diff -Nru linux-3.2.46/debian/changelog linux-3.2.46/debian/changelog --- linux-3.2.46/debian/changelog 2013-06-08 21:36:15.000000000 +0000 +++ linux-3.2.46/debian/changelog 2013-07-26 18:09:43.000000000 +0000 @@ -1,3 +1,21 @@ +linux (3.2.46-1+rpi1) wheezy-staging; urgency=low + + [Vagrant Cascadian ] + * Include patches to support RaspberryPI from: + https://github.com/raspberrypi/linux.git + branch: rpi-3.2.27 + * disable other armhf variants. + * disable other armhf debian-installer variants. + * disable #features/all/rt/0072-hwlatdetect.patch.patch + * attempt to enable debian-installer udebs for rpi. + * try harder to enable debian-installer udebs. + [Peter Michael Green] + * add script to automatically regenerate rpi patches from git repos + * add hack to allow upgrading of kernel located on fat partition to succeed + * backport code to defuzz patches at end of update-rpi-patches + + -- Peter Michael Green Fri, 26 Jul 2013 18:02:53 +0000 + linux (3.2.46-1) wheezy; urgency=low * New upstream stable update: diff -Nru linux-3.2.46/debian/config/armhf/config.rpi linux-3.2.46/debian/config/armhf/config.rpi --- linux-3.2.46/debian/config/armhf/config.rpi 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/config/armhf/config.rpi 2013-07-26 18:03:26.000000000 +0000 @@ -0,0 +1,141 @@ +## +## file: arch/arm/Kconfig +CONFIG_ARCH_BCM2708=y + +# Enable MMC +CONFIG_MMC=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMC_SDHCI_BCM2708=y +CONFIG_MMC_SDHCI_BCM2708_DMA=y +# +# MMC/SD/SDIO Card Drivers +# +CONFIG_MMC_BLOCK=y +CONFIG_MMC_BLOCK_MINORS=8 +CONFIG_MMC_BLOCK_BOUNCE=y + +# +# Boot options +# +CONFIG_CMDLINE_FROM_BOOTLOADER=y + +# +# Non-8250 serial port support +# +# CONFIG_SERIAL_AMBA_PL010 is not set +CONFIG_SERIAL_AMBA_PL011=y +CONFIG_SERIAL_AMBA_PL011_CONSOLE=y + +# Serial Console +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_CONSOLE_POLL=y + +CONFIG_TTY_PRINTK=y + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +CONFIG_I2C_BCM2708=m +CONFIG_I2C_BCM2708_BAUDRATE=100000 + +CONFIG_SPI=y +CONFIG_SPI_MASTER=y + +# +# SPI Master Controller Drivers +# +CONFIG_SPI_BCM2708=m + +# +# SPI Protocol Masters +# +CONFIG_SPI_SPIDEV=m + +# +# Enable Device Drivers -> PPS to see the PTP clock options. +# +CONFIG_ARCH_REQUIRE_GPIOLIB=y +CONFIG_GPIOLIB=y +CONFIG_GPIO_SYSFS=y + +CONFIG_THERMAL=y +CONFIG_THERMAL_BCM2835=y + +CONFIG_WATCHDOG=y + +# +# Watchdog Device Drivers +# +CONFIG_BCM2708_WDT=m + +# +# Audio decoders, processors and mixers +# +CONFIG_VIDEO_MSP3400=m +CONFIG_VIDEO_CS53L32A=m +CONFIG_VIDEO_WM8775=m + +# +# Video decoders +# +CONFIG_VIDEO_SAA711X=m + +# +# Video and audio decoders +# +# CONFIG_VIDEO_SAA717X is not set +CONFIG_VIDEO_CX25840=m + +# +# MPEG video encoders +# +CONFIG_VIDEO_CX2341X=m + +# +# Graphics support +# +CONFIG_FB=y +##CONFIG_FB_CFB_FILLRECT=y +##CONFIG_FB_CFB_COPYAREA=y +##CONFIG_FB_CFB_IMAGEBLIT=y + +# +# Frame buffer hardware drivers +# +CONFIG_FB_BCM2708=y +CONFIG_BACKLIGHT_LCD_SUPPORT=y +CONFIG_LCD_CLASS_DEVICE=m +CONFIG_BACKLIGHT_CLASS_DEVICE=m +CONFIG_BACKLIGHT_GENERIC=m + +# +# Console display driver support +# +CONFIG_DUMMY_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE=y +## CONFIG_FONTS is not set +##CONFIG_FONT_8x8=y +##CONFIG_FONT_8x16=y + +# Sound +CONFIG_SND_BCM2835=m + +# +# File systems +# +CONFIG_EXT4_FS=y +CONFIG_EXT4_USE_FOR_EXT23=y +CONFIG_EXT4_FS_XATTR=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_EXT4_FS_SECURITY=y + +CONFIG_USB=y + +# USB controller for RPI? +CONFIG_USB_DWCOTG=y + +# USB network for RPI? +CONFIG_USB_USBNET=y +CONFIG_USB_NET_SMSC95XX=y diff -Nru linux-3.2.46/debian/config/armhf/defines linux-3.2.46/debian/config/armhf/defines --- linux-3.2.46/debian/config/armhf/defines 2013-02-24 03:53:14.000000000 +0000 +++ linux-3.2.46/debian/config/armhf/defines 2013-07-26 18:03:26.000000000 +0000 @@ -1,8 +1,6 @@ [base] flavours: - mx5 - omap - vexpress + rpi kernel-arch: arm [image] @@ -35,3 +33,11 @@ hardware: ARM Ltd. Versatile Express hardware-long: ARM Ltd. Versatile Express family of processors +[rpi_build] +image-file: arch/arm/boot/zImage + +[rpi_description] +hardware: RaspberryPI +hardware-long: Raspberry PI + + diff -Nru linux-3.2.46/debian/config.defines.dump linux-3.2.46/debian/config.defines.dump --- linux-3.2.46/debian/config.defines.dump 2013-06-08 21:44:19.000000000 +0000 +++ linux-3.2.46/debian/config.defines.dump 2013-07-26 21:15:04.000000000 +0000 @@ -27,793 +27,799 @@ p14 aS'lilo' p15 -ass(S'base' -S'hppa' +ass(S'description' +S'i386' p16 -NS'parisc64' +NS'686-pae' tp17 (dp18 -S'override-host-type' +S'hardware' p19 -S'hppa64-linux-gnu' +S'modern PCs' p20 -sS'cflags' +sS'parts' p21 -S'-fno-cse-follow-jumps' -p22 +(lp22 +S'pae' +p23 +asS'hardware-long' +p24 +S'PCs with one or more processors supporting PAE' +p25 ss(S'base' g5 S'none' -p23 -tp24 -(dp25 -S'flavours' p26 -(lp27 +tp27 +(dp28 +S'flavours' +p29 +(lp30 S'amd64' -p28 +p31 ass(S'description' S'm68k' -p29 -NS'mac' -tp30 -(dp31 -S'hardware' p32 -S'Macintosh' -p33 +NS'amiga' +tp33 +(dp34 +S'hardware' +p35 +S'Amiga' +p36 ss(S'image' -S's390x' -p34 -NS's390x-tape' -tp35 -(dp36 -S'configs' +S'ia64' p37 -(lp38 -S's390/config.s390x-tape' -p39 -asS'override-localversion' +tp38 +(dp39 +S'suggests' p40 -S's390x' +S'fdutils' p41 -sS'type' +sS'bootloaders' p42 -S'plain-s390-tape' -p43 -sS'initramfs' +(lp43 +S'elilo' p44 -I00 -ss(S'build' -S'sh4' +ass(S'description' +S's390' p45 -NS'sh7785lcr' +NS's390x' tp46 (dp47 -S'image-file' +S'hardware' p48 -S'arch/sh/boot/zImage' +S'IBM zSeries' p49 -ss(S'image' -S'ia64' +sS'parts' p50 -tp51 -(dp52 -S'suggests' +(lp51 +S'reader' +p52 +ass(S'build' +S'armhf' p53 -S'fdutils' -p54 -sS'bootloaders' -p55 -(lp56 -S'elilo' +NS'rpi' +tp54 +(dp55 +S'image-file' +p56 +S'arch/arm/boot/zImage' p57 -ass(S'xen' -S'i386' -p58 +ss(S'xen' +g16 S'none' -p59 +p58 S'amd64' -tp60 -(dp61 +tp59 +(dp60 S'flavours' -p62 -(lp63 +p61 +(lp62 S'amd64' -p64 +p63 asS'dom0-support' -p65 +p64 I01 ss(S'image' -S'mipsel' -p66 -NS'4kc-malta' -tp67 -(dp68 +S'ppc64' +p65 +NS'powerpc64' +tp66 +(dp67 S'configs' -p69 -(lp70 -S'mips/config.4kc-malta' +p68 +(lp69 +S'powerpc/config.powerpc64' +p70 +ass(S'version' p71 -ass(S'description' -g5 -g23 -S'amd64' tp72 (dp73 -S'parts' +S'abiname' p74 -(lp75 -S'xen' +S'3.2.0-4' +p75 +sS'source' p76 -ass(S'description' -g58 -NS'486' -tp77 -(dp78 -S'hardware' -p79 -S'older PCs' -p80 -sS'parts' +V3.2.46-1+rpi1 +p77 +ss(S'build' +S'armel' +p78 +NS'kirkwood' +tp79 +(dp80 +S'image-file' p81 -(lp82 -S'up' -p83 -asS'hardware-long' -p84 -S'PCs with a single processor not supporting PAE' -p85 -ss(S'description' -g29 -NS'bvme6000' -tp86 -(dp87 -S'hardware' -p88 -S'BVM BVME4000 and BVME6000' -p89 +S'arch/arm/boot/zImage' +p82 ss(S'description' -g34 +g5 +g26 +S'amd64' +tp83 +(dp84 +S'parts' +p85 +(lp86 +S'xen' +p87 +ass(S'build' +g45 NS's390x-tape' -tp90 -(dp91 -S'hardware' +tp88 +(dp89 +S'modules' +p90 +I00 +ss(S'base' +p91 +g65 +S'none' p92 -S'IBM zSeries' -p93 -sS'parts' -p94 -(lp95 -S'tape' +tp93 +(dp94 +S'implicit-flavour' +p95 +I01 +sS'flavours' p96 -ass(S'base' -NS'rt' -tp97 -(dp98 -S'enabled' +(lp97 +S'powerpc64' +p98 +ass(S'image' +S'sh4' p99 -I01 -ss(S'description' -S'powerpc' -p100 -NS'powerpc-smp' -tp101 -(dp102 -S'hardware' +NS'sh7785lcr' +tp100 +(dp101 +S'check-size' +p102 +S'4194304' p103 -S'multiprocessor 32-bit PowerPC' +sS'recommends' p104 +S'uboot-mkimage' +p105 ss(S'description' -g58 -g59 -S'amd64' -tp105 -(dp106 -S'parts' -p107 -(lp108 -S'xen' -p109 -ass(S'description' -g45 -NS'sh7785lcr' -tp110 -(dp111 +S'mips' +p106 +NS'octeon' +tp107 +(dp108 S'hardware' -p112 -S'sh7785lcr' -p113 +p109 +S'Octeon' +p110 sS'hardware-long' -p114 -S'Renesas SH7785 reference board' -p115 +p111 +S'Cavium Networks Octeon' +p112 ss(S'base' S'alpha' -p116 -tp117 -(dp118 +p113 +tp114 +(dp115 S'kernel-arch' -p119 +p116 S'alpha' -p120 +p117 sS'featuresets' -p121 -(lp122 -S'none' +p118 +(lp119 +g92 +ass(S'image' +g78 +NS'ixp4xx' +tp120 +(dp121 +S'check-size' +p122 +S'1441760' p123 -ass(S'description' -S'armel' -p124 -NS'mv78xx0' -tp125 -(dp126 -S'hardware' +ss(S'image' +g45 +NS's390-tape' +tp124 +(dp125 +S'override-localversion' +p126 +S's390' p127 -S'Marvell 78xx0' +sS'type' p128 -sS'hardware-long' +S'plain-s390-tape' p129 -S'Marvell DB-78xx0-BP Development Board' +sS'initramfs' p130 -ss(S'description' -g29 -NS'amiga' +I00 +ss(g91 +g53 +g92 tp131 (dp132 -S'hardware' -p133 -S'Amiga' +g95 +I01 +sg96 +(lp133 +S'rpi' p134 -ss(S'build' -g5 +ass(S'base' +g53 tp135 (dp136 -S'debug-info' +S'kernel-arch' p137 -I01 -ss(S'base' -g58 -S'rt' -tp138 -(dp139 -S'flavours' +S'arm' +p138 +sg118 +(lp139 +g92 +ass(S'description' +S'sparc' p140 -(lp141 -S'686-pae' -p142 -ass(S'base' +NS'sparc64' +tp141 +(dp142 +S'hardware' p143 -g29 -g123 -tp144 -(dp145 -S'implicit-flavour' -p146 -I01 -sS'flavours' +S'uniprocessor 64-bit UltraSPARC' +p144 +ss(S'description' +g37 +NS'itanium' +tp145 +(dp146 +S'hardware' p147 -(lp148 -S'amiga' -p149 -aS'atari' -p150 -aS'bvme6000' +S'Itanium' +p148 +ss(S'base' +g16 +S'rt' +tp149 +(dp150 +S'flavours' p151 -aS'mac' -p152 -aS'mvme147' +(lp152 +S'686-pae' p153 -aS'mvme16x' -p154 -ass(S'description' -g29 -NS'mvme147' -tp155 -(dp156 -S'hardware' +ass(S'build' +g78 +NS'iop32x' +tp154 +(dp155 +S'image-file' +p156 +S'arch/arm/boot/zImage' p157 -S'Motorola MVME147' -p158 -ss(g143 -g100 -g123 -tp159 -(dp160 -g146 -I01 -sg147 -(lp161 -S'powerpc' -p162 -aS'powerpc-smp' -p163 -aS'powerpc64' -p164 -ass(S'image' -g66 -NS'loongson-2f' -tp165 -(dp166 -S'recommends' -p167 -S'libc6-loongson2f' -p168 ss(S'description' -S'mips' -p169 -NS'sb1-bcm91250a' -tp170 -(dp171 +g37 +NS'mckinley' +tp158 +(dp159 S'hardware' -p172 -S'BCM91250A' -p173 -sS'hardware-long' -p174 -S'Broadcom BCM91250A systems (aka SWARM)' -p175 -ss(S'image' -g124 -NS'orion5x' -tp176 -(dp177 -S'check-size' -p178 -S'1572792' -p179 -sS'recommends' -p180 -S'uboot-mkimage' -p181 +p160 +S'Itanium II' +p161 +ss(S'build' +g53 +NS'mx5' +tp162 +(dp163 +S'image-file' +p164 +S'arch/arm/boot/zImage' +p165 +ss(S'image' +S'powerpc' +p166 +tp167 +(dp168 +S'suggests' +p169 +S'mkvmlinuz' +p170 +ss(S'description' +g106 +NS'4kc-malta' +tp171 +(dp172 +S'hardware' +p173 +S'MIPS Malta' +p174 +sS'hardware-long' +p175 +S'MIPS Malta boards' +p176 ss(S'base' g5 S'rt' +tp177 +(dp178 +S'flavours' +p179 +(lp180 +S'amd64' +p181 +ass(S'description' +g78 +NS'iop32x' tp182 (dp183 -S'flavours' +S'hardware' p184 -(lp185 -S'amd64' +S'IOP32x' +p185 +sS'hardware-long' p186 -ass(S'description' -S'armhf' +S'IOP32x based systems (Thecus N2100, etc)' p187 -NS'omap' +ss(S'description' +g16 +g58 +S'amd64' tp188 (dp189 -S'hardware' +S'parts' p190 -S'TI OMAP3+' -p191 -sS'hardware-long' +(lp191 +S'xen' p192 -S'Texas Instruments OMAP3 or OMAP4 based systems' -p193 -ss(S'build' -g187 -NS'vexpress' -tp194 -(dp195 -S'image-file' +ass(S'description' +g166 +NS'powerpc-smp' +tp193 +(dp194 +S'hardware' +p195 +S'multiprocessor 32-bit PowerPC' p196 -S'arch/arm/boot/zImage' -p197 ss(S'base' -g58 -tp198 -(dp199 +g16 +tp197 +(dp198 S'kernel-arch' -p200 +p199 S'x86' -p201 +p200 sS'featuresets' -p202 -(lp203 +p201 +(lp202 S'none' -p204 +p203 aS'rt' -p205 +p204 ass(S'base' -g66 +S'mipsel' +p205 tp206 (dp207 S'kernel-arch' p208 S'mips' p209 -sg121 +sg118 (lp210 -g123 +g92 ass(S'description' -S'sparc64' -p211 -NS'sparc64' -tp212 -(dp213 +g140 +NS'sparc32' +tp211 +(dp212 S'hardware' +p213 +S'uniprocessor sparc32 (sun4m)' p214 -S'uniprocessor 64-bit UltraSPARC' +ss(S'image' +S's390x' p215 -ss(S'build' -g187 -NS'omap' +NS's390x-tape' tp216 (dp217 -S'image-file' +S'configs' p218 -S'arch/arm/boot/zImage' -p219 -ss(S'description' -g124 -NS'iop32x' -tp220 -(dp221 -S'hardware' +(lp219 +S's390/config.s390x-tape' +p220 +asS'override-localversion' +p221 +S's390x' p222 -S'IOP32x' +sS'type' p223 -sS'hardware-long' +S'plain-s390-tape' p224 -S'IOP32x based systems (Thecus N2100, etc)' +sS'initramfs' p225 +I00 ss(S'description' -g187 -NS'vexpress' +g205 +NS'4kc-malta' tp226 (dp227 S'hardware' p228 -S'ARM Ltd. Versatile Express' +S'MIPS Malta' p229 sS'hardware-long' p230 -S'ARM Ltd. Versatile Express family of processors' +S'MIPS Malta boards' p231 -ss(S'description' -g124 -NS'ixp4xx' +ss(g91 +g205 +g92 tp232 (dp233 -S'hardware' -p234 -S'IXP4xx' -p235 -sS'hardware-long' -p236 -S'IXP4xx based systems (Linksys NSLU2, etc)' -p237 -ss(g143 -g66 -g123 -tp238 -(dp239 -g146 +g95 I01 -sg147 -(lp240 +sg96 +(lp234 S'r5k-cobalt' -p241 +p235 aS'sb1-bcm91250a' -p242 +p236 aS'sb1a-bcm91480b' -p243 +p237 aS'4kc-malta' -p244 +p238 aS'5kc-malta' -p245 +p239 aS'loongson-2f' -p246 -ass(S'image' -S's390' -p247 -NS's390x-tape' -tp248 -(dp249 -S'override-localversion' -p250 -S's390x' -p251 -sS'type' -p252 -S'plain-s390-tape' -p253 -sS'initramfs' -p254 -I00 +p240 +ass(S'description' +g65 +NS'powerpc64' +tp241 +(dp242 +S'hardware' +p243 +S'64-bit PowerPC' +p244 ss(S'relations' -tp255 -(dp256 +tp245 +(dp246 S'initramfs-fallback' -p257 +p247 S'linux-initramfs-tool' -p258 +p248 sS'gcc-4.5' -p259 +p249 S'gcc-4.5' -p260 +p250 sS'gcc-4.6' -p261 +p251 S'gcc-4.6' -p262 +p252 sS'initramfs-tools' -p263 +p253 S'initramfs-tools (>= 0.99~)' -p264 +p254 sS'gcc-4.4' -p265 +p255 S'gcc-4.4' +p256 +ss(S'description' +g205 +NS'sb1a-bcm91480b' +tp257 +(dp258 +S'hardware' +p259 +S'BCM91480B' +p260 +sS'hardware-long' +p261 +S'Broadcom BCM91480B systems (aka BigSur)' +p262 +ss(S'image' +g78 +NS'orion5x' +tp263 +(dp264 +S'check-size' +p265 +S'1572792' p266 +sS'recommends' +p267 +S'uboot-mkimage' +p268 ss(S'description' -g247 -NS's390x' -tp267 -(dp268 +g78 +NS'mv78xx0' +tp269 +(dp270 S'hardware' -p269 -S'IBM zSeries' -p270 -sS'parts' p271 -(lp272 -S'reader' +S'Marvell 78xx0' +p272 +sS'hardware-long' p273 -ass(S'image' -g58 -NS'686-pae' -tp274 -(dp275 -S'configs' -p276 -(lp277 -S'kernelarch-x86/config-arch-32' +S'Marvell DB-78xx0-BP Development Board' +p274 +ss(S'description' +g78 +NS'ixp4xx' +tp275 +(dp276 +S'hardware' +p277 +S'IXP4xx' p278 -asS'recommends' +sS'hardware-long' p279 -S'libc6-i686' +S'IXP4xx based systems (Linksys NSLU2, etc)' p280 ss(S'description' -g5 -NS'amd64' +g53 +NS'omap' tp281 (dp282 S'hardware' p283 -S'64-bit PCs' +S'TI OMAP3+' p284 sS'hardware-long' p285 -S'PCs with AMD64, Intel 64 or VIA Nano processors' +S'Texas Instruments OMAP3 or OMAP4 based systems' p286 -ss(g143 -g45 -g123 +ss(g91 +g99 +g92 tp287 (dp288 -g146 +g95 I01 -sg147 +sg96 (lp289 S'sh7751r' p290 aS'sh7785lcr' p291 ass(S'description' -g247 -NS's390-tape' +g78 +NS'versatile' tp292 (dp293 S'hardware' p294 -S'IBM S/390' +S'Versatile' p295 -sS'parts' +sS'hardware-long' p296 -(lp297 -S'tape' -p298 -ass(S'xen' -g58 -g59 -S'686-pae' -tp299 -(dp300 -S'flavours' +S'Versatile systems (PB, AB, Qemu)' +p297 +ss(S'description' +g32 +NS'bvme6000' +tp298 +(dp299 +S'hardware' +p300 +S'BVM BVME4000 and BVME6000' p301 -(lp302 -S'i386' -p303 -aS'amd64' +ss(S'description' +g140 +NS'sparc64-smp' +tp302 +(dp303 +S'hardware' p304 -asS'dom0-support' +S'multiprocessor 64-bit UltraSPARC' p305 -I01 ss(S'description' -S'ppc64' +S'sparc64' p306 -NS'powerpc64' +NS'sparc64-smp' tp307 (dp308 S'hardware' p309 -S'64-bit PowerPC' +S'multiprocessor 64-bit UltraSPARC' p310 ss(S'base' -g124 +g78 tp311 (dp312 S'kernel-arch' p313 S'arm' p314 -sg121 +sg118 (lp315 -g123 -ass(S'image' -g187 -NS'omap' +g92 +ass(S'build' +g99 +NS'sh7751r' tp316 (dp317 -S'recommends' +S'image-file' p318 -S'uboot-mkimage' +S'arch/sh/boot/zImage' p319 -ss(S'description' -g66 -NS'5kc-malta' +ss(S'base' +g140 tp320 (dp321 -S'hardware' +S'kernel-arch' p322 -S'MIPS Malta (64-bit)' +S'sparc' p323 +sg118 +(lp324 +g92 +ass(S'description' +g53 +NS'rpi' +tp325 +(dp326 +S'hardware' +p327 +S'RaspberryPI' +p328 sS'hardware-long' -p324 -S'MIPS Malta boards (64-bit)' -p325 -ss(S'base' -S'sparc' -p326 -tp327 -(dp328 -S'kernel-arch' p329 -S'sparc' +S'Raspberry PI' p330 -sg121 -(lp331 -g123 -ass(S'image' -g66 -NS'5kc-malta' -tp332 -(dp333 +ss(S'image' +g215 +NS's390x' +tp331 +(dp332 S'configs' -p334 -(lp335 -S'mips/config.5kc-malta' -p336 +p333 +(lp334 +S's390/config.s390x' +p335 ass(S'description' -g34 -NS's390x' -tp337 -(dp338 +g99 +NS'sh7751r' +tp336 +(dp337 S'hardware' +p338 +S'sh7751r' p339 -S'IBM zSeries' +sS'hardware-long' p340 -sS'parts' +S'Renesas SH7751R R2D plus board' p341 -(lp342 -S'reader' -p343 -ass(S'description' -g169 -NS'r5k-ip32' -tp344 -(dp345 -S'hardware' -p346 -S'SGI IP32' -p347 -sS'hardware-long' -p348 -S'SGI IP32 systems (O2)' -p349 -ss(S'description' -g211 -NS'sparc64-smp' -tp350 -(dp351 -S'hardware' -p352 -S'multiprocessor 64-bit UltraSPARC' -p353 -ss(g143 -g247 -g123 -tp354 -(dp355 -g146 +ss(S'image' +g205 +NS'loongson-2f' +tp342 +(dp343 +S'recommends' +p344 +S'libc6-loongson2f' +p345 +ss(g91 +g45 +g92 +tp346 +(dp347 +g95 I01 -sg147 -(lp356 +sg96 +(lp348 S's390x' -p357 +p349 aS's390x-tape' -p358 -ass(S'description' -g326 -NS'sparc64-smp' -tp359 -(dp360 -S'hardware' -p361 -S'multiprocessor 64-bit UltraSPARC' -p362 -ss(g143 -g34 -g123 -tp363 -(dp364 -g146 +p350 +ass(g91 +g215 +g92 +tp351 +(dp352 +g95 I01 -sg147 -(lp365 +sg96 +(lp353 S's390x' -p366 +p354 aS's390x-tape' -p367 +p355 ass(S'base' -g169 -tp368 -(dp369 +g106 +tp356 +(dp357 S'kernel-arch' -p370 +p358 S'mips' -p371 -sg121 -(lp372 -g123 -ass(S'description' -g169 -NS'sb1a-bcm91480b' -tp373 -(dp374 +p359 +sg118 +(lp360 +g92 +ass(S'build' +g215 +NS's390x-tape' +tp361 +(dp362 +S'modules' +p363 +I00 +ss(S'build' +g5 +tp364 +(dp365 +S'debug-info' +p366 +I01 +ss(S'description' +g32 +NS'mvme147' +tp367 +(dp368 S'hardware' +p369 +S'Motorola MVME147' +p370 +ss(S'image' +g205 +tp371 +(dp372 +S'configs' +p373 +(lp374 +S'kernelarch-mips/config' p375 -S'BCM91480B' +aS'mipsel/config' p376 -sS'hardware-long' +asS'initramfs' p377 -S'Broadcom BCM91480B systems (aka BigSur)' -p378 -ss(S'build' -g124 -NS'iop32x' -tp379 -(dp380 -S'image-file' -p381 -S'arch/arm/boot/zImage' -p382 +I00 ss(S'image' -g66 +g205 +NS'sb1-bcm91250a' +tp378 +(dp379 +S'configs' +p380 +(lp381 +S'mips/config.sb1-bcm91250a' +p382 +ass(S'xen' +g16 +g58 +S'686-pae' tp383 (dp384 -S'configs' +S'flavours' p385 (lp386 -S'kernelarch-mips/config' +S'i386' p387 -aS'mipsel/config' +aS'amd64' p388 -asS'initramfs' +asS'dom0-support' p389 -I00 +I01 ss(S'description' -g247 -NS's390x-tape' +g215 +NS's390x' tp390 (dp391 S'hardware' @@ -823,278 +829,274 @@ sS'parts' p394 (lp395 -S'tape' +S'reader' p396 -ass(S'build' -g124 -NS'ixp4xx' +ass(S'description' +g78 +NS'orion5x' tp397 (dp398 -S'image-file' +S'hardware' p399 -S'arch/arm/boot/zImage' +S'Marvell Orion' p400 +sS'hardware-long' +p401 +S'Marvell Orion 5181, 5182 and 5281 based systems (QNAP TS-109/TS-209, etc)' +p402 ss(S'image' -g58 -NS'486' -tp401 -(dp402 -S'configs' -p403 -(lp404 -S'kernelarch-x86/config-arch-32' +g78 +NS'iop32x' +tp403 +(dp404 +S'check-size' p405 -ass(S'image' -g66 -NS'sb1a-bcm91480b' -tp406 -(dp407 -S'configs' -p408 -(lp409 -S'mips/config.sb1a-bcm91480b' -p410 -ass(S'base' +S'1441784' +p406 +ss(S'base' g5 -tp411 -(dp412 +tp407 +(dp408 S'kernel-arch' -p413 +p409 S'x86' -p414 +p410 sS'featuresets' -p415 -(lp416 +p411 +(lp412 S'none' -p417 +p413 aS'rt' +p414 +ass(S'description' +g166 +NS'powerpc' +tp415 +(dp416 +S'hardware' +p417 +S'uniprocessor 32-bit PowerPC' p418 -ass(S'base' -g50 +ss(S'image' tp419 (dp420 -S'kernel-arch' +S'initramfs-generators' p421 -S'ia64' -p422 -sg121 -(lp423 -g123 -ass(S'description' +(lp422 +S'initramfs-tools' +p423 +aS'initramfs-fallback' +p424 +asS'type' +p425 +S'plain' +p426 +ss(S'description' g16 -NS'parisc' -tp424 -(dp425 +NS'amd64' +tp427 +(dp428 S'hardware' -p426 -S'32-bit PA-RISC' -p427 -ss(g143 -g306 -g123 -tp428 -(dp429 -g146 -I01 -sg147 -(lp430 -S'powerpc64' +p429 +S'64-bit PCs' +p430 +sS'hardware-long' p431 -ass(S'base' -g247 -tp432 -(dp433 -S'kernel-arch' -p434 -S's390' +S'PCs with AMD64, Intel 64 or VIA Nano processors' +p432 +ss(S'build' +g78 +NS'orion5x' +tp433 +(dp434 +S'image-file' p435 -sg121 -(lp436 -g123 -ass(S'image' -g124 -NS'iop32x' +S'arch/arm/boot/zImage' +p436 +ss(S'image' +g53 +NS'omap' tp437 (dp438 -S'check-size' +S'recommends' p439 -S'1441784' +S'uboot-mkimage' p440 -ss(S'description' -g16 -NS'parisc-smp' +ss(g91 +g78 +g92 tp441 (dp442 -S'hardware' -p443 -S'multiprocessor 32-bit PA-RISC' +g95 +I01 +sg96 +(lp443 +S'iop32x' p444 -ss(S'description' -g116 -NS'alpha-generic' -tp445 -(dp446 -S'hardware' +aS'ixp4xx' +p445 +aS'kirkwood' +p446 +aS'mv78xx0' p447 -S'Alpha' +aS'orion5x' p448 -sS'hardware-long' +aS'versatile' p449 -S'DEC Alpha systems with extended kernel start address (Wildfire, Titan, Marvel)' -p450 -ss(S'description' -g16 -NS'parisc64' -tp451 -(dp452 -S'hardware' +ass(S'base' +g37 +tp450 +(dp451 +S'kernel-arch' +p452 +S'ia64' p453 -S'64-bit PA-RISC' -p454 -ss(S'image' -g124 -NS'ixp4xx' -tp455 -(dp456 -S'check-size' -p457 -S'1441760' +sg118 +(lp454 +g92 +ass(S'description' +S'hppa' +p455 +NS'parisc64-smp' +tp456 +(dp457 +S'hardware' p458 -ss(S'build' -g45 -NS'sh7751r' -tp459 -(dp460 -S'image-file' -p461 -S'arch/sh/boot/zImage' +S'multiprocessor 64-bit PA-RISC' +p459 +ss(S'base' +g455 +NS'parisc64' +tp460 +(dp461 +S'override-host-type' p462 +S'hppa64-linux-gnu' +p463 +sS'cflags' +p464 +S'-fno-cse-follow-jumps' +p465 ss(S'description' -g58 -tp463 -(dp464 +g16 +tp466 +(dp467 S'part-long-pae' -p465 +p468 S'This kernel requires PAE (Physical Address Extension).\nThis feature is supported by the Intel Pentium Pro/II/III/4/4M/D, Xeon,\nCore and Atom; AMD Geode NX, Athlon (K7), Duron, Opteron, Sempron,\nTurion or Phenom; Transmeta Efficeon; VIA C7; and some other processors.' -p466 -ss(S'description' -g58 -NS'amd64' -tp467 -(dp468 -S'hardware' p469 -S'64-bit PCs' -p470 -sS'hardware-long' -p471 -S'PCs with AMD64, Intel 64 or VIA Nano processors' +ss(S'base' +g16 +g58 +tp470 +(dp471 +S'flavours' p472 -ss(S'image' -g187 -tp473 -(dp474 -S'suggests' +(lp473 +S'486' +p474 +aS'686-pae' p475 -S'fdutils' +aS'amd64' p476 -sS'configs' -p477 -(lp478 -S'armel/config' -p479 -aS'armhf/config' -p480 ass(S'xen' g5 -g23 +g26 S'amd64' -tp481 -(dp482 +tp477 +(dp478 S'flavours' -p483 -(lp484 +p479 +(lp480 S'amd64' -p485 +p481 asS'dom0-support' -p486 +p482 +I01 +ss(S'build' +g215 +NS's390x' +tp483 +(dp484 +S'debug-info' +p485 I01 ss(S'image' -g124 -tp487 -(dp488 +g78 +tp486 +(dp487 S'suggests' -p489 +p488 S'fdutils' -p490 +p489 ss(S'image' -g247 -tp491 -(dp492 +g45 +tp490 +(dp491 S'bootloaders' -p493 -(lp494 +p492 +(lp493 S's390-tools' -p495 +p494 ass(S'abi' -g34 -tp496 -(dp497 +g215 +tp495 +(dp496 S'ignore-changes' -p498 -(lp499 +p497 +(lp498 S'arch_pick_mmap_layout' -p500 +p499 ass(S'abi' g5 -tp501 -(dp502 +tp500 +(dp501 S'ignore-changes' -p503 -(lp504 +p502 +(lp503 S'module:arch/x86/kvm/kvm' -p505 +p504 ass(S'image' -g16 -tp506 -(dp507 +g455 +tp505 +(dp506 S'suggests' -p508 +p507 S'palo' -p509 +p508 ss(S'abi' -g169 -tp510 -(dp511 +g106 +tp509 +(dp510 S'ignore-changes' -p512 -(lp513 +p511 +(lp512 S'vgacon_*' -p514 -ass(S'image' -g326 -NS'sparc32' -tp515 -(dp516 -S'image-postproc' +p513 +ass(S'relations' +g455 +tp514 +(dp515 +S'gcc-4.4' +p516 +S'gcc-4.4, binutils-hppa64, gcc-4.4-hppa64' p517 -S'sparc32-image-postproc' -p518 ss(S'description' -g116 -NS'alpha-smp' -tp519 -(dp520 +g215 +NS's390x-tape' +tp518 +(dp519 S'hardware' +p520 +S'IBM zSeries' p521 -S'Alpha SMP' +sS'parts' p522 -sS'hardware-long' -p523 -S'DEC Alpha SMP systems with extended kernel start address (Wildfire, Titan, Marvel)' +(lp523 +S'tape' p524 -ss(S'abi' -g247 +ass(S'abi' +g45 tp525 (dp526 S'ignore-changes' @@ -1102,1169 +1104,1185 @@ (lp528 S'arch_pick_mmap_layout' p529 -ass(S'description' -g326 -NS'sparc64' +ass(S'image' +g306 +NS'sparc64-smp' tp530 (dp531 -S'hardware' +S'configs' p532 -S'uniprocessor 64-bit UltraSPARC' -p533 -ss(S'build' -g247 -NS's390-tape' -tp534 -(dp535 -S'modules' -p536 -I00 -ss(S'description' -g169 -NS'4kc-malta' -tp537 -(dp538 -S'hardware' -p539 -S'MIPS Malta' -p540 -sS'hardware-long' -p541 -S'MIPS Malta boards' -p542 -ss(g143 -g16 -g123 -tp543 -(dp544 -g146 +(lp533 +S'sparc/config.sparc64-smp' +p534 +ass(S'base' +NS'rt' +tp535 +(dp536 +S'enabled' +p537 +I01 +ss(g91 +g455 +g92 +tp538 +(dp539 +g95 I01 -sg147 -(lp545 +sg96 +(lp540 S'parisc' -p546 +p541 aS'parisc-smp' -p547 +p542 aS'parisc64' -p548 +p543 aS'parisc64-smp' -p549 +p544 ass(S'image' -g211 -NS'sparc64-smp' -tp550 -(dp551 -S'configs' +g113 +tp545 +(dp546 +S'suggests' +p547 +S'aboot, fdutils' +p548 +ss(S'description' +g205 +NS'r5k-cobalt' +tp549 +(dp550 +S'hardware' +p551 +S'Cobalt' p552 -(lp553 -S'sparc/config.sparc64-smp' +sS'hardware-long' +p553 +S'Cobalt systems (Qube, RaQ, Qube2, RaQ2)' p554 -ass(S'image' -g116 +ss(S'base' +g306 tp555 (dp556 -S'suggests' -p557 -S'aboot, fdutils' -p558 -ss(S'base' -g211 -tp559 -(dp560 S'kernel-arch' -p561 +p557 S'sparc' +p558 +sg118 +(lp559 +g92 +ass(S'image' +g16 +tp560 +(dp561 +S'configs' p562 -sg121 (lp563 -g123 -ass(S'version' +S'kernelarch-x86/config' p564 -tp565 -(dp566 -S'abiname' +asS'bootloaders' +p565 +(lp566 +S'grub-pc' p567 -S'3.2.0-4' +aS'extlinux' p568 -sS'source' +aS'lilo' p569 -V3.2.46-1 -p570 -ss(S'base' -g34 -tp571 -(dp572 -S'kernel-arch' -p573 -S's390' +ass(S'image' +g205 +NS'4kc-malta' +tp570 +(dp571 +S'configs' +p572 +(lp573 +S'mips/config.4kc-malta' p574 -sg121 -(lp575 -g123 -ass(S'base' -g16 -NS'parisc64-smp' -tp576 -(dp577 -S'override-host-type' +ass(S'description' +g99 +NS'sh7785lcr' +tp575 +(dp576 +S'hardware' +p577 +S'sh7785lcr' p578 -S'hppa64-linux-gnu' +sS'hardware-long' p579 -sS'cflags' +S'Renesas SH7785 reference board' p580 -S'-fno-cse-follow-jumps' -p581 -ss(S'image' -g247 -NS's390-tape' -tp582 -(dp583 -S'override-localversion' -p584 +ss(S'base' +g215 +tp581 +(dp582 +S'kernel-arch' +p583 S's390' -p585 -sS'type' -p586 -S'plain-s390-tape' -p587 -sS'initramfs' +p584 +sg118 +(lp585 +g92 +ass(S'description' +g106 +NS'5kc-malta' +tp586 +(dp587 +S'hardware' p588 -I00 -ss(S'abi' -NS'rt' +S'MIPS Malta (64-bit)' p589 -tp590 -(dp591 -S'ignore-changes' -p592 -(lp593 -S'*' -ass(S'image' -g100 -NS'powerpc-smp' -tp594 -(dp595 -S'configs' +sS'hardware-long' +p590 +S'MIPS Malta boards (64-bit)' +p591 +ss(S'description' +g106 +NS'r5k-ip32' +tp592 +(dp593 +S'hardware' +p594 +S'SGI IP32' +p595 +sS'hardware-long' p596 -(lp597 -S'powerpc/config.powerpc' -p598 -aS'powerpc/config.powerpc-smp' -p599 -ass(g143 -g124 -g123 -tp600 -(dp601 -g146 -I01 -sg147 -(lp602 -S'iop32x' -p603 -aS'ixp4xx' -p604 -aS'kirkwood' -p605 -aS'mv78xx0' -p606 -aS'orion5x' -p607 -aS'versatile' -p608 -ass(S'image' -g306 -tp609 -(dp610 +S'SGI IP32 systems (O2)' +p597 +ss(S'image' +g65 +tp598 +(dp599 S'suggests' -p611 +p600 S'mkvmlinuz' -p612 +p601 sS'configs' -p613 -(lp614 +p602 +(lp603 S'powerpc/config' -p615 +p604 ass(S'image' -g169 -tp616 -(dp617 +g106 +tp605 +(dp606 S'configs' -p618 -(lp619 +p607 +(lp608 S'kernelarch-mips/config' -p620 +p609 aS'mips/config' -p621 +p610 asS'initramfs' -p622 +p611 I00 ss(S'image' -g58 -tp623 -(dp624 -S'configs' -p625 -(lp626 -S'kernelarch-x86/config' -p627 -asS'bootloaders' -p628 -(lp629 -S'grub-pc' -p630 -aS'extlinux' -p631 -aS'lilo' -p632 -ass(g143 -g326 -g123 -tp633 -(dp634 -g146 +g78 +NS'kirkwood' +tp612 +(dp613 +S'check-size' +p614 +S'2097080' +p615 +sS'recommends' +p616 +S'uboot-mkimage' +p617 +ss(g91 +g140 +g92 +tp618 +(dp619 +g95 I01 -sg147 -(lp635 +sg96 +(lp620 S'sparc64' -p636 +p621 aS'sparc64-smp' -p637 +p622 ass(S'base' -g306 -tp638 -(dp639 +g65 +tp623 +(dp624 S'kernel-arch' -p640 +p625 S'powerpc' -p641 -sg121 -(lp642 -g123 -ass(g143 -g116 -g123 -tp643 -(dp644 -g146 +p626 +sg118 +(lp627 +g92 +ass(g91 +g113 +g92 +tp628 +(dp629 +g95 I01 -sg147 -(lp645 +sg96 +(lp630 S'alpha-generic' -p646 +p631 aS'alpha-smp' -p647 +p632 aS'alpha-legacy' -p648 +p633 ass(S'description' -g169 -NS'r4k-ip22' -tp649 -(dp650 -S'hardware' -p651 -S'SGI IP22' -p652 -sS'hardware-long' -p653 -S'SGI IP22 systems (Indy, Indigo2)' -p654 -ss(S'image' -g45 -NS'sh7785lcr' -tp655 -(dp656 -S'check-size' -p657 -S'4194304' -p658 -sS'recommends' -p659 -S'uboot-mkimage' -p660 -ss(g143 -g50 -g123 -tp661 -(dp662 -g146 +g16 +g58 +S'686-pae' +tp634 +(dp635 +S'parts' +p636 +(lp637 +S'xen' +p638 +ass(g91 +g37 +g92 +tp639 +(dp640 +g95 I01 -sg147 -(lp663 +sg96 +(lp641 S'itanium' -p664 +p642 aS'mckinley' -p665 +p643 ass(S'description' -g247 -tp666 -(dp667 +g45 +tp644 +(dp645 S'part-short-tape' -p668 +p646 S'IPL from tape' -p669 +p647 sS'part-long-tape' -p670 +p648 S'This kernel has support to IPL (boot) from a tape.' -p671 +p649 sS'part-long-reader' -p672 +p650 S'This kernel has support to IPL (boot) from a VM reader or DASD device.' -p673 -ss(S'build' -g187 -NS'mx5' -tp674 -(dp675 -S'image-file' -p676 -S'arch/arm/boot/zImage' -p677 -ss(S'image' -g124 -NS'kirkwood' -tp678 -(dp679 -S'check-size' -p680 -S'2097080' -p681 -sS'recommends' -p682 -S'uboot-mkimage' -p683 -ss(g143 -g169 -g123 -tp684 -(dp685 -g146 +p651 +ss(g91 +g106 +g92 +tp652 +(dp653 +g95 I01 -sg147 -(lp686 +sg96 +(lp654 S'r4k-ip22' -p687 +p655 aS'r5k-ip32' -p688 +p656 aS'sb1-bcm91250a' -p689 +p657 aS'sb1a-bcm91480b' -p690 +p658 aS'4kc-malta' -p691 +p659 aS'5kc-malta' -p692 +p660 aS'octeon' -p693 +p661 +ass(S'image' +g306 +NS'sparc64' +tp662 +(dp663 +S'configs' +p664 +(lp665 +S'sparc/config.sparc64' +p666 ass(S'description' -g100 -NS'powerpc' -tp694 -(dp695 +g166 +NS'powerpc64' +tp667 +(dp668 +S'hardware' +p669 +S'64-bit PowerPC' +p670 +ss(S'image' +g32 +tp671 +(dp672 +S'suggests' +p673 +S'vmelilo, fdutils' +p674 +sS'initramfs' +p675 +I00 +ss(S'description' +g106 +NS'r4k-ip22' +tp676 +(dp677 +S'hardware' +p678 +S'SGI IP22' +p679 +sS'hardware-long' +p680 +S'SGI IP22 systems (Indy, Indigo2)' +p681 +ss(S'image' +g166 +NS'powerpc-smp' +tp682 +(dp683 +S'configs' +p684 +(lp685 +S'powerpc/config.powerpc' +p686 +aS'powerpc/config.powerpc-smp' +p687 +ass(S'image' +g140 +NS'sparc32' +tp688 +(dp689 +S'image-postproc' +p690 +S'sparc32-image-postproc' +p691 +ss(S'description' +g53 +NS'vexpress' +tp692 +(dp693 S'hardware' +p694 +S'ARM Ltd. Versatile Express' +p695 +sS'hardware-long' p696 -S'uniprocessor 32-bit PowerPC' +S'ARM Ltd. Versatile Express family of processors' p697 ss(S'image' -g66 -NS'sb1-bcm91250a' +g99 tp698 (dp699 -S'configs' +S'suggests' p700 -(lp701 -S'mips/config.sb1-bcm91250a' -p702 -ass(S'description' -g58 -g59 -S'686-pae' -tp703 -(dp704 -S'parts' +S'fdutils' +p701 +ss(S'base' +g455 +tp702 +(dp703 +S'kernel-arch' +p704 +S'parisc' p705 +sg118 (lp706 -S'xen' +g92 +asS'compiler' p707 -ass(S'description' -g187 -NS'mx5' -tp708 -(dp709 +S'gcc-4.4' +p708 +ss(S'description' +g78 +NS'kirkwood' +tp709 +(dp710 S'hardware' -p710 -S'Freescale i.MX51/53' p711 -sS'hardware-long' +S'Marvell Kirkwood' p712 -S'Freescale i.MX51 or i.MX53 based systems' +sS'hardware-long' p713 -ss(S'image' -g5 -NS'amd64' -tp714 -(dp715 -S'configs' -p716 -(lp717 -S'kernelarch-x86/config-arch-64' +S'Marvell Kirkwood based systems (SheevaPlug, QNAP TS-119/TS-219, etc)' +p714 +ss(S'description' +g32 +NS'mvme16x' +tp715 +(dp716 +S'hardware' +p717 +S'Motorola MVME162/6/7, MVME172/7' p718 -ass(S'image' -g306 -NS'powerpc64' +ss(S'base' +g99 tp719 (dp720 -S'configs' +S'kernel-arch' p721 -(lp722 -S'powerpc/config.powerpc64' -p723 -ass(S'image' -g29 +S'sh' +p722 +sg118 +(lp723 +g92 +ass(S'build' +g16 +NS'686-pae' tp724 (dp725 -S'suggests' +S'debug-info' p726 -S'vmelilo, fdutils' -p727 -sS'initramfs' -p728 -I00 -ss(S'description' -g45 -NS'sh7751r' -tp729 -(dp730 -S'hardware' +I01 +ss(S'abi' +g205 +tp727 +(dp728 +S'ignore-changes' +p729 +(lp730 +S'vgacon_*' p731 -S'sh7751r' -p732 -sS'hardware-long' -p733 -S'Renesas SH7751R R2D plus board' +ass(S'image' +g140 +tp732 +(dp733 +S'suggests' p734 -ss(g143 -g187 -g123 -tp735 -(dp736 -g146 -I01 -sg147 -(lp737 -S'mx5' -p738 -aS'omap' +S'silo, fdutils' +p735 +ss(S'description' +NS'rt' +p736 +tp737 +(dp738 +S'part-long-rt' p739 -aS'vexpress' +S'This kernel includes the PREEMPT_RT realtime patch set.' p740 -ass(S'base' -g187 -tp741 -(dp742 -S'kernel-arch' +sS'parts' +p741 +(lp742 +S'rt' p743 -S'arm' +asS'part-short-rt' p744 -sg121 -(lp745 -g123 -ass(S'description' -g116 -NS'alpha-legacy' +S'PREEMPT_RT' +p745 +ss(S'description' tp746 (dp747 -S'hardware' +S'part-long-up' p748 -S'Alpha Legacy' +S'This kernel is not suitable for SMP (multi-processor,\nmulti-core or hyper-threaded) systems.' p749 -sS'hardware-long' +sS'part-long-xen' p750 -S'DEC Alpha systems with legacy kernel start address' +S'This kernel also runs on a Xen hypervisor.\nIt supports both privileged (dom0) and unprivileged (domU) operation.' p751 -ss(S'image' -g45 +ss(S'description' +g205 +NS'sb1-bcm91250a' tp752 (dp753 -S'suggests' +S'hardware' p754 -S'fdutils' +S'BCM91250A' p755 -ss(S'base' -g16 -tp756 -(dp757 -S'kernel-arch' -p758 -S'parisc' -p759 -sg121 -(lp760 -g123 -asS'compiler' -p761 -S'gcc-4.4' -p762 -ss(S'description' -g66 -NS'4kc-malta' -tp763 -(dp764 -S'hardware' -p765 -S'MIPS Malta' -p766 sS'hardware-long' +p756 +S'Broadcom BCM91250A systems (aka SWARM)' +p757 +ss(S'build' +g45 +NS's390-tape' +tp758 +(dp759 +S'modules' +p760 +I00 +ss(S'build' +g78 +NS'mv78xx0' +tp761 +(dp762 +S'image-file' +p763 +S'arch/arm/boot/zImage' +p764 +ss(S'image' +g16 +NS'amd64' +tp765 +(dp766 +S'configs' p767 -S'MIPS Malta boards' -p768 +(lp768 +S'kernelarch-x86/config-arch-64' +p769 +asS'recommends' +p770 +S'libc6-i686' +p771 ss(S'description' -g100 -NS'powerpc64' -tp769 -(dp770 +g113 +NS'alpha-generic' +tp772 +(dp773 S'hardware' -p771 -S'64-bit PowerPC' -p772 -ss(S'base' -tp773 -(dp774 -S'arches' +p774 +S'Alpha' p775 -(lp776 -S'alpha' +sS'hardware-long' +p776 +S'DEC Alpha systems with extended kernel start address (Wildfire, Titan, Marvel)' p777 -aS'amd64' -p778 -aS'armel' -p779 -aS'armhf' +ss(S'base' +g45 +tp778 +(dp779 +S'kernel-arch' p780 -aS'hppa' +S's390' p781 -aS'i386' -p782 -aS'ia64' -p783 -aS'm68k' -p784 -aS'mips' +sg118 +(lp782 +g92 +ass(S'image' +g306 +tp783 +(dp784 +S'suggests' p785 -aS'mipsel' +S'silo, fdutils' p786 -aS'powerpc' +sS'configs' p787 -aS'ppc64' -p788 -aS's390' +(lp788 +S'sparc/config' p789 -aS's390x' -p790 -aS'sh4' -p791 -aS'sparc' +ass(S'description' +g106 +NS'sb1-bcm91250a' +tp790 +(dp791 +S'hardware' p792 -aS'sparc64' +S'BCM91250A' p793 -asS'featuresets' +sS'hardware-long' p794 -(lp795 -S'none' -p796 -aS'rt' -p797 -asS'compiler' +S'Broadcom BCM91250A systems (aka SWARM)' +p795 +ss(S'image' +g45 +NS's390x-tape' +tp796 +(dp797 +S'override-localversion' p798 -S'gcc-4.6' +S's390x' p799 +sS'type' +p800 +S'plain-s390-tape' +p801 +sS'initramfs' +p802 +I00 +ss(S'build' +g99 +NS'sh7785lcr' +tp803 +(dp804 +S'image-file' +p805 +S'arch/sh/boot/zImage' +p806 ss(S'base' -g45 -tp800 -(dp801 +g166 +tp807 +(dp808 S'kernel-arch' -p802 -S'sh' -p803 -sg121 -(lp804 -g123 -ass(S'abi' -g66 -tp805 -(dp806 -S'ignore-changes' -p807 -(lp808 -S'vgacon_*' p809 -ass(S'image' -g326 -tp810 -(dp811 -S'suggests' -p812 -S'silo, fdutils' -p813 -ss(S'build' -g247 -NS's390x' -tp814 -(dp815 -S'debug-info' -p816 -I01 -ss(S'description' -tp817 -(dp818 -S'part-long-up' +S'powerpc' +p810 +sg118 +(lp811 +g92 +ass(S'description' +g32 +NS'atari' +tp812 +(dp813 +S'hardware' +p814 +S'Atari' +p815 +ss(S'base' +g455 +NS'parisc64-smp' +tp816 +(dp817 +S'override-host-type' +p818 +S'hppa64-linux-gnu' p819 -S'This kernel is not suitable for SMP (multi-processor,\nmulti-core or hyper-threaded) systems.' +sS'cflags' p820 -sS'part-long-xen' +S'-fno-cse-follow-jumps' p821 -S'This kernel also runs on a Xen hypervisor.\nIt supports both privileged (dom0) and unprivileged (domU) operation.' -p822 -ss(S'build' -g34 -NS's390x' -tp823 -(dp824 -S'debug-info' -p825 -I01 ss(S'description' -g124 -NS'kirkwood' -tp826 -(dp827 +g113 +NS'alpha-smp' +tp822 +(dp823 S'hardware' -p828 -S'Marvell Kirkwood' -p829 +p824 +S'Alpha SMP' +p825 sS'hardware-long' +p826 +S'DEC Alpha SMP systems with extended kernel start address (Wildfire, Titan, Marvel)' +p827 +ss(S'description' +g32 +NS'mac' +tp828 +(dp829 +S'hardware' p830 -S'Marvell Kirkwood based systems (SheevaPlug, QNAP TS-119/TS-219, etc)' +S'Macintosh' p831 ss(S'build' -g58 -NS'686-pae' +g53 +NS'vexpress' tp832 (dp833 -S'debug-info' +S'image-file' p834 -I01 +S'arch/arm/boot/zImage' +p835 ss(S'description' -g66 -NS'sb1a-bcm91480b' -tp835 -(dp836 +g205 +NS'5kc-malta' +tp836 +(dp837 S'hardware' -p837 -S'BCM91480B' p838 -sS'hardware-long' +S'MIPS Malta (64-bit)' p839 -S'Broadcom BCM91480B systems (aka BigSur)' +sS'hardware-long' p840 +S'MIPS Malta boards (64-bit)' +p841 ss(S'image' -g211 -tp841 -(dp842 -S'suggests' -p843 -S'silo, fdutils' +g205 +NS'5kc-malta' +tp842 +(dp843 +S'configs' p844 -sS'configs' -p845 -(lp846 -S'sparc/config' -p847 -ass(S'base' -g100 -tp848 -(dp849 -S'kernel-arch' -p850 -S'powerpc' -p851 -sg121 -(lp852 -g123 +(lp845 +S'mips/config.5kc-malta' +p846 ass(S'description' -g124 -NS'orion5x' -tp853 -(dp854 -S'hardware' -p855 -S'Marvell Orion' -p856 -sS'hardware-long' +g215 +tp847 +(dp848 +S'part-short-tape' +p849 +S'IPL from tape' +p850 +sS'part-long-tape' +p851 +S'This kernel has support to IPL (boot) from a tape.' +p852 +sS'part-long-reader' +p853 +S'This kernel has support to IPL (boot) from a VM reader or DASD device.' +p854 +ss(S'image' +g53 +tp855 +(dp856 +S'suggests' p857 -S'Marvell Orion 5181, 5182 and 5281 based systems (QNAP TS-109/TS-209, etc)' +S'fdutils' p858 -ss(S'description' -g66 -NS'r5k-cobalt' -tp859 -(dp860 -S'hardware' +sS'configs' +p859 +(lp860 +S'armel/config' p861 -S'Cobalt' +aS'armhf/config' p862 -sS'hardware-long' -p863 -S'Cobalt systems (Qube, RaQ, Qube2, RaQ2)' -p864 -ss(S'description' -g66 -NS'loongson-2f' -tp865 -(dp866 -S'hardware' -p867 -S'Loongson 2F' +ass(S'abi' +tp863 +(dp864 +S'abiname' +p865 +S'4' +sS'ignore-changes' +p866 +(lp867 +S'module:net/l2tp/*' p868 -sS'hardware-long' +aS'__rpc_wait_for_completion_task' p869 -S'Lemote Loongson 2F systems' +aS'bc_svc_process' p870 -ss(S'description' -g124 -NS'versatile' -tp871 -(dp872 -S'hardware' +aS'nfs4*' +p871 +aS'nfs_*' +p872 +aS'nlmclnt_*' p873 -S'Versatile' +aS'nlmsvc_*' p874 -sS'hardware-long' +aS'pnfs_*' p875 -S'Versatile systems (PB, AB, Qemu)' +aS'put_lseg' p876 -ss(S'description' -g247 -NS's390' -tp877 -(dp878 -S'hardware' +aS'put_rpccred' +p877 +aS'rpc_*' +p878 +aS'rpcauth_*' p879 -S'IBM S/390' +aS'rpcb_getport_async' p880 -sS'parts' +aS'svc_*' p881 -(lp882 -S'reader' +aS'svcauth_unix_set_client' +p882 +aS'unix_domain_find' p883 -ass(S'build' -g124 -NS'orion5x' -tp884 -(dp885 -S'image-file' +aS'xprt_*' +p884 +aS'get_write_access' +p885 +aS'module:drivers/gpu/drm/*' p886 -S'arch/arm/boot/zImage' +aS'drm_sman_*' p887 -ss(S'description' -g34 -tp888 -(dp889 -S'part-short-tape' +aS'intel_agp_enabled' +p888 +aS'intel_gmch_*' +p889 +aS'intel_gtt_*' p890 -S'IPL from tape' +aS'module:drivers/net/wan/cycx_drv' p891 -sS'part-long-tape' +aS'module:net/wanrouter/wanrouter' p892 -S'This kernel has support to IPL (boot) from a tape.' +aS'register_virtio_*' p893 -sS'part-long-reader' +aS'unregister_virtio_*' p894 -S'This kernel has support to IPL (boot) from a VM reader or DASD device.' +aS'virtio_*' p895 -ss(S'description' -g169 -NS'octeon' -tp896 -(dp897 -S'hardware' +aS'virtqueue_*' +p896 +aS'vring_*' +p897 +aS'module:drivers/staging/*' p898 -S'Octeon' +aS'module:drivers/net/wireless/rtlwifi/*' p899 -sS'hardware-long' +aS'kmsg_dump_register' p900 -S'Cavium Networks Octeon' +aS'kmsg_dump_unregister' p901 -ss(S'abi' -tp902 -(dp903 -S'abiname' +aS'register_efivars' +p902 +aS'unregister_efivars' +p903 +aS'module:drivers/usb/serial/*' p904 -S'4' -sS'ignore-changes' +aS'module:arch/s390/kvm/kvm' p905 -(lp906 -S'module:net/l2tp/*' -p907 -aS'__rpc_wait_for_completion_task' +ass(S'build' +g78 +NS'ixp4xx' +tp906 +(dp907 +S'image-file' p908 -aS'bc_svc_process' +S'arch/arm/boot/zImage' p909 -aS'nfs4*' -p910 -aS'nfs_*' -p911 -aS'nlmclnt_*' +ss(S'description' +g45 +NS's390-tape' +tp910 +(dp911 +S'hardware' p912 -aS'nlmsvc_*' +S'IBM S/390' p913 -aS'pnfs_*' +sS'parts' p914 -aS'put_lseg' -p915 -aS'put_rpccred' +(lp915 +S'tape' p916 -aS'rpc_*' -p917 -aS'rpcauth_*' -p918 -aS'rpcb_getport_async' +ass(S'description' +g306 +NS'sparc64' +tp917 +(dp918 +S'hardware' p919 -aS'svc_*' +S'uniprocessor 64-bit UltraSPARC' p920 -aS'svcauth_unix_set_client' -p921 -aS'unix_domain_find' -p922 -aS'xprt_*' -p923 -aS'get_write_access' +ss(g91 +g32 +g92 +tp921 +(dp922 +g95 +I01 +sg96 +(lp923 +S'amiga' p924 -aS'module:drivers/gpu/drm/*' +aS'atari' p925 -aS'drm_sman_*' +aS'bvme6000' p926 -aS'intel_agp_enabled' +aS'mac' p927 -aS'intel_gmch_*' +aS'mvme147' p928 -aS'intel_gtt_*' +aS'mvme16x' p929 -aS'module:drivers/net/wan/cycx_drv' -p930 -aS'module:net/wanrouter/wanrouter' -p931 -aS'register_virtio_*' +ass(S'description' +g106 +NS'sb1a-bcm91480b' +tp930 +(dp931 +S'hardware' p932 -aS'unregister_virtio_*' +S'BCM91480B' p933 -aS'virtio_*' +sS'hardware-long' p934 -aS'virtqueue_*' +S'Broadcom BCM91480B systems (aka BigSur)' p935 -aS'vring_*' -p936 -aS'module:drivers/staging/*' -p937 -aS'module:drivers/net/wireless/rtlwifi/*' +ss(S'abi' +g16 +tp936 +(dp937 +S'ignore-changes' p938 -aS'kmsg_dump_register' -p939 -aS'kmsg_dump_unregister' +(lp939 +S'disable_hlt' p940 -aS'register_efivars' +aS'enable_hlt' p941 -aS'unregister_efivars' +aS'module:arch/x86/kvm/kvm' p942 -aS'module:drivers/usb/serial/*' -p943 -aS'module:arch/s390/kvm/kvm' -p944 -ass(S'build' -g247 -NS's390x-tape' -tp945 -(dp946 -S'modules' +ass(S'base' +tp943 +(dp944 +S'arches' +p945 +(lp946 +S'alpha' p947 -I00 -ss(S'build' -g34 -NS's390x-tape' -tp948 -(dp949 -S'modules' +aS'amd64' +p948 +aS'armel' +p949 +aS'armhf' p950 -I00 -ss(S'abi' -g58 -tp951 -(dp952 -S'ignore-changes' +aS'hppa' +p951 +aS'i386' +p952 +aS'ia64' p953 -(lp954 -S'disable_hlt' +aS'm68k' +p954 +aS'mips' p955 -aS'enable_hlt' +aS'mipsel' p956 -aS'module:arch/x86/kvm/kvm' +aS'powerpc' p957 -ass(S'base' -g58 -g59 -tp958 -(dp959 -S'flavours' +aS'ppc64' +p958 +aS's390' +p959 +aS's390x' p960 -(lp961 -S'486' +aS'sh4' +p961 +aS'sparc' p962 -aS'686-pae' +aS'sparc64' p963 -aS'amd64' +asS'featuresets' p964 -ass(S'description' -g50 -NS'itanium' -tp965 -(dp966 -S'hardware' +(lp965 +S'none' +p966 +aS'rt' p967 -S'Itanium' +asS'compiler' p968 +S'gcc-4.6' +p969 ss(S'image' -g34 -NS's390x' -tp969 -(dp970 +g5 +NS'amd64' +tp970 +(dp971 S'configs' -p971 -(lp972 -S's390/config.s390x' -p973 +p972 +(lp973 +S'kernelarch-x86/config-arch-64' +p974 ass(S'description' -g29 -NS'atari' -tp974 -(dp975 +g53 +NS'mx5' +tp975 +(dp976 S'hardware' -p976 -S'Atari' p977 -ss(S'build' -g124 -NS'kirkwood' -tp978 -(dp979 -S'image-file' +S'Freescale i.MX51/53' +p978 +sS'hardware-long' +p979 +S'Freescale i.MX51 or i.MX53 based systems' p980 -S'arch/arm/boot/zImage' -p981 ss(S'description' -Ng589 -tp982 -(dp983 -S'part-long-rt' +g113 +NS'alpha-legacy' +tp981 +(dp982 +S'hardware' +p983 +S'Alpha Legacy' p984 -S'This kernel includes the PREEMPT_RT realtime patch set.' +sS'hardware-long' p985 -sS'parts' +S'DEC Alpha systems with legacy kernel start address' p986 -(lp987 -S'rt' -p988 -asS'part-short-rt' -p989 -S'PREEMPT_RT' +ss(g91 +g166 +g92 +tp987 +(dp988 +g95 +I01 +sg96 +(lp989 +S'powerpc' p990 -ss(S'base' -g29 -tp991 -(dp992 -S'kernel-arch' -p993 -S'm68k' -p994 -sg121 -(lp995 -g123 -asS'cflags' +aS'powerpc-smp' +p991 +aS'powerpc64' +p992 +ass(S'description' +g16 +NS'486' +tp993 +(dp994 +S'hardware' +p995 +S'older PCs' p996 -S'-ffreestanding' +sS'parts' p997 -sS'compiler' -p998 -S'gcc-4.6' +(lp998 +S'up' p999 +asS'hardware-long' +p1000 +S'PCs with a single processor not supporting PAE' +p1001 ss(S'image' -tp1000 -(dp1001 -S'initramfs-generators' -p1002 -(lp1003 -S'initramfs-tools' +g16 +NS'486' +tp1002 +(dp1003 +S'configs' p1004 -aS'initramfs-fallback' -p1005 -asS'type' +(lp1005 +S'kernelarch-x86/config-arch-32' p1006 -S'plain' -p1007 -ss(S'description' -g29 -NS'mvme16x' -tp1008 -(dp1009 -S'hardware' -p1010 -S'Motorola MVME162/6/7, MVME172/7' +ass(S'image' +g205 +NS'sb1a-bcm91480b' +tp1007 +(dp1008 +S'configs' +p1009 +(lp1010 +S'mips/config.sb1a-bcm91480b' p1011 -ss(S'description' -g169 -NS'5kc-malta' +ass(S'abi' +Ng736 tp1012 (dp1013 -S'hardware' +S'ignore-changes' p1014 -S'MIPS Malta (64-bit)' -p1015 -sS'hardware-long' -p1016 -S'MIPS Malta boards (64-bit)' -p1017 -ss(g143 -g211 -g123 -tp1018 -(dp1019 -g146 -I01 -sg147 +(lp1015 +S'*' +ass(S'base' +g32 +tp1016 +(dp1017 +S'kernel-arch' +p1018 +S'm68k' +p1019 +sg118 (lp1020 -S'sparc64' +g92 +asS'cflags' p1021 -aS'sparc64-smp' +S'-ffreestanding' p1022 -ass(S'image' -g58 +sS'compiler' +p1023 +S'gcc-4.6' +p1024 +ss(S'description' +g5 NS'amd64' -tp1023 -(dp1024 -S'configs' -p1025 -(lp1026 -S'kernelarch-x86/config-arch-64' +tp1025 +(dp1026 +S'hardware' p1027 -asS'recommends' +S'64-bit PCs' p1028 -S'libc6-i686' +sS'hardware-long' p1029 -ss(S'image' -g100 -tp1030 -(dp1031 -S'suggests' -p1032 -S'mkvmlinuz' +S'PCs with AMD64, Intel 64 or VIA Nano processors' +p1030 +ss(S'description' +g45 +NS's390x-tape' +tp1031 +(dp1032 +S'hardware' p1033 -ss(S'build' -g124 -NS'mv78xx0' -tp1034 -(dp1035 -S'image-file' -p1036 -S'arch/arm/boot/zImage' +S'IBM zSeries' +p1034 +sS'parts' +p1035 +(lp1036 +S'tape' p1037 -ss(S'description' -g58 -NS'686-pae' +ass(g91 +g306 +g92 tp1038 (dp1039 -S'hardware' -p1040 -S'modern PCs' +g95 +I01 +sg96 +(lp1040 +S'sparc64' p1041 -sS'parts' +aS'sparc64-smp' p1042 -(lp1043 -S'pae' -p1044 -asS'hardware-long' +ass(S'image' +g16 +NS'686-pae' +tp1043 +(dp1044 +S'configs' p1045 -S'PCs with one or more processors supporting PAE' -p1046 +(lp1046 +S'kernelarch-x86/config-arch-32' +p1047 +asS'recommends' +p1048 +S'libc6-i686' +p1049 +ss(S'build' +g45 +NS's390x' +tp1050 +(dp1051 +S'debug-info' +p1052 +I01 ss(S'description' -g50 -NS'mckinley' -tp1047 -(dp1048 +g455 +NS'parisc64' +tp1053 +(dp1054 S'hardware' -p1049 -S'Itanium II' -p1050 -ss(S'image' -g34 -tp1051 -(dp1052 -S'configs' -p1053 -(lp1054 -S's390/config' p1055 -asS'bootloaders' +S'64-bit PA-RISC' p1056 -(lp1057 -S's390-tools' -p1058 -ass(S'description' -g16 -NS'parisc64-smp' -tp1059 -(dp1060 -S'hardware' -p1061 -S'multiprocessor 64-bit PA-RISC' -p1062 ss(S'description' -g326 -NS'sparc32' -tp1063 -(dp1064 +g45 +NS's390' +tp1057 +(dp1058 S'hardware' -p1065 -S'uniprocessor sparc32 (sun4m)' +p1059 +S'IBM S/390' +p1060 +sS'parts' +p1061 +(lp1062 +S'reader' +p1063 +ass(S'image' +g215 +tp1064 +(dp1065 +S'configs' p1066 -ss(S'relations' -g16 -tp1067 -(dp1068 -S'gcc-4.4' +(lp1067 +S's390/config' +p1068 +asS'bootloaders' p1069 -S'gcc-4.4, binutils-hppa64, gcc-4.4-hppa64' -p1070 -ss(S'description' -g66 -NS'sb1-bcm91250a' -tp1071 -(dp1072 +(lp1070 +S's390-tools' +p1071 +ass(S'description' +g455 +NS'parisc' +tp1072 +(dp1073 S'hardware' -p1073 -S'BCM91250A' p1074 -sS'hardware-long' +S'32-bit PA-RISC' p1075 -S'Broadcom BCM91250A systems (aka SWARM)' -p1076 -ss(S'image' -g211 -NS'sparc64' -tp1077 -(dp1078 -S'configs' +ss(S'description' +g205 +NS'loongson-2f' +tp1076 +(dp1077 +S'hardware' +p1078 +S'Loongson 2F' p1079 -(lp1080 -S'sparc/config.sparc64' +sS'hardware-long' +p1080 +S'Lemote Loongson 2F systems' p1081 -asstRp1082 +ss(S'build' +g53 +NS'omap' +tp1082 +(dp1083 +S'image-file' +p1084 +S'arch/arm/boot/zImage' +p1085 +ss(S'description' +g455 +NS'parisc-smp' +tp1086 +(dp1087 +S'hardware' +p1088 +S'multiprocessor 32-bit PA-RISC' +p1089 +sstRp1090 . \ No newline at end of file diff -Nru linux-3.2.46/debian/control linux-3.2.46/debian/control --- linux-3.2.46/debian/control 2013-06-08 21:44:19.000000000 +0000 +++ linux-3.2.46/debian/control 2013-07-26 21:15:07.000000000 +0000 @@ -193,8 +193,8 @@ This package contains the kernel image for the Debian installer boot images. It does _not_ provide a usable kernel for your full Debian system. -Kernel-Version: 3.2.0-4-amd64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-amd64 Package: nic-modules-3.2.0-4-amd64-di Architecture: amd64 @@ -204,8 +204,8 @@ Depends: kernel-image-3.2.0-4-amd64-di, nic-shared-modules-3.2.0-4-amd64-di, core-modules-3.2.0-4-amd64-di, firewire-core-modules-3.2.0-4-amd64-di Description: Common NIC drivers This package contains common NIC drivers for the kernel. -Kernel-Version: 3.2.0-4-amd64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-amd64 Package: nic-extra-modules-3.2.0-4-amd64-di Architecture: amd64 @@ -215,8 +215,8 @@ Depends: kernel-image-3.2.0-4-amd64-di, nic-shared-modules-3.2.0-4-amd64-di, core-modules-3.2.0-4-amd64-di, i2c-modules-3.2.0-4-amd64-di, crc-modules-3.2.0-4-amd64-di Description: Rare NIC drivers This package contains rare NIC drivers for the kernel. -Kernel-Version: 3.2.0-4-amd64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-amd64 Package: nic-wireless-modules-3.2.0-4-amd64-di Architecture: amd64 @@ -227,8 +227,8 @@ Description: Wireless NIC drivers This package contains wireless NIC drivers for the kernel. Includes crypto modules only needed for wireless (WEP). -Kernel-Version: 3.2.0-4-amd64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-amd64 Package: nic-shared-modules-3.2.0-4-amd64-di Architecture: amd64 @@ -239,8 +239,8 @@ Description: Shared NIC drivers This package contains NIC drivers needed by combinations of nic-modules, nic-extra-modules, nic-pcmcia-modules, and nic-wireless-modules. -Kernel-Version: 3.2.0-4-amd64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-amd64 Package: serial-modules-3.2.0-4-amd64-di Architecture: amd64 @@ -250,8 +250,8 @@ Depends: kernel-image-3.2.0-4-amd64-di, pcmcia-modules-3.2.0-4-amd64-di Description: Serial drivers This package contains serial drivers for the kernel. -Kernel-Version: 3.2.0-4-amd64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-amd64 Package: usb-serial-modules-3.2.0-4-amd64-di Architecture: amd64 @@ -261,8 +261,8 @@ Depends: kernel-image-3.2.0-4-amd64-di, usb-modules-3.2.0-4-amd64-di Description: USB serial drivers This package contains USB serial drivers for the kernel. -Kernel-Version: 3.2.0-4-amd64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-amd64 Package: ppp-modules-3.2.0-4-amd64-di Architecture: amd64 @@ -272,8 +272,8 @@ Depends: kernel-image-3.2.0-4-amd64-di, serial-modules-3.2.0-4-amd64-di, zlib-modules-3.2.0-4-amd64-di, crc-modules-3.2.0-4-amd64-di Description: PPP drivers This package contains PPP drivers for the kernel. -Kernel-Version: 3.2.0-4-amd64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-amd64 Package: pata-modules-3.2.0-4-amd64-di Architecture: amd64 @@ -283,8 +283,8 @@ Depends: kernel-image-3.2.0-4-amd64-di, ata-modules-3.2.0-4-amd64-di Description: PATA drivers This package contains PATA drivers for the kernel. -Kernel-Version: 3.2.0-4-amd64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-amd64 Package: cdrom-core-modules-3.2.0-4-amd64-di Architecture: amd64 @@ -294,8 +294,8 @@ Depends: kernel-image-3.2.0-4-amd64-di, scsi-core-modules-3.2.0-4-amd64-di, isofs-modules-3.2.0-4-amd64-di Description: CDROM support This package contains core CDROM support for the kernel. -Kernel-Version: 3.2.0-4-amd64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-amd64 Package: firewire-core-modules-3.2.0-4-amd64-di Architecture: amd64 @@ -305,8 +305,8 @@ Depends: kernel-image-3.2.0-4-amd64-di, scsi-core-modules-3.2.0-4-amd64-di, crc-modules-3.2.0-4-amd64-di Description: Core FireWire drivers This package contains core FireWire drivers for the kernel. -Kernel-Version: 3.2.0-4-amd64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-amd64 Package: scsi-core-modules-3.2.0-4-amd64-di Architecture: amd64 @@ -316,8 +316,8 @@ Depends: kernel-image-3.2.0-4-amd64-di Description: Core SCSI subsystem This package contains the core SCSI subsystem for the kernel. -Kernel-Version: 3.2.0-4-amd64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-amd64 Package: scsi-modules-3.2.0-4-amd64-di Architecture: amd64 @@ -327,8 +327,8 @@ Depends: kernel-image-3.2.0-4-amd64-di, scsi-core-modules-3.2.0-4-amd64-di, scsi-common-modules-3.2.0-4-amd64-di, parport-modules-3.2.0-4-amd64-di, cdrom-core-modules-3.2.0-4-amd64-di, core-modules-3.2.0-4-amd64-di, ata-modules-3.2.0-4-amd64-di Description: SCSI drivers This package contains SCSI drivers for the kernel. -Kernel-Version: 3.2.0-4-amd64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-amd64 Package: scsi-common-modules-3.2.0-4-amd64-di Architecture: amd64 @@ -338,8 +338,8 @@ Depends: kernel-image-3.2.0-4-amd64-di, scsi-core-modules-3.2.0-4-amd64-di, cdrom-core-modules-3.2.0-4-amd64-di Description: Very common SCSI drivers This package contains very common SCSI drivers for the kernel. -Kernel-Version: 3.2.0-4-amd64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-amd64 Package: scsi-extra-modules-3.2.0-4-amd64-di Architecture: amd64 @@ -350,8 +350,8 @@ Description: Uncommon SCSI drivers This package contains uncommon SCSI drivers for the kernel. This includes SCSI RAID drivers, and some of the less common SCSI controllers. -Kernel-Version: 3.2.0-4-amd64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-amd64 Package: plip-modules-3.2.0-4-amd64-di Architecture: amd64 @@ -361,8 +361,8 @@ Depends: kernel-image-3.2.0-4-amd64-di, parport-modules-3.2.0-4-amd64-di Description: PLIP drivers This package contains PLIP drivers for the kernel. -Kernel-Version: 3.2.0-4-amd64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-amd64 Package: floppy-modules-3.2.0-4-amd64-di Architecture: amd64 @@ -372,8 +372,8 @@ Depends: kernel-image-3.2.0-4-amd64-di Description: Floppy driver This package contains the floppy driver for the kernel. -Kernel-Version: 3.2.0-4-amd64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-amd64 Package: loop-modules-3.2.0-4-amd64-di Architecture: amd64 @@ -383,8 +383,8 @@ Depends: kernel-image-3.2.0-4-amd64-di Description: Loopback filesystem support This package contains loopback filesystem support for the kernel. -Kernel-Version: 3.2.0-4-amd64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-amd64 Package: btrfs-modules-3.2.0-4-amd64-di Architecture: amd64 @@ -394,8 +394,8 @@ Depends: kernel-image-3.2.0-4-amd64-di, core-modules-3.2.0-4-amd64-di, crc-modules-3.2.0-4-amd64-di, zlib-modules-3.2.0-4-amd64-di Description: BTRFS filesystem support This package contains the BTRFS filesystem module for the kernel. -Kernel-Version: 3.2.0-4-amd64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-amd64 Package: ext2-modules-3.2.0-4-amd64-di Architecture: amd64 @@ -405,8 +405,8 @@ Depends: kernel-image-3.2.0-4-amd64-di, core-modules-3.2.0-4-amd64-di Description: EXT2 filesystem support This package contains the EXT2 filesystem module for the kernel. -Kernel-Version: 3.2.0-4-amd64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-amd64 Package: ext3-modules-3.2.0-4-amd64-di Architecture: amd64 @@ -416,8 +416,8 @@ Depends: kernel-image-3.2.0-4-amd64-di, core-modules-3.2.0-4-amd64-di Description: EXT3 filesystem support This package contains the EXT3 filesystem module for the kernel. -Kernel-Version: 3.2.0-4-amd64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-amd64 Package: ext4-modules-3.2.0-4-amd64-di Architecture: amd64 @@ -427,8 +427,8 @@ Depends: kernel-image-3.2.0-4-amd64-di, core-modules-3.2.0-4-amd64-di Description: EXT4 filesystem support This package contains the EXT4 filesystem module for the kernel. -Kernel-Version: 3.2.0-4-amd64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-amd64 Package: isofs-modules-3.2.0-4-amd64-di Architecture: amd64 @@ -438,8 +438,8 @@ Depends: kernel-image-3.2.0-4-amd64-di Description: ISOFS filesystem support This package contains the ISOFS filesystem module for the kernel. -Kernel-Version: 3.2.0-4-amd64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-amd64 Package: jfs-modules-3.2.0-4-amd64-di Architecture: amd64 @@ -449,8 +449,8 @@ Depends: kernel-image-3.2.0-4-amd64-di Description: JFS filesystem support This package contains the JFS filesystem module for the kernel. -Kernel-Version: 3.2.0-4-amd64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-amd64 Package: ntfs-modules-3.2.0-4-amd64-di Architecture: amd64 @@ -460,8 +460,8 @@ Depends: kernel-image-3.2.0-4-amd64-di Description: NTFS filesystem support This package contains the NTFS file system module for the kernel. -Kernel-Version: 3.2.0-4-amd64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-amd64 Package: reiserfs-modules-3.2.0-4-amd64-di Architecture: amd64 @@ -471,8 +471,8 @@ Depends: kernel-image-3.2.0-4-amd64-di Description: Reiser filesystem support This package contains the Reiser filesystem module for the kernel. -Kernel-Version: 3.2.0-4-amd64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-amd64 Package: xfs-modules-3.2.0-4-amd64-di Architecture: amd64 @@ -482,8 +482,8 @@ Depends: kernel-image-3.2.0-4-amd64-di Description: XFS filesystem support This package contains the XFS filesystem module for the kernel. -Kernel-Version: 3.2.0-4-amd64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-amd64 Package: fat-modules-3.2.0-4-amd64-di Architecture: amd64 @@ -493,8 +493,8 @@ Depends: kernel-image-3.2.0-4-amd64-di Description: FAT filesystem support This package contains the FAT and VFAT filesystem modules for the kernel. -Kernel-Version: 3.2.0-4-amd64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-amd64 Package: ufs-modules-3.2.0-4-amd64-di Architecture: amd64 @@ -504,8 +504,8 @@ Depends: kernel-image-3.2.0-4-amd64-di Description: UFS filesystem support This package contains the UFS filesystem module for the kernel. -Kernel-Version: 3.2.0-4-amd64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-amd64 Package: qnx4-modules-3.2.0-4-amd64-di Architecture: amd64 @@ -515,8 +515,8 @@ Depends: kernel-image-3.2.0-4-amd64-di Description: QNX4 filesystem support This package contains the QNX4 filesystem module for the kernel. -Kernel-Version: 3.2.0-4-amd64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-amd64 Package: md-modules-3.2.0-4-amd64-di Architecture: amd64 @@ -526,8 +526,8 @@ Depends: kernel-image-3.2.0-4-amd64-di Description: RAID and LVM support This package contains RAID and LVM modules for the kernel. -Kernel-Version: 3.2.0-4-amd64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-amd64 Package: multipath-modules-3.2.0-4-amd64-di Architecture: amd64 @@ -537,8 +537,8 @@ Depends: kernel-image-3.2.0-4-amd64-di, md-modules-3.2.0-4-amd64-di, scsi-core-modules-3.2.0-4-amd64-di Description: Multipath support This package contains DM-Multipath modules for the kernel. -Kernel-Version: 3.2.0-4-amd64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-amd64 Package: usb-modules-3.2.0-4-amd64-di Architecture: amd64 @@ -548,8 +548,8 @@ Depends: kernel-image-3.2.0-4-amd64-di Description: USB support This package contains core USB drivers for the kernel. -Kernel-Version: 3.2.0-4-amd64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-amd64 Package: usb-storage-modules-3.2.0-4-amd64-di Architecture: amd64 @@ -559,8 +559,8 @@ Depends: kernel-image-3.2.0-4-amd64-di, scsi-core-modules-3.2.0-4-amd64-di, usb-modules-3.2.0-4-amd64-di Description: USB storage support This package contains the USB storage driver for the kernel. -Kernel-Version: 3.2.0-4-amd64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-amd64 Package: pcmcia-storage-modules-3.2.0-4-amd64-di Architecture: amd64 @@ -570,8 +570,8 @@ Depends: kernel-image-3.2.0-4-amd64-di, cdrom-core-modules-3.2.0-4-amd64-di, pcmcia-modules-3.2.0-4-amd64-di, ata-modules-3.2.0-4-amd64-di Description: PCMCIA storage drivers This package contains PCMCIA storage drivers for the kernel. -Kernel-Version: 3.2.0-4-amd64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-amd64 Package: fb-modules-3.2.0-4-amd64-di Architecture: amd64 @@ -581,8 +581,8 @@ Depends: kernel-image-3.2.0-4-amd64-di Description: Frame buffer support This package contains Frame buffer drivers for the kernel. -Kernel-Version: 3.2.0-4-amd64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-amd64 Package: input-modules-3.2.0-4-amd64-di Architecture: amd64 @@ -592,8 +592,8 @@ Depends: kernel-image-3.2.0-4-amd64-di, usb-modules-3.2.0-4-amd64-di Description: Input devices support This package contains input device drivers for the kernel. -Kernel-Version: 3.2.0-4-amd64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-amd64 Package: event-modules-3.2.0-4-amd64-di Architecture: amd64 @@ -603,8 +603,8 @@ Depends: kernel-image-3.2.0-4-amd64-di Description: Event support This package contains event drivers for the kernel. -Kernel-Version: 3.2.0-4-amd64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-amd64 Package: mouse-modules-3.2.0-4-amd64-di Architecture: amd64 @@ -614,8 +614,8 @@ Depends: kernel-image-3.2.0-4-amd64-di, event-modules-3.2.0-4-amd64-di, input-modules-3.2.0-4-amd64-di, usb-modules-3.2.0-4-amd64-di Description: Mouse support This package contains mouse drivers for the kernel. -Kernel-Version: 3.2.0-4-amd64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-amd64 Package: irda-modules-3.2.0-4-amd64-di Architecture: amd64 @@ -625,8 +625,8 @@ Depends: kernel-image-3.2.0-4-amd64-di, ppp-modules-3.2.0-4-amd64-di, usb-modules-3.2.0-4-amd64-di Description: Infrared devices support This package contains infrared device drivers for the kernel. -Kernel-Version: 3.2.0-4-amd64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-amd64 Package: parport-modules-3.2.0-4-amd64-di Architecture: amd64 @@ -636,8 +636,8 @@ Depends: kernel-image-3.2.0-4-amd64-di Description: Parallel port support This package contains parallel port drivers for the kernel. -Kernel-Version: 3.2.0-4-amd64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-amd64 Package: nic-pcmcia-modules-3.2.0-4-amd64-di Architecture: amd64 @@ -647,8 +647,8 @@ Depends: kernel-image-3.2.0-4-amd64-di, nic-shared-modules-3.2.0-4-amd64-di, nic-wireless-modules-3.2.0-4-amd64-di, pcmcia-modules-3.2.0-4-amd64-di, mmc-core-modules-3.2.0-4-amd64-di Description: Common PCMCIA NIC drivers This package contains common PCMCIA NIC drivers for the kernel. -Kernel-Version: 3.2.0-4-amd64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-amd64 Package: pcmcia-modules-3.2.0-4-amd64-di Architecture: amd64 @@ -658,8 +658,8 @@ Depends: kernel-image-3.2.0-4-amd64-di, core-modules-3.2.0-4-amd64-di Description: Common PCMCIA drivers This package contains common PCMCIA drivers for the kernel. -Kernel-Version: 3.2.0-4-amd64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-amd64 Package: nic-usb-modules-3.2.0-4-amd64-di Architecture: amd64 @@ -669,8 +669,8 @@ Depends: kernel-image-3.2.0-4-amd64-di, nic-shared-modules-3.2.0-4-amd64-di, nic-wireless-modules-3.2.0-4-amd64-di, usb-modules-3.2.0-4-amd64-di, core-modules-3.2.0-4-amd64-di Description: USB NIC drivers This package contains USB network adapter drivers for the kernel. -Kernel-Version: 3.2.0-4-amd64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-amd64 Package: sata-modules-3.2.0-4-amd64-di Architecture: amd64 @@ -680,8 +680,8 @@ Depends: kernel-image-3.2.0-4-amd64-di, scsi-core-modules-3.2.0-4-amd64-di, ata-modules-3.2.0-4-amd64-di Description: SATA drivers This package contains SATA drivers for the kernel. -Kernel-Version: 3.2.0-4-amd64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-amd64 Package: core-modules-3.2.0-4-amd64-di Architecture: amd64 @@ -692,8 +692,8 @@ Description: Core modules This package contains core modules for the kernel, that will almost always be needed. -Kernel-Version: 3.2.0-4-amd64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-amd64 Package: acpi-modules-3.2.0-4-amd64-di Architecture: amd64 @@ -703,8 +703,8 @@ Depends: kernel-image-3.2.0-4-amd64-di Description: ACPI support modules This package contains kernel modules for ACPI. -Kernel-Version: 3.2.0-4-amd64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-amd64 Package: i2c-modules-3.2.0-4-amd64-di Architecture: amd64 @@ -714,8 +714,8 @@ Depends: kernel-image-3.2.0-4-amd64-di Description: i2c support modules This package contains basic i2c support modules. -Kernel-Version: 3.2.0-4-amd64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-amd64 Package: crc-modules-3.2.0-4-amd64-di Architecture: amd64 @@ -725,8 +725,8 @@ Depends: kernel-image-3.2.0-4-amd64-di Description: CRC modules This package contains CRC support modules. -Kernel-Version: 3.2.0-4-amd64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-amd64 Package: crypto-modules-3.2.0-4-amd64-di Architecture: amd64 @@ -736,8 +736,8 @@ Depends: kernel-image-3.2.0-4-amd64-di Description: crypto modules This package contains crypto modules. -Kernel-Version: 3.2.0-4-amd64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-amd64 Package: crypto-dm-modules-3.2.0-4-amd64-di Architecture: amd64 @@ -747,8 +747,8 @@ Depends: kernel-image-3.2.0-4-amd64-di, md-modules-3.2.0-4-amd64-di Description: devicemapper crypto module This package contains the devicemapper crypto (dm-crypt) module. -Kernel-Version: 3.2.0-4-amd64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-amd64 Package: efi-modules-3.2.0-4-amd64-di Architecture: amd64 @@ -758,8 +758,8 @@ Depends: kernel-image-3.2.0-4-amd64-di Description: EFI modules This package contains EFI modules. -Kernel-Version: 3.2.0-4-amd64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-amd64 Package: ata-modules-3.2.0-4-amd64-di Architecture: amd64 @@ -770,8 +770,8 @@ Description: ATA disk modules This package contains core ATA disk modules used by both PATA and SATA disk drivers. -Kernel-Version: 3.2.0-4-amd64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-amd64 Package: mmc-core-modules-3.2.0-4-amd64-di Architecture: amd64 @@ -781,8 +781,8 @@ Depends: kernel-image-3.2.0-4-amd64-di, core-modules-3.2.0-4-amd64-di Description: MMC/SD/SDIO core modules This package contains core modules for MMC/SD/SDIO support. -Kernel-Version: 3.2.0-4-amd64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-amd64 Package: mmc-modules-3.2.0-4-amd64-di Architecture: amd64 @@ -793,8 +793,8 @@ Description: MMC/SD card modules This package contains modules needed to support MMC (multimedia) and SD cards. -Kernel-Version: 3.2.0-4-amd64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-amd64 Package: nbd-modules-3.2.0-4-amd64-di Architecture: amd64 @@ -805,8 +805,8 @@ Description: Network Block Device modules This package contains the modules required for support of the Network Block Device -Kernel-Version: 3.2.0-4-amd64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-amd64 Package: squashfs-modules-3.2.0-4-amd64-di Architecture: amd64 @@ -816,8 +816,8 @@ Depends: kernel-image-3.2.0-4-amd64-di Description: squashfs modules This package contains squashfs modules. -Kernel-Version: 3.2.0-4-amd64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-amd64 Package: speakup-modules-3.2.0-4-amd64-di Architecture: amd64 @@ -827,8 +827,8 @@ Depends: kernel-image-3.2.0-4-amd64-di Description: speakup modules This package contains speakup modules. -Kernel-Version: 3.2.0-4-amd64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-amd64 Package: virtio-modules-3.2.0-4-amd64-di Architecture: amd64 @@ -838,8 +838,8 @@ Depends: kernel-image-3.2.0-4-amd64-di Description: virtio modules This package contains virtio modules. -Kernel-Version: 3.2.0-4-amd64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-amd64 Package: uinput-modules-3.2.0-4-amd64-di Architecture: amd64 @@ -849,8 +849,8 @@ Depends: kernel-image-3.2.0-4-amd64-di Description: uinput support This package contains the uinput module. -Kernel-Version: 3.2.0-4-amd64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-amd64 Package: sound-modules-3.2.0-4-amd64-di Architecture: amd64 @@ -860,8 +860,8 @@ Depends: kernel-image-3.2.0-4-amd64-di, core-modules-3.2.0-4-amd64-di, i2c-modules-3.2.0-4-amd64-di, usb-modules-3.2.0-4-amd64-di, pcmcia-modules-3.2.0-4-amd64-di, firewire-core-modules-3.2.0-4-amd64-di, crc-modules-3.2.0-4-amd64-di Description: sound support This package contains sound modules. -Kernel-Version: 3.2.0-4-amd64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-amd64 Package: zlib-modules-3.2.0-4-amd64-di Architecture: amd64 @@ -871,8 +871,8 @@ Depends: kernel-image-3.2.0-4-amd64-di Description: zlib modules This package contains zlib modules. -Kernel-Version: 3.2.0-4-amd64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-amd64 Package: hyperv-modules-3.2.0-4-amd64-di Architecture: amd64 @@ -882,8 +882,8 @@ Depends: kernel-image-3.2.0-4-amd64-di, input-modules-3.2.0-4-amd64-di, scsi-core-modules-3.2.0-4-amd64-di Description: Hyper-V modules This package contains Hyper-V paravirtualised drivers for the kernel. -Kernel-Version: 3.2.0-4-amd64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-amd64 Package: udf-modules-3.2.0-4-amd64-di Architecture: amd64 @@ -893,8 +893,8 @@ Depends: kernel-image-3.2.0-4-amd64-di, crc-modules-3.2.0-4-amd64-di Description: UDF modules This package contains the UDF filesystem module. -Kernel-Version: 3.2.0-4-amd64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-amd64 Package: fuse-modules-3.2.0-4-amd64-di Architecture: amd64 @@ -904,8 +904,8 @@ Depends: kernel-image-3.2.0-4-amd64-di Description: FUSE modules This package contains the Filesystem in Userspace (FUSE) module. -Kernel-Version: 3.2.0-4-amd64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-amd64 Package: linux-image-3.2.0-4-amd64 Architecture: amd64 i386 @@ -1011,8 +1011,8 @@ This package contains the kernel image for the Debian installer boot images. It does _not_ provide a usable kernel for your full Debian system. -Kernel-Version: 3.2.0-4-iop32x -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-iop32x Package: nic-modules-3.2.0-4-iop32x-di Architecture: armel @@ -1022,8 +1022,8 @@ Depends: kernel-image-3.2.0-4-iop32x-di, nic-shared-modules-3.2.0-4-iop32x-di, core-modules-3.2.0-4-iop32x-di Description: Common NIC drivers This package contains common NIC drivers for the kernel. -Kernel-Version: 3.2.0-4-iop32x -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-iop32x Package: nic-shared-modules-3.2.0-4-iop32x-di Architecture: armel @@ -1034,8 +1034,8 @@ Description: Shared NIC drivers This package contains NIC drivers needed by combinations of nic-modules, nic-extra-modules, nic-pcmcia-modules, and nic-wireless-modules. -Kernel-Version: 3.2.0-4-iop32x -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-iop32x Package: usb-serial-modules-3.2.0-4-iop32x-di Architecture: armel @@ -1045,8 +1045,8 @@ Depends: kernel-image-3.2.0-4-iop32x-di, usb-modules-3.2.0-4-iop32x-di Description: USB serial drivers This package contains USB serial drivers for the kernel. -Kernel-Version: 3.2.0-4-iop32x -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-iop32x Package: ppp-modules-3.2.0-4-iop32x-di Architecture: armel @@ -1056,8 +1056,8 @@ Depends: kernel-image-3.2.0-4-iop32x-di, zlib-modules-3.2.0-4-iop32x-di, crc-modules-3.2.0-4-iop32x-di Description: PPP drivers This package contains PPP drivers for the kernel. -Kernel-Version: 3.2.0-4-iop32x -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-iop32x Package: pata-modules-3.2.0-4-iop32x-di Architecture: armel @@ -1067,8 +1067,8 @@ Depends: kernel-image-3.2.0-4-iop32x-di, ata-modules-3.2.0-4-iop32x-di Description: PATA drivers This package contains PATA drivers for the kernel. -Kernel-Version: 3.2.0-4-iop32x -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-iop32x Package: cdrom-core-modules-3.2.0-4-iop32x-di Architecture: armel @@ -1078,8 +1078,8 @@ Depends: kernel-image-3.2.0-4-iop32x-di, scsi-core-modules-3.2.0-4-iop32x-di, isofs-modules-3.2.0-4-iop32x-di Description: CDROM support This package contains core CDROM support for the kernel. -Kernel-Version: 3.2.0-4-iop32x -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-iop32x Package: scsi-core-modules-3.2.0-4-iop32x-di Architecture: armel @@ -1089,8 +1089,8 @@ Depends: kernel-image-3.2.0-4-iop32x-di Description: Core SCSI subsystem This package contains the core SCSI subsystem for the kernel. -Kernel-Version: 3.2.0-4-iop32x -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-iop32x Package: loop-modules-3.2.0-4-iop32x-di Architecture: armel @@ -1100,8 +1100,8 @@ Depends: kernel-image-3.2.0-4-iop32x-di Description: Loopback filesystem support This package contains loopback filesystem support for the kernel. -Kernel-Version: 3.2.0-4-iop32x -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-iop32x Package: ipv6-modules-3.2.0-4-iop32x-di Architecture: armel @@ -1111,8 +1111,8 @@ Depends: kernel-image-3.2.0-4-iop32x-di Description: IPv6 driver This package contains the IPv6 driver for the kernel. -Kernel-Version: 3.2.0-4-iop32x -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-iop32x Package: btrfs-modules-3.2.0-4-iop32x-di Architecture: armel @@ -1122,8 +1122,8 @@ Depends: kernel-image-3.2.0-4-iop32x-di, core-modules-3.2.0-4-iop32x-di, crc-modules-3.2.0-4-iop32x-di, zlib-modules-3.2.0-4-iop32x-di Description: BTRFS filesystem support This package contains the BTRFS filesystem module for the kernel. -Kernel-Version: 3.2.0-4-iop32x -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-iop32x Package: ext2-modules-3.2.0-4-iop32x-di Architecture: armel @@ -1133,8 +1133,8 @@ Depends: kernel-image-3.2.0-4-iop32x-di, core-modules-3.2.0-4-iop32x-di Description: EXT2 filesystem support This package contains the EXT2 filesystem module for the kernel. -Kernel-Version: 3.2.0-4-iop32x -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-iop32x Package: ext3-modules-3.2.0-4-iop32x-di Architecture: armel @@ -1144,8 +1144,8 @@ Depends: kernel-image-3.2.0-4-iop32x-di, core-modules-3.2.0-4-iop32x-di Description: EXT3 filesystem support This package contains the EXT3 filesystem module for the kernel. -Kernel-Version: 3.2.0-4-iop32x -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-iop32x Package: ext4-modules-3.2.0-4-iop32x-di Architecture: armel @@ -1155,8 +1155,8 @@ Depends: kernel-image-3.2.0-4-iop32x-di, core-modules-3.2.0-4-iop32x-di Description: EXT4 filesystem support This package contains the EXT4 filesystem module for the kernel. -Kernel-Version: 3.2.0-4-iop32x -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-iop32x Package: isofs-modules-3.2.0-4-iop32x-di Architecture: armel @@ -1166,8 +1166,8 @@ Depends: kernel-image-3.2.0-4-iop32x-di Description: ISOFS filesystem support This package contains the ISOFS filesystem module for the kernel. -Kernel-Version: 3.2.0-4-iop32x -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-iop32x Package: jffs2-modules-3.2.0-4-iop32x-di Architecture: armel @@ -1177,8 +1177,8 @@ Depends: kernel-image-3.2.0-4-iop32x-di, zlib-modules-3.2.0-4-iop32x-di Description: JFFS2 filesystem support This package contains the JFFS2 filesystem module for the kernel. -Kernel-Version: 3.2.0-4-iop32x -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-iop32x Package: jfs-modules-3.2.0-4-iop32x-di Architecture: armel @@ -1188,8 +1188,8 @@ Depends: kernel-image-3.2.0-4-iop32x-di Description: JFS filesystem support This package contains the JFS filesystem module for the kernel. -Kernel-Version: 3.2.0-4-iop32x -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-iop32x Package: reiserfs-modules-3.2.0-4-iop32x-di Architecture: armel @@ -1199,8 +1199,8 @@ Depends: kernel-image-3.2.0-4-iop32x-di Description: Reiser filesystem support This package contains the Reiser filesystem module for the kernel. -Kernel-Version: 3.2.0-4-iop32x -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-iop32x Package: fat-modules-3.2.0-4-iop32x-di Architecture: armel @@ -1210,8 +1210,8 @@ Depends: kernel-image-3.2.0-4-iop32x-di Description: FAT filesystem support This package contains the FAT and VFAT filesystem modules for the kernel. -Kernel-Version: 3.2.0-4-iop32x -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-iop32x Package: md-modules-3.2.0-4-iop32x-di Architecture: armel @@ -1221,8 +1221,8 @@ Depends: kernel-image-3.2.0-4-iop32x-di Description: RAID and LVM support This package contains RAID and LVM modules for the kernel. -Kernel-Version: 3.2.0-4-iop32x -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-iop32x Package: multipath-modules-3.2.0-4-iop32x-di Architecture: armel @@ -1232,8 +1232,8 @@ Depends: kernel-image-3.2.0-4-iop32x-di, md-modules-3.2.0-4-iop32x-di, scsi-core-modules-3.2.0-4-iop32x-di Description: Multipath support This package contains DM-Multipath modules for the kernel. -Kernel-Version: 3.2.0-4-iop32x -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-iop32x Package: usb-modules-3.2.0-4-iop32x-di Architecture: armel @@ -1243,8 +1243,8 @@ Depends: kernel-image-3.2.0-4-iop32x-di Description: USB support This package contains core USB drivers for the kernel. -Kernel-Version: 3.2.0-4-iop32x -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-iop32x Package: usb-storage-modules-3.2.0-4-iop32x-di Architecture: armel @@ -1254,8 +1254,8 @@ Depends: kernel-image-3.2.0-4-iop32x-di, scsi-core-modules-3.2.0-4-iop32x-di, usb-modules-3.2.0-4-iop32x-di Description: USB storage support This package contains the USB storage driver for the kernel. -Kernel-Version: 3.2.0-4-iop32x -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-iop32x Package: event-modules-3.2.0-4-iop32x-di Architecture: armel @@ -1265,8 +1265,8 @@ Depends: kernel-image-3.2.0-4-iop32x-di Description: Event support This package contains event drivers for the kernel. -Kernel-Version: 3.2.0-4-iop32x -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-iop32x Package: nic-usb-modules-3.2.0-4-iop32x-di Architecture: armel @@ -1276,8 +1276,8 @@ Depends: kernel-image-3.2.0-4-iop32x-di, nic-shared-modules-3.2.0-4-iop32x-di, usb-modules-3.2.0-4-iop32x-di, core-modules-3.2.0-4-iop32x-di Description: USB NIC drivers This package contains USB network adapter drivers for the kernel. -Kernel-Version: 3.2.0-4-iop32x -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-iop32x Package: sata-modules-3.2.0-4-iop32x-di Architecture: armel @@ -1287,8 +1287,8 @@ Depends: kernel-image-3.2.0-4-iop32x-di, scsi-core-modules-3.2.0-4-iop32x-di, ata-modules-3.2.0-4-iop32x-di Description: SATA drivers This package contains SATA drivers for the kernel. -Kernel-Version: 3.2.0-4-iop32x -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-iop32x Package: core-modules-3.2.0-4-iop32x-di Architecture: armel @@ -1299,8 +1299,8 @@ Description: Core modules This package contains core modules for the kernel, that will almost always be needed. -Kernel-Version: 3.2.0-4-iop32x -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-iop32x Package: crc-modules-3.2.0-4-iop32x-di Architecture: armel @@ -1310,8 +1310,8 @@ Depends: kernel-image-3.2.0-4-iop32x-di Description: CRC modules This package contains CRC support modules. -Kernel-Version: 3.2.0-4-iop32x -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-iop32x Package: crypto-modules-3.2.0-4-iop32x-di Architecture: armel @@ -1321,8 +1321,8 @@ Depends: kernel-image-3.2.0-4-iop32x-di Description: crypto modules This package contains crypto modules. -Kernel-Version: 3.2.0-4-iop32x -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-iop32x Package: crypto-dm-modules-3.2.0-4-iop32x-di Architecture: armel @@ -1332,8 +1332,8 @@ Depends: kernel-image-3.2.0-4-iop32x-di, md-modules-3.2.0-4-iop32x-di Description: devicemapper crypto module This package contains the devicemapper crypto (dm-crypt) module. -Kernel-Version: 3.2.0-4-iop32x -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-iop32x Package: ata-modules-3.2.0-4-iop32x-di Architecture: armel @@ -1344,8 +1344,8 @@ Description: ATA disk modules This package contains core ATA disk modules used by both PATA and SATA disk drivers. -Kernel-Version: 3.2.0-4-iop32x -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-iop32x Package: nbd-modules-3.2.0-4-iop32x-di Architecture: armel @@ -1356,8 +1356,8 @@ Description: Network Block Device modules This package contains the modules required for support of the Network Block Device -Kernel-Version: 3.2.0-4-iop32x -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-iop32x Package: squashfs-modules-3.2.0-4-iop32x-di Architecture: armel @@ -1367,8 +1367,8 @@ Depends: kernel-image-3.2.0-4-iop32x-di Description: squashfs modules This package contains squashfs modules. -Kernel-Version: 3.2.0-4-iop32x -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-iop32x Package: zlib-modules-3.2.0-4-iop32x-di Architecture: armel @@ -1378,8 +1378,8 @@ Depends: kernel-image-3.2.0-4-iop32x-di Description: zlib modules This package contains zlib modules. -Kernel-Version: 3.2.0-4-iop32x -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-iop32x Package: udf-modules-3.2.0-4-iop32x-di Architecture: armel @@ -1389,8 +1389,8 @@ Depends: kernel-image-3.2.0-4-iop32x-di, crc-modules-3.2.0-4-iop32x-di Description: UDF modules This package contains the UDF filesystem module. -Kernel-Version: 3.2.0-4-iop32x -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-iop32x Package: fuse-modules-3.2.0-4-iop32x-di Architecture: armel @@ -1400,8 +1400,8 @@ Depends: kernel-image-3.2.0-4-iop32x-di Description: FUSE modules This package contains the Filesystem in Userspace (FUSE) module. -Kernel-Version: 3.2.0-4-iop32x -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-iop32x Package: kernel-image-3.2.0-4-kirkwood-di Architecture: armel @@ -1412,8 +1412,8 @@ This package contains the kernel image for the Debian installer boot images. It does _not_ provide a usable kernel for your full Debian system. -Kernel-Version: 3.2.0-4-kirkwood -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-kirkwood Package: nic-modules-3.2.0-4-kirkwood-di Architecture: armel @@ -1423,8 +1423,8 @@ Depends: kernel-image-3.2.0-4-kirkwood-di, nic-shared-modules-3.2.0-4-kirkwood-di, core-modules-3.2.0-4-kirkwood-di Description: Common NIC drivers This package contains common NIC drivers for the kernel. -Kernel-Version: 3.2.0-4-kirkwood -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-kirkwood Package: nic-shared-modules-3.2.0-4-kirkwood-di Architecture: armel @@ -1435,8 +1435,8 @@ Description: Shared NIC drivers This package contains NIC drivers needed by combinations of nic-modules, nic-extra-modules, nic-pcmcia-modules, and nic-wireless-modules. -Kernel-Version: 3.2.0-4-kirkwood -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-kirkwood Package: usb-serial-modules-3.2.0-4-kirkwood-di Architecture: armel @@ -1446,8 +1446,8 @@ Depends: kernel-image-3.2.0-4-kirkwood-di, usb-modules-3.2.0-4-kirkwood-di Description: USB serial drivers This package contains USB serial drivers for the kernel. -Kernel-Version: 3.2.0-4-kirkwood -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-kirkwood Package: ppp-modules-3.2.0-4-kirkwood-di Architecture: armel @@ -1457,8 +1457,8 @@ Depends: kernel-image-3.2.0-4-kirkwood-di, crc-modules-3.2.0-4-kirkwood-di Description: PPP drivers This package contains PPP drivers for the kernel. -Kernel-Version: 3.2.0-4-kirkwood -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-kirkwood Package: cdrom-core-modules-3.2.0-4-kirkwood-di Architecture: armel @@ -1468,8 +1468,8 @@ Depends: kernel-image-3.2.0-4-kirkwood-di, scsi-core-modules-3.2.0-4-kirkwood-di, isofs-modules-3.2.0-4-kirkwood-di Description: CDROM support This package contains core CDROM support for the kernel. -Kernel-Version: 3.2.0-4-kirkwood -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-kirkwood Package: scsi-core-modules-3.2.0-4-kirkwood-di Architecture: armel @@ -1479,8 +1479,8 @@ Depends: kernel-image-3.2.0-4-kirkwood-di Description: Core SCSI subsystem This package contains the core SCSI subsystem for the kernel. -Kernel-Version: 3.2.0-4-kirkwood -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-kirkwood Package: loop-modules-3.2.0-4-kirkwood-di Architecture: armel @@ -1490,8 +1490,8 @@ Depends: kernel-image-3.2.0-4-kirkwood-di Description: Loopback filesystem support This package contains loopback filesystem support for the kernel. -Kernel-Version: 3.2.0-4-kirkwood -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-kirkwood Package: ipv6-modules-3.2.0-4-kirkwood-di Architecture: armel @@ -1501,8 +1501,8 @@ Depends: kernel-image-3.2.0-4-kirkwood-di Description: IPv6 driver This package contains the IPv6 driver for the kernel. -Kernel-Version: 3.2.0-4-kirkwood -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-kirkwood Package: btrfs-modules-3.2.0-4-kirkwood-di Architecture: armel @@ -1512,8 +1512,8 @@ Depends: kernel-image-3.2.0-4-kirkwood-di, core-modules-3.2.0-4-kirkwood-di, crc-modules-3.2.0-4-kirkwood-di Description: BTRFS filesystem support This package contains the BTRFS filesystem module for the kernel. -Kernel-Version: 3.2.0-4-kirkwood -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-kirkwood Package: ext2-modules-3.2.0-4-kirkwood-di Architecture: armel @@ -1523,8 +1523,8 @@ Depends: kernel-image-3.2.0-4-kirkwood-di, core-modules-3.2.0-4-kirkwood-di Description: EXT2 filesystem support This package contains the EXT2 filesystem module for the kernel. -Kernel-Version: 3.2.0-4-kirkwood -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-kirkwood Package: ext3-modules-3.2.0-4-kirkwood-di Architecture: armel @@ -1534,8 +1534,8 @@ Depends: kernel-image-3.2.0-4-kirkwood-di, core-modules-3.2.0-4-kirkwood-di Description: EXT3 filesystem support This package contains the EXT3 filesystem module for the kernel. -Kernel-Version: 3.2.0-4-kirkwood -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-kirkwood Package: ext4-modules-3.2.0-4-kirkwood-di Architecture: armel @@ -1545,8 +1545,8 @@ Depends: kernel-image-3.2.0-4-kirkwood-di, core-modules-3.2.0-4-kirkwood-di Description: EXT4 filesystem support This package contains the EXT4 filesystem module for the kernel. -Kernel-Version: 3.2.0-4-kirkwood -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-kirkwood Package: isofs-modules-3.2.0-4-kirkwood-di Architecture: armel @@ -1556,8 +1556,8 @@ Depends: kernel-image-3.2.0-4-kirkwood-di Description: ISOFS filesystem support This package contains the ISOFS filesystem module for the kernel. -Kernel-Version: 3.2.0-4-kirkwood -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-kirkwood Package: jfs-modules-3.2.0-4-kirkwood-di Architecture: armel @@ -1567,8 +1567,8 @@ Depends: kernel-image-3.2.0-4-kirkwood-di Description: JFS filesystem support This package contains the JFS filesystem module for the kernel. -Kernel-Version: 3.2.0-4-kirkwood -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-kirkwood Package: reiserfs-modules-3.2.0-4-kirkwood-di Architecture: armel @@ -1578,8 +1578,8 @@ Depends: kernel-image-3.2.0-4-kirkwood-di Description: Reiser filesystem support This package contains the Reiser filesystem module for the kernel. -Kernel-Version: 3.2.0-4-kirkwood -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-kirkwood Package: fat-modules-3.2.0-4-kirkwood-di Architecture: armel @@ -1589,8 +1589,8 @@ Depends: kernel-image-3.2.0-4-kirkwood-di Description: FAT filesystem support This package contains the FAT and VFAT filesystem modules for the kernel. -Kernel-Version: 3.2.0-4-kirkwood -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-kirkwood Package: minix-modules-3.2.0-4-kirkwood-di Architecture: armel @@ -1600,8 +1600,8 @@ Depends: kernel-image-3.2.0-4-kirkwood-di Description: Minix filesystem support This package contains the Minix filesystem module for the kernel. -Kernel-Version: 3.2.0-4-kirkwood -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-kirkwood Package: md-modules-3.2.0-4-kirkwood-di Architecture: armel @@ -1611,8 +1611,8 @@ Depends: kernel-image-3.2.0-4-kirkwood-di Description: RAID and LVM support This package contains RAID and LVM modules for the kernel. -Kernel-Version: 3.2.0-4-kirkwood -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-kirkwood Package: multipath-modules-3.2.0-4-kirkwood-di Architecture: armel @@ -1622,8 +1622,8 @@ Depends: kernel-image-3.2.0-4-kirkwood-di, md-modules-3.2.0-4-kirkwood-di, scsi-core-modules-3.2.0-4-kirkwood-di Description: Multipath support This package contains DM-Multipath modules for the kernel. -Kernel-Version: 3.2.0-4-kirkwood -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-kirkwood Package: usb-modules-3.2.0-4-kirkwood-di Architecture: armel @@ -1633,8 +1633,8 @@ Depends: kernel-image-3.2.0-4-kirkwood-di Description: USB support This package contains core USB drivers for the kernel. -Kernel-Version: 3.2.0-4-kirkwood -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-kirkwood Package: usb-storage-modules-3.2.0-4-kirkwood-di Architecture: armel @@ -1644,8 +1644,8 @@ Depends: kernel-image-3.2.0-4-kirkwood-di, scsi-core-modules-3.2.0-4-kirkwood-di, usb-modules-3.2.0-4-kirkwood-di Description: USB storage support This package contains the USB storage driver for the kernel. -Kernel-Version: 3.2.0-4-kirkwood -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-kirkwood Package: fb-modules-3.2.0-4-kirkwood-di Architecture: armel @@ -1655,8 +1655,8 @@ Depends: kernel-image-3.2.0-4-kirkwood-di, usb-modules-3.2.0-4-kirkwood-di Description: Frame buffer support This package contains Frame buffer drivers for the kernel. -Kernel-Version: 3.2.0-4-kirkwood -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-kirkwood Package: input-modules-3.2.0-4-kirkwood-di Architecture: armel @@ -1666,8 +1666,8 @@ Depends: kernel-image-3.2.0-4-kirkwood-di, usb-modules-3.2.0-4-kirkwood-di Description: Input devices support This package contains input device drivers for the kernel. -Kernel-Version: 3.2.0-4-kirkwood -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-kirkwood Package: event-modules-3.2.0-4-kirkwood-di Architecture: armel @@ -1677,8 +1677,8 @@ Depends: kernel-image-3.2.0-4-kirkwood-di Description: Event support This package contains event drivers for the kernel. -Kernel-Version: 3.2.0-4-kirkwood -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-kirkwood Package: mouse-modules-3.2.0-4-kirkwood-di Architecture: armel @@ -1688,8 +1688,8 @@ Depends: kernel-image-3.2.0-4-kirkwood-di, event-modules-3.2.0-4-kirkwood-di, input-modules-3.2.0-4-kirkwood-di, usb-modules-3.2.0-4-kirkwood-di Description: Mouse support This package contains mouse drivers for the kernel. -Kernel-Version: 3.2.0-4-kirkwood -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-kirkwood Package: nic-usb-modules-3.2.0-4-kirkwood-di Architecture: armel @@ -1699,8 +1699,8 @@ Depends: kernel-image-3.2.0-4-kirkwood-di, nic-shared-modules-3.2.0-4-kirkwood-di, usb-modules-3.2.0-4-kirkwood-di, core-modules-3.2.0-4-kirkwood-di Description: USB NIC drivers This package contains USB network adapter drivers for the kernel. -Kernel-Version: 3.2.0-4-kirkwood -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-kirkwood Package: sata-modules-3.2.0-4-kirkwood-di Architecture: armel @@ -1710,8 +1710,8 @@ Depends: kernel-image-3.2.0-4-kirkwood-di, scsi-core-modules-3.2.0-4-kirkwood-di Description: SATA drivers This package contains SATA drivers for the kernel. -Kernel-Version: 3.2.0-4-kirkwood -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-kirkwood Package: core-modules-3.2.0-4-kirkwood-di Architecture: armel @@ -1722,8 +1722,8 @@ Description: Core modules This package contains core modules for the kernel, that will almost always be needed. -Kernel-Version: 3.2.0-4-kirkwood -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-kirkwood Package: crc-modules-3.2.0-4-kirkwood-di Architecture: armel @@ -1733,8 +1733,8 @@ Depends: kernel-image-3.2.0-4-kirkwood-di Description: CRC modules This package contains CRC support modules. -Kernel-Version: 3.2.0-4-kirkwood -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-kirkwood Package: crypto-modules-3.2.0-4-kirkwood-di Architecture: armel @@ -1744,8 +1744,8 @@ Depends: kernel-image-3.2.0-4-kirkwood-di Description: crypto modules This package contains crypto modules. -Kernel-Version: 3.2.0-4-kirkwood -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-kirkwood Package: crypto-dm-modules-3.2.0-4-kirkwood-di Architecture: armel @@ -1755,8 +1755,8 @@ Depends: kernel-image-3.2.0-4-kirkwood-di, md-modules-3.2.0-4-kirkwood-di Description: devicemapper crypto module This package contains the devicemapper crypto (dm-crypt) module. -Kernel-Version: 3.2.0-4-kirkwood -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-kirkwood Package: mmc-modules-3.2.0-4-kirkwood-di Architecture: armel @@ -1767,8 +1767,8 @@ Description: MMC/SD card modules This package contains modules needed to support MMC (multimedia) and SD cards. -Kernel-Version: 3.2.0-4-kirkwood -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-kirkwood Package: nbd-modules-3.2.0-4-kirkwood-di Architecture: armel @@ -1779,8 +1779,8 @@ Description: Network Block Device modules This package contains the modules required for support of the Network Block Device -Kernel-Version: 3.2.0-4-kirkwood -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-kirkwood Package: squashfs-modules-3.2.0-4-kirkwood-di Architecture: armel @@ -1790,8 +1790,8 @@ Depends: kernel-image-3.2.0-4-kirkwood-di Description: squashfs modules This package contains squashfs modules. -Kernel-Version: 3.2.0-4-kirkwood -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-kirkwood Package: uinput-modules-3.2.0-4-kirkwood-di Architecture: armel @@ -1801,8 +1801,8 @@ Depends: kernel-image-3.2.0-4-kirkwood-di Description: uinput support This package contains the uinput module. -Kernel-Version: 3.2.0-4-kirkwood -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-kirkwood Package: leds-modules-3.2.0-4-kirkwood-di Architecture: armel @@ -1812,8 +1812,8 @@ Depends: kernel-image-3.2.0-4-kirkwood-di Description: LED modules This package contains LED modules. -Kernel-Version: 3.2.0-4-kirkwood -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-kirkwood Package: udf-modules-3.2.0-4-kirkwood-di Architecture: armel @@ -1823,8 +1823,8 @@ Depends: kernel-image-3.2.0-4-kirkwood-di, crc-modules-3.2.0-4-kirkwood-di Description: UDF modules This package contains the UDF filesystem module. -Kernel-Version: 3.2.0-4-kirkwood -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-kirkwood Package: fuse-modules-3.2.0-4-kirkwood-di Architecture: armel @@ -1834,8 +1834,8 @@ Depends: kernel-image-3.2.0-4-kirkwood-di Description: FUSE modules This package contains the Filesystem in Userspace (FUSE) module. -Kernel-Version: 3.2.0-4-kirkwood -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-kirkwood Package: kernel-image-3.2.0-4-orion5x-di Architecture: armel @@ -1846,8 +1846,8 @@ This package contains the kernel image for the Debian installer boot images. It does _not_ provide a usable kernel for your full Debian system. -Kernel-Version: 3.2.0-4-orion5x -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-orion5x Package: nic-modules-3.2.0-4-orion5x-di Architecture: armel @@ -1857,8 +1857,8 @@ Depends: kernel-image-3.2.0-4-orion5x-di, nic-shared-modules-3.2.0-4-orion5x-di, core-modules-3.2.0-4-orion5x-di Description: Common NIC drivers This package contains common NIC drivers for the kernel. -Kernel-Version: 3.2.0-4-orion5x -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-orion5x Package: nic-shared-modules-3.2.0-4-orion5x-di Architecture: armel @@ -1869,8 +1869,8 @@ Description: Shared NIC drivers This package contains NIC drivers needed by combinations of nic-modules, nic-extra-modules, nic-pcmcia-modules, and nic-wireless-modules. -Kernel-Version: 3.2.0-4-orion5x -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-orion5x Package: usb-serial-modules-3.2.0-4-orion5x-di Architecture: armel @@ -1880,8 +1880,8 @@ Depends: kernel-image-3.2.0-4-orion5x-di, usb-modules-3.2.0-4-orion5x-di Description: USB serial drivers This package contains USB serial drivers for the kernel. -Kernel-Version: 3.2.0-4-orion5x -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-orion5x Package: ppp-modules-3.2.0-4-orion5x-di Architecture: armel @@ -1891,8 +1891,8 @@ Depends: kernel-image-3.2.0-4-orion5x-di, zlib-modules-3.2.0-4-orion5x-di, crc-modules-3.2.0-4-orion5x-di Description: PPP drivers This package contains PPP drivers for the kernel. -Kernel-Version: 3.2.0-4-orion5x -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-orion5x Package: cdrom-core-modules-3.2.0-4-orion5x-di Architecture: armel @@ -1902,8 +1902,8 @@ Depends: kernel-image-3.2.0-4-orion5x-di, scsi-core-modules-3.2.0-4-orion5x-di, isofs-modules-3.2.0-4-orion5x-di Description: CDROM support This package contains core CDROM support for the kernel. -Kernel-Version: 3.2.0-4-orion5x -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-orion5x Package: scsi-core-modules-3.2.0-4-orion5x-di Architecture: armel @@ -1913,8 +1913,8 @@ Depends: kernel-image-3.2.0-4-orion5x-di Description: Core SCSI subsystem This package contains the core SCSI subsystem for the kernel. -Kernel-Version: 3.2.0-4-orion5x -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-orion5x Package: loop-modules-3.2.0-4-orion5x-di Architecture: armel @@ -1924,8 +1924,8 @@ Depends: kernel-image-3.2.0-4-orion5x-di Description: Loopback filesystem support This package contains loopback filesystem support for the kernel. -Kernel-Version: 3.2.0-4-orion5x -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-orion5x Package: ipv6-modules-3.2.0-4-orion5x-di Architecture: armel @@ -1935,8 +1935,8 @@ Depends: kernel-image-3.2.0-4-orion5x-di Description: IPv6 driver This package contains the IPv6 driver for the kernel. -Kernel-Version: 3.2.0-4-orion5x -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-orion5x Package: btrfs-modules-3.2.0-4-orion5x-di Architecture: armel @@ -1946,8 +1946,8 @@ Depends: kernel-image-3.2.0-4-orion5x-di, core-modules-3.2.0-4-orion5x-di, crc-modules-3.2.0-4-orion5x-di, zlib-modules-3.2.0-4-orion5x-di Description: BTRFS filesystem support This package contains the BTRFS filesystem module for the kernel. -Kernel-Version: 3.2.0-4-orion5x -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-orion5x Package: ext2-modules-3.2.0-4-orion5x-di Architecture: armel @@ -1957,8 +1957,8 @@ Depends: kernel-image-3.2.0-4-orion5x-di, core-modules-3.2.0-4-orion5x-di Description: EXT2 filesystem support This package contains the EXT2 filesystem module for the kernel. -Kernel-Version: 3.2.0-4-orion5x -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-orion5x Package: ext3-modules-3.2.0-4-orion5x-di Architecture: armel @@ -1968,8 +1968,8 @@ Depends: kernel-image-3.2.0-4-orion5x-di, core-modules-3.2.0-4-orion5x-di Description: EXT3 filesystem support This package contains the EXT3 filesystem module for the kernel. -Kernel-Version: 3.2.0-4-orion5x -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-orion5x Package: ext4-modules-3.2.0-4-orion5x-di Architecture: armel @@ -1979,8 +1979,8 @@ Depends: kernel-image-3.2.0-4-orion5x-di, core-modules-3.2.0-4-orion5x-di Description: EXT4 filesystem support This package contains the EXT4 filesystem module for the kernel. -Kernel-Version: 3.2.0-4-orion5x -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-orion5x Package: isofs-modules-3.2.0-4-orion5x-di Architecture: armel @@ -1990,8 +1990,8 @@ Depends: kernel-image-3.2.0-4-orion5x-di Description: ISOFS filesystem support This package contains the ISOFS filesystem module for the kernel. -Kernel-Version: 3.2.0-4-orion5x -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-orion5x Package: jffs2-modules-3.2.0-4-orion5x-di Architecture: armel @@ -2001,8 +2001,8 @@ Depends: kernel-image-3.2.0-4-orion5x-di, zlib-modules-3.2.0-4-orion5x-di Description: JFFS2 filesystem support This package contains the JFFS2 filesystem module for the kernel. -Kernel-Version: 3.2.0-4-orion5x -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-orion5x Package: jfs-modules-3.2.0-4-orion5x-di Architecture: armel @@ -2012,8 +2012,8 @@ Depends: kernel-image-3.2.0-4-orion5x-di Description: JFS filesystem support This package contains the JFS filesystem module for the kernel. -Kernel-Version: 3.2.0-4-orion5x -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-orion5x Package: reiserfs-modules-3.2.0-4-orion5x-di Architecture: armel @@ -2023,8 +2023,8 @@ Depends: kernel-image-3.2.0-4-orion5x-di Description: Reiser filesystem support This package contains the Reiser filesystem module for the kernel. -Kernel-Version: 3.2.0-4-orion5x -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-orion5x Package: fat-modules-3.2.0-4-orion5x-di Architecture: armel @@ -2034,8 +2034,8 @@ Depends: kernel-image-3.2.0-4-orion5x-di Description: FAT filesystem support This package contains the FAT and VFAT filesystem modules for the kernel. -Kernel-Version: 3.2.0-4-orion5x -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-orion5x Package: minix-modules-3.2.0-4-orion5x-di Architecture: armel @@ -2045,8 +2045,8 @@ Depends: kernel-image-3.2.0-4-orion5x-di Description: Minix filesystem support This package contains the Minix filesystem module for the kernel. -Kernel-Version: 3.2.0-4-orion5x -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-orion5x Package: md-modules-3.2.0-4-orion5x-di Architecture: armel @@ -2056,8 +2056,8 @@ Depends: kernel-image-3.2.0-4-orion5x-di Description: RAID and LVM support This package contains RAID and LVM modules for the kernel. -Kernel-Version: 3.2.0-4-orion5x -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-orion5x Package: multipath-modules-3.2.0-4-orion5x-di Architecture: armel @@ -2067,8 +2067,8 @@ Depends: kernel-image-3.2.0-4-orion5x-di, md-modules-3.2.0-4-orion5x-di, scsi-core-modules-3.2.0-4-orion5x-di Description: Multipath support This package contains DM-Multipath modules for the kernel. -Kernel-Version: 3.2.0-4-orion5x -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-orion5x Package: usb-modules-3.2.0-4-orion5x-di Architecture: armel @@ -2078,8 +2078,8 @@ Depends: kernel-image-3.2.0-4-orion5x-di Description: USB support This package contains core USB drivers for the kernel. -Kernel-Version: 3.2.0-4-orion5x -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-orion5x Package: usb-storage-modules-3.2.0-4-orion5x-di Architecture: armel @@ -2089,8 +2089,8 @@ Depends: kernel-image-3.2.0-4-orion5x-di, scsi-core-modules-3.2.0-4-orion5x-di, usb-modules-3.2.0-4-orion5x-di Description: USB storage support This package contains the USB storage driver for the kernel. -Kernel-Version: 3.2.0-4-orion5x -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-orion5x Package: event-modules-3.2.0-4-orion5x-di Architecture: armel @@ -2100,8 +2100,8 @@ Depends: kernel-image-3.2.0-4-orion5x-di Description: Event support This package contains event drivers for the kernel. -Kernel-Version: 3.2.0-4-orion5x -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-orion5x Package: nic-usb-modules-3.2.0-4-orion5x-di Architecture: armel @@ -2111,8 +2111,8 @@ Depends: kernel-image-3.2.0-4-orion5x-di, nic-shared-modules-3.2.0-4-orion5x-di, usb-modules-3.2.0-4-orion5x-di, core-modules-3.2.0-4-orion5x-di Description: USB NIC drivers This package contains USB network adapter drivers for the kernel. -Kernel-Version: 3.2.0-4-orion5x -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-orion5x Package: sata-modules-3.2.0-4-orion5x-di Architecture: armel @@ -2122,8 +2122,8 @@ Depends: kernel-image-3.2.0-4-orion5x-di, scsi-core-modules-3.2.0-4-orion5x-di Description: SATA drivers This package contains SATA drivers for the kernel. -Kernel-Version: 3.2.0-4-orion5x -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-orion5x Package: core-modules-3.2.0-4-orion5x-di Architecture: armel @@ -2134,8 +2134,8 @@ Description: Core modules This package contains core modules for the kernel, that will almost always be needed. -Kernel-Version: 3.2.0-4-orion5x -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-orion5x Package: crc-modules-3.2.0-4-orion5x-di Architecture: armel @@ -2145,8 +2145,8 @@ Depends: kernel-image-3.2.0-4-orion5x-di Description: CRC modules This package contains CRC support modules. -Kernel-Version: 3.2.0-4-orion5x -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-orion5x Package: crypto-modules-3.2.0-4-orion5x-di Architecture: armel @@ -2156,8 +2156,8 @@ Depends: kernel-image-3.2.0-4-orion5x-di Description: crypto modules This package contains crypto modules. -Kernel-Version: 3.2.0-4-orion5x -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-orion5x Package: crypto-dm-modules-3.2.0-4-orion5x-di Architecture: armel @@ -2167,8 +2167,8 @@ Depends: kernel-image-3.2.0-4-orion5x-di, md-modules-3.2.0-4-orion5x-di Description: devicemapper crypto module This package contains the devicemapper crypto (dm-crypt) module. -Kernel-Version: 3.2.0-4-orion5x -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-orion5x Package: nbd-modules-3.2.0-4-orion5x-di Architecture: armel @@ -2179,8 +2179,8 @@ Description: Network Block Device modules This package contains the modules required for support of the Network Block Device -Kernel-Version: 3.2.0-4-orion5x -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-orion5x Package: squashfs-modules-3.2.0-4-orion5x-di Architecture: armel @@ -2190,8 +2190,8 @@ Depends: kernel-image-3.2.0-4-orion5x-di Description: squashfs modules This package contains squashfs modules. -Kernel-Version: 3.2.0-4-orion5x -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-orion5x Package: zlib-modules-3.2.0-4-orion5x-di Architecture: armel @@ -2201,8 +2201,8 @@ Depends: kernel-image-3.2.0-4-orion5x-di Description: zlib modules This package contains zlib modules. -Kernel-Version: 3.2.0-4-orion5x -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-orion5x Package: udf-modules-3.2.0-4-orion5x-di Architecture: armel @@ -2212,8 +2212,8 @@ Depends: kernel-image-3.2.0-4-orion5x-di, crc-modules-3.2.0-4-orion5x-di Description: UDF modules This package contains the UDF filesystem module. -Kernel-Version: 3.2.0-4-orion5x -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-orion5x Package: fuse-modules-3.2.0-4-orion5x-di Architecture: armel @@ -2223,8 +2223,8 @@ Depends: kernel-image-3.2.0-4-orion5x-di Description: FUSE modules This package contains the Filesystem in Userspace (FUSE) module. -Kernel-Version: 3.2.0-4-orion5x -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-orion5x Package: kernel-image-3.2.0-4-versatile-di Architecture: armel @@ -2235,8 +2235,8 @@ This package contains the kernel image for the Debian installer boot images. It does _not_ provide a usable kernel for your full Debian system. -Kernel-Version: 3.2.0-4-versatile -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-versatile Package: nic-modules-3.2.0-4-versatile-di Architecture: armel @@ -2246,8 +2246,8 @@ Depends: kernel-image-3.2.0-4-versatile-di, nic-shared-modules-3.2.0-4-versatile-di, core-modules-3.2.0-4-versatile-di Description: Common NIC drivers This package contains common NIC drivers for the kernel. -Kernel-Version: 3.2.0-4-versatile -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-versatile Package: nic-shared-modules-3.2.0-4-versatile-di Architecture: armel @@ -2258,8 +2258,8 @@ Description: Shared NIC drivers This package contains NIC drivers needed by combinations of nic-modules, nic-extra-modules, nic-pcmcia-modules, and nic-wireless-modules. -Kernel-Version: 3.2.0-4-versatile -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-versatile Package: usb-serial-modules-3.2.0-4-versatile-di Architecture: armel @@ -2269,8 +2269,8 @@ Depends: kernel-image-3.2.0-4-versatile-di, usb-modules-3.2.0-4-versatile-di Description: USB serial drivers This package contains USB serial drivers for the kernel. -Kernel-Version: 3.2.0-4-versatile -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-versatile Package: ppp-modules-3.2.0-4-versatile-di Architecture: armel @@ -2280,8 +2280,8 @@ Depends: kernel-image-3.2.0-4-versatile-di, zlib-modules-3.2.0-4-versatile-di, crc-modules-3.2.0-4-versatile-di Description: PPP drivers This package contains PPP drivers for the kernel. -Kernel-Version: 3.2.0-4-versatile -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-versatile Package: cdrom-core-modules-3.2.0-4-versatile-di Architecture: armel @@ -2291,8 +2291,8 @@ Depends: kernel-image-3.2.0-4-versatile-di, scsi-core-modules-3.2.0-4-versatile-di, isofs-modules-3.2.0-4-versatile-di Description: CDROM support This package contains core CDROM support for the kernel. -Kernel-Version: 3.2.0-4-versatile -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-versatile Package: scsi-core-modules-3.2.0-4-versatile-di Architecture: armel @@ -2302,8 +2302,8 @@ Depends: kernel-image-3.2.0-4-versatile-di Description: Core SCSI subsystem This package contains the core SCSI subsystem for the kernel. -Kernel-Version: 3.2.0-4-versatile -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-versatile Package: scsi-common-modules-3.2.0-4-versatile-di Architecture: armel @@ -2313,8 +2313,8 @@ Depends: kernel-image-3.2.0-4-versatile-di, scsi-core-modules-3.2.0-4-versatile-di, cdrom-core-modules-3.2.0-4-versatile-di Description: Very common SCSI drivers This package contains very common SCSI drivers for the kernel. -Kernel-Version: 3.2.0-4-versatile -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-versatile Package: loop-modules-3.2.0-4-versatile-di Architecture: armel @@ -2324,8 +2324,8 @@ Depends: kernel-image-3.2.0-4-versatile-di Description: Loopback filesystem support This package contains loopback filesystem support for the kernel. -Kernel-Version: 3.2.0-4-versatile -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-versatile Package: ipv6-modules-3.2.0-4-versatile-di Architecture: armel @@ -2335,8 +2335,8 @@ Depends: kernel-image-3.2.0-4-versatile-di Description: IPv6 driver This package contains the IPv6 driver for the kernel. -Kernel-Version: 3.2.0-4-versatile -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-versatile Package: btrfs-modules-3.2.0-4-versatile-di Architecture: armel @@ -2346,8 +2346,8 @@ Depends: kernel-image-3.2.0-4-versatile-di, core-modules-3.2.0-4-versatile-di, crc-modules-3.2.0-4-versatile-di, zlib-modules-3.2.0-4-versatile-di Description: BTRFS filesystem support This package contains the BTRFS filesystem module for the kernel. -Kernel-Version: 3.2.0-4-versatile -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-versatile Package: ext2-modules-3.2.0-4-versatile-di Architecture: armel @@ -2357,8 +2357,8 @@ Depends: kernel-image-3.2.0-4-versatile-di, core-modules-3.2.0-4-versatile-di Description: EXT2 filesystem support This package contains the EXT2 filesystem module for the kernel. -Kernel-Version: 3.2.0-4-versatile -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-versatile Package: ext3-modules-3.2.0-4-versatile-di Architecture: armel @@ -2368,8 +2368,8 @@ Depends: kernel-image-3.2.0-4-versatile-di, core-modules-3.2.0-4-versatile-di Description: EXT3 filesystem support This package contains the EXT3 filesystem module for the kernel. -Kernel-Version: 3.2.0-4-versatile -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-versatile Package: ext4-modules-3.2.0-4-versatile-di Architecture: armel @@ -2379,8 +2379,8 @@ Depends: kernel-image-3.2.0-4-versatile-di, core-modules-3.2.0-4-versatile-di Description: EXT4 filesystem support This package contains the EXT4 filesystem module for the kernel. -Kernel-Version: 3.2.0-4-versatile -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-versatile Package: isofs-modules-3.2.0-4-versatile-di Architecture: armel @@ -2390,8 +2390,8 @@ Depends: kernel-image-3.2.0-4-versatile-di Description: ISOFS filesystem support This package contains the ISOFS filesystem module for the kernel. -Kernel-Version: 3.2.0-4-versatile -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-versatile Package: reiserfs-modules-3.2.0-4-versatile-di Architecture: armel @@ -2401,8 +2401,8 @@ Depends: kernel-image-3.2.0-4-versatile-di Description: Reiser filesystem support This package contains the Reiser filesystem module for the kernel. -Kernel-Version: 3.2.0-4-versatile -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-versatile Package: fat-modules-3.2.0-4-versatile-di Architecture: armel @@ -2412,8 +2412,8 @@ Depends: kernel-image-3.2.0-4-versatile-di Description: FAT filesystem support This package contains the FAT and VFAT filesystem modules for the kernel. -Kernel-Version: 3.2.0-4-versatile -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-versatile Package: md-modules-3.2.0-4-versatile-di Architecture: armel @@ -2423,8 +2423,8 @@ Depends: kernel-image-3.2.0-4-versatile-di Description: RAID and LVM support This package contains RAID and LVM modules for the kernel. -Kernel-Version: 3.2.0-4-versatile -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-versatile Package: multipath-modules-3.2.0-4-versatile-di Architecture: armel @@ -2434,8 +2434,8 @@ Depends: kernel-image-3.2.0-4-versatile-di, md-modules-3.2.0-4-versatile-di, scsi-core-modules-3.2.0-4-versatile-di Description: Multipath support This package contains DM-Multipath modules for the kernel. -Kernel-Version: 3.2.0-4-versatile -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-versatile Package: usb-modules-3.2.0-4-versatile-di Architecture: armel @@ -2445,8 +2445,8 @@ Depends: kernel-image-3.2.0-4-versatile-di Description: USB support This package contains core USB drivers for the kernel. -Kernel-Version: 3.2.0-4-versatile -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-versatile Package: usb-storage-modules-3.2.0-4-versatile-di Architecture: armel @@ -2456,8 +2456,8 @@ Depends: kernel-image-3.2.0-4-versatile-di, scsi-core-modules-3.2.0-4-versatile-di, usb-modules-3.2.0-4-versatile-di Description: USB storage support This package contains the USB storage driver for the kernel. -Kernel-Version: 3.2.0-4-versatile -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-versatile Package: nic-usb-modules-3.2.0-4-versatile-di Architecture: armel @@ -2467,8 +2467,8 @@ Depends: kernel-image-3.2.0-4-versatile-di, nic-shared-modules-3.2.0-4-versatile-di, usb-modules-3.2.0-4-versatile-di, core-modules-3.2.0-4-versatile-di Description: USB NIC drivers This package contains USB network adapter drivers for the kernel. -Kernel-Version: 3.2.0-4-versatile -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-versatile Package: sata-modules-3.2.0-4-versatile-di Architecture: armel @@ -2478,8 +2478,8 @@ Depends: kernel-image-3.2.0-4-versatile-di, scsi-core-modules-3.2.0-4-versatile-di Description: SATA drivers This package contains SATA drivers for the kernel. -Kernel-Version: 3.2.0-4-versatile -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-versatile Package: core-modules-3.2.0-4-versatile-di Architecture: armel @@ -2490,8 +2490,8 @@ Description: Core modules This package contains core modules for the kernel, that will almost always be needed. -Kernel-Version: 3.2.0-4-versatile -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-versatile Package: crc-modules-3.2.0-4-versatile-di Architecture: armel @@ -2501,8 +2501,8 @@ Depends: kernel-image-3.2.0-4-versatile-di Description: CRC modules This package contains CRC support modules. -Kernel-Version: 3.2.0-4-versatile -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-versatile Package: crypto-modules-3.2.0-4-versatile-di Architecture: armel @@ -2512,8 +2512,8 @@ Depends: kernel-image-3.2.0-4-versatile-di Description: crypto modules This package contains crypto modules. -Kernel-Version: 3.2.0-4-versatile -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-versatile Package: crypto-dm-modules-3.2.0-4-versatile-di Architecture: armel @@ -2523,8 +2523,8 @@ Depends: kernel-image-3.2.0-4-versatile-di, md-modules-3.2.0-4-versatile-di Description: devicemapper crypto module This package contains the devicemapper crypto (dm-crypt) module. -Kernel-Version: 3.2.0-4-versatile -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-versatile Package: nbd-modules-3.2.0-4-versatile-di Architecture: armel @@ -2535,8 +2535,8 @@ Description: Network Block Device modules This package contains the modules required for support of the Network Block Device -Kernel-Version: 3.2.0-4-versatile -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-versatile Package: squashfs-modules-3.2.0-4-versatile-di Architecture: armel @@ -2546,8 +2546,8 @@ Depends: kernel-image-3.2.0-4-versatile-di Description: squashfs modules This package contains squashfs modules. -Kernel-Version: 3.2.0-4-versatile -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-versatile Package: virtio-modules-3.2.0-4-versatile-di Architecture: armel @@ -2557,8 +2557,8 @@ Depends: kernel-image-3.2.0-4-versatile-di Description: virtio modules This package contains virtio modules. -Kernel-Version: 3.2.0-4-versatile -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-versatile Package: zlib-modules-3.2.0-4-versatile-di Architecture: armel @@ -2568,8 +2568,8 @@ Depends: kernel-image-3.2.0-4-versatile-di Description: zlib modules This package contains zlib modules. -Kernel-Version: 3.2.0-4-versatile -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-versatile Package: udf-modules-3.2.0-4-versatile-di Architecture: armel @@ -2579,8 +2579,8 @@ Depends: kernel-image-3.2.0-4-versatile-di, crc-modules-3.2.0-4-versatile-di Description: UDF modules This package contains the UDF filesystem module. -Kernel-Version: 3.2.0-4-versatile -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-versatile Package: fuse-modules-3.2.0-4-versatile-di Architecture: armel @@ -2590,8 +2590,8 @@ Depends: kernel-image-3.2.0-4-versatile-di Description: FUSE modules This package contains the Filesystem in Userspace (FUSE) module. -Kernel-Version: 3.2.0-4-versatile -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-versatile Package: linux-image-3.2.0-4-iop32x Architecture: armel @@ -2739,799 +2739,310 @@ Package: linux-headers-3.2.0-4-all-armhf Architecture: armhf -Depends: ${misc:Depends}, linux-headers-3.2.0-4-mx5 (= ${binary:Version}), linux-headers-3.2.0-4-omap (= ${binary:Version}), linux-headers-3.2.0-4-vexpress (= ${binary:Version}) +Depends: ${misc:Depends}, linux-headers-3.2.0-4-rpi (= ${binary:Version}) Description: All header files for Linux 3.2 (meta-package) This package depends against all architecture-specific kernel header files for Linux kernel version 3.2, generally used for building out-of-tree kernel modules. -Package: kernel-image-3.2.0-4-mx5-di +Package: kernel-image-3.2.0-4-rpi-di Architecture: armhf Section: debian-installer Priority: extra -Provides: kernel-image, rtc-modules +Provides: kernel-image Description: Linux kernel binary image for the Debian installer This package contains the kernel image for the Debian installer boot images. It does _not_ provide a usable kernel for your full Debian system. -Kernel-Version: 3.2.0-4-mx5 -Package-Type: udeb - -Package: nic-wireless-modules-3.2.0-4-mx5-di -Architecture: armhf -Section: debian-installer -Priority: standard -Provides: nic-wireless-modules -Depends: kernel-image-3.2.0-4-mx5-di, nic-shared-modules-3.2.0-4-mx5-di, core-modules-3.2.0-4-mx5-di, mmc-modules-3.2.0-4-mx5-di, crc-modules-3.2.0-4-mx5-di -Description: Wireless NIC drivers - This package contains wireless NIC drivers for the kernel. Includes - crypto modules only needed for wireless (WEP). -Kernel-Version: 3.2.0-4-mx5 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-rpi -Package: nic-shared-modules-3.2.0-4-mx5-di -Architecture: armhf -Section: debian-installer -Priority: standard -Provides: nic-shared-modules -Depends: kernel-image-3.2.0-4-mx5-di -Description: Shared NIC drivers - This package contains NIC drivers needed by combinations of nic-modules, - nic-extra-modules, nic-pcmcia-modules, and nic-wireless-modules. -Kernel-Version: 3.2.0-4-mx5 -Package-Type: udeb - -Package: pata-modules-3.2.0-4-mx5-di -Architecture: armhf -Section: debian-installer -Priority: extra -Provides: pata-modules -Depends: kernel-image-3.2.0-4-mx5-di, ata-modules-3.2.0-4-mx5-di -Description: PATA drivers - This package contains PATA drivers for the kernel. -Kernel-Version: 3.2.0-4-mx5 -Package-Type: udeb - -Package: scsi-core-modules-3.2.0-4-mx5-di +Package: scsi-core-modules-3.2.0-4-rpi-di Architecture: armhf Section: debian-installer Priority: standard Provides: scsi-core-modules -Depends: kernel-image-3.2.0-4-mx5-di +Depends: kernel-image-3.2.0-4-rpi-di Description: Core SCSI subsystem This package contains the core SCSI subsystem for the kernel. -Kernel-Version: 3.2.0-4-mx5 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-rpi -Package: loop-modules-3.2.0-4-mx5-di +Package: loop-modules-3.2.0-4-rpi-di Architecture: armhf Section: debian-installer Priority: standard Provides: loop-modules -Depends: kernel-image-3.2.0-4-mx5-di +Depends: kernel-image-3.2.0-4-rpi-di Description: Loopback filesystem support This package contains loopback filesystem support for the kernel. -Kernel-Version: 3.2.0-4-mx5 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-rpi -Package: ipv6-modules-3.2.0-4-mx5-di +Package: ipv6-modules-3.2.0-4-rpi-di Architecture: armhf Section: debian-installer Priority: extra Provides: ipv6-modules -Depends: kernel-image-3.2.0-4-mx5-di +Depends: kernel-image-3.2.0-4-rpi-di Description: IPv6 driver This package contains the IPv6 driver for the kernel. -Kernel-Version: 3.2.0-4-mx5 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-rpi -Package: btrfs-modules-3.2.0-4-mx5-di +Package: btrfs-modules-3.2.0-4-rpi-di Architecture: armhf Section: debian-installer Priority: extra Provides: btrfs-modules -Depends: kernel-image-3.2.0-4-mx5-di, core-modules-3.2.0-4-mx5-di, crc-modules-3.2.0-4-mx5-di +Depends: kernel-image-3.2.0-4-rpi-di, crc-modules-3.2.0-4-rpi-di Description: BTRFS filesystem support This package contains the BTRFS filesystem module for the kernel. -Kernel-Version: 3.2.0-4-mx5 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-rpi -Package: ext2-modules-3.2.0-4-mx5-di +Package: ext2-modules-3.2.0-4-rpi-di Architecture: armhf Section: debian-installer Priority: standard Provides: ext2-modules -Depends: kernel-image-3.2.0-4-mx5-di, core-modules-3.2.0-4-mx5-di +Depends: kernel-image-3.2.0-4-rpi-di Description: EXT2 filesystem support This package contains the EXT2 filesystem module for the kernel. -Kernel-Version: 3.2.0-4-mx5 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-rpi -Package: ext3-modules-3.2.0-4-mx5-di +Package: ext3-modules-3.2.0-4-rpi-di Architecture: armhf Section: debian-installer Priority: standard Provides: ext3-modules -Depends: kernel-image-3.2.0-4-mx5-di, core-modules-3.2.0-4-mx5-di +Depends: kernel-image-3.2.0-4-rpi-di Description: EXT3 filesystem support This package contains the EXT3 filesystem module for the kernel. -Kernel-Version: 3.2.0-4-mx5 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-rpi -Package: ext4-modules-3.2.0-4-mx5-di -Architecture: armhf -Section: debian-installer -Priority: standard -Provides: ext4-modules -Depends: kernel-image-3.2.0-4-mx5-di, core-modules-3.2.0-4-mx5-di -Description: EXT4 filesystem support - This package contains the EXT4 filesystem module for the kernel. -Kernel-Version: 3.2.0-4-mx5 -Package-Type: udeb - -Package: isofs-modules-3.2.0-4-mx5-di +Package: isofs-modules-3.2.0-4-rpi-di Architecture: armhf Section: debian-installer Priority: standard Provides: isofs-modules -Depends: kernel-image-3.2.0-4-mx5-di +Depends: kernel-image-3.2.0-4-rpi-di Description: ISOFS filesystem support This package contains the ISOFS filesystem module for the kernel. -Kernel-Version: 3.2.0-4-mx5 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-rpi -Package: jfs-modules-3.2.0-4-mx5-di +Package: jfs-modules-3.2.0-4-rpi-di Architecture: armhf Section: debian-installer Priority: standard Provides: jfs-modules -Depends: kernel-image-3.2.0-4-mx5-di +Depends: kernel-image-3.2.0-4-rpi-di Description: JFS filesystem support This package contains the JFS filesystem module for the kernel. -Kernel-Version: 3.2.0-4-mx5 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-rpi -Package: reiserfs-modules-3.2.0-4-mx5-di +Package: reiserfs-modules-3.2.0-4-rpi-di Architecture: armhf Section: debian-installer Priority: extra Provides: reiserfs-modules -Depends: kernel-image-3.2.0-4-mx5-di +Depends: kernel-image-3.2.0-4-rpi-di Description: Reiser filesystem support This package contains the Reiser filesystem module for the kernel. -Kernel-Version: 3.2.0-4-mx5 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-rpi -Package: fat-modules-3.2.0-4-mx5-di +Package: fat-modules-3.2.0-4-rpi-di Architecture: armhf Section: debian-installer Priority: extra Provides: fat-modules -Depends: kernel-image-3.2.0-4-mx5-di +Depends: kernel-image-3.2.0-4-rpi-di Description: FAT filesystem support This package contains the FAT and VFAT filesystem modules for the kernel. -Kernel-Version: 3.2.0-4-mx5 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-rpi -Package: minix-modules-3.2.0-4-mx5-di +Package: minix-modules-3.2.0-4-rpi-di Architecture: armhf Section: debian-installer Priority: extra Provides: minix-modules -Depends: kernel-image-3.2.0-4-mx5-di +Depends: kernel-image-3.2.0-4-rpi-di Description: Minix filesystem support This package contains the Minix filesystem module for the kernel. -Kernel-Version: 3.2.0-4-mx5 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-rpi -Package: md-modules-3.2.0-4-mx5-di +Package: md-modules-3.2.0-4-rpi-di Architecture: armhf Section: debian-installer Priority: extra Provides: md-modules -Depends: kernel-image-3.2.0-4-mx5-di +Depends: kernel-image-3.2.0-4-rpi-di Description: RAID and LVM support This package contains RAID and LVM modules for the kernel. -Kernel-Version: 3.2.0-4-mx5 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-rpi -Package: multipath-modules-3.2.0-4-mx5-di +Package: multipath-modules-3.2.0-4-rpi-di Architecture: armhf Section: debian-installer Priority: extra Provides: multipath-modules -Depends: kernel-image-3.2.0-4-mx5-di, md-modules-3.2.0-4-mx5-di, scsi-core-modules-3.2.0-4-mx5-di +Depends: kernel-image-3.2.0-4-rpi-di, md-modules-3.2.0-4-rpi-di, scsi-core-modules-3.2.0-4-rpi-di Description: Multipath support This package contains DM-Multipath modules for the kernel. -Kernel-Version: 3.2.0-4-mx5 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-rpi -Package: usb-storage-modules-3.2.0-4-mx5-di +Package: usb-storage-modules-3.2.0-4-rpi-di Architecture: armhf Section: debian-installer Priority: standard Provides: usb-storage-modules -Depends: kernel-image-3.2.0-4-mx5-di, scsi-core-modules-3.2.0-4-mx5-di +Depends: kernel-image-3.2.0-4-rpi-di, scsi-core-modules-3.2.0-4-rpi-di Description: USB storage support This package contains the USB storage driver for the kernel. -Kernel-Version: 3.2.0-4-mx5 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-rpi -Package: input-modules-3.2.0-4-mx5-di +Package: input-modules-3.2.0-4-rpi-di Architecture: armhf Section: debian-installer Priority: extra Provides: input-modules -Depends: kernel-image-3.2.0-4-mx5-di +Depends: kernel-image-3.2.0-4-rpi-di Description: Input devices support This package contains input device drivers for the kernel. -Kernel-Version: 3.2.0-4-mx5 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-rpi -Package: nic-usb-modules-3.2.0-4-mx5-di +Package: nic-usb-modules-3.2.0-4-rpi-di Architecture: armhf Section: debian-installer Priority: standard Provides: nic-usb-modules -Depends: kernel-image-3.2.0-4-mx5-di, nic-shared-modules-3.2.0-4-mx5-di, nic-wireless-modules-3.2.0-4-mx5-di, core-modules-3.2.0-4-mx5-di +Depends: kernel-image-3.2.0-4-rpi-di Description: USB NIC drivers This package contains USB network adapter drivers for the kernel. -Kernel-Version: 3.2.0-4-mx5 -Package-Type: udeb - -Package: sata-modules-3.2.0-4-mx5-di -Architecture: armhf -Section: debian-installer -Priority: standard -Provides: sata-modules -Depends: kernel-image-3.2.0-4-mx5-di, scsi-core-modules-3.2.0-4-mx5-di, ata-modules-3.2.0-4-mx5-di -Description: SATA drivers - This package contains SATA drivers for the kernel. -Kernel-Version: 3.2.0-4-mx5 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-rpi -Package: core-modules-3.2.0-4-mx5-di -Architecture: armhf -Section: debian-installer -Priority: standard -Provides: core-modules -Depends: kernel-image-3.2.0-4-mx5-di -Description: Core modules - This package contains core modules for the kernel, that will almost - always be needed. -Kernel-Version: 3.2.0-4-mx5 -Package-Type: udeb - -Package: crc-modules-3.2.0-4-mx5-di +Package: crc-modules-3.2.0-4-rpi-di Architecture: armhf Section: debian-installer Priority: extra Provides: crc-modules -Depends: kernel-image-3.2.0-4-mx5-di +Depends: kernel-image-3.2.0-4-rpi-di Description: CRC modules This package contains CRC support modules. -Kernel-Version: 3.2.0-4-mx5 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-rpi -Package: crypto-modules-3.2.0-4-mx5-di +Package: crypto-modules-3.2.0-4-rpi-di Architecture: armhf Section: debian-installer Priority: extra Provides: crypto-modules -Depends: kernel-image-3.2.0-4-mx5-di +Depends: kernel-image-3.2.0-4-rpi-di Description: crypto modules This package contains crypto modules. -Kernel-Version: 3.2.0-4-mx5 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-rpi -Package: crypto-dm-modules-3.2.0-4-mx5-di +Package: crypto-dm-modules-3.2.0-4-rpi-di Architecture: armhf Section: debian-installer Priority: extra Provides: crypto-dm-modules -Depends: kernel-image-3.2.0-4-mx5-di, md-modules-3.2.0-4-mx5-di +Depends: kernel-image-3.2.0-4-rpi-di, md-modules-3.2.0-4-rpi-di Description: devicemapper crypto module This package contains the devicemapper crypto (dm-crypt) module. -Kernel-Version: 3.2.0-4-mx5 -Package-Type: udeb - -Package: ata-modules-3.2.0-4-mx5-di -Architecture: armhf -Section: debian-installer -Priority: extra -Provides: ata-modules -Depends: kernel-image-3.2.0-4-mx5-di, scsi-core-modules-3.2.0-4-mx5-di -Description: ATA disk modules - This package contains core ATA disk modules used by both PATA and SATA - disk drivers. -Kernel-Version: 3.2.0-4-mx5 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-rpi -Package: mmc-modules-3.2.0-4-mx5-di -Architecture: armhf -Section: debian-installer -Priority: extra -Provides: mmc-modules -Depends: kernel-image-3.2.0-4-mx5-di, core-modules-3.2.0-4-mx5-di -Description: MMC/SD card modules - This package contains modules needed to support MMC (multimedia) and SD - cards. -Kernel-Version: 3.2.0-4-mx5 -Package-Type: udeb - -Package: nbd-modules-3.2.0-4-mx5-di +Package: nbd-modules-3.2.0-4-rpi-di Architecture: armhf Section: debian-installer Priority: extra Provides: nbd-modules -Depends: kernel-image-3.2.0-4-mx5-di +Depends: kernel-image-3.2.0-4-rpi-di Description: Network Block Device modules This package contains the modules required for support of the Network Block Device -Kernel-Version: 3.2.0-4-mx5 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-rpi -Package: squashfs-modules-3.2.0-4-mx5-di +Package: squashfs-modules-3.2.0-4-rpi-di Architecture: armhf Section: debian-installer Priority: extra Provides: squashfs-modules -Depends: kernel-image-3.2.0-4-mx5-di +Depends: kernel-image-3.2.0-4-rpi-di Description: squashfs modules This package contains squashfs modules. -Kernel-Version: 3.2.0-4-mx5 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-rpi -Package: uinput-modules-3.2.0-4-mx5-di +Package: uinput-modules-3.2.0-4-rpi-di Architecture: armhf Section: debian-installer Priority: extra Provides: uinput-modules -Depends: kernel-image-3.2.0-4-mx5-di +Depends: kernel-image-3.2.0-4-rpi-di Description: uinput support This package contains the uinput module. -Kernel-Version: 3.2.0-4-mx5 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-rpi -Package: udf-modules-3.2.0-4-mx5-di +Package: udf-modules-3.2.0-4-rpi-di Architecture: armhf Section: debian-installer Priority: extra Provides: udf-modules -Depends: kernel-image-3.2.0-4-mx5-di, crc-modules-3.2.0-4-mx5-di +Depends: kernel-image-3.2.0-4-rpi-di, crc-modules-3.2.0-4-rpi-di Description: UDF modules This package contains the UDF filesystem module. -Kernel-Version: 3.2.0-4-mx5 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-rpi -Package: fuse-modules-3.2.0-4-mx5-di +Package: fuse-modules-3.2.0-4-rpi-di Architecture: armhf Section: debian-installer Priority: extra Provides: fuse-modules -Depends: kernel-image-3.2.0-4-mx5-di +Depends: kernel-image-3.2.0-4-rpi-di Description: FUSE modules This package contains the Filesystem in Userspace (FUSE) module. -Kernel-Version: 3.2.0-4-mx5 -Package-Type: udeb - -Package: mtd-modules-3.2.0-4-mx5-di -Architecture: armhf -Section: debian-installer -Priority: extra -Provides: mtd-modules -Depends: kernel-image-3.2.0-4-mx5-di -Description: MTD modules - This package contains MTD modules. -Kernel-Version: 3.2.0-4-mx5 -Package-Type: udeb - -Package: kernel-image-3.2.0-4-vexpress-di -Architecture: armhf -Section: debian-installer -Priority: extra -Provides: kernel-image, rtc-modules -Description: Linux kernel binary image for the Debian installer - This package contains the kernel image for the Debian installer boot - images. It does _not_ provide a usable kernel for your full Debian - system. -Kernel-Version: 3.2.0-4-vexpress -Package-Type: udeb - -Package: nic-modules-3.2.0-4-vexpress-di -Architecture: armhf -Section: debian-installer -Priority: standard -Provides: nic-modules -Depends: kernel-image-3.2.0-4-vexpress-di, nic-shared-modules-3.2.0-4-vexpress-di, core-modules-3.2.0-4-vexpress-di -Description: Common NIC drivers - This package contains common NIC drivers for the kernel. -Kernel-Version: 3.2.0-4-vexpress -Package-Type: udeb - -Package: nic-wireless-modules-3.2.0-4-vexpress-di -Architecture: armhf -Section: debian-installer -Priority: standard -Provides: nic-wireless-modules -Depends: kernel-image-3.2.0-4-vexpress-di, nic-shared-modules-3.2.0-4-vexpress-di, core-modules-3.2.0-4-vexpress-di, usb-modules-3.2.0-4-vexpress-di, mmc-modules-3.2.0-4-vexpress-di, crc-modules-3.2.0-4-vexpress-di -Description: Wireless NIC drivers - This package contains wireless NIC drivers for the kernel. Includes - crypto modules only needed for wireless (WEP). -Kernel-Version: 3.2.0-4-vexpress -Package-Type: udeb - -Package: nic-shared-modules-3.2.0-4-vexpress-di -Architecture: armhf -Section: debian-installer -Priority: standard -Provides: nic-shared-modules -Depends: kernel-image-3.2.0-4-vexpress-di -Description: Shared NIC drivers - This package contains NIC drivers needed by combinations of nic-modules, - nic-extra-modules, nic-pcmcia-modules, and nic-wireless-modules. -Kernel-Version: 3.2.0-4-vexpress -Package-Type: udeb - -Package: scsi-core-modules-3.2.0-4-vexpress-di -Architecture: armhf -Section: debian-installer -Priority: standard -Provides: scsi-core-modules -Depends: kernel-image-3.2.0-4-vexpress-di -Description: Core SCSI subsystem - This package contains the core SCSI subsystem for the kernel. -Kernel-Version: 3.2.0-4-vexpress -Package-Type: udeb - -Package: loop-modules-3.2.0-4-vexpress-di -Architecture: armhf -Section: debian-installer -Priority: standard -Provides: loop-modules -Depends: kernel-image-3.2.0-4-vexpress-di -Description: Loopback filesystem support - This package contains loopback filesystem support for the kernel. -Kernel-Version: 3.2.0-4-vexpress -Package-Type: udeb - -Package: ipv6-modules-3.2.0-4-vexpress-di -Architecture: armhf -Section: debian-installer -Priority: extra -Provides: ipv6-modules -Depends: kernel-image-3.2.0-4-vexpress-di -Description: IPv6 driver - This package contains the IPv6 driver for the kernel. -Kernel-Version: 3.2.0-4-vexpress -Package-Type: udeb - -Package: btrfs-modules-3.2.0-4-vexpress-di -Architecture: armhf -Section: debian-installer -Priority: extra -Provides: btrfs-modules -Depends: kernel-image-3.2.0-4-vexpress-di, core-modules-3.2.0-4-vexpress-di, crc-modules-3.2.0-4-vexpress-di -Description: BTRFS filesystem support - This package contains the BTRFS filesystem module for the kernel. -Kernel-Version: 3.2.0-4-vexpress -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-rpi -Package: ext2-modules-3.2.0-4-vexpress-di +Package: linux-image-3.2.0-4-rpi Architecture: armhf -Section: debian-installer -Priority: standard -Provides: ext2-modules -Depends: kernel-image-3.2.0-4-vexpress-di, core-modules-3.2.0-4-vexpress-di -Description: EXT2 filesystem support - This package contains the EXT2 filesystem module for the kernel. -Kernel-Version: 3.2.0-4-vexpress -Package-Type: udeb - -Package: ext3-modules-3.2.0-4-vexpress-di -Architecture: armhf -Section: debian-installer -Priority: standard -Provides: ext3-modules -Depends: kernel-image-3.2.0-4-vexpress-di, core-modules-3.2.0-4-vexpress-di -Description: EXT3 filesystem support - This package contains the EXT3 filesystem module for the kernel. -Kernel-Version: 3.2.0-4-vexpress -Package-Type: udeb - -Package: ext4-modules-3.2.0-4-vexpress-di -Architecture: armhf -Section: debian-installer -Priority: standard -Provides: ext4-modules -Depends: kernel-image-3.2.0-4-vexpress-di, core-modules-3.2.0-4-vexpress-di -Description: EXT4 filesystem support - This package contains the EXT4 filesystem module for the kernel. -Kernel-Version: 3.2.0-4-vexpress -Package-Type: udeb - -Package: isofs-modules-3.2.0-4-vexpress-di -Architecture: armhf -Section: debian-installer -Priority: standard -Provides: isofs-modules -Depends: kernel-image-3.2.0-4-vexpress-di -Description: ISOFS filesystem support - This package contains the ISOFS filesystem module for the kernel. -Kernel-Version: 3.2.0-4-vexpress -Package-Type: udeb - -Package: jfs-modules-3.2.0-4-vexpress-di -Architecture: armhf -Section: debian-installer -Priority: standard -Provides: jfs-modules -Depends: kernel-image-3.2.0-4-vexpress-di -Description: JFS filesystem support - This package contains the JFS filesystem module for the kernel. -Kernel-Version: 3.2.0-4-vexpress -Package-Type: udeb - -Package: fat-modules-3.2.0-4-vexpress-di -Architecture: armhf -Section: debian-installer -Priority: extra -Provides: fat-modules -Depends: kernel-image-3.2.0-4-vexpress-di -Description: FAT filesystem support - This package contains the FAT and VFAT filesystem modules for the kernel. -Kernel-Version: 3.2.0-4-vexpress -Package-Type: udeb - -Package: md-modules-3.2.0-4-vexpress-di -Architecture: armhf -Section: debian-installer -Priority: extra -Provides: md-modules -Depends: kernel-image-3.2.0-4-vexpress-di -Description: RAID and LVM support - This package contains RAID and LVM modules for the kernel. -Kernel-Version: 3.2.0-4-vexpress -Package-Type: udeb - -Package: multipath-modules-3.2.0-4-vexpress-di -Architecture: armhf -Section: debian-installer -Priority: extra -Provides: multipath-modules -Depends: kernel-image-3.2.0-4-vexpress-di, md-modules-3.2.0-4-vexpress-di, scsi-core-modules-3.2.0-4-vexpress-di -Description: Multipath support - This package contains DM-Multipath modules for the kernel. -Kernel-Version: 3.2.0-4-vexpress -Package-Type: udeb - -Package: usb-modules-3.2.0-4-vexpress-di -Architecture: armhf -Section: debian-installer -Priority: extra -Provides: usb-modules -Depends: kernel-image-3.2.0-4-vexpress-di -Description: USB support - This package contains core USB drivers for the kernel. -Kernel-Version: 3.2.0-4-vexpress -Package-Type: udeb - -Package: usb-storage-modules-3.2.0-4-vexpress-di -Architecture: armhf -Section: debian-installer -Priority: standard -Provides: usb-storage-modules -Depends: kernel-image-3.2.0-4-vexpress-di, scsi-core-modules-3.2.0-4-vexpress-di, usb-modules-3.2.0-4-vexpress-di -Description: USB storage support - This package contains the USB storage driver for the kernel. -Kernel-Version: 3.2.0-4-vexpress -Package-Type: udeb - -Package: input-modules-3.2.0-4-vexpress-di -Architecture: armhf -Section: debian-installer -Priority: extra -Provides: input-modules -Depends: kernel-image-3.2.0-4-vexpress-di, usb-modules-3.2.0-4-vexpress-di -Description: Input devices support - This package contains input device drivers for the kernel. -Kernel-Version: 3.2.0-4-vexpress -Package-Type: udeb - -Package: nic-usb-modules-3.2.0-4-vexpress-di -Architecture: armhf -Section: debian-installer -Priority: standard -Provides: nic-usb-modules -Depends: kernel-image-3.2.0-4-vexpress-di, nic-shared-modules-3.2.0-4-vexpress-di, nic-wireless-modules-3.2.0-4-vexpress-di, usb-modules-3.2.0-4-vexpress-di, core-modules-3.2.0-4-vexpress-di -Description: USB NIC drivers - This package contains USB network adapter drivers for the kernel. -Kernel-Version: 3.2.0-4-vexpress -Package-Type: udeb - -Package: core-modules-3.2.0-4-vexpress-di -Architecture: armhf -Section: debian-installer -Priority: standard -Provides: core-modules -Depends: kernel-image-3.2.0-4-vexpress-di -Description: Core modules - This package contains core modules for the kernel, that will almost - always be needed. -Kernel-Version: 3.2.0-4-vexpress -Package-Type: udeb - -Package: crc-modules-3.2.0-4-vexpress-di -Architecture: armhf -Section: debian-installer -Priority: extra -Provides: crc-modules -Depends: kernel-image-3.2.0-4-vexpress-di -Description: CRC modules - This package contains CRC support modules. -Kernel-Version: 3.2.0-4-vexpress -Package-Type: udeb - -Package: crypto-modules-3.2.0-4-vexpress-di -Architecture: armhf -Section: debian-installer -Priority: extra -Provides: crypto-modules -Depends: kernel-image-3.2.0-4-vexpress-di -Description: crypto modules - This package contains crypto modules. -Kernel-Version: 3.2.0-4-vexpress -Package-Type: udeb - -Package: crypto-dm-modules-3.2.0-4-vexpress-di -Architecture: armhf -Section: debian-installer -Priority: extra -Provides: crypto-dm-modules -Depends: kernel-image-3.2.0-4-vexpress-di, md-modules-3.2.0-4-vexpress-di -Description: devicemapper crypto module - This package contains the devicemapper crypto (dm-crypt) module. -Kernel-Version: 3.2.0-4-vexpress -Package-Type: udeb - -Package: mmc-modules-3.2.0-4-vexpress-di -Architecture: armhf -Section: debian-installer -Priority: extra -Provides: mmc-modules -Depends: kernel-image-3.2.0-4-vexpress-di, core-modules-3.2.0-4-vexpress-di -Description: MMC/SD card modules - This package contains modules needed to support MMC (multimedia) and SD - cards. -Kernel-Version: 3.2.0-4-vexpress -Package-Type: udeb - -Package: nbd-modules-3.2.0-4-vexpress-di -Architecture: armhf -Section: debian-installer -Priority: extra -Provides: nbd-modules -Depends: kernel-image-3.2.0-4-vexpress-di -Description: Network Block Device modules - This package contains the modules required for support of the Network - Block Device -Kernel-Version: 3.2.0-4-vexpress -Package-Type: udeb - -Package: squashfs-modules-3.2.0-4-vexpress-di -Architecture: armhf -Section: debian-installer -Priority: extra -Provides: squashfs-modules -Depends: kernel-image-3.2.0-4-vexpress-di -Description: squashfs modules - This package contains squashfs modules. -Kernel-Version: 3.2.0-4-vexpress -Package-Type: udeb - -Package: uinput-modules-3.2.0-4-vexpress-di -Architecture: armhf -Section: debian-installer -Priority: extra -Provides: uinput-modules -Depends: kernel-image-3.2.0-4-vexpress-di -Description: uinput support - This package contains the uinput module. -Kernel-Version: 3.2.0-4-vexpress -Package-Type: udeb - -Package: udf-modules-3.2.0-4-vexpress-di -Architecture: armhf -Section: debian-installer -Priority: extra -Provides: udf-modules -Depends: kernel-image-3.2.0-4-vexpress-di, crc-modules-3.2.0-4-vexpress-di -Description: UDF modules - This package contains the UDF filesystem module. -Kernel-Version: 3.2.0-4-vexpress -Package-Type: udeb - -Package: fuse-modules-3.2.0-4-vexpress-di -Architecture: armhf -Section: debian-installer -Priority: extra -Provides: fuse-modules -Depends: kernel-image-3.2.0-4-vexpress-di -Description: FUSE modules - This package contains the Filesystem in Userspace (FUSE) module. -Kernel-Version: 3.2.0-4-vexpress -Package-Type: udeb - -Package: linux-image-3.2.0-4-mx5 -Architecture: armhf -Provides: linux-image, linux-modules-3.2.0-4-mx5 +Provides: linux-image, linux-modules-3.2.0-4-rpi Pre-Depends: debconf | debconf-2.0 Depends: kmod | module-init-tools, linux-base (>= 3~), ${misc:Depends}, initramfs-tools (>= 0.99~) [armhf] | linux-initramfs-tool [armhf] Recommends: firmware-linux-free (>= 3~) Suggests: linux-doc-3.2, debian-kernel-handbook, fdutils [armhf] Breaks: at (<< 3.1.12-1+squeeze1), initramfs-tools (<< 0.99~) -Description: Linux 3.2 for Freescale i.MX51/53 - The Linux kernel 3.2 and modules for use on Freescale i.MX51 or i.MX53 - based systems. - -Package: linux-headers-3.2.0-4-mx5 -Architecture: armhf -Provides: linux-headers -Depends: linux-headers-3.2.0-4-common (= ${binary:Version}), linux-kbuild-3.2, ${misc:Depends}, gcc-4.6 -Description: Header files for Linux 3.2.0-4-mx5 - This package provides the architecture-specific kernel header files for - Linux kernel 3.2.0-4-mx5, generally used for building out-of-tree kernel - modules. These files are going to be installed into - /usr/src/linux-headers-3.2.0-4-mx5, and can be used for building modules - that load into the kernel provided by the linux-image-3.2.0-4-mx5 package. - -Package: linux-image-3.2.0-4-omap -Architecture: armhf -Provides: linux-image, linux-modules-3.2.0-4-omap -Pre-Depends: debconf | debconf-2.0 -Depends: kmod | module-init-tools, linux-base (>= 3~), ${misc:Depends}, initramfs-tools (>= 0.99~) [armhf] | linux-initramfs-tool [armhf] -Recommends: firmware-linux-free (>= 3~), uboot-mkimage [armhf] -Suggests: linux-doc-3.2, debian-kernel-handbook, fdutils [armhf] -Breaks: at (<< 3.1.12-1+squeeze1), initramfs-tools (<< 0.99~) -Description: Linux 3.2 for TI OMAP3+ - The Linux kernel 3.2 and modules for use on Texas Instruments OMAP3 or - OMAP4 based systems. +Description: Linux 3.2 for RaspberryPI + The Linux kernel 3.2 and modules for use on Raspberry PI. -Package: linux-headers-3.2.0-4-omap +Package: linux-headers-3.2.0-4-rpi Architecture: armhf Provides: linux-headers Depends: linux-headers-3.2.0-4-common (= ${binary:Version}), linux-kbuild-3.2, ${misc:Depends}, gcc-4.6 -Description: Header files for Linux 3.2.0-4-omap +Description: Header files for Linux 3.2.0-4-rpi This package provides the architecture-specific kernel header files for - Linux kernel 3.2.0-4-omap, generally used for building out-of-tree kernel + Linux kernel 3.2.0-4-rpi, generally used for building out-of-tree kernel modules. These files are going to be installed into - /usr/src/linux-headers-3.2.0-4-omap, and can be used for building modules - that load into the kernel provided by the linux-image-3.2.0-4-omap - package. - -Package: linux-image-3.2.0-4-vexpress -Architecture: armhf -Provides: linux-image, linux-modules-3.2.0-4-vexpress -Pre-Depends: debconf | debconf-2.0 -Depends: kmod | module-init-tools, linux-base (>= 3~), ${misc:Depends}, initramfs-tools (>= 0.99~) [armhf] | linux-initramfs-tool [armhf] -Recommends: firmware-linux-free (>= 3~) -Suggests: linux-doc-3.2, debian-kernel-handbook, fdutils [armhf] -Breaks: at (<< 3.1.12-1+squeeze1), initramfs-tools (<< 0.99~) -Description: Linux 3.2 for ARM Ltd. Versatile Express - The Linux kernel 3.2 and modules for use on ARM Ltd. Versatile Express - family of processors. - -Package: linux-headers-3.2.0-4-vexpress -Architecture: armhf -Provides: linux-headers -Depends: linux-headers-3.2.0-4-common (= ${binary:Version}), linux-kbuild-3.2, ${misc:Depends}, gcc-4.6 -Description: Header files for Linux 3.2.0-4-vexpress - This package provides the architecture-specific kernel header files for - Linux kernel 3.2.0-4-vexpress, generally used for building out-of-tree - kernel modules. These files are going to be installed into - /usr/src/linux-headers-3.2.0-4-vexpress, and can be used for building - modules that load into the kernel provided by the - linux-image-3.2.0-4-vexpress package. + /usr/src/linux-headers-3.2.0-4-rpi, and can be used for building modules + that load into the kernel provided by the linux-image-3.2.0-4-rpi package. Package: linux-headers-3.2.0-4-all-hppa Architecture: hppa @@ -3550,8 +3061,8 @@ This package contains the kernel image for the Debian installer boot images. It does _not_ provide a usable kernel for your full Debian system. -Kernel-Version: 3.2.0-4-parisc -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-parisc Package: nic-modules-3.2.0-4-parisc-di Architecture: hppa @@ -3561,8 +3072,8 @@ Depends: kernel-image-3.2.0-4-parisc-di Description: Common NIC drivers This package contains common NIC drivers for the kernel. -Kernel-Version: 3.2.0-4-parisc -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-parisc Package: ppp-modules-3.2.0-4-parisc-di Architecture: hppa @@ -3572,8 +3083,8 @@ Depends: kernel-image-3.2.0-4-parisc-di, zlib-modules-3.2.0-4-parisc-di Description: PPP drivers This package contains PPP drivers for the kernel. -Kernel-Version: 3.2.0-4-parisc -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-parisc Package: pata-modules-3.2.0-4-parisc-di Architecture: hppa @@ -3583,8 +3094,8 @@ Depends: kernel-image-3.2.0-4-parisc-di, scsi-core-modules-3.2.0-4-parisc-di Description: PATA drivers This package contains PATA drivers for the kernel. -Kernel-Version: 3.2.0-4-parisc -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-parisc Package: cdrom-core-modules-3.2.0-4-parisc-di Architecture: hppa @@ -3594,8 +3105,8 @@ Depends: kernel-image-3.2.0-4-parisc-di, scsi-core-modules-3.2.0-4-parisc-di Description: CDROM support This package contains core CDROM support for the kernel. -Kernel-Version: 3.2.0-4-parisc -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-parisc Package: scsi-core-modules-3.2.0-4-parisc-di Architecture: hppa @@ -3605,8 +3116,8 @@ Depends: kernel-image-3.2.0-4-parisc-di Description: Core SCSI subsystem This package contains the core SCSI subsystem for the kernel. -Kernel-Version: 3.2.0-4-parisc -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-parisc Package: scsi-modules-3.2.0-4-parisc-di Architecture: hppa @@ -3616,8 +3127,8 @@ Depends: kernel-image-3.2.0-4-parisc-di, scsi-core-modules-3.2.0-4-parisc-di, cdrom-core-modules-3.2.0-4-parisc-di Description: SCSI drivers This package contains SCSI drivers for the kernel. -Kernel-Version: 3.2.0-4-parisc -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-parisc Package: loop-modules-3.2.0-4-parisc-di Architecture: hppa @@ -3627,8 +3138,8 @@ Depends: kernel-image-3.2.0-4-parisc-di Description: Loopback filesystem support This package contains loopback filesystem support for the kernel. -Kernel-Version: 3.2.0-4-parisc -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-parisc Package: ipv6-modules-3.2.0-4-parisc-di Architecture: hppa @@ -3638,8 +3149,8 @@ Depends: kernel-image-3.2.0-4-parisc-di Description: IPv6 driver This package contains the IPv6 driver for the kernel. -Kernel-Version: 3.2.0-4-parisc -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-parisc Package: btrfs-modules-3.2.0-4-parisc-di Architecture: hppa @@ -3649,8 +3160,8 @@ Depends: kernel-image-3.2.0-4-parisc-di, zlib-modules-3.2.0-4-parisc-di Description: BTRFS filesystem support This package contains the BTRFS filesystem module for the kernel. -Kernel-Version: 3.2.0-4-parisc -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-parisc Package: ext3-modules-3.2.0-4-parisc-di Architecture: hppa @@ -3660,8 +3171,8 @@ Depends: kernel-image-3.2.0-4-parisc-di Description: EXT3 filesystem support This package contains the EXT3 filesystem module for the kernel. -Kernel-Version: 3.2.0-4-parisc -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-parisc Package: ext4-modules-3.2.0-4-parisc-di Architecture: hppa @@ -3671,8 +3182,8 @@ Depends: kernel-image-3.2.0-4-parisc-di Description: EXT4 filesystem support This package contains the EXT4 filesystem module for the kernel. -Kernel-Version: 3.2.0-4-parisc -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-parisc Package: fat-modules-3.2.0-4-parisc-di Architecture: hppa @@ -3682,8 +3193,8 @@ Depends: kernel-image-3.2.0-4-parisc-di Description: FAT filesystem support This package contains the FAT and VFAT filesystem modules for the kernel. -Kernel-Version: 3.2.0-4-parisc -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-parisc Package: md-modules-3.2.0-4-parisc-di Architecture: hppa @@ -3693,8 +3204,8 @@ Depends: kernel-image-3.2.0-4-parisc-di Description: RAID and LVM support This package contains RAID and LVM modules for the kernel. -Kernel-Version: 3.2.0-4-parisc -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-parisc Package: multipath-modules-3.2.0-4-parisc-di Architecture: hppa @@ -3704,8 +3215,8 @@ Depends: kernel-image-3.2.0-4-parisc-di, md-modules-3.2.0-4-parisc-di, scsi-core-modules-3.2.0-4-parisc-di Description: Multipath support This package contains DM-Multipath modules for the kernel. -Kernel-Version: 3.2.0-4-parisc -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-parisc Package: usb-modules-3.2.0-4-parisc-di Architecture: hppa @@ -3715,8 +3226,8 @@ Depends: kernel-image-3.2.0-4-parisc-di Description: USB support This package contains core USB drivers for the kernel. -Kernel-Version: 3.2.0-4-parisc -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-parisc Package: usb-storage-modules-3.2.0-4-parisc-di Architecture: hppa @@ -3726,8 +3237,8 @@ Depends: kernel-image-3.2.0-4-parisc-di, scsi-modules-3.2.0-4-parisc-di, usb-modules-3.2.0-4-parisc-di Description: USB storage support This package contains the USB storage driver for the kernel. -Kernel-Version: 3.2.0-4-parisc -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-parisc Package: input-modules-3.2.0-4-parisc-di Architecture: hppa @@ -3737,8 +3248,8 @@ Depends: kernel-image-3.2.0-4-parisc-di, usb-modules-3.2.0-4-parisc-di Description: Input devices support This package contains input device drivers for the kernel. -Kernel-Version: 3.2.0-4-parisc -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-parisc Package: crypto-modules-3.2.0-4-parisc-di Architecture: hppa @@ -3748,8 +3259,8 @@ Depends: kernel-image-3.2.0-4-parisc-di Description: crypto modules This package contains crypto modules. -Kernel-Version: 3.2.0-4-parisc -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-parisc Package: crypto-dm-modules-3.2.0-4-parisc-di Architecture: hppa @@ -3759,8 +3270,8 @@ Depends: kernel-image-3.2.0-4-parisc-di, md-modules-3.2.0-4-parisc-di Description: devicemapper crypto module This package contains the devicemapper crypto (dm-crypt) module. -Kernel-Version: 3.2.0-4-parisc -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-parisc Package: nbd-modules-3.2.0-4-parisc-di Architecture: hppa @@ -3771,8 +3282,8 @@ Description: Network Block Device modules This package contains the modules required for support of the Network Block Device -Kernel-Version: 3.2.0-4-parisc -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-parisc Package: zlib-modules-3.2.0-4-parisc-di Architecture: hppa @@ -3782,8 +3293,8 @@ Depends: kernel-image-3.2.0-4-parisc-di Description: zlib modules This package contains zlib modules. -Kernel-Version: 3.2.0-4-parisc -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-parisc Package: fuse-modules-3.2.0-4-parisc-di Architecture: hppa @@ -3793,8 +3304,8 @@ Depends: kernel-image-3.2.0-4-parisc-di Description: FUSE modules This package contains the Filesystem in Userspace (FUSE) module. -Kernel-Version: 3.2.0-4-parisc -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-parisc Package: kernel-image-3.2.0-4-parisc64-di Architecture: hppa @@ -3805,8 +3316,8 @@ This package contains the kernel image for the Debian installer boot images. It does _not_ provide a usable kernel for your full Debian system. -Kernel-Version: 3.2.0-4-parisc64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-parisc64 Package: nic-modules-3.2.0-4-parisc64-di Architecture: hppa @@ -3816,8 +3327,8 @@ Depends: kernel-image-3.2.0-4-parisc64-di Description: Common NIC drivers This package contains common NIC drivers for the kernel. -Kernel-Version: 3.2.0-4-parisc64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-parisc64 Package: ppp-modules-3.2.0-4-parisc64-di Architecture: hppa @@ -3827,8 +3338,8 @@ Depends: kernel-image-3.2.0-4-parisc64-di, zlib-modules-3.2.0-4-parisc64-di Description: PPP drivers This package contains PPP drivers for the kernel. -Kernel-Version: 3.2.0-4-parisc64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-parisc64 Package: pata-modules-3.2.0-4-parisc64-di Architecture: hppa @@ -3838,8 +3349,8 @@ Depends: kernel-image-3.2.0-4-parisc64-di, scsi-core-modules-3.2.0-4-parisc64-di Description: PATA drivers This package contains PATA drivers for the kernel. -Kernel-Version: 3.2.0-4-parisc64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-parisc64 Package: cdrom-core-modules-3.2.0-4-parisc64-di Architecture: hppa @@ -3849,8 +3360,8 @@ Depends: kernel-image-3.2.0-4-parisc64-di, scsi-core-modules-3.2.0-4-parisc64-di Description: CDROM support This package contains core CDROM support for the kernel. -Kernel-Version: 3.2.0-4-parisc64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-parisc64 Package: scsi-core-modules-3.2.0-4-parisc64-di Architecture: hppa @@ -3860,8 +3371,8 @@ Depends: kernel-image-3.2.0-4-parisc64-di Description: Core SCSI subsystem This package contains the core SCSI subsystem for the kernel. -Kernel-Version: 3.2.0-4-parisc64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-parisc64 Package: scsi-modules-3.2.0-4-parisc64-di Architecture: hppa @@ -3871,8 +3382,8 @@ Depends: kernel-image-3.2.0-4-parisc64-di, scsi-core-modules-3.2.0-4-parisc64-di, cdrom-core-modules-3.2.0-4-parisc64-di Description: SCSI drivers This package contains SCSI drivers for the kernel. -Kernel-Version: 3.2.0-4-parisc64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-parisc64 Package: loop-modules-3.2.0-4-parisc64-di Architecture: hppa @@ -3882,8 +3393,8 @@ Depends: kernel-image-3.2.0-4-parisc64-di Description: Loopback filesystem support This package contains loopback filesystem support for the kernel. -Kernel-Version: 3.2.0-4-parisc64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-parisc64 Package: ipv6-modules-3.2.0-4-parisc64-di Architecture: hppa @@ -3893,8 +3404,8 @@ Depends: kernel-image-3.2.0-4-parisc64-di Description: IPv6 driver This package contains the IPv6 driver for the kernel. -Kernel-Version: 3.2.0-4-parisc64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-parisc64 Package: btrfs-modules-3.2.0-4-parisc64-di Architecture: hppa @@ -3904,8 +3415,8 @@ Depends: kernel-image-3.2.0-4-parisc64-di, zlib-modules-3.2.0-4-parisc64-di Description: BTRFS filesystem support This package contains the BTRFS filesystem module for the kernel. -Kernel-Version: 3.2.0-4-parisc64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-parisc64 Package: ext3-modules-3.2.0-4-parisc64-di Architecture: hppa @@ -3915,8 +3426,8 @@ Depends: kernel-image-3.2.0-4-parisc64-di Description: EXT3 filesystem support This package contains the EXT3 filesystem module for the kernel. -Kernel-Version: 3.2.0-4-parisc64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-parisc64 Package: ext4-modules-3.2.0-4-parisc64-di Architecture: hppa @@ -3926,8 +3437,8 @@ Depends: kernel-image-3.2.0-4-parisc64-di Description: EXT4 filesystem support This package contains the EXT4 filesystem module for the kernel. -Kernel-Version: 3.2.0-4-parisc64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-parisc64 Package: fat-modules-3.2.0-4-parisc64-di Architecture: hppa @@ -3937,8 +3448,8 @@ Depends: kernel-image-3.2.0-4-parisc64-di Description: FAT filesystem support This package contains the FAT and VFAT filesystem modules for the kernel. -Kernel-Version: 3.2.0-4-parisc64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-parisc64 Package: md-modules-3.2.0-4-parisc64-di Architecture: hppa @@ -3948,8 +3459,8 @@ Depends: kernel-image-3.2.0-4-parisc64-di Description: RAID and LVM support This package contains RAID and LVM modules for the kernel. -Kernel-Version: 3.2.0-4-parisc64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-parisc64 Package: multipath-modules-3.2.0-4-parisc64-di Architecture: hppa @@ -3959,8 +3470,8 @@ Depends: kernel-image-3.2.0-4-parisc64-di, md-modules-3.2.0-4-parisc64-di, scsi-core-modules-3.2.0-4-parisc64-di Description: Multipath support This package contains DM-Multipath modules for the kernel. -Kernel-Version: 3.2.0-4-parisc64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-parisc64 Package: usb-modules-3.2.0-4-parisc64-di Architecture: hppa @@ -3970,8 +3481,8 @@ Depends: kernel-image-3.2.0-4-parisc64-di Description: USB support This package contains core USB drivers for the kernel. -Kernel-Version: 3.2.0-4-parisc64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-parisc64 Package: usb-storage-modules-3.2.0-4-parisc64-di Architecture: hppa @@ -3981,8 +3492,8 @@ Depends: kernel-image-3.2.0-4-parisc64-di, scsi-modules-3.2.0-4-parisc64-di, usb-modules-3.2.0-4-parisc64-di Description: USB storage support This package contains the USB storage driver for the kernel. -Kernel-Version: 3.2.0-4-parisc64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-parisc64 Package: input-modules-3.2.0-4-parisc64-di Architecture: hppa @@ -3992,8 +3503,8 @@ Depends: kernel-image-3.2.0-4-parisc64-di, usb-modules-3.2.0-4-parisc64-di Description: Input devices support This package contains input device drivers for the kernel. -Kernel-Version: 3.2.0-4-parisc64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-parisc64 Package: crypto-modules-3.2.0-4-parisc64-di Architecture: hppa @@ -4003,8 +3514,8 @@ Depends: kernel-image-3.2.0-4-parisc64-di Description: crypto modules This package contains crypto modules. -Kernel-Version: 3.2.0-4-parisc64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-parisc64 Package: crypto-dm-modules-3.2.0-4-parisc64-di Architecture: hppa @@ -4014,8 +3525,8 @@ Depends: kernel-image-3.2.0-4-parisc64-di, md-modules-3.2.0-4-parisc64-di Description: devicemapper crypto module This package contains the devicemapper crypto (dm-crypt) module. -Kernel-Version: 3.2.0-4-parisc64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-parisc64 Package: nbd-modules-3.2.0-4-parisc64-di Architecture: hppa @@ -4026,8 +3537,8 @@ Description: Network Block Device modules This package contains the modules required for support of the Network Block Device -Kernel-Version: 3.2.0-4-parisc64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-parisc64 Package: zlib-modules-3.2.0-4-parisc64-di Architecture: hppa @@ -4037,8 +3548,8 @@ Depends: kernel-image-3.2.0-4-parisc64-di Description: zlib modules This package contains zlib modules. -Kernel-Version: 3.2.0-4-parisc64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-parisc64 Package: fuse-modules-3.2.0-4-parisc64-di Architecture: hppa @@ -4048,8 +3559,8 @@ Depends: kernel-image-3.2.0-4-parisc64-di Description: FUSE modules This package contains the Filesystem in Userspace (FUSE) module. -Kernel-Version: 3.2.0-4-parisc64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-parisc64 Package: linux-image-3.2.0-4-parisc Architecture: hppa @@ -4160,8 +3671,8 @@ This package contains the kernel image for the Debian installer boot images. It does _not_ provide a usable kernel for your full Debian system. -Kernel-Version: 3.2.0-4-486 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-486 Package: nic-modules-3.2.0-4-486-di Architecture: i386 @@ -4171,8 +3682,8 @@ Depends: kernel-image-3.2.0-4-486-di, nic-shared-modules-3.2.0-4-486-di, core-modules-3.2.0-4-486-di, firewire-core-modules-3.2.0-4-486-di Description: Common NIC drivers This package contains common NIC drivers for the kernel. -Kernel-Version: 3.2.0-4-486 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-486 Package: nic-extra-modules-3.2.0-4-486-di Architecture: i386 @@ -4182,8 +3693,8 @@ Depends: kernel-image-3.2.0-4-486-di, nic-shared-modules-3.2.0-4-486-di, core-modules-3.2.0-4-486-di, i2c-modules-3.2.0-4-486-di, crc-modules-3.2.0-4-486-di Description: Rare NIC drivers This package contains rare NIC drivers for the kernel. -Kernel-Version: 3.2.0-4-486 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-486 Package: nic-wireless-modules-3.2.0-4-486-di Architecture: i386 @@ -4194,8 +3705,8 @@ Description: Wireless NIC drivers This package contains wireless NIC drivers for the kernel. Includes crypto modules only needed for wireless (WEP). -Kernel-Version: 3.2.0-4-486 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-486 Package: nic-shared-modules-3.2.0-4-486-di Architecture: i386 @@ -4206,8 +3717,8 @@ Description: Shared NIC drivers This package contains NIC drivers needed by combinations of nic-modules, nic-extra-modules, nic-pcmcia-modules, and nic-wireless-modules. -Kernel-Version: 3.2.0-4-486 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-486 Package: serial-modules-3.2.0-4-486-di Architecture: i386 @@ -4217,8 +3728,8 @@ Depends: kernel-image-3.2.0-4-486-di, pcmcia-modules-3.2.0-4-486-di Description: Serial drivers This package contains serial drivers for the kernel. -Kernel-Version: 3.2.0-4-486 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-486 Package: usb-serial-modules-3.2.0-4-486-di Architecture: i386 @@ -4228,8 +3739,8 @@ Depends: kernel-image-3.2.0-4-486-di, usb-modules-3.2.0-4-486-di Description: USB serial drivers This package contains USB serial drivers for the kernel. -Kernel-Version: 3.2.0-4-486 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-486 Package: ppp-modules-3.2.0-4-486-di Architecture: i386 @@ -4239,8 +3750,8 @@ Depends: kernel-image-3.2.0-4-486-di, serial-modules-3.2.0-4-486-di, zlib-modules-3.2.0-4-486-di, crc-modules-3.2.0-4-486-di Description: PPP drivers This package contains PPP drivers for the kernel. -Kernel-Version: 3.2.0-4-486 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-486 Package: pata-modules-3.2.0-4-486-di Architecture: i386 @@ -4250,8 +3761,8 @@ Depends: kernel-image-3.2.0-4-486-di, ata-modules-3.2.0-4-486-di Description: PATA drivers This package contains PATA drivers for the kernel. -Kernel-Version: 3.2.0-4-486 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-486 Package: cdrom-core-modules-3.2.0-4-486-di Architecture: i386 @@ -4261,8 +3772,8 @@ Depends: kernel-image-3.2.0-4-486-di, scsi-core-modules-3.2.0-4-486-di, isofs-modules-3.2.0-4-486-di Description: CDROM support This package contains core CDROM support for the kernel. -Kernel-Version: 3.2.0-4-486 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-486 Package: firewire-core-modules-3.2.0-4-486-di Architecture: i386 @@ -4272,8 +3783,8 @@ Depends: kernel-image-3.2.0-4-486-di, scsi-core-modules-3.2.0-4-486-di, crc-modules-3.2.0-4-486-di Description: Core FireWire drivers This package contains core FireWire drivers for the kernel. -Kernel-Version: 3.2.0-4-486 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-486 Package: scsi-core-modules-3.2.0-4-486-di Architecture: i386 @@ -4283,8 +3794,8 @@ Depends: kernel-image-3.2.0-4-486-di Description: Core SCSI subsystem This package contains the core SCSI subsystem for the kernel. -Kernel-Version: 3.2.0-4-486 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-486 Package: scsi-modules-3.2.0-4-486-di Architecture: i386 @@ -4294,8 +3805,8 @@ Depends: kernel-image-3.2.0-4-486-di, scsi-core-modules-3.2.0-4-486-di, parport-modules-3.2.0-4-486-di, cdrom-core-modules-3.2.0-4-486-di, core-modules-3.2.0-4-486-di, ata-modules-3.2.0-4-486-di Description: SCSI drivers This package contains SCSI drivers for the kernel. -Kernel-Version: 3.2.0-4-486 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-486 Package: scsi-common-modules-3.2.0-4-486-di Architecture: i386 @@ -4305,8 +3816,8 @@ Depends: kernel-image-3.2.0-4-486-di, scsi-core-modules-3.2.0-4-486-di, cdrom-core-modules-3.2.0-4-486-di Description: Very common SCSI drivers This package contains very common SCSI drivers for the kernel. -Kernel-Version: 3.2.0-4-486 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-486 Package: scsi-extra-modules-3.2.0-4-486-di Architecture: i386 @@ -4317,8 +3828,8 @@ Description: Uncommon SCSI drivers This package contains uncommon SCSI drivers for the kernel. This includes SCSI RAID drivers, and some of the less common SCSI controllers. -Kernel-Version: 3.2.0-4-486 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-486 Package: plip-modules-3.2.0-4-486-di Architecture: i386 @@ -4328,8 +3839,8 @@ Depends: kernel-image-3.2.0-4-486-di, parport-modules-3.2.0-4-486-di Description: PLIP drivers This package contains PLIP drivers for the kernel. -Kernel-Version: 3.2.0-4-486 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-486 Package: floppy-modules-3.2.0-4-486-di Architecture: i386 @@ -4339,8 +3850,8 @@ Depends: kernel-image-3.2.0-4-486-di Description: Floppy driver This package contains the floppy driver for the kernel. -Kernel-Version: 3.2.0-4-486 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-486 Package: loop-modules-3.2.0-4-486-di Architecture: i386 @@ -4350,8 +3861,8 @@ Depends: kernel-image-3.2.0-4-486-di Description: Loopback filesystem support This package contains loopback filesystem support for the kernel. -Kernel-Version: 3.2.0-4-486 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-486 Package: btrfs-modules-3.2.0-4-486-di Architecture: i386 @@ -4361,8 +3872,8 @@ Depends: kernel-image-3.2.0-4-486-di, core-modules-3.2.0-4-486-di, crc-modules-3.2.0-4-486-di, zlib-modules-3.2.0-4-486-di Description: BTRFS filesystem support This package contains the BTRFS filesystem module for the kernel. -Kernel-Version: 3.2.0-4-486 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-486 Package: ext2-modules-3.2.0-4-486-di Architecture: i386 @@ -4372,8 +3883,8 @@ Depends: kernel-image-3.2.0-4-486-di, core-modules-3.2.0-4-486-di Description: EXT2 filesystem support This package contains the EXT2 filesystem module for the kernel. -Kernel-Version: 3.2.0-4-486 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-486 Package: ext3-modules-3.2.0-4-486-di Architecture: i386 @@ -4383,8 +3894,8 @@ Depends: kernel-image-3.2.0-4-486-di, core-modules-3.2.0-4-486-di Description: EXT3 filesystem support This package contains the EXT3 filesystem module for the kernel. -Kernel-Version: 3.2.0-4-486 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-486 Package: ext4-modules-3.2.0-4-486-di Architecture: i386 @@ -4394,8 +3905,8 @@ Depends: kernel-image-3.2.0-4-486-di, core-modules-3.2.0-4-486-di Description: EXT4 filesystem support This package contains the EXT4 filesystem module for the kernel. -Kernel-Version: 3.2.0-4-486 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-486 Package: isofs-modules-3.2.0-4-486-di Architecture: i386 @@ -4405,8 +3916,8 @@ Depends: kernel-image-3.2.0-4-486-di Description: ISOFS filesystem support This package contains the ISOFS filesystem module for the kernel. -Kernel-Version: 3.2.0-4-486 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-486 Package: jfs-modules-3.2.0-4-486-di Architecture: i386 @@ -4416,8 +3927,8 @@ Depends: kernel-image-3.2.0-4-486-di Description: JFS filesystem support This package contains the JFS filesystem module for the kernel. -Kernel-Version: 3.2.0-4-486 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-486 Package: ntfs-modules-3.2.0-4-486-di Architecture: i386 @@ -4427,8 +3938,8 @@ Depends: kernel-image-3.2.0-4-486-di Description: NTFS filesystem support This package contains the NTFS file system module for the kernel. -Kernel-Version: 3.2.0-4-486 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-486 Package: reiserfs-modules-3.2.0-4-486-di Architecture: i386 @@ -4438,8 +3949,8 @@ Depends: kernel-image-3.2.0-4-486-di Description: Reiser filesystem support This package contains the Reiser filesystem module for the kernel. -Kernel-Version: 3.2.0-4-486 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-486 Package: xfs-modules-3.2.0-4-486-di Architecture: i386 @@ -4449,8 +3960,8 @@ Depends: kernel-image-3.2.0-4-486-di Description: XFS filesystem support This package contains the XFS filesystem module for the kernel. -Kernel-Version: 3.2.0-4-486 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-486 Package: fat-modules-3.2.0-4-486-di Architecture: i386 @@ -4460,8 +3971,8 @@ Depends: kernel-image-3.2.0-4-486-di Description: FAT filesystem support This package contains the FAT and VFAT filesystem modules for the kernel. -Kernel-Version: 3.2.0-4-486 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-486 Package: ufs-modules-3.2.0-4-486-di Architecture: i386 @@ -4471,8 +3982,8 @@ Depends: kernel-image-3.2.0-4-486-di Description: UFS filesystem support This package contains the UFS filesystem module for the kernel. -Kernel-Version: 3.2.0-4-486 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-486 Package: qnx4-modules-3.2.0-4-486-di Architecture: i386 @@ -4482,8 +3993,8 @@ Depends: kernel-image-3.2.0-4-486-di Description: QNX4 filesystem support This package contains the QNX4 filesystem module for the kernel. -Kernel-Version: 3.2.0-4-486 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-486 Package: md-modules-3.2.0-4-486-di Architecture: i386 @@ -4493,8 +4004,8 @@ Depends: kernel-image-3.2.0-4-486-di Description: RAID and LVM support This package contains RAID and LVM modules for the kernel. -Kernel-Version: 3.2.0-4-486 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-486 Package: multipath-modules-3.2.0-4-486-di Architecture: i386 @@ -4504,8 +4015,8 @@ Depends: kernel-image-3.2.0-4-486-di, md-modules-3.2.0-4-486-di, scsi-core-modules-3.2.0-4-486-di Description: Multipath support This package contains DM-Multipath modules for the kernel. -Kernel-Version: 3.2.0-4-486 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-486 Package: usb-modules-3.2.0-4-486-di Architecture: i386 @@ -4515,8 +4026,8 @@ Depends: kernel-image-3.2.0-4-486-di Description: USB support This package contains core USB drivers for the kernel. -Kernel-Version: 3.2.0-4-486 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-486 Package: usb-storage-modules-3.2.0-4-486-di Architecture: i386 @@ -4526,8 +4037,8 @@ Depends: kernel-image-3.2.0-4-486-di, scsi-core-modules-3.2.0-4-486-di, usb-modules-3.2.0-4-486-di Description: USB storage support This package contains the USB storage driver for the kernel. -Kernel-Version: 3.2.0-4-486 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-486 Package: pcmcia-storage-modules-3.2.0-4-486-di Architecture: i386 @@ -4537,8 +4048,8 @@ Depends: kernel-image-3.2.0-4-486-di, cdrom-core-modules-3.2.0-4-486-di, pcmcia-modules-3.2.0-4-486-di, ata-modules-3.2.0-4-486-di Description: PCMCIA storage drivers This package contains PCMCIA storage drivers for the kernel. -Kernel-Version: 3.2.0-4-486 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-486 Package: fb-modules-3.2.0-4-486-di Architecture: i386 @@ -4548,8 +4059,8 @@ Depends: kernel-image-3.2.0-4-486-di, i2c-modules-3.2.0-4-486-di Description: Frame buffer support This package contains Frame buffer drivers for the kernel. -Kernel-Version: 3.2.0-4-486 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-486 Package: input-modules-3.2.0-4-486-di Architecture: i386 @@ -4559,8 +4070,8 @@ Depends: kernel-image-3.2.0-4-486-di, usb-modules-3.2.0-4-486-di Description: Input devices support This package contains input device drivers for the kernel. -Kernel-Version: 3.2.0-4-486 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-486 Package: event-modules-3.2.0-4-486-di Architecture: i386 @@ -4570,8 +4081,8 @@ Depends: kernel-image-3.2.0-4-486-di Description: Event support This package contains event drivers for the kernel. -Kernel-Version: 3.2.0-4-486 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-486 Package: mouse-modules-3.2.0-4-486-di Architecture: i386 @@ -4581,8 +4092,8 @@ Depends: kernel-image-3.2.0-4-486-di, event-modules-3.2.0-4-486-di, input-modules-3.2.0-4-486-di, usb-modules-3.2.0-4-486-di Description: Mouse support This package contains mouse drivers for the kernel. -Kernel-Version: 3.2.0-4-486 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-486 Package: irda-modules-3.2.0-4-486-di Architecture: i386 @@ -4592,8 +4103,8 @@ Depends: kernel-image-3.2.0-4-486-di, ppp-modules-3.2.0-4-486-di, usb-modules-3.2.0-4-486-di Description: Infrared devices support This package contains infrared device drivers for the kernel. -Kernel-Version: 3.2.0-4-486 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-486 Package: parport-modules-3.2.0-4-486-di Architecture: i386 @@ -4603,8 +4114,8 @@ Depends: kernel-image-3.2.0-4-486-di Description: Parallel port support This package contains parallel port drivers for the kernel. -Kernel-Version: 3.2.0-4-486 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-486 Package: nic-pcmcia-modules-3.2.0-4-486-di Architecture: i386 @@ -4614,8 +4125,8 @@ Depends: kernel-image-3.2.0-4-486-di, nic-shared-modules-3.2.0-4-486-di, nic-wireless-modules-3.2.0-4-486-di, pcmcia-modules-3.2.0-4-486-di, mmc-core-modules-3.2.0-4-486-di Description: Common PCMCIA NIC drivers This package contains common PCMCIA NIC drivers for the kernel. -Kernel-Version: 3.2.0-4-486 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-486 Package: pcmcia-modules-3.2.0-4-486-di Architecture: i386 @@ -4625,8 +4136,8 @@ Depends: kernel-image-3.2.0-4-486-di, core-modules-3.2.0-4-486-di Description: Common PCMCIA drivers This package contains common PCMCIA drivers for the kernel. -Kernel-Version: 3.2.0-4-486 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-486 Package: nic-usb-modules-3.2.0-4-486-di Architecture: i386 @@ -4636,8 +4147,8 @@ Depends: kernel-image-3.2.0-4-486-di, nic-shared-modules-3.2.0-4-486-di, nic-wireless-modules-3.2.0-4-486-di, usb-modules-3.2.0-4-486-di, core-modules-3.2.0-4-486-di Description: USB NIC drivers This package contains USB network adapter drivers for the kernel. -Kernel-Version: 3.2.0-4-486 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-486 Package: sata-modules-3.2.0-4-486-di Architecture: i386 @@ -4647,8 +4158,8 @@ Depends: kernel-image-3.2.0-4-486-di, scsi-core-modules-3.2.0-4-486-di, ata-modules-3.2.0-4-486-di Description: SATA drivers This package contains SATA drivers for the kernel. -Kernel-Version: 3.2.0-4-486 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-486 Package: core-modules-3.2.0-4-486-di Architecture: i386 @@ -4659,8 +4170,8 @@ Description: Core modules This package contains core modules for the kernel, that will almost always be needed. -Kernel-Version: 3.2.0-4-486 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-486 Package: acpi-modules-3.2.0-4-486-di Architecture: i386 @@ -4670,8 +4181,8 @@ Depends: kernel-image-3.2.0-4-486-di Description: ACPI support modules This package contains kernel modules for ACPI. -Kernel-Version: 3.2.0-4-486 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-486 Package: i2c-modules-3.2.0-4-486-di Architecture: i386 @@ -4681,8 +4192,8 @@ Depends: kernel-image-3.2.0-4-486-di Description: i2c support modules This package contains basic i2c support modules. -Kernel-Version: 3.2.0-4-486 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-486 Package: crc-modules-3.2.0-4-486-di Architecture: i386 @@ -4692,8 +4203,8 @@ Depends: kernel-image-3.2.0-4-486-di Description: CRC modules This package contains CRC support modules. -Kernel-Version: 3.2.0-4-486 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-486 Package: crypto-modules-3.2.0-4-486-di Architecture: i386 @@ -4703,8 +4214,8 @@ Depends: kernel-image-3.2.0-4-486-di Description: crypto modules This package contains crypto modules. -Kernel-Version: 3.2.0-4-486 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-486 Package: crypto-dm-modules-3.2.0-4-486-di Architecture: i386 @@ -4714,8 +4225,8 @@ Depends: kernel-image-3.2.0-4-486-di, md-modules-3.2.0-4-486-di Description: devicemapper crypto module This package contains the devicemapper crypto (dm-crypt) module. -Kernel-Version: 3.2.0-4-486 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-486 Package: efi-modules-3.2.0-4-486-di Architecture: i386 @@ -4725,8 +4236,8 @@ Depends: kernel-image-3.2.0-4-486-di Description: EFI modules This package contains EFI modules. -Kernel-Version: 3.2.0-4-486 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-486 Package: ata-modules-3.2.0-4-486-di Architecture: i386 @@ -4737,8 +4248,8 @@ Description: ATA disk modules This package contains core ATA disk modules used by both PATA and SATA disk drivers. -Kernel-Version: 3.2.0-4-486 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-486 Package: mmc-core-modules-3.2.0-4-486-di Architecture: i386 @@ -4748,8 +4259,8 @@ Depends: kernel-image-3.2.0-4-486-di, core-modules-3.2.0-4-486-di Description: MMC/SD/SDIO core modules This package contains core modules for MMC/SD/SDIO support. -Kernel-Version: 3.2.0-4-486 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-486 Package: mmc-modules-3.2.0-4-486-di Architecture: i386 @@ -4760,8 +4271,8 @@ Description: MMC/SD card modules This package contains modules needed to support MMC (multimedia) and SD cards. -Kernel-Version: 3.2.0-4-486 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-486 Package: nbd-modules-3.2.0-4-486-di Architecture: i386 @@ -4772,8 +4283,8 @@ Description: Network Block Device modules This package contains the modules required for support of the Network Block Device -Kernel-Version: 3.2.0-4-486 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-486 Package: squashfs-modules-3.2.0-4-486-di Architecture: i386 @@ -4783,8 +4294,8 @@ Depends: kernel-image-3.2.0-4-486-di Description: squashfs modules This package contains squashfs modules. -Kernel-Version: 3.2.0-4-486 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-486 Package: speakup-modules-3.2.0-4-486-di Architecture: i386 @@ -4794,8 +4305,8 @@ Depends: kernel-image-3.2.0-4-486-di Description: speakup modules This package contains speakup modules. -Kernel-Version: 3.2.0-4-486 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-486 Package: virtio-modules-3.2.0-4-486-di Architecture: i386 @@ -4805,8 +4316,8 @@ Depends: kernel-image-3.2.0-4-486-di Description: virtio modules This package contains virtio modules. -Kernel-Version: 3.2.0-4-486 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-486 Package: uinput-modules-3.2.0-4-486-di Architecture: i386 @@ -4816,8 +4327,8 @@ Depends: kernel-image-3.2.0-4-486-di Description: uinput support This package contains the uinput module. -Kernel-Version: 3.2.0-4-486 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-486 Package: sound-modules-3.2.0-4-486-di Architecture: i386 @@ -4827,8 +4338,8 @@ Depends: kernel-image-3.2.0-4-486-di, core-modules-3.2.0-4-486-di, i2c-modules-3.2.0-4-486-di, usb-modules-3.2.0-4-486-di, pcmcia-modules-3.2.0-4-486-di, firewire-core-modules-3.2.0-4-486-di, crc-modules-3.2.0-4-486-di Description: sound support This package contains sound modules. -Kernel-Version: 3.2.0-4-486 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-486 Package: zlib-modules-3.2.0-4-486-di Architecture: i386 @@ -4838,8 +4349,8 @@ Depends: kernel-image-3.2.0-4-486-di Description: zlib modules This package contains zlib modules. -Kernel-Version: 3.2.0-4-486 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-486 Package: hyperv-modules-3.2.0-4-486-di Architecture: i386 @@ -4849,8 +4360,8 @@ Depends: kernel-image-3.2.0-4-486-di, input-modules-3.2.0-4-486-di, scsi-core-modules-3.2.0-4-486-di Description: Hyper-V modules This package contains Hyper-V paravirtualised drivers for the kernel. -Kernel-Version: 3.2.0-4-486 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-486 Package: udf-modules-3.2.0-4-486-di Architecture: i386 @@ -4860,8 +4371,8 @@ Depends: kernel-image-3.2.0-4-486-di, crc-modules-3.2.0-4-486-di Description: UDF modules This package contains the UDF filesystem module. -Kernel-Version: 3.2.0-4-486 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-486 Package: fuse-modules-3.2.0-4-486-di Architecture: i386 @@ -4871,8 +4382,8 @@ Depends: kernel-image-3.2.0-4-486-di Description: FUSE modules This package contains the Filesystem in Userspace (FUSE) module. -Kernel-Version: 3.2.0-4-486 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-486 Package: kernel-image-3.2.0-4-686-pae-di Architecture: i386 @@ -4883,8 +4394,8 @@ This package contains the kernel image for the Debian installer boot images. It does _not_ provide a usable kernel for your full Debian system. -Kernel-Version: 3.2.0-4-686-pae -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-686-pae Package: nic-modules-3.2.0-4-686-pae-di Architecture: i386 @@ -4894,8 +4405,8 @@ Depends: kernel-image-3.2.0-4-686-pae-di, nic-shared-modules-3.2.0-4-686-pae-di, core-modules-3.2.0-4-686-pae-di, firewire-core-modules-3.2.0-4-686-pae-di Description: Common NIC drivers This package contains common NIC drivers for the kernel. -Kernel-Version: 3.2.0-4-686-pae -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-686-pae Package: nic-extra-modules-3.2.0-4-686-pae-di Architecture: i386 @@ -4905,8 +4416,8 @@ Depends: kernel-image-3.2.0-4-686-pae-di, nic-shared-modules-3.2.0-4-686-pae-di, core-modules-3.2.0-4-686-pae-di, i2c-modules-3.2.0-4-686-pae-di, crc-modules-3.2.0-4-686-pae-di Description: Rare NIC drivers This package contains rare NIC drivers for the kernel. -Kernel-Version: 3.2.0-4-686-pae -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-686-pae Package: nic-wireless-modules-3.2.0-4-686-pae-di Architecture: i386 @@ -4917,8 +4428,8 @@ Description: Wireless NIC drivers This package contains wireless NIC drivers for the kernel. Includes crypto modules only needed for wireless (WEP). -Kernel-Version: 3.2.0-4-686-pae -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-686-pae Package: nic-shared-modules-3.2.0-4-686-pae-di Architecture: i386 @@ -4929,8 +4440,8 @@ Description: Shared NIC drivers This package contains NIC drivers needed by combinations of nic-modules, nic-extra-modules, nic-pcmcia-modules, and nic-wireless-modules. -Kernel-Version: 3.2.0-4-686-pae -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-686-pae Package: serial-modules-3.2.0-4-686-pae-di Architecture: i386 @@ -4940,8 +4451,8 @@ Depends: kernel-image-3.2.0-4-686-pae-di, pcmcia-modules-3.2.0-4-686-pae-di Description: Serial drivers This package contains serial drivers for the kernel. -Kernel-Version: 3.2.0-4-686-pae -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-686-pae Package: usb-serial-modules-3.2.0-4-686-pae-di Architecture: i386 @@ -4951,8 +4462,8 @@ Depends: kernel-image-3.2.0-4-686-pae-di, usb-modules-3.2.0-4-686-pae-di Description: USB serial drivers This package contains USB serial drivers for the kernel. -Kernel-Version: 3.2.0-4-686-pae -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-686-pae Package: ppp-modules-3.2.0-4-686-pae-di Architecture: i386 @@ -4962,8 +4473,8 @@ Depends: kernel-image-3.2.0-4-686-pae-di, serial-modules-3.2.0-4-686-pae-di, zlib-modules-3.2.0-4-686-pae-di, crc-modules-3.2.0-4-686-pae-di Description: PPP drivers This package contains PPP drivers for the kernel. -Kernel-Version: 3.2.0-4-686-pae -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-686-pae Package: pata-modules-3.2.0-4-686-pae-di Architecture: i386 @@ -4973,8 +4484,8 @@ Depends: kernel-image-3.2.0-4-686-pae-di, ata-modules-3.2.0-4-686-pae-di Description: PATA drivers This package contains PATA drivers for the kernel. -Kernel-Version: 3.2.0-4-686-pae -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-686-pae Package: cdrom-core-modules-3.2.0-4-686-pae-di Architecture: i386 @@ -4984,8 +4495,8 @@ Depends: kernel-image-3.2.0-4-686-pae-di, scsi-core-modules-3.2.0-4-686-pae-di, isofs-modules-3.2.0-4-686-pae-di Description: CDROM support This package contains core CDROM support for the kernel. -Kernel-Version: 3.2.0-4-686-pae -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-686-pae Package: firewire-core-modules-3.2.0-4-686-pae-di Architecture: i386 @@ -4995,8 +4506,8 @@ Depends: kernel-image-3.2.0-4-686-pae-di, scsi-core-modules-3.2.0-4-686-pae-di, crc-modules-3.2.0-4-686-pae-di Description: Core FireWire drivers This package contains core FireWire drivers for the kernel. -Kernel-Version: 3.2.0-4-686-pae -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-686-pae Package: scsi-core-modules-3.2.0-4-686-pae-di Architecture: i386 @@ -5006,8 +4517,8 @@ Depends: kernel-image-3.2.0-4-686-pae-di Description: Core SCSI subsystem This package contains the core SCSI subsystem for the kernel. -Kernel-Version: 3.2.0-4-686-pae -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-686-pae Package: scsi-modules-3.2.0-4-686-pae-di Architecture: i386 @@ -5017,8 +4528,8 @@ Depends: kernel-image-3.2.0-4-686-pae-di, scsi-core-modules-3.2.0-4-686-pae-di, parport-modules-3.2.0-4-686-pae-di, cdrom-core-modules-3.2.0-4-686-pae-di, core-modules-3.2.0-4-686-pae-di, ata-modules-3.2.0-4-686-pae-di Description: SCSI drivers This package contains SCSI drivers for the kernel. -Kernel-Version: 3.2.0-4-686-pae -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-686-pae Package: scsi-common-modules-3.2.0-4-686-pae-di Architecture: i386 @@ -5028,8 +4539,8 @@ Depends: kernel-image-3.2.0-4-686-pae-di, scsi-core-modules-3.2.0-4-686-pae-di, cdrom-core-modules-3.2.0-4-686-pae-di Description: Very common SCSI drivers This package contains very common SCSI drivers for the kernel. -Kernel-Version: 3.2.0-4-686-pae -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-686-pae Package: scsi-extra-modules-3.2.0-4-686-pae-di Architecture: i386 @@ -5040,8 +4551,8 @@ Description: Uncommon SCSI drivers This package contains uncommon SCSI drivers for the kernel. This includes SCSI RAID drivers, and some of the less common SCSI controllers. -Kernel-Version: 3.2.0-4-686-pae -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-686-pae Package: plip-modules-3.2.0-4-686-pae-di Architecture: i386 @@ -5051,8 +4562,8 @@ Depends: kernel-image-3.2.0-4-686-pae-di, parport-modules-3.2.0-4-686-pae-di Description: PLIP drivers This package contains PLIP drivers for the kernel. -Kernel-Version: 3.2.0-4-686-pae -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-686-pae Package: floppy-modules-3.2.0-4-686-pae-di Architecture: i386 @@ -5062,8 +4573,8 @@ Depends: kernel-image-3.2.0-4-686-pae-di Description: Floppy driver This package contains the floppy driver for the kernel. -Kernel-Version: 3.2.0-4-686-pae -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-686-pae Package: loop-modules-3.2.0-4-686-pae-di Architecture: i386 @@ -5073,8 +4584,8 @@ Depends: kernel-image-3.2.0-4-686-pae-di Description: Loopback filesystem support This package contains loopback filesystem support for the kernel. -Kernel-Version: 3.2.0-4-686-pae -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-686-pae Package: btrfs-modules-3.2.0-4-686-pae-di Architecture: i386 @@ -5084,8 +4595,8 @@ Depends: kernel-image-3.2.0-4-686-pae-di, core-modules-3.2.0-4-686-pae-di, crc-modules-3.2.0-4-686-pae-di, zlib-modules-3.2.0-4-686-pae-di Description: BTRFS filesystem support This package contains the BTRFS filesystem module for the kernel. -Kernel-Version: 3.2.0-4-686-pae -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-686-pae Package: ext2-modules-3.2.0-4-686-pae-di Architecture: i386 @@ -5095,8 +4606,8 @@ Depends: kernel-image-3.2.0-4-686-pae-di, core-modules-3.2.0-4-686-pae-di Description: EXT2 filesystem support This package contains the EXT2 filesystem module for the kernel. -Kernel-Version: 3.2.0-4-686-pae -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-686-pae Package: ext3-modules-3.2.0-4-686-pae-di Architecture: i386 @@ -5106,8 +4617,8 @@ Depends: kernel-image-3.2.0-4-686-pae-di, core-modules-3.2.0-4-686-pae-di Description: EXT3 filesystem support This package contains the EXT3 filesystem module for the kernel. -Kernel-Version: 3.2.0-4-686-pae -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-686-pae Package: ext4-modules-3.2.0-4-686-pae-di Architecture: i386 @@ -5117,8 +4628,8 @@ Depends: kernel-image-3.2.0-4-686-pae-di, core-modules-3.2.0-4-686-pae-di Description: EXT4 filesystem support This package contains the EXT4 filesystem module for the kernel. -Kernel-Version: 3.2.0-4-686-pae -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-686-pae Package: isofs-modules-3.2.0-4-686-pae-di Architecture: i386 @@ -5128,8 +4639,8 @@ Depends: kernel-image-3.2.0-4-686-pae-di Description: ISOFS filesystem support This package contains the ISOFS filesystem module for the kernel. -Kernel-Version: 3.2.0-4-686-pae -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-686-pae Package: jfs-modules-3.2.0-4-686-pae-di Architecture: i386 @@ -5139,8 +4650,8 @@ Depends: kernel-image-3.2.0-4-686-pae-di Description: JFS filesystem support This package contains the JFS filesystem module for the kernel. -Kernel-Version: 3.2.0-4-686-pae -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-686-pae Package: ntfs-modules-3.2.0-4-686-pae-di Architecture: i386 @@ -5150,8 +4661,8 @@ Depends: kernel-image-3.2.0-4-686-pae-di Description: NTFS filesystem support This package contains the NTFS file system module for the kernel. -Kernel-Version: 3.2.0-4-686-pae -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-686-pae Package: reiserfs-modules-3.2.0-4-686-pae-di Architecture: i386 @@ -5161,8 +4672,8 @@ Depends: kernel-image-3.2.0-4-686-pae-di Description: Reiser filesystem support This package contains the Reiser filesystem module for the kernel. -Kernel-Version: 3.2.0-4-686-pae -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-686-pae Package: xfs-modules-3.2.0-4-686-pae-di Architecture: i386 @@ -5172,8 +4683,8 @@ Depends: kernel-image-3.2.0-4-686-pae-di Description: XFS filesystem support This package contains the XFS filesystem module for the kernel. -Kernel-Version: 3.2.0-4-686-pae -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-686-pae Package: fat-modules-3.2.0-4-686-pae-di Architecture: i386 @@ -5183,8 +4694,8 @@ Depends: kernel-image-3.2.0-4-686-pae-di Description: FAT filesystem support This package contains the FAT and VFAT filesystem modules for the kernel. -Kernel-Version: 3.2.0-4-686-pae -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-686-pae Package: ufs-modules-3.2.0-4-686-pae-di Architecture: i386 @@ -5194,8 +4705,8 @@ Depends: kernel-image-3.2.0-4-686-pae-di Description: UFS filesystem support This package contains the UFS filesystem module for the kernel. -Kernel-Version: 3.2.0-4-686-pae -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-686-pae Package: qnx4-modules-3.2.0-4-686-pae-di Architecture: i386 @@ -5205,8 +4716,8 @@ Depends: kernel-image-3.2.0-4-686-pae-di Description: QNX4 filesystem support This package contains the QNX4 filesystem module for the kernel. -Kernel-Version: 3.2.0-4-686-pae -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-686-pae Package: md-modules-3.2.0-4-686-pae-di Architecture: i386 @@ -5216,8 +4727,8 @@ Depends: kernel-image-3.2.0-4-686-pae-di Description: RAID and LVM support This package contains RAID and LVM modules for the kernel. -Kernel-Version: 3.2.0-4-686-pae -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-686-pae Package: multipath-modules-3.2.0-4-686-pae-di Architecture: i386 @@ -5227,8 +4738,8 @@ Depends: kernel-image-3.2.0-4-686-pae-di, md-modules-3.2.0-4-686-pae-di, scsi-core-modules-3.2.0-4-686-pae-di Description: Multipath support This package contains DM-Multipath modules for the kernel. -Kernel-Version: 3.2.0-4-686-pae -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-686-pae Package: usb-modules-3.2.0-4-686-pae-di Architecture: i386 @@ -5238,8 +4749,8 @@ Depends: kernel-image-3.2.0-4-686-pae-di Description: USB support This package contains core USB drivers for the kernel. -Kernel-Version: 3.2.0-4-686-pae -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-686-pae Package: usb-storage-modules-3.2.0-4-686-pae-di Architecture: i386 @@ -5249,8 +4760,8 @@ Depends: kernel-image-3.2.0-4-686-pae-di, scsi-core-modules-3.2.0-4-686-pae-di, usb-modules-3.2.0-4-686-pae-di Description: USB storage support This package contains the USB storage driver for the kernel. -Kernel-Version: 3.2.0-4-686-pae -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-686-pae Package: pcmcia-storage-modules-3.2.0-4-686-pae-di Architecture: i386 @@ -5260,8 +4771,8 @@ Depends: kernel-image-3.2.0-4-686-pae-di, cdrom-core-modules-3.2.0-4-686-pae-di, pcmcia-modules-3.2.0-4-686-pae-di, ata-modules-3.2.0-4-686-pae-di Description: PCMCIA storage drivers This package contains PCMCIA storage drivers for the kernel. -Kernel-Version: 3.2.0-4-686-pae -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-686-pae Package: fb-modules-3.2.0-4-686-pae-di Architecture: i386 @@ -5271,8 +4782,8 @@ Depends: kernel-image-3.2.0-4-686-pae-di, i2c-modules-3.2.0-4-686-pae-di Description: Frame buffer support This package contains Frame buffer drivers for the kernel. -Kernel-Version: 3.2.0-4-686-pae -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-686-pae Package: input-modules-3.2.0-4-686-pae-di Architecture: i386 @@ -5282,8 +4793,8 @@ Depends: kernel-image-3.2.0-4-686-pae-di, usb-modules-3.2.0-4-686-pae-di Description: Input devices support This package contains input device drivers for the kernel. -Kernel-Version: 3.2.0-4-686-pae -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-686-pae Package: event-modules-3.2.0-4-686-pae-di Architecture: i386 @@ -5293,8 +4804,8 @@ Depends: kernel-image-3.2.0-4-686-pae-di Description: Event support This package contains event drivers for the kernel. -Kernel-Version: 3.2.0-4-686-pae -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-686-pae Package: mouse-modules-3.2.0-4-686-pae-di Architecture: i386 @@ -5304,8 +4815,8 @@ Depends: kernel-image-3.2.0-4-686-pae-di, event-modules-3.2.0-4-686-pae-di, input-modules-3.2.0-4-686-pae-di, usb-modules-3.2.0-4-686-pae-di Description: Mouse support This package contains mouse drivers for the kernel. -Kernel-Version: 3.2.0-4-686-pae -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-686-pae Package: irda-modules-3.2.0-4-686-pae-di Architecture: i386 @@ -5315,8 +4826,8 @@ Depends: kernel-image-3.2.0-4-686-pae-di, ppp-modules-3.2.0-4-686-pae-di, usb-modules-3.2.0-4-686-pae-di Description: Infrared devices support This package contains infrared device drivers for the kernel. -Kernel-Version: 3.2.0-4-686-pae -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-686-pae Package: parport-modules-3.2.0-4-686-pae-di Architecture: i386 @@ -5326,8 +4837,8 @@ Depends: kernel-image-3.2.0-4-686-pae-di Description: Parallel port support This package contains parallel port drivers for the kernel. -Kernel-Version: 3.2.0-4-686-pae -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-686-pae Package: nic-pcmcia-modules-3.2.0-4-686-pae-di Architecture: i386 @@ -5337,8 +4848,8 @@ Depends: kernel-image-3.2.0-4-686-pae-di, nic-shared-modules-3.2.0-4-686-pae-di, nic-wireless-modules-3.2.0-4-686-pae-di, pcmcia-modules-3.2.0-4-686-pae-di, mmc-core-modules-3.2.0-4-686-pae-di Description: Common PCMCIA NIC drivers This package contains common PCMCIA NIC drivers for the kernel. -Kernel-Version: 3.2.0-4-686-pae -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-686-pae Package: pcmcia-modules-3.2.0-4-686-pae-di Architecture: i386 @@ -5348,8 +4859,8 @@ Depends: kernel-image-3.2.0-4-686-pae-di, core-modules-3.2.0-4-686-pae-di Description: Common PCMCIA drivers This package contains common PCMCIA drivers for the kernel. -Kernel-Version: 3.2.0-4-686-pae -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-686-pae Package: nic-usb-modules-3.2.0-4-686-pae-di Architecture: i386 @@ -5359,8 +4870,8 @@ Depends: kernel-image-3.2.0-4-686-pae-di, nic-shared-modules-3.2.0-4-686-pae-di, nic-wireless-modules-3.2.0-4-686-pae-di, usb-modules-3.2.0-4-686-pae-di, core-modules-3.2.0-4-686-pae-di Description: USB NIC drivers This package contains USB network adapter drivers for the kernel. -Kernel-Version: 3.2.0-4-686-pae -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-686-pae Package: sata-modules-3.2.0-4-686-pae-di Architecture: i386 @@ -5370,8 +4881,8 @@ Depends: kernel-image-3.2.0-4-686-pae-di, scsi-core-modules-3.2.0-4-686-pae-di, ata-modules-3.2.0-4-686-pae-di Description: SATA drivers This package contains SATA drivers for the kernel. -Kernel-Version: 3.2.0-4-686-pae -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-686-pae Package: core-modules-3.2.0-4-686-pae-di Architecture: i386 @@ -5382,8 +4893,8 @@ Description: Core modules This package contains core modules for the kernel, that will almost always be needed. -Kernel-Version: 3.2.0-4-686-pae -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-686-pae Package: acpi-modules-3.2.0-4-686-pae-di Architecture: i386 @@ -5393,8 +4904,8 @@ Depends: kernel-image-3.2.0-4-686-pae-di Description: ACPI support modules This package contains kernel modules for ACPI. -Kernel-Version: 3.2.0-4-686-pae -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-686-pae Package: i2c-modules-3.2.0-4-686-pae-di Architecture: i386 @@ -5404,8 +4915,8 @@ Depends: kernel-image-3.2.0-4-686-pae-di Description: i2c support modules This package contains basic i2c support modules. -Kernel-Version: 3.2.0-4-686-pae -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-686-pae Package: crc-modules-3.2.0-4-686-pae-di Architecture: i386 @@ -5415,8 +4926,8 @@ Depends: kernel-image-3.2.0-4-686-pae-di Description: CRC modules This package contains CRC support modules. -Kernel-Version: 3.2.0-4-686-pae -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-686-pae Package: crypto-modules-3.2.0-4-686-pae-di Architecture: i386 @@ -5426,8 +4937,8 @@ Depends: kernel-image-3.2.0-4-686-pae-di Description: crypto modules This package contains crypto modules. -Kernel-Version: 3.2.0-4-686-pae -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-686-pae Package: crypto-dm-modules-3.2.0-4-686-pae-di Architecture: i386 @@ -5437,8 +4948,8 @@ Depends: kernel-image-3.2.0-4-686-pae-di, md-modules-3.2.0-4-686-pae-di Description: devicemapper crypto module This package contains the devicemapper crypto (dm-crypt) module. -Kernel-Version: 3.2.0-4-686-pae -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-686-pae Package: efi-modules-3.2.0-4-686-pae-di Architecture: i386 @@ -5448,8 +4959,8 @@ Depends: kernel-image-3.2.0-4-686-pae-di Description: EFI modules This package contains EFI modules. -Kernel-Version: 3.2.0-4-686-pae -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-686-pae Package: ata-modules-3.2.0-4-686-pae-di Architecture: i386 @@ -5460,8 +4971,8 @@ Description: ATA disk modules This package contains core ATA disk modules used by both PATA and SATA disk drivers. -Kernel-Version: 3.2.0-4-686-pae -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-686-pae Package: mmc-core-modules-3.2.0-4-686-pae-di Architecture: i386 @@ -5471,8 +4982,8 @@ Depends: kernel-image-3.2.0-4-686-pae-di, core-modules-3.2.0-4-686-pae-di Description: MMC/SD/SDIO core modules This package contains core modules for MMC/SD/SDIO support. -Kernel-Version: 3.2.0-4-686-pae -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-686-pae Package: mmc-modules-3.2.0-4-686-pae-di Architecture: i386 @@ -5483,8 +4994,8 @@ Description: MMC/SD card modules This package contains modules needed to support MMC (multimedia) and SD cards. -Kernel-Version: 3.2.0-4-686-pae -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-686-pae Package: nbd-modules-3.2.0-4-686-pae-di Architecture: i386 @@ -5495,8 +5006,8 @@ Description: Network Block Device modules This package contains the modules required for support of the Network Block Device -Kernel-Version: 3.2.0-4-686-pae -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-686-pae Package: squashfs-modules-3.2.0-4-686-pae-di Architecture: i386 @@ -5506,8 +5017,8 @@ Depends: kernel-image-3.2.0-4-686-pae-di Description: squashfs modules This package contains squashfs modules. -Kernel-Version: 3.2.0-4-686-pae -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-686-pae Package: speakup-modules-3.2.0-4-686-pae-di Architecture: i386 @@ -5517,8 +5028,8 @@ Depends: kernel-image-3.2.0-4-686-pae-di Description: speakup modules This package contains speakup modules. -Kernel-Version: 3.2.0-4-686-pae -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-686-pae Package: virtio-modules-3.2.0-4-686-pae-di Architecture: i386 @@ -5528,8 +5039,8 @@ Depends: kernel-image-3.2.0-4-686-pae-di Description: virtio modules This package contains virtio modules. -Kernel-Version: 3.2.0-4-686-pae -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-686-pae Package: uinput-modules-3.2.0-4-686-pae-di Architecture: i386 @@ -5539,8 +5050,8 @@ Depends: kernel-image-3.2.0-4-686-pae-di Description: uinput support This package contains the uinput module. -Kernel-Version: 3.2.0-4-686-pae -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-686-pae Package: sound-modules-3.2.0-4-686-pae-di Architecture: i386 @@ -5550,8 +5061,8 @@ Depends: kernel-image-3.2.0-4-686-pae-di, core-modules-3.2.0-4-686-pae-di, i2c-modules-3.2.0-4-686-pae-di, usb-modules-3.2.0-4-686-pae-di, pcmcia-modules-3.2.0-4-686-pae-di, firewire-core-modules-3.2.0-4-686-pae-di, crc-modules-3.2.0-4-686-pae-di Description: sound support This package contains sound modules. -Kernel-Version: 3.2.0-4-686-pae -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-686-pae Package: zlib-modules-3.2.0-4-686-pae-di Architecture: i386 @@ -5561,8 +5072,8 @@ Depends: kernel-image-3.2.0-4-686-pae-di Description: zlib modules This package contains zlib modules. -Kernel-Version: 3.2.0-4-686-pae -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-686-pae Package: hyperv-modules-3.2.0-4-686-pae-di Architecture: i386 @@ -5572,8 +5083,8 @@ Depends: kernel-image-3.2.0-4-686-pae-di, input-modules-3.2.0-4-686-pae-di, scsi-core-modules-3.2.0-4-686-pae-di Description: Hyper-V modules This package contains Hyper-V paravirtualised drivers for the kernel. -Kernel-Version: 3.2.0-4-686-pae -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-686-pae Package: udf-modules-3.2.0-4-686-pae-di Architecture: i386 @@ -5583,8 +5094,8 @@ Depends: kernel-image-3.2.0-4-686-pae-di, crc-modules-3.2.0-4-686-pae-di Description: UDF modules This package contains the UDF filesystem module. -Kernel-Version: 3.2.0-4-686-pae -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-686-pae Package: fuse-modules-3.2.0-4-686-pae-di Architecture: i386 @@ -5594,8 +5105,8 @@ Depends: kernel-image-3.2.0-4-686-pae-di Description: FUSE modules This package contains the Filesystem in Userspace (FUSE) module. -Kernel-Version: 3.2.0-4-686-pae -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-686-pae Package: linux-image-3.2.0-4-486 Architecture: i386 @@ -5727,8 +5238,8 @@ This package contains the kernel image for the Debian installer boot images. It does _not_ provide a usable kernel for your full Debian system. -Kernel-Version: 3.2.0-4-itanium -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-itanium Package: nic-modules-3.2.0-4-itanium-di Architecture: ia64 @@ -5738,8 +5249,8 @@ Depends: kernel-image-3.2.0-4-itanium-di, nic-shared-modules-3.2.0-4-itanium-di, core-modules-3.2.0-4-itanium-di, firewire-core-modules-3.2.0-4-itanium-di, crc-modules-3.2.0-4-itanium-di Description: Common NIC drivers This package contains common NIC drivers for the kernel. -Kernel-Version: 3.2.0-4-itanium -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-itanium Package: nic-shared-modules-3.2.0-4-itanium-di Architecture: ia64 @@ -5750,8 +5261,8 @@ Description: Shared NIC drivers This package contains NIC drivers needed by combinations of nic-modules, nic-extra-modules, nic-pcmcia-modules, and nic-wireless-modules. -Kernel-Version: 3.2.0-4-itanium -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-itanium Package: serial-modules-3.2.0-4-itanium-di Architecture: ia64 @@ -5761,8 +5272,8 @@ Depends: kernel-image-3.2.0-4-itanium-di, pcmcia-modules-3.2.0-4-itanium-di, sn-modules-3.2.0-4-itanium-di Description: Serial drivers This package contains serial drivers for the kernel. -Kernel-Version: 3.2.0-4-itanium -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-itanium Package: ppp-modules-3.2.0-4-itanium-di Architecture: ia64 @@ -5772,8 +5283,8 @@ Depends: kernel-image-3.2.0-4-itanium-di, serial-modules-3.2.0-4-itanium-di, zlib-modules-3.2.0-4-itanium-di, crc-modules-3.2.0-4-itanium-di Description: PPP drivers This package contains PPP drivers for the kernel. -Kernel-Version: 3.2.0-4-itanium -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-itanium Package: ide-modules-3.2.0-4-itanium-di Architecture: ia64 @@ -5783,8 +5294,8 @@ Depends: kernel-image-3.2.0-4-itanium-di, ide-core-modules-3.2.0-4-itanium-di, sn-modules-3.2.0-4-itanium-di Description: IDE drivers This package contains IDE drivers for the kernel. -Kernel-Version: 3.2.0-4-itanium -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-itanium Package: pata-modules-3.2.0-4-itanium-di Architecture: ia64 @@ -5794,8 +5305,8 @@ Depends: kernel-image-3.2.0-4-itanium-di, ata-modules-3.2.0-4-itanium-di Description: PATA drivers This package contains PATA drivers for the kernel. -Kernel-Version: 3.2.0-4-itanium -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-itanium Package: ide-core-modules-3.2.0-4-itanium-di Architecture: ia64 @@ -5805,8 +5316,8 @@ Depends: kernel-image-3.2.0-4-itanium-di Description: IDE support This package contains core IDE support for the kernel. -Kernel-Version: 3.2.0-4-itanium -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-itanium Package: cdrom-core-modules-3.2.0-4-itanium-di Architecture: ia64 @@ -5816,8 +5327,8 @@ Depends: kernel-image-3.2.0-4-itanium-di, scsi-core-modules-3.2.0-4-itanium-di, ide-modules-3.2.0-4-itanium-di, isofs-modules-3.2.0-4-itanium-di Description: CDROM support This package contains core CDROM support for the kernel. -Kernel-Version: 3.2.0-4-itanium -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-itanium Package: firewire-core-modules-3.2.0-4-itanium-di Architecture: ia64 @@ -5827,8 +5338,8 @@ Depends: kernel-image-3.2.0-4-itanium-di, scsi-core-modules-3.2.0-4-itanium-di, crc-modules-3.2.0-4-itanium-di Description: Core FireWire drivers This package contains core FireWire drivers for the kernel. -Kernel-Version: 3.2.0-4-itanium -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-itanium Package: scsi-core-modules-3.2.0-4-itanium-di Architecture: ia64 @@ -5838,8 +5349,8 @@ Depends: kernel-image-3.2.0-4-itanium-di Description: Core SCSI subsystem This package contains the core SCSI subsystem for the kernel. -Kernel-Version: 3.2.0-4-itanium -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-itanium Package: scsi-modules-3.2.0-4-itanium-di Architecture: ia64 @@ -5849,8 +5360,8 @@ Depends: kernel-image-3.2.0-4-itanium-di, scsi-core-modules-3.2.0-4-itanium-di, parport-modules-3.2.0-4-itanium-di, cdrom-core-modules-3.2.0-4-itanium-di, core-modules-3.2.0-4-itanium-di, ata-modules-3.2.0-4-itanium-di Description: SCSI drivers This package contains SCSI drivers for the kernel. -Kernel-Version: 3.2.0-4-itanium -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-itanium Package: plip-modules-3.2.0-4-itanium-di Architecture: ia64 @@ -5860,8 +5371,8 @@ Depends: kernel-image-3.2.0-4-itanium-di, parport-modules-3.2.0-4-itanium-di Description: PLIP drivers This package contains PLIP drivers for the kernel. -Kernel-Version: 3.2.0-4-itanium -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-itanium Package: loop-modules-3.2.0-4-itanium-di Architecture: ia64 @@ -5871,8 +5382,8 @@ Depends: kernel-image-3.2.0-4-itanium-di Description: Loopback filesystem support This package contains loopback filesystem support for the kernel. -Kernel-Version: 3.2.0-4-itanium -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-itanium Package: btrfs-modules-3.2.0-4-itanium-di Architecture: ia64 @@ -5882,8 +5393,8 @@ Depends: kernel-image-3.2.0-4-itanium-di, core-modules-3.2.0-4-itanium-di, crc-modules-3.2.0-4-itanium-di, zlib-modules-3.2.0-4-itanium-di Description: BTRFS filesystem support This package contains the BTRFS filesystem module for the kernel. -Kernel-Version: 3.2.0-4-itanium -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-itanium Package: ext2-modules-3.2.0-4-itanium-di Architecture: ia64 @@ -5893,8 +5404,8 @@ Depends: kernel-image-3.2.0-4-itanium-di, core-modules-3.2.0-4-itanium-di Description: EXT2 filesystem support This package contains the EXT2 filesystem module for the kernel. -Kernel-Version: 3.2.0-4-itanium -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-itanium Package: ext3-modules-3.2.0-4-itanium-di Architecture: ia64 @@ -5904,8 +5415,8 @@ Depends: kernel-image-3.2.0-4-itanium-di, core-modules-3.2.0-4-itanium-di Description: EXT3 filesystem support This package contains the EXT3 filesystem module for the kernel. -Kernel-Version: 3.2.0-4-itanium -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-itanium Package: ext4-modules-3.2.0-4-itanium-di Architecture: ia64 @@ -5915,8 +5426,8 @@ Depends: kernel-image-3.2.0-4-itanium-di, core-modules-3.2.0-4-itanium-di Description: EXT4 filesystem support This package contains the EXT4 filesystem module for the kernel. -Kernel-Version: 3.2.0-4-itanium -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-itanium Package: isofs-modules-3.2.0-4-itanium-di Architecture: ia64 @@ -5926,8 +5437,8 @@ Depends: kernel-image-3.2.0-4-itanium-di Description: ISOFS filesystem support This package contains the ISOFS filesystem module for the kernel. -Kernel-Version: 3.2.0-4-itanium -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-itanium Package: jfs-modules-3.2.0-4-itanium-di Architecture: ia64 @@ -5937,8 +5448,8 @@ Depends: kernel-image-3.2.0-4-itanium-di Description: JFS filesystem support This package contains the JFS filesystem module for the kernel. -Kernel-Version: 3.2.0-4-itanium -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-itanium Package: ntfs-modules-3.2.0-4-itanium-di Architecture: ia64 @@ -5948,8 +5459,8 @@ Depends: kernel-image-3.2.0-4-itanium-di Description: NTFS filesystem support This package contains the NTFS file system module for the kernel. -Kernel-Version: 3.2.0-4-itanium -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-itanium Package: reiserfs-modules-3.2.0-4-itanium-di Architecture: ia64 @@ -5959,8 +5470,8 @@ Depends: kernel-image-3.2.0-4-itanium-di Description: Reiser filesystem support This package contains the Reiser filesystem module for the kernel. -Kernel-Version: 3.2.0-4-itanium -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-itanium Package: xfs-modules-3.2.0-4-itanium-di Architecture: ia64 @@ -5970,8 +5481,8 @@ Depends: kernel-image-3.2.0-4-itanium-di Description: XFS filesystem support This package contains the XFS filesystem module for the kernel. -Kernel-Version: 3.2.0-4-itanium -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-itanium Package: fat-modules-3.2.0-4-itanium-di Architecture: ia64 @@ -5981,8 +5492,8 @@ Depends: kernel-image-3.2.0-4-itanium-di Description: FAT filesystem support This package contains the FAT and VFAT filesystem modules for the kernel. -Kernel-Version: 3.2.0-4-itanium -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-itanium Package: ufs-modules-3.2.0-4-itanium-di Architecture: ia64 @@ -5992,8 +5503,8 @@ Depends: kernel-image-3.2.0-4-itanium-di Description: UFS filesystem support This package contains the UFS filesystem module for the kernel. -Kernel-Version: 3.2.0-4-itanium -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-itanium Package: md-modules-3.2.0-4-itanium-di Architecture: ia64 @@ -6003,8 +5514,8 @@ Depends: kernel-image-3.2.0-4-itanium-di Description: RAID and LVM support This package contains RAID and LVM modules for the kernel. -Kernel-Version: 3.2.0-4-itanium -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-itanium Package: multipath-modules-3.2.0-4-itanium-di Architecture: ia64 @@ -6014,8 +5525,8 @@ Depends: kernel-image-3.2.0-4-itanium-di, md-modules-3.2.0-4-itanium-di, scsi-core-modules-3.2.0-4-itanium-di Description: Multipath support This package contains DM-Multipath modules for the kernel. -Kernel-Version: 3.2.0-4-itanium -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-itanium Package: usb-modules-3.2.0-4-itanium-di Architecture: ia64 @@ -6025,8 +5536,8 @@ Depends: kernel-image-3.2.0-4-itanium-di Description: USB support This package contains core USB drivers for the kernel. -Kernel-Version: 3.2.0-4-itanium -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-itanium Package: usb-storage-modules-3.2.0-4-itanium-di Architecture: ia64 @@ -6036,8 +5547,8 @@ Depends: kernel-image-3.2.0-4-itanium-di, scsi-core-modules-3.2.0-4-itanium-di, usb-modules-3.2.0-4-itanium-di Description: USB storage support This package contains the USB storage driver for the kernel. -Kernel-Version: 3.2.0-4-itanium -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-itanium Package: fb-modules-3.2.0-4-itanium-di Architecture: ia64 @@ -6047,8 +5558,8 @@ Depends: kernel-image-3.2.0-4-itanium-di Description: Frame buffer support This package contains Frame buffer drivers for the kernel. -Kernel-Version: 3.2.0-4-itanium -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-itanium Package: input-modules-3.2.0-4-itanium-di Architecture: ia64 @@ -6058,8 +5569,8 @@ Depends: kernel-image-3.2.0-4-itanium-di, usb-modules-3.2.0-4-itanium-di Description: Input devices support This package contains input device drivers for the kernel. -Kernel-Version: 3.2.0-4-itanium -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-itanium Package: event-modules-3.2.0-4-itanium-di Architecture: ia64 @@ -6069,8 +5580,8 @@ Depends: kernel-image-3.2.0-4-itanium-di Description: Event support This package contains event drivers for the kernel. -Kernel-Version: 3.2.0-4-itanium -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-itanium Package: mouse-modules-3.2.0-4-itanium-di Architecture: ia64 @@ -6080,8 +5591,8 @@ Depends: kernel-image-3.2.0-4-itanium-di, event-modules-3.2.0-4-itanium-di, input-modules-3.2.0-4-itanium-di, usb-modules-3.2.0-4-itanium-di Description: Mouse support This package contains mouse drivers for the kernel. -Kernel-Version: 3.2.0-4-itanium -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-itanium Package: irda-modules-3.2.0-4-itanium-di Architecture: ia64 @@ -6091,8 +5602,8 @@ Depends: kernel-image-3.2.0-4-itanium-di, ppp-modules-3.2.0-4-itanium-di, usb-modules-3.2.0-4-itanium-di Description: Infrared devices support This package contains infrared device drivers for the kernel. -Kernel-Version: 3.2.0-4-itanium -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-itanium Package: parport-modules-3.2.0-4-itanium-di Architecture: ia64 @@ -6102,8 +5613,8 @@ Depends: kernel-image-3.2.0-4-itanium-di Description: Parallel port support This package contains parallel port drivers for the kernel. -Kernel-Version: 3.2.0-4-itanium -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-itanium Package: pcmcia-modules-3.2.0-4-itanium-di Architecture: ia64 @@ -6113,8 +5624,8 @@ Depends: kernel-image-3.2.0-4-itanium-di, core-modules-3.2.0-4-itanium-di Description: Common PCMCIA drivers This package contains common PCMCIA drivers for the kernel. -Kernel-Version: 3.2.0-4-itanium -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-itanium Package: nic-usb-modules-3.2.0-4-itanium-di Architecture: ia64 @@ -6124,8 +5635,8 @@ Depends: kernel-image-3.2.0-4-itanium-di, nic-shared-modules-3.2.0-4-itanium-di, usb-modules-3.2.0-4-itanium-di, core-modules-3.2.0-4-itanium-di Description: USB NIC drivers This package contains USB network adapter drivers for the kernel. -Kernel-Version: 3.2.0-4-itanium -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-itanium Package: sata-modules-3.2.0-4-itanium-di Architecture: ia64 @@ -6135,8 +5646,8 @@ Depends: kernel-image-3.2.0-4-itanium-di, scsi-core-modules-3.2.0-4-itanium-di, ata-modules-3.2.0-4-itanium-di Description: SATA drivers This package contains SATA drivers for the kernel. -Kernel-Version: 3.2.0-4-itanium -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-itanium Package: core-modules-3.2.0-4-itanium-di Architecture: ia64 @@ -6147,8 +5658,8 @@ Description: Core modules This package contains core modules for the kernel, that will almost always be needed. -Kernel-Version: 3.2.0-4-itanium -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-itanium Package: crc-modules-3.2.0-4-itanium-di Architecture: ia64 @@ -6158,8 +5669,8 @@ Depends: kernel-image-3.2.0-4-itanium-di Description: CRC modules This package contains CRC support modules. -Kernel-Version: 3.2.0-4-itanium -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-itanium Package: crypto-modules-3.2.0-4-itanium-di Architecture: ia64 @@ -6169,8 +5680,8 @@ Depends: kernel-image-3.2.0-4-itanium-di Description: crypto modules This package contains crypto modules. -Kernel-Version: 3.2.0-4-itanium -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-itanium Package: crypto-dm-modules-3.2.0-4-itanium-di Architecture: ia64 @@ -6180,8 +5691,8 @@ Depends: kernel-image-3.2.0-4-itanium-di, md-modules-3.2.0-4-itanium-di Description: devicemapper crypto module This package contains the devicemapper crypto (dm-crypt) module. -Kernel-Version: 3.2.0-4-itanium -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-itanium Package: ata-modules-3.2.0-4-itanium-di Architecture: ia64 @@ -6192,8 +5703,8 @@ Description: ATA disk modules This package contains core ATA disk modules used by both PATA and SATA disk drivers. -Kernel-Version: 3.2.0-4-itanium -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-itanium Package: nbd-modules-3.2.0-4-itanium-di Architecture: ia64 @@ -6204,8 +5715,8 @@ Description: Network Block Device modules This package contains the modules required for support of the Network Block Device -Kernel-Version: 3.2.0-4-itanium -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-itanium Package: squashfs-modules-3.2.0-4-itanium-di Architecture: ia64 @@ -6215,8 +5726,8 @@ Depends: kernel-image-3.2.0-4-itanium-di Description: squashfs modules This package contains squashfs modules. -Kernel-Version: 3.2.0-4-itanium -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-itanium Package: uinput-modules-3.2.0-4-itanium-di Architecture: ia64 @@ -6226,8 +5737,8 @@ Depends: kernel-image-3.2.0-4-itanium-di Description: uinput support This package contains the uinput module. -Kernel-Version: 3.2.0-4-itanium -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-itanium Package: zlib-modules-3.2.0-4-itanium-di Architecture: ia64 @@ -6237,8 +5748,8 @@ Depends: kernel-image-3.2.0-4-itanium-di Description: zlib modules This package contains zlib modules. -Kernel-Version: 3.2.0-4-itanium -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-itanium Package: udf-modules-3.2.0-4-itanium-di Architecture: ia64 @@ -6248,8 +5759,8 @@ Depends: kernel-image-3.2.0-4-itanium-di, crc-modules-3.2.0-4-itanium-di Description: UDF modules This package contains the UDF filesystem module. -Kernel-Version: 3.2.0-4-itanium -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-itanium Package: fuse-modules-3.2.0-4-itanium-di Architecture: ia64 @@ -6259,8 +5770,8 @@ Depends: kernel-image-3.2.0-4-itanium-di Description: FUSE modules This package contains the Filesystem in Userspace (FUSE) module. -Kernel-Version: 3.2.0-4-itanium -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-itanium Package: sn-modules-3.2.0-4-itanium-di Architecture: ia64 @@ -6270,8 +5781,8 @@ Depends: kernel-image-3.2.0-4-itanium-di Description: SN modules This package contains SN modules for Altix systems -Kernel-Version: 3.2.0-4-itanium -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-itanium Package: linux-image-3.2.0-4-itanium Architecture: ia64 @@ -6336,8 +5847,8 @@ This package contains the kernel image for the Debian installer boot images. It does _not_ provide a usable kernel for your full Debian system. -Kernel-Version: 3.2.0-4-amiga -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-amiga Package: nic-shared-modules-3.2.0-4-amiga-di Architecture: m68k @@ -6348,8 +5859,8 @@ Description: Shared NIC drivers This package contains NIC drivers needed by combinations of nic-modules, nic-extra-modules, nic-pcmcia-modules, and nic-wireless-modules. -Kernel-Version: 3.2.0-4-amiga -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-amiga Package: ppp-modules-3.2.0-4-amiga-di Architecture: m68k @@ -6359,8 +5870,8 @@ Depends: kernel-image-3.2.0-4-amiga-di, zlib-modules-3.2.0-4-amiga-di Description: PPP drivers This package contains PPP drivers for the kernel. -Kernel-Version: 3.2.0-4-amiga -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-amiga Package: cdrom-core-modules-3.2.0-4-amiga-di Architecture: m68k @@ -6370,8 +5881,8 @@ Depends: kernel-image-3.2.0-4-amiga-di, isofs-modules-3.2.0-4-amiga-di Description: CDROM support This package contains core CDROM support for the kernel. -Kernel-Version: 3.2.0-4-amiga -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-amiga Package: scsi-modules-3.2.0-4-amiga-di Architecture: m68k @@ -6381,8 +5892,8 @@ Depends: kernel-image-3.2.0-4-amiga-di, cdrom-core-modules-3.2.0-4-amiga-di Description: SCSI drivers This package contains SCSI drivers for the kernel. -Kernel-Version: 3.2.0-4-amiga -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-amiga Package: ipv6-modules-3.2.0-4-amiga-di Architecture: m68k @@ -6392,8 +5903,8 @@ Depends: kernel-image-3.2.0-4-amiga-di Description: IPv6 driver This package contains the IPv6 driver for the kernel. -Kernel-Version: 3.2.0-4-amiga -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-amiga Package: btrfs-modules-3.2.0-4-amiga-di Architecture: m68k @@ -6403,8 +5914,8 @@ Depends: kernel-image-3.2.0-4-amiga-di, zlib-modules-3.2.0-4-amiga-di Description: BTRFS filesystem support This package contains the BTRFS filesystem module for the kernel. -Kernel-Version: 3.2.0-4-amiga -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-amiga Package: isofs-modules-3.2.0-4-amiga-di Architecture: m68k @@ -6414,8 +5925,8 @@ Depends: kernel-image-3.2.0-4-amiga-di Description: ISOFS filesystem support This package contains the ISOFS filesystem module for the kernel. -Kernel-Version: 3.2.0-4-amiga -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-amiga Package: jfs-modules-3.2.0-4-amiga-di Architecture: m68k @@ -6425,8 +5936,8 @@ Depends: kernel-image-3.2.0-4-amiga-di Description: JFS filesystem support This package contains the JFS filesystem module for the kernel. -Kernel-Version: 3.2.0-4-amiga -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-amiga Package: reiserfs-modules-3.2.0-4-amiga-di Architecture: m68k @@ -6436,8 +5947,8 @@ Depends: kernel-image-3.2.0-4-amiga-di Description: Reiser filesystem support This package contains the Reiser filesystem module for the kernel. -Kernel-Version: 3.2.0-4-amiga -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-amiga Package: fat-modules-3.2.0-4-amiga-di Architecture: m68k @@ -6447,8 +5958,8 @@ Depends: kernel-image-3.2.0-4-amiga-di Description: FAT filesystem support This package contains the FAT and VFAT filesystem modules for the kernel. -Kernel-Version: 3.2.0-4-amiga -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-amiga Package: md-modules-3.2.0-4-amiga-di Architecture: m68k @@ -6458,8 +5969,8 @@ Depends: kernel-image-3.2.0-4-amiga-di Description: RAID and LVM support This package contains RAID and LVM modules for the kernel. -Kernel-Version: 3.2.0-4-amiga -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-amiga Package: crypto-modules-3.2.0-4-amiga-di Architecture: m68k @@ -6469,8 +5980,8 @@ Depends: kernel-image-3.2.0-4-amiga-di Description: crypto modules This package contains crypto modules. -Kernel-Version: 3.2.0-4-amiga -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-amiga Package: nbd-modules-3.2.0-4-amiga-di Architecture: m68k @@ -6481,8 +5992,8 @@ Description: Network Block Device modules This package contains the modules required for support of the Network Block Device -Kernel-Version: 3.2.0-4-amiga -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-amiga Package: squashfs-modules-3.2.0-4-amiga-di Architecture: m68k @@ -6492,8 +6003,8 @@ Depends: kernel-image-3.2.0-4-amiga-di Description: squashfs modules This package contains squashfs modules. -Kernel-Version: 3.2.0-4-amiga -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-amiga Package: zlib-modules-3.2.0-4-amiga-di Architecture: m68k @@ -6503,8 +6014,8 @@ Depends: kernel-image-3.2.0-4-amiga-di Description: zlib modules This package contains zlib modules. -Kernel-Version: 3.2.0-4-amiga -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-amiga Package: udf-modules-3.2.0-4-amiga-di Architecture: m68k @@ -6514,8 +6025,8 @@ Depends: kernel-image-3.2.0-4-amiga-di Description: UDF modules This package contains the UDF filesystem module. -Kernel-Version: 3.2.0-4-amiga -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-amiga Package: fuse-modules-3.2.0-4-amiga-di Architecture: m68k @@ -6525,8 +6036,8 @@ Depends: kernel-image-3.2.0-4-amiga-di Description: FUSE modules This package contains the Filesystem in Userspace (FUSE) module. -Kernel-Version: 3.2.0-4-amiga -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-amiga Package: kernel-image-3.2.0-4-atari-di Architecture: m68k @@ -6537,8 +6048,8 @@ This package contains the kernel image for the Debian installer boot images. It does _not_ provide a usable kernel for your full Debian system. -Kernel-Version: 3.2.0-4-atari -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-atari Package: nic-shared-modules-3.2.0-4-atari-di Architecture: m68k @@ -6549,8 +6060,8 @@ Description: Shared NIC drivers This package contains NIC drivers needed by combinations of nic-modules, nic-extra-modules, nic-pcmcia-modules, and nic-wireless-modules. -Kernel-Version: 3.2.0-4-atari -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-atari Package: ppp-modules-3.2.0-4-atari-di Architecture: m68k @@ -6560,8 +6071,8 @@ Depends: kernel-image-3.2.0-4-atari-di, zlib-modules-3.2.0-4-atari-di Description: PPP drivers This package contains PPP drivers for the kernel. -Kernel-Version: 3.2.0-4-atari -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-atari Package: cdrom-core-modules-3.2.0-4-atari-di Architecture: m68k @@ -6571,8 +6082,8 @@ Depends: kernel-image-3.2.0-4-atari-di, isofs-modules-3.2.0-4-atari-di Description: CDROM support This package contains core CDROM support for the kernel. -Kernel-Version: 3.2.0-4-atari -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-atari Package: scsi-modules-3.2.0-4-atari-di Architecture: m68k @@ -6582,8 +6093,8 @@ Depends: kernel-image-3.2.0-4-atari-di, cdrom-core-modules-3.2.0-4-atari-di Description: SCSI drivers This package contains SCSI drivers for the kernel. -Kernel-Version: 3.2.0-4-atari -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-atari Package: ipv6-modules-3.2.0-4-atari-di Architecture: m68k @@ -6593,8 +6104,8 @@ Depends: kernel-image-3.2.0-4-atari-di Description: IPv6 driver This package contains the IPv6 driver for the kernel. -Kernel-Version: 3.2.0-4-atari -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-atari Package: btrfs-modules-3.2.0-4-atari-di Architecture: m68k @@ -6604,8 +6115,8 @@ Depends: kernel-image-3.2.0-4-atari-di, zlib-modules-3.2.0-4-atari-di Description: BTRFS filesystem support This package contains the BTRFS filesystem module for the kernel. -Kernel-Version: 3.2.0-4-atari -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-atari Package: isofs-modules-3.2.0-4-atari-di Architecture: m68k @@ -6615,8 +6126,8 @@ Depends: kernel-image-3.2.0-4-atari-di Description: ISOFS filesystem support This package contains the ISOFS filesystem module for the kernel. -Kernel-Version: 3.2.0-4-atari -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-atari Package: jfs-modules-3.2.0-4-atari-di Architecture: m68k @@ -6626,8 +6137,8 @@ Depends: kernel-image-3.2.0-4-atari-di Description: JFS filesystem support This package contains the JFS filesystem module for the kernel. -Kernel-Version: 3.2.0-4-atari -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-atari Package: reiserfs-modules-3.2.0-4-atari-di Architecture: m68k @@ -6637,8 +6148,8 @@ Depends: kernel-image-3.2.0-4-atari-di Description: Reiser filesystem support This package contains the Reiser filesystem module for the kernel. -Kernel-Version: 3.2.0-4-atari -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-atari Package: fat-modules-3.2.0-4-atari-di Architecture: m68k @@ -6648,8 +6159,8 @@ Depends: kernel-image-3.2.0-4-atari-di Description: FAT filesystem support This package contains the FAT and VFAT filesystem modules for the kernel. -Kernel-Version: 3.2.0-4-atari -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-atari Package: md-modules-3.2.0-4-atari-di Architecture: m68k @@ -6659,8 +6170,8 @@ Depends: kernel-image-3.2.0-4-atari-di Description: RAID and LVM support This package contains RAID and LVM modules for the kernel. -Kernel-Version: 3.2.0-4-atari -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-atari Package: crypto-modules-3.2.0-4-atari-di Architecture: m68k @@ -6670,8 +6181,8 @@ Depends: kernel-image-3.2.0-4-atari-di Description: crypto modules This package contains crypto modules. -Kernel-Version: 3.2.0-4-atari -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-atari Package: nbd-modules-3.2.0-4-atari-di Architecture: m68k @@ -6682,8 +6193,8 @@ Description: Network Block Device modules This package contains the modules required for support of the Network Block Device -Kernel-Version: 3.2.0-4-atari -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-atari Package: squashfs-modules-3.2.0-4-atari-di Architecture: m68k @@ -6693,8 +6204,8 @@ Depends: kernel-image-3.2.0-4-atari-di Description: squashfs modules This package contains squashfs modules. -Kernel-Version: 3.2.0-4-atari -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-atari Package: zlib-modules-3.2.0-4-atari-di Architecture: m68k @@ -6704,8 +6215,8 @@ Depends: kernel-image-3.2.0-4-atari-di Description: zlib modules This package contains zlib modules. -Kernel-Version: 3.2.0-4-atari -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-atari Package: udf-modules-3.2.0-4-atari-di Architecture: m68k @@ -6715,8 +6226,8 @@ Depends: kernel-image-3.2.0-4-atari-di Description: UDF modules This package contains the UDF filesystem module. -Kernel-Version: 3.2.0-4-atari -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-atari Package: fuse-modules-3.2.0-4-atari-di Architecture: m68k @@ -6726,8 +6237,8 @@ Depends: kernel-image-3.2.0-4-atari-di Description: FUSE modules This package contains the Filesystem in Userspace (FUSE) module. -Kernel-Version: 3.2.0-4-atari -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-atari Package: kernel-image-3.2.0-4-mac-di Architecture: m68k @@ -6738,8 +6249,8 @@ This package contains the kernel image for the Debian installer boot images. It does _not_ provide a usable kernel for your full Debian system. -Kernel-Version: 3.2.0-4-mac -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-mac Package: nic-shared-modules-3.2.0-4-mac-di Architecture: m68k @@ -6750,8 +6261,8 @@ Description: Shared NIC drivers This package contains NIC drivers needed by combinations of nic-modules, nic-extra-modules, nic-pcmcia-modules, and nic-wireless-modules. -Kernel-Version: 3.2.0-4-mac -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-mac Package: ppp-modules-3.2.0-4-mac-di Architecture: m68k @@ -6761,8 +6272,8 @@ Depends: kernel-image-3.2.0-4-mac-di, zlib-modules-3.2.0-4-mac-di Description: PPP drivers This package contains PPP drivers for the kernel. -Kernel-Version: 3.2.0-4-mac -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-mac Package: cdrom-core-modules-3.2.0-4-mac-di Architecture: m68k @@ -6772,8 +6283,8 @@ Depends: kernel-image-3.2.0-4-mac-di, isofs-modules-3.2.0-4-mac-di Description: CDROM support This package contains core CDROM support for the kernel. -Kernel-Version: 3.2.0-4-mac -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-mac Package: scsi-modules-3.2.0-4-mac-di Architecture: m68k @@ -6783,8 +6294,8 @@ Depends: kernel-image-3.2.0-4-mac-di, cdrom-core-modules-3.2.0-4-mac-di Description: SCSI drivers This package contains SCSI drivers for the kernel. -Kernel-Version: 3.2.0-4-mac -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-mac Package: ipv6-modules-3.2.0-4-mac-di Architecture: m68k @@ -6794,8 +6305,8 @@ Depends: kernel-image-3.2.0-4-mac-di Description: IPv6 driver This package contains the IPv6 driver for the kernel. -Kernel-Version: 3.2.0-4-mac -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-mac Package: btrfs-modules-3.2.0-4-mac-di Architecture: m68k @@ -6805,8 +6316,8 @@ Depends: kernel-image-3.2.0-4-mac-di, zlib-modules-3.2.0-4-mac-di Description: BTRFS filesystem support This package contains the BTRFS filesystem module for the kernel. -Kernel-Version: 3.2.0-4-mac -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-mac Package: isofs-modules-3.2.0-4-mac-di Architecture: m68k @@ -6816,8 +6327,8 @@ Depends: kernel-image-3.2.0-4-mac-di Description: ISOFS filesystem support This package contains the ISOFS filesystem module for the kernel. -Kernel-Version: 3.2.0-4-mac -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-mac Package: jfs-modules-3.2.0-4-mac-di Architecture: m68k @@ -6827,8 +6338,8 @@ Depends: kernel-image-3.2.0-4-mac-di Description: JFS filesystem support This package contains the JFS filesystem module for the kernel. -Kernel-Version: 3.2.0-4-mac -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-mac Package: reiserfs-modules-3.2.0-4-mac-di Architecture: m68k @@ -6838,8 +6349,8 @@ Depends: kernel-image-3.2.0-4-mac-di Description: Reiser filesystem support This package contains the Reiser filesystem module for the kernel. -Kernel-Version: 3.2.0-4-mac -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-mac Package: fat-modules-3.2.0-4-mac-di Architecture: m68k @@ -6849,8 +6360,8 @@ Depends: kernel-image-3.2.0-4-mac-di Description: FAT filesystem support This package contains the FAT and VFAT filesystem modules for the kernel. -Kernel-Version: 3.2.0-4-mac -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-mac Package: md-modules-3.2.0-4-mac-di Architecture: m68k @@ -6860,8 +6371,8 @@ Depends: kernel-image-3.2.0-4-mac-di Description: RAID and LVM support This package contains RAID and LVM modules for the kernel. -Kernel-Version: 3.2.0-4-mac -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-mac Package: crypto-modules-3.2.0-4-mac-di Architecture: m68k @@ -6871,8 +6382,8 @@ Depends: kernel-image-3.2.0-4-mac-di Description: crypto modules This package contains crypto modules. -Kernel-Version: 3.2.0-4-mac -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-mac Package: nbd-modules-3.2.0-4-mac-di Architecture: m68k @@ -6883,8 +6394,8 @@ Description: Network Block Device modules This package contains the modules required for support of the Network Block Device -Kernel-Version: 3.2.0-4-mac -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-mac Package: squashfs-modules-3.2.0-4-mac-di Architecture: m68k @@ -6894,8 +6405,8 @@ Depends: kernel-image-3.2.0-4-mac-di Description: squashfs modules This package contains squashfs modules. -Kernel-Version: 3.2.0-4-mac -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-mac Package: zlib-modules-3.2.0-4-mac-di Architecture: m68k @@ -6905,8 +6416,8 @@ Depends: kernel-image-3.2.0-4-mac-di Description: zlib modules This package contains zlib modules. -Kernel-Version: 3.2.0-4-mac -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-mac Package: udf-modules-3.2.0-4-mac-di Architecture: m68k @@ -6916,8 +6427,8 @@ Depends: kernel-image-3.2.0-4-mac-di Description: UDF modules This package contains the UDF filesystem module. -Kernel-Version: 3.2.0-4-mac -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-mac Package: fuse-modules-3.2.0-4-mac-di Architecture: m68k @@ -6927,8 +6438,8 @@ Depends: kernel-image-3.2.0-4-mac-di Description: FUSE modules This package contains the Filesystem in Userspace (FUSE) module. -Kernel-Version: 3.2.0-4-mac -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-mac Package: linux-image-3.2.0-4-amiga Architecture: m68k @@ -7085,8 +6596,8 @@ This package contains the kernel image for the Debian installer boot images. It does _not_ provide a usable kernel for your full Debian system. -Kernel-Version: 3.2.0-4-sb1-bcm91250a -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-sb1-bcm91250a Package: nic-shared-modules-3.2.0-4-sb1-bcm91250a-di Architecture: mips mipsel @@ -7097,8 +6608,8 @@ Description: Shared NIC drivers This package contains NIC drivers needed by combinations of nic-modules, nic-extra-modules, nic-pcmcia-modules, and nic-wireless-modules. -Kernel-Version: 3.2.0-4-sb1-bcm91250a -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-sb1-bcm91250a Package: ppp-modules-3.2.0-4-sb1-bcm91250a-di Architecture: mips mipsel @@ -7108,8 +6619,8 @@ Depends: kernel-image-3.2.0-4-sb1-bcm91250a-di, zlib-modules-3.2.0-4-sb1-bcm91250a-di Description: PPP drivers This package contains PPP drivers for the kernel. -Kernel-Version: 3.2.0-4-sb1-bcm91250a -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-sb1-bcm91250a Package: cdrom-core-modules-3.2.0-4-sb1-bcm91250a-di Architecture: mips mipsel @@ -7119,8 +6630,8 @@ Depends: kernel-image-3.2.0-4-sb1-bcm91250a-di, scsi-core-modules-3.2.0-4-sb1-bcm91250a-di, isofs-modules-3.2.0-4-sb1-bcm91250a-di Description: CDROM support This package contains core CDROM support for the kernel. -Kernel-Version: 3.2.0-4-sb1-bcm91250a -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-sb1-bcm91250a Package: scsi-core-modules-3.2.0-4-sb1-bcm91250a-di Architecture: mips mipsel @@ -7130,8 +6641,8 @@ Depends: kernel-image-3.2.0-4-sb1-bcm91250a-di Description: Core SCSI subsystem This package contains the core SCSI subsystem for the kernel. -Kernel-Version: 3.2.0-4-sb1-bcm91250a -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-sb1-bcm91250a Package: scsi-modules-3.2.0-4-sb1-bcm91250a-di Architecture: mips mipsel @@ -7141,8 +6652,8 @@ Depends: kernel-image-3.2.0-4-sb1-bcm91250a-di, scsi-core-modules-3.2.0-4-sb1-bcm91250a-di, cdrom-core-modules-3.2.0-4-sb1-bcm91250a-di Description: SCSI drivers This package contains SCSI drivers for the kernel. -Kernel-Version: 3.2.0-4-sb1-bcm91250a -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-sb1-bcm91250a Package: scsi-common-modules-3.2.0-4-sb1-bcm91250a-di Architecture: mips mipsel @@ -7152,8 +6663,8 @@ Depends: kernel-image-3.2.0-4-sb1-bcm91250a-di, scsi-core-modules-3.2.0-4-sb1-bcm91250a-di, cdrom-core-modules-3.2.0-4-sb1-bcm91250a-di Description: Very common SCSI drivers This package contains very common SCSI drivers for the kernel. -Kernel-Version: 3.2.0-4-sb1-bcm91250a -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-sb1-bcm91250a Package: loop-modules-3.2.0-4-sb1-bcm91250a-di Architecture: mips mipsel @@ -7163,8 +6674,8 @@ Depends: kernel-image-3.2.0-4-sb1-bcm91250a-di Description: Loopback filesystem support This package contains loopback filesystem support for the kernel. -Kernel-Version: 3.2.0-4-sb1-bcm91250a -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-sb1-bcm91250a Package: ipv6-modules-3.2.0-4-sb1-bcm91250a-di Architecture: mips mipsel @@ -7174,8 +6685,8 @@ Depends: kernel-image-3.2.0-4-sb1-bcm91250a-di Description: IPv6 driver This package contains the IPv6 driver for the kernel. -Kernel-Version: 3.2.0-4-sb1-bcm91250a -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-sb1-bcm91250a Package: btrfs-modules-3.2.0-4-sb1-bcm91250a-di Architecture: mips mipsel @@ -7185,8 +6696,8 @@ Depends: kernel-image-3.2.0-4-sb1-bcm91250a-di, zlib-modules-3.2.0-4-sb1-bcm91250a-di Description: BTRFS filesystem support This package contains the BTRFS filesystem module for the kernel. -Kernel-Version: 3.2.0-4-sb1-bcm91250a -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-sb1-bcm91250a Package: isofs-modules-3.2.0-4-sb1-bcm91250a-di Architecture: mips mipsel @@ -7196,8 +6707,8 @@ Depends: kernel-image-3.2.0-4-sb1-bcm91250a-di Description: ISOFS filesystem support This package contains the ISOFS filesystem module for the kernel. -Kernel-Version: 3.2.0-4-sb1-bcm91250a -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-sb1-bcm91250a Package: jfs-modules-3.2.0-4-sb1-bcm91250a-di Architecture: mips mipsel @@ -7207,8 +6718,8 @@ Depends: kernel-image-3.2.0-4-sb1-bcm91250a-di Description: JFS filesystem support This package contains the JFS filesystem module for the kernel. -Kernel-Version: 3.2.0-4-sb1-bcm91250a -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-sb1-bcm91250a Package: reiserfs-modules-3.2.0-4-sb1-bcm91250a-di Architecture: mips mipsel @@ -7218,8 +6729,8 @@ Depends: kernel-image-3.2.0-4-sb1-bcm91250a-di Description: Reiser filesystem support This package contains the Reiser filesystem module for the kernel. -Kernel-Version: 3.2.0-4-sb1-bcm91250a -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-sb1-bcm91250a Package: xfs-modules-3.2.0-4-sb1-bcm91250a-di Architecture: mips mipsel @@ -7229,8 +6740,8 @@ Depends: kernel-image-3.2.0-4-sb1-bcm91250a-di Description: XFS filesystem support This package contains the XFS filesystem module for the kernel. -Kernel-Version: 3.2.0-4-sb1-bcm91250a -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-sb1-bcm91250a Package: fat-modules-3.2.0-4-sb1-bcm91250a-di Architecture: mips mipsel @@ -7240,8 +6751,8 @@ Depends: kernel-image-3.2.0-4-sb1-bcm91250a-di Description: FAT filesystem support This package contains the FAT and VFAT filesystem modules for the kernel. -Kernel-Version: 3.2.0-4-sb1-bcm91250a -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-sb1-bcm91250a Package: md-modules-3.2.0-4-sb1-bcm91250a-di Architecture: mips mipsel @@ -7251,8 +6762,8 @@ Depends: kernel-image-3.2.0-4-sb1-bcm91250a-di Description: RAID and LVM support This package contains RAID and LVM modules for the kernel. -Kernel-Version: 3.2.0-4-sb1-bcm91250a -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-sb1-bcm91250a Package: multipath-modules-3.2.0-4-sb1-bcm91250a-di Architecture: mips mipsel @@ -7262,8 +6773,8 @@ Depends: kernel-image-3.2.0-4-sb1-bcm91250a-di, md-modules-3.2.0-4-sb1-bcm91250a-di, scsi-core-modules-3.2.0-4-sb1-bcm91250a-di Description: Multipath support This package contains DM-Multipath modules for the kernel. -Kernel-Version: 3.2.0-4-sb1-bcm91250a -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-sb1-bcm91250a Package: usb-modules-3.2.0-4-sb1-bcm91250a-di Architecture: mips mipsel @@ -7273,8 +6784,8 @@ Depends: kernel-image-3.2.0-4-sb1-bcm91250a-di Description: USB support This package contains core USB drivers for the kernel. -Kernel-Version: 3.2.0-4-sb1-bcm91250a -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-sb1-bcm91250a Package: usb-storage-modules-3.2.0-4-sb1-bcm91250a-di Architecture: mips mipsel @@ -7284,8 +6795,8 @@ Depends: kernel-image-3.2.0-4-sb1-bcm91250a-di, scsi-core-modules-3.2.0-4-sb1-bcm91250a-di, usb-modules-3.2.0-4-sb1-bcm91250a-di Description: USB storage support This package contains the USB storage driver for the kernel. -Kernel-Version: 3.2.0-4-sb1-bcm91250a -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-sb1-bcm91250a Package: fb-modules-3.2.0-4-sb1-bcm91250a-di Architecture: mips mipsel @@ -7295,8 +6806,8 @@ Depends: kernel-image-3.2.0-4-sb1-bcm91250a-di Description: Frame buffer support This package contains Frame buffer drivers for the kernel. -Kernel-Version: 3.2.0-4-sb1-bcm91250a -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-sb1-bcm91250a Package: input-modules-3.2.0-4-sb1-bcm91250a-di Architecture: mips mipsel @@ -7306,8 +6817,8 @@ Depends: kernel-image-3.2.0-4-sb1-bcm91250a-di, usb-modules-3.2.0-4-sb1-bcm91250a-di Description: Input devices support This package contains input device drivers for the kernel. -Kernel-Version: 3.2.0-4-sb1-bcm91250a -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-sb1-bcm91250a Package: sata-modules-3.2.0-4-sb1-bcm91250a-di Architecture: mips mipsel @@ -7317,8 +6828,8 @@ Depends: kernel-image-3.2.0-4-sb1-bcm91250a-di, scsi-core-modules-3.2.0-4-sb1-bcm91250a-di Description: SATA drivers This package contains SATA drivers for the kernel. -Kernel-Version: 3.2.0-4-sb1-bcm91250a -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-sb1-bcm91250a Package: crypto-modules-3.2.0-4-sb1-bcm91250a-di Architecture: mips mipsel @@ -7328,8 +6839,8 @@ Depends: kernel-image-3.2.0-4-sb1-bcm91250a-di Description: crypto modules This package contains crypto modules. -Kernel-Version: 3.2.0-4-sb1-bcm91250a -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-sb1-bcm91250a Package: crypto-dm-modules-3.2.0-4-sb1-bcm91250a-di Architecture: mips mipsel @@ -7339,8 +6850,8 @@ Depends: kernel-image-3.2.0-4-sb1-bcm91250a-di, md-modules-3.2.0-4-sb1-bcm91250a-di Description: devicemapper crypto module This package contains the devicemapper crypto (dm-crypt) module. -Kernel-Version: 3.2.0-4-sb1-bcm91250a -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-sb1-bcm91250a Package: nbd-modules-3.2.0-4-sb1-bcm91250a-di Architecture: mips mipsel @@ -7351,8 +6862,8 @@ Description: Network Block Device modules This package contains the modules required for support of the Network Block Device -Kernel-Version: 3.2.0-4-sb1-bcm91250a -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-sb1-bcm91250a Package: squashfs-modules-3.2.0-4-sb1-bcm91250a-di Architecture: mips mipsel @@ -7362,8 +6873,8 @@ Depends: kernel-image-3.2.0-4-sb1-bcm91250a-di Description: squashfs modules This package contains squashfs modules. -Kernel-Version: 3.2.0-4-sb1-bcm91250a -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-sb1-bcm91250a Package: rtc-modules-3.2.0-4-sb1-bcm91250a-di Architecture: mips mipsel @@ -7373,8 +6884,8 @@ Depends: kernel-image-3.2.0-4-sb1-bcm91250a-di Description: RTC modules This package contains RTC modules. -Kernel-Version: 3.2.0-4-sb1-bcm91250a -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-sb1-bcm91250a Package: zlib-modules-3.2.0-4-sb1-bcm91250a-di Architecture: mips mipsel @@ -7384,8 +6895,8 @@ Depends: kernel-image-3.2.0-4-sb1-bcm91250a-di Description: zlib modules This package contains zlib modules. -Kernel-Version: 3.2.0-4-sb1-bcm91250a -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-sb1-bcm91250a Package: udf-modules-3.2.0-4-sb1-bcm91250a-di Architecture: mips mipsel @@ -7395,8 +6906,8 @@ Depends: kernel-image-3.2.0-4-sb1-bcm91250a-di Description: UDF modules This package contains the UDF filesystem module. -Kernel-Version: 3.2.0-4-sb1-bcm91250a -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-sb1-bcm91250a Package: fuse-modules-3.2.0-4-sb1-bcm91250a-di Architecture: mips mipsel @@ -7406,8 +6917,8 @@ Depends: kernel-image-3.2.0-4-sb1-bcm91250a-di Description: FUSE modules This package contains the Filesystem in Userspace (FUSE) module. -Kernel-Version: 3.2.0-4-sb1-bcm91250a -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-sb1-bcm91250a Package: kernel-image-3.2.0-4-r4k-ip22-di Architecture: mips @@ -7418,8 +6929,8 @@ This package contains the kernel image for the Debian installer boot images. It does _not_ provide a usable kernel for your full Debian system. -Kernel-Version: 3.2.0-4-r4k-ip22 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-r4k-ip22 Package: nic-shared-modules-3.2.0-4-r4k-ip22-di Architecture: mips @@ -7430,8 +6941,8 @@ Description: Shared NIC drivers This package contains NIC drivers needed by combinations of nic-modules, nic-extra-modules, nic-pcmcia-modules, and nic-wireless-modules. -Kernel-Version: 3.2.0-4-r4k-ip22 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-r4k-ip22 Package: loop-modules-3.2.0-4-r4k-ip22-di Architecture: mips @@ -7441,8 +6952,8 @@ Depends: kernel-image-3.2.0-4-r4k-ip22-di Description: Loopback filesystem support This package contains loopback filesystem support for the kernel. -Kernel-Version: 3.2.0-4-r4k-ip22 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-r4k-ip22 Package: ipv6-modules-3.2.0-4-r4k-ip22-di Architecture: mips @@ -7452,8 +6963,8 @@ Depends: kernel-image-3.2.0-4-r4k-ip22-di Description: IPv6 driver This package contains the IPv6 driver for the kernel. -Kernel-Version: 3.2.0-4-r4k-ip22 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-r4k-ip22 Package: btrfs-modules-3.2.0-4-r4k-ip22-di Architecture: mips @@ -7463,8 +6974,8 @@ Depends: kernel-image-3.2.0-4-r4k-ip22-di, zlib-modules-3.2.0-4-r4k-ip22-di Description: BTRFS filesystem support This package contains the BTRFS filesystem module for the kernel. -Kernel-Version: 3.2.0-4-r4k-ip22 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-r4k-ip22 Package: isofs-modules-3.2.0-4-r4k-ip22-di Architecture: mips @@ -7474,8 +6985,8 @@ Depends: kernel-image-3.2.0-4-r4k-ip22-di Description: ISOFS filesystem support This package contains the ISOFS filesystem module for the kernel. -Kernel-Version: 3.2.0-4-r4k-ip22 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-r4k-ip22 Package: jfs-modules-3.2.0-4-r4k-ip22-di Architecture: mips @@ -7485,8 +6996,8 @@ Depends: kernel-image-3.2.0-4-r4k-ip22-di Description: JFS filesystem support This package contains the JFS filesystem module for the kernel. -Kernel-Version: 3.2.0-4-r4k-ip22 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-r4k-ip22 Package: reiserfs-modules-3.2.0-4-r4k-ip22-di Architecture: mips @@ -7496,8 +7007,8 @@ Depends: kernel-image-3.2.0-4-r4k-ip22-di Description: Reiser filesystem support This package contains the Reiser filesystem module for the kernel. -Kernel-Version: 3.2.0-4-r4k-ip22 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-r4k-ip22 Package: xfs-modules-3.2.0-4-r4k-ip22-di Architecture: mips @@ -7507,8 +7018,8 @@ Depends: kernel-image-3.2.0-4-r4k-ip22-di Description: XFS filesystem support This package contains the XFS filesystem module for the kernel. -Kernel-Version: 3.2.0-4-r4k-ip22 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-r4k-ip22 Package: md-modules-3.2.0-4-r4k-ip22-di Architecture: mips @@ -7518,8 +7029,8 @@ Depends: kernel-image-3.2.0-4-r4k-ip22-di Description: RAID and LVM support This package contains RAID and LVM modules for the kernel. -Kernel-Version: 3.2.0-4-r4k-ip22 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-r4k-ip22 Package: multipath-modules-3.2.0-4-r4k-ip22-di Architecture: mips @@ -7529,8 +7040,8 @@ Depends: kernel-image-3.2.0-4-r4k-ip22-di, md-modules-3.2.0-4-r4k-ip22-di Description: Multipath support This package contains DM-Multipath modules for the kernel. -Kernel-Version: 3.2.0-4-r4k-ip22 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-r4k-ip22 Package: crypto-modules-3.2.0-4-r4k-ip22-di Architecture: mips @@ -7540,8 +7051,8 @@ Depends: kernel-image-3.2.0-4-r4k-ip22-di Description: crypto modules This package contains crypto modules. -Kernel-Version: 3.2.0-4-r4k-ip22 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-r4k-ip22 Package: crypto-dm-modules-3.2.0-4-r4k-ip22-di Architecture: mips @@ -7551,8 +7062,8 @@ Depends: kernel-image-3.2.0-4-r4k-ip22-di, md-modules-3.2.0-4-r4k-ip22-di Description: devicemapper crypto module This package contains the devicemapper crypto (dm-crypt) module. -Kernel-Version: 3.2.0-4-r4k-ip22 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-r4k-ip22 Package: nbd-modules-3.2.0-4-r4k-ip22-di Architecture: mips @@ -7563,8 +7074,8 @@ Description: Network Block Device modules This package contains the modules required for support of the Network Block Device -Kernel-Version: 3.2.0-4-r4k-ip22 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-r4k-ip22 Package: squashfs-modules-3.2.0-4-r4k-ip22-di Architecture: mips @@ -7574,8 +7085,8 @@ Depends: kernel-image-3.2.0-4-r4k-ip22-di Description: squashfs modules This package contains squashfs modules. -Kernel-Version: 3.2.0-4-r4k-ip22 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-r4k-ip22 Package: zlib-modules-3.2.0-4-r4k-ip22-di Architecture: mips @@ -7585,8 +7096,8 @@ Depends: kernel-image-3.2.0-4-r4k-ip22-di Description: zlib modules This package contains zlib modules. -Kernel-Version: 3.2.0-4-r4k-ip22 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-r4k-ip22 Package: udf-modules-3.2.0-4-r4k-ip22-di Architecture: mips @@ -7596,8 +7107,8 @@ Depends: kernel-image-3.2.0-4-r4k-ip22-di Description: UDF modules This package contains the UDF filesystem module. -Kernel-Version: 3.2.0-4-r4k-ip22 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-r4k-ip22 Package: fuse-modules-3.2.0-4-r4k-ip22-di Architecture: mips @@ -7607,8 +7118,8 @@ Depends: kernel-image-3.2.0-4-r4k-ip22-di Description: FUSE modules This package contains the Filesystem in Userspace (FUSE) module. -Kernel-Version: 3.2.0-4-r4k-ip22 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-r4k-ip22 Package: kernel-image-3.2.0-4-r5k-ip32-di Architecture: mips @@ -7619,8 +7130,8 @@ This package contains the kernel image for the Debian installer boot images. It does _not_ provide a usable kernel for your full Debian system. -Kernel-Version: 3.2.0-4-r5k-ip32 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-r5k-ip32 Package: nic-shared-modules-3.2.0-4-r5k-ip32-di Architecture: mips @@ -7631,8 +7142,8 @@ Description: Shared NIC drivers This package contains NIC drivers needed by combinations of nic-modules, nic-extra-modules, nic-pcmcia-modules, and nic-wireless-modules. -Kernel-Version: 3.2.0-4-r5k-ip32 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-r5k-ip32 Package: loop-modules-3.2.0-4-r5k-ip32-di Architecture: mips @@ -7642,8 +7153,8 @@ Depends: kernel-image-3.2.0-4-r5k-ip32-di Description: Loopback filesystem support This package contains loopback filesystem support for the kernel. -Kernel-Version: 3.2.0-4-r5k-ip32 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-r5k-ip32 Package: ipv6-modules-3.2.0-4-r5k-ip32-di Architecture: mips @@ -7653,8 +7164,8 @@ Depends: kernel-image-3.2.0-4-r5k-ip32-di Description: IPv6 driver This package contains the IPv6 driver for the kernel. -Kernel-Version: 3.2.0-4-r5k-ip32 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-r5k-ip32 Package: btrfs-modules-3.2.0-4-r5k-ip32-di Architecture: mips @@ -7664,8 +7175,8 @@ Depends: kernel-image-3.2.0-4-r5k-ip32-di, zlib-modules-3.2.0-4-r5k-ip32-di Description: BTRFS filesystem support This package contains the BTRFS filesystem module for the kernel. -Kernel-Version: 3.2.0-4-r5k-ip32 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-r5k-ip32 Package: isofs-modules-3.2.0-4-r5k-ip32-di Architecture: mips @@ -7675,8 +7186,8 @@ Depends: kernel-image-3.2.0-4-r5k-ip32-di Description: ISOFS filesystem support This package contains the ISOFS filesystem module for the kernel. -Kernel-Version: 3.2.0-4-r5k-ip32 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-r5k-ip32 Package: jfs-modules-3.2.0-4-r5k-ip32-di Architecture: mips @@ -7686,8 +7197,8 @@ Depends: kernel-image-3.2.0-4-r5k-ip32-di Description: JFS filesystem support This package contains the JFS filesystem module for the kernel. -Kernel-Version: 3.2.0-4-r5k-ip32 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-r5k-ip32 Package: reiserfs-modules-3.2.0-4-r5k-ip32-di Architecture: mips @@ -7697,8 +7208,8 @@ Depends: kernel-image-3.2.0-4-r5k-ip32-di Description: Reiser filesystem support This package contains the Reiser filesystem module for the kernel. -Kernel-Version: 3.2.0-4-r5k-ip32 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-r5k-ip32 Package: xfs-modules-3.2.0-4-r5k-ip32-di Architecture: mips @@ -7708,8 +7219,8 @@ Depends: kernel-image-3.2.0-4-r5k-ip32-di Description: XFS filesystem support This package contains the XFS filesystem module for the kernel. -Kernel-Version: 3.2.0-4-r5k-ip32 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-r5k-ip32 Package: md-modules-3.2.0-4-r5k-ip32-di Architecture: mips @@ -7719,8 +7230,8 @@ Depends: kernel-image-3.2.0-4-r5k-ip32-di Description: RAID and LVM support This package contains RAID and LVM modules for the kernel. -Kernel-Version: 3.2.0-4-r5k-ip32 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-r5k-ip32 Package: multipath-modules-3.2.0-4-r5k-ip32-di Architecture: mips @@ -7730,8 +7241,8 @@ Depends: kernel-image-3.2.0-4-r5k-ip32-di, md-modules-3.2.0-4-r5k-ip32-di Description: Multipath support This package contains DM-Multipath modules for the kernel. -Kernel-Version: 3.2.0-4-r5k-ip32 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-r5k-ip32 Package: crypto-modules-3.2.0-4-r5k-ip32-di Architecture: mips @@ -7741,8 +7252,8 @@ Depends: kernel-image-3.2.0-4-r5k-ip32-di Description: crypto modules This package contains crypto modules. -Kernel-Version: 3.2.0-4-r5k-ip32 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-r5k-ip32 Package: crypto-dm-modules-3.2.0-4-r5k-ip32-di Architecture: mips @@ -7752,8 +7263,8 @@ Depends: kernel-image-3.2.0-4-r5k-ip32-di, md-modules-3.2.0-4-r5k-ip32-di Description: devicemapper crypto module This package contains the devicemapper crypto (dm-crypt) module. -Kernel-Version: 3.2.0-4-r5k-ip32 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-r5k-ip32 Package: nbd-modules-3.2.0-4-r5k-ip32-di Architecture: mips @@ -7764,8 +7275,8 @@ Description: Network Block Device modules This package contains the modules required for support of the Network Block Device -Kernel-Version: 3.2.0-4-r5k-ip32 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-r5k-ip32 Package: squashfs-modules-3.2.0-4-r5k-ip32-di Architecture: mips @@ -7775,8 +7286,8 @@ Depends: kernel-image-3.2.0-4-r5k-ip32-di Description: squashfs modules This package contains squashfs modules. -Kernel-Version: 3.2.0-4-r5k-ip32 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-r5k-ip32 Package: zlib-modules-3.2.0-4-r5k-ip32-di Architecture: mips @@ -7786,8 +7297,8 @@ Depends: kernel-image-3.2.0-4-r5k-ip32-di Description: zlib modules This package contains zlib modules. -Kernel-Version: 3.2.0-4-r5k-ip32 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-r5k-ip32 Package: udf-modules-3.2.0-4-r5k-ip32-di Architecture: mips @@ -7797,8 +7308,8 @@ Depends: kernel-image-3.2.0-4-r5k-ip32-di Description: UDF modules This package contains the UDF filesystem module. -Kernel-Version: 3.2.0-4-r5k-ip32 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-r5k-ip32 Package: fuse-modules-3.2.0-4-r5k-ip32-di Architecture: mips @@ -7808,8 +7319,8 @@ Depends: kernel-image-3.2.0-4-r5k-ip32-di Description: FUSE modules This package contains the Filesystem in Userspace (FUSE) module. -Kernel-Version: 3.2.0-4-r5k-ip32 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-r5k-ip32 Package: kernel-image-3.2.0-4-4kc-malta-di Architecture: mips mipsel @@ -7820,8 +7331,8 @@ This package contains the kernel image for the Debian installer boot images. It does _not_ provide a usable kernel for your full Debian system. -Kernel-Version: 3.2.0-4-4kc-malta -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-4kc-malta Package: ppp-modules-3.2.0-4-4kc-malta-di Architecture: mips mipsel @@ -7831,8 +7342,8 @@ Depends: kernel-image-3.2.0-4-4kc-malta-di, zlib-modules-3.2.0-4-4kc-malta-di Description: PPP drivers This package contains PPP drivers for the kernel. -Kernel-Version: 3.2.0-4-4kc-malta -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-4kc-malta Package: cdrom-core-modules-3.2.0-4-4kc-malta-di Architecture: mips mipsel @@ -7842,8 +7353,8 @@ Depends: kernel-image-3.2.0-4-4kc-malta-di, isofs-modules-3.2.0-4-4kc-malta-di Description: CDROM support This package contains core CDROM support for the kernel. -Kernel-Version: 3.2.0-4-4kc-malta -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-4kc-malta Package: loop-modules-3.2.0-4-4kc-malta-di Architecture: mips mipsel @@ -7853,8 +7364,8 @@ Depends: kernel-image-3.2.0-4-4kc-malta-di Description: Loopback filesystem support This package contains loopback filesystem support for the kernel. -Kernel-Version: 3.2.0-4-4kc-malta -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-4kc-malta Package: ipv6-modules-3.2.0-4-4kc-malta-di Architecture: mips mipsel @@ -7864,8 +7375,8 @@ Depends: kernel-image-3.2.0-4-4kc-malta-di Description: IPv6 driver This package contains the IPv6 driver for the kernel. -Kernel-Version: 3.2.0-4-4kc-malta -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-4kc-malta Package: btrfs-modules-3.2.0-4-4kc-malta-di Architecture: mips mipsel @@ -7875,8 +7386,8 @@ Depends: kernel-image-3.2.0-4-4kc-malta-di, zlib-modules-3.2.0-4-4kc-malta-di Description: BTRFS filesystem support This package contains the BTRFS filesystem module for the kernel. -Kernel-Version: 3.2.0-4-4kc-malta -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-4kc-malta Package: isofs-modules-3.2.0-4-4kc-malta-di Architecture: mips mipsel @@ -7886,8 +7397,8 @@ Depends: kernel-image-3.2.0-4-4kc-malta-di Description: ISOFS filesystem support This package contains the ISOFS filesystem module for the kernel. -Kernel-Version: 3.2.0-4-4kc-malta -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-4kc-malta Package: jfs-modules-3.2.0-4-4kc-malta-di Architecture: mips mipsel @@ -7897,8 +7408,8 @@ Depends: kernel-image-3.2.0-4-4kc-malta-di Description: JFS filesystem support This package contains the JFS filesystem module for the kernel. -Kernel-Version: 3.2.0-4-4kc-malta -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-4kc-malta Package: reiserfs-modules-3.2.0-4-4kc-malta-di Architecture: mips mipsel @@ -7908,8 +7419,8 @@ Depends: kernel-image-3.2.0-4-4kc-malta-di Description: Reiser filesystem support This package contains the Reiser filesystem module for the kernel. -Kernel-Version: 3.2.0-4-4kc-malta -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-4kc-malta Package: xfs-modules-3.2.0-4-4kc-malta-di Architecture: mips mipsel @@ -7919,8 +7430,8 @@ Depends: kernel-image-3.2.0-4-4kc-malta-di Description: XFS filesystem support This package contains the XFS filesystem module for the kernel. -Kernel-Version: 3.2.0-4-4kc-malta -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-4kc-malta Package: fat-modules-3.2.0-4-4kc-malta-di Architecture: mips mipsel @@ -7930,8 +7441,8 @@ Depends: kernel-image-3.2.0-4-4kc-malta-di Description: FAT filesystem support This package contains the FAT and VFAT filesystem modules for the kernel. -Kernel-Version: 3.2.0-4-4kc-malta -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-4kc-malta Package: md-modules-3.2.0-4-4kc-malta-di Architecture: mips mipsel @@ -7941,8 +7452,8 @@ Depends: kernel-image-3.2.0-4-4kc-malta-di Description: RAID and LVM support This package contains RAID and LVM modules for the kernel. -Kernel-Version: 3.2.0-4-4kc-malta -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-4kc-malta Package: multipath-modules-3.2.0-4-4kc-malta-di Architecture: mips mipsel @@ -7952,8 +7463,8 @@ Depends: kernel-image-3.2.0-4-4kc-malta-di, md-modules-3.2.0-4-4kc-malta-di Description: Multipath support This package contains DM-Multipath modules for the kernel. -Kernel-Version: 3.2.0-4-4kc-malta -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-4kc-malta Package: usb-modules-3.2.0-4-4kc-malta-di Architecture: mips mipsel @@ -7963,8 +7474,8 @@ Depends: kernel-image-3.2.0-4-4kc-malta-di Description: USB support This package contains core USB drivers for the kernel. -Kernel-Version: 3.2.0-4-4kc-malta -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-4kc-malta Package: usb-storage-modules-3.2.0-4-4kc-malta-di Architecture: mips mipsel @@ -7974,8 +7485,8 @@ Depends: kernel-image-3.2.0-4-4kc-malta-di, usb-modules-3.2.0-4-4kc-malta-di Description: USB storage support This package contains the USB storage driver for the kernel. -Kernel-Version: 3.2.0-4-4kc-malta -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-4kc-malta Package: input-modules-3.2.0-4-4kc-malta-di Architecture: mips mipsel @@ -7985,8 +7496,8 @@ Depends: kernel-image-3.2.0-4-4kc-malta-di, usb-modules-3.2.0-4-4kc-malta-di Description: Input devices support This package contains input device drivers for the kernel. -Kernel-Version: 3.2.0-4-4kc-malta -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-4kc-malta Package: sata-modules-3.2.0-4-4kc-malta-di Architecture: mips mipsel @@ -7996,8 +7507,8 @@ Depends: kernel-image-3.2.0-4-4kc-malta-di Description: SATA drivers This package contains SATA drivers for the kernel. -Kernel-Version: 3.2.0-4-4kc-malta -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-4kc-malta Package: crypto-modules-3.2.0-4-4kc-malta-di Architecture: mips mipsel @@ -8007,8 +7518,8 @@ Depends: kernel-image-3.2.0-4-4kc-malta-di Description: crypto modules This package contains crypto modules. -Kernel-Version: 3.2.0-4-4kc-malta -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-4kc-malta Package: crypto-dm-modules-3.2.0-4-4kc-malta-di Architecture: mips mipsel @@ -8018,8 +7529,8 @@ Depends: kernel-image-3.2.0-4-4kc-malta-di, md-modules-3.2.0-4-4kc-malta-di Description: devicemapper crypto module This package contains the devicemapper crypto (dm-crypt) module. -Kernel-Version: 3.2.0-4-4kc-malta -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-4kc-malta Package: nbd-modules-3.2.0-4-4kc-malta-di Architecture: mips mipsel @@ -8030,8 +7541,8 @@ Description: Network Block Device modules This package contains the modules required for support of the Network Block Device -Kernel-Version: 3.2.0-4-4kc-malta -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-4kc-malta Package: squashfs-modules-3.2.0-4-4kc-malta-di Architecture: mips mipsel @@ -8041,8 +7552,8 @@ Depends: kernel-image-3.2.0-4-4kc-malta-di Description: squashfs modules This package contains squashfs modules. -Kernel-Version: 3.2.0-4-4kc-malta -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-4kc-malta Package: virtio-modules-3.2.0-4-4kc-malta-di Architecture: mips mipsel @@ -8052,8 +7563,8 @@ Depends: kernel-image-3.2.0-4-4kc-malta-di Description: virtio modules This package contains virtio modules. -Kernel-Version: 3.2.0-4-4kc-malta -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-4kc-malta Package: zlib-modules-3.2.0-4-4kc-malta-di Architecture: mips mipsel @@ -8063,8 +7574,8 @@ Depends: kernel-image-3.2.0-4-4kc-malta-di Description: zlib modules This package contains zlib modules. -Kernel-Version: 3.2.0-4-4kc-malta -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-4kc-malta Package: udf-modules-3.2.0-4-4kc-malta-di Architecture: mips mipsel @@ -8074,8 +7585,8 @@ Depends: kernel-image-3.2.0-4-4kc-malta-di Description: UDF modules This package contains the UDF filesystem module. -Kernel-Version: 3.2.0-4-4kc-malta -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-4kc-malta Package: fuse-modules-3.2.0-4-4kc-malta-di Architecture: mips mipsel @@ -8085,8 +7596,8 @@ Depends: kernel-image-3.2.0-4-4kc-malta-di Description: FUSE modules This package contains the Filesystem in Userspace (FUSE) module. -Kernel-Version: 3.2.0-4-4kc-malta -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-4kc-malta Package: linux-image-3.2.0-4-r4k-ip22 Architecture: mips @@ -8269,8 +7780,8 @@ This package contains the kernel image for the Debian installer boot images. It does _not_ provide a usable kernel for your full Debian system. -Kernel-Version: 3.2.0-4-r5k-cobalt -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-r5k-cobalt Package: nic-shared-modules-3.2.0-4-r5k-cobalt-di Architecture: mipsel @@ -8281,8 +7792,8 @@ Description: Shared NIC drivers This package contains NIC drivers needed by combinations of nic-modules, nic-extra-modules, nic-pcmcia-modules, and nic-wireless-modules. -Kernel-Version: 3.2.0-4-r5k-cobalt -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-r5k-cobalt Package: ppp-modules-3.2.0-4-r5k-cobalt-di Architecture: mipsel @@ -8292,8 +7803,8 @@ Depends: kernel-image-3.2.0-4-r5k-cobalt-di, zlib-modules-3.2.0-4-r5k-cobalt-di Description: PPP drivers This package contains PPP drivers for the kernel. -Kernel-Version: 3.2.0-4-r5k-cobalt -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-r5k-cobalt Package: loop-modules-3.2.0-4-r5k-cobalt-di Architecture: mipsel @@ -8303,8 +7814,8 @@ Depends: kernel-image-3.2.0-4-r5k-cobalt-di Description: Loopback filesystem support This package contains loopback filesystem support for the kernel. -Kernel-Version: 3.2.0-4-r5k-cobalt -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-r5k-cobalt Package: ipv6-modules-3.2.0-4-r5k-cobalt-di Architecture: mipsel @@ -8314,8 +7825,8 @@ Depends: kernel-image-3.2.0-4-r5k-cobalt-di Description: IPv6 driver This package contains the IPv6 driver for the kernel. -Kernel-Version: 3.2.0-4-r5k-cobalt -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-r5k-cobalt Package: btrfs-modules-3.2.0-4-r5k-cobalt-di Architecture: mipsel @@ -8325,8 +7836,8 @@ Depends: kernel-image-3.2.0-4-r5k-cobalt-di, zlib-modules-3.2.0-4-r5k-cobalt-di Description: BTRFS filesystem support This package contains the BTRFS filesystem module for the kernel. -Kernel-Version: 3.2.0-4-r5k-cobalt -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-r5k-cobalt Package: jfs-modules-3.2.0-4-r5k-cobalt-di Architecture: mipsel @@ -8336,8 +7847,8 @@ Depends: kernel-image-3.2.0-4-r5k-cobalt-di Description: JFS filesystem support This package contains the JFS filesystem module for the kernel. -Kernel-Version: 3.2.0-4-r5k-cobalt -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-r5k-cobalt Package: reiserfs-modules-3.2.0-4-r5k-cobalt-di Architecture: mipsel @@ -8347,8 +7858,8 @@ Depends: kernel-image-3.2.0-4-r5k-cobalt-di Description: Reiser filesystem support This package contains the Reiser filesystem module for the kernel. -Kernel-Version: 3.2.0-4-r5k-cobalt -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-r5k-cobalt Package: xfs-modules-3.2.0-4-r5k-cobalt-di Architecture: mipsel @@ -8358,8 +7869,8 @@ Depends: kernel-image-3.2.0-4-r5k-cobalt-di Description: XFS filesystem support This package contains the XFS filesystem module for the kernel. -Kernel-Version: 3.2.0-4-r5k-cobalt -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-r5k-cobalt Package: fat-modules-3.2.0-4-r5k-cobalt-di Architecture: mipsel @@ -8369,8 +7880,8 @@ Depends: kernel-image-3.2.0-4-r5k-cobalt-di Description: FAT filesystem support This package contains the FAT and VFAT filesystem modules for the kernel. -Kernel-Version: 3.2.0-4-r5k-cobalt -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-r5k-cobalt Package: nfs-modules-3.2.0-4-r5k-cobalt-di Architecture: mipsel @@ -8380,8 +7891,8 @@ Depends: kernel-image-3.2.0-4-r5k-cobalt-di Description: NFS filesystem support This package contains the NFS filesystem module for the kernel. -Kernel-Version: 3.2.0-4-r5k-cobalt -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-r5k-cobalt Package: md-modules-3.2.0-4-r5k-cobalt-di Architecture: mipsel @@ -8391,8 +7902,8 @@ Depends: kernel-image-3.2.0-4-r5k-cobalt-di Description: RAID and LVM support This package contains RAID and LVM modules for the kernel. -Kernel-Version: 3.2.0-4-r5k-cobalt -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-r5k-cobalt Package: multipath-modules-3.2.0-4-r5k-cobalt-di Architecture: mipsel @@ -8402,8 +7913,8 @@ Depends: kernel-image-3.2.0-4-r5k-cobalt-di, md-modules-3.2.0-4-r5k-cobalt-di Description: Multipath support This package contains DM-Multipath modules for the kernel. -Kernel-Version: 3.2.0-4-r5k-cobalt -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-r5k-cobalt Package: crypto-modules-3.2.0-4-r5k-cobalt-di Architecture: mipsel @@ -8413,8 +7924,8 @@ Depends: kernel-image-3.2.0-4-r5k-cobalt-di Description: crypto modules This package contains crypto modules. -Kernel-Version: 3.2.0-4-r5k-cobalt -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-r5k-cobalt Package: crypto-dm-modules-3.2.0-4-r5k-cobalt-di Architecture: mipsel @@ -8424,8 +7935,8 @@ Depends: kernel-image-3.2.0-4-r5k-cobalt-di, md-modules-3.2.0-4-r5k-cobalt-di Description: devicemapper crypto module This package contains the devicemapper crypto (dm-crypt) module. -Kernel-Version: 3.2.0-4-r5k-cobalt -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-r5k-cobalt Package: nbd-modules-3.2.0-4-r5k-cobalt-di Architecture: mipsel @@ -8436,8 +7947,8 @@ Description: Network Block Device modules This package contains the modules required for support of the Network Block Device -Kernel-Version: 3.2.0-4-r5k-cobalt -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-r5k-cobalt Package: squashfs-modules-3.2.0-4-r5k-cobalt-di Architecture: mipsel @@ -8447,8 +7958,8 @@ Depends: kernel-image-3.2.0-4-r5k-cobalt-di Description: squashfs modules This package contains squashfs modules. -Kernel-Version: 3.2.0-4-r5k-cobalt -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-r5k-cobalt Package: zlib-modules-3.2.0-4-r5k-cobalt-di Architecture: mipsel @@ -8458,8 +7969,8 @@ Depends: kernel-image-3.2.0-4-r5k-cobalt-di Description: zlib modules This package contains zlib modules. -Kernel-Version: 3.2.0-4-r5k-cobalt -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-r5k-cobalt Package: fuse-modules-3.2.0-4-r5k-cobalt-di Architecture: mipsel @@ -8469,8 +7980,8 @@ Depends: kernel-image-3.2.0-4-r5k-cobalt-di Description: FUSE modules This package contains the Filesystem in Userspace (FUSE) module. -Kernel-Version: 3.2.0-4-r5k-cobalt -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-r5k-cobalt Package: kernel-image-3.2.0-4-loongson-2f-di Architecture: mipsel @@ -8481,8 +7992,8 @@ This package contains the kernel image for the Debian installer boot images. It does _not_ provide a usable kernel for your full Debian system. -Kernel-Version: 3.2.0-4-loongson-2f -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-loongson-2f Package: nic-modules-3.2.0-4-loongson-2f-di Architecture: mipsel @@ -8492,8 +8003,8 @@ Depends: kernel-image-3.2.0-4-loongson-2f-di, nic-shared-modules-3.2.0-4-loongson-2f-di Description: Common NIC drivers This package contains common NIC drivers for the kernel. -Kernel-Version: 3.2.0-4-loongson-2f -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-loongson-2f Package: nic-shared-modules-3.2.0-4-loongson-2f-di Architecture: mipsel @@ -8504,8 +8015,8 @@ Description: Shared NIC drivers This package contains NIC drivers needed by combinations of nic-modules, nic-extra-modules, nic-pcmcia-modules, and nic-wireless-modules. -Kernel-Version: 3.2.0-4-loongson-2f -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-loongson-2f Package: ppp-modules-3.2.0-4-loongson-2f-di Architecture: mipsel @@ -8515,8 +8026,8 @@ Depends: kernel-image-3.2.0-4-loongson-2f-di, zlib-modules-3.2.0-4-loongson-2f-di Description: PPP drivers This package contains PPP drivers for the kernel. -Kernel-Version: 3.2.0-4-loongson-2f -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-loongson-2f Package: cdrom-core-modules-3.2.0-4-loongson-2f-di Architecture: mipsel @@ -8526,8 +8037,8 @@ Depends: kernel-image-3.2.0-4-loongson-2f-di, isofs-modules-3.2.0-4-loongson-2f-di Description: CDROM support This package contains core CDROM support for the kernel. -Kernel-Version: 3.2.0-4-loongson-2f -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-loongson-2f Package: loop-modules-3.2.0-4-loongson-2f-di Architecture: mipsel @@ -8537,8 +8048,8 @@ Depends: kernel-image-3.2.0-4-loongson-2f-di Description: Loopback filesystem support This package contains loopback filesystem support for the kernel. -Kernel-Version: 3.2.0-4-loongson-2f -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-loongson-2f Package: ipv6-modules-3.2.0-4-loongson-2f-di Architecture: mipsel @@ -8548,8 +8059,8 @@ Depends: kernel-image-3.2.0-4-loongson-2f-di Description: IPv6 driver This package contains the IPv6 driver for the kernel. -Kernel-Version: 3.2.0-4-loongson-2f -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-loongson-2f Package: btrfs-modules-3.2.0-4-loongson-2f-di Architecture: mipsel @@ -8559,8 +8070,8 @@ Depends: kernel-image-3.2.0-4-loongson-2f-di, zlib-modules-3.2.0-4-loongson-2f-di Description: BTRFS filesystem support This package contains the BTRFS filesystem module for the kernel. -Kernel-Version: 3.2.0-4-loongson-2f -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-loongson-2f Package: isofs-modules-3.2.0-4-loongson-2f-di Architecture: mipsel @@ -8570,8 +8081,8 @@ Depends: kernel-image-3.2.0-4-loongson-2f-di Description: ISOFS filesystem support This package contains the ISOFS filesystem module for the kernel. -Kernel-Version: 3.2.0-4-loongson-2f -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-loongson-2f Package: jfs-modules-3.2.0-4-loongson-2f-di Architecture: mipsel @@ -8581,8 +8092,8 @@ Depends: kernel-image-3.2.0-4-loongson-2f-di Description: JFS filesystem support This package contains the JFS filesystem module for the kernel. -Kernel-Version: 3.2.0-4-loongson-2f -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-loongson-2f Package: reiserfs-modules-3.2.0-4-loongson-2f-di Architecture: mipsel @@ -8592,8 +8103,8 @@ Depends: kernel-image-3.2.0-4-loongson-2f-di Description: Reiser filesystem support This package contains the Reiser filesystem module for the kernel. -Kernel-Version: 3.2.0-4-loongson-2f -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-loongson-2f Package: xfs-modules-3.2.0-4-loongson-2f-di Architecture: mipsel @@ -8603,8 +8114,8 @@ Depends: kernel-image-3.2.0-4-loongson-2f-di Description: XFS filesystem support This package contains the XFS filesystem module for the kernel. -Kernel-Version: 3.2.0-4-loongson-2f -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-loongson-2f Package: fat-modules-3.2.0-4-loongson-2f-di Architecture: mipsel @@ -8614,8 +8125,8 @@ Depends: kernel-image-3.2.0-4-loongson-2f-di Description: FAT filesystem support This package contains the FAT and VFAT filesystem modules for the kernel. -Kernel-Version: 3.2.0-4-loongson-2f -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-loongson-2f Package: md-modules-3.2.0-4-loongson-2f-di Architecture: mipsel @@ -8625,8 +8136,8 @@ Depends: kernel-image-3.2.0-4-loongson-2f-di Description: RAID and LVM support This package contains RAID and LVM modules for the kernel. -Kernel-Version: 3.2.0-4-loongson-2f -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-loongson-2f Package: multipath-modules-3.2.0-4-loongson-2f-di Architecture: mipsel @@ -8636,8 +8147,8 @@ Depends: kernel-image-3.2.0-4-loongson-2f-di, md-modules-3.2.0-4-loongson-2f-di Description: Multipath support This package contains DM-Multipath modules for the kernel. -Kernel-Version: 3.2.0-4-loongson-2f -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-loongson-2f Package: usb-modules-3.2.0-4-loongson-2f-di Architecture: mipsel @@ -8647,8 +8158,8 @@ Depends: kernel-image-3.2.0-4-loongson-2f-di Description: USB support This package contains core USB drivers for the kernel. -Kernel-Version: 3.2.0-4-loongson-2f -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-loongson-2f Package: usb-storage-modules-3.2.0-4-loongson-2f-di Architecture: mipsel @@ -8658,8 +8169,8 @@ Depends: kernel-image-3.2.0-4-loongson-2f-di, usb-modules-3.2.0-4-loongson-2f-di Description: USB storage support This package contains the USB storage driver for the kernel. -Kernel-Version: 3.2.0-4-loongson-2f -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-loongson-2f Package: input-modules-3.2.0-4-loongson-2f-di Architecture: mipsel @@ -8669,8 +8180,8 @@ Depends: kernel-image-3.2.0-4-loongson-2f-di, usb-modules-3.2.0-4-loongson-2f-di Description: Input devices support This package contains input device drivers for the kernel. -Kernel-Version: 3.2.0-4-loongson-2f -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-loongson-2f Package: nic-usb-modules-3.2.0-4-loongson-2f-di Architecture: mipsel @@ -8680,8 +8191,8 @@ Depends: kernel-image-3.2.0-4-loongson-2f-di, nic-shared-modules-3.2.0-4-loongson-2f-di, usb-modules-3.2.0-4-loongson-2f-di Description: USB NIC drivers This package contains USB network adapter drivers for the kernel. -Kernel-Version: 3.2.0-4-loongson-2f -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-loongson-2f Package: sata-modules-3.2.0-4-loongson-2f-di Architecture: mipsel @@ -8691,8 +8202,8 @@ Depends: kernel-image-3.2.0-4-loongson-2f-di Description: SATA drivers This package contains SATA drivers for the kernel. -Kernel-Version: 3.2.0-4-loongson-2f -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-loongson-2f Package: crypto-modules-3.2.0-4-loongson-2f-di Architecture: mipsel @@ -8702,8 +8213,8 @@ Depends: kernel-image-3.2.0-4-loongson-2f-di Description: crypto modules This package contains crypto modules. -Kernel-Version: 3.2.0-4-loongson-2f -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-loongson-2f Package: crypto-dm-modules-3.2.0-4-loongson-2f-di Architecture: mipsel @@ -8713,8 +8224,8 @@ Depends: kernel-image-3.2.0-4-loongson-2f-di, md-modules-3.2.0-4-loongson-2f-di Description: devicemapper crypto module This package contains the devicemapper crypto (dm-crypt) module. -Kernel-Version: 3.2.0-4-loongson-2f -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-loongson-2f Package: nbd-modules-3.2.0-4-loongson-2f-di Architecture: mipsel @@ -8725,8 +8236,8 @@ Description: Network Block Device modules This package contains the modules required for support of the Network Block Device -Kernel-Version: 3.2.0-4-loongson-2f -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-loongson-2f Package: squashfs-modules-3.2.0-4-loongson-2f-di Architecture: mipsel @@ -8736,8 +8247,8 @@ Depends: kernel-image-3.2.0-4-loongson-2f-di Description: squashfs modules This package contains squashfs modules. -Kernel-Version: 3.2.0-4-loongson-2f -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-loongson-2f Package: virtio-modules-3.2.0-4-loongson-2f-di Architecture: mipsel @@ -8747,8 +8258,8 @@ Depends: kernel-image-3.2.0-4-loongson-2f-di Description: virtio modules This package contains virtio modules. -Kernel-Version: 3.2.0-4-loongson-2f -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-loongson-2f Package: zlib-modules-3.2.0-4-loongson-2f-di Architecture: mipsel @@ -8758,8 +8269,8 @@ Depends: kernel-image-3.2.0-4-loongson-2f-di Description: zlib modules This package contains zlib modules. -Kernel-Version: 3.2.0-4-loongson-2f -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-loongson-2f Package: udf-modules-3.2.0-4-loongson-2f-di Architecture: mipsel @@ -8769,8 +8280,8 @@ Depends: kernel-image-3.2.0-4-loongson-2f-di Description: UDF modules This package contains the UDF filesystem module. -Kernel-Version: 3.2.0-4-loongson-2f -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-loongson-2f Package: fuse-modules-3.2.0-4-loongson-2f-di Architecture: mipsel @@ -8780,8 +8291,8 @@ Depends: kernel-image-3.2.0-4-loongson-2f-di Description: FUSE modules This package contains the Filesystem in Userspace (FUSE) module. -Kernel-Version: 3.2.0-4-loongson-2f -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-loongson-2f Package: linux-image-3.2.0-4-r5k-cobalt Architecture: mipsel @@ -8847,8 +8358,8 @@ This package contains the kernel image for the Debian installer boot images. It does _not_ provide a usable kernel for your full Debian system. -Kernel-Version: 3.2.0-4-powerpc -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-powerpc Package: nic-modules-3.2.0-4-powerpc-di Architecture: powerpc @@ -8858,8 +8369,8 @@ Depends: kernel-image-3.2.0-4-powerpc-di, nic-shared-modules-3.2.0-4-powerpc-di, core-modules-3.2.0-4-powerpc-di Description: Common NIC drivers This package contains common NIC drivers for the kernel. -Kernel-Version: 3.2.0-4-powerpc -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-powerpc Package: nic-extra-modules-3.2.0-4-powerpc-di Architecture: powerpc @@ -8869,8 +8380,8 @@ Depends: kernel-image-3.2.0-4-powerpc-di, nic-shared-modules-3.2.0-4-powerpc-di, core-modules-3.2.0-4-powerpc-di, crc-modules-3.2.0-4-powerpc-di Description: Rare NIC drivers This package contains rare NIC drivers for the kernel. -Kernel-Version: 3.2.0-4-powerpc -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-powerpc Package: nic-shared-modules-3.2.0-4-powerpc-di Architecture: powerpc @@ -8881,8 +8392,8 @@ Description: Shared NIC drivers This package contains NIC drivers needed by combinations of nic-modules, nic-extra-modules, nic-pcmcia-modules, and nic-wireless-modules. -Kernel-Version: 3.2.0-4-powerpc -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-powerpc Package: serial-modules-3.2.0-4-powerpc-di Architecture: powerpc @@ -8892,8 +8403,8 @@ Depends: kernel-image-3.2.0-4-powerpc-di, pcmcia-modules-3.2.0-4-powerpc-di Description: Serial drivers This package contains serial drivers for the kernel. -Kernel-Version: 3.2.0-4-powerpc -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-powerpc Package: usb-serial-modules-3.2.0-4-powerpc-di Architecture: powerpc @@ -8903,8 +8414,8 @@ Depends: kernel-image-3.2.0-4-powerpc-di, usb-modules-3.2.0-4-powerpc-di Description: USB serial drivers This package contains USB serial drivers for the kernel. -Kernel-Version: 3.2.0-4-powerpc -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-powerpc Package: ppp-modules-3.2.0-4-powerpc-di Architecture: powerpc @@ -8914,8 +8425,8 @@ Depends: kernel-image-3.2.0-4-powerpc-di, serial-modules-3.2.0-4-powerpc-di, zlib-modules-3.2.0-4-powerpc-di, crc-modules-3.2.0-4-powerpc-di Description: PPP drivers This package contains PPP drivers for the kernel. -Kernel-Version: 3.2.0-4-powerpc -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-powerpc Package: pata-modules-3.2.0-4-powerpc-di Architecture: powerpc @@ -8925,8 +8436,8 @@ Depends: kernel-image-3.2.0-4-powerpc-di, ata-modules-3.2.0-4-powerpc-di, core-modules-3.2.0-4-powerpc-di Description: PATA drivers This package contains PATA drivers for the kernel. -Kernel-Version: 3.2.0-4-powerpc -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-powerpc Package: cdrom-core-modules-3.2.0-4-powerpc-di Architecture: powerpc @@ -8936,8 +8447,8 @@ Depends: kernel-image-3.2.0-4-powerpc-di, scsi-core-modules-3.2.0-4-powerpc-di, isofs-modules-3.2.0-4-powerpc-di Description: CDROM support This package contains core CDROM support for the kernel. -Kernel-Version: 3.2.0-4-powerpc -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-powerpc Package: firewire-core-modules-3.2.0-4-powerpc-di Architecture: powerpc @@ -8947,8 +8458,8 @@ Depends: kernel-image-3.2.0-4-powerpc-di, scsi-core-modules-3.2.0-4-powerpc-di, crc-modules-3.2.0-4-powerpc-di Description: Core FireWire drivers This package contains core FireWire drivers for the kernel. -Kernel-Version: 3.2.0-4-powerpc -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-powerpc Package: scsi-core-modules-3.2.0-4-powerpc-di Architecture: powerpc @@ -8958,8 +8469,8 @@ Depends: kernel-image-3.2.0-4-powerpc-di Description: Core SCSI subsystem This package contains the core SCSI subsystem for the kernel. -Kernel-Version: 3.2.0-4-powerpc -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-powerpc Package: scsi-modules-3.2.0-4-powerpc-di Architecture: powerpc @@ -8969,8 +8480,8 @@ Depends: kernel-image-3.2.0-4-powerpc-di, scsi-core-modules-3.2.0-4-powerpc-di, cdrom-core-modules-3.2.0-4-powerpc-di, core-modules-3.2.0-4-powerpc-di, ata-modules-3.2.0-4-powerpc-di Description: SCSI drivers This package contains SCSI drivers for the kernel. -Kernel-Version: 3.2.0-4-powerpc -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-powerpc Package: scsi-common-modules-3.2.0-4-powerpc-di Architecture: powerpc @@ -8980,8 +8491,8 @@ Depends: kernel-image-3.2.0-4-powerpc-di, scsi-core-modules-3.2.0-4-powerpc-di, cdrom-core-modules-3.2.0-4-powerpc-di Description: Very common SCSI drivers This package contains very common SCSI drivers for the kernel. -Kernel-Version: 3.2.0-4-powerpc -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-powerpc Package: scsi-extra-modules-3.2.0-4-powerpc-di Architecture: powerpc @@ -8992,8 +8503,8 @@ Description: Uncommon SCSI drivers This package contains uncommon SCSI drivers for the kernel. This includes SCSI RAID drivers, and some of the less common SCSI controllers. -Kernel-Version: 3.2.0-4-powerpc -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-powerpc Package: floppy-modules-3.2.0-4-powerpc-di Architecture: powerpc @@ -9003,8 +8514,8 @@ Depends: kernel-image-3.2.0-4-powerpc-di Description: Floppy driver This package contains the floppy driver for the kernel. -Kernel-Version: 3.2.0-4-powerpc -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-powerpc Package: loop-modules-3.2.0-4-powerpc-di Architecture: powerpc @@ -9014,8 +8525,8 @@ Depends: kernel-image-3.2.0-4-powerpc-di Description: Loopback filesystem support This package contains loopback filesystem support for the kernel. -Kernel-Version: 3.2.0-4-powerpc -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-powerpc Package: btrfs-modules-3.2.0-4-powerpc-di Architecture: powerpc @@ -9025,8 +8536,8 @@ Depends: kernel-image-3.2.0-4-powerpc-di, core-modules-3.2.0-4-powerpc-di, crc-modules-3.2.0-4-powerpc-di, zlib-modules-3.2.0-4-powerpc-di Description: BTRFS filesystem support This package contains the BTRFS filesystem module for the kernel. -Kernel-Version: 3.2.0-4-powerpc -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-powerpc Package: ext2-modules-3.2.0-4-powerpc-di Architecture: powerpc @@ -9036,8 +8547,8 @@ Depends: kernel-image-3.2.0-4-powerpc-di, core-modules-3.2.0-4-powerpc-di Description: EXT2 filesystem support This package contains the EXT2 filesystem module for the kernel. -Kernel-Version: 3.2.0-4-powerpc -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-powerpc Package: ext3-modules-3.2.0-4-powerpc-di Architecture: powerpc @@ -9047,8 +8558,8 @@ Depends: kernel-image-3.2.0-4-powerpc-di, core-modules-3.2.0-4-powerpc-di Description: EXT3 filesystem support This package contains the EXT3 filesystem module for the kernel. -Kernel-Version: 3.2.0-4-powerpc -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-powerpc Package: ext4-modules-3.2.0-4-powerpc-di Architecture: powerpc @@ -9058,8 +8569,8 @@ Depends: kernel-image-3.2.0-4-powerpc-di, core-modules-3.2.0-4-powerpc-di Description: EXT4 filesystem support This package contains the EXT4 filesystem module for the kernel. -Kernel-Version: 3.2.0-4-powerpc -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-powerpc Package: isofs-modules-3.2.0-4-powerpc-di Architecture: powerpc @@ -9069,8 +8580,8 @@ Depends: kernel-image-3.2.0-4-powerpc-di Description: ISOFS filesystem support This package contains the ISOFS filesystem module for the kernel. -Kernel-Version: 3.2.0-4-powerpc -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-powerpc Package: jfs-modules-3.2.0-4-powerpc-di Architecture: powerpc @@ -9080,8 +8591,8 @@ Depends: kernel-image-3.2.0-4-powerpc-di Description: JFS filesystem support This package contains the JFS filesystem module for the kernel. -Kernel-Version: 3.2.0-4-powerpc -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-powerpc Package: reiserfs-modules-3.2.0-4-powerpc-di Architecture: powerpc @@ -9091,8 +8602,8 @@ Depends: kernel-image-3.2.0-4-powerpc-di Description: Reiser filesystem support This package contains the Reiser filesystem module for the kernel. -Kernel-Version: 3.2.0-4-powerpc -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-powerpc Package: xfs-modules-3.2.0-4-powerpc-di Architecture: powerpc @@ -9102,8 +8613,8 @@ Depends: kernel-image-3.2.0-4-powerpc-di Description: XFS filesystem support This package contains the XFS filesystem module for the kernel. -Kernel-Version: 3.2.0-4-powerpc -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-powerpc Package: fat-modules-3.2.0-4-powerpc-di Architecture: powerpc @@ -9113,8 +8624,8 @@ Depends: kernel-image-3.2.0-4-powerpc-di Description: FAT filesystem support This package contains the FAT and VFAT filesystem modules for the kernel. -Kernel-Version: 3.2.0-4-powerpc -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-powerpc Package: hfs-modules-3.2.0-4-powerpc-di Architecture: powerpc @@ -9124,8 +8635,8 @@ Depends: kernel-image-3.2.0-4-powerpc-di Description: HFS filesystem support This package contains the HFS and HFS+ filesystem modules for the kernel. -Kernel-Version: 3.2.0-4-powerpc -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-powerpc Package: affs-modules-3.2.0-4-powerpc-di Architecture: powerpc @@ -9135,8 +8646,8 @@ Depends: kernel-image-3.2.0-4-powerpc-di Description: Amiga filesystem support This package contains the Amiga filesystem module for the kernel. -Kernel-Version: 3.2.0-4-powerpc -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-powerpc Package: ufs-modules-3.2.0-4-powerpc-di Architecture: powerpc @@ -9146,8 +8657,8 @@ Depends: kernel-image-3.2.0-4-powerpc-di Description: UFS filesystem support This package contains the UFS filesystem module for the kernel. -Kernel-Version: 3.2.0-4-powerpc -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-powerpc Package: md-modules-3.2.0-4-powerpc-di Architecture: powerpc @@ -9157,8 +8668,8 @@ Depends: kernel-image-3.2.0-4-powerpc-di Description: RAID and LVM support This package contains RAID and LVM modules for the kernel. -Kernel-Version: 3.2.0-4-powerpc -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-powerpc Package: multipath-modules-3.2.0-4-powerpc-di Architecture: powerpc @@ -9168,8 +8679,8 @@ Depends: kernel-image-3.2.0-4-powerpc-di, md-modules-3.2.0-4-powerpc-di, scsi-core-modules-3.2.0-4-powerpc-di Description: Multipath support This package contains DM-Multipath modules for the kernel. -Kernel-Version: 3.2.0-4-powerpc -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-powerpc Package: usb-modules-3.2.0-4-powerpc-di Architecture: powerpc @@ -9179,8 +8690,8 @@ Depends: kernel-image-3.2.0-4-powerpc-di Description: USB support This package contains core USB drivers for the kernel. -Kernel-Version: 3.2.0-4-powerpc -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-powerpc Package: usb-storage-modules-3.2.0-4-powerpc-di Architecture: powerpc @@ -9190,8 +8701,8 @@ Depends: kernel-image-3.2.0-4-powerpc-di, scsi-core-modules-3.2.0-4-powerpc-di, usb-modules-3.2.0-4-powerpc-di Description: USB storage support This package contains the USB storage driver for the kernel. -Kernel-Version: 3.2.0-4-powerpc -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-powerpc Package: pcmcia-storage-modules-3.2.0-4-powerpc-di Architecture: powerpc @@ -9201,8 +8712,8 @@ Depends: kernel-image-3.2.0-4-powerpc-di, cdrom-core-modules-3.2.0-4-powerpc-di, pcmcia-modules-3.2.0-4-powerpc-di, ata-modules-3.2.0-4-powerpc-di Description: PCMCIA storage drivers This package contains PCMCIA storage drivers for the kernel. -Kernel-Version: 3.2.0-4-powerpc -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-powerpc Package: input-modules-3.2.0-4-powerpc-di Architecture: powerpc @@ -9212,8 +8723,8 @@ Depends: kernel-image-3.2.0-4-powerpc-di, usb-modules-3.2.0-4-powerpc-di Description: Input devices support This package contains input device drivers for the kernel. -Kernel-Version: 3.2.0-4-powerpc -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-powerpc Package: event-modules-3.2.0-4-powerpc-di Architecture: powerpc @@ -9223,8 +8734,8 @@ Depends: kernel-image-3.2.0-4-powerpc-di Description: Event support This package contains event drivers for the kernel. -Kernel-Version: 3.2.0-4-powerpc -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-powerpc Package: mouse-modules-3.2.0-4-powerpc-di Architecture: powerpc @@ -9234,8 +8745,8 @@ Depends: kernel-image-3.2.0-4-powerpc-di, event-modules-3.2.0-4-powerpc-di, input-modules-3.2.0-4-powerpc-di, usb-modules-3.2.0-4-powerpc-di Description: Mouse support This package contains mouse drivers for the kernel. -Kernel-Version: 3.2.0-4-powerpc -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-powerpc Package: irda-modules-3.2.0-4-powerpc-di Architecture: powerpc @@ -9245,8 +8756,8 @@ Depends: kernel-image-3.2.0-4-powerpc-di, ppp-modules-3.2.0-4-powerpc-di, usb-modules-3.2.0-4-powerpc-di Description: Infrared devices support This package contains infrared device drivers for the kernel. -Kernel-Version: 3.2.0-4-powerpc -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-powerpc Package: nic-pcmcia-modules-3.2.0-4-powerpc-di Architecture: powerpc @@ -9256,8 +8767,8 @@ Depends: kernel-image-3.2.0-4-powerpc-di, nic-modules-3.2.0-4-powerpc-di, nic-shared-modules-3.2.0-4-powerpc-di, pcmcia-modules-3.2.0-4-powerpc-di, core-modules-3.2.0-4-powerpc-di Description: Common PCMCIA NIC drivers This package contains common PCMCIA NIC drivers for the kernel. -Kernel-Version: 3.2.0-4-powerpc -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-powerpc Package: pcmcia-modules-3.2.0-4-powerpc-di Architecture: powerpc @@ -9267,8 +8778,8 @@ Depends: kernel-image-3.2.0-4-powerpc-di, core-modules-3.2.0-4-powerpc-di Description: Common PCMCIA drivers This package contains common PCMCIA drivers for the kernel. -Kernel-Version: 3.2.0-4-powerpc -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-powerpc Package: sata-modules-3.2.0-4-powerpc-di Architecture: powerpc @@ -9278,8 +8789,8 @@ Depends: kernel-image-3.2.0-4-powerpc-di, scsi-core-modules-3.2.0-4-powerpc-di, ata-modules-3.2.0-4-powerpc-di Description: SATA drivers This package contains SATA drivers for the kernel. -Kernel-Version: 3.2.0-4-powerpc -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-powerpc Package: core-modules-3.2.0-4-powerpc-di Architecture: powerpc @@ -9290,8 +8801,8 @@ Description: Core modules This package contains core modules for the kernel, that will almost always be needed. -Kernel-Version: 3.2.0-4-powerpc -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-powerpc Package: crc-modules-3.2.0-4-powerpc-di Architecture: powerpc @@ -9301,8 +8812,8 @@ Depends: kernel-image-3.2.0-4-powerpc-di Description: CRC modules This package contains CRC support modules. -Kernel-Version: 3.2.0-4-powerpc -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-powerpc Package: crypto-modules-3.2.0-4-powerpc-di Architecture: powerpc @@ -9312,8 +8823,8 @@ Depends: kernel-image-3.2.0-4-powerpc-di Description: crypto modules This package contains crypto modules. -Kernel-Version: 3.2.0-4-powerpc -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-powerpc Package: crypto-dm-modules-3.2.0-4-powerpc-di Architecture: powerpc @@ -9323,8 +8834,8 @@ Depends: kernel-image-3.2.0-4-powerpc-di, md-modules-3.2.0-4-powerpc-di Description: devicemapper crypto module This package contains the devicemapper crypto (dm-crypt) module. -Kernel-Version: 3.2.0-4-powerpc -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-powerpc Package: ata-modules-3.2.0-4-powerpc-di Architecture: powerpc @@ -9335,8 +8846,8 @@ Description: ATA disk modules This package contains core ATA disk modules used by both PATA and SATA disk drivers. -Kernel-Version: 3.2.0-4-powerpc -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-powerpc Package: nbd-modules-3.2.0-4-powerpc-di Architecture: powerpc @@ -9347,8 +8858,8 @@ Description: Network Block Device modules This package contains the modules required for support of the Network Block Device -Kernel-Version: 3.2.0-4-powerpc -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-powerpc Package: squashfs-modules-3.2.0-4-powerpc-di Architecture: powerpc @@ -9358,8 +8869,8 @@ Depends: kernel-image-3.2.0-4-powerpc-di Description: squashfs modules This package contains squashfs modules. -Kernel-Version: 3.2.0-4-powerpc -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-powerpc Package: virtio-modules-3.2.0-4-powerpc-di Architecture: powerpc @@ -9369,8 +8880,8 @@ Depends: kernel-image-3.2.0-4-powerpc-di Description: virtio modules This package contains virtio modules. -Kernel-Version: 3.2.0-4-powerpc -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-powerpc Package: uinput-modules-3.2.0-4-powerpc-di Architecture: powerpc @@ -9380,8 +8891,8 @@ Depends: kernel-image-3.2.0-4-powerpc-di Description: uinput support This package contains the uinput module. -Kernel-Version: 3.2.0-4-powerpc -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-powerpc Package: zlib-modules-3.2.0-4-powerpc-di Architecture: powerpc @@ -9391,8 +8902,8 @@ Depends: kernel-image-3.2.0-4-powerpc-di Description: zlib modules This package contains zlib modules. -Kernel-Version: 3.2.0-4-powerpc -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-powerpc Package: udf-modules-3.2.0-4-powerpc-di Architecture: powerpc @@ -9402,8 +8913,8 @@ Depends: kernel-image-3.2.0-4-powerpc-di, crc-modules-3.2.0-4-powerpc-di Description: UDF modules This package contains the UDF filesystem module. -Kernel-Version: 3.2.0-4-powerpc -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-powerpc Package: fuse-modules-3.2.0-4-powerpc-di Architecture: powerpc @@ -9413,8 +8924,8 @@ Depends: kernel-image-3.2.0-4-powerpc-di Description: FUSE modules This package contains the Filesystem in Userspace (FUSE) module. -Kernel-Version: 3.2.0-4-powerpc -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-powerpc Package: kernel-image-3.2.0-4-powerpc64-di Architecture: powerpc ppc64 @@ -9425,8 +8936,8 @@ This package contains the kernel image for the Debian installer boot images. It does _not_ provide a usable kernel for your full Debian system. -Kernel-Version: 3.2.0-4-powerpc64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-powerpc64 Package: nic-modules-3.2.0-4-powerpc64-di Architecture: powerpc ppc64 @@ -9436,8 +8947,8 @@ Depends: kernel-image-3.2.0-4-powerpc64-di, nic-shared-modules-3.2.0-4-powerpc64-di, core-modules-3.2.0-4-powerpc64-di Description: Common NIC drivers This package contains common NIC drivers for the kernel. -Kernel-Version: 3.2.0-4-powerpc64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-powerpc64 Package: nic-extra-modules-3.2.0-4-powerpc64-di Architecture: powerpc ppc64 @@ -9447,8 +8958,8 @@ Depends: kernel-image-3.2.0-4-powerpc64-di, nic-shared-modules-3.2.0-4-powerpc64-di, core-modules-3.2.0-4-powerpc64-di, crc-modules-3.2.0-4-powerpc64-di Description: Rare NIC drivers This package contains rare NIC drivers for the kernel. -Kernel-Version: 3.2.0-4-powerpc64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-powerpc64 Package: nic-shared-modules-3.2.0-4-powerpc64-di Architecture: powerpc ppc64 @@ -9459,8 +8970,8 @@ Description: Shared NIC drivers This package contains NIC drivers needed by combinations of nic-modules, nic-extra-modules, nic-pcmcia-modules, and nic-wireless-modules. -Kernel-Version: 3.2.0-4-powerpc64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-powerpc64 Package: serial-modules-3.2.0-4-powerpc64-di Architecture: powerpc ppc64 @@ -9470,8 +8981,8 @@ Depends: kernel-image-3.2.0-4-powerpc64-di, pcmcia-modules-3.2.0-4-powerpc64-di Description: Serial drivers This package contains serial drivers for the kernel. -Kernel-Version: 3.2.0-4-powerpc64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-powerpc64 Package: usb-serial-modules-3.2.0-4-powerpc64-di Architecture: powerpc ppc64 @@ -9481,8 +8992,8 @@ Depends: kernel-image-3.2.0-4-powerpc64-di, usb-modules-3.2.0-4-powerpc64-di Description: USB serial drivers This package contains USB serial drivers for the kernel. -Kernel-Version: 3.2.0-4-powerpc64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-powerpc64 Package: ppp-modules-3.2.0-4-powerpc64-di Architecture: powerpc ppc64 @@ -9492,8 +9003,8 @@ Depends: kernel-image-3.2.0-4-powerpc64-di, serial-modules-3.2.0-4-powerpc64-di, crc-modules-3.2.0-4-powerpc64-di Description: PPP drivers This package contains PPP drivers for the kernel. -Kernel-Version: 3.2.0-4-powerpc64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-powerpc64 Package: pata-modules-3.2.0-4-powerpc64-di Architecture: powerpc ppc64 @@ -9503,8 +9014,8 @@ Depends: kernel-image-3.2.0-4-powerpc64-di, ata-modules-3.2.0-4-powerpc64-di, core-modules-3.2.0-4-powerpc64-di Description: PATA drivers This package contains PATA drivers for the kernel. -Kernel-Version: 3.2.0-4-powerpc64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-powerpc64 Package: cdrom-core-modules-3.2.0-4-powerpc64-di Architecture: powerpc ppc64 @@ -9514,8 +9025,8 @@ Depends: kernel-image-3.2.0-4-powerpc64-di, scsi-core-modules-3.2.0-4-powerpc64-di, isofs-modules-3.2.0-4-powerpc64-di Description: CDROM support This package contains core CDROM support for the kernel. -Kernel-Version: 3.2.0-4-powerpc64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-powerpc64 Package: firewire-core-modules-3.2.0-4-powerpc64-di Architecture: powerpc ppc64 @@ -9525,8 +9036,8 @@ Depends: kernel-image-3.2.0-4-powerpc64-di, scsi-core-modules-3.2.0-4-powerpc64-di, crc-modules-3.2.0-4-powerpc64-di Description: Core FireWire drivers This package contains core FireWire drivers for the kernel. -Kernel-Version: 3.2.0-4-powerpc64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-powerpc64 Package: scsi-core-modules-3.2.0-4-powerpc64-di Architecture: powerpc ppc64 @@ -9536,8 +9047,8 @@ Depends: kernel-image-3.2.0-4-powerpc64-di Description: Core SCSI subsystem This package contains the core SCSI subsystem for the kernel. -Kernel-Version: 3.2.0-4-powerpc64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-powerpc64 Package: scsi-modules-3.2.0-4-powerpc64-di Architecture: powerpc ppc64 @@ -9547,8 +9058,8 @@ Depends: kernel-image-3.2.0-4-powerpc64-di, scsi-core-modules-3.2.0-4-powerpc64-di, cdrom-core-modules-3.2.0-4-powerpc64-di, core-modules-3.2.0-4-powerpc64-di, ata-modules-3.2.0-4-powerpc64-di Description: SCSI drivers This package contains SCSI drivers for the kernel. -Kernel-Version: 3.2.0-4-powerpc64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-powerpc64 Package: scsi-common-modules-3.2.0-4-powerpc64-di Architecture: powerpc ppc64 @@ -9558,8 +9069,8 @@ Depends: kernel-image-3.2.0-4-powerpc64-di, scsi-core-modules-3.2.0-4-powerpc64-di, cdrom-core-modules-3.2.0-4-powerpc64-di Description: Very common SCSI drivers This package contains very common SCSI drivers for the kernel. -Kernel-Version: 3.2.0-4-powerpc64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-powerpc64 Package: scsi-extra-modules-3.2.0-4-powerpc64-di Architecture: powerpc ppc64 @@ -9570,8 +9081,8 @@ Description: Uncommon SCSI drivers This package contains uncommon SCSI drivers for the kernel. This includes SCSI RAID drivers, and some of the less common SCSI controllers. -Kernel-Version: 3.2.0-4-powerpc64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-powerpc64 Package: floppy-modules-3.2.0-4-powerpc64-di Architecture: powerpc ppc64 @@ -9581,8 +9092,8 @@ Depends: kernel-image-3.2.0-4-powerpc64-di Description: Floppy driver This package contains the floppy driver for the kernel. -Kernel-Version: 3.2.0-4-powerpc64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-powerpc64 Package: loop-modules-3.2.0-4-powerpc64-di Architecture: powerpc ppc64 @@ -9592,8 +9103,8 @@ Depends: kernel-image-3.2.0-4-powerpc64-di Description: Loopback filesystem support This package contains loopback filesystem support for the kernel. -Kernel-Version: 3.2.0-4-powerpc64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-powerpc64 Package: btrfs-modules-3.2.0-4-powerpc64-di Architecture: powerpc ppc64 @@ -9603,8 +9114,8 @@ Depends: kernel-image-3.2.0-4-powerpc64-di, core-modules-3.2.0-4-powerpc64-di, crc-modules-3.2.0-4-powerpc64-di Description: BTRFS filesystem support This package contains the BTRFS filesystem module for the kernel. -Kernel-Version: 3.2.0-4-powerpc64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-powerpc64 Package: ext2-modules-3.2.0-4-powerpc64-di Architecture: powerpc ppc64 @@ -9614,8 +9125,8 @@ Depends: kernel-image-3.2.0-4-powerpc64-di, core-modules-3.2.0-4-powerpc64-di Description: EXT2 filesystem support This package contains the EXT2 filesystem module for the kernel. -Kernel-Version: 3.2.0-4-powerpc64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-powerpc64 Package: ext3-modules-3.2.0-4-powerpc64-di Architecture: powerpc ppc64 @@ -9625,8 +9136,8 @@ Depends: kernel-image-3.2.0-4-powerpc64-di, core-modules-3.2.0-4-powerpc64-di Description: EXT3 filesystem support This package contains the EXT3 filesystem module for the kernel. -Kernel-Version: 3.2.0-4-powerpc64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-powerpc64 Package: ext4-modules-3.2.0-4-powerpc64-di Architecture: powerpc ppc64 @@ -9636,8 +9147,8 @@ Depends: kernel-image-3.2.0-4-powerpc64-di, core-modules-3.2.0-4-powerpc64-di Description: EXT4 filesystem support This package contains the EXT4 filesystem module for the kernel. -Kernel-Version: 3.2.0-4-powerpc64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-powerpc64 Package: isofs-modules-3.2.0-4-powerpc64-di Architecture: powerpc ppc64 @@ -9647,8 +9158,8 @@ Depends: kernel-image-3.2.0-4-powerpc64-di Description: ISOFS filesystem support This package contains the ISOFS filesystem module for the kernel. -Kernel-Version: 3.2.0-4-powerpc64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-powerpc64 Package: jfs-modules-3.2.0-4-powerpc64-di Architecture: powerpc ppc64 @@ -9658,8 +9169,8 @@ Depends: kernel-image-3.2.0-4-powerpc64-di Description: JFS filesystem support This package contains the JFS filesystem module for the kernel. -Kernel-Version: 3.2.0-4-powerpc64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-powerpc64 Package: reiserfs-modules-3.2.0-4-powerpc64-di Architecture: powerpc ppc64 @@ -9669,8 +9180,8 @@ Depends: kernel-image-3.2.0-4-powerpc64-di Description: Reiser filesystem support This package contains the Reiser filesystem module for the kernel. -Kernel-Version: 3.2.0-4-powerpc64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-powerpc64 Package: xfs-modules-3.2.0-4-powerpc64-di Architecture: powerpc ppc64 @@ -9680,8 +9191,8 @@ Depends: kernel-image-3.2.0-4-powerpc64-di Description: XFS filesystem support This package contains the XFS filesystem module for the kernel. -Kernel-Version: 3.2.0-4-powerpc64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-powerpc64 Package: fat-modules-3.2.0-4-powerpc64-di Architecture: powerpc ppc64 @@ -9691,8 +9202,8 @@ Depends: kernel-image-3.2.0-4-powerpc64-di Description: FAT filesystem support This package contains the FAT and VFAT filesystem modules for the kernel. -Kernel-Version: 3.2.0-4-powerpc64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-powerpc64 Package: hfs-modules-3.2.0-4-powerpc64-di Architecture: powerpc ppc64 @@ -9702,8 +9213,8 @@ Depends: kernel-image-3.2.0-4-powerpc64-di Description: HFS filesystem support This package contains the HFS and HFS+ filesystem modules for the kernel. -Kernel-Version: 3.2.0-4-powerpc64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-powerpc64 Package: affs-modules-3.2.0-4-powerpc64-di Architecture: powerpc ppc64 @@ -9713,8 +9224,8 @@ Depends: kernel-image-3.2.0-4-powerpc64-di Description: Amiga filesystem support This package contains the Amiga filesystem module for the kernel. -Kernel-Version: 3.2.0-4-powerpc64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-powerpc64 Package: ufs-modules-3.2.0-4-powerpc64-di Architecture: powerpc ppc64 @@ -9724,8 +9235,8 @@ Depends: kernel-image-3.2.0-4-powerpc64-di Description: UFS filesystem support This package contains the UFS filesystem module for the kernel. -Kernel-Version: 3.2.0-4-powerpc64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-powerpc64 Package: md-modules-3.2.0-4-powerpc64-di Architecture: powerpc ppc64 @@ -9735,8 +9246,8 @@ Depends: kernel-image-3.2.0-4-powerpc64-di Description: RAID and LVM support This package contains RAID and LVM modules for the kernel. -Kernel-Version: 3.2.0-4-powerpc64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-powerpc64 Package: multipath-modules-3.2.0-4-powerpc64-di Architecture: powerpc ppc64 @@ -9746,8 +9257,8 @@ Depends: kernel-image-3.2.0-4-powerpc64-di, md-modules-3.2.0-4-powerpc64-di, scsi-core-modules-3.2.0-4-powerpc64-di Description: Multipath support This package contains DM-Multipath modules for the kernel. -Kernel-Version: 3.2.0-4-powerpc64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-powerpc64 Package: usb-modules-3.2.0-4-powerpc64-di Architecture: powerpc ppc64 @@ -9757,8 +9268,8 @@ Depends: kernel-image-3.2.0-4-powerpc64-di Description: USB support This package contains core USB drivers for the kernel. -Kernel-Version: 3.2.0-4-powerpc64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-powerpc64 Package: usb-storage-modules-3.2.0-4-powerpc64-di Architecture: powerpc ppc64 @@ -9768,8 +9279,8 @@ Depends: kernel-image-3.2.0-4-powerpc64-di, scsi-core-modules-3.2.0-4-powerpc64-di, usb-modules-3.2.0-4-powerpc64-di Description: USB storage support This package contains the USB storage driver for the kernel. -Kernel-Version: 3.2.0-4-powerpc64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-powerpc64 Package: pcmcia-storage-modules-3.2.0-4-powerpc64-di Architecture: powerpc ppc64 @@ -9779,8 +9290,8 @@ Depends: kernel-image-3.2.0-4-powerpc64-di, cdrom-core-modules-3.2.0-4-powerpc64-di, pcmcia-modules-3.2.0-4-powerpc64-di, ata-modules-3.2.0-4-powerpc64-di Description: PCMCIA storage drivers This package contains PCMCIA storage drivers for the kernel. -Kernel-Version: 3.2.0-4-powerpc64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-powerpc64 Package: input-modules-3.2.0-4-powerpc64-di Architecture: powerpc ppc64 @@ -9790,8 +9301,8 @@ Depends: kernel-image-3.2.0-4-powerpc64-di, usb-modules-3.2.0-4-powerpc64-di Description: Input devices support This package contains input device drivers for the kernel. -Kernel-Version: 3.2.0-4-powerpc64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-powerpc64 Package: event-modules-3.2.0-4-powerpc64-di Architecture: powerpc ppc64 @@ -9801,8 +9312,8 @@ Depends: kernel-image-3.2.0-4-powerpc64-di Description: Event support This package contains event drivers for the kernel. -Kernel-Version: 3.2.0-4-powerpc64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-powerpc64 Package: mouse-modules-3.2.0-4-powerpc64-di Architecture: powerpc ppc64 @@ -9812,8 +9323,8 @@ Depends: kernel-image-3.2.0-4-powerpc64-di, event-modules-3.2.0-4-powerpc64-di, input-modules-3.2.0-4-powerpc64-di, usb-modules-3.2.0-4-powerpc64-di Description: Mouse support This package contains mouse drivers for the kernel. -Kernel-Version: 3.2.0-4-powerpc64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-powerpc64 Package: irda-modules-3.2.0-4-powerpc64-di Architecture: powerpc ppc64 @@ -9823,8 +9334,8 @@ Depends: kernel-image-3.2.0-4-powerpc64-di, ppp-modules-3.2.0-4-powerpc64-di, usb-modules-3.2.0-4-powerpc64-di Description: Infrared devices support This package contains infrared device drivers for the kernel. -Kernel-Version: 3.2.0-4-powerpc64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-powerpc64 Package: nic-pcmcia-modules-3.2.0-4-powerpc64-di Architecture: powerpc ppc64 @@ -9834,8 +9345,8 @@ Depends: kernel-image-3.2.0-4-powerpc64-di, nic-modules-3.2.0-4-powerpc64-di, nic-shared-modules-3.2.0-4-powerpc64-di, pcmcia-modules-3.2.0-4-powerpc64-di, core-modules-3.2.0-4-powerpc64-di Description: Common PCMCIA NIC drivers This package contains common PCMCIA NIC drivers for the kernel. -Kernel-Version: 3.2.0-4-powerpc64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-powerpc64 Package: pcmcia-modules-3.2.0-4-powerpc64-di Architecture: powerpc ppc64 @@ -9845,8 +9356,8 @@ Depends: kernel-image-3.2.0-4-powerpc64-di, core-modules-3.2.0-4-powerpc64-di Description: Common PCMCIA drivers This package contains common PCMCIA drivers for the kernel. -Kernel-Version: 3.2.0-4-powerpc64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-powerpc64 Package: sata-modules-3.2.0-4-powerpc64-di Architecture: powerpc ppc64 @@ -9856,8 +9367,8 @@ Depends: kernel-image-3.2.0-4-powerpc64-di, scsi-core-modules-3.2.0-4-powerpc64-di, ata-modules-3.2.0-4-powerpc64-di Description: SATA drivers This package contains SATA drivers for the kernel. -Kernel-Version: 3.2.0-4-powerpc64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-powerpc64 Package: core-modules-3.2.0-4-powerpc64-di Architecture: powerpc ppc64 @@ -9868,8 +9379,8 @@ Description: Core modules This package contains core modules for the kernel, that will almost always be needed. -Kernel-Version: 3.2.0-4-powerpc64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-powerpc64 Package: crc-modules-3.2.0-4-powerpc64-di Architecture: powerpc ppc64 @@ -9879,8 +9390,8 @@ Depends: kernel-image-3.2.0-4-powerpc64-di Description: CRC modules This package contains CRC support modules. -Kernel-Version: 3.2.0-4-powerpc64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-powerpc64 Package: crypto-modules-3.2.0-4-powerpc64-di Architecture: powerpc ppc64 @@ -9890,8 +9401,8 @@ Depends: kernel-image-3.2.0-4-powerpc64-di Description: crypto modules This package contains crypto modules. -Kernel-Version: 3.2.0-4-powerpc64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-powerpc64 Package: crypto-dm-modules-3.2.0-4-powerpc64-di Architecture: powerpc ppc64 @@ -9901,8 +9412,8 @@ Depends: kernel-image-3.2.0-4-powerpc64-di, md-modules-3.2.0-4-powerpc64-di Description: devicemapper crypto module This package contains the devicemapper crypto (dm-crypt) module. -Kernel-Version: 3.2.0-4-powerpc64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-powerpc64 Package: ata-modules-3.2.0-4-powerpc64-di Architecture: powerpc ppc64 @@ -9913,8 +9424,8 @@ Description: ATA disk modules This package contains core ATA disk modules used by both PATA and SATA disk drivers. -Kernel-Version: 3.2.0-4-powerpc64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-powerpc64 Package: nbd-modules-3.2.0-4-powerpc64-di Architecture: powerpc ppc64 @@ -9925,8 +9436,8 @@ Description: Network Block Device modules This package contains the modules required for support of the Network Block Device -Kernel-Version: 3.2.0-4-powerpc64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-powerpc64 Package: squashfs-modules-3.2.0-4-powerpc64-di Architecture: powerpc ppc64 @@ -9936,8 +9447,8 @@ Depends: kernel-image-3.2.0-4-powerpc64-di Description: squashfs modules This package contains squashfs modules. -Kernel-Version: 3.2.0-4-powerpc64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-powerpc64 Package: virtio-modules-3.2.0-4-powerpc64-di Architecture: powerpc ppc64 @@ -9947,8 +9458,8 @@ Depends: kernel-image-3.2.0-4-powerpc64-di Description: virtio modules This package contains virtio modules. -Kernel-Version: 3.2.0-4-powerpc64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-powerpc64 Package: uinput-modules-3.2.0-4-powerpc64-di Architecture: powerpc ppc64 @@ -9958,8 +9469,8 @@ Depends: kernel-image-3.2.0-4-powerpc64-di Description: uinput support This package contains the uinput module. -Kernel-Version: 3.2.0-4-powerpc64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-powerpc64 Package: udf-modules-3.2.0-4-powerpc64-di Architecture: powerpc ppc64 @@ -9969,8 +9480,8 @@ Depends: kernel-image-3.2.0-4-powerpc64-di, crc-modules-3.2.0-4-powerpc64-di Description: UDF modules This package contains the UDF filesystem module. -Kernel-Version: 3.2.0-4-powerpc64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-powerpc64 Package: fuse-modules-3.2.0-4-powerpc64-di Architecture: powerpc ppc64 @@ -9980,8 +9491,8 @@ Depends: kernel-image-3.2.0-4-powerpc64-di Description: FUSE modules This package contains the Filesystem in Userspace (FUSE) module. -Kernel-Version: 3.2.0-4-powerpc64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-powerpc64 Package: hypervisor-modules-3.2.0-4-powerpc64-di Architecture: powerpc ppc64 @@ -9992,8 +9503,8 @@ Description: IBM 64bit hypervisor console modules Contains drivers for the hypervisor console, used as console for linux running in logical partitions of IBM hardware supporting it. -Kernel-Version: 3.2.0-4-powerpc64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-powerpc64 Package: fancontrol-modules-3.2.0-4-powerpc64-di Architecture: powerpc ppc64 @@ -10005,8 +9516,8 @@ Contains drivers for macintosh i2c bus as well as for the monitoring devices connected to it. This allows to control the fans during installation. -Kernel-Version: 3.2.0-4-powerpc64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-powerpc64 Package: linux-image-3.2.0-4-powerpc Architecture: powerpc @@ -10102,8 +9613,8 @@ This package contains the kernel image for the Debian installer boot images. It does _not_ provide a usable kernel for your full Debian system. -Kernel-Version: 3.2.0-4-s390x -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-s390x Package: nic-modules-3.2.0-4-s390x-di Architecture: s390 s390x @@ -10113,8 +9624,8 @@ Depends: kernel-image-3.2.0-4-s390x-di, core-modules-3.2.0-4-s390x-di Description: Common NIC drivers This package contains common NIC drivers for the kernel. -Kernel-Version: 3.2.0-4-s390x -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-s390x Package: scsi-core-modules-3.2.0-4-s390x-di Architecture: s390 s390x @@ -10124,8 +9635,8 @@ Depends: kernel-image-3.2.0-4-s390x-di Description: Core SCSI subsystem This package contains the core SCSI subsystem for the kernel. -Kernel-Version: 3.2.0-4-s390x -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-s390x Package: scsi-modules-3.2.0-4-s390x-di Architecture: s390 s390x @@ -10135,8 +9646,8 @@ Depends: kernel-image-3.2.0-4-s390x-di, scsi-core-modules-3.2.0-4-s390x-di, core-modules-3.2.0-4-s390x-di Description: SCSI drivers This package contains SCSI drivers for the kernel. -Kernel-Version: 3.2.0-4-s390x -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-s390x Package: ext2-modules-3.2.0-4-s390x-di Architecture: s390 s390x @@ -10146,8 +9657,8 @@ Depends: kernel-image-3.2.0-4-s390x-di, core-modules-3.2.0-4-s390x-di Description: EXT2 filesystem support This package contains the EXT2 filesystem module for the kernel. -Kernel-Version: 3.2.0-4-s390x -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-s390x Package: ext3-modules-3.2.0-4-s390x-di Architecture: s390 s390x @@ -10157,8 +9668,8 @@ Depends: kernel-image-3.2.0-4-s390x-di, core-modules-3.2.0-4-s390x-di Description: EXT3 filesystem support This package contains the EXT3 filesystem module for the kernel. -Kernel-Version: 3.2.0-4-s390x -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-s390x Package: ext4-modules-3.2.0-4-s390x-di Architecture: s390 s390x @@ -10168,8 +9679,8 @@ Depends: kernel-image-3.2.0-4-s390x-di, core-modules-3.2.0-4-s390x-di Description: EXT4 filesystem support This package contains the EXT4 filesystem module for the kernel. -Kernel-Version: 3.2.0-4-s390x -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-s390x Package: xfs-modules-3.2.0-4-s390x-di Architecture: s390 s390x @@ -10179,8 +9690,8 @@ Depends: kernel-image-3.2.0-4-s390x-di Description: XFS filesystem support This package contains the XFS filesystem module for the kernel. -Kernel-Version: 3.2.0-4-s390x -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-s390x Package: fat-modules-3.2.0-4-s390x-di Architecture: s390 s390x @@ -10190,8 +9701,8 @@ Depends: kernel-image-3.2.0-4-s390x-di Description: FAT filesystem support This package contains the FAT and VFAT filesystem modules for the kernel. -Kernel-Version: 3.2.0-4-s390x -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-s390x Package: md-modules-3.2.0-4-s390x-di Architecture: s390 s390x @@ -10201,8 +9712,8 @@ Depends: kernel-image-3.2.0-4-s390x-di Description: RAID and LVM support This package contains RAID and LVM modules for the kernel. -Kernel-Version: 3.2.0-4-s390x -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-s390x Package: multipath-modules-3.2.0-4-s390x-di Architecture: s390 s390x @@ -10212,8 +9723,8 @@ Depends: kernel-image-3.2.0-4-s390x-di, md-modules-3.2.0-4-s390x-di, scsi-core-modules-3.2.0-4-s390x-di Description: Multipath support This package contains DM-Multipath modules for the kernel. -Kernel-Version: 3.2.0-4-s390x -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-s390x Package: core-modules-3.2.0-4-s390x-di Architecture: s390 s390x @@ -10224,8 +9735,8 @@ Description: Core modules This package contains core modules for the kernel, that will almost always be needed. -Kernel-Version: 3.2.0-4-s390x -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-s390x Package: crypto-modules-3.2.0-4-s390x-di Architecture: s390 s390x @@ -10235,8 +9746,8 @@ Depends: kernel-image-3.2.0-4-s390x-di Description: crypto modules This package contains crypto modules. -Kernel-Version: 3.2.0-4-s390x -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-s390x Package: crypto-dm-modules-3.2.0-4-s390x-di Architecture: s390 s390x @@ -10246,8 +9757,8 @@ Depends: kernel-image-3.2.0-4-s390x-di, md-modules-3.2.0-4-s390x-di Description: devicemapper crypto module This package contains the devicemapper crypto (dm-crypt) module. -Kernel-Version: 3.2.0-4-s390x -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-s390x Package: nbd-modules-3.2.0-4-s390x-di Architecture: s390 s390x @@ -10258,8 +9769,8 @@ Description: Network Block Device modules This package contains the modules required for support of the Network Block Device -Kernel-Version: 3.2.0-4-s390x -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-s390x Package: virtio-modules-3.2.0-4-s390x-di Architecture: s390 s390x @@ -10269,8 +9780,8 @@ Depends: kernel-image-3.2.0-4-s390x-di Description: virtio modules This package contains virtio modules. -Kernel-Version: 3.2.0-4-s390x -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-s390x Package: fuse-modules-3.2.0-4-s390x-di Architecture: s390 s390x @@ -10280,8 +9791,8 @@ Depends: kernel-image-3.2.0-4-s390x-di Description: FUSE modules This package contains the Filesystem in Userspace (FUSE) module. -Kernel-Version: 3.2.0-4-s390x -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-s390x Package: dasd-modules-3.2.0-4-s390x-di Architecture: s390 s390x @@ -10291,8 +9802,8 @@ Depends: kernel-image-3.2.0-4-s390x-di Description: dasd modules This package contains dasd modules. -Kernel-Version: 3.2.0-4-s390x -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-s390x Package: dasd-extra-modules-3.2.0-4-s390x-di Architecture: s390 s390x @@ -10304,8 +9815,8 @@ This package contains the module for dasd DIAG support. The udeb is not loaded by default as the installer does not actually support this. It can however be useful to have available in rescue situations. -Kernel-Version: 3.2.0-4-s390x -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-s390x Package: kernel-image-3.2.0-4-s390x-tape-di Architecture: s390 s390x @@ -10316,8 +9827,8 @@ This package contains the kernel image for the Debian installer boot images. It does _not_ provide a usable kernel for your full Debian system. -Kernel-Version: 3.2.0-4-s390x-tape -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-s390x-tape Package: linux-image-3.2.0-4-s390x Architecture: s390 s390x @@ -10388,8 +9899,8 @@ This package contains the kernel image for the Debian installer boot images. It does _not_ provide a usable kernel for your full Debian system. -Kernel-Version: 3.2.0-4-sh7751r -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-sh7751r Package: nic-modules-3.2.0-4-sh7751r-di Architecture: sh4 @@ -10399,8 +9910,8 @@ Depends: kernel-image-3.2.0-4-sh7751r-di, firewire-core-modules-3.2.0-4-sh7751r-di Description: Common NIC drivers This package contains common NIC drivers for the kernel. -Kernel-Version: 3.2.0-4-sh7751r -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-sh7751r Package: usb-serial-modules-3.2.0-4-sh7751r-di Architecture: sh4 @@ -10410,8 +9921,8 @@ Depends: kernel-image-3.2.0-4-sh7751r-di Description: USB serial drivers This package contains USB serial drivers for the kernel. -Kernel-Version: 3.2.0-4-sh7751r -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-sh7751r Package: ppp-modules-3.2.0-4-sh7751r-di Architecture: sh4 @@ -10421,8 +9932,8 @@ Depends: kernel-image-3.2.0-4-sh7751r-di, zlib-modules-3.2.0-4-sh7751r-di, crc-modules-3.2.0-4-sh7751r-di Description: PPP drivers This package contains PPP drivers for the kernel. -Kernel-Version: 3.2.0-4-sh7751r -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-sh7751r Package: pata-modules-3.2.0-4-sh7751r-di Architecture: sh4 @@ -10432,8 +9943,8 @@ Depends: kernel-image-3.2.0-4-sh7751r-di Description: PATA drivers This package contains PATA drivers for the kernel. -Kernel-Version: 3.2.0-4-sh7751r -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-sh7751r Package: cdrom-core-modules-3.2.0-4-sh7751r-di Architecture: sh4 @@ -10443,8 +9954,8 @@ Depends: kernel-image-3.2.0-4-sh7751r-di, scsi-core-modules-3.2.0-4-sh7751r-di, isofs-modules-3.2.0-4-sh7751r-di Description: CDROM support This package contains core CDROM support for the kernel. -Kernel-Version: 3.2.0-4-sh7751r -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-sh7751r Package: firewire-core-modules-3.2.0-4-sh7751r-di Architecture: sh4 @@ -10454,8 +9965,8 @@ Depends: kernel-image-3.2.0-4-sh7751r-di, scsi-core-modules-3.2.0-4-sh7751r-di, crc-modules-3.2.0-4-sh7751r-di Description: Core FireWire drivers This package contains core FireWire drivers for the kernel. -Kernel-Version: 3.2.0-4-sh7751r -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-sh7751r Package: scsi-core-modules-3.2.0-4-sh7751r-di Architecture: sh4 @@ -10465,8 +9976,8 @@ Depends: kernel-image-3.2.0-4-sh7751r-di Description: Core SCSI subsystem This package contains the core SCSI subsystem for the kernel. -Kernel-Version: 3.2.0-4-sh7751r -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-sh7751r Package: loop-modules-3.2.0-4-sh7751r-di Architecture: sh4 @@ -10476,8 +9987,8 @@ Depends: kernel-image-3.2.0-4-sh7751r-di Description: Loopback filesystem support This package contains loopback filesystem support for the kernel. -Kernel-Version: 3.2.0-4-sh7751r -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-sh7751r Package: ipv6-modules-3.2.0-4-sh7751r-di Architecture: sh4 @@ -10487,8 +9998,8 @@ Depends: kernel-image-3.2.0-4-sh7751r-di Description: IPv6 driver This package contains the IPv6 driver for the kernel. -Kernel-Version: 3.2.0-4-sh7751r -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-sh7751r Package: btrfs-modules-3.2.0-4-sh7751r-di Architecture: sh4 @@ -10498,8 +10009,8 @@ Depends: kernel-image-3.2.0-4-sh7751r-di, crc-modules-3.2.0-4-sh7751r-di, zlib-modules-3.2.0-4-sh7751r-di Description: BTRFS filesystem support This package contains the BTRFS filesystem module for the kernel. -Kernel-Version: 3.2.0-4-sh7751r -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-sh7751r Package: ext2-modules-3.2.0-4-sh7751r-di Architecture: sh4 @@ -10509,8 +10020,8 @@ Depends: kernel-image-3.2.0-4-sh7751r-di Description: EXT2 filesystem support This package contains the EXT2 filesystem module for the kernel. -Kernel-Version: 3.2.0-4-sh7751r -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-sh7751r Package: ext4-modules-3.2.0-4-sh7751r-di Architecture: sh4 @@ -10520,8 +10031,8 @@ Depends: kernel-image-3.2.0-4-sh7751r-di Description: EXT4 filesystem support This package contains the EXT4 filesystem module for the kernel. -Kernel-Version: 3.2.0-4-sh7751r -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-sh7751r Package: isofs-modules-3.2.0-4-sh7751r-di Architecture: sh4 @@ -10531,8 +10042,8 @@ Depends: kernel-image-3.2.0-4-sh7751r-di Description: ISOFS filesystem support This package contains the ISOFS filesystem module for the kernel. -Kernel-Version: 3.2.0-4-sh7751r -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-sh7751r Package: jfs-modules-3.2.0-4-sh7751r-di Architecture: sh4 @@ -10542,8 +10053,8 @@ Depends: kernel-image-3.2.0-4-sh7751r-di Description: JFS filesystem support This package contains the JFS filesystem module for the kernel. -Kernel-Version: 3.2.0-4-sh7751r -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-sh7751r Package: reiserfs-modules-3.2.0-4-sh7751r-di Architecture: sh4 @@ -10553,8 +10064,8 @@ Depends: kernel-image-3.2.0-4-sh7751r-di Description: Reiser filesystem support This package contains the Reiser filesystem module for the kernel. -Kernel-Version: 3.2.0-4-sh7751r -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-sh7751r Package: xfs-modules-3.2.0-4-sh7751r-di Architecture: sh4 @@ -10564,8 +10075,8 @@ Depends: kernel-image-3.2.0-4-sh7751r-di Description: XFS filesystem support This package contains the XFS filesystem module for the kernel. -Kernel-Version: 3.2.0-4-sh7751r -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-sh7751r Package: fat-modules-3.2.0-4-sh7751r-di Architecture: sh4 @@ -10575,8 +10086,8 @@ Depends: kernel-image-3.2.0-4-sh7751r-di Description: FAT filesystem support This package contains the FAT and VFAT filesystem modules for the kernel. -Kernel-Version: 3.2.0-4-sh7751r -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-sh7751r Package: ufs-modules-3.2.0-4-sh7751r-di Architecture: sh4 @@ -10586,8 +10097,8 @@ Depends: kernel-image-3.2.0-4-sh7751r-di Description: UFS filesystem support This package contains the UFS filesystem module for the kernel. -Kernel-Version: 3.2.0-4-sh7751r -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-sh7751r Package: minix-modules-3.2.0-4-sh7751r-di Architecture: sh4 @@ -10597,8 +10108,8 @@ Depends: kernel-image-3.2.0-4-sh7751r-di Description: Minix filesystem support This package contains the Minix filesystem module for the kernel. -Kernel-Version: 3.2.0-4-sh7751r -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-sh7751r Package: md-modules-3.2.0-4-sh7751r-di Architecture: sh4 @@ -10608,8 +10119,8 @@ Depends: kernel-image-3.2.0-4-sh7751r-di Description: RAID and LVM support This package contains RAID and LVM modules for the kernel. -Kernel-Version: 3.2.0-4-sh7751r -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-sh7751r Package: multipath-modules-3.2.0-4-sh7751r-di Architecture: sh4 @@ -10619,8 +10130,8 @@ Depends: kernel-image-3.2.0-4-sh7751r-di, md-modules-3.2.0-4-sh7751r-di, scsi-core-modules-3.2.0-4-sh7751r-di Description: Multipath support This package contains DM-Multipath modules for the kernel. -Kernel-Version: 3.2.0-4-sh7751r -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-sh7751r Package: usb-storage-modules-3.2.0-4-sh7751r-di Architecture: sh4 @@ -10630,8 +10141,8 @@ Depends: kernel-image-3.2.0-4-sh7751r-di, scsi-core-modules-3.2.0-4-sh7751r-di Description: USB storage support This package contains the USB storage driver for the kernel. -Kernel-Version: 3.2.0-4-sh7751r -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-sh7751r Package: parport-modules-3.2.0-4-sh7751r-di Architecture: sh4 @@ -10641,8 +10152,8 @@ Depends: kernel-image-3.2.0-4-sh7751r-di Description: Parallel port support This package contains parallel port drivers for the kernel. -Kernel-Version: 3.2.0-4-sh7751r -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-sh7751r Package: nic-usb-modules-3.2.0-4-sh7751r-di Architecture: sh4 @@ -10652,8 +10163,8 @@ Depends: kernel-image-3.2.0-4-sh7751r-di Description: USB NIC drivers This package contains USB network adapter drivers for the kernel. -Kernel-Version: 3.2.0-4-sh7751r -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-sh7751r Package: sata-modules-3.2.0-4-sh7751r-di Architecture: sh4 @@ -10663,8 +10174,8 @@ Depends: kernel-image-3.2.0-4-sh7751r-di, scsi-core-modules-3.2.0-4-sh7751r-di Description: SATA drivers This package contains SATA drivers for the kernel. -Kernel-Version: 3.2.0-4-sh7751r -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-sh7751r Package: i2c-modules-3.2.0-4-sh7751r-di Architecture: sh4 @@ -10674,8 +10185,8 @@ Depends: kernel-image-3.2.0-4-sh7751r-di Description: i2c support modules This package contains basic i2c support modules. -Kernel-Version: 3.2.0-4-sh7751r -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-sh7751r Package: crc-modules-3.2.0-4-sh7751r-di Architecture: sh4 @@ -10685,8 +10196,8 @@ Depends: kernel-image-3.2.0-4-sh7751r-di Description: CRC modules This package contains CRC support modules. -Kernel-Version: 3.2.0-4-sh7751r -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-sh7751r Package: crypto-modules-3.2.0-4-sh7751r-di Architecture: sh4 @@ -10696,8 +10207,8 @@ Depends: kernel-image-3.2.0-4-sh7751r-di Description: crypto modules This package contains crypto modules. -Kernel-Version: 3.2.0-4-sh7751r -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-sh7751r Package: crypto-dm-modules-3.2.0-4-sh7751r-di Architecture: sh4 @@ -10707,8 +10218,8 @@ Depends: kernel-image-3.2.0-4-sh7751r-di, md-modules-3.2.0-4-sh7751r-di Description: devicemapper crypto module This package contains the devicemapper crypto (dm-crypt) module. -Kernel-Version: 3.2.0-4-sh7751r -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-sh7751r Package: nbd-modules-3.2.0-4-sh7751r-di Architecture: sh4 @@ -10719,8 +10230,8 @@ Description: Network Block Device modules This package contains the modules required for support of the Network Block Device -Kernel-Version: 3.2.0-4-sh7751r -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-sh7751r Package: squashfs-modules-3.2.0-4-sh7751r-di Architecture: sh4 @@ -10730,8 +10241,8 @@ Depends: kernel-image-3.2.0-4-sh7751r-di Description: squashfs modules This package contains squashfs modules. -Kernel-Version: 3.2.0-4-sh7751r -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-sh7751r Package: speakup-modules-3.2.0-4-sh7751r-di Architecture: sh4 @@ -10741,8 +10252,8 @@ Depends: kernel-image-3.2.0-4-sh7751r-di Description: speakup modules This package contains speakup modules. -Kernel-Version: 3.2.0-4-sh7751r -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-sh7751r Package: virtio-modules-3.2.0-4-sh7751r-di Architecture: sh4 @@ -10752,8 +10263,8 @@ Depends: kernel-image-3.2.0-4-sh7751r-di Description: virtio modules This package contains virtio modules. -Kernel-Version: 3.2.0-4-sh7751r -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-sh7751r Package: sound-modules-3.2.0-4-sh7751r-di Architecture: sh4 @@ -10763,8 +10274,8 @@ Depends: kernel-image-3.2.0-4-sh7751r-di, i2c-modules-3.2.0-4-sh7751r-di, firewire-core-modules-3.2.0-4-sh7751r-di, crc-modules-3.2.0-4-sh7751r-di Description: sound support This package contains sound modules. -Kernel-Version: 3.2.0-4-sh7751r -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-sh7751r Package: zlib-modules-3.2.0-4-sh7751r-di Architecture: sh4 @@ -10774,8 +10285,8 @@ Depends: kernel-image-3.2.0-4-sh7751r-di Description: zlib modules This package contains zlib modules. -Kernel-Version: 3.2.0-4-sh7751r -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-sh7751r Package: udf-modules-3.2.0-4-sh7751r-di Architecture: sh4 @@ -10785,8 +10296,8 @@ Depends: kernel-image-3.2.0-4-sh7751r-di, crc-modules-3.2.0-4-sh7751r-di Description: UDF modules This package contains the UDF filesystem module. -Kernel-Version: 3.2.0-4-sh7751r -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-sh7751r Package: fuse-modules-3.2.0-4-sh7751r-di Architecture: sh4 @@ -10796,8 +10307,8 @@ Depends: kernel-image-3.2.0-4-sh7751r-di Description: FUSE modules This package contains the Filesystem in Userspace (FUSE) module. -Kernel-Version: 3.2.0-4-sh7751r -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-sh7751r Package: kernel-image-3.2.0-4-sh7785lcr-di Architecture: sh4 @@ -10808,8 +10319,8 @@ This package contains the kernel image for the Debian installer boot images. It does _not_ provide a usable kernel for your full Debian system. -Kernel-Version: 3.2.0-4-sh7785lcr -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-sh7785lcr Package: nic-modules-3.2.0-4-sh7785lcr-di Architecture: sh4 @@ -10819,8 +10330,8 @@ Depends: kernel-image-3.2.0-4-sh7785lcr-di, firewire-core-modules-3.2.0-4-sh7785lcr-di Description: Common NIC drivers This package contains common NIC drivers for the kernel. -Kernel-Version: 3.2.0-4-sh7785lcr -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-sh7785lcr Package: usb-serial-modules-3.2.0-4-sh7785lcr-di Architecture: sh4 @@ -10830,8 +10341,8 @@ Depends: kernel-image-3.2.0-4-sh7785lcr-di Description: USB serial drivers This package contains USB serial drivers for the kernel. -Kernel-Version: 3.2.0-4-sh7785lcr -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-sh7785lcr Package: ppp-modules-3.2.0-4-sh7785lcr-di Architecture: sh4 @@ -10841,8 +10352,8 @@ Depends: kernel-image-3.2.0-4-sh7785lcr-di, zlib-modules-3.2.0-4-sh7785lcr-di, crc-modules-3.2.0-4-sh7785lcr-di Description: PPP drivers This package contains PPP drivers for the kernel. -Kernel-Version: 3.2.0-4-sh7785lcr -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-sh7785lcr Package: pata-modules-3.2.0-4-sh7785lcr-di Architecture: sh4 @@ -10852,8 +10363,8 @@ Depends: kernel-image-3.2.0-4-sh7785lcr-di Description: PATA drivers This package contains PATA drivers for the kernel. -Kernel-Version: 3.2.0-4-sh7785lcr -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-sh7785lcr Package: cdrom-core-modules-3.2.0-4-sh7785lcr-di Architecture: sh4 @@ -10863,8 +10374,8 @@ Depends: kernel-image-3.2.0-4-sh7785lcr-di, scsi-core-modules-3.2.0-4-sh7785lcr-di, isofs-modules-3.2.0-4-sh7785lcr-di Description: CDROM support This package contains core CDROM support for the kernel. -Kernel-Version: 3.2.0-4-sh7785lcr -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-sh7785lcr Package: firewire-core-modules-3.2.0-4-sh7785lcr-di Architecture: sh4 @@ -10874,8 +10385,8 @@ Depends: kernel-image-3.2.0-4-sh7785lcr-di, scsi-core-modules-3.2.0-4-sh7785lcr-di, crc-modules-3.2.0-4-sh7785lcr-di Description: Core FireWire drivers This package contains core FireWire drivers for the kernel. -Kernel-Version: 3.2.0-4-sh7785lcr -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-sh7785lcr Package: scsi-core-modules-3.2.0-4-sh7785lcr-di Architecture: sh4 @@ -10885,8 +10396,8 @@ Depends: kernel-image-3.2.0-4-sh7785lcr-di Description: Core SCSI subsystem This package contains the core SCSI subsystem for the kernel. -Kernel-Version: 3.2.0-4-sh7785lcr -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-sh7785lcr Package: loop-modules-3.2.0-4-sh7785lcr-di Architecture: sh4 @@ -10896,8 +10407,8 @@ Depends: kernel-image-3.2.0-4-sh7785lcr-di Description: Loopback filesystem support This package contains loopback filesystem support for the kernel. -Kernel-Version: 3.2.0-4-sh7785lcr -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-sh7785lcr Package: ipv6-modules-3.2.0-4-sh7785lcr-di Architecture: sh4 @@ -10907,8 +10418,8 @@ Depends: kernel-image-3.2.0-4-sh7785lcr-di Description: IPv6 driver This package contains the IPv6 driver for the kernel. -Kernel-Version: 3.2.0-4-sh7785lcr -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-sh7785lcr Package: btrfs-modules-3.2.0-4-sh7785lcr-di Architecture: sh4 @@ -10918,8 +10429,8 @@ Depends: kernel-image-3.2.0-4-sh7785lcr-di, crc-modules-3.2.0-4-sh7785lcr-di, zlib-modules-3.2.0-4-sh7785lcr-di Description: BTRFS filesystem support This package contains the BTRFS filesystem module for the kernel. -Kernel-Version: 3.2.0-4-sh7785lcr -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-sh7785lcr Package: ext2-modules-3.2.0-4-sh7785lcr-di Architecture: sh4 @@ -10929,8 +10440,8 @@ Depends: kernel-image-3.2.0-4-sh7785lcr-di Description: EXT2 filesystem support This package contains the EXT2 filesystem module for the kernel. -Kernel-Version: 3.2.0-4-sh7785lcr -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-sh7785lcr Package: ext4-modules-3.2.0-4-sh7785lcr-di Architecture: sh4 @@ -10940,8 +10451,8 @@ Depends: kernel-image-3.2.0-4-sh7785lcr-di Description: EXT4 filesystem support This package contains the EXT4 filesystem module for the kernel. -Kernel-Version: 3.2.0-4-sh7785lcr -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-sh7785lcr Package: isofs-modules-3.2.0-4-sh7785lcr-di Architecture: sh4 @@ -10951,8 +10462,8 @@ Depends: kernel-image-3.2.0-4-sh7785lcr-di Description: ISOFS filesystem support This package contains the ISOFS filesystem module for the kernel. -Kernel-Version: 3.2.0-4-sh7785lcr -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-sh7785lcr Package: jfs-modules-3.2.0-4-sh7785lcr-di Architecture: sh4 @@ -10962,8 +10473,8 @@ Depends: kernel-image-3.2.0-4-sh7785lcr-di Description: JFS filesystem support This package contains the JFS filesystem module for the kernel. -Kernel-Version: 3.2.0-4-sh7785lcr -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-sh7785lcr Package: reiserfs-modules-3.2.0-4-sh7785lcr-di Architecture: sh4 @@ -10973,8 +10484,8 @@ Depends: kernel-image-3.2.0-4-sh7785lcr-di Description: Reiser filesystem support This package contains the Reiser filesystem module for the kernel. -Kernel-Version: 3.2.0-4-sh7785lcr -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-sh7785lcr Package: xfs-modules-3.2.0-4-sh7785lcr-di Architecture: sh4 @@ -10984,8 +10495,8 @@ Depends: kernel-image-3.2.0-4-sh7785lcr-di Description: XFS filesystem support This package contains the XFS filesystem module for the kernel. -Kernel-Version: 3.2.0-4-sh7785lcr -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-sh7785lcr Package: fat-modules-3.2.0-4-sh7785lcr-di Architecture: sh4 @@ -10995,8 +10506,8 @@ Depends: kernel-image-3.2.0-4-sh7785lcr-di Description: FAT filesystem support This package contains the FAT and VFAT filesystem modules for the kernel. -Kernel-Version: 3.2.0-4-sh7785lcr -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-sh7785lcr Package: ufs-modules-3.2.0-4-sh7785lcr-di Architecture: sh4 @@ -11006,8 +10517,8 @@ Depends: kernel-image-3.2.0-4-sh7785lcr-di Description: UFS filesystem support This package contains the UFS filesystem module for the kernel. -Kernel-Version: 3.2.0-4-sh7785lcr -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-sh7785lcr Package: minix-modules-3.2.0-4-sh7785lcr-di Architecture: sh4 @@ -11017,8 +10528,8 @@ Depends: kernel-image-3.2.0-4-sh7785lcr-di Description: Minix filesystem support This package contains the Minix filesystem module for the kernel. -Kernel-Version: 3.2.0-4-sh7785lcr -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-sh7785lcr Package: md-modules-3.2.0-4-sh7785lcr-di Architecture: sh4 @@ -11028,8 +10539,8 @@ Depends: kernel-image-3.2.0-4-sh7785lcr-di Description: RAID and LVM support This package contains RAID and LVM modules for the kernel. -Kernel-Version: 3.2.0-4-sh7785lcr -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-sh7785lcr Package: multipath-modules-3.2.0-4-sh7785lcr-di Architecture: sh4 @@ -11039,8 +10550,8 @@ Depends: kernel-image-3.2.0-4-sh7785lcr-di, md-modules-3.2.0-4-sh7785lcr-di, scsi-core-modules-3.2.0-4-sh7785lcr-di Description: Multipath support This package contains DM-Multipath modules for the kernel. -Kernel-Version: 3.2.0-4-sh7785lcr -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-sh7785lcr Package: parport-modules-3.2.0-4-sh7785lcr-di Architecture: sh4 @@ -11050,8 +10561,8 @@ Depends: kernel-image-3.2.0-4-sh7785lcr-di Description: Parallel port support This package contains parallel port drivers for the kernel. -Kernel-Version: 3.2.0-4-sh7785lcr -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-sh7785lcr Package: nic-usb-modules-3.2.0-4-sh7785lcr-di Architecture: sh4 @@ -11061,8 +10572,8 @@ Depends: kernel-image-3.2.0-4-sh7785lcr-di Description: USB NIC drivers This package contains USB network adapter drivers for the kernel. -Kernel-Version: 3.2.0-4-sh7785lcr -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-sh7785lcr Package: sata-modules-3.2.0-4-sh7785lcr-di Architecture: sh4 @@ -11072,8 +10583,8 @@ Depends: kernel-image-3.2.0-4-sh7785lcr-di, scsi-core-modules-3.2.0-4-sh7785lcr-di Description: SATA drivers This package contains SATA drivers for the kernel. -Kernel-Version: 3.2.0-4-sh7785lcr -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-sh7785lcr Package: crc-modules-3.2.0-4-sh7785lcr-di Architecture: sh4 @@ -11083,8 +10594,8 @@ Depends: kernel-image-3.2.0-4-sh7785lcr-di Description: CRC modules This package contains CRC support modules. -Kernel-Version: 3.2.0-4-sh7785lcr -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-sh7785lcr Package: crypto-modules-3.2.0-4-sh7785lcr-di Architecture: sh4 @@ -11094,8 +10605,8 @@ Depends: kernel-image-3.2.0-4-sh7785lcr-di Description: crypto modules This package contains crypto modules. -Kernel-Version: 3.2.0-4-sh7785lcr -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-sh7785lcr Package: crypto-dm-modules-3.2.0-4-sh7785lcr-di Architecture: sh4 @@ -11105,8 +10616,8 @@ Depends: kernel-image-3.2.0-4-sh7785lcr-di, md-modules-3.2.0-4-sh7785lcr-di Description: devicemapper crypto module This package contains the devicemapper crypto (dm-crypt) module. -Kernel-Version: 3.2.0-4-sh7785lcr -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-sh7785lcr Package: nbd-modules-3.2.0-4-sh7785lcr-di Architecture: sh4 @@ -11117,8 +10628,8 @@ Description: Network Block Device modules This package contains the modules required for support of the Network Block Device -Kernel-Version: 3.2.0-4-sh7785lcr -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-sh7785lcr Package: squashfs-modules-3.2.0-4-sh7785lcr-di Architecture: sh4 @@ -11128,8 +10639,8 @@ Depends: kernel-image-3.2.0-4-sh7785lcr-di Description: squashfs modules This package contains squashfs modules. -Kernel-Version: 3.2.0-4-sh7785lcr -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-sh7785lcr Package: speakup-modules-3.2.0-4-sh7785lcr-di Architecture: sh4 @@ -11139,8 +10650,8 @@ Depends: kernel-image-3.2.0-4-sh7785lcr-di Description: speakup modules This package contains speakup modules. -Kernel-Version: 3.2.0-4-sh7785lcr -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-sh7785lcr Package: sound-modules-3.2.0-4-sh7785lcr-di Architecture: sh4 @@ -11150,8 +10661,8 @@ Depends: kernel-image-3.2.0-4-sh7785lcr-di, firewire-core-modules-3.2.0-4-sh7785lcr-di, crc-modules-3.2.0-4-sh7785lcr-di Description: sound support This package contains sound modules. -Kernel-Version: 3.2.0-4-sh7785lcr -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-sh7785lcr Package: zlib-modules-3.2.0-4-sh7785lcr-di Architecture: sh4 @@ -11161,8 +10672,8 @@ Depends: kernel-image-3.2.0-4-sh7785lcr-di Description: zlib modules This package contains zlib modules. -Kernel-Version: 3.2.0-4-sh7785lcr -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-sh7785lcr Package: udf-modules-3.2.0-4-sh7785lcr-di Architecture: sh4 @@ -11172,8 +10683,8 @@ Depends: kernel-image-3.2.0-4-sh7785lcr-di, crc-modules-3.2.0-4-sh7785lcr-di Description: UDF modules This package contains the UDF filesystem module. -Kernel-Version: 3.2.0-4-sh7785lcr -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-sh7785lcr Package: fuse-modules-3.2.0-4-sh7785lcr-di Architecture: sh4 @@ -11183,8 +10694,8 @@ Depends: kernel-image-3.2.0-4-sh7785lcr-di Description: FUSE modules This package contains the Filesystem in Userspace (FUSE) module. -Kernel-Version: 3.2.0-4-sh7785lcr -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-sh7785lcr Package: linux-image-3.2.0-4-sh7751r Architecture: sh4 @@ -11251,8 +10762,8 @@ This package contains the kernel image for the Debian installer boot images. It does _not_ provide a usable kernel for your full Debian system. -Kernel-Version: 3.2.0-4-sparc64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-sparc64 Package: nic-modules-3.2.0-4-sparc64-di Architecture: sparc sparc64 @@ -11267,8 +10778,8 @@ . Do not install this package on a real Debian system! You probably want a kernel-image package instead. -Kernel-Version: 3.2.0-4-sparc64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-sparc64 Package: ppp-modules-3.2.0-4-sparc64-di Architecture: sparc sparc64 @@ -11278,8 +10789,8 @@ Depends: kernel-image-3.2.0-4-sparc64-di, zlib-modules-3.2.0-4-sparc64-di Description: PPP drivers This package contains PPP drivers for the kernel. -Kernel-Version: 3.2.0-4-sparc64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-sparc64 Package: pata-modules-3.2.0-4-sparc64-di Architecture: sparc sparc64 @@ -11289,8 +10800,8 @@ Depends: kernel-image-3.2.0-4-sparc64-di, ata-modules-3.2.0-4-sparc64-di Description: PATA drivers This package contains PATA drivers for the kernel. -Kernel-Version: 3.2.0-4-sparc64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-sparc64 Package: cdrom-core-modules-3.2.0-4-sparc64-di Architecture: sparc sparc64 @@ -11300,8 +10811,8 @@ Depends: kernel-image-3.2.0-4-sparc64-di, scsi-core-modules-3.2.0-4-sparc64-di, isofs-modules-3.2.0-4-sparc64-di Description: CDROM support This package contains core CDROM support for the kernel. -Kernel-Version: 3.2.0-4-sparc64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-sparc64 Package: scsi-core-modules-3.2.0-4-sparc64-di Architecture: sparc sparc64 @@ -11311,8 +10822,8 @@ Depends: kernel-image-3.2.0-4-sparc64-di Description: Core SCSI subsystem This package contains the core SCSI subsystem for the kernel. -Kernel-Version: 3.2.0-4-sparc64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-sparc64 Package: scsi-modules-3.2.0-4-sparc64-di Architecture: sparc sparc64 @@ -11322,8 +10833,8 @@ Depends: kernel-image-3.2.0-4-sparc64-di, scsi-core-modules-3.2.0-4-sparc64-di, cdrom-core-modules-3.2.0-4-sparc64-di, core-modules-3.2.0-4-sparc64-di, ata-modules-3.2.0-4-sparc64-di Description: SCSI drivers This package contains SCSI drivers for the kernel. -Kernel-Version: 3.2.0-4-sparc64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-sparc64 Package: scsi-common-modules-3.2.0-4-sparc64-di Architecture: sparc sparc64 @@ -11333,8 +10844,8 @@ Depends: kernel-image-3.2.0-4-sparc64-di, scsi-core-modules-3.2.0-4-sparc64-di, cdrom-core-modules-3.2.0-4-sparc64-di Description: Very common SCSI drivers This package contains very common SCSI drivers for the kernel. -Kernel-Version: 3.2.0-4-sparc64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-sparc64 Package: plip-modules-3.2.0-4-sparc64-di Architecture: sparc sparc64 @@ -11344,8 +10855,8 @@ Depends: kernel-image-3.2.0-4-sparc64-di Description: PLIP drivers This package contains PLIP drivers for the kernel. -Kernel-Version: 3.2.0-4-sparc64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-sparc64 Package: btrfs-modules-3.2.0-4-sparc64-di Architecture: sparc sparc64 @@ -11355,8 +10866,8 @@ Depends: kernel-image-3.2.0-4-sparc64-di, core-modules-3.2.0-4-sparc64-di, zlib-modules-3.2.0-4-sparc64-di Description: BTRFS filesystem support This package contains the BTRFS filesystem module for the kernel. -Kernel-Version: 3.2.0-4-sparc64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-sparc64 Package: ext2-modules-3.2.0-4-sparc64-di Architecture: sparc sparc64 @@ -11366,8 +10877,8 @@ Depends: kernel-image-3.2.0-4-sparc64-di, core-modules-3.2.0-4-sparc64-di Description: EXT2 filesystem support This package contains the EXT2 filesystem module for the kernel. -Kernel-Version: 3.2.0-4-sparc64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-sparc64 Package: ext3-modules-3.2.0-4-sparc64-di Architecture: sparc sparc64 @@ -11377,8 +10888,8 @@ Depends: kernel-image-3.2.0-4-sparc64-di, core-modules-3.2.0-4-sparc64-di Description: EXT3 filesystem support This package contains the EXT3 filesystem module for the kernel. -Kernel-Version: 3.2.0-4-sparc64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-sparc64 Package: ext4-modules-3.2.0-4-sparc64-di Architecture: sparc sparc64 @@ -11388,8 +10899,8 @@ Depends: kernel-image-3.2.0-4-sparc64-di, core-modules-3.2.0-4-sparc64-di Description: EXT4 filesystem support This package contains the EXT4 filesystem module for the kernel. -Kernel-Version: 3.2.0-4-sparc64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-sparc64 Package: isofs-modules-3.2.0-4-sparc64-di Architecture: sparc sparc64 @@ -11399,8 +10910,8 @@ Depends: kernel-image-3.2.0-4-sparc64-di Description: ISOFS filesystem support This package contains the ISOFS filesystem module for the kernel. -Kernel-Version: 3.2.0-4-sparc64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-sparc64 Package: jfs-modules-3.2.0-4-sparc64-di Architecture: sparc sparc64 @@ -11410,8 +10921,8 @@ Depends: kernel-image-3.2.0-4-sparc64-di Description: JFS filesystem support This package contains the JFS filesystem module for the kernel. -Kernel-Version: 3.2.0-4-sparc64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-sparc64 Package: reiserfs-modules-3.2.0-4-sparc64-di Architecture: sparc sparc64 @@ -11421,8 +10932,8 @@ Depends: kernel-image-3.2.0-4-sparc64-di Description: Reiser filesystem support This package contains the Reiser filesystem module for the kernel. -Kernel-Version: 3.2.0-4-sparc64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-sparc64 Package: xfs-modules-3.2.0-4-sparc64-di Architecture: sparc sparc64 @@ -11432,8 +10943,8 @@ Depends: kernel-image-3.2.0-4-sparc64-di Description: XFS filesystem support This package contains the XFS filesystem module for the kernel. -Kernel-Version: 3.2.0-4-sparc64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-sparc64 Package: fat-modules-3.2.0-4-sparc64-di Architecture: sparc sparc64 @@ -11443,8 +10954,8 @@ Depends: kernel-image-3.2.0-4-sparc64-di Description: FAT filesystem support This package contains the FAT and VFAT filesystem modules for the kernel. -Kernel-Version: 3.2.0-4-sparc64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-sparc64 Package: md-modules-3.2.0-4-sparc64-di Architecture: sparc sparc64 @@ -11454,8 +10965,8 @@ Depends: kernel-image-3.2.0-4-sparc64-di Description: RAID and LVM support This package contains RAID and LVM modules for the kernel. -Kernel-Version: 3.2.0-4-sparc64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-sparc64 Package: multipath-modules-3.2.0-4-sparc64-di Architecture: sparc sparc64 @@ -11465,8 +10976,8 @@ Depends: kernel-image-3.2.0-4-sparc64-di, md-modules-3.2.0-4-sparc64-di, scsi-core-modules-3.2.0-4-sparc64-di Description: Multipath support This package contains DM-Multipath modules for the kernel. -Kernel-Version: 3.2.0-4-sparc64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-sparc64 Package: usb-modules-3.2.0-4-sparc64-di Architecture: sparc sparc64 @@ -11476,8 +10987,8 @@ Depends: kernel-image-3.2.0-4-sparc64-di Description: USB support This package contains core USB drivers for the kernel. -Kernel-Version: 3.2.0-4-sparc64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-sparc64 Package: usb-storage-modules-3.2.0-4-sparc64-di Architecture: sparc sparc64 @@ -11487,8 +10998,8 @@ Depends: kernel-image-3.2.0-4-sparc64-di, scsi-core-modules-3.2.0-4-sparc64-di, usb-modules-3.2.0-4-sparc64-di Description: USB storage support This package contains the USB storage driver for the kernel. -Kernel-Version: 3.2.0-4-sparc64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-sparc64 Package: input-modules-3.2.0-4-sparc64-di Architecture: sparc sparc64 @@ -11498,8 +11009,8 @@ Depends: kernel-image-3.2.0-4-sparc64-di, usb-modules-3.2.0-4-sparc64-di Description: Input devices support This package contains input device drivers for the kernel. -Kernel-Version: 3.2.0-4-sparc64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-sparc64 Package: sata-modules-3.2.0-4-sparc64-di Architecture: sparc sparc64 @@ -11509,8 +11020,8 @@ Depends: kernel-image-3.2.0-4-sparc64-di, scsi-core-modules-3.2.0-4-sparc64-di, ata-modules-3.2.0-4-sparc64-di Description: SATA drivers This package contains SATA drivers for the kernel. -Kernel-Version: 3.2.0-4-sparc64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-sparc64 Package: core-modules-3.2.0-4-sparc64-di Architecture: sparc sparc64 @@ -11521,8 +11032,8 @@ Description: Core modules This package contains core modules for the kernel, that will almost always be needed. -Kernel-Version: 3.2.0-4-sparc64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-sparc64 Package: crypto-modules-3.2.0-4-sparc64-di Architecture: sparc sparc64 @@ -11532,8 +11043,8 @@ Depends: kernel-image-3.2.0-4-sparc64-di Description: crypto modules This package contains crypto modules. -Kernel-Version: 3.2.0-4-sparc64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-sparc64 Package: crypto-dm-modules-3.2.0-4-sparc64-di Architecture: sparc sparc64 @@ -11543,8 +11054,8 @@ Depends: kernel-image-3.2.0-4-sparc64-di, md-modules-3.2.0-4-sparc64-di Description: devicemapper crypto module This package contains the devicemapper crypto (dm-crypt) module. -Kernel-Version: 3.2.0-4-sparc64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-sparc64 Package: ata-modules-3.2.0-4-sparc64-di Architecture: sparc sparc64 @@ -11555,8 +11066,8 @@ Description: ATA disk modules This package contains core ATA disk modules used by both PATA and SATA disk drivers. -Kernel-Version: 3.2.0-4-sparc64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-sparc64 Package: nbd-modules-3.2.0-4-sparc64-di Architecture: sparc sparc64 @@ -11567,8 +11078,8 @@ Description: Network Block Device modules This package contains the modules required for support of the Network Block Device -Kernel-Version: 3.2.0-4-sparc64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-sparc64 Package: squashfs-modules-3.2.0-4-sparc64-di Architecture: sparc sparc64 @@ -11578,8 +11089,8 @@ Depends: kernel-image-3.2.0-4-sparc64-di Description: squashfs modules This package contains squashfs modules. -Kernel-Version: 3.2.0-4-sparc64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-sparc64 Package: virtio-modules-3.2.0-4-sparc64-di Architecture: sparc sparc64 @@ -11589,8 +11100,8 @@ Depends: kernel-image-3.2.0-4-sparc64-di Description: virtio modules This package contains virtio modules. -Kernel-Version: 3.2.0-4-sparc64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-sparc64 Package: zlib-modules-3.2.0-4-sparc64-di Architecture: sparc sparc64 @@ -11600,8 +11111,8 @@ Depends: kernel-image-3.2.0-4-sparc64-di Description: zlib modules This package contains zlib modules. -Kernel-Version: 3.2.0-4-sparc64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-sparc64 Package: udf-modules-3.2.0-4-sparc64-di Architecture: sparc sparc64 @@ -11611,8 +11122,8 @@ Depends: kernel-image-3.2.0-4-sparc64-di Description: UDF modules This package contains the UDF filesystem module. -Kernel-Version: 3.2.0-4-sparc64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-sparc64 Package: fuse-modules-3.2.0-4-sparc64-di Architecture: sparc sparc64 @@ -11622,8 +11133,8 @@ Depends: kernel-image-3.2.0-4-sparc64-di Description: FUSE modules This package contains the Filesystem in Userspace (FUSE) module. -Kernel-Version: 3.2.0-4-sparc64 -Package-Type: udeb +XC-Package-Type: udeb +XB-Kernel-Version: 3.2.0-4-sparc64 Package: linux-image-3.2.0-4-sparc64 Architecture: sparc sparc64 diff -Nru linux-3.2.46/debian/control.md5sum linux-3.2.46/debian/control.md5sum --- linux-3.2.46/debian/control.md5sum 2013-06-08 21:44:19.000000000 +0000 +++ linux-3.2.46/debian/control.md5sum 2013-07-26 21:15:07.000000000 +0000 @@ -1,5 +1,5 @@ 1f6dcffb2a91d522eabe7e1ecf65f22f debian/bin/gencontrol.py -e7954ea9b62802652a5a6597dd5c97ec debian/changelog +a8674e4fe88cda9ed1159b6cc10fd10e debian/changelog d253b8a3cc1ffc2054b1d485facc490a debian/templates/control.headers.arch.in d60e1ee86882c530ea74bfbb684a506e debian/templates/control.headers.featureset.in 3a8040742dfc77adae08116a336e98c3 debian/templates/control.headers.in @@ -15,7 +15,7 @@ 7805244237b17ec0c1e068c364136ee1 debian/config/alpha/defines 3d96cae2effd53505bc5bbd4757e84ae debian/config/amd64/defines 159a7bc773dbd2714d6fe996f03b257d debian/config/armel/defines -cf147e7ee6517debc3c4ae7902ba33ab debian/config/armhf/defines +5cc055c69dff8e48f3bf13766cc667f9 debian/config/armhf/defines 366b94d652a66b437eabcd165bcc9610 debian/config/featureset-rt/defines 7663688e373ff5b5857c15e69a7c1d3e debian/config/hppa/defines 7c7dbe81936c5309f7830d6172380486 debian/config/i386/defines @@ -36,7 +36,7 @@ 7146ff53fc4f9fbb49948225d8589b69 debian/config/i386/rt/defines 7ecaa8334419297fe6715afadae794c6 debian/installer/amd64/kernel-versions 07c9cbe632c22b1a4d696e305a43dd79 debian/installer/armel/kernel-versions -8fc812d2bcca102604f6e03fc145e6bd debian/installer/armhf/kernel-versions +c6c2f69708acb852bcf319c7d9bfcdc2 debian/installer/armhf/kernel-versions fb5fd18c89403e59d2df08c6b261ba87 debian/installer/hppa/kernel-versions 967797430d58c1aeecac819cd6c23bd8 debian/installer/i386/kernel-versions 3003a272236f91494508a5f7e9c9b467 debian/installer/ia64/kernel-versions diff -Nru linux-3.2.46/debian/installer/armhf/kernel-versions linux-3.2.46/debian/installer/armhf/kernel-versions --- linux-3.2.46/debian/installer/armhf/kernel-versions 2013-02-24 03:53:13.000000000 +0000 +++ linux-3.2.46/debian/installer/armhf/kernel-versions 2013-07-26 18:03:26.000000000 +0000 @@ -1,3 +1,3 @@ # arch version flavour installedname suffix build-depends -armhf - mx5 - y - -armhf - vexpress - y - +armhf - rpi - y - + diff -Nru linux-3.2.46/debian/installer/armhf/modules/armhf-rpi/btrfs-modules linux-3.2.46/debian/installer/armhf/modules/armhf-rpi/btrfs-modules --- linux-3.2.46/debian/installer/armhf/modules/armhf-rpi/btrfs-modules 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/installer/armhf/modules/armhf-rpi/btrfs-modules 2013-07-26 18:03:26.000000000 +0000 @@ -0,0 +1 @@ +#include diff -Nru linux-3.2.46/debian/installer/armhf/modules/armhf-rpi/crc-modules linux-3.2.46/debian/installer/armhf/modules/armhf-rpi/crc-modules --- linux-3.2.46/debian/installer/armhf/modules/armhf-rpi/crc-modules 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/installer/armhf/modules/armhf-rpi/crc-modules 2013-07-26 18:03:26.000000000 +0000 @@ -0,0 +1 @@ +#include diff -Nru linux-3.2.46/debian/installer/armhf/modules/armhf-rpi/crypto-dm-modules linux-3.2.46/debian/installer/armhf/modules/armhf-rpi/crypto-dm-modules --- linux-3.2.46/debian/installer/armhf/modules/armhf-rpi/crypto-dm-modules 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/installer/armhf/modules/armhf-rpi/crypto-dm-modules 2013-07-26 18:03:26.000000000 +0000 @@ -0,0 +1 @@ +#include diff -Nru linux-3.2.46/debian/installer/armhf/modules/armhf-rpi/crypto-modules linux-3.2.46/debian/installer/armhf/modules/armhf-rpi/crypto-modules --- linux-3.2.46/debian/installer/armhf/modules/armhf-rpi/crypto-modules 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/installer/armhf/modules/armhf-rpi/crypto-modules 2013-07-26 18:03:26.000000000 +0000 @@ -0,0 +1 @@ +#include diff -Nru linux-3.2.46/debian/installer/armhf/modules/armhf-rpi/ext2-modules linux-3.2.46/debian/installer/armhf/modules/armhf-rpi/ext2-modules --- linux-3.2.46/debian/installer/armhf/modules/armhf-rpi/ext2-modules 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/installer/armhf/modules/armhf-rpi/ext2-modules 2013-07-26 18:03:26.000000000 +0000 @@ -0,0 +1 @@ +#include diff -Nru linux-3.2.46/debian/installer/armhf/modules/armhf-rpi/ext3-modules linux-3.2.46/debian/installer/armhf/modules/armhf-rpi/ext3-modules --- linux-3.2.46/debian/installer/armhf/modules/armhf-rpi/ext3-modules 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/installer/armhf/modules/armhf-rpi/ext3-modules 2013-07-26 18:03:26.000000000 +0000 @@ -0,0 +1 @@ +#include diff -Nru linux-3.2.46/debian/installer/armhf/modules/armhf-rpi/fat-modules linux-3.2.46/debian/installer/armhf/modules/armhf-rpi/fat-modules --- linux-3.2.46/debian/installer/armhf/modules/armhf-rpi/fat-modules 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/installer/armhf/modules/armhf-rpi/fat-modules 2013-07-26 18:03:26.000000000 +0000 @@ -0,0 +1 @@ +#include diff -Nru linux-3.2.46/debian/installer/armhf/modules/armhf-rpi/fuse-modules linux-3.2.46/debian/installer/armhf/modules/armhf-rpi/fuse-modules --- linux-3.2.46/debian/installer/armhf/modules/armhf-rpi/fuse-modules 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/installer/armhf/modules/armhf-rpi/fuse-modules 2013-07-26 18:03:26.000000000 +0000 @@ -0,0 +1 @@ +#include diff -Nru linux-3.2.46/debian/installer/armhf/modules/armhf-rpi/input-modules linux-3.2.46/debian/installer/armhf/modules/armhf-rpi/input-modules --- linux-3.2.46/debian/installer/armhf/modules/armhf-rpi/input-modules 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/installer/armhf/modules/armhf-rpi/input-modules 2013-07-26 18:03:26.000000000 +0000 @@ -0,0 +1,4 @@ +#include +usbhid - +usbmouse - +usbkbd - diff -Nru linux-3.2.46/debian/installer/armhf/modules/armhf-rpi/ipv6-modules linux-3.2.46/debian/installer/armhf/modules/armhf-rpi/ipv6-modules --- linux-3.2.46/debian/installer/armhf/modules/armhf-rpi/ipv6-modules 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/installer/armhf/modules/armhf-rpi/ipv6-modules 2013-07-26 18:03:26.000000000 +0000 @@ -0,0 +1 @@ +#include diff -Nru linux-3.2.46/debian/installer/armhf/modules/armhf-rpi/isofs-modules linux-3.2.46/debian/installer/armhf/modules/armhf-rpi/isofs-modules --- linux-3.2.46/debian/installer/armhf/modules/armhf-rpi/isofs-modules 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/installer/armhf/modules/armhf-rpi/isofs-modules 2013-07-26 18:03:26.000000000 +0000 @@ -0,0 +1 @@ +#include diff -Nru linux-3.2.46/debian/installer/armhf/modules/armhf-rpi/jfs-modules linux-3.2.46/debian/installer/armhf/modules/armhf-rpi/jfs-modules --- linux-3.2.46/debian/installer/armhf/modules/armhf-rpi/jfs-modules 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/installer/armhf/modules/armhf-rpi/jfs-modules 2013-07-26 18:03:26.000000000 +0000 @@ -0,0 +1 @@ +#include diff -Nru linux-3.2.46/debian/installer/armhf/modules/armhf-rpi/kernel-image linux-3.2.46/debian/installer/armhf/modules/armhf-rpi/kernel-image --- linux-3.2.46/debian/installer/armhf/modules/armhf-rpi/kernel-image 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/installer/armhf/modules/armhf-rpi/kernel-image 2013-07-26 18:03:26.000000000 +0000 @@ -0,0 +1 @@ +# empty diff -Nru linux-3.2.46/debian/installer/armhf/modules/armhf-rpi/loop-modules linux-3.2.46/debian/installer/armhf/modules/armhf-rpi/loop-modules --- linux-3.2.46/debian/installer/armhf/modules/armhf-rpi/loop-modules 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/installer/armhf/modules/armhf-rpi/loop-modules 2013-07-26 18:03:26.000000000 +0000 @@ -0,0 +1 @@ +#include diff -Nru linux-3.2.46/debian/installer/armhf/modules/armhf-rpi/md-modules linux-3.2.46/debian/installer/armhf/modules/armhf-rpi/md-modules --- linux-3.2.46/debian/installer/armhf/modules/armhf-rpi/md-modules 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/installer/armhf/modules/armhf-rpi/md-modules 2013-07-26 18:03:26.000000000 +0000 @@ -0,0 +1 @@ +#include diff -Nru linux-3.2.46/debian/installer/armhf/modules/armhf-rpi/minix-modules linux-3.2.46/debian/installer/armhf/modules/armhf-rpi/minix-modules --- linux-3.2.46/debian/installer/armhf/modules/armhf-rpi/minix-modules 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/installer/armhf/modules/armhf-rpi/minix-modules 2013-07-26 18:03:26.000000000 +0000 @@ -0,0 +1 @@ +#include diff -Nru linux-3.2.46/debian/installer/armhf/modules/armhf-rpi/multipath-modules linux-3.2.46/debian/installer/armhf/modules/armhf-rpi/multipath-modules --- linux-3.2.46/debian/installer/armhf/modules/armhf-rpi/multipath-modules 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/installer/armhf/modules/armhf-rpi/multipath-modules 2013-07-26 18:03:26.000000000 +0000 @@ -0,0 +1 @@ +#include diff -Nru linux-3.2.46/debian/installer/armhf/modules/armhf-rpi/nbd-modules linux-3.2.46/debian/installer/armhf/modules/armhf-rpi/nbd-modules --- linux-3.2.46/debian/installer/armhf/modules/armhf-rpi/nbd-modules 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/installer/armhf/modules/armhf-rpi/nbd-modules 2013-07-26 18:03:26.000000000 +0000 @@ -0,0 +1 @@ +#include diff -Nru linux-3.2.46/debian/installer/armhf/modules/armhf-rpi/nic-usb-modules linux-3.2.46/debian/installer/armhf/modules/armhf-rpi/nic-usb-modules --- linux-3.2.46/debian/installer/armhf/modules/armhf-rpi/nic-usb-modules 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/installer/armhf/modules/armhf-rpi/nic-usb-modules 2013-07-26 18:03:26.000000000 +0000 @@ -0,0 +1 @@ +#include diff -Nru linux-3.2.46/debian/installer/armhf/modules/armhf-rpi/reiserfs-modules linux-3.2.46/debian/installer/armhf/modules/armhf-rpi/reiserfs-modules --- linux-3.2.46/debian/installer/armhf/modules/armhf-rpi/reiserfs-modules 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/installer/armhf/modules/armhf-rpi/reiserfs-modules 2013-07-26 18:03:26.000000000 +0000 @@ -0,0 +1 @@ +#include diff -Nru linux-3.2.46/debian/installer/armhf/modules/armhf-rpi/scsi-core-modules linux-3.2.46/debian/installer/armhf/modules/armhf-rpi/scsi-core-modules --- linux-3.2.46/debian/installer/armhf/modules/armhf-rpi/scsi-core-modules 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/installer/armhf/modules/armhf-rpi/scsi-core-modules 2013-07-26 18:03:26.000000000 +0000 @@ -0,0 +1,3 @@ +#include +scsi_mod - +sd_mod - diff -Nru linux-3.2.46/debian/installer/armhf/modules/armhf-rpi/squashfs-modules linux-3.2.46/debian/installer/armhf/modules/armhf-rpi/squashfs-modules --- linux-3.2.46/debian/installer/armhf/modules/armhf-rpi/squashfs-modules 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/installer/armhf/modules/armhf-rpi/squashfs-modules 2013-07-26 18:03:26.000000000 +0000 @@ -0,0 +1 @@ +#include diff -Nru linux-3.2.46/debian/installer/armhf/modules/armhf-rpi/udf-modules linux-3.2.46/debian/installer/armhf/modules/armhf-rpi/udf-modules --- linux-3.2.46/debian/installer/armhf/modules/armhf-rpi/udf-modules 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/installer/armhf/modules/armhf-rpi/udf-modules 2013-07-26 18:03:26.000000000 +0000 @@ -0,0 +1 @@ +#include diff -Nru linux-3.2.46/debian/installer/armhf/modules/armhf-rpi/uinput-modules linux-3.2.46/debian/installer/armhf/modules/armhf-rpi/uinput-modules --- linux-3.2.46/debian/installer/armhf/modules/armhf-rpi/uinput-modules 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/installer/armhf/modules/armhf-rpi/uinput-modules 2013-07-26 18:03:26.000000000 +0000 @@ -0,0 +1 @@ +#include diff -Nru linux-3.2.46/debian/installer/armhf/modules/armhf-rpi/usb-storage-modules linux-3.2.46/debian/installer/armhf/modules/armhf-rpi/usb-storage-modules --- linux-3.2.46/debian/installer/armhf/modules/armhf-rpi/usb-storage-modules 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/installer/armhf/modules/armhf-rpi/usb-storage-modules 2013-07-26 18:03:26.000000000 +0000 @@ -0,0 +1,2 @@ +#include +usb-storage - diff -Nru linux-3.2.46/debian/patches/bugfix/all/0004-media-staging-lirc_serial-Fix-bogus-error-codes.patch linux-3.2.46/debian/patches/bugfix/all/0004-media-staging-lirc_serial-Fix-bogus-error-codes.patch --- linux-3.2.46/debian/patches/bugfix/all/0004-media-staging-lirc_serial-Fix-bogus-error-codes.patch 2013-02-24 03:52:24.000000000 +0000 +++ linux-3.2.46/debian/patches/bugfix/all/0004-media-staging-lirc_serial-Fix-bogus-error-codes.patch 2013-07-26 19:17:31.000000000 +0000 @@ -16,11 +16,11 @@ drivers/staging/media/lirc/lirc_serial.c | 23 ++++++++++++----------- 1 files changed, 12 insertions(+), 11 deletions(-) -diff --git a/drivers/staging/media/lirc/lirc_serial.c b/drivers/staging/media/lirc/lirc_serial.c -index befe626..6f5257e 100644 ---- a/drivers/staging/media/lirc/lirc_serial.c -+++ b/drivers/staging/media/lirc/lirc_serial.c -@@ -773,7 +773,7 @@ static int hardware_init_port(void) +Index: linux-3.2.46/drivers/staging/media/lirc/lirc_serial.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/media/lirc/lirc_serial.c 2013-07-26 18:56:30.000000000 +0000 ++++ linux-3.2.46/drivers/staging/media/lirc/lirc_serial.c 2013-07-26 19:17:30.000000000 +0000 +@@ -773,7 +773,7 @@ /* we fail, there's nothing here */ printk(KERN_ERR LIRC_DRIVER_NAME ": port existence test " "failed, cannot continue\n"); @@ -29,7 +29,7 @@ } -@@ -879,10 +879,9 @@ static int __devinit lirc_serial_probe(struct platform_device *dev) +@@ -876,10 +876,9 @@ goto exit_free_irq; } @@ -42,7 +42,7 @@ /* Initialize pulse/space widths */ init_timing_params(duty_cycle, freq); -@@ -980,7 +979,7 @@ static ssize_t lirc_write(struct file *file, const char *buf, +@@ -977,7 +976,7 @@ int *wbuf; if (!(hardware[type].features & LIRC_CAN_SEND_PULSE)) @@ -51,7 +51,7 @@ count = n / sizeof(int); if (n % sizeof(int) || count % 2 == 0) -@@ -1031,11 +1030,11 @@ static long lirc_ioctl(struct file *filep, unsigned int cmd, unsigned long arg) +@@ -1028,11 +1027,11 @@ return result; /* only LIRC_MODE_PULSE supported */ if (value != LIRC_MODE_PULSE) @@ -65,7 +65,7 @@ break; case LIRC_SET_SEND_DUTY_CYCLE: -@@ -1126,9 +1125,11 @@ static void lirc_serial_exit(void); +@@ -1123,9 +1122,11 @@ static int lirc_serial_resume(struct platform_device *dev) { unsigned long flags; @@ -79,7 +79,7 @@ spin_lock_irqsave(&hardware[type].lock, flags); /* Enable Interrupt */ -@@ -1161,7 +1162,7 @@ static int __init lirc_serial_init(void) +@@ -1158,7 +1159,7 @@ /* Init read buffer. */ result = lirc_buffer_init(&rbuf, sizeof(int), RBUF_LEN); if (result < 0) @@ -88,7 +88,7 @@ result = platform_driver_register(&lirc_serial_driver); if (result) { -@@ -1247,7 +1248,7 @@ static int __init lirc_serial_init_module(void) +@@ -1244,7 +1245,7 @@ printk(KERN_ERR LIRC_DRIVER_NAME ": register_chrdev failed!\n"); lirc_serial_exit(); @@ -97,6 +97,3 @@ } return 0; } --- -1.7.7.3 - diff -Nru linux-3.2.46/debian/patches/bugfix/all/apparmor-remove-advertising-the-support-of-network-r.patch linux-3.2.46/debian/patches/bugfix/all/apparmor-remove-advertising-the-support-of-network-r.patch --- linux-3.2.46/debian/patches/bugfix/all/apparmor-remove-advertising-the-support-of-network-r.patch 2013-04-11 03:27:32.000000000 +0000 +++ linux-3.2.46/debian/patches/bugfix/all/apparmor-remove-advertising-the-support-of-network-r.patch 2013-07-26 19:22:45.000000000 +0000 @@ -17,11 +17,11 @@ security/apparmor/apparmorfs-24.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -diff --git a/security/apparmor/apparmorfs-24.c b/security/apparmor/apparmorfs-24.c -index dc8c744..367c7ea 100644 ---- a/security/apparmor/apparmorfs-24.c -+++ b/security/apparmor/apparmorfs-24.c -@@ -49,7 +49,7 @@ const struct file_operations aa_fs_matching_fops = { +Index: linux-3.2.46/security/apparmor/apparmorfs-24.c +=================================================================== +--- linux-3.2.46.orig/security/apparmor/apparmorfs-24.c 2013-07-26 19:22:42.000000000 +0000 ++++ linux-3.2.46/security/apparmor/apparmorfs-24.c 2013-07-26 19:22:44.000000000 +0000 +@@ -49,7 +49,7 @@ static ssize_t aa_features_read(struct file *file, char __user *buf, size_t size, loff_t *ppos) { @@ -30,6 +30,3 @@ "change_hat=1.5 change_profile=1.1 " "aanamespaces=1.1 rlimit=1.1"; return simple_read_from_buffer(buf, size, ppos, features, --- -1.7.9.5 - diff -Nru linux-3.2.46/debian/patches/bugfix/all/ath9k-Disable-PowerSave-by-default.patch linux-3.2.46/debian/patches/bugfix/all/ath9k-Disable-PowerSave-by-default.patch --- linux-3.2.46/debian/patches/bugfix/all/ath9k-Disable-PowerSave-by-default.patch 2013-06-08 15:14:07.000000000 +0000 +++ linux-3.2.46/debian/patches/bugfix/all/ath9k-Disable-PowerSave-by-default.patch 2013-07-26 19:30:54.000000000 +0000 @@ -18,9 +18,11 @@ drivers/net/wireless/ath/ath9k/init.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) ---- a/drivers/net/wireless/ath/ath9k/init.c -+++ b/drivers/net/wireless/ath/ath9k/init.c -@@ -691,8 +691,7 @@ void ath9k_set_hw_capab(struct ath_softc +Index: linux-3.2.46/drivers/net/wireless/ath/ath9k/init.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/wireless/ath/ath9k/init.c 2013-07-26 18:52:13.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/ath/ath9k/init.c 2013-07-26 19:30:54.000000000 +0000 +@@ -691,8 +691,7 @@ BIT(NL80211_IFTYPE_ADHOC) | BIT(NL80211_IFTYPE_MESH_POINT); diff -Nru linux-3.2.46/debian/patches/bugfix/all/cifs-fix-potential-buffer-overrun-when-composing-a-new-options.patch linux-3.2.46/debian/patches/bugfix/all/cifs-fix-potential-buffer-overrun-when-composing-a-new-options.patch --- linux-3.2.46/debian/patches/bugfix/all/cifs-fix-potential-buffer-overrun-when-composing-a-new-options.patch 2013-06-08 17:42:27.000000000 +0000 +++ linux-3.2.46/debian/patches/bugfix/all/cifs-fix-potential-buffer-overrun-when-composing-a-new-options.patch 2013-07-26 19:31:19.000000000 +0000 @@ -17,8 +17,10 @@ fs/cifs/cifs_dfs_ref.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) ---- a/fs/cifs/cifs_dfs_ref.c -+++ b/fs/cifs/cifs_dfs_ref.c +Index: linux-3.2.46/fs/cifs/cifs_dfs_ref.c +=================================================================== +--- linux-3.2.46.orig/fs/cifs/cifs_dfs_ref.c 2013-07-26 18:52:05.000000000 +0000 ++++ linux-3.2.46/fs/cifs/cifs_dfs_ref.c 2013-07-26 19:31:18.000000000 +0000 @@ -18,6 +18,7 @@ #include #include @@ -27,7 +29,7 @@ #include "cifsglob.h" #include "cifsproto.h" #include "cifsfs.h" -@@ -150,7 +151,8 @@ char *cifs_compose_mount_options(const c +@@ -150,7 +151,8 @@ * assuming that we have 'unc=' and 'ip=' in * the original sb_mountdata */ diff -Nru linux-3.2.46/debian/patches/bugfix/all/dlm-Do-not-allocate-a-fd-for-peeloff.patch linux-3.2.46/debian/patches/bugfix/all/dlm-Do-not-allocate-a-fd-for-peeloff.patch --- linux-3.2.46/debian/patches/bugfix/all/dlm-Do-not-allocate-a-fd-for-peeloff.patch 2013-06-08 16:00:15.000000000 +0000 +++ linux-3.2.46/debian/patches/bugfix/all/dlm-Do-not-allocate-a-fd-for-peeloff.patch 2013-07-26 19:30:57.000000000 +0000 @@ -14,10 +14,10 @@ fs/dlm/lowcomms.c | 22 ++++++++-------------- 1 file changed, 8 insertions(+), 14 deletions(-) -diff --git a/fs/dlm/lowcomms.c b/fs/dlm/lowcomms.c -index 0b3109e..ca0c59a 100644 ---- a/fs/dlm/lowcomms.c -+++ b/fs/dlm/lowcomms.c +Index: linux-3.2.46/fs/dlm/lowcomms.c +=================================================================== +--- linux-3.2.46.orig/fs/dlm/lowcomms.c 2013-07-26 18:52:12.000000000 +0000 ++++ linux-3.2.46/fs/dlm/lowcomms.c 2013-07-26 19:30:56.000000000 +0000 @@ -52,6 +52,7 @@ #include #include @@ -26,7 +26,7 @@ #include #include -@@ -474,9 +475,6 @@ static void process_sctp_notification(struct connection *con, +@@ -474,9 +475,6 @@ int prim_len, ret; int addr_len; struct connection *new_con; @@ -36,7 +36,7 @@ /* * We get this before any data for an association. -@@ -525,23 +523,19 @@ static void process_sctp_notification(struct connection *con, +@@ -525,23 +523,19 @@ return; /* Peel off a new sock */ diff -Nru linux-3.2.46/debian/patches/bugfix/all/dm-Deal-with-merge_bvec_fn-in-component-devices-bett.patch linux-3.2.46/debian/patches/bugfix/all/dm-Deal-with-merge_bvec_fn-in-component-devices-bett.patch --- linux-3.2.46/debian/patches/bugfix/all/dm-Deal-with-merge_bvec_fn-in-component-devices-bett.patch 2013-02-24 03:52:24.000000000 +0000 +++ linux-3.2.46/debian/patches/bugfix/all/dm-Deal-with-merge_bvec_fn-in-component-devices-bett.patch 2013-07-26 19:17:19.000000000 +0000 @@ -22,9 +22,11 @@ Signed-off-by: Ben Hutchings --- ---- a/drivers/md/dm-table.c -+++ b/drivers/md/dm-table.c -@@ -536,13 +536,15 @@ int dm_set_device_limits(struct dm_target *ti, struct dm_dev *dev, +Index: linux-3.2.46/drivers/md/dm-table.c +=================================================================== +--- linux-3.2.46.orig/drivers/md/dm-table.c 2013-07-26 18:56:34.000000000 +0000 ++++ linux-3.2.46/drivers/md/dm-table.c 2013-07-26 19:17:18.000000000 +0000 +@@ -538,13 +538,15 @@ (unsigned long long) start << SECTOR_SHIFT); /* diff -Nru linux-3.2.46/debian/patches/bugfix/all/drm-nouveau-fix-init-with-agpgart-uninorth.patch linux-3.2.46/debian/patches/bugfix/all/drm-nouveau-fix-init-with-agpgart-uninorth.patch --- linux-3.2.46/debian/patches/bugfix/all/drm-nouveau-fix-init-with-agpgart-uninorth.patch 2013-02-24 03:52:24.000000000 +0000 +++ linux-3.2.46/debian/patches/bugfix/all/drm-nouveau-fix-init-with-agpgart-uninorth.patch 2013-07-26 19:27:26.000000000 +0000 @@ -25,9 +25,11 @@ drivers/gpu/drm/nouveau/nouveau_bo.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) ---- a/drivers/gpu/drm/nouveau/nouveau_bo.c -+++ b/drivers/gpu/drm/nouveau/nouveau_bo.c -@@ -940,7 +940,7 @@ nouveau_ttm_io_mem_reserve(struct ttm_bo +Index: linux-3.2.46/drivers/gpu/drm/nouveau/nouveau_bo.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/nouveau/nouveau_bo.c 2013-07-26 19:26:23.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/nouveau/nouveau_bo.c 2013-07-26 19:27:25.000000000 +0000 +@@ -946,7 +946,7 @@ if (dev_priv->gart_info.type == NOUVEAU_GART_AGP) { mem->bus.offset = mem->start << PAGE_SHIFT; mem->bus.base = dev_priv->gart_info.aper_base; diff -Nru linux-3.2.46/debian/patches/bugfix/all/drm-radeon-add-connector-table-for-Mac-G4-Silver.patch linux-3.2.46/debian/patches/bugfix/all/drm-radeon-add-connector-table-for-Mac-G4-Silver.patch --- linux-3.2.46/debian/patches/bugfix/all/drm-radeon-add-connector-table-for-Mac-G4-Silver.patch 2013-02-24 03:52:24.000000000 +0000 +++ linux-3.2.46/debian/patches/bugfix/all/drm-radeon-add-connector-table-for-Mac-G4-Silver.patch 2013-07-26 19:27:34.000000000 +0000 @@ -18,11 +18,11 @@ drivers/gpu/drm/radeon/radeon_mode.h | 3 +- 2 files changed, 53 insertions(+), 1 deletion(-) -diff --git a/drivers/gpu/drm/radeon/radeon_combios.c b/drivers/gpu/drm/radeon/radeon_combios.c -index 4af8912..33a56a0 100644 ---- a/drivers/gpu/drm/radeon/radeon_combios.c -+++ b/drivers/gpu/drm/radeon/radeon_combios.c -@@ -1548,6 +1548,9 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev) +Index: linux-3.2.46/drivers/gpu/drm/radeon/radeon_combios.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/radeon/radeon_combios.c 2013-07-26 19:27:32.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/radeon/radeon_combios.c 2013-07-26 19:27:33.000000000 +0000 +@@ -1545,6 +1545,9 @@ of_machine_is_compatible("PowerBook6,7")) { /* ibook */ rdev->mode_info.connector_table = CT_IBOOK; @@ -32,10 +32,12 @@ } else if (of_machine_is_compatible("PowerMac4,4")) { /* emac */ rdev->mode_info.connector_table = CT_EMAC; -@@ -2212,6 +2215,54 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev) +@@ -2207,6 +2210,54 @@ + DRM_MODE_CONNECTOR_SVIDEO, + &ddc_i2c, CONNECTOR_OBJECT_ID_SVIDEO, - &hpd); - break; ++ &hpd); ++ break; + case CT_MAC_G4_SILVER: + DRM_INFO("Connector Table: %d (mac g4 silver)\n", + rdev->mode_info.connector_table); @@ -82,16 +84,14 @@ + DRM_MODE_CONNECTOR_SVIDEO, + &ddc_i2c, + CONNECTOR_OBJECT_ID_SVIDEO, -+ &hpd); -+ break; + &hpd); + break; default: - DRM_INFO("Connector table: %d (invalid)\n", - rdev->mode_info.connector_table); -diff --git a/drivers/gpu/drm/radeon/radeon_mode.h b/drivers/gpu/drm/radeon/radeon_mode.h -index d818b50..ed8a0fa 100644 ---- a/drivers/gpu/drm/radeon/radeon_mode.h -+++ b/drivers/gpu/drm/radeon/radeon_mode.h -@@ -209,7 +209,8 @@ enum radeon_connector_table { +Index: linux-3.2.46/drivers/gpu/drm/radeon/radeon_mode.h +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/radeon/radeon_mode.h 2013-07-26 19:27:32.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/radeon/radeon_mode.h 2013-07-26 19:27:33.000000000 +0000 +@@ -210,7 +210,8 @@ CT_RN50_POWER, CT_MAC_X800, CT_MAC_G5_9600, diff -Nru linux-3.2.46/debian/patches/bugfix/all/drm-radeon-add-connector-table-for-SAM440ep-embedded.patch linux-3.2.46/debian/patches/bugfix/all/drm-radeon-add-connector-table-for-SAM440ep-embedded.patch --- linux-3.2.46/debian/patches/bugfix/all/drm-radeon-add-connector-table-for-SAM440ep-embedded.patch 2013-02-24 03:52:24.000000000 +0000 +++ linux-3.2.46/debian/patches/bugfix/all/drm-radeon-add-connector-table-for-SAM440ep-embedded.patch 2013-07-26 19:27:33.000000000 +0000 @@ -14,11 +14,11 @@ drivers/gpu/drm/radeon/radeon_mode.h | 1 + 2 files changed, 67 insertions(+) -diff --git a/drivers/gpu/drm/radeon/radeon_combios.c b/drivers/gpu/drm/radeon/radeon_combios.c -index 2cad9fd..576f4f6 100644 ---- a/drivers/gpu/drm/radeon/radeon_combios.c -+++ b/drivers/gpu/drm/radeon/radeon_combios.c -@@ -1561,6 +1561,11 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev) +Index: linux-3.2.46/drivers/gpu/drm/radeon/radeon_combios.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/radeon/radeon_combios.c 2013-07-26 19:26:24.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/radeon/radeon_combios.c 2013-07-26 19:27:32.000000000 +0000 +@@ -1570,6 +1570,11 @@ (rdev->pdev->subsystem_device == 0x4150)) { /* Mac G5 tower 9600 */ rdev->mode_info.connector_table = CT_MAC_G5_9600; @@ -30,10 +30,12 @@ } else #endif /* CONFIG_PPC_PMAC */ #ifdef CONFIG_PPC64 -@@ -2134,6 +2139,67 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev) +@@ -2141,6 +2146,67 @@ + DRM_MODE_CONNECTOR_SVIDEO, + &ddc_i2c, CONNECTOR_OBJECT_ID_SVIDEO, - &hpd); - break; ++ &hpd); ++ break; + case CT_SAM440EP: + DRM_INFO("Connector Table: %d (SAM440ep embedded board)\n", + rdev->mode_info.connector_table); @@ -93,16 +95,14 @@ + DRM_MODE_CONNECTOR_SVIDEO, + &ddc_i2c, + CONNECTOR_OBJECT_ID_SVIDEO, -+ &hpd); -+ break; + &hpd); + break; default: - DRM_INFO("Connector table: %d (invalid)\n", - rdev->mode_info.connector_table); -diff --git a/drivers/gpu/drm/radeon/radeon_mode.h b/drivers/gpu/drm/radeon/radeon_mode.h -index 0c3cdbd..499a5fe 100644 ---- a/drivers/gpu/drm/radeon/radeon_mode.h -+++ b/drivers/gpu/drm/radeon/radeon_mode.h -@@ -210,6 +210,7 @@ enum radeon_connector_table { +Index: linux-3.2.46/drivers/gpu/drm/radeon/radeon_mode.h +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/radeon/radeon_mode.h 2013-07-26 19:26:24.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/radeon/radeon_mode.h 2013-07-26 19:27:32.000000000 +0000 +@@ -210,6 +210,7 @@ CT_RN50_POWER, CT_MAC_X800, CT_MAC_G5_9600, diff -Nru linux-3.2.46/debian/patches/bugfix/all/drm-radeon-dce32-use-fractional-fb-dividers-for-high.patch linux-3.2.46/debian/patches/bugfix/all/drm-radeon-dce32-use-fractional-fb-dividers-for-high.patch --- linux-3.2.46/debian/patches/bugfix/all/drm-radeon-dce32-use-fractional-fb-dividers-for-high.patch 2013-02-24 03:52:24.000000000 +0000 +++ linux-3.2.46/debian/patches/bugfix/all/drm-radeon-dce32-use-fractional-fb-dividers-for-high.patch 2013-07-26 19:27:29.000000000 +0000 @@ -13,9 +13,11 @@ drivers/gpu/drm/radeon/atombios_crtc.c | 2 ++ 1 file changed, 2 insertions(+) ---- a/drivers/gpu/drm/radeon/atombios_crtc.c -+++ b/drivers/gpu/drm/radeon/atombios_crtc.c -@@ -577,6 +577,8 @@ static u32 atombios_adjust_pll(struct dr +Index: linux-3.2.46/drivers/gpu/drm/radeon/atombios_crtc.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/radeon/atombios_crtc.c 2013-07-26 19:26:23.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/radeon/atombios_crtc.c 2013-07-26 19:27:28.000000000 +0000 +@@ -573,6 +573,8 @@ /* use frac fb div on APUs */ if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)) pll->flags |= RADEON_PLL_USE_FRAC_FB_DIV; diff -Nru linux-3.2.46/debian/patches/bugfix/all/drm-radeon-fix-amd-afusion-gpu-setup-aka-sumo-v2.patch linux-3.2.46/debian/patches/bugfix/all/drm-radeon-fix-amd-afusion-gpu-setup-aka-sumo-v2.patch --- linux-3.2.46/debian/patches/bugfix/all/drm-radeon-fix-amd-afusion-gpu-setup-aka-sumo-v2.patch 2013-02-24 03:52:24.000000000 +0000 +++ linux-3.2.46/debian/patches/bugfix/all/drm-radeon-fix-amd-afusion-gpu-setup-aka-sumo-v2.patch 2013-07-26 19:27:30.000000000 +0000 @@ -22,9 +22,11 @@ drivers/gpu/drm/radeon/evergreend.h | 2 ++ 2 files changed, 6 insertions(+), 4 deletions(-) ---- a/drivers/gpu/drm/radeon/evergreen.c -+++ b/drivers/gpu/drm/radeon/evergreen.c -@@ -1730,7 +1730,7 @@ static void evergreen_gpu_init(struct ra +Index: linux-3.2.46/drivers/gpu/drm/radeon/evergreen.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/radeon/evergreen.c 2013-07-26 19:26:23.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/radeon/evergreen.c 2013-07-26 19:27:29.000000000 +0000 +@@ -1857,7 +1857,7 @@ case CHIP_SUMO: rdev->config.evergreen.num_ses = 1; rdev->config.evergreen.max_pipes = 4; @@ -33,7 +35,7 @@ if (rdev->pdev->device == 0x9648) rdev->config.evergreen.max_simds = 3; else if ((rdev->pdev->device == 0x9647) || -@@ -1819,7 +1819,7 @@ static void evergreen_gpu_init(struct ra +@@ -1946,7 +1946,7 @@ break; case CHIP_CAICOS: rdev->config.evergreen.num_ses = 1; diff -Nru linux-3.2.46/debian/patches/bugfix/all/ext3-return-32-64-bit-dir-name-hash-according-to-usa.patch linux-3.2.46/debian/patches/bugfix/all/ext3-return-32-64-bit-dir-name-hash-according-to-usa.patch --- linux-3.2.46/debian/patches/bugfix/all/ext3-return-32-64-bit-dir-name-hash-according-to-usa.patch 2013-06-08 16:47:39.000000000 +0000 +++ linux-3.2.46/debian/patches/bugfix/all/ext3-return-32-64-bit-dir-name-hash-according-to-usa.patch 2013-07-26 19:31:12.000000000 +0000 @@ -37,10 +37,10 @@ include/linux/ext3_fs.h | 6 +- 3 files changed, 129 insertions(+), 48 deletions(-) -diff --git a/fs/ext3/dir.c b/fs/ext3/dir.c -index 34f0a07..3268697 100644 ---- a/fs/ext3/dir.c -+++ b/fs/ext3/dir.c +Index: linux-3.2.46/fs/ext3/dir.c +=================================================================== +--- linux-3.2.46.orig/fs/ext3/dir.c 2013-07-26 18:52:07.000000000 +0000 ++++ linux-3.2.46/fs/ext3/dir.c 2013-07-26 19:31:11.000000000 +0000 @@ -25,6 +25,7 @@ #include #include @@ -49,7 +49,7 @@ #include #include -@@ -32,24 +33,8 @@ static unsigned char ext3_filetype_table[] = { +@@ -32,24 +33,8 @@ DT_UNKNOWN, DT_REG, DT_DIR, DT_CHR, DT_BLK, DT_FIFO, DT_SOCK, DT_LNK }; @@ -74,7 +74,7 @@ static unsigned char get_dtype(struct super_block *sb, int filetype) { -@@ -60,6 +45,25 @@ static unsigned char get_dtype(struct super_block *sb, int filetype) +@@ -60,6 +45,25 @@ return (ext3_filetype_table[filetype]); } @@ -100,7 +100,7 @@ int ext3_check_dir_entry (const char * function, struct inode * dir, struct ext3_dir_entry_2 * de, -@@ -99,18 +103,13 @@ static int ext3_readdir(struct file * filp, +@@ -99,18 +103,13 @@ unsigned long offset; int i, stored; struct ext3_dir_entry_2 *de; @@ -121,7 +121,7 @@ err = ext3_dx_readdir(filp, dirent, filldir); if (err != ERR_BAD_DX_DIR) { ret = err; -@@ -232,22 +231,87 @@ out: +@@ -232,22 +231,87 @@ return ret; } @@ -138,23 +138,12 @@ * These functions convert from the major/minor hash to an f_pos - * value. + * value for dx directories - * -- * Currently we only use major hash numer. This is unfortunate, but -- * on 32-bit machines, the same VFS interface is used for lseek and -- * llseek, so if we use the 64 bit offset, then the 32-bit versions of -- * lseek/telldir/seekdir will blow out spectacularly, and from within -- * the ext2 low-level routine, we don't know if we're being called by -- * a 64-bit version of the system call or the 32-bit version of the -- * system call. Worse yet, NFSv2 only allows for a 32-bit readdir -- * cookie. Sigh. ++ * + * Upper layer (for example NFS) should specify FMODE_32BITHASH or + * FMODE_64BITHASH explicitly. On the other hand, we allow ext3 to be mounted + * directly on both 32-bit and 64-bit nodes, under such case, neither + * FMODE_32BITHASH nor FMODE_64BITHASH is specified. - */ --#define hash2pos(major, minor) (major >> 1) --#define pos2maj_hash(pos) ((pos << 1) & 0xffffffff) --#define pos2min_hash(pos) (0) ++ */ +static inline loff_t hash2pos(struct file *filp, __u32 major, __u32 minor) +{ + if ((filp->f_mode & FMODE_32BITHASH) || @@ -199,14 +188,25 @@ + * ext3_dir_llseek() calls generic_file_llseek[_size]() to handle both + * non-htree and htree directories, where the "offset" is in terms + * of the filename hash value instead of the byte offset. -+ * + * +- * Currently we only use major hash numer. This is unfortunate, but +- * on 32-bit machines, the same VFS interface is used for lseek and +- * llseek, so if we use the 64 bit offset, then the 32-bit versions of +- * lseek/telldir/seekdir will blow out spectacularly, and from within +- * the ext2 low-level routine, we don't know if we're being called by +- * a 64-bit version of the system call or the 32-bit version of the +- * system call. Worse yet, NFSv2 only allows for a 32-bit readdir +- * cookie. Sigh. + * Because we may return a 64-bit hash that is well beyond s_maxbytes, + * we need to pass the max hash as the maximum allowable offset in + * the htree directory case. + * + * NOTE: offsets obtained *before* ext3_set_inode_flag(dir, EXT3_INODE_INDEX) + * will be invalid once the directory was converted into a dx directory -+ */ + */ +-#define hash2pos(major, minor) (major >> 1) +-#define pos2maj_hash(pos) ((pos << 1) & 0xffffffff) +-#define pos2min_hash(pos) (0) +loff_t ext3_dir_llseek(struct file *file, loff_t offset, int origin) +{ + struct inode *inode = file->f_mapping->host; @@ -221,7 +221,7 @@ /* * This structure holds the nodes of the red-black tree used to store -@@ -308,15 +372,16 @@ static void free_rb_tree_fname(struct rb_root *root) +@@ -308,15 +372,16 @@ } @@ -241,7 +241,7 @@ return p; } -@@ -406,7 +471,7 @@ static int call_filldir(struct file * filp, void * dirent, +@@ -406,7 +471,7 @@ printk("call_filldir: called with null fname?!?\n"); return 0; } @@ -250,7 +250,7 @@ while (fname) { error = filldir(dirent, fname->name, fname->name_len, curr_pos, -@@ -431,13 +496,13 @@ static int ext3_dx_readdir(struct file * filp, +@@ -431,13 +496,13 @@ int ret; if (!info) { @@ -266,7 +266,7 @@ return 0; /* EOF */ /* Some one has messed with f_pos; reset the world */ -@@ -445,8 +510,8 @@ static int ext3_dx_readdir(struct file * filp, +@@ -445,8 +510,8 @@ free_rb_tree_fname(&info->root); info->curr_node = NULL; info->extra_fname = NULL; @@ -277,7 +277,7 @@ } /* -@@ -478,7 +543,7 @@ static int ext3_dx_readdir(struct file * filp, +@@ -478,7 +543,7 @@ if (ret < 0) return ret; if (ret == 0) { @@ -286,7 +286,7 @@ break; } info->curr_node = rb_first(&info->root); -@@ -498,7 +563,7 @@ static int ext3_dx_readdir(struct file * filp, +@@ -498,7 +563,7 @@ info->curr_minor_hash = fname->minor_hash; } else { if (info->next_hash == ~0) { @@ -295,7 +295,7 @@ break; } info->curr_hash = info->next_hash; -@@ -517,3 +582,15 @@ static int ext3_release_dir (struct inode * inode, struct file * filp) +@@ -517,3 +582,15 @@ return 0; } @@ -311,11 +311,11 @@ + .fsync = ext3_sync_file, + .release = ext3_release_dir, +}; -diff --git a/fs/ext3/hash.c b/fs/ext3/hash.c -index 7d215b4..d4d3ade 100644 ---- a/fs/ext3/hash.c -+++ b/fs/ext3/hash.c -@@ -200,8 +200,8 @@ int ext3fs_dirhash(const char *name, int len, struct dx_hash_info *hinfo) +Index: linux-3.2.46/fs/ext3/hash.c +=================================================================== +--- linux-3.2.46.orig/fs/ext3/hash.c 2013-07-26 18:52:07.000000000 +0000 ++++ linux-3.2.46/fs/ext3/hash.c 2013-07-26 19:31:11.000000000 +0000 +@@ -200,8 +200,8 @@ return -1; } hash = hash & ~1; @@ -326,11 +326,11 @@ hinfo->hash = hash; hinfo->minor_hash = minor_hash; return 0; -diff --git a/include/linux/ext3_fs.h b/include/linux/ext3_fs.h -index dec9911..d59ab12 100644 ---- a/include/linux/ext3_fs.h -+++ b/include/linux/ext3_fs.h -@@ -781,7 +781,11 @@ struct dx_hash_info +Index: linux-3.2.46/include/linux/ext3_fs.h +=================================================================== +--- linux-3.2.46.orig/include/linux/ext3_fs.h 2013-07-26 18:52:07.000000000 +0000 ++++ linux-3.2.46/include/linux/ext3_fs.h 2013-07-26 19:31:11.000000000 +0000 +@@ -781,7 +781,11 @@ u32 *seed; }; @@ -343,6 +343,3 @@ /* * Control parameters used by ext3_htree_next_block --- -1.7.10.4 - diff -Nru linux-3.2.46/debian/patches/bugfix/all/ext4-avoid-hang-when-mounting-non-journal-filesystem.patch linux-3.2.46/debian/patches/bugfix/all/ext4-avoid-hang-when-mounting-non-journal-filesystem.patch --- linux-3.2.46/debian/patches/bugfix/all/ext4-avoid-hang-when-mounting-non-journal-filesystem.patch 2013-06-05 01:28:28.000000000 +0000 +++ linux-3.2.46/debian/patches/bugfix/all/ext4-avoid-hang-when-mounting-non-journal-filesystem.patch 2013-07-26 19:30:50.000000000 +0000 @@ -27,11 +27,11 @@ fs/ext4/namei.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) -diff --git a/fs/ext4/namei.c b/fs/ext4/namei.c -index cac4482..8990165 100644 ---- a/fs/ext4/namei.c -+++ b/fs/ext4/namei.c -@@ -2648,7 +2648,8 @@ int ext4_orphan_del(handle_t *handle, struct inode *inode) +Index: linux-3.2.46/fs/ext4/namei.c +=================================================================== +--- linux-3.2.46.orig/fs/ext4/namei.c 2013-07-26 19:30:48.000000000 +0000 ++++ linux-3.2.46/fs/ext4/namei.c 2013-07-26 19:30:49.000000000 +0000 +@@ -2056,7 +2056,8 @@ struct ext4_iloc iloc; int err = 0; @@ -41,6 +41,3 @@ return 0; mutex_lock(&EXT4_SB(inode->i_sb)->s_orphan_lock); --- -1.7.10.4 - diff -Nru linux-3.2.46/debian/patches/bugfix/all/ext4-make-orphan-functions-be-no-op-in-no-journal-mo.patch linux-3.2.46/debian/patches/bugfix/all/ext4-make-orphan-functions-be-no-op-in-no-journal-mo.patch --- linux-3.2.46/debian/patches/bugfix/all/ext4-make-orphan-functions-be-no-op-in-no-journal-mo.patch 2013-06-05 01:28:28.000000000 +0000 +++ linux-3.2.46/debian/patches/bugfix/all/ext4-make-orphan-functions-be-no-op-in-no-journal-mo.patch 2013-07-26 19:30:49.000000000 +0000 @@ -14,11 +14,11 @@ fs/ext4/namei.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) -diff --git a/fs/ext4/namei.c b/fs/ext4/namei.c -index 37c03b3..8f4bda7 100644 ---- a/fs/ext4/namei.c -+++ b/fs/ext4/namei.c -@@ -2369,7 +2369,7 @@ int ext4_orphan_add(handle_t *handle, struct inode *inode) +Index: linux-3.2.46/fs/ext4/namei.c +=================================================================== +--- linux-3.2.46.orig/fs/ext4/namei.c 2013-07-26 18:52:15.000000000 +0000 ++++ linux-3.2.46/fs/ext4/namei.c 2013-07-26 19:30:48.000000000 +0000 +@@ -1982,7 +1982,7 @@ struct ext4_iloc iloc; int err = 0, rc; @@ -27,7 +27,7 @@ return 0; mutex_lock(&EXT4_SB(sb)->s_orphan_lock); -@@ -2443,8 +2443,7 @@ int ext4_orphan_del(handle_t *handle, struct inode *inode) +@@ -2056,8 +2056,7 @@ struct ext4_iloc iloc; int err = 0; @@ -37,7 +37,7 @@ return 0; mutex_lock(&EXT4_SB(inode->i_sb)->s_orphan_lock); -@@ -2463,7 +2462,7 @@ int ext4_orphan_del(handle_t *handle, struct inode *inode) +@@ -2076,7 +2075,7 @@ * transaction handle with which to update the orphan list on * disk, but we still need to remove the inode from the linked * list in memory. */ @@ -46,5 +46,3 @@ goto out; err = ext4_reserve_inode_write(handle, inode, &iloc); --- -1.7.10.4 diff -Nru linux-3.2.46/debian/patches/bugfix/all/ext4-return-32-64-bit-dir-name-hash-according-to-usa.patch linux-3.2.46/debian/patches/bugfix/all/ext4-return-32-64-bit-dir-name-hash-according-to-usa.patch --- linux-3.2.46/debian/patches/bugfix/all/ext4-return-32-64-bit-dir-name-hash-according-to-usa.patch 2013-06-08 16:47:39.000000000 +0000 +++ linux-3.2.46/debian/patches/bugfix/all/ext4-return-32-64-bit-dir-name-hash-according-to-usa.patch 2013-07-26 19:31:08.000000000 +0000 @@ -28,11 +28,11 @@ fs/ext4/hash.c | 4 +- 3 files changed, 176 insertions(+), 48 deletions(-) -diff --git a/fs/ext4/dir.c b/fs/ext4/dir.c -index 164c560..689d1b1 100644 ---- a/fs/ext4/dir.c -+++ b/fs/ext4/dir.c -@@ -32,24 +32,8 @@ static unsigned char ext4_filetype_table[] = { +Index: linux-3.2.46/fs/ext4/dir.c +=================================================================== +--- linux-3.2.46.orig/fs/ext4/dir.c 2013-07-26 18:52:09.000000000 +0000 ++++ linux-3.2.46/fs/ext4/dir.c 2013-07-26 19:31:07.000000000 +0000 +@@ -32,24 +32,8 @@ DT_UNKNOWN, DT_REG, DT_DIR, DT_CHR, DT_BLK, DT_FIFO, DT_SOCK, DT_LNK }; @@ -57,7 +57,7 @@ static unsigned char get_dtype(struct super_block *sb, int filetype) { -@@ -60,6 +44,26 @@ static unsigned char get_dtype(struct super_block *sb, int filetype) +@@ -60,6 +44,26 @@ return (ext4_filetype_table[filetype]); } @@ -84,7 +84,7 @@ /* * Return 0 if the directory entry is OK, and 1 if there is a problem * -@@ -115,18 +119,13 @@ static int ext4_readdir(struct file *filp, +@@ -115,18 +119,13 @@ unsigned int offset; int i, stored; struct ext4_dir_entry_2 *de; @@ -105,7 +105,7 @@ err = ext4_dx_readdir(filp, dirent, filldir); if (err != ERR_BAD_DX_DIR) { ret = err; -@@ -254,22 +253,134 @@ out: +@@ -254,22 +253,134 @@ return ret; } @@ -252,7 +252,7 @@ /* * This structure holds the nodes of the red-black tree used to store -@@ -330,15 +441,16 @@ static void free_rb_tree_fname(struct rb_root *root) +@@ -330,15 +441,16 @@ } @@ -272,7 +272,7 @@ return p; } -@@ -429,7 +541,7 @@ static int call_filldir(struct file *filp, void *dirent, +@@ -429,7 +541,7 @@ "null fname?!?\n"); return 0; } @@ -281,7 +281,7 @@ while (fname) { error = filldir(dirent, fname->name, fname->name_len, curr_pos, -@@ -454,13 +566,13 @@ static int ext4_dx_readdir(struct file *filp, +@@ -454,13 +566,13 @@ int ret; if (!info) { @@ -297,7 +297,7 @@ return 0; /* EOF */ /* Some one has messed with f_pos; reset the world */ -@@ -468,8 +580,8 @@ static int ext4_dx_readdir(struct file *filp, +@@ -468,8 +580,8 @@ free_rb_tree_fname(&info->root); info->curr_node = NULL; info->extra_fname = NULL; @@ -308,7 +308,7 @@ } /* -@@ -501,7 +613,7 @@ static int ext4_dx_readdir(struct file *filp, +@@ -501,7 +613,7 @@ if (ret < 0) return ret; if (ret == 0) { @@ -317,7 +317,7 @@ break; } info->curr_node = rb_first(&info->root); -@@ -521,7 +633,7 @@ static int ext4_dx_readdir(struct file *filp, +@@ -521,7 +633,7 @@ info->curr_minor_hash = fname->minor_hash; } else { if (info->next_hash == ~0) { @@ -326,7 +326,7 @@ break; } info->curr_hash = info->next_hash; -@@ -540,3 +652,15 @@ static int ext4_release_dir(struct inode *inode, struct file *filp) +@@ -540,3 +652,15 @@ return 0; } @@ -342,11 +342,11 @@ + .fsync = ext4_sync_file, + .release = ext4_release_dir, +}; -diff --git a/fs/ext4/ext4.h b/fs/ext4/ext4.h -index 8cb184c..2ac1eef 100644 ---- a/fs/ext4/ext4.h -+++ b/fs/ext4/ext4.h -@@ -1597,7 +1597,11 @@ struct dx_hash_info +Index: linux-3.2.46/fs/ext4/ext4.h +=================================================================== +--- linux-3.2.46.orig/fs/ext4/ext4.h 2013-07-26 18:52:09.000000000 +0000 ++++ linux-3.2.46/fs/ext4/ext4.h 2013-07-26 19:31:07.000000000 +0000 +@@ -1597,7 +1597,11 @@ u32 *seed; }; @@ -359,11 +359,11 @@ /* * Control parameters used by ext4_htree_next_block -diff --git a/fs/ext4/hash.c b/fs/ext4/hash.c -index ac8f168..fa8e491 100644 ---- a/fs/ext4/hash.c -+++ b/fs/ext4/hash.c -@@ -200,8 +200,8 @@ int ext4fs_dirhash(const char *name, int len, struct dx_hash_info *hinfo) +Index: linux-3.2.46/fs/ext4/hash.c +=================================================================== +--- linux-3.2.46.orig/fs/ext4/hash.c 2013-07-26 18:52:09.000000000 +0000 ++++ linux-3.2.46/fs/ext4/hash.c 2013-07-26 19:31:07.000000000 +0000 +@@ -200,8 +200,8 @@ return -1; } hash = hash & ~1; @@ -374,6 +374,3 @@ hinfo->hash = hash; hinfo->minor_hash = minor_hash; return 0; --- -1.7.10.4 - diff -Nru linux-3.2.46/debian/patches/bugfix/all/firmware_class-log-every-success-and-failure.patch linux-3.2.46/debian/patches/bugfix/all/firmware_class-log-every-success-and-failure.patch --- linux-3.2.46/debian/patches/bugfix/all/firmware_class-log-every-success-and-failure.patch 2013-02-24 03:52:24.000000000 +0000 +++ linux-3.2.46/debian/patches/bugfix/all/firmware_class-log-every-success-and-failure.patch 2013-07-26 19:25:20.000000000 +0000 @@ -17,9 +17,11 @@ This makes many error messages in drivers redundant, which will be removed in later patches. ---- a/drivers/base/firmware_class.c -+++ b/drivers/base/firmware_class.c -@@ -251,7 +251,8 @@ static ssize_t firmware_loading_store(st +Index: linux-3.2.46/drivers/base/firmware_class.c +=================================================================== +--- linux-3.2.46.orig/drivers/base/firmware_class.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/base/firmware_class.c 2013-07-26 19:25:19.000000000 +0000 +@@ -251,7 +251,8 @@ fw_priv->nr_pages, 0, PAGE_KERNEL_RO); if (!fw_priv->fw->data) { @@ -29,7 +31,7 @@ goto err; } /* Pages are now owned by 'struct firmware' */ -@@ -266,9 +267,14 @@ static ssize_t firmware_loading_store(st +@@ -266,9 +267,14 @@ } /* fallthrough */ default: @@ -46,7 +48,7 @@ err: fw_load_abort(fw_priv); break; -@@ -431,6 +437,9 @@ static void firmware_class_timeout(u_lon +@@ -431,6 +437,9 @@ { struct firmware_priv *fw_priv = (struct firmware_priv *) data; @@ -56,7 +58,7 @@ fw_load_abort(fw_priv); } -@@ -530,7 +539,8 @@ static int _request_firmware(const struc +@@ -530,7 +539,8 @@ } if (fw_get_builtin_firmware(firmware, name)) { @@ -66,7 +68,7 @@ return 0; } -@@ -564,8 +574,15 @@ static int _request_firmware(const struc +@@ -564,8 +574,15 @@ del_timer_sync(&fw_priv->timeout); mutex_lock(&fw_lock); @@ -83,7 +85,7 @@ fw_priv->fw = NULL; mutex_unlock(&fw_lock); -@@ -575,6 +592,9 @@ out: +@@ -575,6 +592,9 @@ if (retval) { release_firmware(firmware); *firmware_p = NULL; diff -Nru linux-3.2.46/debian/patches/bugfix/all/firmware-remove-redundant-log-messages-from-drivers.patch linux-3.2.46/debian/patches/bugfix/all/firmware-remove-redundant-log-messages-from-drivers.patch --- linux-3.2.46/debian/patches/bugfix/all/firmware-remove-redundant-log-messages-from-drivers.patch 2013-02-24 03:52:24.000000000 +0000 +++ linux-3.2.46/debian/patches/bugfix/all/firmware-remove-redundant-log-messages-from-drivers.patch 2013-07-26 19:25:40.000000000 +0000 @@ -8,9 +8,11 @@ This will probably need to be split up into multiple patches prior to upstream submission. ---- a/arch/arm/mach-netx/xc.c -+++ b/arch/arm/mach-netx/xc.c -@@ -127,10 +127,8 @@ int xc_request_firmware(struct xc *x) +Index: linux-3.2.46/arch/arm/mach-netx/xc.c +=================================================================== +--- linux-3.2.46.orig/arch/arm/mach-netx/xc.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/arch/arm/mach-netx/xc.c 2013-07-26 19:25:21.000000000 +0000 +@@ -127,10 +127,8 @@ ret = request_firmware(&fw, name, x->dev); @@ -22,9 +24,11 @@ head = (struct fw_header *)fw->data; if (head->magic != 0x4e657458) { ---- a/arch/cris/arch-v32/drivers/iop_fw_load.c -+++ b/arch/cris/arch-v32/drivers/iop_fw_load.c -@@ -74,12 +74,7 @@ int iop_fw_load_spu(const unsigned char +Index: linux-3.2.46/arch/cris/arch-v32/drivers/iop_fw_load.c +=================================================================== +--- linux-3.2.46.orig/arch/cris/arch-v32/drivers/iop_fw_load.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/arch/cris/arch-v32/drivers/iop_fw_load.c 2013-07-26 19:25:21.000000000 +0000 +@@ -74,12 +74,7 @@ fw_name, &iop_spu_device[spu_inst]); if (retval != 0) @@ -37,7 +41,7 @@ data = (u32 *) fw_entry->data; /* acquire ownership of memory controller */ -@@ -137,12 +132,7 @@ int iop_fw_load_mpu(unsigned char *fw_na +@@ -137,12 +132,7 @@ /* get firmware */ retval = request_firmware(&fw_entry, fw_name, &iop_mpu_device); if (retval != 0) @@ -50,9 +54,11 @@ data = (u32 *) fw_entry->data; /* disable MPU */ ---- a/arch/x86/kernel/microcode_amd.c -+++ b/arch/x86/kernel/microcode_amd.c -@@ -330,10 +330,8 @@ static enum ucode_state request_microcod +Index: linux-3.2.46/arch/x86/kernel/microcode_amd.c +=================================================================== +--- linux-3.2.46.orig/arch/x86/kernel/microcode_amd.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/arch/x86/kernel/microcode_amd.c 2013-07-26 19:25:21.000000000 +0000 +@@ -330,10 +330,8 @@ if (c->x86 >= 0x15) snprintf(fw_name, sizeof(fw_name), "amd-ucode/microcode_amd_fam%.2xh.bin", c->x86); @@ -64,9 +70,11 @@ ret = UCODE_ERROR; if (*(u32 *)fw->data != UCODE_MAGIC) { ---- a/drivers/atm/ambassador.c -+++ b/drivers/atm/ambassador.c -@@ -1926,10 +1926,8 @@ static int __devinit ucode_init (loader_ +Index: linux-3.2.46/drivers/atm/ambassador.c +=================================================================== +--- linux-3.2.46.orig/drivers/atm/ambassador.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/atm/ambassador.c 2013-07-26 19:25:21.000000000 +0000 +@@ -1926,10 +1926,8 @@ int res; res = request_ihex_firmware(&fw, "atmsar11.fw", &dev->pci_dev->dev); @@ -78,9 +86,11 @@ /* First record contains just the start address */ rec = (const struct ihex_binrec *)fw->data; ---- a/drivers/atm/fore200e.c -+++ b/drivers/atm/fore200e.c -@@ -2519,10 +2519,9 @@ fore200e_load_and_start_fw(struct fore20 +Index: linux-3.2.46/drivers/atm/fore200e.c +=================================================================== +--- linux-3.2.46.orig/drivers/atm/fore200e.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/atm/fore200e.c 2013-07-26 19:25:21.000000000 +0000 +@@ -2519,10 +2519,9 @@ return err; sprintf(buf, "%s%s", fore200e->bus->proc_name, FW_EXT); @@ -93,9 +103,11 @@ fw_data = (__le32 *) firmware->data; fw_size = firmware->size / sizeof(u32); ---- a/drivers/bluetooth/ath3k.c -+++ b/drivers/bluetooth/ath3k.c -@@ -305,10 +305,8 @@ static int ath3k_load_patch(struct usb_d +Index: linux-3.2.46/drivers/bluetooth/ath3k.c +=================================================================== +--- linux-3.2.46.orig/drivers/bluetooth/ath3k.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/bluetooth/ath3k.c 2013-07-26 19:25:21.000000000 +0000 +@@ -324,10 +324,8 @@ fw_version.rom_version); ret = request_firmware(&firmware, filename, &udev->dev); @@ -107,7 +119,7 @@ pt_version.rom_version = *(int *)(firmware->data + firmware->size - 8); pt_version.build_version = *(int *) -@@ -367,10 +365,8 @@ static int ath3k_load_syscfg(struct usb_ +@@ -386,10 +384,8 @@ fw_version.rom_version, clk_value, ".dfu"); ret = request_firmware(&firmware, filename, &udev->dev); @@ -119,9 +131,11 @@ ret = ath3k_load_fwfile(udev, firmware); release_firmware(firmware); ---- a/drivers/bluetooth/bcm203x.c -+++ b/drivers/bluetooth/bcm203x.c -@@ -194,7 +194,6 @@ static int bcm203x_probe(struct usb_inte +Index: linux-3.2.46/drivers/bluetooth/bcm203x.c +=================================================================== +--- linux-3.2.46.orig/drivers/bluetooth/bcm203x.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/bluetooth/bcm203x.c 2013-07-26 19:25:21.000000000 +0000 +@@ -194,7 +194,6 @@ } if (request_firmware(&firmware, "BCM2033-MD.hex", &udev->dev) < 0) { @@ -129,7 +143,7 @@ usb_free_urb(data->urb); kfree(data); return -EIO; -@@ -221,7 +220,6 @@ static int bcm203x_probe(struct usb_inte +@@ -221,7 +220,6 @@ release_firmware(firmware); if (request_firmware(&firmware, "BCM2033-FW.bin", &udev->dev) < 0) { @@ -137,9 +151,11 @@ usb_free_urb(data->urb); kfree(data->buffer); kfree(data); ---- a/drivers/bluetooth/bfusb.c -+++ b/drivers/bluetooth/bfusb.c -@@ -681,10 +681,8 @@ static int bfusb_probe(struct usb_interf +Index: linux-3.2.46/drivers/bluetooth/bfusb.c +=================================================================== +--- linux-3.2.46.orig/drivers/bluetooth/bfusb.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/bluetooth/bfusb.c 2013-07-26 19:25:21.000000000 +0000 +@@ -681,10 +681,8 @@ skb_queue_head_init(&data->pending_q); skb_queue_head_init(&data->completed_q); @@ -151,9 +167,11 @@ BT_DBG("firmware data %p size %zu", firmware->data, firmware->size); ---- a/drivers/bluetooth/bt3c_cs.c -+++ b/drivers/bluetooth/bt3c_cs.c -@@ -594,10 +594,8 @@ static int bt3c_open(bt3c_info_t *info) +Index: linux-3.2.46/drivers/bluetooth/bt3c_cs.c +=================================================================== +--- linux-3.2.46.orig/drivers/bluetooth/bt3c_cs.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/bluetooth/bt3c_cs.c 2013-07-26 19:25:21.000000000 +0000 +@@ -594,10 +594,8 @@ /* Load firmware */ err = request_firmware(&firmware, "BT3CPCC.bin", &info->p_dev->dev); @@ -165,9 +183,11 @@ err = bt3c_load_firmware(info, firmware->data, firmware->size); ---- a/drivers/bluetooth/btmrvl_sdio.c -+++ b/drivers/bluetooth/btmrvl_sdio.c -@@ -258,8 +258,6 @@ static int btmrvl_sdio_download_helper(s +Index: linux-3.2.46/drivers/bluetooth/btmrvl_sdio.c +=================================================================== +--- linux-3.2.46.orig/drivers/bluetooth/btmrvl_sdio.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/bluetooth/btmrvl_sdio.c 2013-07-26 19:25:21.000000000 +0000 +@@ -258,8 +258,6 @@ ret = request_firmware(&fw_helper, card->helper, &card->func->dev); if ((ret < 0) || !fw_helper) { @@ -176,7 +196,7 @@ ret = -ENOENT; goto done; } -@@ -360,8 +358,6 @@ static int btmrvl_sdio_download_fw_w_hel +@@ -360,8 +358,6 @@ ret = request_firmware(&fw_firmware, card->firmware, &card->func->dev); if ((ret < 0) || !fw_firmware) { @@ -185,9 +205,11 @@ ret = -ENOENT; goto done; } ---- a/drivers/char/dsp56k.c -+++ b/drivers/char/dsp56k.c -@@ -140,11 +140,8 @@ static int dsp56k_upload(u_char __user * +Index: linux-3.2.46/drivers/char/dsp56k.c +=================================================================== +--- linux-3.2.46.orig/drivers/char/dsp56k.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/char/dsp56k.c 2013-07-26 19:25:21.000000000 +0000 +@@ -140,11 +140,8 @@ } err = request_firmware(&fw, fw_name, &pdev->dev); platform_device_unregister(pdev); @@ -200,9 +222,11 @@ if (fw->size % 3) { printk(KERN_ERR "Bogus length %d in image \"%s\"\n", fw->size, fw_name); ---- a/drivers/dma/imx-sdma.c -+++ b/drivers/dma/imx-sdma.c -@@ -1152,10 +1152,8 @@ static void sdma_load_firmware(const str +Index: linux-3.2.46/drivers/dma/imx-sdma.c +=================================================================== +--- linux-3.2.46.orig/drivers/dma/imx-sdma.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/dma/imx-sdma.c 2013-07-26 19:25:21.000000000 +0000 +@@ -1152,10 +1152,8 @@ const struct sdma_script_start_addrs *addr; unsigned short *ram_code; @@ -214,9 +238,11 @@ if (fw->size < sizeof(*header)) goto err_firmware; ---- a/drivers/gpu/drm/mga/mga_warp.c -+++ b/drivers/gpu/drm/mga/mga_warp.c -@@ -80,11 +80,8 @@ int mga_warp_install_microcode(drm_mga_p +Index: linux-3.2.46/drivers/gpu/drm/mga/mga_warp.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/mga/mga_warp.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/mga/mga_warp.c 2013-07-26 19:25:21.000000000 +0000 +@@ -80,11 +80,8 @@ } rc = request_ihex_firmware(&fw, firmware_name, &pdev->dev); platform_device_unregister(pdev); @@ -229,9 +255,11 @@ size = 0; where = 0; ---- a/drivers/gpu/drm/nouveau/nvc0_graph.c -+++ b/drivers/gpu/drm/nouveau/nvc0_graph.c -@@ -732,10 +732,8 @@ nvc0_graph_create_fw(struct drm_device * +Index: linux-3.2.46/drivers/gpu/drm/nouveau/nvc0_graph.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/nouveau/nvc0_graph.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/nouveau/nvc0_graph.c 2013-07-26 19:25:21.000000000 +0000 +@@ -740,10 +740,8 @@ if (ret) { snprintf(f, sizeof(f), "nouveau/%s", fwname); ret = request_firmware(&fw, f, &dev->pdev->dev); @@ -243,9 +271,11 @@ } fuc->size = fw->size; ---- a/drivers/gpu/drm/r128/r128_cce.c -+++ b/drivers/gpu/drm/r128/r128_cce.c -@@ -155,11 +155,8 @@ static int r128_cce_load_microcode(drm_r +Index: linux-3.2.46/drivers/gpu/drm/r128/r128_cce.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/r128/r128_cce.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/r128/r128_cce.c 2013-07-26 19:25:21.000000000 +0000 +@@ -155,11 +155,8 @@ } rc = request_firmware(&fw, FIRMWARE_NAME, &pdev->dev); platform_device_unregister(pdev); @@ -258,9 +288,11 @@ if (fw->size != 256 * 8) { printk(KERN_ERR ---- a/drivers/gpu/drm/radeon/ni.c -+++ b/drivers/gpu/drm/radeon/ni.c -@@ -379,10 +379,6 @@ out: +Index: linux-3.2.46/drivers/gpu/drm/radeon/ni.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/radeon/ni.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/radeon/ni.c 2013-07-26 19:25:21.000000000 +0000 +@@ -379,10 +379,6 @@ platform_device_unregister(pdev); if (err) { @@ -271,9 +303,11 @@ release_firmware(rdev->pfp_fw); rdev->pfp_fw = NULL; release_firmware(rdev->me_fw); ---- a/drivers/gpu/drm/radeon/r100.c -+++ b/drivers/gpu/drm/radeon/r100.c -@@ -994,10 +994,7 @@ static int r100_cp_init_microcode(struct +Index: linux-3.2.46/drivers/gpu/drm/radeon/r100.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/radeon/r100.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/radeon/r100.c 2013-07-26 19:25:21.000000000 +0000 +@@ -994,10 +994,7 @@ err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev); platform_device_unregister(pdev); @@ -285,9 +319,11 @@ printk(KERN_ERR "radeon_cp: Bogus length %zu in firmware \"%s\"\n", rdev->me_fw->size, fw_name); ---- a/drivers/gpu/drm/radeon/r600.c -+++ b/drivers/gpu/drm/radeon/r600.c -@@ -2087,10 +2087,6 @@ out: +Index: linux-3.2.46/drivers/gpu/drm/radeon/r600.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/radeon/r600.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/radeon/r600.c 2013-07-26 19:25:21.000000000 +0000 +@@ -2087,10 +2087,6 @@ platform_device_unregister(pdev); if (err) { @@ -298,9 +334,11 @@ release_firmware(rdev->pfp_fw); rdev->pfp_fw = NULL; release_firmware(rdev->me_fw); ---- a/drivers/gpu/drm/radeon/r600_cp.c -+++ b/drivers/gpu/drm/radeon/r600_cp.c -@@ -375,10 +375,6 @@ out: +Index: linux-3.2.46/drivers/gpu/drm/radeon/r600_cp.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/radeon/r600_cp.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/radeon/r600_cp.c 2013-07-26 19:25:21.000000000 +0000 +@@ -375,10 +375,6 @@ platform_device_unregister(pdev); if (err) { @@ -311,9 +349,11 @@ release_firmware(dev_priv->pfp_fw); dev_priv->pfp_fw = NULL; release_firmware(dev_priv->me_fw); ---- a/drivers/gpu/drm/radeon/radeon_cp.c -+++ b/drivers/gpu/drm/radeon/radeon_cp.c -@@ -544,10 +544,7 @@ static int radeon_cp_init_microcode(drm_ +Index: linux-3.2.46/drivers/gpu/drm/radeon/radeon_cp.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/radeon/radeon_cp.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/radeon/radeon_cp.c 2013-07-26 19:25:21.000000000 +0000 +@@ -544,10 +544,7 @@ err = request_firmware(&dev_priv->me_fw, fw_name, &pdev->dev); platform_device_unregister(pdev); @@ -325,9 +365,11 @@ printk(KERN_ERR "radeon_cp: Bogus length %zu in firmware \"%s\"\n", dev_priv->me_fw->size, fw_name); ---- a/drivers/infiniband/hw/qib/qib_sd7220.c -+++ b/drivers/infiniband/hw/qib/qib_sd7220.c -@@ -403,10 +403,8 @@ int qib_sd7220_init(struct qib_devdata * +Index: linux-3.2.46/drivers/infiniband/hw/qib/qib_sd7220.c +=================================================================== +--- linux-3.2.46.orig/drivers/infiniband/hw/qib/qib_sd7220.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/infiniband/hw/qib/qib_sd7220.c 2013-07-26 19:25:21.000000000 +0000 +@@ -403,10 +403,8 @@ } ret = request_firmware(&fw, SD7220_FW_NAME, &dd->pcidev->dev); @@ -339,9 +381,11 @@ /* Substitute our deduced value for was_reset */ ret = qib_ibsd_ucode_loaded(dd->pport, fw); ---- a/drivers/input/touchscreen/atmel_mxt_ts.c -+++ b/drivers/input/touchscreen/atmel_mxt_ts.c -@@ -954,10 +954,8 @@ static int mxt_load_fw(struct device *de +Index: linux-3.2.46/drivers/input/touchscreen/atmel_mxt_ts.c +=================================================================== +--- linux-3.2.46.orig/drivers/input/touchscreen/atmel_mxt_ts.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/input/touchscreen/atmel_mxt_ts.c 2013-07-26 19:25:21.000000000 +0000 +@@ -954,10 +954,8 @@ int ret; ret = request_firmware(&fw, fn, dev); @@ -353,9 +397,11 @@ /* Change to the bootloader mode */ mxt_write_object(data, MXT_GEN_COMMAND_T6, ---- a/drivers/isdn/hardware/mISDN/speedfax.c -+++ b/drivers/isdn/hardware/mISDN/speedfax.c -@@ -389,11 +389,8 @@ setup_instance(struct sfax_hw *card) +Index: linux-3.2.46/drivers/isdn/hardware/mISDN/speedfax.c +=================================================================== +--- linux-3.2.46.orig/drivers/isdn/hardware/mISDN/speedfax.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/isdn/hardware/mISDN/speedfax.c 2013-07-26 19:25:21.000000000 +0000 +@@ -389,11 +389,8 @@ card->isar.owner = THIS_MODULE; err = request_firmware(&firmware, "isdn/ISAR.BIN", &card->pdev->dev); @@ -368,9 +414,11 @@ if (debug & DEBUG_HW) pr_notice("%s: got firmware %zu bytes\n", card->name, firmware->size); ---- a/drivers/media/common/tuners/tuner-xc2028.c -+++ b/drivers/media/common/tuners/tuner-xc2028.c -@@ -278,16 +278,8 @@ static int load_all_firmwares(struct dvb +Index: linux-3.2.46/drivers/media/common/tuners/tuner-xc2028.c +=================================================================== +--- linux-3.2.46.orig/drivers/media/common/tuners/tuner-xc2028.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/media/common/tuners/tuner-xc2028.c 2013-07-26 19:25:22.000000000 +0000 +@@ -278,16 +278,8 @@ tuner_dbg("Reading firmware %s\n", fname); rc = request_firmware(&fw, fname, priv->i2c_props.adap->dev.parent); @@ -388,9 +436,11 @@ p = fw->data; endp = p + fw->size; ---- a/drivers/media/dvb/dvb-usb/dib0700_devices.c -+++ b/drivers/media/dvb/dvb-usb/dib0700_devices.c -@@ -1852,12 +1852,9 @@ static int stk9090m_frontend_attach(stru +Index: linux-3.2.46/drivers/media/dvb/dvb-usb/dib0700_devices.c +=================================================================== +--- linux-3.2.46.orig/drivers/media/dvb/dvb-usb/dib0700_devices.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/media/dvb/dvb-usb/dib0700_devices.c 2013-07-26 19:25:22.000000000 +0000 +@@ -1852,12 +1852,9 @@ dib9000_i2c_enumeration(&adap->dev->i2c_adap, 1, 0x10, 0x80); @@ -405,7 +455,7 @@ stk9090m_config.microcode_B_fe_size = state->frontend_firmware->size; stk9090m_config.microcode_B_fe_buffer = state->frontend_firmware->data; -@@ -1918,12 +1915,9 @@ static int nim9090md_frontend_attach(str +@@ -1918,12 +1915,9 @@ msleep(20); dib0700_set_gpio(adap->dev, GPIO0, GPIO_OUT, 1); @@ -420,9 +470,11 @@ nim9090md_config[0].microcode_B_fe_size = state->frontend_firmware->size; nim9090md_config[0].microcode_B_fe_buffer = state->frontend_firmware->data; nim9090md_config[1].microcode_B_fe_size = state->frontend_firmware->size; ---- a/drivers/media/dvb/dvb-usb/dvb-usb-firmware.c -+++ b/drivers/media/dvb/dvb-usb/dvb-usb-firmware.c -@@ -80,14 +80,9 @@ int dvb_usb_download_firmware(struct usb +Index: linux-3.2.46/drivers/media/dvb/dvb-usb/dvb-usb-firmware.c +=================================================================== +--- linux-3.2.46.orig/drivers/media/dvb/dvb-usb/dvb-usb-firmware.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/media/dvb/dvb-usb/dvb-usb-firmware.c 2013-07-26 19:25:22.000000000 +0000 +@@ -80,14 +80,9 @@ int ret; const struct firmware *fw = NULL; @@ -439,9 +491,11 @@ switch (props->usb_ctrl) { case CYPRESS_AN2135: ---- a/drivers/media/dvb/dvb-usb/gp8psk.c -+++ b/drivers/media/dvb/dvb-usb/gp8psk.c -@@ -116,20 +116,14 @@ static int gp8psk_load_bcm4500fw(struct +Index: linux-3.2.46/drivers/media/dvb/dvb-usb/gp8psk.c +=================================================================== +--- linux-3.2.46.orig/drivers/media/dvb/dvb-usb/gp8psk.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/media/dvb/dvb-usb/gp8psk.c 2013-07-26 19:25:22.000000000 +0000 +@@ -116,20 +116,14 @@ const u8 *ptr; u8 *buf; if ((ret = request_firmware(&fw, bcm4500_firmware, @@ -463,9 +517,11 @@ ptr = fw->data; buf = kmalloc(64, GFP_KERNEL | GFP_DMA); if (!buf) { ---- a/drivers/media/dvb/dvb-usb/opera1.c -+++ b/drivers/media/dvb/dvb-usb/opera1.c -@@ -452,9 +452,6 @@ static int opera1_xilinx_load_firmware(s +Index: linux-3.2.46/drivers/media/dvb/dvb-usb/opera1.c +=================================================================== +--- linux-3.2.46.orig/drivers/media/dvb/dvb-usb/opera1.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/media/dvb/dvb-usb/opera1.c 2013-07-26 19:25:22.000000000 +0000 +@@ -452,9 +452,6 @@ info("start downloading fpga firmware %s",filename); if ((ret = request_firmware(&fw, filename, &dev->dev)) != 0) { @@ -475,9 +531,11 @@ return ret; } else { p = kmalloc(fw->size, GFP_KERNEL); ---- a/drivers/media/dvb/frontends/af9013.c -+++ b/drivers/media/dvb/frontends/af9013.c -@@ -1346,15 +1346,8 @@ static int af9013_download_firmware(stru +Index: linux-3.2.46/drivers/media/dvb/frontends/af9013.c +=================================================================== +--- linux-3.2.46.orig/drivers/media/dvb/frontends/af9013.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/media/dvb/frontends/af9013.c 2013-07-26 19:25:22.000000000 +0000 +@@ -1346,15 +1346,8 @@ /* request the firmware, this will block and timeout */ ret = request_firmware(&fw, fw_file, state->i2c->dev.parent); @@ -494,9 +552,11 @@ /* calc checksum */ for (i = 0; i < fw->size; i++) ---- a/drivers/media/dvb/frontends/bcm3510.c -+++ b/drivers/media/dvb/frontends/bcm3510.c -@@ -619,10 +619,9 @@ static int bcm3510_download_firmware(str +Index: linux-3.2.46/drivers/media/dvb/frontends/bcm3510.c +=================================================================== +--- linux-3.2.46.orig/drivers/media/dvb/frontends/bcm3510.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/media/dvb/frontends/bcm3510.c 2013-07-26 19:25:22.000000000 +0000 +@@ -619,10 +619,9 @@ int ret,i; deb_info("requesting firmware\n"); @@ -509,9 +569,11 @@ deb_info("got firmware: %zd\n",fw->size); b = fw->data; ---- a/drivers/media/dvb/frontends/cx24116.c -+++ b/drivers/media/dvb/frontends/cx24116.c -@@ -493,13 +493,8 @@ static int cx24116_firmware_ondemand(str +Index: linux-3.2.46/drivers/media/dvb/frontends/cx24116.c +=================================================================== +--- linux-3.2.46.orig/drivers/media/dvb/frontends/cx24116.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/media/dvb/frontends/cx24116.c 2013-07-26 19:25:22.000000000 +0000 +@@ -493,13 +493,8 @@ __func__, CX24116_DEFAULT_FIRMWARE); ret = request_firmware(&fw, CX24116_DEFAULT_FIRMWARE, state->i2c->dev.parent); @@ -526,9 +588,11 @@ /* Make sure we don't recurse back through here * during loading */ ---- a/drivers/media/dvb/frontends/drxd_hard.c -+++ b/drivers/media/dvb/frontends/drxd_hard.c -@@ -909,10 +909,8 @@ static int load_firmware(struct drxd_sta +Index: linux-3.2.46/drivers/media/dvb/frontends/drxd_hard.c +=================================================================== +--- linux-3.2.46.orig/drivers/media/dvb/frontends/drxd_hard.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/media/dvb/frontends/drxd_hard.c 2013-07-26 19:25:22.000000000 +0000 +@@ -909,10 +909,8 @@ { const struct firmware *fw; @@ -540,9 +604,11 @@ state->microcode = kmalloc(fw->size, GFP_KERNEL); if (state->microcode == NULL) { ---- a/drivers/media/dvb/frontends/drxk_hard.c -+++ b/drivers/media/dvb/frontends/drxk_hard.c -@@ -5968,13 +5968,8 @@ static int load_microcode(struct drxk_st +Index: linux-3.2.46/drivers/media/dvb/frontends/drxk_hard.c +=================================================================== +--- linux-3.2.46.orig/drivers/media/dvb/frontends/drxk_hard.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/media/dvb/frontends/drxk_hard.c 2013-07-26 19:25:22.000000000 +0000 +@@ -5968,13 +5968,8 @@ dprintk(1, "\n"); err = request_firmware(&fw, mc_name, state->i2c->dev.parent); @@ -557,9 +623,11 @@ err = DownloadMicrocode(state, fw->data, fw->size); release_firmware(fw); return err; ---- a/drivers/media/dvb/frontends/ds3000.c -+++ b/drivers/media/dvb/frontends/ds3000.c -@@ -403,12 +403,8 @@ static int ds3000_firmware_ondemand(stru +Index: linux-3.2.46/drivers/media/dvb/frontends/ds3000.c +=================================================================== +--- linux-3.2.46.orig/drivers/media/dvb/frontends/ds3000.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/media/dvb/frontends/ds3000.c 2013-07-26 19:25:22.000000000 +0000 +@@ -403,12 +403,8 @@ DS3000_DEFAULT_FIRMWARE); ret = request_firmware(&fw, DS3000_DEFAULT_FIRMWARE, state->i2c->dev.parent); @@ -573,9 +641,11 @@ /* Make sure we don't recurse back through here during loading */ state->skip_fw_load = 1; ---- a/drivers/media/dvb/frontends/nxt200x.c -+++ b/drivers/media/dvb/frontends/nxt200x.c -@@ -881,11 +881,8 @@ static int nxt2002_init(struct dvb_front +Index: linux-3.2.46/drivers/media/dvb/frontends/nxt200x.c +=================================================================== +--- linux-3.2.46.orig/drivers/media/dvb/frontends/nxt200x.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/media/dvb/frontends/nxt200x.c 2013-07-26 19:25:22.000000000 +0000 +@@ -881,11 +881,8 @@ printk("nxt2002: Waiting for firmware upload (%s)...\n", NXT2002_DEFAULT_FIRMWARE); ret = request_firmware(&fw, NXT2002_DEFAULT_FIRMWARE, state->i2c->dev.parent); @@ -588,7 +658,7 @@ ret = nxt2002_load_firmware(fe, fw); release_firmware(fw); -@@ -946,11 +943,8 @@ static int nxt2004_init(struct dvb_front +@@ -946,11 +943,8 @@ printk("nxt2004: Waiting for firmware upload (%s)...\n", NXT2004_DEFAULT_FIRMWARE); ret = request_firmware(&fw, NXT2004_DEFAULT_FIRMWARE, state->i2c->dev.parent); @@ -601,9 +671,11 @@ ret = nxt2004_load_firmware(fe, fw); release_firmware(fw); ---- a/drivers/media/dvb/frontends/or51132.c -+++ b/drivers/media/dvb/frontends/or51132.c -@@ -341,11 +341,8 @@ static int or51132_set_parameters(struct +Index: linux-3.2.46/drivers/media/dvb/frontends/or51132.c +=================================================================== +--- linux-3.2.46.orig/drivers/media/dvb/frontends/or51132.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/media/dvb/frontends/or51132.c 2013-07-26 19:25:22.000000000 +0000 +@@ -341,11 +341,8 @@ printk("or51132: Waiting for firmware upload(%s)...\n", fwname); ret = request_firmware(&fw, fwname, state->i2c->dev.parent); @@ -616,9 +688,11 @@ ret = or51132_load_firmware(fe, fw); release_firmware(fw); if (ret) { ---- a/drivers/media/dvb/frontends/or51211.c -+++ b/drivers/media/dvb/frontends/or51211.c -@@ -379,12 +379,8 @@ static int or51211_init(struct dvb_front +Index: linux-3.2.46/drivers/media/dvb/frontends/or51211.c +=================================================================== +--- linux-3.2.46.orig/drivers/media/dvb/frontends/or51211.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/media/dvb/frontends/or51211.c 2013-07-26 19:25:22.000000000 +0000 +@@ -379,12 +379,8 @@ "(%s)...\n", OR51211_DEFAULT_FIRMWARE); ret = config->request_firmware(fe, &fw, OR51211_DEFAULT_FIRMWARE); @@ -632,9 +706,11 @@ ret = or51211_load_firmware(fe, fw); release_firmware(fw); ---- a/drivers/media/dvb/frontends/sp8870.c -+++ b/drivers/media/dvb/frontends/sp8870.c -@@ -315,10 +315,8 @@ static int sp8870_init (struct dvb_front +Index: linux-3.2.46/drivers/media/dvb/frontends/sp8870.c +=================================================================== +--- linux-3.2.46.orig/drivers/media/dvb/frontends/sp8870.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/media/dvb/frontends/sp8870.c 2013-07-26 19:25:22.000000000 +0000 +@@ -315,10 +315,8 @@ /* request the firmware, this will block until someone uploads it */ printk("sp8870: waiting for firmware upload (%s)...\n", SP8870_DEFAULT_FIRMWARE); @@ -646,9 +722,11 @@ if (sp8870_firmware_upload(state, fw)) { printk("sp8870: writing firmware to device failed\n"); ---- a/drivers/media/dvb/frontends/sp887x.c -+++ b/drivers/media/dvb/frontends/sp887x.c -@@ -514,10 +514,8 @@ static int sp887x_init(struct dvb_fronte +Index: linux-3.2.46/drivers/media/dvb/frontends/sp887x.c +=================================================================== +--- linux-3.2.46.orig/drivers/media/dvb/frontends/sp887x.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/media/dvb/frontends/sp887x.c 2013-07-26 19:25:22.000000000 +0000 +@@ -514,10 +514,8 @@ /* request the firmware, this will block until someone uploads it */ printk("sp887x: waiting for firmware upload (%s)...\n", SP887X_DEFAULT_FIRMWARE); ret = state->config->request_firmware(fe, &fw, SP887X_DEFAULT_FIRMWARE); @@ -660,9 +738,11 @@ ret = sp887x_initial_setup(fe, fw); release_firmware(fw); ---- a/drivers/media/dvb/frontends/tda10048.c -+++ b/drivers/media/dvb/frontends/tda10048.c -@@ -509,8 +509,6 @@ static int tda10048_firmware_upload(stru +Index: linux-3.2.46/drivers/media/dvb/frontends/tda10048.c +=================================================================== +--- linux-3.2.46.orig/drivers/media/dvb/frontends/tda10048.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/media/dvb/frontends/tda10048.c 2013-07-26 19:25:22.000000000 +0000 +@@ -509,8 +509,6 @@ ret = request_firmware(&fw, TDA10048_DEFAULT_FIRMWARE, state->i2c->dev.parent); if (ret) { @@ -671,9 +751,11 @@ return -EIO; } else { printk(KERN_INFO "%s: firmware read %Zu bytes.\n", ---- a/drivers/media/dvb/frontends/tda1004x.c -+++ b/drivers/media/dvb/frontends/tda1004x.c -@@ -397,10 +397,8 @@ static int tda10045_fwupload(struct dvb_ +Index: linux-3.2.46/drivers/media/dvb/frontends/tda1004x.c +=================================================================== +--- linux-3.2.46.orig/drivers/media/dvb/frontends/tda1004x.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/media/dvb/frontends/tda1004x.c 2013-07-26 19:25:22.000000000 +0000 +@@ -397,10 +397,8 @@ /* request the firmware, this will block until someone uploads it */ printk(KERN_INFO "tda1004x: waiting for firmware upload (%s)...\n", TDA10045_DEFAULT_FIRMWARE); ret = state->config->request_firmware(fe, &fw, TDA10045_DEFAULT_FIRMWARE); @@ -685,7 +767,7 @@ /* reset chip */ tda1004x_write_mask(state, TDA1004X_CONFC4, 0x10, 0); -@@ -541,7 +539,6 @@ static int tda10046_fwupload(struct dvb_ +@@ -541,7 +539,6 @@ /* remain compatible to old bug: try to load with tda10045 image name */ ret = state->config->request_firmware(fe, &fw, TDA10045_DEFAULT_FIRMWARE); if (ret) { @@ -693,9 +775,11 @@ return ret; } else { printk(KERN_INFO "tda1004x: please rename the firmware file to %s\n", ---- a/drivers/media/dvb/frontends/tda10071.c -+++ b/drivers/media/dvb/frontends/tda10071.c -@@ -930,13 +930,8 @@ static int tda10071_init(struct dvb_fron +Index: linux-3.2.46/drivers/media/dvb/frontends/tda10071.c +=================================================================== +--- linux-3.2.46.orig/drivers/media/dvb/frontends/tda10071.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/media/dvb/frontends/tda10071.c 2013-07-26 19:25:22.000000000 +0000 +@@ -930,13 +930,8 @@ /* request the firmware, this will block and timeout */ ret = request_firmware(&fw, fw_file, priv->i2c->dev.parent); @@ -710,9 +794,11 @@ /* init */ for (i = 0; i < ARRAY_SIZE(tab2); i++) { ---- a/drivers/media/dvb/ngene/ngene-core.c -+++ b/drivers/media/dvb/ngene/ngene-core.c -@@ -1272,13 +1272,8 @@ static int ngene_load_firm(struct ngene +Index: linux-3.2.46/drivers/media/dvb/ngene/ngene-core.c +=================================================================== +--- linux-3.2.46.orig/drivers/media/dvb/ngene/ngene-core.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/media/dvb/ngene/ngene-core.c 2013-07-26 19:25:22.000000000 +0000 +@@ -1272,13 +1272,8 @@ break; } @@ -727,7 +813,7 @@ if (size == 0) size = fw->size; if (size != fw->size) { -@@ -1286,8 +1281,6 @@ static int ngene_load_firm(struct ngene +@@ -1286,8 +1281,6 @@ ": Firmware %s has invalid size!", fw_name); err = -1; } else { @@ -736,9 +822,11 @@ ngene_fw = (u8 *) fw->data; err = ngene_command_load_firmware(dev, ngene_fw, size); } ---- a/drivers/media/dvb/siano/smscoreapi.c -+++ b/drivers/media/dvb/siano/smscoreapi.c -@@ -642,10 +642,8 @@ static int smscore_load_firmware_from_fi +Index: linux-3.2.46/drivers/media/dvb/siano/smscoreapi.c +=================================================================== +--- linux-3.2.46.orig/drivers/media/dvb/siano/smscoreapi.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/media/dvb/siano/smscoreapi.c 2013-07-26 19:25:22.000000000 +0000 +@@ -642,10 +642,8 @@ return -EINVAL; rc = request_firmware(&fw, filename, coredev->device); @@ -750,9 +838,11 @@ sms_info("read FW %s, size=%zd", filename, fw->size); fw_buffer = kmalloc(ALIGN(fw->size, SMS_ALLOC_ALIGNMENT), GFP_KERNEL | GFP_DMA); ---- a/drivers/media/dvb/ttpci/av7110.c -+++ b/drivers/media/dvb/ttpci/av7110.c -@@ -1532,16 +1532,9 @@ static int get_firmware(struct av7110* a +Index: linux-3.2.46/drivers/media/dvb/ttpci/av7110.c +=================================================================== +--- linux-3.2.46.orig/drivers/media/dvb/ttpci/av7110.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/media/dvb/ttpci/av7110.c 2013-07-26 19:25:22.000000000 +0000 +@@ -1532,16 +1532,9 @@ /* request the av7110 firmware, this will block until someone uploads it */ ret = request_firmware(&fw, "dvb-ttpci-01.fw", &av7110->dev->pci->dev); if (ret) { @@ -771,9 +861,11 @@ return -EINVAL; } ---- a/drivers/media/dvb/ttpci/av7110_hw.c -+++ b/drivers/media/dvb/ttpci/av7110_hw.c -@@ -243,11 +243,8 @@ int av7110_bootarm(struct av7110 *av7110 +Index: linux-3.2.46/drivers/media/dvb/ttpci/av7110_hw.c +=================================================================== +--- linux-3.2.46.orig/drivers/media/dvb/ttpci/av7110_hw.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/media/dvb/ttpci/av7110_hw.c 2013-07-26 19:25:22.000000000 +0000 +@@ -243,11 +243,8 @@ //saa7146_setgpio(dev, 3, SAA7146_GPIO_INPUT); ret = request_firmware(&fw, fw_name, &dev->pci->dev); @@ -786,9 +878,11 @@ mwdebi(av7110, DEBISWAB, DPRAM_BASE, fw->data, fw->size); release_firmware(fw); ---- a/drivers/media/dvb/ttusb-budget/dvb-ttusb-budget.c -+++ b/drivers/media/dvb/ttusb-budget/dvb-ttusb-budget.c -@@ -296,10 +296,8 @@ static int ttusb_boot_dsp(struct ttusb * +Index: linux-3.2.46/drivers/media/dvb/ttusb-budget/dvb-ttusb-budget.c +=================================================================== +--- linux-3.2.46.orig/drivers/media/dvb/ttusb-budget/dvb-ttusb-budget.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/media/dvb/ttusb-budget/dvb-ttusb-budget.c 2013-07-26 19:25:22.000000000 +0000 +@@ -296,10 +296,8 @@ err = request_firmware(&fw, "ttusb-budget/dspbootcode.bin", &ttusb->dev->dev); @@ -800,9 +894,11 @@ /* BootBlock */ b[0] = 0xaa; ---- a/drivers/media/dvb/ttusb-dec/ttusb_dec.c -+++ b/drivers/media/dvb/ttusb-dec/ttusb_dec.c -@@ -1293,11 +1293,8 @@ static int ttusb_dec_boot_dsp(struct ttu +Index: linux-3.2.46/drivers/media/dvb/ttusb-dec/ttusb_dec.c +=================================================================== +--- linux-3.2.46.orig/drivers/media/dvb/ttusb-dec/ttusb_dec.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/media/dvb/ttusb-dec/ttusb_dec.c 2013-07-26 19:25:22.000000000 +0000 +@@ -1293,11 +1293,8 @@ dprintk("%s\n", __func__); @@ -815,9 +911,11 @@ firmware = fw_entry->data; firmware_size = fw_entry->size; ---- a/drivers/media/radio/radio-wl1273.c -+++ b/drivers/media/radio/radio-wl1273.c -@@ -512,11 +512,8 @@ static int wl1273_fm_upload_firmware_pat +Index: linux-3.2.46/drivers/media/radio/radio-wl1273.c +=================================================================== +--- linux-3.2.46.orig/drivers/media/radio/radio-wl1273.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/media/radio/radio-wl1273.c 2013-07-26 19:25:22.000000000 +0000 +@@ -512,11 +512,8 @@ * Uploading the firmware patch is not always necessary, * so we only print an info message. */ @@ -830,9 +928,11 @@ ptr = (__u8 *) fw_p->data; packet_num = ptr[0]; ---- a/drivers/media/radio/wl128x/fmdrv_common.c -+++ b/drivers/media/radio/wl128x/fmdrv_common.c -@@ -1248,10 +1248,8 @@ static u32 fm_download_firmware(struct f +Index: linux-3.2.46/drivers/media/radio/wl128x/fmdrv_common.c +=================================================================== +--- linux-3.2.46.orig/drivers/media/radio/wl128x/fmdrv_common.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/media/radio/wl128x/fmdrv_common.c 2013-07-26 19:25:22.000000000 +0000 +@@ -1248,10 +1248,8 @@ ret = request_firmware(&fw_entry, fw_name, &fmdev->radio_dev->dev); @@ -844,9 +944,11 @@ fmdbg("Firmware(%s) length : %d bytes\n", fw_name, fw_entry->size); fw_data = (void *)fw_entry->data; ---- a/drivers/media/video/bt8xx/bttv-cards.c -+++ b/drivers/media/video/bt8xx/bttv-cards.c -@@ -3766,10 +3766,8 @@ static int __devinit pvr_boot(struct btt +Index: linux-3.2.46/drivers/media/video/bt8xx/bttv-cards.c +=================================================================== +--- linux-3.2.46.orig/drivers/media/video/bt8xx/bttv-cards.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/media/video/bt8xx/bttv-cards.c 2013-07-26 19:25:22.000000000 +0000 +@@ -3766,10 +3766,8 @@ int rc; rc = request_firmware(&fw_entry, "hcwamc.rbf", &btv->c.pci->dev); @@ -858,9 +960,11 @@ rc = pvr_altera_load(btv, fw_entry->data, fw_entry->size); pr_info("%d: altera firmware upload %s\n", btv->c.nr, (rc < 0) ? "failed" : "ok"); ---- a/drivers/media/video/cpia2/cpia2_core.c -+++ b/drivers/media/video/cpia2/cpia2_core.c -@@ -905,11 +905,8 @@ static int apply_vp_patch(struct camera_ +Index: linux-3.2.46/drivers/media/video/cpia2/cpia2_core.c +=================================================================== +--- linux-3.2.46.orig/drivers/media/video/cpia2/cpia2_core.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/media/video/cpia2/cpia2_core.c 2013-07-26 19:25:22.000000000 +0000 +@@ -905,11 +905,8 @@ struct cpia2_command cmd; ret = request_firmware(&fw, fw_name, &cam->dev->dev); @@ -873,9 +977,11 @@ cmd.req_mode = CAMERAACCESS_TYPE_REPEAT | CAMERAACCESS_VP; cmd.direction = TRANSFER_WRITE; ---- a/drivers/media/video/cx18/cx18-av-firmware.c -+++ b/drivers/media/video/cx18/cx18-av-firmware.c -@@ -85,10 +85,8 @@ int cx18_av_loadfw(struct cx18 *cx) +Index: linux-3.2.46/drivers/media/video/cx18/cx18-av-firmware.c +=================================================================== +--- linux-3.2.46.orig/drivers/media/video/cx18/cx18-av-firmware.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/media/video/cx18/cx18-av-firmware.c 2013-07-26 19:25:22.000000000 +0000 +@@ -85,10 +85,8 @@ int i; int retries1 = 0; @@ -887,9 +993,11 @@ /* The firmware load often has byte errors, so allow for several retries, both at byte level and at the firmware load level. */ ---- a/drivers/media/video/cx18/cx18-dvb.c -+++ b/drivers/media/video/cx18/cx18-dvb.c -@@ -139,9 +139,7 @@ static int yuan_mpc718_mt352_reqfw(struc +Index: linux-3.2.46/drivers/media/video/cx18/cx18-dvb.c +=================================================================== +--- linux-3.2.46.orig/drivers/media/video/cx18/cx18-dvb.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/media/video/cx18/cx18-dvb.c 2013-07-26 19:25:22.000000000 +0000 +@@ -139,9 +139,7 @@ int ret; ret = request_firmware(fw, fn, &cx->pci_dev->dev); @@ -900,7 +1008,7 @@ size_t sz = (*fw)->size; if (sz < 2 || sz > 64 || (sz % 2) != 0) { CX18_ERR("Firmware %s has a bad size: %lu bytes\n", -@@ -154,7 +152,7 @@ static int yuan_mpc718_mt352_reqfw(struc +@@ -154,7 +152,7 @@ if (ret) { CX18_ERR("The MPC718 board variant with the MT352 DVB-T" @@ -909,9 +1017,11 @@ CX18_ERR("Run 'linux/Documentation/dvb/get_dvb_firmware " "mpc718' if you need the firmware\n"); } ---- a/drivers/media/video/cx18/cx18-firmware.c -+++ b/drivers/media/video/cx18/cx18-firmware.c -@@ -106,11 +106,8 @@ static int load_cpu_fw_direct(const char +Index: linux-3.2.46/drivers/media/video/cx18/cx18-firmware.c +=================================================================== +--- linux-3.2.46.orig/drivers/media/video/cx18/cx18-firmware.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/media/video/cx18/cx18-firmware.c 2013-07-26 19:25:22.000000000 +0000 +@@ -106,11 +106,8 @@ u32 __iomem *dst = (u32 __iomem *)mem; const u32 *src; @@ -924,7 +1034,7 @@ src = (const u32 *)fw->data; -@@ -151,8 +148,6 @@ static int load_apu_fw_direct(const char +@@ -151,8 +148,6 @@ int sz; if (request_firmware(&fw, fn, &cx->pci_dev->dev)) { @@ -933,9 +1043,11 @@ cx18_setup_page(cx, 0); return -ENOMEM; } ---- a/drivers/media/video/cx231xx/cx231xx-417.c -+++ b/drivers/media/video/cx231xx/cx231xx-417.c -@@ -979,14 +979,8 @@ static int cx231xx_load_firmware(struct +Index: linux-3.2.46/drivers/media/video/cx231xx/cx231xx-417.c +=================================================================== +--- linux-3.2.46.orig/drivers/media/video/cx231xx/cx231xx-417.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/media/video/cx231xx/cx231xx-417.c 2013-07-26 19:25:22.000000000 +0000 +@@ -979,14 +979,8 @@ retval = request_firmware(&firmware, CX231xx_FIRM_IMAGE_NAME, &dev->udev->dev); @@ -951,9 +1063,11 @@ if (firmware->size != CX231xx_FIRM_IMAGE_SIZE) { printk(KERN_ERR "ERROR: Firmware size mismatch " ---- a/drivers/media/video/cx23885/cx23885-417.c -+++ b/drivers/media/video/cx23885/cx23885-417.c -@@ -929,14 +929,8 @@ static int cx23885_load_firmware(struct +Index: linux-3.2.46/drivers/media/video/cx23885/cx23885-417.c +=================================================================== +--- linux-3.2.46.orig/drivers/media/video/cx23885/cx23885-417.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/media/video/cx23885/cx23885-417.c 2013-07-26 19:25:22.000000000 +0000 +@@ -929,14 +929,8 @@ retval = request_firmware(&firmware, CX23885_FIRM_IMAGE_NAME, &dev->pci->dev); @@ -969,9 +1083,11 @@ if (firmware->size != CX23885_FIRM_IMAGE_SIZE) { printk(KERN_ERR "ERROR: Firmware size mismatch " ---- a/drivers/media/video/cx23885/cx23885-cards.c -+++ b/drivers/media/video/cx23885/cx23885-cards.c -@@ -1513,11 +1513,7 @@ void cx23885_card_setup(struct cx23885_d +Index: linux-3.2.46/drivers/media/video/cx23885/cx23885-cards.c +=================================================================== +--- linux-3.2.46.orig/drivers/media/video/cx23885/cx23885-cards.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/media/video/cx23885/cx23885-cards.c 2013-07-26 19:25:22.000000000 +0000 +@@ -1513,11 +1513,7 @@ cinfo.rev, filename); ret = request_firmware(&fw, filename, &dev->pci->dev); @@ -984,9 +1100,11 @@ altera_init(&netup_config, fw); release_firmware(fw); ---- a/drivers/media/video/cx25840/cx25840-firmware.c -+++ b/drivers/media/video/cx25840/cx25840-firmware.c -@@ -123,10 +123,8 @@ int cx25840_loadfw(struct i2c_client *cl +Index: linux-3.2.46/drivers/media/video/cx25840/cx25840-firmware.c +=================================================================== +--- linux-3.2.46.orig/drivers/media/video/cx25840/cx25840-firmware.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/media/video/cx25840/cx25840-firmware.c 2013-07-26 19:25:23.000000000 +0000 +@@ -123,10 +123,8 @@ MAX_BUF_SIZE = 16; /* cx231xx cannot accept more than 16 bytes at a time */ } @@ -998,9 +1116,11 @@ start_fw_load(client); ---- a/drivers/media/video/cx88/cx88-blackbird.c -+++ b/drivers/media/video/cx88/cx88-blackbird.c -@@ -446,13 +446,8 @@ static int blackbird_load_firmware(struc +Index: linux-3.2.46/drivers/media/video/cx88/cx88-blackbird.c +=================================================================== +--- linux-3.2.46.orig/drivers/media/video/cx88/cx88-blackbird.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/media/video/cx88/cx88-blackbird.c 2013-07-26 19:25:23.000000000 +0000 +@@ -446,13 +446,8 @@ &dev->pci->dev); @@ -1015,9 +1135,11 @@ if (firmware->size != BLACKBIRD_FIRM_IMAGE_SIZE) { dprintk(0, "ERROR: Firmware size mismatch (have %zd, expected %d)\n", ---- a/drivers/media/video/gspca/vicam.c -+++ b/drivers/media/video/gspca/vicam.c -@@ -270,10 +270,8 @@ static int sd_init(struct gspca_dev *gsp +Index: linux-3.2.46/drivers/media/video/gspca/vicam.c +=================================================================== +--- linux-3.2.46.orig/drivers/media/video/gspca/vicam.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/media/video/gspca/vicam.c 2013-07-26 19:25:23.000000000 +0000 +@@ -270,10 +270,8 @@ ret = request_ihex_firmware(&fw, "vicam/firmware.fw", &gspca_dev->dev->dev); @@ -1029,9 +1151,11 @@ firmware_buf = kmalloc(PAGE_SIZE, GFP_KERNEL); if (!firmware_buf) { ---- a/drivers/media/video/ivtv/ivtv-firmware.c -+++ b/drivers/media/video/ivtv/ivtv-firmware.c -@@ -80,8 +80,6 @@ retry: +Index: linux-3.2.46/drivers/media/video/ivtv/ivtv-firmware.c +=================================================================== +--- linux-3.2.46.orig/drivers/media/video/ivtv/ivtv-firmware.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/media/video/ivtv/ivtv-firmware.c 2013-07-26 19:25:23.000000000 +0000 +@@ -80,8 +80,6 @@ release_firmware(fw); return size; } @@ -1040,9 +1164,11 @@ return -ENOMEM; } ---- a/drivers/media/video/pvrusb2/pvrusb2-hdw.c -+++ b/drivers/media/video/pvrusb2/pvrusb2-hdw.c -@@ -1415,29 +1415,6 @@ static int pvr2_locate_firmware(struct p +Index: linux-3.2.46/drivers/media/video/pvrusb2/pvrusb2-hdw.c +=================================================================== +--- linux-3.2.46.orig/drivers/media/video/pvrusb2/pvrusb2-hdw.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/media/video/pvrusb2/pvrusb2-hdw.c 2013-07-26 19:25:23.000000000 +0000 +@@ -1415,29 +1415,6 @@ "request_firmware fatal error with code=%d",ret); return ret; } @@ -1072,9 +1198,11 @@ return ret; } ---- a/drivers/media/video/s2255drv.c -+++ b/drivers/media/video/s2255drv.c -@@ -2588,10 +2588,8 @@ static int s2255_probe(struct usb_interf +Index: linux-3.2.46/drivers/media/video/s2255drv.c +=================================================================== +--- linux-3.2.46.orig/drivers/media/video/s2255drv.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/media/video/s2255drv.c 2013-07-26 19:25:23.000000000 +0000 +@@ -2588,10 +2588,8 @@ } /* load the first chunk */ if (request_firmware(&dev->fw_data->fw, @@ -1086,9 +1214,11 @@ /* check the firmware is valid */ fw_size = dev->fw_data->fw->size; pdata = (__le32 *) &dev->fw_data->fw->data[fw_size - 8]; ---- a/drivers/media/video/s5p-mfc/s5p_mfc_ctrl.c -+++ b/drivers/media/video/s5p-mfc/s5p_mfc_ctrl.c -@@ -39,10 +39,8 @@ int s5p_mfc_alloc_and_load_firmware(stru +Index: linux-3.2.46/drivers/media/video/s5p-mfc/s5p_mfc_ctrl.c +=================================================================== +--- linux-3.2.46.orig/drivers/media/video/s5p-mfc/s5p_mfc_ctrl.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/media/video/s5p-mfc/s5p_mfc_ctrl.c 2013-07-26 19:25:23.000000000 +0000 +@@ -39,10 +39,8 @@ mfc_debug_enter(); err = request_firmware((const struct firmware **)&fw_blob, "s5p-mfc.fw", dev->v4l2_dev.dev); @@ -1100,7 +1230,7 @@ dev->fw_size = ALIGN(fw_blob->size, FIRMWARE_ALIGN); if (s5p_mfc_bitproc_buf) { mfc_err("Attempting to allocate firmware when it seems that it is already loaded\n"); -@@ -117,10 +115,8 @@ int s5p_mfc_reload_firmware(struct s5p_m +@@ -117,10 +115,8 @@ mfc_debug_enter(); err = request_firmware((const struct firmware **)&fw_blob, "s5p-mfc.fw", dev->v4l2_dev.dev); @@ -1112,9 +1242,11 @@ if (fw_blob->size > dev->fw_size) { mfc_err("MFC firmware is too big to be loaded\n"); release_firmware(fw_blob); ---- a/drivers/media/video/saa7164/saa7164-fw.c -+++ b/drivers/media/video/saa7164/saa7164-fw.c -@@ -420,11 +420,8 @@ int saa7164_downloadfirmware(struct saa7 +Index: linux-3.2.46/drivers/media/video/saa7164/saa7164-fw.c +=================================================================== +--- linux-3.2.46.orig/drivers/media/video/saa7164/saa7164-fw.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/media/video/saa7164/saa7164-fw.c 2013-07-26 19:25:23.000000000 +0000 +@@ -420,11 +420,8 @@ __func__, fwname); ret = request_firmware(&fw, fwname, &dev->pci->dev); @@ -1127,9 +1259,11 @@ printk(KERN_INFO "%s() firmware read %Zu bytes.\n", __func__, fw->size); ---- a/drivers/media/video/tlg2300/pd-main.c -+++ b/drivers/media/video/tlg2300/pd-main.c -@@ -219,10 +219,8 @@ static int firmware_download(struct usb_ +Index: linux-3.2.46/drivers/media/video/tlg2300/pd-main.c +=================================================================== +--- linux-3.2.46.orig/drivers/media/video/tlg2300/pd-main.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/media/video/tlg2300/pd-main.c 2013-07-26 19:25:23.000000000 +0000 +@@ -219,10 +219,8 @@ size_t max_packet_size; ret = request_firmware(&fw, firmware_name, &udev->dev); @@ -1141,9 +1275,11 @@ fwlength = fw->size; ---- a/drivers/misc/iwmc3200top/fw-download.c -+++ b/drivers/misc/iwmc3200top/fw-download.c -@@ -311,11 +311,8 @@ int iwmct_fw_load(struct iwmct_priv *pri +Index: linux-3.2.46/drivers/misc/iwmc3200top/fw-download.c +=================================================================== +--- linux-3.2.46.orig/drivers/misc/iwmc3200top/fw-download.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/misc/iwmc3200top/fw-download.c 2013-07-26 19:25:23.000000000 +0000 +@@ -311,11 +311,8 @@ /* get the firmware */ ret = request_firmware(&raw, fw_name, &priv->func->dev); @@ -1156,9 +1292,11 @@ if (raw->size < sizeof(struct iwmct_fw_sec_hdr)) { LOG_ERROR(priv, FW_DOWNLOAD, "%s smaller then (%zd) (%zd)\n", ---- a/drivers/misc/ti-st/st_kim.c -+++ b/drivers/misc/ti-st/st_kim.c -@@ -281,11 +281,8 @@ static long download_firmware(struct kim +Index: linux-3.2.46/drivers/misc/ti-st/st_kim.c +=================================================================== +--- linux-3.2.46.orig/drivers/misc/ti-st/st_kim.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/misc/ti-st/st_kim.c 2013-07-26 19:25:23.000000000 +0000 +@@ -281,11 +281,8 @@ request_firmware(&kim_gdata->fw_entry, bts_scr_name, &kim_gdata->kim_pdev->dev); if (unlikely((err != 0) || (kim_gdata->fw_entry->data == NULL) || @@ -1171,9 +1309,11 @@ ptr = (void *)kim_gdata->fw_entry->data; len = kim_gdata->fw_entry->size; /* bts_header to remove out magic number and ---- a/drivers/net/can/softing/softing_fw.c -+++ b/drivers/net/can/softing/softing_fw.c -@@ -237,11 +237,8 @@ int softing_load_app_fw(const char *file +Index: linux-3.2.46/drivers/net/can/softing/softing_fw.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/can/softing/softing_fw.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/net/can/softing/softing_fw.c 2013-07-26 19:25:23.000000000 +0000 +@@ -237,11 +237,8 @@ int8_t type_end = 0, type_entrypoint = 0; ret = request_firmware(&fw, file, &card->pdev->dev); @@ -1186,9 +1326,11 @@ dev_dbg(&card->pdev->dev, "firmware(%s) got %lu bytes\n", file, (unsigned long)fw->size); /* parse the firmware */ ---- a/drivers/net/ethernet/3com/typhoon.c -+++ b/drivers/net/ethernet/3com/typhoon.c -@@ -1289,11 +1289,8 @@ typhoon_request_firmware(struct typhoon +Index: linux-3.2.46/drivers/net/ethernet/3com/typhoon.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/3com/typhoon.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/3com/typhoon.c 2013-07-26 19:25:23.000000000 +0000 +@@ -1289,11 +1289,8 @@ return 0; err = request_firmware(&typhoon_fw, FIRMWARE_NAME, &tp->pdev->dev); @@ -1201,9 +1343,11 @@ image_data = (u8 *) typhoon_fw->data; remaining = typhoon_fw->size; ---- a/drivers/net/ethernet/adaptec/starfire.c -+++ b/drivers/net/ethernet/adaptec/starfire.c -@@ -1044,11 +1044,8 @@ static int netdev_open(struct net_device +Index: linux-3.2.46/drivers/net/ethernet/adaptec/starfire.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/adaptec/starfire.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/adaptec/starfire.c 2013-07-26 19:25:23.000000000 +0000 +@@ -1044,11 +1044,8 @@ #endif /* VLAN_SUPPORT */ retval = request_firmware(&fw_rx, FIRMWARE_RX, &np->pci_dev->dev); @@ -1216,7 +1360,7 @@ if (fw_rx->size % 4) { printk(KERN_ERR "starfire: bogus length %zu in \"%s\"\n", fw_rx->size, FIRMWARE_RX); -@@ -1056,11 +1053,8 @@ static int netdev_open(struct net_device +@@ -1056,11 +1053,8 @@ goto out_rx; } retval = request_firmware(&fw_tx, FIRMWARE_TX, &np->pci_dev->dev); @@ -1229,9 +1373,11 @@ if (fw_tx->size % 4) { printk(KERN_ERR "starfire: bogus length %zu in \"%s\"\n", fw_tx->size, FIRMWARE_TX); ---- a/drivers/net/ethernet/alteon/acenic.c -+++ b/drivers/net/ethernet/alteon/acenic.c -@@ -2906,11 +2906,8 @@ static int __devinit ace_load_firmware(s +Index: linux-3.2.46/drivers/net/ethernet/alteon/acenic.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/alteon/acenic.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/alteon/acenic.c 2013-07-26 19:25:23.000000000 +0000 +@@ -2906,11 +2906,8 @@ fw_name = "acenic/tg1.bin"; ret = request_firmware(&fw, fw_name, &ap->pdev->dev); @@ -1244,9 +1390,11 @@ fw_data = (void *)fw->data; ---- a/drivers/net/ethernet/broadcom/bnx2.c -+++ b/drivers/net/ethernet/broadcom/bnx2.c -@@ -3681,16 +3681,13 @@ static int bnx2_request_uncached_firmwar +Index: linux-3.2.46/drivers/net/ethernet/broadcom/bnx2.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/broadcom/bnx2.c 2013-07-26 19:24:43.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/broadcom/bnx2.c 2013-07-26 19:25:23.000000000 +0000 +@@ -3681,16 +3681,13 @@ } rc = request_firmware(&bp->mips_firmware, mips_fw_file, &bp->pdev->dev); @@ -1266,9 +1414,11 @@ mips_fw = (const struct bnx2_mips_fw_file *) bp->mips_firmware->data; rv2p_fw = (const struct bnx2_rv2p_fw_file *) bp->rv2p_firmware->data; if (bp->mips_firmware->size < sizeof(*mips_fw) || ---- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c -+++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c -@@ -10569,11 +10569,8 @@ int bnx2x_init_firmware(struct bnx2x *bp +Index: linux-3.2.46/drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c 2013-07-26 19:25:23.000000000 +0000 +@@ -10569,11 +10569,8 @@ rc = request_firmware(&bp->firmware, fw_file_name, &bp->pdev->dev); @@ -1281,9 +1431,11 @@ rc = bnx2x_check_firmware(bp); if (rc) { ---- a/drivers/net/ethernet/broadcom/tg3.c -+++ b/drivers/net/ethernet/broadcom/tg3.c -@@ -9527,11 +9527,8 @@ static int tg3_request_firmware(struct t +Index: linux-3.2.46/drivers/net/ethernet/broadcom/tg3.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/broadcom/tg3.c 2013-07-26 19:24:34.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/broadcom/tg3.c 2013-07-26 19:25:23.000000000 +0000 +@@ -9562,11 +9562,8 @@ { const __be32 *fw_data; @@ -1296,9 +1448,11 @@ fw_data = (void *)tp->fw->data; ---- a/drivers/net/ethernet/brocade/bna/cna_fwimg.c -+++ b/drivers/net/ethernet/brocade/bna/cna_fwimg.c -@@ -29,10 +29,8 @@ cna_read_firmware(struct pci_dev *pdev, +Index: linux-3.2.46/drivers/net/ethernet/brocade/bna/cna_fwimg.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/brocade/bna/cna_fwimg.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/brocade/bna/cna_fwimg.c 2013-07-26 19:25:23.000000000 +0000 +@@ -29,10 +29,8 @@ { const struct firmware *fw; @@ -1310,9 +1464,11 @@ *bfi_image = (u32 *)fw->data; *bfi_image_size = fw->size/sizeof(u32); ---- a/drivers/net/ethernet/chelsio/cxgb3/cxgb3_main.c -+++ b/drivers/net/ethernet/chelsio/cxgb3/cxgb3_main.c -@@ -1030,12 +1030,8 @@ int t3_get_edc_fw(struct cphy *phy, int +Index: linux-3.2.46/drivers/net/ethernet/chelsio/cxgb3/cxgb3_main.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/chelsio/cxgb3/cxgb3_main.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/chelsio/cxgb3/cxgb3_main.c 2013-07-26 19:25:23.000000000 +0000 +@@ -1030,12 +1030,8 @@ snprintf(buf, sizeof(buf), get_edc_fw_name(edc_idx)); ret = request_firmware(&fw, buf, &adapter->pdev->dev); @@ -1326,7 +1482,7 @@ /* check size, take checksum in account */ if (fw->size > size + 4) { -@@ -1072,11 +1068,8 @@ static int upgrade_fw(struct adapter *ad +@@ -1072,11 +1068,8 @@ struct device *dev = &adap->pdev->dev; ret = request_firmware(&fw, FW_FNAME, dev); @@ -1339,7 +1495,7 @@ ret = t3_load_fw(adap, fw->data, fw->size); release_firmware(fw); -@@ -1121,11 +1114,8 @@ static int update_tpsram(struct adapter +@@ -1121,11 +1114,8 @@ snprintf(buf, sizeof(buf), TPSRAM_NAME, rev); ret = request_firmware(&tpsram, buf, dev); @@ -1352,9 +1508,11 @@ ret = t3_check_tpsram(adap, tpsram->data, tpsram->size); if (ret) ---- a/drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c -+++ b/drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c -@@ -830,11 +830,8 @@ static int upgrade_fw(struct adapter *ad +Index: linux-3.2.46/drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c 2013-07-26 19:25:23.000000000 +0000 +@@ -830,11 +830,8 @@ struct device *dev = adap->pdev_dev; ret = request_firmware(&fw, FW_FNAME, dev); @@ -1367,9 +1525,11 @@ hdr = (const struct fw_hdr *)fw->data; vers = ntohl(hdr->fw_ver); ---- a/drivers/net/ethernet/intel/e100.c -+++ b/drivers/net/ethernet/intel/e100.c -@@ -1273,9 +1273,6 @@ static const struct firmware *e100_reque +Index: linux-3.2.46/drivers/net/ethernet/intel/e100.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/intel/e100.c 2013-07-26 19:24:06.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/intel/e100.c 2013-07-26 19:25:23.000000000 +0000 +@@ -1273,9 +1273,6 @@ if (err) { if (required) { @@ -1379,9 +1539,11 @@ return ERR_PTR(err); } else { netif_info(nic, probe, nic->netdev, ---- a/drivers/net/ethernet/myricom/myri10ge/myri10ge.c -+++ b/drivers/net/ethernet/myricom/myri10ge/myri10ge.c -@@ -594,8 +594,6 @@ static int myri10ge_load_hotplug_firmwar +Index: linux-3.2.46/drivers/net/ethernet/myricom/myri10ge/myri10ge.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/myricom/myri10ge/myri10ge.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/myricom/myri10ge/myri10ge.c 2013-07-26 19:25:23.000000000 +0000 +@@ -594,8 +594,6 @@ unsigned i; if ((status = request_firmware(&fw, mgp->fw_name, dev)) < 0) { @@ -1390,9 +1552,11 @@ status = -EINVAL; goto abort_with_nothing; } ---- a/drivers/net/ethernet/smsc/smc91c92_cs.c -+++ b/drivers/net/ethernet/smsc/smc91c92_cs.c -@@ -649,10 +649,8 @@ static int osi_load_firmware(struct pcmc +Index: linux-3.2.46/drivers/net/ethernet/smsc/smc91c92_cs.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/smsc/smc91c92_cs.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/smsc/smc91c92_cs.c 2013-07-26 19:25:23.000000000 +0000 +@@ -649,10 +649,8 @@ int i, err; err = request_firmware(&fw, FIRMWARE_NAME, &link->dev); @@ -1404,9 +1568,11 @@ /* Download the Seven of Diamonds firmware */ for (i = 0; i < fw->size; i++) { ---- a/drivers/net/ethernet/sun/cassini.c -+++ b/drivers/net/ethernet/sun/cassini.c -@@ -819,11 +819,8 @@ static int cas_saturn_firmware_init(stru +Index: linux-3.2.46/drivers/net/ethernet/sun/cassini.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/sun/cassini.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/sun/cassini.c 2013-07-26 19:25:23.000000000 +0000 +@@ -819,11 +819,8 @@ return 0; err = request_firmware(&fw, fw_name, &cp->pdev->dev); @@ -1419,9 +1585,11 @@ if (fw->size < 2) { pr_err("bogus length %zu in \"%s\"\n", fw->size, fw_name); ---- a/drivers/net/hamradio/yam.c -+++ b/drivers/net/hamradio/yam.c -@@ -373,11 +373,8 @@ static unsigned char *add_mcs(unsigned c +Index: linux-3.2.46/drivers/net/hamradio/yam.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/hamradio/yam.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/net/hamradio/yam.c 2013-07-26 19:25:23.000000000 +0000 +@@ -373,11 +373,8 @@ } err = request_firmware(&fw, fw_name[predef], &pdev->dev); platform_device_unregister(pdev); @@ -1434,9 +1602,11 @@ if (fw->size != YAM_FPGA_SIZE) { printk(KERN_ERR "Bogus length %zu in firmware \"%s\"\n", fw->size, fw_name[predef]); ---- a/drivers/net/usb/kaweth.c -+++ b/drivers/net/usb/kaweth.c -@@ -399,10 +399,8 @@ static int kaweth_download_firmware(stru +Index: linux-3.2.46/drivers/net/usb/kaweth.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/usb/kaweth.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/net/usb/kaweth.c 2013-07-26 19:25:23.000000000 +0000 +@@ -399,10 +399,8 @@ int ret; ret = request_firmware(&fw, fwname, &kaweth->dev->dev); @@ -1448,9 +1618,11 @@ if (fw->size > KAWETH_FIRMWARE_BUF_SIZE) { err("Firmware too big: %zu", fw->size); ---- a/drivers/net/wimax/i2400m/fw.c -+++ b/drivers/net/wimax/i2400m/fw.c -@@ -1582,11 +1582,8 @@ int i2400m_dev_bootstrap(struct i2400m * +Index: linux-3.2.46/drivers/net/wimax/i2400m/fw.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/wimax/i2400m/fw.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/net/wimax/i2400m/fw.c 2013-07-26 19:25:23.000000000 +0000 +@@ -1582,11 +1582,8 @@ } d_printf(1, dev, "trying firmware %s (%d)\n", fw_name, itr); ret = request_firmware(&fw, fw_name, dev); @@ -1463,7 +1635,7 @@ i2400m->fw_name = fw_name; ret = i2400m_fw_bootstrap(i2400m, fw, flags); release_firmware(fw); -@@ -1629,8 +1626,6 @@ void i2400m_fw_cache(struct i2400m *i240 +@@ -1629,8 +1626,6 @@ kref_init(&i2400m_fw->kref); result = request_firmware(&i2400m_fw->fw, i2400m->fw_name, dev); if (result < 0) { @@ -1472,9 +1644,11 @@ kfree(i2400m_fw); i2400m_fw = (void *) ~0; } else ---- a/drivers/net/wireless/at76c50x-usb.c -+++ b/drivers/net/wireless/at76c50x-usb.c -@@ -1584,14 +1584,8 @@ static struct fwentry *at76_load_firmwar +Index: linux-3.2.46/drivers/net/wireless/at76c50x-usb.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/wireless/at76c50x-usb.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/at76c50x-usb.c 2013-07-26 19:25:23.000000000 +0000 +@@ -1584,14 +1584,8 @@ at76_dbg(DBG_FW, "downloading firmware %s", fwe->fwname); ret = request_firmware(&fwe->fw, fwe->fwname, &udev->dev); @@ -1490,9 +1664,11 @@ at76_dbg(DBG_FW, "got it."); fwh = (struct at76_fw_header *)(fwe->fw->data); ---- a/drivers/net/wireless/ath/ath9k/hif_usb.c -+++ b/drivers/net/wireless/ath/ath9k/hif_usb.c -@@ -1030,11 +1030,8 @@ static int ath9k_hif_usb_dev_init(struct +Index: linux-3.2.46/drivers/net/wireless/ath/ath9k/hif_usb.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/wireless/ath/ath9k/hif_usb.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/ath/ath9k/hif_usb.c 2013-07-26 19:25:24.000000000 +0000 +@@ -1030,11 +1030,8 @@ /* Request firmware */ ret = request_firmware(&hif_dev->firmware, hif_dev->fw_name, &hif_dev->udev->dev); @@ -1505,9 +1681,11 @@ /* Download firmware */ ret = ath9k_hif_usb_download_fw(hif_dev, drv_info); ---- a/drivers/net/wireless/ath/carl9170/usb.c -+++ b/drivers/net/wireless/ath/carl9170/usb.c -@@ -1018,7 +1018,6 @@ static void carl9170_usb_firmware_step2( +Index: linux-3.2.46/drivers/net/wireless/ath/carl9170/usb.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/wireless/ath/carl9170/usb.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/ath/carl9170/usb.c 2013-07-26 19:25:24.000000000 +0000 +@@ -1018,7 +1018,6 @@ return; } @@ -1515,9 +1693,11 @@ carl9170_usb_firmware_failed(ar); } ---- a/drivers/net/wireless/atmel.c -+++ b/drivers/net/wireless/atmel.c -@@ -3937,12 +3937,8 @@ static int reset_atmel_card(struct net_d +Index: linux-3.2.46/drivers/net/wireless/atmel.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/wireless/atmel.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/atmel.c 2013-07-26 19:25:24.000000000 +0000 +@@ -3937,12 +3937,8 @@ strcpy(priv->firmware_id, "atmel_at76c502.bin"); } err = request_firmware(&fw_entry, priv->firmware_id, priv->sys_dev); @@ -1531,9 +1711,11 @@ } else { int fw_index = 0; int success = 0; ---- a/drivers/net/wireless/b43/main.c -+++ b/drivers/net/wireless/b43/main.c -@@ -2138,18 +2138,8 @@ int b43_do_request_fw(struct b43_request +Index: linux-3.2.46/drivers/net/wireless/b43/main.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/wireless/b43/main.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/b43/main.c 2013-07-26 19:25:24.000000000 +0000 +@@ -2131,18 +2131,8 @@ return -ENOSYS; } err = request_firmware(&blob, ctx->fwname, ctx->dev->dev->dev); @@ -1553,9 +1735,11 @@ if (blob->size < sizeof(struct b43_fw_header)) goto err_format; hdr = (struct b43_fw_header *)(blob->data); ---- a/drivers/net/wireless/b43legacy/main.c -+++ b/drivers/net/wireless/b43legacy/main.c -@@ -1527,11 +1527,8 @@ static int do_request_fw(struct b43legac +Index: linux-3.2.46/drivers/net/wireless/b43legacy/main.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/wireless/b43legacy/main.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/b43legacy/main.c 2013-07-26 19:25:24.000000000 +0000 +@@ -1527,11 +1527,8 @@ "b43legacy%s/%s.fw", modparam_fwpostfix, name); err = request_firmware(fw, path, dev->dev->dev); @@ -1568,9 +1752,11 @@ if ((*fw)->size < sizeof(struct b43legacy_fw_header)) goto err_format; hdr = (struct b43legacy_fw_header *)((*fw)->data); ---- a/drivers/net/wireless/brcm80211/brcmfmac/dhd_sdio.c -+++ b/drivers/net/wireless/brcm80211/brcmfmac/dhd_sdio.c -@@ -3413,10 +3413,8 @@ static int brcmf_sdbrcm_download_code_fi +Index: linux-3.2.46/drivers/net/wireless/brcm80211/brcmfmac/dhd_sdio.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/wireless/brcm80211/brcmfmac/dhd_sdio.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/brcm80211/brcmfmac/dhd_sdio.c 2013-07-26 19:25:24.000000000 +0000 +@@ -3413,10 +3413,8 @@ bus->fw_name = BCM4329_FW_NAME; ret = request_firmware(&bus->firmware, bus->fw_name, &bus->sdiodev->func[2]->dev); @@ -1582,7 +1768,7 @@ bus->fw_ptr = 0; memptr = memblock = kmalloc(MEMBLOCK + BRCMF_SDALIGN, GFP_ATOMIC); -@@ -3511,10 +3509,8 @@ static int brcmf_sdbrcm_download_nvram(s +@@ -3511,10 +3509,8 @@ bus->nv_name = BCM4329_NV_NAME; ret = request_firmware(&bus->firmware, bus->nv_name, &bus->sdiodev->func[2]->dev); @@ -1594,9 +1780,11 @@ bus->fw_ptr = 0; memblock = kmalloc(MEMBLOCK, GFP_ATOMIC); ---- a/drivers/net/wireless/brcm80211/brcmsmac/mac80211_if.c -+++ b/drivers/net/wireless/brcm80211/brcmsmac/mac80211_if.c -@@ -785,19 +785,13 @@ static int brcms_request_fw(struct brcms +Index: linux-3.2.46/drivers/net/wireless/brcm80211/brcmsmac/mac80211_if.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/wireless/brcm80211/brcmsmac/mac80211_if.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/brcm80211/brcmsmac/mac80211_if.c 2013-07-26 19:25:24.000000000 +0000 +@@ -785,19 +785,13 @@ sprintf(fw_name, "%s-%d.fw", brcms_firmwares[i], UCODE_LOADER_API_VER); status = request_firmware(&wl->fw.fw_bin[i], fw_name, device); @@ -1618,9 +1806,11 @@ wl->fw.hdr_num_entries[i] = wl->fw.fw_hdr[i]->size / (sizeof(struct firmware_hdr)); } ---- a/drivers/net/wireless/ipw2x00/ipw2100.c -+++ b/drivers/net/wireless/ipw2x00/ipw2100.c -@@ -8519,12 +8519,8 @@ static int ipw2100_get_firmware(struct i +Index: linux-3.2.46/drivers/net/wireless/ipw2x00/ipw2100.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/wireless/ipw2x00/ipw2100.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/ipw2x00/ipw2100.c 2013-07-26 19:25:24.000000000 +0000 +@@ -8519,12 +8519,8 @@ rc = request_firmware(&fw->fw_entry, fw_name, &priv->pci_dev->dev); @@ -1634,9 +1824,11 @@ IPW_DEBUG_INFO("firmware data %p size %zd\n", fw->fw_entry->data, fw->fw_entry->size); ---- a/drivers/net/wireless/ipw2x00/ipw2200.c -+++ b/drivers/net/wireless/ipw2x00/ipw2200.c -@@ -3401,10 +3401,8 @@ static int ipw_get_fw(struct ipw_priv *p +Index: linux-3.2.46/drivers/net/wireless/ipw2x00/ipw2200.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/wireless/ipw2x00/ipw2200.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/ipw2x00/ipw2200.c 2013-07-26 19:25:24.000000000 +0000 +@@ -3401,10 +3401,8 @@ /* ask firmware_class module to get the boot firmware off disk */ rc = request_firmware(raw, name, &priv->pci_dev->dev); @@ -1648,9 +1840,11 @@ if ((*raw)->size < sizeof(*fw)) { IPW_ERROR("%s is too small (%zd)\n", name, (*raw)->size); ---- a/drivers/net/wireless/iwlegacy/iwl3945-base.c -+++ b/drivers/net/wireless/iwlegacy/iwl3945-base.c -@@ -1870,8 +1870,6 @@ static int iwl3945_read_ucode(struct iwl +Index: linux-3.2.46/drivers/net/wireless/iwlegacy/iwl3945-base.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/wireless/iwlegacy/iwl3945-base.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/iwlegacy/iwl3945-base.c 2013-07-26 19:25:24.000000000 +0000 +@@ -1870,8 +1870,6 @@ sprintf(buf, "%s%u%s", name_pre, index, ".ucode"); ret = request_firmware(&ucode_raw, buf, &priv->pci_dev->dev); if (ret < 0) { @@ -1659,9 +1853,11 @@ if (ret == -ENOENT) continue; else ---- a/drivers/net/wireless/iwlwifi/iwl-agn.c -+++ b/drivers/net/wireless/iwlwifi/iwl-agn.c -@@ -909,13 +909,8 @@ static void iwl_ucode_callback(const str +Index: linux-3.2.46/drivers/net/wireless/iwlwifi/iwl-agn.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/wireless/iwlwifi/iwl-agn.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/iwlwifi/iwl-agn.c 2013-07-26 19:25:24.000000000 +0000 +@@ -909,13 +909,8 @@ memset(&pieces, 0, sizeof(pieces)); @@ -1676,9 +1872,11 @@ IWL_DEBUG_INFO(priv, "Loaded firmware file '%s' (%zd bytes).\n", priv->firmware_name, ucode_raw->size); ---- a/drivers/net/wireless/iwmc3200wifi/fw.c -+++ b/drivers/net/wireless/iwmc3200wifi/fw.c -@@ -168,10 +168,8 @@ static int iwm_load_img(struct iwm_priv +Index: linux-3.2.46/drivers/net/wireless/iwmc3200wifi/fw.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/wireless/iwmc3200wifi/fw.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/iwmc3200wifi/fw.c 2013-07-26 19:25:24.000000000 +0000 +@@ -168,10 +168,8 @@ char *build_tag; ret = request_firmware(&fw, img_name, iwm_to_dev(iwm)); @@ -1690,9 +1888,11 @@ IWM_DBG_FW(iwm, INFO, "Start to load FW %s\n", img_name); ---- a/drivers/net/wireless/libertas/main.c -+++ b/drivers/net/wireless/libertas/main.c -@@ -1207,19 +1207,13 @@ int lbs_get_firmware(struct device *dev, +Index: linux-3.2.46/drivers/net/wireless/libertas/main.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/wireless/libertas/main.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/libertas/main.c 2013-07-26 19:25:24.000000000 +0000 +@@ -1207,19 +1207,13 @@ /* Try user-specified firmware first */ if (user_helper) { ret = request_firmware(helper, user_helper, dev); @@ -1714,9 +1914,11 @@ } if (*helper && *mainfw) ---- a/drivers/net/wireless/libertas_tf/if_usb.c -+++ b/drivers/net/wireless/libertas_tf/if_usb.c -@@ -827,8 +827,6 @@ static int if_usb_prog_firmware(struct i +Index: linux-3.2.46/drivers/net/wireless/libertas_tf/if_usb.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/wireless/libertas_tf/if_usb.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/libertas_tf/if_usb.c 2013-07-26 19:25:24.000000000 +0000 +@@ -827,8 +827,6 @@ kparam_block_sysfs_write(fw_name); ret = request_firmware(&cardp->fw, lbtf_fw_name, &cardp->udev->dev); if (ret < 0) { @@ -1725,9 +1927,11 @@ kparam_unblock_sysfs_write(fw_name); goto done; } ---- a/drivers/net/wireless/mwifiex/main.c -+++ b/drivers/net/wireless/mwifiex/main.c -@@ -311,8 +311,6 @@ static int mwifiex_init_hw_fw(struct mwi +Index: linux-3.2.46/drivers/net/wireless/mwifiex/main.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/wireless/mwifiex/main.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/mwifiex/main.c 2013-07-26 19:25:24.000000000 +0000 +@@ -311,8 +311,6 @@ err = request_firmware(&adapter->firmware, adapter->fw_name, adapter->dev); if (err < 0) { @@ -1736,9 +1940,11 @@ ret = -1; goto done; } ---- a/drivers/net/wireless/mwl8k.c -+++ b/drivers/net/wireless/mwl8k.c -@@ -5191,16 +5191,12 @@ static int mwl8k_firmware_load_success(s +Index: linux-3.2.46/drivers/net/wireless/mwl8k.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/wireless/mwl8k.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/mwl8k.c 2013-07-26 19:25:24.000000000 +0000 +@@ -5191,16 +5191,12 @@ static void mwl8k_fw_state_machine(const struct firmware *fw, void *context) { struct mwl8k_priv *priv = context; @@ -1756,7 +1962,7 @@ priv->fw_helper = fw; rc = mwl8k_request_fw(priv, priv->fw_pref, &priv->fw_ucode, true); -@@ -5235,11 +5231,8 @@ static void mwl8k_fw_state_machine(const +@@ -5235,11 +5231,8 @@ break; case FW_STATE_LOADING_ALT: @@ -1769,7 +1975,7 @@ priv->fw_ucode = fw; rc = mwl8k_firmware_load_success(priv); if (rc) -@@ -5274,10 +5267,8 @@ static int mwl8k_init_firmware(struct ie +@@ -5274,10 +5267,8 @@ /* Ask userland hotplug daemon for the device firmware */ rc = mwl8k_request_firmware(priv, fw_image, nowait); @@ -1781,9 +1987,11 @@ if (nowait) return rc; ---- a/drivers/net/wireless/orinoco/fw.c -+++ b/drivers/net/wireless/orinoco/fw.c -@@ -132,7 +132,6 @@ orinoco_dl_firmware(struct orinoco_priva +Index: linux-3.2.46/drivers/net/wireless/orinoco/fw.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/wireless/orinoco/fw.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/orinoco/fw.c 2013-07-26 19:25:24.000000000 +0000 +@@ -132,7 +132,6 @@ err = request_firmware(&fw_entry, firmware, priv->dev); if (err) { @@ -1791,7 +1999,7 @@ err = -ENOENT; goto free; } -@@ -292,10 +291,8 @@ symbol_dl_firmware(struct orinoco_privat +@@ -292,10 +291,8 @@ const struct firmware *fw_entry; if (!orinoco_cached_fw_get(priv, true)) { @@ -1803,7 +2011,7 @@ } else fw_entry = orinoco_cached_fw_get(priv, true); -@@ -311,10 +308,8 @@ symbol_dl_firmware(struct orinoco_privat +@@ -311,10 +308,8 @@ } if (!orinoco_cached_fw_get(priv, false)) { @@ -1815,9 +2023,11 @@ } else fw_entry = orinoco_cached_fw_get(priv, false); ---- a/drivers/net/wireless/orinoco/orinoco_usb.c -+++ b/drivers/net/wireless/orinoco/orinoco_usb.c -@@ -1684,7 +1684,6 @@ static int ezusb_probe(struct usb_interf +Index: linux-3.2.46/drivers/net/wireless/orinoco/orinoco_usb.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/wireless/orinoco/orinoco_usb.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/orinoco/orinoco_usb.c 2013-07-26 19:25:24.000000000 +0000 +@@ -1684,7 +1684,6 @@ if (firmware.size && firmware.code) { ezusb_firmware_download(upriv, &firmware); } else { @@ -1825,9 +2035,11 @@ goto error; } ---- a/drivers/net/wireless/p54/p54pci.c -+++ b/drivers/net/wireless/p54/p54pci.c -@@ -564,7 +564,6 @@ static int __devinit p54p_probe(struct p +Index: linux-3.2.46/drivers/net/wireless/p54/p54pci.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/wireless/p54/p54pci.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/p54/p54pci.c 2013-07-26 19:25:24.000000000 +0000 +@@ -564,7 +564,6 @@ err = request_firmware(&priv->firmware, "isl3886pci", &priv->pdev->dev); if (err) { @@ -1835,9 +2047,11 @@ err = request_firmware(&priv->firmware, "isl3886", &priv->pdev->dev); if (err) ---- a/drivers/net/wireless/p54/p54spi.c -+++ b/drivers/net/wireless/p54/p54spi.c -@@ -171,10 +171,8 @@ static int p54spi_request_firmware(struc +Index: linux-3.2.46/drivers/net/wireless/p54/p54spi.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/wireless/p54/p54spi.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/p54/p54spi.c 2013-07-26 19:25:24.000000000 +0000 +@@ -171,10 +171,8 @@ /* FIXME: should driver use it's own struct device? */ ret = request_firmware(&priv->firmware, "3826.arm", &priv->spi->dev); @@ -1849,9 +2063,11 @@ ret = p54_parse_firmware(dev, priv->firmware); if (ret) { ---- a/drivers/net/wireless/p54/p54usb.c -+++ b/drivers/net/wireless/p54/p54usb.c -@@ -852,9 +852,6 @@ static int p54u_load_firmware(struct iee +Index: linux-3.2.46/drivers/net/wireless/p54/p54usb.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/wireless/p54/p54usb.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/p54/p54usb.c 2013-07-26 19:25:24.000000000 +0000 +@@ -856,9 +856,6 @@ err = request_firmware(&priv->fw, p54u_fwlist[i].fw, &priv->udev->dev); if (err) { @@ -1861,9 +2077,11 @@ err = request_firmware(&priv->fw, p54u_fwlist[i].fw_legacy, &priv->udev->dev); if (err) ---- a/drivers/net/wireless/prism54/islpci_dev.c -+++ b/drivers/net/wireless/prism54/islpci_dev.c -@@ -93,12 +93,9 @@ isl_upload_firmware(islpci_private *priv +Index: linux-3.2.46/drivers/net/wireless/prism54/islpci_dev.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/wireless/prism54/islpci_dev.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/prism54/islpci_dev.c 2013-07-26 19:25:24.000000000 +0000 +@@ -93,12 +93,9 @@ const u32 *fw_ptr; rc = request_firmware(&fw_entry, priv->firmware, PRISM_FW_PDEV); @@ -1878,9 +2096,11 @@ /* prepare the Direct Memory Base register */ reg = ISL38XX_DEV_FIRMWARE_ADDRES; ---- a/drivers/net/wireless/rt2x00/rt2x00firmware.c -+++ b/drivers/net/wireless/rt2x00/rt2x00firmware.c -@@ -51,10 +51,8 @@ static int rt2x00lib_request_firmware(st +Index: linux-3.2.46/drivers/net/wireless/rt2x00/rt2x00firmware.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/wireless/rt2x00/rt2x00firmware.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rt2x00/rt2x00firmware.c 2013-07-26 19:25:24.000000000 +0000 +@@ -51,10 +51,8 @@ INFO(rt2x00dev, "Loading firmware file '%s'.\n", fw_name); retval = request_firmware(&fw, fw_name, device); @@ -1892,9 +2112,11 @@ if (!fw || !fw->size || !fw->data) { ERROR(rt2x00dev, "Failed to read Firmware.\n"); ---- a/drivers/net/wireless/rtlwifi/rtl8192ce/sw.c -+++ b/drivers/net/wireless/rtlwifi/rtl8192ce/sw.c -@@ -174,11 +174,8 @@ int rtl92c_init_sw_vars(struct ieee80211 +Index: linux-3.2.46/drivers/net/wireless/rtlwifi/rtl8192ce/sw.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/wireless/rtlwifi/rtl8192ce/sw.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtlwifi/rtl8192ce/sw.c 2013-07-26 19:25:24.000000000 +0000 +@@ -174,11 +174,8 @@ fw_name = rtlpriv->cfg->fw_name; } err = request_firmware(&firmware, fw_name, rtlpriv->io.dev); @@ -1907,9 +2129,11 @@ if (firmware->size > 0x4000) { RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, ("Firmware is too big!\n")); ---- a/drivers/net/wireless/rtlwifi/rtl8192cu/sw.c -+++ b/drivers/net/wireless/rtlwifi/rtl8192cu/sw.c -@@ -71,11 +71,8 @@ static int rtl92cu_init_sw_vars(struct i +Index: linux-3.2.46/drivers/net/wireless/rtlwifi/rtl8192cu/sw.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/wireless/rtlwifi/rtl8192cu/sw.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtlwifi/rtl8192cu/sw.c 2013-07-26 19:25:24.000000000 +0000 +@@ -71,11 +71,8 @@ /* request fw */ err = request_firmware(&firmware, rtlpriv->cfg->fw_name, rtlpriv->io.dev); @@ -1922,9 +2146,11 @@ if (firmware->size > 0x4000) { RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, ("Firmware is too big!\n")); ---- a/drivers/net/wireless/rtlwifi/rtl8192de/sw.c -+++ b/drivers/net/wireless/rtlwifi/rtl8192de/sw.c -@@ -186,11 +186,8 @@ static int rtl92d_init_sw_vars(struct ie +Index: linux-3.2.46/drivers/net/wireless/rtlwifi/rtl8192de/sw.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/wireless/rtlwifi/rtl8192de/sw.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtlwifi/rtl8192de/sw.c 2013-07-26 19:25:24.000000000 +0000 +@@ -186,11 +186,8 @@ /* request fw */ err = request_firmware(&firmware, rtlpriv->cfg->fw_name, rtlpriv->io.dev); @@ -1937,9 +2163,11 @@ if (firmware->size > 0x8000) { RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, ("Firmware is too big!\n")); ---- a/drivers/net/wireless/rtlwifi/rtl8192se/sw.c -+++ b/drivers/net/wireless/rtlwifi/rtl8192se/sw.c -@@ -197,11 +197,8 @@ static int rtl92s_init_sw_vars(struct ie +Index: linux-3.2.46/drivers/net/wireless/rtlwifi/rtl8192se/sw.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/wireless/rtlwifi/rtl8192se/sw.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtlwifi/rtl8192se/sw.c 2013-07-26 19:25:24.000000000 +0000 +@@ -197,11 +197,8 @@ /* request fw */ err = request_firmware(&firmware, rtlpriv->cfg->fw_name, rtlpriv->io.dev); @@ -1952,9 +2180,11 @@ if (firmware->size > sizeof(struct rt_firmware)) { RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, ("Firmware is too big!\n")); ---- a/drivers/net/wireless/wl1251/main.c -+++ b/drivers/net/wireless/wl1251/main.c -@@ -70,10 +70,8 @@ static int wl1251_fetch_firmware(struct +Index: linux-3.2.46/drivers/net/wireless/wl1251/main.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/wireless/wl1251/main.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/wl1251/main.c 2013-07-26 19:25:24.000000000 +0000 +@@ -70,10 +70,8 @@ ret = request_firmware(&fw, WL1251_FW_NAME, dev); @@ -1966,7 +2196,7 @@ if (fw->size % 4) { wl1251_error("firmware size is not multiple of 32 bits: %zu", -@@ -109,10 +107,8 @@ static int wl1251_fetch_nvs(struct wl125 +@@ -109,10 +107,8 @@ ret = request_firmware(&fw, WL1251_NVS_NAME, dev); @@ -1978,9 +2208,11 @@ if (fw->size % 4) { wl1251_error("nvs size is not multiple of 32 bits: %zu", ---- a/drivers/net/wireless/wl12xx/main.c -+++ b/drivers/net/wireless/wl12xx/main.c -@@ -1071,10 +1071,8 @@ static int wl1271_fetch_firmware(struct +Index: linux-3.2.46/drivers/net/wireless/wl12xx/main.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/wireless/wl12xx/main.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/wl12xx/main.c 2013-07-26 19:25:24.000000000 +0000 +@@ -1071,10 +1071,8 @@ ret = request_firmware(&fw, fw_name, wl1271_wl_to_dev(wl)); @@ -1992,7 +2224,7 @@ if (fw->size % 4) { wl1271_error("firmware size is not multiple of 32 bits: %zu", -@@ -1109,10 +1107,8 @@ static int wl1271_fetch_nvs(struct wl127 +@@ -1109,10 +1107,8 @@ ret = request_firmware(&fw, WL12XX_NVS_NAME, wl1271_wl_to_dev(wl)); @@ -2004,9 +2236,11 @@ wl->nvs = kmemdup(fw->data, fw->size, GFP_KERNEL); ---- a/drivers/net/wireless/wl12xx/sdio_test.c -+++ b/drivers/net/wireless/wl12xx/sdio_test.c -@@ -206,10 +206,8 @@ static int wl1271_fetch_firmware(struct +Index: linux-3.2.46/drivers/net/wireless/wl12xx/sdio_test.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/wireless/wl12xx/sdio_test.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/wl12xx/sdio_test.c 2013-07-26 19:25:24.000000000 +0000 +@@ -206,10 +206,8 @@ ret = request_firmware(&fw, WL127X_FW_NAME, wl1271_wl_to_dev(wl)); @@ -2018,7 +2252,7 @@ if (fw->size % 4) { wl1271_error("firmware size is not multiple of 32 bits: %zu", -@@ -244,10 +242,8 @@ static int wl1271_fetch_nvs(struct wl127 +@@ -244,10 +242,8 @@ ret = request_firmware(&fw, WL12XX_NVS_NAME, wl1271_wl_to_dev(wl)); @@ -2030,9 +2264,11 @@ wl->nvs = kmemdup(fw->data, fw->size, GFP_KERNEL); ---- a/drivers/net/wireless/zd1201.c -+++ b/drivers/net/wireless/zd1201.c -@@ -65,8 +65,6 @@ static int zd1201_fw_upload(struct usb_d +Index: linux-3.2.46/drivers/net/wireless/zd1201.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/wireless/zd1201.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/zd1201.c 2013-07-26 19:25:24.000000000 +0000 +@@ -65,8 +65,6 @@ err = request_firmware(&fw_entry, fwfile, &dev->dev); if (err) { @@ -2041,9 +2277,11 @@ dev_err(&dev->dev, "Goto http://linux-lc100020.sourceforge.net for more info.\n"); return err; } ---- a/drivers/net/wireless/zd1211rw/zd_usb.c -+++ b/drivers/net/wireless/zd1211rw/zd_usb.c -@@ -121,16 +121,9 @@ static void int_urb_complete(struct urb +Index: linux-3.2.46/drivers/net/wireless/zd1211rw/zd_usb.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/wireless/zd1211rw/zd_usb.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/zd1211rw/zd_usb.c 2013-07-26 19:25:24.000000000 +0000 +@@ -121,16 +121,9 @@ static int request_fw_file( const struct firmware **fw, const char *name, struct device *device) { @@ -2061,9 +2299,11 @@ } static inline u16 get_bcdDevice(const struct usb_device *udev) ---- a/drivers/scsi/advansys.c -+++ b/drivers/scsi/advansys.c -@@ -4792,8 +4792,6 @@ static ushort AscInitAsc1000Driver(ASC_D +Index: linux-3.2.46/drivers/scsi/advansys.c +=================================================================== +--- linux-3.2.46.orig/drivers/scsi/advansys.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/scsi/advansys.c 2013-07-26 19:25:24.000000000 +0000 +@@ -4792,8 +4792,6 @@ err = request_firmware(&fw, fwname, asc_dvc->drv_ptr->dev); if (err) { @@ -2072,7 +2312,7 @@ asc_dvc->err_code |= ASC_IERR_MCODE_CHKSUM; return err; } -@@ -5125,8 +5123,6 @@ static int AdvInitAsc3550Driver(ADV_DVC_ +@@ -5125,8 +5123,6 @@ err = request_firmware(&fw, fwname, asc_dvc->drv_ptr->dev); if (err) { @@ -2081,7 +2321,7 @@ asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM; return err; } -@@ -5641,8 +5637,6 @@ static int AdvInitAsc38C0800Driver(ADV_D +@@ -5641,8 +5637,6 @@ err = request_firmware(&fw, fwname, asc_dvc->drv_ptr->dev); if (err) { @@ -2090,7 +2330,7 @@ asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM; return err; } -@@ -6143,8 +6137,6 @@ static int AdvInitAsc38C1600Driver(ADV_D +@@ -6143,8 +6137,6 @@ err = request_firmware(&fw, fwname, asc_dvc->drv_ptr->dev); if (err) { @@ -2099,9 +2339,11 @@ asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM; return err; } ---- a/drivers/scsi/aic94xx/aic94xx_init.c -+++ b/drivers/scsi/aic94xx/aic94xx_init.c -@@ -399,8 +399,6 @@ static ssize_t asd_store_update_bios(str +Index: linux-3.2.46/drivers/scsi/aic94xx/aic94xx_init.c +=================================================================== +--- linux-3.2.46.orig/drivers/scsi/aic94xx/aic94xx_init.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/scsi/aic94xx/aic94xx_init.c 2013-07-26 19:25:25.000000000 +0000 +@@ -399,8 +399,6 @@ filename_ptr, &asd_ha->pcidev->dev); if (err) { @@ -2110,9 +2352,11 @@ err = FAIL_OPEN_BIOS_FILE; goto out1; } ---- a/drivers/scsi/aic94xx/aic94xx_seq.c -+++ b/drivers/scsi/aic94xx/aic94xx_seq.c -@@ -1318,11 +1318,8 @@ int asd_init_seqs(struct asd_ha_struct * +Index: linux-3.2.46/drivers/scsi/aic94xx/aic94xx_seq.c +=================================================================== +--- linux-3.2.46.orig/drivers/scsi/aic94xx/aic94xx_seq.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/scsi/aic94xx/aic94xx_seq.c 2013-07-26 19:25:25.000000000 +0000 +@@ -1318,11 +1318,8 @@ err = asd_request_firmware(asd_ha); @@ -2125,9 +2369,11 @@ err = asd_seq_download_seqs(asd_ha); if (err) { ---- a/drivers/scsi/bfa/bfad.c -+++ b/drivers/scsi/bfa/bfad.c -@@ -1592,7 +1592,6 @@ bfad_read_firmware(struct pci_dev *pdev, +Index: linux-3.2.46/drivers/scsi/bfa/bfad.c +=================================================================== +--- linux-3.2.46.orig/drivers/scsi/bfa/bfad.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/scsi/bfa/bfad.c 2013-07-26 19:25:25.000000000 +0000 +@@ -1592,7 +1592,6 @@ const struct firmware *fw; if (request_firmware(&fw, fw_name, &pdev->dev)) { @@ -2135,9 +2381,11 @@ *bfi_image = NULL; goto out; } ---- a/drivers/scsi/ipr.c -+++ b/drivers/scsi/ipr.c -@@ -3744,10 +3744,8 @@ static ssize_t ipr_store_update_fw(struc +Index: linux-3.2.46/drivers/scsi/ipr.c +=================================================================== +--- linux-3.2.46.orig/drivers/scsi/ipr.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/scsi/ipr.c 2013-07-26 19:25:25.000000000 +0000 +@@ -3744,10 +3744,8 @@ len = snprintf(fname, 99, "%s", buf); fname[len-1] = '\0'; @@ -2149,9 +2397,11 @@ image_hdr = (struct ipr_ucode_image_header *)fw_entry->data; ---- a/drivers/scsi/pm8001/pm8001_ctl.c -+++ b/drivers/scsi/pm8001/pm8001_ctl.c -@@ -502,9 +502,6 @@ static ssize_t pm8001_store_update_fw(st +Index: linux-3.2.46/drivers/scsi/pm8001/pm8001_ctl.c +=================================================================== +--- linux-3.2.46.orig/drivers/scsi/pm8001/pm8001_ctl.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/scsi/pm8001/pm8001_ctl.c 2013-07-26 19:25:25.000000000 +0000 +@@ -502,9 +502,6 @@ pm8001_ha->dev); if (err) { @@ -2161,9 +2411,11 @@ err = FAIL_OPEN_BIOS_FILE; goto out1; } ---- a/drivers/scsi/qla1280.c -+++ b/drivers/scsi/qla1280.c -@@ -1561,8 +1561,6 @@ qla1280_request_firmware(struct scsi_qla +Index: linux-3.2.46/drivers/scsi/qla1280.c +=================================================================== +--- linux-3.2.46.orig/drivers/scsi/qla1280.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/scsi/qla1280.c 2013-07-26 19:25:25.000000000 +0000 +@@ -1561,8 +1561,6 @@ err = request_firmware(&fw, fwname, &ha->pdev->dev); if (err) { @@ -2172,9 +2424,11 @@ fw = ERR_PTR(err); goto unlock; } ---- a/drivers/scsi/qla2xxx/qla_init.c -+++ b/drivers/scsi/qla2xxx/qla_init.c -@@ -4725,8 +4725,6 @@ qla2x00_load_risc(scsi_qla_host_t *vha, +Index: linux-3.2.46/drivers/scsi/qla2xxx/qla_init.c +=================================================================== +--- linux-3.2.46.orig/drivers/scsi/qla2xxx/qla_init.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/scsi/qla2xxx/qla_init.c 2013-07-26 19:25:25.000000000 +0000 +@@ -4725,8 +4725,6 @@ /* Load firmware blob. */ blob = qla2x00_request_firmware(vha); if (!blob) { @@ -2183,7 +2437,7 @@ ql_log(ql_log_info, vha, 0x0084, "Firmware images can be retrieved from: "QLA_FW_URL ".\n"); return QLA_FUNCTION_FAILED; -@@ -4827,8 +4825,6 @@ qla24xx_load_risc_blob(scsi_qla_host_t * +@@ -4827,8 +4825,6 @@ /* Load firmware blob. */ blob = qla2x00_request_firmware(vha); if (!blob) { @@ -2192,9 +2446,11 @@ ql_log(ql_log_warn, vha, 0x0091, "Firmware images can be retrieved from: " QLA_FW_URL ".\n"); ---- a/drivers/scsi/qla2xxx/qla_nx.c -+++ b/drivers/scsi/qla2xxx/qla_nx.c -@@ -2466,11 +2466,8 @@ try_blob_fw: +Index: linux-3.2.46/drivers/scsi/qla2xxx/qla_nx.c +=================================================================== +--- linux-3.2.46.orig/drivers/scsi/qla2xxx/qla_nx.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/scsi/qla2xxx/qla_nx.c 2013-07-26 19:25:25.000000000 +0000 +@@ -2466,11 +2466,8 @@ /* Load firmware blob. */ blob = ha->hablob = qla2x00_request_firmware(vha); @@ -2207,9 +2463,11 @@ /* Validating firmware blob */ if (qla82xx_validate_firmware_blob(vha, ---- a/drivers/scsi/qla2xxx/qla_os.c -+++ b/drivers/scsi/qla2xxx/qla_os.c -@@ -3967,8 +3967,6 @@ qla2x00_request_firmware(scsi_qla_host_t +Index: linux-3.2.46/drivers/scsi/qla2xxx/qla_os.c +=================================================================== +--- linux-3.2.46.orig/drivers/scsi/qla2xxx/qla_os.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/scsi/qla2xxx/qla_os.c 2013-07-26 19:25:25.000000000 +0000 +@@ -3967,8 +3967,6 @@ goto out; if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) { @@ -2218,9 +2476,11 @@ blob->fw = NULL; blob = NULL; goto out; ---- a/drivers/scsi/qlogicpti.c -+++ b/drivers/scsi/qlogicpti.c -@@ -476,11 +476,8 @@ static int __devinit qlogicpti_load_firm +Index: linux-3.2.46/drivers/scsi/qlogicpti.c +=================================================================== +--- linux-3.2.46.orig/drivers/scsi/qlogicpti.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/scsi/qlogicpti.c 2013-07-26 19:25:25.000000000 +0000 +@@ -476,11 +476,8 @@ int i, timeout; err = request_firmware(&fw, fwname, &qpti->op->dev); @@ -2233,9 +2493,11 @@ if (fw->size % 2) { printk(KERN_ERR "Bogus length %zu in image \"%s\"\n", fw->size, fwname); ---- a/drivers/staging/comedi/drivers/usbdux.c -+++ b/drivers/staging/comedi/drivers/usbdux.c -@@ -2307,11 +2307,8 @@ static void usbdux_firmware_request_comp +Index: linux-3.2.46/drivers/staging/comedi/drivers/usbdux.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/comedi/drivers/usbdux.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/staging/comedi/drivers/usbdux.c 2013-07-26 19:25:25.000000000 +0000 +@@ -2307,11 +2307,8 @@ struct usb_device *usbdev = usbduxsub_tmp->usbdev; int ret; @@ -2248,9 +2510,11 @@ /* * we need to upload the firmware here because fw will be ---- a/drivers/staging/comedi/drivers/usbduxsigma.c -+++ b/drivers/staging/comedi/drivers/usbduxsigma.c -@@ -2312,11 +2312,8 @@ static void usbdux_firmware_request_comp +Index: linux-3.2.46/drivers/staging/comedi/drivers/usbduxsigma.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/comedi/drivers/usbduxsigma.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/staging/comedi/drivers/usbduxsigma.c 2013-07-26 19:25:25.000000000 +0000 +@@ -2312,11 +2312,8 @@ struct usb_device *usbdev = usbduxsub_tmp->usbdev; int ret; @@ -2263,9 +2527,11 @@ /* * we need to upload the firmware here because fw will be ---- a/drivers/staging/ft1000/ft1000-pcmcia/ft1000_hw.c -+++ b/drivers/staging/ft1000/ft1000-pcmcia/ft1000_hw.c -@@ -2194,16 +2194,12 @@ struct net_device *init_ft1000_card(stru +Index: linux-3.2.46/drivers/staging/ft1000/ft1000-pcmcia/ft1000_hw.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/ft1000/ft1000-pcmcia/ft1000_hw.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/staging/ft1000/ft1000-pcmcia/ft1000_hw.c 2013-07-26 19:25:25.000000000 +0000 +@@ -2194,16 +2194,12 @@ info->AsicID = ft1000_read_reg(dev, FT1000_REG_ASIC_ID); if (info->AsicID == ELECTRABUZZ_ID) { DEBUG(0, "ft1000_hw: ELECTRABUZZ ASIC\n"); @@ -2284,9 +2550,11 @@ } ft1000_enable_interrupts(dev); ---- a/drivers/staging/ft1000/ft1000-usb/ft1000_usb.c -+++ b/drivers/staging/ft1000/ft1000-usb/ft1000_usb.c -@@ -139,10 +139,8 @@ static int ft1000_probe(struct usb_inter +Index: linux-3.2.46/drivers/staging/ft1000/ft1000-usb/ft1000_usb.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/ft1000/ft1000-usb/ft1000_usb.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/staging/ft1000/ft1000-usb/ft1000_usb.c 2013-07-26 19:25:25.000000000 +0000 +@@ -139,10 +139,8 @@ ft1000dev->bulk_out_endpointAddr); ret = request_firmware(&dsp_fw, "ft3000.img", &dev->dev); @@ -2298,9 +2566,11 @@ size = max_t(uint, dsp_fw->size, 4096); pFileStart = kmalloc(size, GFP_KERNEL); ---- a/drivers/staging/intel_sst/intel_sst_drv_interface.c -+++ b/drivers/staging/intel_sst/intel_sst_drv_interface.c -@@ -66,10 +66,8 @@ int sst_download_fw(void) +Index: linux-3.2.46/drivers/staging/intel_sst/intel_sst_drv_interface.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/intel_sst/intel_sst_drv_interface.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/staging/intel_sst/intel_sst_drv_interface.c 2013-07-26 19:25:25.000000000 +0000 +@@ -66,10 +66,8 @@ pr_debug("Downloading %s FW now...\n", name); retval = request_firmware(&fw_sst, name, &sst_drv_ctx->pci->dev); @@ -2312,9 +2582,11 @@ sst_drv_ctx->alloc_block[0].sst_id = FW_DWNL_ID; sst_drv_ctx->alloc_block[0].ops_block.condition = false; retval = sst_load_fw(fw_sst, NULL); ---- a/drivers/staging/intel_sst/intel_sst_dsp.c -+++ b/drivers/staging/intel_sst/intel_sst_dsp.c -@@ -471,10 +471,8 @@ int sst_load_library(struct snd_sst_lib_ +Index: linux-3.2.46/drivers/staging/intel_sst/intel_sst_dsp.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/intel_sst/intel_sst_dsp.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/staging/intel_sst/intel_sst_dsp.c 2013-07-26 19:25:25.000000000 +0000 +@@ -471,10 +471,8 @@ pr_debug("Requesting %s\n", buf); error = request_firmware(&fw_lib, buf, &sst_drv_ctx->pci->dev); @@ -2326,9 +2598,11 @@ error = sst_validate_library(fw_lib, &lib->slot_info, &entry_point); if (error) goto wake_free; ---- a/drivers/staging/media/as102/as102_fw.c -+++ b/drivers/staging/media/as102/as102_fw.c -@@ -197,11 +197,8 @@ int as102_fw_upload(struct as102_bus_ada +Index: linux-3.2.46/drivers/staging/media/as102/as102_fw.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/media/as102/as102_fw.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/staging/media/as102/as102_fw.c 2013-07-26 19:25:25.000000000 +0000 +@@ -197,11 +197,8 @@ /* request kernel to locate firmware file: part1 */ errno = request_firmware(&firmware, fw1, &dev->dev); @@ -2341,7 +2615,7 @@ /* initiate firmware upload */ errno = as102_firmware_upload(bus_adap, cmd_buf, firmware); -@@ -220,11 +217,8 @@ int as102_fw_upload(struct as102_bus_ada +@@ -220,11 +217,8 @@ /* request kernel to locate firmware file: part2 */ errno = request_firmware(&firmware, fw2, &dev->dev); @@ -2354,9 +2628,11 @@ /* initiate firmware upload */ errno = as102_firmware_upload(bus_adap, cmd_buf, firmware); ---- a/drivers/staging/media/go7007/go7007-driver.c -+++ b/drivers/staging/media/go7007/go7007-driver.c -@@ -97,11 +97,8 @@ static int go7007_load_encoder(struct go +Index: linux-3.2.46/drivers/staging/media/go7007/go7007-driver.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/media/go7007/go7007-driver.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/staging/media/go7007/go7007-driver.c 2013-07-26 19:25:25.000000000 +0000 +@@ -97,11 +97,8 @@ int fw_len, rv = 0; u16 intr_val, intr_data; @@ -2369,9 +2645,11 @@ if (fw_entry->size < 16 || memcmp(fw_entry->data, "WISGO7007FW", 11)) { v4l2_err(go, "file \"%s\" does not appear to be " "go7007 firmware\n", fw_name); ---- a/drivers/staging/media/go7007/go7007-fw.c -+++ b/drivers/staging/media/go7007/go7007-fw.c -@@ -1576,12 +1576,8 @@ int go7007_construct_fw_image(struct go7 +Index: linux-3.2.46/drivers/staging/media/go7007/go7007-fw.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/media/go7007/go7007-fw.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/staging/media/go7007/go7007-fw.c 2013-07-26 19:25:25.000000000 +0000 +@@ -1576,12 +1576,8 @@ default: return -1; } @@ -2385,9 +2663,11 @@ code = kzalloc(codespace * 2, GFP_KERNEL); if (code == NULL) { printk(KERN_ERR "go7007: unable to allocate %d bytes for " ---- a/drivers/staging/media/go7007/s2250-loader.c -+++ b/drivers/staging/media/go7007/s2250-loader.c -@@ -98,12 +98,8 @@ static int s2250loader_probe(struct usb_ +Index: linux-3.2.46/drivers/staging/media/go7007/s2250-loader.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/media/go7007/s2250-loader.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/staging/media/go7007/s2250-loader.c 2013-07-26 19:25:25.000000000 +0000 +@@ -98,12 +98,8 @@ mutex_unlock(&s2250_dev_table_mutex); @@ -2401,7 +2681,7 @@ ret = usb_cypress_load_firmware(usbdev, fw, CYPRESS_FX2); release_firmware(fw); if (0 != ret) { -@@ -111,12 +107,8 @@ static int s2250loader_probe(struct usb_ +@@ -111,12 +107,8 @@ goto failed2; } @@ -2415,9 +2695,11 @@ ret = usb_cypress_load_firmware(usbdev, fw, CYPRESS_FX2); release_firmware(fw); if (0 != ret) { ---- a/drivers/staging/media/lirc/lirc_zilog.c -+++ b/drivers/staging/media/lirc/lirc_zilog.c -@@ -765,8 +765,6 @@ static int fw_load(struct IR_tx *tx) +Index: linux-3.2.46/drivers/staging/media/lirc/lirc_zilog.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/media/lirc/lirc_zilog.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/staging/media/lirc/lirc_zilog.c 2013-07-26 19:25:25.000000000 +0000 +@@ -765,8 +765,6 @@ /* Request codeset data file */ ret = request_firmware(&fw_entry, "haup-ir-blaster.bin", tx->ir->l.dev); if (ret != 0) { @@ -2426,9 +2708,11 @@ ret = ret < 0 ? ret : -EFAULT; goto out; } ---- a/drivers/staging/rtl8192u/r819xU_firmware.c -+++ b/drivers/staging/rtl8192u/r819xU_firmware.c -@@ -284,10 +284,8 @@ bool init_firmware(struct net_device *de +Index: linux-3.2.46/drivers/staging/rtl8192u/r819xU_firmware.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/rtl8192u/r819xU_firmware.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/staging/rtl8192u/r819xU_firmware.c 2013-07-26 19:25:25.000000000 +0000 +@@ -284,10 +284,8 @@ */ if(rst_opt == OPT_SYSTEM_RESET) { rc = request_firmware(&fw_entry, fw_name[init_step],&priv->udev->dev); @@ -2440,9 +2724,11 @@ if(fw_entry->size > sizeof(pfirmware->firmware_buf)) { RT_TRACE(COMP_ERR, "img file size exceed the container buffer fail!\n"); ---- a/drivers/staging/rtl8712/hal_init.c -+++ b/drivers/staging/rtl8712/hal_init.c -@@ -50,7 +50,6 @@ static void rtl871x_load_fw_cb(const str +Index: linux-3.2.46/drivers/staging/rtl8712/hal_init.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/rtl8712/hal_init.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/staging/rtl8712/hal_init.c 2013-07-26 19:25:25.000000000 +0000 +@@ -50,7 +50,6 @@ if (!firmware) { struct usb_device *udev = padapter->dvobjpriv.pusbdev; struct usb_interface *pusb_intf = padapter->pusb_intf; @@ -2450,9 +2736,11 @@ padapter->fw_found = false; usb_put_dev(udev); usb_set_intfdata(pusb_intf, NULL); ---- a/drivers/staging/slicoss/slicoss.c -+++ b/drivers/staging/slicoss/slicoss.c -@@ -519,11 +519,8 @@ static int slic_card_download_gbrcv(stru +Index: linux-3.2.46/drivers/staging/slicoss/slicoss.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/slicoss/slicoss.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/staging/slicoss/slicoss.c 2013-07-26 19:25:25.000000000 +0000 +@@ -519,11 +519,8 @@ } ret = request_firmware(&fw, file, &adapter->pcidev->dev); @@ -2465,7 +2753,7 @@ rcvucodelen = *(u32 *)(fw->data + index); index += 4; -@@ -597,11 +594,8 @@ static int slic_card_download(struct ada +@@ -597,11 +594,8 @@ break; } ret = request_firmware(&fw, file, &adapter->pcidev->dev); @@ -2478,9 +2766,11 @@ numsects = *(u32 *)(fw->data + index); index += 4; ASSERT(numsects <= 3); ---- a/drivers/staging/vt6656/firmware.c -+++ b/drivers/staging/vt6656/firmware.c -@@ -76,11 +76,8 @@ FIRMWAREbDownload( +Index: linux-3.2.46/drivers/staging/vt6656/firmware.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/vt6656/firmware.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/staging/vt6656/firmware.c 2013-07-26 19:25:25.000000000 +0000 +@@ -76,11 +76,8 @@ int rc; rc = request_firmware(&pDevice->firmware, FIRMWARE_NAME, dev); @@ -2493,9 +2783,11 @@ } fw = pDevice->firmware; ---- a/drivers/tty/cyclades.c -+++ b/drivers/tty/cyclades.c -@@ -3543,10 +3543,8 @@ static int __devinit cyz_load_fw(struct +Index: linux-3.2.46/drivers/tty/cyclades.c +=================================================================== +--- linux-3.2.46.orig/drivers/tty/cyclades.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/tty/cyclades.c 2013-07-26 19:25:26.000000000 +0000 +@@ -3543,10 +3543,8 @@ int retval; retval = request_firmware(&fw, "cyzfirm.bin", &pdev->dev); @@ -2507,9 +2799,11 @@ /* Check whether the firmware is already loaded and running. If positive, skip this board */ ---- a/drivers/tty/moxa.c -+++ b/drivers/tty/moxa.c -@@ -867,13 +867,8 @@ static int moxa_init_board(struct moxa_b +Index: linux-3.2.46/drivers/tty/moxa.c +=================================================================== +--- linux-3.2.46.orig/drivers/tty/moxa.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/tty/moxa.c 2013-07-26 19:25:26.000000000 +0000 +@@ -867,13 +867,8 @@ } ret = request_firmware(&fw, file, dev); @@ -2524,9 +2818,11 @@ ret = moxa_load_fw(brd, fw); ---- a/drivers/tty/serial/icom.c -+++ b/drivers/tty/serial/icom.c -@@ -374,7 +374,6 @@ static void load_code(struct icom_port * +Index: linux-3.2.46/drivers/tty/serial/icom.c +=================================================================== +--- linux-3.2.46.orig/drivers/tty/serial/icom.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/tty/serial/icom.c 2013-07-26 19:25:26.000000000 +0000 +@@ -374,7 +374,6 @@ /* Load Call Setup into Adapter */ if (request_firmware(&fw, "icom_call_setup.bin", &dev->dev) < 0) { @@ -2534,7 +2830,7 @@ status = -1; goto load_code_exit; } -@@ -394,7 +393,6 @@ static void load_code(struct icom_port * +@@ -394,7 +393,6 @@ /* Load Resident DCE portion of Adapter */ if (request_firmware(&fw, "icom_res_dce.bin", &dev->dev) < 0) { @@ -2542,7 +2838,7 @@ status = -1; goto load_code_exit; } -@@ -439,7 +437,6 @@ static void load_code(struct icom_port * +@@ -439,7 +437,6 @@ } if (request_firmware(&fw, "icom_asc.bin", &dev->dev) < 0) { @@ -2550,9 +2846,11 @@ status = -1; goto load_code_exit; } ---- a/drivers/tty/serial/ucc_uart.c -+++ b/drivers/tty/serial/ucc_uart.c -@@ -1173,10 +1173,8 @@ static void uart_firmware_cont(const str +Index: linux-3.2.46/drivers/tty/serial/ucc_uart.c +=================================================================== +--- linux-3.2.46.orig/drivers/tty/serial/ucc_uart.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/tty/serial/ucc_uart.c 2013-07-26 19:25:26.000000000 +0000 +@@ -1173,10 +1173,8 @@ struct device *dev = context; int ret; @@ -2564,9 +2862,11 @@ firmware = (struct qe_firmware *) fw->data; ---- a/drivers/usb/atm/cxacru.c -+++ b/drivers/usb/atm/cxacru.c -@@ -1081,8 +1081,6 @@ static int cxacru_find_firmware(struct c +Index: linux-3.2.46/drivers/usb/atm/cxacru.c +=================================================================== +--- linux-3.2.46.orig/drivers/usb/atm/cxacru.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/usb/atm/cxacru.c 2013-07-26 19:25:26.000000000 +0000 +@@ -1082,8 +1082,6 @@ return -ENOENT; } @@ -2575,9 +2875,11 @@ return 0; } ---- a/drivers/usb/atm/ueagle-atm.c -+++ b/drivers/usb/atm/ueagle-atm.c -@@ -622,10 +622,8 @@ static void uea_upload_pre_firmware(cons +Index: linux-3.2.46/drivers/usb/atm/ueagle-atm.c +=================================================================== +--- linux-3.2.46.orig/drivers/usb/atm/ueagle-atm.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/usb/atm/ueagle-atm.c 2013-07-26 19:25:26.000000000 +0000 +@@ -622,10 +622,8 @@ int ret, size; uea_enters(usb); @@ -2589,7 +2891,7 @@ pfw = fw_entry->data; size = fw_entry->size; -@@ -720,10 +718,6 @@ static int uea_load_firmware(struct usb_ +@@ -720,10 +718,6 @@ ret = request_firmware_nowait(THIS_MODULE, 1, fw_name, &usb->dev, GFP_KERNEL, usb, uea_upload_pre_firmware); @@ -2600,7 +2902,7 @@ uea_leaves(usb); return ret; -@@ -885,12 +879,8 @@ static int request_dsp(struct uea_softc +@@ -885,12 +879,8 @@ } ret = request_firmware(&sc->dsp_firm, dsp_name, &sc->usb_dev->dev); @@ -2614,7 +2916,7 @@ if (UEA_CHIP_VERSION(sc) == EAGLE_IV) ret = check_dsp_e4(sc->dsp_firm->data, sc->dsp_firm->size); -@@ -1607,12 +1597,8 @@ static int request_cmvs_old(struct uea_s +@@ -1607,12 +1597,8 @@ cmvs_file_name(sc, cmv_name, 1); ret = request_firmware(fw, cmv_name, &sc->usb_dev->dev); @@ -2628,7 +2930,7 @@ data = (u8 *) (*fw)->data; size = (*fw)->size; -@@ -1649,9 +1635,6 @@ static int request_cmvs(struct uea_softc +@@ -1649,9 +1635,6 @@ "try to get older cmvs\n", cmv_name); return request_cmvs_old(sc, cmvs, fw); } @@ -2638,7 +2940,7 @@ return ret; } -@@ -1934,11 +1917,8 @@ static int load_XILINX_firmware(struct u +@@ -1934,11 +1917,8 @@ uea_enters(INS_TO_USBDEV(sc)); ret = request_firmware(&fw_entry, fw_name, &sc->usb_dev->dev); @@ -2651,9 +2953,11 @@ pfw = fw_entry->data; size = fw_entry->size; ---- a/drivers/usb/misc/emi26.c -+++ b/drivers/usb/misc/emi26.c -@@ -96,21 +96,17 @@ static int emi26_load_firmware (struct u +Index: linux-3.2.46/drivers/usb/misc/emi26.c +=================================================================== +--- linux-3.2.46.orig/drivers/usb/misc/emi26.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/usb/misc/emi26.c 2013-07-26 19:25:26.000000000 +0000 +@@ -96,21 +96,17 @@ err = request_ihex_firmware(&loader_fw, "emi26/loader.fw", &dev->dev); if (err) @@ -2678,9 +2982,11 @@ /* Assert reset (stop the CPU in the EMI) */ err = emi26_set_reset(dev,1); ---- a/drivers/usb/misc/emi62.c -+++ b/drivers/usb/misc/emi62.c -@@ -105,19 +105,16 @@ static int emi62_load_firmware (struct u +Index: linux-3.2.46/drivers/usb/misc/emi62.c +=================================================================== +--- linux-3.2.46.orig/drivers/usb/misc/emi62.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/usb/misc/emi62.c 2013-07-26 19:25:26.000000000 +0000 +@@ -105,19 +105,16 @@ err = request_ihex_firmware(&loader_fw, "emi62/loader.fw", &dev->dev); if (err) @@ -2703,9 +3009,11 @@ /* Assert reset (stop the CPU in the EMI) */ err = emi62_set_reset(dev,1); ---- a/drivers/usb/misc/isight_firmware.c -+++ b/drivers/usb/misc/isight_firmware.c -@@ -48,7 +48,6 @@ static int isight_firmware_load(struct u +Index: linux-3.2.46/drivers/usb/misc/isight_firmware.c +=================================================================== +--- linux-3.2.46.orig/drivers/usb/misc/isight_firmware.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/usb/misc/isight_firmware.c 2013-07-26 19:25:26.000000000 +0000 +@@ -48,7 +48,6 @@ return -ENOMEM; if (request_firmware(&firmware, "isight.fw", &dev->dev) != 0) { @@ -2713,9 +3021,11 @@ ret = -ENODEV; goto out; } ---- a/drivers/usb/serial/io_edgeport.c -+++ b/drivers/usb/serial/io_edgeport.c -@@ -309,11 +309,8 @@ static void update_edgeport_E2PROM(struc +Index: linux-3.2.46/drivers/usb/serial/io_edgeport.c +=================================================================== +--- linux-3.2.46.orig/drivers/usb/serial/io_edgeport.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/usb/serial/io_edgeport.c 2013-07-26 19:25:26.000000000 +0000 +@@ -308,11 +308,8 @@ response = request_ihex_firmware(&fw, fw_name, &edge_serial->serial->dev->dev); @@ -2728,9 +3038,11 @@ rec = (const struct ihex_binrec *)fw->data; BootMajorVersion = rec->data[0]; ---- a/drivers/usb/serial/io_ti.c -+++ b/drivers/usb/serial/io_ti.c -@@ -870,8 +870,6 @@ static int build_i2c_fw_hdr(__u8 *header +Index: linux-3.2.46/drivers/usb/serial/io_ti.c +=================================================================== +--- linux-3.2.46.orig/drivers/usb/serial/io_ti.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/usb/serial/io_ti.c 2013-07-26 19:25:26.000000000 +0000 +@@ -870,8 +870,6 @@ err = request_firmware(&fw, fw_name, dev); if (err) { @@ -2739,7 +3051,7 @@ kfree(buffer); return err; } -@@ -1436,8 +1434,6 @@ static int download_fw(struct edgeport_s +@@ -1436,8 +1434,6 @@ err = request_firmware(&fw, fw_name, dev); if (err) { @@ -2748,9 +3060,11 @@ kfree(buffer); return err; } ---- a/drivers/usb/serial/keyspan.c -+++ b/drivers/usb/serial/keyspan.c -@@ -1399,10 +1399,8 @@ static int keyspan_fake_startup(struct u +Index: linux-3.2.46/drivers/usb/serial/keyspan.c +=================================================================== +--- linux-3.2.46.orig/drivers/usb/serial/keyspan.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/usb/serial/keyspan.c 2013-07-26 19:25:26.000000000 +0000 +@@ -1399,10 +1399,8 @@ return 1; } @@ -2762,9 +3076,11 @@ dbg("Uploading Keyspan %s firmware.", fw_name); ---- a/drivers/usb/serial/keyspan_pda.c -+++ b/drivers/usb/serial/keyspan_pda.c -@@ -765,11 +765,8 @@ static int keyspan_pda_fake_startup(stru +Index: linux-3.2.46/drivers/usb/serial/keyspan_pda.c +=================================================================== +--- linux-3.2.46.orig/drivers/usb/serial/keyspan_pda.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/usb/serial/keyspan_pda.c 2013-07-26 19:25:26.000000000 +0000 +@@ -765,11 +765,8 @@ __func__); return -ENODEV; } @@ -2777,9 +3093,11 @@ record = (const struct ihex_binrec *)fw->data; while (record) { ---- a/drivers/usb/serial/ti_usb_3410_5052.c -+++ b/drivers/usb/serial/ti_usb_3410_5052.c -@@ -1743,10 +1743,8 @@ static int ti_download_firmware(struct t +Index: linux-3.2.46/drivers/usb/serial/ti_usb_3410_5052.c +=================================================================== +--- linux-3.2.46.orig/drivers/usb/serial/ti_usb_3410_5052.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/usb/serial/ti_usb_3410_5052.c 2013-07-26 19:25:26.000000000 +0000 +@@ -1745,10 +1745,8 @@ } status = request_firmware(&fw_p, buf, &dev->dev); } @@ -2791,9 +3109,11 @@ if (fw_p->size > TI_FIRMWARE_BUF_SIZE) { dev_err(&dev->dev, "%s - firmware too large %zu\n", __func__, fw_p->size); release_firmware(fw_p); ---- a/drivers/usb/serial/whiteheat.c -+++ b/drivers/usb/serial/whiteheat.c -@@ -301,18 +301,11 @@ static int whiteheat_firmware_download(s +Index: linux-3.2.46/drivers/usb/serial/whiteheat.c +=================================================================== +--- linux-3.2.46.orig/drivers/usb/serial/whiteheat.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/usb/serial/whiteheat.c 2013-07-26 19:25:26.000000000 +0000 +@@ -301,18 +301,11 @@ dbg("%s", __func__); if (request_ihex_firmware(&firmware_fw, "whiteheat.fw", @@ -2814,9 +3134,11 @@ ret = 0; response = ezusb_set_reset (serial, 1); ---- a/drivers/video/broadsheetfb.c -+++ b/drivers/video/broadsheetfb.c -@@ -741,10 +741,8 @@ static ssize_t broadsheet_loadstore_wave +Index: linux-3.2.46/drivers/video/broadsheetfb.c +=================================================================== +--- linux-3.2.46.orig/drivers/video/broadsheetfb.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/video/broadsheetfb.c 2013-07-26 19:25:26.000000000 +0000 +@@ -741,10 +741,8 @@ return -EINVAL; err = request_firmware(&fw_entry, "broadsheet.wbf", dev); @@ -2828,9 +3150,11 @@ /* try to enforce reasonable min max on waveform */ if ((fw_entry->size < 8*1024) || (fw_entry->size > 64*1024)) { ---- a/drivers/video/metronomefb.c -+++ b/drivers/video/metronomefb.c -@@ -677,10 +677,8 @@ static int __devinit metronomefb_probe(s +Index: linux-3.2.46/drivers/video/metronomefb.c +=================================================================== +--- linux-3.2.46.orig/drivers/video/metronomefb.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/drivers/video/metronomefb.c 2013-07-26 19:25:26.000000000 +0000 +@@ -677,10 +677,8 @@ a) request the waveform file from userspace b) process waveform and decode into metromem */ retval = request_firmware(&fw_entry, "metronome.wbf", &dev->dev); @@ -2842,9 +3166,11 @@ retval = load_waveform((u8 *) fw_entry->data, fw_entry->size, 3, 31, par); ---- a/sound/drivers/vx/vx_hwdep.c -+++ b/sound/drivers/vx/vx_hwdep.c -@@ -73,10 +73,8 @@ int snd_vx_setup_firmware(struct vx_core +Index: linux-3.2.46/sound/drivers/vx/vx_hwdep.c +=================================================================== +--- linux-3.2.46.orig/sound/drivers/vx/vx_hwdep.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/sound/drivers/vx/vx_hwdep.c 2013-07-26 19:25:26.000000000 +0000 +@@ -73,10 +73,8 @@ if (! fw_files[chip->type][i]) continue; sprintf(path, "vx/%s", fw_files[chip->type][i]); @@ -2856,9 +3182,11 @@ err = chip->ops->load_dsp(chip, i, fw); if (err < 0) { release_firmware(fw); ---- a/sound/isa/msnd/msnd_pinnacle.c -+++ b/sound/isa/msnd/msnd_pinnacle.c -@@ -387,15 +387,11 @@ static int upload_dsp_code(struct snd_ca +Index: linux-3.2.46/sound/isa/msnd/msnd_pinnacle.c +=================================================================== +--- linux-3.2.46.orig/sound/isa/msnd/msnd_pinnacle.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/sound/isa/msnd/msnd_pinnacle.c 2013-07-26 19:25:26.000000000 +0000 +@@ -387,15 +387,11 @@ outb(HPBLKSEL_0, chip->io + HP_BLKS); err = request_firmware(&init_fw, INITCODEFILE, card->dev); @@ -2876,9 +3204,11 @@ memcpy_toio(chip->mappedbase, perm_fw->data, perm_fw->size); if (snd_msnd_upload_host(chip, init_fw->data, init_fw->size) < 0) { ---- a/sound/isa/sscape.c -+++ b/sound/isa/sscape.c -@@ -543,10 +543,8 @@ static int sscape_upload_bootblock(struc +Index: linux-3.2.46/sound/isa/sscape.c +=================================================================== +--- linux-3.2.46.orig/sound/isa/sscape.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/sound/isa/sscape.c 2013-07-26 19:25:26.000000000 +0000 +@@ -543,10 +543,8 @@ int ret; ret = request_firmware(&init_fw, "scope.cod", card->dev); @@ -2890,7 +3220,7 @@ ret = upload_dma_data(sscape, init_fw->data, init_fw->size); release_firmware(init_fw); -@@ -583,11 +581,8 @@ static int sscape_upload_microcode(struc +@@ -583,11 +581,8 @@ snprintf(name, sizeof(name), "sndscape.co%d", version); err = request_firmware(&init_fw, name, card->dev); @@ -2903,9 +3233,11 @@ err = upload_dma_data(sscape, init_fw->data, init_fw->size); if (err == 0) snd_printk(KERN_INFO "sscape: MIDI firmware loaded %d KBs\n", ---- a/sound/isa/wavefront/wavefront_synth.c -+++ b/sound/isa/wavefront/wavefront_synth.c -@@ -1947,10 +1947,8 @@ wavefront_download_firmware (snd_wavefro +Index: linux-3.2.46/sound/isa/wavefront/wavefront_synth.c +=================================================================== +--- linux-3.2.46.orig/sound/isa/wavefront/wavefront_synth.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/sound/isa/wavefront/wavefront_synth.c 2013-07-26 19:25:26.000000000 +0000 +@@ -1947,10 +1947,8 @@ const struct firmware *firmware; err = request_firmware(&firmware, path, dev->card->dev); @@ -2917,9 +3249,11 @@ len = 0; buf = firmware->data; ---- a/sound/pci/asihpi/hpidspcd.c -+++ b/sound/pci/asihpi/hpidspcd.c -@@ -51,9 +51,6 @@ short hpi_dsp_code_open(u32 adapter, voi +Index: linux-3.2.46/sound/pci/asihpi/hpidspcd.c +=================================================================== +--- linux-3.2.46.orig/sound/pci/asihpi/hpidspcd.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/sound/pci/asihpi/hpidspcd.c 2013-07-26 19:25:26.000000000 +0000 +@@ -51,9 +51,6 @@ err = request_firmware(&firmware, fw_name, &dev->dev); if (err || !firmware) { @@ -2929,9 +3263,11 @@ goto error1; } if (firmware->size < sizeof(header)) { ---- a/sound/pci/cs46xx/cs46xx_lib.c -+++ b/sound/pci/cs46xx/cs46xx_lib.c -@@ -411,10 +411,8 @@ static int snd_cs46xx_download_image(str +Index: linux-3.2.46/sound/pci/cs46xx/cs46xx_lib.c +=================================================================== +--- linux-3.2.46.orig/sound/pci/cs46xx/cs46xx_lib.c 2013-07-26 19:16:50.000000000 +0000 ++++ linux-3.2.46/sound/pci/cs46xx/cs46xx_lib.c 2013-07-26 19:25:26.000000000 +0000 +@@ -411,10 +411,8 @@ err = request_firmware(&firmware, "cs46xx/cs46xx-old.fw", &chip->pci->dev); @@ -2943,9 +3279,11 @@ err = snd_cs46xx_check_image_size(firmware); if (err < 0) ---- a/sound/pci/echoaudio/echoaudio.c -+++ b/sound/pci/echoaudio/echoaudio.c -@@ -57,10 +57,8 @@ static int get_firmware(const struct fir +Index: linux-3.2.46/sound/pci/echoaudio/echoaudio.c +=================================================================== +--- linux-3.2.46.orig/sound/pci/echoaudio/echoaudio.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/sound/pci/echoaudio/echoaudio.c 2013-07-26 19:25:26.000000000 +0000 +@@ -57,10 +57,8 @@ DE_ACT(("firmware requested: %s\n", card_fw[fw_index].data)); snprintf(name, sizeof(name), "ea/%s", card_fw[fw_index].data); err = request_firmware(fw_entry, name, pci_device(chip)); @@ -2957,9 +3295,11 @@ chip->fw_cache[fw_index] = *fw_entry; #endif return err; ---- a/sound/pci/emu10k1/emu10k1_main.c -+++ b/sound/pci/emu10k1/emu10k1_main.c -@@ -668,10 +668,8 @@ static int snd_emu1010_load_firmware(str +Index: linux-3.2.46/sound/pci/emu10k1/emu10k1_main.c +=================================================================== +--- linux-3.2.46.orig/sound/pci/emu10k1/emu10k1_main.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/sound/pci/emu10k1/emu10k1_main.c 2013-07-26 19:25:26.000000000 +0000 +@@ -668,10 +668,8 @@ const struct firmware *fw_entry; err = request_firmware(&fw_entry, filename, &emu->pci->dev); @@ -2971,9 +3311,11 @@ snd_printk(KERN_INFO "firmware size = 0x%zx\n", fw_entry->size); /* The FPGA is a Xilinx Spartan IIE XC2S50E */ ---- a/sound/pci/hda/hda_hwdep.c -+++ b/sound/pci/hda/hda_hwdep.c -@@ -792,11 +792,8 @@ int snd_hda_load_patch(struct hda_bus *b +Index: linux-3.2.46/sound/pci/hda/hda_hwdep.c +=================================================================== +--- linux-3.2.46.orig/sound/pci/hda/hda_hwdep.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/sound/pci/hda/hda_hwdep.c 2013-07-26 19:25:26.000000000 +0000 +@@ -792,11 +792,8 @@ if (snd_BUG_ON(!dev)) return -ENODEV; err = request_firmware(&fw, patch, dev); @@ -2986,9 +3328,11 @@ tmp = *fw; line_mode = LINE_MODE_NONE; ---- a/sound/pci/korg1212/korg1212.c -+++ b/sound/pci/korg1212/korg1212.c -@@ -2346,7 +2346,6 @@ static int __devinit snd_korg1212_create +Index: linux-3.2.46/sound/pci/korg1212/korg1212.c +=================================================================== +--- linux-3.2.46.orig/sound/pci/korg1212/korg1212.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/sound/pci/korg1212/korg1212.c 2013-07-26 19:25:26.000000000 +0000 +@@ -2346,7 +2346,6 @@ err = request_firmware(&dsp_code, "korg/k1212.dsp", &pci->dev); if (err < 0) { release_firmware(dsp_code); @@ -2996,9 +3340,11 @@ snd_korg1212_free(korg1212); return err; } ---- a/sound/pci/mixart/mixart_hwdep.c -+++ b/sound/pci/mixart/mixart_hwdep.c -@@ -566,10 +566,8 @@ int snd_mixart_setup_firmware(struct mix +Index: linux-3.2.46/sound/pci/mixart/mixart_hwdep.c +=================================================================== +--- linux-3.2.46.orig/sound/pci/mixart/mixart_hwdep.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/sound/pci/mixart/mixart_hwdep.c 2013-07-26 19:25:26.000000000 +0000 +@@ -566,10 +566,8 @@ for (i = 0; i < 3; i++) { sprintf(path, "mixart/%s", fw_files[i]); @@ -3010,9 +3356,11 @@ /* fake hwdep dsp record */ err = mixart_dsp_load(mgr, i, fw_entry); release_firmware(fw_entry); ---- a/sound/pci/pcxhr/pcxhr_hwdep.c -+++ b/sound/pci/pcxhr/pcxhr_hwdep.c -@@ -390,11 +390,8 @@ int pcxhr_setup_firmware(struct pcxhr_mg +Index: linux-3.2.46/sound/pci/pcxhr/pcxhr_hwdep.c +=================================================================== +--- linux-3.2.46.orig/sound/pci/pcxhr/pcxhr_hwdep.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/sound/pci/pcxhr/pcxhr_hwdep.c 2013-07-26 19:25:26.000000000 +0000 +@@ -390,11 +390,8 @@ if (!fw_files[fw_set][i]) continue; sprintf(path, "pcxhr/%s", fw_files[fw_set][i]); @@ -3025,9 +3373,11 @@ /* fake hwdep dsp record */ err = pcxhr_dsp_load(mgr, i, fw_entry); release_firmware(fw_entry); ---- a/sound/pci/riptide/riptide.c -+++ b/sound/pci/riptide/riptide.c -@@ -1238,11 +1238,8 @@ static int try_to_load_firmware(struct c +Index: linux-3.2.46/sound/pci/riptide/riptide.c +=================================================================== +--- linux-3.2.46.orig/sound/pci/riptide/riptide.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/sound/pci/riptide/riptide.c 2013-07-26 19:25:26.000000000 +0000 +@@ -1238,11 +1238,8 @@ if (!chip->fw_entry) { err = request_firmware(&chip->fw_entry, "riptide.hex", &chip->pci->dev); @@ -3040,9 +3390,11 @@ } err = loadfirmware(cif, chip->fw_entry->data, chip->fw_entry->size); if (err) { ---- a/sound/pci/rme9652/hdsp.c -+++ b/sound/pci/rme9652/hdsp.c -@@ -5369,10 +5369,8 @@ static int hdsp_request_fw_loader(struct +Index: linux-3.2.46/sound/pci/rme9652/hdsp.c +=================================================================== +--- linux-3.2.46.orig/sound/pci/rme9652/hdsp.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/sound/pci/rme9652/hdsp.c 2013-07-26 19:25:26.000000000 +0000 +@@ -5369,10 +5369,8 @@ return -EINVAL; } @@ -3054,9 +3406,11 @@ if (fw->size < sizeof(hdsp->firmware_cache)) { snd_printk(KERN_ERR "Hammerfall-DSP: too short firmware size %d (expected %d)\n", (int)fw->size, (int)sizeof(hdsp->firmware_cache)); ---- a/sound/soc/codecs/wm2000.c -+++ b/sound/soc/codecs/wm2000.c -@@ -773,10 +773,8 @@ static int __devinit wm2000_i2c_probe(st +Index: linux-3.2.46/sound/soc/codecs/wm2000.c +=================================================================== +--- linux-3.2.46.orig/sound/soc/codecs/wm2000.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/sound/soc/codecs/wm2000.c 2013-07-26 19:25:27.000000000 +0000 +@@ -773,10 +773,8 @@ } ret = request_firmware(&fw, filename, &i2c->dev); @@ -3068,9 +3422,11 @@ /* Pre-cook the concatenation of the register address onto the image */ wm2000->anc_download_size = fw->size + 2; ---- a/sound/usb/6fire/firmware.c -+++ b/sound/usb/6fire/firmware.c -@@ -220,8 +220,6 @@ static int usb6fire_fw_ezusb_upload( +Index: linux-3.2.46/sound/usb/6fire/firmware.c +=================================================================== +--- linux-3.2.46.orig/sound/usb/6fire/firmware.c 2013-07-26 18:53:58.000000000 +0000 ++++ linux-3.2.46/sound/usb/6fire/firmware.c 2013-07-26 19:25:27.000000000 +0000 +@@ -220,8 +220,6 @@ ret = request_firmware(&fw, fwname, &device->dev); if (ret < 0) { kfree(rec); @@ -3079,7 +3435,7 @@ return ret; } ret = usb6fire_fw_ihex_init(fw, rec); -@@ -293,8 +291,6 @@ static int usb6fire_fw_fpga_upload( +@@ -293,8 +291,6 @@ ret = request_firmware(&fw, fwname, &device->dev); if (ret < 0) { diff -Nru linux-3.2.46/debian/patches/bugfix/all/fs-add-new-FMODE-flags-FMODE_32bithash-and-FMODE_64b.patch linux-3.2.46/debian/patches/bugfix/all/fs-add-new-FMODE-flags-FMODE_32bithash-and-FMODE_64b.patch --- linux-3.2.46/debian/patches/bugfix/all/fs-add-new-FMODE-flags-FMODE_32bithash-and-FMODE_64b.patch 2013-06-08 16:47:39.000000000 +0000 +++ linux-3.2.46/debian/patches/bugfix/all/fs-add-new-FMODE-flags-FMODE_32bithash-and-FMODE_64b.patch 2013-07-26 19:31:07.000000000 +0000 @@ -14,11 +14,11 @@ include/linux/fs.h | 4 ++++ 1 file changed, 4 insertions(+) -diff --git a/include/linux/fs.h b/include/linux/fs.h -index 29b6353..fb7ce74 100644 ---- a/include/linux/fs.h -+++ b/include/linux/fs.h -@@ -92,6 +92,10 @@ struct inodes_stat_t { +Index: linux-3.2.46/include/linux/fs.h +=================================================================== +--- linux-3.2.46.orig/include/linux/fs.h 2013-07-26 19:17:51.000000000 +0000 ++++ linux-3.2.46/include/linux/fs.h 2013-07-26 19:31:06.000000000 +0000 +@@ -92,6 +92,10 @@ /* File is opened using open(.., 3, ..) and is writeable only for ioctls (specialy hack for floppy.c) */ #define FMODE_WRITE_IOCTL ((__force fmode_t)0x100) @@ -29,6 +29,3 @@ /* * Don't update ctime and mtime. --- -1.7.10.4 - diff -Nru linux-3.2.46/debian/patches/bugfix/all/i915-ensure-that-VGA-plane-is-disabled.patch linux-3.2.46/debian/patches/bugfix/all/i915-ensure-that-VGA-plane-is-disabled.patch --- linux-3.2.46/debian/patches/bugfix/all/i915-ensure-that-VGA-plane-is-disabled.patch 2013-02-24 03:52:24.000000000 +0000 +++ linux-3.2.46/debian/patches/bugfix/all/i915-ensure-that-VGA-plane-is-disabled.patch 2013-07-26 19:27:31.000000000 +0000 @@ -17,9 +17,11 @@ exist, so call i915_redisable_vga() directly from intel_lid_notify()] Signed-off-by: Ben Hutchings --- ---- a/drivers/gpu/drm/i915/intel_display.c -+++ b/drivers/gpu/drm/i915/intel_display.c -@@ -8898,6 +8898,23 @@ static void i915_disable_vga(struct drm_ +Index: linux-3.2.46/drivers/gpu/drm/i915/intel_display.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/i915/intel_display.c 2013-07-26 19:27:26.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/i915/intel_display.c 2013-07-26 19:27:30.000000000 +0000 +@@ -9314,6 +9314,23 @@ POSTING_READ(vga_reg); } @@ -43,9 +45,11 @@ void intel_modeset_init(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; ---- a/drivers/gpu/drm/i915/i915_drv.h -+++ b/drivers/gpu/drm/i915/i915_drv.h -@@ -1305,6 +1305,7 @@ static inline void intel_unregister_dsm_ +Index: linux-3.2.46/drivers/gpu/drm/i915/i915_drv.h +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/i915/i915_drv.h 2013-07-26 19:27:17.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/i915/i915_drv.h 2013-07-26 19:27:30.000000000 +0000 +@@ -1397,6 +1397,7 @@ #endif /* CONFIG_ACPI */ /* modesetting */ @@ -53,9 +57,11 @@ extern void intel_modeset_init(struct drm_device *dev); extern void intel_modeset_gem_init(struct drm_device *dev); extern void intel_modeset_cleanup(struct drm_device *dev); ---- a/drivers/gpu/drm/i915/intel_lvds.c -+++ b/drivers/gpu/drm/i915/intel_lvds.c -@@ -535,6 +535,7 @@ static int intel_lid_notify(struct notif +Index: linux-3.2.46/drivers/gpu/drm/i915/intel_lvds.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/i915/intel_lvds.c 2013-07-26 19:26:22.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/i915/intel_lvds.c 2013-07-26 19:27:30.000000000 +0000 +@@ -541,6 +541,7 @@ mutex_lock(&dev->mode_config.mutex); drm_helper_resume_force_mode(dev); diff -Nru linux-3.2.46/debian/patches/bugfix/all/iscsi-target-fix-heap-buffer-overflow-on-error.patch linux-3.2.46/debian/patches/bugfix/all/iscsi-target-fix-heap-buffer-overflow-on-error.patch --- linux-3.2.46/debian/patches/bugfix/all/iscsi-target-fix-heap-buffer-overflow-on-error.patch 2013-06-05 03:41:51.000000000 +0000 +++ linux-3.2.46/debian/patches/bugfix/all/iscsi-target-fix-heap-buffer-overflow-on-error.patch 2013-07-26 19:30:52.000000000 +0000 @@ -21,11 +21,11 @@ drivers/target/iscsi/iscsi_target_parameters.h | 4 +++- 2 files changed, 6 insertions(+), 6 deletions(-) -diff --git a/drivers/target/iscsi/iscsi_target_parameters.c b/drivers/target/iscsi/iscsi_target_parameters.c -index c2185fc..e382221 100644 ---- a/drivers/target/iscsi/iscsi_target_parameters.c -+++ b/drivers/target/iscsi/iscsi_target_parameters.c -@@ -758,9 +758,9 @@ static int iscsi_add_notunderstood_response( +Index: linux-3.2.46/drivers/target/iscsi/iscsi_target_parameters.c +=================================================================== +--- linux-3.2.46.orig/drivers/target/iscsi/iscsi_target_parameters.c 2013-07-26 18:52:14.000000000 +0000 ++++ linux-3.2.46/drivers/target/iscsi/iscsi_target_parameters.c 2013-07-26 19:30:51.000000000 +0000 +@@ -713,9 +713,9 @@ } INIT_LIST_HEAD(&extra_response->er_list); @@ -38,7 +38,7 @@ list_add_tail(&extra_response->er_list, ¶m_list->extra_response_list); -@@ -1629,8 +1629,6 @@ int iscsi_decode_text_input( +@@ -1572,8 +1572,6 @@ if (phase & PHASE_SECURITY) { if (iscsi_check_for_auth_key(key) > 0) { @@ -47,10 +47,10 @@ kfree(tmpbuf); return 1; } -diff --git a/drivers/target/iscsi/iscsi_target_parameters.h b/drivers/target/iscsi/iscsi_target_parameters.h -index 915b067..a47046a 100644 ---- a/drivers/target/iscsi/iscsi_target_parameters.h -+++ b/drivers/target/iscsi/iscsi_target_parameters.h +Index: linux-3.2.46/drivers/target/iscsi/iscsi_target_parameters.h +=================================================================== +--- linux-3.2.46.orig/drivers/target/iscsi/iscsi_target_parameters.h 2013-07-26 18:52:14.000000000 +0000 ++++ linux-3.2.46/drivers/target/iscsi/iscsi_target_parameters.h 2013-07-26 19:30:51.000000000 +0000 @@ -1,8 +1,10 @@ #ifndef ISCSI_PARAMETERS_H #define ISCSI_PARAMETERS_H diff -Nru linux-3.2.46/debian/patches/bugfix/all/kbuild-Fix-missing-n-for-NEW-symbols-in-yes-make-old.patch linux-3.2.46/debian/patches/bugfix/all/kbuild-Fix-missing-n-for-NEW-symbols-in-yes-make-old.patch --- linux-3.2.46/debian/patches/bugfix/all/kbuild-Fix-missing-n-for-NEW-symbols-in-yes-make-old.patch 2013-06-08 17:21:02.000000000 +0000 +++ linux-3.2.46/debian/patches/bugfix/all/kbuild-Fix-missing-n-for-NEW-symbols-in-yes-make-old.patch 2013-07-26 19:31:15.000000000 +0000 @@ -25,9 +25,11 @@ scripts/kconfig/conf.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) ---- a/scripts/kconfig/conf.c -+++ b/scripts/kconfig/conf.c -@@ -36,6 +36,7 @@ enum input_mode { +Index: linux-3.2.46/scripts/kconfig/conf.c +=================================================================== +--- linux-3.2.46.orig/scripts/kconfig/conf.c 2013-07-26 19:17:20.000000000 +0000 ++++ linux-3.2.46/scripts/kconfig/conf.c 2013-07-26 19:31:14.000000000 +0000 +@@ -36,6 +36,7 @@ } input_mode = oldaskconfig; static int indent = 1; @@ -35,7 +37,7 @@ static int valid_stdin = 1; static int sync_kconfig; static int conf_cnt; -@@ -108,6 +109,8 @@ static int conf_askvalue(struct symbol * +@@ -108,6 +109,8 @@ case oldaskconfig: fflush(stdout); xfgets(line, 128, stdin); @@ -44,7 +46,7 @@ return 1; default: break; -@@ -508,6 +511,8 @@ int main(int ac, char **av) +@@ -508,6 +511,8 @@ bindtextdomain(PACKAGE, LOCALEDIR); textdomain(PACKAGE); @@ -53,7 +55,7 @@ while ((opt = getopt_long(ac, av, "", long_opts, NULL)) != -1) { input_mode = (enum input_mode)opt; switch (opt) { -@@ -624,7 +629,7 @@ int main(int ac, char **av) +@@ -624,7 +629,7 @@ return 1; } } diff -Nru linux-3.2.46/debian/patches/bugfix/all/kexec-remove-KMSG_DUMP_KEXEC.patch linux-3.2.46/debian/patches/bugfix/all/kexec-remove-KMSG_DUMP_KEXEC.patch --- linux-3.2.46/debian/patches/bugfix/all/kexec-remove-KMSG_DUMP_KEXEC.patch 2013-03-19 01:33:24.000000000 +0000 +++ linux-3.2.46/debian/patches/bugfix/all/kexec-remove-KMSG_DUMP_KEXEC.patch 2013-07-26 19:30:29.000000000 +0000 @@ -25,11 +25,11 @@ kernel/kexec.c | 3 --- 5 files changed, 2 insertions(+), 9 deletions(-) -diff --git a/arch/powerpc/platforms/pseries/nvram.c b/arch/powerpc/platforms/pseries/nvram.c -index 330a57b..36f957f 100644 ---- a/arch/powerpc/platforms/pseries/nvram.c -+++ b/arch/powerpc/platforms/pseries/nvram.c -@@ -638,7 +638,6 @@ static void oops_to_nvram(struct kmsg_dumper *dumper, +Index: linux-3.2.46/arch/powerpc/platforms/pseries/nvram.c +=================================================================== +--- linux-3.2.46.orig/arch/powerpc/platforms/pseries/nvram.c 2013-07-26 18:52:22.000000000 +0000 ++++ linux-3.2.46/arch/powerpc/platforms/pseries/nvram.c 2013-07-26 19:30:27.000000000 +0000 +@@ -636,7 +636,6 @@ /* These are almost always orderly shutdowns. */ return; case KMSG_DUMP_OOPS: @@ -37,11 +37,11 @@ break; case KMSG_DUMP_PANIC: panicking = true; -diff --git a/drivers/char/ramoops.c b/drivers/char/ramoops.c -index 7c7f42a1f8..feda90c 100644 ---- a/drivers/char/ramoops.c -+++ b/drivers/char/ramoops.c -@@ -83,8 +83,7 @@ static void ramoops_do_dump(struct kmsg_dumper *dumper, +Index: linux-3.2.46/drivers/char/ramoops.c +=================================================================== +--- linux-3.2.46.orig/drivers/char/ramoops.c 2013-07-26 18:52:22.000000000 +0000 ++++ linux-3.2.46/drivers/char/ramoops.c 2013-07-26 19:30:27.000000000 +0000 +@@ -83,8 +83,7 @@ struct timeval timestamp; if (reason != KMSG_DUMP_OOPS && @@ -51,11 +51,11 @@ return; /* Only dump oopses if dump_oops is set */ -diff --git a/drivers/mtd/mtdoops.c b/drivers/mtd/mtdoops.c -index db8e827..3ce99e0 100644 ---- a/drivers/mtd/mtdoops.c -+++ b/drivers/mtd/mtdoops.c -@@ -315,8 +315,7 @@ static void mtdoops_do_dump(struct kmsg_dumper *dumper, +Index: linux-3.2.46/drivers/mtd/mtdoops.c +=================================================================== +--- linux-3.2.46.orig/drivers/mtd/mtdoops.c 2013-07-26 18:52:22.000000000 +0000 ++++ linux-3.2.46/drivers/mtd/mtdoops.c 2013-07-26 19:30:27.000000000 +0000 +@@ -311,8 +311,7 @@ char *dst; if (reason != KMSG_DUMP_OOPS && @@ -65,10 +65,10 @@ return; /* Only dump oopses if dump_oops is set */ -diff --git a/include/linux/kmsg_dump.h b/include/linux/kmsg_dump.h -index ee0c952..fee6631 100644 ---- a/include/linux/kmsg_dump.h -+++ b/include/linux/kmsg_dump.h +Index: linux-3.2.46/include/linux/kmsg_dump.h +=================================================================== +--- linux-3.2.46.orig/include/linux/kmsg_dump.h 2013-07-26 18:52:22.000000000 +0000 ++++ linux-3.2.46/include/linux/kmsg_dump.h 2013-07-26 19:30:27.000000000 +0000 @@ -18,7 +18,6 @@ enum kmsg_dump_reason { KMSG_DUMP_OOPS, @@ -77,10 +77,10 @@ KMSG_DUMP_RESTART, KMSG_DUMP_HALT, KMSG_DUMP_POWEROFF, -diff --git a/kernel/kexec.c b/kernel/kexec.c -index 090ee10..20ed47a 100644 ---- a/kernel/kexec.c -+++ b/kernel/kexec.c +Index: linux-3.2.46/kernel/kexec.c +=================================================================== +--- linux-3.2.46.orig/kernel/kexec.c 2013-07-26 18:52:22.000000000 +0000 ++++ linux-3.2.46/kernel/kexec.c 2013-07-26 19:30:27.000000000 +0000 @@ -32,7 +32,6 @@ #include #include @@ -89,7 +89,7 @@ #include #include -@@ -1094,8 +1093,6 @@ void crash_kexec(struct pt_regs *regs) +@@ -1094,8 +1093,6 @@ if (kexec_crash_image) { struct pt_regs fixed_regs; diff -Nru linux-3.2.46/debian/patches/bugfix/all/kmsg_dump-don-t-run-on-non-error-paths-by-default.patch linux-3.2.46/debian/patches/bugfix/all/kmsg_dump-don-t-run-on-non-error-paths-by-default.patch --- linux-3.2.46/debian/patches/bugfix/all/kmsg_dump-don-t-run-on-non-error-paths-by-default.patch 2013-03-19 01:03:59.000000000 +0000 +++ linux-3.2.46/debian/patches/bugfix/all/kmsg_dump-don-t-run-on-non-error-paths-by-default.patch 2013-07-26 19:30:30.000000000 +0000 @@ -37,11 +37,11 @@ kernel/printk.c | 6 ++++++ 3 files changed, 19 insertions(+), 2 deletions(-) -diff --git a/Documentation/kernel-parameters.txt b/Documentation/kernel-parameters.txt -index 033d4e6..d99fd9c 100644 ---- a/Documentation/kernel-parameters.txt -+++ b/Documentation/kernel-parameters.txt -@@ -2211,6 +2211,12 @@ bytes respectively. Such letter suffixes can also be entirely omitted. +Index: linux-3.2.46/Documentation/kernel-parameters.txt +=================================================================== +--- linux-3.2.46.orig/Documentation/kernel-parameters.txt 2013-07-26 19:17:23.000000000 +0000 ++++ linux-3.2.46/Documentation/kernel-parameters.txt 2013-07-26 19:30:29.000000000 +0000 +@@ -2194,6 +2194,12 @@ default: off. @@ -54,10 +54,10 @@ printk.time= Show timing data prefixed to each printk message line Format: (1/Y/y=enable, 0/N/n=disable) -diff --git a/include/linux/kmsg_dump.h b/include/linux/kmsg_dump.h -index fee6631..35f7237 100644 ---- a/include/linux/kmsg_dump.h -+++ b/include/linux/kmsg_dump.h +Index: linux-3.2.46/include/linux/kmsg_dump.h +=================================================================== +--- linux-3.2.46.orig/include/linux/kmsg_dump.h 2013-07-26 19:30:27.000000000 +0000 ++++ linux-3.2.46/include/linux/kmsg_dump.h 2013-07-26 19:30:29.000000000 +0000 @@ -15,13 +15,18 @@ #include #include @@ -79,11 +79,11 @@ }; /** -diff --git a/kernel/printk.c b/kernel/printk.c -index 13c0a11..32690a0 100644 ---- a/kernel/printk.c -+++ b/kernel/printk.c -@@ -702,6 +702,9 @@ static bool printk_time = 0; +Index: linux-3.2.46/kernel/printk.c +=================================================================== +--- linux-3.2.46.orig/kernel/printk.c 2013-07-26 18:52:21.000000000 +0000 ++++ linux-3.2.46/kernel/printk.c 2013-07-26 19:30:29.000000000 +0000 +@@ -712,6 +712,9 @@ #endif module_param_named(time, printk_time, bool, S_IRUGO | S_IWUSR); @@ -93,7 +93,7 @@ /* Check if we have any console registered that can be called early in boot. */ static int have_callable_console(void) { -@@ -1732,6 +1735,9 @@ void kmsg_dump(enum kmsg_dump_reason reason) +@@ -1744,6 +1747,9 @@ unsigned long l1, l2; unsigned long flags; diff -Nru linux-3.2.46/debian/patches/bugfix/all/megaraid_sas-fix-memory-leak-if-SGL-has-zero-length-entries.patch linux-3.2.46/debian/patches/bugfix/all/megaraid_sas-fix-memory-leak-if-SGL-has-zero-length-entries.patch --- linux-3.2.46/debian/patches/bugfix/all/megaraid_sas-fix-memory-leak-if-SGL-has-zero-length-entries.patch 2013-02-24 03:52:24.000000000 +0000 +++ linux-3.2.46/debian/patches/bugfix/all/megaraid_sas-fix-memory-leak-if-SGL-has-zero-length-entries.patch 2013-07-26 19:25:41.000000000 +0000 @@ -18,9 +18,11 @@ drivers/scsi/megaraid/megaraid_sas_base.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) ---- a/drivers/scsi/megaraid/megaraid_sas_base.c -+++ b/drivers/scsi/megaraid/megaraid_sas_base.c -@@ -4886,10 +4886,12 @@ megasas_mgmt_fw_ioctl(struct megasas_ins +Index: linux-3.2.46/drivers/scsi/megaraid/megaraid_sas_base.c +=================================================================== +--- linux-3.2.46.orig/drivers/scsi/megaraid/megaraid_sas_base.c 2013-07-26 18:53:47.000000000 +0000 ++++ linux-3.2.46/drivers/scsi/megaraid/megaraid_sas_base.c 2013-07-26 19:25:40.000000000 +0000 +@@ -4886,10 +4886,12 @@ sense, sense_handle); } diff -Nru linux-3.2.46/debian/patches/bugfix/all/mm-Try-harder-to-allocate-vmemmap-blocks.patch linux-3.2.46/debian/patches/bugfix/all/mm-Try-harder-to-allocate-vmemmap-blocks.patch --- linux-3.2.46/debian/patches/bugfix/all/mm-Try-harder-to-allocate-vmemmap-blocks.patch 2013-02-24 03:52:24.000000000 +0000 +++ linux-3.2.46/debian/patches/bugfix/all/mm-Try-harder-to-allocate-vmemmap-blocks.patch 2013-07-26 19:30:20.000000000 +0000 @@ -14,11 +14,11 @@ mm/sparse-vmemmap.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) -diff --git a/mm/sparse-vmemmap.c b/mm/sparse-vmemmap.c -index 1b7e22a..22b7e18 100644 ---- a/mm/sparse-vmemmap.c -+++ b/mm/sparse-vmemmap.c -@@ -53,10 +53,12 @@ void * __meminit vmemmap_alloc_block(unsigned long size, int node) +Index: linux-3.2.46/mm/sparse-vmemmap.c +=================================================================== +--- linux-3.2.46.orig/mm/sparse-vmemmap.c 2013-07-26 18:52:25.000000000 +0000 ++++ linux-3.2.46/mm/sparse-vmemmap.c 2013-07-26 19:30:19.000000000 +0000 +@@ -53,10 +53,12 @@ struct page *page; if (node_state(node, N_HIGH_MEMORY)) diff -Nru linux-3.2.46/debian/patches/bugfix/all/net-e100-ucode-is-optional-in-some-cases.patch linux-3.2.46/debian/patches/bugfix/all/net-e100-ucode-is-optional-in-some-cases.patch --- linux-3.2.46/debian/patches/bugfix/all/net-e100-ucode-is-optional-in-some-cases.patch 2013-02-24 03:52:24.000000000 +0000 +++ linux-3.2.46/debian/patches/bugfix/all/net-e100-ucode-is-optional-in-some-cases.patch 2013-07-26 19:24:07.000000000 +0000 @@ -37,11 +37,11 @@ drivers/net/ethernet/intel/e100.c | 40 ++++++++++++++++++++++++++++--------- 1 file changed, 31 insertions(+), 9 deletions(-) -diff --git a/drivers/net/ethernet/intel/e100.c b/drivers/net/ethernet/intel/e100.c -index ada720b..535f94f 100644 ---- a/drivers/net/ethernet/intel/e100.c -+++ b/drivers/net/ethernet/intel/e100.c -@@ -1249,20 +1249,35 @@ static const struct firmware *e100_request_firmware(struct nic *nic) +Index: linux-3.2.46/drivers/net/ethernet/intel/e100.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/intel/e100.c 2013-07-26 18:54:23.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/intel/e100.c 2013-07-26 19:24:06.000000000 +0000 +@@ -1233,20 +1233,35 @@ const struct firmware *fw = nic->fw; u8 timer, bundle, min_size; int err = 0; @@ -82,7 +82,7 @@ /* If the firmware has not previously been loaded, request a pointer * to it. If it was previously loaded, we are reinitializing the -@@ -1273,10 +1288,17 @@ static const struct firmware *e100_request_firmware(struct nic *nic) +@@ -1257,10 +1272,17 @@ err = request_firmware(&fw, fw_name, &nic->pdev->dev); if (err) { diff -Nru linux-3.2.46/debian/patches/bugfix/all/nfsd4-hash-lockowners-to-simplify-RELEASE_LOCKOWNER.patch linux-3.2.46/debian/patches/bugfix/all/nfsd4-hash-lockowners-to-simplify-RELEASE_LOCKOWNER.patch --- linux-3.2.46/debian/patches/bugfix/all/nfsd4-hash-lockowners-to-simplify-RELEASE_LOCKOWNER.patch 2013-06-08 16:23:55.000000000 +0000 +++ linux-3.2.46/debian/patches/bugfix/all/nfsd4-hash-lockowners-to-simplify-RELEASE_LOCKOWNER.patch 2013-07-26 19:31:00.000000000 +0000 @@ -16,9 +16,11 @@ fs/nfsd/nfs4state.c | 42 ++++++++++++++---------------------------- 1 file changed, 14 insertions(+), 28 deletions(-) ---- a/fs/nfsd/nfs4state.c -+++ b/fs/nfsd/nfs4state.c -@@ -3743,15 +3743,6 @@ last_byte_offset(u64 start, u64 len) +Index: linux-3.2.46/fs/nfsd/nfs4state.c +=================================================================== +--- linux-3.2.46.orig/fs/nfsd/nfs4state.c 2013-07-26 19:30:58.000000000 +0000 ++++ linux-3.2.46/fs/nfsd/nfs4state.c 2013-07-26 19:30:59.000000000 +0000 +@@ -3743,15 +3743,6 @@ return end > start ? end - 1: NFS4_MAX_UINT64; } @@ -34,7 +36,7 @@ static struct list_head lock_ownerstr_hashtbl[LOCK_HASH_SIZE]; /* -@@ -3821,7 +3812,7 @@ static struct nfs4_lockowner * +@@ -3821,7 +3812,7 @@ find_lockowner_str(struct inode *inode, clientid_t *clid, struct xdr_netobj *owner) { @@ -43,7 +45,7 @@ struct nfs4_lockowner *lo; struct nfs4_stateowner *op; -@@ -3844,7 +3835,7 @@ static void hash_lockowner(struct nfs4_l +@@ -3844,7 +3835,7 @@ * Called in nfsd4_lock - therefore, OPEN and OPEN_CONFIRM (if needed) has * occurred. * @@ -52,7 +54,7 @@ */ static struct nfs4_lockowner * -@@ -3919,7 +3910,7 @@ __be32 lookup_or_create_lock_state(struc +@@ -3919,7 +3910,7 @@ struct nfs4_ol_stateid, st_perstateowner); return nfs_ok; } @@ -61,7 +63,7 @@ &lock->v.new.owner); lo = alloc_init_lock_stateowner(strhashval, cl, ost, lock); if (lo == NULL) -@@ -4274,7 +4265,7 @@ nfsd4_release_lockowner(struct svc_rqst +@@ -4274,7 +4265,7 @@ struct nfs4_ol_stateid *stp; struct xdr_netobj *owner = &rlockowner->rl_owner; struct list_head matches; @@ -70,7 +72,7 @@ __be32 status; dprintk("nfsd4_release_lockowner clientid: (%08x/%08x):\n", -@@ -4289,22 +4280,17 @@ nfsd4_release_lockowner(struct svc_rqst +@@ -4289,22 +4280,17 @@ nfs4_lock_state(); status = nfserr_locks_held; diff -Nru linux-3.2.46/debian/patches/bugfix/all/nfsd4-maintain-one-seqid-stream-per-lockowner-file.patch linux-3.2.46/debian/patches/bugfix/all/nfsd4-maintain-one-seqid-stream-per-lockowner-file.patch --- linux-3.2.46/debian/patches/bugfix/all/nfsd4-maintain-one-seqid-stream-per-lockowner-file.patch 2013-06-08 16:23:07.000000000 +0000 +++ linux-3.2.46/debian/patches/bugfix/all/nfsd4-maintain-one-seqid-stream-per-lockowner-file.patch 2013-07-26 19:30:59.000000000 +0000 @@ -13,9 +13,11 @@ fs/nfsd/nfs4state.c | 58 +++++++++++++++++++++++++++++++++------------------ 1 file changed, 38 insertions(+), 20 deletions(-) ---- a/fs/nfsd/nfs4state.c -+++ b/fs/nfsd/nfs4state.c -@@ -3902,6 +3902,37 @@ static void get_lock_access(struct nfs4_ +Index: linux-3.2.46/fs/nfsd/nfs4state.c +=================================================================== +--- linux-3.2.46.orig/fs/nfsd/nfs4state.c 2013-07-26 18:52:11.000000000 +0000 ++++ linux-3.2.46/fs/nfsd/nfs4state.c 2013-07-26 19:30:58.000000000 +0000 +@@ -3902,6 +3902,37 @@ __set_bit(access, &lock_stp->st_access_bmap); } @@ -53,7 +55,7 @@ /* * LOCK operation */ -@@ -3917,7 +3948,7 @@ nfsd4_lock(struct svc_rqst *rqstp, struc +@@ -3917,7 +3948,7 @@ struct file_lock file_lock; struct file_lock conflock; __be32 status = 0; @@ -62,7 +64,7 @@ int lkflg; int err; -@@ -3962,21 +3993,9 @@ nfsd4_lock(struct svc_rqst *rqstp, struc +@@ -3962,21 +3993,9 @@ !same_clid(&open_sop->oo_owner.so_client->cl_clientid, &lock->v.new.clientid)) goto out; @@ -87,7 +89,7 @@ goto out; } else { /* lock (lock owner + lock stateid) already exists */ -@@ -3986,10 +4005,9 @@ nfsd4_lock(struct svc_rqst *rqstp, struc +@@ -3986,10 +4005,9 @@ NFS4_LOCK_STID, &lock_stp); if (status) goto out; @@ -100,7 +102,7 @@ lkflg = setlkflg(lock->lk_type); status = nfs4_check_openmode(lock_stp, lkflg); -@@ -4064,7 +4082,7 @@ nfsd4_lock(struct svc_rqst *rqstp, struc +@@ -4064,7 +4082,7 @@ break; } out: diff -Nru linux-3.2.46/debian/patches/bugfix/all/nfsd-rename-int-access-to-int-may_flags-in-nfsd_open.patch linux-3.2.46/debian/patches/bugfix/all/nfsd-rename-int-access-to-int-may_flags-in-nfsd_open.patch --- linux-3.2.46/debian/patches/bugfix/all/nfsd-rename-int-access-to-int-may_flags-in-nfsd_open.patch 2013-06-08 16:47:39.000000000 +0000 +++ linux-3.2.46/debian/patches/bugfix/all/nfsd-rename-int-access-to-int-may_flags-in-nfsd_open.patch 2013-07-26 19:31:09.000000000 +0000 @@ -15,11 +15,11 @@ fs/nfsd/vfs.c | 18 ++++++++++-------- 1 file changed, 10 insertions(+), 8 deletions(-) -diff --git a/fs/nfsd/vfs.c b/fs/nfsd/vfs.c -index 5c3cd82..b395c61 100644 ---- a/fs/nfsd/vfs.c -+++ b/fs/nfsd/vfs.c -@@ -726,12 +726,13 @@ static int nfsd_open_break_lease(struct inode *inode, int access) +Index: linux-3.2.46/fs/nfsd/vfs.c +=================================================================== +--- linux-3.2.46.orig/fs/nfsd/vfs.c 2013-07-26 18:52:08.000000000 +0000 ++++ linux-3.2.46/fs/nfsd/vfs.c 2013-07-26 19:31:09.000000000 +0000 +@@ -726,12 +726,13 @@ /* * Open an existing file or directory. @@ -35,7 +35,7 @@ { struct dentry *dentry; struct inode *inode; -@@ -746,7 +747,7 @@ nfsd_open(struct svc_rqst *rqstp, struct svc_fh *fhp, int type, +@@ -746,7 +747,7 @@ * and (hopefully) checked permission - so allow OWNER_OVERRIDE * in case a chmod has now revoked permission. */ @@ -44,7 +44,7 @@ if (err) goto out; -@@ -757,7 +758,7 @@ nfsd_open(struct svc_rqst *rqstp, struct svc_fh *fhp, int type, +@@ -757,7 +758,7 @@ * or any access when mandatory locking enabled */ err = nfserr_perm; @@ -53,7 +53,7 @@ goto out; /* * We must ignore files (but only files) which might have mandatory -@@ -770,12 +771,12 @@ nfsd_open(struct svc_rqst *rqstp, struct svc_fh *fhp, int type, +@@ -770,12 +771,12 @@ if (!inode->i_fop) goto out; @@ -69,7 +69,7 @@ flags = O_RDWR|O_LARGEFILE; else flags = O_WRONLY|O_LARGEFILE; -@@ -785,7 +786,8 @@ nfsd_open(struct svc_rqst *rqstp, struct svc_fh *fhp, int type, +@@ -785,7 +786,8 @@ if (IS_ERR(*filp)) host_err = PTR_ERR(*filp); else @@ -79,6 +79,3 @@ out_nfserr: err = nfserrno(host_err); out: --- -1.7.10.4 - diff -Nru linux-3.2.46/debian/patches/bugfix/all/nfsd-vfs_llseek-with-32-or-64-bit-offsets-hashes.patch linux-3.2.46/debian/patches/bugfix/all/nfsd-vfs_llseek-with-32-or-64-bit-offsets-hashes.patch --- linux-3.2.46/debian/patches/bugfix/all/nfsd-vfs_llseek-with-32-or-64-bit-offsets-hashes.patch 2013-06-08 16:47:39.000000000 +0000 +++ linux-3.2.46/debian/patches/bugfix/all/nfsd-vfs_llseek-with-32-or-64-bit-offsets-hashes.patch 2013-07-26 19:31:11.000000000 +0000 @@ -23,11 +23,11 @@ fs/nfsd/vfs.h | 2 ++ 2 files changed, 15 insertions(+), 2 deletions(-) -diff --git a/fs/nfsd/vfs.c b/fs/nfsd/vfs.c -index b395c61..959039e 100644 ---- a/fs/nfsd/vfs.c -+++ b/fs/nfsd/vfs.c -@@ -785,9 +785,15 @@ nfsd_open(struct svc_rqst *rqstp, struct svc_fh *fhp, int type, +Index: linux-3.2.46/fs/nfsd/vfs.c +=================================================================== +--- linux-3.2.46.orig/fs/nfsd/vfs.c 2013-07-26 19:31:09.000000000 +0000 ++++ linux-3.2.46/fs/nfsd/vfs.c 2013-07-26 19:31:10.000000000 +0000 +@@ -785,9 +785,15 @@ flags, current_cred()); if (IS_ERR(*filp)) host_err = PTR_ERR(*filp); @@ -44,25 +44,25 @@ out_nfserr: err = nfserrno(host_err); out: -@@ -2011,8 +2017,13 @@ nfsd_readdir(struct svc_rqst *rqstp, struct svc_fh *fhp, loff_t *offsetp, +@@ -2017,8 +2023,13 @@ __be32 err; struct file *file; loff_t offset = *offsetp; + int may_flags = NFSD_MAY_READ; - -- err = nfsd_open(rqstp, fhp, S_IFDIR, NFSD_MAY_READ, &file); ++ + /* NFSv2 only supports 32 bit cookies */ + if (rqstp->rq_vers > 2) + may_flags |= NFSD_MAY_64BIT_COOKIE; -+ + +- err = nfsd_open(rqstp, fhp, S_IFDIR, NFSD_MAY_READ, &file); + err = nfsd_open(rqstp, fhp, S_IFDIR, may_flags, &file); if (err) goto out; -diff --git a/fs/nfsd/vfs.h b/fs/nfsd/vfs.h -index 3f54ad0..85d4d42 100644 ---- a/fs/nfsd/vfs.h -+++ b/fs/nfsd/vfs.h +Index: linux-3.2.46/fs/nfsd/vfs.h +=================================================================== +--- linux-3.2.46.orig/fs/nfsd/vfs.h 2013-07-26 18:52:08.000000000 +0000 ++++ linux-3.2.46/fs/nfsd/vfs.h 2013-07-26 19:31:10.000000000 +0000 @@ -27,6 +27,8 @@ #define NFSD_MAY_BYPASS_GSS 0x400 #define NFSD_MAY_READ_IF_EXEC 0x800 @@ -72,6 +72,3 @@ #define NFSD_MAY_CREATE (NFSD_MAY_EXEC|NFSD_MAY_WRITE) #define NFSD_MAY_REMOVE (NFSD_MAY_EXEC|NFSD_MAY_WRITE|NFSD_MAY_TRUNC) --- -1.7.10.4 - diff -Nru linux-3.2.46/debian/patches/bugfix/all/PCI-PM-Runtime-make-PCI-traces-quieter.patch linux-3.2.46/debian/patches/bugfix/all/PCI-PM-Runtime-make-PCI-traces-quieter.patch --- linux-3.2.46/debian/patches/bugfix/all/PCI-PM-Runtime-make-PCI-traces-quieter.patch 2013-02-24 03:52:24.000000000 +0000 +++ linux-3.2.46/debian/patches/bugfix/all/PCI-PM-Runtime-make-PCI-traces-quieter.patch 2013-07-26 19:24:54.000000000 +0000 @@ -18,11 +18,11 @@ drivers/pci/setup-res.c | 6 +++--- 3 files changed, 10 insertions(+), 11 deletions(-) -diff --git a/drivers/acpi/pci_irq.c b/drivers/acpi/pci_irq.c -index 7f9eba9..0eefa12 100644 ---- a/drivers/acpi/pci_irq.c -+++ b/drivers/acpi/pci_irq.c -@@ -487,10 +487,10 @@ int acpi_pci_irq_enable(struct pci_dev *dev) +Index: linux-3.2.46/drivers/acpi/pci_irq.c +=================================================================== +--- linux-3.2.46.orig/drivers/acpi/pci_irq.c 2013-07-26 18:54:07.000000000 +0000 ++++ linux-3.2.46/drivers/acpi/pci_irq.c 2013-07-26 19:24:53.000000000 +0000 +@@ -487,10 +487,10 @@ else link_desc[0] = '\0'; @@ -37,7 +37,7 @@ return 0; } -@@ -524,6 +524,6 @@ void acpi_pci_irq_disable(struct pci_dev *dev) +@@ -524,6 +524,6 @@ * (e.g. PCI_UNDEFINED_IRQ). */ @@ -45,11 +45,11 @@ + dev_dbg(&dev->dev, "PCI INT %c disabled\n", pin_name(pin)); acpi_unregister_gsi(gsi); } -diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c -index 5c5adef..54343aa 100644 ---- a/drivers/pci/pci.c -+++ b/drivers/pci/pci.c -@@ -973,7 +973,7 @@ void pci_restore_state(struct pci_dev *dev) +Index: linux-3.2.46/drivers/pci/pci.c +=================================================================== +--- linux-3.2.46.orig/drivers/pci/pci.c 2013-07-26 18:54:07.000000000 +0000 ++++ linux-3.2.46/drivers/pci/pci.c 2013-07-26 19:24:53.000000000 +0000 +@@ -963,7 +963,7 @@ for (i = 15; i >= 0; i--) { pci_read_config_dword(dev, i * 4, &val); if (val != dev->saved_config_space[i]) { @@ -58,7 +58,7 @@ "space at offset %#x (was %#x, writing %#x)\n", i, val, (int)dev->saved_config_space[i]); pci_write_config_dword(dev,i * 4, -@@ -1542,8 +1542,7 @@ void pci_pme_active(struct pci_dev *dev, bool enable) +@@ -1532,8 +1532,7 @@ } out: @@ -68,11 +68,11 @@ } /** -diff --git a/drivers/pci/setup-res.c b/drivers/pci/setup-res.c -index 5717509b..b66bfdb 100644 ---- a/drivers/pci/setup-res.c -+++ b/drivers/pci/setup-res.c -@@ -85,9 +85,9 @@ void pci_update_resource(struct pci_dev *dev, int resno) +Index: linux-3.2.46/drivers/pci/setup-res.c +=================================================================== +--- linux-3.2.46.orig/drivers/pci/setup-res.c 2013-07-26 18:54:07.000000000 +0000 ++++ linux-3.2.46/drivers/pci/setup-res.c 2013-07-26 19:24:53.000000000 +0000 +@@ -85,9 +85,9 @@ } } res->flags &= ~IORESOURCE_UNSET; diff -Nru linux-3.2.46/debian/patches/bugfix/all/sctp-Export-sctp_do_peeloff.patch linux-3.2.46/debian/patches/bugfix/all/sctp-Export-sctp_do_peeloff.patch --- linux-3.2.46/debian/patches/bugfix/all/sctp-Export-sctp_do_peeloff.patch 2013-06-08 16:00:02.000000000 +0000 +++ linux-3.2.46/debian/patches/bugfix/all/sctp-Export-sctp_do_peeloff.patch 2013-07-26 19:30:56.000000000 +0000 @@ -15,9 +15,11 @@ net/sctp/socket.c | 24 +++++++++--------------- 2 files changed, 10 insertions(+), 15 deletions(-) ---- a/include/net/sctp/sctp.h -+++ b/include/net/sctp/sctp.h -@@ -413,6 +413,7 @@ static inline sctp_assoc_t sctp_assoc2id +Index: linux-3.2.46/include/net/sctp/sctp.h +=================================================================== +--- linux-3.2.46.orig/include/net/sctp/sctp.h 2013-07-26 18:52:12.000000000 +0000 ++++ linux-3.2.46/include/net/sctp/sctp.h 2013-07-26 19:30:55.000000000 +0000 +@@ -413,6 +413,7 @@ /* Look up the association by its id. */ struct sctp_association *sctp_id2assoc(struct sock *sk, sctp_assoc_t id); @@ -25,9 +27,11 @@ /* A macro to walk a list of skbs. */ #define sctp_skb_for_each(pos, head, tmp) \ ---- a/net/sctp/socket.c -+++ b/net/sctp/socket.c -@@ -4179,14 +4179,16 @@ static int sctp_getsockopt_autoclose(str +Index: linux-3.2.46/net/sctp/socket.c +=================================================================== +--- linux-3.2.46.orig/net/sctp/socket.c 2013-07-26 18:52:12.000000000 +0000 ++++ linux-3.2.46/net/sctp/socket.c 2013-07-26 19:30:55.000000000 +0000 +@@ -4179,14 +4179,16 @@ } /* Helper routine to branch off an association to a new socket. */ @@ -47,7 +51,7 @@ /* An association cannot be branched off from an already peeled-off * socket, nor is this supported for tcp style sockets. */ -@@ -4215,13 +4217,13 @@ SCTP_STATIC int sctp_do_peeloff(struct s +@@ -4215,13 +4217,13 @@ return err; } @@ -62,7 +66,7 @@ if (len < sizeof(sctp_peeloff_arg_t)) return -EINVAL; -@@ -4229,15 +4231,7 @@ static int sctp_getsockopt_peeloff(struc +@@ -4229,15 +4231,7 @@ if (copy_from_user(&peeloff, optval, len)) return -EFAULT; @@ -79,7 +83,7 @@ if (retval < 0) goto out; -@@ -4248,8 +4242,8 @@ static int sctp_getsockopt_peeloff(struc +@@ -4248,8 +4242,8 @@ goto out; } diff -Nru linux-3.2.46/debian/patches/bugfix/all/snapshot-Implement-compat_ioctl.patch linux-3.2.46/debian/patches/bugfix/all/snapshot-Implement-compat_ioctl.patch --- linux-3.2.46/debian/patches/bugfix/all/snapshot-Implement-compat_ioctl.patch 2013-02-24 03:52:24.000000000 +0000 +++ linux-3.2.46/debian/patches/bugfix/all/snapshot-Implement-compat_ioctl.patch 2013-07-26 19:17:34.000000000 +0000 @@ -14,10 +14,10 @@ kernel/power/user.c | 64 +++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 64 insertions(+) -diff --git a/kernel/power/user.c b/kernel/power/user.c -index 78bdb44..6b1ab7a 100644 ---- a/kernel/power/user.c -+++ b/kernel/power/user.c +Index: linux-3.2.46/kernel/power/user.c +=================================================================== +--- linux-3.2.46.orig/kernel/power/user.c 2013-07-26 18:56:29.000000000 +0000 ++++ linux-3.2.46/kernel/power/user.c 2013-07-26 19:17:33.000000000 +0000 @@ -21,6 +21,7 @@ #include #include @@ -26,7 +26,7 @@ #include #include #include -@@ -380,6 +381,66 @@ static long snapshot_ioctl(struct file *filp, unsigned int cmd, +@@ -480,6 +481,66 @@ return error; } @@ -93,7 +93,7 @@ static const struct file_operations snapshot_fops = { .open = snapshot_open, .release = snapshot_release, -@@ -387,6 +448,9 @@ static const struct file_operations snapshot_fops = { +@@ -487,6 +548,9 @@ .write = snapshot_write, .llseek = no_llseek, .unlocked_ioctl = snapshot_ioctl, @@ -103,6 +103,3 @@ }; static struct miscdevice snapshot_device = { --- -1.7.10 - diff -Nru linux-3.2.46/debian/patches/bugfix/all/udf-Fix-handling-of-i_blocks.patch linux-3.2.46/debian/patches/bugfix/all/udf-Fix-handling-of-i_blocks.patch --- linux-3.2.46/debian/patches/bugfix/all/udf-Fix-handling-of-i_blocks.patch 2013-06-08 17:16:34.000000000 +0000 +++ linux-3.2.46/debian/patches/bugfix/all/udf-Fix-handling-of-i_blocks.patch 2013-07-26 19:31:14.000000000 +0000 @@ -14,11 +14,11 @@ fs/udf/balloc.c | 84 ++++++++++++++++++++++++++++++------------------------- 1 file changed, 46 insertions(+), 38 deletions(-) -diff --git a/fs/udf/balloc.c b/fs/udf/balloc.c -index 987585b..1ba2baa 100644 ---- a/fs/udf/balloc.c -+++ b/fs/udf/balloc.c -@@ -105,7 +105,6 @@ static void udf_add_free_space(struct super_block *sb, u16 partition, u32 cnt) +Index: linux-3.2.46/fs/udf/balloc.c +=================================================================== +--- linux-3.2.46.orig/fs/udf/balloc.c 2013-07-26 18:52:07.000000000 +0000 ++++ linux-3.2.46/fs/udf/balloc.c 2013-07-26 19:31:13.000000000 +0000 +@@ -105,7 +105,6 @@ } static void udf_bitmap_free_blocks(struct super_block *sb, @@ -26,7 +26,7 @@ struct udf_bitmap *bitmap, struct kernel_lb_addr *bloc, uint32_t offset, -@@ -172,7 +171,6 @@ error_return: +@@ -172,7 +171,6 @@ } static int udf_bitmap_prealloc_blocks(struct super_block *sb, @@ -34,7 +34,7 @@ struct udf_bitmap *bitmap, uint16_t partition, uint32_t first_block, uint32_t block_count) -@@ -223,7 +221,6 @@ out: +@@ -223,7 +221,6 @@ } static int udf_bitmap_new_block(struct super_block *sb, @@ -42,7 +42,7 @@ struct udf_bitmap *bitmap, uint16_t partition, uint32_t goal, int *err) { -@@ -349,7 +346,6 @@ error_return: +@@ -349,7 +346,6 @@ } static void udf_table_free_blocks(struct super_block *sb, @@ -50,7 +50,7 @@ struct inode *table, struct kernel_lb_addr *bloc, uint32_t offset, -@@ -581,7 +577,6 @@ error_return: +@@ -581,7 +577,6 @@ } static int udf_table_prealloc_blocks(struct super_block *sb, @@ -58,7 +58,7 @@ struct inode *table, uint16_t partition, uint32_t first_block, uint32_t block_count) { -@@ -643,7 +638,6 @@ static int udf_table_prealloc_blocks(struct super_block *sb, +@@ -643,7 +638,6 @@ } static int udf_table_new_block(struct super_block *sb, @@ -66,7 +66,7 @@ struct inode *table, uint16_t partition, uint32_t goal, int *err) { -@@ -743,18 +737,23 @@ void udf_free_blocks(struct super_block *sb, struct inode *inode, +@@ -743,18 +737,23 @@ struct udf_part_map *map = &UDF_SB(sb)->s_partmaps[partition]; if (map->s_partition_flags & UDF_PART_FLAG_UNALLOC_BITMAP) { @@ -94,7 +94,7 @@ } inline int udf_prealloc_blocks(struct super_block *sb, -@@ -763,29 +762,34 @@ inline int udf_prealloc_blocks(struct super_block *sb, +@@ -763,29 +762,34 @@ uint32_t block_count) { struct udf_part_map *map = &UDF_SB(sb)->s_partmaps[partition]; @@ -145,7 +145,7 @@ } inline int udf_new_block(struct super_block *sb, -@@ -793,25 +797,29 @@ inline int udf_new_block(struct super_block *sb, +@@ -793,25 +797,29 @@ uint16_t partition, uint32_t goal, int *err) { struct udf_part_map *map = &UDF_SB(sb)->s_partmaps[partition]; diff -Nru linux-3.2.46/debian/patches/bugfix/alpha/alpha-add-io-read-write-16-32-be-functions.patch linux-3.2.46/debian/patches/bugfix/alpha/alpha-add-io-read-write-16-32-be-functions.patch --- linux-3.2.46/debian/patches/bugfix/alpha/alpha-add-io-read-write-16-32-be-functions.patch 2013-04-11 03:27:32.000000000 +0000 +++ linux-3.2.46/debian/patches/bugfix/alpha/alpha-add-io-read-write-16-32-be-functions.patch 2013-07-26 19:17:38.000000000 +0000 @@ -23,11 +23,11 @@ arch/alpha/include/asm/io.h | 5 +++++ 1 files changed, 5 insertions(+), 0 deletions(-) -diff --git a/arch/alpha/include/asm/io.h b/arch/alpha/include/asm/io.h -index 56ff965..6365ef2 100644 ---- a/arch/alpha/include/asm/io.h -+++ b/arch/alpha/include/asm/io.h -@@ -490,6 +490,11 @@ extern inline void writeq(u64 b, volatile void __iomem *addr) +Index: linux-3.2.46/arch/alpha/include/asm/io.h +=================================================================== +--- linux-3.2.46.orig/arch/alpha/include/asm/io.h 2013-07-26 18:56:28.000000000 +0000 ++++ linux-3.2.46/arch/alpha/include/asm/io.h 2013-07-26 19:17:37.000000000 +0000 +@@ -490,6 +490,11 @@ } #endif @@ -39,6 +39,3 @@ #define inb_p inb #define inw_p inw #define inl_p inl --- -1.7.4.3 - diff -Nru linux-3.2.46/debian/patches/bugfix/alpha/alpha-use-large-data-model.diff linux-3.2.46/debian/patches/bugfix/alpha/alpha-use-large-data-model.diff --- linux-3.2.46/debian/patches/bugfix/alpha/alpha-use-large-data-model.diff 2013-04-11 03:27:32.000000000 +0000 +++ linux-3.2.46/debian/patches/bugfix/alpha/alpha-use-large-data-model.diff 2013-07-26 19:24:57.000000000 +0000 @@ -12,11 +12,11 @@ Alpha maintainer why using gcc-4.6 should have such an effect but did not get back a particularly informative answer. -diff --git a/arch/alpha/Makefile b/arch/alpha/Makefile -index 4759fe7..b5d44bd 100644 ---- a/arch/alpha/Makefile -+++ b/arch/alpha/Makefile -@@ -12,7 +12,7 @@ NM := $(NM) -B +Index: linux-3.2.46/arch/alpha/Makefile +=================================================================== +--- linux-3.2.46.orig/arch/alpha/Makefile 2013-07-26 18:54:06.000000000 +0000 ++++ linux-3.2.46/arch/alpha/Makefile 2013-07-26 19:24:56.000000000 +0000 +@@ -12,7 +12,7 @@ LDFLAGS_vmlinux := -static -N #-relax CHECKFLAGS += -D__alpha__ -m64 diff -Nru linux-3.2.46/debian/patches/bugfix/arm/ARM-topdown-mmap.patch linux-3.2.46/debian/patches/bugfix/arm/ARM-topdown-mmap.patch --- linux-3.2.46/debian/patches/bugfix/arm/ARM-topdown-mmap.patch 2013-02-24 03:52:24.000000000 +0000 +++ linux-3.2.46/debian/patches/bugfix/arm/ARM-topdown-mmap.patch 2013-07-26 19:17:37.000000000 +0000 @@ -23,11 +23,11 @@ arch/arm/mm/mmap.c | 173 ++++++++++++++++++++++++++++++++++++-- 3 files changed, 171 insertions(+), 5 deletions(-) -diff --git a/arch/arm/include/asm/pgtable.h b/arch/arm/include/asm/pgtable.h -index 9451dce..2f659e2 100644 ---- a/arch/arm/include/asm/pgtable.h -+++ b/arch/arm/include/asm/pgtable.h -@@ -336,6 +336,7 @@ static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) +Index: linux-3.2.46/arch/arm/include/asm/pgtable.h +=================================================================== +--- linux-3.2.46.orig/arch/arm/include/asm/pgtable.h 2013-07-26 18:56:28.000000000 +0000 ++++ linux-3.2.46/arch/arm/include/asm/pgtable.h 2013-07-26 19:17:36.000000000 +0000 +@@ -338,6 +338,7 @@ * We provide our own arch_get_unmapped_area to cope with VIPT caches. */ #define HAVE_ARCH_UNMAPPED_AREA @@ -35,11 +35,11 @@ /* * remap a physical page `pfn' of size `size' with page protection `prot' -diff --git a/arch/arm/include/asm/processor.h b/arch/arm/include/asm/processor.h -index b2d9df5..ce280b8 100644 ---- a/arch/arm/include/asm/processor.h -+++ b/arch/arm/include/asm/processor.h -@@ -123,6 +123,8 @@ static inline void prefetch(const void *ptr) +Index: linux-3.2.46/arch/arm/include/asm/processor.h +=================================================================== +--- linux-3.2.46.orig/arch/arm/include/asm/processor.h 2013-07-26 18:56:28.000000000 +0000 ++++ linux-3.2.46/arch/arm/include/asm/processor.h 2013-07-26 19:17:36.000000000 +0000 +@@ -123,6 +123,8 @@ #endif @@ -48,10 +48,10 @@ #endif #endif /* __ASM_ARM_PROCESSOR_H */ -diff --git a/arch/arm/mm/mmap.c b/arch/arm/mm/mmap.c -index 44b628e..ce8cb19 100644 ---- a/arch/arm/mm/mmap.c -+++ b/arch/arm/mm/mmap.c +Index: linux-3.2.46/arch/arm/mm/mmap.c +=================================================================== +--- linux-3.2.46.orig/arch/arm/mm/mmap.c 2013-07-26 18:56:28.000000000 +0000 ++++ linux-3.2.46/arch/arm/mm/mmap.c 2013-07-26 19:17:36.000000000 +0000 @@ -11,10 +11,49 @@ #include #include @@ -102,7 +102,7 @@ /* * We need to ensure that shared mappings are correctly aligned to * avoid aliasing issues with VIPT caches. We need to ensure that -@@ -68,13 +107,9 @@ arch_get_unmapped_area(struct file *filp, unsigned long addr, +@@ -68,13 +107,9 @@ if (len > mm->cached_hole_size) { start_addr = addr = mm->free_area_cache; } else { @@ -117,7 +117,7 @@ full_search: if (do_align) -@@ -111,6 +146,134 @@ full_search: +@@ -111,6 +146,134 @@ } } @@ -252,6 +252,3 @@ /* * You really shouldn't be using read() or write() on /dev/mem. This --- -1.7.10 - diff -Nru linux-3.2.46/debian/patches/bugfix/arm/ixp4xx_iobe.patch linux-3.2.46/debian/patches/bugfix/arm/ixp4xx_iobe.patch --- linux-3.2.46/debian/patches/bugfix/arm/ixp4xx_iobe.patch 2013-02-24 03:52:24.000000000 +0000 +++ linux-3.2.46/debian/patches/bugfix/arm/ixp4xx_iobe.patch 2013-07-26 19:17:28.000000000 +0000 @@ -14,11 +14,11 @@ Signed-off-by: Arnaud Patard -Index: linux-3.1/arch/arm/mach-ixp4xx/include/mach/io.h +Index: linux-3.2.46/arch/arm/mach-ixp4xx/include/mach/io.h =================================================================== ---- linux-3.1.orig/arch/arm/mach-ixp4xx/include/mach/io.h 2011-11-13 14:14:50.662853902 +0100 -+++ linux-3.1/arch/arm/mach-ixp4xx/include/mach/io.h 2011-11-13 14:19:38.522841236 +0100 -@@ -387,6 +387,20 @@ static inline unsigned int ioread16(cons +--- linux-3.2.46.orig/arch/arm/mach-ixp4xx/include/mach/io.h 2013-07-26 18:56:31.000000000 +0000 ++++ linux-3.2.46/arch/arm/mach-ixp4xx/include/mach/io.h 2013-07-26 19:17:27.000000000 +0000 +@@ -385,6 +385,20 @@ #endif } @@ -39,7 +39,7 @@ #define ioread16_rep(p, v, c) ioread16_rep(p, v, c) static inline void ioread16_rep(const void __iomem *addr, void *vaddr, u32 count) -@@ -417,6 +431,21 @@ static inline unsigned int ioread32(cons +@@ -415,6 +429,21 @@ } } @@ -61,7 +61,7 @@ #define ioread32_rep(p, v, c) ioread32_rep(p, v, c) static inline void ioread32_rep(const void __iomem *addr, void *vaddr, u32 count) -@@ -475,6 +504,20 @@ static inline void iowrite16(u16 value, +@@ -473,6 +502,20 @@ #endif } @@ -82,7 +82,7 @@ #define iowrite16_rep(p, v, c) iowrite16_rep(p, v, c) static inline void iowrite16_rep(void __iomem *addr, const void *vaddr, u32 count) -@@ -504,6 +547,20 @@ static inline void iowrite32(u32 value, +@@ -502,6 +545,20 @@ #endif } diff -Nru linux-3.2.46/debian/patches/bugfix/ia64/hardcode-arch-script-output.patch linux-3.2.46/debian/patches/bugfix/ia64/hardcode-arch-script-output.patch --- linux-3.2.46/debian/patches/bugfix/ia64/hardcode-arch-script-output.patch 2013-04-11 03:27:32.000000000 +0000 +++ linux-3.2.46/debian/patches/bugfix/ia64/hardcode-arch-script-output.patch 2013-07-26 19:17:06.000000000 +0000 @@ -21,11 +21,11 @@ altogether, and allow for the possibility of other archs to provide their own scripts in the future. -diff --git a/arch/ia64/Makefile b/arch/ia64/Makefile -index e7cbaa0..c8af869 100644 ---- a/arch/ia64/Makefile -+++ b/arch/ia64/Makefile -@@ -30,16 +30,7 @@ cflags-y := -pipe $(EXTRA) -ffixed-r13 -mfixed-range=f12-f15,f32-f127 \ +Index: linux-3.2.46/arch/ia64/Makefile +=================================================================== +--- linux-3.2.46.orig/arch/ia64/Makefile 2013-07-26 18:56:38.000000000 +0000 ++++ linux-3.2.46/arch/ia64/Makefile 2013-07-26 19:17:05.000000000 +0000 +@@ -30,16 +30,7 @@ -falign-functions=32 -frename-registers -fno-optimize-sibling-calls KBUILD_CFLAGS_KERNEL := -mconstant-gp @@ -43,7 +43,7 @@ KBUILD_CFLAGS += $(cflags-y) head-y := arch/ia64/kernel/head.o arch/ia64/kernel/init_task.o -@@ -69,7 +60,7 @@ boot := arch/ia64/hp/sim/boot +@@ -68,7 +59,7 @@ PHONY += boot compressed check @@ -52,7 +52,7 @@ compressed: vmlinux.gz -@@ -78,9 +69,6 @@ vmlinuz: vmlinux.gz +@@ -77,9 +68,6 @@ vmlinux.gz: vmlinux $(Q)$(MAKE) $(build)=$(boot) $@ @@ -62,7 +62,7 @@ archclean: $(Q)$(MAKE) $(clean)=$(boot) -@@ -96,7 +84,6 @@ define archhelp +@@ -95,7 +83,6 @@ echo '* compressed - Build compressed kernel image' echo ' install - Install compressed kernel image' echo ' boot - Build vmlinux and bootloader for Ski simulator' diff -Nru linux-3.2.46/debian/patches/bugfix/ia64/nouveau-ACPI-support-is-dependent-on-X86.patch linux-3.2.46/debian/patches/bugfix/ia64/nouveau-ACPI-support-is-dependent-on-X86.patch --- linux-3.2.46/debian/patches/bugfix/ia64/nouveau-ACPI-support-is-dependent-on-X86.patch 2013-02-24 03:52:24.000000000 +0000 +++ linux-3.2.46/debian/patches/bugfix/ia64/nouveau-ACPI-support-is-dependent-on-X86.patch 2013-07-26 19:27:13.000000000 +0000 @@ -13,11 +13,11 @@ drivers/gpu/drm/nouveau/nouveau_drv.h | 2 +- 3 files changed, 5 insertions(+), 3 deletions(-) -Index: linux/drivers/gpu/drm/nouveau/Kconfig +Index: linux-3.2.46/drivers/gpu/drm/nouveau/Kconfig =================================================================== ---- linux.orig/drivers/gpu/drm/nouveau/Kconfig -+++ linux/drivers/gpu/drm/nouveau/Kconfig -@@ -11,8 +11,8 @@ config DRM_NOUVEAU +--- linux-3.2.46.orig/drivers/gpu/drm/nouveau/Kconfig 2013-07-26 19:26:22.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/nouveau/Kconfig 2013-07-26 19:27:12.000000000 +0000 +@@ -11,8 +11,8 @@ select FRAMEBUFFER_CONSOLE if !EXPERT select FB_BACKLIGHT if DRM_NOUVEAU_BACKLIGHT select ACPI_VIDEO if ACPI && X86 && BACKLIGHT_CLASS_DEVICE && VIDEO_OUTPUT_CONTROL && INPUT @@ -28,11 +28,11 @@ select POWER_SUPPLY help Choose this option for open-source nVidia support. -Index: linux/drivers/gpu/drm/nouveau/Makefile +Index: linux-3.2.46/drivers/gpu/drm/nouveau/Makefile =================================================================== ---- linux.orig/drivers/gpu/drm/nouveau/Makefile -+++ linux/drivers/gpu/drm/nouveau/Makefile -@@ -42,6 +42,8 @@ nouveau-y := nouveau_drv.o nouveau_state +--- linux-3.2.46.orig/drivers/gpu/drm/nouveau/Makefile 2013-07-26 19:26:22.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/nouveau/Makefile 2013-07-26 19:27:12.000000000 +0000 +@@ -42,6 +42,8 @@ nouveau-$(CONFIG_DRM_NOUVEAU_DEBUG) += nouveau_debugfs.o nouveau-$(CONFIG_COMPAT) += nouveau_ioc32.o nouveau-$(CONFIG_DRM_NOUVEAU_BACKLIGHT) += nouveau_backlight.o @@ -41,11 +41,11 @@ +endif obj-$(CONFIG_DRM_NOUVEAU)+= nouveau.o -Index: linux/drivers/gpu/drm/nouveau/nouveau_drv.h +Index: linux-3.2.46/drivers/gpu/drm/nouveau/nouveau_drv.h =================================================================== ---- linux.orig/drivers/gpu/drm/nouveau/nouveau_drv.h -+++ linux/drivers/gpu/drm/nouveau/nouveau_drv.h -@@ -1095,7 +1095,7 @@ extern int nouveau_dma_wait(struct nouv +--- linux-3.2.46.orig/drivers/gpu/drm/nouveau/nouveau_drv.h 2013-07-26 19:26:23.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/nouveau/nouveau_drv.h 2013-07-26 19:27:12.000000000 +0000 +@@ -1095,7 +1095,7 @@ /* nouveau_acpi.c */ #define ROM_BIOS_PAGE 4096 diff -Nru linux-3.2.46/debian/patches/bugfix/mips/disable-advansys.patch linux-3.2.46/debian/patches/bugfix/mips/disable-advansys.patch --- linux-3.2.46/debian/patches/bugfix/mips/disable-advansys.patch 2013-02-24 03:52:24.000000000 +0000 +++ linux-3.2.46/debian/patches/bugfix/mips/disable-advansys.patch 2013-07-26 19:17:08.000000000 +0000 @@ -11,9 +11,11 @@ But report: http://www.mail-archive.com/linux-scsi@vger.kernel.org/msg12773.html ---- a/drivers/scsi/Kconfig 2007-12-27 19:16:18.000000000 +0000 -+++ b/drivers/scsi/Kconfig 2007-12-27 19:16:58.000000000 +0000 -@@ -523,6 +523,7 @@ +Index: linux-3.2.46/drivers/scsi/Kconfig +=================================================================== +--- linux-3.2.46.orig/drivers/scsi/Kconfig 2013-07-26 18:56:38.000000000 +0000 ++++ linux-3.2.46/drivers/scsi/Kconfig 2013-07-26 19:17:07.000000000 +0000 +@@ -584,6 +584,7 @@ tristate "AdvanSys SCSI support" depends on SCSI && VIRT_TO_BUS depends on ISA || EISA || PCI diff -Nru linux-3.2.46/debian/patches/bugfix/powerpc/lpar-console.patch linux-3.2.46/debian/patches/bugfix/powerpc/lpar-console.patch --- linux-3.2.46/debian/patches/bugfix/powerpc/lpar-console.patch 2013-02-24 03:52:24.000000000 +0000 +++ linux-3.2.46/debian/patches/bugfix/powerpc/lpar-console.patch 2013-07-26 19:17:10.000000000 +0000 @@ -7,9 +7,11 @@ Original version by Bastian Blank . ---- a/drivers/tty/hvc/hvc_vio.c -+++ b/drivers/tty/hvc/hvc_vio.c -@@ -48,6 +48,7 @@ +Index: linux-3.2.46/drivers/tty/hvc/hvc_vio.c +=================================================================== +--- linux-3.2.46.orig/drivers/tty/hvc/hvc_vio.c 2013-07-26 18:56:37.000000000 +0000 ++++ linux-3.2.46/drivers/tty/hvc/hvc_vio.c 2013-07-26 19:17:10.000000000 +0000 +@@ -49,6 +49,7 @@ #include #include #include @@ -17,7 +19,7 @@ #include "hvc_console.h" -@@ -446,7 +447,9 @@ void __init hvc_vio_init_early(void) +@@ -447,7 +448,9 @@ if (hvterm_priv0.proto == HV_PROTOCOL_HVSI) goto out; #endif diff -Nru linux-3.2.46/debian/patches/bugfix/x86/drm-i915-add-quirk_invert_brightness-for-ncr-machine.patch linux-3.2.46/debian/patches/bugfix/x86/drm-i915-add-quirk_invert_brightness-for-ncr-machine.patch --- linux-3.2.46/debian/patches/bugfix/x86/drm-i915-add-quirk_invert_brightness-for-ncr-machine.patch 2013-04-28 20:19:02.000000000 +0000 +++ linux-3.2.46/debian/patches/bugfix/x86/drm-i915-add-quirk_invert_brightness-for-ncr-machine.patch 2013-07-26 19:27:21.000000000 +0000 @@ -19,8 +19,10 @@ drivers/gpu/drm/i915/intel_display.c | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) ---- a/drivers/gpu/drm/i915/intel_display.c -+++ b/drivers/gpu/drm/i915/intel_display.c +Index: linux-3.2.46/drivers/gpu/drm/i915/intel_display.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/i915/intel_display.c 2013-07-26 19:27:19.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/i915/intel_display.c 2013-07-26 19:27:20.000000000 +0000 @@ -25,6 +25,7 @@ */ @@ -29,7 +31,7 @@ #include #include #include -@@ -9172,6 +9173,34 @@ struct intel_quirk { +@@ -9177,6 +9178,34 @@ void (*hook)(struct drm_device *dev); }; @@ -64,7 +66,7 @@ struct intel_quirk intel_quirks[] = { /* HP Mini needs pipe A force quirk (LP: #322104) */ { 0x27ae, 0x103c, 0x361a, quirk_pipea_force }, -@@ -9217,6 +9246,10 @@ static void intel_init_quirks(struct drm +@@ -9222,6 +9251,10 @@ q->subsystem_device == PCI_ANY_ID)) q->hook(dev); } diff -Nru linux-3.2.46/debian/patches/bugfix/x86/drm-i915-add-quirk-to-invert-brightness-on-emachines-e725.patch linux-3.2.46/debian/patches/bugfix/x86/drm-i915-add-quirk-to-invert-brightness-on-emachines-e725.patch --- linux-3.2.46/debian/patches/bugfix/x86/drm-i915-add-quirk-to-invert-brightness-on-emachines-e725.patch 2013-04-28 20:19:02.000000000 +0000 +++ linux-3.2.46/debian/patches/bugfix/x86/drm-i915-add-quirk-to-invert-brightness-on-emachines-e725.patch 2013-07-26 19:27:23.000000000 +0000 @@ -10,11 +10,11 @@ Signed-off-by: Jani Nikula Signed-off-by: Daniel Vetter --- -diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c -index 44f9d8f..8575a62 100644 ---- a/drivers/gpu/drm/i915/intel_display.c -+++ b/drivers/gpu/drm/i915/intel_display.c -@@ -8602,6 +8602,9 @@ static struct intel_quirk intel_quirks[] = { +Index: linux-3.2.46/drivers/gpu/drm/i915/intel_display.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/i915/intel_display.c 2013-07-26 19:27:21.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/i915/intel_display.c 2013-07-26 19:27:23.000000000 +0000 +@@ -9237,6 +9237,9 @@ /* Acer/eMachines G725 */ { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness }, diff -Nru linux-3.2.46/debian/patches/bugfix/x86/drm-i915-add-quirk-to-invert-brightness-on-emachines-g725.patch linux-3.2.46/debian/patches/bugfix/x86/drm-i915-add-quirk-to-invert-brightness-on-emachines-g725.patch --- linux-3.2.46/debian/patches/bugfix/x86/drm-i915-add-quirk-to-invert-brightness-on-emachines-g725.patch 2013-04-28 20:19:02.000000000 +0000 +++ linux-3.2.46/debian/patches/bugfix/x86/drm-i915-add-quirk-to-invert-brightness-on-emachines-g725.patch 2013-07-26 19:27:22.000000000 +0000 @@ -9,11 +9,11 @@ Signed-off-by: Jani Nikula Signed-off-by: Daniel Vetter --- -diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c -index 7725446..44f9d8f 100644 ---- a/drivers/gpu/drm/i915/intel_display.c -+++ b/drivers/gpu/drm/i915/intel_display.c -@@ -8599,6 +8599,9 @@ static struct intel_quirk intel_quirks[] = { +Index: linux-3.2.46/drivers/gpu/drm/i915/intel_display.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/i915/intel_display.c 2013-07-26 19:27:20.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/i915/intel_display.c 2013-07-26 19:27:21.000000000 +0000 +@@ -9234,6 +9234,9 @@ /* Acer Aspire 5734Z must invert backlight brightness */ { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness }, diff -Nru linux-3.2.46/debian/patches/bugfix/x86/drm-i915-add-quirk-to-invert-brightness-on-packard-bell-ncl20.patch linux-3.2.46/debian/patches/bugfix/x86/drm-i915-add-quirk-to-invert-brightness-on-packard-bell-ncl20.patch --- linux-3.2.46/debian/patches/bugfix/x86/drm-i915-add-quirk-to-invert-brightness-on-packard-bell-ncl20.patch 2013-04-28 20:19:02.000000000 +0000 +++ linux-3.2.46/debian/patches/bugfix/x86/drm-i915-add-quirk-to-invert-brightness-on-packard-bell-ncl20.patch 2013-07-26 19:27:25.000000000 +0000 @@ -9,11 +9,11 @@ Signed-off-by: Jani Nikula Signed-off-by: Daniel Vetter --- -diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c -index 8575a62..7262786 100644 ---- a/drivers/gpu/drm/i915/intel_display.c -+++ b/drivers/gpu/drm/i915/intel_display.c -@@ -8605,6 +8605,9 @@ static struct intel_quirk intel_quirks[] = { +Index: linux-3.2.46/drivers/gpu/drm/i915/intel_display.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/i915/intel_display.c 2013-07-26 19:27:23.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/i915/intel_display.c 2013-07-26 19:27:24.000000000 +0000 +@@ -9240,6 +9240,9 @@ /* Acer/eMachines e725 */ { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness }, diff -Nru linux-3.2.46/debian/patches/bugfix/x86/drm-i915-Close-race-between-processing-unpin-task-an.patch linux-3.2.46/debian/patches/bugfix/x86/drm-i915-Close-race-between-processing-unpin-task-an.patch --- linux-3.2.46/debian/patches/bugfix/x86/drm-i915-Close-race-between-processing-unpin-task-an.patch 2013-02-24 03:52:24.000000000 +0000 +++ linux-3.2.46/debian/patches/bugfix/x86/drm-i915-Close-race-between-processing-unpin-task-an.patch 2013-07-26 19:27:28.000000000 +0000 @@ -38,9 +38,11 @@ drivers/gpu/drm/i915/intel_drv.h | 5 ++++- 4 files changed, 41 insertions(+), 11 deletions(-) ---- a/drivers/gpu/drm/i915/i915_debugfs.c -+++ b/drivers/gpu/drm/i915/i915_debugfs.c -@@ -340,7 +340,7 @@ static int i915_gem_pageflip_info(struct +Index: linux-3.2.46/drivers/gpu/drm/i915/i915_debugfs.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/i915/i915_debugfs.c 2013-07-26 19:26:55.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/i915/i915_debugfs.c 2013-07-26 19:27:26.000000000 +0000 +@@ -340,7 +340,7 @@ seq_printf(m, "No flip due on pipe %c (plane %c)\n", pipe, plane); } else { @@ -49,7 +51,7 @@ seq_printf(m, "Flip queued on pipe %c (plane %c)\n", pipe, plane); } else { -@@ -351,7 +351,7 @@ static int i915_gem_pageflip_info(struct +@@ -351,7 +351,7 @@ seq_printf(m, "Stall check enabled, "); else seq_printf(m, "Stall check waiting for page flip ioctl, "); @@ -58,9 +60,11 @@ if (work->old_fb_obj) { struct drm_i915_gem_object *obj = work->old_fb_obj; ---- a/drivers/gpu/drm/i915/i915_irq.c -+++ b/drivers/gpu/drm/i915/i915_irq.c -@@ -1251,7 +1251,9 @@ static void i915_pageflip_stall_check(st +Index: linux-3.2.46/drivers/gpu/drm/i915/i915_irq.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/i915/i915_irq.c 2013-07-26 19:27:13.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/i915/i915_irq.c 2013-07-26 19:27:26.000000000 +0000 +@@ -1251,7 +1251,9 @@ spin_lock_irqsave(&dev->event_lock, flags); work = intel_crtc->unpin_work; @@ -71,9 +75,11 @@ /* Either the pending flip IRQ arrived, or we're too early. Don't check */ spin_unlock_irqrestore(&dev->event_lock, flags); return; ---- a/drivers/gpu/drm/i915/intel_display.c -+++ b/drivers/gpu/drm/i915/intel_display.c -@@ -7234,11 +7234,18 @@ static void do_intel_finish_page_flip(st +Index: linux-3.2.46/drivers/gpu/drm/i915/intel_display.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/i915/intel_display.c 2013-07-26 19:27:24.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/i915/intel_display.c 2013-07-26 19:27:26.000000000 +0000 +@@ -7242,11 +7242,18 @@ spin_lock_irqsave(&dev->event_lock, flags); work = intel_crtc->unpin_work; @@ -93,7 +99,7 @@ intel_crtc->unpin_work = NULL; if (work->event) { -@@ -7310,16 +7317,25 @@ void intel_prepare_page_flip(struct drm_ +@@ -7318,16 +7325,25 @@ to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]); unsigned long flags; @@ -125,7 +131,7 @@ static int intel_gen2_queue_flip(struct drm_device *dev, struct drm_crtc *crtc, struct drm_framebuffer *fb, -@@ -7356,6 +7372,8 @@ static int intel_gen2_queue_flip(struct +@@ -7364,6 +7380,8 @@ OUT_RING(fb->pitches[0]); OUT_RING(obj->gtt_offset + offset); OUT_RING(0); /* aux display base address, unused */ @@ -134,7 +140,7 @@ ADVANCE_LP_RING(); return 0; -@@ -7399,6 +7417,7 @@ static int intel_gen3_queue_flip(struct +@@ -7407,6 +7425,7 @@ OUT_RING(obj->gtt_offset + offset); OUT_RING(MI_NOOP); @@ -142,7 +148,7 @@ ADVANCE_LP_RING(); return 0; -@@ -7442,6 +7461,8 @@ static int intel_gen4_queue_flip(struct +@@ -7450,6 +7469,8 @@ pf = 0; pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; OUT_RING(pf | pipesrc); @@ -151,7 +157,7 @@ ADVANCE_LP_RING(); return 0; -@@ -7483,6 +7504,8 @@ static int intel_gen6_queue_flip(struct +@@ -7491,6 +7512,8 @@ pf = 0; pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; OUT_RING(pf | pipesrc); @@ -160,7 +166,7 @@ ADVANCE_LP_RING(); return 0; -@@ -7537,6 +7560,8 @@ static int intel_gen7_queue_flip(struct +@@ -7545,6 +7568,8 @@ intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode)); intel_ring_emit(ring, (obj->gtt_offset)); intel_ring_emit(ring, (MI_NOOP)); @@ -169,9 +175,11 @@ intel_ring_advance(ring); return 0; ---- a/drivers/gpu/drm/i915/intel_drv.h -+++ b/drivers/gpu/drm/i915/intel_drv.h -@@ -277,7 +277,10 @@ struct intel_unpin_work { +Index: linux-3.2.46/drivers/gpu/drm/i915/intel_drv.h +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/i915/intel_drv.h 2013-07-26 19:26:22.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/i915/intel_drv.h 2013-07-26 19:27:26.000000000 +0000 +@@ -277,7 +277,10 @@ struct drm_i915_gem_object *old_fb_obj; struct drm_i915_gem_object *pending_flip_obj; struct drm_pending_vblank_event *event; diff -Nru linux-3.2.46/debian/patches/bugfix/x86/drm-i915-Disable-AsyncFlip-performance-optimisations.patch linux-3.2.46/debian/patches/bugfix/x86/drm-i915-Disable-AsyncFlip-performance-optimisations.patch --- linux-3.2.46/debian/patches/bugfix/x86/drm-i915-Disable-AsyncFlip-performance-optimisations.patch 2013-02-24 03:52:24.000000000 +0000 +++ linux-3.2.46/debian/patches/bugfix/x86/drm-i915-Disable-AsyncFlip-performance-optimisations.patch 2013-07-26 19:27:37.000000000 +0000 @@ -23,9 +23,11 @@ drivers/gpu/drm/i915/intel_ringbuffer.c | 19 +++++++++++++------ 2 files changed, 14 insertions(+), 6 deletions(-) ---- a/drivers/gpu/drm/i915/i915_reg.h -+++ b/drivers/gpu/drm/i915/i915_reg.h -@@ -400,6 +400,7 @@ +Index: linux-3.2.46/drivers/gpu/drm/i915/i915_reg.h +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/i915/i915_reg.h 2013-07-26 19:26:22.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/i915/i915_reg.h 2013-07-26 19:27:36.000000000 +0000 +@@ -447,6 +447,7 @@ #define MI_MODE 0x0209c # define VS_TIMER_DISPATCH (1 << 6) # define MI_FLUSH_ENABLE (1 << 12) @@ -33,9 +35,11 @@ #define GEN6_GT_MODE 0x20d0 #define GEN6_GT_MODE_HI (1 << 9) ---- a/drivers/gpu/drm/i915/intel_ringbuffer.c -+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c -@@ -399,12 +399,20 @@ static int init_render_ring(struct intel +Index: linux-3.2.46/drivers/gpu/drm/i915/intel_ringbuffer.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/i915/intel_ringbuffer.c 2013-07-26 19:27:13.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/i915/intel_ringbuffer.c 2013-07-26 19:27:36.000000000 +0000 +@@ -397,12 +397,20 @@ if (INTEL_INFO(dev)->gen > 3) { int mode = VS_TIMER_DISPATCH << 16 | VS_TIMER_DISPATCH; I915_WRITE(MI_MODE, mode); diff -Nru linux-3.2.46/debian/patches/bugfix/x86/drm-i915-dump-UTS_RELEASE-into-the-error_state.patch linux-3.2.46/debian/patches/bugfix/x86/drm-i915-dump-UTS_RELEASE-into-the-error_state.patch --- linux-3.2.46/debian/patches/bugfix/x86/drm-i915-dump-UTS_RELEASE-into-the-error_state.patch 2013-02-24 03:52:24.000000000 +0000 +++ linux-3.2.46/debian/patches/bugfix/x86/drm-i915-dump-UTS_RELEASE-into-the-error_state.patch 2013-07-26 19:27:39.000000000 +0000 @@ -15,8 +15,10 @@ drivers/gpu/drm/i915/i915_debugfs.c | 2 ++ 1 file changed, 2 insertions(+) ---- a/drivers/gpu/drm/i915/i915_debugfs.c -+++ b/drivers/gpu/drm/i915/i915_debugfs.c +Index: linux-3.2.46/drivers/gpu/drm/i915/i915_debugfs.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/i915/i915_debugfs.c 2013-07-26 19:27:26.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/i915/i915_debugfs.c 2013-07-26 19:27:38.000000000 +0000 @@ -30,6 +30,7 @@ #include #include @@ -25,7 +27,7 @@ #include "drmP.h" #include "drm.h" #include "intel_drv.h" -@@ -755,6 +756,7 @@ static int i915_error_state(struct seq_f +@@ -750,6 +751,7 @@ seq_printf(m, "Time: %ld s %ld us\n", error->time.tv_sec, error->time.tv_usec); diff -Nru linux-3.2.46/debian/patches/bugfix/x86/drm-i915-GFX_MODE-Flush-TLB-Invalidate-Mode-must-be-.patch linux-3.2.46/debian/patches/bugfix/x86/drm-i915-GFX_MODE-Flush-TLB-Invalidate-Mode-must-be-.patch --- linux-3.2.46/debian/patches/bugfix/x86/drm-i915-GFX_MODE-Flush-TLB-Invalidate-Mode-must-be-.patch 2013-02-24 03:52:24.000000000 +0000 +++ linux-3.2.46/debian/patches/bugfix/x86/drm-i915-GFX_MODE-Flush-TLB-Invalidate-Mode-must-be-.patch 2013-07-26 19:27:38.000000000 +0000 @@ -22,9 +22,11 @@ drivers/gpu/drm/i915/intel_ringbuffer.c | 5 +++++ 1 file changed, 5 insertions(+) ---- a/drivers/gpu/drm/i915/intel_ringbuffer.c -+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c -@@ -407,6 +407,11 @@ static int init_render_ring(struct intel +Index: linux-3.2.46/drivers/gpu/drm/i915/intel_ringbuffer.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/i915/intel_ringbuffer.c 2013-07-26 19:27:36.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/i915/intel_ringbuffer.c 2013-07-26 19:27:37.000000000 +0000 +@@ -406,6 +406,11 @@ if (INTEL_INFO(dev)->gen >= 6) I915_WRITE(MI_MODE, GFX_MODE_ENABLE(ASYNC_FLIP_PERF_DISABLE)); diff -Nru linux-3.2.46/debian/patches/bugfix/x86/drm-i915-i8xx-interrupt-handler.patch linux-3.2.46/debian/patches/bugfix/x86/drm-i915-i8xx-interrupt-handler.patch --- linux-3.2.46/debian/patches/bugfix/x86/drm-i915-i8xx-interrupt-handler.patch 2013-03-03 02:14:00.000000000 +0000 +++ linux-3.2.46/debian/patches/bugfix/x86/drm-i915-i8xx-interrupt-handler.patch 2013-07-26 19:27:14.000000000 +0000 @@ -31,11 +31,11 @@ drivers/gpu/drm/i915/intel_ringbuffer.c | 18 +++- 2 files changed, 171 insertions(+), 8 deletions(-) -diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c -index 578ddfc..ac5a50d 100644 ---- a/drivers/gpu/drm/i915/i915_irq.c -+++ b/drivers/gpu/drm/i915/i915_irq.c -@@ -2083,6 +2083,152 @@ static void i915_driver_irq_uninstall(struct drm_device * dev) +Index: linux-3.2.46/drivers/gpu/drm/i915/i915_irq.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/i915/i915_irq.c 2013-07-26 19:26:22.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/i915/i915_irq.c 2013-07-26 19:27:13.000000000 +0000 +@@ -2140,6 +2140,152 @@ I915_WRITE(IIR, I915_READ(IIR)); } @@ -188,7 +188,7 @@ void intel_irq_init(struct drm_device *dev) { dev->driver->get_vblank_counter = i915_get_vblank_counter; -@@ -2114,10 +2260,17 @@ void intel_irq_init(struct drm_device *dev) +@@ -2171,10 +2317,17 @@ dev->driver->enable_vblank = ironlake_enable_vblank; dev->driver->disable_vblank = ironlake_disable_vblank; } else { @@ -210,11 +210,11 @@ dev->driver->enable_vblank = i915_enable_vblank; dev->driver->disable_vblank = i915_disable_vblank; } -diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c -index 19085c0..57a7363 100644 ---- a/drivers/gpu/drm/i915/intel_ringbuffer.c -+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c -@@ -689,16 +689,26 @@ static void +Index: linux-3.2.46/drivers/gpu/drm/i915/intel_ringbuffer.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/i915/intel_ringbuffer.c 2013-07-26 19:26:22.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/i915/intel_ringbuffer.c 2013-07-26 19:27:13.000000000 +0000 +@@ -686,16 +686,26 @@ i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask) { dev_priv->irq_mask &= ~mask; @@ -245,6 +245,3 @@ } static bool --- -1.7.10.4 - diff -Nru linux-3.2.46/debian/patches/bugfix/x86/drm-i915-kick-any-firmware-framebuffers-before-claim.patch linux-3.2.46/debian/patches/bugfix/x86/drm-i915-kick-any-firmware-framebuffers-before-claim.patch --- linux-3.2.46/debian/patches/bugfix/x86/drm-i915-kick-any-firmware-framebuffers-before-claim.patch 2013-02-24 03:52:24.000000000 +0000 +++ linux-3.2.46/debian/patches/bugfix/x86/drm-i915-kick-any-firmware-framebuffers-before-claim.patch 2013-07-26 19:27:10.000000000 +0000 @@ -48,11 +48,11 @@ drivers/gpu/drm/i915/i915_dma.c | 37 ++++++++++++++++++++++++++++++------- 1 file changed, 30 insertions(+), 7 deletions(-) -diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c -index f947926..36822b9 100644 ---- a/drivers/gpu/drm/i915/i915_dma.c -+++ b/drivers/gpu/drm/i915/i915_dma.c -@@ -1401,6 +1401,27 @@ i915_mtrr_setup(struct drm_i915_private *dev_priv, unsigned long base, +Index: linux-3.2.46/drivers/gpu/drm/i915/i915_dma.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/i915/i915_dma.c 2013-07-26 19:26:22.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/i915/i915_dma.c 2013-07-26 19:27:09.000000000 +0000 +@@ -1934,6 +1934,27 @@ } } @@ -80,7 +80,7 @@ /** * i915_driver_load - setup chip and create an initial config * @dev: DRM device -@@ -1446,6 +1467,15 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags) +@@ -1971,6 +1992,15 @@ goto free_priv; } @@ -96,7 +96,7 @@ pci_set_master(dev->pdev); /* overlay on gen2 is broken and can't address above 1G */ -@@ -1471,13 +1501,6 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags) +@@ -1996,13 +2026,6 @@ goto put_bridge; } @@ -110,6 +110,3 @@ agp_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT; dev_priv->mm.gtt_mapping = --- -1.7.10.4 - diff -Nru linux-3.2.46/debian/patches/bugfix/x86/drm-i915-Only-increment-the-user-pin-count-after-suc.patch linux-3.2.46/debian/patches/bugfix/x86/drm-i915-Only-increment-the-user-pin-count-after-suc.patch --- linux-3.2.46/debian/patches/bugfix/x86/drm-i915-Only-increment-the-user-pin-count-after-suc.patch 2013-02-24 03:52:24.000000000 +0000 +++ linux-3.2.46/debian/patches/bugfix/x86/drm-i915-Only-increment-the-user-pin-count-after-suc.patch 2013-07-26 19:27:35.000000000 +0000 @@ -17,9 +17,11 @@ drivers/gpu/drm/i915/i915_gem.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) ---- a/drivers/gpu/drm/i915/i915_gem.c -+++ b/drivers/gpu/drm/i915/i915_gem.c -@@ -3456,14 +3456,15 @@ i915_gem_pin_ioctl(struct drm_device *de +Index: linux-3.2.46/drivers/gpu/drm/i915/i915_gem.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/i915/i915_gem.c 2013-07-26 19:26:57.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/i915/i915_gem.c 2013-07-26 19:27:34.000000000 +0000 +@@ -3413,14 +3413,15 @@ goto out; } diff -Nru linux-3.2.46/debian/patches/bugfix/x86/drm-i915-Only-kick-out-vesafb-if-we-takeover-the-fbc.patch linux-3.2.46/debian/patches/bugfix/x86/drm-i915-Only-kick-out-vesafb-if-we-takeover-the-fbc.patch --- linux-3.2.46/debian/patches/bugfix/x86/drm-i915-Only-kick-out-vesafb-if-we-takeover-the-fbc.patch 2013-02-24 03:52:24.000000000 +0000 +++ linux-3.2.46/debian/patches/bugfix/x86/drm-i915-Only-kick-out-vesafb-if-we-takeover-the-fbc.patch 2013-07-26 19:27:11.000000000 +0000 @@ -21,9 +21,11 @@ drivers/gpu/drm/i915/i915_dma.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) ---- a/drivers/gpu/drm/i915/i915_dma.c -+++ b/drivers/gpu/drm/i915/i915_dma.c -@@ -1999,7 +1999,8 @@ int i915_driver_load(struct drm_device * +Index: linux-3.2.46/drivers/gpu/drm/i915/i915_dma.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/i915/i915_dma.c 2013-07-26 19:27:09.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/i915/i915_dma.c 2013-07-26 19:27:10.000000000 +0000 +@@ -1999,7 +1999,8 @@ goto put_bridge; } diff -Nru linux-3.2.46/debian/patches/bugfix/x86/drm-i915-panel-invert-brightness-acer-aspire-5734z.patch linux-3.2.46/debian/patches/bugfix/x86/drm-i915-panel-invert-brightness-acer-aspire-5734z.patch --- linux-3.2.46/debian/patches/bugfix/x86/drm-i915-panel-invert-brightness-acer-aspire-5734z.patch 2013-04-28 20:19:02.000000000 +0000 +++ linux-3.2.46/debian/patches/bugfix/x86/drm-i915-panel-invert-brightness-acer-aspire-5734z.patch 2013-07-26 19:27:20.000000000 +0000 @@ -15,11 +15,11 @@ drivers/gpu/drm/i915/intel_display.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) -diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c -index 92208f8..683002fb 100644 ---- a/drivers/gpu/drm/i915/intel_display.c -+++ b/drivers/gpu/drm/i915/intel_display.c -@@ -9021,7 +9021,8 @@ static void quirk_ssc_force_disable(struct drm_device *dev) +Index: linux-3.2.46/drivers/gpu/drm/i915/intel_display.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/i915/intel_display.c 2013-07-26 19:27:17.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/i915/intel_display.c 2013-07-26 19:27:19.000000000 +0000 +@@ -9161,7 +9161,8 @@ } /* @@ -29,7 +29,7 @@ */ static void quirk_invert_brightness(struct drm_device *dev) { -@@ -9061,6 +9062,9 @@ struct intel_quirk intel_quirks[] = { +@@ -9201,6 +9202,9 @@ /* Sony Vaio Y cannot use SSC on LVDS */ { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable }, diff -Nru linux-3.2.46/debian/patches/bugfix/x86/drm-i915-panel-invert-brightness-via-parameter.patch linux-3.2.46/debian/patches/bugfix/x86/drm-i915-panel-invert-brightness-via-parameter.patch --- linux-3.2.46/debian/patches/bugfix/x86/drm-i915-panel-invert-brightness-via-parameter.patch 2013-04-28 20:23:35.000000000 +0000 +++ linux-3.2.46/debian/patches/bugfix/x86/drm-i915-panel-invert-brightness-via-parameter.patch 2013-07-26 19:27:17.000000000 +0000 @@ -23,8 +23,10 @@ Reviewed-by: Chris Wilson Signed-off-by: Daniel Vetter --- ---- a/drivers/gpu/drm/i915/intel_panel.c -+++ b/drivers/gpu/drm/i915/intel_panel.c +Index: linux-3.2.46/drivers/gpu/drm/i915/intel_panel.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/i915/intel_panel.c 2013-07-26 19:26:22.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/i915/intel_panel.c 2013-07-26 19:27:16.000000000 +0000 @@ -28,6 +28,7 @@ * Chris Wilson */ @@ -33,7 +35,7 @@ #include "intel_drv.h" #define PCI_LBPC 0xf4 /* legacy/combination backlight modes */ -@@ -189,6 +190,20 @@ u32 intel_panel_get_max_backlight(struct +@@ -189,6 +190,20 @@ return max; } @@ -54,7 +56,7 @@ u32 intel_panel_get_backlight(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; -@@ -209,6 +224,7 @@ u32 intel_panel_get_backlight(struct drm +@@ -209,6 +224,7 @@ } } @@ -62,7 +64,7 @@ DRM_DEBUG_DRIVER("get backlight PWM = %d\n", val); return val; } -@@ -226,6 +242,7 @@ static void intel_panel_actually_set_bac +@@ -226,6 +242,7 @@ u32 tmp; DRM_DEBUG_DRIVER("set backlight PWM = %d\n", level); diff -Nru linux-3.2.46/debian/patches/bugfix/x86/drm-i915-panel-invert-brightness-via-quirk.patch linux-3.2.46/debian/patches/bugfix/x86/drm-i915-panel-invert-brightness-via-quirk.patch --- linux-3.2.46/debian/patches/bugfix/x86/drm-i915-panel-invert-brightness-via-quirk.patch 2013-04-28 20:23:58.000000000 +0000 +++ linux-3.2.46/debian/patches/bugfix/x86/drm-i915-panel-invert-brightness-via-quirk.patch 2013-07-26 19:27:18.000000000 +0000 @@ -11,9 +11,11 @@ Reviewed-by: Chris Wilson Signed-off-by: Daniel Vetter --- ---- a/drivers/gpu/drm/i915/i915_drv.h -+++ b/drivers/gpu/drm/i915/i915_drv.h -@@ -296,6 +296,7 @@ enum intel_pch { +Index: linux-3.2.46/drivers/gpu/drm/i915/i915_drv.h +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/i915/i915_drv.h 2013-07-26 19:26:22.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/i915/i915_drv.h 2013-07-26 19:27:17.000000000 +0000 +@@ -296,6 +296,7 @@ #define QUIRK_PIPEA_FORCE (1<<0) #define QUIRK_LVDS_SSC_DISABLE (1<<1) @@ -21,9 +23,11 @@ struct intel_fbdev; struct intel_fbc_work; ---- a/drivers/gpu/drm/i915/intel_display.c -+++ b/drivers/gpu/drm/i915/intel_display.c -@@ -9160,6 +9160,15 @@ static void quirk_ssc_force_disable(stru +Index: linux-3.2.46/drivers/gpu/drm/i915/intel_display.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/i915/intel_display.c 2013-07-26 19:26:22.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/i915/intel_display.c 2013-07-26 19:27:17.000000000 +0000 +@@ -9160,6 +9160,15 @@ dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE; } @@ -39,9 +43,11 @@ struct intel_quirk { int device; int subsystem_vendor; ---- a/drivers/gpu/drm/i915/intel_panel.c -+++ b/drivers/gpu/drm/i915/intel_panel.c -@@ -190,15 +190,22 @@ u32 intel_panel_get_max_backlight(struct +Index: linux-3.2.46/drivers/gpu/drm/i915/intel_panel.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/i915/intel_panel.c 2013-07-26 19:27:16.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/i915/intel_panel.c 2013-07-26 19:27:17.000000000 +0000 +@@ -190,15 +190,22 @@ return max; } diff -Nru linux-3.2.46/debian/patches/bugfix/x86/drm-i915-Unconditionally-initialise-the-interrupt-wo.patch linux-3.2.46/debian/patches/bugfix/x86/drm-i915-Unconditionally-initialise-the-interrupt-wo.patch --- linux-3.2.46/debian/patches/bugfix/x86/drm-i915-Unconditionally-initialise-the-interrupt-wo.patch 2013-03-10 23:51:02.000000000 +0000 +++ linux-3.2.46/debian/patches/bugfix/x86/drm-i915-Unconditionally-initialise-the-interrupt-wo.patch 2013-07-26 19:30:25.000000000 +0000 @@ -21,9 +21,11 @@ drivers/gpu/drm/i915/i915_irq.c | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) ---- a/drivers/gpu/drm/i915/i915_irq.c -+++ b/drivers/gpu/drm/i915/i915_irq.c -@@ -1806,10 +1806,6 @@ static void ironlake_irq_preinstall(stru +Index: linux-3.2.46/drivers/gpu/drm/i915/i915_irq.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/i915/i915_irq.c 2013-07-26 19:27:26.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/i915/i915_irq.c 2013-07-26 19:30:25.000000000 +0000 +@@ -1806,10 +1806,6 @@ atomic_set(&dev_priv->irq_received, 0); @@ -34,7 +36,7 @@ I915_WRITE(HWSTAM, 0xeffe); -@@ -1983,9 +1979,6 @@ static void i915_driver_irq_preinstall(s +@@ -1983,9 +1979,6 @@ atomic_set(&dev_priv->irq_received, 0); @@ -44,7 +46,7 @@ if (I915_HAS_HOTPLUG(dev)) { I915_WRITE(PORT_HOTPLUG_EN, 0); I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); -@@ -2290,6 +2283,12 @@ static void i8xx_irq_uninstall(struct dr +@@ -2290,6 +2283,12 @@ void intel_irq_init(struct drm_device *dev) { diff -Nru linux-3.2.46/debian/patches/bugfix/x86/ipw2100-Fix-order-of-device-registration.patch linux-3.2.46/debian/patches/bugfix/x86/ipw2100-Fix-order-of-device-registration.patch --- linux-3.2.46/debian/patches/bugfix/x86/ipw2100-Fix-order-of-device-registration.patch 2013-06-08 16:37:26.000000000 +0000 +++ linux-3.2.46/debian/patches/bugfix/x86/ipw2100-Fix-order-of-device-registration.patch 2013-07-26 19:31:04.000000000 +0000 @@ -16,9 +16,11 @@ drivers/net/wireless/ipw2x00/ipw2100.c | 24 +++++++++++++----------- 1 file changed, 13 insertions(+), 11 deletions(-) ---- a/drivers/net/wireless/ipw2x00/ipw2100.c -+++ b/drivers/net/wireless/ipw2x00/ipw2100.c -@@ -1960,10 +1960,8 @@ static int ipw2100_wdev_init(struct net_ +Index: linux-3.2.46/drivers/net/wireless/ipw2x00/ipw2100.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/wireless/ipw2x00/ipw2100.c 2013-07-26 19:25:24.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/ipw2x00/ipw2100.c 2013-07-26 19:31:03.000000000 +0000 +@@ -1960,10 +1960,8 @@ wdev->wiphy->n_cipher_suites = ARRAY_SIZE(ipw_cipher_suites); set_wiphy_dev(wdev->wiphy, &priv->pci_dev->dev); @@ -30,7 +32,7 @@ return 0; } -@@ -6340,6 +6338,11 @@ static int ipw2100_pci_init_one(struct p +@@ -6340,6 +6338,11 @@ printk(KERN_INFO DRV_NAME ": Detected Intel PRO/Wireless 2100 Network Connection\n"); @@ -42,7 +44,7 @@ /* Bring up the interface. Pre 0.46, after we registered the * network device we would call ipw2100_up. This introduced a race * condition with newer hotplug configurations (network was coming -@@ -6356,11 +6359,7 @@ static int ipw2100_pci_init_one(struct p +@@ -6356,11 +6359,7 @@ "Error calling register_netdev.\n"); goto fail; } @@ -55,7 +57,7 @@ mutex_lock(&priv->action_mutex); -@@ -6399,13 +6398,16 @@ static int ipw2100_pci_init_one(struct p +@@ -6399,13 +6398,16 @@ fail_unlock: mutex_unlock(&priv->action_mutex); diff -Nru linux-3.2.46/debian/patches/bugfix/x86/ipw2200-Fix-order-of-device-registration.patch linux-3.2.46/debian/patches/bugfix/x86/ipw2200-Fix-order-of-device-registration.patch --- linux-3.2.46/debian/patches/bugfix/x86/ipw2200-Fix-order-of-device-registration.patch 2013-06-08 16:37:05.000000000 +0000 +++ linux-3.2.46/debian/patches/bugfix/x86/ipw2200-Fix-order-of-device-registration.patch 2013-07-26 19:31:03.000000000 +0000 @@ -17,9 +17,11 @@ drivers/net/wireless/ipw2x00/ipw2200.c | 23 ++++++++++++----------- 1 file changed, 12 insertions(+), 11 deletions(-) ---- a/drivers/net/wireless/ipw2x00/ipw2200.c -+++ b/drivers/net/wireless/ipw2x00/ipw2200.c -@@ -11834,16 +11834,17 @@ static int __devinit ipw_pci_probe(struc +Index: linux-3.2.46/drivers/net/wireless/ipw2x00/ipw2200.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/wireless/ipw2x00/ipw2200.c 2013-07-26 19:31:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/ipw2x00/ipw2200.c 2013-07-26 19:31:02.000000000 +0000 +@@ -11834,16 +11834,17 @@ } mutex_unlock(&priv->mutex); @@ -42,7 +44,7 @@ } #ifdef CONFIG_IPW2200_PROMISCUOUS -@@ -11852,10 +11853,8 @@ static int __devinit ipw_pci_probe(struc +@@ -11852,10 +11853,8 @@ if (err) { IPW_ERROR("Failed to register promiscuous network " "device (error %d).\n", err); @@ -55,7 +57,7 @@ } } #endif -@@ -11867,8 +11866,10 @@ static int __devinit ipw_pci_probe(struc +@@ -11867,8 +11866,10 @@ return 0; diff -Nru linux-3.2.46/debian/patches/bugfix/x86/KVM-nVMX-Add-KVM_REQ_IMMEDIATE_EXIT.patch linux-3.2.46/debian/patches/bugfix/x86/KVM-nVMX-Add-KVM_REQ_IMMEDIATE_EXIT.patch --- linux-3.2.46/debian/patches/bugfix/x86/KVM-nVMX-Add-KVM_REQ_IMMEDIATE_EXIT.patch 2013-02-24 03:52:24.000000000 +0000 +++ linux-3.2.46/debian/patches/bugfix/x86/KVM-nVMX-Add-KVM_REQ_IMMEDIATE_EXIT.patch 2013-07-26 19:17:48.000000000 +0000 @@ -38,11 +38,11 @@ include/linux/kvm_host.h | 1 + 3 files changed, 14 insertions(+), 5 deletions(-) -diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c -index 579a0b5..d75d914 100644 ---- a/arch/x86/kvm/vmx.c -+++ b/arch/x86/kvm/vmx.c -@@ -3945,12 +3945,15 @@ static bool nested_exit_on_intr(struct kvm_vcpu *vcpu) +Index: linux-3.2.46/arch/x86/kvm/vmx.c +=================================================================== +--- linux-3.2.46.orig/arch/x86/kvm/vmx.c 2013-07-26 18:56:24.000000000 +0000 ++++ linux-3.2.46/arch/x86/kvm/vmx.c 2013-07-26 19:17:47.000000000 +0000 +@@ -3948,12 +3948,15 @@ static void enable_irq_window(struct kvm_vcpu *vcpu) { u32 cpu_based_vm_exec_control; @@ -62,11 +62,11 @@ cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL); cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING; -diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c -index 4c938da..e24edbc 100644 ---- a/arch/x86/kvm/x86.c -+++ b/arch/x86/kvm/x86.c -@@ -5648,6 +5648,7 @@ static int vcpu_enter_guest(struct kvm_vcpu *vcpu) +Index: linux-3.2.46/arch/x86/kvm/x86.c +=================================================================== +--- linux-3.2.46.orig/arch/x86/kvm/x86.c 2013-07-26 18:56:24.000000000 +0000 ++++ linux-3.2.46/arch/x86/kvm/x86.c 2013-07-26 19:17:47.000000000 +0000 +@@ -5669,6 +5669,7 @@ int r; bool req_int_win = !irqchip_in_kernel(vcpu->kvm) && vcpu->run->request_interrupt_window; @@ -74,7 +74,7 @@ if (vcpu->requests) { if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu)) -@@ -5687,7 +5688,8 @@ static int vcpu_enter_guest(struct kvm_vcpu *vcpu) +@@ -5708,7 +5709,8 @@ record_steal_time(vcpu); if (kvm_check_request(KVM_REQ_NMI, vcpu)) process_nmi(vcpu); @@ -84,7 +84,7 @@ } r = kvm_mmu_reload(vcpu); -@@ -5738,6 +5740,9 @@ static int vcpu_enter_guest(struct kvm_vcpu *vcpu) +@@ -5759,6 +5761,9 @@ srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx); @@ -94,10 +94,10 @@ kvm_guest_enter(); if (unlikely(vcpu->arch.switch_db_regs)) { -diff --git a/include/linux/kvm_host.h b/include/linux/kvm_host.h -index d526231..9fedeb3 100644 ---- a/include/linux/kvm_host.h -+++ b/include/linux/kvm_host.h +Index: linux-3.2.46/include/linux/kvm_host.h +=================================================================== +--- linux-3.2.46.orig/include/linux/kvm_host.h 2013-07-26 18:56:24.000000000 +0000 ++++ linux-3.2.46/include/linux/kvm_host.h 2013-07-26 19:17:47.000000000 +0000 @@ -50,6 +50,7 @@ #define KVM_REQ_APF_HALT 12 #define KVM_REQ_STEAL_UPDATE 13 @@ -106,6 +106,3 @@ #define KVM_USERSPACE_IRQ_SOURCE_ID 0 --- -1.7.8.3 - diff -Nru linux-3.2.46/debian/patches/bugfix/x86/KVM-nVMX-Fix-warning-causing-idt-vectoring-info-beha.patch linux-3.2.46/debian/patches/bugfix/x86/KVM-nVMX-Fix-warning-causing-idt-vectoring-info-beha.patch --- linux-3.2.46/debian/patches/bugfix/x86/KVM-nVMX-Fix-warning-causing-idt-vectoring-info-beha.patch 2013-02-24 03:52:24.000000000 +0000 +++ linux-3.2.46/debian/patches/bugfix/x86/KVM-nVMX-Fix-warning-causing-idt-vectoring-info-beha.patch 2013-07-26 19:17:49.000000000 +0000 @@ -48,11 +48,11 @@ arch/x86/kvm/vmx.c | 7 ++++--- 1 files changed, 4 insertions(+), 3 deletions(-) -diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c -index d75d914..6e28d58 100644 ---- a/arch/x86/kvm/vmx.c -+++ b/arch/x86/kvm/vmx.c -@@ -4080,11 +4080,12 @@ static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked) +Index: linux-3.2.46/arch/x86/kvm/vmx.c +=================================================================== +--- linux-3.2.46.orig/arch/x86/kvm/vmx.c 2013-07-26 19:17:47.000000000 +0000 ++++ linux-3.2.46/arch/x86/kvm/vmx.c 2013-07-26 19:17:48.000000000 +0000 +@@ -4083,11 +4083,12 @@ static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu) { if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu)) { @@ -68,6 +68,3 @@ vmcs12->vm_exit_reason = EXIT_REASON_EXTERNAL_INTERRUPT; vmcs12->vm_exit_intr_info = 0; /* fall through to normal code, but now in L1, not L2 */ --- -1.7.8.3 - diff -Nru linux-3.2.46/debian/patches/bugfix/x86/net-wireless-ipw2100-Fix-WARN_ON-occurring-in-wiphy_.patch linux-3.2.46/debian/patches/bugfix/x86/net-wireless-ipw2100-Fix-WARN_ON-occurring-in-wiphy_.patch --- linux-3.2.46/debian/patches/bugfix/x86/net-wireless-ipw2100-Fix-WARN_ON-occurring-in-wiphy_.patch 2013-06-08 16:37:45.000000000 +0000 +++ linux-3.2.46/debian/patches/bugfix/x86/net-wireless-ipw2100-Fix-WARN_ON-occurring-in-wiphy_.patch 2013-07-26 19:31:05.000000000 +0000 @@ -71,9 +71,11 @@ drivers/net/wireless/ipw2x00/ipw2100.c | 20 +++++--------------- 1 file changed, 5 insertions(+), 15 deletions(-) ---- a/drivers/net/wireless/ipw2x00/ipw2100.c -+++ b/drivers/net/wireless/ipw2x00/ipw2100.c -@@ -1900,14 +1900,6 @@ static void ipw2100_down(struct ipw2100_ +Index: linux-3.2.46/drivers/net/wireless/ipw2x00/ipw2100.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/wireless/ipw2x00/ipw2100.c 2013-07-26 19:31:03.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/ipw2x00/ipw2100.c 2013-07-26 19:31:04.000000000 +0000 +@@ -1900,14 +1900,6 @@ netif_stop_queue(priv->net_dev); } @@ -88,7 +90,7 @@ static int ipw2100_wdev_init(struct net_device *dev) { struct ipw2100_priv *priv = libipw_priv(dev); -@@ -6086,7 +6078,6 @@ static const struct net_device_ops ipw21 +@@ -6086,7 +6078,6 @@ .ndo_stop = ipw2100_close, .ndo_start_xmit = libipw_xmit, .ndo_change_mtu = libipw_change_mtu, @@ -96,7 +98,7 @@ .ndo_tx_timeout = ipw2100_tx_timeout, .ndo_set_mac_address = ipw2100_set_address, .ndo_validate_addr = eth_validate_addr, -@@ -6338,6 +6329,10 @@ static int ipw2100_pci_init_one(struct p +@@ -6338,6 +6329,10 @@ printk(KERN_INFO DRV_NAME ": Detected Intel PRO/Wireless 2100 Network Connection\n"); @@ -107,7 +109,7 @@ err = ipw2100_wdev_init(dev); if (err) goto fail; -@@ -6347,12 +6342,7 @@ static int ipw2100_pci_init_one(struct p +@@ -6347,12 +6342,7 @@ * network device we would call ipw2100_up. This introduced a race * condition with newer hotplug configurations (network was coming * up and making calls before the device was initialized). diff -Nru linux-3.2.46/debian/patches/bugfix/x86/net-wireless-ipw2200-Fix-WARN_ON-occurring-in-wiphy_.patch linux-3.2.46/debian/patches/bugfix/x86/net-wireless-ipw2200-Fix-WARN_ON-occurring-in-wiphy_.patch --- linux-3.2.46/debian/patches/bugfix/x86/net-wireless-ipw2200-Fix-WARN_ON-occurring-in-wiphy_.patch 2013-06-08 16:36:48.000000000 +0000 +++ linux-3.2.46/debian/patches/bugfix/x86/net-wireless-ipw2200-Fix-WARN_ON-occurring-in-wiphy_.patch 2013-07-26 19:31:01.000000000 +0000 @@ -60,9 +60,11 @@ drivers/net/wireless/ipw2x00/ipw2200.c | 21 ++++++--------------- 1 file changed, 6 insertions(+), 15 deletions(-) ---- a/drivers/net/wireless/ipw2x00/ipw2200.c -+++ b/drivers/net/wireless/ipw2x00/ipw2200.c -@@ -11433,20 +11433,6 @@ static void ipw_bg_down(struct work_stru +Index: linux-3.2.46/drivers/net/wireless/ipw2x00/ipw2200.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/wireless/ipw2x00/ipw2200.c 2013-07-26 19:25:24.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/ipw2x00/ipw2200.c 2013-07-26 19:31:00.000000000 +0000 +@@ -11433,20 +11433,6 @@ mutex_unlock(&priv->mutex); } @@ -83,7 +85,7 @@ static int ipw_wdev_init(struct net_device *dev) { int i, rc = 0; -@@ -11715,7 +11701,6 @@ static void ipw_prom_free(struct ipw_pri +@@ -11715,7 +11701,6 @@ #endif static const struct net_device_ops ipw_netdev_ops = { @@ -91,7 +93,7 @@ .ndo_open = ipw_net_open, .ndo_stop = ipw_net_stop, .ndo_set_rx_mode = ipw_net_set_multicast_list, -@@ -11842,6 +11827,12 @@ static int __devinit ipw_pci_probe(struc +@@ -11842,6 +11827,12 @@ goto out_release_irq; } diff -Nru linux-3.2.46/debian/patches/bugfix/x86/viafb-autoload-on-olpc-xo1.5-only.patch linux-3.2.46/debian/patches/bugfix/x86/viafb-autoload-on-olpc-xo1.5-only.patch --- linux-3.2.46/debian/patches/bugfix/x86/viafb-autoload-on-olpc-xo1.5-only.patch 2013-06-08 17:24:20.000000000 +0000 +++ linux-3.2.46/debian/patches/bugfix/x86/viafb-autoload-on-olpc-xo1.5-only.patch 2013-07-26 19:31:17.000000000 +0000 @@ -13,21 +13,23 @@ un-blacklist it in udev. --- ---- a/drivers/video/via/via-core.c -+++ b/drivers/video/via/via-core.c -@@ -754,7 +754,14 @@ static struct pci_device_id via_pci_tabl - .driver_data = UNICHROME_VX900 }, - { } - }; --MODULE_DEVICE_TABLE(pci, via_pci_table); -+ -+static const struct pci_device_id via_pci_autoload_table[] __initconst = { -+ /* OLPC XO 1.5 */ -+ { PCI_DEVICE(PCI_VENDOR_ID_VIA, UNICHROME_VX855_DID), -+ .subvendor = 0x152d, .subdevice = 0x0833 }, -+ { } -+}; -+MODULE_DEVICE_TABLE(pci, via_pci_autoload_table); - - static struct pci_driver via_driver = { - .name = "viafb", +Index: linux-3.2.46/drivers/video/via/via-core.c +=================================================================== +--- linux-3.2.46.orig/drivers/video/via/via-core.c 2013-07-26 18:52:06.000000000 +0000 ++++ linux-3.2.46/drivers/video/via/via-core.c 2013-07-26 19:31:15.000000000 +0000 +@@ -754,7 +754,14 @@ + .driver_data = UNICHROME_VX900 }, + { } + }; +-MODULE_DEVICE_TABLE(pci, via_pci_table); ++ ++static const struct pci_device_id via_pci_autoload_table[] __initconst = { ++ /* OLPC XO 1.5 */ ++ { PCI_DEVICE(PCI_VENDOR_ID_VIA, UNICHROME_VX855_DID), ++ .subvendor = 0x152d, .subdevice = 0x0833 }, ++ { } ++}; ++MODULE_DEVICE_TABLE(pci, via_pci_autoload_table); + + static struct pci_driver via_driver = { + .name = "viafb", diff -Nru linux-3.2.46/debian/patches/debian/af_802154-Disable-auto-loading-as-mitigation-against.patch linux-3.2.46/debian/patches/debian/af_802154-Disable-auto-loading-as-mitigation-against.patch --- linux-3.2.46/debian/patches/debian/af_802154-Disable-auto-loading-as-mitigation-against.patch 2013-04-11 03:27:32.000000000 +0000 +++ linux-3.2.46/debian/patches/debian/af_802154-Disable-auto-loading-as-mitigation-against.patch 2013-07-26 19:17:15.000000000 +0000 @@ -19,16 +19,13 @@ net/ieee802154/af_ieee802154.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) -diff --git a/net/ieee802154/af_ieee802154.c b/net/ieee802154/af_ieee802154.c -index cd949d5..8f49dd5 100644 ---- a/net/ieee802154/af_ieee802154.c -+++ b/net/ieee802154/af_ieee802154.c -@@ -363,4 +363,4 @@ module_init(af_ieee802154_init); +Index: linux-3.2.46/net/ieee802154/af_ieee802154.c +=================================================================== +--- linux-3.2.46.orig/net/ieee802154/af_ieee802154.c 2013-07-26 18:56:35.000000000 +0000 ++++ linux-3.2.46/net/ieee802154/af_ieee802154.c 2013-07-26 19:17:14.000000000 +0000 +@@ -370,4 +370,4 @@ module_exit(af_ieee802154_remove); MODULE_LICENSE("GPL"); -MODULE_ALIAS_NETPROTO(PF_IEEE802154); +/* MODULE_ALIAS_NETPROTO(PF_IEEE802154); */ --- -1.7.2.3 - diff -Nru linux-3.2.46/debian/patches/debian/ALSA-avoid-ABI-change-in-3.2.34.patch linux-3.2.46/debian/patches/debian/ALSA-avoid-ABI-change-in-3.2.34.patch --- linux-3.2.46/debian/patches/debian/ALSA-avoid-ABI-change-in-3.2.34.patch 2013-04-11 03:27:32.000000000 +0000 +++ linux-3.2.46/debian/patches/debian/ALSA-avoid-ABI-change-in-3.2.34.patch 2013-07-26 19:25:09.000000000 +0000 @@ -16,9 +16,11 @@ genksyms, and there is no ABI change. --- ---- a/include/sound/core.h -+++ b/include/sound/core.h -@@ -132,7 +132,6 @@ struct snd_card { +Index: linux-3.2.46/include/sound/core.h +=================================================================== +--- linux-3.2.46.orig/include/sound/core.h 2013-07-26 18:54:02.000000000 +0000 ++++ linux-3.2.46/include/sound/core.h 2013-07-26 19:25:09.000000000 +0000 +@@ -132,7 +132,6 @@ int shutdown; /* this card is going down */ int free_on_last_close; /* free in context of file_release */ wait_queue_head_t shutdown_sleep; @@ -26,7 +28,7 @@ struct device *dev; /* device assigned to this card */ struct device *card_dev; /* cardX object for sysfs */ -@@ -146,6 +145,9 @@ struct snd_card { +@@ -146,6 +145,9 @@ struct snd_mixer_oss *mixer_oss; int mixer_oss_change_count; #endif diff -Nru linux-3.2.46/debian/patches/debian/arch-sh4-fix-uimage-build.patch linux-3.2.46/debian/patches/debian/arch-sh4-fix-uimage-build.patch --- linux-3.2.46/debian/patches/debian/arch-sh4-fix-uimage-build.patch 2013-02-24 03:52:24.000000000 +0000 +++ linux-3.2.46/debian/patches/debian/arch-sh4-fix-uimage-build.patch 2013-07-26 19:17:13.000000000 +0000 @@ -1,5 +1,7 @@ ---- a/arch/sh/Makefile -+++ b/arch/sh/Makefile +Index: linux-3.2.46/arch/sh/Makefile +=================================================================== +--- linux-3.2.46.orig/arch/sh/Makefile 2013-07-26 18:56:36.000000000 +0000 ++++ linux-3.2.46/arch/sh/Makefile 2013-07-26 19:17:12.000000000 +0000 @@ -75,7 +75,6 @@ # Give the various platforms the opportunity to set default image types diff -Nru linux-3.2.46/debian/patches/debian/ARM-Remove-use-of-possibly-undefined-BUILD_BUG_ON-in.patch linux-3.2.46/debian/patches/debian/ARM-Remove-use-of-possibly-undefined-BUILD_BUG_ON-in.patch --- linux-3.2.46/debian/patches/debian/ARM-Remove-use-of-possibly-undefined-BUILD_BUG_ON-in.patch 2013-02-24 03:52:24.000000000 +0000 +++ linux-3.2.46/debian/patches/debian/ARM-Remove-use-of-possibly-undefined-BUILD_BUG_ON-in.patch 2013-07-26 19:17:35.000000000 +0000 @@ -10,10 +10,10 @@ arch/arm/include/asm/bug.h | 1 - 1 files changed, 0 insertions(+), 1 deletions(-) -diff --git a/arch/arm/include/asm/bug.h b/arch/arm/include/asm/bug.h -index 9abe7a0..fac79dc 100644 ---- a/arch/arm/include/asm/bug.h -+++ b/arch/arm/include/asm/bug.h +Index: linux-3.2.46/arch/arm/include/asm/bug.h +=================================================================== +--- linux-3.2.46.orig/arch/arm/include/asm/bug.h 2013-07-26 18:56:29.000000000 +0000 ++++ linux-3.2.46/arch/arm/include/asm/bug.h 2013-07-26 19:17:34.000000000 +0000 @@ -32,7 +32,6 @@ #define __BUG(__file, __line, __value) \ @@ -22,6 +22,3 @@ asm volatile("1:\t" BUG_INSTR_TYPE #__value "\n" \ ".pushsection .rodata.str, \"aMS\", %progbits, 1\n" \ "2:\t.asciz " #__file "\n" \ --- -1.7.7.3 - diff -Nru linux-3.2.46/debian/patches/debian/audit-increase-AUDIT_NAMES.patch linux-3.2.46/debian/patches/debian/audit-increase-AUDIT_NAMES.patch --- linux-3.2.46/debian/patches/debian/audit-increase-AUDIT_NAMES.patch 2013-04-11 03:27:32.000000000 +0000 +++ linux-3.2.46/debian/patches/debian/audit-increase-AUDIT_NAMES.patch 2013-07-26 19:25:43.000000000 +0000 @@ -12,8 +12,10 @@ ('audit: dynamically allocate audit_names when not enough space is in the names array'). ---- a/kernel/auditsc.c -+++ b/kernel/auditsc.c +Index: linux-3.2.46/kernel/auditsc.c +=================================================================== +--- linux-3.2.46.orig/kernel/auditsc.c 2013-07-26 18:53:47.000000000 +0000 ++++ linux-3.2.46/kernel/auditsc.c 2013-07-26 19:25:42.000000000 +0000 @@ -72,7 +72,7 @@ /* AUDIT_NAMES is the number of slots we reserve in the audit_context diff -Nru linux-3.2.46/debian/patches/debian/bcma-Do-not-claim-PCI-device-IDs-also-claimed-by-brc.patch linux-3.2.46/debian/patches/debian/bcma-Do-not-claim-PCI-device-IDs-also-claimed-by-brc.patch --- linux-3.2.46/debian/patches/debian/bcma-Do-not-claim-PCI-device-IDs-also-claimed-by-brc.patch 2013-04-11 03:27:32.000000000 +0000 +++ linux-3.2.46/debian/patches/debian/bcma-Do-not-claim-PCI-device-IDs-also-claimed-by-brc.patch 2013-07-26 19:17:30.000000000 +0000 @@ -13,8 +13,10 @@ drivers/net/wireless/brcm80211/Kconfig | 1 - 2 files changed, 3 insertions(+), 2 deletions(-) ---- a/drivers/bcma/host_pci.c -+++ b/drivers/bcma/host_pci.c +Index: linux-3.2.46/drivers/bcma/host_pci.c +=================================================================== +--- linux-3.2.46.orig/drivers/bcma/host_pci.c 2013-07-26 18:56:31.000000000 +0000 ++++ linux-3.2.46/drivers/bcma/host_pci.c 2013-07-26 19:17:29.000000000 +0000 @@ -263,11 +263,13 @@ #endif /* CONFIG_PM */ @@ -30,8 +32,10 @@ { 0, }, }; MODULE_DEVICE_TABLE(pci, bcma_pci_bridge_tbl); ---- a/drivers/net/wireless/brcm80211/Kconfig -+++ b/drivers/net/wireless/brcm80211/Kconfig +Index: linux-3.2.46/drivers/net/wireless/brcm80211/Kconfig +=================================================================== +--- linux-3.2.46.orig/drivers/net/wireless/brcm80211/Kconfig 2013-07-26 18:56:31.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/brcm80211/Kconfig 2013-07-26 19:17:29.000000000 +0000 @@ -5,7 +5,6 @@ tristate "Broadcom IEEE802.11n PCIe SoftMAC WLAN driver" depends on PCI diff -Nru linux-3.2.46/debian/patches/debian/cgroups-Document-the-Debian-memory-resource-controll.patch linux-3.2.46/debian/patches/debian/cgroups-Document-the-Debian-memory-resource-controll.patch --- linux-3.2.46/debian/patches/debian/cgroups-Document-the-Debian-memory-resource-controll.patch 2013-02-24 03:52:24.000000000 +0000 +++ linux-3.2.46/debian/patches/debian/cgroups-Document-the-Debian-memory-resource-controll.patch 2013-07-26 19:17:25.000000000 +0000 @@ -8,11 +8,11 @@ Documentation/cgroups/memory.txt | 4 ++++ 1 files changed, 4 insertions(+), 0 deletions(-) -diff --git a/Documentation/cgroups/memory.txt b/Documentation/cgroups/memory.txt -index 7c16347..684f70d 100644 ---- a/Documentation/cgroups/memory.txt -+++ b/Documentation/cgroups/memory.txt -@@ -47,6 +47,10 @@ Features: +Index: linux-3.2.46/Documentation/cgroups/memory.txt +=================================================================== +--- linux-3.2.46.orig/Documentation/cgroups/memory.txt 2013-07-26 18:56:32.000000000 +0000 ++++ linux-3.2.46/Documentation/cgroups/memory.txt 2013-07-26 19:17:24.000000000 +0000 +@@ -47,6 +47,10 @@ Kernel memory and Hugepages are not under control yet. We just manage pages on LRU. To add more controls, we have to take care of performance. @@ -23,6 +23,3 @@ Brief summary of control files. tasks # attach a task(thread) and show list of threads --- -1.7.4.4 - diff -Nru linux-3.2.46/debian/patches/debian/debugfs-set-default-mode-to-700.patch linux-3.2.46/debian/patches/debian/debugfs-set-default-mode-to-700.patch --- linux-3.2.46/debian/patches/debian/debugfs-set-default-mode-to-700.patch 2013-04-11 03:27:32.000000000 +0000 +++ linux-3.2.46/debian/patches/debian/debugfs-set-default-mode-to-700.patch 2013-07-26 19:24:10.000000000 +0000 @@ -16,11 +16,11 @@ fs/debugfs/inode.c | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) -diff --git a/Documentation/filesystems/debugfs.txt b/Documentation/filesystems/debugfs.txt -index 7a34f82..3a863f6 100644 ---- a/Documentation/filesystems/debugfs.txt -+++ b/Documentation/filesystems/debugfs.txt -@@ -15,8 +15,8 @@ Debugfs is typically mounted with a command like: +Index: linux-3.2.46/Documentation/filesystems/debugfs.txt +=================================================================== +--- linux-3.2.46.orig/Documentation/filesystems/debugfs.txt 2013-07-26 19:24:07.000000000 +0000 ++++ linux-3.2.46/Documentation/filesystems/debugfs.txt 2013-07-26 19:24:09.000000000 +0000 +@@ -15,8 +15,8 @@ mount -t debugfs none /sys/kernel/debug (Or an equivalent /etc/fstab line). @@ -31,10 +31,10 @@ options can be used. Note that the debugfs API is exported GPL-only to modules. -diff --git a/fs/debugfs/inode.c b/fs/debugfs/inode.c -index 2c9fafb..6393fd6 100644 ---- a/fs/debugfs/inode.c -+++ b/fs/debugfs/inode.c +Index: linux-3.2.46/fs/debugfs/inode.c +=================================================================== +--- linux-3.2.46.orig/fs/debugfs/inode.c 2013-07-26 19:24:07.000000000 +0000 ++++ linux-3.2.46/fs/debugfs/inode.c 2013-07-26 19:24:09.000000000 +0000 @@ -28,7 +28,7 @@ #include #include diff -Nru linux-3.2.46/debian/patches/debian/decnet-Disable-auto-loading-as-mitigation-against-lo.patch linux-3.2.46/debian/patches/debian/decnet-Disable-auto-loading-as-mitigation-against-lo.patch --- linux-3.2.46/debian/patches/debian/decnet-Disable-auto-loading-as-mitigation-against-lo.patch 2013-04-11 03:27:32.000000000 +0000 +++ linux-3.2.46/debian/patches/debian/decnet-Disable-auto-loading-as-mitigation-against-lo.patch 2013-07-26 19:17:18.000000000 +0000 @@ -19,11 +19,11 @@ net/decnet/af_decnet.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) -diff --git a/net/decnet/af_decnet.c b/net/decnet/af_decnet.c -index 7a58c87..ed9e2b0 100644 ---- a/net/decnet/af_decnet.c -+++ b/net/decnet/af_decnet.c -@@ -2358,7 +2358,7 @@ void dn_unregister_sysctl(void); +Index: linux-3.2.46/net/decnet/af_decnet.c +=================================================================== +--- linux-3.2.46.orig/net/decnet/af_decnet.c 2013-07-26 18:56:35.000000000 +0000 ++++ linux-3.2.46/net/decnet/af_decnet.c 2013-07-26 19:17:17.000000000 +0000 +@@ -2362,7 +2362,7 @@ MODULE_DESCRIPTION("The Linux DECnet Network Protocol"); MODULE_AUTHOR("Linux DECnet Project Team"); MODULE_LICENSE("GPL"); @@ -32,6 +32,3 @@ static char banner[] __initdata = KERN_INFO "NET4: DECnet for Linux: V.2.5.68s (C) 1995-2003 Linux DECnet Project Team\n"; --- -1.7.2.3 - diff -Nru linux-3.2.46/debian/patches/debian/dm-avoid-ABI-change-in-3.2.41.patch linux-3.2.46/debian/patches/debian/dm-avoid-ABI-change-in-3.2.41.patch --- linux-3.2.46/debian/patches/debian/dm-avoid-ABI-change-in-3.2.41.patch 2013-04-11 03:27:32.000000000 +0000 +++ linux-3.2.46/debian/patches/debian/dm-avoid-ABI-change-in-3.2.41.patch 2013-07-26 19:30:32.000000000 +0000 @@ -10,9 +10,11 @@ Also, genksyms is too stupid to understand that 'unsigned' is the same thing as 'unsigned int'. ---- a/drivers/md/dm-crypt.c -+++ b/drivers/md/dm-crypt.c -@@ -1725,7 +1725,7 @@ static int crypt_map(struct dm_target *t +Index: linux-3.2.46/drivers/md/dm-crypt.c +=================================================================== +--- linux-3.2.46.orig/drivers/md/dm-crypt.c 2013-07-26 18:52:21.000000000 +0000 ++++ linux-3.2.46/drivers/md/dm-crypt.c 2013-07-26 19:30:30.000000000 +0000 +@@ -1725,7 +1725,7 @@ return DM_MAPIO_SUBMITTED; } @@ -21,7 +23,7 @@ char *result, unsigned maxlen) { struct crypt_config *cc = ti->private; -@@ -1753,6 +1753,7 @@ static void crypt_status(struct dm_targe +@@ -1753,6 +1753,7 @@ break; } @@ -29,9 +31,11 @@ } static void crypt_postsuspend(struct dm_target *ti) ---- a/drivers/md/dm-delay.c -+++ b/drivers/md/dm-delay.c -@@ -293,7 +293,7 @@ static int delay_map(struct dm_target *t +Index: linux-3.2.46/drivers/md/dm-delay.c +=================================================================== +--- linux-3.2.46.orig/drivers/md/dm-delay.c 2013-07-26 18:52:21.000000000 +0000 ++++ linux-3.2.46/drivers/md/dm-delay.c 2013-07-26 19:30:30.000000000 +0000 +@@ -293,7 +293,7 @@ return delay_bio(dc, dc->read_delay, bio); } @@ -40,7 +44,7 @@ char *result, unsigned maxlen) { struct delay_c *dc = ti->private; -@@ -314,6 +314,8 @@ static void delay_status(struct dm_targe +@@ -314,6 +314,8 @@ dc->write_delay); break; } @@ -49,9 +53,11 @@ } static int delay_iterate_devices(struct dm_target *ti, ---- a/drivers/md/dm-flakey.c -+++ b/drivers/md/dm-flakey.c -@@ -331,7 +331,7 @@ static int flakey_end_io(struct dm_targe +Index: linux-3.2.46/drivers/md/dm-flakey.c +=================================================================== +--- linux-3.2.46.orig/drivers/md/dm-flakey.c 2013-07-26 18:52:21.000000000 +0000 ++++ linux-3.2.46/drivers/md/dm-flakey.c 2013-07-26 19:30:31.000000000 +0000 +@@ -331,7 +331,7 @@ return error; } @@ -60,7 +66,7 @@ char *result, unsigned maxlen) { unsigned sz = 0; -@@ -362,6 +362,7 @@ static void flakey_status(struct dm_targ +@@ -362,6 +362,7 @@ break; } @@ -68,9 +74,11 @@ } static int flakey_ioctl(struct dm_target *ti, unsigned int cmd, unsigned long arg) ---- a/drivers/md/dm-linear.c -+++ b/drivers/md/dm-linear.c -@@ -94,7 +94,7 @@ static int linear_map(struct dm_target * +Index: linux-3.2.46/drivers/md/dm-linear.c +=================================================================== +--- linux-3.2.46.orig/drivers/md/dm-linear.c 2013-07-26 18:52:21.000000000 +0000 ++++ linux-3.2.46/drivers/md/dm-linear.c 2013-07-26 19:30:31.000000000 +0000 +@@ -94,7 +94,7 @@ return DM_MAPIO_REMAPPED; } @@ -79,7 +87,7 @@ char *result, unsigned maxlen) { struct linear_c *lc = (struct linear_c *) ti->private; -@@ -109,6 +109,7 @@ static void linear_status(struct dm_targ +@@ -109,6 +109,7 @@ (unsigned long long)lc->start); break; } @@ -87,9 +95,11 @@ } static int linear_ioctl(struct dm_target *ti, unsigned int cmd, ---- a/drivers/md/dm-mpath.c -+++ b/drivers/md/dm-mpath.c -@@ -1323,7 +1323,7 @@ static void multipath_resume(struct dm_t +Index: linux-3.2.46/drivers/md/dm-mpath.c +=================================================================== +--- linux-3.2.46.orig/drivers/md/dm-mpath.c 2013-07-26 18:52:21.000000000 +0000 ++++ linux-3.2.46/drivers/md/dm-mpath.c 2013-07-26 19:30:31.000000000 +0000 +@@ -1323,7 +1323,7 @@ * [priority selector-name num_ps_args [ps_args]* * num_paths num_selector_args [path_dev [selector_args]* ]+ ]+ */ @@ -98,7 +108,7 @@ char *result, unsigned maxlen) { int sz = 0; -@@ -1427,6 +1427,8 @@ static void multipath_status(struct dm_t +@@ -1427,6 +1427,8 @@ } spin_unlock_irqrestore(&m->lock, flags); @@ -107,9 +117,11 @@ } static int multipath_message(struct dm_target *ti, unsigned argc, char **argv) ---- a/drivers/md/dm-raid.c -+++ b/drivers/md/dm-raid.c -@@ -1017,7 +1017,7 @@ static int raid_map(struct dm_target *ti +Index: linux-3.2.46/drivers/md/dm-raid.c +=================================================================== +--- linux-3.2.46.orig/drivers/md/dm-raid.c 2013-07-26 18:52:21.000000000 +0000 ++++ linux-3.2.46/drivers/md/dm-raid.c 2013-07-26 19:30:31.000000000 +0000 +@@ -1017,7 +1017,7 @@ return DM_MAPIO_SUBMITTED; } @@ -118,7 +130,7 @@ char *result, unsigned maxlen) { struct raid_set *rs = ti->private; -@@ -1153,6 +1153,8 @@ static void raid_status(struct dm_target +@@ -1153,6 +1153,8 @@ DMEMIT(" -"); } } @@ -127,9 +139,11 @@ } static int raid_iterate_devices(struct dm_target *ti, iterate_devices_callout_fn fn, void *data) ---- a/drivers/md/dm-raid1.c -+++ b/drivers/md/dm-raid1.c -@@ -1358,7 +1358,7 @@ static char device_status_char(struct mi +Index: linux-3.2.46/drivers/md/dm-raid1.c +=================================================================== +--- linux-3.2.46.orig/drivers/md/dm-raid1.c 2013-07-26 18:52:21.000000000 +0000 ++++ linux-3.2.46/drivers/md/dm-raid1.c 2013-07-26 19:30:31.000000000 +0000 +@@ -1358,7 +1358,7 @@ } @@ -138,7 +152,7 @@ char *result, unsigned maxlen) { unsigned int m, sz = 0; -@@ -1394,6 +1394,8 @@ static void mirror_status(struct dm_targ +@@ -1394,6 +1394,8 @@ if (ms->features & DM_RAID1_HANDLE_ERRORS) DMEMIT(" 1 handle_errors"); } @@ -147,9 +161,11 @@ } static int mirror_iterate_devices(struct dm_target *ti, ---- a/drivers/md/dm-snap.c -+++ b/drivers/md/dm-snap.c -@@ -1845,7 +1845,7 @@ static void snapshot_merge_resume(struct +Index: linux-3.2.46/drivers/md/dm-snap.c +=================================================================== +--- linux-3.2.46.orig/drivers/md/dm-snap.c 2013-07-26 18:52:21.000000000 +0000 ++++ linux-3.2.46/drivers/md/dm-snap.c 2013-07-26 19:30:31.000000000 +0000 +@@ -1846,7 +1846,7 @@ start_merge(s); } @@ -158,7 +174,7 @@ char *result, unsigned maxlen) { unsigned sz = 0; -@@ -1892,6 +1892,8 @@ static void snapshot_status(struct dm_ta +@@ -1893,6 +1893,8 @@ maxlen - sz); break; } @@ -167,7 +183,7 @@ } static int snapshot_iterate_devices(struct dm_target *ti, -@@ -2146,7 +2148,7 @@ static void origin_resume(struct dm_targ +@@ -2147,7 +2149,7 @@ ti->split_io = get_origin_minimum_chunksize(dev->bdev); } @@ -176,7 +192,7 @@ char *result, unsigned maxlen) { struct dm_dev *dev = ti->private; -@@ -2160,6 +2162,8 @@ static void origin_status(struct dm_targ +@@ -2161,6 +2163,8 @@ snprintf(result, maxlen, "%s", dev->name); break; } @@ -185,9 +201,11 @@ } static int origin_merge(struct dm_target *ti, struct bvec_merge_data *bvm, ---- a/drivers/md/dm-stripe.c -+++ b/drivers/md/dm-stripe.c -@@ -301,7 +301,7 @@ static int stripe_map(struct dm_target * +Index: linux-3.2.46/drivers/md/dm-stripe.c +=================================================================== +--- linux-3.2.46.orig/drivers/md/dm-stripe.c 2013-07-26 18:52:21.000000000 +0000 ++++ linux-3.2.46/drivers/md/dm-stripe.c 2013-07-26 19:30:31.000000000 +0000 +@@ -301,7 +301,7 @@ * */ @@ -196,7 +214,7 @@ char *result, unsigned maxlen) { struct stripe_c *sc = (struct stripe_c *) ti->private; -@@ -329,6 +329,7 @@ static void stripe_status(struct dm_targ +@@ -329,6 +329,7 @@ (unsigned long long)sc->stripe[i].physical_start); break; } @@ -204,9 +222,11 @@ } static int stripe_end_io(struct dm_target *ti, struct bio *bio, ---- a/drivers/md/dm-thin.c -+++ b/drivers/md/dm-thin.c -@@ -2090,7 +2090,7 @@ static int pool_message(struct dm_target +Index: linux-3.2.46/drivers/md/dm-thin.c +=================================================================== +--- linux-3.2.46.orig/drivers/md/dm-thin.c 2013-07-26 18:52:21.000000000 +0000 ++++ linux-3.2.46/drivers/md/dm-thin.c 2013-07-26 19:30:31.000000000 +0000 +@@ -2090,7 +2090,7 @@ * / * / */ @@ -215,7 +235,7 @@ char *result, unsigned maxlen) { int r; -@@ -2171,10 +2171,11 @@ static void pool_status(struct dm_target +@@ -2171,10 +2171,11 @@ DMEMIT("skip_block_zeroing "); break; } @@ -228,7 +248,7 @@ } static int pool_iterate_devices(struct dm_target *ti, -@@ -2350,7 +2351,7 @@ static void thin_postsuspend(struct dm_t +@@ -2350,7 +2351,7 @@ /* * */ @@ -237,7 +257,7 @@ char *result, unsigned maxlen) { int r; -@@ -2392,10 +2393,11 @@ static void thin_status(struct dm_target +@@ -2392,10 +2393,11 @@ } } @@ -250,9 +270,11 @@ } static int thin_iterate_devices(struct dm_target *ti, ---- a/include/linux/device-mapper.h -+++ b/include/linux/device-mapper.h -@@ -72,8 +72,8 @@ typedef void (*dm_postsuspend_fn) (struc +Index: linux-3.2.46/include/linux/device-mapper.h +=================================================================== +--- linux-3.2.46.orig/include/linux/device-mapper.h 2013-07-26 18:52:21.000000000 +0000 ++++ linux-3.2.46/include/linux/device-mapper.h 2013-07-26 19:30:31.000000000 +0000 +@@ -72,8 +72,8 @@ typedef int (*dm_preresume_fn) (struct dm_target *ti); typedef void (*dm_resume_fn) (struct dm_target *ti); diff -Nru linux-3.2.46/debian/patches/debian/doc-build-parallel.patch linux-3.2.46/debian/patches/debian/doc-build-parallel.patch --- linux-3.2.46/debian/patches/debian/doc-build-parallel.patch 2013-02-24 03:52:24.000000000 +0000 +++ linux-3.2.46/debian/patches/debian/doc-build-parallel.patch 2013-07-26 19:16:48.000000000 +0000 @@ -9,11 +9,11 @@ Since dh_compress will compress manual pages later, we don't need to run gzip here at all. -diff --git a/Documentation/DocBook/Makefile b/Documentation/DocBook/Makefile -index 5a2882d..71c7077 100644 ---- a/Documentation/DocBook/Makefile -+++ b/Documentation/DocBook/Makefile -@@ -146,7 +146,7 @@ quiet_cmd_db2html = HTML $@ +Index: linux-3.2.46/Documentation/DocBook/Makefile +=================================================================== +--- linux-3.2.46.orig/Documentation/DocBook/Makefile 2013-07-26 18:56:44.000000000 +0000 ++++ linux-3.2.46/Documentation/DocBook/Makefile 2013-07-26 19:16:47.000000000 +0000 +@@ -159,7 +159,7 @@ cp $(PNG-$(basename $(notdir $@))) $(patsubst %.html,%,$@); fi quiet_cmd_db2man = MAN $@ diff -Nru linux-3.2.46/debian/patches/debian/efi-autoload-efivars.patch linux-3.2.46/debian/patches/debian/efi-autoload-efivars.patch --- linux-3.2.46/debian/patches/debian/efi-autoload-efivars.patch 2013-03-19 01:02:45.000000000 +0000 +++ linux-3.2.46/debian/patches/debian/efi-autoload-efivars.patch 2013-07-26 19:30:27.000000000 +0000 @@ -13,8 +13,10 @@ are available. This should trigger udev to load it. --- ---- a/arch/x86/platform/efi/efi.c -+++ b/arch/x86/platform/efi/efi.c +Index: linux-3.2.46/arch/x86/platform/efi/efi.c +=================================================================== +--- linux-3.2.46.orig/arch/x86/platform/efi/efi.c 2013-07-26 19:30:20.000000000 +0000 ++++ linux-3.2.46/arch/x86/platform/efi/efi.c 2013-07-26 19:30:26.000000000 +0000 @@ -38,6 +38,7 @@ #include #include @@ -23,7 +25,7 @@ #include #include -@@ -612,6 +613,20 @@ void __init efi_init(void) +@@ -621,6 +622,20 @@ #endif } @@ -44,9 +46,11 @@ void __init efi_set_executable(efi_memory_desc_t *md, bool executable) { u64 addr, npages; ---- a/drivers/firmware/efivars.c -+++ b/drivers/firmware/efivars.c -@@ -89,6 +89,7 @@ MODULE_AUTHOR("Matt Domsch state); } @@ -17,7 +19,7 @@ static inline struct backing_dev_info *inode_to_bdi(struct inode *inode) { -@@ -1406,3 +1405,6 @@ int sync_inode_metadata(struct inode *in +@@ -1406,3 +1405,6 @@ return sync_inode(inode, &wbc); } EXPORT_SYMBOL(sync_inode_metadata); diff -Nru linux-3.2.46/debian/patches/debian/hid-avoid-ABI-change-in-3.2.31.patch linux-3.2.46/debian/patches/debian/hid-avoid-ABI-change-in-3.2.31.patch --- linux-3.2.46/debian/patches/debian/hid-avoid-ABI-change-in-3.2.31.patch 2013-04-11 03:27:32.000000000 +0000 +++ linux-3.2.46/debian/patches/debian/hid-avoid-ABI-change-in-3.2.31.patch 2013-07-26 19:25:03.000000000 +0000 @@ -8,9 +8,11 @@ (an error number). Any existing OOT callers are going to ignore this value, whether or not they get recompiled. Therefore, hide the change from genksyms. ---- a/include/linux/hid.h -+++ b/include/linux/hid.h -@@ -875,8 +875,14 @@ static inline int hid_hw_power(struct hi +Index: linux-3.2.46/include/linux/hid.h +=================================================================== +--- linux-3.2.46.orig/include/linux/hid.h 2013-07-26 18:54:04.000000000 +0000 ++++ linux-3.2.46/include/linux/hid.h 2013-07-26 19:25:01.000000000 +0000 +@@ -875,8 +875,14 @@ return hdev->ll_driver->power ? hdev->ll_driver->power(hdev, level) : 0; } @@ -25,9 +27,11 @@ extern int hid_generic_init(void); extern void hid_generic_exit(void); ---- a/include/linux/hidraw.h -+++ b/include/linux/hidraw.h -@@ -76,7 +76,12 @@ struct hidraw_list { +Index: linux-3.2.46/include/linux/hidraw.h +=================================================================== +--- linux-3.2.46.orig/include/linux/hidraw.h 2013-07-26 18:54:04.000000000 +0000 ++++ linux-3.2.46/include/linux/hidraw.h 2013-07-26 19:25:01.000000000 +0000 +@@ -76,7 +76,12 @@ #ifdef CONFIG_HIDRAW int hidraw_init(void); void hidraw_exit(void); diff -Nru linux-3.2.46/debian/patches/debian/inet_frag-avoid-abi-change-in-3.2.42.patch linux-3.2.46/debian/patches/debian/inet_frag-avoid-abi-change-in-3.2.42.patch --- linux-3.2.46/debian/patches/debian/inet_frag-avoid-abi-change-in-3.2.42.patch 2013-04-11 03:27:32.000000000 +0000 +++ linux-3.2.46/debian/patches/debian/inet_frag-avoid-abi-change-in-3.2.42.patch 2013-07-26 19:30:45.000000000 +0000 @@ -6,8 +6,10 @@ Hide an added #include from genksyms, as it will otherwise change symbol versions. --- ---- a/net/ipv4/inet_fragment.c -+++ b/net/ipv4/inet_fragment.c +Index: linux-3.2.46/net/ipv4/inet_fragment.c +=================================================================== +--- linux-3.2.46.orig/net/ipv4/inet_fragment.c 2013-07-26 18:52:16.000000000 +0000 ++++ linux-3.2.46/net/ipv4/inet_fragment.c 2013-07-26 19:30:44.000000000 +0000 @@ -21,7 +21,9 @@ #include #include diff -Nru linux-3.2.46/debian/patches/debian/iwlwifi-do-not-request-unreleased-firmware.patch linux-3.2.46/debian/patches/debian/iwlwifi-do-not-request-unreleased-firmware.patch --- linux-3.2.46/debian/patches/debian/iwlwifi-do-not-request-unreleased-firmware.patch 2013-04-18 04:42:42.000000000 +0000 +++ linux-3.2.46/debian/patches/debian/iwlwifi-do-not-request-unreleased-firmware.patch 2013-07-26 19:25:01.000000000 +0000 @@ -17,8 +17,10 @@ not easy to detect that this particular failure is harmless. So stop requesting the unreleased firmware. ---- a/drivers/net/wireless/iwlwifi/iwl-6000.c -+++ b/drivers/net/wireless/iwlwifi/iwl-6000.c +Index: linux-3.2.46/drivers/net/wireless/iwlwifi/iwl-6000.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/wireless/iwlwifi/iwl-6000.c 2013-07-26 18:54:04.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/iwlwifi/iwl-6000.c 2013-07-26 19:25:00.000000000 +0000 @@ -46,9 +46,10 @@ #include "iwl-cfg.h" @@ -32,7 +34,7 @@ #define IWL6035_UCODE_API_MAX 6 /* Oldest version we won't warn about */ -@@ -413,7 +414,7 @@ struct iwl_cfg iwl6005_2agn_d_cfg = { +@@ -413,7 +414,7 @@ #define IWL_DEVICE_6030 \ .fw_name_pre = IWL6030_FW_PRE, \ diff -Nru linux-3.2.46/debian/patches/debian/jbd2-avoid-ABI-change-in-3.2.45.patch linux-3.2.46/debian/patches/debian/jbd2-avoid-ABI-change-in-3.2.45.patch --- linux-3.2.46/debian/patches/debian/jbd2-avoid-ABI-change-in-3.2.45.patch 2013-06-07 01:38:04.000000000 +0000 +++ linux-3.2.46/debian/patches/debian/jbd2-avoid-ABI-change-in-3.2.45.patch 2013-07-26 19:30:53.000000000 +0000 @@ -7,9 +7,11 @@ and ->j_commit_callback' in 3.2.45. t_state is accessed only by jbd2 itself, not the filesystems that use jbd2, so this shouldn't affect binary compatibility. Hide the change from genksyms. ---- a/include/linux/jbd2.h -+++ b/include/linux/jbd2.h -@@ -470,7 +470,9 @@ struct transaction_s +Index: linux-3.2.46/include/linux/jbd2.h +=================================================================== +--- linux-3.2.46.orig/include/linux/jbd2.h 2013-07-26 18:52:13.000000000 +0000 ++++ linux-3.2.46/include/linux/jbd2.h 2013-07-26 19:30:52.000000000 +0000 +@@ -470,7 +470,9 @@ T_COMMIT, T_COMMIT_DFLUSH, T_COMMIT_JFLUSH, diff -Nru linux-3.2.46/debian/patches/debian/kernelvariables.patch linux-3.2.46/debian/patches/debian/kernelvariables.patch --- linux-3.2.46/debian/patches/debian/kernelvariables.patch 2013-04-11 03:27:32.000000000 +0000 +++ linux-3.2.46/debian/patches/debian/kernelvariables.patch 2013-07-26 19:16:46.000000000 +0000 @@ -12,8 +12,10 @@ This file can only be read after we establish the build tree, and all use of $(ARCH) needs to be moved after this. ---- a/Makefile -+++ b/Makefile +Index: linux-3.2.46/Makefile +=================================================================== +--- linux-3.2.46.orig/Makefile 2013-07-26 19:16:41.000000000 +0000 ++++ linux-3.2.46/Makefile 2013-07-26 19:16:45.000000000 +0000 @@ -195,46 +195,6 @@ ARCH ?= $(SUBARCH) CROSS_COMPILE ?= $(CONFIG_CROSS_COMPILE:"%"=%) diff -Nru linux-3.2.46/debian/patches/debian/mips-disable-werror.patch linux-3.2.46/debian/patches/debian/mips-disable-werror.patch --- linux-3.2.46/debian/patches/debian/mips-disable-werror.patch 2013-04-11 03:27:32.000000000 +0000 +++ linux-3.2.46/debian/patches/debian/mips-disable-werror.patch 2013-07-26 19:17:09.000000000 +0000 @@ -10,10 +10,10 @@ arch/mips/Kbuild | 5 ----- 1 files changed, 0 insertions(+), 5 deletions(-) -diff --git a/arch/mips/Kbuild b/arch/mips/Kbuild -index e322d65..2e6b28f 100644 ---- a/arch/mips/Kbuild -+++ b/arch/mips/Kbuild +Index: linux-3.2.46/arch/mips/Kbuild +=================================================================== +--- linux-3.2.46.orig/arch/mips/Kbuild 2013-07-26 18:56:37.000000000 +0000 ++++ linux-3.2.46/arch/mips/Kbuild 2013-07-26 19:17:08.000000000 +0000 @@ -1,8 +1,3 @@ -# Fail on warnings - also for files referenced in subdirs -# -Werror can be disabled for specific files using: @@ -23,6 +23,3 @@ # platform specific definitions include arch/mips/Kbuild.platforms obj-y := $(platform-y) --- -1.7.1 - diff -Nru linux-3.2.46/debian/patches/debian/mm-avoid-ABI-change-in-3.2.33.patch linux-3.2.46/debian/patches/debian/mm-avoid-ABI-change-in-3.2.33.patch --- linux-3.2.46/debian/patches/debian/mm-avoid-ABI-change-in-3.2.33.patch 2013-04-11 03:27:32.000000000 +0000 +++ linux-3.2.46/debian/patches/debian/mm-avoid-ABI-change-in-3.2.33.patch 2013-07-26 19:25:12.000000000 +0000 @@ -6,8 +6,10 @@ Don't let genksyms see the new #include, as this changes symbol versions. --- ---- a/mm/rmap.c -+++ b/mm/rmap.c +Index: linux-3.2.46/mm/rmap.c +=================================================================== +--- linux-3.2.46.orig/mm/rmap.c 2013-07-26 18:54:01.000000000 +0000 ++++ linux-3.2.46/mm/rmap.c 2013-07-26 19:25:11.000000000 +0000 @@ -56,7 +56,9 @@ #include #include diff -Nru linux-3.2.46/debian/patches/debian/net-avoid-ABI-break-in-3.2.37.patch linux-3.2.46/debian/patches/debian/net-avoid-ABI-break-in-3.2.37.patch --- linux-3.2.46/debian/patches/debian/net-avoid-ABI-break-in-3.2.37.patch 2013-04-11 03:27:32.000000000 +0000 +++ linux-3.2.46/debian/patches/debian/net-avoid-ABI-break-in-3.2.37.patch 2013-07-26 19:26:07.000000000 +0000 @@ -9,9 +9,11 @@ deleted enumerator and hide the added enumerators from genksyms. --- ---- a/include/linux/snmp.h -+++ b/include/linux/snmp.h -@@ -210,6 +210,7 @@ enum +Index: linux-3.2.46/include/linux/snmp.h +=================================================================== +--- linux-3.2.46.orig/include/linux/snmp.h 2013-07-26 18:53:39.000000000 +0000 ++++ linux-3.2.46/include/linux/snmp.h 2013-07-26 19:26:06.000000000 +0000 +@@ -210,6 +210,7 @@ LINUX_MIB_TCPDSACKRECV, /* TCPDSACKRecv */ LINUX_MIB_TCPDSACKOFORECV, /* TCPDSACKOfoRecv */ LINUX_MIB_TCPABORTONDATA, /* TCPAbortOnData */ @@ -19,7 +21,7 @@ LINUX_MIB_TCPABORTONCLOSE, /* TCPAbortOnClose */ LINUX_MIB_TCPABORTONMEMORY, /* TCPAbortOnMemory */ LINUX_MIB_TCPABORTONTIMEOUT, /* TCPAbortOnTimeout */ -@@ -232,8 +233,10 @@ enum +@@ -232,8 +233,10 @@ LINUX_MIB_TCPTIMEWAITOVERFLOW, /* TCPTimeWaitOverflow */ LINUX_MIB_TCPREQQFULLDOCOOKIES, /* TCPReqQFullDoCookies */ LINUX_MIB_TCPREQQFULLDROP, /* TCPReqQFullDrop */ diff -Nru linux-3.2.46/debian/patches/debian/perf-hide-abi-change-in-3.2.30.patch linux-3.2.46/debian/patches/debian/perf-hide-abi-change-in-3.2.30.patch --- linux-3.2.46/debian/patches/debian/perf-hide-abi-change-in-3.2.30.patch 2013-04-11 03:27:32.000000000 +0000 +++ linux-3.2.46/debian/patches/debian/perf-hide-abi-change-in-3.2.30.patch 2013-07-26 19:24:59.000000000 +0000 @@ -8,9 +8,11 @@ The new member (atomic_long_t refcount) has the same size as the old (struct file *filp) and neither should be needed by OOT modules (if they make use of perf_events at all). So pretend this didn't happen. ---- a/include/linux/perf_event.h -+++ b/include/linux/perf_event.h -@@ -794,7 +794,11 @@ struct perf_event { +Index: linux-3.2.46/include/linux/perf_event.h +=================================================================== +--- linux-3.2.46.orig/include/linux/perf_event.h 2013-07-26 18:54:05.000000000 +0000 ++++ linux-3.2.46/include/linux/perf_event.h 2013-07-26 19:24:59.000000000 +0000 +@@ -794,7 +794,11 @@ struct hw_perf_event hw; struct perf_event_context *ctx; diff -Nru linux-3.2.46/debian/patches/debian/pps-avoid-abi-change-in-3.2.40.patch linux-3.2.46/debian/patches/debian/pps-avoid-abi-change-in-3.2.40.patch --- linux-3.2.46/debian/patches/debian/pps-avoid-abi-change-in-3.2.40.patch 2013-04-11 03:27:32.000000000 +0000 +++ linux-3.2.46/debian/patches/debian/pps-avoid-abi-change-in-3.2.40.patch 2013-07-26 19:30:24.000000000 +0000 @@ -8,9 +8,11 @@ allocated by pps_register_source(). --- ---- a/include/linux/pps_kernel.h -+++ b/include/linux/pps_kernel.h -@@ -69,11 +69,14 @@ struct pps_device { +Index: linux-3.2.46/include/linux/pps_kernel.h +=================================================================== +--- linux-3.2.46.orig/include/linux/pps_kernel.h 2013-07-26 18:52:23.000000000 +0000 ++++ linux-3.2.46/include/linux/pps_kernel.h 2013-07-26 19:30:23.000000000 +0000 +@@ -69,11 +69,14 @@ wait_queue_head_t queue; /* PPS event queue */ unsigned int id; /* PPS source unique ID */ diff -Nru linux-3.2.46/debian/patches/debian/radeon-firmware-is-required-for-drm-and-kms-on-r600-onward.patch linux-3.2.46/debian/patches/debian/radeon-firmware-is-required-for-drm-and-kms-on-r600-onward.patch --- linux-3.2.46/debian/patches/debian/radeon-firmware-is-required-for-drm-and-kms-on-r600-onward.patch 2013-02-24 03:52:24.000000000 +0000 +++ linux-3.2.46/debian/patches/debian/radeon-firmware-is-required-for-drm-and-kms-on-r600-onward.patch 2013-07-26 19:27:16.000000000 +0000 @@ -25,8 +25,10 @@ missing, except for the pre-R600 KMS case. --- ---- a/drivers/gpu/drm/radeon/radeon_drv.c -+++ b/drivers/gpu/drm/radeon/radeon_drv.c +Index: linux-3.2.46/drivers/gpu/drm/radeon/radeon_drv.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/radeon/radeon_drv.c 2013-07-26 19:26:24.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/radeon/radeon_drv.c 2013-07-26 19:27:15.000000000 +0000 @@ -37,6 +37,8 @@ #include "drm_pciids.h" #include @@ -36,7 +38,7 @@ /* -@@ -257,6 +259,35 @@ static struct drm_driver driver_old = { +@@ -266,6 +268,35 @@ static struct drm_driver kms_driver; @@ -72,7 +74,7 @@ static void radeon_kick_out_firmware_fb(struct pci_dev *pdev) { struct apertures_struct *ap; -@@ -276,6 +307,12 @@ static void radeon_kick_out_firmware_fb( +@@ -285,6 +316,12 @@ static int __devinit radeon_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) { @@ -85,7 +87,7 @@ /* Get rid of things like offb */ radeon_kick_out_firmware_fb(pdev); -@@ -367,6 +404,7 @@ static struct pci_driver *pdriver; +@@ -379,6 +416,7 @@ static struct pci_driver radeon_pci_driver = { .name = DRIVER_NAME, .id_table = pciidlist, diff -Nru linux-3.2.46/debian/patches/debian/rds-Disable-auto-loading-as-mitigation-against-local.patch linux-3.2.46/debian/patches/debian/rds-Disable-auto-loading-as-mitigation-against-local.patch --- linux-3.2.46/debian/patches/debian/rds-Disable-auto-loading-as-mitigation-against-local.patch 2013-04-11 03:27:32.000000000 +0000 +++ linux-3.2.46/debian/patches/debian/rds-Disable-auto-loading-as-mitigation-against-local.patch 2013-07-26 19:17:16.000000000 +0000 @@ -19,16 +19,13 @@ net/rds/af_rds.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) -diff --git a/net/rds/af_rds.c b/net/rds/af_rds.c -index 98e0538..d8d4525 100644 ---- a/net/rds/af_rds.c -+++ b/net/rds/af_rds.c -@@ -574,4 +574,4 @@ MODULE_DESCRIPTION("RDS: Reliable Datagram Sockets" +Index: linux-3.2.46/net/rds/af_rds.c +=================================================================== +--- linux-3.2.46.orig/net/rds/af_rds.c 2013-07-26 18:56:35.000000000 +0000 ++++ linux-3.2.46/net/rds/af_rds.c 2013-07-26 19:17:15.000000000 +0000 +@@ -596,4 +596,4 @@ " v" DRV_VERSION " (" DRV_RELDATE ")"); MODULE_VERSION(DRV_VERSION); MODULE_LICENSE("Dual BSD/GPL"); -MODULE_ALIAS_NETPROTO(PF_RDS); +/* MODULE_ALIAS_NETPROTO(PF_RDS); */ --- -1.7.2.3 - diff -Nru linux-3.2.46/debian/patches/debian/rtnetlink-avoid-ABI-change-in-3.2.34.patch linux-3.2.46/debian/patches/debian/rtnetlink-avoid-ABI-change-in-3.2.34.patch --- linux-3.2.46/debian/patches/debian/rtnetlink-avoid-ABI-change-in-3.2.34.patch 2013-04-11 03:27:32.000000000 +0000 +++ linux-3.2.46/debian/patches/debian/rtnetlink-avoid-ABI-change-in-3.2.34.patch 2013-07-26 19:25:11.000000000 +0000 @@ -14,8 +14,10 @@ hide the change from genksyms. --- ---- a/include/net/rtnetlink.h -+++ b/include/net/rtnetlink.h +Index: linux-3.2.46/include/net/rtnetlink.h +=================================================================== +--- linux-3.2.46.orig/include/net/rtnetlink.h 2013-07-26 18:54:02.000000000 +0000 ++++ linux-3.2.46/include/net/rtnetlink.h 2013-07-26 19:25:10.000000000 +0000 @@ -6,7 +6,7 @@ typedef int (*rtnl_doit_func)(struct sk_buff *, struct nlmsghdr *, void *); @@ -25,9 +27,11 @@ extern int __rtnl_register(int protocol, int msgtype, rtnl_doit_func, rtnl_dumpit_func, ---- a/net/core/rtnetlink.c -+++ b/net/core/rtnetlink.c -@@ -1116,7 +1116,9 @@ const struct nla_policy ifla_policy[IFLA +Index: linux-3.2.46/net/core/rtnetlink.c +=================================================================== +--- linux-3.2.46.orig/net/core/rtnetlink.c 2013-07-26 18:54:02.000000000 +0000 ++++ linux-3.2.46/net/core/rtnetlink.c 2013-07-26 19:25:10.000000000 +0000 +@@ -1117,7 +1117,9 @@ [IFLA_VF_PORTS] = { .type = NLA_NESTED }, [IFLA_PORT_SELF] = { .type = NLA_NESTED }, [IFLA_AF_SPEC] = { .type = NLA_NESTED }, @@ -37,7 +41,7 @@ }; EXPORT_SYMBOL(ifla_policy); -@@ -2020,7 +2022,9 @@ static int rtnetlink_rcv_msg(struct sk_b +@@ -2021,7 +2023,9 @@ return -EOPNOTSUPP; calcit = rtnl_get_calcit(family, type); if (calcit) @@ -48,7 +52,7 @@ __rtnl_unlock(); rtnl = net->rtnl; -@@ -2136,7 +2140,7 @@ void __init rtnetlink_init(void) +@@ -2137,7 +2141,7 @@ register_netdevice_notifier(&rtnetlink_dev_notifier); rtnl_register(PF_UNSPEC, RTM_GETLINK, rtnl_getlink, @@ -57,9 +61,11 @@ rtnl_register(PF_UNSPEC, RTM_SETLINK, rtnl_setlink, NULL, NULL); rtnl_register(PF_UNSPEC, RTM_NEWLINK, rtnl_newlink, NULL, NULL); rtnl_register(PF_UNSPEC, RTM_DELLINK, rtnl_dellink, NULL, NULL); ---- a/include/linux/if_link.h -+++ b/include/linux/if_link.h -@@ -137,7 +137,9 @@ enum { +Index: linux-3.2.46/include/linux/if_link.h +=================================================================== +--- linux-3.2.46.orig/include/linux/if_link.h 2013-07-26 18:54:02.000000000 +0000 ++++ linux-3.2.46/include/linux/if_link.h 2013-07-26 19:25:10.000000000 +0000 +@@ -137,7 +137,9 @@ IFLA_AF_SPEC, IFLA_GROUP, /* Group the device belongs to */ IFLA_NET_NS_FD, diff -Nru linux-3.2.46/debian/patches/debian/sched-autogroup-disabled.patch linux-3.2.46/debian/patches/debian/sched-autogroup-disabled.patch --- linux-3.2.46/debian/patches/debian/sched-autogroup-disabled.patch 2013-04-11 03:27:32.000000000 +0000 +++ linux-3.2.46/debian/patches/debian/sched-autogroup-disabled.patch 2013-07-26 19:17:22.000000000 +0000 @@ -6,10 +6,10 @@ We want to provide the option of autogrouping but without enabling it by default yet. -diff --git a/kernel/sched_autogroup.c b/kernel/sched_autogroup.c -index 9fb6562..96abaaf 100644 ---- a/kernel/sched_autogroup.c -+++ b/kernel/sched_autogroup.c +Index: linux-3.2.46/kernel/sched_autogroup.c +=================================================================== +--- linux-3.2.46.orig/kernel/sched_autogroup.c 2013-07-26 18:56:33.000000000 +0000 ++++ linux-3.2.46/kernel/sched_autogroup.c 2013-07-26 19:17:21.000000000 +0000 @@ -5,7 +5,7 @@ #include #include diff -Nru linux-3.2.46/debian/patches/debian/skb-avoid-abi-change-in-3.2.42.patch linux-3.2.46/debian/patches/debian/skb-avoid-abi-change-in-3.2.42.patch --- linux-3.2.46/debian/patches/debian/skb-avoid-abi-change-in-3.2.42.patch 2013-04-11 03:27:32.000000000 +0000 +++ linux-3.2.46/debian/patches/debian/skb-avoid-abi-change-in-3.2.42.patch 2013-07-26 19:30:42.000000000 +0000 @@ -10,9 +10,11 @@ genksyms. --- ---- a/include/linux/skbuff.h -+++ b/include/linux/skbuff.h -@@ -455,7 +455,12 @@ struct sk_buff { +Index: linux-3.2.46/include/linux/skbuff.h +=================================================================== +--- linux-3.2.46.orig/include/linux/skbuff.h 2013-07-26 18:52:17.000000000 +0000 ++++ linux-3.2.46/include/linux/skbuff.h 2013-07-26 19:30:41.000000000 +0000 +@@ -455,7 +455,12 @@ union { __u32 mark; __u32 dropcount; diff -Nru linux-3.2.46/debian/patches/debian/sysrq-mask.patch linux-3.2.46/debian/patches/debian/sysrq-mask.patch --- linux-3.2.46/debian/patches/debian/sysrq-mask.patch 2013-02-24 03:52:24.000000000 +0000 +++ linux-3.2.46/debian/patches/debian/sysrq-mask.patch 2013-07-26 19:17:12.000000000 +0000 @@ -5,8 +5,10 @@ Add a Kconfig variable to set the initial value of the Magic SysRq mask (sysctl: kernel.sysrq). ---- a/include/linux/sysrq.h -+++ b/include/linux/sysrq.h +Index: linux-3.2.46/include/linux/sysrq.h +=================================================================== +--- linux-3.2.46.orig/include/linux/sysrq.h 2013-07-26 18:56:36.000000000 +0000 ++++ linux-3.2.46/include/linux/sysrq.h 2013-07-26 19:17:11.000000000 +0000 @@ -18,7 +18,7 @@ #include @@ -16,11 +18,11 @@ /* Possible values of bitmask for enabling sysrq functions */ /* 0x0001 is reserved for enable everything */ -diff --git a/lib/Kconfig.debug b/lib/Kconfig.debug -index 234ceb1..415a834 100644 ---- a/lib/Kconfig.debug -+++ b/lib/Kconfig.debug -@@ -50,6 +50,14 @@ config MAGIC_SYSRQ +Index: linux-3.2.46/lib/Kconfig.debug +=================================================================== +--- linux-3.2.46.orig/lib/Kconfig.debug 2013-07-26 18:56:36.000000000 +0000 ++++ linux-3.2.46/lib/Kconfig.debug 2013-07-26 19:17:11.000000000 +0000 +@@ -62,6 +62,14 @@ keys are documented in . Don't say Y unless you really know what this hack does. diff -Nru linux-3.2.46/debian/patches/debian/tracing-avoid-abi-change-in-3.2.42.patch linux-3.2.46/debian/patches/debian/tracing-avoid-abi-change-in-3.2.42.patch --- linux-3.2.46/debian/patches/debian/tracing-avoid-abi-change-in-3.2.42.patch 2013-04-11 03:27:32.000000000 +0000 +++ linux-3.2.46/debian/patches/debian/tracing-avoid-abi-change-in-3.2.42.patch 2013-07-26 19:30:43.000000000 +0000 @@ -13,9 +13,11 @@ Hide the changes from genksyms. --- ---- a/kernel/trace/trace.h -+++ b/kernel/trace/trace.h -@@ -272,13 +272,17 @@ struct tracer { +Index: linux-3.2.46/kernel/trace/trace.h +=================================================================== +--- linux-3.2.46.orig/kernel/trace/trace.h 2013-07-26 18:52:17.000000000 +0000 ++++ linux-3.2.46/kernel/trace/trace.h 2013-07-26 19:30:42.000000000 +0000 +@@ -272,13 +272,17 @@ /* If you handled the flag setting, return 0 */ int (*set_flag)(u32 old_flags, u32 bit, int set); /* Return 0 if OK with change, else return non-zero */ diff -Nru linux-3.2.46/debian/patches/debian/version.patch linux-3.2.46/debian/patches/debian/version.patch --- linux-3.2.46/debian/patches/debian/version.patch 2013-02-24 03:52:24.000000000 +0000 +++ linux-3.2.46/debian/patches/debian/version.patch 2013-07-26 19:16:45.000000000 +0000 @@ -6,9 +6,11 @@ $DISTRIBUTION_OFFICIAL_BUILD, $DISTRIBUTOR and $DISTRIBUTION_VERSION are set. ---- a/Makefile -+++ b/Makefile -@@ -976,7 +976,7 @@ endif +Index: linux-3.2.46/Makefile +=================================================================== +--- linux-3.2.46.orig/Makefile 2013-07-26 18:56:45.000000000 +0000 ++++ linux-3.2.46/Makefile 2013-07-26 19:16:41.000000000 +0000 +@@ -976,7 +976,7 @@ prepare2: prepare3 outputmakefile asm-generic prepare1: prepare2 include/linux/version.h include/generated/utsrelease.h \ @@ -17,7 +19,7 @@ $(cmd_crmodverdir) archprepare: archscripts prepare1 scripts_basic -@@ -1008,12 +1008,25 @@ define filechk_version.h +@@ -1008,12 +1008,25 @@ echo '#define KERNEL_VERSION(a,b,c) (((a) << 16) + ((b) << 8) + (c))';) endef @@ -43,8 +45,10 @@ PHONY += headerdep headerdep: $(Q)find $(srctree)/include/ -name '*.h' | xargs --max-args 1 \ ---- a/arch/s390/kernel/traps.c -+++ b/arch/s390/kernel/traps.c +Index: linux-3.2.46/arch/s390/kernel/traps.c +=================================================================== +--- linux-3.2.46.orig/arch/s390/kernel/traps.c 2013-07-26 18:56:45.000000000 +0000 ++++ linux-3.2.46/arch/s390/kernel/traps.c 2013-07-26 19:16:41.000000000 +0000 @@ -33,6 +33,7 @@ #include #include @@ -53,7 +57,7 @@ #include #include #include -@@ -166,11 +167,12 @@ static void show_last_breaking_event(str +@@ -166,11 +167,12 @@ */ void dump_stack(void) { @@ -68,7 +72,7 @@ printk("Process %s (pid: %d, task: %p, ksp: %p)\n", current->comm, current->pid, current, (void *) current->thread.ksp); -@@ -217,11 +219,12 @@ void show_registers(struct pt_regs *regs +@@ -217,11 +219,12 @@ void show_regs(struct pt_regs *regs) { print_modules(); @@ -83,8 +87,10 @@ printk("Process %s (pid: %d, task: %p, ksp: %p)\n", current->comm, current->pid, current, (void *) current->thread.ksp); ---- a/arch/x86/um/sysrq_64.c -+++ b/arch/x86/um/sysrq_64.c +Index: linux-3.2.46/arch/x86/um/sysrq_64.c +=================================================================== +--- linux-3.2.46.orig/arch/x86/um/sysrq_64.c 2013-07-26 18:56:45.000000000 +0000 ++++ linux-3.2.46/arch/x86/um/sysrq_64.c 2013-07-26 19:16:41.000000000 +0000 @@ -8,6 +8,7 @@ #include #include @@ -93,7 +99,7 @@ #include #include #include "sysrq.h" -@@ -16,8 +17,9 @@ void __show_regs(struct pt_regs *regs) +@@ -16,8 +17,9 @@ { printk("\n"); print_modules(); @@ -105,8 +111,10 @@ printk(KERN_INFO "RIP: %04lx:[<%016lx>]\n", PT_REGS_CS(regs) & 0xffff, PT_REGS_RIP(regs)); printk(KERN_INFO "RSP: %016lx EFLAGS: %08lx\n", PT_REGS_SP(regs), ---- a/arch/x86/kernel/process.c -+++ b/arch/x86/kernel/process.c +Index: linux-3.2.46/arch/x86/kernel/process.c +=================================================================== +--- linux-3.2.46.orig/arch/x86/kernel/process.c 2013-07-26 18:56:45.000000000 +0000 ++++ linux-3.2.46/arch/x86/kernel/process.c 2013-07-26 19:16:41.000000000 +0000 @@ -14,6 +14,7 @@ #include #include @@ -115,7 +123,7 @@ #include #include #include -@@ -105,11 +106,12 @@ void show_regs_common(void) +@@ -105,11 +106,12 @@ board = dmi_get_system_info(DMI_BOARD_NAME); printk(KERN_CONT "\n"); @@ -130,8 +138,10 @@ printk(KERN_CONT " %s %s", vendor, product); if (board) printk(KERN_CONT "/%s", board); ---- a/arch/x86/kernel/dumpstack.c -+++ b/arch/x86/kernel/dumpstack.c +Index: linux-3.2.46/arch/x86/kernel/dumpstack.c +=================================================================== +--- linux-3.2.46.orig/arch/x86/kernel/dumpstack.c 2013-07-26 18:56:45.000000000 +0000 ++++ linux-3.2.46/arch/x86/kernel/dumpstack.c 2013-07-26 19:16:41.000000000 +0000 @@ -15,6 +15,7 @@ #include #include @@ -140,7 +150,7 @@ #include -@@ -185,11 +186,12 @@ void dump_stack(void) +@@ -185,11 +186,12 @@ unsigned long stack; bp = stack_frame(current, NULL); @@ -155,8 +165,10 @@ show_trace(NULL, NULL, &stack, bp); } EXPORT_SYMBOL(dump_stack); ---- a/arch/ia64/kernel/process.c -+++ b/arch/ia64/kernel/process.c +Index: linux-3.2.46/arch/ia64/kernel/process.c +=================================================================== +--- linux-3.2.46.orig/arch/ia64/kernel/process.c 2013-07-26 18:56:45.000000000 +0000 ++++ linux-3.2.46/arch/ia64/kernel/process.c 2013-07-26 19:16:41.000000000 +0000 @@ -29,6 +29,7 @@ #include #include @@ -165,7 +177,7 @@ #include #include -@@ -111,9 +112,9 @@ show_regs (struct pt_regs *regs) +@@ -111,9 +112,9 @@ print_modules(); printk("\nPid: %d, CPU %d, comm: %20s\n", task_pid_nr(current), smp_processor_id(), current->comm); @@ -177,8 +189,10 @@ print_symbol("ip is at %s\n", ip); printk("unat: %016lx pfs : %016lx rsc : %016lx\n", regs->ar_unat, regs->ar_pfs, regs->ar_rsc); ---- a/arch/arm/kernel/process.c -+++ b/arch/arm/kernel/process.c +Index: linux-3.2.46/arch/arm/kernel/process.c +=================================================================== +--- linux-3.2.46.orig/arch/arm/kernel/process.c 2013-07-26 18:56:45.000000000 +0000 ++++ linux-3.2.46/arch/arm/kernel/process.c 2013-07-26 19:16:41.000000000 +0000 @@ -31,6 +31,7 @@ #include #include @@ -187,7 +201,7 @@ #include #include -@@ -261,11 +262,12 @@ void __show_regs(struct pt_regs *regs) +@@ -263,11 +264,12 @@ unsigned long flags; char buf[64]; @@ -202,8 +216,10 @@ print_symbol("PC is at %s\n", instruction_pointer(regs)); print_symbol("LR is at %s\n", regs->ARM_lr); printk("pc : [<%08lx>] lr : [<%08lx>] psr: %08lx\n" ---- a/arch/powerpc/kernel/process.c -+++ b/arch/powerpc/kernel/process.c +Index: linux-3.2.46/arch/powerpc/kernel/process.c +=================================================================== +--- linux-3.2.46.orig/arch/powerpc/kernel/process.c 2013-07-26 18:56:45.000000000 +0000 ++++ linux-3.2.46/arch/powerpc/kernel/process.c 2013-07-26 19:16:42.000000000 +0000 @@ -38,6 +38,7 @@ #include #include @@ -212,7 +228,7 @@ #include #include -@@ -626,8 +627,9 @@ void show_regs(struct pt_regs * regs) +@@ -626,8 +627,9 @@ printk("NIP: "REG" LR: "REG" CTR: "REG"\n", regs->nip, regs->link, regs->ctr); @@ -224,8 +240,10 @@ printk("MSR: "REG" ", regs->msr); printbits(regs->msr, msr_bits); printk(" CR: %08lx XER: %08lx\n", regs->ccr, regs->xer); ---- a/arch/sh/kernel/process_32.c -+++ b/arch/sh/kernel/process_32.c +Index: linux-3.2.46/arch/sh/kernel/process_32.c +=================================================================== +--- linux-3.2.46.orig/arch/sh/kernel/process_32.c 2013-07-26 18:56:45.000000000 +0000 ++++ linux-3.2.46/arch/sh/kernel/process_32.c 2013-07-26 19:16:42.000000000 +0000 @@ -22,6 +22,7 @@ #include #include @@ -234,7 +252,7 @@ #include #include #include -@@ -32,10 +33,11 @@ void show_regs(struct pt_regs * regs) +@@ -32,10 +33,11 @@ { printk("\n"); printk("Pid : %d, Comm: \t\t%s\n", task_pid_nr(current), current->comm); diff -Nru linux-3.2.46/debian/patches/debian/x86-efi-avoid-abi-change-in-3.2.38.patch linux-3.2.46/debian/patches/debian/x86-efi-avoid-abi-change-in-3.2.38.patch --- linux-3.2.46/debian/patches/debian/x86-efi-avoid-abi-change-in-3.2.38.patch 2013-04-11 03:27:32.000000000 +0000 +++ linux-3.2.46/debian/patches/debian/x86-efi-avoid-abi-change-in-3.2.38.patch 2013-07-26 19:30:21.000000000 +0000 @@ -14,8 +14,10 @@ and make efi_enabled() a function-macro. This should keep both old and new usage working. ---- a/arch/x86/platform/efi/efi.c -+++ b/arch/x86/platform/efi/efi.c +Index: linux-3.2.46/arch/x86/platform/efi/efi.c +=================================================================== +--- linux-3.2.46.orig/arch/x86/platform/efi/efi.c 2013-07-26 18:52:24.000000000 +0000 ++++ linux-3.2.46/arch/x86/platform/efi/efi.c 2013-07-26 19:30:20.000000000 +0000 @@ -49,6 +49,9 @@ #define EFI_DEBUG 1 #define PFX "EFI: " @@ -26,7 +28,7 @@ struct efi __read_mostly efi = { .mps = EFI_INVALID_TABLE_ADDR, .acpi = EFI_INVALID_TABLE_ADDR, -@@ -77,11 +80,11 @@ unsigned long x86_efi_facility; +@@ -77,11 +80,11 @@ /* * Returns 1 if 'facility' is enabled, 0 otherwise. */ @@ -40,7 +42,7 @@ static bool disable_runtime = false; static int __init setup_noefi(char *arg) -@@ -576,6 +579,7 @@ void __init efi_init(void) +@@ -585,6 +588,7 @@ efi.get_time = phys_efi_get_time; set_bit(EFI_RUNTIME_SERVICES, &x86_efi_facility); @@ -48,9 +50,11 @@ } else printk(KERN_ERR "Could not map the EFI runtime service " "table!\n"); ---- a/include/linux/efi.h -+++ b/include/linux/efi.h -@@ -503,7 +503,9 @@ extern int __init efi_setup_pcdp_console +Index: linux-3.2.46/include/linux/efi.h +=================================================================== +--- linux-3.2.46.orig/include/linux/efi.h 2013-07-26 19:19:51.000000000 +0000 ++++ linux-3.2.46/include/linux/efi.h 2013-07-26 19:30:20.000000000 +0000 +@@ -517,7 +517,9 @@ #ifdef CONFIG_EFI # ifdef CONFIG_X86 diff -Nru linux-3.2.46/debian/patches/debian/x86-memtest-WARN-if-bad-RAM-found.patch linux-3.2.46/debian/patches/debian/x86-memtest-WARN-if-bad-RAM-found.patch --- linux-3.2.46/debian/patches/debian/x86-memtest-WARN-if-bad-RAM-found.patch 2013-02-24 03:52:24.000000000 +0000 +++ linux-3.2.46/debian/patches/debian/x86-memtest-WARN-if-bad-RAM-found.patch 2013-07-26 19:17:32.000000000 +0000 @@ -11,11 +11,11 @@ arch/x86/mm/memtest.c | 2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) -diff --git a/arch/x86/mm/memtest.c b/arch/x86/mm/memtest.c -index 92faf3a..ac6bdaa 100644 ---- a/arch/x86/mm/memtest.c -+++ b/arch/x86/mm/memtest.c -@@ -30,6 +30,8 @@ static u64 patterns[] __initdata = { +Index: linux-3.2.46/arch/x86/mm/memtest.c +=================================================================== +--- linux-3.2.46.orig/arch/x86/mm/memtest.c 2013-07-26 18:56:30.000000000 +0000 ++++ linux-3.2.46/arch/x86/mm/memtest.c 2013-07-26 19:17:31.000000000 +0000 +@@ -30,6 +30,8 @@ static void __init reserve_bad_mem(u64 pattern, u64 start_bad, u64 end_bad) { @@ -24,6 +24,3 @@ printk(KERN_INFO " %016llx bad mem addr %010llx - %010llx reserved\n", (unsigned long long) pattern, (unsigned long long) start_bad, --- -1.7.7.3 - diff -Nru linux-3.2.46/debian/patches/debian/x86-mm-avoid-abi-change-in-3.2.44.patch linux-3.2.46/debian/patches/debian/x86-mm-avoid-abi-change-in-3.2.44.patch --- linux-3.2.46/debian/patches/debian/x86-mm-avoid-abi-change-in-3.2.44.patch 2013-04-29 04:05:39.000000000 +0000 +++ linux-3.2.46/debian/patches/debian/x86-mm-avoid-abi-change-in-3.2.44.patch 2013-07-26 19:30:46.000000000 +0000 @@ -20,9 +20,11 @@ be out of luck. --- ---- a/arch/x86/include/asm/paravirt.h -+++ b/arch/x86/include/asm/paravirt.h -@@ -742,7 +742,7 @@ static inline void arch_leave_lazy_mmu_m +Index: linux-3.2.46/arch/x86/include/asm/paravirt.h +=================================================================== +--- linux-3.2.46.orig/arch/x86/include/asm/paravirt.h 2013-07-26 18:52:16.000000000 +0000 ++++ linux-3.2.46/arch/x86/include/asm/paravirt.h 2013-07-26 19:30:45.000000000 +0000 +@@ -742,7 +742,7 @@ static inline void arch_flush_lazy_mmu_mode(void) { @@ -31,9 +33,11 @@ } static inline void __set_fixmap(unsigned /* enum fixed_addresses */ idx, ---- a/arch/x86/include/asm/paravirt_types.h -+++ b/arch/x86/include/asm/paravirt_types.h -@@ -91,7 +91,6 @@ struct pv_lazy_ops { +Index: linux-3.2.46/arch/x86/include/asm/paravirt_types.h +=================================================================== +--- linux-3.2.46.orig/arch/x86/include/asm/paravirt_types.h 2013-07-26 18:52:16.000000000 +0000 ++++ linux-3.2.46/arch/x86/include/asm/paravirt_types.h 2013-07-26 19:30:45.000000000 +0000 +@@ -91,7 +91,6 @@ /* Set deferred update mode, used for batching operations. */ void (*enter)(void); void (*leave)(void); @@ -41,7 +45,7 @@ }; struct pv_time_ops { -@@ -348,6 +347,9 @@ struct paravirt_patch_template { +@@ -348,6 +347,9 @@ struct pv_apic_ops pv_apic_ops; struct pv_mmu_ops pv_mmu_ops; struct pv_lock_ops pv_lock_ops; @@ -51,7 +55,7 @@ }; extern struct pv_info pv_info; -@@ -358,6 +360,7 @@ extern struct pv_irq_ops pv_irq_ops; +@@ -358,6 +360,7 @@ extern struct pv_apic_ops pv_apic_ops; extern struct pv_mmu_ops pv_mmu_ops; extern struct pv_lock_ops pv_lock_ops; @@ -59,9 +63,11 @@ #define PARAVIRT_PATCH(x) \ (offsetof(struct paravirt_patch_template, x) / sizeof(void *)) ---- a/arch/x86/kernel/paravirt.c -+++ b/arch/x86/kernel/paravirt.c -@@ -132,6 +132,7 @@ static void *get_call_destination(u8 typ +Index: linux-3.2.46/arch/x86/kernel/paravirt.c +=================================================================== +--- linux-3.2.46.orig/arch/x86/kernel/paravirt.c 2013-07-26 18:52:16.000000000 +0000 ++++ linux-3.2.46/arch/x86/kernel/paravirt.c 2013-07-26 19:30:45.000000000 +0000 +@@ -132,6 +132,7 @@ #ifdef CONFIG_PARAVIRT_SPINLOCKS .pv_lock_ops = pv_lock_ops, #endif @@ -69,7 +75,7 @@ }; return *((void **)&tmpl + type); } -@@ -475,12 +476,13 @@ struct pv_mmu_ops pv_mmu_ops = { +@@ -475,12 +476,13 @@ .lazy_mode = { .enter = paravirt_nop, .leave = paravirt_nop, @@ -84,9 +90,11 @@ EXPORT_SYMBOL_GPL(pv_time_ops); EXPORT_SYMBOL (pv_cpu_ops); EXPORT_SYMBOL (pv_mmu_ops); ---- a/arch/x86/lguest/boot.c -+++ b/arch/x86/lguest/boot.c -@@ -1328,7 +1328,7 @@ __init void lguest_init(void) +Index: linux-3.2.46/arch/x86/lguest/boot.c +=================================================================== +--- linux-3.2.46.orig/arch/x86/lguest/boot.c 2013-07-26 18:52:16.000000000 +0000 ++++ linux-3.2.46/arch/x86/lguest/boot.c 2013-07-26 19:30:45.000000000 +0000 +@@ -1328,7 +1328,7 @@ pv_mmu_ops.read_cr3 = lguest_read_cr3; pv_mmu_ops.lazy_mode.enter = paravirt_enter_lazy_mmu; pv_mmu_ops.lazy_mode.leave = lguest_leave_lazy_mmu_mode; @@ -95,9 +103,11 @@ pv_mmu_ops.pte_update = lguest_pte_update; pv_mmu_ops.pte_update_defer = lguest_pte_update; ---- a/arch/x86/xen/mmu.c -+++ b/arch/x86/xen/mmu.c -@@ -2079,7 +2079,6 @@ static const struct pv_mmu_ops xen_mmu_o +Index: linux-3.2.46/arch/x86/xen/mmu.c +=================================================================== +--- linux-3.2.46.orig/arch/x86/xen/mmu.c 2013-07-26 18:52:16.000000000 +0000 ++++ linux-3.2.46/arch/x86/xen/mmu.c 2013-07-26 19:30:45.000000000 +0000 +@@ -2079,7 +2079,6 @@ .lazy_mode = { .enter = paravirt_enter_lazy_mmu, .leave = xen_leave_lazy_mmu, @@ -105,7 +115,7 @@ }, .set_fixmap = xen_set_fixmap, -@@ -2091,6 +2090,7 @@ void __init xen_init_mmu_ops(void) +@@ -2091,6 +2090,7 @@ x86_init.paging.pagetable_setup_start = xen_pagetable_setup_start; x86_init.paging.pagetable_setup_done = xen_pagetable_setup_done; pv_mmu_ops = xen_mmu_ops; diff -Nru linux-3.2.46/debian/patches/debian/xfrm-avoid-ABI-change-in-3.2.31.patch linux-3.2.46/debian/patches/debian/xfrm-avoid-ABI-change-in-3.2.31.patch --- linux-3.2.46/debian/patches/debian/xfrm-avoid-ABI-change-in-3.2.31.patch 2013-04-11 03:27:32.000000000 +0000 +++ linux-3.2.46/debian/patches/debian/xfrm-avoid-ABI-change-in-3.2.31.patch 2013-07-26 19:25:05.000000000 +0000 @@ -9,9 +9,11 @@ operation, check whether we're using that instance and call the recheck implementation directly. ---- a/include/net/xfrm.h -+++ b/include/net/xfrm.h -@@ -269,9 +269,6 @@ struct xfrm_replay { +Index: linux-3.2.46/include/net/xfrm.h +=================================================================== +--- linux-3.2.46.orig/include/net/xfrm.h 2013-07-26 18:54:04.000000000 +0000 ++++ linux-3.2.46/include/net/xfrm.h 2013-07-26 19:25:04.000000000 +0000 +@@ -269,9 +269,6 @@ int (*check)(struct xfrm_state *x, struct sk_buff *skb, __be32 net_seq); @@ -21,9 +23,11 @@ void (*notify)(struct xfrm_state *x, int event); int (*overflow)(struct xfrm_state *x, struct sk_buff *skb); }; ---- a/net/xfrm/xfrm_input.c -+++ b/net/xfrm/xfrm_input.c -@@ -102,6 +102,19 @@ int xfrm_prepare_input(struct xfrm_state +Index: linux-3.2.46/net/xfrm/xfrm_input.c +=================================================================== +--- linux-3.2.46.orig/net/xfrm/xfrm_input.c 2013-07-26 18:54:04.000000000 +0000 ++++ linux-3.2.46/net/xfrm/xfrm_input.c 2013-07-26 19:25:04.000000000 +0000 +@@ -102,6 +102,19 @@ } EXPORT_SYMBOL(xfrm_prepare_input); @@ -43,7 +47,7 @@ int xfrm_input(struct sk_buff *skb, int nexthdr, __be32 spi, int encap_type) { struct net *net = dev_net(skb->dev); -@@ -212,7 +225,7 @@ resume: +@@ -212,7 +225,7 @@ /* only the first xfrm gets the encap type */ encap_type = 0; @@ -52,9 +56,11 @@ XFRM_INC_STATS(net, LINUX_MIB_XFRMINSTATESEQERROR); goto drop_unlock; } ---- a/net/xfrm/xfrm_replay.c -+++ b/net/xfrm/xfrm_replay.c -@@ -420,7 +420,7 @@ err: +Index: linux-3.2.46/net/xfrm/xfrm_replay.c +=================================================================== +--- linux-3.2.46.orig/net/xfrm/xfrm_replay.c 2013-07-26 18:54:04.000000000 +0000 ++++ linux-3.2.46/net/xfrm/xfrm_replay.c 2013-07-26 19:25:04.000000000 +0000 +@@ -420,7 +420,7 @@ return -EINVAL; } @@ -63,7 +69,7 @@ struct sk_buff *skb, __be32 net_seq) { if (unlikely(XFRM_SKB_CB(skb)->seq.input.hi != -@@ -491,7 +491,6 @@ static void xfrm_replay_advance_esn(stru +@@ -491,7 +491,6 @@ static struct xfrm_replay xfrm_replay_legacy = { .advance = xfrm_replay_advance, .check = xfrm_replay_check, @@ -71,7 +77,7 @@ .notify = xfrm_replay_notify, .overflow = xfrm_replay_overflow, }; -@@ -499,15 +498,13 @@ static struct xfrm_replay xfrm_replay_le +@@ -499,15 +498,13 @@ static struct xfrm_replay xfrm_replay_bmp = { .advance = xfrm_replay_advance_bmp, .check = xfrm_replay_check_bmp, diff -Nru linux-3.2.46/debian/patches/features/all/alx/alx-add-new-QCA-ethernet-driver-which-supercedes-atl.patch linux-3.2.46/debian/patches/features/all/alx/alx-add-new-QCA-ethernet-driver-which-supercedes-atl.patch --- linux-3.2.46/debian/patches/features/all/alx/alx-add-new-QCA-ethernet-driver-which-supercedes-atl.patch 2013-02-24 03:52:32.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/alx/alx-add-new-QCA-ethernet-driver-which-supercedes-atl.patch 2013-07-26 19:26:12.000000000 +0000 @@ -78,9 +78,11 @@ create mode 100644 drivers/net/ethernet/atheros/alx/alx_main.c create mode 100644 drivers/net/ethernet/atheros/alx/alx_sw.h ---- a/MAINTAINERS -+++ b/MAINTAINERS -@@ -1317,6 +1317,17 @@ W: http://atl1.sourceforge.net +Index: linux-3.2.46/MAINTAINERS +=================================================================== +--- linux-3.2.46.orig/MAINTAINERS 2013-07-26 18:53:38.000000000 +0000 ++++ linux-3.2.46/MAINTAINERS 2013-07-26 19:26:10.000000000 +0000 +@@ -1321,6 +1321,17 @@ S: Maintained F: drivers/net/ethernet/atheros/ @@ -98,9 +100,11 @@ ATM M: Chas Williams L: linux-atm-general@lists.sourceforge.net (moderated for non-subscribers) ---- a/drivers/net/ethernet/atheros/Kconfig -+++ b/drivers/net/ethernet/atheros/Kconfig -@@ -56,15 +56,55 @@ config ATL1E +Index: linux-3.2.46/drivers/net/ethernet/atheros/Kconfig +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/atheros/Kconfig 2013-07-26 18:53:38.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/atheros/Kconfig 2013-07-26 19:26:10.000000000 +0000 +@@ -56,15 +56,55 @@ will be called atl1e. config ATL1C @@ -157,21 +161,27 @@ + will be called alx. + endif # NET_VENDOR_ATHEROS ---- a/drivers/net/ethernet/atheros/Makefile -+++ b/drivers/net/ethernet/atheros/Makefile -@@ -6,3 +6,4 @@ obj-$(CONFIG_ATL1) += atlx/ +Index: linux-3.2.46/drivers/net/ethernet/atheros/Makefile +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/atheros/Makefile 2013-07-26 18:53:38.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/atheros/Makefile 2013-07-26 19:26:10.000000000 +0000 +@@ -6,3 +6,4 @@ obj-$(CONFIG_ATL2) += atlx/ obj-$(CONFIG_ATL1E) += atl1e/ obj-$(CONFIG_ATL1C) += atl1c/ +obj-$(CONFIG_ALX) += alx/ ---- /dev/null -+++ b/drivers/net/ethernet/atheros/alx/Makefile +Index: linux-3.2.46/drivers/net/ethernet/atheros/alx/Makefile +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/atheros/alx/Makefile 2013-07-26 19:26:10.000000000 +0000 @@ -0,0 +1,3 @@ +obj-$(CONFIG_ALX) += alx.o +alx-objs := alx_main.o alx_ethtool.o alc_cb.o alc_hw.o alf_cb.o alf_hw.o +ccflags-y += -D__CHECK_ENDIAN__ ---- /dev/null -+++ b/drivers/net/ethernet/atheros/alx/alc_cb.c +Index: linux-3.2.46/drivers/net/ethernet/atheros/alx/alc_cb.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/atheros/alx/alc_cb.c 2013-07-26 19:26:10.000000000 +0000 @@ -0,0 +1,912 @@ +/* + * Copyright (c) 2012 Qualcomm Atheros, Inc. @@ -1085,8 +1095,10 @@ + return 0; +} + ---- /dev/null -+++ b/drivers/net/ethernet/atheros/alx/alc_hw.c +Index: linux-3.2.46/drivers/net/ethernet/atheros/alx/alc_hw.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/atheros/alx/alc_hw.c 2013-07-26 19:26:10.000000000 +0000 @@ -0,0 +1,1087 @@ +/* + * Copyright (c) 2012 Qualcomm Atheros, Inc. @@ -2175,8 +2187,10 @@ + return LX_DRV_PHY_UNKNOWN; +} + ---- /dev/null -+++ b/drivers/net/ethernet/atheros/alx/alc_hw.h +Index: linux-3.2.46/drivers/net/ethernet/atheros/alx/alc_hw.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/atheros/alx/alc_hw.h 2013-07-26 19:26:10.000000000 +0000 @@ -0,0 +1,1324 @@ +/* + * Copyright (c) 2012 Qualcomm Atheros, Inc. @@ -3502,8 +3516,10 @@ + +#endif/*L1C_HW_H_*/ + ---- /dev/null -+++ b/drivers/net/ethernet/atheros/alx/alf_cb.c +Index: linux-3.2.46/drivers/net/ethernet/atheros/alx/alf_cb.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/atheros/alx/alf_cb.c 2013-07-26 19:26:10.000000000 +0000 @@ -0,0 +1,1187 @@ +/* + * Copyright (c) 2012 Qualcomm Atheros, Inc. @@ -4692,8 +4708,10 @@ + return 0; +} + ---- /dev/null -+++ b/drivers/net/ethernet/atheros/alx/alf_hw.c +Index: linux-3.2.46/drivers/net/ethernet/atheros/alx/alf_hw.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/atheros/alx/alf_hw.c 2013-07-26 19:26:10.000000000 +0000 @@ -0,0 +1,918 @@ +/* + * Copyright (c) 2012 Qualcomm Atheros, Inc. @@ -5613,8 +5631,10 @@ + return LX_DRV_PHY_UNKNOWN; +} + ---- /dev/null -+++ b/drivers/net/ethernet/atheros/alx/alf_hw.h +Index: linux-3.2.46/drivers/net/ethernet/atheros/alx/alf_hw.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/atheros/alx/alf_hw.h 2013-07-26 19:26:10.000000000 +0000 @@ -0,0 +1,2098 @@ +/* + * Copyright (c) 2012 Qualcomm Atheros, Inc. @@ -7714,8 +7734,10 @@ + +#endif/*L1F_HW_H_*/ + ---- /dev/null -+++ b/drivers/net/ethernet/atheros/alx/alx.h +Index: linux-3.2.46/drivers/net/ethernet/atheros/alx/alx.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/atheros/alx/alx.h 2013-07-26 19:26:10.000000000 +0000 @@ -0,0 +1,670 @@ +/* + * Copyright (c) 2012 Qualcomm Atheros, Inc. @@ -8387,8 +8409,10 @@ +#endif + +#endif /* _ALX_H_ */ ---- /dev/null -+++ b/drivers/net/ethernet/atheros/alx/alx_ethtool.c +Index: linux-3.2.46/drivers/net/ethernet/atheros/alx/alx_ethtool.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/atheros/alx/alx_ethtool.c 2013-07-26 19:26:10.000000000 +0000 @@ -0,0 +1,519 @@ +/* + * Copyright (c) 2012 Qualcomm Atheros, Inc. @@ -8909,8 +8933,10 @@ +{ + SET_ETHTOOL_OPS(netdev, &alx_ethtool_ops); +} ---- /dev/null -+++ b/drivers/net/ethernet/atheros/alx/alx_hwcom.h +Index: linux-3.2.46/drivers/net/ethernet/atheros/alx/alx_hwcom.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/atheros/alx/alx_hwcom.h 2013-07-26 19:26:10.000000000 +0000 @@ -0,0 +1,187 @@ +/* + * Copyright (c) 2012 Qualcomm Atheros, Inc. @@ -9099,8 +9125,10 @@ + +#endif/*_ALX_HWCOMMON_H_*/ + ---- /dev/null -+++ b/drivers/net/ethernet/atheros/alx/alx_main.c +Index: linux-3.2.46/drivers/net/ethernet/atheros/alx/alx_main.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/atheros/alx/alx_main.c 2013-07-26 19:26:10.000000000 +0000 @@ -0,0 +1,3899 @@ +/* + * Copyright (c) 2012 Qualcomm Atheros, Inc. @@ -13001,8 +13029,10 @@ + + +module_exit(alx_exit_module); ---- /dev/null -+++ b/drivers/net/ethernet/atheros/alx/alx_sw.h +Index: linux-3.2.46/drivers/net/ethernet/atheros/alx/alx_sw.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/atheros/alx/alx_sw.h 2013-07-26 19:26:10.000000000 +0000 @@ -0,0 +1,493 @@ +/* + * Copyright (c) 2012 Qualcomm Atheros, Inc. diff -Nru linux-3.2.46/debian/patches/features/all/alx/mark-as-staging.patch linux-3.2.46/debian/patches/features/all/alx/mark-as-staging.patch --- linux-3.2.46/debian/patches/features/all/alx/mark-as-staging.patch 2013-02-24 03:52:32.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/alx/mark-as-staging.patch 2013-07-26 19:26:15.000000000 +0000 @@ -11,9 +11,11 @@ entry. --- ---- a/MAINTAINERS -+++ b/MAINTAINERS -@@ -1326,10 +1326,8 @@ M: Cloud Ren +Index: linux-3.2.46/MAINTAINERS +=================================================================== +--- linux-3.2.46.orig/MAINTAINERS 2013-07-26 19:26:10.000000000 +0000 ++++ linux-3.2.46/MAINTAINERS 2013-07-26 19:26:14.000000000 +0000 +@@ -1326,10 +1326,8 @@ M: Stevent Li M: Wu Ken M: David Liu @@ -24,9 +26,11 @@ F: drivers/net/ethernet/atheros/alx/ ATM ---- a/drivers/net/ethernet/atheros/alx/alx_main.c -+++ b/drivers/net/ethernet/atheros/alx/alx_main.c -@@ -41,6 +41,7 @@ MODULE_DEVICE_TABLE(pci, alx_pci_tbl); +Index: linux-3.2.46/drivers/net/ethernet/atheros/alx/alx_main.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/atheros/alx/alx_main.c 2013-07-26 19:26:13.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/atheros/alx/alx_main.c 2013-07-26 19:26:14.000000000 +0000 +@@ -41,6 +41,7 @@ MODULE_AUTHOR("Qualcomm Corporation, "); MODULE_DESCRIPTION("Qualcomm Atheros Gigabit Ethernet Driver"); MODULE_LICENSE("Dual BSD/GPL"); diff -Nru linux-3.2.46/debian/patches/features/all/alx/remove-atl1c-devices-from-alx.patch linux-3.2.46/debian/patches/features/all/alx/remove-atl1c-devices-from-alx.patch --- linux-3.2.46/debian/patches/features/all/alx/remove-atl1c-devices-from-alx.patch 2013-02-24 03:52:32.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/alx/remove-atl1c-devices-from-alx.patch 2013-07-26 19:26:14.000000000 +0000 @@ -16,9 +16,11 @@ I've also changed the Kconfig help text to reflect this. --- ---- a/drivers/net/ethernet/atheros/Kconfig -+++ b/drivers/net/ethernet/atheros/Kconfig -@@ -56,14 +56,13 @@ config ATL1E +Index: linux-3.2.46/drivers/net/ethernet/atheros/Kconfig +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/atheros/Kconfig 2013-07-26 19:26:10.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/atheros/Kconfig 2013-07-26 19:26:13.000000000 +0000 +@@ -56,14 +56,13 @@ will be called atl1e. config ATL1C @@ -34,7 +36,7 @@ This driver supports the following chipsets: 1969:1063 - AR8131 Gigabit Ethernet -@@ -84,18 +83,7 @@ config ALX +@@ -84,18 +83,7 @@ select MII ---help--- This driver supports the Atheros L1C/L1D/L1F gigabit ethernet @@ -54,9 +56,11 @@ 1969:1091 - AR8161 1969:1090 - AR8162 ---- a/drivers/net/ethernet/atheros/alx/alx_main.c -+++ b/drivers/net/ethernet/atheros/alx/alx_main.c -@@ -33,12 +33,6 @@ static const char alx_drv_description[] +Index: linux-3.2.46/drivers/net/ethernet/atheros/alx/alx_main.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/atheros/alx/alx_main.c 2013-07-26 19:26:10.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/atheros/alx/alx_main.c 2013-07-26 19:26:13.000000000 +0000 +@@ -33,12 +33,6 @@ #define ALX_ETHER_DEVICE(device_id) {\ PCI_DEVICE(ALX_VENDOR_ID, device_id)} static DEFINE_PCI_DEVICE_TABLE(alx_pci_tbl) = { diff -Nru linux-3.2.46/debian/patches/features/all/AppArmor-compatibility-patch-for-v5-interface.patch linux-3.2.46/debian/patches/features/all/AppArmor-compatibility-patch-for-v5-interface.patch --- linux-3.2.46/debian/patches/features/all/AppArmor-compatibility-patch-for-v5-interface.patch 2013-04-11 03:27:34.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/AppArmor-compatibility-patch-for-v5-interface.patch 2013-07-26 19:22:43.000000000 +0000 @@ -18,9 +18,11 @@ 5 files changed, 319 insertions(+), 2 deletions(-) create mode 100644 security/apparmor/apparmorfs-24.c ---- a/security/apparmor/Kconfig -+++ b/security/apparmor/Kconfig -@@ -29,3 +29,12 @@ config SECURITY_APPARMOR_BOOTPARAM_VALUE +Index: linux-3.2.46/security/apparmor/Kconfig +=================================================================== +--- linux-3.2.46.orig/security/apparmor/Kconfig 2013-07-26 18:54:51.000000000 +0000 ++++ linux-3.2.46/security/apparmor/Kconfig 2013-07-26 19:22:42.000000000 +0000 +@@ -29,3 +29,12 @@ boot. If you are unsure how to answer this question, answer 1. @@ -33,9 +35,11 @@ + This option enables compatability with AppArmor 2.4. It is + recommended if compatability with older versions of AppArmor + is desired. ---- a/security/apparmor/Makefile -+++ b/security/apparmor/Makefile -@@ -5,6 +5,7 @@ obj-$(CONFIG_SECURITY_APPARMOR) += apparmor.o +Index: linux-3.2.46/security/apparmor/Makefile +=================================================================== +--- linux-3.2.46.orig/security/apparmor/Makefile 2013-07-26 18:54:51.000000000 +0000 ++++ linux-3.2.46/security/apparmor/Makefile 2013-07-26 19:22:42.000000000 +0000 +@@ -5,6 +5,7 @@ apparmor-y := apparmorfs.o audit.o capability.o context.o ipc.o lib.o match.o \ path.o domain.o policy.o policy_unpack.o procattr.o lsm.o \ resource.o sid.o file.o @@ -43,8 +47,10 @@ clean-files := capability_names.h rlim_names.h ---- /dev/null -+++ b/security/apparmor/apparmorfs-24.c +Index: linux-3.2.46/security/apparmor/apparmorfs-24.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/security/apparmor/apparmorfs-24.c 2013-07-26 19:22:42.000000000 +0000 @@ -0,0 +1,287 @@ +/* + * AppArmor security module @@ -333,9 +339,11 @@ + .llseek = seq_lseek, + .release = profiles_release, +}; ---- a/security/apparmor/apparmorfs.c -+++ b/security/apparmor/apparmorfs.c -@@ -187,7 +187,11 @@ void __init aa_destroy_aafs(void) +Index: linux-3.2.46/security/apparmor/apparmorfs.c +=================================================================== +--- linux-3.2.46.orig/security/apparmor/apparmorfs.c 2013-07-26 18:54:51.000000000 +0000 ++++ linux-3.2.46/security/apparmor/apparmorfs.c 2013-07-26 19:22:42.000000000 +0000 +@@ -187,7 +187,11 @@ aafs_remove(".remove"); aafs_remove(".replace"); aafs_remove(".load"); @@ -348,7 +356,7 @@ securityfs_remove(aa_fs_dentry); aa_fs_dentry = NULL; } -@@ -218,7 +222,17 @@ static int __init aa_create_aafs(void) +@@ -218,7 +222,17 @@ aa_fs_dentry = NULL; goto error; } @@ -367,8 +375,10 @@ error = aafs_create(".load", 0640, &aa_fs_profile_load); if (error) goto error; ---- a/security/apparmor/include/apparmorfs.h -+++ b/security/apparmor/include/apparmorfs.h +Index: linux-3.2.46/security/apparmor/include/apparmorfs.h +=================================================================== +--- linux-3.2.46.orig/security/apparmor/include/apparmorfs.h 2013-07-26 18:54:51.000000000 +0000 ++++ linux-3.2.46/security/apparmor/include/apparmorfs.h 2013-07-26 19:22:42.000000000 +0000 @@ -17,4 +17,10 @@ extern void __init aa_destroy_aafs(void); diff -Nru linux-3.2.46/debian/patches/features/all/asix-Adds-support-for-Lenovo-10-100-USB-dongle.patch linux-3.2.46/debian/patches/features/all/asix-Adds-support-for-Lenovo-10-100-USB-dongle.patch --- linux-3.2.46/debian/patches/features/all/asix-Adds-support-for-Lenovo-10-100-USB-dongle.patch 2013-02-24 03:52:42.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/asix-Adds-support-for-Lenovo-10-100-USB-dongle.patch 2013-07-26 19:25:44.000000000 +0000 @@ -14,9 +14,11 @@ drivers/net/usb/asix.c | 4 ++++ 1 file changed, 4 insertions(+) ---- a/drivers/net/usb/asix.c -+++ b/drivers/net/usb/asix.c -@@ -1616,6 +1616,10 @@ static const struct usb_device_id produc +Index: linux-3.2.46/drivers/net/usb/asix.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/usb/asix.c 2013-07-26 18:53:46.000000000 +0000 ++++ linux-3.2.46/drivers/net/usb/asix.c 2013-07-26 19:25:43.000000000 +0000 +@@ -1616,6 +1616,10 @@ USB_DEVICE (0x04f1, 0x3008), .driver_info = (unsigned long) &ax8817x_info, }, { diff -Nru linux-3.2.46/debian/patches/features/all/aufs3/aufs3-add.patch linux-3.2.46/debian/patches/features/all/aufs3/aufs3-add.patch --- linux-3.2.46/debian/patches/features/all/aufs3/aufs3-add.patch 2013-03-10 01:50:40.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/aufs3/aufs3-add.patch 2013-07-26 19:17:02.000000000 +0000 @@ -1,5 +1,7 @@ ---- a/fs/aufs/Kconfig 1970-01-01 01:00:00.000000000 +0100 -+++ b/fs/aufs/Kconfig 2012-01-10 02:15:56.000000000 +0000 +Index: linux-3.2.46/fs/aufs/Kconfig +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/fs/aufs/Kconfig 2013-07-26 19:16:57.000000000 +0000 @@ -0,0 +1,203 @@ +config AUFS_FS + tristate "Aufs (Advanced multi layered unification filesystem) support" @@ -204,8 +206,10 @@ + Automatic configuration for internal use. + When aufs supports Magic SysRq, enabled automatically. +endif ---- a/fs/aufs/Makefile 1970-01-01 01:00:00.000000000 +0100 -+++ b/fs/aufs/Makefile 2012-08-01 03:41:52.000000000 +0100 +Index: linux-3.2.46/fs/aufs/Makefile +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/fs/aufs/Makefile 2013-07-26 19:16:57.000000000 +0000 @@ -0,0 +1,42 @@ + +include ${src}/magic.mk @@ -249,8 +253,10 @@ +aufs-$(CONFIG_AUFS_BR_HFSPLUS) += hfsplus.o +aufs-$(CONFIG_AUFS_DEBUG) += debug.o +aufs-$(CONFIG_AUFS_MAGIC_SYSRQ) += sysrq.o ---- a/fs/aufs/aufs.h 1970-01-01 01:00:00.000000000 +0100 -+++ b/fs/aufs/aufs.h 2013-02-13 14:16:11.494511808 +0000 +Index: linux-3.2.46/fs/aufs/aufs.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/fs/aufs/aufs.h 2013-07-26 19:16:57.000000000 +0000 @@ -0,0 +1,60 @@ +/* + * Copyright (C) 2005-2013 Junjiro R. Okajima @@ -312,8 +318,10 @@ + +#endif /* __KERNEL__ */ +#endif /* __AUFS_H__ */ ---- a/fs/aufs/branch.c 1970-01-01 01:00:00.000000000 +0100 -+++ b/fs/aufs/branch.c 2013-02-13 14:16:11.494511808 +0000 +Index: linux-3.2.46/fs/aufs/branch.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/fs/aufs/branch.c 2013-07-26 19:16:57.000000000 +0000 @@ -0,0 +1,1172 @@ +/* + * Copyright (C) 2005-2013 Junjiro R. Okajima @@ -1487,8 +1495,10 @@ + AuTraceErr(err); + return err; +} ---- a/fs/aufs/branch.h 1970-01-01 01:00:00.000000000 +0100 -+++ b/fs/aufs/branch.h 2013-02-13 14:16:11.494511808 +0000 +Index: linux-3.2.46/fs/aufs/branch.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/fs/aufs/branch.h 2013-07-26 19:16:57.000000000 +0000 @@ -0,0 +1,230 @@ +/* + * Copyright (C) 2005-2013 Junjiro R. Okajima @@ -1720,8 +1730,10 @@ + +#endif /* __KERNEL__ */ +#endif /* __AUFS_BRANCH_H__ */ ---- a/fs/aufs/conf.mk 1970-01-01 01:00:00.000000000 +0100 -+++ b/fs/aufs/conf.mk 2012-01-10 02:15:56.000000000 +0000 +Index: linux-3.2.46/fs/aufs/conf.mk +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/fs/aufs/conf.mk 2013-07-26 19:16:57.000000000 +0000 @@ -0,0 +1,38 @@ + +AuConfStr = CONFIG_AUFS_FS=${CONFIG_AUFS_FS} @@ -1761,8 +1773,10 @@ +${obj}/sysfs.o: ${AuConfName} + +-include ${srctree}/${src}/conf_priv.mk ---- a/fs/aufs/cpup.c 1970-01-01 01:00:00.000000000 +0100 -+++ b/fs/aufs/cpup.c 2013-02-13 14:16:11.494511808 +0000 +Index: linux-3.2.46/fs/aufs/cpup.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/fs/aufs/cpup.c 2013-07-26 19:16:57.000000000 +0000 @@ -0,0 +1,1079 @@ +/* + * Copyright (C) 2005-2013 Junjiro R. Okajima @@ -2843,8 +2857,10 @@ + dput(parent); + return err; +} ---- a/fs/aufs/cpup.h 1970-01-01 01:00:00.000000000 +0100 -+++ b/fs/aufs/cpup.h 2013-02-13 14:16:11.494511808 +0000 +Index: linux-3.2.46/fs/aufs/cpup.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/fs/aufs/cpup.h 2013-07-26 19:16:57.000000000 +0000 @@ -0,0 +1,81 @@ +/* + * Copyright (C) 2005-2013 Junjiro R. Okajima @@ -2927,8 +2943,10 @@ + +#endif /* __KERNEL__ */ +#endif /* __AUFS_CPUP_H__ */ ---- a/fs/aufs/dbgaufs.c 1970-01-01 01:00:00.000000000 +0100 -+++ b/fs/aufs/dbgaufs.c 2013-02-13 14:16:11.498511808 +0000 +Index: linux-3.2.46/fs/aufs/dbgaufs.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/fs/aufs/dbgaufs.c 2013-07-26 19:16:57.000000000 +0000 @@ -0,0 +1,334 @@ +/* + * Copyright (C) 2005-2013 Junjiro R. Okajima @@ -3264,8 +3282,10 @@ + err = 0; + return err; +} ---- a/fs/aufs/dbgaufs.h 1970-01-01 01:00:00.000000000 +0100 -+++ b/fs/aufs/dbgaufs.h 2013-02-13 14:16:11.498511808 +0000 +Index: linux-3.2.46/fs/aufs/dbgaufs.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/fs/aufs/dbgaufs.h 2013-07-26 19:16:57.000000000 +0000 @@ -0,0 +1,49 @@ +/* + * Copyright (C) 2005-2013 Junjiro R. Okajima @@ -3316,8 +3336,10 @@ + +#endif /* __KERNEL__ */ +#endif /* __DBGAUFS_H__ */ ---- a/fs/aufs/dcsub.c 1970-01-01 01:00:00.000000000 +0100 -+++ b/fs/aufs/dcsub.c 2013-02-13 14:16:11.498511808 +0000 +Index: linux-3.2.46/fs/aufs/dcsub.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/fs/aufs/dcsub.c 2013-07-26 19:16:57.000000000 +0000 @@ -0,0 +1,243 @@ +/* + * Copyright (C) 2005-2013 Junjiro R. Okajima @@ -3562,8 +3584,10 @@ + + return path_is_under(path + 0, path + 1); +} ---- a/fs/aufs/dcsub.h 1970-01-01 01:00:00.000000000 +0100 -+++ b/fs/aufs/dcsub.h 2013-02-13 14:16:11.498511808 +0000 +Index: linux-3.2.46/fs/aufs/dcsub.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/fs/aufs/dcsub.h 2013-07-26 19:16:57.000000000 +0000 @@ -0,0 +1,94 @@ +/* + * Copyright (C) 2005-2013 Junjiro R. Okajima @@ -3659,8 +3683,10 @@ + +#endif /* __KERNEL__ */ +#endif /* __AUFS_DCSUB_H__ */ ---- a/fs/aufs/debug.c 1970-01-01 01:00:00.000000000 +0100 -+++ b/fs/aufs/debug.c 2013-02-13 14:16:11.498511808 +0000 +Index: linux-3.2.46/fs/aufs/debug.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/fs/aufs/debug.c 2013-07-26 19:16:57.000000000 +0000 @@ -0,0 +1,489 @@ +/* + * Copyright (C) 2005-2013 Junjiro R. Okajima @@ -4151,8 +4177,10 @@ + + return 0; +} ---- a/fs/aufs/debug.h 1970-01-01 01:00:00.000000000 +0100 -+++ b/fs/aufs/debug.h 2013-02-13 14:16:11.498511808 +0000 +Index: linux-3.2.46/fs/aufs/debug.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/fs/aufs/debug.h 2013-07-26 19:16:57.000000000 +0000 @@ -0,0 +1,243 @@ +/* + * Copyright (C) 2005-2013 Junjiro R. Okajima @@ -4397,8 +4425,10 @@ + +#endif /* __KERNEL__ */ +#endif /* __AUFS_DEBUG_H__ */ ---- a/fs/aufs/dentry.c 1970-01-01 01:00:00.000000000 +0100 -+++ b/fs/aufs/dentry.c 2013-02-13 14:16:11.498511808 +0000 +Index: linux-3.2.46/fs/aufs/dentry.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/fs/aufs/dentry.c 2013-07-26 19:16:57.000000000 +0000 @@ -0,0 +1,1140 @@ +/* + * Copyright (C) 2005-2013 Junjiro R. Okajima @@ -5540,8 +5570,10 @@ + .d_revalidate = aufs_d_revalidate, + .d_release = aufs_d_release +}; ---- a/fs/aufs/dentry.h 1970-01-01 01:00:00.000000000 +0100 -+++ b/fs/aufs/dentry.h 2013-02-13 14:16:11.498511808 +0000 +Index: linux-3.2.46/fs/aufs/dentry.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/fs/aufs/dentry.h 2013-07-26 19:16:57.000000000 +0000 @@ -0,0 +1,237 @@ +/* + * Copyright (C) 2005-2013 Junjiro R. Okajima @@ -5780,8 +5812,10 @@ + +#endif /* __KERNEL__ */ +#endif /* __AUFS_DENTRY_H__ */ ---- a/fs/aufs/dinfo.c 1970-01-01 01:00:00.000000000 +0100 -+++ b/fs/aufs/dinfo.c 2013-02-13 14:16:11.498511808 +0000 +Index: linux-3.2.46/fs/aufs/dinfo.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/fs/aufs/dinfo.c 2013-07-26 19:16:57.000000000 +0000 @@ -0,0 +1,543 @@ +/* + * Copyright (C) 2005-2013 Junjiro R. Okajima @@ -6326,8 +6360,10 @@ + return bindex; + return -1; +} ---- a/fs/aufs/dir.c 1970-01-01 01:00:00.000000000 +0100 -+++ b/fs/aufs/dir.c 2013-02-13 14:16:11.498511808 +0000 +Index: linux-3.2.46/fs/aufs/dir.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/fs/aufs/dir.c 2013-07-26 19:16:57.000000000 +0000 @@ -0,0 +1,634 @@ +/* + * Copyright (C) 2005-2013 Junjiro R. Okajima @@ -6963,8 +6999,10 @@ + .flush = aufs_flush_dir, + .fsync = aufs_fsync_dir +}; ---- a/fs/aufs/dir.h 1970-01-01 01:00:00.000000000 +0100 -+++ b/fs/aufs/dir.h 2013-02-13 14:16:11.498511808 +0000 +Index: linux-3.2.46/fs/aufs/dir.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/fs/aufs/dir.h 2013-07-26 19:16:57.000000000 +0000 @@ -0,0 +1,137 @@ +/* + * Copyright (C) 2005-2013 Junjiro R. Okajima @@ -7103,8 +7141,10 @@ + +#endif /* __KERNEL__ */ +#endif /* __AUFS_DIR_H__ */ ---- a/fs/aufs/dynop.c 1970-01-01 01:00:00.000000000 +0100 -+++ b/fs/aufs/dynop.c 2013-02-13 14:16:11.498511808 +0000 +Index: linux-3.2.46/fs/aufs/dynop.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/fs/aufs/dynop.c 2013-07-26 19:16:57.000000000 +0000 @@ -0,0 +1,377 @@ +/* + * Copyright (C) 2010-2013 Junjiro R. Okajima @@ -7483,8 +7523,10 @@ + for (i = 0; i < AuDyLast; i++) + WARN_ON(!list_empty(&dynop[i].head)); +} ---- a/fs/aufs/dynop.h 1970-01-01 01:00:00.000000000 +0100 -+++ b/fs/aufs/dynop.h 2013-02-13 14:16:11.498511808 +0000 +Index: linux-3.2.46/fs/aufs/dynop.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/fs/aufs/dynop.h 2013-07-26 19:16:57.000000000 +0000 @@ -0,0 +1,76 @@ +/* + * Copyright (C) 2010-2013 Junjiro R. Okajima @@ -7562,8 +7604,10 @@ + +#endif /* __KERNEL__ */ +#endif /* __AUFS_DYNOP_H__ */ ---- a/fs/aufs/export.c 1970-01-01 01:00:00.000000000 +0100 -+++ b/fs/aufs/export.c 2013-02-13 14:16:11.498511808 +0000 +Index: linux-3.2.46/fs/aufs/export.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/fs/aufs/export.c 2013-07-26 19:16:57.000000000 +0000 @@ -0,0 +1,805 @@ +/* + * Copyright (C) 2005-2013 Junjiro R. Okajima @@ -8370,8 +8414,10 @@ + BUILD_BUG_ON(sizeof(u) != sizeof(int)); + atomic_set(&sbinfo->si_xigen_next, u); +} ---- a/fs/aufs/f_op.c 1970-01-01 01:00:00.000000000 +0100 -+++ b/fs/aufs/f_op.c 2013-02-13 14:16:11.498511808 +0000 +Index: linux-3.2.46/fs/aufs/f_op.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/fs/aufs/f_op.c 2013-07-26 19:16:57.000000000 +0000 @@ -0,0 +1,729 @@ +/* + * Copyright (C) 2005-2013 Junjiro R. Okajima @@ -9102,8 +9148,10 @@ + .aio_splice_read = aufs_aio_splice_read +#endif +}; ---- a/fs/aufs/f_op_sp.c 1970-01-01 01:00:00.000000000 +0100 -+++ b/fs/aufs/f_op_sp.c 2013-02-13 14:16:11.498511808 +0000 +Index: linux-3.2.46/fs/aufs/f_op_sp.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/fs/aufs/f_op_sp.c 2013-07-26 19:16:57.000000000 +0000 @@ -0,0 +1,298 @@ +/* + * Copyright (C) 2005-2013 Junjiro R. Okajima @@ -9403,8 +9451,10 @@ + + return ret; +} ---- a/fs/aufs/file.c 1970-01-01 01:00:00.000000000 +0100 -+++ b/fs/aufs/file.c 2013-02-13 14:16:11.498511808 +0000 +Index: linux-3.2.46/fs/aufs/file.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/fs/aufs/file.c 2013-07-26 19:16:57.000000000 +0000 @@ -0,0 +1,673 @@ +/* + * Copyright (C) 2005-2013 Junjiro R. Okajima @@ -10079,8 +10129,10 @@ + .error_remove_page = aufs_error_remove_page +#endif /* CONFIG_AUFS_DEBUG */ +}; ---- a/fs/aufs/file.h 1970-01-01 01:00:00.000000000 +0100 -+++ b/fs/aufs/file.h 2013-02-13 14:16:11.498511808 +0000 +Index: linux-3.2.46/fs/aufs/file.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/fs/aufs/file.h 2013-07-26 19:16:57.000000000 +0000 @@ -0,0 +1,298 @@ +/* + * Copyright (C) 2005-2013 Junjiro R. Okajima @@ -10380,8 +10432,10 @@ + +#endif /* __KERNEL__ */ +#endif /* __AUFS_FILE_H__ */ ---- a/fs/aufs/finfo.c 1970-01-01 01:00:00.000000000 +0100 -+++ b/fs/aufs/finfo.c 2013-02-13 14:16:11.498511808 +0000 +Index: linux-3.2.46/fs/aufs/finfo.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/fs/aufs/finfo.c 2013-07-26 19:16:57.000000000 +0000 @@ -0,0 +1,157 @@ +/* + * Copyright (C) 2005-2013 Junjiro R. Okajima @@ -10540,8 +10594,10 @@ +out: + return err; +} ---- a/fs/aufs/fstype.h 1970-01-01 01:00:00.000000000 +0100 -+++ b/fs/aufs/fstype.h 2013-02-13 14:16:11.498511808 +0000 +Index: linux-3.2.46/fs/aufs/fstype.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/fs/aufs/fstype.h 2013-07-26 19:16:57.000000000 +0000 @@ -0,0 +1,496 @@ +/* + * Copyright (C) 2005-2013 Junjiro R. Okajima @@ -11039,8 +11095,10 @@ + +#endif /* __KERNEL__ */ +#endif /* __AUFS_FSTYPE_H__ */ ---- a/fs/aufs/hfsnotify.c 1970-01-01 01:00:00.000000000 +0100 -+++ b/fs/aufs/hfsnotify.c 2013-02-13 14:16:11.498511808 +0000 +Index: linux-3.2.46/fs/aufs/hfsnotify.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/fs/aufs/hfsnotify.c 2013-07-26 19:16:57.000000000 +0000 @@ -0,0 +1,260 @@ +/* + * Copyright (C) 2005-2013 Junjiro R. Okajima @@ -11302,8 +11360,10 @@ + .fin_br = au_hfsn_fin_br, + .init_br = au_hfsn_init_br +}; ---- a/fs/aufs/hfsplus.c 1970-01-01 01:00:00.000000000 +0100 -+++ b/fs/aufs/hfsplus.c 2013-02-13 14:16:11.498511808 +0000 +Index: linux-3.2.46/fs/aufs/hfsplus.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/fs/aufs/hfsplus.c 2013-07-26 19:16:57.000000000 +0000 @@ -0,0 +1,57 @@ +/* + * Copyright (C) 2010-2013 Junjiro R. Okajima @@ -11362,8 +11422,10 @@ + au_sbr_put(dentry->d_sb, bindex); + } +} ---- a/fs/aufs/hnotify.c 1970-01-01 01:00:00.000000000 +0100 -+++ b/fs/aufs/hnotify.c 2013-02-13 14:16:11.498511808 +0000 +Index: linux-3.2.46/fs/aufs/hnotify.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/fs/aufs/hnotify.c 2013-07-26 19:16:57.000000000 +0000 @@ -0,0 +1,712 @@ +/* + * Copyright (C) 2005-2013 Junjiro R. Okajima @@ -12077,8 +12139,10 @@ + if (au_cachep[AuCache_HNOTIFY]) + au_hn_destroy_cache(); +} ---- a/fs/aufs/i_op.c 1970-01-01 01:00:00.000000000 +0100 -+++ b/fs/aufs/i_op.c 2013-02-13 14:16:11.498511808 +0000 +Index: linux-3.2.46/fs/aufs/i_op.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/fs/aufs/i_op.c 2013-07-26 19:16:57.000000000 +0000 @@ -0,0 +1,1004 @@ +/* + * Copyright (C) 2005-2013 Junjiro R. Okajima @@ -13084,8 +13148,10 @@ + .getattr = aufs_getattr, + .truncate_range = aufs_truncate_range +}; ---- a/fs/aufs/i_op_add.c 1970-01-01 01:00:00.000000000 +0100 -+++ b/fs/aufs/i_op_add.c 2013-02-13 14:16:11.502511808 +0000 +Index: linux-3.2.46/fs/aufs/i_op_add.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/fs/aufs/i_op_add.c 2013-07-26 19:16:57.000000000 +0000 @@ -0,0 +1,711 @@ +/* + * Copyright (C) 2005-2013 Junjiro R. Okajima @@ -13798,8 +13864,10 @@ +out: + return err; +} ---- a/fs/aufs/i_op_del.c 1970-01-01 01:00:00.000000000 +0100 -+++ b/fs/aufs/i_op_del.c 2013-02-13 14:16:11.502511808 +0000 +Index: linux-3.2.46/fs/aufs/i_op_del.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/fs/aufs/i_op_del.c 2013-07-26 19:16:57.000000000 +0000 @@ -0,0 +1,478 @@ +/* + * Copyright (C) 2005-2013 Junjiro R. Okajima @@ -14279,8 +14347,10 @@ + AuTraceErr(err); + return err; +} ---- a/fs/aufs/i_op_ren.c 1970-01-01 01:00:00.000000000 +0100 -+++ b/fs/aufs/i_op_ren.c 2013-02-13 14:16:11.502511808 +0000 +Index: linux-3.2.46/fs/aufs/i_op_ren.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/fs/aufs/i_op_ren.c 2013-07-26 19:16:57.000000000 +0000 @@ -0,0 +1,1026 @@ +/* + * Copyright (C) 2005-2013 Junjiro R. Okajima @@ -15308,8 +15378,10 @@ + AuTraceErr(err); + return err; +} ---- a/fs/aufs/iinfo.c 1970-01-01 01:00:00.000000000 +0100 -+++ b/fs/aufs/iinfo.c 2013-02-13 14:16:11.502511808 +0000 +Index: linux-3.2.46/fs/aufs/iinfo.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/fs/aufs/iinfo.c 2013-07-26 19:16:57.000000000 +0000 @@ -0,0 +1,276 @@ +/* + * Copyright (C) 2005-2013 Junjiro R. Okajima @@ -15587,8 +15659,10 @@ + iinfo->ii_hinode = NULL; + AuRwDestroy(&iinfo->ii_rwsem); +} ---- a/fs/aufs/inode.c 1970-01-01 01:00:00.000000000 +0100 -+++ b/fs/aufs/inode.c 2013-02-13 14:16:11.502511808 +0000 +Index: linux-3.2.46/fs/aufs/inode.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/fs/aufs/inode.c 2013-07-26 19:16:57.000000000 +0000 @@ -0,0 +1,492 @@ +/* + * Copyright (C) 2005-2013 Junjiro R. Okajima @@ -16082,8 +16156,10 @@ + mask |= MAY_READ; /* force permission check */ + return au_test_h_perm(h_inode, mask); +} ---- a/fs/aufs/inode.h 1970-01-01 01:00:00.000000000 +0100 -+++ b/fs/aufs/inode.h 2013-02-13 14:16:11.502511808 +0000 +Index: linux-3.2.46/fs/aufs/inode.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/fs/aufs/inode.h 2013-07-26 19:16:57.000000000 +0000 @@ -0,0 +1,587 @@ +/* + * Copyright (C) 2005-2013 Junjiro R. Okajima @@ -16672,8 +16748,10 @@ + +#endif /* __KERNEL__ */ +#endif /* __AUFS_INODE_H__ */ ---- a/fs/aufs/ioctl.c 1970-01-01 01:00:00.000000000 +0100 -+++ b/fs/aufs/ioctl.c 2013-02-13 14:16:11.502511808 +0000 +Index: linux-3.2.46/fs/aufs/ioctl.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/fs/aufs/ioctl.c 2013-07-26 19:16:57.000000000 +0000 @@ -0,0 +1,196 @@ +/* + * Copyright (C) 2005-2013 Junjiro R. Okajima @@ -16871,8 +16949,10 @@ +} +#endif +#endif ---- a/fs/aufs/loop.c 1970-01-01 01:00:00.000000000 +0100 -+++ b/fs/aufs/loop.c 2013-02-13 14:16:11.502511808 +0000 +Index: linux-3.2.46/fs/aufs/loop.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/fs/aufs/loop.c 2013-07-26 19:16:57.000000000 +0000 @@ -0,0 +1,133 @@ +/* + * Copyright (C) 2005-2013 Junjiro R. Okajima @@ -17007,8 +17087,10 @@ +{ + kfree(au_warn_loopback_array); +} ---- a/fs/aufs/loop.h 1970-01-01 01:00:00.000000000 +0100 -+++ b/fs/aufs/loop.h 2013-02-13 14:16:11.502511808 +0000 +Index: linux-3.2.46/fs/aufs/loop.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/fs/aufs/loop.h 2013-07-26 19:16:57.000000000 +0000 @@ -0,0 +1,50 @@ +/* + * Copyright (C) 2005-2013 Junjiro R. Okajima @@ -17060,8 +17142,10 @@ + +#endif /* __KERNEL__ */ +#endif /* __AUFS_LOOP_H__ */ ---- a/fs/aufs/magic.mk 1970-01-01 01:00:00.000000000 +0100 -+++ b/fs/aufs/magic.mk 2012-01-10 02:15:56.000000000 +0000 +Index: linux-3.2.46/fs/aufs/magic.mk +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/fs/aufs/magic.mk 2013-07-26 19:16:57.000000000 +0000 @@ -0,0 +1,54 @@ + +# defined in ${srctree}/fs/fuse/inode.c @@ -17117,8 +17201,10 @@ +ifdef CONFIG_HFSPLUS_FS +ccflags-y += -DHFSPLUS_SUPER_MAGIC=0x482b +endif ---- a/fs/aufs/module.c 1970-01-01 01:00:00.000000000 +0100 -+++ b/fs/aufs/module.c 2013-02-13 14:16:11.502511808 +0000 +Index: linux-3.2.46/fs/aufs/module.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/fs/aufs/module.c 2013-07-26 19:16:57.000000000 +0000 @@ -0,0 +1,196 @@ +/* + * Copyright (C) 2005-2013 Junjiro R. Okajima @@ -17316,8 +17402,10 @@ + +module_init(aufs_init); +module_exit(aufs_exit); ---- a/fs/aufs/module.h 1970-01-01 01:00:00.000000000 +0100 -+++ b/fs/aufs/module.h 2013-02-13 14:16:11.502511808 +0000 +Index: linux-3.2.46/fs/aufs/module.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/fs/aufs/module.h 2013-07-26 19:16:57.000000000 +0000 @@ -0,0 +1,105 @@ +/* + * Copyright (C) 2005-2013 Junjiro R. Okajima @@ -17424,8 +17512,10 @@ + +#endif /* __KERNEL__ */ +#endif /* __AUFS_MODULE_H__ */ ---- a/fs/aufs/opts.c 1970-01-01 01:00:00.000000000 +0100 -+++ b/fs/aufs/opts.c 2013-02-13 14:16:11.502511808 +0000 +Index: linux-3.2.46/fs/aufs/opts.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/fs/aufs/opts.c 2013-07-26 19:16:57.000000000 +0000 @@ -0,0 +1,1677 @@ +/* + * Copyright (C) 2005-2013 Junjiro R. Okajima @@ -19104,8 +19194,10 @@ +{ + return au_mntflags(sb) & AuOptMask_UDBA; +} ---- a/fs/aufs/opts.h 1970-01-01 01:00:00.000000000 +0100 -+++ b/fs/aufs/opts.h 2013-02-13 14:16:11.502511808 +0000 +Index: linux-3.2.46/fs/aufs/opts.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/fs/aufs/opts.h 2013-07-26 19:16:57.000000000 +0000 @@ -0,0 +1,209 @@ +/* + * Copyright (C) 2005-2013 Junjiro R. Okajima @@ -19316,8 +19408,10 @@ + +#endif /* __KERNEL__ */ +#endif /* __AUFS_OPTS_H__ */ ---- a/fs/aufs/plink.c 1970-01-01 01:00:00.000000000 +0100 -+++ b/fs/aufs/plink.c 2013-02-13 14:16:11.502511808 +0000 +Index: linux-3.2.46/fs/aufs/plink.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/fs/aufs/plink.c 2013-07-26 19:16:57.000000000 +0000 @@ -0,0 +1,515 @@ +/* + * Copyright (C) 2005-2013 Junjiro R. Okajima @@ -19834,8 +19928,10 @@ + iput(inode); + } +} ---- a/fs/aufs/poll.c 1970-01-01 01:00:00.000000000 +0100 -+++ b/fs/aufs/poll.c 2013-02-13 14:16:11.502511808 +0000 +Index: linux-3.2.46/fs/aufs/poll.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/fs/aufs/poll.c 2013-07-26 19:16:57.000000000 +0000 @@ -0,0 +1,56 @@ +/* + * Copyright (C) 2005-2013 Junjiro R. Okajima @@ -19893,8 +19989,10 @@ + AuTraceErr((int)mask); + return mask; +} ---- a/fs/aufs/procfs.c 1970-01-01 01:00:00.000000000 +0100 -+++ b/fs/aufs/procfs.c 2013-02-13 14:16:11.502511808 +0000 +Index: linux-3.2.46/fs/aufs/procfs.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/fs/aufs/procfs.c 2013-07-26 19:16:57.000000000 +0000 @@ -0,0 +1,170 @@ +/* + * Copyright (C) 2010-2013 Junjiro R. Okajima @@ -20066,8 +20164,10 @@ +out: + return err; +} ---- a/fs/aufs/rdu.c 1970-01-01 01:00:00.000000000 +0100 -+++ b/fs/aufs/rdu.c 2013-02-13 14:16:11.502511808 +0000 +Index: linux-3.2.46/fs/aufs/rdu.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/fs/aufs/rdu.c 2013-07-26 19:16:57.000000000 +0000 @@ -0,0 +1,383 @@ +/* + * Copyright (C) 2005-2013 Junjiro R. Okajima @@ -20452,8 +20552,10 @@ + return err; +} +#endif ---- a/fs/aufs/rwsem.h 1970-01-01 01:00:00.000000000 +0100 -+++ b/fs/aufs/rwsem.h 2013-02-13 14:16:11.502511808 +0000 +Index: linux-3.2.46/fs/aufs/rwsem.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/fs/aufs/rwsem.h 2013-07-26 19:16:57.000000000 +0000 @@ -0,0 +1,188 @@ +/* + * Copyright (C) 2005-2013 Junjiro R. Okajima @@ -20643,8 +20745,10 @@ + +#endif /* __KERNEL__ */ +#endif /* __AUFS_RWSEM_H__ */ ---- a/fs/aufs/sbinfo.c 1970-01-01 01:00:00.000000000 +0100 -+++ b/fs/aufs/sbinfo.c 2013-02-13 14:16:11.502511808 +0000 +Index: linux-3.2.46/fs/aufs/sbinfo.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/fs/aufs/sbinfo.c 2013-07-26 19:16:57.000000000 +0000 @@ -0,0 +1,343 @@ +/* + * Copyright (C) 2005-2013 Junjiro R. Okajima @@ -20989,8 +21093,10 @@ + p = radix_tree_delete(&sbinfo->au_si_pid.tree, current->pid); + spin_unlock(&sbinfo->au_si_pid.tree_lock); +} ---- a/fs/aufs/spl.h 1970-01-01 01:00:00.000000000 +0100 -+++ b/fs/aufs/spl.h 2013-02-13 14:16:11.502511808 +0000 +Index: linux-3.2.46/fs/aufs/spl.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/fs/aufs/spl.h 2013-07-26 19:16:57.000000000 +0000 @@ -0,0 +1,62 @@ +/* + * Copyright (C) 2005-2013 Junjiro R. Okajima @@ -21054,8 +21160,10 @@ + +#endif /* __KERNEL__ */ +#endif /* __AUFS_SPL_H__ */ ---- a/fs/aufs/super.c 1970-01-01 01:00:00.000000000 +0100 -+++ b/fs/aufs/super.c 2013-02-13 14:16:11.502511808 +0000 +Index: linux-3.2.46/fs/aufs/super.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/fs/aufs/super.c 2013-07-26 19:16:57.000000000 +0000 @@ -0,0 +1,999 @@ +/* + * Copyright (C) 2005-2013 Junjiro R. Okajima @@ -22056,8 +22164,10 @@ + /* no need to __module_get() and module_put(). */ + .owner = THIS_MODULE, +}; ---- a/fs/aufs/super.h 1970-01-01 01:00:00.000000000 +0100 -+++ b/fs/aufs/super.h 2013-02-13 14:16:11.502511808 +0000 +Index: linux-3.2.46/fs/aufs/super.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/fs/aufs/super.h 2013-07-26 19:16:57.000000000 +0000 @@ -0,0 +1,546 @@ +/* + * Copyright (C) 2005-2013 Junjiro R. Okajima @@ -22605,8 +22715,10 @@ + +#endif /* __KERNEL__ */ +#endif /* __AUFS_SUPER_H__ */ ---- a/fs/aufs/sysaufs.c 1970-01-01 01:00:00.000000000 +0100 -+++ b/fs/aufs/sysaufs.c 2013-02-13 14:16:11.502511808 +0000 +Index: linux-3.2.46/fs/aufs/sysaufs.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/fs/aufs/sysaufs.c 2013-07-26 19:16:57.000000000 +0000 @@ -0,0 +1,105 @@ +/* + * Copyright (C) 2005-2013 Junjiro R. Okajima @@ -22713,8 +22825,10 @@ +out: + return err; +} ---- a/fs/aufs/sysaufs.h 1970-01-01 01:00:00.000000000 +0100 -+++ b/fs/aufs/sysaufs.h 2013-02-13 14:16:11.502511808 +0000 +Index: linux-3.2.46/fs/aufs/sysaufs.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/fs/aufs/sysaufs.h 2013-07-26 19:16:57.000000000 +0000 @@ -0,0 +1,104 @@ +/* + * Copyright (C) 2005-2013 Junjiro R. Okajima @@ -22820,8 +22934,10 @@ + +#endif /* __KERNEL__ */ +#endif /* __SYSAUFS_H__ */ ---- a/fs/aufs/sysfs.c 1970-01-01 01:00:00.000000000 +0100 -+++ b/fs/aufs/sysfs.c 2013-02-13 14:16:11.502511808 +0000 +Index: linux-3.2.46/fs/aufs/sysfs.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/fs/aufs/sysfs.c 2013-07-26 19:16:57.000000000 +0000 @@ -0,0 +1,257 @@ +/* + * Copyright (C) 2005-2013 Junjiro R. Okajima @@ -23080,8 +23196,10 @@ + br->br_name, err); + } +} ---- a/fs/aufs/sysrq.c 1970-01-01 01:00:00.000000000 +0100 -+++ b/fs/aufs/sysrq.c 2013-02-13 14:16:11.502511808 +0000 +Index: linux-3.2.46/fs/aufs/sysrq.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/fs/aufs/sysrq.c 2013-07-26 19:16:57.000000000 +0000 @@ -0,0 +1,148 @@ +/* + * Copyright (C) 2005-2013 Junjiro R. Okajima @@ -23231,8 +23349,10 @@ + if (unlikely(err)) + pr_err("err %d (ignored)\n", err); +} ---- a/fs/aufs/vdir.c 1970-01-01 01:00:00.000000000 +0100 -+++ b/fs/aufs/vdir.c 2013-02-13 14:16:11.506511808 +0000 +Index: linux-3.2.46/fs/aufs/vdir.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/fs/aufs/vdir.c 2013-07-26 19:16:57.000000000 +0000 @@ -0,0 +1,885 @@ +/* + * Copyright (C) 2005-2013 Junjiro R. Okajima @@ -24119,8 +24239,10 @@ + /* smp_mb(); */ + return 0; +} ---- a/fs/aufs/vfsub.c 1970-01-01 01:00:00.000000000 +0100 -+++ b/fs/aufs/vfsub.c 2013-02-13 14:16:11.506511808 +0000 +Index: linux-3.2.46/fs/aufs/vfsub.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/fs/aufs/vfsub.c 2013-07-26 19:16:57.000000000 +0000 @@ -0,0 +1,835 @@ +/* + * Copyright (C) 2005-2013 Junjiro R. Okajima @@ -24957,8 +25079,10 @@ + + return err; +} ---- a/fs/aufs/vfsub.h 1970-01-01 01:00:00.000000000 +0100 -+++ b/fs/aufs/vfsub.h 2013-02-13 14:16:11.506511808 +0000 +Index: linux-3.2.46/fs/aufs/vfsub.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/fs/aufs/vfsub.h 2013-07-26 19:16:57.000000000 +0000 @@ -0,0 +1,232 @@ +/* + * Copyright (C) 2005-2013 Junjiro R. Okajima @@ -25192,8 +25316,10 @@ + +#endif /* __KERNEL__ */ +#endif /* __AUFS_VFSUB_H__ */ ---- a/fs/aufs/wbr_policy.c 1970-01-01 01:00:00.000000000 +0100 -+++ b/fs/aufs/wbr_policy.c 2013-02-13 14:16:11.506511808 +0000 +Index: linux-3.2.46/fs/aufs/wbr_policy.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/fs/aufs/wbr_policy.c 2013-07-26 19:16:57.000000000 +0000 @@ -0,0 +1,700 @@ +/* + * Copyright (C) 2005-2013 Junjiro R. Okajima @@ -25895,8 +26021,10 @@ + .fin = au_wbr_create_fin_mfs + } +}; ---- a/fs/aufs/whout.c 1970-01-01 01:00:00.000000000 +0100 -+++ b/fs/aufs/whout.c 2013-02-13 14:16:11.506511808 +0000 +Index: linux-3.2.46/fs/aufs/whout.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/fs/aufs/whout.c 2013-07-26 19:16:57.000000000 +0000 @@ -0,0 +1,1049 @@ +/* + * Copyright (C) 2005-2013 Junjiro R. Okajima @@ -26947,8 +27075,10 @@ + au_whtmp_rmdir_free(args); + } +} ---- a/fs/aufs/whout.h 1970-01-01 01:00:00.000000000 +0100 -+++ b/fs/aufs/whout.h 2013-02-13 14:16:11.506511808 +0000 +Index: linux-3.2.46/fs/aufs/whout.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/fs/aufs/whout.h 2013-07-26 19:16:57.000000000 +0000 @@ -0,0 +1,88 @@ +/* + * Copyright (C) 2005-2013 Junjiro R. Okajima @@ -27038,8 +27168,10 @@ + +#endif /* __KERNEL__ */ +#endif /* __AUFS_WHOUT_H__ */ ---- a/fs/aufs/wkq.c 1970-01-01 01:00:00.000000000 +0100 -+++ b/fs/aufs/wkq.c 2013-02-13 14:16:11.506511808 +0000 +Index: linux-3.2.46/fs/aufs/wkq.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/fs/aufs/wkq.c 2013-07-26 19:16:57.000000000 +0000 @@ -0,0 +1,214 @@ +/* + * Copyright (C) 2005-2013 Junjiro R. Okajima @@ -27255,8 +27387,10 @@ + + return err; +} ---- a/fs/aufs/wkq.h 1970-01-01 01:00:00.000000000 +0100 -+++ b/fs/aufs/wkq.h 2013-02-13 14:16:11.506511808 +0000 +Index: linux-3.2.46/fs/aufs/wkq.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/fs/aufs/wkq.h 2013-07-26 19:16:57.000000000 +0000 @@ -0,0 +1,92 @@ +/* + * Copyright (C) 2005-2013 Junjiro R. Okajima @@ -27350,8 +27484,10 @@ + +#endif /* __KERNEL__ */ +#endif /* __AUFS_WKQ_H__ */ ---- a/fs/aufs/xino.c 1970-01-01 01:00:00.000000000 +0100 -+++ b/fs/aufs/xino.c 2013-02-13 14:16:11.506511808 +0000 +Index: linux-3.2.46/fs/aufs/xino.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/fs/aufs/xino.c 2013-07-26 19:16:57.000000000 +0000 @@ -0,0 +1,1265 @@ +/* + * Copyright (C) 2005-2013 Junjiro R. Okajima @@ -28618,8 +28754,10 @@ +out: + return err; +} ---- a/include/linux/aufs_type.h 1970-01-01 01:00:00.000000000 +0100 -+++ b/include/linux/aufs_type.h 2013-02-13 14:16:11.506511808 +0000 +Index: linux-3.2.46/include/linux/aufs_type.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/include/linux/aufs_type.h 2013-07-26 19:16:57.000000000 +0000 @@ -0,0 +1,233 @@ +/* + * Copyright (C) 2005-2013 Junjiro R. Okajima diff -Nru linux-3.2.46/debian/patches/features/all/aufs3/aufs3-base.patch linux-3.2.46/debian/patches/features/all/aufs3/aufs3-base.patch --- linux-3.2.46/debian/patches/features/all/aufs3/aufs3-base.patch 2013-03-10 01:49:17.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/aufs3/aufs3-base.patch 2013-07-26 19:16:53.000000000 +0000 @@ -1,10 +1,10 @@ aufs3.2 base patch -diff --git a/fs/namei.c b/fs/namei.c -index 5008f01..4cc94cf 100644 ---- a/fs/namei.c -+++ b/fs/namei.c -@@ -1753,7 +1753,7 @@ static struct dentry *__lookup_hash(struct qstr *name, +Index: linux-3.2.46/fs/namei.c +=================================================================== +--- linux-3.2.46.orig/fs/namei.c 2013-07-26 18:56:42.000000000 +0000 ++++ linux-3.2.46/fs/namei.c 2013-07-26 19:16:51.000000000 +0000 +@@ -1755,7 +1755,7 @@ * needs parent already locked. Doesn't follow mounts. * SMP-safe. */ @@ -13,11 +13,11 @@ { return __lookup_hash(&nd->last, nd->path.dentry, nd); } -diff --git a/fs/splice.c b/fs/splice.c -index fa2defa..e3569b0 100644 ---- a/fs/splice.c -+++ b/fs/splice.c -@@ -1085,8 +1085,8 @@ EXPORT_SYMBOL(generic_splice_sendpage); +Index: linux-3.2.46/fs/splice.c +=================================================================== +--- linux-3.2.46.orig/fs/splice.c 2013-07-26 18:56:42.000000000 +0000 ++++ linux-3.2.46/fs/splice.c 2013-07-26 19:16:51.000000000 +0000 +@@ -1094,8 +1094,8 @@ /* * Attempt to initiate a splice from pipe to file. */ @@ -28,7 +28,7 @@ { ssize_t (*splice_write)(struct pipe_inode_info *, struct file *, loff_t *, size_t, unsigned int); -@@ -1113,9 +1113,9 @@ static long do_splice_from(struct pipe_inode_info *pipe, struct file *out, +@@ -1122,9 +1122,9 @@ /* * Attempt to initiate a splice from a file to a pipe. */ @@ -41,11 +41,11 @@ { ssize_t (*splice_read)(struct file *, loff_t *, struct pipe_inode_info *, size_t, unsigned int); -diff --git a/include/linux/namei.h b/include/linux/namei.h -index ffc0213..ef35a31 100644 ---- a/include/linux/namei.h -+++ b/include/linux/namei.h -@@ -85,6 +85,7 @@ extern int vfs_path_lookup(struct dentry *, struct vfsmount *, +Index: linux-3.2.46/include/linux/namei.h +=================================================================== +--- linux-3.2.46.orig/include/linux/namei.h 2013-07-26 18:56:42.000000000 +0000 ++++ linux-3.2.46/include/linux/namei.h 2013-07-26 19:16:52.000000000 +0000 +@@ -85,6 +85,7 @@ extern struct file *lookup_instantiate_filp(struct nameidata *nd, struct dentry *dentry, int (*open)(struct inode *, struct file *)); @@ -53,11 +53,11 @@ extern struct dentry *lookup_one_len(const char *, struct dentry *, int); extern int follow_down_one(struct path *); -diff --git a/include/linux/splice.h b/include/linux/splice.h -index 26e5b61..3ffef2f 100644 ---- a/include/linux/splice.h -+++ b/include/linux/splice.h -@@ -91,4 +91,10 @@ extern void splice_shrink_spd(struct pipe_inode_info *, +Index: linux-3.2.46/include/linux/splice.h +=================================================================== +--- linux-3.2.46.orig/include/linux/splice.h 2013-07-26 18:56:42.000000000 +0000 ++++ linux-3.2.46/include/linux/splice.h 2013-07-26 19:16:52.000000000 +0000 +@@ -91,4 +91,10 @@ extern void spd_release_page(struct splice_pipe_desc *, unsigned int); extern const struct pipe_buf_operations page_cache_pipe_buf_ops; diff -Nru linux-3.2.46/debian/patches/features/all/aufs3/aufs3-fix-export-__devcgroup_inode_permission.patch linux-3.2.46/debian/patches/features/all/aufs3/aufs3-fix-export-__devcgroup_inode_permission.patch --- linux-3.2.46/debian/patches/features/all/aufs3/aufs3-fix-export-__devcgroup_inode_permission.patch 2013-02-24 03:52:40.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/aufs3/aufs3-fix-export-__devcgroup_inode_permission.patch 2013-07-26 19:17:05.000000000 +0000 @@ -1,8 +1,8 @@ -diff --git a/security/device_cgroup.c b/security/device_cgroup.c -index 4450fbe..7147fa7 100644 ---- a/security/device_cgroup.c -+++ b/security/device_cgroup.c -@@ -13,6 +13,7 @@ +Index: linux-3.2.46/security/device_cgroup.c +=================================================================== +--- linux-3.2.46.orig/security/device_cgroup.c 2013-07-26 19:16:53.000000000 +0000 ++++ linux-3.2.46/security/device_cgroup.c 2013-07-26 19:17:04.000000000 +0000 +@@ -14,6 +14,7 @@ #include #include #include diff -Nru linux-3.2.46/debian/patches/features/all/aufs3/aufs3-kbuild.patch linux-3.2.46/debian/patches/features/all/aufs3/aufs3-kbuild.patch --- linux-3.2.46/debian/patches/features/all/aufs3/aufs3-kbuild.patch 2013-03-10 01:49:17.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/aufs3/aufs3-kbuild.patch 2013-07-26 19:16:56.000000000 +0000 @@ -1,10 +1,10 @@ aufs3.2 kbuild patch -diff --git a/fs/Kconfig b/fs/Kconfig -index 5f4c45d..357a8a6 100644 ---- a/fs/Kconfig -+++ b/fs/Kconfig -@@ -215,6 +215,7 @@ source "fs/pstore/Kconfig" +Index: linux-3.2.46/fs/Kconfig +=================================================================== +--- linux-3.2.46.orig/fs/Kconfig 2013-07-26 18:56:41.000000000 +0000 ++++ linux-3.2.46/fs/Kconfig 2013-07-26 19:16:55.000000000 +0000 +@@ -215,6 +215,7 @@ source "fs/sysv/Kconfig" source "fs/ufs/Kconfig" source "fs/exofs/Kconfig" @@ -12,20 +12,20 @@ endif # MISC_FILESYSTEMS -diff --git a/fs/Makefile b/fs/Makefile -index d2c3353..680ad8a 100644 ---- a/fs/Makefile -+++ b/fs/Makefile -@@ -123,3 +123,4 @@ obj-$(CONFIG_GFS2_FS) += gfs2/ +Index: linux-3.2.46/fs/Makefile +=================================================================== +--- linux-3.2.46.orig/fs/Makefile 2013-07-26 18:56:41.000000000 +0000 ++++ linux-3.2.46/fs/Makefile 2013-07-26 19:16:55.000000000 +0000 +@@ -123,3 +123,4 @@ obj-y += exofs/ # Multiple modules obj-$(CONFIG_CEPH_FS) += ceph/ obj-$(CONFIG_PSTORE) += pstore/ +obj-$(CONFIG_AUFS_FS) += aufs/ -diff --git a/include/linux/Kbuild b/include/linux/Kbuild -index 619b565..29f386b 100644 ---- a/include/linux/Kbuild -+++ b/include/linux/Kbuild -@@ -65,6 +65,7 @@ header-y += atmppp.h +Index: linux-3.2.46/include/linux/Kbuild +=================================================================== +--- linux-3.2.46.orig/include/linux/Kbuild 2013-07-26 18:56:41.000000000 +0000 ++++ linux-3.2.46/include/linux/Kbuild 2013-07-26 19:16:55.000000000 +0000 +@@ -65,6 +65,7 @@ header-y += atmsap.h header-y += atmsvc.h header-y += audit.h diff -Nru linux-3.2.46/debian/patches/features/all/aufs3/aufs3-standalone.patch linux-3.2.46/debian/patches/features/all/aufs3/aufs3-standalone.patch --- linux-3.2.46/debian/patches/features/all/aufs3/aufs3-standalone.patch 2013-03-10 01:49:17.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/aufs3/aufs3-standalone.patch 2013-07-26 19:16:55.000000000 +0000 @@ -1,10 +1,10 @@ aufs3.2 standalone patch -diff --git a/fs/file_table.c b/fs/file_table.c -index c322794..2aad244 100644 ---- a/fs/file_table.c -+++ b/fs/file_table.c -@@ -443,6 +443,8 @@ void file_sb_list_del(struct file *file) +Index: linux-3.2.46/fs/file_table.c +=================================================================== +--- linux-3.2.46.orig/fs/file_table.c 2013-07-26 18:56:42.000000000 +0000 ++++ linux-3.2.46/fs/file_table.c 2013-07-26 19:16:53.000000000 +0000 +@@ -443,6 +443,8 @@ } } @@ -13,11 +13,11 @@ #ifdef CONFIG_SMP /* -diff --git a/fs/inode.c b/fs/inode.c -index ee4e66b..728042b 100644 ---- a/fs/inode.c -+++ b/fs/inode.c -@@ -65,6 +65,7 @@ static struct hlist_head *inode_hashtable __read_mostly; +Index: linux-3.2.46/fs/inode.c +=================================================================== +--- linux-3.2.46.orig/fs/inode.c 2013-07-26 18:56:42.000000000 +0000 ++++ linux-3.2.46/fs/inode.c 2013-07-26 19:16:53.000000000 +0000 +@@ -65,6 +65,7 @@ static __cacheline_aligned_in_smp DEFINE_SPINLOCK(inode_hash_lock); __cacheline_aligned_in_smp DEFINE_SPINLOCK(inode_sb_list_lock); @@ -25,11 +25,11 @@ /* * Empty aops. Can be used for the cases where the user does not -diff --git a/fs/namei.c b/fs/namei.c -index 4cc94cf..af19e30 100644 ---- a/fs/namei.c -+++ b/fs/namei.c -@@ -1757,6 +1757,7 @@ struct dentry *lookup_hash(struct nameidata *nd) +Index: linux-3.2.46/fs/namei.c +=================================================================== +--- linux-3.2.46.orig/fs/namei.c 2013-07-26 19:16:51.000000000 +0000 ++++ linux-3.2.46/fs/namei.c 2013-07-26 19:16:53.000000000 +0000 +@@ -1759,6 +1759,7 @@ { return __lookup_hash(&nd->last, nd->path.dentry, nd); } @@ -37,11 +37,11 @@ /** * lookup_one_len - filesystem helper to lookup single pathname component -diff --git a/fs/namespace.c b/fs/namespace.c -index cfc6d44..173d15a 100644 ---- a/fs/namespace.c -+++ b/fs/namespace.c -@@ -1506,6 +1506,7 @@ int iterate_mounts(int (*f)(struct vfsmount *, void *), void *arg, +Index: linux-3.2.46/fs/namespace.c +=================================================================== +--- linux-3.2.46.orig/fs/namespace.c 2013-07-26 18:56:42.000000000 +0000 ++++ linux-3.2.46/fs/namespace.c 2013-07-26 19:16:53.000000000 +0000 +@@ -1507,6 +1507,7 @@ } return 0; } @@ -49,10 +49,10 @@ static void cleanup_group_ids(struct vfsmount *mnt, struct vfsmount *end) { -diff --git a/fs/notify/group.c b/fs/notify/group.c -index 63fc294..6f4adca 100644 ---- a/fs/notify/group.c -+++ b/fs/notify/group.c +Index: linux-3.2.46/fs/notify/group.c +=================================================================== +--- linux-3.2.46.orig/fs/notify/group.c 2013-07-26 18:56:42.000000000 +0000 ++++ linux-3.2.46/fs/notify/group.c 2013-07-26 19:16:53.000000000 +0000 @@ -22,6 +22,7 @@ #include #include @@ -61,7 +61,7 @@ #include #include "fsnotify.h" -@@ -70,6 +71,7 @@ void fsnotify_put_group(struct fsnotify_group *group) +@@ -70,6 +71,7 @@ if (atomic_dec_and_test(&group->refcnt)) fsnotify_destroy_group(group); } @@ -69,16 +69,16 @@ /* * Create a new fsnotify_group and hold a reference for the group returned. -@@ -102,3 +104,4 @@ struct fsnotify_group *fsnotify_alloc_group(const struct fsnotify_ops *ops) +@@ -102,3 +104,4 @@ return group; } +EXPORT_SYMBOL_GPL(fsnotify_alloc_group); -diff --git a/fs/notify/mark.c b/fs/notify/mark.c -index e14587d..be6533b 100644 ---- a/fs/notify/mark.c -+++ b/fs/notify/mark.c -@@ -112,6 +112,7 @@ void fsnotify_put_mark(struct fsnotify_mark *mark) +Index: linux-3.2.46/fs/notify/mark.c +=================================================================== +--- linux-3.2.46.orig/fs/notify/mark.c 2013-07-26 18:56:42.000000000 +0000 ++++ linux-3.2.46/fs/notify/mark.c 2013-07-26 19:16:53.000000000 +0000 +@@ -112,6 +112,7 @@ if (atomic_dec_and_test(&mark->refcnt)) mark->free_mark(mark); } @@ -86,7 +86,7 @@ /* * Any time a mark is getting freed we end up here. -@@ -189,6 +190,7 @@ void fsnotify_destroy_mark(struct fsnotify_mark *mark) +@@ -191,6 +192,7 @@ if (unlikely(atomic_dec_and_test(&group->num_marks))) fsnotify_final_destroy_group(group); } @@ -94,7 +94,7 @@ void fsnotify_set_mark_mask_locked(struct fsnotify_mark *mark, __u32 mask) { -@@ -276,6 +278,7 @@ err: +@@ -278,6 +280,7 @@ return ret; } @@ -102,7 +102,7 @@ /* * clear any marks in a group in which mark->flags & flags is true -@@ -331,6 +334,7 @@ void fsnotify_init_mark(struct fsnotify_mark *mark, +@@ -333,6 +336,7 @@ atomic_set(&mark->refcnt, 1); mark->free_mark = free_mark; } @@ -110,11 +110,11 @@ static int fsnotify_mark_destroy(void *ignored) { -diff --git a/fs/open.c b/fs/open.c -index 22c41b5..33b4033 100644 ---- a/fs/open.c -+++ b/fs/open.c -@@ -60,6 +60,7 @@ int do_truncate(struct dentry *dentry, loff_t length, unsigned int time_attrs, +Index: linux-3.2.46/fs/open.c +=================================================================== +--- linux-3.2.46.orig/fs/open.c 2013-07-26 18:56:42.000000000 +0000 ++++ linux-3.2.46/fs/open.c 2013-07-26 19:16:53.000000000 +0000 +@@ -60,6 +60,7 @@ mutex_unlock(&dentry->d_inode->i_mutex); return ret; } @@ -122,11 +122,11 @@ static long do_sys_truncate(const char __user *pathname, loff_t length) { -diff --git a/fs/splice.c b/fs/splice.c -index e3569b0..9dc07b7 100644 ---- a/fs/splice.c -+++ b/fs/splice.c -@@ -1109,6 +1109,7 @@ long do_splice_from(struct pipe_inode_info *pipe, struct file *out, +Index: linux-3.2.46/fs/splice.c +=================================================================== +--- linux-3.2.46.orig/fs/splice.c 2013-07-26 19:16:51.000000000 +0000 ++++ linux-3.2.46/fs/splice.c 2013-07-26 19:16:53.000000000 +0000 +@@ -1118,6 +1118,7 @@ return splice_write(pipe, out, ppos, len, flags); } @@ -134,7 +134,7 @@ /* * Attempt to initiate a splice from a file to a pipe. -@@ -1135,6 +1136,7 @@ long do_splice_to(struct file *in, loff_t *ppos, +@@ -1144,6 +1145,7 @@ return splice_read(in, ppos, pipe, len, flags); } @@ -142,19 +142,19 @@ /** * splice_direct_to_actor - splices data directly between two non-pipes -diff --git a/security/commoncap.c b/security/commoncap.c -index ee4f848..611fd70 100644 ---- a/security/commoncap.c -+++ b/security/commoncap.c -@@ -975,3 +975,4 @@ int cap_file_mmap(struct file *file, unsigned long reqprot, +Index: linux-3.2.46/security/commoncap.c +=================================================================== +--- linux-3.2.46.orig/security/commoncap.c 2013-07-26 18:56:42.000000000 +0000 ++++ linux-3.2.46/security/commoncap.c 2013-07-26 19:16:53.000000000 +0000 +@@ -981,3 +981,4 @@ } return ret; } +EXPORT_SYMBOL_GPL(cap_file_mmap); -diff --git a/security/device_cgroup.c b/security/device_cgroup.c -index 4450fbe..bc94175 100644 ---- a/security/device_cgroup.c -+++ b/security/device_cgroup.c +Index: linux-3.2.46/security/device_cgroup.c +=================================================================== +--- linux-3.2.46.orig/security/device_cgroup.c 2013-07-26 18:56:42.000000000 +0000 ++++ linux-3.2.46/security/device_cgroup.c 2013-07-26 19:16:53.000000000 +0000 @@ -7,6 +7,7 @@ #include #include @@ -163,7 +163,7 @@ #include #include #include -@@ -500,6 +501,7 @@ found: +@@ -500,6 +501,7 @@ return -EPERM; } @@ -171,11 +171,11 @@ int devcgroup_inode_mknod(int mode, dev_t dev) { -diff --git a/security/security.c b/security/security.c -index e2f684a..892000c 100644 ---- a/security/security.c -+++ b/security/security.c -@@ -411,6 +411,7 @@ int security_path_rmdir(struct path *dir, struct dentry *dentry) +Index: linux-3.2.46/security/security.c +=================================================================== +--- linux-3.2.46.orig/security/security.c 2013-07-26 18:56:42.000000000 +0000 ++++ linux-3.2.46/security/security.c 2013-07-26 19:16:53.000000000 +0000 +@@ -411,6 +411,7 @@ return 0; return security_ops->path_rmdir(dir, dentry); } @@ -183,7 +183,7 @@ int security_path_unlink(struct path *dir, struct dentry *dentry) { -@@ -427,6 +428,7 @@ int security_path_symlink(struct path *dir, struct dentry *dentry, +@@ -427,6 +428,7 @@ return 0; return security_ops->path_symlink(dir, dentry, old_name); } @@ -191,7 +191,7 @@ int security_path_link(struct dentry *old_dentry, struct path *new_dir, struct dentry *new_dentry) -@@ -435,6 +437,7 @@ int security_path_link(struct dentry *old_dentry, struct path *new_dir, +@@ -435,6 +437,7 @@ return 0; return security_ops->path_link(old_dentry, new_dir, new_dentry); } @@ -199,7 +199,7 @@ int security_path_rename(struct path *old_dir, struct dentry *old_dentry, struct path *new_dir, struct dentry *new_dentry) -@@ -453,6 +456,7 @@ int security_path_truncate(struct path *path) +@@ -453,6 +456,7 @@ return 0; return security_ops->path_truncate(path); } @@ -207,7 +207,7 @@ int security_path_chmod(struct dentry *dentry, struct vfsmount *mnt, mode_t mode) -@@ -461,6 +465,7 @@ int security_path_chmod(struct dentry *dentry, struct vfsmount *mnt, +@@ -461,6 +465,7 @@ return 0; return security_ops->path_chmod(dentry, mnt, mode); } @@ -215,7 +215,7 @@ int security_path_chown(struct path *path, uid_t uid, gid_t gid) { -@@ -468,6 +473,7 @@ int security_path_chown(struct path *path, uid_t uid, gid_t gid) +@@ -468,6 +473,7 @@ return 0; return security_ops->path_chown(path, uid, gid); } @@ -223,7 +223,7 @@ int security_path_chroot(struct path *path) { -@@ -544,6 +550,7 @@ int security_inode_readlink(struct dentry *dentry) +@@ -544,6 +550,7 @@ return 0; return security_ops->inode_readlink(dentry); } @@ -231,7 +231,7 @@ int security_inode_follow_link(struct dentry *dentry, struct nameidata *nd) { -@@ -558,6 +565,7 @@ int security_inode_permission(struct inode *inode, int mask) +@@ -558,6 +565,7 @@ return 0; return security_ops->inode_permission(inode, mask); } @@ -239,7 +239,7 @@ int security_inode_setattr(struct dentry *dentry, struct iattr *attr) { -@@ -673,6 +681,7 @@ int security_file_permission(struct file *file, int mask) +@@ -673,6 +681,7 @@ return fsnotify_perm(file, mask); } @@ -247,7 +247,7 @@ int security_file_alloc(struct file *file) { -@@ -700,6 +709,7 @@ int security_file_mmap(struct file *file, unsigned long reqprot, +@@ -700,6 +709,7 @@ return ret; return ima_file_mmap(file, prot); } diff -Nru linux-3.2.46/debian/patches/features/all/aufs3/mark-as-staging.patch linux-3.2.46/debian/patches/features/all/aufs3/mark-as-staging.patch --- linux-3.2.46/debian/patches/features/all/aufs3/mark-as-staging.patch 2013-02-24 03:52:40.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/aufs3/mark-as-staging.patch 2013-07-26 19:17:04.000000000 +0000 @@ -3,9 +3,11 @@ I really don't want to support this. ---- a/fs/aufs/module.c -+++ b/fs/aufs/module.c -@@ -89,6 +89,7 @@ +Index: linux-3.2.46/fs/aufs/module.c +=================================================================== +--- linux-3.2.46.orig/fs/aufs/module.c 2013-07-26 19:16:57.000000000 +0000 ++++ linux-3.2.46/fs/aufs/module.c 2013-07-26 19:17:03.000000000 +0000 +@@ -97,6 +97,7 @@ MODULE_DESCRIPTION(AUFS_NAME " -- Advanced multi layered unification filesystem"); MODULE_VERSION(AUFS_VERSION); diff -Nru linux-3.2.46/debian/patches/features/all/be2net/0001-sweep-the-floors-and-convert-some-.get_drvinfo-routi.patch linux-3.2.46/debian/patches/features/all/be2net/0001-sweep-the-floors-and-convert-some-.get_drvinfo-routi.patch --- linux-3.2.46/debian/patches/features/all/be2net/0001-sweep-the-floors-and-convert-some-.get_drvinfo-routi.patch 2013-02-24 03:52:39.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/be2net/0001-sweep-the-floors-and-convert-some-.get_drvinfo-routi.patch 2013-07-26 19:20:52.000000000 +0000 @@ -17,11 +17,11 @@ drivers/net/ethernet/emulex/benet/be_ethtool.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) -diff --git a/drivers/net/ethernet/emulex/benet/be_ethtool.c b/drivers/net/ethernet/emulex/benet/be_ethtool.c -index bf8153e..1ad7a28 100644 ---- a/drivers/net/ethernet/emulex/benet/be_ethtool.c -+++ b/drivers/net/ethernet/emulex/benet/be_ethtool.c -@@ -127,8 +127,8 @@ static void be_get_drvinfo(struct net_device *netdev, +Index: linux-3.2.46/drivers/net/ethernet/emulex/benet/be_ethtool.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/emulex/benet/be_ethtool.c 2013-07-26 18:55:27.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/emulex/benet/be_ethtool.c 2013-07-26 19:20:51.000000000 +0000 +@@ -127,8 +127,8 @@ memset(fw_on_flash, 0 , sizeof(fw_on_flash)); be_cmd_get_fw_ver(adapter, adapter->fw_ver, fw_on_flash); @@ -32,7 +32,7 @@ strncpy(drvinfo->fw_version, adapter->fw_ver, FW_VER_LEN); if (memcmp(adapter->fw_ver, fw_on_flash, FW_VER_LEN) != 0) { strcat(drvinfo->fw_version, " ["); -@@ -136,7 +136,8 @@ static void be_get_drvinfo(struct net_device *netdev, +@@ -136,7 +136,8 @@ strcat(drvinfo->fw_version, "]"); } @@ -42,6 +42,3 @@ drvinfo->testinfo_len = 0; drvinfo->regdump_len = 0; drvinfo->eedump_len = 0; --- -1.7.10 - diff -Nru linux-3.2.46/debian/patches/features/all/be2net/0002-be2net-init-vf-_if_handle-vf_pmac_id-to-handle-failu.patch linux-3.2.46/debian/patches/features/all/be2net/0002-be2net-init-vf-_if_handle-vf_pmac_id-to-handle-failu.patch --- linux-3.2.46/debian/patches/features/all/be2net/0002-be2net-init-vf-_if_handle-vf_pmac_id-to-handle-failu.patch 2013-02-24 03:52:39.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/be2net/0002-be2net-init-vf-_if_handle-vf_pmac_id-to-handle-failu.patch 2013-07-26 19:20:53.000000000 +0000 @@ -18,11 +18,11 @@ drivers/net/ethernet/emulex/benet/be_main.c | 55 +++++++++++++++------------ 4 files changed, 42 insertions(+), 34 deletions(-) -diff --git a/drivers/net/ethernet/emulex/benet/be.h b/drivers/net/ethernet/emulex/benet/be.h -index 644e8fe..4163980 100644 ---- a/drivers/net/ethernet/emulex/benet/be.h -+++ b/drivers/net/ethernet/emulex/benet/be.h -@@ -289,14 +289,12 @@ struct be_drv_stats { +Index: linux-3.2.46/drivers/net/ethernet/emulex/benet/be.h +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/emulex/benet/be.h 2013-07-26 18:55:27.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/emulex/benet/be.h 2013-07-26 19:20:52.000000000 +0000 +@@ -289,14 +289,12 @@ struct be_vf_cfg { unsigned char vf_mac_addr[ETH_ALEN]; @@ -39,7 +39,7 @@ struct be_adapter { struct pci_dev *pdev; struct net_device *netdev; -@@ -347,7 +345,7 @@ struct be_adapter { +@@ -347,7 +345,7 @@ /* Ethtool knobs and info */ char fw_ver[FW_VER_LEN]; @@ -48,11 +48,11 @@ u32 pmac_id; /* MAC addr handle used by BE card */ u32 beacon_state; /* for set_phys_id */ -diff --git a/drivers/net/ethernet/emulex/benet/be_cmds.c b/drivers/net/ethernet/emulex/benet/be_cmds.c -index 2c7b366..c5912c4 100644 ---- a/drivers/net/ethernet/emulex/benet/be_cmds.c -+++ b/drivers/net/ethernet/emulex/benet/be_cmds.c -@@ -695,12 +695,15 @@ err: +Index: linux-3.2.46/drivers/net/ethernet/emulex/benet/be_cmds.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/emulex/benet/be_cmds.c 2013-07-26 18:55:27.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/emulex/benet/be_cmds.c 2013-07-26 19:20:52.000000000 +0000 +@@ -695,12 +695,15 @@ } /* Uses synchronous MCCQ */ @@ -69,7 +69,7 @@ spin_lock_bh(&adapter->mcc_lock); wrb = wrb_from_mccq(adapter); -@@ -1136,7 +1139,7 @@ err: +@@ -1136,7 +1139,7 @@ } /* Uses MCCQ */ @@ -78,7 +78,7 @@ { struct be_mcc_wrb *wrb; struct be_cmd_req_if_destroy *req; -@@ -1145,7 +1148,7 @@ int be_cmd_if_destroy(struct be_adapter *adapter, u32 interface_id, u32 domain) +@@ -1145,7 +1148,7 @@ if (adapter->eeh_err) return -EIO; @@ -87,11 +87,11 @@ return 0; spin_lock_bh(&adapter->mcc_lock); -diff --git a/drivers/net/ethernet/emulex/benet/be_cmds.h b/drivers/net/ethernet/emulex/benet/be_cmds.h -index a35cd03..0818039 100644 ---- a/drivers/net/ethernet/emulex/benet/be_cmds.h -+++ b/drivers/net/ethernet/emulex/benet/be_cmds.h -@@ -1417,11 +1417,11 @@ extern int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr, +Index: linux-3.2.46/drivers/net/ethernet/emulex/benet/be_cmds.h +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/emulex/benet/be_cmds.h 2013-07-26 18:55:27.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/emulex/benet/be_cmds.h 2013-07-26 19:20:52.000000000 +0000 +@@ -1417,11 +1417,11 @@ extern int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr, u32 if_id, u32 *pmac_id, u32 domain); extern int be_cmd_pmac_del(struct be_adapter *adapter, u32 if_id, @@ -105,11 +105,11 @@ u32 domain); extern int be_cmd_eq_create(struct be_adapter *adapter, struct be_queue_info *eq, int eq_delay); -diff --git a/drivers/net/ethernet/emulex/benet/be_main.c b/drivers/net/ethernet/emulex/benet/be_main.c -index bf266a0..83d971d 100644 ---- a/drivers/net/ethernet/emulex/benet/be_main.c -+++ b/drivers/net/ethernet/emulex/benet/be_main.c -@@ -848,15 +848,11 @@ static int be_set_vf_mac(struct net_device *netdev, int vf, u8 *mac) +Index: linux-3.2.46/drivers/net/ethernet/emulex/benet/be_main.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/emulex/benet/be_main.c 2013-07-26 18:55:27.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/emulex/benet/be_main.c 2013-07-26 19:20:52.000000000 +0000 +@@ -849,15 +849,11 @@ if (!is_valid_ether_addr(mac) || (vf >= num_vfs)) return -EINVAL; @@ -128,7 +128,7 @@ if (status) dev_err(&adapter->pdev->dev, "MAC %pM set on VF %d Failed\n", mac, vf); -@@ -2488,17 +2484,13 @@ static void be_vf_clear(struct be_adapter *adapter) +@@ -2489,17 +2485,13 @@ { u32 vf; @@ -151,7 +151,7 @@ } static int be_clear(struct be_adapter *adapter) -@@ -2511,22 +2503,30 @@ static int be_clear(struct be_adapter *adapter) +@@ -2512,22 +2504,30 @@ be_mcc_queues_destroy(adapter); be_rx_queues_destroy(adapter); be_tx_queues_destroy(adapter); @@ -186,7 +186,7 @@ cap_flags = en_flags = BE_IF_FLAGS_UNTAGGED | BE_IF_FLAGS_BROADCAST; for (vf = 0; vf < num_vfs; vf++) { status = be_cmd_if_create(adapter, cap_flags, en_flags, NULL, -@@ -2534,7 +2534,6 @@ static int be_vf_setup(struct be_adapter *adapter) +@@ -2535,7 +2535,6 @@ NULL, vf+1); if (status) goto err; @@ -194,7 +194,7 @@ } if (!lancer_chip(adapter)) { -@@ -2555,6 +2554,16 @@ err: +@@ -2556,6 +2555,16 @@ return status; } @@ -211,7 +211,7 @@ static int be_setup(struct be_adapter *adapter) { struct net_device *netdev = adapter->netdev; -@@ -2563,9 +2572,7 @@ static int be_setup(struct be_adapter *adapter) +@@ -2564,9 +2573,7 @@ int status; u8 mac[ETH_ALEN]; @@ -222,6 +222,3 @@ be_cmd_req_native_mode(adapter); --- -1.7.10 - diff -Nru linux-3.2.46/debian/patches/features/all/be2net/0003-be2net-stop-checking-the-UE-registers-after-an-EEH-e.patch linux-3.2.46/debian/patches/features/all/be2net/0003-be2net-stop-checking-the-UE-registers-after-an-EEH-e.patch --- linux-3.2.46/debian/patches/features/all/be2net/0003-be2net-stop-checking-the-UE-registers-after-an-EEH-e.patch 2013-02-24 03:52:39.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/be2net/0003-be2net-stop-checking-the-UE-registers-after-an-EEH-e.patch 2013-07-26 19:20:54.000000000 +0000 @@ -11,11 +11,11 @@ drivers/net/ethernet/emulex/benet/be_main.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) -diff --git a/drivers/net/ethernet/emulex/benet/be_main.c b/drivers/net/ethernet/emulex/benet/be_main.c -index 83d971d..99da07f 100644 ---- a/drivers/net/ethernet/emulex/benet/be_main.c -+++ b/drivers/net/ethernet/emulex/benet/be_main.c -@@ -1978,6 +1978,9 @@ void be_detect_dump_ue(struct be_adapter *adapter) +Index: linux-3.2.46/drivers/net/ethernet/emulex/benet/be_main.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/emulex/benet/be_main.c 2013-07-26 19:20:52.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/emulex/benet/be_main.c 2013-07-26 19:20:54.000000000 +0000 +@@ -1979,6 +1979,9 @@ u32 sliport_status = 0, sliport_err1 = 0, sliport_err2 = 0; u32 i; @@ -25,7 +25,7 @@ if (lancer_chip(adapter)) { sliport_status = ioread32(adapter->db + SLIPORT_STATUS_OFFSET); if (sliport_status & SLIPORT_STATUS_ERR_MASK) { -@@ -2039,8 +2042,7 @@ static void be_worker(struct work_struct *work) +@@ -2040,8 +2043,7 @@ struct be_rx_obj *rxo; int i; @@ -35,6 +35,3 @@ /* when interrupts are not yet enabled, just reap any pending * mcc completions */ --- -1.7.10 - diff -Nru linux-3.2.46/debian/patches/features/all/be2net/0004-be2net-don-t-log-more-than-one-error-on-detecting-EE.patch linux-3.2.46/debian/patches/features/all/be2net/0004-be2net-don-t-log-more-than-one-error-on-detecting-EE.patch --- linux-3.2.46/debian/patches/features/all/be2net/0004-be2net-don-t-log-more-than-one-error-on-detecting-EE.patch 2013-02-24 03:52:39.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/be2net/0004-be2net-don-t-log-more-than-one-error-on-detecting-EE.patch 2013-07-26 19:20:56.000000000 +0000 @@ -15,11 +15,11 @@ drivers/net/ethernet/emulex/benet/be_main.c | 3 ++- 2 files changed, 5 insertions(+), 13 deletions(-) -diff --git a/drivers/net/ethernet/emulex/benet/be_cmds.c b/drivers/net/ethernet/emulex/benet/be_cmds.c -index c5912c4..94cd77c 100644 ---- a/drivers/net/ethernet/emulex/benet/be_cmds.c -+++ b/drivers/net/ethernet/emulex/benet/be_cmds.c -@@ -31,11 +31,8 @@ static void be_mcc_notify(struct be_adapter *adapter) +Index: linux-3.2.46/drivers/net/ethernet/emulex/benet/be_cmds.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/emulex/benet/be_cmds.c 2013-07-26 19:20:52.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/emulex/benet/be_cmds.c 2013-07-26 19:20:55.000000000 +0000 +@@ -31,11 +31,8 @@ struct be_queue_info *mccq = &adapter->mcc_obj.q; u32 val = 0; @@ -32,7 +32,7 @@ val |= mccq->id & DB_MCCQ_RING_ID_MASK; val |= 1 << DB_MCCQ_NUM_POSTED_SHIFT; -@@ -298,19 +295,13 @@ static int be_mbox_db_ready_wait(struct be_adapter *adapter, void __iomem *db) +@@ -298,19 +295,13 @@ int msecs = 0; u32 ready; @@ -54,11 +54,11 @@ ready &= MPU_MAILBOX_DB_RDY_MASK; if (ready) -diff --git a/drivers/net/ethernet/emulex/benet/be_main.c b/drivers/net/ethernet/emulex/benet/be_main.c -index 99da07f..0e97b6d 100644 ---- a/drivers/net/ethernet/emulex/benet/be_main.c -+++ b/drivers/net/ethernet/emulex/benet/be_main.c -@@ -2007,7 +2007,8 @@ void be_detect_dump_ue(struct be_adapter *adapter) +Index: linux-3.2.46/drivers/net/ethernet/emulex/benet/be_main.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/emulex/benet/be_main.c 2013-07-26 19:20:54.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/emulex/benet/be_main.c 2013-07-26 19:20:55.000000000 +0000 +@@ -2008,7 +2008,8 @@ sliport_status & SLIPORT_STATUS_ERR_MASK) { adapter->ue_detected = true; adapter->eeh_err = true; @@ -68,6 +68,3 @@ } if (ue_lo) { --- -1.7.10 - diff -Nru linux-3.2.46/debian/patches/features/all/be2net/0005-be2net-stop-issuing-FW-cmds-if-any-cmd-times-out.patch linux-3.2.46/debian/patches/features/all/be2net/0005-be2net-stop-issuing-FW-cmds-if-any-cmd-times-out.patch --- linux-3.2.46/debian/patches/features/all/be2net/0005-be2net-stop-issuing-FW-cmds-if-any-cmd-times-out.patch 2013-02-24 03:52:39.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/be2net/0005-be2net-stop-issuing-FW-cmds-if-any-cmd-times-out.patch 2013-07-26 19:20:57.000000000 +0000 @@ -16,11 +16,11 @@ drivers/net/ethernet/emulex/benet/be_main.c | 2 ++ 3 files changed, 20 insertions(+), 19 deletions(-) -diff --git a/drivers/net/ethernet/emulex/benet/be.h b/drivers/net/ethernet/emulex/benet/be.h -index 4163980..34f162d 100644 ---- a/drivers/net/ethernet/emulex/benet/be.h -+++ b/drivers/net/ethernet/emulex/benet/be.h -@@ -350,6 +350,8 @@ struct be_adapter { +Index: linux-3.2.46/drivers/net/ethernet/emulex/benet/be.h +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/emulex/benet/be.h 2013-07-26 19:20:52.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/emulex/benet/be.h 2013-07-26 19:20:56.000000000 +0000 +@@ -350,6 +350,8 @@ u32 beacon_state; /* for set_phys_id */ bool eeh_err; @@ -29,7 +29,7 @@ u32 port_num; bool promiscuous; bool wol; -@@ -357,7 +359,6 @@ struct be_adapter { +@@ -357,7 +359,6 @@ u32 function_caps; u32 rx_fc; /* Rx flow control */ u32 tx_fc; /* Tx flow control */ @@ -37,7 +37,7 @@ bool stats_cmd_sent; int link_speed; u8 port_type; -@@ -522,6 +523,11 @@ static inline bool be_multi_rxq(const struct be_adapter *adapter) +@@ -522,6 +523,11 @@ return adapter->num_rx_qs > 1; } @@ -49,11 +49,11 @@ extern void be_cq_notify(struct be_adapter *adapter, u16 qid, bool arm, u16 num_popped); extern void be_link_status_update(struct be_adapter *adapter, u32 link_status); -diff --git a/drivers/net/ethernet/emulex/benet/be_cmds.c b/drivers/net/ethernet/emulex/benet/be_cmds.c -index 94cd77c..ad3eef0 100644 ---- a/drivers/net/ethernet/emulex/benet/be_cmds.c -+++ b/drivers/net/ethernet/emulex/benet/be_cmds.c -@@ -31,7 +31,7 @@ static void be_mcc_notify(struct be_adapter *adapter) +Index: linux-3.2.46/drivers/net/ethernet/emulex/benet/be_cmds.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/emulex/benet/be_cmds.c 2013-07-26 19:20:55.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/emulex/benet/be_cmds.c 2013-07-26 19:20:56.000000000 +0000 +@@ -31,7 +31,7 @@ struct be_queue_info *mccq = &adapter->mcc_obj.q; u32 val = 0; @@ -62,7 +62,7 @@ return; val |= mccq->id & DB_MCCQ_RING_ID_MASK; -@@ -263,10 +263,10 @@ static int be_mcc_wait_compl(struct be_adapter *adapter) +@@ -263,10 +263,10 @@ int i, num, status = 0; struct be_mcc_obj *mcc_obj = &adapter->mcc_obj; @@ -76,7 +76,7 @@ num = be_process_mcc(adapter, &status); if (num) be_cq_notify(adapter, mcc_obj->cq.id, -@@ -277,7 +277,8 @@ static int be_mcc_wait_compl(struct be_adapter *adapter) +@@ -277,7 +277,8 @@ udelay(100); } if (i == mcc_timeout) { @@ -86,7 +86,7 @@ return -1; } return status; -@@ -295,10 +296,10 @@ static int be_mbox_db_ready_wait(struct be_adapter *adapter, void __iomem *db) +@@ -295,10 +296,10 @@ int msecs = 0; u32 ready; @@ -100,7 +100,7 @@ ready = ioread32(db); if (ready == 0xffffffff) return -1; -@@ -308,7 +309,8 @@ static int be_mbox_db_ready_wait(struct be_adapter *adapter, void __iomem *db) +@@ -308,7 +309,8 @@ break; if (msecs > 4000) { @@ -110,7 +110,7 @@ be_detect_dump_ue(adapter); return -1; } -@@ -546,9 +548,6 @@ int be_cmd_fw_clean(struct be_adapter *adapter) +@@ -546,9 +548,6 @@ u8 *wrb; int status; @@ -120,7 +120,7 @@ if (mutex_lock_interruptible(&adapter->mbox_lock)) return -1; -@@ -1012,9 +1011,6 @@ int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q, +@@ -1012,9 +1011,6 @@ u8 subsys = 0, opcode = 0; int status; @@ -130,7 +130,7 @@ if (mutex_lock_interruptible(&adapter->mbox_lock)) return -1; -@@ -1136,9 +1132,6 @@ int be_cmd_if_destroy(struct be_adapter *adapter, int interface_id, u32 domain) +@@ -1136,9 +1132,6 @@ struct be_cmd_req_if_destroy *req; int status; @@ -140,11 +140,11 @@ if (interface_id == -1) return 0; -diff --git a/drivers/net/ethernet/emulex/benet/be_main.c b/drivers/net/ethernet/emulex/benet/be_main.c -index 0e97b6d..ce20d64 100644 ---- a/drivers/net/ethernet/emulex/benet/be_main.c -+++ b/drivers/net/ethernet/emulex/benet/be_main.c -@@ -3569,6 +3569,8 @@ static pci_ers_result_t be_eeh_reset(struct pci_dev *pdev) +Index: linux-3.2.46/drivers/net/ethernet/emulex/benet/be_main.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/emulex/benet/be_main.c 2013-07-26 19:20:55.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/emulex/benet/be_main.c 2013-07-26 19:20:56.000000000 +0000 +@@ -3570,6 +3570,8 @@ dev_info(&adapter->pdev->dev, "EEH reset\n"); adapter->eeh_err = false; @@ -153,6 +153,3 @@ status = pci_enable_device(pdev); if (status) --- -1.7.10 - diff -Nru linux-3.2.46/debian/patches/features/all/be2net/0006-be2net-Fix-TX-queue-create-for-Lancer.patch linux-3.2.46/debian/patches/features/all/be2net/0006-be2net-Fix-TX-queue-create-for-Lancer.patch --- linux-3.2.46/debian/patches/features/all/be2net/0006-be2net-Fix-TX-queue-create-for-Lancer.patch 2013-02-24 03:52:39.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/be2net/0006-be2net-Fix-TX-queue-create-for-Lancer.patch 2013-07-26 19:20:58.000000000 +0000 @@ -16,11 +16,11 @@ drivers/net/ethernet/emulex/benet/be_main.c | 12 ++++++++---- 2 files changed, 18 insertions(+), 9 deletions(-) -diff --git a/drivers/net/ethernet/emulex/benet/be_cmds.c b/drivers/net/ethernet/emulex/benet/be_cmds.c -index ad3eef0..d35a214 100644 ---- a/drivers/net/ethernet/emulex/benet/be_cmds.c -+++ b/drivers/net/ethernet/emulex/benet/be_cmds.c -@@ -916,10 +916,14 @@ int be_cmd_txq_create(struct be_adapter *adapter, +Index: linux-3.2.46/drivers/net/ethernet/emulex/benet/be_cmds.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/emulex/benet/be_cmds.c 2013-07-26 19:20:56.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/emulex/benet/be_cmds.c 2013-07-26 19:20:58.000000000 +0000 +@@ -916,10 +916,14 @@ void *ctxt; int status; @@ -38,7 +38,7 @@ req = embedded_payload(wrb); ctxt = &req->context; -@@ -945,14 +949,15 @@ int be_cmd_txq_create(struct be_adapter *adapter, +@@ -945,14 +949,15 @@ be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem); @@ -56,11 +56,11 @@ return status; } -diff --git a/drivers/net/ethernet/emulex/benet/be_main.c b/drivers/net/ethernet/emulex/benet/be_main.c -index ce20d64..c982b51 100644 ---- a/drivers/net/ethernet/emulex/benet/be_main.c -+++ b/drivers/net/ethernet/emulex/benet/be_main.c -@@ -1689,9 +1689,6 @@ static int be_tx_queues_create(struct be_adapter *adapter) +Index: linux-3.2.46/drivers/net/ethernet/emulex/benet/be_main.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/emulex/benet/be_main.c 2013-07-26 19:20:56.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/emulex/benet/be_main.c 2013-07-26 19:20:58.000000000 +0000 +@@ -1690,9 +1690,6 @@ if (be_queue_alloc(adapter, q, TX_Q_LEN, sizeof(struct be_eth_wrb))) goto err; @@ -70,7 +70,7 @@ } return 0; -@@ -2572,8 +2569,9 @@ static int be_setup(struct be_adapter *adapter) +@@ -2573,8 +2570,9 @@ struct net_device *netdev = adapter->netdev; u32 cap_flags, en_flags; u32 tx_fc, rx_fc; @@ -81,7 +81,7 @@ be_setup_init(adapter); -@@ -2613,6 +2611,12 @@ static int be_setup(struct be_adapter *adapter) +@@ -2614,6 +2612,12 @@ if (status != 0) goto err; @@ -94,6 +94,3 @@ /* For BEx, the VF's permanent mac queried from card is incorrect. * Query the mac configued by the PF using if_handle */ --- -1.7.10 - diff -Nru linux-3.2.46/debian/patches/features/all/be2net/0007-be2net-add-register-dump-feature-for-Lancer.patch linux-3.2.46/debian/patches/features/all/be2net/0007-be2net-add-register-dump-feature-for-Lancer.patch --- linux-3.2.46/debian/patches/features/all/be2net/0007-be2net-add-register-dump-feature-for-Lancer.patch 2013-02-24 03:52:39.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/be2net/0007-be2net-add-register-dump-feature-for-Lancer.patch 2013-07-26 19:21:00.000000000 +0000 @@ -14,11 +14,11 @@ drivers/net/ethernet/emulex/benet/be_ethtool.c | 74 ++++++++++++++++++++++-- 3 files changed, 151 insertions(+), 4 deletions(-) -diff --git a/drivers/net/ethernet/emulex/benet/be_cmds.c b/drivers/net/ethernet/emulex/benet/be_cmds.c -index d35a214..1522065 100644 ---- a/drivers/net/ethernet/emulex/benet/be_cmds.c -+++ b/drivers/net/ethernet/emulex/benet/be_cmds.c -@@ -1828,6 +1828,53 @@ err_unlock: +Index: linux-3.2.46/drivers/net/ethernet/emulex/benet/be_cmds.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/emulex/benet/be_cmds.c 2013-07-26 19:20:58.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/emulex/benet/be_cmds.c 2013-07-26 19:20:59.000000000 +0000 +@@ -1828,6 +1828,53 @@ return status; } @@ -72,11 +72,11 @@ int be_cmd_write_flashrom(struct be_adapter *adapter, struct be_dma_mem *cmd, u32 flash_type, u32 flash_opcode, u32 buf_size) { -diff --git a/drivers/net/ethernet/emulex/benet/be_cmds.h b/drivers/net/ethernet/emulex/benet/be_cmds.h -index 0818039..2d3fe6a 100644 ---- a/drivers/net/ethernet/emulex/benet/be_cmds.h -+++ b/drivers/net/ethernet/emulex/benet/be_cmds.h -@@ -189,6 +189,7 @@ struct be_mcc_mailbox { +Index: linux-3.2.46/drivers/net/ethernet/emulex/benet/be_cmds.h +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/emulex/benet/be_cmds.h 2013-07-26 19:20:52.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/emulex/benet/be_cmds.h 2013-07-26 19:20:59.000000000 +0000 +@@ -189,6 +189,7 @@ #define OPCODE_COMMON_GET_PHY_DETAILS 102 #define OPCODE_COMMON_SET_DRIVER_FUNCTION_CAP 103 #define OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES 121 @@ -84,7 +84,7 @@ #define OPCODE_COMMON_WRITE_OBJECT 172 #define OPCODE_ETH_RSS_CONFIG 1 -@@ -1161,6 +1162,36 @@ struct lancer_cmd_resp_write_object { +@@ -1161,6 +1162,36 @@ u32 actual_write_len; }; @@ -121,7 +121,7 @@ /************************ WOL *******************************/ struct be_cmd_req_acpi_wol_magic_config{ struct be_cmd_req_hdr hdr; -@@ -1480,6 +1511,9 @@ extern int lancer_cmd_write_object(struct be_adapter *adapter, +@@ -1480,6 +1511,9 @@ u32 data_size, u32 data_offset, const char *obj_name, u32 *data_written, u8 *addn_status); @@ -131,11 +131,11 @@ int be_cmd_get_flash_crc(struct be_adapter *adapter, u8 *flashed_crc, int offset); extern int be_cmd_enable_magic_wol(struct be_adapter *adapter, u8 *mac, -diff --git a/drivers/net/ethernet/emulex/benet/be_ethtool.c b/drivers/net/ethernet/emulex/benet/be_ethtool.c -index 1ad7a28..1e7252e 100644 ---- a/drivers/net/ethernet/emulex/benet/be_ethtool.c -+++ b/drivers/net/ethernet/emulex/benet/be_ethtool.c -@@ -143,15 +143,77 @@ static void be_get_drvinfo(struct net_device *netdev, +Index: linux-3.2.46/drivers/net/ethernet/emulex/benet/be_ethtool.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/emulex/benet/be_ethtool.c 2013-07-26 19:20:51.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/emulex/benet/be_ethtool.c 2013-07-26 19:20:59.000000000 +0000 +@@ -143,15 +143,77 @@ drvinfo->eedump_len = 0; } @@ -216,7 +216,7 @@ return log_size; } -@@ -162,7 +224,11 @@ be_get_regs(struct net_device *netdev, struct ethtool_regs *regs, void *buf) +@@ -162,7 +224,11 @@ if (be_physfn(adapter)) { memset(buf, 0, regs->len); @@ -229,6 +229,3 @@ } } --- -1.7.10 - diff -Nru linux-3.2.46/debian/patches/features/all/be2net/0008-be2net-Add-EEPROM-dump-feature-for-Lancer.patch linux-3.2.46/debian/patches/features/all/be2net/0008-be2net-Add-EEPROM-dump-feature-for-Lancer.patch --- linux-3.2.46/debian/patches/features/all/be2net/0008-be2net-Add-EEPROM-dump-feature-for-Lancer.patch 2013-02-24 03:52:39.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/be2net/0008-be2net-Add-EEPROM-dump-feature-for-Lancer.patch 2013-07-26 19:21:02.000000000 +0000 @@ -13,11 +13,11 @@ drivers/net/ethernet/emulex/benet/be_ethtool.c | 21 ++++++++++++++++++++- 2 files changed, 22 insertions(+), 1 deletion(-) -diff --git a/drivers/net/ethernet/emulex/benet/be_cmds.h b/drivers/net/ethernet/emulex/benet/be_cmds.h -index 2d3fe6a..ac11246 100644 ---- a/drivers/net/ethernet/emulex/benet/be_cmds.h -+++ b/drivers/net/ethernet/emulex/benet/be_cmds.h -@@ -1167,6 +1167,8 @@ struct lancer_cmd_resp_write_object { +Index: linux-3.2.46/drivers/net/ethernet/emulex/benet/be_cmds.h +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/emulex/benet/be_cmds.h 2013-07-26 19:20:59.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/emulex/benet/be_cmds.h 2013-07-26 19:21:00.000000000 +0000 +@@ -1167,6 +1167,8 @@ #define LANCER_READ_FILE_EOF_MASK 0x80000000 #define LANCER_FW_DUMP_FILE "/dbg/dump.bin" @@ -26,11 +26,11 @@ struct lancer_cmd_req_read_object { struct be_cmd_req_hdr hdr; -diff --git a/drivers/net/ethernet/emulex/benet/be_ethtool.c b/drivers/net/ethernet/emulex/benet/be_ethtool.c -index 1e7252e..575c783 100644 ---- a/drivers/net/ethernet/emulex/benet/be_ethtool.c -+++ b/drivers/net/ethernet/emulex/benet/be_ethtool.c -@@ -727,7 +727,17 @@ be_do_flash(struct net_device *netdev, struct ethtool_flash *efl) +Index: linux-3.2.46/drivers/net/ethernet/emulex/benet/be_ethtool.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/emulex/benet/be_ethtool.c 2013-07-26 19:20:59.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/emulex/benet/be_ethtool.c 2013-07-26 19:21:00.000000000 +0000 +@@ -723,7 +723,17 @@ static int be_get_eeprom_len(struct net_device *netdev) { @@ -49,7 +49,7 @@ } static int -@@ -742,6 +752,15 @@ be_read_eeprom(struct net_device *netdev, struct ethtool_eeprom *eeprom, +@@ -738,6 +748,15 @@ if (!eeprom->len) return -EINVAL; @@ -65,6 +65,3 @@ eeprom->magic = BE_VENDOR_ID | (adapter->pdev->device<<16); memset(&eeprom_cmd, 0, sizeof(struct be_dma_mem)); --- -1.7.10 - diff -Nru linux-3.2.46/debian/patches/features/all/be2net/0009-be2net-Fix-VLAN-promiscous-mode-for-Lancer.patch linux-3.2.46/debian/patches/features/all/be2net/0009-be2net-Fix-VLAN-promiscous-mode-for-Lancer.patch --- linux-3.2.46/debian/patches/features/all/be2net/0009-be2net-Fix-VLAN-promiscous-mode-for-Lancer.patch 2013-02-24 03:52:39.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/be2net/0009-be2net-Fix-VLAN-promiscous-mode-for-Lancer.patch 2013-07-26 19:21:04.000000000 +0000 @@ -14,11 +14,11 @@ drivers/net/ethernet/emulex/benet/be_main.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) -diff --git a/drivers/net/ethernet/emulex/benet/be_main.c b/drivers/net/ethernet/emulex/benet/be_main.c -index c982b51..93869d4 100644 ---- a/drivers/net/ethernet/emulex/benet/be_main.c -+++ b/drivers/net/ethernet/emulex/benet/be_main.c -@@ -2600,7 +2600,8 @@ static int be_setup(struct be_adapter *adapter) +Index: linux-3.2.46/drivers/net/ethernet/emulex/benet/be_main.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/emulex/benet/be_main.c 2013-07-26 19:20:58.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/emulex/benet/be_main.c 2013-07-26 19:21:02.000000000 +0000 +@@ -2601,7 +2601,8 @@ en_flags = BE_IF_FLAGS_UNTAGGED | BE_IF_FLAGS_BROADCAST | BE_IF_FLAGS_MULTICAST | BE_IF_FLAGS_PASS_L3L4_ERRORS; cap_flags = en_flags | BE_IF_FLAGS_MCAST_PROMISCUOUS | @@ -28,6 +28,3 @@ if (adapter->function_caps & BE_FUNCTION_CAPS_RSS) { cap_flags |= BE_IF_FLAGS_RSS; en_flags |= BE_IF_FLAGS_RSS; --- -1.7.10 - diff -Nru linux-3.2.46/debian/patches/features/all/be2net/0010-be2net-Use-V1-query-link-status-command-for-lancer.patch linux-3.2.46/debian/patches/features/all/be2net/0010-be2net-Use-V1-query-link-status-command-for-lancer.patch --- linux-3.2.46/debian/patches/features/all/be2net/0010-be2net-Use-V1-query-link-status-command-for-lancer.patch 2013-02-24 03:52:39.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/be2net/0010-be2net-Use-V1-query-link-status-command-for-lancer.patch 2013-07-26 19:21:05.000000000 +0000 @@ -12,11 +12,11 @@ drivers/net/ethernet/emulex/benet/be_cmds.c | 3 +++ 1 file changed, 3 insertions(+) -diff --git a/drivers/net/ethernet/emulex/benet/be_cmds.c b/drivers/net/ethernet/emulex/benet/be_cmds.c -index 1522065..64f0c1a 100644 ---- a/drivers/net/ethernet/emulex/benet/be_cmds.c -+++ b/drivers/net/ethernet/emulex/benet/be_cmds.c -@@ -1246,6 +1246,9 @@ int be_cmd_link_status_query(struct be_adapter *adapter, u8 *mac_speed, +Index: linux-3.2.46/drivers/net/ethernet/emulex/benet/be_cmds.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/emulex/benet/be_cmds.c 2013-07-26 19:20:59.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/emulex/benet/be_cmds.c 2013-07-26 19:21:05.000000000 +0000 +@@ -1246,6 +1246,9 @@ } req = embedded_payload(wrb); @@ -26,6 +26,3 @@ be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, OPCODE_COMMON_NTWK_LINK_STATUS_QUERY, sizeof(*req), wrb, NULL); --- -1.7.10 - diff -Nru linux-3.2.46/debian/patches/features/all/be2net/0011-be2net-Move-to-new-SR-IOV-implementation-in-Lancer.patch linux-3.2.46/debian/patches/features/all/be2net/0011-be2net-Move-to-new-SR-IOV-implementation-in-Lancer.patch --- linux-3.2.46/debian/patches/features/all/be2net/0011-be2net-Move-to-new-SR-IOV-implementation-in-Lancer.patch 2013-02-24 03:52:39.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/be2net/0011-be2net-Move-to-new-SR-IOV-implementation-in-Lancer.patch 2013-07-26 19:21:07.000000000 +0000 @@ -18,11 +18,11 @@ drivers/net/ethernet/emulex/benet/be_main.c | 89 +++++++++++++++++------- 3 files changed, 200 insertions(+), 25 deletions(-) -diff --git a/drivers/net/ethernet/emulex/benet/be_cmds.c b/drivers/net/ethernet/emulex/benet/be_cmds.c -index 64f0c1a..7988798 100644 ---- a/drivers/net/ethernet/emulex/benet/be_cmds.c -+++ b/drivers/net/ethernet/emulex/benet/be_cmds.c -@@ -609,7 +609,7 @@ int be_cmd_eq_create(struct be_adapter *adapter, +Index: linux-3.2.46/drivers/net/ethernet/emulex/benet/be_cmds.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/emulex/benet/be_cmds.c 2013-07-26 19:21:05.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/emulex/benet/be_cmds.c 2013-07-26 19:21:06.000000000 +0000 +@@ -609,7 +609,7 @@ /* Use MCC */ int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr, @@ -31,7 +31,7 @@ { struct be_mcc_wrb *wrb; struct be_cmd_req_mac_query *req; -@@ -631,6 +631,7 @@ int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr, +@@ -631,6 +631,7 @@ req->permanent = 1; } else { req->if_id = cpu_to_le16((u16) if_handle); @@ -39,7 +39,7 @@ req->permanent = 0; } -@@ -2280,3 +2281,99 @@ err: +@@ -2280,3 +2281,99 @@ mutex_unlock(&adapter->mbox_lock); return status; } @@ -139,11 +139,11 @@ + spin_unlock_bh(&adapter->mcc_lock); + return status; +} -diff --git a/drivers/net/ethernet/emulex/benet/be_cmds.h b/drivers/net/ethernet/emulex/benet/be_cmds.h -index ac11246..0b694c6 100644 ---- a/drivers/net/ethernet/emulex/benet/be_cmds.h -+++ b/drivers/net/ethernet/emulex/benet/be_cmds.h -@@ -189,6 +189,8 @@ struct be_mcc_mailbox { +Index: linux-3.2.46/drivers/net/ethernet/emulex/benet/be_cmds.h +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/emulex/benet/be_cmds.h 2013-07-26 19:21:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/emulex/benet/be_cmds.h 2013-07-26 19:21:06.000000000 +0000 +@@ -189,6 +189,8 @@ #define OPCODE_COMMON_GET_PHY_DETAILS 102 #define OPCODE_COMMON_SET_DRIVER_FUNCTION_CAP 103 #define OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES 121 @@ -152,7 +152,7 @@ #define OPCODE_COMMON_READ_OBJECT 171 #define OPCODE_COMMON_WRITE_OBJECT 172 -@@ -295,6 +297,7 @@ struct be_cmd_req_mac_query { +@@ -295,6 +297,7 @@ u8 type; u8 permanent; u16 if_id; @@ -160,7 +160,7 @@ } __packed; struct be_cmd_resp_mac_query { -@@ -1340,6 +1343,34 @@ struct be_cmd_resp_set_func_cap { +@@ -1340,6 +1343,34 @@ u8 rsvd[212]; }; @@ -195,7 +195,7 @@ /*************** HW Stats Get v1 **********************************/ #define BE_TXP_SW_SZ 48 struct be_port_rxf_stats_v1 { -@@ -1446,7 +1477,7 @@ static inline void *be_erx_stats_from_cmd(struct be_adapter *adapter) +@@ -1446,7 +1477,7 @@ extern int be_pci_fnum_get(struct be_adapter *adapter); extern int be_cmd_POST(struct be_adapter *adapter); extern int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr, @@ -204,7 +204,7 @@ extern int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr, u32 if_id, u32 *pmac_id, u32 domain); extern int be_cmd_pmac_del(struct be_adapter *adapter, u32 if_id, -@@ -1542,4 +1573,8 @@ extern int be_cmd_get_cntl_attributes(struct be_adapter *adapter); +@@ -1542,4 +1573,8 @@ extern int be_cmd_req_native_mode(struct be_adapter *adapter); extern int be_cmd_get_reg_len(struct be_adapter *adapter, u32 *log_size); extern void be_cmd_get_regs(struct be_adapter *adapter, u32 buf_len, void *buf); @@ -213,11 +213,11 @@ +extern int be_cmd_set_mac_list(struct be_adapter *adapter, u8 *mac_array, + u8 mac_count, u32 domain); -diff --git a/drivers/net/ethernet/emulex/benet/be_main.c b/drivers/net/ethernet/emulex/benet/be_main.c -index 93869d4..c6fb7c3 100644 ---- a/drivers/net/ethernet/emulex/benet/be_main.c -+++ b/drivers/net/ethernet/emulex/benet/be_main.c -@@ -237,7 +237,8 @@ static int be_mac_addr_set(struct net_device *netdev, void *p) +Index: linux-3.2.46/drivers/net/ethernet/emulex/benet/be_main.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/emulex/benet/be_main.c 2013-07-26 19:21:02.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/emulex/benet/be_main.c 2013-07-26 19:21:06.000000000 +0000 +@@ -237,7 +237,8 @@ return -EADDRNOTAVAIL; status = be_cmd_mac_addr_query(adapter, current_mac, @@ -227,7 +227,7 @@ if (status) goto err; -@@ -848,11 +849,18 @@ static int be_set_vf_mac(struct net_device *netdev, int vf, u8 *mac) +@@ -849,11 +850,18 @@ if (!is_valid_ether_addr(mac) || (vf >= num_vfs)) return -EINVAL; @@ -248,7 +248,7 @@ if (status) dev_err(&adapter->pdev->dev, "MAC %pM set on VF %d Failed\n", mac, vf); -@@ -2465,13 +2473,18 @@ static inline int be_vf_eth_addr_config(struct be_adapter *adapter) +@@ -2466,13 +2474,18 @@ be_vf_eth_addr_generate(adapter, mac); for (vf = 0; vf < num_vfs; vf++) { @@ -269,7 +269,7 @@ else memcpy(adapter->vf_cfg[vf].vf_mac_addr, mac, ETH_ALEN); -@@ -2484,9 +2497,14 @@ static void be_vf_clear(struct be_adapter *adapter) +@@ -2485,9 +2498,14 @@ { u32 vf; @@ -287,7 +287,7 @@ for (vf = 0; vf < num_vfs; vf++) be_cmd_if_destroy(adapter, adapter->vf_cfg[vf].vf_if_handle, -@@ -2527,7 +2545,9 @@ static int be_vf_setup(struct be_adapter *adapter) +@@ -2528,7 +2546,9 @@ be_vf_setup_init(adapter); @@ -298,7 +298,7 @@ for (vf = 0; vf < num_vfs; vf++) { status = be_cmd_if_create(adapter, cap_flags, en_flags, NULL, &adapter->vf_cfg[vf].vf_if_handle, -@@ -2536,11 +2556,9 @@ static int be_vf_setup(struct be_adapter *adapter) +@@ -2537,11 +2557,9 @@ goto err; } @@ -313,7 +313,7 @@ for (vf = 0; vf < num_vfs; vf++) { status = be_cmd_link_status_query(adapter, NULL, &lnk_speed, -@@ -2564,6 +2582,23 @@ static void be_setup_init(struct be_adapter *adapter) +@@ -2565,6 +2583,23 @@ adapter->eq_next_idx = 0; } @@ -337,7 +337,7 @@ static int be_setup(struct be_adapter *adapter) { struct net_device *netdev = adapter->netdev; -@@ -2591,7 +2626,7 @@ static int be_setup(struct be_adapter *adapter) +@@ -2592,7 +2627,7 @@ memset(mac, 0, ETH_ALEN); status = be_cmd_mac_addr_query(adapter, mac, MAC_ADDRESS_TYPE_NETWORK, @@ -346,7 +346,7 @@ if (status) return status; memcpy(adapter->netdev->dev_addr, mac, ETH_ALEN); -@@ -2618,12 +2653,17 @@ static int be_setup(struct be_adapter *adapter) +@@ -2619,12 +2654,17 @@ goto err; } @@ -370,7 +370,7 @@ if (!status) { memcpy(adapter->netdev->dev_addr, mac, ETH_ALEN); memcpy(adapter->netdev->perm_addr, mac, ETH_ALEN); -@@ -2639,12 +2679,15 @@ static int be_setup(struct be_adapter *adapter) +@@ -2640,12 +2680,15 @@ be_set_rx_mode(adapter->netdev); status = be_cmd_get_flow_control(adapter, &tx_fc, &rx_fc); @@ -388,6 +388,3 @@ goto err; } --- -1.7.10 - diff -Nru linux-3.2.46/debian/patches/features/all/be2net/0012-be2net-Fix-error-recovery-paths.patch linux-3.2.46/debian/patches/features/all/be2net/0012-be2net-Fix-error-recovery-paths.patch --- linux-3.2.46/debian/patches/features/all/be2net/0012-be2net-Fix-error-recovery-paths.patch 2013-02-24 03:52:39.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/be2net/0012-be2net-Fix-error-recovery-paths.patch 2013-07-26 19:21:08.000000000 +0000 @@ -14,11 +14,11 @@ drivers/net/ethernet/emulex/benet/be_main.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) -diff --git a/drivers/net/ethernet/emulex/benet/be_main.c b/drivers/net/ethernet/emulex/benet/be_main.c -index c6fb7c3..a1b8ebc 100644 ---- a/drivers/net/ethernet/emulex/benet/be_main.c -+++ b/drivers/net/ethernet/emulex/benet/be_main.c -@@ -1666,9 +1666,12 @@ static int be_tx_queues_create(struct be_adapter *adapter) +Index: linux-3.2.46/drivers/net/ethernet/emulex/benet/be_main.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/emulex/benet/be_main.c 2013-07-26 19:21:06.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/emulex/benet/be_main.c 2013-07-26 19:21:07.000000000 +0000 +@@ -1667,9 +1667,12 @@ u8 i; adapter->num_tx_qs = be_num_txqs_want(adapter); @@ -32,6 +32,3 @@ adapter->tx_eq.max_eqd = 0; adapter->tx_eq.min_eqd = 0; --- -1.7.10 - diff -Nru linux-3.2.46/debian/patches/features/all/be2net/0013-be2net-Add-error-handling-for-Lancer.patch linux-3.2.46/debian/patches/features/all/be2net/0013-be2net-Add-error-handling-for-Lancer.patch --- linux-3.2.46/debian/patches/features/all/be2net/0013-be2net-Add-error-handling-for-Lancer.patch 2013-02-24 03:52:39.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/be2net/0013-be2net-Add-error-handling-for-Lancer.patch 2013-07-26 19:21:09.000000000 +0000 @@ -13,11 +13,11 @@ drivers/net/ethernet/emulex/benet/be_main.c | 155 ++++++++++++++++++--------- 1 file changed, 106 insertions(+), 49 deletions(-) -diff --git a/drivers/net/ethernet/emulex/benet/be_main.c b/drivers/net/ethernet/emulex/benet/be_main.c -index a1b8ebc..66429ea 100644 ---- a/drivers/net/ethernet/emulex/benet/be_main.c -+++ b/drivers/net/ethernet/emulex/benet/be_main.c -@@ -2044,52 +2044,6 @@ void be_detect_dump_ue(struct be_adapter *adapter) +Index: linux-3.2.46/drivers/net/ethernet/emulex/benet/be_main.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/emulex/benet/be_main.c 2013-07-26 19:21:07.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/emulex/benet/be_main.c 2013-07-26 19:21:09.000000000 +0000 +@@ -2045,52 +2045,6 @@ } } @@ -70,7 +70,7 @@ static void be_msix_disable(struct be_adapter *adapter) { if (msix_enabled(adapter)) { -@@ -3328,7 +3282,7 @@ static int be_dev_family_check(struct be_adapter *adapter) +@@ -3329,7 +3283,7 @@ static int lancer_wait_ready(struct be_adapter *adapter) { @@ -79,7 +79,7 @@ u32 sliport_status; int status = 0, i; -@@ -3337,7 +3291,7 @@ static int lancer_wait_ready(struct be_adapter *adapter) +@@ -3338,7 +3292,7 @@ if (sliport_status & SLIPORT_STATUS_RDY_MASK) break; @@ -88,7 +88,7 @@ } if (i == SLIPORT_READY_TIMEOUT) -@@ -3374,6 +3328,104 @@ static int lancer_test_and_set_rdy_state(struct be_adapter *adapter) +@@ -3375,6 +3329,104 @@ return status; } @@ -193,7 +193,7 @@ static int __devinit be_probe(struct pci_dev *pdev, const struct pci_device_id *pdev_id) { -@@ -3426,7 +3478,12 @@ static int __devinit be_probe(struct pci_dev *pdev, +@@ -3427,7 +3479,12 @@ goto disable_sriov; if (lancer_chip(adapter)) { @@ -207,6 +207,3 @@ if (status) { dev_err(&pdev->dev, "Adapter in non recoverable error\n"); goto ctrl_clean; --- -1.7.10 - diff -Nru linux-3.2.46/debian/patches/features/all/be2net/0014-be2net-Use-new-hash-key.patch linux-3.2.46/debian/patches/features/all/be2net/0014-be2net-Use-new-hash-key.patch --- linux-3.2.46/debian/patches/features/all/be2net/0014-be2net-Use-new-hash-key.patch 2013-02-24 03:52:39.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/be2net/0014-be2net-Use-new-hash-key.patch 2013-07-26 19:21:11.000000000 +0000 @@ -13,11 +13,11 @@ drivers/net/ethernet/emulex/benet/be_cmds.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) -diff --git a/drivers/net/ethernet/emulex/benet/be_cmds.c b/drivers/net/ethernet/emulex/benet/be_cmds.c -index 7988798..62868ea 100644 ---- a/drivers/net/ethernet/emulex/benet/be_cmds.c -+++ b/drivers/net/ethernet/emulex/benet/be_cmds.c -@@ -1669,8 +1669,9 @@ int be_cmd_rss_config(struct be_adapter *adapter, u8 *rsstable, u16 table_size) +Index: linux-3.2.46/drivers/net/ethernet/emulex/benet/be_cmds.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/emulex/benet/be_cmds.c 2013-07-26 19:21:06.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/emulex/benet/be_cmds.c 2013-07-26 19:21:10.000000000 +0000 +@@ -1669,8 +1669,9 @@ { struct be_mcc_wrb *wrb; struct be_cmd_req_rss_config *req; @@ -29,6 +29,3 @@ int status; if (mutex_lock_interruptible(&adapter->mbox_lock)) --- -1.7.10 - diff -Nru linux-3.2.46/debian/patches/features/all/be2net/0015-be2net-Fix-non-utilization-of-RX-queues.patch linux-3.2.46/debian/patches/features/all/be2net/0015-be2net-Fix-non-utilization-of-RX-queues.patch --- linux-3.2.46/debian/patches/features/all/be2net/0015-be2net-Fix-non-utilization-of-RX-queues.patch 2013-02-24 03:52:39.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/be2net/0015-be2net-Fix-non-utilization-of-RX-queues.patch 2013-07-26 19:21:12.000000000 +0000 @@ -14,11 +14,11 @@ drivers/net/ethernet/emulex/benet/be_main.c | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) -diff --git a/drivers/net/ethernet/emulex/benet/be_main.c b/drivers/net/ethernet/emulex/benet/be_main.c -index 66429ea..7236280 100644 ---- a/drivers/net/ethernet/emulex/benet/be_main.c -+++ b/drivers/net/ethernet/emulex/benet/be_main.c -@@ -2312,8 +2312,8 @@ static int be_close(struct net_device *netdev) +Index: linux-3.2.46/drivers/net/ethernet/emulex/benet/be_main.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/emulex/benet/be_main.c 2013-07-26 19:21:09.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/emulex/benet/be_main.c 2013-07-26 19:21:11.000000000 +0000 +@@ -2313,8 +2313,8 @@ static int be_rx_queues_setup(struct be_adapter *adapter) { struct be_rx_obj *rxo; @@ -29,7 +29,7 @@ for_all_rx_queues(adapter, rxo, i) { rc = be_cmd_rxq_create(adapter, &rxo->q, rxo->cq.id, -@@ -2325,11 +2325,15 @@ static int be_rx_queues_setup(struct be_adapter *adapter) +@@ -2326,11 +2326,15 @@ } if (be_multi_rxq(adapter)) { @@ -49,6 +49,3 @@ if (rc) return rc; } --- -1.7.10 - diff -Nru linux-3.2.46/debian/patches/features/all/be2net/0016-be2net-netpoll-support.patch linux-3.2.46/debian/patches/features/all/be2net/0016-be2net-netpoll-support.patch --- linux-3.2.46/debian/patches/features/all/be2net/0016-be2net-netpoll-support.patch 2013-02-24 03:52:39.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/be2net/0016-be2net-netpoll-support.patch 2013-07-26 19:21:13.000000000 +0000 @@ -12,11 +12,11 @@ drivers/net/ethernet/emulex/benet/be_main.c | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) -diff --git a/drivers/net/ethernet/emulex/benet/be_main.c b/drivers/net/ethernet/emulex/benet/be_main.c -index 7236280..3854fb0 100644 ---- a/drivers/net/ethernet/emulex/benet/be_main.c -+++ b/drivers/net/ethernet/emulex/benet/be_main.c -@@ -2666,6 +2666,19 @@ err: +Index: linux-3.2.46/drivers/net/ethernet/emulex/benet/be_main.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/emulex/benet/be_main.c 2013-07-26 19:21:11.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/emulex/benet/be_main.c 2013-07-26 19:21:12.000000000 +0000 +@@ -2667,6 +2667,19 @@ return status; } @@ -36,7 +36,7 @@ #define FW_FILE_HDR_SIGN "ServerEngines Corp. " static bool be_flash_redboot(struct be_adapter *adapter, const u8 *p, u32 img_start, int image_size, -@@ -3014,7 +3027,10 @@ static struct net_device_ops be_netdev_ops = { +@@ -3015,7 +3028,10 @@ .ndo_set_vf_mac = be_set_vf_mac, .ndo_set_vf_vlan = be_set_vf_vlan, .ndo_set_vf_tx_rate = be_set_vf_tx_rate, @@ -48,6 +48,3 @@ }; static void be_netdev_init(struct net_device *netdev) --- -1.7.10 - diff -Nru linux-3.2.46/debian/patches/features/all/be2net/0017-be2net-update-some-counters-to-display-via-ethtool.patch linux-3.2.46/debian/patches/features/all/be2net/0017-be2net-update-some-counters-to-display-via-ethtool.patch --- linux-3.2.46/debian/patches/features/all/be2net/0017-be2net-update-some-counters-to-display-via-ethtool.patch 2013-02-24 03:52:39.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/be2net/0017-be2net-update-some-counters-to-display-via-ethtool.patch 2013-07-26 19:21:15.000000000 +0000 @@ -12,11 +12,11 @@ drivers/net/ethernet/emulex/benet/be_main.c | 2 ++ 1 file changed, 2 insertions(+) -diff --git a/drivers/net/ethernet/emulex/benet/be_main.c b/drivers/net/ethernet/emulex/benet/be_main.c -index 3854fb0..0da3df0 100644 ---- a/drivers/net/ethernet/emulex/benet/be_main.c -+++ b/drivers/net/ethernet/emulex/benet/be_main.c -@@ -316,6 +316,8 @@ static void populate_be3_stats(struct be_adapter *adapter) +Index: linux-3.2.46/drivers/net/ethernet/emulex/benet/be_main.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/emulex/benet/be_main.c 2013-07-26 19:21:12.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/emulex/benet/be_main.c 2013-07-26 19:21:14.000000000 +0000 +@@ -316,6 +316,8 @@ struct be_drv_stats *drvs = &adapter->drv_stats; be_dws_le_to_cpu(hw_stats, sizeof(*hw_stats)); @@ -25,6 +25,3 @@ drvs->rx_pause_frames = port_stats->rx_pause_frames; drvs->rx_crc_errors = port_stats->rx_crc_errors; drvs->rx_control_frames = port_stats->rx_control_frames; --- -1.7.10 - diff -Nru linux-3.2.46/debian/patches/features/all/be2net/0018-be2net-workaround-to-fix-a-bug-in-BE.patch linux-3.2.46/debian/patches/features/all/be2net/0018-be2net-workaround-to-fix-a-bug-in-BE.patch --- linux-3.2.46/debian/patches/features/all/be2net/0018-be2net-workaround-to-fix-a-bug-in-BE.patch 2013-02-24 03:52:39.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/be2net/0018-be2net-workaround-to-fix-a-bug-in-BE.patch 2013-07-26 19:21:16.000000000 +0000 @@ -12,11 +12,11 @@ drivers/net/ethernet/emulex/benet/be_main.c | 46 ++++++++++++++++++++++----- 1 file changed, 38 insertions(+), 8 deletions(-) -diff --git a/drivers/net/ethernet/emulex/benet/be_main.c b/drivers/net/ethernet/emulex/benet/be_main.c -index 0da3df0..f180f49 100644 ---- a/drivers/net/ethernet/emulex/benet/be_main.c -+++ b/drivers/net/ethernet/emulex/benet/be_main.c -@@ -552,11 +552,26 @@ static inline void wrb_fill(struct be_eth_wrb *wrb, u64 addr, int len) +Index: linux-3.2.46/drivers/net/ethernet/emulex/benet/be_main.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/emulex/benet/be_main.c 2013-07-26 19:21:14.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/emulex/benet/be_main.c 2013-07-26 19:21:15.000000000 +0000 +@@ -552,11 +552,26 @@ wrb->frag_len = len & ETH_WRB_FRAG_LEN_MASK; } @@ -45,7 +45,7 @@ memset(hdr, 0, sizeof(*hdr)); -@@ -587,12 +602,7 @@ static void wrb_fill_hdr(struct be_adapter *adapter, struct be_eth_hdr_wrb *hdr, +@@ -587,12 +602,7 @@ if (vlan_tx_tag_present(skb)) { AMAP_SET_BITS(struct amap_eth_hdr_wrb, vlan, hdr, 1); @@ -59,7 +59,7 @@ AMAP_SET_BITS(struct amap_eth_hdr_wrb, vlan_tag, hdr, vlan_tag); } -@@ -695,6 +705,25 @@ static netdev_tx_t be_xmit(struct sk_buff *skb, +@@ -695,6 +705,25 @@ u32 start = txq->head; bool dummy_wrb, stopped = false; @@ -85,7 +85,7 @@ wrb_cnt = wrb_cnt_for_skb(adapter, skb, &dummy_wrb); copied = make_tx_wrbs(adapter, txq, skb, wrb_cnt, dummy_wrb); -@@ -722,6 +751,7 @@ static netdev_tx_t be_xmit(struct sk_buff *skb, +@@ -723,6 +752,7 @@ txq->head = start; dev_kfree_skb_any(skb); } @@ -93,6 +93,3 @@ return NETDEV_TX_OK; } --- -1.7.10 - diff -Nru linux-3.2.46/debian/patches/features/all/be2net/0019-be2net-fix-ethtool-ringparam-reporting.patch linux-3.2.46/debian/patches/features/all/be2net/0019-be2net-fix-ethtool-ringparam-reporting.patch --- linux-3.2.46/debian/patches/features/all/be2net/0019-be2net-fix-ethtool-ringparam-reporting.patch 2013-02-24 03:52:39.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/be2net/0019-be2net-fix-ethtool-ringparam-reporting.patch 2013-07-26 19:21:17.000000000 +0000 @@ -16,11 +16,11 @@ drivers/net/ethernet/emulex/benet/be_ethtool.c | 11 ++++------- 1 file changed, 4 insertions(+), 7 deletions(-) -diff --git a/drivers/net/ethernet/emulex/benet/be_ethtool.c b/drivers/net/ethernet/emulex/benet/be_ethtool.c -index 575c783..6ba2dc6 100644 ---- a/drivers/net/ethernet/emulex/benet/be_ethtool.c -+++ b/drivers/net/ethernet/emulex/benet/be_ethtool.c -@@ -520,16 +520,13 @@ static int be_get_settings(struct net_device *netdev, struct ethtool_cmd *ecmd) +Index: linux-3.2.46/drivers/net/ethernet/emulex/benet/be_ethtool.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/emulex/benet/be_ethtool.c 2013-07-26 19:21:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/emulex/benet/be_ethtool.c 2013-07-26 19:21:16.000000000 +0000 +@@ -520,16 +520,13 @@ return 0; } @@ -41,6 +41,3 @@ } static void --- -1.7.10 - diff -Nru linux-3.2.46/debian/patches/features/all/be2net/0020-be2net-refactor-cleanup-vf-configuration-code.patch linux-3.2.46/debian/patches/features/all/be2net/0020-be2net-refactor-cleanup-vf-configuration-code.patch --- linux-3.2.46/debian/patches/features/all/be2net/0020-be2net-refactor-cleanup-vf-configuration-code.patch 2013-02-24 03:52:39.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/be2net/0020-be2net-refactor-cleanup-vf-configuration-code.patch 2013-07-26 19:21:19.000000000 +0000 @@ -20,11 +20,11 @@ drivers/net/ethernet/emulex/benet/be_main.c | 137 +++++++++++++-------------- 2 files changed, 80 insertions(+), 77 deletions(-) -diff --git a/drivers/net/ethernet/emulex/benet/be.h b/drivers/net/ethernet/emulex/benet/be.h -index 34f162d..a3588fb 100644 ---- a/drivers/net/ethernet/emulex/benet/be.h -+++ b/drivers/net/ethernet/emulex/benet/be.h -@@ -288,11 +288,11 @@ struct be_drv_stats { +Index: linux-3.2.46/drivers/net/ethernet/emulex/benet/be.h +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/emulex/benet/be.h 2013-07-26 19:20:56.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/emulex/benet/be.h 2013-07-26 19:21:18.000000000 +0000 +@@ -288,11 +288,11 @@ }; struct be_vf_cfg { @@ -41,7 +41,7 @@ }; struct be_adapter { -@@ -368,16 +368,20 @@ struct be_adapter { +@@ -368,16 +368,20 @@ u32 flash_status; struct completion flash_compl; @@ -65,11 +65,11 @@ /* BladeEngine Generation numbers */ #define BE_GEN2 2 -diff --git a/drivers/net/ethernet/emulex/benet/be_main.c b/drivers/net/ethernet/emulex/benet/be_main.c -index f180f49..cf83b33 100644 ---- a/drivers/net/ethernet/emulex/benet/be_main.c -+++ b/drivers/net/ethernet/emulex/benet/be_main.c -@@ -27,13 +27,14 @@ MODULE_DESCRIPTION(DRV_DESC " " DRV_VER); +Index: linux-3.2.46/drivers/net/ethernet/emulex/benet/be_main.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/emulex/benet/be_main.c 2013-07-26 19:21:15.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/emulex/benet/be_main.c 2013-07-26 19:21:18.000000000 +0000 +@@ -27,13 +27,14 @@ MODULE_AUTHOR("ServerEngines Corporation"); MODULE_LICENSE("GPL"); @@ -87,7 +87,7 @@ static DEFINE_PCI_DEVICE_TABLE(be_dev_ids) = { { PCI_DEVICE(BE_VENDOR_ID, BE_DEVICE_ID1) }, { PCI_DEVICE(BE_VENDOR_ID, BE_DEVICE_ID2) }, -@@ -779,15 +780,15 @@ static int be_change_mtu(struct net_device *netdev, int new_mtu) +@@ -780,15 +781,15 @@ */ static int be_vid_config(struct be_adapter *adapter, bool vf, u32 vf_num) { @@ -107,7 +107,7 @@ } /* No need to further configure vids if in promiscuous mode */ -@@ -873,31 +874,30 @@ done: +@@ -874,31 +875,30 @@ static int be_set_vf_mac(struct net_device *netdev, int vf, u8 *mac) { struct be_adapter *adapter = netdev_priv(netdev); @@ -128,12 +128,13 @@ - status = be_cmd_pmac_del(adapter, - adapter->vf_cfg[vf].vf_if_handle, - adapter->vf_cfg[vf].vf_pmac_id, vf + 1); -+ status = be_cmd_pmac_del(adapter, vf_cfg->if_handle, -+ vf_cfg->pmac_id, vf + 1); - +- - status = be_cmd_pmac_add(adapter, mac, - adapter->vf_cfg[vf].vf_if_handle, - &adapter->vf_cfg[vf].vf_pmac_id, vf + 1); ++ status = be_cmd_pmac_del(adapter, vf_cfg->if_handle, ++ vf_cfg->pmac_id, vf + 1); ++ + status = be_cmd_pmac_add(adapter, mac, vf_cfg->if_handle, + &vf_cfg->pmac_id, vf + 1); } @@ -147,7 +148,7 @@ return status; } -@@ -906,18 +906,19 @@ static int be_get_vf_config(struct net_device *netdev, int vf, +@@ -907,18 +907,19 @@ struct ifla_vf_info *vi) { struct be_adapter *adapter = netdev_priv(netdev); @@ -172,7 +173,7 @@ return 0; } -@@ -928,17 +929,17 @@ static int be_set_vf_vlan(struct net_device *netdev, +@@ -929,17 +930,17 @@ struct be_adapter *adapter = netdev_priv(netdev); int status = 0; @@ -194,7 +195,7 @@ adapter->vlans_added--; } -@@ -956,16 +957,16 @@ static int be_set_vf_tx_rate(struct net_device *netdev, +@@ -957,16 +958,16 @@ struct be_adapter *adapter = netdev_priv(netdev); int status = 0; @@ -214,7 +215,7 @@ status = be_cmd_set_qos(adapter, rate / 10, vf + 1); if (status) -@@ -1681,8 +1682,7 @@ static void be_tx_queues_destroy(struct be_adapter *adapter) +@@ -1682,8 +1683,7 @@ static int be_num_txqs_want(struct be_adapter *adapter) { @@ -224,7 +225,7 @@ lancer_chip(adapter) || !be_physfn(adapter) || adapter->generation == BE_GEN2) return 1; -@@ -1764,8 +1764,8 @@ static void be_rx_queues_destroy(struct be_adapter *adapter) +@@ -1765,8 +1765,8 @@ static u32 be_num_rxqs_want(struct be_adapter *adapter) { if ((adapter->function_caps & BE_FUNCTION_CAPS_RSS) && @@ -235,7 +236,7 @@ return 1 + MAX_RSS_QS; /* one default non-RSS queue */ } else { dev_warn(&adapter->pdev->dev, -@@ -2112,27 +2112,28 @@ done: +@@ -2113,27 +2113,28 @@ static int be_sriov_enable(struct be_adapter *adapter) { be_check_sriov_fn_type(adapter); @@ -274,7 +275,7 @@ adapter->vf_cfg = kcalloc(num_vfs, sizeof(struct be_vf_cfg), GFP_KERNEL); -@@ -2147,10 +2148,10 @@ static int be_sriov_enable(struct be_adapter *adapter) +@@ -2148,10 +2149,10 @@ static void be_sriov_disable(struct be_adapter *adapter) { #ifdef CONFIG_PCI_IOV @@ -287,7 +288,7 @@ } #endif } -@@ -2462,24 +2463,24 @@ static inline int be_vf_eth_addr_config(struct be_adapter *adapter) +@@ -2463,24 +2464,24 @@ u32 vf; int status = 0; u8 mac[ETH_ALEN]; @@ -317,7 +318,7 @@ mac[5] += 1; } -@@ -2488,25 +2489,23 @@ static inline int be_vf_eth_addr_config(struct be_adapter *adapter) +@@ -2489,25 +2490,23 @@ static void be_vf_clear(struct be_adapter *adapter) { @@ -350,7 +351,7 @@ be_vf_clear(adapter); be_cmd_if_destroy(adapter, adapter->if_handle, 0); -@@ -2522,16 +2521,18 @@ static int be_clear(struct be_adapter *adapter) +@@ -2523,16 +2522,18 @@ static void be_vf_setup_init(struct be_adapter *adapter) { @@ -372,7 +373,7 @@ u32 cap_flags, en_flags, vf; u16 lnk_speed; int status; -@@ -2540,11 +2541,9 @@ static int be_vf_setup(struct be_adapter *adapter) +@@ -2541,11 +2542,9 @@ cap_flags = en_flags = BE_IF_FLAGS_UNTAGGED | BE_IF_FLAGS_BROADCAST | BE_IF_FLAGS_MULTICAST; @@ -386,7 +387,7 @@ if (status) goto err; } -@@ -2553,12 +2552,12 @@ static int be_vf_setup(struct be_adapter *adapter) +@@ -2554,12 +2553,12 @@ if (status) goto err; @@ -402,7 +403,7 @@ } return 0; err: -@@ -2686,7 +2685,7 @@ static int be_setup(struct be_adapter *adapter) +@@ -2687,7 +2686,7 @@ pcie_set_readrq(adapter->pdev, 4096); @@ -411,6 +412,3 @@ status = be_vf_setup(adapter); if (status) goto err; --- -1.7.10 - diff -Nru linux-3.2.46/debian/patches/features/all/be2net/0021-be2net-Add-support-for-Skyhawk-cards.patch linux-3.2.46/debian/patches/features/all/be2net/0021-be2net-Add-support-for-Skyhawk-cards.patch --- linux-3.2.46/debian/patches/features/all/be2net/0021-be2net-Add-support-for-Skyhawk-cards.patch 2013-02-24 03:52:39.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/be2net/0021-be2net-Add-support-for-Skyhawk-cards.patch 2013-07-26 19:21:20.000000000 +0000 @@ -11,10 +11,10 @@ drivers/net/ethernet/emulex/benet/be_main.c | 2 ++ 2 files changed, 6 insertions(+) -diff --git a/drivers/net/ethernet/emulex/benet/be.h b/drivers/net/ethernet/emulex/benet/be.h -index a3588fb..995198d 100644 ---- a/drivers/net/ethernet/emulex/benet/be.h -+++ b/drivers/net/ethernet/emulex/benet/be.h +Index: linux-3.2.46/drivers/net/ethernet/emulex/benet/be.h +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/emulex/benet/be.h 2013-07-26 19:21:18.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/emulex/benet/be.h 2013-07-26 19:21:19.000000000 +0000 @@ -40,6 +40,7 @@ #define OC_NAME "Emulex OneConnect 10Gbps NIC" #define OC_NAME_BE OC_NAME "(be3)" @@ -31,7 +31,7 @@ static inline char *nic_name(struct pci_dev *pdev) { -@@ -63,6 +65,8 @@ static inline char *nic_name(struct pci_dev *pdev) +@@ -63,6 +65,8 @@ return OC_NAME_LANCER; case BE_DEVICE_ID2: return BE3_NAME; @@ -40,11 +40,11 @@ default: return BE_NAME; } -diff --git a/drivers/net/ethernet/emulex/benet/be_main.c b/drivers/net/ethernet/emulex/benet/be_main.c -index cf83b33..3ed2987 100644 ---- a/drivers/net/ethernet/emulex/benet/be_main.c -+++ b/drivers/net/ethernet/emulex/benet/be_main.c -@@ -42,6 +42,7 @@ static DEFINE_PCI_DEVICE_TABLE(be_dev_ids) = { +Index: linux-3.2.46/drivers/net/ethernet/emulex/benet/be_main.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/emulex/benet/be_main.c 2013-07-26 19:21:18.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/emulex/benet/be_main.c 2013-07-26 19:21:19.000000000 +0000 +@@ -42,6 +42,7 @@ { PCI_DEVICE(BE_VENDOR_ID, OC_DEVICE_ID2) }, { PCI_DEVICE(EMULEX_VENDOR_ID, OC_DEVICE_ID3)}, { PCI_DEVICE(EMULEX_VENDOR_ID, OC_DEVICE_ID4)}, @@ -52,7 +52,7 @@ { 0 } }; MODULE_DEVICE_TABLE(pci, be_dev_ids); -@@ -3308,6 +3309,7 @@ static int be_dev_family_check(struct be_adapter *adapter) +@@ -3309,6 +3310,7 @@ break; case BE_DEVICE_ID2: case OC_DEVICE_ID2: @@ -60,6 +60,3 @@ adapter->generation = BE_GEN3; break; case OC_DEVICE_ID3: --- -1.7.10 - diff -Nru linux-3.2.46/debian/patches/features/all/be2net/0022-be2net-Fix-INTx-processing-for-Lancer.patch linux-3.2.46/debian/patches/features/all/be2net/0022-be2net-Fix-INTx-processing-for-Lancer.patch --- linux-3.2.46/debian/patches/features/all/be2net/0022-be2net-Fix-INTx-processing-for-Lancer.patch 2013-02-24 03:52:39.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/be2net/0022-be2net-Fix-INTx-processing-for-Lancer.patch 2013-07-26 19:21:21.000000000 +0000 @@ -15,11 +15,11 @@ drivers/net/ethernet/emulex/benet/be_main.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) -diff --git a/drivers/net/ethernet/emulex/benet/be_main.c b/drivers/net/ethernet/emulex/benet/be_main.c -index 3ed2987..a185e61 100644 ---- a/drivers/net/ethernet/emulex/benet/be_main.c -+++ b/drivers/net/ethernet/emulex/benet/be_main.c -@@ -1966,6 +1966,7 @@ static int be_poll_tx_mcc(struct napi_struct *napi, int budget) +Index: linux-3.2.46/drivers/net/ethernet/emulex/benet/be_main.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/emulex/benet/be_main.c 2013-07-26 19:21:19.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/emulex/benet/be_main.c 2013-07-26 19:21:20.000000000 +0000 +@@ -1967,6 +1967,7 @@ struct be_eq_obj *tx_eq = container_of(napi, struct be_eq_obj, napi); struct be_adapter *adapter = container_of(tx_eq, struct be_adapter, tx_eq); @@ -27,7 +27,7 @@ struct be_tx_obj *txo; struct be_eth_tx_compl *txcp; int tx_compl, mcc_compl, status = 0; -@@ -2002,12 +2003,19 @@ static int be_poll_tx_mcc(struct napi_struct *napi, int budget) +@@ -2003,12 +2004,19 @@ mcc_compl = be_process_mcc(adapter, &status); if (mcc_compl) { @@ -48,6 +48,3 @@ be_eq_notify(adapter, tx_eq->q.id, true, false, 0); adapter->drv_stats.tx_events++; return 1; --- -1.7.10 - diff -Nru linux-3.2.46/debian/patches/features/all/be2net/0023-be2net-fix-be_vlan_add-rem_vid.patch linux-3.2.46/debian/patches/features/all/be2net/0023-be2net-fix-be_vlan_add-rem_vid.patch --- linux-3.2.46/debian/patches/features/all/be2net/0023-be2net-fix-be_vlan_add-rem_vid.patch 2013-02-24 03:52:39.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/be2net/0023-be2net-fix-be_vlan_add-rem_vid.patch 2013-07-26 19:21:22.000000000 +0000 @@ -13,11 +13,11 @@ drivers/net/ethernet/emulex/benet/be_main.c | 19 ++++++++++++++----- 1 file changed, 14 insertions(+), 5 deletions(-) -diff --git a/drivers/net/ethernet/emulex/benet/be_main.c b/drivers/net/ethernet/emulex/benet/be_main.c -index a185e61..acef082 100644 ---- a/drivers/net/ethernet/emulex/benet/be_main.c -+++ b/drivers/net/ethernet/emulex/benet/be_main.c -@@ -817,28 +817,37 @@ static int be_vid_config(struct be_adapter *adapter, bool vf, u32 vf_num) +Index: linux-3.2.46/drivers/net/ethernet/emulex/benet/be_main.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/emulex/benet/be_main.c 2013-07-26 19:21:20.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/emulex/benet/be_main.c 2013-07-26 19:21:22.000000000 +0000 +@@ -818,28 +818,37 @@ static void be_vlan_add_vid(struct net_device *netdev, u16 vid) { struct be_adapter *adapter = netdev_priv(netdev); @@ -60,6 +60,3 @@ } static void be_set_rx_mode(struct net_device *netdev) --- -1.7.10 - diff -Nru linux-3.2.46/debian/patches/features/all/be2net/0024-be2net-fix-range-check-for-set_qos-for-a-VF.patch linux-3.2.46/debian/patches/features/all/be2net/0024-be2net-fix-range-check-for-set_qos-for-a-VF.patch --- linux-3.2.46/debian/patches/features/all/be2net/0024-be2net-fix-range-check-for-set_qos-for-a-VF.patch 2013-02-24 03:52:39.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/be2net/0024-be2net-fix-range-check-for-set_qos-for-a-VF.patch 2013-07-26 19:21:24.000000000 +0000 @@ -10,11 +10,11 @@ drivers/net/ethernet/emulex/benet/be_main.c | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) -diff --git a/drivers/net/ethernet/emulex/benet/be_main.c b/drivers/net/ethernet/emulex/benet/be_main.c -index acef082..cd7f5e3 100644 ---- a/drivers/net/ethernet/emulex/benet/be_main.c -+++ b/drivers/net/ethernet/emulex/benet/be_main.c -@@ -970,18 +970,22 @@ static int be_set_vf_tx_rate(struct net_device *netdev, +Index: linux-3.2.46/drivers/net/ethernet/emulex/benet/be_main.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/emulex/benet/be_main.c 2013-07-26 19:21:22.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/emulex/benet/be_main.c 2013-07-26 19:21:23.000000000 +0000 +@@ -971,18 +971,22 @@ if (!sriov_enabled(adapter)) return -EPERM; @@ -42,6 +42,3 @@ return status; } --- -1.7.10 - diff -Nru linux-3.2.46/debian/patches/features/all/be2net/0025-be2net-query-link-status-in-be_open.patch linux-3.2.46/debian/patches/features/all/be2net/0025-be2net-query-link-status-in-be_open.patch --- linux-3.2.46/debian/patches/features/all/be2net/0025-be2net-query-link-status-in-be_open.patch 2013-02-24 03:52:39.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/be2net/0025-be2net-query-link-status-in-be_open.patch 2013-07-26 19:21:25.000000000 +0000 @@ -21,11 +21,11 @@ drivers/net/ethernet/emulex/benet/be_main.c | 24 +++++++++++++++--------- 5 files changed, 45 insertions(+), 19 deletions(-) -diff --git a/drivers/net/ethernet/emulex/benet/be.h b/drivers/net/ethernet/emulex/benet/be.h -index 995198d..cbdec25 100644 ---- a/drivers/net/ethernet/emulex/benet/be.h -+++ b/drivers/net/ethernet/emulex/benet/be.h -@@ -299,6 +299,8 @@ struct be_vf_cfg { +Index: linux-3.2.46/drivers/net/ethernet/emulex/benet/be.h +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/emulex/benet/be.h 2013-07-26 19:21:19.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/emulex/benet/be.h 2013-07-26 19:21:24.000000000 +0000 +@@ -299,6 +299,8 @@ u32 tx_rate; }; @@ -34,7 +34,7 @@ struct be_adapter { struct pci_dev *pdev; struct net_device *netdev; -@@ -347,6 +349,7 @@ struct be_adapter { +@@ -347,6 +349,7 @@ struct delayed_work work; u16 work_counter; @@ -42,7 +42,7 @@ /* Ethtool knobs and info */ char fw_ver[FW_VER_LEN]; int if_handle; /* Used to configure filtering */ -@@ -538,7 +541,7 @@ static inline bool be_error(struct be_adapter *adapter) +@@ -538,7 +541,7 @@ extern void be_cq_notify(struct be_adapter *adapter, u16 qid, bool arm, u16 num_popped); @@ -51,11 +51,11 @@ extern void be_parse_stats(struct be_adapter *adapter); extern int be_load_fw(struct be_adapter *adapter, u8 *func); #endif /* BE_H */ -diff --git a/drivers/net/ethernet/emulex/benet/be_cmds.c b/drivers/net/ethernet/emulex/benet/be_cmds.c -index 62868ea..0fcb456 100644 ---- a/drivers/net/ethernet/emulex/benet/be_cmds.c -+++ b/drivers/net/ethernet/emulex/benet/be_cmds.c -@@ -125,7 +125,14 @@ done: +Index: linux-3.2.46/drivers/net/ethernet/emulex/benet/be_cmds.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/emulex/benet/be_cmds.c 2013-07-26 19:21:10.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/emulex/benet/be_cmds.c 2013-07-26 19:21:24.000000000 +0000 +@@ -125,7 +125,14 @@ static void be_async_link_state_process(struct be_adapter *adapter, struct be_async_event_link_state *evt) { @@ -71,7 +71,7 @@ } /* Grp5 CoS Priority evt */ -@@ -1232,7 +1239,7 @@ err: +@@ -1232,7 +1239,7 @@ /* Uses synchronous mcc */ int be_cmd_link_status_query(struct be_adapter *adapter, u8 *mac_speed, @@ -80,7 +80,7 @@ { struct be_mcc_wrb *wrb; struct be_cmd_req_link_status *req; -@@ -1240,6 +1247,9 @@ int be_cmd_link_status_query(struct be_adapter *adapter, u8 *mac_speed, +@@ -1240,6 +1247,9 @@ spin_lock_bh(&adapter->mcc_lock); @@ -90,7 +90,7 @@ wrb = wrb_from_mccq(adapter); if (!wrb) { status = -EBUSY; -@@ -1247,7 +1257,7 @@ int be_cmd_link_status_query(struct be_adapter *adapter, u8 *mac_speed, +@@ -1247,7 +1257,7 @@ } req = embedded_payload(wrb); @@ -99,7 +99,7 @@ req->hdr.version = 1; be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, -@@ -1257,10 +1267,13 @@ int be_cmd_link_status_query(struct be_adapter *adapter, u8 *mac_speed, +@@ -1257,10 +1267,13 @@ if (!status) { struct be_cmd_resp_link_status *resp = embedded_payload(wrb); if (resp->mac_speed != PHY_LINK_SPEED_ZERO) { @@ -114,11 +114,11 @@ } err: -diff --git a/drivers/net/ethernet/emulex/benet/be_cmds.h b/drivers/net/ethernet/emulex/benet/be_cmds.h -index 0b694c6..dca8924 100644 ---- a/drivers/net/ethernet/emulex/benet/be_cmds.h -+++ b/drivers/net/ethernet/emulex/benet/be_cmds.h -@@ -960,7 +960,8 @@ struct be_cmd_resp_link_status { +Index: linux-3.2.46/drivers/net/ethernet/emulex/benet/be_cmds.h +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/emulex/benet/be_cmds.h 2013-07-26 19:21:06.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/emulex/benet/be_cmds.h 2013-07-26 19:21:24.000000000 +0000 +@@ -960,7 +960,8 @@ u8 mgmt_mac_duplex; u8 mgmt_mac_speed; u16 link_speed; @@ -128,7 +128,7 @@ } __packed; /******************** Port Identification ***************************/ -@@ -1507,8 +1508,8 @@ extern int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q, +@@ -1507,8 +1508,8 @@ int type); extern int be_cmd_rxq_destroy(struct be_adapter *adapter, struct be_queue_info *q); @@ -139,11 +139,11 @@ extern int be_cmd_reset(struct be_adapter *adapter); extern int be_cmd_get_stats(struct be_adapter *adapter, struct be_dma_mem *nonemb_cmd); -diff --git a/drivers/net/ethernet/emulex/benet/be_ethtool.c b/drivers/net/ethernet/emulex/benet/be_ethtool.c -index 6ba2dc6..6db6b6a 100644 ---- a/drivers/net/ethernet/emulex/benet/be_ethtool.c -+++ b/drivers/net/ethernet/emulex/benet/be_ethtool.c -@@ -429,11 +429,14 @@ static int be_get_settings(struct net_device *netdev, struct ethtool_cmd *ecmd) +Index: linux-3.2.46/drivers/net/ethernet/emulex/benet/be_ethtool.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/emulex/benet/be_ethtool.c 2013-07-26 19:21:16.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/emulex/benet/be_ethtool.c 2013-07-26 19:21:24.000000000 +0000 +@@ -429,11 +429,14 @@ struct be_phy_info phy_info; u8 mac_speed = 0; u16 link_speed = 0; @@ -159,7 +159,7 @@ /* link_speed is in units of 10 Mbps */ if (link_speed) { -@@ -700,7 +703,7 @@ be_self_test(struct net_device *netdev, struct ethtool_test *test, u64 *data) +@@ -700,7 +703,7 @@ } if (be_cmd_link_status_query(adapter, &mac_speed, @@ -168,11 +168,11 @@ test->flags |= ETH_TEST_FL_FAILED; data[4] = -1; } else if (!mac_speed) { -diff --git a/drivers/net/ethernet/emulex/benet/be_main.c b/drivers/net/ethernet/emulex/benet/be_main.c -index cd7f5e3..42ee4c9 100644 ---- a/drivers/net/ethernet/emulex/benet/be_main.c -+++ b/drivers/net/ethernet/emulex/benet/be_main.c -@@ -496,19 +496,19 @@ static struct rtnl_link_stats64 *be_get_stats64(struct net_device *netdev, +Index: linux-3.2.46/drivers/net/ethernet/emulex/benet/be_main.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/emulex/benet/be_main.c 2013-07-26 19:21:23.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/emulex/benet/be_main.c 2013-07-26 19:21:24.000000000 +0000 +@@ -496,19 +496,19 @@ return stats; } @@ -200,7 +200,7 @@ } static void be_tx_stats_update(struct be_tx_obj *txo, -@@ -2406,6 +2406,7 @@ static int be_open(struct net_device *netdev) +@@ -2407,6 +2407,7 @@ struct be_adapter *adapter = netdev_priv(netdev); struct be_eq_obj *tx_eq = &adapter->tx_eq; struct be_rx_obj *rxo; @@ -208,7 +208,7 @@ int status, i; status = be_rx_queues_setup(adapter); -@@ -2429,6 +2430,11 @@ static int be_open(struct net_device *netdev) +@@ -2430,6 +2431,11 @@ /* Now that interrupts are on we can process async mcc */ be_async_mcc_enable(adapter); @@ -220,7 +220,7 @@ return 0; err: be_close(adapter->netdev); -@@ -2576,7 +2582,7 @@ static int be_vf_setup(struct be_adapter *adapter) +@@ -2577,7 +2583,7 @@ for_all_vfs(adapter, vf_cfg, vf) { status = be_cmd_link_status_query(adapter, NULL, &lnk_speed, @@ -229,6 +229,3 @@ if (status) goto err; vf_cfg->tx_rate = lnk_speed * 10; --- -1.7.10 - diff -Nru linux-3.2.46/debian/patches/features/all/be2net/0026-netdev-make-net_device_ops-const.patch linux-3.2.46/debian/patches/features/all/be2net/0026-netdev-make-net_device_ops-const.patch --- linux-3.2.46/debian/patches/features/all/be2net/0026-netdev-make-net_device_ops-const.patch 2013-02-24 03:52:39.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/be2net/0026-netdev-make-net_device_ops-const.patch 2013-07-26 19:21:27.000000000 +0000 @@ -13,11 +13,11 @@ drivers/net/ethernet/emulex/benet/be_main.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -diff --git a/drivers/net/ethernet/emulex/benet/be_main.c b/drivers/net/ethernet/emulex/benet/be_main.c -index 42ee4c9..804ab7e 100644 ---- a/drivers/net/ethernet/emulex/benet/be_main.c -+++ b/drivers/net/ethernet/emulex/benet/be_main.c -@@ -3072,7 +3072,7 @@ fw_exit: +Index: linux-3.2.46/drivers/net/ethernet/emulex/benet/be_main.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/emulex/benet/be_main.c 2013-07-26 19:21:24.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/emulex/benet/be_main.c 2013-07-26 19:21:26.000000000 +0000 +@@ -3073,7 +3073,7 @@ return status; } @@ -26,6 +26,3 @@ .ndo_open = be_open, .ndo_stop = be_close, .ndo_start_xmit = be_xmit, --- -1.7.10 - diff -Nru linux-3.2.46/debian/patches/features/all/be2net/0027-be2net-create-RSS-rings-even-in-multi-channel-config.patch linux-3.2.46/debian/patches/features/all/be2net/0027-be2net-create-RSS-rings-even-in-multi-channel-config.patch --- linux-3.2.46/debian/patches/features/all/be2net/0027-be2net-create-RSS-rings-even-in-multi-channel-config.patch 2013-02-24 03:52:39.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/be2net/0027-be2net-create-RSS-rings-even-in-multi-channel-config.patch 2013-07-26 19:21:28.000000000 +0000 @@ -17,11 +17,11 @@ drivers/net/ethernet/emulex/benet/be_main.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) -diff --git a/drivers/net/ethernet/emulex/benet/be_main.c b/drivers/net/ethernet/emulex/benet/be_main.c -index 804ab7e..adfd66a 100644 ---- a/drivers/net/ethernet/emulex/benet/be_main.c -+++ b/drivers/net/ethernet/emulex/benet/be_main.c -@@ -1778,8 +1778,7 @@ static void be_rx_queues_destroy(struct be_adapter *adapter) +Index: linux-3.2.46/drivers/net/ethernet/emulex/benet/be_main.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/emulex/benet/be_main.c 2013-07-26 19:21:26.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/emulex/benet/be_main.c 2013-07-26 19:21:27.000000000 +0000 +@@ -1779,8 +1779,7 @@ static u32 be_num_rxqs_want(struct be_adapter *adapter) { if ((adapter->function_caps & BE_FUNCTION_CAPS_RSS) && @@ -31,6 +31,3 @@ return 1 + MAX_RSS_QS; /* one default non-RSS queue */ } else { dev_warn(&adapter->pdev->dev, --- -1.7.10 - diff -Nru linux-3.2.46/debian/patches/features/all/be2net/0028-be2net-allocate-more-headroom-in-incoming-skbs.patch linux-3.2.46/debian/patches/features/all/be2net/0028-be2net-allocate-more-headroom-in-incoming-skbs.patch --- linux-3.2.46/debian/patches/features/all/be2net/0028-be2net-allocate-more-headroom-in-incoming-skbs.patch 2013-02-24 03:52:39.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/be2net/0028-be2net-allocate-more-headroom-in-incoming-skbs.patch 2013-07-26 19:21:29.000000000 +0000 @@ -25,11 +25,11 @@ drivers/net/ethernet/emulex/benet/be_main.c | 2 +- 2 files changed, 4 insertions(+), 1 deletion(-) -diff --git a/drivers/net/ethernet/emulex/benet/be.h b/drivers/net/ethernet/emulex/benet/be.h -index cbdec25..453d486 100644 ---- a/drivers/net/ethernet/emulex/benet/be.h -+++ b/drivers/net/ethernet/emulex/benet/be.h -@@ -74,6 +74,9 @@ static inline char *nic_name(struct pci_dev *pdev) +Index: linux-3.2.46/drivers/net/ethernet/emulex/benet/be.h +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/emulex/benet/be.h 2013-07-26 19:21:24.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/emulex/benet/be.h 2013-07-26 19:21:28.000000000 +0000 +@@ -74,6 +74,9 @@ /* Number of bytes of an RX frame that are copied to skb->data */ #define BE_HDR_LEN ((u16) 64) @@ -39,11 +39,11 @@ #define BE_MAX_JUMBO_FRAME_SIZE 9018 #define BE_MIN_MTU 256 -diff --git a/drivers/net/ethernet/emulex/benet/be_main.c b/drivers/net/ethernet/emulex/benet/be_main.c -index adfd66a..860c461 100644 ---- a/drivers/net/ethernet/emulex/benet/be_main.c -+++ b/drivers/net/ethernet/emulex/benet/be_main.c -@@ -1181,7 +1181,7 @@ static void be_rx_compl_process(struct be_adapter *adapter, +Index: linux-3.2.46/drivers/net/ethernet/emulex/benet/be_main.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/emulex/benet/be_main.c 2013-07-26 19:21:27.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/emulex/benet/be_main.c 2013-07-26 19:21:28.000000000 +0000 +@@ -1182,7 +1182,7 @@ struct net_device *netdev = adapter->netdev; struct sk_buff *skb; @@ -52,6 +52,3 @@ if (unlikely(!skb)) { rx_stats(rxo)->rx_drops_no_skbs++; be_rx_compl_discard(adapter, rxo, rxcp); --- -1.7.10 - diff -Nru linux-3.2.46/debian/patches/features/all/be2net/0029-be2net-add-descriptions-for-stat-counters-reported-v.patch linux-3.2.46/debian/patches/features/all/be2net/0029-be2net-add-descriptions-for-stat-counters-reported-v.patch --- linux-3.2.46/debian/patches/features/all/be2net/0029-be2net-add-descriptions-for-stat-counters-reported-v.patch 2013-02-24 03:52:39.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/be2net/0029-be2net-add-descriptions-for-stat-counters-reported-v.patch 2013-07-26 19:21:31.000000000 +0000 @@ -20,11 +20,11 @@ drivers/net/ethernet/emulex/benet/be_main.c | 15 +++--- 4 files changed, 74 insertions(+), 18 deletions(-) -diff --git a/drivers/net/ethernet/emulex/benet/be.h b/drivers/net/ethernet/emulex/benet/be.h -index 453d486..74aa148 100644 ---- a/drivers/net/ethernet/emulex/benet/be.h -+++ b/drivers/net/ethernet/emulex/benet/be.h -@@ -265,7 +265,6 @@ struct be_drv_stats { +Index: linux-3.2.46/drivers/net/ethernet/emulex/benet/be.h +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/emulex/benet/be.h 2013-07-26 19:21:28.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/emulex/benet/be.h 2013-07-26 19:21:30.000000000 +0000 +@@ -265,7 +265,6 @@ u32 rx_drops_no_erx_descr; u32 rx_drops_no_tpre_descr; u32 rx_drops_too_many_frags; @@ -32,7 +32,7 @@ u32 forwarded_packets; u32 rx_drops_mtu; u32 rx_crc_errors; -@@ -276,7 +275,7 @@ struct be_drv_stats { +@@ -276,7 +275,7 @@ u32 rx_in_range_errors; u32 rx_out_range_errors; u32 rx_frame_too_long; @@ -41,11 +41,11 @@ u32 rx_dropped_too_small; u32 rx_dropped_too_short; u32 rx_dropped_header_too_small; -diff --git a/drivers/net/ethernet/emulex/benet/be_cmds.h b/drivers/net/ethernet/emulex/benet/be_cmds.h -index dca8924..bbd012b 100644 ---- a/drivers/net/ethernet/emulex/benet/be_cmds.h -+++ b/drivers/net/ethernet/emulex/benet/be_cmds.h -@@ -592,8 +592,8 @@ struct be_port_rxf_stats_v0 { +Index: linux-3.2.46/drivers/net/ethernet/emulex/benet/be_cmds.h +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/emulex/benet/be_cmds.h 2013-07-26 19:21:24.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/emulex/benet/be_cmds.h 2013-07-26 19:21:30.000000000 +0000 +@@ -592,8 +592,8 @@ u32 rx_in_range_errors; /* dword 10*/ u32 rx_out_range_errors; /* dword 11*/ u32 rx_frame_too_long; /* dword 12*/ @@ -56,7 +56,7 @@ u32 rx_dropped_too_small; /* dword 15*/ u32 rx_dropped_too_short; /* dword 16*/ u32 rx_dropped_header_too_small; /* dword 17*/ -@@ -799,8 +799,8 @@ struct lancer_pport_stats { +@@ -799,8 +799,8 @@ u32 rx_control_frames_unknown_opcode_hi; u32 rx_in_range_errors; u32 rx_out_of_range_errors; @@ -67,7 +67,7 @@ u32 rx_dropped_too_small; u32 rx_dropped_too_short; u32 rx_dropped_header_too_small; -@@ -1384,7 +1384,7 @@ struct be_port_rxf_stats_v1 { +@@ -1384,7 +1384,7 @@ u32 rx_in_range_errors; u32 rx_out_range_errors; u32 rx_frame_too_long; @@ -76,11 +76,11 @@ u32 rx_dropped_too_small; u32 rx_dropped_too_short; u32 rx_dropped_header_too_small; -diff --git a/drivers/net/ethernet/emulex/benet/be_ethtool.c b/drivers/net/ethernet/emulex/benet/be_ethtool.c -index 6db6b6a..0a5ee22 100644 ---- a/drivers/net/ethernet/emulex/benet/be_ethtool.c -+++ b/drivers/net/ethernet/emulex/benet/be_ethtool.c -@@ -42,15 +42,42 @@ static const struct be_ethtool_stat et_stats[] = { +Index: linux-3.2.46/drivers/net/ethernet/emulex/benet/be_ethtool.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/emulex/benet/be_ethtool.c 2013-07-26 19:21:24.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/emulex/benet/be_ethtool.c 2013-07-26 19:21:30.000000000 +0000 +@@ -42,15 +42,42 @@ {DRVSTAT_INFO(rx_alignment_symbol_errors)}, {DRVSTAT_INFO(rx_pause_frames)}, {DRVSTAT_INFO(rx_control_frames)}, @@ -124,7 +124,7 @@ {DRVSTAT_INFO(rxpp_fifo_overflow_drop)}, {DRVSTAT_INFO(rx_input_fifo_overflow_drop)}, {DRVSTAT_INFO(rx_ip_checksum_errs)}, -@@ -59,16 +86,35 @@ static const struct be_ethtool_stat et_stats[] = { +@@ -59,16 +86,35 @@ {DRVSTAT_INFO(tx_pauseframes)}, {DRVSTAT_INFO(tx_controlframes)}, {DRVSTAT_INFO(rx_priority_pause_frames)}, @@ -162,7 +162,7 @@ {DRVSTAT_INFO(eth_red_drops)}, {DRVSTAT_INFO(be_on_die_temperature)} }; -@@ -84,8 +130,15 @@ static const struct be_ethtool_stat et_rx_stats[] = { +@@ -84,8 +130,15 @@ {DRVSTAT_RX_INFO(rx_events)}, {DRVSTAT_RX_INFO(rx_compl)}, {DRVSTAT_RX_INFO(rx_mcast_pkts)}, @@ -178,7 +178,7 @@ {DRVSTAT_RX_INFO(rx_drops_no_frags)} }; #define ETHTOOL_RXSTATS_NUM (ARRAY_SIZE(et_rx_stats)) -@@ -97,9 +150,14 @@ static const struct be_ethtool_stat et_tx_stats[] = { +@@ -97,9 +150,14 @@ {DRVSTAT_TX_INFO(tx_compl)}, /* If moving this member see above note */ {DRVSTAT_TX_INFO(tx_bytes)}, {DRVSTAT_TX_INFO(tx_pkts)}, @@ -193,11 +193,11 @@ {DRVSTAT_TX_INFO(tx_stops)} }; #define ETHTOOL_TXSTATS_NUM (ARRAY_SIZE(et_tx_stats)) -diff --git a/drivers/net/ethernet/emulex/benet/be_main.c b/drivers/net/ethernet/emulex/benet/be_main.c -index 860c461..d1536e2 100644 ---- a/drivers/net/ethernet/emulex/benet/be_main.c -+++ b/drivers/net/ethernet/emulex/benet/be_main.c -@@ -286,7 +286,9 @@ static void populate_be2_stats(struct be_adapter *adapter) +Index: linux-3.2.46/drivers/net/ethernet/emulex/benet/be_main.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/emulex/benet/be_main.c 2013-07-26 19:21:28.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/emulex/benet/be_main.c 2013-07-26 19:21:30.000000000 +0000 +@@ -286,7 +286,9 @@ drvs->rx_input_fifo_overflow_drop = port_stats->rx_input_fifo_overflow; drvs->rx_dropped_header_too_small = port_stats->rx_dropped_header_too_small; @@ -208,7 +208,7 @@ drvs->rx_alignment_symbol_errors = port_stats->rx_alignment_symbol_errors; -@@ -298,9 +300,7 @@ static void populate_be2_stats(struct be_adapter *adapter) +@@ -298,9 +300,7 @@ else drvs->jabber_events = rxf_stats->port0_jabber_events; drvs->rx_drops_no_pbuf = rxf_stats->rx_drops_no_pbuf; @@ -218,7 +218,7 @@ drvs->forwarded_packets = rxf_stats->forwarded_packets; drvs->rx_drops_mtu = rxf_stats->rx_drops_mtu; drvs->rx_drops_no_tpre_descr = rxf_stats->rx_drops_no_tpre_descr; -@@ -337,7 +337,7 @@ static void populate_be3_stats(struct be_adapter *adapter) +@@ -337,7 +337,7 @@ port_stats->rx_dropped_header_too_small; drvs->rx_input_fifo_overflow_drop = port_stats->rx_input_fifo_overflow_drop; @@ -227,7 +227,7 @@ drvs->rx_alignment_symbol_errors = port_stats->rx_alignment_symbol_errors; drvs->rxpp_fifo_overflow_drop = port_stats->rxpp_fifo_overflow_drop; -@@ -345,9 +345,7 @@ static void populate_be3_stats(struct be_adapter *adapter) +@@ -345,9 +345,7 @@ drvs->tx_controlframes = port_stats->tx_controlframes; drvs->jabber_events = port_stats->jabber_events; drvs->rx_drops_no_pbuf = rxf_stats->rx_drops_no_pbuf; @@ -237,7 +237,7 @@ drvs->forwarded_packets = rxf_stats->forwarded_packets; drvs->rx_drops_mtu = rxf_stats->rx_drops_mtu; drvs->rx_drops_no_tpre_descr = rxf_stats->rx_drops_no_tpre_descr; -@@ -380,13 +378,14 @@ static void populate_lancer_stats(struct be_adapter *adapter) +@@ -380,13 +378,14 @@ drvs->rx_dropped_header_too_small = pport_stats->rx_dropped_header_too_small; drvs->rx_input_fifo_overflow_drop = pport_stats->rx_fifo_overflow; @@ -254,6 +254,3 @@ drvs->forwarded_packets = pport_stats->num_forwards_lo; drvs->rx_drops_mtu = pport_stats->rx_drops_mtu_lo; drvs->rx_drops_too_many_frags = --- -1.7.10 - diff -Nru linux-3.2.46/debian/patches/features/all/be2net/0030-be2net-Fix-link-status-query-command.patch linux-3.2.46/debian/patches/features/all/be2net/0030-be2net-Fix-link-status-query-command.patch --- linux-3.2.46/debian/patches/features/all/be2net/0030-be2net-Fix-link-status-query-command.patch 2013-02-24 03:52:39.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/be2net/0030-be2net-Fix-link-status-query-command.patch 2013-07-26 19:21:32.000000000 +0000 @@ -14,11 +14,11 @@ drivers/net/ethernet/emulex/benet/be_cmds.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) -diff --git a/drivers/net/ethernet/emulex/benet/be_cmds.c b/drivers/net/ethernet/emulex/benet/be_cmds.c -index 0fcb456..dd6e8e2 100644 ---- a/drivers/net/ethernet/emulex/benet/be_cmds.c -+++ b/drivers/net/ethernet/emulex/benet/be_cmds.c -@@ -1257,11 +1257,13 @@ int be_cmd_link_status_query(struct be_adapter *adapter, u8 *mac_speed, +Index: linux-3.2.46/drivers/net/ethernet/emulex/benet/be_cmds.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/emulex/benet/be_cmds.c 2013-07-26 19:21:24.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/emulex/benet/be_cmds.c 2013-07-26 19:21:31.000000000 +0000 +@@ -1257,11 +1257,13 @@ } req = embedded_payload(wrb); @@ -34,6 +34,3 @@ status = be_mcc_notify_wait(adapter); if (!status) { --- -1.7.10 - diff -Nru linux-3.2.46/debian/patches/features/all/be2net/0031-be2net-Use-new-implementation-of-get-mac-list-comman.patch linux-3.2.46/debian/patches/features/all/be2net/0031-be2net-Use-new-implementation-of-get-mac-list-comman.patch --- linux-3.2.46/debian/patches/features/all/be2net/0031-be2net-Use-new-implementation-of-get-mac-list-comman.patch 2013-02-24 03:52:39.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/be2net/0031-be2net-Use-new-implementation-of-get-mac-list-comman.patch 2013-07-26 19:21:33.000000000 +0000 @@ -16,11 +16,11 @@ drivers/net/ethernet/emulex/benet/be_main.c | 29 ++++++++---- 3 files changed, 92 insertions(+), 40 deletions(-) -diff --git a/drivers/net/ethernet/emulex/benet/be_cmds.c b/drivers/net/ethernet/emulex/benet/be_cmds.c -index dd6e8e2..29dff7d 100644 ---- a/drivers/net/ethernet/emulex/benet/be_cmds.c -+++ b/drivers/net/ethernet/emulex/benet/be_cmds.c -@@ -2300,52 +2300,81 @@ err: +Index: linux-3.2.46/drivers/net/ethernet/emulex/benet/be_cmds.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/emulex/benet/be_cmds.c 2013-07-26 19:21:31.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/emulex/benet/be_cmds.c 2013-07-26 19:21:32.000000000 +0000 +@@ -2300,52 +2300,81 @@ /* Uses synchronous MCCQ */ int be_cmd_get_mac_from_list(struct be_adapter *adapter, u32 domain, @@ -121,11 +121,11 @@ return status; } -diff --git a/drivers/net/ethernet/emulex/benet/be_cmds.h b/drivers/net/ethernet/emulex/benet/be_cmds.h -index bbd012b..5bb66c8 100644 ---- a/drivers/net/ethernet/emulex/benet/be_cmds.h -+++ b/drivers/net/ethernet/emulex/benet/be_cmds.h -@@ -1346,22 +1346,36 @@ struct be_cmd_resp_set_func_cap { +Index: linux-3.2.46/drivers/net/ethernet/emulex/benet/be_cmds.h +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/emulex/benet/be_cmds.h 2013-07-26 19:21:30.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/emulex/benet/be_cmds.h 2013-07-26 19:21:32.000000000 +0000 +@@ -1346,22 +1346,36 @@ /******************** GET/SET_MACLIST **************************/ #define BE_MAX_MAC 64 @@ -172,7 +172,7 @@ } __packed; struct be_cmd_req_set_mac_list { -@@ -1575,7 +1589,7 @@ extern int be_cmd_req_native_mode(struct be_adapter *adapter); +@@ -1575,7 +1589,7 @@ extern int be_cmd_get_reg_len(struct be_adapter *adapter, u32 *log_size); extern void be_cmd_get_regs(struct be_adapter *adapter, u32 buf_len, void *buf); extern int be_cmd_get_mac_from_list(struct be_adapter *adapter, u32 domain, @@ -181,11 +181,11 @@ extern int be_cmd_set_mac_list(struct be_adapter *adapter, u8 *mac_array, u8 mac_count, u32 domain); -diff --git a/drivers/net/ethernet/emulex/benet/be_main.c b/drivers/net/ethernet/emulex/benet/be_main.c -index d1536e2..4364f01 100644 ---- a/drivers/net/ethernet/emulex/benet/be_main.c -+++ b/drivers/net/ethernet/emulex/benet/be_main.c -@@ -2600,19 +2600,28 @@ static void be_setup_init(struct be_adapter *adapter) +Index: linux-3.2.46/drivers/net/ethernet/emulex/benet/be_main.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/emulex/benet/be_main.c 2013-07-26 19:21:30.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/emulex/benet/be_main.c 2013-07-26 19:21:32.000000000 +0000 +@@ -2601,19 +2601,28 @@ adapter->eq_next_idx = 0; } @@ -223,7 +223,7 @@ do_none: return status; } -@@ -2677,7 +2686,7 @@ static int be_setup(struct be_adapter *adapter) +@@ -2678,7 +2687,7 @@ */ if (!be_physfn(adapter)) { if (lancer_chip(adapter)) @@ -232,6 +232,3 @@ else status = be_cmd_mac_addr_query(adapter, mac, MAC_ADDRESS_TYPE_NETWORK, false, --- -1.7.10 - diff -Nru linux-3.2.46/debian/patches/features/all/be2net/0032-be2net-event-queue-re-design.patch linux-3.2.46/debian/patches/features/all/be2net/0032-be2net-event-queue-re-design.patch --- linux-3.2.46/debian/patches/features/all/be2net/0032-be2net-event-queue-re-design.patch 2013-02-24 03:52:39.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/be2net/0032-be2net-event-queue-re-design.patch 2013-07-26 19:21:35.000000000 +0000 @@ -29,11 +29,11 @@ drivers/net/ethernet/emulex/benet/be_main.c | 812 +++++++++++------------- 5 files changed, 434 insertions(+), 578 deletions(-) -diff --git a/drivers/net/ethernet/emulex/benet/be.h b/drivers/net/ethernet/emulex/benet/be.h -index 74aa148..86f51de 100644 ---- a/drivers/net/ethernet/emulex/benet/be.h -+++ b/drivers/net/ethernet/emulex/benet/be.h -@@ -81,7 +81,7 @@ static inline char *nic_name(struct pci_dev *pdev) +Index: linux-3.2.46/drivers/net/ethernet/emulex/benet/be.h +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/emulex/benet/be.h 2013-07-26 19:21:30.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/emulex/benet/be.h 2013-07-26 19:21:34.000000000 +0000 +@@ -81,7 +81,7 @@ #define BE_MIN_MTU 256 #define BE_NUM_VLANS_SUPPORTED 64 @@ -42,7 +42,7 @@ #define BE_MAX_TX_FRAG_COUNT 30 #define EVNT_Q_LEN 1024 -@@ -92,12 +92,16 @@ static inline char *nic_name(struct pci_dev *pdev) +@@ -92,12 +92,16 @@ #define MCC_Q_LEN 128 /* total size not to exceed 8 pages */ #define MCC_CQ_LEN 256 @@ -62,7 +62,7 @@ #define RX_FRAGS_REFILL_WM (RX_Q_LEN - MAX_RX_POST) #define FW_VER_LEN 32 -@@ -165,13 +169,16 @@ struct be_eq_obj { +@@ -165,13 +169,16 @@ /* Adaptive interrupt coalescing (AIC) info */ bool enable_aic; @@ -84,7 +84,7 @@ struct be_mcc_obj { struct be_queue_info q; -@@ -197,7 +204,7 @@ struct be_tx_obj { +@@ -197,7 +204,7 @@ /* Remember the skbs that were transmitted */ struct sk_buff *sent_skb_list[TX_Q_LEN]; struct be_tx_stats stats; @@ -93,7 +93,7 @@ /* Struct to remember the pages posted for rx frags */ struct be_rx_page_info { -@@ -215,8 +222,6 @@ struct be_rx_stats { +@@ -215,8 +222,6 @@ u32 rx_drops_no_skbs; /* skb allocation errors */ u32 rx_drops_no_frags; /* HW has no fetched frags */ u32 rx_post_fail; /* page post alloc failures */ @@ -102,7 +102,7 @@ u32 rx_compl; u32 rx_mcast_pkts; u32 rx_compl_err; /* completions with err set */ -@@ -249,16 +254,13 @@ struct be_rx_obj { +@@ -249,16 +254,13 @@ struct be_queue_info cq; struct be_rx_compl_info rxcp; struct be_rx_page_info page_info_tbl[RX_Q_LEN]; @@ -120,7 +120,7 @@ u32 eth_red_drops; u32 rx_drops_no_pbuf; u32 rx_drops_no_txpb; -@@ -320,20 +322,19 @@ struct be_adapter { +@@ -320,20 +322,19 @@ spinlock_t mcc_lock; /* For serializing mcc cmds to BE card */ spinlock_t mcc_cq_lock; @@ -146,7 +146,7 @@ u32 big_page_size; /* Compounded page size shared by rx wrbs */ u8 eq_next_idx; -@@ -404,24 +405,34 @@ struct be_adapter { +@@ -404,24 +405,34 @@ extern const struct ethtool_ops be_ethtool_ops; #define msix_enabled(adapter) (adapter->num_msix_vec > 0) @@ -186,11 +186,11 @@ #define PAGE_SHIFT_4K 12 #define PAGE_SIZE_4K (1 << PAGE_SHIFT_4K) -diff --git a/drivers/net/ethernet/emulex/benet/be_cmds.c b/drivers/net/ethernet/emulex/benet/be_cmds.c -index 29dff7d..6432efa 100644 ---- a/drivers/net/ethernet/emulex/benet/be_cmds.c -+++ b/drivers/net/ethernet/emulex/benet/be_cmds.c -@@ -235,10 +235,10 @@ void be_async_mcc_disable(struct be_adapter *adapter) +Index: linux-3.2.46/drivers/net/ethernet/emulex/benet/be_cmds.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/emulex/benet/be_cmds.c 2013-07-26 19:21:32.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/emulex/benet/be_cmds.c 2013-07-26 19:21:34.000000000 +0000 +@@ -235,10 +235,10 @@ adapter->mcc_obj.rearm_cq = false; } @@ -203,7 +203,7 @@ struct be_mcc_obj *mcc_obj = &adapter->mcc_obj; spin_lock_bh(&adapter->mcc_cq_lock); -@@ -252,32 +252,32 @@ int be_process_mcc(struct be_adapter *adapter, int *status) +@@ -252,32 +252,32 @@ be_async_grp5_evt_process(adapter, compl->flags, compl); } else if (compl->flags & CQE_FLAGS_COMPLETED_MASK) { @@ -243,7 +243,7 @@ if (atomic_read(&mcc_obj->q.used) == 0) break; -@@ -726,9 +726,8 @@ err: +@@ -726,9 +726,8 @@ } /* Uses Mbox */ @@ -255,7 +255,7 @@ { struct be_mcc_wrb *wrb; struct be_cmd_req_cq_create *req; -@@ -759,7 +758,6 @@ int be_cmd_cq_create(struct be_adapter *adapter, +@@ -759,7 +758,6 @@ ctxt, 1); AMAP_SET_BITS(struct amap_cq_context_lancer, eqid, ctxt, eq->id); @@ -263,7 +263,7 @@ } else { AMAP_SET_BITS(struct amap_cq_context_be, coalescwm, ctxt, coalesce_wm); -@@ -768,11 +766,8 @@ int be_cmd_cq_create(struct be_adapter *adapter, +@@ -768,11 +766,8 @@ AMAP_SET_BITS(struct amap_cq_context_be, count, ctxt, __ilog2_u32(cq->len/256)); AMAP_SET_BITS(struct amap_cq_context_be, valid, ctxt, 1); @@ -275,7 +275,7 @@ } be_dws_cpu_to_le(ctxt, sizeof(req->context)); -@@ -973,7 +968,7 @@ err: +@@ -973,7 +968,7 @@ /* Uses MCC */ int be_cmd_rxq_create(struct be_adapter *adapter, struct be_queue_info *rxq, u16 cq_id, u16 frag_size, @@ -284,7 +284,7 @@ { struct be_mcc_wrb *wrb; struct be_cmd_req_eth_rx_create *req; -@@ -997,7 +992,7 @@ int be_cmd_rxq_create(struct be_adapter *adapter, +@@ -997,7 +992,7 @@ req->num_pages = 2; be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem); req->interface_id = cpu_to_le32(if_id); @@ -293,11 +293,11 @@ req->rss_queue = cpu_to_le32(rss); status = be_mcc_notify_wait(adapter); -diff --git a/drivers/net/ethernet/emulex/benet/be_cmds.h b/drivers/net/ethernet/emulex/benet/be_cmds.h -index 5bb66c8..687c420 100644 ---- a/drivers/net/ethernet/emulex/benet/be_cmds.h -+++ b/drivers/net/ethernet/emulex/benet/be_cmds.h -@@ -1506,8 +1506,7 @@ extern int be_cmd_eq_create(struct be_adapter *adapter, +Index: linux-3.2.46/drivers/net/ethernet/emulex/benet/be_cmds.h +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/emulex/benet/be_cmds.h 2013-07-26 19:21:32.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/emulex/benet/be_cmds.h 2013-07-26 19:21:34.000000000 +0000 +@@ -1506,8 +1506,7 @@ struct be_queue_info *eq, int eq_delay); extern int be_cmd_cq_create(struct be_adapter *adapter, struct be_queue_info *cq, struct be_queue_info *eq, @@ -307,7 +307,7 @@ extern int be_cmd_mccq_create(struct be_adapter *adapter, struct be_queue_info *mccq, struct be_queue_info *cq); -@@ -1516,8 +1515,7 @@ extern int be_cmd_txq_create(struct be_adapter *adapter, +@@ -1516,8 +1515,7 @@ struct be_queue_info *cq); extern int be_cmd_rxq_create(struct be_adapter *adapter, struct be_queue_info *rxq, u16 cq_id, @@ -317,7 +317,7 @@ extern int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q, int type); extern int be_cmd_rxq_destroy(struct be_adapter *adapter, -@@ -1546,7 +1544,7 @@ extern int be_cmd_query_fw_cfg(struct be_adapter *adapter, +@@ -1546,7 +1544,7 @@ extern int be_cmd_reset_function(struct be_adapter *adapter); extern int be_cmd_rss_config(struct be_adapter *adapter, u8 *rsstable, u16 table_size); @@ -326,11 +326,11 @@ extern int be_cmd_set_beacon_state(struct be_adapter *adapter, u8 port_num, u8 beacon, u8 status, u8 state); extern int be_cmd_get_beacon_state(struct be_adapter *adapter, -diff --git a/drivers/net/ethernet/emulex/benet/be_ethtool.c b/drivers/net/ethernet/emulex/benet/be_ethtool.c -index 0a5ee22..d98ad7e 100644 ---- a/drivers/net/ethernet/emulex/benet/be_ethtool.c -+++ b/drivers/net/ethernet/emulex/benet/be_ethtool.c -@@ -37,7 +37,6 @@ enum {DRVSTAT_TX, DRVSTAT_RX, DRVSTAT}; +Index: linux-3.2.46/drivers/net/ethernet/emulex/benet/be_ethtool.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/emulex/benet/be_ethtool.c 2013-07-26 19:21:30.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/emulex/benet/be_ethtool.c 2013-07-26 19:21:34.000000000 +0000 +@@ -37,7 +37,6 @@ FIELDINFO(struct be_drv_stats, field) static const struct be_ethtool_stat et_stats[] = { @@ -338,7 +338,7 @@ {DRVSTAT_INFO(rx_crc_errors)}, {DRVSTAT_INFO(rx_alignment_symbol_errors)}, {DRVSTAT_INFO(rx_pause_frames)}, -@@ -126,8 +125,6 @@ static const struct be_ethtool_stat et_stats[] = { +@@ -126,8 +125,6 @@ static const struct be_ethtool_stat et_rx_stats[] = { {DRVSTAT_RX_INFO(rx_bytes)},/* If moving this member see above note */ {DRVSTAT_RX_INFO(rx_pkts)}, /* If moving this member see above note */ @@ -347,7 +347,7 @@ {DRVSTAT_RX_INFO(rx_compl)}, {DRVSTAT_RX_INFO(rx_mcast_pkts)}, /* Number of page allocation failures while posting receive buffers -@@ -154,7 +151,6 @@ static const struct be_ethtool_stat et_tx_stats[] = { +@@ -154,7 +151,6 @@ {DRVSTAT_TX_INFO(tx_reqs)}, /* Number of TX work request blocks DMAed to HW */ {DRVSTAT_TX_INFO(tx_wrbs)}, @@ -355,7 +355,7 @@ /* Number of times the TX queue was stopped due to lack * of spaces in the TXQ. */ -@@ -290,86 +286,42 @@ be_get_regs(struct net_device *netdev, struct ethtool_regs *regs, void *buf) +@@ -290,86 +286,42 @@ } } @@ -373,19 +373,20 @@ - coalesce->rx_coalesce_usecs = rx_eq->cur_eqd; - coalesce->rx_coalesce_usecs_high = rx_eq->max_eqd; - coalesce->rx_coalesce_usecs_low = rx_eq->min_eqd; +- +- coalesce->tx_coalesce_usecs = tx_eq->cur_eqd; +- coalesce->tx_coalesce_usecs_high = tx_eq->max_eqd; +- coalesce->tx_coalesce_usecs_low = tx_eq->min_eqd; + et->rx_coalesce_usecs = eqo->cur_eqd; + et->rx_coalesce_usecs_high = eqo->max_eqd; + et->rx_coalesce_usecs_low = eqo->min_eqd; -- coalesce->tx_coalesce_usecs = tx_eq->cur_eqd; -- coalesce->tx_coalesce_usecs_high = tx_eq->max_eqd; -- coalesce->tx_coalesce_usecs_low = tx_eq->min_eqd; +- coalesce->use_adaptive_rx_coalesce = rx_eq->enable_aic; +- coalesce->use_adaptive_tx_coalesce = tx_eq->enable_aic; + et->tx_coalesce_usecs = eqo->cur_eqd; + et->tx_coalesce_usecs_high = eqo->max_eqd; + et->tx_coalesce_usecs_low = eqo->min_eqd; - -- coalesce->use_adaptive_rx_coalesce = rx_eq->enable_aic; -- coalesce->use_adaptive_tx_coalesce = tx_eq->enable_aic; ++ + et->use_adaptive_rx_coalesce = eqo->enable_aic; + et->use_adaptive_tx_coalesce = eqo->enable_aic; @@ -448,16 +449,15 @@ - } - - tx_cur = coalesce->tx_coalesce_usecs; -- ++ struct be_eq_obj *eqo; ++ int i; + - if (tx_cur > BE_MAX_EQD) - tx_cur = BE_MAX_EQD; - if (tx_eq->cur_eqd != tx_cur) { - status = be_cmd_modify_eqd(adapter, tx_eq->q.id, tx_cur); - if (!status) - tx_eq->cur_eqd = tx_cur; -+ struct be_eq_obj *eqo; -+ int i; -+ + for_all_evt_queues(adapter, eqo, i) { + eqo->enable_aic = et->use_adaptive_rx_coalesce; + eqo->max_eqd = min(et->rx_coalesce_usecs_high, BE_MAX_EQD); @@ -466,11 +466,11 @@ } return 0; -diff --git a/drivers/net/ethernet/emulex/benet/be_main.c b/drivers/net/ethernet/emulex/benet/be_main.c -index 4364f01..4a3a186 100644 ---- a/drivers/net/ethernet/emulex/benet/be_main.c -+++ b/drivers/net/ethernet/emulex/benet/be_main.c -@@ -144,7 +144,7 @@ static int be_queue_alloc(struct be_adapter *adapter, struct be_queue_info *q, +Index: linux-3.2.46/drivers/net/ethernet/emulex/benet/be_main.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/emulex/benet/be_main.c 2013-07-26 19:21:32.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/emulex/benet/be_main.c 2013-07-26 19:21:34.000000000 +0000 +@@ -144,7 +144,7 @@ mem->va = dma_alloc_coherent(&adapter->pdev->dev, mem->size, &mem->dma, GFP_KERNEL); if (!mem->va) @@ -479,7 +479,7 @@ memset(mem->va, 0, mem->size); return 0; } -@@ -988,18 +988,24 @@ static int be_set_vf_tx_rate(struct net_device *netdev, +@@ -989,18 +989,24 @@ return status; } @@ -508,7 +508,7 @@ /* Wrapped around */ if (time_before(now, stats->rx_jiffies)) { stats->rx_jiffies = now; -@@ -1018,17 +1024,16 @@ static void be_rx_eqd_update(struct be_adapter *adapter, struct be_rx_obj *rxo) +@@ -1019,17 +1025,16 @@ stats->rx_pps = (unsigned long)(pkts - stats->rx_pkts_prev) / (delta / HZ); stats->rx_pkts_prev = pkts; stats->rx_jiffies = now; @@ -534,7 +534,7 @@ } } -@@ -1056,11 +1061,10 @@ static inline bool csum_passed(struct be_rx_compl_info *rxcp) +@@ -1057,11 +1062,10 @@ (rxcp->ip_csum || rxcp->ipv6); } @@ -549,7 +549,7 @@ struct be_rx_page_info *rx_page_info; struct be_queue_info *rxq = &rxo->q; -@@ -1079,16 +1083,15 @@ get_rx_page_info(struct be_adapter *adapter, +@@ -1080,16 +1084,15 @@ } /* Throwaway the data in the Rx completion */ @@ -569,7 +569,7 @@ put_page(page_info->page); memset(page_info, 0, sizeof(*page_info)); index_inc(&rxcp->rxq_idx, rxq->len); -@@ -1099,8 +1102,8 @@ static void be_rx_compl_discard(struct be_adapter *adapter, +@@ -1100,8 +1103,8 @@ * skb_fill_rx_data forms a complete skb for an ether frame * indicated by rxcp. */ @@ -580,7 +580,7 @@ { struct be_queue_info *rxq = &rxo->q; struct be_rx_page_info *page_info; -@@ -1108,7 +1111,7 @@ static void skb_fill_rx_data(struct be_adapter *adapter, struct be_rx_obj *rxo, +@@ -1109,7 +1112,7 @@ u16 hdr_len, curr_frag_len, remaining; u8 *start; @@ -589,7 +589,7 @@ start = page_address(page_info->page) + page_info->page_offset; prefetch(start); -@@ -1145,7 +1148,7 @@ static void skb_fill_rx_data(struct be_adapter *adapter, struct be_rx_obj *rxo, +@@ -1146,7 +1149,7 @@ index_inc(&rxcp->rxq_idx, rxq->len); remaining = rxcp->pkt_size - curr_frag_len; for (i = 1, j = 0; i < rxcp->num_rcvd; i++) { @@ -598,7 +598,7 @@ curr_frag_len = min(remaining, rx_frag_size); /* Coalesce all frags from the same physical page in one slot */ -@@ -1173,21 +1176,21 @@ static void skb_fill_rx_data(struct be_adapter *adapter, struct be_rx_obj *rxo, +@@ -1174,21 +1177,21 @@ } /* Process the RX completion indicated by rxcp when GRO is disabled */ @@ -625,7 +625,7 @@ if (likely((netdev->features & NETIF_F_RXCSUM) && csum_passed(rxcp))) skb->ip_summed = CHECKSUM_UNNECESSARY; -@@ -1195,7 +1198,7 @@ static void be_rx_compl_process(struct be_adapter *adapter, +@@ -1196,7 +1199,7 @@ skb_checksum_none_assert(skb); skb->protocol = eth_type_trans(skb, netdev); @@ -634,7 +634,7 @@ skb->rxhash = rxcp->rss_hash; -@@ -1206,26 +1209,25 @@ static void be_rx_compl_process(struct be_adapter *adapter, +@@ -1207,26 +1210,25 @@ } /* Process the RX completion indicated by rxcp when GRO is enabled */ @@ -667,7 +667,7 @@ curr_frag_len = min(remaining, rx_frag_size); -@@ -1258,12 +1260,11 @@ static void be_rx_compl_process_gro(struct be_adapter *adapter, +@@ -1259,12 +1261,11 @@ if (rxcp->vlanf) __vlan_hwaccel_put_tag(skb, rxcp->vlan_tag); @@ -683,7 +683,7 @@ { rxcp->pkt_size = AMAP_GET_BITS(struct amap_eth_rx_compl_v1, pktsize, compl); -@@ -1294,9 +1295,8 @@ static void be_parse_rx_compl_v1(struct be_adapter *adapter, +@@ -1295,9 +1296,8 @@ rxcp->port = AMAP_GET_BITS(struct amap_eth_rx_compl_v1, port, compl); } @@ -695,7 +695,7 @@ { rxcp->pkt_size = AMAP_GET_BITS(struct amap_eth_rx_compl_v0, pktsize, compl); -@@ -1342,9 +1342,9 @@ static struct be_rx_compl_info *be_rx_compl_get(struct be_rx_obj *rxo) +@@ -1343,9 +1343,9 @@ be_dws_le_to_cpu(compl, sizeof(*compl)); if (adapter->be3_native) @@ -707,7 +707,7 @@ if (rxcp->vlanf) { /* vlanf could be wrongly set in some cards. -@@ -1383,7 +1383,6 @@ static inline struct page *be_alloc_pages(u32 size, gfp_t gfp) +@@ -1384,7 +1384,6 @@ static void be_post_rx_frags(struct be_rx_obj *rxo, gfp_t gfp) { struct be_adapter *adapter = rxo->adapter; @@ -715,7 +715,7 @@ struct be_rx_page_info *page_info = NULL, *prev_page_info = NULL; struct be_queue_info *rxq = &rxo->q; struct page *pagep = NULL; -@@ -1425,7 +1424,7 @@ static void be_post_rx_frags(struct be_rx_obj *rxo, gfp_t gfp) +@@ -1426,7 +1425,7 @@ prev_page_info = page_info; queue_head_inc(rxq); @@ -724,7 +724,7 @@ } if (pagep) prev_page_info->last_page_user = true; -@@ -1487,62 +1486,51 @@ static u16 be_tx_compl_process(struct be_adapter *adapter, +@@ -1488,62 +1487,51 @@ return num_wrbs; } @@ -813,7 +813,7 @@ { struct be_rx_page_info *page_info; struct be_queue_info *rxq = &rxo->q; -@@ -1552,14 +1540,14 @@ static void be_rx_q_clean(struct be_adapter *adapter, struct be_rx_obj *rxo) +@@ -1553,14 +1541,14 @@ /* First cleanup pending rx completions */ while ((rxcp = be_rx_compl_get(rxo)) != NULL) { @@ -831,7 +831,7 @@ put_page(page_info->page); memset(page_info, 0, sizeof(*page_info)); } -@@ -1615,6 +1603,47 @@ static void be_tx_compl_clean(struct be_adapter *adapter, +@@ -1616,6 +1604,47 @@ } } @@ -879,7 +879,7 @@ static void be_mcc_queues_destroy(struct be_adapter *adapter) { struct be_queue_info *q; -@@ -1635,22 +1664,19 @@ static int be_mcc_queues_create(struct be_adapter *adapter) +@@ -1636,22 +1665,19 @@ { struct be_queue_info *q, *cq; @@ -904,7 +904,7 @@ if (be_cmd_mccq_create(adapter, q, cq)) goto mcc_q_free; -@@ -1683,14 +1709,6 @@ static void be_tx_queues_destroy(struct be_adapter *adapter) +@@ -1684,14 +1710,6 @@ be_cmd_q_destroy(adapter, q, QTYPE_CQ); be_queue_free(adapter, q); } @@ -919,7 +919,7 @@ } static int be_num_txqs_want(struct be_adapter *adapter) -@@ -1703,10 +1721,10 @@ static int be_num_txqs_want(struct be_adapter *adapter) +@@ -1704,10 +1722,10 @@ return MAX_TX_QS; } @@ -933,7 +933,7 @@ struct be_tx_obj *txo; u8 i; -@@ -1718,192 +1736,109 @@ static int be_tx_queues_create(struct be_adapter *adapter) +@@ -1719,192 +1737,109 @@ rtnl_unlock(); } @@ -941,46 +941,26 @@ - adapter->tx_eq.min_eqd = 0; - adapter->tx_eq.cur_eqd = 96; - adapter->tx_eq.enable_aic = false; -+ for_all_tx_queues(adapter, txo, i) { -+ cq = &txo->cq; -+ status = be_queue_alloc(adapter, cq, TX_CQ_LEN, -+ sizeof(struct be_eth_tx_compl)); -+ if (status) -+ return status; - +- - eq = &adapter->tx_eq.q; - if (be_queue_alloc(adapter, eq, EVNT_Q_LEN, - sizeof(struct be_eq_entry))) - return -1; -+ /* If num_evt_qs is less than num_tx_qs, then more than -+ * one txq share an eq -+ */ -+ eq = &adapter->eq_obj[i % adapter->num_evt_qs].q; -+ status = be_cmd_cq_create(adapter, cq, eq, false, 3); -+ if (status) -+ return status; -+ } -+ return 0; -+} - +- - if (be_cmd_eq_create(adapter, eq, adapter->tx_eq.cur_eqd)) - goto err; - adapter->tx_eq.eq_idx = adapter->eq_next_idx++; -+static int be_tx_qs_create(struct be_adapter *adapter) -+{ -+ struct be_tx_obj *txo; -+ int i, status; - +- for_all_tx_queues(adapter, txo, i) { -- cq = &txo->cq; + cq = &txo->cq; - if (be_queue_alloc(adapter, cq, TX_CQ_LEN, - sizeof(struct be_eth_tx_compl))) - goto err; - - if (be_cmd_cq_create(adapter, cq, eq, false, false, 3)) - goto err; -+ status = be_queue_alloc(adapter, &txo->q, TX_Q_LEN, -+ sizeof(struct be_eth_wrb)); ++ status = be_queue_alloc(adapter, cq, TX_CQ_LEN, ++ sizeof(struct be_eth_tx_compl)); + if (status) + return status; @@ -988,15 +968,36 @@ - if (be_queue_alloc(adapter, q, TX_Q_LEN, - sizeof(struct be_eth_wrb))) - goto err; -+ status = be_cmd_txq_create(adapter, &txo->q, &txo->cq); ++ /* If num_evt_qs is less than num_tx_qs, then more than ++ * one txq share an eq ++ */ ++ eq = &adapter->eq_obj[i % adapter->num_evt_qs].q; ++ status = be_cmd_cq_create(adapter, cq, eq, false, 3); + if (status) + return status; } -- return 0; + return 0; ++} -err: - be_tx_queues_destroy(adapter); - return -1; ++static int be_tx_qs_create(struct be_adapter *adapter) ++{ ++ struct be_tx_obj *txo; ++ int i, status; ++ ++ for_all_tx_queues(adapter, txo, i) { ++ status = be_queue_alloc(adapter, &txo->q, TX_Q_LEN, ++ sizeof(struct be_eth_wrb)); ++ if (status) ++ return status; ++ ++ status = be_cmd_txq_create(adapter, &txo->q, &txo->cq); ++ if (status) ++ return status; ++ } ++ + return 0; } @@ -1079,19 +1080,19 @@ sizeof(struct be_eth_rx_compl)); if (rc) - goto err; -+ return rc; - +- - rc = be_cmd_cq_create(adapter, cq, eq, false, false, 3); -+ eq = &adapter->eq_obj[i % adapter->num_evt_qs].q; -+ rc = be_cmd_cq_create(adapter, cq, eq, false, 3); - if (rc) +- if (rc) - goto err; -- ++ return rc; + - /* Rx Q - will be created in be_open() */ - q = &rxo->q; - rc = be_queue_alloc(adapter, q, RX_Q_LEN, - sizeof(struct be_eth_rx_d)); -- if (rc) ++ eq = &adapter->eq_obj[i % adapter->num_evt_qs].q; ++ rc = be_cmd_cq_create(adapter, cq, eq, false, 3); + if (rc) - goto err; - + return rc; @@ -1132,7 +1133,8 @@ - - if (!(tx || rx)) - return IRQ_NONE; -- ++ int num_evts; + - } else { - isr = ioread32(adapter->csr + CEV_ISR0_OFFSET + - (adapter->tx_eq.q.id / 8) * CEV_ISR_SIZE); @@ -1155,8 +1157,7 @@ -{ - struct be_rx_obj *rxo = dev; - struct be_adapter *adapter = rxo->adapter; -+ int num_evts; - +- - event_handle(adapter, &rxo->rx_eq, true); - - return IRQ_HANDLED; @@ -1180,7 +1181,7 @@ return IRQ_HANDLED; } -@@ -1912,16 +1847,14 @@ static inline bool do_gro(struct be_rx_compl_info *rxcp) +@@ -1913,16 +1848,14 @@ return (rxcp->tcpf && !rxcp->err) ? true : false; } @@ -1199,7 +1200,7 @@ for (work_done = 0; work_done < budget; work_done++) { rxcp = be_rx_compl_get(rxo); if (!rxcp) -@@ -1933,7 +1866,7 @@ static int be_poll_rx(struct napi_struct *napi, int budget) +@@ -1934,7 +1867,7 @@ /* Discard compl with partial DMA Lancer B0 */ if (unlikely(!rxcp->pkt_size)) { @@ -1208,7 +1209,7 @@ goto loop_continue; } -@@ -1942,94 +1875,96 @@ static int be_poll_rx(struct napi_struct *napi, int budget) +@@ -1943,94 +1876,96 @@ */ if (unlikely(rxcp->port != adapter->port_num && !lancer_chip(adapter))) { @@ -1228,13 +1229,13 @@ } - be_cq_notify(adapter, rx_cq->id, false, work_done); -+ if (work_done) { -+ be_cq_notify(adapter, rx_cq->id, true, work_done); - +- - /* Refill the queue */ - if (work_done && atomic_read(&rxo->q.used) < RX_FRAGS_REFILL_WM) - be_post_rx_frags(rxo, GFP_ATOMIC); -- ++ if (work_done) { ++ be_cq_notify(adapter, rx_cq->id, true, work_done); + - /* All consumed */ - if (work_done < budget) { - napi_complete(napi); @@ -1281,20 +1282,20 @@ - } - if (tx_compl) { - be_cq_notify(adapter, txo->cq.id, true, tx_compl); -- -- atomic_sub(num_wrbs, &txo->q.used); + } +- atomic_sub(num_wrbs, &txo->q.used); ++ if (work_done) { ++ be_cq_notify(adapter, txo->cq.id, true, work_done); ++ atomic_sub(num_wrbs, &txo->q.used); + - /* As Tx wrbs have been freed up, wake up netdev queue - * if it was stopped due to lack of tx wrbs. */ - if (__netif_subqueue_stopped(adapter->netdev, i) && - atomic_read(&txo->q.used) < txo->q.len / 2) { - netif_wake_subqueue(adapter->netdev, i); - } -+ if (work_done) { -+ be_cq_notify(adapter, txo->cq.id, true, work_done); -+ atomic_sub(num_wrbs, &txo->q.used); - +- - u64_stats_update_begin(&tx_stats(txo)->sync_compl); - tx_stats(txo)->tx_compl += tx_compl; - u64_stats_update_end(&tx_stats(txo)->sync_compl); @@ -1363,7 +1364,7 @@ } void be_detect_dump_ue(struct be_adapter *adapter) -@@ -2104,12 +2039,24 @@ static void be_msix_disable(struct be_adapter *adapter) +@@ -2105,12 +2040,24 @@ } } @@ -1390,12 +1391,13 @@ for (i = 0; i < num_vec; i++) adapter->msix_entries[i].entry = i; -@@ -2177,60 +2124,31 @@ static void be_sriov_disable(struct be_adapter *adapter) +@@ -2178,60 +2125,31 @@ } static inline int be_msix_vec_get(struct be_adapter *adapter, - struct be_eq_obj *eq_obj) --{ ++ struct be_eq_obj *eqo) + { - return adapter->msix_entries[eq_obj->eq_idx].vector; -} - @@ -1413,8 +1415,7 @@ - -static void be_free_irq(struct be_adapter *adapter, struct be_eq_obj *eq_obj, - void *context) -+ struct be_eq_obj *eqo) - { +-{ - int vec = be_msix_vec_get(adapter, eq_obj); - free_irq(vec, context); + return adapter->msix_entries[eqo->idx].vector; @@ -1464,7 +1465,7 @@ be_msix_disable(adapter); return status; } -@@ -2266,7 +2184,7 @@ done: +@@ -2267,7 +2185,7 @@ static void be_irq_unregister(struct be_adapter *adapter) { struct net_device *netdev = adapter->netdev; @@ -1473,7 +1474,7 @@ int i; if (!adapter->isr_registered) -@@ -2279,16 +2197,14 @@ static void be_irq_unregister(struct be_adapter *adapter) +@@ -2280,16 +2198,14 @@ } /* MSIx */ @@ -1493,7 +1494,7 @@ { struct be_queue_info *q; struct be_rx_obj *rxo; -@@ -2303,53 +2219,33 @@ static void be_rx_queues_clear(struct be_adapter *adapter) +@@ -2304,53 +2220,33 @@ * arrive */ mdelay(1); @@ -1558,7 +1559,7 @@ be_irq_unregister(adapter); /* Wait for all pending tx completions to arrive so that -@@ -2358,21 +2254,34 @@ static int be_close(struct net_device *netdev) +@@ -2359,21 +2255,34 @@ for_all_tx_queues(adapter, txo, i) be_tx_compl_clean(adapter, txo); @@ -1598,7 +1599,7 @@ if (rc) return rc; } -@@ -2386,48 +2295,47 @@ static int be_rx_queues_setup(struct be_adapter *adapter) +@@ -2387,48 +2296,47 @@ } } rc = be_cmd_rss_config(adapter, rsstable, 128); @@ -1660,7 +1661,7 @@ status = be_cmd_link_status_query(adapter, NULL, NULL, &link_status, 0); if (!status) -@@ -2537,11 +2445,14 @@ static int be_clear(struct be_adapter *adapter) +@@ -2538,11 +2446,14 @@ be_cmd_if_destroy(adapter, adapter->if_handle, 0); be_mcc_queues_destroy(adapter); @@ -1676,7 +1677,7 @@ return 0; } -@@ -2631,24 +2542,29 @@ static int be_setup(struct be_adapter *adapter) +@@ -2632,24 +2543,29 @@ struct net_device *netdev = adapter->netdev; u32 cap_flags, en_flags; u32 tx_fc, rx_fc; @@ -1713,7 +1714,7 @@ goto err; memset(mac, 0, ETH_ALEN); -@@ -2674,12 +2590,6 @@ static int be_setup(struct be_adapter *adapter) +@@ -2675,12 +2591,6 @@ if (status != 0) goto err; @@ -1726,7 +1727,7 @@ /* The VF's permanent mac queried from card is incorrect. * For BEx: Query the mac configued by the PF using if_handle * For Lancer: Get and use mac_list to obtain mac address. -@@ -2697,6 +2607,10 @@ static int be_setup(struct be_adapter *adapter) +@@ -2698,6 +2608,10 @@ } } @@ -1737,7 +1738,7 @@ be_cmd_get_fw_ver(adapter, adapter->fw_ver, NULL); status = be_vid_config(adapter, false, 0); -@@ -2736,12 +2650,13 @@ err: +@@ -2737,12 +2651,13 @@ static void be_netpoll(struct net_device *netdev) { struct be_adapter *adapter = netdev_priv(netdev); @@ -1755,7 +1756,7 @@ } #endif -@@ -3102,7 +3017,7 @@ static const struct net_device_ops be_netdev_ops = { +@@ -3103,7 +3018,7 @@ static void be_netdev_init(struct net_device *netdev) { struct be_adapter *adapter = netdev_priv(netdev); @@ -1764,7 +1765,7 @@ int i; netdev->hw_features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6 | -@@ -3121,16 +3036,12 @@ static void be_netdev_init(struct net_device *netdev) +@@ -3122,16 +3037,12 @@ netif_set_gso_max_size(netdev, 65535); @@ -1784,7 +1785,7 @@ } static void be_unmap_pci_bars(struct be_adapter *adapter) -@@ -3301,8 +3212,6 @@ static void __devexit be_remove(struct pci_dev *pdev) +@@ -3302,8 +3213,6 @@ be_sriov_disable(adapter); @@ -1793,7 +1794,7 @@ pci_set_drvdata(pdev, NULL); pci_release_regions(pdev); pci_disable_device(pdev); -@@ -3469,6 +3378,7 @@ static void be_worker(struct work_struct *work) +@@ -3470,6 +3379,7 @@ struct be_adapter *adapter = container_of(work, struct be_adapter, work.work); struct be_rx_obj *rxo; @@ -1801,7 +1802,7 @@ int i; if (lancer_chip(adapter)) -@@ -3479,15 +3389,7 @@ static void be_worker(struct work_struct *work) +@@ -3480,15 +3390,7 @@ /* when interrupts are not yet enabled, just reap any pending * mcc completions */ if (!netif_running(adapter->netdev)) { @@ -1818,7 +1819,7 @@ goto reschedule; } -@@ -3500,14 +3402,15 @@ static void be_worker(struct work_struct *work) +@@ -3501,14 +3403,15 @@ } for_all_rx_queues(adapter, rxo, i) { @@ -1836,7 +1837,7 @@ reschedule: adapter->work_counter++; schedule_delayed_work(&adapter->work, msecs_to_jiffies(1000)); -@@ -3593,6 +3496,12 @@ static int __devinit be_probe(struct pci_dev *pdev, +@@ -3594,6 +3497,12 @@ if (status) goto ctrl_clean; @@ -1849,7 +1850,7 @@ status = be_stats_init(adapter); if (status) goto ctrl_clean; -@@ -3601,14 +3510,6 @@ static int __devinit be_probe(struct pci_dev *pdev, +@@ -3602,14 +3511,6 @@ if (status) goto stats_clean; @@ -1864,7 +1865,7 @@ INIT_DELAYED_WORK(&adapter->work, be_worker); adapter->rx_fc = adapter->tx_fc = true; -@@ -3621,7 +3522,8 @@ static int __devinit be_probe(struct pci_dev *pdev, +@@ -3622,7 +3523,8 @@ if (status != 0) goto unsetup; @@ -1874,7 +1875,7 @@ schedule_delayed_work(&adapter->work, msecs_to_jiffies(100)); return 0; -@@ -3665,7 +3567,6 @@ static int be_suspend(struct pci_dev *pdev, pm_message_t state) +@@ -3666,7 +3568,6 @@ } be_clear(adapter); @@ -1882,7 +1883,7 @@ pci_save_state(pdev); pci_disable_device(pdev); pci_set_power_state(pdev, pci_choose_state(pdev, state)); -@@ -3687,7 +3588,6 @@ static int be_resume(struct pci_dev *pdev) +@@ -3688,7 +3589,6 @@ pci_set_power_state(pdev, 0); pci_restore_state(pdev); @@ -1890,6 +1891,3 @@ /* tell fw we're ready to fire cmds */ status = be_cmd_fw_init(adapter); if (status) --- -1.7.10 - diff -Nru linux-3.2.46/debian/patches/features/all/be2net/0033-be2net-cancel-be_worker-during-EEH-recovery.patch linux-3.2.46/debian/patches/features/all/be2net/0033-be2net-cancel-be_worker-during-EEH-recovery.patch --- linux-3.2.46/debian/patches/features/all/be2net/0033-be2net-cancel-be_worker-during-EEH-recovery.patch 2013-02-24 03:52:39.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/be2net/0033-be2net-cancel-be_worker-during-EEH-recovery.patch 2013-07-26 19:21:36.000000000 +0000 @@ -14,11 +14,11 @@ drivers/net/ethernet/emulex/benet/be_main.c | 13 ++++++++----- 2 files changed, 9 insertions(+), 5 deletions(-) -diff --git a/drivers/net/ethernet/emulex/benet/be.h b/drivers/net/ethernet/emulex/benet/be.h -index 86f51de..4b1994d 100644 ---- a/drivers/net/ethernet/emulex/benet/be.h -+++ b/drivers/net/ethernet/emulex/benet/be.h -@@ -304,6 +304,7 @@ struct be_vf_cfg { +Index: linux-3.2.46/drivers/net/ethernet/emulex/benet/be.h +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/emulex/benet/be.h 2013-07-26 19:21:34.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/emulex/benet/be.h 2013-07-26 19:21:35.000000000 +0000 +@@ -304,6 +304,7 @@ }; #define BE_FLAGS_LINK_STATUS_INIT 1 @@ -26,11 +26,11 @@ struct be_adapter { struct pci_dev *pdev; -diff --git a/drivers/net/ethernet/emulex/benet/be_main.c b/drivers/net/ethernet/emulex/benet/be_main.c -index 4a3a186..2c146ac 100644 ---- a/drivers/net/ethernet/emulex/benet/be_main.c -+++ b/drivers/net/ethernet/emulex/benet/be_main.c -@@ -2439,6 +2439,11 @@ static void be_vf_clear(struct be_adapter *adapter) +Index: linux-3.2.46/drivers/net/ethernet/emulex/benet/be_main.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/emulex/benet/be_main.c 2013-07-26 19:21:34.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/emulex/benet/be_main.c 2013-07-26 19:21:35.000000000 +0000 +@@ -2440,6 +2440,11 @@ static int be_clear(struct be_adapter *adapter) { @@ -42,7 +42,7 @@ if (sriov_enabled(adapter)) be_vf_clear(adapter); -@@ -2640,6 +2645,9 @@ static int be_setup(struct be_adapter *adapter) +@@ -2641,6 +2646,9 @@ goto err; } @@ -52,7 +52,7 @@ return 0; err: be_clear(adapter); -@@ -3200,8 +3208,6 @@ static void __devexit be_remove(struct pci_dev *pdev) +@@ -3201,8 +3209,6 @@ if (!adapter) return; @@ -61,7 +61,7 @@ unregister_netdev(adapter->netdev); be_clear(adapter); -@@ -3525,7 +3531,6 @@ static int __devinit be_probe(struct pci_dev *pdev, +@@ -3526,7 +3532,6 @@ dev_info(&pdev->dev, "%s: %s port %d\n", netdev->name, nic_name(pdev), adapter->port_num); @@ -69,7 +69,7 @@ return 0; unsetup: -@@ -3555,7 +3560,6 @@ static int be_suspend(struct pci_dev *pdev, pm_message_t state) +@@ -3556,7 +3561,6 @@ struct be_adapter *adapter = pci_get_drvdata(pdev); struct net_device *netdev = adapter->netdev; @@ -77,7 +77,7 @@ if (adapter->wol) be_setup_wol(adapter, true); -@@ -3604,7 +3608,6 @@ static int be_resume(struct pci_dev *pdev) +@@ -3605,7 +3609,6 @@ if (adapter->wol) be_setup_wol(adapter, false); @@ -85,6 +85,3 @@ return 0; } --- -1.7.10 - diff -Nru linux-3.2.46/debian/patches/features/all/be2net/0034-be2net-fix-tx-completion-cleanup.patch linux-3.2.46/debian/patches/features/all/be2net/0034-be2net-fix-tx-completion-cleanup.patch --- linux-3.2.46/debian/patches/features/all/be2net/0034-be2net-fix-tx-completion-cleanup.patch 2013-02-24 03:52:39.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/be2net/0034-be2net-fix-tx-completion-cleanup.patch 2013-07-26 19:21:38.000000000 +0000 @@ -13,11 +13,11 @@ drivers/net/ethernet/emulex/benet/be_main.c | 75 +++++++++++++++------------ 1 file changed, 42 insertions(+), 33 deletions(-) -diff --git a/drivers/net/ethernet/emulex/benet/be_main.c b/drivers/net/ethernet/emulex/benet/be_main.c -index 2c146ac..dce97dc 100644 ---- a/drivers/net/ethernet/emulex/benet/be_main.c -+++ b/drivers/net/ethernet/emulex/benet/be_main.c -@@ -1555,51 +1555,62 @@ static void be_rx_cq_clean(struct be_rx_obj *rxo) +Index: linux-3.2.46/drivers/net/ethernet/emulex/benet/be_main.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/emulex/benet/be_main.c 2013-07-26 19:21:35.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/emulex/benet/be_main.c 2013-07-26 19:21:37.000000000 +0000 +@@ -1556,51 +1556,62 @@ rxq->tail = rxq->head = 0; } @@ -110,7 +110,7 @@ } } -@@ -2228,7 +2239,6 @@ static void be_rx_qs_destroy(struct be_adapter *adapter) +@@ -2229,7 +2240,6 @@ static int be_close(struct net_device *netdev) { struct be_adapter *adapter = netdev_priv(netdev); @@ -118,7 +118,7 @@ struct be_eq_obj *eqo; int i; -@@ -2251,8 +2261,7 @@ static int be_close(struct net_device *netdev) +@@ -2252,8 +2262,7 @@ /* Wait for all pending tx completions to arrive so that * all tx skbs are freed. */ @@ -128,6 +128,3 @@ be_rx_qs_destroy(adapter); return 0; --- -1.7.10 - diff -Nru linux-3.2.46/debian/patches/features/all/be2net/0035-be2net-reset-queue-address-after-freeing.patch linux-3.2.46/debian/patches/features/all/be2net/0035-be2net-reset-queue-address-after-freeing.patch --- linux-3.2.46/debian/patches/features/all/be2net/0035-be2net-reset-queue-address-after-freeing.patch 2013-02-24 03:52:39.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/be2net/0035-be2net-reset-queue-address-after-freeing.patch 2013-07-26 19:21:39.000000000 +0000 @@ -13,11 +13,11 @@ drivers/net/ethernet/emulex/benet/be_main.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) -diff --git a/drivers/net/ethernet/emulex/benet/be_main.c b/drivers/net/ethernet/emulex/benet/be_main.c -index dce97dc..c1b9cdf 100644 ---- a/drivers/net/ethernet/emulex/benet/be_main.c -+++ b/drivers/net/ethernet/emulex/benet/be_main.c -@@ -127,9 +127,11 @@ static inline bool be_is_mc(struct be_adapter *adapter) { +Index: linux-3.2.46/drivers/net/ethernet/emulex/benet/be_main.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/emulex/benet/be_main.c 2013-07-26 19:21:37.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/emulex/benet/be_main.c 2013-07-26 19:21:38.000000000 +0000 +@@ -127,9 +127,11 @@ static void be_queue_free(struct be_adapter *adapter, struct be_queue_info *q) { struct be_dma_mem *mem = &q->dma_mem; @@ -30,7 +30,7 @@ } static int be_queue_alloc(struct be_adapter *adapter, struct be_queue_info *q, -@@ -1652,7 +1654,7 @@ static int be_evt_queues_create(struct be_adapter *adapter) +@@ -1653,7 +1655,7 @@ if (rc) return rc; } @@ -39,6 +39,3 @@ } static void be_mcc_queues_destroy(struct be_adapter *adapter) --- -1.7.10 - diff -Nru linux-3.2.46/debian/patches/features/all/be2net/0036-be2net-enable-RSS-for-ipv6-pkts.patch linux-3.2.46/debian/patches/features/all/be2net/0036-be2net-enable-RSS-for-ipv6-pkts.patch --- linux-3.2.46/debian/patches/features/all/be2net/0036-be2net-enable-RSS-for-ipv6-pkts.patch 2013-02-24 03:52:39.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/be2net/0036-be2net-enable-RSS-for-ipv6-pkts.patch 2013-07-26 19:21:40.000000000 +0000 @@ -10,11 +10,11 @@ drivers/net/ethernet/emulex/benet/be_cmds.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) -diff --git a/drivers/net/ethernet/emulex/benet/be_cmds.c b/drivers/net/ethernet/emulex/benet/be_cmds.c -index 6432efa..398fb5c 100644 ---- a/drivers/net/ethernet/emulex/benet/be_cmds.c -+++ b/drivers/net/ethernet/emulex/benet/be_cmds.c -@@ -1694,7 +1694,8 @@ int be_cmd_rss_config(struct be_adapter *adapter, u8 *rsstable, u16 table_size) +Index: linux-3.2.46/drivers/net/ethernet/emulex/benet/be_cmds.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/emulex/benet/be_cmds.c 2013-07-26 19:21:34.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/emulex/benet/be_cmds.c 2013-07-26 19:21:39.000000000 +0000 +@@ -1694,7 +1694,8 @@ OPCODE_ETH_RSS_CONFIG, sizeof(*req), wrb, NULL); req->if_id = cpu_to_le32(adapter->if_handle); @@ -24,6 +24,3 @@ req->cpu_table_size_log2 = cpu_to_le16(fls(table_size) - 1); memcpy(req->cpu_table, rsstable, table_size); memcpy(req->hash, myhash, sizeof(myhash)); --- -1.7.10 - diff -Nru linux-3.2.46/debian/patches/features/all/be2net/0037-be2net-update-driver-version.patch linux-3.2.46/debian/patches/features/all/be2net/0037-be2net-update-driver-version.patch --- linux-3.2.46/debian/patches/features/all/be2net/0037-be2net-update-driver-version.patch 2013-02-24 03:52:39.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/be2net/0037-be2net-update-driver-version.patch 2013-07-26 19:21:41.000000000 +0000 @@ -10,10 +10,10 @@ drivers/net/ethernet/emulex/benet/be.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -diff --git a/drivers/net/ethernet/emulex/benet/be.h b/drivers/net/ethernet/emulex/benet/be.h -index 4b1994d..c357172 100644 ---- a/drivers/net/ethernet/emulex/benet/be.h -+++ b/drivers/net/ethernet/emulex/benet/be.h +Index: linux-3.2.46/drivers/net/ethernet/emulex/benet/be.h +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/emulex/benet/be.h 2013-07-26 19:21:35.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/emulex/benet/be.h 2013-07-26 19:21:41.000000000 +0000 @@ -33,7 +33,7 @@ #include "be_hw.h" @@ -23,6 +23,3 @@ #define DRV_NAME "be2net" #define BE_NAME "ServerEngines BladeEngine2 10Gbps NIC" #define BE3_NAME "ServerEngines BladeEngine3 10Gbps NIC" --- -1.7.10 - diff -Nru linux-3.2.46/debian/patches/features/all/be2net/0038-be2net-Remove-unused-OFFSET_IN_PAGE-macro.patch linux-3.2.46/debian/patches/features/all/be2net/0038-be2net-Remove-unused-OFFSET_IN_PAGE-macro.patch --- linux-3.2.46/debian/patches/features/all/be2net/0038-be2net-Remove-unused-OFFSET_IN_PAGE-macro.patch 2013-02-24 03:52:39.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/be2net/0038-be2net-Remove-unused-OFFSET_IN_PAGE-macro.patch 2013-07-26 19:21:43.000000000 +0000 @@ -10,11 +10,11 @@ drivers/net/ethernet/emulex/benet/be.h | 4 ---- 1 file changed, 4 deletions(-) -diff --git a/drivers/net/ethernet/emulex/benet/be.h b/drivers/net/ethernet/emulex/benet/be.h -index c357172..ab24e46 100644 ---- a/drivers/net/ethernet/emulex/benet/be.h -+++ b/drivers/net/ethernet/emulex/benet/be.h -@@ -442,10 +442,6 @@ extern const struct ethtool_ops be_ethtool_ops; +Index: linux-3.2.46/drivers/net/ethernet/emulex/benet/be.h +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/emulex/benet/be.h 2013-07-26 19:21:41.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/emulex/benet/be.h 2013-07-26 19:21:42.000000000 +0000 +@@ -442,10 +442,6 @@ ((u32)((((size_t)(_address) & (PAGE_SIZE_4K - 1)) + \ (size) + (PAGE_SIZE_4K - 1)) >> PAGE_SHIFT_4K)) @@ -25,6 +25,3 @@ /* Returns bit offset within a DWORD of a bitfield */ #define AMAP_BIT_OFFSET(_struct, field) \ (((size_t)&(((_struct *)0)->field))%32) --- -1.7.10 - diff -Nru linux-3.2.46/debian/patches/features/all/be2net/0039-be2net-enable-WOL-by-default-if-h-w-supports-it.patch linux-3.2.46/debian/patches/features/all/be2net/0039-be2net-enable-WOL-by-default-if-h-w-supports-it.patch --- linux-3.2.46/debian/patches/features/all/be2net/0039-be2net-enable-WOL-by-default-if-h-w-supports-it.patch 2013-02-24 03:52:39.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/be2net/0039-be2net-enable-WOL-by-default-if-h-w-supports-it.patch 2013-07-26 19:21:44.000000000 +0000 @@ -14,10 +14,10 @@ drivers/net/ethernet/emulex/benet/be_main.c | 17 ++++++++ 5 files changed, 136 insertions(+), 17 deletions(-) -diff --git a/drivers/net/ethernet/emulex/benet/be.h b/drivers/net/ethernet/emulex/benet/be.h -index ab24e46..cabe1b8 100644 ---- a/drivers/net/ethernet/emulex/benet/be.h -+++ b/drivers/net/ethernet/emulex/benet/be.h +Index: linux-3.2.46/drivers/net/ethernet/emulex/benet/be.h +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/emulex/benet/be.h 2013-07-26 19:21:42.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/emulex/benet/be.h 2013-07-26 19:21:43.000000000 +0000 @@ -52,6 +52,10 @@ #define OC_DEVICE_ID3 0xe220 /* Device id for Lancer cards */ #define OC_DEVICE_ID4 0xe228 /* Device id for VF in Lancer */ @@ -29,7 +29,7 @@ static inline char *nic_name(struct pci_dev *pdev) { -@@ -365,7 +369,6 @@ struct be_adapter { +@@ -365,7 +369,6 @@ bool fw_timeout; u32 port_num; bool promiscuous; @@ -37,7 +37,7 @@ u32 function_mode; u32 function_caps; u32 rx_fc; /* Rx flow control */ -@@ -386,6 +389,8 @@ struct be_adapter { +@@ -386,6 +389,8 @@ u32 sli_family; u8 hba_port_num; u16 pvid; @@ -46,7 +46,7 @@ }; #define be_physfn(adapter) (!adapter->is_virtfn) -@@ -549,9 +554,28 @@ static inline bool be_error(struct be_adapter *adapter) +@@ -549,9 +554,28 @@ return adapter->eeh_err || adapter->ue_detected || adapter->fw_timeout; } @@ -75,11 +75,11 @@ extern int be_load_fw(struct be_adapter *adapter, u8 *func); +extern bool be_is_wol_supported(struct be_adapter *adapter); #endif /* BE_H */ -diff --git a/drivers/net/ethernet/emulex/benet/be_cmds.c b/drivers/net/ethernet/emulex/benet/be_cmds.c -index 398fb5c..d72c2b4 100644 ---- a/drivers/net/ethernet/emulex/benet/be_cmds.c -+++ b/drivers/net/ethernet/emulex/benet/be_cmds.c -@@ -2418,3 +2418,58 @@ err: +Index: linux-3.2.46/drivers/net/ethernet/emulex/benet/be_cmds.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/emulex/benet/be_cmds.c 2013-07-26 19:21:39.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/emulex/benet/be_cmds.c 2013-07-26 19:21:43.000000000 +0000 +@@ -2418,3 +2418,58 @@ spin_unlock_bh(&adapter->mcc_lock); return status; } @@ -138,11 +138,11 @@ + pci_free_consistent(adapter->pdev, cmd.size, cmd.va, cmd.dma); + return status; +} -diff --git a/drivers/net/ethernet/emulex/benet/be_cmds.h b/drivers/net/ethernet/emulex/benet/be_cmds.h -index 687c420..345d49e 100644 ---- a/drivers/net/ethernet/emulex/benet/be_cmds.h -+++ b/drivers/net/ethernet/emulex/benet/be_cmds.h -@@ -1206,6 +1206,33 @@ struct be_cmd_req_acpi_wol_magic_config{ +Index: linux-3.2.46/drivers/net/ethernet/emulex/benet/be_cmds.h +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/emulex/benet/be_cmds.h 2013-07-26 19:21:34.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/emulex/benet/be_cmds.h 2013-07-26 19:21:43.000000000 +0000 +@@ -1206,6 +1206,33 @@ u8 rsvd2[2]; } __packed; @@ -176,17 +176,17 @@ /********************** LoopBack test *********************/ struct be_cmd_req_loopback_test { struct be_cmd_req_hdr hdr; -@@ -1590,4 +1617,5 @@ extern int be_cmd_get_mac_from_list(struct be_adapter *adapter, u32 domain, +@@ -1590,4 +1617,5 @@ bool *pmac_id_active, u32 *pmac_id, u8 *mac); extern int be_cmd_set_mac_list(struct be_adapter *adapter, u8 *mac_array, u8 mac_count, u32 domain); +extern int be_cmd_get_acpi_wol_cap(struct be_adapter *adapter); -diff --git a/drivers/net/ethernet/emulex/benet/be_ethtool.c b/drivers/net/ethernet/emulex/benet/be_ethtool.c -index d98ad7e..e0eb995 100644 ---- a/drivers/net/ethernet/emulex/benet/be_ethtool.c -+++ b/drivers/net/ethernet/emulex/benet/be_ethtool.c -@@ -600,26 +600,16 @@ be_set_phys_id(struct net_device *netdev, +Index: linux-3.2.46/drivers/net/ethernet/emulex/benet/be_ethtool.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/emulex/benet/be_ethtool.c 2013-07-26 19:21:34.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/emulex/benet/be_ethtool.c 2013-07-26 19:21:43.000000000 +0000 +@@ -600,26 +600,16 @@ return 0; } @@ -217,7 +217,7 @@ wol->wolopts = 0; memset(&wol->sopass, 0, sizeof(wol->sopass)); } -@@ -630,9 +620,14 @@ be_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol) +@@ -630,9 +620,14 @@ struct be_adapter *adapter = netdev_priv(netdev); if (wol->wolopts & ~WAKE_MAGIC) @@ -234,11 +234,11 @@ adapter->wol = true; else adapter->wol = false; -diff --git a/drivers/net/ethernet/emulex/benet/be_main.c b/drivers/net/ethernet/emulex/benet/be_main.c -index c1b9cdf..70b138f 100644 ---- a/drivers/net/ethernet/emulex/benet/be_main.c -+++ b/drivers/net/ethernet/emulex/benet/be_main.c -@@ -3236,6 +3236,12 @@ static void __devexit be_remove(struct pci_dev *pdev) +Index: linux-3.2.46/drivers/net/ethernet/emulex/benet/be_main.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/emulex/benet/be_main.c 2013-07-26 19:21:38.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/emulex/benet/be_main.c 2013-07-26 19:21:43.000000000 +0000 +@@ -3237,6 +3237,12 @@ free_netdev(adapter->netdev); } @@ -251,7 +251,7 @@ static int be_get_config(struct be_adapter *adapter) { int status; -@@ -3254,6 +3260,17 @@ static int be_get_config(struct be_adapter *adapter) +@@ -3255,6 +3261,17 @@ if (status) return status; @@ -269,6 +269,3 @@ return 0; } --- -1.7.10 - diff -Nru linux-3.2.46/debian/patches/features/all/be2net/0040-be2net-Program-secondary-UC-MAC-address-into-MAC-fil.patch linux-3.2.46/debian/patches/features/all/be2net/0040-be2net-Program-secondary-UC-MAC-address-into-MAC-fil.patch --- linux-3.2.46/debian/patches/features/all/be2net/0040-be2net-Program-secondary-UC-MAC-address-into-MAC-fil.patch 2013-02-24 03:52:39.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/be2net/0040-be2net-Program-secondary-UC-MAC-address-into-MAC-fil.patch 2013-07-26 19:21:46.000000000 +0000 @@ -12,11 +12,11 @@ drivers/net/ethernet/emulex/benet/be_main.c | 53 ++++++++++++++++++++++++--- 2 files changed, 53 insertions(+), 6 deletions(-) -diff --git a/drivers/net/ethernet/emulex/benet/be.h b/drivers/net/ethernet/emulex/benet/be.h -index cabe1b8..03fc3db 100644 ---- a/drivers/net/ethernet/emulex/benet/be.h -+++ b/drivers/net/ethernet/emulex/benet/be.h -@@ -309,6 +309,8 @@ struct be_vf_cfg { +Index: linux-3.2.46/drivers/net/ethernet/emulex/benet/be.h +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/emulex/benet/be.h 2013-07-26 19:21:43.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/emulex/benet/be.h 2013-07-26 19:21:45.000000000 +0000 +@@ -309,6 +309,8 @@ #define BE_FLAGS_LINK_STATUS_INIT 1 #define BE_FLAGS_WORKER_SCHEDULED (1 << 3) @@ -25,7 +25,7 @@ struct be_adapter { struct pci_dev *pdev; -@@ -361,7 +363,7 @@ struct be_adapter { +@@ -361,7 +363,7 @@ /* Ethtool knobs and info */ char fw_ver[FW_VER_LEN]; int if_handle; /* Used to configure filtering */ @@ -34,7 +34,7 @@ u32 beacon_state; /* for set_phys_id */ bool eeh_err; -@@ -391,6 +393,8 @@ struct be_adapter { +@@ -391,6 +393,8 @@ u16 pvid; u8 wol_cap; bool wol; @@ -43,11 +43,11 @@ }; #define be_physfn(adapter) (!adapter->is_virtfn) -diff --git a/drivers/net/ethernet/emulex/benet/be_main.c b/drivers/net/ethernet/emulex/benet/be_main.c -index 70b138f..b8b34f5 100644 ---- a/drivers/net/ethernet/emulex/benet/be_main.c -+++ b/drivers/net/ethernet/emulex/benet/be_main.c -@@ -235,7 +235,7 @@ static int be_mac_addr_set(struct net_device *netdev, void *p) +Index: linux-3.2.46/drivers/net/ethernet/emulex/benet/be_main.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/emulex/benet/be_main.c 2013-07-26 19:21:43.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/emulex/benet/be_main.c 2013-07-26 19:21:45.000000000 +0000 +@@ -235,7 +235,7 @@ struct sockaddr *addr = p; int status = 0; u8 current_mac[ETH_ALEN]; @@ -56,7 +56,7 @@ if (!is_valid_ether_addr(addr->sa_data)) return -EADDRNOTAVAIL; -@@ -248,7 +248,7 @@ static int be_mac_addr_set(struct net_device *netdev, void *p) +@@ -248,7 +248,7 @@ if (memcmp(addr->sa_data, current_mac, ETH_ALEN)) { status = be_cmd_pmac_add(adapter, (u8 *)addr->sa_data, @@ -65,7 +65,7 @@ if (status) goto err; -@@ -877,6 +877,29 @@ static void be_set_rx_mode(struct net_device *netdev) +@@ -878,6 +878,29 @@ goto done; } @@ -95,7 +95,7 @@ be_cmd_rx_filter(adapter, IFF_MULTICAST, ON); done: return; -@@ -2450,6 +2473,8 @@ static void be_vf_clear(struct be_adapter *adapter) +@@ -2451,6 +2474,8 @@ static int be_clear(struct be_adapter *adapter) { @@ -104,7 +104,7 @@ if (adapter->flags & BE_FLAGS_WORKER_SCHEDULED) { cancel_delayed_work_sync(&adapter->work); adapter->flags &= ~BE_FLAGS_WORKER_SCHEDULED; -@@ -2458,6 +2483,10 @@ static int be_clear(struct be_adapter *adapter) +@@ -2459,6 +2484,10 @@ if (sriov_enabled(adapter)) be_vf_clear(adapter); @@ -115,7 +115,7 @@ be_cmd_if_destroy(adapter, adapter->if_handle, 0); be_mcc_queues_destroy(adapter); -@@ -2469,6 +2498,7 @@ static int be_clear(struct be_adapter *adapter) +@@ -2470,6 +2499,7 @@ be_cmd_fw_clean(adapter); be_msix_disable(adapter); @@ -123,7 +123,7 @@ return 0; } -@@ -2544,10 +2574,10 @@ static int be_add_mac_from_list(struct be_adapter *adapter, u8 *mac) +@@ -2545,10 +2575,10 @@ false, adapter->if_handle, pmac_id); if (!status) @@ -136,7 +136,7 @@ } do_none: return status; -@@ -2602,7 +2632,7 @@ static int be_setup(struct be_adapter *adapter) +@@ -2603,7 +2633,7 @@ } status = be_cmd_if_create(adapter, cap_flags, en_flags, netdev->dev_addr, &adapter->if_handle, @@ -145,7 +145,7 @@ if (status != 0) goto err; -@@ -3051,6 +3081,8 @@ static void be_netdev_init(struct net_device *netdev) +@@ -3052,6 +3082,8 @@ netdev->vlan_features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM; @@ -154,7 +154,7 @@ netdev->flags |= IFF_MULTICAST; netif_set_gso_max_size(netdev, 65535); -@@ -3256,6 +3288,17 @@ static int be_get_config(struct be_adapter *adapter) +@@ -3257,6 +3289,17 @@ else adapter->max_vlans = BE_NUM_VLANS_SUPPORTED; @@ -172,6 +172,3 @@ status = be_cmd_get_cntl_attributes(adapter); if (status) return status; --- -1.7.10 - diff -Nru linux-3.2.46/debian/patches/features/all/be2net/0041-be2net-Fix-number-of-vlan-slots-in-flex-mode.patch linux-3.2.46/debian/patches/features/all/be2net/0041-be2net-Fix-number-of-vlan-slots-in-flex-mode.patch --- linux-3.2.46/debian/patches/features/all/be2net/0041-be2net-Fix-number-of-vlan-slots-in-flex-mode.patch 2013-02-24 03:52:39.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/be2net/0041-be2net-Fix-number-of-vlan-slots-in-flex-mode.patch 2013-07-26 19:21:47.000000000 +0000 @@ -12,11 +12,11 @@ drivers/net/ethernet/emulex/benet/be_main.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -diff --git a/drivers/net/ethernet/emulex/benet/be_main.c b/drivers/net/ethernet/emulex/benet/be_main.c -index b8b34f5..c9a9bf0 100644 ---- a/drivers/net/ethernet/emulex/benet/be_main.c -+++ b/drivers/net/ethernet/emulex/benet/be_main.c -@@ -3284,7 +3284,7 @@ static int be_get_config(struct be_adapter *adapter) +Index: linux-3.2.46/drivers/net/ethernet/emulex/benet/be_main.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/emulex/benet/be_main.c 2013-07-26 19:21:45.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/emulex/benet/be_main.c 2013-07-26 19:21:46.000000000 +0000 +@@ -3285,7 +3285,7 @@ return status; if (adapter->function_mode & FLEX10_MODE) @@ -25,6 +25,3 @@ else adapter->max_vlans = BE_NUM_VLANS_SUPPORTED; --- -1.7.10 - diff -Nru linux-3.2.46/debian/patches/features/all/be2net/0042-be2net-fix-programming-of-VLAN-tags-for-VF.patch linux-3.2.46/debian/patches/features/all/be2net/0042-be2net-fix-programming-of-VLAN-tags-for-VF.patch --- linux-3.2.46/debian/patches/features/all/be2net/0042-be2net-fix-programming-of-VLAN-tags-for-VF.patch 2013-02-24 03:52:39.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/be2net/0042-be2net-fix-programming-of-VLAN-tags-for-VF.patch 2013-07-26 19:21:48.000000000 +0000 @@ -13,11 +13,11 @@ drivers/net/ethernet/emulex/benet/be_main.c | 23 ++++++-- 4 files changed, 157 insertions(+), 5 deletions(-) -diff --git a/drivers/net/ethernet/emulex/benet/be.h b/drivers/net/ethernet/emulex/benet/be.h -index 03fc3db..9576ac0 100644 ---- a/drivers/net/ethernet/emulex/benet/be.h -+++ b/drivers/net/ethernet/emulex/benet/be.h -@@ -303,6 +303,7 @@ struct be_vf_cfg { +Index: linux-3.2.46/drivers/net/ethernet/emulex/benet/be.h +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/emulex/benet/be.h 2013-07-26 19:21:45.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/emulex/benet/be.h 2013-07-26 19:21:47.000000000 +0000 +@@ -303,6 +303,7 @@ unsigned char mac_addr[ETH_ALEN]; int if_handle; int pmac_id; @@ -25,11 +25,11 @@ u16 vlan_tag; u32 tx_rate; }; -diff --git a/drivers/net/ethernet/emulex/benet/be_cmds.c b/drivers/net/ethernet/emulex/benet/be_cmds.c -index d72c2b4..67b030d 100644 ---- a/drivers/net/ethernet/emulex/benet/be_cmds.c -+++ b/drivers/net/ethernet/emulex/benet/be_cmds.c -@@ -2419,6 +2419,89 @@ err: +Index: linux-3.2.46/drivers/net/ethernet/emulex/benet/be_cmds.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/emulex/benet/be_cmds.c 2013-07-26 19:21:43.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/emulex/benet/be_cmds.c 2013-07-26 19:21:47.000000000 +0000 +@@ -2419,6 +2419,89 @@ return status; } @@ -119,11 +119,11 @@ int be_cmd_get_acpi_wol_cap(struct be_adapter *adapter) { struct be_mcc_wrb *wrb; -diff --git a/drivers/net/ethernet/emulex/benet/be_cmds.h b/drivers/net/ethernet/emulex/benet/be_cmds.h -index 345d49e..d5b680c 100644 ---- a/drivers/net/ethernet/emulex/benet/be_cmds.h -+++ b/drivers/net/ethernet/emulex/benet/be_cmds.h -@@ -191,6 +191,8 @@ struct be_mcc_mailbox { +Index: linux-3.2.46/drivers/net/ethernet/emulex/benet/be_cmds.h +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/emulex/benet/be_cmds.h 2013-07-26 19:21:43.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/emulex/benet/be_cmds.h 2013-07-26 19:21:47.000000000 +0000 +@@ -191,6 +191,8 @@ #define OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES 121 #define OPCODE_COMMON_GET_MAC_LIST 147 #define OPCODE_COMMON_SET_MAC_LIST 148 @@ -132,7 +132,7 @@ #define OPCODE_COMMON_READ_OBJECT 171 #define OPCODE_COMMON_WRITE_OBJECT 172 -@@ -1413,6 +1415,55 @@ struct be_cmd_req_set_mac_list { +@@ -1413,6 +1415,55 @@ struct macaddr mac[BE_MAX_MAC]; } __packed; @@ -188,7 +188,7 @@ /*************** HW Stats Get v1 **********************************/ #define BE_TXP_SW_SZ 48 struct be_port_rxf_stats_v1 { -@@ -1617,5 +1668,9 @@ extern int be_cmd_get_mac_from_list(struct be_adapter *adapter, u32 domain, +@@ -1617,5 +1668,9 @@ bool *pmac_id_active, u32 *pmac_id, u8 *mac); extern int be_cmd_set_mac_list(struct be_adapter *adapter, u8 *mac_array, u8 mac_count, u32 domain); @@ -198,11 +198,11 @@ + u32 domain, u16 intf_id); extern int be_cmd_get_acpi_wol_cap(struct be_adapter *adapter); -diff --git a/drivers/net/ethernet/emulex/benet/be_main.c b/drivers/net/ethernet/emulex/benet/be_main.c -index c9a9bf0..2e54335 100644 ---- a/drivers/net/ethernet/emulex/benet/be_main.c -+++ b/drivers/net/ethernet/emulex/benet/be_main.c -@@ -970,14 +970,21 @@ static int be_set_vf_vlan(struct net_device *netdev, +Index: linux-3.2.46/drivers/net/ethernet/emulex/benet/be_main.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/emulex/benet/be_main.c 2013-07-26 19:21:46.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/emulex/benet/be_main.c 2013-07-26 19:21:47.000000000 +0000 +@@ -971,14 +971,21 @@ return -EINVAL; if (vlan) { @@ -228,7 +228,7 @@ if (status) dev_info(&adapter->pdev->dev, -@@ -2517,7 +2524,7 @@ static int be_vf_setup(struct be_adapter *adapter) +@@ -2518,7 +2525,7 @@ { struct be_vf_cfg *vf_cfg; u32 cap_flags, en_flags, vf; @@ -237,7 +237,7 @@ int status; be_vf_setup_init(adapter); -@@ -2541,6 +2548,12 @@ static int be_vf_setup(struct be_adapter *adapter) +@@ -2542,6 +2549,12 @@ if (status) goto err; vf_cfg->tx_rate = lnk_speed * 10; @@ -250,6 +250,3 @@ } return 0; err: --- -1.7.10 - diff -Nru linux-3.2.46/debian/patches/features/all/be2net/0043-be2net-fix-ethtool-get-settings.patch linux-3.2.46/debian/patches/features/all/be2net/0043-be2net-fix-ethtool-get-settings.patch --- linux-3.2.46/debian/patches/features/all/be2net/0043-be2net-fix-ethtool-get-settings.patch 2013-02-24 03:52:39.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/be2net/0043-be2net-fix-ethtool-get-settings.patch 2013-07-26 19:21:50.000000000 +0000 @@ -17,11 +17,11 @@ drivers/net/ethernet/emulex/benet/be_main.c | 20 +- 5 files changed, 239 insertions(+), 102 deletions(-) -diff --git a/drivers/net/ethernet/emulex/benet/be.h b/drivers/net/ethernet/emulex/benet/be.h -index 9576ac0..ad69cf8 100644 ---- a/drivers/net/ethernet/emulex/benet/be.h -+++ b/drivers/net/ethernet/emulex/benet/be.h -@@ -313,6 +313,23 @@ struct be_vf_cfg { +Index: linux-3.2.46/drivers/net/ethernet/emulex/benet/be.h +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/emulex/benet/be.h 2013-07-26 19:21:47.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/emulex/benet/be.h 2013-07-26 19:21:49.000000000 +0000 +@@ -313,6 +313,23 @@ #define BE_UC_PMAC_COUNT 30 #define BE_VF_UC_PMAC_COUNT 2 @@ -45,7 +45,7 @@ struct be_adapter { struct pci_dev *pdev; struct net_device *netdev; -@@ -377,10 +394,6 @@ struct be_adapter { +@@ -377,10 +394,6 @@ u32 rx_fc; /* Rx flow control */ u32 tx_fc; /* Tx flow control */ bool stats_cmd_sent; @@ -56,7 +56,7 @@ u8 generation; /* BladeEngine ASIC generation */ u32 flash_status; struct completion flash_compl; -@@ -392,6 +405,7 @@ struct be_adapter { +@@ -392,6 +405,7 @@ u32 sli_family; u8 hba_port_num; u16 pvid; @@ -64,17 +64,17 @@ u8 wol_cap; bool wol; u32 max_pmac_cnt; /* Max secondary UC MACs programmable */ -@@ -583,4 +597,5 @@ extern void be_link_status_update(struct be_adapter *adapter, u8 link_status); +@@ -583,4 +597,5 @@ extern void be_parse_stats(struct be_adapter *adapter); extern int be_load_fw(struct be_adapter *adapter, u8 *func); extern bool be_is_wol_supported(struct be_adapter *adapter); +extern bool be_pause_supported(struct be_adapter *adapter); #endif /* BE_H */ -diff --git a/drivers/net/ethernet/emulex/benet/be_cmds.c b/drivers/net/ethernet/emulex/benet/be_cmds.c -index 67b030d..22be08c 100644 ---- a/drivers/net/ethernet/emulex/benet/be_cmds.c -+++ b/drivers/net/ethernet/emulex/benet/be_cmds.c -@@ -126,7 +126,7 @@ static void be_async_link_state_process(struct be_adapter *adapter, +Index: linux-3.2.46/drivers/net/ethernet/emulex/benet/be_cmds.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/emulex/benet/be_cmds.c 2013-07-26 19:21:47.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/emulex/benet/be_cmds.c 2013-07-26 19:21:49.000000000 +0000 +@@ -126,7 +126,7 @@ struct be_async_event_link_state *evt) { /* When link status changes, link speed must be re-queried from FW */ @@ -83,7 +83,7 @@ /* For the initial link status do not rely on the ASYNC event as * it may not be received in some cases. -@@ -153,7 +153,7 @@ static void be_async_grp5_qos_speed_process(struct be_adapter *adapter, +@@ -153,7 +153,7 @@ { if (evt->physical_port == adapter->port_num) { /* qos_link_speed is in units of 10 Mbps */ @@ -92,7 +92,7 @@ } } -@@ -2136,8 +2136,7 @@ err: +@@ -2136,8 +2136,7 @@ return status; } @@ -102,7 +102,7 @@ { struct be_mcc_wrb *wrb; struct be_cmd_req_get_phy_info *req; -@@ -2170,9 +2169,15 @@ int be_cmd_get_phy_info(struct be_adapter *adapter, +@@ -2170,9 +2169,15 @@ if (!status) { struct be_phy_info *resp_phy_info = cmd.va + sizeof(struct be_cmd_req_hdr); @@ -120,11 +120,11 @@ } pci_free_consistent(adapter->pdev, cmd.size, cmd.va, cmd.dma); -diff --git a/drivers/net/ethernet/emulex/benet/be_cmds.h b/drivers/net/ethernet/emulex/benet/be_cmds.h -index d5b680c..3c54361 100644 ---- a/drivers/net/ethernet/emulex/benet/be_cmds.h -+++ b/drivers/net/ethernet/emulex/benet/be_cmds.h -@@ -1309,9 +1309,36 @@ enum { +Index: linux-3.2.46/drivers/net/ethernet/emulex/benet/be_cmds.h +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/emulex/benet/be_cmds.h 2013-07-26 19:21:47.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/emulex/benet/be_cmds.h 2013-07-26 19:21:49.000000000 +0000 +@@ -1309,9 +1309,36 @@ PHY_TYPE_KX4_10GB, PHY_TYPE_BASET_10GB, PHY_TYPE_BASET_1GB, @@ -161,7 +161,7 @@ struct be_cmd_req_get_phy_info { struct be_cmd_req_hdr hdr; u8 rsvd0[24]; -@@ -1321,7 +1348,11 @@ struct be_phy_info { +@@ -1321,7 +1348,11 @@ u16 phy_type; u16 interface_type; u32 misc_params; @@ -174,7 +174,7 @@ }; struct be_cmd_resp_get_phy_info { -@@ -1655,8 +1686,7 @@ extern int be_cmd_get_seeprom_data(struct be_adapter *adapter, +@@ -1655,8 +1686,7 @@ struct be_dma_mem *nonemb_cmd); extern int be_cmd_set_loopback(struct be_adapter *adapter, u8 port_num, u8 loopback_type, u8 enable); @@ -184,11 +184,11 @@ extern int be_cmd_set_qos(struct be_adapter *adapter, u32 bps, u32 domain); extern void be_detect_dump_ue(struct be_adapter *adapter); extern int be_cmd_get_die_temperature(struct be_adapter *adapter); -diff --git a/drivers/net/ethernet/emulex/benet/be_ethtool.c b/drivers/net/ethernet/emulex/benet/be_ethtool.c -index e0eb995..076adeb 100644 ---- a/drivers/net/ethernet/emulex/benet/be_ethtool.c -+++ b/drivers/net/ethernet/emulex/benet/be_ethtool.c -@@ -433,102 +433,193 @@ static int be_get_sset_count(struct net_device *netdev, int stringset) +Index: linux-3.2.46/drivers/net/ethernet/emulex/benet/be_ethtool.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/emulex/benet/be_ethtool.c 2013-07-26 19:21:43.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/emulex/benet/be_ethtool.c 2013-07-26 19:21:49.000000000 +0000 +@@ -433,102 +433,193 @@ } } @@ -363,6 +363,11 @@ - ecmd->port = PORT_TP; - break; - } +- +- switch (phy_info.interface_type) { +- case PHY_TYPE_KR_10GB: +- case PHY_TYPE_KX4_10GB: +- ecmd->autoneg = AUTONEG_ENABLE; + ethtool_cmd_speed_set(ecmd, et_speed); + + status = be_cmd_get_phy_info(adapter); @@ -376,11 +381,7 @@ + ecmd->advertising = + convert_to_et_setting(adapter->phy.interface_type, + adapter->phy.auto_speeds_supported); - -- switch (phy_info.interface_type) { -- case PHY_TYPE_KR_10GB: -- case PHY_TYPE_KX4_10GB: -- ecmd->autoneg = AUTONEG_ENABLE; ++ + ecmd->port = be_get_port_type(adapter->phy.interface_type, + adapter->phy.dac_cable_len); + @@ -458,7 +459,7 @@ return 0; } -@@ -548,7 +639,7 @@ be_get_pauseparam(struct net_device *netdev, struct ethtool_pauseparam *ecmd) +@@ -548,7 +639,7 @@ struct be_adapter *adapter = netdev_priv(netdev); be_cmd_get_flow_control(adapter, &ecmd->tx_pause, &ecmd->rx_pause); @@ -467,11 +468,11 @@ } static int -diff --git a/drivers/net/ethernet/emulex/benet/be_main.c b/drivers/net/ethernet/emulex/benet/be_main.c -index 2e54335..376a2fa 100644 ---- a/drivers/net/ethernet/emulex/benet/be_main.c -+++ b/drivers/net/ethernet/emulex/benet/be_main.c -@@ -2563,11 +2563,12 @@ err: +Index: linux-3.2.46/drivers/net/ethernet/emulex/benet/be_main.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/emulex/benet/be_main.c 2013-07-26 19:21:47.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/emulex/benet/be_main.c 2013-07-26 19:21:49.000000000 +0000 +@@ -2564,11 +2564,12 @@ static void be_setup_init(struct be_adapter *adapter) { adapter->vlan_prio_bmap = 0xff; @@ -485,7 +486,7 @@ } static int be_add_mac_from_list(struct be_adapter *adapter, u8 *mac) -@@ -2699,6 +2700,10 @@ static int be_setup(struct be_adapter *adapter) +@@ -2700,6 +2701,10 @@ goto err; } @@ -496,7 +497,7 @@ schedule_delayed_work(&adapter->work, msecs_to_jiffies(1000)); adapter->flags |= BE_FLAGS_WORKER_SCHEDULED; -@@ -2752,17 +2757,8 @@ static bool be_flash_redboot(struct be_adapter *adapter, +@@ -2753,17 +2758,8 @@ static bool phy_flashing_required(struct be_adapter *adapter) { @@ -516,6 +517,3 @@ } static int be_flash_data(struct be_adapter *adapter, --- -1.7.10 - diff -Nru linux-3.2.46/debian/patches/features/all/be2net/0044-be2net-Fix-VLAN-multicast-packet-reception.patch linux-3.2.46/debian/patches/features/all/be2net/0044-be2net-Fix-VLAN-multicast-packet-reception.patch --- linux-3.2.46/debian/patches/features/all/be2net/0044-be2net-Fix-VLAN-multicast-packet-reception.patch 2013-02-24 03:52:39.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/be2net/0044-be2net-Fix-VLAN-multicast-packet-reception.patch 2013-07-26 19:21:51.000000000 +0000 @@ -17,11 +17,11 @@ drivers/net/ethernet/emulex/benet/be_main.c | 44 ++++++++++++++++++--------- 1 file changed, 30 insertions(+), 14 deletions(-) -diff --git a/drivers/net/ethernet/emulex/benet/be_main.c b/drivers/net/ethernet/emulex/benet/be_main.c -index 376a2fa..34b8ad2 100644 ---- a/drivers/net/ethernet/emulex/benet/be_main.c -+++ b/drivers/net/ethernet/emulex/benet/be_main.c -@@ -797,22 +797,30 @@ static int be_vid_config(struct be_adapter *adapter, bool vf, u32 vf_num) +Index: linux-3.2.46/drivers/net/ethernet/emulex/benet/be_main.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/emulex/benet/be_main.c 2013-07-26 19:21:49.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/emulex/benet/be_main.c 2013-07-26 19:21:50.000000000 +0000 +@@ -798,22 +798,30 @@ if (adapter->promiscuous) return 0; @@ -65,7 +65,7 @@ } static void be_vlan_add_vid(struct net_device *netdev, u16 vid) -@@ -854,6 +862,7 @@ static void be_vlan_rem_vid(struct net_device *netdev, u16 vid) +@@ -855,6 +863,7 @@ static void be_set_rx_mode(struct net_device *netdev) { struct be_adapter *adapter = netdev_priv(netdev); @@ -73,7 +73,7 @@ if (netdev->flags & IFF_PROMISC) { be_cmd_rx_filter(adapter, IFF_PROMISC, ON); -@@ -900,7 +909,14 @@ static void be_set_rx_mode(struct net_device *netdev) +@@ -901,7 +910,14 @@ } } @@ -89,6 +89,3 @@ done: return; } --- -1.7.10 - diff -Nru linux-3.2.46/debian/patches/features/all/be2net/0045-be2net-Fix-FW-download-in-Lancer.patch linux-3.2.46/debian/patches/features/all/be2net/0045-be2net-Fix-FW-download-in-Lancer.patch --- linux-3.2.46/debian/patches/features/all/be2net/0045-be2net-Fix-FW-download-in-Lancer.patch 2013-02-24 03:52:39.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/be2net/0045-be2net-Fix-FW-download-in-Lancer.patch 2013-07-26 19:21:52.000000000 +0000 @@ -13,11 +13,11 @@ drivers/net/ethernet/emulex/benet/be_cmds.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) -diff --git a/drivers/net/ethernet/emulex/benet/be_cmds.c b/drivers/net/ethernet/emulex/benet/be_cmds.c -index 22be08c..3ba4aed 100644 ---- a/drivers/net/ethernet/emulex/benet/be_cmds.c -+++ b/drivers/net/ethernet/emulex/benet/be_cmds.c -@@ -1824,18 +1824,16 @@ int lancer_cmd_write_object(struct be_adapter *adapter, struct be_dma_mem *cmd, +Index: linux-3.2.46/drivers/net/ethernet/emulex/benet/be_cmds.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/emulex/benet/be_cmds.c 2013-07-26 19:21:49.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/emulex/benet/be_cmds.c 2013-07-26 19:21:51.000000000 +0000 +@@ -1824,18 +1824,16 @@ spin_unlock_bh(&adapter->mcc_lock); if (!wait_for_completion_timeout(&adapter->flash_compl, @@ -39,6 +39,3 @@ return status; --- -1.7.10 - diff -Nru linux-3.2.46/debian/patches/features/all/be2net/0046-be2net-Fix-ethtool-self-test-for-Lancer.patch linux-3.2.46/debian/patches/features/all/be2net/0046-be2net-Fix-ethtool-self-test-for-Lancer.patch --- linux-3.2.46/debian/patches/features/all/be2net/0046-be2net-Fix-ethtool-self-test-for-Lancer.patch 2013-02-24 03:52:39.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/be2net/0046-be2net-Fix-ethtool-self-test-for-Lancer.patch 2013-07-26 19:21:54.000000000 +0000 @@ -13,11 +13,11 @@ drivers/net/ethernet/emulex/benet/be_ethtool.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -diff --git a/drivers/net/ethernet/emulex/benet/be_ethtool.c b/drivers/net/ethernet/emulex/benet/be_ethtool.c -index 076adeb..9d71bad 100644 ---- a/drivers/net/ethernet/emulex/benet/be_ethtool.c -+++ b/drivers/net/ethernet/emulex/benet/be_ethtool.c -@@ -793,7 +793,7 @@ be_self_test(struct net_device *netdev, struct ethtool_test *test, u64 *data) +Index: linux-3.2.46/drivers/net/ethernet/emulex/benet/be_ethtool.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/emulex/benet/be_ethtool.c 2013-07-26 19:21:49.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/emulex/benet/be_ethtool.c 2013-07-26 19:21:53.000000000 +0000 +@@ -793,7 +793,7 @@ } } @@ -26,6 +26,3 @@ data[3] = 1; test->flags |= ETH_TEST_FL_FAILED; } --- -1.7.10 - diff -Nru linux-3.2.46/debian/patches/features/all/be2net/0047-be2net-Fix-traffic-stall-INTx-mode.patch linux-3.2.46/debian/patches/features/all/be2net/0047-be2net-Fix-traffic-stall-INTx-mode.patch --- linux-3.2.46/debian/patches/features/all/be2net/0047-be2net-Fix-traffic-stall-INTx-mode.patch 2013-02-24 03:52:39.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/be2net/0047-be2net-Fix-traffic-stall-INTx-mode.patch 2013-07-26 19:21:55.000000000 +0000 @@ -16,11 +16,11 @@ drivers/net/ethernet/emulex/benet/be_main.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) -diff --git a/drivers/net/ethernet/emulex/benet/be_main.c b/drivers/net/ethernet/emulex/benet/be_main.c -index 34b8ad2..915b95e 100644 ---- a/drivers/net/ethernet/emulex/benet/be_main.c -+++ b/drivers/net/ethernet/emulex/benet/be_main.c -@@ -1563,7 +1563,9 @@ static int event_handle(struct be_eq_obj *eqo) +Index: linux-3.2.46/drivers/net/ethernet/emulex/benet/be_main.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/emulex/benet/be_main.c 2013-07-26 19:21:50.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/emulex/benet/be_main.c 2013-07-26 19:21:54.000000000 +0000 +@@ -1564,7 +1564,9 @@ if (!num) rearm = true; @@ -31,6 +31,3 @@ if (num) napi_schedule(&eqo->napi); --- -1.7.10 - diff -Nru linux-3.2.46/debian/patches/features/all/be2net/0048-be2net-Fix-Lancer-statistics.patch linux-3.2.46/debian/patches/features/all/be2net/0048-be2net-Fix-Lancer-statistics.patch --- linux-3.2.46/debian/patches/features/all/be2net/0048-be2net-Fix-Lancer-statistics.patch 2013-02-24 03:52:39.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/be2net/0048-be2net-Fix-Lancer-statistics.patch 2013-07-26 19:21:56.000000000 +0000 @@ -14,11 +14,11 @@ drivers/net/ethernet/emulex/benet/be_main.c | 5 +++++ 2 files changed, 6 insertions(+), 1 deletion(-) -diff --git a/drivers/net/ethernet/emulex/benet/be_cmds.c b/drivers/net/ethernet/emulex/benet/be_cmds.c -index 3ba4aed..4e07e58 100644 ---- a/drivers/net/ethernet/emulex/benet/be_cmds.c -+++ b/drivers/net/ethernet/emulex/benet/be_cmds.c -@@ -1221,7 +1221,7 @@ int lancer_cmd_get_pport_stats(struct be_adapter *adapter, +Index: linux-3.2.46/drivers/net/ethernet/emulex/benet/be_cmds.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/emulex/benet/be_cmds.c 2013-07-26 19:21:51.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/emulex/benet/be_cmds.c 2013-07-26 19:21:55.000000000 +0000 +@@ -1221,7 +1221,7 @@ OPCODE_ETH_GET_PPORT_STATS, nonemb_cmd->size, wrb, nonemb_cmd); @@ -27,11 +27,11 @@ req->cmd_params.params.reset_stats = 0; be_mcc_notify(adapter); -diff --git a/drivers/net/ethernet/emulex/benet/be_main.c b/drivers/net/ethernet/emulex/benet/be_main.c -index 915b95e..9b1c03e 100644 ---- a/drivers/net/ethernet/emulex/benet/be_main.c -+++ b/drivers/net/ethernet/emulex/benet/be_main.c -@@ -421,6 +421,9 @@ void be_parse_stats(struct be_adapter *adapter) +Index: linux-3.2.46/drivers/net/ethernet/emulex/benet/be_main.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/emulex/benet/be_main.c 2013-07-26 19:21:54.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/emulex/benet/be_main.c 2013-07-26 19:21:55.000000000 +0000 +@@ -421,6 +421,9 @@ populate_be2_stats(adapter); } @@ -41,7 +41,7 @@ /* as erx_v1 is longer than v0, ok to use v1 defn for v0 access */ for_all_rx_queues(adapter, rxo, i) { /* below erx HW counter can actually wrap around after -@@ -429,6 +432,8 @@ void be_parse_stats(struct be_adapter *adapter) +@@ -429,6 +432,8 @@ accumulate_16bit_val(&rx_stats(rxo)->rx_drops_no_frags, (u16)erx->rx_drops_no_fragments[rxo->q.id]); } @@ -50,6 +50,3 @@ } static struct rtnl_link_stats64 *be_get_stats64(struct net_device *netdev, --- -1.7.10 - diff -Nru linux-3.2.46/debian/patches/features/all/be2net/0049-be2net-Fix-wrong-status-getting-returned-for-MCC-com.patch linux-3.2.46/debian/patches/features/all/be2net/0049-be2net-Fix-wrong-status-getting-returned-for-MCC-com.patch --- linux-3.2.46/debian/patches/features/all/be2net/0049-be2net-Fix-wrong-status-getting-returned-for-MCC-com.patch 2013-02-24 03:52:39.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/be2net/0049-be2net-Fix-wrong-status-getting-returned-for-MCC-com.patch 2013-07-26 19:21:58.000000000 +0000 @@ -19,11 +19,11 @@ drivers/net/ethernet/emulex/benet/be_cmds.h | 8 ++- 3 files changed, 67 insertions(+), 27 deletions(-) -diff --git a/drivers/net/ethernet/emulex/benet/be.h b/drivers/net/ethernet/emulex/benet/be.h -index ad69cf8..4bc18ef 100644 ---- a/drivers/net/ethernet/emulex/benet/be.h -+++ b/drivers/net/ethernet/emulex/benet/be.h -@@ -162,6 +162,11 @@ static inline void queue_head_inc(struct be_queue_info *q) +Index: linux-3.2.46/drivers/net/ethernet/emulex/benet/be.h +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/emulex/benet/be.h 2013-07-26 19:21:49.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/emulex/benet/be.h 2013-07-26 19:21:57.000000000 +0000 +@@ -162,6 +162,11 @@ index_inc(&q->head, q->len); } @@ -35,11 +35,11 @@ static inline void queue_tail_inc(struct be_queue_info *q) { index_inc(&q->tail, q->len); -diff --git a/drivers/net/ethernet/emulex/benet/be_cmds.c b/drivers/net/ethernet/emulex/benet/be_cmds.c -index 4e07e58..2673081 100644 ---- a/drivers/net/ethernet/emulex/benet/be_cmds.c -+++ b/drivers/net/ethernet/emulex/benet/be_cmds.c -@@ -61,10 +61,21 @@ static inline void be_mcc_compl_use(struct be_mcc_compl *compl) +Index: linux-3.2.46/drivers/net/ethernet/emulex/benet/be_cmds.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/emulex/benet/be_cmds.c 2013-07-26 19:21:55.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/emulex/benet/be_cmds.c 2013-07-26 19:21:57.000000000 +0000 +@@ -61,10 +61,21 @@ compl->flags = 0; } @@ -62,7 +62,7 @@ /* Just swap the status to host endian; mcc tag is opaquely copied * from mcc_wrb */ -@@ -73,32 +84,36 @@ static int be_mcc_compl_process(struct be_adapter *adapter, +@@ -73,32 +84,36 @@ compl_status = (compl->status >> CQE_STATUS_COMPL_SHIFT) & CQE_STATUS_COMPL_MASK; @@ -112,7 +112,7 @@ be_get_temp_freq = 0; if (compl_status == MCC_STATUS_NOT_SUPPORTED || -@@ -108,13 +123,13 @@ static int be_mcc_compl_process(struct be_adapter *adapter, +@@ -108,13 +123,13 @@ if (compl_status == MCC_STATUS_UNAUTHORIZED_REQUEST) { dev_warn(&adapter->pdev->dev, "This domain(VM) is not " "permitted to execute this cmd (opcode %d)\n", @@ -128,7 +128,7 @@ } } done: -@@ -286,7 +301,7 @@ static int be_mcc_wait_compl(struct be_adapter *adapter) +@@ -286,7 +301,7 @@ if (i == mcc_timeout) { dev_err(&adapter->pdev->dev, "FW not responding\n"); adapter->fw_timeout = true; @@ -137,7 +137,7 @@ } return status; } -@@ -294,8 +309,26 @@ static int be_mcc_wait_compl(struct be_adapter *adapter) +@@ -294,8 +309,26 @@ /* Notify MCC requests and wait for completion */ static int be_mcc_notify_wait(struct be_adapter *adapter) { @@ -165,7 +165,7 @@ } static int be_mbox_db_ready_wait(struct be_adapter *adapter, void __iomem *db) -@@ -435,14 +468,17 @@ static void be_wrb_cmd_hdr_prepare(struct be_cmd_req_hdr *req_hdr, +@@ -435,14 +468,17 @@ struct be_mcc_wrb *wrb, struct be_dma_mem *mem) { struct be_sge *sge; @@ -185,7 +185,7 @@ wrb->payload_length = cmd_len; if (mem) { wrb->embedded |= (1 & MCC_WRB_SGE_CNT_MASK) << -@@ -1283,13 +1319,10 @@ int be_cmd_get_die_temperature(struct be_adapter *adapter) +@@ -1283,13 +1319,10 @@ { struct be_mcc_wrb *wrb; struct be_cmd_req_get_cntl_addnl_attribs *req; @@ -199,7 +199,7 @@ wrb = wrb_from_mccq(adapter); if (!wrb) { status = -EBUSY; -@@ -1301,8 +1334,6 @@ int be_cmd_get_die_temperature(struct be_adapter *adapter) +@@ -1301,8 +1334,6 @@ OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES, sizeof(*req), wrb, NULL); @@ -208,11 +208,11 @@ be_mcc_notify(adapter); err: -diff --git a/drivers/net/ethernet/emulex/benet/be_cmds.h b/drivers/net/ethernet/emulex/benet/be_cmds.h -index 3c54361..944f031 100644 ---- a/drivers/net/ethernet/emulex/benet/be_cmds.h -+++ b/drivers/net/ethernet/emulex/benet/be_cmds.h -@@ -225,8 +225,12 @@ struct be_cmd_req_hdr { +Index: linux-3.2.46/drivers/net/ethernet/emulex/benet/be_cmds.h +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/emulex/benet/be_cmds.h 2013-07-26 19:21:49.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/emulex/benet/be_cmds.h 2013-07-26 19:21:57.000000000 +0000 +@@ -225,8 +225,12 @@ #define RESP_HDR_INFO_OPCODE_SHIFT 0 /* bits 0 - 7 */ #define RESP_HDR_INFO_SUBSYS_SHIFT 8 /* bits 8 - 15 */ struct be_cmd_resp_hdr { @@ -227,6 +227,3 @@ u32 response_length; /* dword 2 */ u32 actual_resp_len; /* dword 3 */ }; --- -1.7.10 - diff -Nru linux-3.2.46/debian/patches/features/all/be2net/0050-be2net-Fix-FW-download-for-BE.patch linux-3.2.46/debian/patches/features/all/be2net/0050-be2net-Fix-FW-download-for-BE.patch --- linux-3.2.46/debian/patches/features/all/be2net/0050-be2net-Fix-FW-download-for-BE.patch 2013-02-24 03:52:39.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/be2net/0050-be2net-Fix-FW-download-for-BE.patch 2013-07-26 19:21:59.000000000 +0000 @@ -16,11 +16,11 @@ drivers/net/ethernet/emulex/benet/be_main.c | 168 ++++++++++++++++++--------- 3 files changed, 166 insertions(+), 78 deletions(-) -diff --git a/drivers/net/ethernet/emulex/benet/be_cmds.c b/drivers/net/ethernet/emulex/benet/be_cmds.c -index 2673081..43167e8 100644 ---- a/drivers/net/ethernet/emulex/benet/be_cmds.c -+++ b/drivers/net/ethernet/emulex/benet/be_cmds.c -@@ -1979,7 +1979,7 @@ int be_cmd_get_flash_crc(struct be_adapter *adapter, u8 *flashed_crc, +Index: linux-3.2.46/drivers/net/ethernet/emulex/benet/be_cmds.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/emulex/benet/be_cmds.c 2013-07-26 19:21:57.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/emulex/benet/be_cmds.c 2013-07-26 19:21:58.000000000 +0000 +@@ -1979,7 +1979,7 @@ be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, OPCODE_COMMON_READ_FLASHROM, sizeof(*req)+4, wrb, NULL); @@ -29,10 +29,10 @@ req->params.op_code = cpu_to_le32(FLASHROM_OPER_REPORT); req->params.offset = cpu_to_le32(offset); req->params.data_buf_size = cpu_to_le32(0x4); -diff --git a/drivers/net/ethernet/emulex/benet/be_hw.h b/drivers/net/ethernet/emulex/benet/be_hw.h -index f2c89e3..0949aa6 100644 ---- a/drivers/net/ethernet/emulex/benet/be_hw.h -+++ b/drivers/net/ethernet/emulex/benet/be_hw.h +Index: linux-3.2.46/drivers/net/ethernet/emulex/benet/be_hw.h +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/emulex/benet/be_hw.h 2013-07-26 18:55:06.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/emulex/benet/be_hw.h 2013-07-26 19:21:58.000000000 +0000 @@ -162,22 +162,23 @@ #define QUERY_FAT 1 @@ -92,7 +92,7 @@ /************* Rx Packet Type Encoding **************/ #define BE_UNICAST_PACKET 0 #define BE_MULTICAST_PACKET 1 -@@ -445,6 +464,7 @@ struct flash_comp { +@@ -445,6 +464,7 @@ unsigned long offset; int optype; int size; @@ -100,7 +100,7 @@ }; struct image_hdr { -@@ -481,17 +501,19 @@ struct flash_section_hdr { +@@ -481,17 +501,19 @@ u32 format_rev; u32 cksum; u32 antidote; @@ -131,7 +131,7 @@ struct flash_section_entry { u32 type; -@@ -503,10 +525,16 @@ struct flash_section_entry { +@@ -503,10 +525,16 @@ u32 rsvd0; u32 rsvd1; u8 ver_data[32]; @@ -150,11 +150,11 @@ + struct flash_section_hdr_g2 fsec_hdr; + struct flash_section_entry fsec_entry[32]; +} __packed; -diff --git a/drivers/net/ethernet/emulex/benet/be_main.c b/drivers/net/ethernet/emulex/benet/be_main.c -index 9b1c03e..730fb1b 100644 ---- a/drivers/net/ethernet/emulex/benet/be_main.c -+++ b/drivers/net/ethernet/emulex/benet/be_main.c -@@ -2751,6 +2751,8 @@ static void be_netpoll(struct net_device *netdev) +Index: linux-3.2.46/drivers/net/ethernet/emulex/benet/be_main.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/emulex/benet/be_main.c 2013-07-26 19:21:55.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/emulex/benet/be_main.c 2013-07-26 19:21:58.000000000 +0000 +@@ -2752,6 +2752,8 @@ #endif #define FW_FILE_HDR_SIGN "ServerEngines Corp. " @@ -163,7 +163,7 @@ static bool be_flash_redboot(struct be_adapter *adapter, const u8 *p, u32 img_start, int image_size, int hdr_size) -@@ -2784,58 +2786,101 @@ static bool phy_flashing_required(struct be_adapter *adapter) +@@ -2785,58 +2787,101 @@ adapter->phy.interface_type == PHY_TYPE_BASET_10GB); } @@ -222,7 +222,9 @@ struct be_cmd_write_flashrom *req = flash_cmd->va; const struct flash_comp *pflashcomp; - int num_comp; -- ++ int num_comp, hdr_size; ++ struct flash_section_info *fsec = NULL; + - static const struct flash_comp gen3_flash_types[10] = { - { FLASH_iSCSI_PRIMARY_IMAGE_START_g3, IMG_TYPE_ISCSI_ACTIVE, - FLASH_IMAGE_MAX_SIZE_g3}, @@ -244,9 +246,6 @@ - FLASH_NCSI_IMAGE_MAX_SIZE_g3}, - { FLASH_PHY_FW_START_g3, IMG_TYPE_PHY_FW, - FLASH_PHY_FW_IMAGE_MAX_SIZE_g3} -+ int num_comp, hdr_size; -+ struct flash_section_info *fsec = NULL; -+ + struct flash_comp gen3_flash_types[] = { + { FLASH_iSCSI_PRIMARY_IMAGE_START_g3, OPTYPE_ISCSI_ACTIVE, + FLASH_IMAGE_MAX_SIZE_g3, IMAGE_FIRMWARE_iSCSI}, @@ -307,7 +306,7 @@ }; if (adapter->generation == BE_GEN3) { -@@ -2847,22 +2892,37 @@ static int be_flash_data(struct be_adapter *adapter, +@@ -2848,22 +2893,37 @@ filehdr_size = sizeof(struct flash_file_hdr_g2); num_comp = ARRAY_SIZE(gen2_flash_types); } @@ -354,7 +353,7 @@ if (p + pflashcomp[i].size > fw->data + fw->size) return -1; total_bytes = pflashcomp[i].size; -@@ -2873,12 +2933,12 @@ static int be_flash_data(struct be_adapter *adapter, +@@ -2874,12 +2934,12 @@ num_bytes = total_bytes; total_bytes -= num_bytes; if (!total_bytes) { @@ -369,7 +368,7 @@ flash_op = FLASHROM_OPER_PHY_SAVE; else flash_op = FLASHROM_OPER_SAVE; -@@ -2890,7 +2950,7 @@ static int be_flash_data(struct be_adapter *adapter, +@@ -2891,7 +2951,7 @@ if (status) { if ((status == ILLEGAL_IOCTL_REQ) && (pflashcomp[i].optype == @@ -378,6 +377,3 @@ break; dev_err(&adapter->pdev->dev, "cmd to write to flash rom failed.\n"); --- -1.7.10 - diff -Nru linux-3.2.46/debian/patches/features/all/be2net/0051-be2net-Ignore-status-of-some-ioctls-during-driver-lo.patch linux-3.2.46/debian/patches/features/all/be2net/0051-be2net-Ignore-status-of-some-ioctls-during-driver-lo.patch --- linux-3.2.46/debian/patches/features/all/be2net/0051-be2net-Ignore-status-of-some-ioctls-during-driver-lo.patch 2013-02-24 03:52:39.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/be2net/0051-be2net-Ignore-status-of-some-ioctls-during-driver-lo.patch 2013-07-26 19:22:00.000000000 +0000 @@ -11,11 +11,11 @@ drivers/net/ethernet/emulex/benet/be_main.c | 17 ++++------------- 1 file changed, 4 insertions(+), 13 deletions(-) -diff --git a/drivers/net/ethernet/emulex/benet/be_main.c b/drivers/net/ethernet/emulex/benet/be_main.c -index 730fb1b..9effea4 100644 ---- a/drivers/net/ethernet/emulex/benet/be_main.c -+++ b/drivers/net/ethernet/emulex/benet/be_main.c -@@ -2696,24 +2696,15 @@ static int be_setup(struct be_adapter *adapter) +Index: linux-3.2.46/drivers/net/ethernet/emulex/benet/be_main.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/emulex/benet/be_main.c 2013-07-26 19:21:58.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/emulex/benet/be_main.c 2013-07-26 19:22:00.000000000 +0000 +@@ -2697,24 +2697,15 @@ be_cmd_get_fw_ver(adapter, adapter->fw_ver, NULL); @@ -44,6 +44,3 @@ pcie_set_readrq(adapter->pdev, 4096); --- -1.7.10 - diff -Nru linux-3.2.46/debian/patches/features/all/be2net/0052-be2net-fix-speed-displayed-by-ethtool-on-certain-SKU.patch linux-3.2.46/debian/patches/features/all/be2net/0052-be2net-fix-speed-displayed-by-ethtool-on-certain-SKU.patch --- linux-3.2.46/debian/patches/features/all/be2net/0052-be2net-fix-speed-displayed-by-ethtool-on-certain-SKU.patch 2013-02-24 03:52:39.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/be2net/0052-be2net-fix-speed-displayed-by-ethtool-on-certain-SKU.patch 2013-07-26 19:22:02.000000000 +0000 @@ -12,11 +12,11 @@ drivers/net/ethernet/emulex/benet/be_ethtool.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -diff --git a/drivers/net/ethernet/emulex/benet/be_ethtool.c b/drivers/net/ethernet/emulex/benet/be_ethtool.c -index 9d71bad..b3b5fae 100644 ---- a/drivers/net/ethernet/emulex/benet/be_ethtool.c -+++ b/drivers/net/ethernet/emulex/benet/be_ethtool.c -@@ -557,7 +557,7 @@ static int be_get_settings(struct net_device *netdev, struct ethtool_cmd *ecmd) +Index: linux-3.2.46/drivers/net/ethernet/emulex/benet/be_ethtool.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/emulex/benet/be_ethtool.c 2013-07-26 19:21:53.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/emulex/benet/be_ethtool.c 2013-07-26 19:22:01.000000000 +0000 +@@ -557,7 +557,7 @@ if (!status) be_link_status_update(adapter, link_status); if (link_speed) @@ -25,6 +25,3 @@ else et_speed = convert_to_et_speed(port_speed); } else { --- -1.7.10 - diff -Nru linux-3.2.46/debian/patches/features/all/be2net/0053-be2net-update-the-driver-version.patch linux-3.2.46/debian/patches/features/all/be2net/0053-be2net-update-the-driver-version.patch --- linux-3.2.46/debian/patches/features/all/be2net/0053-be2net-update-the-driver-version.patch 2013-02-24 03:52:39.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/be2net/0053-be2net-update-the-driver-version.patch 2013-07-26 19:22:03.000000000 +0000 @@ -10,10 +10,10 @@ drivers/net/ethernet/emulex/benet/be.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -diff --git a/drivers/net/ethernet/emulex/benet/be.h b/drivers/net/ethernet/emulex/benet/be.h -index 4bc18ef..c3ee910 100644 ---- a/drivers/net/ethernet/emulex/benet/be.h -+++ b/drivers/net/ethernet/emulex/benet/be.h +Index: linux-3.2.46/drivers/net/ethernet/emulex/benet/be.h +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/emulex/benet/be.h 2013-07-26 19:21:57.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/emulex/benet/be.h 2013-07-26 19:22:02.000000000 +0000 @@ -33,7 +33,7 @@ #include "be_hw.h" @@ -23,6 +23,3 @@ #define DRV_NAME "be2net" #define BE_NAME "ServerEngines BladeEngine2 10Gbps NIC" #define BE3_NAME "ServerEngines BladeEngine3 10Gbps NIC" --- -1.7.10 - diff -Nru linux-3.2.46/debian/patches/features/all/be2net/0054-be2net-Fix-to-not-set-link-speed-for-disabled-functi.patch linux-3.2.46/debian/patches/features/all/be2net/0054-be2net-Fix-to-not-set-link-speed-for-disabled-functi.patch --- linux-3.2.46/debian/patches/features/all/be2net/0054-be2net-Fix-to-not-set-link-speed-for-disabled-functi.patch 2013-02-24 03:52:39.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/be2net/0054-be2net-Fix-to-not-set-link-speed-for-disabled-functi.patch 2013-07-26 19:22:04.000000000 +0000 @@ -15,11 +15,11 @@ drivers/net/ethernet/emulex/benet/be_ethtool.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -diff --git a/drivers/net/ethernet/emulex/benet/be_ethtool.c b/drivers/net/ethernet/emulex/benet/be_ethtool.c -index b3b5fae..1763836 100644 ---- a/drivers/net/ethernet/emulex/benet/be_ethtool.c -+++ b/drivers/net/ethernet/emulex/benet/be_ethtool.c -@@ -558,7 +558,7 @@ static int be_get_settings(struct net_device *netdev, struct ethtool_cmd *ecmd) +Index: linux-3.2.46/drivers/net/ethernet/emulex/benet/be_ethtool.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/emulex/benet/be_ethtool.c 2013-07-26 19:22:01.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/emulex/benet/be_ethtool.c 2013-07-26 19:22:03.000000000 +0000 +@@ -558,7 +558,7 @@ be_link_status_update(adapter, link_status); if (link_speed) et_speed = link_speed * 10; @@ -28,6 +28,3 @@ et_speed = convert_to_et_speed(port_speed); } else { et_speed = adapter->phy.forced_port_speed; --- -1.7.10 - diff -Nru linux-3.2.46/debian/patches/features/all/be2net/0055-be2net-Fix-to-apply-duplex-value-as-unknown-when-lin.patch linux-3.2.46/debian/patches/features/all/be2net/0055-be2net-Fix-to-apply-duplex-value-as-unknown-when-lin.patch --- linux-3.2.46/debian/patches/features/all/be2net/0055-be2net-Fix-to-apply-duplex-value-as-unknown-when-lin.patch 2013-02-24 03:52:39.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/be2net/0055-be2net-Fix-to-apply-duplex-value-as-unknown-when-lin.patch 2013-07-26 19:22:06.000000000 +0000 @@ -13,11 +13,11 @@ drivers/net/ethernet/emulex/benet/be_ethtool.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -diff --git a/drivers/net/ethernet/emulex/benet/be_ethtool.c b/drivers/net/ethernet/emulex/benet/be_ethtool.c -index 1763836..730e96a 100644 ---- a/drivers/net/ethernet/emulex/benet/be_ethtool.c -+++ b/drivers/net/ethernet/emulex/benet/be_ethtool.c -@@ -618,7 +618,7 @@ static int be_get_settings(struct net_device *netdev, struct ethtool_cmd *ecmd) +Index: linux-3.2.46/drivers/net/ethernet/emulex/benet/be_ethtool.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/emulex/benet/be_ethtool.c 2013-07-26 19:22:03.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/emulex/benet/be_ethtool.c 2013-07-26 19:22:05.000000000 +0000 +@@ -618,7 +618,7 @@ ecmd->supported = adapter->phy.supported; } @@ -26,6 +26,3 @@ ecmd->phy_address = adapter->port_num; return 0; --- -1.7.10 - diff -Nru linux-3.2.46/debian/patches/features/all/be2net/0056-be2net-Record-receive-queue-index-in-skb-to-aid-RPS.patch linux-3.2.46/debian/patches/features/all/be2net/0056-be2net-Record-receive-queue-index-in-skb-to-aid-RPS.patch --- linux-3.2.46/debian/patches/features/all/be2net/0056-be2net-Record-receive-queue-index-in-skb-to-aid-RPS.patch 2013-02-24 03:52:39.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/be2net/0056-be2net-Record-receive-queue-index-in-skb-to-aid-RPS.patch 2013-07-26 19:22:07.000000000 +0000 @@ -11,11 +11,11 @@ drivers/net/ethernet/emulex/benet/be_main.c | 2 ++ 1 file changed, 2 insertions(+) -diff --git a/drivers/net/ethernet/emulex/benet/be_main.c b/drivers/net/ethernet/emulex/benet/be_main.c -index 9effea4..0dd4b88 100644 ---- a/drivers/net/ethernet/emulex/benet/be_main.c -+++ b/drivers/net/ethernet/emulex/benet/be_main.c -@@ -1251,6 +1251,7 @@ static void be_rx_compl_process(struct be_rx_obj *rxo, +Index: linux-3.2.46/drivers/net/ethernet/emulex/benet/be_main.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/emulex/benet/be_main.c 2013-07-26 19:22:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/emulex/benet/be_main.c 2013-07-26 19:22:06.000000000 +0000 +@@ -1252,6 +1252,7 @@ skb_checksum_none_assert(skb); skb->protocol = eth_type_trans(skb, netdev); @@ -23,7 +23,7 @@ if (netdev->features & NETIF_F_RXHASH) skb->rxhash = rxcp->rss_hash; -@@ -1307,6 +1308,7 @@ void be_rx_compl_process_gro(struct be_rx_obj *rxo, struct napi_struct *napi, +@@ -1308,6 +1309,7 @@ skb->len = rxcp->pkt_size; skb->data_len = rxcp->pkt_size; skb->ip_summed = CHECKSUM_UNNECESSARY; @@ -31,6 +31,3 @@ if (adapter->netdev->features & NETIF_F_RXHASH) skb->rxhash = rxcp->rss_hash; --- -1.7.10 - diff -Nru linux-3.2.46/debian/patches/features/all/be2net/0057-be2net-Fix-EEH-error-reset-before-a-flash-dump-compl.patch linux-3.2.46/debian/patches/features/all/be2net/0057-be2net-Fix-EEH-error-reset-before-a-flash-dump-compl.patch --- linux-3.2.46/debian/patches/features/all/be2net/0057-be2net-Fix-EEH-error-reset-before-a-flash-dump-compl.patch 2013-02-24 03:52:39.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/be2net/0057-be2net-Fix-EEH-error-reset-before-a-flash-dump-compl.patch 2013-07-26 19:22:08.000000000 +0000 @@ -16,11 +16,11 @@ drivers/net/ethernet/emulex/benet/be_main.c | 5 +++++ 1 file changed, 5 insertions(+) -diff --git a/drivers/net/ethernet/emulex/benet/be_main.c b/drivers/net/ethernet/emulex/benet/be_main.c -index 0dd4b88..3492dc8 100644 ---- a/drivers/net/ethernet/emulex/benet/be_main.c -+++ b/drivers/net/ethernet/emulex/benet/be_main.c -@@ -3813,6 +3813,11 @@ static pci_ers_result_t be_eeh_err_detected(struct pci_dev *pdev, +Index: linux-3.2.46/drivers/net/ethernet/emulex/benet/be_main.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/emulex/benet/be_main.c 2013-07-26 19:22:06.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/emulex/benet/be_main.c 2013-07-26 19:22:07.000000000 +0000 +@@ -3814,6 +3814,11 @@ pci_disable_device(pdev); @@ -32,6 +32,3 @@ return PCI_ERS_RESULT_NEED_RESET; } --- -1.7.10 - diff -Nru linux-3.2.46/debian/patches/features/all/be2net/0058-be2net-avoid-disabling-sriov-while-VFs-are-assigned.patch linux-3.2.46/debian/patches/features/all/be2net/0058-be2net-avoid-disabling-sriov-while-VFs-are-assigned.patch --- linux-3.2.46/debian/patches/features/all/be2net/0058-be2net-avoid-disabling-sriov-while-VFs-are-assigned.patch 2013-02-24 03:52:39.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/be2net/0058-be2net-avoid-disabling-sriov-while-VFs-are-assigned.patch 2013-07-26 19:22:09.000000000 +0000 @@ -19,11 +19,11 @@ drivers/net/ethernet/emulex/benet/be_main.c | 199 ++++++++++++++++----------- 3 files changed, 134 insertions(+), 89 deletions(-) -diff --git a/drivers/net/ethernet/emulex/benet/be.h b/drivers/net/ethernet/emulex/benet/be.h -index c3ee910..ecf1a81 100644 ---- a/drivers/net/ethernet/emulex/benet/be.h -+++ b/drivers/net/ethernet/emulex/benet/be.h -@@ -313,6 +313,11 @@ struct be_vf_cfg { +Index: linux-3.2.46/drivers/net/ethernet/emulex/benet/be.h +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/emulex/benet/be.h 2013-07-26 19:22:02.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/emulex/benet/be.h 2013-07-26 19:22:08.000000000 +0000 +@@ -313,6 +313,11 @@ u32 tx_rate; }; @@ -35,7 +35,7 @@ #define BE_FLAGS_LINK_STATUS_INIT 1 #define BE_FLAGS_WORKER_SCHEDULED (1 << 3) #define BE_UC_PMAC_COUNT 30 -@@ -403,8 +408,9 @@ struct be_adapter { +@@ -403,8 +408,9 @@ u32 flash_status; struct completion flash_compl; @@ -47,7 +47,7 @@ struct be_vf_cfg *vf_cfg; bool be3_native; u32 sli_family; -@@ -417,8 +423,10 @@ struct be_adapter { +@@ -417,8 +423,10 @@ u32 uc_macs; /* Count of secondary UC MAC programmed */ }; @@ -59,7 +59,7 @@ #define for_all_vfs(adapter, vf_cfg, i) \ for (i = 0, vf_cfg = &adapter->vf_cfg[i]; i < adapter->num_vfs; \ i++, vf_cfg++) -@@ -547,14 +555,6 @@ static inline u8 is_udp_pkt(struct sk_buff *skb) +@@ -547,14 +555,6 @@ return val; } @@ -74,10 +74,10 @@ static inline void be_vf_eth_addr_generate(struct be_adapter *adapter, u8 *mac) { u32 addr; -diff --git a/drivers/net/ethernet/emulex/benet/be_hw.h b/drivers/net/ethernet/emulex/benet/be_hw.h -index 0949aa6..f38b58c 100644 ---- a/drivers/net/ethernet/emulex/benet/be_hw.h -+++ b/drivers/net/ethernet/emulex/benet/be_hw.h +Index: linux-3.2.46/drivers/net/ethernet/emulex/benet/be_hw.h +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/emulex/benet/be_hw.h 2013-07-26 19:21:58.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/emulex/benet/be_hw.h 2013-07-26 19:22:08.000000000 +0000 @@ -58,6 +58,8 @@ #define SLI_PORT_CONTROL_IP_MASK 0x08000000 @@ -87,11 +87,11 @@ /********* Memory BAR register ************/ #define PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET 0xfc /* Host Interrupt Enable, if set interrupts are enabled although "PCI Interrupt -diff --git a/drivers/net/ethernet/emulex/benet/be_main.c b/drivers/net/ethernet/emulex/benet/be_main.c -index 3492dc8..910bae8 100644 ---- a/drivers/net/ethernet/emulex/benet/be_main.c -+++ b/drivers/net/ethernet/emulex/benet/be_main.c -@@ -1041,6 +1041,29 @@ static int be_set_vf_tx_rate(struct net_device *netdev, +Index: linux-3.2.46/drivers/net/ethernet/emulex/benet/be_main.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/emulex/benet/be_main.c 2013-07-26 19:22:07.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/emulex/benet/be_main.c 2013-07-26 19:22:08.000000000 +0000 +@@ -1042,6 +1042,29 @@ return status; } @@ -121,7 +121,7 @@ static void be_eqd_update(struct be_adapter *adapter, struct be_eq_obj *eqo) { struct be_rx_stats *stats = rx_stats(&adapter->rx_obj[eqo->idx]); -@@ -1781,9 +1804,9 @@ static void be_tx_queues_destroy(struct be_adapter *adapter) +@@ -1782,9 +1805,9 @@ static int be_num_txqs_want(struct be_adapter *adapter) { @@ -134,7 +134,7 @@ return 1; else return MAX_TX_QS; -@@ -2110,7 +2133,7 @@ static void be_msix_disable(struct be_adapter *adapter) +@@ -2111,7 +2134,7 @@ static uint be_num_rss_want(struct be_adapter *adapter) { if ((adapter->function_caps & BE_FUNCTION_CAPS_RSS) && @@ -143,7 +143,7 @@ !be_is_mc(adapter)) return (adapter->be3_native) ? BE3_MAX_RSS_QS : BE2_MAX_RSS_QS; else -@@ -2144,53 +2167,6 @@ done: +@@ -2145,53 +2168,6 @@ return; } @@ -197,7 +197,7 @@ static inline int be_msix_vec_get(struct be_adapter *adapter, struct be_eq_obj *eqo) { -@@ -2492,6 +2468,11 @@ static void be_vf_clear(struct be_adapter *adapter) +@@ -2493,6 +2469,11 @@ struct be_vf_cfg *vf_cfg; u32 vf; @@ -209,7 +209,7 @@ for_all_vfs(adapter, vf_cfg, vf) { if (lancer_chip(adapter)) be_cmd_set_mac_list(adapter, NULL, 0, vf + 1); -@@ -2501,6 +2482,10 @@ static void be_vf_clear(struct be_adapter *adapter) +@@ -2502,6 +2483,10 @@ be_cmd_if_destroy(adapter, vf_cfg->if_handle, vf + 1); } @@ -220,7 +220,7 @@ } static int be_clear(struct be_adapter *adapter) -@@ -2530,29 +2515,60 @@ static int be_clear(struct be_adapter *adapter) +@@ -2531,29 +2516,60 @@ be_cmd_fw_clean(adapter); be_msix_disable(adapter); @@ -255,15 +255,15 @@ u16 def_vlan, lnk_speed; - int status; + int status, enabled_vfs; -+ + +- be_vf_setup_init(adapter); + enabled_vfs = be_find_vfs(adapter, ENABLED); + if (enabled_vfs) { + dev_warn(dev, "%d VFs are already enabled\n", enabled_vfs); + dev_warn(dev, "Ignoring num_vfs=%d setting\n", num_vfs); + return 0; + } - -- be_vf_setup_init(adapter); ++ + if (num_vfs > adapter->dev_num_vfs) { + dev_warn(dev, "Device supports %d VFs and not %d\n", + adapter->dev_num_vfs, num_vfs); @@ -285,7 +285,7 @@ cap_flags = en_flags = BE_IF_FLAGS_UNTAGGED | BE_IF_FLAGS_BROADCAST | BE_IF_FLAGS_MULTICAST; -@@ -2563,9 +2579,11 @@ static int be_vf_setup(struct be_adapter *adapter) +@@ -2564,9 +2580,11 @@ goto err; } @@ -300,7 +300,7 @@ for_all_vfs(adapter, vf_cfg, vf) { status = be_cmd_link_status_query(adapter, NULL, &lnk_speed, -@@ -2622,9 +2640,25 @@ do_none: +@@ -2623,9 +2641,25 @@ return status; } @@ -326,7 +326,7 @@ u32 cap_flags, en_flags; u32 tx_fc, rx_fc; int status; -@@ -2632,6 +2666,8 @@ static int be_setup(struct be_adapter *adapter) +@@ -2633,6 +2667,8 @@ be_setup_init(adapter); @@ -335,7 +335,7 @@ be_cmd_req_native_mode(adapter); be_msix_enable(adapter); -@@ -2710,10 +2746,11 @@ static int be_setup(struct be_adapter *adapter) +@@ -2711,10 +2747,11 @@ pcie_set_readrq(adapter->pdev, 4096); @@ -351,7 +351,7 @@ } be_cmd_get_phy_info(adapter); -@@ -2723,6 +2760,7 @@ static int be_setup(struct be_adapter *adapter) +@@ -2724,6 +2761,7 @@ schedule_delayed_work(&adapter->work, msecs_to_jiffies(1000)); adapter->flags |= BE_FLAGS_WORKER_SCHEDULED; @@ -359,7 +359,7 @@ return 0; err: be_clear(adapter); -@@ -3344,8 +3382,6 @@ static void __devexit be_remove(struct pci_dev *pdev) +@@ -3345,8 +3383,6 @@ be_ctrl_cleanup(adapter); @@ -368,7 +368,7 @@ pci_set_drvdata(pdev, NULL); pci_release_regions(pdev); pci_disable_device(pdev); -@@ -3359,7 +3395,7 @@ bool be_is_wol_supported(struct be_adapter *adapter) +@@ -3360,7 +3396,7 @@ !be_is_wol_excluded(adapter)) ? true : false; } @@ -377,7 +377,7 @@ { int status; -@@ -3402,7 +3438,7 @@ static int be_get_config(struct be_adapter *adapter) +@@ -3403,7 +3439,7 @@ return 0; } @@ -386,7 +386,7 @@ { struct pci_dev *pdev = adapter->pdev; u32 sli_intf = 0, if_type; -@@ -3435,6 +3471,9 @@ static int be_dev_family_check(struct be_adapter *adapter) +@@ -3436,6 +3472,9 @@ default: adapter->generation = 0; } @@ -396,7 +396,7 @@ return 0; } -@@ -3578,6 +3617,14 @@ reschedule: +@@ -3579,6 +3618,14 @@ schedule_delayed_work(&adapter->work, msecs_to_jiffies(1000)); } @@ -411,7 +411,7 @@ static int __devinit be_probe(struct pci_dev *pdev, const struct pci_device_id *pdev_id) { -@@ -3603,7 +3650,7 @@ static int __devinit be_probe(struct pci_dev *pdev, +@@ -3604,7 +3651,7 @@ adapter->pdev = pdev; pci_set_drvdata(pdev, adapter); @@ -420,7 +420,7 @@ if (status) goto free_netdev; -@@ -3621,13 +3668,9 @@ static int __devinit be_probe(struct pci_dev *pdev, +@@ -3622,13 +3669,9 @@ } } @@ -435,7 +435,7 @@ if (lancer_chip(adapter)) { status = lancer_wait_ready(adapter); -@@ -3654,9 +3697,11 @@ static int __devinit be_probe(struct pci_dev *pdev, +@@ -3655,9 +3698,11 @@ if (status) goto ctrl_clean; @@ -450,7 +450,7 @@ /* The INTR bit may be set in the card when probed by a kdump kernel * after a crash. -@@ -3668,7 +3713,7 @@ static int __devinit be_probe(struct pci_dev *pdev, +@@ -3669,7 +3714,7 @@ if (status) goto ctrl_clean; @@ -459,7 +459,7 @@ if (status) goto stats_clean; -@@ -3697,8 +3742,6 @@ stats_clean: +@@ -3698,8 +3743,6 @@ be_stats_cleanup(adapter); ctrl_clean: be_ctrl_cleanup(adapter); @@ -468,6 +468,3 @@ free_netdev: free_netdev(netdev); pci_set_drvdata(pdev, NULL); --- -1.7.10 - diff -Nru linux-3.2.46/debian/patches/features/all/be2net/0059-be2net-do-not-modify-PCI-MaxReadReq-size.patch linux-3.2.46/debian/patches/features/all/be2net/0059-be2net-do-not-modify-PCI-MaxReadReq-size.patch --- linux-3.2.46/debian/patches/features/all/be2net/0059-be2net-do-not-modify-PCI-MaxReadReq-size.patch 2013-02-24 03:52:39.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/be2net/0059-be2net-do-not-modify-PCI-MaxReadReq-size.patch 2013-07-26 19:22:11.000000000 +0000 @@ -23,11 +23,11 @@ drivers/net/ethernet/emulex/benet/be_main.c | 2 -- 1 file changed, 2 deletions(-) -diff --git a/drivers/net/ethernet/emulex/benet/be_main.c b/drivers/net/ethernet/emulex/benet/be_main.c -index 8b6ce5b..2cf02d6 100644 ---- a/drivers/net/ethernet/emulex/benet/be_main.c -+++ b/drivers/net/ethernet/emulex/benet/be_main.c -@@ -2745,8 +2745,6 @@ static int be_setup(struct be_adapter *adapter) +Index: linux-3.2.46/drivers/net/ethernet/emulex/benet/be_main.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/emulex/benet/be_main.c 2013-07-26 19:22:08.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/emulex/benet/be_main.c 2013-07-26 19:22:10.000000000 +0000 +@@ -2745,8 +2745,6 @@ be_cmd_set_flow_control(adapter, adapter->tx_fc, adapter->rx_fc); @@ -36,6 +36,3 @@ if (be_physfn(adapter) && num_vfs) { if (adapter->dev_num_vfs) be_vf_setup(adapter); --- -1.7.10.4 - diff -Nru linux-3.2.46/debian/patches/features/all/be2net/0060-be2net-fix-reporting-number-of-actual-rx-queues.patch linux-3.2.46/debian/patches/features/all/be2net/0060-be2net-fix-reporting-number-of-actual-rx-queues.patch --- linux-3.2.46/debian/patches/features/all/be2net/0060-be2net-fix-reporting-number-of-actual-rx-queues.patch 2013-02-24 03:52:39.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/be2net/0060-be2net-fix-reporting-number-of-actual-rx-queues.patch 2013-07-26 19:22:12.000000000 +0000 @@ -11,11 +11,11 @@ drivers/net/ethernet/emulex/benet/be_main.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) -diff --git a/drivers/net/ethernet/emulex/benet/be_main.c b/drivers/net/ethernet/emulex/benet/be_main.c -index 2cf02d6..4e1305f 100644 ---- a/drivers/net/ethernet/emulex/benet/be_main.c -+++ b/drivers/net/ethernet/emulex/benet/be_main.c -@@ -1890,6 +1890,12 @@ static int be_rx_cqs_create(struct be_adapter *adapter) +Index: linux-3.2.46/drivers/net/ethernet/emulex/benet/be_main.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/emulex/benet/be_main.c 2013-07-26 19:22:10.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/emulex/benet/be_main.c 2013-07-26 19:22:11.000000000 +0000 +@@ -1890,6 +1890,12 @@ */ adapter->num_rx_qs = (num_irqs(adapter) > 1) ? num_irqs(adapter) + 1 : 1; @@ -28,7 +28,7 @@ adapter->big_page_size = (1 << get_order(rx_frag_size)) * PAGE_SIZE; for_all_rx_queues(adapter, rxo, i) { -@@ -3640,7 +3646,7 @@ static int __devinit be_probe(struct pci_dev *pdev, +@@ -3640,7 +3646,7 @@ goto disable_dev; pci_set_master(pdev); @@ -37,6 +37,3 @@ if (netdev == NULL) { status = -ENOMEM; goto rel_reg; --- -1.7.10.4 - diff -Nru linux-3.2.46/debian/patches/features/all/be2net/0061-be2net-do-not-use-SCRATCHPAD-register.patch linux-3.2.46/debian/patches/features/all/be2net/0061-be2net-do-not-use-SCRATCHPAD-register.patch --- linux-3.2.46/debian/patches/features/all/be2net/0061-be2net-do-not-use-SCRATCHPAD-register.patch 2013-02-24 03:52:39.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/be2net/0061-be2net-do-not-use-SCRATCHPAD-register.patch 2013-07-26 19:22:13.000000000 +0000 @@ -18,10 +18,10 @@ drivers/net/ethernet/emulex/benet/be_main.c | 10 +++------- 2 files changed, 3 insertions(+), 9 deletions(-) -diff --git a/drivers/net/ethernet/emulex/benet/be_hw.h b/drivers/net/ethernet/emulex/benet/be_hw.h -index f38b58c..0949aa6 100644 ---- a/drivers/net/ethernet/emulex/benet/be_hw.h -+++ b/drivers/net/ethernet/emulex/benet/be_hw.h +Index: linux-3.2.46/drivers/net/ethernet/emulex/benet/be_hw.h +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/emulex/benet/be_hw.h 2013-07-26 19:22:08.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/emulex/benet/be_hw.h 2013-07-26 19:22:12.000000000 +0000 @@ -58,8 +58,6 @@ #define SLI_PORT_CONTROL_IP_MASK 0x08000000 @@ -31,11 +31,11 @@ /********* Memory BAR register ************/ #define PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET 0xfc /* Host Interrupt Enable, if set interrupts are enabled although "PCI Interrupt -diff --git a/drivers/net/ethernet/emulex/benet/be_main.c b/drivers/net/ethernet/emulex/benet/be_main.c -index 4e1305f..24bd2cb 100644 ---- a/drivers/net/ethernet/emulex/benet/be_main.c -+++ b/drivers/net/ethernet/emulex/benet/be_main.c -@@ -1049,6 +1049,8 @@ static int be_find_vfs(struct be_adapter *adapter, int vf_state) +Index: linux-3.2.46/drivers/net/ethernet/emulex/benet/be_main.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/emulex/benet/be_main.c 2013-07-26 19:22:11.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/emulex/benet/be_main.c 2013-07-26 19:22:12.000000000 +0000 +@@ -1049,6 +1049,8 @@ u16 offset, stride; pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_SRIOV); @@ -44,7 +44,7 @@ pci_read_config_word(pdev, pos + PCI_SRIOV_VF_OFFSET, &offset); pci_read_config_word(pdev, pos + PCI_SRIOV_VF_STRIDE, &stride); -@@ -2522,7 +2524,6 @@ static int be_clear(struct be_adapter *adapter) +@@ -2522,7 +2524,6 @@ be_cmd_fw_clean(adapter); be_msix_disable(adapter); @@ -52,7 +52,7 @@ return 0; } -@@ -2764,8 +2765,6 @@ static int be_setup(struct be_adapter *adapter) +@@ -2764,8 +2765,6 @@ schedule_delayed_work(&adapter->work, msecs_to_jiffies(1000)); adapter->flags |= BE_FLAGS_WORKER_SCHEDULED; @@ -61,7 +61,7 @@ return 0; err: be_clear(adapter); -@@ -3624,10 +3623,7 @@ reschedule: +@@ -3624,10 +3623,7 @@ static bool be_reset_required(struct be_adapter *adapter) { @@ -73,6 +73,3 @@ } static int __devinit be_probe(struct pci_dev *pdev, --- -1.7.10.4 - diff -Nru linux-3.2.46/debian/patches/features/all/be2net/0062-be2net-reduce-gso_max_size-setting-to-account-for-et.patch linux-3.2.46/debian/patches/features/all/be2net/0062-be2net-reduce-gso_max_size-setting-to-account-for-et.patch --- linux-3.2.46/debian/patches/features/all/be2net/0062-be2net-reduce-gso_max_size-setting-to-account-for-et.patch 2013-02-24 03:52:39.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/be2net/0062-be2net-reduce-gso_max_size-setting-to-account-for-et.patch 2013-07-26 19:22:15.000000000 +0000 @@ -15,11 +15,11 @@ drivers/net/ethernet/emulex/benet/be_main.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -diff --git a/drivers/net/ethernet/emulex/benet/be_main.c b/drivers/net/ethernet/emulex/benet/be_main.c -index 24bd2cb..9c42942 100644 ---- a/drivers/net/ethernet/emulex/benet/be_main.c -+++ b/drivers/net/ethernet/emulex/benet/be_main.c -@@ -3212,7 +3212,7 @@ static void be_netdev_init(struct net_device *netdev) +Index: linux-3.2.46/drivers/net/ethernet/emulex/benet/be_main.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/emulex/benet/be_main.c 2013-07-26 19:22:12.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/emulex/benet/be_main.c 2013-07-26 19:22:14.000000000 +0000 +@@ -3212,7 +3212,7 @@ netdev->flags |= IFF_MULTICAST; @@ -28,6 +28,3 @@ netdev->netdev_ops = &be_netdev_ops; --- -1.7.10.4 - diff -Nru linux-3.2.46/debian/patches/features/all/be2net/0063-be2net-Increase-statistics-structure-size-for-skyhaw.patch linux-3.2.46/debian/patches/features/all/be2net/0063-be2net-Increase-statistics-structure-size-for-skyhaw.patch --- linux-3.2.46/debian/patches/features/all/be2net/0063-be2net-Increase-statistics-structure-size-for-skyhaw.patch 2013-02-24 03:52:39.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/be2net/0063-be2net-Increase-statistics-structure-size-for-skyhaw.patch 2013-07-26 19:22:16.000000000 +0000 @@ -14,11 +14,11 @@ drivers/net/ethernet/emulex/benet/be_cmds.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -diff --git a/drivers/net/ethernet/emulex/benet/be_cmds.h b/drivers/net/ethernet/emulex/benet/be_cmds.h -index 944f031..c3d881f 100644 ---- a/drivers/net/ethernet/emulex/benet/be_cmds.h -+++ b/drivers/net/ethernet/emulex/benet/be_cmds.h -@@ -1563,7 +1563,7 @@ struct be_hw_stats_v1 { +Index: linux-3.2.46/drivers/net/ethernet/emulex/benet/be_cmds.h +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/emulex/benet/be_cmds.h 2013-07-26 19:21:57.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/emulex/benet/be_cmds.h 2013-07-26 19:22:15.000000000 +0000 +@@ -1563,7 +1563,7 @@ u32 rsvd0[BE_TXP_SW_SZ]; struct be_erx_stats_v1 erx; struct be_pmem_stats pmem; @@ -27,6 +27,3 @@ }; struct be_cmd_req_get_stats_v1 { --- -1.7.10.4 - diff -Nru linux-3.2.46/debian/patches/features/all/be2net/0064-be2net-Explicitly-clear-the-reserved-field-in-the-Tx.patch linux-3.2.46/debian/patches/features/all/be2net/0064-be2net-Explicitly-clear-the-reserved-field-in-the-Tx.patch --- linux-3.2.46/debian/patches/features/all/be2net/0064-be2net-Explicitly-clear-the-reserved-field-in-the-Tx.patch 2013-02-24 03:52:39.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/be2net/0064-be2net-Explicitly-clear-the-reserved-field-in-the-Tx.patch 2013-07-26 19:22:17.000000000 +0000 @@ -12,11 +12,11 @@ drivers/net/ethernet/emulex/benet/be_main.c | 1 + 1 file changed, 1 insertion(+) -diff --git a/drivers/net/ethernet/emulex/benet/be_main.c b/drivers/net/ethernet/emulex/benet/be_main.c -index 9c42942..3041436 100644 ---- a/drivers/net/ethernet/emulex/benet/be_main.c -+++ b/drivers/net/ethernet/emulex/benet/be_main.c -@@ -558,6 +558,7 @@ static inline void wrb_fill(struct be_eth_wrb *wrb, u64 addr, int len) +Index: linux-3.2.46/drivers/net/ethernet/emulex/benet/be_main.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/emulex/benet/be_main.c 2013-07-26 19:22:14.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/emulex/benet/be_main.c 2013-07-26 19:22:16.000000000 +0000 +@@ -558,6 +558,7 @@ wrb->frag_pa_hi = upper_32_bits(addr); wrb->frag_pa_lo = addr & 0xFFFFFFFF; wrb->frag_len = len & ETH_WRB_FRAG_LEN_MASK; @@ -24,6 +24,3 @@ } static inline u16 be_get_tx_vlan_tag(struct be_adapter *adapter, --- -1.7.10.4 - diff -Nru linux-3.2.46/debian/patches/features/all/be2net/0065-be2net-Regression-bug-wherein-VFs-creation-broken-fo.patch linux-3.2.46/debian/patches/features/all/be2net/0065-be2net-Regression-bug-wherein-VFs-creation-broken-fo.patch --- linux-3.2.46/debian/patches/features/all/be2net/0065-be2net-Regression-bug-wherein-VFs-creation-broken-fo.patch 2013-02-24 03:52:39.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/be2net/0065-be2net-Regression-bug-wherein-VFs-creation-broken-fo.patch 2013-07-26 19:22:19.000000000 +0000 @@ -14,11 +14,11 @@ drivers/net/ethernet/emulex/benet/be_main.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) -diff --git a/drivers/net/ethernet/emulex/benet/be_main.c b/drivers/net/ethernet/emulex/benet/be_main.c -index 3041436..dc10904 100644 ---- a/drivers/net/ethernet/emulex/benet/be_main.c -+++ b/drivers/net/ethernet/emulex/benet/be_main.c -@@ -1058,7 +1058,8 @@ static int be_find_vfs(struct be_adapter *adapter, int vf_state) +Index: linux-3.2.46/drivers/net/ethernet/emulex/benet/be_main.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/emulex/benet/be_main.c 2013-07-26 19:22:16.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/emulex/benet/be_main.c 2013-07-26 19:22:18.000000000 +0000 +@@ -1058,7 +1058,8 @@ dev = pci_get_device(pdev->vendor, PCI_ANY_ID, NULL); while (dev) { vf_fn = (pdev->devfn + offset + stride * vfs) & 0xFFFF; @@ -28,6 +28,3 @@ vfs++; if (dev->dev_flags & PCI_DEV_FLAGS_ASSIGNED) assigned_vfs++; --- -1.7.10.4 - diff -Nru linux-3.2.46/debian/patches/features/all/be2net/0066-be2net-Fix-to-trim-skb-for-padded-vlan-packets-to-wo.patch linux-3.2.46/debian/patches/features/all/be2net/0066-be2net-Fix-to-trim-skb-for-padded-vlan-packets-to-wo.patch --- linux-3.2.46/debian/patches/features/all/be2net/0066-be2net-Fix-to-trim-skb-for-padded-vlan-packets-to-wo.patch 2013-02-24 03:52:39.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/be2net/0066-be2net-Fix-to-trim-skb-for-padded-vlan-packets-to-wo.patch 2013-07-26 19:22:20.000000000 +0000 @@ -17,11 +17,11 @@ drivers/net/ethernet/emulex/benet/be_main.c | 57 ++++++++++++++++++++------- 2 files changed, 48 insertions(+), 14 deletions(-) -diff --git a/drivers/net/ethernet/emulex/benet/be.h b/drivers/net/ethernet/emulex/benet/be.h -index ecf1a81..d1a17dc 100644 ---- a/drivers/net/ethernet/emulex/benet/be.h -+++ b/drivers/net/ethernet/emulex/benet/be.h -@@ -555,6 +555,11 @@ static inline u8 is_udp_pkt(struct sk_buff *skb) +Index: linux-3.2.46/drivers/net/ethernet/emulex/benet/be.h +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/emulex/benet/be.h 2013-07-26 19:22:08.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/emulex/benet/be.h 2013-07-26 19:22:19.000000000 +0000 +@@ -555,6 +555,11 @@ return val; } @@ -33,11 +33,11 @@ static inline void be_vf_eth_addr_generate(struct be_adapter *adapter, u8 *mac) { u32 addr; -diff --git a/drivers/net/ethernet/emulex/benet/be_main.c b/drivers/net/ethernet/emulex/benet/be_main.c -index dc10904..ec72318 100644 ---- a/drivers/net/ethernet/emulex/benet/be_main.c -+++ b/drivers/net/ethernet/emulex/benet/be_main.c -@@ -577,6 +577,11 @@ static inline u16 be_get_tx_vlan_tag(struct be_adapter *adapter, +Index: linux-3.2.46/drivers/net/ethernet/emulex/benet/be_main.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/emulex/benet/be_main.c 2013-07-26 19:22:18.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/emulex/benet/be_main.c 2013-07-26 19:22:19.000000000 +0000 +@@ -577,6 +577,11 @@ return vlan_tag; } @@ -49,7 +49,7 @@ static void wrb_fill_hdr(struct be_adapter *adapter, struct be_eth_hdr_wrb *hdr, struct sk_buff *skb, u32 wrb_cnt, u32 len) { -@@ -704,33 +709,57 @@ dma_err: +@@ -704,33 +709,57 @@ return 0; } @@ -121,6 +121,3 @@ } wrb_cnt = wrb_cnt_for_skb(adapter, skb, &dummy_wrb); --- -1.7.10.4 - diff -Nru linux-3.2.46/debian/patches/features/all/be2net/0067-be2net-Fix-Endian.patch linux-3.2.46/debian/patches/features/all/be2net/0067-be2net-Fix-Endian.patch --- linux-3.2.46/debian/patches/features/all/be2net/0067-be2net-Fix-Endian.patch 2013-02-24 03:52:39.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/be2net/0067-be2net-Fix-Endian.patch 2013-07-26 19:22:21.000000000 +0000 @@ -17,11 +17,11 @@ drivers/net/ethernet/emulex/benet/be.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -diff --git a/drivers/net/ethernet/emulex/benet/be.h b/drivers/net/ethernet/emulex/benet/be.h -index d1a17dc..75d9b60 100644 ---- a/drivers/net/ethernet/emulex/benet/be.h -+++ b/drivers/net/ethernet/emulex/benet/be.h -@@ -557,7 +557,7 @@ static inline u8 is_udp_pkt(struct sk_buff *skb) +Index: linux-3.2.46/drivers/net/ethernet/emulex/benet/be.h +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/emulex/benet/be.h 2013-07-26 19:22:19.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/emulex/benet/be.h 2013-07-26 19:22:20.000000000 +0000 +@@ -557,7 +557,7 @@ static inline bool is_ipv4_pkt(struct sk_buff *skb) { @@ -30,6 +30,3 @@ } static inline void be_vf_eth_addr_generate(struct be_adapter *adapter, u8 *mac) --- -1.7.10.4 - diff -Nru linux-3.2.46/debian/patches/features/all/be2net/0068-be2net-Enable-RSS-UDP-hashing-for-Lancer-and-Skyhawk.patch linux-3.2.46/debian/patches/features/all/be2net/0068-be2net-Enable-RSS-UDP-hashing-for-Lancer-and-Skyhawk.patch --- linux-3.2.46/debian/patches/features/all/be2net/0068-be2net-Enable-RSS-UDP-hashing-for-Lancer-and-Skyhawk.patch 2013-02-24 03:52:39.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/be2net/0068-be2net-Enable-RSS-UDP-hashing-for-Lancer-and-Skyhawk.patch 2013-07-26 19:22:23.000000000 +0000 @@ -13,11 +13,11 @@ drivers/net/ethernet/emulex/benet/be_cmds.h | 2 ++ 3 files changed, 13 insertions(+) -diff --git a/drivers/net/ethernet/emulex/benet/be.h b/drivers/net/ethernet/emulex/benet/be.h -index 75d9b60..c648a40 100644 ---- a/drivers/net/ethernet/emulex/benet/be.h -+++ b/drivers/net/ethernet/emulex/benet/be.h -@@ -440,6 +440,10 @@ struct be_adapter { +Index: linux-3.2.46/drivers/net/ethernet/emulex/benet/be.h +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/emulex/benet/be.h 2013-07-26 19:22:20.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/emulex/benet/be.h 2013-07-26 19:22:22.000000000 +0000 +@@ -440,6 +440,10 @@ #define lancer_chip(adapter) ((adapter->pdev->device == OC_DEVICE_ID3) || \ (adapter->pdev->device == OC_DEVICE_ID4)) @@ -28,11 +28,11 @@ extern const struct ethtool_ops be_ethtool_ops; #define msix_enabled(adapter) (adapter->num_msix_vec > 0) -diff --git a/drivers/net/ethernet/emulex/benet/be_cmds.c b/drivers/net/ethernet/emulex/benet/be_cmds.c -index 43167e8..0757df4 100644 ---- a/drivers/net/ethernet/emulex/benet/be_cmds.c -+++ b/drivers/net/ethernet/emulex/benet/be_cmds.c -@@ -1727,6 +1727,13 @@ int be_cmd_rss_config(struct be_adapter *adapter, u8 *rsstable, u16 table_size) +Index: linux-3.2.46/drivers/net/ethernet/emulex/benet/be_cmds.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/emulex/benet/be_cmds.c 2013-07-26 19:21:58.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/emulex/benet/be_cmds.c 2013-07-26 19:22:22.000000000 +0000 +@@ -1727,6 +1727,13 @@ req->if_id = cpu_to_le32(adapter->if_handle); req->enable_rss = cpu_to_le16(RSS_ENABLE_TCP_IPV4 | RSS_ENABLE_IPV4 | RSS_ENABLE_TCP_IPV6 | RSS_ENABLE_IPV6); @@ -46,11 +46,11 @@ req->cpu_table_size_log2 = cpu_to_le16(fls(table_size) - 1); memcpy(req->cpu_table, rsstable, table_size); memcpy(req->hash, myhash, sizeof(myhash)); -diff --git a/drivers/net/ethernet/emulex/benet/be_cmds.h b/drivers/net/ethernet/emulex/benet/be_cmds.h -index c3d881f..d42b3b9 100644 ---- a/drivers/net/ethernet/emulex/benet/be_cmds.h -+++ b/drivers/net/ethernet/emulex/benet/be_cmds.h -@@ -1085,6 +1085,8 @@ struct be_cmd_resp_query_fw_cfg { +Index: linux-3.2.46/drivers/net/ethernet/emulex/benet/be_cmds.h +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/emulex/benet/be_cmds.h 2013-07-26 19:22:15.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/emulex/benet/be_cmds.h 2013-07-26 19:22:22.000000000 +0000 +@@ -1085,6 +1085,8 @@ #define RSS_ENABLE_TCP_IPV4 0x2 #define RSS_ENABLE_IPV6 0x4 #define RSS_ENABLE_TCP_IPV6 0x8 @@ -59,6 +59,3 @@ struct be_cmd_req_rss_config { struct be_cmd_req_hdr hdr; --- -1.7.10.4 - diff -Nru linux-3.2.46/debian/patches/features/all/be2net/0069-be2net-dont-pull-too-much-data-in-skb-linear-part.patch linux-3.2.46/debian/patches/features/all/be2net/0069-be2net-dont-pull-too-much-data-in-skb-linear-part.patch --- linux-3.2.46/debian/patches/features/all/be2net/0069-be2net-dont-pull-too-much-data-in-skb-linear-part.patch 2013-02-24 03:52:39.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/be2net/0069-be2net-dont-pull-too-much-data-in-skb-linear-part.patch 2013-07-26 19:22:24.000000000 +0000 @@ -20,11 +20,11 @@ drivers/net/ethernet/emulex/benet/be_main.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) -diff --git a/drivers/net/ethernet/emulex/benet/be_main.c b/drivers/net/ethernet/emulex/benet/be_main.c -index ec72318..e2e2472 100644 ---- a/drivers/net/ethernet/emulex/benet/be_main.c -+++ b/drivers/net/ethernet/emulex/benet/be_main.c -@@ -1228,16 +1228,16 @@ static void skb_fill_rx_data(struct be_rx_obj *rxo, struct sk_buff *skb, +Index: linux-3.2.46/drivers/net/ethernet/emulex/benet/be_main.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/emulex/benet/be_main.c 2013-07-26 19:22:19.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/emulex/benet/be_main.c 2013-07-26 19:22:23.000000000 +0000 +@@ -1228,16 +1228,16 @@ /* Copy data in the first descriptor of this completion */ curr_frag_len = min(rxcp->pkt_size, rx_frag_size); @@ -44,6 +44,3 @@ skb_shinfo(skb)->nr_frags = 1; skb_frag_set_page(skb, 0, page_info->page); skb_shinfo(skb)->frags[0].page_offset = --- -1.7.10.4 - diff -Nru linux-3.2.46/debian/patches/features/all/be2net/0070-be2net-Fix-to-parse-RSS-hash-from-Receive-completion.patch linux-3.2.46/debian/patches/features/all/be2net/0070-be2net-Fix-to-parse-RSS-hash-from-Receive-completion.patch --- linux-3.2.46/debian/patches/features/all/be2net/0070-be2net-Fix-to-parse-RSS-hash-from-Receive-completion.patch 2013-02-24 03:52:39.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/be2net/0070-be2net-Fix-to-parse-RSS-hash-from-Receive-completion.patch 2013-07-26 19:22:25.000000000 +0000 @@ -15,11 +15,11 @@ drivers/net/ethernet/emulex/benet/be_main.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -diff --git a/drivers/net/ethernet/emulex/benet/be_main.c b/drivers/net/ethernet/emulex/benet/be_main.c -index e2e2472..19307ad 100644 ---- a/drivers/net/ethernet/emulex/benet/be_main.c -+++ b/drivers/net/ethernet/emulex/benet/be_main.c -@@ -1397,7 +1397,7 @@ static void be_parse_rx_compl_v1(struct be_eth_rx_compl *compl, +Index: linux-3.2.46/drivers/net/ethernet/emulex/benet/be_main.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/emulex/benet/be_main.c 2013-07-26 19:22:23.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/emulex/benet/be_main.c 2013-07-26 19:22:24.000000000 +0000 +@@ -1397,7 +1397,7 @@ rxcp->pkt_type = AMAP_GET_BITS(struct amap_eth_rx_compl_v1, cast_enc, compl); rxcp->rss_hash = @@ -28,7 +28,7 @@ if (rxcp->vlanf) { rxcp->vtm = AMAP_GET_BITS(struct amap_eth_rx_compl_v1, vtm, compl); -@@ -1429,7 +1429,7 @@ static void be_parse_rx_compl_v0(struct be_eth_rx_compl *compl, +@@ -1429,7 +1429,7 @@ rxcp->pkt_type = AMAP_GET_BITS(struct amap_eth_rx_compl_v0, cast_enc, compl); rxcp->rss_hash = @@ -37,6 +37,3 @@ if (rxcp->vlanf) { rxcp->vtm = AMAP_GET_BITS(struct amap_eth_rx_compl_v0, vtm, compl); --- -1.7.10.4 - diff -Nru linux-3.2.46/debian/patches/features/all/be2net/0071-netpoll-revert-6bdb7fe3104-and-fix-be_poll-instead.patch linux-3.2.46/debian/patches/features/all/be2net/0071-netpoll-revert-6bdb7fe3104-and-fix-be_poll-instead.patch --- linux-3.2.46/debian/patches/features/all/be2net/0071-netpoll-revert-6bdb7fe3104-and-fix-be_poll-instead.patch 2013-02-24 03:52:39.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/be2net/0071-netpoll-revert-6bdb7fe3104-and-fix-be_poll-instead.patch 2013-07-26 19:22:27.000000000 +0000 @@ -59,11 +59,11 @@ drivers/net/ethernet/emulex/benet/be_main.c | 2 ++ 2 files changed, 6 insertions(+), 2 deletions(-) -diff --git a/drivers/net/ethernet/emulex/benet/be_cmds.c b/drivers/net/ethernet/emulex/benet/be_cmds.c -index 0757df4..5d42468 100644 ---- a/drivers/net/ethernet/emulex/benet/be_cmds.c -+++ b/drivers/net/ethernet/emulex/benet/be_cmds.c -@@ -256,7 +256,7 @@ int be_process_mcc(struct be_adapter *adapter) +Index: linux-3.2.46/drivers/net/ethernet/emulex/benet/be_cmds.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/emulex/benet/be_cmds.c 2013-07-26 19:22:22.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/emulex/benet/be_cmds.c 2013-07-26 19:22:26.000000000 +0000 +@@ -256,7 +256,7 @@ int num = 0, status = 0; struct be_mcc_obj *mcc_obj = &adapter->mcc_obj; @@ -72,7 +72,7 @@ while ((compl = be_mcc_compl_get(adapter))) { if (compl->flags & CQE_FLAGS_ASYNC_MASK) { /* Interpret flags as an async trailer */ -@@ -277,7 +277,7 @@ int be_process_mcc(struct be_adapter *adapter) +@@ -277,7 +277,7 @@ if (num) be_cq_notify(adapter, mcc_obj->cq.id, mcc_obj->rearm_cq, num); @@ -81,7 +81,7 @@ return status; } -@@ -292,7 +292,9 @@ static int be_mcc_wait_compl(struct be_adapter *adapter) +@@ -292,7 +292,9 @@ if (be_error(adapter)) return -EIO; @@ -91,11 +91,11 @@ if (atomic_read(&mcc_obj->q.used) == 0) break; -diff --git a/drivers/net/ethernet/emulex/benet/be_main.c b/drivers/net/ethernet/emulex/benet/be_main.c -index 19307ad..3a21dda 100644 ---- a/drivers/net/ethernet/emulex/benet/be_main.c -+++ b/drivers/net/ethernet/emulex/benet/be_main.c -@@ -3625,7 +3625,9 @@ static void be_worker(struct work_struct *work) +Index: linux-3.2.46/drivers/net/ethernet/emulex/benet/be_main.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/emulex/benet/be_main.c 2013-07-26 19:22:24.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/emulex/benet/be_main.c 2013-07-26 19:22:26.000000000 +0000 +@@ -3625,7 +3625,9 @@ /* when interrupts are not yet enabled, just reap any pending * mcc completions */ if (!netif_running(adapter->netdev)) { @@ -105,6 +105,3 @@ goto reschedule; } --- -1.7.10.4 - diff -Nru linux-3.2.46/debian/patches/features/all/bql/bnx2-support-for-byte-queue-limits.patch linux-3.2.46/debian/patches/features/all/bql/bnx2-support-for-byte-queue-limits.patch --- linux-3.2.46/debian/patches/features/all/bql/bnx2-support-for-byte-queue-limits.patch 2013-02-24 03:52:36.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/bql/bnx2-support-for-byte-queue-limits.patch 2013-07-26 19:24:44.000000000 +0000 @@ -13,11 +13,11 @@ drivers/net/ethernet/broadcom/bnx2.c | 6 ++++++ 1 file changed, 6 insertions(+) -diff --git a/drivers/net/ethernet/broadcom/bnx2.c b/drivers/net/ethernet/broadcom/bnx2.c -index d573169..787e175 100644 ---- a/drivers/net/ethernet/broadcom/bnx2.c -+++ b/drivers/net/ethernet/broadcom/bnx2.c -@@ -2810,6 +2810,7 @@ bnx2_tx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget) +Index: linux-3.2.46/drivers/net/ethernet/broadcom/bnx2.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/broadcom/bnx2.c 2013-07-26 18:54:11.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/broadcom/bnx2.c 2013-07-26 19:24:43.000000000 +0000 +@@ -2823,6 +2823,7 @@ struct bnx2_tx_ring_info *txr = &bnapi->tx_ring; u16 hw_cons, sw_cons, sw_ring_cons; int tx_pkt = 0, index; @@ -25,7 +25,7 @@ struct netdev_queue *txq; index = (bnapi - bp->bnx2_napi); -@@ -2864,6 +2865,7 @@ bnx2_tx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget) +@@ -2877,6 +2878,7 @@ sw_cons = NEXT_TX_BD(sw_cons); @@ -33,7 +33,7 @@ dev_kfree_skb(skb); tx_pkt++; if (tx_pkt == budget) -@@ -2873,6 +2875,7 @@ bnx2_tx_int(struct bnx2 *bp, struct bnx2_napi *bnapi, int budget) +@@ -2886,6 +2888,7 @@ hw_cons = bnx2_get_hw_tx_cons(bnapi); } @@ -41,7 +41,7 @@ txr->hw_tx_cons = hw_cons; txr->tx_cons = sw_cons; -@@ -5393,6 +5396,7 @@ bnx2_free_tx_skbs(struct bnx2 *bp) +@@ -5400,6 +5403,7 @@ } dev_kfree_skb(skb); } @@ -49,7 +49,7 @@ } } -@@ -6546,6 +6550,8 @@ bnx2_start_xmit(struct sk_buff *skb, struct net_device *dev) +@@ -6552,6 +6556,8 @@ } txbd->tx_bd_vlan_tag_flags |= TX_BD_FLAGS_END; diff -Nru linux-3.2.46/debian/patches/features/all/bql/bnx2x-fix-crash-while-ethtool-t.patch linux-3.2.46/debian/patches/features/all/bql/bnx2x-fix-crash-while-ethtool-t.patch --- linux-3.2.46/debian/patches/features/all/bql/bnx2x-fix-crash-while-ethtool-t.patch 2013-02-24 03:52:36.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/bql/bnx2x-fix-crash-while-ethtool-t.patch 2013-07-26 19:24:39.000000000 +0000 @@ -19,8 +19,10 @@ drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c | 3 +++ 1 file changed, 3 insertions(+) ---- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c -+++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c +Index: linux-3.2.46/drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c 2013-07-26 18:54:13.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c 2013-07-26 19:24:38.000000000 +0000 @@ -1740,6 +1740,7 @@ struct sw_rx_bd *rx_buf; u16 len; diff -Nru linux-3.2.46/debian/patches/features/all/bql/bnx2x-remove-unused-variable.patch linux-3.2.46/debian/patches/features/all/bql/bnx2x-remove-unused-variable.patch --- linux-3.2.46/debian/patches/features/all/bql/bnx2x-remove-unused-variable.patch 2013-02-24 03:52:36.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/bql/bnx2x-remove-unused-variable.patch 2013-07-26 19:24:36.000000000 +0000 @@ -11,11 +11,11 @@ drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) -diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.c b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.c -index 1ace946..f946a6e 100644 ---- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.c -+++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.c -@@ -1094,13 +1094,11 @@ static void bnx2x_free_tx_skbs(struct bnx2x *bp) +Index: linux-3.2.46/drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.c 2013-07-26 18:54:14.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.c 2013-07-26 19:24:35.000000000 +0000 +@@ -1112,13 +1112,11 @@ for_each_cos_in_tx_queue(fp, cos) { struct bnx2x_fp_txdata *txdata = &fp->txdata[cos]; diff -Nru linux-3.2.46/debian/patches/features/all/bql/bnx2x-support-for-byte-queue-limits.patch linux-3.2.46/debian/patches/features/all/bql/bnx2x-support-for-byte-queue-limits.patch --- linux-3.2.46/debian/patches/features/all/bql/bnx2x-support-for-byte-queue-limits.patch 2013-02-24 03:52:36.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/bql/bnx2x-support-for-byte-queue-limits.patch 2013-07-26 19:24:38.000000000 +0000 @@ -13,11 +13,11 @@ drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.c | 26 +++++++++++++++++++---- 1 file changed, 22 insertions(+), 4 deletions(-) -diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.c b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.c -index 8336c78..42ce566 100644 ---- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.c -+++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.c -@@ -102,7 +102,8 @@ int load_count[2][3] = { {0} }; /* per-path: 0-common, 1-port0, 2-port1 */ +Index: linux-3.2.46/drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.c 2013-07-26 19:24:35.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.c 2013-07-26 19:24:37.000000000 +0000 +@@ -100,7 +100,8 @@ * return idx of last bd freed */ static u16 bnx2x_free_tx_pkt(struct bnx2x *bp, struct bnx2x_fp_txdata *txdata, @@ -27,7 +27,7 @@ { struct sw_tx_bd *tx_buf = &txdata->tx_buf_ring[idx]; struct eth_tx_start_bd *tx_start_bd; -@@ -159,6 +160,10 @@ static u16 bnx2x_free_tx_pkt(struct bnx2x *bp, struct bnx2x_fp_txdata *txdata, +@@ -157,6 +158,10 @@ /* release skb */ WARN_ON(!skb); @@ -38,7 +38,7 @@ dev_kfree_skb_any(skb); tx_buf->first_bd = 0; tx_buf->skb = NULL; -@@ -170,6 +175,7 @@ int bnx2x_tx_int(struct bnx2x *bp, struct bnx2x_fp_txdata *txdata) +@@ -168,6 +173,7 @@ { struct netdev_queue *txq; u16 hw_cons, sw_cons, bd_cons = txdata->tx_bd_cons; @@ -46,7 +46,7 @@ #ifdef BNX2X_STOP_ON_ERROR if (unlikely(bp->panic)) -@@ -189,10 +195,14 @@ int bnx2x_tx_int(struct bnx2x *bp, struct bnx2x_fp_txdata *txdata) +@@ -187,10 +193,14 @@ " pkt_cons %u\n", txdata->txq_index, hw_cons, sw_cons, pkt_cons); @@ -62,7 +62,7 @@ txdata->tx_pkt_cons = sw_cons; txdata->tx_bd_cons = bd_cons; -@@ -1077,14 +1087,18 @@ static void bnx2x_free_tx_skbs(struct bnx2x *bp) +@@ -1111,14 +1121,18 @@ struct bnx2x_fastpath *fp = &bp->fp[i]; for_each_cos_in_tx_queue(fp, cos) { struct bnx2x_fp_txdata *txdata = &fp->txdata[cos]; @@ -82,7 +82,7 @@ } } } -@@ -2788,6 +2802,7 @@ netdev_tx_t bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev) +@@ -2813,6 +2827,7 @@ mapping = skb_frag_dma_map(&bp->pdev->dev, frag, 0, skb_frag_size(frag), DMA_TO_DEVICE); if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) { @@ -90,7 +90,7 @@ DP(NETIF_MSG_TX_QUEUED, "Unable to map page - " "dropping packet...\n"); -@@ -2799,7 +2814,8 @@ netdev_tx_t bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev) +@@ -2824,7 +2839,8 @@ */ first_bd->nbd = cpu_to_le16(nbd); bnx2x_free_tx_pkt(bp, txdata, @@ -100,7 +100,7 @@ return NETDEV_TX_OK; } -@@ -2860,6 +2876,8 @@ netdev_tx_t bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev) +@@ -2885,6 +2901,8 @@ pbd_e2->parsing_data); DP(NETIF_MSG_TX_QUEUED, "doorbell: nbd %d bd %u\n", nbd, bd_prod); diff -Nru linux-3.2.46/debian/patches/features/all/bql/bql-avoid-possible-inconsistent-calculation.patch linux-3.2.46/debian/patches/features/all/bql/bql-avoid-possible-inconsistent-calculation.patch --- linux-3.2.46/debian/patches/features/all/bql/bql-avoid-possible-inconsistent-calculation.patch 2013-02-24 03:52:36.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/bql/bql-avoid-possible-inconsistent-calculation.patch 2013-07-26 19:24:27.000000000 +0000 @@ -17,10 +17,10 @@ lib/dynamic_queue_limits.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) -diff --git a/lib/dynamic_queue_limits.c b/lib/dynamic_queue_limits.c -index 0fafa77..0777c5a 100644 ---- a/lib/dynamic_queue_limits.c -+++ b/lib/dynamic_queue_limits.c +Index: linux-3.2.46/lib/dynamic_queue_limits.c +=================================================================== +--- linux-3.2.46.orig/lib/dynamic_queue_limits.c 2013-07-26 19:24:24.000000000 +0000 ++++ linux-3.2.46/lib/dynamic_queue_limits.c 2013-07-26 19:24:26.000000000 +0000 @@ -17,16 +17,18 @@ void dql_completed(struct dql *dql, unsigned int count) { @@ -44,7 +44,7 @@ prev_inprogress = dql->prev_num_queued - dql->num_completed; all_prev_completed = AFTER_EQ(completed, dql->prev_num_queued); -@@ -106,7 +108,7 @@ void dql_completed(struct dql *dql, unsigned int count) +@@ -106,7 +108,7 @@ dql->prev_ovlimit = ovlimit; dql->prev_last_obj_cnt = dql->last_obj_cnt; dql->num_completed = completed; diff -Nru linux-3.2.46/debian/patches/features/all/bql/bql-avoid-unneeded-limit-decrement.patch linux-3.2.46/debian/patches/features/all/bql/bql-avoid-unneeded-limit-decrement.patch --- linux-3.2.46/debian/patches/features/all/bql/bql-avoid-unneeded-limit-decrement.patch 2013-02-24 03:52:36.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/bql/bql-avoid-unneeded-limit-decrement.patch 2013-07-26 19:24:25.000000000 +0000 @@ -39,10 +39,10 @@ lib/dynamic_queue_limits.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) -diff --git a/lib/dynamic_queue_limits.c b/lib/dynamic_queue_limits.c -index c87eb76..0fafa77 100644 ---- a/lib/dynamic_queue_limits.c -+++ b/lib/dynamic_queue_limits.c +Index: linux-3.2.46/lib/dynamic_queue_limits.c +=================================================================== +--- linux-3.2.46.orig/lib/dynamic_queue_limits.c 2013-07-26 19:24:23.000000000 +0000 ++++ linux-3.2.46/lib/dynamic_queue_limits.c 2013-07-26 19:24:24.000000000 +0000 @@ -11,12 +11,14 @@ #include @@ -59,7 +59,7 @@ /* Can't complete more than what's in queue */ BUG_ON(count > dql->num_queued - dql->num_completed); -@@ -26,7 +28,7 @@ void dql_completed(struct dql *dql, unsigned int count) +@@ -26,7 +28,7 @@ ovlimit = POSDIFF(dql->num_queued - dql->num_completed, limit); inprogress = dql->num_queued - completed; prev_inprogress = dql->prev_num_queued - dql->num_completed; diff -Nru linux-3.2.46/debian/patches/features/all/bql/bql-byte-queue-limits.patch linux-3.2.46/debian/patches/features/all/bql/bql-byte-queue-limits.patch --- linux-3.2.46/debian/patches/features/all/bql/bql-byte-queue-limits.patch 2013-02-24 03:52:36.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/bql/bql-byte-queue-limits.patch 2013-07-26 19:24:19.000000000 +0000 @@ -30,8 +30,10 @@ net/core/net-sysfs.c | 140 ++++++++++++++++++++++++++++++++++++++++++--- 4 files changed, 172 insertions(+), 9 deletions(-) ---- a/include/linux/netdevice.h -+++ b/include/linux/netdevice.h +Index: linux-3.2.46/include/linux/netdevice.h +=================================================================== +--- linux-3.2.46.orig/include/linux/netdevice.h 2013-07-26 19:24:15.000000000 +0000 ++++ linux-3.2.46/include/linux/netdevice.h 2013-07-26 19:24:18.000000000 +0000 @@ -43,6 +43,7 @@ #include #include @@ -61,7 +63,7 @@ } ____cacheline_aligned_in_smp; static inline int netdev_queue_numa_node_read(const struct netdev_queue *q) -@@ -1926,6 +1932,15 @@ +@@ -1930,6 +1936,15 @@ static inline void netdev_tx_sent_queue(struct netdev_queue *dev_queue, unsigned int bytes) { @@ -77,7 +79,7 @@ } static inline void netdev_sent_queue(struct net_device *dev, unsigned int bytes) -@@ -1936,6 +1951,18 @@ +@@ -1940,6 +1955,18 @@ static inline void netdev_tx_completed_queue(struct netdev_queue *dev_queue, unsigned pkts, unsigned bytes) { @@ -96,7 +98,7 @@ } static inline void netdev_completed_queue(struct net_device *dev, -@@ -1946,6 +1973,9 @@ +@@ -1950,6 +1977,9 @@ static inline void netdev_tx_reset_queue(struct netdev_queue *q) { @@ -106,8 +108,10 @@ } static inline void netdev_reset_queue(struct net_device *dev_queue) ---- a/net/Kconfig -+++ b/net/Kconfig +Index: linux-3.2.46/net/Kconfig +=================================================================== +--- linux-3.2.46.orig/net/Kconfig 2013-07-26 19:24:04.000000000 +0000 ++++ linux-3.2.46/net/Kconfig 2013-07-26 19:24:18.000000000 +0000 @@ -232,6 +232,12 @@ depends on SMP && SYSFS && USE_GENERIC_SMP_HELPERS default y @@ -121,9 +125,11 @@ config BPF_JIT bool "enable BPF Just In Time compiler" depends on HAVE_BPF_JIT ---- a/net/core/dev.c -+++ b/net/core/dev.c -@@ -5524,6 +5524,9 @@ +Index: linux-3.2.46/net/core/dev.c +=================================================================== +--- linux-3.2.46.orig/net/core/dev.c 2013-07-26 19:24:13.000000000 +0000 ++++ linux-3.2.46/net/core/dev.c 2013-07-26 19:24:18.000000000 +0000 +@@ -5538,6 +5538,9 @@ queue->xmit_lock_owner = -1; netdev_queue_numa_node_write(queue, NUMA_NO_NODE); queue->dev = dev; @@ -133,8 +139,10 @@ } static int netif_alloc_netdev_queues(struct net_device *dev) ---- a/net/core/net-sysfs.c -+++ b/net/core/net-sysfs.c +Index: linux-3.2.46/net/core/net-sysfs.c +=================================================================== +--- linux-3.2.46.orig/net/core/net-sysfs.c 2013-07-26 19:24:16.000000000 +0000 ++++ linux-3.2.46/net/core/net-sysfs.c 2013-07-26 19:24:18.000000000 +0000 @@ -21,6 +21,7 @@ #include #include diff -Nru linux-3.2.46/debian/patches/features/all/bql/bql-fix-config_xps-n-build.patch linux-3.2.46/debian/patches/features/all/bql/bql-fix-config_xps-n-build.patch --- linux-3.2.46/debian/patches/features/all/bql/bql-fix-config_xps-n-build.patch 2013-02-24 03:52:36.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/bql/bql-fix-config_xps-n-build.patch 2013-07-26 19:24:20.000000000 +0000 @@ -13,11 +13,11 @@ net/core/net-sysfs.c | 2 -- 1 file changed, 2 deletions(-) -diff --git a/net/core/net-sysfs.c b/net/core/net-sysfs.c -index 3bf72b6..9d13463 100644 ---- a/net/core/net-sysfs.c -+++ b/net/core/net-sysfs.c -@@ -1221,9 +1221,7 @@ static void netdev_queue_release(struct kobject *kobj) +Index: linux-3.2.46/net/core/net-sysfs.c +=================================================================== +--- linux-3.2.46.orig/net/core/net-sysfs.c 2013-07-26 19:24:18.000000000 +0000 ++++ linux-3.2.46/net/core/net-sysfs.c 2013-07-26 19:24:19.000000000 +0000 +@@ -1221,9 +1221,7 @@ static struct kobj_type netdev_queue_ktype = { .sysfs_ops = &netdev_queue_sysfs_ops, diff -Nru linux-3.2.46/debian/patches/features/all/bql/bql-fix-inconsistency-between-file-mode-and-attr-method.patch linux-3.2.46/debian/patches/features/all/bql/bql-fix-inconsistency-between-file-mode-and-attr-method.patch --- linux-3.2.46/debian/patches/features/all/bql/bql-fix-inconsistency-between-file-mode-and-attr-method.patch 2013-02-24 03:52:36.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/bql/bql-fix-inconsistency-between-file-mode-and-attr-method.patch 2013-07-26 19:24:21.000000000 +0000 @@ -15,11 +15,11 @@ net/core/net-sysfs.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -diff --git a/net/core/net-sysfs.c b/net/core/net-sysfs.c -index f3dbd4f..a1727cd 100644 ---- a/net/core/net-sysfs.c -+++ b/net/core/net-sysfs.c -@@ -929,7 +929,7 @@ static ssize_t bql_show_inflight(struct netdev_queue *queue, +Index: linux-3.2.46/net/core/net-sysfs.c +=================================================================== +--- linux-3.2.46.orig/net/core/net-sysfs.c 2013-07-26 19:24:19.000000000 +0000 ++++ linux-3.2.46/net/core/net-sysfs.c 2013-07-26 19:24:20.000000000 +0000 +@@ -916,7 +916,7 @@ } static struct netdev_queue_attribute bql_inflight_attribute = diff -Nru linux-3.2.46/debian/patches/features/all/bql/bql-fix-posdiff-to-integer-overflow-aware.patch linux-3.2.46/debian/patches/features/all/bql/bql-fix-posdiff-to-integer-overflow-aware.patch --- linux-3.2.46/debian/patches/features/all/bql/bql-fix-posdiff-to-integer-overflow-aware.patch 2013-02-24 03:52:36.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/bql/bql-fix-posdiff-to-integer-overflow-aware.patch 2013-07-26 19:24:24.000000000 +0000 @@ -16,10 +16,10 @@ lib/dynamic_queue_limits.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -diff --git a/lib/dynamic_queue_limits.c b/lib/dynamic_queue_limits.c -index 6ab4587..c87eb76 100644 ---- a/lib/dynamic_queue_limits.c -+++ b/lib/dynamic_queue_limits.c +Index: linux-3.2.46/lib/dynamic_queue_limits.c +=================================================================== +--- linux-3.2.46.orig/lib/dynamic_queue_limits.c 2013-07-26 19:24:22.000000000 +0000 ++++ linux-3.2.46/lib/dynamic_queue_limits.c 2013-07-26 19:24:23.000000000 +0000 @@ -10,7 +10,7 @@ #include #include diff -Nru linux-3.2.46/debian/patches/features/all/bql/dql-dynamic-queue-limits.patch linux-3.2.46/debian/patches/features/all/bql/dql-dynamic-queue-limits.patch --- linux-3.2.46/debian/patches/features/all/bql/dql-dynamic-queue-limits.patch 2013-02-24 03:52:36.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/bql/dql-dynamic-queue-limits.patch 2013-07-26 19:24:13.000000000 +0000 @@ -57,11 +57,10 @@ create mode 100644 include/linux/dynamic_queue_limits.h create mode 100644 lib/dynamic_queue_limits.c -diff --git a/include/linux/dynamic_queue_limits.h b/include/linux/dynamic_queue_limits.h -new file mode 100644 -index 0000000..5621547 ---- /dev/null -+++ b/include/linux/dynamic_queue_limits.h +Index: linux-3.2.46/include/linux/dynamic_queue_limits.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/include/linux/dynamic_queue_limits.h 2013-07-26 19:24:12.000000000 +0000 @@ -0,0 +1,97 @@ +/* + * Dynamic queue limits (dql) - Definitions @@ -160,11 +159,11 @@ +#endif /* _KERNEL_ */ + +#endif /* _LINUX_DQL_H */ -diff --git a/lib/Kconfig b/lib/Kconfig -index 32f3e5a..63b5782 100644 ---- a/lib/Kconfig -+++ b/lib/Kconfig -@@ -244,6 +244,9 @@ config CPU_RMAP +Index: linux-3.2.46/lib/Kconfig +=================================================================== +--- linux-3.2.46.orig/lib/Kconfig 2013-07-26 18:54:21.000000000 +0000 ++++ linux-3.2.46/lib/Kconfig 2013-07-26 19:24:12.000000000 +0000 +@@ -244,6 +244,9 @@ bool depends on SMP @@ -174,11 +173,11 @@ # # Netlink attribute parsing support is select'ed if needed # -diff --git a/lib/Makefile b/lib/Makefile -index a4da283..ff00d4d 100644 ---- a/lib/Makefile -+++ b/lib/Makefile -@@ -115,6 +115,8 @@ obj-$(CONFIG_CPU_RMAP) += cpu_rmap.o +Index: linux-3.2.46/lib/Makefile +=================================================================== +--- linux-3.2.46.orig/lib/Makefile 2013-07-26 18:54:21.000000000 +0000 ++++ linux-3.2.46/lib/Makefile 2013-07-26 19:24:12.000000000 +0000 +@@ -115,6 +115,8 @@ obj-$(CONFIG_CORDIC) += cordic.o @@ -187,11 +186,10 @@ hostprogs-y := gen_crc32table clean-files := crc32table.h -diff --git a/lib/dynamic_queue_limits.c b/lib/dynamic_queue_limits.c -new file mode 100644 -index 0000000..3d1bdcd ---- /dev/null -+++ b/lib/dynamic_queue_limits.c +Index: linux-3.2.46/lib/dynamic_queue_limits.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/lib/dynamic_queue_limits.c 2013-07-26 19:24:12.000000000 +0000 @@ -0,0 +1,133 @@ +/* + * Dynamic byte queue limits. See include/linux/dynamic_queue_limits.h diff -Nru linux-3.2.46/debian/patches/features/all/bql/dql-fix-undefined-jiffies.patch linux-3.2.46/debian/patches/features/all/bql/dql-fix-undefined-jiffies.patch --- linux-3.2.46/debian/patches/features/all/bql/dql-fix-undefined-jiffies.patch 2013-02-24 03:52:36.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/bql/dql-fix-undefined-jiffies.patch 2013-07-26 19:24:23.000000000 +0000 @@ -14,10 +14,10 @@ lib/dynamic_queue_limits.c | 1 + 1 file changed, 1 insertion(+) -diff --git a/lib/dynamic_queue_limits.c b/lib/dynamic_queue_limits.c -index 3d1bdcd..6ab4587 100644 ---- a/lib/dynamic_queue_limits.c -+++ b/lib/dynamic_queue_limits.c +Index: linux-3.2.46/lib/dynamic_queue_limits.c +=================================================================== +--- linux-3.2.46.orig/lib/dynamic_queue_limits.c 2013-07-26 19:24:12.000000000 +0000 ++++ linux-3.2.46/lib/dynamic_queue_limits.c 2013-07-26 19:24:22.000000000 +0000 @@ -7,6 +7,7 @@ #include #include diff -Nru linux-3.2.46/debian/patches/features/all/bql/e1000e-Change-wthresh-to-1-to-avoid-possible-Tx-stal.patch linux-3.2.46/debian/patches/features/all/bql/e1000e-Change-wthresh-to-1-to-avoid-possible-Tx-stal.patch --- linux-3.2.46/debian/patches/features/all/bql/e1000e-Change-wthresh-to-1-to-avoid-possible-Tx-stal.patch 2013-02-24 03:52:36.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/bql/e1000e-Change-wthresh-to-1-to-avoid-possible-Tx-stal.patch 2013-07-26 19:24:29.000000000 +0000 @@ -44,11 +44,11 @@ drivers/net/ethernet/intel/e1000e/netdev.c | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) -diff --git a/drivers/net/ethernet/intel/e1000e/e1000.h b/drivers/net/ethernet/intel/e1000e/e1000.h -index cb3356c..04668b4 100644 ---- a/drivers/net/ethernet/intel/e1000e/e1000.h -+++ b/drivers/net/ethernet/intel/e1000e/e1000.h -@@ -175,13 +175,13 @@ struct e1000_info; +Index: linux-3.2.46/drivers/net/ethernet/intel/e1000e/e1000.h +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/intel/e1000e/e1000.h 2013-07-26 18:54:16.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/intel/e1000e/e1000.h 2013-07-26 19:24:28.000000000 +0000 +@@ -169,13 +169,13 @@ /* * in the case of WTHRESH, it appears at least the 82571/2 hardware * writes back 4 descriptors when WTHRESH=5, and 3 descriptors when @@ -65,11 +65,11 @@ (1 << 8) | /* hthresh */ \ 0x1f) /* pthresh */ -diff --git a/drivers/net/ethernet/intel/e1000e/netdev.c b/drivers/net/ethernet/intel/e1000e/netdev.c -index de57a2b..f444eb0 100644 ---- a/drivers/net/ethernet/intel/e1000e/netdev.c -+++ b/drivers/net/ethernet/intel/e1000e/netdev.c -@@ -2831,7 +2831,7 @@ static void e1000_configure_tx(struct e1000_adapter *adapter) +Index: linux-3.2.46/drivers/net/ethernet/intel/e1000e/netdev.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/intel/e1000e/netdev.c 2013-07-26 19:24:27.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/intel/e1000e/netdev.c 2013-07-26 19:24:28.000000000 +0000 +@@ -2801,7 +2801,7 @@ * set up some performance related parameters to encourage the * hardware to use the bus more efficiently in bursts, depends * on the tx_int_delay to be enabled, diff -Nru linux-3.2.46/debian/patches/features/all/bql/e1000e-support-for-byte-queue-limits.patch linux-3.2.46/debian/patches/features/all/bql/e1000e-support-for-byte-queue-limits.patch --- linux-3.2.46/debian/patches/features/all/bql/e1000e-support-for-byte-queue-limits.patch 2013-02-24 03:52:36.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/bql/e1000e-support-for-byte-queue-limits.patch 2013-07-26 19:24:28.000000000 +0000 @@ -13,9 +13,11 @@ drivers/net/ethernet/intel/e1000e/netdev.c | 9 +++++++++ 1 file changed, 9 insertions(+) ---- a/drivers/net/ethernet/intel/e1000e/netdev.c -+++ b/drivers/net/ethernet/intel/e1000e/netdev.c -@@ -1111,6 +1111,7 @@ static bool e1000_clean_tx_irq(struct e1 +Index: linux-3.2.46/drivers/net/ethernet/intel/e1000e/netdev.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/intel/e1000e/netdev.c 2013-07-26 18:54:16.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/intel/e1000e/netdev.c 2013-07-26 19:24:27.000000000 +0000 +@@ -1111,6 +1111,7 @@ unsigned int i, eop; unsigned int count = 0; unsigned int total_tx_bytes = 0, total_tx_packets = 0; @@ -23,7 +25,7 @@ i = tx_ring->next_to_clean; eop = tx_ring->buffer_info[i].next_to_watch; -@@ -1128,6 +1129,10 @@ static bool e1000_clean_tx_irq(struct e1 +@@ -1128,6 +1129,10 @@ if (cleaned) { total_tx_packets += buffer_info->segs; total_tx_bytes += buffer_info->bytecount; @@ -34,7 +36,7 @@ } e1000_put_txbuf(adapter, buffer_info); -@@ -1146,6 +1151,8 @@ static bool e1000_clean_tx_irq(struct e1 +@@ -1146,6 +1151,8 @@ tx_ring->next_to_clean = i; @@ -43,7 +45,7 @@ #define TX_WAKE_THRESHOLD 32 if (count && netif_carrier_ok(netdev) && e1000_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD) { -@@ -2276,6 +2283,7 @@ static void e1000_clean_tx_ring(struct e +@@ -2276,6 +2283,7 @@ e1000_put_txbuf(adapter, buffer_info); } @@ -51,7 +53,7 @@ size = sizeof(struct e1000_buffer) * tx_ring->count; memset(tx_ring->buffer_info, 0, size); -@@ -4997,6 +5005,7 @@ static netdev_tx_t e1000_xmit_frame(stru +@@ -4997,6 +5005,7 @@ count = e1000_tx_map(adapter, skb, first, adapter->tx_fifo_limit, nr_frags); if (count) { diff -Nru linux-3.2.46/debian/patches/features/all/bql/forcedeath-fix-bql-support-for-forcedeath.patch linux-3.2.46/debian/patches/features/all/bql/forcedeath-fix-bql-support-for-forcedeath.patch --- linux-3.2.46/debian/patches/features/all/bql/forcedeath-fix-bql-support-for-forcedeath.patch 2013-02-24 03:52:36.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/bql/forcedeath-fix-bql-support-for-forcedeath.patch 2013-07-26 19:24:32.000000000 +0000 @@ -16,11 +16,11 @@ drivers/net/ethernet/nvidia/forcedeth.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) -diff --git a/drivers/net/ethernet/nvidia/forcedeth.c b/drivers/net/ethernet/nvidia/forcedeth.c -index 5245dac..4c4e7f4 100644 ---- a/drivers/net/ethernet/nvidia/forcedeth.c -+++ b/drivers/net/ethernet/nvidia/forcedeth.c -@@ -2561,13 +2561,14 @@ static int nv_tx_done_optimized(struct net_device *dev, int limit) +Index: linux-3.2.46/drivers/net/ethernet/nvidia/forcedeth.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/nvidia/forcedeth.c 2013-07-26 19:24:30.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/nvidia/forcedeth.c 2013-07-26 19:24:31.000000000 +0000 +@@ -2470,13 +2470,14 @@ nv_tx_flip_ownership(dev); } diff -Nru linux-3.2.46/debian/patches/features/all/bql/forcedeth-support-for-byte-queue-limits.patch linux-3.2.46/debian/patches/features/all/bql/forcedeth-support-for-byte-queue-limits.patch --- linux-3.2.46/debian/patches/features/all/bql/forcedeth-support-for-byte-queue-limits.patch 2013-02-24 03:52:36.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/bql/forcedeth-support-for-byte-queue-limits.patch 2013-07-26 19:24:31.000000000 +0000 @@ -13,8 +13,10 @@ drivers/net/ethernet/nvidia/forcedeth.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) ---- a/drivers/net/ethernet/nvidia/forcedeth.c -+++ b/drivers/net/ethernet/nvidia/forcedeth.c +Index: linux-3.2.46/drivers/net/ethernet/nvidia/forcedeth.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/nvidia/forcedeth.c 2013-07-26 18:54:16.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/nvidia/forcedeth.c 2013-07-26 19:24:30.000000000 +0000 @@ -1849,6 +1849,7 @@ np->last_tx.ex = &np->tx_ring.ex[np->tx_ring_size-1]; np->get_tx_ctx = np->put_tx_ctx = np->first_tx_ctx = np->tx_skb; diff -Nru linux-3.2.46/debian/patches/features/all/bql/igb-add-support-for-byte-queue-limits.patch linux-3.2.46/debian/patches/features/all/bql/igb-add-support-for-byte-queue-limits.patch --- linux-3.2.46/debian/patches/features/all/bql/igb-add-support-for-byte-queue-limits.patch 2013-02-24 03:52:36.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/bql/igb-add-support-for-byte-queue-limits.patch 2013-07-26 19:24:46.000000000 +0000 @@ -19,11 +19,11 @@ drivers/net/ethernet/intel/igb/igb_main.c | 5 +++++ 2 files changed, 10 insertions(+) -diff --git a/drivers/net/ethernet/intel/igb/igb.h b/drivers/net/ethernet/intel/igb/igb.h -index c69feeb..3d12e67 100644 ---- a/drivers/net/ethernet/intel/igb/igb.h -+++ b/drivers/net/ethernet/intel/igb/igb.h -@@ -447,4 +447,9 @@ static inline s32 igb_get_phy_info(struct e1000_hw *hw) +Index: linux-3.2.46/drivers/net/ethernet/intel/igb/igb.h +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/intel/igb/igb.h 2013-07-26 18:54:11.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/intel/igb/igb.h 2013-07-26 19:24:45.000000000 +0000 +@@ -447,4 +447,9 @@ return 0; } @@ -33,11 +33,11 @@ +} + #endif /* _IGB_H_ */ -diff --git a/drivers/net/ethernet/intel/igb/igb_main.c b/drivers/net/ethernet/intel/igb/igb_main.c -index 89d576c..dcc68cc 100644 ---- a/drivers/net/ethernet/intel/igb/igb_main.c -+++ b/drivers/net/ethernet/intel/igb/igb_main.c -@@ -3201,6 +3201,7 @@ static void igb_clean_tx_ring(struct igb_ring *tx_ring) +Index: linux-3.2.46/drivers/net/ethernet/intel/igb/igb_main.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/intel/igb/igb_main.c 2013-07-26 18:54:11.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/intel/igb/igb_main.c 2013-07-26 19:24:45.000000000 +0000 +@@ -3213,6 +3213,7 @@ buffer_info = &tx_ring->tx_buffer_info[i]; igb_unmap_and_free_tx_resource(tx_ring, buffer_info); } @@ -45,7 +45,7 @@ size = sizeof(struct igb_tx_buffer) * tx_ring->count; memset(tx_ring->tx_buffer_info, 0, size); -@@ -4238,6 +4239,8 @@ static void igb_tx_map(struct igb_ring *tx_ring, +@@ -4251,6 +4252,8 @@ frag++; } @@ -54,7 +54,7 @@ /* write last descriptor with RS and EOP bits */ cmd_type |= cpu_to_le32(size) | cpu_to_le32(IGB_TXD_DCMD); tx_desc->read.cmd_type_len = cmd_type; -@@ -5777,6 +5780,8 @@ static bool igb_clean_tx_irq(struct igb_q_vector *q_vector) +@@ -5793,6 +5796,8 @@ } } diff -Nru linux-3.2.46/debian/patches/features/all/bql/igb-fix-ethtool-offline-test.patch linux-3.2.46/debian/patches/features/all/bql/igb-fix-ethtool-offline-test.patch --- linux-3.2.46/debian/patches/features/all/bql/igb-fix-ethtool-offline-test.patch 2013-02-24 03:52:36.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/bql/igb-fix-ethtool-offline-test.patch 2013-07-26 19:24:47.000000000 +0000 @@ -21,11 +21,11 @@ drivers/net/ethernet/intel/igb/igb_ethtool.c | 7 +++++++ 1 file changed, 7 insertions(+) -diff --git a/drivers/net/ethernet/intel/igb/igb_ethtool.c b/drivers/net/ethernet/intel/igb/igb_ethtool.c -index aa399a8..e10821a 100644 ---- a/drivers/net/ethernet/intel/igb/igb_ethtool.c -+++ b/drivers/net/ethernet/intel/igb/igb_ethtool.c -@@ -1577,7 +1577,9 @@ static int igb_clean_test_rings(struct igb_ring *rx_ring, +Index: linux-3.2.46/drivers/net/ethernet/intel/igb/igb_ethtool.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/intel/igb/igb_ethtool.c 2013-07-26 18:54:10.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/intel/igb/igb_ethtool.c 2013-07-26 19:24:46.000000000 +0000 +@@ -1577,7 +1577,9 @@ union e1000_adv_rx_desc *rx_desc; struct igb_rx_buffer *rx_buffer_info; struct igb_tx_buffer *tx_buffer_info; @@ -35,7 +35,7 @@ /* initialize next to clean and descriptor values */ rx_ntc = rx_ring->next_to_clean; -@@ -1601,6 +1603,8 @@ static int igb_clean_test_rings(struct igb_ring *rx_ring, +@@ -1601,6 +1603,8 @@ /* unmap buffer on tx side */ tx_buffer_info = &tx_ring->tx_buffer_info[tx_ntc]; @@ -44,7 +44,7 @@ igb_unmap_and_free_tx_resource(tx_ring, tx_buffer_info); /* increment rx/tx next to clean counters */ -@@ -1615,6 +1619,9 @@ static int igb_clean_test_rings(struct igb_ring *rx_ring, +@@ -1615,6 +1619,9 @@ rx_desc = IGB_RX_DESC(rx_ring, rx_ntc); } diff -Nru linux-3.2.46/debian/patches/features/all/bql/igb-ixgbe-netdev_tx_reset_queue-incorrectly-called-from-tx-init.patch linux-3.2.46/debian/patches/features/all/bql/igb-ixgbe-netdev_tx_reset_queue-incorrectly-called-from-tx-init.patch --- linux-3.2.46/debian/patches/features/all/bql/igb-ixgbe-netdev_tx_reset_queue-incorrectly-called-from-tx-init.patch 2013-02-24 03:52:36.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/bql/igb-ixgbe-netdev_tx_reset_queue-incorrectly-called-from-tx-init.patch 2013-07-26 19:24:51.000000000 +0000 @@ -26,9 +26,11 @@ drivers/net/ethernet/intel/ixgbe/ixgbe_main.c | 4 ++-- 3 files changed, 6 insertions(+), 4 deletions(-) ---- a/drivers/net/ethernet/intel/igb/igb_main.c -+++ b/drivers/net/ethernet/intel/igb/igb_main.c -@@ -2711,8 +2711,6 @@ +Index: linux-3.2.46/drivers/net/ethernet/intel/igb/igb_main.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/intel/igb/igb_main.c 2013-07-26 19:24:47.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/intel/igb/igb_main.c 2013-07-26 19:24:50.000000000 +0000 +@@ -2721,8 +2721,6 @@ txdctl |= E1000_TXDCTL_QUEUE_ENABLE; wr32(E1000_TXDCTL(reg_idx), txdctl); @@ -37,7 +39,7 @@ } /** -@@ -3206,6 +3204,8 @@ +@@ -3216,6 +3214,8 @@ igb_unmap_and_free_tx_resource(tx_ring, buffer_info); } @@ -46,8 +48,10 @@ size = sizeof(struct igb_tx_buffer) * tx_ring->count; memset(tx_ring->tx_buffer_info, 0, size); ---- a/drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c -+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c +Index: linux-3.2.46/drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c 2013-07-26 18:54:08.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c 2013-07-26 19:24:50.000000000 +0000 @@ -1764,6 +1764,8 @@ staterr = le32_to_cpu(rx_desc->wb.upper.status_error); } @@ -57,9 +61,11 @@ /* re-map buffers to ring, store next to clean values */ ixgbe_alloc_rx_buffers(rx_ring, count); rx_ring->next_to_clean = rx_ntc; ---- a/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c -+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c -@@ -2411,8 +2411,6 @@ +Index: linux-3.2.46/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c 2013-07-26 19:24:49.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c 2013-07-26 19:24:50.000000000 +0000 +@@ -2423,8 +2423,6 @@ /* enable queue */ IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl); @@ -68,7 +74,7 @@ /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */ if (hw->mac.type == ixgbe_mac_82598EB && !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) -@@ -3930,6 +3928,8 @@ +@@ -3942,6 +3940,8 @@ ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info); } diff -Nru linux-3.2.46/debian/patches/features/all/bql/ixgbe-add-support-for-byte-queue-limits.patch linux-3.2.46/debian/patches/features/all/bql/ixgbe-add-support-for-byte-queue-limits.patch --- linux-3.2.46/debian/patches/features/all/bql/ixgbe-add-support-for-byte-queue-limits.patch 2013-02-24 03:52:36.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/bql/ixgbe-add-support-for-byte-queue-limits.patch 2013-07-26 19:24:50.000000000 +0000 @@ -15,8 +15,10 @@ drivers/net/ethernet/intel/ixgbe/ixgbe_main.c | 7 +++++++ 2 files changed, 12 insertions(+) ---- a/drivers/net/ethernet/intel/ixgbe/ixgbe.h -+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe.h +Index: linux-3.2.46/drivers/net/ethernet/intel/ixgbe/ixgbe.h +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/intel/ixgbe/ixgbe.h 2013-07-26 18:54:09.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/intel/ixgbe/ixgbe.h 2013-07-26 19:24:49.000000000 +0000 @@ -629,4 +629,9 @@ extern int ixgbe_fcoe_get_wwn(struct net_device *netdev, u64 *wwn, int type); #endif /* IXGBE_FCOE */ @@ -27,9 +29,11 @@ +} + #endif /* _IXGBE_H_ */ ---- a/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c -+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c -@@ -832,6 +832,9 @@ +Index: linux-3.2.46/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c 2013-07-26 18:54:09.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c 2013-07-26 19:24:49.000000000 +0000 +@@ -834,6 +834,9 @@ return true; } @@ -39,7 +43,7 @@ #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2) if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) && (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) { -@@ -2408,6 +2411,8 @@ +@@ -2420,6 +2423,8 @@ /* enable queue */ IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl); @@ -48,7 +52,7 @@ /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */ if (hw->mac.type == ixgbe_mac_82598EB && !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP)) -@@ -6581,6 +6586,8 @@ +@@ -6595,6 +6600,8 @@ tx_buffer_info->gso_segs = gso_segs; tx_buffer_info->skb = skb; diff -Nru linux-3.2.46/debian/patches/features/all/bql/net-add-netdev-interfaces-for-recording-sends-comp.patch linux-3.2.46/debian/patches/features/all/bql/net-add-netdev-interfaces-for-recording-sends-comp.patch --- linux-3.2.46/debian/patches/features/all/bql/net-add-netdev-interfaces-for-recording-sends-comp.patch 2013-02-24 03:52:36.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/bql/net-add-netdev-interfaces-for-recording-sends-comp.patch 2013-07-26 19:24:16.000000000 +0000 @@ -15,11 +15,11 @@ include/linux/netdevice.h | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) -diff --git a/include/linux/netdevice.h b/include/linux/netdevice.h -index d19f932..9b24cc7 100644 ---- a/include/linux/netdevice.h -+++ b/include/linux/netdevice.h -@@ -1859,6 +1859,34 @@ static inline int netif_xmit_frozen_or_stopped(const struct netdev_queue *dev_qu +Index: linux-3.2.46/include/linux/netdevice.h +=================================================================== +--- linux-3.2.46.orig/include/linux/netdevice.h 2013-07-26 19:24:13.000000000 +0000 ++++ linux-3.2.46/include/linux/netdevice.h 2013-07-26 19:24:15.000000000 +0000 +@@ -1927,6 +1927,34 @@ return dev_queue->state & QUEUE_STATE_ANY_XOFF_OR_FROZEN; } diff -Nru linux-3.2.46/debian/patches/features/all/bql/net-add-queue-state-xoff-flag-for-stack.patch linux-3.2.46/debian/patches/features/all/bql/net-add-queue-state-xoff-flag-for-stack.patch --- linux-3.2.46/debian/patches/features/all/bql/net-add-queue-state-xoff-flag-for-stack.patch 2013-02-24 03:52:36.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/bql/net-add-queue-state-xoff-flag-for-stack.patch 2013-07-26 19:24:15.000000000 +0000 @@ -21,11 +21,11 @@ net/sched/sch_teql.c | 6 +++--- 7 files changed, 46 insertions(+), 25 deletions(-) -diff --git a/include/linux/netdevice.h b/include/linux/netdevice.h -index ac9a4b9..d19f932 100644 ---- a/include/linux/netdevice.h -+++ b/include/linux/netdevice.h -@@ -517,11 +517,23 @@ static inline void napi_synchronize(const struct napi_struct *n) +Index: linux-3.2.46/include/linux/netdevice.h +=================================================================== +--- linux-3.2.46.orig/include/linux/netdevice.h 2013-07-26 19:24:10.000000000 +0000 ++++ linux-3.2.46/include/linux/netdevice.h 2013-07-26 19:24:13.000000000 +0000 +@@ -516,11 +516,23 @@ #endif enum netdev_queue_state_t { @@ -52,7 +52,7 @@ struct netdev_queue { /* -@@ -1718,7 +1730,7 @@ extern void __netif_schedule(struct Qdisc *q); +@@ -1786,7 +1798,7 @@ static inline void netif_schedule_queue(struct netdev_queue *txq) { @@ -61,7 +61,7 @@ __netif_schedule(txq->qdisc); } -@@ -1732,7 +1744,7 @@ static inline void netif_tx_schedule_all(struct net_device *dev) +@@ -1800,7 +1812,7 @@ static inline void netif_tx_start_queue(struct netdev_queue *dev_queue) { @@ -70,7 +70,7 @@ } /** -@@ -1764,7 +1776,7 @@ static inline void netif_tx_wake_queue(struct netdev_queue *dev_queue) +@@ -1832,7 +1844,7 @@ return; } #endif @@ -79,7 +79,7 @@ __netif_schedule(dev_queue->qdisc); } -@@ -1796,7 +1808,7 @@ static inline void netif_tx_stop_queue(struct netdev_queue *dev_queue) +@@ -1864,7 +1876,7 @@ pr_info("netif_stop_queue() cannot be called before register_netdev()\n"); return; } @@ -88,7 +88,7 @@ } /** -@@ -1823,7 +1835,7 @@ static inline void netif_tx_stop_all_queues(struct net_device *dev) +@@ -1891,7 +1903,7 @@ static inline int netif_tx_queue_stopped(const struct netdev_queue *dev_queue) { @@ -97,7 +97,7 @@ } /** -@@ -1837,9 +1849,16 @@ static inline int netif_queue_stopped(const struct net_device *dev) +@@ -1905,9 +1917,16 @@ return netif_tx_queue_stopped(netdev_get_tx_queue(dev, 0)); } @@ -116,7 +116,7 @@ } /** -@@ -1926,7 +1945,7 @@ static inline void netif_wake_subqueue(struct net_device *dev, u16 queue_index) +@@ -1994,7 +2013,7 @@ if (netpoll_trap()) return; #endif @@ -125,11 +125,11 @@ __netif_schedule(txq->qdisc); } -diff --git a/net/core/dev.c b/net/core/dev.c -index c7ef6c5..cb8f753 100644 ---- a/net/core/dev.c -+++ b/net/core/dev.c -@@ -2270,7 +2270,7 @@ gso: +Index: linux-3.2.46/net/core/dev.c +=================================================================== +--- linux-3.2.46.orig/net/core/dev.c 2013-07-26 18:54:21.000000000 +0000 ++++ linux-3.2.46/net/core/dev.c 2013-07-26 19:24:13.000000000 +0000 +@@ -2251,7 +2251,7 @@ return rc; } txq_trans_update(txq); @@ -138,7 +138,7 @@ return NETDEV_TX_BUSY; } while (skb->next); -@@ -2558,7 +2558,7 @@ int dev_queue_xmit(struct sk_buff *skb) +@@ -2525,7 +2525,7 @@ HARD_TX_LOCK(dev, txq, cpu); @@ -147,11 +147,11 @@ __this_cpu_inc(xmit_recursion); rc = dev_hard_start_xmit(skb, dev, txq); __this_cpu_dec(xmit_recursion); -diff --git a/net/core/netpoll.c b/net/core/netpoll.c -index 1a7d8e2..0d38808 100644 ---- a/net/core/netpoll.c -+++ b/net/core/netpoll.c -@@ -76,7 +76,7 @@ static void queue_process(struct work_struct *work) +Index: linux-3.2.46/net/core/netpoll.c +=================================================================== +--- linux-3.2.46.orig/net/core/netpoll.c 2013-07-26 18:54:21.000000000 +0000 ++++ linux-3.2.46/net/core/netpoll.c 2013-07-26 19:24:13.000000000 +0000 +@@ -76,7 +76,7 @@ local_irq_save(flags); __netif_tx_lock(txq, smp_processor_id()); @@ -160,7 +160,7 @@ ops->ndo_start_xmit(skb, dev) != NETDEV_TX_OK) { skb_queue_head(&npinfo->txq, skb); __netif_tx_unlock(txq); -@@ -317,7 +317,7 @@ void netpoll_send_skb_on_dev(struct netpoll *np, struct sk_buff *skb, +@@ -317,7 +317,7 @@ for (tries = jiffies_to_usecs(1)/USEC_PER_POLL; tries > 0; --tries) { if (__netif_tx_trylock(txq)) { @@ -169,11 +169,11 @@ status = ops->ndo_start_xmit(skb, dev); if (status == NETDEV_TX_OK) txq_trans_update(txq); -diff --git a/net/core/pktgen.c b/net/core/pktgen.c -index aa53a35..449fe0f 100644 ---- a/net/core/pktgen.c -+++ b/net/core/pktgen.c -@@ -3342,7 +3342,7 @@ static void pktgen_xmit(struct pktgen_dev *pkt_dev) +Index: linux-3.2.46/net/core/pktgen.c +=================================================================== +--- linux-3.2.46.orig/net/core/pktgen.c 2013-07-26 18:54:21.000000000 +0000 ++++ linux-3.2.46/net/core/pktgen.c 2013-07-26 19:24:13.000000000 +0000 +@@ -3348,7 +3348,7 @@ __netif_tx_lock_bh(txq); @@ -182,11 +182,11 @@ ret = NETDEV_TX_BUSY; pkt_dev->last_ok = 0; goto unlock; -diff --git a/net/sched/sch_generic.c b/net/sched/sch_generic.c -index 79ac145..67fc573 100644 ---- a/net/sched/sch_generic.c -+++ b/net/sched/sch_generic.c -@@ -60,7 +60,7 @@ static inline struct sk_buff *dequeue_skb(struct Qdisc *q) +Index: linux-3.2.46/net/sched/sch_generic.c +=================================================================== +--- linux-3.2.46.orig/net/sched/sch_generic.c 2013-07-26 19:24:10.000000000 +0000 ++++ linux-3.2.46/net/sched/sch_generic.c 2013-07-26 19:24:13.000000000 +0000 +@@ -60,7 +60,7 @@ /* check the reason of requeuing without tx lock first */ txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb)); @@ -195,7 +195,7 @@ q->gso_skb = NULL; q->q.qlen--; } else -@@ -121,7 +121,7 @@ int sch_direct_xmit(struct sk_buff *skb, struct Qdisc *q, +@@ -121,7 +121,7 @@ spin_unlock(root_lock); HARD_TX_LOCK(dev, txq, smp_processor_id()); @@ -204,7 +204,7 @@ ret = dev_hard_start_xmit(skb, dev, txq); HARD_TX_UNLOCK(dev, txq); -@@ -143,7 +143,7 @@ int sch_direct_xmit(struct sk_buff *skb, struct Qdisc *q, +@@ -143,7 +143,7 @@ ret = dev_requeue_skb(skb, q); } @@ -213,7 +213,7 @@ ret = 0; return ret; -@@ -242,7 +242,7 @@ static void dev_watchdog(unsigned long arg) +@@ -242,7 +242,7 @@ * old device drivers set dev->trans_start */ trans_start = txq->trans_start ? : dev->trans_start; @@ -222,11 +222,11 @@ time_after(jiffies, (trans_start + dev->watchdog_timeo))) { some_queue_timedout = 1; -diff --git a/net/sched/sch_multiq.c b/net/sched/sch_multiq.c -index edc1950..49131d7 100644 ---- a/net/sched/sch_multiq.c -+++ b/net/sched/sch_multiq.c -@@ -107,7 +107,8 @@ static struct sk_buff *multiq_dequeue(struct Qdisc *sch) +Index: linux-3.2.46/net/sched/sch_multiq.c +=================================================================== +--- linux-3.2.46.orig/net/sched/sch_multiq.c 2013-07-26 18:54:21.000000000 +0000 ++++ linux-3.2.46/net/sched/sch_multiq.c 2013-07-26 19:24:13.000000000 +0000 +@@ -107,7 +107,8 @@ /* Check that target subqueue is available before * pulling an skb to avoid head-of-line blocking. */ @@ -236,7 +236,7 @@ qdisc = q->queues[q->curband]; skb = qdisc->dequeue(qdisc); if (skb) { -@@ -138,7 +139,8 @@ static struct sk_buff *multiq_peek(struct Qdisc *sch) +@@ -138,7 +139,8 @@ /* Check that target subqueue is available before * pulling an skb to avoid head-of-line blocking. */ @@ -246,11 +246,11 @@ qdisc = q->queues[curband]; skb = qdisc->ops->peek(qdisc); if (skb) -diff --git a/net/sched/sch_teql.c b/net/sched/sch_teql.c -index a3b7120..283bfe3 100644 ---- a/net/sched/sch_teql.c -+++ b/net/sched/sch_teql.c -@@ -301,7 +301,7 @@ restart: +Index: linux-3.2.46/net/sched/sch_teql.c +=================================================================== +--- linux-3.2.46.orig/net/sched/sch_teql.c 2013-07-26 18:54:21.000000000 +0000 ++++ linux-3.2.46/net/sched/sch_teql.c 2013-07-26 19:24:13.000000000 +0000 +@@ -310,7 +310,7 @@ if (slave_txq->qdisc_sleeping != q) continue; @@ -259,7 +259,7 @@ !netif_running(slave)) { busy = 1; continue; -@@ -312,7 +312,7 @@ restart: +@@ -321,7 +321,7 @@ if (__netif_tx_trylock(slave_txq)) { unsigned int length = qdisc_pkt_len(skb); @@ -268,7 +268,7 @@ slave_ops->ndo_start_xmit(skb, slave) == NETDEV_TX_OK) { txq_trans_update(slave_txq); __netif_tx_unlock(slave_txq); -@@ -324,7 +324,7 @@ restart: +@@ -333,7 +333,7 @@ } __netif_tx_unlock(slave_txq); } diff -Nru linux-3.2.46/debian/patches/features/all/bql/net-fix-issue-with-netdev_tx_reset_queue-not-resetting-queue-from.patch linux-3.2.46/debian/patches/features/all/bql/net-fix-issue-with-netdev_tx_reset_queue-not-resetting-queue-from.patch --- linux-3.2.46/debian/patches/features/all/bql/net-fix-issue-with-netdev_tx_reset_queue-not-resetting-queue-from.patch 2013-02-24 03:52:36.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/bql/net-fix-issue-with-netdev_tx_reset_queue-not-resetting-queue-from.patch 2013-07-26 19:24:48.000000000 +0000 @@ -23,11 +23,11 @@ include/linux/netdevice.h | 1 + 2 files changed, 3 insertions(+), 1 deletion(-) -diff --git a/drivers/net/ethernet/intel/igb/igb_main.c b/drivers/net/ethernet/intel/igb/igb_main.c -index fda8247..e96cef8 100644 ---- a/drivers/net/ethernet/intel/igb/igb_main.c -+++ b/drivers/net/ethernet/intel/igb/igb_main.c -@@ -2752,6 +2752,8 @@ void igb_configure_tx_ring(struct igb_adapter *adapter, +Index: linux-3.2.46/drivers/net/ethernet/intel/igb/igb_main.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/intel/igb/igb_main.c 2013-07-26 19:24:45.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/intel/igb/igb_main.c 2013-07-26 19:24:47.000000000 +0000 +@@ -2721,6 +2721,8 @@ txdctl |= E1000_TXDCTL_QUEUE_ENABLE; wr32(E1000_TXDCTL(reg_idx), txdctl); @@ -36,7 +36,7 @@ } /** -@@ -3244,7 +3246,6 @@ static void igb_clean_tx_ring(struct igb_ring *tx_ring) +@@ -3213,7 +3215,6 @@ buffer_info = &tx_ring->tx_buffer_info[i]; igb_unmap_and_free_tx_resource(tx_ring, buffer_info); } @@ -44,11 +44,11 @@ size = sizeof(struct igb_tx_buffer) * tx_ring->count; memset(tx_ring->tx_buffer_info, 0, size); -diff --git a/include/linux/netdevice.h b/include/linux/netdevice.h -index b195a34..4bf314f 100644 ---- a/include/linux/netdevice.h -+++ b/include/linux/netdevice.h -@@ -1939,6 +1939,7 @@ static inline void netdev_completed_queue(struct net_device *dev, +Index: linux-3.2.46/include/linux/netdevice.h +=================================================================== +--- linux-3.2.46.orig/include/linux/netdevice.h 2013-07-26 19:24:18.000000000 +0000 ++++ linux-3.2.46/include/linux/netdevice.h 2013-07-26 19:24:47.000000000 +0000 +@@ -1978,6 +1978,7 @@ static inline void netdev_tx_reset_queue(struct netdev_queue *q) { #ifdef CONFIG_BQL diff -Nru linux-3.2.46/debian/patches/features/all/bql/net-new-counter-for-tx_timeout-errors-in-sysfs.patch linux-3.2.46/debian/patches/features/all/bql/net-new-counter-for-tx_timeout-errors-in-sysfs.patch --- linux-3.2.46/debian/patches/features/all/bql/net-new-counter-for-tx_timeout-errors-in-sysfs.patch 2013-02-24 03:52:36.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/bql/net-new-counter-for-tx_timeout-errors-in-sysfs.patch 2013-07-26 19:24:11.000000000 +0000 @@ -26,11 +26,11 @@ net/sched/sch_generic.c | 1 + 3 files changed, 42 insertions(+), 8 deletions(-) -diff --git a/include/linux/netdevice.h b/include/linux/netdevice.h -index 31da3bb..4d5698a 100644 ---- a/include/linux/netdevice.h -+++ b/include/linux/netdevice.h -@@ -532,7 +532,7 @@ struct netdev_queue { +Index: linux-3.2.46/include/linux/netdevice.h +=================================================================== +--- linux-3.2.46.orig/include/linux/netdevice.h 2013-07-26 18:54:22.000000000 +0000 ++++ linux-3.2.46/include/linux/netdevice.h 2013-07-26 19:24:10.000000000 +0000 +@@ -530,7 +530,7 @@ struct Qdisc *qdisc; unsigned long state; struct Qdisc *qdisc_sleeping; @@ -39,7 +39,7 @@ struct kobject kobj; #endif #if defined(CONFIG_XPS) && defined(CONFIG_NUMA) -@@ -547,6 +547,12 @@ struct netdev_queue { +@@ -545,6 +545,12 @@ * please use this field instead of dev->trans_start */ unsigned long trans_start; @@ -52,7 +52,7 @@ } ____cacheline_aligned_in_smp; static inline int netdev_queue_numa_node_read(const struct netdev_queue *q) -@@ -1109,9 +1115,11 @@ struct net_device { +@@ -1184,9 +1190,11 @@ unsigned char broadcast[MAX_ADDR_LEN]; /* hw bcast add */ @@ -65,11 +65,11 @@ struct netdev_rx_queue *_rx; /* Number of RX queues allocated at register_netdev() time */ -diff --git a/net/core/net-sysfs.c b/net/core/net-sysfs.c -index a64382f..602b141 100644 ---- a/net/core/net-sysfs.c -+++ b/net/core/net-sysfs.c -@@ -780,7 +780,7 @@ net_rx_queue_update_kobjects(struct net_device *net, int old_num, int new_num) +Index: linux-3.2.46/net/core/net-sysfs.c +=================================================================== +--- linux-3.2.46.orig/net/core/net-sysfs.c 2013-07-26 18:54:22.000000000 +0000 ++++ linux-3.2.46/net/core/net-sysfs.c 2013-07-26 19:24:10.000000000 +0000 +@@ -783,7 +783,7 @@ #endif } @@ -78,7 +78,7 @@ /* * netdev_queue sysfs structures and functions. */ -@@ -826,6 +826,23 @@ static const struct sysfs_ops netdev_queue_sysfs_ops = { +@@ -829,6 +829,23 @@ .store = netdev_queue_attr_store, }; @@ -102,7 +102,7 @@ static inline unsigned int get_netdev_queue_index(struct netdev_queue *queue) { struct net_device *dev = queue->dev; -@@ -1020,12 +1037,17 @@ error: +@@ -1023,12 +1040,17 @@ static struct netdev_queue_attribute xps_cpus_attribute = __ATTR(xps_cpus, S_IRUGO | S_IWUSR, show_xps_map, store_xps_map); @@ -120,7 +120,7 @@ static void netdev_queue_release(struct kobject *kobj) { struct netdev_queue *queue = to_netdev_queue(kobj); -@@ -1076,10 +1098,13 @@ static void netdev_queue_release(struct kobject *kobj) +@@ -1079,10 +1101,13 @@ memset(kobj, 0, sizeof(*kobj)); dev_put(queue->dev); } @@ -134,7 +134,7 @@ .default_attrs = netdev_queue_default_attrs, }; -@@ -1102,12 +1127,12 @@ static int netdev_queue_add_kobject(struct net_device *net, int index) +@@ -1105,12 +1130,12 @@ return error; } @@ -149,7 +149,7 @@ int i; int error = 0; -@@ -1125,14 +1150,14 @@ netdev_queue_update_kobjects(struct net_device *net, int old_num, int new_num) +@@ -1128,14 +1153,14 @@ return error; #else return 0; @@ -166,7 +166,7 @@ net->queues_kset = kset_create_and_add("queues", NULL, &net->dev.kobj); if (!net->queues_kset) -@@ -1173,7 +1198,7 @@ static void remove_queue_kobjects(struct net_device *net) +@@ -1176,7 +1201,7 @@ net_rx_queue_update_kobjects(net, real_rx, 0); netdev_queue_update_kobjects(net, real_tx, 0); @@ -175,11 +175,11 @@ kset_unregister(net->queues_kset); #endif } -diff --git a/net/sched/sch_generic.c b/net/sched/sch_generic.c -index 69fca27..79ac145 100644 ---- a/net/sched/sch_generic.c -+++ b/net/sched/sch_generic.c -@@ -246,6 +246,7 @@ static void dev_watchdog(unsigned long arg) +Index: linux-3.2.46/net/sched/sch_generic.c +=================================================================== +--- linux-3.2.46.orig/net/sched/sch_generic.c 2013-07-26 18:54:22.000000000 +0000 ++++ linux-3.2.46/net/sched/sch_generic.c 2013-07-26 19:24:10.000000000 +0000 +@@ -246,6 +246,7 @@ time_after(jiffies, (trans_start + dev->watchdog_timeo))) { some_queue_timedout = 1; diff -Nru linux-3.2.46/debian/patches/features/all/bql/sfc-fix-race-in-efx_enqueue_skb_tso.patch linux-3.2.46/debian/patches/features/all/bql/sfc-fix-race-in-efx_enqueue_skb_tso.patch --- linux-3.2.46/debian/patches/features/all/bql/sfc-fix-race-in-efx_enqueue_skb_tso.patch 2013-02-24 03:52:36.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/bql/sfc-fix-race-in-efx_enqueue_skb_tso.patch 2013-07-26 19:24:42.000000000 +0000 @@ -13,11 +13,11 @@ drivers/net/ethernet/sfc/tx.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -diff --git a/drivers/net/ethernet/sfc/tx.c b/drivers/net/ethernet/sfc/tx.c -index ab4c635..e0e00b3 100644 ---- a/drivers/net/ethernet/sfc/tx.c -+++ b/drivers/net/ethernet/sfc/tx.c -@@ -1173,11 +1173,11 @@ static int efx_enqueue_skb_tso(struct efx_tx_queue *tx_queue, +Index: linux-3.2.46/drivers/net/ethernet/sfc/tx.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/sfc/tx.c 2013-07-26 19:24:39.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/sfc/tx.c 2013-07-26 19:24:41.000000000 +0000 +@@ -1192,11 +1192,11 @@ goto mem_err; } diff -Nru linux-3.2.46/debian/patches/features/all/bql/sfc-support-for-byte-queue-limits.patch linux-3.2.46/debian/patches/features/all/bql/sfc-support-for-byte-queue-limits.patch --- linux-3.2.46/debian/patches/features/all/bql/sfc-support-for-byte-queue-limits.patch 2013-02-24 03:52:36.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/bql/sfc-support-for-byte-queue-limits.patch 2013-07-26 19:24:40.000000000 +0000 @@ -13,10 +13,10 @@ drivers/net/ethernet/sfc/tx.c | 27 +++++++++++++++++++++------ 1 file changed, 21 insertions(+), 6 deletions(-) -diff --git a/drivers/net/ethernet/sfc/tx.c b/drivers/net/ethernet/sfc/tx.c -index df88c543..ab4c635 100644 ---- a/drivers/net/ethernet/sfc/tx.c -+++ b/drivers/net/ethernet/sfc/tx.c +Index: linux-3.2.46/drivers/net/ethernet/sfc/tx.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/sfc/tx.c 2013-07-26 18:54:13.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/sfc/tx.c 2013-07-26 19:24:39.000000000 +0000 @@ -31,7 +31,9 @@ #define EFX_TXQ_THRESHOLD(_efx) ((_efx)->txq_entries / 2u) @@ -28,7 +28,7 @@ { if (buffer->unmap_len) { struct pci_dev *pci_dev = tx_queue->efx->pci_dev; -@@ -48,6 +50,8 @@ static void efx_dequeue_buffer(struct efx_tx_queue *tx_queue, +@@ -48,6 +50,8 @@ } if (buffer->skb) { @@ -37,7 +37,7 @@ dev_kfree_skb_any((struct sk_buff *) buffer->skb); buffer->skb = NULL; netif_vdbg(tx_queue->efx, tx_done, tx_queue->efx->net_dev, -@@ -250,6 +254,8 @@ netdev_tx_t efx_enqueue_skb(struct efx_tx_queue *tx_queue, struct sk_buff *skb) +@@ -269,6 +273,8 @@ buffer->skb = skb; buffer->continuation = false; @@ -46,7 +46,7 @@ /* Pass off to hardware */ efx_nic_push_buffers(tx_queue); -@@ -267,10 +273,11 @@ netdev_tx_t efx_enqueue_skb(struct efx_tx_queue *tx_queue, struct sk_buff *skb) +@@ -286,10 +292,11 @@ unwind: /* Work backwards until we hit the original insert pointer value */ while (tx_queue->insert_count != tx_queue->write_count) { @@ -59,7 +59,7 @@ buffer->len = 0; } -@@ -293,7 +300,9 @@ netdev_tx_t efx_enqueue_skb(struct efx_tx_queue *tx_queue, struct sk_buff *skb) +@@ -312,7 +319,9 @@ * specified index. */ static void efx_dequeue_buffers(struct efx_tx_queue *tx_queue, @@ -70,7 +70,7 @@ { struct efx_nic *efx = tx_queue->efx; unsigned int stop_index, read_ptr; -@@ -311,7 +320,7 @@ static void efx_dequeue_buffers(struct efx_tx_queue *tx_queue, +@@ -330,7 +339,7 @@ return; } @@ -79,7 +79,7 @@ buffer->continuation = true; buffer->len = 0; -@@ -422,10 +431,12 @@ void efx_xmit_done(struct efx_tx_queue *tx_queue, unsigned int index) +@@ -441,10 +450,12 @@ { unsigned fill_level; struct efx_nic *efx = tx_queue->efx; @@ -93,7 +93,7 @@ /* See if we need to restart the netif queue. This barrier * separates the update of read_count from the test of the -@@ -515,13 +526,15 @@ void efx_release_tx_buffers(struct efx_tx_queue *tx_queue) +@@ -534,13 +545,15 @@ /* Free any buffers left in the ring */ while (tx_queue->read_count != tx_queue->write_count) { @@ -110,7 +110,7 @@ } void efx_fini_tx_queue(struct efx_tx_queue *tx_queue) -@@ -1163,6 +1176,8 @@ static int efx_enqueue_skb_tso(struct efx_tx_queue *tx_queue, +@@ -1182,6 +1195,8 @@ /* Pass off to hardware */ efx_nic_push_buffers(tx_queue); diff -Nru linux-3.2.46/debian/patches/features/all/bql/skge-add-byte-queue-limit-support.patch linux-3.2.46/debian/patches/features/all/bql/skge-add-byte-queue-limit-support.patch --- linux-3.2.46/debian/patches/features/all/bql/skge-add-byte-queue-limit-support.patch 2013-02-24 03:52:36.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/bql/skge-add-byte-queue-limit-support.patch 2013-07-26 19:24:52.000000000 +0000 @@ -14,11 +14,11 @@ drivers/net/ethernet/marvell/skge.c | 37 +++++++++++++++++++++++------------ 1 file changed, 24 insertions(+), 13 deletions(-) -diff --git a/drivers/net/ethernet/marvell/skge.c b/drivers/net/ethernet/marvell/skge.c -index 299c33b..edb9bda 100644 ---- a/drivers/net/ethernet/marvell/skge.c -+++ b/drivers/net/ethernet/marvell/skge.c -@@ -2817,6 +2817,8 @@ static netdev_tx_t skge_xmit_frame(struct sk_buff *skb, +Index: linux-3.2.46/drivers/net/ethernet/marvell/skge.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/marvell/skge.c 2013-07-26 18:54:07.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/marvell/skge.c 2013-07-26 19:24:52.000000000 +0000 +@@ -2797,6 +2797,8 @@ td->control = BMU_OWN | BMU_SW | BMU_STF | control | len; wmb(); @@ -27,7 +27,7 @@ skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_START); netif_printk(skge, tx_queued, KERN_DEBUG, skge->netdev, -@@ -2858,11 +2860,9 @@ mapping_error: +@@ -2816,11 +2818,9 @@ /* Free resources associated with this reing element */ @@ -41,7 +41,7 @@ /* skb header vs. fragment */ if (control & BMU_STF) pci_unmap_single(pdev, dma_unmap_addr(e, mapaddr), -@@ -2872,13 +2872,6 @@ static void skge_tx_free(struct skge_port *skge, struct skge_element *e, +@@ -2830,13 +2830,6 @@ pci_unmap_page(pdev, dma_unmap_addr(e, mapaddr), dma_unmap_len(e, maplen), PCI_DMA_TODEVICE); @@ -55,7 +55,7 @@ } /* Free all buffers in transmit ring */ -@@ -2889,10 +2882,15 @@ static void skge_tx_clean(struct net_device *dev) +@@ -2847,10 +2840,15 @@ for (e = skge->tx_ring.to_clean; e != skge->tx_ring.to_use; e = e->next) { struct skge_tx_desc *td = e->desc; @@ -72,7 +72,7 @@ skge->tx_ring.to_clean = e; } -@@ -3157,6 +3155,7 @@ static void skge_tx_done(struct net_device *dev) +@@ -3111,6 +3109,7 @@ struct skge_port *skge = netdev_priv(dev); struct skge_ring *ring = &skge->tx_ring; struct skge_element *e; @@ -80,7 +80,7 @@ skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F); -@@ -3166,8 +3165,20 @@ static void skge_tx_done(struct net_device *dev) +@@ -3120,8 +3119,20 @@ if (control & BMU_OWN) break; diff -Nru linux-3.2.46/debian/patches/features/all/bql/sky2-add-bql-support.patch linux-3.2.46/debian/patches/features/all/bql/sky2-add-bql-support.patch --- linux-3.2.46/debian/patches/features/all/bql/sky2-add-bql-support.patch 2013-02-24 03:52:36.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/bql/sky2-add-bql-support.patch 2013-07-26 19:24:43.000000000 +0000 @@ -13,11 +13,11 @@ drivers/net/ethernet/marvell/sky2.c | 18 +++++++++++++----- 1 file changed, 13 insertions(+), 5 deletions(-) -diff --git a/drivers/net/ethernet/marvell/sky2.c b/drivers/net/ethernet/marvell/sky2.c -index 29adc78..760c2b1 100644 ---- a/drivers/net/ethernet/marvell/sky2.c -+++ b/drivers/net/ethernet/marvell/sky2.c -@@ -1110,6 +1110,7 @@ static void tx_init(struct sky2_port *sky2) +Index: linux-3.2.46/drivers/net/ethernet/marvell/sky2.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/marvell/sky2.c 2013-07-26 18:54:12.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/marvell/sky2.c 2013-07-26 19:24:42.000000000 +0000 +@@ -1121,6 +1121,7 @@ sky2->tx_prod = sky2->tx_cons = 0; sky2->tx_tcpsum = 0; sky2->tx_last_mss = 0; @@ -25,7 +25,7 @@ le = get_tx_le(sky2, &sky2->tx_prod); le->addr = 0; -@@ -1971,6 +1972,7 @@ static netdev_tx_t sky2_xmit_frame(struct sk_buff *skb, +@@ -1983,6 +1984,7 @@ if (tx_avail(sky2) <= MAX_SKB_TX_LE) netif_stop_queue(dev); @@ -33,7 +33,7 @@ sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod); return NETDEV_TX_OK; -@@ -2002,7 +2004,8 @@ mapping_error: +@@ -2014,7 +2016,8 @@ static void sky2_tx_complete(struct sky2_port *sky2, u16 done) { struct net_device *dev = sky2->netdev; @@ -43,7 +43,7 @@ BUG_ON(done >= sky2->tx_ring_size); -@@ -2017,10 +2020,8 @@ static void sky2_tx_complete(struct sky2_port *sky2, u16 done) +@@ -2029,10 +2032,8 @@ netif_printk(sky2, tx_done, KERN_DEBUG, dev, "tx done %u\n", idx); @@ -56,7 +56,7 @@ re->skb = NULL; dev_kfree_skb_any(skb); -@@ -2031,6 +2032,13 @@ static void sky2_tx_complete(struct sky2_port *sky2, u16 done) +@@ -2043,6 +2044,13 @@ sky2->tx_cons = idx; smp_mb(); diff -Nru linux-3.2.46/debian/patches/features/all/bql/tg3-fix-to-use-multi-queue-bql-interfaces.patch linux-3.2.46/debian/patches/features/all/bql/tg3-fix-to-use-multi-queue-bql-interfaces.patch --- linux-3.2.46/debian/patches/features/all/bql/tg3-fix-to-use-multi-queue-bql-interfaces.patch 2013-02-24 03:52:36.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/bql/tg3-fix-to-use-multi-queue-bql-interfaces.patch 2013-07-26 19:24:35.000000000 +0000 @@ -15,11 +15,11 @@ drivers/net/ethernet/broadcom/tg3.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) -diff --git a/drivers/net/ethernet/broadcom/tg3.c b/drivers/net/ethernet/broadcom/tg3.c -index 423d023..35c2a20 100644 ---- a/drivers/net/ethernet/broadcom/tg3.c -+++ b/drivers/net/ethernet/broadcom/tg3.c -@@ -5352,7 +5352,7 @@ static void tg3_tx(struct tg3_napi *tnapi) +Index: linux-3.2.46/drivers/net/ethernet/broadcom/tg3.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/broadcom/tg3.c 2013-07-26 19:24:33.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/broadcom/tg3.c 2013-07-26 19:24:34.000000000 +0000 +@@ -5421,7 +5421,7 @@ } } @@ -28,7 +28,7 @@ tnapi->tx_cons = sw_idx; -@@ -6793,7 +6793,7 @@ static netdev_tx_t tg3_start_xmit(struct sk_buff *skb, struct net_device *dev) +@@ -6867,7 +6867,7 @@ } skb_tx_timestamp(skb); @@ -37,7 +37,7 @@ /* Packets are ready, update Tx producer idx local and on card. */ tw32_tx_mbox(tnapi->prodmbox, entry); -@@ -7275,8 +7275,8 @@ static void tg3_free_rings(struct tg3 *tp) +@@ -7348,8 +7348,8 @@ dev_kfree_skb_any(skb); } diff -Nru linux-3.2.46/debian/patches/features/all/bql/tg3-support-for-byte-queue-limits.patch linux-3.2.46/debian/patches/features/all/bql/tg3-support-for-byte-queue-limits.patch --- linux-3.2.46/debian/patches/features/all/bql/tg3-support-for-byte-queue-limits.patch 2013-02-24 03:52:36.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/bql/tg3-support-for-byte-queue-limits.patch 2013-07-26 19:24:34.000000000 +0000 @@ -13,11 +13,11 @@ drivers/net/ethernet/broadcom/tg3.c | 8 ++++++++ 1 file changed, 8 insertions(+) -diff --git a/drivers/net/ethernet/broadcom/tg3.c b/drivers/net/ethernet/broadcom/tg3.c -index aa413d6..cf36312 100644 ---- a/drivers/net/ethernet/broadcom/tg3.c -+++ b/drivers/net/ethernet/broadcom/tg3.c -@@ -5302,6 +5302,7 @@ static void tg3_tx(struct tg3_napi *tnapi) +Index: linux-3.2.46/drivers/net/ethernet/broadcom/tg3.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/ethernet/broadcom/tg3.c 2013-07-26 18:54:15.000000000 +0000 ++++ linux-3.2.46/drivers/net/ethernet/broadcom/tg3.c 2013-07-26 19:24:33.000000000 +0000 +@@ -5359,6 +5359,7 @@ u32 sw_idx = tnapi->tx_cons; struct netdev_queue *txq; int index = tnapi - tp->napi; @@ -25,7 +25,7 @@ if (tg3_flag(tp, ENABLE_TSS)) index--; -@@ -5352,6 +5353,9 @@ static void tg3_tx(struct tg3_napi *tnapi) +@@ -5409,6 +5410,9 @@ sw_idx = NEXT_TX(sw_idx); } @@ -35,7 +35,7 @@ dev_kfree_skb(skb); if (unlikely(tx_bug)) { -@@ -5360,6 +5364,8 @@ static void tg3_tx(struct tg3_napi *tnapi) +@@ -5417,6 +5421,8 @@ } } @@ -44,7 +44,7 @@ tnapi->tx_cons = sw_idx; /* Need to make the tx_cons update visible to tg3_start_xmit() -@@ -6804,6 +6810,7 @@ static netdev_tx_t tg3_start_xmit(struct sk_buff *skb, struct net_device *dev) +@@ -6861,6 +6867,7 @@ } skb_tx_timestamp(skb); @@ -52,7 +52,7 @@ /* Packets are ready, update Tx producer idx local and on card. */ tw32_tx_mbox(tnapi->prodmbox, entry); -@@ -7286,6 +7293,7 @@ static void tg3_free_rings(struct tg3 *tp) +@@ -7342,6 +7349,7 @@ dev_kfree_skb_any(skb); } } diff -Nru linux-3.2.46/debian/patches/features/all/bql/xps-add-xps_queue_release-function.patch linux-3.2.46/debian/patches/features/all/bql/xps-add-xps_queue_release-function.patch --- linux-3.2.46/debian/patches/features/all/bql/xps-add-xps_queue_release-function.patch 2013-02-24 03:52:36.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/bql/xps-add-xps_queue_release-function.patch 2013-07-26 19:24:17.000000000 +0000 @@ -16,11 +16,11 @@ net/core/net-sysfs.c | 89 ++++++++++++++++++++++++++------------------------ 1 file changed, 47 insertions(+), 42 deletions(-) -diff --git a/net/core/net-sysfs.c b/net/core/net-sysfs.c -index db6c2f8..b17c14a 100644 ---- a/net/core/net-sysfs.c -+++ b/net/core/net-sysfs.c -@@ -910,6 +910,52 @@ static DEFINE_MUTEX(xps_map_mutex); +Index: linux-3.2.46/net/core/net-sysfs.c +=================================================================== +--- linux-3.2.46.orig/net/core/net-sysfs.c 2013-07-26 19:24:10.000000000 +0000 ++++ linux-3.2.46/net/core/net-sysfs.c 2013-07-26 19:24:16.000000000 +0000 +@@ -910,6 +910,52 @@ #define xmap_dereference(P) \ rcu_dereference_protected((P), lockdep_is_held(&xps_map_mutex)) @@ -73,7 +73,7 @@ static ssize_t store_xps_map(struct netdev_queue *queue, struct netdev_queue_attribute *attribute, const char *buf, size_t len) -@@ -1054,49 +1100,8 @@ static struct attribute *netdev_queue_default_attrs[] = { +@@ -1054,49 +1100,8 @@ static void netdev_queue_release(struct kobject *kobj) { struct netdev_queue *queue = to_netdev_queue(kobj); diff -Nru linux-3.2.46/debian/patches/features/all/cgroups-Allow-memory-cgroup-support-to-be-included-b.patch linux-3.2.46/debian/patches/features/all/cgroups-Allow-memory-cgroup-support-to-be-included-b.patch --- linux-3.2.46/debian/patches/features/all/cgroups-Allow-memory-cgroup-support-to-be-included-b.patch 2013-02-24 03:52:42.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/cgroups-Allow-memory-cgroup-support-to-be-included-b.patch 2013-07-26 19:17:24.000000000 +0000 @@ -16,11 +16,11 @@ mm/memcontrol.c | 3 +++ 4 files changed, 29 insertions(+), 6 deletions(-) -diff --git a/Documentation/kernel-parameters.txt b/Documentation/kernel-parameters.txt -index cc85a92..38e0b44 100644 ---- a/Documentation/kernel-parameters.txt -+++ b/Documentation/kernel-parameters.txt -@@ -425,8 +425,8 @@ bytes respectively. Such letter suffixes can also be entirely omitted. +Index: linux-3.2.46/Documentation/kernel-parameters.txt +=================================================================== +--- linux-3.2.46.orig/Documentation/kernel-parameters.txt 2013-07-26 18:56:33.000000000 +0000 ++++ linux-3.2.46/Documentation/kernel-parameters.txt 2013-07-26 19:17:23.000000000 +0000 +@@ -446,8 +446,8 @@ ccw_timeout_log [S390] See Documentation/s390/CommonIO for details. @@ -31,11 +31,11 @@ {Currently supported controllers - "memory"} checkreqprot [SELINUX] Set initial checkreqprot flag value. -diff --git a/init/Kconfig b/init/Kconfig -index d886b1e..3410369 100644 ---- a/init/Kconfig -+++ b/init/Kconfig -@@ -659,6 +659,14 @@ config CGROUP_MEM_RES_CTLR +Index: linux-3.2.46/init/Kconfig +=================================================================== +--- linux-3.2.46.orig/init/Kconfig 2013-07-26 18:56:33.000000000 +0000 ++++ linux-3.2.46/init/Kconfig 2013-07-26 19:17:23.000000000 +0000 +@@ -659,6 +659,14 @@ This config option also selects MM_OWNER config option, which could in turn add some fork/exit overhead. @@ -50,11 +50,11 @@ config CGROUP_MEM_RES_CTLR_SWAP bool "Memory Resource Controller Swap Extension" depends on CGROUP_MEM_RES_CTLR && SWAP -diff --git a/kernel/cgroup.c b/kernel/cgroup.c -index 25c7eb5..b3c5aa7 100644 ---- a/kernel/cgroup.c -+++ b/kernel/cgroup.c -@@ -4526,7 +4526,7 @@ static void cgroup_release_agent(struct work_struct *work) +Index: linux-3.2.46/kernel/cgroup.c +=================================================================== +--- linux-3.2.46.orig/kernel/cgroup.c 2013-07-26 18:56:33.000000000 +0000 ++++ linux-3.2.46/kernel/cgroup.c 2013-07-26 19:17:23.000000000 +0000 +@@ -4769,7 +4769,7 @@ mutex_unlock(&cgroup_mutex); } @@ -63,7 +63,7 @@ { int i; char *token; -@@ -4542,17 +4542,29 @@ static int __init cgroup_disable(char *str) +@@ -4785,17 +4785,29 @@ struct cgroup_subsys *ss = subsys[i]; if (!strcmp(token, ss->name)) { @@ -96,11 +96,11 @@ /* * Functons for CSS ID. */ -diff --git a/mm/memcontrol.c b/mm/memcontrol.c -index 010f916..f660a07 100644 ---- a/mm/memcontrol.c -+++ b/mm/memcontrol.c -@@ -5153,6 +5153,9 @@ static void mem_cgroup_move_task(struct cgroup_subsys *ss, +Index: linux-3.2.46/mm/memcontrol.c +=================================================================== +--- linux-3.2.46.orig/mm/memcontrol.c 2013-07-26 18:56:33.000000000 +0000 ++++ linux-3.2.46/mm/memcontrol.c 2013-07-26 19:17:23.000000000 +0000 +@@ -5555,6 +5555,9 @@ struct cgroup_subsys mem_cgroup_subsys = { .name = "memory", @@ -110,6 +110,3 @@ .subsys_id = mem_cgroup_subsys_id, .create = mem_cgroup_create, .pre_destroy = mem_cgroup_pre_destroy, --- -1.7.4.4 - diff -Nru linux-3.2.46/debian/patches/features/all/codel/0001-codel-Controlled-Delay-AQM.patch linux-3.2.46/debian/patches/features/all/codel/0001-codel-Controlled-Delay-AQM.patch --- linux-3.2.46/debian/patches/features/all/codel/0001-codel-Controlled-Delay-AQM.patch 2013-02-24 03:52:32.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/codel/0001-codel-Controlled-Delay-AQM.patch 2013-07-26 19:22:32.000000000 +0000 @@ -78,11 +78,11 @@ create mode 100644 include/net/codel.h create mode 100644 net/sched/sch_codel.c -diff --git a/include/linux/pkt_sched.h b/include/linux/pkt_sched.h -index ffe975c..cde56c2 100644 ---- a/include/linux/pkt_sched.h -+++ b/include/linux/pkt_sched.h -@@ -655,4 +655,30 @@ struct tc_qfq_stats { +Index: linux-3.2.46/include/linux/pkt_sched.h +=================================================================== +--- linux-3.2.46.orig/include/linux/pkt_sched.h 2013-07-26 18:54:54.000000000 +0000 ++++ linux-3.2.46/include/linux/pkt_sched.h 2013-07-26 19:22:31.000000000 +0000 +@@ -603,4 +603,30 @@ __u32 lmax; }; @@ -113,11 +113,10 @@ +}; + #endif -diff --git a/include/net/codel.h b/include/net/codel.h -new file mode 100644 -index 0000000..bce2cef ---- /dev/null -+++ b/include/net/codel.h +Index: linux-3.2.46/include/net/codel.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/include/net/codel.h 2013-07-26 19:22:31.000000000 +0000 @@ -0,0 +1,332 @@ +#ifndef __NET_SCHED_CODEL_H +#define __NET_SCHED_CODEL_H @@ -451,11 +450,11 @@ + return skb; +} +#endif -diff --git a/net/sched/Kconfig b/net/sched/Kconfig -index 75b58f8..fadd252 100644 ---- a/net/sched/Kconfig -+++ b/net/sched/Kconfig -@@ -250,6 +250,17 @@ config NET_SCH_QFQ +Index: linux-3.2.46/net/sched/Kconfig +=================================================================== +--- linux-3.2.46.orig/net/sched/Kconfig 2013-07-26 18:54:54.000000000 +0000 ++++ linux-3.2.46/net/sched/Kconfig 2013-07-26 19:22:31.000000000 +0000 +@@ -250,6 +250,17 @@ If unsure, say N. @@ -473,11 +472,11 @@ config NET_SCH_INGRESS tristate "Ingress Qdisc" depends on NET_CLS_ACT -diff --git a/net/sched/Makefile b/net/sched/Makefile -index 8cdf4e2..30fab03 100644 ---- a/net/sched/Makefile -+++ b/net/sched/Makefile -@@ -37,6 +37,7 @@ obj-$(CONFIG_NET_SCH_PLUG) += sch_plug.o +Index: linux-3.2.46/net/sched/Makefile +=================================================================== +--- linux-3.2.46.orig/net/sched/Makefile 2013-07-26 18:54:54.000000000 +0000 ++++ linux-3.2.46/net/sched/Makefile 2013-07-26 19:22:31.000000000 +0000 +@@ -36,6 +36,7 @@ obj-$(CONFIG_NET_SCH_MQPRIO) += sch_mqprio.o obj-$(CONFIG_NET_SCH_CHOKE) += sch_choke.o obj-$(CONFIG_NET_SCH_QFQ) += sch_qfq.o @@ -485,11 +484,10 @@ obj-$(CONFIG_NET_CLS_U32) += cls_u32.o obj-$(CONFIG_NET_CLS_ROUTE4) += cls_route.o -diff --git a/net/sched/sch_codel.c b/net/sched/sch_codel.c -new file mode 100644 -index 0000000..b4a1a81 ---- /dev/null -+++ b/net/sched/sch_codel.c +Index: linux-3.2.46/net/sched/sch_codel.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/net/sched/sch_codel.c 2013-07-26 19:22:31.000000000 +0000 @@ -0,0 +1,275 @@ +/* + * Codel - The Controlled-Delay Active Queue Management algorithm @@ -766,6 +764,3 @@ +MODULE_AUTHOR("Dave Taht"); +MODULE_AUTHOR("Eric Dumazet"); +MODULE_LICENSE("Dual BSD/GPL"); --- -1.7.10 - diff -Nru linux-3.2.46/debian/patches/features/all/codel/0002-codel-use-Newton-method-instead-of-sqrt-and-divides.patch linux-3.2.46/debian/patches/features/all/codel/0002-codel-use-Newton-method-instead-of-sqrt-and-divides.patch --- linux-3.2.46/debian/patches/features/all/codel/0002-codel-use-Newton-method-instead-of-sqrt-and-divides.patch 2013-02-24 03:52:32.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/codel/0002-codel-use-Newton-method-instead-of-sqrt-and-divides.patch 2013-07-26 19:22:34.000000000 +0000 @@ -34,10 +34,10 @@ include/net/codel.h | 68 ++++++++++++++++++++++++++++----------------------- 1 file changed, 37 insertions(+), 31 deletions(-) -diff --git a/include/net/codel.h b/include/net/codel.h -index bce2cef..bd8747c 100644 ---- a/include/net/codel.h -+++ b/include/net/codel.h +Index: linux-3.2.46/include/net/codel.h +=================================================================== +--- linux-3.2.46.orig/include/net/codel.h 2013-07-26 19:22:31.000000000 +0000 ++++ linux-3.2.46/include/net/codel.h 2013-07-26 19:22:33.000000000 +0000 @@ -46,6 +46,7 @@ #include #include @@ -46,7 +46,7 @@ /* Controlling Queue Delay (CoDel) algorithm * ========================================= -@@ -123,6 +124,7 @@ struct codel_params { +@@ -123,6 +124,7 @@ * entered dropping state * @lastcount: count at entry to dropping state * @dropping: set to true if in dropping state @@ -54,7 +54,7 @@ * @first_above_time: when we went (or will go) continuously above target * for interval * @drop_next: time to drop next packet, or when we dropped last -@@ -131,7 +133,8 @@ struct codel_params { +@@ -131,7 +133,8 @@ struct codel_vars { u32 count; u32 lastcount; @@ -64,7 +64,7 @@ codel_time_t first_above_time; codel_time_t drop_next; codel_time_t ldelay; -@@ -158,11 +161,7 @@ static void codel_params_init(struct codel_params *params) +@@ -158,11 +161,7 @@ static void codel_vars_init(struct codel_vars *vars) { @@ -77,7 +77,7 @@ } static void codel_stats_init(struct codel_stats *stats) -@@ -170,38 +169,37 @@ static void codel_stats_init(struct codel_stats *stats) +@@ -170,38 +169,37 @@ stats->maxpacket = 256; } @@ -94,12 +94,12 @@ { - u64 interval = _interval; - unsigned long x = _x; +- +- /* Scale operands for max precision */ + u32 invsqrt = vars->rec_inv_sqrt; + u32 invsqrt2 = ((u64)invsqrt * invsqrt) >> 31; + u64 val = (3LL << 31) - ((u64)vars->count * invsqrt2); -- /* Scale operands for max precision */ -- -#if BITS_PER_LONG == 64 - x <<= 32; /* On 64bit arches, we can prescale x by 32bits */ - interval <<= 16; @@ -135,7 +135,7 @@ unsigned int *backlog, struct codel_vars *vars, struct codel_params *params, -@@ -274,14 +272,16 @@ static struct sk_buff *codel_dequeue(struct Qdisc *sch, +@@ -274,14 +272,16 @@ */ while (vars->dropping && codel_time_after_eq(now, vars->drop_next)) { @@ -155,7 +155,7 @@ goto end; } qdisc_drop(skb, sch); -@@ -296,7 +296,7 @@ static struct sk_buff *codel_dequeue(struct Qdisc *sch, +@@ -296,7 +296,7 @@ vars->drop_next = codel_control_law(vars->drop_next, params->interval, @@ -164,7 +164,7 @@ } } } -@@ -319,12 +319,18 @@ static struct sk_buff *codel_dequeue(struct Qdisc *sch, +@@ -319,12 +319,18 @@ if (codel_time_before(now - vars->drop_next, 16 * params->interval)) { vars->count = (vars->count - vars->lastcount) | 1; @@ -184,6 +184,3 @@ } end: return skb; --- -1.7.10 - diff -Nru linux-3.2.46/debian/patches/features/all/codel/0003-fq_codel-Fair-Queue-Codel-AQM.patch linux-3.2.46/debian/patches/features/all/codel/0003-fq_codel-Fair-Queue-Codel-AQM.patch --- linux-3.2.46/debian/patches/features/all/codel/0003-fq_codel-Fair-Queue-Codel-AQM.patch 2013-02-24 03:52:32.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/codel/0003-fq_codel-Fair-Queue-Codel-AQM.patch 2013-07-26 19:22:35.000000000 +0000 @@ -118,11 +118,11 @@ 4 files changed, 690 insertions(+) create mode 100644 net/sched/sch_fq_codel.c -diff --git a/include/linux/pkt_sched.h b/include/linux/pkt_sched.h -index cde56c2..32aef0a 100644 ---- a/include/linux/pkt_sched.h -+++ b/include/linux/pkt_sched.h -@@ -681,4 +681,58 @@ struct tc_codel_xstats { +Index: linux-3.2.46/include/linux/pkt_sched.h +=================================================================== +--- linux-3.2.46.orig/include/linux/pkt_sched.h 2013-07-26 19:22:31.000000000 +0000 ++++ linux-3.2.46/include/linux/pkt_sched.h 2013-07-26 19:22:34.000000000 +0000 +@@ -629,4 +629,58 @@ __u32 dropping; /* are we in dropping state ? */ }; @@ -181,11 +181,11 @@ +}; + #endif -diff --git a/net/sched/Kconfig b/net/sched/Kconfig -index fadd252..e7a8976 100644 ---- a/net/sched/Kconfig -+++ b/net/sched/Kconfig -@@ -261,6 +261,17 @@ config NET_SCH_CODEL +Index: linux-3.2.46/net/sched/Kconfig +=================================================================== +--- linux-3.2.46.orig/net/sched/Kconfig 2013-07-26 19:22:31.000000000 +0000 ++++ linux-3.2.46/net/sched/Kconfig 2013-07-26 19:22:34.000000000 +0000 +@@ -261,6 +261,17 @@ If unsure, say N. @@ -203,11 +203,11 @@ config NET_SCH_INGRESS tristate "Ingress Qdisc" depends on NET_CLS_ACT -diff --git a/net/sched/Makefile b/net/sched/Makefile -index 30fab03..5940a19 100644 ---- a/net/sched/Makefile -+++ b/net/sched/Makefile -@@ -38,6 +38,7 @@ obj-$(CONFIG_NET_SCH_MQPRIO) += sch_mqprio.o +Index: linux-3.2.46/net/sched/Makefile +=================================================================== +--- linux-3.2.46.orig/net/sched/Makefile 2013-07-26 19:22:31.000000000 +0000 ++++ linux-3.2.46/net/sched/Makefile 2013-07-26 19:22:34.000000000 +0000 +@@ -37,6 +37,7 @@ obj-$(CONFIG_NET_SCH_CHOKE) += sch_choke.o obj-$(CONFIG_NET_SCH_QFQ) += sch_qfq.o obj-$(CONFIG_NET_SCH_CODEL) += sch_codel.o @@ -215,11 +215,10 @@ obj-$(CONFIG_NET_CLS_U32) += cls_u32.o obj-$(CONFIG_NET_CLS_ROUTE4) += cls_route.o -diff --git a/net/sched/sch_fq_codel.c b/net/sched/sch_fq_codel.c -new file mode 100644 -index 0000000..a7b3754 ---- /dev/null -+++ b/net/sched/sch_fq_codel.c +Index: linux-3.2.46/net/sched/sch_fq_codel.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/net/sched/sch_fq_codel.c 2013-07-26 19:22:34.000000000 +0000 @@ -0,0 +1,624 @@ +/* + * Fair Queue CoDel discipline @@ -845,6 +844,3 @@ +module_exit(fq_codel_module_exit) +MODULE_AUTHOR("Eric Dumazet"); +MODULE_LICENSE("GPL"); --- -1.7.10 - diff -Nru linux-3.2.46/debian/patches/features/all/codel/0004-net-codel-Add-missing-include-linux-prefetch.h.patch linux-3.2.46/debian/patches/features/all/codel/0004-net-codel-Add-missing-include-linux-prefetch.h.patch --- linux-3.2.46/debian/patches/features/all/codel/0004-net-codel-Add-missing-include-linux-prefetch.h.patch 2013-02-24 03:52:32.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/codel/0004-net-codel-Add-missing-include-linux-prefetch.h.patch 2013-07-26 19:22:37.000000000 +0000 @@ -20,10 +20,10 @@ net/sched/sch_codel.c | 1 + 1 file changed, 1 insertion(+) -diff --git a/net/sched/sch_codel.c b/net/sched/sch_codel.c -index b4a1a81..213ef60 100644 ---- a/net/sched/sch_codel.c -+++ b/net/sched/sch_codel.c +Index: linux-3.2.46/net/sched/sch_codel.c +=================================================================== +--- linux-3.2.46.orig/net/sched/sch_codel.c 2013-07-26 19:22:31.000000000 +0000 ++++ linux-3.2.46/net/sched/sch_codel.c 2013-07-26 19:22:36.000000000 +0000 @@ -46,6 +46,7 @@ #include #include @@ -32,6 +32,3 @@ #include #include --- -1.7.10 - diff -Nru linux-3.2.46/debian/patches/features/all/codel/0005-net-codel-fix-build-errors.patch linux-3.2.46/debian/patches/features/all/codel/0005-net-codel-fix-build-errors.patch --- linux-3.2.46/debian/patches/features/all/codel/0005-net-codel-fix-build-errors.patch 2013-02-24 03:52:32.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/codel/0005-net-codel-fix-build-errors.patch 2013-07-26 19:22:38.000000000 +0000 @@ -27,11 +27,11 @@ net/sched/sch_fq_codel.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) -diff --git a/net/sched/sch_fq_codel.c b/net/sched/sch_fq_codel.c -index a7b3754..337ff20 100644 ---- a/net/sched/sch_fq_codel.c -+++ b/net/sched/sch_fq_codel.c -@@ -461,13 +461,14 @@ static int fq_codel_dump_stats(struct Qdisc *sch, struct gnet_dump *d) +Index: linux-3.2.46/net/sched/sch_fq_codel.c +=================================================================== +--- linux-3.2.46.orig/net/sched/sch_fq_codel.c 2013-07-26 19:22:34.000000000 +0000 ++++ linux-3.2.46/net/sched/sch_fq_codel.c 2013-07-26 19:22:37.000000000 +0000 +@@ -461,13 +461,14 @@ struct fq_codel_sched_data *q = qdisc_priv(sch); struct tc_fq_codel_xstats st = { .type = TCA_FQ_CODEL_XSTATS_QDISC, @@ -50,6 +50,3 @@ list_for_each(pos, &q->new_flows) st.qdisc_stats.new_flows_len++; --- -1.7.10 - diff -Nru linux-3.2.46/debian/patches/features/all/codel/0006-codel-use-u16-field-instead-of-31bits-for-rec_inv_sq.patch linux-3.2.46/debian/patches/features/all/codel/0006-codel-use-u16-field-instead-of-31bits-for-rec_inv_sq.patch --- linux-3.2.46/debian/patches/features/all/codel/0006-codel-use-u16-field-instead-of-31bits-for-rec_inv_sq.patch 2013-02-24 03:52:32.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/codel/0006-codel-use-u16-field-instead-of-31bits-for-rec_inv_sq.patch 2013-07-26 19:22:39.000000000 +0000 @@ -18,11 +18,11 @@ include/net/codel.h | 25 +++++++++++++++---------- 1 file changed, 15 insertions(+), 10 deletions(-) -diff --git a/include/net/codel.h b/include/net/codel.h -index bd8747c..7546517 100644 ---- a/include/net/codel.h -+++ b/include/net/codel.h -@@ -133,13 +133,17 @@ struct codel_params { +Index: linux-3.2.46/include/net/codel.h +=================================================================== +--- linux-3.2.46.orig/include/net/codel.h 2013-07-26 19:22:33.000000000 +0000 ++++ linux-3.2.46/include/net/codel.h 2013-07-26 19:22:38.000000000 +0000 +@@ -133,13 +133,17 @@ struct codel_vars { u32 count; u32 lastcount; @@ -42,7 +42,7 @@ /** * struct codel_stats - contains codel shared variables and stats * @maxpacket: largest packet we've seen so far -@@ -173,17 +177,18 @@ static void codel_stats_init(struct codel_stats *stats) +@@ -173,17 +177,18 @@ * http://en.wikipedia.org/wiki/Methods_of_computing_square_roots#Iterative_methods_for_reciprocal_square_roots * new_invsqrt = (invsqrt / 2) * (3 - count * invsqrt^2) * @@ -67,7 +67,7 @@ } /* -@@ -195,7 +200,7 @@ static codel_time_t codel_control_law(codel_time_t t, +@@ -195,7 +200,7 @@ codel_time_t interval, u32 rec_inv_sqrt) { @@ -76,7 +76,7 @@ } -@@ -326,7 +331,7 @@ static struct sk_buff *codel_dequeue(struct Qdisc *sch, +@@ -326,7 +331,7 @@ codel_Newton_step(vars); } else { vars->count = 1; @@ -85,6 +85,3 @@ } vars->lastcount = vars->count; vars->drop_next = codel_control_law(now, params->interval, --- -1.7.10 - diff -Nru linux-3.2.46/debian/patches/features/all/codel/0007-fq_codel-should-use-qdisc-backlog-as-threshold.patch linux-3.2.46/debian/patches/features/all/codel/0007-fq_codel-should-use-qdisc-backlog-as-threshold.patch --- linux-3.2.46/debian/patches/features/all/codel/0007-fq_codel-should-use-qdisc-backlog-as-threshold.patch 2013-02-24 03:52:32.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/codel/0007-fq_codel-should-use-qdisc-backlog-as-threshold.patch 2013-07-26 19:22:40.000000000 +0000 @@ -25,11 +25,11 @@ net/sched/sch_fq_codel.c | 5 +++-- 3 files changed, 12 insertions(+), 12 deletions(-) -diff --git a/include/net/codel.h b/include/net/codel.h -index 7546517..550debf 100644 ---- a/include/net/codel.h -+++ b/include/net/codel.h -@@ -205,7 +205,7 @@ static codel_time_t codel_control_law(codel_time_t t, +Index: linux-3.2.46/include/net/codel.h +=================================================================== +--- linux-3.2.46.orig/include/net/codel.h 2013-07-26 19:22:38.000000000 +0000 ++++ linux-3.2.46/include/net/codel.h 2013-07-26 19:22:39.000000000 +0000 +@@ -205,7 +205,7 @@ static bool codel_should_drop(const struct sk_buff *skb, @@ -38,7 +38,7 @@ struct codel_vars *vars, struct codel_params *params, struct codel_stats *stats, -@@ -219,13 +219,13 @@ static bool codel_should_drop(const struct sk_buff *skb, +@@ -219,13 +219,13 @@ } vars->ldelay = now - codel_get_enqueue_time(skb); @@ -54,7 +54,7 @@ /* went below - stay below for at least interval */ vars->first_above_time = 0; return false; -@@ -249,8 +249,7 @@ static struct sk_buff *codel_dequeue(struct Qdisc *sch, +@@ -249,8 +249,7 @@ struct codel_params *params, struct codel_vars *vars, struct codel_stats *stats, @@ -64,7 +64,7 @@ { struct sk_buff *skb = dequeue_func(vars, sch); codel_time_t now; -@@ -261,7 +260,7 @@ static struct sk_buff *codel_dequeue(struct Qdisc *sch, +@@ -261,7 +260,7 @@ return skb; } now = codel_get_time(); @@ -73,7 +73,7 @@ if (vars->dropping) { if (!drop) { /* sojourn time below target - leave dropping state */ -@@ -292,7 +291,7 @@ static struct sk_buff *codel_dequeue(struct Qdisc *sch, +@@ -292,7 +291,7 @@ qdisc_drop(skb, sch); stats->drop_count++; skb = dequeue_func(vars, sch); @@ -82,7 +82,7 @@ vars, params, stats, now)) { /* leave dropping state */ vars->dropping = false; -@@ -313,7 +312,7 @@ static struct sk_buff *codel_dequeue(struct Qdisc *sch, +@@ -313,7 +312,7 @@ stats->drop_count++; skb = dequeue_func(vars, sch); @@ -91,11 +91,11 @@ stats, now); } vars->dropping = true; -diff --git a/net/sched/sch_codel.c b/net/sched/sch_codel.c -index 213ef60..2f9ab17 100644 ---- a/net/sched/sch_codel.c -+++ b/net/sched/sch_codel.c -@@ -77,8 +77,8 @@ static struct sk_buff *codel_qdisc_dequeue(struct Qdisc *sch) +Index: linux-3.2.46/net/sched/sch_codel.c +=================================================================== +--- linux-3.2.46.orig/net/sched/sch_codel.c 2013-07-26 19:22:36.000000000 +0000 ++++ linux-3.2.46/net/sched/sch_codel.c 2013-07-26 19:22:39.000000000 +0000 +@@ -77,8 +77,8 @@ struct codel_sched_data *q = qdisc_priv(sch); struct sk_buff *skb; @@ -106,11 +106,11 @@ /* We cant call qdisc_tree_decrease_qlen() if our qlen is 0, * or HTB crashes. Defer it for next round. */ -diff --git a/net/sched/sch_fq_codel.c b/net/sched/sch_fq_codel.c -index 337ff20..9fc1c62 100644 ---- a/net/sched/sch_fq_codel.c -+++ b/net/sched/sch_fq_codel.c -@@ -217,13 +217,14 @@ static int fq_codel_enqueue(struct sk_buff *skb, struct Qdisc *sch) +Index: linux-3.2.46/net/sched/sch_fq_codel.c +=================================================================== +--- linux-3.2.46.orig/net/sched/sch_fq_codel.c 2013-07-26 19:22:37.000000000 +0000 ++++ linux-3.2.46/net/sched/sch_fq_codel.c 2013-07-26 19:22:39.000000000 +0000 +@@ -217,13 +217,14 @@ */ static struct sk_buff *dequeue(struct codel_vars *vars, struct Qdisc *sch) { @@ -126,7 +126,7 @@ sch->q.qlen--; } return skb; -@@ -256,7 +257,7 @@ begin: +@@ -256,7 +257,7 @@ prev_ecn_mark = q->cstats.ecn_mark; skb = codel_dequeue(sch, &q->cparams, &flow->cvars, &q->cstats, @@ -135,6 +135,3 @@ flow->dropped += q->cstats.drop_count - prev_drop_count; flow->dropped += q->cstats.ecn_mark - prev_ecn_mark; --- -1.7.10 - diff -Nru linux-3.2.46/debian/patches/features/all/codel/0008-codel-refine-one-condition-to-avoid-a-nul-rec_inv_sq.patch linux-3.2.46/debian/patches/features/all/codel/0008-codel-refine-one-condition-to-avoid-a-nul-rec_inv_sq.patch --- linux-3.2.46/debian/patches/features/all/codel/0008-codel-refine-one-condition-to-avoid-a-nul-rec_inv_sq.patch 2013-02-24 03:52:32.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/codel/0008-codel-refine-one-condition-to-avoid-a-nul-rec_inv_sq.patch 2013-07-26 19:22:42.000000000 +0000 @@ -24,11 +24,11 @@ include/net/codel.h | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) -diff --git a/include/net/codel.h b/include/net/codel.h -index 550debf..389cf62 100644 ---- a/include/net/codel.h -+++ b/include/net/codel.h -@@ -305,6 +305,8 @@ static struct sk_buff *codel_dequeue(struct Qdisc *sch, +Index: linux-3.2.46/include/net/codel.h +=================================================================== +--- linux-3.2.46.orig/include/net/codel.h 2013-07-26 19:22:39.000000000 +0000 ++++ linux-3.2.46/include/net/codel.h 2013-07-26 19:22:41.000000000 +0000 +@@ -305,6 +305,8 @@ } } } else if (drop) { @@ -37,7 +37,7 @@ if (params->ecn && INET_ECN_set_ce(skb)) { stats->ecn_mark++; } else { -@@ -320,9 +322,11 @@ static struct sk_buff *codel_dequeue(struct Qdisc *sch, +@@ -320,9 +322,11 @@ * assume that the drop rate that controlled the queue on the * last cycle is a good starting point to control it now. */ diff -Nru linux-3.2.46/debian/patches/features/all/cpu-devices/ACPI-Load-acpi-cpufreq-from-processor-driver-automat.patch linux-3.2.46/debian/patches/features/all/cpu-devices/ACPI-Load-acpi-cpufreq-from-processor-driver-automat.patch --- linux-3.2.46/debian/patches/features/all/cpu-devices/ACPI-Load-acpi-cpufreq-from-processor-driver-automat.patch 2013-02-24 03:52:33.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/cpu-devices/ACPI-Load-acpi-cpufreq-from-processor-driver-automat.patch 2013-07-26 19:23:19.000000000 +0000 @@ -22,11 +22,11 @@ include/acpi/processor.h | 1 + 3 files changed, 24 insertions(+) -diff --git a/drivers/acpi/processor_driver.c b/drivers/acpi/processor_driver.c -index 0034ede..e6920d0 100644 ---- a/drivers/acpi/processor_driver.c -+++ b/drivers/acpi/processor_driver.c -@@ -497,6 +497,7 @@ static int __cpuinit acpi_processor_add(struct acpi_device *device) +Index: linux-3.2.46/drivers/acpi/processor_driver.c +=================================================================== +--- linux-3.2.46.orig/drivers/acpi/processor_driver.c 2013-07-26 19:22:54.000000000 +0000 ++++ linux-3.2.46/drivers/acpi/processor_driver.c 2013-07-26 19:23:17.000000000 +0000 +@@ -500,6 +500,7 @@ #ifdef CONFIG_CPU_FREQ acpi_processor_ppc_has_changed(pr, 0); @@ -34,11 +34,11 @@ #endif acpi_processor_get_throttling_info(pr); acpi_processor_get_limit_info(pr); -diff --git a/drivers/acpi/processor_perflib.c b/drivers/acpi/processor_perflib.c -index 85b3237..0af48a8 100644 ---- a/drivers/acpi/processor_perflib.c -+++ b/drivers/acpi/processor_perflib.c -@@ -240,6 +240,28 @@ void acpi_processor_ppc_exit(void) +Index: linux-3.2.46/drivers/acpi/processor_perflib.c +=================================================================== +--- linux-3.2.46.orig/drivers/acpi/processor_perflib.c 2013-07-26 18:54:39.000000000 +0000 ++++ linux-3.2.46/drivers/acpi/processor_perflib.c 2013-07-26 19:23:18.000000000 +0000 +@@ -240,6 +240,28 @@ acpi_processor_ppc_status &= ~PPC_REGISTERED; } @@ -67,11 +67,11 @@ static int acpi_processor_get_performance_control(struct acpi_processor *pr) { int result = 0; -diff --git a/include/acpi/processor.h b/include/acpi/processor.h -index 610f6fb..da57fdc 100644 ---- a/include/acpi/processor.h -+++ b/include/acpi/processor.h -@@ -224,6 +224,7 @@ struct acpi_processor_errata { +Index: linux-3.2.46/include/acpi/processor.h +=================================================================== +--- linux-3.2.46.orig/include/acpi/processor.h 2013-07-26 18:54:39.000000000 +0000 ++++ linux-3.2.46/include/acpi/processor.h 2013-07-26 19:23:18.000000000 +0000 +@@ -224,6 +224,7 @@ } piix4; }; diff -Nru linux-3.2.46/debian/patches/features/all/cpu-devices/Add-driver-auto-probing-for-x86-features-v4.patch linux-3.2.46/debian/patches/features/all/cpu-devices/Add-driver-auto-probing-for-x86-features-v4.patch --- linux-3.2.46/debian/patches/features/all/cpu-devices/Add-driver-auto-probing-for-x86-features-v4.patch 2013-02-24 03:52:33.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/cpu-devices/Add-driver-auto-probing-for-x86-features-v4.patch 2013-07-26 19:23:10.000000000 +0000 @@ -68,8 +68,10 @@ - adjust context - make do without ADD_TO_DEVTABLE in file2alias] --- ---- /dev/null -+++ b/arch/x86/include/asm/cpu_device_id.h +Index: linux-3.2.46/arch/x86/include/asm/cpu_device_id.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/arch/x86/include/asm/cpu_device_id.h 2013-07-26 19:23:08.000000000 +0000 @@ -0,0 +1,13 @@ +#ifndef _CPU_DEVICE_ID +#define _CPU_DEVICE_ID 1 @@ -84,8 +86,10 @@ +extern const struct x86_cpu_id *x86_match_cpu(const struct x86_cpu_id *match); + +#endif ---- a/arch/x86/kernel/cpu/Makefile -+++ b/arch/x86/kernel/cpu/Makefile +Index: linux-3.2.46/arch/x86/kernel/cpu/Makefile +=================================================================== +--- linux-3.2.46.orig/arch/x86/kernel/cpu/Makefile 2013-07-26 18:54:42.000000000 +0000 ++++ linux-3.2.46/arch/x86/kernel/cpu/Makefile 2013-07-26 19:23:09.000000000 +0000 @@ -16,6 +16,7 @@ obj-y += proc.o capflags.o powerflags.o common.o obj-y += vmware.o hypervisor.o sched.o mshyperv.o @@ -94,8 +98,10 @@ obj-$(CONFIG_X86_32) += bugs.o obj-$(CONFIG_X86_64) += bugs_64.o ---- /dev/null -+++ b/arch/x86/kernel/cpu/match.c +Index: linux-3.2.46/arch/x86/kernel/cpu/match.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/arch/x86/kernel/cpu/match.c 2013-07-26 19:23:09.000000000 +0000 @@ -0,0 +1,48 @@ +#include +#include @@ -145,8 +151,10 @@ + return NULL; +} +EXPORT_SYMBOL(x86_match_cpu); ---- a/arch/x86/kernel/cpuid.c -+++ b/arch/x86/kernel/cpuid.c +Index: linux-3.2.46/arch/x86/kernel/cpuid.c +=================================================================== +--- linux-3.2.46.orig/arch/x86/kernel/cpuid.c 2013-07-26 18:54:42.000000000 +0000 ++++ linux-3.2.46/arch/x86/kernel/cpuid.c 2013-07-26 19:23:09.000000000 +0000 @@ -40,6 +40,7 @@ #include #include @@ -240,8 +248,10 @@ for_each_online_cpu(i) { err = cpuid_device_create(i); if (err != 0) ---- a/include/linux/mod_devicetable.h -+++ b/include/linux/mod_devicetable.h +Index: linux-3.2.46/include/linux/mod_devicetable.h +=================================================================== +--- linux-3.2.46.orig/include/linux/mod_devicetable.h 2013-07-26 18:54:42.000000000 +0000 ++++ linux-3.2.46/include/linux/mod_devicetable.h 2013-07-26 19:23:09.000000000 +0000 @@ -542,4 +542,25 @@ kernel_ulong_t driver_data; /* data private to the driver */ }; @@ -268,8 +278,10 @@ +#define X86_FEATURE_ANY 0 /* Same as FPU, you can't test for that */ + #endif /* LINUX_MOD_DEVICETABLE_H */ ---- a/scripts/mod/file2alias.c -+++ b/scripts/mod/file2alias.c +Index: linux-3.2.46/scripts/mod/file2alias.c +=================================================================== +--- linux-3.2.46.orig/scripts/mod/file2alias.c 2013-07-26 18:54:42.000000000 +0000 ++++ linux-3.2.46/scripts/mod/file2alias.c 2013-07-26 19:23:09.000000000 +0000 @@ -880,6 +880,29 @@ return 1; } diff -Nru linux-3.2.46/debian/patches/features/all/cpu-devices/cpu-convert-cpu-and-machinecheck-sysdev_class-to-a-r.patch linux-3.2.46/debian/patches/features/all/cpu-devices/cpu-convert-cpu-and-machinecheck-sysdev_class-to-a-r.patch --- linux-3.2.46/debian/patches/features/all/cpu-devices/cpu-convert-cpu-and-machinecheck-sysdev_class-to-a-r.patch 2013-02-24 03:52:33.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/cpu-devices/cpu-convert-cpu-and-machinecheck-sysdev_class-to-a-r.patch 2013-07-26 19:22:57.000000000 +0000 @@ -87,8 +87,10 @@ kernel/sched.c | 40 ++-- 38 files changed, 874 insertions(+), 877 deletions(-) ---- a/arch/avr32/kernel/cpu.c -+++ b/arch/avr32/kernel/cpu.c +Index: linux-3.2.46/arch/avr32/kernel/cpu.c +=================================================================== +--- linux-3.2.46.orig/arch/avr32/kernel/cpu.c 2013-07-26 18:54:47.000000000 +0000 ++++ linux-3.2.46/arch/avr32/kernel/cpu.c 2013-07-26 19:22:53.000000000 +0000 @@ -6,7 +6,7 @@ * published by the Free Software Foundation. */ @@ -98,7 +100,7 @@ #include #include #include -@@ -26,16 +26,16 @@ static DEFINE_PER_CPU(struct cpu, cpu_de +@@ -26,16 +26,16 @@ * XXX: If/when a SMP-capable implementation of AVR32 will ever be * made, we must make sure that the code executes on the correct CPU. */ @@ -119,7 +121,7 @@ size_t count) { unsigned long val; -@@ -48,16 +48,16 @@ static ssize_t store_pc0event(struct sys +@@ -48,16 +48,16 @@ sysreg_write(PCCR, val); return count; } @@ -140,7 +142,7 @@ const char *buf, size_t count) { unsigned long val; -@@ -71,16 +71,16 @@ static ssize_t store_pc0count(struct sys +@@ -71,16 +71,16 @@ return count; } @@ -161,7 +163,7 @@ size_t count) { unsigned long val; -@@ -93,16 +93,16 @@ static ssize_t store_pc1event(struct sys +@@ -93,16 +93,16 @@ sysreg_write(PCCR, val); return count; } @@ -182,7 +184,7 @@ size_t count) { unsigned long val; -@@ -116,16 +116,16 @@ static ssize_t store_pc1count(struct sys +@@ -116,16 +116,16 @@ return count; } @@ -203,7 +205,7 @@ size_t count) { unsigned long val; -@@ -139,16 +139,16 @@ static ssize_t store_pccycles(struct sys +@@ -139,16 +139,16 @@ return count; } @@ -224,7 +226,7 @@ size_t count) { unsigned long pccr, val; -@@ -167,12 +167,12 @@ static ssize_t store_pcenable(struct sys +@@ -167,12 +167,12 @@ return count; } @@ -243,7 +245,7 @@ #endif /* CONFIG_PERFORMANCE_COUNTERS */ -@@ -186,12 +186,12 @@ static int __init topology_init(void) +@@ -186,12 +186,12 @@ register_cpu(c, cpu); #ifdef CONFIG_PERFORMANCE_COUNTERS @@ -262,8 +264,10 @@ #endif } ---- a/arch/ia64/kernel/err_inject.c -+++ b/arch/ia64/kernel/err_inject.c +Index: linux-3.2.46/arch/ia64/kernel/err_inject.c +=================================================================== +--- linux-3.2.46.orig/arch/ia64/kernel/err_inject.c 2013-07-26 18:54:47.000000000 +0000 ++++ linux-3.2.46/arch/ia64/kernel/err_inject.c 2013-07-26 19:22:53.000000000 +0000 @@ -24,7 +24,7 @@ * Copyright (C) 2006, Intel Corp. All rights reserved. * @@ -286,7 +290,7 @@ static u64 call_start[NR_CPUS]; static u64 phys_addr[NR_CPUS]; -@@ -55,7 +55,7 @@ static u64 resources[NR_CPUS]; +@@ -55,7 +55,7 @@ #define show(name) \ static ssize_t \ @@ -295,7 +299,7 @@ char *buf) \ { \ u32 cpu=dev->id; \ -@@ -64,7 +64,7 @@ show_##name(struct sys_device *dev, stru +@@ -64,7 +64,7 @@ #define store(name) \ static ssize_t \ @@ -304,7 +308,7 @@ const char *buf, size_t size) \ { \ unsigned int cpu=dev->id; \ -@@ -78,7 +78,7 @@ show(call_start) +@@ -78,7 +78,7 @@ * processor. The cpu number in driver is only used for storing data. */ static ssize_t @@ -313,7 +317,7 @@ const char *buf, size_t size) { unsigned int cpu=dev->id; -@@ -127,7 +127,7 @@ show(err_type_info) +@@ -127,7 +127,7 @@ store(err_type_info) static ssize_t @@ -322,7 +326,7 @@ char *buf) { unsigned int cpu=dev->id; -@@ -135,7 +135,7 @@ show_virtual_to_phys(struct sys_device * +@@ -135,7 +135,7 @@ } static ssize_t @@ -331,7 +335,7 @@ const char *buf, size_t size) { unsigned int cpu=dev->id; -@@ -159,8 +159,8 @@ show(err_struct_info) +@@ -159,8 +159,8 @@ store(err_struct_info) static ssize_t @@ -342,7 +346,7 @@ { unsigned int cpu=dev->id; -@@ -171,8 +171,8 @@ show_err_data_buffer(struct sys_device * +@@ -171,8 +171,8 @@ } static ssize_t @@ -353,7 +357,7 @@ const char *buf, size_t size) { unsigned int cpu=dev->id; -@@ -209,14 +209,14 @@ define_one_ro(capabilities); +@@ -209,14 +209,14 @@ define_one_ro(resources); static struct attribute *default_attrs[] = { @@ -376,7 +380,7 @@ NULL }; -@@ -225,12 +225,12 @@ static struct attribute_group err_inject +@@ -225,12 +225,12 @@ .name = "err_inject" }; /* Add/Remove err_inject interface for CPU device */ @@ -391,7 +395,7 @@ { sysfs_remove_group(&sys_dev->kobj, &err_inject_attr_group); return 0; -@@ -239,9 +239,9 @@ static int __cpuinit err_inject_cpu_call +@@ -239,9 +239,9 @@ unsigned long action, void *hcpu) { unsigned int cpu = (unsigned long)hcpu; @@ -403,7 +407,7 @@ switch (action) { case CPU_ONLINE: case CPU_ONLINE_FROZEN: -@@ -283,13 +283,13 @@ static void __exit +@@ -283,13 +283,13 @@ err_inject_exit(void) { int i; @@ -419,9 +423,11 @@ sysfs_remove_group(&sys_dev->kobj, &err_inject_attr_group); } unregister_hotcpu_notifier(&err_inject_cpu_notifier); ---- a/arch/ia64/kernel/topology.c -+++ b/arch/ia64/kernel/topology.c -@@ -350,7 +350,7 @@ static int __cpuinit cpu_cache_sysfs_ini +Index: linux-3.2.46/arch/ia64/kernel/topology.c +=================================================================== +--- linux-3.2.46.orig/arch/ia64/kernel/topology.c 2013-07-26 18:54:47.000000000 +0000 ++++ linux-3.2.46/arch/ia64/kernel/topology.c 2013-07-26 19:22:53.000000000 +0000 +@@ -350,7 +350,7 @@ } /* Add cache interface for CPU device */ @@ -430,7 +436,7 @@ { unsigned int cpu = sys_dev->id; unsigned long i, j; -@@ -400,7 +400,7 @@ static int __cpuinit cache_add_dev(struc +@@ -400,7 +400,7 @@ } /* Remove cache interface for CPU device */ @@ -439,7 +445,7 @@ { unsigned int cpu = sys_dev->id; unsigned long i; -@@ -428,9 +428,9 @@ static int __cpuinit cache_cpu_callback( +@@ -428,9 +428,9 @@ unsigned long action, void *hcpu) { unsigned int cpu = (unsigned long)hcpu; @@ -451,7 +457,7 @@ switch (action) { case CPU_ONLINE: case CPU_ONLINE_FROZEN: -@@ -454,7 +454,7 @@ static int __init cache_sysfs_init(void) +@@ -454,7 +454,7 @@ int i; for_each_online_cpu(i) { @@ -460,8 +466,10 @@ cache_add_dev(sys_dev); } ---- a/arch/powerpc/include/asm/spu.h -+++ b/arch/powerpc/include/asm/spu.h +Index: linux-3.2.46/arch/powerpc/include/asm/spu.h +=================================================================== +--- linux-3.2.46.orig/arch/powerpc/include/asm/spu.h 2013-07-26 18:54:47.000000000 +0000 ++++ linux-3.2.46/arch/powerpc/include/asm/spu.h 2013-07-26 19:22:53.000000000 +0000 @@ -25,7 +25,7 @@ #ifdef __KERNEL__ @@ -471,7 +479,7 @@ #include #define LS_SIZE (256 * 1024) -@@ -166,7 +166,7 @@ struct spu { +@@ -166,7 +166,7 @@ /* beat only */ u64 shadow_int_mask_RW[3]; @@ -480,7 +488,7 @@ int has_mem_affinity; struct list_head aff_list; -@@ -270,11 +270,11 @@ struct spufs_calls { +@@ -270,11 +270,11 @@ int register_spu_syscalls(struct spufs_calls *calls); void unregister_spu_syscalls(struct spufs_calls *calls); @@ -496,8 +504,10 @@ int spu_handle_mm_fault(struct mm_struct *mm, unsigned long ea, unsigned long dsisr, unsigned *flt); ---- a/arch/powerpc/include/asm/topology.h -+++ b/arch/powerpc/include/asm/topology.h +Index: linux-3.2.46/arch/powerpc/include/asm/topology.h +=================================================================== +--- linux-3.2.46.orig/arch/powerpc/include/asm/topology.h 2013-07-26 18:54:47.000000000 +0000 ++++ linux-3.2.46/arch/powerpc/include/asm/topology.h 2013-07-26 19:22:53.000000000 +0000 @@ -3,7 +3,7 @@ #ifdef __KERNEL__ @@ -507,7 +517,7 @@ struct device_node; #ifdef CONFIG_NUMA -@@ -86,19 +86,19 @@ extern int __node_distance(int, int); +@@ -86,19 +86,19 @@ extern void __init dump_numa_cpu_topology(void); @@ -531,9 +541,11 @@ int nid) { } ---- a/arch/powerpc/kernel/cacheinfo.c -+++ b/arch/powerpc/kernel/cacheinfo.c -@@ -451,15 +451,15 @@ out: +Index: linux-3.2.46/arch/powerpc/kernel/cacheinfo.c +=================================================================== +--- linux-3.2.46.orig/arch/powerpc/kernel/cacheinfo.c 2013-07-26 18:54:47.000000000 +0000 ++++ linux-3.2.46/arch/powerpc/kernel/cacheinfo.c 2013-07-26 19:22:53.000000000 +0000 +@@ -451,15 +451,15 @@ static struct cache_dir *__cpuinit cacheinfo_create_cache_dir(unsigned int cpu_id) { struct cache_dir *cache_dir; @@ -554,8 +566,10 @@ if (!kobj) goto err; ---- a/arch/powerpc/kernel/smp.c -+++ b/arch/powerpc/kernel/smp.c +Index: linux-3.2.46/arch/powerpc/kernel/smp.c +=================================================================== +--- linux-3.2.46.orig/arch/powerpc/kernel/smp.c 2013-07-26 18:54:47.000000000 +0000 ++++ linux-3.2.46/arch/powerpc/kernel/smp.c 2013-07-26 19:22:53.000000000 +0000 @@ -27,7 +27,7 @@ #include #include @@ -565,15 +579,17 @@ #include #include #include ---- a/arch/powerpc/kernel/sysfs.c -+++ b/arch/powerpc/kernel/sysfs.c +Index: linux-3.2.46/arch/powerpc/kernel/sysfs.c +=================================================================== +--- linux-3.2.46.orig/arch/powerpc/kernel/sysfs.c 2013-07-26 18:54:47.000000000 +0000 ++++ linux-3.2.46/arch/powerpc/kernel/sysfs.c 2013-07-26 19:22:53.000000000 +0000 @@ -1,4 +1,4 @@ -#include +#include #include #include #include -@@ -37,12 +37,12 @@ static DEFINE_PER_CPU(struct cpu, cpu_de +@@ -37,12 +37,12 @@ /* Time in microseconds we delay before sleeping in the idle loop */ DEFINE_PER_CPU(long, smt_snooze_delay) = { 100 }; @@ -589,7 +605,7 @@ ssize_t ret; long snooze; -@@ -50,21 +50,21 @@ static ssize_t store_smt_snooze_delay(st +@@ -50,21 +50,21 @@ if (ret != 1) return -EINVAL; @@ -617,7 +633,7 @@ store_smt_snooze_delay); static int __init setup_smt_snooze_delay(char *str) -@@ -117,25 +117,25 @@ static void write_##NAME(void *val) \ +@@ -117,25 +117,25 @@ ppc_enable_pmcs(); \ mtspr(ADDRESS, *(unsigned long *)val); \ } \ @@ -650,7 +666,7 @@ return count; \ } -@@ -178,16 +178,16 @@ SYSFS_PMCSETUP(purr, SPRN_PURR); +@@ -178,16 +178,16 @@ SYSFS_PMCSETUP(spurr, SPRN_SPURR); SYSFS_PMCSETUP(dscr, SPRN_DSCR); @@ -673,7 +689,7 @@ { return sprintf(buf, "%lx\n", dscr_default); } -@@ -200,8 +200,8 @@ static void update_dscr(void *dummy) +@@ -200,8 +200,8 @@ } } @@ -684,7 +700,7 @@ size_t count) { unsigned long val; -@@ -217,15 +217,14 @@ static ssize_t __used store_dscr_default +@@ -217,15 +217,14 @@ return count; } @@ -702,7 +718,7 @@ } #endif /* CONFIG_PPC64 */ -@@ -269,72 +268,72 @@ SYSFS_PMCSETUP(tsr3, SPRN_PA6T_TSR3); +@@ -269,72 +268,72 @@ #endif /* HAS_PPC_PMC_PA6T */ #ifdef HAS_PPC_PMC_IBM @@ -828,7 +844,7 @@ #endif /* CONFIG_DEBUG_KERNEL */ }; #endif /* HAS_PPC_PMC_PA6T */ -@@ -343,14 +342,14 @@ static struct sysdev_attribute pa6t_attr +@@ -343,14 +342,14 @@ static void __cpuinit register_cpu_online(unsigned int cpu) { struct cpu *c = &per_cpu(cpu_devices, cpu); @@ -846,7 +862,7 @@ #endif /* PMC stuff */ -@@ -358,14 +357,14 @@ static void __cpuinit register_cpu_onlin +@@ -358,14 +357,14 @@ #ifdef HAS_PPC_PMC_IBM case PPC_PMC_IBM: attrs = ibm_common_attrs; @@ -863,7 +879,7 @@ pmc_attrs = classic_pmc_attrs; break; #endif /* HAS_PPC_PMC_G4 */ -@@ -373,7 +372,7 @@ static void __cpuinit register_cpu_onlin +@@ -373,7 +372,7 @@ case PPC_PMC_PA6T: /* PA Semi starts counting at PMC0 */ attrs = pa6t_attrs; @@ -872,7 +888,7 @@ pmc_attrs = NULL; break; #endif /* HAS_PPC_PMC_PA6T */ -@@ -384,24 +383,24 @@ static void __cpuinit register_cpu_onlin +@@ -384,24 +383,24 @@ } for (i = 0; i < nattrs; i++) @@ -903,7 +919,7 @@ #endif /* CONFIG_PPC64 */ cacheinfo_cpu_online(cpu); -@@ -411,8 +410,8 @@ static void __cpuinit register_cpu_onlin +@@ -411,8 +410,8 @@ static void unregister_cpu_online(unsigned int cpu) { struct cpu *c = &per_cpu(cpu_devices, cpu); @@ -914,7 +930,7 @@ int i, nattrs; BUG_ON(!c->hotpluggable); -@@ -420,7 +419,7 @@ static void unregister_cpu_online(unsign +@@ -420,7 +419,7 @@ #ifdef CONFIG_PPC64 if (!firmware_has_feature(FW_FEATURE_ISERIES) && cpu_has_feature(CPU_FTR_SMT)) @@ -923,7 +939,7 @@ #endif /* PMC stuff */ -@@ -428,14 +427,14 @@ static void unregister_cpu_online(unsign +@@ -428,14 +427,14 @@ #ifdef HAS_PPC_PMC_IBM case PPC_PMC_IBM: attrs = ibm_common_attrs; @@ -940,7 +956,7 @@ pmc_attrs = classic_pmc_attrs; break; #endif /* HAS_PPC_PMC_G4 */ -@@ -443,7 +442,7 @@ static void unregister_cpu_online(unsign +@@ -443,7 +442,7 @@ case PPC_PMC_PA6T: /* PA Semi starts counting at PMC0 */ attrs = pa6t_attrs; @@ -949,7 +965,7 @@ pmc_attrs = NULL; break; #endif /* HAS_PPC_PMC_PA6T */ -@@ -454,24 +453,24 @@ static void unregister_cpu_online(unsign +@@ -454,24 +453,24 @@ } for (i = 0; i < nattrs; i++) @@ -980,7 +996,7 @@ #endif /* CONFIG_PPC64 */ cacheinfo_cpu_offline(cpu); -@@ -523,70 +522,70 @@ static struct notifier_block __cpuinitda +@@ -523,70 +522,70 @@ static DEFINE_MUTEX(cpu_mutex); @@ -1067,7 +1083,7 @@ /* NUMA stuff */ -@@ -600,7 +599,7 @@ static void register_nodes(void) +@@ -600,7 +599,7 @@ register_one_node(i); } @@ -1076,7 +1092,7 @@ { struct node *node = &node_devices[nid]; return sysfs_create_link(&node->sysdev.kobj, &dev->kobj, -@@ -608,7 +607,7 @@ int sysfs_add_device_to_node(struct sys_ +@@ -608,7 +607,7 @@ } EXPORT_SYMBOL_GPL(sysfs_add_device_to_node); @@ -1085,7 +1101,7 @@ { struct node *node = &node_devices[nid]; sysfs_remove_link(&node->sysdev.kobj, kobject_name(&dev->kobj)); -@@ -624,14 +623,14 @@ static void register_nodes(void) +@@ -624,14 +623,14 @@ #endif /* Only valid if CPU is present. */ @@ -1105,7 +1121,7 @@ static int __init topology_init(void) { -@@ -656,7 +655,7 @@ static int __init topology_init(void) +@@ -656,7 +655,7 @@ if (cpu_online(cpu) || c->hotpluggable) { register_cpu(c, cpu); @@ -1114,9 +1130,11 @@ } if (cpu_online(cpu)) ---- a/arch/powerpc/mm/numa.c -+++ b/arch/powerpc/mm/numa.c -@@ -1462,7 +1462,7 @@ int arch_update_cpu_topology(void) +Index: linux-3.2.46/arch/powerpc/mm/numa.c +=================================================================== +--- linux-3.2.46.orig/arch/powerpc/mm/numa.c 2013-07-26 18:54:47.000000000 +0000 ++++ linux-3.2.46/arch/powerpc/mm/numa.c 2013-07-26 19:22:53.000000000 +0000 +@@ -1462,7 +1462,7 @@ { int cpu, nid, old_nid; unsigned int associativity[VPHN_ASSOC_BUFSIZE] = {0}; @@ -1125,7 +1143,7 @@ for_each_cpu(cpu,&cpu_associativity_changes_mask) { vphn_get_associativity(cpu, associativity); -@@ -1483,9 +1483,9 @@ int arch_update_cpu_topology(void) +@@ -1483,9 +1483,9 @@ register_cpu_under_node(cpu, nid); put_online_cpus(); @@ -1138,8 +1156,10 @@ } return 1; ---- a/arch/powerpc/platforms/cell/cbe_thermal.c -+++ b/arch/powerpc/platforms/cell/cbe_thermal.c +Index: linux-3.2.46/arch/powerpc/platforms/cell/cbe_thermal.c +=================================================================== +--- linux-3.2.46.orig/arch/powerpc/platforms/cell/cbe_thermal.c 2013-07-26 18:54:47.000000000 +0000 ++++ linux-3.2.46/arch/powerpc/platforms/cell/cbe_thermal.c 2013-07-26 19:22:53.000000000 +0000 @@ -46,7 +46,7 @@ */ @@ -1160,7 +1180,7 @@ .attr = { .name = __stringify(_name), .mode = _mode }, \ .show = _prefix ## _show_ ## _name, \ .store = _prefix ## _store_ ## _name, \ -@@ -76,36 +76,36 @@ static inline u8 temp_to_reg(u8 temp) +@@ -76,36 +76,36 @@ return ((temp - TEMP_MIN) >> 1) & 0x3f; } @@ -1204,7 +1224,7 @@ return sprintf(buf, "%d\n", reg_to_temp(value)); } -@@ -147,48 +147,48 @@ static ssize_t store_throttle(struct cbe +@@ -147,48 +147,48 @@ return size; } @@ -1273,7 +1293,7 @@ value = in_be64(&pmd_regs->ts_ctsr2); value = (value >> pos) & 0x3f; -@@ -199,64 +199,64 @@ static ssize_t ppe_show_temp(struct sys_ +@@ -199,64 +199,64 @@ /* shows the temperature of the DTS on the PPE, * located near the linear thermal sensor */ @@ -1366,7 +1386,7 @@ static struct attribute *spu_attributes[] = { -@@ -272,19 +272,19 @@ static struct attribute_group spu_attrib +@@ -272,19 +272,19 @@ .attrs = spu_attributes, }; @@ -1391,7 +1411,7 @@ static struct attribute *ppe_attributes[] = { &attr_ppe_temperature0.attr, -@@ -307,7 +307,7 @@ static int __init init_default_values(vo +@@ -307,7 +307,7 @@ { int cpu; struct cbe_pmd_regs __iomem *pmd_regs; @@ -1400,7 +1420,7 @@ union ppe_spe_reg tpr; union spe_reg str1; u64 str2; -@@ -349,14 +349,14 @@ static int __init init_default_values(vo +@@ -349,14 +349,14 @@ for_each_possible_cpu (cpu) { pr_debug("processing cpu %d\n", cpu); @@ -1419,7 +1439,7 @@ if (!pmd_regs) { pr_info("invalid CBE regs pointer for cbe_thermal\n"); -@@ -379,8 +379,8 @@ static int __init thermal_init(void) +@@ -379,8 +379,8 @@ int rc = init_default_values(); if (rc == 0) { @@ -1430,7 +1450,7 @@ } return rc; -@@ -389,8 +389,8 @@ module_init(thermal_init); +@@ -389,8 +389,8 @@ static void __exit thermal_exit(void) { @@ -1441,9 +1461,11 @@ } module_exit(thermal_exit); ---- a/arch/powerpc/platforms/cell/spu_base.c -+++ b/arch/powerpc/platforms/cell/spu_base.c -@@ -519,31 +519,32 @@ void spu_init_channels(struct spu *spu) +Index: linux-3.2.46/arch/powerpc/platforms/cell/spu_base.c +=================================================================== +--- linux-3.2.46.orig/arch/powerpc/platforms/cell/spu_base.c 2013-07-26 18:54:47.000000000 +0000 ++++ linux-3.2.46/arch/powerpc/platforms/cell/spu_base.c 2013-07-26 19:22:53.000000000 +0000 +@@ -519,31 +519,32 @@ } EXPORT_SYMBOL_GPL(spu_init_channels); @@ -1482,7 +1504,7 @@ /* we're in trouble here, but try unwinding anyway */ if (rc) { -@@ -552,7 +553,7 @@ int spu_add_sysdev_attr_group(struct att +@@ -552,7 +553,7 @@ list_for_each_entry_continue_reverse(spu, &spu_full_list, full_list) @@ -1491,7 +1513,7 @@ break; } } -@@ -561,45 +562,45 @@ int spu_add_sysdev_attr_group(struct att +@@ -561,45 +562,45 @@ return rc; } @@ -1549,7 +1571,7 @@ return 0; } -@@ -635,7 +636,7 @@ static int __init create_spu(void *data) +@@ -635,7 +636,7 @@ if (ret) goto out_destroy; @@ -1558,7 +1580,7 @@ if (ret) goto out_free_irqs; -@@ -692,10 +693,10 @@ static unsigned long long spu_acct_time( +@@ -692,10 +693,10 @@ } @@ -1572,7 +1594,7 @@ return sprintf(buf, "%s %llu %llu %llu %llu " "%llu %llu %llu %llu %llu %llu %llu %llu\n", -@@ -714,7 +715,7 @@ static ssize_t spu_stat_show(struct sys_ +@@ -714,7 +715,7 @@ spu->stats.libassist); } @@ -1581,7 +1603,7 @@ #ifdef CONFIG_KEXEC -@@ -813,8 +814,8 @@ static int __init init_spu_base(void) +@@ -813,8 +814,8 @@ if (!spu_management_ops) goto out; @@ -1592,7 +1614,7 @@ if (ret) goto out; -@@ -823,7 +824,7 @@ static int __init init_spu_base(void) +@@ -823,7 +824,7 @@ if (ret < 0) { printk(KERN_WARNING "%s: Error initializing spus\n", __func__); @@ -1601,7 +1623,7 @@ } if (ret > 0) -@@ -833,15 +834,15 @@ static int __init init_spu_base(void) +@@ -833,15 +834,15 @@ xmon_register_spus(&spu_full_list); crash_register_spus(&spu_full_list); mutex_unlock(&spu_full_list_mutex); @@ -1620,8 +1642,10 @@ out: return ret; } ---- a/arch/powerpc/platforms/pseries/pseries_energy.c -+++ b/arch/powerpc/platforms/pseries/pseries_energy.c +Index: linux-3.2.46/arch/powerpc/platforms/pseries/pseries_energy.c +=================================================================== +--- linux-3.2.46.orig/arch/powerpc/platforms/pseries/pseries_energy.c 2013-07-26 18:54:47.000000000 +0000 ++++ linux-3.2.46/arch/powerpc/platforms/pseries/pseries_energy.c 2013-07-26 19:22:53.000000000 +0000 @@ -15,7 +15,7 @@ #include #include @@ -1631,7 +1655,7 @@ #include #include #include -@@ -184,7 +184,7 @@ static ssize_t get_best_energy_list(char +@@ -184,7 +184,7 @@ return s-page; } @@ -1640,7 +1664,7 @@ char *page, int activate) { int rc; -@@ -207,26 +207,26 @@ static ssize_t get_best_energy_data(stru +@@ -207,26 +207,26 @@ /* Wrapper functions */ @@ -1675,7 +1699,7 @@ { return get_best_energy_data(dev, page, 0); } -@@ -241,48 +241,48 @@ static ssize_t percpu_deactivate_hint_sh +@@ -241,48 +241,48 @@ * Per-cpu value of the hint */ @@ -1742,7 +1766,7 @@ if (err) break; } -@@ -298,23 +298,20 @@ static int __init pseries_energy_init(vo +@@ -298,23 +298,20 @@ static void __exit pseries_energy_cleanup(void) { int cpu; @@ -1772,9 +1796,11 @@ &attr_percpu_deactivate_hint.attr); } } ---- a/arch/powerpc/sysdev/ppc4xx_cpm.c -+++ b/arch/powerpc/sysdev/ppc4xx_cpm.c -@@ -179,12 +179,12 @@ static struct kobj_attribute cpm_idle_at +Index: linux-3.2.46/arch/powerpc/sysdev/ppc4xx_cpm.c +=================================================================== +--- linux-3.2.46.orig/arch/powerpc/sysdev/ppc4xx_cpm.c 2013-07-26 18:54:47.000000000 +0000 ++++ linux-3.2.46/arch/powerpc/sysdev/ppc4xx_cpm.c 2013-07-26 19:22:53.000000000 +0000 +@@ -179,12 +179,12 @@ static void cpm_idle_config_sysfs(void) { @@ -1790,9 +1816,11 @@ &cpm_idle_attr.attr); if (ret) printk(KERN_WARNING ---- a/arch/s390/kernel/smp.c -+++ b/arch/s390/kernel/smp.c -@@ -831,8 +831,8 @@ int setup_profiling_timer(unsigned int m +Index: linux-3.2.46/arch/s390/kernel/smp.c +=================================================================== +--- linux-3.2.46.orig/arch/s390/kernel/smp.c 2013-07-26 18:54:47.000000000 +0000 ++++ linux-3.2.46/arch/s390/kernel/smp.c 2013-07-26 19:22:53.000000000 +0000 +@@ -831,8 +831,8 @@ } #ifdef CONFIG_HOTPLUG_CPU @@ -1803,7 +1831,7 @@ { ssize_t count; -@@ -842,8 +842,8 @@ static ssize_t cpu_configure_show(struct +@@ -842,8 +842,8 @@ return count; } @@ -1814,7 +1842,7 @@ const char *buf, size_t count) { int cpu = dev->id; -@@ -889,11 +889,11 @@ out: +@@ -889,11 +889,11 @@ put_online_cpus(); return rc ? rc : count; } @@ -1829,7 +1857,7 @@ { int cpu = dev->id; ssize_t count; -@@ -919,22 +919,22 @@ static ssize_t cpu_polarization_show(str +@@ -919,22 +919,22 @@ mutex_unlock(&smp_cpu_state_mutex); return count; } @@ -1859,7 +1887,7 @@ NULL, }; -@@ -942,8 +942,8 @@ static struct attribute_group cpu_common +@@ -942,8 +942,8 @@ .attrs = cpu_common_attrs, }; @@ -1870,7 +1898,7 @@ { unsigned int capability; int rc; -@@ -953,10 +953,10 @@ static ssize_t show_capability(struct sy +@@ -953,10 +953,10 @@ return rc; return sprintf(buf, "%u\n", capability); } @@ -1884,7 +1912,7 @@ { struct s390_idle_data *idle; unsigned long long idle_count; -@@ -976,10 +976,10 @@ repeat: +@@ -976,10 +976,10 @@ goto repeat; return sprintf(buf, "%llu\n", idle_count); } @@ -1898,7 +1926,7 @@ { struct s390_idle_data *idle; unsigned long long now, idle_time, idle_enter; -@@ -1001,12 +1001,12 @@ repeat: +@@ -1001,12 +1001,12 @@ goto repeat; return sprintf(buf, "%llu\n", idle_time >> 12); } @@ -1915,7 +1943,7 @@ NULL, }; -@@ -1019,7 +1019,7 @@ static int __cpuinit smp_cpu_notify(stru +@@ -1019,7 +1019,7 @@ { unsigned int cpu = (unsigned int)(long)hcpu; struct cpu *c = &per_cpu(cpu_devices, cpu); @@ -1924,7 +1952,7 @@ int err = 0; switch (action) { -@@ -1042,7 +1042,7 @@ static struct notifier_block __cpuinitda +@@ -1042,7 +1042,7 @@ static int __devinit smp_add_present_cpu(int cpu) { struct cpu *c = &per_cpu(cpu_devices, cpu); @@ -1933,7 +1961,7 @@ int rc; c->hotpluggable = 1; -@@ -1095,8 +1095,8 @@ out: +@@ -1095,8 +1095,8 @@ return rc; } @@ -1944,7 +1972,7 @@ const char *buf, size_t count) { -@@ -1105,11 +1105,11 @@ static ssize_t __ref rescan_store(struct +@@ -1105,11 +1105,11 @@ rc = smp_rescan_cpus(); return rc ? rc : count; } @@ -1959,7 +1987,7 @@ char *buf) { ssize_t count; -@@ -1120,8 +1120,8 @@ static ssize_t dispatching_show(struct s +@@ -1120,8 +1120,8 @@ return count; } @@ -1970,7 +1998,7 @@ const char *buf, size_t count) { -@@ -1145,7 +1145,7 @@ out: +@@ -1145,7 +1145,7 @@ put_online_cpus(); return rc ? rc : count; } @@ -1979,7 +2007,7 @@ dispatching_store); static int __init topology_init(void) -@@ -1156,11 +1156,11 @@ static int __init topology_init(void) +@@ -1156,11 +1156,11 @@ register_cpu_notifier(&smp_cpu_nb); #ifdef CONFIG_HOTPLUG_CPU @@ -1993,9 +2021,11 @@ if (rc) return rc; for_each_present_cpu(cpu) { ---- a/arch/s390/kernel/topology.c -+++ b/arch/s390/kernel/topology.c -@@ -261,7 +261,7 @@ void store_topology(struct sysinfo_15_1_ +Index: linux-3.2.46/arch/s390/kernel/topology.c +=================================================================== +--- linux-3.2.46.orig/arch/s390/kernel/topology.c 2013-07-26 18:54:47.000000000 +0000 ++++ linux-3.2.46/arch/s390/kernel/topology.c 2013-07-26 19:22:53.000000000 +0000 +@@ -261,7 +261,7 @@ int arch_update_cpu_topology(void) { struct sysinfo_15_1_x *info = tl_info; @@ -2004,7 +2034,7 @@ int cpu; if (!MACHINE_HAS_TOPOLOGY) { -@@ -273,8 +273,8 @@ int arch_update_cpu_topology(void) +@@ -273,8 +273,8 @@ tl_to_cores(info); update_cpu_core_map(); for_each_online_cpu(cpu) { @@ -2015,8 +2045,10 @@ } return 1; } ---- a/arch/sh/kernel/cpu/sh4/sq.c -+++ b/arch/sh/kernel/cpu/sh4/sq.c +Index: linux-3.2.46/arch/sh/kernel/cpu/sh4/sq.c +=================================================================== +--- linux-3.2.46.orig/arch/sh/kernel/cpu/sh4/sq.c 2013-07-26 18:54:47.000000000 +0000 ++++ linux-3.2.46/arch/sh/kernel/cpu/sh4/sq.c 2013-07-26 19:22:53.000000000 +0000 @@ -13,7 +13,7 @@ #include #include @@ -2026,7 +2058,7 @@ #include #include #include -@@ -337,9 +337,9 @@ static struct kobj_type ktype_percpu_ent +@@ -337,9 +337,9 @@ .default_attrs = sq_sysfs_attrs, }; @@ -2038,7 +2070,7 @@ struct kobject *kobj; int error; -@@ -348,25 +348,27 @@ static int __devinit sq_sysdev_add(struc +@@ -348,25 +348,27 @@ return -ENOMEM; kobj = sq_kobject[cpu]; @@ -2072,7 +2104,7 @@ }; static int __init sq_api_init(void) -@@ -386,7 +388,7 @@ static int __init sq_api_init(void) +@@ -386,7 +388,7 @@ if (unlikely(!sq_bitmap)) goto out; @@ -2081,7 +2113,7 @@ if (unlikely(ret != 0)) goto out; -@@ -401,7 +403,7 @@ out: +@@ -401,7 +403,7 @@ static void __exit sq_api_exit(void) { @@ -2090,8 +2122,10 @@ kfree(sq_bitmap); kmem_cache_destroy(sq_cache); } ---- a/arch/sparc/kernel/sysfs.c -+++ b/arch/sparc/kernel/sysfs.c +Index: linux-3.2.46/arch/sparc/kernel/sysfs.c +=================================================================== +--- linux-3.2.46.orig/arch/sparc/kernel/sysfs.c 2013-07-26 18:54:47.000000000 +0000 ++++ linux-3.2.46/arch/sparc/kernel/sysfs.c 2013-07-26 19:22:53.000000000 +0000 @@ -3,7 +3,7 @@ * Copyright (C) 2007 David S. Miller */ @@ -2118,7 +2152,7 @@ SHOW_MMUSTAT_ULONG(immu_tsb_hits_ctx0_8k_tte); SHOW_MMUSTAT_ULONG(immu_tsb_ticks_ctx0_8k_tte); -@@ -58,38 +58,38 @@ SHOW_MMUSTAT_ULONG(dmmu_tsb_hits_ctxnon0 +@@ -58,38 +58,38 @@ SHOW_MMUSTAT_ULONG(dmmu_tsb_ticks_ctxnon0_256mb_tte); static struct attribute *mmu_stat_attrs[] = { @@ -2189,7 +2223,7 @@ NULL, }; -@@ -139,15 +139,15 @@ static unsigned long write_mmustat_enabl +@@ -139,15 +139,15 @@ return sun4v_mmustat_conf(ra, &orig_ra); } @@ -2209,7 +2243,7 @@ size_t count) { unsigned long val, err; -@@ -163,39 +163,39 @@ static ssize_t store_mmustat_enable(stru +@@ -163,39 +163,39 @@ return count; } @@ -2258,7 +2292,7 @@ { \ cpuinfo_sparc *c = &cpu_data(dev->id); \ return sprintf(buf, "%u\n", c->MEMBER); \ -@@ -209,14 +209,14 @@ SHOW_CPUDATA_UINT_NAME(l1_icache_line_si +@@ -209,14 +209,14 @@ SHOW_CPUDATA_UINT_NAME(l2_cache_size, ecache_size); SHOW_CPUDATA_UINT_NAME(l2_cache_line_size, ecache_line_size); @@ -2281,7 +2315,7 @@ }; static DEFINE_PER_CPU(struct cpu, cpu_devices); -@@ -224,11 +224,11 @@ static DEFINE_PER_CPU(struct cpu, cpu_de +@@ -224,11 +224,11 @@ static void register_cpu_online(unsigned int cpu) { struct cpu *c = &per_cpu(cpu_devices, cpu); @@ -2295,7 +2329,7 @@ register_mmu_stats(s); } -@@ -237,12 +237,12 @@ static void register_cpu_online(unsigned +@@ -237,12 +237,12 @@ static void unregister_cpu_online(unsigned int cpu) { struct cpu *c = &per_cpu(cpu_devices, cpu); @@ -2310,8 +2344,10 @@ } #endif ---- a/arch/tile/kernel/sysfs.c -+++ b/arch/tile/kernel/sysfs.c +Index: linux-3.2.46/arch/tile/kernel/sysfs.c +=================================================================== +--- linux-3.2.46.orig/arch/tile/kernel/sysfs.c 2013-07-26 18:54:47.000000000 +0000 ++++ linux-3.2.46/arch/tile/kernel/sysfs.c 2013-07-26 19:22:53.000000000 +0000 @@ -14,7 +14,7 @@ * /sys entry support. */ @@ -2321,7 +2357,7 @@ #include #include #include -@@ -32,55 +32,55 @@ static ssize_t get_hv_confstr(char *page +@@ -32,55 +32,55 @@ return n; } @@ -2395,7 +2431,7 @@ HV_CONF_ATTR(version, HV_CONFSTR_HV_SW_VER) HV_CONF_ATTR(config_version, HV_CONFSTR_HV_CONFIG_VER) -@@ -96,15 +96,15 @@ HV_CONF_ATTR(mezz_description, HV_CONFST +@@ -96,15 +96,15 @@ HV_CONF_ATTR(switch_control, HV_CONFSTR_SWITCH_CONTROL) static struct attribute *board_attrs[] = { @@ -2420,7 +2456,7 @@ NULL }; -@@ -151,12 +151,11 @@ hvconfig_bin_read(struct file *filp, str +@@ -151,12 +151,11 @@ static int __init create_sysfs_entries(void) { @@ -2434,7 +2470,7 @@ create_cpu_attr(chip_width); create_cpu_attr(chip_height); create_cpu_attr(chip_serial); -@@ -164,7 +163,7 @@ static int __init create_sysfs_entries(v +@@ -164,7 +163,7 @@ #define create_hv_attr(name) \ if (!err) \ @@ -2443,9 +2479,11 @@ create_hv_attr(type); create_hv_attr(version); create_hv_attr(config_version); ---- a/arch/x86/include/asm/mce.h -+++ b/arch/x86/include/asm/mce.h -@@ -149,7 +149,7 @@ static inline void enable_p5_mce(void) { +Index: linux-3.2.46/arch/x86/include/asm/mce.h +=================================================================== +--- linux-3.2.46.orig/arch/x86/include/asm/mce.h 2013-07-26 18:54:47.000000000 +0000 ++++ linux-3.2.46/arch/x86/include/asm/mce.h 2013-07-26 19:22:53.000000000 +0000 +@@ -149,7 +149,7 @@ void mce_setup(struct mce *m); void mce_log(struct mce *m); @@ -2454,9 +2492,11 @@ /* * Maximum banks number. ---- a/arch/x86/kernel/cpu/intel_cacheinfo.c -+++ b/arch/x86/kernel/cpu/intel_cacheinfo.c -@@ -872,8 +872,7 @@ static int __cpuinit detect_cache_attrib +Index: linux-3.2.46/arch/x86/kernel/cpu/intel_cacheinfo.c +=================================================================== +--- linux-3.2.46.orig/arch/x86/kernel/cpu/intel_cacheinfo.c 2013-07-26 18:54:47.000000000 +0000 ++++ linux-3.2.46/arch/x86/kernel/cpu/intel_cacheinfo.c 2013-07-26 19:22:54.000000000 +0000 +@@ -872,8 +872,7 @@ #include #include @@ -2466,7 +2506,7 @@ /* pointer to kobject for cpuX/cache */ static DEFINE_PER_CPU(struct kobject *, ici_cache_kobject); -@@ -1101,9 +1100,9 @@ err_out: +@@ -1101,9 +1100,9 @@ static DECLARE_BITMAP(cache_dev_map, NR_CPUS); /* Add/Remove cache interface for CPU device */ @@ -2478,7 +2518,7 @@ unsigned long i, j; struct _index_kobject *this_object; struct _cpuid4_info *this_leaf; -@@ -1115,7 +1114,7 @@ static int __cpuinit cache_add_dev(struc +@@ -1115,7 +1114,7 @@ retval = kobject_init_and_add(per_cpu(ici_cache_kobject, cpu), &ktype_percpu_entry, @@ -2487,7 +2527,7 @@ if (retval < 0) { cpuid4_cache_sysfs_exit(cpu); return retval; -@@ -1152,9 +1151,9 @@ static int __cpuinit cache_add_dev(struc +@@ -1152,9 +1151,9 @@ return 0; } @@ -2499,7 +2539,7 @@ unsigned long i; if (per_cpu(ici_cpuid4_info, cpu) == NULL) -@@ -1173,17 +1172,17 @@ static int __cpuinit cacheinfo_cpu_callb +@@ -1173,17 +1172,17 @@ unsigned long action, void *hcpu) { unsigned int cpu = (unsigned long)hcpu; @@ -2521,7 +2561,7 @@ break; } return NOTIFY_OK; -@@ -1202,9 +1201,9 @@ static int __cpuinit cache_sysfs_init(vo +@@ -1202,9 +1201,9 @@ for_each_online_cpu(i) { int err; @@ -2533,15 +2573,17 @@ if (err) return err; } ---- a/arch/x86/kernel/cpu/mcheck/mce-internal.h -+++ b/arch/x86/kernel/cpu/mcheck/mce-internal.h +Index: linux-3.2.46/arch/x86/kernel/cpu/mcheck/mce-internal.h +=================================================================== +--- linux-3.2.46.orig/arch/x86/kernel/cpu/mcheck/mce-internal.h 2013-07-26 18:54:47.000000000 +0000 ++++ linux-3.2.46/arch/x86/kernel/cpu/mcheck/mce-internal.h 2013-07-26 19:22:54.000000000 +0000 @@ -1,4 +1,4 @@ -#include +#include #include enum severity_level { -@@ -17,7 +17,7 @@ enum severity_level { +@@ -17,7 +17,7 @@ struct mce_bank { u64 ctl; /* subevents to enable */ unsigned char init; /* initialise bank? */ @@ -2550,8 +2592,10 @@ char attrname[ATTR_LEN]; /* attribute name */ }; ---- a/arch/x86/kernel/cpu/mcheck/mce.c -+++ b/arch/x86/kernel/cpu/mcheck/mce.c +Index: linux-3.2.46/arch/x86/kernel/cpu/mcheck/mce.c +=================================================================== +--- linux-3.2.46.orig/arch/x86/kernel/cpu/mcheck/mce.c 2013-07-26 18:54:47.000000000 +0000 ++++ linux-3.2.46/arch/x86/kernel/cpu/mcheck/mce.c 2013-07-26 19:22:54.000000000 +0000 @@ -19,7 +19,7 @@ #include #include @@ -2561,7 +2605,7 @@ #include #include #include -@@ -1776,7 +1776,7 @@ static struct syscore_ops mce_syscore_op +@@ -1776,7 +1776,7 @@ }; /* @@ -2570,7 +2614,7 @@ */ static void mce_cpu_restart(void *data) -@@ -1812,27 +1812,28 @@ static void mce_enable_ce(void *all) +@@ -1812,27 +1812,28 @@ __mcheck_cpu_init_timer(); } @@ -2604,7 +2648,7 @@ const char *buf, size_t size) { u64 new; -@@ -1847,14 +1848,14 @@ static ssize_t set_bank(struct sys_devic +@@ -1847,14 +1848,14 @@ } static ssize_t @@ -2621,7 +2665,7 @@ const char *buf, size_t siz) { char *p; -@@ -1869,8 +1870,8 @@ static ssize_t set_trigger(struct sys_de +@@ -1869,8 +1870,8 @@ return strlen(mce_helper) + !!p; } @@ -2632,7 +2676,7 @@ const char *buf, size_t size) { u64 new; -@@ -1893,8 +1894,8 @@ static ssize_t set_ignore_ce(struct sys_ +@@ -1893,8 +1894,8 @@ return size; } @@ -2643,7 +2687,7 @@ const char *buf, size_t size) { u64 new; -@@ -1916,108 +1917,107 @@ static ssize_t set_cmci_disabled(struct +@@ -1916,108 +1917,107 @@ return size; } @@ -2797,7 +2841,7 @@ } /* Make sure there are no machine checks on offlined CPUs. */ -@@ -2067,7 +2067,7 @@ mce_cpu_callback(struct notifier_block * +@@ -2067,7 +2067,7 @@ switch (action) { case CPU_ONLINE: case CPU_ONLINE_FROZEN: @@ -2806,7 +2850,7 @@ if (threshold_cpu_callback) threshold_cpu_callback(action, cpu); break; -@@ -2075,7 +2075,7 @@ mce_cpu_callback(struct notifier_block * +@@ -2075,7 +2075,7 @@ case CPU_DEAD_FROZEN: if (threshold_cpu_callback) threshold_cpu_callback(action, cpu); @@ -2815,7 +2859,7 @@ break; case CPU_DOWN_PREPARE: case CPU_DOWN_PREPARE_FROZEN: -@@ -2109,7 +2109,7 @@ static __init void mce_init_banks(void) +@@ -2109,7 +2109,7 @@ for (i = 0; i < banks; i++) { struct mce_bank *b = &mce_banks[i]; @@ -2824,7 +2868,7 @@ sysfs_attr_init(&a->attr); a->attr.name = b->attrname; -@@ -2129,16 +2129,16 @@ static __init int mcheck_init_device(voi +@@ -2129,16 +2129,16 @@ if (!mce_available(&boot_cpu_data)) return -EIO; @@ -2844,8 +2888,10 @@ if (err) return err; } ---- a/arch/x86/kernel/cpu/mcheck/mce_amd.c -+++ b/arch/x86/kernel/cpu/mcheck/mce_amd.c +Index: linux-3.2.46/arch/x86/kernel/cpu/mcheck/mce_amd.c +=================================================================== +--- linux-3.2.46.orig/arch/x86/kernel/cpu/mcheck/mce_amd.c 2013-07-26 18:54:47.000000000 +0000 ++++ linux-3.2.46/arch/x86/kernel/cpu/mcheck/mce_amd.c 2013-07-26 19:22:54.000000000 +0000 @@ -17,7 +17,6 @@ #include #include @@ -2854,7 +2900,7 @@ #include #include #include -@@ -578,7 +577,7 @@ static __cpuinit int threshold_create_ba +@@ -578,7 +577,7 @@ if (!b) goto out; @@ -2863,7 +2909,7 @@ b->kobj, name); if (err) goto out; -@@ -601,7 +600,7 @@ static __cpuinit int threshold_create_ba +@@ -601,7 +600,7 @@ goto out; } @@ -2872,7 +2918,7 @@ if (!b->kobj) goto out_free; -@@ -621,7 +620,7 @@ static __cpuinit int threshold_create_ba +@@ -621,7 +620,7 @@ if (i == cpu) continue; @@ -2881,7 +2927,7 @@ b->kobj, name); if (err) goto out; -@@ -699,7 +698,7 @@ static void threshold_remove_bank(unsign +@@ -699,7 +698,7 @@ #ifdef CONFIG_SMP /* sibling symlink */ if (shared_bank[bank] && b->blocks->cpu != cpu) { @@ -2890,7 +2936,7 @@ per_cpu(threshold_banks, cpu)[bank] = NULL; return; -@@ -711,7 +710,7 @@ static void threshold_remove_bank(unsign +@@ -711,7 +710,7 @@ if (i == cpu) continue; @@ -2899,8 +2945,10 @@ per_cpu(threshold_banks, i)[bank] = NULL; } ---- a/arch/x86/kernel/cpu/mcheck/therm_throt.c -+++ b/arch/x86/kernel/cpu/mcheck/therm_throt.c +Index: linux-3.2.46/arch/x86/kernel/cpu/mcheck/therm_throt.c +=================================================================== +--- linux-3.2.46.orig/arch/x86/kernel/cpu/mcheck/therm_throt.c 2013-07-26 18:54:47.000000000 +0000 ++++ linux-3.2.46/arch/x86/kernel/cpu/mcheck/therm_throt.c 2013-07-26 19:22:54.000000000 +0000 @@ -19,7 +19,6 @@ #include #include @@ -2909,7 +2957,7 @@ #include #include #include -@@ -69,16 +68,16 @@ static atomic_t therm_throt_en = ATOMIC_ +@@ -69,16 +68,16 @@ static u32 lvtthmr_init __read_mostly; #ifdef CONFIG_SYSFS @@ -2933,7 +2981,7 @@ char *buf) \ { \ unsigned int cpu = dev->id; \ -@@ -95,20 +94,20 @@ static ssize_t therm_throt_sysdev_show_# +@@ -95,20 +94,20 @@ return ret; \ } @@ -2963,7 +3011,7 @@ NULL }; -@@ -223,36 +222,36 @@ static int thresh_event_valid(int event) +@@ -223,36 +222,36 @@ #ifdef CONFIG_SYSFS /* Add/Remove thermal_throttle interface for CPU device: */ @@ -3010,7 +3058,7 @@ } /* Mutex protecting device creation against CPU hotplug: */ -@@ -265,16 +264,16 @@ thermal_throttle_cpu_callback(struct not +@@ -265,16 +264,16 @@ void *hcpu) { unsigned int cpu = (unsigned long)hcpu; @@ -3030,7 +3078,7 @@ mutex_unlock(&therm_cpu_lock); WARN_ON(err); break; -@@ -283,7 +282,7 @@ thermal_throttle_cpu_callback(struct not +@@ -283,7 +282,7 @@ case CPU_DEAD: case CPU_DEAD_FROZEN: mutex_lock(&therm_cpu_lock); @@ -3039,7 +3087,7 @@ mutex_unlock(&therm_cpu_lock); break; } -@@ -310,7 +309,7 @@ static __init int thermal_throttle_init_ +@@ -310,7 +309,7 @@ #endif /* connect live CPUs to sysfs */ for_each_online_cpu(cpu) { @@ -3048,9 +3096,11 @@ WARN_ON(err); } #ifdef CONFIG_HOTPLUG_CPU ---- a/arch/x86/kernel/microcode_core.c -+++ b/arch/x86/kernel/microcode_core.c -@@ -292,8 +292,8 @@ static int reload_for_cpu(int cpu) +Index: linux-3.2.46/arch/x86/kernel/microcode_core.c +=================================================================== +--- linux-3.2.46.orig/arch/x86/kernel/microcode_core.c 2013-07-26 18:54:47.000000000 +0000 ++++ linux-3.2.46/arch/x86/kernel/microcode_core.c 2013-07-26 19:22:54.000000000 +0000 +@@ -292,8 +292,8 @@ return err; } @@ -3061,7 +3111,7 @@ const char *buf, size_t size) { unsigned long val; -@@ -329,30 +329,30 @@ static ssize_t reload_store(struct sys_d +@@ -329,30 +329,30 @@ return ret; } @@ -3102,7 +3152,7 @@ NULL }; -@@ -416,16 +416,16 @@ static enum ucode_state microcode_update +@@ -416,16 +416,16 @@ return ustate; } @@ -3122,7 +3172,7 @@ if (err) return err; -@@ -435,22 +435,24 @@ static int mc_sysdev_add(struct sys_devi +@@ -435,22 +435,24 @@ return err; } @@ -3153,7 +3203,7 @@ }; /** -@@ -473,9 +475,9 @@ static __cpuinit int +@@ -473,9 +475,9 @@ mc_cpu_callback(struct notifier_block *nb, unsigned long action, void *hcpu) { unsigned int cpu = (unsigned long)hcpu; @@ -3165,7 +3215,7 @@ switch (action) { case CPU_ONLINE: case CPU_ONLINE_FROZEN: -@@ -483,13 +485,13 @@ mc_cpu_callback(struct notifier_block *n +@@ -483,13 +485,13 @@ case CPU_DOWN_FAILED: case CPU_DOWN_FAILED_FROZEN: pr_debug("CPU%d added\n", cpu); @@ -3181,7 +3231,7 @@ pr_debug("CPU%d removed\n", cpu); break; -@@ -534,7 +536,7 @@ static int __init microcode_init(void) +@@ -534,7 +536,7 @@ get_online_cpus(); mutex_lock(µcode_mutex); @@ -3190,7 +3240,7 @@ mutex_unlock(µcode_mutex); put_online_cpus(); -@@ -544,7 +546,7 @@ static int __init microcode_init(void) +@@ -544,7 +546,7 @@ error = microcode_dev_init(); if (error) @@ -3199,7 +3249,7 @@ register_syscore_ops(&mc_syscore_ops); register_hotcpu_notifier(&mc_cpu_notifier); -@@ -554,11 +556,11 @@ static int __init microcode_init(void) +@@ -554,11 +556,11 @@ return 0; @@ -3213,7 +3263,7 @@ mutex_unlock(µcode_mutex); put_online_cpus(); -@@ -580,7 +582,7 @@ static void __exit microcode_exit(void) +@@ -580,7 +582,7 @@ get_online_cpus(); mutex_lock(µcode_mutex); @@ -3222,9 +3272,11 @@ mutex_unlock(µcode_mutex); put_online_cpus(); ---- a/drivers/acpi/processor_driver.c -+++ b/drivers/acpi/processor_driver.c -@@ -446,7 +446,7 @@ static int __cpuinit acpi_processor_add( +Index: linux-3.2.46/drivers/acpi/processor_driver.c +=================================================================== +--- linux-3.2.46.orig/drivers/acpi/processor_driver.c 2013-07-26 18:54:47.000000000 +0000 ++++ linux-3.2.46/drivers/acpi/processor_driver.c 2013-07-26 19:22:54.000000000 +0000 +@@ -447,7 +447,7 @@ { struct acpi_processor *pr = NULL; int result = 0; @@ -3233,7 +3285,7 @@ pr = kzalloc(sizeof(struct acpi_processor), GFP_KERNEL); if (!pr) -@@ -491,8 +491,8 @@ static int __cpuinit acpi_processor_add( +@@ -492,8 +492,8 @@ per_cpu(processors, pr->id) = pr; @@ -3244,8 +3296,10 @@ result = -EFAULT; goto err_free_cpumask; } ---- a/drivers/acpi/processor_thermal.c -+++ b/drivers/acpi/processor_thermal.c +Index: linux-3.2.46/drivers/acpi/processor_thermal.c +=================================================================== +--- linux-3.2.46.orig/drivers/acpi/processor_thermal.c 2013-07-26 18:54:47.000000000 +0000 ++++ linux-3.2.46/drivers/acpi/processor_thermal.c 2013-07-26 19:22:54.000000000 +0000 @@ -30,7 +30,6 @@ #include #include @@ -3254,8 +3308,10 @@ #include ---- a/drivers/base/cpu.c -+++ b/drivers/base/cpu.c +Index: linux-3.2.46/drivers/base/cpu.c +=================================================================== +--- linux-3.2.46.orig/drivers/base/cpu.c 2013-07-26 18:54:47.000000000 +0000 ++++ linux-3.2.46/drivers/base/cpu.c 2013-07-26 19:22:54.000000000 +0000 @@ -1,8 +1,7 @@ /* - * drivers/base/cpu.c - basic CPU class support @@ -3321,7 +3377,7 @@ if (!ret) kobject_uevent(&dev->kobj, KOBJ_ONLINE); break; -@@ -60,44 +59,44 @@ static ssize_t __ref store_online(struct +@@ -60,44 +59,44 @@ ret = count; return ret; } @@ -3377,7 +3433,7 @@ #endif /* CONFIG_ARCH_CPU_PROBE_RELEASE */ #else /* ... !CONFIG_HOTPLUG_CPU */ -@@ -109,15 +108,15 @@ static inline void register_cpu_control( +@@ -109,15 +108,15 @@ #ifdef CONFIG_KEXEC #include @@ -3396,7 +3452,7 @@ /* * Might be reading other cpu's data based on which cpu read thread -@@ -129,7 +128,7 @@ static ssize_t show_crash_notes(struct s +@@ -129,7 +128,7 @@ rc = sprintf(buf, "%Lx\n", addr); return rc; } @@ -3405,7 +3461,7 @@ #endif /* -@@ -137,12 +136,12 @@ static SYSDEV_ATTR(crash_notes, 0400, sh +@@ -137,12 +136,12 @@ */ struct cpu_attr { @@ -3421,7 +3477,7 @@ char *buf) { struct cpu_attr *ca = container_of(attr, struct cpu_attr, attr); -@@ -153,10 +152,10 @@ static ssize_t show_cpus_attr(struct sys +@@ -153,10 +152,10 @@ return n; } @@ -3435,7 +3491,7 @@ static struct cpu_attr cpu_attrs[] = { _CPU_ATTR(online, &cpu_online_mask), _CPU_ATTR(possible, &cpu_possible_mask), -@@ -166,19 +165,19 @@ static struct cpu_attr cpu_attrs[] = { +@@ -166,19 +165,19 @@ /* * Print values for NR_CPUS and offlined cpus */ @@ -3460,7 +3516,7 @@ { int n = 0, len = PAGE_SIZE-2; cpumask_var_t offline; -@@ -205,7 +204,7 @@ static ssize_t print_cpus_offline(struct +@@ -205,7 +204,7 @@ n += snprintf(&buf[n], len - n, "\n"); return n; } @@ -3469,7 +3525,7 @@ /* * register_cpu - Setup a sysfs device for a CPU. -@@ -218,57 +217,66 @@ static SYSDEV_CLASS_ATTR(offline, 0444, +@@ -218,57 +217,66 @@ int __cpuinit register_cpu(struct cpu *cpu, int num) { int error; @@ -3562,9 +3618,11 @@ - &attr_offline, - NULL -}; ---- a/drivers/base/node.c -+++ b/drivers/base/node.c -@@ -317,12 +317,12 @@ struct node node_devices[MAX_NUMNODES]; +Index: linux-3.2.46/drivers/base/node.c +=================================================================== +--- linux-3.2.46.orig/drivers/base/node.c 2013-07-26 18:54:47.000000000 +0000 ++++ linux-3.2.46/drivers/base/node.c 2013-07-26 19:22:54.000000000 +0000 +@@ -317,12 +317,12 @@ int register_cpu_under_node(unsigned int cpu, unsigned int nid) { int ret; @@ -3579,7 +3637,7 @@ if (!obj) return 0; -@@ -339,12 +339,12 @@ int register_cpu_under_node(unsigned int +@@ -339,12 +339,12 @@ int unregister_cpu_under_node(unsigned int cpu, unsigned int nid) { @@ -3594,8 +3652,10 @@ if (!obj) return 0; ---- a/drivers/base/topology.c -+++ b/drivers/base/topology.c +Index: linux-3.2.46/drivers/base/topology.c +=================================================================== +--- linux-3.2.46.orig/drivers/base/topology.c 2013-07-26 18:54:47.000000000 +0000 ++++ linux-3.2.46/drivers/base/topology.c 2013-07-26 19:22:54.000000000 +0000 @@ -23,7 +23,6 @@ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. * @@ -3623,7 +3683,7 @@ { \ unsigned int cpu = dev->id; \ return sprintf(buf, "%d\n", topology_##name(cpu)); \ -@@ -65,16 +64,16 @@ static ssize_t show_cpumap(int type, con +@@ -65,16 +64,16 @@ #ifdef arch_provides_topology_pointers #define define_siblings_show_map(name) \ @@ -3644,7 +3704,7 @@ char *buf) \ { \ unsigned int cpu = dev->id; \ -@@ -83,15 +82,15 @@ static ssize_t show_##name##_list(struct +@@ -83,15 +82,15 @@ #else #define define_siblings_show_map(name) \ @@ -3664,7 +3724,7 @@ char *buf) \ { \ return show_cpumap(1, topology_##name(dev->id), buf); \ -@@ -124,16 +123,16 @@ define_one_ro_named(book_siblings_list, +@@ -124,16 +123,16 @@ #endif static struct attribute *default_attrs[] = { @@ -3690,7 +3750,7 @@ #endif NULL }; -@@ -146,16 +145,16 @@ static struct attribute_group topology_a +@@ -146,16 +145,16 @@ /* Add/Remove cpu_topology interface for CPU device */ static int __cpuinit topology_add_dev(unsigned int cpu) { @@ -3711,9 +3771,11 @@ } static int __cpuinit topology_cpu_callback(struct notifier_block *nfb, ---- a/drivers/cpufreq/cpufreq.c -+++ b/drivers/cpufreq/cpufreq.c -@@ -679,7 +679,7 @@ static struct kobj_type ktype_cpufreq = +Index: linux-3.2.46/drivers/cpufreq/cpufreq.c +=================================================================== +--- linux-3.2.46.orig/drivers/cpufreq/cpufreq.c 2013-07-26 18:54:47.000000000 +0000 ++++ linux-3.2.46/drivers/cpufreq/cpufreq.c 2013-07-26 19:22:54.000000000 +0000 +@@ -679,7 +679,7 @@ */ static int cpufreq_add_dev_policy(unsigned int cpu, struct cpufreq_policy *policy, @@ -3722,7 +3784,7 @@ { int ret = 0; #ifdef CONFIG_SMP -@@ -728,7 +728,7 @@ static int cpufreq_add_dev_policy(unsign +@@ -728,7 +728,7 @@ spin_unlock_irqrestore(&cpufreq_driver_lock, flags); pr_debug("CPU already managed, adding link\n"); @@ -3731,7 +3793,7 @@ &managed_policy->kobj, "cpufreq"); if (ret) -@@ -761,7 +761,7 @@ static int cpufreq_add_dev_symlink(unsig +@@ -761,7 +761,7 @@ for_each_cpu(j, policy->cpus) { struct cpufreq_policy *managed_policy; @@ -3740,7 +3802,7 @@ if (j == cpu) continue; -@@ -770,8 +770,8 @@ static int cpufreq_add_dev_symlink(unsig +@@ -770,8 +770,8 @@ pr_debug("CPU %u already managed, adding link\n", j); managed_policy = cpufreq_cpu_get(cpu); @@ -3751,7 +3813,7 @@ "cpufreq"); if (ret) { cpufreq_cpu_put(managed_policy); -@@ -783,7 +783,7 @@ static int cpufreq_add_dev_symlink(unsig +@@ -783,7 +783,7 @@ static int cpufreq_add_dev_interface(unsigned int cpu, struct cpufreq_policy *policy, @@ -3760,7 +3822,7 @@ { struct cpufreq_policy new_policy; struct freq_attr **drv_attr; -@@ -793,7 +793,7 @@ static int cpufreq_add_dev_interface(uns +@@ -793,7 +793,7 @@ /* prepare interface data */ ret = kobject_init_and_add(&policy->kobj, &ktype_cpufreq, @@ -3769,7 +3831,7 @@ if (ret) return ret; -@@ -866,9 +866,9 @@ err_out_kobj_put: +@@ -866,9 +866,9 @@ * with with cpu hotplugging and all hell will break loose. Tried to clean this * mess up, but more thorough testing is needed. - Mathieu */ @@ -3781,7 +3843,7 @@ int ret = 0, found = 0; struct cpufreq_policy *policy; unsigned long flags; -@@ -947,7 +947,7 @@ static int cpufreq_add_dev(struct sys_de +@@ -947,7 +947,7 @@ blocking_notifier_call_chain(&cpufreq_policy_notifier_list, CPUFREQ_START, policy); @@ -3790,7 +3852,7 @@ if (ret) { if (ret > 0) /* This is a managed cpu, symlink created, -@@ -956,7 +956,7 @@ static int cpufreq_add_dev(struct sys_de +@@ -956,7 +956,7 @@ goto err_unlock_policy; } @@ -3799,7 +3861,7 @@ if (ret) goto err_out_unregister; -@@ -999,15 +999,15 @@ module_out: +@@ -999,15 +999,15 @@ * Caller should already have policy_rwsem in write mode for this CPU. * This routine frees the rwsem before returning. */ @@ -3818,7 +3880,7 @@ unsigned int j; #endif -@@ -1032,7 +1032,7 @@ static int __cpufreq_remove_dev(struct s +@@ -1032,7 +1032,7 @@ pr_debug("removing link\n"); cpumask_clear_cpu(cpu, data->cpus); spin_unlock_irqrestore(&cpufreq_driver_lock, flags); @@ -3827,7 +3889,7 @@ cpufreq_cpu_put(data); unlock_policy_rwsem_write(cpu); sysfs_remove_link(kobj, "cpufreq"); -@@ -1071,8 +1071,8 @@ static int __cpufreq_remove_dev(struct s +@@ -1071,8 +1071,8 @@ strncpy(per_cpu(cpufreq_cpu_governor, j), data->governor->name, CPUFREQ_NAME_LEN); #endif @@ -3838,7 +3900,7 @@ unlock_policy_rwsem_write(cpu); sysfs_remove_link(kobj, "cpufreq"); lock_policy_rwsem_write(cpu); -@@ -1112,11 +1112,11 @@ static int __cpufreq_remove_dev(struct s +@@ -1112,11 +1112,11 @@ if (unlikely(cpumask_weight(data->cpus) > 1)) { /* first sibling now owns the new sysfs dir */ cpumask_clear_cpu(cpu, data->cpus); @@ -3852,7 +3914,7 @@ } #endif -@@ -1128,9 +1128,9 @@ static int __cpufreq_remove_dev(struct s +@@ -1128,9 +1128,9 @@ } @@ -3864,7 +3926,7 @@ int retval; if (cpu_is_offline(cpu)) -@@ -1139,7 +1139,7 @@ static int cpufreq_remove_dev(struct sys +@@ -1139,7 +1139,7 @@ if (unlikely(lock_policy_rwsem_write(cpu))) BUG(); @@ -3873,7 +3935,7 @@ return retval; } -@@ -1271,9 +1271,11 @@ out: +@@ -1271,9 +1271,11 @@ } EXPORT_SYMBOL(cpufreq_get); @@ -3888,7 +3950,7 @@ }; -@@ -1765,25 +1767,25 @@ static int __cpuinit cpufreq_cpu_callbac +@@ -1765,25 +1767,25 @@ unsigned long action, void *hcpu) { unsigned int cpu = (unsigned long)hcpu; @@ -3920,7 +3982,7 @@ break; } } -@@ -1830,8 +1832,7 @@ int cpufreq_register_driver(struct cpufr +@@ -1830,8 +1832,7 @@ cpufreq_driver = driver_data; spin_unlock_irqrestore(&cpufreq_driver_lock, flags); @@ -3930,7 +3992,7 @@ if (ret) goto err_null_driver; -@@ -1850,7 +1851,7 @@ int cpufreq_register_driver(struct cpufr +@@ -1850,7 +1851,7 @@ if (ret) { pr_debug("no CPU initialized for driver %s\n", driver_data->name); @@ -3939,7 +4001,7 @@ } } -@@ -1858,9 +1859,8 @@ int cpufreq_register_driver(struct cpufr +@@ -1858,9 +1859,8 @@ pr_debug("driver %s up and running\n", driver_data->name); return 0; @@ -3951,7 +4013,7 @@ err_null_driver: spin_lock_irqsave(&cpufreq_driver_lock, flags); cpufreq_driver = NULL; -@@ -1887,7 +1887,7 @@ int cpufreq_unregister_driver(struct cpu +@@ -1887,7 +1887,7 @@ pr_debug("unregistering driver %s\n", driver->name); @@ -3960,7 +4022,7 @@ unregister_hotcpu_notifier(&cpufreq_cpu_notifier); spin_lock_irqsave(&cpufreq_driver_lock, flags); -@@ -1907,8 +1907,7 @@ static int __init cpufreq_core_init(void +@@ -1907,8 +1907,7 @@ init_rwsem(&per_cpu(cpu_policy_rwsem, cpu)); } @@ -3970,8 +4032,10 @@ BUG_ON(!cpufreq_global_kobject); register_syscore_ops(&cpufreq_syscore_ops); ---- a/drivers/cpufreq/cpufreq_stats.c -+++ b/drivers/cpufreq/cpufreq_stats.c +Index: linux-3.2.46/drivers/cpufreq/cpufreq_stats.c +=================================================================== +--- linux-3.2.46.orig/drivers/cpufreq/cpufreq_stats.c 2013-07-26 18:54:47.000000000 +0000 ++++ linux-3.2.46/drivers/cpufreq/cpufreq_stats.c 2013-07-26 19:22:54.000000000 +0000 @@ -11,7 +11,6 @@ #include @@ -3980,9 +4044,11 @@ #include #include #include ---- a/drivers/cpuidle/cpuidle.c -+++ b/drivers/cpuidle/cpuidle.c -@@ -291,10 +291,10 @@ EXPORT_SYMBOL_GPL(cpuidle_disable_device +Index: linux-3.2.46/drivers/cpuidle/cpuidle.c +=================================================================== +--- linux-3.2.46.orig/drivers/cpuidle/cpuidle.c 2013-07-26 18:54:47.000000000 +0000 ++++ linux-3.2.46/drivers/cpuidle/cpuidle.c 2013-07-26 19:22:54.000000000 +0000 +@@ -291,10 +291,10 @@ static int __cpuidle_register_device(struct cpuidle_device *dev) { int ret; @@ -3995,7 +4061,7 @@ return -EINVAL; if (!try_module_get(cpuidle_driver->owner)) return -EINVAL; -@@ -303,7 +303,7 @@ static int __cpuidle_register_device(str +@@ -303,7 +303,7 @@ per_cpu(cpuidle_devices, dev->cpu) = dev; list_add(&dev->device_list, &cpuidle_detected_devices); @@ -4004,7 +4070,7 @@ module_put(cpuidle_driver->owner); return ret; } -@@ -344,7 +344,7 @@ EXPORT_SYMBOL_GPL(cpuidle_register_devic +@@ -344,7 +344,7 @@ */ void cpuidle_unregister_device(struct cpuidle_device *dev) { @@ -4013,7 +4079,7 @@ struct cpuidle_driver *cpuidle_driver = cpuidle_get_driver(); if (dev->registered == 0) -@@ -354,7 +354,7 @@ void cpuidle_unregister_device(struct cp +@@ -354,7 +354,7 @@ cpuidle_disable_device(dev); @@ -4022,7 +4088,7 @@ list_del(&dev->device_list); wait_for_completion(&dev->kobj_unregister); per_cpu(cpuidle_devices, dev->cpu) = NULL; -@@ -411,7 +411,7 @@ static int __init cpuidle_init(void) +@@ -411,7 +411,7 @@ if (cpuidle_disabled()) return -ENODEV; @@ -4031,8 +4097,10 @@ if (ret) return ret; ---- a/drivers/cpuidle/cpuidle.h -+++ b/drivers/cpuidle/cpuidle.h +Index: linux-3.2.46/drivers/cpuidle/cpuidle.h +=================================================================== +--- linux-3.2.46.orig/drivers/cpuidle/cpuidle.h 2013-07-26 18:54:47.000000000 +0000 ++++ linux-3.2.46/drivers/cpuidle/cpuidle.h 2013-07-26 19:22:54.000000000 +0000 @@ -5,7 +5,7 @@ #ifndef __DRIVER_CPUIDLE_H #define __DRIVER_CPUIDLE_H @@ -4042,7 +4110,7 @@ /* For internal use only */ extern struct cpuidle_governor *cpuidle_curr_governor; -@@ -23,11 +23,11 @@ extern void cpuidle_uninstall_idle_handl +@@ -23,11 +23,11 @@ extern int cpuidle_switch_governor(struct cpuidle_governor *gov); /* sysfs */ @@ -4058,9 +4126,11 @@ +extern void cpuidle_remove_sysfs(struct device *dev); #endif /* __DRIVER_CPUIDLE_H */ ---- a/drivers/cpuidle/sysfs.c -+++ b/drivers/cpuidle/sysfs.c -@@ -22,8 +22,8 @@ static int __init cpuidle_sysfs_setup(ch +Index: linux-3.2.46/drivers/cpuidle/sysfs.c +=================================================================== +--- linux-3.2.46.orig/drivers/cpuidle/sysfs.c 2013-07-26 18:54:47.000000000 +0000 ++++ linux-3.2.46/drivers/cpuidle/sysfs.c 2013-07-26 19:22:54.000000000 +0000 +@@ -22,8 +22,8 @@ } __setup("cpuidle_sysfs_switch", cpuidle_sysfs_setup); @@ -4071,7 +4141,7 @@ char *buf) { ssize_t i = 0; -@@ -42,8 +42,8 @@ out: +@@ -42,8 +42,8 @@ return i; } @@ -4082,7 +4152,7 @@ char *buf) { ssize_t ret; -@@ -59,8 +59,8 @@ static ssize_t show_current_driver(struc +@@ -59,8 +59,8 @@ return ret; } @@ -4093,7 +4163,7 @@ char *buf) { ssize_t ret; -@@ -75,8 +75,8 @@ static ssize_t show_current_governor(str +@@ -75,8 +75,8 @@ return ret; } @@ -4104,7 +4174,7 @@ const char *buf, size_t count) { char gov_name[CPUIDLE_NAME_LEN]; -@@ -109,50 +109,48 @@ static ssize_t store_current_governor(st +@@ -109,50 +109,48 @@ return count; } @@ -4178,7 +4248,7 @@ } struct cpuidle_attr { -@@ -365,16 +363,16 @@ void cpuidle_remove_state_sysfs(struct c +@@ -365,16 +363,16 @@ /** * cpuidle_add_sysfs - creates a sysfs instance for the target device @@ -4199,7 +4269,7 @@ "cpuidle"); if (!error) kobject_uevent(&dev->kobj, KOBJ_ADD); -@@ -383,11 +381,11 @@ int cpuidle_add_sysfs(struct sys_device +@@ -383,11 +381,11 @@ /** * cpuidle_remove_sysfs - deletes a sysfs instance on the target device @@ -4214,8 +4284,10 @@ struct cpuidle_device *dev; dev = per_cpu(cpuidle_devices, cpu); ---- a/drivers/s390/char/sclp_config.c -+++ b/drivers/s390/char/sclp_config.c +Index: linux-3.2.46/drivers/s390/char/sclp_config.c +=================================================================== +--- linux-3.2.46.orig/drivers/s390/char/sclp_config.c 2013-07-26 18:54:47.000000000 +0000 ++++ linux-3.2.46/drivers/s390/char/sclp_config.c 2013-07-26 19:22:54.000000000 +0000 @@ -11,7 +11,7 @@ #include #include @@ -4225,7 +4297,7 @@ #include #include -@@ -31,14 +31,14 @@ static struct work_struct sclp_cpu_chang +@@ -31,14 +31,14 @@ static void sclp_cpu_capability_notify(struct work_struct *work) { int cpu; @@ -4243,8 +4315,10 @@ } put_online_cpus(); } ---- a/include/linux/cpu.h -+++ b/include/linux/cpu.h +Index: linux-3.2.46/include/linux/cpu.h +=================================================================== +--- linux-3.2.46.orig/include/linux/cpu.h 2013-07-26 18:54:47.000000000 +0000 ++++ linux-3.2.46/include/linux/cpu.h 2013-07-26 19:22:54.000000000 +0000 @@ -14,7 +14,7 @@ #ifndef _LINUX_CPU_H_ #define _LINUX_CPU_H_ @@ -4281,7 +4355,7 @@ #ifdef CONFIG_HOTPLUG_CPU extern void unregister_cpu(struct cpu *cpu); -@@ -161,7 +161,7 @@ static inline void cpu_maps_update_done( +@@ -161,7 +161,7 @@ } #endif /* CONFIG_SMP */ @@ -4290,9 +4364,11 @@ #ifdef CONFIG_HOTPLUG_CPU /* Stop CPUs going up and down. */ ---- a/kernel/sched.c -+++ b/kernel/sched.c -@@ -8139,54 +8139,52 @@ static ssize_t sched_power_savings_store +Index: linux-3.2.46/kernel/sched.c +=================================================================== +--- linux-3.2.46.orig/kernel/sched.c 2013-07-26 18:54:47.000000000 +0000 ++++ linux-3.2.46/kernel/sched.c 2013-07-26 19:22:54.000000000 +0000 +@@ -8151,54 +8151,52 @@ } #ifdef CONFIG_SCHED_MC diff -Nru linux-3.2.46/debian/patches/features/all/cpu-devices/cpu-Do-not-return-errors-from-cpu_dev_init-which-wil.patch linux-3.2.46/debian/patches/features/all/cpu-devices/cpu-Do-not-return-errors-from-cpu_dev_init-which-wil.patch --- linux-3.2.46/debian/patches/features/all/cpu-devices/cpu-Do-not-return-errors-from-cpu_dev_init-which-wil.patch 2013-02-24 03:52:33.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/cpu-devices/cpu-Do-not-return-errors-from-cpu_dev_init-which-wil.patch 2013-07-26 19:23:00.000000000 +0000 @@ -19,8 +19,10 @@ drivers/base/cpu.c | 13 +++++-------- 2 files changed, 6 insertions(+), 9 deletions(-) ---- a/drivers/base/base.h -+++ b/drivers/base/base.h +Index: linux-3.2.46/drivers/base/base.h +=================================================================== +--- linux-3.2.46.orig/drivers/base/base.h 2013-07-26 19:22:51.000000000 +0000 ++++ linux-3.2.46/drivers/base/base.h 2013-07-26 19:22:59.000000000 +0000 @@ -94,7 +94,7 @@ static inline int hypervisor_init(void) { return 0; } #endif @@ -30,8 +32,10 @@ extern int bus_add_device(struct device *dev); extern void bus_probe_device(struct device *dev); ---- a/drivers/base/cpu.c -+++ b/drivers/base/cpu.c +Index: linux-3.2.46/drivers/base/cpu.c +=================================================================== +--- linux-3.2.46.orig/drivers/base/cpu.c 2013-07-26 19:22:54.000000000 +0000 ++++ linux-3.2.46/drivers/base/cpu.c 2013-07-26 19:22:59.000000000 +0000 @@ -2,6 +2,7 @@ * CPU subsystem support */ diff -Nru linux-3.2.46/debian/patches/features/all/cpu-devices/cpufreq-Add-support-for-x86-cpuinfo-auto-loading-v4.patch linux-3.2.46/debian/patches/features/all/cpu-devices/cpufreq-Add-support-for-x86-cpuinfo-auto-loading-v4.patch --- linux-3.2.46/debian/patches/features/all/cpu-devices/cpufreq-Add-support-for-x86-cpuinfo-auto-loading-v4.patch 2013-02-24 03:52:33.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/cpu-devices/cpufreq-Add-support-for-x86-cpuinfo-auto-loading-v4.patch 2013-07-26 19:23:25.000000000 +0000 @@ -43,11 +43,11 @@ drivers/cpufreq/speedstep-smi.c | 15 +++++++++++++++ 15 files changed, 142 insertions(+), 61 deletions(-) -diff --git a/drivers/cpufreq/cpufreq-nforce2.c b/drivers/cpufreq/cpufreq-nforce2.c -index 7bac808..13d311e 100644 ---- a/drivers/cpufreq/cpufreq-nforce2.c -+++ b/drivers/cpufreq/cpufreq-nforce2.c -@@ -385,6 +385,14 @@ static struct cpufreq_driver nforce2_driver = { +Index: linux-3.2.46/drivers/cpufreq/cpufreq-nforce2.c +=================================================================== +--- linux-3.2.46.orig/drivers/cpufreq/cpufreq-nforce2.c 2013-07-26 18:54:37.000000000 +0000 ++++ linux-3.2.46/drivers/cpufreq/cpufreq-nforce2.c 2013-07-26 19:23:23.000000000 +0000 +@@ -385,6 +385,14 @@ .owner = THIS_MODULE, }; @@ -62,10 +62,10 @@ /** * nforce2_detect_chipset - detect the Southbridge which contains FSB PLL logic * -diff --git a/drivers/cpufreq/e_powersaver.c b/drivers/cpufreq/e_powersaver.c -index 4bd6815..3fffbe6 100644 ---- a/drivers/cpufreq/e_powersaver.c -+++ b/drivers/cpufreq/e_powersaver.c +Index: linux-3.2.46/drivers/cpufreq/e_powersaver.c +=================================================================== +--- linux-3.2.46.orig/drivers/cpufreq/e_powersaver.c 2013-07-26 18:54:37.000000000 +0000 ++++ linux-3.2.46/drivers/cpufreq/e_powersaver.c 2013-07-26 19:23:23.000000000 +0000 @@ -16,6 +16,7 @@ #include #include @@ -74,7 +74,7 @@ #include #include -@@ -437,18 +438,19 @@ static struct cpufreq_driver eps_driver = { +@@ -437,18 +438,19 @@ .attr = eps_attr, }; @@ -103,10 +103,10 @@ if (cpufreq_register_driver(&eps_driver)) return -EINVAL; return 0; -diff --git a/drivers/cpufreq/elanfreq.c b/drivers/cpufreq/elanfreq.c -index c587db4..960671f 100644 ---- a/drivers/cpufreq/elanfreq.c -+++ b/drivers/cpufreq/elanfreq.c +Index: linux-3.2.46/drivers/cpufreq/elanfreq.c +=================================================================== +--- linux-3.2.46.orig/drivers/cpufreq/elanfreq.c 2013-07-26 18:54:37.000000000 +0000 ++++ linux-3.2.46/drivers/cpufreq/elanfreq.c 2013-07-26 19:23:23.000000000 +0000 @@ -23,6 +23,7 @@ #include #include @@ -115,7 +115,7 @@ #include #include #include -@@ -277,17 +278,16 @@ static struct cpufreq_driver elanfreq_driver = { +@@ -277,17 +278,16 @@ .attr = elanfreq_attr, }; @@ -139,10 +139,10 @@ return cpufreq_register_driver(&elanfreq_driver); } -diff --git a/drivers/cpufreq/gx-suspmod.c b/drivers/cpufreq/gx-suspmod.c -index ffe1f2c..5a06c0b 100644 ---- a/drivers/cpufreq/gx-suspmod.c -+++ b/drivers/cpufreq/gx-suspmod.c +Index: linux-3.2.46/drivers/cpufreq/gx-suspmod.c +=================================================================== +--- linux-3.2.46.orig/drivers/cpufreq/gx-suspmod.c 2013-07-26 18:54:37.000000000 +0000 ++++ linux-3.2.46/drivers/cpufreq/gx-suspmod.c 2013-07-26 19:23:23.000000000 +0000 @@ -82,6 +82,7 @@ #include #include @@ -151,7 +151,7 @@ #include /* PCI config registers, all at F0 */ -@@ -171,6 +172,7 @@ static struct pci_device_id gx_chipset_tbl[] __initdata = { +@@ -171,6 +172,7 @@ { PCI_VDEVICE(CYRIX, PCI_DEVICE_ID_CYRIX_5510), }, { 0, }, }; @@ -159,7 +159,7 @@ static void gx_write_byte(int reg, int value) { -@@ -185,13 +187,6 @@ static __init struct pci_dev *gx_detect_chipset(void) +@@ -185,13 +187,6 @@ { struct pci_dev *gx_pci = NULL; @@ -173,10 +173,10 @@ /* detect which companion chip is used */ for_each_pci_dev(gx_pci) { if ((pci_match_id(gx_chipset_tbl, gx_pci)) != NULL) -diff --git a/drivers/cpufreq/longhaul.c b/drivers/cpufreq/longhaul.c -index f47d26e..53ddbc7 100644 ---- a/drivers/cpufreq/longhaul.c -+++ b/drivers/cpufreq/longhaul.c +Index: linux-3.2.46/drivers/cpufreq/longhaul.c +=================================================================== +--- linux-3.2.46.orig/drivers/cpufreq/longhaul.c 2013-07-26 18:54:37.000000000 +0000 ++++ linux-3.2.46/drivers/cpufreq/longhaul.c 2013-07-26 19:23:23.000000000 +0000 @@ -35,6 +35,7 @@ #include @@ -185,7 +185,7 @@ #include #include "longhaul.h" -@@ -951,12 +952,17 @@ static struct cpufreq_driver longhaul_driver = { +@@ -951,12 +952,17 @@ .attr = longhaul_attr, }; @@ -204,10 +204,10 @@ return -ENODEV; #ifdef CONFIG_SMP -diff --git a/drivers/cpufreq/longrun.c b/drivers/cpufreq/longrun.c -index 34ea359..8bc9f5f 100644 ---- a/drivers/cpufreq/longrun.c -+++ b/drivers/cpufreq/longrun.c +Index: linux-3.2.46/drivers/cpufreq/longrun.c +=================================================================== +--- linux-3.2.46.orig/drivers/cpufreq/longrun.c 2013-07-26 18:54:37.000000000 +0000 ++++ linux-3.2.46/drivers/cpufreq/longrun.c 2013-07-26 19:23:23.000000000 +0000 @@ -14,6 +14,7 @@ #include @@ -216,7 +216,7 @@ static struct cpufreq_driver longrun_driver; -@@ -288,6 +289,12 @@ static struct cpufreq_driver longrun_driver = { +@@ -288,6 +289,12 @@ .owner = THIS_MODULE, }; @@ -229,7 +229,7 @@ /** * longrun_init - initializes the Transmeta Crusoe LongRun CPUFreq driver -@@ -296,12 +303,8 @@ static struct cpufreq_driver longrun_driver = { +@@ -296,12 +303,8 @@ */ static int __init longrun_init(void) { @@ -243,10 +243,10 @@ return cpufreq_register_driver(&longrun_driver); } -diff --git a/drivers/cpufreq/p4-clockmod.c b/drivers/cpufreq/p4-clockmod.c -index 6be3e07..827629c9 100644 ---- a/drivers/cpufreq/p4-clockmod.c -+++ b/drivers/cpufreq/p4-clockmod.c +Index: linux-3.2.46/drivers/cpufreq/p4-clockmod.c +=================================================================== +--- linux-3.2.46.orig/drivers/cpufreq/p4-clockmod.c 2013-07-26 18:54:37.000000000 +0000 ++++ linux-3.2.46/drivers/cpufreq/p4-clockmod.c 2013-07-26 19:23:23.000000000 +0000 @@ -31,6 +31,7 @@ #include #include @@ -255,7 +255,7 @@ #include "speedstep-lib.h" -@@ -289,21 +290,25 @@ static struct cpufreq_driver p4clockmod_driver = { +@@ -289,21 +290,25 @@ .attr = p4clockmod_attr, }; @@ -287,10 +287,10 @@ return -ENODEV; ret = cpufreq_register_driver(&p4clockmod_driver); -diff --git a/drivers/cpufreq/powernow-k6.c b/drivers/cpufreq/powernow-k6.c -index b3379d6..54dd031 100644 ---- a/drivers/cpufreq/powernow-k6.c -+++ b/drivers/cpufreq/powernow-k6.c +Index: linux-3.2.46/drivers/cpufreq/powernow-k6.c +=================================================================== +--- linux-3.2.46.orig/drivers/cpufreq/powernow-k6.c 2013-07-26 18:54:37.000000000 +0000 ++++ linux-3.2.46/drivers/cpufreq/powernow-k6.c 2013-07-26 19:23:23.000000000 +0000 @@ -16,6 +16,7 @@ #include #include @@ -299,7 +299,7 @@ #include #define POWERNOW_IOPORT 0xfff0 /* it doesn't matter where, as long -@@ -210,6 +211,12 @@ static struct cpufreq_driver powernow_k6_driver = { +@@ -210,6 +211,12 @@ .attr = powernow_k6_attr, }; @@ -312,7 +312,7 @@ /** * powernow_k6_init - initializes the k6 PowerNow! CPUFreq driver -@@ -220,10 +227,7 @@ static struct cpufreq_driver powernow_k6_driver = { +@@ -220,10 +227,7 @@ */ static int __init powernow_k6_init(void) { @@ -324,10 +324,10 @@ return -ENODEV; if (!request_region(POWERNOW_IOPORT, 16, "PowerNow!")) { -diff --git a/drivers/cpufreq/powernow-k7.c b/drivers/cpufreq/powernow-k7.c -index d71d9f3..501d167 100644 ---- a/drivers/cpufreq/powernow-k7.c -+++ b/drivers/cpufreq/powernow-k7.c +Index: linux-3.2.46/drivers/cpufreq/powernow-k7.c +=================================================================== +--- linux-3.2.46.orig/drivers/cpufreq/powernow-k7.c 2013-07-26 18:54:37.000000000 +0000 ++++ linux-3.2.46/drivers/cpufreq/powernow-k7.c 2013-07-26 19:23:23.000000000 +0000 @@ -28,6 +28,7 @@ #include /* Needed for recalibrate_cpu_khz() */ #include @@ -336,7 +336,7 @@ #ifdef CONFIG_X86_POWERNOW_K7_ACPI #include -@@ -110,18 +111,19 @@ static int check_fsb(unsigned int fsbspeed) +@@ -110,18 +111,19 @@ return delta < 5; } @@ -362,11 +362,11 @@ /* Get maximum capabilities */ maxei = cpuid_eax(0x80000000); -diff --git a/drivers/cpufreq/powernow-k8.c b/drivers/cpufreq/powernow-k8.c -index 8f9b2ce..c0e8164 100644 ---- a/drivers/cpufreq/powernow-k8.c -+++ b/drivers/cpufreq/powernow-k8.c -@@ -40,6 +40,7 @@ +Index: linux-3.2.46/drivers/cpufreq/powernow-k8.c +=================================================================== +--- linux-3.2.46.orig/drivers/cpufreq/powernow-k8.c 2013-07-26 18:54:37.000000000 +0000 ++++ linux-3.2.46/drivers/cpufreq/powernow-k8.c 2013-07-26 19:23:23.000000000 +0000 +@@ -36,6 +36,7 @@ #include #include @@ -374,7 +374,7 @@ #include #include -@@ -520,6 +521,15 @@ static int core_voltage_post_transition(struct powernow_k8_data *data, +@@ -516,6 +517,15 @@ return 0; } @@ -390,7 +390,7 @@ static void check_supported_cpu(void *_rc) { u32 eax, ebx, ecx, edx; -@@ -527,13 +537,7 @@ static void check_supported_cpu(void *_rc) +@@ -523,13 +533,7 @@ *rc = -ENODEV; @@ -404,7 +404,7 @@ if ((eax & CPUID_XFAM) == CPUID_XFAM_K8) { if (((eax & CPUID_USE_XFAM_XMOD) != CPUID_USE_XFAM_XMOD) || -@@ -1553,6 +1557,9 @@ static int __cpuinit powernowk8_init(void) +@@ -1548,6 +1552,9 @@ unsigned int i, supported_cpus = 0, cpu; int rv; @@ -414,10 +414,10 @@ for_each_online_cpu(i) { int rc; smp_call_function_single(i, check_supported_cpu, &rc, 1); -diff --git a/drivers/cpufreq/sc520_freq.c b/drivers/cpufreq/sc520_freq.c -index 1e205e6..e42e073 100644 ---- a/drivers/cpufreq/sc520_freq.c -+++ b/drivers/cpufreq/sc520_freq.c +Index: linux-3.2.46/drivers/cpufreq/sc520_freq.c +=================================================================== +--- linux-3.2.46.orig/drivers/cpufreq/sc520_freq.c 2013-07-26 18:54:37.000000000 +0000 ++++ linux-3.2.46/drivers/cpufreq/sc520_freq.c 2013-07-26 19:23:23.000000000 +0000 @@ -22,6 +22,7 @@ #include #include @@ -426,7 +426,7 @@ #include #define MMCR_BASE 0xfffef000 /* The default base address */ -@@ -150,18 +151,19 @@ static struct cpufreq_driver sc520_freq_driver = { +@@ -150,18 +151,19 @@ .attr = sc520_freq_attr, }; @@ -452,10 +452,10 @@ cpuctl = ioremap((unsigned long)(MMCR_BASE + OFFS_CPUCTL), 1); if (!cpuctl) { printk(KERN_ERR "sc520_freq: error: failed to remap memory\n"); -diff --git a/drivers/cpufreq/speedstep-centrino.c b/drivers/cpufreq/speedstep-centrino.c -index 6ea3455..3a953d5 100644 ---- a/drivers/cpufreq/speedstep-centrino.c -+++ b/drivers/cpufreq/speedstep-centrino.c +Index: linux-3.2.46/drivers/cpufreq/speedstep-centrino.c +=================================================================== +--- linux-3.2.46.orig/drivers/cpufreq/speedstep-centrino.c 2013-07-26 18:54:37.000000000 +0000 ++++ linux-3.2.46/drivers/cpufreq/speedstep-centrino.c 2013-07-26 19:23:23.000000000 +0000 @@ -25,6 +25,7 @@ #include #include @@ -464,7 +464,7 @@ #define PFX "speedstep-centrino: " #define MAINTAINER "cpufreq@vger.kernel.org" -@@ -595,6 +596,24 @@ static struct cpufreq_driver centrino_driver = { +@@ -595,6 +596,24 @@ .owner = THIS_MODULE, }; @@ -489,7 +489,7 @@ /** * centrino_init - initializes the Enhanced SpeedStep CPUFreq driver -@@ -612,11 +631,8 @@ static struct cpufreq_driver centrino_driver = { +@@ -612,11 +631,8 @@ */ static int __init centrino_init(void) { @@ -502,10 +502,10 @@ return cpufreq_register_driver(¢rino_driver); } -diff --git a/drivers/cpufreq/speedstep-ich.c b/drivers/cpufreq/speedstep-ich.c -index a748ce7..7432b3a 100644 ---- a/drivers/cpufreq/speedstep-ich.c -+++ b/drivers/cpufreq/speedstep-ich.c +Index: linux-3.2.46/drivers/cpufreq/speedstep-ich.c +=================================================================== +--- linux-3.2.46.orig/drivers/cpufreq/speedstep-ich.c 2013-07-26 18:54:37.000000000 +0000 ++++ linux-3.2.46/drivers/cpufreq/speedstep-ich.c 2013-07-26 19:23:23.000000000 +0000 @@ -25,6 +25,8 @@ #include #include @@ -515,7 +515,7 @@ #include "speedstep-lib.h" -@@ -388,6 +390,16 @@ static struct cpufreq_driver speedstep_driver = { +@@ -388,6 +390,16 @@ .attr = speedstep_attr, }; @@ -532,7 +532,7 @@ /** * speedstep_init - initializes the SpeedStep CPUFreq driver -@@ -398,6 +410,9 @@ static struct cpufreq_driver speedstep_driver = { +@@ -398,6 +410,9 @@ */ static int __init speedstep_init(void) { @@ -542,11 +542,11 @@ /* detect processor */ speedstep_processor = speedstep_detect_processor(); if (!speedstep_processor) { -diff --git a/drivers/cpufreq/speedstep-lib.c b/drivers/cpufreq/speedstep-lib.c -index 8af2d2f..7047821 100644 ---- a/drivers/cpufreq/speedstep-lib.c -+++ b/drivers/cpufreq/speedstep-lib.c -@@ -249,6 +249,7 @@ EXPORT_SYMBOL_GPL(speedstep_get_frequency); +Index: linux-3.2.46/drivers/cpufreq/speedstep-lib.c +=================================================================== +--- linux-3.2.46.orig/drivers/cpufreq/speedstep-lib.c 2013-07-26 18:54:37.000000000 +0000 ++++ linux-3.2.46/drivers/cpufreq/speedstep-lib.c 2013-07-26 19:23:23.000000000 +0000 +@@ -249,6 +249,7 @@ * DETECT SPEEDSTEP-CAPABLE PROCESSOR * *********************************************************************/ @@ -554,10 +554,10 @@ unsigned int speedstep_detect_processor(void) { struct cpuinfo_x86 *c = &cpu_data(0); -diff --git a/drivers/cpufreq/speedstep-smi.c b/drivers/cpufreq/speedstep-smi.c -index c76ead3..6a457fc 100644 ---- a/drivers/cpufreq/speedstep-smi.c -+++ b/drivers/cpufreq/speedstep-smi.c +Index: linux-3.2.46/drivers/cpufreq/speedstep-smi.c +=================================================================== +--- linux-3.2.46.orig/drivers/cpufreq/speedstep-smi.c 2013-07-26 18:54:37.000000000 +0000 ++++ linux-3.2.46/drivers/cpufreq/speedstep-smi.c 2013-07-26 19:23:23.000000000 +0000 @@ -20,6 +20,7 @@ #include #include @@ -566,7 +566,7 @@ #include "speedstep-lib.h" -@@ -379,6 +380,17 @@ static struct cpufreq_driver speedstep_driver = { +@@ -379,6 +380,17 @@ .attr = speedstep_attr, }; @@ -584,7 +584,7 @@ /** * speedstep_init - initializes the SpeedStep CPUFreq driver * -@@ -388,6 +400,9 @@ static struct cpufreq_driver speedstep_driver = { +@@ -388,6 +400,9 @@ */ static int __init speedstep_init(void) { diff -Nru linux-3.2.46/debian/patches/features/all/cpu-devices/cpufreq-gx-Fix-the-compile-error.patch linux-3.2.46/debian/patches/features/all/cpu-devices/cpufreq-gx-Fix-the-compile-error.patch --- linux-3.2.46/debian/patches/features/all/cpu-devices/cpufreq-gx-Fix-the-compile-error.patch 2013-02-24 03:52:33.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/cpu-devices/cpufreq-gx-Fix-the-compile-error.patch 2013-07-26 19:23:35.000000000 +0000 @@ -13,11 +13,11 @@ drivers/cpufreq/gx-suspmod.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -diff --git a/drivers/cpufreq/gx-suspmod.c b/drivers/cpufreq/gx-suspmod.c -index 5a06c0b..456bee0 100644 ---- a/drivers/cpufreq/gx-suspmod.c -+++ b/drivers/cpufreq/gx-suspmod.c -@@ -172,7 +172,7 @@ static struct pci_device_id gx_chipset_tbl[] __initdata = { +Index: linux-3.2.46/drivers/cpufreq/gx-suspmod.c +=================================================================== +--- linux-3.2.46.orig/drivers/cpufreq/gx-suspmod.c 2013-07-26 19:23:23.000000000 +0000 ++++ linux-3.2.46/drivers/cpufreq/gx-suspmod.c 2013-07-26 19:23:35.000000000 +0000 +@@ -172,7 +172,7 @@ { PCI_VDEVICE(CYRIX, PCI_DEVICE_ID_CYRIX_5510), }, { 0, }, }; diff -Nru linux-3.2.46/debian/patches/features/all/cpu-devices/cpufreq-Longhaul-Disable-driver-by-default.patch linux-3.2.46/debian/patches/features/all/cpu-devices/cpufreq-Longhaul-Disable-driver-by-default.patch --- linux-3.2.46/debian/patches/features/all/cpu-devices/cpufreq-Longhaul-Disable-driver-by-default.patch 2013-05-09 01:22:45.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/cpu-devices/cpufreq-Longhaul-Disable-driver-by-default.patch 2013-07-26 19:30:48.000000000 +0000 @@ -18,11 +18,11 @@ drivers/cpufreq/longhaul.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) -diff --git a/drivers/cpufreq/longhaul.c b/drivers/cpufreq/longhaul.c -index f1fa500..1180d53 100644 ---- a/drivers/cpufreq/longhaul.c -+++ b/drivers/cpufreq/longhaul.c -@@ -77,7 +77,7 @@ static unsigned int longhaul_index; +Index: linux-3.2.46/drivers/cpufreq/longhaul.c +=================================================================== +--- linux-3.2.46.orig/drivers/cpufreq/longhaul.c 2013-07-26 19:23:23.000000000 +0000 ++++ linux-3.2.46/drivers/cpufreq/longhaul.c 2013-07-26 19:30:47.000000000 +0000 +@@ -77,7 +77,7 @@ static int scale_voltage; static int disable_acpi_c3; static int revid_errata; @@ -31,7 +31,7 @@ /* Clock ratios multiplied by 10 */ static int mults[32]; -@@ -965,6 +965,10 @@ static int __init longhaul_init(void) +@@ -965,6 +965,10 @@ if (!x86_match_cpu(longhaul_id)) return -ENODEV; @@ -42,7 +42,7 @@ #ifdef CONFIG_SMP if (num_online_cpus() > 1) { printk(KERN_ERR PFX "More than 1 CPU detected, " -@@ -1021,6 +1025,10 @@ MODULE_PARM_DESC(scale_voltage, "Scale voltage of processor"); +@@ -1021,6 +1025,10 @@ * such. */ module_param(revid_errata, int, 0644); MODULE_PARM_DESC(revid_errata, "Ignore CPU Revision ID"); diff -Nru linux-3.2.46/debian/patches/features/all/cpu-devices/CPU-Introduce-ARCH_HAS_CPU_AUTOPROBE-and-X86-parts.patch linux-3.2.46/debian/patches/features/all/cpu-devices/CPU-Introduce-ARCH_HAS_CPU_AUTOPROBE-and-X86-parts.patch --- linux-3.2.46/debian/patches/features/all/cpu-devices/CPU-Introduce-ARCH_HAS_CPU_AUTOPROBE-and-X86-parts.patch 2013-02-24 03:52:33.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/cpu-devices/CPU-Introduce-ARCH_HAS_CPU_AUTOPROBE-and-X86-parts.patch 2013-07-26 19:23:11.000000000 +0000 @@ -33,11 +33,11 @@ include/linux/cpu.h | 7 +++++ 5 files changed, 66 insertions(+), 58 deletions(-) -diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig -index 864cc6e..6baa1e6 100644 ---- a/arch/x86/Kconfig -+++ b/arch/x86/Kconfig -@@ -179,6 +179,9 @@ config ARCH_HAS_DEFAULT_IDLE +Index: linux-3.2.46/arch/x86/Kconfig +=================================================================== +--- linux-3.2.46.orig/arch/x86/Kconfig 2013-07-26 19:19:52.000000000 +0000 ++++ linux-3.2.46/arch/x86/Kconfig 2013-07-26 19:23:10.000000000 +0000 +@@ -185,6 +185,9 @@ config ARCH_HAS_CACHE_LINE_SIZE def_bool y @@ -47,10 +47,10 @@ config HAVE_SETUP_PER_CPU_AREA def_bool y -diff --git a/arch/x86/kernel/cpu/match.c b/arch/x86/kernel/cpu/match.c -index 7acc961..940e2d4 100644 ---- a/arch/x86/kernel/cpu/match.c -+++ b/arch/x86/kernel/cpu/match.c +Index: linux-3.2.46/arch/x86/kernel/cpu/match.c +=================================================================== +--- linux-3.2.46.orig/arch/x86/kernel/cpu/match.c 2013-07-26 19:23:09.000000000 +0000 ++++ linux-3.2.46/arch/x86/kernel/cpu/match.c 2013-07-26 19:23:10.000000000 +0000 @@ -2,6 +2,7 @@ #include #include @@ -59,7 +59,7 @@ /** * x86_match_cpu - match current CPU again an array of x86_cpu_ids -@@ -46,3 +47,46 @@ const struct x86_cpu_id *x86_match_cpu(const struct x86_cpu_id *match) +@@ -46,3 +47,46 @@ return NULL; } EXPORT_SYMBOL(x86_match_cpu); @@ -106,10 +106,10 @@ + } + return 0; +} -diff --git a/arch/x86/kernel/cpuid.c b/arch/x86/kernel/cpuid.c -index 7c89880..a524353 100644 ---- a/arch/x86/kernel/cpuid.c -+++ b/arch/x86/kernel/cpuid.c +Index: linux-3.2.46/arch/x86/kernel/cpuid.c +=================================================================== +--- linux-3.2.46.orig/arch/x86/kernel/cpuid.c 2013-07-26 19:23:09.000000000 +0000 ++++ linux-3.2.46/arch/x86/kernel/cpuid.c 2013-07-26 19:23:10.000000000 +0000 @@ -40,7 +40,6 @@ #include #include @@ -118,7 +118,7 @@ #include #include -@@ -139,57 +138,13 @@ static const struct file_operations cpuid_fops = { +@@ -139,57 +138,13 @@ .open = cpuid_open, }; @@ -177,7 +177,7 @@ } static void cpuid_device_destroy(int cpu) -@@ -227,17 +182,6 @@ static char *cpuid_devnode(struct device *dev, umode_t *mode) +@@ -227,17 +182,6 @@ return kasprintf(GFP_KERNEL, "cpu/%u/cpuid", MINOR(dev->devt)); } @@ -195,7 +195,7 @@ static int __init cpuid_init(void) { int i, err = 0; -@@ -256,7 +200,6 @@ static int __init cpuid_init(void) +@@ -256,7 +200,6 @@ goto out_chrdev; } cpuid_class->devnode = cpuid_devnode; @@ -203,10 +203,10 @@ for_each_online_cpu(i) { err = cpuid_device_create(i); if (err != 0) -diff --git a/drivers/base/cpu.c b/drivers/base/cpu.c -index db87e78..2a0c670 100644 ---- a/drivers/base/cpu.c -+++ b/drivers/base/cpu.c +Index: linux-3.2.46/drivers/base/cpu.c +=================================================================== +--- linux-3.2.46.orig/drivers/base/cpu.c 2013-07-26 19:23:01.000000000 +0000 ++++ linux-3.2.46/drivers/base/cpu.c 2013-07-26 19:23:10.000000000 +0000 @@ -11,6 +11,7 @@ #include #include @@ -215,7 +215,7 @@ #include #include "base.h" -@@ -223,6 +224,9 @@ int __cpuinit register_cpu(struct cpu *cpu, int num) +@@ -223,6 +224,9 @@ cpu->node_id = cpu_to_node(num); cpu->dev.id = num; cpu->dev.bus = &cpu_subsys; @@ -225,7 +225,7 @@ error = device_register(&cpu->dev); if (!error && cpu->hotpluggable) register_cpu_control(cpu); -@@ -247,6 +251,10 @@ struct device *get_cpu_device(unsigned cpu) +@@ -247,6 +251,10 @@ } EXPORT_SYMBOL_GPL(get_cpu_device); @@ -236,7 +236,7 @@ static struct attribute *cpu_root_attrs[] = { #ifdef CONFIG_ARCH_CPU_PROBE_RELEASE &dev_attr_probe.attr, -@@ -257,6 +265,9 @@ static struct attribute *cpu_root_attrs[] = { +@@ -257,6 +265,9 @@ &cpu_attrs[2].attr.attr, &dev_attr_kernel_max.attr, &dev_attr_offline.attr, @@ -246,11 +246,11 @@ NULL }; -diff --git a/include/linux/cpu.h b/include/linux/cpu.h -index 1f65875..6e53b48 100644 ---- a/include/linux/cpu.h -+++ b/include/linux/cpu.h -@@ -44,6 +44,13 @@ extern ssize_t arch_cpu_release(const char *, size_t); +Index: linux-3.2.46/include/linux/cpu.h +=================================================================== +--- linux-3.2.46.orig/include/linux/cpu.h 2013-07-26 19:22:54.000000000 +0000 ++++ linux-3.2.46/include/linux/cpu.h 2013-07-26 19:23:10.000000000 +0000 +@@ -43,6 +43,13 @@ #endif struct notifier_block; diff -Nru linux-3.2.46/debian/patches/features/all/cpu-devices/cpu-Register-a-generic-CPU-device-on-architectures-t.patch linux-3.2.46/debian/patches/features/all/cpu-devices/cpu-Register-a-generic-CPU-device-on-architectures-t.patch --- linux-3.2.46/debian/patches/features/all/cpu-devices/cpu-Register-a-generic-CPU-device-on-architectures-t.patch 2013-02-24 03:52:33.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/cpu-devices/cpu-Register-a-generic-CPU-device-on-architectures-t.patch 2013-07-26 19:23:04.000000000 +0000 @@ -28,8 +28,10 @@ drivers/base/cpu.c | 19 +++++++++++++++++++ 10 files changed, 31 insertions(+) ---- a/arch/frv/Kconfig -+++ b/arch/frv/Kconfig +Index: linux-3.2.46/arch/frv/Kconfig +=================================================================== +--- linux-3.2.46.orig/arch/frv/Kconfig 2013-07-26 18:54:44.000000000 +0000 ++++ linux-3.2.46/arch/frv/Kconfig 2013-07-26 19:23:00.000000000 +0000 @@ -8,6 +8,7 @@ select HAVE_GENERIC_HARDIRQS select GENERIC_IRQ_SHOW @@ -38,8 +40,10 @@ config ZONE_DMA bool ---- a/arch/h8300/Kconfig -+++ b/arch/h8300/Kconfig +Index: linux-3.2.46/arch/h8300/Kconfig +=================================================================== +--- linux-3.2.46.orig/arch/h8300/Kconfig 2013-07-26 18:54:44.000000000 +0000 ++++ linux-3.2.46/arch/h8300/Kconfig 2013-07-26 19:23:01.000000000 +0000 @@ -4,6 +4,7 @@ select HAVE_IDE select HAVE_GENERIC_HARDIRQS @@ -48,8 +52,10 @@ config SYMBOL_PREFIX string ---- a/arch/m68k/Kconfig -+++ b/arch/m68k/Kconfig +Index: linux-3.2.46/arch/m68k/Kconfig +=================================================================== +--- linux-3.2.46.orig/arch/m68k/Kconfig 2013-07-26 18:54:44.000000000 +0000 ++++ linux-3.2.46/arch/m68k/Kconfig 2013-07-26 19:23:01.000000000 +0000 @@ -7,6 +7,7 @@ select HAVE_GENERIC_HARDIRQS select GENERIC_IRQ_SHOW @@ -58,8 +64,10 @@ config RWSEM_GENERIC_SPINLOCK bool ---- a/arch/microblaze/Kconfig -+++ b/arch/microblaze/Kconfig +Index: linux-3.2.46/arch/microblaze/Kconfig +=================================================================== +--- linux-3.2.46.orig/arch/microblaze/Kconfig 2013-07-26 18:54:44.000000000 +0000 ++++ linux-3.2.46/arch/microblaze/Kconfig 2013-07-26 19:23:01.000000000 +0000 @@ -17,6 +17,7 @@ select HAVE_GENERIC_HARDIRQS select GENERIC_IRQ_PROBE @@ -68,8 +76,10 @@ config SWAP def_bool n ---- a/arch/openrisc/Kconfig -+++ b/arch/openrisc/Kconfig +Index: linux-3.2.46/arch/openrisc/Kconfig +=================================================================== +--- linux-3.2.46.orig/arch/openrisc/Kconfig 2013-07-26 18:54:44.000000000 +0000 ++++ linux-3.2.46/arch/openrisc/Kconfig 2013-07-26 19:23:01.000000000 +0000 @@ -15,6 +15,7 @@ select GENERIC_IRQ_PROBE select GENERIC_IRQ_SHOW @@ -78,8 +88,10 @@ config MMU def_bool y ---- a/arch/score/Kconfig -+++ b/arch/score/Kconfig +Index: linux-3.2.46/arch/score/Kconfig +=================================================================== +--- linux-3.2.46.orig/arch/score/Kconfig 2013-07-26 18:54:44.000000000 +0000 ++++ linux-3.2.46/arch/score/Kconfig 2013-07-26 19:23:01.000000000 +0000 @@ -4,6 +4,7 @@ def_bool y select HAVE_GENERIC_HARDIRQS @@ -88,8 +100,10 @@ choice prompt "System type" ---- a/arch/um/Kconfig.common -+++ b/arch/um/Kconfig.common +Index: linux-3.2.46/arch/um/Kconfig.common +=================================================================== +--- linux-3.2.46.orig/arch/um/Kconfig.common 2013-07-26 18:54:44.000000000 +0000 ++++ linux-3.2.46/arch/um/Kconfig.common 2013-07-26 19:23:01.000000000 +0000 @@ -8,6 +8,7 @@ default y select HAVE_GENERIC_HARDIRQS @@ -98,8 +112,10 @@ config MMU bool ---- a/arch/xtensa/Kconfig -+++ b/arch/xtensa/Kconfig +Index: linux-3.2.46/arch/xtensa/Kconfig +=================================================================== +--- linux-3.2.46.orig/arch/xtensa/Kconfig 2013-07-26 18:54:44.000000000 +0000 ++++ linux-3.2.46/arch/xtensa/Kconfig 2013-07-26 19:23:01.000000000 +0000 @@ -9,6 +9,7 @@ select HAVE_IDE select HAVE_GENERIC_HARDIRQS @@ -108,8 +124,10 @@ help Xtensa processors are 32-bit RISC machines designed by Tensilica primarily for embedded systems. These processors are both ---- a/drivers/base/Kconfig -+++ b/drivers/base/Kconfig +Index: linux-3.2.46/drivers/base/Kconfig +=================================================================== +--- linux-3.2.46.orig/drivers/base/Kconfig 2013-07-26 18:54:44.000000000 +0000 ++++ linux-3.2.46/drivers/base/Kconfig 2013-07-26 19:23:01.000000000 +0000 @@ -172,6 +172,10 @@ bool default n @@ -121,8 +139,10 @@ source "drivers/base/regmap/Kconfig" endmenu ---- a/drivers/base/cpu.c -+++ b/drivers/base/cpu.c +Index: linux-3.2.46/drivers/base/cpu.c +=================================================================== +--- linux-3.2.46.orig/drivers/base/cpu.c 2013-07-26 19:22:59.000000000 +0000 ++++ linux-3.2.46/drivers/base/cpu.c 2013-07-26 19:23:01.000000000 +0000 @@ -11,6 +11,7 @@ #include #include diff -Nru linux-3.2.46/debian/patches/features/all/cpu-devices/crypto-Add-support-for-x86-cpuid-auto-loading-for-x8.patch linux-3.2.46/debian/patches/features/all/cpu-devices/crypto-Add-support-for-x86-cpuid-auto-loading-for-x8.patch --- linux-3.2.46/debian/patches/features/all/cpu-devices/crypto-Add-support-for-x86-cpuid-auto-loading-for-x8.patch 2013-02-24 03:52:33.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/cpu-devices/crypto-Add-support-for-x86-cpuid-auto-loading-for-x8.patch 2013-07-26 19:23:16.000000000 +0000 @@ -36,10 +36,10 @@ drivers/crypto/padlock-sha.c | 16 ++++++++-------- 5 files changed, 41 insertions(+), 19 deletions(-) -diff --git a/arch/x86/crypto/aesni-intel_glue.c b/arch/x86/crypto/aesni-intel_glue.c -index 545d0ce..b3350bd 100644 ---- a/arch/x86/crypto/aesni-intel_glue.c -+++ b/arch/x86/crypto/aesni-intel_glue.c +Index: linux-3.2.46/arch/x86/crypto/aesni-intel_glue.c +=================================================================== +--- linux-3.2.46.orig/arch/x86/crypto/aesni-intel_glue.c 2013-07-26 18:54:40.000000000 +0000 ++++ linux-3.2.46/arch/x86/crypto/aesni-intel_glue.c 2013-07-26 19:23:15.000000000 +0000 @@ -28,6 +28,7 @@ #include #include @@ -48,7 +48,7 @@ #include #include #include -@@ -1253,14 +1254,19 @@ static struct crypto_alg __rfc4106_alg = { +@@ -1253,14 +1254,19 @@ }; #endif @@ -71,10 +71,10 @@ if ((err = crypto_fpu_init())) goto fpu_err; -diff --git a/arch/x86/crypto/crc32c-intel.c b/arch/x86/crypto/crc32c-intel.c -index b9d0026..493f959 100644 ---- a/arch/x86/crypto/crc32c-intel.c -+++ b/arch/x86/crypto/crc32c-intel.c +Index: linux-3.2.46/arch/x86/crypto/crc32c-intel.c +=================================================================== +--- linux-3.2.46.orig/arch/x86/crypto/crc32c-intel.c 2013-07-26 18:54:40.000000000 +0000 ++++ linux-3.2.46/arch/x86/crypto/crc32c-intel.c 2013-07-26 19:23:15.000000000 +0000 @@ -31,6 +31,7 @@ #include @@ -83,7 +83,7 @@ #define CHKSUM_BLOCK_SIZE 1 #define CHKSUM_DIGEST_SIZE 4 -@@ -173,13 +174,17 @@ static struct shash_alg alg = { +@@ -173,13 +174,17 @@ } }; @@ -104,10 +104,10 @@ } static void __exit crc32c_intel_mod_fini(void) -diff --git a/arch/x86/crypto/ghash-clmulni-intel_glue.c b/arch/x86/crypto/ghash-clmulni-intel_glue.c -index 976aa64..b4bf0a6 100644 ---- a/arch/x86/crypto/ghash-clmulni-intel_glue.c -+++ b/arch/x86/crypto/ghash-clmulni-intel_glue.c +Index: linux-3.2.46/arch/x86/crypto/ghash-clmulni-intel_glue.c +=================================================================== +--- linux-3.2.46.orig/arch/x86/crypto/ghash-clmulni-intel_glue.c 2013-07-26 18:54:40.000000000 +0000 ++++ linux-3.2.46/arch/x86/crypto/ghash-clmulni-intel_glue.c 2013-07-26 19:23:15.000000000 +0000 @@ -20,6 +20,7 @@ #include #include @@ -116,7 +116,7 @@ #define GHASH_BLOCK_SIZE 16 #define GHASH_DIGEST_SIZE 16 -@@ -294,15 +295,18 @@ static struct ahash_alg ghash_async_alg = { +@@ -294,15 +295,18 @@ }, }; @@ -139,10 +139,10 @@ err = crypto_register_shash(&ghash_alg); if (err) -diff --git a/drivers/crypto/padlock-aes.c b/drivers/crypto/padlock-aes.c -index 29b9469..37b2e94 100644 ---- a/drivers/crypto/padlock-aes.c -+++ b/drivers/crypto/padlock-aes.c +Index: linux-3.2.46/drivers/crypto/padlock-aes.c +=================================================================== +--- linux-3.2.46.orig/drivers/crypto/padlock-aes.c 2013-07-26 18:54:40.000000000 +0000 ++++ linux-3.2.46/drivers/crypto/padlock-aes.c 2013-07-26 19:23:15.000000000 +0000 @@ -19,6 +19,7 @@ #include #include @@ -151,7 +151,7 @@ #include #include #include -@@ -503,12 +504,18 @@ static struct crypto_alg cbc_aes_alg = { +@@ -503,12 +504,18 @@ } }; @@ -171,10 +171,10 @@ return -ENODEV; if (!cpu_has_xcrypt_enabled) { -diff --git a/drivers/crypto/padlock-sha.c b/drivers/crypto/padlock-sha.c -index 06bdb4b..9266c0e 100644 ---- a/drivers/crypto/padlock-sha.c -+++ b/drivers/crypto/padlock-sha.c +Index: linux-3.2.46/drivers/crypto/padlock-sha.c +=================================================================== +--- linux-3.2.46.orig/drivers/crypto/padlock-sha.c 2013-07-26 18:54:40.000000000 +0000 ++++ linux-3.2.46/drivers/crypto/padlock-sha.c 2013-07-26 19:23:15.000000000 +0000 @@ -22,6 +22,7 @@ #include #include @@ -183,7 +183,7 @@ #include struct padlock_sha_desc { -@@ -526,6 +527,12 @@ static struct shash_alg sha256_alg_nano = { +@@ -526,6 +527,12 @@ } }; @@ -196,7 +196,7 @@ static int __init padlock_init(void) { int rc = -ENODEV; -@@ -533,15 +540,8 @@ static int __init padlock_init(void) +@@ -533,15 +540,8 @@ struct shash_alg *sha1; struct shash_alg *sha256; diff -Nru linux-3.2.46/debian/patches/features/all/cpu-devices/driver-core-cpu-fix-kobject-warning-when-hotplugging.patch linux-3.2.46/debian/patches/features/all/cpu-devices/driver-core-cpu-fix-kobject-warning-when-hotplugging.patch --- linux-3.2.46/debian/patches/features/all/cpu-devices/driver-core-cpu-fix-kobject-warning-when-hotplugging.patch 2013-02-24 03:52:33.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/cpu-devices/driver-core-cpu-fix-kobject-warning-when-hotplugging.patch 2013-07-26 19:23:14.000000000 +0000 @@ -17,11 +17,11 @@ drivers/base/cpu.c | 1 + 1 file changed, 1 insertion(+) -diff --git a/drivers/base/cpu.c b/drivers/base/cpu.c -index 23f2c4c..4dabf50 100644 ---- a/drivers/base/cpu.c -+++ b/drivers/base/cpu.c -@@ -240,6 +240,7 @@ int __cpuinit register_cpu(struct cpu *cpu, int num) +Index: linux-3.2.46/drivers/base/cpu.c +=================================================================== +--- linux-3.2.46.orig/drivers/base/cpu.c 2013-07-26 19:23:12.000000000 +0000 ++++ linux-3.2.46/drivers/base/cpu.c 2013-07-26 19:23:13.000000000 +0000 +@@ -241,6 +241,7 @@ int error; cpu->node_id = cpu_to_node(num); diff -Nru linux-3.2.46/debian/patches/features/all/cpu-devices/driver-core-cpu-remove-kernel-warning-when-removing-.patch linux-3.2.46/debian/patches/features/all/cpu-devices/driver-core-cpu-remove-kernel-warning-when-removing-.patch --- linux-3.2.46/debian/patches/features/all/cpu-devices/driver-core-cpu-remove-kernel-warning-when-removing-.patch 2013-02-24 03:52:33.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/cpu-devices/driver-core-cpu-remove-kernel-warning-when-removing-.patch 2013-07-26 19:23:13.000000000 +0000 @@ -21,8 +21,10 @@ drivers/base/cpu.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) ---- a/drivers/base/cpu.c -+++ b/drivers/base/cpu.c +Index: linux-3.2.46/drivers/base/cpu.c +=================================================================== +--- linux-3.2.46.orig/drivers/base/cpu.c 2013-07-26 19:23:10.000000000 +0000 ++++ linux-3.2.46/drivers/base/cpu.c 2013-07-26 19:23:12.000000000 +0000 @@ -209,6 +209,25 @@ } static DEVICE_ATTR(offline, 0444, print_cpus_offline, NULL); diff -Nru linux-3.2.46/debian/patches/features/all/cpu-devices/driver-core-implement-sysdev-functionality-for-regul.patch linux-3.2.46/debian/patches/features/all/cpu-devices/driver-core-implement-sysdev-functionality-for-regul.patch --- linux-3.2.46/debian/patches/features/all/cpu-devices/driver-core-implement-sysdev-functionality-for-regul.patch 2013-02-24 03:52:33.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/cpu-devices/driver-core-implement-sysdev-functionality-for-regul.patch 2013-07-26 19:22:52.000000000 +0000 @@ -41,10 +41,10 @@ include/linux/device.h | 78 ++++++++++++- 7 files changed, 431 insertions(+), 62 deletions(-) -diff --git a/drivers/base/base.h b/drivers/base/base.h -index 21c1b96..7a6ae42 100644 ---- a/drivers/base/base.h -+++ b/drivers/base/base.h +Index: linux-3.2.46/drivers/base/base.h +=================================================================== +--- linux-3.2.46.orig/drivers/base/base.h 2013-07-26 18:54:48.000000000 +0000 ++++ linux-3.2.46/drivers/base/base.h 2013-07-26 19:22:51.000000000 +0000 @@ -4,7 +4,9 @@ * struct subsys_private - structure to hold the private to the driver core portions of the bus_type/class structure. * @@ -76,7 +76,7 @@ struct kset *drivers_kset; struct klist klist_devices; -@@ -36,9 +38,7 @@ struct subsys_private { +@@ -36,9 +38,7 @@ unsigned int drivers_autoprobe:1; struct bus_type *bus; @@ -86,7 +86,7 @@ struct class *class; }; #define to_subsys_private(obj) container_of(obj, struct subsys_private, subsys.kobj) -@@ -94,7 +94,6 @@ extern int hypervisor_init(void); +@@ -94,7 +94,6 @@ static inline int hypervisor_init(void) { return 0; } #endif extern int platform_bus_init(void); @@ -94,7 +94,7 @@ extern int cpu_dev_init(void); extern int bus_add_device(struct device *dev); -@@ -116,6 +115,7 @@ extern char *make_class_name(const char *name, struct kobject *kobj); +@@ -116,6 +115,7 @@ extern int devres_release_all(struct device *dev); @@ -102,10 +102,10 @@ extern struct kset *devices_kset; #if defined(CONFIG_MODULES) && defined(CONFIG_SYSFS) -diff --git a/drivers/base/bus.c b/drivers/base/bus.c -index 000e7b2..99dc592 100644 ---- a/drivers/base/bus.c -+++ b/drivers/base/bus.c +Index: linux-3.2.46/drivers/base/bus.c +=================================================================== +--- linux-3.2.46.orig/drivers/base/bus.c 2013-07-26 18:54:48.000000000 +0000 ++++ linux-3.2.46/drivers/base/bus.c 2013-07-26 19:22:51.000000000 +0000 @@ -16,9 +16,14 @@ #include #include @@ -121,7 +121,7 @@ #define to_bus_attr(_attr) container_of(_attr, struct bus_attribute, attr) /* -@@ -360,6 +365,47 @@ struct device *bus_find_device_by_name(struct bus_type *bus, +@@ -360,6 +365,47 @@ } EXPORT_SYMBOL_GPL(bus_find_device_by_name); @@ -169,7 +169,7 @@ static struct device_driver *next_driver(struct klist_iter *i) { struct klist_node *n = klist_next(i); -@@ -487,38 +533,59 @@ out_put: +@@ -487,38 +533,59 @@ void bus_probe_device(struct device *dev) { struct bus_type *bus = dev->bus; @@ -212,15 +212,14 @@ - device_remove_attrs(dev->bus, dev); - if (klist_node_attached(&dev->p->knode_bus)) - klist_del(&dev->p->knode_bus); -- ++ struct bus_type *bus = dev->bus; ++ struct subsys_interface *sif; + - pr_debug("bus: '%s': remove device %s\n", - dev->bus->name, dev_name(dev)); - device_release_driver(dev); - bus_put(dev->bus); - } -+ struct bus_type *bus = dev->bus; -+ struct subsys_interface *sif; -+ + if (!bus) + return; + @@ -244,7 +243,7 @@ } static int driver_add_attrs(struct bus_type *bus, struct device_driver *drv) -@@ -847,14 +914,14 @@ static ssize_t bus_uevent_store(struct bus_type *bus, +@@ -847,14 +914,14 @@ static BUS_ATTR(uevent, S_IWUSR, NULL, bus_uevent_store); /** @@ -262,7 +261,7 @@ { int retval; struct subsys_private *priv; -@@ -898,6 +965,8 @@ int bus_register(struct bus_type *bus) +@@ -898,6 +965,8 @@ goto bus_drivers_fail; } @@ -271,7 +270,7 @@ klist_init(&priv->klist_devices, klist_devices_get, klist_devices_put); klist_init(&priv->klist_drivers, NULL, NULL); -@@ -927,7 +996,7 @@ out: +@@ -927,7 +996,7 @@ bus->p = NULL; return retval; } @@ -280,7 +279,7 @@ /** * bus_unregister - remove a bus from the system -@@ -939,6 +1008,8 @@ EXPORT_SYMBOL_GPL(bus_register); +@@ -939,6 +1008,8 @@ void bus_unregister(struct bus_type *bus) { pr_debug("bus: '%s': unregistering\n", bus->name); @@ -289,7 +288,7 @@ bus_remove_attrs(bus); remove_probe_files(bus); kset_unregister(bus->p->drivers_kset); -@@ -1028,10 +1099,194 @@ void bus_sort_breadthfirst(struct bus_type *bus, +@@ -1028,10 +1099,194 @@ } EXPORT_SYMBOL_GPL(bus_sort_breadthfirst); @@ -484,11 +483,11 @@ + return 0; } -diff --git a/drivers/base/class.c b/drivers/base/class.c -index b80d91c..03243d4 100644 ---- a/drivers/base/class.c -+++ b/drivers/base/class.c -@@ -184,9 +184,9 @@ int __class_register(struct class *cls, struct lock_class_key *key) +Index: linux-3.2.46/drivers/base/class.c +=================================================================== +--- linux-3.2.46.orig/drivers/base/class.c 2013-07-26 18:54:48.000000000 +0000 ++++ linux-3.2.46/drivers/base/class.c 2013-07-26 19:22:51.000000000 +0000 +@@ -184,9 +184,9 @@ if (!cp) return -ENOMEM; klist_init(&cp->klist_devices, klist_class_dev_get, klist_class_dev_put); @@ -500,7 +499,7 @@ error = kobject_set_name(&cp->subsys.kobj, "%s", cls->name); if (error) { kfree(cp); -@@ -460,15 +460,15 @@ int class_interface_register(struct class_interface *class_intf) +@@ -460,15 +460,15 @@ if (!parent) return -EINVAL; @@ -519,7 +518,7 @@ return 0; } -@@ -482,7 +482,7 @@ void class_interface_unregister(struct class_interface *class_intf) +@@ -482,7 +482,7 @@ if (!parent) return; @@ -528,7 +527,7 @@ list_del_init(&class_intf->node); if (class_intf->remove_dev) { class_dev_iter_init(&iter, parent, NULL, NULL); -@@ -490,7 +490,7 @@ void class_interface_unregister(struct class_interface *class_intf) +@@ -490,7 +490,7 @@ class_intf->remove_dev(dev, class_intf); class_dev_iter_exit(&iter); } @@ -537,11 +536,11 @@ class_put(parent); } -diff --git a/drivers/base/core.c b/drivers/base/core.c -index 82c8654..a31ea19 100644 ---- a/drivers/base/core.c -+++ b/drivers/base/core.c -@@ -117,6 +117,56 @@ static const struct sysfs_ops dev_sysfs_ops = { +Index: linux-3.2.46/drivers/base/core.c +=================================================================== +--- linux-3.2.46.orig/drivers/base/core.c 2013-07-26 18:54:48.000000000 +0000 ++++ linux-3.2.46/drivers/base/core.c 2013-07-26 19:22:51.000000000 +0000 +@@ -118,6 +118,56 @@ .store = dev_attr_store, }; @@ -598,7 +597,7 @@ /** * device_release - free device structure. -@@ -463,7 +513,7 @@ static ssize_t show_dev(struct device *dev, struct device_attribute *attr, +@@ -464,7 +514,7 @@ static struct device_attribute devt_attr = __ATTR(dev, S_IRUGO, show_dev, NULL); @@ -607,7 +606,7 @@ struct kset *devices_kset; /** -@@ -710,6 +760,10 @@ static struct kobject *get_device_parent(struct device *dev, +@@ -711,6 +761,10 @@ return k; } @@ -618,7 +617,7 @@ if (parent) return &parent->kobj; return NULL; -@@ -730,14 +784,6 @@ static void cleanup_device_parent(struct device *dev) +@@ -731,14 +785,6 @@ cleanup_glue_dir(dev, dev->kobj.parent); } @@ -633,7 +632,7 @@ static int device_add_class_symlinks(struct device *dev) { int error; -@@ -890,6 +936,7 @@ int device_private_init(struct device *dev) +@@ -891,6 +937,7 @@ int device_add(struct device *dev) { struct device *parent = NULL; @@ -641,7 +640,7 @@ struct class_interface *class_intf; int error = -EINVAL; -@@ -913,6 +960,10 @@ int device_add(struct device *dev) +@@ -914,6 +961,10 @@ dev->init_name = NULL; } @@ -652,7 +651,7 @@ if (!dev_name(dev)) { error = -EINVAL; goto name_error; -@@ -921,7 +972,9 @@ int device_add(struct device *dev) +@@ -922,7 +973,9 @@ pr_debug("device: '%s': %s\n", dev_name(dev), __func__); parent = get_device(dev->parent); @@ -663,7 +662,7 @@ /* use parent numa_node */ if (parent) -@@ -981,17 +1034,17 @@ int device_add(struct device *dev) +@@ -982,17 +1035,17 @@ &parent->p->klist_children); if (dev->class) { @@ -684,7 +683,7 @@ } done: put_device(dev); -@@ -1106,15 +1159,15 @@ void device_del(struct device *dev) +@@ -1107,15 +1160,15 @@ if (dev->class) { device_remove_class_symlinks(dev); @@ -703,11 +702,11 @@ } device_remove_file(dev, &uevent_attr); device_remove_attrs(dev); -diff --git a/drivers/base/init.c b/drivers/base/init.c -index c8a934e..c16f0b8 100644 ---- a/drivers/base/init.c -+++ b/drivers/base/init.c -@@ -31,7 +31,6 @@ void __init driver_init(void) +Index: linux-3.2.46/drivers/base/init.c +=================================================================== +--- linux-3.2.46.orig/drivers/base/init.c 2013-07-26 18:54:48.000000000 +0000 ++++ linux-3.2.46/drivers/base/init.c 2013-07-26 19:22:51.000000000 +0000 +@@ -31,7 +31,6 @@ * core core pieces. */ platform_bus_init(); @@ -715,11 +714,11 @@ cpu_dev_init(); memory_dev_init(); } -diff --git a/drivers/base/sys.c b/drivers/base/sys.c -index 9dff77b..409f5ce 100644 ---- a/drivers/base/sys.c -+++ b/drivers/base/sys.c -@@ -126,7 +126,7 @@ void sysdev_class_remove_file(struct sysdev_class *c, +Index: linux-3.2.46/drivers/base/sys.c +=================================================================== +--- linux-3.2.46.orig/drivers/base/sys.c 2013-07-26 18:54:48.000000000 +0000 ++++ linux-3.2.46/drivers/base/sys.c 2013-07-26 19:22:51.000000000 +0000 +@@ -126,7 +126,7 @@ } EXPORT_SYMBOL_GPL(sysdev_class_remove_file); @@ -728,7 +727,7 @@ int sysdev_class_register(struct sysdev_class *cls) { -@@ -331,14 +331,6 @@ void sysdev_unregister(struct sys_device *sysdev) +@@ -331,14 +331,6 @@ EXPORT_SYMBOL_GPL(sysdev_register); EXPORT_SYMBOL_GPL(sysdev_unregister); @@ -743,11 +742,11 @@ #define to_ext_attr(x) container_of(x, struct sysdev_ext_attribute, attr) ssize_t sysdev_store_ulong(struct sys_device *sysdev, -diff --git a/include/linux/device.h b/include/linux/device.h -index 341fb74..7f9fc15 100644 ---- a/include/linux/device.h -+++ b/include/linux/device.h -@@ -53,6 +53,8 @@ extern void bus_remove_file(struct bus_type *, struct bus_attribute *); +Index: linux-3.2.46/include/linux/device.h +=================================================================== +--- linux-3.2.46.orig/include/linux/device.h 2013-07-26 18:54:48.000000000 +0000 ++++ linux-3.2.46/include/linux/device.h 2013-07-26 19:22:51.000000000 +0000 +@@ -53,6 +53,8 @@ * struct bus_type - The bus type of the device * * @name: The name of the bus. @@ -756,7 +755,7 @@ * @bus_attrs: Default attributes of the bus. * @dev_attrs: Default attributes of the devices on the bus. * @drv_attrs: Default attributes of the device drivers on the bus. -@@ -86,6 +88,8 @@ extern void bus_remove_file(struct bus_type *, struct bus_attribute *); +@@ -86,6 +88,8 @@ */ struct bus_type { const char *name; @@ -765,7 +764,7 @@ struct bus_attribute *bus_attrs; struct device_attribute *dev_attrs; struct driver_attribute *drv_attrs; -@@ -106,12 +110,30 @@ struct bus_type { +@@ -106,12 +110,30 @@ struct subsys_private *p; }; @@ -797,7 +796,7 @@ int bus_for_each_dev(struct bus_type *bus, struct device *start, void *data, int (*fn)(struct device *dev, void *data)); -@@ -121,10 +143,10 @@ struct device *bus_find_device(struct bus_type *bus, struct device *start, +@@ -121,10 +143,10 @@ struct device *bus_find_device_by_name(struct bus_type *bus, struct device *start, const char *name); @@ -810,7 +809,7 @@ void bus_sort_breadthfirst(struct bus_type *bus, int (*compare)(const struct device *a, const struct device *b)); -@@ -256,6 +278,33 @@ struct device *driver_find_device(struct device_driver *drv, +@@ -256,6 +278,33 @@ int (*match)(struct device *dev, void *data)); /** @@ -844,7 +843,7 @@ * struct class - device classes * @name: Name of the class. * @owner: The module owner. -@@ -438,8 +487,28 @@ struct device_attribute { +@@ -438,8 +487,28 @@ const char *buf, size_t count); }; @@ -874,7 +873,7 @@ extern int __must_check device_create_file(struct device *device, const struct device_attribute *entry); -@@ -603,6 +672,7 @@ struct device { +@@ -600,6 +669,7 @@ struct device_node *of_node; /* associated device tree node */ dev_t devt; /* dev_t, creates the sysfs "dev" */ diff -Nru linux-3.2.46/debian/patches/features/all/cpu-devices/driver-core-remove-__must_check-from-device_create_f.patch linux-3.2.46/debian/patches/features/all/cpu-devices/driver-core-remove-__must_check-from-device_create_f.patch --- linux-3.2.46/debian/patches/features/all/cpu-devices/driver-core-remove-__must_check-from-device_create_f.patch 2013-02-24 03:52:33.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/cpu-devices/driver-core-remove-__must_check-from-device_create_f.patch 2013-07-26 19:23:38.000000000 +0000 @@ -19,11 +19,11 @@ include/linux/device.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -diff --git a/include/linux/device.h b/include/linux/device.h -index 7f9fc15..acf505e 100644 ---- a/include/linux/device.h -+++ b/include/linux/device.h -@@ -510,8 +510,8 @@ ssize_t device_store_int(struct device *dev, struct device_attribute *attr, +Index: linux-3.2.46/include/linux/device.h +=================================================================== +--- linux-3.2.46.orig/include/linux/device.h 2013-07-26 19:22:51.000000000 +0000 ++++ linux-3.2.46/include/linux/device.h 2013-07-26 19:23:37.000000000 +0000 +@@ -510,8 +510,8 @@ struct dev_ext_attribute dev_attr_##_name = \ { __ATTR(_name, _mode, device_show_ulong, device_store_ulong), &(_var) } diff -Nru linux-3.2.46/debian/patches/features/all/cpu-devices/HWMON-Convert-coretemp-to-x86-cpuid-autoprobing.patch linux-3.2.46/debian/patches/features/all/cpu-devices/HWMON-Convert-coretemp-to-x86-cpuid-autoprobing.patch --- linux-3.2.46/debian/patches/features/all/cpu-devices/HWMON-Convert-coretemp-to-x86-cpuid-autoprobing.patch 2013-02-24 03:52:33.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/cpu-devices/HWMON-Convert-coretemp-to-x86-cpuid-autoprobing.patch 2013-07-26 19:23:21.000000000 +0000 @@ -18,10 +18,10 @@ drivers/hwmon/coretemp.c | 17 ++++++++++++++--- 1 file changed, 14 insertions(+), 3 deletions(-) -diff --git a/drivers/hwmon/coretemp.c b/drivers/hwmon/coretemp.c -index a6c6ec3..249ac46 100644 ---- a/drivers/hwmon/coretemp.c -+++ b/drivers/hwmon/coretemp.c +Index: linux-3.2.46/drivers/hwmon/coretemp.c +=================================================================== +--- linux-3.2.46.orig/drivers/hwmon/coretemp.c 2013-07-26 18:54:38.000000000 +0000 ++++ linux-3.2.46/drivers/hwmon/coretemp.c 2013-07-26 19:23:20.000000000 +0000 @@ -39,6 +39,7 @@ #include #include @@ -30,7 +30,7 @@ #define DRVNAME "coretemp" -@@ -759,13 +760,23 @@ static struct notifier_block coretemp_cpu_notifier __refdata = { +@@ -791,13 +792,23 @@ .notifier_call = coretemp_cpu_callback, }; diff -Nru linux-3.2.46/debian/patches/features/all/cpu-devices/HWMON-Convert-via-cputemp-to-x86-cpuid-autoprobing.patch linux-3.2.46/debian/patches/features/all/cpu-devices/HWMON-Convert-via-cputemp-to-x86-cpuid-autoprobing.patch --- linux-3.2.46/debian/patches/features/all/cpu-devices/HWMON-Convert-via-cputemp-to-x86-cpuid-autoprobing.patch 2013-02-24 03:52:33.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/cpu-devices/HWMON-Convert-via-cputemp-to-x86-cpuid-autoprobing.patch 2013-07-26 19:23:20.000000000 +0000 @@ -16,10 +16,10 @@ drivers/hwmon/via-cputemp.c | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-) -diff --git a/drivers/hwmon/via-cputemp.c b/drivers/hwmon/via-cputemp.c -index 8eac67d..8689664 100644 ---- a/drivers/hwmon/via-cputemp.c -+++ b/drivers/hwmon/via-cputemp.c +Index: linux-3.2.46/drivers/hwmon/via-cputemp.c +=================================================================== +--- linux-3.2.46.orig/drivers/hwmon/via-cputemp.c 2013-07-26 18:54:38.000000000 +0000 ++++ linux-3.2.46/drivers/hwmon/via-cputemp.c 2013-07-26 19:23:19.000000000 +0000 @@ -37,6 +37,7 @@ #include #include @@ -28,7 +28,7 @@ #define DRVNAME "via_cputemp" -@@ -308,15 +309,20 @@ static struct notifier_block via_cputemp_cpu_notifier __refdata = { +@@ -308,15 +309,20 @@ .notifier_call = via_cputemp_cpu_callback, }; diff -Nru linux-3.2.46/debian/patches/features/all/cpu-devices/intel-idle-convert-to-x86_cpu_id-auto-probing.patch linux-3.2.46/debian/patches/features/all/cpu-devices/intel-idle-convert-to-x86_cpu_id-auto-probing.patch --- linux-3.2.46/debian/patches/features/all/cpu-devices/intel-idle-convert-to-x86_cpu_id-auto-probing.patch 2013-02-24 03:52:33.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/cpu-devices/intel-idle-convert-to-x86_cpu_id-auto-probing.patch 2013-07-26 19:23:17.000000000 +0000 @@ -20,8 +20,10 @@ drivers/idle/intel_idle.c | 116 ++++++++++++++++++++++++++------------------- 1 file changed, 66 insertions(+), 50 deletions(-) ---- a/drivers/idle/intel_idle.c -+++ b/drivers/idle/intel_idle.c +Index: linux-3.2.46/drivers/idle/intel_idle.c +=================================================================== +--- linux-3.2.46.orig/drivers/idle/intel_idle.c 2013-07-26 18:54:39.000000000 +0000 ++++ linux-3.2.46/drivers/idle/intel_idle.c 2013-07-26 19:23:16.000000000 +0000 @@ -62,6 +62,7 @@ #include #include @@ -61,7 +63,7 @@ * Set this flag for states where the HW flushes the TLB for us * and so we don't need cross-calls to keep it consistent. * If this flag is set, SW flushes the TLB, so even if the -@@ -320,27 +326,78 @@ +@@ -352,27 +358,78 @@ unsigned long long msr_bits; rdmsrl(MSR_NHM_SNB_PKG_CST_CFG_CTL, msr_bits); @@ -145,7 +147,7 @@ if (boot_cpu_data.cpuid_level < CPUID_MWAIT_LEAF) return -ENODEV; -@@ -354,48 +405,8 @@ +@@ -386,48 +443,8 @@ pr_debug(PREFIX "MWAIT substates: 0x%x\n", mwait_substates); @@ -196,7 +198,7 @@ if (boot_cpu_has(X86_FEATURE_ARAT)) /* Always Reliable APIC Timer */ lapic_timer_reliable_states = LAPIC_TIMER_ALWAYS_RELIABLE; -@@ -471,7 +487,7 @@ +@@ -506,7 +523,7 @@ drv->state_count += 1; } diff -Nru linux-3.2.46/debian/patches/features/all/cpu-devices/intel_idle-Fix-ID-for-Nehalem-EX-Xeon-in-device-ID-t.patch linux-3.2.46/debian/patches/features/all/cpu-devices/intel_idle-Fix-ID-for-Nehalem-EX-Xeon-in-device-ID-t.patch --- linux-3.2.46/debian/patches/features/all/cpu-devices/intel_idle-Fix-ID-for-Nehalem-EX-Xeon-in-device-ID-t.patch 2013-02-24 03:52:33.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/cpu-devices/intel_idle-Fix-ID-for-Nehalem-EX-Xeon-in-device-ID-t.patch 2013-07-26 19:23:29.000000000 +0000 @@ -17,11 +17,11 @@ drivers/idle/intel_idle.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -diff --git a/drivers/idle/intel_idle.c b/drivers/idle/intel_idle.c -index 237fe57..a238649 100644 ---- a/drivers/idle/intel_idle.c -+++ b/drivers/idle/intel_idle.c -@@ -360,7 +360,7 @@ static const struct x86_cpu_id intel_idle_ids[] = { +Index: linux-3.2.46/drivers/idle/intel_idle.c +=================================================================== +--- linux-3.2.46.orig/drivers/idle/intel_idle.c 2013-07-26 19:23:16.000000000 +0000 ++++ linux-3.2.46/drivers/idle/intel_idle.c 2013-07-26 19:23:28.000000000 +0000 +@@ -397,7 +397,7 @@ ICPU(0x1f, idle_cpu_nehalem), ICPU(0x25, idle_cpu_westmere), ICPU(0x2c, idle_cpu_westmere), diff -Nru linux-3.2.46/debian/patches/features/all/cpu-devices/intel_idle-Revert-change-of-auto_demotion_disable_fl.patch linux-3.2.46/debian/patches/features/all/cpu-devices/intel_idle-Revert-change-of-auto_demotion_disable_fl.patch --- linux-3.2.46/debian/patches/features/all/cpu-devices/intel_idle-Revert-change-of-auto_demotion_disable_fl.patch 2013-02-24 03:52:33.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/cpu-devices/intel_idle-Revert-change-of-auto_demotion_disable_fl.patch 2013-07-26 19:23:33.000000000 +0000 @@ -18,9 +18,11 @@ drivers/idle/intel_idle.c | 12 ++++-------- 1 file changed, 4 insertions(+), 8 deletions(-) ---- a/drivers/idle/intel_idle.c -+++ b/drivers/idle/intel_idle.c -@@ -364,10 +364,6 @@ static void auto_demotion_disable(void * +Index: linux-3.2.46/drivers/idle/intel_idle.c +=================================================================== +--- linux-3.2.46.orig/drivers/idle/intel_idle.c 2013-07-26 19:23:28.000000000 +0000 ++++ linux-3.2.46/drivers/idle/intel_idle.c 2013-07-26 19:23:32.000000000 +0000 +@@ -364,10 +364,6 @@ static const struct idle_cpu idle_cpu_nehalem = { .state_table = nehalem_cstates, @@ -31,7 +33,7 @@ .auto_demotion_disable_flags = NHM_C1_AUTO_DEMOTE | NHM_C3_AUTO_DEMOTE, }; -@@ -395,12 +391,12 @@ static const struct x86_cpu_id intel_idl +@@ -395,12 +391,12 @@ ICPU(0x1a, idle_cpu_nehalem), ICPU(0x1e, idle_cpu_nehalem), ICPU(0x1f, idle_cpu_nehalem), diff -Nru linux-3.2.46/debian/patches/features/all/cpu-devices/mce-fix-warning-messages-about-static-struct-mce_dev.patch linux-3.2.46/debian/patches/features/all/cpu-devices/mce-fix-warning-messages-about-static-struct-mce_dev.patch --- linux-3.2.46/debian/patches/features/all/cpu-devices/mce-fix-warning-messages-about-static-struct-mce_dev.patch 2013-02-24 03:52:33.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/cpu-devices/mce-fix-warning-messages-about-static-struct-mce_dev.patch 2013-07-26 19:23:07.000000000 +0000 @@ -26,11 +26,11 @@ arch/x86/kernel/cpu/mcheck/mce_amd.c | 18 +++++++++++------- 3 files changed, 26 insertions(+), 12 deletions(-) -diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h -index f35ce43..6aefb14 100644 ---- a/arch/x86/include/asm/mce.h -+++ b/arch/x86/include/asm/mce.h -@@ -151,7 +151,7 @@ static inline void enable_p5_mce(void) {} +Index: linux-3.2.46/arch/x86/include/asm/mce.h +=================================================================== +--- linux-3.2.46.orig/arch/x86/include/asm/mce.h 2013-07-26 19:22:53.000000000 +0000 ++++ linux-3.2.46/arch/x86/include/asm/mce.h 2013-07-26 19:23:06.000000000 +0000 +@@ -149,7 +149,7 @@ void mce_setup(struct mce *m); void mce_log(struct mce *m); @@ -39,11 +39,11 @@ /* * Maximum banks number. -diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c -index 29ba329..5a11ae2 100644 ---- a/arch/x86/kernel/cpu/mcheck/mce.c -+++ b/arch/x86/kernel/cpu/mcheck/mce.c -@@ -1859,7 +1859,7 @@ static struct bus_type mce_subsys = { +Index: linux-3.2.46/arch/x86/kernel/cpu/mcheck/mce.c +=================================================================== +--- linux-3.2.46.orig/arch/x86/kernel/cpu/mcheck/mce.c 2013-07-26 19:23:04.000000000 +0000 ++++ linux-3.2.46/arch/x86/kernel/cpu/mcheck/mce.c 2013-07-26 19:23:06.000000000 +0000 +@@ -1817,7 +1817,7 @@ .dev_name = "machinecheck", }; @@ -52,7 +52,7 @@ __cpuinitdata void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu); -@@ -2001,19 +2001,27 @@ static struct device_attribute *mce_device_attrs[] = { +@@ -1959,19 +1959,27 @@ static cpumask_var_t mce_device_initialized; @@ -82,7 +82,7 @@ err = device_register(dev); if (err) -@@ -2030,6 +2038,7 @@ static __cpuinit int mce_device_create(unsigned int cpu) +@@ -1988,6 +1996,7 @@ goto error2; } cpumask_set_cpu(cpu, mce_device_initialized); @@ -90,7 +90,7 @@ return 0; error2: -@@ -2046,7 +2055,7 @@ error: +@@ -2004,7 +2013,7 @@ static __cpuinit void mce_device_remove(unsigned int cpu) { @@ -99,7 +99,7 @@ int i; if (!cpumask_test_cpu(cpu, mce_device_initialized)) -@@ -2060,6 +2069,7 @@ static __cpuinit void mce_device_remove(unsigned int cpu) +@@ -2018,6 +2027,7 @@ device_unregister(dev); cpumask_clear_cpu(cpu, mce_device_initialized); @@ -107,11 +107,11 @@ } /* Make sure there are no machine checks on offlined CPUs. */ -diff --git a/arch/x86/kernel/cpu/mcheck/mce_amd.c b/arch/x86/kernel/cpu/mcheck/mce_amd.c -index ba0b94a..786e76a 100644 ---- a/arch/x86/kernel/cpu/mcheck/mce_amd.c -+++ b/arch/x86/kernel/cpu/mcheck/mce_amd.c -@@ -523,6 +523,7 @@ static __cpuinit int threshold_create_bank(unsigned int cpu, unsigned int bank) +Index: linux-3.2.46/arch/x86/kernel/cpu/mcheck/mce_amd.c +=================================================================== +--- linux-3.2.46.orig/arch/x86/kernel/cpu/mcheck/mce_amd.c 2013-07-26 19:22:54.000000000 +0000 ++++ linux-3.2.46/arch/x86/kernel/cpu/mcheck/mce_amd.c 2013-07-26 19:23:06.000000000 +0000 +@@ -556,6 +556,7 @@ { int i, err = 0; struct threshold_bank *b = NULL; @@ -119,7 +119,7 @@ char name[32]; sprintf(name, "threshold_bank%i", bank); -@@ -543,8 +544,7 @@ static __cpuinit int threshold_create_bank(unsigned int cpu, unsigned int bank) +@@ -577,8 +578,7 @@ if (!b) goto out; @@ -129,7 +129,7 @@ if (err) goto out; -@@ -565,7 +565,7 @@ static __cpuinit int threshold_create_bank(unsigned int cpu, unsigned int bank) +@@ -600,7 +600,7 @@ goto out; } @@ -138,7 +138,7 @@ if (!b->kobj) goto out_free; -@@ -585,8 +585,9 @@ static __cpuinit int threshold_create_bank(unsigned int cpu, unsigned int bank) +@@ -620,8 +620,9 @@ if (i == cpu) continue; @@ -150,7 +150,7 @@ if (err) goto out; -@@ -649,6 +650,7 @@ static void deallocate_threshold_block(unsigned int cpu, +@@ -684,6 +685,7 @@ static void threshold_remove_bank(unsigned int cpu, int bank) { struct threshold_bank *b; @@ -158,7 +158,7 @@ char name[32]; int i = 0; -@@ -663,7 +665,7 @@ static void threshold_remove_bank(unsigned int cpu, int bank) +@@ -698,7 +700,7 @@ #ifdef CONFIG_SMP /* sibling symlink */ if (shared_bank[bank] && b->blocks->cpu != cpu) { @@ -167,7 +167,7 @@ per_cpu(threshold_banks, cpu)[bank] = NULL; return; -@@ -675,7 +677,9 @@ static void threshold_remove_bank(unsigned int cpu, int bank) +@@ -710,7 +712,9 @@ if (i == cpu) continue; diff -Nru linux-3.2.46/debian/patches/features/all/cpu-devices/Partially-revert-cpufreq-Add-support-for-x86-cpuinfo.patch linux-3.2.46/debian/patches/features/all/cpu-devices/Partially-revert-cpufreq-Add-support-for-x86-cpuinfo.patch --- linux-3.2.46/debian/patches/features/all/cpu-devices/Partially-revert-cpufreq-Add-support-for-x86-cpuinfo.patch 2013-02-24 03:52:33.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/cpu-devices/Partially-revert-cpufreq-Add-support-for-x86-cpuinfo.patch 2013-07-26 19:23:34.000000000 +0000 @@ -12,10 +12,10 @@ drivers/cpufreq/e_powersaver.c | 20 +++++++++----------- 1 file changed, 9 insertions(+), 11 deletions(-) -diff --git a/drivers/cpufreq/e_powersaver.c b/drivers/cpufreq/e_powersaver.c -index 3fffbe6..4bd6815 100644 ---- a/drivers/cpufreq/e_powersaver.c -+++ b/drivers/cpufreq/e_powersaver.c +Index: linux-3.2.46/drivers/cpufreq/e_powersaver.c +=================================================================== +--- linux-3.2.46.orig/drivers/cpufreq/e_powersaver.c 2013-07-26 19:23:23.000000000 +0000 ++++ linux-3.2.46/drivers/cpufreq/e_powersaver.c 2013-07-26 19:23:33.000000000 +0000 @@ -16,7 +16,6 @@ #include #include @@ -24,7 +24,7 @@ #include #include -@@ -438,19 +437,18 @@ static struct cpufreq_driver eps_driver = { +@@ -438,19 +437,18 @@ .attr = eps_attr, }; diff -Nru linux-3.2.46/debian/patches/features/all/cpu-devices/powernow-k6-Really-enable-auto-loading.patch linux-3.2.46/debian/patches/features/all/cpu-devices/powernow-k6-Really-enable-auto-loading.patch --- linux-3.2.46/debian/patches/features/all/cpu-devices/powernow-k6-Really-enable-auto-loading.patch 2013-02-24 03:52:33.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/cpu-devices/powernow-k6-Really-enable-auto-loading.patch 2013-07-26 19:23:32.000000000 +0000 @@ -16,11 +16,11 @@ drivers/cpufreq/powernow-k6.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -diff --git a/drivers/cpufreq/powernow-k6.c b/drivers/cpufreq/powernow-k6.c -index 54dd031..af23e0b 100644 ---- a/drivers/cpufreq/powernow-k6.c -+++ b/drivers/cpufreq/powernow-k6.c -@@ -216,7 +216,7 @@ static const struct x86_cpu_id powernow_k6_ids[] = { +Index: linux-3.2.46/drivers/cpufreq/powernow-k6.c +=================================================================== +--- linux-3.2.46.orig/drivers/cpufreq/powernow-k6.c 2013-07-26 19:23:23.000000000 +0000 ++++ linux-3.2.46/drivers/cpufreq/powernow-k6.c 2013-07-26 19:23:31.000000000 +0000 +@@ -216,7 +216,7 @@ { X86_VENDOR_AMD, 5, 13 }, {} }; diff -Nru linux-3.2.46/debian/patches/features/all/cpu-devices/powernow-k7-Fix-CPU-family-number.patch linux-3.2.46/debian/patches/features/all/cpu-devices/powernow-k7-Fix-CPU-family-number.patch --- linux-3.2.46/debian/patches/features/all/cpu-devices/powernow-k7-Fix-CPU-family-number.patch 2013-02-24 03:52:33.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/cpu-devices/powernow-k7-Fix-CPU-family-number.patch 2013-07-26 19:23:30.000000000 +0000 @@ -16,11 +16,11 @@ drivers/cpufreq/powernow-k7.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -diff --git a/drivers/cpufreq/powernow-k7.c b/drivers/cpufreq/powernow-k7.c -index 501d167..cf7e1ee 100644 ---- a/drivers/cpufreq/powernow-k7.c -+++ b/drivers/cpufreq/powernow-k7.c -@@ -112,7 +112,7 @@ static int check_fsb(unsigned int fsbspeed) +Index: linux-3.2.46/drivers/cpufreq/powernow-k7.c +=================================================================== +--- linux-3.2.46.orig/drivers/cpufreq/powernow-k7.c 2013-07-26 19:23:23.000000000 +0000 ++++ linux-3.2.46/drivers/cpufreq/powernow-k7.c 2013-07-26 19:23:29.000000000 +0000 +@@ -112,7 +112,7 @@ } static const struct x86_cpu_id powernow_k7_cpuids[] = { diff -Nru linux-3.2.46/debian/patches/features/all/cpu-devices/sh-Fix-up-store-queue-code-for-subsys_interface-chan.patch linux-3.2.46/debian/patches/features/all/cpu-devices/sh-Fix-up-store-queue-code-for-subsys_interface-chan.patch --- linux-3.2.46/debian/patches/features/all/cpu-devices/sh-Fix-up-store-queue-code-for-subsys_interface-chan.patch 2013-02-24 03:52:33.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/cpu-devices/sh-Fix-up-store-queue-code-for-subsys_interface-chan.patch 2013-07-26 19:23:39.000000000 +0000 @@ -12,11 +12,11 @@ arch/sh/kernel/cpu/sh4/sq.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) -diff --git a/arch/sh/kernel/cpu/sh4/sq.c b/arch/sh/kernel/cpu/sh4/sq.c -index a8140f0..0a47bd3 100644 ---- a/arch/sh/kernel/cpu/sh4/sq.c -+++ b/arch/sh/kernel/cpu/sh4/sq.c -@@ -337,7 +337,7 @@ static struct kobj_type ktype_percpu_entry = { +Index: linux-3.2.46/arch/sh/kernel/cpu/sh4/sq.c +=================================================================== +--- linux-3.2.46.orig/arch/sh/kernel/cpu/sh4/sq.c 2013-07-26 19:22:53.000000000 +0000 ++++ linux-3.2.46/arch/sh/kernel/cpu/sh4/sq.c 2013-07-26 19:23:39.000000000 +0000 +@@ -337,7 +337,7 @@ .default_attrs = sq_sysfs_attrs, }; @@ -25,7 +25,7 @@ { unsigned int cpu = dev->id; struct kobject *kobj; -@@ -355,7 +355,7 @@ static int __devinit sq_dev_add(struct device *dev) +@@ -355,7 +355,7 @@ return error; } @@ -34,7 +34,7 @@ { unsigned int cpu = dev->id; struct kobject *kobj = sq_kobject[cpu]; -@@ -365,10 +365,10 @@ static int __devexit sq_dev_remove(struct device *dev) +@@ -365,10 +365,10 @@ } static struct subsys_interface sq_interface = { diff -Nru linux-3.2.46/debian/patches/features/all/cpu-devices/topology-Provide-CPU-topology-in-sysfs-in-SMP-configura.patch linux-3.2.46/debian/patches/features/all/cpu-devices/topology-Provide-CPU-topology-in-sysfs-in-SMP-configura.patch --- linux-3.2.46/debian/patches/features/all/cpu-devices/topology-Provide-CPU-topology-in-sysfs-in-SMP-configura.patch 2013-02-24 03:52:33.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/cpu-devices/topology-Provide-CPU-topology-in-sysfs-in-SMP-configura.patch 2013-07-26 19:22:59.000000000 +0000 @@ -17,10 +17,10 @@ drivers/base/Makefile | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) -diff --git a/drivers/base/Makefile b/drivers/base/Makefile -index 99a375a..1334d89 100644 ---- a/drivers/base/Makefile -+++ b/drivers/base/Makefile +Index: linux-3.2.46/drivers/base/Makefile +=================================================================== +--- linux-3.2.46.orig/drivers/base/Makefile 2013-07-26 18:54:45.000000000 +0000 ++++ linux-3.2.46/drivers/base/Makefile 2013-07-26 19:22:58.000000000 +0000 @@ -3,7 +3,8 @@ obj-y := core.o sys.o bus.o dd.o syscore.o \ driver.o class.o platform.o \ @@ -31,7 +31,7 @@ obj-$(CONFIG_DEVTMPFS) += devtmpfs.o obj-y += power/ obj-$(CONFIG_HAS_DMA) += dma-mapping.o -@@ -12,7 +13,6 @@ obj-$(CONFIG_ISA) += isa.o +@@ -12,7 +13,6 @@ obj-$(CONFIG_FW_LOADER) += firmware_class.o obj-$(CONFIG_NUMA) += node.o obj-$(CONFIG_MEMORY_HOTPLUG_SPARSE) += memory.o @@ -39,6 +39,3 @@ ifeq ($(CONFIG_SYSFS),y) obj-$(CONFIG_MODULES) += module.o endif --- -1.7.7.3 - diff -Nru linux-3.2.46/debian/patches/features/all/cpu-devices/tracing-mm-Move-include-of-trace-events-kmem.h-out-o.patch linux-3.2.46/debian/patches/features/all/cpu-devices/tracing-mm-Move-include-of-trace-events-kmem.h-out-o.patch --- linux-3.2.46/debian/patches/features/all/cpu-devices/tracing-mm-Move-include-of-trace-events-kmem.h-out-o.patch 2013-02-24 03:52:33.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/cpu-devices/tracing-mm-Move-include-of-trace-events-kmem.h-out-o.patch 2013-07-26 19:23:37.000000000 +0000 @@ -25,10 +25,10 @@ mm/slab.c | 2 ++ 2 files changed, 2 insertions(+), 2 deletions(-) -diff --git a/include/linux/slab_def.h b/include/linux/slab_def.h -index d00e0ba..fbd1117 100644 ---- a/include/linux/slab_def.h -+++ b/include/linux/slab_def.h +Index: linux-3.2.46/include/linux/slab_def.h +=================================================================== +--- linux-3.2.46.orig/include/linux/slab_def.h 2013-07-26 18:54:33.000000000 +0000 ++++ linux-3.2.46/include/linux/slab_def.h 2013-07-26 19:23:36.000000000 +0000 @@ -15,8 +15,6 @@ #include /* kmalloc_sizes.h needs L1_CACHE_BYTES */ #include @@ -38,10 +38,10 @@ /* * struct kmem_cache * -diff --git a/mm/slab.c b/mm/slab.c -index 83311c9a..2acfa0d 100644 ---- a/mm/slab.c -+++ b/mm/slab.c +Index: linux-3.2.46/mm/slab.c +=================================================================== +--- linux-3.2.46.orig/mm/slab.c 2013-07-26 18:54:33.000000000 +0000 ++++ linux-3.2.46/mm/slab.c 2013-07-26 19:23:36.000000000 +0000 @@ -121,6 +121,8 @@ #include #include diff -Nru linux-3.2.46/debian/patches/features/all/cpu-devices/x86-cpu-Clean-up-modalias-feature-matching.patch linux-3.2.46/debian/patches/features/all/cpu-devices/x86-cpu-Clean-up-modalias-feature-matching.patch --- linux-3.2.46/debian/patches/features/all/cpu-devices/x86-cpu-Clean-up-modalias-feature-matching.patch 2013-02-24 03:52:33.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/cpu-devices/x86-cpu-Clean-up-modalias-feature-matching.patch 2013-07-26 19:23:28.000000000 +0000 @@ -22,8 +22,10 @@ scripts/mod/file2alias.c | 5 +++-- 2 files changed, 4 insertions(+), 4 deletions(-) ---- a/arch/x86/kernel/cpu/match.c -+++ b/arch/x86/kernel/cpu/match.c +Index: linux-3.2.46/arch/x86/kernel/cpu/match.c +=================================================================== +--- linux-3.2.46.orig/arch/x86/kernel/cpu/match.c 2013-07-26 19:23:26.000000000 +0000 ++++ linux-3.2.46/arch/x86/kernel/cpu/match.c 2013-07-26 19:23:27.000000000 +0000 @@ -63,7 +63,7 @@ boot_cpu_data.x86_model); size -= n; @@ -41,8 +43,10 @@ *buf++ = '\n'; return buf - bufptr; } ---- a/scripts/mod/file2alias.c -+++ b/scripts/mod/file2alias.c +Index: linux-3.2.46/scripts/mod/file2alias.c +=================================================================== +--- linux-3.2.46.orig/scripts/mod/file2alias.c 2013-07-26 19:23:09.000000000 +0000 ++++ linux-3.2.46/scripts/mod/file2alias.c 2013-07-26 19:23:27.000000000 +0000 @@ -898,8 +898,9 @@ ADD(alias, "vendor:", id->vendor != X86_VENDOR_ANY, id->vendor); ADD(alias, ":family:", id->family != X86_FAMILY_ANY, id->family); diff -Nru linux-3.2.46/debian/patches/features/all/cpu-devices/x86-cpufeature-Rename-X86_FEATURE_DTS-to-X86_FEATURE.patch linux-3.2.46/debian/patches/features/all/cpu-devices/x86-cpufeature-Rename-X86_FEATURE_DTS-to-X86_FEATURE.patch --- linux-3.2.46/debian/patches/features/all/cpu-devices/x86-cpufeature-Rename-X86_FEATURE_DTS-to-X86_FEATURE.patch 2013-02-24 03:52:33.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/cpu-devices/x86-cpufeature-Rename-X86_FEATURE_DTS-to-X86_FEATURE.patch 2013-07-26 19:23:41.000000000 +0000 @@ -22,9 +22,11 @@ [bwh: Most of this was applied in 3.2.22; just apply the device table change which didn't belong there] --- ---- a/drivers/hwmon/coretemp.c -+++ b/drivers/hwmon/coretemp.c -@@ -762,7 +762,7 @@ static struct notifier_block coretemp_cp +Index: linux-3.2.46/drivers/hwmon/coretemp.c +=================================================================== +--- linux-3.2.46.orig/drivers/hwmon/coretemp.c 2013-07-26 19:23:20.000000000 +0000 ++++ linux-3.2.46/drivers/hwmon/coretemp.c 2013-07-26 19:23:40.000000000 +0000 +@@ -793,7 +793,7 @@ }; static const struct x86_cpu_id coretemp_ids[] = { diff -Nru linux-3.2.46/debian/patches/features/all/cpu-devices/x86-cpu-Fix-overrun-check-in-arch_print_cpu_modalias.patch linux-3.2.46/debian/patches/features/all/cpu-devices/x86-cpu-Fix-overrun-check-in-arch_print_cpu_modalias.patch --- linux-3.2.46/debian/patches/features/all/cpu-devices/x86-cpu-Fix-overrun-check-in-arch_print_cpu_modalias.patch 2013-02-24 03:52:33.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/cpu-devices/x86-cpu-Fix-overrun-check-in-arch_print_cpu_modalias.patch 2013-07-26 19:23:26.000000000 +0000 @@ -14,11 +14,11 @@ arch/x86/kernel/cpu/match.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -diff --git a/arch/x86/kernel/cpu/match.c b/arch/x86/kernel/cpu/match.c -index 940e2d4..2dfa52b 100644 ---- a/arch/x86/kernel/cpu/match.c -+++ b/arch/x86/kernel/cpu/match.c -@@ -67,7 +67,7 @@ ssize_t arch_print_cpu_modalias(struct device *dev, +Index: linux-3.2.46/arch/x86/kernel/cpu/match.c +=================================================================== +--- linux-3.2.46.orig/arch/x86/kernel/cpu/match.c 2013-07-26 19:23:10.000000000 +0000 ++++ linux-3.2.46/arch/x86/kernel/cpu/match.c 2013-07-26 19:23:26.000000000 +0000 +@@ -67,7 +67,7 @@ for (i = 0; i < NCAPINTS*32; i++) { if (boot_cpu_has(i)) { n = snprintf(buf, size, ",%04X", i); diff -Nru linux-3.2.46/debian/patches/features/all/cpu-devices/X86-Introduce-HW-Pstate-scattered-cpuid-feature.patch linux-3.2.46/debian/patches/features/all/cpu-devices/X86-Introduce-HW-Pstate-scattered-cpuid-feature.patch --- linux-3.2.46/debian/patches/features/all/cpu-devices/X86-Introduce-HW-Pstate-scattered-cpuid-feature.patch 2013-02-24 03:52:33.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/cpu-devices/X86-Introduce-HW-Pstate-scattered-cpuid-feature.patch 2013-07-26 19:23:23.000000000 +0000 @@ -22,8 +22,10 @@ arch/x86/kernel/cpu/scattered.c | 1 + 2 files changed, 2 insertions(+) ---- a/arch/x86/include/asm/cpufeature.h -+++ b/arch/x86/include/asm/cpufeature.h +Index: linux-3.2.46/arch/x86/include/asm/cpufeature.h +=================================================================== +--- linux-3.2.46.orig/arch/x86/include/asm/cpufeature.h 2013-07-26 18:54:37.000000000 +0000 ++++ linux-3.2.46/arch/x86/include/asm/cpufeature.h 2013-07-26 19:23:22.000000000 +0000 @@ -176,6 +176,7 @@ #define X86_FEATURE_PLN (7*32+ 5) /* Intel Power Limit Notification */ #define X86_FEATURE_PTS (7*32+ 6) /* Intel Package Thermal Status */ @@ -32,9 +34,11 @@ /* Virtualization flags: Linux defined, word 8 */ #define X86_FEATURE_TPR_SHADOW (8*32+ 0) /* Intel TPR Shadow */ ---- a/arch/x86/kernel/cpu/scattered.c -+++ b/arch/x86/kernel/cpu/scattered.c -@@ -40,6 +40,7 @@ void __cpuinit init_scattered_cpuid_features(struct cpuinfo_x86 *c) +Index: linux-3.2.46/arch/x86/kernel/cpu/scattered.c +=================================================================== +--- linux-3.2.46.orig/arch/x86/kernel/cpu/scattered.c 2013-07-26 18:54:37.000000000 +0000 ++++ linux-3.2.46/arch/x86/kernel/cpu/scattered.c 2013-07-26 19:23:22.000000000 +0000 +@@ -40,6 +40,7 @@ { X86_FEATURE_EPB, CR_ECX, 3, 0x00000006, 0 }, { X86_FEATURE_XSAVEOPT, CR_EAX, 0, 0x0000000d, 1 }, { X86_FEATURE_CPB, CR_EDX, 9, 0x80000007, 0 }, diff -Nru linux-3.2.46/debian/patches/features/all/cpu-devices/x86-mce-Convert-static-array-of-pointers-to-per-cpu-.patch linux-3.2.46/debian/patches/features/all/cpu-devices/x86-mce-Convert-static-array-of-pointers-to-per-cpu-.patch --- linux-3.2.46/debian/patches/features/all/cpu-devices/x86-mce-Convert-static-array-of-pointers-to-per-cpu-.patch 2013-02-24 03:52:33.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/cpu-devices/x86-mce-Convert-static-array-of-pointers-to-per-cpu-.patch 2013-07-26 19:23:08.000000000 +0000 @@ -21,11 +21,11 @@ arch/x86/kernel/cpu/mcheck/mce_amd.c | 9 +++++---- 3 files changed, 10 insertions(+), 9 deletions(-) -diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h -index 6aefb14..441520e 100644 ---- a/arch/x86/include/asm/mce.h -+++ b/arch/x86/include/asm/mce.h -@@ -151,7 +151,7 @@ static inline void enable_p5_mce(void) {} +Index: linux-3.2.46/arch/x86/include/asm/mce.h +=================================================================== +--- linux-3.2.46.orig/arch/x86/include/asm/mce.h 2013-07-26 19:23:06.000000000 +0000 ++++ linux-3.2.46/arch/x86/include/asm/mce.h 2013-07-26 19:23:07.000000000 +0000 +@@ -149,7 +149,7 @@ void mce_setup(struct mce *m); void mce_log(struct mce *m); @@ -34,11 +34,11 @@ /* * Maximum banks number. -diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c -index 5a11ae2..4979a5d 100644 ---- a/arch/x86/kernel/cpu/mcheck/mce.c -+++ b/arch/x86/kernel/cpu/mcheck/mce.c -@@ -1859,7 +1859,7 @@ static struct bus_type mce_subsys = { +Index: linux-3.2.46/arch/x86/kernel/cpu/mcheck/mce.c +=================================================================== +--- linux-3.2.46.orig/arch/x86/kernel/cpu/mcheck/mce.c 2013-07-26 19:23:06.000000000 +0000 ++++ linux-3.2.46/arch/x86/kernel/cpu/mcheck/mce.c 2013-07-26 19:23:07.000000000 +0000 +@@ -1817,7 +1817,7 @@ .dev_name = "machinecheck", }; @@ -47,7 +47,7 @@ __cpuinitdata void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu); -@@ -2038,7 +2038,7 @@ static __cpuinit int mce_device_create(unsigned int cpu) +@@ -1996,7 +1996,7 @@ goto error2; } cpumask_set_cpu(cpu, mce_device_initialized); @@ -56,7 +56,7 @@ return 0; error2: -@@ -2055,7 +2055,7 @@ error: +@@ -2013,7 +2013,7 @@ static __cpuinit void mce_device_remove(unsigned int cpu) { @@ -65,7 +65,7 @@ int i; if (!cpumask_test_cpu(cpu, mce_device_initialized)) -@@ -2069,7 +2069,7 @@ static __cpuinit void mce_device_remove(unsigned int cpu) +@@ -2027,7 +2027,7 @@ device_unregister(dev); cpumask_clear_cpu(cpu, mce_device_initialized); @@ -74,11 +74,11 @@ } /* Make sure there are no machine checks on offlined CPUs. */ -diff --git a/arch/x86/kernel/cpu/mcheck/mce_amd.c b/arch/x86/kernel/cpu/mcheck/mce_amd.c -index 786e76a..a4bf9d2 100644 ---- a/arch/x86/kernel/cpu/mcheck/mce_amd.c -+++ b/arch/x86/kernel/cpu/mcheck/mce_amd.c -@@ -523,7 +523,7 @@ static __cpuinit int threshold_create_bank(unsigned int cpu, unsigned int bank) +Index: linux-3.2.46/arch/x86/kernel/cpu/mcheck/mce_amd.c +=================================================================== +--- linux-3.2.46.orig/arch/x86/kernel/cpu/mcheck/mce_amd.c 2013-07-26 19:23:06.000000000 +0000 ++++ linux-3.2.46/arch/x86/kernel/cpu/mcheck/mce_amd.c 2013-07-26 19:23:07.000000000 +0000 +@@ -556,7 +556,7 @@ { int i, err = 0; struct threshold_bank *b = NULL; @@ -87,7 +87,7 @@ char name[32]; sprintf(name, "threshold_bank%i", bank); -@@ -585,7 +585,7 @@ static __cpuinit int threshold_create_bank(unsigned int cpu, unsigned int bank) +@@ -620,7 +620,7 @@ if (i == cpu) continue; @@ -96,7 +96,7 @@ if (dev) err = sysfs_create_link(&dev->kobj,b->kobj, name); if (err) -@@ -665,7 +665,8 @@ static void threshold_remove_bank(unsigned int cpu, int bank) +@@ -700,7 +700,8 @@ #ifdef CONFIG_SMP /* sibling symlink */ if (shared_bank[bank] && b->blocks->cpu != cpu) { @@ -106,7 +106,7 @@ per_cpu(threshold_banks, cpu)[bank] = NULL; return; -@@ -677,7 +678,7 @@ static void threshold_remove_bank(unsigned int cpu, int bank) +@@ -712,7 +713,7 @@ if (i == cpu) continue; diff -Nru linux-3.2.46/debian/patches/features/all/cpu-devices/x86-mce-Fix-CPU-hotplug-and-suspend-regression-relat.patch linux-3.2.46/debian/patches/features/all/cpu-devices/x86-mce-Fix-CPU-hotplug-and-suspend-regression-relat.patch --- linux-3.2.46/debian/patches/features/all/cpu-devices/x86-mce-Fix-CPU-hotplug-and-suspend-regression-relat.patch 2013-02-24 03:52:33.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/cpu-devices/x86-mce-Fix-CPU-hotplug-and-suspend-regression-relat.patch 2013-07-26 19:23:05.000000000 +0000 @@ -20,11 +20,11 @@ arch/x86/kernel/cpu/mcheck/mce.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c -index f22a9f7..29ba329 100644 ---- a/arch/x86/kernel/cpu/mcheck/mce.c -+++ b/arch/x86/kernel/cpu/mcheck/mce.c -@@ -2011,7 +2011,7 @@ static __cpuinit int mce_device_create(unsigned int cpu) +Index: linux-3.2.46/arch/x86/kernel/cpu/mcheck/mce.c +=================================================================== +--- linux-3.2.46.orig/arch/x86/kernel/cpu/mcheck/mce.c 2013-07-26 19:22:54.000000000 +0000 ++++ linux-3.2.46/arch/x86/kernel/cpu/mcheck/mce.c 2013-07-26 19:23:04.000000000 +0000 +@@ -1969,7 +1969,7 @@ if (!mce_available(&boot_cpu_data)) return -EIO; diff -Nru linux-3.2.46/debian/patches/features/all/debugfs-add-mode-uid-and-gid-options.patch linux-3.2.46/debian/patches/features/all/debugfs-add-mode-uid-and-gid-options.patch --- linux-3.2.46/debian/patches/features/all/debugfs-add-mode-uid-and-gid-options.patch 2013-02-24 03:52:32.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/debugfs-add-mode-uid-and-gid-options.patch 2013-07-26 19:24:08.000000000 +0000 @@ -20,9 +20,11 @@ fs/debugfs/inode.c | 149 ++++++++++++++++++++++++++++++++- 2 files changed, 152 insertions(+), 2 deletions(-) ---- a/Documentation/filesystems/debugfs.txt -+++ b/Documentation/filesystems/debugfs.txt -@@ -14,7 +14,10 @@ Debugfs is typically mounted with a comm +Index: linux-3.2.46/Documentation/filesystems/debugfs.txt +=================================================================== +--- linux-3.2.46.orig/Documentation/filesystems/debugfs.txt 2013-07-26 18:54:22.000000000 +0000 ++++ linux-3.2.46/Documentation/filesystems/debugfs.txt 2013-07-26 19:24:07.000000000 +0000 +@@ -14,7 +14,10 @@ mount -t debugfs none /sys/kernel/debug @@ -34,8 +36,10 @@ Note that the debugfs API is exported GPL-only to modules. ---- a/fs/debugfs/inode.c -+++ b/fs/debugfs/inode.c +Index: linux-3.2.46/fs/debugfs/inode.c +=================================================================== +--- linux-3.2.46.orig/fs/debugfs/inode.c 2013-07-26 18:54:22.000000000 +0000 ++++ linux-3.2.46/fs/debugfs/inode.c 2013-07-26 19:24:07.000000000 +0000 @@ -23,9 +23,13 @@ #include #include @@ -50,7 +54,7 @@ static struct vfsmount *debugfs_mount; static int debugfs_mount_count; static bool debugfs_registered; -@@ -125,11 +129,154 @@ static inline int debugfs_positive(struc +@@ -125,11 +129,154 @@ return dentry->d_inode && !d_unhashed(dentry); } diff -Nru linux-3.2.46/debian/patches/features/all/drivercore-Generalize-module_platform_driver.patch linux-3.2.46/debian/patches/features/all/drivercore-Generalize-module_platform_driver.patch --- linux-3.2.46/debian/patches/features/all/drivercore-Generalize-module_platform_driver.patch 2013-02-24 03:52:42.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/drivercore-Generalize-module_platform_driver.patch 2013-07-26 19:25:45.000000000 +0000 @@ -25,11 +25,11 @@ include/linux/platform_device.h | 12 ++---------- 2 files changed, 23 insertions(+), 10 deletions(-) -diff --git a/include/linux/device.h b/include/linux/device.h -index c633598..341fb74 100644 ---- a/include/linux/device.h -+++ b/include/linux/device.h -@@ -922,4 +922,25 @@ extern long sysfs_deprecated; +Index: linux-3.2.46/include/linux/device.h +=================================================================== +--- linux-3.2.46.orig/include/linux/device.h 2013-07-26 19:23:37.000000000 +0000 ++++ linux-3.2.46/include/linux/device.h 2013-07-26 19:25:44.000000000 +0000 +@@ -994,4 +994,25 @@ #define sysfs_deprecated 0 #endif @@ -55,11 +55,11 @@ +module_exit(__driver##_exit); + #endif /* _DEVICE_H_ */ -diff --git a/include/linux/platform_device.h b/include/linux/platform_device.h -index 2a23f7d..165a8d1 100644 ---- a/include/linux/platform_device.h -+++ b/include/linux/platform_device.h -@@ -196,16 +196,8 @@ static inline void platform_set_drvdata(struct platform_device *pdev, void *data +Index: linux-3.2.46/include/linux/platform_device.h +=================================================================== +--- linux-3.2.46.orig/include/linux/platform_device.h 2013-07-26 18:53:46.000000000 +0000 ++++ linux-3.2.46/include/linux/platform_device.h 2013-07-26 19:25:45.000000000 +0000 +@@ -196,16 +196,8 @@ * calling it replaces module_init() and module_exit() */ #define module_platform_driver(__platform_driver) \ diff -Nru linux-3.2.46/debian/patches/features/all/drivers-media-dvb-usb-af9005-request_firmware.patch linux-3.2.46/debian/patches/features/all/drivers-media-dvb-usb-af9005-request_firmware.patch --- linux-3.2.46/debian/patches/features/all/drivers-media-dvb-usb-af9005-request_firmware.patch 2013-02-24 03:52:36.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/drivers-media-dvb-usb-af9005-request_firmware.patch 2013-07-26 19:16:49.000000000 +0000 @@ -11,11 +11,11 @@ drivers/media/dvb/dvb-usb/af9005-fe.c | 66 ++++++++++++++++++++++++++------ 2 files changed, 54 insertions(+), 14 deletions(-) -diff --git a/drivers/media/dvb/dvb-usb/Kconfig b/drivers/media/dvb/dvb-usb/Kconfig -index 868e1cb..1c3d56d 100644 ---- a/drivers/media/dvb/dvb-usb/Kconfig -+++ b/drivers/media/dvb/dvb-usb/Kconfig -@@ -238,10 +238,10 @@ config DVB_USB_OPERA1 +Index: linux-3.2.46/drivers/media/dvb/dvb-usb/Kconfig +=================================================================== +--- linux-3.2.46.orig/drivers/media/dvb/dvb-usb/Kconfig 2013-07-26 18:56:43.000000000 +0000 ++++ linux-3.2.46/drivers/media/dvb/dvb-usb/Kconfig 2013-07-26 19:16:48.000000000 +0000 +@@ -244,10 +244,10 @@ config DVB_USB_AF9005 tristate "Afatech AF9005 DVB-T USB1.1 support" @@ -27,10 +27,10 @@ help Say Y here to support the Afatech AF9005 based DVB-T USB1.1 receiver and the TerraTec Cinergy T USB XE (Rev.1) -diff --git a/drivers/media/dvb/dvb-usb/af9005-fe.c b/drivers/media/dvb/dvb-usb/af9005-fe.c -index 199ece0..bcc26c8 100644 ---- a/drivers/media/dvb/dvb-usb/af9005-fe.c -+++ b/drivers/media/dvb/dvb-usb/af9005-fe.c +Index: linux-3.2.46/drivers/media/dvb/dvb-usb/af9005-fe.c +=================================================================== +--- linux-3.2.46.orig/drivers/media/dvb/dvb-usb/af9005-fe.c 2013-07-26 18:56:43.000000000 +0000 ++++ linux-3.2.46/drivers/media/dvb/dvb-usb/af9005-fe.c 2013-07-26 19:16:48.000000000 +0000 @@ -22,10 +22,26 @@ * see Documentation/dvb/README.dvb-usb for more information */ @@ -59,7 +59,7 @@ struct af9005_fe_state { struct dvb_usb_device *d; -@@ -818,6 +834,8 @@ static int af9005_fe_init(struct dvb_frontend *fe) +@@ -816,6 +832,8 @@ { struct af9005_fe_state *state = fe->demodulator_priv; struct dvb_usb_adapter *adap = fe->dvb->priv; @@ -68,7 +68,7 @@ int ret, i, scriptlen; u8 temp, temp0 = 0, temp1 = 0, temp2 = 0; u8 buf[2]; -@@ -969,37 +987,55 @@ static int af9005_fe_init(struct dvb_frontend *fe) +@@ -967,37 +985,55 @@ if ((ret = af9005_write_ofdm_register(state->d, 0xaefb, 0x01))) return ret; @@ -136,7 +136,7 @@ /* save original TOPs */ deb_info("save original TOPs\n"); -@@ -1079,6 +1115,10 @@ static int af9005_fe_init(struct dvb_frontend *fe) +@@ -1077,6 +1113,10 @@ deb_info("profit!\n"); return 0; @@ -147,6 +147,3 @@ } static int af9005_fe_sleep(struct dvb_frontend *fe) --- -1.6.3.3 - diff -Nru linux-3.2.46/debian/patches/features/all/drm/drm-3.4.patch linux-3.2.46/debian/patches/features/all/drm/drm-3.4.patch --- linux-3.2.46/debian/patches/features/all/drm/drm-3.4.patch 2013-06-05 03:28:46.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/drm/drm-3.4.patch 2013-07-26 19:26:54.000000000 +0000 @@ -1,7 +1,7 @@ -diff --git a/drivers/char/agp/amd64-agp.c b/drivers/char/agp/amd64-agp.c -index 780498d..444f8b6 100644 ---- a/drivers/char/agp/amd64-agp.c -+++ b/drivers/char/agp/amd64-agp.c +Index: linux-3.2.46/drivers/char/agp/amd64-agp.c +=================================================================== +--- linux-3.2.46.orig/drivers/char/agp/amd64-agp.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/char/agp/amd64-agp.c 2013-07-26 19:26:21.000000000 +0000 @@ -33,7 +33,7 @@ #define ULI_X86_64_ENU_SCR_REG 0x54 @@ -11,11 +11,11 @@ static int agp_bridges_found; static void amd64_tlbflush(struct agp_memory *temp) -diff --git a/drivers/char/agp/backend.c b/drivers/char/agp/backend.c -index 4b71647..317c28c 100644 ---- a/drivers/char/agp/backend.c -+++ b/drivers/char/agp/backend.c -@@ -194,10 +194,10 @@ static int agp_backend_initialize(struct agp_bridge_data *bridge) +Index: linux-3.2.46/drivers/char/agp/backend.c +=================================================================== +--- linux-3.2.46.orig/drivers/char/agp/backend.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/char/agp/backend.c 2013-07-26 19:26:21.000000000 +0000 +@@ -194,10 +194,10 @@ err_out: if (bridge->driver->needs_scratch_page) { @@ -29,7 +29,7 @@ } if (got_gatt) bridge->driver->free_gatt_table(bridge); -@@ -221,10 +221,10 @@ static void agp_backend_cleanup(struct agp_bridge_data *bridge) +@@ -221,10 +221,10 @@ if (bridge->driver->agp_destroy_page && bridge->driver->needs_scratch_page) { @@ -43,11 +43,11 @@ } } -diff --git a/drivers/char/agp/generic.c b/drivers/char/agp/generic.c -index b072648..17e05d1 100644 ---- a/drivers/char/agp/generic.c -+++ b/drivers/char/agp/generic.c -@@ -514,12 +514,12 @@ static void agp_v2_parse_one(u32 *requested_mode, u32 *bridge_agpstat, u32 *vga_ +Index: linux-3.2.46/drivers/char/agp/generic.c +=================================================================== +--- linux-3.2.46.orig/drivers/char/agp/generic.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/char/agp/generic.c 2013-07-26 19:26:21.000000000 +0000 +@@ -514,12 +514,12 @@ switch (*bridge_agpstat & 7) { case 4: *bridge_agpstat |= (AGPSTAT2_2X | AGPSTAT2_1X); @@ -62,7 +62,7 @@ "Fixing up support for x1\n"); break; default: -@@ -693,7 +693,7 @@ static void agp_v3_parse_one(u32 *requested_mode, u32 *bridge_agpstat, u32 *vga_ +@@ -693,7 +693,7 @@ *bridge_agpstat &= ~(AGPSTAT3_4X | AGPSTAT3_RSVD); *vga_agpstat &= ~(AGPSTAT3_4X | AGPSTAT3_RSVD); } else { @@ -71,7 +71,7 @@ if (!(*bridge_agpstat & AGPSTAT3_8X)) { printk(KERN_INFO PFX "bridge couldn't do x8. bridge_agpstat:%x (orig=%x)\n", *bridge_agpstat, origbridge); -@@ -956,7 +956,7 @@ int agp_generic_create_gatt_table(struct agp_bridge_data *bridge) +@@ -956,7 +956,7 @@ bridge->driver->cache_flush(); #ifdef CONFIG_X86 if (set_memory_uc((unsigned long)table, 1 << page_order)) @@ -80,11 +80,11 @@ bridge->gatt_table = (void *)table; #else -diff --git a/drivers/char/agp/intel-agp.c b/drivers/char/agp/intel-agp.c -index 58b49d1..4293c48 100644 ---- a/drivers/char/agp/intel-agp.c -+++ b/drivers/char/agp/intel-agp.c -@@ -850,6 +850,7 @@ static struct pci_device_id agp_intel_pci_table[] = { +Index: linux-3.2.46/drivers/char/agp/intel-agp.c +=================================================================== +--- linux-3.2.46.orig/drivers/char/agp/intel-agp.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/char/agp/intel-agp.c 2013-07-26 19:26:21.000000000 +0000 +@@ -850,6 +850,7 @@ .subvendor = PCI_ANY_ID, \ .subdevice = PCI_ANY_ID, \ } @@ -92,11 +92,11 @@ ID(PCI_DEVICE_ID_INTEL_82443LX_0), ID(PCI_DEVICE_ID_INTEL_82443BX_0), ID(PCI_DEVICE_ID_INTEL_82443GX_0), -diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c -index 43c4ec3..7f025fb 100644 ---- a/drivers/char/agp/intel-gtt.c -+++ b/drivers/char/agp/intel-gtt.c -@@ -76,7 +76,6 @@ static struct _intel_private { +Index: linux-3.2.46/drivers/char/agp/intel-gtt.c +=================================================================== +--- linux-3.2.46.orig/drivers/char/agp/intel-gtt.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/char/agp/intel-gtt.c 2013-07-26 19:26:21.000000000 +0000 +@@ -76,7 +76,6 @@ struct resource ifp_resource; int resource_valid; struct page *scratch_page; @@ -104,7 +104,7 @@ } intel_private; #define INTEL_GTT_GEN intel_private.driver->gen -@@ -306,9 +305,9 @@ static int intel_gtt_setup_scratch_page(void) +@@ -306,9 +305,9 @@ if (pci_dma_mapping_error(intel_private.pcidev, dma_addr)) return -EINVAL; @@ -116,7 +116,7 @@ intel_private.scratch_page = page; -@@ -631,7 +630,7 @@ static unsigned int intel_gtt_mappable_entries(void) +@@ -631,7 +630,7 @@ static void intel_gtt_teardown_scratch_page(void) { set_pages_wb(intel_private.scratch_page, 1); @@ -125,7 +125,7 @@ PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); put_page(intel_private.scratch_page); __free_page(intel_private.scratch_page); -@@ -681,6 +680,7 @@ static int intel_gtt_init(void) +@@ -681,6 +680,7 @@ iounmap(intel_private.registers); return -ENOMEM; } @@ -133,7 +133,7 @@ global_cache_flush(); /* FIXME: ? */ -@@ -975,7 +975,7 @@ void intel_gtt_clear_range(unsigned int first_entry, unsigned int num_entries) +@@ -975,7 +975,7 @@ unsigned int i; for (i = first_entry; i < (first_entry + num_entries); i++) { @@ -142,7 +142,7 @@ i, 0); } readl(intel_private.gtt+i-1); -@@ -1190,7 +1190,6 @@ static inline int needs_idle_maps(void) +@@ -1190,7 +1190,6 @@ { #ifdef CONFIG_INTEL_IOMMU const unsigned short gpu_devid = intel_private.pcidev->device; @@ -150,10 +150,10 @@ /* Query intel_iommu to see if we need the workaround. Presumably that * was loaded first. -diff --git a/drivers/char/agp/sis-agp.c b/drivers/char/agp/sis-agp.c -index 29aacd8..08704ae 100644 ---- a/drivers/char/agp/sis-agp.c -+++ b/drivers/char/agp/sis-agp.c +Index: linux-3.2.46/drivers/char/agp/sis-agp.c +=================================================================== +--- linux-3.2.46.orig/drivers/char/agp/sis-agp.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/char/agp/sis-agp.c 2013-07-26 19:26:21.000000000 +0000 @@ -17,7 +17,7 @@ #define PCI_DEVICE_ID_SI_662 0x0662 #define PCI_DEVICE_ID_SI_671 0x0671 @@ -163,11 +163,11 @@ static int __devinitdata agp_sis_agp_spec = -1; static int sis_fetch_size(void) -diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig -index 1368826..e354bc0 100644 ---- a/drivers/gpu/drm/Kconfig -+++ b/drivers/gpu/drm/Kconfig -@@ -9,6 +9,7 @@ menuconfig DRM +Index: linux-3.2.46/drivers/gpu/drm/Kconfig +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/Kconfig 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/Kconfig 2013-07-26 19:26:21.000000000 +0000 +@@ -9,6 +9,7 @@ depends on (AGP || AGP=n) && !EMULATED_CMPXCHG && MMU select I2C select I2C_ALGOBIT @@ -175,7 +175,7 @@ help Kernel-level support for the Direct Rendering Infrastructure (DRI) introduced in XFree86 4.0. If you say Y here, you need to select -@@ -18,6 +19,11 @@ menuconfig DRM +@@ -18,6 +19,11 @@ details. You should also select and configure AGP (/dev/agpgart) support if it is available for your platform. @@ -187,7 +187,7 @@ config DRM_KMS_HELPER tristate depends on DRM -@@ -27,6 +33,18 @@ config DRM_KMS_HELPER +@@ -27,6 +33,18 @@ help FB and CRTC helpers for KMS drivers. @@ -206,7 +206,7 @@ config DRM_TTM tristate depends on DRM -@@ -71,6 +89,8 @@ config DRM_RADEON +@@ -71,6 +89,8 @@ source "drivers/gpu/drm/radeon/Kconfig" @@ -215,7 +215,7 @@ config DRM_I810 tristate "Intel I810" # !PREEMPT because of missing ioctl locking -@@ -162,3 +182,7 @@ config DRM_SAVAGE +@@ -162,3 +182,7 @@ source "drivers/gpu/drm/exynos/Kconfig" source "drivers/gpu/drm/vmwgfx/Kconfig" @@ -223,11 +223,11 @@ +source "drivers/gpu/drm/gma500/Kconfig" + +source "drivers/gpu/drm/udl/Kconfig" -diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile -index c0496f6..c20da5b 100644 ---- a/drivers/gpu/drm/Makefile -+++ b/drivers/gpu/drm/Makefile -@@ -9,20 +9,24 @@ drm-y := drm_auth.o drm_buffer.o drm_bufs.o drm_cache.o \ +Index: linux-3.2.46/drivers/gpu/drm/Makefile +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/Makefile 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/Makefile 2013-07-26 19:26:21.000000000 +0000 +@@ -9,20 +9,24 @@ drm_drv.o drm_fops.o drm_gem.o drm_ioctl.o drm_irq.o \ drm_lock.o drm_memory.o drm_proc.o drm_stub.o drm_vm.o \ drm_agpsupport.o drm_scatter.o ati_pcigart.o drm_pci.o \ @@ -254,18 +254,18 @@ obj-$(CONFIG_DRM_TTM) += ttm/ obj-$(CONFIG_DRM_TDFX) += tdfx/ obj-$(CONFIG_DRM_R128) += r128/ -@@ -36,4 +40,6 @@ obj-$(CONFIG_DRM_VMWGFX)+= vmwgfx/ +@@ -36,4 +40,6 @@ obj-$(CONFIG_DRM_VIA) +=via/ obj-$(CONFIG_DRM_NOUVEAU) +=nouveau/ obj-$(CONFIG_DRM_EXYNOS) +=exynos/ +obj-$(CONFIG_DRM_GMA500) += gma500/ +obj-$(CONFIG_DRM_UDL) += udl/ obj-y += i2c/ -diff --git a/drivers/gpu/drm/drm_bufs.c b/drivers/gpu/drm/drm_bufs.c -index 30372f7..348b367 100644 ---- a/drivers/gpu/drm/drm_bufs.c -+++ b/drivers/gpu/drm/drm_bufs.c -@@ -1510,8 +1510,8 @@ int drm_freebufs(struct drm_device *dev, void *data, +Index: linux-3.2.46/drivers/gpu/drm/drm_bufs.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/drm_bufs.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/drm_bufs.c 2013-07-26 19:26:21.000000000 +0000 +@@ -1510,8 +1510,8 @@ * \param arg pointer to a drm_buf_map structure. * \return zero on success or a negative number on failure. * @@ -276,7 +276,7 @@ * offset equal to 0, which drm_mmap() interpretes as PCI buffers and calls * drm_mmap_dma(). */ -@@ -1553,18 +1553,14 @@ int drm_mapbufs(struct drm_device *dev, void *data, +@@ -1553,18 +1553,14 @@ retcode = -EINVAL; goto done; } @@ -297,11 +297,11 @@ } if (virtual > -1024UL) { /* Real error */ -diff --git a/drivers/gpu/drm/drm_cache.c b/drivers/gpu/drm/drm_cache.c -index 5928653..4b8653b 100644 ---- a/drivers/gpu/drm/drm_cache.c -+++ b/drivers/gpu/drm/drm_cache.c -@@ -41,10 +41,10 @@ drm_clflush_page(struct page *page) +Index: linux-3.2.46/drivers/gpu/drm/drm_cache.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/drm_cache.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/drm_cache.c 2013-07-26 19:26:21.000000000 +0000 +@@ -41,10 +41,10 @@ if (unlikely(page == NULL)) return; @@ -314,7 +314,7 @@ } static void drm_cache_flush_clflush(struct page *pages[], -@@ -87,10 +87,10 @@ drm_clflush_pages(struct page *pages[], unsigned long num_pages) +@@ -87,10 +87,10 @@ if (unlikely(page == NULL)) continue; @@ -327,11 +327,11 @@ } #else printk(KERN_ERR "Architecture has no drm_cache.c support\n"); -diff --git a/drivers/gpu/drm/drm_context.c b/drivers/gpu/drm/drm_context.c -index 6d440fb..325365f 100644 ---- a/drivers/gpu/drm/drm_context.c -+++ b/drivers/gpu/drm/drm_context.c -@@ -154,8 +154,6 @@ int drm_getsareactx(struct drm_device *dev, void *data, +Index: linux-3.2.46/drivers/gpu/drm/drm_context.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/drm_context.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/drm_context.c 2013-07-26 19:26:21.000000000 +0000 +@@ -154,8 +154,6 @@ return -EINVAL; } @@ -340,7 +340,7 @@ request->handle = NULL; list_for_each_entry(_entry, &dev->maplist, head) { if (_entry->map == map) { -@@ -164,6 +162,9 @@ int drm_getsareactx(struct drm_device *dev, void *data, +@@ -164,6 +162,9 @@ break; } } @@ -350,10 +350,10 @@ if (request->handle == NULL) return -EINVAL; -diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c -index 3f1799b..c61e672 100644 ---- a/drivers/gpu/drm/drm_crtc.c -+++ b/drivers/gpu/drm/drm_crtc.c +Index: linux-3.2.46/drivers/gpu/drm/drm_crtc.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/drm_crtc.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/drm_crtc.c 2013-07-26 19:26:21.000000000 +0000 @@ -36,11 +36,7 @@ #include "drmP.h" #include "drm_crtc.h" @@ -367,7 +367,7 @@ /* Avoid boilerplate. I'm tired of typing. */ #define DRM_ENUM_NAME_FN(fnname, list) \ -@@ -297,9 +293,8 @@ int drm_framebuffer_init(struct drm_device *dev, struct drm_framebuffer *fb, +@@ -297,9 +293,8 @@ int ret; ret = drm_mode_object_get(dev, &fb->base, DRM_MODE_OBJECT_FB); @@ -378,7 +378,7 @@ fb->dev = dev; fb->funcs = funcs; -@@ -324,6 +319,7 @@ void drm_framebuffer_cleanup(struct drm_framebuffer *fb) +@@ -324,6 +319,7 @@ { struct drm_device *dev = fb->dev; struct drm_crtc *crtc; @@ -386,7 +386,7 @@ struct drm_mode_set set; int ret; -@@ -340,6 +336,18 @@ void drm_framebuffer_cleanup(struct drm_framebuffer *fb) +@@ -340,6 +336,18 @@ } } @@ -405,7 +405,7 @@ drm_mode_object_put(dev, &fb->base); list_del(&fb->head); dev->mode_config.num_fb--; -@@ -356,19 +364,31 @@ EXPORT_SYMBOL(drm_framebuffer_cleanup); +@@ -356,19 +364,31 @@ * Caller must hold mode config lock. * * Inits a new object created as base part of an driver crtc object. @@ -439,7 +439,7 @@ } EXPORT_SYMBOL(drm_crtc_init); -@@ -428,7 +448,7 @@ void drm_mode_remove(struct drm_connector *connector, +@@ -428,7 +448,7 @@ struct drm_display_mode *mode) { list_del(&mode->head); @@ -448,7 +448,7 @@ } EXPORT_SYMBOL(drm_mode_remove); -@@ -440,21 +460,29 @@ EXPORT_SYMBOL(drm_mode_remove); +@@ -440,21 +460,29 @@ * @name: user visible name of the connector * * LOCKING: @@ -484,7 +484,7 @@ connector->connector_type = connector_type; connector->connector_type_id = ++drm_connector_enum_list[connector_type].count; /* TODO */ -@@ -474,7 +502,10 @@ void drm_connector_init(struct drm_device *dev, +@@ -474,7 +502,10 @@ drm_connector_attach_property(connector, dev->mode_config.dpms_property, 0); @@ -495,7 +495,7 @@ } EXPORT_SYMBOL(drm_connector_init); -@@ -483,7 +514,7 @@ EXPORT_SYMBOL(drm_connector_init); +@@ -483,7 +514,7 @@ * @connector: connector to cleanup * * LOCKING: @@ -504,7 +504,7 @@ * * Cleans up the connector but doesn't free the object. */ -@@ -509,23 +540,41 @@ void drm_connector_cleanup(struct drm_connector *connector) +@@ -509,23 +540,41 @@ } EXPORT_SYMBOL(drm_connector_cleanup); @@ -549,7 +549,7 @@ } EXPORT_SYMBOL(drm_encoder_init); -@@ -540,6 +589,69 @@ void drm_encoder_cleanup(struct drm_encoder *encoder) +@@ -540,6 +589,69 @@ } EXPORT_SYMBOL(drm_encoder_cleanup); @@ -619,7 +619,7 @@ /** * drm_mode_create - create a new display mode * @dev: DRM device -@@ -560,7 +672,11 @@ struct drm_display_mode *drm_mode_create(struct drm_device *dev) +@@ -560,7 +672,11 @@ if (!nmode) return NULL; @@ -632,7 +632,7 @@ return nmode; } EXPORT_SYMBOL(drm_mode_create); -@@ -577,6 +693,9 @@ EXPORT_SYMBOL(drm_mode_create); +@@ -577,6 +693,9 @@ */ void drm_mode_destroy(struct drm_device *dev, struct drm_display_mode *mode) { @@ -642,7 +642,7 @@ drm_mode_object_put(dev, &mode->base); kfree(mode); -@@ -587,7 +706,6 @@ static int drm_mode_create_standard_connector_properties(struct drm_device *dev) +@@ -587,7 +706,6 @@ { struct drm_property *edid; struct drm_property *dpms; @@ -650,7 +650,7 @@ /* * Standard properties (apply to all connectors) -@@ -597,11 +715,9 @@ static int drm_mode_create_standard_connector_properties(struct drm_device *dev) +@@ -597,11 +715,9 @@ "EDID", 0); dev->mode_config.edid_property = edid; @@ -665,7 +665,7 @@ dev->mode_config.dpms_property = dpms; return 0; -@@ -617,30 +733,21 @@ int drm_mode_create_dvi_i_properties(struct drm_device *dev) +@@ -617,30 +733,21 @@ { struct drm_property *dvi_i_selector; struct drm_property *dvi_i_subconnector; @@ -700,7 +700,7 @@ dev->mode_config.dvi_i_subconnector_property = dvi_i_subconnector; return 0; -@@ -671,51 +778,33 @@ int drm_mode_create_tv_properties(struct drm_device *dev, int num_modes, +@@ -671,51 +778,33 @@ /* * Basic connector properties */ @@ -761,7 +761,7 @@ dev->mode_config.tv_mode_property = drm_property_create(dev, DRM_MODE_PROP_ENUM, -@@ -725,40 +814,22 @@ int drm_mode_create_tv_properties(struct drm_device *dev, int num_modes, +@@ -725,40 +814,22 @@ i, modes[i]); dev->mode_config.tv_brightness_property = @@ -808,7 +808,7 @@ return 0; } -@@ -774,18 +845,14 @@ EXPORT_SYMBOL(drm_mode_create_tv_properties); +@@ -774,18 +845,14 @@ int drm_mode_create_scaling_mode_property(struct drm_device *dev) { struct drm_property *scaling_mode; @@ -829,7 +829,7 @@ dev->mode_config.scaling_mode_property = scaling_mode; -@@ -803,18 +870,14 @@ EXPORT_SYMBOL(drm_mode_create_scaling_mode_property); +@@ -803,18 +870,14 @@ int drm_mode_create_dithering_property(struct drm_device *dev) { struct drm_property *dithering_mode; @@ -850,7 +850,7 @@ dev->mode_config.dithering_mode_property = dithering_mode; return 0; -@@ -831,20 +894,15 @@ EXPORT_SYMBOL(drm_mode_create_dithering_property); +@@ -831,20 +894,15 @@ int drm_mode_create_dirty_info_property(struct drm_device *dev) { struct drm_property *dirty_info; @@ -873,7 +873,7 @@ dev->mode_config.dirty_info_property = dirty_info; return 0; -@@ -871,6 +929,7 @@ void drm_mode_config_init(struct drm_device *dev) +@@ -871,6 +929,7 @@ INIT_LIST_HEAD(&dev->mode_config.encoder_list); INIT_LIST_HEAD(&dev->mode_config.property_list); INIT_LIST_HEAD(&dev->mode_config.property_blob_list); @@ -881,7 +881,7 @@ idr_init(&dev->mode_config.crtc_idr); mutex_lock(&dev->mode_config.mutex); -@@ -927,6 +986,7 @@ int drm_mode_group_init_legacy_group(struct drm_device *dev, +@@ -927,6 +986,7 @@ return 0; } @@ -889,7 +889,7 @@ /** * drm_mode_config_cleanup - free up DRM mode_config info -@@ -947,6 +1007,7 @@ void drm_mode_config_cleanup(struct drm_device *dev) +@@ -947,6 +1007,7 @@ struct drm_encoder *encoder, *enct; struct drm_framebuffer *fb, *fbt; struct drm_property *property, *pt; @@ -897,7 +897,7 @@ list_for_each_entry_safe(encoder, enct, &dev->mode_config.encoder_list, head) { -@@ -967,10 +1028,17 @@ void drm_mode_config_cleanup(struct drm_device *dev) +@@ -967,10 +1028,17 @@ fb->funcs->destroy(fb); } @@ -915,7 +915,7 @@ } EXPORT_SYMBOL(drm_mode_config_cleanup); -@@ -985,9 +1053,16 @@ EXPORT_SYMBOL(drm_mode_config_cleanup); +@@ -985,9 +1053,16 @@ * Convert a drm_display_mode into a drm_mode_modeinfo structure to return to * the user. */ @@ -934,7 +934,7 @@ out->clock = in->clock; out->hdisplay = in->hdisplay; out->hsync_start = in->hsync_start; -@@ -1016,10 +1091,16 @@ void drm_crtc_convert_to_umode(struct drm_mode_modeinfo *out, +@@ -1016,10 +1091,16 @@ * * Convert a drm_mode_modeinfo into a drm_display_mode structure to return to * the caller. @@ -953,7 +953,7 @@ out->clock = in->clock; out->hdisplay = in->hdisplay; out->hsync_start = in->hsync_start; -@@ -1036,6 +1117,8 @@ void drm_crtc_convert_umode(struct drm_display_mode *out, +@@ -1036,6 +1117,8 @@ out->type = in->type; strncpy(out->name, in->name, DRM_DISPLAY_MODE_LEN); out->name[DRM_DISPLAY_MODE_LEN-1] = 0; @@ -962,7 +962,7 @@ } /** -@@ -1234,7 +1317,7 @@ out: +@@ -1234,7 +1317,7 @@ * @arg: arg from ioctl * * LOCKING: @@ -971,7 +971,7 @@ * * Construct a CRTC configuration structure to return to the user. * -@@ -1294,7 +1377,7 @@ out: +@@ -1294,7 +1377,7 @@ * @arg: arg from ioctl * * LOCKING: @@ -980,7 +980,7 @@ * * Construct a connector configuration structure to return to the user. * -@@ -1379,7 +1462,7 @@ int drm_mode_getconnector(struct drm_device *dev, void *data, +@@ -1379,7 +1462,7 @@ */ if ((out_resp->count_modes >= mode_count) && mode_count) { copied = 0; @@ -989,7 +989,7 @@ list_for_each_entry(mode, &connector->modes, head) { drm_crtc_convert_to_umode(&u_mode, mode); if (copy_to_user(mode_ptr + copied, -@@ -1394,8 +1477,8 @@ int drm_mode_getconnector(struct drm_device *dev, void *data, +@@ -1394,8 +1477,8 @@ if ((out_resp->count_props >= props_count) && props_count) { copied = 0; @@ -1000,7 +1000,7 @@ for (i = 0; i < DRM_CONNECTOR_MAX_PROPERTY; i++) { if (connector->property_ids[i] != 0) { if (put_user(connector->property_ids[i], -@@ -1417,7 +1500,7 @@ int drm_mode_getconnector(struct drm_device *dev, void *data, +@@ -1417,7 +1500,7 @@ if ((out_resp->count_encoders >= encoders_count) && encoders_count) { copied = 0; @@ -1009,7 +1009,7 @@ for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) { if (connector->encoder_ids[i] != 0) { if (put_user(connector->encoder_ids[i], -@@ -1471,6 +1554,254 @@ out: +@@ -1471,6 +1554,254 @@ } /** @@ -1264,7 +1264,7 @@ * drm_mode_setcrtc - set CRTC configuration * @inode: inode from the ioctl * @filp: file * from the ioctl -@@ -1478,7 +1809,7 @@ out: +@@ -1478,7 +1809,7 @@ * @arg: arg from ioctl * * LOCKING: @@ -1273,7 +1273,7 @@ * * Build a new CRTC configuration based on user request. * -@@ -1493,7 +1824,7 @@ int drm_mode_setcrtc(struct drm_device *dev, void *data, +@@ -1493,7 +1824,7 @@ struct drm_mode_config *config = &dev->mode_config; struct drm_mode_crtc *crtc_req = data; struct drm_mode_object *obj; @@ -1282,7 +1282,7 @@ struct drm_connector **connector_set = NULL, *connector; struct drm_framebuffer *fb = NULL; struct drm_display_mode *mode = NULL; -@@ -1505,6 +1836,10 @@ int drm_mode_setcrtc(struct drm_device *dev, void *data, +@@ -1505,6 +1836,10 @@ if (!drm_core_check_feature(dev, DRIVER_MODESET)) return -EINVAL; @@ -1293,7 +1293,7 @@ mutex_lock(&dev->mode_config.mutex); obj = drm_mode_object_find(dev, crtc_req->crtc_id, DRM_MODE_OBJECT_CRTC); -@@ -1520,14 +1855,12 @@ int drm_mode_setcrtc(struct drm_device *dev, void *data, +@@ -1520,14 +1855,12 @@ /* If we have a mode we need a framebuffer. */ /* If we pass -1, set the mode with the currently bound fb */ if (crtc_req->fb_id == -1) { @@ -1313,7 +1313,7 @@ } else { obj = drm_mode_object_find(dev, crtc_req->fb_id, DRM_MODE_OBJECT_FB); -@@ -1541,8 +1874,30 @@ int drm_mode_setcrtc(struct drm_device *dev, void *data, +@@ -1541,8 +1874,30 @@ } mode = drm_mode_create(dev); @@ -1345,7 +1345,7 @@ } if (crtc_req->count_connectors == 0 && mode) { -@@ -1576,7 +1931,7 @@ int drm_mode_setcrtc(struct drm_device *dev, void *data, +@@ -1576,7 +1931,7 @@ } for (i = 0; i < crtc_req->count_connectors; i++) { @@ -1354,7 +1354,7 @@ if (get_user(out_id, &set_connectors_ptr[i])) { ret = -EFAULT; goto out; -@@ -1610,6 +1965,7 @@ int drm_mode_setcrtc(struct drm_device *dev, void *data, +@@ -1610,6 +1965,7 @@ out: kfree(connector_set); @@ -1362,7 +1362,7 @@ mutex_unlock(&dev->mode_config.mutex); return ret; } -@@ -1660,6 +2016,42 @@ out: +@@ -1660,6 +2016,42 @@ return ret; } @@ -1405,7 +1405,7 @@ /** * drm_mode_addfb - add an FB to the graphics configuration * @inode: inode from the ioctl -@@ -1680,18 +2072,27 @@ out: +@@ -1680,18 +2072,27 @@ int drm_mode_addfb(struct drm_device *dev, void *data, struct drm_file *file_priv) { @@ -1436,7 +1436,7 @@ return -EINVAL; mutex_lock(&dev->mode_config.mutex); -@@ -1699,6 +2100,138 @@ int drm_mode_addfb(struct drm_device *dev, +@@ -1699,6 +2100,138 @@ /* TODO check buffer is sufficiently large */ /* TODO setup destructor callback */ @@ -1575,7 +1575,7 @@ fb = dev->mode_config.funcs->fb_create(dev, file_priv, r); if (IS_ERR(fb)) { DRM_ERROR("could not create framebuffer\n"); -@@ -1782,7 +2315,7 @@ out: +@@ -1782,7 +2315,7 @@ * @arg: arg from ioctl * * LOCKING: @@ -1584,7 +1584,7 @@ * * Lookup the FB given its ID and return info about it. * -@@ -1814,7 +2347,7 @@ int drm_mode_getfb(struct drm_device *dev, +@@ -1814,7 +2347,7 @@ r->width = fb->width; r->depth = fb->depth; r->bpp = fb->bits_per_pixel; @@ -1593,7 +1593,7 @@ fb->funcs->create_handle(fb, file_priv, &r->handle); out: -@@ -1846,7 +2379,7 @@ int drm_mode_dirtyfb_ioctl(struct drm_device *dev, +@@ -1846,7 +2379,7 @@ fb = obj_to_fb(obj); num_clips = r->num_clips; @@ -1602,7 +1602,7 @@ if (!num_clips != !clips_ptr) { ret = -EINVAL; -@@ -1931,38 +2464,48 @@ void drm_fb_release(struct drm_file *priv) +@@ -1931,38 +2464,48 @@ * * Add @mode to @connector's user mode list. */ @@ -1670,7 +1670,7 @@ } EXPORT_SYMBOL(drm_mode_attachmode_crtc); -@@ -2041,9 +2584,14 @@ int drm_mode_attachmode_ioctl(struct drm_device *dev, +@@ -2041,9 +2584,14 @@ goto out; } @@ -1687,7 +1687,7 @@ out: mutex_unlock(&dev->mode_config.mutex); return ret; -@@ -2084,7 +2632,12 @@ int drm_mode_detachmode_ioctl(struct drm_device *dev, +@@ -2084,7 +2632,12 @@ } connector = obj_to_connector(obj); @@ -1701,7 +1701,7 @@ ret = drm_mode_detachmode(dev, connector, &mode); out: mutex_unlock(&dev->mode_config.mutex); -@@ -2095,6 +2648,7 @@ struct drm_property *drm_property_create(struct drm_device *dev, int flags, +@@ -2095,6 +2648,7 @@ const char *name, int num_values) { struct drm_property *property = NULL; @@ -1709,7 +1709,7 @@ property = kzalloc(sizeof(struct drm_property), GFP_KERNEL); if (!property) -@@ -2106,7 +2660,10 @@ struct drm_property *drm_property_create(struct drm_device *dev, int flags, +@@ -2106,7 +2660,10 @@ goto fail; } @@ -1721,7 +1721,7 @@ property->flags = flags; property->num_values = num_values; INIT_LIST_HEAD(&property->enum_blob_list); -@@ -2119,11 +2676,59 @@ struct drm_property *drm_property_create(struct drm_device *dev, int flags, +@@ -2119,11 +2676,59 @@ list_add_tail(&property->head, &dev->mode_config.property_list); return property; fail: @@ -1781,7 +1781,7 @@ int drm_property_add_enum(struct drm_property *property, int index, uint64_t value, const char *name) { -@@ -2242,7 +2847,7 @@ int drm_mode_getproperty_ioctl(struct drm_device *dev, +@@ -2242,7 +2847,7 @@ struct drm_property_enum *prop_enum; struct drm_mode_property_enum __user *enum_ptr; struct drm_property_blob *prop_blob; @@ -1790,7 +1790,7 @@ uint64_t __user *values_ptr; uint32_t __user *blob_length_ptr; -@@ -2272,7 +2877,7 @@ int drm_mode_getproperty_ioctl(struct drm_device *dev, +@@ -2272,7 +2877,7 @@ out_resp->flags = property->flags; if ((out_resp->count_values >= value_count) && value_count) { @@ -1799,7 +1799,7 @@ for (i = 0; i < value_count; i++) { if (copy_to_user(values_ptr + i, &property->values[i], sizeof(uint64_t))) { ret = -EFAULT; -@@ -2285,7 +2890,7 @@ int drm_mode_getproperty_ioctl(struct drm_device *dev, +@@ -2285,7 +2890,7 @@ if (property->flags & DRM_MODE_PROP_ENUM) { if ((out_resp->count_enum_blobs >= enum_count) && enum_count) { copied = 0; @@ -1808,7 +1808,7 @@ list_for_each_entry(prop_enum, &property->enum_blob_list, head) { if (copy_to_user(&enum_ptr[copied].value, &prop_enum->value, sizeof(uint64_t))) { -@@ -2307,8 +2912,8 @@ int drm_mode_getproperty_ioctl(struct drm_device *dev, +@@ -2307,8 +2912,8 @@ if (property->flags & DRM_MODE_PROP_BLOB) { if ((out_resp->count_enum_blobs >= blob_count) && blob_count) { copied = 0; @@ -1819,7 +1819,7 @@ list_for_each_entry(prop_blob, &property->enum_blob_list, head) { if (put_user(prop_blob->base.id, blob_id_ptr + copied)) { -@@ -2335,6 +2940,7 @@ static struct drm_property_blob *drm_property_create_blob(struct drm_device *dev +@@ -2335,6 +2940,7 @@ void *data) { struct drm_property_blob *blob; @@ -1827,7 +1827,7 @@ if (!length || !data) return NULL; -@@ -2343,13 +2949,16 @@ static struct drm_property_blob *drm_property_create_blob(struct drm_device *dev +@@ -2343,13 +2949,16 @@ if (!blob) return NULL; @@ -1847,7 +1847,7 @@ list_add_tail(&blob->head, &dev->mode_config.property_blob_list); return blob; } -@@ -2369,7 +2978,7 @@ int drm_mode_getblob_ioctl(struct drm_device *dev, +@@ -2369,7 +2978,7 @@ struct drm_mode_get_blob *out_resp = data; struct drm_property_blob *blob; int ret = 0; @@ -1856,7 +1856,7 @@ if (!drm_core_check_feature(dev, DRIVER_MODESET)) return -EINVAL; -@@ -2383,7 +2992,7 @@ int drm_mode_getblob_ioctl(struct drm_device *dev, +@@ -2383,7 +2992,7 @@ blob = obj_to_blob(obj); if (out_resp->length == blob->length) { @@ -1865,7 +1865,7 @@ if (copy_to_user(blob_ptr, blob->data, blob->length)){ ret = -EFAULT; goto done; -@@ -2528,7 +3137,7 @@ void drm_mode_connector_detach_encoder(struct drm_connector *connector, +@@ -2528,7 +3137,7 @@ } EXPORT_SYMBOL(drm_mode_connector_detach_encoder); @@ -1874,7 +1874,7 @@ int gamma_size) { crtc->gamma_size = gamma_size; -@@ -2536,10 +3145,10 @@ bool drm_mode_crtc_set_gamma_size(struct drm_crtc *crtc, +@@ -2536,10 +3145,10 @@ crtc->gamma_store = kzalloc(gamma_size * sizeof(uint16_t) * 3, GFP_KERNEL); if (!crtc->gamma_store) { crtc->gamma_size = 0; @@ -1887,7 +1887,7 @@ } EXPORT_SYMBOL(drm_mode_crtc_set_gamma_size); -@@ -2685,6 +3294,18 @@ int drm_mode_page_flip_ioctl(struct drm_device *dev, +@@ -2685,6 +3294,18 @@ goto out; fb = obj_to_fb(obj); @@ -1906,7 +1906,7 @@ if (page_flip->flags & DRM_MODE_PAGE_FLIP_EVENT) { ret = -ENOMEM; spin_lock_irqsave(&dev->event_lock, flags); -@@ -2714,10 +3335,12 @@ int drm_mode_page_flip_ioctl(struct drm_device *dev, +@@ -2714,10 +3335,12 @@ ret = crtc->funcs->page_flip(crtc, fb, e); if (ret) { @@ -1923,7 +1923,7 @@ } out: -@@ -2777,3 +3400,72 @@ int drm_mode_destroy_dumb_ioctl(struct drm_device *dev, +@@ -2777,3 +3400,72 @@ return dev->driver->dumb_destroy(file_priv, dev, args->handle); } @@ -1996,10 +1996,10 @@ + } +} +EXPORT_SYMBOL(drm_fb_get_bpp_depth); -diff --git a/drivers/gpu/drm/drm_crtc_helper.c b/drivers/gpu/drm/drm_crtc_helper.c -index 11788f7..8111889 100644 ---- a/drivers/gpu/drm/drm_crtc_helper.c -+++ b/drivers/gpu/drm/drm_crtc_helper.c +Index: linux-3.2.46/drivers/gpu/drm/drm_crtc_helper.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/drm_crtc_helper.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/drm_crtc_helper.c 2013-07-26 19:26:21.000000000 +0000 @@ -34,8 +34,10 @@ #include "drmP.h" @@ -2011,7 +2011,7 @@ static bool drm_kms_helper_poll = true; module_param_named(poll, drm_kms_helper_poll, bool, 0600); -@@ -43,12 +45,12 @@ module_param_named(poll, drm_kms_helper_poll, bool, 0600); +@@ -43,12 +45,12 @@ static void drm_mode_validate_flag(struct drm_connector *connector, int flags) { @@ -2026,7 +2026,7 @@ if ((mode->flags & DRM_MODE_FLAG_INTERLACE) && !(flags & DRM_MODE_FLAG_INTERLACE)) mode->status = MODE_NO_INTERLACE; -@@ -86,7 +88,7 @@ int drm_helper_probe_single_connector_modes(struct drm_connector *connector, +@@ -86,7 +88,7 @@ uint32_t maxX, uint32_t maxY) { struct drm_device *dev = connector->dev; @@ -2035,7 +2035,7 @@ struct drm_connector_helper_funcs *connector_funcs = connector->helper_private; int count = 0; -@@ -95,7 +97,7 @@ int drm_helper_probe_single_connector_modes(struct drm_connector *connector, +@@ -95,7 +97,7 @@ DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", connector->base.id, drm_get_connector_name(connector)); /* set all modes to the unverified state */ @@ -2044,7 +2044,7 @@ mode->status = MODE_UNVERIFIED; if (connector->force) { -@@ -117,7 +119,12 @@ int drm_helper_probe_single_connector_modes(struct drm_connector *connector, +@@ -117,7 +119,12 @@ goto prune; } @@ -2058,7 +2058,7 @@ if (count == 0 && connector->status == connector_status_connected) count = drm_add_modes_noedid(connector, 1024, 768); if (count == 0) -@@ -135,7 +142,7 @@ int drm_helper_probe_single_connector_modes(struct drm_connector *connector, +@@ -135,7 +142,7 @@ mode_flags |= DRM_MODE_FLAG_DBLSCAN; drm_mode_validate_flag(connector, mode_flags); @@ -2067,7 +2067,7 @@ if (mode->status == MODE_OK) mode->status = connector_funcs->mode_valid(connector, mode); -@@ -151,7 +158,7 @@ prune: +@@ -151,7 +158,7 @@ DRM_DEBUG_KMS("[CONNECTOR:%d:%s] probed modes :\n", connector->base.id, drm_get_connector_name(connector)); @@ -2076,7 +2076,7 @@ mode->vrefresh = drm_mode_vrefresh(mode); drm_mode_set_crtcinfo(mode, CRTC_INTERLACE_HALVE_V); -@@ -321,8 +328,8 @@ drm_crtc_prepare_encoders(struct drm_device *dev) +@@ -321,8 +328,8 @@ * drm_crtc_set_mode - set a mode * @crtc: CRTC to program * @mode: mode to use @@ -2087,7 +2087,7 @@ * * LOCKING: * Caller must hold mode config lock. -@@ -351,6 +358,8 @@ bool drm_crtc_helper_set_mode(struct drm_crtc *crtc, +@@ -351,6 +358,8 @@ return true; adjusted_mode = drm_mode_duplicate(dev, mode); @@ -2096,7 +2096,7 @@ saved_hwmode = crtc->hwmode; saved_mode = crtc->mode; -@@ -710,7 +719,7 @@ int drm_crtc_helper_set_config(struct drm_mode_set *set) +@@ -710,7 +719,7 @@ for (i = 0; i < set->num_connectors; i++) { DRM_DEBUG_KMS("\t[CONNECTOR:%d:%s] set DPMS on\n", set->connectors[i]->base.id, drm_get_connector_name(set->connectors[i])); @@ -2105,7 +2105,7 @@ } } drm_helper_disable_unused_functions(dev); -@@ -847,13 +856,19 @@ void drm_helper_connector_dpms(struct drm_connector *connector, int mode) +@@ -847,13 +856,19 @@ EXPORT_SYMBOL(drm_helper_connector_dpms); int drm_helper_mode_fill_fb_struct(struct drm_framebuffer *fb, @@ -2129,7 +2129,7 @@ return 0; } -@@ -1008,3 +1023,36 @@ void drm_helper_hpd_irq_event(struct drm_device *dev) +@@ -1008,3 +1023,36 @@ queue_delayed_work(system_nrt_wq, &dev->mode_config.output_poll_work, 0); } EXPORT_SYMBOL(drm_helper_hpd_irq_event); @@ -2166,11 +2166,11 @@ + } +} +EXPORT_SYMBOL(drm_format_num_planes); -diff --git a/drivers/gpu/drm/drm_drv.c b/drivers/gpu/drm/drm_drv.c -index 40c187c..6116e3b 100644 ---- a/drivers/gpu/drm/drm_drv.c -+++ b/drivers/gpu/drm/drm_drv.c -@@ -61,14 +61,14 @@ static int drm_version(struct drm_device *dev, void *data, +Index: linux-3.2.46/drivers/gpu/drm/drm_drv.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/drm_drv.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/drm_drv.c 2013-07-26 19:26:21.000000000 +0000 +@@ -61,14 +61,14 @@ /** Ioctl table */ static struct drm_ioctl_desc drm_ioctls[] = { @@ -2190,7 +2190,7 @@ DRM_IOCTL_DEF(DRM_IOCTL_SET_VERSION, drm_setversion, DRM_MASTER), DRM_IOCTL_DEF(DRM_IOCTL_SET_UNIQUE, drm_setunique, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), -@@ -135,21 +135,29 @@ static struct drm_ioctl_desc drm_ioctls[] = { +@@ -135,21 +135,29 @@ DRM_IOCTL_DEF(DRM_IOCTL_GEM_FLINK, drm_gem_flink_ioctl, DRM_AUTH|DRM_UNLOCKED), DRM_IOCTL_DEF(DRM_IOCTL_GEM_OPEN, drm_gem_open_ioctl, DRM_AUTH|DRM_UNLOCKED), @@ -2226,7 +2226,7 @@ DRM_IOCTL_DEF(DRM_IOCTL_MODE_RMFB, drm_mode_rmfb, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED), DRM_IOCTL_DEF(DRM_IOCTL_MODE_PAGE_FLIP, drm_mode_page_flip_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED), DRM_IOCTL_DEF(DRM_IOCTL_MODE_DIRTYFB, drm_mode_dirtyfb_ioctl, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED), -@@ -386,6 +394,10 @@ long drm_ioctl(struct file *filp, +@@ -386,6 +394,10 @@ unsigned int usize, asize; dev = file_priv->minor->dev; @@ -2237,11 +2237,11 @@ atomic_inc(&dev->ioctl_count); atomic_inc(&dev->counts[_DRM_STAT_IOCTLS]); ++file_priv->ioctl_count; -diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c -index 7211f67..8b77fd3 100644 ---- a/drivers/gpu/drm/drm_edid.c -+++ b/drivers/gpu/drm/drm_edid.c -@@ -154,8 +154,7 @@ EXPORT_SYMBOL(drm_edid_header_is_valid); +Index: linux-3.2.46/drivers/gpu/drm/drm_edid.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/drm_edid.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/drm_edid.c 2013-07-26 19:26:21.000000000 +0000 +@@ -154,8 +154,7 @@ * Sanity check the EDID block (base or extension). Return 0 if the block * doesn't check out, or 1 if it's valid. */ @@ -2251,7 +2251,7 @@ { int i; u8 csum = 0; -@@ -208,6 +207,7 @@ bad: +@@ -208,6 +207,7 @@ } return 0; } @@ -2259,7 +2259,7 @@ /** * drm_edid_is_valid - sanity check EDID data -@@ -231,7 +231,6 @@ bool drm_edid_is_valid(struct edid *edid) +@@ -231,7 +231,6 @@ } EXPORT_SYMBOL(drm_edid_is_valid); @@ -2267,7 +2267,7 @@ #define DDC_SEGMENT_ADDR 0x30 /** * Get EDID information via I2C. -@@ -518,25 +517,10 @@ static void +@@ -518,25 +517,10 @@ cea_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure) { int i, n = 0; @@ -2295,7 +2295,7 @@ for (i = 0; i < n; i++) cb((struct detailed_timing *)(det_base + 18 * i), closure); } -@@ -770,7 +754,7 @@ drm_mode_std(struct drm_connector *connector, struct edid *edid, +@@ -770,7 +754,7 @@ */ mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); if (drm_mode_hsync(mode) > drm_gtf2_hbreak(edid)) { @@ -2304,7 +2304,7 @@ mode = drm_gtf_mode_complex(dev, hsize, vsize, vrefresh_rate, 0, 0, drm_gtf2_m(edid), -@@ -1339,6 +1323,7 @@ add_detailed_modes(struct drm_connector *connector, struct edid *edid, +@@ -1339,6 +1323,7 @@ #define HDMI_IDENTIFIER 0x000C03 #define AUDIO_BLOCK 0x01 @@ -2312,7 +2312,7 @@ #define VENDOR_BLOCK 0x03 #define SPEAKER_BLOCK 0x04 #define EDID_BASIC_AUDIO (1 << 6) -@@ -1369,6 +1354,47 @@ u8 *drm_find_cea_extension(struct edid *edid) +@@ -1369,6 +1354,47 @@ } EXPORT_SYMBOL(drm_find_cea_extension); @@ -2360,7 +2360,7 @@ static void parse_hdmi_vsdb(struct drm_connector *connector, uint8_t *db) { -@@ -1452,26 +1478,29 @@ void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid) +@@ -1452,26 +1478,29 @@ eld[18] = edid->prod_code[0]; eld[19] = edid->prod_code[1]; @@ -2409,7 +2409,7 @@ eld[5] |= sad_count << 4; eld[2] = (20 + mnl + sad_count * 3 + 3) / 4; -@@ -1743,6 +1772,7 @@ int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid) +@@ -1743,6 +1772,7 @@ num_modes += add_established_modes(connector, edid); if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF) num_modes += add_inferred_modes(connector, edid); @@ -2417,11 +2417,10 @@ if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75)) edid_fixup_preferred(connector, quirks); -diff --git a/drivers/gpu/drm/drm_edid_load.c b/drivers/gpu/drm/drm_edid_load.c -new file mode 100644 -index 0000000..da9acba ---- /dev/null -+++ b/drivers/gpu/drm/drm_edid_load.c +Index: linux-3.2.46/drivers/gpu/drm/drm_edid_load.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/drm_edid_load.c 2013-07-26 19:26:21.000000000 +0000 @@ -0,0 +1,250 @@ +/* + drm_edid_load.c: use a built-in EDID data set or load it via the firmware @@ -2673,11 +2672,11 @@ + return drm_add_edid_modes(connector, (struct edid *) + connector->display_info.raw_edid); +} -diff --git a/drivers/gpu/drm/drm_edid_modes.h b/drivers/gpu/drm/drm_edid_modes.h -index 5f20644..a91ffb1 100644 ---- a/drivers/gpu/drm/drm_edid_modes.h -+++ b/drivers/gpu/drm/drm_edid_modes.h -@@ -378,3 +378,287 @@ static const struct { +Index: linux-3.2.46/drivers/gpu/drm/drm_edid_modes.h +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/drm_edid_modes.h 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/drm_edid_modes.h 2013-07-26 19:26:21.000000000 +0000 +@@ -378,3 +378,287 @@ { 1920, 1440, 75, 0 }, }; static const int num_est3_modes = sizeof(est3_modes) / sizeof(est3_modes[0]); @@ -2965,11 +2964,11 @@ +}; +static const int drm_num_cea_modes = + sizeof (edid_cea_modes) / sizeof (edid_cea_modes[0]); -diff --git a/drivers/gpu/drm/drm_fb_helper.c b/drivers/gpu/drm/drm_fb_helper.c -index dd58373..a0d6e89 100644 ---- a/drivers/gpu/drm/drm_fb_helper.c -+++ b/drivers/gpu/drm/drm_fb_helper.c -@@ -255,6 +255,13 @@ bool drm_fb_helper_force_kernel_mode(void) +Index: linux-3.2.46/drivers/gpu/drm/drm_fb_helper.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/drm_fb_helper.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/drm_fb_helper.c 2013-07-26 19:26:21.000000000 +0000 +@@ -255,6 +255,13 @@ int drm_fb_helper_panic(struct notifier_block *n, unsigned long ununsed, void *panic_str) { @@ -2983,7 +2982,7 @@ printk(KERN_ERR "panic occurred, switching back to text console\n"); return drm_fb_helper_force_kernel_mode(); } -@@ -299,91 +306,31 @@ static struct sysrq_key_op sysrq_drm_fb_helper_restore_op = { +@@ -299,91 +306,31 @@ static struct sysrq_key_op sysrq_drm_fb_helper_restore_op = { }; #endif @@ -3065,8 +3064,7 @@ drm_connector_property_set_value(connector, - dev->mode_config.dpms_property, - dpms_mode); -+ dev->mode_config.dpms_property, dpms_mode); - } +- } - /* Found a CRTC on this fb, now find encoders */ - list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { - if (encoder->crtc == crtc) { @@ -3075,12 +3073,13 @@ - encoder_funcs = encoder->helper_private; - encoder_funcs->dpms(encoder, dpms_mode); - } -- } ++ dev->mode_config.dpms_property, dpms_mode); + } - crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF); } mutex_unlock(&dev->mode_config.mutex); } -@@ -393,23 +340,23 @@ int drm_fb_helper_blank(int blank, struct fb_info *info) +@@ -393,23 +340,23 @@ switch (blank) { /* Display: On; HSync: On, VSync: On */ case FB_BLANK_UNBLANK: @@ -3109,7 +3108,7 @@ break; } return 0; -@@ -423,8 +370,11 @@ static void drm_fb_helper_crtc_free(struct drm_fb_helper *helper) +@@ -423,8 +370,11 @@ for (i = 0; i < helper->connector_count; i++) kfree(helper->connector_info[i]); kfree(helper->connector_info); @@ -3122,7 +3121,7 @@ kfree(helper->crtc_info); } -@@ -467,11 +417,10 @@ int drm_fb_helper_init(struct drm_device *dev, +@@ -467,11 +417,10 @@ i = 0; list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { @@ -3135,11 +3134,11 @@ return 0; out_free: drm_fb_helper_crtc_free(fb_helper); -diff --git a/drivers/gpu/drm/drm_fops.c b/drivers/gpu/drm/drm_fops.c -index 020b103..b90abff 100644 ---- a/drivers/gpu/drm/drm_fops.c -+++ b/drivers/gpu/drm/drm_fops.c -@@ -133,6 +133,9 @@ int drm_open(struct inode *inode, struct file *filp) +Index: linux-3.2.46/drivers/gpu/drm/drm_fops.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/drm_fops.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/drm_fops.c 2013-07-26 19:26:21.000000000 +0000 +@@ -133,6 +133,9 @@ if (!(dev = minor->dev)) return -ENODEV; @@ -3149,7 +3148,7 @@ retcode = drm_open_helper(inode, filp, dev); if (!retcode) { atomic_inc(&dev->counts[_DRM_STAT_OPENS]); -@@ -184,8 +187,11 @@ int drm_stub_open(struct inode *inode, struct file *filp) +@@ -184,8 +187,11 @@ if (!(dev = minor->dev)) goto out; @@ -3162,7 +3161,7 @@ if (filp->f_op == NULL) { filp->f_op = old_fops; goto out; -@@ -268,6 +274,9 @@ static int drm_open_helper(struct inode *inode, struct file *filp, +@@ -268,6 +274,9 @@ if (dev->driver->driver_features & DRIVER_GEM) drm_gem_open(dev, priv); @@ -3172,7 +3171,7 @@ if (dev->driver->open) { ret = dev->driver->open(dev, priv); if (ret < 0) -@@ -501,12 +510,12 @@ int drm_release(struct inode *inode, struct file *filp) +@@ -501,12 +510,12 @@ drm_events_release(file_priv); @@ -3188,7 +3187,7 @@ mutex_lock(&dev->ctxlist_mutex); if (!list_empty(&dev->ctxlist)) { struct drm_ctx_list *pos, *n; -@@ -568,6 +577,10 @@ int drm_release(struct inode *inode, struct file *filp) +@@ -568,6 +577,10 @@ if (dev->driver->postclose) dev->driver->postclose(dev, file_priv); @@ -3199,7 +3198,7 @@ kfree(file_priv); /* ======================================================== -@@ -582,6 +595,8 @@ int drm_release(struct inode *inode, struct file *filp) +@@ -582,6 +595,8 @@ retcode = -EBUSY; } else retcode = drm_lastclose(dev); @@ -3208,10 +3207,10 @@ } mutex_unlock(&drm_global_mutex); -diff --git a/drivers/gpu/drm/drm_gem.c b/drivers/gpu/drm/drm_gem.c -index 396e60c..83114b5 100644 ---- a/drivers/gpu/drm/drm_gem.c -+++ b/drivers/gpu/drm/drm_gem.c +Index: linux-3.2.46/drivers/gpu/drm/drm_gem.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/drm_gem.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/drm_gem.c 2013-07-26 19:26:21.000000000 +0000 @@ -35,6 +35,7 @@ #include #include @@ -3220,7 +3219,7 @@ #include "drmP.h" /** @file drm_gem.c -@@ -140,7 +141,7 @@ int drm_gem_object_init(struct drm_device *dev, +@@ -140,7 +141,7 @@ obj->dev = dev; obj->filp = shmem_file_setup("drm mm object", size, VM_NORESERVE); if (IS_ERR(obj->filp)) @@ -3229,7 +3228,7 @@ kref_init(&obj->refcount); atomic_set(&obj->handle_count, 0); -@@ -232,6 +233,10 @@ drm_gem_handle_delete(struct drm_file *filp, u32 handle) +@@ -232,6 +233,10 @@ idr_remove(&filp->object_idr, handle); spin_unlock(&filp->table_lock); @@ -3240,7 +3239,7 @@ if (dev->driver->gem_close_object) dev->driver->gem_close_object(obj, filp); drm_gem_object_handle_unreference_unlocked(obj); -@@ -527,6 +532,10 @@ drm_gem_object_release_handle(int id, void *ptr, void *data) +@@ -527,6 +532,10 @@ struct drm_gem_object *obj = ptr; struct drm_device *dev = obj->dev; @@ -3251,7 +3250,7 @@ if (dev->driver->gem_close_object) dev->driver->gem_close_object(obj, file_priv); -@@ -661,6 +670,9 @@ int drm_gem_mmap(struct file *filp, struct vm_area_struct *vma) +@@ -661,6 +670,9 @@ struct drm_hash_item *hash; int ret = 0; @@ -3261,7 +3260,7 @@ mutex_lock(&dev->struct_mutex); if (drm_ht_find_item(&mm->offset_hash, vma->vm_pgoff, &hash)) { -@@ -700,7 +712,6 @@ int drm_gem_mmap(struct file *filp, struct vm_area_struct *vma) +@@ -700,7 +712,6 @@ */ drm_gem_object_reference(obj); @@ -3269,11 +3268,11 @@ drm_vm_open_locked(vma); out_unlock: -diff --git a/drivers/gpu/drm/drm_ioc32.c b/drivers/gpu/drm/drm_ioc32.c -index ddd70db..637fcc3 100644 ---- a/drivers/gpu/drm/drm_ioc32.c -+++ b/drivers/gpu/drm/drm_ioc32.c -@@ -315,7 +315,8 @@ static int compat_drm_getclient(struct file *file, unsigned int cmd, +Index: linux-3.2.46/drivers/gpu/drm/drm_ioc32.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/drm_ioc32.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/drm_ioc32.c 2013-07-26 19:26:21.000000000 +0000 +@@ -315,7 +315,8 @@ if (err) return err; @@ -3283,10 +3282,10 @@ || __get_user(c32.pid, &client->pid) || __get_user(c32.uid, &client->uid) || __get_user(c32.magic, &client->magic) -diff --git a/drivers/gpu/drm/drm_ioctl.c b/drivers/gpu/drm/drm_ioctl.c -index 904d7e9..cf85155 100644 ---- a/drivers/gpu/drm/drm_ioctl.c -+++ b/drivers/gpu/drm/drm_ioctl.c +Index: linux-3.2.46/drivers/gpu/drm/drm_ioctl.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/drm_ioctl.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/drm_ioctl.c 2013-07-26 19:26:21.000000000 +0000 @@ -37,6 +37,7 @@ #include "drm_core.h" @@ -3295,7 +3294,7 @@ /** * Get the bus id. -@@ -158,14 +159,11 @@ int drm_getmap(struct drm_device *dev, void *data, +@@ -158,14 +159,11 @@ int i; idx = map->offset; @@ -3312,7 +3311,7 @@ list_for_each(list, &dev->maplist) { if (i == idx) { r_list = list_entry(list, struct drm_map_list, head); -@@ -211,9 +209,9 @@ int drm_getclient(struct drm_device *dev, void *data, +@@ -211,9 +209,9 @@ int i; idx = client->idx; @@ -3324,7 +3323,7 @@ list_for_each_entry(pt, &dev->filelist, lhead) { if (i++ >= idx) { client->auth = pt->authenticated; -@@ -249,8 +247,6 @@ int drm_getstats(struct drm_device *dev, void *data, +@@ -249,8 +247,6 @@ memset(stats, 0, sizeof(*stats)); @@ -3333,7 +3332,7 @@ for (i = 0; i < dev->counters; i++) { if (dev->types[i] == _DRM_STAT_LOCK) stats->data[i].value = -@@ -262,8 +258,6 @@ int drm_getstats(struct drm_device *dev, void *data, +@@ -262,8 +258,6 @@ stats->count = dev->counters; @@ -3342,7 +3341,7 @@ return 0; } -@@ -283,6 +277,12 @@ int drm_getcap(struct drm_device *dev, void *data, struct drm_file *file_priv) +@@ -283,6 +277,12 @@ case DRM_CAP_VBLANK_HIGH_CRTC: req->value = 1; break; @@ -3355,16 +3354,16 @@ default: return -EINVAL; } -@@ -353,3 +353,4 @@ int drm_noop(struct drm_device *dev, void *data, +@@ -353,3 +353,4 @@ DRM_DEBUG("\n"); return 0; } +EXPORT_SYMBOL(drm_noop); -diff --git a/drivers/gpu/drm/drm_irq.c b/drivers/gpu/drm/drm_irq.c -index 44a5d0a..c869436 100644 ---- a/drivers/gpu/drm/drm_irq.c -+++ b/drivers/gpu/drm/drm_irq.c -@@ -305,7 +305,7 @@ static void drm_irq_vgaarb_nokms(void *cookie, bool state) +Index: linux-3.2.46/drivers/gpu/drm/drm_irq.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/drm_irq.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/drm_irq.c 2013-07-26 19:26:21.000000000 +0000 +@@ -305,7 +305,7 @@ * \param dev DRM device. * * Initializes the IRQ related data. Installs the handler, calling the driver @@ -3373,7 +3372,7 @@ * before and after the installation. */ int drm_irq_install(struct drm_device *dev) -@@ -385,7 +385,7 @@ EXPORT_SYMBOL(drm_irq_install); +@@ -385,7 +385,7 @@ * * \param dev DRM device. * @@ -3382,10 +3381,10 @@ */ int drm_irq_uninstall(struct drm_device *dev) { -diff --git a/drivers/gpu/drm/drm_lock.c b/drivers/gpu/drm/drm_lock.c -index 632ae24..c79c713 100644 ---- a/drivers/gpu/drm/drm_lock.c -+++ b/drivers/gpu/drm/drm_lock.c +Index: linux-3.2.46/drivers/gpu/drm/drm_lock.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/drm_lock.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/drm_lock.c 2013-07-26 19:26:21.000000000 +0000 @@ -33,6 +33,7 @@ * OTHER DEALINGS IN THE SOFTWARE. */ @@ -3394,7 +3393,7 @@ #include "drmP.h" static int drm_notifier(void *priv); -@@ -345,6 +346,7 @@ void drm_idlelock_take(struct drm_lock_data *lock_data) +@@ -345,6 +346,7 @@ } spin_unlock_bh(&lock_data->spinlock); } @@ -3402,7 +3401,7 @@ void drm_idlelock_release(struct drm_lock_data *lock_data) { -@@ -364,6 +366,7 @@ void drm_idlelock_release(struct drm_lock_data *lock_data) +@@ -364,6 +366,7 @@ } spin_unlock_bh(&lock_data->spinlock); } @@ -3410,10 +3409,10 @@ int drm_i_have_hw_lock(struct drm_device *dev, struct drm_file *file_priv) { -diff --git a/drivers/gpu/drm/drm_memory.c b/drivers/gpu/drm/drm_memory.c -index c8b6b66..c86a0f1 100644 ---- a/drivers/gpu/drm/drm_memory.c -+++ b/drivers/gpu/drm/drm_memory.c +Index: linux-3.2.46/drivers/gpu/drm/drm_memory.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/drm_memory.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/drm_memory.c 2013-07-26 19:26:21.000000000 +0000 @@ -37,25 +37,6 @@ #include #include "drmP.h" @@ -3440,11 +3439,11 @@ #if __OS_HAS_AGP static void *agp_remap(unsigned long offset, unsigned long size, struct drm_device * dev) -diff --git a/drivers/gpu/drm/drm_mm.c b/drivers/gpu/drm/drm_mm.c -index 961fb54..7f88de6 100644 ---- a/drivers/gpu/drm/drm_mm.c -+++ b/drivers/gpu/drm/drm_mm.c -@@ -680,33 +680,35 @@ void drm_mm_debug_table(struct drm_mm *mm, const char *prefix) +Index: linux-3.2.46/drivers/gpu/drm/drm_mm.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/drm_mm.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/drm_mm.c 2013-07-26 19:26:21.000000000 +0000 +@@ -680,33 +680,35 @@ EXPORT_SYMBOL(drm_mm_debug_table); #if defined(CONFIG_DEBUG_FS) @@ -3496,11 +3495,11 @@ } total = total_free + total_used; -diff --git a/drivers/gpu/drm/drm_modes.c b/drivers/gpu/drm/drm_modes.c -index fb8e46b..b7adb4a 100644 ---- a/drivers/gpu/drm/drm_modes.c -+++ b/drivers/gpu/drm/drm_modes.c -@@ -686,8 +686,6 @@ void drm_mode_set_crtcinfo(struct drm_display_mode *p, int adjust_flags) +Index: linux-3.2.46/drivers/gpu/drm/drm_modes.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/drm_modes.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/drm_modes.c 2013-07-26 19:26:21.000000000 +0000 +@@ -686,8 +686,6 @@ p->crtc_vsync_end /= 2; p->crtc_vtotal /= 2; } @@ -3509,7 +3508,7 @@ } if (p->flags & DRM_MODE_FLAG_DBLSCAN) { -@@ -716,6 +714,27 @@ EXPORT_SYMBOL(drm_mode_set_crtcinfo); +@@ -716,6 +714,27 @@ /** @@ -3537,7 +3536,7 @@ * drm_mode_duplicate - allocate and duplicate an existing mode * @m: mode to duplicate * -@@ -729,16 +748,13 @@ struct drm_display_mode *drm_mode_duplicate(struct drm_device *dev, +@@ -729,16 +748,13 @@ const struct drm_display_mode *mode) { struct drm_display_mode *nmode; @@ -3556,11 +3555,11 @@ return nmode; } EXPORT_SYMBOL(drm_mode_duplicate); -diff --git a/drivers/gpu/drm/drm_pci.c b/drivers/gpu/drm/drm_pci.c -index d4d10b7..13f3d93 100644 ---- a/drivers/gpu/drm/drm_pci.c -+++ b/drivers/gpu/drm/drm_pci.c -@@ -324,8 +324,6 @@ int drm_get_pci_dev(struct pci_dev *pdev, const struct pci_device_id *ent, +Index: linux-3.2.46/drivers/gpu/drm/drm_pci.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/drm_pci.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/drm_pci.c 2013-07-26 19:26:21.000000000 +0000 +@@ -324,8 +324,6 @@ if (ret) goto err_g1; @@ -3569,11 +3568,11 @@ dev->pdev = pdev; dev->dev = &pdev->dev; -diff --git a/drivers/gpu/drm/drm_platform.c b/drivers/gpu/drm/drm_platform.c -index ae9db5e..82431dc 100644 ---- a/drivers/gpu/drm/drm_platform.c -+++ b/drivers/gpu/drm/drm_platform.c -@@ -122,7 +122,7 @@ static const char *drm_platform_get_name(struct drm_device *dev) +Index: linux-3.2.46/drivers/gpu/drm/drm_platform.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/drm_platform.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/drm_platform.c 2013-07-26 19:26:21.000000000 +0000 +@@ -122,7 +122,7 @@ static int drm_platform_set_busid(struct drm_device *dev, struct drm_master *master) { @@ -3582,7 +3581,7 @@ master->unique_len = 13 + strlen(dev->platformdev->name); master->unique_size = master->unique_len; -@@ -131,8 +131,16 @@ static int drm_platform_set_busid(struct drm_device *dev, struct drm_master *mas +@@ -131,8 +131,16 @@ if (master->unique == NULL) return -ENOMEM; @@ -3600,11 +3599,10 @@ if (len > master->unique_len) { DRM_ERROR("Unique buffer overflowed\n"); -diff --git a/drivers/gpu/drm/drm_prime.c b/drivers/gpu/drm/drm_prime.c -new file mode 100644 -index 0000000..1bdf2b5 ---- /dev/null -+++ b/drivers/gpu/drm/drm_prime.c +Index: linux-3.2.46/drivers/gpu/drm/drm_prime.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/drm_prime.c 2013-07-26 19:26:21.000000000 +0000 @@ -0,0 +1,304 @@ +/* + * Copyright © 2012 Red Hat @@ -3910,11 +3908,10 @@ + mutex_unlock(&prime_fpriv->lock); +} +EXPORT_SYMBOL(drm_prime_remove_imported_buf_handle); -diff --git a/drivers/gpu/drm/drm_sman.c b/drivers/gpu/drm/drm_sman.c -deleted file mode 100644 -index cebce45..0000000 ---- a/drivers/gpu/drm/drm_sman.c -+++ /dev/null +Index: linux-3.2.46/drivers/gpu/drm/drm_sman.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/drm_sman.c 2013-07-26 18:53:34.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 @@ -1,351 +0,0 @@ -/************************************************************************** - * @@ -4267,11 +4264,11 @@ -} - -EXPORT_SYMBOL(drm_sman_cleanup); -diff --git a/drivers/gpu/drm/drm_stub.c b/drivers/gpu/drm/drm_stub.c -index 6d7b083..aa454f8 100644 ---- a/drivers/gpu/drm/drm_stub.c -+++ b/drivers/gpu/drm/drm_stub.c -@@ -319,6 +319,7 @@ int drm_fill_in_dev(struct drm_device *dev, +Index: linux-3.2.46/drivers/gpu/drm/drm_stub.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/drm_stub.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/drm_stub.c 2013-07-26 19:26:21.000000000 +0000 +@@ -319,6 +319,7 @@ drm_lastclose(dev); return retcode; } @@ -4279,7 +4276,7 @@ /** -@@ -397,6 +398,7 @@ err_idr: +@@ -397,6 +398,7 @@ *minor = NULL; return ret; } @@ -4287,7 +4284,7 @@ /** * Put a secondary minor number. -@@ -428,6 +430,12 @@ int drm_put_minor(struct drm_minor **minor_p) +@@ -428,6 +430,12 @@ *minor_p = NULL; return 0; } @@ -4300,7 +4297,7 @@ /** * Called via drm_exit() at module unload time or when pci device is -@@ -492,3 +500,21 @@ void drm_put_dev(struct drm_device *dev) +@@ -492,3 +500,21 @@ kfree(dev); } EXPORT_SYMBOL(drm_put_dev); @@ -4322,11 +4319,11 @@ + mutex_unlock(&drm_global_mutex); +} +EXPORT_SYMBOL(drm_unplug_dev); -diff --git a/drivers/gpu/drm/drm_sysfs.c b/drivers/gpu/drm/drm_sysfs.c -index 0f9ef9b..5a7bd51 100644 ---- a/drivers/gpu/drm/drm_sysfs.c -+++ b/drivers/gpu/drm/drm_sysfs.c -@@ -72,7 +72,7 @@ static int drm_class_resume(struct device *dev) +Index: linux-3.2.46/drivers/gpu/drm/drm_sysfs.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/drm_sysfs.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/drm_sysfs.c 2013-07-26 19:26:21.000000000 +0000 +@@ -72,7 +72,7 @@ return 0; } @@ -4335,7 +4332,7 @@ { return kasprintf(GFP_KERNEL, "dri/%s", dev_name(dev)); } -@@ -454,6 +454,8 @@ void drm_sysfs_connector_remove(struct drm_connector *connector) +@@ -454,6 +454,8 @@ { int i; @@ -4344,7 +4341,7 @@ DRM_DEBUG("removing \"%s\" from sysfs\n", drm_get_connector_name(connector)); -@@ -461,6 +463,7 @@ void drm_sysfs_connector_remove(struct drm_connector *connector) +@@ -461,6 +463,7 @@ device_remove_file(&connector->kdev, &connector_attrs[i]); sysfs_remove_bin_file(&connector->kdev.kobj, &edid_attr); device_unregister(&connector->kdev); @@ -4352,7 +4349,7 @@ } EXPORT_SYMBOL(drm_sysfs_connector_remove); -@@ -533,7 +536,9 @@ err_out: +@@ -533,7 +536,9 @@ */ void drm_sysfs_device_remove(struct drm_minor *minor) { @@ -4363,10 +4360,10 @@ } -diff --git a/drivers/gpu/drm/drm_usb.c b/drivers/gpu/drm/drm_usb.c -index 471f453..767782a 100644 ---- a/drivers/gpu/drm/drm_usb.c -+++ b/drivers/gpu/drm/drm_usb.c +Index: linux-3.2.46/drivers/gpu/drm/drm_usb.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/drm_usb.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/drm_usb.c 2013-07-26 19:26:21.000000000 +0000 @@ -1,8 +1,7 @@ #include "drmP.h" #include @@ -4377,7 +4374,7 @@ int drm_get_usb_dev(struct usb_interface *interface, const struct usb_device_id *id, struct drm_driver *driver) -@@ -115,4 +114,7 @@ void drm_usb_exit(struct drm_driver *driver, +@@ -115,4 +114,7 @@ usb_deregister(udriver); } EXPORT_SYMBOL(drm_usb_exit); @@ -4386,11 +4383,11 @@ +MODULE_AUTHOR("David Airlie"); +MODULE_DESCRIPTION("USB DRM support"); +MODULE_LICENSE("GPL and additional rights"); -diff --git a/drivers/gpu/drm/drm_vm.c b/drivers/gpu/drm/drm_vm.c -index 8c03eaf..1495618 100644 ---- a/drivers/gpu/drm/drm_vm.c -+++ b/drivers/gpu/drm/drm_vm.c -@@ -519,7 +519,6 @@ static int drm_mmap_dma(struct file *filp, struct vm_area_struct *vma) +Index: linux-3.2.46/drivers/gpu/drm/drm_vm.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/drm_vm.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/drm_vm.c 2013-07-26 19:26:21.000000000 +0000 +@@ -519,7 +519,6 @@ vma->vm_flags |= VM_RESERVED; /* Don't swap */ vma->vm_flags |= VM_DONTEXPAND; @@ -4398,7 +4395,7 @@ drm_vm_open_locked(vma); return 0; } -@@ -671,7 +670,6 @@ int drm_mmap_locked(struct file *filp, struct vm_area_struct *vma) +@@ -671,7 +670,6 @@ vma->vm_flags |= VM_RESERVED; /* Don't swap */ vma->vm_flags |= VM_DONTEXPAND; @@ -4406,7 +4403,7 @@ drm_vm_open_locked(vma); return 0; } -@@ -682,6 +680,9 @@ int drm_mmap(struct file *filp, struct vm_area_struct *vma) +@@ -682,6 +680,9 @@ struct drm_device *dev = priv->minor->dev; int ret; @@ -4416,10 +4413,10 @@ mutex_lock(&dev->struct_mutex); ret = drm_mmap_locked(filp, vma); mutex_unlock(&dev->struct_mutex); -diff --git a/drivers/gpu/drm/exynos/Kconfig b/drivers/gpu/drm/exynos/Kconfig -index 847466a..3343ac4 100644 ---- a/drivers/gpu/drm/exynos/Kconfig -+++ b/drivers/gpu/drm/exynos/Kconfig +Index: linux-3.2.46/drivers/gpu/drm/exynos/Kconfig +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/exynos/Kconfig 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/exynos/Kconfig 2013-07-26 19:26:21.000000000 +0000 @@ -1,7 +1,6 @@ config DRM_EXYNOS tristate "DRM Support for Samsung SoC EXYNOS Series" @@ -4428,7 +4425,7 @@ select DRM_KMS_HELPER select FB_CFB_FILLRECT select FB_CFB_COPYAREA -@@ -12,9 +11,19 @@ config DRM_EXYNOS +@@ -12,9 +11,19 @@ If M is selected the module will be called exynosdrm. config DRM_EXYNOS_FIMD @@ -4452,10 +4449,10 @@ + depends on DRM_EXYNOS + help + Choose this option if you want to use Exynos VIDI for DRM. -diff --git a/drivers/gpu/drm/exynos/Makefile b/drivers/gpu/drm/exynos/Makefile -index 0496d3f..9e0bff8 100644 ---- a/drivers/gpu/drm/exynos/Makefile -+++ b/drivers/gpu/drm/exynos/Makefile +Index: linux-3.2.46/drivers/gpu/drm/exynos/Makefile +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/exynos/Makefile 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/exynos/Makefile 2013-07-26 19:26:21.000000000 +0000 @@ -5,7 +5,13 @@ ccflags-y := -Iinclude/drm -Idrivers/gpu/drm/exynos exynosdrm-y := exynos_drm_drv.o exynos_drm_encoder.o exynos_drm_connector.o \ @@ -4473,11 +4470,10 @@ +exynosdrm-$(CONFIG_DRM_EXYNOS_VIDI) += exynos_drm_vidi.o + +obj-$(CONFIG_DRM_EXYNOS) += exynosdrm.o -diff --git a/drivers/gpu/drm/exynos/exynos_ddc.c b/drivers/gpu/drm/exynos/exynos_ddc.c -new file mode 100644 -index 0000000..7e1051d ---- /dev/null -+++ b/drivers/gpu/drm/exynos/exynos_ddc.c +Index: linux-3.2.46/drivers/gpu/drm/exynos/exynos_ddc.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/exynos/exynos_ddc.c 2013-07-26 19:26:21.000000000 +0000 @@ -0,0 +1,57 @@ +/* + * Copyright (C) 2011 Samsung Electronics Co.Ltd @@ -4536,10 +4532,10 @@ + .remove = __devexit_p(s5p_ddc_remove), + .command = NULL, +}; -diff --git a/drivers/gpu/drm/exynos/exynos_drm_buf.c b/drivers/gpu/drm/exynos/exynos_drm_buf.c -index 2bb07bc..de8d209 100644 ---- a/drivers/gpu/drm/exynos/exynos_drm_buf.c -+++ b/drivers/gpu/drm/exynos/exynos_drm_buf.c +Index: linux-3.2.46/drivers/gpu/drm/exynos/exynos_drm_buf.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/exynos/exynos_drm_buf.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/exynos/exynos_drm_buf.c 2013-07-26 19:26:21.000000000 +0000 @@ -25,45 +25,142 @@ #include "drmP.h" @@ -4589,22 +4585,17 @@ + buf->sgt = kzalloc(sizeof(struct sg_table), GFP_KERNEL); + if (!buf->sgt) { + DRM_ERROR("failed to allocate sg table.\n"); - return -ENOMEM; - } - -- DRM_DEBUG_KMS("vaddr(0x%lx), dma_addr(0x%lx), size(0x%lx)\n", -- (unsigned long)buffer->kvaddr, -- (unsigned long)buffer->dma_addr, -- buffer->size); ++ return -ENOMEM; ++ } ++ + ret = sg_alloc_table(buf->sgt, npages, GFP_KERNEL); + if (ret < 0) { + DRM_ERROR("failed to initialize sg table.\n"); + kfree(buf->sgt); + buf->sgt = NULL; -+ return -ENOMEM; -+ } + return -ENOMEM; + } -- return 0; + buf->kvaddr = dma_alloc_writecombine(dev->dev, buf->size, + &buf->dma_addr, GFP_KERNEL); + if (!buf->kvaddr) { @@ -4632,7 +4623,10 @@ + i++; + } + -+ DRM_DEBUG_KMS("vaddr(0x%lx), dma_addr(0x%lx), size(0x%lx)\n", + DRM_DEBUG_KMS("vaddr(0x%lx), dma_addr(0x%lx), size(0x%lx)\n", +- (unsigned long)buffer->kvaddr, +- (unsigned long)buffer->dma_addr, +- buffer->size); + (unsigned long)buf->kvaddr, + (unsigned long)buf->dma_addr, + buf->size); @@ -4646,7 +4640,8 @@ + sg_free_table(buf->sgt); + kfree(buf->sgt); + buf->sgt = NULL; -+ + +- return 0; + return ret; } @@ -4701,7 +4696,7 @@ { struct exynos_drm_gem_buf *buffer; -@@ -73,26 +170,15 @@ struct exynos_drm_gem_buf *exynos_drm_buf_create(struct drm_device *dev, +@@ -73,26 +170,15 @@ buffer = kzalloc(sizeof(*buffer), GFP_KERNEL); if (!buffer) { DRM_ERROR("failed to allocate exynos_drm_gem_buf.\n"); @@ -4731,7 +4726,7 @@ { DRM_DEBUG_KMS("%s.\n", __FILE__); -@@ -101,12 +187,27 @@ void exynos_drm_buf_destroy(struct drm_device *dev, +@@ -101,12 +187,27 @@ return; } @@ -4764,10 +4759,10 @@ + + lowlevel_buffer_deallocate(dev, flags, buffer); +} -diff --git a/drivers/gpu/drm/exynos/exynos_drm_buf.h b/drivers/gpu/drm/exynos/exynos_drm_buf.h -index 6e91f9c..3388e4e 100644 ---- a/drivers/gpu/drm/exynos/exynos_drm_buf.h -+++ b/drivers/gpu/drm/exynos/exynos_drm_buf.h +Index: linux-3.2.46/drivers/gpu/drm/exynos/exynos_drm_buf.h +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/exynos/exynos_drm_buf.h 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/exynos/exynos_drm_buf.h 2013-07-26 19:26:21.000000000 +0000 @@ -26,15 +26,22 @@ #ifndef _EXYNOS_DRM_BUF_H_ #define _EXYNOS_DRM_BUF_H_ @@ -4799,10 +4794,10 @@ + struct exynos_drm_gem_buf *buffer); #endif -diff --git a/drivers/gpu/drm/exynos/exynos_drm_connector.c b/drivers/gpu/drm/exynos/exynos_drm_connector.c -index d620b07..bf791fa 100644 ---- a/drivers/gpu/drm/exynos/exynos_drm_connector.c -+++ b/drivers/gpu/drm/exynos/exynos_drm_connector.c +Index: linux-3.2.46/drivers/gpu/drm/exynos/exynos_drm_connector.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/exynos/exynos_drm_connector.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/exynos/exynos_drm_connector.c 2013-07-26 19:26:21.000000000 +0000 @@ -28,6 +28,7 @@ #include "drmP.h" #include "drm_crtc_helper.h" @@ -4811,7 +4806,7 @@ #include "exynos_drm_drv.h" #include "exynos_drm_encoder.h" -@@ -44,22 +45,25 @@ struct exynos_drm_connector { +@@ -44,22 +45,25 @@ /* convert exynos_video_timings to drm_display_mode */ static inline void convert_to_display_mode(struct drm_display_mode *mode, @@ -4842,7 +4837,7 @@ if (timing->vmode & FB_VMODE_INTERLACED) mode->flags |= DRM_MODE_FLAG_INTERLACE; -@@ -81,14 +85,14 @@ convert_to_video_timing(struct fb_videomode *timing, +@@ -81,14 +85,14 @@ timing->refresh = drm_mode_vrefresh(mode); timing->xres = mode->hdisplay; @@ -4861,7 +4856,7 @@ if (mode->flags & DRM_MODE_FLAG_INTERLACE) timing->vmode = FB_VMODE_INTERLACED; -@@ -148,16 +152,18 @@ static int exynos_drm_connector_get_modes(struct drm_connector *connector) +@@ -148,16 +152,18 @@ connector->display_info.raw_edid = edid; } else { struct drm_display_mode *mode = drm_mode_create(connector->dev); @@ -4884,7 +4879,7 @@ mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED; drm_mode_set_name(mode); -@@ -219,6 +225,29 @@ static struct drm_connector_helper_funcs exynos_connector_helper_funcs = { +@@ -219,6 +225,29 @@ .best_encoder = exynos_drm_best_encoder, }; @@ -4914,7 +4909,7 @@ /* get detection status of display device. */ static enum drm_connector_status exynos_drm_connector_detect(struct drm_connector *connector, bool force) -@@ -256,7 +285,7 @@ static void exynos_drm_connector_destroy(struct drm_connector *connector) +@@ -256,7 +285,7 @@ static struct drm_connector_funcs exynos_connector_funcs = { .dpms = drm_helper_connector_dpms, @@ -4923,7 +4918,7 @@ .detect = exynos_drm_connector_detect, .destroy = exynos_drm_connector_destroy, }; -@@ -286,6 +315,10 @@ struct drm_connector *exynos_drm_connector_create(struct drm_device *dev, +@@ -286,6 +315,10 @@ connector->interlace_allowed = true; connector->polled = DRM_CONNECTOR_POLL_HPD; break; @@ -4934,7 +4929,7 @@ default: type = DRM_MODE_CONNECTOR_Unknown; break; -@@ -319,9 +352,3 @@ err_connector: +@@ -319,9 +352,3 @@ kfree(exynos_connector); return NULL; } @@ -4944,10 +4939,10 @@ -MODULE_AUTHOR("Seung-Woo Kim "); -MODULE_DESCRIPTION("Samsung SoC DRM Connector Driver"); -MODULE_LICENSE("GPL"); -diff --git a/drivers/gpu/drm/exynos/exynos_drm_core.c b/drivers/gpu/drm/exynos/exynos_drm_core.c -index 661a035..eaf630d 100644 ---- a/drivers/gpu/drm/exynos/exynos_drm_core.c -+++ b/drivers/gpu/drm/exynos/exynos_drm_core.c +Index: linux-3.2.46/drivers/gpu/drm/exynos/exynos_drm_core.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/exynos/exynos_drm_core.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/exynos/exynos_drm_core.c 2013-07-26 19:26:21.000000000 +0000 @@ -32,7 +32,6 @@ #include "exynos_drm_connector.h" #include "exynos_drm_fbdev.h" @@ -4956,7 +4951,7 @@ static LIST_HEAD(exynos_drm_subdrv_list); static struct drm_device *drm_dev; -@@ -55,13 +54,18 @@ static int exynos_drm_subdrv_probe(struct drm_device *dev, +@@ -55,13 +54,18 @@ * * P.S. note that this driver is considered for modularization. */ @@ -4977,7 +4972,7 @@ (1 << MAX_CRTC) - 1); if (!encoder) { DRM_ERROR("failed to create encoder\n"); -@@ -116,13 +120,10 @@ int exynos_drm_device_register(struct drm_device *dev) +@@ -116,13 +120,10 @@ if (!dev) return -EINVAL; @@ -4993,7 +4988,7 @@ err = exynos_drm_subdrv_probe(dev, subdrv); if (err) { DRM_DEBUG("exynos drm subdrv probe failed.\n"); -@@ -130,9 +131,6 @@ int exynos_drm_device_register(struct drm_device *dev) +@@ -130,9 +131,6 @@ } } @@ -5003,7 +4998,7 @@ return 0; } EXPORT_SYMBOL_GPL(exynos_drm_device_register); -@@ -143,83 +141,28 @@ int exynos_drm_device_unregister(struct drm_device *dev) +@@ -143,83 +141,28 @@ DRM_DEBUG_DRIVER("%s\n", __FILE__); @@ -5088,7 +5083,7 @@ return 0; } -@@ -227,46 +170,48 @@ EXPORT_SYMBOL_GPL(exynos_drm_subdrv_register); +@@ -227,46 +170,48 @@ int exynos_drm_subdrv_unregister(struct exynos_drm_subdrv *subdrv) { @@ -5169,10 +5164,10 @@ + } +} +EXPORT_SYMBOL_GPL(exynos_drm_subdrv_close); -diff --git a/drivers/gpu/drm/exynos/exynos_drm_crtc.c b/drivers/gpu/drm/exynos/exynos_drm_crtc.c -index ee43cc2..3486ffe 100644 ---- a/drivers/gpu/drm/exynos/exynos_drm_crtc.c -+++ b/drivers/gpu/drm/exynos/exynos_drm_crtc.c +Index: linux-3.2.46/drivers/gpu/drm/exynos/exynos_drm_crtc.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/exynos/exynos_drm_crtc.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/exynos/exynos_drm_crtc.c 2013-07-26 19:26:21.000000000 +0000 @@ -34,7 +34,6 @@ #include "exynos_drm_fb.h" #include "exynos_drm_encoder.h" @@ -5195,13 +5190,18 @@ }; static void exynos_drm_crtc_apply(struct drm_crtc *crtc) -@@ -78,19 +79,23 @@ int exynos_drm_overlay_update(struct exynos_drm_overlay *overlay, +@@ -78,19 +79,23 @@ struct exynos_drm_gem_buf *buffer; unsigned int actual_w; unsigned int actual_h; + int nr = exynos_drm_format_num_buffers(fb->pixel_format); + int i; -+ + +- buffer = exynos_drm_fb_get_buf(fb); +- if (!buffer) { +- DRM_LOG_KMS("buffer is null.\n"); +- return -EFAULT; +- } + for (i = 0; i < nr; i++) { + buffer = exynos_drm_fb_buffer(fb, i); + if (!buffer) { @@ -5209,12 +5209,6 @@ + return -EFAULT; + } -- buffer = exynos_drm_fb_get_buf(fb); -- if (!buffer) { -- DRM_LOG_KMS("buffer is null.\n"); -- return -EFAULT; -- } -- - overlay->dma_addr = buffer->dma_addr; - overlay->vaddr = buffer->kvaddr; + overlay->dma_addr[i] = buffer->dma_addr; @@ -5230,7 +5224,7 @@ actual_w = min((mode->hdisplay - pos->crtc_x), pos->crtc_w); actual_h = min((mode->vdisplay - pos->crtc_y), pos->crtc_h); -@@ -101,7 +106,8 @@ int exynos_drm_overlay_update(struct exynos_drm_overlay *overlay, +@@ -101,7 +106,8 @@ overlay->fb_width = fb->width; overlay->fb_height = fb->height; overlay->bpp = fb->bits_per_pixel; @@ -5240,7 +5234,7 @@ /* set overlay range to be displayed. */ overlay->crtc_x = pos->crtc_x; -@@ -153,26 +159,37 @@ static int exynos_drm_crtc_update(struct drm_crtc *crtc) +@@ -153,26 +159,37 @@ static void exynos_drm_crtc_dpms(struct drm_crtc *crtc, int mode) { @@ -5284,7 +5278,7 @@ } static void exynos_drm_crtc_prepare(struct drm_crtc *crtc) -@@ -188,6 +205,28 @@ static void exynos_drm_crtc_commit(struct drm_crtc *crtc) +@@ -188,6 +205,28 @@ DRM_DEBUG_KMS("%s\n", __FILE__); @@ -5313,7 +5307,7 @@ exynos_drm_fn_encoder(crtc, &exynos_crtc->pipe, exynos_drm_encoder_crtc_commit); } -@@ -210,7 +249,11 @@ exynos_drm_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *mode, +@@ -210,7 +249,11 @@ { DRM_DEBUG_KMS("%s\n", __FILE__); @@ -5326,7 +5320,7 @@ return exynos_drm_crtc_update(crtc); } -@@ -268,9 +311,6 @@ static int exynos_drm_crtc_page_flip(struct drm_crtc *crtc, +@@ -268,9 +311,6 @@ */ event->pipe = exynos_crtc->pipe; @@ -5336,7 +5330,7 @@ ret = drm_vblank_get(dev, exynos_crtc->pipe); if (ret) { DRM_DEBUG("failed to acquire vblank counter\n"); -@@ -279,6 +319,9 @@ static int exynos_drm_crtc_page_flip(struct drm_crtc *crtc, +@@ -279,6 +319,9 @@ goto out; } @@ -5346,7 +5340,7 @@ crtc->fb = fb; ret = exynos_drm_crtc_update(crtc); if (ret) { -@@ -344,6 +387,8 @@ int exynos_drm_crtc_create(struct drm_device *dev, unsigned int nr) +@@ -344,6 +387,8 @@ } exynos_crtc->pipe = nr; @@ -5355,7 +5349,7 @@ crtc = &exynos_crtc->drm_crtc; private->crtc[nr] = crtc; -@@ -357,9 +402,14 @@ int exynos_drm_crtc_create(struct drm_device *dev, unsigned int nr) +@@ -357,9 +402,14 @@ int exynos_drm_crtc_enable_vblank(struct drm_device *dev, int crtc) { struct exynos_drm_private *private = dev->dev_private; @@ -5370,7 +5364,7 @@ exynos_drm_fn_encoder(private->crtc[crtc], &crtc, exynos_drm_enable_vblank); -@@ -369,15 +419,14 @@ int exynos_drm_crtc_enable_vblank(struct drm_device *dev, int crtc) +@@ -369,15 +419,14 @@ void exynos_drm_crtc_disable_vblank(struct drm_device *dev, int crtc) { struct exynos_drm_private *private = dev->dev_private; @@ -5391,10 +5385,10 @@ -MODULE_AUTHOR("Seung-Woo Kim "); -MODULE_DESCRIPTION("Samsung SoC DRM CRTC Driver"); -MODULE_LICENSE("GPL"); -diff --git a/drivers/gpu/drm/exynos/exynos_drm_drv.c b/drivers/gpu/drm/exynos/exynos_drm_drv.c -index 53e2216..a6819b5 100644 ---- a/drivers/gpu/drm/exynos/exynos_drm_drv.c -+++ b/drivers/gpu/drm/exynos/exynos_drm_drv.c +Index: linux-3.2.46/drivers/gpu/drm/exynos/exynos_drm_drv.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/exynos/exynos_drm_drv.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/exynos/exynos_drm_drv.c 2013-07-26 19:26:21.000000000 +0000 @@ -33,16 +33,21 @@ #include "exynos_drm_drv.h" @@ -5418,7 +5412,7 @@ static int exynos_drm_load(struct drm_device *dev, unsigned long flags) { struct exynos_drm_private *private; -@@ -77,6 +82,12 @@ static int exynos_drm_load(struct drm_device *dev, unsigned long flags) +@@ -77,6 +82,12 @@ goto err_crtc; } @@ -5431,7 +5425,7 @@ ret = drm_vblank_init(dev, MAX_CRTC); if (ret) goto err_crtc; -@@ -90,6 +101,9 @@ static int exynos_drm_load(struct drm_device *dev, unsigned long flags) +@@ -90,6 +101,9 @@ if (ret) goto err_vblank; @@ -5441,7 +5435,7 @@ /* * create and configure fb helper and also exynos specific * fbdev object. -@@ -100,6 +114,8 @@ static int exynos_drm_load(struct drm_device *dev, unsigned long flags) +@@ -100,6 +114,8 @@ goto err_drm_device; } @@ -5450,7 +5444,7 @@ return 0; err_drm_device: -@@ -129,17 +145,45 @@ static int exynos_drm_unload(struct drm_device *dev) +@@ -129,17 +145,45 @@ return 0; } @@ -5504,7 +5498,7 @@ } static void exynos_drm_lastclose(struct drm_device *dev) -@@ -163,6 +207,20 @@ static struct drm_ioctl_desc exynos_ioctls[] = { +@@ -163,6 +207,20 @@ DRM_AUTH), DRM_IOCTL_DEF_DRV(EXYNOS_GEM_MMAP, exynos_drm_gem_mmap_ioctl, DRM_UNLOCKED | DRM_AUTH), @@ -5525,7 +5519,7 @@ }; static struct drm_driver exynos_drm_driver = { -@@ -170,8 +228,10 @@ static struct drm_driver exynos_drm_driver = { +@@ -170,8 +228,10 @@ DRIVER_MODESET | DRIVER_GEM, .load = exynos_drm_load, .unload = exynos_drm_unload, @@ -5536,7 +5530,7 @@ .get_vblank_counter = drm_vblank_count, .enable_vblank = exynos_drm_crtc_enable_vblank, .disable_vblank = exynos_drm_crtc_disable_vblank, -@@ -182,15 +242,7 @@ static struct drm_driver exynos_drm_driver = { +@@ -182,15 +242,7 @@ .dumb_map_offset = exynos_drm_gem_dumb_map_offset, .dumb_destroy = exynos_drm_gem_dumb_destroy, .ioctls = exynos_ioctls, @@ -5553,7 +5547,7 @@ .name = DRIVER_NAME, .desc = DRIVER_DESC, .date = DRIVER_DATE, -@@ -221,15 +273,66 @@ static struct platform_driver exynos_drm_platform_driver = { +@@ -221,15 +273,66 @@ .remove = __devexit_p(exynos_drm_platform_remove), .driver = { .owner = THIS_MODULE, @@ -5622,7 +5616,7 @@ } static void __exit exynos_drm_exit(void) -@@ -237,6 +340,20 @@ static void __exit exynos_drm_exit(void) +@@ -237,6 +340,20 @@ DRM_DEBUG_DRIVER("%s\n", __FILE__); platform_driver_unregister(&exynos_drm_platform_driver); @@ -5643,10 +5637,10 @@ } module_init(exynos_drm_init); -diff --git a/drivers/gpu/drm/exynos/exynos_drm_drv.h b/drivers/gpu/drm/exynos/exynos_drm_drv.h -index 5e02e6e..1d81417 100644 ---- a/drivers/gpu/drm/exynos/exynos_drm_drv.h -+++ b/drivers/gpu/drm/exynos/exynos_drm_drv.h +Index: linux-3.2.46/drivers/gpu/drm/exynos/exynos_drm_drv.h +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/exynos/exynos_drm_drv.h 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/exynos/exynos_drm_drv.h 2013-07-26 19:26:21.000000000 +0000 @@ -32,12 +32,17 @@ #include #include "drm.h" @@ -5666,7 +5660,7 @@ /* this enumerates display type. */ enum exynos_drm_output_type { EXYNOS_DISPLAY_TYPE_NONE, -@@ -45,6 +50,8 @@ enum exynos_drm_output_type { +@@ -45,6 +50,8 @@ EXYNOS_DISPLAY_TYPE_LCD, /* HDMI Interface. */ EXYNOS_DISPLAY_TYPE_HDMI, @@ -5675,7 +5669,7 @@ }; /* -@@ -57,8 +64,8 @@ enum exynos_drm_output_type { +@@ -57,8 +64,8 @@ struct exynos_drm_overlay_ops { void (*mode_set)(struct device *subdrv_dev, struct exynos_drm_overlay *overlay); @@ -5686,7 +5680,7 @@ }; /* -@@ -80,9 +87,11 @@ struct exynos_drm_overlay_ops { +@@ -80,9 +87,11 @@ * @scan_flag: interlace or progressive way. * (it could be DRM_MODE_FLAG_*) * @bpp: pixel size.(in bit) @@ -5701,7 +5695,7 @@ * @default_win: a window to be enabled. * @color_key: color key on or off. * @index_color: if using color key feature then this value would be used -@@ -109,8 +118,10 @@ struct exynos_drm_overlay { +@@ -109,8 +118,10 @@ unsigned int scan_flag; unsigned int bpp; unsigned int pitch; @@ -5714,7 +5708,7 @@ bool default_win; bool color_key; -@@ -127,7 +138,7 @@ struct exynos_drm_overlay { +@@ -127,7 +138,7 @@ * @type: one of EXYNOS_DISPLAY_TYPE_LCD and HDMI. * @is_connected: check for that display is connected or not. * @get_edid: get edid modes from display driver. @@ -5723,7 +5717,7 @@ * @check_timing: check if timing is valid or not. * @power_on: display device on or off. */ -@@ -136,7 +147,7 @@ struct exynos_drm_display_ops { +@@ -136,7 +147,7 @@ bool (*is_connected)(struct device *dev); int (*get_edid)(struct device *dev, struct drm_connector *connector, u8 *edid, int len); @@ -5732,7 +5726,7 @@ int (*check_timing)(struct device *dev, void *timing); int (*power_on)(struct device *dev, int mode); }; -@@ -144,17 +155,27 @@ struct exynos_drm_display_ops { +@@ -144,17 +155,27 @@ /* * Exynos drm manager ops * @@ -5762,7 +5756,7 @@ int (*enable_vblank)(struct device *subdrv_dev); void (*disable_vblank)(struct device *subdrv_dev); }; -@@ -204,25 +225,33 @@ struct exynos_drm_private { +@@ -204,25 +225,33 @@ * Exynos drm sub driver structure. * * @list: sub driver has its own list object to register to exynos drm driver. @@ -5799,7 +5793,7 @@ struct drm_encoder *encoder; struct drm_connector *connector; }; -@@ -243,15 +272,19 @@ int exynos_drm_device_unregister(struct drm_device *dev); +@@ -243,15 +272,19 @@ * this function would be called by sub drivers such as display controller * or hdmi driver to register this sub driver object to exynos drm driver * and when a sub driver is registered to exynos drm driver a probe callback @@ -5825,10 +5819,10 @@ +extern struct platform_driver exynos_drm_common_hdmi_driver; +extern struct platform_driver vidi_driver; #endif -diff --git a/drivers/gpu/drm/exynos/exynos_drm_encoder.c b/drivers/gpu/drm/exynos/exynos_drm_encoder.c -index 1530614..6e9ac7b 100644 ---- a/drivers/gpu/drm/exynos/exynos_drm_encoder.c -+++ b/drivers/gpu/drm/exynos/exynos_drm_encoder.c +Index: linux-3.2.46/drivers/gpu/drm/exynos/exynos_drm_encoder.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/exynos/exynos_drm_encoder.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/exynos/exynos_drm_encoder.c 2013-07-26 19:26:22.000000000 +0000 @@ -42,49 +42,68 @@ * @drm_encoder: encoder object. * @manager: specific encoder has its own manager to control a hardware @@ -5915,7 +5909,7 @@ } static bool -@@ -92,9 +111,19 @@ exynos_drm_encoder_mode_fixup(struct drm_encoder *encoder, +@@ -92,9 +111,19 @@ struct drm_display_mode *mode, struct drm_display_mode *adjusted_mode) { @@ -5936,7 +5930,7 @@ return true; } -@@ -113,12 +142,11 @@ static void exynos_drm_encoder_mode_set(struct drm_encoder *encoder, +@@ -113,12 +142,11 @@ DRM_DEBUG_KMS("%s\n", __FILE__); @@ -5951,7 +5945,7 @@ if (overlay_ops && overlay_ops->mode_set) overlay_ops->mode_set(manager->dev, overlay); -@@ -169,7 +197,6 @@ static void exynos_drm_encoder_destroy(struct drm_encoder *encoder) +@@ -169,7 +197,6 @@ exynos_encoder->manager->pipe = -1; drm_encoder_cleanup(encoder); @@ -5959,7 +5953,7 @@ kfree(exynos_encoder); } -@@ -177,6 +204,41 @@ static struct drm_encoder_funcs exynos_encoder_funcs = { +@@ -177,6 +204,41 @@ .destroy = exynos_drm_encoder_destroy, }; @@ -6001,7 +5995,7 @@ struct drm_encoder * exynos_drm_encoder_create(struct drm_device *dev, struct exynos_drm_manager *manager, -@@ -199,6 +261,7 @@ exynos_drm_encoder_create(struct drm_device *dev, +@@ -199,6 +261,7 @@ return NULL; } @@ -6009,7 +6003,7 @@ exynos_encoder->manager = manager; encoder = &exynos_encoder->drm_encoder; encoder->possible_crtcs = possible_crtcs; -@@ -275,12 +338,27 @@ void exynos_drm_disable_vblank(struct drm_encoder *encoder, void *data) +@@ -275,12 +338,27 @@ manager_ops->disable_vblank(manager->dev); } @@ -6038,7 +6032,7 @@ DRM_DEBUG_KMS("%s\n", __FILE__); -@@ -290,8 +368,53 @@ void exynos_drm_encoder_crtc_commit(struct drm_encoder *encoder, void *data) +@@ -290,8 +368,53 @@ */ manager->pipe = crtc; @@ -6094,7 +6088,7 @@ } void exynos_drm_encoder_crtc_mode_set(struct drm_encoder *encoder, void *data) -@@ -310,23 +433,13 @@ void exynos_drm_encoder_crtc_disable(struct drm_encoder *encoder, void *data) +@@ -310,23 +433,13 @@ struct exynos_drm_manager *manager = to_exynos_encoder(encoder)->manager; struct exynos_drm_overlay_ops *overlay_ops = manager->overlay_ops; @@ -6123,10 +6117,10 @@ -MODULE_AUTHOR("Seung-Woo Kim "); -MODULE_DESCRIPTION("Samsung SoC DRM Encoder Driver"); -MODULE_LICENSE("GPL"); -diff --git a/drivers/gpu/drm/exynos/exynos_drm_encoder.h b/drivers/gpu/drm/exynos/exynos_drm_encoder.h -index a22acfb..eb7d231 100644 ---- a/drivers/gpu/drm/exynos/exynos_drm_encoder.h -+++ b/drivers/gpu/drm/exynos/exynos_drm_encoder.h +Index: linux-3.2.46/drivers/gpu/drm/exynos/exynos_drm_encoder.h +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/exynos/exynos_drm_encoder.h 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/exynos/exynos_drm_encoder.h 2013-07-26 19:26:22.000000000 +0000 @@ -30,6 +30,7 @@ struct exynos_drm_manager; @@ -6135,7 +6129,7 @@ struct drm_encoder *exynos_drm_encoder_create(struct drm_device *dev, struct exynos_drm_manager *mgr, unsigned int possible_crtcs); -@@ -39,7 +40,12 @@ void exynos_drm_fn_encoder(struct drm_crtc *crtc, void *data, +@@ -39,7 +40,12 @@ void (*fn)(struct drm_encoder *, void *)); void exynos_drm_enable_vblank(struct drm_encoder *encoder, void *data); void exynos_drm_disable_vblank(struct drm_encoder *encoder, void *data); @@ -6148,10 +6142,10 @@ void exynos_drm_encoder_crtc_mode_set(struct drm_encoder *encoder, void *data); void exynos_drm_encoder_crtc_disable(struct drm_encoder *encoder, void *data); -diff --git a/drivers/gpu/drm/exynos/exynos_drm_fb.c b/drivers/gpu/drm/exynos/exynos_drm_fb.c -index 5bf4a1a..c38c8f4 100644 ---- a/drivers/gpu/drm/exynos/exynos_drm_fb.c -+++ b/drivers/gpu/drm/exynos/exynos_drm_fb.c +Index: linux-3.2.46/drivers/gpu/drm/exynos/exynos_drm_fb.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/exynos/exynos_drm_fb.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/exynos/exynos_drm_fb.c 2013-07-26 19:26:22.000000000 +0000 @@ -33,7 +33,6 @@ #include "exynos_drm_drv.h" @@ -6178,7 +6172,7 @@ }; static void exynos_drm_fb_destroy(struct drm_framebuffer *fb) -@@ -61,13 +56,6 @@ static void exynos_drm_fb_destroy(struct drm_framebuffer *fb) +@@ -61,13 +56,6 @@ drm_framebuffer_cleanup(fb); @@ -6192,7 +6186,7 @@ kfree(exynos_fb); exynos_fb = NULL; } -@@ -81,7 +69,7 @@ static int exynos_drm_fb_create_handle(struct drm_framebuffer *fb, +@@ -81,7 +69,7 @@ DRM_DEBUG_KMS("%s\n", __FILE__); return drm_gem_handle_create(file_priv, @@ -6201,7 +6195,7 @@ } static int exynos_drm_fb_dirty(struct drm_framebuffer *fb, -@@ -102,134 +90,88 @@ static struct drm_framebuffer_funcs exynos_drm_fb_funcs = { +@@ -102,134 +90,88 @@ .dirty = exynos_drm_fb_dirty, }; @@ -6321,29 +6315,18 @@ - * only its own buffer object. - */ - exynos_fb->buffer = exynos_gem_obj->buffer; -- ++ drm_gem_object_unreference_unlocked(obj); + - DRM_LOG_KMS("dma_addr = 0x%lx, size = 0x%x, gem object = 0x%x\n", - (unsigned long)exynos_fb->buffer->dma_addr, size, - (unsigned int)&exynos_gem_obj->base); -+ drm_gem_object_unreference_unlocked(obj); - --out: -- exynos_fb->exynos_gem_obj = exynos_gem_obj; + fb = exynos_drm_framebuffer_init(dev, mode_cmd, obj); + if (IS_ERR(fb)) + return fb; - -- drm_helper_mode_fill_fb_struct(fb, mode_cmd); ++ + exynos_fb = to_exynos_fb(fb); + nr = exynos_drm_format_num_buffers(fb->pixel_format); - -- return fb; -- --err_buffer: -- drm_framebuffer_cleanup(fb); -- --err_init: -- kfree(exynos_fb); ++ + for (i = 1; i < nr; i++) { + obj = drm_gem_object_lookup(dev, file_priv, + mode_cmd->handles[i]); @@ -6353,20 +6336,32 @@ + return ERR_PTR(-ENOENT); + } -- return ERR_PTR(ret); --} +-out: +- exynos_fb->exynos_gem_obj = exynos_gem_obj; + drm_gem_object_unreference_unlocked(obj); +- drm_helper_mode_fill_fb_struct(fb, mode_cmd); ++ exynos_fb->exynos_gem_obj[i] = to_exynos_gem_obj(obj); ++ } + + return fb; +- +-err_buffer: +- drm_framebuffer_cleanup(fb); +- +-err_init: +- kfree(exynos_fb); +- +- return ERR_PTR(ret); +-} +- -struct drm_framebuffer *exynos_drm_fb_create(struct drm_device *dev, - struct drm_file *file_priv, - struct drm_mode_fb_cmd *mode_cmd) -{ - DRM_DEBUG_KMS("%s\n", __FILE__); -+ exynos_fb->exynos_gem_obj[i] = to_exynos_gem_obj(obj); -+ } - +- - return exynos_drm_fb_init(file_priv, dev, mode_cmd); -+ return fb; } -struct exynos_drm_gem_buf *exynos_drm_fb_get_buf(struct drm_framebuffer *fb) @@ -6386,7 +6381,7 @@ if (!buffer) return NULL; -@@ -250,7 +192,7 @@ static void exynos_drm_output_poll_changed(struct drm_device *dev) +@@ -250,7 +192,7 @@ } static struct drm_mode_config_funcs exynos_drm_mode_config_funcs = { @@ -6395,7 +6390,7 @@ .output_poll_changed = exynos_drm_output_poll_changed, }; -@@ -269,9 +211,3 @@ void exynos_drm_mode_config_init(struct drm_device *dev) +@@ -269,9 +211,3 @@ dev->mode_config.funcs = &exynos_drm_mode_config_funcs; } @@ -6405,10 +6400,10 @@ -MODULE_AUTHOR("Seung-Woo Kim "); -MODULE_DESCRIPTION("Samsung SoC DRM FB Driver"); -MODULE_LICENSE("GPL"); -diff --git a/drivers/gpu/drm/exynos/exynos_drm_fb.h b/drivers/gpu/drm/exynos/exynos_drm_fb.h -index eb35931..3ecb30d 100644 ---- a/drivers/gpu/drm/exynos/exynos_drm_fb.h -+++ b/drivers/gpu/drm/exynos/exynos_drm_fb.h +Index: linux-3.2.46/drivers/gpu/drm/exynos/exynos_drm_fb.h +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/exynos/exynos_drm_fb.h 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/exynos/exynos_drm_fb.h 2013-07-26 19:26:22.000000000 +0000 @@ -28,9 +28,27 @@ #ifndef _EXYNOS_DRM_FB_H_ #define _EXYNOS_DRM_FB_H @@ -6440,10 +6435,10 @@ void exynos_drm_mode_config_init(struct drm_device *dev); -diff --git a/drivers/gpu/drm/exynos/exynos_drm_fbdev.c b/drivers/gpu/drm/exynos/exynos_drm_fbdev.c -index 836f4100..d5586cc 100644 ---- a/drivers/gpu/drm/exynos/exynos_drm_fbdev.c -+++ b/drivers/gpu/drm/exynos/exynos_drm_fbdev.c +Index: linux-3.2.46/drivers/gpu/drm/exynos/exynos_drm_fbdev.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/exynos/exynos_drm_fbdev.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/exynos/exynos_drm_fbdev.c 2013-07-26 19:26:22.000000000 +0000 @@ -34,7 +34,6 @@ #include "exynos_drm_drv.h" #include "exynos_drm_fb.h" @@ -6499,7 +6494,7 @@ .fb_blank = drm_fb_helper_blank, .fb_pan_display = drm_fb_helper_pan_display, .fb_setcmap = drm_fb_helper_setcmap, -@@ -90,26 +63,24 @@ static int exynos_drm_fbdev_update(struct drm_fb_helper *helper, +@@ -90,26 +63,24 @@ { struct fb_info *fbi = helper->fbdev; struct drm_device *dev = helper->dev; @@ -6530,7 +6525,7 @@ dev->mode_config.fb_base = (resource_size_t)buffer->dma_addr; fbi->screen_base = buffer->kvaddr + offset; -@@ -124,10 +95,12 @@ static int exynos_drm_fbdev_create(struct drm_fb_helper *helper, +@@ -124,10 +95,12 @@ struct drm_fb_helper_surface_size *sizes) { struct exynos_drm_fbdev *exynos_fbdev = to_exynos_fbdev(helper); @@ -6544,7 +6539,7 @@ int ret; DRM_DEBUG_KMS("%s\n", __FILE__); -@@ -138,8 +111,9 @@ static int exynos_drm_fbdev_create(struct drm_fb_helper *helper, +@@ -138,8 +111,9 @@ mode_cmd.width = sizes->surface_width; mode_cmd.height = sizes->surface_height; @@ -6556,7 +6551,7 @@ mutex_lock(&dev->struct_mutex); -@@ -150,14 +124,25 @@ static int exynos_drm_fbdev_create(struct drm_fb_helper *helper, +@@ -150,14 +124,25 @@ goto out; } @@ -6586,7 +6581,7 @@ helper->fbdev = fbi; fbi->par = helper; -@@ -171,8 +156,10 @@ static int exynos_drm_fbdev_create(struct drm_fb_helper *helper, +@@ -171,8 +156,10 @@ } ret = exynos_drm_fbdev_update(helper, helper->fb); @@ -6598,7 +6593,7 @@ /* * if failed, all resources allocated above would be released by -@@ -184,58 +171,6 @@ out: +@@ -184,58 +171,6 @@ return ret; } @@ -6657,7 +6652,7 @@ static int exynos_drm_fbdev_probe(struct drm_fb_helper *helper, struct drm_fb_helper_surface_size *sizes) { -@@ -243,6 +178,10 @@ static int exynos_drm_fbdev_probe(struct drm_fb_helper *helper, +@@ -243,6 +178,10 @@ DRM_DEBUG_KMS("%s\n", __FILE__); @@ -6668,7 +6663,7 @@ if (!helper->fb) { ret = exynos_drm_fbdev_create(helper, sizes); if (ret < 0) { -@@ -255,12 +194,6 @@ static int exynos_drm_fbdev_probe(struct drm_fb_helper *helper, +@@ -255,12 +194,6 @@ * because register_framebuffer() should be called. */ ret = 1; @@ -6681,7 +6676,7 @@ } return ret; -@@ -366,6 +299,9 @@ void exynos_drm_fbdev_fini(struct drm_device *dev) +@@ -366,6 +299,9 @@ fbdev = to_exynos_fbdev(private->fb_helper); @@ -6691,7 +6686,7 @@ exynos_drm_fbdev_destroy(dev, private->fb_helper); kfree(fbdev); private->fb_helper = NULL; -@@ -380,89 +316,3 @@ void exynos_drm_fbdev_restore_mode(struct drm_device *dev) +@@ -380,89 +316,3 @@ drm_fb_helper_restore_fbdev_mode(private->fb_helper); } @@ -6781,10 +6776,10 @@ -MODULE_AUTHOR("Seung-Woo Kim "); -MODULE_DESCRIPTION("Samsung SoC DRM FBDEV Driver"); -MODULE_LICENSE("GPL"); -diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c b/drivers/gpu/drm/exynos/exynos_drm_fimd.c -index db3b3d9..29fdbfe 100644 ---- a/drivers/gpu/drm/exynos/exynos_drm_fimd.c -+++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.c +Index: linux-3.2.46/drivers/gpu/drm/exynos/exynos_drm_fimd.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/exynos/exynos_drm_fimd.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/exynos/exynos_drm_fimd.c 2013-07-26 19:26:22.000000000 +0000 @@ -17,6 +17,7 @@ #include #include @@ -6793,7 +6788,7 @@ #include #include -@@ -68,6 +69,7 @@ struct fimd_win_data { +@@ -68,6 +69,7 @@ void __iomem *vaddr; unsigned int buf_offsize; unsigned int line_size; /* bytes */ @@ -6801,7 +6796,7 @@ }; struct fimd_context { -@@ -84,8 +86,10 @@ struct fimd_context { +@@ -84,8 +86,10 @@ unsigned long irq_flags; u32 vidcon0; u32 vidcon1; @@ -6813,7 +6808,7 @@ }; static bool fimd_display_is_connected(struct device *dev) -@@ -97,13 +101,13 @@ static bool fimd_display_is_connected(struct device *dev) +@@ -97,13 +101,13 @@ return true; } @@ -6829,7 +6824,7 @@ } static int fimd_check_timing(struct device *dev, void *timing) -@@ -119,7 +123,7 @@ static int fimd_display_power_on(struct device *dev, int mode) +@@ -119,7 +123,7 @@ { DRM_DEBUG_KMS("%s\n", __FILE__); @@ -6838,7 +6833,7 @@ return 0; } -@@ -127,17 +131,75 @@ static int fimd_display_power_on(struct device *dev, int mode) +@@ -127,17 +131,75 @@ static struct exynos_drm_display_ops fimd_display_ops = { .type = EXYNOS_DISPLAY_TYPE_LCD, .is_connected = fimd_display_is_connected, @@ -6916,7 +6911,7 @@ DRM_DEBUG_KMS("%s\n", __FILE__); /* setup polarity values from machine code. */ -@@ -177,40 +239,6 @@ static void fimd_commit(struct device *dev) +@@ -177,40 +239,6 @@ writel(val, ctx->regs + VIDCON0); } @@ -6957,7 +6952,7 @@ static int fimd_enable_vblank(struct device *dev) { struct fimd_context *ctx = get_fimd_context(dev); -@@ -218,6 +246,9 @@ static int fimd_enable_vblank(struct device *dev) +@@ -218,6 +246,9 @@ DRM_DEBUG_KMS("%s\n", __FILE__); @@ -6967,7 +6962,7 @@ if (!test_and_set_bit(0, &ctx->irq_flags)) { val = readl(ctx->regs + VIDINTCON0); -@@ -242,6 +273,9 @@ static void fimd_disable_vblank(struct device *dev) +@@ -242,6 +273,9 @@ DRM_DEBUG_KMS("%s\n", __FILE__); @@ -6977,7 +6972,7 @@ if (test_and_clear_bit(0, &ctx->irq_flags)) { val = readl(ctx->regs + VIDINTCON0); -@@ -253,8 +287,9 @@ static void fimd_disable_vblank(struct device *dev) +@@ -253,8 +287,9 @@ } static struct exynos_drm_manager_ops fimd_manager_ops = { @@ -6988,7 +6983,7 @@ .enable_vblank = fimd_enable_vblank, .disable_vblank = fimd_disable_vblank, }; -@@ -264,6 +299,7 @@ static void fimd_win_mode_set(struct device *dev, +@@ -264,6 +299,7 @@ { struct fimd_context *ctx = get_fimd_context(dev); struct fimd_win_data *win_data; @@ -6996,7 +6991,7 @@ unsigned long offset; DRM_DEBUG_KMS("%s\n", __FILE__); -@@ -273,12 +309,19 @@ static void fimd_win_mode_set(struct device *dev, +@@ -273,12 +309,19 @@ return; } @@ -7017,7 +7012,7 @@ win_data->offset_x = overlay->crtc_x; win_data->offset_y = overlay->crtc_y; -@@ -286,8 +329,8 @@ static void fimd_win_mode_set(struct device *dev, +@@ -286,8 +329,8 @@ win_data->ovl_height = overlay->crtc_height; win_data->fb_width = overlay->fb_width; win_data->fb_height = overlay->fb_height; @@ -7028,7 +7023,7 @@ win_data->bpp = overlay->bpp; win_data->buf_offsize = (overlay->fb_width - overlay->crtc_width) * (overlay->bpp >> 3); -@@ -381,15 +424,21 @@ static void fimd_win_set_colkey(struct device *dev, unsigned int win) +@@ -381,15 +424,21 @@ writel(keycon1, ctx->regs + WKEYCON1_BASE(win)); } @@ -7052,7 +7047,7 @@ if (win < 0 || win > WINDOWS_NR) return; -@@ -472,24 +521,37 @@ static void fimd_win_commit(struct device *dev) +@@ -472,24 +521,37 @@ if (win != 0) fimd_win_set_colkey(dev, win); @@ -7092,7 +7087,7 @@ /* protect windows */ val = readl(ctx->regs + SHADOWCON); val |= SHADOWCON_WINx_PROTECT(win); -@@ -505,6 +567,8 @@ static void fimd_win_disable(struct device *dev) +@@ -505,6 +567,8 @@ val &= ~SHADOWCON_CHx_ENABLE(win); val &= ~SHADOWCON_WINx_PROTECT(win); writel(val, ctx->regs + SHADOWCON); @@ -7101,7 +7096,7 @@ } static struct exynos_drm_overlay_ops fimd_overlay_ops = { -@@ -513,6 +577,13 @@ static struct exynos_drm_overlay_ops fimd_overlay_ops = { +@@ -513,6 +577,13 @@ .disable = fimd_win_disable, }; @@ -7115,7 +7110,7 @@ static void fimd_finish_pageflip(struct drm_device *drm_dev, int crtc) { struct exynos_drm_private *dev_priv = drm_dev->dev_private; -@@ -540,8 +611,21 @@ static void fimd_finish_pageflip(struct drm_device *drm_dev, int crtc) +@@ -540,8 +611,21 @@ wake_up_interruptible(&e->base.file_priv->event_wait); } @@ -7139,7 +7134,7 @@ spin_unlock_irqrestore(&drm_dev->event_lock, flags); } -@@ -551,7 +635,7 @@ static irqreturn_t fimd_irq_handler(int irq, void *dev_id) +@@ -551,7 +635,7 @@ struct fimd_context *ctx = (struct fimd_context *)dev_id; struct exynos_drm_subdrv *subdrv = &ctx->subdrv; struct drm_device *drm_dev = subdrv->drm_dev; @@ -7148,7 +7143,7 @@ u32 val; val = readl(ctx->regs + VIDINTCON1); -@@ -560,19 +644,14 @@ static irqreturn_t fimd_irq_handler(int irq, void *dev_id) +@@ -560,19 +644,14 @@ /* VSYNC interrupt */ writel(VIDINTCON1_INT_FRAME, ctx->regs + VIDINTCON1); @@ -7172,7 +7167,7 @@ return IRQ_HANDLED; } -@@ -590,6 +669,13 @@ static int fimd_subdrv_probe(struct drm_device *drm_dev, struct device *dev) +@@ -590,6 +669,13 @@ */ drm_dev->irq_enabled = 1; @@ -7186,7 +7181,7 @@ return 0; } -@@ -662,13 +748,53 @@ static void fimd_clear_win(struct fimd_context *ctx, int win) +@@ -662,13 +748,53 @@ writel(val, ctx->regs + SHADOWCON); } @@ -7241,7 +7236,7 @@ struct resource *res; int win; int ret = -EINVAL; -@@ -681,9 +807,9 @@ static int __devinit fimd_probe(struct platform_device *pdev) +@@ -681,9 +807,9 @@ return -EINVAL; } @@ -7254,7 +7249,7 @@ return -EINVAL; } -@@ -698,8 +824,6 @@ static int __devinit fimd_probe(struct platform_device *pdev) +@@ -698,8 +824,6 @@ goto err_clk_get; } @@ -7263,7 +7258,7 @@ ctx->lcd_clk = clk_get(dev, "sclk_fimd"); if (IS_ERR(ctx->lcd_clk)) { dev_err(dev, "failed to get lcd clock\n"); -@@ -707,8 +831,6 @@ static int __devinit fimd_probe(struct platform_device *pdev) +@@ -707,8 +831,6 @@ goto err_bus_clk; } @@ -7272,7 +7267,7 @@ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); if (!res) { dev_err(dev, "failed to find registers\n"); -@@ -739,37 +861,40 @@ static int __devinit fimd_probe(struct platform_device *pdev) +@@ -739,37 +861,40 @@ ctx->irq = res->start; @@ -7328,7 +7323,7 @@ exynos_drm_subdrv_register(subdrv); return 0; -@@ -797,14 +922,25 @@ err_clk_get: +@@ -797,14 +922,25 @@ static int __devexit fimd_remove(struct platform_device *pdev) { @@ -7354,7 +7349,7 @@ clk_put(ctx->lcd_clk); clk_put(ctx->bus_clk); -@@ -818,29 +954,69 @@ static int __devexit fimd_remove(struct platform_device *pdev) +@@ -818,29 +954,69 @@ return 0; } @@ -7373,7 +7368,8 @@ + + if (pm_runtime_suspended(dev)) + return 0; -+ + +-static int __init fimd_init(void) + /* + * do not use pm_runtime_suspend(). if pm_runtime_suspend() is + * called here, an error would be returned by that interface @@ -7383,7 +7379,8 @@ +} + +static int fimd_resume(struct device *dev) -+{ + { +- return platform_driver_register(&fimd_driver); + struct fimd_context *ctx = get_fimd_context(dev); + + /* @@ -7393,16 +7390,16 @@ + */ + if (!pm_runtime_suspended(dev)) + return fimd_power_on(ctx, true); - --static int __init fimd_init(void) ++ + return 0; -+} + } +#endif -+ + +-static void __exit fimd_exit(void) +#ifdef CONFIG_PM_RUNTIME +static int fimd_runtime_suspend(struct device *dev) { -- return platform_driver_register(&fimd_driver); +- platform_driver_unregister(&fimd_driver); + struct fimd_context *ctx = get_fimd_context(dev); + + DRM_DEBUG_KMS("%s\n", __FILE__); @@ -7410,29 +7407,27 @@ + return fimd_power_on(ctx, false); } --static void __exit fimd_exit(void) +-module_init(fimd_init); +-module_exit(fimd_exit); +static int fimd_runtime_resume(struct device *dev) - { -- platform_driver_unregister(&fimd_driver); ++{ + struct fimd_context *ctx = get_fimd_context(dev); + + DRM_DEBUG_KMS("%s\n", __FILE__); + + return fimd_power_on(ctx, true); - } ++} +#endif --module_init(fimd_init); --module_exit(fimd_exit); -+static const struct dev_pm_ops fimd_pm_ops = { -+ SET_SYSTEM_SLEEP_PM_OPS(fimd_suspend, fimd_resume) -+ SET_RUNTIME_PM_OPS(fimd_runtime_suspend, fimd_runtime_resume, NULL) -+}; - -MODULE_AUTHOR("Joonyoung Shim "); -MODULE_AUTHOR("Inki Dae "); -MODULE_DESCRIPTION("Samsung DRM FIMD Driver"); -MODULE_LICENSE("GPL"); ++static const struct dev_pm_ops fimd_pm_ops = { ++ SET_SYSTEM_SLEEP_PM_OPS(fimd_suspend, fimd_resume) ++ SET_RUNTIME_PM_OPS(fimd_runtime_suspend, fimd_runtime_resume, NULL) ++}; ++ +struct platform_driver fimd_driver = { + .probe = fimd_probe, + .remove = __devexit_p(fimd_remove), @@ -7442,10 +7437,10 @@ + .pm = &fimd_pm_ops, + }, +}; -diff --git a/drivers/gpu/drm/exynos/exynos_drm_gem.c b/drivers/gpu/drm/exynos/exynos_drm_gem.c -index aba0fe4..1dffa83 100644 ---- a/drivers/gpu/drm/exynos/exynos_drm_gem.c -+++ b/drivers/gpu/drm/exynos/exynos_drm_gem.c +Index: linux-3.2.46/drivers/gpu/drm/exynos/exynos_drm_gem.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/exynos/exynos_drm_gem.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/exynos/exynos_drm_gem.c 2013-07-26 19:26:22.000000000 +0000 @@ -26,6 +26,7 @@ #include "drmP.h" #include "drm.h" @@ -7454,7 +7449,7 @@ #include #include "exynos_drm_drv.h" -@@ -55,118 +56,413 @@ static unsigned int convert_to_vm_err_msg(int msg) +@@ -55,118 +56,413 @@ return out_msg; } @@ -7918,7 +7913,7 @@ { struct drm_exynos_gem_map_off *args = data; -@@ -185,21 +481,23 @@ int exynos_drm_gem_map_offset_ioctl(struct drm_device *dev, void *data, +@@ -185,21 +481,23 @@ } static int exynos_drm_gem_mmap_buffer(struct file *filp, @@ -7946,7 +7941,7 @@ /* * a buffer contains information to physically continuous memory * allocated by user request or at framebuffer creation. -@@ -210,18 +508,39 @@ static int exynos_drm_gem_mmap_buffer(struct file *filp, +@@ -210,18 +508,39 @@ if (vm_size > buffer->size) return -EINVAL; @@ -7955,21 +7950,19 @@ - * to user space. - */ - pfn = ((unsigned long)exynos_gem_obj->buffer->dma_addr) >> PAGE_SHIFT; -- -- DRM_DEBUG_KMS("pfn = 0x%lx\n", pfn); -- -- if (remap_pfn_range(vma, vma->vm_start, pfn, vm_size, -- vma->vm_page_prot)) { -- DRM_ERROR("failed to remap pfn range.\n"); -- return -EAGAIN; + if (exynos_gem_obj->flags & EXYNOS_BO_NONCONTIG) { + int i = 0; + + if (!buffer->pages) + return -EINVAL; -+ + +- DRM_DEBUG_KMS("pfn = 0x%lx\n", pfn); + vma->vm_flags |= VM_MIXEDMAP; -+ + +- if (remap_pfn_range(vma, vma->vm_start, pfn, vm_size, +- vma->vm_page_prot)) { +- DRM_ERROR("failed to remap pfn range.\n"); +- return -EAGAIN; + do { + ret = vm_insert_page(vma, uaddr, buffer->pages[i++]); + if (ret) { @@ -7998,7 +7991,7 @@ } return 0; -@@ -232,7 +551,7 @@ static const struct file_operations exynos_drm_gem_fops = { +@@ -232,7 +551,7 @@ }; int exynos_drm_gem_mmap_ioctl(struct drm_device *dev, void *data, @@ -8007,7 +8000,7 @@ { struct drm_exynos_gem_mmap *args = data; struct drm_gem_object *obj; -@@ -254,10 +573,8 @@ int exynos_drm_gem_mmap_ioctl(struct drm_device *dev, void *data, +@@ -254,10 +573,8 @@ obj->filp->f_op = &exynos_drm_gem_fops; obj->filp->private_data = obj; @@ -8019,7 +8012,7 @@ drm_gem_object_unreference_unlocked(obj); -@@ -278,32 +595,19 @@ int exynos_drm_gem_init_object(struct drm_gem_object *obj) +@@ -278,32 +595,19 @@ return 0; } @@ -8057,7 +8050,7 @@ DRM_DEBUG_KMS("%s\n", __FILE__); -@@ -314,21 +618,29 @@ int exynos_drm_gem_dumb_create(struct drm_file *file_priv, +@@ -314,21 +618,29 @@ */ args->pitch = args->width * args->bpp >> 3; @@ -8091,7 +8084,7 @@ DRM_DEBUG_KMS("%s\n", __FILE__); -@@ -343,19 +655,46 @@ int exynos_drm_gem_dumb_map_offset(struct drm_file *file_priv, +@@ -343,19 +655,46 @@ obj = drm_gem_object_lookup(dev, file_priv, handle); if (!obj) { DRM_ERROR("failed to lookup gem object.\n"); @@ -8143,7 +8136,7 @@ return 0; } -@@ -363,21 +702,20 @@ int exynos_drm_gem_dumb_map_offset(struct drm_file *file_priv, +@@ -363,21 +702,20 @@ int exynos_drm_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf) { struct drm_gem_object *obj = vma->vm_private_data; @@ -8170,7 +8163,7 @@ mutex_unlock(&dev->struct_mutex); -@@ -402,29 +740,3 @@ int exynos_drm_gem_mmap(struct file *filp, struct vm_area_struct *vma) +@@ -402,29 +740,3 @@ return ret; } @@ -8200,10 +8193,10 @@ -MODULE_AUTHOR("Inki Dae "); -MODULE_DESCRIPTION("Samsung SoC DRM GEM Module"); -MODULE_LICENSE("GPL"); -diff --git a/drivers/gpu/drm/exynos/exynos_drm_gem.h b/drivers/gpu/drm/exynos/exynos_drm_gem.h -index ef87973..4ed8420 100644 ---- a/drivers/gpu/drm/exynos/exynos_drm_gem.h -+++ b/drivers/gpu/drm/exynos/exynos_drm_gem.h +Index: linux-3.2.46/drivers/gpu/drm/exynos/exynos_drm_gem.h +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/exynos/exynos_drm_gem.h 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/exynos/exynos_drm_gem.h 2013-07-26 19:26:22.000000000 +0000 @@ -29,6 +29,8 @@ #define to_exynos_gem_obj(x) container_of(x,\ struct exynos_drm_gem_obj, base) @@ -8229,7 +8222,7 @@ unsigned long size; }; -@@ -55,19 +61,26 @@ struct exynos_drm_gem_buf { +@@ -55,19 +61,26 @@ * by user request or at framebuffer creation. * continuous memory region allocated by user request * or at framebuffer creation. @@ -8261,7 +8254,7 @@ /* * request gem object creation and buffer allocation as the size -@@ -75,15 +88,36 @@ struct exynos_drm_gem_obj *exynos_drm_gem_create(struct drm_device *dev, +@@ -75,15 +88,36 @@ * height and bpp. */ int exynos_drm_gem_create_ioctl(struct drm_device *dev, void *data, @@ -8303,7 +8296,7 @@ /* initialize gem object. */ int exynos_drm_gem_init_object(struct drm_gem_object *obj); -@@ -93,24 +127,13 @@ void exynos_drm_gem_free_object(struct drm_gem_object *gem_obj); +@@ -93,24 +127,13 @@ /* create memory region for drm framebuffer. */ int exynos_drm_gem_dumb_create(struct drm_file *file_priv, @@ -8332,7 +8325,7 @@ /* * destroy memory region allocated. -@@ -118,6 +141,13 @@ int exynos_drm_gem_mmap(struct file *filp, struct vm_area_struct *vma); +@@ -118,6 +141,13 @@ * would be released by drm_gem_handle_delete(). */ int exynos_drm_gem_dumb_destroy(struct drm_file *file_priv, @@ -8347,11 +8340,10 @@ +int exynos_drm_gem_mmap(struct file *filp, struct vm_area_struct *vma); #endif -diff --git a/drivers/gpu/drm/exynos/exynos_drm_hdmi.c b/drivers/gpu/drm/exynos/exynos_drm_hdmi.c -new file mode 100644 -index 0000000..3424463 ---- /dev/null -+++ b/drivers/gpu/drm/exynos/exynos_drm_hdmi.c +Index: linux-3.2.46/drivers/gpu/drm/exynos/exynos_drm_hdmi.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/exynos/exynos_drm_hdmi.c 2013-07-26 19:26:22.000000000 +0000 @@ -0,0 +1,377 @@ +/* + * Copyright (C) 2011 Samsung Electronics Co.Ltd @@ -8730,11 +8722,10 @@ + .pm = &hdmi_pm_ops, + }, +}; -diff --git a/drivers/gpu/drm/exynos/exynos_drm_hdmi.h b/drivers/gpu/drm/exynos/exynos_drm_hdmi.h -new file mode 100644 -index 0000000..f3ae192 ---- /dev/null -+++ b/drivers/gpu/drm/exynos/exynos_drm_hdmi.h +Index: linux-3.2.46/drivers/gpu/drm/exynos/exynos_drm_hdmi.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/exynos/exynos_drm_hdmi.h 2013-07-26 19:26:22.000000000 +0000 @@ -0,0 +1,73 @@ +/* exynos_drm_hdmi.h + * @@ -8809,11 +8800,10 @@ +void exynos_hdmi_ops_register(struct exynos_hdmi_ops *ops); +void exynos_mixer_ops_register(struct exynos_mixer_ops *ops); +#endif -diff --git a/drivers/gpu/drm/exynos/exynos_drm_plane.c b/drivers/gpu/drm/exynos/exynos_drm_plane.c -new file mode 100644 -index 0000000..f92fe4c ---- /dev/null -+++ b/drivers/gpu/drm/exynos/exynos_drm_plane.c +Index: linux-3.2.46/drivers/gpu/drm/exynos/exynos_drm_plane.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/exynos/exynos_drm_plane.c 2013-07-26 19:26:22.000000000 +0000 @@ -0,0 +1,171 @@ +/* + * Copyright (C) 2011 Samsung Electronics Co.Ltd @@ -8986,11 +8976,10 @@ + mutex_unlock(&dev->mode_config.mutex); + return ret; +} -diff --git a/drivers/gpu/drm/exynos/exynos_drm_plane.h b/drivers/gpu/drm/exynos/exynos_drm_plane.h -new file mode 100644 -index 0000000..16b71f8 ---- /dev/null -+++ b/drivers/gpu/drm/exynos/exynos_drm_plane.h +Index: linux-3.2.46/drivers/gpu/drm/exynos/exynos_drm_plane.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/exynos/exynos_drm_plane.h 2013-07-26 19:26:22.000000000 +0000 @@ -0,0 +1,14 @@ +/* + * Copyright (C) 2011 Samsung Electronics Co.Ltd @@ -9006,11 +8995,10 @@ +int exynos_plane_init(struct drm_device *dev, unsigned int nr); +int exynos_plane_set_zpos_ioctl(struct drm_device *dev, void *data, + struct drm_file *file_priv); -diff --git a/drivers/gpu/drm/exynos/exynos_drm_vidi.c b/drivers/gpu/drm/exynos/exynos_drm_vidi.c -new file mode 100644 -index 0000000..7b9c153 ---- /dev/null -+++ b/drivers/gpu/drm/exynos/exynos_drm_vidi.c +Index: linux-3.2.46/drivers/gpu/drm/exynos/exynos_drm_vidi.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/exynos/exynos_drm_vidi.c 2013-07-26 19:26:22.000000000 +0000 @@ -0,0 +1,680 @@ +/* exynos_drm_vidi.c + * @@ -9692,11 +9680,10 @@ + .pm = &vidi_pm_ops, + }, +}; -diff --git a/drivers/gpu/drm/exynos/exynos_drm_vidi.h b/drivers/gpu/drm/exynos/exynos_drm_vidi.h -new file mode 100644 -index 0000000..a4babe4 ---- /dev/null -+++ b/drivers/gpu/drm/exynos/exynos_drm_vidi.h +Index: linux-3.2.46/drivers/gpu/drm/exynos/exynos_drm_vidi.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/exynos/exynos_drm_vidi.h 2013-07-26 19:26:22.000000000 +0000 @@ -0,0 +1,36 @@ +/* exynos_drm_vidi.h + * @@ -9734,11 +9721,10 @@ +#endif + +#endif -diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c b/drivers/gpu/drm/exynos/exynos_hdmi.c -new file mode 100644 -index 0000000..b003538 ---- /dev/null -+++ b/drivers/gpu/drm/exynos/exynos_hdmi.c +Index: linux-3.2.46/drivers/gpu/drm/exynos/exynos_hdmi.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/exynos/exynos_hdmi.c 2013-07-26 19:26:22.000000000 +0000 @@ -0,0 +1,2389 @@ +/* + * Copyright (C) 2011 Samsung Electronics Co.Ltd @@ -12129,11 +12115,10 @@ + .pm = &hdmi_pm_ops, + }, +}; -diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.h b/drivers/gpu/drm/exynos/exynos_hdmi.h -new file mode 100644 -index 0000000..1c3b6d8 ---- /dev/null -+++ b/drivers/gpu/drm/exynos/exynos_hdmi.h +Index: linux-3.2.46/drivers/gpu/drm/exynos/exynos_hdmi.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/exynos/exynos_hdmi.h 2013-07-26 19:26:22.000000000 +0000 @@ -0,0 +1,37 @@ +/* + * @@ -12172,11 +12157,10 @@ +extern struct i2c_driver ddc_driver; + +#endif -diff --git a/drivers/gpu/drm/exynos/exynos_hdmiphy.c b/drivers/gpu/drm/exynos/exynos_hdmiphy.c -new file mode 100644 -index 0000000..9fe2995 ---- /dev/null -+++ b/drivers/gpu/drm/exynos/exynos_hdmiphy.c +Index: linux-3.2.46/drivers/gpu/drm/exynos/exynos_hdmiphy.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/exynos/exynos_hdmiphy.c 2013-07-26 19:26:22.000000000 +0000 @@ -0,0 +1,58 @@ +/* + * Copyright (C) 2011 Samsung Electronics Co.Ltd @@ -12236,11 +12220,10 @@ + .command = NULL, +}; +EXPORT_SYMBOL(hdmiphy_driver); -diff --git a/drivers/gpu/drm/exynos/exynos_mixer.c b/drivers/gpu/drm/exynos/exynos_mixer.c -new file mode 100644 -index 0000000..e15438c ---- /dev/null -+++ b/drivers/gpu/drm/exynos/exynos_mixer.c +Index: linux-3.2.46/drivers/gpu/drm/exynos/exynos_mixer.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/exynos/exynos_mixer.c 2013-07-26 19:26:22.000000000 +0000 @@ -0,0 +1,1112 @@ +/* + * Copyright (C) 2011 Samsung Electronics Co.Ltd @@ -13354,11 +13337,10 @@ + .probe = mixer_probe, + .remove = __devexit_p(mixer_remove), +}; -diff --git a/drivers/gpu/drm/exynos/regs-hdmi.h b/drivers/gpu/drm/exynos/regs-hdmi.h -new file mode 100644 -index 0000000..3c04bea ---- /dev/null -+++ b/drivers/gpu/drm/exynos/regs-hdmi.h +Index: linux-3.2.46/drivers/gpu/drm/exynos/regs-hdmi.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/exynos/regs-hdmi.h 2013-07-26 19:26:22.000000000 +0000 @@ -0,0 +1,561 @@ +/* + * @@ -13921,11 +13903,10 @@ +#define HDMI_TG_3D HDMI_TG_BASE(0x00F0) + +#endif /* SAMSUNG_REGS_HDMI_H */ -diff --git a/drivers/gpu/drm/exynos/regs-mixer.h b/drivers/gpu/drm/exynos/regs-mixer.h -new file mode 100644 -index 0000000..fd2f4d1 ---- /dev/null -+++ b/drivers/gpu/drm/exynos/regs-mixer.h +Index: linux-3.2.46/drivers/gpu/drm/exynos/regs-mixer.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/exynos/regs-mixer.h 2013-07-26 19:26:22.000000000 +0000 @@ -0,0 +1,141 @@ +/* + * @@ -14068,11 +14049,10 @@ + +#endif /* SAMSUNG_REGS_MIXER_H */ + -diff --git a/drivers/gpu/drm/exynos/regs-vp.h b/drivers/gpu/drm/exynos/regs-vp.h -new file mode 100644 -index 0000000..10b737a ---- /dev/null -+++ b/drivers/gpu/drm/exynos/regs-vp.h +Index: linux-3.2.46/drivers/gpu/drm/exynos/regs-vp.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/exynos/regs-vp.h 2013-07-26 19:26:22.000000000 +0000 @@ -0,0 +1,91 @@ +/* + * @@ -14165,11 +14145,10 @@ +#define VP_ENDIAN_MODE_LITTLE (1 << 0) + +#endif /* SAMSUNG_REGS_VP_H */ -diff --git a/drivers/gpu/drm/gma500/Kconfig b/drivers/gpu/drm/gma500/Kconfig -new file mode 100644 -index 0000000..42e665c ---- /dev/null -+++ b/drivers/gpu/drm/gma500/Kconfig +Index: linux-3.2.46/drivers/gpu/drm/gma500/Kconfig +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/gma500/Kconfig 2013-07-26 19:26:22.000000000 +0000 @@ -0,0 +1,33 @@ +config DRM_GMA500 + tristate "Intel GMA5/600 KMS Framebuffer" @@ -14204,11 +14183,10 @@ + help + Say yes to include support for the Intel Medfield platform. + -diff --git a/drivers/gpu/drm/gma500/Makefile b/drivers/gpu/drm/gma500/Makefile -new file mode 100644 -index 0000000..1583982 ---- /dev/null -+++ b/drivers/gpu/drm/gma500/Makefile +Index: linux-3.2.46/drivers/gpu/drm/gma500/Makefile +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/gma500/Makefile 2013-07-26 19:26:22.000000000 +0000 @@ -0,0 +1,50 @@ +# +# KMS driver for the GMA500 @@ -14260,11 +14238,10 @@ + tc35876x-dsi-lvds.o + +obj-$(CONFIG_DRM_GMA500) += gma500_gfx.o -diff --git a/drivers/gpu/drm/gma500/accel_2d.c b/drivers/gpu/drm/gma500/accel_2d.c -new file mode 100644 -index 0000000..d5ef1a5 ---- /dev/null -+++ b/drivers/gpu/drm/gma500/accel_2d.c +Index: linux-3.2.46/drivers/gpu/drm/gma500/accel_2d.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/gma500/accel_2d.c 2013-07-26 19:26:22.000000000 +0000 @@ -0,0 +1,364 @@ +/************************************************************************** + * Copyright (c) 2007-2011, Intel Corporation. @@ -14630,11 +14607,10 @@ + spin_unlock_irqrestore(&dev_priv->lock_2d, flags); + return (busy) ? -EBUSY : 0; +} -diff --git a/drivers/gpu/drm/gma500/backlight.c b/drivers/gpu/drm/gma500/backlight.c -new file mode 100644 -index 0000000..2079395 ---- /dev/null -+++ b/drivers/gpu/drm/gma500/backlight.c +Index: linux-3.2.46/drivers/gpu/drm/gma500/backlight.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/gma500/backlight.c 2013-07-26 19:26:22.000000000 +0000 @@ -0,0 +1,49 @@ +/* + * GMA500 Backlight Interface @@ -14685,11 +14661,10 @@ + } +#endif +} -diff --git a/drivers/gpu/drm/gma500/cdv_device.c b/drivers/gpu/drm/gma500/cdv_device.c -new file mode 100644 -index 0000000..a54cc73 ---- /dev/null -+++ b/drivers/gpu/drm/gma500/cdv_device.c +Index: linux-3.2.46/drivers/gpu/drm/gma500/cdv_device.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/gma500/cdv_device.c 2013-07-26 19:26:22.000000000 +0000 @@ -0,0 +1,484 @@ +/************************************************************************** + * Copyright (c) 2011, Intel Corporation. @@ -15175,11 +15150,10 @@ + .power_down = cdv_power_down, + .power_up = cdv_power_up, +}; -diff --git a/drivers/gpu/drm/gma500/cdv_device.h b/drivers/gpu/drm/gma500/cdv_device.h -new file mode 100644 -index 0000000..9561e17 ---- /dev/null -+++ b/drivers/gpu/drm/gma500/cdv_device.h +Index: linux-3.2.46/drivers/gpu/drm/gma500/cdv_device.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/gma500/cdv_device.h 2013-07-26 19:26:22.000000000 +0000 @@ -0,0 +1,36 @@ +/* + * Copyright © 2011 Intel Corporation @@ -15217,11 +15191,10 @@ +} + + -diff --git a/drivers/gpu/drm/gma500/cdv_intel_crt.c b/drivers/gpu/drm/gma500/cdv_intel_crt.c -new file mode 100644 -index 0000000..a71a6cd ---- /dev/null -+++ b/drivers/gpu/drm/gma500/cdv_intel_crt.c +Index: linux-3.2.46/drivers/gpu/drm/gma500/cdv_intel_crt.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/gma500/cdv_intel_crt.c 2013-07-26 19:26:22.000000000 +0000 @@ -0,0 +1,340 @@ +/* + * Copyright © 2006-2007 Intel Corporation @@ -15563,11 +15536,10 @@ + kfree(psb_intel_encoder); + return; +} -diff --git a/drivers/gpu/drm/gma500/cdv_intel_display.c b/drivers/gpu/drm/gma500/cdv_intel_display.c -new file mode 100644 -index 0000000..be84559 ---- /dev/null -+++ b/drivers/gpu/drm/gma500/cdv_intel_display.c +Index: linux-3.2.46/drivers/gpu/drm/gma500/cdv_intel_display.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/gma500/cdv_intel_display.c 2013-07-26 19:26:22.000000000 +0000 @@ -0,0 +1,1459 @@ +/* + * Copyright © 2006-2011 Intel Corporation @@ -17028,11 +17000,10 @@ + .set_config = cdv_crtc_set_config, + .destroy = cdv_intel_crtc_destroy, +}; -diff --git a/drivers/gpu/drm/gma500/cdv_intel_hdmi.c b/drivers/gpu/drm/gma500/cdv_intel_hdmi.c -new file mode 100644 -index 0000000..8d52695 ---- /dev/null -+++ b/drivers/gpu/drm/gma500/cdv_intel_hdmi.c +Index: linux-3.2.46/drivers/gpu/drm/gma500/cdv_intel_hdmi.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/gma500/cdv_intel_hdmi.c 2013-07-26 19:26:22.000000000 +0000 @@ -0,0 +1,393 @@ +/* + * Copyright © 2006-2011 Intel Corporation @@ -17427,11 +17398,10 @@ +err_connector: + kfree(psb_intel_encoder); +} -diff --git a/drivers/gpu/drm/gma500/cdv_intel_lvds.c b/drivers/gpu/drm/gma500/cdv_intel_lvds.c -new file mode 100644 -index 0000000..8359c1a ---- /dev/null -+++ b/drivers/gpu/drm/gma500/cdv_intel_lvds.c +Index: linux-3.2.46/drivers/gpu/drm/gma500/cdv_intel_lvds.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/gma500/cdv_intel_lvds.c 2013-07-26 19:26:22.000000000 +0000 @@ -0,0 +1,734 @@ +/* + * Copyright © 2006-2011 Intel Corporation @@ -18167,11 +18137,10 @@ +failed_connector: + kfree(psb_intel_encoder); +} -diff --git a/drivers/gpu/drm/gma500/framebuffer.c b/drivers/gpu/drm/gma500/framebuffer.c -new file mode 100644 -index 0000000..8ea202f ---- /dev/null -+++ b/drivers/gpu/drm/gma500/framebuffer.c +Index: linux-3.2.46/drivers/gpu/drm/gma500/framebuffer.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/gma500/framebuffer.c 2013-07-26 19:26:22.000000000 +0000 @@ -0,0 +1,800 @@ +/************************************************************************** + * Copyright (c) 2007-2011, Intel Corporation. @@ -18973,11 +18942,10 @@ + + mutex_unlock(&dev->struct_mutex); +} -diff --git a/drivers/gpu/drm/gma500/framebuffer.h b/drivers/gpu/drm/gma500/framebuffer.h -new file mode 100644 -index 0000000..989558a ---- /dev/null -+++ b/drivers/gpu/drm/gma500/framebuffer.h +Index: linux-3.2.46/drivers/gpu/drm/gma500/framebuffer.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/gma500/framebuffer.h 2013-07-26 19:26:22.000000000 +0000 @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2008-2011, Intel Corporation @@ -19026,11 +18994,10 @@ + +#endif + -diff --git a/drivers/gpu/drm/gma500/gem.c b/drivers/gpu/drm/gma500/gem.c -new file mode 100644 -index 0000000..9fbb868 ---- /dev/null -+++ b/drivers/gpu/drm/gma500/gem.c +Index: linux-3.2.46/drivers/gpu/drm/gma500/gem.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/gma500/gem.c 2013-07-26 19:26:22.000000000 +0000 @@ -0,0 +1,292 @@ +/* + * psb GEM interface @@ -19324,11 +19291,10 @@ + args->handle, &args->offset); +} + -diff --git a/drivers/gpu/drm/gma500/gem_glue.c b/drivers/gpu/drm/gma500/gem_glue.c -new file mode 100644 -index 0000000..3c17634 ---- /dev/null -+++ b/drivers/gpu/drm/gma500/gem_glue.c +Index: linux-3.2.46/drivers/gpu/drm/gma500/gem_glue.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/gma500/gem_glue.c 2013-07-26 19:26:22.000000000 +0000 @@ -0,0 +1,90 @@ +/************************************************************************** + * Copyright (c) 2011, Intel Corporation. @@ -19420,19 +19386,17 @@ + list->map = NULL; + return ret; +} -diff --git a/drivers/gpu/drm/gma500/gem_glue.h b/drivers/gpu/drm/gma500/gem_glue.h -new file mode 100644 -index 0000000..ce5ce30 ---- /dev/null -+++ b/drivers/gpu/drm/gma500/gem_glue.h +Index: linux-3.2.46/drivers/gpu/drm/gma500/gem_glue.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/gma500/gem_glue.h 2013-07-26 19:26:22.000000000 +0000 @@ -0,0 +1,2 @@ +extern void drm_gem_object_release_wrap(struct drm_gem_object *obj); +extern int gem_create_mmap_offset(struct drm_gem_object *obj); -diff --git a/drivers/gpu/drm/gma500/gtt.c b/drivers/gpu/drm/gma500/gtt.c -new file mode 100644 -index 0000000..c6465b4 ---- /dev/null -+++ b/drivers/gpu/drm/gma500/gtt.c +Index: linux-3.2.46/drivers/gpu/drm/gma500/gtt.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/gma500/gtt.c 2013-07-26 19:26:22.000000000 +0000 @@ -0,0 +1,551 @@ +/* + * Copyright (c) 2007, Intel Corporation. @@ -19985,11 +19949,10 @@ + psb_gtt_takedown(dev); + return ret; +} -diff --git a/drivers/gpu/drm/gma500/gtt.h b/drivers/gpu/drm/gma500/gtt.h -new file mode 100644 -index 0000000..aa17423 ---- /dev/null -+++ b/drivers/gpu/drm/gma500/gtt.h +Index: linux-3.2.46/drivers/gpu/drm/gma500/gtt.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/gma500/gtt.h 2013-07-26 19:26:22.000000000 +0000 @@ -0,0 +1,64 @@ +/************************************************************************** + * Copyright (c) 2007-2008, Intel Corporation. @@ -20055,11 +20018,10 @@ + struct gtt_range *gt, int roll); + +#endif -diff --git a/drivers/gpu/drm/gma500/intel_bios.c b/drivers/gpu/drm/gma500/intel_bios.c -new file mode 100644 -index 0000000..d4d0c5b ---- /dev/null -+++ b/drivers/gpu/drm/gma500/intel_bios.c +Index: linux-3.2.46/drivers/gpu/drm/gma500/intel_bios.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/gma500/intel_bios.c 2013-07-26 19:26:22.000000000 +0000 @@ -0,0 +1,303 @@ +/* + * Copyright (c) 2006 Intel Corporation @@ -20364,11 +20326,10 @@ + kfree(lvds_bl); + } +} -diff --git a/drivers/gpu/drm/gma500/intel_bios.h b/drivers/gpu/drm/gma500/intel_bios.h -new file mode 100644 -index 0000000..70f1bf0 ---- /dev/null -+++ b/drivers/gpu/drm/gma500/intel_bios.h +Index: linux-3.2.46/drivers/gpu/drm/gma500/intel_bios.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/gma500/intel_bios.h 2013-07-26 19:26:22.000000000 +0000 @@ -0,0 +1,430 @@ +/* + * Copyright (c) 2006 Intel Corporation @@ -20800,11 +20761,10 @@ +#define SWF14_APM_RESTORE 0x0 + +#endif /* _I830_BIOS_H_ */ -diff --git a/drivers/gpu/drm/gma500/intel_gmbus.c b/drivers/gpu/drm/gma500/intel_gmbus.c -new file mode 100644 -index 0000000..9db9052 ---- /dev/null -+++ b/drivers/gpu/drm/gma500/intel_gmbus.c +Index: linux-3.2.46/drivers/gpu/drm/gma500/intel_gmbus.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/gma500/intel_gmbus.c 2013-07-26 19:26:22.000000000 +0000 @@ -0,0 +1,493 @@ +/* + * Copyright (c) 2006 Dave Airlie @@ -21299,11 +21259,10 @@ + kfree(dev_priv->gmbus); + dev_priv->gmbus = NULL; +} -diff --git a/drivers/gpu/drm/gma500/intel_i2c.c b/drivers/gpu/drm/gma500/intel_i2c.c -new file mode 100644 -index 0000000..98a28c2 ---- /dev/null -+++ b/drivers/gpu/drm/gma500/intel_i2c.c +Index: linux-3.2.46/drivers/gpu/drm/gma500/intel_i2c.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/gma500/intel_i2c.c 2013-07-26 19:26:22.000000000 +0000 @@ -0,0 +1,169 @@ +/* + * Copyright © 2006-2007 Intel Corporation @@ -21474,11 +21433,10 @@ + i2c_del_adapter(&chan->adapter); + kfree(chan); +} -diff --git a/drivers/gpu/drm/gma500/intel_opregion.c b/drivers/gpu/drm/gma500/intel_opregion.c -new file mode 100644 -index 0000000..d946bc1 ---- /dev/null -+++ b/drivers/gpu/drm/gma500/intel_opregion.c +Index: linux-3.2.46/drivers/gpu/drm/gma500/intel_opregion.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/gma500/intel_opregion.c 2013-07-26 19:26:22.000000000 +0000 @@ -0,0 +1,81 @@ +/* + * Copyright 2010 Intel Corporation @@ -21561,11 +21519,10 @@ + iounmap(dev_priv->lid_state); + return 0; +} -diff --git a/drivers/gpu/drm/gma500/mdfld_device.c b/drivers/gpu/drm/gma500/mdfld_device.c -new file mode 100644 -index 0000000..af65678 ---- /dev/null -+++ b/drivers/gpu/drm/gma500/mdfld_device.c +Index: linux-3.2.46/drivers/gpu/drm/gma500/mdfld_device.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/gma500/mdfld_device.c 2013-07-26 19:26:22.000000000 +0000 @@ -0,0 +1,691 @@ +/************************************************************************** + * Copyright (c) 2011, Intel Corporation. @@ -22258,11 +22215,10 @@ + .power_down = mdfld_power_down, + .power_up = mdfld_power_up, +}; -diff --git a/drivers/gpu/drm/gma500/mdfld_dsi_dpi.c b/drivers/gpu/drm/gma500/mdfld_dsi_dpi.c -new file mode 100644 -index 0000000..d52358b ---- /dev/null -+++ b/drivers/gpu/drm/gma500/mdfld_dsi_dpi.c +Index: linux-3.2.46/drivers/gpu/drm/gma500/mdfld_dsi_dpi.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/gma500/mdfld_dsi_dpi.c 2013-07-26 19:26:22.000000000 +0000 @@ -0,0 +1,1017 @@ +/* + * Copyright © 2010 Intel Corporation @@ -23281,11 +23237,10 @@ + + return &dpi_output->base; +} -diff --git a/drivers/gpu/drm/gma500/mdfld_dsi_dpi.h b/drivers/gpu/drm/gma500/mdfld_dsi_dpi.h -new file mode 100644 -index 0000000..6f76247 ---- /dev/null -+++ b/drivers/gpu/drm/gma500/mdfld_dsi_dpi.h +Index: linux-3.2.46/drivers/gpu/drm/gma500/mdfld_dsi_dpi.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/gma500/mdfld_dsi_dpi.h 2013-07-26 19:26:22.000000000 +0000 @@ -0,0 +1,79 @@ +/* + * Copyright © 2010 Intel Corporation @@ -23366,11 +23321,10 @@ +extern void mdfld_dsi_dpi_controller_init(struct mdfld_dsi_config *dsi_config, + int pipe); +#endif /*__MDFLD_DSI_DPI_H__*/ -diff --git a/drivers/gpu/drm/gma500/mdfld_dsi_output.c b/drivers/gpu/drm/gma500/mdfld_dsi_output.c -new file mode 100644 -index 0000000..5675d93 ---- /dev/null -+++ b/drivers/gpu/drm/gma500/mdfld_dsi_output.c +Index: linux-3.2.46/drivers/gpu/drm/gma500/mdfld_dsi_output.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/gma500/mdfld_dsi_output.c 2013-07-26 19:26:22.000000000 +0000 @@ -0,0 +1,621 @@ +/* + * Copyright © 2010 Intel Corporation @@ -23993,11 +23947,10 @@ +dsi_init_err0: + kfree(dsi_connector); +} -diff --git a/drivers/gpu/drm/gma500/mdfld_dsi_output.h b/drivers/gpu/drm/gma500/mdfld_dsi_output.h -new file mode 100644 -index 0000000..36eb074 ---- /dev/null -+++ b/drivers/gpu/drm/gma500/mdfld_dsi_output.h +Index: linux-3.2.46/drivers/gpu/drm/gma500/mdfld_dsi_output.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/gma500/mdfld_dsi_output.h 2013-07-26 19:26:22.000000000 +0000 @@ -0,0 +1,377 @@ +/* + * Copyright © 2010 Intel Corporation @@ -24376,11 +24329,10 @@ +extern int mdfld_dsi_panel_reset(int pipe); + +#endif /*__MDFLD_DSI_OUTPUT_H__*/ -diff --git a/drivers/gpu/drm/gma500/mdfld_dsi_pkg_sender.c b/drivers/gpu/drm/gma500/mdfld_dsi_pkg_sender.c -new file mode 100644 -index 0000000..baa0e14 ---- /dev/null -+++ b/drivers/gpu/drm/gma500/mdfld_dsi_pkg_sender.c +Index: linux-3.2.46/drivers/gpu/drm/gma500/mdfld_dsi_pkg_sender.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/gma500/mdfld_dsi_pkg_sender.c 2013-07-26 19:26:22.000000000 +0000 @@ -0,0 +1,694 @@ +/* + * Copyright © 2010 Intel Corporation @@ -25076,11 +25028,10 @@ +} + + -diff --git a/drivers/gpu/drm/gma500/mdfld_dsi_pkg_sender.h b/drivers/gpu/drm/gma500/mdfld_dsi_pkg_sender.h -new file mode 100644 -index 0000000..459cd7e ---- /dev/null -+++ b/drivers/gpu/drm/gma500/mdfld_dsi_pkg_sender.h +Index: linux-3.2.46/drivers/gpu/drm/gma500/mdfld_dsi_pkg_sender.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/gma500/mdfld_dsi_pkg_sender.h 2013-07-26 19:26:22.000000000 +0000 @@ -0,0 +1,92 @@ +/* + * Copyright © 2010 Intel Corporation @@ -25174,11 +25125,10 @@ + u32 *data, u16 len, bool hs); + +#endif -diff --git a/drivers/gpu/drm/gma500/mdfld_intel_display.c b/drivers/gpu/drm/gma500/mdfld_intel_display.c -new file mode 100644 -index 0000000..a35a292 ---- /dev/null -+++ b/drivers/gpu/drm/gma500/mdfld_intel_display.c +Index: linux-3.2.46/drivers/gpu/drm/gma500/mdfld_intel_display.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/gma500/mdfld_intel_display.c 2013-07-26 19:26:22.000000000 +0000 @@ -0,0 +1,1180 @@ +/* + * Copyright © 2006-2007 Intel Corporation @@ -26360,11 +26310,10 @@ + .commit = psb_intel_crtc_commit, +}; + -diff --git a/drivers/gpu/drm/gma500/mdfld_output.c b/drivers/gpu/drm/gma500/mdfld_output.c -new file mode 100644 -index 0000000..c95966b ---- /dev/null -+++ b/drivers/gpu/drm/gma500/mdfld_output.c +Index: linux-3.2.46/drivers/gpu/drm/gma500/mdfld_output.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/gma500/mdfld_output.c 2013-07-26 19:26:22.000000000 +0000 @@ -0,0 +1,74 @@ +/* + * Copyright (c) 2010 Intel Corporation @@ -26440,11 +26389,10 @@ + return 0; +} + -diff --git a/drivers/gpu/drm/gma500/mdfld_output.h b/drivers/gpu/drm/gma500/mdfld_output.h -new file mode 100644 -index 0000000..ab2b27c ---- /dev/null -+++ b/drivers/gpu/drm/gma500/mdfld_output.h +Index: linux-3.2.46/drivers/gpu/drm/gma500/mdfld_output.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/gma500/mdfld_output.h 2013-07-26 19:26:22.000000000 +0000 @@ -0,0 +1,77 @@ +/* + * Copyright (c) 2010 Intel Corporation @@ -26523,11 +26471,10 @@ +extern void mdfldWaitForPipeEnable(struct drm_device *dev, int pipe); +extern void mdfldWaitForPipeDisable(struct drm_device *dev, int pipe); +#endif -diff --git a/drivers/gpu/drm/gma500/mdfld_tmd_vid.c b/drivers/gpu/drm/gma500/mdfld_tmd_vid.c -new file mode 100644 -index 0000000..dc0c6c3 ---- /dev/null -+++ b/drivers/gpu/drm/gma500/mdfld_tmd_vid.c +Index: linux-3.2.46/drivers/gpu/drm/gma500/mdfld_tmd_vid.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/gma500/mdfld_tmd_vid.c 2013-07-26 19:26:22.000000000 +0000 @@ -0,0 +1,201 @@ +/* + * Copyright © 2010 Intel Corporation @@ -26730,11 +26677,10 @@ + .reset = mdfld_dsi_panel_reset, + .drv_ic_init = mdfld_dsi_tmd_drv_ic_init, +}; -diff --git a/drivers/gpu/drm/gma500/mdfld_tpo_vid.c b/drivers/gpu/drm/gma500/mdfld_tpo_vid.c -new file mode 100644 -index 0000000..d8d4170 ---- /dev/null -+++ b/drivers/gpu/drm/gma500/mdfld_tpo_vid.c +Index: linux-3.2.46/drivers/gpu/drm/gma500/mdfld_tpo_vid.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/gma500/mdfld_tpo_vid.c 2013-07-26 19:26:22.000000000 +0000 @@ -0,0 +1,124 @@ +/* + * Copyright © 2010 Intel Corporation @@ -26860,11 +26806,10 @@ + .get_config_mode = &tpo_vid_get_config_mode, + .get_panel_info = tpo_vid_get_panel_info, +}; -diff --git a/drivers/gpu/drm/gma500/mid_bios.c b/drivers/gpu/drm/gma500/mid_bios.c -new file mode 100644 -index 0000000..5eee9ad ---- /dev/null -+++ b/drivers/gpu/drm/gma500/mid_bios.c +Index: linux-3.2.46/drivers/gpu/drm/gma500/mid_bios.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/gma500/mid_bios.c 2013-07-26 19:26:22.000000000 +0000 @@ -0,0 +1,263 @@ +/************************************************************************** + * Copyright (c) 2011, Intel Corporation. @@ -27129,11 +27074,10 @@ + mid_get_pci_revID(dev_priv); + return 0; +} -diff --git a/drivers/gpu/drm/gma500/mid_bios.h b/drivers/gpu/drm/gma500/mid_bios.h -new file mode 100644 -index 0000000..00e7d56 ---- /dev/null -+++ b/drivers/gpu/drm/gma500/mid_bios.h +Index: linux-3.2.46/drivers/gpu/drm/gma500/mid_bios.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/gma500/mid_bios.h 2013-07-26 19:26:22.000000000 +0000 @@ -0,0 +1,21 @@ +/************************************************************************** + * Copyright (c) 2011, Intel Corporation. @@ -27156,11 +27100,10 @@ + +extern int mid_chip_setup(struct drm_device *dev); + -diff --git a/drivers/gpu/drm/gma500/mmu.c b/drivers/gpu/drm/gma500/mmu.c -new file mode 100644 -index 0000000..49bac41 ---- /dev/null -+++ b/drivers/gpu/drm/gma500/mmu.c +Index: linux-3.2.46/drivers/gpu/drm/gma500/mmu.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/gma500/mmu.c 2013-07-26 19:26:22.000000000 +0000 @@ -0,0 +1,849 @@ +/************************************************************************** + * Copyright (c) 2007, Intel Corporation. @@ -28011,11 +27954,10 @@ + up_read(&pd->driver->sem); + return ret; +} -diff --git a/drivers/gpu/drm/gma500/oaktrail.h b/drivers/gpu/drm/gma500/oaktrail.h -new file mode 100644 -index 0000000..2da1f36 ---- /dev/null -+++ b/drivers/gpu/drm/gma500/oaktrail.h +Index: linux-3.2.46/drivers/gpu/drm/gma500/oaktrail.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/gma500/oaktrail.h 2013-07-26 19:26:22.000000000 +0000 @@ -0,0 +1,252 @@ +/************************************************************************** + * Copyright (c) 2007-2011, Intel Corporation. @@ -28269,11 +28211,10 @@ +extern void oaktrail_hdmi_save(struct drm_device *dev); +extern void oaktrail_hdmi_restore(struct drm_device *dev); +extern void oaktrail_hdmi_init(struct drm_device *dev, struct psb_intel_mode_device *mode_dev); -diff --git a/drivers/gpu/drm/gma500/oaktrail_crtc.c b/drivers/gpu/drm/gma500/oaktrail_crtc.c -new file mode 100644 -index 0000000..a39b0d0 ---- /dev/null -+++ b/drivers/gpu/drm/gma500/oaktrail_crtc.c +Index: linux-3.2.46/drivers/gpu/drm/gma500/oaktrail_crtc.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/gma500/oaktrail_crtc.c 2013-07-26 19:26:22.000000000 +0000 @@ -0,0 +1,592 @@ +/* + * Copyright © 2009 Intel Corporation @@ -28867,11 +28808,10 @@ + .commit = oaktrail_crtc_commit, +}; + -diff --git a/drivers/gpu/drm/gma500/oaktrail_device.c b/drivers/gpu/drm/gma500/oaktrail_device.c -new file mode 100644 -index 0000000..41d1924 ---- /dev/null -+++ b/drivers/gpu/drm/gma500/oaktrail_device.c +Index: linux-3.2.46/drivers/gpu/drm/gma500/oaktrail_device.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/gma500/oaktrail_device.c 2013-07-26 19:26:22.000000000 +0000 @@ -0,0 +1,509 @@ +/************************************************************************** + * Copyright (c) 2011, Intel Corporation. @@ -29382,11 +29322,10 @@ + + .i2c_bus = 1, +}; -diff --git a/drivers/gpu/drm/gma500/oaktrail_hdmi.c b/drivers/gpu/drm/gma500/oaktrail_hdmi.c -new file mode 100644 -index 0000000..f8b367b ---- /dev/null -+++ b/drivers/gpu/drm/gma500/oaktrail_hdmi.c +Index: linux-3.2.46/drivers/gpu/drm/gma500/oaktrail_hdmi.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/gma500/oaktrail_hdmi.c 2013-07-26 19:26:22.000000000 +0000 @@ -0,0 +1,540 @@ +/* + * Copyright © 2010 Intel Corporation @@ -29928,11 +29867,10 @@ + for (i = 0; i < 256; i++) + PSB_WVDC32(regs->save_palette_b[i], PALETTE_B + (i << 2)); +} -diff --git a/drivers/gpu/drm/gma500/oaktrail_hdmi_i2c.c b/drivers/gpu/drm/gma500/oaktrail_hdmi_i2c.c -new file mode 100644 -index 0000000..5e84fbd ---- /dev/null -+++ b/drivers/gpu/drm/gma500/oaktrail_hdmi_i2c.c +Index: linux-3.2.46/drivers/gpu/drm/gma500/oaktrail_hdmi_i2c.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/gma500/oaktrail_hdmi_i2c.c 2013-07-26 19:26:22.000000000 +0000 @@ -0,0 +1,328 @@ +/* + * Copyright © 2010 Intel Corporation @@ -30262,11 +30200,10 @@ + kfree(i2c_dev); + free_irq(dev->irq, hdmi_dev); +} -diff --git a/drivers/gpu/drm/gma500/oaktrail_lvds.c b/drivers/gpu/drm/gma500/oaktrail_lvds.c -new file mode 100644 -index 0000000..654f32b ---- /dev/null -+++ b/drivers/gpu/drm/gma500/oaktrail_lvds.c +Index: linux-3.2.46/drivers/gpu/drm/gma500/oaktrail_lvds.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/gma500/oaktrail_lvds.c 2013-07-26 19:26:22.000000000 +0000 @@ -0,0 +1,448 @@ +/* + * Copyright © 2006-2009 Intel Corporation @@ -30716,11 +30653,10 @@ + kfree(psb_intel_encoder); +} + -diff --git a/drivers/gpu/drm/gma500/power.c b/drivers/gpu/drm/gma500/power.c -new file mode 100644 -index 0000000..889b854 ---- /dev/null -+++ b/drivers/gpu/drm/gma500/power.c +Index: linux-3.2.46/drivers/gpu/drm/gma500/power.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/gma500/power.c 2013-07-26 19:26:22.000000000 +0000 @@ -0,0 +1,315 @@ +/************************************************************************** + * Copyright (c) 2009-2011, Intel Corporation. @@ -31037,11 +30973,10 @@ + else + return 1; +} -diff --git a/drivers/gpu/drm/gma500/power.h b/drivers/gpu/drm/gma500/power.h -new file mode 100644 -index 0000000..1969d2e ---- /dev/null -+++ b/drivers/gpu/drm/gma500/power.h +Index: linux-3.2.46/drivers/gpu/drm/gma500/power.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/gma500/power.h 2013-07-26 19:26:22.000000000 +0000 @@ -0,0 +1,67 @@ +/************************************************************************** + * Copyright (c) 2009-2011, Intel Corporation. @@ -31110,11 +31045,10 @@ +int psb_runtime_idle(struct device *dev); + +#endif /*_PSB_POWERMGMT_H_*/ -diff --git a/drivers/gpu/drm/gma500/psb_device.c b/drivers/gpu/drm/gma500/psb_device.c -new file mode 100644 -index 0000000..328a193 ---- /dev/null -+++ b/drivers/gpu/drm/gma500/psb_device.c +Index: linux-3.2.46/drivers/gpu/drm/gma500/psb_device.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/gma500/psb_device.c 2013-07-26 19:26:22.000000000 +0000 @@ -0,0 +1,332 @@ +/************************************************************************** + * Copyright (c) 2011, Intel Corporation. @@ -31448,11 +31382,10 @@ + .power_up = psb_power_up, +}; + -diff --git a/drivers/gpu/drm/gma500/psb_drv.c b/drivers/gpu/drm/gma500/psb_drv.c -new file mode 100644 -index 0000000..09af2ff ---- /dev/null -+++ b/drivers/gpu/drm/gma500/psb_drv.c +Index: linux-3.2.46/drivers/gpu/drm/gma500/psb_drv.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/gma500/psb_drv.c 2013-07-26 19:26:22.000000000 +0000 @@ -0,0 +1,706 @@ +/************************************************************************** + * Copyright (c) 2007-2011, Intel Corporation. @@ -32160,11 +32093,10 @@ +MODULE_AUTHOR("Alan Cox and others"); +MODULE_DESCRIPTION(DRIVER_DESC); +MODULE_LICENSE("GPL"); -diff --git a/drivers/gpu/drm/gma500/psb_drv.h b/drivers/gpu/drm/gma500/psb_drv.h -new file mode 100644 -index 0000000..40ce2c9 ---- /dev/null -+++ b/drivers/gpu/drm/gma500/psb_drv.h +Index: linux-3.2.46/drivers/gpu/drm/gma500/psb_drv.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/gma500/psb_drv.h 2013-07-26 19:26:22.000000000 +0000 @@ -0,0 +1,993 @@ +/************************************************************************** + * Copyright (c) 2007-2011, Intel Corporation. @@ -33159,11 +33091,10 @@ +#define PSB_RMSVDX32(_offs) ioread32(dev_priv->msvdx_reg + (_offs)) + +#endif -diff --git a/drivers/gpu/drm/gma500/psb_intel_display.c b/drivers/gpu/drm/gma500/psb_intel_display.c -new file mode 100644 -index 0000000..2616558 ---- /dev/null -+++ b/drivers/gpu/drm/gma500/psb_intel_display.c +Index: linux-3.2.46/drivers/gpu/drm/gma500/psb_intel_display.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/gma500/psb_intel_display.c 2013-07-26 19:26:22.000000000 +0000 @@ -0,0 +1,1436 @@ +/* + * Copyright © 2006-2011 Intel Corporation @@ -34601,11 +34532,10 @@ + drm_mode_connector_attach_encoder(&connector->base, + &encoder->base); +} -diff --git a/drivers/gpu/drm/gma500/psb_intel_display.h b/drivers/gpu/drm/gma500/psb_intel_display.h -new file mode 100644 -index 0000000..535b49a ---- /dev/null -+++ b/drivers/gpu/drm/gma500/psb_intel_display.h +Index: linux-3.2.46/drivers/gpu/drm/gma500/psb_intel_display.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/gma500/psb_intel_display.h 2013-07-26 19:26:22.000000000 +0000 @@ -0,0 +1,28 @@ +/* copyright (c) 2008, Intel Corporation + * @@ -34635,11 +34565,10 @@ +void psb_intel_crtc_destroy(struct drm_crtc *crtc); + +#endif -diff --git a/drivers/gpu/drm/gma500/psb_intel_drv.h b/drivers/gpu/drm/gma500/psb_intel_drv.h -new file mode 100644 -index 0000000..f40535e ---- /dev/null -+++ b/drivers/gpu/drm/gma500/psb_intel_drv.h +Index: linux-3.2.46/drivers/gpu/drm/gma500/psb_intel_drv.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/gma500/psb_intel_drv.h 2013-07-26 19:26:22.000000000 +0000 @@ -0,0 +1,289 @@ +/* + * Copyright (c) 2009-2011, Intel Corporation. @@ -34930,11 +34859,10 @@ +extern void gma_intel_teardown_gmbus(struct drm_device *dev); + +#endif /* __INTEL_DRV_H__ */ -diff --git a/drivers/gpu/drm/gma500/psb_intel_lvds.c b/drivers/gpu/drm/gma500/psb_intel_lvds.c -new file mode 100644 -index 0000000..c83f5b5 ---- /dev/null -+++ b/drivers/gpu/drm/gma500/psb_intel_lvds.c +Index: linux-3.2.46/drivers/gpu/drm/gma500/psb_intel_lvds.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/gma500/psb_intel_lvds.c 2013-07-26 19:26:22.000000000 +0000 @@ -0,0 +1,867 @@ +/* + * Copyright © 2006-2007 Intel Corporation @@ -35803,11 +35731,10 @@ + kfree(psb_intel_encoder); +} + -diff --git a/drivers/gpu/drm/gma500/psb_intel_modes.c b/drivers/gpu/drm/gma500/psb_intel_modes.c -new file mode 100644 -index 0000000..4fca0d6 ---- /dev/null -+++ b/drivers/gpu/drm/gma500/psb_intel_modes.c +Index: linux-3.2.46/drivers/gpu/drm/gma500/psb_intel_modes.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/gma500/psb_intel_modes.c 2013-07-26 19:26:22.000000000 +0000 @@ -0,0 +1,75 @@ +/* + * Copyright (c) 2007 Intel Corporation @@ -35884,11 +35811,10 @@ + } + return ret; +} -diff --git a/drivers/gpu/drm/gma500/psb_intel_reg.h b/drivers/gpu/drm/gma500/psb_intel_reg.h -new file mode 100644 -index 0000000..e89d3a2 ---- /dev/null -+++ b/drivers/gpu/drm/gma500/psb_intel_reg.h +Index: linux-3.2.46/drivers/gpu/drm/gma500/psb_intel_reg.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/gma500/psb_intel_reg.h 2013-07-26 19:26:22.000000000 +0000 @@ -0,0 +1,1318 @@ +/* + * Copyright (c) 2009, Intel Corporation. @@ -37208,11 +37134,10 @@ + + +#endif -diff --git a/drivers/gpu/drm/gma500/psb_intel_sdvo.c b/drivers/gpu/drm/gma500/psb_intel_sdvo.c -new file mode 100644 -index 0000000..36330ca ---- /dev/null -+++ b/drivers/gpu/drm/gma500/psb_intel_sdvo.c +Index: linux-3.2.46/drivers/gpu/drm/gma500/psb_intel_sdvo.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/gma500/psb_intel_sdvo.c 2013-07-26 19:26:22.000000000 +0000 @@ -0,0 +1,2607 @@ +/* + * Copyright 2006 Dave Airlie @@ -39821,11 +39746,10 @@ + + return false; +} -diff --git a/drivers/gpu/drm/gma500/psb_intel_sdvo_regs.h b/drivers/gpu/drm/gma500/psb_intel_sdvo_regs.h -new file mode 100644 -index 0000000..600e797 ---- /dev/null -+++ b/drivers/gpu/drm/gma500/psb_intel_sdvo_regs.h +Index: linux-3.2.46/drivers/gpu/drm/gma500/psb_intel_sdvo_regs.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/gma500/psb_intel_sdvo_regs.h 2013-07-26 19:26:22.000000000 +0000 @@ -0,0 +1,723 @@ +/* + * Copyright ? 2006-2007 Intel Corporation @@ -40550,11 +40474,10 @@ + u8 dvi_rev; + u8 hdmi_rev; +} __attribute__ ((packed)); -diff --git a/drivers/gpu/drm/gma500/psb_irq.c b/drivers/gpu/drm/gma500/psb_irq.c -new file mode 100644 -index 0000000..1869586 ---- /dev/null -+++ b/drivers/gpu/drm/gma500/psb_irq.c +Index: linux-3.2.46/drivers/gpu/drm/gma500/psb_irq.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/gma500/psb_irq.c 2013-07-26 19:26:22.000000000 +0000 @@ -0,0 +1,622 @@ +/************************************************************************** + * Copyright (c) 2007, Intel Corporation. @@ -41178,11 +41101,10 @@ + return count; +} + -diff --git a/drivers/gpu/drm/gma500/psb_irq.h b/drivers/gpu/drm/gma500/psb_irq.h -new file mode 100644 -index 0000000..603045b ---- /dev/null -+++ b/drivers/gpu/drm/gma500/psb_irq.h +Index: linux-3.2.46/drivers/gpu/drm/gma500/psb_irq.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/gma500/psb_irq.h 2013-07-26 19:26:22.000000000 +0000 @@ -0,0 +1,47 @@ +/************************************************************************** + * Copyright (c) 2009-2011, Intel Corporation. @@ -41231,11 +41153,10 @@ +int mdfld_enable_te(struct drm_device *dev, int pipe); +void mdfld_disable_te(struct drm_device *dev, int pipe); +#endif /* _SYSIRQ_H_ */ -diff --git a/drivers/gpu/drm/gma500/psb_lid.c b/drivers/gpu/drm/gma500/psb_lid.c -new file mode 100644 -index 0000000..b867aabe ---- /dev/null -+++ b/drivers/gpu/drm/gma500/psb_lid.c +Index: linux-3.2.46/drivers/gpu/drm/gma500/psb_lid.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/gma500/psb_lid.c 2013-07-26 19:26:22.000000000 +0000 @@ -0,0 +1,88 @@ +/************************************************************************** + * Copyright (c) 2007, Intel Corporation. @@ -41325,11 +41246,10 @@ + del_timer_sync(&dev_priv->lid_timer); +} + -diff --git a/drivers/gpu/drm/gma500/psb_reg.h b/drivers/gpu/drm/gma500/psb_reg.h -new file mode 100644 -index 0000000..b81c7c1 ---- /dev/null -+++ b/drivers/gpu/drm/gma500/psb_reg.h +Index: linux-3.2.46/drivers/gpu/drm/gma500/psb_reg.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/gma500/psb_reg.h 2013-07-26 19:26:22.000000000 +0000 @@ -0,0 +1,582 @@ +/************************************************************************** + * @@ -41913,11 +41833,10 @@ +#define MDFLD_PWRGT_DISPLAY_STS_A0 (MDFLD_PWRGT_DISPLAY_A_STS | MDFLD_PWRGT_DISPLAY_B_STS | MDFLD_PWRGT_DISPLAY_C_STS | MDFLD_PWRGT_DISP_MIPI_STS) /* 0x000fc00c */ +#define MDFLD_PWRGT_DISPLAY_STS_B0 (MDFLD_PWRGT_DISPLAY_A_STS_B0 | MDFLD_PWRGT_DISPLAY_B_STS_B0 | MDFLD_PWRGT_DISPLAY_C_STS_B0 | MDFLD_PWRGT_DISP_MIPI_STS) /* 0x000fc00c */ +#endif -diff --git a/drivers/gpu/drm/gma500/tc35876x-dsi-lvds.c b/drivers/gpu/drm/gma500/tc35876x-dsi-lvds.c -new file mode 100644 -index 0000000..4a07ab5 ---- /dev/null -+++ b/drivers/gpu/drm/gma500/tc35876x-dsi-lvds.c +Index: linux-3.2.46/drivers/gpu/drm/gma500/tc35876x-dsi-lvds.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/gma500/tc35876x-dsi-lvds.c 2013-07-26 19:26:22.000000000 +0000 @@ -0,0 +1,829 @@ +/* + * Copyright © 2011 Intel Corporation @@ -42748,11 +42667,10 @@ + if (cmi_lcd_i2c_client) + i2c_del_driver(&cmi_lcd_i2c_driver); +} -diff --git a/drivers/gpu/drm/gma500/tc35876x-dsi-lvds.h b/drivers/gpu/drm/gma500/tc35876x-dsi-lvds.h -new file mode 100644 -index 0000000..b14b7f9 ---- /dev/null -+++ b/drivers/gpu/drm/gma500/tc35876x-dsi-lvds.h +Index: linux-3.2.46/drivers/gpu/drm/gma500/tc35876x-dsi-lvds.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/gma500/tc35876x-dsi-lvds.h 2013-07-26 19:26:22.000000000 +0000 @@ -0,0 +1,38 @@ +/* + * Copyright © 2011 Intel Corporation @@ -42792,11 +42710,11 @@ +extern const struct panel_funcs mdfld_tc35876x_funcs; + +#endif /*__MDFLD_DSI_LVDS_BRIDGE_H__*/ -diff --git a/drivers/gpu/drm/i2c/ch7006_drv.c b/drivers/gpu/drm/i2c/ch7006_drv.c -index 07d55df..d3f2e87 100644 ---- a/drivers/gpu/drm/i2c/ch7006_drv.c -+++ b/drivers/gpu/drm/i2c/ch7006_drv.c -@@ -252,10 +252,7 @@ static int ch7006_encoder_create_resources(struct drm_encoder *encoder, +Index: linux-3.2.46/drivers/gpu/drm/i2c/ch7006_drv.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/i2c/ch7006_drv.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/i2c/ch7006_drv.c 2013-07-26 19:26:22.000000000 +0000 +@@ -252,10 +252,7 @@ drm_mode_create_tv_properties(dev, NUM_TV_NORMS, ch7006_tv_norm_names); @@ -42808,11 +42726,11 @@ drm_connector_attach_property(connector, conf->tv_select_subconnector_property, priv->select_subconnector); -diff --git a/drivers/gpu/drm/i810/i810_dma.c b/drivers/gpu/drm/i810/i810_dma.c -index 8f371e8..f920fb5 100644 ---- a/drivers/gpu/drm/i810/i810_dma.c -+++ b/drivers/gpu/drm/i810/i810_dma.c -@@ -99,7 +99,6 @@ static int i810_mmap_buffers(struct file *filp, struct vm_area_struct *vma) +Index: linux-3.2.46/drivers/gpu/drm/i810/i810_dma.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/i810/i810_dma.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/i810/i810_dma.c 2013-07-26 19:26:22.000000000 +0000 +@@ -99,7 +99,6 @@ buf_priv = buf->dev_private; vma->vm_flags |= (VM_IO | VM_DONTCOPY); @@ -42820,7 +42738,7 @@ buf_priv->currently_mapped = I810_BUF_MAPPED; -@@ -130,6 +129,7 @@ static int i810_map_buffer(struct drm_buf *buf, struct drm_file *file_priv) +@@ -130,6 +129,7 @@ if (buf_priv->currently_mapped == I810_BUF_MAPPED) return -EINVAL; @@ -42828,7 +42746,7 @@ down_write(¤t->mm->mmap_sem); old_fops = file_priv->filp->f_op; file_priv->filp->f_op = &i810_buffer_fops; -@@ -158,11 +158,8 @@ static int i810_unmap_buffer(struct drm_buf *buf) +@@ -158,11 +158,8 @@ if (buf_priv->currently_mapped != I810_BUF_MAPPED) return -EINVAL; @@ -42841,7 +42759,7 @@ buf_priv->currently_mapped = I810_BUF_UNMAPPED; buf_priv->virtual = NULL; -@@ -222,8 +219,6 @@ static int i810_dma_cleanup(struct drm_device *dev) +@@ -222,8 +219,6 @@ pci_free_consistent(dev->pdev, PAGE_SIZE, dev_priv->hw_status_page, dev_priv->dma_status_page); @@ -42850,7 +42768,7 @@ } kfree(dev->dev_private); dev->dev_private = NULL; -@@ -1210,6 +1205,8 @@ int i810_driver_load(struct drm_device *dev, unsigned long flags) +@@ -1210,6 +1205,8 @@ dev->types[8] = _DRM_STAT_SECONDARY; dev->types[9] = _DRM_STAT_DMA; @@ -42859,11 +42777,11 @@ return 0; } -diff --git a/drivers/gpu/drm/i810/i810_drv.c b/drivers/gpu/drm/i810/i810_drv.c -index d4266bd..ec12f7d 100644 ---- a/drivers/gpu/drm/i810/i810_drv.c -+++ b/drivers/gpu/drm/i810/i810_drv.c -@@ -43,6 +43,17 @@ static struct pci_device_id pciidlist[] = { +Index: linux-3.2.46/drivers/gpu/drm/i810/i810_drv.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/i810/i810_drv.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/i810/i810_drv.c 2013-07-26 19:26:22.000000000 +0000 +@@ -43,6 +43,17 @@ i810_PCI_IDS }; @@ -42881,7 +42799,7 @@ static struct drm_driver driver = { .driver_features = DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | DRIVER_USE_MTRR | -@@ -55,17 +66,7 @@ static struct drm_driver driver = { +@@ -55,17 +66,7 @@ .reclaim_buffers_locked = i810_driver_reclaim_buffers_locked, .dma_quiescent = i810_driver_dma_quiescent, .ioctls = i810_ioctls, @@ -42900,10 +42818,10 @@ .name = DRIVER_NAME, .desc = DRIVER_DESC, .date = DRIVER_DATE, -diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile -index 0ae6a7c..ce7fc77 100644 ---- a/drivers/gpu/drm/i915/Makefile -+++ b/drivers/gpu/drm/i915/Makefile +Index: linux-3.2.46/drivers/gpu/drm/i915/Makefile +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/i915/Makefile 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/i915/Makefile 2013-07-26 19:26:22.000000000 +0000 @@ -3,7 +3,7 @@ # Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher. @@ -42913,7 +42831,7 @@ i915_debugfs.o \ i915_suspend.o \ i915_gem.o \ -@@ -28,6 +28,7 @@ i915-y := i915_drv.o i915_dma.o i915_irq.o i915_mem.o \ +@@ -28,6 +28,7 @@ intel_dvo.o \ intel_ringbuffer.o \ intel_overlay.o \ @@ -42921,10 +42839,10 @@ intel_opregion.o \ dvo_ch7xxx.o \ dvo_ch7017.o \ -diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c -index 9b4e5c6..34791fb 100644 ---- a/drivers/gpu/drm/i915/i915_debugfs.c -+++ b/drivers/gpu/drm/i915/i915_debugfs.c +Index: linux-3.2.46/drivers/gpu/drm/i915/i915_debugfs.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/i915/i915_debugfs.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/i915/i915_debugfs.c 2013-07-26 19:26:22.000000000 +0000 @@ -30,7 +30,6 @@ #include #include @@ -42933,7 +42851,7 @@ #include "drmP.h" #include "drm.h" #include "intel_drv.h" -@@ -84,6 +83,7 @@ static int i915_capabilities(struct seq_file *m, void *data) +@@ -84,6 +83,7 @@ B(supports_tv); B(has_bsd_ring); B(has_blt_ring); @@ -42941,7 +42859,7 @@ #undef B return 0; -@@ -122,11 +122,11 @@ static const char *cache_level_str(int type) +@@ -122,11 +122,11 @@ static void describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj) { @@ -42955,7 +42873,7 @@ obj->base.read_domains, obj->base.write_domain, obj->last_rendering_seqno, -@@ -340,7 +340,7 @@ static int i915_gem_pageflip_info(struct seq_file *m, void *data) +@@ -340,7 +340,7 @@ seq_printf(m, "No flip due on pipe %c (plane %c)\n", pipe, plane); } else { @@ -42964,7 +42882,7 @@ seq_printf(m, "Flip queued on pipe %c (plane %c)\n", pipe, plane); } else { -@@ -351,7 +351,7 @@ static int i915_gem_pageflip_info(struct seq_file *m, void *data) +@@ -351,7 +351,7 @@ seq_printf(m, "Stall check enabled, "); else seq_printf(m, "Stall check waiting for page flip ioctl, "); @@ -42973,7 +42891,7 @@ if (work->old_fb_obj) { struct drm_i915_gem_object *obj = work->old_fb_obj; -@@ -564,45 +564,6 @@ static int i915_hws_info(struct seq_file *m, void *data) +@@ -564,45 +564,6 @@ return 0; } @@ -43019,7 +42937,7 @@ static int i915_ringbuffer_data(struct seq_file *m, void *data) { struct drm_info_node *node = (struct drm_info_node *) m->private; -@@ -654,7 +615,7 @@ static int i915_ringbuffer_info(struct seq_file *m, void *data) +@@ -654,7 +615,7 @@ seq_printf(m, " Size : %08x\n", ring->size); seq_printf(m, " Active : %08x\n", intel_ring_get_active_head(ring)); seq_printf(m, " NOPID : %08x\n", I915_READ_NOPID(ring)); @@ -43028,7 +42946,7 @@ seq_printf(m, " Sync 0 : %08x\n", I915_READ_SYNC_0(ring)); seq_printf(m, " Sync 1 : %08x\n", I915_READ_SYNC_1(ring)); } -@@ -669,9 +630,9 @@ static int i915_ringbuffer_info(struct seq_file *m, void *data) +@@ -669,9 +630,9 @@ static const char *ring_str(int ring) { switch (ring) { @@ -43041,7 +42959,7 @@ default: return ""; } } -@@ -714,7 +675,7 @@ static void print_error_buffers(struct seq_file *m, +@@ -714,7 +675,7 @@ seq_printf(m, "%s [%d]:\n", name, count); while (count--) { @@ -43050,7 +42968,7 @@ err->gtt_offset, err->size, err->read_domains, -@@ -724,6 +685,7 @@ static void print_error_buffers(struct seq_file *m, +@@ -724,6 +685,7 @@ tiling_flag(err->tiling), dirty_flag(err->dirty), purgeable_flag(err->purgeable), @@ -43058,7 +42976,7 @@ ring_str(err->ring), cache_level_str(err->cache_level)); -@@ -737,6 +699,38 @@ static void print_error_buffers(struct seq_file *m, +@@ -737,6 +699,38 @@ } } @@ -43097,7 +43015,7 @@ static int i915_error_state(struct seq_file *m, void *unused) { struct drm_info_node *node = (struct drm_info_node *) m->private; -@@ -744,7 +738,7 @@ static int i915_error_state(struct seq_file *m, void *unused) +@@ -744,7 +738,7 @@ drm_i915_private_t *dev_priv = dev->dev_private; struct drm_i915_error_state *error; unsigned long flags; @@ -43106,7 +43024,7 @@ spin_lock_irqsave(&dev_priv->error_lock, flags); if (!dev_priv->first_error) { -@@ -756,39 +750,23 @@ static int i915_error_state(struct seq_file *m, void *unused) +@@ -756,39 +750,23 @@ seq_printf(m, "Time: %ld s %ld us\n", error->time.tv_sec, error->time.tv_usec); @@ -43132,8 +43050,7 @@ - seq_printf(m, " IPEHR: 0x%08x\n", error->vcs_ipehr); - seq_printf(m, " INSTDONE: 0x%08x\n", error->vcs_instdone); - seq_printf(m, " seqno: 0x%08x\n", error->vcs_seqno); -+ seq_printf(m, "DONE_REG: 0x%08x\n", error->done_reg); - } +- } - seq_printf(m, "Render command stream:\n"); - seq_printf(m, " ACTHD: 0x%08x\n", error->acthd); - seq_printf(m, " IPEIR: 0x%08x\n", error->ipeir); @@ -43142,7 +43059,8 @@ - if (INTEL_INFO(dev)->gen >= 4) { - seq_printf(m, " INSTDONE1: 0x%08x\n", error->instdone1); - seq_printf(m, " INSTPS: 0x%08x\n", error->instps); -- } ++ seq_printf(m, "DONE_REG: 0x%08x\n", error->done_reg); + } - seq_printf(m, " INSTPM: 0x%08x\n", error->instpm); - seq_printf(m, " seqno: 0x%08x\n", error->seqno); @@ -43156,7 +43074,7 @@ if (error->active_bo) print_error_buffers(m, "Active", -@@ -800,10 +778,10 @@ static int i915_error_state(struct seq_file *m, void *unused) +@@ -800,10 +778,10 @@ error->pinned_bo, error->pinned_bo_count); @@ -43170,7 +43088,7 @@ seq_printf(m, "%s --- gtt_offset = 0x%08x\n", dev_priv->ring[i].name, obj->gtt_offset); -@@ -815,11 +793,20 @@ static int i915_error_state(struct seq_file *m, void *unused) +@@ -815,11 +793,20 @@ } } } @@ -43195,7 +43113,7 @@ seq_printf(m, "%s --- ringbuffer = 0x%08x\n", dev_priv->ring[i].name, obj->gtt_offset); -@@ -1003,7 +990,7 @@ static int i915_inttoext_table(struct seq_file *m, void *unused) +@@ -1003,7 +990,7 @@ return 0; } @@ -43204,7 +43122,7 @@ { struct drm_info_node *node = (struct drm_info_node *) m->private; struct drm_device *dev = node->minor->dev; -@@ -1070,6 +1057,95 @@ static int i915_drpc_info(struct seq_file *m, void *unused) +@@ -1070,6 +1057,95 @@ return 0; } @@ -43300,7 +43218,7 @@ static int i915_fbc_status(struct seq_file *m, void *unused) { struct drm_info_node *node = (struct drm_info_node *) m->private; -@@ -1148,6 +1224,9 @@ static int i915_emon_status(struct seq_file *m, void *unused) +@@ -1148,6 +1224,9 @@ unsigned long temp, chipset, gfx; int ret; @@ -43310,7 +43228,7 @@ ret = mutex_lock_interruptible(&dev->struct_mutex); if (ret) return ret; -@@ -1327,11 +1406,102 @@ static int i915_gen6_forcewake_count_info(struct seq_file *m, void *data) +@@ -1327,11 +1406,102 @@ return 0; } @@ -43417,7 +43335,7 @@ return 0; } -@@ -1385,20 +1555,12 @@ i915_wedged_write(struct file *filp, +@@ -1385,20 +1555,12 @@ static const struct file_operations i915_wedged_fops = { .owner = THIS_MODULE, @@ -43439,7 +43357,7 @@ static ssize_t i915_max_freq_read(struct file *filp, char __user *ubuf, -@@ -1455,20 +1617,12 @@ i915_max_freq_write(struct file *filp, +@@ -1455,20 +1617,12 @@ static const struct file_operations i915_max_freq_fops = { .owner = THIS_MODULE, @@ -43461,7 +43379,7 @@ static ssize_t i915_cache_sharing_read(struct file *filp, char __user *ubuf, -@@ -1534,7 +1688,7 @@ i915_cache_sharing_write(struct file *filp, +@@ -1534,7 +1688,7 @@ static const struct file_operations i915_cache_sharing_fops = { .owner = THIS_MODULE, @@ -43470,7 +43388,7 @@ .read = i915_cache_sharing_read, .write = i915_cache_sharing_write, .llseek = default_llseek, -@@ -1566,28 +1720,13 @@ drm_add_fake_info_node(struct drm_minor *minor, +@@ -1566,28 +1720,13 @@ return 0; } @@ -43500,7 +43418,7 @@ return 0; ret = mutex_lock_interruptible(&dev->struct_mutex); -@@ -1604,7 +1743,7 @@ int i915_forcewake_release(struct inode *inode, struct file *file) +@@ -1604,7 +1743,7 @@ struct drm_device *dev = inode->i_private; struct drm_i915_private *dev_priv = dev->dev_private; @@ -43509,7 +43427,7 @@ return 0; /* -@@ -1642,34 +1781,22 @@ static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor) +@@ -1642,34 +1781,22 @@ return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops); } @@ -43551,7 +43469,7 @@ } static struct drm_info_list i915_debugfs_list[] = { -@@ -1695,7 +1822,6 @@ static struct drm_info_list i915_debugfs_list[] = { +@@ -1695,7 +1822,6 @@ {"i915_bsd_ringbuffer_info", i915_ringbuffer_info, 0, (void *)VCS}, {"i915_blt_ringbuffer_data", i915_ringbuffer_data, 0, (void *)BCS}, {"i915_blt_ringbuffer_info", i915_ringbuffer_info, 0, (void *)BCS}, @@ -43559,7 +43477,7 @@ {"i915_error_state", i915_error_state, 0}, {"i915_rstdby_delays", i915_rstdby_delays, 0}, {"i915_cur_delayinfo", i915_cur_delayinfo, 0}, -@@ -1711,6 +1837,8 @@ static struct drm_info_list i915_debugfs_list[] = { +@@ -1711,6 +1837,8 @@ {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0}, {"i915_context_status", i915_context_status, 0}, {"i915_gen6_forcewake_count", i915_gen6_forcewake_count_info, 0}, @@ -43568,7 +43486,7 @@ }; #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list) -@@ -1718,17 +1846,25 @@ int i915_debugfs_init(struct drm_minor *minor) +@@ -1718,17 +1846,25 @@ { int ret; @@ -43597,11 +43515,11 @@ if (ret) return ret; -diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c -index ca67338..ba60f3c 100644 ---- a/drivers/gpu/drm/i915/i915_dma.c -+++ b/drivers/gpu/drm/i915/i915_dma.c -@@ -781,6 +781,12 @@ static int i915_getparam(struct drm_device *dev, void *data, +Index: linux-3.2.46/drivers/gpu/drm/i915/i915_dma.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/i915/i915_dma.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/i915/i915_dma.c 2013-07-26 19:26:22.000000000 +0000 +@@ -781,6 +781,12 @@ case I915_PARAM_HAS_RELAXED_DELTA: value = 1; break; @@ -43614,7 +43532,7 @@ default: DRM_DEBUG_DRIVER("Unknown parameter %d\n", param->param); -@@ -1177,6 +1183,21 @@ static bool i915_switcheroo_can_switch(struct pci_dev *pdev) +@@ -1177,6 +1183,21 @@ return can_switch; } @@ -43636,7 +43554,7 @@ static int i915_load_gem_init(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; -@@ -1190,22 +1211,41 @@ static int i915_load_gem_init(struct drm_device *dev) +@@ -1190,22 +1211,41 @@ /* Basic memrange allocator for stolen space */ drm_mm_init(&dev_priv->mm.stolen, 0, prealloc_size); @@ -43691,7 +43609,7 @@ /* Try to set up FBC with a reasonable compressed buffer size */ if (I915_HAS_FBC(dev) && i915_powersave) { -@@ -1292,6 +1332,7 @@ cleanup_gem: +@@ -1292,6 +1332,7 @@ mutex_lock(&dev->struct_mutex); i915_gem_cleanup_ringbuffer(dev); mutex_unlock(&dev->struct_mutex); @@ -43699,7 +43617,7 @@ cleanup_vga_switcheroo: vga_switcheroo_unregister_client(dev->pdev); cleanup_vga_client: -@@ -1660,6 +1701,9 @@ void i915_update_gfx_val(struct drm_i915_private *dev_priv) +@@ -1660,6 +1701,9 @@ unsigned long diffms; u32 count; @@ -43709,7 +43627,7 @@ getrawmonotonic(&now); diff1 = timespec_sub(now, dev_priv->last_time2); -@@ -1890,27 +1934,6 @@ ips_ping_for_i915_load(void) +@@ -1890,27 +1934,6 @@ } } @@ -43737,7 +43655,7 @@ /** * i915_driver_load - setup chip and create an initial config * @dev: DRM device -@@ -1948,14 +1971,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags) +@@ -1948,14 +1971,7 @@ goto free_priv; } @@ -43753,7 +43671,7 @@ /* overlay on gen2 is broken and can't address above 1G */ if (IS_GEN2(dev)) -@@ -1980,6 +1996,13 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags) +@@ -1980,6 +1996,13 @@ goto put_bridge; } @@ -43767,7 +43685,7 @@ agp_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT; dev_priv->mm.gtt_mapping = -@@ -2101,12 +2124,14 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags) +@@ -2101,12 +2124,14 @@ setup_timer(&dev_priv->hangcheck_timer, i915_hangcheck_elapsed, (unsigned long) dev); @@ -43787,7 +43705,7 @@ return 0; -@@ -2149,7 +2174,7 @@ int i915_driver_unload(struct drm_device *dev) +@@ -2149,7 +2174,7 @@ unregister_shrinker(&dev_priv->mm.inactive_shrinker); mutex_lock(&dev->struct_mutex); @@ -43796,7 +43714,7 @@ if (ret) DRM_ERROR("failed to idle hardware: %d\n", ret); mutex_unlock(&dev->struct_mutex); -@@ -2202,6 +2227,7 @@ int i915_driver_unload(struct drm_device *dev) +@@ -2202,6 +2227,7 @@ i915_gem_free_all_phys_object(dev); i915_gem_cleanup_ringbuffer(dev); mutex_unlock(&dev->struct_mutex); @@ -43804,7 +43722,7 @@ if (I915_HAS_FBC(dev) && i915_powersave) i915_cleanup_compression(dev); drm_mm_takedown(&dev_priv->mm.stolen); -@@ -2267,18 +2293,12 @@ void i915_driver_lastclose(struct drm_device * dev) +@@ -2267,18 +2293,12 @@ i915_gem_lastclose(dev); @@ -43823,7 +43741,7 @@ } void i915_driver_postclose(struct drm_device *dev, struct drm_file *file) -@@ -2297,11 +2317,11 @@ struct drm_ioctl_desc i915_ioctls[] = { +@@ -2297,11 +2317,11 @@ DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH), DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH), DRM_IOCTL_DEF_DRV(I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), @@ -43839,7 +43757,7 @@ DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE, i915_vblank_pipe_set, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY), DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE, i915_vblank_pipe_get, DRM_AUTH), DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH), -@@ -2329,6 +2349,8 @@ struct drm_ioctl_desc i915_ioctls[] = { +@@ -2329,6 +2349,8 @@ DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_UNLOCKED), DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED), DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED), @@ -43848,11 +43766,11 @@ }; int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls); -diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c -index 452bc51..89f3d4a 100644 ---- a/drivers/gpu/drm/i915/i915_drv.c -+++ b/drivers/gpu/drm/i915/i915_drv.c -@@ -66,7 +66,11 @@ MODULE_PARM_DESC(semaphores, +Index: linux-3.2.46/drivers/gpu/drm/i915/i915_drv.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/i915/i915_drv.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/i915/i915_drv.c 2013-07-26 19:26:22.000000000 +0000 +@@ -66,7 +66,11 @@ int i915_enable_rc6 __read_mostly = -1; module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0400); MODULE_PARM_DESC(i915_enable_rc6, @@ -43865,7 +43783,7 @@ int i915_enable_fbc __read_mostly = -1; module_param_named(i915_enable_fbc, i915_enable_fbc, int, 0600); -@@ -103,6 +107,11 @@ MODULE_PARM_DESC(enable_hangcheck, +@@ -103,6 +107,11 @@ "WARNING: Disabling this can cause system wide hangs. " "(default: true)"); @@ -43877,7 +43795,7 @@ static struct drm_driver driver; extern int intel_agp_enabled; -@@ -198,7 +207,7 @@ static const struct intel_device_info intel_pineview_info = { +@@ -198,7 +207,7 @@ static const struct intel_device_info intel_ironlake_d_info = { .gen = 5, @@ -43886,7 +43804,7 @@ .has_bsd_ring = 1, }; -@@ -214,6 +223,7 @@ static const struct intel_device_info intel_sandybridge_d_info = { +@@ -214,6 +223,7 @@ .need_gfx_hws = 1, .has_hotplug = 1, .has_bsd_ring = 1, .has_blt_ring = 1, @@ -43894,7 +43812,7 @@ .has_force_wake = 1, }; -@@ -223,6 +233,7 @@ static const struct intel_device_info intel_sandybridge_m_info = { +@@ -223,6 +233,7 @@ .has_fbc = 1, .has_bsd_ring = 1, .has_blt_ring = 1, @@ -43902,7 +43820,7 @@ .has_force_wake = 1, }; -@@ -231,6 +242,7 @@ static const struct intel_device_info intel_ivybridge_d_info = { +@@ -231,6 +242,7 @@ .need_gfx_hws = 1, .has_hotplug = 1, .has_bsd_ring = 1, .has_blt_ring = 1, @@ -43910,7 +43828,7 @@ .has_force_wake = 1, }; -@@ -240,6 +252,7 @@ static const struct intel_device_info intel_ivybridge_m_info = { +@@ -240,6 +252,7 @@ .has_fbc = 0, /* FBC is not enabled on Ivybridge mobile yet */ .has_bsd_ring = 1, .has_blt_ring = 1, @@ -43918,7 +43836,7 @@ .has_force_wake = 1, }; -@@ -381,16 +394,27 @@ void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv) +@@ -381,16 +394,27 @@ spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); } @@ -43948,7 +43866,7 @@ } /* -@@ -406,8 +430,10 @@ void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv) +@@ -406,8 +430,10 @@ spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); } @@ -43960,7 +43878,7 @@ if (dev_priv->gt_fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) { int loop = 500; u32 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES); -@@ -415,10 +441,13 @@ void __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv) +@@ -415,10 +441,13 @@ udelay(10); fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES); } @@ -43975,7 +43893,7 @@ } static int i915_drm_freeze(struct drm_device *dev) -@@ -503,7 +532,7 @@ static int i915_drm_thaw(struct drm_device *dev) +@@ -503,7 +532,7 @@ mutex_lock(&dev->struct_mutex); dev_priv->mm.suspended = 0; @@ -43984,7 +43902,7 @@ mutex_unlock(&dev->struct_mutex); if (HAS_PCH_SPLIT(dev)) -@@ -614,13 +643,40 @@ static int ironlake_do_reset(struct drm_device *dev, u8 flags) +@@ -614,13 +643,40 @@ static int gen6_do_reset(struct drm_device *dev, u8 flags) { struct drm_i915_private *dev_priv = dev->dev_private; @@ -44028,7 +43946,7 @@ * @dev: drm device to reset * @flags: reset domains * -@@ -643,7 +699,6 @@ int i915_reset(struct drm_device *dev, u8 flags) +@@ -643,7 +699,6 @@ * need to */ bool need_display = true; @@ -44036,7 +43954,7 @@ int ret; if (!i915_try_reset) -@@ -661,11 +716,6 @@ int i915_reset(struct drm_device *dev, u8 flags) +@@ -661,11 +716,6 @@ case 7: case 6: ret = gen6_do_reset(dev, flags); @@ -44048,7 +43966,7 @@ break; case 5: ret = ironlake_do_reset(dev, flags); -@@ -702,12 +752,16 @@ int i915_reset(struct drm_device *dev, u8 flags) +@@ -702,12 +752,16 @@ !dev_priv->mm.suspended) { dev_priv->mm.suspended = 0; @@ -44065,7 +43983,7 @@ mutex_unlock(&dev->struct_mutex); drm_irq_uninstall(dev); drm_mode_config_reset(dev); -@@ -830,6 +884,21 @@ static struct vm_operations_struct i915_gem_vm_ops = { +@@ -830,6 +884,21 @@ .close = drm_gem_vm_close, }; @@ -44087,7 +44005,7 @@ static struct drm_driver driver = { /* Don't use MTRRs here; the Xserver or userspace app should * deal with them for Intel hardware. -@@ -863,21 +932,7 @@ static struct drm_driver driver = { +@@ -863,21 +932,7 @@ .dumb_map_offset = i915_gem_mmap_gtt, .dumb_destroy = i915_gem_dumb_destroy, .ioctls = i915_ioctls, @@ -44110,7 +44028,7 @@ .name = DRIVER_NAME, .desc = DRIVER_DESC, .date = DRIVER_DATE, -@@ -945,17 +1000,21 @@ MODULE_LICENSE("GPL and additional rights"); +@@ -945,17 +1000,21 @@ /* We give fast paths for the really cool registers */ #define NEEDS_FORCE_WAKE(dev_priv, reg) \ ((HAS_FORCE_WAKE((dev_priv)->dev)) && \ @@ -44137,7 +44055,7 @@ } else { \ val = read##y(dev_priv->regs + reg); \ } \ -@@ -971,11 +1030,15 @@ __i915_read(64, q) +@@ -971,11 +1030,15 @@ #define __i915_write(x, y) \ void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \ @@ -44154,10 +44072,10 @@ } __i915_write(8, b) __i915_write(16, w) -diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h -index 144d37c..45c5cf8 100644 ---- a/drivers/gpu/drm/i915/i915_drv.h -+++ b/drivers/gpu/drm/i915/i915_drv.h +Index: linux-3.2.46/drivers/gpu/drm/i915/i915_drv.h +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/i915/i915_drv.h 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/i915/i915_drv.h 2013-07-26 19:26:22.000000000 +0000 @@ -35,6 +35,7 @@ #include "intel_ringbuffer.h" #include @@ -44166,7 +44084,7 @@ #include #include -@@ -135,6 +136,7 @@ struct drm_i915_fence_reg { +@@ -135,6 +136,7 @@ struct list_head lru_list; struct drm_i915_gem_object *obj; uint32_t setup_seqno; @@ -44174,7 +44092,7 @@ }; struct sdvo_device_mapping { -@@ -152,33 +154,40 @@ struct drm_i915_error_state { +@@ -152,33 +154,40 @@ u32 eir; u32 pgtbl_er; u32 pipestat[I915_MAX_PIPES]; @@ -44237,7 +44155,7 @@ struct drm_i915_error_buffer { u32 size; u32 name; -@@ -191,7 +200,7 @@ struct drm_i915_error_state { +@@ -191,7 +200,7 @@ u32 tiling:2; u32 dirty:1; u32 purgeable:1; @@ -44246,7 +44164,7 @@ u32 cache_level:2; } *active_bo, *pinned_bo; u32 active_bo_count, pinned_bo_count; -@@ -207,6 +216,8 @@ struct drm_i915_display_funcs { +@@ -207,6 +216,8 @@ int (*get_display_clock_speed)(struct drm_device *dev); int (*get_fifo_size)(struct drm_device *dev, int plane); void (*update_wm)(struct drm_device *dev); @@ -44255,7 +44173,7 @@ int (*crtc_mode_set)(struct drm_crtc *crtc, struct drm_display_mode *mode, struct drm_display_mode *adjusted_mode, -@@ -254,6 +265,17 @@ struct intel_device_info { +@@ -254,6 +265,17 @@ u8 supports_tv:1; u8 has_bsd_ring:1; u8 has_blt_ring:1; @@ -44273,7 +44191,7 @@ }; enum no_fbc_reason { -@@ -274,11 +296,20 @@ enum intel_pch { +@@ -274,11 +296,20 @@ #define QUIRK_PIPEA_FORCE (1<<0) #define QUIRK_LVDS_SSC_DISABLE (1<<1) @@ -44295,7 +44213,7 @@ typedef struct drm_i915_private { struct drm_device *dev; -@@ -296,11 +327,11 @@ typedef struct drm_i915_private { +@@ -296,11 +327,11 @@ /** gt_lock is also taken in irq contexts. */ struct spinlock gt_lock; @@ -44312,7 +44230,7 @@ struct pci_dev *bridge_dev; struct intel_ring_buffer ring[I915_NUM_RINGS]; -@@ -335,7 +366,6 @@ typedef struct drm_i915_private { +@@ -335,7 +366,6 @@ int tex_lru_log_granularity; int allow_batchbuffer; @@ -44320,7 +44238,7 @@ unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds; int vblank_pipe; int num_pipe; -@@ -360,6 +390,7 @@ typedef struct drm_i915_private { +@@ -360,6 +390,7 @@ /* overlay */ struct intel_overlay *overlay; @@ -44328,7 +44246,7 @@ /* LVDS info */ int backlight_level; /* restore backlight to this value */ -@@ -585,6 +616,9 @@ typedef struct drm_i915_private { +@@ -585,6 +616,9 @@ struct io_mapping *gtt_mapping; int gtt_mtrr; @@ -44338,7 +44256,7 @@ struct shrinker inactive_shrinker; /** -@@ -750,6 +784,13 @@ typedef struct drm_i915_private { +@@ -750,6 +784,13 @@ struct drm_property *force_audio_property; } drm_i915_private_t; @@ -44352,7 +44270,7 @@ enum i915_cache_level { I915_CACHE_NONE, I915_CACHE_LLC, -@@ -842,6 +883,8 @@ struct drm_i915_gem_object { +@@ -842,6 +883,8 @@ unsigned int cache_level:2; @@ -44361,7 +44279,7 @@ struct page **pages; /** -@@ -919,6 +962,9 @@ struct drm_i915_gem_request { +@@ -919,6 +962,9 @@ /** GEM sequence number associated with this request. */ uint32_t seqno; @@ -44371,7 +44289,7 @@ /** Time at which this request was emitted, in jiffies. */ unsigned long emitted_jiffies; -@@ -975,8 +1021,11 @@ struct drm_i915_file_private { +@@ -975,8 +1021,11 @@ #define HAS_BSD(dev) (INTEL_INFO(dev)->has_bsd_ring) #define HAS_BLT(dev) (INTEL_INFO(dev)->has_blt_ring) @@ -44383,7 +44301,7 @@ #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay) #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical) -@@ -1009,6 +1058,27 @@ struct drm_i915_file_private { +@@ -1009,6 +1058,27 @@ #include "i915_trace.h" @@ -44411,7 +44329,7 @@ extern struct drm_ioctl_desc i915_ioctls[]; extern int i915_max_ioctl; extern unsigned int i915_fbpercrtc __always_unused; -@@ -1021,6 +1091,7 @@ extern int i915_vbt_sdvo_panel_type __read_mostly; +@@ -1021,6 +1091,7 @@ extern int i915_enable_rc6 __read_mostly; extern int i915_enable_fbc __read_mostly; extern bool i915_enable_hangcheck __read_mostly; @@ -44419,7 +44337,7 @@ extern int i915_suspend(struct drm_device *dev, pm_message_t state); extern int i915_resume(struct drm_device *dev); -@@ -1082,18 +1153,6 @@ extern void i915_destroy_error_state(struct drm_device *dev); +@@ -1082,18 +1153,6 @@ #endif @@ -44438,7 +44356,7 @@ /* i915_gem.c */ int i915_gem_init_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv); -@@ -1179,26 +1238,49 @@ int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj, +@@ -1179,26 +1238,49 @@ struct intel_ring_buffer *pipelined); int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj); @@ -44491,7 +44409,7 @@ int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf); int __must_check i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, -@@ -1225,6 +1307,14 @@ int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, +@@ -1225,6 +1307,14 @@ enum i915_cache_level cache_level); /* i915_gem_gtt.c */ @@ -44506,7 +44424,7 @@ void i915_gem_restore_gtt_mappings(struct drm_device *dev); int __must_check i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj); void i915_gem_gtt_rebind_object(struct drm_i915_gem_object *obj, -@@ -1306,7 +1396,6 @@ static inline void intel_unregister_dsm_handler(void) { return; } +@@ -1306,7 +1396,6 @@ #endif /* CONFIG_ACPI */ /* modesetting */ @@ -44514,7 +44432,7 @@ extern void intel_modeset_init(struct drm_device *dev); extern void intel_modeset_gem_init(struct drm_device *dev); extern void intel_modeset_cleanup(struct drm_device *dev); -@@ -1364,14 +1453,7 @@ extern void intel_display_print_error_state(struct seq_file *m, +@@ -1364,14 +1453,7 @@ */ void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv); void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv); @@ -44530,11 +44448,11 @@ #define __i915_read(x, y) \ u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg); -diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c -index 2865b44..eb33945 100644 ---- a/drivers/gpu/drm/i915/i915_gem.c -+++ b/drivers/gpu/drm/i915/i915_gem.c -@@ -58,6 +58,7 @@ static void i915_gem_free_object_tail(struct drm_i915_gem_object *obj); +Index: linux-3.2.46/drivers/gpu/drm/i915/i915_gem.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/i915/i915_gem.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/i915/i915_gem.c 2013-07-26 19:26:22.000000000 +0000 +@@ -58,6 +58,7 @@ static int i915_gem_inactive_shrink(struct shrinker *shrinker, struct shrink_control *sc); @@ -44542,7 +44460,7 @@ /* some bookkeeping */ static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv, -@@ -258,73 +259,6 @@ static int i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj) +@@ -258,73 +259,6 @@ obj->tiling_mode != I915_TILING_NONE; } @@ -44616,7 +44534,7 @@ /** * This is the fast shmem pread path, which attempts to copy_from_user directly * from the backing pages of the object to the user's address space. On a -@@ -385,6 +319,58 @@ i915_gem_shmem_pread_fast(struct drm_device *dev, +@@ -385,6 +319,58 @@ return 0; } @@ -44675,7 +44593,7 @@ /** * This is the fallback shmem pread path, which allocates temporary storage * in kernel space to copy_to_user into outside of the struct_mutex, so we -@@ -398,72 +384,34 @@ i915_gem_shmem_pread_slow(struct drm_device *dev, +@@ -398,72 +384,34 @@ struct drm_file *file) { struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; @@ -44756,7 +44674,7 @@ page = shmem_read_mapping_page(mapping, offset >> PAGE_SHIFT); if (IS_ERR(page)) { -@@ -471,36 +419,38 @@ i915_gem_shmem_pread_slow(struct drm_device *dev, +@@ -471,36 +419,38 @@ goto out; } @@ -44816,7 +44734,7 @@ return ret; } -@@ -841,71 +791,36 @@ i915_gem_shmem_pwrite_slow(struct drm_device *dev, +@@ -841,71 +791,36 @@ struct drm_file *file) { struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; @@ -44897,7 +44815,7 @@ page = shmem_read_mapping_page(mapping, offset >> PAGE_SHIFT); if (IS_ERR(page)) { -@@ -913,34 +828,45 @@ i915_gem_shmem_pwrite_slow(struct drm_device *dev, +@@ -913,34 +828,45 @@ goto out; } @@ -44961,7 +44879,7 @@ return ret; } -@@ -996,11 +922,14 @@ i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, +@@ -996,11 +922,14 @@ * pread/pwrite currently are reading and writing from the CPU * perspective, requiring manual detiling by the client. */ @@ -44980,7 +44898,7 @@ ret = i915_gem_object_pin(obj, 0, true); if (ret) goto out; -@@ -1019,18 +948,24 @@ i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, +@@ -1019,18 +948,24 @@ out_unpin: i915_gem_object_unpin(obj); @@ -45014,7 +44932,7 @@ out: drm_gem_object_unreference(&obj->base); unlock: -@@ -1142,7 +1077,6 @@ int +@@ -1142,7 +1077,6 @@ i915_gem_mmap_ioctl(struct drm_device *dev, void *data, struct drm_file *file) { @@ -45022,7 +44940,7 @@ struct drm_i915_gem_mmap *args = data; struct drm_gem_object *obj; unsigned long addr; -@@ -1154,16 +1088,9 @@ i915_gem_mmap_ioctl(struct drm_device *dev, void *data, +@@ -1154,16 +1088,9 @@ if (obj == NULL) return -ENOENT; @@ -45040,7 +44958,7 @@ drm_gem_object_unreference_unlocked(obj); if (IS_ERR((void *)addr)) return addr; -@@ -1687,12 +1614,20 @@ i915_add_request(struct intel_ring_buffer *ring, +@@ -1687,12 +1614,20 @@ { drm_i915_private_t *dev_priv = ring->dev->dev_private; uint32_t seqno; @@ -45061,7 +44979,7 @@ ret = ring->add_request(ring, &seqno); if (ret) return ret; -@@ -1701,6 +1636,7 @@ i915_add_request(struct intel_ring_buffer *ring, +@@ -1701,6 +1636,7 @@ request->seqno = seqno; request->ring = ring; @@ -45069,7 +44987,7 @@ request->emitted_jiffies = jiffies; was_empty = list_empty(&ring->request_list); list_add_tail(&request->list, &ring->request_list); -@@ -1715,7 +1651,7 @@ i915_add_request(struct intel_ring_buffer *ring, +@@ -1715,7 +1651,7 @@ spin_unlock(&file_priv->mm.lock); } @@ -45078,7 +44996,7 @@ if (!dev_priv->mm.suspended) { if (i915_enable_hangcheck) { -@@ -1837,7 +1773,7 @@ void i915_gem_reset(struct drm_device *dev) +@@ -1837,7 +1773,7 @@ /** * This function clears the request list as sequence numbers are passed. */ @@ -45087,7 +45005,7 @@ i915_gem_retire_requests_ring(struct intel_ring_buffer *ring) { uint32_t seqno; -@@ -1865,6 +1801,12 @@ i915_gem_retire_requests_ring(struct intel_ring_buffer *ring) +@@ -1865,6 +1801,12 @@ break; trace_i915_gem_request_retire(ring, request->seqno); @@ -45100,7 +45018,7 @@ list_del(&request->list); i915_gem_request_remove_from_client(request); -@@ -1977,7 +1919,8 @@ i915_gem_retire_work_handler(struct work_struct *work) +@@ -1977,7 +1919,8 @@ */ int i915_wait_request(struct intel_ring_buffer *ring, @@ -45110,7 +45028,7 @@ { drm_i915_private_t *dev_priv = ring->dev->dev_private; u32 ier; -@@ -2040,9 +1983,9 @@ i915_wait_request(struct intel_ring_buffer *ring, +@@ -2040,9 +1983,9 @@ || atomic_read(&dev_priv->mm.wedged)); ring->irq_put(ring); @@ -45123,7 +45041,7 @@ ret = -EBUSY; ring->waiting_seqno = 0; -@@ -2051,17 +1994,12 @@ i915_wait_request(struct intel_ring_buffer *ring, +@@ -2051,17 +1994,12 @@ if (atomic_read(&dev_priv->mm.wedged)) ret = -EAGAIN; @@ -45142,7 +45060,7 @@ i915_gem_retire_requests_ring(ring); return ret; -@@ -2085,7 +2023,8 @@ i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj) +@@ -2085,7 +2023,8 @@ * it. */ if (obj->active) { @@ -45152,7 +45070,7 @@ if (ret) return ret; } -@@ -2123,6 +2062,7 @@ static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj) +@@ -2123,6 +2062,7 @@ int i915_gem_object_unbind(struct drm_i915_gem_object *obj) { @@ -45160,7 +45078,7 @@ int ret = 0; if (obj->gtt_space == NULL) -@@ -2167,6 +2107,11 @@ i915_gem_object_unbind(struct drm_i915_gem_object *obj) +@@ -2167,6 +2107,11 @@ trace_i915_gem_object_unbind(obj); i915_gem_gtt_unbind_object(obj); @@ -45172,7 +45090,7 @@ i915_gem_object_put_pages_gtt(obj); list_del_init(&obj->gtt_list); -@@ -2206,7 +2151,7 @@ i915_gem_flush_ring(struct intel_ring_buffer *ring, +@@ -2206,7 +2151,7 @@ return 0; } @@ -45181,7 +45099,7 @@ { int ret; -@@ -2220,18 +2165,18 @@ static int i915_ring_idle(struct intel_ring_buffer *ring) +@@ -2220,18 +2165,18 @@ return ret; } @@ -45204,7 +45122,7 @@ if (ret) return ret; } -@@ -2434,7 +2379,8 @@ i915_gem_object_flush_fence(struct drm_i915_gem_object *obj, +@@ -2434,7 +2379,8 @@ if (!ring_passed_seqno(obj->last_fenced_ring, obj->last_fenced_seqno)) { ret = i915_wait_request(obj->last_fenced_ring, @@ -45214,7 +45132,7 @@ if (ret) return ret; } -@@ -2466,6 +2412,8 @@ i915_gem_object_put_fence(struct drm_i915_gem_object *obj) +@@ -2466,6 +2412,8 @@ if (obj->fence_reg != I915_FENCE_REG_NONE) { struct drm_i915_private *dev_priv = obj->base.dev->dev_private; @@ -45223,7 +45141,7 @@ i915_gem_clear_fence_reg(obj->base.dev, &dev_priv->fence_regs[obj->fence_reg]); -@@ -2490,7 +2438,7 @@ i915_find_fence_reg(struct drm_device *dev, +@@ -2490,7 +2438,7 @@ if (!reg->obj) return reg; @@ -45232,7 +45150,7 @@ avail = reg; } -@@ -2500,7 +2448,7 @@ i915_find_fence_reg(struct drm_device *dev, +@@ -2500,7 +2448,7 @@ /* None available, try to steal one or wait for a user to finish */ avail = first = NULL; list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) { @@ -45241,7 +45159,7 @@ continue; if (first == NULL) -@@ -2520,11 +2468,6 @@ i915_find_fence_reg(struct drm_device *dev, +@@ -2520,11 +2468,6 @@ return avail; } @@ -45253,7 +45171,7 @@ /** * i915_gem_object_get_fence - set up a fence reg for an object * @obj: object to map through a fence reg -@@ -2580,7 +2523,8 @@ i915_gem_object_get_fence(struct drm_i915_gem_object *obj, +@@ -2580,7 +2523,8 @@ if (!ring_passed_seqno(obj->last_fenced_ring, reg->setup_seqno)) { ret = i915_wait_request(obj->last_fenced_ring, @@ -45263,7 +45181,7 @@ if (ret) return ret; } -@@ -2599,7 +2543,7 @@ i915_gem_object_get_fence(struct drm_i915_gem_object *obj, +@@ -2599,7 +2543,7 @@ reg = i915_find_fence_reg(dev, pipelined); if (reg == NULL) @@ -45272,7 +45190,7 @@ ret = i915_gem_object_flush_fence(obj, pipelined); if (ret) -@@ -2645,17 +2589,6 @@ update: +@@ -2645,17 +2589,6 @@ switch (INTEL_INFO(dev)->gen) { case 7: case 6: @@ -45290,7 +45208,7 @@ ret = sandybridge_write_fence_reg(obj, pipelined); break; case 5: -@@ -2710,6 +2643,7 @@ i915_gem_clear_fence_reg(struct drm_device *dev, +@@ -2710,6 +2643,7 @@ list_del_init(®->lru_list); reg->obj = NULL; reg->setup_seqno = 0; @@ -45298,7 +45216,7 @@ } /** -@@ -2996,6 +2930,8 @@ i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write) +@@ -2996,6 +2930,8 @@ int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, enum i915_cache_level cache_level) { @@ -45307,7 +45225,7 @@ int ret; if (obj->cache_level == cache_level) -@@ -3024,6 +2960,9 @@ int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, +@@ -3024,6 +2960,9 @@ } i915_gem_gtt_rebind_object(obj, cache_level); @@ -45317,7 +45235,7 @@ } if (cache_level == I915_CACHE_NONE) { -@@ -3362,8 +3301,8 @@ i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file) +@@ -3362,8 +3301,8 @@ if (ret == 0 && atomic_read(&dev_priv->mm.wedged)) ret = -EIO; @@ -45328,7 +45246,7 @@ atomic_read(&dev_priv->mm.wedged), 3000)) { ret = -EBUSY; } -@@ -3472,15 +3411,14 @@ i915_gem_pin_ioctl(struct drm_device *dev, void *data, +@@ -3472,15 +3411,14 @@ goto out; } @@ -45347,7 +45265,7 @@ /* XXX - flush the CPU caches for pinned objects * as the X server doesn't manage domains yet */ -@@ -3674,8 +3612,8 @@ struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, +@@ -3674,8 +3612,8 @@ obj->base.write_domain = I915_GEM_DOMAIN_CPU; obj->base.read_domains = I915_GEM_DOMAIN_CPU; @@ -45358,7 +45276,7 @@ * cache) for about a 10% performance improvement * compared to uncached. Graphics requests other than * display scanout are coherent with the CPU in -@@ -3765,7 +3703,7 @@ i915_gem_idle(struct drm_device *dev) +@@ -3765,7 +3703,7 @@ return 0; } @@ -45367,7 +45285,7 @@ if (ret) { mutex_unlock(&dev->struct_mutex); return ret; -@@ -3800,12 +3738,91 @@ i915_gem_idle(struct drm_device *dev) +@@ -3800,12 +3738,91 @@ return 0; } @@ -45460,7 +45378,7 @@ ret = intel_init_render_ring_buffer(dev); if (ret) return ret; -@@ -3824,6 +3841,8 @@ i915_gem_init_ringbuffer(struct drm_device *dev) +@@ -3824,6 +3841,8 @@ dev_priv->next_seqno = 1; @@ -45469,7 +45387,7 @@ return 0; cleanup_bsd_ring: -@@ -3861,7 +3880,7 @@ i915_gem_entervt_ioctl(struct drm_device *dev, void *data, +@@ -3861,7 +3880,7 @@ mutex_lock(&dev->struct_mutex); dev_priv->mm.suspended = 0; @@ -45478,7 +45396,7 @@ if (ret != 0) { mutex_unlock(&dev->struct_mutex); return ret; -@@ -4256,7 +4275,7 @@ rescan: +@@ -4256,7 +4275,7 @@ * This has a dramatic impact to reduce the number of * OOM-killer events whilst running the GPU aggressively. */ @@ -45487,11 +45405,11 @@ goto rescan; } mutex_unlock(&dev->struct_mutex); -diff --git a/drivers/gpu/drm/i915/i915_gem_evict.c b/drivers/gpu/drm/i915/i915_gem_evict.c -index ead5d00..21a8271 100644 ---- a/drivers/gpu/drm/i915/i915_gem_evict.c -+++ b/drivers/gpu/drm/i915/i915_gem_evict.c -@@ -36,7 +36,6 @@ static bool +Index: linux-3.2.46/drivers/gpu/drm/i915/i915_gem_evict.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/i915/i915_gem_evict.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/i915/i915_gem_evict.c 2013-07-26 19:26:22.000000000 +0000 +@@ -36,7 +36,6 @@ mark_free(struct drm_i915_gem_object *obj, struct list_head *unwind) { list_add(&obj->exec_list, unwind); @@ -45499,7 +45417,7 @@ return drm_mm_scan_add_block(obj->gtt_space); } -@@ -49,21 +48,6 @@ i915_gem_evict_something(struct drm_device *dev, int min_size, +@@ -49,21 +48,6 @@ struct drm_i915_gem_object *obj; int ret = 0; @@ -45521,7 +45439,7 @@ trace_i915_gem_evict(dev, min_size, alignment, mappable); /* -@@ -139,7 +123,6 @@ i915_gem_evict_something(struct drm_device *dev, int min_size, +@@ -139,7 +123,6 @@ BUG_ON(ret); list_del_init(&obj->exec_list); @@ -45529,7 +45447,7 @@ } /* We expect the caller to unpin, evict all and try again, or give up. -@@ -158,10 +141,10 @@ found: +@@ -158,10 +141,10 @@ exec_list); if (drm_mm_scan_remove_block(obj->gtt_space)) { list_move(&obj->exec_list, &eviction_list); @@ -45541,7 +45459,7 @@ } /* Unbinding will emit any required flushes */ -@@ -195,7 +178,7 @@ i915_gem_evict_everything(struct drm_device *dev, bool purgeable_only) +@@ -195,7 +178,7 @@ trace_i915_gem_evict_everything(dev, purgeable_only); /* Flush everything (on to the inactive lists) and evict */ @@ -45550,11 +45468,11 @@ if (ret) return ret; -diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c -index b1bb734..e97ed61 100644 ---- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c -+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c -@@ -203,9 +203,9 @@ i915_gem_object_set_to_gpu_domain(struct drm_i915_gem_object *obj, +Index: linux-3.2.46/drivers/gpu/drm/i915/i915_gem_execbuffer.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/i915/i915_gem_execbuffer.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/i915/i915_gem_execbuffer.c 2013-07-26 19:26:22.000000000 +0000 +@@ -203,9 +203,9 @@ cd->invalidate_domains |= invalidate_domains; cd->flush_domains |= flush_domains; if (flush_domains & I915_GEM_GPU_DOMAINS) @@ -45566,7 +45484,7 @@ } struct eb_objects { -@@ -287,14 +287,14 @@ i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj, +@@ -287,14 +287,14 @@ * exec_object list, so it should have a GTT space bound by now. */ if (unlikely(target_offset == 0)) { @@ -45583,7 +45501,7 @@ "obj %p target %d offset %d " "read %08x write %08x", obj, reloc->target_handle, -@@ -303,8 +303,9 @@ i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj, +@@ -303,8 +303,9 @@ reloc->write_domain); return ret; } @@ -45595,7 +45513,7 @@ "obj %p target %d offset %d " "read %08x write %08x", obj, reloc->target_handle, -@@ -315,7 +316,7 @@ i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj, +@@ -315,7 +316,7 @@ } if (unlikely(reloc->write_domain && target_obj->pending_write_domain && reloc->write_domain != target_obj->pending_write_domain)) { @@ -45604,7 +45522,7 @@ "obj %p target %d offset %d " "new %08x old %08x\n", obj, reloc->target_handle, -@@ -336,7 +337,7 @@ i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj, +@@ -336,7 +337,7 @@ /* Check that the relocation address is valid... */ if (unlikely(reloc->offset > obj->base.size - 4)) { @@ -45613,7 +45531,7 @@ "obj %p target %d offset %d size %d.\n", obj, reloc->target_handle, (int) reloc->offset, -@@ -344,7 +345,7 @@ i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj, +@@ -344,7 +345,7 @@ return ret; } if (unlikely(reloc->offset & 3)) { @@ -45622,7 +45540,7 @@ "obj %p target %d offset %d.\n", obj, reloc->target_handle, (int) reloc->offset); -@@ -461,11 +462,60 @@ i915_gem_execbuffer_relocate(struct drm_device *dev, +@@ -461,11 +462,60 @@ return ret; } @@ -45683,7 +45601,7 @@ struct drm_i915_gem_object *obj; int ret, retry; bool has_fenced_gpu_access = INTEL_INFO(ring->dev)->gen < 4; -@@ -518,6 +568,7 @@ i915_gem_execbuffer_reserve(struct intel_ring_buffer *ring, +@@ -518,6 +568,7 @@ list_for_each_entry(obj, objects, exec_list) { struct drm_i915_gem_exec_object2 *entry = obj->exec_entry; bool need_fence, need_mappable; @@ -45691,7 +45609,7 @@ if (!obj->gtt_space) continue; -@@ -532,59 +583,55 @@ i915_gem_execbuffer_reserve(struct intel_ring_buffer *ring, +@@ -532,59 +583,55 @@ (need_mappable && !obj->map_and_fenceable)) ret = i915_gem_object_unbind(obj); else @@ -45709,44 +45627,23 @@ list_for_each_entry(obj, objects, exec_list) { - struct drm_i915_gem_exec_object2 *entry = obj->exec_entry; - bool need_fence; -+ if (obj->gtt_space) -+ continue; - +- - need_fence = - has_fenced_gpu_access && - entry->flags & EXEC_OBJECT_NEEDS_FENCE && - obj->tiling_mode != I915_TILING_NONE; -+ ret = pin_and_fence_object(obj, ring); -+ if (ret) { -+ int ret_ignore; -+ -+ /* This can potentially raise a harmless -+ * -EINVAL if we failed to bind in the above -+ * call. It cannot raise -EINTR since we know -+ * that the bo is freshly bound and so will -+ * not need to be flushed or waited upon. -+ */ -+ ret_ignore = i915_gem_object_unbind(obj); -+ (void)ret_ignore; -+ WARN_ON(obj->gtt_space); -+ break; -+ } -+ } - +- - if (!obj->gtt_space) { - bool need_mappable = - entry->relocation_count ? true : need_fence; -+ /* Decrement pin count for bound objects */ -+ list_for_each_entry(obj, objects, exec_list) { -+ struct drm_i915_gem_exec_object2 *entry; - +- - ret = i915_gem_object_pin(obj, - entry->alignment, - need_mappable); - if (ret) - break; - } -+ if (!obj->gtt_space) ++ if (obj->gtt_space) + continue; - if (has_fenced_gpu_access) { @@ -45763,20 +45660,42 @@ - } - obj->pending_fenced_gpu_access = - !!(entry->flags & EXEC_OBJECT_NEEDS_FENCE); -+ entry = obj->exec_entry; -+ if (entry->flags & __EXEC_OBJECT_HAS_FENCE) { -+ i915_gem_object_unpin_fence(obj); -+ entry->flags &= ~__EXEC_OBJECT_HAS_FENCE; ++ ret = pin_and_fence_object(obj, ring); ++ if (ret) { ++ int ret_ignore; ++ ++ /* This can potentially raise a harmless ++ * -EINVAL if we failed to bind in the above ++ * call. It cannot raise -EINTR since we know ++ * that the bo is freshly bound and so will ++ * not need to be flushed or waited upon. ++ */ ++ ret_ignore = i915_gem_object_unbind(obj); ++ (void)ret_ignore; ++ WARN_ON(obj->gtt_space); ++ break; } - +- - entry->offset = obj->gtt_offset; -- } -+ i915_gem_object_unpin(obj); + } -- /* Decrement pin count for bound objects */ -- list_for_each_entry(obj, objects, exec_list) { + /* Decrement pin count for bound objects */ + list_for_each_entry(obj, objects, exec_list) { - if (obj->gtt_space) - i915_gem_object_unpin(obj); ++ struct drm_i915_gem_exec_object2 *entry; ++ ++ if (!obj->gtt_space) ++ continue; ++ ++ entry = obj->exec_entry; ++ if (entry->flags & __EXEC_OBJECT_HAS_FENCE) { ++ i915_gem_object_unpin_fence(obj); ++ entry->flags &= ~__EXEC_OBJECT_HAS_FENCE; ++ } ++ ++ i915_gem_object_unpin(obj); ++ + /* ... and ensure ppgtt mapping exist if needed. */ + if (dev_priv->mm.aliasing_ppgtt && !obj->has_aliasing_ppgtt_mapping) { + i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt, @@ -45787,7 +45706,7 @@ } if (ret != -ENOSPC || retry > 1) -@@ -601,16 +648,19 @@ i915_gem_execbuffer_reserve(struct intel_ring_buffer *ring, +@@ -601,16 +648,19 @@ } while (1); err: @@ -45799,13 +45718,13 @@ - i915_gem_object_unpin(obj); + list_for_each_entry_continue_reverse(obj, objects, exec_list) { + struct drm_i915_gem_exec_object2 *entry; -+ -+ if (!obj->gtt_space) -+ continue; - obj = list_entry(obj->exec_list.prev, - struct drm_i915_gem_object, - exec_list); ++ if (!obj->gtt_space) ++ continue; ++ + entry = obj->exec_entry; + if (entry->flags & __EXEC_OBJECT_HAS_FENCE) { + i915_gem_object_unpin_fence(obj); @@ -45816,7 +45735,7 @@ } return ret; -@@ -704,7 +754,7 @@ i915_gem_execbuffer_relocate_slow(struct drm_device *dev, +@@ -704,7 +754,7 @@ obj = to_intel_bo(drm_gem_object_lookup(dev, file, exec[i].handle)); if (&obj->base == NULL) { @@ -45825,7 +45744,7 @@ exec[i].handle, i); ret = -ENOENT; goto err; -@@ -998,6 +1048,31 @@ i915_gem_execbuffer_retire_commands(struct drm_device *dev, +@@ -998,6 +1048,31 @@ } static int @@ -45857,7 +45776,7 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data, struct drm_file *file, struct drm_i915_gem_execbuffer2 *args, -@@ -1015,7 +1090,7 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data, +@@ -1015,7 +1090,7 @@ int ret, mode, i; if (!i915_gem_check_execbuffer(args)) { @@ -45866,7 +45785,7 @@ return -EINVAL; } -@@ -1030,20 +1105,20 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data, +@@ -1030,20 +1105,20 @@ break; case I915_EXEC_BSD: if (!HAS_BSD(dev)) { @@ -45890,7 +45809,7 @@ (int)(args->flags & I915_EXEC_RING_MASK)); return -EINVAL; } -@@ -1069,18 +1144,18 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data, +@@ -1069,18 +1144,18 @@ } break; default: @@ -45912,7 +45831,7 @@ return -EINVAL; } -@@ -1130,7 +1205,7 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data, +@@ -1130,7 +1205,7 @@ obj = to_intel_bo(drm_gem_object_lookup(dev, file, exec[i].handle)); if (&obj->base == NULL) { @@ -45921,7 +45840,7 @@ exec[i].handle, i); /* prevent error path from reading uninitialized data */ ret = -ENOENT; -@@ -1138,7 +1213,7 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data, +@@ -1138,7 +1213,7 @@ } if (!list_empty(&obj->exec_list)) { @@ -45930,7 +45849,7 @@ obj, exec[i].handle, i); ret = -EINVAL; goto err; -@@ -1176,7 +1251,7 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data, +@@ -1176,7 +1251,7 @@ /* Set the pending read domains for the batch buffer to COMMAND */ if (batch_obj->base.pending_write_domain) { @@ -45939,7 +45858,7 @@ ret = -EINVAL; goto err; } -@@ -1193,7 +1268,7 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data, +@@ -1193,7 +1268,7 @@ * so every billion or so execbuffers, we need to stall * the GPU in order to reset the counters. */ @@ -45948,7 +45867,7 @@ if (ret) goto err; -@@ -1216,6 +1291,12 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data, +@@ -1216,6 +1291,12 @@ dev_priv->relative_constants_mode = mode; } @@ -45961,7 +45880,7 @@ trace_i915_gem_ring_dispatch(ring, seqno); exec_start = batch_obj->gtt_offset + args->batch_start_offset; -@@ -1275,7 +1356,7 @@ i915_gem_execbuffer(struct drm_device *dev, void *data, +@@ -1275,7 +1356,7 @@ int ret, i; if (args->buffer_count < 1) { @@ -45970,7 +45889,7 @@ return -EINVAL; } -@@ -1283,7 +1364,7 @@ i915_gem_execbuffer(struct drm_device *dev, void *data, +@@ -1283,7 +1364,7 @@ exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count); exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count); if (exec_list == NULL || exec2_list == NULL) { @@ -45979,7 +45898,7 @@ args->buffer_count); drm_free_large(exec_list); drm_free_large(exec2_list); -@@ -1294,7 +1375,7 @@ i915_gem_execbuffer(struct drm_device *dev, void *data, +@@ -1294,7 +1375,7 @@ (uintptr_t) args->buffers_ptr, sizeof(*exec_list) * args->buffer_count); if (ret != 0) { @@ -45988,7 +45907,7 @@ args->buffer_count, ret); drm_free_large(exec_list); drm_free_large(exec2_list); -@@ -1335,7 +1416,7 @@ i915_gem_execbuffer(struct drm_device *dev, void *data, +@@ -1335,7 +1416,7 @@ sizeof(*exec_list) * args->buffer_count); if (ret) { ret = -EFAULT; @@ -45997,7 +45916,7 @@ "back to user (%d)\n", args->buffer_count, ret); } -@@ -1356,7 +1437,7 @@ i915_gem_execbuffer2(struct drm_device *dev, void *data, +@@ -1356,7 +1437,7 @@ if (args->buffer_count < 1 || args->buffer_count > UINT_MAX / sizeof(*exec2_list)) { @@ -46006,7 +45925,7 @@ return -EINVAL; } -@@ -1366,7 +1447,7 @@ i915_gem_execbuffer2(struct drm_device *dev, void *data, +@@ -1366,7 +1447,7 @@ exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count); if (exec2_list == NULL) { @@ -46015,7 +45934,7 @@ args->buffer_count); return -ENOMEM; } -@@ -1375,7 +1456,7 @@ i915_gem_execbuffer2(struct drm_device *dev, void *data, +@@ -1375,7 +1456,7 @@ (uintptr_t) args->buffers_ptr, sizeof(*exec2_list) * args->buffer_count); if (ret != 0) { @@ -46024,7 +45943,7 @@ args->buffer_count, ret); drm_free_large(exec2_list); return -EFAULT; -@@ -1390,7 +1471,7 @@ i915_gem_execbuffer2(struct drm_device *dev, void *data, +@@ -1390,7 +1471,7 @@ sizeof(*exec2_list) * args->buffer_count); if (ret) { ret = -EFAULT; @@ -46033,10 +45952,10 @@ "back to user (%d)\n", args->buffer_count, ret); } -diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c -index 6042c5e..99a7855 100644 ---- a/drivers/gpu/drm/i915/i915_gem_gtt.c -+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c +Index: linux-3.2.46/drivers/gpu/drm/i915/i915_gem_gtt.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/i915/i915_gem_gtt.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/i915/i915_gem_gtt.c 2013-07-26 19:26:22.000000000 +0000 @@ -29,6 +29,270 @@ #include "i915_trace.h" #include "intel_drv.h" @@ -46308,7 +46227,7 @@ /* XXX kill agp_type! */ static unsigned int cache_level_to_agp_type(struct drm_device *dev, enum i915_cache_level cache_level) -@@ -55,7 +319,7 @@ static bool do_idling(struct drm_i915_private *dev_priv) +@@ -55,7 +319,7 @@ if (unlikely(dev_priv->mm.gtt->do_idle_maps)) { dev_priv->mm.interruptible = false; @@ -46317,11 +46236,11 @@ DRM_ERROR("Couldn't idle GPU\n"); /* Wait a bit, in hopes it avoids the hang */ udelay(10); -diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i915/i915_gem_tiling.c -index 861223b..1a93066 100644 ---- a/drivers/gpu/drm/i915/i915_gem_tiling.c -+++ b/drivers/gpu/drm/i915/i915_gem_tiling.c -@@ -93,8 +93,23 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev) +Index: linux-3.2.46/drivers/gpu/drm/i915/i915_gem_tiling.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/i915/i915_gem_tiling.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/i915/i915_gem_tiling.c 2013-07-26 19:26:22.000000000 +0000 +@@ -93,8 +93,23 @@ uint32_t swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN; if (INTEL_INFO(dev)->gen >= 6) { @@ -46347,11 +46266,11 @@ } else if (IS_GEN5(dev)) { /* On Ironlake whatever DRAM config, GPU always do * same swizzling setup. -diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c -index 93e74fb..8bca2d2 100644 ---- a/drivers/gpu/drm/i915/i915_irq.c -+++ b/drivers/gpu/drm/i915/i915_irq.c -@@ -716,7 +716,6 @@ i915_error_object_create(struct drm_i915_private *dev_priv, +Index: linux-3.2.46/drivers/gpu/drm/i915/i915_irq.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/i915/i915_irq.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/i915/i915_irq.c 2013-07-26 19:26:22.000000000 +0000 +@@ -716,7 +716,6 @@ reloc_offset = src->gtt_offset; for (page = 0; page < page_count; page++) { unsigned long flags; @@ -46359,7 +46278,7 @@ void *d; d = kmalloc(PAGE_SIZE, GFP_ATOMIC); -@@ -724,10 +723,29 @@ i915_error_object_create(struct drm_i915_private *dev_priv, +@@ -724,10 +723,29 @@ goto unwind; local_irq_save(flags); @@ -46393,7 +46312,7 @@ local_irq_restore(flags); dst->pages[page] = d; -@@ -766,11 +784,11 @@ i915_error_state_free(struct drm_device *dev, +@@ -766,11 +784,11 @@ { int i; @@ -46410,7 +46329,7 @@ kfree(error->active_bo); kfree(error->overlay); -@@ -800,7 +818,7 @@ static u32 capture_bo_list(struct drm_i915_error_buffer *err, +@@ -800,7 +818,7 @@ err->tiling = obj->tiling_mode; err->dirty = obj->dirty; err->purgeable = obj->madv != I915_MADV_WILLNEED; @@ -46419,7 +46338,7 @@ err->cache_level = obj->cache_level; if (++i == count) -@@ -872,6 +890,92 @@ i915_error_first_batchbuffer(struct drm_i915_private *dev_priv, +@@ -872,6 +890,92 @@ return NULL; } @@ -46512,7 +46431,7 @@ /** * i915_capture_error_state - capture an error record for later analysis * @dev: drm device -@@ -896,7 +1000,7 @@ static void i915_capture_error_state(struct drm_device *dev) +@@ -896,7 +1000,7 @@ return; /* Account for pipe specific data like PIPE*STAT */ @@ -46521,7 +46440,7 @@ if (!error) { DRM_DEBUG_DRIVER("out of memory, not capturing error state\n"); return; -@@ -905,59 +1009,18 @@ static void i915_capture_error_state(struct drm_device *dev) +@@ -905,59 +1009,18 @@ DRM_INFO("capturing error event; look for more information in /debug/dri/%d/i915_error_state\n", dev->primary->index); @@ -46585,7 +46504,7 @@ /* Record buffers on the active and pinned lists. */ error->active_bo = NULL; -@@ -1013,11 +1076,12 @@ void i915_destroy_error_state(struct drm_device *dev) +@@ -1013,11 +1076,12 @@ { struct drm_i915_private *dev_priv = dev->dev_private; struct drm_i915_error_state *error; @@ -46600,7 +46519,7 @@ if (error) i915_error_state_free(dev, error); -@@ -1187,9 +1251,7 @@ static void i915_pageflip_stall_check(struct drm_device *dev, int pipe) +@@ -1187,9 +1251,7 @@ spin_lock_irqsave(&dev->event_lock, flags); work = intel_crtc->unpin_work; @@ -46611,7 +46530,7 @@ /* Either the pending flip IRQ arrived, or we're too early. Don't check */ spin_unlock_irqrestore(&dev->event_lock, flags); return; -@@ -1203,7 +1265,7 @@ static void i915_pageflip_stall_check(struct drm_device *dev, int pipe) +@@ -1203,7 +1265,7 @@ } else { int dspaddr = DSPADDR(intel_crtc->plane); stall_detected = I915_READ(dspaddr) == (obj->gtt_offset + @@ -46620,7 +46539,7 @@ crtc->x * crtc->fb->bits_per_pixel/8); } -@@ -1647,13 +1709,6 @@ static bool kick_ring(struct intel_ring_buffer *ring) +@@ -1647,13 +1709,6 @@ I915_WRITE_CTL(ring, tmp); return true; } @@ -46634,7 +46553,7 @@ return false; } -@@ -1703,6 +1758,7 @@ void i915_hangcheck_elapsed(unsigned long data) +@@ -1703,6 +1758,7 @@ dev_priv->last_instdone1 == instdone1) { if (dev_priv->hangcheck_count++ > 1) { DRM_ERROR("Hangcheck timer elapsed... GPU hung\n"); @@ -46642,7 +46561,7 @@ if (!IS_GEN2(dev)) { /* Is the chip hanging on a WAIT_FOR_EVENT? -@@ -1710,7 +1766,6 @@ void i915_hangcheck_elapsed(unsigned long data) +@@ -1710,7 +1766,6 @@ * and break the hang. This should work on * all but the second generation chipsets. */ @@ -46650,7 +46569,7 @@ if (kick_ring(&dev_priv->ring[RCS])) goto repeat; -@@ -1723,7 +1778,6 @@ void i915_hangcheck_elapsed(unsigned long data) +@@ -1723,7 +1778,6 @@ goto repeat; } @@ -46658,7 +46577,7 @@ return; } } else { -@@ -1756,17 +1810,6 @@ static void ironlake_irq_preinstall(struct drm_device *dev) +@@ -1756,17 +1810,6 @@ INIT_WORK(&dev_priv->rps_work, gen6_pm_rps_work); I915_WRITE(HWSTAM, 0xeffe); @@ -46676,11 +46595,10 @@ /* XXX hotplug from PCH */ -diff --git a/drivers/gpu/drm/i915/i915_mem.c b/drivers/gpu/drm/i915/i915_mem.c -deleted file mode 100644 -index cc8f6d4..0000000 ---- a/drivers/gpu/drm/i915/i915_mem.c -+++ /dev/null +Index: linux-3.2.46/drivers/gpu/drm/i915/i915_mem.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/i915/i915_mem.c 2013-07-26 18:53:34.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 @@ -1,387 +0,0 @@ -/* i915_mem.c -- Simple agp/fb memory manager for i915 -*- linux-c -*- - */ @@ -47069,10 +46987,10 @@ - i915_mem_takedown(heap); - return 0; -} -diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h -index 124dd87..dde62bf 100644 ---- a/drivers/gpu/drm/i915/i915_reg.h -+++ b/drivers/gpu/drm/i915/i915_reg.h +Index: linux-3.2.46/drivers/gpu/drm/i915/i915_reg.h +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/i915/i915_reg.h 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/i915/i915_reg.h 2013-07-26 19:26:22.000000000 +0000 @@ -88,12 +88,45 @@ #define GEN6_MBC_SNPCR_LOW (2<<21) #define GEN6_MBC_SNPCR_MIN (3<<21) /* only 1/16th of the cache is shared */ @@ -47559,10 +47477,10 @@ +#define AUD_CONFIG_DISABLE_NCTS (1 << 3) #endif /* _I915_REG_H_ */ -diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c -index f38d196..0d13778 100644 ---- a/drivers/gpu/drm/i915/i915_suspend.c -+++ b/drivers/gpu/drm/i915/i915_suspend.c +Index: linux-3.2.46/drivers/gpu/drm/i915/i915_suspend.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/i915/i915_suspend.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/i915/i915_suspend.c 2013-07-26 19:26:22.000000000 +0000 @@ -28,6 +28,7 @@ #include "drm.h" #include "i915_drm.h" @@ -47571,7 +47489,7 @@ static bool i915_pipe_enabled(struct drm_device *dev, enum pipe pipe) { -@@ -39,7 +40,7 @@ static bool i915_pipe_enabled(struct drm_device *dev, enum pipe pipe) +@@ -39,7 +40,7 @@ return false; if (HAS_PCH_SPLIT(dev)) @@ -47580,11 +47498,11 @@ else dpll_reg = (pipe == PIPE_A) ? _DPLL_A : _DPLL_B; -diff --git a/drivers/gpu/drm/i915/intel_acpi.c b/drivers/gpu/drm/i915/intel_acpi.c -index cb91210..bae3edf 100644 ---- a/drivers/gpu/drm/i915/intel_acpi.c -+++ b/drivers/gpu/drm/i915/intel_acpi.c -@@ -208,7 +208,7 @@ static bool intel_dsm_pci_probe(struct pci_dev *pdev) +Index: linux-3.2.46/drivers/gpu/drm/i915/intel_acpi.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/i915/intel_acpi.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/i915/intel_acpi.c 2013-07-26 19:26:22.000000000 +0000 +@@ -208,7 +208,7 @@ ret = intel_dsm(dhandle, INTEL_DSM_FN_SUPPORTED_FUNCTIONS, 0); if (ret < 0) { @@ -47593,11 +47511,11 @@ return false; } -diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c -index 0016fee..a2c9e56 100644 ---- a/drivers/gpu/drm/i915/intel_bios.c -+++ b/drivers/gpu/drm/i915/intel_bios.c -@@ -605,7 +605,7 @@ parse_device_mapping(struct drm_i915_private *dev_priv, +Index: linux-3.2.46/drivers/gpu/drm/i915/intel_bios.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/i915/intel_bios.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/i915/intel_bios.c 2013-07-26 19:26:22.000000000 +0000 +@@ -605,7 +605,7 @@ DRM_DEBUG_KMS("no child dev is parsed from VBT\n"); return; } @@ -47606,7 +47524,7 @@ if (!dev_priv->child_dev) { DRM_DEBUG_KMS("No memory space for child device\n"); return; -@@ -719,7 +719,7 @@ intel_parse_bios(struct drm_device *dev) +@@ -719,7 +719,7 @@ } if (!vbt) { @@ -47615,11 +47533,11 @@ pci_unmap_rom(pdev, bios); return -1; } -diff --git a/drivers/gpu/drm/i915/intel_bios.h b/drivers/gpu/drm/i915/intel_bios.h -index 8af3735..dbda6e3 100644 ---- a/drivers/gpu/drm/i915/intel_bios.h -+++ b/drivers/gpu/drm/i915/intel_bios.h -@@ -467,8 +467,12 @@ struct edp_link_params { +Index: linux-3.2.46/drivers/gpu/drm/i915/intel_bios.h +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/i915/intel_bios.h 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/i915/intel_bios.h 2013-07-26 19:26:22.000000000 +0000 +@@ -467,8 +467,12 @@ struct bdb_edp { struct edp_power_seq power_seqs[16]; u32 color_depth; @@ -47633,10 +47551,10 @@ } __attribute__ ((packed)); void intel_setup_bios(struct drm_device *dev); -diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c -index fee0ad0..342ffb7 100644 ---- a/drivers/gpu/drm/i915/intel_crt.c -+++ b/drivers/gpu/drm/i915/intel_crt.c +Index: linux-3.2.46/drivers/gpu/drm/i915/intel_crt.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/i915/intel_crt.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/i915/intel_crt.c 2013-07-26 19:26:22.000000000 +0000 @@ -24,6 +24,7 @@ * Eric Anholt */ @@ -47645,7 +47563,7 @@ #include #include #include "drmP.h" -@@ -265,6 +266,36 @@ static bool intel_crt_detect_hotplug(struct drm_connector *connector) +@@ -265,6 +266,36 @@ return ret; } @@ -47682,7 +47600,7 @@ static bool intel_crt_detect_ddc(struct drm_connector *connector) { struct intel_crt *crt = intel_attached_crt(connector); -@@ -278,7 +309,7 @@ static bool intel_crt_detect_ddc(struct drm_connector *connector) +@@ -278,7 +309,7 @@ struct edid *edid; bool is_digital = false; @@ -47691,7 +47609,7 @@ &dev_priv->gmbus[dev_priv->crt_ddc_pin].adapter); /* * This may be a DVI-I connector with a shared DDC -@@ -429,8 +460,8 @@ intel_crt_detect(struct drm_connector *connector, bool force) +@@ -429,8 +460,8 @@ { struct drm_device *dev = connector->dev; struct intel_crt *crt = intel_attached_crt(connector); @@ -47701,7 +47619,7 @@ if (I915_HAS_HOTPLUG(dev)) { if (intel_crt_detect_hotplug(connector)) { -@@ -449,23 +480,16 @@ intel_crt_detect(struct drm_connector *connector, bool force) +@@ -449,23 +480,16 @@ return connector->status; /* for pre-945g platforms use load detect */ @@ -47735,7 +47653,7 @@ return status; } -@@ -483,13 +507,13 @@ static int intel_crt_get_modes(struct drm_connector *connector) +@@ -483,13 +507,13 @@ struct drm_i915_private *dev_priv = dev->dev_private; int ret; @@ -47751,7 +47669,7 @@ &dev_priv->gmbus[GMBUS_PORT_DPB].adapter); } -@@ -540,6 +564,24 @@ static const struct drm_encoder_funcs intel_crt_enc_funcs = { +@@ -540,6 +564,24 @@ .destroy = intel_encoder_destroy, }; @@ -47776,7 +47694,7 @@ void intel_crt_init(struct drm_device *dev) { struct drm_connector *connector; -@@ -547,6 +589,10 @@ void intel_crt_init(struct drm_device *dev) +@@ -547,6 +589,10 @@ struct intel_connector *intel_connector; struct drm_i915_private *dev_priv = dev->dev_private; @@ -47787,7 +47705,7 @@ crt = kzalloc(sizeof(struct intel_crt), GFP_KERNEL); if (!crt) return; -@@ -571,7 +617,10 @@ void intel_crt_init(struct drm_device *dev) +@@ -571,7 +617,10 @@ 1 << INTEL_ANALOG_CLONE_BIT | 1 << INTEL_SDVO_LVDS_CLONE_BIT); crt->base.crtc_mask = (1 << 0) | (1 << 1); @@ -47799,10 +47717,10 @@ connector->doublescan_allowed = 0; drm_encoder_helper_add(&crt->base.base, &intel_crt_helper_funcs); -diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c -index cfbb893..84867a8 100644 ---- a/drivers/gpu/drm/i915/intel_display.c -+++ b/drivers/gpu/drm/i915/intel_display.c +Index: linux-3.2.46/drivers/gpu/drm/i915/intel_display.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/i915/intel_display.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/i915/intel_display.c 2013-07-26 19:26:22.000000000 +0000 @@ -25,7 +25,6 @@ */ @@ -47811,7 +47729,7 @@ #include #include #include -@@ -76,7 +75,7 @@ struct intel_limit { +@@ -76,7 +75,7 @@ intel_range_t dot, vco, n, m, m1, m2, p, p1; intel_p2_t p2; bool (* find_pll)(const intel_limit_t *, struct drm_crtc *, @@ -47820,7 +47738,7 @@ }; /* FDI */ -@@ -84,17 +83,21 @@ struct intel_limit { +@@ -84,17 +83,21 @@ static bool intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, @@ -47846,7 +47764,7 @@ static inline u32 /* units of 100MHz */ intel_fdi_link_freq(struct drm_device *dev) -@@ -535,7 +538,8 @@ static bool intel_PLL_is_valid(struct drm_device *dev, +@@ -535,7 +538,8 @@ static bool intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, @@ -47856,7 +47774,7 @@ { struct drm_device *dev = crtc->dev; -@@ -581,6 +585,9 @@ intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, +@@ -581,6 +585,9 @@ if (!intel_PLL_is_valid(dev, limit, &clock)) continue; @@ -47866,7 +47784,7 @@ this_err = abs(clock.dot - target); if (this_err < err) { -@@ -597,7 +604,8 @@ intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, +@@ -597,7 +604,8 @@ static bool intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, @@ -47876,7 +47794,7 @@ { struct drm_device *dev = crtc->dev; struct drm_i915_private *dev_priv = dev->dev_private; -@@ -644,6 +652,9 @@ intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, +@@ -644,6 +652,9 @@ if (!intel_PLL_is_valid(dev, limit, &clock)) continue; @@ -47886,7 +47804,7 @@ this_err = abs(clock.dot - target); if (this_err < err_most) { -@@ -661,7 +672,8 @@ intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc, +@@ -661,7 +672,8 @@ static bool intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc, @@ -47896,7 +47814,7 @@ { struct drm_device *dev = crtc->dev; intel_clock_t clock; -@@ -687,7 +699,8 @@ intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc, +@@ -687,7 +699,8 @@ /* DisplayPort has only two frequencies, 162MHz and 270MHz */ static bool intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc, @@ -47906,7 +47824,7 @@ { intel_clock_t clock; if (target < 200000) { -@@ -934,13 +947,17 @@ static void assert_panel_unlocked(struct drm_i915_private *dev_priv, +@@ -934,13 +947,17 @@ pipe_name(pipe)); } @@ -47926,7 +47844,7 @@ reg = PIPECONF(pipe); val = I915_READ(reg); cur_state = !!(val & PIPECONF_ENABLE); -@@ -948,22 +965,25 @@ static void assert_pipe(struct drm_i915_private *dev_priv, +@@ -948,22 +965,25 @@ "pipe %c assertion failure (expected %s, current %s)\n", pipe_name(pipe), state_string(state), state_string(cur_state)); } @@ -47959,7 +47877,7 @@ static void assert_planes_disabled(struct drm_i915_private *dev_priv, enum pipe pipe) { -@@ -972,8 +992,14 @@ static void assert_planes_disabled(struct drm_i915_private *dev_priv, +@@ -972,8 +992,14 @@ int cur_pipe; /* Planes are fixed to pipes on ILK+ */ @@ -47975,7 +47893,7 @@ /* Need to check both planes against the pipe */ for (i = 0; i < 2; i++) { -@@ -1225,7 +1251,8 @@ static void intel_disable_pch_pll(struct drm_i915_private *dev_priv, +@@ -1225,7 +1251,8 @@ enum pipe pipe) { int reg; @@ -47985,7 +47903,7 @@ if (pipe > 1) return; -@@ -1236,6 +1263,15 @@ static void intel_disable_pch_pll(struct drm_i915_private *dev_priv, +@@ -1236,6 +1263,15 @@ /* Make sure transcoder isn't still depending on us */ assert_transcoder_disabled(dev_priv, pipe); @@ -48001,7 +47919,7 @@ reg = PCH_DPLL(pipe); val = I915_READ(reg); val &= ~DPLL_VCO_ENABLE; -@@ -1248,7 +1284,8 @@ static void intel_enable_transcoder(struct drm_i915_private *dev_priv, +@@ -1248,7 +1284,8 @@ enum pipe pipe) { int reg; @@ -48011,7 +47929,7 @@ /* PCH only available on ILK+ */ BUG_ON(dev_priv->info->gen < 5); -@@ -1262,6 +1299,7 @@ static void intel_enable_transcoder(struct drm_i915_private *dev_priv, +@@ -1262,6 +1299,7 @@ reg = TRANSCONF(pipe); val = I915_READ(reg); @@ -48019,7 +47937,7 @@ if (HAS_PCH_IBX(dev_priv->dev)) { /* -@@ -1269,8 +1307,19 @@ static void intel_enable_transcoder(struct drm_i915_private *dev_priv, +@@ -1269,8 +1307,19 @@ * that in pipeconf reg. */ val &= ~PIPE_BPC_MASK; @@ -48040,7 +47958,7 @@ I915_WRITE(reg, val | TRANS_ENABLE); if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100)) DRM_ERROR("failed to enable transcoder %d\n", pipe); -@@ -1530,8 +1579,8 @@ static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval) +@@ -1530,8 +1579,8 @@ u32 fbc_ctl, fbc_ctl2; cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE; @@ -48051,7 +47969,7 @@ /* FBC_CTL wants 64B units */ cfb_pitch = (cfb_pitch / 64) - 1; -@@ -2023,6 +2072,8 @@ intel_pin_and_fence_fb_obj(struct drm_device *dev, +@@ -2023,6 +2072,8 @@ ret = i915_gem_object_get_fence(obj, pipelined); if (ret) goto err_unpin; @@ -48060,7 +47978,7 @@ } dev_priv->mm.interruptible = true; -@@ -2035,6 +2086,12 @@ err_interruptible: +@@ -2035,6 +2086,12 @@ return ret; } @@ -48073,7 +47991,7 @@ static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb, int x, int y) { -@@ -2092,11 +2149,11 @@ static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb, +@@ -2092,11 +2149,11 @@ I915_WRITE(reg, dspcntr); Start = obj->gtt_offset; @@ -48088,7 +48006,7 @@ if (INTEL_INFO(dev)->gen >= 4) { I915_WRITE(DSPSURF(plane), Start); I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); -@@ -2173,11 +2230,11 @@ static int ironlake_update_plane(struct drm_crtc *crtc, +@@ -2173,11 +2230,11 @@ I915_WRITE(reg, dspcntr); Start = obj->gtt_offset; @@ -48103,7 +48021,7 @@ I915_WRITE(DSPSURF(plane), Start); I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); I915_WRITE(DSPADDR(plane), Offset); -@@ -2276,7 +2333,7 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y, +@@ -2276,7 +2333,7 @@ ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y, LEAVE_ATOMIC_MODE_SET); if (ret) { @@ -48112,7 +48030,7 @@ mutex_unlock(&dev->struct_mutex); DRM_ERROR("failed to update base address\n"); return ret; -@@ -2284,7 +2341,7 @@ intel_pipe_set_base(struct drm_crtc *crtc, int x, int y, +@@ -2284,7 +2341,7 @@ if (old_fb) { intel_wait_for_vblank(dev, intel_crtc->pipe); @@ -48121,7 +48039,7 @@ } mutex_unlock(&dev->struct_mutex); -@@ -2428,9 +2485,11 @@ static void ironlake_fdi_link_train(struct drm_crtc *crtc) +@@ -2428,9 +2485,11 @@ udelay(150); /* Ironlake workaround, enable clock pointer after FDI enable*/ @@ -48136,7 +48054,7 @@ reg = FDI_RX_IIR(pipe); for (tries = 0; tries < 5; tries++) { -@@ -2943,6 +3002,7 @@ static void ironlake_pch_enable(struct drm_crtc *crtc) +@@ -2943,6 +3002,7 @@ I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe))); I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe))); I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe))); @@ -48144,7 +48062,7 @@ intel_fdi_normal_train(crtc); -@@ -3340,10 +3400,12 @@ static void intel_crtc_disable(struct drm_crtc *crtc) +@@ -3340,10 +3400,12 @@ struct drm_device *dev = crtc->dev; crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF); @@ -48158,7 +48076,7 @@ mutex_unlock(&dev->struct_mutex); } } -@@ -3417,10 +3479,10 @@ static bool intel_crtc_mode_fixup(struct drm_crtc *crtc, +@@ -3417,10 +3479,10 @@ return false; } @@ -48173,7 +48091,7 @@ drm_mode_set_crtcinfo(adjusted_mode, 0); return true; -@@ -4536,10 +4598,11 @@ static void ironlake_update_wm(struct drm_device *dev) +@@ -4536,10 +4598,11 @@ */ } @@ -48186,7 +48104,7 @@ int fbc_wm, plane_wm, cursor_wm; unsigned int enabled; -@@ -4548,8 +4611,10 @@ static void sandybridge_update_wm(struct drm_device *dev) +@@ -4548,8 +4611,10 @@ &sandybridge_display_wm_info, latency, &sandybridge_cursor_wm_info, latency, &plane_wm, &cursor_wm)) { @@ -48199,7 +48117,7 @@ DRM_DEBUG_KMS("FIFO watermarks For pipe A -" " plane %d, " "cursor: %d\n", plane_wm, cursor_wm); -@@ -4560,8 +4625,10 @@ static void sandybridge_update_wm(struct drm_device *dev) +@@ -4560,8 +4625,10 @@ &sandybridge_display_wm_info, latency, &sandybridge_cursor_wm_info, latency, &plane_wm, &cursor_wm)) { @@ -48212,7 +48130,7 @@ DRM_DEBUG_KMS("FIFO watermarks For pipe B -" " plane %d, cursor: %d\n", plane_wm, cursor_wm); -@@ -4574,8 +4641,10 @@ static void sandybridge_update_wm(struct drm_device *dev) +@@ -4574,8 +4641,10 @@ &sandybridge_display_wm_info, latency, &sandybridge_cursor_wm_info, latency, &plane_wm, &cursor_wm)) { @@ -48225,7 +48143,7 @@ DRM_DEBUG_KMS("FIFO watermarks For pipe C -" " plane %d, cursor: %d\n", plane_wm, cursor_wm); -@@ -4596,7 +4665,8 @@ static void sandybridge_update_wm(struct drm_device *dev) +@@ -4596,7 +4665,8 @@ I915_WRITE(WM2_LP_ILK, 0); I915_WRITE(WM1_LP_ILK, 0); @@ -48235,7 +48153,7 @@ return; enabled = ffs(enabled) - 1; -@@ -4646,6 +4716,161 @@ static void sandybridge_update_wm(struct drm_device *dev) +@@ -4646,6 +4716,161 @@ cursor_wm); } @@ -48397,7 +48315,7 @@ /** * intel_update_watermarks - update FIFO watermark values based on current modes * -@@ -4686,6 +4911,16 @@ static void intel_update_watermarks(struct drm_device *dev) +@@ -4686,6 +4911,16 @@ dev_priv->display.update_wm(dev); } @@ -48414,7 +48332,7 @@ static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) { if (i915_panel_use_ssc >= 0) -@@ -4833,6 +5068,82 @@ static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc, +@@ -4833,6 +5068,82 @@ return display_bpc != bpc; } @@ -48497,7 +48415,7 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *mode, struct drm_display_mode *adjusted_mode, -@@ -4846,7 +5157,7 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc, +@@ -4846,7 +5157,7 @@ int plane = intel_crtc->plane; int refclk, num_connectors = 0; intel_clock_t clock, reduced_clock; @@ -48506,7 +48424,7 @@ bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false; bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false; struct drm_mode_config *mode_config = &dev->mode_config; -@@ -4887,15 +5198,7 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc, +@@ -4887,15 +5198,7 @@ num_connectors++; } @@ -48523,7 +48441,7 @@ /* * Returns a set of divisors for the desired target clock with the given -@@ -4903,7 +5206,8 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc, +@@ -4903,7 +5206,8 @@ * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. */ limit = intel_limit(crtc, refclk); @@ -48533,7 +48451,7 @@ if (!ok) { DRM_ERROR("Couldn't find PLL settings for mode!\n"); return -EINVAL; -@@ -4913,53 +5217,24 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc, +@@ -4913,53 +5217,24 @@ intel_crtc_update_cursor(crtc, true); if (is_lvds && dev_priv->lvds_downclock_avail) { @@ -48599,7 +48517,7 @@ dpll = DPLL_VGA_MODE_DIS; -@@ -5033,8 +5308,6 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc, +@@ -5033,8 +5308,6 @@ /* Set up the display plane register */ dspcntr = DISPPLANE_GAMMA_ENABLE; @@ -48608,7 +48526,7 @@ if (pipe == 0) dspcntr &= ~DISPPLANE_SEL_PIPE_MASK; else -@@ -5069,7 +5342,6 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc, +@@ -5069,7 +5342,6 @@ DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B'); drm_mode_debug_printmodeline(mode); @@ -48616,7 +48534,7 @@ I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE); POSTING_READ(DPLL(pipe)); -@@ -5156,33 +5428,32 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc, +@@ -5156,33 +5428,32 @@ I915_WRITE(DPLL(pipe), dpll); } @@ -48665,7 +48583,7 @@ I915_WRITE(HTOTAL(pipe), (adjusted_mode->crtc_hdisplay - 1) | -@@ -5299,7 +5570,8 @@ void ironlake_init_pch_refclk(struct drm_device *dev) +@@ -5299,7 +5570,8 @@ if (intel_panel_use_ssc(dev_priv) && can_ssc) { DRM_DEBUG_KMS("Using SSC on panel\n"); temp |= DREF_SSC1_ENABLE; @@ -48675,7 +48593,7 @@ /* Get SSC going before enabling the outputs */ I915_WRITE(PCH_DREF_CONTROL, temp); -@@ -5448,7 +5720,8 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc, +@@ -5448,7 +5720,8 @@ * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. */ limit = intel_limit(crtc, refclk); @@ -48685,7 +48603,7 @@ if (!ok) { DRM_ERROR("Couldn't find PLL settings for mode!\n"); return -EINVAL; -@@ -5458,21 +5731,17 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc, +@@ -5458,21 +5731,17 @@ intel_crtc_update_cursor(crtc, true); if (is_lvds && dev_priv->lvds_downclock_avail) { @@ -48714,7 +48632,7 @@ } /* SDVO TV has fixed PLL values depend on its clock range, this mirrors vbios setting. */ -@@ -5767,17 +6036,19 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc, +@@ -5767,17 +6036,19 @@ } } @@ -48741,7 +48659,7 @@ I915_WRITE(HTOTAL(pipe), (adjusted_mode->crtc_hdisplay - 1) | -@@ -5820,12 +6091,6 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc, +@@ -5820,12 +6091,6 @@ intel_wait_for_vblank(dev, pipe); @@ -48754,7 +48672,7 @@ I915_WRITE(DSPCNTR(plane), dspcntr); POSTING_READ(DSPCNTR(plane)); -@@ -5852,14 +6117,45 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc, +@@ -5852,14 +6117,45 @@ ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode, x, y, old_fb); @@ -48802,7 +48720,7 @@ static void g4x_write_eld(struct drm_connector *connector, struct drm_crtc *crtc) { -@@ -5876,6 +6172,12 @@ static void g4x_write_eld(struct drm_connector *connector, +@@ -5876,6 +6172,12 @@ else eldv = G4X_ELDV_DEVCTG; @@ -48815,7 +48733,7 @@ i = I915_READ(G4X_AUD_CNTL_ST); i &= ~(eldv | G4X_ELD_ADDR); len = (i >> 9) & 0x1f; /* ELD buffer size */ -@@ -5903,22 +6205,26 @@ static void ironlake_write_eld(struct drm_connector *connector, +@@ -5903,22 +6205,26 @@ uint32_t i; int len; int hdmiw_hdmiedid; @@ -48827,14 +48745,15 @@ - hdmiw_hdmiedid = GEN5_HDMIW_HDMIEDID_A; - aud_cntl_st = GEN5_AUD_CNTL_ST_A; - aud_cntrl_st2 = GEN5_AUD_CNTL_ST2; +- } else { +- hdmiw_hdmiedid = GEN7_HDMIW_HDMIEDID_A; +- aud_cntl_st = GEN7_AUD_CNTRL_ST_A; +- aud_cntrl_st2 = GEN7_AUD_CNTRL_ST2; + hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID_A; + aud_config = IBX_AUD_CONFIG_A; + aud_cntl_st = IBX_AUD_CNTL_ST_A; + aud_cntrl_st2 = IBX_AUD_CNTL_ST2; - } else { -- hdmiw_hdmiedid = GEN7_HDMIW_HDMIEDID_A; -- aud_cntl_st = GEN7_AUD_CNTRL_ST_A; -- aud_cntrl_st2 = GEN7_AUD_CNTRL_ST2; ++ } else { + hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID_A; + aud_config = CPT_AUD_CONFIG_A; + aud_cntl_st = CPT_AUD_CNTL_ST_A; @@ -48848,7 +48767,7 @@ DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(i)); -@@ -5927,14 +6233,27 @@ static void ironlake_write_eld(struct drm_connector *connector, +@@ -5927,14 +6233,27 @@ if (!i) { DRM_DEBUG_DRIVER("Audio directed to unknown port\n"); /* operate blindly on all ports */ @@ -48880,7 +48799,7 @@ i = I915_READ(aud_cntrl_st2); i &= ~eldv; I915_WRITE(aud_cntrl_st2, i); -@@ -5942,13 +6261,8 @@ static void ironlake_write_eld(struct drm_connector *connector, +@@ -5942,13 +6261,8 @@ if (!eld[0]) return; @@ -48895,7 +48814,7 @@ I915_WRITE(aud_cntl_st, i); len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */ -@@ -6328,7 +6642,7 @@ static struct drm_display_mode load_detect_mode = { +@@ -6328,7 +6642,7 @@ static struct drm_framebuffer * intel_framebuffer_create(struct drm_device *dev, @@ -48904,7 +48823,7 @@ struct drm_i915_gem_object *obj) { struct intel_framebuffer *intel_fb; -@@ -6370,7 +6684,7 @@ intel_framebuffer_create_for_mode(struct drm_device *dev, +@@ -6370,7 +6684,7 @@ int depth, int bpp) { struct drm_i915_gem_object *obj; @@ -48913,7 +48832,7 @@ obj = i915_gem_alloc_object(dev, intel_framebuffer_size_for_mode(mode, bpp)); -@@ -6379,9 +6693,9 @@ intel_framebuffer_create_for_mode(struct drm_device *dev, +@@ -6379,9 +6693,9 @@ mode_cmd.width = mode->hdisplay; mode_cmd.height = mode->vdisplay; @@ -48926,7 +48845,7 @@ return intel_framebuffer_create(dev, &mode_cmd, obj); } -@@ -6402,11 +6716,11 @@ mode_fits_in_fbdev(struct drm_device *dev, +@@ -6402,11 +6716,11 @@ return NULL; fb = &dev_priv->fbdev->ifb.base; @@ -48941,7 +48860,7 @@ return NULL; return fb; -@@ -6738,9 +7052,7 @@ static void intel_increase_pllclock(struct drm_crtc *crtc) +@@ -6738,9 +7052,7 @@ if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) { DRM_DEBUG_DRIVER("upclocking LVDS\n"); @@ -48952,7 +48871,7 @@ dpll &= ~DISPLAY_RATE_SELECT_FPA1; I915_WRITE(dpll_reg, dpll); -@@ -6749,9 +7061,6 @@ static void intel_increase_pllclock(struct drm_crtc *crtc) +@@ -6749,9 +7061,6 @@ dpll = I915_READ(dpll_reg); if (dpll & DISPLAY_RATE_SELECT_FPA1) DRM_DEBUG_DRIVER("failed to upclock LVDS!\n"); @@ -48962,7 +48881,7 @@ } /* Schedule downclock */ -@@ -6764,9 +7073,6 @@ static void intel_decrease_pllclock(struct drm_crtc *crtc) +@@ -6764,9 +7073,6 @@ struct drm_device *dev = crtc->dev; drm_i915_private_t *dev_priv = dev->dev_private; struct intel_crtc *intel_crtc = to_intel_crtc(crtc); @@ -48972,7 +48891,7 @@ if (HAS_PCH_SPLIT(dev)) return; -@@ -6779,23 +7085,22 @@ static void intel_decrease_pllclock(struct drm_crtc *crtc) +@@ -6779,23 +7085,22 @@ * the manual case. */ if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) { @@ -49002,7 +48921,7 @@ } /** -@@ -6908,7 +7213,7 @@ static void intel_unpin_work_fn(struct work_struct *__work) +@@ -6908,7 +7213,7 @@ container_of(__work, struct intel_unpin_work, work); mutex_lock(&work->dev->struct_mutex); @@ -49011,7 +48930,7 @@ drm_gem_object_unreference(&work->pending_flip_obj->base); drm_gem_object_unreference(&work->old_fb_obj->base); -@@ -6936,18 +7241,11 @@ static void do_intel_finish_page_flip(struct drm_device *dev, +@@ -6936,18 +7241,11 @@ spin_lock_irqsave(&dev->event_lock, flags); work = intel_crtc->unpin_work; @@ -49031,7 +48950,7 @@ intel_crtc->unpin_work = NULL; if (work->event) { -@@ -7019,25 +7317,16 @@ void intel_prepare_page_flip(struct drm_device *dev, int plane) +@@ -7019,25 +7317,16 @@ to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]); unsigned long flags; @@ -49063,7 +48982,7 @@ static int intel_gen2_queue_flip(struct drm_device *dev, struct drm_crtc *crtc, struct drm_framebuffer *fb, -@@ -7054,7 +7343,7 @@ static int intel_gen2_queue_flip(struct drm_device *dev, +@@ -7054,7 +7343,7 @@ goto err; /* Offset into the new buffer for cases of shared fbs between CRTCs */ @@ -49072,7 +48991,7 @@ ret = BEGIN_LP_RING(6); if (ret) -@@ -7071,16 +7360,14 @@ static int intel_gen2_queue_flip(struct drm_device *dev, +@@ -7071,16 +7360,14 @@ OUT_RING(MI_NOOP); OUT_RING(MI_DISPLAY_FLIP | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); @@ -49092,7 +49011,7 @@ err: return ret; } -@@ -7101,7 +7388,7 @@ static int intel_gen3_queue_flip(struct drm_device *dev, +@@ -7101,7 +7388,7 @@ goto err; /* Offset into the new buffer for cases of shared fbs between CRTCs */ @@ -49101,7 +49020,7 @@ ret = BEGIN_LP_RING(6); if (ret) -@@ -7115,16 +7402,15 @@ static int intel_gen3_queue_flip(struct drm_device *dev, +@@ -7115,16 +7402,15 @@ OUT_RING(MI_NOOP); OUT_RING(MI_DISPLAY_FLIP_I915 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); @@ -49120,7 +49039,7 @@ err: return ret; } -@@ -7153,7 +7439,7 @@ static int intel_gen4_queue_flip(struct drm_device *dev, +@@ -7153,7 +7439,7 @@ */ OUT_RING(MI_DISPLAY_FLIP | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); @@ -49129,7 +49048,7 @@ OUT_RING(obj->gtt_offset | obj->tiling_mode); /* XXX Enabling the panel-fitter across page-flip is so far -@@ -7163,13 +7449,11 @@ static int intel_gen4_queue_flip(struct drm_device *dev, +@@ -7163,13 +7449,11 @@ pf = 0; pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; OUT_RING(pf | pipesrc); @@ -49144,7 +49063,7 @@ err: return ret; } -@@ -7194,19 +7478,23 @@ static int intel_gen6_queue_flip(struct drm_device *dev, +@@ -7194,19 +7478,23 @@ OUT_RING(MI_DISPLAY_FLIP | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); @@ -49173,7 +49092,7 @@ err: return ret; } -@@ -7253,16 +7541,14 @@ static int intel_gen7_queue_flip(struct drm_device *dev, +@@ -7253,16 +7541,14 @@ goto err_unpin; intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit); @@ -49192,7 +49111,7 @@ err: return ret; } -@@ -7557,10 +7843,9 @@ static void intel_setup_outputs(struct drm_device *dev) +@@ -7557,10 +7843,9 @@ struct drm_i915_private *dev_priv = dev->dev_private; struct intel_encoder *encoder; bool dpd_is_edp = false; @@ -49205,7 +49124,7 @@ if (!has_lvds && !HAS_PCH_SPLIT(dev)) { /* disable the panel fitter on everything but LVDS */ I915_WRITE(PFIT_CONTROL, 0); -@@ -7689,7 +7974,7 @@ static const struct drm_framebuffer_funcs intel_fb_funcs = { +@@ -7689,7 +7974,7 @@ int intel_framebuffer_init(struct drm_device *dev, struct intel_framebuffer *intel_fb, @@ -49214,7 +49133,7 @@ struct drm_i915_gem_object *obj) { int ret; -@@ -7697,21 +7982,27 @@ int intel_framebuffer_init(struct drm_device *dev, +@@ -7697,21 +7982,27 @@ if (obj->tiling_mode == I915_TILING_Y) return -EINVAL; @@ -49228,6 +49147,10 @@ - /* Only pre-ILK can handle 5:5:5 */ - if (mode_cmd->depth == 15 && !HAS_PCH_SPLIT(dev)) - return -EINVAL; +- break; +- +- case 24: +- case 32: + switch (mode_cmd->pixel_format) { + case DRM_FORMAT_RGB332: + case DRM_FORMAT_RGB565: @@ -49237,10 +49160,7 @@ + case DRM_FORMAT_XRGB2101010: + case DRM_FORMAT_ARGB2101010: + /* RGB formats are common across chipsets */ - break; -- -- case 24: -- case 32: ++ break; + case DRM_FORMAT_YUYV: + case DRM_FORMAT_UYVY: + case DRM_FORMAT_YVYU: @@ -49252,7 +49172,7 @@ return -EINVAL; } -@@ -7729,11 +8020,12 @@ int intel_framebuffer_init(struct drm_device *dev, +@@ -7729,11 +8020,12 @@ static struct drm_framebuffer * intel_user_framebuffer_create(struct drm_device *dev, struct drm_file *filp, @@ -49267,7 +49187,7 @@ if (&obj->base == NULL) return ERR_PTR(-ENOENT); -@@ -8002,7 +8294,7 @@ void intel_init_emon(struct drm_device *dev) +@@ -8002,7 +8294,7 @@ dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK); } @@ -49276,7 +49196,7 @@ { /* * Respect the kernel parameter if it is set -@@ -8020,11 +8312,11 @@ static bool intel_enable_rc6(struct drm_device *dev) +@@ -8020,11 +8312,11 @@ * Disable rc6 on Sandybridge */ if (INTEL_INFO(dev)->gen == 6) { @@ -49292,7 +49212,7 @@ } void gen6_enable_rps(struct drm_i915_private *dev_priv) -@@ -8032,7 +8324,9 @@ void gen6_enable_rps(struct drm_i915_private *dev_priv) +@@ -8032,7 +8324,9 @@ u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS); u32 pcu_mbox, rc6_mask = 0; @@ -49302,7 +49222,7 @@ int i; /* Here begins a magic sequence of register writes to enable -@@ -8043,6 +8337,13 @@ void gen6_enable_rps(struct drm_i915_private *dev_priv) +@@ -8043,6 +8337,13 @@ */ I915_WRITE(GEN6_RC_STATE, 0); mutex_lock(&dev_priv->dev->struct_mutex); @@ -49316,7 +49236,7 @@ gen6_gt_force_wake_get(dev_priv); /* disable the counters and set deterministic thresholds */ -@@ -8063,9 +8364,20 @@ void gen6_enable_rps(struct drm_i915_private *dev_priv) +@@ -8063,9 +8364,20 @@ I915_WRITE(GEN6_RC6p_THRESHOLD, 150000); I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */ @@ -49340,7 +49260,7 @@ I915_WRITE(GEN6_RC_CONTROL, rc6_mask | -@@ -8293,6 +8605,10 @@ static void gen6_init_clock_gating(struct drm_device *dev) +@@ -8293,6 +8605,10 @@ I915_WRITE(WM2_LP_ILK, 0); I915_WRITE(WM1_LP_ILK, 0); @@ -49351,7 +49271,7 @@ /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock * gating disable must be set. Failure to set it results in * flickering pixels due to Z write ordering failures after -@@ -8371,6 +8687,10 @@ static void ivybridge_init_clock_gating(struct drm_device *dev) +@@ -8371,6 +8687,10 @@ I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE); @@ -49362,7 +49282,7 @@ /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */ I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1, GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC); -@@ -8681,9 +9001,15 @@ static void intel_init_display(struct drm_device *dev) +@@ -8681,9 +9001,15 @@ if (IS_IVYBRIDGE(dev)) { u32 ecobus; @@ -49379,7 +49299,7 @@ __gen6_gt_force_wake_mt_put(dev_priv); mutex_unlock(&dev->struct_mutex); -@@ -8715,6 +9041,7 @@ static void intel_init_display(struct drm_device *dev) +@@ -8715,6 +9041,7 @@ } else if (IS_GEN6(dev)) { if (SNB_READ_WM0_LATENCY()) { dev_priv->display.update_wm = sandybridge_update_wm; @@ -49387,7 +49307,7 @@ } else { DRM_DEBUG_KMS("Failed to read display plane latency. " "Disable CxSR\n"); -@@ -8728,6 +9055,7 @@ static void intel_init_display(struct drm_device *dev) +@@ -8728,6 +9055,7 @@ dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; if (SNB_READ_WM0_LATENCY()) { dev_priv->display.update_wm = sandybridge_update_wm; @@ -49395,7 +49315,7 @@ } else { DRM_DEBUG_KMS("Failed to read display plane latency. " "Disable CxSR\n"); -@@ -8832,16 +9160,6 @@ static void quirk_ssc_force_disable(struct drm_device *dev) +@@ -8832,16 +9160,6 @@ dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE; } @@ -49412,7 +49332,7 @@ struct intel_quirk { int device; int subsystem_vendor; -@@ -8849,37 +9167,7 @@ struct intel_quirk { +@@ -8849,37 +9167,7 @@ void (*hook)(struct drm_device *dev); }; @@ -49450,7 +49370,7 @@ /* HP Mini needs pipe A force quirk (LP: #322104) */ { 0x27ae, 0x103c, 0x361a, quirk_pipea_force }, -@@ -8904,18 +9192,6 @@ struct intel_quirk intel_quirks[] = { +@@ -8904,18 +9192,6 @@ /* Sony Vaio Y cannot use SSC on LVDS */ { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable }, @@ -49469,7 +49389,7 @@ }; static void intel_init_quirks(struct drm_device *dev) -@@ -8933,10 +9209,6 @@ static void intel_init_quirks(struct drm_device *dev) +@@ -8933,10 +9209,6 @@ q->subsystem_device == PCI_ANY_ID)) q->hook(dev); } @@ -49480,7 +49400,7 @@ } /* Disable the VGA plane that we never use */ -@@ -8962,33 +9234,19 @@ static void i915_disable_vga(struct drm_device *dev) +@@ -8962,33 +9234,19 @@ POSTING_READ(vga_reg); } @@ -49518,7 +49438,7 @@ dev->mode_config.funcs = (void *)&intel_mode_funcs; intel_init_quirks(dev); -@@ -9012,6 +9270,9 @@ void intel_modeset_init(struct drm_device *dev) +@@ -9012,6 +9270,9 @@ for (i = 0; i < dev_priv->num_pipe; i++) { intel_crtc_init(dev, i); @@ -49528,7 +49448,7 @@ } /* Just disable it once at startup */ -@@ -9093,9 +9354,6 @@ void intel_modeset_cleanup(struct drm_device *dev) +@@ -9093,9 +9354,6 @@ del_timer_sync(&dev_priv->idle_timer); cancel_work_sync(&dev_priv->idle_work); @@ -49538,11 +49458,11 @@ drm_mode_config_cleanup(dev); } -diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c -index a07ccab..069725c 100644 ---- a/drivers/gpu/drm/i915/intel_dp.c -+++ b/drivers/gpu/drm/i915/intel_dp.c -@@ -49,7 +49,7 @@ struct intel_dp { +Index: linux-3.2.46/drivers/gpu/drm/i915/intel_dp.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/i915/intel_dp.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/i915/intel_dp.c 2013-07-26 19:26:22.000000000 +0000 +@@ -49,7 +49,7 @@ uint32_t DP; uint8_t link_configuration[DP_LINK_CONFIGURATION_SIZE]; bool has_audio; @@ -49551,7 +49471,7 @@ uint32_t color_range; int dpms_mode; uint8_t link_bw; -@@ -384,7 +384,7 @@ intel_dp_aux_ch(struct intel_dp *intel_dp, +@@ -384,7 +384,7 @@ else aux_clock_divider = 225; /* eDP input clock at 450Mhz */ } else if (HAS_PCH_SPLIT(dev)) @@ -49560,7 +49480,7 @@ else aux_clock_divider = intel_hrawclk(dev) / 2; -@@ -437,6 +437,10 @@ intel_dp_aux_ch(struct intel_dp *intel_dp, +@@ -437,6 +437,10 @@ DP_AUX_CH_CTL_DONE | DP_AUX_CH_CTL_TIME_OUT_ERROR | DP_AUX_CH_CTL_RECEIVE_ERROR); @@ -49571,7 +49491,7 @@ if (status & DP_AUX_CH_CTL_DONE) break; } -@@ -2137,8 +2141,8 @@ intel_dp_detect(struct drm_connector *connector, bool force) +@@ -2137,8 +2141,8 @@ if (status != connector_status_connected) return status; @@ -49582,7 +49502,7 @@ } else { edid = intel_dp_get_edid(connector, &intel_dp->adapter); if (edid) { -@@ -2238,10 +2242,10 @@ intel_dp_set_property(struct drm_connector *connector, +@@ -2238,10 +2242,10 @@ intel_dp->force_audio = i; @@ -49595,7 +49515,7 @@ if (has_audio == intel_dp->has_audio) return 0; -@@ -2274,6 +2278,11 @@ done: +@@ -2274,6 +2278,11 @@ static void intel_dp_destroy(struct drm_connector *connector) { @@ -49607,10 +49527,10 @@ drm_sysfs_connector_remove(connector); drm_connector_cleanup(connector); kfree(connector); -diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h -index 5212284..cd623e8 100644 ---- a/drivers/gpu/drm/i915/intel_drv.h -+++ b/drivers/gpu/drm/i915/intel_drv.h +Index: linux-3.2.46/drivers/gpu/drm/i915/intel_drv.h +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/i915/intel_drv.h 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/i915/intel_drv.h 2013-07-26 19:26:22.000000000 +0000 @@ -26,6 +26,7 @@ #define __INTEL_DRV_H__ @@ -49653,7 +49573,7 @@ static inline void intel_mode_set_pixel_multiplier(struct drm_display_mode *mode, -@@ -177,10 +175,32 @@ struct intel_crtc { +@@ -177,10 +175,32 @@ bool use_pll_a; }; @@ -49686,7 +49606,7 @@ #define DIP_HEADER_SIZE 5 -@@ -257,10 +277,7 @@ struct intel_unpin_work { +@@ -257,10 +277,7 @@ struct drm_i915_gem_object *old_fb_obj; struct drm_i915_gem_object *pending_flip_obj; struct drm_pending_vblank_event *event; @@ -49698,7 +49618,7 @@ bool enable_stall_check; }; -@@ -271,6 +288,8 @@ struct intel_fbc_work { +@@ -271,6 +288,8 @@ int interval; }; @@ -49707,7 +49627,7 @@ int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter); extern bool intel_ddc_probe(struct intel_encoder *intel_encoder, int ddc_bus); -@@ -293,6 +312,7 @@ intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode, +@@ -293,6 +312,7 @@ extern bool intel_dpd_is_edp(struct drm_device *dev); extern void intel_edp_link_config(struct intel_encoder *, int *, int *); extern bool intel_encoder_is_pch_edp(struct drm_encoder *encoder); @@ -49715,7 +49635,7 @@ /* intel_panel.c */ extern void intel_fixed_panel_mode(struct drm_display_mode *fixed_mode, -@@ -360,10 +380,11 @@ extern void intel_init_emon(struct drm_device *dev); +@@ -360,10 +380,11 @@ extern int intel_pin_and_fence_fb_obj(struct drm_device *dev, struct drm_i915_gem_object *obj, struct intel_ring_buffer *pipelined); @@ -49728,7 +49648,7 @@ struct drm_i915_gem_object *obj); extern int intel_fbdev_init(struct drm_device *dev); extern void intel_fbdev_fini(struct drm_device *dev); -@@ -383,9 +404,25 @@ extern int intel_overlay_attrs(struct drm_device *dev, void *data, +@@ -383,9 +404,25 @@ extern void intel_fb_output_poll_changed(struct drm_device *dev); extern void intel_fb_restore_mode(struct drm_device *dev); @@ -49754,11 +49674,11 @@ + struct drm_file *file_priv); + #endif /* __INTEL_DRV_H__ */ -diff --git a/drivers/gpu/drm/i915/intel_dvo.c b/drivers/gpu/drm/i915/intel_dvo.c -index 8ac91b8..69bea56 100644 ---- a/drivers/gpu/drm/i915/intel_dvo.c -+++ b/drivers/gpu/drm/i915/intel_dvo.c -@@ -157,7 +157,6 @@ static bool intel_dvo_mode_fixup(struct drm_encoder *encoder, +Index: linux-3.2.46/drivers/gpu/drm/i915/intel_dvo.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/i915/intel_dvo.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/i915/intel_dvo.c 2013-07-26 19:26:22.000000000 +0000 +@@ -157,7 +157,6 @@ C(vsync_end); C(vtotal); C(clock); @@ -49766,11 +49686,11 @@ #undef C } -diff --git a/drivers/gpu/drm/i915/intel_fb.c b/drivers/gpu/drm/i915/intel_fb.c -index d0ce34b..6e9ee33 100644 ---- a/drivers/gpu/drm/i915/intel_fb.c -+++ b/drivers/gpu/drm/i915/intel_fb.c -@@ -65,7 +65,7 @@ static int intelfb_create(struct intel_fbdev *ifbdev, +Index: linux-3.2.46/drivers/gpu/drm/i915/intel_fb.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/i915/intel_fb.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/i915/intel_fb.c 2013-07-26 19:26:22.000000000 +0000 +@@ -65,7 +65,7 @@ struct drm_i915_private *dev_priv = dev->dev_private; struct fb_info *info; struct drm_framebuffer *fb; @@ -49779,7 +49699,7 @@ struct drm_i915_gem_object *obj; struct device *device = &dev->pdev->dev; int size, ret; -@@ -77,11 +77,12 @@ static int intelfb_create(struct intel_fbdev *ifbdev, +@@ -77,11 +77,12 @@ mode_cmd.width = sizes->surface_width; mode_cmd.height = sizes->surface_height; @@ -49796,7 +49716,7 @@ size = ALIGN(size, PAGE_SIZE); obj = i915_gem_alloc_object(dev, size); if (!obj) { -@@ -148,14 +149,10 @@ static int intelfb_create(struct intel_fbdev *ifbdev, +@@ -148,14 +149,10 @@ // memset(info->screen_base, 0, size); @@ -49813,7 +49733,7 @@ DRM_DEBUG_KMS("allocated %dx%d fb: 0x%08x, bo %p\n", fb->width, fb->height, -@@ -279,8 +276,18 @@ void intel_fb_restore_mode(struct drm_device *dev) +@@ -279,8 +276,18 @@ { int ret; drm_i915_private_t *dev_priv = dev->dev_private; @@ -49832,11 +49752,11 @@ + + mutex_unlock(&dev->mode_config.mutex); } -diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c -index 497da2a..c60100d 100644 ---- a/drivers/gpu/drm/i915/intel_hdmi.c -+++ b/drivers/gpu/drm/i915/intel_hdmi.c -@@ -44,7 +44,7 @@ struct intel_hdmi { +Index: linux-3.2.46/drivers/gpu/drm/i915/intel_hdmi.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/i915/intel_hdmi.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/i915/intel_hdmi.c 2013-07-26 19:26:22.000000000 +0000 +@@ -44,7 +44,7 @@ uint32_t color_range; bool has_hdmi_sink; bool has_audio; @@ -49845,7 +49765,7 @@ void (*write_infoframe)(struct drm_encoder *encoder, struct dip_infoframe *frame); }; -@@ -143,9 +143,6 @@ static void i9xx_write_infoframe(struct drm_encoder *encoder, +@@ -143,9 +143,6 @@ I915_WRITE(VIDEO_DIP_DATA, *data); data++; } @@ -49855,7 +49775,7 @@ mmiowb(); flags |= intel_infoframe_flags(frame); -@@ -179,9 +176,6 @@ static void ironlake_write_infoframe(struct drm_encoder *encoder, +@@ -179,9 +176,6 @@ I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data); data++; } @@ -49865,7 +49785,7 @@ mmiowb(); flags |= intel_infoframe_flags(frame); -@@ -351,7 +345,9 @@ intel_hdmi_detect(struct drm_connector *connector, bool force) +@@ -351,7 +345,9 @@ if (edid) { if (edid->input & DRM_EDID_INPUT_DIGITAL) { status = connector_status_connected; @@ -49876,7 +49796,7 @@ intel_hdmi->has_audio = drm_detect_monitor_audio(edid); } connector->display_info.raw_edid = NULL; -@@ -359,8 +355,9 @@ intel_hdmi_detect(struct drm_connector *connector, bool force) +@@ -359,8 +355,9 @@ } if (status == connector_status_connected) { @@ -49888,7 +49808,7 @@ } return status; -@@ -414,7 +411,7 @@ intel_hdmi_set_property(struct drm_connector *connector, +@@ -414,7 +411,7 @@ return ret; if (property == dev_priv->force_audio_property) { @@ -49897,7 +49817,7 @@ bool has_audio; if (i == intel_hdmi->force_audio) -@@ -422,13 +419,13 @@ intel_hdmi_set_property(struct drm_connector *connector, +@@ -422,13 +419,13 @@ intel_hdmi->force_audio = i; @@ -49915,7 +49835,7 @@ intel_hdmi->has_audio = has_audio; goto done; -@@ -526,7 +523,7 @@ void intel_hdmi_init(struct drm_device *dev, int sdvox_reg) +@@ -526,7 +523,7 @@ intel_encoder->type = INTEL_OUTPUT_HDMI; connector->polled = DRM_CONNECTOR_POLL_HPD; @@ -49924,10 +49844,10 @@ connector->doublescan_allowed = 0; intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); -diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c -index d30cccc..8fdc957 100644 ---- a/drivers/gpu/drm/i915/intel_i2c.c -+++ b/drivers/gpu/drm/i915/intel_i2c.c +Index: linux-3.2.46/drivers/gpu/drm/i915/intel_i2c.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/i915/intel_i2c.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/i915/intel_i2c.c 2013-07-26 19:26:22.000000000 +0000 @@ -37,7 +37,7 @@ /* Intel GPIO access functions */ @@ -49937,7 +49857,7 @@ static inline struct intel_gmbus * to_intel_gmbus(struct i2c_adapter *i2c) -@@ -45,13 +45,6 @@ to_intel_gmbus(struct i2c_adapter *i2c) +@@ -45,13 +45,6 @@ return container_of(i2c, struct intel_gmbus, adapter); } @@ -49951,7 +49871,7 @@ void intel_i2c_reset(struct drm_device *dev) { -@@ -78,15 +71,15 @@ static void intel_i2c_quirk_set(struct drm_i915_private *dev_priv, bool enable) +@@ -78,15 +71,15 @@ I915_WRITE(DSPCLK_GATE_D, val); } @@ -49970,7 +49890,7 @@ (GPIO_DATA_PULLUP_DISABLE | GPIO_CLOCK_PULLUP_DISABLE); -@@ -95,29 +88,29 @@ static u32 get_reserved(struct intel_gpio *gpio) +@@ -95,29 +88,29 @@ static int get_clock(void *data) { @@ -50015,7 +49935,7 @@ u32 clock_bits; if (state_high) -@@ -126,15 +119,15 @@ static void set_clock(void *data, int state_high) +@@ -126,15 +119,15 @@ clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK | GPIO_CLOCK_VAL_MASK; @@ -50036,7 +49956,7 @@ u32 data_bits; if (state_high) -@@ -143,13 +136,14 @@ static void set_data(void *data, int state_high) +@@ -143,13 +136,14 @@ data_bits = GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK | GPIO_DATA_VAL_MASK; @@ -50055,7 +49975,7 @@ static const int map_pin_to_reg[] = { 0, GPIOB, -@@ -160,65 +154,48 @@ intel_gpio_create(struct drm_i915_private *dev_priv, u32 pin) +@@ -160,65 +154,48 @@ 0, GPIOF, }; @@ -50076,7 +49996,17 @@ if (HAS_PCH_SPLIT(dev_priv->dev)) - gpio->reg += PCH_GPIOA - GPIOA; - gpio->dev_priv = dev_priv; -- ++ bus->gpio_reg += PCH_GPIOA - GPIOA; ++ ++ bus->adapter.algo_data = algo; ++ algo->setsda = set_data; ++ algo->setscl = set_clock; ++ algo->getsda = get_data; ++ algo->getscl = get_clock; ++ algo->udelay = I2C_RISEFALL_TIME; ++ algo->timeout = usecs_to_jiffies(2200); ++ algo->data = bus; + - snprintf(gpio->adapter.name, sizeof(gpio->adapter.name), - "i915 GPIO%c", "?BACDE?F"[pin]); - gpio->adapter.owner = THIS_MODULE; @@ -50098,17 +50028,6 @@ -out_free: - kfree(gpio); - return NULL; -+ bus->gpio_reg += PCH_GPIOA - GPIOA; -+ -+ bus->adapter.algo_data = algo; -+ algo->setsda = set_data; -+ algo->setscl = set_clock; -+ algo->getsda = get_data; -+ algo->getscl = get_clock; -+ algo->udelay = I2C_RISEFALL_TIME; -+ algo->timeout = usecs_to_jiffies(2200); -+ algo->data = bus; -+ + return true; } @@ -50144,7 +50063,7 @@ intel_i2c_quirk_set(dev_priv, false); return ret; -@@ -232,12 +209,15 @@ gmbus_xfer(struct i2c_adapter *adapter, +@@ -232,12 +209,15 @@ struct intel_gmbus *bus = container_of(adapter, struct intel_gmbus, adapter); @@ -50152,12 +50071,12 @@ - int i, reg_offset; + struct drm_i915_private *dev_priv = bus->dev_priv; + int i, reg_offset, ret; ++ ++ mutex_lock(&dev_priv->gmbus_mutex); - if (bus->force_bit) - return intel_i2c_quirk_xfer(dev_priv, - bus->force_bit, msgs, num); -+ mutex_lock(&dev_priv->gmbus_mutex); -+ + if (bus->force_bit) { + ret = intel_i2c_quirk_xfer(bus, msgs, num); + goto out; @@ -50165,7 +50084,7 @@ reg_offset = HAS_PCH_SPLIT(dev_priv->dev) ? PCH_GMBUS0 - GMBUS0 : 0; -@@ -249,7 +229,8 @@ gmbus_xfer(struct i2c_adapter *adapter, +@@ -249,7 +229,8 @@ if (msgs[i].flags & I2C_M_RD) { I915_WRITE(GMBUS1 + reg_offset, @@ -50175,7 +50094,7 @@ (len << GMBUS_BYTE_COUNT_SHIFT) | (msgs[i].addr << GMBUS_SLAVE_ADDR_SHIFT) | GMBUS_SLAVE_READ | GMBUS_SW_RDY); -@@ -278,7 +259,8 @@ gmbus_xfer(struct i2c_adapter *adapter, +@@ -278,7 +259,8 @@ I915_WRITE(GMBUS3 + reg_offset, val); I915_WRITE(GMBUS1 + reg_offset, @@ -50185,7 +50104,7 @@ (msgs[i].len << GMBUS_BYTE_COUNT_SHIFT) | (msgs[i].addr << GMBUS_SLAVE_ADDR_SHIFT) | GMBUS_SLAVE_WRITE | GMBUS_SW_RDY); -@@ -317,11 +299,15 @@ clear_err: +@@ -317,11 +299,15 @@ I915_WRITE(GMBUS1 + reg_offset, 0); done: @@ -50204,7 +50123,7 @@ timeout: DRM_INFO("GMBUS timed out, falling back to bit banging on pin %d [%s]\n", -@@ -329,23 +315,21 @@ timeout: +@@ -329,23 +315,21 @@ I915_WRITE(GMBUS0 + reg_offset, 0); /* Hardware may not support GMBUS over these pins? Try GPIO bitbanging instead. */ @@ -50239,7 +50158,7 @@ /* I2C_FUNC_10BIT_ADDR | */ I2C_FUNC_SMBUS_READ_BLOCK_DATA | I2C_FUNC_SMBUS_BLOCK_PROC_CALL); -@@ -375,11 +359,13 @@ int intel_setup_gmbus(struct drm_device *dev) +@@ -375,11 +359,13 @@ struct drm_i915_private *dev_priv = dev->dev_private; int ret, i; @@ -50254,7 +50173,7 @@ for (i = 0; i < GMBUS_NUM_PORTS; i++) { struct intel_gmbus *bus = &dev_priv->gmbus[i]; -@@ -391,7 +377,7 @@ int intel_setup_gmbus(struct drm_device *dev) +@@ -391,7 +377,7 @@ names[i]); bus->adapter.dev.parent = &dev->pdev->dev; @@ -50263,7 +50182,7 @@ bus->adapter.algo = &gmbus_algorithm; ret = i2c_add_adapter(&bus->adapter); -@@ -401,8 +387,11 @@ int intel_setup_gmbus(struct drm_device *dev) +@@ -401,8 +387,11 @@ /* By default use a conservative clock rate */ bus->reg0 = i | GMBUS_RATE_100KHZ; @@ -50276,7 +50195,7 @@ } intel_i2c_reset(dev_priv->dev); -@@ -430,19 +419,8 @@ void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit) +@@ -430,19 +419,8 @@ { struct intel_gmbus *bus = to_intel_gmbus(adapter); @@ -50298,7 +50217,7 @@ } void intel_teardown_gmbus(struct drm_device *dev) -@@ -455,10 +433,6 @@ void intel_teardown_gmbus(struct drm_device *dev) +@@ -455,10 +433,6 @@ for (i = 0; i < GMBUS_NUM_PORTS; i++) { struct intel_gmbus *bus = &dev_priv->gmbus[i]; @@ -50309,11 +50228,11 @@ i2c_del_adapter(&bus->adapter); } -diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c -index 876bac0..1ad5906 100644 ---- a/drivers/gpu/drm/i915/intel_lvds.c -+++ b/drivers/gpu/drm/i915/intel_lvds.c -@@ -187,6 +187,8 @@ centre_horizontally(struct drm_display_mode *mode, +Index: linux-3.2.46/drivers/gpu/drm/i915/intel_lvds.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/i915/intel_lvds.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/i915/intel_lvds.c 2013-07-26 19:26:22.000000000 +0000 +@@ -187,6 +187,8 @@ mode->crtc_hsync_start = mode->crtc_hblank_start + sync_pos; mode->crtc_hsync_end = mode->crtc_hsync_start + sync_width; @@ -50322,7 +50241,7 @@ } static void -@@ -208,6 +210,8 @@ centre_vertically(struct drm_display_mode *mode, +@@ -208,6 +210,8 @@ mode->crtc_vsync_start = mode->crtc_vblank_start + sync_pos; mode->crtc_vsync_end = mode->crtc_vsync_start + sync_width; @@ -50331,7 +50250,7 @@ } static inline u32 panel_fitter_scaling(u32 source, u32 target) -@@ -283,6 +287,8 @@ static bool intel_lvds_mode_fixup(struct drm_encoder *encoder, +@@ -283,6 +287,8 @@ for_each_pipe(pipe) I915_WRITE(BCLRPAT(pipe), 0); @@ -50340,7 +50259,7 @@ switch (intel_lvds->fitting_mode) { case DRM_MODE_SCALE_CENTER: /* -@@ -535,7 +541,6 @@ static int intel_lid_notify(struct notifier_block *nb, unsigned long val, +@@ -535,7 +541,6 @@ mutex_lock(&dev->mode_config.mutex); drm_helper_resume_force_mode(dev); @@ -50348,7 +50267,7 @@ mutex_unlock(&dev->mode_config.mutex); return NOTIFY_OK; -@@ -553,6 +558,8 @@ static void intel_lvds_destroy(struct drm_connector *connector) +@@ -553,6 +558,8 @@ struct drm_device *dev = connector->dev; struct drm_i915_private *dev_priv = dev->dev_private; @@ -50357,7 +50276,7 @@ if (dev_priv->lid_notifier.notifier_call) acpi_lid_notifier_unregister(&dev_priv->lid_notifier); drm_sysfs_connector_remove(connector); -@@ -899,6 +906,18 @@ static bool lvds_is_present_in_vbt(struct drm_device *dev, +@@ -899,6 +906,18 @@ return false; } @@ -50376,7 +50295,7 @@ /** * intel_lvds_init - setup LVDS connectors on this device * @dev: drm device -@@ -920,6 +939,9 @@ bool intel_lvds_init(struct drm_device *dev) +@@ -920,6 +939,9 @@ int pipe; u8 pin; @@ -50386,10 +50305,10 @@ /* Skip init on machines we know falsely report LVDS */ if (dmi_check_system(intel_no_lvds)) return false; -diff --git a/drivers/gpu/drm/i915/intel_modes.c b/drivers/gpu/drm/i915/intel_modes.c -index be2c6fe..9a2b270 100644 ---- a/drivers/gpu/drm/i915/intel_modes.c -+++ b/drivers/gpu/drm/i915/intel_modes.c +Index: linux-3.2.46/drivers/gpu/drm/i915/intel_modes.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/i915/intel_modes.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/i915/intel_modes.c 2013-07-26 19:26:22.000000000 +0000 @@ -28,6 +28,7 @@ #include #include @@ -50398,7 +50317,7 @@ #include "intel_drv.h" #include "i915_drv.h" -@@ -42,13 +43,13 @@ bool intel_ddc_probe(struct intel_encoder *intel_encoder, int ddc_bus) +@@ -42,13 +43,13 @@ u8 buf[2]; struct i2c_msg msgs[] = { { @@ -50414,7 +50333,7 @@ .flags = I2C_M_RD, .len = 1, .buf = buf, -@@ -59,6 +60,25 @@ bool intel_ddc_probe(struct intel_encoder *intel_encoder, int ddc_bus) +@@ -59,6 +60,25 @@ } /** @@ -50440,7 +50359,7 @@ * intel_ddc_get_modes - get modelist from monitor * @connector: DRM connector device to use * @adapter: i2c adapter -@@ -69,24 +89,19 @@ int intel_ddc_get_modes(struct drm_connector *connector, +@@ -69,24 +89,19 @@ struct i2c_adapter *adapter) { struct edid *edid; @@ -50473,7 +50392,7 @@ }; void -@@ -95,27 +110,24 @@ intel_attach_force_audio_property(struct drm_connector *connector) +@@ -95,27 +110,24 @@ struct drm_device *dev = connector->dev; struct drm_i915_private *dev_priv = dev->dev_private; struct drm_property *prop; @@ -50506,7 +50425,7 @@ }; void -@@ -124,19 +136,16 @@ intel_attach_broadcast_rgb_property(struct drm_connector *connector) +@@ -124,19 +136,16 @@ struct drm_device *dev = connector->dev; struct drm_i915_private *dev_priv = dev->dev_private; struct drm_property *prop; @@ -50528,10 +50447,10 @@ dev_priv->broadcast_rgb_property = prop; } -diff --git a/drivers/gpu/drm/i915/intel_overlay.c b/drivers/gpu/drm/i915/intel_overlay.c -index 478b51f..5ba5e66 100644 ---- a/drivers/gpu/drm/i915/intel_overlay.c -+++ b/drivers/gpu/drm/i915/intel_overlay.c +Index: linux-3.2.46/drivers/gpu/drm/i915/intel_overlay.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/i915/intel_overlay.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/i915/intel_overlay.c 2013-07-26 19:26:22.000000000 +0000 @@ -25,8 +25,6 @@ * * Derived from Xorg ddx, xf86-video-intel, src/i830_video.c @@ -50541,7 +50460,7 @@ #include "drmP.h" #include "drm.h" #include "i915_drm.h" -@@ -227,7 +225,8 @@ static int intel_overlay_do_wait_request(struct intel_overlay *overlay, +@@ -227,7 +225,8 @@ } overlay->last_flip_req = request->seqno; overlay->flip_tail = tail; @@ -50551,7 +50470,7 @@ if (ret) return ret; -@@ -263,7 +262,7 @@ i830_activate_pipe_a(struct drm_device *dev) +@@ -263,7 +262,7 @@ DRM_DEBUG_DRIVER("Enabling pipe A in order to enable overlay\n"); mode = drm_mode_duplicate(dev, &vesa_640x480); @@ -50560,7 +50479,7 @@ if (!drm_crtc_helper_set_mode(&crtc->base, mode, crtc->base.x, crtc->base.y, crtc->base.fb)) -@@ -456,7 +455,8 @@ static int intel_overlay_recover_from_interrupt(struct intel_overlay *overlay) +@@ -456,7 +455,8 @@ if (overlay->last_flip_req == 0) return 0; @@ -50570,7 +50489,7 @@ if (ret) return ret; -@@ -943,10 +943,10 @@ static int check_overlay_dst(struct intel_overlay *overlay, +@@ -943,10 +943,10 @@ { struct drm_display_mode *mode = &overlay->crtc->base.mode; @@ -50585,10 +50504,10 @@ return 0; else return -EINVAL; -diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c -index 04cb34a..48177ec 100644 ---- a/drivers/gpu/drm/i915/intel_panel.c -+++ b/drivers/gpu/drm/i915/intel_panel.c +Index: linux-3.2.46/drivers/gpu/drm/i915/intel_panel.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/i915/intel_panel.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/i915/intel_panel.c 2013-07-26 19:26:22.000000000 +0000 @@ -28,7 +28,6 @@ * Chris Wilson */ @@ -50597,7 +50516,7 @@ #include "intel_drv.h" #define PCI_LBPC 0xf4 /* legacy/combination backlight modes */ -@@ -48,8 +47,6 @@ intel_fixed_panel_mode(struct drm_display_mode *fixed_mode, +@@ -48,8 +47,6 @@ adjusted_mode->vtotal = fixed_mode->vtotal; adjusted_mode->clock = fixed_mode->clock; @@ -50606,7 +50525,7 @@ } /* adjusted_mode has been preset to be the panel's fixed mode */ -@@ -142,8 +139,8 @@ static u32 i915_read_blc_pwm_ctl(struct drm_i915_private *dev_priv) +@@ -142,8 +139,8 @@ dev_priv->saveBLC_PWM_CTL2 = val; } else if (val == 0) { I915_WRITE(BLC_PWM_PCH_CTL2, @@ -50617,7 +50536,7 @@ } } else { val = I915_READ(BLC_PWM_CTL); -@@ -192,27 +189,6 @@ u32 intel_panel_get_max_backlight(struct drm_device *dev) +@@ -192,27 +189,6 @@ return max; } @@ -50645,7 +50564,7 @@ u32 intel_panel_get_backlight(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; -@@ -233,7 +209,6 @@ u32 intel_panel_get_backlight(struct drm_device *dev) +@@ -233,7 +209,6 @@ } } @@ -50653,7 +50572,7 @@ DRM_DEBUG_DRIVER("get backlight PWM = %d\n", val); return val; } -@@ -251,7 +226,6 @@ static void intel_panel_actually_set_backlight(struct drm_device *dev, u32 level +@@ -251,7 +226,6 @@ u32 tmp; DRM_DEBUG_DRIVER("set backlight PWM = %d\n", level); @@ -50661,7 +50580,7 @@ if (HAS_PCH_SPLIT(dev)) return intel_pch_panel_set_backlight(dev, level); -@@ -361,9 +335,6 @@ int intel_panel_setup_backlight(struct drm_device *dev) +@@ -361,9 +335,6 @@ intel_panel_init_backlight(dev); @@ -50671,7 +50590,7 @@ if (dev_priv->int_lvds_connector) connector = dev_priv->int_lvds_connector; else if (dev_priv->int_edp_connector) -@@ -391,10 +362,8 @@ int intel_panel_setup_backlight(struct drm_device *dev) +@@ -391,10 +362,8 @@ void intel_panel_destroy_backlight(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; @@ -50683,11 +50602,11 @@ } #else int intel_panel_setup_backlight(struct drm_device *dev) -diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c -index 4fddd21..c17325c 100644 ---- a/drivers/gpu/drm/i915/intel_ringbuffer.c -+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c -@@ -263,6 +263,8 @@ static int init_ring_common(struct intel_ring_buffer *ring) +Index: linux-3.2.46/drivers/gpu/drm/i915/intel_ringbuffer.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/i915/intel_ringbuffer.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/i915/intel_ringbuffer.c 2013-07-26 19:26:22.000000000 +0000 +@@ -263,6 +263,8 @@ I915_WRITE_HEAD(ring, 0); ring->write_tail(ring, 0); @@ -50696,7 +50615,7 @@ head = I915_READ_HEAD(ring) & HEAD_ADDR; /* G45 ring initialization fails to reset head to zero */ -@@ -288,11 +290,6 @@ static int init_ring_common(struct intel_ring_buffer *ring) +@@ -288,11 +290,6 @@ } } @@ -50708,7 +50627,7 @@ I915_WRITE_CTL(ring, ((ring->size - PAGE_SIZE) & RING_NR_PAGES) | RING_VALID); -@@ -318,6 +315,7 @@ static int init_ring_common(struct intel_ring_buffer *ring) +@@ -318,6 +315,7 @@ ring->head = I915_READ_HEAD(ring); ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR; ring->space = ring_space(ring); @@ -50716,7 +50635,7 @@ } out: -@@ -399,25 +397,12 @@ static int init_render_ring(struct intel_ring_buffer *ring) +@@ -399,25 +397,12 @@ if (INTEL_INFO(dev)->gen > 3) { int mode = VS_TIMER_DISPATCH << 16 | VS_TIMER_DISPATCH; I915_WRITE(MI_MODE, mode); @@ -50746,7 +50665,7 @@ if (INTEL_INFO(dev)->gen >= 5) { ret = init_pipe_control(ring); if (ret) -@@ -620,6 +605,7 @@ pc_render_add_request(struct intel_ring_buffer *ring, +@@ -620,6 +605,7 @@ PIPE_CONTROL_FLUSH(ring, scratch_addr); scratch_addr += 128; PIPE_CONTROL_FLUSH(ring, scratch_addr); @@ -50754,7 +50673,7 @@ intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_WRITE_FLUSH | PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | -@@ -662,7 +648,7 @@ gen6_ring_get_seqno(struct intel_ring_buffer *ring) +@@ -662,7 +648,7 @@ /* Workaround to force correct ordering between irq and seqno writes on * ivb (and maybe also on snb) by reading from a CS register (like * ACTHD) before reading the status page. */ @@ -50763,7 +50682,7 @@ intel_ring_get_active_head(ring); return intel_read_status_page(ring, I915_GEM_HWS_INDEX); } -@@ -763,13 +749,13 @@ void intel_ring_setup_status_page(struct intel_ring_buffer *ring) +@@ -763,13 +749,13 @@ */ if (IS_GEN7(dev)) { switch (ring->id) { @@ -50780,7 +50699,7 @@ mmio = BSD_HWS_PGA_GEN7; break; } -@@ -835,8 +821,7 @@ gen6_ring_get_irq(struct intel_ring_buffer *ring, u32 gflag, u32 rflag) +@@ -835,8 +821,7 @@ /* It looks like we need to prevent the gt from suspending while waiting * for an notifiy irq, otherwise irqs seem to get lost on at least the * blt/bsd rings on ivb. */ @@ -50790,7 +50709,7 @@ spin_lock(&ring->irq_lock); if (ring->irq_refcount++ == 0) { -@@ -863,8 +848,7 @@ gen6_ring_put_irq(struct intel_ring_buffer *ring, u32 gflag, u32 rflag) +@@ -863,8 +848,7 @@ } spin_unlock(&ring->irq_lock); @@ -50800,7 +50719,7 @@ } static bool -@@ -1150,14 +1134,105 @@ static int intel_wrap_ring_buffer(struct intel_ring_buffer *ring) +@@ -1150,14 +1134,105 @@ return 0; } @@ -50907,7 +50826,7 @@ do { ring->head = I915_READ_HEAD(ring); ring->space = ring_space(ring); -@@ -1214,7 +1289,7 @@ void intel_ring_advance(struct intel_ring_buffer *ring) +@@ -1214,7 +1289,7 @@ static const struct intel_ring_buffer render_ring = { .name = "render ring", @@ -50916,7 +50835,7 @@ .mmio_base = RENDER_RING_BASE, .size = 32 * PAGE_SIZE, .init = init_render_ring, -@@ -1237,7 +1312,7 @@ static const struct intel_ring_buffer render_ring = { +@@ -1237,7 +1312,7 @@ static const struct intel_ring_buffer bsd_ring = { .name = "bsd ring", @@ -50925,7 +50844,7 @@ .mmio_base = BSD_RING_BASE, .size = 32 * PAGE_SIZE, .init = init_ring_common, -@@ -1347,7 +1422,7 @@ gen6_bsd_ring_put_irq(struct intel_ring_buffer *ring) +@@ -1347,7 +1422,7 @@ /* ring buffer for Video Codec for Gen6+ */ static const struct intel_ring_buffer gen6_bsd_ring = { .name = "gen6 bsd ring", @@ -50934,7 +50853,7 @@ .mmio_base = GEN6_BSD_RING_BASE, .size = 32 * PAGE_SIZE, .init = init_ring_common, -@@ -1383,79 +1458,13 @@ blt_ring_put_irq(struct intel_ring_buffer *ring) +@@ -1383,79 +1458,13 @@ GEN6_BLITTER_USER_INTERRUPT); } @@ -51015,7 +50934,7 @@ if (ret) return ret; -@@ -1470,22 +1479,12 @@ static int blt_ring_flush(struct intel_ring_buffer *ring, +@@ -1470,22 +1479,12 @@ return 0; } @@ -51040,7 +50959,7 @@ .write_tail = ring_write_tail, .flush = blt_ring_flush, .add_request = gen6_add_request, -@@ -1493,7 +1492,6 @@ static const struct intel_ring_buffer gen6_blt_ring = { +@@ -1493,7 +1492,6 @@ .irq_get = blt_ring_get_irq, .irq_put = blt_ring_put_irq, .dispatch_execbuffer = gen6_ring_dispatch_execbuffer, @@ -51048,10 +50967,10 @@ .sync_to = gen6_blt_ring_sync_to, .semaphore_register = {MI_SEMAPHORE_SYNC_BR, MI_SEMAPHORE_SYNC_BV, -diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h -index 68281c9..bc0365b 100644 ---- a/drivers/gpu/drm/i915/intel_ringbuffer.h -+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h +Index: linux-3.2.46/drivers/gpu/drm/i915/intel_ringbuffer.h +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/i915/intel_ringbuffer.h 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/i915/intel_ringbuffer.h 2013-07-26 19:26:22.000000000 +0000 @@ -1,13 +1,6 @@ #ifndef _INTEL_RINGBUFFER_H_ #define _INTEL_RINGBUFFER_H_ @@ -51066,7 +50985,7 @@ struct intel_hw_status_page { u32 __iomem *page_addr; unsigned int gfx_addr; -@@ -36,10 +29,11 @@ struct intel_hw_status_page { +@@ -36,10 +29,11 @@ struct intel_ring_buffer { const char *name; enum intel_ring_id { @@ -51081,7 +51000,7 @@ u32 mmio_base; void __iomem *virtual_start; struct drm_device *dev; -@@ -52,6 +46,16 @@ struct intel_ring_buffer { +@@ -52,6 +46,16 @@ int effective_size; struct intel_hw_status_page status_page; @@ -51098,7 +51017,7 @@ spinlock_t irq_lock; u32 irq_refcount; u32 irq_mask; -@@ -119,6 +123,12 @@ struct intel_ring_buffer { +@@ -119,6 +123,12 @@ void *private; }; @@ -51111,7 +51030,7 @@ static inline u32 intel_ring_sync_index(struct intel_ring_buffer *ring, struct intel_ring_buffer *other) -@@ -193,6 +203,11 @@ int intel_init_blt_ring_buffer(struct drm_device *dev); +@@ -193,6 +203,11 @@ u32 intel_ring_get_active_head(struct intel_ring_buffer *ring); void intel_ring_setup_status_page(struct intel_ring_buffer *ring); @@ -51123,11 +51042,11 @@ static inline void i915_trace_irq_get(struct intel_ring_buffer *ring, u32 seqno) { if (ring->trace_irq_seqno == 0 && ring->irq_get(ring)) -diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c -index 9e24670..1b6b157 100644 ---- a/drivers/gpu/drm/i915/intel_sdvo.c -+++ b/drivers/gpu/drm/i915/intel_sdvo.c -@@ -148,7 +148,7 @@ struct intel_sdvo_connector { +Index: linux-3.2.46/drivers/gpu/drm/i915/intel_sdvo.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/i915/intel_sdvo.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/i915/intel_sdvo.c 2013-07-26 19:26:22.000000000 +0000 +@@ -148,7 +148,7 @@ /* Mark the type of connector */ uint16_t output_flag; @@ -51136,7 +51055,7 @@ /* This contains all current supported TV format */ u8 tv_format_supported[TV_FORMAT_NUM]; -@@ -982,7 +982,6 @@ intel_sdvo_set_input_timings_for_mode(struct intel_sdvo *intel_sdvo, +@@ -982,7 +982,6 @@ intel_sdvo_get_mode_from_dtd(adjusted_mode, &intel_sdvo->input_dtd); @@ -51144,7 +51063,7 @@ return true; } -@@ -1351,8 +1350,8 @@ intel_sdvo_tmds_sink_detect(struct drm_connector *connector) +@@ -1351,8 +1350,8 @@ if (status == connector_status_connected) { struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); @@ -51155,7 +51074,7 @@ } return status; -@@ -1725,10 +1724,10 @@ intel_sdvo_set_property(struct drm_connector *connector, +@@ -1725,10 +1724,10 @@ intel_sdvo_connector->force_audio = i; @@ -51168,7 +51087,7 @@ if (has_audio == intel_sdvo->has_hdmi_audio) return 0; -@@ -2026,7 +2025,7 @@ intel_sdvo_connector_init(struct intel_sdvo_connector *connector, +@@ -2026,7 +2025,7 @@ drm_connector_helper_add(&connector->base.base, &intel_sdvo_connector_helper_funcs); @@ -51177,7 +51096,7 @@ connector->base.base.doublescan_allowed = 0; connector->base.base.display_info.subpixel_order = SubPixelHorizontalRGB; -@@ -2264,18 +2263,6 @@ intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags) +@@ -2264,18 +2263,6 @@ return true; } @@ -51196,7 +51115,7 @@ static bool intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo, struct intel_sdvo_connector *intel_sdvo_connector, int type) -@@ -2330,10 +2317,8 @@ static bool intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo, +@@ -2330,10 +2317,8 @@ intel_sdvo_connector->max_##name = data_value[0]; \ intel_sdvo_connector->cur_##name = response; \ intel_sdvo_connector->name = \ @@ -51208,7 +51127,7 @@ drm_connector_attach_property(connector, \ intel_sdvo_connector->name, \ intel_sdvo_connector->cur_##name); \ -@@ -2367,25 +2352,19 @@ intel_sdvo_create_enhance_property_tv(struct intel_sdvo *intel_sdvo, +@@ -2367,25 +2352,19 @@ intel_sdvo_connector->left_margin = data_value[0] - response; intel_sdvo_connector->right_margin = intel_sdvo_connector->left_margin; intel_sdvo_connector->left = @@ -51236,7 +51155,7 @@ drm_connector_attach_property(connector, intel_sdvo_connector->right, intel_sdvo_connector->right_margin); -@@ -2409,25 +2388,21 @@ intel_sdvo_create_enhance_property_tv(struct intel_sdvo *intel_sdvo, +@@ -2409,25 +2388,21 @@ intel_sdvo_connector->top_margin = data_value[0] - response; intel_sdvo_connector->bottom_margin = intel_sdvo_connector->top_margin; intel_sdvo_connector->top = @@ -51266,7 +51185,7 @@ drm_connector_attach_property(connector, intel_sdvo_connector->bottom, intel_sdvo_connector->bottom_margin); -@@ -2456,12 +2431,10 @@ intel_sdvo_create_enhance_property_tv(struct intel_sdvo *intel_sdvo, +@@ -2456,12 +2431,10 @@ intel_sdvo_connector->max_dot_crawl = 1; intel_sdvo_connector->cur_dot_crawl = response & 0x1; intel_sdvo_connector->dot_crawl = @@ -51280,7 +51199,7 @@ drm_connector_attach_property(connector, intel_sdvo_connector->dot_crawl, intel_sdvo_connector->cur_dot_crawl); -@@ -2608,8 +2581,7 @@ bool intel_sdvo_init(struct drm_device *dev, int sdvo_reg) +@@ -2608,8 +2581,7 @@ intel_sdvo->caps.output_flags) != true) { DRM_DEBUG_KMS("SDVO output failed to setup on SDVO%c\n", IS_SDVOB(sdvo_reg) ? 'B' : 'C'); @@ -51290,7 +51209,7 @@ } /* Only enable the hotplug irq if we need it, to work around noisy -@@ -2622,12 +2594,12 @@ bool intel_sdvo_init(struct drm_device *dev, int sdvo_reg) +@@ -2622,12 +2594,12 @@ /* Set the input timing to the screen. Assume always input 0. */ if (!intel_sdvo_set_target_input(intel_sdvo)) @@ -51305,7 +51224,7 @@ DRM_DEBUG_KMS("%s device VID/DID: %02X:%02X.%02X, " "clock range %dMHz - %dMHz, " -@@ -2647,9 +2619,6 @@ bool intel_sdvo_init(struct drm_device *dev, int sdvo_reg) +@@ -2647,9 +2619,6 @@ (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N'); return true; @@ -51315,10 +51234,10 @@ err: drm_encoder_cleanup(&intel_encoder->base); i2c_del_adapter(&intel_sdvo->ddc); -diff --git a/drivers/gpu/drm/i915/intel_sdvo_regs.h b/drivers/gpu/drm/i915/intel_sdvo_regs.h -index 4193c54..770bdd6 100644 ---- a/drivers/gpu/drm/i915/intel_sdvo_regs.h -+++ b/drivers/gpu/drm/i915/intel_sdvo_regs.h +Index: linux-3.2.46/drivers/gpu/drm/i915/intel_sdvo_regs.h +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/i915/intel_sdvo_regs.h 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/i915/intel_sdvo_regs.h 2013-07-26 19:26:22.000000000 +0000 @@ -1,5 +1,5 @@ /* - * Copyright © 2006-2007 Intel Corporation @@ -51326,11 +51245,10 @@ * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), -diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c -new file mode 100644 -index 0000000..e90dfb6 ---- /dev/null -+++ b/drivers/gpu/drm/i915/intel_sprite.c +Index: linux-3.2.46/drivers/gpu/drm/i915/intel_sprite.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/i915/intel_sprite.c 2013-07-26 19:26:22.000000000 +0000 @@ -0,0 +1,666 @@ +/* + * Copyright © 2011 Intel Corporation @@ -51998,11 +51916,11 @@ + return ret; +} + -diff --git a/drivers/gpu/drm/i915/intel_tv.c b/drivers/gpu/drm/i915/intel_tv.c -index 12041fa..c82b1d4 100644 ---- a/drivers/gpu/drm/i915/intel_tv.c -+++ b/drivers/gpu/drm/i915/intel_tv.c -@@ -674,7 +674,7 @@ static const struct tv_mode tv_modes[] = { +Index: linux-3.2.46/drivers/gpu/drm/i915/intel_tv.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/i915/intel_tv.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/i915/intel_tv.c 2013-07-26 19:26:22.000000000 +0000 +@@ -674,7 +674,7 @@ .filter_table = filter_table, }, { @@ -52011,7 +51929,7 @@ .clock = 107520, .refresh = 59940, .oversample = TV_OVERSAMPLE_4X, -@@ -698,30 +698,6 @@ static const struct tv_mode tv_modes[] = { +@@ -698,30 +698,6 @@ .filter_table = filter_table, }, { @@ -52042,7 +51960,7 @@ .name = "576p", .clock = 107520, .refresh = 50000, -@@ -731,7 +707,7 @@ static const struct tv_mode tv_modes[] = { +@@ -731,7 +707,7 @@ .hsync_end = 64, .hblank_end = 139, .hblank_start = 859, .htotal = 863, @@ -52051,7 +51969,7 @@ .vsync_start_f1 = 10, .vsync_start_f2 = 10, .vsync_len = 10, -@@ -770,30 +746,6 @@ static const struct tv_mode tv_modes[] = { +@@ -770,30 +746,6 @@ .filter_table = filter_table, }, { @@ -52082,7 +52000,7 @@ .name = "720p@50Hz", .clock = 148800, .refresh = 50000, -@@ -870,32 +822,6 @@ static const struct tv_mode tv_modes[] = { +@@ -870,32 +822,6 @@ .filter_table = filter_table, }, @@ -52115,7 +52033,7 @@ }; static struct intel_tv *enc_to_intel_tv(struct drm_encoder *encoder) -@@ -1367,7 +1293,7 @@ intel_tv_detect(struct drm_connector *connector, bool force) +@@ -1367,7 +1293,7 @@ int type; mode = reported_modes[0]; @@ -52124,11 +52042,11 @@ if (intel_tv->base.base.crtc && intel_tv->base.base.crtc->enabled) { type = intel_tv_detect_type(intel_tv, connector); -diff --git a/drivers/gpu/drm/mga/mga_dma.c b/drivers/gpu/drm/mga/mga_dma.c -index 5ccb65de..507aa3d 100644 ---- a/drivers/gpu/drm/mga/mga_dma.c -+++ b/drivers/gpu/drm/mga/mga_dma.c -@@ -403,6 +403,8 @@ int mga_driver_load(struct drm_device *dev, unsigned long flags) +Index: linux-3.2.46/drivers/gpu/drm/mga/mga_dma.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/mga/mga_dma.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/mga/mga_dma.c 2013-07-26 19:26:22.000000000 +0000 +@@ -403,6 +403,8 @@ dev_priv->usec_timeout = MGA_DEFAULT_USEC_TIMEOUT; dev_priv->chipset = flags; @@ -52137,11 +52055,11 @@ dev_priv->mmio_base = pci_resource_start(dev->pdev, 1); dev_priv->mmio_size = pci_resource_len(dev->pdev, 1); -diff --git a/drivers/gpu/drm/mga/mga_drv.c b/drivers/gpu/drm/mga/mga_drv.c -index 33daa29..f9a925d 100644 ---- a/drivers/gpu/drm/mga/mga_drv.c -+++ b/drivers/gpu/drm/mga/mga_drv.c -@@ -44,6 +44,20 @@ static struct pci_device_id pciidlist[] = { +Index: linux-3.2.46/drivers/gpu/drm/mga/mga_drv.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/mga/mga_drv.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/mga/mga_drv.c 2013-07-26 19:26:22.000000000 +0000 +@@ -44,6 +44,20 @@ mga_PCI_IDS }; @@ -52162,7 +52080,7 @@ static struct drm_driver driver = { .driver_features = DRIVER_USE_AGP | DRIVER_USE_MTRR | DRIVER_PCI_DMA | -@@ -64,20 +78,7 @@ static struct drm_driver driver = { +@@ -64,20 +78,7 @@ .reclaim_buffers = drm_core_reclaim_buffers, .ioctls = mga_ioctls, .dma_ioctl = mga_dma_buffers, @@ -52184,11 +52102,11 @@ .name = DRIVER_NAME, .desc = DRIVER_DESC, .date = DRIVER_DATE, -diff --git a/drivers/gpu/drm/nouveau/Kconfig b/drivers/gpu/drm/nouveau/Kconfig -index ca16399..97a8126 100644 ---- a/drivers/gpu/drm/nouveau/Kconfig -+++ b/drivers/gpu/drm/nouveau/Kconfig -@@ -13,6 +13,7 @@ config DRM_NOUVEAU +Index: linux-3.2.46/drivers/gpu/drm/nouveau/Kconfig +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/nouveau/Kconfig 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/nouveau/Kconfig 2013-07-26 19:26:22.000000000 +0000 +@@ -13,6 +13,7 @@ select ACPI_VIDEO if ACPI && X86 && BACKLIGHT_CLASS_DEVICE && VIDEO_OUTPUT_CONTROL && INPUT select ACPI_WMI if ACPI select MXM_WMI if ACPI @@ -52196,11 +52114,11 @@ help Choose this option for open-source nVidia support. -diff --git a/drivers/gpu/drm/nouveau/Makefile b/drivers/gpu/drm/nouveau/Makefile -index 35ef5b1..1a2ad7e 100644 ---- a/drivers/gpu/drm/nouveau/Makefile -+++ b/drivers/gpu/drm/nouveau/Makefile -@@ -9,19 +9,23 @@ nouveau-y := nouveau_drv.o nouveau_state.o nouveau_channel.o nouveau_mem.o \ +Index: linux-3.2.46/drivers/gpu/drm/nouveau/Makefile +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/nouveau/Makefile 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/nouveau/Makefile 2013-07-26 19:26:22.000000000 +0000 +@@ -9,19 +9,23 @@ nouveau_bo.o nouveau_fence.o nouveau_gem.o nouveau_ttm.o \ nouveau_hw.o nouveau_calc.o nouveau_bios.o nouveau_i2c.o \ nouveau_display.o nouveau_connector.o nouveau_fbcon.o \ @@ -52228,10 +52146,10 @@ nv04_instmem.o nv50_instmem.o nvc0_instmem.o \ nv04_dac.o nv04_dfp.o nv04_tv.o nv17_tv.o nv17_tv_modes.o \ nv04_crtc.o nv04_display.o nv04_cursor.o \ -diff --git a/drivers/gpu/drm/nouveau/nouveau_acpi.c b/drivers/gpu/drm/nouveau/nouveau_acpi.c -index 3df56c7..284bd25 100644 ---- a/drivers/gpu/drm/nouveau/nouveau_acpi.c -+++ b/drivers/gpu/drm/nouveau/nouveau_acpi.c +Index: linux-3.2.46/drivers/gpu/drm/nouveau/nouveau_acpi.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/nouveau/nouveau_acpi.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/nouveau/nouveau_acpi.c 2013-07-26 19:26:23.000000000 +0000 @@ -18,12 +18,6 @@ #include @@ -52255,7 +52173,7 @@ static struct nouveau_dsm_priv { bool dsm_detected; bool optimus_detected; -@@ -61,7 +58,8 @@ static int nouveau_optimus_dsm(acpi_handle handle, int func, int arg, uint32_t * +@@ -61,7 +58,8 @@ struct acpi_object_list input; union acpi_object params[4]; union acpi_object *obj; @@ -52265,7 +52183,7 @@ input.count = 4; input.pointer = params; -@@ -73,7 +71,11 @@ static int nouveau_optimus_dsm(acpi_handle handle, int func, int arg, uint32_t * +@@ -73,7 +71,11 @@ params[2].type = ACPI_TYPE_INTEGER; params[2].integer.value = func; params[3].type = ACPI_TYPE_BUFFER; @@ -52278,7 +52196,7 @@ err = acpi_evaluate_object(handle, "_DSM", &input, &output); if (err) { -@@ -148,6 +150,23 @@ static int nouveau_dsm(acpi_handle handle, int func, int arg, uint32_t *result) +@@ -148,6 +150,23 @@ return 0; } @@ -52302,7 +52220,7 @@ static int nouveau_dsm_switch_mux(acpi_handle handle, int mux_id) { mxm_wmi_call_mxmx(mux_id == NOUVEAU_DSM_LED_STAMINA ? MXM_MXDS_ADAPTER_IGD : MXM_MXDS_ADAPTER_0); -@@ -168,6 +187,10 @@ static int nouveau_dsm_set_discrete_state(acpi_handle handle, enum vga_switchero +@@ -168,6 +187,10 @@ static int nouveau_dsm_switchto(enum vga_switcheroo_client_id id) { @@ -52313,7 +52231,7 @@ if (id == VGA_SWITCHEROO_IGD) return nouveau_dsm_switch_mux(nouveau_dsm_priv.dhandle, NOUVEAU_DSM_LED_STAMINA); else -@@ -180,6 +203,11 @@ static int nouveau_dsm_power_state(enum vga_switcheroo_client_id id, +@@ -180,6 +203,11 @@ if (id == VGA_SWITCHEROO_IGD) return 0; @@ -52325,7 +52243,7 @@ return nouveau_dsm_set_discrete_state(nouveau_dsm_priv.dhandle, state); } -@@ -212,8 +240,7 @@ static int nouveau_dsm_pci_probe(struct pci_dev *pdev) +@@ -212,8 +240,7 @@ { acpi_handle dhandle, nvidia_handle; acpi_status status; @@ -52335,7 +52253,7 @@ dhandle = DEVICE_ACPI_HANDLE(&pdev->dev); if (!dhandle) -@@ -224,13 +251,11 @@ static int nouveau_dsm_pci_probe(struct pci_dev *pdev) +@@ -224,13 +251,11 @@ return false; } @@ -52352,7 +52270,7 @@ retval |= NOUVEAU_DSM_HAS_OPT; if (retval) -@@ -269,15 +294,22 @@ static bool nouveau_dsm_detect(void) +@@ -269,15 +294,22 @@ } if (vga_count == 2 && has_dsm && guid_valid) { @@ -52378,7 +52296,7 @@ return ret; } -@@ -293,6 +325,17 @@ void nouveau_register_dsm_handler(void) +@@ -293,6 +325,17 @@ vga_switcheroo_register_handler(&nouveau_dsm_handler); } @@ -52396,10 +52314,10 @@ void nouveau_unregister_dsm_handler(void) { vga_switcheroo_unregister_handler(); -diff --git a/drivers/gpu/drm/nouveau/nouveau_bios.c b/drivers/gpu/drm/nouveau/nouveau_bios.c -index 5fc201b..0be4a81 100644 ---- a/drivers/gpu/drm/nouveau/nouveau_bios.c -+++ b/drivers/gpu/drm/nouveau/nouveau_bios.c +Index: linux-3.2.46/drivers/gpu/drm/nouveau/nouveau_bios.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/nouveau/nouveau_bios.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/nouveau/nouveau_bios.c 2013-07-26 19:26:23.000000000 +0000 @@ -27,6 +27,7 @@ #include "nouveau_drv.h" #include "nouveau_hw.h" @@ -52418,7 +52336,7 @@ #define EDID1_LEN 128 -@@ -67,195 +65,233 @@ static bool nv_cksum(const uint8_t *data, unsigned int length) +@@ -67,195 +65,233 @@ } static int @@ -52567,14 +52485,27 @@ if (dev_priv->card_type >= NV_50) - nv_wr32(dev, 0x1700, old_bar0_pramin); + nv_wr32(dev, 0x001700, bar0); -+} -+ + } + +-static void load_vbios_pci(struct drm_device *dev, uint8_t *data) +static void +bios_shadow_pci(struct nvbios *bios) -+{ + { +- void __iomem *rom = NULL; +- size_t rom_len; +- int ret; +- +- ret = pci_enable_rom(dev->pdev); +- if (ret) +- return; + struct pci_dev *pdev = bios->dev->pdev; + size_t length; -+ + +- rom = pci_map_rom(dev->pdev, &rom_len); +- if (!rom) +- goto out; +- memcpy_fromio(data, rom, rom_len); +- pci_unmap_rom(dev->pdev, rom); + if (!pci_enable_rom(pdev)) { + void __iomem *rom = pci_map_rom(pdev, &length); + if (rom && length) { @@ -52586,69 +52517,55 @@ + } + if (rom) + pci_unmap_rom(pdev, rom); -+ + +-out: +- pci_disable_rom(dev->pdev); + pci_disable_rom(pdev); + } } --static void load_vbios_pci(struct drm_device *dev, uint8_t *data) +-static void load_vbios_acpi(struct drm_device *dev, uint8_t *data) +static void +bios_shadow_acpi(struct nvbios *bios) { -- void __iomem *rom = NULL; -- size_t rom_len; +- int i; - int ret; +- int size = 64 * 1024; + struct pci_dev *pdev = bios->dev->pdev; + int ptr, len, ret; + u8 data[3]; -- ret = pci_enable_rom(dev->pdev); -- if (ret) +- if (!nouveau_acpi_rom_supported(dev->pdev)) + if (!nouveau_acpi_rom_supported(pdev)) return; -- rom = pci_map_rom(dev->pdev, &rom_len); -- if (!rom) -- goto out; -- memcpy_fromio(data, rom, rom_len); -- pci_unmap_rom(dev->pdev, rom); +- for (i = 0; i < (size / ROM_BIOS_PAGE); i++) { +- ret = nouveau_acpi_get_bios_chunk(data, +- (i * ROM_BIOS_PAGE), +- ROM_BIOS_PAGE); +- if (ret <= 0) +- break; + ret = nouveau_acpi_get_bios_chunk(data, 0, sizeof(data)); + if (ret != sizeof(data)) + return; - --out: -- pci_disable_rom(dev->pdev); --} ++ + bios->length = min(data[2] * 512, 65536); + bios->data = kmalloc(bios->length, GFP_KERNEL); + if (!bios->data) + return; - --static void load_vbios_acpi(struct drm_device *dev, uint8_t *data) --{ -- int i; -- int ret; -- int size = 64 * 1024; ++ + len = bios->length; + ptr = 0; + while (len) { + int size = (len > ROM_BIOS_PAGE) ? ROM_BIOS_PAGE : len; - -- if (!nouveau_acpi_rom_supported(dev->pdev)) -- return; ++ + ret = nouveau_acpi_get_bios_chunk(bios->data, ptr, size); + if (ret != size) { + kfree(bios->data); + bios->data = NULL; + return; + } - -- for (i = 0; i < (size / ROM_BIOS_PAGE); i++) { -- ret = nouveau_acpi_get_bios_chunk(data, -- (i * ROM_BIOS_PAGE), -- ROM_BIOS_PAGE); -- if (ret <= 0) -- break; ++ + len -= size; + ptr += size; } @@ -52674,13 +52591,12 @@ -#define NUM_SHADOW_METHODS ARRAY_SIZE(shadow_methods) - -static bool NVShadowVBIOS(struct drm_device *dev, uint8_t *data) --{ ++static bool ++bios_shadow(struct drm_device *dev) + { - struct methods *methods = shadow_methods; - int testscore = 3; - int scores[NUM_SHADOW_METHODS], i; -+static bool -+bios_shadow(struct drm_device *dev) -+{ + struct methods shadow_methods[] = { + { "PRAMIN", bios_shadow_pramin, true, 0, 0, NULL }, + { "PROM", bios_shadow_prom, false, 0, 0, NULL }, @@ -52727,15 +52643,6 @@ - if (scores[i] == testscore) - return true; - } -- -- while (--testscore > 0) { -- for (i = 0; i < NUM_SHADOW_METHODS; i++) { -- if (scores[i] == testscore) { -- NV_TRACE(dev, "Using BIOS image from %s\n", -- methods[i].desc); -- methods[i].loadbios(dev, data); -- return true; -- } + mthd = shadow_methods; + do { + NV_TRACE(dev, "Checking %s for VBIOS\n", mthd->desc); @@ -52744,14 +52651,23 @@ + mthd->size = bios->length; + mthd->data = bios->data; + } while (mthd->score != 3 && (++mthd)->shadow); -+ + +- while (--testscore > 0) { +- for (i = 0; i < NUM_SHADOW_METHODS; i++) { +- if (scores[i] == testscore) { +- NV_TRACE(dev, "Using BIOS image from %s\n", +- methods[i].desc); +- methods[i].loadbios(dev, data); +- return true; +- } +- } + mthd = shadow_methods; + best = mthd; + do { + if (mthd->score > best->score) { + kfree(best->data); + best = mthd; - } ++ } + } while ((++mthd)->shadow); + + if (best->score) { @@ -52766,7 +52682,7 @@ return false; } -@@ -723,115 +759,19 @@ static int dcb_entry_idx_from_crtchead(struct drm_device *dev) +@@ -723,115 +759,19 @@ return dcb_entry; } @@ -52887,7 +52803,7 @@ return nouveau_i2c_find(dev, i2c_index); } -@@ -1199,17 +1139,14 @@ init_dp_condition(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) +@@ -1199,17 +1139,14 @@ switch (cond) { case 0: @@ -52909,7 +52825,7 @@ iexec->execute = false; break; case 5: -@@ -3227,49 +3164,6 @@ init_8d(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) +@@ -3227,49 +3164,6 @@ return 1; } @@ -52959,7 +52875,7 @@ static int init_gpio(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) { -@@ -3282,35 +3176,8 @@ init_gpio(struct nvbios *bios, uint16_t offset, struct init_exec *iexec) +@@ -3282,35 +3176,8 @@ * each GPIO according to various values listed in each entry */ @@ -52997,7 +52913,7 @@ return 1; } -@@ -4407,18 +4274,6 @@ int nouveau_bios_parse_lvds_table(struct drm_device *dev, int pxclk, bool *dl, b +@@ -4407,18 +4274,6 @@ break; } @@ -53016,7 +52932,7 @@ /* set dual_link flag for EDID case */ if (pxclk && (chip_version < 0x25 || chip_version > 0x28)) bios->fp.dual_link = (pxclk >= bios->fp.duallink_transition_clk); -@@ -4541,7 +4396,7 @@ nouveau_bios_run_display_table(struct drm_device *dev, u16 type, int pclk, +@@ -4541,7 +4396,7 @@ NV_DEBUG_KMS(dev, "Searching for output entry for %d %d %d\n", dcbent->type, dcbent->location, dcbent->or); for (i = 0; i < table[3]; i++) { @@ -53025,7 +52941,7 @@ if (otable && bios_encoder_match(dcbent, ROM32(otable[0]))) break; } -@@ -4719,7 +4574,7 @@ static struct pll_mapping nv84_pll_mapping[] = { +@@ -4719,7 +4574,7 @@ { PLL_CORE , 0x004028 }, { PLL_SHADER, 0x004020 }, { PLL_MEMORY, 0x004008 }, @@ -53034,7 +52950,7 @@ { PLL_UNK41 , 0x00e818 }, { PLL_VPLL0 , 0x614100 }, { PLL_VPLL1 , 0x614900 }, -@@ -5485,6 +5340,9 @@ bit_table(struct drm_device *dev, u8 id, struct bit_entry *bit) +@@ -5485,6 +5340,9 @@ struct nvbios *bios = &dev_priv->vbios; u8 entries, *entry; @@ -53044,7 +52960,7 @@ entries = bios->data[bios->offset + 10]; entry = &bios->data[bios->offset + 12]; while (entries--) { -@@ -5493,7 +5351,7 @@ bit_table(struct drm_device *dev, u8 id, struct bit_entry *bit) +@@ -5493,7 +5351,7 @@ bit->version = entry[1]; bit->length = ROM16(entry[2]); bit->offset = ROM16(entry[4]); @@ -53053,7 +52969,7 @@ return 0; } -@@ -5598,10 +5456,6 @@ static int parse_bmp_structure(struct drm_device *dev, struct nvbios *bios, unsi +@@ -5598,10 +5456,6 @@ uint16_t legacy_scripts_offset, legacy_i2c_offset; /* load needed defaults in case we can't parse this info */ @@ -53064,7 +52980,7 @@ bios->digital_min_front_porch = 0x4b; bios->fmaxvco = 256000; bios->fminvco = 128000; -@@ -5709,14 +5563,6 @@ static int parse_bmp_structure(struct drm_device *dev, struct nvbios *bios, unsi +@@ -5709,14 +5563,6 @@ bios->legacy.i2c_indices.crt = bios->data[legacy_i2c_offset]; bios->legacy.i2c_indices.tv = bios->data[legacy_i2c_offset + 1]; bios->legacy.i2c_indices.panel = bios->data[legacy_i2c_offset + 2]; @@ -53079,7 +52995,7 @@ if (bmplength > 74) { bios->fmaxvco = ROM32(bmp[67]); -@@ -5767,286 +5613,128 @@ static uint16_t findstr(uint8_t *data, int n, const uint8_t *str, int len) +@@ -5767,286 +5613,128 @@ return 0; } @@ -53294,18 +53210,18 @@ - type = DCB_CONNECTOR_DVI_I; - else - type = DCB_CONNECTOR_DVI_D; -- } else -- if (encoders & (1 << OUTPUT_ANALOG)) { -- type = DCB_CONNECTOR_VGA; -- } else -- if (encoders & (1 << OUTPUT_LVDS)) { -- type = DCB_CONNECTOR_LVDS; + if (dcb && dcb[0] >= 0x20) { + u8 *i2c = ROMPTR(dev, dcb[2]); + u8 *ent = dcb + 8 + (idx * 8); + if (i2c && ent < i2c) + return ent; } else +- if (encoders & (1 << OUTPUT_ANALOG)) { +- type = DCB_CONNECTOR_VGA; +- } else +- if (encoders & (1 << OUTPUT_LVDS)) { +- type = DCB_CONNECTOR_LVDS; +- } else - if (encoders & (1 << OUTPUT_TV)) { - type = DCB_CONNECTOR_TV_0; + if (dcb && dcb[0] >= 0x15) { @@ -53321,13 +53237,12 @@ -static void -apply_dcb_connector_quirks(struct nvbios *bios, int idx) --{ -- struct dcb_connector_table_entry *cte = &bios->dcb.connector.entry[idx]; -- struct drm_device *dev = bios->dev; +int +dcb_outp_foreach(struct drm_device *dev, void *data, + int (*exec)(struct drm_device *, void *, int idx, u8 *outp)) -+{ + { +- struct dcb_connector_table_entry *cte = &bios->dcb.connector.entry[idx]; +- struct drm_device *dev = bios->dev; + int ret, idx = -1; + u8 *outp = NULL; + while ((outp = dcb_outp(dev, ++idx))) { @@ -53335,34 +53250,34 @@ + break; /* seen on an NV11 with DCB v1.5 */ + if (ROM32(outp[0]) == 0xffffffff) + break; /* seen on an NV17 with DCB v2.0 */ -+ + +- /* Gigabyte NX85T */ +- if (nv_match_device(dev, 0x0421, 0x1458, 0x344c)) { +- if (cte->type == DCB_CONNECTOR_HDMI_1) +- cte->type = DCB_CONNECTOR_DVI_I; +- } + if ((outp[0] & 0x0f) == OUTPUT_UNUSED) + continue; + if ((outp[0] & 0x0f) == OUTPUT_EOL) + break; -- /* Gigabyte NX85T */ -- if (nv_match_device(dev, 0x0421, 0x1458, 0x344c)) { +- /* Gigabyte GV-NX86T512H */ +- if (nv_match_device(dev, 0x0402, 0x1458, 0x3455)) { - if (cte->type == DCB_CONNECTOR_HDMI_1) - cte->type = DCB_CONNECTOR_DVI_I; + ret = exec(dev, data, idx, outp); + if (ret) + return ret; } - -- /* Gigabyte GV-NX86T512H */ -- if (nv_match_device(dev, 0x0402, 0x1458, 0x3455)) { -- if (cte->type == DCB_CONNECTOR_HDMI_1) -- cte->type = DCB_CONNECTOR_DVI_I; -- } -+ return 0; - } +-} -static const u8 hpd_gpio[16] = { - 0xff, 0x07, 0x08, 0xff, 0xff, 0x51, 0x52, 0xff, - 0xff, 0xff, 0xff, 0xff, 0xff, 0x5e, 0x5f, 0x60, -}; -- ++ return 0; ++} + -static void -parse_dcb_connector_table(struct nvbios *bios) +u8 * @@ -53460,7 +53375,7 @@ } static struct dcb_entry *new_dcb_entry(struct dcb_table *dcb) -@@ -6079,8 +5767,7 @@ parse_dcb20_entry(struct drm_device *dev, struct dcb_table *dcb, +@@ -6079,8 +5767,7 @@ entry->type = conn & 0xf; entry->i2c_index = (conn >> 4) & 0xf; entry->heads = (conn >> 8) & 0xf; @@ -53470,7 +53385,7 @@ entry->bus = (conn >> 16) & 0xf; entry->location = (conn >> 20) & 0x3; entry->or = (conn >> 24) & 0xf; -@@ -6252,25 +5939,6 @@ parse_dcb15_entry(struct drm_device *dev, struct dcb_table *dcb, +@@ -6252,25 +5939,6 @@ return true; } @@ -53496,7 +53411,7 @@ static void merge_like_dcb_entries(struct drm_device *dev, struct dcb_table *dcb) { -@@ -6431,154 +6099,122 @@ fabricate_dcb_encoder_table(struct drm_device *dev, struct nvbios *bios) +@@ -6431,154 +6099,122 @@ #endif /* Make up some sane defaults */ @@ -53543,9 +53458,15 @@ - fabricate_dcb_encoder_table(dev, bios); - return 0; - } -- ++ struct dcb_table *dcb = &dev_priv->vbios.dcb; ++ u32 conf = (dcb->version >= 0x20) ? ROM32(outp[4]) : ROM32(outp[6]); ++ u32 conn = ROM32(outp[0]); ++ bool ret; + - dcbtable = &bios->data[dcbptr]; -- ++ if (apply_dcb_encoder_quirks(dev, idx, &conn, &conf)) { ++ struct dcb_entry *entry = new_dcb_entry(dcb); + - /* get DCB version */ - dcb->version = dcbtable[0]; - NV_TRACE(dev, "Found Display Configuration Block version %d.%d\n", @@ -53553,11 +53474,7 @@ - - if (dcb->version >= 0x20) { /* NV17+ */ - uint32_t sig; -+ struct dcb_table *dcb = &dev_priv->vbios.dcb; -+ u32 conf = (dcb->version >= 0x20) ? ROM32(outp[4]) : ROM32(outp[6]); -+ u32 conn = ROM32(outp[0]); -+ bool ret; - +- - if (dcb->version >= 0x30) { /* NV40+ */ - headerlen = dcbtable[1]; - entries = dcbtable[2]; @@ -53571,8 +53488,7 @@ - sig = ROM32(dcbtable[4]); - headerlen = 8; - } -+ if (apply_dcb_encoder_quirks(dev, idx, &conn, &conf)) { -+ struct dcb_entry *entry = new_dcb_entry(dcb); ++ NV_TRACEWARN(dev, "DCB outp %02d: %08x %08x\n", idx, conn, conf); - if (sig != 0x4edcbdcb) { - NV_ERROR(dev, "Bad Display Configuration Block " @@ -53581,12 +53497,6 @@ - } - } else if (dcb->version >= 0x15) { /* some NV11 and NV20 */ - char sig[8] = { 0 }; -+ NV_TRACEWARN(dev, "DCB outp %02d: %08x %08x\n", idx, conn, conf); - -- strncpy(sig, (char *)&dcbtable[-7], 7); -- i2ctabptr = ROM16(dcbtable[2]); -- recordlength = 10; -- confofs = 6; + if (dcb->version >= 0x20) + ret = parse_dcb20_entry(dev, dcb, conn, conf, entry); + else @@ -53594,6 +53504,11 @@ + if (!ret) + return 1; /* stop parsing */ +- strncpy(sig, (char *)&dcbtable[-7], 7); +- i2ctabptr = ROM16(dcbtable[2]); +- recordlength = 10; +- confofs = 6; +- - if (strcmp(sig, "DEV_REC")) { - NV_ERROR(dev, "Bad Display Configuration Block " - "signature (%s)\n", sig); @@ -53670,10 +53585,6 @@ - connection = ROM32(dcbtable[headerlen + recordlength * i]); - if (configblock) - config = ROM32(dcbtable[headerlen + confofs + recordlength * i]); -- -- /* seen on an NV11 with DCB v1.5 */ -- if (connection == 0x00000000) -- break; + /* no useful connector info available, we need to make it up + * ourselves. the rule here is: anything on the same i2c bus + * is considered to be on the same connector. any output @@ -53691,8 +53602,8 @@ + } + } -- /* seen on an NV17 with DCB v2.0 */ -- if (connection == 0xffffffff) +- /* seen on an NV11 with DCB v1.5 */ +- if (connection == 0x00000000) - break; + /* if we created more than one connector, destroy the connector + * table - just in case it has random, rather than stub, entries. @@ -53704,15 +53615,18 @@ + } +} -- if ((connection & 0x0000000f) == 0x0000000f) -- continue; +- /* seen on an NV17 with DCB v2.0 */ +- if (connection == 0xffffffff) +- break; +static int +parse_dcb_table(struct drm_device *dev, struct nvbios *bios) +{ + struct dcb_table *dcb = &bios->dcb; + u8 *dcbt, *conn; + int idx; -+ + +- if ((connection & 0x0000000f) == 0x0000000f) +- continue; + dcbt = dcb_table(dev); + if (!dcbt) { + /* handle pre-DCB boards */ @@ -53738,7 +53652,7 @@ /* * apart for v2.1+ not being known for requiring merging, this -@@ -6590,77 +6226,19 @@ parse_dcb_table(struct drm_device *dev, struct nvbios *bios) +@@ -6590,77 +6226,19 @@ if (!dcb->entries) return -ENXIO; @@ -53827,7 +53741,7 @@ } static int load_nv17_hwsq_ucode_entry(struct drm_device *dev, struct nvbios *bios, uint16_t hwsq_offset, int entry) -@@ -6799,11 +6377,7 @@ static bool NVInitVBIOS(struct drm_device *dev) +@@ -6799,11 +6377,7 @@ spin_lock_init(&bios->lock); bios->dev = dev; @@ -53840,7 +53754,7 @@ } static int nouveau_parse_vbios_struct(struct drm_device *dev) -@@ -6879,19 +6453,6 @@ nouveau_run_vbios_init(struct drm_device *dev) +@@ -6879,19 +6453,6 @@ return ret; } @@ -53860,7 +53774,7 @@ static bool nouveau_bios_posted(struct drm_device *dev) { -@@ -6928,12 +6489,17 @@ nouveau_bios_init(struct drm_device *dev) +@@ -6928,12 +6489,17 @@ if (ret) return ret; @@ -53881,7 +53795,7 @@ if (!bios->major_version) /* we don't run version 0 bios */ return 0; -@@ -6971,5 +6537,10 @@ nouveau_bios_init(struct drm_device *dev) +@@ -6971,5 +6537,10 @@ void nouveau_bios_takedown(struct drm_device *dev) { @@ -53893,10 +53807,10 @@ + + kfree(dev_priv->vbios.data); } -diff --git a/drivers/gpu/drm/nouveau/nouveau_bios.h b/drivers/gpu/drm/nouveau/nouveau_bios.h -index 8adb69e..298a3af 100644 ---- a/drivers/gpu/drm/nouveau/nouveau_bios.h -+++ b/drivers/gpu/drm/nouveau/nouveau_bios.h +Index: linux-3.2.46/drivers/gpu/drm/nouveau/nouveau_bios.h +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/nouveau/nouveau_bios.h 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/nouveau/nouveau_bios.h 2013-07-26 19:26:23.000000000 +0000 @@ -34,9 +34,14 @@ #define DCB_LOC_ON_CHIP 0 @@ -53915,7 +53829,7 @@ struct bit_entry { uint8_t id; -@@ -48,30 +53,13 @@ struct bit_entry { +@@ -48,30 +53,13 @@ int bit_table(struct drm_device *, u8 id, struct bit_entry *); @@ -53951,7 +53865,7 @@ }; enum dcb_connector_type { -@@ -81,29 +69,19 @@ enum dcb_connector_type { +@@ -81,29 +69,19 @@ DCB_CONNECTOR_TV_3 = 0x13, DCB_CONNECTOR_DVI_I = 0x30, DCB_CONNECTOR_DVI_D = 0x31, @@ -53985,7 +53899,7 @@ enum dcb_type { OUTPUT_ANALOG = 0, OUTPUT_TV = 1, -@@ -111,6 +89,7 @@ enum dcb_type { +@@ -111,6 +89,7 @@ OUTPUT_LVDS = 3, OUTPUT_DP = 6, OUTPUT_EOL = 14, /* DCB 4.0+, appears to be end-of-list */ @@ -53993,7 +53907,7 @@ OUTPUT_ANY = -1 }; -@@ -155,18 +134,8 @@ struct dcb_entry { +@@ -155,18 +134,8 @@ struct dcb_table { uint8_t version; @@ -54012,7 +53926,7 @@ }; enum nouveau_or { -@@ -195,7 +164,7 @@ enum pll_types { +@@ -195,7 +164,7 @@ PLL_SHADER = 0x02, PLL_UNK03 = 0x03, PLL_MEMORY = 0x04, @@ -54021,7 +53935,7 @@ PLL_UNK40 = 0x40, PLL_UNK41 = 0x41, PLL_UNK42 = 0x42, -@@ -244,6 +213,8 @@ struct nvbios { +@@ -244,6 +213,8 @@ NVBIOS_BIT } type; uint16_t offset; @@ -54030,7 +53944,7 @@ uint8_t chip_version; -@@ -254,8 +225,6 @@ struct nvbios { +@@ -254,8 +225,6 @@ spinlock_t lock; @@ -54039,7 +53953,7 @@ bool execute; uint8_t major_version; -@@ -333,4 +302,11 @@ struct nvbios { +@@ -333,4 +302,11 @@ } legacy; }; @@ -54051,10 +53965,10 @@ +u8 *dcb_conn(struct drm_device *, u8 idx); + #endif -diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.c b/drivers/gpu/drm/nouveau/nouveau_bo.c -index 2bb29c9..12ce044 100644 ---- a/drivers/gpu/drm/nouveau/nouveau_bo.c -+++ b/drivers/gpu/drm/nouveau/nouveau_bo.c +Index: linux-3.2.46/drivers/gpu/drm/nouveau/nouveau_bo.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/nouveau/nouveau_bo.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/nouveau/nouveau_bo.c 2013-07-26 19:26:23.000000000 +0000 @@ -28,6 +28,7 @@ */ @@ -54063,7 +53977,7 @@ #include "nouveau_drm.h" #include "nouveau_drv.h" -@@ -92,6 +93,7 @@ nouveau_bo_new(struct drm_device *dev, int size, int align, +@@ -92,6 +93,7 @@ { struct drm_nouveau_private *dev_priv = dev->dev_private; struct nouveau_bo *nvbo; @@ -54071,7 +53985,7 @@ int ret; nvbo = kzalloc(sizeof(struct nouveau_bo), GFP_KERNEL); -@@ -114,9 +116,12 @@ nouveau_bo_new(struct drm_device *dev, int size, int align, +@@ -114,9 +116,12 @@ nvbo->bo.mem.num_pages = size >> PAGE_SHIFT; nouveau_bo_placement_set(nvbo, flags, 0); @@ -54085,7 +53999,7 @@ nouveau_bo_del_ttm); if (ret) { /* ttm will call nouveau_bo_del_ttm if it fails.. */ -@@ -343,8 +348,10 @@ nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val) +@@ -343,8 +348,10 @@ *mem = val; } @@ -54098,7 +54012,7 @@ { struct drm_nouveau_private *dev_priv = nouveau_bdev(bdev); struct drm_device *dev = dev_priv->dev; -@@ -352,11 +359,13 @@ nouveau_bo_create_ttm_backend_entry(struct ttm_bo_device *bdev) +@@ -352,11 +359,13 @@ switch (dev_priv->gart_info.type) { #if __OS_HAS_AGP case NOUVEAU_GART_AGP: @@ -54114,7 +54028,7 @@ default: NV_ERROR(dev, "Unknown GART type %d\n", dev_priv->gart_info.type); -@@ -673,8 +682,7 @@ nouveau_vma_getmap(struct nouveau_channel *chan, struct nouveau_bo *nvbo, +@@ -673,8 +682,7 @@ if (mem->mem_type == TTM_PL_VRAM) nouveau_vm_map(vma, node); else @@ -54124,7 +54038,7 @@ return 0; } -@@ -685,16 +693,12 @@ nouveau_bo_move_m2mf(struct ttm_buffer_object *bo, int evict, bool intr, +@@ -685,16 +693,12 @@ struct ttm_mem_reg *new_mem) { struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev); @@ -54143,7 +54057,7 @@ /* create temporary vmas for the transfer and attach them to the * old nouveau_mem node, these will get cleaned up after ttm has -@@ -726,8 +730,7 @@ nouveau_bo_move_m2mf(struct ttm_buffer_object *bo, int evict, bool intr, +@@ -726,8 +730,7 @@ } out: @@ -54153,7 +54067,7 @@ return ret; } -@@ -801,19 +804,22 @@ out: +@@ -801,19 +804,22 @@ static void nouveau_bo_move_ntfy(struct ttm_buffer_object *bo, struct ttm_mem_reg *new_mem) { @@ -54180,7 +54094,7 @@ } else { nouveau_vm_unmap(vma); } -@@ -940,7 +946,7 @@ nouveau_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem) +@@ -940,7 +946,7 @@ if (dev_priv->gart_info.type == NOUVEAU_GART_AGP) { mem->bus.offset = mem->start << PAGE_SHIFT; mem->bus.base = dev_priv->gart_info.aper_base; @@ -54189,7 +54103,7 @@ } #endif break; -@@ -1044,8 +1050,94 @@ nouveau_bo_fence(struct nouveau_bo *nvbo, struct nouveau_fence *fence) +@@ -1044,8 +1050,94 @@ nouveau_fence_unref(&old_fence); } @@ -54285,7 +54199,7 @@ .invalidate_caches = nouveau_bo_invalidate_caches, .init_mem_type = nouveau_bo_init_mem_type, .evict_flags = nouveau_bo_evict_flags, -@@ -1091,7 +1183,7 @@ nouveau_bo_vma_add(struct nouveau_bo *nvbo, struct nouveau_vm *vm, +@@ -1091,7 +1183,7 @@ nouveau_vm_map(vma, nvbo->bo.mem.mm_node); else if (nvbo->bo.mem.mem_type == TTM_PL_TT) @@ -54294,11 +54208,11 @@ list_add_tail(&vma->head, &nvbo->vma_list); vma->refcount = 1; -diff --git a/drivers/gpu/drm/nouveau/nouveau_channel.c b/drivers/gpu/drm/nouveau/nouveau_channel.c -index bb6ec9e..846afb0 100644 ---- a/drivers/gpu/drm/nouveau/nouveau_channel.c -+++ b/drivers/gpu/drm/nouveau/nouveau_channel.c -@@ -122,7 +122,7 @@ nouveau_channel_alloc(struct drm_device *dev, struct nouveau_channel **chan_ret, +Index: linux-3.2.46/drivers/gpu/drm/nouveau/nouveau_channel.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/nouveau/nouveau_channel.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/nouveau/nouveau_channel.c 2013-07-26 19:26:23.000000000 +0000 +@@ -122,7 +122,7 @@ struct nouveau_fpriv *fpriv = nouveau_fpriv(file_priv); struct nouveau_channel *chan; unsigned long flags; @@ -54307,7 +54221,7 @@ /* allocate and lock channel structure */ chan = kzalloc(sizeof(*chan), GFP_KERNEL); -@@ -184,9 +184,11 @@ nouveau_channel_alloc(struct drm_device *dev, struct nouveau_channel **chan_ret, +@@ -184,9 +184,11 @@ return ret; } @@ -54320,7 +54234,7 @@ /* disable the fifo caches */ pfifo->reassign(dev, false); -@@ -200,9 +202,18 @@ nouveau_channel_alloc(struct drm_device *dev, struct nouveau_channel **chan_ret, +@@ -200,9 +202,18 @@ pfifo->reassign(dev, true); @@ -54342,7 +54256,7 @@ if (ret) { nouveau_channel_put(&chan); return ret; -@@ -425,18 +436,11 @@ nouveau_ioctl_fifo_alloc(struct drm_device *dev, void *data, +@@ -425,18 +436,11 @@ } if (dev_priv->card_type < NV_C0) { @@ -54363,10 +54277,10 @@ } /* Named memory object area */ -diff --git a/drivers/gpu/drm/nouveau/nouveau_connector.c b/drivers/gpu/drm/nouveau/nouveau_connector.c -index 1e72db5..7b11edb 100644 ---- a/drivers/gpu/drm/nouveau/nouveau_connector.c -+++ b/drivers/gpu/drm/nouveau/nouveau_connector.c +Index: linux-3.2.46/drivers/gpu/drm/nouveau/nouveau_connector.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/nouveau/nouveau_connector.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/nouveau/nouveau_connector.c 2013-07-26 19:26:23.000000000 +0000 @@ -35,6 +35,7 @@ #include "nouveau_encoder.h" #include "nouveau_crtc.h" @@ -54375,7 +54289,7 @@ #include "nouveau_hw.h" static void nouveau_connector_hotplug(void *, int); -@@ -78,29 +79,11 @@ nouveau_encoder_connector_get(struct nouveau_encoder *encoder) +@@ -78,29 +79,11 @@ return NULL; } @@ -54405,7 +54319,7 @@ struct drm_device *dev; if (!nv_connector) -@@ -110,10 +93,9 @@ nouveau_connector_destroy(struct drm_connector *connector) +@@ -110,10 +93,9 @@ dev_priv = dev->dev_private; NV_DEBUG_KMS(dev, "\n"); @@ -54419,7 +54333,7 @@ } kfree(nv_connector->edid); -@@ -198,6 +180,10 @@ nouveau_connector_set_encoder(struct drm_connector *connector, +@@ -198,6 +180,10 @@ return; nv_connector->detected_encoder = nv_encoder; @@ -54430,7 +54344,7 @@ if (nv_encoder->dcb->type == OUTPUT_LVDS || nv_encoder->dcb->type == OUTPUT_TMDS) { connector->doublescan_allowed = false; -@@ -214,7 +200,7 @@ nouveau_connector_set_encoder(struct drm_connector *connector, +@@ -214,7 +200,7 @@ connector->interlace_allowed = true; } @@ -54439,7 +54353,7 @@ drm_connector_property_set_value(connector, dev->mode_config.dvi_i_subconnector_property, nv_encoder->dcb->type == OUTPUT_TMDS ? -@@ -397,7 +383,7 @@ nouveau_connector_force(struct drm_connector *connector) +@@ -397,7 +383,7 @@ struct nouveau_encoder *nv_encoder; int type; @@ -54448,7 +54362,7 @@ if (connector->force == DRM_FORCE_ON_DIGITAL) type = OUTPUT_TMDS; else -@@ -420,15 +406,21 @@ static int +@@ -420,15 +406,21 @@ nouveau_connector_set_property(struct drm_connector *connector, struct drm_property *property, uint64_t value) { @@ -54471,7 +54385,7 @@ bool modeset = false; switch (value) { -@@ -454,8 +446,6 @@ nouveau_connector_set_property(struct drm_connector *connector, +@@ -454,8 +446,6 @@ modeset = true; nv_connector->scaling_mode = value; @@ -54480,7 +54394,7 @@ if (!nv_crtc) return 0; -@@ -467,7 +457,7 @@ nouveau_connector_set_property(struct drm_connector *connector, +@@ -467,7 +457,7 @@ if (!ret) return -EINVAL; } else { @@ -54489,7 +54403,7 @@ if (ret) return ret; } -@@ -475,23 +465,71 @@ nouveau_connector_set_property(struct drm_connector *connector, +@@ -475,23 +465,71 @@ return 0; } @@ -54544,10 +54458,10 @@ + nv_connector->dithering_mode = value; + if (!nv_crtc || !nv_crtc->set_dither) + return 0; -+ + + return nv_crtc->set_dither(nv_crtc, true); + } - ++ + if (property == disp->dithering_depth) { + nv_connector->dithering_depth = value; if (!nv_crtc || !nv_crtc->set_dither) @@ -54572,7 +54486,7 @@ } if (nv_encoder && nv_encoder->dcb->type == OUTPUT_TV) -@@ -617,7 +655,7 @@ nouveau_connector_detect_depth(struct drm_connector *connector) +@@ -617,7 +655,7 @@ return; /* EDID 1.4 is *supposed* to be supported on eDP, but, Apple... */ @@ -54581,7 +54495,7 @@ connector->display_info.bpc = 6; return; } -@@ -641,7 +679,7 @@ nouveau_connector_detect_depth(struct drm_connector *connector) +@@ -641,7 +679,7 @@ * know which if_is_24bit flag to check... */ if (nv_connector->edid && @@ -54590,7 +54504,7 @@ duallink = ((u8 *)nv_connector->edid)[121] == 2; else duallink = mode->clock >= bios->fp.duallink_transition_clk; -@@ -680,6 +718,12 @@ nouveau_connector_get_modes(struct drm_connector *connector) +@@ -680,6 +718,12 @@ nv_connector->native_mode = drm_mode_duplicate(dev, &mode); } @@ -54603,7 +54517,7 @@ /* Find the native mode if this is a digital panel, if we didn't * find any modes through DDC previously add the native mode to * the list of modes. -@@ -695,18 +739,19 @@ nouveau_connector_get_modes(struct drm_connector *connector) +@@ -695,18 +739,19 @@ ret = 1; } @@ -54630,7 +54544,7 @@ ret += nouveau_connector_scaler_modes_add(connector); return ret; -@@ -765,7 +810,7 @@ nouveau_connector_mode_valid(struct drm_connector *connector, +@@ -765,7 +810,7 @@ case OUTPUT_DP: max_clock = nv_encoder->dp.link_nr; max_clock *= nv_encoder->dp.link_bw; @@ -54639,7 +54553,7 @@ break; default: BUG_ON(1); -@@ -823,96 +868,188 @@ nouveau_connector_funcs_lvds = { +@@ -823,96 +868,188 @@ .force = nouveau_connector_force }; @@ -54738,7 +54652,10 @@ + connector = &nv_connector->base; + nv_connector->index = index; -+ + +- /* defaults, will get overridden in detect() */ +- connector->interlace_allowed = false; +- connector->doublescan_allowed = false; + /* attempt to parse vbios connector type and hotplug gpio */ + nv_connector->dcb = dcb_conn(dev, index); + if (nv_connector->dcb) { @@ -54762,17 +54679,14 @@ + nv_connector->type = DCB_CONNECTOR_NONE; + } -- /* defaults, will get overridden in detect() */ -- connector->interlace_allowed = false; -- connector->doublescan_allowed = false; +- drm_connector_init(dev, connector, funcs, type); +- drm_connector_helper_add(connector, &nouveau_connector_helper_funcs); + /* Gigabyte NX85T */ + if (nv_match_device(dev, 0x0421, 0x1458, 0x344c)) { + if (nv_connector->type == DCB_CONNECTOR_HDMI_1) + nv_connector->type = DCB_CONNECTOR_DVI_I; + } - -- drm_connector_init(dev, connector, funcs, type); -- drm_connector_helper_add(connector, &nouveau_connector_helper_funcs); ++ + /* Gigabyte GV-NX86T512H */ + if (nv_match_device(dev, 0x0402, 0x1458, 0x3455)) { + if (nv_connector->type == DCB_CONNECTOR_HDMI_1) @@ -54888,7 +54802,7 @@ case DCB_CONNECTOR_VGA: if (dev_priv->card_type >= NV_50) { drm_connector_attach_property(connector, -@@ -931,32 +1068,32 @@ nouveau_connector_create(struct drm_device *dev, int index) +@@ -931,32 +1068,32 @@ drm_connector_attach_property(connector, dev->mode_config.scaling_mode_property, nv_connector->scaling_mode); @@ -54941,10 +54855,10 @@ } static void -diff --git a/drivers/gpu/drm/nouveau/nouveau_connector.h b/drivers/gpu/drm/nouveau/nouveau_connector.h -index 711b1e9..e485702 100644 ---- a/drivers/gpu/drm/nouveau/nouveau_connector.h -+++ b/drivers/gpu/drm/nouveau/nouveau_connector.h +Index: linux-3.2.46/drivers/gpu/drm/nouveau/nouveau_connector.h +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/nouveau/nouveau_connector.h 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/nouveau/nouveau_connector.h 2013-07-26 19:26:23.000000000 +0000 @@ -30,13 +30,43 @@ #include "drm_edid.h" #include "nouveau_i2c.h" @@ -54992,11 +54906,11 @@ struct nouveau_encoder *detected_encoder; struct edid *edid; -diff --git a/drivers/gpu/drm/nouveau/nouveau_crtc.h b/drivers/gpu/drm/nouveau/nouveau_crtc.h -index bf8e128..e6d0d1e 100644 ---- a/drivers/gpu/drm/nouveau/nouveau_crtc.h -+++ b/drivers/gpu/drm/nouveau/nouveau_crtc.h -@@ -32,11 +32,11 @@ struct nouveau_crtc { +Index: linux-3.2.46/drivers/gpu/drm/nouveau/nouveau_crtc.h +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/nouveau/nouveau_crtc.h 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/nouveau/nouveau_crtc.h 2013-07-26 19:26:23.000000000 +0000 +@@ -32,11 +32,11 @@ int index; @@ -55010,7 +54924,7 @@ int sharpness; int last_dpms; -@@ -67,8 +67,9 @@ struct nouveau_crtc { +@@ -67,8 +67,9 @@ int depth; } lut; @@ -55022,11 +54936,11 @@ }; static inline struct nouveau_crtc *nouveau_crtc(struct drm_crtc *crtc) -diff --git a/drivers/gpu/drm/nouveau/nouveau_debugfs.c b/drivers/gpu/drm/nouveau/nouveau_debugfs.c -index 8e15923..fa2ec49 100644 ---- a/drivers/gpu/drm/nouveau/nouveau_debugfs.c -+++ b/drivers/gpu/drm/nouveau/nouveau_debugfs.c -@@ -44,7 +44,7 @@ nouveau_debugfs_channel_info(struct seq_file *m, void *data) +Index: linux-3.2.46/drivers/gpu/drm/nouveau/nouveau_debugfs.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/nouveau/nouveau_debugfs.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/nouveau/nouveau_debugfs.c 2013-07-26 19:26:23.000000000 +0000 +@@ -44,7 +44,7 @@ seq_printf(m, "channel id : %d\n", chan->id); seq_printf(m, "cpu fifo state:\n"); @@ -55035,7 +54949,7 @@ seq_printf(m, " max: 0x%08x\n", chan->dma.max << 2); seq_printf(m, " cur: 0x%08x\n", chan->dma.cur << 2); seq_printf(m, " put: 0x%08x\n", chan->dma.put << 2); -@@ -178,6 +178,7 @@ static struct drm_info_list nouveau_debugfs_list[] = { +@@ -178,6 +178,7 @@ { "memory", nouveau_debugfs_memory_info, 0, NULL }, { "vbios.rom", nouveau_debugfs_vbios_image, 0, NULL }, { "ttm_page_pool", ttm_page_alloc_debugfs, 0, NULL }, @@ -55043,10 +54957,10 @@ }; #define NOUVEAU_DEBUGFS_ENTRIES ARRAY_SIZE(nouveau_debugfs_list) -diff --git a/drivers/gpu/drm/nouveau/nouveau_display.c b/drivers/gpu/drm/nouveau/nouveau_display.c -index 6adef06..f233b8f 100644 ---- a/drivers/gpu/drm/nouveau/nouveau_display.c -+++ b/drivers/gpu/drm/nouveau/nouveau_display.c +Index: linux-3.2.46/drivers/gpu/drm/nouveau/nouveau_display.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/nouveau/nouveau_display.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/nouveau/nouveau_display.c 2013-07-26 19:26:23.000000000 +0000 @@ -32,6 +32,8 @@ #include "nouveau_hw.h" #include "nouveau_crtc.h" @@ -55056,7 +54970,7 @@ #include "nv50_display.h" static void -@@ -64,7 +66,7 @@ static const struct drm_framebuffer_funcs nouveau_framebuffer_funcs = { +@@ -64,7 +66,7 @@ int nouveau_framebuffer_init(struct drm_device *dev, struct nouveau_framebuffer *nv_fb, @@ -55065,7 +54979,7 @@ struct nouveau_bo *nvbo) { struct drm_nouveau_private *dev_priv = dev->dev_private; -@@ -107,14 +109,14 @@ nouveau_framebuffer_init(struct drm_device *dev, +@@ -107,14 +109,14 @@ if (!tile_flags) { if (dev_priv->card_type < NV_D0) @@ -55083,7 +54997,7 @@ } } -@@ -124,13 +126,13 @@ nouveau_framebuffer_init(struct drm_device *dev, +@@ -124,13 +126,13 @@ static struct drm_framebuffer * nouveau_user_framebuffer_create(struct drm_device *dev, struct drm_file *file_priv, @@ -55099,7 +55013,7 @@ if (!gem) return ERR_PTR(-ENOENT); -@@ -147,11 +149,207 @@ nouveau_user_framebuffer_create(struct drm_device *dev, +@@ -147,11 +149,207 @@ return &nouveau_fb->base; } @@ -55308,7 +55222,7 @@ int nouveau_vblank_enable(struct drm_device *dev, int crtc) { -@@ -243,15 +441,19 @@ nouveau_page_flip_emit(struct nouveau_channel *chan, +@@ -243,15 +441,19 @@ goto fail; /* Emit the pageflip */ @@ -55333,7 +55247,7 @@ FIRE_RING (chan); ret = nouveau_fence_new(chan, pfence, true); -@@ -294,7 +496,7 @@ nouveau_crtc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb, +@@ -294,7 +496,7 @@ /* Initialize a page flip struct */ *s = (struct nouveau_page_flip_state) { { }, event, nouveau_crtc(crtc)->index, @@ -55342,7 +55256,7 @@ new_bo->bo.offset }; /* Choose the channel the flip will be handled in */ -@@ -305,7 +507,10 @@ nouveau_crtc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb, +@@ -305,7 +507,10 @@ /* Emit a page flip */ if (dev_priv->card_type >= NV_50) { @@ -55354,10 +55268,10 @@ if (ret) { nouveau_channel_put(&chan); goto fail_unreserve; -diff --git a/drivers/gpu/drm/nouveau/nouveau_dma.c b/drivers/gpu/drm/nouveau/nouveau_dma.c -index 00bc6ea..295932e 100644 ---- a/drivers/gpu/drm/nouveau/nouveau_dma.c -+++ b/drivers/gpu/drm/nouveau/nouveau_dma.c +Index: linux-3.2.46/drivers/gpu/drm/nouveau/nouveau_dma.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/nouveau/nouveau_dma.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/nouveau/nouveau_dma.c 2013-07-26 19:26:23.000000000 +0000 @@ -31,7 +31,7 @@ #include "nouveau_ramht.h" @@ -55367,7 +55281,7 @@ { struct drm_nouveau_private *dev_priv = chan->dev->dev_private; struct nouveau_bo *pushbuf = chan->pushbuf_bo; -@@ -54,65 +54,6 @@ nouveau_dma_pre_init(struct nouveau_channel *chan) +@@ -54,65 +54,6 @@ chan->dma.free = chan->dma.max - chan->dma.cur; } @@ -55433,7 +55347,7 @@ void OUT_RINGp(struct nouveau_channel *chan, const void *data, unsigned nr_dwords) { -@@ -134,11 +75,13 @@ OUT_RINGp(struct nouveau_channel *chan, const void *data, unsigned nr_dwords) +@@ -134,11 +75,13 @@ * -EBUSY if timeout exceeded */ static inline int @@ -55449,7 +55363,7 @@ /* reset counter as long as GET is still advancing, this is * to avoid misdetecting a GPU lockup if the GPU happens to -@@ -218,8 +161,8 @@ nv50_dma_push_wait(struct nouveau_channel *chan, int count) +@@ -218,8 +161,8 @@ static int nv50_dma_wait(struct nouveau_channel *chan, int slots, int count) { @@ -55460,7 +55374,7 @@ ret = nv50_dma_push_wait(chan, slots + 1); if (unlikely(ret)) -@@ -261,8 +204,8 @@ nv50_dma_wait(struct nouveau_channel *chan, int slots, int count) +@@ -261,8 +204,8 @@ int nouveau_dma_wait(struct nouveau_channel *chan, int slots, int size) { @@ -55471,10 +55385,10 @@ if (chan->dma.ib_max) return nv50_dma_wait(chan, slots, size); -diff --git a/drivers/gpu/drm/nouveau/nouveau_dp.c b/drivers/gpu/drm/nouveau/nouveau_dp.c -index de5efe7..d996134 100644 ---- a/drivers/gpu/drm/nouveau/nouveau_dp.c -+++ b/drivers/gpu/drm/nouveau/nouveau_dp.c +Index: linux-3.2.46/drivers/gpu/drm/nouveau/nouveau_dp.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/nouveau/nouveau_dp.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/nouveau/nouveau_dp.c 2013-07-26 19:26:23.000000000 +0000 @@ -29,6 +29,7 @@ #include "nouveau_connector.h" #include "nouveau_encoder.h" @@ -55483,7 +55397,7 @@ /****************************************************************************** * aux channel util functions -@@ -160,121 +161,9 @@ out: +@@ -160,121 +161,9 @@ return ret; } @@ -55605,7 +55519,7 @@ struct bit_entry d; u8 *table; int i; -@@ -289,7 +178,7 @@ nouveau_dp_bios_data(struct drm_device *dev, struct dcb_entry *dcb, u8 **entry) +@@ -289,7 +178,7 @@ return NULL; } @@ -55614,7 +55528,7 @@ if (!table) { NV_ERROR(dev, "displayport table pointer invalid\n"); return NULL; -@@ -299,6 +188,7 @@ nouveau_dp_bios_data(struct drm_device *dev, struct dcb_entry *dcb, u8 **entry) +@@ -299,6 +188,7 @@ case 0x20: case 0x21: case 0x30: @@ -55622,7 +55536,7 @@ break; default: NV_ERROR(dev, "displayport table 0x%02x unknown\n", table[0]); -@@ -306,7 +196,7 @@ nouveau_dp_bios_data(struct drm_device *dev, struct dcb_entry *dcb, u8 **entry) +@@ -306,7 +196,7 @@ } for (i = 0; i < table[3]; i++) { @@ -55631,7 +55545,7 @@ if (*entry && bios_encoder_match(dcb, ROM32((*entry)[0]))) return table; } -@@ -319,13 +209,10 @@ nouveau_dp_bios_data(struct drm_device *dev, struct dcb_entry *dcb, u8 **entry) +@@ -319,13 +209,10 @@ * link training *****************************************************************************/ struct dp_state { @@ -55646,7 +55560,7 @@ u8 *dpcd; int link_nr; u32 link_bw; -@@ -336,143 +223,58 @@ struct dp_state { +@@ -336,143 +223,58 @@ static void dp_set_link_config(struct drm_device *dev, struct dp_state *dp) { @@ -55670,7 +55584,10 @@ - sink[0] = DP_LINK_BW_1_62; - break; - } -- ++ /* set desired link configuration on the source */ ++ dp->func->link_set(dev, dp->dcb, dp->crtc, dp->link_nr, dp->link_bw, ++ dp->dpcd[2] & DP_ENHANCED_FRAME_CAP); + - /* offset +0x0a of each dp encoder table entry is a pointer to another - * table, that has (among other things) pointers to more scripts that - * need to be executed, this time depending on link speed. @@ -55689,10 +55606,7 @@ - - nouveau_bios_run_init_table(dev, script, dp->dcb, dp->crtc); - } -+ /* set desired link configuration on the source */ -+ dp->func->link_set(dev, dp->dcb, dp->crtc, dp->link_nr, dp->link_bw, -+ dp->dpcd[2] & DP_ENHANCED_FRAME_CAP); - +- - /* configure lane count on the source */ - dp_ctrl = ((1 << dp->link_nr) - 1) << 16; + /* inform the sink of the new configuration */ @@ -55703,9 +55617,9 @@ + if (dp->dpcd[2] & DP_ENHANCED_FRAME_CAP) sink[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; - } -- -- nv_mask(dev, NV50_SOR_DP_CTRL(or, link), 0x001f4000, dp_ctrl); +- nv_mask(dev, NV50_SOR_DP_CTRL(or, link), 0x001f4000, dp_ctrl); +- - /* inform the sink of the new configuration */ auxch_tx(dev, dp->auxch, 8, DP_LINK_BW_SET, sink, 2); } @@ -55803,7 +55717,7 @@ return auxch_tx(dev, dp->auxch, 8, DP_TRAINING_LANE0_SET, dp->conf, 4); } -@@ -556,11 +358,61 @@ dp_link_train_eq(struct drm_device *dev, struct dp_state *dp) +@@ -556,11 +358,61 @@ return eq_done ? 0 : -1; } @@ -55868,7 +55782,7 @@ struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); struct nouveau_connector *nv_connector = -@@ -575,34 +427,26 @@ nouveau_dp_link_train(struct drm_encoder *encoder, u32 datarate) +@@ -575,34 +427,26 @@ if (!auxch) return false; @@ -55911,7 +55825,7 @@ /* start off at highest link rate supported by encoder and display */ while (*link_bw > nv_encoder->dp.link_bw) -@@ -636,13 +480,36 @@ nouveau_dp_link_train(struct drm_encoder *encoder, u32 datarate) +@@ -636,13 +480,36 @@ dp_set_training_pattern(dev, &dp, DP_TRAINING_PATTERN_DISABLE); /* execute post-train script from vbios */ @@ -55950,7 +55864,7 @@ bool nouveau_dp_detect(struct drm_encoder *encoder) { -@@ -656,7 +523,7 @@ nouveau_dp_detect(struct drm_encoder *encoder) +@@ -656,7 +523,7 @@ if (!auxch) return false; @@ -55959,7 +55873,7 @@ if (ret) return false; -@@ -684,7 +551,7 @@ int +@@ -684,7 +551,7 @@ nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr, uint8_t *data, int data_nr) { @@ -55968,11 +55882,11 @@ } static int -diff --git a/drivers/gpu/drm/nouveau/nouveau_drv.c b/drivers/gpu/drm/nouveau/nouveau_drv.c -index 8c084c0..05091c2 100644 ---- a/drivers/gpu/drm/nouveau/nouveau_drv.c -+++ b/drivers/gpu/drm/nouveau/nouveau_drv.c -@@ -57,6 +57,10 @@ MODULE_PARM_DESC(vram_notify, "Force DMA notifiers to be in VRAM"); +Index: linux-3.2.46/drivers/gpu/drm/nouveau/nouveau_drv.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/nouveau/nouveau_drv.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/nouveau/nouveau_drv.c 2013-07-26 19:26:23.000000000 +0000 +@@ -57,6 +57,10 @@ int nouveau_vram_notify = 0; module_param_named(vram_notify, nouveau_vram_notify, int, 0400); @@ -55983,7 +55897,7 @@ MODULE_PARM_DESC(duallink, "Allow dual-link TMDS (>=GeForce 8)"); int nouveau_duallink = 1; module_param_named(duallink, nouveau_duallink, int, 0400); -@@ -89,7 +93,7 @@ MODULE_PARM_DESC(override_conntype, "Ignore DCB connector type"); +@@ -89,7 +93,7 @@ int nouveau_override_conntype = 0; module_param_named(override_conntype, nouveau_override_conntype, int, 0400); @@ -55992,7 +55906,7 @@ int nouveau_tv_disable = 0; module_param_named(tv_disable, nouveau_tv_disable, int, 0400); -@@ -104,26 +108,30 @@ module_param_named(tv_norm, nouveau_tv_norm, charp, 0400); +@@ -104,26 +108,30 @@ MODULE_PARM_DESC(reg_debug, "Register access debug bitmask:\n" "\t\t0x1 mc, 0x2 video, 0x4 fb, 0x8 extdev,\n" "\t\t0x10 crtc, 0x20 ramdac, 0x40 vgacrtc, 0x80 rmvio,\n" @@ -56028,7 +55942,7 @@ int nouveau_fbpercrtc; #if 0 module_param_named(fbpercrtc, nouveau_fbpercrtc, int, 0400); -@@ -179,8 +187,11 @@ nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state) +@@ -179,8 +187,11 @@ return 0; if (dev->mode_config.num_crtc) { @@ -56042,7 +55956,7 @@ } NV_INFO(dev, "Unpinning framebuffer(s)...\n"); -@@ -222,7 +233,7 @@ nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state) +@@ -222,7 +233,7 @@ ret = dev_priv->eng[e]->fini(dev, e, true); if (ret) { @@ -56051,7 +55965,7 @@ goto out_abort; } } -@@ -248,12 +259,6 @@ nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state) +@@ -248,12 +259,6 @@ pci_set_power_state(pdev, PCI_D3hot); } @@ -56064,7 +55978,7 @@ return 0; out_abort: -@@ -279,9 +284,6 @@ nouveau_pci_resume(struct pci_dev *pdev) +@@ -279,9 +284,6 @@ if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) return 0; @@ -56074,7 +55988,7 @@ NV_INFO(dev, "We're back, enabling device...\n"); pci_set_power_state(pdev, PCI_D0); pci_restore_state(pdev); -@@ -301,8 +303,6 @@ nouveau_pci_resume(struct pci_dev *pdev) +@@ -301,8 +303,6 @@ if (ret) return ret; @@ -56083,7 +55997,7 @@ if (dev_priv->gart_info.type == NOUVEAU_GART_AGP) { ret = nouveau_mem_init_agp(dev); if (ret) { -@@ -342,6 +342,8 @@ nouveau_pci_resume(struct pci_dev *pdev) +@@ -342,6 +342,8 @@ } } @@ -56092,7 +56006,7 @@ NV_INFO(dev, "Restoring mode...\n"); list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { struct nouveau_framebuffer *nouveau_fb; -@@ -363,15 +365,11 @@ nouveau_pci_resume(struct pci_dev *pdev) +@@ -363,15 +365,11 @@ NV_ERROR(dev, "Could not pin/map cursor.\n"); } @@ -56112,7 +56026,7 @@ } /* Force CLUT to get re-loaded during modeset */ -@@ -381,21 +379,35 @@ nouveau_pci_resume(struct pci_dev *pdev) +@@ -381,21 +379,35 @@ nv_crtc->lut.depth = 0; } @@ -56157,7 +56071,7 @@ static struct drm_driver driver = { .driver_features = DRIVER_USE_AGP | DRIVER_PCI_DMA | DRIVER_SG | -@@ -421,21 +433,7 @@ static struct drm_driver driver = { +@@ -421,21 +433,7 @@ .disable_vblank = nouveau_vblank_disable, .reclaim_buffers = drm_core_reclaim_buffers, .ioctls = nouveau_ioctls, @@ -56180,10 +56094,10 @@ .gem_init_object = nouveau_gem_object_new, .gem_free_object = nouveau_gem_object_del, .gem_open_object = nouveau_gem_object_open, -diff --git a/drivers/gpu/drm/nouveau/nouveau_drv.h b/drivers/gpu/drm/nouveau/nouveau_drv.h -index 4c0be3a..3aef353 100644 ---- a/drivers/gpu/drm/nouveau/nouveau_drv.h -+++ b/drivers/gpu/drm/nouveau/nouveau_drv.h +Index: linux-3.2.46/drivers/gpu/drm/nouveau/nouveau_drv.h +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/nouveau/nouveau_drv.h 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/nouveau/nouveau_drv.h 2013-07-26 19:26:23.000000000 +0000 @@ -26,15 +26,15 @@ #define __NOUVEAU_DRV_H__ @@ -56204,7 +56118,7 @@ #define NOUVEAU_FAMILY 0x0000FFFF #define NOUVEAU_FLAGS 0xFFFF0000 -@@ -113,8 +113,6 @@ struct nouveau_bo { +@@ -113,8 +113,6 @@ int pbbo_index; bool validate_mapped; @@ -56213,7 +56127,7 @@ struct list_head vma_list; unsigned page_shift; -@@ -163,6 +161,9 @@ enum nouveau_flags { +@@ -163,6 +161,9 @@ #define NVOBJ_ENGINE_COPY0 3 #define NVOBJ_ENGINE_COPY1 4 #define NVOBJ_ENGINE_MPEG 5 @@ -56223,7 +56137,7 @@ #define NVOBJ_ENGINE_DISPLAY 15 #define NVOBJ_ENGINE_NR 16 -@@ -229,6 +230,7 @@ struct nouveau_channel { +@@ -229,6 +230,7 @@ /* mapping of the regs controlling the fifo */ void __iomem *user; uint32_t user_get; @@ -56231,7 +56145,7 @@ uint32_t user_put; /* Fencing */ -@@ -246,7 +248,7 @@ struct nouveau_channel { +@@ -246,7 +248,7 @@ struct nouveau_gpuobj *pushbuf; struct nouveau_bo *pushbuf_bo; struct nouveau_vma pushbuf_vma; @@ -56240,7 +56154,7 @@ /* Notifier memory */ struct nouveau_bo *notifier_bo; -@@ -292,7 +294,7 @@ struct nouveau_channel { +@@ -292,7 +294,7 @@ uint32_t sw_subchannel[8]; @@ -56249,7 +56163,7 @@ struct { struct nouveau_gpuobj *vblsem; uint32_t vblsem_head; -@@ -393,24 +395,28 @@ struct nouveau_display_engine { +@@ -393,24 +395,28 @@ int (*early_init)(struct drm_device *); void (*late_takedown)(struct drm_device *); int (*create)(struct drm_device *); @@ -56292,7 +56206,7 @@ }; struct nouveau_pm_voltage_level { -@@ -427,64 +433,91 @@ struct nouveau_pm_voltage { +@@ -427,64 +433,91 @@ int nr_level; }; @@ -56369,20 +56283,20 @@ + u8 tUNK_18; + u8 tCWL; + u8 tUNK_20, tUNK_21; - }; - --/* nouveau_mem.c */ --void nv30_mem_timing_entry(struct drm_device *dev, struct nouveau_pm_tbl_header *hdr, -- struct nouveau_pm_tbl_entry *e, uint8_t magic_number, -- struct nouveau_pm_memtiming *timing); ++}; ++ +struct nouveau_pm_profile; +struct nouveau_pm_profile_func { + void (*destroy)(struct nouveau_pm_profile *); + void (*init)(struct nouveau_pm_profile *); + void (*fini)(struct nouveau_pm_profile *); + struct nouveau_pm_level *(*select)(struct nouveau_pm_profile *); -+}; -+ + }; + +-/* nouveau_mem.c */ +-void nv30_mem_timing_entry(struct drm_device *dev, struct nouveau_pm_tbl_header *hdr, +- struct nouveau_pm_tbl_entry *e, uint8_t magic_number, +- struct nouveau_pm_memtiming *timing); +struct nouveau_pm_profile { + const struct nouveau_pm_profile_func *func; + struct list_head head; @@ -56412,7 +56326,7 @@ u32 unka0; /* nva3:nvc0 */ u32 hub01; /* nvc0- */ u32 hub06; /* nvc0- */ -@@ -493,9 +526,6 @@ struct nouveau_pm_level { +@@ -493,9 +526,6 @@ u32 volt_min; /* microvolts */ u32 volt_max; u8 fanspeed; @@ -56422,7 +56336,7 @@ }; struct nouveau_pm_temp_sensor_constants { -@@ -512,19 +542,26 @@ struct nouveau_pm_threshold_temp { +@@ -512,19 +542,26 @@ s16 fan_boost; }; @@ -56454,7 +56368,7 @@ struct nouveau_pm_level boot; struct nouveau_pm_level *cur; -@@ -532,19 +569,14 @@ struct nouveau_pm_engine { +@@ -532,19 +569,14 @@ struct device *hwmon; struct notifier_block acpi_nb; @@ -56477,7 +56391,7 @@ int (*temp_get)(struct drm_device *); }; -@@ -661,14 +693,15 @@ struct nv04_mode_state { +@@ -661,14 +693,15 @@ }; enum nouveau_card_type { @@ -56495,7 +56409,7 @@ }; struct drm_nouveau_private { -@@ -764,8 +797,22 @@ struct drm_nouveau_private { +@@ -764,8 +797,22 @@ } tile; /* VRAM/fb configuration */ @@ -56518,7 +56432,7 @@ uint64_t fb_available_size; uint64_t fb_mappable_pages; -@@ -780,6 +827,8 @@ struct drm_nouveau_private { +@@ -780,6 +827,8 @@ struct nouveau_vm *chan_vm; struct nvbios vbios; @@ -56527,7 +56441,7 @@ struct nv04_mode_state mode_reg; struct nv04_mode_state saved_reg; -@@ -836,6 +885,7 @@ extern int nouveau_uscript_lvds; +@@ -836,6 +885,7 @@ extern int nouveau_uscript_tmds; extern int nouveau_vram_pushbuf; extern int nouveau_vram_notify; @@ -56535,7 +56449,7 @@ extern int nouveau_fbpercrtc; extern int nouveau_tv_disable; extern char *nouveau_tv_norm; -@@ -850,6 +900,7 @@ extern char *nouveau_perflvl; +@@ -850,6 +900,7 @@ extern int nouveau_perflvl_wr; extern int nouveau_msi; extern int nouveau_ctxfw; @@ -56543,7 +56457,7 @@ extern int nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state); extern int nouveau_pci_resume(struct pci_dev *pdev); -@@ -883,8 +934,12 @@ extern void nouveau_mem_gart_fini(struct drm_device *); +@@ -883,8 +934,12 @@ extern int nouveau_mem_init_agp(struct drm_device *); extern int nouveau_mem_reset_agp(struct drm_device *); extern void nouveau_mem_close(struct drm_device *); @@ -56557,7 +56471,7 @@ extern struct nouveau_tile_reg *nv10_mem_set_tiling( struct drm_device *dev, uint32_t addr, uint32_t size, uint32_t pitch, uint32_t flags); -@@ -1000,7 +1055,10 @@ extern int nouveau_sgdma_init(struct drm_device *); +@@ -1000,7 +1055,10 @@ extern void nouveau_sgdma_takedown(struct drm_device *); extern uint32_t nouveau_sgdma_get_physical(struct drm_device *, uint32_t offset); @@ -56569,7 +56483,7 @@ /* nouveau_debugfs.c */ #if defined(CONFIG_DRM_NOUVEAU_DEBUG) -@@ -1032,8 +1090,7 @@ nouveau_debugfs_channel_fini(struct nouveau_channel *chan) +@@ -1032,8 +1090,7 @@ #endif /* nouveau_dma.c */ @@ -56579,7 +56493,7 @@ extern int nouveau_dma_wait(struct nouveau_channel *, int slots, int size); /* nouveau_acpi.c */ -@@ -1041,12 +1098,14 @@ extern int nouveau_dma_wait(struct nouveau_channel *, int slots, int size); +@@ -1041,12 +1098,14 @@ #if defined(CONFIG_ACPI) void nouveau_register_dsm_handler(void); void nouveau_unregister_dsm_handler(void); @@ -56594,7 +56508,7 @@ static inline bool nouveau_acpi_rom_supported(struct pci_dev *pdev) { return false; } static inline int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len) { return -EINVAL; } static inline int nouveau_acpi_edid(struct drm_device *dev, struct drm_connector *connector) { return -EINVAL; } -@@ -1072,8 +1131,6 @@ extern int nouveau_run_vbios_init(struct drm_device *); +@@ -1072,8 +1131,6 @@ extern void nouveau_bios_run_init_table(struct drm_device *, uint16_t table, struct dcb_entry *, int crtc); extern void nouveau_bios_init_exec(struct drm_device *, uint16_t table); @@ -56603,7 +56517,7 @@ extern struct dcb_connector_table_entry * nouveau_bios_connector_entry(struct drm_device *, int index); extern u32 get_pll_register(struct drm_device *, enum pll_types); -@@ -1091,24 +1148,26 @@ extern int call_lvds_script(struct drm_device *, struct dcb_entry *, int head, +@@ -1091,24 +1148,26 @@ enum LVDS_script, int pxclk); bool bios_encoder_match(struct dcb_entry *, u32 hash); @@ -56637,7 +56551,7 @@ extern int nv10_fb_init(struct drm_device *); extern void nv10_fb_takedown(struct drm_device *); extern void nv10_fb_init_tile_region(struct drm_device *dev, int i, -@@ -1117,6 +1176,16 @@ extern void nv10_fb_init_tile_region(struct drm_device *dev, int i, +@@ -1117,6 +1176,16 @@ extern void nv10_fb_set_tile_region(struct drm_device *dev, int i); extern void nv10_fb_free_tile_region(struct drm_device *dev, int i); @@ -56654,7 +56568,7 @@ /* nv30_fb.c */ extern int nv30_fb_init(struct drm_device *); extern void nv30_fb_takedown(struct drm_device *); -@@ -1126,6 +1195,7 @@ extern void nv30_fb_init_tile_region(struct drm_device *dev, int i, +@@ -1126,6 +1195,7 @@ extern void nv30_fb_free_tile_region(struct drm_device *dev, int i); /* nv40_fb.c */ @@ -56662,7 +56576,7 @@ extern int nv40_fb_init(struct drm_device *); extern void nv40_fb_takedown(struct drm_device *); extern void nv40_fb_set_tile_region(struct drm_device *dev, int i); -@@ -1222,6 +1292,9 @@ extern int nvc0_graph_isr_chid(struct drm_device *dev, u64 inst); +@@ -1222,6 +1292,9 @@ /* nv84_crypt.c */ extern int nv84_crypt_create(struct drm_device *); @@ -56672,7 +56586,7 @@ /* nva3_copy.c */ extern int nva3_copy_create(struct drm_device *dev); -@@ -1234,6 +1307,17 @@ extern int nv31_mpeg_create(struct drm_device *dev); +@@ -1234,6 +1307,17 @@ /* nv50_mpeg.c */ extern int nv50_mpeg_create(struct drm_device *dev); @@ -56690,7 +56604,7 @@ /* nv04_instmem.c */ extern int nv04_instmem_init(struct drm_device *); extern void nv04_instmem_takedown(struct drm_device *); -@@ -1311,13 +1395,19 @@ extern int nv17_tv_create(struct drm_connector *, struct dcb_entry *); +@@ -1311,13 +1395,19 @@ extern int nv04_display_early_init(struct drm_device *); extern void nv04_display_late_takedown(struct drm_device *); extern int nv04_display_create(struct drm_device *); @@ -56712,7 +56626,7 @@ /* nv04_crtc.c */ extern int nv04_crtc_create(struct drm_device *, int index); -@@ -1412,6 +1502,10 @@ extern int nouveau_gem_ioctl_info(struct drm_device *, void *, +@@ -1412,6 +1502,10 @@ struct drm_file *); /* nouveau_display.c */ @@ -56723,7 +56637,7 @@ int nouveau_vblank_enable(struct drm_device *dev, int crtc); void nouveau_vblank_disable(struct drm_device *dev, int crtc); int nouveau_crtc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb, -@@ -1426,23 +1520,22 @@ int nouveau_display_dumb_destroy(struct drm_file *, struct drm_device *, +@@ -1426,23 +1520,22 @@ uint32_t handle); /* nv10_gpio.c */ @@ -56747,19 +56661,18 @@ -void nv50_gpio_irq_unregister(struct drm_device *, enum dcb_gpio_tag, - void (*)(void *, int), void *); -bool nv50_gpio_irq_enable(struct drm_device *, enum dcb_gpio_tag, bool on); -- --/* nv50_calc. */ +int nv50_gpio_drive(struct drm_device *dev, int line, int dir, int out); +int nv50_gpio_sense(struct drm_device *dev, int line); +void nv50_gpio_irq_enable(struct drm_device *, int line, bool on); +int nvd0_gpio_drive(struct drm_device *dev, int line, int dir, int out); +int nvd0_gpio_sense(struct drm_device *dev, int line); -+ + +-/* nv50_calc. */ +/* nv50_calc.c */ int nv50_calc_pll(struct drm_device *, struct pll_lims *, int clk, int *N1, int *M1, int *N2, int *M2, int *P); int nva3_calc_pll(struct drm_device *, struct pll_lims *, -@@ -1565,6 +1658,13 @@ extern void nv_wo32(struct nouveau_gpuobj *, u32 offset, u32 val); +@@ -1565,6 +1658,13 @@ #define NV_TRACEWARN(d, fmt, arg...) NV_PRINTK(KERN_NOTICE, d, fmt, ##arg) #define NV_TRACE(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) #define NV_WARN(d, fmt, arg...) NV_PRINTK(KERN_WARNING, d, fmt, ##arg) @@ -56773,7 +56686,7 @@ /* nouveau_reg_debug bitmask */ enum { -@@ -1652,6 +1752,7 @@ nv44_graph_class(struct drm_device *dev) +@@ -1652,6 +1752,7 @@ #define NV_MEM_ACCESS_RW (NV_MEM_ACCESS_RO | NV_MEM_ACCESS_WO) #define NV_MEM_ACCESS_SYS 4 #define NV_MEM_ACCESS_VM 8 @@ -56781,7 +56694,7 @@ #define NV_MEM_TARGET_VRAM 0 #define NV_MEM_TARGET_PCI 1 -@@ -1662,13 +1763,27 @@ nv44_graph_class(struct drm_device *dev) +@@ -1662,13 +1763,27 @@ #define NV_MEM_TYPE_VM 0x7f #define NV_MEM_COMP_VM 0x03 @@ -56814,10 +56727,10 @@ #define NV_SW_DMA_VBLSEM 0x0000018c #define NV_SW_VBLSEM_OFFSET 0x00000400 #define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404 -diff --git a/drivers/gpu/drm/nouveau/nouveau_encoder.h b/drivers/gpu/drm/nouveau/nouveau_encoder.h -index e5d6e3f..3dc14a3 100644 ---- a/drivers/gpu/drm/nouveau/nouveau_encoder.h -+++ b/drivers/gpu/drm/nouveau/nouveau_encoder.h +Index: linux-3.2.46/drivers/gpu/drm/nouveau/nouveau_encoder.h +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/nouveau/nouveau_encoder.h 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/nouveau/nouveau_encoder.h 2013-07-26 19:26:23.000000000 +0000 @@ -32,6 +32,14 @@ #define NV_DPMS_CLEARED 0x80 @@ -56833,7 +56746,7 @@ struct nouveau_encoder { struct drm_encoder_slave base; -@@ -78,9 +86,19 @@ get_slave_funcs(struct drm_encoder *enc) +@@ -78,9 +86,19 @@ return to_encoder_slave(enc)->slave_funcs; } @@ -56853,11 +56766,11 @@ + #endif /* __NOUVEAU_ENCODER_H__ */ -diff --git a/drivers/gpu/drm/nouveau/nouveau_fb.h b/drivers/gpu/drm/nouveau/nouveau_fb.h -index 95c843e..f3fb649 100644 ---- a/drivers/gpu/drm/nouveau/nouveau_fb.h -+++ b/drivers/gpu/drm/nouveau/nouveau_fb.h -@@ -42,8 +42,6 @@ nouveau_framebuffer(struct drm_framebuffer *fb) +Index: linux-3.2.46/drivers/gpu/drm/nouveau/nouveau_fb.h +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/nouveau/nouveau_fb.h 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/nouveau/nouveau_fb.h 2013-07-26 19:26:23.000000000 +0000 +@@ -42,8 +42,6 @@ return container_of(fb, struct nouveau_framebuffer, base); } @@ -56867,10 +56780,10 @@ - struct drm_mode_fb_cmd *mode_cmd, struct nouveau_bo *nvbo); + struct drm_mode_fb_cmd2 *mode_cmd, struct nouveau_bo *nvbo); #endif /* __NOUVEAU_FB_H__ */ -diff --git a/drivers/gpu/drm/nouveau/nouveau_fbcon.c b/drivers/gpu/drm/nouveau/nouveau_fbcon.c -index cc0801d..6fd2211 100644 ---- a/drivers/gpu/drm/nouveau/nouveau_fbcon.c -+++ b/drivers/gpu/drm/nouveau/nouveau_fbcon.c +Index: linux-3.2.46/drivers/gpu/drm/nouveau/nouveau_fbcon.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/nouveau/nouveau_fbcon.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/nouveau/nouveau_fbcon.c 2013-07-26 19:26:23.000000000 +0000 @@ -36,6 +36,7 @@ #include #include @@ -56879,7 +56792,7 @@ #include "drmP.h" #include "drm.h" -@@ -281,7 +282,7 @@ nouveau_fbcon_create(struct nouveau_fbdev *nfbdev, +@@ -281,7 +282,7 @@ struct nouveau_framebuffer *nouveau_fb; struct nouveau_channel *chan; struct nouveau_bo *nvbo; @@ -56888,7 +56801,7 @@ struct pci_dev *pdev = dev->pdev; struct device *device = &pdev->dev; int size, ret; -@@ -289,12 +290,13 @@ nouveau_fbcon_create(struct nouveau_fbdev *nfbdev, +@@ -289,12 +290,13 @@ mode_cmd.width = sizes->surface_width; mode_cmd.height = sizes->surface_height; @@ -56907,7 +56820,7 @@ size = roundup(size, PAGE_SIZE); ret = nouveau_gem_new(dev, size, 0, NOUVEAU_GEM_DOMAIN_VRAM, -@@ -369,7 +371,7 @@ nouveau_fbcon_create(struct nouveau_fbdev *nfbdev, +@@ -369,7 +371,7 @@ info->screen_base = nvbo_kmap_obj_iovirtual(nouveau_fb->nvbo); info->screen_size = size; @@ -56916,7 +56829,7 @@ drm_fb_helper_fill_var(info, &nfbdev->helper, sizes->fb_width, sizes->fb_height); /* Set aperture base/size for vesafb takeover */ -@@ -379,11 +381,7 @@ nouveau_fbcon_create(struct nouveau_fbdev *nfbdev, +@@ -379,11 +381,7 @@ goto out_unref; } @@ -56929,7 +56842,7 @@ mutex_unlock(&dev->struct_mutex); -@@ -547,7 +545,13 @@ void nouveau_fbcon_restore_accel(struct drm_device *dev) +@@ -547,7 +545,13 @@ void nouveau_fbcon_set_suspend(struct drm_device *dev, int state) { struct drm_nouveau_private *dev_priv = dev->dev_private; @@ -56943,11 +56856,11 @@ } void nouveau_fbcon_zfill_all(struct drm_device *dev) -diff --git a/drivers/gpu/drm/nouveau/nouveau_fence.c b/drivers/gpu/drm/nouveau/nouveau_fence.c -index 2f6daae..c1dc20f 100644 ---- a/drivers/gpu/drm/nouveau/nouveau_fence.c -+++ b/drivers/gpu/drm/nouveau/nouveau_fence.c -@@ -93,18 +93,17 @@ nouveau_fence_update(struct nouveau_channel *chan) +Index: linux-3.2.46/drivers/gpu/drm/nouveau/nouveau_fence.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/nouveau/nouveau_fence.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/nouveau/nouveau_fence.c 2013-07-26 19:26:23.000000000 +0000 +@@ -93,18 +93,17 @@ } list_for_each_entry_safe(fence, tmp, &chan->fence.pending, entry) { @@ -56971,7 +56884,7 @@ out: spin_unlock(&chan->fence.lock); } -@@ -165,9 +164,9 @@ nouveau_fence_emit(struct nouveau_fence *fence) +@@ -165,9 +164,9 @@ if (USE_REFCNT(dev)) { if (dev_priv->card_type < NV_C0) @@ -56983,7 +56896,7 @@ } else { BEGIN_RING(chan, NvSubSw, 0x0150, 1); } -@@ -344,7 +343,7 @@ semaphore_acquire(struct nouveau_channel *chan, struct nouveau_semaphore *sema) +@@ -344,7 +343,7 @@ if (ret) return ret; @@ -56992,7 +56905,7 @@ OUT_RING (chan, NvSema); OUT_RING (chan, offset); OUT_RING (chan, 1); -@@ -354,9 +353,9 @@ semaphore_acquire(struct nouveau_channel *chan, struct nouveau_semaphore *sema) +@@ -354,9 +353,9 @@ if (ret) return ret; @@ -57004,7 +56917,7 @@ OUT_RING (chan, upper_32_bits(offset)); OUT_RING (chan, lower_32_bits(offset)); OUT_RING (chan, 1); -@@ -366,7 +365,7 @@ semaphore_acquire(struct nouveau_channel *chan, struct nouveau_semaphore *sema) +@@ -366,7 +365,7 @@ if (ret) return ret; @@ -57013,7 +56926,7 @@ OUT_RING (chan, upper_32_bits(offset)); OUT_RING (chan, lower_32_bits(offset)); OUT_RING (chan, 1); -@@ -397,10 +396,10 @@ semaphore_release(struct nouveau_channel *chan, struct nouveau_semaphore *sema) +@@ -397,10 +396,10 @@ if (ret) return ret; @@ -57026,7 +56939,7 @@ OUT_RING (chan, 1); } else if (dev_priv->chipset < 0xc0) { -@@ -408,9 +407,9 @@ semaphore_release(struct nouveau_channel *chan, struct nouveau_semaphore *sema) +@@ -408,9 +407,9 @@ if (ret) return ret; @@ -57038,7 +56951,7 @@ OUT_RING (chan, upper_32_bits(offset)); OUT_RING (chan, lower_32_bits(offset)); OUT_RING (chan, 1); -@@ -420,7 +419,7 @@ semaphore_release(struct nouveau_channel *chan, struct nouveau_semaphore *sema) +@@ -420,7 +419,7 @@ if (ret) return ret; @@ -57047,7 +56960,7 @@ OUT_RING (chan, upper_32_bits(offset)); OUT_RING (chan, lower_32_bits(offset)); OUT_RING (chan, 1); -@@ -510,7 +509,7 @@ nouveau_fence_channel_init(struct nouveau_channel *chan) +@@ -510,7 +509,7 @@ if (ret) return ret; @@ -57056,11 +56969,11 @@ OUT_RING (chan, NvSw); FIRE_RING (chan); } -diff --git a/drivers/gpu/drm/nouveau/nouveau_gem.c b/drivers/gpu/drm/nouveau/nouveau_gem.c -index 7ce3fde..ed52a6f 100644 ---- a/drivers/gpu/drm/nouveau/nouveau_gem.c -+++ b/drivers/gpu/drm/nouveau/nouveau_gem.c -@@ -426,9 +426,7 @@ validate_list(struct nouveau_channel *chan, struct list_head *list, +Index: linux-3.2.46/drivers/gpu/drm/nouveau/nouveau_gem.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/nouveau/nouveau_gem.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/nouveau/nouveau_gem.c 2013-07-26 19:26:23.000000000 +0000 +@@ -426,9 +426,7 @@ return ret; } @@ -57070,7 +56983,7 @@ if (unlikely(ret)) { if (ret != -ERESTARTSYS) NV_ERROR(dev, "fail ttm_validate\n"); -@@ -678,19 +676,13 @@ nouveau_gem_ioctl_pushbuf(struct drm_device *dev, void *data, +@@ -678,19 +676,13 @@ return PTR_ERR(bo); } @@ -57091,11 +57004,10 @@ } /* Validate buffer list */ -diff --git a/drivers/gpu/drm/nouveau/nouveau_gpio.c b/drivers/gpu/drm/nouveau/nouveau_gpio.c -new file mode 100644 -index 0000000..a580cc6 ---- /dev/null -+++ b/drivers/gpu/drm/nouveau/nouveau_gpio.c +Index: linux-3.2.46/drivers/gpu/drm/nouveau/nouveau_gpio.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/nouveau/nouveau_gpio.c 2013-07-26 19:26:23.000000000 +0000 @@ -0,0 +1,400 @@ +/* + * Copyright 2011 Red Hat Inc. @@ -57497,11 +57409,10 @@ + } + } +} -diff --git a/drivers/gpu/drm/nouveau/nouveau_gpio.h b/drivers/gpu/drm/nouveau/nouveau_gpio.h -new file mode 100644 -index 0000000..64c5cb0 ---- /dev/null -+++ b/drivers/gpu/drm/nouveau/nouveau_gpio.h +Index: linux-3.2.46/drivers/gpu/drm/nouveau/nouveau_gpio.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/nouveau/nouveau_gpio.h 2013-07-26 19:26:23.000000000 +0000 @@ -0,0 +1,71 @@ +/* + * Copyright 2011 Red Hat Inc. @@ -57574,11 +57485,10 @@ +} + +#endif -diff --git a/drivers/gpu/drm/nouveau/nouveau_hdmi.c b/drivers/gpu/drm/nouveau/nouveau_hdmi.c -new file mode 100644 -index 0000000..c3de363 ---- /dev/null -+++ b/drivers/gpu/drm/nouveau/nouveau_hdmi.c +Index: linux-3.2.46/drivers/gpu/drm/nouveau/nouveau_hdmi.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/nouveau/nouveau_hdmi.c 2013-07-26 19:26:23.000000000 +0000 @@ -0,0 +1,260 @@ +/* + * Copyright 2011 Red Hat Inc. @@ -57840,11 +57750,10 @@ + + nouveau_audio_mode_set(encoder, mode); +} -diff --git a/drivers/gpu/drm/nouveau/nouveau_hwsq.h b/drivers/gpu/drm/nouveau/nouveau_hwsq.h -new file mode 100644 -index 0000000..6976875 ---- /dev/null -+++ b/drivers/gpu/drm/nouveau/nouveau_hwsq.h +Index: linux-3.2.46/drivers/gpu/drm/nouveau/nouveau_hwsq.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/nouveau/nouveau_hwsq.h 2013-07-26 19:26:23.000000000 +0000 @@ -0,0 +1,115 @@ +/* + * Copyright 2010 Red Hat Inc. @@ -57961,10 +57870,10 @@ +} + +#endif -diff --git a/drivers/gpu/drm/nouveau/nouveau_i2c.c b/drivers/gpu/drm/nouveau/nouveau_i2c.c -index d39b220..77e5646 100644 ---- a/drivers/gpu/drm/nouveau/nouveau_i2c.c -+++ b/drivers/gpu/drm/nouveau/nouveau_i2c.c +Index: linux-3.2.46/drivers/gpu/drm/nouveau/nouveau_i2c.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/nouveau/nouveau_i2c.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/nouveau/nouveau_i2c.c 2013-07-26 19:26:23.000000000 +0000 @@ -30,83 +30,83 @@ #include "nouveau_hw.h" @@ -58113,7 +58022,7 @@ } static const uint32_t nv50_i2c_port[] = { -@@ -114,177 +114,223 @@ static const uint32_t nv50_i2c_port[] = { +@@ -114,177 +114,223 @@ 0x00e254, 0x00e274, 0x00e764, 0x00e780, 0x00e79c, 0x00e7b8 }; @@ -58121,24 +58030,15 @@ -static int -nv50_i2c_getscl(void *data) --{ -- struct nouveau_i2c_chan *i2c = data; -- struct drm_device *dev = i2c->dev; -- -- return !!(nv_rd32(dev, i2c->rd) & 1); --} -- -- --static int --nv50_i2c_getsda(void *data) +static u8 * +i2c_table(struct drm_device *dev, u8 *version) { - struct nouveau_i2c_chan *i2c = data; - struct drm_device *dev = i2c->dev; - -- return !!(nv_rd32(dev, i2c->rd) & 2); +- return !!(nv_rd32(dev, i2c->rd) & 1); -} +- + u8 *dcb = dcb_table(dev), *i2c = NULL; + if (dcb) { + if (dcb[0] >= 0x15) @@ -58147,10 +58047,11 @@ + i2c = ROMPTR(dev, dcb[4]); + } --static void --nv50_i2c_setscl(void *data, int state) +-static int +-nv50_i2c_getsda(void *data) -{ - struct nouveau_i2c_chan *i2c = data; +- struct drm_device *dev = i2c->dev; + /* early revisions had no version number, use dcb version */ + if (i2c) { + *version = dcb[0]; @@ -58158,12 +58059,12 @@ + *version = i2c[0]; + } -- nv_wr32(i2c->dev, i2c->wr, 4 | (i2c->data ? 2 : 0) | (state ? 1 : 0)); +- return !!(nv_rd32(dev, i2c->rd) & 2); + return i2c; } -static void --nv50_i2c_setsda(void *data, int state) +-nv50_i2c_setscl(void *data, int state) +int +nouveau_i2c_init(struct drm_device *dev) { @@ -58202,8 +58103,7 @@ + if (i2c[7]) legacy[1][1] = i2c[7]; + } -- nv_mask(i2c->dev, i2c->wr, 0x00000006, 4 | (state ? 2 : 0)); -- i2c->data = state; +- nv_wr32(i2c->dev, i2c->wr, 4 | (i2c->data ? 2 : 0) | (state ? 1 : 0)); -} + if (version >= 0x30) { + entry = i2c[1] + i2c; @@ -58220,12 +58120,10 @@ + recordlen = 4; + } --static int --nvd0_i2c_getscl(void *data) +-static void +-nv50_i2c_setsda(void *data, int state) -{ - struct nouveau_i2c_chan *i2c = data; -- return !!(nv_rd32(i2c->dev, i2c->rd) & 0x10); --} + for (i = 0; i < entries; i++, entry += recordlen) { + port = kzalloc(sizeof(*port), GFP_KERNEL); + if (port == NULL) { @@ -58233,11 +58131,8 @@ + return -ENOMEM; + } --static int --nvd0_i2c_getsda(void *data) --{ -- struct nouveau_i2c_chan *i2c = data; -- return !!(nv_rd32(i2c->dev, i2c->rd) & 0x20); +- nv_mask(i2c->dev, i2c->wr, 0x00000006, 4 | (state ? 2 : 0)); +- i2c->data = state; -} + port->type = entry[3]; + if (version < 0x30) { @@ -58246,19 +58141,23 @@ + port->type = 0xff; + } --int --nouveau_i2c_init(struct drm_device *dev, struct dcb_i2c_entry *entry, int index) +-static int +-nvd0_i2c_getscl(void *data) -{ -- struct drm_nouveau_private *dev_priv = dev->dev_private; -- struct nouveau_i2c_chan *i2c; -- int ret; +- struct nouveau_i2c_chan *i2c = data; +- return !!(nv_rd32(i2c->dev, i2c->rd) & 0x10); +-} + if (port->type == 0xff) { + kfree(port); + continue; + } -- if (entry->chan) -- return -EEXIST; +-static int +-nvd0_i2c_getsda(void *data) +-{ +- struct nouveau_i2c_chan *i2c = data; +- return !!(nv_rd32(i2c->dev, i2c->rd) & 0x20); +-} + switch (port->type) { + case 0: /* NV04:NV50 */ + port->drive = entry[0]; @@ -58289,11 +58188,12 @@ + break; + } -- if (dev_priv->card_type >= NV_50 && -- dev_priv->card_type <= NV_C0 && entry->read >= NV50_I2C_PORTS) { -- NV_ERROR(dev, "unknown i2c port %d\n", entry->read); -- return -EINVAL; -- } +-int +-nouveau_i2c_init(struct drm_device *dev, struct dcb_i2c_entry *entry, int index) +-{ +- struct drm_nouveau_private *dev_priv = dev->dev_private; +- struct nouveau_i2c_chan *i2c; +- int ret; + if (!port->adapter.algo && !port->drive) { + NV_ERROR(dev, "I2C%d: type %d index %x/%x unknown\n", + i, port->type, port->drive, port->sense); @@ -58301,6 +58201,37 @@ + continue; + } +- if (entry->chan) +- return -EEXIST; ++ snprintf(port->adapter.name, sizeof(port->adapter.name), ++ "nouveau-%s-%d", pci_name(dev->pdev), i); ++ port->adapter.owner = THIS_MODULE; ++ port->adapter.dev.parent = &dev->pdev->dev; ++ port->dev = dev; ++ port->index = i; ++ port->dcb = ROM32(entry[0]); ++ i2c_set_adapdata(&port->adapter, i2c); ++ ++ if (port->adapter.algo != &nouveau_dp_i2c_algo) { ++ port->adapter.algo_data = &port->bit; ++ port->bit.udelay = 10; ++ port->bit.timeout = usecs_to_jiffies(2200); ++ port->bit.data = port; ++ port->bit.setsda = i2c_drive_sda; ++ port->bit.setscl = i2c_drive_scl; ++ port->bit.getsda = i2c_sense_sda; ++ port->bit.getscl = i2c_sense_scl; ++ ++ i2c_drive_scl(port, 0); ++ i2c_drive_sda(port, 1); ++ i2c_drive_scl(port, 1); + +- if (dev_priv->card_type >= NV_50 && +- dev_priv->card_type <= NV_C0 && entry->read >= NV50_I2C_PORTS) { +- NV_ERROR(dev, "unknown i2c port %d\n", entry->read); +- return -EINVAL; +- } +- - i2c = kzalloc(sizeof(*i2c), GFP_KERNEL); - if (i2c == NULL) - return -ENOMEM; @@ -58330,38 +58261,13 @@ - i2c->bit.getscl = nv50_i2c_getscl; - i2c->rd = nv50_i2c_port[entry->read]; - i2c->wr = i2c->rd; -+ snprintf(port->adapter.name, sizeof(port->adapter.name), -+ "nouveau-%s-%d", pci_name(dev->pdev), i); -+ port->adapter.owner = THIS_MODULE; -+ port->adapter.dev.parent = &dev->pdev->dev; -+ port->dev = dev; -+ port->index = i; -+ port->dcb = ROM32(entry[0]); -+ i2c_set_adapdata(&port->adapter, i2c); -+ -+ if (port->adapter.algo != &nouveau_dp_i2c_algo) { -+ port->adapter.algo_data = &port->bit; -+ port->bit.udelay = 10; -+ port->bit.timeout = usecs_to_jiffies(2200); -+ port->bit.data = port; -+ port->bit.setsda = i2c_drive_sda; -+ port->bit.setscl = i2c_drive_scl; -+ port->bit.getsda = i2c_sense_sda; -+ port->bit.getscl = i2c_sense_scl; -+ -+ i2c_drive_scl(port, 0); -+ i2c_drive_sda(port, 1); -+ i2c_drive_scl(port, 1); -+ + ret = i2c_bit_add_bus(&port->adapter); } else { - i2c->bit.getsda = nvd0_i2c_getsda; - i2c->bit.getscl = nvd0_i2c_getscl; - i2c->rd = 0x00d014 + (entry->read * 0x20); - i2c->wr = i2c->rd; -+ port->adapter.algo = &nouveau_dp_i2c_algo; -+ ret = i2c_add_adapter(&port->adapter); - } +- } - break; - case 6: - i2c->rd = entry->read; @@ -58373,7 +58279,7 @@ - kfree(i2c); - return -EINVAL; - } - +- - snprintf(i2c->adapter.name, sizeof(i2c->adapter.name), - "nouveau-%s-%d", pci_name(dev->pdev), index); - i2c->adapter.owner = THIS_MODULE; @@ -58391,16 +58297,20 @@ - i2c->adapter.algo = &nouveau_dp_i2c_algo; - ret = i2c_add_adapter(&i2c->adapter); - } -+ if (ret) { -+ NV_ERROR(dev, "I2C%d: failed register: %d\n", i, ret); -+ kfree(port); -+ continue; ++ port->adapter.algo = &nouveau_dp_i2c_algo; ++ ret = i2c_add_adapter(&port->adapter); + } - if (ret) { - NV_ERROR(dev, "Failed to register i2c %d\n", index); - kfree(i2c); - return ret; ++ if (ret) { ++ NV_ERROR(dev, "I2C%d: failed register: %d\n", i, ret); ++ kfree(port); ++ continue; ++ } ++ + list_add_tail(&port->head, &dev_priv->i2c_ports); } @@ -58433,7 +58343,9 @@ struct drm_nouveau_private *dev_priv = dev->dev_private; - struct dcb_i2c_entry *i2c = &dev_priv->vbios.dcb.i2c[index]; + struct nouveau_i2c_chan *port; -+ + +- if (index >= DCB_MAX_NUM_I2C_ENTRIES) +- return NULL; + if (index == NV_I2C_DEFAULT(0) || + index == NV_I2C_DEFAULT(1)) { + u8 version, *i2c = i2c_table(dev, &version); @@ -58447,20 +58359,18 @@ + } + } -- if (index >= DCB_MAX_NUM_I2C_ENTRIES) -- return NULL; +- if (dev_priv->card_type >= NV_50 && (i2c->entry & 0x00000100)) { +- uint32_t reg = 0xe500, val; + list_for_each_entry(port, &dev_priv->i2c_ports, head) { + if (port->index == index) + break; + } -- if (dev_priv->card_type >= NV_50 && (i2c->entry & 0x00000100)) { -- uint32_t reg = 0xe500, val; -+ if (&port->head == &dev_priv->i2c_ports) -+ return NULL; - - if (i2c->port_type == 6) { - reg += i2c->read * 0x50; ++ if (&port->head == &dev_priv->i2c_ports) ++ return NULL; ++ + if (dev_priv->card_type >= NV_50 && (port->dcb & 0x00000100)) { + u32 reg = 0x00e500, val; + if (port->type == 6) { @@ -58472,7 +58382,7 @@ val = 0xe001; } -@@ -294,9 +340,7 @@ nouveau_i2c_find(struct drm_device *dev, int index) +@@ -294,9 +340,7 @@ nv_mask(dev, reg + 0x00, 0x0000f003, val); } @@ -58483,7 +58393,7 @@ } bool -@@ -331,9 +375,13 @@ nouveau_i2c_identify(struct drm_device *dev, const char *what, +@@ -331,9 +375,13 @@ struct nouveau_i2c_chan *i2c = nouveau_i2c_find(dev, index); int i; @@ -58499,17 +58409,17 @@ if (nouveau_probe_i2c_addr(i2c, info[i].addr) && (!match || match(i2c, &info[i]))) { NV_INFO(dev, "Detected %s: %s\n", what, info[i].type); -@@ -342,6 +390,5 @@ nouveau_i2c_identify(struct drm_device *dev, const char *what, +@@ -342,6 +390,5 @@ } NV_DEBUG(dev, "No devices found.\n"); - return -ENODEV; } -diff --git a/drivers/gpu/drm/nouveau/nouveau_i2c.h b/drivers/gpu/drm/nouveau/nouveau_i2c.h -index 422b62f..1d08389 100644 ---- a/drivers/gpu/drm/nouveau/nouveau_i2c.h -+++ b/drivers/gpu/drm/nouveau/nouveau_i2c.h +Index: linux-3.2.46/drivers/gpu/drm/nouveau/nouveau_i2c.h +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/nouveau/nouveau_i2c.h 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/nouveau/nouveau_i2c.h 2013-07-26 19:26:23.000000000 +0000 @@ -27,20 +27,26 @@ #include #include "drm_dp_helper.h" @@ -58544,10 +58454,10 @@ bool nouveau_probe_i2c_addr(struct nouveau_i2c_chan *i2c, int addr); int nouveau_i2c_identify(struct drm_device *dev, const char *what, struct i2c_board_info *info, -diff --git a/drivers/gpu/drm/nouveau/nouveau_mem.c b/drivers/gpu/drm/nouveau/nouveau_mem.c -index 36bec48..b08065f 100644 ---- a/drivers/gpu/drm/nouveau/nouveau_mem.c -+++ b/drivers/gpu/drm/nouveau/nouveau_mem.c +Index: linux-3.2.46/drivers/gpu/drm/nouveau/nouveau_mem.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/nouveau/nouveau_mem.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/nouveau/nouveau_mem.c 2013-07-26 19:26:23.000000000 +0000 @@ -26,7 +26,8 @@ * DEALINGS IN THE SOFTWARE. * @@ -58558,7 +58468,7 @@ */ -@@ -192,75 +193,6 @@ nouveau_mem_gart_fini(struct drm_device *dev) +@@ -192,75 +193,6 @@ } } @@ -58634,7 +58544,7 @@ bool nouveau_mem_flags_valid(struct drm_device *dev, u32 tile_flags) { -@@ -385,11 +317,29 @@ nouveau_mem_init_agp(struct drm_device *dev) +@@ -385,11 +317,29 @@ return 0; } @@ -58664,7 +58574,7 @@ int ret, dma_bits; dma_bits = 32; -@@ -407,6 +357,12 @@ nouveau_mem_vram_init(struct drm_device *dev) +@@ -407,6 +357,12 @@ ret = pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(dma_bits)); if (ret) return ret; @@ -58677,7 +58587,7 @@ ret = nouveau_ttm_global_init(dev_priv); if (ret) -@@ -421,7 +377,21 @@ nouveau_mem_vram_init(struct drm_device *dev) +@@ -421,7 +377,21 @@ return ret; } @@ -58700,7 +58610,7 @@ if (dev_priv->vram_sys_base) { NV_INFO(dev, "Stolen system memory at: 0x%010llx\n", dev_priv->vram_sys_base); -@@ -502,216 +472,617 @@ nouveau_mem_gart_init(struct drm_device *dev) +@@ -502,216 +472,617 @@ return 0; } @@ -58734,9 +58644,6 @@ - (e->tCL + 2 - magic_number); - timing->reg_2 = (magic_number << 24 | e->tUNK_12 << 16 | e->tUNK_11 << 8 | e->tUNK_10); - timing->reg_2 |= 0x20200000; -- -- NV_DEBUG(dev, "Entry %d: 220: %08x %08x %08x\n", timing->id, -- timing->reg_0, timing->reg_1,timing->reg_2); + t->reg[1] = (e->tWR + 2 + (t->tCWL - 1)) << 24 | + 1 << 16 | + (e->tWTR + 2 + (t->tCWL - 1)) << 8 | @@ -58747,7 +58654,9 @@ + e->tRRD << 16 | + e->tRCDWR << 8 | + e->tRCDRD); -+ + +- NV_DEBUG(dev, "Entry %d: 220: %08x %08x %08x\n", timing->id, +- timing->reg_0, timing->reg_1,timing->reg_2); + NV_DEBUG(dev, "Entry %d: 220: %08x %08x %08x\n", t->id, + t->reg[0], t->reg[1], t->reg[2]); + return 0; @@ -58801,19 +58710,6 @@ - timing->reg_1 |= (e->tCL + 2 - magic_number); - } - timing->reg_2 = (e->tUNK_12 << 16 | e->tUNK_11 << 8 | e->tUNK_10); -- -- timing->reg_5 = (e->tRAS << 24 | e->tRC); -- timing->reg_5 += max(e->tUNK_10, e->tUNK_11) << 16; -- -- if (P->version == 1) { -- timing->reg_2 |= magic_number << 24; -- timing->reg_3 = (0x14 + e->tCL) << 24 | -- 0x16 << 16 | -- (e->tCL - 1) << 8 | -- (e->tCL - 1); -- timing->reg_4 = (nv_rd32(dev,0x10022c) & 0xffff0000) | e->tUNK_13 << 8 | e->tUNK_13; -- timing->reg_5 |= (e->tCL + 2) << 8; -- timing->reg_7 = 0x4000202 | (e->tCL - 1) << 16; + t->reg[1] = (e->tWR + 2 + (t->tCWL - 1)) << 24 | + max(unk18, (u8) 1) << 16 | + (e->tWTR + 2 + (t->tCWL - 1)) << 8; @@ -58826,9 +58722,20 @@ + t->reg[4] = e->tUNK_13 << 8 | e->tUNK_13; + + t->reg[5] = (e->tRFC << 24 | max(e->tRCDRD, e->tRCDWR) << 16 | e->tRP); -+ + +- timing->reg_5 = (e->tRAS << 24 | e->tRC); +- timing->reg_5 += max(e->tUNK_10, e->tUNK_11) << 16; + t->reg[8] = boot->reg[8] & 0xffffff00; -+ + +- if (P->version == 1) { +- timing->reg_2 |= magic_number << 24; +- timing->reg_3 = (0x14 + e->tCL) << 24 | +- 0x16 << 16 | +- (e->tCL - 1) << 8 | +- (e->tCL - 1); +- timing->reg_4 = (nv_rd32(dev,0x10022c) & 0xffff0000) | e->tUNK_13 << 8 | e->tUNK_13; +- timing->reg_5 |= (e->tCL + 2) << 8; +- timing->reg_7 = 0x4000202 | (e->tCL - 1) << 16; + if (P.version == 1) { + t->reg[1] |= (e->tCL + 2 - (t->tCWL - 1)); + @@ -58965,19 +58872,39 @@ + struct nouveau_pm_tbl_entry *e, u8 len, + struct nouveau_pm_memtiming *boot, + struct nouveau_pm_memtiming *t) -+{ + { +- struct drm_nouveau_private *dev_priv = dev->dev_private; +- struct nouveau_pm_engine *pm = &dev_priv->engine.pm; +- struct nouveau_pm_memtimings *memtimings = &pm->memtimings; +- struct nvbios *bios = &dev_priv->vbios; +- struct bit_entry P; +- struct nouveau_pm_tbl_header *hdr = NULL; +- uint8_t magic_number; +- u8 *entry; +- int i; + t->drive_strength = 0; + if (len < 15) { + t->odt = boot->odt; + } else { + t->odt = e->RAM_FT1 & 0x07; + } -+ + +- if (bios->type == NVBIOS_BIT) { +- if (bit_table(dev, 'P', &P)) +- return; + if (e->tCL >= NV_MEM_CL_DDR2_MAX) { + NV_WARN(dev, "(%u) Invalid tCL: %u", t->id, e->tCL); + return -ERANGE; + } -+ + +- if (P.version == 1) +- hdr = (struct nouveau_pm_tbl_header *) ROMPTR(bios, P.data[4]); +- else +- if (P.version == 2) +- hdr = (struct nouveau_pm_tbl_header *) ROMPTR(bios, P.data[8]); +- else { +- NV_WARN(dev, "unknown mem for BIT P %d\n", P.version); +- } + if (e->tWR >= NV_MEM_WR_DDR2_MAX) { + NV_WARN(dev, "(%u) Invalid tWR: %u", t->id, e->tWR); + return -ERANGE; @@ -59014,25 +58941,42 @@ + t->drive_strength = 0; + if (len < 15) { + t->odt = boot->odt; -+ } else { + } else { +- NV_DEBUG(dev, "BMP version too old for memory\n"); +- return; + t->odt = e->RAM_FT1 & 0x07; -+ } -+ + } + +- if (!hdr) { +- NV_DEBUG(dev, "memory timing table pointer invalid\n"); +- return; + if (e->tCL >= NV_MEM_CL_DDR3_MAX || e->tCL < 4) { + NV_WARN(dev, "(%u) Invalid tCL: %u", t->id, e->tCL); + return -ERANGE; -+ } -+ + } + +- if (hdr->version != 0x10) { +- NV_WARN(dev, "memory timing table 0x%02x unknown\n", hdr->version); +- return; + if (e->tWR >= NV_MEM_WR_DDR3_MAX || e->tWR < 4) { + NV_WARN(dev, "(%u) Invalid tWR: %u", t->id, e->tWR); + return -ERANGE; -+ } -+ + } + +- /* validate record length */ +- if (hdr->entry_len < 15) { +- NV_ERROR(dev, "mem timing table length unknown: %d\n", hdr->entry_len); +- return; + if (e->tCWL < 5) { + NV_WARN(dev, "(%u) Invalid tCWL: %u", t->id, e->tCWL); + return -ERANGE; -+ } -+ + } + +- /* parse vbios entries into common format */ +- memtimings->timing = +- kcalloc(hdr->entry_cnt, sizeof(*memtimings->timing), GFP_KERNEL); +- if (!memtimings->timing) +- return; + t->mr[0] = (boot->mr[0] & 0x180b) | + /* CAS */ + (cl & 0x7) << 4 | @@ -59043,7 +58987,12 @@ + (t->odt & 0x2) << 5 | + (t->odt & 0x4) << 7; + t->mr[2] = (boot->mr[2] & 0x20ffb7) | (e->tCWL - 5) << 3; -+ + +- /* Get "some number" from the timing reg for NV_40 and NV_50 +- * Used in calculations later... source unknown */ +- magic_number = 0; +- if (P.version == 1) { +- magic_number = (nv_rd32(dev, 0x100228) & 0x0f000000) >> 24; + NV_DEBUG(dev, "(%u) MR: %08x %08x", t->id, t->mr[0], t->mr[2]); + return 0; +} @@ -59065,18 +59014,32 @@ + } else { + t->drive_strength = (e->RAM_FT1 & 0x30) >> 4; + t->odt = e->RAM_FT1 & 0x07; -+ } -+ + } + +- entry = (u8*) hdr + hdr->header_len; +- for (i = 0; i < hdr->entry_cnt; i++, entry += hdr->entry_len) { +- struct nouveau_pm_memtiming *timing = &pm->memtimings.timing[i]; +- if (entry[0] == 0) +- continue; + if (e->tCL >= NV_MEM_CL_GDDR3_MAX) { + NV_WARN(dev, "(%u) Invalid tCL: %u", t->id, e->tCL); + return -ERANGE; + } -+ + +- timing->id = i; +- timing->WR = entry[0]; +- timing->CL = entry[2]; + if (e->tWR >= NV_MEM_WR_GDDR3_MAX) { + NV_WARN(dev, "(%u) Invalid tWR: %u", t->id, e->tWR); + return -ERANGE; + } -+ + +- if(dev_priv->card_type <= NV_40) { +- nv40_mem_timing_entry(dev,hdr,(struct nouveau_pm_tbl_entry*) entry,magic_number,&pm->memtimings.timing[i]); +- } else if(dev_priv->card_type == NV_50){ +- nv50_mem_timing_entry(dev,&P,hdr,(struct nouveau_pm_tbl_entry*) entry,magic_number,&pm->memtimings.timing[i]); +- } else if(dev_priv->card_type == NV_C0) { +- nvc0_mem_timing_entry(dev,hdr,(struct nouveau_pm_tbl_entry*) entry,&pm->memtimings.timing[i]); + if (t->odt > 3) { + NV_WARN(dev, "(%u) Invalid odt value, assuming autocal: %x", + t->id, t->odt); @@ -59141,16 +59104,9 @@ +int +nouveau_mem_timing_calc(struct drm_device *dev, u32 freq, + struct nouveau_pm_memtiming *t) - { - struct drm_nouveau_private *dev_priv = dev->dev_private; - struct nouveau_pm_engine *pm = &dev_priv->engine.pm; -- struct nouveau_pm_memtimings *memtimings = &pm->memtimings; -- struct nvbios *bios = &dev_priv->vbios; -- struct bit_entry P; -- struct nouveau_pm_tbl_header *hdr = NULL; -- uint8_t magic_number; -- u8 *entry; -- int i; ++{ ++ struct drm_nouveau_private *dev_priv = dev->dev_private; ++ struct nouveau_pm_engine *pm = &dev_priv->engine.pm; + struct nouveau_pm_memtiming *boot = &pm->boot.timing; + struct nouveau_pm_tbl_entry *e; + u8 ver, len, *ptr, *ramcfg; @@ -59179,10 +59135,7 @@ + ret = -ENODEV; + break; + } - -- if (bios->type == NVBIOS_BIT) { -- if (bit_table(dev, 'P', &P)) -- return; ++ + switch (dev_priv->vram_type * !ret) { + case NV_MEM_TYPE_GDDR3: + ret = nouveau_mem_gddr3_mr(dev, freq, e, len, boot, t); @@ -59200,20 +59153,14 @@ + ret = -EINVAL; + break; + } - -- if (P.version == 1) -- hdr = (struct nouveau_pm_tbl_header *) ROMPTR(bios, P.data[4]); ++ + ramcfg = nouveau_perf_ramcfg(dev, freq, &ver, &len); + if (ramcfg) { + int dll_off; + + if (ver == 0x00) + dll_off = !!(ramcfg[3] & 0x04); - else -- if (P.version == 2) -- hdr = (struct nouveau_pm_tbl_header *) ROMPTR(bios, P.data[8]); -- else { -- NV_WARN(dev, "unknown mem for BIT P %d\n", P.version); ++ else + dll_off = !!(ramcfg[2] & 0x40); + + switch (dev_priv->vram_type) { @@ -59226,30 +59173,30 @@ + t->mr[1] |= 0x00000001 * dll_off; + break; } -+ } -+ + } + +- memtimings->nr_timing = hdr->entry_cnt; +- memtimings->supported = P.version == 1; + return ret; -+} -+ -+void + } + + void +-nouveau_mem_timing_fini(struct drm_device *dev) +nouveau_mem_timing_read(struct drm_device *dev, struct nouveau_pm_memtiming *t) -+{ -+ struct drm_nouveau_private *dev_priv = dev->dev_private; + { + struct drm_nouveau_private *dev_priv = dev->dev_private; +- struct nouveau_pm_memtimings *mem = &dev_priv->engine.pm.memtimings; + u32 timing_base, timing_regs, mr_base; + int i; + + if (dev_priv->card_type >= 0xC0) { + timing_base = 0x10f290; + mr_base = 0x10f300; - } else { -- NV_DEBUG(dev, "BMP version too old for memory\n"); -- return; ++ } else { + timing_base = 0x100220; + mr_base = 0x1002c0; - } - -- if (!hdr) { -- NV_DEBUG(dev, "memory timing table pointer invalid\n"); ++ } ++ + t->id = -1; + + switch (dev_priv->card_type) { @@ -59266,8 +59213,8 @@ + break; + default: + timing_regs = 0; - return; - } ++ return; ++ } + for(i = 0; i < timing_regs; i++) + t->reg[i] = nv_rd32(dev, timing_base + (0x04 * i)); + @@ -59277,10 +59224,7 @@ + } else if (dev_priv->card_type <= NV_D0) { + t->tCWL = ((nv_rd32(dev, 0x10f294) & 0x00000f80) >> 7); + } - -- if (hdr->version != 0x10) { -- NV_WARN(dev, "memory timing table 0x%02x unknown\n", hdr->version); -- return; ++ + t->mr[0] = nv_rd32(dev, mr_base); + t->mr[1] = nv_rd32(dev, mr_base + 0x04); + t->mr[2] = nv_rd32(dev, mr_base + 0x20); @@ -59303,13 +59247,9 @@ + break; + default: + break; - } ++ } +} - -- /* validate record length */ -- if (hdr->entry_len < 15) { -- NV_ERROR(dev, "mem timing table length unknown: %d\n", hdr->entry_len); -- return; ++ +int +nouveau_mem_exec(struct nouveau_mem_exec_func *exec, + struct nouveau_pm_level *perflvl) @@ -59336,13 +59276,8 @@ + default: + NV_ERROR(exec->dev, "cannot reclock unsupported memtype\n"); + return -ENODEV; - } - -- /* parse vbios entries into common format */ -- memtimings->timing = -- kcalloc(hdr->entry_cnt, sizeof(*memtimings->timing), GFP_KERNEL); -- if (!memtimings->timing) -- return; ++ } ++ + /* fetch current MRs */ + switch (dev_priv->vram_type) { + case NV_MEM_TYPE_GDDR3: @@ -59353,24 +59288,14 @@ + mr[0] = exec->mrg(exec, 0); + break; + } - -- /* Get "some number" from the timing reg for NV_40 and NV_50 -- * Used in calculations later... source unknown */ -- magic_number = 0; -- if (P.version == 1) { -- magic_number = (nv_rd32(dev, 0x100228) & 0x0f000000) >> 24; ++ + /* DLL 'on' -> DLL 'off' mode, disable before entering self-refresh */ + if (!(mr[1] & mr1_dlloff) && (info->mr[1] & mr1_dlloff)) { + exec->precharge(exec); + exec->mrs (exec, 1, mr[1] | mr1_dlloff); + exec->wait(exec, tMRD); - } - -- entry = (u8*) hdr + hdr->header_len; -- for (i = 0; i < hdr->entry_cnt; i++, entry += hdr->entry_len) { -- struct nouveau_pm_memtiming *timing = &pm->memtimings.timing[i]; -- if (entry[0] == 0) -- continue; ++ } ++ + /* enter self-refresh mode */ + exec->precharge(exec); + exec->refresh(exec); @@ -59405,25 +59330,16 @@ + exec->mrs (exec, 0, info->mr[0]); + exec->wait(exec, tMRD); + } - -- timing->id = i; -- timing->WR = entry[0]; -- timing->CL = entry[2]; ++ + /* update PFB timing registers */ + exec->timing_set(exec); - -- if(dev_priv->card_type <= NV_40) { -- nv40_mem_timing_entry(dev,hdr,(struct nouveau_pm_tbl_entry*) entry,magic_number,&pm->memtimings.timing[i]); -- } else if(dev_priv->card_type == NV_50){ -- nv50_mem_timing_entry(dev,&P,hdr,(struct nouveau_pm_tbl_entry*) entry,magic_number,&pm->memtimings.timing[i]); -- } else if(dev_priv->card_type == NV_C0) { -- nvc0_mem_timing_entry(dev,hdr,(struct nouveau_pm_tbl_entry*) entry,&pm->memtimings.timing[i]); ++ + /* DLL (enable + ) reset */ + if (!(info->mr[1] & mr1_dlloff)) { + if (mr[1] & mr1_dlloff) { + exec->mrs (exec, 1, info->mr[1]); + exec->wait(exec, tMRD); - } ++ } + exec->mrs (exec, 0, info->mr[0] | 0x00000100); + exec->wait(exec, tMRD); + exec->mrs (exec, 0, info->mr[0] | 0x00000000); @@ -59431,20 +59347,14 @@ + exec->wait(exec, tDLLK); + if (dev_priv->vram_type == NV_MEM_TYPE_GDDR3) + exec->precharge(exec); - } - -- memtimings->nr_timing = hdr->entry_cnt; -- memtimings->supported = P.version == 1; ++ } ++ + return 0; - } - --void --nouveau_mem_timing_fini(struct drm_device *dev) ++} ++ +int +nouveau_mem_vbios_type(struct drm_device *dev) - { -- struct drm_nouveau_private *dev_priv = dev->dev_private; -- struct nouveau_pm_memtimings *mem = &dev_priv->engine.pm.memtimings; ++{ + struct bit_entry M; + u8 ramcfg = (nv_rd32(dev, 0x101000) & 0x0000003c) >> 2; + if (!bit_table(dev, 'M', &M) || M.version != 2 || M.length < 5) { @@ -59469,11 +59379,10 @@ } static int -diff --git a/drivers/gpu/drm/nouveau/nouveau_mxm.c b/drivers/gpu/drm/nouveau/nouveau_mxm.c -new file mode 100644 -index 0000000..07d0d1e ---- /dev/null -+++ b/drivers/gpu/drm/nouveau/nouveau_mxm.c +Index: linux-3.2.46/drivers/gpu/drm/nouveau/nouveau_mxm.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/nouveau/nouveau_mxm.c 2013-07-26 19:26:23.000000000 +0000 @@ -0,0 +1,723 @@ +/* + * Copyright 2011 Red Hat Inc. @@ -60198,11 +60107,11 @@ + kfree(dev_priv->mxms); + dev_priv->mxms = NULL; +} -diff --git a/drivers/gpu/drm/nouveau/nouveau_notifier.c b/drivers/gpu/drm/nouveau/nouveau_notifier.c -index 6abdbe6..2ef883c 100644 ---- a/drivers/gpu/drm/nouveau/nouveau_notifier.c -+++ b/drivers/gpu/drm/nouveau/nouveau_notifier.c -@@ -115,7 +115,7 @@ nouveau_notifier_alloc(struct nouveau_channel *chan, uint32_t handle, +Index: linux-3.2.46/drivers/gpu/drm/nouveau/nouveau_notifier.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/nouveau/nouveau_notifier.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/nouveau/nouveau_notifier.c 2013-07-26 19:26:23.000000000 +0000 +@@ -115,7 +115,7 @@ struct drm_nouveau_private *dev_priv = dev->dev_private; struct nouveau_gpuobj *nobj = NULL; struct drm_mm_node *mem; @@ -60211,34 +60120,33 @@ int target, ret; mem = drm_mm_search_free_in_range(&chan->notifier_heap, size, 0, -diff --git a/drivers/gpu/drm/nouveau/nouveau_object.c b/drivers/gpu/drm/nouveau/nouveau_object.c -index 960c0ae..cc419fae 100644 ---- a/drivers/gpu/drm/nouveau/nouveau_object.c -+++ b/drivers/gpu/drm/nouveau/nouveau_object.c -@@ -723,14 +723,14 @@ nvc0_gpuobj_channel_init(struct nouveau_channel *chan, struct nouveau_vm *vm) +Index: linux-3.2.46/drivers/gpu/drm/nouveau/nouveau_object.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/nouveau/nouveau_object.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/nouveau/nouveau_object.c 2013-07-26 19:26:23.000000000 +0000 +@@ -723,14 +723,14 @@ nv_wo32(chan->ramin, 0x020c, 0x000000ff); /* map display semaphore buffers into channel's vm */ - if (dev_priv->card_type >= NV_D0) - return 0; -- -- for (i = 0; i < 2; i++) { -- struct nv50_display_crtc *dispc = &nv50_display(dev)->crtc[i]; -- -- ret = nouveau_bo_vma_add(dispc->sem.bo, chan->vm, -- &chan->dispc_vma[i]); + for (i = 0; i < dev->mode_config.num_crtc; i++) { + struct nouveau_bo *bo; + if (dev_priv->card_type >= NV_D0) + bo = nvd0_display_crtc_sema(dev, i); + else + bo = nv50_display(dev)->crtc[i].sem.bo; -+ + +- for (i = 0; i < 2; i++) { +- struct nv50_display_crtc *dispc = &nv50_display(dev)->crtc[i]; +- +- ret = nouveau_bo_vma_add(dispc->sem.bo, chan->vm, +- &chan->dispc_vma[i]); + ret = nouveau_bo_vma_add(bo, chan->vm, &chan->dispc_vma[i]); if (ret) return ret; } -@@ -879,9 +879,14 @@ nouveau_gpuobj_channel_takedown(struct nouveau_channel *chan) +@@ -879,9 +879,14 @@ NV_DEBUG(dev, "ch%d\n", chan->id); @@ -60255,10 +60163,10 @@ for (i = 0; i < dev->mode_config.num_crtc; i++) { struct nv50_display_crtc *dispc = &disp->crtc[i]; nouveau_bo_vma_del(dispc->sem.bo, &chan->dispc_vma[i]); -diff --git a/drivers/gpu/drm/nouveau/nouveau_perf.c b/drivers/gpu/drm/nouveau/nouveau_perf.c -index 33d03fb..69a528d 100644 ---- a/drivers/gpu/drm/nouveau/nouveau_perf.c -+++ b/drivers/gpu/drm/nouveau/nouveau_perf.c +Index: linux-3.2.46/drivers/gpu/drm/nouveau/nouveau_perf.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/nouveau/nouveau_perf.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/nouveau/nouveau_perf.c 2013-07-26 19:26:23.000000000 +0000 @@ -27,6 +27,178 @@ #include "nouveau_drv.h" #include "nouveau_pm.h" @@ -60438,7 +60346,7 @@ static void legacy_perf_init(struct drm_device *dev) { -@@ -41,7 +213,7 @@ legacy_perf_init(struct drm_device *dev) +@@ -41,7 +213,7 @@ return; } @@ -60447,7 +60355,7 @@ if (!perf) { NV_DEBUG(dev, "No memclock table pointer found.\n"); return; -@@ -72,75 +244,11 @@ legacy_perf_init(struct drm_device *dev) +@@ -72,75 +244,11 @@ pm->nr_perflvl = 1; } @@ -60525,7 +60433,7 @@ u8 *vmap; int id; -@@ -159,13 +267,13 @@ nouveau_perf_voltage(struct drm_device *dev, struct bit_entry *P, +@@ -159,13 +267,13 @@ /* on newer ones, the perflvl stores an index into yet another * vbios table containing a min/max voltage value for the perflvl */ @@ -60542,7 +60450,7 @@ if (!vmap) { NV_DEBUG(dev, "volt map table pointer invalid\n"); return; -@@ -184,129 +292,70 @@ nouveau_perf_init(struct drm_device *dev) +@@ -184,129 +292,70 @@ struct drm_nouveau_private *dev_priv = dev->dev_private; struct nouveau_pm_engine *pm = &dev_priv->engine.pm; struct nvbios *bios = &dev_priv->vbios; @@ -60709,7 +60617,7 @@ if (dev_priv->card_type == NV_50) { perflvl->core = subent(0); perflvl->shader = subent(1); -@@ -329,36 +378,34 @@ nouveau_perf_init(struct drm_device *dev) +@@ -329,36 +378,34 @@ } /* make sure vid is valid */ @@ -60760,10 +60668,10 @@ } } -diff --git a/drivers/gpu/drm/nouveau/nouveau_pm.c b/drivers/gpu/drm/nouveau/nouveau_pm.c -index a539fd2..da3e7c3 100644 ---- a/drivers/gpu/drm/nouveau/nouveau_pm.c -+++ b/drivers/gpu/drm/nouveau/nouveau_pm.c +Index: linux-3.2.46/drivers/gpu/drm/nouveau/nouveau_pm.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/nouveau/nouveau_pm.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/nouveau/nouveau_pm.c 2013-07-26 19:26:23.000000000 +0000 @@ -26,6 +26,7 @@ #include "nouveau_drv.h" @@ -60829,7 +60737,10 @@ + if (dev_priv->chipset < 0xa3) + divs /= 4; + } -+ + +- pre_state = pm->clock_pre(dev, perflvl, id, khz); +- if (IS_ERR(pre_state)) +- return PTR_ERR(pre_state); + duty = ((divs * percent) + 99) / 100; + if (dev_priv->card_type <= NV_40 || (gpio.log[0] & 1)) + duty = divs - duty; @@ -60850,10 +60761,7 @@ + struct drm_nouveau_private *dev_priv = dev->dev_private; + struct nouveau_pm_engine *pm = &dev_priv->engine.pm; + int ret; - -- pre_state = pm->clock_pre(dev, perflvl, id, khz); -- if (IS_ERR(pre_state)) -- return PTR_ERR(pre_state); ++ + /*XXX: not on all boards, we should control based on temperature + * on recent boards.. or maybe on some other factor we don't + * know about? @@ -60881,7 +60789,7 @@ return 0; } -@@ -59,34 +136,90 @@ nouveau_pm_perflvl_set(struct drm_device *dev, struct nouveau_pm_level *perflvl) +@@ -59,34 +136,90 @@ { struct drm_nouveau_private *dev_priv = dev->dev_private; struct nouveau_pm_engine *pm = &dev_priv->engine.pm; @@ -60990,7 +60898,7 @@ } static int -@@ -94,33 +227,55 @@ nouveau_pm_profile_set(struct drm_device *dev, const char *profile) +@@ -94,33 +227,55 @@ { struct drm_nouveau_private *dev_priv = dev->dev_private; struct nouveau_pm_engine *pm = &dev_priv->engine.pm; @@ -61007,52 +60915,53 @@ - else { - int pl = simple_strtol(profile, NULL, 10); - int i; -+ strncpy(string, profile, sizeof(string)); -+ string[sizeof(string) - 1] = 0; -+ if ((ptr = strchr(string, '\n'))) -+ *ptr = '\0'; - +- - for (i = 0; i < pm->nr_perflvl; i++) { - if (pm->perflvl[i].id == pl) { - perflvl = &pm->perflvl[i]; - break; - } - } ++ strncpy(string, profile, sizeof(string)); ++ string[sizeof(string) - 1] = 0; ++ if ((ptr = strchr(string, '\n'))) ++ *ptr = '\0'; ++ + ptr = strsep(&cur, ","); + if (ptr) + ac = profile_find(dev, ptr); - -- if (!perflvl) -- return -EINVAL; -- } ++ + ptr = strsep(&cur, ","); + if (ptr) + dc = profile_find(dev, ptr); + else + dc = ac; -+ + +- if (!perflvl) +- return -EINVAL; +- } + if (ac == NULL || dc == NULL) + return -EINVAL; - -- NV_INFO(dev, "setting performance level: %s\n", profile); -- return nouveau_pm_perflvl_set(dev, perflvl); ++ + pm->profile_ac = ac; + pm->profile_dc = dc; + nouveau_pm_trigger(dev); + return 0; - } - ++} ++ +static void +nouveau_pm_static_dummy(struct nouveau_pm_profile *profile) +{ +} -+ + +- NV_INFO(dev, "setting performance level: %s\n", profile); +- return nouveau_pm_perflvl_set(dev, perflvl); +static struct nouveau_pm_level * +nouveau_pm_static_select(struct nouveau_pm_profile *profile) +{ + return container_of(profile, struct nouveau_pm_level, profile); -+} -+ + } + +const struct nouveau_pm_profile_func nouveau_pm_static_profile_func = { + .destroy = nouveau_pm_static_dummy, + .init = nouveau_pm_static_dummy, @@ -61063,7 +60972,7 @@ static int nouveau_pm_perflvl_get(struct drm_device *dev, struct nouveau_pm_level *perflvl) { -@@ -134,23 +289,6 @@ nouveau_pm_perflvl_get(struct drm_device *dev, struct nouveau_pm_level *perflvl) +@@ -134,23 +289,6 @@ ret = pm->clocks_get(dev, perflvl); if (ret) return ret; @@ -61087,7 +60996,7 @@ } if (pm->voltage.supported && pm->voltage_get) { -@@ -161,13 +299,18 @@ nouveau_pm_perflvl_get(struct drm_device *dev, struct nouveau_pm_level *perflvl) +@@ -161,13 +299,18 @@ } } @@ -61107,7 +61016,7 @@ c[0] = '\0'; if (perflvl->core) -@@ -195,18 +338,15 @@ nouveau_pm_perflvl_info(struct nouveau_pm_level *perflvl, char *ptr, int len) +@@ -195,18 +338,15 @@ if (perflvl->fanspeed) snprintf(f, sizeof(f), " fanspeed %d%%", perflvl->fanspeed); @@ -61129,7 +61038,7 @@ char *ptr = buf; int len = PAGE_SIZE; -@@ -228,12 +368,8 @@ nouveau_pm_get_perflvl(struct device *d, struct device_attribute *a, char *buf) +@@ -228,12 +368,8 @@ int len = PAGE_SIZE, ret; char *ptr = buf; @@ -61144,7 +61053,7 @@ ptr += strlen(buf); len -= strlen(buf); -@@ -345,7 +481,7 @@ nouveau_hwmon_set_max_temp(struct device *d, struct device_attribute *a, +@@ -345,7 +481,7 @@ struct nouveau_pm_threshold_temp *temp = &pm->threshold_temp; long value; @@ -61153,7 +61062,7 @@ return count; temp->down_clock = value/1000; -@@ -380,7 +516,7 @@ nouveau_hwmon_set_critical_temp(struct device *d, struct device_attribute *a, +@@ -380,7 +516,7 @@ struct nouveau_pm_threshold_temp *temp = &pm->threshold_temp; long value; @@ -61162,7 +61071,7 @@ return count; temp->critical = value/1000; -@@ -412,6 +548,172 @@ static SENSOR_DEVICE_ATTR(update_rate, S_IRUGO, +@@ -412,6 +548,172 @@ nouveau_hwmon_show_update_rate, NULL, 0); @@ -61335,7 +61244,7 @@ static struct attribute *hwmon_attributes[] = { &sensor_dev_attr_temp1_input.dev_attr.attr, &sensor_dev_attr_temp1_max.dev_attr.attr, -@@ -420,20 +722,36 @@ static struct attribute *hwmon_attributes[] = { +@@ -420,20 +722,36 @@ &sensor_dev_attr_update_rate.dev_attr.attr, NULL }; @@ -61374,7 +61283,7 @@ if (!pm->temp_get) return -ENODEV; -@@ -446,17 +764,46 @@ nouveau_hwmon_init(struct drm_device *dev) +@@ -446,17 +764,46 @@ return ret; } dev_set_drvdata(hwmon_dev, dev); @@ -61426,7 +61335,7 @@ } static void -@@ -468,6 +815,11 @@ nouveau_hwmon_fini(struct drm_device *dev) +@@ -468,6 +815,11 @@ if (pm->hwmon) { sysfs_remove_group(&dev->pdev->dev.kobj, &hwmon_attrgroup); @@ -61438,7 +61347,7 @@ hwmon_device_unregister(pm->hwmon); } #endif -@@ -486,6 +838,7 @@ nouveau_pm_acpi_event(struct notifier_block *nb, unsigned long val, void *data) +@@ -486,6 +838,7 @@ bool ac = power_supply_is_system_supplied(); NV_DEBUG(dev, "power supply changed: %s\n", ac ? "AC" : "DC"); @@ -61446,7 +61355,7 @@ } return NOTIFY_OK; -@@ -500,35 +853,48 @@ nouveau_pm_init(struct drm_device *dev) +@@ -500,35 +853,48 @@ char info[256]; int ret, i; @@ -61513,7 +61422,7 @@ nouveau_sysfs_init(dev); nouveau_hwmon_init(dev); -@@ -545,6 +911,12 @@ nouveau_pm_fini(struct drm_device *dev) +@@ -545,6 +911,12 @@ { struct drm_nouveau_private *dev_priv = dev->dev_private; struct nouveau_pm_engine *pm = &dev_priv->engine.pm; @@ -61526,7 +61435,7 @@ if (pm->cur != &pm->boot) nouveau_pm_perflvl_set(dev, &pm->boot); -@@ -552,7 +924,6 @@ nouveau_pm_fini(struct drm_device *dev) +@@ -552,7 +924,6 @@ nouveau_temp_fini(dev); nouveau_perf_fini(dev); nouveau_volt_fini(dev); @@ -61534,16 +61443,16 @@ #if defined(CONFIG_ACPI) && defined(CONFIG_POWER_SUPPLY) unregister_acpi_notifier(&pm->acpi_nb); -@@ -574,4 +945,5 @@ nouveau_pm_resume(struct drm_device *dev) +@@ -574,4 +945,5 @@ perflvl = pm->cur; pm->cur = &pm->boot; nouveau_pm_perflvl_set(dev, perflvl); + nouveau_pwmfan_set(dev, pm->fan.percent); } -diff --git a/drivers/gpu/drm/nouveau/nouveau_pm.h b/drivers/gpu/drm/nouveau/nouveau_pm.h -index 8ac02cd..3f82dfe 100644 ---- a/drivers/gpu/drm/nouveau/nouveau_pm.h -+++ b/drivers/gpu/drm/nouveau/nouveau_pm.h +Index: linux-3.2.46/drivers/gpu/drm/nouveau/nouveau_pm.h +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/nouveau/nouveau_pm.h 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/nouveau/nouveau_pm.h 2013-07-26 19:26:23.000000000 +0000 @@ -25,10 +25,30 @@ #ifndef __NOUVEAU_PM_H__ #define __NOUVEAU_PM_H__ @@ -61575,7 +61484,7 @@ /* nouveau_volt.c */ void nouveau_volt_init(struct drm_device *); -@@ -41,35 +61,41 @@ int nouveau_voltage_gpio_set(struct drm_device *, int voltage); +@@ -41,35 +61,41 @@ /* nouveau_perf.c */ void nouveau_perf_init(struct drm_device *); void nouveau_perf_fini(struct drm_device *); @@ -61627,10 +61536,10 @@ /* nouveau_temp.c */ void nouveau_temp_init(struct drm_device *dev); -diff --git a/drivers/gpu/drm/nouveau/nouveau_sgdma.c b/drivers/gpu/drm/nouveau/nouveau_sgdma.c -index c8a463b..47f245e 100644 ---- a/drivers/gpu/drm/nouveau/nouveau_sgdma.c -+++ b/drivers/gpu/drm/nouveau/nouveau_sgdma.c +Index: linux-3.2.46/drivers/gpu/drm/nouveau/nouveau_sgdma.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/nouveau/nouveau_sgdma.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/nouveau/nouveau_sgdma.c 2013-07-26 19:26:23.000000000 +0000 @@ -8,91 +8,30 @@ #define NV_CTXDMA_PAGE_MASK (NV_CTXDMA_PAGE_SIZE - 1) @@ -61693,8 +61602,7 @@ - - if (nvbe->bound) - be->func->unbind(be); -+ struct nouveau_sgdma_be *nvbe = (struct nouveau_sgdma_be *)ttm; - +- - if (nvbe->unmap_pages) { - while (nvbe->nr_pages--) { - pci_unmap_page(dev->pdev, nvbe->pages[nvbe->nr_pages], @@ -61710,7 +61618,8 @@ -nouveau_sgdma_destroy(struct ttm_backend *be) -{ - struct nouveau_sgdma_be *nvbe = (struct nouveau_sgdma_be *)be; -- ++ struct nouveau_sgdma_be *nvbe = (struct nouveau_sgdma_be *)ttm; + - if (be) { + if (ttm) { NV_DEBUG(nvbe->dev, "\n"); @@ -61734,7 +61643,7 @@ struct drm_device *dev = nvbe->dev; struct drm_nouveau_private *dev_priv = dev->dev_private; struct nouveau_gpuobj *gpuobj = dev_priv->gart_info.sg_ctxdma; -@@ -102,8 +41,8 @@ nv04_sgdma_bind(struct ttm_backend *be, struct ttm_mem_reg *mem) +@@ -102,8 +41,8 @@ nvbe->offset = mem->start << PAGE_SHIFT; pte = (nvbe->offset >> NV_CTXDMA_PAGE_SHIFT) + 2; @@ -61745,7 +61654,7 @@ uint32_t offset_l = lower_32_bits(dma_offset); for (j = 0; j < PAGE_SIZE / NV_CTXDMA_PAGE_SIZE; j++, pte++) { -@@ -112,14 +51,13 @@ nv04_sgdma_bind(struct ttm_backend *be, struct ttm_mem_reg *mem) +@@ -112,14 +51,13 @@ } } @@ -61762,7 +61671,7 @@ struct drm_device *dev = nvbe->dev; struct drm_nouveau_private *dev_priv = dev->dev_private; struct nouveau_gpuobj *gpuobj = dev_priv->gart_info.sg_ctxdma; -@@ -127,22 +65,19 @@ nv04_sgdma_unbind(struct ttm_backend *be) +@@ -127,22 +65,19 @@ NV_DEBUG(dev, "\n"); @@ -61787,7 +61696,7 @@ .bind = nv04_sgdma_bind, .unbind = nv04_sgdma_unbind, .destroy = nouveau_sgdma_destroy -@@ -161,14 +96,14 @@ nv41_sgdma_flush(struct nouveau_sgdma_be *nvbe) +@@ -161,14 +96,14 @@ } static int @@ -61806,7 +61715,7 @@ nvbe->offset = mem->start << PAGE_SHIFT; -@@ -178,18 +113,17 @@ nv41_sgdma_bind(struct ttm_backend *be, struct ttm_mem_reg *mem) +@@ -178,18 +113,17 @@ } nv41_sgdma_flush(nvbe); @@ -61828,7 +61737,7 @@ while (cnt--) { nv_wo32(pgt, pte, 0x00000000); -@@ -197,24 +131,22 @@ nv41_sgdma_unbind(struct ttm_backend *be) +@@ -197,24 +131,22 @@ } nv41_sgdma_flush(nvbe); @@ -61856,7 +61765,7 @@ nv_wr32(dev, 0x100808, nvbe->offset | 0x20); if (!nv_wait(dev, 0x100808, 0x00000001, 0x00000001)) NV_ERROR(dev, "gart flush timeout: 0x%08x\n", -@@ -273,14 +205,14 @@ nv44_sgdma_fill(struct nouveau_gpuobj *pgt, dma_addr_t *list, u32 base, u32 cnt) +@@ -273,14 +205,14 @@ } static int @@ -61875,7 +61784,7 @@ int i; nvbe->offset = mem->start << PAGE_SHIFT; -@@ -308,19 +240,18 @@ nv44_sgdma_bind(struct ttm_backend *be, struct ttm_mem_reg *mem) +@@ -308,19 +240,18 @@ if (cnt) nv44_sgdma_fill(pgt, list, pte, cnt); @@ -61899,7 +61808,7 @@ if (pte & 0x0000000c) { u32 max = 4 - ((pte >> 2) & 0x3); -@@ -342,55 +273,47 @@ nv44_sgdma_unbind(struct ttm_backend *be) +@@ -342,55 +273,47 @@ if (cnt) nv44_sgdma_fill(pgt, NULL, pte, cnt); @@ -61967,7 +61876,7 @@ struct nouveau_sgdma_be *nvbe; nvbe = kzalloc(sizeof(*nvbe), GFP_KERNEL); -@@ -398,9 +321,13 @@ nouveau_sgdma_init_ttm(struct drm_device *dev) +@@ -398,9 +321,13 @@ return NULL; nvbe->dev = dev; @@ -61983,10 +61892,10 @@ } int -diff --git a/drivers/gpu/drm/nouveau/nouveau_state.c b/drivers/gpu/drm/nouveau/nouveau_state.c -index 01adcfb..b096cf2 100644 ---- a/drivers/gpu/drm/nouveau/nouveau_state.c -+++ b/drivers/gpu/drm/nouveau/nouveau_state.c +Index: linux-3.2.46/drivers/gpu/drm/nouveau/nouveau_state.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/nouveau/nouveau_state.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/nouveau/nouveau_state.c 2013-07-26 19:26:23.000000000 +0000 @@ -36,6 +36,7 @@ #include "nouveau_drm.h" #include "nouveau_fbcon.h" @@ -61995,7 +61904,7 @@ #include "nouveau_pm.h" #include "nv50_display.h" -@@ -81,17 +82,13 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev) +@@ -81,17 +82,13 @@ engine->display.early_init = nv04_display_early_init; engine->display.late_takedown = nv04_display_late_takedown; engine->display.create = nv04_display_create; @@ -62019,7 +61928,7 @@ engine->vram.takedown = nouveau_stub_takedown; engine->vram.flags_valid = nouveau_mem_flags_valid; break; -@@ -130,17 +127,19 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev) +@@ -130,17 +127,19 @@ engine->display.early_init = nv04_display_early_init; engine->display.late_takedown = nv04_display_late_takedown; engine->display.create = nv04_display_create; @@ -62049,7 +61958,7 @@ engine->vram.takedown = nouveau_stub_takedown; engine->vram.flags_valid = nouveau_mem_flags_valid; break; -@@ -159,11 +158,11 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev) +@@ -159,11 +158,11 @@ engine->timer.init = nv04_timer_init; engine->timer.read = nv04_timer_read; engine->timer.takedown = nv04_timer_takedown; @@ -62066,7 +61975,7 @@ engine->fifo.channels = 32; engine->fifo.init = nv10_fifo_init; engine->fifo.takedown = nv04_fifo_fini; -@@ -179,17 +178,15 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev) +@@ -179,17 +178,15 @@ engine->display.early_init = nv04_display_early_init; engine->display.late_takedown = nv04_display_late_takedown; engine->display.create = nv04_display_create; @@ -62092,7 +62001,7 @@ engine->vram.takedown = nouveau_stub_takedown; engine->vram.flags_valid = nouveau_mem_flags_valid; break; -@@ -228,19 +225,17 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev) +@@ -228,19 +225,17 @@ engine->display.early_init = nv04_display_early_init; engine->display.late_takedown = nv04_display_late_takedown; engine->display.create = nv04_display_create; @@ -62120,7 +62029,7 @@ engine->vram.takedown = nouveau_stub_takedown; engine->vram.flags_valid = nouveau_mem_flags_valid; break; -@@ -280,20 +275,23 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev) +@@ -280,20 +275,23 @@ engine->display.early_init = nv04_display_early_init; engine->display.late_takedown = nv04_display_late_takedown; engine->display.create = nv04_display_create; @@ -62151,7 +62060,7 @@ engine->vram.takedown = nouveau_stub_takedown; engine->vram.flags_valid = nouveau_mem_flags_valid; break; -@@ -335,14 +333,13 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev) +@@ -335,14 +333,13 @@ engine->display.early_init = nv50_display_early_init; engine->display.late_takedown = nv50_display_late_takedown; engine->display.create = nv50_display_create; @@ -62171,7 +62080,7 @@ engine->gpio.irq_enable = nv50_gpio_irq_enable; switch (dev_priv->chipset) { case 0x84: -@@ -355,9 +352,9 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev) +@@ -355,9 +352,9 @@ case 0xaa: case 0xac: case 0x50: @@ -62184,7 +62093,7 @@ break; default: engine->pm.clocks_get = nva3_pm_clocks_get; -@@ -371,6 +368,8 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev) +@@ -371,6 +368,8 @@ engine->pm.temp_get = nv84_temp_get; else engine->pm.temp_get = nv40_temp_get; @@ -62193,7 +62102,7 @@ engine->vram.init = nv50_vram_init; engine->vram.takedown = nv50_vram_fini; engine->vram.get = nv50_vram_new; -@@ -408,14 +407,13 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev) +@@ -408,14 +407,13 @@ engine->display.early_init = nv50_display_early_init; engine->display.late_takedown = nv50_display_late_takedown; engine->display.create = nv50_display_create; @@ -62213,7 +62122,7 @@ engine->gpio.irq_enable = nv50_gpio_irq_enable; engine->vram.init = nvc0_vram_init; engine->vram.takedown = nv50_vram_fini; -@@ -424,8 +422,12 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev) +@@ -424,8 +422,12 @@ engine->vram.flags_valid = nvc0_vram_flags_valid; engine->pm.temp_get = nv84_temp_get; engine->pm.clocks_get = nvc0_pm_clocks_get; @@ -62226,7 +62135,7 @@ break; case 0xd0: engine->instmem.init = nvc0_instmem_init; -@@ -458,24 +460,67 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev) +@@ -458,24 +460,67 @@ engine->display.early_init = nouveau_stub_init; engine->display.late_takedown = nouveau_stub_takedown; engine->display.create = nvd0_display_create; @@ -62300,7 +62209,7 @@ default: NV_ERROR(dev, "NV%02x unsupported\n", dev_priv->chipset); return 1; -@@ -527,6 +572,7 @@ static void nouveau_switcheroo_set_state(struct pci_dev *pdev, +@@ -527,6 +572,7 @@ printk(KERN_ERR "VGA switcheroo: switched nouveau off\n"); dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; drm_kms_helper_poll_disable(dev); @@ -62308,7 +62217,7 @@ nouveau_pci_suspend(pdev, pmm); dev->switch_power_state = DRM_SWITCH_POWER_OFF; } -@@ -549,6 +595,75 @@ static bool nouveau_switcheroo_can_switch(struct pci_dev *pdev) +@@ -549,6 +595,75 @@ return can_switch; } @@ -62384,7 +62293,7 @@ int nouveau_card_init(struct drm_device *dev) { -@@ -589,47 +704,45 @@ nouveau_card_init(struct drm_device *dev) +@@ -589,47 +704,45 @@ nv_mask(dev, 0x00088080, 0x00000800, 0x00000000); } @@ -62453,7 +62362,7 @@ if (!dev_priv->noaccel) { switch (dev_priv->card_type) { -@@ -650,6 +763,7 @@ nouveau_card_init(struct drm_device *dev) +@@ -650,6 +763,7 @@ nv50_graph_create(dev); break; case NV_C0: @@ -62461,7 +62370,7 @@ nvc0_graph_create(dev); break; default: -@@ -665,6 +779,11 @@ nouveau_card_init(struct drm_device *dev) +@@ -665,6 +779,11 @@ case 0xa0: nv84_crypt_create(dev); break; @@ -62473,7 +62382,7 @@ } switch (dev_priv->card_type) { -@@ -686,15 +805,25 @@ nouveau_card_init(struct drm_device *dev) +@@ -686,15 +805,25 @@ break; } @@ -62504,7 +62413,7 @@ for (e = 0; e < NVOBJ_ENGINE_NR; e++) { if (dev_priv->eng[e]) { -@@ -714,63 +843,41 @@ nouveau_card_init(struct drm_device *dev) +@@ -714,63 +843,41 @@ if (ret) goto out_fifo; @@ -62580,7 +62489,7 @@ out_irq: nouveau_irq_fini(dev); out_fifo: -@@ -785,15 +892,6 @@ out_engine: +@@ -785,15 +892,6 @@ dev_priv->eng[e]->destroy(dev,e ); } } @@ -62596,7 +62505,7 @@ nouveau_mem_gart_fini(dev); out_ttmvram: nouveau_mem_vram_fini(dev); -@@ -801,10 +899,17 @@ out_instmem: +@@ -801,10 +899,17 @@ engine->instmem.takedown(dev); out_gpuobj: nouveau_gpuobj_takedown(dev); @@ -62615,7 +62524,7 @@ nouveau_bios_takedown(dev); out_display_early: engine->display.late_takedown(dev); -@@ -820,19 +925,15 @@ static void nouveau_card_takedown(struct drm_device *dev) +@@ -820,19 +925,15 @@ int e; if (dev->mode_config.num_crtc) { @@ -62640,7 +62549,7 @@ if (!dev_priv->noaccel) { engine->fifo.takedown(dev); -@@ -843,11 +944,6 @@ static void nouveau_card_takedown(struct drm_device *dev) +@@ -843,11 +944,6 @@ } } } @@ -62652,7 +62561,7 @@ if (dev_priv->vga_ram) { nouveau_bo_unpin(dev_priv->vga_ram); -@@ -863,12 +959,17 @@ static void nouveau_card_takedown(struct drm_device *dev) +@@ -863,12 +959,17 @@ engine->instmem.takedown(dev); nouveau_gpuobj_takedown(dev); @@ -62673,7 +62582,7 @@ vga_client_register(dev->pdev, NULL, NULL, NULL); } -@@ -998,8 +1099,8 @@ static int nouveau_remove_conflicting_drivers(struct drm_device *dev) +@@ -998,8 +1099,8 @@ int nouveau_load(struct drm_device *dev, unsigned long flags) { struct drm_nouveau_private *dev_priv; @@ -62684,7 +62593,7 @@ int ret; dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL); -@@ -1010,83 +1111,90 @@ int nouveau_load(struct drm_device *dev, unsigned long flags) +@@ -1010,83 +1111,90 @@ dev->dev_private = dev_priv; dev_priv->dev = dev; @@ -62699,22 +62608,36 @@ - /* resource 1 is linear FB */ - /* resource 2 is RAMIN (mmio regs + 0x1000000) */ - /* resource 6 is bios */ +- +- /* map the mmio regs */ +- mmio_start_offs = pci_resource_start(dev->pdev, 0); +- dev_priv->mmio = ioremap(mmio_start_offs, 0x00800000); +- if (!dev_priv->mmio) { +- NV_ERROR(dev, "Unable to initialize the mmio mapping. " +- "Please report your setup to " DRIVER_EMAIL "\n"); +- ret = -EINVAL; +- goto err_priv; +- } +- NV_DEBUG(dev, "regs mapped ok at 0x%llx\n", +- (unsigned long long)mmio_start_offs); +- + /* first up, map the start of mmio and determine the chipset */ + dev_priv->mmio = ioremap(pci_resource_start(dev->pdev, 0), PAGE_SIZE); + if (dev_priv->mmio) { -+#ifdef __BIG_ENDIAN + #ifdef __BIG_ENDIAN +- /* Put the card in BE mode if it's not */ +- if (nv_rd32(dev, NV03_PMC_BOOT_1) != 0x01000001) +- nv_wr32(dev, NV03_PMC_BOOT_1, 0x01000001); +- +- DRM_MEMORYBARRIER(); + /* put the card into big-endian mode if it's not */ + if (nv_rd32(dev, NV03_PMC_BOOT_1) != 0x01000001) + nv_wr32(dev, NV03_PMC_BOOT_1, 0x01000001); + DRM_MEMORYBARRIER(); -+#endif + #endif -- /* map the mmio regs */ -- mmio_start_offs = pci_resource_start(dev->pdev, 0); -- dev_priv->mmio = ioremap(mmio_start_offs, 0x00800000); -- if (!dev_priv->mmio) { -- NV_ERROR(dev, "Unable to initialize the mmio mapping. " -- "Please report your setup to " DRIVER_EMAIL "\n"); +- /* Time to determine the card architecture */ +- reg0 = nv_rd32(dev, NV03_PMC_BOOT_0); + /* determine chipset and derive architecture from it */ + reg0 = nv_rd32(dev, NV03_PMC_BOOT_0); + if ((reg0 & 0x0f000000) > 0) { @@ -62755,36 +62678,7 @@ + dev_priv->chipset = 0x04; + dev_priv->card_type = NV_04; + } -+ -+ iounmap(dev_priv->mmio); -+ } -+ -+ if (!dev_priv->card_type) { -+ NV_ERROR(dev, "unsupported chipset 0x%08x\n", reg0); - ret = -EINVAL; - goto err_priv; - } -- NV_DEBUG(dev, "regs mapped ok at 0x%llx\n", -- (unsigned long long)mmio_start_offs); --#ifdef __BIG_ENDIAN -- /* Put the card in BE mode if it's not */ -- if (nv_rd32(dev, NV03_PMC_BOOT_1) != 0x01000001) -- nv_wr32(dev, NV03_PMC_BOOT_1, 0x01000001); -+ NV_INFO(dev, "Detected an NV%2x generation card (0x%08x)\n", -+ dev_priv->card_type, reg0); - -- DRM_MEMORYBARRIER(); --#endif -+ /* map the mmio regs, limiting the amount to preserve vmap space */ -+ offset = pci_resource_start(dev->pdev, 0); -+ length = pci_resource_len(dev->pdev, 0); -+ if (dev_priv->card_type < NV_E0) -+ length = min(length, (unsigned long long)0x00800000); - -- /* Time to determine the card architecture */ -- reg0 = nv_rd32(dev, NV03_PMC_BOOT_0); -- - /* We're dealing with >=NV10 */ - if ((reg0 & 0x0f000000) > 0) { - /* Bit 27-20 contain the architecture in hex */ @@ -62797,7 +62691,9 @@ - dev_priv->chipset = 0x04; - } else - dev_priv->chipset = 0xff; -- ++ iounmap(dev_priv->mmio); ++ } + - switch (dev_priv->chipset & 0xf0) { - case 0x00: - case 0x10: @@ -62823,22 +62719,35 @@ - break; - default: - NV_INFO(dev, "Unsupported chipset 0x%08x\n", reg0); -+ dev_priv->mmio = ioremap(offset, length); -+ if (!dev_priv->mmio) { -+ NV_ERROR(dev, "Unable to initialize the mmio mapping. " -+ "Please report your setup to " DRIVER_EMAIL "\n"); ++ if (!dev_priv->card_type) { ++ NV_ERROR(dev, "unsupported chipset 0x%08x\n", reg0); ret = -EINVAL; - goto err_mmio; + goto err_priv; } -- -- NV_INFO(dev, "Detected an NV%2x generation card (0x%08x)\n", + + NV_INFO(dev, "Detected an NV%2x generation card (0x%08x)\n", - dev_priv->card_type, reg0); ++ dev_priv->card_type, reg0); ++ ++ /* map the mmio regs, limiting the amount to preserve vmap space */ ++ offset = pci_resource_start(dev->pdev, 0); ++ length = pci_resource_len(dev->pdev, 0); ++ if (dev_priv->card_type < NV_E0) ++ length = min(length, (unsigned long long)0x00800000); ++ ++ dev_priv->mmio = ioremap(offset, length); ++ if (!dev_priv->mmio) { ++ NV_ERROR(dev, "Unable to initialize the mmio mapping. " ++ "Please report your setup to " DRIVER_EMAIL "\n"); ++ ret = -EINVAL; ++ goto err_priv; ++ } + NV_DEBUG(dev, "regs mapped ok at 0x%llx\n", offset); /* determine frequency of timing crystal */ strap = nv_rd32(dev, 0x101000); -@@ -1112,13 +1220,11 @@ int nouveau_load(struct drm_device *dev, unsigned long flags) +@@ -1112,13 +1220,11 @@ dev_priv->noaccel = !!nouveau_noaccel; if (nouveau_noaccel == -1) { switch (dev_priv->chipset) { @@ -62853,7 +62762,7 @@ default: dev_priv->noaccel = false; break; -@@ -1146,7 +1252,7 @@ int nouveau_load(struct drm_device *dev, unsigned long flags) +@@ -1146,7 +1252,7 @@ } } else { dev_priv->ramin_size = 1 * 1024 * 1024; @@ -62862,7 +62771,7 @@ dev_priv->ramin_size); if (!dev_priv->ramin) { NV_ERROR(dev, "Failed to map BAR0 PRAMIN.\n"); -@@ -1240,7 +1346,7 @@ int nouveau_ioctl_getparam(struct drm_device *dev, void *data, +@@ -1240,7 +1346,7 @@ getparam->value = 1; break; case NOUVEAU_GETPARAM_HAS_PAGEFLIP: @@ -62871,11 +62780,11 @@ break; case NOUVEAU_GETPARAM_GRAPH_UNITS: /* NV40 and NV50 versions are quite different, but register -diff --git a/drivers/gpu/drm/nouveau/nouveau_temp.c b/drivers/gpu/drm/nouveau/nouveau_temp.c -index 5a46446..0f5a301 100644 ---- a/drivers/gpu/drm/nouveau/nouveau_temp.c -+++ b/drivers/gpu/drm/nouveau/nouveau_temp.c -@@ -55,6 +55,10 @@ nouveau_temp_vbios_parse(struct drm_device *dev, u8 *temp) +Index: linux-3.2.46/drivers/gpu/drm/nouveau/nouveau_temp.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/nouveau/nouveau_temp.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/nouveau/nouveau_temp.c 2013-07-26 19:26:23.000000000 +0000 +@@ -55,6 +55,10 @@ temps->down_clock = 100; temps->fan_boost = 90; @@ -62886,7 +62795,7 @@ /* Set the known default values to setup the temperature sensor */ if (dev_priv->card_type >= NV_40) { switch (dev_priv->chipset) { -@@ -156,11 +160,26 @@ nouveau_temp_vbios_parse(struct drm_device *dev, u8 *temp) +@@ -156,11 +160,26 @@ case 0x13: sensor->slope_div = value; break; @@ -62913,7 +62822,7 @@ } static int -@@ -267,8 +286,6 @@ probe_monitoring_device(struct nouveau_i2c_chan *i2c, +@@ -267,8 +286,6 @@ static void nouveau_temp_probe_i2c(struct drm_device *dev) { @@ -62922,7 +62831,7 @@ struct i2c_board_info info[] = { { I2C_BOARD_INFO("w83l785ts", 0x2d) }, { I2C_BOARD_INFO("w83781d", 0x2d) }, -@@ -277,11 +294,9 @@ nouveau_temp_probe_i2c(struct drm_device *dev) +@@ -277,11 +294,9 @@ { I2C_BOARD_INFO("lm99", 0x4c) }, { } }; @@ -62935,7 +62844,7 @@ } void -@@ -297,9 +312,9 @@ nouveau_temp_init(struct drm_device *dev) +@@ -297,9 +312,9 @@ return; if (P.version == 1) @@ -62947,11 +62856,11 @@ else NV_WARN(dev, "unknown temp for BIT P %d\n", P.version); -diff --git a/drivers/gpu/drm/nouveau/nouveau_vm.c b/drivers/gpu/drm/nouveau/nouveau_vm.c -index ef0832b..2bf6c03 100644 ---- a/drivers/gpu/drm/nouveau/nouveau_vm.c -+++ b/drivers/gpu/drm/nouveau/nouveau_vm.c -@@ -78,9 +78,10 @@ nouveau_vm_map(struct nouveau_vma *vma, struct nouveau_mem *node) +Index: linux-3.2.46/drivers/gpu/drm/nouveau/nouveau_vm.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/nouveau/nouveau_vm.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/nouveau/nouveau_vm.c 2013-07-26 19:26:23.000000000 +0000 +@@ -78,9 +78,10 @@ void nouveau_vm_map_sg(struct nouveau_vma *vma, u64 delta, u64 length, @@ -62963,11 +62872,11 @@ int big = vma->node->type != vm->spg_shift; u32 offset = vma->node->offset + (delta >> 12); u32 bits = vma->node->type - 12; -diff --git a/drivers/gpu/drm/nouveau/nouveau_vm.h b/drivers/gpu/drm/nouveau/nouveau_vm.h -index 6ce995f..4fb6e72 100644 ---- a/drivers/gpu/drm/nouveau/nouveau_vm.h -+++ b/drivers/gpu/drm/nouveau/nouveau_vm.h -@@ -89,7 +89,7 @@ void nouveau_vm_map_at(struct nouveau_vma *, u64 offset, struct nouveau_mem *); +Index: linux-3.2.46/drivers/gpu/drm/nouveau/nouveau_vm.h +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/nouveau/nouveau_vm.h 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/nouveau/nouveau_vm.h 2013-07-26 19:26:23.000000000 +0000 +@@ -89,7 +89,7 @@ void nouveau_vm_unmap(struct nouveau_vma *); void nouveau_vm_unmap_at(struct nouveau_vma *, u64 offset, u64 length); void nouveau_vm_map_sg(struct nouveau_vma *, u64 offset, u64 length, @@ -62976,10 +62885,10 @@ /* nv50_vm.c */ void nv50_vm_map_pgt(struct nouveau_gpuobj *pgd, u32 pde, -diff --git a/drivers/gpu/drm/nouveau/nouveau_volt.c b/drivers/gpu/drm/nouveau/nouveau_volt.c -index 86d03e1..b010cb9 100644 ---- a/drivers/gpu/drm/nouveau/nouveau_volt.c -+++ b/drivers/gpu/drm/nouveau/nouveau_volt.c +Index: linux-3.2.46/drivers/gpu/drm/nouveau/nouveau_volt.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/nouveau/nouveau_volt.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/nouveau/nouveau_volt.c 2013-07-26 19:26:23.000000000 +0000 @@ -26,6 +26,7 @@ #include "nouveau_drv.h" @@ -62988,7 +62897,7 @@ static const enum dcb_gpio_tag vidtag[] = { 0x04, 0x05, 0x06, 0x1a, 0x73 }; static int nr_vidtag = sizeof(vidtag) / sizeof(vidtag[0]); -@@ -34,7 +35,6 @@ int +@@ -34,7 +35,6 @@ nouveau_voltage_gpio_get(struct drm_device *dev) { struct drm_nouveau_private *dev_priv = dev->dev_private; @@ -62996,7 +62905,7 @@ struct nouveau_pm_voltage *volt = &dev_priv->engine.pm.voltage; u8 vid = 0; int i; -@@ -43,7 +43,7 @@ nouveau_voltage_gpio_get(struct drm_device *dev) +@@ -43,7 +43,7 @@ if (!(volt->vid_mask & (1 << i))) continue; @@ -63005,7 +62914,7 @@ } return nouveau_volt_lvl_lookup(dev, vid); -@@ -53,7 +53,6 @@ int +@@ -53,7 +53,6 @@ nouveau_voltage_gpio_set(struct drm_device *dev, int voltage) { struct drm_nouveau_private *dev_priv = dev->dev_private; @@ -63013,7 +62922,7 @@ struct nouveau_pm_voltage *volt = &dev_priv->engine.pm.voltage; int vid, i; -@@ -65,7 +64,7 @@ nouveau_voltage_gpio_set(struct drm_device *dev, int voltage) +@@ -65,7 +64,7 @@ if (!(volt->vid_mask & (1 << i))) continue; @@ -63022,7 +62931,7 @@ } return 0; -@@ -117,10 +116,10 @@ nouveau_volt_init(struct drm_device *dev) +@@ -117,10 +116,10 @@ return; if (P.version == 1) @@ -63035,7 +62944,7 @@ else { NV_WARN(dev, "unknown volt for BIT P %d\n", P.version); } -@@ -130,7 +129,7 @@ nouveau_volt_init(struct drm_device *dev) +@@ -130,7 +129,7 @@ return; } @@ -63044,7 +62953,7 @@ } if (!volt) { -@@ -194,7 +193,7 @@ nouveau_volt_init(struct drm_device *dev) +@@ -194,7 +193,7 @@ return; } @@ -63053,11 +62962,11 @@ NV_DEBUG(dev, "vid bit %d has no gpio tag\n", i); return; } -diff --git a/drivers/gpu/drm/nouveau/nv04_crtc.c b/drivers/gpu/drm/nouveau/nv04_crtc.c -index 5e45398..728d075 100644 ---- a/drivers/gpu/drm/nouveau/nv04_crtc.c -+++ b/drivers/gpu/drm/nouveau/nv04_crtc.c -@@ -364,7 +364,7 @@ nv_crtc_mode_set_vga(struct drm_crtc *crtc, struct drm_display_mode *mode) +Index: linux-3.2.46/drivers/gpu/drm/nouveau/nv04_crtc.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/nouveau/nv04_crtc.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/nouveau/nv04_crtc.c 2013-07-26 19:26:23.000000000 +0000 +@@ -364,7 +364,7 @@ regp->CRTC[NV_CIO_CR_VRE_INDEX] = 1 << 5 | XLATE(vertEnd, 0, NV_CIO_CR_VRE_3_0); regp->CRTC[NV_CIO_CR_VDE_INDEX] = vertDisplay; /* framebuffer can be larger than crtc scanout area. */ @@ -63066,7 +62975,7 @@ regp->CRTC[NV_CIO_CR_ULINE_INDEX] = 0x00; regp->CRTC[NV_CIO_CR_VBS_INDEX] = vertBlankStart; regp->CRTC[NV_CIO_CR_VBE_INDEX] = vertBlankEnd; -@@ -377,9 +377,9 @@ nv_crtc_mode_set_vga(struct drm_crtc *crtc, struct drm_display_mode *mode) +@@ -377,9 +377,9 @@ /* framebuffer can be larger than crtc scanout area. */ regp->CRTC[NV_CIO_CRE_RPC0_INDEX] = @@ -63078,7 +62987,7 @@ regp->CRTC[NV_CIO_CRE_RPC1_INDEX] = mode->crtc_hdisplay < 1280 ? MASK(NV_CIO_CRE_RPC1_LARGE) : 0x00; regp->CRTC[NV_CIO_CRE_LSR_INDEX] = XLATE(horizBlankEnd, 6, NV_CIO_CRE_LSR_HBE_6) | -@@ -835,18 +835,18 @@ nv04_crtc_do_mode_set_base(struct drm_crtc *crtc, +@@ -835,18 +835,18 @@ NVWriteRAMDAC(dev, nv_crtc->index, NV_PRAMDAC_GENERAL_CONTROL, regp->ramdac_gen_ctrl); @@ -63101,10 +63010,10 @@ nv_set_crtc_base(dev, nv_crtc->index, regp->fb_start); /* Update the arbitration parameters. */ -diff --git a/drivers/gpu/drm/nouveau/nv04_dac.c b/drivers/gpu/drm/nouveau/nv04_dac.c -index 2d6bfd0..f180dcf 100644 ---- a/drivers/gpu/drm/nouveau/nv04_dac.c -+++ b/drivers/gpu/drm/nouveau/nv04_dac.c +Index: linux-3.2.46/drivers/gpu/drm/nouveau/nv04_dac.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/nouveau/nv04_dac.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/nouveau/nv04_dac.c 2013-07-26 19:26:23.000000000 +0000 @@ -32,6 +32,7 @@ #include "nouveau_connector.h" #include "nouveau_crtc.h" @@ -63113,7 +63022,7 @@ #include "nvreg.h" int nv04_dac_output_offset(struct drm_encoder *encoder) -@@ -220,7 +221,6 @@ uint32_t nv17_dac_sample_load(struct drm_encoder *encoder) +@@ -220,7 +221,6 @@ { struct drm_device *dev = encoder->dev; struct drm_nouveau_private *dev_priv = dev->dev_private; @@ -63121,7 +63030,7 @@ struct dcb_entry *dcb = nouveau_encoder(encoder)->dcb; uint32_t sample, testval, regoffset = nv04_dac_output_offset(encoder); uint32_t saved_powerctrl_2 = 0, saved_powerctrl_4 = 0, saved_routput, -@@ -252,11 +252,11 @@ uint32_t nv17_dac_sample_load(struct drm_encoder *encoder) +@@ -252,11 +252,11 @@ nvWriteMC(dev, NV_PBUS_POWERCTRL_4, saved_powerctrl_4 & 0xffffffcf); } @@ -63137,7 +63046,7 @@ msleep(4); -@@ -306,8 +306,8 @@ uint32_t nv17_dac_sample_load(struct drm_encoder *encoder) +@@ -306,8 +306,8 @@ nvWriteMC(dev, NV_PBUS_POWERCTRL_4, saved_powerctrl_4); nvWriteMC(dev, NV_PBUS_POWERCTRL_2, saved_powerctrl_2); @@ -63148,11 +63057,11 @@ return sample; } -diff --git a/drivers/gpu/drm/nouveau/nv04_dfp.c b/drivers/gpu/drm/nouveau/nv04_dfp.c -index 752440c..71b6235 100644 ---- a/drivers/gpu/drm/nouveau/nv04_dfp.c -+++ b/drivers/gpu/drm/nouveau/nv04_dfp.c -@@ -289,6 +289,7 @@ static void nv04_dfp_mode_set(struct drm_encoder *encoder, +Index: linux-3.2.46/drivers/gpu/drm/nouveau/nv04_dfp.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/nouveau/nv04_dfp.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/nouveau/nv04_dfp.c 2013-07-26 19:26:23.000000000 +0000 +@@ -289,6 +289,7 @@ struct nouveau_connector *nv_connector = nouveau_crtc_connector_get(nv_crtc); struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); struct drm_display_mode *output_mode = &nv_encoder->mode; @@ -63160,7 +63069,7 @@ uint32_t mode_ratio, panel_ratio; NV_DEBUG_KMS(dev, "Output mode on CRTC %d:\n", nv_crtc->index); -@@ -340,10 +341,15 @@ static void nv04_dfp_mode_set(struct drm_encoder *encoder, +@@ -340,10 +341,15 @@ output_mode->clock > 165000) regp->fp_control |= (2 << 24); if (nv_encoder->dcb->type == OUTPUT_LVDS) { @@ -63179,7 +63088,7 @@ if (duallink) regp->fp_control |= (8 << 28); } else -@@ -407,7 +413,9 @@ static void nv04_dfp_mode_set(struct drm_encoder *encoder, +@@ -407,7 +413,9 @@ } /* Output property. */ @@ -63190,7 +63099,7 @@ if (dev_priv->chipset == 0x11) regp->dither = savep->dither | 0x00010000; else { -@@ -496,7 +504,7 @@ static void nv04_dfp_update_backlight(struct drm_encoder *encoder, int mode) +@@ -496,7 +504,7 @@ static inline bool is_powersaving_dpms(int mode) { @@ -63199,11 +63108,11 @@ } static void nv04_lvds_dpms(struct drm_encoder *encoder, int mode) -diff --git a/drivers/gpu/drm/nouveau/nv04_display.c b/drivers/gpu/drm/nouveau/nv04_display.c -index 6bd8518..7047d37 100644 ---- a/drivers/gpu/drm/nouveau/nv04_display.c -+++ b/drivers/gpu/drm/nouveau/nv04_display.c -@@ -243,6 +243,11 @@ nv04_display_init(struct drm_device *dev) +Index: linux-3.2.46/drivers/gpu/drm/nouveau/nv04_display.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/nouveau/nv04_display.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/nouveau/nv04_display.c 2013-07-26 19:26:23.000000000 +0000 +@@ -243,6 +243,11 @@ return 0; } @@ -63215,10 +63124,10 @@ static void nv04_vblank_crtc0_isr(struct drm_device *dev) { -diff --git a/drivers/gpu/drm/nouveau/nv04_fb.c b/drivers/gpu/drm/nouveau/nv04_fb.c -index 638cf60..d5eedd6 100644 ---- a/drivers/gpu/drm/nouveau/nv04_fb.c -+++ b/drivers/gpu/drm/nouveau/nv04_fb.c +Index: linux-3.2.46/drivers/gpu/drm/nouveau/nv04_fb.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/nouveau/nv04_fb.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/nouveau/nv04_fb.c 2013-07-26 19:26:23.000000000 +0000 @@ -4,6 +4,40 @@ #include "nouveau_drm.h" @@ -63260,10 +63169,10 @@ nv04_fb_init(struct drm_device *dev) { /* This is what the DDX did for NV_ARCH_04, but a mmio-trace shows -diff --git a/drivers/gpu/drm/nouveau/nv04_pm.c b/drivers/gpu/drm/nouveau/nv04_pm.c -index 9ae92a8..6e75899 100644 ---- a/drivers/gpu/drm/nouveau/nv04_pm.c -+++ b/drivers/gpu/drm/nouveau/nv04_pm.c +Index: linux-3.2.46/drivers/gpu/drm/nouveau/nv04_pm.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/nouveau/nv04_pm.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/nouveau/nv04_pm.c 2013-07-26 19:26:23.000000000 +0000 @@ -27,68 +27,111 @@ #include "nouveau_hw.h" #include "nouveau_pm.h" @@ -63336,14 +63245,15 @@ - kfree(state); - return (ret == -ENOENT) ? NULL : ERR_PTR(ret); - } -+ ret = calc_pll(dev, PLL_CORE, perflvl->core, &info->core); -+ if (ret) -+ goto error; - +- - ret = nouveau_calc_pll_mnp(dev, &state->pll, khz, &state->calc); - if (!ret) { - kfree(state); - return ERR_PTR(-EINVAL); ++ ret = calc_pll(dev, PLL_CORE, perflvl->core, &info->core); ++ if (ret) ++ goto error; ++ + if (perflvl->memory) { + ret = calc_pll(dev, PLL_MEMORY, perflvl->memory, &info->memory); + if (ret) @@ -63375,7 +63285,10 @@ - nouveau_hw_setpll(dev, reg, &state->calc); + nouveau_hw_setpll(dev, reg, &clk->calc); +} -+ + +- if (dev_priv->card_type < NV_30 && reg == NV_PRAMDAC_MPLL_COEFF) { +- if (dev_priv->card_type == NV_20) +- nv_mask(dev, 0x1002c4, 0, 1 << 20); +int +nv04_pm_clocks_set(struct drm_device *dev, void *pre_state) +{ @@ -63385,17 +63298,14 @@ + + prog_pll(dev, &state->core); -- if (dev_priv->card_type < NV_30 && reg == NV_PRAMDAC_MPLL_COEFF) { -- if (dev_priv->card_type == NV_20) -- nv_mask(dev, 0x1002c4, 0, 1 << 20); +- /* Reset the DLLs */ +- nv_mask(dev, 0x1002c0, 0, 1 << 8); + if (state->memory.pll.reg) { + prog_pll(dev, &state->memory); + if (dev_priv->card_type < NV_30) { + if (dev_priv->card_type == NV_20) + nv_mask(dev, 0x1002c4, 0, 1 << 20); - -- /* Reset the DLLs */ -- nv_mask(dev, 0x1002c0, 0, 1 << 8); ++ + /* Reset the DLLs */ + nv_mask(dev, 0x1002c0, 0, 1 << 8); + } @@ -63409,10 +63319,10 @@ + return 0; } - -diff --git a/drivers/gpu/drm/nouveau/nv04_timer.c b/drivers/gpu/drm/nouveau/nv04_timer.c -index 263301b..55c9452 100644 ---- a/drivers/gpu/drm/nouveau/nv04_timer.c -+++ b/drivers/gpu/drm/nouveau/nv04_timer.c +Index: linux-3.2.46/drivers/gpu/drm/nouveau/nv04_timer.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/nouveau/nv04_timer.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/nouveau/nv04_timer.c 2013-07-26 19:26:23.000000000 +0000 @@ -2,6 +2,7 @@ #include "drm.h" #include "nouveau_drv.h" @@ -63421,7 +63331,7 @@ int nv04_timer_init(struct drm_device *dev) -@@ -17,7 +18,7 @@ nv04_timer_init(struct drm_device *dev) +@@ -17,7 +18,7 @@ /* determine base clock for timer source */ if (dev_priv->chipset < 0x40) { @@ -63430,10 +63340,10 @@ } else if (dev_priv->chipset == 0x40) { /*XXX: figure this out */ -diff --git a/drivers/gpu/drm/nouveau/nv10_fb.c b/drivers/gpu/drm/nouveau/nv10_fb.c -index f78181a..420b1608 100644 ---- a/drivers/gpu/drm/nouveau/nv10_fb.c -+++ b/drivers/gpu/drm/nouveau/nv10_fb.c +Index: linux-3.2.46/drivers/gpu/drm/nouveau/nv10_fb.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/nouveau/nv10_fb.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/nouveau/nv10_fb.c 2013-07-26 19:26:23.000000000 +0000 @@ -3,81 +3,16 @@ #include "nouveau_drv.h" #include "nouveau_drm.h" @@ -63517,7 +63427,7 @@ } void -@@ -86,11 +21,6 @@ nv10_fb_free_tile_region(struct drm_device *dev, int i) +@@ -86,11 +21,6 @@ struct drm_nouveau_private *dev_priv = dev->dev_private; struct nouveau_tile_reg *tile = &dev_priv->tile.reg[i]; @@ -63529,7 +63439,7 @@ tile->addr = tile->limit = tile->pitch = tile->zcomp = 0; } -@@ -103,9 +33,48 @@ nv10_fb_set_tile_region(struct drm_device *dev, int i) +@@ -103,9 +33,48 @@ nv_wr32(dev, NV10_PFB_TLIMIT(i), tile->limit); nv_wr32(dev, NV10_PFB_TSIZE(i), tile->pitch); nv_wr32(dev, NV10_PFB_TILE(i), tile->addr); @@ -63580,7 +63490,7 @@ } int -@@ -115,14 +84,8 @@ nv10_fb_init(struct drm_device *dev) +@@ -115,14 +84,8 @@ struct nouveau_fb_engine *pfb = &dev_priv->engine.fb; int i; @@ -63596,7 +63506,7 @@ for (i = 0; i < pfb->num_tiles; i++) pfb->set_tile_region(dev, i); -@@ -138,7 +101,4 @@ nv10_fb_takedown(struct drm_device *dev) +@@ -138,7 +101,4 @@ for (i = 0; i < pfb->num_tiles; i++) pfb->free_tile_region(dev, i); @@ -63604,10 +63514,10 @@ - if (dev_priv->card_type == NV_20) - drm_mm_takedown(&pfb->tag_heap); } -diff --git a/drivers/gpu/drm/nouveau/nv10_gpio.c b/drivers/gpu/drm/nouveau/nv10_gpio.c -index 007fc29..9d79180 100644 ---- a/drivers/gpu/drm/nouveau/nv10_gpio.c -+++ b/drivers/gpu/drm/nouveau/nv10_gpio.c +Index: linux-3.2.46/drivers/gpu/drm/nouveau/nv10_gpio.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/nouveau/nv10_gpio.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/nouveau/nv10_gpio.c 2013-07-26 19:26:23.000000000 +0000 @@ -27,66 +27,97 @@ #include "drmP.h" #include "nouveau_drv.h" @@ -63617,9 +63527,7 @@ -static bool -get_gpio_location(struct dcb_gpio_entry *ent, uint32_t *reg, uint32_t *shift, - uint32_t *mask) -+int -+nv10_gpio_sense(struct drm_device *dev, int line) - { +-{ - if (ent->line < 2) { - *reg = NV_PCRTC_GPIO; - *shift = ent->line * 16; @@ -63629,6 +63537,17 @@ - *reg = NV_PCRTC_GPIO_EXT; - *shift = (ent->line - 2) * 4; - *mask = 0x3; +- +- } else if (ent->line < 14) { +- *reg = NV_PCRTC_850; +- *shift = (ent->line - 10) * 4; +- *mask = 0x3; +- +- } else { +- return false; ++int ++nv10_gpio_sense(struct drm_device *dev, int line) ++{ + if (line < 2) { + line = line * 16; + line = NVReadCRTC(dev, 0, NV_PCRTC_GPIO) >> line; @@ -63643,20 +63562,27 @@ + line = (line - 10) * 4; + line = NVReadCRTC(dev, 0, NV_PCRTC_850) >> line; + return !!(line & 0x04); -+ } + } -- } else if (ent->line < 14) { -- *reg = NV_PCRTC_850; -- *shift = (ent->line - 10) * 4; -- *mask = 0x3; +- return true; + return -EINVAL; -+} + } -+int + int +-nv10_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag) +nv10_gpio_drive(struct drm_device *dev, int line, int dir, int out) -+{ + { +- struct dcb_gpio_entry *ent = nouveau_bios_gpio_entry(dev, tag); +- uint32_t reg, shift, mask, value; +- +- if (!ent) +- return -ENODEV; + u32 reg, mask, data; -+ + +- if (!get_gpio_location(ent, ®, &shift, &mask)) +- return -ENODEV; +- +- value = NVReadCRTC(dev, 0, reg) >> shift; + if (line < 2) { + line = line * 16; + reg = NV_PCRTC_GPIO; @@ -63674,19 +63600,18 @@ + reg = NV_PCRTC_850; + mask = 0x00000003; + data = (dir << 1) | out; - } else { -- return false; ++ } else { + return -EINVAL; - } ++ } -- return true; +- return (ent->invert ? 1 : 0) ^ (value & 1); + mask = NVReadCRTC(dev, 0, reg) & ~(mask << line); + NVWriteCRTC(dev, 0, reg, mask | (data << line)); + return 0; } -int --nv10_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag) +-nv10_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state) +void +nv10_gpio_irq_enable(struct drm_device *dev, int line, bool on) { @@ -63709,31 +63634,17 @@ + u32 hi = (intr & 0x0000ffff) >> 0; + u32 lo = (intr & 0xffff0000) >> 16; -- value = NVReadCRTC(dev, 0, reg) >> shift; +- value = ((ent->invert ? 1 : 0) ^ (state ? 1 : 0)) << shift; +- mask = ~(mask << shift); + nouveau_gpio_isr(dev, 0, hi | lo); -- return (ent->invert ? 1 : 0) ^ (value & 1); +- NVWriteCRTC(dev, 0, reg, value | (NVReadCRTC(dev, 0, reg) & mask)); + nv_wr32(dev, 0x001104, intr); - } ++} - int --nv10_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state) ++int +nv10_gpio_init(struct drm_device *dev) - { -- struct dcb_gpio_entry *ent = nouveau_bios_gpio_entry(dev, tag); -- uint32_t reg, shift, mask, value; -- -- if (!ent) -- return -ENODEV; -- -- if (!get_gpio_location(ent, ®, &shift, &mask)) -- return -ENODEV; -- -- value = ((ent->invert ? 1 : 0) ^ (state ? 1 : 0)) << shift; -- mask = ~(mask << shift); -- -- NVWriteCRTC(dev, 0, reg, value | (NVReadCRTC(dev, 0, reg) & mask)); -- ++{ + nv_wr32(dev, 0x001140, 0x00000000); + nv_wr32(dev, 0x001100, 0xffffffff); + nv_wr32(dev, 0x001144, 0x00000000); @@ -63749,10 +63660,10 @@ + nv_wr32(dev, 0x001144, 0x00000000); + nouveau_irq_unregister(dev, 28); +} -diff --git a/drivers/gpu/drm/nouveau/nv17_tv.c b/drivers/gpu/drm/nouveau/nv17_tv.c -index 3900ceb..696d7e7 100644 ---- a/drivers/gpu/drm/nouveau/nv17_tv.c -+++ b/drivers/gpu/drm/nouveau/nv17_tv.c +Index: linux-3.2.46/drivers/gpu/drm/nouveau/nv17_tv.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/nouveau/nv17_tv.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/nouveau/nv17_tv.c 2013-07-26 19:26:23.000000000 +0000 @@ -30,6 +30,7 @@ #include "nouveau_encoder.h" #include "nouveau_connector.h" @@ -63761,7 +63672,7 @@ #include "nouveau_hw.h" #include "nv17_tv.h" -@@ -37,7 +38,6 @@ static uint32_t nv42_tv_sample_load(struct drm_encoder *encoder) +@@ -37,7 +38,6 @@ { struct drm_device *dev = encoder->dev; struct drm_nouveau_private *dev_priv = dev->dev_private; @@ -63769,7 +63680,7 @@ uint32_t testval, regoffset = nv04_dac_output_offset(encoder); uint32_t gpio0, gpio1, fp_htotal, fp_hsync_start, fp_hsync_end, fp_control, test_ctrl, dacclk, ctv_14, ctv_1c, ctv_6c; -@@ -53,8 +53,8 @@ static uint32_t nv42_tv_sample_load(struct drm_encoder *encoder) +@@ -53,8 +53,8 @@ head = (dacclk & 0x100) >> 8; /* Save the previous state. */ @@ -63780,7 +63691,7 @@ fp_htotal = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_HTOTAL); fp_hsync_start = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_START); fp_hsync_end = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_END); -@@ -65,8 +65,8 @@ static uint32_t nv42_tv_sample_load(struct drm_encoder *encoder) +@@ -65,8 +65,8 @@ ctv_6c = NVReadRAMDAC(dev, head, 0x680c6c); /* Prepare the DAC for load detection. */ @@ -63791,7 +63702,7 @@ NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HTOTAL, 1343); NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_START, 1047); -@@ -111,8 +111,8 @@ static uint32_t nv42_tv_sample_load(struct drm_encoder *encoder) +@@ -111,8 +111,8 @@ NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_END, fp_hsync_end); NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HSYNC_START, fp_hsync_start); NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_HTOTAL, fp_htotal); @@ -63802,7 +63713,7 @@ return sample; } -@@ -357,8 +357,6 @@ static bool nv17_tv_mode_fixup(struct drm_encoder *encoder, +@@ -357,8 +357,6 @@ static void nv17_tv_dpms(struct drm_encoder *encoder, int mode) { struct drm_device *dev = encoder->dev; @@ -63811,7 +63722,7 @@ struct nv17_tv_state *regs = &to_tv_enc(encoder)->state; struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder); -@@ -383,8 +381,8 @@ static void nv17_tv_dpms(struct drm_encoder *encoder, int mode) +@@ -383,8 +381,8 @@ nv_load_ptv(dev, regs, 200); @@ -63822,11 +63733,10 @@ nv04_dac_update_dacclk(encoder, mode == DRM_MODE_DPMS_ON); } -diff --git a/drivers/gpu/drm/nouveau/nv20_fb.c b/drivers/gpu/drm/nouveau/nv20_fb.c -new file mode 100644 -index 0000000..19bd640 ---- /dev/null -+++ b/drivers/gpu/drm/nouveau/nv20_fb.c +Index: linux-3.2.46/drivers/gpu/drm/nouveau/nv20_fb.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/nouveau/nv20_fb.c 2013-07-26 19:26:23.000000000 +0000 @@ -0,0 +1,148 @@ +#include "drmP.h" +#include "drm.h" @@ -63976,11 +63886,11 @@ + + drm_mm_takedown(&pfb->tag_heap); +} -diff --git a/drivers/gpu/drm/nouveau/nv40_fb.c b/drivers/gpu/drm/nouveau/nv40_fb.c -index f0ac2a7..7fbcb33 100644 ---- a/drivers/gpu/drm/nouveau/nv40_fb.c -+++ b/drivers/gpu/drm/nouveau/nv40_fb.c -@@ -72,6 +72,51 @@ nv44_fb_init_gart(struct drm_device *dev) +Index: linux-3.2.46/drivers/gpu/drm/nouveau/nv40_fb.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/nouveau/nv40_fb.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/nouveau/nv40_fb.c 2013-07-26 19:26:23.000000000 +0000 +@@ -72,6 +72,51 @@ } int @@ -64032,11 +63942,11 @@ nv40_fb_init(struct drm_device *dev) { struct drm_nouveau_private *dev_priv = dev->dev_private; -diff --git a/drivers/gpu/drm/nouveau/nv40_pm.c b/drivers/gpu/drm/nouveau/nv40_pm.c -index e676b0d..c761538 100644 ---- a/drivers/gpu/drm/nouveau/nv40_pm.c -+++ b/drivers/gpu/drm/nouveau/nv40_pm.c -@@ -222,7 +222,7 @@ nv40_pm_gr_idle(void *data) +Index: linux-3.2.46/drivers/gpu/drm/nouveau/nv40_pm.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/nouveau/nv40_pm.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/nouveau/nv40_pm.c 2013-07-26 19:26:23.000000000 +0000 +@@ -222,7 +222,7 @@ return true; } @@ -64045,7 +63955,7 @@ nv40_pm_clocks_set(struct drm_device *dev, void *pre_state) { struct drm_nouveau_private *dev_priv = dev->dev_private; -@@ -231,7 +231,7 @@ nv40_pm_clocks_set(struct drm_device *dev, void *pre_state) +@@ -231,7 +231,7 @@ struct bit_entry M; u32 crtc_mask = 0; u8 sr1[2]; @@ -64054,7 +63964,7 @@ /* determine which CRTCs are active, fetch VGA_SR1 for each */ for (i = 0; i < 2; i++) { -@@ -263,6 +263,8 @@ nv40_pm_clocks_set(struct drm_device *dev, void *pre_state) +@@ -263,6 +263,8 @@ if (!nv_wait_cb(dev, nv40_pm_gr_idle, dev)) goto resume; @@ -64063,7 +63973,7 @@ /* set engine clocks */ nv_mask(dev, 0x00c040, 0x00000333, 0x00000000); nv_wr32(dev, 0x004004, info->npll_coef); -@@ -345,4 +347,48 @@ resume: +@@ -345,4 +347,48 @@ spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags); kfree(info); @@ -64112,11 +64022,11 @@ + + return 0; } -diff --git a/drivers/gpu/drm/nouveau/nv50_crtc.c b/drivers/gpu/drm/nouveau/nv50_crtc.c -index 882080e..701b927 100644 ---- a/drivers/gpu/drm/nouveau/nv50_crtc.c -+++ b/drivers/gpu/drm/nouveau/nv50_crtc.c -@@ -132,30 +132,74 @@ nv50_crtc_blank(struct nouveau_crtc *nv_crtc, bool blanked) +Index: linux-3.2.46/drivers/gpu/drm/nouveau/nv50_crtc.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/nouveau/nv50_crtc.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/nouveau/nv50_crtc.c 2013-07-26 19:26:23.000000000 +0000 +@@ -132,30 +132,74 @@ } static int @@ -64201,7 +64111,7 @@ } return 0; -@@ -180,80 +224,103 @@ nouveau_crtc_connector_get(struct nouveau_crtc *nv_crtc) +@@ -180,80 +224,103 @@ } static int @@ -64354,7 +64264,7 @@ } return 0; -@@ -333,7 +400,6 @@ nv50_crtc_destroy(struct drm_crtc *crtc) +@@ -333,7 +400,6 @@ nouveau_bo_ref(NULL, &nv_crtc->lut.nvbo); nouveau_bo_unmap(nv_crtc->cursor.nvbo); nouveau_bo_ref(NULL, &nv_crtc->cursor.nvbo); @@ -64362,7 +64272,7 @@ kfree(nv_crtc); } -@@ -441,39 +507,6 @@ nv50_crtc_dpms(struct drm_crtc *crtc, int mode) +@@ -441,39 +507,6 @@ { } @@ -64402,7 +64312,7 @@ static void nv50_crtc_prepare(struct drm_crtc *crtc) { -@@ -497,7 +530,7 @@ nv50_crtc_commit(struct drm_crtc *crtc) +@@ -497,7 +530,7 @@ nv50_crtc_blank(nv_crtc, false); drm_vblank_post_modeset(dev, nv_crtc->index); @@ -64411,7 +64321,7 @@ nv50_display_flip_next(crtc, crtc->fb, NULL); } -@@ -579,8 +612,6 @@ nv50_crtc_do_mode_set_base(struct drm_crtc *crtc, +@@ -579,8 +612,6 @@ OUT_RING (evo, fb->base.depth == 8 ? NV50_EVO_CRTC_CLUT_MODE_OFF : NV50_EVO_CRTC_CLUT_MODE_ON); @@ -64420,7 +64330,7 @@ BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, FB_POS), 1); OUT_RING (evo, (y << 16) | x); -@@ -593,90 +624,77 @@ nv50_crtc_do_mode_set_base(struct drm_crtc *crtc, +@@ -593,90 +624,77 @@ } static int @@ -64450,18 +64360,7 @@ - *nv_crtc->mode = *adjusted_mode; - - NV_DEBUG_KMS(dev, "index %d\n", nv_crtc->index); -+ /* hw timing description looks like this: -+ * -+ * <---------display---------> -+ * ______ -+ * |____________|---------------------------|____________| -+ * -+ * ^ synce ^ blanke ^ blanks ^ active -+ * -+ * interlaced modes also have 2 additional values pointing at the end -+ * and start of the next field's blanking period. -+ */ - +- - hsync_dur = adjusted_mode->hsync_end - adjusted_mode->hsync_start; - vsync_dur = adjusted_mode->vsync_end - adjusted_mode->vsync_start; - hsync_start_to_end = adjusted_mode->htotal - adjusted_mode->hsync_start; @@ -64490,25 +64389,8 @@ - vunk2a -= 1; - vunk2b -= 1; - } -+ hactive = mode->htotal; -+ hsynce = mode->hsync_end - mode->hsync_start - 1; -+ hbackp = mode->htotal - mode->hsync_end; -+ hblanke = hsynce + hbackp; -+ hfrontp = mode->hsync_start - mode->hdisplay; -+ hblanks = mode->htotal - hfrontp - 1; -+ -+ vactive = mode->vtotal * vscan / ilace; -+ vsynce = ((mode->vsync_end - mode->vsync_start) * vscan / ilace) - 1; -+ vbackp = (mode->vtotal - mode->vsync_end) * vscan / ilace; -+ vblanke = vsynce + vbackp; -+ vfrontp = (mode->vsync_start - mode->vdisplay) * vscan / ilace; -+ vblanks = vactive - vfrontp - 1; -+ if (mode->flags & DRM_MODE_FLAG_INTERLACE) { -+ vblan2e = vactive + vsynce + vbackp; -+ vblan2s = vblan2e + (mode->vdisplay * vscan / ilace); -+ vactive = (vactive * 2) + 1; - } - +- } +- - ret = RING_SPACE(evo, 17); - if (ret) - return ret; @@ -64531,6 +64413,49 @@ - } else { - OUT_RING(evo, 0); - OUT_RING(evo, 0); +- } +- +- BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, UNK082C), 1); +- OUT_RING(evo, 0); +- +- /* This is the actual resolution of the mode. */ +- BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, REAL_RES), 1); +- OUT_RING(evo, (mode->vdisplay << 16) | mode->hdisplay); +- BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, SCALE_CENTER_OFFSET), 1); +- OUT_RING(evo, NV50_EVO_CRTC_SCALE_CENTER_OFFSET_VAL(0, 0)); ++ /* hw timing description looks like this: ++ * ++ * <---------display---------> ++ * ______ ++ * |____________|---------------------------|____________| ++ * ++ * ^ synce ^ blanke ^ blanks ^ active ++ * ++ * interlaced modes also have 2 additional values pointing at the end ++ * and start of the next field's blanking period. ++ */ + +- nv_crtc->set_dither(nv_crtc, nv_connector->use_dithering, false); +- nv_crtc->set_scale(nv_crtc, nv_connector->scaling_mode, false); ++ hactive = mode->htotal; ++ hsynce = mode->hsync_end - mode->hsync_start - 1; ++ hbackp = mode->htotal - mode->hsync_end; ++ hblanke = hsynce + hbackp; ++ hfrontp = mode->hsync_start - mode->hdisplay; ++ hblanks = mode->htotal - hfrontp - 1; ++ ++ vactive = mode->vtotal * vscan / ilace; ++ vsynce = ((mode->vsync_end - mode->vsync_start) * vscan / ilace) - 1; ++ vbackp = (mode->vtotal - mode->vsync_end) * vscan / ilace; ++ vblanke = vsynce + vbackp; ++ vfrontp = (mode->vsync_start - mode->vdisplay) * vscan / ilace; ++ vblanks = vactive - vfrontp - 1; ++ if (mode->flags & DRM_MODE_FLAG_INTERLACE) { ++ vblan2e = vactive + vsynce + vbackp; ++ vblan2s = vblan2e + (mode->vdisplay * vscan / ilace); ++ vactive = (vactive * 2) + 1; ++ } ++ + ret = RING_SPACE(evo, 18); + if (ret == 0) { + BEGIN_RING(evo, 0, 0x0804 + head, 2); @@ -64551,26 +64476,15 @@ + OUT_RING (evo, (umode->vdisplay << 16) | umode->hdisplay); + BEGIN_RING(evo, 0, 0x08d4 + head, 1); + OUT_RING (evo, 0x00000000); /* screen position */ - } - -- BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, UNK082C), 1); -- OUT_RING(evo, 0); -- -- /* This is the actual resolution of the mode. */ -- BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, REAL_RES), 1); -- OUT_RING(evo, (mode->vdisplay << 16) | mode->hdisplay); -- BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, SCALE_CENTER_OFFSET), 1); -- OUT_RING(evo, NV50_EVO_CRTC_SCALE_CENTER_OFFSET_VAL(0, 0)); -- -- nv_crtc->set_dither(nv_crtc, nv_connector->use_dithering, false); -- nv_crtc->set_scale(nv_crtc, nv_connector->scaling_mode, false); ++ } ++ + nv_crtc->set_dither(nv_crtc, false); + nv_crtc->set_scale(nv_crtc, false); + nv_crtc->set_color_vibrance(nv_crtc, false); return nv50_crtc_do_mode_set_base(crtc, old_fb, x, y, false); } -@@ -692,7 +710,7 @@ nv50_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y, +@@ -692,7 +710,7 @@ if (ret) return ret; @@ -64579,7 +64493,7 @@ if (ret) return ret; -@@ -711,7 +729,7 @@ nv50_crtc_mode_set_base_atomic(struct drm_crtc *crtc, +@@ -711,7 +729,7 @@ if (ret) return ret; @@ -64588,7 +64502,7 @@ } static const struct drm_crtc_helper_funcs nv50_crtc_helper_funcs = { -@@ -737,11 +755,8 @@ nv50_crtc_create(struct drm_device *dev, int index) +@@ -737,11 +755,8 @@ if (!nv_crtc) return -ENOMEM; @@ -64602,7 +64516,7 @@ /* Default CLUT parameters, will be activated on the hw upon * first mode set. -@@ -764,7 +779,6 @@ nv50_crtc_create(struct drm_device *dev, int index) +@@ -764,7 +779,6 @@ } if (ret) { @@ -64610,7 +64524,7 @@ kfree(nv_crtc); return ret; } -@@ -774,6 +788,7 @@ nv50_crtc_create(struct drm_device *dev, int index) +@@ -774,6 +788,7 @@ /* set function pointers */ nv_crtc->set_dither = nv50_crtc_set_dither; nv_crtc->set_scale = nv50_crtc_set_scale; @@ -64618,11 +64532,11 @@ drm_crtc_init(dev, &nv_crtc->base, &nv50_crtc_funcs); drm_crtc_helper_add(&nv_crtc->base, &nv50_crtc_helper_funcs); -diff --git a/drivers/gpu/drm/nouveau/nv50_dac.c b/drivers/gpu/drm/nouveau/nv50_dac.c -index 808f3ec..55c5633 100644 ---- a/drivers/gpu/drm/nouveau/nv50_dac.c -+++ b/drivers/gpu/drm/nouveau/nv50_dac.c -@@ -190,21 +190,13 @@ nv50_dac_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode, +Index: linux-3.2.46/drivers/gpu/drm/nouveau/nv50_dac.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/nouveau/nv50_dac.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/nouveau/nv50_dac.c 2013-07-26 19:26:23.000000000 +0000 +@@ -190,21 +190,13 @@ } if (connector->scaling_mode != DRM_MODE_SCALE_NONE && @@ -64646,7 +64560,7 @@ nv50_dac_commit(struct drm_encoder *encoder) { } -@@ -266,7 +258,7 @@ static const struct drm_encoder_helper_funcs nv50_dac_helper_funcs = { +@@ -266,7 +258,7 @@ .save = nv50_dac_save, .restore = nv50_dac_restore, .mode_fixup = nv50_dac_mode_fixup, @@ -64655,11 +64569,11 @@ .commit = nv50_dac_commit, .mode_set = nv50_dac_mode_set, .get_crtc = nv50_dac_crtc_get, -diff --git a/drivers/gpu/drm/nouveau/nv50_display.c b/drivers/gpu/drm/nouveau/nv50_display.c -index 06de250..8b78b9c 100644 ---- a/drivers/gpu/drm/nouveau/nv50_display.c -+++ b/drivers/gpu/drm/nouveau/nv50_display.c -@@ -50,9 +50,76 @@ nv50_sor_nr(struct drm_device *dev) +Index: linux-3.2.46/drivers/gpu/drm/nouveau/nv50_display.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/nouveau/nv50_display.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/nouveau/nv50_display.c 2013-07-26 19:26:23.000000000 +0000 +@@ -50,9 +50,76 @@ return 4; } @@ -64736,7 +64650,7 @@ return 0; } -@@ -62,11 +129,40 @@ nv50_display_late_takedown(struct drm_device *dev) +@@ -62,11 +129,40 @@ } int @@ -64780,7 +64694,7 @@ struct nouveau_channel *evo; int ret, i; u32 val; -@@ -161,16 +257,6 @@ nv50_display_init(struct drm_device *dev) +@@ -161,16 +257,6 @@ NV50_PDISPLAY_INTR_EN_1_CLK_UNK20 | NV50_PDISPLAY_INTR_EN_1_CLK_UNK40); @@ -64797,7 +64711,7 @@ ret = nv50_evo_init(dev); if (ret) return ret; -@@ -178,36 +264,19 @@ nv50_display_init(struct drm_device *dev) +@@ -178,36 +264,19 @@ nv_wr32(dev, NV50_PDISPLAY_OBJECTS, (evo->ramin->vinst >> 8) | 9); @@ -64840,7 +64754,7 @@ struct nv50_display *disp = nv50_display(dev); struct nouveau_channel *evo = disp->master; struct drm_crtc *drm_crtc; -@@ -270,18 +339,10 @@ static int nv50_display_disable(struct drm_device *dev) +@@ -270,18 +339,10 @@ /* disable interrupts. */ nv_wr32(dev, NV50_PDISPLAY_INTR_EN_1, 0x00000000); @@ -64861,7 +64775,7 @@ { struct drm_nouveau_private *dev_priv = dev->dev_private; struct dcb_table *dcb = &dev_priv->vbios.dcb; -@@ -341,7 +402,7 @@ int nv50_display_create(struct drm_device *dev) +@@ -341,7 +402,7 @@ tasklet_init(&priv->tasklet, nv50_display_bh, (unsigned long)dev); nouveau_irq_register(dev, 26, nv50_display_isr); @@ -64870,7 +64784,7 @@ if (ret) { nv50_display_destroy(dev); return ret; -@@ -357,7 +418,7 @@ nv50_display_destroy(struct drm_device *dev) +@@ -357,7 +418,7 @@ NV_DEBUG_KMS(dev, "\n"); @@ -64879,7 +64793,7 @@ nouveau_irq_unregister(dev, 26); kfree(disp); } -@@ -413,15 +474,15 @@ nv50_display_flip_next(struct drm_crtc *crtc, struct drm_framebuffer *fb, +@@ -413,15 +474,15 @@ } if (dev_priv->chipset < 0xc0) { @@ -64899,7 +64813,7 @@ if (dev_priv->chipset < 0x84) OUT_RING (chan, NvSema); else -@@ -429,12 +490,12 @@ nv50_display_flip_next(struct drm_crtc *crtc, struct drm_framebuffer *fb, +@@ -429,12 +490,12 @@ } else { u64 offset = chan->dispc_vma[nv_crtc->index].offset; offset += dispc->sem.offset; @@ -64914,7 +64828,7 @@ OUT_RING (chan, upper_32_bits(offset)); OUT_RING (chan, lower_32_bits(offset ^ 0x10)); OUT_RING (chan, 0x74b1e000); -@@ -521,7 +582,7 @@ nv50_display_script_select(struct drm_device *dev, struct dcb_entry *dcb, +@@ -521,7 +582,7 @@ } else { /* determine number of lvds links */ if (nv_connector && nv_connector->edid && @@ -64923,7 +64837,7 @@ /* http://www.spwg.org */ if (((u8 *)nv_connector->edid)[121] == 2) script |= 0x0100; -@@ -722,8 +783,8 @@ nv50_display_unk20_handler(struct drm_device *dev) +@@ -722,8 +783,8 @@ if (crtc >= 0) { pclk = nv_rd32(dev, NV50_PDISPLAY_CRTC_P(crtc, CLOCK)); pclk &= 0x003fffff; @@ -64934,7 +64848,7 @@ tmp = nv_rd32(dev, NV50_PDISPLAY_CRTC_CLK_CTRL2(crtc)); tmp &= ~0x000000f; -@@ -802,9 +863,9 @@ nv50_display_unk20_handler(struct drm_device *dev) +@@ -802,9 +863,9 @@ if (type == OUTPUT_DP) { int link = !(dcb->dpconf.sor.link & 1); if ((mc & 0x000f0000) == 0x00020000) @@ -64946,11 +64860,11 @@ } if (dcb->type != OUTPUT_ANALOG) { -diff --git a/drivers/gpu/drm/nouveau/nv50_display.h b/drivers/gpu/drm/nouveau/nv50_display.h -index c2da503..5d3dd14 100644 ---- a/drivers/gpu/drm/nouveau/nv50_display.h -+++ b/drivers/gpu/drm/nouveau/nv50_display.h -@@ -69,14 +69,20 @@ int nv50_display_early_init(struct drm_device *dev); +Index: linux-3.2.46/drivers/gpu/drm/nouveau/nv50_display.h +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/nouveau/nv50_display.h 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/nouveau/nv50_display.h 2013-07-26 19:26:23.000000000 +0000 +@@ -69,14 +69,20 @@ void nv50_display_late_takedown(struct drm_device *dev); int nv50_display_create(struct drm_device *dev); int nv50_display_init(struct drm_device *dev); @@ -64971,11 +64885,11 @@ int nv50_evo_init(struct drm_device *dev); void nv50_evo_fini(struct drm_device *dev); void nv50_evo_dmaobj_init(struct nouveau_gpuobj *, u32 memtype, u64 base, -diff --git a/drivers/gpu/drm/nouveau/nv50_evo.c b/drivers/gpu/drm/nouveau/nv50_evo.c -index c99d975..9b962e9 100644 ---- a/drivers/gpu/drm/nouveau/nv50_evo.c -+++ b/drivers/gpu/drm/nouveau/nv50_evo.c -@@ -218,7 +218,7 @@ nv50_evo_channel_fini(struct nouveau_channel *evo) +Index: linux-3.2.46/drivers/gpu/drm/nouveau/nv50_evo.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/nouveau/nv50_evo.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/nouveau/nv50_evo.c 2013-07-26 19:26:23.000000000 +0000 +@@ -218,7 +218,7 @@ } } @@ -64984,7 +64898,7 @@ nv50_evo_destroy(struct drm_device *dev) { struct nv50_display *disp = nv50_display(dev); -@@ -235,7 +235,7 @@ nv50_evo_destroy(struct drm_device *dev) +@@ -235,7 +235,7 @@ nv50_evo_channel_del(&disp->master); } @@ -64993,7 +64907,7 @@ nv50_evo_create(struct drm_device *dev) { struct drm_nouveau_private *dev_priv = dev->dev_private; -@@ -388,12 +388,6 @@ nv50_evo_init(struct drm_device *dev) +@@ -388,12 +388,6 @@ struct nv50_display *disp = nv50_display(dev); int ret, i; @@ -65006,17 +64920,17 @@ ret = nv50_evo_channel_init(disp->master); if (ret) return ret; -@@ -420,6 +414,4 @@ nv50_evo_fini(struct drm_device *dev) +@@ -420,6 +414,4 @@ if (disp->master) nv50_evo_channel_fini(disp->master); - - nv50_evo_destroy(dev); } -diff --git a/drivers/gpu/drm/nouveau/nv50_evo.h b/drivers/gpu/drm/nouveau/nv50_evo.h -index 3860ca6..771d879 100644 ---- a/drivers/gpu/drm/nouveau/nv50_evo.h -+++ b/drivers/gpu/drm/nouveau/nv50_evo.h +Index: linux-3.2.46/drivers/gpu/drm/nouveau/nv50_evo.h +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/nouveau/nv50_evo.h 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/nouveau/nv50_evo.h 2013-07-26 19:26:23.000000000 +0000 @@ -104,7 +104,8 @@ #define NV50_EVO_CRTC_SCALE_CTRL_INACTIVE 0x00000000 #define NV50_EVO_CRTC_SCALE_CTRL_ACTIVE 0x00000009 @@ -65027,11 +64941,11 @@ #define NV50_EVO_CRTC_FB_POS 0x000008c0 #define NV50_EVO_CRTC_REAL_RES 0x000008c8 #define NV50_EVO_CRTC_SCALE_CENTER_OFFSET 0x000008d4 -diff --git a/drivers/gpu/drm/nouveau/nv50_fifo.c b/drivers/gpu/drm/nouveau/nv50_fifo.c -index c34a074..3bc2a56 100644 ---- a/drivers/gpu/drm/nouveau/nv50_fifo.c -+++ b/drivers/gpu/drm/nouveau/nv50_fifo.c -@@ -230,6 +230,7 @@ nv50_fifo_create_context(struct nouveau_channel *chan) +Index: linux-3.2.46/drivers/gpu/drm/nouveau/nv50_fifo.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/nouveau/nv50_fifo.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/nouveau/nv50_fifo.c 2013-07-26 19:26:23.000000000 +0000 +@@ -230,6 +230,7 @@ struct drm_device *dev = chan->dev; struct drm_nouveau_private *dev_priv = dev->dev_private; struct nouveau_gpuobj *ramfc = NULL; @@ -65039,7 +64953,7 @@ unsigned long flags; int ret; -@@ -280,8 +281,9 @@ nv50_fifo_create_context(struct nouveau_channel *chan) +@@ -280,8 +281,9 @@ nv_wo32(ramfc, 0x7c, 0x30000001); nv_wo32(ramfc, 0x78, 0x00000000); nv_wo32(ramfc, 0x3c, 0x403f6078); @@ -65051,10 +64965,10 @@ if (dev_priv->chipset != 0x50) { nv_wo32(chan->ramin, 0, chan->id); -diff --git a/drivers/gpu/drm/nouveau/nv50_gpio.c b/drivers/gpu/drm/nouveau/nv50_gpio.c -index 793a5cc..f429e6a 100644 ---- a/drivers/gpu/drm/nouveau/nv50_gpio.c -+++ b/drivers/gpu/drm/nouveau/nv50_gpio.c +Index: linux-3.2.46/drivers/gpu/drm/nouveau/nv50_gpio.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/nouveau/nv50_gpio.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/nouveau/nv50_gpio.c 2013-07-26 19:26:23.000000000 +0000 @@ -25,229 +25,95 @@ #include "drmP.h" #include "nouveau_drv.h" @@ -65152,13 +65066,13 @@ { - struct dcb_gpio_entry *gpio; - u32 v; -- -- gpio = nouveau_bios_gpio_entry(dev, tag); -- if (!gpio) -- return -ENOENT; + u32 reg = line < 16 ? 0xe050 : 0xe070; + u32 mask = 0x00010001 << (line & 0xf); +- gpio = nouveau_bios_gpio_entry(dev, tag); +- if (!gpio) +- return -ENOENT; +- - v = nv_rd32(dev, 0x00d610 + (gpio->line * 4)); - v &= 0x00004000; - return (!!v == (gpio->state[1] & 1)); @@ -65277,13 +65191,13 @@ struct drm_nouveau_private *dev_priv = dev->dev_private; - struct nouveau_gpio_engine *pgpio = &dev_priv->engine.gpio; - struct nv50_gpio_priv *priv; -- -- priv = kzalloc(sizeof(*priv), GFP_KERNEL); -- if (!priv) -- return -ENOMEM; + u32 intr0, intr1 = 0; + u32 hi, lo; +- priv = kzalloc(sizeof(*priv), GFP_KERNEL); +- if (!priv) +- return -ENOMEM; +- - INIT_LIST_HEAD(&priv->handlers); - spin_lock_init(&priv->lock); - pgpio->priv = priv; @@ -65324,7 +65238,7 @@ /* disable, and ack any pending gpio interrupts */ nv_wr32(dev, 0xe050, 0x00000000); -@@ -270,64 +136,4 @@ nv50_gpio_fini(struct drm_device *dev) +@@ -270,64 +136,4 @@ if (dev_priv->chipset >= 0x90) nv_wr32(dev, 0xe070, 0x00000000); nouveau_irq_unregister(dev, 21); @@ -65389,11 +65303,11 @@ - } - spin_unlock(&priv->lock); } -diff --git a/drivers/gpu/drm/nouveau/nv50_graph.c b/drivers/gpu/drm/nouveau/nv50_graph.c -index ac601f7..33d5711 100644 ---- a/drivers/gpu/drm/nouveau/nv50_graph.c -+++ b/drivers/gpu/drm/nouveau/nv50_graph.c -@@ -616,9 +616,9 @@ nv50_pgraph_tp_trap(struct drm_device *dev, int type, uint32_t ustatus_old, +Index: linux-3.2.46/drivers/gpu/drm/nouveau/nv50_graph.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/nouveau/nv50_graph.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/nouveau/nv50_graph.c 2013-07-26 19:26:23.000000000 +0000 +@@ -616,9 +616,9 @@ } break; case 7: /* MP error */ @@ -65405,10 +65319,10 @@ } break; case 8: /* TPDMA error */ -diff --git a/drivers/gpu/drm/nouveau/nv50_pm.c b/drivers/gpu/drm/nouveau/nv50_pm.c -index 3d5a86b..d020ed4 100644 ---- a/drivers/gpu/drm/nouveau/nv50_pm.c -+++ b/drivers/gpu/drm/nouveau/nv50_pm.c +Index: linux-3.2.46/drivers/gpu/drm/nouveau/nv50_pm.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/nouveau/nv50_pm.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/nouveau/nv50_pm.c 2013-07-26 19:26:23.000000000 +0000 @@ -25,122 +25,862 @@ #include "drmP.h" #include "nouveau_drv.h" @@ -65770,7 +65684,9 @@ if (ret) - return ret; + return 0; -+ + +- reg0 = nv_rd32(dev, pll.reg + 0); +- reg1 = nv_rd32(dev, pll.reg + 4); + pll->vco2.maxfreq = 0; + pll->refclk = read_pll_ref(dev, reg); + if (!pll->refclk) @@ -65779,10 +65695,13 @@ + ret = nouveau_calc_pll_mnp(dev, pll, clk, &coef); + if (ret == 0) + return 0; ++ ++ *N1 = coef.N1; ++ *M1 = coef.M1; ++ *log2P = coef.log2P; ++ return ret; ++} -- reg0 = nv_rd32(dev, pll.reg + 0); -- reg1 = nv_rd32(dev, pll.reg + 4); -- - if ((reg0 & 0x80000000) == 0) { - if (id == PLL_SHADER) { - NV_DEBUG(dev, "Shader PLL is disabled. " @@ -65794,12 +65713,6 @@ - NV_DEBUG(dev, "Memory PLL is disabled. " - "Memory clock is equal to the ref_clk\n"); - return pll.refclk; -+ *N1 = coef.N1; -+ *M1 = coef.M1; -+ *log2P = coef.log2P; -+ return ret; -+} -+ +static inline u32 +calc_div(u32 src, u32 target, int *div) +{ @@ -65896,9 +65809,12 @@ + if (dev_priv->vram_rank_B) + hwsq_wr32(hwsq, 0x1002e8 + ((mr - 2) * 4), data); + hwsq_wr32(hwsq, 0x1002e0 + ((mr - 2) * 4), data); -+ } + } +} -+ + +- P = (reg0 & 0x00070000) >> 16; +- N = (reg1 & 0x0000ff00) >> 8; +- M = (reg1 & 0x000000ff); +static void +mclk_clock_set(struct nouveau_mem_exec_func *exec) +{ @@ -65916,7 +65832,8 @@ + hwsq_wr32(hwsq, 0x400c, info->mcoef); + hwsq_wr32(hwsq, 0x4008, info->mctrl); +} -+ + +- return ((pll.refclk * N / M) >> P); +static void +mclk_timing_set(struct nouveau_mem_exec_func *exec) +{ @@ -65971,11 +65888,8 @@ + info->mctrl |= 0x80000000 | (P << 22) | (P << 16); + info->mctrl |= pll.log2p_bias << 19; + info->mcoef = (N << 8) | M; - } - -- P = (reg0 & 0x00070000) >> 16; -- N = (reg1 & 0x0000ff00) >> 8; -- M = (reg1 & 0x000000ff); ++ } ++ + /* build the ucode which will reclock the memory for us */ + hwsq_init(hwsq); + if (crtc_mask) { @@ -65986,8 +65900,7 @@ + hwsq_wr32(hwsq, 0x611200, 0x00003300); /* disable scanout */ + hwsq_setf(hwsq, 0x10, 0); /* disable bus access */ + hwsq_op5f(hwsq, 0x00, 0x01); /* no idea :s */ - -- return ((pll.refclk * N / M) >> P); ++ + ret = nouveau_mem_exec(&exec, perflvl); + if (ret) + return ret; @@ -66014,13 +65927,13 @@ + u32 out, mast, divs, ctrl; + int clk, ret = -EINVAL; + int N, M, P1, P2; - -- state = kzalloc(sizeof(*state), GFP_KERNEL); -- if (!state) ++ + if (dev_priv->chipset == 0xaa || + dev_priv->chipset == 0xac) + return ERR_PTR(-ENODEV); -+ + +- state = kzalloc(sizeof(*state), GFP_KERNEL); +- if (!state) + info = kmalloc(sizeof(*info), GFP_KERNEL); + if (!info) return ERR_PTR(-ENOMEM); @@ -66099,12 +66012,21 @@ + } else { + clk = read_clk(dev, clk_src_hclk) * 3; + clk = calc_div(clk, perflvl->dom6, &P1); -+ + +- ret = get_pll_limits(dev, id, &state->pll); +- if (ret < 0) { +- kfree(state); +- return (ret == -ENOENT) ? NULL : ERR_PTR(ret); + mast |= 0x0c000000; + divs |= P1; + } -+ } -+ + } + +- ret = nv50_calc_pll(dev, &state->pll, khz, &state->N, &state->M, +- &dummy, &dummy, &state->P); +- if (ret < 0) { +- kfree(state); +- return ERR_PTR(ret); + /* vdec/dom6: complete switch to new clocks */ + switch (dev_priv->chipset) { + case 0x92: @@ -66115,8 +66037,9 @@ + default: + hwsq_wr32(hwsq, 0x004700, divs); + break; -+ } -+ + } + +- return state; + hwsq_wr32(hwsq, 0x00c040, mast); + + /* core/shader: make sure sclk/nvclk are disconnected from their @@ -66171,26 +66094,32 @@ +error: + kfree(info); + return ERR_PTR(ret); -+} -+ + } + +-void +-nv50_pm_clock_set(struct drm_device *dev, void *pre_state) +static int +prog_hwsq(struct drm_device *dev, struct hwsq_ucode *hwsq) -+{ + { +- struct nv50_pm_state *state = pre_state; +- struct nouveau_pm_level *perflvl = state->perflvl; +- u32 reg = state->pll.reg, tmp; +- struct bit_entry BIT_M; +- u16 script; +- int N = state->N; +- int M = state->M; +- int P = state->P; + struct drm_nouveau_private *dev_priv = dev->dev_private; + u32 hwsq_data, hwsq_kick; + int i; - -- ret = get_pll_limits(dev, id, &state->pll); -- if (ret < 0) { -- kfree(state); -- return (ret == -ENOENT) ? NULL : ERR_PTR(ret); ++ + if (dev_priv->chipset < 0x94) { + hwsq_data = 0x001400; + hwsq_kick = 0x00000003; + } else { + hwsq_data = 0x080000; + hwsq_kick = 0x00000001; - } ++ } + /* upload hwsq ucode */ + nv_mask(dev, 0x001098, 0x00000008, 0x00000000); + nv_wr32(dev, 0x001304, 0x00000000); @@ -66210,42 +66139,6 @@ + nv_rd32(dev, 0x001400 + (i * 4))); + } -- ret = nv50_calc_pll(dev, &state->pll, khz, &state->N, &state->M, -- &dummy, &dummy, &state->P); -- if (ret < 0) { -- kfree(state); -- return ERR_PTR(ret); -+ return -EIO; - } - -- return state; -+ return 0; - } - --void --nv50_pm_clock_set(struct drm_device *dev, void *pre_state) -+int -+nv50_pm_clocks_set(struct drm_device *dev, void *data) - { -- struct nv50_pm_state *state = pre_state; -- struct nouveau_pm_level *perflvl = state->perflvl; -- u32 reg = state->pll.reg, tmp; -- struct bit_entry BIT_M; -- u16 script; -- int N = state->N; -- int M = state->M; -- int P = state->P; -+ struct nv50_pm_state *info = data; -+ struct bit_entry M; -+ int ret = -EBUSY; -+ -+ /* halt and idle execution engines */ -+ nv_mask(dev, 0x002504, 0x00000001, 0x00000001); -+ if (!nv_wait(dev, 0x002504, 0x00000010, 0x00000010)) -+ goto resume; -+ if (!nv_wait(dev, 0x00251c, 0x0000003f, 0x0000003f)) -+ goto resume; - - if (state->type == PLL_MEMORY && perflvl->memscript && - bit_table(dev, 'M', &BIT_M) == 0 && - BIT_M.version == 1 && BIT_M.length >= 0x0b) { @@ -66258,6 +66151,27 @@ - script = ROM16(BIT_M.data[0x09]); - if (script) - nouveau_bios_run_init_table(dev, script, NULL, -1); ++ return -EIO; ++ } + +- nouveau_bios_run_init_table(dev, perflvl->memscript, NULL, -1); ++ return 0; ++} ++ ++int ++nv50_pm_clocks_set(struct drm_device *dev, void *data) ++{ ++ struct nv50_pm_state *info = data; ++ struct bit_entry M; ++ int ret = -EBUSY; ++ ++ /* halt and idle execution engines */ ++ nv_mask(dev, 0x002504, 0x00000001, 0x00000001); ++ if (!nv_wait(dev, 0x002504, 0x00000010, 0x00000010)) ++ goto resume; ++ if (!nv_wait(dev, 0x00251c, 0x0000003f, 0x0000003f)) ++ goto resume; ++ + /* program memory clock, if necessary - must come before engine clock + * reprogramming due to how we construct the hwsq scripts in pre() + */ @@ -66272,8 +66186,7 @@ + nouveau_bios_init_exec(dev, ROM16(M.data[9])); + nouveau_bios_init_exec(dev, info->mscript); + } - -- nouveau_bios_run_init_table(dev, perflvl->memscript, NULL, -1); ++ + ret = prog_hwsq(dev, &info->mclk_hwsq); + if (ret) + goto resume; @@ -66352,10 +66265,10 @@ + nv_wr32(dev, 0x00e118 + (id * 8), duty | 0x80000000); + return 0; +} -diff --git a/drivers/gpu/drm/nouveau/nv50_sor.c b/drivers/gpu/drm/nouveau/nv50_sor.c -index 2633aa8..2746402 100644 ---- a/drivers/gpu/drm/nouveau/nv50_sor.c -+++ b/drivers/gpu/drm/nouveau/nv50_sor.c +Index: linux-3.2.46/drivers/gpu/drm/nouveau/nv50_sor.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/nouveau/nv50_sor.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/nouveau/nv50_sor.c 2013-07-26 19:26:23.000000000 +0000 @@ -36,6 +36,193 @@ #include "nouveau_crtc.h" #include "nv50_display.h" @@ -66550,7 +66463,7 @@ static void nv50_sor_disconnect(struct drm_encoder *encoder) { -@@ -60,6 +247,8 @@ nv50_sor_disconnect(struct drm_encoder *encoder) +@@ -60,6 +247,8 @@ BEGIN_RING(evo, 0, NV50_EVO_UPDATE, 1); OUT_RING (evo, 0); @@ -66559,7 +66472,7 @@ nv_encoder->crtc = NULL; nv_encoder->last_dpms = DRM_MODE_DPMS_OFF; } -@@ -115,20 +304,13 @@ nv50_sor_dpms(struct drm_encoder *encoder, int mode) +@@ -115,20 +304,13 @@ } if (nv_encoder->dcb->type == OUTPUT_DP) { @@ -66586,7 +66499,7 @@ } } -@@ -160,11 +342,8 @@ nv50_sor_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode, +@@ -160,11 +342,8 @@ } if (connector->scaling_mode != DRM_MODE_SCALE_NONE && @@ -66600,7 +66513,7 @@ return true; } -@@ -172,6 +351,12 @@ nv50_sor_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode, +@@ -172,6 +351,12 @@ static void nv50_sor_prepare(struct drm_encoder *encoder) { @@ -66613,7 +66526,7 @@ } static void -@@ -180,8 +365,8 @@ nv50_sor_commit(struct drm_encoder *encoder) +@@ -180,8 +365,8 @@ } static void @@ -66624,7 +66537,7 @@ { struct nouveau_channel *evo = nv50_display(encoder->dev)->master; struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); -@@ -193,24 +378,27 @@ nv50_sor_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode, +@@ -193,24 +378,27 @@ NV_DEBUG_KMS(dev, "or %d type %d -> crtc %d\n", nv_encoder->or, nv_encoder->dcb->type, crtc->index); @@ -66655,7 +66568,7 @@ mode_ctl |= 0x00050000; } -@@ -228,10 +416,10 @@ nv50_sor_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode, +@@ -228,10 +416,10 @@ else mode_ctl |= NV50_EVO_SOR_MODE_CTRL_CRTC0; @@ -66668,7 +66581,7 @@ mode_ctl |= NV50_EVO_SOR_MODE_CTRL_NVSYNC; nv50_sor_dpms(encoder, DRM_MODE_DPMS_ON); -@@ -239,12 +427,11 @@ nv50_sor_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode, +@@ -239,12 +427,11 @@ ret = RING_SPACE(evo, 2); if (ret) { NV_ERROR(dev, "no space while connecting SOR\n"); @@ -66682,11 +66595,11 @@ } static struct drm_crtc * -diff --git a/drivers/gpu/drm/nouveau/nv50_vm.c b/drivers/gpu/drm/nouveau/nv50_vm.c -index 40b84f2..44fbac9 100644 ---- a/drivers/gpu/drm/nouveau/nv50_vm.c -+++ b/drivers/gpu/drm/nouveau/nv50_vm.c -@@ -48,7 +48,7 @@ nv50_vm_map_pgt(struct nouveau_gpuobj *pgd, u32 pde, +Index: linux-3.2.46/drivers/gpu/drm/nouveau/nv50_vm.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/nouveau/nv50_vm.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/nouveau/nv50_vm.c 2013-07-26 19:26:23.000000000 +0000 +@@ -48,7 +48,7 @@ phys |= 0x60; else if (coverage <= 64 * 1024 * 1024) phys |= 0x40; @@ -66695,7 +66608,7 @@ phys |= 0x20; } -@@ -57,27 +57,15 @@ nv50_vm_map_pgt(struct nouveau_gpuobj *pgd, u32 pde, +@@ -57,27 +57,15 @@ } static inline u64 @@ -66724,7 +66637,7 @@ return phys; } -@@ -85,11 +73,19 @@ void +@@ -85,11 +73,19 @@ nv50_vm_map(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt, struct nouveau_mem *mem, u32 pte, u32 cnt, u64 phys, u64 delta) { @@ -66746,7 +66659,7 @@ pte <<= 3; cnt <<= 3; -@@ -125,9 +121,10 @@ void +@@ -125,9 +121,10 @@ nv50_vm_map_sg(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt, struct nouveau_mem *mem, u32 pte, u32 cnt, dma_addr_t *list) { @@ -66758,11 +66671,11 @@ nv_wo32(pgt, pte + 0, lower_32_bits(phys)); nv_wo32(pgt, pte + 4, upper_32_bits(phys)); pte += 8; -diff --git a/drivers/gpu/drm/nouveau/nv50_vram.c b/drivers/gpu/drm/nouveau/nv50_vram.c -index 2e45e57..9ed9ae39 100644 ---- a/drivers/gpu/drm/nouveau/nv50_vram.c -+++ b/drivers/gpu/drm/nouveau/nv50_vram.c -@@ -189,8 +189,25 @@ nv50_vram_init(struct drm_device *dev) +Index: linux-3.2.46/drivers/gpu/drm/nouveau/nv50_vram.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/nouveau/nv50_vram.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/nouveau/nv50_vram.c 2013-07-26 19:26:23.000000000 +0000 +@@ -189,8 +189,25 @@ struct nouveau_vram_engine *vram = &dev_priv->engine.vram; const u32 rsvd_head = ( 256 * 1024) >> 12; /* vga memory */ const u32 rsvd_tail = (1024 * 1024) >> 12; /* vbios etc */ @@ -66788,11 +66701,10 @@ dev_priv->vram_size = nv_rd32(dev, 0x10020c); dev_priv->vram_size |= (dev_priv->vram_size & 0xff) << 32; dev_priv->vram_size &= 0xffffffff00ULL; -diff --git a/drivers/gpu/drm/nouveau/nv84_bsp.c b/drivers/gpu/drm/nouveau/nv84_bsp.c -new file mode 100644 -index 0000000..7487573 ---- /dev/null -+++ b/drivers/gpu/drm/nouveau/nv84_bsp.c +Index: linux-3.2.46/drivers/gpu/drm/nouveau/nv84_bsp.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/nouveau/nv84_bsp.c 2013-07-26 19:26:23.000000000 +0000 @@ -0,0 +1,83 @@ +/* + * Copyright 2011 Red Hat Inc. @@ -66877,11 +66789,10 @@ + NVOBJ_ENGINE_ADD(dev, BSP, &pbsp->base); + return 0; +} -diff --git a/drivers/gpu/drm/nouveau/nv84_vp.c b/drivers/gpu/drm/nouveau/nv84_vp.c -new file mode 100644 -index 0000000..6570d30 ---- /dev/null -+++ b/drivers/gpu/drm/nouveau/nv84_vp.c +Index: linux-3.2.46/drivers/gpu/drm/nouveau/nv84_vp.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/nouveau/nv84_vp.c 2013-07-26 19:26:23.000000000 +0000 @@ -0,0 +1,83 @@ +/* + * Copyright 2011 Red Hat Inc. @@ -66966,11 +66877,10 @@ + NVOBJ_ENGINE_ADD(dev, VP, &pvp->base); + return 0; +} -diff --git a/drivers/gpu/drm/nouveau/nv98_crypt.c b/drivers/gpu/drm/nouveau/nv98_crypt.c -new file mode 100644 -index 0000000..db94ff0 ---- /dev/null -+++ b/drivers/gpu/drm/nouveau/nv98_crypt.c +Index: linux-3.2.46/drivers/gpu/drm/nouveau/nv98_crypt.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/nouveau/nv98_crypt.c 2013-07-26 19:26:23.000000000 +0000 @@ -0,0 +1,78 @@ +/* + * Copyright 2011 Red Hat Inc. @@ -67050,11 +66960,10 @@ + NVOBJ_ENGINE_ADD(dev, CRYPT, &pcrypt->base); + return 0; +} -diff --git a/drivers/gpu/drm/nouveau/nv98_ppp.c b/drivers/gpu/drm/nouveau/nv98_ppp.c -new file mode 100644 -index 0000000..a987dd6 ---- /dev/null -+++ b/drivers/gpu/drm/nouveau/nv98_ppp.c +Index: linux-3.2.46/drivers/gpu/drm/nouveau/nv98_ppp.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/nouveau/nv98_ppp.c 2013-07-26 19:26:23.000000000 +0000 @@ -0,0 +1,78 @@ +/* + * Copyright 2011 Red Hat Inc. @@ -67134,10 +67043,10 @@ + NVOBJ_ENGINE_ADD(dev, PPP, &pppp->base); + return 0; +} -diff --git a/drivers/gpu/drm/nouveau/nva3_copy.fuc b/drivers/gpu/drm/nouveau/nva3_copy.fuc -index d894731..219850d 100644 ---- a/drivers/gpu/drm/nouveau/nva3_copy.fuc -+++ b/drivers/gpu/drm/nouveau/nva3_copy.fuc +Index: linux-3.2.46/drivers/gpu/drm/nouveau/nva3_copy.fuc +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/nouveau/nva3_copy.fuc 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/nouveau/nva3_copy.fuc 2013-07-26 19:26:23.000000000 +0000 @@ -31,8 +31,9 @@ */ @@ -67150,7 +67059,7 @@ ) ctx_object: .b32 0 -@@ -42,7 +43,7 @@ ctx_dma_query: .b32 0 +@@ -42,7 +43,7 @@ ctx_dma_src: .b32 0 ctx_dma_dst: .b32 0 ,) @@ -67159,7 +67068,7 @@ ctx_query_address_high: .b32 0 ctx_query_address_low: .b32 0 ctx_query_counter: .b32 0 -@@ -78,64 +79,65 @@ ctx_ycnt: .b32 0 +@@ -78,64 +79,65 @@ dispatch_table: // mthd 0x0000, NAME .b16 0x000 1 @@ -67264,7 +67173,7 @@ ) main: -@@ -143,12 +145,12 @@ main: +@@ -143,12 +145,12 @@ mov $sp $r0 // setup i0 handler and route fifo and ctxswitch to it @@ -67279,7 +67188,7 @@ // enable interrupts or $r2 0xc -@@ -164,19 +166,19 @@ main: +@@ -164,19 +166,19 @@ bset $flags $p0 spin: sleep $p0 @@ -67304,7 +67213,7 @@ ih_no_cmd: and $r1 $r1 0x0000000c -@@ -235,9 +237,9 @@ ifdef(`NVA3', ` +@@ -235,9 +237,9 @@ sethi $r4 0x60000 // swap! @@ -67316,7 +67225,7 @@ swctx_load: xdld $r0 $r4 swctx_done: -@@ -251,9 +253,9 @@ chsw: +@@ -251,9 +253,9 @@ // if it's active, unload it and return xbit $r15 $r3 0x1e @@ -67328,7 +67237,7 @@ bclr $r3 0x1e iowr I[$r2] $r3 mov $r4 1 -@@ -266,20 +268,20 @@ chsw: +@@ -266,20 +268,20 @@ // is there a channel waiting to be loaded? xbit $r13 $r3 0x1e @@ -67354,7 +67263,7 @@ ,) chsw_finish_load: -@@ -297,7 +299,7 @@ dispatch: +@@ -297,7 +299,7 @@ shl b32 $r2 0x10 // lookup method in the dispatch table, ILLEGAL_MTHD if not found @@ -67363,7 +67272,7 @@ clear b32 $r6 clear b32 $r7 dispatch_loop: -@@ -305,14 +307,14 @@ dispatch: +@@ -305,14 +307,14 @@ ld b16 $r7 D[$r5 + 2] add b32 $r5 4 cmpu b32 $r4 $r6 @@ -67381,7 +67290,7 @@ // ensure no bits set in reserved fields, INVALID_BITFIELD dispatch_valid_mthd: -@@ -322,20 +324,20 @@ dispatch: +@@ -322,20 +324,20 @@ ld b32 $r5 D[$r4 + 4] and $r5 $r3 cmpu b32 $r5 0 @@ -67407,7 +67316,7 @@ dispatch_invalid_bitfield: or $r2 2 -@@ -353,7 +355,7 @@ dispatch: +@@ -353,7 +355,7 @@ iord $r2 I[$r0 + 0x200] and $r2 0x40 cmpu b32 $r2 0 @@ -67416,7 +67325,7 @@ dispatch_done: mov $r2 0x1d00 -@@ -409,10 +411,10 @@ ifdef(`NVA3', +@@ -409,10 +411,10 @@ // $r2: hostirq state // $r3: data cmd_dma: @@ -67429,7 +67338,7 @@ add b32 $r4 0x600 shl b32 $r4 6 iowr I[$r4] $r3 -@@ -430,7 +432,7 @@ cmd_exec_set_format: +@@ -430,7 +432,7 @@ st b32 D[$sp + 0x0c] $r0 // extract cpp, src_ncomp and dst_ncomp from FORMAT @@ -67438,7 +67347,7 @@ extr $r5 $r4 16:17 add b32 $r5 1 extr $r6 $r4 20:21 -@@ -448,22 +450,22 @@ cmd_exec_set_format: +@@ -448,22 +450,22 @@ clear b32 $r11 bpc_loop: cmpu b8 $r10 4 @@ -67467,7 +67376,7 @@ cmp_zero: mov $r12 0x80 bpc_next: -@@ -471,22 +473,22 @@ cmd_exec_set_format: +@@ -471,22 +473,22 @@ add b32 $r8 1 add b32 $r11 1 cmpu b32 $r11 $r5 @@ -67496,7 +67405,7 @@ mulu $r7 $r8 mov $r5 0x810 -@@ -494,10 +496,10 @@ cmd_exec_set_format: +@@ -494,10 +496,10 @@ iowr I[$r5 + 0x000] $r6 iowr I[$r5 + 0x100] $r7 add b32 $r5 0x800 @@ -67509,7 +67418,7 @@ sub b32 $r7 1 or $r6 $r7 iowr I[$r5 + 0x000] $r6 -@@ -511,9 +513,9 @@ cmd_exec_set_format: +@@ -511,9 +513,9 @@ ld b32 $r6 D[$sp + 0x0c] iowr I[$r5 + 0x300] $r6 add b32 $r5 0x400 @@ -67521,7 +67430,7 @@ iowr I[$r5 + 0x100] $r6 add $sp 0x10 ret -@@ -543,7 +545,7 @@ cmd_exec_set_format: +@@ -543,7 +545,7 @@ // cmd_exec_set_surface_tiled: // translate TILE_MODE into Tp, Th, Td shift values @@ -67530,7 +67439,7 @@ extr $r9 $r7 8:11 extr $r8 $r7 4:7 ifdef(`NVA3', -@@ -553,9 +555,9 @@ ifdef(`NVA3', +@@ -553,9 +555,9 @@ ) extr $r7 $r7 0:3 cmp b32 $r7 0xe @@ -67542,7 +67451,7 @@ xtile64: xbit $r7 $flags $p2 add b32 $r7 17 -@@ -565,8 +567,8 @@ ifdef(`NVA3', +@@ -565,8 +567,8 @@ // Op = (x * cpp) & ((1 << Tp) - 1) // Tx = (x * cpp) >> Tp @@ -67553,7 +67462,7 @@ mulu $r10 $r11 mov $r11 1 shl b32 $r11 $r7 -@@ -576,7 +578,7 @@ ifdef(`NVA3', +@@ -576,7 +578,7 @@ // Tyo = y & ((1 << Th) - 1) // Ty = y >> Th @@ -67562,7 +67471,7 @@ mov $r14 1 shl b32 $r14 $r8 sub b32 $r14 1 -@@ -598,8 +600,8 @@ ifdef(`NVA3', +@@ -598,8 +600,8 @@ add b32 $r12 $r11 // nTx = ((w * cpp) + ((1 << Tp) - 1) >> Tp) @@ -67573,7 +67482,7 @@ mulu $r15 $r11 mov $r11 1 shl b32 $r11 $r7 -@@ -609,7 +611,7 @@ ifdef(`NVA3', +@@ -609,7 +611,7 @@ push $r15 // nTy = (h + ((1 << Th) - 1)) >> Th @@ -67582,7 +67491,7 @@ mov $r11 1 shl b32 $r11 $r8 sub b32 $r11 1 -@@ -629,7 +631,7 @@ ifdef(`NVA3', +@@ -629,7 +631,7 @@ // Tz = z >> Td // Op += Tzo << Tys // Ts = Tys + Td @@ -67591,7 +67500,7 @@ mov $r14 1 shl b32 $r14 $r9 sub b32 $r14 1 -@@ -656,8 +658,8 @@ ifdef(`NVA3', +@@ -656,8 +658,8 @@ // SRC_ADDRESS_LOW = (Ot + Op) & 0xffffffff // CFG_ADDRESS_HIGH |= ((Ot + Op) >> 32) << 16 @@ -67602,7 +67511,7 @@ add b32 $r10 $r12 add b32 $r7 $r10 adc b32 $r8 0 -@@ -677,14 +679,14 @@ cmd_exec_set_surface_linear: +@@ -677,14 +679,14 @@ xbit $r6 $flags $p2 add b32 $r6 0x202 shl b32 $r6 8 @@ -67620,7 +67529,7 @@ iowr I[$r6 + 0x000] $r7 ret -@@ -697,7 +699,7 @@ cmd_exec_wait: +@@ -697,7 +699,7 @@ loop: iord $r1 I[$r0] and $r1 1 @@ -67629,7 +67538,7 @@ pop $r1 pop $r0 ret -@@ -705,18 +707,18 @@ cmd_exec_wait: +@@ -705,18 +707,18 @@ cmd_exec_query: // if QUERY_SHORT not set, write out { -, 0, TIME_LO, TIME_HI } xbit $r4 $r3 13 @@ -67652,7 +67561,7 @@ shl b32 $r5 16 iowr I[$r4 + 0x000] $r5 add b32 $r4 0x500 -@@ -741,16 +743,16 @@ cmd_exec_query: +@@ -741,16 +743,16 @@ // write COUNTER query_counter: @@ -67672,7 +67581,7 @@ shl b32 $r5 16 iowr I[$r4 + 0x000] $r5 add b32 $r4 0x500 -@@ -759,7 +761,7 @@ cmd_exec_query: +@@ -759,7 +761,7 @@ mov $r5 0x00001110 sethi $r5 0x13120000 iowr I[$r4 + 0x100] $r5 @@ -67681,7 +67590,7 @@ add b32 $r4 0x500 iowr I[$r4 + 0x000] $r5 mov $r5 0x00002601 -@@ -787,22 +789,22 @@ cmd_exec_query: +@@ -787,22 +789,22 @@ // $r2: hostirq state // $r3: data cmd_exec: @@ -67711,7 +67620,7 @@ iowr I[$r6 + 0x000] $r7 iowr I[$r6 + 0x100] $r7 clear b32 $r4 -@@ -811,28 +813,28 @@ cmd_exec: +@@ -811,28 +813,28 @@ bclr $flags $p2 clear b32 $r5 xbit $r15 $r3 4 @@ -67750,7 +67659,7 @@ iowr I[$r5 + 0x100] $r6 mov $r6 0x0041 // SRC_TARGET = 1, DST_TARGET = 2 -@@ -842,8 +844,8 @@ cmd_exec: +@@ -842,8 +844,8 @@ // if requested, queue up a QUERY write after the copy has completed xbit $r15 $r3 12 @@ -67761,11 +67670,11 @@ cmd_exec_done: ret -diff --git a/drivers/gpu/drm/nouveau/nva3_copy.fuc.h b/drivers/gpu/drm/nouveau/nva3_copy.fuc.h -index e2a0e88..37d6de3 100644 ---- a/drivers/gpu/drm/nouveau/nva3_copy.fuc.h -+++ b/drivers/gpu/drm/nouveau/nva3_copy.fuc.h -@@ -190,7 +190,7 @@ u32 nva3_pcopy_code[] = { +Index: linux-3.2.46/drivers/gpu/drm/nouveau/nva3_copy.fuc.h +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/nouveau/nva3_copy.fuc.h 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/nouveau/nva3_copy.fuc.h 2013-07-26 19:26:23.000000000 +0000 +@@ -190,7 +190,7 @@ 0xf10010fe, 0xf1040017, 0xf0fff327, @@ -67774,11 +67683,11 @@ 0x0c25f0c0, 0xf40012d0, 0x17f11031, -diff --git a/drivers/gpu/drm/nouveau/nva3_pm.c b/drivers/gpu/drm/nouveau/nva3_pm.c -index 618c144..9e636e6 100644 ---- a/drivers/gpu/drm/nouveau/nva3_pm.c -+++ b/drivers/gpu/drm/nouveau/nva3_pm.c -@@ -287,12 +287,13 @@ nva3_pm_grcp_idle(void *data) +Index: linux-3.2.46/drivers/gpu/drm/nouveau/nva3_pm.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/nouveau/nva3_pm.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/nouveau/nva3_pm.c 2013-07-26 19:26:23.000000000 +0000 +@@ -287,12 +287,13 @@ return false; } @@ -67793,7 +67702,7 @@ /* prevent any new grctx switches from starting */ spin_lock_irqsave(&dev_priv->context_switch_lock, flags); -@@ -328,6 +329,8 @@ nva3_pm_clocks_set(struct drm_device *dev, void *pre_state) +@@ -328,6 +329,8 @@ nv_wr32(dev, 0x100210, 0x80000000); } @@ -67802,17 +67711,17 @@ cleanup: /* unfreeze PFIFO */ nv_mask(dev, 0x002504, 0x00000001, 0x00000000); -@@ -339,4 +342,5 @@ cleanup: +@@ -339,4 +342,5 @@ nv_mask(dev, 0x400824, 0x10000000, 0x10000000); spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags); kfree(info); + return ret; } -diff --git a/drivers/gpu/drm/nouveau/nvc0_copy.fuc.h b/drivers/gpu/drm/nouveau/nvc0_copy.fuc.h -index 9e87036..cd879f3 100644 ---- a/drivers/gpu/drm/nouveau/nvc0_copy.fuc.h -+++ b/drivers/gpu/drm/nouveau/nvc0_copy.fuc.h -@@ -178,7 +178,7 @@ u32 nvc0_pcopy_code[] = { +Index: linux-3.2.46/drivers/gpu/drm/nouveau/nvc0_copy.fuc.h +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/nouveau/nvc0_copy.fuc.h 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/nouveau/nvc0_copy.fuc.h 2013-07-26 19:26:23.000000000 +0000 +@@ -178,7 +178,7 @@ 0xf10010fe, 0xf1040017, 0xf0fff327, @@ -67821,11 +67730,11 @@ 0x0c25f0c0, 0xf40012d0, 0x17f11031, -diff --git a/drivers/gpu/drm/nouveau/nvc0_fb.c b/drivers/gpu/drm/nouveau/nvc0_fb.c -index 5bf5503..f704e94 100644 ---- a/drivers/gpu/drm/nouveau/nvc0_fb.c -+++ b/drivers/gpu/drm/nouveau/nvc0_fb.c -@@ -54,6 +54,11 @@ nvc0_mfb_isr(struct drm_device *dev) +Index: linux-3.2.46/drivers/gpu/drm/nouveau/nvc0_fb.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/nouveau/nvc0_fb.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/nouveau/nvc0_fb.c 2013-07-26 19:26:23.000000000 +0000 +@@ -54,6 +54,11 @@ nvc0_mfb_subp_isr(dev, unit, subp); units &= ~(1 << unit); } @@ -67837,11 +67746,11 @@ } static void -diff --git a/drivers/gpu/drm/nouveau/nvc0_fifo.c b/drivers/gpu/drm/nouveau/nvc0_fifo.c -index dcbe0d5..50d68a7 100644 ---- a/drivers/gpu/drm/nouveau/nvc0_fifo.c -+++ b/drivers/gpu/drm/nouveau/nvc0_fifo.c -@@ -436,6 +436,24 @@ nvc0_fifo_isr_vm_fault(struct drm_device *dev, int unit) +Index: linux-3.2.46/drivers/gpu/drm/nouveau/nvc0_fifo.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/nouveau/nvc0_fifo.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/nouveau/nvc0_fifo.c 2013-07-26 19:26:23.000000000 +0000 +@@ -436,6 +436,24 @@ printk(" on channel 0x%010llx\n", (u64)inst << 12); } @@ -67866,23 +67775,23 @@ static void nvc0_fifo_isr_subfifo_intr(struct drm_device *dev, int unit) { -@@ -445,11 +463,21 @@ nvc0_fifo_isr_subfifo_intr(struct drm_device *dev, int unit) +@@ -445,11 +463,21 @@ u32 chid = nv_rd32(dev, 0x040120 + (unit * 0x2000)) & 0x7f; u32 subc = (addr & 0x00070000); u32 mthd = (addr & 0x00003ffc); + u32 show = stat; - -- NV_INFO(dev, "PSUBFIFO %d:", unit); -- nouveau_bitfield_print(nvc0_fifo_subfifo_intr, stat); -- NV_INFO(dev, "PSUBFIFO %d: ch %d subc %d mthd 0x%04x data 0x%08x\n", -- unit, chid, subc, mthd, data); ++ + if (stat & 0x00200000) { + if (mthd == 0x0054) { + if (!nvc0_fifo_page_flip(dev, chid)) + show &= ~0x00200000; + } + } -+ + +- NV_INFO(dev, "PSUBFIFO %d:", unit); +- nouveau_bitfield_print(nvc0_fifo_subfifo_intr, stat); +- NV_INFO(dev, "PSUBFIFO %d: ch %d subc %d mthd 0x%04x data 0x%08x\n", +- unit, chid, subc, mthd, data); + if (show) { + NV_INFO(dev, "PFIFO%d:", unit); + nouveau_bitfield_print(nvc0_fifo_subfifo_intr, show); @@ -67892,11 +67801,11 @@ nv_wr32(dev, 0x0400c0 + (unit * 0x2000), 0x80600008); nv_wr32(dev, 0x040108 + (unit * 0x2000), stat); -diff --git a/drivers/gpu/drm/nouveau/nvc0_graph.c b/drivers/gpu/drm/nouveau/nvc0_graph.c -index ecfafd7..9066102 100644 ---- a/drivers/gpu/drm/nouveau/nvc0_graph.c -+++ b/drivers/gpu/drm/nouveau/nvc0_graph.c -@@ -333,14 +333,6 @@ nvc0_graph_fini(struct drm_device *dev, int engine, bool suspend) +Index: linux-3.2.46/drivers/gpu/drm/nouveau/nvc0_graph.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/nouveau/nvc0_graph.c 2013-07-26 19:25:21.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/nouveau/nvc0_graph.c 2013-07-26 19:26:23.000000000 +0000 +@@ -333,14 +333,6 @@ return 0; } @@ -67911,7 +67820,7 @@ static void nvc0_graph_init_obj418880(struct drm_device *dev) { -@@ -875,19 +867,20 @@ nvc0_graph_create(struct drm_device *dev) +@@ -873,19 +865,20 @@ case 0xcf: /* 4/0/0/0, 3 */ priv->magic_not_rop_nr = 0x03; break; @@ -67935,11 +67844,11 @@ NVOBJ_CLASS(dev, 0x9097, GR); /* 3D */ if (fermi >= 0x9197) NVOBJ_CLASS(dev, 0x9197, GR); /* 3D (NVC1-) */ -diff --git a/drivers/gpu/drm/nouveau/nvc0_graph.fuc b/drivers/gpu/drm/nouveau/nvc0_graph.fuc -index 2a4b6dc..e6b2288 100644 ---- a/drivers/gpu/drm/nouveau/nvc0_graph.fuc -+++ b/drivers/gpu/drm/nouveau/nvc0_graph.fuc -@@ -71,9 +71,9 @@ queue_put: +Index: linux-3.2.46/drivers/gpu/drm/nouveau/nvc0_graph.fuc +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/nouveau/nvc0_graph.fuc 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/nouveau/nvc0_graph.fuc 2013-07-26 19:26:23.000000000 +0000 +@@ -71,9 +71,9 @@ ld b32 $r9 D[$r13 + 0x4] // PUT xor $r8 8 cmpu b32 $r8 $r9 @@ -67951,7 +67860,7 @@ ret // store cmd/data on queue -@@ -104,7 +104,7 @@ queue_get: +@@ -104,7 +104,7 @@ ld b32 $r8 D[$r13 + 0x0] // GET ld b32 $r9 D[$r13 + 0x4] // PUT cmpu b32 $r8 $r9 @@ -67960,7 +67869,7 @@ // fetch first cmd/data pair and $r9 $r8 7 shl b32 $r9 3 -@@ -135,9 +135,9 @@ nv_rd32: +@@ -135,9 +135,9 @@ nv_rd32_wait: iord $r12 I[$r11 + 0x000] xbit $r12 $r12 31 @@ -67972,7 +67881,7 @@ iord $r15 I[$r11 + 0x100] // MMIO_RDVAL ret -@@ -157,7 +157,7 @@ nv_wr32: +@@ -157,7 +157,7 @@ nv_wr32_wait: iord $r12 I[$r11 + 0x000] xbit $r12 $r12 31 @@ -67981,7 +67890,7 @@ ret // (re)set watchdog timer -@@ -193,7 +193,7 @@ $1: +@@ -193,7 +193,7 @@ shl b32 $r8 6 iord $r8 I[$r8 + 0x000] // DONE xbit $r8 $r8 $r10 @@ -67990,7 +67899,7 @@ trace_clr(T_WAIT) ret ') -@@ -216,7 +216,7 @@ mmctx_size: +@@ -216,7 +216,7 @@ add b32 $r9 $r8 add b32 $r14 4 cmpu b32 $r14 $r15 @@ -67999,7 +67908,7 @@ mov b32 $r15 $r9 ret -@@ -238,12 +238,12 @@ mmctx_xfer: +@@ -238,12 +238,12 @@ shl b32 $r8 6 clear b32 $r9 or $r11 $r11 @@ -68014,7 +67923,7 @@ iowr I[$r8 + 0x200] $r14 // MMCTX_MULTI_STRIDE iowr I[$r8 + 0x300] $r15 // MMCTX_MULTI_MASK bset $r9 1 // MULTI_EN -@@ -264,7 +264,7 @@ mmctx_xfer: +@@ -264,7 +264,7 @@ mmctx_wait_free: iord $r14 I[$r8 + 0x000] // MMCTX_CTRL and $r14 0x1f @@ -68023,7 +67932,7 @@ // queue up an entry ld b32 $r14 D[$r12] -@@ -272,19 +272,19 @@ mmctx_xfer: +@@ -272,19 +272,19 @@ iowr I[$r8 + 0x300] $r14 add b32 $r12 4 cmpu b32 $r12 $r13 @@ -68048,7 +67957,7 @@ mmctx_stop: xbit $r11 $r10 0 shl b32 $r11 16 // DIR -@@ -295,7 +295,7 @@ mmctx_xfer: +@@ -295,7 +295,7 @@ // wait for STOP_TRIGGER to clear iord $r11 I[$r8 + 0x000] // MMCTX_CTRL xbit $r11 $r11 18 @@ -68057,7 +67966,7 @@ mmctx_done: trace_clr(T_MMCTX) ret -@@ -305,7 +305,7 @@ mmctx_xfer: +@@ -305,7 +305,7 @@ strand_wait: push $r10 mov $r10 2 @@ -68066,7 +67975,7 @@ pop $r10 ret -@@ -316,7 +316,7 @@ strand_pre: +@@ -316,7 +316,7 @@ sethi $r8 0x20000 mov $r9 0xc iowr I[$r8] $r9 @@ -68075,7 +67984,7 @@ ret // unknown - call after issuing strand commands -@@ -326,7 +326,7 @@ strand_post: +@@ -326,7 +326,7 @@ sethi $r8 0x20000 mov $r9 0xd iowr I[$r8] $r9 @@ -68084,7 +67993,7 @@ ret // Selects strand set?! -@@ -341,11 +341,11 @@ strand_set: +@@ -341,11 +341,11 @@ iowr I[$r10 + 0x000] $r12 // 0x93c = 0xf mov $r12 0xb iowr I[$r11 + 0x000] $r12 // 0x928 = 0xb @@ -68098,7 +68007,7 @@ ret // Initialise strand context data -@@ -357,22 +357,22 @@ strand_set: +@@ -357,22 +357,22 @@ // strand_ctx_init: trace_set(T_STRINIT) @@ -68126,7 +68035,7 @@ // read the size of each strand, poke the context offset of // each into STRAND_{SAVE,LOAD}_SWBASE now, no need to worry -@@ -391,7 +391,7 @@ strand_ctx_init: +@@ -391,7 +391,7 @@ add b32 $r14 $r10 add b32 $r8 4 sub b32 $r9 1 @@ -68135,11 +68044,11 @@ shl b32 $r14 8 sub b32 $r15 $r14 $r15 -diff --git a/drivers/gpu/drm/nouveau/nvc0_graph.h b/drivers/gpu/drm/nouveau/nvc0_graph.h -index 636fe98..91d44ea 100644 ---- a/drivers/gpu/drm/nouveau/nvc0_graph.h -+++ b/drivers/gpu/drm/nouveau/nvc0_graph.h -@@ -87,6 +87,7 @@ nvc0_graph_class(struct drm_device *dev) +Index: linux-3.2.46/drivers/gpu/drm/nouveau/nvc0_graph.h +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/nouveau/nvc0_graph.h 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/nouveau/nvc0_graph.h 2013-07-26 19:26:23.000000000 +0000 +@@ -87,6 +87,7 @@ case 0xc1: return 0x9197; case 0xc8: @@ -68147,11 +68056,11 @@ return 0x9297; default: return 0; -diff --git a/drivers/gpu/drm/nouveau/nvc0_grctx.c b/drivers/gpu/drm/nouveau/nvc0_grctx.c -index 96b0b93d..de77842 100644 ---- a/drivers/gpu/drm/nouveau/nvc0_grctx.c -+++ b/drivers/gpu/drm/nouveau/nvc0_grctx.c -@@ -1268,6 +1268,17 @@ nvc0_grctx_generate_9039(struct drm_device *dev) +Index: linux-3.2.46/drivers/gpu/drm/nouveau/nvc0_grctx.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/nouveau/nvc0_grctx.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/nouveau/nvc0_grctx.c 2013-07-26 19:26:23.000000000 +0000 +@@ -1268,6 +1268,17 @@ static void nvc0_grctx_generate_90c0(struct drm_device *dev) { @@ -68169,7 +68078,7 @@ nv_mthd(dev, 0x90c0, 0x270c, 0x00000000); nv_mthd(dev, 0x90c0, 0x272c, 0x00000000); nv_mthd(dev, 0x90c0, 0x274c, 0x00000000); -@@ -1276,6 +1287,12 @@ nvc0_grctx_generate_90c0(struct drm_device *dev) +@@ -1276,6 +1287,12 @@ nv_mthd(dev, 0x90c0, 0x27ac, 0x00000000); nv_mthd(dev, 0x90c0, 0x27cc, 0x00000000); nv_mthd(dev, 0x90c0, 0x27ec, 0x00000000); @@ -68182,7 +68091,7 @@ nv_mthd(dev, 0x90c0, 0x030c, 0x00000001); nv_mthd(dev, 0x90c0, 0x1944, 0x00000000); nv_mthd(dev, 0x90c0, 0x0758, 0x00000100); -@@ -1471,14 +1488,20 @@ nvc0_grctx_generate_shaders(struct drm_device *dev) +@@ -1471,14 +1488,20 @@ { struct drm_nouveau_private *dev_priv = dev->dev_private; @@ -68208,7 +68117,7 @@ nv_wr32(dev, 0x405838, 0x00000000); nv_wr32(dev, 0x405854, 0x00000000); nv_wr32(dev, 0x405870, 0x00000001); -@@ -1509,7 +1532,10 @@ nvc0_grctx_generate_unk64xx(struct drm_device *dev) +@@ -1509,7 +1532,10 @@ nv_wr32(dev, 0x4064ac, 0x00003fff); nv_wr32(dev, 0x4064b4, 0x00000000); nv_wr32(dev, 0x4064b8, 0x00000000); @@ -68220,7 +68129,7 @@ nv_wr32(dev, 0x4064c0, 0x80140078); nv_wr32(dev, 0x4064c4, 0x0086ffff); } -@@ -1550,10 +1576,23 @@ nvc0_grctx_generate_rop(struct drm_device *dev) +@@ -1550,10 +1576,23 @@ /* ROPC_BROADCAST */ nv_wr32(dev, 0x408800, 0x02802a3c); nv_wr32(dev, 0x408804, 0x00000040); @@ -68248,7 +68157,7 @@ nv_wr32(dev, 0x40890c, 0x00000000); nv_wr32(dev, 0x408980, 0x0000011d); } -@@ -1572,7 +1611,7 @@ nvc0_grctx_generate_gpc(struct drm_device *dev) +@@ -1572,7 +1611,7 @@ nv_wr32(dev, 0x418408, 0x00000000); nv_wr32(dev, 0x41840c, 0x00001008); nv_wr32(dev, 0x418410, 0x0fff0fff); @@ -68257,7 +68166,7 @@ nv_wr32(dev, 0x418450, 0x00000000); nv_wr32(dev, 0x418454, 0x00000000); nv_wr32(dev, 0x418458, 0x00000000); -@@ -1587,14 +1626,17 @@ nvc0_grctx_generate_gpc(struct drm_device *dev) +@@ -1587,14 +1626,17 @@ nv_wr32(dev, 0x418700, 0x00000002); nv_wr32(dev, 0x418704, 0x00000080); nv_wr32(dev, 0x418708, 0x00000000); @@ -68278,7 +68187,7 @@ nv_wr32(dev, 0x4188d8, 0x00000008); nv_wr32(dev, 0x4188e0, 0x01000000); nv_wr32(dev, 0x4188e8, 0x00000000); -@@ -1602,7 +1644,12 @@ nvc0_grctx_generate_gpc(struct drm_device *dev) +@@ -1602,7 +1644,12 @@ nv_wr32(dev, 0x4188f0, 0x00000000); nv_wr32(dev, 0x4188f4, 0x00000000); nv_wr32(dev, 0x4188f8, 0x00000000); @@ -68292,7 +68201,7 @@ nv_wr32(dev, 0x41891c, 0x00ff00ff); nv_wr32(dev, 0x418924, 0x00000000); nv_wr32(dev, 0x418928, 0x00ffff00); -@@ -1616,7 +1663,7 @@ nvc0_grctx_generate_gpc(struct drm_device *dev) +@@ -1616,7 +1663,7 @@ nv_wr32(dev, 0x418a14 + (i * 0x20), 0x00000000); nv_wr32(dev, 0x418a18 + (i * 0x20), 0x00000000); } @@ -68301,7 +68210,7 @@ nv_wr32(dev, 0x418b08, 0x0a418820); nv_wr32(dev, 0x418b0c, 0x062080e6); nv_wr32(dev, 0x418b10, 0x020398a4); -@@ -1633,7 +1680,7 @@ nvc0_grctx_generate_gpc(struct drm_device *dev) +@@ -1633,7 +1680,7 @@ nv_wr32(dev, 0x418c24, 0x00000000); nv_wr32(dev, 0x418c28, 0x00000000); nv_wr32(dev, 0x418c2c, 0x00000000); @@ -68310,7 +68219,7 @@ nv_wr32(dev, 0x418c6c, 0x00000001); nv_wr32(dev, 0x418c80, 0x20200004); nv_wr32(dev, 0x418c8c, 0x00000001); -@@ -1653,7 +1700,10 @@ nvc0_grctx_generate_tp(struct drm_device *dev) +@@ -1653,7 +1700,10 @@ nv_wr32(dev, 0x419818, 0x00000000); nv_wr32(dev, 0x41983c, 0x00038bc7); nv_wr32(dev, 0x419848, 0x00000000); @@ -68322,7 +68231,7 @@ nv_wr32(dev, 0x419888, 0x00000000); nv_wr32(dev, 0x419a00, 0x000001f0); nv_wr32(dev, 0x419a04, 0x00000001); -@@ -1663,7 +1713,9 @@ nvc0_grctx_generate_tp(struct drm_device *dev) +@@ -1663,7 +1713,9 @@ nv_wr32(dev, 0x419a14, 0x00000200); nv_wr32(dev, 0x419a1c, 0x00000000); nv_wr32(dev, 0x419a20, 0x00000800); @@ -68333,7 +68242,7 @@ nv_wr32(dev, 0x00419ac4, 0x0007f440); nv_wr32(dev, 0x419b00, 0x0a418820); nv_wr32(dev, 0x419b04, 0x062080e6); -@@ -1672,21 +1724,33 @@ nvc0_grctx_generate_tp(struct drm_device *dev) +@@ -1672,21 +1724,33 @@ nv_wr32(dev, 0x419b10, 0x0a418820); nv_wr32(dev, 0x419b14, 0x000000e6); nv_wr32(dev, 0x419bd0, 0x00900103); @@ -68373,7 +68282,7 @@ nv_wr32(dev, 0x419d44, 0x02180218); nv_wr32(dev, 0x419e04, 0x00000000); nv_wr32(dev, 0x419e08, 0x00000000); -@@ -1986,6 +2050,10 @@ nvc0_grctx_generate(struct nouveau_channel *chan) +@@ -1986,6 +2050,10 @@ nv_icmd(dev, 0x00000215, 0x00000040); nv_icmd(dev, 0x00000216, 0x00000040); nv_icmd(dev, 0x00000217, 0x00000040); @@ -68384,7 +68293,7 @@ nv_icmd(dev, 0x00000218, 0x0000c080); nv_icmd(dev, 0x00000219, 0x0000c080); nv_icmd(dev, 0x0000021a, 0x0000c080); -@@ -1994,6 +2062,10 @@ nvc0_grctx_generate(struct nouveau_channel *chan) +@@ -1994,6 +2062,10 @@ nv_icmd(dev, 0x0000021d, 0x0000c080); nv_icmd(dev, 0x0000021e, 0x0000c080); nv_icmd(dev, 0x0000021f, 0x0000c080); @@ -68395,7 +68304,7 @@ nv_icmd(dev, 0x000000ad, 0x0000013e); nv_icmd(dev, 0x000000e1, 0x00000010); nv_icmd(dev, 0x00000290, 0x00000000); -@@ -2556,7 +2628,8 @@ nvc0_grctx_generate(struct nouveau_channel *chan) +@@ -2556,7 +2628,8 @@ nv_icmd(dev, 0x0000053f, 0xffff0000); nv_icmd(dev, 0x00000585, 0x0000003f); nv_icmd(dev, 0x00000576, 0x00000003); @@ -68405,7 +68314,7 @@ nv_icmd(dev, 0x0000057b, 0x00000059); nv_icmd(dev, 0x00000586, 0x00000040); nv_icmd(dev, 0x00000582, 0x00000080); -@@ -2658,6 +2731,8 @@ nvc0_grctx_generate(struct nouveau_channel *chan) +@@ -2658,6 +2731,8 @@ nv_icmd(dev, 0x00000957, 0x00000003); nv_icmd(dev, 0x0000095e, 0x20164010); nv_icmd(dev, 0x0000095f, 0x00000020); @@ -68414,10 +68323,10 @@ nv_icmd(dev, 0x00000683, 0x00000006); nv_icmd(dev, 0x00000685, 0x003fffff); nv_icmd(dev, 0x00000687, 0x00000c48); -diff --git a/drivers/gpu/drm/nouveau/nvc0_grgpc.fuc b/drivers/gpu/drm/nouveau/nvc0_grgpc.fuc -index 06f5e26..15272be 100644 ---- a/drivers/gpu/drm/nouveau/nvc0_grgpc.fuc -+++ b/drivers/gpu/drm/nouveau/nvc0_grgpc.fuc +Index: linux-3.2.46/drivers/gpu/drm/nouveau/nvc0_grgpc.fuc +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/nouveau/nvc0_grgpc.fuc 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/nouveau/nvc0_grgpc.fuc 2013-07-26 19:26:23.000000000 +0000 @@ -32,7 +32,7 @@ * - watchdog timer around ctx operations */ @@ -68427,7 +68336,7 @@ include(`nvc0_graph.fuc') gpc_id: .b32 0 gpc_mmio_list_head: .b32 0 -@@ -48,40 +48,45 @@ cmd_queue: queue_init +@@ -48,40 +48,45 @@ // chipset descriptions chipsets: .b8 0xc0 0 0 0 @@ -68501,7 +68410,7 @@ .b8 0 0 0 0 // GPC mmio lists -@@ -114,6 +119,35 @@ nvc0_gpc_mmio_tail: +@@ -114,6 +119,35 @@ mmctx_data(0x000c6c, 1); nvc1_gpc_mmio_tail: @@ -68537,7 +68446,7 @@ // TPC mmio lists nvc0_tpc_mmio_head: mmctx_data(0x000018, 1) -@@ -146,9 +180,34 @@ nvc3_tpc_mmio_tail: +@@ -146,9 +180,34 @@ mmctx_data(0x000544, 1) nvc1_tpc_mmio_tail: @@ -68574,7 +68483,7 @@ define(`include_code') include(`nvc0_graph.fuc') -@@ -160,10 +219,10 @@ error: +@@ -160,10 +219,10 @@ push $r14 mov $r14 -0x67ec // 0x9814 sethi $r14 0x400000 @@ -68587,7 +68496,7 @@ pop $r14 ret -@@ -190,7 +249,7 @@ init: +@@ -190,7 +249,7 @@ iowr I[$r1 + 0x000] $r2 // FIFO_ENABLE // setup i0 handler, and route all interrupts to it @@ -68596,7 +68505,7 @@ mov $iv0 $r1 mov $r1 0x400 iowr I[$r1 + 0x300] $r0 // INTR_DISPATCH -@@ -210,24 +269,24 @@ init: +@@ -210,24 +269,24 @@ and $r2 0x1f shl b32 $r3 $r2 sub b32 $r3 1 @@ -68627,7 +68536,7 @@ // unknown chipset ret -@@ -253,19 +312,19 @@ init: +@@ -253,19 +312,19 @@ clear b32 $r15 ld b16 $r14 D[$r1 + 4] ld b16 $r15 D[$r1 + 6] @@ -68654,7 +68563,7 @@ mulu $r14 $r15 add b32 $r2 $r14 add b32 $r3 $r14 -@@ -283,7 +342,7 @@ init: +@@ -283,7 +342,7 @@ // calculate size of strand context data mov b32 $r15 $r2 @@ -68663,7 +68572,7 @@ add b32 $r3 $r15 // save context size, and tell HUB we're done -@@ -301,13 +360,13 @@ init: +@@ -301,13 +360,13 @@ main: bset $flags $p0 sleep $p0 @@ -68681,7 +68590,7 @@ // fetch $flags and mask off $p1/$p2 mov $r1 $flags mov $r2 0x0006 -@@ -318,14 +377,14 @@ main: +@@ -318,14 +377,14 @@ or $r1 $r14 mov $flags $r1 // transfer context data @@ -68700,7 +68609,7 @@ // interrupt handler ih: -@@ -342,13 +401,13 @@ ih: +@@ -342,13 +401,13 @@ // incoming fifo command? iord $r10 I[$r0 + 0x200] // INTR and $r11 $r10 0x00000004 @@ -68717,7 +68626,7 @@ add b32 $r11 0x400 mov $r14 1 iowr I[$r11 + 0x000] $r14 // FIFO_ACK -@@ -374,11 +433,11 @@ ih: +@@ -374,11 +433,11 @@ // hub_barrier_done: mov $r15 1 @@ -68731,7 +68640,7 @@ ret // Disables various things, waits a bit, and re-enables them.. -@@ -395,7 +454,7 @@ ctx_redswitch: +@@ -395,7 +454,7 @@ mov $r15 8 ctx_redswitch_delay: sub b32 $r15 1 @@ -68740,7 +68649,7 @@ mov $r15 0xa20 iowr I[$r14] $r15 // GPC_RED_SWITCH = UNK11, ENABLE, POWER ret -@@ -413,8 +472,8 @@ ctx_xfer: +@@ -413,8 +472,8 @@ mov $r1 0xa04 shl b32 $r1 6 iowr I[$r1 + 0x000] $r15// MEM_BASE @@ -68751,7 +68660,7 @@ ctx_xfer_not_load: // strands -@@ -422,7 +481,7 @@ ctx_xfer: +@@ -422,7 +481,7 @@ sethi $r1 0x20000 mov $r2 0xc iowr I[$r1] $r2 // STRAND_CMD(0x3f) = 0x0c @@ -68760,7 +68669,7 @@ mov $r2 0x47fc sethi $r2 0x20000 iowr I[$r2] $r0 // STRAND_FIRST_GENE(0x3f) = 0x00 -@@ -435,46 +494,46 @@ ctx_xfer: +@@ -435,46 +494,46 @@ or $r10 2 // first mov $r11 0x0000 sethi $r11 0x500000 @@ -68821,11 +68730,11 @@ ret .align 256 -diff --git a/drivers/gpu/drm/nouveau/nvc0_grgpc.fuc.h b/drivers/gpu/drm/nouveau/nvc0_grgpc.fuc.h -index 6f82032..a988b8a 100644 ---- a/drivers/gpu/drm/nouveau/nvc0_grgpc.fuc.h -+++ b/drivers/gpu/drm/nouveau/nvc0_grgpc.fuc.h -@@ -25,26 +25,29 @@ uint32_t nvc0_grgpc_data[] = { +Index: linux-3.2.46/drivers/gpu/drm/nouveau/nvc0_grgpc.fuc.h +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/nouveau/nvc0_grgpc.fuc.h 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/nouveau/nvc0_grgpc.fuc.h 2013-07-26 19:26:23.000000000 +0000 +@@ -25,26 +25,29 @@ 0x00000000, 0x00000000, 0x000000c0, @@ -68869,7 +68778,7 @@ 0x00000000, 0x00000380, 0x14000400, -@@ -71,6 +74,32 @@ uint32_t nvc0_grgpc_data[] = { +@@ -71,6 +74,32 @@ 0x08001000, 0x00001014, 0x00000c6c, @@ -68902,7 +68811,7 @@ 0x00000018, 0x0000003c, 0x00000048, -@@ -96,6 +125,29 @@ uint32_t nvc0_grgpc_data[] = { +@@ -96,6 +125,29 @@ 0x000006e0, 0x000004bc, 0x00000544, @@ -68932,10 +68841,10 @@ }; uint32_t nvc0_grgpc_code[] = { -diff --git a/drivers/gpu/drm/nouveau/nvc0_grhub.fuc b/drivers/gpu/drm/nouveau/nvc0_grhub.fuc -index e4f8c7e..98acddb 100644 ---- a/drivers/gpu/drm/nouveau/nvc0_grhub.fuc -+++ b/drivers/gpu/drm/nouveau/nvc0_grhub.fuc +Index: linux-3.2.46/drivers/gpu/drm/nouveau/nvc0_grhub.fuc +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/nouveau/nvc0_grhub.fuc 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/nouveau/nvc0_grhub.fuc 2013-07-26 19:26:23.000000000 +0000 @@ -27,7 +27,7 @@ * m4 nvc0_grhub.fuc | envyas -a -w -m fuc -V nva3 -o nvc0_grhub.fuc.h */ @@ -68945,7 +68854,7 @@ include(`nvc0_graph.fuc') gpc_count: .b32 0 rop_count: .b32 0 -@@ -39,26 +39,29 @@ ctx_current: .b32 0 +@@ -39,26 +39,29 @@ chipsets: .b8 0xc0 0 0 0 @@ -68989,7 +68898,7 @@ .b8 0 0 0 0 nvc0_hub_mmio_head: -@@ -105,6 +108,48 @@ nvc0_hub_mmio_tail: +@@ -105,6 +108,48 @@ mmctx_data(0x4064c0, 2) nvc1_hub_mmio_tail: @@ -69038,7 +68947,7 @@ .align 256 chan_data: chan_mmio_count: .b32 0 -@@ -113,8 +158,8 @@ chan_mmio_address: .b32 0 +@@ -113,8 +158,8 @@ .align 256 xfer_data: .b32 0 @@ -69049,7 +68958,7 @@ define(`include_code') include(`nvc0_graph.fuc') -@@ -157,7 +202,7 @@ init: +@@ -157,7 +202,7 @@ iowr I[$r1 + 0x000] $r2 // FIFO_ENABLE // setup i0 handler, and route all interrupts to it @@ -69058,7 +68967,7 @@ mov $iv0 $r1 mov $r1 0x400 iowr I[$r1 + 0x300] $r0 // INTR_DISPATCH -@@ -201,11 +246,11 @@ init: +@@ -201,11 +246,11 @@ // fetch enabled GPC/ROP counts mov $r14 -0x69fc // 0x409604 sethi $r14 0x400000 @@ -69073,7 +68982,7 @@ // set BAR_REQMASK to GPC mask mov $r1 1 -@@ -220,14 +265,14 @@ init: +@@ -220,14 +265,14 @@ mov $r2 0x800 shl b32 $r2 6 iord $r2 I[$r2 + 0x000] // CC_SCRATCH[0] @@ -69091,7 +69000,7 @@ // unknown chipset ret -@@ -239,9 +284,9 @@ init: +@@ -239,9 +284,9 @@ ld b16 $r14 D[$r15 + 4] ld b16 $r15 D[$r15 + 6] sethi $r14 0 @@ -69104,7 +69013,7 @@ // set mmctx base addresses now so we don't have to do it later, // they don't (currently) ever change -@@ -260,7 +305,7 @@ init: +@@ -260,7 +305,7 @@ add b32 $r1 1 shl b32 $r1 8 mov b32 $r15 $r1 @@ -69113,7 +69022,7 @@ add b32 $r1 $r15 // initialise each GPC in sequence by passing in the offset of its -@@ -271,40 +316,40 @@ init: +@@ -271,40 +316,40 @@ // when it has completed, and return the size of its context data // in GPCn_CC_SCRATCH[1] // @@ -69164,7 +69073,7 @@ // save context size, and tell host we're ready mov $r2 0x800 -@@ -322,13 +367,13 @@ main: +@@ -322,13 +367,13 @@ // sleep until we have something to do bset $flags $p0 sleep $p0 @@ -69182,7 +69091,7 @@ trace_set(T_AUTO) mov $r1 0xb00 shl b32 $r1 6 -@@ -336,39 +381,39 @@ main: +@@ -336,39 +381,39 @@ iord $r1 I[$r1 + 0x000] // CHAN_CUR xbit $r3 $r1 31 @@ -69231,7 +69140,7 @@ // ack the context switch request chsw_done: -@@ -377,32 +422,32 @@ main: +@@ -377,32 +422,32 @@ mov $r2 1 iowr I[$r1 + 0x000] $r2 // 0x409b0c trace_clr(T_AUTO) @@ -69273,7 +69182,7 @@ main_done: mov $r1 0x820 -@@ -410,7 +455,7 @@ main: +@@ -410,7 +455,7 @@ clear b32 $r2 bset $r2 31 iowr I[$r1 + 0x000] $r2 // CC_SCRATCH[0] |= 0x80000000 @@ -69282,7 +69191,7 @@ // interrupt handler ih: -@@ -427,13 +472,13 @@ ih: +@@ -427,13 +472,13 @@ // incoming fifo command? iord $r10 I[$r0 + 0x200] // INTR and $r11 $r10 0x00000004 @@ -69299,7 +69208,7 @@ add b32 $r11 0x400 mov $r14 1 iowr I[$r11 + 0x000] $r14 // FIFO_ACK -@@ -441,18 +486,18 @@ ih: +@@ -441,18 +486,18 @@ // context switch request? ih_no_fifo: and $r11 $r10 0x00000100 @@ -69322,7 +69231,7 @@ mov $r10 0xc1c shl b32 $r10 6 iowr I[$r10] $r11 // INTR_UP_SET -@@ -478,11 +523,11 @@ ctx_4160s: +@@ -478,11 +523,11 @@ mov $r14 0x4160 sethi $r14 0x400000 mov $r15 1 @@ -69337,7 +69246,7 @@ ret // Without clearing again at end of xfer, some things cause PGRAPH -@@ -492,7 +537,7 @@ ctx_4160c: +@@ -492,7 +537,7 @@ mov $r14 0x4160 sethi $r14 0x400000 clear b32 $r15 @@ -69346,7 +69255,7 @@ ret // Again, not real sure -@@ -503,7 +548,7 @@ ctx_4170s: +@@ -503,7 +548,7 @@ mov $r14 0x4170 sethi $r14 0x400000 or $r15 0x10 @@ -69355,7 +69264,7 @@ ret // Waits for a ctx_4170s() call to complete -@@ -511,9 +556,9 @@ ctx_4170s: +@@ -511,9 +556,9 @@ ctx_4170w: mov $r14 0x4170 sethi $r14 0x400000 @@ -69367,7 +69276,7 @@ ret // Disables various things, waits a bit, and re-enables them.. -@@ -530,7 +575,7 @@ ctx_redswitch: +@@ -530,7 +575,7 @@ mov $r15 8 ctx_redswitch_delay: sub b32 $r15 1 @@ -69376,7 +69285,7 @@ mov $r15 0x770 iowr I[$r14] $r15 // HUB_RED_SWITCH = ENABLE_ALL, POWER_ALL ret -@@ -546,10 +591,10 @@ ctx_86c: +@@ -546,10 +591,10 @@ iowr I[$r14] $r15 // HUB(0x86c) = val mov $r14 -0x75ec sethi $r14 0x400000 @@ -69389,7 +69298,7 @@ ret // ctx_load - load's a channel's ctxctl data, and selects its vm -@@ -561,7 +606,7 @@ ctx_load: +@@ -561,7 +606,7 @@ // switch to channel, somewhat magic in parts.. mov $r10 12 // DONE_UNK12 @@ -69398,7 +69307,7 @@ mov $r1 0xa24 shl b32 $r1 6 iowr I[$r1 + 0x000] $r0 // 0x409a24 -@@ -576,7 +621,7 @@ ctx_load: +@@ -576,7 +621,7 @@ ctx_chan_wait_0: iord $r4 I[$r1 + 0x100] and $r4 0x1f @@ -69407,7 +69316,7 @@ iowr I[$r3 + 0x000] $r2 // CHAN_CUR // load channel header, fetch PGRAPH context pointer -@@ -595,19 +640,19 @@ ctx_load: +@@ -595,19 +640,19 @@ sethi $r2 0x80000000 iowr I[$r1 + 0x000] $r2 // MEM_TARGET = vram mov $r1 0x10 // chan + 0x0210 @@ -69431,7 +69340,7 @@ // set transfer base to start of context, and fetch context header trace_set(T_LCTXH) -@@ -618,7 +663,7 @@ ctx_load: +@@ -618,7 +663,7 @@ mov $r1 0xa20 shl b32 $r1 6 iowr I[$r1 + 0x000] $r2 // MEM_TARGET = vm @@ -69440,7 +69349,7 @@ sethi $r1 0x00060000 // 256 bytes xdld $r0 $r1 xdwait -@@ -635,10 +680,10 @@ ctx_load: +@@ -635,10 +680,10 @@ // In: $r2 channel address // ctx_chan: @@ -69454,7 +69363,7 @@ mov $r1 0xa10 shl b32 $r1 6 mov $r2 5 -@@ -646,8 +691,8 @@ ctx_chan: +@@ -646,8 +691,8 @@ ctx_chan_wait: iord $r2 I[$r1 + 0x000] or $r2 $r2 @@ -69465,7 +69374,7 @@ ret // Execute per-context state overrides list -@@ -661,7 +706,7 @@ ctx_chan: +@@ -661,7 +706,7 @@ // ctx_mmio_exec: // set transfer base to be the mmio list @@ -69474,7 +69383,7 @@ mov $r2 0xa04 shl b32 $r2 6 iowr I[$r2 + 0x000] $r3 // MEM_BASE -@@ -670,31 +715,31 @@ ctx_mmio_exec: +@@ -670,31 +715,31 @@ ctx_mmio_loop: // fetch next 256 bytes of mmio list if necessary and $r4 $r3 0xff @@ -69515,7 +69424,7 @@ sethi $r1 0x00060000 // 256 bytes xdst $r0 $r1 xdwait -@@ -709,46 +754,46 @@ ctx_mmio_exec: +@@ -709,46 +754,46 @@ // on load it means: "a save preceeded this load" // ctx_xfer: @@ -69576,7 +69485,7 @@ mov $r2 0x47fc sethi $r2 0x20000 iowr I[$r2] $r0 // STRAND_FIRST_GENE(0x3f) = 0x00 -@@ -760,22 +805,22 @@ ctx_xfer: +@@ -760,22 +805,22 @@ xbit $r10 $flags $p1 // direction or $r10 6 // first, last mov $r11 0 // base = 0 @@ -69606,7 +69515,7 @@ mov $r1 0xa10 shl b32 $r1 6 mov $r2 5 -@@ -783,27 +828,27 @@ ctx_xfer: +@@ -783,27 +828,27 @@ ctx_xfer_post_save_wait: iord $r2 I[$r1] or $r2 $r2 @@ -69646,11 +69555,11 @@ ctx_xfer_done: ret -diff --git a/drivers/gpu/drm/nouveau/nvc0_grhub.fuc.h b/drivers/gpu/drm/nouveau/nvc0_grhub.fuc.h -index 241d326..c5ed307 100644 ---- a/drivers/gpu/drm/nouveau/nvc0_grhub.fuc.h -+++ b/drivers/gpu/drm/nouveau/nvc0_grhub.fuc.h -@@ -23,19 +23,21 @@ uint32_t nvc0_grhub_data[] = { +Index: linux-3.2.46/drivers/gpu/drm/nouveau/nvc0_grhub.fuc.h +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/nouveau/nvc0_grhub.fuc.h 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/nouveau/nvc0_grhub.fuc.h 2013-07-26 19:26:23.000000000 +0000 +@@ -23,19 +23,21 @@ 0x00000000, 0x00000000, 0x000000c0, @@ -69679,7 +69588,7 @@ 0x00000000, 0x0417e91c, 0x04400204, -@@ -77,47 +79,45 @@ uint32_t nvc0_grhub_data[] = { +@@ -77,47 +79,45 @@ 0x0c408900, 0x00408980, 0x044064c0, @@ -69766,11 +69675,11 @@ 0x00000000, 0x00000000, 0x00000000, -diff --git a/drivers/gpu/drm/nouveau/nvc0_pm.c b/drivers/gpu/drm/nouveau/nvc0_pm.c -index 929aded..ce65f81 100644 ---- a/drivers/gpu/drm/nouveau/nvc0_pm.c -+++ b/drivers/gpu/drm/nouveau/nvc0_pm.c -@@ -153,3 +153,240 @@ nvc0_pm_clocks_get(struct drm_device *dev, struct nouveau_pm_level *perflvl) +Index: linux-3.2.46/drivers/gpu/drm/nouveau/nvc0_pm.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/nouveau/nvc0_pm.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/nouveau/nvc0_pm.c 2013-07-26 19:26:23.000000000 +0000 +@@ -153,3 +153,240 @@ perflvl->vdec = read_clk(dev, 0x0e); return 0; } @@ -70011,11 +69920,11 @@ + kfree(info); + return 0; +} -diff --git a/drivers/gpu/drm/nouveau/nvc0_vm.c b/drivers/gpu/drm/nouveau/nvc0_vm.c -index 9e35294..30d2bd5 100644 ---- a/drivers/gpu/drm/nouveau/nvc0_vm.c -+++ b/drivers/gpu/drm/nouveau/nvc0_vm.c -@@ -77,9 +77,11 @@ void +Index: linux-3.2.46/drivers/gpu/drm/nouveau/nvc0_vm.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/nouveau/nvc0_vm.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/nouveau/nvc0_vm.c 2013-07-26 19:26:23.000000000 +0000 +@@ -77,9 +77,11 @@ nvc0_vm_map_sg(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt, struct nouveau_mem *mem, u32 pte, u32 cnt, dma_addr_t *list) { @@ -70028,11 +69937,11 @@ nv_wo32(pgt, pte + 0, lower_32_bits(phys)); nv_wo32(pgt, pte + 4, upper_32_bits(phys)); pte += 8; -diff --git a/drivers/gpu/drm/nouveau/nvc0_vram.c b/drivers/gpu/drm/nouveau/nvc0_vram.c -index ce984d5..a7eef89 100644 ---- a/drivers/gpu/drm/nouveau/nvc0_vram.c -+++ b/drivers/gpu/drm/nouveau/nvc0_vram.c -@@ -106,31 +106,32 @@ nvc0_vram_init(struct drm_device *dev) +Index: linux-3.2.46/drivers/gpu/drm/nouveau/nvc0_vram.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/nouveau/nvc0_vram.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/nouveau/nvc0_vram.c 2013-07-26 19:26:23.000000000 +0000 +@@ -106,31 +106,32 @@ struct nouveau_vram_engine *vram = &dev_priv->engine.vram; const u32 rsvd_head = ( 256 * 1024) >> 12; /* vga memory */ const u32 rsvd_tail = (1024 * 1024) >> 12; /* vbios etc */ @@ -70058,11 +69967,6 @@ - if (psize == 0) - continue; - parts--; -- -- if (psize != bsize) { -- if (psize < bsize) -- bsize = psize; -- uniform = false; + for (part = 0; part < parts; part++) { + if (!(pmask & (1 << part))) { + u32 psize = nv_rd32(dev, 0x11020c + (part * 0x1000)); @@ -70071,7 +69975,11 @@ + bsize = psize; + uniform = false; + } -+ + +- if (psize != bsize) { +- if (psize < bsize) +- bsize = psize; +- uniform = false; + NV_DEBUG(dev, "%d: mem_amount 0x%08x\n", part, psize); + dev_priv->vram_size += (u64)psize << 20; } @@ -70081,10 +69989,10 @@ } /* if all controllers have the same amount attached, there's no holes */ -diff --git a/drivers/gpu/drm/nouveau/nvd0_display.c b/drivers/gpu/drm/nouveau/nvd0_display.c -index 3002d82..8a555fb 100644 ---- a/drivers/gpu/drm/nouveau/nvd0_display.c -+++ b/drivers/gpu/drm/nouveau/nvd0_display.c +Index: linux-3.2.46/drivers/gpu/drm/nouveau/nvd0_display.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/nouveau/nvd0_display.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/nouveau/nvd0_display.c 2013-07-26 19:26:23.000000000 +0000 @@ -35,12 +35,34 @@ #include "nouveau_fb.h" #include "nv50_display.h" @@ -70124,7 +70032,7 @@ struct tasklet_struct tasklet; u32 modeset; -@@ -53,6 +75,15 @@ nvd0_display(struct drm_device *dev) +@@ -53,6 +75,15 @@ return dev_priv->engine.display.priv; } @@ -70140,7 +70048,7 @@ static inline int evo_icmd(struct drm_device *dev, int id, u32 mthd, u32 data) { -@@ -84,6 +115,9 @@ evo_wait(struct drm_device *dev, int id, int nr) +@@ -84,6 +115,9 @@ put = 0; } @@ -70150,7 +70058,7 @@ return disp->evo[id].ptr + put; } -@@ -91,104 +125,372 @@ static void +@@ -91,104 +125,372 @@ evo_kick(u32 *push, struct drm_device *dev, int id) { struct nvd0_display *disp = nvd0_display(dev); @@ -70576,7 +70484,7 @@ } return 0; -@@ -201,7 +503,7 @@ nvd0_crtc_set_image(struct nouveau_crtc *nv_crtc, struct drm_framebuffer *fb, +@@ -201,7 +503,7 @@ struct nouveau_framebuffer *nvfb = nouveau_framebuffer(fb); u32 *push; @@ -70585,7 +70493,7 @@ if (push) { evo_mthd(push, 0x0460 + (nv_crtc->index * 0x300), 1); evo_data(push, nvfb->nvbo->bo.offset >> 8); -@@ -216,7 +518,7 @@ nvd0_crtc_set_image(struct nouveau_crtc *nv_crtc, struct drm_framebuffer *fb, +@@ -216,7 +518,7 @@ evo_mthd(push, 0x0080, 1); evo_data(push, 0x00000000); } @@ -70594,7 +70502,7 @@ } nv_crtc->fb.tile_flags = nvfb->r_dma; -@@ -227,7 +529,7 @@ static void +@@ -227,7 +529,7 @@ nvd0_crtc_cursor_show(struct nouveau_crtc *nv_crtc, bool show, bool update) { struct drm_device *dev = nv_crtc->base.dev; @@ -70603,7 +70511,7 @@ if (push) { if (show) { evo_mthd(push, 0x0480 + (nv_crtc->index * 0x300), 2); -@@ -247,7 +549,7 @@ nvd0_crtc_cursor_show(struct nouveau_crtc *nv_crtc, bool show, bool update) +@@ -247,7 +549,7 @@ evo_data(push, 0x00000000); } @@ -70612,7 +70520,7 @@ } } -@@ -262,7 +564,9 @@ nvd0_crtc_prepare(struct drm_crtc *crtc) +@@ -262,7 +564,9 @@ struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); u32 *push; @@ -70623,7 +70531,7 @@ if (push) { evo_mthd(push, 0x0474 + (nv_crtc->index * 0x300), 1); evo_data(push, 0x00000000); -@@ -270,7 +574,7 @@ nvd0_crtc_prepare(struct drm_crtc *crtc) +@@ -270,7 +574,7 @@ evo_data(push, 0x03000000); evo_mthd(push, 0x045c + (nv_crtc->index * 0x300), 1); evo_data(push, 0x00000000); @@ -70632,7 +70540,7 @@ } nvd0_crtc_cursor_show(nv_crtc, false, false); -@@ -282,7 +586,7 @@ nvd0_crtc_commit(struct drm_crtc *crtc) +@@ -282,7 +586,7 @@ struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); u32 *push; @@ -70641,7 +70549,7 @@ if (push) { evo_mthd(push, 0x0474 + (nv_crtc->index * 0x300), 1); evo_data(push, nv_crtc->fb.tile_flags); -@@ -295,10 +599,11 @@ nvd0_crtc_commit(struct drm_crtc *crtc) +@@ -295,10 +599,11 @@ evo_data(push, NvEvoVRAM); evo_mthd(push, 0x0430 + (nv_crtc->index * 0x300), 1); evo_data(push, 0xffffff00); @@ -70654,7 +70562,7 @@ } static bool -@@ -333,53 +638,61 @@ nvd0_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *umode, +@@ -333,53 +638,61 @@ { struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); struct nouveau_connector *nv_connector; @@ -70745,7 +70653,7 @@ nvd0_crtc_set_image(nv_crtc, crtc->fb, x, y, false); return 0; } -@@ -400,7 +713,9 @@ nvd0_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y, +@@ -400,7 +713,9 @@ if (ret) return ret; @@ -70755,7 +70663,7 @@ return 0; } -@@ -410,6 +725,7 @@ nvd0_crtc_mode_set_base_atomic(struct drm_crtc *crtc, +@@ -410,6 +725,7 @@ enum mode_set_atomic state) { struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); @@ -70763,7 +70671,7 @@ nvd0_crtc_set_image(nv_crtc, fb, x, y, true); return 0; } -@@ -472,10 +788,10 @@ static int +@@ -472,10 +788,10 @@ nvd0_crtc_cursor_move(struct drm_crtc *crtc, int x, int y) { struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); @@ -70777,7 +70685,7 @@ return 0; } -@@ -525,6 +841,7 @@ static const struct drm_crtc_funcs nvd0_crtc_func = { +@@ -525,6 +841,7 @@ .gamma_set = nvd0_crtc_gamma_set, .set_config = drm_crtc_helper_set_config, .destroy = nvd0_crtc_destroy, @@ -70785,7 +70693,7 @@ }; static void -@@ -640,11 +957,6 @@ nvd0_dac_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode, +@@ -640,11 +957,6 @@ } static void @@ -70797,7 +70705,7 @@ nvd0_dac_commit(struct drm_encoder *encoder) { } -@@ -655,16 +967,29 @@ nvd0_dac_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode, +@@ -655,16 +967,29 @@ { struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); @@ -70831,7 +70739,7 @@ } nv_encoder->crtc = encoder->crtc; -@@ -680,13 +1005,13 @@ nvd0_dac_disconnect(struct drm_encoder *encoder) +@@ -680,13 +1005,13 @@ if (nv_encoder->crtc) { nvd0_crtc_prepare(nv_encoder->crtc); @@ -70847,7 +70755,7 @@ } nv_encoder->crtc = NULL; -@@ -724,7 +1049,7 @@ nvd0_dac_destroy(struct drm_encoder *encoder) +@@ -724,7 +1049,7 @@ static const struct drm_encoder_helper_funcs nvd0_dac_hfunc = { .dpms = nvd0_dac_dpms, .mode_fixup = nvd0_dac_mode_fixup, @@ -70856,7 +70764,7 @@ .commit = nvd0_dac_commit, .mode_set = nvd0_dac_mode_set, .disable = nvd0_dac_disconnect, -@@ -760,8 +1085,253 @@ nvd0_dac_create(struct drm_connector *connector, struct dcb_entry *dcbe) +@@ -760,8 +1085,253 @@ } /****************************************************************************** @@ -71110,7 +71018,7 @@ static void nvd0_sor_dpms(struct drm_encoder *encoder, int mode) { -@@ -794,6 +1364,16 @@ nvd0_sor_dpms(struct drm_encoder *encoder, int mode) +@@ -794,6 +1364,16 @@ nv_mask(dev, 0x61c004 + (or * 0x0800), 0x80000001, dpms_ctrl); nv_wait(dev, 0x61c004 + (or * 0x0800), 0x80000000, 0x00000000); nv_wait(dev, 0x61c030 + (or * 0x0800), 0x10000000, 0x00000000); @@ -71127,7 +71035,7 @@ } static bool -@@ -816,8 +1396,37 @@ nvd0_sor_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode, +@@ -816,8 +1396,37 @@ } static void @@ -71165,7 +71073,7 @@ } static void -@@ -829,13 +1438,25 @@ static void +@@ -829,13 +1438,25 @@ nvd0_sor_mode_set(struct drm_encoder *encoder, struct drm_display_mode *umode, struct drm_display_mode *mode) { @@ -71193,7 +71101,7 @@ nv_connector = nouveau_encoder_connector_get(nv_encoder); switch (nv_encoder->dcb->type) { -@@ -852,6 +1473,8 @@ nvd0_sor_mode_set(struct drm_encoder *encoder, struct drm_display_mode *umode, +@@ -852,6 +1473,8 @@ or_config = (mode_ctrl & 0x00000f00) >> 8; if (mode->clock >= 165000) or_config |= 0x0100; @@ -71202,7 +71110,7 @@ break; case OUTPUT_LVDS: or_config = (mode_ctrl & 0x00000f00) >> 8; -@@ -861,7 +1484,7 @@ nvd0_sor_mode_set(struct drm_encoder *encoder, struct drm_display_mode *umode, +@@ -861,7 +1484,7 @@ if (bios->fp.if_is_24bit) or_config |= 0x0200; } else { @@ -71211,7 +71119,7 @@ if (((u8 *)nv_connector->edid)[121] == 2) or_config |= 0x0100; } else -@@ -882,6 +1505,22 @@ nvd0_sor_mode_set(struct drm_encoder *encoder, struct drm_display_mode *umode, +@@ -882,6 +1505,22 @@ } break; @@ -71234,7 +71142,7 @@ default: BUG_ON(1); break; -@@ -889,42 +1528,26 @@ nvd0_sor_mode_set(struct drm_encoder *encoder, struct drm_display_mode *umode, +@@ -889,42 +1528,26 @@ nvd0_sor_dpms(encoder, DRM_MODE_DPMS_ON); @@ -71288,7 +71196,7 @@ nvd0_sor_destroy(struct drm_encoder *encoder) { drm_encoder_cleanup(encoder); -@@ -976,17 +1599,19 @@ static struct dcb_entry * +@@ -976,17 +1599,19 @@ lookup_dcb(struct drm_device *dev, int id, u32 mc) { struct drm_nouveau_private *dev_priv = dev->dev_private; @@ -71313,7 +71221,7 @@ default: NV_ERROR(dev, "PDISP: unknown SOR mc 0x%08x\n", mc); return NULL; -@@ -997,7 +1622,8 @@ lookup_dcb(struct drm_device *dev, int id, u32 mc) +@@ -997,7 +1622,8 @@ for (i = 0; i < dev_priv->vbios.dcb.entries; i++) { struct dcb_entry *dcb = &dev_priv->vbios.dcb.entry[i]; @@ -71323,7 +71231,7 @@ return dcb; } -@@ -1048,7 +1674,9 @@ nvd0_display_unk2_handler(struct drm_device *dev, u32 crtc, u32 mask) +@@ -1048,7 +1674,9 @@ } pclk = nv_rd32(dev, 0x660450 + (crtc * 0x300)) / 1000; @@ -71334,7 +71242,7 @@ nv50_crtc_set_clock(dev, crtc, pclk); } -@@ -1072,6 +1700,7 @@ nvd0_display_unk2_handler(struct drm_device *dev, u32 crtc, u32 mask) +@@ -1072,6 +1700,7 @@ break; case OUTPUT_TMDS: case OUTPUT_LVDS: @@ -71342,7 +71250,7 @@ if (cfg & 0x00000100) tmp = 0x00000101; else -@@ -1122,7 +1751,7 @@ nvd0_display_bh(unsigned long data) +@@ -1122,7 +1751,7 @@ { struct drm_device *dev = (struct drm_device *)data; struct nvd0_display *disp = nvd0_display(dev); @@ -71351,7 +71259,7 @@ int i; if (drm_debug & (DRM_UT_DRIVER | DRM_UT_KMS)) { -@@ -1138,12 +1767,8 @@ nvd0_display_bh(unsigned long data) +@@ -1138,12 +1767,8 @@ } } @@ -71366,7 +71274,7 @@ if (disp->modeset & 0x00000001) nvd0_display_unk1_handler(dev, crtc, mask); -@@ -1158,6 +1783,13 @@ nvd0_display_intr(struct drm_device *dev) +@@ -1158,6 +1783,13 @@ { struct nvd0_display *disp = nvd0_display(dev); u32 intr = nv_rd32(dev, 0x610088); @@ -71380,7 +71288,7 @@ if (intr & 0x00000002) { u32 stat = nv_rd32(dev, 0x61009c); -@@ -1196,16 +1828,13 @@ nvd0_display_intr(struct drm_device *dev) +@@ -1196,16 +1828,13 @@ intr &= ~0x00100000; } @@ -71404,7 +71312,7 @@ } if (intr) -@@ -1215,38 +1844,29 @@ nvd0_display_intr(struct drm_device *dev) +@@ -1215,38 +1844,29 @@ /****************************************************************************** * Init *****************************************************************************/ @@ -71452,7 +71360,7 @@ if (nv_rd32(dev, 0x6100ac) & 0x00000100) { nv_wr32(dev, 0x6100ac, 0x00000100); -@@ -1271,7 +1891,7 @@ nvd0_display_init(struct drm_device *dev) +@@ -1271,7 +1891,7 @@ nv_wr32(dev, 0x6301c4 + (i * 0x800), sor); } @@ -71461,7 +71369,7 @@ u32 crtc0 = nv_rd32(dev, 0x616104 + (i * 0x800)); u32 crtc1 = nv_rd32(dev, 0x616108 + (i * 0x800)); u32 crtc2 = nv_rd32(dev, 0x61610c + (i * 0x800)); -@@ -1285,36 +1905,24 @@ nvd0_display_init(struct drm_device *dev) +@@ -1285,36 +1905,24 @@ nv_mask(dev, 0x6100b0, 0x00000307, 0x00000307); /* init master */ @@ -71475,21 +71383,10 @@ - NV_ERROR(dev, "PDISP: master 0x%08x\n", - nv_rd32(dev, 0x610490)); - return -EBUSY; -+ ret = evo_init_dma(dev, EVO_MASTER); -+ if (ret) -+ goto error; -+ -+ /* init flips + overlays + cursors */ -+ for (i = 0; i < dev->mode_config.num_crtc; i++) { -+ if ((ret = evo_init_dma(dev, EVO_FLIP(i))) || -+ (ret = evo_init_dma(dev, EVO_OVLY(i))) || -+ (ret = evo_init_pio(dev, EVO_OIMM(i))) || -+ (ret = evo_init_pio(dev, EVO_CURS(i)))) -+ goto error; - } +- } - nv_mask(dev, 0x610090, 0x00000001, 0x00000001); - nv_mask(dev, 0x6100a0, 0x00000001, 0x00000001); - +- - /* init cursors */ - for (i = 13; i <= 14; i++) { - nv_wr32(dev, 0x610490 + (i * 0x10), 0x00000001); @@ -71498,22 +71395,33 @@ - nv_rd32(dev, 0x610490 + (i * 0x10))); - return -EBUSY; - } -- ++ ret = evo_init_dma(dev, EVO_MASTER); ++ if (ret) ++ goto error; + - nv_mask(dev, 0x610090, 1 << i, 1 << i); - nv_mask(dev, 0x6100a0, 1 << i, 1 << i); -+ push = evo_wait(dev, EVO_MASTER, 32); -+ if (!push) { -+ ret = -EBUSY; -+ goto error; ++ /* init flips + overlays + cursors */ ++ for (i = 0; i < dev->mode_config.num_crtc; i++) { ++ if ((ret = evo_init_dma(dev, EVO_FLIP(i))) || ++ (ret = evo_init_dma(dev, EVO_OVLY(i))) || ++ (ret = evo_init_pio(dev, EVO_OIMM(i))) || ++ (ret = evo_init_pio(dev, EVO_CURS(i)))) ++ goto error; } -- + - push = evo_wait(dev, 0, 32); - if (!push) - return -EBUSY; ++ push = evo_wait(dev, EVO_MASTER, 32); ++ if (!push) { ++ ret = -EBUSY; ++ goto error; ++ } evo_mthd(push, 0x0088, 1); evo_data(push, NvEvoSync); evo_mthd(push, 0x0084, 1); -@@ -1323,9 +1931,12 @@ nvd0_display_init(struct drm_device *dev) +@@ -1323,9 +1931,12 @@ evo_data(push, 0x80000000); evo_mthd(push, 0x008c, 1); evo_data(push, 0x00000000); @@ -71528,7 +71436,7 @@ } void -@@ -1334,11 +1945,16 @@ nvd0_display_destroy(struct drm_device *dev) +@@ -1334,11 +1945,16 @@ struct drm_nouveau_private *dev_priv = dev->dev_private; struct nvd0_display *disp = nvd0_display(dev); struct pci_dev *pdev = dev->pdev; @@ -71547,7 +71455,7 @@ nouveau_irq_unregister(dev, 26); dev_priv->engine.display.priv = NULL; -@@ -1355,7 +1971,7 @@ nvd0_display_create(struct drm_device *dev) +@@ -1355,7 +1971,7 @@ struct pci_dev *pdev = dev->pdev; struct nvd0_display *disp; struct dcb_entry *dcbe; @@ -71556,7 +71464,7 @@ disp = kzalloc(sizeof(*disp), GFP_KERNEL); if (!disp) -@@ -1363,7 +1979,8 @@ nvd0_display_create(struct drm_device *dev) +@@ -1363,7 +1979,8 @@ dev_priv->engine.display.priv = disp; /* create crtc objects to represent the hw heads */ @@ -71566,7 +71474,7 @@ ret = nvd0_crtc_create(dev, i); if (ret) goto out; -@@ -1384,6 +2001,7 @@ nvd0_display_create(struct drm_device *dev) +@@ -1384,6 +2001,7 @@ switch (dcbe->type) { case OUTPUT_TMDS: case OUTPUT_LVDS: @@ -71574,7 +71482,7 @@ nvd0_sor_create(connector, dcbe); break; case OUTPUT_ANALOG: -@@ -1410,61 +2028,83 @@ nvd0_display_create(struct drm_device *dev) +@@ -1410,61 +2028,83 @@ tasklet_init(&disp->tasklet, nvd0_display_bh, (unsigned long)dev); nouveau_irq_register(dev, 26, nvd0_display_intr); @@ -71704,11 +71612,11 @@ out: if (ret) -diff --git a/drivers/gpu/drm/r128/r128_drv.c b/drivers/gpu/drm/r128/r128_drv.c -index 4c8796b..88718fa 100644 ---- a/drivers/gpu/drm/r128/r128_drv.c -+++ b/drivers/gpu/drm/r128/r128_drv.c -@@ -42,6 +42,20 @@ static struct pci_device_id pciidlist[] = { +Index: linux-3.2.46/drivers/gpu/drm/r128/r128_drv.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/r128/r128_drv.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/r128/r128_drv.c 2013-07-26 19:26:23.000000000 +0000 +@@ -42,6 +42,20 @@ r128_PCI_IDS }; @@ -71729,7 +71637,7 @@ static struct drm_driver driver = { .driver_features = DRIVER_USE_AGP | DRIVER_USE_MTRR | DRIVER_PCI_DMA | DRIVER_SG | -@@ -60,21 +74,7 @@ static struct drm_driver driver = { +@@ -60,21 +74,7 @@ .reclaim_buffers = drm_core_reclaim_buffers, .ioctls = r128_ioctls, .dma_ioctl = r128_cce_buffers, @@ -71752,7 +71660,7 @@ .name = DRIVER_NAME, .desc = DRIVER_DESC, .date = DRIVER_DATE, -@@ -85,6 +85,7 @@ static struct drm_driver driver = { +@@ -85,6 +85,7 @@ int r128_driver_load(struct drm_device *dev, unsigned long flags) { @@ -71760,11 +71668,11 @@ return drm_vblank_init(dev, 1); } -diff --git a/drivers/gpu/drm/radeon/Makefile b/drivers/gpu/drm/radeon/Makefile -index cf8b4bc..9d83729 100644 ---- a/drivers/gpu/drm/radeon/Makefile -+++ b/drivers/gpu/drm/radeon/Makefile -@@ -70,7 +70,8 @@ radeon-y += radeon_device.o radeon_asic.o radeon_kms.o \ +Index: linux-3.2.46/drivers/gpu/drm/radeon/Makefile +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/radeon/Makefile 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/radeon/Makefile 2013-07-26 19:26:23.000000000 +0000 +@@ -70,7 +70,8 @@ r200.o radeon_legacy_tv.o r600_cs.o r600_blit.o r600_blit_shaders.o \ r600_blit_kms.o radeon_pm.o atombios_dp.o r600_audio.o r600_hdmi.o \ evergreen.o evergreen_cs.o evergreen_blit_shaders.o evergreen_blit_kms.o \ @@ -71774,17 +71682,17 @@ radeon-$(CONFIG_COMPAT) += radeon_ioc32.o radeon-$(CONFIG_VGA_SWITCHEROO) += radeon_atpx_handler.o -@@ -78,4 +79,4 @@ radeon-$(CONFIG_ACPI) += radeon_acpi.o +@@ -78,4 +79,4 @@ obj-$(CONFIG_DRM_RADEON)+= radeon.o -CFLAGS_radeon_trace_points.o := -I$(src) \ No newline at end of file +CFLAGS_radeon_trace_points.o := -I$(src) -diff --git a/drivers/gpu/drm/radeon/ObjectID.h b/drivers/gpu/drm/radeon/ObjectID.h -index c61c3fe..ca4b038 100644 ---- a/drivers/gpu/drm/radeon/ObjectID.h -+++ b/drivers/gpu/drm/radeon/ObjectID.h +Index: linux-3.2.46/drivers/gpu/drm/radeon/ObjectID.h +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/radeon/ObjectID.h 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/radeon/ObjectID.h 2013-07-26 19:26:23.000000000 +0000 @@ -85,6 +85,7 @@ #define ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA 0x1F #define ENCODER_OBJECT_ID_INTERNAL_UNIPHY1 0x20 @@ -71804,11 +71712,11 @@ /****************************************************/ /* Connector Object ID definition - Shared with BIOS */ /****************************************************/ -diff --git a/drivers/gpu/drm/radeon/atom.c b/drivers/gpu/drm/radeon/atom.c -index d969f3c..43672b6 100644 ---- a/drivers/gpu/drm/radeon/atom.c -+++ b/drivers/gpu/drm/radeon/atom.c -@@ -665,6 +665,8 @@ static void atom_op_delay(atom_exec_context *ctx, int *ptr, int arg) +Index: linux-3.2.46/drivers/gpu/drm/radeon/atom.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/radeon/atom.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/radeon/atom.c 2013-07-26 19:26:23.000000000 +0000 +@@ -665,6 +665,8 @@ SDEBUG(" count: %d\n", count); if (arg == ATOM_UNIT_MICROSEC) udelay(count); @@ -71817,11 +71725,11 @@ else msleep(count); } -diff --git a/drivers/gpu/drm/radeon/atombios.h b/drivers/gpu/drm/radeon/atombios.h -index 4760466..4b04ba3 100644 ---- a/drivers/gpu/drm/radeon/atombios.h -+++ b/drivers/gpu/drm/radeon/atombios.h -@@ -7270,6 +7270,8 @@ typedef struct _ATOM_PPLIB_THERMALCONTROLLER +Index: linux-3.2.46/drivers/gpu/drm/radeon/atombios.h +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/radeon/atombios.h 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/radeon/atombios.h 2013-07-26 19:26:23.000000000 +0000 +@@ -7270,6 +7270,8 @@ #define ATOM_PP_THERMALCONTROLLER_EMC2103 13 /* 0x0D */ // Only fan control will be implemented, do NOT show this in PPGen. #define ATOM_PP_THERMALCONTROLLER_SUMO 14 /* 0x0E */ // Sumo type, used internally #define ATOM_PP_THERMALCONTROLLER_NISLANDS 15 @@ -71830,7 +71738,7 @@ // Thermal controller 'combo type' to use an external controller for Fan control and an internal controller for thermal. // We probably should reserve the bit 0x80 for this use. -@@ -7285,6 +7287,7 @@ typedef struct _ATOM_PPLIB_STATE +@@ -7285,6 +7287,7 @@ UCHAR ucClockStateIndices[1]; // variable-sized } ATOM_PPLIB_STATE; @@ -71838,7 +71746,7 @@ typedef struct _ATOM_PPLIB_FANTABLE { UCHAR ucFanTableFormat; // Change this if the table format changes or version changes so that the other fields are not the same. -@@ -7297,12 +7300,20 @@ typedef struct _ATOM_PPLIB_FANTABLE +@@ -7297,12 +7300,20 @@ USHORT usPWMHigh; // The PWM value at THigh. } ATOM_PPLIB_FANTABLE; @@ -71859,7 +71767,7 @@ } ATOM_PPLIB_EXTENDEDHEADER; //// ATOM_PPLIB_POWERPLAYTABLE::ulPlatformCaps -@@ -7325,6 +7336,7 @@ typedef struct _ATOM_PPLIB_EXTENDEDHEADER +@@ -7325,6 +7336,7 @@ #define ATOM_PP_PLATFORM_CAP_REGULATOR_HOT 0x00010000 // Enable the 'regulator hot' feature. #define ATOM_PP_PLATFORM_CAP_BACO 0x00020000 // Does the driver supports BACO state. @@ -71867,7 +71775,7 @@ typedef struct _ATOM_PPLIB_POWERPLAYTABLE { ATOM_COMMON_TABLE_HEADER sHeader; -@@ -7383,7 +7395,8 @@ typedef struct _ATOM_PPLIB_POWERPLAYTABLE4 +@@ -7383,7 +7395,8 @@ USHORT usVddciDependencyOnMCLKOffset; USHORT usVddcDependencyOnMCLKOffset; USHORT usMaxClockVoltageOnDCOffset; @@ -71877,7 +71785,7 @@ } ATOM_PPLIB_POWERPLAYTABLE4, *LPATOM_PPLIB_POWERPLAYTABLE4; typedef struct _ATOM_PPLIB_POWERPLAYTABLE5 -@@ -7393,8 +7406,9 @@ typedef struct _ATOM_PPLIB_POWERPLAYTABLE5 +@@ -7393,8 +7406,9 @@ ULONG ulNearTDPLimit; ULONG ulSQRampingThreshold; USHORT usCACLeakageTableOffset; // Points to ATOM_PPLIB_CAC_Leakage_Table @@ -71889,7 +71797,7 @@ } ATOM_PPLIB_POWERPLAYTABLE5, *LPATOM_PPLIB_POWERPLAYTABLE5; //// ATOM_PPLIB_NONCLOCK_INFO::usClassification -@@ -7423,6 +7437,7 @@ typedef struct _ATOM_PPLIB_POWERPLAYTABLE5 +@@ -7423,6 +7437,7 @@ //// ATOM_PPLIB_NONCLOCK_INFO::usClassification2 #define ATOM_PPLIB_CLASSIFICATION2_LIMITEDPOWERSOURCE_2 0x0001 #define ATOM_PPLIB_CLASSIFICATION2_ULV 0x0002 @@ -71897,7 +71805,7 @@ //// ATOM_PPLIB_NONCLOCK_INFO::ulCapsAndSettings #define ATOM_PPLIB_SINGLE_DISPLAY_ONLY 0x00000001 -@@ -7446,7 +7461,9 @@ typedef struct _ATOM_PPLIB_POWERPLAYTABLE5 +@@ -7446,7 +7461,9 @@ #define ATOM_PPLIB_SOFTWARE_DISABLE_LOADBALANCING 0x00001000 #define ATOM_PPLIB_SOFTWARE_ENABLE_SLEEP_FOR_TIMESTAMPS 0x00002000 @@ -71908,7 +71816,7 @@ #define ATOM_PPLIB_ENABLE_VARIBRIGHT 0x00008000 //memory related flags -@@ -7508,7 +7525,7 @@ typedef struct _ATOM_PPLIB_R600_CLOCK_INFO +@@ -7508,7 +7525,7 @@ #define ATOM_PPLIB_R600_FLAGS_UVDSAFE 2 #define ATOM_PPLIB_R600_FLAGS_BACKBIASENABLE 4 #define ATOM_PPLIB_R600_FLAGS_MEMORY_ODT_OFF 8 @@ -71917,7 +71825,7 @@ #define ATOM_PPLIB_R600_FLAGS_LOWPOWER 32 // On the RV770 use 'low power' setting (sequencer S0). typedef struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO -@@ -7527,6 +7544,24 @@ typedef struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO +@@ -7527,6 +7544,24 @@ } ATOM_PPLIB_EVERGREEN_CLOCK_INFO; @@ -71942,7 +71850,7 @@ typedef struct _ATOM_PPLIB_RS780_CLOCK_INFO { -@@ -7539,7 +7574,7 @@ typedef struct _ATOM_PPLIB_RS780_CLOCK_INFO +@@ -7539,7 +7574,7 @@ UCHAR ucPadding; // For proper alignment and size. USHORT usVDDC; // For the 780, use: None, Low, High, Variable UCHAR ucMaxHTLinkWidth; // From SBIOS - {2, 4, 8, 16} @@ -71951,7 +71859,7 @@ USHORT usHTLinkFreq; // See definition ATOM_PPLIB_RS780_HTLINKFREQ_xxx or in MHz(>=200). ULONG ulFlags; } ATOM_PPLIB_RS780_CLOCK_INFO; -@@ -7561,9 +7596,7 @@ typedef struct _ATOM_PPLIB_SUMO_CLOCK_INFO{ +@@ -7561,9 +7596,7 @@ USHORT usEngineClockLow; //clockfrequency & 0xFFFF. The unit is in 10khz UCHAR ucEngineClockHigh; //clockfrequency >> 16. UCHAR vddcIndex; //2-bit vddc index; @@ -71962,7 +71870,7 @@ //please initalize to 0 USHORT rsv1; //please initialize to 0s -@@ -7586,7 +7619,7 @@ typedef struct _ATOM_PPLIB_STATE_V2 +@@ -7586,7 +7619,7 @@ UCHAR clockInfoIndex[1]; } ATOM_PPLIB_STATE_V2; @@ -71971,7 +71879,7 @@ //how many states we have UCHAR ucNumEntries; -@@ -7594,18 +7627,17 @@ typedef struct StateArray{ +@@ -7594,18 +7627,17 @@ }StateArray; @@ -71994,7 +71902,7 @@ //how many non-clock levels we have. normally should be same as number of states UCHAR ucNumEntries; -@@ -7644,6 +7676,124 @@ typedef struct _ATOM_PPLIB_Clock_Voltage_Limit_Table +@@ -7644,6 +7676,124 @@ ATOM_PPLIB_Clock_Voltage_Limit_Record entries[1]; // Dynamically allocate entries. }ATOM_PPLIB_Clock_Voltage_Limit_Table; @@ -72119,11 +72027,11 @@ /**************************************************************************/ -diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c -index 038570a..ebbfbd2 100644 ---- a/drivers/gpu/drm/radeon/atombios_crtc.c -+++ b/drivers/gpu/drm/radeon/atombios_crtc.c -@@ -231,6 +231,22 @@ static void atombios_blank_crtc(struct drm_crtc *crtc, int state) +Index: linux-3.2.46/drivers/gpu/drm/radeon/atombios_crtc.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/radeon/atombios_crtc.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/radeon/atombios_crtc.c 2013-07-26 19:26:23.000000000 +0000 +@@ -231,6 +231,22 @@ atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); } @@ -72146,7 +72054,7 @@ void atombios_crtc_dpms(struct drm_crtc *crtc, int mode) { struct drm_device *dev = crtc->dev; -@@ -243,7 +259,7 @@ void atombios_crtc_dpms(struct drm_crtc *crtc, int mode) +@@ -243,7 +259,7 @@ /* adjust pm to dpms changes BEFORE enabling crtcs */ radeon_pm_compute_clocks(rdev); atombios_enable_crtc(crtc, ATOM_ENABLE); @@ -72155,7 +72063,7 @@ atombios_enable_crtc_memreq(crtc, ATOM_ENABLE); atombios_blank_crtc(crtc, ATOM_DISABLE); drm_vblank_post_modeset(dev, radeon_crtc->crtc_id); -@@ -255,7 +271,7 @@ void atombios_crtc_dpms(struct drm_crtc *crtc, int mode) +@@ -255,7 +271,7 @@ drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id); if (radeon_crtc->enabled) atombios_blank_crtc(crtc, ATOM_ENABLE); @@ -72164,7 +72072,7 @@ atombios_enable_crtc_memreq(crtc, ATOM_DISABLE); atombios_enable_crtc(crtc, ATOM_DISABLE); radeon_crtc->enabled = false; -@@ -355,15 +371,12 @@ static void atombios_crtc_set_timing(struct drm_crtc *crtc, +@@ -355,15 +371,12 @@ atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); } @@ -72182,7 +72090,7 @@ case ATOM_PPLL1: ss_cntl = RREG32(EVERGREEN_P1PLL_SS_CNTL); ss_cntl &= ~EVERGREEN_PxPLL_SS_EN; -@@ -379,7 +392,7 @@ static void atombios_disable_ss(struct drm_crtc *crtc) +@@ -379,7 +392,7 @@ return; } } else if (ASIC_IS_AVIVO(rdev)) { @@ -72191,7 +72099,7 @@ case ATOM_PPLL1: ss_cntl = RREG32(AVIVO_P1PLL_INT_SS_CNTL); ss_cntl &= ~1; -@@ -406,16 +419,31 @@ union atom_enable_ss { +@@ -406,16 +419,31 @@ ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3 v3; }; @@ -72226,7 +72134,7 @@ memset(&args, 0, sizeof(args)); if (ASIC_IS_DCE5(rdev)) { -@@ -441,7 +469,7 @@ static void atombios_crtc_program_ss(struct drm_crtc *crtc, +@@ -441,7 +469,7 @@ return; } args.v3.ucEnable = enable; @@ -72235,7 +72143,7 @@ args.v3.ucEnable = ATOM_DISABLE; } else if (ASIC_IS_DCE4(rdev)) { args.v2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage); -@@ -479,7 +507,7 @@ static void atombios_crtc_program_ss(struct drm_crtc *crtc, +@@ -479,7 +507,7 @@ } else if (ASIC_IS_AVIVO(rdev)) { if ((enable == ATOM_DISABLE) || (ss->percentage == 0) || (ss->type & ATOM_EXTERNAL_SS_MASK)) { @@ -72244,7 +72152,7 @@ return; } args.lvds_ss_2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage); -@@ -491,7 +519,7 @@ static void atombios_crtc_program_ss(struct drm_crtc *crtc, +@@ -491,7 +519,7 @@ } else { if ((enable == ATOM_DISABLE) || (ss->percentage == 0) || (ss->type & ATOM_EXTERNAL_SS_MASK)) { @@ -72253,7 +72161,7 @@ return; } args.lvds_ss.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage); -@@ -523,6 +551,7 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc, +@@ -523,6 +551,7 @@ int encoder_mode = 0; u32 dp_clock = mode->clock; int bpc = 8; @@ -72261,7 +72169,7 @@ /* reset the pll flags */ pll->flags = 0; -@@ -542,12 +571,7 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc, +@@ -542,12 +571,7 @@ if (rdev->family < CHIP_RV770) pll->flags |= RADEON_PLL_PREFER_MINM_OVER_MAXP; /* use frac fb div on APUs */ @@ -72275,7 +72183,7 @@ pll->flags |= RADEON_PLL_USE_FRAC_FB_DIV; } else { pll->flags |= RADEON_PLL_LEGACY; -@@ -562,9 +586,10 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc, +@@ -562,9 +586,10 @@ if (encoder->crtc == crtc) { radeon_encoder = to_radeon_encoder(encoder); connector = radeon_get_connector_for_encoder(encoder); @@ -72288,7 +72196,7 @@ if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) || (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)) { if (connector) { -@@ -660,7 +685,7 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc, +@@ -660,7 +685,7 @@ if (dig->coherent_mode) args.v3.sInput.ucDispPllConfig |= DISPPLL_CONFIG_COHERENT_MODE; @@ -72297,7 +72205,7 @@ args.v3.sInput.ucDispPllConfig |= DISPPLL_CONFIG_DUAL_LINK; } -@@ -710,11 +735,9 @@ union set_pixel_clock { +@@ -710,11 +735,9 @@ /* on DCE5, make sure the voltage is high enough to support the * required disp clk. */ @@ -72310,7 +72218,7 @@ u8 frev, crev; int index; union set_pixel_clock args; -@@ -742,7 +765,12 @@ static void atombios_crtc_set_dcpll(struct drm_crtc *crtc, +@@ -742,7 +765,12 @@ * SetPixelClock provides the dividers */ args.v6.ulDispEngClkFreq = cpu_to_le32(dispclk); @@ -72324,7 +72232,7 @@ break; default: DRM_ERROR("Unknown table version %d %d\n", frev, crev); -@@ -935,7 +963,9 @@ static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode +@@ -935,7 +963,9 @@ struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv; int dp_clock; @@ -72335,7 +72243,7 @@ switch (encoder_mode) { case ATOM_ENCODER_MODE_DP_MST: -@@ -1004,7 +1034,7 @@ static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode +@@ -1004,7 +1034,7 @@ radeon_compute_pll_legacy(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div, &ref_div, &post_div); @@ -72344,7 +72252,7 @@ atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id, encoder_mode, radeon_encoder->encoder_id, mode->clock, -@@ -1027,7 +1057,7 @@ static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode +@@ -1027,7 +1057,7 @@ ss.step = step_size; } @@ -72353,7 +72261,7 @@ } } -@@ -1044,6 +1074,7 @@ static int dce4_crtc_do_set_base(struct drm_crtc *crtc, +@@ -1044,6 +1074,7 @@ struct radeon_bo *rbo; uint64_t fb_location; uint32_t fb_format, fb_pitch_pixels, tiling_flags; @@ -72361,7 +72269,7 @@ u32 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_NONE); u32 tmp, viewport_w, viewport_h; int r; -@@ -1134,20 +1165,13 @@ static int dce4_crtc_do_set_base(struct drm_crtc *crtc, +@@ -1134,20 +1165,13 @@ break; } @@ -72388,7 +72296,7 @@ } else if (tiling_flags & RADEON_TILING_MICRO) fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1); -@@ -1192,7 +1216,7 @@ static int dce4_crtc_do_set_base(struct drm_crtc *crtc, +@@ -1192,7 +1216,7 @@ WREG32(EVERGREEN_GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width); WREG32(EVERGREEN_GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height); @@ -72397,7 +72305,7 @@ WREG32(EVERGREEN_GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels); WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 1); -@@ -1361,7 +1385,7 @@ static int avivo_crtc_do_set_base(struct drm_crtc *crtc, +@@ -1361,7 +1385,7 @@ WREG32(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width); WREG32(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height); @@ -72406,7 +72314,7 @@ WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels); WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1); -@@ -1463,7 +1487,36 @@ static int radeon_atom_pick_pll(struct drm_crtc *crtc) +@@ -1463,7 +1487,36 @@ struct drm_crtc *test_crtc; uint32_t pll_in_use = 0; @@ -72444,7 +72352,7 @@ list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) { if (test_encoder->crtc && (test_encoder->crtc == crtc)) { /* in DP mode, the DP ref clock can come from PPLL, DCPLL, or ext clock, -@@ -1478,6 +1531,8 @@ static int radeon_atom_pick_pll(struct drm_crtc *crtc) +@@ -1478,6 +1531,8 @@ if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_encoder))) { if (rdev->clock.dp_extclk) return ATOM_PPLL_INVALID; @@ -72453,7 +72361,7 @@ else if (ASIC_IS_DCE5(rdev)) return ATOM_DCPLL; } -@@ -1504,6 +1559,26 @@ static int radeon_atom_pick_pll(struct drm_crtc *crtc) +@@ -1504,6 +1559,26 @@ } @@ -72480,7 +72388,7 @@ int atombios_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *mode, struct drm_display_mode *adjusted_mode, -@@ -1525,19 +1600,6 @@ int atombios_crtc_mode_set(struct drm_crtc *crtc, +@@ -1525,19 +1600,6 @@ } } @@ -72500,7 +72408,7 @@ atombios_crtc_set_pll(crtc, adjusted_mode); if (ASIC_IS_DCE4(rdev)) -@@ -1571,18 +1633,28 @@ static bool atombios_crtc_mode_fixup(struct drm_crtc *crtc, +@@ -1571,18 +1633,28 @@ static void atombios_crtc_prepare(struct drm_crtc *crtc) { struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); @@ -72529,7 +72437,7 @@ } static void atombios_crtc_disable(struct drm_crtc *crtc) -@@ -1594,6 +1666,8 @@ static void atombios_crtc_disable(struct drm_crtc *crtc) +@@ -1594,6 +1666,8 @@ int i; atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); @@ -72538,7 +72446,7 @@ for (i = 0; i < rdev->num_crtc; i++) { if (rdev->mode_info.crtcs[i] && -@@ -1614,6 +1688,12 @@ static void atombios_crtc_disable(struct drm_crtc *crtc) +@@ -1614,6 +1688,12 @@ atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id, 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss); break; @@ -72551,11 +72459,11 @@ default: break; } -diff --git a/drivers/gpu/drm/radeon/atombios_dp.c b/drivers/gpu/drm/radeon/atombios_dp.c -index 3254d51..886b41f 100644 ---- a/drivers/gpu/drm/radeon/atombios_dp.c -+++ b/drivers/gpu/drm/radeon/atombios_dp.c -@@ -64,12 +64,12 @@ static int radeon_process_aux_ch(struct radeon_i2c_chan *chan, +Index: linux-3.2.46/drivers/gpu/drm/radeon/atombios_dp.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/radeon/atombios_dp.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/radeon/atombios_dp.c 2013-07-26 19:26:23.000000000 +0000 +@@ -64,12 +64,12 @@ memset(&args, 0, sizeof(args)); @@ -72571,7 +72479,7 @@ args.v1.ucDataOutLen = 0; args.v1.ucChannelID = chan->rec.i2c_id; args.v1.ucDelay = delay / 10; -@@ -406,10 +406,13 @@ static void dp_get_adjust_train(u8 link_status[DP_LINK_STATUS_SIZE], +@@ -406,10 +406,13 @@ /* get bpc from the EDID */ static int convert_bpc_to_bpp(int bpc) { @@ -72585,7 +72493,7 @@ } /* get the max pix clock supported by the link rate and lane num */ -@@ -746,7 +749,8 @@ static int radeon_dp_link_train_init(struct radeon_dp_link_train_info *dp_info) +@@ -746,7 +749,8 @@ /* set the lane count on the sink */ tmp = dp_info->dp_lane_count; @@ -72595,11 +72503,11 @@ tmp |= DP_LANE_COUNT_ENHANCED_FRAME_EN; radeon_write_dpcd_reg(dp_info->radeon_connector, DP_LANE_COUNT_SET, tmp); -diff --git a/drivers/gpu/drm/radeon/atombios_encoders.c b/drivers/gpu/drm/radeon/atombios_encoders.c -index f0dc04b..23e3ea6 100644 ---- a/drivers/gpu/drm/radeon/atombios_encoders.c -+++ b/drivers/gpu/drm/radeon/atombios_encoders.c -@@ -57,22 +57,6 @@ static inline bool radeon_encoder_is_digital(struct drm_encoder *encoder) +Index: linux-3.2.46/drivers/gpu/drm/radeon/atombios_encoders.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/radeon/atombios_encoders.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/radeon/atombios_encoders.c 2013-07-26 19:26:23.000000000 +0000 +@@ -57,22 +57,6 @@ } } @@ -72622,7 +72530,7 @@ static bool radeon_atom_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode, struct drm_display_mode *adjusted_mode) -@@ -257,7 +241,7 @@ atombios_dvo_setup(struct drm_encoder *encoder, int action) +@@ -257,7 +241,7 @@ /* R4xx, R5xx */ args.ext_tmds.sXTmdsEncoder.ucEnable = action; @@ -72631,7 +72539,7 @@ args.ext_tmds.sXTmdsEncoder.ucMisc |= PANEL_ENCODER_MISC_DUAL; args.ext_tmds.sXTmdsEncoder.ucMisc |= ATOM_PANEL_MISC_888RGB; -@@ -269,7 +253,7 @@ atombios_dvo_setup(struct drm_encoder *encoder, int action) +@@ -269,7 +253,7 @@ /* DFP1, CRT1, TV1 depending on the type of port */ args.dvo.sDVOEncoder.ucDeviceType = ATOM_DEVICE_DFP1_INDEX; @@ -72640,7 +72548,7 @@ args.dvo.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute |= PANEL_ENCODER_MISC_DUAL; break; case 3: -@@ -353,7 +337,7 @@ atombios_digital_setup(struct drm_encoder *encoder, int action) +@@ -353,7 +337,7 @@ } else { if (dig->linkb) args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB; @@ -72649,7 +72557,7 @@ args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL; /*if (pScrn->rgbBits == 8) */ args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB; -@@ -392,7 +376,7 @@ atombios_digital_setup(struct drm_encoder *encoder, int action) +@@ -392,7 +376,7 @@ } else { if (dig->linkb) args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB; @@ -72658,7 +72566,7 @@ args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL; } break; -@@ -413,8 +397,6 @@ int +@@ -413,8 +397,6 @@ atombios_get_encoder_mode(struct drm_encoder *encoder) { struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); @@ -72667,7 +72575,7 @@ struct drm_connector *connector; struct radeon_connector *radeon_connector; struct radeon_connector_atom_dig *dig_connector; -@@ -438,13 +420,10 @@ atombios_get_encoder_mode(struct drm_encoder *encoder) +@@ -438,13 +420,10 @@ switch (connector->connector_type) { case DRM_MODE_CONNECTOR_DVII: case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */ @@ -72685,7 +72593,7 @@ return ATOM_ENCODER_MODE_DVI; else return ATOM_ENCODER_MODE_CRT; -@@ -452,13 +431,10 @@ atombios_get_encoder_mode(struct drm_encoder *encoder) +@@ -452,13 +431,10 @@ case DRM_MODE_CONNECTOR_DVID: case DRM_MODE_CONNECTOR_HDMIA: default: @@ -72703,7 +72611,7 @@ return ATOM_ENCODER_MODE_DVI; break; case DRM_MODE_CONNECTOR_LVDS: -@@ -469,13 +445,10 @@ atombios_get_encoder_mode(struct drm_encoder *encoder) +@@ -469,13 +445,10 @@ if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) return ATOM_ENCODER_MODE_DP; @@ -72721,7 +72629,7 @@ return ATOM_ENCODER_MODE_DVI; break; case DRM_MODE_CONNECTOR_eDP: -@@ -510,7 +483,7 @@ atombios_get_encoder_mode(struct drm_encoder *encoder) +@@ -510,7 +483,7 @@ * - 2 DIG encoder blocks. * DIG1/2 can drive UNIPHY0/1/2 link A or link B * @@ -72730,7 +72638,7 @@ * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B). * Supports up to 6 digital outputs * - 6 DIG encoder blocks. -@@ -526,7 +499,11 @@ atombios_get_encoder_mode(struct drm_encoder *encoder) +@@ -526,7 +499,11 @@ * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B). * Supports up to 6 digital outputs * - 2 DIG encoder blocks. @@ -72742,7 +72650,7 @@ * * Routing * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links) -@@ -568,7 +545,7 @@ atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mo +@@ -568,7 +545,7 @@ dp_clock = dig_connector->dp_clock; dp_lane_count = dig_connector->dp_lane_count; hpd_id = radeon_connector->hpd.hpd; @@ -72751,7 +72659,7 @@ } /* no dig encoder assigned */ -@@ -602,7 +579,7 @@ atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mo +@@ -602,7 +579,7 @@ if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode)) args.v1.ucLaneNum = dp_lane_count; @@ -72760,7 +72668,7 @@ args.v1.ucLaneNum = 8; else args.v1.ucLaneNum = 4; -@@ -637,7 +614,7 @@ atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mo +@@ -637,7 +614,7 @@ if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode)) args.v3.ucLaneNum = dp_lane_count; @@ -72769,7 +72677,7 @@ args.v3.ucLaneNum = 8; else args.v3.ucLaneNum = 4; -@@ -677,7 +654,7 @@ atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mo +@@ -677,7 +654,7 @@ if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode)) args.v4.ucLaneNum = dp_lane_count; @@ -72778,7 +72686,7 @@ args.v4.ucLaneNum = 8; else args.v4.ucLaneNum = 4; -@@ -734,6 +711,7 @@ union dig_transmitter_control { +@@ -734,6 +711,7 @@ DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2; DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3; DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 v4; @@ -72786,7 +72694,7 @@ }; void -@@ -754,6 +732,7 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t +@@ -754,6 +732,7 @@ int connector_object_id = 0; int igp_lane_info = 0; int dig_encoder = dig->dig_encoder; @@ -72794,7 +72702,7 @@ if (action == ATOM_TRANSMITTER_ACTION_INIT) { connector = radeon_get_connector_for_encoder_init(encoder); -@@ -769,6 +748,7 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t +@@ -769,6 +748,7 @@ struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv; @@ -72802,7 +72710,7 @@ dp_clock = dig_connector->dp_clock; dp_lane_count = dig_connector->dp_lane_count; connector_object_id = -@@ -821,7 +801,7 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t +@@ -821,7 +801,7 @@ if (is_dp) args.v1.usPixelClock = cpu_to_le16(dp_clock / 10); @@ -72811,7 +72719,7 @@ args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); else args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); -@@ -836,7 +816,8 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t +@@ -836,7 +816,8 @@ if ((rdev->flags & RADEON_IS_IGP) && (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) { @@ -72821,7 +72729,7 @@ if (igp_lane_info & 0x1) args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3; else if (igp_lane_info & 0x2) -@@ -863,7 +844,7 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t +@@ -863,7 +844,7 @@ else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { if (dig->coherent_mode) args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT; @@ -72830,7 +72738,7 @@ args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK; } break; -@@ -878,7 +859,7 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t +@@ -878,7 +859,7 @@ if (is_dp) args.v2.usPixelClock = cpu_to_le16(dp_clock / 10); @@ -72839,7 +72747,7 @@ args.v2.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); else args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); -@@ -906,7 +887,7 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t +@@ -906,7 +887,7 @@ } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { if (dig->coherent_mode) args.v2.acConfig.fCoherentMode = 1; @@ -72848,7 +72756,7 @@ args.v2.acConfig.fDualLinkConnector = 1; } break; -@@ -921,7 +902,7 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t +@@ -921,7 +902,7 @@ if (is_dp) args.v3.usPixelClock = cpu_to_le16(dp_clock / 10); @@ -72857,7 +72765,7 @@ args.v3.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); else args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); -@@ -929,7 +910,7 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t +@@ -929,7 +910,7 @@ if (is_dp) args.v3.ucLaneNum = dp_lane_count; @@ -72866,7 +72774,7 @@ args.v3.ucLaneNum = 8; else args.v3.ucLaneNum = 4; -@@ -966,7 +947,7 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t +@@ -966,7 +947,7 @@ else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { if (dig->coherent_mode) args.v3.acConfig.fCoherentMode = 1; @@ -72875,7 +72783,7 @@ args.v3.acConfig.fDualLinkConnector = 1; } break; -@@ -981,7 +962,7 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t +@@ -981,7 +962,7 @@ if (is_dp) args.v4.usPixelClock = cpu_to_le16(dp_clock / 10); @@ -72884,7 +72792,7 @@ args.v4.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10); else args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); -@@ -989,7 +970,7 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t +@@ -989,7 +970,7 @@ if (is_dp) args.v4.ucLaneNum = dp_lane_count; @@ -72893,7 +72801,7 @@ args.v4.ucLaneNum = 8; else args.v4.ucLaneNum = 4; -@@ -1029,10 +1010,64 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t +@@ -1029,10 +1010,64 @@ else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { if (dig->coherent_mode) args.v4.acConfig.fCoherentMode = 1; @@ -72959,7 +72867,7 @@ default: DRM_ERROR("Unknown table version %d, %d\n", frev, crev); break; -@@ -1128,7 +1163,7 @@ atombios_external_encoder_setup(struct drm_encoder *encoder, +@@ -1128,7 +1163,7 @@ dp_lane_count = dig_connector->dp_lane_count; connector_object_id = (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; @@ -72968,7 +72876,7 @@ } memset(&args, 0, sizeof(args)); -@@ -1152,7 +1187,7 @@ atombios_external_encoder_setup(struct drm_encoder *encoder, +@@ -1152,7 +1187,7 @@ if (dp_clock == 270000) args.v1.sDigEncoder.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ; args.v1.sDigEncoder.ucLaneNum = dp_lane_count; @@ -72977,7 +72885,7 @@ args.v1.sDigEncoder.ucLaneNum = 8; else args.v1.sDigEncoder.ucLaneNum = 4; -@@ -1171,7 +1206,7 @@ atombios_external_encoder_setup(struct drm_encoder *encoder, +@@ -1171,7 +1206,7 @@ else if (dp_clock == 540000) args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ; args.v3.sExtEncoder.ucLaneNum = dp_lane_count; @@ -72986,7 +72894,7 @@ args.v3.sExtEncoder.ucLaneNum = 8; else args.v3.sExtEncoder.ucLaneNum = 4; -@@ -1369,7 +1404,7 @@ radeon_atom_encoder_dpms_dig(struct drm_encoder *encoder, int mode) +@@ -1369,7 +1404,7 @@ ATOM_ENCODER_CMD_SETUP_PANEL_MODE, dig->panel_mode); if (ext_encoder) { @@ -72995,7 +72903,7 @@ atombios_external_encoder_setup(encoder, ext_encoder, EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP); } -@@ -1444,7 +1479,7 @@ radeon_atom_encoder_dpms_ext(struct drm_encoder *encoder, +@@ -1444,7 +1479,7 @@ switch (mode) { case DRM_MODE_DPMS_ON: default: @@ -73004,7 +72912,7 @@ atombios_external_encoder_setup(encoder, ext_encoder, EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT); atombios_external_encoder_setup(encoder, ext_encoder, -@@ -1455,7 +1490,7 @@ radeon_atom_encoder_dpms_ext(struct drm_encoder *encoder, +@@ -1455,7 +1490,7 @@ case DRM_MODE_DPMS_STANDBY: case DRM_MODE_DPMS_SUSPEND: case DRM_MODE_DPMS_OFF: @@ -73013,7 +72921,7 @@ atombios_external_encoder_setup(encoder, ext_encoder, EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING); atombios_external_encoder_setup(encoder, ext_encoder, -@@ -1734,13 +1769,34 @@ static int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder) +@@ -1734,13 +1769,34 @@ struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); struct drm_encoder *test_encoder; @@ -73053,7 +72961,7 @@ /* ontario follows DCE4 */ if (rdev->family == CHIP_PALM) { if (dig->linkb) -@@ -1828,7 +1884,7 @@ radeon_atom_encoder_init(struct radeon_device *rdev) +@@ -1828,7 +1884,7 @@ break; } @@ -73062,11 +72970,10 @@ atombios_external_encoder_setup(encoder, ext_encoder, EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT); } -diff --git a/drivers/gpu/drm/radeon/atombios_i2c.c b/drivers/gpu/drm/radeon/atombios_i2c.c -new file mode 100644 -index 0000000..44d87b6 ---- /dev/null -+++ b/drivers/gpu/drm/radeon/atombios_i2c.c +Index: linux-3.2.46/drivers/gpu/drm/radeon/atombios_i2c.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/radeon/atombios_i2c.c 2013-07-26 19:26:23.000000000 +0000 @@ -0,0 +1,139 @@ +/* + * Copyright 2011 Advanced Micro Devices, Inc. @@ -73207,10 +73114,10 @@ + return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; +} + -diff --git a/drivers/gpu/drm/radeon/cayman_blit_shaders.c b/drivers/gpu/drm/radeon/cayman_blit_shaders.c -index 7b4eeb7..19a0114 100644 ---- a/drivers/gpu/drm/radeon/cayman_blit_shaders.c -+++ b/drivers/gpu/drm/radeon/cayman_blit_shaders.c +Index: linux-3.2.46/drivers/gpu/drm/radeon/cayman_blit_shaders.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/radeon/cayman_blit_shaders.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/radeon/cayman_blit_shaders.c 2013-07-26 19:26:23.000000000 +0000 @@ -24,6 +24,7 @@ * Alex Deucher */ @@ -73219,11 +73126,11 @@ #include #include -diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c -index 0495a50..6a8776e 100644 ---- a/drivers/gpu/drm/radeon/evergreen.c -+++ b/drivers/gpu/drm/radeon/evergreen.c -@@ -50,6 +50,39 @@ static const u32 crtc_offsets[6] = +Index: linux-3.2.46/drivers/gpu/drm/radeon/evergreen.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/radeon/evergreen.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/radeon/evergreen.c 2013-07-26 19:26:23.000000000 +0000 +@@ -50,6 +50,39 @@ static void evergreen_gpu_init(struct radeon_device *rdev); void evergreen_fini(struct radeon_device *rdev); void evergreen_pcie_gen2_enable(struct radeon_device *rdev); @@ -73263,7 +73170,7 @@ void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev) { -@@ -570,7 +603,7 @@ static u32 evergreen_line_buffer_adjust(struct radeon_device *rdev, +@@ -570,7 +603,7 @@ return 0; } @@ -73272,7 +73179,7 @@ { u32 tmp = RREG32(MC_SHARED_CHMAP); -@@ -1119,11 +1152,23 @@ void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *sav +@@ -1119,11 +1152,23 @@ crtc_enabled = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]) & EVERGREEN_CRTC_MASTER_EN; if (crtc_enabled) { save->crtc_enabled[i] = true; @@ -73301,7 +73208,7 @@ } /* wait for the next frame */ frame_count = radeon_get_vblank_counter(rdev, i); -@@ -1132,12 +1177,21 @@ void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *sav +@@ -1132,12 +1177,21 @@ break; udelay(1); } @@ -73324,7 +73231,7 @@ blackout = RREG32(MC_SHARED_BLACKOUT_CNTL); if ((blackout & BLACKOUT_MODE_MASK) != 1) { -@@ -1149,6 +1203,22 @@ void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *sav +@@ -1149,6 +1203,22 @@ } /* wait for the MC to settle */ udelay(100); @@ -73347,7 +73254,7 @@ } void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save) -@@ -1170,6 +1240,33 @@ void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *s +@@ -1170,6 +1240,33 @@ WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(rdev->mc.vram_start)); WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start); @@ -73381,7 +73288,7 @@ /* unblackout the MC */ tmp = RREG32(MC_SHARED_BLACKOUT_CNTL); tmp &= ~BLACKOUT_MODE_MASK; -@@ -1178,10 +1275,20 @@ void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *s +@@ -1178,10 +1275,20 @@ WREG32(BIF_FB_EN, FB_READ_EN | FB_WRITE_EN); for (i = 0; i < rdev->num_crtc; i++) { @@ -73406,7 +73313,7 @@ /* wait for the next frame */ frame_count = radeon_get_vblank_counter(rdev, i); for (j = 0; j < rdev->usec_timeout; j++) { -@@ -1241,7 +1348,10 @@ void evergreen_mc_program(struct radeon_device *rdev) +@@ -1241,7 +1348,10 @@ rdev->mc.vram_end >> 12); } WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12); @@ -73418,7 +73325,7 @@ tmp = RREG32(MC_FUS_VM_FB_OFFSET) & 0x000FFFFF; tmp |= ((rdev->mc.vram_end >> 20) & 0xF) << 24; tmp |= ((rdev->mc.vram_start >> 20) & 0xF) << 20; -@@ -1276,18 +1386,20 @@ void evergreen_mc_program(struct radeon_device *rdev) +@@ -1276,18 +1386,20 @@ */ void evergreen_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) { @@ -73445,7 +73352,7 @@ } -@@ -1325,71 +1437,73 @@ static int evergreen_cp_load_microcode(struct radeon_device *rdev) +@@ -1325,71 +1437,73 @@ static int evergreen_cp_start(struct radeon_device *rdev) { @@ -73523,16 +73430,17 @@ - radeon_ring_write(rdev, 0xffffffff); - radeon_ring_write(rdev, 0xffffffff); - radeon_ring_write(rdev, 0xffffffff); +- +- radeon_ring_write(rdev, 0xc0026900); +- radeon_ring_write(rdev, 0x00000316); +- radeon_ring_write(rdev, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */ +- radeon_ring_write(rdev, 0x00000010); /* */ + radeon_ring_write(ring, 0xc0036f00); + radeon_ring_write(ring, 0x00000bc4); + radeon_ring_write(ring, 0xffffffff); + radeon_ring_write(ring, 0xffffffff); + radeon_ring_write(ring, 0xffffffff); - -- radeon_ring_write(rdev, 0xc0026900); -- radeon_ring_write(rdev, 0x00000316); -- radeon_ring_write(rdev, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */ -- radeon_ring_write(rdev, 0x00000010); /* */ ++ + radeon_ring_write(ring, 0xc0026900); + radeon_ring_write(ring, 0x00000316); + radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */ @@ -73550,7 +73458,7 @@ u32 tmp; u32 rb_bufsz; int r; -@@ -1407,13 +1521,14 @@ int evergreen_cp_resume(struct radeon_device *rdev) +@@ -1407,13 +1521,14 @@ RREG32(GRBM_SOFT_RESET); /* Set ring buffer size */ @@ -73567,7 +73475,7 @@ /* Set the write pointer delay */ WREG32(CP_RB_WPTR_DELAY, 0); -@@ -1421,8 +1536,8 @@ int evergreen_cp_resume(struct radeon_device *rdev) +@@ -1421,8 +1536,8 @@ /* Initialize the ring buffer's read and write pointers */ WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA); WREG32(CP_RB_RPTR_WR, 0); @@ -73578,7 +73486,7 @@ /* set the wb address wether it's enabled or not */ WREG32(CP_RB_RPTR_ADDR, -@@ -1440,16 +1555,16 @@ int evergreen_cp_resume(struct radeon_device *rdev) +@@ -1440,16 +1555,16 @@ mdelay(1); WREG32(CP_RB_CNTL, tmp); @@ -73600,7 +73508,7 @@ return r; } return 0; -@@ -1742,7 +1857,7 @@ static void evergreen_gpu_init(struct radeon_device *rdev) +@@ -1742,7 +1857,7 @@ case CHIP_SUMO: rdev->config.evergreen.num_ses = 1; rdev->config.evergreen.max_pipes = 4; @@ -73609,7 +73517,7 @@ if (rdev->pdev->device == 0x9648) rdev->config.evergreen.max_simds = 3; else if ((rdev->pdev->device == 0x9647) || -@@ -1831,7 +1946,7 @@ static void evergreen_gpu_init(struct radeon_device *rdev) +@@ -1831,7 +1946,7 @@ break; case CHIP_CAICOS: rdev->config.evergreen.num_ses = 1; @@ -73618,7 +73526,7 @@ rdev->config.evergreen.max_tile_pipes = 2; rdev->config.evergreen.max_simds = 2; rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses; -@@ -1880,7 +1995,9 @@ static void evergreen_gpu_init(struct radeon_device *rdev) +@@ -1880,7 +1995,9 @@ mc_shared_chmap = RREG32(MC_SHARED_CHMAP); @@ -73629,7 +73537,7 @@ mc_arb_ramcfg = RREG32(FUS_MC_ARB_RAMCFG); else mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG); -@@ -2284,7 +2401,9 @@ int evergreen_mc_init(struct radeon_device *rdev) +@@ -2284,7 +2401,9 @@ /* Get VRAM informations */ rdev->mc.vram_is_ddr = true; @@ -73640,7 +73548,7 @@ tmp = RREG32(FUS_MC_ARB_RAMCFG); else tmp = RREG32(MC_ARB_RAMCFG); -@@ -2316,14 +2435,16 @@ int evergreen_mc_init(struct radeon_device *rdev) +@@ -2316,14 +2435,16 @@ rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0); rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0); /* Setup GPU memory space */ @@ -73661,7 +73569,7 @@ } rdev->mc.visible_vram_size = rdev->mc.aper_size; r700_vram_gtt_location(rdev, &rdev->mc); -@@ -2332,7 +2453,7 @@ int evergreen_mc_init(struct radeon_device *rdev) +@@ -2332,7 +2453,7 @@ return 0; } @@ -73670,7 +73578,7 @@ { u32 srbm_status; u32 grbm_status; -@@ -2345,19 +2466,19 @@ bool evergreen_gpu_is_lockup(struct radeon_device *rdev) +@@ -2345,19 +2466,19 @@ grbm_status_se0 = RREG32(GRBM_STATUS_SE0); grbm_status_se1 = RREG32(GRBM_STATUS_SE1); if (!(grbm_status & GUI_ACTIVE)) { @@ -73697,7 +73605,7 @@ } static int evergreen_gpu_soft_reset(struct radeon_device *rdev) -@@ -2449,7 +2570,13 @@ void evergreen_disable_interrupt_state(struct radeon_device *rdev) +@@ -2449,7 +2570,13 @@ { u32 tmp; @@ -73712,7 +73620,7 @@ WREG32(GRBM_INT_CNTL, 0); WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); -@@ -2473,7 +2600,9 @@ void evergreen_disable_interrupt_state(struct radeon_device *rdev) +@@ -2473,7 +2600,9 @@ WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); } @@ -73723,7 +73631,7 @@ WREG32(DACB_AUTODETECT_INT_CONTROL, 0); tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY; -@@ -2494,6 +2623,7 @@ void evergreen_disable_interrupt_state(struct radeon_device *rdev) +@@ -2494,6 +2623,7 @@ int evergreen_irq_set(struct radeon_device *rdev) { u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE; @@ -73731,7 +73639,7 @@ u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0; u32 hpd1, hpd2, hpd3, hpd4, hpd5, hpd6; u32 grbm_int_cntl = 0; -@@ -2518,11 +2648,28 @@ int evergreen_irq_set(struct radeon_device *rdev) +@@ -2518,11 +2648,28 @@ hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN; hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN; @@ -73764,7 +73672,7 @@ if (rdev->irq.crtc_vblank_int[0] || rdev->irq.pflip[0]) { DRM_DEBUG("evergreen_irq_set: vblank 0\n"); -@@ -2582,7 +2729,12 @@ int evergreen_irq_set(struct radeon_device *rdev) +@@ -2582,7 +2729,12 @@ grbm_int_cntl |= GUI_IDLE_INT_ENABLE; } @@ -73778,7 +73686,7 @@ WREG32(GRBM_INT_CNTL, grbm_int_cntl); WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1); -@@ -2997,11 +3149,24 @@ restart_ih: +@@ -2997,11 +3149,24 @@ case 177: /* CP_INT in IB1 */ case 178: /* CP_INT in IB2 */ DRM_DEBUG("IH: CP int: 0x%08x\n", src_data); @@ -73805,7 +73713,7 @@ break; case 233: /* GUI IDLE */ DRM_DEBUG("IH: GUI idle\n"); -@@ -3031,6 +3196,7 @@ restart_ih: +@@ -3031,6 +3196,7 @@ static int evergreen_startup(struct radeon_device *rdev) { @@ -73813,7 +73721,7 @@ int r; /* enable pcie gen2 link */ -@@ -3076,7 +3242,7 @@ static int evergreen_startup(struct radeon_device *rdev) +@@ -3076,7 +3242,7 @@ r = evergreen_blit_init(rdev); if (r) { r600_blit_fini(rdev); @@ -73822,7 +73730,7 @@ dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r); } -@@ -3085,6 +3251,12 @@ static int evergreen_startup(struct radeon_device *rdev) +@@ -3085,6 +3251,12 @@ if (r) return r; @@ -73835,7 +73743,7 @@ /* Enable IRQ */ r = r600_irq_init(rdev); if (r) { -@@ -3094,7 +3266,9 @@ static int evergreen_startup(struct radeon_device *rdev) +@@ -3094,7 +3266,9 @@ } evergreen_irq_set(rdev); @@ -73846,7 +73754,7 @@ if (r) return r; r = evergreen_cp_load_microcode(rdev); -@@ -3104,6 +3278,23 @@ static int evergreen_startup(struct radeon_device *rdev) +@@ -3104,6 +3278,23 @@ if (r) return r; @@ -73870,7 +73778,7 @@ return 0; } -@@ -3123,15 +3314,11 @@ int evergreen_resume(struct radeon_device *rdev) +@@ -3123,15 +3314,11 @@ /* post card */ atom_asic_init(rdev->mode_info.atom_context); @@ -73888,7 +73796,7 @@ return r; } -@@ -3141,13 +3328,17 @@ int evergreen_resume(struct radeon_device *rdev) +@@ -3141,13 +3328,17 @@ int evergreen_suspend(struct radeon_device *rdev) { @@ -73908,7 +73816,7 @@ return 0; } -@@ -3222,8 +3413,8 @@ int evergreen_init(struct radeon_device *rdev) +@@ -3222,8 +3413,8 @@ if (r) return r; @@ -73919,7 +73827,7 @@ rdev->ih.ring_obj = NULL; r600_ih_ring_init(rdev, 64 * 1024); -@@ -3232,29 +3423,24 @@ int evergreen_init(struct radeon_device *rdev) +@@ -3232,29 +3423,24 @@ if (r) return r; @@ -73956,7 +73864,7 @@ /* Don't start up if the MC ucode is missing on BTC parts. * The default clocks and voltages before the MC ucode -@@ -3272,15 +3458,17 @@ int evergreen_init(struct radeon_device *rdev) +@@ -3272,15 +3458,17 @@ void evergreen_fini(struct radeon_device *rdev) { @@ -73975,10 +73883,10 @@ radeon_fence_driver_fini(rdev); radeon_agp_fini(rdev); radeon_bo_fini(rdev); -diff --git a/drivers/gpu/drm/radeon/evergreen_blit_kms.c b/drivers/gpu/drm/radeon/evergreen_blit_kms.c -index 914e5af..222acd2 100644 ---- a/drivers/gpu/drm/radeon/evergreen_blit_kms.c -+++ b/drivers/gpu/drm/radeon/evergreen_blit_kms.c +Index: linux-3.2.46/drivers/gpu/drm/radeon/evergreen_blit_kms.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/radeon/evergreen_blit_kms.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/radeon/evergreen_blit_kms.c 2013-07-26 19:26:23.000000000 +0000 @@ -32,23 +32,14 @@ #include "evergreend.h" #include "evergreen_blit_shaders.h" @@ -74005,7 +73913,7 @@ u32 cb_color_info; int pitch, slice; -@@ -62,23 +53,23 @@ set_render_target(struct radeon_device *rdev, int format, +@@ -62,23 +53,23 @@ pitch = (w / 8) - 1; slice = ((w * h) / 64) - 1; @@ -74046,7 +73954,7 @@ } /* emits 5dw */ -@@ -87,6 +78,7 @@ cp_set_surface_sync(struct radeon_device *rdev, +@@ -87,6 +78,7 @@ u32 sync_type, u32 size, u64 mc_addr) { @@ -74054,7 +73962,7 @@ u32 cp_coher_size; if (size == 0xffffffff) -@@ -99,39 +91,40 @@ cp_set_surface_sync(struct radeon_device *rdev, +@@ -99,39 +91,40 @@ * to the RB directly. For IBs, the CP programs this as part of the * surface_sync packet. */ @@ -74114,7 +74022,7 @@ gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.vs_offset; cp_set_surface_sync(rdev, PACKET3_SH_ACTION_ENA, 512, gpu_addr); -@@ -141,6 +134,7 @@ set_shaders(struct radeon_device *rdev) +@@ -141,6 +134,7 @@ static void set_vtx_resource(struct radeon_device *rdev, u64 gpu_addr) { @@ -74122,7 +74030,7 @@ u32 sq_vtx_constant_word2, sq_vtx_constant_word3; /* high addr, stride */ -@@ -155,16 +149,16 @@ set_vtx_resource(struct radeon_device *rdev, u64 gpu_addr) +@@ -155,16 +149,16 @@ SQ_VTCX_SEL_Z(SQ_SEL_Z) | SQ_VTCX_SEL_W(SQ_SEL_W); @@ -74149,7 +74057,7 @@ if ((rdev->family == CHIP_CEDAR) || (rdev->family == CHIP_PALM) || -@@ -185,6 +179,7 @@ set_tex_resource(struct radeon_device *rdev, +@@ -185,6 +179,7 @@ int format, int w, int h, int pitch, u64 gpu_addr, u32 size) { @@ -74157,7 +74065,7 @@ u32 sq_tex_resource_word0, sq_tex_resource_word1; u32 sq_tex_resource_word4, sq_tex_resource_word7; -@@ -208,16 +203,16 @@ set_tex_resource(struct radeon_device *rdev, +@@ -208,16 +203,16 @@ cp_set_surface_sync(rdev, PACKET3_TC_ACTION_ENA, size, gpu_addr); @@ -74184,7 +74092,7 @@ } /* emits 12 */ -@@ -225,53 +220,55 @@ static void +@@ -225,53 +220,55 @@ set_scissors(struct radeon_device *rdev, int x1, int y1, int x2, int y2) { @@ -74204,25 +74112,27 @@ - radeon_ring_write(rdev, (PA_SC_SCREEN_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_START) >> 2); - radeon_ring_write(rdev, (x1 << 0) | (y1 << 16)); - radeon_ring_write(rdev, (x2 << 0) | (y2 << 16)); -+ radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); -+ radeon_ring_write(ring, (PA_SC_SCREEN_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_START) >> 2); -+ radeon_ring_write(ring, (x1 << 0) | (y1 << 16)); -+ radeon_ring_write(ring, (x2 << 0) | (y2 << 16)); - +- - radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); - radeon_ring_write(rdev, (PA_SC_GENERIC_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_START) >> 2); - radeon_ring_write(rdev, (x1 << 0) | (y1 << 16) | (1 << 31)); - radeon_ring_write(rdev, (x2 << 0) | (y2 << 16)); -+ radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); -+ radeon_ring_write(ring, (PA_SC_GENERIC_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_START) >> 2); -+ radeon_ring_write(ring, (x1 << 0) | (y1 << 16) | (1 << 31)); -+ radeon_ring_write(ring, (x2 << 0) | (y2 << 16)); - +- - radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); - radeon_ring_write(rdev, (PA_SC_WINDOW_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_START) >> 2); - radeon_ring_write(rdev, (x1 << 0) | (y1 << 16) | (1 << 31)); - radeon_ring_write(rdev, (x2 << 0) | (y2 << 16)); + radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); ++ radeon_ring_write(ring, (PA_SC_SCREEN_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_START) >> 2); ++ radeon_ring_write(ring, (x1 << 0) | (y1 << 16)); ++ radeon_ring_write(ring, (x2 << 0) | (y2 << 16)); ++ ++ radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); ++ radeon_ring_write(ring, (PA_SC_GENERIC_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_START) >> 2); ++ radeon_ring_write(ring, (x1 << 0) | (y1 << 16) | (1 << 31)); ++ radeon_ring_write(ring, (x2 << 0) | (y2 << 16)); ++ ++ radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); + radeon_ring_write(ring, (PA_SC_WINDOW_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_START) >> 2); + radeon_ring_write(ring, (x1 << 0) | (y1 << 16) | (1 << 31)); + radeon_ring_write(ring, (x2 << 0) | (y2 << 16)); @@ -74263,7 +74173,7 @@ } -@@ -279,6 +276,7 @@ draw_auto(struct radeon_device *rdev) +@@ -279,6 +276,7 @@ static void set_default_state(struct radeon_device *rdev) { @@ -74271,7 +74181,7 @@ u32 sq_config, sq_gpr_resource_mgmt_1, sq_gpr_resource_mgmt_2, sq_gpr_resource_mgmt_3; u32 sq_thread_resource_mgmt, sq_thread_resource_mgmt_2; u32 sq_stack_resource_mgmt_1, sq_stack_resource_mgmt_2, sq_stack_resource_mgmt_3; -@@ -292,8 +290,8 @@ set_default_state(struct radeon_device *rdev) +@@ -292,8 +290,8 @@ int dwords; /* set clear context state */ @@ -74282,7 +74192,7 @@ if (rdev->family < CHIP_CAYMAN) { switch (rdev->family) { -@@ -550,60 +548,60 @@ set_default_state(struct radeon_device *rdev) +@@ -550,60 +548,60 @@ NUM_LS_STACK_ENTRIES(num_ls_stack_entries)); /* disable dyn gprs */ @@ -74380,10 +74290,10 @@ } -diff --git a/drivers/gpu/drm/radeon/evergreen_blit_shaders.c b/drivers/gpu/drm/radeon/evergreen_blit_shaders.c -index 3a10399..f85c0af 100644 ---- a/drivers/gpu/drm/radeon/evergreen_blit_shaders.c -+++ b/drivers/gpu/drm/radeon/evergreen_blit_shaders.c +Index: linux-3.2.46/drivers/gpu/drm/radeon/evergreen_blit_shaders.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/radeon/evergreen_blit_shaders.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/radeon/evergreen_blit_shaders.c 2013-07-26 19:26:23.000000000 +0000 @@ -24,6 +24,7 @@ * Alex Deucher */ @@ -74392,10 +74302,10 @@ #include #include -diff --git a/drivers/gpu/drm/radeon/evergreen_cs.c b/drivers/gpu/drm/radeon/evergreen_cs.c -index cd4590a..2cbd369 100644 ---- a/drivers/gpu/drm/radeon/evergreen_cs.c -+++ b/drivers/gpu/drm/radeon/evergreen_cs.c +Index: linux-3.2.46/drivers/gpu/drm/radeon/evergreen_cs.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/radeon/evergreen_cs.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/radeon/evergreen_cs.c 2013-07-26 19:26:23.000000000 +0000 @@ -31,6 +31,9 @@ #include "evergreen_reg_safe.h" #include "cayman_reg_safe.h" @@ -74406,7 +74316,7 @@ static int evergreen_cs_packet_next_reloc(struct radeon_cs_parser *p, struct radeon_cs_reloc **cs_reloc); -@@ -40,42 +43,47 @@ struct evergreen_cs_track { +@@ -40,42 +43,47 @@ u32 npipes; u32 row_size; /* value we track */ @@ -74468,7 +74378,7 @@ }; static u32 evergreen_cs_get_aray_mode(u32 tiling_flags) -@@ -103,19 +111,6 @@ static u32 evergreen_cs_get_num_banks(u32 nbanks) +@@ -103,19 +111,6 @@ } } @@ -74488,7 +74398,7 @@ static void evergreen_cs_track_init(struct evergreen_cs_track *track) { int i; -@@ -128,50 +123,858 @@ static void evergreen_cs_track_init(struct evergreen_cs_track *track) +@@ -128,50 +123,858 @@ } for (i = 0; i < 12; i++) { @@ -75029,7 +74939,10 @@ + unsigned pitch, slice, mslice; + unsigned long offset; + int r; -+ + +- /* we don't support stream out buffer yet */ +- if (track->vgt_strmout_config || track->vgt_strmout_buffer_config) { +- dev_warn(p->dev, "this kernel doesn't support SMX output buffer\n"); + mslice = G_028008_SLICE_MAX(track->db_depth_view) + 1; + pitch = G_028058_PITCH_TILE_MAX(track->db_depth_size); + slice = track->db_depth_slice; @@ -75065,10 +74978,7 @@ + track->db_depth_slice, track->db_z_info); + return r; + } - -- /* we don't support stream out buffer yet */ -- if (track->vgt_strmout_config || track->vgt_strmout_buffer_config) { -- dev_warn(p->dev, "this kernel doesn't support SMX output buffer\n"); ++ + r = evergreen_surface_check(p, &surf, "depth"); + if (r) { + dev_warn(p->dev, "%s:%d depth invalid (0x%08x 0x%08x 0x%08x)\n", @@ -75106,10 +75016,9 @@ + __func__, __LINE__, surf.layer_size, + (unsigned long)track->db_z_write_offset << 8, mslice, + radeon_bo_size(track->db_z_write_bo)); - return -EINVAL; - } - -- /* XXX fill in */ ++ return -EINVAL; ++ } ++ + /* hyperz */ + if (G_028040_TILE_SURFACE_ENABLE(track->db_z_info)) { + r = evergreen_cs_track_validate_htile(p, surf.nbx, surf.nby); @@ -75177,9 +75086,10 @@ + default: + dev_warn(p->dev, "%s:%d texture invalid dimension %d\n", + __func__, __LINE__, dim); -+ return -EINVAL; -+ } -+ + return -EINVAL; + } + +- /* XXX fill in */ + r = evergreen_surface_value_conv_check(p, &surf, "texture"); + if (r) { + return r; @@ -75362,7 +75272,7 @@ return 0; } -@@ -503,6 +1306,7 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) +@@ -503,6 +1306,7 @@ break; case DB_DEPTH_CONTROL: track->db_depth_control = radeon_get_ib_value(p, idx); @@ -75370,7 +75280,7 @@ break; case CAYMAN_DB_EQAA: if (p->rdev->family < CHIP_CAYMAN) { -@@ -520,7 +1324,7 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) +@@ -520,7 +1324,7 @@ break; case DB_Z_INFO: track->db_z_info = radeon_get_ib_value(p, idx); @@ -75379,7 +75289,7 @@ r = evergreen_cs_packet_next_reloc(p, &reloc); if (r) { dev_warn(p->dev, "bad SET_CONTEXT_REG " -@@ -532,20 +1336,35 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) +@@ -532,20 +1336,35 @@ ib[idx] |= Z_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags)); track->db_z_info |= Z_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags)); if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) { @@ -75417,7 +75327,7 @@ break; case DB_Z_READ_BASE: r = evergreen_cs_packet_next_reloc(p, &reloc); -@@ -557,6 +1376,7 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) +@@ -557,6 +1376,7 @@ track->db_z_read_offset = radeon_get_ib_value(p, idx); ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); track->db_z_read_bo = reloc->robj; @@ -75425,7 +75335,7 @@ break; case DB_Z_WRITE_BASE: r = evergreen_cs_packet_next_reloc(p, &reloc); -@@ -568,6 +1388,7 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) +@@ -568,6 +1388,7 @@ track->db_z_write_offset = radeon_get_ib_value(p, idx); ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); track->db_z_write_bo = reloc->robj; @@ -75433,7 +75343,7 @@ break; case DB_STENCIL_READ_BASE: r = evergreen_cs_packet_next_reloc(p, &reloc); -@@ -579,6 +1400,7 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) +@@ -579,6 +1400,7 @@ track->db_s_read_offset = radeon_get_ib_value(p, idx); ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); track->db_s_read_bo = reloc->robj; @@ -75441,7 +75351,7 @@ break; case DB_STENCIL_WRITE_BASE: r = evergreen_cs_packet_next_reloc(p, &reloc); -@@ -590,18 +1412,56 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) +@@ -590,18 +1412,56 @@ track->db_s_write_offset = radeon_get_ib_value(p, idx); ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); track->db_s_write_bo = reloc->robj; @@ -75454,7 +75364,7 @@ case VGT_STRMOUT_BUFFER_CONFIG: track->vgt_strmout_buffer_config = radeon_get_ib_value(p, idx); + track->streamout_dirty = true; - break; ++ break; + case VGT_STRMOUT_BUFFER_BASE_0: + case VGT_STRMOUT_BUFFER_BASE_1: + case VGT_STRMOUT_BUFFER_BASE_2: @@ -75470,7 +75380,7 @@ + ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); + track->vgt_strmout_bo[tmp] = reloc->robj; + track->streamout_dirty = true; -+ break; + break; + case VGT_STRMOUT_BUFFER_SIZE_0: + case VGT_STRMOUT_BUFFER_SIZE_1: + case VGT_STRMOUT_BUFFER_SIZE_2: @@ -75498,7 +75408,7 @@ break; case PA_SC_AA_CONFIG: if (p->rdev->family >= CHIP_CAYMAN) { -@@ -631,6 +1491,7 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) +@@ -631,6 +1491,7 @@ case CB_COLOR7_VIEW: tmp = (reg - CB_COLOR0_VIEW) / 0x3c; track->cb_color_view[tmp] = radeon_get_ib_value(p, idx); @@ -75506,7 +75416,7 @@ break; case CB_COLOR8_VIEW: case CB_COLOR9_VIEW: -@@ -638,6 +1499,7 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) +@@ -638,6 +1499,7 @@ case CB_COLOR11_VIEW: tmp = ((reg - CB_COLOR8_VIEW) / 0x1c) + 8; track->cb_color_view[tmp] = radeon_get_ib_value(p, idx); @@ -75514,7 +75424,7 @@ break; case CB_COLOR0_INFO: case CB_COLOR1_INFO: -@@ -649,7 +1511,7 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) +@@ -649,7 +1511,7 @@ case CB_COLOR7_INFO: tmp = (reg - CB_COLOR0_INFO) / 0x3c; track->cb_color_info[tmp] = radeon_get_ib_value(p, idx); @@ -75523,7 +75433,7 @@ r = evergreen_cs_packet_next_reloc(p, &reloc); if (r) { dev_warn(p->dev, "bad SET_CONTEXT_REG " -@@ -659,6 +1521,7 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) +@@ -659,6 +1521,7 @@ ib[idx] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags)); track->cb_color_info[tmp] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags)); } @@ -75531,7 +75441,7 @@ break; case CB_COLOR8_INFO: case CB_COLOR9_INFO: -@@ -666,7 +1529,7 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) +@@ -666,7 +1529,7 @@ case CB_COLOR11_INFO: tmp = ((reg - CB_COLOR8_INFO) / 0x1c) + 8; track->cb_color_info[tmp] = radeon_get_ib_value(p, idx); @@ -75540,7 +75450,7 @@ r = evergreen_cs_packet_next_reloc(p, &reloc); if (r) { dev_warn(p->dev, "bad SET_CONTEXT_REG " -@@ -676,6 +1539,7 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) +@@ -676,6 +1539,7 @@ ib[idx] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags)); track->cb_color_info[tmp] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags)); } @@ -75548,7 +75458,7 @@ break; case CB_COLOR0_PITCH: case CB_COLOR1_PITCH: -@@ -687,7 +1551,7 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) +@@ -687,7 +1551,7 @@ case CB_COLOR7_PITCH: tmp = (reg - CB_COLOR0_PITCH) / 0x3c; track->cb_color_pitch[tmp] = radeon_get_ib_value(p, idx); @@ -75557,7 +75467,7 @@ break; case CB_COLOR8_PITCH: case CB_COLOR9_PITCH: -@@ -695,7 +1559,7 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) +@@ -695,7 +1559,7 @@ case CB_COLOR11_PITCH: tmp = ((reg - CB_COLOR8_PITCH) / 0x1c) + 8; track->cb_color_pitch[tmp] = radeon_get_ib_value(p, idx); @@ -75566,7 +75476,7 @@ break; case CB_COLOR0_SLICE: case CB_COLOR1_SLICE: -@@ -708,6 +1572,7 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) +@@ -708,6 +1572,7 @@ tmp = (reg - CB_COLOR0_SLICE) / 0x3c; track->cb_color_slice[tmp] = radeon_get_ib_value(p, idx); track->cb_color_slice_idx[tmp] = idx; @@ -75574,7 +75484,7 @@ break; case CB_COLOR8_SLICE: case CB_COLOR9_SLICE: -@@ -716,6 +1581,7 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) +@@ -716,6 +1581,7 @@ tmp = ((reg - CB_COLOR8_SLICE) / 0x1c) + 8; track->cb_color_slice[tmp] = radeon_get_ib_value(p, idx); track->cb_color_slice_idx[tmp] = idx; @@ -75582,7 +75492,7 @@ break; case CB_COLOR0_ATTRIB: case CB_COLOR1_ATTRIB: -@@ -725,6 +1591,30 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) +@@ -725,6 +1591,30 @@ case CB_COLOR5_ATTRIB: case CB_COLOR6_ATTRIB: case CB_COLOR7_ATTRIB: @@ -75613,27 +75523,14 @@ case CB_COLOR8_ATTRIB: case CB_COLOR9_ATTRIB: case CB_COLOR10_ATTRIB: -@@ -735,30 +1625,23 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) +@@ -735,30 +1625,23 @@ "0x%04X\n", reg); return -EINVAL; } - if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) { - ib[idx] |= CB_NUM_BANKS(evergreen_cs_get_num_banks(track->nbanks)); - ib[idx] |= CB_TILE_SPLIT(evergreen_cs_get_tile_split(track->row_size)); -+ if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { -+ if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) { -+ unsigned bankw, bankh, mtaspect, tile_split; -+ -+ evergreen_tiling_fields(reloc->lobj.tiling_flags, -+ &bankw, &bankh, &mtaspect, -+ &tile_split); -+ ib[idx] |= CB_NUM_BANKS(evergreen_cs_get_num_banks(track->nbanks)); -+ ib[idx] |= CB_TILE_SPLIT(tile_split) | -+ CB_BANK_WIDTH(bankw) | -+ CB_BANK_HEIGHT(bankh) | -+ CB_MACRO_TILE_ASPECT(mtaspect); -+ } - } +- } - break; - case CB_COLOR0_DIM: - case CB_COLOR1_DIM: @@ -75654,13 +75551,27 @@ - tmp = ((reg - CB_COLOR8_DIM) / 0x1c) + 8; - track->cb_color_dim[tmp] = radeon_get_ib_value(p, idx); - track->cb_color_dim_idx[tmp] = idx; ++ if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { ++ if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) { ++ unsigned bankw, bankh, mtaspect, tile_split; ++ ++ evergreen_tiling_fields(reloc->lobj.tiling_flags, ++ &bankw, &bankh, &mtaspect, ++ &tile_split); ++ ib[idx] |= CB_NUM_BANKS(evergreen_cs_get_num_banks(track->nbanks)); ++ ib[idx] |= CB_TILE_SPLIT(tile_split) | ++ CB_BANK_WIDTH(bankw) | ++ CB_BANK_HEIGHT(bankh) | ++ CB_MACRO_TILE_ASPECT(mtaspect); ++ } ++ } + tmp = ((reg - CB_COLOR8_ATTRIB) / 0x1c) + 8; + track->cb_color_attrib[tmp] = ib[idx]; + track->cb_dirty = true; break; case CB_COLOR0_FMASK: case CB_COLOR1_FMASK: -@@ -833,8 +1716,8 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) +@@ -833,8 +1716,8 @@ tmp = (reg - CB_COLOR0_BASE) / 0x3c; track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx); ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); @@ -75670,7 +75581,7 @@ break; case CB_COLOR8_BASE: case CB_COLOR9_BASE: -@@ -849,8 +1732,25 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) +@@ -849,8 +1732,25 @@ tmp = ((reg - CB_COLOR8_BASE) / 0x1c) + 8; track->cb_color_bo_offset[tmp] = radeon_get_ib_value(p, idx); ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); @@ -75697,7 +75608,7 @@ break; case CB_IMMED0_BASE: case CB_IMMED1_BASE: -@@ -864,7 +1764,6 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) +@@ -864,7 +1764,6 @@ case CB_IMMED9_BASE: case CB_IMMED10_BASE: case CB_IMMED11_BASE: @@ -75705,7 +75616,7 @@ case SQ_PGM_START_FS: case SQ_PGM_START_ES: case SQ_PGM_START_VS: -@@ -989,6 +1888,9 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) +@@ -989,6 +1888,9 @@ } ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); break; @@ -75715,7 +75626,7 @@ default: dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx); return -EINVAL; -@@ -996,22 +1898,30 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) +@@ -996,22 +1898,30 @@ return 0; } @@ -75761,7 +75672,7 @@ } static int evergreen_packet3_check(struct radeon_cs_parser *p, -@@ -1036,6 +1946,8 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p, +@@ -1036,6 +1946,8 @@ { int pred_op; int tmp; @@ -75770,7 +75681,7 @@ if (pkt->count != 1) { DRM_ERROR("bad SET PREDICATION\n"); return -EINVAL; -@@ -1059,8 +1971,12 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p, +@@ -1059,8 +1971,12 @@ return -EINVAL; } @@ -75785,7 +75696,7 @@ } break; case PACKET3_CONTEXT_CONTROL: -@@ -1088,6 +2004,9 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p, +@@ -1088,6 +2004,9 @@ } break; case PACKET3_INDEX_BASE: @@ -75795,7 +75706,7 @@ if (pkt->count != 1) { DRM_ERROR("bad INDEX_BASE\n"); return -EINVAL; -@@ -1097,15 +2016,24 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p, +@@ -1097,15 +2016,24 @@ DRM_ERROR("bad INDEX_BASE\n"); return -EINVAL; } @@ -75822,7 +75733,7 @@ if (pkt->count != 3) { DRM_ERROR("bad DRAW_INDEX\n"); return -EINVAL; -@@ -1115,15 +2043,25 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p, +@@ -1115,15 +2043,25 @@ DRM_ERROR("bad DRAW_INDEX\n"); return -EINVAL; } @@ -75850,7 +75761,7 @@ if (pkt->count != 4) { DRM_ERROR("bad DRAW_INDEX_2\n"); return -EINVAL; -@@ -1133,14 +2071,21 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p, +@@ -1133,14 +2071,21 @@ DRM_ERROR("bad DRAW_INDEX_2\n"); return -EINVAL; } @@ -75874,7 +75785,7 @@ case PACKET3_DRAW_INDEX_AUTO: if (pkt->count != 1) { DRM_ERROR("bad DRAW_INDEX_AUTO\n"); -@@ -1231,13 +2176,20 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p, +@@ -1231,13 +2176,20 @@ } /* bit 4 is reg (0) or mem (1) */ if (idx_value & 0x10) { @@ -75897,7 +75808,7 @@ } break; case PACKET3_SURFACE_SYNC: -@@ -1262,16 +2214,25 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p, +@@ -1262,16 +2214,25 @@ return -EINVAL; } if (pkt->count) { @@ -75925,7 +75836,7 @@ if (pkt->count != 4) { DRM_ERROR("bad EVENT_WRITE_EOP\n"); return -EINVAL; -@@ -1281,10 +2242,19 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p, +@@ -1281,10 +2242,19 @@ DRM_ERROR("bad EVENT_WRITE_EOP\n"); return -EINVAL; } @@ -75947,7 +75858,7 @@ if (pkt->count != 3) { DRM_ERROR("bad EVENT_WRITE_EOS\n"); return -EINVAL; -@@ -1294,9 +2264,15 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p, +@@ -1294,9 +2264,15 @@ DRM_ERROR("bad EVENT_WRITE_EOS\n"); return -EINVAL; } @@ -75965,7 +75876,7 @@ case PACKET3_SET_CONFIG_REG: start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_START; end_reg = 4 * pkt->count + start_reg - 4; -@@ -1344,6 +2320,7 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p, +@@ -1344,6 +2320,7 @@ } for (i = 0; i < (pkt->count / 8); i++) { struct radeon_bo *texture, *mipmap; @@ -75973,7 +75884,7 @@ u32 size, offset; switch (G__SQ_CONSTANT_TYPE(radeon_get_ib_value(p, idx+1+(i*8)+7))) { -@@ -1354,32 +2331,42 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p, +@@ -1354,32 +2331,42 @@ DRM_ERROR("bad SET_RESOURCE (tex)\n"); return -EINVAL; } @@ -76023,7 +75934,7 @@ /* vtx base */ r = evergreen_cs_packet_next_reloc(p, &reloc); if (r) { -@@ -1391,11 +2378,15 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p, +@@ -1391,11 +2378,15 @@ if (p->rdev && (size + offset) > radeon_bo_size(reloc->robj)) { /* force size to size of the buffer */ dev_warn(p->dev, "vbo resource seems too big for the bo\n"); @@ -76042,7 +75953,7 @@ case SQ_TEX_VTX_INVALID_TEXTURE: case SQ_TEX_VTX_INVALID_BUFFER: default: -@@ -1451,6 +2442,104 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p, +@@ -1451,6 +2442,104 @@ return -EINVAL; } break; @@ -76147,7 +76058,7 @@ case PACKET3_NOP: break; default: -@@ -1572,3 +2661,247 @@ int evergreen_cs_parse(struct radeon_cs_parser *p) +@@ -1572,3 +2661,247 @@ return 0; } @@ -76395,10 +76306,10 @@ + + return ret; +} -diff --git a/drivers/gpu/drm/radeon/evergreen_reg.h b/drivers/gpu/drm/radeon/evergreen_reg.h -index e022776b..e534e5d 100644 ---- a/drivers/gpu/drm/radeon/evergreen_reg.h -+++ b/drivers/gpu/drm/radeon/evergreen_reg.h +Index: linux-3.2.46/drivers/gpu/drm/radeon/evergreen_reg.h +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/radeon/evergreen_reg.h 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/radeon/evergreen_reg.h 2013-07-26 19:26:23.000000000 +0000 @@ -35,6 +35,14 @@ #define EVERGREEN_P1PLL_SS_CNTL 0x414 #define EVERGREEN_P2PLL_SS_CNTL 0x454 @@ -76432,10 +76343,10 @@ +#define EVERGREEN_HDMI_CONFIG_OFFSET 0xf0 + #endif -diff --git a/drivers/gpu/drm/radeon/evergreend.h b/drivers/gpu/drm/radeon/evergreend.h -index fe44a95..81e744f 100644 ---- a/drivers/gpu/drm/radeon/evergreend.h -+++ b/drivers/gpu/drm/radeon/evergreend.h +Index: linux-3.2.46/drivers/gpu/drm/radeon/evergreend.h +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/radeon/evergreend.h 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/radeon/evergreend.h 2013-07-26 19:26:23.000000000 +0000 @@ -81,6 +81,11 @@ #define FB_READ_EN (1 << 0) #define FB_WRITE_EN (1 << 1) @@ -76505,11 +76416,10 @@ #define PA_SC_SCREEN_SCISSOR_TL 0x28030 #define PA_SC_GENERIC_SCISSOR_TL 0x28240 #define PA_SC_WINDOW_SCISSOR_TL 0x28204 --#define VGT_PRIMITIVE_TYPE 0x8958 - -+#define VGT_PRIMITIVE_TYPE 0x8958 -+#define VGT_INDEX_TYPE 0x895C + + #define VGT_PRIMITIVE_TYPE 0x8958 ++#define VGT_INDEX_TYPE 0x895C + +#define VGT_NUM_INDICES 0x8970 + +#define VGT_COMPUTE_DIM_X 0x8990 @@ -77009,11 +76919,11 @@ #define CAYMAN_DB_EQAA 0x28804 #define CAYMAN_DB_DEPTH_INFO 0x2803C #define CAYMAN_PA_SC_AA_CONFIG 0x28BE0 -diff --git a/drivers/gpu/drm/radeon/ni.c b/drivers/gpu/drm/radeon/ni.c -index 636255b..d706da8 100644 ---- a/drivers/gpu/drm/radeon/ni.c -+++ b/drivers/gpu/drm/radeon/ni.c -@@ -42,6 +42,8 @@ extern void evergreen_irq_suspend(struct radeon_device *rdev); +Index: linux-3.2.46/drivers/gpu/drm/radeon/ni.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/radeon/ni.c 2013-07-26 19:25:21.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/radeon/ni.c 2013-07-26 19:26:23.000000000 +0000 +@@ -42,6 +42,8 @@ extern int evergreen_mc_init(struct radeon_device *rdev); extern void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev); extern void evergreen_pcie_gen2_enable(struct radeon_device *rdev); @@ -77022,7 +76932,7 @@ #define EVERGREEN_PFP_UCODE_SIZE 1120 #define EVERGREEN_PM4_UCODE_SIZE 1376 -@@ -53,6 +55,8 @@ extern void evergreen_pcie_gen2_enable(struct radeon_device *rdev); +@@ -53,6 +55,8 @@ #define CAYMAN_RLC_UCODE_SIZE 1024 #define CAYMAN_MC_UCODE_SIZE 6037 @@ -77031,7 +76941,7 @@ /* Firmware Names */ MODULE_FIRMWARE("radeon/BARTS_pfp.bin"); MODULE_FIRMWARE("radeon/BARTS_me.bin"); -@@ -68,6 +72,9 @@ MODULE_FIRMWARE("radeon/CAYMAN_pfp.bin"); +@@ -68,6 +72,9 @@ MODULE_FIRMWARE("radeon/CAYMAN_me.bin"); MODULE_FIRMWARE("radeon/CAYMAN_mc.bin"); MODULE_FIRMWARE("radeon/CAYMAN_rlc.bin"); @@ -77041,7 +76951,7 @@ #define BTC_IO_MC_REGS_SIZE 29 -@@ -326,6 +333,15 @@ int ni_init_microcode(struct radeon_device *rdev) +@@ -326,6 +333,15 @@ rlc_req_size = CAYMAN_RLC_UCODE_SIZE * 4; mc_req_size = CAYMAN_MC_UCODE_SIZE * 4; break; @@ -77057,7 +76967,7 @@ default: BUG(); } -@@ -365,15 +381,18 @@ int ni_init_microcode(struct radeon_device *rdev) +@@ -365,15 +381,18 @@ err = -EINVAL; } @@ -77085,7 +76995,7 @@ } out: platform_device_unregister(pdev); -@@ -478,6 +497,7 @@ static u32 cayman_get_tile_pipe_to_backend_map(struct radeon_device *rdev, +@@ -474,6 +493,7 @@ memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * CAYMAN_MAX_PIPES); switch (rdev->family) { case CHIP_CAYMAN: @@ -77093,7 +77003,7 @@ force_no_swizzle = true; break; default: -@@ -610,7 +630,6 @@ static void cayman_gpu_init(struct radeon_device *rdev) +@@ -606,7 +626,6 @@ switch (rdev->family) { case CHIP_CAYMAN: @@ -77101,7 +77011,7 @@ rdev->config.cayman.max_shader_engines = 2; rdev->config.cayman.max_pipes_per_simd = 4; rdev->config.cayman.max_tile_pipes = 8; -@@ -632,6 +651,67 @@ static void cayman_gpu_init(struct radeon_device *rdev) +@@ -628,6 +647,67 @@ rdev->config.cayman.sc_hiz_tile_fifo_size = 0x30; rdev->config.cayman.sc_earlyz_tile_fifo_size = 0x130; break; @@ -77169,7 +77079,7 @@ } /* Initialize HDP */ -@@ -652,7 +732,9 @@ static void cayman_gpu_init(struct radeon_device *rdev) +@@ -648,7 +728,9 @@ cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE); cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG); @@ -77180,7 +77090,7 @@ gc_user_rb_backend_disable = RREG32(GC_USER_RB_BACKEND_DISABLE); gc_user_shader_pipe_config = RREG32(GC_USER_SHADER_PIPE_CONFIG); cgts_user_tcc_disable = RREG32(CGTS_USER_TCC_DISABLE); -@@ -804,17 +886,23 @@ static void cayman_gpu_init(struct radeon_device *rdev) +@@ -800,17 +882,23 @@ rdev->config.cayman.tile_config |= (3 << 0); break; } @@ -77214,7 +77124,7 @@ } rdev->config.cayman.tile_config |= ((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8; -@@ -825,6 +913,8 @@ static void cayman_gpu_init(struct radeon_device *rdev) +@@ -821,6 +909,8 @@ WREG32(GB_BACKEND_MAP, gb_backend_map); WREG32(GB_ADDR_CONFIG, gb_addr_config); WREG32(DMIF_ADDR_CONFIG, gb_addr_config); @@ -77223,7 +77133,7 @@ WREG32(HDP_ADDR_CONFIG, gb_addr_config); /* primary versions */ -@@ -944,7 +1034,7 @@ void cayman_pcie_gart_tlb_flush(struct radeon_device *rdev) +@@ -940,7 +1030,7 @@ int cayman_pcie_gart_enable(struct radeon_device *rdev) { @@ -77232,7 +77142,7 @@ if (rdev->gart.robj == NULL) { dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); -@@ -955,9 +1045,12 @@ int cayman_pcie_gart_enable(struct radeon_device *rdev) +@@ -951,9 +1041,12 @@ return r; radeon_gart_restore(rdev); /* Setup TLB control */ @@ -77246,7 +77156,7 @@ SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU); /* Setup L2 cache */ WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | -@@ -977,9 +1070,26 @@ int cayman_pcie_gart_enable(struct radeon_device *rdev) +@@ -973,9 +1066,26 @@ WREG32(VM_CONTEXT0_CNTL2, 0); WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | RANGE_PROTECTION_FAULT_ENABLE_DEFAULT); @@ -77274,7 +77184,7 @@ cayman_pcie_gart_tlb_flush(rdev); DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", -@@ -1016,9 +1126,69 @@ void cayman_pcie_gart_fini(struct radeon_device *rdev) +@@ -1012,9 +1122,69 @@ radeon_gart_fini(rdev); } @@ -77344,7 +77254,7 @@ static void cayman_cp_enable(struct radeon_device *rdev, bool enable) { if (enable) -@@ -1059,63 +1229,64 @@ static int cayman_cp_load_microcode(struct radeon_device *rdev) +@@ -1055,63 +1225,64 @@ static int cayman_cp_start(struct radeon_device *rdev) { @@ -77420,16 +77330,17 @@ - radeon_ring_write(rdev, 0xffffffff); - radeon_ring_write(rdev, 0xffffffff); - radeon_ring_write(rdev, 0xffffffff); +- +- radeon_ring_write(rdev, 0xc0026900); +- radeon_ring_write(rdev, 0x00000316); +- radeon_ring_write(rdev, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */ +- radeon_ring_write(rdev, 0x00000010); /* */ + radeon_ring_write(ring, 0xc0036f00); + radeon_ring_write(ring, 0x00000bc4); + radeon_ring_write(ring, 0xffffffff); + radeon_ring_write(ring, 0xffffffff); + radeon_ring_write(ring, 0xffffffff); - -- radeon_ring_write(rdev, 0xc0026900); -- radeon_ring_write(rdev, 0x00000316); -- radeon_ring_write(rdev, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */ -- radeon_ring_write(rdev, 0x00000010); /* */ ++ + radeon_ring_write(ring, 0xc0026900); + radeon_ring_write(ring, 0x00000316); + radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */ @@ -77440,7 +77351,7 @@ /* XXX init other rings */ -@@ -1125,11 +1296,12 @@ static int cayman_cp_start(struct radeon_device *rdev) +@@ -1121,11 +1292,12 @@ static void cayman_cp_fini(struct radeon_device *rdev) { cayman_cp_enable(rdev, false); @@ -77454,7 +77365,7 @@ u32 tmp; u32 rb_bufsz; int r; -@@ -1146,7 +1318,8 @@ int cayman_cp_resume(struct radeon_device *rdev) +@@ -1142,7 +1314,8 @@ WREG32(GRBM_SOFT_RESET, 0); RREG32(GRBM_SOFT_RESET); @@ -77464,7 +77375,7 @@ /* Set the write pointer delay */ WREG32(CP_RB_WPTR_DELAY, 0); -@@ -1155,7 +1328,8 @@ int cayman_cp_resume(struct radeon_device *rdev) +@@ -1151,7 +1324,8 @@ /* ring 0 - compute and gfx */ /* Set ring buffer size */ @@ -77474,7 +77385,7 @@ tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; #ifdef __BIG_ENDIAN tmp |= BUF_SWAP_32BIT; -@@ -1164,8 +1338,8 @@ int cayman_cp_resume(struct radeon_device *rdev) +@@ -1160,8 +1334,8 @@ /* Initialize the ring buffer's read and write pointers */ WREG32(CP_RB0_CNTL, tmp | RB_RPTR_WR_ENA); @@ -77485,7 +77396,7 @@ /* set the wb address wether it's enabled or not */ WREG32(CP_RB0_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC); -@@ -1182,13 +1356,14 @@ int cayman_cp_resume(struct radeon_device *rdev) +@@ -1178,13 +1352,14 @@ mdelay(1); WREG32(CP_RB0_CNTL, tmp); @@ -77503,7 +77414,7 @@ tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; #ifdef __BIG_ENDIAN tmp |= BUF_SWAP_32BIT; -@@ -1197,8 +1372,8 @@ int cayman_cp_resume(struct radeon_device *rdev) +@@ -1193,8 +1368,8 @@ /* Initialize the ring buffer's read and write pointers */ WREG32(CP_RB1_CNTL, tmp | RB_RPTR_WR_ENA); @@ -77514,7 +77425,7 @@ /* set the wb address wether it's enabled or not */ WREG32(CP_RB1_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFFFFFFFC); -@@ -1207,13 +1382,14 @@ int cayman_cp_resume(struct radeon_device *rdev) +@@ -1203,13 +1378,14 @@ mdelay(1); WREG32(CP_RB1_CNTL, tmp); @@ -77532,7 +77443,7 @@ tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; #ifdef __BIG_ENDIAN tmp |= BUF_SWAP_32BIT; -@@ -1222,8 +1398,8 @@ int cayman_cp_resume(struct radeon_device *rdev) +@@ -1218,8 +1394,8 @@ /* Initialize the ring buffer's read and write pointers */ WREG32(CP_RB2_CNTL, tmp | RB_RPTR_WR_ENA); @@ -77543,7 +77454,7 @@ /* set the wb address wether it's enabled or not */ WREG32(CP_RB2_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFFFFFFFC); -@@ -1232,28 +1408,28 @@ int cayman_cp_resume(struct radeon_device *rdev) +@@ -1228,28 +1404,28 @@ mdelay(1); WREG32(CP_RB2_CNTL, tmp); @@ -77582,7 +77493,7 @@ { u32 srbm_status; u32 grbm_status; -@@ -1266,20 +1442,20 @@ bool cayman_gpu_is_lockup(struct radeon_device *rdev) +@@ -1262,20 +1438,20 @@ grbm_status_se0 = RREG32(GRBM_STATUS_SE0); grbm_status_se1 = RREG32(GRBM_STATUS_SE1); if (!(grbm_status & GUI_ACTIVE)) { @@ -77610,7 +77521,7 @@ } static int cayman_gpu_soft_reset(struct radeon_device *rdev) -@@ -1299,6 +1475,15 @@ static int cayman_gpu_soft_reset(struct radeon_device *rdev) +@@ -1295,6 +1471,15 @@ RREG32(GRBM_STATUS_SE1)); dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n", RREG32(SRBM_STATUS)); @@ -77626,7 +77537,7 @@ evergreen_mc_stop(rdev, &save); if (evergreen_mc_wait_for_idle(rdev)) { dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); -@@ -1329,6 +1514,7 @@ static int cayman_gpu_soft_reset(struct radeon_device *rdev) +@@ -1325,6 +1510,7 @@ (void)RREG32(GRBM_SOFT_RESET); /* Wait a little for things to settle down */ udelay(50); @@ -77634,7 +77545,7 @@ dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n", RREG32(GRBM_STATUS)); dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n", -@@ -1348,23 +1534,35 @@ int cayman_asic_reset(struct radeon_device *rdev) +@@ -1344,23 +1530,35 @@ static int cayman_startup(struct radeon_device *rdev) { @@ -77678,7 +77589,7 @@ r = r600_vram_scratch_init(rdev); if (r) -@@ -1379,15 +1577,42 @@ static int cayman_startup(struct radeon_device *rdev) +@@ -1375,15 +1573,42 @@ r = evergreen_blit_init(rdev); if (r) { r600_blit_fini(rdev); @@ -77722,7 +77633,7 @@ /* Enable IRQ */ r = r600_irq_init(rdev); if (r) { -@@ -1397,7 +1622,9 @@ static int cayman_startup(struct radeon_device *rdev) +@@ -1393,7 +1618,9 @@ } evergreen_irq_set(rdev); @@ -77733,7 +77644,7 @@ if (r) return r; r = cayman_cp_load_microcode(rdev); -@@ -1407,6 +1634,21 @@ static int cayman_startup(struct radeon_device *rdev) +@@ -1403,6 +1630,21 @@ if (r) return r; @@ -77755,7 +77666,7 @@ return 0; } -@@ -1421,32 +1663,27 @@ int cayman_resume(struct radeon_device *rdev) +@@ -1417,32 +1659,27 @@ /* post card */ atom_asic_init(rdev->mode_info.atom_context); @@ -77794,7 +77705,7 @@ return 0; } -@@ -1458,6 +1695,7 @@ int cayman_suspend(struct radeon_device *rdev) +@@ -1454,6 +1691,7 @@ */ int cayman_init(struct radeon_device *rdev) { @@ -77802,7 +77713,7 @@ int r; /* This don't do much */ -@@ -1510,8 +1748,8 @@ int cayman_init(struct radeon_device *rdev) +@@ -1506,8 +1744,8 @@ if (r) return r; @@ -77813,7 +77724,7 @@ rdev->ih.ring_obj = NULL; r600_ih_ring_init(rdev, 64 * 1024); -@@ -1520,35 +1758,40 @@ int cayman_init(struct radeon_device *rdev) +@@ -1516,35 +1754,40 @@ if (r) return r; @@ -77867,7 +77778,7 @@ DRM_ERROR("radeon: MC ucode required for NI+.\n"); return -EINVAL; } -@@ -1561,12 +1804,16 @@ void cayman_fini(struct radeon_device *rdev) +@@ -1557,12 +1800,16 @@ r600_blit_fini(rdev); cayman_cp_fini(rdev); r600_irq_fini(rdev); @@ -77885,7 +77796,7 @@ radeon_fence_driver_fini(rdev); radeon_bo_fini(rdev); radeon_atombios_fini(rdev); -@@ -1574,3 +1821,89 @@ void cayman_fini(struct radeon_device *rdev) +@@ -1570,3 +1817,89 @@ rdev->bios = NULL; } @@ -77975,10 +77886,10 @@ + addr |= flags; + writeq(addr, ptr + (pfn * 8)); +} -diff --git a/drivers/gpu/drm/radeon/nid.h b/drivers/gpu/drm/radeon/nid.h -index 4672869..d90b8b7 100644 ---- a/drivers/gpu/drm/radeon/nid.h -+++ b/drivers/gpu/drm/radeon/nid.h +Index: linux-3.2.46/drivers/gpu/drm/radeon/nid.h +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/radeon/nid.h 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/radeon/nid.h 2013-07-26 19:26:23.000000000 +0000 @@ -42,6 +42,13 @@ #define CAYMAN_MAX_TCC_MASK 0xFF @@ -78070,11 +77981,11 @@ #define PACKET3_EVENT_WRITE_EOS 0x48 #define PACKET3_PREAMBLE_CNTL 0x4A # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) -diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c -index fad7cd1..fe33d35 100644 ---- a/drivers/gpu/drm/radeon/r100.c -+++ b/drivers/gpu/drm/radeon/r100.c -@@ -65,6 +65,40 @@ MODULE_FIRMWARE(FIRMWARE_R520); +Index: linux-3.2.46/drivers/gpu/drm/radeon/r100.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/radeon/r100.c 2013-07-26 19:25:21.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/radeon/r100.c 2013-07-26 19:26:23.000000000 +0000 +@@ -65,6 +65,40 @@ #include "r100_track.h" @@ -78115,7 +78026,7 @@ /* This files gather functions specifics to: * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 */ -@@ -87,23 +121,27 @@ int r100_reloc_pitch_offset(struct radeon_cs_parser *p, +@@ -87,23 +121,27 @@ r100_cs_dump_packet(p, pkt); return r; } @@ -78154,7 +78065,7 @@ return 0; } -@@ -412,7 +450,7 @@ void r100_pm_misc(struct radeon_device *rdev) +@@ -412,7 +450,7 @@ /* set pcie lanes */ if ((rdev->flags & RADEON_IS_PCIE) && !(rdev->flags & RADEON_IS_IGP) && @@ -78163,7 +78074,7 @@ (ps->pcie_lanes != rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) { radeon_set_pcie_lanes(rdev, -@@ -592,8 +630,8 @@ int r100_pci_gart_init(struct radeon_device *rdev) +@@ -592,8 +630,8 @@ if (r) return r; rdev->gart.table_size = rdev->gart.num_gpu_pages * 4; @@ -78174,7 +78085,7 @@ return radeon_gart_table_ram_alloc(rdev); } -@@ -667,7 +705,7 @@ int r100_irq_set(struct radeon_device *rdev) +@@ -667,7 +705,7 @@ WREG32(R_000040_GEN_INT_CNTL, 0); return -EINVAL; } @@ -78183,7 +78094,7 @@ tmp |= RADEON_SW_INT_ENABLE; } if (rdev->irq.gui_idle) { -@@ -739,7 +777,7 @@ int r100_irq_process(struct radeon_device *rdev) +@@ -739,7 +777,7 @@ while (status) { /* SW interrupt */ if (status & RADEON_SW_INT_TEST) { @@ -78192,7 +78103,7 @@ } /* gui idle interrupt */ if (status & RADEON_GUI_IDLE_STAT) { -@@ -809,25 +847,36 @@ u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc) +@@ -809,25 +847,36 @@ void r100_fence_ring_emit(struct radeon_device *rdev, struct radeon_fence *fence) { @@ -78243,7 +78154,7 @@ } int r100_copy_blit(struct radeon_device *rdev, -@@ -836,6 +885,7 @@ int r100_copy_blit(struct radeon_device *rdev, +@@ -836,6 +885,7 @@ unsigned num_gpu_pages, struct radeon_fence *fence) { @@ -78251,7 +78162,7 @@ uint32_t cur_pages; uint32_t stride_bytes = RADEON_GPU_PAGE_SIZE; uint32_t pitch; -@@ -853,7 +903,7 @@ int r100_copy_blit(struct radeon_device *rdev, +@@ -853,7 +903,7 @@ /* Ask for enough room for blit + flush + fence */ ndw = 64 + (10 * num_loops); @@ -78260,7 +78171,7 @@ if (r) { DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw); return -EINVAL; -@@ -867,8 +917,8 @@ int r100_copy_blit(struct radeon_device *rdev, +@@ -867,8 +917,8 @@ /* pages are in Y direction - height page width in X direction - width */ @@ -78271,7 +78182,7 @@ RADEON_GMC_SRC_PITCH_OFFSET_CNTL | RADEON_GMC_DST_PITCH_OFFSET_CNTL | RADEON_GMC_SRC_CLIPPING | -@@ -880,26 +930,26 @@ int r100_copy_blit(struct radeon_device *rdev, +@@ -880,26 +930,26 @@ RADEON_DP_SRC_SOURCE_MEMORY | RADEON_GMC_CLR_CMP_CNTL_DIS | RADEON_GMC_WR_MSK_DIS); @@ -78312,7 +78223,7 @@ return r; } -@@ -918,21 +968,21 @@ static int r100_cp_wait_for_idle(struct radeon_device *rdev) +@@ -918,21 +968,21 @@ return -1; } @@ -78339,7 +78250,7 @@ } -@@ -1033,6 +1083,7 @@ static void r100_cp_load_microcode(struct radeon_device *rdev) +@@ -1030,6 +1080,7 @@ int r100_cp_init(struct radeon_device *rdev, unsigned ring_size) { @@ -78347,7 +78258,7 @@ unsigned rb_bufsz; unsigned rb_blksz; unsigned max_fetch; -@@ -1058,7 +1109,9 @@ int r100_cp_init(struct radeon_device *rdev, unsigned ring_size) +@@ -1055,7 +1106,9 @@ rb_bufsz = drm_order(ring_size / 8); ring_size = (1 << (rb_bufsz + 1)) * 4; r100_cp_load_microcode(rdev); @@ -78358,7 +78269,7 @@ if (r) { return r; } -@@ -1067,7 +1120,7 @@ int r100_cp_init(struct radeon_device *rdev, unsigned ring_size) +@@ -1064,7 +1117,7 @@ rb_blksz = 9; /* cp will read 128bytes at a time (4 dwords) */ max_fetch = 1; @@ -78367,7 +78278,7 @@ /* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */ pre_write_timer = 64; /* Force CP_RB_WPTR write if written more than one time before the -@@ -1097,13 +1150,13 @@ int r100_cp_init(struct radeon_device *rdev, unsigned ring_size) +@@ -1094,13 +1147,13 @@ WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_NO_UPDATE); /* Set ring address */ @@ -78385,7 +78296,7 @@ /* set the wb address whether it's enabled or not */ WREG32(R_00070C_CP_RB_RPTR_ADDR, -@@ -1119,7 +1172,7 @@ int r100_cp_init(struct radeon_device *rdev, unsigned ring_size) +@@ -1116,7 +1169,7 @@ WREG32(RADEON_CP_RB_CNTL, tmp); udelay(10); @@ -78394,7 +78305,7 @@ /* Set cp mode to bus mastering & enable cp*/ WREG32(RADEON_CP_CSQ_MODE, REG_SET(RADEON_INDIRECT2_START, indirect2_start) | -@@ -1127,13 +1180,13 @@ int r100_cp_init(struct radeon_device *rdev, unsigned ring_size) +@@ -1124,13 +1177,13 @@ WREG32(RADEON_CP_RB_WPTR_DELAY, 0); WREG32(RADEON_CP_CSQ_MODE, 0x00004D4D); WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM); @@ -78411,7 +78322,7 @@ radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size); return 0; } -@@ -1145,7 +1198,7 @@ void r100_cp_fini(struct radeon_device *rdev) +@@ -1142,7 +1195,7 @@ } /* Disable ring */ r100_cp_disable(rdev); @@ -78420,7 +78331,7 @@ DRM_INFO("radeon: cp finalized\n"); } -@@ -1153,7 +1206,7 @@ void r100_cp_disable(struct radeon_device *rdev) +@@ -1150,7 +1203,7 @@ { /* Disable ring */ radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); @@ -78429,7 +78340,7 @@ WREG32(RADEON_CP_CSQ_MODE, 0); WREG32(RADEON_CP_CSQ_CNTL, 0); WREG32(R_000770_SCRATCH_UMSK, 0); -@@ -1163,13 +1216,6 @@ void r100_cp_disable(struct radeon_device *rdev) +@@ -1160,13 +1213,6 @@ } } @@ -78443,7 +78354,7 @@ /* * CS functions */ -@@ -1543,7 +1589,17 @@ static int r100_packet0_check(struct radeon_cs_parser *p, +@@ -1540,7 +1586,17 @@ r100_cs_dump_packet(p, pkt); return r; } @@ -78462,7 +78373,7 @@ track->textures[i].robj = reloc->robj; track->tex_dirty = true; break; -@@ -1614,15 +1670,17 @@ static int r100_packet0_check(struct radeon_cs_parser *p, +@@ -1611,15 +1667,17 @@ r100_cs_dump_packet(p, pkt); return r; } @@ -78489,7 +78400,7 @@ track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK; track->cb_dirty = true; -@@ -2097,9 +2155,9 @@ int r100_mc_wait_for_idle(struct radeon_device *rdev) +@@ -2094,9 +2152,9 @@ return -1; } @@ -78501,7 +78412,7 @@ lockup->last_jiffies = jiffies; } -@@ -2124,20 +2182,20 @@ void r100_gpu_lockup_update(struct r100_gpu_lockup *lockup, struct radeon_cp *cp +@@ -2121,20 +2179,20 @@ * false positive when CP is just gived nothing to do. * **/ @@ -78526,7 +78437,7 @@ lockup->last_jiffies = jiffies; return false; } -@@ -2150,32 +2208,31 @@ bool r100_gpu_cp_is_lockup(struct radeon_device *rdev, struct r100_gpu_lockup *l +@@ -2147,32 +2205,31 @@ return false; } @@ -78567,7 +78478,7 @@ /* disable bus mastering */ tmp = RREG32(R_000030_BUS_CNTL); -@@ -2186,8 +2243,7 @@ void r100_bm_disable(struct radeon_device *rdev) +@@ -2183,8 +2240,7 @@ WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000040); tmp = RREG32(RADEON_BUS_CNTL); mdelay(1); @@ -78577,7 +78488,7 @@ mdelay(1); } -@@ -2497,7 +2553,7 @@ static void r100_pll_errata_after_data(struct radeon_device *rdev) +@@ -2494,7 +2550,7 @@ * or the chip could hang on a subsequent access */ if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) { @@ -78586,7 +78497,7 @@ } /* This function is required to workaround a hardware bug in some (all?) -@@ -2578,21 +2634,22 @@ static int r100_debugfs_cp_ring_info(struct seq_file *m, void *data) +@@ -2575,21 +2631,22 @@ struct drm_info_node *node = (struct drm_info_node *) m->private; struct drm_device *dev = node->minor->dev; struct radeon_device *rdev = dev->dev_private; @@ -78614,7 +78525,7 @@ } return 0; } -@@ -3634,7 +3691,7 @@ void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track +@@ -3631,7 +3688,7 @@ } } @@ -78623,7 +78534,7 @@ { uint32_t scratch; uint32_t tmp = 0; -@@ -3647,15 +3704,15 @@ int r100_ring_test(struct radeon_device *rdev) +@@ -3644,15 +3701,15 @@ return r; } WREG32(scratch, 0xCAFEDEAD); @@ -78643,7 +78554,7 @@ for (i = 0; i < rdev->usec_timeout; i++) { tmp = RREG32(scratch); if (tmp == 0xDEADBEEF) { -@@ -3676,12 +3733,14 @@ int r100_ring_test(struct radeon_device *rdev) +@@ -3673,12 +3730,14 @@ void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) { @@ -78662,7 +78573,7 @@ { struct radeon_ib *ib; uint32_t scratch; -@@ -3695,7 +3754,7 @@ int r100_ib_test(struct radeon_device *rdev) +@@ -3692,7 +3751,7 @@ return r; } WREG32(scratch, 0xCAFEDEAD); @@ -78671,7 +78582,7 @@ if (r) { return r; } -@@ -3739,34 +3798,16 @@ int r100_ib_test(struct radeon_device *rdev) +@@ -3736,34 +3795,16 @@ void r100_ib_fini(struct radeon_device *rdev) { @@ -78708,7 +78619,7 @@ WREG32(R_000740_CP_CSQ_CNTL, 0); /* Save few CRTC registers */ -@@ -3904,6 +3945,12 @@ static int r100_startup(struct radeon_device *rdev) +@@ -3901,6 +3942,12 @@ if (r) return r; @@ -78721,7 +78632,7 @@ /* Enable IRQ */ r100_irq_set(rdev); rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); -@@ -3913,16 +3960,25 @@ static int r100_startup(struct radeon_device *rdev) +@@ -3910,16 +3957,25 @@ dev_err(rdev->dev, "failed initializing CP (%d).\n", r); return r; } @@ -78749,7 +78660,7 @@ /* Make sur GART are not working */ if (rdev->flags & RADEON_IS_PCI) r100_pci_gart_disable(rdev); -@@ -3940,11 +3996,18 @@ int r100_resume(struct radeon_device *rdev) +@@ -3937,11 +3993,18 @@ r100_clock_startup(rdev); /* Initialize surface registers */ radeon_surface_init(rdev); @@ -78769,7 +78680,7 @@ r100_cp_disable(rdev); radeon_wb_disable(rdev); r100_irq_disable(rdev); -@@ -4063,7 +4126,14 @@ int r100_init(struct radeon_device *rdev) +@@ -4060,7 +4123,14 @@ return r; } r100_set_safe_registers(rdev); @@ -78784,11 +78695,11 @@ r = r100_startup(rdev); if (r) { /* Somethings want wront with the accel init stop accel */ -diff --git a/drivers/gpu/drm/radeon/r200.c b/drivers/gpu/drm/radeon/r200.c -index a1f3ba0..a59cc47 100644 ---- a/drivers/gpu/drm/radeon/r200.c -+++ b/drivers/gpu/drm/radeon/r200.c -@@ -87,6 +87,7 @@ int r200_copy_dma(struct radeon_device *rdev, +Index: linux-3.2.46/drivers/gpu/drm/radeon/r200.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/radeon/r200.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/radeon/r200.c 2013-07-26 19:26:23.000000000 +0000 +@@ -87,6 +87,7 @@ unsigned num_gpu_pages, struct radeon_fence *fence) { @@ -78796,7 +78707,7 @@ uint32_t size; uint32_t cur_size; int i, num_loops; -@@ -95,33 +96,33 @@ int r200_copy_dma(struct radeon_device *rdev, +@@ -95,33 +96,33 @@ /* radeon pitch is /64 */ size = num_gpu_pages << RADEON_GPU_PAGE_SHIFT; num_loops = DIV_ROUND_UP(size, 0x1FFFFF); @@ -78840,7 +78751,7 @@ return r; } -@@ -214,7 +215,17 @@ int r200_packet0_check(struct radeon_cs_parser *p, +@@ -214,7 +215,17 @@ r100_cs_dump_packet(p, pkt); return r; } @@ -78859,7 +78770,7 @@ track->textures[i].robj = reloc->robj; track->tex_dirty = true; break; -@@ -276,14 +287,17 @@ int r200_packet0_check(struct radeon_cs_parser *p, +@@ -276,14 +287,17 @@ return r; } @@ -78867,15 +78778,16 @@ - tile_flags |= RADEON_COLOR_TILE_ENABLE; - if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) - tile_flags |= RADEON_COLOR_MICROTILE_ENABLE; +- +- tmp = idx_value & ~(0x7 << 16); +- tmp |= tile_flags; +- ib[idx] = tmp; + if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { + if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) + tile_flags |= RADEON_COLOR_TILE_ENABLE; + if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) + tile_flags |= RADEON_COLOR_MICROTILE_ENABLE; - -- tmp = idx_value & ~(0x7 << 16); -- tmp |= tile_flags; -- ib[idx] = tmp; ++ + tmp = idx_value & ~(0x7 << 16); + tmp |= tile_flags; + ib[idx] = tmp; @@ -78884,11 +78796,11 @@ track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK; track->cb_dirty = true; -diff --git a/drivers/gpu/drm/radeon/r300.c b/drivers/gpu/drm/radeon/r300.c -index c93bc64..fa14383 100644 ---- a/drivers/gpu/drm/radeon/r300.c -+++ b/drivers/gpu/drm/radeon/r300.c -@@ -105,8 +105,8 @@ int rv370_pcie_gart_init(struct radeon_device *rdev) +Index: linux-3.2.46/drivers/gpu/drm/radeon/r300.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/radeon/r300.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/radeon/r300.c 2013-07-26 19:26:23.000000000 +0000 +@@ -105,8 +105,8 @@ if (r) DRM_ERROR("Failed to register debugfs file for PCIE gart !\n"); rdev->gart.table_size = rdev->gart.num_gpu_pages * 4; @@ -78899,7 +78811,7 @@ return radeon_gart_table_vram_alloc(rdev); } -@@ -175,36 +175,38 @@ void rv370_pcie_gart_fini(struct radeon_device *rdev) +@@ -175,36 +175,38 @@ void r300_fence_ring_emit(struct radeon_device *rdev, struct radeon_fence *fence) { @@ -78957,7 +78869,7 @@ { unsigned gb_tile_config; int r; -@@ -227,44 +229,44 @@ void r300_ring_start(struct radeon_device *rdev) +@@ -227,44 +229,44 @@ break; } @@ -79029,7 +78941,7 @@ ((6 << R300_MS_X0_SHIFT) | (6 << R300_MS_Y0_SHIFT) | (6 << R300_MS_X1_SHIFT) | -@@ -273,8 +275,8 @@ void r300_ring_start(struct radeon_device *rdev) +@@ -273,8 +275,8 @@ (6 << R300_MS_Y2_SHIFT) | (6 << R300_MSBD0_Y_SHIFT) | (6 << R300_MSBD0_X_SHIFT))); @@ -79040,7 +78952,7 @@ ((6 << R300_MS_X3_SHIFT) | (6 << R300_MS_Y3_SHIFT) | (6 << R300_MS_X4_SHIFT) | -@@ -282,16 +284,16 @@ void r300_ring_start(struct radeon_device *rdev) +@@ -282,16 +284,16 @@ (6 << R300_MS_X5_SHIFT) | (6 << R300_MS_Y5_SHIFT) | (6 << R300_MSBD1_SHIFT))); @@ -79064,7 +78976,7 @@ } void r300_errata(struct radeon_device *rdev) -@@ -375,26 +377,26 @@ void r300_gpu_init(struct radeon_device *rdev) +@@ -375,26 +377,26 @@ rdev->num_gb_pipes, rdev->num_z_pipes); } @@ -79099,7 +79011,7 @@ } int r300_asic_reset(struct radeon_device *rdev) -@@ -701,7 +703,7 @@ static int r300_packet0_check(struct radeon_cs_parser *p, +@@ -701,7 +703,7 @@ return r; } @@ -79108,7 +79020,7 @@ ib[idx] = (idx_value & 31) | /* keep the 1st 5 bits */ ((idx_value & ~31) + (u32)reloc->lobj.gpu_offset); } else { -@@ -765,7 +767,7 @@ static int r300_packet0_check(struct radeon_cs_parser *p, +@@ -765,7 +767,7 @@ /* RB3D_COLORPITCH1 */ /* RB3D_COLORPITCH2 */ /* RB3D_COLORPITCH3 */ @@ -79117,7 +79029,7 @@ r = r100_cs_packet_next_reloc(p, &reloc); if (r) { DRM_ERROR("No reloc for ib[%d]=0x%04X\n", -@@ -850,7 +852,7 @@ static int r300_packet0_check(struct radeon_cs_parser *p, +@@ -850,7 +852,7 @@ break; case 0x4F24: /* ZB_DEPTHPITCH */ @@ -79126,7 +79038,7 @@ r = r100_cs_packet_next_reloc(p, &reloc); if (r) { DRM_ERROR("No reloc for ib[%d]=0x%04X\n", -@@ -1396,6 +1398,12 @@ static int r300_startup(struct radeon_device *rdev) +@@ -1396,6 +1398,12 @@ if (r) return r; @@ -79139,7 +79051,7 @@ /* Enable IRQ */ r100_irq_set(rdev); rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); -@@ -1405,16 +1413,25 @@ static int r300_startup(struct radeon_device *rdev) +@@ -1405,16 +1413,25 @@ dev_err(rdev->dev, "failed initializing CP (%d).\n", r); return r; } @@ -79167,7 +79079,7 @@ /* Make sur GART are not working */ if (rdev->flags & RADEON_IS_PCIE) rv370_pcie_gart_disable(rdev); -@@ -1434,11 +1451,18 @@ int r300_resume(struct radeon_device *rdev) +@@ -1434,11 +1451,18 @@ r300_clock_startup(rdev); /* Initialize surface registers */ radeon_surface_init(rdev); @@ -79187,7 +79099,7 @@ r100_cp_disable(rdev); radeon_wb_disable(rdev); r100_irq_disable(rdev); -@@ -1539,7 +1563,14 @@ int r300_init(struct radeon_device *rdev) +@@ -1539,7 +1563,14 @@ return r; } r300_set_reg_safe(rdev); @@ -79202,11 +79114,11 @@ r = r300_startup(rdev); if (r) { /* Somethings want wront with the accel init stop accel */ -diff --git a/drivers/gpu/drm/radeon/r420.c b/drivers/gpu/drm/radeon/r420.c -index 417fab8..f3fcaac 100644 ---- a/drivers/gpu/drm/radeon/r420.c -+++ b/drivers/gpu/drm/radeon/r420.c -@@ -199,6 +199,8 @@ static void r420_clock_resume(struct radeon_device *rdev) +Index: linux-3.2.46/drivers/gpu/drm/radeon/r420.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/radeon/r420.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/radeon/r420.c 2013-07-26 19:26:23.000000000 +0000 +@@ -199,6 +199,8 @@ static void r420_cp_errata_init(struct radeon_device *rdev) { @@ -79215,7 +79127,7 @@ /* RV410 and R420 can lock up if CP DMA to host memory happens * while the 2D engine is busy. * -@@ -206,22 +208,24 @@ static void r420_cp_errata_init(struct radeon_device *rdev) +@@ -206,22 +208,24 @@ * of the CP init, apparently. */ radeon_scratch_get(rdev, &rdev->config.r300.resync_scratch); @@ -79249,7 +79161,7 @@ radeon_scratch_free(rdev, rdev->config.r300.resync_scratch); } -@@ -254,6 +258,12 @@ static int r420_startup(struct radeon_device *rdev) +@@ -254,6 +258,12 @@ if (r) return r; @@ -79262,7 +79174,7 @@ /* Enable IRQ */ r100_irq_set(rdev); rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); -@@ -264,16 +274,25 @@ static int r420_startup(struct radeon_device *rdev) +@@ -264,16 +274,25 @@ return r; } r420_cp_errata_init(rdev); @@ -79290,7 +79202,7 @@ /* Make sur GART are not working */ if (rdev->flags & RADEON_IS_PCIE) rv370_pcie_gart_disable(rdev); -@@ -297,11 +316,18 @@ int r420_resume(struct radeon_device *rdev) +@@ -297,11 +316,18 @@ r420_clock_resume(rdev); /* Initialize surface registers */ radeon_surface_init(rdev); @@ -79310,7 +79222,7 @@ r420_cp_errata_fini(rdev); r100_cp_disable(rdev); radeon_wb_disable(rdev); -@@ -414,7 +440,14 @@ int r420_init(struct radeon_device *rdev) +@@ -414,7 +440,14 @@ return r; } r420_set_reg_safe(rdev); @@ -79325,10 +79237,10 @@ r = r420_startup(rdev); if (r) { /* Somethings want wront with the accel init stop accel */ -diff --git a/drivers/gpu/drm/radeon/r500_reg.h b/drivers/gpu/drm/radeon/r500_reg.h -index fc43705..ec576aa 100644 ---- a/drivers/gpu/drm/radeon/r500_reg.h -+++ b/drivers/gpu/drm/radeon/r500_reg.h +Index: linux-3.2.46/drivers/gpu/drm/radeon/r500_reg.h +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/radeon/r500_reg.h 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/radeon/r500_reg.h 2013-07-26 19:26:23.000000000 +0000 @@ -351,6 +351,8 @@ #define AVIVO_D1CRTC_BLANK_CONTROL 0x6084 #define AVIVO_D1CRTC_INTERLACE_CONTROL 0x6088 @@ -79354,10 +79266,10 @@ # define AVIVO_LVTMA_CNTL_HPD_MASK (1 << 4) # define AVIVO_LVTMA_CNTL_HPD_SELECT (1 << 8) # define AVIVO_LVTMA_CNTL_SYNC_PHASE (1 << 12) -diff --git a/drivers/gpu/drm/radeon/r520.c b/drivers/gpu/drm/radeon/r520.c -index 3081d07..ebcc15b 100644 ---- a/drivers/gpu/drm/radeon/r520.c -+++ b/drivers/gpu/drm/radeon/r520.c +Index: linux-3.2.46/drivers/gpu/drm/radeon/r520.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/radeon/r520.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/radeon/r520.c 2013-07-26 19:26:23.000000000 +0000 @@ -33,7 +33,7 @@ /* This files gather functions specifics to: r520,rv530,rv560,rv570,r580 */ @@ -79367,7 +79279,7 @@ { unsigned i; uint32_t tmp; -@@ -187,6 +187,12 @@ static int r520_startup(struct radeon_device *rdev) +@@ -187,6 +187,12 @@ if (r) return r; @@ -79380,7 +79292,7 @@ /* Enable IRQ */ rs600_irq_set(rdev); rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); -@@ -196,9 +202,15 @@ static int r520_startup(struct radeon_device *rdev) +@@ -196,9 +202,15 @@ dev_err(rdev->dev, "failed initializing CP (%d).\n", r); return r; } @@ -79398,7 +79310,7 @@ return r; } return 0; -@@ -206,6 +218,8 @@ static int r520_startup(struct radeon_device *rdev) +@@ -206,6 +218,8 @@ int r520_resume(struct radeon_device *rdev) { @@ -79407,7 +79319,7 @@ /* Make sur GART are not working */ if (rdev->flags & RADEON_IS_PCIE) rv370_pcie_gart_disable(rdev); -@@ -223,7 +237,13 @@ int r520_resume(struct radeon_device *rdev) +@@ -223,7 +237,13 @@ rv515_clock_startup(rdev); /* Initialize surface registers */ radeon_surface_init(rdev); @@ -79422,7 +79334,7 @@ } int r520_init(struct radeon_device *rdev) -@@ -292,7 +312,14 @@ int r520_init(struct radeon_device *rdev) +@@ -292,7 +312,14 @@ if (r) return r; rv515_set_safe_registers(rdev); @@ -79437,10 +79349,10 @@ r = r520_startup(rdev); if (r) { /* Somethings want wront with the accel init stop accel */ -diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c -index bdfa82a..b1ff9cc 100644 ---- a/drivers/gpu/drm/radeon/r600.c -+++ b/drivers/gpu/drm/radeon/r600.c +Index: linux-3.2.46/drivers/gpu/drm/radeon/r600.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/radeon/r600.c 2013-07-26 19:25:21.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/radeon/r600.c 2013-07-26 19:26:23.000000000 +0000 @@ -49,6 +49,7 @@ #define EVERGREEN_PM4_UCODE_SIZE 1376 #define EVERGREEN_RLC_UCODE_SIZE 768 @@ -79449,7 +79361,7 @@ /* Firmware Names */ MODULE_FIRMWARE("radeon/R600_pfp.bin"); -@@ -1134,7 +1135,7 @@ static void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc +@@ -1134,7 +1135,7 @@ } if (rdev->flags & RADEON_IS_AGP) { size_bf = mc->gtt_start; @@ -79458,7 +79370,7 @@ if (size_bf > size_af) { if (mc->mc_vram_size > size_bf) { dev_warn(rdev->dev, "limiting VRAM\n"); -@@ -1148,7 +1149,7 @@ static void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc +@@ -1148,7 +1149,7 @@ mc->real_vram_size = size_af; mc->mc_vram_size = size_af; } @@ -79467,7 +79379,7 @@ } mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n", -@@ -1344,7 +1345,7 @@ int r600_gpu_soft_reset(struct radeon_device *rdev) +@@ -1344,7 +1345,7 @@ return 0; } @@ -79476,7 +79388,7 @@ { u32 srbm_status; u32 grbm_status; -@@ -1361,19 +1362,19 @@ bool r600_gpu_is_lockup(struct radeon_device *rdev) +@@ -1361,19 +1362,19 @@ grbm_status = RREG32(R_008010_GRBM_STATUS); grbm_status2 = RREG32(R_008014_GRBM_STATUS2); if (!G_008010_GUI_ACTIVE(grbm_status)) { @@ -79503,7 +79415,7 @@ } int r600_asic_reset(struct radeon_device *rdev) -@@ -2145,27 +2146,28 @@ static int r600_cp_load_microcode(struct radeon_device *rdev) +@@ -2141,27 +2142,28 @@ int r600_cp_start(struct radeon_device *rdev) { @@ -79543,7 +79455,7 @@ cp_me = 0xff; WREG32(R_0086D8_CP_ME_CNTL, cp_me); -@@ -2174,6 +2176,7 @@ int r600_cp_start(struct radeon_device *rdev) +@@ -2170,6 +2172,7 @@ int r600_cp_resume(struct radeon_device *rdev) { @@ -79551,7 +79463,7 @@ u32 tmp; u32 rb_bufsz; int r; -@@ -2185,13 +2188,13 @@ int r600_cp_resume(struct radeon_device *rdev) +@@ -2181,13 +2184,13 @@ WREG32(GRBM_SOFT_RESET, 0); /* Set ring buffer size */ @@ -79567,7 +79479,7 @@ /* Set the write pointer delay */ WREG32(CP_RB_WPTR_DELAY, 0); -@@ -2199,8 +2202,8 @@ int r600_cp_resume(struct radeon_device *rdev) +@@ -2195,8 +2198,8 @@ /* Initialize the ring buffer's read and write pointers */ WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA); WREG32(CP_RB_RPTR_WR, 0); @@ -79578,7 +79490,7 @@ /* set the wb address whether it's enabled or not */ WREG32(CP_RB_RPTR_ADDR, -@@ -2218,42 +2221,36 @@ int r600_cp_resume(struct radeon_device *rdev) +@@ -2214,42 +2217,36 @@ mdelay(1); WREG32(CP_RB_CNTL, tmp); @@ -79630,7 +79542,7 @@ } -@@ -2272,11 +2269,11 @@ void r600_scratch_init(struct radeon_device *rdev) +@@ -2268,11 +2265,11 @@ } } @@ -79644,7 +79556,7 @@ int r; r = radeon_scratch_get(rdev, &scratch); -@@ -2285,16 +2282,16 @@ int r600_ring_test(struct radeon_device *rdev) +@@ -2281,16 +2278,16 @@ return r; } WREG32(scratch, 0xCAFEDEAD); @@ -79667,7 +79579,7 @@ for (i = 0; i < rdev->usec_timeout; i++) { tmp = RREG32(scratch); if (tmp == 0xDEADBEEF) -@@ -2302,10 +2299,10 @@ int r600_ring_test(struct radeon_device *rdev) +@@ -2298,10 +2295,10 @@ DRM_UDELAY(1); } if (i < rdev->usec_timeout) { @@ -79681,7 +79593,7 @@ r = -EINVAL; } radeon_scratch_free(rdev, scratch); -@@ -2315,49 +2312,66 @@ int r600_ring_test(struct radeon_device *rdev) +@@ -2311,49 +2308,66 @@ void r600_fence_ring_emit(struct radeon_device *rdev, struct radeon_fence *fence) { @@ -79776,7 +79688,7 @@ int r600_copy_blit(struct radeon_device *rdev, uint64_t src_offset, uint64_t dst_offset, -@@ -2410,6 +2424,7 @@ void r600_clear_surface_reg(struct radeon_device *rdev, int reg) +@@ -2406,6 +2420,7 @@ int r600_startup(struct radeon_device *rdev) { @@ -79784,7 +79696,7 @@ int r; /* enable pcie gen2 link */ -@@ -2439,7 +2454,7 @@ int r600_startup(struct radeon_device *rdev) +@@ -2435,7 +2450,7 @@ r = r600_blit_init(rdev); if (r) { r600_blit_fini(rdev); @@ -79793,7 +79705,7 @@ dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r); } -@@ -2448,6 +2463,12 @@ int r600_startup(struct radeon_device *rdev) +@@ -2444,6 +2459,12 @@ if (r) return r; @@ -79806,7 +79718,7 @@ /* Enable IRQ */ r = r600_irq_init(rdev); if (r) { -@@ -2457,7 +2478,10 @@ int r600_startup(struct radeon_device *rdev) +@@ -2453,7 +2474,10 @@ } r600_irq_set(rdev); @@ -79818,7 +79730,7 @@ if (r) return r; r = r600_cp_load_microcode(rdev); -@@ -2467,6 +2491,17 @@ int r600_startup(struct radeon_device *rdev) +@@ -2463,6 +2487,17 @@ if (r) return r; @@ -79836,7 +79748,7 @@ return 0; } -@@ -2495,15 +2530,11 @@ int r600_resume(struct radeon_device *rdev) +@@ -2491,15 +2526,11 @@ /* post card */ atom_asic_init(rdev->mode_info.atom_context); @@ -79854,7 +79766,7 @@ return r; } -@@ -2519,13 +2550,14 @@ int r600_resume(struct radeon_device *rdev) +@@ -2515,13 +2546,14 @@ int r600_suspend(struct radeon_device *rdev) { r600_audio_fini(rdev); @@ -79871,7 +79783,7 @@ return 0; } -@@ -2596,8 +2628,8 @@ int r600_init(struct radeon_device *rdev) +@@ -2592,8 +2624,8 @@ if (r) return r; @@ -79882,7 +79794,7 @@ rdev->ih.ring_obj = NULL; r600_ih_ring_init(rdev, 64 * 1024); -@@ -2606,30 +2638,24 @@ int r600_init(struct radeon_device *rdev) +@@ -2602,30 +2634,24 @@ if (r) return r; @@ -79920,7 +79832,7 @@ r = r600_audio_init(rdev); if (r) -@@ -2644,12 +2670,13 @@ void r600_fini(struct radeon_device *rdev) +@@ -2640,12 +2666,13 @@ r600_cp_fini(rdev); r600_irq_fini(rdev); radeon_wb_fini(rdev); @@ -79935,7 +79847,7 @@ radeon_fence_driver_fini(rdev); radeon_bo_fini(rdev); radeon_atombios_fini(rdev); -@@ -2663,24 +2690,27 @@ void r600_fini(struct radeon_device *rdev) +@@ -2659,24 +2686,27 @@ */ void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) { @@ -79968,7 +79880,7 @@ r = radeon_scratch_get(rdev, &scratch); if (r) { -@@ -2688,7 +2718,7 @@ int r600_ib_test(struct radeon_device *rdev) +@@ -2684,7 +2714,7 @@ return r; } WREG32(scratch, 0xCAFEDEAD); @@ -79977,7 +79889,7 @@ if (r) { DRM_ERROR("radeon: failed to get ib (%d).\n", r); return r; -@@ -2696,20 +2726,7 @@ int r600_ib_test(struct radeon_device *rdev) +@@ -2692,20 +2722,7 @@ ib->ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1); ib->ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); ib->ptr[2] = 0xDEADBEEF; @@ -79999,7 +79911,7 @@ r = radeon_ib_schedule(rdev, ib); if (r) { radeon_scratch_free(rdev, scratch); -@@ -2729,7 +2746,7 @@ int r600_ib_test(struct radeon_device *rdev) +@@ -2725,7 +2742,7 @@ DRM_UDELAY(1); } if (i < rdev->usec_timeout) { @@ -80008,7 +79920,7 @@ } else { DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n", scratch, tmp); -@@ -2763,7 +2780,7 @@ void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size) +@@ -2759,7 +2776,7 @@ rdev->ih.rptr = 0; } @@ -80017,7 +79929,7 @@ { int r; -@@ -2799,7 +2816,7 @@ static int r600_ih_ring_alloc(struct radeon_device *rdev) +@@ -2795,7 +2812,7 @@ return 0; } @@ -80026,7 +79938,7 @@ { int r; if (rdev->ih.ring_obj) { -@@ -2823,7 +2840,7 @@ void r600_rlc_stop(struct radeon_device *rdev) +@@ -2819,7 +2836,7 @@ /* r7xx asics need to soft reset RLC before halting */ WREG32(SRBM_SOFT_RESET, SOFT_RESET_RLC); RREG32(SRBM_SOFT_RESET); @@ -80035,7 +79947,7 @@ WREG32(SRBM_SOFT_RESET, 0); RREG32(SRBM_SOFT_RESET); } -@@ -2846,10 +2863,17 @@ static int r600_rlc_init(struct radeon_device *rdev) +@@ -2842,10 +2859,17 @@ r600_rlc_stop(rdev); @@ -80056,7 +79968,7 @@ if (rdev->family <= CHIP_CAICOS) { WREG32(RLC_HB_WPTR_LSB_ADDR, 0); WREG32(RLC_HB_WPTR_MSB_ADDR, 0); -@@ -2858,7 +2882,12 @@ static int r600_rlc_init(struct radeon_device *rdev) +@@ -2854,7 +2878,12 @@ WREG32(RLC_UCODE_CNTL, 0); fw_data = (const __be32 *)rdev->rlc_fw->data; @@ -80070,7 +79982,7 @@ for (i = 0; i < CAYMAN_RLC_UCODE_SIZE; i++) { WREG32(RLC_UCODE_ADDR, i); WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++)); -@@ -3076,7 +3105,7 @@ int r600_irq_set(struct radeon_device *rdev) +@@ -3072,7 +3101,7 @@ hpd3 = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & ~DC_HPDx_INT_EN; } @@ -80079,7 +79991,7 @@ DRM_DEBUG("r600_irq_set: sw int\n"); cp_int_cntl |= RB_INT_ENABLE; cp_int_cntl |= TIME_STAMP_INT_ENABLE; -@@ -3460,11 +3489,11 @@ restart_ih: +@@ -3456,11 +3485,11 @@ case 177: /* CP_INT in IB1 */ case 178: /* CP_INT in IB2 */ DRM_DEBUG("IH: CP int: 0x%08x\n", src_data); @@ -80093,7 +80005,7 @@ break; case 233: /* GUI IDLE */ DRM_DEBUG("IH: GUI idle\n"); -@@ -3497,30 +3526,6 @@ restart_ih: +@@ -3493,30 +3522,6 @@ */ #if defined(CONFIG_DEBUG_FS) @@ -80124,7 +80036,7 @@ static int r600_debugfs_mc_info(struct seq_file *m, void *data) { struct drm_info_node *node = (struct drm_info_node *) m->private; -@@ -3534,7 +3539,6 @@ static int r600_debugfs_mc_info(struct seq_file *m, void *data) +@@ -3530,7 +3535,6 @@ static struct drm_info_list r600_mc_info_list[] = { {"r600_mc_info", r600_debugfs_mc_info, 0, NULL}, @@ -80132,10 +80044,10 @@ }; #endif -diff --git a/drivers/gpu/drm/radeon/r600_audio.c b/drivers/gpu/drm/radeon/r600_audio.c -index 846fae5..24e3939 100644 ---- a/drivers/gpu/drm/radeon/r600_audio.c -+++ b/drivers/gpu/drm/radeon/r600_audio.c +Index: linux-3.2.46/drivers/gpu/drm/radeon/r600_audio.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/radeon/r600_audio.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/radeon/r600_audio.c 2013-07-26 19:26:23.000000000 +0000 @@ -36,7 +36,7 @@ */ static int r600_audio_chipset_supported(struct radeon_device *rdev) @@ -80145,7 +80057,7 @@ || rdev->family == CHIP_RS600 || rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740; -@@ -161,8 +161,18 @@ static void r600_audio_update_hdmi(unsigned long param) +@@ -161,8 +161,18 @@ */ static void r600_audio_engine_enable(struct radeon_device *rdev, bool enable) { @@ -80165,7 +80077,7 @@ rdev->audio_enabled = enable; } -@@ -229,6 +239,7 @@ void r600_audio_set_clock(struct drm_encoder *encoder, int clock) +@@ -229,6 +239,7 @@ struct radeon_device *rdev = dev->dev_private; struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; @@ -80173,7 +80085,7 @@ int base_rate = 48000; switch (radeon_encoder->encoder_id) { -@@ -248,22 +259,33 @@ void r600_audio_set_clock(struct drm_encoder *encoder, int clock) +@@ -248,22 +259,33 @@ return; } @@ -80223,10 +80135,10 @@ } } -diff --git a/drivers/gpu/drm/radeon/r600_blit_kms.c b/drivers/gpu/drm/radeon/r600_blit_kms.c -index e09d281..db38f58 100644 ---- a/drivers/gpu/drm/radeon/r600_blit_kms.c -+++ b/drivers/gpu/drm/radeon/r600_blit_kms.c +Index: linux-3.2.46/drivers/gpu/drm/radeon/r600_blit_kms.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/radeon/r600_blit_kms.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/radeon/r600_blit_kms.c 2013-07-26 19:26:23.000000000 +0000 @@ -30,26 +30,14 @@ #include "r600d.h" @@ -80256,7 +80168,7 @@ u32 cb_color_info; int pitch, slice; -@@ -63,38 +51,38 @@ set_render_target(struct radeon_device *rdev, int format, +@@ -63,38 +51,38 @@ pitch = (w / 8) - 1; slice = ((w * h) / 64) - 1; @@ -80318,7 +80230,7 @@ } /* emits 5dw */ -@@ -103,6 +91,7 @@ cp_set_surface_sync(struct radeon_device *rdev, +@@ -103,6 +91,7 @@ u32 sync_type, u32 size, u64 mc_addr) { @@ -80326,7 +80238,7 @@ u32 cp_coher_size; if (size == 0xffffffff) -@@ -110,17 +99,18 @@ cp_set_surface_sync(struct radeon_device *rdev, +@@ -110,17 +99,18 @@ else cp_coher_size = ((size + 255) >> 8); @@ -80350,28 +80262,30 @@ u64 gpu_addr; u32 sq_pgm_resources; -@@ -129,35 +119,35 @@ set_shaders(struct radeon_device *rdev) +@@ -129,35 +119,35 @@ /* VS */ gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.vs_offset; - radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); - radeon_ring_write(rdev, (SQ_PGM_START_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); - radeon_ring_write(rdev, gpu_addr >> 8); -+ radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); -+ radeon_ring_write(ring, (SQ_PGM_START_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); -+ radeon_ring_write(ring, gpu_addr >> 8); - +- - radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); - radeon_ring_write(rdev, (SQ_PGM_RESOURCES_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); - radeon_ring_write(rdev, sq_pgm_resources); -+ radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); -+ radeon_ring_write(ring, (SQ_PGM_RESOURCES_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); -+ radeon_ring_write(ring, sq_pgm_resources); - +- - radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); - radeon_ring_write(rdev, (SQ_PGM_CF_OFFSET_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); - radeon_ring_write(rdev, 0); + radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); ++ radeon_ring_write(ring, (SQ_PGM_START_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); ++ radeon_ring_write(ring, gpu_addr >> 8); ++ ++ radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); ++ radeon_ring_write(ring, (SQ_PGM_RESOURCES_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); ++ radeon_ring_write(ring, sq_pgm_resources); ++ ++ radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); + radeon_ring_write(ring, (SQ_PGM_CF_OFFSET_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); + radeon_ring_write(ring, 0); @@ -80380,34 +80294,37 @@ - radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); - radeon_ring_write(rdev, (SQ_PGM_START_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); - radeon_ring_write(rdev, gpu_addr >> 8); -+ radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); -+ radeon_ring_write(ring, (SQ_PGM_START_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); -+ radeon_ring_write(ring, gpu_addr >> 8); - +- - radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); - radeon_ring_write(rdev, (SQ_PGM_RESOURCES_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); - radeon_ring_write(rdev, sq_pgm_resources | (1 << 28)); -+ radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); -+ radeon_ring_write(ring, (SQ_PGM_RESOURCES_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); -+ radeon_ring_write(ring, sq_pgm_resources | (1 << 28)); - +- - radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); - radeon_ring_write(rdev, (SQ_PGM_EXPORTS_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); - radeon_ring_write(rdev, 2); -+ radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); -+ radeon_ring_write(ring, (SQ_PGM_EXPORTS_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); -+ radeon_ring_write(ring, 2); - +- - radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); - radeon_ring_write(rdev, (SQ_PGM_CF_OFFSET_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); - radeon_ring_write(rdev, 0); + radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); ++ radeon_ring_write(ring, (SQ_PGM_START_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); ++ radeon_ring_write(ring, gpu_addr >> 8); ++ ++ radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); ++ radeon_ring_write(ring, (SQ_PGM_RESOURCES_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); ++ radeon_ring_write(ring, sq_pgm_resources | (1 << 28)); ++ ++ radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); ++ radeon_ring_write(ring, (SQ_PGM_EXPORTS_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); ++ radeon_ring_write(ring, 2); ++ ++ radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); + radeon_ring_write(ring, (SQ_PGM_CF_OFFSET_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); + radeon_ring_write(ring, 0); gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.vs_offset; cp_set_surface_sync(rdev, PACKET3_SH_ACTION_ENA, 512, gpu_addr); -@@ -167,6 +157,7 @@ set_shaders(struct radeon_device *rdev) +@@ -167,6 +157,7 @@ static void set_vtx_resource(struct radeon_device *rdev, u64 gpu_addr) { @@ -80415,7 +80332,7 @@ u32 sq_vtx_constant_word2; sq_vtx_constant_word2 = SQ_VTXC_BASE_ADDR_HI(upper_32_bits(gpu_addr) & 0xff) | -@@ -175,15 +166,15 @@ set_vtx_resource(struct radeon_device *rdev, u64 gpu_addr) +@@ -175,15 +166,15 @@ sq_vtx_constant_word2 |= SQ_VTXC_ENDIAN_SWAP(SQ_ENDIAN_8IN32); #endif @@ -80440,7 +80357,7 @@ if ((rdev->family == CHIP_RV610) || (rdev->family == CHIP_RV620) || -@@ -203,6 +194,7 @@ set_tex_resource(struct radeon_device *rdev, +@@ -203,6 +194,7 @@ int format, int w, int h, int pitch, u64 gpu_addr, u32 size) { @@ -80448,7 +80365,7 @@ uint32_t sq_tex_resource_word0, sq_tex_resource_word1, sq_tex_resource_word4; if (h < 1) -@@ -225,15 +217,15 @@ set_tex_resource(struct radeon_device *rdev, +@@ -225,15 +217,15 @@ cp_set_surface_sync(rdev, PACKET3_TC_ACTION_ENA, size, gpu_addr); @@ -80473,7 +80390,7 @@ } /* emits 12 */ -@@ -241,43 +233,45 @@ static void +@@ -241,43 +233,45 @@ set_scissors(struct radeon_device *rdev, int x1, int y1, int x2, int y2) { @@ -80543,7 +80460,7 @@ } -@@ -285,6 +279,7 @@ draw_auto(struct radeon_device *rdev) +@@ -285,6 +279,7 @@ static void set_default_state(struct radeon_device *rdev) { @@ -80551,7 +80468,7 @@ u32 sq_config, sq_gpr_resource_mgmt_1, sq_gpr_resource_mgmt_2; u32 sq_thread_resource_mgmt, sq_stack_resource_mgmt_1, sq_stack_resource_mgmt_2; int num_ps_gprs, num_vs_gprs, num_temp_gprs, num_gs_gprs, num_es_gprs; -@@ -440,47 +435,62 @@ set_default_state(struct radeon_device *rdev) +@@ -440,47 +435,62 @@ /* emit an IB pointing at default state */ dwords = ALIGN(rdev->r600_blit.state_len, 0x10); gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.state_offset; @@ -80577,6 +80494,8 @@ - radeon_ring_write(rdev, sq_thread_resource_mgmt); - radeon_ring_write(rdev, sq_stack_resource_mgmt_1); - radeon_ring_write(rdev, sq_stack_resource_mgmt_2); +-} +- + radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 6)); + radeon_ring_write(ring, (SQ_CONFIG - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); + radeon_ring_write(ring, sq_config); @@ -80585,8 +80504,8 @@ + radeon_ring_write(ring, sq_thread_resource_mgmt); + radeon_ring_write(ring, sq_stack_resource_mgmt_1); + radeon_ring_write(ring, sq_stack_resource_mgmt_2); - } - ++} ++ +#define I2F_MAX_BITS 15 +#define I2F_MAX_INPUT ((1 << I2F_MAX_BITS) - 1) +#define I2F_SHIFT (24 - I2F_MAX_BITS) @@ -80636,7 +80555,7 @@ } return result; } -@@ -611,16 +621,17 @@ void r600_blit_fini(struct radeon_device *rdev) +@@ -611,16 +621,17 @@ radeon_bo_unref(&rdev->r600_blit.shader_obj); } @@ -80657,7 +80576,7 @@ rdev->r600_blit.vb_used = 0; return 0; } -@@ -679,15 +690,12 @@ static unsigned r600_blit_create_rect(unsigned num_gpu_pages, +@@ -679,15 +690,12 @@ int r600_blit_prepare_copy(struct radeon_device *rdev, unsigned num_gpu_pages) { @@ -80674,7 +80593,7 @@ /* num loops */ while (num_gpu_pages) { num_gpu_pages -= -@@ -696,10 +704,15 @@ int r600_blit_prepare_copy(struct radeon_device *rdev, unsigned num_gpu_pages) +@@ -696,10 +704,15 @@ num_loops++; } @@ -80691,7 +80610,7 @@ if (r) return r; -@@ -718,7 +731,7 @@ void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence) +@@ -718,7 +731,7 @@ if (fence) r = radeon_fence_emit(rdev, fence); @@ -80700,10 +80619,10 @@ } void r600_kms_blit_copy(struct radeon_device *rdev, -diff --git a/drivers/gpu/drm/radeon/r600_blit_shaders.c b/drivers/gpu/drm/radeon/r600_blit_shaders.c -index 73e2c7c..34c8b23 100644 ---- a/drivers/gpu/drm/radeon/r600_blit_shaders.c -+++ b/drivers/gpu/drm/radeon/r600_blit_shaders.c +Index: linux-3.2.46/drivers/gpu/drm/radeon/r600_blit_shaders.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/radeon/r600_blit_shaders.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/radeon/r600_blit_shaders.c 2013-07-26 19:26:23.000000000 +0000 @@ -24,6 +24,7 @@ * Alex Deucher */ @@ -80712,11 +80631,11 @@ #include #include -diff --git a/drivers/gpu/drm/radeon/r600_cp.c b/drivers/gpu/drm/radeon/r600_cp.c -index c9db493..75ed17c 100644 ---- a/drivers/gpu/drm/radeon/r600_cp.c -+++ b/drivers/gpu/drm/radeon/r600_cp.c -@@ -407,7 +407,7 @@ static void r600_cp_load_microcode(drm_radeon_private_t *dev_priv) +Index: linux-3.2.46/drivers/gpu/drm/radeon/r600_cp.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/radeon/r600_cp.c 2013-07-26 19:25:21.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/radeon/r600_cp.c 2013-07-26 19:26:23.000000000 +0000 +@@ -403,7 +403,7 @@ RADEON_WRITE(R600_GRBM_SOFT_RESET, R600_SOFT_RESET_CP); RADEON_READ(R600_GRBM_SOFT_RESET); @@ -80725,7 +80644,7 @@ RADEON_WRITE(R600_GRBM_SOFT_RESET, 0); fw_data = (const __be32 *)dev_priv->me_fw->data; -@@ -500,7 +500,7 @@ static void r700_cp_load_microcode(drm_radeon_private_t *dev_priv) +@@ -496,7 +496,7 @@ RADEON_WRITE(R600_GRBM_SOFT_RESET, R600_SOFT_RESET_CP); RADEON_READ(R600_GRBM_SOFT_RESET); @@ -80734,7 +80653,7 @@ RADEON_WRITE(R600_GRBM_SOFT_RESET, 0); fw_data = (const __be32 *)dev_priv->pfp_fw->data; -@@ -1797,7 +1797,7 @@ static void r600_cp_init_ring_buffer(struct drm_device *dev, +@@ -1793,7 +1793,7 @@ RADEON_WRITE(R600_GRBM_SOFT_RESET, R600_SOFT_RESET_CP); RADEON_READ(R600_GRBM_SOFT_RESET); @@ -80743,7 +80662,7 @@ RADEON_WRITE(R600_GRBM_SOFT_RESET, 0); -@@ -1815,7 +1815,7 @@ static void r600_cp_init_ring_buffer(struct drm_device *dev, +@@ -1811,7 +1811,7 @@ dev_priv->ring.size_l2qw); #endif @@ -80752,11 +80671,11 @@ /* Set the write pointer delay */ RADEON_WRITE(R600_CP_RB_WPTR_DELAY, 0); -diff --git a/drivers/gpu/drm/radeon/r600_cs.c b/drivers/gpu/drm/radeon/r600_cs.c -index cb1acff..b8e12af 100644 ---- a/drivers/gpu/drm/radeon/r600_cs.c -+++ b/drivers/gpu/drm/radeon/r600_cs.c -@@ -52,15 +52,20 @@ struct r600_cs_track { +Index: linux-3.2.46/drivers/gpu/drm/radeon/r600_cs.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/radeon/r600_cs.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/radeon/r600_cs.c 2013-07-26 19:26:24.000000000 +0000 +@@ -52,15 +52,20 @@ struct radeon_bo *cb_color_bo[8]; u64 cb_color_bo_mc[8]; u32 cb_color_bo_offset[8]; @@ -80781,7 +80700,7 @@ u32 db_depth_control; u32 db_depth_info; u32 db_depth_size_idx; -@@ -69,13 +74,20 @@ struct r600_cs_track { +@@ -69,13 +74,20 @@ u32 db_offset; struct radeon_bo *db_bo; u64 db_bo_mc; @@ -80804,7 +80723,7 @@ #define FMT_64_BIT(fmt, vc) [fmt] = { 1, 1, 8, vc, CHIP_R600 } #define FMT_96_BIT(fmt) [fmt] = { 1, 1, 12, 0, CHIP_R600 } #define FMT_128_BIT(fmt, vc) [fmt] = { 1, 1, 16,vc, CHIP_R600 } -@@ -107,7 +119,7 @@ static const struct gpu_formats color_formats_table[] = { +@@ -107,7 +119,7 @@ /* 24-bit */ FMT_24_BIT(V_038004_FMT_8_8_8), @@ -80813,7 +80732,7 @@ /* 32-bit */ FMT_32_BIT(V_038004_COLOR_32, 1), FMT_32_BIT(V_038004_COLOR_32_FLOAT, 1), -@@ -162,22 +174,22 @@ static const struct gpu_formats color_formats_table[] = { +@@ -162,22 +174,22 @@ [V_038004_FMT_32_AS_32_32_32_32] = { 1, 1, 4, 0, CHIP_CEDAR}, }; @@ -80840,7 +80759,7 @@ if (family < color_formats_table[format].min_family) return false; -@@ -187,7 +199,7 @@ static bool fmt_is_valid_texture(u32 format, enum radeon_family family) +@@ -187,7 +199,7 @@ return false; } @@ -80849,7 +80768,7 @@ { if (format >= ARRAY_SIZE(color_formats_table)) return 0; -@@ -195,7 +207,7 @@ static int fmt_get_blocksize(u32 format) +@@ -195,7 +207,7 @@ return color_formats_table[format].blocksize; } @@ -80858,7 +80777,7 @@ { unsigned bw; -@@ -209,7 +221,7 @@ static int fmt_get_nblocksx(u32 format, u32 w) +@@ -209,7 +221,7 @@ return (w + bw - 1) / bw; } @@ -80867,7 +80786,7 @@ { unsigned bh; -@@ -256,7 +268,7 @@ static int r600_get_array_mode_alignment(struct array_mode_checker *values, +@@ -256,7 +268,7 @@ break; case ARRAY_LINEAR_ALIGNED: *pitch_align = max((u32)64, (u32)(values->group_size / values->blocksize)); @@ -80876,7 +80795,7 @@ *depth_align = 1; *base_align = values->group_size; break; -@@ -269,10 +281,9 @@ static int r600_get_array_mode_alignment(struct array_mode_checker *values, +@@ -269,10 +281,9 @@ *base_align = values->group_size; break; case ARRAY_2D_TILED_THIN1: @@ -80890,7 +80809,7 @@ *height_align = macro_tile_height * tile_height; *depth_align = 1; *base_align = max(macro_tile_bytes, -@@ -296,12 +307,14 @@ static void r600_cs_track_init(struct r600_cs_track *track) +@@ -296,12 +307,14 @@ track->cb_color_size[i] = 0; track->cb_color_size_idx[i] = 0; track->cb_color_info[i] = 0; @@ -80905,7 +80824,7 @@ track->db_bo = NULL; track->db_bo_mc = 0xFFFFFFFF; /* assume the biggest format and that htile is enabled */ -@@ -310,6 +323,19 @@ static void r600_cs_track_init(struct r600_cs_track *track) +@@ -310,6 +323,19 @@ track->db_depth_size = 0xFFFFFFFF; track->db_depth_size_idx = 0; track->db_depth_control = 0xFFFFFFFF; @@ -80925,7 +80844,7 @@ } static int r600_cs_track_validate_cb(struct radeon_cs_parser *p, int i) -@@ -322,13 +348,14 @@ static int r600_cs_track_validate_cb(struct radeon_cs_parser *p, int i) +@@ -322,13 +348,14 @@ volatile u32 *ib = p->ib->ptr; unsigned array_mode; u32 format; @@ -80941,7 +80860,7 @@ dev_warn(p->dev, "%s:%d cb invalid format %d for %d (0x%08X)\n", __func__, __LINE__, format, i, track->cb_color_info[i]); -@@ -349,7 +376,7 @@ static int r600_cs_track_validate_cb(struct radeon_cs_parser *p, int i) +@@ -349,7 +376,7 @@ array_check.nbanks = track->nbanks; array_check.npipes = track->npipes; array_check.nsamples = track->nsamples; @@ -80950,7 +80869,7 @@ if (r600_get_array_mode_alignment(&array_check, &pitch_align, &height_align, &depth_align, &base_align)) { dev_warn(p->dev, "%s invalid tiling %d for %d (0x%08X)\n", __func__, -@@ -393,7 +420,18 @@ static int r600_cs_track_validate_cb(struct radeon_cs_parser *p, int i) +@@ -393,7 +420,18 @@ } /* check offset */ @@ -80970,7 +80889,7 @@ if ((tmp + track->cb_color_bo_offset[i]) > radeon_bo_size(track->cb_color_bo[i])) { if (array_mode == V_0280A0_ARRAY_LINEAR_GENERAL) { /* the initial DDX does bad things with the CB size occasionally */ -@@ -403,10 +441,13 @@ static int r600_cs_track_validate_cb(struct radeon_cs_parser *p, int i) +@@ -403,10 +441,13 @@ * broken userspace. */ } else { @@ -80987,7 +80906,7 @@ return -EINVAL; } } -@@ -420,154 +461,316 @@ static int r600_cs_track_validate_cb(struct radeon_cs_parser *p, int i) +@@ -420,154 +461,316 @@ return 0; } @@ -81060,34 +80979,19 @@ - u64 base_offset, base_align; - struct array_mode_checker array_check; - int array_mode; -- -- if (track->db_bo == NULL) { -- dev_warn(p->dev, "z/stencil with no depth buffer\n"); + if ((track->db_depth_size & 0xFFFFFC00) == 0xFFFFFC00) { + if (!track->db_depth_size_idx) { + dev_warn(p->dev, "z/stencil buffer size not set\n"); - return -EINVAL; - } -- if (G_028010_TILE_SURFACE_ENABLE(track->db_depth_info)) { -- dev_warn(p->dev, "this kernel doesn't support z/stencil htile\n"); ++ return -EINVAL; ++ } + tmp = radeon_bo_size(track->db_bo) - track->db_offset; + tmp = (tmp / bpe) >> 6; + if (!tmp) { + dev_warn(p->dev, "z/stencil buffer too small (0x%08X %d %d %ld)\n", + track->db_depth_size, bpe, track->db_offset, + radeon_bo_size(track->db_bo)); - return -EINVAL; - } -- switch (G_028010_FORMAT(track->db_depth_info)) { -- case V_028010_DEPTH_16: -- bpe = 2; -- break; -- case V_028010_DEPTH_X8_24: -- case V_028010_DEPTH_8_24: -- case V_028010_DEPTH_X8_24_FLOAT: -- case V_028010_DEPTH_8_24_FLOAT: -- case V_028010_DEPTH_32_FLOAT: -- bpe = 4; ++ return -EINVAL; ++ } + ib[track->db_depth_size_idx] = S_028000_SLICE_TILE_MAX(tmp - 1) | (track->db_depth_size & 0x3FF); + } else { + size = radeon_bo_size(track->db_bo); @@ -81117,29 +81021,46 @@ + case V_028010_ARRAY_1D_TILED_THIN1: + /* don't break userspace */ + height &= ~0x7; - break; -- case V_028010_DEPTH_X24_8_32_FLOAT: -- bpe = 8; ++ break; + case V_028010_ARRAY_2D_TILED_THIN1: - break; - default: -- dev_warn(p->dev, "z/stencil with invalid format %d\n", G_028010_FORMAT(track->db_depth_info)); ++ break; ++ default: + dev_warn(p->dev, "%s invalid tiling %d (0x%08X)\n", __func__, + G_028010_ARRAY_MODE(track->db_depth_info), + track->db_depth_info); + return -EINVAL; + } -+ + +- if (track->db_bo == NULL) { +- dev_warn(p->dev, "z/stencil with no depth buffer\n"); + if (!IS_ALIGNED(pitch, pitch_align)) { + dev_warn(p->dev, "%s:%d db pitch (%d, 0x%x, %d) invalid\n", + __func__, __LINE__, pitch, pitch_align, array_mode); -+ return -EINVAL; -+ } + return -EINVAL; + } +- if (G_028010_TILE_SURFACE_ENABLE(track->db_depth_info)) { +- dev_warn(p->dev, "this kernel doesn't support z/stencil htile\n"); + if (!IS_ALIGNED(height, height_align)) { + dev_warn(p->dev, "%s:%d db height (%d, 0x%x, %d) invalid\n", + __func__, __LINE__, height, height_align, array_mode); -+ return -EINVAL; -+ } + return -EINVAL; + } +- switch (G_028010_FORMAT(track->db_depth_info)) { +- case V_028010_DEPTH_16: +- bpe = 2; +- break; +- case V_028010_DEPTH_X8_24: +- case V_028010_DEPTH_8_24: +- case V_028010_DEPTH_X8_24_FLOAT: +- case V_028010_DEPTH_8_24_FLOAT: +- case V_028010_DEPTH_32_FLOAT: +- bpe = 4; +- break; +- case V_028010_DEPTH_X24_8_32_FLOAT: +- bpe = 8; +- break; +- default: +- dev_warn(p->dev, "z/stencil with invalid format %d\n", G_028010_FORMAT(track->db_depth_info)); + if (!IS_ALIGNED(base_offset, base_align)) { + dev_warn(p->dev, "%s offset 0x%llx, 0x%llx, %d not aligned\n", __func__, + base_offset, base_align, array_mode); @@ -81246,7 +81167,8 @@ + default: + return -EINVAL; + } -+ break; + break; +- case V_028010_ARRAY_2D_TILED_THIN1: + case 4: + switch (tmp) { + case 3: /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 8*/ @@ -81284,8 +81206,7 @@ + default: + return -EINVAL; + } - break; -- case V_028010_ARRAY_2D_TILED_THIN1: ++ break; + case 1: + switch (tmp) { + case 3: /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 8*/ @@ -81319,14 +81240,6 @@ + nby = G_028D24_HTILE_HEIGHT(track->htile_surface) ? nby / 8 : nby / 4; + size = nbx * nby * 4; + size += track->htile_offset; -+ -+ if (size > radeon_bo_size(track->htile_bo)) { -+ dev_warn(p->dev, "%s:%d htile surface too small %ld for %ld (%d %d)\n", -+ __func__, __LINE__, radeon_bo_size(track->htile_bo), -+ size, nbx, nby); -+ return -EINVAL; -+ } -+ } - if (!IS_ALIGNED(pitch, pitch_align)) { - dev_warn(p->dev, "%s:%d db pitch (%d, 0x%x, %d) invalid\n", @@ -81342,6 +81255,14 @@ - dev_warn(p->dev, "%s offset[%d] 0x%llx, 0x%llx, %d not aligned\n", __func__, i, - base_offset, base_align, array_mode); - return -EINVAL; ++ if (size > radeon_bo_size(track->htile_bo)) { ++ dev_warn(p->dev, "%s:%d htile surface too small %ld for %ld (%d %d)\n", ++ __func__, __LINE__, radeon_bo_size(track->htile_bo), ++ size, nbx, nby); ++ return -EINVAL; ++ } ++ } ++ + track->db_dirty = false; + return 0; +} @@ -81423,7 +81344,7 @@ return 0; } -@@ -939,9 +1142,10 @@ static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) +@@ -939,9 +1142,10 @@ break; case R_028800_DB_DEPTH_CONTROL: track->db_depth_control = radeon_get_ib_value(p, idx); @@ -81435,7 +81356,7 @@ r600_cs_packet_next_is_pkt3_nop(p)) { r = r600_cs_packet_next_reloc(p, &reloc); if (r) { -@@ -959,24 +1163,66 @@ static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) +@@ -959,24 +1163,66 @@ ib[idx] |= S_028010_ARRAY_MODE(V_028010_ARRAY_1D_TILED_THIN1); track->db_depth_info |= S_028010_ARRAY_MODE(V_028010_ARRAY_1D_TILED_THIN1); } @@ -81503,7 +81424,7 @@ break; case R_02823C_CB_SHADER_MASK: track->cb_shader_mask = radeon_get_ib_value(p, idx); -@@ -984,6 +1230,7 @@ static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) +@@ -984,6 +1230,7 @@ case R_028C04_PA_SC_AA_CONFIG: tmp = G_028C04_MSAA_NUM_SAMPLES(radeon_get_ib_value(p, idx)); track->nsamples = 1 << tmp; @@ -81511,7 +81432,7 @@ break; case R_0280A0_CB_COLOR0_INFO: case R_0280A4_CB_COLOR1_INFO: -@@ -993,7 +1240,7 @@ static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) +@@ -993,7 +1240,7 @@ case R_0280B4_CB_COLOR5_INFO: case R_0280B8_CB_COLOR6_INFO: case R_0280BC_CB_COLOR7_INFO: @@ -81520,7 +81441,7 @@ r600_cs_packet_next_is_pkt3_nop(p)) { r = r600_cs_packet_next_reloc(p, &reloc); if (r) { -@@ -1013,6 +1260,19 @@ static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) +@@ -1013,6 +1260,19 @@ tmp = (reg - R_0280A0_CB_COLOR0_INFO) / 4; track->cb_color_info[tmp] = radeon_get_ib_value(p, idx); } @@ -81540,7 +81461,7 @@ break; case R_028060_CB_COLOR0_SIZE: case R_028064_CB_COLOR1_SIZE: -@@ -1025,6 +1285,7 @@ static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) +@@ -1025,6 +1285,7 @@ tmp = (reg - R_028060_CB_COLOR0_SIZE) / 4; track->cb_color_size[tmp] = radeon_get_ib_value(p, idx); track->cb_color_size_idx[tmp] = idx; @@ -81548,7 +81469,7 @@ break; /* This register were added late, there is userspace * which does provide relocation for those but set -@@ -1107,6 +1368,7 @@ static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) +@@ -1107,6 +1368,7 @@ track->cb_color_base_last[tmp] = ib[idx]; track->cb_color_bo[tmp] = reloc->robj; track->cb_color_bo_mc[tmp] = reloc->lobj.gpu_offset; @@ -81556,7 +81477,7 @@ break; case DB_DEPTH_BASE: r = r600_cs_packet_next_reloc(p, &reloc); -@@ -1119,8 +1381,24 @@ static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) +@@ -1119,8 +1381,24 @@ ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); track->db_bo = reloc->robj; track->db_bo_mc = reloc->lobj.gpu_offset; @@ -81581,7 +81502,7 @@ case SQ_PGM_START_FS: case SQ_PGM_START_ES: case SQ_PGM_START_VS: -@@ -1191,6 +1469,9 @@ static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) +@@ -1191,6 +1469,9 @@ } ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); break; @@ -81591,7 +81512,7 @@ default: dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx); return -EINVAL; -@@ -1198,7 +1479,7 @@ static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx) +@@ -1198,7 +1479,7 @@ return 0; } @@ -81600,7 +81521,7 @@ { unsigned val; -@@ -1220,22 +1501,22 @@ static void r600_texture_size(unsigned nfaces, unsigned blevel, unsigned llevel, +@@ -1220,22 +1501,22 @@ unsigned nlevels = llevel - blevel + 1; *l0_size = -1; @@ -81632,7 +81553,7 @@ size = nbx * nby * blocksize; if (nfaces) -@@ -1293,7 +1574,7 @@ static int r600_check_texture_resource(struct radeon_cs_parser *p, u32 idx, +@@ -1293,7 +1574,7 @@ mip_offset <<= 8; word0 = radeon_get_ib_value(p, idx + 0); @@ -81641,7 +81562,7 @@ if (tiling_flags & RADEON_TILING_MACRO) word0 |= S_038000_TILE_MODE(V_038000_ARRAY_2D_TILED_THIN1); else if (tiling_flags & RADEON_TILING_MICRO) -@@ -1304,6 +1585,7 @@ static int r600_check_texture_resource(struct radeon_cs_parser *p, u32 idx, +@@ -1304,6 +1585,7 @@ h0 = G_038004_TEX_HEIGHT(word1) + 1; d0 = G_038004_TEX_DEPTH(word1); nfaces = 1; @@ -81649,7 +81570,7 @@ switch (G_038000_DIM(word0)) { case V_038000_SQ_TEX_DIM_1D: case V_038000_SQ_TEX_DIM_2D: -@@ -1326,7 +1608,7 @@ static int r600_check_texture_resource(struct radeon_cs_parser *p, u32 idx, +@@ -1326,7 +1608,7 @@ return -EINVAL; } format = G_038004_DATA_FORMAT(word1); @@ -81658,7 +81579,7 @@ dev_warn(p->dev, "%s:%d texture invalid format %d\n", __func__, __LINE__, format); return -EINVAL; -@@ -1339,7 +1621,7 @@ static int r600_check_texture_resource(struct radeon_cs_parser *p, u32 idx, +@@ -1339,7 +1621,7 @@ array_check.nbanks = track->nbanks; array_check.npipes = track->npipes; array_check.nsamples = 1; @@ -81667,7 +81588,7 @@ if (r600_get_array_mode_alignment(&array_check, &pitch_align, &height_align, &depth_align, &base_align)) { dev_warn(p->dev, "%s:%d tex array mode (%d) invalid\n", -@@ -1372,6 +1654,10 @@ static int r600_check_texture_resource(struct radeon_cs_parser *p, u32 idx, +@@ -1372,6 +1654,10 @@ word1 = radeon_get_ib_value(p, idx + 5); blevel = G_038010_BASE_LEVEL(word0); llevel = G_038014_LAST_LEVEL(word1); @@ -81678,7 +81599,7 @@ if (array == 1) { barray = G_038014_BASE_ARRAY(word1); larray = G_038014_LAST_ARRAY(word1); -@@ -1383,8 +1669,10 @@ static int r600_check_texture_resource(struct radeon_cs_parser *p, u32 idx, +@@ -1383,8 +1669,10 @@ &l0_size, &mipmap_size); /* using get ib will give us the offset into the texture bo */ if ((l0_size + word2) > radeon_bo_size(texture)) { @@ -81691,7 +81612,7 @@ dev_warn(p->dev, "alignments %d %d %d %lld\n", pitch, pitch_align, height_align, base_align); return -EINVAL; } -@@ -1397,6 +1685,22 @@ static int r600_check_texture_resource(struct radeon_cs_parser *p, u32 idx, +@@ -1397,6 +1685,22 @@ return 0; } @@ -81714,7 +81635,7 @@ static int r600_packet3_check(struct radeon_cs_parser *p, struct radeon_cs_packet *pkt) { -@@ -1419,6 +1723,8 @@ static int r600_packet3_check(struct radeon_cs_parser *p, +@@ -1419,6 +1723,8 @@ { int pred_op; int tmp; @@ -81723,7 +81644,7 @@ if (pkt->count != 1) { DRM_ERROR("bad SET PREDICATION\n"); return -EINVAL; -@@ -1442,8 +1748,12 @@ static int r600_packet3_check(struct radeon_cs_parser *p, +@@ -1442,8 +1748,12 @@ return -EINVAL; } @@ -81738,7 +81659,7 @@ } break; -@@ -1467,6 +1777,8 @@ static int r600_packet3_check(struct radeon_cs_parser *p, +@@ -1467,6 +1777,8 @@ } break; case PACKET3_DRAW_INDEX: @@ -81747,7 +81668,7 @@ if (pkt->count != 3) { DRM_ERROR("bad DRAW_INDEX\n"); return -EINVAL; -@@ -1476,14 +1788,21 @@ static int r600_packet3_check(struct radeon_cs_parser *p, +@@ -1476,14 +1788,21 @@ DRM_ERROR("bad DRAW_INDEX\n"); return -EINVAL; } @@ -81771,7 +81692,7 @@ case PACKET3_DRAW_INDEX_AUTO: if (pkt->count != 1) { DRM_ERROR("bad DRAW_INDEX_AUTO\n"); -@@ -1514,13 +1833,20 @@ static int r600_packet3_check(struct radeon_cs_parser *p, +@@ -1514,13 +1833,20 @@ } /* bit 4 is reg (0) or mem (1) */ if (idx_value & 0x10) { @@ -81794,7 +81715,7 @@ } break; case PACKET3_SURFACE_SYNC: -@@ -1545,16 +1871,25 @@ static int r600_packet3_check(struct radeon_cs_parser *p, +@@ -1545,16 +1871,25 @@ return -EINVAL; } if (pkt->count) { @@ -81822,7 +81743,7 @@ if (pkt->count != 4) { DRM_ERROR("bad EVENT_WRITE_EOP\n"); return -EINVAL; -@@ -1564,9 +1899,15 @@ static int r600_packet3_check(struct radeon_cs_parser *p, +@@ -1564,9 +1899,15 @@ DRM_ERROR("bad EVENT_WRITE\n"); return -EINVAL; } @@ -81840,7 +81761,7 @@ case PACKET3_SET_CONFIG_REG: start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_OFFSET; end_reg = 4 * pkt->count + start_reg - 4; -@@ -1625,7 +1966,7 @@ static int r600_packet3_check(struct radeon_cs_parser *p, +@@ -1625,7 +1966,7 @@ return -EINVAL; } base_offset = (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff); @@ -81849,7 +81770,7 @@ if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) ib[idx+1+(i*7)+0] |= S_038000_TILE_MODE(V_038000_ARRAY_2D_TILED_THIN1); else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) -@@ -1651,6 +1992,8 @@ static int r600_packet3_check(struct radeon_cs_parser *p, +@@ -1651,6 +1992,8 @@ ib[idx+1+(i*7)+3] += mip_offset; break; case SQ_TEX_VTX_VALID_BUFFER: @@ -81858,7 +81779,7 @@ /* vtx base */ r = r600_cs_packet_next_reloc(p, &reloc); if (r) { -@@ -1663,11 +2006,15 @@ static int r600_packet3_check(struct radeon_cs_parser *p, +@@ -1663,11 +2006,15 @@ /* force size to size of the buffer */ dev_warn(p->dev, "vbo resource seems too big (%d) for the bo (%ld)\n", size + offset, radeon_bo_size(reloc->robj)); @@ -81877,7 +81798,7 @@ case SQ_TEX_VTX_INVALID_TEXTURE: case SQ_TEX_VTX_INVALID_BUFFER: default: -@@ -1742,6 +2089,104 @@ static int r600_packet3_check(struct radeon_cs_parser *p, +@@ -1742,6 +2089,104 @@ return -EINVAL; } break; @@ -81982,11 +81903,11 @@ case PACKET3_NOP: break; default: -diff --git a/drivers/gpu/drm/radeon/r600_hdmi.c b/drivers/gpu/drm/radeon/r600_hdmi.c -index 57a825d..0b59206 100644 ---- a/drivers/gpu/drm/radeon/r600_hdmi.c -+++ b/drivers/gpu/drm/radeon/r600_hdmi.c -@@ -320,7 +320,7 @@ void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mod +Index: linux-3.2.46/drivers/gpu/drm/radeon/r600_hdmi.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/radeon/r600_hdmi.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/radeon/r600_hdmi.c 2013-07-26 19:26:24.000000000 +0000 +@@ -320,7 +320,7 @@ struct radeon_device *rdev = dev->dev_private; uint32_t offset = to_radeon_encoder(encoder)->hdmi_offset; @@ -81995,7 +81916,7 @@ return; if (!offset) -@@ -462,13 +462,31 @@ static void r600_hdmi_assign_block(struct drm_encoder *encoder) +@@ -462,13 +462,31 @@ struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; @@ -82028,7 +81949,7 @@ } else if (ASIC_IS_DCE3(rdev)) { radeon_encoder->hdmi_offset = dig->dig_encoder ? R600_HDMI_BLOCK3 : R600_HDMI_BLOCK1; -@@ -491,7 +509,7 @@ void r600_hdmi_enable(struct drm_encoder *encoder) +@@ -491,7 +509,7 @@ struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); uint32_t offset; @@ -82037,7 +81958,7 @@ return; if (!radeon_encoder->hdmi_offset) { -@@ -504,16 +522,24 @@ void r600_hdmi_enable(struct drm_encoder *encoder) +@@ -504,16 +522,24 @@ } offset = radeon_encoder->hdmi_offset; @@ -82066,7 +81987,7 @@ WREG32(offset + R600_HDMI_ENABLE, 0x105); break; default: -@@ -525,8 +551,8 @@ void r600_hdmi_enable(struct drm_encoder *encoder) +@@ -525,8 +551,8 @@ if (rdev->irq.installed && rdev->family != CHIP_RS600 && rdev->family != CHIP_RS690 @@ -82077,7 +81998,7 @@ /* if irq is available use it */ rdev->irq.hdmi[offset == R600_HDMI_BLOCK1 ? 0 : 1] = true; radeon_irq_set(rdev); -@@ -551,7 +577,7 @@ void r600_hdmi_disable(struct drm_encoder *encoder) +@@ -551,7 +577,7 @@ struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); uint32_t offset; @@ -82086,7 +82007,7 @@ return; offset = radeon_encoder->hdmi_offset; -@@ -570,16 +596,22 @@ void r600_hdmi_disable(struct drm_encoder *encoder) +@@ -570,16 +596,22 @@ /* disable polling */ r600_audio_disable_polling(encoder); @@ -82113,10 +82034,10 @@ WREG32(offset + R600_HDMI_ENABLE, 0); break; default: -diff --git a/drivers/gpu/drm/radeon/r600d.h b/drivers/gpu/drm/radeon/r600d.h -index d4d23a8d..12ceb82 100644 ---- a/drivers/gpu/drm/radeon/r600d.h -+++ b/drivers/gpu/drm/radeon/r600d.h +Index: linux-3.2.46/drivers/gpu/drm/radeon/r600d.h +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/radeon/r600d.h 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/radeon/r600d.h 2013-07-26 19:26:24.000000000 +0000 @@ -78,6 +78,20 @@ #define CB_COLOR0_SIZE 0x28060 @@ -82188,11 +82109,11 @@ #define PACKET3_WAIT_REG_MEM 0x3C #define PACKET3_MEM_WRITE 0x3D #define PACKET3_INDIRECT_BUFFER 0x32 -diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h -index 28e69e9..66150f0 100644 ---- a/drivers/gpu/drm/radeon/radeon.h -+++ b/drivers/gpu/drm/radeon/radeon.h -@@ -107,6 +107,21 @@ extern int radeon_msi; +Index: linux-3.2.46/drivers/gpu/drm/radeon/radeon.h +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/radeon/radeon.h 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/radeon/radeon.h 2013-07-26 19:26:24.000000000 +0000 +@@ -107,6 +107,21 @@ #define RADEONFB_CONN_LIMIT 4 #define RADEON_BIOS_NUM_SCRATCH 8 @@ -82214,7 +82135,7 @@ /* * Errata workarounds. */ -@@ -127,6 +142,47 @@ bool radeon_get_bios(struct radeon_device *rdev); +@@ -127,6 +142,47 @@ /* @@ -82262,7 +82183,7 @@ * Dummy page */ struct radeon_dummy_page { -@@ -165,26 +221,30 @@ void radeon_pm_resume(struct radeon_device *rdev); +@@ -165,26 +221,30 @@ void radeon_combios_get_power_modes(struct radeon_device *rdev); void radeon_atombios_get_power_modes(struct radeon_device *rdev); void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type); @@ -82296,7 +82217,7 @@ struct list_head signaled; bool initialized; }; -@@ -195,21 +255,26 @@ struct radeon_fence { +@@ -195,21 +255,26 @@ struct list_head list; /* protected by radeon_fence.lock */ uint32_t seq; @@ -82328,7 +82249,7 @@ /* * Tiling registers -@@ -231,6 +296,21 @@ struct radeon_mman { +@@ -231,6 +296,21 @@ bool initialized; }; @@ -82350,7 +82271,7 @@ struct radeon_bo { /* Protected by gem.mutex */ struct list_head list; -@@ -244,6 +324,10 @@ struct radeon_bo { +@@ -244,6 +324,10 @@ u32 tiling_flags; u32 pitch; int surface_reg; @@ -82361,7 +82282,7 @@ /* Constant after initialization */ struct radeon_device *rdev; struct drm_gem_object gem_base; -@@ -259,6 +343,48 @@ struct radeon_bo_list { +@@ -259,6 +343,48 @@ u32 tiling_flags; }; @@ -82410,7 +82331,7 @@ /* * GEM objects. */ -@@ -273,9 +399,6 @@ int radeon_gem_object_create(struct radeon_device *rdev, int size, +@@ -273,9 +399,6 @@ int alignment, int initial_domain, bool discardable, bool kernel, struct drm_gem_object **obj); @@ -82420,7 +82341,7 @@ int radeon_mode_dumb_create(struct drm_file *file_priv, struct drm_device *dev, -@@ -288,6 +411,46 @@ int radeon_mode_dumb_destroy(struct drm_file *file_priv, +@@ -288,6 +411,46 @@ uint32_t handle); /* @@ -82467,7 +82388,7 @@ * GART structures, functions & helpers */ struct radeon_mc; -@@ -295,6 +458,7 @@ struct radeon_mc; +@@ -295,6 +458,7 @@ #define RADEON_GPU_PAGE_SIZE 4096 #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1) #define RADEON_GPU_PAGE_SHIFT 12 @@ -82475,7 +82396,7 @@ struct radeon_gart { dma_addr_t table_addr; -@@ -305,7 +469,6 @@ struct radeon_gart { +@@ -305,7 +469,6 @@ unsigned table_size; struct page **pages; dma_addr_t *pages_addr; @@ -82483,7 +82404,7 @@ bool ready; }; -@@ -419,7 +582,7 @@ union radeon_irq_stat_regs { +@@ -419,7 +582,7 @@ struct radeon_irq { bool installed; @@ -82492,7 +82413,7 @@ bool crtc_vblank_int[RADEON_MAX_CRTCS]; bool pflip[RADEON_MAX_CRTCS]; wait_queue_head_t vblank_queue; -@@ -429,7 +592,7 @@ struct radeon_irq { +@@ -429,7 +592,7 @@ wait_queue_head_t idle_queue; bool hdmi[RADEON_MAX_HDMI_BLOCKS]; spinlock_t sw_lock; @@ -82501,7 +82422,7 @@ union radeon_irq_stat_regs stat_regs; spinlock_t pflip_lock[RADEON_MAX_CRTCS]; int pflip_refcount[RADEON_MAX_CRTCS]; -@@ -437,22 +600,24 @@ struct radeon_irq { +@@ -437,22 +600,24 @@ int radeon_irq_kms_init(struct radeon_device *rdev); void radeon_irq_kms_fini(struct radeon_device *rdev); @@ -82533,7 +82454,7 @@ }; /* -@@ -460,20 +625,22 @@ struct radeon_ib { +@@ -460,20 +625,22 @@ * mutex protects scheduled_ibs, ready, alloc_bm */ struct radeon_ib_pool { @@ -82563,7 +82484,7 @@ unsigned ring_size; unsigned ring_free_dw; int count_dw; -@@ -482,6 +649,61 @@ struct radeon_cp { +@@ -482,6 +649,61 @@ uint32_t ptr_mask; struct mutex mutex; bool ready; @@ -82625,7 +82546,7 @@ }; /* -@@ -491,6 +713,7 @@ struct r600_ih { +@@ -491,6 +713,7 @@ struct radeon_bo *ring_obj; volatile uint32_t *ring; unsigned rptr; @@ -82633,7 +82554,7 @@ unsigned wptr; unsigned wptr_old; unsigned ring_size; -@@ -534,23 +757,40 @@ struct r600_blit { +@@ -534,23 +757,40 @@ void r600_blit_suspend(struct radeon_device *rdev); @@ -82686,7 +82607,7 @@ /* -@@ -567,12 +807,12 @@ struct radeon_cs_reloc { +@@ -567,12 +807,12 @@ struct radeon_cs_chunk { uint32_t chunk_id; uint32_t length_dw; @@ -82704,7 +82625,7 @@ }; struct radeon_cs_parser { -@@ -593,11 +833,16 @@ struct radeon_cs_parser { +@@ -593,11 +833,16 @@ /* indices of various chunks */ int chunk_ib_idx; int chunk_relocs_idx; @@ -82722,7 +82643,7 @@ }; extern int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx); -@@ -733,6 +978,7 @@ enum radeon_int_thermal_type { +@@ -733,6 +978,7 @@ THERMAL_TYPE_EVERGREEN, THERMAL_TYPE_SUMO, THERMAL_TYPE_NI, @@ -82730,7 +82651,7 @@ }; struct radeon_voltage { -@@ -854,11 +1100,20 @@ void radeon_benchmark(struct radeon_device *rdev, int test_number); +@@ -854,11 +1100,20 @@ * Testing */ void radeon_test_moves(struct radeon_device *rdev); @@ -82751,7 +82672,7 @@ int radeon_debugfs_add_files(struct radeon_device *rdev, struct drm_info_list *files, unsigned nfiles); -@@ -874,53 +1129,8 @@ struct radeon_asic { +@@ -874,53 +1129,8 @@ int (*resume)(struct radeon_device *rdev); int (*suspend)(struct radeon_device *rdev); void (*vga_set_state)(struct radeon_device *rdev, bool state); @@ -82806,7 +82727,7 @@ /* ioctl hw specific callback. Some hw might want to perform special * operation on specific ioctl. For instance on wait idle some hw * might want to perform and HDP flush through MMIO as it seems that -@@ -928,17 +1138,99 @@ struct radeon_asic { +@@ -928,17 +1138,99 @@ * through ring. */ void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo); @@ -82914,7 +82835,7 @@ }; /* -@@ -1078,6 +1370,37 @@ struct cayman_asic { +@@ -1078,6 +1370,37 @@ struct r100_gpu_lockup lockup; }; @@ -82952,7 +82873,7 @@ union radeon_asic_config { struct r300_asic r300; struct r100_asic r100; -@@ -1085,6 +1408,7 @@ union radeon_asic_config { +@@ -1085,6 +1408,7 @@ struct rv770_asic rv770; struct evergreen_asic evergreen; struct cayman_asic cayman; @@ -82960,7 +82881,7 @@ }; /* -@@ -1117,6 +1441,8 @@ int radeon_gem_busy_ioctl(struct drm_device *dev, void *data, +@@ -1117,6 +1441,8 @@ struct drm_file *filp); int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); @@ -82969,7 +82890,7 @@ int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); -@@ -1132,47 +1458,6 @@ struct r600_vram_scratch { +@@ -1132,47 +1458,6 @@ /* @@ -83017,7 +82938,7 @@ * Core structure, functions and helpers. */ typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t); -@@ -1216,11 +1501,10 @@ struct radeon_device { +@@ -1216,11 +1501,10 @@ struct radeon_mode_info mode_info; struct radeon_scratch scratch; struct radeon_mman mman; @@ -83033,7 +82954,7 @@ struct radeon_ib_pool ib_pool; struct radeon_irq irq; struct radeon_asic *asic; -@@ -1240,10 +1524,12 @@ struct radeon_device { +@@ -1240,10 +1524,12 @@ const struct firmware *pfp_fw; /* r6/700 PFP firmware */ const struct firmware *rlc_fw; /* r6/700 RLC firmware */ const struct firmware *mc_fw; /* NI MC firmware */ @@ -83046,7 +82967,7 @@ struct work_struct hotplug_work; int num_crtc; /* number of crtcs */ struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */ -@@ -1264,6 +1550,11 @@ struct radeon_device { +@@ -1264,6 +1550,11 @@ struct drm_file *cmask_filp; /* i2c buses */ struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS]; @@ -83058,7 +82979,7 @@ }; int radeon_device_init(struct radeon_device *rdev, -@@ -1382,6 +1673,9 @@ void r100_pll_errata_after_index(struct radeon_device *rdev); +@@ -1382,6 +1673,9 @@ #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \ (rdev->flags & RADEON_IS_IGP)) #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS)) @@ -83068,7 +82989,7 @@ /* * BIOS helpers. -@@ -1399,18 +1693,17 @@ void radeon_atombios_fini(struct radeon_device *rdev); +@@ -1399,18 +1693,17 @@ /* * RING helpers. */ @@ -83093,7 +83014,7 @@ #endif /* -@@ -1420,46 +1713,53 @@ void radeon_ring_write(struct radeon_device *rdev, uint32_t v); +@@ -1420,46 +1713,53 @@ #define radeon_fini(rdev) (rdev)->asic->fini((rdev)) #define radeon_resume(rdev) (rdev)->asic->resume((rdev)) #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev)) @@ -83184,7 +83105,7 @@ /* Common functions */ /* AGP */ -@@ -1488,12 +1788,49 @@ extern int radeon_suspend_kms(struct drm_device *dev, pm_message_t state); +@@ -1488,12 +1788,49 @@ extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size); /* @@ -83234,11 +83155,11 @@ * r600 functions used by radeon_encoder.c */ extern void r600_hdmi_enable(struct drm_encoder *encoder); -diff --git a/drivers/gpu/drm/radeon/radeon_asic.c b/drivers/gpu/drm/radeon/radeon_asic.c -index a2e1eae..be4dc2f 100644 ---- a/drivers/gpu/drm/radeon/radeon_asic.c -+++ b/drivers/gpu/drm/radeon/radeon_asic.c -@@ -114,13 +114,13 @@ void radeon_agp_disable(struct radeon_device *rdev) +Index: linux-3.2.46/drivers/gpu/drm/radeon/radeon_asic.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/radeon/radeon_asic.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/radeon/radeon_asic.c 2013-07-26 19:26:24.000000000 +0000 +@@ -114,13 +114,13 @@ rdev->family == CHIP_R423) { DRM_INFO("Forcing AGP to PCIE mode\n"); rdev->flags |= RADEON_IS_PCIE; @@ -83256,7 +83177,7 @@ } rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; } -@@ -136,44 +136,70 @@ static struct radeon_asic r100_asic = { +@@ -136,44 +136,70 @@ .vga_set_state = &r100_vga_set_state, .gpu_is_lockup = &r100_gpu_is_lockup, .asic_reset = &r100_asic_reset, @@ -83363,7 +83284,7 @@ }; static struct radeon_asic r200_asic = { -@@ -184,43 +210,70 @@ static struct radeon_asic r200_asic = { +@@ -184,43 +210,70 @@ .vga_set_state = &r100_vga_set_state, .gpu_is_lockup = &r100_gpu_is_lockup, .asic_reset = &r100_asic_reset, @@ -83469,7 +83390,7 @@ }; static struct radeon_asic r300_asic = { -@@ -231,44 +284,70 @@ static struct radeon_asic r300_asic = { +@@ -231,44 +284,70 @@ .vga_set_state = &r100_vga_set_state, .gpu_is_lockup = &r300_gpu_is_lockup, .asic_reset = &r300_asic_reset, @@ -83576,7 +83497,7 @@ }; static struct radeon_asic r300_asic_pcie = { -@@ -279,43 +358,70 @@ static struct radeon_asic r300_asic_pcie = { +@@ -279,43 +358,70 @@ .vga_set_state = &r100_vga_set_state, .gpu_is_lockup = &r300_gpu_is_lockup, .asic_reset = &r300_asic_reset, @@ -83682,7 +83603,7 @@ }; static struct radeon_asic r420_asic = { -@@ -326,44 +432,70 @@ static struct radeon_asic r420_asic = { +@@ -326,44 +432,70 @@ .vga_set_state = &r100_vga_set_state, .gpu_is_lockup = &r300_gpu_is_lockup, .asic_reset = &r300_asic_reset, @@ -83789,7 +83710,7 @@ }; static struct radeon_asic rs400_asic = { -@@ -374,44 +506,70 @@ static struct radeon_asic rs400_asic = { +@@ -374,44 +506,70 @@ .vga_set_state = &r100_vga_set_state, .gpu_is_lockup = &r300_gpu_is_lockup, .asic_reset = &r300_asic_reset, @@ -83896,7 +83817,7 @@ }; static struct radeon_asic rs600_asic = { -@@ -422,44 +580,70 @@ static struct radeon_asic rs600_asic = { +@@ -422,44 +580,70 @@ .vga_set_state = &r100_vga_set_state, .gpu_is_lockup = &r300_gpu_is_lockup, .asic_reset = &rs600_asic_reset, @@ -84003,7 +83924,7 @@ }; static struct radeon_asic rs690_asic = { -@@ -470,44 +654,70 @@ static struct radeon_asic rs690_asic = { +@@ -470,44 +654,70 @@ .vga_set_state = &r100_vga_set_state, .gpu_is_lockup = &r300_gpu_is_lockup, .asic_reset = &rs600_asic_reset, @@ -84110,7 +84031,7 @@ }; static struct radeon_asic rv515_asic = { -@@ -518,44 +728,70 @@ static struct radeon_asic rv515_asic = { +@@ -518,44 +728,70 @@ .vga_set_state = &r100_vga_set_state, .gpu_is_lockup = &r300_gpu_is_lockup, .asic_reset = &rs600_asic_reset, @@ -84217,7 +84138,7 @@ }; static struct radeon_asic r520_asic = { -@@ -566,44 +802,70 @@ static struct radeon_asic r520_asic = { +@@ -566,44 +802,70 @@ .vga_set_state = &r100_vga_set_state, .gpu_is_lockup = &r300_gpu_is_lockup, .asic_reset = &rs600_asic_reset, @@ -84324,7 +84245,7 @@ }; static struct radeon_asic r600_asic = { -@@ -611,46 +873,72 @@ static struct radeon_asic r600_asic = { +@@ -611,46 +873,72 @@ .fini = &r600_fini, .suspend = &r600_suspend, .resume = &r600_resume, @@ -84432,7 +84353,7 @@ }; static struct radeon_asic rs780_asic = { -@@ -658,46 +946,72 @@ static struct radeon_asic rs780_asic = { +@@ -658,46 +946,72 @@ .fini = &r600_fini, .suspend = &r600_suspend, .resume = &r600_resume, @@ -84540,7 +84461,7 @@ }; static struct radeon_asic rv770_asic = { -@@ -705,46 +1019,72 @@ static struct radeon_asic rv770_asic = { +@@ -705,46 +1019,72 @@ .fini = &rv770_fini, .suspend = &rv770_suspend, .resume = &rv770_resume, @@ -84648,7 +84569,7 @@ }; static struct radeon_asic evergreen_asic = { -@@ -752,46 +1092,72 @@ static struct radeon_asic evergreen_asic = { +@@ -752,46 +1092,72 @@ .fini = &evergreen_fini, .suspend = &evergreen_suspend, .resume = &evergreen_resume, @@ -84756,7 +84677,7 @@ }; static struct radeon_asic sumo_asic = { -@@ -799,46 +1165,72 @@ static struct radeon_asic sumo_asic = { +@@ -799,46 +1165,72 @@ .fini = &evergreen_fini, .suspend = &evergreen_suspend, .resume = &evergreen_resume, @@ -84864,7 +84785,7 @@ }; static struct radeon_asic btc_asic = { -@@ -846,46 +1238,82 @@ static struct radeon_asic btc_asic = { +@@ -846,46 +1238,82 @@ .fini = &evergreen_fini, .suspend = &evergreen_suspend, .resume = &evergreen_resume, @@ -84982,7 +84903,7 @@ }; static struct radeon_asic cayman_asic = { -@@ -893,46 +1321,285 @@ static struct radeon_asic cayman_asic = { +@@ -893,46 +1321,285 @@ .fini = &cayman_fini, .suspend = &cayman_suspend, .resume = &cayman_resume, @@ -85303,7 +85224,7 @@ }; int radeon_asic_init(struct radeon_device *rdev) -@@ -974,10 +1641,10 @@ int radeon_asic_init(struct radeon_device *rdev) +@@ -974,10 +1641,10 @@ rdev->asic = &r420_asic; /* handle macs */ if (rdev->bios == NULL) { @@ -85318,7 +85239,7 @@ } break; case CHIP_RS400: -@@ -1050,6 +1717,21 @@ int radeon_asic_init(struct radeon_device *rdev) +@@ -1050,6 +1717,21 @@ rdev->asic = &cayman_asic; /* set num crtcs */ rdev->num_crtc = 6; @@ -85340,7 +85261,7 @@ break; default: /* FIXME: not supported yet */ -@@ -1057,8 +1739,8 @@ int radeon_asic_init(struct radeon_device *rdev) +@@ -1057,8 +1739,8 @@ } if (rdev->flags & RADEON_IS_IGP) { @@ -85351,11 +85272,11 @@ } return 0; -diff --git a/drivers/gpu/drm/radeon/radeon_asic.h b/drivers/gpu/drm/radeon/radeon_asic.h -index 5aa6670..917e49c 100644 ---- a/drivers/gpu/drm/radeon/radeon_asic.h -+++ b/drivers/gpu/drm/radeon/radeon_asic.h -@@ -58,17 +58,20 @@ void r100_fini(struct radeon_device *rdev); +Index: linux-3.2.46/drivers/gpu/drm/radeon/radeon_asic.h +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/radeon/radeon_asic.h 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/radeon/radeon_asic.h 2013-07-26 19:26:24.000000000 +0000 +@@ -58,17 +58,20 @@ int r100_suspend(struct radeon_device *rdev); int r100_resume(struct radeon_device *rdev); void r100_vga_set_state(struct radeon_device *rdev, bool state); @@ -85379,7 +85300,7 @@ int r100_cs_parse(struct radeon_cs_parser *p); void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg); -@@ -83,7 +86,7 @@ int r100_set_surface_reg(struct radeon_device *rdev, int reg, +@@ -83,7 +86,7 @@ void r100_clear_surface_reg(struct radeon_device *rdev, int reg); void r100_bandwidth_update(struct radeon_device *rdev); void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); @@ -85388,7 +85309,7 @@ void r100_hpd_init(struct radeon_device *rdev); void r100_hpd_fini(struct radeon_device *rdev); bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd); -@@ -101,12 +104,12 @@ void r100_pci_gart_disable(struct radeon_device *rdev); +@@ -101,12 +104,12 @@ int r100_debugfs_mc_info_init(struct radeon_device *rdev); int r100_gui_wait_for_idle(struct radeon_device *rdev); void r100_gpu_lockup_update(struct r100_gpu_lockup *lockup, @@ -85404,7 +85325,7 @@ void r100_irq_disable(struct radeon_device *rdev); void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save); void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save); -@@ -136,6 +139,8 @@ extern void r100_pm_get_dynpm_state(struct radeon_device *rdev); +@@ -136,6 +139,8 @@ extern void r100_pre_page_flip(struct radeon_device *rdev, int crtc); extern u32 r100_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base); extern void r100_post_page_flip(struct radeon_device *rdev, int crtc); @@ -85413,7 +85334,7 @@ /* * r200,rv250,rs300,rv280 -@@ -154,9 +159,9 @@ extern int r300_init(struct radeon_device *rdev); +@@ -154,9 +159,9 @@ extern void r300_fini(struct radeon_device *rdev); extern int r300_suspend(struct radeon_device *rdev); extern int r300_resume(struct radeon_device *rdev); @@ -85425,7 +85346,7 @@ extern void r300_fence_ring_emit(struct radeon_device *rdev, struct radeon_fence *fence); extern int r300_cs_parse(struct radeon_cs_parser *p); -@@ -173,6 +178,7 @@ extern int rv370_pcie_gart_init(struct radeon_device *rdev); +@@ -173,6 +178,7 @@ extern void rv370_pcie_gart_fini(struct radeon_device *rdev); extern int rv370_pcie_gart_enable(struct radeon_device *rdev); extern void rv370_pcie_gart_disable(struct radeon_device *rdev); @@ -85433,7 +85354,7 @@ /* * r420,r423,rv410 -@@ -203,6 +209,7 @@ int rs400_gart_enable(struct radeon_device *rdev); +@@ -203,6 +209,7 @@ void rs400_gart_adjust_size(struct radeon_device *rdev); void rs400_gart_disable(struct radeon_device *rdev); void rs400_gart_fini(struct radeon_device *rdev); @@ -85441,7 +85362,7 @@ /* * rs600. -@@ -233,7 +240,8 @@ extern void rs600_pre_page_flip(struct radeon_device *rdev, int crtc); +@@ -233,7 +240,8 @@ extern u32 rs600_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base); extern void rs600_post_page_flip(struct radeon_device *rdev, int crtc); void rs600_set_safe_registers(struct radeon_device *rdev); @@ -85451,7 +85372,7 @@ /* * rs690,rs740 -@@ -248,6 +256,7 @@ void rs690_bandwidth_update(struct radeon_device *rdev); +@@ -248,6 +256,7 @@ void rs690_line_buffer_adjust(struct radeon_device *rdev, struct drm_display_mode *mode1, struct drm_display_mode *mode2); @@ -85459,7 +85380,7 @@ /* * rv515 -@@ -261,7 +270,7 @@ int rv515_init(struct radeon_device *rdev); +@@ -261,7 +270,7 @@ void rv515_fini(struct radeon_device *rdev); uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg); void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); @@ -85468,7 +85389,7 @@ void rv515_bandwidth_update(struct radeon_device *rdev); int rv515_resume(struct radeon_device *rdev); int rv515_suspend(struct radeon_device *rdev); -@@ -272,13 +281,14 @@ void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save); +@@ -272,13 +281,14 @@ void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save); void rv515_clock_startup(struct radeon_device *rdev); void rv515_debugfs(struct radeon_device *rdev); @@ -85484,7 +85405,7 @@ /* * r600,rv610,rv630,rv620,rv635,rv670,rs780,rs880 -@@ -290,22 +300,25 @@ int r600_resume(struct radeon_device *rdev); +@@ -290,22 +300,25 @@ void r600_vga_set_state(struct radeon_device *rdev, bool state); int r600_wb_init(struct radeon_device *rdev); void r600_wb_fini(struct radeon_device *rdev); @@ -85514,7 +85435,7 @@ int r600_copy_blit(struct radeon_device *rdev, uint64_t src_offset, uint64_t dst_offset, unsigned num_gpu_pages, struct radeon_fence *fence); -@@ -325,7 +338,7 @@ extern int r600_get_pcie_lanes(struct radeon_device *rdev); +@@ -325,7 +338,7 @@ bool r600_card_posted(struct radeon_device *rdev); void r600_cp_stop(struct radeon_device *rdev); int r600_cp_start(struct radeon_device *rdev); @@ -85523,7 +85444,7 @@ int r600_cp_resume(struct radeon_device *rdev); void r600_cp_fini(struct radeon_device *rdev); int r600_count_pipe_bits(uint32_t val); -@@ -366,6 +379,7 @@ void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence) +@@ -366,6 +379,7 @@ void r600_kms_blit_copy(struct radeon_device *rdev, u64 src_gpu_addr, u64 dst_gpu_addr, unsigned num_gpu_pages); @@ -85531,7 +85452,7 @@ /* * rv770,rv730,rv710,rv740 -@@ -394,7 +408,7 @@ int evergreen_init(struct radeon_device *rdev); +@@ -394,7 +408,7 @@ void evergreen_fini(struct radeon_device *rdev); int evergreen_suspend(struct radeon_device *rdev); int evergreen_resume(struct radeon_device *rdev); @@ -85540,7 +85461,7 @@ int evergreen_asic_reset(struct radeon_device *rdev); void evergreen_bandwidth_update(struct radeon_device *rdev); void evergreen_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); -@@ -414,18 +428,59 @@ extern void sumo_pm_init_profile(struct radeon_device *rdev); +@@ -414,18 +428,59 @@ extern void evergreen_pre_page_flip(struct radeon_device *rdev, int crtc); extern u32 evergreen_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base); extern void evergreen_post_page_flip(struct radeon_device *rdev, int crtc); @@ -85601,11 +85522,11 @@ +int si_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib); #endif -diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c b/drivers/gpu/drm/radeon/radeon_atombios.c -index 383b38e..38d87e1 100644 ---- a/drivers/gpu/drm/radeon/radeon_atombios.c -+++ b/drivers/gpu/drm/radeon/radeon_atombios.c -@@ -56,6 +56,10 @@ extern void +Index: linux-3.2.46/drivers/gpu/drm/radeon/radeon_atombios.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/radeon/radeon_atombios.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/radeon/radeon_atombios.c 2013-07-26 19:26:24.000000000 +0000 +@@ -56,6 +56,10 @@ radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum, uint32_t supported_device); @@ -85616,7 +85537,7 @@ union atom_supported_devices { struct _ATOM_SUPPORTED_DEVICES_INFO info; struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2; -@@ -253,7 +257,9 @@ static struct radeon_hpd radeon_atom_get_hpd_info_from_gpio(struct radeon_device +@@ -253,7 +257,9 @@ memset(&hpd, 0, sizeof(struct radeon_hpd)); @@ -85627,7 +85548,7 @@ reg = EVERGREEN_DC_GPIO_HPD_A; else reg = AVIVO_DC_GPIO_HPD_A; -@@ -1890,6 +1896,8 @@ static const char *pp_lib_thermal_controller_names[] = { +@@ -1890,6 +1896,8 @@ "emc2103", "Sumo", "Northern Islands", @@ -85636,7 +85557,7 @@ }; union power_info { -@@ -1906,6 +1914,7 @@ union pplib_clock_info { +@@ -1906,6 +1914,7 @@ struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780; struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen; struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo; @@ -85644,7 +85565,7 @@ }; union pplib_power_state { -@@ -2165,6 +2174,11 @@ static void radeon_atombios_add_pplib_thermal_controller(struct radeon_device *r +@@ -2165,6 +2174,11 @@ (controller->ucFanParameters & ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with"); rdev->pm.int_thermal_type = THERMAL_TYPE_NI; @@ -85656,7 +85577,7 @@ } else if ((controller->ucType == ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO) || (controller->ucType == -@@ -2285,6 +2299,7 @@ static bool radeon_atombios_parse_pplib_clock_info(struct radeon_device *rdev, +@@ -2285,6 +2299,7 @@ union pplib_clock_info *clock_info) { u32 sclk, mclk; @@ -85664,7 +85585,7 @@ if (rdev->flags & RADEON_IS_IGP) { if (rdev->family >= CHIP_PALM) { -@@ -2296,6 +2311,19 @@ static bool radeon_atombios_parse_pplib_clock_info(struct radeon_device *rdev, +@@ -2296,6 +2311,19 @@ sclk |= clock_info->rs780.ucLowEngineClockHigh << 16; rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk; } @@ -85684,7 +85605,7 @@ } else if (ASIC_IS_DCE4(rdev)) { sclk = le16_to_cpu(clock_info->evergreen.usEngineClockLow); sclk |= clock_info->evergreen.ucEngineClockHigh << 16; -@@ -2323,11 +2351,18 @@ static bool radeon_atombios_parse_pplib_clock_info(struct radeon_device *rdev, +@@ -2323,11 +2351,18 @@ } /* patch up vddc if necessary */ @@ -85707,7 +85628,7 @@ } if (rdev->flags & RADEON_IS_IGP) { -@@ -2439,9 +2474,9 @@ static int radeon_atombios_parse_power_table_6(struct radeon_device *rdev) +@@ -2439,9 +2474,9 @@ int i, j, non_clock_array_index, clock_array_index; int state_index = 0, mode_index = 0; union pplib_clock_info *clock_info; @@ -85720,7 +85641,7 @@ bool valid; union power_info *power_info; int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); -@@ -2455,13 +2490,13 @@ static int radeon_atombios_parse_power_table_6(struct radeon_device *rdev) +@@ -2455,13 +2490,13 @@ power_info = (union power_info *)(mode_info->atom_context->bios + data_offset); radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController); @@ -85737,7 +85658,7 @@ (mode_info->atom_context->bios + data_offset + le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset)); if (state_array->ucNumEntries == 0) -@@ -2487,7 +2522,7 @@ static int radeon_atombios_parse_power_table_6(struct radeon_device *rdev) +@@ -2487,7 +2522,7 @@ for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) { clock_array_index = power_state->v2.clockInfoIndex[j]; clock_info = (union pplib_clock_info *) @@ -85746,7 +85667,7 @@ valid = radeon_atombios_parse_pplib_clock_info(rdev, state_index, mode_index, clock_info); -@@ -2647,6 +2682,7 @@ union set_voltage { +@@ -2647,6 +2682,7 @@ struct _SET_VOLTAGE_PS_ALLOCATION alloc; struct _SET_VOLTAGE_PARAMETERS v1; struct _SET_VOLTAGE_PARAMETERS_V2 v2; @@ -85754,7 +85675,7 @@ }; void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type) -@@ -2673,6 +2709,11 @@ void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 v +@@ -2673,6 +2709,11 @@ args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE; args.v2.usVoltageLevel = cpu_to_le16(voltage_level); break; @@ -85766,7 +85687,7 @@ default: DRM_ERROR("Unknown table version %d, %d\n", frev, crev); return; -@@ -2681,8 +2722,8 @@ void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 v +@@ -2681,8 +2722,8 @@ atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); } @@ -85777,7 +85698,7 @@ { union set_voltage args; int index = GetIndexIntoMasterTable(COMMAND, SetVoltage); -@@ -2703,6 +2744,15 @@ int radeon_atom_get_max_vddc(struct radeon_device *rdev, +@@ -2703,6 +2744,15 @@ *voltage = le16_to_cpu(args.v2.usVoltageLevel); break; @@ -85793,7 +85714,7 @@ default: DRM_ERROR("Unknown table version %d, %d\n", frev, crev); return -EINVAL; -@@ -2954,6 +3004,20 @@ radeon_atombios_connected_scratch_regs(struct drm_connector *connector, +@@ -2954,6 +3004,20 @@ bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5; } } @@ -85814,7 +85735,7 @@ if (rdev->family >= CHIP_R600) { WREG32(R600_BIOS_0_SCRATCH, bios_0_scratch); -@@ -2974,6 +3038,9 @@ radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc) +@@ -2974,6 +3038,9 @@ struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); uint32_t bios_3_scratch; @@ -85824,7 +85745,7 @@ if (rdev->family >= CHIP_R600) bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH); else -@@ -3026,6 +3093,9 @@ radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on) +@@ -3026,6 +3093,9 @@ struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); uint32_t bios_2_scratch; @@ -85834,11 +85755,11 @@ if (rdev->family >= CHIP_R600) bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH); else -diff --git a/drivers/gpu/drm/radeon/radeon_benchmark.c b/drivers/gpu/drm/radeon/radeon_benchmark.c -index 441de38..89a0eec 100644 ---- a/drivers/gpu/drm/radeon/radeon_benchmark.c -+++ b/drivers/gpu/drm/radeon/radeon_benchmark.c -@@ -43,17 +43,19 @@ static int radeon_benchmark_do_move(struct radeon_device *rdev, unsigned size, +Index: linux-3.2.46/drivers/gpu/drm/radeon/radeon_benchmark.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/radeon/radeon_benchmark.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/radeon/radeon_benchmark.c 2013-07-26 19:26:24.000000000 +0000 +@@ -43,17 +43,19 @@ start_jiffies = jiffies; for (i = 0; i < n; i++) { @@ -85862,7 +85783,7 @@ r = radeon_copy_blit(rdev, saddr, daddr, size / RADEON_GPU_PAGE_SIZE, fence); -@@ -129,7 +131,7 @@ static void radeon_benchmark_move(struct radeon_device *rdev, unsigned size, +@@ -129,7 +131,7 @@ /* r100 doesn't have dma engine so skip the test */ /* also, VRAM-to-VRAM test doesn't make much sense for DMA */ /* skip it as well if domains are the same */ @@ -85871,7 +85792,7 @@ time = radeon_benchmark_do_move(rdev, size, saddr, daddr, RADEON_BENCHMARK_COPY_DMA, n); if (time < 0) -@@ -139,7 +141,7 @@ static void radeon_benchmark_move(struct radeon_device *rdev, unsigned size, +@@ -139,7 +141,7 @@ sdomain, ddomain, "dma"); } @@ -85880,7 +85801,7 @@ time = radeon_benchmark_do_move(rdev, size, saddr, daddr, RADEON_BENCHMARK_COPY_BLIT, n); if (time < 0) -@@ -210,42 +212,42 @@ void radeon_benchmark(struct radeon_device *rdev, int test_number) +@@ -210,42 +212,42 @@ break; case 3: /* GTT to VRAM, buffer size sweep, powers of 2 */ @@ -85932,11 +85853,10 @@ radeon_benchmark_move(rdev, common_modes[i], RADEON_GEM_DOMAIN_VRAM, RADEON_GEM_DOMAIN_VRAM); -diff --git a/drivers/gpu/drm/radeon/radeon_blit_common.h b/drivers/gpu/drm/radeon/radeon_blit_common.h -new file mode 100644 -index 0000000..4ecbe72 ---- /dev/null -+++ b/drivers/gpu/drm/radeon/radeon_blit_common.h +Index: linux-3.2.46/drivers/gpu/drm/radeon/radeon_blit_common.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/radeon/radeon_blit_common.h 2013-07-26 19:26:24.000000000 +0000 @@ -0,0 +1,44 @@ +/* + * Copyright 2009 Advanced Micro Devices, Inc. @@ -85982,11 +85902,11 @@ + +#define __RADEON_BLIT_COMMON_H__ +#endif -diff --git a/drivers/gpu/drm/radeon/radeon_clocks.c b/drivers/gpu/drm/radeon/radeon_clocks.c -index b6e18c8..9c6b29a 100644 ---- a/drivers/gpu/drm/radeon/radeon_clocks.c -+++ b/drivers/gpu/drm/radeon/radeon_clocks.c -@@ -334,7 +334,7 @@ void radeon_get_clock_info(struct drm_device *dev) +Index: linux-3.2.46/drivers/gpu/drm/radeon/radeon_clocks.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/radeon/radeon_clocks.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/radeon/radeon_clocks.c 2013-07-26 19:26:24.000000000 +0000 +@@ -334,7 +334,7 @@ if (!rdev->clock.default_sclk) rdev->clock.default_sclk = radeon_get_engine_clock(rdev); @@ -85995,7 +85915,7 @@ rdev->clock.default_mclk = radeon_get_memory_clock(rdev); rdev->pm.current_sclk = rdev->clock.default_sclk; -@@ -633,7 +633,7 @@ void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable) +@@ -633,7 +633,7 @@ tmp &= ~(R300_SCLK_FORCE_VAP); tmp |= RADEON_SCLK_FORCE_CP; WREG32_PLL(RADEON_SCLK_CNTL, tmp); @@ -86004,7 +85924,7 @@ tmp = RREG32_PLL(R300_SCLK_CNTL2); tmp &= ~(R300_SCLK_FORCE_TCL | -@@ -651,12 +651,12 @@ void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable) +@@ -651,12 +651,12 @@ tmp |= (RADEON_ENGIN_DYNCLK_MODE | (0x01 << RADEON_ACTIVE_HILO_LAT_SHIFT)); WREG32_PLL(RADEON_CLK_PWRMGT_CNTL, tmp); @@ -86019,7 +85939,7 @@ /* When DRI is enabled, setting DYN_STOP_LAT to zero can cause some R200 to lockup randomly, leave them as set by BIOS. -@@ -696,7 +696,7 @@ void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable) +@@ -696,7 +696,7 @@ tmp |= RADEON_SCLK_MORE_FORCEON; } WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp); @@ -86028,7 +85948,7 @@ } /* RV200::A11 A12, RV250::A11 A12 */ -@@ -709,7 +709,7 @@ void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable) +@@ -709,7 +709,7 @@ tmp |= RADEON_TCL_BYPASS_DISABLE; WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp); } @@ -86037,7 +85957,7 @@ /*enable dynamic mode for display clocks (PIXCLK and PIX2CLK) */ tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL); -@@ -722,14 +722,14 @@ void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable) +@@ -722,14 +722,14 @@ RADEON_PIXCLK_TMDS_ALWAYS_ONb); WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp); @@ -86054,7 +85974,7 @@ } } else { /* Turn everything OFF (ForceON to everything) */ -@@ -861,7 +861,7 @@ void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable) +@@ -861,7 +861,7 @@ } WREG32_PLL(RADEON_SCLK_CNTL, tmp); @@ -86063,7 +85983,7 @@ if ((rdev->family == CHIP_R300) || (rdev->family == CHIP_R350)) { -@@ -870,7 +870,7 @@ void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable) +@@ -870,7 +870,7 @@ R300_SCLK_FORCE_GA | R300_SCLK_FORCE_CBA); WREG32_PLL(R300_SCLK_CNTL2, tmp); @@ -86072,7 +85992,7 @@ } if (rdev->flags & RADEON_IS_IGP) { -@@ -878,7 +878,7 @@ void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable) +@@ -878,7 +878,7 @@ tmp &= ~(RADEON_FORCEON_MCLKA | RADEON_FORCEON_YCLKA); WREG32_PLL(RADEON_MCLK_CNTL, tmp); @@ -86081,7 +86001,7 @@ } if ((rdev->family == CHIP_RV200) || -@@ -887,7 +887,7 @@ void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable) +@@ -887,7 +887,7 @@ tmp = RREG32_PLL(RADEON_SCLK_MORE_CNTL); tmp |= RADEON_SCLK_MORE_FORCEON; WREG32_PLL(RADEON_SCLK_MORE_CNTL, tmp); @@ -86090,7 +86010,7 @@ } tmp = RREG32_PLL(RADEON_PIXCLKS_CNTL); -@@ -900,7 +900,7 @@ void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable) +@@ -900,7 +900,7 @@ RADEON_PIXCLK_TMDS_ALWAYS_ONb); WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp); @@ -86099,11 +86019,11 @@ tmp = RREG32_PLL(RADEON_VCLK_ECP_CNTL); tmp &= ~(RADEON_PIXCLK_ALWAYS_ONb | -diff --git a/drivers/gpu/drm/radeon/radeon_combios.c b/drivers/gpu/drm/radeon/radeon_combios.c -index c32fd93..2b2c557 100644 ---- a/drivers/gpu/drm/radeon/radeon_combios.c -+++ b/drivers/gpu/drm/radeon/radeon_combios.c -@@ -1545,9 +1545,6 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev) +Index: linux-3.2.46/drivers/gpu/drm/radeon/radeon_combios.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/radeon/radeon_combios.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/radeon/radeon_combios.c 2013-07-26 19:26:24.000000000 +0000 +@@ -1545,9 +1545,6 @@ of_machine_is_compatible("PowerBook6,7")) { /* ibook */ rdev->mode_info.connector_table = CT_IBOOK; @@ -86113,7 +86033,7 @@ } else if (of_machine_is_compatible("PowerMac4,4")) { /* emac */ rdev->mode_info.connector_table = CT_EMAC; -@@ -1573,11 +1570,6 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev) +@@ -1573,11 +1570,6 @@ (rdev->pdev->subsystem_device == 0x4150)) { /* Mac G5 tower 9600 */ rdev->mode_info.connector_table = CT_MAC_G5_9600; @@ -86125,7 +86045,7 @@ } else #endif /* CONFIG_PPC_PMAC */ #ifdef CONFIG_PPC64 -@@ -2151,115 +2143,6 @@ bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev) +@@ -2151,115 +2143,6 @@ CONNECTOR_OBJECT_ID_SVIDEO, &hpd); break; @@ -86241,7 +86161,7 @@ default: DRM_INFO("Connector table: %d (invalid)\n", rdev->mode_info.connector_table); -@@ -2979,7 +2862,7 @@ bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder) +@@ -2979,7 +2862,7 @@ case 4: val = RBIOS16(index); index += 2; @@ -86250,7 +86170,7 @@ break; case 6: slave_addr = id & 0xff; -@@ -3178,7 +3061,7 @@ static void combios_parse_pll_table(struct drm_device *dev, uint16_t offset) +@@ -3178,7 +3061,7 @@ udelay(150); break; case 2: @@ -86259,7 +86179,7 @@ break; case 3: while (tmp--) { -@@ -3209,13 +3092,13 @@ static void combios_parse_pll_table(struct drm_device *dev, uint16_t offset) +@@ -3209,13 +3092,13 @@ /*mclk_cntl |= 0x00001111;*//* ??? */ WREG32_PLL(RADEON_MCLK_CNTL, mclk_cntl); @@ -86275,11 +86195,11 @@ } break; default: -diff --git a/drivers/gpu/drm/radeon/radeon_connectors.c b/drivers/gpu/drm/radeon/radeon_connectors.c -index 6fd53b6..ab63bcd 100644 ---- a/drivers/gpu/drm/radeon/radeon_connectors.c -+++ b/drivers/gpu/drm/radeon/radeon_connectors.c -@@ -846,6 +846,27 @@ static int radeon_dvi_get_modes(struct drm_connector *connector) +Index: linux-3.2.46/drivers/gpu/drm/radeon/radeon_connectors.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/radeon/radeon_connectors.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/radeon/radeon_connectors.c 2013-07-26 19:26:24.000000000 +0000 +@@ -846,6 +846,27 @@ return ret; } @@ -86307,7 +86227,7 @@ /* * DVI is complicated * Do a DDC probe, if DDC probe passes, get the full EDID so -@@ -870,6 +891,9 @@ radeon_dvi_detect(struct drm_connector *connector, bool force) +@@ -870,6 +891,9 @@ enum drm_connector_status ret = connector_status_disconnected; bool dret = false; @@ -86317,7 +86237,7 @@ if (radeon_connector->ddc_bus) dret = radeon_ddc_probe(radeon_connector, false); if (dret) { -@@ -1080,7 +1104,7 @@ static int radeon_dvi_mode_valid(struct drm_connector *connector, +@@ -1080,7 +1104,7 @@ (radeon_connector->connector_object_id == CONNECTOR_OBJECT_ID_HDMI_TYPE_B)) return MODE_OK; else if (radeon_connector->connector_object_id == CONNECTOR_OBJECT_ID_HDMI_TYPE_A) { @@ -86326,7 +86246,7 @@ /* HDMI 1.3+ supports max clock of 340 Mhz */ if (mode->clock > 340000) return MODE_CLOCK_HIGH; -@@ -1140,13 +1164,23 @@ static int radeon_dp_get_modes(struct drm_connector *connector) +@@ -1140,13 +1164,23 @@ (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)) { struct drm_display_mode *mode; @@ -86357,7 +86277,7 @@ if (ret > 0) { if (encoder) { -@@ -1157,7 +1191,6 @@ static int radeon_dp_get_modes(struct drm_connector *connector) +@@ -1157,7 +1191,6 @@ return ret; } @@ -86365,7 +86285,7 @@ if (!encoder) return 0; -@@ -1264,6 +1297,9 @@ radeon_dp_detect(struct drm_connector *connector, bool force) +@@ -1264,6 +1297,9 @@ struct radeon_connector_atom_dig *radeon_dig_connector = radeon_connector->con_priv; struct drm_encoder *encoder = radeon_best_single_encoder(connector); @@ -86375,11 +86295,11 @@ if (radeon_connector->edid) { kfree(radeon_connector->edid); radeon_connector->edid = NULL; -diff --git a/drivers/gpu/drm/radeon/radeon_cp.c b/drivers/gpu/drm/radeon/radeon_cp.c -index 72ae826..0ebb7d4 100644 ---- a/drivers/gpu/drm/radeon/radeon_cp.c -+++ b/drivers/gpu/drm/radeon/radeon_cp.c -@@ -2115,6 +2115,8 @@ int radeon_driver_load(struct drm_device *dev, unsigned long flags) +Index: linux-3.2.46/drivers/gpu/drm/radeon/radeon_cp.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/radeon/radeon_cp.c 2013-07-26 19:25:21.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/radeon/radeon_cp.c 2013-07-26 19:26:24.000000000 +0000 +@@ -2112,6 +2112,8 @@ break; } @@ -86388,11 +86308,11 @@ if (drm_pci_device_is_agp(dev)) dev_priv->flags |= RADEON_IS_AGP; else if (pci_is_pcie(dev->pdev)) -diff --git a/drivers/gpu/drm/radeon/radeon_cs.c b/drivers/gpu/drm/radeon/radeon_cs.c -index 1f32557..cf723c4 100644 ---- a/drivers/gpu/drm/radeon/radeon_cs.c -+++ b/drivers/gpu/drm/radeon/radeon_cs.c -@@ -58,7 +58,7 @@ int radeon_cs_parser_relocs(struct radeon_cs_parser *p) +Index: linux-3.2.46/drivers/gpu/drm/radeon/radeon_cs.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/radeon/radeon_cs.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/radeon/radeon_cs.c 2013-07-26 19:26:24.000000000 +0000 +@@ -58,7 +58,7 @@ duplicate = false; r = (struct drm_radeon_cs_reloc *)&chunk->kdata[i*4]; @@ -86401,7 +86321,7 @@ if (r->handle == p->relocs[j].handle) { p->relocs_ptr[i] = &p->relocs[j]; duplicate = true; -@@ -84,16 +84,88 @@ int radeon_cs_parser_relocs(struct radeon_cs_parser *p) +@@ -84,16 +84,88 @@ p->relocs[i].flags = r->flags; radeon_bo_list_add_object(&p->relocs[i].lobj, &p->validated); @@ -86492,7 +86412,7 @@ if (!cs->num_chunks) { return 0; -@@ -103,6 +175,8 @@ int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data) +@@ -103,6 +175,8 @@ p->idx = 0; p->chunk_ib_idx = -1; p->chunk_relocs_idx = -1; @@ -86501,7 +86421,7 @@ p->chunks_array = kcalloc(cs->num_chunks, sizeof(uint64_t), GFP_KERNEL); if (p->chunks_array == NULL) { return -ENOMEM; -@@ -112,6 +186,7 @@ int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data) +@@ -112,6 +186,7 @@ sizeof(uint64_t)*cs->num_chunks)) { return -EFAULT; } @@ -86509,7 +86429,7 @@ p->nchunks = cs->num_chunks; p->chunks = kcalloc(p->nchunks, sizeof(struct radeon_cs_chunk), GFP_KERNEL); if (p->chunks == NULL) { -@@ -140,16 +215,25 @@ int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data) +@@ -140,16 +215,25 @@ if (p->chunks[i].length_dw == 0) return -EINVAL; } @@ -86539,12 +86459,17 @@ size = p->chunks[i].length_dw * sizeof(uint32_t); p->chunks[i].kdata = kmalloc(size, GFP_KERNEL); if (p->chunks[i].kdata == NULL) { -@@ -160,31 +244,55 @@ int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data) +@@ -160,31 +244,55 @@ return -EFAULT; } if (p->chunks[i].chunk_id == RADEON_CHUNK_ID_FLAGS) { - flags = p->chunks[i].kdata[0]; -- } ++ p->cs_flags = p->chunks[i].kdata[0]; ++ if (p->chunks[i].length_dw > 1) ++ ring = p->chunks[i].kdata[1]; ++ if (p->chunks[i].length_dw > 2) ++ priority = (s32)p->chunks[i].kdata[2]; + } - } else { - p->chunks[i].kpage[0] = kmalloc(PAGE_SIZE, GFP_KERNEL); - p->chunks[i].kpage[1] = kmalloc(PAGE_SIZE, GFP_KERNEL); @@ -86554,12 +86479,7 @@ - p->chunks[i].kpage[0] = NULL; - p->chunks[i].kpage[1] = NULL; - return -ENOMEM; -+ p->cs_flags = p->chunks[i].kdata[0]; -+ if (p->chunks[i].length_dw > 1) -+ ring = p->chunks[i].kdata[1]; -+ if (p->chunks[i].length_dw > 2) -+ priority = (s32)p->chunks[i].kdata[2]; - } +- } - p->chunks[i].kpage_idx[0] = -1; - p->chunks[i].kpage_idx[1] = -1; - p->chunks[i].last_copied_page = -1; @@ -86615,7 +86535,7 @@ return 0; } -@@ -226,14 +334,186 @@ static void radeon_cs_parser_fini(struct radeon_cs_parser *parser, int error) +@@ -226,14 +334,186 @@ radeon_ib_free(parser->rdev, &parser->ib); } @@ -86803,7 +86723,7 @@ /* initialize parser */ memset(&parser, 0, sizeof(struct radeon_cs_parser)); parser.filp = filp; -@@ -247,13 +527,6 @@ int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) +@@ -247,13 +527,6 @@ radeon_mutex_unlock(&rdev->cs_mutex); return r; } @@ -86817,7 +86737,7 @@ r = radeon_cs_parser_relocs(&parser); if (r) { if (r != -ERESTARTSYS) -@@ -262,29 +535,15 @@ int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) +@@ -262,29 +535,15 @@ radeon_mutex_unlock(&rdev->cs_mutex); return r; } @@ -86852,11 +86772,11 @@ radeon_cs_parser_fini(&parser, r); radeon_mutex_unlock(&rdev->cs_mutex); return r; -diff --git a/drivers/gpu/drm/radeon/radeon_cursor.c b/drivers/gpu/drm/radeon/radeon_cursor.c -index 2132109..8fb6f41 100644 ---- a/drivers/gpu/drm/radeon/radeon_cursor.c -+++ b/drivers/gpu/drm/radeon/radeon_cursor.c -@@ -197,7 +197,12 @@ int radeon_crtc_cursor_set(struct drm_crtc *crtc, +Index: linux-3.2.46/drivers/gpu/drm/radeon/radeon_cursor.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/radeon/radeon_cursor.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/radeon/radeon_cursor.c 2013-07-26 19:26:24.000000000 +0000 +@@ -197,7 +197,12 @@ unpin: if (radeon_crtc->cursor_bo) { @@ -86870,7 +86790,7 @@ drm_gem_object_unreference_unlocked(radeon_crtc->cursor_bo); } -@@ -233,7 +238,8 @@ int radeon_crtc_cursor_move(struct drm_crtc *crtc, +@@ -233,7 +238,8 @@ y = 0; } @@ -86880,11 +86800,11 @@ int i = 0; struct drm_crtc *crtc_p; -diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c -index bd959c1..68c89db 100644 ---- a/drivers/gpu/drm/radeon/radeon_device.c -+++ b/drivers/gpu/drm/radeon/radeon_device.c -@@ -89,6 +89,10 @@ static const char radeon_family_name[][16] = { +Index: linux-3.2.46/drivers/gpu/drm/radeon/radeon_device.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/radeon/radeon_device.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/radeon/radeon_device.c 2013-07-26 19:26:24.000000000 +0000 +@@ -89,6 +89,10 @@ "TURKS", "CAICOS", "CAYMAN", @@ -86895,7 +86815,7 @@ "LAST", }; -@@ -237,8 +241,8 @@ int radeon_wb_init(struct radeon_device *rdev) +@@ -237,8 +241,8 @@ rdev->wb.use_event = true; } } @@ -86906,7 +86826,7 @@ rdev->wb.enabled = true; rdev->wb.use_event = true; } -@@ -721,18 +725,25 @@ int radeon_device_init(struct radeon_device *rdev, +@@ -721,18 +725,25 @@ /* mutex initialization are all done here so we * can recall function without having locking issues */ radeon_mutex_init(&rdev->cs_mutex); @@ -86935,7 +86855,7 @@ /* Set asic functions */ r = radeon_asic_init(rdev); -@@ -769,8 +780,14 @@ int radeon_device_init(struct radeon_device *rdev, +@@ -769,8 +780,14 @@ r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits)); if (r) { rdev->need_dma32 = true; @@ -86950,7 +86870,7 @@ /* Registers mapping */ /* TODO: block userspace mapping of io register */ -@@ -818,15 +835,20 @@ int radeon_device_init(struct radeon_device *rdev, +@@ -818,15 +835,20 @@ if (r) return r; } @@ -86972,7 +86892,7 @@ void radeon_device_fini(struct radeon_device *rdev) { DRM_INFO("radeon: finishing device.\n"); -@@ -841,6 +863,7 @@ void radeon_device_fini(struct radeon_device *rdev) +@@ -841,6 +863,7 @@ rdev->rio_mem = NULL; iounmap(rdev->rmmio); rdev->rmmio = NULL; @@ -86980,7 +86900,7 @@ } -@@ -852,7 +875,7 @@ int radeon_suspend_kms(struct drm_device *dev, pm_message_t state) +@@ -852,7 +875,7 @@ struct radeon_device *rdev; struct drm_crtc *crtc; struct drm_connector *connector; @@ -86989,7 +86909,7 @@ if (dev == NULL || dev->dev_private == NULL) { return -ENODEV; -@@ -893,7 +916,8 @@ int radeon_suspend_kms(struct drm_device *dev, pm_message_t state) +@@ -893,7 +916,8 @@ /* evict vram memory */ radeon_bo_evict_vram(rdev); /* wait for gpu to finish processing current batch */ @@ -86999,7 +86919,7 @@ radeon_save_bios_scratch_regs(rdev); -@@ -942,9 +966,11 @@ int radeon_resume_kms(struct drm_device *dev) +@@ -942,9 +966,11 @@ radeon_fbdev_set_suspend(rdev, 0); console_unlock(); @@ -87013,7 +86933,7 @@ /* reset hpd state */ radeon_hpd_init(rdev); /* blat the mode back in */ -@@ -994,36 +1020,29 @@ int radeon_gpu_reset(struct radeon_device *rdev) +@@ -994,36 +1020,29 @@ /* * Debugfs */ @@ -87056,7 +86976,7 @@ #if defined(CONFIG_DEBUG_FS) drm_debugfs_create_files(files, nfiles, rdev->ddev->control->debugfs_root, -@@ -1035,6 +1054,22 @@ int radeon_debugfs_add_files(struct radeon_device *rdev, +@@ -1035,6 +1054,22 @@ return 0; } @@ -87079,7 +86999,7 @@ #if defined(CONFIG_DEBUG_FS) int radeon_debugfs_init(struct drm_minor *minor) { -@@ -1043,11 +1078,5 @@ int radeon_debugfs_init(struct drm_minor *minor) +@@ -1043,11 +1078,5 @@ void radeon_debugfs_cleanup(struct drm_minor *minor) { @@ -87091,11 +87011,11 @@ - } } #endif -diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/radeon/radeon_display.c -index 63e7143..00d9cac 100644 ---- a/drivers/gpu/drm/radeon/radeon_display.c -+++ b/drivers/gpu/drm/radeon/radeon_display.c -@@ -303,8 +303,17 @@ void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id) +Index: linux-3.2.46/drivers/gpu/drm/radeon/radeon_display.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/radeon/radeon_display.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/radeon/radeon_display.c 2013-07-26 19:26:24.000000000 +0000 +@@ -303,8 +303,17 @@ if (update_pending && (DRM_SCANOUTPOS_VALID & radeon_get_crtc_scanoutpos(rdev->ddev, crtc_id, &vpos, &hpos)) && @@ -87115,7 +87035,7 @@ /* crtc didn't flip in this target vblank interval, * but flip is pending in crtc. It will complete it * in next vblank interval, so complete the flip at -@@ -393,7 +402,9 @@ static int radeon_crtc_page_flip(struct drm_crtc *crtc, +@@ -393,7 +402,9 @@ DRM_ERROR("failed to reserve new rbo buffer before flip\n"); goto pflip_cleanup; } @@ -87126,7 +87046,7 @@ if (unlikely(r != 0)) { radeon_bo_unreserve(rbo); r = -EINVAL; -@@ -406,7 +417,7 @@ static int radeon_crtc_page_flip(struct drm_crtc *crtc, +@@ -406,7 +417,7 @@ if (!ASIC_IS_AVIVO(rdev)) { /* crtc offset is from display base addr not FB location */ base -= radeon_crtc->legacy_display_base_addr; @@ -87135,7 +87055,7 @@ if (tiling_flags & RADEON_TILING_MACRO) { if (ASIC_IS_R300(rdev)) { -@@ -522,7 +533,7 @@ static void radeon_crtc_init(struct drm_device *dev, int index) +@@ -522,7 +533,7 @@ radeon_legacy_init_crtc(dev, radeon_crtc); } @@ -87144,7 +87064,7 @@ "NONE", "INTERNAL_LVDS", "INTERNAL_TMDS1", -@@ -559,6 +570,7 @@ static const char *encoder_names[36] = { +@@ -559,6 +570,7 @@ "INTERNAL_UNIPHY2", "NUTMEG", "TRAVIS", @@ -87152,7 +87072,7 @@ }; static const char *connector_names[15] = { -@@ -1083,29 +1095,36 @@ static const struct drm_framebuffer_funcs radeon_fb_funcs = { +@@ -1083,29 +1095,36 @@ .create_handle = radeon_user_framebuffer_create_handle, }; @@ -87195,7 +87115,7 @@ return ERR_PTR(-ENOENT); } -@@ -1115,7 +1134,12 @@ radeon_user_framebuffer_create(struct drm_device *dev, +@@ -1115,7 +1134,12 @@ return ERR_PTR(-ENOMEM); } @@ -87209,7 +87129,7 @@ return &radeon_fb->base; } -@@ -1131,11 +1155,6 @@ static const struct drm_mode_config_funcs radeon_mode_funcs = { +@@ -1131,11 +1155,6 @@ .output_poll_changed = radeon_output_poll_changed }; @@ -87221,7 +87141,7 @@ static struct drm_prop_enum_list radeon_tmds_pll_enum_list[] = { { 0, "driver" }, { 1, "bios" }, -@@ -1160,86 +1179,53 @@ static struct drm_prop_enum_list radeon_underscan_enum_list[] = +@@ -1160,86 +1179,53 @@ static int radeon_modeset_create_props(struct radeon_device *rdev) { @@ -87324,7 +87244,7 @@ return 0; } -@@ -1285,6 +1271,9 @@ int radeon_modeset_init(struct radeon_device *rdev) +@@ -1285,6 +1271,9 @@ rdev->ddev->mode_config.max_height = 4096; } @@ -87334,7 +87254,7 @@ rdev->ddev->mode_config.fb_base = rdev->mc.aper_base; ret = radeon_modeset_create_props(rdev); -@@ -1312,9 +1301,11 @@ int radeon_modeset_init(struct radeon_device *rdev) +@@ -1312,9 +1301,11 @@ return ret; } @@ -87348,10 +87268,10 @@ /* initialize hpd */ radeon_hpd_init(rdev); -diff --git a/drivers/gpu/drm/radeon/radeon_drv.c b/drivers/gpu/drm/radeon/radeon_drv.c -index 71499fc..15250fb 100644 ---- a/drivers/gpu/drm/radeon/radeon_drv.c -+++ b/drivers/gpu/drm/radeon/radeon_drv.c +Index: linux-3.2.46/drivers/gpu/drm/radeon/radeon_drv.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/radeon/radeon_drv.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/radeon/radeon_drv.c 2013-07-26 19:26:24.000000000 +0000 @@ -54,9 +54,13 @@ * 2.10.0 - fusion 2D tiling * 2.11.0 - backend map, initial compute support for the CS checker @@ -87367,7 +87287,7 @@ #define KMS_DRIVER_PATCHLEVEL 0 int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags); int radeon_driver_unload_kms(struct drm_device *dev); -@@ -84,6 +88,10 @@ int radeon_dma_ioctl_kms(struct drm_device *dev, void *data, +@@ -84,6 +88,10 @@ struct drm_file *file_priv); int radeon_gem_object_init(struct drm_gem_object *obj); void radeon_gem_object_free(struct drm_gem_object *obj); @@ -87378,7 +87298,7 @@ extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc, int *vpos, int *hpos); extern struct drm_ioctl_desc radeon_ioctls_kms[]; -@@ -140,7 +148,7 @@ module_param_named(vramlimit, radeon_vram_limit, int, 0600); +@@ -140,7 +148,7 @@ MODULE_PARM_DESC(agpmode, "AGP Mode (-1 == PCI)"); module_param_named(agpmode, radeon_agpmode, int, 0444); @@ -87387,7 +87307,7 @@ module_param_named(gartsize, radeon_gart_size, int, 0600); MODULE_PARM_DESC(benchmark, "Run benchmark"); -@@ -206,6 +214,21 @@ static struct pci_device_id pciidlist[] = { +@@ -206,6 +214,21 @@ MODULE_DEVICE_TABLE(pci, pciidlist); #endif @@ -87409,7 +87329,7 @@ static struct drm_driver driver_old = { .driver_features = DRIVER_USE_AGP | DRIVER_USE_MTRR | DRIVER_PCI_DMA | DRIVER_SG | -@@ -232,21 +255,7 @@ static struct drm_driver driver_old = { +@@ -232,21 +255,7 @@ .reclaim_buffers = drm_core_reclaim_buffers, .ioctls = radeon_ioctls, .dma_ioctl = radeon_cp_buffers, @@ -87432,7 +87352,7 @@ .name = DRIVER_NAME, .desc = DRIVER_DESC, .date = DRIVER_DATE, -@@ -304,6 +313,20 @@ radeon_pci_resume(struct pci_dev *pdev) +@@ -304,6 +313,20 @@ return radeon_resume_kms(dev); } @@ -87453,7 +87373,7 @@ static struct drm_driver kms_driver = { .driver_features = DRIVER_USE_AGP | DRIVER_USE_MTRR | DRIVER_PCI_DMA | DRIVER_SG | -@@ -335,24 +358,13 @@ static struct drm_driver kms_driver = { +@@ -335,24 +358,13 @@ .ioctls = radeon_ioctls_kms, .gem_init_object = radeon_gem_object_init, .gem_free_object = radeon_gem_object_free, @@ -87481,11 +87401,11 @@ .name = DRIVER_NAME, .desc = DRIVER_DESC, .date = DRIVER_DATE, -diff --git a/drivers/gpu/drm/radeon/radeon_encoders.c b/drivers/gpu/drm/radeon/radeon_encoders.c -index 4b27efa..7467069 100644 ---- a/drivers/gpu/drm/radeon/radeon_encoders.c -+++ b/drivers/gpu/drm/radeon/radeon_encoders.c -@@ -202,6 +202,22 @@ radeon_get_connector_for_encoder(struct drm_encoder *encoder) +Index: linux-3.2.46/drivers/gpu/drm/radeon/radeon_encoders.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/radeon/radeon_encoders.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/radeon/radeon_encoders.c 2013-07-26 19:26:24.000000000 +0000 +@@ -202,6 +202,22 @@ return NULL; } @@ -87508,7 +87428,7 @@ struct drm_encoder *radeon_get_external_encoder(struct drm_encoder *encoder) { struct drm_device *dev = encoder->dev; -@@ -288,3 +304,64 @@ void radeon_panel_mode_fixup(struct drm_encoder *encoder, +@@ -288,3 +304,64 @@ } @@ -87573,11 +87493,11 @@ + } +} + -diff --git a/drivers/gpu/drm/radeon/radeon_family.h b/drivers/gpu/drm/radeon/radeon_family.h -index ec2f1ea..d1fafea 100644 ---- a/drivers/gpu/drm/radeon/radeon_family.h -+++ b/drivers/gpu/drm/radeon/radeon_family.h -@@ -87,6 +87,10 @@ enum radeon_family { +Index: linux-3.2.46/drivers/gpu/drm/radeon/radeon_family.h +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/radeon/radeon_family.h 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/radeon/radeon_family.h 2013-07-26 19:26:24.000000000 +0000 +@@ -87,6 +87,10 @@ CHIP_TURKS, CHIP_CAICOS, CHIP_CAYMAN, @@ -87588,11 +87508,11 @@ CHIP_LAST, }; -diff --git a/drivers/gpu/drm/radeon/radeon_fb.c b/drivers/gpu/drm/radeon/radeon_fb.c -index 0b7b486..5906914 100644 ---- a/drivers/gpu/drm/radeon/radeon_fb.c -+++ b/drivers/gpu/drm/radeon/radeon_fb.c -@@ -103,7 +103,7 @@ static void radeonfb_destroy_pinned_object(struct drm_gem_object *gobj) +Index: linux-3.2.46/drivers/gpu/drm/radeon/radeon_fb.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/radeon/radeon_fb.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/radeon/radeon_fb.c 2013-07-26 19:26:24.000000000 +0000 +@@ -103,7 +103,7 @@ } static int radeonfb_create_pinned_object(struct radeon_fbdev *rfbdev, @@ -87601,7 +87521,7 @@ struct drm_gem_object **gobj_p) { struct radeon_device *rdev = rfbdev->rdev; -@@ -114,13 +114,17 @@ static int radeonfb_create_pinned_object(struct radeon_fbdev *rfbdev, +@@ -114,13 +114,17 @@ int ret; int aligned_size, size; int height = mode_cmd->height; @@ -87621,7 +87541,7 @@ aligned_size = ALIGN(size, PAGE_SIZE); ret = radeon_gem_object_create(rdev, aligned_size, 0, RADEON_GEM_DOMAIN_VRAM, -@@ -137,7 +141,7 @@ static int radeonfb_create_pinned_object(struct radeon_fbdev *rfbdev, +@@ -137,7 +141,7 @@ tiling_flags = RADEON_TILING_MACRO; #ifdef __BIG_ENDIAN @@ -87630,7 +87550,7 @@ case 32: tiling_flags |= RADEON_TILING_SWAP_32BIT; break; -@@ -151,7 +155,7 @@ static int radeonfb_create_pinned_object(struct radeon_fbdev *rfbdev, +@@ -151,7 +155,7 @@ if (tiling_flags) { ret = radeon_bo_set_tiling_flags(rbo, tiling_flags | RADEON_TILING_SURFACE, @@ -87639,7 +87559,7 @@ if (ret) dev_err(rdev->dev, "FB failed to set tiling flags\n"); } -@@ -160,7 +164,10 @@ static int radeonfb_create_pinned_object(struct radeon_fbdev *rfbdev, +@@ -160,7 +164,10 @@ ret = radeon_bo_reserve(rbo, false); if (unlikely(ret != 0)) goto out_unref; @@ -87651,7 +87571,7 @@ if (ret) { radeon_bo_unreserve(rbo); goto out_unref; -@@ -187,7 +194,7 @@ static int radeonfb_create(struct radeon_fbdev *rfbdev, +@@ -187,7 +194,7 @@ struct radeon_device *rdev = rfbdev->rdev; struct fb_info *info; struct drm_framebuffer *fb = NULL; @@ -87660,7 +87580,7 @@ struct drm_gem_object *gobj = NULL; struct radeon_bo *rbo = NULL; struct device *device = &rdev->pdev->dev; -@@ -201,10 +208,15 @@ static int radeonfb_create(struct radeon_fbdev *rfbdev, +@@ -201,10 +208,15 @@ if ((sizes->surface_bpp == 24) && ASIC_IS_AVIVO(rdev)) sizes->surface_bpp = 32; @@ -87678,7 +87598,7 @@ rbo = gem_to_radeon_bo(gobj); /* okay we have an object now allocate the framebuffer */ -@@ -216,7 +228,11 @@ static int radeonfb_create(struct radeon_fbdev *rfbdev, +@@ -216,7 +228,11 @@ info->par = rfbdev; @@ -87691,7 +87611,7 @@ fb = &rfbdev->rfb.base; -@@ -228,7 +244,7 @@ static int radeonfb_create(struct radeon_fbdev *rfbdev, +@@ -228,7 +244,7 @@ strcpy(info->fix.id, "radeondrmfb"); @@ -87700,7 +87620,7 @@ info->flags = FBINFO_DEFAULT | FBINFO_CAN_FORCE_OUTPUT; info->fbops = &radeonfb_ops; -@@ -250,11 +266,7 @@ static int radeonfb_create(struct radeon_fbdev *rfbdev, +@@ -250,11 +266,7 @@ info->apertures->ranges[0].base = rdev->ddev->mode_config.fb_base; info->apertures->ranges[0].size = rdev->mc.aper_size; @@ -87713,7 +87633,7 @@ if (info->screen_base == NULL) { ret = -ENOSPC; -@@ -271,7 +283,7 @@ static int radeonfb_create(struct radeon_fbdev *rfbdev, +@@ -271,7 +283,7 @@ DRM_INFO("vram apper at 0x%lX\n", (unsigned long)rdev->mc.aper_base); DRM_INFO("size %lu\n", (unsigned long)radeon_bo_size(rbo)); DRM_INFO("fb depth is %d\n", fb->depth); @@ -87722,10 +87642,10 @@ vga_switcheroo_client_fb_set(rdev->ddev->pdev, info); return 0; -diff --git a/drivers/gpu/drm/radeon/radeon_fence.c b/drivers/gpu/drm/radeon/radeon_fence.c -index 76ec0e9..4bd36a3 100644 ---- a/drivers/gpu/drm/radeon/radeon_fence.c -+++ b/drivers/gpu/drm/radeon/radeon_fence.c +Index: linux-3.2.46/drivers/gpu/drm/radeon/radeon_fence.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/radeon/radeon_fence.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/radeon/radeon_fence.c 2013-07-26 19:26:24.000000000 +0000 @@ -40,32 +40,24 @@ #include "radeon.h" #include "radeon_trace.h" @@ -87770,7 +87690,7 @@ return seq; } -@@ -73,28 +65,28 @@ int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence) +@@ -73,28 +65,28 @@ { unsigned long irq_flags; @@ -87810,7 +87730,7 @@ { struct radeon_fence *fence; struct list_head *i, *n; -@@ -102,34 +94,34 @@ static bool radeon_fence_poll_locked(struct radeon_device *rdev) +@@ -102,34 +94,34 @@ bool wake = false; unsigned long cjiffies; @@ -87857,7 +87777,7 @@ fence = list_entry(i, struct radeon_fence, list); if (fence->seq == seq) { n = i; -@@ -141,11 +133,11 @@ static bool radeon_fence_poll_locked(struct radeon_device *rdev) +@@ -141,11 +133,11 @@ i = n; do { n = i->prev; @@ -87871,7 +87791,7 @@ wake = true; } return wake; -@@ -157,14 +149,18 @@ static void radeon_fence_destroy(struct kref *kref) +@@ -157,14 +149,18 @@ struct radeon_fence *fence; fence = container_of(kref, struct radeon_fence, kref); @@ -87894,7 +87814,7 @@ { unsigned long irq_flags; -@@ -174,18 +170,19 @@ int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence) +@@ -174,18 +170,19 @@ } kref_init(&((*fence)->kref)); (*fence)->rdev = rdev; @@ -87919,7 +87839,7 @@ bool radeon_fence_signaled(struct radeon_fence *fence) { unsigned long irq_flags; -@@ -197,21 +194,21 @@ bool radeon_fence_signaled(struct radeon_fence *fence) +@@ -197,21 +194,21 @@ if (fence->rdev->gpu_lockup) return true; @@ -87946,7 +87866,7 @@ return signaled; } -@@ -230,24 +227,24 @@ int radeon_fence_wait(struct radeon_fence *fence, bool intr) +@@ -230,24 +227,24 @@ if (radeon_fence_signaled(fence)) { return 0; } @@ -87979,7 +87899,7 @@ } trace_radeon_fence_wait_end(rdev->ddev, seq); if (unlikely(!radeon_fence_signaled(fence))) { -@@ -258,10 +255,11 @@ retry: +@@ -258,10 +255,11 @@ timeout = r; goto retry; } @@ -87993,7 +87913,7 @@ /* good news we believe it's a lockup */ printk(KERN_WARNING "GPU lockup (waiting for 0x%08X last fence id 0x%08X)\n", fence->seq, seq); -@@ -272,20 +270,20 @@ retry: +@@ -272,20 +270,20 @@ r = radeon_gpu_reset(rdev); if (r) return r; @@ -88020,7 +87940,7 @@ { unsigned long irq_flags; struct radeon_fence *fence; -@@ -294,21 +292,21 @@ int radeon_fence_wait_next(struct radeon_device *rdev) +@@ -294,21 +292,21 @@ if (rdev->gpu_lockup) { return 0; } @@ -88048,7 +87968,7 @@ { unsigned long irq_flags; struct radeon_fence *fence; -@@ -317,15 +315,15 @@ int radeon_fence_wait_last(struct radeon_device *rdev) +@@ -317,15 +315,15 @@ if (rdev->gpu_lockup) { return 0; } @@ -88069,7 +87989,7 @@ r = radeon_fence_wait(fence, false); radeon_fence_unref(&fence); return r; -@@ -347,39 +345,97 @@ void radeon_fence_unref(struct radeon_fence **fence) +@@ -347,39 +345,97 @@ } } @@ -88127,6 +88047,15 @@ - dev_err(rdev->dev, "fence failed to get scratch register\n"); - write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags); - return r; +- } +- radeon_fence_write(rdev, 0); +- atomic_set(&rdev->fence_drv.seq, 0); +- INIT_LIST_HEAD(&rdev->fence_drv.created); +- INIT_LIST_HEAD(&rdev->fence_drv.emited); +- INIT_LIST_HEAD(&rdev->fence_drv.signaled); +- init_waitqueue_head(&rdev->fence_drv.queue); +- rdev->fence_drv.initialized = true; +- write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags); + write_lock_irqsave(&rdev->fence_lock, irq_flags); + radeon_scratch_free(rdev, rdev->fence_drv[ring].scratch_reg); + if (rdev->wb.use_event) { @@ -88174,24 +88103,17 @@ + write_lock_irqsave(&rdev->fence_lock, irq_flags); + for (ring = 0; ring < RADEON_NUM_RINGS; ring++) { + radeon_fence_driver_init_ring(rdev, ring); - } -- radeon_fence_write(rdev, 0); -- atomic_set(&rdev->fence_drv.seq, 0); -- INIT_LIST_HEAD(&rdev->fence_drv.created); -- INIT_LIST_HEAD(&rdev->fence_drv.emited); -- INIT_LIST_HEAD(&rdev->fence_drv.signaled); -- init_waitqueue_head(&rdev->fence_drv.queue); -- rdev->fence_drv.initialized = true; -- write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags); ++ } + write_unlock_irqrestore(&rdev->fence_lock, irq_flags); if (radeon_debugfs_fence_init(rdev)) { dev_err(rdev->dev, "fence debugfs file creation failed\n"); } -@@ -389,14 +445,18 @@ int radeon_fence_driver_init(struct radeon_device *rdev) +@@ -389,14 +445,18 @@ void radeon_fence_driver_fini(struct radeon_device *rdev) { unsigned long irq_flags; -- ++ int ring; + - if (!rdev->fence_drv.initialized) - return; - wake_up_all(&rdev->fence_drv.queue); @@ -88199,8 +88121,6 @@ - radeon_scratch_free(rdev, rdev->fence_drv.scratch_reg); - write_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags); - rdev->fence_drv.initialized = false; -+ int ring; -+ + for (ring = 0; ring < RADEON_NUM_RINGS; ring++) { + if (!rdev->fence_drv[ring].initialized) + continue; @@ -88214,11 +88134,12 @@ } -@@ -410,14 +470,21 @@ static int radeon_debugfs_fence_info(struct seq_file *m, void *data) +@@ -410,14 +470,21 @@ struct drm_device *dev = node->minor->dev; struct radeon_device *rdev = dev->dev_private; struct radeon_fence *fence; -- ++ int i; + - seq_printf(m, "Last signaled fence 0x%08X\n", - radeon_fence_read(rdev)); - if (!list_empty(&rdev->fence_drv.emited)) { @@ -88226,8 +88147,6 @@ - struct radeon_fence, list); - seq_printf(m, "Last emited fence %p with 0x%08X\n", - fence, fence->seq); -+ int i; -+ + for (i = 0; i < RADEON_NUM_RINGS; ++i) { + if (!rdev->fence_drv[i].initialized) + continue; @@ -88244,11 +88163,11 @@ } return 0; } -diff --git a/drivers/gpu/drm/radeon/radeon_gart.c b/drivers/gpu/drm/radeon/radeon_gart.c -index ba7ab79..2a4c592 100644 ---- a/drivers/gpu/drm/radeon/radeon_gart.c -+++ b/drivers/gpu/drm/radeon/radeon_gart.c -@@ -157,9 +157,6 @@ void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset, +Index: linux-3.2.46/drivers/gpu/drm/radeon/radeon_gart.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/radeon/radeon_gart.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/radeon/radeon_gart.c 2013-07-26 19:26:24.000000000 +0000 +@@ -157,9 +157,6 @@ p = t / (PAGE_SIZE / RADEON_GPU_PAGE_SIZE); for (i = 0; i < pages; i++, p++) { if (rdev->gart.pages[p]) { @@ -88258,7 +88177,7 @@ rdev->gart.pages[p] = NULL; rdev->gart.pages_addr[p] = rdev->dummy_page.addr; page_base = rdev->gart.pages_addr[p]; -@@ -191,23 +188,7 @@ int radeon_gart_bind(struct radeon_device *rdev, unsigned offset, +@@ -191,23 +188,7 @@ p = t / (PAGE_SIZE / RADEON_GPU_PAGE_SIZE); for (i = 0; i < pages; i++, p++) { @@ -88283,7 +88202,7 @@ rdev->gart.pages[p] = pagelist[i]; if (rdev->gart.ptr) { page_base = rdev->gart.pages_addr[p]; -@@ -274,12 +255,6 @@ int radeon_gart_init(struct radeon_device *rdev) +@@ -274,12 +255,6 @@ radeon_gart_fini(rdev); return -ENOMEM; } @@ -88296,7 +88215,7 @@ /* set GART entry to point to the dummy page by default */ for (i = 0; i < rdev->gart.num_cpu_pages; i++) { rdev->gart.pages_addr[i] = rdev->dummy_page.addr; -@@ -296,10 +271,418 @@ void radeon_gart_fini(struct radeon_device *rdev) +@@ -296,10 +271,418 @@ rdev->gart.ready = false; kfree(rdev->gart.pages); kfree(rdev->gart.pages_addr); @@ -88717,11 +88636,11 @@ + } + mutex_unlock(&vm->mutex); +} -diff --git a/drivers/gpu/drm/radeon/radeon_gem.c b/drivers/gpu/drm/radeon/radeon_gem.c -index aa1ca2d..c7008b5 100644 ---- a/drivers/gpu/drm/radeon/radeon_gem.c -+++ b/drivers/gpu/drm/radeon/radeon_gem.c -@@ -75,32 +75,6 @@ int radeon_gem_object_create(struct radeon_device *rdev, int size, +Index: linux-3.2.46/drivers/gpu/drm/radeon/radeon_gem.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/radeon/radeon_gem.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/radeon/radeon_gem.c 2013-07-26 19:26:24.000000000 +0000 +@@ -75,32 +75,6 @@ return 0; } @@ -88754,7 +88673,7 @@ int radeon_gem_set_domain(struct drm_gem_object *gobj, uint32_t rdomain, uint32_t wdomain) { -@@ -142,6 +116,44 @@ void radeon_gem_fini(struct radeon_device *rdev) +@@ -142,6 +116,44 @@ radeon_bo_force_delete(rdev); } @@ -88799,7 +88718,7 @@ /* * GEM ioctls. -@@ -152,6 +164,7 @@ int radeon_gem_info_ioctl(struct drm_device *dev, void *data, +@@ -152,6 +164,7 @@ struct radeon_device *rdev = dev->dev_private; struct drm_radeon_gem_info *args = data; struct ttm_mem_type_manager *man; @@ -88807,7 +88726,7 @@ man = &rdev->mman.bdev.man[TTM_PL_VRAM]; -@@ -160,8 +173,9 @@ int radeon_gem_info_ioctl(struct drm_device *dev, void *data, +@@ -160,8 +173,9 @@ if (rdev->stollen_vga_memory) args->vram_visible -= radeon_bo_size(rdev->stollen_vga_memory); args->vram_visible -= radeon_fbdev_total_size(rdev); @@ -88819,10 +88738,11 @@ return 0; } -@@ -352,6 +366,109 @@ out: +@@ -351,6 +365,109 @@ + drm_gem_object_unreference_unlocked(gobj); return r; } - ++ +int radeon_gem_va_ioctl(struct drm_device *dev, void *data, + struct drm_file *filp) +{ @@ -88925,14 +88845,13 @@ + drm_gem_object_unreference_unlocked(gobj); + return r; +} -+ + int radeon_mode_dumb_create(struct drm_file *file_priv, struct drm_device *dev, - struct drm_mode_create_dumb *args) -diff --git a/drivers/gpu/drm/radeon/radeon_i2c.c b/drivers/gpu/drm/radeon/radeon_i2c.c -index cf20351..6076e85 100644 ---- a/drivers/gpu/drm/radeon/radeon_i2c.c -+++ b/drivers/gpu/drm/radeon/radeon_i2c.c +Index: linux-3.2.46/drivers/gpu/drm/radeon/radeon_i2c.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/radeon/radeon_i2c.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/radeon/radeon_i2c.c 2013-07-26 19:26:24.000000000 +0000 @@ -26,10 +26,15 @@ #include @@ -88949,7 +88868,7 @@ /** * radeon_ddc_probe * -@@ -41,13 +46,13 @@ bool radeon_ddc_probe(struct radeon_connector *radeon_connector, bool use_aux) +@@ -41,13 +46,13 @@ int ret; struct i2c_msg msgs[] = { { @@ -88965,7 +88884,7 @@ .flags = I2C_M_RD, .len = 8, .buf = buf, -@@ -888,6 +893,11 @@ static const struct i2c_algorithm radeon_i2c_algo = { +@@ -888,6 +893,11 @@ .functionality = radeon_hw_i2c_func, }; @@ -88977,7 +88896,7 @@ struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev, struct radeon_i2c_bus_rec *rec, const char *name) -@@ -907,6 +917,7 @@ struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev, +@@ -907,6 +917,7 @@ i2c->rec = *rec; i2c->adapter.owner = THIS_MODULE; i2c->adapter.class = I2C_CLASS_DDC; @@ -88985,7 +88904,7 @@ i2c->dev = dev; i2c_set_adapdata(&i2c->adapter, i2c); if (rec->mm_i2c || -@@ -923,6 +934,18 @@ struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev, +@@ -923,6 +934,18 @@ DRM_ERROR("Failed to register hw i2c %s\n", name); goto out_free; } @@ -89004,7 +88923,7 @@ } else { /* set the radeon bit adapter */ snprintf(i2c->adapter.name, sizeof(i2c->adapter.name), -@@ -934,10 +957,8 @@ struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev, +@@ -934,10 +957,8 @@ i2c->algo.bit.setscl = set_clock; i2c->algo.bit.getsda = get_data; i2c->algo.bit.getscl = get_clock; @@ -89017,7 +88936,7 @@ i2c->algo.bit.data = i2c; ret = i2c_bit_add_bus(&i2c->adapter); if (ret) { -@@ -967,6 +988,7 @@ struct radeon_i2c_chan *radeon_i2c_create_dp(struct drm_device *dev, +@@ -967,6 +988,7 @@ i2c->rec = *rec; i2c->adapter.owner = THIS_MODULE; i2c->adapter.class = I2C_CLASS_DDC; @@ -89025,11 +88944,11 @@ i2c->dev = dev; snprintf(i2c->adapter.name, sizeof(i2c->adapter.name), "Radeon aux bus %s", name); -diff --git a/drivers/gpu/drm/radeon/radeon_irq_kms.c b/drivers/gpu/drm/radeon/radeon_irq_kms.c -index 4f9496e..645dcbf 100644 ---- a/drivers/gpu/drm/radeon/radeon_irq_kms.c -+++ b/drivers/gpu/drm/radeon/radeon_irq_kms.c -@@ -65,7 +65,8 @@ void radeon_driver_irq_preinstall_kms(struct drm_device *dev) +Index: linux-3.2.46/drivers/gpu/drm/radeon/radeon_irq_kms.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/radeon/radeon_irq_kms.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/radeon/radeon_irq_kms.c 2013-07-26 19:26:24.000000000 +0000 +@@ -65,7 +65,8 @@ unsigned i; /* Disable *all* interrupts */ @@ -89039,7 +88958,7 @@ rdev->irq.gui_idle = false; for (i = 0; i < RADEON_MAX_HPD_PINS; i++) rdev->irq.hpd[i] = false; -@@ -81,9 +82,11 @@ void radeon_driver_irq_preinstall_kms(struct drm_device *dev) +@@ -81,9 +82,11 @@ int radeon_driver_irq_postinstall_kms(struct drm_device *dev) { struct radeon_device *rdev = dev->dev_private; @@ -89052,7 +88971,7 @@ radeon_irq_set(rdev); return 0; } -@@ -97,7 +100,8 @@ void radeon_driver_irq_uninstall_kms(struct drm_device *dev) +@@ -97,7 +100,8 @@ return; } /* Disable *all* interrupts */ @@ -89062,7 +88981,7 @@ rdev->irq.gui_idle = false; for (i = 0; i < RADEON_MAX_HPD_PINS; i++) rdev->irq.hpd[i] = false; -@@ -216,26 +220,26 @@ void radeon_irq_kms_fini(struct radeon_device *rdev) +@@ -216,26 +220,26 @@ flush_work_sync(&rdev->hotplug_work); } @@ -89096,11 +89015,11 @@ radeon_irq_set(rdev); } spin_unlock_irqrestore(&rdev->irq.sw_lock, irqflags); -diff --git a/drivers/gpu/drm/radeon/radeon_kms.c b/drivers/gpu/drm/radeon/radeon_kms.c -index 4bb9e27..3c2628b 100644 ---- a/drivers/gpu/drm/radeon/radeon_kms.c -+++ b/drivers/gpu/drm/radeon/radeon_kms.c -@@ -39,12 +39,8 @@ int radeon_driver_unload_kms(struct drm_device *dev) +Index: linux-3.2.46/drivers/gpu/drm/radeon/radeon_kms.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/radeon/radeon_kms.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/radeon/radeon_kms.c 2013-07-26 19:26:24.000000000 +0000 +@@ -39,12 +39,8 @@ if (rdev == NULL) return 0; @@ -89113,7 +89032,7 @@ kfree(rdev); dev->dev_private = NULL; return 0; -@@ -61,6 +57,8 @@ int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags) +@@ -61,6 +57,8 @@ } dev->dev_private = (void *)rdev; @@ -89122,7 +89041,7 @@ /* update BUS flag */ if (drm_pci_device_is_agp(dev)) { flags |= RADEON_IS_AGP; -@@ -173,7 +171,9 @@ int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) +@@ -173,7 +171,9 @@ value = rdev->accel_working; break; case RADEON_INFO_TILING_CONFIG: @@ -89133,7 +89052,7 @@ value = rdev->config.cayman.tile_config; else if (rdev->family >= CHIP_CEDAR) value = rdev->config.evergreen.tile_config; -@@ -212,7 +212,10 @@ int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) +@@ -212,7 +212,10 @@ value = rdev->clock.spll.reference_freq * 10; break; case RADEON_INFO_NUM_BACKENDS: @@ -89145,7 +89064,7 @@ value = rdev->config.cayman.max_backends_per_se * rdev->config.cayman.max_shader_engines; else if (rdev->family >= CHIP_CEDAR) -@@ -226,7 +229,9 @@ int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) +@@ -226,7 +229,9 @@ } break; case RADEON_INFO_NUM_TILE_PIPES: @@ -89156,7 +89075,7 @@ value = rdev->config.cayman.max_tile_pipes; else if (rdev->family >= CHIP_CEDAR) value = rdev->config.evergreen.max_tile_pipes; -@@ -242,7 +247,9 @@ int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) +@@ -242,7 +247,9 @@ value = 1; break; case RADEON_INFO_BACKEND_MAP: @@ -89167,7 +89086,7 @@ value = rdev->config.cayman.backend_map; else if (rdev->family >= CHIP_CEDAR) value = rdev->config.evergreen.backend_map; -@@ -254,6 +261,33 @@ int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) +@@ -254,6 +261,33 @@ return -EINVAL; } break; @@ -89201,7 +89120,7 @@ default: DRM_DEBUG_KMS("Invalid request %d\n", info->request); return -EINVAL; -@@ -274,7 +308,6 @@ int radeon_driver_firstopen_kms(struct drm_device *dev) +@@ -274,7 +308,6 @@ return 0; } @@ -89209,7 +89128,7 @@ void radeon_driver_lastclose_kms(struct drm_device *dev) { vga_switcheroo_process_delayed_switch(); -@@ -282,12 +315,45 @@ void radeon_driver_lastclose_kms(struct drm_device *dev) +@@ -282,12 +315,45 @@ int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv) { @@ -89255,18 +89174,18 @@ } void radeon_driver_preclose_kms(struct drm_device *dev, -@@ -455,5 +521,6 @@ struct drm_ioctl_desc radeon_ioctls_kms[] = { +@@ -455,5 +521,6 @@ DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_TILING, radeon_gem_set_tiling_ioctl, DRM_AUTH|DRM_UNLOCKED), DRM_IOCTL_DEF_DRV(RADEON_GEM_GET_TILING, radeon_gem_get_tiling_ioctl, DRM_AUTH|DRM_UNLOCKED), DRM_IOCTL_DEF_DRV(RADEON_GEM_BUSY, radeon_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED), + DRM_IOCTL_DEF_DRV(RADEON_GEM_VA, radeon_gem_va_ioctl, DRM_AUTH|DRM_UNLOCKED), }; int radeon_max_kms_ioctl = DRM_ARRAY_SIZE(radeon_ioctls_kms); -diff --git a/drivers/gpu/drm/radeon/radeon_legacy_crtc.c b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c -index daadf21..9760e5a 100644 ---- a/drivers/gpu/drm/radeon/radeon_legacy_crtc.c -+++ b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c -@@ -419,7 +419,9 @@ int radeon_crtc_do_set_base(struct drm_crtc *crtc, +Index: linux-3.2.46/drivers/gpu/drm/radeon/radeon_legacy_crtc.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/radeon/radeon_legacy_crtc.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/radeon/radeon_legacy_crtc.c 2013-07-26 19:26:24.000000000 +0000 +@@ -419,7 +419,9 @@ r = radeon_bo_reserve(rbo, false); if (unlikely(r != 0)) return r; @@ -89277,7 +89196,7 @@ if (unlikely(r != 0)) { radeon_bo_unreserve(rbo); return -EINVAL; -@@ -437,7 +439,7 @@ int radeon_crtc_do_set_base(struct drm_crtc *crtc, +@@ -437,7 +439,7 @@ crtc_offset_cntl = 0; @@ -89286,7 +89205,7 @@ crtc_pitch = (((pitch_pixels * target_fb->bits_per_pixel) + ((target_fb->bits_per_pixel * 8) - 1)) / (target_fb->bits_per_pixel * 8)); -@@ -1023,9 +1025,11 @@ static int radeon_crtc_mode_set(struct drm_crtc *crtc, +@@ -1023,9 +1025,11 @@ static void radeon_crtc_prepare(struct drm_crtc *crtc) { @@ -89298,7 +89217,7 @@ /* * The hardware wedges sometimes if you reconfigure one CRTC * whilst another is running (see fdo bug #24611). -@@ -1036,6 +1040,7 @@ static void radeon_crtc_prepare(struct drm_crtc *crtc) +@@ -1036,6 +1040,7 @@ static void radeon_crtc_commit(struct drm_crtc *crtc) { @@ -89306,7 +89225,7 @@ struct drm_device *dev = crtc->dev; struct drm_crtc *crtci; -@@ -1046,6 +1051,7 @@ static void radeon_crtc_commit(struct drm_crtc *crtc) +@@ -1046,6 +1051,7 @@ if (crtci->enabled) radeon_crtc_dpms(crtci, DRM_MODE_DPMS_ON); } @@ -89314,11 +89233,11 @@ } static const struct drm_crtc_helper_funcs legacy_helper_funcs = { -diff --git a/drivers/gpu/drm/radeon/radeon_legacy_encoders.c b/drivers/gpu/drm/radeon/radeon_legacy_encoders.c -index a906803..53b07a3 100644 ---- a/drivers/gpu/drm/radeon/radeon_legacy_encoders.c -+++ b/drivers/gpu/drm/radeon/radeon_legacy_encoders.c -@@ -88,7 +88,7 @@ static void radeon_legacy_lvds_update(struct drm_encoder *encoder, int mode) +Index: linux-3.2.46/drivers/gpu/drm/radeon/radeon_legacy_encoders.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/radeon/radeon_legacy_encoders.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/radeon/radeon_legacy_encoders.c 2013-07-26 19:26:24.000000000 +0000 +@@ -88,7 +88,7 @@ lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL); lvds_pll_cntl |= RADEON_LVDS_PLL_EN; WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl); @@ -89327,7 +89246,7 @@ lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL); lvds_pll_cntl &= ~RADEON_LVDS_PLL_RESET; -@@ -101,7 +101,7 @@ static void radeon_legacy_lvds_update(struct drm_encoder *encoder, int mode) +@@ -101,7 +101,7 @@ (backlight_level << RADEON_LVDS_BL_MOD_LEVEL_SHIFT)); if (is_mac) lvds_gen_cntl |= RADEON_LVDS_BL_MOD_EN; @@ -89336,7 +89255,7 @@ WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl); break; case DRM_MODE_DPMS_STANDBY: -@@ -118,10 +118,10 @@ static void radeon_legacy_lvds_update(struct drm_encoder *encoder, int mode) +@@ -118,10 +118,10 @@ WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl); lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN | RADEON_LVDS_DIGON); } @@ -89349,7 +89268,7 @@ break; } -@@ -665,7 +665,7 @@ static enum drm_connector_status radeon_legacy_primary_dac_detect(struct drm_enc +@@ -665,7 +665,7 @@ WREG32(RADEON_DAC_MACRO_CNTL, tmp); @@ -89358,7 +89277,7 @@ if (RREG32(RADEON_DAC_CNTL) & RADEON_DAC_CMP_OUTPUT) found = connector_status_connected; -@@ -1504,7 +1504,7 @@ static enum drm_connector_status radeon_legacy_tv_dac_detect(struct drm_encoder +@@ -1504,7 +1504,7 @@ tmp = dac_cntl2 | RADEON_DAC2_DAC2_CLK_SEL | RADEON_DAC2_CMP_EN; WREG32(RADEON_DAC_CNTL2, tmp); @@ -89367,11 +89286,11 @@ if (ASIC_IS_R300(rdev)) { if (RREG32(RADEON_DAC_CNTL2) & RADEON_DAC2_CMP_OUT_B) -diff --git a/drivers/gpu/drm/radeon/radeon_mode.h b/drivers/gpu/drm/radeon/radeon_mode.h -index bb42df4..dabfefd 100644 ---- a/drivers/gpu/drm/radeon/radeon_mode.h -+++ b/drivers/gpu/drm/radeon/radeon_mode.h -@@ -210,8 +210,6 @@ enum radeon_connector_table { +Index: linux-3.2.46/drivers/gpu/drm/radeon/radeon_mode.h +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/radeon/radeon_mode.h 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/radeon/radeon_mode.h 2013-07-26 19:26:24.000000000 +0000 +@@ -210,8 +210,6 @@ CT_RN50_POWER, CT_MAC_X800, CT_MAC_G5_9600, @@ -89380,7 +89299,7 @@ }; enum radeon_dvo_chip { -@@ -268,6 +266,7 @@ struct radeon_crtc { +@@ -268,6 +266,7 @@ u16 lut_r[256], lut_g[256], lut_b[256]; bool enabled; bool can_tile; @@ -89388,7 +89307,7 @@ uint32_t crtc_offset; struct drm_gem_object *cursor_bo; uint64_t cursor_addr; -@@ -469,6 +468,10 @@ radeon_atombios_get_tv_info(struct radeon_device *rdev); +@@ -469,6 +468,10 @@ extern struct drm_connector * radeon_get_connector_for_encoder(struct drm_encoder *encoder); @@ -89399,7 +89318,7 @@ extern u16 radeon_encoder_get_dp_bridge_encoder_id(struct drm_encoder *encoder); extern u16 radeon_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector); -@@ -489,6 +492,7 @@ extern int radeon_dp_get_panel_mode(struct drm_encoder *encoder, +@@ -489,6 +492,7 @@ struct drm_connector *connector); extern void atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode); extern void radeon_atom_encoder_init(struct radeon_device *rdev); @@ -89407,7 +89326,7 @@ extern void atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set); -@@ -646,9 +650,9 @@ extern void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, +@@ -646,9 +650,9 @@ u16 blue, int regno); extern void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, u16 *blue, int regno); @@ -89419,11 +89338,11 @@ struct drm_gem_object *obj); int radeonfb_remove(struct drm_device *dev, struct drm_framebuffer *fb); -diff --git a/drivers/gpu/drm/radeon/radeon_object.c b/drivers/gpu/drm/radeon/radeon_object.c -index f3ae607..df6a4db 100644 ---- a/drivers/gpu/drm/radeon/radeon_object.c -+++ b/drivers/gpu/drm/radeon/radeon_object.c -@@ -46,6 +46,20 @@ static void radeon_bo_clear_surface_reg(struct radeon_bo *bo); +Index: linux-3.2.46/drivers/gpu/drm/radeon/radeon_object.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/radeon/radeon_object.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/radeon/radeon_object.c 2013-07-26 19:26:24.000000000 +0000 +@@ -46,6 +46,20 @@ * function are calling it. */ @@ -89444,7 +89363,7 @@ static void radeon_ttm_bo_destroy(struct ttm_buffer_object *tbo) { struct radeon_bo *bo; -@@ -55,6 +69,7 @@ static void radeon_ttm_bo_destroy(struct ttm_buffer_object *tbo) +@@ -55,6 +69,7 @@ list_del_init(&bo->list); mutex_unlock(&bo->rdev->gem.mutex); radeon_bo_clear_surface_reg(bo); @@ -89452,7 +89371,7 @@ drm_gem_object_release(&bo->gem_base); kfree(bo); } -@@ -95,6 +110,7 @@ int radeon_bo_create(struct radeon_device *rdev, +@@ -95,6 +110,7 @@ enum ttm_bo_type type; unsigned long page_align = roundup(byte_align, PAGE_SIZE) >> PAGE_SHIFT; unsigned long max_size = 0; @@ -89460,7 +89379,7 @@ int r; size = ALIGN(size, PAGE_SIZE); -@@ -117,6 +133,9 @@ int radeon_bo_create(struct radeon_device *rdev, +@@ -117,6 +133,9 @@ return -ENOMEM; } @@ -89470,7 +89389,7 @@ retry: bo = kzalloc(sizeof(struct radeon_bo), GFP_KERNEL); if (bo == NULL) -@@ -130,12 +149,13 @@ retry: +@@ -130,12 +149,13 @@ bo->gem_base.driver_private = NULL; bo->surface_reg = -1; INIT_LIST_HEAD(&bo->list); @@ -89486,7 +89405,7 @@ mutex_unlock(&rdev->vram_mutex); if (unlikely(r != 0)) { if (r != -ERESTARTSYS) { -@@ -213,7 +233,18 @@ int radeon_bo_pin_restricted(struct radeon_bo *bo, u32 domain, u64 max_offset, +@@ -213,7 +233,18 @@ bo->pin_count++; if (gpu_addr) *gpu_addr = radeon_bo_gpu_offset(bo); @@ -89506,7 +89425,7 @@ return 0; } radeon_ttm_placement_from_domain(bo, domain); -@@ -441,8 +472,54 @@ static void radeon_bo_clear_surface_reg(struct radeon_bo *bo) +@@ -441,8 +472,54 @@ int radeon_bo_set_tiling_flags(struct radeon_bo *bo, uint32_t tiling_flags, uint32_t pitch) { @@ -89561,7 +89480,7 @@ r = radeon_bo_reserve(bo, false); if (unlikely(r != 0)) return r; -@@ -499,6 +576,7 @@ void radeon_bo_move_notify(struct ttm_buffer_object *bo, +@@ -499,6 +576,7 @@ return; rbo = container_of(bo, struct radeon_bo, tbo); radeon_bo_check_tiling(rbo, 0, 1); @@ -89569,7 +89488,7 @@ } int radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo) -@@ -572,3 +650,16 @@ int radeon_bo_reserve(struct radeon_bo *bo, bool no_wait) +@@ -572,3 +650,16 @@ } return 0; } @@ -89586,11 +89505,11 @@ + } + return NULL; +} -diff --git a/drivers/gpu/drm/radeon/radeon_object.h b/drivers/gpu/drm/radeon/radeon_object.h -index fb3f433..f9104be 100644 ---- a/drivers/gpu/drm/radeon/radeon_object.h -+++ b/drivers/gpu/drm/radeon/radeon_object.h -@@ -83,6 +83,16 @@ static inline bool radeon_bo_is_reserved(struct radeon_bo *bo) +Index: linux-3.2.46/drivers/gpu/drm/radeon/radeon_object.h +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/radeon/radeon_object.h 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/radeon/radeon_object.h 2013-07-26 19:26:24.000000000 +0000 +@@ -83,6 +83,16 @@ return !!atomic_read(&bo->tbo.reserved); } @@ -89607,7 +89526,7 @@ /** * radeon_bo_mmap_offset - return mmap offset of bo * @bo: radeon object for which we query the offset -@@ -130,4 +140,26 @@ extern void radeon_bo_move_notify(struct ttm_buffer_object *bo, +@@ -130,4 +140,26 @@ struct ttm_mem_reg *mem); extern int radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo); extern int radeon_bo_get_surface_reg(struct radeon_bo *bo); @@ -89634,11 +89553,11 @@ + struct radeon_sa_bo *sa_bo); + #endif -diff --git a/drivers/gpu/drm/radeon/radeon_pm.c b/drivers/gpu/drm/radeon/radeon_pm.c -index d58eccb..bf6ca2d 100644 ---- a/drivers/gpu/drm/radeon/radeon_pm.c -+++ b/drivers/gpu/drm/radeon/radeon_pm.c -@@ -221,7 +221,7 @@ static void radeon_set_power_state(struct radeon_device *rdev) +Index: linux-3.2.46/drivers/gpu/drm/radeon/radeon_pm.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/radeon/radeon_pm.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/radeon/radeon_pm.c 2013-07-26 19:26:24.000000000 +0000 +@@ -221,7 +221,7 @@ } /* set memory clock */ @@ -89647,7 +89566,7 @@ radeon_pm_debug_check_in_vbl(rdev, false); radeon_set_memory_clock(rdev, mclk); radeon_pm_debug_check_in_vbl(rdev, true); -@@ -252,7 +252,10 @@ static void radeon_pm_set_clocks(struct radeon_device *rdev) +@@ -252,7 +252,10 @@ mutex_lock(&rdev->ddev->struct_mutex); mutex_lock(&rdev->vram_mutex); @@ -89659,7 +89578,7 @@ /* gui idle int has issues on older chips it seems */ if (rdev->family >= CHIP_R600) { -@@ -268,12 +271,13 @@ static void radeon_pm_set_clocks(struct radeon_device *rdev) +@@ -268,12 +271,13 @@ radeon_irq_set(rdev); } } else { @@ -89677,7 +89596,7 @@ radeon_fence_wait(fence, false); radeon_fence_unref(&fence); } -@@ -307,7 +311,10 @@ static void radeon_pm_set_clocks(struct radeon_device *rdev) +@@ -307,7 +311,10 @@ rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE; @@ -89689,7 +89608,7 @@ mutex_unlock(&rdev->vram_mutex); mutex_unlock(&rdev->ddev->struct_mutex); } -@@ -467,6 +474,9 @@ static ssize_t radeon_hwmon_show_temp(struct device *dev, +@@ -467,6 +474,9 @@ case THERMAL_TYPE_SUMO: temp = sumo_get_temp(rdev); break; @@ -89699,7 +89618,7 @@ default: temp = 0; break; -@@ -507,6 +517,10 @@ static int radeon_hwmon_init(struct radeon_device *rdev) +@@ -507,6 +517,10 @@ case THERMAL_TYPE_EVERGREEN: case THERMAL_TYPE_NI: case THERMAL_TYPE_SUMO: @@ -89710,7 +89629,7 @@ rdev->pm.int_hwmon_dev = hwmon_device_register(rdev->dev); if (IS_ERR(rdev->pm.int_hwmon_dev)) { err = PTR_ERR(rdev->pm.int_hwmon_dev); -@@ -799,19 +813,14 @@ static void radeon_dynpm_idle_work_handler(struct work_struct *work) +@@ -799,19 +813,14 @@ resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev); mutex_lock(&rdev->pm.mutex); if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) { @@ -89735,7 +89654,7 @@ if (not_processed >= 3) { /* should upclock */ if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_DOWNCLOCK) { -@@ -869,11 +878,11 @@ static int radeon_debugfs_pm_info(struct seq_file *m, void *data) +@@ -869,11 +878,11 @@ else seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev)); seq_printf(m, "default memory clock: %u0 kHz\n", rdev->pm.default_mclk); @@ -89749,10 +89668,10 @@ seq_printf(m, "PCIE lanes: %d\n", radeon_get_pcie_lanes(rdev)); return 0; -diff --git a/drivers/gpu/drm/radeon/radeon_reg.h b/drivers/gpu/drm/radeon/radeon_reg.h -index b4ce864..5d8f735 100644 ---- a/drivers/gpu/drm/radeon/radeon_reg.h -+++ b/drivers/gpu/drm/radeon/radeon_reg.h +Index: linux-3.2.46/drivers/gpu/drm/radeon/radeon_reg.h +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/radeon/radeon_reg.h 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/radeon/radeon_reg.h 2013-07-26 19:26:24.000000000 +0000 @@ -56,6 +56,7 @@ #include "r600_reg.h" #include "evergreen_reg.h" @@ -89773,10 +89692,10 @@ # define RADEON_CRTC2_VBLANK_SAVE (1 << 1) # define RADEON_CRTC2_VBLANK_SAVE_CLEAR (1 << 1) #define RADEON_CRTC_V_SYNC_STRT_WID 0x020c -diff --git a/drivers/gpu/drm/radeon/radeon_ring.c b/drivers/gpu/drm/radeon/radeon_ring.c -index 65be5e8..33eff8b 100644 ---- a/drivers/gpu/drm/radeon/radeon_ring.c -+++ b/drivers/gpu/drm/radeon/radeon_ring.c +Index: linux-3.2.46/drivers/gpu/drm/radeon/radeon_ring.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/radeon/radeon_ring.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/radeon/radeon_ring.c 2013-07-26 19:26:24.000000000 +0000 @@ -34,6 +34,7 @@ #include "atom.h" @@ -89785,7 +89704,7 @@ u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx) { -@@ -60,105 +61,107 @@ u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx) +@@ -60,105 +61,107 @@ return idx_value; } @@ -89809,22 +89728,31 @@ } -void radeon_ib_bogus_cleanup(struct radeon_device *rdev) --{ ++/* ++ * IB. ++ */ ++bool radeon_ib_try_free(struct radeon_device *rdev, struct radeon_ib *ib) + { - struct radeon_ib *ib, *n; -- ++ bool done = false; + - list_for_each_entry_safe(ib, n, &rdev->ib_pool.bogus_ib, list) { - list_del(&ib->list); - vfree(ib->ptr); - kfree(ib); -- } --} -- ++ /* only free ib which have been emited */ ++ if (ib->fence && ib->fence->emitted) { ++ if (radeon_fence_signaled(ib->fence)) { ++ radeon_fence_unref(&ib->fence); ++ radeon_sa_bo_free(rdev, &ib->sa_bo); ++ done = true; ++ } + } ++ return done; + } + -void radeon_ib_bogus_add(struct radeon_device *rdev, struct radeon_ib *ib) -+/* -+ * IB. -+ */ -+bool radeon_ib_try_free(struct radeon_device *rdev, struct radeon_ib *ib) - { +-{ - struct radeon_ib *bib; - - bib = kmalloc(sizeof(*bib), GFP_KERNEL); @@ -89834,24 +89762,14 @@ - if (bib->ptr == NULL) { - kfree(bib); - return; -+ bool done = false; -+ -+ /* only free ib which have been emited */ -+ if (ib->fence && ib->fence->emitted) { -+ if (radeon_fence_signaled(ib->fence)) { -+ radeon_fence_unref(&ib->fence); -+ radeon_sa_bo_free(rdev, &ib->sa_bo); -+ done = true; -+ } - } +- } - memcpy(bib->ptr, ib->ptr, ib->length_dw * 4); - bib->length_dw = ib->length_dw; - mutex_lock(&rdev->ib_pool.mutex); - list_add_tail(&bib->list, &rdev->ib_pool.bogus_ib); - mutex_unlock(&rdev->ib_pool.mutex); -+ return done; - } - +-} +- -/* - * IB. - */ @@ -89969,7 +89887,7 @@ } void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib) -@@ -169,250 +172,261 @@ void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib) +@@ -169,250 +172,261 @@ if (tmp == NULL) { return; } @@ -90094,8 +90012,7 @@ { - int r; - struct radeon_bo *robj; -+ unsigned i; - +- - if (!rdev->ib_pool.ready) { - return; - } @@ -90104,7 +90021,8 @@ - robj = rdev->ib_pool.robj; - rdev->ib_pool.robj = NULL; - mutex_unlock(&rdev->ib_pool.mutex); -- ++ unsigned i; + - if (robj) { - r = radeon_bo_reserve(robj, false); - if (likely(r == 0)) { @@ -90122,13 +90040,13 @@ + rdev->ib_pool.ready = false; } + radeon_mutex_unlock(&rdev->ib_pool.mutex); -+} -+ + } + +int radeon_ib_pool_start(struct radeon_device *rdev) +{ + return radeon_sa_bo_manager_start(rdev, &rdev->ib_pool.sa_manager); - } - ++} ++ +int radeon_ib_pool_suspend(struct radeon_device *rdev) +{ + return radeon_sa_bo_manager_suspend(rdev, &rdev->ib_pool.sa_manager); @@ -90351,7 +90269,7 @@ if (ring_obj) { r = radeon_bo_reserve(ring_obj, false); -@@ -425,78 +439,96 @@ void radeon_ring_fini(struct radeon_device *rdev) +@@ -425,78 +439,96 @@ } } @@ -90482,11 +90400,10 @@ } return radeon_debugfs_add_files(rdev, radeon_debugfs_ib_list, RADEON_IB_POOL_SIZE); -diff --git a/drivers/gpu/drm/radeon/radeon_sa.c b/drivers/gpu/drm/radeon/radeon_sa.c -new file mode 100644 -index 0000000..4cce47e ---- /dev/null -+++ b/drivers/gpu/drm/radeon/radeon_sa.c +Index: linux-3.2.46/drivers/gpu/drm/radeon/radeon_sa.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/radeon/radeon_sa.c 2013-07-26 19:26:24.000000000 +0000 @@ -0,0 +1,189 @@ +/* + * Copyright 2011 Red Hat Inc. @@ -90677,11 +90594,10 @@ +{ + list_del_init(&sa_bo->list); +} -diff --git a/drivers/gpu/drm/radeon/radeon_semaphore.c b/drivers/gpu/drm/radeon/radeon_semaphore.c -new file mode 100644 -index 0000000..61dd4e3 ---- /dev/null -+++ b/drivers/gpu/drm/radeon/radeon_semaphore.c +Index: linux-3.2.46/drivers/gpu/drm/radeon/radeon_semaphore.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/radeon/radeon_semaphore.c 2013-07-26 19:26:24.000000000 +0000 @@ -0,0 +1,178 @@ +/* + * Copyright 2011 Christian König. @@ -90861,11 +90777,11 @@ + } + write_unlock_irqrestore(&rdev->semaphore_drv.lock, irq_flags); +} -diff --git a/drivers/gpu/drm/radeon/radeon_test.c b/drivers/gpu/drm/radeon/radeon_test.c -index 602fa35..dc5dcf4 100644 ---- a/drivers/gpu/drm/radeon/radeon_test.c -+++ b/drivers/gpu/drm/radeon/radeon_test.c -@@ -42,7 +42,9 @@ void radeon_test_moves(struct radeon_device *rdev) +Index: linux-3.2.46/drivers/gpu/drm/radeon/radeon_test.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/radeon/radeon_test.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/radeon/radeon_test.c 2013-07-26 19:26:24.000000000 +0000 +@@ -42,7 +42,9 @@ /* Number of tests = * (Total GTT - IB pool - writeback page - ring buffers) / test size */ @@ -90876,7 +90792,7 @@ if (rdev->wb.wb_obj) n -= RADEON_GPU_PAGE_SIZE; if (rdev->ih.ring_obj) -@@ -104,7 +106,7 @@ void radeon_test_moves(struct radeon_device *rdev) +@@ -104,7 +106,7 @@ radeon_bo_kunmap(gtt_obj[i]); @@ -90885,7 +90801,7 @@ if (r) { DRM_ERROR("Failed to create GTT->VRAM fence %d\n", i); goto out_cleanup; -@@ -153,7 +155,7 @@ void radeon_test_moves(struct radeon_device *rdev) +@@ -153,7 +155,7 @@ radeon_bo_kunmap(vram_obj); @@ -90894,7 +90810,7 @@ if (r) { DRM_ERROR("Failed to create VRAM->GTT fence %d\n", i); goto out_cleanup; -@@ -232,3 +234,264 @@ out_cleanup: +@@ -232,3 +234,264 @@ printk(KERN_WARNING "Error while testing BO move.\n"); } } @@ -91159,11 +91075,11 @@ + } + } +} -diff --git a/drivers/gpu/drm/radeon/radeon_ttm.c b/drivers/gpu/drm/radeon/radeon_ttm.c -index 0b5468b..49b55ed 100644 ---- a/drivers/gpu/drm/radeon/radeon_ttm.c -+++ b/drivers/gpu/drm/radeon/radeon_ttm.c -@@ -114,24 +114,6 @@ static void radeon_ttm_global_fini(struct radeon_device *rdev) +Index: linux-3.2.46/drivers/gpu/drm/radeon/radeon_ttm.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/radeon/radeon_ttm.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/radeon/radeon_ttm.c 2013-07-26 19:26:24.000000000 +0000 +@@ -114,24 +114,6 @@ } } @@ -91188,7 +91104,7 @@ static int radeon_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags) { return 0; -@@ -206,7 +188,7 @@ static void radeon_evict_flags(struct ttm_buffer_object *bo, +@@ -206,7 +188,7 @@ rbo = container_of(bo, struct radeon_bo, tbo); switch (bo->mem.mem_type) { case TTM_PL_VRAM: @@ -91197,7 +91113,7 @@ radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_CPU); else radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_GTT); -@@ -241,10 +223,10 @@ static int radeon_move_blit(struct ttm_buffer_object *bo, +@@ -241,10 +223,10 @@ struct radeon_device *rdev; uint64_t old_start, new_start; struct radeon_fence *fence; @@ -91210,7 +91126,7 @@ if (unlikely(r)) { return r; } -@@ -273,13 +255,43 @@ static int radeon_move_blit(struct ttm_buffer_object *bo, +@@ -273,13 +255,43 @@ DRM_ERROR("Unknown placement %d\n", old_mem->mem_type); return -EINVAL; } @@ -91256,7 +91172,7 @@ r = radeon_copy(rdev, old_start, new_start, new_mem->num_pages * (PAGE_SIZE / RADEON_GPU_PAGE_SIZE), /* GPU pages */ fence); -@@ -398,7 +410,8 @@ static int radeon_bo_move(struct ttm_buffer_object *bo, +@@ -398,7 +410,8 @@ radeon_move_null(bo, new_mem); return 0; } @@ -91266,7 +91182,7 @@ /* use memcpy */ goto memcpy; } -@@ -515,8 +528,166 @@ static bool radeon_sync_obj_signaled(void *sync_obj, void *sync_arg) +@@ -515,8 +528,166 @@ return radeon_fence_signaled((struct radeon_fence *)sync_obj); } @@ -91434,7 +91350,7 @@ .invalidate_caches = &radeon_invalidate_caches, .init_mem_type = &radeon_init_mem_type, .evict_flags = &radeon_evict_flags, -@@ -573,7 +744,7 @@ int radeon_ttm_init(struct radeon_device *rdev) +@@ -573,7 +744,7 @@ return r; } DRM_INFO("radeon: %uM of VRAM memory ready\n", @@ -91443,7 +91359,7 @@ r = ttm_bo_init_mm(&rdev->mman.bdev, TTM_PL_TT, rdev->mc.gtt_size >> PAGE_SHIFT); if (r) { -@@ -680,124 +851,6 @@ int radeon_mmap(struct file *filp, struct vm_area_struct *vma) +@@ -680,124 +851,6 @@ } @@ -91568,7 +91484,7 @@ #define RADEON_DEBUGFS_MEM_TYPES 2 #if defined(CONFIG_DEBUG_FS) -@@ -820,8 +873,8 @@ static int radeon_mm_dump_table(struct seq_file *m, void *data) +@@ -820,8 +873,8 @@ static int radeon_ttm_debugfs_init(struct radeon_device *rdev) { #if defined(CONFIG_DEBUG_FS) @@ -91579,7 +91495,7 @@ unsigned i; for (i = 0; i < RADEON_DEBUGFS_MEM_TYPES; i++) { -@@ -843,8 +896,17 @@ static int radeon_ttm_debugfs_init(struct radeon_device *rdev) +@@ -843,8 +896,17 @@ radeon_mem_types_list[i].name = radeon_mem_types_names[i]; radeon_mem_types_list[i].show = &ttm_page_alloc_debugfs; radeon_mem_types_list[i].driver_features = 0; @@ -91599,10 +91515,10 @@ #endif return 0; -diff --git a/drivers/gpu/drm/radeon/reg_srcs/cayman b/drivers/gpu/drm/radeon/reg_srcs/cayman -index 2316977..a072fa8 100644 ---- a/drivers/gpu/drm/radeon/reg_srcs/cayman -+++ b/drivers/gpu/drm/radeon/reg_srcs/cayman +Index: linux-3.2.46/drivers/gpu/drm/radeon/reg_srcs/cayman +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/radeon/reg_srcs/cayman 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/radeon/reg_srcs/cayman 2013-07-26 19:26:24.000000000 +0000 @@ -1,5 +1,9 @@ cayman 0x9400 0x0000802C GRBM_GFX_INDEX @@ -91613,7 +91529,7 @@ 0x000088B0 VGT_VTX_VECT_EJECT_REG 0x000088C4 VGT_CACHE_INVALIDATION 0x000088D4 VGT_GS_VERTEX_REUSE -@@ -77,7 +81,6 @@ cayman 0x9400 +@@ -77,7 +81,6 @@ 0x0002802C DB_DEPTH_CLEAR 0x00028030 PA_SC_SCREEN_SCISSOR_TL 0x00028034 PA_SC_SCREEN_SCISSOR_BR @@ -91621,7 +91537,7 @@ 0x00028140 SQ_ALU_CONST_BUFFER_SIZE_PS_0 0x00028144 SQ_ALU_CONST_BUFFER_SIZE_PS_1 0x00028148 SQ_ALU_CONST_BUFFER_SIZE_PS_2 -@@ -206,7 +209,6 @@ cayman 0x9400 +@@ -206,7 +209,6 @@ 0x00028344 PA_SC_VPORT_ZMAX_14 0x00028348 PA_SC_VPORT_ZMIN_15 0x0002834C PA_SC_VPORT_ZMAX_15 @@ -91629,7 +91545,7 @@ 0x00028354 SX_SURFACE_SYNC 0x0002835C SX_SCATTER_EXPORT_SIZE 0x00028380 SQ_VTX_SEMANTIC_0 -@@ -508,10 +510,16 @@ cayman 0x9400 +@@ -508,10 +510,16 @@ 0x00028AA8 IA_MULTI_VGT_PARAM 0x00028AB4 VGT_REUSE_OFF 0x00028AB8 VGT_VTX_CNT_EN @@ -91647,7 +91563,7 @@ 0x00028B38 VGT_GS_MAX_VERT_OUT 0x00028B54 VGT_SHADER_STAGES_EN 0x00028B58 VGT_LS_HS_CONFIG -@@ -551,6 +559,18 @@ cayman 0x9400 +@@ -551,6 +559,18 @@ 0x00028C34 PA_SC_AA_SAMPLE_LOCS_PIXEL_X1_Y1_3 0x00028C38 PA_SC_AA_MASK_X0_Y0_X1_Y0 0x00028C3C PA_SC_AA_MASK_X0_Y1_X1_Y1 @@ -91666,11 +91582,11 @@ 0x00028C8C CB_COLOR0_CLEAR_WORD0 0x00028C90 CB_COLOR0_CLEAR_WORD1 0x00028C94 CB_COLOR0_CLEAR_WORD2 -diff --git a/drivers/gpu/drm/radeon/reg_srcs/evergreen b/drivers/gpu/drm/radeon/reg_srcs/evergreen -index 161737a..b912a37 100644 ---- a/drivers/gpu/drm/radeon/reg_srcs/evergreen -+++ b/drivers/gpu/drm/radeon/reg_srcs/evergreen -@@ -4,6 +4,9 @@ evergreen 0x9400 +Index: linux-3.2.46/drivers/gpu/drm/radeon/reg_srcs/evergreen +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/radeon/reg_srcs/evergreen 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/radeon/reg_srcs/evergreen 2013-07-26 19:26:24.000000000 +0000 +@@ -4,6 +4,9 @@ 0x00008044 WAIT_UNTIL_POLL_CNTL 0x00008048 WAIT_UNTIL_POLL_MASK 0x0000804c WAIT_UNTIL_POLL_REFDATA @@ -91680,7 +91596,7 @@ 0x000088B0 VGT_VTX_VECT_EJECT_REG 0x000088C4 VGT_CACHE_INVALIDATION 0x000088D4 VGT_GS_VERTEX_REUSE -@@ -93,7 +96,6 @@ evergreen 0x9400 +@@ -93,7 +96,6 @@ 0x0002802C DB_DEPTH_CLEAR 0x00028030 PA_SC_SCREEN_SCISSOR_TL 0x00028034 PA_SC_SCREEN_SCISSOR_BR @@ -91688,7 +91604,7 @@ 0x00028140 SQ_ALU_CONST_BUFFER_SIZE_PS_0 0x00028144 SQ_ALU_CONST_BUFFER_SIZE_PS_1 0x00028148 SQ_ALU_CONST_BUFFER_SIZE_PS_2 -@@ -222,7 +224,6 @@ evergreen 0x9400 +@@ -222,7 +224,6 @@ 0x00028344 PA_SC_VPORT_ZMAX_14 0x00028348 PA_SC_VPORT_ZMIN_15 0x0002834C PA_SC_VPORT_ZMAX_15 @@ -91696,7 +91612,7 @@ 0x00028354 SX_SURFACE_SYNC 0x00028380 SQ_VTX_SEMANTIC_0 0x00028384 SQ_VTX_SEMANTIC_1 -@@ -518,10 +519,16 @@ evergreen 0x9400 +@@ -518,10 +519,16 @@ 0x00028AA4 VGT_INSTANCE_STEP_RATE_1 0x00028AB4 VGT_REUSE_OFF 0x00028AB8 VGT_VTX_CNT_EN @@ -91714,7 +91630,7 @@ 0x00028B38 VGT_GS_MAX_VERT_OUT 0x00028B54 VGT_SHADER_STAGES_EN 0x00028B58 VGT_LS_HS_CONFIG -@@ -554,6 +561,18 @@ evergreen 0x9400 +@@ -554,6 +561,18 @@ 0x00028C34 PA_SC_AA_SAMPLE_LOCS_6 0x00028C38 PA_SC_AA_SAMPLE_LOCS_7 0x00028C3C PA_SC_AA_MASK @@ -91733,11 +91649,11 @@ 0x00028C8C CB_COLOR0_CLEAR_WORD0 0x00028C90 CB_COLOR0_CLEAR_WORD1 0x00028C94 CB_COLOR0_CLEAR_WORD2 -diff --git a/drivers/gpu/drm/radeon/reg_srcs/r600 b/drivers/gpu/drm/radeon/reg_srcs/r600 -index 0380c5c..5e659b0 100644 ---- a/drivers/gpu/drm/radeon/reg_srcs/r600 -+++ b/drivers/gpu/drm/radeon/reg_srcs/r600 -@@ -3,6 +3,9 @@ r600 0x9400 +Index: linux-3.2.46/drivers/gpu/drm/radeon/reg_srcs/r600 +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/radeon/reg_srcs/r600 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/radeon/reg_srcs/r600 2013-07-26 19:26:24.000000000 +0000 +@@ -3,6 +3,9 @@ 0x00028230 R7xx_PA_SC_EDGERULE 0x000286C8 R7xx_SPI_THREAD_GROUPING 0x00008D8C R7xx_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ @@ -91747,7 +91663,7 @@ 0x000088C4 VGT_CACHE_INVALIDATION 0x00028A50 VGT_ENHANCE 0x000088CC VGT_ES_PER_GS -@@ -38,6 +41,13 @@ r600 0x9400 +@@ -38,6 +41,13 @@ 0x00028AB4 VGT_REUSE_OFF 0x00028AB8 VGT_VTX_CNT_EN 0x000088B0 VGT_VTX_VECT_EJECT_REG @@ -91761,7 +91677,7 @@ 0x00028810 PA_CL_CLIP_CNTL 0x00008A14 PA_CL_ENHANCE 0x00028C14 PA_CL_GB_HORZ_CLIP_ADJ -@@ -428,7 +438,7 @@ r600 0x9400 +@@ -428,7 +438,7 @@ 0x00028638 SPI_VS_OUT_ID_9 0x00028438 SX_ALPHA_REF 0x00028410 SX_ALPHA_TEST_CONTROL @@ -91770,7 +91686,7 @@ 0x00009014 SX_MEMORY_EXPORT_SIZE 0x00009604 TC_INVALIDATE 0x00009400 TD_FILTER4 -@@ -703,7 +713,6 @@ r600 0x9400 +@@ -703,7 +713,6 @@ 0x0000A710 TD_VS_SAMPLER17_BORDER_RED 0x00009508 TA_CNTL_AUX 0x0002802C DB_DEPTH_CLEAR @@ -91778,7 +91694,7 @@ 0x00028D34 DB_PREFETCH_LIMIT 0x00028D30 DB_PRELOAD_CONTROL 0x00028D0C DB_RENDER_CONTROL -@@ -743,14 +752,6 @@ r600 0x9400 +@@ -743,14 +752,6 @@ 0x00028114 CB_COLOR5_MASK 0x00028118 CB_COLOR6_MASK 0x0002811C CB_COLOR7_MASK @@ -91793,11 +91709,11 @@ 0x00028808 CB_COLOR_CONTROL 0x0002842C CB_FOG_BLUE 0x00028428 CB_FOG_GREEN -diff --git a/drivers/gpu/drm/radeon/rs400.c b/drivers/gpu/drm/radeon/rs400.c -index 06b90c8..4cf381b 100644 ---- a/drivers/gpu/drm/radeon/rs400.c -+++ b/drivers/gpu/drm/radeon/rs400.c -@@ -410,6 +410,12 @@ static int rs400_startup(struct radeon_device *rdev) +Index: linux-3.2.46/drivers/gpu/drm/radeon/rs400.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/radeon/rs400.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/radeon/rs400.c 2013-07-26 19:26:24.000000000 +0000 +@@ -410,6 +410,12 @@ if (r) return r; @@ -91810,7 +91726,7 @@ /* Enable IRQ */ r100_irq_set(rdev); rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); -@@ -419,16 +425,25 @@ static int rs400_startup(struct radeon_device *rdev) +@@ -419,16 +425,25 @@ dev_err(rdev->dev, "failed initializing CP (%d).\n", r); return r; } @@ -91838,7 +91754,7 @@ /* Make sur GART are not working */ rs400_gart_disable(rdev); /* Resume clock before doing reset */ -@@ -447,11 +462,18 @@ int rs400_resume(struct radeon_device *rdev) +@@ -447,11 +462,18 @@ r300_clock_startup(rdev); /* Initialize surface registers */ radeon_surface_init(rdev); @@ -91858,7 +91774,7 @@ r100_cp_disable(rdev); radeon_wb_disable(rdev); r100_irq_disable(rdev); -@@ -530,7 +552,14 @@ int rs400_init(struct radeon_device *rdev) +@@ -530,7 +552,14 @@ if (r) return r; r300_set_reg_safe(rdev); @@ -91873,10 +91789,10 @@ r = rs400_startup(rdev); if (r) { /* Somethings want wront with the accel init stop accel */ -diff --git a/drivers/gpu/drm/radeon/rs600.c b/drivers/gpu/drm/radeon/rs600.c -index ee898e9..d25cf86 100644 ---- a/drivers/gpu/drm/radeon/rs600.c -+++ b/drivers/gpu/drm/radeon/rs600.c +Index: linux-3.2.46/drivers/gpu/drm/radeon/rs600.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/radeon/rs600.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/radeon/rs600.c 2013-07-26 19:26:24.000000000 +0000 @@ -46,6 +46,25 @@ void rs600_gpu_init(struct radeon_device *rdev); int rs600_mc_wait_for_idle(struct radeon_device *rdev); @@ -91903,7 +91819,7 @@ void rs600_pre_page_flip(struct radeon_device *rdev, int crtc) { /* enable the pflip int */ -@@ -175,7 +194,7 @@ void rs600_pm_misc(struct radeon_device *rdev) +@@ -175,7 +194,7 @@ /* set pcie lanes */ if ((rdev->flags & RADEON_IS_PCIE) && !(rdev->flags & RADEON_IS_IGP) && @@ -91912,7 +91828,7 @@ (ps->pcie_lanes != rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) { radeon_set_pcie_lanes(rdev, -@@ -322,16 +341,6 @@ void rs600_hpd_fini(struct radeon_device *rdev) +@@ -322,16 +341,6 @@ } } @@ -91929,7 +91845,7 @@ int rs600_asic_reset(struct radeon_device *rdev) { struct rv515_mc_save save; -@@ -355,7 +364,8 @@ int rs600_asic_reset(struct radeon_device *rdev) +@@ -355,7 +364,8 @@ WREG32(RADEON_CP_RB_CNTL, tmp); pci_save_state(rdev->pdev); /* disable bus mastering */ @@ -91939,7 +91855,7 @@ /* reset GA+VAP */ WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_VAP(1) | S_0000F0_SOFT_RESET_GA(1)); -@@ -549,7 +559,7 @@ int rs600_irq_set(struct radeon_device *rdev) +@@ -549,7 +559,7 @@ WREG32(R_000040_GEN_INT_CNTL, 0); return -EINVAL; } @@ -91948,7 +91864,7 @@ tmp |= S_000040_SW_INT_EN(1); } if (rdev->irq.gui_idle) { -@@ -642,7 +652,7 @@ int rs600_irq_process(struct radeon_device *rdev) +@@ -642,7 +652,7 @@ while (status || rdev->irq.stat_regs.r500.disp_int) { /* SW interrupt */ if (G_000044_SW_INT(status)) { @@ -91957,7 +91873,7 @@ } /* GUI idle */ if (G_000040_GUI_IDLE(status)) { -@@ -847,6 +857,12 @@ static int rs600_startup(struct radeon_device *rdev) +@@ -847,6 +857,12 @@ if (r) return r; @@ -91970,7 +91886,7 @@ /* Enable IRQ */ rs600_irq_set(rdev); rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); -@@ -856,15 +872,21 @@ static int rs600_startup(struct radeon_device *rdev) +@@ -856,15 +872,21 @@ dev_err(rdev->dev, "failed initializing CP (%d).\n", r); return r; } @@ -91996,7 +91912,7 @@ return r; } -@@ -873,6 +895,8 @@ static int rs600_startup(struct radeon_device *rdev) +@@ -873,6 +895,8 @@ int rs600_resume(struct radeon_device *rdev) { @@ -92005,7 +91921,7 @@ /* Make sur GART are not working */ rs600_gart_disable(rdev); /* Resume clock before doing reset */ -@@ -889,11 +913,18 @@ int rs600_resume(struct radeon_device *rdev) +@@ -889,11 +913,18 @@ rv515_clock_startup(rdev); /* Initialize surface registers */ radeon_surface_init(rdev); @@ -92025,7 +91941,7 @@ r600_audio_fini(rdev); r100_cp_disable(rdev); radeon_wb_disable(rdev); -@@ -974,7 +1005,14 @@ int rs600_init(struct radeon_device *rdev) +@@ -974,7 +1005,14 @@ if (r) return r; rs600_set_safe_registers(rdev); @@ -92040,10 +91956,10 @@ r = rs600_startup(rdev); if (r) { /* Somethings want wront with the accel init stop accel */ -diff --git a/drivers/gpu/drm/radeon/rs690.c b/drivers/gpu/drm/radeon/rs690.c -index a9049ed..f2c3b9d 100644 ---- a/drivers/gpu/drm/radeon/rs690.c -+++ b/drivers/gpu/drm/radeon/rs690.c +Index: linux-3.2.46/drivers/gpu/drm/radeon/rs690.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/radeon/rs690.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/radeon/rs690.c 2013-07-26 19:26:24.000000000 +0000 @@ -31,7 +31,7 @@ #include "atom.h" #include "rs690d.h" @@ -92053,7 +91969,7 @@ { unsigned i; uint32_t tmp; -@@ -621,6 +621,12 @@ static int rs690_startup(struct radeon_device *rdev) +@@ -621,6 +621,12 @@ if (r) return r; @@ -92066,7 +91982,7 @@ /* Enable IRQ */ rs600_irq_set(rdev); rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); -@@ -630,15 +636,21 @@ static int rs690_startup(struct radeon_device *rdev) +@@ -630,15 +636,21 @@ dev_err(rdev->dev, "failed initializing CP (%d).\n", r); return r; } @@ -92092,7 +92008,7 @@ return r; } -@@ -647,6 +659,8 @@ static int rs690_startup(struct radeon_device *rdev) +@@ -647,6 +659,8 @@ int rs690_resume(struct radeon_device *rdev) { @@ -92101,7 +92017,7 @@ /* Make sur GART are not working */ rs400_gart_disable(rdev); /* Resume clock before doing reset */ -@@ -663,11 +677,18 @@ int rs690_resume(struct radeon_device *rdev) +@@ -663,11 +677,18 @@ rv515_clock_startup(rdev); /* Initialize surface registers */ radeon_surface_init(rdev); @@ -92121,7 +92037,7 @@ r600_audio_fini(rdev); r100_cp_disable(rdev); radeon_wb_disable(rdev); -@@ -749,7 +770,14 @@ int rs690_init(struct radeon_device *rdev) +@@ -749,7 +770,14 @@ if (r) return r; rs600_set_safe_registers(rdev); @@ -92136,11 +92052,11 @@ r = rs690_startup(rdev); if (r) { /* Somethings want wront with the accel init stop accel */ -diff --git a/drivers/gpu/drm/radeon/rv515.c b/drivers/gpu/drm/radeon/rv515.c -index d5f45b4..43af363 100644 ---- a/drivers/gpu/drm/radeon/rv515.c -+++ b/drivers/gpu/drm/radeon/rv515.c -@@ -53,46 +53,46 @@ void rv515_debugfs(struct radeon_device *rdev) +Index: linux-3.2.46/drivers/gpu/drm/radeon/rv515.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/radeon/rv515.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/radeon/rv515.c 2013-07-26 19:26:24.000000000 +0000 +@@ -53,46 +53,46 @@ } } @@ -92217,7 +92133,7 @@ ((6 << MS_X0_SHIFT) | (6 << MS_Y0_SHIFT) | (6 << MS_X1_SHIFT) | -@@ -101,8 +101,8 @@ void rv515_ring_start(struct radeon_device *rdev) +@@ -101,8 +101,8 @@ (6 << MS_Y2_SHIFT) | (6 << MSBD0_Y_SHIFT) | (6 << MSBD0_X_SHIFT))); @@ -92228,7 +92144,7 @@ ((6 << MS_X3_SHIFT) | (6 << MS_Y3_SHIFT) | (6 << MS_X4_SHIFT) | -@@ -110,15 +110,15 @@ void rv515_ring_start(struct radeon_device *rdev) +@@ -110,15 +110,15 @@ (6 << MS_X5_SHIFT) | (6 << MS_Y5_SHIFT) | (6 << MSBD1_SHIFT))); @@ -92253,7 +92169,7 @@ } int rv515_mc_wait_for_idle(struct radeon_device *rdev) -@@ -149,7 +149,7 @@ void rv515_gpu_init(struct radeon_device *rdev) +@@ -149,7 +149,7 @@ if (r100_gui_wait_for_idle(rdev)) { printk(KERN_WARNING "Failed to wait GUI idle while " @@ -92262,7 +92178,7 @@ } rv515_vga_render_disable(rdev); r420_pipes_init(rdev); -@@ -161,7 +161,7 @@ void rv515_gpu_init(struct radeon_device *rdev) +@@ -161,7 +161,7 @@ WREG32_PLL(0x000D, tmp); if (r100_gui_wait_for_idle(rdev)) { printk(KERN_WARNING "Failed to wait GUI idle while " @@ -92271,7 +92187,7 @@ } if (rv515_mc_wait_for_idle(rdev)) { printk(KERN_WARNING "Failed to wait MC idle while " -@@ -379,6 +379,12 @@ static int rv515_startup(struct radeon_device *rdev) +@@ -379,6 +379,12 @@ if (r) return r; @@ -92284,7 +92200,7 @@ /* Enable IRQ */ rs600_irq_set(rdev); rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); -@@ -388,9 +394,15 @@ static int rv515_startup(struct radeon_device *rdev) +@@ -388,9 +394,15 @@ dev_err(rdev->dev, "failed initializing CP (%d).\n", r); return r; } @@ -92302,7 +92218,7 @@ return r; } return 0; -@@ -398,6 +410,8 @@ static int rv515_startup(struct radeon_device *rdev) +@@ -398,6 +410,8 @@ int rv515_resume(struct radeon_device *rdev) { @@ -92311,7 +92227,7 @@ /* Make sur GART are not working */ if (rdev->flags & RADEON_IS_PCIE) rv370_pcie_gart_disable(rdev); -@@ -415,7 +429,13 @@ int rv515_resume(struct radeon_device *rdev) +@@ -415,7 +429,13 @@ rv515_clock_startup(rdev); /* Initialize surface registers */ radeon_surface_init(rdev); @@ -92326,7 +92242,7 @@ } int rv515_suspend(struct radeon_device *rdev) -@@ -511,7 +531,14 @@ int rv515_init(struct radeon_device *rdev) +@@ -511,7 +531,14 @@ if (r) return r; rv515_set_safe_registers(rdev); @@ -92341,11 +92257,11 @@ r = rv515_startup(rdev); if (r) { /* Somethings want wront with the accel init stop accel */ -diff --git a/drivers/gpu/drm/radeon/rv770.c b/drivers/gpu/drm/radeon/rv770.c -index cc79449..591040b 100644 ---- a/drivers/gpu/drm/radeon/rv770.c -+++ b/drivers/gpu/drm/radeon/rv770.c -@@ -359,7 +359,7 @@ static int rv770_cp_load_microcode(struct radeon_device *rdev) +Index: linux-3.2.46/drivers/gpu/drm/radeon/rv770.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/radeon/rv770.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/radeon/rv770.c 2013-07-26 19:26:24.000000000 +0000 +@@ -359,7 +359,7 @@ void r700_cp_fini(struct radeon_device *rdev) { r700_cp_stop(rdev); @@ -92354,7 +92270,7 @@ } /* -@@ -978,7 +978,7 @@ void r700_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc) +@@ -978,7 +978,7 @@ } if (rdev->flags & RADEON_IS_AGP) { size_bf = mc->gtt_start; @@ -92363,7 +92279,7 @@ if (size_bf > size_af) { if (mc->mc_vram_size > size_bf) { dev_warn(rdev->dev, "limiting VRAM\n"); -@@ -992,7 +992,7 @@ void r700_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc) +@@ -992,7 +992,7 @@ mc->real_vram_size = size_af; mc->mc_vram_size = size_af; } @@ -92372,7 +92288,7 @@ } mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n", -@@ -1052,6 +1052,7 @@ int rv770_mc_init(struct radeon_device *rdev) +@@ -1052,6 +1052,7 @@ static int rv770_startup(struct radeon_device *rdev) { @@ -92380,7 +92296,7 @@ int r; /* enable pcie gen2 link */ -@@ -1082,7 +1083,7 @@ static int rv770_startup(struct radeon_device *rdev) +@@ -1082,7 +1083,7 @@ r = r600_blit_init(rdev); if (r) { r600_blit_fini(rdev); @@ -92389,7 +92305,7 @@ dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r); } -@@ -1091,6 +1092,12 @@ static int rv770_startup(struct radeon_device *rdev) +@@ -1091,6 +1092,12 @@ if (r) return r; @@ -92402,7 +92318,7 @@ /* Enable IRQ */ r = r600_irq_init(rdev); if (r) { -@@ -1100,7 +1107,9 @@ static int rv770_startup(struct radeon_device *rdev) +@@ -1100,7 +1107,9 @@ } r600_irq_set(rdev); @@ -92413,7 +92329,7 @@ if (r) return r; r = rv770_cp_load_microcode(rdev); -@@ -1110,6 +1119,17 @@ static int rv770_startup(struct radeon_device *rdev) +@@ -1110,6 +1119,17 @@ if (r) return r; @@ -92431,7 +92347,7 @@ return 0; } -@@ -1124,15 +1144,11 @@ int rv770_resume(struct radeon_device *rdev) +@@ -1124,15 +1144,11 @@ /* post card */ atom_asic_init(rdev->mode_info.atom_context); @@ -92449,7 +92365,7 @@ return r; } -@@ -1149,13 +1165,14 @@ int rv770_resume(struct radeon_device *rdev) +@@ -1149,13 +1165,14 @@ int rv770_suspend(struct radeon_device *rdev) { r600_audio_fini(rdev); @@ -92466,7 +92382,7 @@ return 0; } -@@ -1224,8 +1241,8 @@ int rv770_init(struct radeon_device *rdev) +@@ -1224,8 +1241,8 @@ if (r) return r; @@ -92477,7 +92393,7 @@ rdev->ih.ring_obj = NULL; r600_ih_ring_init(rdev, 64 * 1024); -@@ -1234,30 +1251,24 @@ int rv770_init(struct radeon_device *rdev) +@@ -1234,30 +1251,24 @@ if (r) return r; @@ -92515,7 +92431,7 @@ r = r600_audio_init(rdev); if (r) { -@@ -1274,11 +1285,12 @@ void rv770_fini(struct radeon_device *rdev) +@@ -1274,11 +1285,12 @@ r700_cp_fini(rdev); r600_irq_fini(rdev); radeon_wb_fini(rdev); @@ -92529,11 +92445,10 @@ radeon_fence_driver_fini(rdev); radeon_agp_fini(rdev); radeon_bo_fini(rdev); -diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c -new file mode 100644 -index 0000000..2dbd585 ---- /dev/null -+++ b/drivers/gpu/drm/radeon/si.c +Index: linux-3.2.46/drivers/gpu/drm/radeon/si.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/radeon/si.c 2013-07-26 19:26:24.000000000 +0000 @@ -0,0 +1,4129 @@ +/* + * Copyright 2011 Advanced Micro Devices, Inc. @@ -96664,11 +96579,10 @@ + rdev->bios = NULL; +} + -diff --git a/drivers/gpu/drm/radeon/si_blit_shaders.c b/drivers/gpu/drm/radeon/si_blit_shaders.c -new file mode 100644 -index 0000000..ec415e7 ---- /dev/null -+++ b/drivers/gpu/drm/radeon/si_blit_shaders.c +Index: linux-3.2.46/drivers/gpu/drm/radeon/si_blit_shaders.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/radeon/si_blit_shaders.c 2013-07-26 19:26:24.000000000 +0000 @@ -0,0 +1,253 @@ +/* + * Copyright 2011 Advanced Micro Devices, Inc. @@ -96923,11 +96837,10 @@ +}; + +const u32 si_default_size = ARRAY_SIZE(si_default_state); -diff --git a/drivers/gpu/drm/radeon/si_blit_shaders.h b/drivers/gpu/drm/radeon/si_blit_shaders.h -new file mode 100644 -index 0000000..c739e51 ---- /dev/null -+++ b/drivers/gpu/drm/radeon/si_blit_shaders.h +Index: linux-3.2.46/drivers/gpu/drm/radeon/si_blit_shaders.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/radeon/si_blit_shaders.h 2013-07-26 19:26:24.000000000 +0000 @@ -0,0 +1,32 @@ +/* + * Copyright 2011 Advanced Micro Devices, Inc. @@ -96961,11 +96874,10 @@ +extern const u32 si_default_size; + +#endif -diff --git a/drivers/gpu/drm/radeon/si_reg.h b/drivers/gpu/drm/radeon/si_reg.h -new file mode 100644 -index 0000000..eda938a ---- /dev/null -+++ b/drivers/gpu/drm/radeon/si_reg.h +Index: linux-3.2.46/drivers/gpu/drm/radeon/si_reg.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/radeon/si_reg.h 2013-07-26 19:26:24.000000000 +0000 @@ -0,0 +1,33 @@ +/* + * Copyright 2010 Advanced Micro Devices, Inc. @@ -97000,11 +96912,10 @@ +#define SI_DC_GPIO_HPD_Y 0x65bc + +#endif -diff --git a/drivers/gpu/drm/radeon/sid.h b/drivers/gpu/drm/radeon/sid.h -new file mode 100644 -index 0000000..45e240d ---- /dev/null -+++ b/drivers/gpu/drm/radeon/sid.h +Index: linux-3.2.46/drivers/gpu/drm/radeon/sid.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/radeon/sid.h 2013-07-26 19:26:24.000000000 +0000 @@ -0,0 +1,889 @@ +/* + * Copyright 2011 Advanced Micro Devices, Inc. @@ -97895,11 +97806,11 @@ +#define PACKET3_WAIT_ON_AVAIL_BUFFER 0x8A + +#endif -diff --git a/drivers/gpu/drm/savage/savage_bci.c b/drivers/gpu/drm/savage/savage_bci.c -index cb1ee4e..2a25888 100644 ---- a/drivers/gpu/drm/savage/savage_bci.c -+++ b/drivers/gpu/drm/savage/savage_bci.c -@@ -547,6 +547,8 @@ int savage_driver_load(struct drm_device *dev, unsigned long chipset) +Index: linux-3.2.46/drivers/gpu/drm/savage/savage_bci.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/savage/savage_bci.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/savage/savage_bci.c 2013-07-26 19:26:24.000000000 +0000 +@@ -547,6 +547,8 @@ dev_priv->chipset = (enum savage_family)chipset; @@ -97908,11 +97819,11 @@ return 0; } -diff --git a/drivers/gpu/drm/savage/savage_drv.c b/drivers/gpu/drm/savage/savage_drv.c -index 5468d1c..89afe0b 100644 ---- a/drivers/gpu/drm/savage/savage_drv.c -+++ b/drivers/gpu/drm/savage/savage_drv.c -@@ -35,6 +35,17 @@ static struct pci_device_id pciidlist[] = { +Index: linux-3.2.46/drivers/gpu/drm/savage/savage_drv.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/savage/savage_drv.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/savage/savage_drv.c 2013-07-26 19:26:24.000000000 +0000 +@@ -35,6 +35,17 @@ savage_PCI_IDS }; @@ -97930,7 +97841,7 @@ static struct drm_driver driver = { .driver_features = DRIVER_USE_AGP | DRIVER_USE_MTRR | DRIVER_HAVE_DMA | DRIVER_PCI_DMA, -@@ -46,17 +57,7 @@ static struct drm_driver driver = { +@@ -46,17 +57,7 @@ .reclaim_buffers = savage_reclaim_buffers, .ioctls = savage_ioctls, .dma_ioctl = savage_bci_buffers, @@ -97949,11 +97860,11 @@ .name = DRIVER_NAME, .desc = DRIVER_DESC, .date = DRIVER_DATE, -diff --git a/drivers/gpu/drm/savage/savage_state.c b/drivers/gpu/drm/savage/savage_state.c -index 8a3e315..b6d8608 100644 ---- a/drivers/gpu/drm/savage/savage_state.c -+++ b/drivers/gpu/drm/savage/savage_state.c -@@ -988,7 +988,7 @@ int savage_bci_cmdbuf(struct drm_device *dev, void *data, struct drm_file *file_ +Index: linux-3.2.46/drivers/gpu/drm/savage/savage_state.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/savage/savage_state.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/savage/savage_state.c 2013-07-26 19:26:24.000000000 +0000 +@@ -988,7 +988,7 @@ * for locking on FreeBSD. */ if (cmdbuf->size) { @@ -97962,7 +97873,7 @@ if (kcmd_addr == NULL) return -ENOMEM; -@@ -1015,8 +1015,8 @@ int savage_bci_cmdbuf(struct drm_device *dev, void *data, struct drm_file *file_ +@@ -1015,8 +1015,8 @@ cmdbuf->vb_addr = kvb_addr; } if (cmdbuf->nbox) { @@ -97973,7 +97884,7 @@ if (kbox_addr == NULL) { ret = -ENOMEM; goto done; -@@ -1057,7 +1057,8 @@ int savage_bci_cmdbuf(struct drm_device *dev, void *data, struct drm_file *file_ +@@ -1057,7 +1057,8 @@ DRM_ERROR("indexed drawing command extends " "beyond end of command buffer\n"); DMA_FLUSH(); @@ -97983,7 +97894,7 @@ } /* fall through */ case SAVAGE_CMD_DMA_PRIM: -@@ -1076,7 +1077,7 @@ int savage_bci_cmdbuf(struct drm_device *dev, void *data, struct drm_file *file_ +@@ -1076,7 +1077,7 @@ cmdbuf->vb_stride, cmdbuf->nbox, cmdbuf->box_addr); if (ret != 0) @@ -97992,11 +97903,11 @@ first_draw_cmd = NULL; } } -diff --git a/drivers/gpu/drm/sis/sis_drv.c b/drivers/gpu/drm/sis/sis_drv.c -index a9c5716..dd14cd1 100644 ---- a/drivers/gpu/drm/sis/sis_drv.c -+++ b/drivers/gpu/drm/sis/sis_drv.c -@@ -40,51 +40,78 @@ static struct pci_device_id pciidlist[] = { +Index: linux-3.2.46/drivers/gpu/drm/sis/sis_drv.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/sis/sis_drv.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/sis/sis_drv.c 2013-07-26 19:26:24.000000000 +0000 +@@ -40,51 +40,78 @@ static int sis_driver_load(struct drm_device *dev, unsigned long chipset) { drm_sis_private_t *dev_priv; @@ -98092,11 +98003,11 @@ .name = DRIVER_NAME, .desc = DRIVER_DESC, .date = DRIVER_DATE, -diff --git a/drivers/gpu/drm/sis/sis_drv.h b/drivers/gpu/drm/sis/sis_drv.h -index 194303c..573758b 100644 ---- a/drivers/gpu/drm/sis/sis_drv.h -+++ b/drivers/gpu/drm/sis/sis_drv.h -@@ -44,7 +44,7 @@ enum sis_family { +Index: linux-3.2.46/drivers/gpu/drm/sis/sis_drv.h +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/sis/sis_drv.h 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/sis/sis_drv.h 2013-07-26 19:26:24.000000000 +0000 +@@ -44,7 +44,7 @@ SIS_CHIP_315 = 1, }; @@ -98105,7 +98016,7 @@ #define SIS_BASE (dev_priv->mmio) -@@ -54,12 +54,15 @@ enum sis_family { +@@ -54,12 +54,15 @@ typedef struct drm_sis_private { drm_local_map_t *mmio; unsigned int idle_fault; @@ -98122,10 +98033,10 @@ } drm_sis_private_t; extern int sis_idle(struct drm_device *dev); -diff --git a/drivers/gpu/drm/sis/sis_mm.c b/drivers/gpu/drm/sis/sis_mm.c -index 7fe2b63..dd4a316 100644 ---- a/drivers/gpu/drm/sis/sis_mm.c -+++ b/drivers/gpu/drm/sis/sis_mm.c +Index: linux-3.2.46/drivers/gpu/drm/sis/sis_mm.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/sis/sis_mm.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/sis/sis_mm.c 2013-07-26 19:26:24.000000000 +0000 @@ -41,40 +41,18 @@ #define AGP_TYPE 1 @@ -98173,7 +98084,7 @@ #else /* CONFIG_FB_SIS[_MODULE] */ #define SIS_MM_ALIGN_SHIFT 4 -@@ -86,30 +64,11 @@ static int sis_fb_init(struct drm_device *dev, void *data, struct drm_file *file +@@ -86,30 +64,11 @@ { drm_sis_private_t *dev_priv = dev->dev_private; drm_sis_fb_t *fb = data; @@ -98207,7 +98118,7 @@ dev_priv->vram_initialized = 1; dev_priv->vram_offset = fb->offset; -@@ -120,13 +79,15 @@ static int sis_fb_init(struct drm_device *dev, void *data, struct drm_file *file +@@ -120,13 +79,15 @@ return 0; } @@ -98226,7 +98137,7 @@ mutex_lock(&dev->struct_mutex); -@@ -138,25 +99,68 @@ static int sis_drm_alloc(struct drm_device *dev, struct drm_file *file_priv, +@@ -138,25 +99,68 @@ return -EINVAL; } @@ -98309,7 +98220,7 @@ DRM_DEBUG("alloc %d, size = %d, offset = %d\n", pool, mem->size, mem->offset); -@@ -167,14 +171,28 @@ static int sis_drm_free(struct drm_device *dev, void *data, struct drm_file *fil +@@ -167,14 +171,28 @@ { drm_sis_private_t *dev_priv = dev->dev_private; drm_sis_mem_t *mem = data; @@ -98341,7 +98252,7 @@ } static int sis_fb_alloc(struct drm_device *dev, void *data, -@@ -188,18 +206,10 @@ static int sis_ioctl_agp_init(struct drm_device *dev, void *data, +@@ -188,18 +206,10 @@ { drm_sis_private_t *dev_priv = dev->dev_private; drm_sis_agp_t *agp = data; @@ -98361,7 +98272,7 @@ dev_priv->agp_initialized = 1; dev_priv->agp_offset = agp->offset; -@@ -293,20 +303,26 @@ void sis_lastclose(struct drm_device *dev) +@@ -293,20 +303,26 @@ return; mutex_lock(&dev->struct_mutex); @@ -98394,7 +98305,7 @@ mutex_unlock(&dev->struct_mutex); return; } -@@ -314,7 +330,18 @@ void sis_reclaim_buffers_locked(struct drm_device *dev, +@@ -314,7 +330,18 @@ if (dev->driver->dma_quiescent) dev->driver->dma_quiescent(dev); @@ -98414,11 +98325,11 @@ mutex_unlock(&dev->struct_mutex); return; } -diff --git a/drivers/gpu/drm/tdfx/tdfx_drv.c b/drivers/gpu/drm/tdfx/tdfx_drv.c -index cda2991..1613c78 100644 ---- a/drivers/gpu/drm/tdfx/tdfx_drv.c -+++ b/drivers/gpu/drm/tdfx/tdfx_drv.c -@@ -41,20 +41,21 @@ static struct pci_device_id pciidlist[] = { +Index: linux-3.2.46/drivers/gpu/drm/tdfx/tdfx_drv.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/tdfx/tdfx_drv.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/tdfx/tdfx_drv.c 2013-07-26 19:26:24.000000000 +0000 +@@ -41,20 +41,21 @@ tdfx_PCI_IDS }; @@ -98451,11 +98362,11 @@ .name = DRIVER_NAME, .desc = DRIVER_DESC, .date = DRIVER_DATE, -diff --git a/drivers/gpu/drm/ttm/Makefile b/drivers/gpu/drm/ttm/Makefile -index f3cf6f0..b2b33dd 100644 ---- a/drivers/gpu/drm/ttm/Makefile -+++ b/drivers/gpu/drm/ttm/Makefile -@@ -7,4 +7,8 @@ ttm-y := ttm_agp_backend.o ttm_memory.o ttm_tt.o ttm_bo.o \ +Index: linux-3.2.46/drivers/gpu/drm/ttm/Makefile +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/ttm/Makefile 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/ttm/Makefile 2013-07-26 19:26:24.000000000 +0000 +@@ -7,4 +7,8 @@ ttm_object.o ttm_lock.o ttm_execbuf_util.o ttm_page_alloc.o \ ttm_bo_manager.o @@ -98464,10 +98375,10 @@ +endif + obj-$(CONFIG_DRM_TTM) += ttm.o -diff --git a/drivers/gpu/drm/ttm/ttm_agp_backend.c b/drivers/gpu/drm/ttm/ttm_agp_backend.c -index 1c4a72f..4a87282 100644 ---- a/drivers/gpu/drm/ttm/ttm_agp_backend.c -+++ b/drivers/gpu/drm/ttm/ttm_agp_backend.c +Index: linux-3.2.46/drivers/gpu/drm/ttm/ttm_agp_backend.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/ttm/ttm_agp_backend.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/ttm/ttm_agp_backend.c 2013-07-26 19:26:24.000000000 +0000 @@ -29,8 +29,11 @@ * Keith Packard. */ @@ -98494,11 +98405,12 @@ - unsigned long num_pages, struct page **pages, - struct page *dummy_read_page, - dma_addr_t *dma_addrs) -+static int ttm_agp_bind(struct ttm_tt *ttm, struct ttm_mem_reg *bo_mem) - { +-{ - struct ttm_agp_backend *agp_be = - container_of(backend, struct ttm_agp_backend, backend); - struct page **cur_page, **last_page = pages + num_pages; ++static int ttm_agp_bind(struct ttm_tt *ttm, struct ttm_mem_reg *bo_mem) ++{ + struct ttm_agp_backend *agp_be = container_of(ttm, struct ttm_agp_backend, ttm); + struct drm_mm_node *node = bo_mem->mm_node; struct agp_memory *mem; @@ -98551,14 +98463,14 @@ { - struct ttm_agp_backend *agp_be = - container_of(backend, struct ttm_agp_backend, backend); -- ++ struct ttm_agp_backend *agp_be = container_of(ttm, struct ttm_agp_backend, ttm); + - if (agp_be->mem->is_bound) - return agp_unbind_memory(agp_be->mem); - else - return 0; -} -+ struct ttm_agp_backend *agp_be = container_of(ttm, struct ttm_agp_backend, ttm); - +- -static void ttm_agp_clear(struct ttm_backend *backend) -{ - struct ttm_agp_backend *agp_be = @@ -98609,7 +98521,7 @@ { struct ttm_agp_backend *agp_be; -@@ -143,10 +123,29 @@ struct ttm_backend *ttm_agp_backend_init(struct ttm_bo_device *bdev, +@@ -143,10 +123,29 @@ agp_be->mem = NULL; agp_be->bridge = bridge; @@ -98643,10 +98555,10 @@ +EXPORT_SYMBOL(ttm_agp_tt_unpopulate); #endif -diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c -index 0d27bff..8b73ae8 100644 ---- a/drivers/gpu/drm/ttm/ttm_bo.c -+++ b/drivers/gpu/drm/ttm/ttm_bo.c +Index: linux-3.2.46/drivers/gpu/drm/ttm/ttm_bo.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/ttm/ttm_bo.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/ttm/ttm_bo.c 2013-07-26 19:26:24.000000000 +0000 @@ -28,6 +28,8 @@ * Authors: Thomas Hellstrom */ @@ -98656,7 +98568,7 @@ #include "ttm/ttm_module.h" #include "ttm/ttm_bo_driver.h" #include "ttm/ttm_placement.h" -@@ -68,15 +70,13 @@ static void ttm_mem_type_debug(struct ttm_bo_device *bdev, int mem_type) +@@ -68,15 +70,13 @@ { struct ttm_mem_type_manager *man = &bdev->man[mem_type]; @@ -98679,7 +98591,7 @@ if (mem_type != TTM_PL_SYSTEM) (*man->func->debug)(man, TTM_PFX); } -@@ -86,16 +86,16 @@ static void ttm_bo_mem_space_debug(struct ttm_buffer_object *bo, +@@ -86,16 +86,16 @@ { int i, ret, mem_type; @@ -98701,7 +98613,7 @@ ttm_mem_type_debug(bo->bdev, mem_type); } } -@@ -137,6 +137,7 @@ static void ttm_bo_release_list(struct kref *list_kref) +@@ -137,6 +137,7 @@ struct ttm_buffer_object *bo = container_of(list_kref, struct ttm_buffer_object, list_kref); struct ttm_bo_device *bdev = bo->bdev; @@ -98709,7 +98621,7 @@ BUG_ON(atomic_read(&bo->list_kref.refcount)); BUG_ON(atomic_read(&bo->kref.refcount)); -@@ -152,9 +153,9 @@ static void ttm_bo_release_list(struct kref *list_kref) +@@ -152,9 +153,9 @@ if (bo->destroy) bo->destroy(bo); else { @@ -98720,7 +98632,7 @@ } int ttm_bo_wait_unreserved(struct ttm_buffer_object *bo, bool interruptible) -@@ -337,29 +338,13 @@ static int ttm_bo_add_ttm(struct ttm_buffer_object *bo, bool zero_alloc) +@@ -337,29 +338,13 @@ if (zero_alloc) page_flags |= TTM_PAGE_FLAG_ZERO_ALLOC; case ttm_bo_type_kernel: @@ -98753,7 +98665,7 @@ ret = -EINVAL; break; } -@@ -431,14 +416,23 @@ static int ttm_bo_handle_move_mem(struct ttm_buffer_object *bo, +@@ -431,14 +416,23 @@ else ret = ttm_bo_move_memcpy(bo, evict, no_wait_reserve, no_wait_gpu, mem); @@ -98779,7 +98691,7 @@ bo->evicted = false; } -@@ -472,6 +466,9 @@ out_err: +@@ -472,6 +466,9 @@ static void ttm_bo_cleanup_memtype_use(struct ttm_buffer_object *bo) { @@ -98789,7 +98701,7 @@ if (bo->ttm) { ttm_tt_unbind(bo->ttm); ttm_tt_destroy(bo->ttm); -@@ -737,9 +734,7 @@ static int ttm_bo_evict(struct ttm_buffer_object *bo, bool interruptible, +@@ -737,9 +734,7 @@ if (unlikely(ret != 0)) { if (ret != -ERESTARTSYS) { @@ -98800,7 +98712,7 @@ } goto out; } -@@ -760,9 +755,8 @@ static int ttm_bo_evict(struct ttm_buffer_object *bo, bool interruptible, +@@ -760,9 +755,8 @@ no_wait_reserve, no_wait_gpu); if (ret) { if (ret != -ERESTARTSYS) { @@ -98812,7 +98724,7 @@ ttm_bo_mem_space_debug(bo, &placement); } goto out; -@@ -772,7 +766,7 @@ static int ttm_bo_evict(struct ttm_buffer_object *bo, bool interruptible, +@@ -772,7 +766,7 @@ no_wait_reserve, no_wait_gpu); if (ret) { if (ret != -ERESTARTSYS) @@ -98821,7 +98733,7 @@ ttm_bo_mem_put(bo, &evict_mem); goto out; } -@@ -913,16 +907,12 @@ static uint32_t ttm_bo_select_caching(struct ttm_mem_type_manager *man, +@@ -913,16 +907,12 @@ } static bool ttm_bo_mt_compatible(struct ttm_mem_type_manager *man, @@ -98838,7 +98750,7 @@ if ((cur_flags & proposed_placement & TTM_PL_MASK_MEM) == 0) return false; -@@ -967,7 +957,6 @@ int ttm_bo_mem_space(struct ttm_buffer_object *bo, +@@ -967,7 +957,6 @@ man = &bdev->man[mem_type]; type_ok = ttm_bo_mt_compatible(man, @@ -98846,7 +98758,7 @@ mem_type, placement->placement[i], &cur_flags); -@@ -1015,7 +1004,6 @@ int ttm_bo_mem_space(struct ttm_buffer_object *bo, +@@ -1015,7 +1004,6 @@ if (!man->has_type) continue; if (!ttm_bo_mt_compatible(man, @@ -98854,7 +98766,7 @@ mem_type, placement->busy_placement[i], &cur_flags)) -@@ -1185,15 +1173,27 @@ int ttm_bo_init(struct ttm_bo_device *bdev, +@@ -1185,15 +1173,27 @@ { int ret = 0; unsigned long num_pages; @@ -98883,27 +98795,29 @@ return -EINVAL; } bo->destroy = destroy; -@@ -1255,14 +1255,34 @@ out_err: +@@ -1255,14 +1255,34 @@ } EXPORT_SYMBOL(ttm_bo_init); -static inline size_t ttm_bo_size(struct ttm_bo_global *glob, - unsigned long num_pages) +-{ +- size_t page_array_size = (num_pages * sizeof(void *) + PAGE_SIZE - 1) & +- PAGE_MASK; +- +- return glob->ttm_bo_size + 2 * page_array_size; +size_t ttm_bo_acc_size(struct ttm_bo_device *bdev, + unsigned long bo_size, + unsigned struct_size) - { -- size_t page_array_size = (num_pages * sizeof(void *) + PAGE_SIZE - 1) & -- PAGE_MASK; ++{ + unsigned npages = (PAGE_ALIGN(bo_size)) >> PAGE_SHIFT; + size_t size = 0; - -- return glob->ttm_bo_size + 2 * page_array_size; ++ + size += ttm_round_pot(struct_size); + size += PAGE_ALIGN(npages * sizeof(void *)); + size += ttm_round_pot(sizeof(struct ttm_tt)); + return size; - } ++} +EXPORT_SYMBOL(ttm_bo_acc_size); + +size_t ttm_bo_dma_acc_size(struct ttm_bo_device *bdev, @@ -98918,12 +98832,12 @@ + size += PAGE_ALIGN(npages * sizeof(dma_addr_t)); + size += ttm_round_pot(sizeof(struct ttm_dma_tt)); + return size; -+} + } +EXPORT_SYMBOL(ttm_bo_dma_acc_size); int ttm_bo_create(struct ttm_bo_device *bdev, unsigned long size, -@@ -1275,22 +1295,14 @@ int ttm_bo_create(struct ttm_bo_device *bdev, +@@ -1275,22 +1295,14 @@ struct ttm_buffer_object **p_bo) { struct ttm_buffer_object *bo; @@ -98949,7 +98863,7 @@ ret = ttm_bo_init(bdev, bo, size, type, placement, page_alignment, buffer_start, interruptible, persistent_swap_storage, acc_size, NULL); -@@ -1320,8 +1332,7 @@ static int ttm_bo_force_list_clean(struct ttm_bo_device *bdev, +@@ -1320,8 +1332,7 @@ if (allow_errors) { return ret; } else { @@ -98959,7 +98873,7 @@ } } spin_lock(&glob->lru_lock); -@@ -1336,14 +1347,14 @@ int ttm_bo_clean_mm(struct ttm_bo_device *bdev, unsigned mem_type) +@@ -1336,14 +1347,14 @@ int ret = -EINVAL; if (mem_type >= TTM_NUM_MEM_TYPES) { @@ -98977,7 +98891,7 @@ return ret; } -@@ -1366,16 +1377,12 @@ int ttm_bo_evict_mm(struct ttm_bo_device *bdev, unsigned mem_type) +@@ -1366,16 +1377,12 @@ struct ttm_mem_type_manager *man = &bdev->man[mem_type]; if (mem_type == 0 || mem_type >= TTM_NUM_MEM_TYPES) { @@ -98996,7 +98910,7 @@ return 0; } -@@ -1460,18 +1467,10 @@ int ttm_bo_global_init(struct drm_global_reference *ref) +@@ -1460,18 +1467,10 @@ ttm_mem_init_shrink(&glob->shrink, ttm_bo_swapout); ret = ttm_mem_register_shrink(glob->mem_glob, &glob->shrink); if (unlikely(ret != 0)) { @@ -99016,7 +98930,7 @@ atomic_set(&glob->bo_count, 0); ret = kobject_init_and_add( -@@ -1501,9 +1500,8 @@ int ttm_bo_device_release(struct ttm_bo_device *bdev) +@@ -1501,9 +1500,8 @@ man->use_type = false; if ((i != TTM_PL_SYSTEM) && ttm_bo_clean_mm(bdev, i)) { ret = -EBUSY; @@ -99028,11 +98942,11 @@ } man->has_type = false; } -diff --git a/drivers/gpu/drm/ttm/ttm_bo_util.c b/drivers/gpu/drm/ttm/ttm_bo_util.c -index 082fcae..f8187ea 100644 ---- a/drivers/gpu/drm/ttm/ttm_bo_util.c -+++ b/drivers/gpu/drm/ttm/ttm_bo_util.c -@@ -244,7 +244,7 @@ static int ttm_copy_io_ttm_page(struct ttm_tt *ttm, void *src, +Index: linux-3.2.46/drivers/gpu/drm/ttm/ttm_bo_util.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/ttm/ttm_bo_util.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/ttm/ttm_bo_util.c 2013-07-26 19:26:24.000000000 +0000 +@@ -244,7 +244,7 @@ unsigned long page, pgprot_t prot) { @@ -99041,7 +98955,7 @@ void *dst; if (!d) -@@ -281,7 +281,7 @@ static int ttm_copy_ttm_io_page(struct ttm_tt *ttm, void *dst, +@@ -281,7 +281,7 @@ unsigned long page, pgprot_t prot) { @@ -99050,7 +98964,7 @@ void *src; if (!s) -@@ -342,6 +342,12 @@ int ttm_bo_move_memcpy(struct ttm_buffer_object *bo, +@@ -342,6 +342,12 @@ if (old_iomap == NULL && ttm == NULL) goto out2; @@ -99063,7 +98977,7 @@ add = 0; dir = 1; -@@ -439,6 +445,7 @@ static int ttm_buffer_object_transfer(struct ttm_buffer_object *bo, +@@ -439,6 +445,7 @@ kref_init(&fbo->list_kref); kref_init(&fbo->kref); fbo->destroy = &ttm_transfered_destroy; @@ -99071,7 +98985,7 @@ *new_obj = fbo; return 0; -@@ -502,10 +509,16 @@ static int ttm_bo_kmap_ttm(struct ttm_buffer_object *bo, +@@ -502,10 +509,16 @@ { struct ttm_mem_reg *mem = &bo->mem; pgprot_t prot; struct ttm_tt *ttm = bo->ttm; @@ -99090,7 +99004,7 @@ if (num_pages == 1 && (mem->placement & TTM_PL_FLAG_CACHED)) { /* * We're mapping a single page, and the desired -@@ -513,18 +526,9 @@ static int ttm_bo_kmap_ttm(struct ttm_buffer_object *bo, +@@ -513,18 +526,9 @@ */ map->bo_kmap_type = ttm_bo_map_kmap; @@ -99110,10 +99024,10 @@ /* * We need to use vmap to get the desired page protection * or to make the buffer object look contiguous. -diff --git a/drivers/gpu/drm/ttm/ttm_bo_vm.c b/drivers/gpu/drm/ttm/ttm_bo_vm.c -index 221b924..a877813 100644 ---- a/drivers/gpu/drm/ttm/ttm_bo_vm.c -+++ b/drivers/gpu/drm/ttm/ttm_bo_vm.c +Index: linux-3.2.46/drivers/gpu/drm/ttm/ttm_bo_vm.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/ttm/ttm_bo_vm.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/ttm/ttm_bo_vm.c 2013-07-26 19:26:24.000000000 +0000 @@ -28,6 +28,8 @@ * Authors: Thomas Hellstrom */ @@ -99123,7 +99037,7 @@ #include #include #include -@@ -174,18 +176,23 @@ static int ttm_bo_vm_fault(struct vm_area_struct *vma, struct vm_fault *vmf) +@@ -174,18 +176,23 @@ vma->vm_page_prot = (bo->mem.placement & TTM_PL_FLAG_CACHED) ? vm_get_page_prot(vma->vm_flags) : ttm_io_prot(bo->mem.placement, vma->vm_page_prot); @@ -99149,7 +99063,7 @@ if (unlikely(!page && i == 0)) { retval = VM_FAULT_OOM; goto out_io_unlock; -@@ -257,8 +264,7 @@ int ttm_bo_mmap(struct file *filp, struct vm_area_struct *vma, +@@ -257,8 +264,7 @@ read_unlock(&bdev->vm_lock); if (unlikely(bo == NULL)) { @@ -99159,10 +99073,10 @@ return -EINVAL; } -diff --git a/drivers/gpu/drm/ttm/ttm_memory.c b/drivers/gpu/drm/ttm/ttm_memory.c -index e70ddd8..23d2ecb 100644 ---- a/drivers/gpu/drm/ttm/ttm_memory.c -+++ b/drivers/gpu/drm/ttm/ttm_memory.c +Index: linux-3.2.46/drivers/gpu/drm/ttm/ttm_memory.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/ttm/ttm_memory.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/ttm/ttm_memory.c 2013-07-26 19:26:24.000000000 +0000 @@ -25,6 +25,8 @@ * **************************************************************************/ @@ -99172,7 +99086,7 @@ #include "ttm/ttm_memory.h" #include "ttm/ttm_module.h" #include "ttm/ttm_page_alloc.h" -@@ -74,9 +76,8 @@ static void ttm_mem_zone_kobj_release(struct kobject *kobj) +@@ -74,9 +76,8 @@ struct ttm_mem_zone *zone = container_of(kobj, struct ttm_mem_zone, kobj); @@ -99184,7 +99098,7 @@ kfree(zone); } -@@ -390,11 +391,11 @@ int ttm_mem_global_init(struct ttm_mem_global *glob) +@@ -390,11 +391,11 @@ #endif for (i = 0; i < glob->num_zones; ++i) { zone = glob->zones[i]; @@ -99199,7 +99113,7 @@ return 0; out_no_zone: ttm_mem_global_release(glob); -@@ -409,6 +410,7 @@ void ttm_mem_global_release(struct ttm_mem_global *glob) +@@ -409,6 +410,7 @@ /* let the page allocator first stop the shrink work. */ ttm_page_alloc_fini(); @@ -99207,10 +99121,10 @@ flush_workqueue(glob->swap_queue); destroy_workqueue(glob->swap_queue); -diff --git a/drivers/gpu/drm/ttm/ttm_object.c b/drivers/gpu/drm/ttm/ttm_object.c -index 93577f2..68daca4 100644 ---- a/drivers/gpu/drm/ttm/ttm_object.c -+++ b/drivers/gpu/drm/ttm/ttm_object.c +Index: linux-3.2.46/drivers/gpu/drm/ttm/ttm_object.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/ttm/ttm_object.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/ttm/ttm_object.c 2013-07-26 19:26:24.000000000 +0000 @@ -49,6 +49,8 @@ * for fast lookup of ref objects given a base object. */ @@ -99220,7 +99134,7 @@ #include "ttm/ttm_object.h" #include "ttm/ttm_module.h" #include -@@ -232,8 +234,7 @@ struct ttm_base_object *ttm_base_object_lookup(struct ttm_object_file *tfile, +@@ -232,8 +234,7 @@ return NULL; if (tfile != base->tfile && !base->shareable) { @@ -99230,10 +99144,10 @@ ttm_base_object_unref(&base); return NULL; } -diff --git a/drivers/gpu/drm/ttm/ttm_page_alloc.c b/drivers/gpu/drm/ttm/ttm_page_alloc.c -index 9e4313e..578207e 100644 ---- a/drivers/gpu/drm/ttm/ttm_page_alloc.c -+++ b/drivers/gpu/drm/ttm/ttm_page_alloc.c +Index: linux-3.2.46/drivers/gpu/drm/ttm/ttm_page_alloc.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/ttm/ttm_page_alloc.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/ttm/ttm_page_alloc.c 2013-07-26 19:26:24.000000000 +0000 @@ -30,6 +30,9 @@ * - Use page->lru to keep a free list * - doesn't track currently in use pages @@ -99244,7 +99158,7 @@ #include #include #include -@@ -167,18 +170,13 @@ static ssize_t ttm_pool_store(struct kobject *kobj, +@@ -167,18 +170,13 @@ m->options.small = val; else if (attr == &ttm_page_pool_alloc_size) { if (val > NUM_PAGES_TO_ALLOC*8) { @@ -99266,7 +99180,7 @@ } m->options.alloc_size = val; } -@@ -279,8 +277,7 @@ static void ttm_pages_put(struct page *pages[], unsigned npages) +@@ -279,8 +277,7 @@ { unsigned i; if (set_pages_array_wb(pages, npages)) @@ -99276,7 +99190,7 @@ for (i = 0; i < npages; ++i) __free_page(pages[i]); } -@@ -315,8 +312,7 @@ static int ttm_page_pool_free(struct ttm_page_pool *pool, unsigned nr_free) +@@ -315,8 +312,7 @@ pages_to_free = kmalloc(npages_to_free * sizeof(struct page *), GFP_KERNEL); if (!pages_to_free) { @@ -99286,7 +99200,7 @@ return 0; } -@@ -438,16 +434,12 @@ static int ttm_set_pages_caching(struct page **pages, +@@ -438,16 +434,12 @@ case tt_uncached: r = set_pages_array_uc(pages, cpages); if (r) @@ -99305,7 +99219,7 @@ break; default: break; -@@ -492,8 +484,7 @@ static int ttm_alloc_new_pages(struct list_head *pages, gfp_t gfp_flags, +@@ -492,8 +484,7 @@ caching_array = kmalloc(max_cpages*sizeof(struct page *), GFP_KERNEL); if (!caching_array) { @@ -99315,7 +99229,7 @@ return -ENOMEM; } -@@ -501,7 +492,7 @@ static int ttm_alloc_new_pages(struct list_head *pages, gfp_t gfp_flags, +@@ -501,7 +492,7 @@ p = alloc_page(gfp_flags); if (!p) { @@ -99324,7 +99238,7 @@ /* store already allocated pages in the pool after * setting the caching state */ -@@ -599,8 +590,7 @@ static void ttm_page_pool_fill_locked(struct ttm_page_pool *pool, +@@ -599,8 +590,7 @@ ++pool->nrefills; pool->npages += alloc_size; } else { @@ -99334,7 +99248,7 @@ /* If we have any pages left put them to the pool. */ list_for_each_entry(p, &pool->list, lru) { ++cpages; -@@ -619,8 +609,10 @@ static void ttm_page_pool_fill_locked(struct ttm_page_pool *pool, +@@ -619,8 +609,10 @@ * @return count of pages still required to fulfill the request. */ static unsigned ttm_page_pool_get_pages(struct ttm_page_pool *pool, @@ -99347,7 +99261,7 @@ { unsigned long irq_flags; struct list_head *p; -@@ -660,17 +652,63 @@ out: +@@ -660,17 +652,63 @@ return count; } @@ -99414,7 +99328,7 @@ int r; /* set zero flag for page allocation if required */ -@@ -684,30 +722,33 @@ int ttm_get_pages(struct list_head *pages, int flags, +@@ -684,30 +722,33 @@ else gfp_flags |= GFP_HIGHUSER; @@ -99455,7 +99369,7 @@ if (PageHighMem(p)) clear_highpage(p); else -@@ -716,67 +757,27 @@ int ttm_get_pages(struct list_head *pages, int flags, +@@ -716,67 +757,27 @@ } /* If pool didn't have enough pages allocate new one. */ @@ -99531,7 +99445,7 @@ static void ttm_page_pool_init_locked(struct ttm_page_pool *pool, int flags, char *name) { -@@ -794,7 +795,7 @@ int ttm_page_alloc_init(struct ttm_mem_global *glob, unsigned max_pages) +@@ -794,7 +795,7 @@ WARN_ON(_manager); @@ -99540,7 +99454,7 @@ _manager = kzalloc(sizeof(*_manager), GFP_KERNEL); -@@ -829,7 +830,7 @@ void ttm_page_alloc_fini(void) +@@ -829,7 +830,7 @@ { int i; @@ -99549,7 +99463,7 @@ ttm_pool_mm_shrink_fini(_manager); for (i = 0; i < NUM_POOLS; ++i) -@@ -839,6 +840,62 @@ void ttm_page_alloc_fini(void) +@@ -839,6 +840,62 @@ _manager = NULL; } @@ -99612,11 +99526,10 @@ int ttm_page_alloc_debugfs(struct seq_file *m, void *data) { struct ttm_page_pool *p; -diff --git a/drivers/gpu/drm/ttm/ttm_page_alloc_dma.c b/drivers/gpu/drm/ttm/ttm_page_alloc_dma.c -new file mode 100644 -index 0000000..4f9e548 ---- /dev/null -+++ b/drivers/gpu/drm/ttm/ttm_page_alloc_dma.c +Index: linux-3.2.46/drivers/gpu/drm/ttm/ttm_page_alloc_dma.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/ttm/ttm_page_alloc_dma.c 2013-07-26 19:26:24.000000000 +0000 @@ -0,0 +1,1134 @@ +/* + * Copyright 2011 (c) Oracle Corp. @@ -100752,10 +100665,10 @@ + return 0; +} +EXPORT_SYMBOL_GPL(ttm_dma_page_alloc_debugfs); -diff --git a/drivers/gpu/drm/ttm/ttm_tt.c b/drivers/gpu/drm/ttm/ttm_tt.c -index f9cc548..fa09daf 100644 ---- a/drivers/gpu/drm/ttm/ttm_tt.c -+++ b/drivers/gpu/drm/ttm/ttm_tt.c +Index: linux-3.2.46/drivers/gpu/drm/ttm/ttm_tt.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/ttm/ttm_tt.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/ttm/ttm_tt.c 2013-07-26 19:26:24.000000000 +0000 @@ -28,6 +28,8 @@ * Authors: Thomas Hellstrom */ @@ -100824,12 +100737,10 @@ - ttm->state = tt_unpopulated; - ttm->first_himem_page = ttm->num_pages; - ttm->last_lomem_page = -1; -+ ttm->pages = drm_calloc_large(ttm->num_pages, sizeof(void*)); - } - +-} +- -static struct page *__ttm_tt_get_page(struct ttm_tt *ttm, int index) -+static void ttm_dma_tt_alloc_page_directory(struct ttm_dma_tt *ttm) - { +-{ - struct page *p; - struct list_head h; - struct ttm_mem_global *mem_glob = ttm->glob->mem_glob; @@ -100872,10 +100783,12 @@ - return NULL; - } - return __ttm_tt_get_page(ttm, index); --} -- ++ ttm->pages = drm_calloc_large(ttm->num_pages, sizeof(void*)); + } + -int ttm_tt_populate(struct ttm_tt *ttm) --{ ++static void ttm_dma_tt_alloc_page_directory(struct ttm_dma_tt *ttm) + { - struct page *page; - unsigned long i; - struct ttm_backend *be; @@ -100910,7 +100823,7 @@ #ifdef CONFIG_X86 static inline int ttm_tt_set_page_caching(struct page *p, -@@ -278,153 +161,100 @@ int ttm_tt_set_placement_caching(struct ttm_tt *ttm, uint32_t placement) +@@ -278,153 +161,100 @@ } EXPORT_SYMBOL(ttm_tt_set_placement_caching); @@ -101005,11 +100918,6 @@ - false, false); - if (unlikely(ret != 0)) - return ret; -- -- down_read(&mm->mmap_sem); -- ret = get_user_pages(tsk, mm, start, num_pages, -- write, 0, ttm->pages, NULL); -- up_read(&mm->mmap_sem); + ttm->bdev = bdev; + ttm->glob = bdev->glob; + ttm->num_pages = (size + PAGE_SIZE - 1) >> PAGE_SHIFT; @@ -101019,6 +100927,11 @@ + ttm->state = tt_unpopulated; + ttm->swap_storage = NULL; +- down_read(&mm->mmap_sem); +- ret = get_user_pages(tsk, mm, start, num_pages, +- write, 0, ttm->pages, NULL); +- up_read(&mm->mmap_sem); +- - if (ret != num_pages && write) { - ttm_tt_free_user_pages(ttm); - ttm_mem_global_free(mem_glob, num_pages * PAGE_SIZE); @@ -101117,7 +101030,7 @@ BUG_ON(ret); ttm->state = tt_unbound; } -@@ -433,7 +263,6 @@ void ttm_tt_unbind(struct ttm_tt *ttm) +@@ -433,7 +263,6 @@ int ttm_tt_bind(struct ttm_tt *ttm, struct ttm_mem_reg *bo_mem) { int ret = 0; @@ -101125,7 +101038,7 @@ if (!ttm) return -EINVAL; -@@ -441,25 +270,21 @@ int ttm_tt_bind(struct ttm_tt *ttm, struct ttm_mem_reg *bo_mem) +@@ -441,25 +270,21 @@ if (ttm->state == tt_bound) return 0; @@ -101154,7 +101067,7 @@ { struct address_space *swap_space; struct file *swap_storage; -@@ -470,16 +295,6 @@ static int ttm_tt_swapin(struct ttm_tt *ttm) +@@ -470,16 +295,6 @@ int i; int ret = -ENOMEM; @@ -101171,7 +101084,7 @@ swap_storage = ttm->swap_storage; BUG_ON(swap_storage == NULL); -@@ -491,16 +306,16 @@ static int ttm_tt_swapin(struct ttm_tt *ttm) +@@ -491,16 +306,16 @@ ret = PTR_ERR(from_page); goto out_err; } @@ -101193,7 +101106,7 @@ preempt_enable(); page_cache_release(from_page); } -@@ -512,7 +327,6 @@ static int ttm_tt_swapin(struct ttm_tt *ttm) +@@ -512,7 +327,6 @@ return 0; out_err: @@ -101201,7 +101114,7 @@ return ret; } -@@ -530,24 +344,12 @@ int ttm_tt_swapout(struct ttm_tt *ttm, struct file *persistent_swap_storage) +@@ -530,24 +344,12 @@ BUG_ON(ttm->state != tt_unbound && ttm->state != tt_unpopulated); BUG_ON(ttm->caching_state != tt_cached); @@ -101227,7 +101140,7 @@ return PTR_ERR(swap_storage); } } else -@@ -565,18 +367,18 @@ int ttm_tt_swapout(struct ttm_tt *ttm, struct file *persistent_swap_storage) +@@ -565,18 +367,18 @@ goto out_err; } preempt_disable(); @@ -101251,11 +101164,10 @@ ttm->swap_storage = swap_storage; ttm->page_flags |= TTM_PAGE_FLAG_SWAPPED; if (persistent_swap_storage) -diff --git a/drivers/gpu/drm/udl/Kconfig b/drivers/gpu/drm/udl/Kconfig -new file mode 100644 -index 0000000..0b5e096 ---- /dev/null -+++ b/drivers/gpu/drm/udl/Kconfig +Index: linux-3.2.46/drivers/gpu/drm/udl/Kconfig +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/udl/Kconfig 2013-07-26 19:26:24.000000000 +0000 @@ -0,0 +1,12 @@ +config DRM_UDL + tristate "DisplayLink" @@ -101269,11 +101181,10 @@ + help + This is a KMS driver for the USB displaylink video adapters. + Say M/Y to add support for these devices via drm/kms interfaces. -diff --git a/drivers/gpu/drm/udl/Makefile b/drivers/gpu/drm/udl/Makefile -new file mode 100644 -index 0000000..05c7481 ---- /dev/null -+++ b/drivers/gpu/drm/udl/Makefile +Index: linux-3.2.46/drivers/gpu/drm/udl/Makefile +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/udl/Makefile 2013-07-26 19:26:24.000000000 +0000 @@ -0,0 +1,6 @@ + +ccflags-y := -Iinclude/drm @@ -101281,11 +101192,10 @@ +udl-y := udl_drv.o udl_modeset.o udl_connector.o udl_encoder.o udl_main.o udl_fb.o udl_transfer.o udl_gem.o + +obj-$(CONFIG_DRM_UDL) := udl.o -diff --git a/drivers/gpu/drm/udl/udl_connector.c b/drivers/gpu/drm/udl/udl_connector.c -new file mode 100644 -index 0000000..b8e6463 ---- /dev/null -+++ b/drivers/gpu/drm/udl/udl_connector.c +Index: linux-3.2.46/drivers/gpu/drm/udl/udl_connector.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/udl/udl_connector.c 2013-07-26 19:26:24.000000000 +0000 @@ -0,0 +1,165 @@ +/* + * Copyright (C) 2012 Red Hat @@ -101452,11 +101362,10 @@ + 1); + return 0; +} -diff --git a/drivers/gpu/drm/udl/udl_drv.c b/drivers/gpu/drm/udl/udl_drv.c -new file mode 100644 -index 0000000..08eff0d ---- /dev/null -+++ b/drivers/gpu/drm/udl/udl_drv.c +Index: linux-3.2.46/drivers/gpu/drm/udl/udl_drv.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/udl/udl_drv.c 2013-07-26 19:26:24.000000000 +0000 @@ -0,0 +1,112 @@ +/* + * Copyright (C) 2012 Red Hat @@ -101570,11 +101479,10 @@ + +module_init(udl_init); +module_exit(udl_exit); -diff --git a/drivers/gpu/drm/udl/udl_drv.h b/drivers/gpu/drm/udl/udl_drv.h -new file mode 100644 -index 0000000..2b8c4fd ---- /dev/null -+++ b/drivers/gpu/drm/udl/udl_drv.h +Index: linux-3.2.46/drivers/gpu/drm/udl/udl_drv.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/udl/udl_drv.h 2013-07-26 19:26:24.000000000 +0000 @@ -0,0 +1,144 @@ +/* + * Copyright (C) 2012 Red Hat @@ -101720,11 +101628,10 @@ +#define CMD_WRITE_RLX16 "\xAF\x6B" /**< 16 bit extended run length command. */ + +#endif -diff --git a/drivers/gpu/drm/udl/udl_encoder.c b/drivers/gpu/drm/udl/udl_encoder.c -new file mode 100644 -index 0000000..56e75f0 ---- /dev/null -+++ b/drivers/gpu/drm/udl/udl_encoder.c +Index: linux-3.2.46/drivers/gpu/drm/udl/udl_encoder.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/udl/udl_encoder.c 2013-07-26 19:26:24.000000000 +0000 @@ -0,0 +1,80 @@ +/* + * Copyright (C) 2012 Red Hat @@ -101806,11 +101713,10 @@ + encoder->possible_crtcs = 1; + return encoder; +} -diff --git a/drivers/gpu/drm/udl/udl_fb.c b/drivers/gpu/drm/udl/udl_fb.c -new file mode 100644 -index 0000000..f02d223 ---- /dev/null -+++ b/drivers/gpu/drm/udl/udl_fb.c +Index: linux-3.2.46/drivers/gpu/drm/udl/udl_fb.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/udl/udl_fb.c 2013-07-26 19:26:24.000000000 +0000 @@ -0,0 +1,649 @@ +/* + * Copyright (C) 2012 Red Hat @@ -102461,11 +102367,10 @@ + } + return &ufb->base; +} -diff --git a/drivers/gpu/drm/udl/udl_gem.c b/drivers/gpu/drm/udl/udl_gem.c -new file mode 100644 -index 0000000..92f19ef ---- /dev/null -+++ b/drivers/gpu/drm/udl/udl_gem.c +Index: linux-3.2.46/drivers/gpu/drm/udl/udl_gem.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/udl/udl_gem.c 2013-07-26 19:26:24.000000000 +0000 @@ -0,0 +1,241 @@ +/* + * Copyright (C) 2012 Red Hat @@ -102708,11 +102613,10 @@ + mutex_unlock(&dev->struct_mutex); + return ret; +} -diff --git a/drivers/gpu/drm/udl/udl_main.c b/drivers/gpu/drm/udl/udl_main.c -new file mode 100644 -index 0000000..a8d5f09 ---- /dev/null -+++ b/drivers/gpu/drm/udl/udl_main.c +Index: linux-3.2.46/drivers/gpu/drm/udl/udl_main.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/udl/udl_main.c 2013-07-26 19:26:24.000000000 +0000 @@ -0,0 +1,338 @@ +/* + * Copyright (C) 2012 Red Hat @@ -103052,11 +102956,10 @@ + kfree(udl); + return 0; +} -diff --git a/drivers/gpu/drm/udl/udl_modeset.c b/drivers/gpu/drm/udl/udl_modeset.c -new file mode 100644 -index 0000000..b3ecb3d ---- /dev/null -+++ b/drivers/gpu/drm/udl/udl_modeset.c +Index: linux-3.2.46/drivers/gpu/drm/udl/udl_modeset.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/udl/udl_modeset.c 2013-07-26 19:26:24.000000000 +0000 @@ -0,0 +1,414 @@ +/* + * Copyright (C) 2012 Red Hat @@ -103472,11 +103375,10 @@ +{ + drm_mode_config_cleanup(dev); +} -diff --git a/drivers/gpu/drm/udl/udl_transfer.c b/drivers/gpu/drm/udl/udl_transfer.c -new file mode 100644 -index 0000000..fc11344 ---- /dev/null -+++ b/drivers/gpu/drm/udl/udl_transfer.c +Index: linux-3.2.46/drivers/gpu/drm/udl/udl_transfer.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/udl/udl_transfer.c 2013-07-26 19:26:24.000000000 +0000 @@ -0,0 +1,254 @@ +/* + * Copyright (C) 2012 Red Hat @@ -103732,10 +103634,10 @@ + return 0; +} + -diff --git a/drivers/gpu/drm/via/via_drv.c b/drivers/gpu/drm/via/via_drv.c -index a83e86d..02661f3 100644 ---- a/drivers/gpu/drm/via/via_drv.c -+++ b/drivers/gpu/drm/via/via_drv.c +Index: linux-3.2.46/drivers/gpu/drm/via/via_drv.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/via/via_drv.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/via/via_drv.c 2013-07-26 19:26:24.000000000 +0000 @@ -30,16 +30,52 @@ #include "drm_pciids.h" @@ -103789,7 +103691,7 @@ .context_dtor = via_final_context, .get_vblank_counter = via_get_vblank_counter, .enable_vblank = via_enable_vblank, -@@ -54,17 +90,7 @@ static struct drm_driver driver = { +@@ -54,17 +90,7 @@ .reclaim_buffers_idlelocked = via_reclaim_buffers_locked, .lastclose = via_lastclose, .ioctls = via_ioctls, @@ -103808,10 +103710,10 @@ .name = DRIVER_NAME, .desc = DRIVER_DESC, .date = DRIVER_DATE, -diff --git a/drivers/gpu/drm/via/via_drv.h b/drivers/gpu/drm/via/via_drv.h -index 9cf87d9..88edacc 100644 ---- a/drivers/gpu/drm/via/via_drv.h -+++ b/drivers/gpu/drm/via/via_drv.h +Index: linux-3.2.46/drivers/gpu/drm/via/via_drv.h +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/via/via_drv.h 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/via/via_drv.h 2013-07-26 19:26:24.000000000 +0000 @@ -24,7 +24,7 @@ #ifndef _VIA_DRV_H_ #define _VIA_DRV_H_ @@ -103821,7 +103723,7 @@ #define DRIVER_AUTHOR "Various" #define DRIVER_NAME "via" -@@ -88,9 +88,12 @@ typedef struct drm_via_private { +@@ -88,9 +88,12 @@ uint32_t irq_pending_mask; int *irq_map; unsigned int idle_fault; @@ -103835,11 +103737,11 @@ unsigned long vram_offset; unsigned long agp_offset; drm_via_blitq_t blit_queues[VIA_NUM_BLIT_ENGINES]; -diff --git a/drivers/gpu/drm/via/via_map.c b/drivers/gpu/drm/via/via_map.c -index 6cca9a7..c126182 100644 ---- a/drivers/gpu/drm/via/via_map.c -+++ b/drivers/gpu/drm/via/via_map.c -@@ -100,19 +100,15 @@ int via_driver_load(struct drm_device *dev, unsigned long chipset) +Index: linux-3.2.46/drivers/gpu/drm/via/via_map.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/via/via_map.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/via/via_map.c 2013-07-26 19:26:24.000000000 +0000 +@@ -100,19 +100,15 @@ if (dev_priv == NULL) return -ENOMEM; @@ -103861,7 +103763,7 @@ kfree(dev_priv); return ret; } -@@ -124,7 +120,8 @@ int via_driver_unload(struct drm_device *dev) +@@ -124,7 +120,8 @@ { drm_via_private_t *dev_priv = dev->dev_private; @@ -103871,10 +103773,10 @@ kfree(dev_priv); -diff --git a/drivers/gpu/drm/via/via_mm.c b/drivers/gpu/drm/via/via_mm.c -index 6cc2dad..a3574d0 100644 ---- a/drivers/gpu/drm/via/via_mm.c -+++ b/drivers/gpu/drm/via/via_mm.c +Index: linux-3.2.46/drivers/gpu/drm/via/via_mm.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/via/via_mm.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/via/via_mm.c 2013-07-26 19:26:24.000000000 +0000 @@ -28,26 +28,22 @@ #include "drmP.h" #include "via_drm.h" @@ -103908,7 +103810,7 @@ dev_priv->agp_initialized = 1; dev_priv->agp_offset = agp->offset; -@@ -61,17 +57,9 @@ int via_fb_init(struct drm_device *dev, void *data, struct drm_file *file_priv) +@@ -61,17 +57,9 @@ { drm_via_fb_t *fb = data; drm_via_private_t *dev_priv = (drm_via_private_t *) dev->dev_private; @@ -103927,7 +103829,7 @@ dev_priv->vram_initialized = 1; dev_priv->vram_offset = fb->offset; -@@ -108,19 +96,25 @@ void via_lastclose(struct drm_device *dev) +@@ -108,19 +96,25 @@ return; mutex_lock(&dev->struct_mutex); @@ -103959,7 +103861,7 @@ unsigned long tmpSize; if (mem->type > VIA_MEM_AGP) { -@@ -136,24 +130,57 @@ int via_mem_alloc(struct drm_device *dev, void *data, +@@ -136,24 +130,57 @@ return -EINVAL; } @@ -104031,7 +103933,7 @@ return retval; } -@@ -161,24 +188,35 @@ int via_mem_free(struct drm_device *dev, void *data, struct drm_file *file_priv) +@@ -161,24 +188,35 @@ { drm_via_private_t *dev_priv = dev->dev_private; drm_via_mem_t *mem = data; @@ -104073,7 +103975,7 @@ mutex_unlock(&dev->struct_mutex); return; } -@@ -186,7 +224,12 @@ void via_reclaim_buffers_locked(struct drm_device *dev, +@@ -186,7 +224,12 @@ if (dev->driver->dma_quiescent) dev->driver->dma_quiescent(dev); @@ -104087,10 +103989,10 @@ mutex_unlock(&dev->struct_mutex); return; } -diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_buffer.c b/drivers/gpu/drm/vmwgfx/vmwgfx_buffer.c -index 5a72ed9..1e2c0fb 100644 ---- a/drivers/gpu/drm/vmwgfx/vmwgfx_buffer.c -+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_buffer.c +Index: linux-3.2.46/drivers/gpu/drm/vmwgfx/vmwgfx_buffer.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/vmwgfx/vmwgfx_buffer.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/vmwgfx/vmwgfx_buffer.c 2013-07-26 19:26:24.000000000 +0000 @@ -28,6 +28,7 @@ #include "vmwgfx_drv.h" #include "ttm/ttm_bo_driver.h" @@ -104099,7 +104001,7 @@ static uint32_t vram_placement_flags = TTM_PL_FLAG_VRAM | TTM_PL_FLAG_CACHED; -@@ -139,85 +140,63 @@ struct ttm_placement vmw_srf_placement = { +@@ -139,85 +140,63 @@ .busy_placement = gmr_vram_placement_flags }; @@ -104207,7 +104109,7 @@ } int vmw_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags) -@@ -357,7 +336,9 @@ static int vmw_sync_obj_wait(void *sync_obj, void *sync_arg, +@@ -357,7 +336,9 @@ } struct ttm_bo_driver vmw_bo_driver = { @@ -104218,10 +104120,10 @@ .invalidate_caches = vmw_invalidate_caches, .init_mem_type = vmw_init_mem_type, .evict_flags = vmw_evict_flags, -diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c b/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c -index b639536..db50604 100644 ---- a/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c -+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c +Index: linux-3.2.46/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c 2013-07-26 19:26:24.000000000 +0000 @@ -38,6 +38,10 @@ #define VMWGFX_CHIP_SVGAII 0 #define VMW_FB_RESERVATION 0 @@ -104233,7 +104135,7 @@ /** * Fully encoded drm commands. Might move to vmw_drm.h */ -@@ -388,6 +392,41 @@ void vmw_3d_resource_dec(struct vmw_private *dev_priv, +@@ -388,6 +392,41 @@ BUG_ON(n3d < 0); } @@ -104275,7 +104177,7 @@ static int vmw_driver_load(struct drm_device *dev, unsigned long chipset) { struct vmw_private *dev_priv; -@@ -401,6 +440,8 @@ static int vmw_driver_load(struct drm_device *dev, unsigned long chipset) +@@ -401,6 +440,8 @@ } memset(dev_priv, 0, sizeof(*dev_priv)); @@ -104284,7 +104186,7 @@ dev_priv->dev = dev; dev_priv->vmw_chipset = chipset; dev_priv->last_read_seqno = (uint32_t) -100; -@@ -431,7 +472,7 @@ static int vmw_driver_load(struct drm_device *dev, unsigned long chipset) +@@ -431,7 +472,7 @@ svga_id = vmw_read(dev_priv, SVGA_REG_ID); if (svga_id != SVGA_ID_2) { ret = -ENOSYS; @@ -104293,7 +104195,7 @@ mutex_unlock(&dev_priv->hw_mutex); goto out_err0; } -@@ -442,6 +483,9 @@ static int vmw_driver_load(struct drm_device *dev, unsigned long chipset) +@@ -442,6 +483,9 @@ dev_priv->mmio_size = vmw_read(dev_priv, SVGA_REG_MEM_SIZE); dev_priv->fb_max_width = vmw_read(dev_priv, SVGA_REG_MAX_WIDTH); dev_priv->fb_max_height = vmw_read(dev_priv, SVGA_REG_MAX_HEIGHT); @@ -104303,7 +104205,7 @@ if (dev_priv->capabilities & SVGA_CAP_GMR) { dev_priv->max_gmr_descriptors = vmw_read(dev_priv, -@@ -689,6 +733,15 @@ static int vmw_driver_unload(struct drm_device *dev) +@@ -689,6 +733,15 @@ return 0; } @@ -104319,7 +104221,7 @@ static void vmw_postclose(struct drm_device *dev, struct drm_file *file_priv) { -@@ -711,6 +764,7 @@ static int vmw_driver_open(struct drm_device *dev, struct drm_file *file_priv) +@@ -711,6 +764,7 @@ if (unlikely(vmw_fp == NULL)) return ret; @@ -104327,7 +104229,7 @@ vmw_fp->tfile = ttm_object_file_init(dev_priv->tdev, 10); if (unlikely(vmw_fp->tfile == NULL)) goto out_no_tfile; -@@ -1070,6 +1124,21 @@ static const struct dev_pm_ops vmw_pm_ops = { +@@ -1070,6 +1124,21 @@ .resume = vmw_pm_resume, }; @@ -104349,7 +104251,7 @@ static struct drm_driver driver = { .driver_features = DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_MODESET, -@@ -1093,26 +1162,14 @@ static struct drm_driver driver = { +@@ -1093,26 +1162,14 @@ .master_set = vmw_master_set, .master_drop = vmw_master_drop, .open = vmw_driver_open, @@ -104378,10 +104280,10 @@ .name = VMWGFX_DRIVER_NAME, .desc = VMWGFX_DRIVER_DESC, .date = VMWGFX_DRIVER_DATE, -diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_drv.h b/drivers/gpu/drm/vmwgfx/vmwgfx_drv.h -index 0e3fa7d..29c984f 100644 ---- a/drivers/gpu/drm/vmwgfx/vmwgfx_drv.h -+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_drv.h +Index: linux-3.2.46/drivers/gpu/drm/vmwgfx/vmwgfx_drv.h +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/vmwgfx/vmwgfx_drv.h 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/vmwgfx/vmwgfx_drv.h 2013-07-26 19:26:24.000000000 +0000 @@ -40,9 +40,9 @@ #include "ttm/ttm_module.h" #include "vmwgfx_fence.h" @@ -104402,7 +104304,7 @@ }; struct vmw_dma_buffer { -@@ -202,6 +203,8 @@ struct vmw_private { +@@ -202,6 +203,8 @@ uint32_t mmio_size; uint32_t fb_max_width; uint32_t fb_max_height; @@ -104411,7 +104313,7 @@ __le32 __iomem *mmio_virt; int mmio_mtrr; uint32_t capabilities; -@@ -533,7 +536,8 @@ extern int vmw_execbuf_process(struct drm_file *file_priv, +@@ -533,7 +536,8 @@ uint32_t command_size, uint64_t throttle_us, struct drm_vmw_fence_rep __user @@ -104421,11 +104323,11 @@ extern void vmw_execbuf_release_pinned_bo(struct vmw_private *dev_priv, -diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c b/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c -index 40932fb..4acced4 100644 ---- a/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c -+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c -@@ -1109,10 +1109,11 @@ int vmw_execbuf_process(struct drm_file *file_priv, +Index: linux-3.2.46/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c 2013-07-26 19:26:24.000000000 +0000 +@@ -1109,10 +1109,11 @@ void *kernel_commands, uint32_t command_size, uint64_t throttle_us, @@ -104439,7 +104341,7 @@ uint32_t handle; void *cmd; int ret; -@@ -1208,8 +1209,13 @@ int vmw_execbuf_process(struct drm_file *file_priv, +@@ -1208,8 +1209,13 @@ vmw_execbuf_copy_fence_user(dev_priv, vmw_fpriv(file_priv), ret, user_fence_rep, fence, handle); @@ -104454,7 +104356,7 @@ mutex_unlock(&dev_priv->cmdbuf_mutex); return 0; -@@ -1362,7 +1368,8 @@ int vmw_execbuf_ioctl(struct drm_device *dev, void *data, +@@ -1362,7 +1368,8 @@ ret = vmw_execbuf_process(file_priv, dev_priv, (void __user *)(unsigned long)arg->commands, NULL, arg->command_size, arg->throttle_us, @@ -104464,11 +104366,11 @@ if (unlikely(ret != 0)) goto out_unlock; -diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_fb.c b/drivers/gpu/drm/vmwgfx/vmwgfx_fb.c -index 34e51a1..3c447bf 100644 ---- a/drivers/gpu/drm/vmwgfx/vmwgfx_fb.c -+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_fb.c -@@ -414,10 +414,6 @@ int vmw_fb_init(struct vmw_private *vmw_priv) +Index: linux-3.2.46/drivers/gpu/drm/vmwgfx/vmwgfx_fb.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/vmwgfx/vmwgfx_fb.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/vmwgfx/vmwgfx_fb.c 2013-07-26 19:26:24.000000000 +0000 +@@ -414,10 +414,6 @@ unsigned fb_bpp, fb_depth, fb_offset, fb_pitch, fb_size; int ret; @@ -104479,7 +104381,7 @@ fb_bpp = 32; fb_depth = 24; -@@ -425,8 +421,8 @@ int vmw_fb_init(struct vmw_private *vmw_priv) +@@ -425,8 +421,8 @@ fb_width = min(vmw_priv->fb_max_width, (unsigned)2048); fb_height = min(vmw_priv->fb_max_height, (unsigned)2048); @@ -104490,7 +104392,7 @@ fb_pitch = fb_width * fb_bpp / 8; fb_size = fb_pitch * fb_height; -@@ -515,19 +511,7 @@ int vmw_fb_init(struct vmw_private *vmw_priv) +@@ -515,19 +511,7 @@ info->var.xres = initial_width; info->var.yres = initial_height; @@ -104511,11 +104413,11 @@ info->apertures = alloc_apertures(1); if (!info->apertures) { -diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_fence.c b/drivers/gpu/drm/vmwgfx/vmwgfx_fence.c -index 15fb260..7e07433 100644 ---- a/drivers/gpu/drm/vmwgfx/vmwgfx_fence.c -+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_fence.c -@@ -69,12 +69,13 @@ struct vmw_user_fence { +Index: linux-3.2.46/drivers/gpu/drm/vmwgfx/vmwgfx_fence.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/vmwgfx/vmwgfx_fence.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/vmwgfx/vmwgfx_fence.c 2013-07-26 19:26:24.000000000 +0000 +@@ -69,12 +69,13 @@ * be assigned the current time tv_usec val when the fence signals. */ struct vmw_event_fence_action { @@ -104532,7 +104434,7 @@ uint32_t *tv_sec; uint32_t *tv_usec; }; -@@ -784,46 +785,40 @@ int vmw_fence_obj_unref_ioctl(struct drm_device *dev, void *data, +@@ -784,46 +785,40 @@ } /** @@ -104565,14 +104467,15 @@ * - * @e: The struct drm_pending_event embedded in a struct - * vmw_event_fence_action. -+ * @fman: Pointer to a struct vmw_fence_manager -+ * @event_list: Pointer to linked list of struct vmw_event_fence_action objects -+ * with pointers to a struct drm_file object about to be closed. - * +- * - * The struct drm_pending_event destructor that is called by drm - * once the event is delivered. Since we don't know whether this function - * will be called before or after the fence action destructor, we - * free a refcount and destroy if it becomes zero. ++ * @fman: Pointer to a struct vmw_fence_manager ++ * @event_list: Pointer to linked list of struct vmw_event_fence_action objects ++ * with pointers to a struct drm_file object about to be closed. ++ * + * This function removes all pending fence events with references to a + * specific struct drm_file object about to be closed. The caller is required + * to pass a list of all struct vmw_event_fence_action objects with such @@ -104608,7 +104511,7 @@ } -@@ -836,18 +831,21 @@ static void vmw_event_fence_action_delivered(struct drm_pending_event *e) +@@ -836,18 +831,21 @@ * This function is called when the seqno of the fence where @action is * attached has passed. It queues the event on the submitter's event list. * This function is always called from atomic context, and may be called @@ -104634,7 +104537,7 @@ spin_lock_irqsave(&dev->event_lock, irq_flags); if (likely(eaction->tv_sec != NULL)) { -@@ -858,7 +856,9 @@ static void vmw_event_fence_action_seq_passed(struct vmw_fence_action *action) +@@ -858,7 +856,9 @@ *eaction->tv_usec = tv.tv_usec; } @@ -104645,7 +104548,7 @@ wake_up_all(&file_priv->event_wait); spin_unlock_irqrestore(&dev->event_lock, irq_flags); } -@@ -876,9 +876,15 @@ static void vmw_event_fence_action_cleanup(struct vmw_fence_action *action) +@@ -876,9 +876,15 @@ { struct vmw_event_fence_action *eaction = container_of(action, struct vmw_event_fence_action, action); @@ -104662,7 +104565,7 @@ } -@@ -946,39 +952,23 @@ void vmw_fence_obj_add_action(struct vmw_fence_obj *fence, +@@ -946,39 +952,23 @@ * an error code, the caller needs to free that object. */ @@ -104712,7 +104615,7 @@ eaction->action.seq_passed = vmw_event_fence_action_seq_passed; eaction->action.cleanup = vmw_event_fence_action_cleanup; -@@ -986,16 +976,89 @@ int vmw_event_fence_action_create(struct drm_file *file_priv, +@@ -986,16 +976,89 @@ eaction->fence = vmw_fence_obj_reference(fence); eaction->dev = fman->dev_priv->dev; @@ -104804,7 +104707,7 @@ int vmw_fence_event_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv) { -@@ -1008,8 +1071,6 @@ int vmw_fence_event_ioctl(struct drm_device *dev, void *data, +@@ -1008,8 +1071,6 @@ (struct drm_vmw_fence_rep __user *)(unsigned long) arg->fence_rep; uint32_t handle; @@ -104813,7 +104716,7 @@ int ret; /* -@@ -1062,59 +1123,28 @@ int vmw_fence_event_ioctl(struct drm_device *dev, void *data, +@@ -1062,59 +1123,28 @@ BUG_ON(fence == NULL); @@ -104879,11 +104782,11 @@ if (user_fence_rep != NULL) ttm_ref_object_base_unref(vmw_fpriv(file_priv)->tfile, handle, TTM_REF_USAGE); -diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_fence.h b/drivers/gpu/drm/vmwgfx/vmwgfx_fence.h -index 0854a20..faf2e78 100644 ---- a/drivers/gpu/drm/vmwgfx/vmwgfx_fence.h -+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_fence.h -@@ -109,5 +109,12 @@ extern int vmw_fence_obj_unref_ioctl(struct drm_device *dev, void *data, +Index: linux-3.2.46/drivers/gpu/drm/vmwgfx/vmwgfx_fence.h +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/vmwgfx/vmwgfx_fence.h 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/vmwgfx/vmwgfx_fence.h 2013-07-26 19:26:24.000000000 +0000 +@@ -109,5 +109,12 @@ struct drm_file *file_priv); extern int vmw_fence_event_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv); @@ -104897,11 +104800,11 @@ + uint32_t *tv_usec, + bool interruptible); #endif /* _VMWGFX_FENCE_H_ */ -diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_gmr.c b/drivers/gpu/drm/vmwgfx/vmwgfx_gmr.c -index c41226a..21ee782 100644 ---- a/drivers/gpu/drm/vmwgfx/vmwgfx_gmr.c -+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_gmr.c -@@ -136,10 +136,10 @@ static int vmw_gmr_build_descriptors(struct list_head *desc_pages, +Index: linux-3.2.46/drivers/gpu/drm/vmwgfx/vmwgfx_gmr.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/vmwgfx/vmwgfx_gmr.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/vmwgfx/vmwgfx_gmr.c 2013-07-26 19:26:24.000000000 +0000 +@@ -136,10 +136,10 @@ if (likely(page_virtual != NULL)) { desc_virtual->ppn = page_to_pfn(page); @@ -104914,7 +104817,7 @@ desc_virtual = page_virtual - 1; prev_pfn = ~(0UL); -@@ -169,7 +169,7 @@ static int vmw_gmr_build_descriptors(struct list_head *desc_pages, +@@ -169,7 +169,7 @@ } if (likely(page_virtual != NULL)) @@ -104923,11 +104826,11 @@ return 0; out_err: -diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c b/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c -index 7c88f1f..00fb5aa 100644 ---- a/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c -+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c -@@ -422,7 +422,8 @@ static int do_surface_dirty_sou(struct vmw_private *dev_priv, +Index: linux-3.2.46/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c 2013-07-26 19:26:24.000000000 +0000 +@@ -422,7 +422,8 @@ struct vmw_framebuffer *framebuffer, unsigned flags, unsigned color, struct drm_clip_rect *clips, @@ -104937,7 +104840,7 @@ { struct vmw_display_unit *units[VMWGFX_NUM_DISPLAY_UNITS]; struct drm_clip_rect *clips_ptr; -@@ -542,12 +543,15 @@ static int do_surface_dirty_sou(struct vmw_private *dev_priv, +@@ -542,12 +543,15 @@ if (num == 0) continue; @@ -104954,7 +104857,7 @@ if (unlikely(ret != 0)) break; -@@ -598,7 +602,7 @@ int vmw_framebuffer_surface_dirty(struct drm_framebuffer *framebuffer, +@@ -598,7 +602,7 @@ ret = do_surface_dirty_sou(dev_priv, file_priv, &vfbs->base, flags, color, @@ -104963,7 +104866,7 @@ ttm_read_unlock(&vmaster->lock); return 0; -@@ -690,7 +694,7 @@ static int vmw_kms_new_framebuffer_surface(struct vmw_private *dev_priv, +@@ -690,7 +694,7 @@ /* XXX get the first 3 from the surface info */ vfbs->base.base.bits_per_pixel = mode_cmd->bpp; @@ -104972,7 +104875,7 @@ vfbs->base.base.depth = mode_cmd->depth; vfbs->base.base.width = mode_cmd->width; vfbs->base.base.height = mode_cmd->height; -@@ -804,12 +808,12 @@ static int do_dmabuf_define_gmrfb(struct drm_file *file_priv, +@@ -804,12 +808,12 @@ cmd->body.format.bitsPerPixel = framebuffer->base.bits_per_pixel; cmd->body.format.colorDepth = depth; cmd->body.format.reserved = 0; @@ -104987,7 +104890,7 @@ kfree(cmd); -@@ -821,7 +825,8 @@ static int do_dmabuf_dirty_sou(struct drm_file *file_priv, +@@ -821,7 +825,8 @@ struct vmw_framebuffer *framebuffer, unsigned flags, unsigned color, struct drm_clip_rect *clips, @@ -104997,7 +104900,7 @@ { struct vmw_display_unit *units[VMWGFX_NUM_DISPLAY_UNITS]; struct drm_clip_rect *clips_ptr; -@@ -894,9 +899,13 @@ static int do_dmabuf_dirty_sou(struct drm_file *file_priv, +@@ -894,9 +899,13 @@ if (hit_num == 0) continue; @@ -105012,7 +104915,7 @@ if (unlikely(ret != 0)) break; -@@ -942,7 +951,7 @@ int vmw_framebuffer_dmabuf_dirty(struct drm_framebuffer *framebuffer, +@@ -942,7 +951,7 @@ } else { ret = do_dmabuf_dirty_sou(file_priv, dev_priv, &vfbd->base, flags, color, @@ -105021,7 +104924,7 @@ } ttm_read_unlock(&vmaster->lock); -@@ -1056,7 +1065,7 @@ static int vmw_kms_new_framebuffer_dmabuf(struct vmw_private *dev_priv, +@@ -1056,7 +1065,7 @@ } vfbd->base.base.bits_per_pixel = mode_cmd->bpp; @@ -105030,7 +104933,7 @@ vfbd->base.base.depth = mode_cmd->depth; vfbd->base.base.width = mode_cmd->width; vfbd->base.base.height = mode_cmd->height; -@@ -1085,7 +1094,7 @@ out_err1: +@@ -1085,7 +1094,7 @@ static struct drm_framebuffer *vmw_kms_fb_create(struct drm_device *dev, struct drm_file *file_priv, @@ -105039,7 +104942,7 @@ { struct vmw_private *dev_priv = vmw_priv(dev); struct ttm_object_file *tfile = vmw_fpriv(file_priv)->tfile; -@@ -1093,8 +1102,16 @@ static struct drm_framebuffer *vmw_kms_fb_create(struct drm_device *dev, +@@ -1093,8 +1102,16 @@ struct vmw_surface *surface = NULL; struct vmw_dma_buffer *bo = NULL; struct ttm_base_object *user_obj; @@ -105056,7 +104959,7 @@ /** * This code should be conditioned on Screen Objects not being used. * If screen objects are used, we can allocate a GMR to hold the -@@ -1102,8 +1119,8 @@ static struct drm_framebuffer *vmw_kms_fb_create(struct drm_device *dev, +@@ -1102,8 +1119,8 @@ */ if (!vmw_kms_validate_mode_vram(dev_priv, @@ -105067,7 +104970,7 @@ DRM_ERROR("VRAM size is too small for requested mode.\n"); return ERR_PTR(-ENOMEM); } -@@ -1117,15 +1134,19 @@ static struct drm_framebuffer *vmw_kms_fb_create(struct drm_device *dev, +@@ -1117,15 +1134,19 @@ * command stream using user-space handles. */ @@ -105089,7 +104992,7 @@ &surface, &bo); if (ret) goto err_out; -@@ -1133,10 +1154,10 @@ static struct drm_framebuffer *vmw_kms_fb_create(struct drm_device *dev, +@@ -1133,10 +1154,10 @@ /* Create the new framebuffer depending one what we got back */ if (bo) ret = vmw_kms_new_framebuffer_dmabuf(dev_priv, bo, &vfb, @@ -105102,7 +105005,7 @@ else BUG(); -@@ -1284,7 +1305,7 @@ int vmw_kms_present(struct vmw_private *dev_priv, +@@ -1284,7 +1305,7 @@ fifo_size = sizeof(*cmd) + sizeof(SVGASignedRect) * num; cmd->header.size = cpu_to_le32(fifo_size - sizeof(cmd->header)); ret = vmw_execbuf_process(file_priv, dev_priv, NULL, cmd, @@ -105111,7 +105014,7 @@ if (unlikely(ret != 0)) break; -@@ -1344,7 +1365,7 @@ int vmw_kms_readback(struct vmw_private *dev_priv, +@@ -1344,7 +1365,7 @@ cmd->body.format.bitsPerPixel = vfb->base.bits_per_pixel; cmd->body.format.colorDepth = vfb->base.depth; cmd->body.format.reserved = 0; @@ -105120,7 +105023,7 @@ cmd->body.ptr.gmrId = vfb->user_handle; cmd->body.ptr.offset = 0; -@@ -1397,7 +1418,7 @@ int vmw_kms_readback(struct vmw_private *dev_priv, +@@ -1397,7 +1418,7 @@ fifo_size = sizeof(*cmd) + sizeof(*blits) * blits_pos; ret = vmw_execbuf_process(file_priv, dev_priv, NULL, cmd, fifo_size, @@ -105129,7 +105032,7 @@ kfree(cmd); -@@ -1660,6 +1681,74 @@ int vmw_du_update_layout(struct vmw_private *dev_priv, unsigned num, +@@ -1660,6 +1681,74 @@ return 0; } @@ -105204,10 +105107,10 @@ void vmw_du_crtc_save(struct drm_crtc *crtc) { } -diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_kms.h b/drivers/gpu/drm/vmwgfx/vmwgfx_kms.h -index e1cb855..8184bc5 100644 ---- a/drivers/gpu/drm/vmwgfx/vmwgfx_kms.h -+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_kms.h +Index: linux-3.2.46/drivers/gpu/drm/vmwgfx/vmwgfx_kms.h +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/vmwgfx/vmwgfx_kms.h 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/vmwgfx/vmwgfx_kms.h 2013-07-26 19:26:24.000000000 +0000 @@ -29,6 +29,7 @@ #define VMWGFX_KMS_H_ @@ -105216,7 +105119,7 @@ #include "vmwgfx_drv.h" #define VMWGFX_NUM_DISPLAY_UNITS 8 -@@ -120,6 +121,9 @@ struct vmw_display_unit { +@@ -120,6 +121,9 @@ * Shared display unit functions - vmwgfx_kms.c */ void vmw_display_unit_cleanup(struct vmw_display_unit *du); @@ -105226,7 +105129,7 @@ void vmw_du_crtc_save(struct drm_crtc *crtc); void vmw_du_crtc_restore(struct drm_crtc *crtc); void vmw_du_crtc_gamma_set(struct drm_crtc *crtc, -@@ -153,5 +157,10 @@ int vmw_kms_init_screen_object_display(struct vmw_private *dev_priv); +@@ -153,5 +157,10 @@ int vmw_kms_close_screen_object_display(struct vmw_private *dev_priv); int vmw_kms_sou_update_layout(struct vmw_private *dev_priv, unsigned num, struct drm_vmw_rect *rects); @@ -105237,11 +105140,11 @@ + #endif -diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c b/drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c -index 8f8dbd4..070fb23 100644 ---- a/drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c -+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c -@@ -95,7 +95,7 @@ static int vmw_ldu_commit_list(struct vmw_private *dev_priv) +Index: linux-3.2.46/drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/vmwgfx/vmwgfx_ldu.c 2013-07-26 19:26:24.000000000 +0000 +@@ -95,7 +95,7 @@ return 0; fb = entry->base.crtc.fb; @@ -105250,7 +105153,7 @@ fb->bits_per_pixel, fb->depth); } -@@ -103,7 +103,7 @@ static int vmw_ldu_commit_list(struct vmw_private *dev_priv) +@@ -103,7 +103,7 @@ entry = list_entry(lds->active.next, typeof(*entry), active); fb = entry->base.crtc.fb; @@ -105259,7 +105162,7 @@ fb->bits_per_pixel, fb->depth); } -@@ -354,8 +354,8 @@ static int vmw_ldu_init(struct vmw_private *dev_priv, unsigned unit) +@@ -354,8 +354,8 @@ INIT_LIST_HEAD(&ldu->active); ldu->base.pref_active = (unit == 0); @@ -105270,11 +105173,11 @@ ldu->base.pref_mode = NULL; ldu->base.is_implicit = true; -diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_resource.c b/drivers/gpu/drm/vmwgfx/vmwgfx_resource.c -index 0795d17..059b32c 100644 ---- a/drivers/gpu/drm/vmwgfx/vmwgfx_resource.c -+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_resource.c -@@ -1540,29 +1540,10 @@ out_bad_surface: +Index: linux-3.2.46/drivers/gpu/drm/vmwgfx/vmwgfx_resource.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/vmwgfx/vmwgfx_resource.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/vmwgfx/vmwgfx_resource.c 2013-07-26 19:26:24.000000000 +0000 +@@ -1540,29 +1540,10 @@ /** * Buffer management. */ @@ -105304,7 +105207,7 @@ kfree(vmw_bo); } -@@ -1573,24 +1554,12 @@ int vmw_dmabuf_init(struct vmw_private *dev_priv, +@@ -1573,24 +1554,12 @@ void (*bo_free) (struct ttm_buffer_object *bo)) { struct ttm_bo_device *bdev = &dev_priv->bdev; @@ -105330,7 +105233,7 @@ memset(vmw_bo, 0, sizeof(*vmw_bo)); INIT_LIST_HEAD(&vmw_bo->validate_list); -@@ -1605,9 +1574,7 @@ int vmw_dmabuf_init(struct vmw_private *dev_priv, +@@ -1605,9 +1574,7 @@ static void vmw_user_dmabuf_destroy(struct ttm_buffer_object *bo) { struct vmw_user_dma_buffer *vmw_user_bo = vmw_user_dma_buffer(bo); @@ -105340,11 +105243,11 @@ kfree(vmw_user_bo); } -diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c b/drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c -index 4defdcf..6deaf2f 100644 ---- a/drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c -+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c -@@ -394,6 +394,7 @@ static struct drm_crtc_funcs vmw_screen_object_crtc_funcs = { +Index: linux-3.2.46/drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/vmwgfx/vmwgfx_scrn.c 2013-07-26 19:26:24.000000000 +0000 +@@ -394,6 +394,7 @@ .gamma_set = vmw_du_crtc_gamma_set, .destroy = vmw_sou_crtc_destroy, .set_config = vmw_sou_crtc_set_config, @@ -105352,7 +105255,7 @@ }; /* -@@ -448,8 +449,8 @@ static int vmw_sou_init(struct vmw_private *dev_priv, unsigned unit) +@@ -448,8 +449,8 @@ sou->active_implicit = false; sou->base.pref_active = (unit == 0); @@ -105363,7 +105266,7 @@ sou->base.pref_mode = NULL; sou->base.is_implicit = true; -@@ -535,3 +536,36 @@ int vmw_kms_close_screen_object_display(struct vmw_private *dev_priv) +@@ -535,3 +536,36 @@ return 0; } @@ -105400,10 +105303,10 @@ + dev_priv->sou_priv->implicit_fb = + vmw_framebuffer_to_vfb(sou->base.crtc.fb); +} -diff --git a/include/drm/Kbuild b/include/drm/Kbuild -index 3a60ac8..1e38a19 100644 ---- a/include/drm/Kbuild -+++ b/include/drm/Kbuild +Index: linux-3.2.46/include/drm/Kbuild +=================================================================== +--- linux-3.2.46.orig/include/drm/Kbuild 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/include/drm/Kbuild 2013-07-26 19:26:25.000000000 +0000 @@ -1,6 +1,8 @@ header-y += drm.h +header-y += drm_fourcc.h @@ -105413,11 +105316,11 @@ header-y += i810_drm.h header-y += i915_drm.h header-y += mga_drm.h -diff --git a/include/drm/drm.h b/include/drm/drm.h -index 4be33b4..64ff02d 100644 ---- a/include/drm/drm.h -+++ b/include/drm/drm.h -@@ -617,6 +617,17 @@ struct drm_get_cap { +Index: linux-3.2.46/include/drm/drm.h +=================================================================== +--- linux-3.2.46.orig/include/drm/drm.h 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/include/drm/drm.h 2013-07-26 19:26:25.000000000 +0000 +@@ -617,6 +617,17 @@ __u64 value; }; @@ -105435,7 +105338,7 @@ #include "drm_mode.h" #define DRM_IOCTL_BASE 'd' -@@ -673,7 +684,8 @@ struct drm_get_cap { +@@ -673,7 +684,8 @@ #define DRM_IOCTL_UNLOCK DRM_IOW( 0x2b, struct drm_lock) #define DRM_IOCTL_FINISH DRM_IOW( 0x2c, struct drm_lock) @@ -105445,7 +105348,7 @@ #define DRM_IOCTL_AGP_ACQUIRE DRM_IO( 0x30) #define DRM_IOCTL_AGP_RELEASE DRM_IO( 0x31) -@@ -714,6 +726,10 @@ struct drm_get_cap { +@@ -714,6 +726,10 @@ #define DRM_IOCTL_MODE_CREATE_DUMB DRM_IOWR(0xB2, struct drm_mode_create_dumb) #define DRM_IOCTL_MODE_MAP_DUMB DRM_IOWR(0xB3, struct drm_mode_map_dumb) #define DRM_IOCTL_MODE_DESTROY_DUMB DRM_IOWR(0xB4, struct drm_mode_destroy_dumb) @@ -105456,7 +105359,7 @@ /** * Device specific ioctls should only be in their respective headers -@@ -757,6 +773,8 @@ struct drm_event_vblank { +@@ -757,6 +773,8 @@ #define DRM_CAP_DUMB_BUFFER 0x1 #define DRM_CAP_VBLANK_HIGH_CRTC 0x2 @@ -105465,11 +105368,11 @@ /* typedef area */ #ifndef __KERNEL__ -diff --git a/include/drm/drmP.h b/include/drm/drmP.h -index bf4b2dc..dd73104 100644 ---- a/include/drm/drmP.h -+++ b/include/drm/drmP.h -@@ -91,6 +91,7 @@ struct drm_device; +Index: linux-3.2.46/include/drm/drmP.h +=================================================================== +--- linux-3.2.46.orig/include/drm/drmP.h 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/include/drm/drmP.h 2013-07-26 19:26:25.000000000 +0000 +@@ -91,6 +91,7 @@ #define DRM_UT_CORE 0x01 #define DRM_UT_DRIVER 0x02 #define DRM_UT_KMS 0x04 @@ -105477,7 +105380,7 @@ /* * Three debug levels are defined. * drm_core, drm_driver, drm_kms -@@ -150,6 +151,7 @@ int drm_err(const char *func, const char *format, ...); +@@ -150,6 +151,7 @@ #define DRIVER_IRQ_VBL2 0x800 #define DRIVER_GEM 0x1000 #define DRIVER_MODESET 0x2000 @@ -105485,7 +105388,7 @@ #define DRIVER_BUS_PCI 0x1 #define DRIVER_BUS_PLATFORM 0x2 -@@ -215,6 +217,11 @@ int drm_err(const char *func, const char *format, ...); +@@ -215,6 +217,11 @@ drm_ut_debug_printk(DRM_UT_KMS, DRM_NAME, \ __func__, fmt, ##args); \ } while (0) @@ -105497,7 +105400,7 @@ #define DRM_LOG(fmt, args...) \ do { \ drm_ut_debug_printk(DRM_UT_CORE, NULL, \ -@@ -238,6 +245,7 @@ int drm_err(const char *func, const char *format, ...); +@@ -238,6 +245,7 @@ #else #define DRM_DEBUG_DRIVER(fmt, args...) do { } while (0) #define DRM_DEBUG_KMS(fmt, args...) do { } while (0) @@ -105505,7 +105408,7 @@ #define DRM_DEBUG(fmt, arg...) do { } while (0) #define DRM_LOG(fmt, arg...) do { } while (0) #define DRM_LOG_KMS(fmt, args...) do { } while (0) -@@ -410,6 +418,12 @@ struct drm_pending_event { +@@ -410,6 +418,12 @@ void (*destroy)(struct drm_pending_event *event); }; @@ -105518,7 +105421,7 @@ /** File private data */ struct drm_file { int authenticated; -@@ -437,6 +451,8 @@ struct drm_file { +@@ -437,6 +451,8 @@ wait_queue_head_t event_wait; struct list_head event_list; int event_space; @@ -105527,7 +105430,7 @@ }; /** Wait queue */ -@@ -652,6 +668,12 @@ struct drm_gem_object { +@@ -652,6 +668,12 @@ uint32_t pending_write_domain; void *driver_private; @@ -105540,7 +105443,7 @@ }; #include "drm_crtc.h" -@@ -820,7 +842,7 @@ struct drm_driver { +@@ -820,7 +842,7 @@ * Specifically, the timestamp in @vblank_time should correspond as * closely as possible to the time when the first video scanline of * the video frame after the end of VBLANK will start scanning out, @@ -105549,7 +105452,7 @@ * @crtc is currently inside VBLANK, this will be a time in the future. * If the @crtc is currently scanning out a frame, this will be the * past start time of the current scanout. This is meant to adhere -@@ -890,6 +912,20 @@ struct drm_driver { +@@ -890,6 +912,20 @@ int (*gem_open_object) (struct drm_gem_object *, struct drm_file *); void (*gem_close_object) (struct drm_gem_object *, struct drm_file *); @@ -105570,7 +105473,7 @@ /* vga arb irq handler */ void (*vgaarb_irq)(struct drm_device *dev, bool state); -@@ -918,7 +954,7 @@ struct drm_driver { +@@ -918,7 +954,7 @@ int dev_priv_size; struct drm_ioctl_desc *ioctls; int num_ioctls; @@ -105579,7 +105482,7 @@ union { struct pci_driver *pci; struct platform_device *platform_device; -@@ -1170,6 +1206,8 @@ struct drm_device { +@@ -1170,6 +1206,8 @@ struct idr object_name_idr; /*@} */ int switch_power_state; @@ -105588,7 +105491,7 @@ }; #define DRM_SWITCH_POWER_ON 0 -@@ -1235,6 +1273,19 @@ static inline int drm_mtrr_del(int handle, unsigned long offset, +@@ -1235,6 +1273,19 @@ } #endif @@ -105608,7 +105511,7 @@ /******************************************************************/ /** \name Internal function definitions */ /*@{*/ -@@ -1264,11 +1315,6 @@ extern unsigned int drm_poll(struct file *filp, struct poll_table_struct *wait); +@@ -1264,11 +1315,6 @@ /* Memory management support (drm_memory.h) */ #include "drm_memory.h" @@ -105620,7 +105523,7 @@ extern void drm_free_agp(DRM_AGP_MEM * handle, int pages); extern int drm_bind_agp(DRM_AGP_MEM * handle, unsigned int start); extern DRM_AGP_MEM *drm_agp_bind_pages(struct drm_device *dev, -@@ -1383,12 +1429,8 @@ extern void drm_core_reclaim_buffers(struct drm_device *dev, +@@ -1383,12 +1429,8 @@ /* IRQ support (drm_irq.h) */ extern int drm_control(struct drm_device *dev, void *data, struct drm_file *file_priv); @@ -105633,7 +105536,7 @@ extern int drm_vblank_init(struct drm_device *dev, int num_crtcs); extern int drm_wait_vblank(struct drm_device *dev, void *data, -@@ -1464,6 +1506,7 @@ extern void drm_master_put(struct drm_master **master); +@@ -1464,6 +1506,7 @@ extern void drm_put_dev(struct drm_device *dev); extern int drm_put_minor(struct drm_minor **minor); @@ -105641,7 +105544,7 @@ extern unsigned int drm_debug; extern unsigned int drm_vblank_offdelay; -@@ -1502,6 +1545,32 @@ extern int drm_vblank_info(struct seq_file *m, void *data); +@@ -1502,6 +1545,32 @@ extern int drm_clients_info(struct seq_file *m, void* data); extern int drm_gem_name_info(struct seq_file *m, void *data); @@ -105674,7 +105577,7 @@ #if DRM_DEBUG_CODE extern int drm_vma_info(struct seq_file *m, void *data); #endif -@@ -1697,5 +1766,13 @@ extern void drm_platform_exit(struct drm_driver *driver, struct platform_device +@@ -1697,5 +1766,13 @@ extern int drm_get_platform_dev(struct platform_device *pdev, struct drm_driver *driver); @@ -105688,10 +105591,10 @@ + #endif /* __KERNEL__ */ #endif -diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h -index 8020798..e250eda 100644 ---- a/include/drm/drm_crtc.h -+++ b/include/drm/drm_crtc.h +Index: linux-3.2.46/include/drm/drm_crtc.h +=================================================================== +--- linux-3.2.46.orig/include/drm/drm_crtc.h 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/include/drm/drm_crtc.h 2013-07-26 19:26:25.000000000 +0000 @@ -29,9 +29,10 @@ #include #include @@ -105704,7 +105607,7 @@ struct drm_device; struct drm_mode_set; struct drm_framebuffer; -@@ -44,6 +45,7 @@ struct drm_framebuffer; +@@ -44,6 +45,7 @@ #define DRM_MODE_OBJECT_PROPERTY 0xb0b0b0b0 #define DRM_MODE_OBJECT_FB 0xfbfbfbfb #define DRM_MODE_OBJECT_BLOB 0xbbbbbbbb @@ -105712,7 +105615,7 @@ struct drm_mode_object { uint32_t id; -@@ -118,9 +120,8 @@ struct drm_display_mode { +@@ -118,9 +120,8 @@ char name[DRM_DISPLAY_MODE_LEN]; @@ -105723,7 +105626,7 @@ /* Proposed mode values */ int clock; /* in kHz */ -@@ -238,13 +239,15 @@ struct drm_framebuffer { +@@ -238,13 +239,15 @@ struct list_head head; struct drm_mode_object base; const struct drm_framebuffer_funcs *funcs; @@ -105740,7 +105643,7 @@ struct list_head filp_head; /* if you are using the helper */ void *helper_private; -@@ -254,7 +257,7 @@ struct drm_property_blob { +@@ -254,7 +257,7 @@ struct drm_mode_object base; struct list_head head; unsigned int length; @@ -105749,7 +105652,7 @@ }; struct drm_property_enum { -@@ -278,6 +281,7 @@ struct drm_crtc; +@@ -278,6 +281,7 @@ struct drm_connector; struct drm_encoder; struct drm_pending_vblank_event; @@ -105757,7 +105660,7 @@ /** * drm_crtc_funcs - control CRTCs for a given device -@@ -341,10 +345,21 @@ struct drm_crtc_funcs { +@@ -341,10 +345,21 @@ /** * drm_crtc - central CRTC control structure @@ -105779,7 +105682,7 @@ * * Each CRTC may have one or more connectors associated with it. This structure * allows the CRTC to be controlled. -@@ -423,6 +438,13 @@ struct drm_connector_funcs { +@@ -423,6 +438,13 @@ void (*force)(struct drm_connector *connector); }; @@ -105793,7 +105696,7 @@ struct drm_encoder_funcs { void (*reset)(struct drm_encoder *encoder); void (*destroy)(struct drm_encoder *encoder); -@@ -431,10 +453,22 @@ struct drm_encoder_funcs { +@@ -431,10 +453,22 @@ #define DRM_CONNECTOR_MAX_UMODES 16 #define DRM_CONNECTOR_MAX_PROPERTY 16 #define DRM_CONNECTOR_LEN 32 @@ -105817,7 +105720,7 @@ */ struct drm_encoder { struct drm_device *dev; -@@ -470,14 +504,37 @@ enum drm_connector_force { +@@ -470,14 +504,37 @@ /** * drm_connector - central DRM connector control structure @@ -105860,7 +105763,7 @@ * * Each connector may be connected to one or more CRTCs, or may be clonable by * another connector if they can share a CRTC. Each connector also has a specific -@@ -498,7 +555,6 @@ struct drm_connector { +@@ -498,7 +555,6 @@ bool doublescan_allowed; struct list_head modes; /* list of modes on this connector */ @@ -105868,7 +105771,7 @@ enum drm_connector_status status; /* these are modes added by probing with DDC or the BIOS */ -@@ -522,7 +578,6 @@ struct drm_connector { +@@ -522,7 +578,6 @@ /* forced on connector */ enum drm_connector_force force; uint32_t encoder_ids[DRM_CONNECTOR_MAX_ENCODER]; @@ -105876,7 +105779,7 @@ struct drm_encoder *encoder; /* currently active encoder */ /* EDID bits */ -@@ -536,7 +591,71 @@ struct drm_connector { +@@ -536,7 +591,71 @@ }; /** @@ -105949,7 +105852,7 @@ * * Represents a single crtc the connectors that it drives with what mode * and from which framebuffer it scans out from. -@@ -558,13 +677,33 @@ struct drm_mode_set { +@@ -558,13 +677,33 @@ }; /** @@ -105985,7 +105888,7 @@ struct drm_mode_group { uint32_t num_crtcs; uint32_t num_encoders; -@@ -576,7 +715,30 @@ struct drm_mode_group { +@@ -576,7 +715,30 @@ /** * drm_mode_config - Mode configuration control structure @@ -106016,7 +105919,7 @@ */ struct drm_mode_config { struct mutex mutex; /* protects configuration (mode lists etc.) */ -@@ -589,6 +751,8 @@ struct drm_mode_config { +@@ -589,6 +751,8 @@ struct list_head connector_list; int num_encoder; struct list_head encoder_list; @@ -106025,7 +105928,7 @@ int num_crtc; struct list_head crtc_list; -@@ -632,6 +796,9 @@ struct drm_mode_config { +@@ -632,6 +796,9 @@ struct drm_property *scaling_mode_property; struct drm_property *dithering_mode_property; struct drm_property *dirty_info_property; @@ -106035,7 +105938,7 @@ }; #define obj_to_crtc(x) container_of(x, struct drm_crtc, base) -@@ -641,24 +808,39 @@ struct drm_mode_config { +@@ -641,24 +808,39 @@ #define obj_to_fb(x) container_of(x, struct drm_framebuffer, base) #define obj_to_property(x) container_of(x, struct drm_property, base) #define obj_to_blob(x) container_of(x, struct drm_property_blob, base) @@ -106064,14 +105967,13 @@ + int connector_type); extern void drm_connector_cleanup(struct drm_connector *connector); -- ++/* helper to unplug all connectors from sysfs for device */ ++extern void drm_connector_unplug_all(struct drm_device *dev); + -extern void drm_encoder_init(struct drm_device *dev, - struct drm_encoder *encoder, - const struct drm_encoder_funcs *funcs, - int encoder_type); -+/* helper to unplug all connectors from sysfs for device */ -+extern void drm_connector_unplug_all(struct drm_device *dev); -+ +extern int drm_encoder_init(struct drm_device *dev, + struct drm_encoder *encoder, + const struct drm_encoder_funcs *funcs, @@ -106087,7 +105989,7 @@ extern void drm_encoder_cleanup(struct drm_encoder *encoder); -@@ -675,6 +857,7 @@ extern struct edid *drm_get_edid(struct drm_connector *connector, +@@ -675,6 +857,7 @@ extern int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid); extern void drm_mode_probed_add(struct drm_connector *connector, struct drm_display_mode *mode); extern void drm_mode_remove(struct drm_connector *connector, struct drm_display_mode *mode); @@ -106095,7 +105997,7 @@ extern struct drm_display_mode *drm_mode_duplicate(struct drm_device *dev, const struct drm_display_mode *mode); extern void drm_mode_debug_printmodeline(struct drm_display_mode *mode); -@@ -689,7 +872,7 @@ extern int drm_mode_height(struct drm_display_mode *mode); +@@ -689,7 +872,7 @@ /* for us by fb module */ extern int drm_mode_attachmode_crtc(struct drm_device *dev, struct drm_crtc *crtc, @@ -106104,7 +106006,7 @@ extern int drm_mode_detachmode_crtc(struct drm_device *dev, struct drm_display_mode *mode); extern struct drm_display_mode *drm_mode_create(struct drm_device *dev); -@@ -731,6 +914,13 @@ extern int drm_connector_attach_property(struct drm_connector *connector, +@@ -731,6 +914,13 @@ struct drm_property *property, uint64_t init_val); extern struct drm_property *drm_property_create(struct drm_device *dev, int flags, const char *name, int num_values); @@ -106118,7 +106020,7 @@ extern void drm_property_destroy(struct drm_device *dev, struct drm_property *property); extern int drm_property_add_enum(struct drm_property *property, int index, uint64_t value, const char *name); -@@ -746,24 +936,32 @@ extern int drm_mode_connector_attach_encoder(struct drm_connector *connector, +@@ -746,24 +936,32 @@ struct drm_encoder *encoder); extern void drm_mode_connector_detach_encoder(struct drm_connector *connector, struct drm_encoder *encoder); @@ -106153,7 +106055,7 @@ extern int drm_mode_rmfb(struct drm_device *dev, void *data, struct drm_file *file_priv); extern int drm_mode_getfb(struct drm_device *dev, -@@ -814,6 +1012,7 @@ extern int drm_add_modes_noedid(struct drm_connector *connector, +@@ -814,6 +1012,7 @@ int hdisplay, int vdisplay); extern int drm_edid_header_is_valid(const u8 *raw_edid); @@ -106161,7 +106063,7 @@ extern bool drm_edid_is_valid(struct edid *edid); struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev, int hsize, int vsize, int fresh); -@@ -824,4 +1023,7 @@ extern int drm_mode_mmap_dumb_ioctl(struct drm_device *dev, +@@ -824,4 +1023,7 @@ void *data, struct drm_file *file_priv); extern int drm_mode_destroy_dumb_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv); @@ -106169,11 +106071,11 @@ +extern void drm_fb_get_bpp_depth(uint32_t format, unsigned int *depth, + int *bpp); #endif /* __DRM_CRTC_H__ */ -diff --git a/include/drm/drm_crtc_helper.h b/include/drm/drm_crtc_helper.h -index 73b0712..37515d1 100644 ---- a/include/drm/drm_crtc_helper.h -+++ b/include/drm/drm_crtc_helper.h -@@ -117,7 +117,7 @@ extern bool drm_helper_encoder_in_use(struct drm_encoder *encoder); +Index: linux-3.2.46/include/drm/drm_crtc_helper.h +=================================================================== +--- linux-3.2.46.orig/include/drm/drm_crtc_helper.h 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/include/drm/drm_crtc_helper.h 2013-07-26 19:26:25.000000000 +0000 +@@ -117,7 +117,7 @@ extern void drm_helper_connector_dpms(struct drm_connector *connector, int mode); extern int drm_helper_mode_fill_fb_struct(struct drm_framebuffer *fb, @@ -106182,7 +106084,7 @@ static inline void drm_crtc_helper_add(struct drm_crtc *crtc, const struct drm_crtc_helper_funcs *funcs) -@@ -144,4 +144,7 @@ extern void drm_helper_hpd_irq_event(struct drm_device *dev); +@@ -144,4 +144,7 @@ extern void drm_kms_helper_poll_disable(struct drm_device *dev); extern void drm_kms_helper_poll_enable(struct drm_device *dev); @@ -106190,22 +106092,22 @@ +extern int drm_format_num_planes(uint32_t format); + #endif -diff --git a/include/drm/drm_edid.h b/include/drm/drm_edid.h -index 74ce916..bcb9a66 100644 ---- a/include/drm/drm_edid.h -+++ b/include/drm/drm_edid.h -@@ -238,5 +238,6 @@ int drm_av_sync_delay(struct drm_connector *connector, +Index: linux-3.2.46/include/drm/drm_edid.h +=================================================================== +--- linux-3.2.46.orig/include/drm/drm_edid.h 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/include/drm/drm_edid.h 2013-07-26 19:26:25.000000000 +0000 +@@ -238,5 +238,6 @@ struct drm_display_mode *mode); struct drm_connector *drm_select_eld(struct drm_encoder *encoder, struct drm_display_mode *mode); +int drm_load_edid_firmware(struct drm_connector *connector); #endif /* __DRM_EDID_H__ */ -diff --git a/include/drm/drm_fb_helper.h b/include/drm/drm_fb_helper.h -index 6e3076a..5120b01 100644 ---- a/include/drm/drm_fb_helper.h -+++ b/include/drm/drm_fb_helper.h -@@ -35,7 +35,6 @@ struct drm_fb_helper; +Index: linux-3.2.46/include/drm/drm_fb_helper.h +=================================================================== +--- linux-3.2.46.orig/include/drm/drm_fb_helper.h 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/include/drm/drm_fb_helper.h 2013-07-26 19:26:25.000000000 +0000 +@@ -35,7 +35,6 @@ #include struct drm_fb_helper_crtc { @@ -106213,7 +106115,7 @@ struct drm_mode_set mode_set; struct drm_display_mode *desired_mode; }; -@@ -74,7 +73,6 @@ struct drm_fb_helper { +@@ -74,7 +73,6 @@ int connector_count; struct drm_fb_helper_connector **connector_info; struct drm_fb_helper_funcs *funcs; @@ -106221,11 +106123,10 @@ struct fb_info *fbdev; u32 pseudo_palette[17]; struct list_head kernel_fb_list; -diff --git a/include/drm/drm_fourcc.h b/include/drm/drm_fourcc.h -new file mode 100644 -index 0000000..bdf0152 ---- /dev/null -+++ b/include/drm/drm_fourcc.h +Index: linux-3.2.46/include/drm/drm_fourcc.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/include/drm/drm_fourcc.h 2013-07-26 19:26:25.000000000 +0000 @@ -0,0 +1,137 @@ +/* + * Copyright 2011 Intel Corporation @@ -106364,10 +106265,10 @@ +#define DRM_FORMAT_YUV420M fourcc_code('Y', 'M', '1', '2') /* 2x2 subsampled Cb (1) and Cr (2) planes */ + +#endif /* DRM_FOURCC_H */ -diff --git a/include/drm/drm_mode.h b/include/drm/drm_mode.h -index 7639f18..9242310 100644 ---- a/include/drm/drm_mode.h -+++ b/include/drm/drm_mode.h +Index: linux-3.2.46/include/drm/drm_mode.h +=================================================================== +--- linux-3.2.46.orig/include/drm/drm_mode.h 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/include/drm/drm_mode.h 2013-07-26 19:26:25.000000000 +0000 @@ -27,6 +27,8 @@ #ifndef _DRM_MODE_H #define _DRM_MODE_H @@ -106377,7 +106278,7 @@ #define DRM_DISPLAY_INFO_LEN 32 #define DRM_CONNECTOR_NAME_LEN 32 #define DRM_DISPLAY_MODE_LEN 32 -@@ -120,11 +122,48 @@ struct drm_mode_crtc { +@@ -120,11 +122,48 @@ struct drm_mode_modeinfo mode; }; @@ -106431,7 +106332,7 @@ #define DRM_MODE_ENCODER_VIRTUAL 5 struct drm_mode_get_encoder { -@@ -231,6 +270,33 @@ struct drm_mode_fb_cmd { +@@ -231,6 +270,33 @@ __u32 handle; }; @@ -106465,10 +106366,10 @@ #define DRM_MODE_FB_DIRTY_ANNOTATE_COPY 0x01 #define DRM_MODE_FB_DIRTY_ANNOTATE_FILL 0x02 #define DRM_MODE_FB_DIRTY_FLAGS 0x03 -diff --git a/include/drm/drm_pciids.h b/include/drm/drm_pciids.h -index def807c..1a13caa 100644 ---- a/include/drm/drm_pciids.h -+++ b/include/drm/drm_pciids.h +Index: linux-3.2.46/include/drm/drm_pciids.h +=================================================================== +--- linux-3.2.46.orig/include/drm/drm_pciids.h 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/include/drm/drm_pciids.h 2013-07-26 19:26:25.000000000 +0000 @@ -204,11 +204,60 @@ {0x1002, 0x6778, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CAICOS|RADEON_NEW_MEMMAP}, \ {0x1002, 0x6779, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CAICOS|RADEON_NEW_MEMMAP}, \ @@ -106574,11 +106475,10 @@ {0, 0, 0} #define r128_PCI_IDS \ -diff --git a/include/drm/drm_sman.h b/include/drm/drm_sman.h -deleted file mode 100644 -index 08ecf83..0000000 ---- a/include/drm/drm_sman.h -+++ /dev/null +Index: linux-3.2.46/include/drm/drm_sman.h +=================================================================== +--- linux-3.2.46.orig/include/drm/drm_sman.h 2013-07-26 18:53:34.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 @@ -1,176 +0,0 @@ -/************************************************************************** - * @@ -106756,11 +106656,11 @@ -extern void drm_sman_cleanup(struct drm_sman * sman); - -#endif -diff --git a/include/drm/exynos_drm.h b/include/drm/exynos_drm.h -index 1205043..e478de4 100644 ---- a/include/drm/exynos_drm.h -+++ b/include/drm/exynos_drm.h -@@ -74,9 +74,38 @@ struct drm_exynos_gem_mmap { +Index: linux-3.2.46/include/drm/exynos_drm.h +=================================================================== +--- linux-3.2.46.orig/include/drm/exynos_drm.h 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/include/drm/exynos_drm.h 2013-07-26 19:26:25.000000000 +0000 +@@ -74,9 +74,38 @@ uint64_t mapped; }; @@ -106799,7 +106699,7 @@ #define DRM_IOCTL_EXYNOS_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + \ DRM_EXYNOS_GEM_CREATE, struct drm_exynos_gem_create) -@@ -87,19 +116,70 @@ struct drm_exynos_gem_mmap { +@@ -87,19 +116,70 @@ #define DRM_IOCTL_EXYNOS_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + \ DRM_EXYNOS_GEM_MMAP, struct drm_exynos_gem_mmap) @@ -106873,11 +106773,10 @@ + +#endif /* __KERNEL__ */ +#endif /* _EXYNOS_DRM_H_ */ -diff --git a/include/drm/gma_drm.h b/include/drm/gma_drm.h -new file mode 100644 -index 0000000..884613e ---- /dev/null -+++ b/include/drm/gma_drm.h +Index: linux-3.2.46/include/drm/gma_drm.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/include/drm/gma_drm.h 2013-07-26 19:26:25.000000000 +0000 @@ -0,0 +1,91 @@ +/************************************************************************** + * Copyright (c) 2007-2011, Intel Corporation. @@ -106970,11 +106869,11 @@ + + +#endif -diff --git a/include/drm/i915_drm.h b/include/drm/i915_drm.h -index 28c0d11..da929bb 100644 ---- a/include/drm/i915_drm.h -+++ b/include/drm/i915_drm.h -@@ -198,6 +198,8 @@ typedef struct _drm_i915_sarea { +Index: linux-3.2.46/include/drm/i915_drm.h +=================================================================== +--- linux-3.2.46.orig/include/drm/i915_drm.h 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/include/drm/i915_drm.h 2013-07-26 19:26:25.000000000 +0000 +@@ -198,6 +198,8 @@ #define DRM_I915_OVERLAY_PUT_IMAGE 0x27 #define DRM_I915_OVERLAY_ATTRS 0x28 #define DRM_I915_GEM_EXECBUFFER2 0x29 @@ -106983,7 +106882,7 @@ #define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t) #define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH) -@@ -239,6 +241,8 @@ typedef struct _drm_i915_sarea { +@@ -239,6 +241,8 @@ #define DRM_IOCTL_I915_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MADVISE, struct drm_i915_gem_madvise) #define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE DRM_IOW(DRM_COMMAND_BASE + DRM_I915_OVERLAY_PUT_IMAGE, struct drm_intel_overlay_put_image) #define DRM_IOCTL_I915_OVERLAY_ATTRS DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_OVERLAY_ATTRS, struct drm_intel_overlay_attrs) @@ -106992,7 +106891,7 @@ /* Allow drivers to submit batchbuffers directly to hardware, relying * on the security mechanisms provided by hardware. -@@ -291,6 +295,8 @@ typedef struct drm_i915_irq_wait { +@@ -291,6 +295,8 @@ #define I915_PARAM_HAS_COHERENT_RINGS 13 #define I915_PARAM_HAS_EXEC_CONSTANTS 14 #define I915_PARAM_HAS_RELAXED_DELTA 15 @@ -107001,7 +106900,7 @@ typedef struct drm_i915_getparam { int param; -@@ -653,6 +659,9 @@ struct drm_i915_gem_execbuffer2 { +@@ -653,6 +659,9 @@ __u64 rsvd2; }; @@ -107011,7 +106910,7 @@ struct drm_i915_gem_pin { /** Handle of the buffer to be pinned. */ __u32 handle; -@@ -844,4 +853,36 @@ struct drm_intel_overlay_attrs { +@@ -844,4 +853,36 @@ __u32 gamma5; }; @@ -107048,11 +106947,11 @@ +}; + #endif /* _I915_DRM_H_ */ -diff --git a/include/drm/intel-gtt.h b/include/drm/intel-gtt.h -index b174620..923afb5 100644 ---- a/include/drm/intel-gtt.h -+++ b/include/drm/intel-gtt.h -@@ -15,6 +15,10 @@ const struct intel_gtt { +Index: linux-3.2.46/include/drm/intel-gtt.h +=================================================================== +--- linux-3.2.46.orig/include/drm/intel-gtt.h 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/include/drm/intel-gtt.h 2013-07-26 19:26:25.000000000 +0000 +@@ -15,6 +15,10 @@ unsigned int needs_dmar : 1; /* Whether we idle the gpu before mapping/unmapping */ unsigned int do_idle_maps : 1; @@ -107063,7 +106962,7 @@ } *intel_gtt_get(void); void intel_gtt_chipset_flush(void); -@@ -40,4 +44,8 @@ void intel_gtt_insert_pages(unsigned int first_entry, unsigned int num_entries, +@@ -40,4 +44,8 @@ /* flag for GFDT type */ #define AGP_USER_CACHED_MEMORY_GFDT (1 << 3) @@ -107072,11 +106971,11 @@ +#endif + #endif -diff --git a/include/drm/radeon_drm.h b/include/drm/radeon_drm.h -index be94be6..7c491b4 100644 ---- a/include/drm/radeon_drm.h -+++ b/include/drm/radeon_drm.h -@@ -509,6 +509,7 @@ typedef struct { +Index: linux-3.2.46/include/drm/radeon_drm.h +=================================================================== +--- linux-3.2.46.orig/include/drm/radeon_drm.h 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/include/drm/radeon_drm.h 2013-07-26 19:26:25.000000000 +0000 +@@ -509,6 +509,7 @@ #define DRM_RADEON_GEM_SET_TILING 0x28 #define DRM_RADEON_GEM_GET_TILING 0x29 #define DRM_RADEON_GEM_BUSY 0x2a @@ -107084,7 +106983,7 @@ #define DRM_IOCTL_RADEON_CP_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_INIT, drm_radeon_init_t) #define DRM_IOCTL_RADEON_CP_START DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_START) -@@ -550,6 +551,7 @@ typedef struct { +@@ -550,6 +551,7 @@ #define DRM_IOCTL_RADEON_GEM_SET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_SET_TILING, struct drm_radeon_gem_set_tiling) #define DRM_IOCTL_RADEON_GEM_GET_TILING DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_GET_TILING, struct drm_radeon_gem_get_tiling) #define DRM_IOCTL_RADEON_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_BUSY, struct drm_radeon_gem_busy) @@ -107092,7 +106991,7 @@ typedef struct drm_radeon_init { enum { -@@ -802,13 +804,23 @@ struct drm_radeon_gem_create { +@@ -802,13 +804,23 @@ uint32_t flags; }; @@ -107123,7 +107022,7 @@ struct drm_radeon_gem_set_tiling { uint32_t handle; -@@ -872,12 +884,40 @@ struct drm_radeon_gem_pwrite { +@@ -872,12 +884,40 @@ uint64_t data_ptr; }; @@ -107164,7 +107063,7 @@ struct drm_radeon_cs_chunk { uint32_t chunk_id; -@@ -885,6 +925,9 @@ struct drm_radeon_cs_chunk { +@@ -885,6 +925,9 @@ uint64_t chunk_data; }; @@ -107174,7 +107073,7 @@ struct drm_radeon_cs_reloc { uint32_t handle; uint32_t read_domains; -@@ -916,6 +959,12 @@ struct drm_radeon_cs { +@@ -916,6 +959,12 @@ #define RADEON_INFO_NUM_TILE_PIPES 0x0b /* tile pipes for r600+ */ #define RADEON_INFO_FUSION_GART_WORKING 0x0c /* fusion writes to GTT were broken before this */ #define RADEON_INFO_BACKEND_MAP 0x0d /* pipe to backend map, needed by mesa */ @@ -107187,11 +107086,11 @@ struct drm_radeon_info { uint32_t request; -diff --git a/include/drm/sis_drm.h b/include/drm/sis_drm.h -index 30f7b38..035b804 100644 ---- a/include/drm/sis_drm.h -+++ b/include/drm/sis_drm.h -@@ -64,4 +64,8 @@ typedef struct { +Index: linux-3.2.46/include/drm/sis_drm.h +=================================================================== +--- linux-3.2.46.orig/include/drm/sis_drm.h 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/include/drm/sis_drm.h 2013-07-26 19:26:25.000000000 +0000 +@@ -64,4 +64,8 @@ unsigned int offset, size; } drm_sis_fb_t; @@ -107200,11 +107099,11 @@ +}; + #endif /* __SIS_DRM_H__ */ -diff --git a/include/drm/ttm/ttm_bo_api.h b/include/drm/ttm/ttm_bo_api.h -index 42e3469..974c8f8 100644 ---- a/include/drm/ttm/ttm_bo_api.h -+++ b/include/drm/ttm/ttm_bo_api.h -@@ -122,17 +122,12 @@ struct ttm_mem_reg { +Index: linux-3.2.46/include/drm/ttm/ttm_bo_api.h +=================================================================== +--- linux-3.2.46.orig/include/drm/ttm/ttm_bo_api.h 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/include/drm/ttm/ttm_bo_api.h 2013-07-26 19:26:25.000000000 +0000 +@@ -122,17 +122,12 @@ * be mmapped by user space. Each of these bos occupy a slot in the * device address space, that can be used for normal vm operations. * @@ -107222,7 +107121,7 @@ ttm_bo_type_kernel }; -@@ -434,9 +429,9 @@ extern void ttm_bo_unlock_delayed_workqueue(struct ttm_bo_device *bdev, +@@ -434,9 +429,9 @@ * -EBUSY if the buffer is busy and no_wait is true. * -ERESTARTSYS if interrupted by a signal. */ @@ -107233,7 +107132,7 @@ /** * ttm_bo_synccpu_write_release: * -@@ -447,6 +442,22 @@ ttm_bo_synccpu_write_grab(struct ttm_buffer_object *bo, bool no_wait); +@@ -447,6 +442,22 @@ extern void ttm_bo_synccpu_write_release(struct ttm_buffer_object *bo); /** @@ -107256,7 +107155,7 @@ * ttm_bo_init * * @bdev: Pointer to a ttm_bo_device struct. -@@ -493,6 +504,7 @@ extern int ttm_bo_init(struct ttm_bo_device *bdev, +@@ -493,6 +504,7 @@ struct file *persistent_swap_storage, size_t acc_size, void (*destroy) (struct ttm_buffer_object *)); @@ -107264,11 +107163,11 @@ /** * ttm_bo_synccpu_object_init * -diff --git a/include/drm/ttm/ttm_bo_driver.h b/include/drm/ttm/ttm_bo_driver.h -index 94eb143..d43e892 100644 ---- a/include/drm/ttm/ttm_bo_driver.h -+++ b/include/drm/ttm/ttm_bo_driver.h -@@ -43,36 +43,9 @@ struct ttm_backend; +Index: linux-3.2.46/include/drm/ttm/ttm_bo_driver.h +=================================================================== +--- linux-3.2.46.orig/include/drm/ttm/ttm_bo_driver.h 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/include/drm/ttm/ttm_bo_driver.h 2013-07-26 19:26:25.000000000 +0000 +@@ -43,36 +43,9 @@ struct ttm_backend_func { /** @@ -107306,7 +107205,7 @@ * @bo_mem: Pointer to a struct ttm_mem_reg describing the * memory type and location for binding. * -@@ -80,46 +53,29 @@ struct ttm_backend_func { +@@ -80,46 +53,29 @@ * indicated by @bo_mem. This function should be able to handle * differences between aperture and system page sizes. */ @@ -107360,7 +107259,7 @@ #define TTM_PAGE_FLAG_WRITE (1 << 3) #define TTM_PAGE_FLAG_SWAPPED (1 << 4) #define TTM_PAGE_FLAG_PERSISTENT_SWAP (1 << 5) -@@ -135,23 +91,18 @@ enum ttm_caching_state { +@@ -135,23 +91,18 @@ /** * struct ttm_tt * @@ -107387,7 +107286,7 @@ * * This is a structure holding the pages, caching- and aperture binding * status for a buffer object that isn't backed by fixed (VRAM / AGP) -@@ -159,16 +110,14 @@ enum ttm_caching_state { +@@ -159,16 +110,14 @@ */ struct ttm_tt { @@ -107406,7 +107305,7 @@ struct file *swap_storage; enum ttm_caching_state caching_state; enum { -@@ -176,7 +125,23 @@ struct ttm_tt { +@@ -176,7 +125,23 @@ tt_unbound, tt_unpopulated, } state; @@ -107430,7 +107329,7 @@ }; #define TTM_MEMTYPE_FLAG_FIXED (1 << 0) /* Fixed (on-card) PCI memory */ -@@ -351,15 +316,42 @@ struct ttm_mem_type_manager { +@@ -351,15 +316,42 @@ struct ttm_bo_driver { /** @@ -107478,7 +107377,7 @@ /** * struct ttm_bo_driver member invalidate_caches -@@ -477,9 +469,6 @@ struct ttm_bo_global_ref { +@@ -477,9 +469,6 @@ * @dummy_read_page: Pointer to a dummy page used for mapping requests * of unpopulated pages. * @shrink: A shrink callback object used for buffer object swap. @@ -107488,7 +107387,7 @@ * @device_list_mutex: Mutex protecting the device list. * This mutex is held while traversing the device list for pm options. * @lru_lock: Spinlock protecting the bo subsystem lru lists. -@@ -497,8 +486,6 @@ struct ttm_bo_global { +@@ -497,8 +486,6 @@ struct ttm_mem_global *mem_glob; struct page *dummy_read_page; struct ttm_mem_shrink shrink; @@ -107497,7 +107396,7 @@ struct mutex device_list_mutex; spinlock_t lru_lock; -@@ -600,8 +587,9 @@ ttm_flag_masked(uint32_t *old, uint32_t new, uint32_t mask) +@@ -600,8 +587,9 @@ } /** @@ -107508,7 +107407,7 @@ * @bdev: pointer to a struct ttm_bo_device: * @size: Size of the data needed backing. * @page_flags: Page flags as identified by TTM_PAGE_FLAG_XX flags. -@@ -612,28 +600,22 @@ ttm_flag_masked(uint32_t *old, uint32_t new, uint32_t mask) +@@ -612,28 +600,22 @@ * Returns: * NULL: Out of memory. */ @@ -107548,7 +107447,7 @@ /** * ttm_ttm_bind: -@@ -646,20 +628,11 @@ extern int ttm_tt_set_user(struct ttm_tt *ttm, +@@ -646,20 +628,11 @@ extern int ttm_tt_bind(struct ttm_tt *ttm, struct ttm_mem_reg *bo_mem); /** @@ -107570,7 +107469,7 @@ */ extern void ttm_tt_destroy(struct ttm_tt *ttm); -@@ -673,19 +646,13 @@ extern void ttm_tt_destroy(struct ttm_tt *ttm); +@@ -673,19 +646,13 @@ extern void ttm_tt_unbind(struct ttm_tt *ttm); /** @@ -107593,7 +107492,7 @@ /** * ttm_tt_cache_flush: -@@ -1046,17 +1013,25 @@ extern const struct ttm_mem_type_manager_func ttm_bo_manager_func; +@@ -1046,17 +1013,25 @@ #include /** @@ -107622,10 +107521,10 @@ #endif #endif -diff --git a/include/drm/ttm/ttm_memory.h b/include/drm/ttm/ttm_memory.h -index 26c1f78..d6d1da4 100644 ---- a/include/drm/ttm/ttm_memory.h -+++ b/include/drm/ttm/ttm_memory.h +Index: linux-3.2.46/include/drm/ttm/ttm_memory.h +=================================================================== +--- linux-3.2.46.orig/include/drm/ttm/ttm_memory.h 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/include/drm/ttm/ttm_memory.h 2013-07-26 19:26:25.000000000 +0000 @@ -30,6 +30,7 @@ #include @@ -107634,10 +107533,10 @@ #include #include #include -diff --git a/include/drm/ttm/ttm_page_alloc.h b/include/drm/ttm/ttm_page_alloc.h -index 129de12..5fe2740 100644 ---- a/include/drm/ttm/ttm_page_alloc.h -+++ b/include/drm/ttm/ttm_page_alloc.h +Index: linux-3.2.46/include/drm/ttm/ttm_page_alloc.h +=================================================================== +--- linux-3.2.46.orig/include/drm/ttm/ttm_page_alloc.h 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/include/drm/ttm/ttm_page_alloc.h 2013-07-26 19:26:25.000000000 +0000 @@ -30,45 +30,70 @@ #include "ttm_memory.h" @@ -107661,20 +107560,19 @@ - * @cstate: ttm caching state for the page. - * @count: number of pages to allocate. - * @dma_address: The DMA (bus) address of pages (if TTM_PAGE_FLAG_DMA32 set). -+ * Add backing pages to all of @ttm - */ +- */ -int ttm_get_pages(struct list_head *pages, - int flags, - enum ttm_caching_state cstate, - unsigned count, - dma_addr_t *dma_address); ++ * Add backing pages to all of @ttm ++ */ +extern int ttm_pool_populate(struct ttm_tt *ttm); + /** - * Put linked list of pages to pool. + * ttm_pool_unpopulate: -+ * -+ * @ttm: The struct ttm_tt which to free backing pages. * - * @pages: list of pages to free. - * @page_count: number of pages in the list. Zero can be passed for unknown @@ -107682,13 +107580,16 @@ - * @flags: ttm flags for page allocation. - * @cstate: ttm caching state. - * @dma_address: The DMA (bus) address of pages (if TTM_PAGE_FLAG_DMA32 set). -+ * Free all pages of @ttm - */ +- */ -void ttm_put_pages(struct list_head *pages, - unsigned page_count, - int flags, - enum ttm_caching_state cstate, - dma_addr_t *dma_address); ++ * @ttm: The struct ttm_tt which to free backing pages. ++ * ++ * Free all pages of @ttm ++ */ +extern void ttm_pool_unpopulate(struct ttm_tt *ttm); + +/** @@ -107735,11 +107636,11 @@ +#endif + #endif -diff --git a/include/drm/via_drm.h b/include/drm/via_drm.h -index fd11a5b..79b3b6e 100644 ---- a/include/drm/via_drm.h -+++ b/include/drm/via_drm.h -@@ -274,4 +274,8 @@ typedef struct drm_via_dmablit { +Index: linux-3.2.46/include/drm/via_drm.h +=================================================================== +--- linux-3.2.46.orig/include/drm/via_drm.h 2013-07-26 18:53:34.000000000 +0000 ++++ linux-3.2.46/include/drm/via_drm.h 2013-07-26 19:26:25.000000000 +0000 +@@ -274,4 +274,8 @@ drm_via_blitsync_t sync; } drm_via_dmablit_t; diff -Nru linux-3.2.46/debian/patches/features/all/drm/drm-i915-revert-switch-to-simple_open.patch linux-3.2.46/debian/patches/features/all/drm/drm-i915-revert-switch-to-simple_open.patch --- linux-3.2.46/debian/patches/features/all/drm/drm-i915-revert-switch-to-simple_open.patch 2013-02-24 03:52:31.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/drm/drm-i915-revert-switch-to-simple_open.patch 2013-07-26 19:26:56.000000000 +0000 @@ -8,11 +8,11 @@ drivers/gpu/drm/i915/i915_debugfs.c | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) -diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c -index e6162a1..8747da0 100644 ---- a/drivers/gpu/drm/i915/i915_debugfs.c -+++ b/drivers/gpu/drm/i915/i915_debugfs.c -@@ -1505,6 +1505,14 @@ static int i915_ppgtt_info(struct seq_file *m, void *data) +Index: linux-3.2.46/drivers/gpu/drm/i915/i915_debugfs.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/i915/i915_debugfs.c 2013-07-26 19:26:22.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/i915/i915_debugfs.c 2013-07-26 19:26:55.000000000 +0000 +@@ -1505,6 +1505,14 @@ return 0; } @@ -27,7 +27,7 @@ static ssize_t i915_wedged_read(struct file *filp, char __user *ubuf, -@@ -1555,7 +1563,7 @@ i915_wedged_write(struct file *filp, +@@ -1555,7 +1563,7 @@ static const struct file_operations i915_wedged_fops = { .owner = THIS_MODULE, @@ -36,7 +36,7 @@ .read = i915_wedged_read, .write = i915_wedged_write, .llseek = default_llseek, -@@ -1617,7 +1625,7 @@ i915_max_freq_write(struct file *filp, +@@ -1617,7 +1625,7 @@ static const struct file_operations i915_max_freq_fops = { .owner = THIS_MODULE, @@ -45,7 +45,7 @@ .read = i915_max_freq_read, .write = i915_max_freq_write, .llseek = default_llseek, -@@ -1688,7 +1696,7 @@ i915_cache_sharing_write(struct file *filp, +@@ -1688,7 +1696,7 @@ static const struct file_operations i915_cache_sharing_fops = { .owner = THIS_MODULE, @@ -54,6 +54,3 @@ .read = i915_cache_sharing_read, .write = i915_cache_sharing_write, .llseek = default_llseek, --- -1.7.10.4 - diff -Nru linux-3.2.46/debian/patches/features/all/drm/drm-revert-part-of-2c9ede55ecec58099b72e4bb8eab719f3.patch linux-3.2.46/debian/patches/features/all/drm/drm-revert-part-of-2c9ede55ecec58099b72e4bb8eab719f3.patch --- linux-3.2.46/debian/patches/features/all/drm/drm-revert-part-of-2c9ede55ecec58099b72e4bb8eab719f3.patch 2013-02-24 03:52:31.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/drm/drm-revert-part-of-2c9ede55ecec58099b72e4bb8eab719f3.patch 2013-07-26 19:26:59.000000000 +0000 @@ -8,11 +8,11 @@ drivers/gpu/drm/drm_sysfs.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -diff --git a/drivers/gpu/drm/drm_sysfs.c b/drivers/gpu/drm/drm_sysfs.c -index 5a7bd51..e7101be 100644 ---- a/drivers/gpu/drm/drm_sysfs.c -+++ b/drivers/gpu/drm/drm_sysfs.c -@@ -72,7 +72,7 @@ static int drm_class_resume(struct device *dev) +Index: linux-3.2.46/drivers/gpu/drm/drm_sysfs.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/drm_sysfs.c 2013-07-26 19:26:21.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/drm_sysfs.c 2013-07-26 19:26:58.000000000 +0000 +@@ -72,7 +72,7 @@ return 0; } @@ -21,6 +21,3 @@ { return kasprintf(GFP_KERNEL, "dri/%s", dev_name(dev)); } --- -1.7.10.4 - diff -Nru linux-3.2.46/debian/patches/features/all/drm/i2c-export-bit-banging-algo-functions.patch linux-3.2.46/debian/patches/features/all/drm/i2c-export-bit-banging-algo-functions.patch --- linux-3.2.46/debian/patches/features/all/drm/i2c-export-bit-banging-algo-functions.patch 2013-02-24 03:52:31.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/drm/i2c-export-bit-banging-algo-functions.patch 2013-07-26 19:26:18.000000000 +0000 @@ -31,11 +31,11 @@ include/linux/i2c-algo-bit.h | 1 + 2 files changed, 3 insertions(+), 1 deletion(-) -diff --git a/drivers/i2c/algos/i2c-algo-bit.c b/drivers/i2c/algos/i2c-algo-bit.c -index 24f94f4..acba1c6 100644 ---- a/drivers/i2c/algos/i2c-algo-bit.c -+++ b/drivers/i2c/algos/i2c-algo-bit.c -@@ -616,10 +616,11 @@ static u32 bit_func(struct i2c_adapter *adap) +Index: linux-3.2.46/drivers/i2c/algos/i2c-algo-bit.c +=================================================================== +--- linux-3.2.46.orig/drivers/i2c/algos/i2c-algo-bit.c 2013-07-26 18:53:36.000000000 +0000 ++++ linux-3.2.46/drivers/i2c/algos/i2c-algo-bit.c 2013-07-26 19:26:17.000000000 +0000 +@@ -616,10 +616,11 @@ /* -----exported algorithm data: ------------------------------------- */ @@ -48,17 +48,14 @@ /* * registering functions to load algorithms at runtime -diff --git a/include/linux/i2c-algo-bit.h b/include/linux/i2c-algo-bit.h -index 4f98148..584ffa0 100644 ---- a/include/linux/i2c-algo-bit.h -+++ b/include/linux/i2c-algo-bit.h -@@ -49,5 +49,6 @@ struct i2c_algo_bit_data { +Index: linux-3.2.46/include/linux/i2c-algo-bit.h +=================================================================== +--- linux-3.2.46.orig/include/linux/i2c-algo-bit.h 2013-07-26 18:53:36.000000000 +0000 ++++ linux-3.2.46/include/linux/i2c-algo-bit.h 2013-07-26 19:26:17.000000000 +0000 +@@ -49,5 +49,6 @@ int i2c_bit_add_bus(struct i2c_adapter *); int i2c_bit_add_numbered_bus(struct i2c_adapter *); +extern const struct i2c_algorithm i2c_bit_algo; #endif /* _LINUX_I2C_ALGO_BIT_H */ --- -1.7.10.4 - diff -Nru linux-3.2.46/debian/patches/features/all/drm/Remove-gma500-driver-from-staging.patch linux-3.2.46/debian/patches/features/all/drm/Remove-gma500-driver-from-staging.patch --- linux-3.2.46/debian/patches/features/all/drm/Remove-gma500-driver-from-staging.patch 2013-02-24 03:52:31.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/drm/Remove-gma500-driver-from-staging.patch 2013-07-26 19:27:06.000000000 +0000 @@ -162,11 +162,11 @@ delete mode 100644 drivers/staging/gma500/psb_lid.c delete mode 100644 drivers/staging/gma500/psb_reg.h -diff --git a/drivers/staging/Kconfig b/drivers/staging/Kconfig -index 25cdff3..1c8d977 100644 ---- a/drivers/staging/Kconfig -+++ b/drivers/staging/Kconfig -@@ -124,8 +124,6 @@ source "drivers/staging/cptm1217/Kconfig" +Index: linux-3.2.46/drivers/staging/Kconfig +=================================================================== +--- linux-3.2.46.orig/drivers/staging/Kconfig 2013-07-26 19:19:22.000000000 +0000 ++++ linux-3.2.46/drivers/staging/Kconfig 2013-07-26 19:26:59.000000000 +0000 +@@ -122,8 +122,6 @@ source "drivers/staging/ste_rmi4/Kconfig" @@ -175,22 +175,21 @@ source "drivers/staging/mei/Kconfig" source "drivers/staging/nvec/Kconfig" -diff --git a/drivers/staging/Makefile b/drivers/staging/Makefile -index a25f3f2..1b78e0c 100644 ---- a/drivers/staging/Makefile -+++ b/drivers/staging/Makefile -@@ -54,6 +54,5 @@ obj-$(CONFIG_SND_INTEL_SST) += intel_sst/ +Index: linux-3.2.46/drivers/staging/Makefile +=================================================================== +--- linux-3.2.46.orig/drivers/staging/Makefile 2013-07-26 19:19:22.000000000 +0000 ++++ linux-3.2.46/drivers/staging/Makefile 2013-07-26 19:26:59.000000000 +0000 +@@ -53,6 +53,5 @@ obj-$(CONFIG_SPEAKUP) += speakup/ obj-$(CONFIG_TOUCHSCREEN_CLEARPAD_TM1217) += cptm1217/ obj-$(CONFIG_TOUCHSCREEN_SYNAPTICS_I2C_RMI4) += ste_rmi4/ -obj-$(CONFIG_DRM_PSB) += gma500/ obj-$(CONFIG_INTEL_MEI) += mei/ obj-$(CONFIG_MFD_NVEC) += nvec/ -diff --git a/drivers/staging/gma500/Kconfig b/drivers/staging/gma500/Kconfig -deleted file mode 100644 -index bfe2166..0000000 ---- a/drivers/staging/gma500/Kconfig -+++ /dev/null +Index: linux-3.2.46/drivers/staging/gma500/Kconfig +=================================================================== +--- linux-3.2.46.orig/drivers/staging/gma500/Kconfig 2013-07-26 18:53:23.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 @@ -1,33 +0,0 @@ -config DRM_PSB - tristate "Intel GMA5/600 KMS Framebuffer" @@ -225,11 +224,10 @@ - depends on DRM_PSB - help - Say yes to include support for Intel Cedarview platforms -diff --git a/drivers/staging/gma500/Makefile b/drivers/staging/gma500/Makefile -deleted file mode 100644 -index c729868..0000000 ---- a/drivers/staging/gma500/Makefile -+++ /dev/null +Index: linux-3.2.46/drivers/staging/gma500/Makefile +=================================================================== +--- linux-3.2.46.orig/drivers/staging/gma500/Makefile 2013-07-26 18:53:23.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 @@ -1,52 +0,0 @@ -# -# KMS driver for the GMA500 @@ -283,11 +281,10 @@ - mdfld_intel_display.o - -obj-$(CONFIG_DRM_PSB) += psb_gfx.o -diff --git a/drivers/staging/gma500/TODO b/drivers/staging/gma500/TODO -deleted file mode 100644 -index fc83615..0000000 ---- a/drivers/staging/gma500/TODO -+++ /dev/null +Index: linux-3.2.46/drivers/staging/gma500/TODO +=================================================================== +--- linux-3.2.46.orig/drivers/staging/gma500/TODO 2013-07-26 18:53:23.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 @@ -1,15 +0,0 @@ -- Sort out the power management side. Not important for Poulsbo but - matters for Moorestown/Medfield @@ -304,11 +301,10 @@ -As per kernel policy and the in the interest of the safety of various -kittens there is no support or plans to add hooks for the closed user space -stuff. -diff --git a/drivers/staging/gma500/accel_2d.c b/drivers/staging/gma500/accel_2d.c -deleted file mode 100644 -index 114b99a..0000000 ---- a/drivers/staging/gma500/accel_2d.c -+++ /dev/null +Index: linux-3.2.46/drivers/staging/gma500/accel_2d.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/gma500/accel_2d.c 2013-07-26 18:53:23.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 @@ -1,414 +0,0 @@ -/************************************************************************** - * Copyright (c) 2007-2011, Intel Corporation. @@ -724,11 +720,10 @@ - drm_gem_object_unreference(obj); - return err; -} -diff --git a/drivers/staging/gma500/backlight.c b/drivers/staging/gma500/backlight.c -deleted file mode 100644 -index 2079395..0000000 ---- a/drivers/staging/gma500/backlight.c -+++ /dev/null +Index: linux-3.2.46/drivers/staging/gma500/backlight.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/gma500/backlight.c 2013-07-26 18:53:23.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 @@ -1,49 +0,0 @@ -/* - * GMA500 Backlight Interface @@ -779,11 +774,10 @@ - } -#endif -} -diff --git a/drivers/staging/gma500/cdv_device.c b/drivers/staging/gma500/cdv_device.c -deleted file mode 100644 -index 8ec10ca..0000000 ---- a/drivers/staging/gma500/cdv_device.c -+++ /dev/null +Index: linux-3.2.46/drivers/staging/gma500/cdv_device.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/gma500/cdv_device.c 2013-07-26 18:53:23.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 @@ -1,350 +0,0 @@ -/************************************************************************** - * Copyright (c) 2011, Intel Corporation. @@ -1135,11 +1129,10 @@ - .power_down = cdv_power_down, - .power_up = cdv_power_up, -}; -diff --git a/drivers/staging/gma500/cdv_device.h b/drivers/staging/gma500/cdv_device.h -deleted file mode 100644 -index 2a88b7b..0000000 ---- a/drivers/staging/gma500/cdv_device.h -+++ /dev/null +Index: linux-3.2.46/drivers/staging/gma500/cdv_device.h +=================================================================== +--- linux-3.2.46.orig/drivers/staging/gma500/cdv_device.h 2013-07-26 18:53:23.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 @@ -1,36 +0,0 @@ -/* - * Copyright © 2011 Intel Corporation @@ -1177,11 +1170,10 @@ -} - - -diff --git a/drivers/staging/gma500/cdv_intel_crt.c b/drivers/staging/gma500/cdv_intel_crt.c -deleted file mode 100644 -index efda63b..0000000 ---- a/drivers/staging/gma500/cdv_intel_crt.c -+++ /dev/null +Index: linux-3.2.46/drivers/staging/gma500/cdv_intel_crt.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/gma500/cdv_intel_crt.c 2013-07-26 18:53:23.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 @@ -1,326 +0,0 @@ -/* - * Copyright © 2006-2007 Intel Corporation @@ -1509,11 +1501,10 @@ - kfree(psb_intel_output); - return; -} -diff --git a/drivers/staging/gma500/cdv_intel_display.c b/drivers/staging/gma500/cdv_intel_display.c -deleted file mode 100644 -index 7b97c60..0000000 ---- a/drivers/staging/gma500/cdv_intel_display.c -+++ /dev/null +Index: linux-3.2.46/drivers/staging/gma500/cdv_intel_display.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/gma500/cdv_intel_display.c 2013-07-26 18:53:23.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 @@ -1,1508 +0,0 @@ -/* - * Copyright © 2006-2011 Intel Corporation @@ -3023,11 +3014,10 @@ - REG_WRITE(base, 0); -} - -diff --git a/drivers/staging/gma500/cdv_intel_hdmi.c b/drivers/staging/gma500/cdv_intel_hdmi.c -deleted file mode 100644 -index cbca2b0..0000000 ---- a/drivers/staging/gma500/cdv_intel_hdmi.c -+++ /dev/null +Index: linux-3.2.46/drivers/staging/gma500/cdv_intel_hdmi.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/gma500/cdv_intel_hdmi.c 2013-07-26 18:53:23.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 @@ -1,376 +0,0 @@ -/* - * Copyright © 2006-2011 Intel Corporation @@ -3405,11 +3395,10 @@ - drm_connector_cleanup(&psb_intel_output->base); - kfree(psb_intel_output); -} -diff --git a/drivers/staging/gma500/cdv_intel_lvds.c b/drivers/staging/gma500/cdv_intel_lvds.c -deleted file mode 100644 -index 988b2d0..0000000 ---- a/drivers/staging/gma500/cdv_intel_lvds.c -+++ /dev/null +Index: linux-3.2.46/drivers/staging/gma500/cdv_intel_lvds.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/gma500/cdv_intel_lvds.c 2013-07-26 18:53:23.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 @@ -1,721 +0,0 @@ -/* - * Copyright © 2006-2011 Intel Corporation @@ -4132,11 +4121,10 @@ - drm_connector_cleanup(connector); - kfree(connector); -} -diff --git a/drivers/staging/gma500/displays/hdmi.h b/drivers/staging/gma500/displays/hdmi.h -deleted file mode 100644 -index d58ba9b..0000000 ---- a/drivers/staging/gma500/displays/hdmi.h -+++ /dev/null +Index: linux-3.2.46/drivers/staging/gma500/displays/hdmi.h +=================================================================== +--- linux-3.2.46.orig/drivers/staging/gma500/displays/hdmi.h 2013-07-26 18:53:23.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 @@ -1,33 +0,0 @@ -/* - * Copyright (c) 2010 Intel Corporation @@ -4171,11 +4159,10 @@ -extern void hdmi_init(struct drm_device *dev); - -#endif -diff --git a/drivers/staging/gma500/displays/pyr_cmd.h b/drivers/staging/gma500/displays/pyr_cmd.h -deleted file mode 100644 -index 84bae5c..0000000 ---- a/drivers/staging/gma500/displays/pyr_cmd.h -+++ /dev/null +Index: linux-3.2.46/drivers/staging/gma500/displays/pyr_cmd.h +=================================================================== +--- linux-3.2.46.orig/drivers/staging/gma500/displays/pyr_cmd.h 2013-07-26 18:53:23.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 @@ -1,34 +0,0 @@ -/* - * Copyright (c) 2010 Intel Corporation @@ -4211,11 +4198,10 @@ - -#endif - -diff --git a/drivers/staging/gma500/displays/pyr_vid.h b/drivers/staging/gma500/displays/pyr_vid.h -deleted file mode 100644 -index ce98860..0000000 ---- a/drivers/staging/gma500/displays/pyr_vid.h -+++ /dev/null +Index: linux-3.2.46/drivers/staging/gma500/displays/pyr_vid.h +=================================================================== +--- linux-3.2.46.orig/drivers/staging/gma500/displays/pyr_vid.h 2013-07-26 18:53:23.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 @@ -1,34 +0,0 @@ -/* - * Copyright (c) 2010 Intel Corporation @@ -4251,11 +4237,10 @@ -extern struct drm_display_mode *pyr_vid_get_config_mode(struct drm_device* dev); - -#endif -diff --git a/drivers/staging/gma500/displays/tmd_cmd.h b/drivers/staging/gma500/displays/tmd_cmd.h -deleted file mode 100644 -index 641e85e..0000000 ---- a/drivers/staging/gma500/displays/tmd_cmd.h -+++ /dev/null +Index: linux-3.2.46/drivers/staging/gma500/displays/tmd_cmd.h +=================================================================== +--- linux-3.2.46.orig/drivers/staging/gma500/displays/tmd_cmd.h 2013-07-26 18:53:23.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 @@ -1,34 +0,0 @@ -/* - * Copyright (c) 2010 Intel Corporation @@ -4291,11 +4276,10 @@ -extern struct drm_display_mode *tmd_cmd_get_config_mode(struct drm_device *dev); - -#endif -diff --git a/drivers/staging/gma500/displays/tmd_vid.h b/drivers/staging/gma500/displays/tmd_vid.h -deleted file mode 100644 -index 7a5fa3b..0000000 ---- a/drivers/staging/gma500/displays/tmd_vid.h -+++ /dev/null +Index: linux-3.2.46/drivers/staging/gma500/displays/tmd_vid.h +=================================================================== +--- linux-3.2.46.orig/drivers/staging/gma500/displays/tmd_vid.h 2013-07-26 18:53:23.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 @@ -1,34 +0,0 @@ -/* - * Copyright (c) 2010 Intel Corporation @@ -4331,11 +4315,10 @@ -extern struct drm_display_mode *tmd_vid_get_config_mode(struct drm_device *dev); - -#endif -diff --git a/drivers/staging/gma500/displays/tpo_cmd.h b/drivers/staging/gma500/displays/tpo_cmd.h -deleted file mode 100644 -index 6105527..0000000 ---- a/drivers/staging/gma500/displays/tpo_cmd.h -+++ /dev/null +Index: linux-3.2.46/drivers/staging/gma500/displays/tpo_cmd.h +=================================================================== +--- linux-3.2.46.orig/drivers/staging/gma500/displays/tpo_cmd.h 2013-07-26 18:53:23.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 @@ -1,35 +0,0 @@ -/* - * Copyright (c) 2010 Intel Corporation @@ -4372,11 +4355,10 @@ -/* tpo_cmd_get_config_mode(struct drm_device *dev); */ - -#endif -diff --git a/drivers/staging/gma500/displays/tpo_vid.h b/drivers/staging/gma500/displays/tpo_vid.h -deleted file mode 100644 -index c24f057..0000000 ---- a/drivers/staging/gma500/displays/tpo_vid.h -+++ /dev/null +Index: linux-3.2.46/drivers/staging/gma500/displays/tpo_vid.h +=================================================================== +--- linux-3.2.46.orig/drivers/staging/gma500/displays/tpo_vid.h 2013-07-26 18:53:23.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 @@ -1,33 +0,0 @@ -/* - * Copyright (c) 2010 Intel Corporation @@ -4411,11 +4393,10 @@ -extern void tpo_vid_init(struct drm_device *dev, struct panel_funcs *p_funcs); - -#endif -diff --git a/drivers/staging/gma500/framebuffer.c b/drivers/staging/gma500/framebuffer.c -deleted file mode 100644 -index 3f39a37..0000000 ---- a/drivers/staging/gma500/framebuffer.c -+++ /dev/null +Index: linux-3.2.46/drivers/staging/gma500/framebuffer.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/gma500/framebuffer.c 2013-07-26 18:53:23.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 @@ -1,849 +0,0 @@ -/************************************************************************** - * Copyright (c) 2007-2011, Intel Corporation. @@ -5266,11 +5247,10 @@ - - mutex_unlock(&dev->struct_mutex); -} -diff --git a/drivers/staging/gma500/framebuffer.h b/drivers/staging/gma500/framebuffer.h -deleted file mode 100644 -index d1b2289..0000000 ---- a/drivers/staging/gma500/framebuffer.h -+++ /dev/null +Index: linux-3.2.46/drivers/staging/gma500/framebuffer.h +=================================================================== +--- linux-3.2.46.orig/drivers/staging/gma500/framebuffer.h 2013-07-26 18:53:23.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 @@ -1,48 +0,0 @@ -/* - * Copyright (c) 2008-2011, Intel Corporation @@ -5320,11 +5300,10 @@ - -#endif - -diff --git a/drivers/staging/gma500/gem.c b/drivers/staging/gma500/gem.c -deleted file mode 100644 -index f6433c0..0000000 ---- a/drivers/staging/gma500/gem.c -+++ /dev/null +Index: linux-3.2.46/drivers/staging/gma500/gem.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/gma500/gem.c 2013-07-26 18:53:23.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 @@ -1,292 +0,0 @@ -/* - * psb GEM interface @@ -5618,11 +5597,10 @@ - args->handle, &args->offset); -} - -diff --git a/drivers/staging/gma500/gem_glue.c b/drivers/staging/gma500/gem_glue.c -deleted file mode 100644 -index daac121..0000000 ---- a/drivers/staging/gma500/gem_glue.c -+++ /dev/null +Index: linux-3.2.46/drivers/staging/gma500/gem_glue.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/gma500/gem_glue.c 2013-07-26 18:53:23.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 @@ -1,89 +0,0 @@ -/************************************************************************** - * Copyright (c) 2011, Intel Corporation. @@ -5713,19 +5691,17 @@ - list->map = NULL; - return ret; -} -diff --git a/drivers/staging/gma500/gem_glue.h b/drivers/staging/gma500/gem_glue.h -deleted file mode 100644 -index ce5ce30..0000000 ---- a/drivers/staging/gma500/gem_glue.h -+++ /dev/null +Index: linux-3.2.46/drivers/staging/gma500/gem_glue.h +=================================================================== +--- linux-3.2.46.orig/drivers/staging/gma500/gem_glue.h 2013-07-26 18:53:23.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 @@ -1,2 +0,0 @@ -extern void drm_gem_object_release_wrap(struct drm_gem_object *obj); -extern int gem_create_mmap_offset(struct drm_gem_object *obj); -diff --git a/drivers/staging/gma500/gtt.c b/drivers/staging/gma500/gtt.c -deleted file mode 100644 -index e770bd1..0000000 ---- a/drivers/staging/gma500/gtt.c -+++ /dev/null +Index: linux-3.2.46/drivers/staging/gma500/gtt.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/gma500/gtt.c 2013-07-26 18:53:23.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 @@ -1,553 +0,0 @@ -/* - * Copyright (c) 2007, Intel Corporation. @@ -6280,11 +6256,10 @@ - psb_gtt_takedown(dev); - return ret; -} -diff --git a/drivers/staging/gma500/gtt.h b/drivers/staging/gma500/gtt.h -deleted file mode 100644 -index aa17423..0000000 ---- a/drivers/staging/gma500/gtt.h -+++ /dev/null +Index: linux-3.2.46/drivers/staging/gma500/gtt.h +=================================================================== +--- linux-3.2.46.orig/drivers/staging/gma500/gtt.h 2013-07-26 18:53:23.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 @@ -1,64 +0,0 @@ -/************************************************************************** - * Copyright (c) 2007-2008, Intel Corporation. @@ -6350,11 +6325,10 @@ - struct gtt_range *gt, int roll); - -#endif -diff --git a/drivers/staging/gma500/intel_bios.c b/drivers/staging/gma500/intel_bios.c -deleted file mode 100644 -index 096757f..0000000 ---- a/drivers/staging/gma500/intel_bios.c -+++ /dev/null +Index: linux-3.2.46/drivers/staging/gma500/intel_bios.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/gma500/intel_bios.c 2013-07-26 18:53:23.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 @@ -1,303 +0,0 @@ -/* - * Copyright (c) 2006 Intel Corporation @@ -6659,11 +6633,10 @@ - kfree(lvds_bl); - } -} -diff --git a/drivers/staging/gma500/intel_bios.h b/drivers/staging/gma500/intel_bios.h -deleted file mode 100644 -index 70f1bf0..0000000 ---- a/drivers/staging/gma500/intel_bios.h -+++ /dev/null +Index: linux-3.2.46/drivers/staging/gma500/intel_bios.h +=================================================================== +--- linux-3.2.46.orig/drivers/staging/gma500/intel_bios.h 2013-07-26 18:53:23.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 @@ -1,430 +0,0 @@ -/* - * Copyright (c) 2006 Intel Corporation @@ -7095,11 +7068,10 @@ -#define SWF14_APM_RESTORE 0x0 - -#endif /* _I830_BIOS_H_ */ -diff --git a/drivers/staging/gma500/intel_i2c.c b/drivers/staging/gma500/intel_i2c.c -deleted file mode 100644 -index 51cbf65..0000000 ---- a/drivers/staging/gma500/intel_i2c.c -+++ /dev/null +Index: linux-3.2.46/drivers/staging/gma500/intel_i2c.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/gma500/intel_i2c.c 2013-07-26 18:53:23.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 @@ -1,170 +0,0 @@ -/* - * Copyright © 2006-2007 Intel Corporation @@ -7271,11 +7243,10 @@ - i2c_del_adapter(&chan->adapter); - kfree(chan); -} -diff --git a/drivers/staging/gma500/intel_opregion.c b/drivers/staging/gma500/intel_opregion.c -deleted file mode 100644 -index d946bc1..0000000 ---- a/drivers/staging/gma500/intel_opregion.c -+++ /dev/null +Index: linux-3.2.46/drivers/staging/gma500/intel_opregion.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/gma500/intel_opregion.c 2013-07-26 18:53:23.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 @@ -1,81 +0,0 @@ -/* - * Copyright 2010 Intel Corporation @@ -7358,11 +7329,10 @@ - iounmap(dev_priv->lid_state); - return 0; -} -diff --git a/drivers/staging/gma500/mdfld_device.c b/drivers/staging/gma500/mdfld_device.c -deleted file mode 100644 -index f47aeb7..0000000 ---- a/drivers/staging/gma500/mdfld_device.c -+++ /dev/null +Index: linux-3.2.46/drivers/staging/gma500/mdfld_device.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/gma500/mdfld_device.c 2013-07-26 18:53:23.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 @@ -1,714 +0,0 @@ -/************************************************************************** - * Copyright (c) 2011, Intel Corporation. @@ -8078,11 +8048,10 @@ - .power_up = mdfld_power_up, -}; - -diff --git a/drivers/staging/gma500/mdfld_dsi_dbi.c b/drivers/staging/gma500/mdfld_dsi_dbi.c -deleted file mode 100644 -index fd211f3..0000000 ---- a/drivers/staging/gma500/mdfld_dsi_dbi.c -+++ /dev/null +Index: linux-3.2.46/drivers/staging/gma500/mdfld_dsi_dbi.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/gma500/mdfld_dsi_dbi.c 2013-07-26 18:53:23.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 @@ -1,761 +0,0 @@ -/* - * Copyright © 2010 Intel Corporation @@ -8845,11 +8814,10 @@ - kfree(dbi_output); - return NULL; -} -diff --git a/drivers/staging/gma500/mdfld_dsi_dbi.h b/drivers/staging/gma500/mdfld_dsi_dbi.h -deleted file mode 100644 -index f0fa986..0000000 ---- a/drivers/staging/gma500/mdfld_dsi_dbi.h -+++ /dev/null +Index: linux-3.2.46/drivers/staging/gma500/mdfld_dsi_dbi.h +=================================================================== +--- linux-3.2.46.orig/drivers/staging/gma500/mdfld_dsi_dbi.h 2013-07-26 18:53:23.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 @@ -1,173 +0,0 @@ -/* - * Copyright © 2010 Intel Corporation @@ -9024,11 +8992,10 @@ - int pipe); - -#endif /*__MDFLD_DSI_DBI_H__*/ -diff --git a/drivers/staging/gma500/mdfld_dsi_dbi_dpu.c b/drivers/staging/gma500/mdfld_dsi_dbi_dpu.c -deleted file mode 100644 -index a4e2ff4..0000000 ---- a/drivers/staging/gma500/mdfld_dsi_dbi_dpu.c -+++ /dev/null +Index: linux-3.2.46/drivers/staging/gma500/mdfld_dsi_dbi_dpu.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/gma500/mdfld_dsi_dbi_dpu.c 2013-07-26 18:53:23.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 @@ -1,778 +0,0 @@ -/* - * Copyright © 2010-2011 Intel Corporation @@ -9808,11 +9775,10 @@ -} - - -diff --git a/drivers/staging/gma500/mdfld_dsi_dbi_dpu.h b/drivers/staging/gma500/mdfld_dsi_dbi_dpu.h -deleted file mode 100644 -index 42367ed..0000000 ---- a/drivers/staging/gma500/mdfld_dsi_dbi_dpu.h -+++ /dev/null +Index: linux-3.2.46/drivers/staging/gma500/mdfld_dsi_dbi_dpu.h +=================================================================== +--- linux-3.2.46.orig/drivers/staging/gma500/mdfld_dsi_dbi_dpu.h 2013-07-26 18:53:23.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 @@ -1,154 +0,0 @@ -/* - * Copyright © 2010 Intel Corporation @@ -9968,11 +9934,10 @@ -extern void mdfld_dpu_update_panel(struct drm_device *dev); - -#endif /*__MDFLD_DSI_DBI_DPU_H__*/ -diff --git a/drivers/staging/gma500/mdfld_dsi_dpi.c b/drivers/staging/gma500/mdfld_dsi_dpi.c -deleted file mode 100644 -index e685f12..0000000 ---- a/drivers/staging/gma500/mdfld_dsi_dpi.c -+++ /dev/null +Index: linux-3.2.46/drivers/staging/gma500/mdfld_dsi_dpi.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/gma500/mdfld_dsi_dpi.c 2013-07-26 18:53:23.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 @@ -1,805 +0,0 @@ -/* - * Copyright © 2010 Intel Corporation @@ -10779,11 +10744,10 @@ - return &dpi_output->base; -} - -diff --git a/drivers/staging/gma500/mdfld_dsi_dpi.h b/drivers/staging/gma500/mdfld_dsi_dpi.h -deleted file mode 100644 -index ed92d45..0000000 ---- a/drivers/staging/gma500/mdfld_dsi_dpi.h -+++ /dev/null +Index: linux-3.2.46/drivers/staging/gma500/mdfld_dsi_dpi.h +=================================================================== +--- linux-3.2.46.orig/drivers/staging/gma500/mdfld_dsi_dpi.h 2013-07-26 18:53:23.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 @@ -1,78 +0,0 @@ -/* - * Copyright © 2010 Intel Corporation @@ -10863,11 +10827,10 @@ -extern void mdfld_dsi_dpi_controller_init(struct mdfld_dsi_config *si_config, - int pipe); -#endif /*__MDFLD_DSI_DPI_H__*/ -diff --git a/drivers/staging/gma500/mdfld_dsi_output.c b/drivers/staging/gma500/mdfld_dsi_output.c -deleted file mode 100644 -index 3f979db..0000000 ---- a/drivers/staging/gma500/mdfld_dsi_output.c -+++ /dev/null +Index: linux-3.2.46/drivers/staging/gma500/mdfld_dsi_output.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/gma500/mdfld_dsi_output.c 2013-07-26 18:53:23.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 @@ -1,1014 +0,0 @@ -/* - * Copyright © 2010 Intel Corporation @@ -11883,11 +11846,10 @@ -dsi_init_err0: - kfree(dsi_connector); -} -diff --git a/drivers/staging/gma500/mdfld_dsi_output.h b/drivers/staging/gma500/mdfld_dsi_output.h -deleted file mode 100644 -index 4699267..0000000 ---- a/drivers/staging/gma500/mdfld_dsi_output.h -+++ /dev/null +Index: linux-3.2.46/drivers/staging/gma500/mdfld_dsi_output.h +=================================================================== +--- linux-3.2.46.orig/drivers/staging/gma500/mdfld_dsi_output.h 2013-07-26 18:53:23.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 @@ -1,138 +0,0 @@ -/* - * Copyright © 2010 Intel Corporation @@ -12027,11 +11989,10 @@ -extern int mdfld_dsi_panel_reset(int pipe); - -#endif /*__MDFLD_DSI_OUTPUT_H__*/ -diff --git a/drivers/staging/gma500/mdfld_dsi_pkg_sender.c b/drivers/staging/gma500/mdfld_dsi_pkg_sender.c -deleted file mode 100644 -index 9b96a5c..0000000 ---- a/drivers/staging/gma500/mdfld_dsi_pkg_sender.c -+++ /dev/null +Index: linux-3.2.46/drivers/staging/gma500/mdfld_dsi_pkg_sender.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/gma500/mdfld_dsi_pkg_sender.c 2013-07-26 18:53:23.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 @@ -1,1484 +0,0 @@ -/* - * Copyright © 2010 Intel Corporation @@ -13517,11 +13478,10 @@ - mdfld_dbi_cb_destroy(sender); /* free mapped command buffer */ - kfree(sender); -} -diff --git a/drivers/staging/gma500/mdfld_dsi_pkg_sender.h b/drivers/staging/gma500/mdfld_dsi_pkg_sender.h -deleted file mode 100644 -index f24abc7..0000000 ---- a/drivers/staging/gma500/mdfld_dsi_pkg_sender.h -+++ /dev/null +Index: linux-3.2.46/drivers/staging/gma500/mdfld_dsi_pkg_sender.h +=================================================================== +--- linux-3.2.46.orig/drivers/staging/gma500/mdfld_dsi_pkg_sender.h 2013-07-26 18:53:23.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 @@ -1,184 +0,0 @@ -/* - * Copyright © 2010 Intel Corporation @@ -13707,11 +13667,10 @@ -extern void mdfld_dsi_cmds_kick_out(struct mdfld_dsi_pkg_sender *sender); - -#endif /* __MDFLD_DSI_PKG_SENDER_H__ */ -diff --git a/drivers/staging/gma500/mdfld_intel_display.c b/drivers/staging/gma500/mdfld_intel_display.c -deleted file mode 100644 -index 8eb827e..0000000 ---- a/drivers/staging/gma500/mdfld_intel_display.c -+++ /dev/null +Index: linux-3.2.46/drivers/staging/gma500/mdfld_intel_display.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/gma500/mdfld_intel_display.c 2013-07-26 18:53:23.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 @@ -1,1404 +0,0 @@ -/* - * Copyright © 2006-2011 Intel Corporation @@ -15117,11 +15076,10 @@ - .prepare = mdfld_crtc_prepare, - .commit = mdfld_crtc_commit, -}; -diff --git a/drivers/staging/gma500/mdfld_msic.h b/drivers/staging/gma500/mdfld_msic.h -deleted file mode 100644 -index a7ad6547..0000000 ---- a/drivers/staging/gma500/mdfld_msic.h -+++ /dev/null +Index: linux-3.2.46/drivers/staging/gma500/mdfld_msic.h +=================================================================== +--- linux-3.2.46.orig/drivers/staging/gma500/mdfld_msic.h 2013-07-26 18:53:23.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 @@ -1,31 +0,0 @@ -/* - * Copyright © 2010 Intel Corporation @@ -15154,11 +15112,10 @@ -int msic_regsiter_driver(void); -int msic_unregister_driver(void); -extern void hpd_notify_um(void); -diff --git a/drivers/staging/gma500/mdfld_output.c b/drivers/staging/gma500/mdfld_output.c -deleted file mode 100644 -index eabf53d..0000000 ---- a/drivers/staging/gma500/mdfld_output.c -+++ /dev/null +Index: linux-3.2.46/drivers/staging/gma500/mdfld_output.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/gma500/mdfld_output.c 2013-07-26 18:53:23.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 @@ -1,171 +0,0 @@ -/* - * Copyright (c) 2010 Intel Corporation @@ -15331,11 +15288,10 @@ - mdfld_dbi_dsr_init(dev); - } -} -diff --git a/drivers/staging/gma500/mdfld_output.h b/drivers/staging/gma500/mdfld_output.h -deleted file mode 100644 -index daf33e7..0000000 ---- a/drivers/staging/gma500/mdfld_output.h -+++ /dev/null +Index: linux-3.2.46/drivers/staging/gma500/mdfld_output.h +=================================================================== +--- linux-3.2.46.orig/drivers/staging/gma500/mdfld_output.h 2013-07-26 18:53:23.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 @@ -1,41 +0,0 @@ -/* - * Copyright (c) 2010 Intel Corporation @@ -15378,11 +15334,10 @@ -extern void mdfld_output_setup(struct drm_device *dev); - -#endif -diff --git a/drivers/staging/gma500/mdfld_pyr_cmd.c b/drivers/staging/gma500/mdfld_pyr_cmd.c -deleted file mode 100644 -index 523f2d8..0000000 ---- a/drivers/staging/gma500/mdfld_pyr_cmd.c -+++ /dev/null +Index: linux-3.2.46/drivers/staging/gma500/mdfld_pyr_cmd.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/gma500/mdfld_pyr_cmd.c 2013-07-26 18:53:23.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 @@ -1,558 +0,0 @@ -/* - * Copyright (c) 2010 Intel Corporation @@ -15942,11 +15897,10 @@ - p_funcs->update_fb = pyr_dsi_dbi_update_fb; - p_funcs->get_panel_info = pyr_cmd_get_panel_info; -} -diff --git a/drivers/staging/gma500/mdfld_tmd_vid.c b/drivers/staging/gma500/mdfld_tmd_vid.c -deleted file mode 100644 -index affdc09..0000000 ---- a/drivers/staging/gma500/mdfld_tmd_vid.c -+++ /dev/null +Index: linux-3.2.46/drivers/staging/gma500/mdfld_tmd_vid.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/gma500/mdfld_tmd_vid.c 2013-07-26 18:53:23.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 @@ -1,206 +0,0 @@ -/* - * Copyright © 2010 Intel Corporation @@ -16154,11 +16108,10 @@ - p_funcs->reset = mdfld_dsi_panel_reset; - p_funcs->drv_ic_init = mdfld_dsi_tmd_drv_ic_init; -} -diff --git a/drivers/staging/gma500/mdfld_tpo_cmd.c b/drivers/staging/gma500/mdfld_tpo_cmd.c -deleted file mode 100644 -index c7f7c9c..0000000 ---- a/drivers/staging/gma500/mdfld_tpo_cmd.c -+++ /dev/null +Index: linux-3.2.46/drivers/staging/gma500/mdfld_tpo_cmd.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/gma500/mdfld_tpo_cmd.c 2013-07-26 18:53:23.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 @@ -1,509 +0,0 @@ -/* - * Copyright (c) 2010 Intel Corporation @@ -16669,11 +16622,10 @@ - p_funcs->reset = mdfld_dsi_panel_reset; - p_funcs->drv_ic_init = mdfld_dsi_brightness_init; -} -diff --git a/drivers/staging/gma500/mdfld_tpo_vid.c b/drivers/staging/gma500/mdfld_tpo_vid.c -deleted file mode 100644 -index 9549017..0000000 ---- a/drivers/staging/gma500/mdfld_tpo_vid.c -+++ /dev/null +Index: linux-3.2.46/drivers/staging/gma500/mdfld_tpo_vid.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/gma500/mdfld_tpo_vid.c 2013-07-26 18:53:23.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 @@ -1,140 +0,0 @@ -/* - * Copyright © 2010 Intel Corporation @@ -16815,11 +16767,10 @@ - p_funcs->update_fb = NULL; - p_funcs->get_panel_info = tpo_vid_get_panel_info; -} -diff --git a/drivers/staging/gma500/medfield.h b/drivers/staging/gma500/medfield.h -deleted file mode 100644 -index 09e9687..0000000 ---- a/drivers/staging/gma500/medfield.h -+++ /dev/null +Index: linux-3.2.46/drivers/staging/gma500/medfield.h +=================================================================== +--- linux-3.2.46.orig/drivers/staging/gma500/medfield.h 2013-07-26 18:53:23.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 @@ -1,268 +0,0 @@ -/* - * Copyright © 2011 Intel Corporation @@ -17089,11 +17040,10 @@ - void (*drv_ic_init)(struct mdfld_dsi_config *dsi_config, int pipe); -}; - -diff --git a/drivers/staging/gma500/mid_bios.c b/drivers/staging/gma500/mid_bios.c -deleted file mode 100644 -index ee3c036..0000000 ---- a/drivers/staging/gma500/mid_bios.c -+++ /dev/null +Index: linux-3.2.46/drivers/staging/gma500/mid_bios.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/gma500/mid_bios.c 2013-07-26 18:53:23.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 @@ -1,270 +0,0 @@ -/************************************************************************** - * Copyright (c) 2011, Intel Corporation. @@ -17365,11 +17315,10 @@ - mid_get_pci_revID(dev_priv); - return 0; -} -diff --git a/drivers/staging/gma500/mid_bios.h b/drivers/staging/gma500/mid_bios.h -deleted file mode 100644 -index 00e7d56..0000000 ---- a/drivers/staging/gma500/mid_bios.h -+++ /dev/null +Index: linux-3.2.46/drivers/staging/gma500/mid_bios.h +=================================================================== +--- linux-3.2.46.orig/drivers/staging/gma500/mid_bios.h 2013-07-26 18:53:23.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 @@ -1,21 +0,0 @@ -/************************************************************************** - * Copyright (c) 2011, Intel Corporation. @@ -17392,11 +17341,10 @@ - -extern int mid_chip_setup(struct drm_device *dev); - -diff --git a/drivers/staging/gma500/mmu.c b/drivers/staging/gma500/mmu.c -deleted file mode 100644 -index c904d73..0000000 ---- a/drivers/staging/gma500/mmu.c -+++ /dev/null +Index: linux-3.2.46/drivers/staging/gma500/mmu.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/gma500/mmu.c 2013-07-26 18:53:23.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 @@ -1,858 +0,0 @@ -/************************************************************************** - * Copyright (c) 2007, Intel Corporation. @@ -18256,11 +18204,10 @@ - up_read(&pd->driver->sem); - return ret; -} -diff --git a/drivers/staging/gma500/mrst.h b/drivers/staging/gma500/mrst.h -deleted file mode 100644 -index b563dbc..0000000 ---- a/drivers/staging/gma500/mrst.h -+++ /dev/null +Index: linux-3.2.46/drivers/staging/gma500/mrst.h +=================================================================== +--- linux-3.2.46.orig/drivers/staging/gma500/mrst.h 2013-07-26 18:53:23.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 @@ -1,252 +0,0 @@ -/************************************************************************** - * Copyright (c) 2007-2011, Intel Corporation. @@ -18514,11 +18461,10 @@ -extern void mrst_hdmi_save(struct drm_device *dev); -extern void mrst_hdmi_restore(struct drm_device *dev); -extern void mrst_hdmi_init(struct drm_device *dev, struct psb_intel_mode_device *mode_dev); -diff --git a/drivers/staging/gma500/mrst_crtc.c b/drivers/staging/gma500/mrst_crtc.c -deleted file mode 100644 -index c9311a5..0000000 ---- a/drivers/staging/gma500/mrst_crtc.c -+++ /dev/null +Index: linux-3.2.46/drivers/staging/gma500/mrst_crtc.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/gma500/mrst_crtc.c 2013-07-26 18:53:23.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 @@ -1,604 +0,0 @@ -/* - * Copyright © 2009 Intel Corporation @@ -19124,11 +19070,10 @@ - .commit = mrst_crtc_commit, -}; - -diff --git a/drivers/staging/gma500/mrst_device.c b/drivers/staging/gma500/mrst_device.c -deleted file mode 100644 -index 6707faf..0000000 ---- a/drivers/staging/gma500/mrst_device.c -+++ /dev/null +Index: linux-3.2.46/drivers/staging/gma500/mrst_device.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/gma500/mrst_device.c 2013-07-26 18:53:23.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 @@ -1,634 +0,0 @@ -/************************************************************************** - * Copyright (c) 2011, Intel Corporation. @@ -19764,11 +19709,10 @@ - .i2c_bus = 2, -}; - -diff --git a/drivers/staging/gma500/mrst_hdmi.c b/drivers/staging/gma500/mrst_hdmi.c -deleted file mode 100644 -index e66607e..0000000 ---- a/drivers/staging/gma500/mrst_hdmi.c -+++ /dev/null +Index: linux-3.2.46/drivers/staging/gma500/mrst_hdmi.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/gma500/mrst_hdmi.c 2013-07-26 18:53:23.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 @@ -1,852 +0,0 @@ -/* - * Copyright © 2010 Intel Corporation @@ -20622,11 +20566,10 @@ - for (i = 0; i < 256; i++) - PSB_WVDC32(dev_priv->save_palette_b[i], PALETTE_B + (i << 2)); -} -diff --git a/drivers/staging/gma500/mrst_hdmi_i2c.c b/drivers/staging/gma500/mrst_hdmi_i2c.c -deleted file mode 100644 -index 36e7edc..0000000 ---- a/drivers/staging/gma500/mrst_hdmi_i2c.c -+++ /dev/null +Index: linux-3.2.46/drivers/staging/gma500/mrst_hdmi_i2c.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/gma500/mrst_hdmi_i2c.c 2013-07-26 18:53:23.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 @@ -1,328 +0,0 @@ -/* - * Copyright © 2010 Intel Corporation @@ -20956,11 +20899,10 @@ - kfree(i2c_dev); - free_irq(dev->irq, hdmi_dev); -} -diff --git a/drivers/staging/gma500/mrst_lvds.c b/drivers/staging/gma500/mrst_lvds.c -deleted file mode 100644 -index e7999a2..0000000 ---- a/drivers/staging/gma500/mrst_lvds.c -+++ /dev/null +Index: linux-3.2.46/drivers/staging/gma500/mrst_lvds.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/gma500/mrst_lvds.c 2013-07-26 18:53:23.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 @@ -1,407 +0,0 @@ -/* - * Copyright © 2006-2009 Intel Corporation @@ -21369,11 +21311,10 @@ - kfree(connector); -} - -diff --git a/drivers/staging/gma500/power.c b/drivers/staging/gma500/power.c -deleted file mode 100644 -index 436fe97..0000000 ---- a/drivers/staging/gma500/power.c -+++ /dev/null +Index: linux-3.2.46/drivers/staging/gma500/power.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/gma500/power.c 2013-07-26 18:53:23.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 @@ -1,318 +0,0 @@ -/************************************************************************** - * Copyright (c) 2009-2011, Intel Corporation. @@ -21693,11 +21634,10 @@ - else - return 1; -} -diff --git a/drivers/staging/gma500/power.h b/drivers/staging/gma500/power.h -deleted file mode 100644 -index 1969d2e..0000000 ---- a/drivers/staging/gma500/power.h -+++ /dev/null +Index: linux-3.2.46/drivers/staging/gma500/power.h +=================================================================== +--- linux-3.2.46.orig/drivers/staging/gma500/power.h 2013-07-26 18:53:23.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 @@ -1,67 +0,0 @@ -/************************************************************************** - * Copyright (c) 2009-2011, Intel Corporation. @@ -21766,11 +21706,10 @@ -int psb_runtime_idle(struct device *dev); - -#endif /*_PSB_POWERMGMT_H_*/ -diff --git a/drivers/staging/gma500/psb_device.c b/drivers/staging/gma500/psb_device.c -deleted file mode 100644 -index b97aa78..0000000 ---- a/drivers/staging/gma500/psb_device.c -+++ /dev/null +Index: linux-3.2.46/drivers/staging/gma500/psb_device.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/gma500/psb_device.c 2013-07-26 18:53:23.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 @@ -1,321 +0,0 @@ -/************************************************************************** - * Copyright (c) 2011, Intel Corporation. @@ -22093,11 +22032,10 @@ - .power_up = psb_power_up, -}; - -diff --git a/drivers/staging/gma500/psb_drm.h b/drivers/staging/gma500/psb_drm.h -deleted file mode 100644 -index 0da8468..0000000 ---- a/drivers/staging/gma500/psb_drm.h -+++ /dev/null +Index: linux-3.2.46/drivers/staging/gma500/psb_drm.h +=================================================================== +--- linux-3.2.46.orig/drivers/staging/gma500/psb_drm.h 2013-07-26 18:53:23.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 @@ -1,219 +0,0 @@ -/************************************************************************** - * Copyright (c) 2007-2011, Intel Corporation. @@ -22318,11 +22256,10 @@ -}; - -#endif -diff --git a/drivers/staging/gma500/psb_drv.c b/drivers/staging/gma500/psb_drv.c -deleted file mode 100644 -index 986a04d..0000000 ---- a/drivers/staging/gma500/psb_drv.c -+++ /dev/null +Index: linux-3.2.46/drivers/staging/gma500/psb_drv.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/gma500/psb_drv.c 2013-07-26 18:53:23.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 @@ -1,1229 +0,0 @@ -/************************************************************************** - * Copyright (c) 2007-2011, Intel Corporation. @@ -23553,11 +23490,10 @@ -MODULE_AUTHOR("Alan Cox and others"); -MODULE_DESCRIPTION(DRIVER_DESC); -MODULE_LICENSE("GPL"); -diff --git a/drivers/staging/gma500/psb_drv.h b/drivers/staging/gma500/psb_drv.h -deleted file mode 100644 -index 11d963a..0000000 ---- a/drivers/staging/gma500/psb_drv.h -+++ /dev/null +Index: linux-3.2.46/drivers/staging/gma500/psb_drv.h +=================================================================== +--- linux-3.2.46.orig/drivers/staging/gma500/psb_drv.h 2013-07-26 18:53:23.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 @@ -1,952 +0,0 @@ -/************************************************************************** - * Copyright (c) 2007-2011, Intel Corporation. @@ -24511,11 +24447,10 @@ -#define PSB_RMSVDX32(_offs) ioread32(dev_priv->msvdx_reg + (_offs)) - -#endif -diff --git a/drivers/staging/gma500/psb_intel_display.c b/drivers/staging/gma500/psb_intel_display.c -deleted file mode 100644 -index caa9d86..0000000 ---- a/drivers/staging/gma500/psb_intel_display.c -+++ /dev/null +Index: linux-3.2.46/drivers/staging/gma500/psb_intel_display.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/gma500/psb_intel_display.c 2013-07-26 18:53:23.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 @@ -1,1429 +0,0 @@ -/* - * Copyright © 2006-2011 Intel Corporation @@ -25946,11 +25881,10 @@ - return &psb_intel_output->enc; -} - -diff --git a/drivers/staging/gma500/psb_intel_display.h b/drivers/staging/gma500/psb_intel_display.h -deleted file mode 100644 -index 535b49a..0000000 ---- a/drivers/staging/gma500/psb_intel_display.h -+++ /dev/null +Index: linux-3.2.46/drivers/staging/gma500/psb_intel_display.h +=================================================================== +--- linux-3.2.46.orig/drivers/staging/gma500/psb_intel_display.h 2013-07-26 18:53:23.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 @@ -1,28 +0,0 @@ -/* copyright (c) 2008, Intel Corporation - * @@ -25980,11 +25914,10 @@ -void psb_intel_crtc_destroy(struct drm_crtc *crtc); - -#endif -diff --git a/drivers/staging/gma500/psb_intel_drv.h b/drivers/staging/gma500/psb_intel_drv.h -deleted file mode 100644 -index 36b554b..0000000 ---- a/drivers/staging/gma500/psb_intel_drv.h -+++ /dev/null +Index: linux-3.2.46/drivers/staging/gma500/psb_intel_drv.h +=================================================================== +--- linux-3.2.46.orig/drivers/staging/gma500/psb_intel_drv.h 2013-07-26 18:53:23.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 @@ -1,230 +0,0 @@ -/* - * Copyright (c) 2009-2011, Intel Corporation. @@ -26216,11 +26149,10 @@ -extern void mdfldWaitForPipeEnable(struct drm_device *dev, int pipe); - -#endif /* __INTEL_DRV_H__ */ -diff --git a/drivers/staging/gma500/psb_intel_lvds.c b/drivers/staging/gma500/psb_intel_lvds.c -deleted file mode 100644 -index 21022e1..0000000 ---- a/drivers/staging/gma500/psb_intel_lvds.c -+++ /dev/null +Index: linux-3.2.46/drivers/staging/gma500/psb_intel_lvds.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/gma500/psb_intel_lvds.c 2013-07-26 18:53:23.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 @@ -1,854 +0,0 @@ -/* - * Copyright © 2006-2007 Intel Corporation @@ -27076,11 +27008,10 @@ - kfree(connector); -} - -diff --git a/drivers/staging/gma500/psb_intel_modes.c b/drivers/staging/gma500/psb_intel_modes.c -deleted file mode 100644 -index bde1aff..0000000 ---- a/drivers/staging/gma500/psb_intel_modes.c -+++ /dev/null +Index: linux-3.2.46/drivers/staging/gma500/psb_intel_modes.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/gma500/psb_intel_modes.c 2013-07-26 18:53:23.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 @@ -1,77 +0,0 @@ -/* - * Copyright (c) 2007 Intel Corporation @@ -27159,11 +27090,10 @@ - } - return ret; -} -diff --git a/drivers/staging/gma500/psb_intel_reg.h b/drivers/staging/gma500/psb_intel_reg.h -deleted file mode 100644 -index 1ac16aa..0000000 ---- a/drivers/staging/gma500/psb_intel_reg.h -+++ /dev/null +Index: linux-3.2.46/drivers/staging/gma500/psb_intel_reg.h +=================================================================== +--- linux-3.2.46.orig/drivers/staging/gma500/psb_intel_reg.h 2013-07-26 18:53:23.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 @@ -1,1235 +0,0 @@ -/* - * Copyright (c) 2009, Intel Corporation. @@ -28400,11 +28330,10 @@ - - -#endif -diff --git a/drivers/staging/gma500/psb_intel_sdvo.c b/drivers/staging/gma500/psb_intel_sdvo.c -deleted file mode 100644 -index a4bad1a..0000000 ---- a/drivers/staging/gma500/psb_intel_sdvo.c -+++ /dev/null +Index: linux-3.2.46/drivers/staging/gma500/psb_intel_sdvo.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/gma500/psb_intel_sdvo.c 2013-07-26 18:53:23.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 @@ -1,1293 +0,0 @@ -/* - * Copyright (c) 2006-2007 Intel Corporation @@ -29699,11 +29628,10 @@ - - return; -} -diff --git a/drivers/staging/gma500/psb_intel_sdvo_regs.h b/drivers/staging/gma500/psb_intel_sdvo_regs.h -deleted file mode 100644 -index 96862ea..0000000 ---- a/drivers/staging/gma500/psb_intel_sdvo_regs.h -+++ /dev/null +Index: linux-3.2.46/drivers/staging/gma500/psb_intel_sdvo_regs.h +=================================================================== +--- linux-3.2.46.orig/drivers/staging/gma500/psb_intel_sdvo_regs.h 2013-07-26 18:53:23.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 @@ -1,338 +0,0 @@ -/* - * SDVO command definitions and structures. @@ -30043,11 +29971,10 @@ -#define SDVO_DEVICE_LVDS 0x04 -#define SDVO_DEVICE_TMDS 0x08 - -diff --git a/drivers/staging/gma500/psb_irq.c b/drivers/staging/gma500/psb_irq.c -deleted file mode 100644 -index 36dd630..0000000 ---- a/drivers/staging/gma500/psb_irq.c -+++ /dev/null +Index: linux-3.2.46/drivers/staging/gma500/psb_irq.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/gma500/psb_irq.c 2013-07-26 18:53:23.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 @@ -1,627 +0,0 @@ -/************************************************************************** - * Copyright (c) 2007, Intel Corporation. @@ -30676,11 +30603,10 @@ - return count; -} - -diff --git a/drivers/staging/gma500/psb_irq.h b/drivers/staging/gma500/psb_irq.h -deleted file mode 100644 -index 216fda3..0000000 ---- a/drivers/staging/gma500/psb_irq.h -+++ /dev/null +Index: linux-3.2.46/drivers/staging/gma500/psb_irq.h +=================================================================== +--- linux-3.2.46.orig/drivers/staging/gma500/psb_irq.h 2013-07-26 18:53:23.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 @@ -1,45 +0,0 @@ -/************************************************************************** - * Copyright (c) 2009-2011, Intel Corporation. @@ -30727,11 +30653,10 @@ -u32 psb_get_vblank_counter(struct drm_device *dev, int pipe); - -#endif /* _SYSIRQ_H_ */ -diff --git a/drivers/staging/gma500/psb_lid.c b/drivers/staging/gma500/psb_lid.c -deleted file mode 100644 -index b867aabe..0000000 ---- a/drivers/staging/gma500/psb_lid.c -+++ /dev/null +Index: linux-3.2.46/drivers/staging/gma500/psb_lid.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/gma500/psb_lid.c 2013-07-26 18:53:23.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 @@ -1,88 +0,0 @@ -/************************************************************************** - * Copyright (c) 2007, Intel Corporation. @@ -30821,11 +30746,10 @@ - del_timer_sync(&dev_priv->lid_timer); -} - -diff --git a/drivers/staging/gma500/psb_reg.h b/drivers/staging/gma500/psb_reg.h -deleted file mode 100644 -index b81c7c1..0000000 ---- a/drivers/staging/gma500/psb_reg.h -+++ /dev/null +Index: linux-3.2.46/drivers/staging/gma500/psb_reg.h +=================================================================== +--- linux-3.2.46.orig/drivers/staging/gma500/psb_reg.h 2013-07-26 18:53:23.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 @@ -1,582 +0,0 @@ -/************************************************************************** - * @@ -31409,6 +31333,3 @@ -#define MDFLD_PWRGT_DISPLAY_STS_A0 (MDFLD_PWRGT_DISPLAY_A_STS | MDFLD_PWRGT_DISPLAY_B_STS | MDFLD_PWRGT_DISPLAY_C_STS | MDFLD_PWRGT_DISP_MIPI_STS) /* 0x000fc00c */ -#define MDFLD_PWRGT_DISPLAY_STS_B0 (MDFLD_PWRGT_DISPLAY_A_STS_B0 | MDFLD_PWRGT_DISPLAY_B_STS_B0 | MDFLD_PWRGT_DISPLAY_C_STS_B0 | MDFLD_PWRGT_DISP_MIPI_STS) /* 0x000fc00c */ -#endif --- -1.7.10.4 - diff -Nru linux-3.2.46/debian/patches/features/all/drm/Revert-drm-base-prime-dma-buf-support-v5.patch linux-3.2.46/debian/patches/features/all/drm/Revert-drm-base-prime-dma-buf-support-v5.patch --- linux-3.2.46/debian/patches/features/all/drm/Revert-drm-base-prime-dma-buf-support-v5.patch 2013-02-24 03:52:31.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/drm/Revert-drm-base-prime-dma-buf-support-v5.patch 2013-07-26 19:27:07.000000000 +0000 @@ -16,11 +16,11 @@ 8 files changed, 2 insertions(+), 401 deletions(-) delete mode 100644 drivers/gpu/drm/drm_prime.c -diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig -index e354bc0..cc11488 100644 ---- a/drivers/gpu/drm/Kconfig -+++ b/drivers/gpu/drm/Kconfig -@@ -9,7 +9,6 @@ menuconfig DRM +Index: linux-3.2.46/drivers/gpu/drm/Kconfig +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/Kconfig 2013-07-26 19:26:21.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/Kconfig 2013-07-26 19:27:06.000000000 +0000 +@@ -9,7 +9,6 @@ depends on (AGP || AGP=n) && !EMULATED_CMPXCHG && MMU select I2C select I2C_ALGOBIT @@ -28,11 +28,11 @@ help Kernel-level support for the Direct Rendering Infrastructure (DRI) introduced in XFree86 4.0. If you say Y here, you need to select -diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile -index c20da5b..a858532 100644 ---- a/drivers/gpu/drm/Makefile -+++ b/drivers/gpu/drm/Makefile -@@ -12,7 +12,7 @@ drm-y := drm_auth.o drm_buffer.o drm_bufs.o drm_cache.o \ +Index: linux-3.2.46/drivers/gpu/drm/Makefile +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/Makefile 2013-07-26 19:26:21.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/Makefile 2013-07-26 19:27:06.000000000 +0000 +@@ -12,7 +12,7 @@ drm_platform.o drm_sysfs.o drm_hashtab.o drm_mm.o \ drm_crtc.o drm_modes.o drm_edid.o \ drm_info.o drm_debugfs.o drm_encoder_slave.o \ @@ -41,11 +41,11 @@ drm-$(CONFIG_COMPAT) += drm_ioc32.o -diff --git a/drivers/gpu/drm/drm_drv.c b/drivers/gpu/drm/drm_drv.c -index 6116e3b..0b65fbc 100644 ---- a/drivers/gpu/drm/drm_drv.c -+++ b/drivers/gpu/drm/drm_drv.c -@@ -136,10 +136,6 @@ static struct drm_ioctl_desc drm_ioctls[] = { +Index: linux-3.2.46/drivers/gpu/drm/drm_drv.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/drm_drv.c 2013-07-26 19:26:21.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/drm_drv.c 2013-07-26 19:27:06.000000000 +0000 +@@ -136,10 +136,6 @@ DRM_IOCTL_DEF(DRM_IOCTL_GEM_OPEN, drm_gem_open_ioctl, DRM_AUTH|DRM_UNLOCKED), DRM_IOCTL_DEF(DRM_IOCTL_MODE_GETRESOURCES, drm_mode_getresources, DRM_CONTROL_ALLOW|DRM_UNLOCKED), @@ -56,11 +56,11 @@ DRM_IOCTL_DEF(DRM_IOCTL_MODE_GETPLANERESOURCES, drm_mode_getplane_res, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED), DRM_IOCTL_DEF(DRM_IOCTL_MODE_GETCRTC, drm_mode_getcrtc, DRM_CONTROL_ALLOW|DRM_UNLOCKED), DRM_IOCTL_DEF(DRM_IOCTL_MODE_SETCRTC, drm_mode_setcrtc, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED), -diff --git a/drivers/gpu/drm/drm_fops.c b/drivers/gpu/drm/drm_fops.c -index 123de28..0db8d56 100644 ---- a/drivers/gpu/drm/drm_fops.c -+++ b/drivers/gpu/drm/drm_fops.c -@@ -271,9 +271,6 @@ static int drm_open_helper(struct inode *inode, struct file *filp, +Index: linux-3.2.46/drivers/gpu/drm/drm_fops.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/drm_fops.c 2013-07-26 19:26:21.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/drm_fops.c 2013-07-26 19:27:06.000000000 +0000 +@@ -274,9 +274,6 @@ if (dev->driver->driver_features & DRIVER_GEM) drm_gem_open(dev, priv); @@ -70,7 +70,7 @@ if (dev->driver->open) { ret = dev->driver->open(dev, priv); if (ret < 0) -@@ -574,10 +571,6 @@ int drm_release(struct inode *inode, struct file *filp) +@@ -577,10 +574,6 @@ if (dev->driver->postclose) dev->driver->postclose(dev, file_priv); @@ -81,10 +81,10 @@ kfree(file_priv); /* ======================================================== -diff --git a/drivers/gpu/drm/drm_gem.c b/drivers/gpu/drm/drm_gem.c -index 83114b5..0ef358e 100644 ---- a/drivers/gpu/drm/drm_gem.c -+++ b/drivers/gpu/drm/drm_gem.c +Index: linux-3.2.46/drivers/gpu/drm/drm_gem.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/drm_gem.c 2013-07-26 19:26:21.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/drm_gem.c 2013-07-26 19:27:06.000000000 +0000 @@ -35,7 +35,6 @@ #include #include @@ -93,7 +93,7 @@ #include "drmP.h" /** @file drm_gem.c -@@ -233,10 +232,6 @@ drm_gem_handle_delete(struct drm_file *filp, u32 handle) +@@ -233,10 +232,6 @@ idr_remove(&filp->object_idr, handle); spin_unlock(&filp->table_lock); @@ -104,7 +104,7 @@ if (dev->driver->gem_close_object) dev->driver->gem_close_object(obj, filp); drm_gem_object_handle_unreference_unlocked(obj); -@@ -532,10 +527,6 @@ drm_gem_object_release_handle(int id, void *ptr, void *data) +@@ -532,10 +527,6 @@ struct drm_gem_object *obj = ptr; struct drm_device *dev = obj->dev; @@ -115,11 +115,10 @@ if (dev->driver->gem_close_object) dev->driver->gem_close_object(obj, file_priv); -diff --git a/drivers/gpu/drm/drm_prime.c b/drivers/gpu/drm/drm_prime.c -deleted file mode 100644 -index 1bdf2b5..0000000 ---- a/drivers/gpu/drm/drm_prime.c -+++ /dev/null +Index: linux-3.2.46/drivers/gpu/drm/drm_prime.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/drm_prime.c 2013-07-26 19:26:21.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 @@ -1,304 +0,0 @@ -/* - * Copyright © 2012 Red Hat @@ -425,11 +424,11 @@ - mutex_unlock(&prime_fpriv->lock); -} -EXPORT_SYMBOL(drm_prime_remove_imported_buf_handle); -diff --git a/include/drm/drm.h b/include/drm/drm.h -index 64ff02d..34a7b89 100644 ---- a/include/drm/drm.h -+++ b/include/drm/drm.h -@@ -617,17 +617,6 @@ struct drm_get_cap { +Index: linux-3.2.46/include/drm/drm.h +=================================================================== +--- linux-3.2.46.orig/include/drm/drm.h 2013-07-26 19:26:25.000000000 +0000 ++++ linux-3.2.46/include/drm/drm.h 2013-07-26 19:27:06.000000000 +0000 +@@ -617,17 +617,6 @@ __u64 value; }; @@ -447,7 +446,7 @@ #include "drm_mode.h" #define DRM_IOCTL_BASE 'd' -@@ -684,8 +673,7 @@ struct drm_prime_handle { +@@ -684,8 +673,7 @@ #define DRM_IOCTL_UNLOCK DRM_IOW( 0x2b, struct drm_lock) #define DRM_IOCTL_FINISH DRM_IOW( 0x2c, struct drm_lock) @@ -457,11 +456,11 @@ #define DRM_IOCTL_AGP_ACQUIRE DRM_IO( 0x30) #define DRM_IOCTL_AGP_RELEASE DRM_IO( 0x31) -diff --git a/include/drm/drmP.h b/include/drm/drmP.h -index dd73104..574bd1c 100644 ---- a/include/drm/drmP.h -+++ b/include/drm/drmP.h -@@ -91,7 +91,6 @@ struct drm_device; +Index: linux-3.2.46/include/drm/drmP.h +=================================================================== +--- linux-3.2.46.orig/include/drm/drmP.h 2013-07-26 19:26:25.000000000 +0000 ++++ linux-3.2.46/include/drm/drmP.h 2013-07-26 19:27:06.000000000 +0000 +@@ -91,7 +91,6 @@ #define DRM_UT_CORE 0x01 #define DRM_UT_DRIVER 0x02 #define DRM_UT_KMS 0x04 @@ -469,7 +468,7 @@ /* * Three debug levels are defined. * drm_core, drm_driver, drm_kms -@@ -151,7 +150,6 @@ int drm_err(const char *func, const char *format, ...); +@@ -151,7 +150,6 @@ #define DRIVER_IRQ_VBL2 0x800 #define DRIVER_GEM 0x1000 #define DRIVER_MODESET 0x2000 @@ -477,7 +476,7 @@ #define DRIVER_BUS_PCI 0x1 #define DRIVER_BUS_PLATFORM 0x2 -@@ -217,11 +215,6 @@ int drm_err(const char *func, const char *format, ...); +@@ -217,11 +215,6 @@ drm_ut_debug_printk(DRM_UT_KMS, DRM_NAME, \ __func__, fmt, ##args); \ } while (0) @@ -489,7 +488,7 @@ #define DRM_LOG(fmt, args...) \ do { \ drm_ut_debug_printk(DRM_UT_CORE, NULL, \ -@@ -245,7 +238,6 @@ int drm_err(const char *func, const char *format, ...); +@@ -245,7 +238,6 @@ #else #define DRM_DEBUG_DRIVER(fmt, args...) do { } while (0) #define DRM_DEBUG_KMS(fmt, args...) do { } while (0) @@ -497,7 +496,7 @@ #define DRM_DEBUG(fmt, arg...) do { } while (0) #define DRM_LOG(fmt, arg...) do { } while (0) #define DRM_LOG_KMS(fmt, args...) do { } while (0) -@@ -418,12 +410,6 @@ struct drm_pending_event { +@@ -418,12 +410,6 @@ void (*destroy)(struct drm_pending_event *event); }; @@ -510,7 +509,7 @@ /** File private data */ struct drm_file { int authenticated; -@@ -451,8 +437,6 @@ struct drm_file { +@@ -451,8 +437,6 @@ wait_queue_head_t event_wait; struct list_head event_list; int event_space; @@ -519,7 +518,7 @@ }; /** Wait queue */ -@@ -668,12 +652,6 @@ struct drm_gem_object { +@@ -668,12 +652,6 @@ uint32_t pending_write_domain; void *driver_private; @@ -532,7 +531,7 @@ }; #include "drm_crtc.h" -@@ -912,20 +890,6 @@ struct drm_driver { +@@ -912,20 +890,6 @@ int (*gem_open_object) (struct drm_gem_object *, struct drm_file *); void (*gem_close_object) (struct drm_gem_object *, struct drm_file *); @@ -553,7 +552,7 @@ /* vga arb irq handler */ void (*vgaarb_irq)(struct drm_device *dev, bool state); -@@ -1545,32 +1509,6 @@ extern int drm_vblank_info(struct seq_file *m, void *data); +@@ -1545,32 +1509,6 @@ extern int drm_clients_info(struct seq_file *m, void* data); extern int drm_gem_name_info(struct seq_file *m, void *data); @@ -586,6 +585,3 @@ #if DRM_DEBUG_CODE extern int drm_vma_info(struct seq_file *m, void *data); #endif --- -1.7.10.4 - diff -Nru linux-3.2.46/debian/patches/features/all/drm/Revert-VM-add-vm_mmap-helper-function.patch linux-3.2.46/debian/patches/features/all/drm/Revert-VM-add-vm_mmap-helper-function.patch --- linux-3.2.46/debian/patches/features/all/drm/Revert-VM-add-vm_mmap-helper-function.patch 2013-02-24 03:52:31.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/drm/Revert-VM-add-vm_mmap-helper-function.patch 2013-07-26 19:26:58.000000000 +0000 @@ -14,11 +14,11 @@ drivers/gpu/drm/i915/i915_gem.c | 4 +++- 4 files changed, 14 insertions(+), 7 deletions(-) -diff --git a/drivers/gpu/drm/drm_bufs.c b/drivers/gpu/drm/drm_bufs.c -index 348b367..30372f7 100644 ---- a/drivers/gpu/drm/drm_bufs.c -+++ b/drivers/gpu/drm/drm_bufs.c -@@ -1510,8 +1510,8 @@ int drm_freebufs(struct drm_device *dev, void *data, +Index: linux-3.2.46/drivers/gpu/drm/drm_bufs.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/drm_bufs.c 2013-07-26 19:26:21.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/drm_bufs.c 2013-07-26 19:26:56.000000000 +0000 +@@ -1510,8 +1510,8 @@ * \param arg pointer to a drm_buf_map structure. * \return zero on success or a negative number on failure. * @@ -29,7 +29,7 @@ * offset equal to 0, which drm_mmap() interpretes as PCI buffers and calls * drm_mmap_dma(). */ -@@ -1553,14 +1553,18 @@ int drm_mapbufs(struct drm_device *dev, void *data, +@@ -1553,14 +1553,18 @@ retcode = -EINVAL; goto done; } @@ -50,11 +50,11 @@ } if (virtual > -1024UL) { /* Real error */ -diff --git a/drivers/gpu/drm/exynos/exynos_drm_gem.c b/drivers/gpu/drm/exynos/exynos_drm_gem.c -index 1dffa83..01139c8 100644 ---- a/drivers/gpu/drm/exynos/exynos_drm_gem.c -+++ b/drivers/gpu/drm/exynos/exynos_drm_gem.c -@@ -573,8 +573,10 @@ int exynos_drm_gem_mmap_ioctl(struct drm_device *dev, void *data, +Index: linux-3.2.46/drivers/gpu/drm/exynos/exynos_drm_gem.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/exynos/exynos_drm_gem.c 2013-07-26 19:26:22.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/exynos/exynos_drm_gem.c 2013-07-26 19:26:56.000000000 +0000 +@@ -573,8 +573,10 @@ obj->filp->f_op = &exynos_drm_gem_fops; obj->filp->private_data = obj; @@ -66,11 +66,11 @@ drm_gem_object_unreference_unlocked(obj); -diff --git a/drivers/gpu/drm/i810/i810_dma.c b/drivers/gpu/drm/i810/i810_dma.c -index f920fb5..877a498 100644 ---- a/drivers/gpu/drm/i810/i810_dma.c -+++ b/drivers/gpu/drm/i810/i810_dma.c -@@ -129,7 +129,6 @@ static int i810_map_buffer(struct drm_buf *buf, struct drm_file *file_priv) +Index: linux-3.2.46/drivers/gpu/drm/i810/i810_dma.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/i810/i810_dma.c 2013-07-26 19:26:22.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/i810/i810_dma.c 2013-07-26 19:26:57.000000000 +0000 +@@ -129,7 +129,6 @@ if (buf_priv->currently_mapped == I810_BUF_MAPPED) return -EINVAL; @@ -78,11 +78,11 @@ down_write(¤t->mm->mmap_sem); old_fops = file_priv->filp->f_op; file_priv->filp->f_op = &i810_buffer_fops; -diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c -index 0d1e4b7..0e3c6ac 100644 ---- a/drivers/gpu/drm/i915/i915_gem.c -+++ b/drivers/gpu/drm/i915/i915_gem.c -@@ -1087,9 +1087,11 @@ i915_gem_mmap_ioctl(struct drm_device *dev, void *data, +Index: linux-3.2.46/drivers/gpu/drm/i915/i915_gem.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/i915/i915_gem.c 2013-07-26 19:26:22.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/i915/i915_gem.c 2013-07-26 19:26:57.000000000 +0000 +@@ -1088,9 +1088,11 @@ if (obj == NULL) return -ENOENT; @@ -95,6 +95,3 @@ drm_gem_object_unreference_unlocked(obj); if (IS_ERR((void *)addr)) return addr; --- -1.7.10.4 - diff -Nru linux-3.2.46/debian/patches/features/all/drm/revert-vm-add-vm_munmap-helper-function.patch linux-3.2.46/debian/patches/features/all/drm/revert-vm-add-vm_munmap-helper-function.patch --- linux-3.2.46/debian/patches/features/all/drm/revert-vm-add-vm_munmap-helper-function.patch 2013-02-24 03:52:31.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/drm/revert-vm-add-vm_munmap-helper-function.patch 2013-07-26 19:27:09.000000000 +0000 @@ -7,8 +7,10 @@ bfce281c287a427d0841fadf5d59242757b4e620 'kill mm argument of vm_munmap()' in drivers/gpu/drm/i810/i810_dma.c ---- a/drivers/gpu/drm/i810/i810_dma.c -+++ b/drivers/gpu/drm/i810/i810_dma.c +Index: linux-3.2.46/drivers/gpu/drm/i810/i810_dma.c +=================================================================== +--- linux-3.2.46.orig/drivers/gpu/drm/i810/i810_dma.c 2013-07-26 19:26:57.000000000 +0000 ++++ linux-3.2.46/drivers/gpu/drm/i810/i810_dma.c 2013-07-26 19:27:08.000000000 +0000 @@ -157,8 +157,11 @@ if (buf_priv->currently_mapped != I810_BUF_MAPPED) return -EINVAL; diff -Nru linux-3.2.46/debian/patches/features/all/drm/slab-introduce-kmalloc_array.patch linux-3.2.46/debian/patches/features/all/drm/slab-introduce-kmalloc_array.patch --- linux-3.2.46/debian/patches/features/all/drm/slab-introduce-kmalloc_array.patch 2013-02-24 03:52:31.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/drm/slab-introduce-kmalloc_array.patch 2013-07-26 19:26:21.000000000 +0000 @@ -18,11 +18,11 @@ include/linux/slab.h | 17 ++++++++++++++--- 1 file changed, 14 insertions(+), 3 deletions(-) -diff --git a/include/linux/slab.h b/include/linux/slab.h -index 573c809..a595dce 100644 ---- a/include/linux/slab.h -+++ b/include/linux/slab.h -@@ -190,7 +190,7 @@ size_t ksize(const void *); +Index: linux-3.2.46/include/linux/slab.h +=================================================================== +--- linux-3.2.46.orig/include/linux/slab.h 2013-07-26 18:53:35.000000000 +0000 ++++ linux-3.2.46/include/linux/slab.h 2013-07-26 19:26:20.000000000 +0000 +@@ -190,7 +190,7 @@ #endif /** @@ -31,7 +31,7 @@ * @n: number of elements. * @size: element size. * @flags: the type of memory to allocate. -@@ -240,11 +240,22 @@ size_t ksize(const void *); +@@ -240,11 +240,22 @@ * for general use, and so are not documented here. For a full list of * potential flags, always refer to linux/gfp.h. */ diff -Nru linux-3.2.46/debian/patches/features/all/drm/swiotlb-Expose-swiotlb_nr_tlb-function-to-modules.patch linux-3.2.46/debian/patches/features/all/drm/swiotlb-Expose-swiotlb_nr_tlb-function-to-modules.patch --- linux-3.2.46/debian/patches/features/all/drm/swiotlb-Expose-swiotlb_nr_tlb-function-to-modules.patch 2013-02-24 03:52:31.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/drm/swiotlb-Expose-swiotlb_nr_tlb-function-to-modules.patch 2013-07-26 19:26:19.000000000 +0000 @@ -17,11 +17,11 @@ lib/swiotlb.c | 5 +++-- 3 files changed, 5 insertions(+), 4 deletions(-) -diff --git a/drivers/xen/swiotlb-xen.c b/drivers/xen/swiotlb-xen.c -index 284798a..19e6a20 100644 ---- a/drivers/xen/swiotlb-xen.c -+++ b/drivers/xen/swiotlb-xen.c -@@ -153,7 +153,7 @@ void __init xen_swiotlb_init(int verbose) +Index: linux-3.2.46/drivers/xen/swiotlb-xen.c +=================================================================== +--- linux-3.2.46.orig/drivers/xen/swiotlb-xen.c 2013-07-26 18:53:35.000000000 +0000 ++++ linux-3.2.46/drivers/xen/swiotlb-xen.c 2013-07-26 19:26:18.000000000 +0000 +@@ -153,7 +153,7 @@ char *m = NULL; unsigned int repeat = 3; @@ -30,11 +30,11 @@ if (nr_tbl) xen_io_tlb_nslabs = nr_tbl; else { -diff --git a/include/linux/swiotlb.h b/include/linux/swiotlb.h -index 445702c..e872526 100644 ---- a/include/linux/swiotlb.h -+++ b/include/linux/swiotlb.h -@@ -24,7 +24,7 @@ extern int swiotlb_force; +Index: linux-3.2.46/include/linux/swiotlb.h +=================================================================== +--- linux-3.2.46.orig/include/linux/swiotlb.h 2013-07-26 18:53:35.000000000 +0000 ++++ linux-3.2.46/include/linux/swiotlb.h 2013-07-26 19:26:18.000000000 +0000 +@@ -24,7 +24,7 @@ extern void swiotlb_init(int verbose); extern void swiotlb_init_with_tbl(char *tlb, unsigned long nslabs, int verbose); @@ -43,11 +43,11 @@ /* * Enumeration for sync targets -diff --git a/lib/swiotlb.c b/lib/swiotlb.c -index 99093b3..058935e 100644 ---- a/lib/swiotlb.c -+++ b/lib/swiotlb.c -@@ -110,11 +110,11 @@ setup_io_tlb_npages(char *str) +Index: linux-3.2.46/lib/swiotlb.c +=================================================================== +--- linux-3.2.46.orig/lib/swiotlb.c 2013-07-26 18:53:35.000000000 +0000 ++++ linux-3.2.46/lib/swiotlb.c 2013-07-26 19:26:18.000000000 +0000 +@@ -110,11 +110,11 @@ __setup("swiotlb=", setup_io_tlb_npages); /* make io_tlb_overflow tunable too? */ @@ -61,7 +61,7 @@ /* Note that this doesn't work with highmem page */ static dma_addr_t swiotlb_virt_to_bus(struct device *hwdev, volatile void *address) -@@ -321,6 +321,7 @@ void __init swiotlb_free(void) +@@ -321,6 +321,7 @@ free_bootmem_late(__pa(io_tlb_start), PAGE_ALIGN(io_tlb_nslabs << IO_TLB_SHIFT)); } @@ -69,6 +69,3 @@ } static int is_swiotlb_buffer(phys_addr_t paddr) --- -1.7.10.4 - diff -Nru linux-3.2.46/debian/patches/features/all/ethernet-define-eth_hw_addr_random.patch linux-3.2.46/debian/patches/features/all/ethernet-define-eth_hw_addr_random.patch --- linux-3.2.46/debian/patches/features/all/ethernet-define-eth_hw_addr_random.patch 2013-02-24 03:52:35.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/ethernet-define-eth_hw_addr_random.patch 2013-07-26 19:26:09.000000000 +0000 @@ -9,9 +9,11 @@ can't remove the latter. --- ---- a/include/linux/etherdevice.h -+++ b/include/linux/etherdevice.h -@@ -154,6 +154,21 @@ static inline void dev_hw_addr_random(st +Index: linux-3.2.46/include/linux/etherdevice.h +=================================================================== +--- linux-3.2.46.orig/include/linux/etherdevice.h 2013-07-26 18:53:39.000000000 +0000 ++++ linux-3.2.46/include/linux/etherdevice.h 2013-07-26 19:26:09.000000000 +0000 +@@ -154,6 +154,21 @@ } /** diff -Nru linux-3.2.46/debian/patches/features/all/flow_dissector-use-a-64bit-load-store.patch linux-3.2.46/debian/patches/features/all/flow_dissector-use-a-64bit-load-store.patch --- linux-3.2.46/debian/patches/features/all/flow_dissector-use-a-64bit-load-store.patch 2013-02-24 03:52:42.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/flow_dissector-use-a-64bit-load-store.patch 2013-07-26 19:22:29.000000000 +0000 @@ -42,10 +42,10 @@ Signed-off-by: Eric Dumazet Signed-off-by: David S. Miller -diff --git a/include/net/flow_keys.h b/include/net/flow_keys.h -index e4cb285..80461c1 100644 ---- a/include/net/flow_keys.h -+++ b/include/net/flow_keys.h +Index: linux-3.2.46/include/net/flow_keys.h +=================================================================== +--- linux-3.2.46.orig/include/net/flow_keys.h 2013-07-26 19:22:27.000000000 +0000 ++++ linux-3.2.46/include/net/flow_keys.h 2013-07-26 19:22:28.000000000 +0000 @@ -2,6 +2,7 @@ #define _NET_FLOW_KEYS_H @@ -54,10 +54,10 @@ __be32 src; __be32 dst; union { -diff --git a/net/core/flow_dissector.c b/net/core/flow_dissector.c -index f0516d9..0985b9b 100644 ---- a/net/core/flow_dissector.c -+++ b/net/core/flow_dissector.c +Index: linux-3.2.46/net/core/flow_dissector.c +=================================================================== +--- linux-3.2.46.orig/net/core/flow_dissector.c 2013-07-26 19:22:27.000000000 +0000 ++++ linux-3.2.46/net/core/flow_dissector.c 2013-07-26 19:22:28.000000000 +0000 @@ -8,6 +8,16 @@ #include #include @@ -75,7 +75,7 @@ bool skb_flow_dissect(const struct sk_buff *skb, struct flow_keys *flow) { -@@ -31,8 +41,7 @@ ip: +@@ -31,8 +41,7 @@ ip_proto = 0; else ip_proto = iph->protocol; @@ -85,6 +85,3 @@ nhoff += iph->ihl * 4; break; } --- -1.7.10 - diff -Nru linux-3.2.46/debian/patches/features/all/fs-add-link-restriction-audit-reporting.patch linux-3.2.46/debian/patches/features/all/fs-add-link-restriction-audit-reporting.patch --- linux-3.2.46/debian/patches/features/all/fs-add-link-restriction-audit-reporting.patch 2013-02-24 03:52:42.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/fs-add-link-restriction-audit-reporting.patch 2013-07-26 19:17:54.000000000 +0000 @@ -16,9 +16,11 @@ kernel/audit.c | 21 +++++++++++++++++++++ 3 files changed, 27 insertions(+) ---- a/fs/namei.c -+++ b/fs/namei.c -@@ -666,6 +666,7 @@ static inline int may_follow_link(struct +Index: linux-3.2.46/fs/namei.c +=================================================================== +--- linux-3.2.46.orig/fs/namei.c 2013-07-26 19:17:51.000000000 +0000 ++++ linux-3.2.46/fs/namei.c 2013-07-26 19:17:53.000000000 +0000 +@@ -666,6 +666,7 @@ path_put_conditional(link, nd); path_put(&nd->path); @@ -26,7 +28,7 @@ return -EACCES; } -@@ -734,6 +735,7 @@ static int may_linkat(struct path *link) +@@ -734,6 +735,7 @@ capable(CAP_FOWNER)) return 0; @@ -34,8 +36,10 @@ return -EPERM; } ---- a/include/linux/audit.h -+++ b/include/linux/audit.h +Index: linux-3.2.46/include/linux/audit.h +=================================================================== +--- linux-3.2.46.orig/include/linux/audit.h 2013-07-26 18:56:22.000000000 +0000 ++++ linux-3.2.46/include/linux/audit.h 2013-07-26 19:17:53.000000000 +0000 @@ -129,6 +129,7 @@ #define AUDIT_LAST_KERN_ANOM_MSG 1799 #define AUDIT_ANOM_PROMISCUOUS 1700 /* Device changed promiscuous mode */ @@ -44,7 +48,7 @@ #define AUDIT_INTEGRITY_DATA 1800 /* Data integrity verification */ #define AUDIT_INTEGRITY_METADATA 1801 /* Metadata integrity verification */ #define AUDIT_INTEGRITY_STATUS 1802 /* Integrity enable status */ -@@ -611,6 +612,8 @@ extern void audit_log_d_path(struct +@@ -611,6 +612,8 @@ struct path *path); extern void audit_log_key(struct audit_buffer *ab, char *key); @@ -53,7 +57,7 @@ extern void audit_log_lost(const char *message); #ifdef CONFIG_SECURITY extern void audit_log_secctx(struct audit_buffer *ab, u32 secid); -@@ -640,6 +643,7 @@ extern int audit_enabled; +@@ -640,6 +643,7 @@ #define audit_log_untrustedstring(a,s) do { ; } while (0) #define audit_log_d_path(b, p, d) do { ; } while (0) #define audit_log_key(b, k) do { ; } while (0) @@ -61,9 +65,11 @@ #define audit_log_secctx(b,s) do { ; } while (0) #define audit_enabled 0 #endif ---- a/kernel/audit.c -+++ b/kernel/audit.c -@@ -1449,6 +1449,27 @@ void audit_log_key(struct audit_buffer * +Index: linux-3.2.46/kernel/audit.c +=================================================================== +--- linux-3.2.46.orig/kernel/audit.c 2013-07-26 18:56:22.000000000 +0000 ++++ linux-3.2.46/kernel/audit.c 2013-07-26 19:17:53.000000000 +0000 +@@ -1449,6 +1449,27 @@ } /** diff -Nru linux-3.2.46/debian/patches/features/all/fs-add-link-restrictions.patch linux-3.2.46/debian/patches/features/all/fs-add-link-restrictions.patch --- linux-3.2.46/debian/patches/features/all/fs-add-link-restrictions.patch 2013-02-24 03:52:42.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/fs-add-link-restrictions.patch 2013-07-26 19:17:53.000000000 +0000 @@ -104,9 +104,11 @@ kernel/sysctl.c | 18 +++++++ 4 files changed, 184 insertions(+) ---- a/Documentation/sysctl/fs.txt -+++ b/Documentation/sysctl/fs.txt -@@ -32,6 +32,8 @@ Currently, these files are in /proc/sys/ +Index: linux-3.2.46/Documentation/sysctl/fs.txt +=================================================================== +--- linux-3.2.46.orig/Documentation/sysctl/fs.txt 2013-07-26 18:56:23.000000000 +0000 ++++ linux-3.2.46/Documentation/sysctl/fs.txt 2013-07-26 19:17:51.000000000 +0000 +@@ -32,6 +32,8 @@ - nr_open - overflowuid - overflowgid @@ -115,7 +117,7 @@ - suid_dumpable - super-max - super-nr -@@ -157,6 +159,46 @@ The default is 65534. +@@ -157,6 +159,46 @@ ============================================================== @@ -162,9 +164,11 @@ suid_dumpable: This value can be used to query and set the core dump mode for setuid ---- a/fs/namei.c -+++ b/fs/namei.c -@@ -624,6 +624,119 @@ static inline void put_link(struct namei +Index: linux-3.2.46/fs/namei.c +=================================================================== +--- linux-3.2.46.orig/fs/namei.c 2013-07-26 19:16:53.000000000 +0000 ++++ linux-3.2.46/fs/namei.c 2013-07-26 19:17:51.000000000 +0000 +@@ -624,6 +624,119 @@ path_put(link); } @@ -284,7 +288,7 @@ static __always_inline int follow_link(struct path *link, struct nameidata *nd, void **p) { -@@ -1613,6 +1726,9 @@ static int path_lookupat(int dfd, const +@@ -1613,6 +1726,9 @@ while (err > 0) { void *cookie; struct path link = path; @@ -294,7 +298,7 @@ nd->flags |= LOOKUP_PARENT; err = follow_link(&link, nd, &cookie); if (!err) -@@ -2325,6 +2441,11 @@ static struct file *path_openat(int dfd, +@@ -2325,6 +2441,11 @@ filp = ERR_PTR(-ELOOP); break; } @@ -306,7 +310,7 @@ nd->flags |= LOOKUP_PARENT; nd->flags &= ~(LOOKUP_OPEN|LOOKUP_CREATE|LOOKUP_EXCL); error = follow_link(&link, nd, &cookie); -@@ -2972,6 +3093,9 @@ SYSCALL_DEFINE5(linkat, int, olddfd, con +@@ -2972,6 +3093,9 @@ error = -EXDEV; if (old_path.mnt != new_path.mnt) goto out_dput; @@ -316,9 +320,11 @@ error = mnt_want_write(new_path.mnt); if (error) goto out_dput; ---- a/include/linux/fs.h -+++ b/include/linux/fs.h -@@ -420,6 +420,8 @@ extern unsigned long get_max_files(void) +Index: linux-3.2.46/include/linux/fs.h +=================================================================== +--- linux-3.2.46.orig/include/linux/fs.h 2013-07-26 18:56:23.000000000 +0000 ++++ linux-3.2.46/include/linux/fs.h 2013-07-26 19:17:51.000000000 +0000 +@@ -420,6 +420,8 @@ extern int sysctl_nr_open; extern struct inodes_stat_t inodes_stat; extern int leases_enable, lease_break_time; @@ -327,9 +333,11 @@ struct buffer_head; typedef int (get_block_t)(struct inode *inode, sector_t iblock, ---- a/kernel/sysctl.c -+++ b/kernel/sysctl.c -@@ -1495,6 +1495,24 @@ static struct ctl_table fs_table[] = { +Index: linux-3.2.46/kernel/sysctl.c +=================================================================== +--- linux-3.2.46.orig/kernel/sysctl.c 2013-07-26 18:56:23.000000000 +0000 ++++ linux-3.2.46/kernel/sysctl.c 2013-07-26 19:17:51.000000000 +0000 +@@ -1495,6 +1495,24 @@ #endif #endif { diff -Nru linux-3.2.46/debian/patches/features/all/fs-handle-failed-audit_log_start-properly.patch linux-3.2.46/debian/patches/features/all/fs-handle-failed-audit_log_start-properly.patch --- linux-3.2.46/debian/patches/features/all/fs-handle-failed-audit_log_start-properly.patch 2013-02-24 03:52:42.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/fs-handle-failed-audit_log_start-properly.patch 2013-07-26 19:17:55.000000000 +0000 @@ -15,11 +15,11 @@ kernel/audit.c | 2 ++ 1 file changed, 2 insertions(+) -diff --git a/kernel/audit.c b/kernel/audit.c -index 4d0ceed..40414e9 100644 ---- a/kernel/audit.c -+++ b/kernel/audit.c -@@ -1440,6 +1440,8 @@ void audit_log_link_denied(const char *operation, struct path *link) +Index: linux-3.2.46/kernel/audit.c +=================================================================== +--- linux-3.2.46.orig/kernel/audit.c 2013-07-26 19:17:53.000000000 +0000 ++++ linux-3.2.46/kernel/audit.c 2013-07-26 19:17:54.000000000 +0000 +@@ -1459,6 +1459,8 @@ ab = audit_log_start(current->audit_context, GFP_KERNEL, AUDIT_ANOM_LINK); diff -Nru linux-3.2.46/debian/patches/features/all/fs-prevent-use-after-free-in-auditing-when-symlink-f.patch linux-3.2.46/debian/patches/features/all/fs-prevent-use-after-free-in-auditing-when-symlink-f.patch --- linux-3.2.46/debian/patches/features/all/fs-prevent-use-after-free-in-auditing-when-symlink-f.patch 2013-02-24 03:52:42.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/fs-prevent-use-after-free-in-auditing-when-symlink-f.patch 2013-07-26 19:17:57.000000000 +0000 @@ -15,9 +15,11 @@ fs/namei.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) ---- a/fs/namei.c -+++ b/fs/namei.c -@@ -664,9 +664,9 @@ static inline int may_follow_link(struct +Index: linux-3.2.46/fs/namei.c +=================================================================== +--- linux-3.2.46.orig/fs/namei.c 2013-07-26 19:17:53.000000000 +0000 ++++ linux-3.2.46/fs/namei.c 2013-07-26 19:17:56.000000000 +0000 +@@ -664,9 +664,9 @@ if (parent->i_uid == inode->i_uid) return 0; diff -Nru linux-3.2.46/debian/patches/features/all/hidepid/0001-procfs-parse-mount-options.patch linux-3.2.46/debian/patches/features/all/hidepid/0001-procfs-parse-mount-options.patch --- linux-3.2.46/debian/patches/features/all/hidepid/0001-procfs-parse-mount-options.patch 2013-02-24 03:52:42.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/hidepid/0001-procfs-parse-mount-options.patch 2013-07-26 19:22:46.000000000 +0000 @@ -27,8 +27,10 @@ fs/proc/root.c | 55 ++++++++++++++++++++++++++++++++++++++++++++++++++-- 3 files changed, 64 insertions(+), 2 deletions(-) ---- a/fs/proc/inode.c -+++ b/fs/proc/inode.c +Index: linux-3.2.46/fs/proc/inode.c +=================================================================== +--- linux-3.2.46.orig/fs/proc/inode.c 2013-07-26 18:54:50.000000000 +0000 ++++ linux-3.2.46/fs/proc/inode.c 2013-07-26 19:22:45.000000000 +0000 @@ -7,6 +7,7 @@ #include #include @@ -67,8 +69,10 @@ }; static void __pde_users_dec(struct proc_dir_entry *pde) ---- a/fs/proc/internal.h -+++ b/fs/proc/internal.h +Index: linux-3.2.46/fs/proc/internal.h +=================================================================== +--- linux-3.2.46.orig/fs/proc/internal.h 2013-07-26 18:54:50.000000000 +0000 ++++ linux-3.2.46/fs/proc/internal.h 2013-07-26 19:22:45.000000000 +0000 @@ -117,6 +117,7 @@ int proc_fill_super(struct super_block *); @@ -77,8 +81,10 @@ /* * These are generic /proc routines that use the internal ---- a/fs/proc/root.c -+++ b/fs/proc/root.c +Index: linux-3.2.46/fs/proc/root.c +=================================================================== +--- linux-3.2.46.orig/fs/proc/root.c 2013-07-26 18:54:50.000000000 +0000 ++++ linux-3.2.46/fs/proc/root.c 2013-07-26 19:22:45.000000000 +0000 @@ -18,6 +18,7 @@ #include #include diff -Nru linux-3.2.46/debian/patches/features/all/hidepid/0002-procfs-add-hidepid-and-gid-mount-options.patch linux-3.2.46/debian/patches/features/all/hidepid/0002-procfs-add-hidepid-and-gid-mount-options.patch --- linux-3.2.46/debian/patches/features/all/hidepid/0002-procfs-add-hidepid-and-gid-mount-options.patch 2013-02-24 03:52:42.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/hidepid/0002-procfs-add-hidepid-and-gid-mount-options.patch 2013-07-26 19:22:48.000000000 +0000 @@ -75,8 +75,10 @@ include/linux/pid_namespace.h | 2 ++ 5 files changed, 135 insertions(+), 4 deletions(-) ---- a/Documentation/filesystems/proc.txt -+++ b/Documentation/filesystems/proc.txt +Index: linux-3.2.46/Documentation/filesystems/proc.txt +=================================================================== +--- linux-3.2.46.orig/Documentation/filesystems/proc.txt 2013-07-26 18:54:49.000000000 +0000 ++++ linux-3.2.46/Documentation/filesystems/proc.txt 2013-07-26 19:22:47.000000000 +0000 @@ -41,6 +41,8 @@ 3.5 /proc//mountinfo - Information about mounts 3.6 /proc//comm & /proc//task//comm @@ -127,8 +129,10 @@ +gid= defines a group authorized to learn processes information otherwise +prohibited by hidepid=. If you use some daemon like identd which needs to learn +information about processes information, just add identd to this group. ---- a/fs/proc/base.c -+++ b/fs/proc/base.c +Index: linux-3.2.46/fs/proc/base.c +=================================================================== +--- linux-3.2.46.orig/fs/proc/base.c 2013-07-26 18:54:49.000000000 +0000 ++++ linux-3.2.46/fs/proc/base.c 2013-07-26 19:22:47.000000000 +0000 @@ -574,6 +574,50 @@ return 0; } @@ -255,8 +259,10 @@ }; static const struct file_operations proc_task_operations = { ---- a/fs/proc/inode.c -+++ b/fs/proc/inode.c +Index: linux-3.2.46/fs/proc/inode.c +=================================================================== +--- linux-3.2.46.orig/fs/proc/inode.c 2013-07-26 19:22:45.000000000 +0000 ++++ linux-3.2.46/fs/proc/inode.c 2013-07-26 19:22:47.000000000 +0000 @@ -107,6 +107,14 @@ static int proc_show_options(struct seq_file *seq, struct vfsmount *vfs) @@ -272,8 +278,10 @@ return 0; } ---- a/fs/proc/root.c -+++ b/fs/proc/root.c +Index: linux-3.2.46/fs/proc/root.c +=================================================================== +--- linux-3.2.46.orig/fs/proc/root.c 2013-07-26 19:22:45.000000000 +0000 ++++ linux-3.2.46/fs/proc/root.c 2013-07-26 19:22:47.000000000 +0000 @@ -38,10 +38,12 @@ } @@ -319,8 +327,10 @@ default: pr_err("proc: unrecognized mount option \"%s\" " "or missing value\n", p); ---- a/include/linux/pid_namespace.h -+++ b/include/linux/pid_namespace.h +Index: linux-3.2.46/include/linux/pid_namespace.h +=================================================================== +--- linux-3.2.46.orig/include/linux/pid_namespace.h 2013-07-26 18:54:49.000000000 +0000 ++++ linux-3.2.46/include/linux/pid_namespace.h 2013-07-26 19:22:47.000000000 +0000 @@ -30,6 +30,8 @@ #ifdef CONFIG_BSD_PROCESS_ACCT struct bsd_acct_struct *bacct; diff -Nru linux-3.2.46/debian/patches/features/all/hidepid/0003-proc-fix-null-pointer-deref-in-proc_pid_permission.patch linux-3.2.46/debian/patches/features/all/hidepid/0003-proc-fix-null-pointer-deref-in-proc_pid_permission.patch --- linux-3.2.46/debian/patches/features/all/hidepid/0003-proc-fix-null-pointer-deref-in-proc_pid_permission.patch 2013-02-24 03:52:42.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/hidepid/0003-proc-fix-null-pointer-deref-in-proc_pid_permission.patch 2013-07-26 19:22:49.000000000 +0000 @@ -27,11 +27,11 @@ fs/proc/base.c | 2 ++ 1 file changed, 2 insertions(+) -diff --git a/fs/proc/base.c b/fs/proc/base.c -index 8173dfd..5485a53 100644 ---- a/fs/proc/base.c -+++ b/fs/proc/base.c -@@ -654,6 +654,8 @@ static int proc_pid_permission(struct inode *inode, int mask) +Index: linux-3.2.46/fs/proc/base.c +=================================================================== +--- linux-3.2.46.orig/fs/proc/base.c 2013-07-26 19:22:47.000000000 +0000 ++++ linux-3.2.46/fs/proc/base.c 2013-07-26 19:22:48.000000000 +0000 +@@ -597,6 +597,8 @@ bool has_perms; task = get_proc_task(inode); diff -Nru linux-3.2.46/debian/patches/features/all/hidepid/0004-proc-fix-mount-t-proc-o-AAA.patch linux-3.2.46/debian/patches/features/all/hidepid/0004-proc-fix-mount-t-proc-o-AAA.patch --- linux-3.2.46/debian/patches/features/all/hidepid/0004-proc-fix-mount-t-proc-o-AAA.patch 2013-02-24 03:52:42.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/hidepid/0004-proc-fix-mount-t-proc-o-AAA.patch 2013-07-26 19:22:50.000000000 +0000 @@ -25,11 +25,11 @@ fs/proc/root.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) -diff --git a/fs/proc/root.c b/fs/proc/root.c -index 46a15d8..eed44bf 100644 ---- a/fs/proc/root.c -+++ b/fs/proc/root.c -@@ -115,12 +115,13 @@ static struct dentry *proc_mount(struct file_system_type *fs_type, +Index: linux-3.2.46/fs/proc/root.c +=================================================================== +--- linux-3.2.46.orig/fs/proc/root.c 2013-07-26 19:22:47.000000000 +0000 ++++ linux-3.2.46/fs/proc/root.c 2013-07-26 19:22:49.000000000 +0000 +@@ -115,12 +115,13 @@ if (IS_ERR(sb)) return ERR_CAST(sb); diff -Nru linux-3.2.46/debian/patches/features/all/hwmon-it87-Add-IT8728F-support.patch linux-3.2.46/debian/patches/features/all/hwmon-it87-Add-IT8728F-support.patch --- linux-3.2.46/debian/patches/features/all/hwmon-it87-Add-IT8728F-support.patch 2013-02-24 03:52:42.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/hwmon-it87-Add-IT8728F-support.patch 2013-07-26 19:17:51.000000000 +0000 @@ -17,11 +17,11 @@ drivers/hwmon/it87.c | 61 ++++++++++++++++++++++++++++++++++----------- 3 files changed, 58 insertions(+), 20 deletions(-) -diff --git a/Documentation/hwmon/it87 b/Documentation/hwmon/it87 -index 6f496a5..23b7def 100644 ---- a/Documentation/hwmon/it87 -+++ b/Documentation/hwmon/it87 -@@ -26,6 +26,10 @@ Supported chips: +Index: linux-3.2.46/Documentation/hwmon/it87 +=================================================================== +--- linux-3.2.46.orig/Documentation/hwmon/it87 2013-07-26 18:56:23.000000000 +0000 ++++ linux-3.2.46/Documentation/hwmon/it87 2013-07-26 19:17:50.000000000 +0000 +@@ -26,6 +26,10 @@ Prefix: 'it8721' Addresses scanned: from Super I/O config space (8 I/O ports) Datasheet: Not publicly available @@ -32,7 +32,7 @@ * SiS950 [clone of IT8705F] Prefix: 'it87' Addresses scanned: from Super I/O config space (8 I/O ports) -@@ -71,7 +75,7 @@ Description +@@ -71,7 +75,7 @@ ----------- This driver implements support for the IT8705F, IT8712F, IT8716F, @@ -41,7 +41,7 @@ These chips are 'Super I/O chips', supporting floppy disks, infrared ports, joysticks and other miscellaneous stuff. For hardware monitoring, they -@@ -105,6 +109,9 @@ The IT8726F is just bit enhanced IT8716F with additional hardware +@@ -105,6 +109,9 @@ for AMD power sequencing. Therefore the chip will appear as IT8716F to userspace applications. @@ -51,7 +51,7 @@ Temperatures are measured in degrees Celsius. An alarm is triggered once when the Overtemperature Shutdown limit is crossed. -@@ -121,8 +128,8 @@ alarm is triggered if the voltage has crossed a programmable minimum or +@@ -121,8 +128,8 @@ maximum limit. Note that minimum in this case always means 'closest to zero'; this is important for negative voltage measurements. All voltage inputs can measure voltages between 0 and 4.08 volts, with a resolution of @@ -62,11 +62,11 @@ On the IT8721F/IT8758E, some voltage inputs are internal and scaled inside the chip (in7, in8 and optionally in3). The driver handles this transparently -diff --git a/drivers/hwmon/Kconfig b/drivers/hwmon/Kconfig -index f468bbb..0226040 100644 ---- a/drivers/hwmon/Kconfig -+++ b/drivers/hwmon/Kconfig -@@ -474,8 +474,8 @@ config SENSORS_IT87 +Index: linux-3.2.46/drivers/hwmon/Kconfig +=================================================================== +--- linux-3.2.46.orig/drivers/hwmon/Kconfig 2013-07-26 18:56:23.000000000 +0000 ++++ linux-3.2.46/drivers/hwmon/Kconfig 2013-07-26 19:17:50.000000000 +0000 +@@ -474,8 +474,8 @@ select HWMON_VID help If you say yes here you get support for ITE IT8705F, IT8712F, @@ -77,10 +77,10 @@ This driver can also be built as a module. If so, the module will be called it87. -diff --git a/drivers/hwmon/it87.c b/drivers/hwmon/it87.c -index 603ef2a..0054d6f 100644 ---- a/drivers/hwmon/it87.c -+++ b/drivers/hwmon/it87.c +Index: linux-3.2.46/drivers/hwmon/it87.c +=================================================================== +--- linux-3.2.46.orig/drivers/hwmon/it87.c 2013-07-26 18:56:23.000000000 +0000 ++++ linux-3.2.46/drivers/hwmon/it87.c 2013-07-26 19:17:50.000000000 +0000 @@ -17,6 +17,7 @@ * IT8720F Super I/O chip w/LPC interface * IT8721F Super I/O chip w/LPC interface @@ -98,7 +98,7 @@ static unsigned short force_id; module_param(force_id, ushort, 0); -@@ -135,6 +136,7 @@ static inline void superio_exit(void) +@@ -135,6 +136,7 @@ #define IT8720F_DEVID 0x8720 #define IT8721F_DEVID 0x8721 #define IT8726F_DEVID 0x8726 @@ -106,7 +106,7 @@ #define IT87_ACT_REG 0x30 #define IT87_BASE_REG 0x60 -@@ -274,11 +276,31 @@ struct it87_data { +@@ -274,11 +276,31 @@ s8 auto_temp[3][5]; /* [nr][0] is point1_temp_hyst */ }; @@ -139,7 +139,7 @@ if (data->in_scaled & (1 << nr)) lsb = 24; else -@@ -292,7 +314,7 @@ static u8 in_to_reg(const struct it87_data *data, int nr, long val) +@@ -292,7 +314,7 @@ static int in_from_reg(const struct it87_data *data, int nr, int val) { @@ -148,7 +148,7 @@ if (data->in_scaled & (1 << nr)) return val * 24; else -@@ -329,7 +351,7 @@ static inline u16 FAN16_TO_REG(long rpm) +@@ -329,7 +351,7 @@ static u8 pwm_to_reg(const struct it87_data *data, long val) { @@ -157,7 +157,7 @@ return val; else return val >> 1; -@@ -337,7 +359,7 @@ static u8 pwm_to_reg(const struct it87_data *data, long val) +@@ -337,7 +359,7 @@ static int pwm_from_reg(const struct it87_data *data, u8 reg) { @@ -166,7 +166,7 @@ return reg; else return (reg & 0x7f) << 1; -@@ -374,7 +396,8 @@ static inline int has_16bit_fans(const struct it87_data *data) +@@ -374,7 +396,8 @@ || data->type == it8716 || data->type == it8718 || data->type == it8720 @@ -176,7 +176,7 @@ } static inline int has_old_autopwm(const struct it87_data *data) -@@ -842,7 +865,7 @@ static ssize_t set_pwm_enable(struct device *dev, +@@ -842,7 +865,7 @@ data->fan_main_ctrl); } else { if (val == 1) /* Manual mode */ @@ -185,7 +185,7 @@ data->pwm_temp_map[nr] : data->pwm_duty[nr]; else /* Automatic mode */ -@@ -870,7 +893,7 @@ static ssize_t set_pwm(struct device *dev, struct device_attribute *attr, +@@ -870,7 +893,7 @@ return -EINVAL; mutex_lock(&data->update_lock); @@ -194,7 +194,7 @@ /* If we are in automatic mode, the PWM duty cycle register * is read-only so we can't write the value */ if (data->pwm_ctrl[nr] & 0x80) { -@@ -1311,8 +1334,8 @@ static ssize_t show_label(struct device *dev, struct device_attribute *attr, +@@ -1311,8 +1334,8 @@ struct it87_data *data = dev_get_drvdata(dev); int nr = to_sensor_dev_attr(attr)->index; @@ -205,7 +205,7 @@ } static SENSOR_DEVICE_ATTR(in3_label, S_IRUGO, show_label, NULL, 0); static SENSOR_DEVICE_ATTR(in7_label, S_IRUGO, show_label, NULL, 1); -@@ -1605,6 +1628,9 @@ static int __init it87_find(unsigned short *address, +@@ -1605,6 +1628,9 @@ case IT8721F_DEVID: sio_data->type = it8721; break; @@ -215,7 +215,7 @@ case 0xffff: /* No device at all */ goto exit; default: -@@ -1646,8 +1672,11 @@ static int __init it87_find(unsigned short *address, +@@ -1646,8 +1672,11 @@ superio_select(GPIO); reg = superio_inb(IT87_SIO_GPIO3_REG); @@ -229,7 +229,7 @@ sio_data->skip_vid = 1; } else { /* We need at least 4 VID pins */ -@@ -1692,7 +1721,8 @@ static int __init it87_find(unsigned short *address, +@@ -1692,7 +1721,8 @@ } if (reg & (1 << 0)) sio_data->internal |= (1 << 0); @@ -239,7 +239,7 @@ sio_data->internal |= (1 << 1); sio_data->beep_pin = superio_inb(IT87_SIO_BEEP_PIN_REG) & 0x3f; -@@ -1770,6 +1800,7 @@ static int __devinit it87_probe(struct platform_device *pdev) +@@ -1770,6 +1800,7 @@ "it8718", "it8720", "it8721", @@ -247,7 +247,7 @@ }; res = platform_get_resource(pdev, IORESOURCE_IO, 0); -@@ -1807,7 +1838,7 @@ static int __devinit it87_probe(struct platform_device *pdev) +@@ -1807,7 +1838,7 @@ enable_pwm_interface = it87_check_pwm(dev); /* Starting with IT8721F, we handle scaling of internal voltages */ @@ -256,7 +256,7 @@ if (sio_data->internal & (1 << 0)) data->in_scaled |= (1 << 3); /* in3 is AVCC */ if (sio_data->internal & (1 << 1)) -@@ -2093,7 +2124,7 @@ static void __devinit it87_init_device(struct platform_device *pdev) +@@ -2093,7 +2124,7 @@ static void it87_update_pwm_ctrl(struct it87_data *data, int nr) { data->pwm_ctrl[nr] = it87_read_value(data, IT87_REG_PWM(nr)); @@ -265,6 +265,3 @@ data->pwm_temp_map[nr] = data->pwm_ctrl[nr] & 0x03; data->pwm_duty[nr] = it87_read_value(data, IT87_REG_PWM_DUTY(nr)); --- -1.7.9 - diff -Nru linux-3.2.46/debian/patches/features/all/I2C-Add-helper-macro-for-i2c_driver-boilerplate.patch linux-3.2.46/debian/patches/features/all/I2C-Add-helper-macro-for-i2c_driver-boilerplate.patch --- linux-3.2.46/debian/patches/features/all/I2C-Add-helper-macro-for-i2c_driver-boilerplate.patch 2013-02-24 03:52:42.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/I2C-Add-helper-macro-for-i2c_driver-boilerplate.patch 2013-07-26 19:25:47.000000000 +0000 @@ -20,11 +20,11 @@ include/linux/i2c.h | 13 +++++++++++++ 1 file changed, 13 insertions(+) -diff --git a/include/linux/i2c.h b/include/linux/i2c.h -index a81bf6d..7e92854 100644 ---- a/include/linux/i2c.h -+++ b/include/linux/i2c.h -@@ -485,6 +485,19 @@ static inline int i2c_adapter_id(struct i2c_adapter *adap) +Index: linux-3.2.46/include/linux/i2c.h +=================================================================== +--- linux-3.2.46.orig/include/linux/i2c.h 2013-07-26 18:53:46.000000000 +0000 ++++ linux-3.2.46/include/linux/i2c.h 2013-07-26 19:25:46.000000000 +0000 +@@ -482,6 +482,19 @@ { return adap->nr; } diff -Nru linux-3.2.46/debian/patches/features/all/iguanair/0001-media-Add-support-for-the-IguanaWorks-USB-IR-Transce.patch linux-3.2.46/debian/patches/features/all/iguanair/0001-media-Add-support-for-the-IguanaWorks-USB-IR-Transce.patch --- linux-3.2.46/debian/patches/features/all/iguanair/0001-media-Add-support-for-the-IguanaWorks-USB-IR-Transce.patch 2013-02-24 03:52:42.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/iguanair/0001-media-Add-support-for-the-IguanaWorks-USB-IR-Transce.patch 2013-07-26 19:25:51.000000000 +0000 @@ -13,9 +13,11 @@ 3 files changed, 651 insertions(+) create mode 100644 drivers/media/rc/iguanair.c ---- a/drivers/media/rc/Kconfig -+++ b/drivers/media/rc/Kconfig -@@ -243,6 +243,17 @@ config IR_WINBOND_CIR +Index: linux-3.2.46/drivers/media/rc/Kconfig +=================================================================== +--- linux-3.2.46.orig/drivers/media/rc/Kconfig 2013-07-26 18:53:44.000000000 +0000 ++++ linux-3.2.46/drivers/media/rc/Kconfig 2013-07-26 19:25:50.000000000 +0000 +@@ -243,6 +243,17 @@ To compile this driver as a module, choose M here: the module will be called winbond_cir. @@ -33,15 +35,19 @@ config RC_LOOPBACK tristate "Remote Control Loopback Driver" depends on RC_CORE ---- a/drivers/media/rc/Makefile -+++ b/drivers/media/rc/Makefile -@@ -25,3 +25,4 @@ obj-$(CONFIG_IR_REDRAT3) += redrat3.o +Index: linux-3.2.46/drivers/media/rc/Makefile +=================================================================== +--- linux-3.2.46.orig/drivers/media/rc/Makefile 2013-07-26 18:53:44.000000000 +0000 ++++ linux-3.2.46/drivers/media/rc/Makefile 2013-07-26 19:25:50.000000000 +0000 +@@ -25,3 +25,4 @@ obj-$(CONFIG_IR_STREAMZAP) += streamzap.o obj-$(CONFIG_IR_WINBOND_CIR) += winbond-cir.o obj-$(CONFIG_RC_LOOPBACK) += rc-loopback.o +obj-$(CONFIG_IR_IGUANA) += iguanair.o ---- /dev/null -+++ b/drivers/media/rc/iguanair.c +Index: linux-3.2.46/drivers/media/rc/iguanair.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/media/rc/iguanair.c 2013-07-26 19:25:50.000000000 +0000 @@ -0,0 +1,639 @@ +/* + * IguanaWorks USB IR Transceiver support diff -Nru linux-3.2.46/debian/patches/features/all/iguanair/0002-media-iguanair-reuse-existing-urb-callback-for-comma.patch linux-3.2.46/debian/patches/features/all/iguanair/0002-media-iguanair-reuse-existing-urb-callback-for-comma.patch --- linux-3.2.46/debian/patches/features/all/iguanair/0002-media-iguanair-reuse-existing-urb-callback-for-comma.patch 2013-02-24 03:52:42.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/iguanair/0002-media-iguanair-reuse-existing-urb-callback-for-comma.patch 2013-07-26 19:25:52.000000000 +0000 @@ -14,11 +14,11 @@ drivers/media/rc/iguanair.c | 147 +++++++++++++++++-------------------------- 1 file changed, 56 insertions(+), 91 deletions(-) -diff --git a/drivers/media/rc/iguanair.c b/drivers/media/rc/iguanair.c -index 5e2eaf8..bdd526d 100644 ---- a/drivers/media/rc/iguanair.c -+++ b/drivers/media/rc/iguanair.c -@@ -35,7 +35,7 @@ struct iguanair { +Index: linux-3.2.46/drivers/media/rc/iguanair.c +=================================================================== +--- linux-3.2.46.orig/drivers/media/rc/iguanair.c 2013-07-26 19:25:50.000000000 +0000 ++++ linux-3.2.46/drivers/media/rc/iguanair.c 2013-07-26 19:25:51.000000000 +0000 +@@ -35,7 +35,7 @@ struct device *dev; struct usb_device *udev; @@ -27,7 +27,7 @@ uint8_t bufsize; uint8_t version[2]; -@@ -82,11 +82,6 @@ struct packet { +@@ -82,11 +82,6 @@ uint8_t cmd; }; @@ -39,7 +39,7 @@ struct send_packet { struct packet header; uint8_t length; -@@ -100,6 +95,26 @@ static void process_ir_data(struct iguanair *ir, unsigned len) +@@ -100,6 +95,26 @@ { if (len >= 4 && ir->buf_in[0] == 0 && ir->buf_in[1] == 0) { switch (ir->buf_in[3]) { @@ -66,7 +66,7 @@ case CMD_TX_OVERFLOW: ir->tx_overflow = true; case CMD_RECEIVER_OFF: -@@ -169,31 +184,22 @@ static void iguanair_rx(struct urb *urb) +@@ -169,31 +184,22 @@ usb_submit_urb(urb, GFP_ATOMIC); } @@ -108,7 +108,7 @@ return rc; } -@@ -201,66 +207,40 @@ static int iguanair_send(struct iguanair *ir, void *data, unsigned size, +@@ -201,66 +207,40 @@ static int iguanair_get_features(struct iguanair *ir) { struct packet packet; @@ -179,7 +179,7 @@ out: return rc; } -@@ -269,17 +249,8 @@ static int iguanair_receiver(struct iguanair *ir, bool enable) +@@ -269,17 +249,8 @@ { struct packet packet = { 0, DIR_OUT, enable ? CMD_RECEIVER_ON : CMD_RECEIVER_OFF }; @@ -190,15 +190,15 @@ - rc = iguanair_send(ir, &packet, sizeof(packet), NULL, NULL); - if (rc) - return rc; -- -- wait_for_completion_timeout(&ir->completion, TIMEOUT); +- wait_for_completion_timeout(&ir->completion, TIMEOUT); +- - return 0; + return iguanair_send(ir, &packet, sizeof(packet)); } /* -@@ -406,17 +377,10 @@ static int iguanair_tx(struct rc_dev *dev, unsigned *txbuf, unsigned count) +@@ -406,17 +377,10 @@ ir->tx_overflow = false; @@ -219,7 +219,7 @@ if (ir->receiver_on) { if (iguanair_receiver(ir, true)) -@@ -437,8 +401,6 @@ static int iguanair_open(struct rc_dev *rdev) +@@ -437,8 +401,6 @@ mutex_lock(&ir->lock); @@ -228,7 +228,7 @@ BUG_ON(ir->receiver_on); rc = iguanair_receiver(ir, true); -@@ -462,8 +424,6 @@ static void iguanair_close(struct rc_dev *rdev) +@@ -462,8 +424,6 @@ if (rc) dev_warn(ir->dev, "failed to disable receiver: %d\n", rc); @@ -237,7 +237,7 @@ mutex_unlock(&ir->lock); } -@@ -473,7 +433,7 @@ static int __devinit iguanair_probe(struct usb_interface *intf, +@@ -473,7 +433,7 @@ struct usb_device *udev = interface_to_usbdev(intf); struct iguanair *ir; struct rc_dev *rc; @@ -246,7 +246,7 @@ struct usb_host_interface *idesc; ir = kzalloc(sizeof(*ir), GFP_KERNEL); -@@ -483,7 +443,7 @@ static int __devinit iguanair_probe(struct usb_interface *intf, +@@ -483,7 +443,7 @@ goto out; } @@ -255,7 +255,7 @@ &ir->dma_in); ir->urb_in = usb_alloc_urb(0, GFP_KERNEL); -@@ -502,25 +462,28 @@ static int __devinit iguanair_probe(struct usb_interface *intf, +@@ -502,25 +462,28 @@ ir->rc = rc; ir->dev = &intf->dev; ir->udev = udev; @@ -293,7 +293,7 @@ snprintf(ir->name, sizeof(ir->name), "IguanaWorks USB IR Transceiver version %d.%d", ir->version[0], ir->version[1]); -@@ -547,7 +510,7 @@ static int __devinit iguanair_probe(struct usb_interface *intf, +@@ -547,7 +510,7 @@ ret = rc_register_device(rc); if (ret < 0) { dev_err(&intf->dev, "failed to register rc device %d", ret); @@ -302,7 +302,7 @@ } usb_set_intfdata(intf, ir); -@@ -555,6 +518,8 @@ static int __devinit iguanair_probe(struct usb_interface *intf, +@@ -555,6 +518,8 @@ dev_info(&intf->dev, "Registered %s", ir->name); return 0; diff -Nru linux-3.2.46/debian/patches/features/all/iguanair/0003-media-iguanair-ignore-unsupported-firmware-versions.patch linux-3.2.46/debian/patches/features/all/iguanair/0003-media-iguanair-ignore-unsupported-firmware-versions.patch --- linux-3.2.46/debian/patches/features/all/iguanair/0003-media-iguanair-ignore-unsupported-firmware-versions.patch 2013-02-24 03:52:42.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/iguanair/0003-media-iguanair-ignore-unsupported-firmware-versions.patch 2013-07-26 19:25:53.000000000 +0000 @@ -14,11 +14,11 @@ drivers/media/rc/iguanair.c | 21 +++++++++++---------- 2 files changed, 17 insertions(+), 12 deletions(-) -diff --git a/drivers/media/rc/Kconfig b/drivers/media/rc/Kconfig -index 5180390..2e91e66 100644 ---- a/drivers/media/rc/Kconfig -+++ b/drivers/media/rc/Kconfig -@@ -264,8 +264,12 @@ config IR_IGUANA +Index: linux-3.2.46/drivers/media/rc/Kconfig +=================================================================== +--- linux-3.2.46.orig/drivers/media/rc/Kconfig 2013-07-26 19:25:50.000000000 +0000 ++++ linux-3.2.46/drivers/media/rc/Kconfig 2013-07-26 19:25:52.000000000 +0000 +@@ -248,8 +248,12 @@ depends on RC_CORE select USB ---help--- @@ -33,11 +33,11 @@ To compile this driver as a module, choose M here: the module will be called iguanair. -diff --git a/drivers/media/rc/iguanair.c b/drivers/media/rc/iguanair.c -index bdd526d..5885400 100644 ---- a/drivers/media/rc/iguanair.c -+++ b/drivers/media/rc/iguanair.c -@@ -36,8 +36,8 @@ struct iguanair { +Index: linux-3.2.46/drivers/media/rc/iguanair.c +=================================================================== +--- linux-3.2.46.orig/drivers/media/rc/iguanair.c 2013-07-26 19:25:51.000000000 +0000 ++++ linux-3.2.46/drivers/media/rc/iguanair.c 2013-07-26 19:25:53.000000000 +0000 +@@ -36,8 +36,8 @@ struct usb_device *udev; int pipe_out; @@ -47,7 +47,7 @@ struct mutex lock; -@@ -97,8 +97,8 @@ static void process_ir_data(struct iguanair *ir, unsigned len) +@@ -97,8 +97,8 @@ switch (ir->buf_in[3]) { case CMD_GET_VERSION: if (len == 6) { @@ -58,7 +58,7 @@ complete(&ir->completion); } break; -@@ -110,8 +110,7 @@ static void process_ir_data(struct iguanair *ir, unsigned len) +@@ -110,8 +110,7 @@ break; case CMD_GET_FEATURES: if (len > 5) { @@ -68,7 +68,7 @@ complete(&ir->completion); } break; -@@ -219,6 +218,12 @@ static int iguanair_get_features(struct iguanair *ir) +@@ -219,6 +218,12 @@ goto out; } @@ -81,7 +81,7 @@ ir->bufsize = 150; ir->cycle_overhead = 65; -@@ -230,9 +235,6 @@ static int iguanair_get_features(struct iguanair *ir) +@@ -230,9 +235,6 @@ goto out; } @@ -91,7 +91,7 @@ packet.cmd = CMD_GET_FEATURES; rc = iguanair_send(ir, &packet, sizeof(packet)); -@@ -485,8 +487,7 @@ static int __devinit iguanair_probe(struct usb_interface *intf, +@@ -485,8 +487,7 @@ goto out2; snprintf(ir->name, sizeof(ir->name), diff -Nru linux-3.2.46/debian/patches/features/all/iguanair/0004-media-iguanair-support-suspend-and-resume.patch linux-3.2.46/debian/patches/features/all/iguanair/0004-media-iguanair-support-suspend-and-resume.patch --- linux-3.2.46/debian/patches/features/all/iguanair/0004-media-iguanair-support-suspend-and-resume.patch 2013-02-24 03:52:42.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/iguanair/0004-media-iguanair-support-suspend-and-resume.patch 2013-07-26 19:25:55.000000000 +0000 @@ -12,11 +12,11 @@ drivers/media/rc/iguanair.c | 21 ++++++++++++++------- 1 file changed, 14 insertions(+), 7 deletions(-) -diff --git a/drivers/media/rc/iguanair.c b/drivers/media/rc/iguanair.c -index 5885400..f1c5846 100644 ---- a/drivers/media/rc/iguanair.c -+++ b/drivers/media/rc/iguanair.c -@@ -155,6 +155,7 @@ static void process_ir_data(struct iguanair *ir, unsigned len) +Index: linux-3.2.46/drivers/media/rc/iguanair.c +=================================================================== +--- linux-3.2.46.orig/drivers/media/rc/iguanair.c 2013-07-26 19:25:53.000000000 +0000 ++++ linux-3.2.46/drivers/media/rc/iguanair.c 2013-07-26 19:25:54.000000000 +0000 +@@ -155,6 +155,7 @@ static void iguanair_rx(struct urb *urb) { struct iguanair *ir; @@ -24,7 +24,7 @@ if (!urb) return; -@@ -180,7 +181,9 @@ static void iguanair_rx(struct urb *urb) +@@ -180,7 +181,9 @@ break; } @@ -35,7 +35,7 @@ } static int iguanair_send(struct iguanair *ir, void *data, unsigned size) -@@ -423,7 +426,7 @@ static void iguanair_close(struct rc_dev *rdev) +@@ -423,7 +426,7 @@ rc = iguanair_receiver(ir, false); ir->receiver_on = false; @@ -44,7 +44,7 @@ dev_warn(ir->dev, "failed to disable receiver: %d\n", rc); mutex_unlock(&ir->lock); -@@ -516,8 +519,6 @@ static int __devinit iguanair_probe(struct usb_interface *intf, +@@ -516,8 +519,6 @@ usb_set_intfdata(intf, ir); @@ -53,7 +53,7 @@ return 0; out2: usb_kill_urb(ir->urb_in); -@@ -536,12 +537,11 @@ static void __devexit iguanair_disconnect(struct usb_interface *intf) +@@ -536,12 +537,11 @@ { struct iguanair *ir = usb_get_intfdata(intf); @@ -67,7 +67,7 @@ kfree(ir); } -@@ -558,6 +558,8 @@ static int iguanair_suspend(struct usb_interface *intf, pm_message_t message) +@@ -558,6 +558,8 @@ dev_warn(ir->dev, "failed to disable receiver for suspend\n"); } @@ -76,7 +76,7 @@ mutex_unlock(&ir->lock); return rc; -@@ -570,6 +572,10 @@ static int iguanair_resume(struct usb_interface *intf) +@@ -570,6 +572,10 @@ mutex_lock(&ir->lock); @@ -87,7 +87,7 @@ if (ir->receiver_on) { rc = iguanair_receiver(ir, true); if (rc) -@@ -593,7 +599,8 @@ static struct usb_driver iguanair_driver = { +@@ -593,7 +599,8 @@ .suspend = iguanair_suspend, .resume = iguanair_resume, .reset_resume = iguanair_resume, diff -Nru linux-3.2.46/debian/patches/features/all/iguanair/0005-media-iguanair-fix-return-value-for-transmit.patch linux-3.2.46/debian/patches/features/all/iguanair/0005-media-iguanair-fix-return-value-for-transmit.patch --- linux-3.2.46/debian/patches/features/all/iguanair/0005-media-iguanair-fix-return-value-for-transmit.patch 2013-02-24 03:52:42.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/iguanair/0005-media-iguanair-fix-return-value-for-transmit.patch 2013-07-26 19:25:56.000000000 +0000 @@ -12,11 +12,11 @@ drivers/media/rc/iguanair.c | 30 ++++++++++++++++++------------ 1 file changed, 18 insertions(+), 12 deletions(-) -diff --git a/drivers/media/rc/iguanair.c b/drivers/media/rc/iguanair.c -index f1c5846..6817258 100644 ---- a/drivers/media/rc/iguanair.c -+++ b/drivers/media/rc/iguanair.c -@@ -327,7 +327,7 @@ static int iguanair_tx(struct rc_dev *dev, unsigned *txbuf, unsigned count) +Index: linux-3.2.46/drivers/media/rc/iguanair.c +=================================================================== +--- linux-3.2.46.orig/drivers/media/rc/iguanair.c 2013-07-26 19:25:54.000000000 +0000 ++++ linux-3.2.46/drivers/media/rc/iguanair.c 2013-07-26 19:25:55.000000000 +0000 +@@ -327,7 +327,7 @@ { struct iguanair *ir = dev->priv; uint8_t space, *payload; @@ -25,7 +25,7 @@ struct send_packet *packet; mutex_lock(&ir->lock); -@@ -335,17 +335,22 @@ static int iguanair_tx(struct rc_dev *dev, unsigned *txbuf, unsigned count) +@@ -335,17 +335,22 @@ /* convert from us to carrier periods */ for (i = size = 0; i < count; i++) { txbuf[i] = DIV_ROUND_CLOSEST(txbuf[i] * ir->carrier, 1000000); @@ -54,7 +54,7 @@ goto out; } -@@ -376,7 +381,7 @@ static int iguanair_tx(struct rc_dev *dev, unsigned *txbuf, unsigned count) +@@ -376,7 +381,7 @@ rc = iguanair_receiver(ir, false); if (rc) { dev_warn(ir->dev, "disable receiver before transmit failed\n"); @@ -63,7 +63,7 @@ } } -@@ -392,11 +397,12 @@ static int iguanair_tx(struct rc_dev *dev, unsigned *txbuf, unsigned count) +@@ -392,11 +397,12 @@ dev_warn(ir->dev, "re-enable receiver after transmit failed\n"); } @@ -78,7 +78,7 @@ } static int iguanair_open(struct rc_dev *rdev) -@@ -444,7 +450,7 @@ static int __devinit iguanair_probe(struct usb_interface *intf, +@@ -444,7 +450,7 @@ ir = kzalloc(sizeof(*ir), GFP_KERNEL); rc = rc_allocate_device(); if (!ir || !rc) { @@ -87,7 +87,7 @@ goto out; } -@@ -453,7 +459,7 @@ static int __devinit iguanair_probe(struct usb_interface *intf, +@@ -453,7 +459,7 @@ ir->urb_in = usb_alloc_urb(0, GFP_KERNEL); if (!ir->buf_in || !ir->urb_in) { diff -Nru linux-3.2.46/debian/patches/features/all/iguanair/0006-media-iguanair-reset-the-IR-state-after-rx-overflow-.patch linux-3.2.46/debian/patches/features/all/iguanair/0006-media-iguanair-reset-the-IR-state-after-rx-overflow-.patch --- linux-3.2.46/debian/patches/features/all/iguanair/0006-media-iguanair-reset-the-IR-state-after-rx-overflow-.patch 2013-02-24 03:52:42.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/iguanair/0006-media-iguanair-reset-the-IR-state-after-rx-overflow-.patch 2013-07-26 19:25:57.000000000 +0000 @@ -11,11 +11,11 @@ drivers/media/rc/iguanair.c | 4 ++++ 1 file changed, 4 insertions(+) -diff --git a/drivers/media/rc/iguanair.c b/drivers/media/rc/iguanair.c -index 6817258..8de690a 100644 ---- a/drivers/media/rc/iguanair.c -+++ b/drivers/media/rc/iguanair.c -@@ -123,6 +123,7 @@ static void process_ir_data(struct iguanair *ir, unsigned len) +Index: linux-3.2.46/drivers/media/rc/iguanair.c +=================================================================== +--- linux-3.2.46.orig/drivers/media/rc/iguanair.c 2013-07-26 19:25:55.000000000 +0000 ++++ linux-3.2.46/drivers/media/rc/iguanair.c 2013-07-26 19:25:56.000000000 +0000 +@@ -123,6 +123,7 @@ break; case CMD_RX_OVERFLOW: dev_warn(ir->dev, "receive overflow\n"); @@ -23,7 +23,7 @@ break; default: dev_warn(ir->dev, "control code %02x received\n", -@@ -255,6 +256,9 @@ static int iguanair_receiver(struct iguanair *ir, bool enable) +@@ -255,6 +256,9 @@ struct packet packet = { 0, DIR_OUT, enable ? CMD_RECEIVER_ON : CMD_RECEIVER_OFF }; diff -Nru linux-3.2.46/debian/patches/features/all/iguanair/0007-media-iguanair-advertise-the-resolution-and-timeout-.patch linux-3.2.46/debian/patches/features/all/iguanair/0007-media-iguanair-advertise-the-resolution-and-timeout-.patch --- linux-3.2.46/debian/patches/features/all/iguanair/0007-media-iguanair-advertise-the-resolution-and-timeout-.patch 2013-02-24 03:52:42.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/iguanair/0007-media-iguanair-advertise-the-resolution-and-timeout-.patch 2013-07-26 19:25:59.000000000 +0000 @@ -14,11 +14,11 @@ drivers/media/rc/iguanair.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) -diff --git a/drivers/media/rc/iguanair.c b/drivers/media/rc/iguanair.c -index 8de690a..9810008 100644 ---- a/drivers/media/rc/iguanair.c -+++ b/drivers/media/rc/iguanair.c -@@ -75,6 +75,7 @@ struct iguanair { +Index: linux-3.2.46/drivers/media/rc/iguanair.c +=================================================================== +--- linux-3.2.46.orig/drivers/media/rc/iguanair.c 2013-07-26 19:25:56.000000000 +0000 ++++ linux-3.2.46/drivers/media/rc/iguanair.c 2013-07-26 19:25:58.000000000 +0000 +@@ -75,6 +75,7 @@ #define MAX_PACKET_SIZE 8u #define TIMEOUT 1000 @@ -26,7 +26,7 @@ struct packet { uint16_t start; -@@ -143,7 +144,7 @@ static void process_ir_data(struct iguanair *ir, unsigned len) +@@ -143,7 +144,7 @@ } else { rawir.pulse = (ir->buf_in[i] & 0x80) == 0; rawir.duration = ((ir->buf_in[i] & 0x7f) + 1) * @@ -35,7 +35,7 @@ } ir_raw_event_store_with_filter(ir->rc, &rawir); -@@ -517,7 +518,9 @@ static int __devinit iguanair_probe(struct usb_interface *intf, +@@ -517,7 +518,9 @@ rc->s_tx_carrier = iguanair_set_tx_carrier; rc->tx_ir = iguanair_tx; rc->driver_name = DRIVER_NAME; diff -Nru linux-3.2.46/debian/patches/features/all/iguanair/0008-media-iguanair-fix-receiver-overflow.patch linux-3.2.46/debian/patches/features/all/iguanair/0008-media-iguanair-fix-receiver-overflow.patch --- linux-3.2.46/debian/patches/features/all/iguanair/0008-media-iguanair-fix-receiver-overflow.patch 2013-02-24 03:52:42.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/iguanair/0008-media-iguanair-fix-receiver-overflow.patch 2013-07-26 19:26:00.000000000 +0000 @@ -18,11 +18,11 @@ drivers/media/rc/iguanair.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) -diff --git a/drivers/media/rc/iguanair.c b/drivers/media/rc/iguanair.c -index 9810008..6a09c2e 100644 ---- a/drivers/media/rc/iguanair.c -+++ b/drivers/media/rc/iguanair.c -@@ -484,9 +484,8 @@ static int __devinit iguanair_probe(struct usb_interface *intf, +Index: linux-3.2.46/drivers/media/rc/iguanair.c +=================================================================== +--- linux-3.2.46.orig/drivers/media/rc/iguanair.c 2013-07-26 19:25:58.000000000 +0000 ++++ linux-3.2.46/drivers/media/rc/iguanair.c 2013-07-26 19:25:59.000000000 +0000 +@@ -484,9 +484,8 @@ init_completion(&ir->completion); pipein = usb_rcvintpipe(udev, idesc->endpoint[0].desc.bEndpointAddress); diff -Nru linux-3.2.46/debian/patches/features/all/iguanair/0009-media-rc-do-not-wake-up-rc-thread-unless-there-is-so.patch linux-3.2.46/debian/patches/features/all/iguanair/0009-media-rc-do-not-wake-up-rc-thread-unless-there-is-so.patch --- linux-3.2.46/debian/patches/features/all/iguanair/0009-media-rc-do-not-wake-up-rc-thread-unless-there-is-so.patch 2013-02-24 03:52:42.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/iguanair/0009-media-rc-do-not-wake-up-rc-thread-unless-there-is-so.patch 2013-07-26 19:26:01.000000000 +0000 @@ -15,9 +15,11 @@ Signed-off-by: Mauro Carvalho Chehab [bwh: Restricted to iguanair driver] --- ---- a/drivers/media/rc/iguanair.c -+++ b/drivers/media/rc/iguanair.c -@@ -134,6 +134,7 @@ static void process_ir_data(struct iguanair *ir, unsigned len) +Index: linux-3.2.46/drivers/media/rc/iguanair.c +=================================================================== +--- linux-3.2.46.orig/drivers/media/rc/iguanair.c 2013-07-26 19:25:59.000000000 +0000 ++++ linux-3.2.46/drivers/media/rc/iguanair.c 2013-07-26 19:26:00.000000000 +0000 +@@ -134,6 +134,7 @@ } else if (len >= 7) { DEFINE_IR_RAW_EVENT(rawir); unsigned i; @@ -25,7 +27,7 @@ init_ir_raw_event(&rawir); -@@ -147,10 +148,12 @@ static void process_ir_data(struct iguanair *ir, unsigned len) +@@ -147,10 +148,12 @@ RX_RESOLUTION; } diff -Nru linux-3.2.46/debian/patches/features/all/iguanair/0010-media-iguanair-do-not-modify-transmit-buffer.patch linux-3.2.46/debian/patches/features/all/iguanair/0010-media-iguanair-do-not-modify-transmit-buffer.patch --- linux-3.2.46/debian/patches/features/all/iguanair/0010-media-iguanair-do-not-modify-transmit-buffer.patch 2013-02-24 03:52:42.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/iguanair/0010-media-iguanair-do-not-modify-transmit-buffer.patch 2013-07-26 19:26:03.000000000 +0000 @@ -13,11 +13,11 @@ drivers/media/rc/iguanair.c | 51 ++++++++++++++++++------------------------- 1 file changed, 21 insertions(+), 30 deletions(-) -diff --git a/drivers/media/rc/iguanair.c b/drivers/media/rc/iguanair.c -index 66ba237..1e4c68a 100644 ---- a/drivers/media/rc/iguanair.c -+++ b/drivers/media/rc/iguanair.c -@@ -334,21 +334,34 @@ static int iguanair_set_tx_mask(struct rc_dev *dev, uint32_t mask) +Index: linux-3.2.46/drivers/media/rc/iguanair.c +=================================================================== +--- linux-3.2.46.orig/drivers/media/rc/iguanair.c 2013-07-26 19:26:00.000000000 +0000 ++++ linux-3.2.46/drivers/media/rc/iguanair.c 2013-07-26 19:26:02.000000000 +0000 +@@ -334,21 +334,34 @@ static int iguanair_tx(struct rc_dev *dev, unsigned *txbuf, unsigned count) { struct iguanair *ir = dev->priv; @@ -58,7 +58,7 @@ } if (count == 0) { -@@ -356,12 +369,6 @@ static int iguanair_tx(struct rc_dev *dev, unsigned *txbuf, unsigned count) +@@ -356,12 +369,6 @@ goto out; } @@ -71,7 +71,7 @@ packet->header.start = 0; packet->header.direction = DIR_OUT; packet->header.cmd = CMD_SEND; -@@ -370,26 +377,11 @@ static int iguanair_tx(struct rc_dev *dev, unsigned *txbuf, unsigned count) +@@ -370,26 +377,11 @@ packet->busy7 = ir->busy7; packet->busy4 = ir->busy4; @@ -99,7 +99,7 @@ } } -@@ -405,9 +397,8 @@ static int iguanair_tx(struct rc_dev *dev, unsigned *txbuf, unsigned count) +@@ -405,9 +397,8 @@ dev_warn(ir->dev, "re-enable receiver after transmit failed\n"); } diff -Nru linux-3.2.46/debian/patches/features/all/iguanair/0011-media-iguanair-cannot-send-data-from-the-stack.patch linux-3.2.46/debian/patches/features/all/iguanair/0011-media-iguanair-cannot-send-data-from-the-stack.patch --- linux-3.2.46/debian/patches/features/all/iguanair/0011-media-iguanair-cannot-send-data-from-the-stack.patch 2013-02-24 03:52:42.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/iguanair/0011-media-iguanair-cannot-send-data-from-the-stack.patch 2013-07-26 19:26:04.000000000 +0000 @@ -14,10 +14,10 @@ drivers/media/rc/iguanair.c | 147 ++++++++++++++++++++++--------------------- 1 file changed, 75 insertions(+), 72 deletions(-) -diff --git a/drivers/media/rc/iguanair.c b/drivers/media/rc/iguanair.c -index 1e4c68a..51d7057 100644 ---- a/drivers/media/rc/iguanair.c -+++ b/drivers/media/rc/iguanair.c +Index: linux-3.2.46/drivers/media/rc/iguanair.c +=================================================================== +--- linux-3.2.46.orig/drivers/media/rc/iguanair.c 2013-07-26 19:26:02.000000000 +0000 ++++ linux-3.2.46/drivers/media/rc/iguanair.c 2013-07-26 19:26:03.000000000 +0000 @@ -28,6 +28,7 @@ #include @@ -26,7 +26,7 @@ struct iguanair { struct rc_dev *rc; -@@ -35,26 +36,23 @@ struct iguanair { +@@ -35,26 +36,23 @@ struct device *dev; struct usb_device *udev; @@ -57,7 +57,7 @@ char name[64]; char phys[64]; -@@ -73,7 +71,8 @@ struct iguanair { +@@ -73,7 +71,8 @@ #define DIR_IN 0xdc #define DIR_OUT 0xcd @@ -67,7 +67,7 @@ #define TIMEOUT 1000 #define RX_RESOLUTION 21333 -@@ -191,20 +190,25 @@ static void iguanair_rx(struct urb *urb) +@@ -191,20 +190,25 @@ dev_warn(ir->dev, "failed to resubmit urb: %d\n", rc); } @@ -100,7 +100,7 @@ if (wait_for_completion_timeout(&ir->completion, TIMEOUT) == 0) return -ETIMEDOUT; -@@ -213,14 +217,13 @@ static int iguanair_send(struct iguanair *ir, void *data, unsigned size) +@@ -213,14 +217,13 @@ static int iguanair_get_features(struct iguanair *ir) { @@ -119,7 +119,7 @@ if (rc) { dev_info(ir->dev, "failed to get version\n"); goto out; -@@ -235,17 +238,23 @@ static int iguanair_get_features(struct iguanair *ir) +@@ -235,17 +238,23 @@ ir->bufsize = 150; ir->cycle_overhead = 65; @@ -147,7 +147,7 @@ if (rc) { dev_info(ir->dev, "failed to get features\n"); goto out; -@@ -257,13 +266,18 @@ out: +@@ -257,13 +266,18 @@ static int iguanair_receiver(struct iguanair *ir, bool enable) { @@ -169,7 +169,7 @@ } /* -@@ -308,8 +322,8 @@ static int iguanair_set_tx_carrier(struct rc_dev *dev, uint32_t carrier) +@@ -308,8 +322,8 @@ fours = (cycles - sevens * 7) / 4; /* magic happens here */ @@ -180,7 +180,7 @@ } mutex_unlock(&ir->lock); -@@ -325,7 +339,7 @@ static int iguanair_set_tx_mask(struct rc_dev *dev, uint32_t mask) +@@ -325,7 +339,7 @@ return 4; mutex_lock(&ir->lock); @@ -189,7 +189,7 @@ mutex_unlock(&ir->lock); return 0; -@@ -337,16 +351,9 @@ static int iguanair_tx(struct rc_dev *dev, unsigned *txbuf, unsigned count) +@@ -337,16 +351,9 @@ uint8_t space; unsigned i, size, periods, bytes; int rc; @@ -206,7 +206,7 @@ /* convert from us to carrier periods */ for (i = space = size = 0; i < count; i++) { periods = DIV_ROUND_CLOSEST(txbuf[i] * ir->carrier, 1000000); -@@ -356,11 +363,11 @@ static int iguanair_tx(struct rc_dev *dev, unsigned *txbuf, unsigned count) +@@ -356,11 +363,11 @@ break; } while (periods > 127) { @@ -220,7 +220,7 @@ space ^= 0x80; } -@@ -369,36 +376,19 @@ static int iguanair_tx(struct rc_dev *dev, unsigned *txbuf, unsigned count) +@@ -369,36 +376,19 @@ goto out; } @@ -262,7 +262,7 @@ mutex_unlock(&ir->lock); return rc ? rc : count; -@@ -411,8 +401,6 @@ static int iguanair_open(struct rc_dev *rdev) +@@ -411,8 +401,6 @@ mutex_lock(&ir->lock); @@ -271,7 +271,7 @@ rc = iguanair_receiver(ir, true); if (rc == 0) ir->receiver_on = true; -@@ -443,7 +431,7 @@ static int __devinit iguanair_probe(struct usb_interface *intf, +@@ -443,7 +431,7 @@ struct usb_device *udev = interface_to_usbdev(intf); struct iguanair *ir; struct rc_dev *rc; @@ -280,7 +280,7 @@ struct usb_host_interface *idesc; ir = kzalloc(sizeof(*ir), GFP_KERNEL); -@@ -453,11 +441,14 @@ static int __devinit iguanair_probe(struct usb_interface *intf, +@@ -453,11 +441,14 @@ goto out; } @@ -297,7 +297,7 @@ ret = -ENOMEM; goto out; } -@@ -472,13 +463,18 @@ static int __devinit iguanair_probe(struct usb_interface *intf, +@@ -472,13 +463,18 @@ ir->rc = rc; ir->dev = &intf->dev; ir->udev = udev; @@ -319,7 +319,7 @@ iguanair_rx, ir, 1); ir->urb_in->transfer_dma = ir->dma_in; ir->urb_in->transfer_flags |= URB_NO_TRANSFER_DMA_MAP; -@@ -528,11 +524,14 @@ static int __devinit iguanair_probe(struct usb_interface *intf, +@@ -528,11 +524,14 @@ return 0; out2: usb_kill_urb(ir->urb_in); @@ -336,7 +336,7 @@ } rc_free_device(rc); kfree(ir); -@@ -546,8 +545,11 @@ static void __devexit iguanair_disconnect(struct usb_interface *intf) +@@ -546,8 +545,11 @@ rc_unregister_device(ir->rc); usb_set_intfdata(intf, NULL); usb_kill_urb(ir->urb_in); @@ -349,7 +349,7 @@ kfree(ir); } -@@ -565,6 +567,7 @@ static int iguanair_suspend(struct usb_interface *intf, pm_message_t message) +@@ -565,6 +567,7 @@ } usb_kill_urb(ir->urb_in); diff -Nru linux-3.2.46/debian/patches/features/all/Input-add-Synaptics-USB-device-driver.patch linux-3.2.46/debian/patches/features/all/Input-add-Synaptics-USB-device-driver.patch --- linux-3.2.46/debian/patches/features/all/Input-add-Synaptics-USB-device-driver.patch 2013-02-24 03:52:42.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/Input-add-Synaptics-USB-device-driver.patch 2013-07-26 19:24:01.000000000 +0000 @@ -26,11 +26,11 @@ 5 files changed, 607 insertions(+) create mode 100644 drivers/input/mouse/synaptics_usb.c -diff --git a/drivers/hid/hid-core.c b/drivers/hid/hid-core.c -index 848a56c..b639855 100644 ---- a/drivers/hid/hid-core.c -+++ b/drivers/hid/hid-core.c -@@ -1892,6 +1892,16 @@ static const struct hid_device_id hid_ignore_list[] = { +Index: linux-3.2.46/drivers/hid/hid-core.c +=================================================================== +--- linux-3.2.46.orig/drivers/hid/hid-core.c 2013-07-26 18:54:25.000000000 +0000 ++++ linux-3.2.46/drivers/hid/hid-core.c 2013-07-26 19:24:00.000000000 +0000 +@@ -1923,6 +1923,16 @@ { HID_USB_DEVICE(USB_VENDOR_ID_PANJIT, 0x0004) }, { HID_USB_DEVICE(USB_VENDOR_ID_PHILIPS, USB_DEVICE_ID_PHILIPS_IEEE802154_DONGLE) }, { HID_USB_DEVICE(USB_VENDOR_ID_POWERCOM, USB_DEVICE_ID_POWERCOM_UPS) }, @@ -47,11 +47,11 @@ { HID_USB_DEVICE(USB_VENDOR_ID_VERNIER, USB_DEVICE_ID_VERNIER_LABPRO) }, { HID_USB_DEVICE(USB_VENDOR_ID_VERNIER, USB_DEVICE_ID_VERNIER_GOTEMP) }, { HID_USB_DEVICE(USB_VENDOR_ID_VERNIER, USB_DEVICE_ID_VERNIER_SKIP) }, -diff --git a/drivers/hid/hid-ids.h b/drivers/hid/hid-ids.h -index 06ce996..3b68343 100644 ---- a/drivers/hid/hid-ids.h -+++ b/drivers/hid/hid-ids.h -@@ -633,6 +633,17 @@ +Index: linux-3.2.46/drivers/hid/hid-ids.h +=================================================================== +--- linux-3.2.46.orig/drivers/hid/hid-ids.h 2013-07-26 18:54:25.000000000 +0000 ++++ linux-3.2.46/drivers/hid/hid-ids.h 2013-07-26 19:24:00.000000000 +0000 +@@ -677,6 +677,17 @@ #define USB_DEVICE_ID_SYMBOL_SCANNER_1 0x0800 #define USB_DEVICE_ID_SYMBOL_SCANNER_2 0x1300 @@ -69,11 +69,11 @@ #define USB_VENDOR_ID_THRUSTMASTER 0x044f #define USB_VENDOR_ID_TOPSEED 0x0766 -diff --git a/drivers/input/mouse/Kconfig b/drivers/input/mouse/Kconfig -index 9c1e6ee..9b8db82 100644 ---- a/drivers/input/mouse/Kconfig -+++ b/drivers/input/mouse/Kconfig -@@ -322,4 +322,21 @@ config MOUSE_SYNAPTICS_I2C +Index: linux-3.2.46/drivers/input/mouse/Kconfig +=================================================================== +--- linux-3.2.46.orig/drivers/input/mouse/Kconfig 2013-07-26 18:54:25.000000000 +0000 ++++ linux-3.2.46/drivers/input/mouse/Kconfig 2013-07-26 19:24:00.000000000 +0000 +@@ -322,4 +322,21 @@ To compile this driver as a module, choose M here: the module will be called synaptics_i2c. @@ -95,11 +95,11 @@ + module will be called synaptics_usb. + endif -diff --git a/drivers/input/mouse/Makefile b/drivers/input/mouse/Makefile -index 570c84a4..4718eff 100644 ---- a/drivers/input/mouse/Makefile -+++ b/drivers/input/mouse/Makefile -@@ -18,6 +18,7 @@ obj-$(CONFIG_MOUSE_PXA930_TRKBALL) += pxa930_trkball.o +Index: linux-3.2.46/drivers/input/mouse/Makefile +=================================================================== +--- linux-3.2.46.orig/drivers/input/mouse/Makefile 2013-07-26 18:54:25.000000000 +0000 ++++ linux-3.2.46/drivers/input/mouse/Makefile 2013-07-26 19:24:00.000000000 +0000 +@@ -18,6 +18,7 @@ obj-$(CONFIG_MOUSE_RISCPC) += rpcmouse.o obj-$(CONFIG_MOUSE_SERIAL) += sermouse.o obj-$(CONFIG_MOUSE_SYNAPTICS_I2C) += synaptics_i2c.o @@ -107,11 +107,10 @@ obj-$(CONFIG_MOUSE_VSXXXAA) += vsxxxaa.o psmouse-objs := psmouse-base.o synaptics.o -diff --git a/drivers/input/mouse/synaptics_usb.c b/drivers/input/mouse/synaptics_usb.c -new file mode 100644 -index 0000000..e559a94 ---- /dev/null -+++ b/drivers/input/mouse/synaptics_usb.c +Index: linux-3.2.46/drivers/input/mouse/synaptics_usb.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/input/mouse/synaptics_usb.c 2013-07-26 19:24:00.000000000 +0000 @@ -0,0 +1,568 @@ +/* + * USB Synaptics device driver diff -Nru linux-3.2.46/debian/patches/features/all/Input-ALPS-add-protocol-version-field-in-alps_model_.patch linux-3.2.46/debian/patches/features/all/Input-ALPS-add-protocol-version-field-in-alps_model_.patch --- linux-3.2.46/debian/patches/features/all/Input-ALPS-add-protocol-version-field-in-alps_model_.patch 2013-02-24 03:52:33.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/Input-ALPS-add-protocol-version-field-in-alps_model_.patch 2013-07-26 19:17:42.000000000 +0000 @@ -14,10 +14,10 @@ Acked-by: Chase Douglas Signed-off-by: Dmitry Torokhov -diff --git a/drivers/input/mouse/alps.c b/drivers/input/mouse/alps.c -index 19d0943..77b776d 100644 ---- a/drivers/input/mouse/alps.c -+++ b/drivers/input/mouse/alps.c +Index: linux-3.2.46/drivers/input/mouse/alps.c +=================================================================== +--- linux-3.2.46.orig/drivers/input/mouse/alps.c 2013-07-26 19:17:40.000000000 +0000 ++++ linux-3.2.46/drivers/input/mouse/alps.c 2013-07-26 19:17:41.000000000 +0000 @@ -23,7 +23,6 @@ #include "psmouse.h" #include "alps.h" @@ -79,7 +79,7 @@ }; /* -@@ -112,7 +111,7 @@ static void alps_process_packet(struct psmouse *psmouse) +@@ -112,7 +111,7 @@ int x, y, z, ges, fin, left, right, middle; int back = 0, forward = 0; @@ -88,10 +88,10 @@ left = packet[2] & 0x10; right = packet[2] & 0x08; middle = 0; -diff --git a/drivers/input/mouse/alps.h b/drivers/input/mouse/alps.h -index 904ed8b..4ce9bba 100644 ---- a/drivers/input/mouse/alps.h -+++ b/drivers/input/mouse/alps.h +Index: linux-3.2.46/drivers/input/mouse/alps.h +=================================================================== +--- linux-3.2.46.orig/drivers/input/mouse/alps.h 2013-07-26 18:56:26.000000000 +0000 ++++ linux-3.2.46/drivers/input/mouse/alps.h 2013-07-26 19:17:41.000000000 +0000 @@ -12,8 +12,12 @@ #ifndef _ALPS_H #define _ALPS_H @@ -105,6 +105,3 @@ unsigned char byte0, mask0; unsigned char flags; }; --- -1.7.8.2 - diff -Nru linux-3.2.46/debian/patches/features/all/Input-ALPS-add-semi-MT-support-for-v3-protocol.patch linux-3.2.46/debian/patches/features/all/Input-ALPS-add-semi-MT-support-for-v3-protocol.patch --- linux-3.2.46/debian/patches/features/all/Input-ALPS-add-semi-MT-support-for-v3-protocol.patch 2013-02-24 03:52:35.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/Input-ALPS-add-semi-MT-support-for-v3-protocol.patch 2013-07-26 19:17:46.000000000 +0000 @@ -8,10 +8,10 @@ Acked-by: Chase Douglas Signed-off-by: Dmitry Torokhov -diff --git a/drivers/input/mouse/alps.c b/drivers/input/mouse/alps.c -index a0248fd..bd87380 100644 ---- a/drivers/input/mouse/alps.c -+++ b/drivers/input/mouse/alps.c +Index: linux-3.2.46/drivers/input/mouse/alps.c +=================================================================== +--- linux-3.2.46.orig/drivers/input/mouse/alps.c 2013-07-26 19:17:44.000000000 +0000 ++++ linux-3.2.46/drivers/input/mouse/alps.c 2013-07-26 19:17:46.000000000 +0000 @@ -17,6 +17,7 @@ #include @@ -33,7 +33,7 @@ #define ALPS_CMD_NIBBLE_10 0x01f2 static const struct alps_nibble_commands alps_v3_nibble_commands[] = { -@@ -250,6 +257,137 @@ static void alps_process_packet_v1_v2(struct psmouse *psmouse) +@@ -250,6 +257,137 @@ input_sync(dev); } @@ -171,7 +171,7 @@ static void alps_process_trackstick_packet_v3(struct psmouse *psmouse) { struct alps_data *priv = psmouse->private; -@@ -318,16 +456,17 @@ static void alps_process_touchpad_packet_v3(struct psmouse *psmouse) +@@ -318,16 +456,17 @@ struct input_dev *dev2 = priv->dev2; int x, y, z; int left, right, middle; @@ -195,7 +195,7 @@ /* * Sometimes a position packet will indicate a multi-packet * sequence, but then what follows is another position -@@ -335,18 +474,49 @@ static void alps_process_touchpad_packet_v3(struct psmouse *psmouse) +@@ -335,18 +474,49 @@ * position packet as usual. */ if (packet[0] & 0x40) { @@ -251,7 +251,7 @@ left = packet[3] & 0x01; right = packet[3] & 0x02; -@@ -366,22 +536,38 @@ static void alps_process_touchpad_packet_v3(struct psmouse *psmouse) +@@ -366,22 +536,38 @@ if (x && y && !z) return; @@ -295,7 +295,7 @@ input_sync(dev); if (!(priv->quirks & ALPS_QUIRK_TRACKSTICK_BUTTONS)) { -@@ -1368,9 +1554,18 @@ int alps_init(struct psmouse *psmouse) +@@ -1371,9 +1557,18 @@ input_set_abs_params(dev1, ABS_Y, 0, 767, 0, 0); break; case ALPS_PROTO_V3: @@ -316,11 +316,11 @@ break; } -diff --git a/drivers/input/mouse/alps.h b/drivers/input/mouse/alps.h -index 62db7f4..a00a4ab 100644 ---- a/drivers/input/mouse/alps.h -+++ b/drivers/input/mouse/alps.h -@@ -38,6 +38,7 @@ struct alps_data { +Index: linux-3.2.46/drivers/input/mouse/alps.h +=================================================================== +--- linux-3.2.46.orig/drivers/input/mouse/alps.h 2013-07-26 19:17:44.000000000 +0000 ++++ linux-3.2.46/drivers/input/mouse/alps.h 2013-07-26 19:17:46.000000000 +0000 +@@ -38,6 +38,7 @@ int addr_command; /* Command to set register address */ int prev_fin; /* Finger bit from previous packet */ int multi_packet; /* Multi-packet data in progress */ @@ -328,6 +328,3 @@ u8 quirks; struct timer_list timer; }; --- -1.7.8.2 - diff -Nru linux-3.2.46/debian/patches/features/all/Input-ALPS-add-support-for-protocol-versions-3-and-4.patch linux-3.2.46/debian/patches/features/all/Input-ALPS-add-support-for-protocol-versions-3-and-4.patch --- linux-3.2.46/debian/patches/features/all/Input-ALPS-add-support-for-protocol-versions-3-and-4.patch 2013-02-24 03:52:32.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/Input-ALPS-add-support-for-protocol-versions-3-and-4.patch 2013-07-26 19:17:45.000000000 +0000 @@ -16,10 +16,10 @@ Acked-by: Chase Douglas Signed-off-by: Dmitry Torokhov -diff --git a/drivers/input/mouse/alps.c b/drivers/input/mouse/alps.c -index 44a0a71..a0248fd 100644 ---- a/drivers/input/mouse/alps.c -+++ b/drivers/input/mouse/alps.c +Index: linux-3.2.46/drivers/input/mouse/alps.c +=================================================================== +--- linux-3.2.46.orig/drivers/input/mouse/alps.c 2013-07-26 19:17:43.000000000 +0000 ++++ linux-3.2.46/drivers/input/mouse/alps.c 2013-07-26 19:17:44.000000000 +0000 @@ -23,6 +23,50 @@ #include "psmouse.h" #include "alps.h" @@ -127,7 +127,7 @@ }; /* -@@ -101,7 +148,7 @@ static void alps_report_buttons(struct psmouse *psmouse, +@@ -101,7 +148,7 @@ input_sync(dev2); } @@ -136,7 +136,7 @@ { struct alps_data *priv = psmouse->private; const struct alps_model_info *model = priv->i; -@@ -203,6 +250,224 @@ static void alps_process_packet(struct psmouse *psmouse) +@@ -203,6 +250,224 @@ input_sync(dev); } @@ -361,7 +361,7 @@ static void alps_report_bare_ps2_packet(struct psmouse *psmouse, unsigned char packet[], bool report_buttons) -@@ -376,11 +641,127 @@ static psmouse_ret_t alps_process_byte(struct psmouse *psmouse) +@@ -376,11 +641,127 @@ return PSMOUSE_GOOD_DATA; } @@ -489,7 +489,7 @@ int i; /* -@@ -428,12 +809,41 @@ static const struct alps_model_info *alps_get_model(struct psmouse *psmouse, int +@@ -431,12 +812,41 @@ *version = (param[0] << 8) | (param[1] << 4) | i; } @@ -503,8 +503,7 @@ + break; + } + } - -- return NULL; ++ + if (model && model->proto_version > ALPS_PROTO_V2) { + /* + * Need to check command mode response to identify @@ -530,12 +529,13 @@ + param[0]); + } + } -+ + +- return NULL; + return model; } /* -@@ -441,7 +851,7 @@ static const struct alps_model_info *alps_get_model(struct psmouse *psmouse, int +@@ -444,7 +854,7 @@ * subsequent commands. It looks like glidepad is behind stickpointer, * I'd thought it would be other way around... */ @@ -544,7 +544,7 @@ { struct ps2dev *ps2dev = &psmouse->ps2dev; int cmd = enable ? PSMOUSE_CMD_SETSCALE21 : PSMOUSE_CMD_SETSCALE11; -@@ -458,7 +868,7 @@ static int alps_passthrough_mode(struct psmouse *psmouse, bool enable) +@@ -461,7 +871,7 @@ return 0; } @@ -553,7 +553,7 @@ { struct ps2dev *ps2dev = &psmouse->ps2dev; -@@ -533,13 +943,13 @@ static int alps_poll(struct psmouse *psmouse) +@@ -536,13 +946,13 @@ bool poll_failed; if (priv->i->flags & ALPS_PASS) @@ -569,7 +569,7 @@ if (poll_failed || (buf[0] & priv->i->mask0) != priv->i->byte0) return -1; -@@ -556,13 +966,13 @@ static int alps_poll(struct psmouse *psmouse) +@@ -559,13 +969,13 @@ return 0; } @@ -585,7 +585,7 @@ return -1; } -@@ -571,13 +981,13 @@ static int alps_hw_init(struct psmouse *psmouse) +@@ -574,13 +984,13 @@ return -1; } @@ -601,7 +601,7 @@ return -1; } -@@ -590,6 +1000,297 @@ static int alps_hw_init(struct psmouse *psmouse) +@@ -593,6 +1003,297 @@ return 0; } @@ -899,7 +899,7 @@ static int alps_reconnect(struct psmouse *psmouse) { const struct alps_model_info *model; -@@ -630,6 +1331,8 @@ int alps_init(struct psmouse *psmouse) +@@ -633,6 +1334,8 @@ psmouse->private = priv; @@ -908,7 +908,7 @@ model = alps_get_model(psmouse, &version); if (!model) goto init_fail; -@@ -657,8 +1360,20 @@ int alps_init(struct psmouse *psmouse) +@@ -660,8 +1363,20 @@ BIT_MASK(BTN_LEFT) | BIT_MASK(BTN_RIGHT); dev1->evbit[BIT_WORD(EV_ABS)] |= BIT_MASK(EV_ABS); @@ -931,7 +931,7 @@ input_set_abs_params(dev1, ABS_PRESSURE, 0, 127, 0, 0); if (model->flags & ALPS_WHEEL) { -@@ -701,7 +1416,7 @@ int alps_init(struct psmouse *psmouse) +@@ -704,7 +1419,7 @@ psmouse->poll = alps_poll; psmouse->disconnect = alps_disconnect; psmouse->reconnect = alps_reconnect; @@ -940,10 +940,10 @@ /* We are having trouble resyncing ALPS touchpads so disable it for now */ psmouse->resync_time = 0; -diff --git a/drivers/input/mouse/alps.h b/drivers/input/mouse/alps.h -index 4ce9bba..62db7f4 100644 ---- a/drivers/input/mouse/alps.h -+++ b/drivers/input/mouse/alps.h +Index: linux-3.2.46/drivers/input/mouse/alps.h +=================================================================== +--- linux-3.2.46.orig/drivers/input/mouse/alps.h 2013-07-26 19:17:41.000000000 +0000 ++++ linux-3.2.46/drivers/input/mouse/alps.h 2013-07-26 19:17:44.000000000 +0000 @@ -14,22 +14,36 @@ #define ALPS_PROTO_V1 0 @@ -981,10 +981,10 @@ #ifdef CONFIG_MOUSE_PS2_ALPS int alps_detect(struct psmouse *psmouse, bool set_properties); int alps_init(struct psmouse *psmouse); -diff --git a/drivers/input/mouse/psmouse.h b/drivers/input/mouse/psmouse.h -index 9b84b0c..11a9c6c 100644 ---- a/drivers/input/mouse/psmouse.h -+++ b/drivers/input/mouse/psmouse.h +Index: linux-3.2.46/drivers/input/mouse/psmouse.h +=================================================================== +--- linux-3.2.46.orig/drivers/input/mouse/psmouse.h 2013-07-26 18:56:25.000000000 +0000 ++++ linux-3.2.46/drivers/input/mouse/psmouse.h 2013-07-26 19:17:44.000000000 +0000 @@ -8,6 +8,7 @@ #define PSMOUSE_CMD_SETSTREAM 0x00ea #define PSMOUSE_CMD_SETPOLL 0x00f0 @@ -993,6 +993,3 @@ #define PSMOUSE_CMD_GETID 0x02f2 #define PSMOUSE_CMD_SETRATE 0x10f3 #define PSMOUSE_CMD_ENABLE 0x00f4 --- -1.7.8.2 - diff -Nru linux-3.2.46/debian/patches/features/all/Input-ALPS-move-protocol-information-to-Documentatio.patch linux-3.2.46/debian/patches/features/all/Input-ALPS-move-protocol-information-to-Documentatio.patch --- linux-3.2.46/debian/patches/features/all/Input-ALPS-move-protocol-information-to-Documentatio.patch 2013-02-24 03:52:42.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/Input-ALPS-move-protocol-information-to-Documentatio.patch 2013-07-26 19:17:41.000000000 +0000 @@ -13,11 +13,10 @@ Acked-by: Chase Douglas Signed-off-by: Dmitry Torokhov -diff --git a/Documentation/input/alps.txt b/Documentation/input/alps.txt -new file mode 100644 -index 0000000..ab5478f ---- /dev/null -+++ b/Documentation/input/alps.txt +Index: linux-3.2.46/Documentation/input/alps.txt +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/Documentation/input/alps.txt 2013-07-26 19:17:40.000000000 +0000 @@ -0,0 +1,75 @@ +ALPS Touchpad Protocol +---------------------- @@ -94,11 +93,11 @@ + byte 6: 0 y9 y8 y7 1 m r l + byte 7: 0 y6 y5 y4 y3 y2 y1 y0 + byte 8: 0 z6 z5 z4 z3 z2 z1 z0 -diff --git a/drivers/input/mouse/alps.c b/drivers/input/mouse/alps.c -index 003587c..19d0943 100644 ---- a/drivers/input/mouse/alps.c -+++ b/drivers/input/mouse/alps.c -@@ -67,42 +67,7 @@ static const struct alps_model_info alps_model_data[] = { +Index: linux-3.2.46/drivers/input/mouse/alps.c +=================================================================== +--- linux-3.2.46.orig/drivers/input/mouse/alps.c 2013-07-26 18:56:27.000000000 +0000 ++++ linux-3.2.46/drivers/input/mouse/alps.c 2013-07-26 19:17:40.000000000 +0000 +@@ -67,42 +67,7 @@ * isn't valid per PS/2 spec. */ @@ -142,6 +141,3 @@ static bool alps_is_valid_first_byte(const struct alps_model_info *model, unsigned char data) --- -1.7.8.2 - diff -Nru linux-3.2.46/debian/patches/features/all/Input-ALPS-remove-assumptions-about-packet-size.patch linux-3.2.46/debian/patches/features/all/Input-ALPS-remove-assumptions-about-packet-size.patch --- linux-3.2.46/debian/patches/features/all/Input-ALPS-remove-assumptions-about-packet-size.patch 2013-02-24 03:52:42.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/Input-ALPS-remove-assumptions-about-packet-size.patch 2013-07-26 19:17:44.000000000 +0000 @@ -12,11 +12,11 @@ Acked-by: Chase Douglas Signed-off-by: Dmitry Torokhov -diff --git a/drivers/input/mouse/alps.c b/drivers/input/mouse/alps.c -index 77b776d..44a0a71 100644 ---- a/drivers/input/mouse/alps.c -+++ b/drivers/input/mouse/alps.c -@@ -308,7 +308,7 @@ static void alps_flush_packet(unsigned long data) +Index: linux-3.2.46/drivers/input/mouse/alps.c +=================================================================== +--- linux-3.2.46.orig/drivers/input/mouse/alps.c 2013-07-26 19:17:41.000000000 +0000 ++++ linux-3.2.46/drivers/input/mouse/alps.c 2013-07-26 19:17:43.000000000 +0000 +@@ -308,7 +308,7 @@ serio_pause_rx(psmouse->ps2dev.serio); @@ -25,7 +25,7 @@ /* * We did not any more data in reasonable amount of time. -@@ -359,8 +359,8 @@ static psmouse_ret_t alps_process_byte(struct psmouse *psmouse) +@@ -359,8 +359,8 @@ return PSMOUSE_BAD_DATA; } @@ -36,7 +36,7 @@ (psmouse->packet[psmouse->pktcnt - 1] & 0x80)) { psmouse_dbg(psmouse, "refusing packet[%i] = %x\n", psmouse->pktcnt - 1, -@@ -368,7 +368,7 @@ static psmouse_ret_t alps_process_byte(struct psmouse *psmouse) +@@ -368,7 +368,7 @@ return PSMOUSE_BAD_DATA; } @@ -45,7 +45,7 @@ alps_process_packet(psmouse); return PSMOUSE_FULL_PACKET; } -@@ -529,7 +529,7 @@ static int alps_tap_mode(struct psmouse *psmouse, int enable) +@@ -532,7 +532,7 @@ static int alps_poll(struct psmouse *psmouse) { struct alps_data *priv = psmouse->private; @@ -54,6 +54,3 @@ bool poll_failed; if (priv->i->flags & ALPS_PASS) --- -1.7.8.2 - diff -Nru linux-3.2.46/debian/patches/features/all/input-mt/Input-add-support-for-Cypress-PS-2-Trackpads.patch linux-3.2.46/debian/patches/features/all/input-mt/Input-add-support-for-Cypress-PS-2-Trackpads.patch --- linux-3.2.46/debian/patches/features/all/input-mt/Input-add-support-for-Cypress-PS-2-Trackpads.patch 2013-04-11 03:27:34.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/input-mt/Input-add-support-for-Cypress-PS-2-Trackpads.patch 2013-07-26 19:30:39.000000000 +0000 @@ -34,9 +34,11 @@ create mode 100644 drivers/input/mouse/cypress_ps2.c create mode 100644 drivers/input/mouse/cypress_ps2.h ---- a/drivers/input/mouse/Kconfig -+++ b/drivers/input/mouse/Kconfig -@@ -68,6 +68,16 @@ config MOUSE_PS2_SYNAPTICS +Index: linux-3.2.46/drivers/input/mouse/Kconfig +=================================================================== +--- linux-3.2.46.orig/drivers/input/mouse/Kconfig 2013-07-26 19:24:00.000000000 +0000 ++++ linux-3.2.46/drivers/input/mouse/Kconfig 2013-07-26 19:30:38.000000000 +0000 +@@ -68,6 +68,16 @@ If unsure, say Y. @@ -53,15 +55,19 @@ config MOUSE_PS2_LIFEBOOK bool "Fujitsu Lifebook PS/2 mouse protocol extension" if EXPERT default y ---- a/drivers/input/mouse/Makefile -+++ b/drivers/input/mouse/Makefile -@@ -31,3 +31,4 @@ psmouse-$(CONFIG_MOUSE_PS2_LIFEBOOK) += +Index: linux-3.2.46/drivers/input/mouse/Makefile +=================================================================== +--- linux-3.2.46.orig/drivers/input/mouse/Makefile 2013-07-26 19:24:00.000000000 +0000 ++++ linux-3.2.46/drivers/input/mouse/Makefile 2013-07-26 19:30:38.000000000 +0000 +@@ -31,3 +31,4 @@ psmouse-$(CONFIG_MOUSE_PS2_SENTELIC) += sentelic.o psmouse-$(CONFIG_MOUSE_PS2_TRACKPOINT) += trackpoint.o psmouse-$(CONFIG_MOUSE_PS2_TOUCHKIT) += touchkit_ps2.o +psmouse-$(CONFIG_MOUSE_PS2_CYPRESS) += cypress_ps2.o ---- /dev/null -+++ b/drivers/input/mouse/cypress_ps2.c +Index: linux-3.2.46/drivers/input/mouse/cypress_ps2.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/input/mouse/cypress_ps2.c 2013-07-26 19:30:38.000000000 +0000 @@ -0,0 +1,725 @@ +/* + * Cypress Trackpad PS/2 mouse driver @@ -788,8 +794,10 @@ +{ + return true; +} ---- /dev/null -+++ b/drivers/input/mouse/cypress_ps2.h +Index: linux-3.2.46/drivers/input/mouse/cypress_ps2.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/input/mouse/cypress_ps2.h 2013-07-26 19:30:38.000000000 +0000 @@ -0,0 +1,191 @@ +#ifndef _CYPRESS_PS2_H +#define _CYPRESS_PS2_H @@ -982,8 +990,10 @@ +#endif /* CONFIG_MOUSE_PS2_CYPRESS */ + +#endif /* _CYPRESS_PS2_H */ ---- a/drivers/input/mouse/psmouse-base.c -+++ b/drivers/input/mouse/psmouse-base.c +Index: linux-3.2.46/drivers/input/mouse/psmouse-base.c +=================================================================== +--- linux-3.2.46.orig/drivers/input/mouse/psmouse-base.c 2013-07-26 18:52:18.000000000 +0000 ++++ linux-3.2.46/drivers/input/mouse/psmouse-base.c 2013-07-26 19:30:38.000000000 +0000 @@ -34,6 +34,7 @@ #include "touchkit_ps2.h" #include "elantech.h" @@ -992,7 +1002,7 @@ #define DRIVER_DESC "PS/2 mouse driver" -@@ -663,6 +664,28 @@ static int psmouse_extensions(struct psm +@@ -663,6 +664,28 @@ } /* @@ -1021,7 +1031,7 @@ * Try ALPS TouchPad */ if (max_proto > PSMOUSE_IMEX) { -@@ -789,6 +812,15 @@ static const struct psmouse_protocol psm +@@ -789,6 +812,15 @@ .alias = "thinkps", .detect = thinking_detect, }, @@ -1037,9 +1047,11 @@ { .type = PSMOUSE_GENPS, .name = "GenPS/2", ---- a/drivers/input/mouse/psmouse.h -+++ b/drivers/input/mouse/psmouse.h -@@ -94,6 +94,7 @@ enum psmouse_type { +Index: linux-3.2.46/drivers/input/mouse/psmouse.h +=================================================================== +--- linux-3.2.46.orig/drivers/input/mouse/psmouse.h 2013-07-26 19:17:44.000000000 +0000 ++++ linux-3.2.46/drivers/input/mouse/psmouse.h 2013-07-26 19:30:38.000000000 +0000 +@@ -94,6 +94,7 @@ PSMOUSE_HGPK, PSMOUSE_ELANTECH, PSMOUSE_FSP, diff -Nru linux-3.2.46/debian/patches/features/all/input-mt/Input-cypress_ps2-fix-trackpadi-found-in-Dell-XPS12.patch linux-3.2.46/debian/patches/features/all/input-mt/Input-cypress_ps2-fix-trackpadi-found-in-Dell-XPS12.patch --- linux-3.2.46/debian/patches/features/all/input-mt/Input-cypress_ps2-fix-trackpadi-found-in-Dell-XPS12.patch 2013-04-11 03:27:34.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/input-mt/Input-cypress_ps2-fix-trackpadi-found-in-Dell-XPS12.patch 2013-07-26 19:30:41.000000000 +0000 @@ -17,11 +17,11 @@ drivers/input/mouse/cypress_ps2.c | 19 +++++++++++++------ 1 file changed, 13 insertions(+), 6 deletions(-) -diff --git a/drivers/input/mouse/cypress_ps2.c b/drivers/input/mouse/cypress_ps2.c -index 1673dc6..f51765f 100644 ---- a/drivers/input/mouse/cypress_ps2.c -+++ b/drivers/input/mouse/cypress_ps2.c -@@ -236,6 +236,13 @@ static int cypress_read_fw_version(struct psmouse *psmouse) +Index: linux-3.2.46/drivers/input/mouse/cypress_ps2.c +=================================================================== +--- linux-3.2.46.orig/drivers/input/mouse/cypress_ps2.c 2013-07-26 19:30:38.000000000 +0000 ++++ linux-3.2.46/drivers/input/mouse/cypress_ps2.c 2013-07-26 19:30:40.000000000 +0000 +@@ -236,6 +236,13 @@ cytp->fw_version = param[2] & FW_VERSION_MASX; cytp->tp_metrics_supported = (param[2] & TP_METRICS_MASK) ? 1 : 0; @@ -35,7 +35,7 @@ psmouse_dbg(psmouse, "cytp->fw_version = %d\n", cytp->fw_version); psmouse_dbg(psmouse, "cytp->tp_metrics_supported = %d\n", cytp->tp_metrics_supported); -@@ -258,6 +265,9 @@ static int cypress_read_tp_metrics(struct psmouse *psmouse) +@@ -258,6 +265,9 @@ cytp->tp_res_x = cytp->tp_max_abs_x / cytp->tp_width; cytp->tp_res_y = cytp->tp_max_abs_y / cytp->tp_high; @@ -45,7 +45,7 @@ memset(param, 0, sizeof(param)); if (cypress_send_ext_cmd(psmouse, CYTP_CMD_READ_TP_METRICS, param) == 0) { /* Update trackpad parameters. */ -@@ -315,18 +325,15 @@ static int cypress_read_tp_metrics(struct psmouse *psmouse) +@@ -315,18 +325,15 @@ static int cypress_query_hardware(struct psmouse *psmouse) { diff -Nru linux-3.2.46/debian/patches/features/all/input-mt/Input-MT-Add-flags-to-input_mt_init_slots.patch linux-3.2.46/debian/patches/features/all/input-mt/Input-MT-Add-flags-to-input_mt_init_slots.patch --- linux-3.2.46/debian/patches/features/all/input-mt/Input-MT-Add-flags-to-input_mt_init_slots.patch 2013-04-11 03:27:34.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/input-mt/Input-MT-Add-flags-to-input_mt_init_slots.patch 2013-07-26 19:30:35.000000000 +0000 @@ -18,8 +18,10 @@ backward-compatible wrapper] [Apollon Oikonomopoulos: fix slot initialization in input_mt_init_slots_flags] --- ---- a/drivers/input/input-mt.c -+++ b/drivers/input/input-mt.c +Index: linux-3.2.46/drivers/input/input-mt.c +=================================================================== +--- linux-3.2.46.orig/drivers/input/input-mt.c 2013-07-26 18:52:19.000000000 +0000 ++++ linux-3.2.46/drivers/input/input-mt.c 2013-07-26 19:30:34.000000000 +0000 @@ -14,6 +14,9 @@ #define TRKID_SGN ((TRKID_MAX + 1) >> 1) @@ -42,7 +44,7 @@ int i; if (!num_slots) -@@ -34,21 +39,29 @@ int input_mt_init_slots(struct input_dev +@@ -34,21 +39,29 @@ if (dev->mt) return dev->mtsize != num_slots ? -EINVAL : 0; @@ -75,7 +77,7 @@ EXPORT_SYMBOL(input_mt_init_slots); /** -@@ -60,7 +73,7 @@ EXPORT_SYMBOL(input_mt_init_slots); +@@ -60,7 +73,7 @@ */ void input_mt_destroy_slots(struct input_dev *dev) { @@ -84,9 +86,11 @@ dev->mt = NULL; dev->mtsize = 0; dev->slot = 0; ---- a/include/linux/input/mt.h -+++ b/include/linux/input/mt.h -@@ -23,6 +23,16 @@ struct input_mt_slot { +Index: linux-3.2.46/include/linux/input/mt.h +=================================================================== +--- linux-3.2.46.orig/include/linux/input/mt.h 2013-07-26 18:52:19.000000000 +0000 ++++ linux-3.2.46/include/linux/input/mt.h 2013-07-26 19:30:34.000000000 +0000 +@@ -23,6 +23,16 @@ int abs[ABS_MT_LAST - ABS_MT_FIRST + 1]; }; @@ -103,7 +107,7 @@ static inline void input_mt_set_value(struct input_mt_slot *slot, unsigned code, int value) { -@@ -36,6 +46,8 @@ static inline int input_mt_get_value(con +@@ -36,6 +46,8 @@ } int input_mt_init_slots(struct input_dev *dev, unsigned int num_slots); diff -Nru linux-3.2.46/debian/patches/features/all/input-mt/Input-MT-Add-in-kernel-tracking.patch linux-3.2.46/debian/patches/features/all/input-mt/Input-MT-Add-in-kernel-tracking.patch --- linux-3.2.46/debian/patches/features/all/input-mt/Input-MT-Add-in-kernel-tracking.patch 2013-04-11 03:27:34.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/input-mt/Input-MT-Add-in-kernel-tracking.patch 2013-07-26 19:30:38.000000000 +0000 @@ -14,9 +14,11 @@ Acked-by: Dmitry Torokhov Signed-off-by: Henrik Rydberg --- ---- a/drivers/input/input-mt.c -+++ b/drivers/input/input-mt.c -@@ -50,7 +50,7 @@ int input_mt_init_slots_flags(struct inp +Index: linux-3.2.46/drivers/input/input-mt.c +=================================================================== +--- linux-3.2.46.orig/drivers/input/input-mt.c 2013-07-26 19:30:35.000000000 +0000 ++++ linux-3.2.46/drivers/input/input-mt.c 2013-07-26 19:30:37.000000000 +0000 +@@ -50,7 +50,7 @@ mt = kzalloc(sizeof(*mt) + num_slots * sizeof(*mt->slots) + num_slots * sizeof(*mt->slot_frame), GFP_KERNEL); if (!mt) @@ -25,7 +27,7 @@ dev->mtsize = num_slots; mt->num_slots = num_slots; -@@ -81,6 +81,12 @@ int input_mt_init_slots_flags(struct inp +@@ -81,6 +81,12 @@ } if (flags & INPUT_MT_DIRECT) __set_bit(INPUT_PROP_DIRECT, dev->propbit); @@ -38,7 +40,7 @@ /* Mark slots as 'unused' */ for (i = 0; i < num_slots; i++) -@@ -88,6 +94,9 @@ int input_mt_init_slots_flags(struct inp +@@ -88,6 +94,9 @@ dev->mt = &mt->slots[0]; return 0; @@ -48,7 +50,7 @@ } EXPORT_SYMBOL(input_mt_init_slots_flags); -@@ -106,7 +115,11 @@ EXPORT_SYMBOL(input_mt_init_slots); +@@ -106,7 +115,11 @@ */ void input_mt_destroy_slots(struct input_dev *dev) { @@ -61,7 +63,7 @@ dev->mt = NULL; dev->mtsize = 0; dev->slot = 0; -@@ -253,3 +266,131 @@ void input_mt_sync_frame(struct input_de +@@ -253,3 +266,131 @@ mt->frame++; } EXPORT_SYMBOL(input_mt_sync_frame); @@ -193,8 +195,10 @@ + return 0; +} +EXPORT_SYMBOL(input_mt_assign_slots); ---- a/include/linux/input/mt.h -+++ b/include/linux/input/mt.h +Index: linux-3.2.46/include/linux/input/mt.h +=================================================================== +--- linux-3.2.46.orig/include/linux/input/mt.h 2013-07-26 19:30:35.000000000 +0000 ++++ linux-3.2.46/include/linux/input/mt.h 2013-07-26 19:30:37.000000000 +0000 @@ -18,6 +18,8 @@ #define INPUT_MT_POINTER 0x0001 /* pointer device, e.g. trackpad */ #define INPUT_MT_DIRECT 0x0002 /* direct device, e.g. touchscreen */ @@ -204,7 +208,7 @@ /** * struct input_mt_slot - represents the state of an input MT slot * @abs: holds current values of ABS_MT axes for this slot -@@ -39,6 +41,7 @@ struct input_mt { +@@ -39,6 +41,7 @@ unsigned int flags; unsigned int frame; unsigned int *slot_frame; @@ -212,7 +216,7 @@ struct input_mt_slot slots[]; }; -@@ -54,6 +57,11 @@ static inline int input_mt_get_value(con +@@ -54,6 +57,11 @@ return slot->abs[code - ABS_MT_FIRST]; } @@ -224,7 +228,7 @@ int input_mt_init_slots(struct input_dev *dev, unsigned int num_slots); int input_mt_init_slots_flags(struct input_dev *dev, unsigned int num_slots, unsigned int flags); -@@ -83,4 +91,16 @@ void input_mt_report_pointer_emulation(s +@@ -83,4 +91,16 @@ void input_mt_sync_frame(struct input_dev *dev); diff -Nru linux-3.2.46/debian/patches/features/all/input-mt/Input-MT-Handle-frame-synchronization-in-core.patch linux-3.2.46/debian/patches/features/all/input-mt/Input-MT-Handle-frame-synchronization-in-core.patch --- linux-3.2.46/debian/patches/features/all/input-mt/Input-MT-Handle-frame-synchronization-in-core.patch 2013-04-11 03:27:34.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/input-mt/Input-MT-Handle-frame-synchronization-in-core.patch 2013-07-26 19:30:36.000000000 +0000 @@ -21,8 +21,10 @@ [bwh: Backported to wheezy: - Add a separate array to track last frame each slot was used] --- ---- a/drivers/input/input-mt.c -+++ b/drivers/input/input-mt.c +Index: linux-3.2.46/drivers/input/input-mt.c +=================================================================== +--- linux-3.2.46.orig/drivers/input/input-mt.c 2013-07-26 19:30:34.000000000 +0000 ++++ linux-3.2.46/drivers/input/input-mt.c 2013-07-26 19:30:35.000000000 +0000 @@ -17,6 +17,14 @@ #define input_dev_to_mt(dev) \ ((dev)->mt ? container_of((dev)->mt, struct input_mt, slots[0]) : NULL) @@ -38,7 +40,7 @@ /** * input_mt_init_slots() - initialize MT input slots * @dev: input device supporting MT events and finger tracking -@@ -39,16 +47,41 @@ int input_mt_init_slots_flags(struct inp +@@ -39,16 +47,41 @@ if (dev->mt) return dev->mtsize != num_slots ? -EINVAL : 0; @@ -81,7 +83,7 @@ /* Mark slots as 'unused' */ for (i = 0; i < num_slots; i++) input_mt_set_value(&mt->slots[i], ABS_MT_TRACKING_ID, -1); -@@ -96,17 +129,23 @@ EXPORT_SYMBOL(input_mt_destroy_slots); +@@ -96,17 +129,23 @@ void input_mt_report_slot_state(struct input_dev *dev, unsigned int tool_type, bool active) { @@ -110,7 +112,7 @@ id = input_mt_new_trkid(dev); input_event(dev, EV_ABS, ABS_MT_TRACKING_ID, id); -@@ -183,3 +222,34 @@ void input_mt_report_pointer_emulation(s +@@ -183,3 +222,34 @@ } } EXPORT_SYMBOL(input_mt_report_pointer_emulation); @@ -145,8 +147,10 @@ + mt->frame++; +} +EXPORT_SYMBOL(input_mt_sync_frame); ---- a/include/linux/input/mt.h -+++ b/include/linux/input/mt.h +Index: linux-3.2.46/include/linux/input/mt.h +=================================================================== +--- linux-3.2.46.orig/include/linux/input/mt.h 2013-07-26 19:30:34.000000000 +0000 ++++ linux-3.2.46/include/linux/input/mt.h 2013-07-26 19:30:35.000000000 +0000 @@ -15,6 +15,9 @@ #define TRKID_MAX 0xffff @@ -157,7 +161,7 @@ /** * struct input_mt_slot - represents the state of an input MT slot * @abs: holds current values of ABS_MT axes for this slot -@@ -25,11 +28,17 @@ struct input_mt_slot { +@@ -25,11 +28,17 @@ /** * struct input_mt - state of tracked contacts @@ -175,7 +179,7 @@ struct input_mt_slot slots[]; }; -@@ -72,4 +81,6 @@ void input_mt_report_slot_state(struct i +@@ -72,4 +81,6 @@ void input_mt_report_finger_count(struct input_dev *dev, int count); void input_mt_report_pointer_emulation(struct input_dev *dev, bool use_count); diff -Nru linux-3.2.46/debian/patches/features/all/ipv6-Treat-ND-option-31-as-userland-DNSSL-support.patch linux-3.2.46/debian/patches/features/all/ipv6-Treat-ND-option-31-as-userland-DNSSL-support.patch --- linux-3.2.46/debian/patches/features/all/ipv6-Treat-ND-option-31-as-userland-DNSSL-support.patch 2013-02-24 03:52:32.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/ipv6-Treat-ND-option-31-as-userland-DNSSL-support.patch 2013-07-26 19:25:14.000000000 +0000 @@ -15,11 +15,11 @@ net/ipv6/ndisc.c | 4 +++- 2 files changed, 4 insertions(+), 1 deletion(-) -diff --git a/include/net/ndisc.h b/include/net/ndisc.h -index 6f9c25a..c02b6ad 100644 ---- a/include/net/ndisc.h -+++ b/include/net/ndisc.h -@@ -34,6 +34,7 @@ enum { +Index: linux-3.2.46/include/net/ndisc.h +=================================================================== +--- linux-3.2.46.orig/include/net/ndisc.h 2013-07-26 18:54:01.000000000 +0000 ++++ linux-3.2.46/include/net/ndisc.h 2013-07-26 19:25:13.000000000 +0000 +@@ -34,6 +34,7 @@ __ND_OPT_ARRAY_MAX, ND_OPT_ROUTE_INFO = 24, /* RFC4191 */ ND_OPT_RDNSS = 25, /* RFC5006 */ @@ -27,10 +27,10 @@ __ND_OPT_MAX }; -diff --git a/net/ipv6/ndisc.c b/net/ipv6/ndisc.c -index 1d6fb0c..7cb236e 100644 ---- a/net/ipv6/ndisc.c -+++ b/net/ipv6/ndisc.c +Index: linux-3.2.46/net/ipv6/ndisc.c +=================================================================== +--- linux-3.2.46.orig/net/ipv6/ndisc.c 2013-07-26 18:54:01.000000000 +0000 ++++ linux-3.2.46/net/ipv6/ndisc.c 2013-07-26 19:25:13.000000000 +0000 @@ -15,6 +15,7 @@ /* * Changes: @@ -39,7 +39,7 @@ * Pierre Ynard : export userland ND options * through netlink (RDNSS support) * Lars Fenneberg : fixed MTU setting on receipt -@@ -228,7 +229,8 @@ static struct nd_opt_hdr *ndisc_next_option(struct nd_opt_hdr *cur, +@@ -229,7 +230,8 @@ static inline int ndisc_is_useropt(struct nd_opt_hdr *opt) { diff -Nru linux-3.2.46/debian/patches/features/all/Kbuild-kconfig-Verbose-version-of-listnewconfig.patch linux-3.2.46/debian/patches/features/all/Kbuild-kconfig-Verbose-version-of-listnewconfig.patch --- linux-3.2.46/debian/patches/features/all/Kbuild-kconfig-Verbose-version-of-listnewconfig.patch 2013-02-24 03:52:42.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/Kbuild-kconfig-Verbose-version-of-listnewconfig.patch 2013-07-26 19:17:21.000000000 +0000 @@ -18,11 +18,11 @@ scripts/kconfig/lkc_proto.h | 1 + 4 files changed, 44 insertions(+), 10 deletions(-) -diff --git a/scripts/kconfig/conf.c b/scripts/kconfig/conf.c -index f208f90..ffaa787 100644 ---- a/scripts/kconfig/conf.c -+++ b/scripts/kconfig/conf.c -@@ -364,7 +364,6 @@ static void conf(struct menu *menu) +Index: linux-3.2.46/scripts/kconfig/conf.c +=================================================================== +--- linux-3.2.46.orig/scripts/kconfig/conf.c 2013-07-26 18:56:34.000000000 +0000 ++++ linux-3.2.46/scripts/kconfig/conf.c 2013-07-26 19:17:20.000000000 +0000 +@@ -364,7 +364,6 @@ switch (prop->type) { case P_MENU: if ((input_mode == silentoldconfig || @@ -30,7 +30,7 @@ input_mode == oldnoconfig) && rootEntry != menu) { check_conf(menu); -@@ -425,11 +424,7 @@ static void check_conf(struct menu *menu) +@@ -425,11 +424,7 @@ if (sym && !sym_has_value(sym)) { if (sym_is_changable(sym) || (sym_is_choice(sym) && sym_get_tristate_value(sym) == yes)) { @@ -43,7 +43,7 @@ if (!conf_cnt++) printf(_("*\n* Restart config...\n*\n")); rootEntry = menu_get_parent_menu(menu); -@@ -442,6 +437,30 @@ static void check_conf(struct menu *menu) +@@ -442,6 +437,30 @@ check_conf(child); } @@ -74,7 +74,7 @@ static struct option long_opts[] = { {"oldaskconfig", no_argument, NULL, oldaskconfig}, {"oldconfig", no_argument, NULL, oldconfig}, -@@ -482,6 +501,7 @@ int main(int ac, char **av) +@@ -482,6 +501,7 @@ const char *progname = av[0]; int opt; const char *name, *defconfig_file = NULL /* gcc uninit */; @@ -82,7 +82,7 @@ struct stat tmpstat; setlocale(LC_ALL, ""); -@@ -634,16 +654,18 @@ int main(int ac, char **av) +@@ -634,16 +654,18 @@ input_mode = silentoldconfig; /* fall through */ case oldconfig: @@ -105,11 +105,11 @@ break; } -diff --git a/scripts/kconfig/confdata.c b/scripts/kconfig/confdata.c -index 59b667c..d2be252 100644 ---- a/scripts/kconfig/confdata.c -+++ b/scripts/kconfig/confdata.c -@@ -695,6 +695,14 @@ next_menu: +Index: linux-3.2.46/scripts/kconfig/confdata.c +=================================================================== +--- linux-3.2.46.orig/scripts/kconfig/confdata.c 2013-07-26 18:56:34.000000000 +0000 ++++ linux-3.2.46/scripts/kconfig/confdata.c 2013-07-26 19:17:20.000000000 +0000 +@@ -713,6 +713,14 @@ return 0; } @@ -124,7 +124,7 @@ int conf_write(const char *name) { FILE *out; -@@ -1079,6 +1087,7 @@ void conf_set_all_new_symbols(enum conf_def_mode mode) +@@ -1102,6 +1110,7 @@ for_all_symbols(i, sym) { if (sym_has_value(sym)) continue; @@ -132,11 +132,11 @@ switch (sym_get_type(sym)) { case S_BOOLEAN: case S_TRISTATE: -diff --git a/scripts/kconfig/expr.h b/scripts/kconfig/expr.h -index 80fce57..0db77f3 100644 ---- a/scripts/kconfig/expr.h -+++ b/scripts/kconfig/expr.h -@@ -104,6 +104,8 @@ struct symbol { +Index: linux-3.2.46/scripts/kconfig/expr.h +=================================================================== +--- linux-3.2.46.orig/scripts/kconfig/expr.h 2013-07-26 18:56:34.000000000 +0000 ++++ linux-3.2.46/scripts/kconfig/expr.h 2013-07-26 19:17:20.000000000 +0000 +@@ -104,6 +104,8 @@ #define SYMBOL_DEF3 0x40000 /* symbol.def[S_DEF_3] is valid */ #define SYMBOL_DEF4 0x80000 /* symbol.def[S_DEF_4] is valid */ @@ -145,11 +145,11 @@ #define SYMBOL_MAXLENGTH 256 #define SYMBOL_HASHSIZE 9973 -diff --git a/scripts/kconfig/lkc_proto.h b/scripts/kconfig/lkc_proto.h -index 47fe9c3..dd0024a 100644 ---- a/scripts/kconfig/lkc_proto.h -+++ b/scripts/kconfig/lkc_proto.h -@@ -7,6 +7,7 @@ P(conf_read_simple,int,(const char *name, int)); +Index: linux-3.2.46/scripts/kconfig/lkc_proto.h +=================================================================== +--- linux-3.2.46.orig/scripts/kconfig/lkc_proto.h 2013-07-26 18:56:34.000000000 +0000 ++++ linux-3.2.46/scripts/kconfig/lkc_proto.h 2013-07-26 19:17:20.000000000 +0000 +@@ -7,6 +7,7 @@ P(conf_write_defconfig,int,(const char *name)); P(conf_write,int,(const char *name)); P(conf_write_autoconf,int,(void)); @@ -157,6 +157,3 @@ P(conf_get_changed,bool,(void)); P(conf_set_changed_callback, void,(void (*fn)(void))); P(conf_set_message_callback, void,(void (*fn)(const char *fmt, va_list ap))); --- -1.7.5.4 - diff -Nru linux-3.2.46/debian/patches/features/all/line6/0001-line6-fix-memory-leaks-in-line6_init_midi.patch linux-3.2.46/debian/patches/features/all/line6/0001-line6-fix-memory-leaks-in-line6_init_midi.patch --- linux-3.2.46/debian/patches/features/all/line6/0001-line6-fix-memory-leaks-in-line6_init_midi.patch 2013-02-24 03:52:35.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/line6/0001-line6-fix-memory-leaks-in-line6_init_midi.patch 2013-07-26 19:27:58.000000000 +0000 @@ -15,11 +15,11 @@ drivers/staging/line6/midi.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) -diff --git a/drivers/staging/line6/midi.c b/drivers/staging/line6/midi.c -index e554a2d..86c50cf 100644 ---- a/drivers/staging/line6/midi.c -+++ b/drivers/staging/line6/midi.c -@@ -391,12 +391,17 @@ int line6_init_midi(struct usb_line6 *line6) +Index: linux-3.2.46/drivers/staging/line6/midi.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/midi.c 2013-07-26 18:53:05.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/midi.c 2013-07-26 19:27:57.000000000 +0000 +@@ -391,12 +391,17 @@ return -ENOMEM; err = line6_midibuf_init(&line6midi->midibuf_in, MIDI_BUFFER_SIZE, 0); diff -Nru linux-3.2.46/debian/patches/features/all/line6/0002-staging-line6-add-Pod-HD300-support.patch linux-3.2.46/debian/patches/features/all/line6/0002-staging-line6-add-Pod-HD300-support.patch --- linux-3.2.46/debian/patches/features/all/line6/0002-staging-line6-add-Pod-HD300-support.patch 2013-02-24 03:52:35.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/line6/0002-staging-line6-add-Pod-HD300-support.patch 2013-07-26 19:28:00.000000000 +0000 @@ -25,21 +25,21 @@ create mode 100644 drivers/staging/line6/podhd.c create mode 100644 drivers/staging/line6/podhd.h -diff --git a/drivers/staging/line6/Makefile b/drivers/staging/line6/Makefile -index de6bd12..34a2dda 100644 ---- a/drivers/staging/line6/Makefile -+++ b/drivers/staging/line6/Makefile -@@ -12,4 +12,5 @@ line6usb-y := \ +Index: linux-3.2.46/drivers/staging/line6/Makefile +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/Makefile 2013-07-26 18:53:05.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/Makefile 2013-07-26 19:27:59.000000000 +0000 +@@ -12,4 +12,5 @@ playback.o \ pod.o \ toneport.o \ - variax.o + variax.o \ + podhd.o -diff --git a/drivers/staging/line6/driver.c b/drivers/staging/line6/driver.c -index 851b762..a71a5af 100644 ---- a/drivers/staging/line6/driver.c -+++ b/drivers/staging/line6/driver.c +Index: linux-3.2.46/drivers/staging/line6/driver.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/driver.c 2013-07-26 18:53:05.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/driver.c 2013-07-26 19:27:59.000000000 +0000 @@ -21,6 +21,7 @@ #include "midi.h" #include "playback.h" @@ -48,7 +48,7 @@ #include "revision.h" #include "toneport.h" #include "usbdefs.h" -@@ -49,6 +50,7 @@ static const struct usb_device_id line6_id_table[] = { +@@ -49,6 +50,7 @@ {USB_DEVICE(LINE6_VENDOR_ID, LINE6_DEVID_TONEPORT_UX1)}, {USB_DEVICE(LINE6_VENDOR_ID, LINE6_DEVID_TONEPORT_UX2)}, {USB_DEVICE(LINE6_VENDOR_ID, LINE6_DEVID_VARIAX)}, @@ -56,7 +56,7 @@ {}, }; -@@ -72,7 +74,8 @@ static struct line6_properties line6_properties_table[] = { +@@ -72,7 +74,8 @@ { "TonePortGX", "TonePort GX", LINE6_BIT_TONEPORT_GX, LINE6_BIT_PCM }, { "TonePortUX1", "TonePort UX1", LINE6_BIT_TONEPORT_UX1, LINE6_BIT_PCM }, { "TonePortUX2", "TonePort UX2", LINE6_BIT_TONEPORT_UX2, LINE6_BIT_PCM }, @@ -66,7 +66,7 @@ }; /* *INDENT-ON* */ -@@ -437,6 +440,9 @@ static void line6_data_received(struct urb *urb) +@@ -437,6 +440,9 @@ line6); break; @@ -76,7 +76,7 @@ case LINE6_DEVID_PODXTLIVE: switch (line6->interface_number) { case PODXTLIVE_INTERFACE_POD: -@@ -812,6 +818,7 @@ static int line6_probe(struct usb_interface *interface, +@@ -812,6 +818,7 @@ case LINE6_DEVID_BASSPODXTPRO: case LINE6_DEVID_PODXT: case LINE6_DEVID_PODXTPRO: @@ -84,7 +84,7 @@ alternate = 5; break; -@@ -865,6 +872,12 @@ static int line6_probe(struct usb_interface *interface, +@@ -865,6 +872,12 @@ ep_write = 0x03; break; @@ -97,7 +97,7 @@ case LINE6_DEVID_POCKETPOD: size = sizeof(struct usb_line6_pod); ep_read = 0x82; -@@ -1017,6 +1030,11 @@ static int line6_probe(struct usb_interface *interface, +@@ -1017,6 +1030,11 @@ ret = line6_pod_init(interface, (struct usb_line6_pod *)line6); break; @@ -109,7 +109,7 @@ case LINE6_DEVID_PODXTLIVE: switch (interface_number) { case PODXTLIVE_INTERFACE_POD: -@@ -1139,6 +1157,10 @@ static void line6_disconnect(struct usb_interface *interface) +@@ -1139,6 +1157,10 @@ line6_pod_disconnect(interface); break; @@ -120,11 +120,11 @@ case LINE6_DEVID_PODXTLIVE: switch (interface_number) { case PODXTLIVE_INTERFACE_POD: -diff --git a/drivers/staging/line6/pcm.c b/drivers/staging/line6/pcm.c -index 9d4c8a6..f56c642 100644 ---- a/drivers/staging/line6/pcm.c -+++ b/drivers/staging/line6/pcm.c -@@ -403,6 +403,7 @@ int line6_init_pcm(struct usb_line6 *line6, +Index: linux-3.2.46/drivers/staging/line6/pcm.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/pcm.c 2013-07-26 18:53:05.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/pcm.c 2013-07-26 19:27:59.000000000 +0000 +@@ -403,6 +403,7 @@ case LINE6_DEVID_PODXT: case LINE6_DEVID_PODXTLIVE: case LINE6_DEVID_PODXTPRO: @@ -132,11 +132,10 @@ ep_read = 0x82; ep_write = 0x01; break; -diff --git a/drivers/staging/line6/podhd.c b/drivers/staging/line6/podhd.c -new file mode 100644 -index 0000000..6c0f7f2 ---- /dev/null -+++ b/drivers/staging/line6/podhd.c +Index: linux-3.2.46/drivers/staging/line6/podhd.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/podhd.c 2013-07-26 19:27:59.000000000 +0000 @@ -0,0 +1,158 @@ +/* + * Line6 Pod HD @@ -296,11 +295,10 @@ + + podhd_destruct(interface); +} -diff --git a/drivers/staging/line6/podhd.h b/drivers/staging/line6/podhd.h -new file mode 100644 -index 0000000..652f740 ---- /dev/null -+++ b/drivers/staging/line6/podhd.h +Index: linux-3.2.46/drivers/staging/line6/podhd.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/podhd.h 2013-07-26 19:27:59.000000000 +0000 @@ -0,0 +1,30 @@ +/* + * Line6 Pod HD @@ -332,10 +330,10 @@ + struct usb_line6_podhd *podhd); + +#endif /* PODHD_H */ -diff --git a/drivers/staging/line6/usbdefs.h b/drivers/staging/line6/usbdefs.h -index c6dffe6..4e13364 100644 ---- a/drivers/staging/line6/usbdefs.h -+++ b/drivers/staging/line6/usbdefs.h +Index: linux-3.2.46/drivers/staging/line6/usbdefs.h +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/usbdefs.h 2013-07-26 18:53:05.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/usbdefs.h 2013-07-26 19:27:59.000000000 +0000 @@ -36,6 +36,7 @@ #define LINE6_DEVID_TONEPORT_UX1 0x4141 #define LINE6_DEVID_TONEPORT_UX2 0x4142 diff -Nru linux-3.2.46/debian/patches/features/all/line6/0003-staging-line6-add-missing-MIDI-postprocessing-case-f.patch linux-3.2.46/debian/patches/features/all/line6/0003-staging-line6-add-missing-MIDI-postprocessing-case-f.patch --- linux-3.2.46/debian/patches/features/all/line6/0003-staging-line6-add-missing-MIDI-postprocessing-case-f.patch 2013-02-24 03:52:35.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/line6/0003-staging-line6-add-missing-MIDI-postprocessing-case-f.patch 2013-07-26 19:28:01.000000000 +0000 @@ -17,11 +17,11 @@ drivers/staging/line6/midi.c | 1 + 1 file changed, 1 insertion(+) -diff --git a/drivers/staging/line6/midi.c b/drivers/staging/line6/midi.c -index 86c50cf..ed5577f 100644 ---- a/drivers/staging/line6/midi.c -+++ b/drivers/staging/line6/midi.c -@@ -173,6 +173,7 @@ static int send_midi_async(struct usb_line6 *line6, unsigned char *data, +Index: linux-3.2.46/drivers/staging/line6/midi.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/midi.c 2013-07-26 19:27:57.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/midi.c 2013-07-26 19:28:00.000000000 +0000 +@@ -173,6 +173,7 @@ break; case LINE6_DEVID_VARIAX: diff -Nru linux-3.2.46/debian/patches/features/all/line6/0004-staging-line6-use-smallest-iso-ep-packet-size.patch linux-3.2.46/debian/patches/features/all/line6/0004-staging-line6-use-smallest-iso-ep-packet-size.patch --- linux-3.2.46/debian/patches/features/all/line6/0004-staging-line6-use-smallest-iso-ep-packet-size.patch 2013-02-24 03:52:35.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/line6/0004-staging-line6-use-smallest-iso-ep-packet-size.patch 2013-07-26 19:28:03.000000000 +0000 @@ -20,11 +20,11 @@ drivers/staging/line6/pcm.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) -diff --git a/drivers/staging/line6/pcm.c b/drivers/staging/line6/pcm.c -index f56c642..ae98434 100644 ---- a/drivers/staging/line6/pcm.c -+++ b/drivers/staging/line6/pcm.c -@@ -452,9 +452,14 @@ int line6_init_pcm(struct usb_line6 *line6, +Index: linux-3.2.46/drivers/staging/line6/pcm.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/pcm.c 2013-07-26 19:27:59.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/pcm.c 2013-07-26 19:28:02.000000000 +0000 +@@ -452,9 +452,14 @@ line6pcm->line6 = line6; line6pcm->ep_audio_read = ep_read; line6pcm->ep_audio_write = ep_write; diff -Nru linux-3.2.46/debian/patches/features/all/line6/0005-staging-line6-alloc-free-buffers-in-hw_params-hw_fre.patch linux-3.2.46/debian/patches/features/all/line6/0005-staging-line6-alloc-free-buffers-in-hw_params-hw_fre.patch --- linux-3.2.46/debian/patches/features/all/line6/0005-staging-line6-alloc-free-buffers-in-hw_params-hw_fre.patch 2013-02-24 03:52:35.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/line6/0005-staging-line6-alloc-free-buffers-in-hw_params-hw_fre.patch 2013-07-26 19:28:04.000000000 +0000 @@ -25,10 +25,10 @@ drivers/staging/line6/playback.c | 15 +++++++++++++++ 3 files changed, 30 insertions(+), 24 deletions(-) -diff --git a/drivers/staging/line6/capture.c b/drivers/staging/line6/capture.c -index 9647154..d9da7ed 100644 ---- a/drivers/staging/line6/capture.c -+++ b/drivers/staging/line6/capture.c +Index: linux-3.2.46/drivers/staging/line6/capture.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/capture.c 2013-07-26 18:53:04.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/capture.c 2013-07-26 19:28:03.000000000 +0000 @@ -9,6 +9,7 @@ * */ @@ -37,7 +37,7 @@ #include #include #include -@@ -319,6 +320,15 @@ static int snd_line6_capture_hw_params(struct snd_pcm_substream *substream, +@@ -319,6 +320,15 @@ } /* -- [FD] end */ @@ -53,7 +53,7 @@ ret = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params)); if (ret < 0) -@@ -331,6 +341,11 @@ static int snd_line6_capture_hw_params(struct snd_pcm_substream *substream, +@@ -331,6 +341,11 @@ /* hw_free capture callback */ static int snd_line6_capture_hw_free(struct snd_pcm_substream *substream) { @@ -65,11 +65,11 @@ return snd_pcm_lib_free_pages(substream); } -diff --git a/drivers/staging/line6/pcm.c b/drivers/staging/line6/pcm.c -index ae98434..2e4e164 100644 ---- a/drivers/staging/line6/pcm.c -+++ b/drivers/staging/line6/pcm.c -@@ -119,16 +119,6 @@ int line6_pcm_start(struct snd_line6_pcm *line6pcm, int channels) +Index: linux-3.2.46/drivers/staging/line6/pcm.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/pcm.c 2013-07-26 19:28:02.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/pcm.c 2013-07-26 19:28:03.000000000 +0000 +@@ -119,16 +119,6 @@ if (line6pcm->active_urb_in | line6pcm->unlink_urb_in) return -EBUSY; @@ -86,7 +86,7 @@ line6pcm->count_in = 0; line6pcm->prev_fsize = 0; err = line6_submit_audio_in_all_urbs(line6pcm); -@@ -147,16 +137,6 @@ int line6_pcm_start(struct snd_line6_pcm *line6pcm, int channels) +@@ -147,16 +137,6 @@ if (line6pcm->active_urb_out | line6pcm->unlink_urb_out) return -EBUSY; @@ -103,7 +103,7 @@ line6pcm->count_out = 0; err = line6_submit_audio_out_all_urbs(line6pcm); -@@ -178,15 +158,11 @@ int line6_pcm_stop(struct snd_line6_pcm *line6pcm, int channels) +@@ -178,15 +158,11 @@ if (((flags_old & MASK_CAPTURE) != 0) && ((flags_new & MASK_CAPTURE) == 0)) { line6_unlink_audio_in_urbs(line6pcm); @@ -119,10 +119,10 @@ } #if LINE6_BACKUP_MONITOR_SIGNAL kfree(line6pcm->prev_fbuf); -diff --git a/drivers/staging/line6/playback.c b/drivers/staging/line6/playback.c -index 10c5438..b344527 100644 ---- a/drivers/staging/line6/playback.c -+++ b/drivers/staging/line6/playback.c +Index: linux-3.2.46/drivers/staging/line6/playback.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/playback.c 2013-07-26 18:53:04.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/playback.c 2013-07-26 19:28:03.000000000 +0000 @@ -9,6 +9,7 @@ * */ @@ -131,7 +131,7 @@ #include #include #include -@@ -469,6 +470,15 @@ static int snd_line6_playback_hw_params(struct snd_pcm_substream *substream, +@@ -469,6 +470,15 @@ } /* -- [FD] end */ @@ -147,7 +147,7 @@ ret = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params)); if (ret < 0) -@@ -481,6 +491,11 @@ static int snd_line6_playback_hw_params(struct snd_pcm_substream *substream, +@@ -481,6 +491,11 @@ /* hw_free playback callback */ static int snd_line6_playback_hw_free(struct snd_pcm_substream *substream) { diff -Nru linux-3.2.46/debian/patches/features/all/line6/0006-Staging-line6-Use-kmemdup-rather-than-duplicating-it.patch linux-3.2.46/debian/patches/features/all/line6/0006-Staging-line6-Use-kmemdup-rather-than-duplicating-it.patch --- linux-3.2.46/debian/patches/features/all/line6/0006-Staging-line6-Use-kmemdup-rather-than-duplicating-it.patch 2013-02-24 03:52:35.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/line6/0006-Staging-line6-Use-kmemdup-rather-than-duplicating-it.patch 2013-07-26 19:28:05.000000000 +0000 @@ -19,11 +19,11 @@ drivers/staging/line6/midi.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) -diff --git a/drivers/staging/line6/midi.c b/drivers/staging/line6/midi.c -index ed5577f..7f1e90e 100644 ---- a/drivers/staging/line6/midi.c -+++ b/drivers/staging/line6/midi.c -@@ -135,7 +135,7 @@ static int send_midi_async(struct usb_line6 *line6, unsigned char *data, +Index: linux-3.2.46/drivers/staging/line6/midi.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/midi.c 2013-07-26 19:28:00.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/midi.c 2013-07-26 19:28:04.000000000 +0000 +@@ -135,7 +135,7 @@ line6_write_hexdump(line6, 'S', data, length); #endif @@ -32,7 +32,7 @@ if (transfer_buffer == NULL) { usb_free_urb(urb); -@@ -143,7 +143,6 @@ static int send_midi_async(struct usb_line6 *line6, unsigned char *data, +@@ -143,7 +143,6 @@ return -ENOMEM; } diff -Nru linux-3.2.46/debian/patches/features/all/line6/0007-Staging-line6-NULL-dereference-in-dev_err.patch linux-3.2.46/debian/patches/features/all/line6/0007-Staging-line6-NULL-dereference-in-dev_err.patch --- linux-3.2.46/debian/patches/features/all/line6/0007-Staging-line6-NULL-dereference-in-dev_err.patch 2013-02-24 03:52:35.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/line6/0007-Staging-line6-NULL-dereference-in-dev_err.patch 2013-07-26 19:28:07.000000000 +0000 @@ -17,11 +17,11 @@ drivers/staging/line6/driver.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) -diff --git a/drivers/staging/line6/driver.c b/drivers/staging/line6/driver.c -index a71a5af..a2f48ee 100644 ---- a/drivers/staging/line6/driver.c -+++ b/drivers/staging/line6/driver.c -@@ -726,8 +726,8 @@ static int line6_probe(struct usb_interface *interface, +Index: linux-3.2.46/drivers/staging/line6/driver.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/driver.c 2013-07-26 19:27:59.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/driver.c 2013-07-26 19:28:06.000000000 +0000 +@@ -726,8 +726,8 @@ const struct usb_device_id *id) { int devtype; @@ -32,7 +32,7 @@ const struct line6_properties *properties; int devnum; int interface_number, alternate = 0; -@@ -936,7 +936,7 @@ static int line6_probe(struct usb_interface *interface, +@@ -936,7 +936,7 @@ } if (size == 0) { diff -Nru linux-3.2.46/debian/patches/features/all/line6/0008-Staging-line6-midi.c-Fixed-call-of-obsolete-function.patch linux-3.2.46/debian/patches/features/all/line6/0008-Staging-line6-midi.c-Fixed-call-of-obsolete-function.patch --- linux-3.2.46/debian/patches/features/all/line6/0008-Staging-line6-midi.c-Fixed-call-of-obsolete-function.patch 2013-02-24 03:52:35.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/line6/0008-Staging-line6-midi.c-Fixed-call-of-obsolete-function.patch 2013-07-26 19:28:08.000000000 +0000 @@ -18,11 +18,11 @@ drivers/staging/line6/midi.h | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) -diff --git a/drivers/staging/line6/midi.c b/drivers/staging/line6/midi.c -index 7f1e90e..3d1ada6 100644 ---- a/drivers/staging/line6/midi.c -+++ b/drivers/staging/line6/midi.c -@@ -307,10 +307,10 @@ static ssize_t midi_set_midi_mask_transmit(struct device *dev, +Index: linux-3.2.46/drivers/staging/line6/midi.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/midi.c 2013-07-26 19:28:04.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/midi.c 2013-07-26 19:28:07.000000000 +0000 +@@ -307,10 +307,10 @@ { struct usb_interface *interface = to_usb_interface(dev); struct usb_line6 *line6 = usb_get_intfdata(interface); @@ -35,11 +35,11 @@ if (ret) return ret; -diff --git a/drivers/staging/line6/midi.h b/drivers/staging/line6/midi.h -index b73a025..2c0a663 100644 ---- a/drivers/staging/line6/midi.h -+++ b/drivers/staging/line6/midi.h -@@ -57,7 +57,7 @@ struct snd_line6_midi { +Index: linux-3.2.46/drivers/staging/line6/midi.h +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/midi.h 2013-07-26 18:53:02.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/midi.h 2013-07-26 19:28:07.000000000 +0000 +@@ -57,7 +57,7 @@ /** Bit mask for output MIDI channels. */ diff -Nru linux-3.2.46/debian/patches/features/all/line6/0009-Staging-line6-midi.c-Fixed-call-of-obsolete-function.patch linux-3.2.46/debian/patches/features/all/line6/0009-Staging-line6-midi.c-Fixed-call-of-obsolete-function.patch --- linux-3.2.46/debian/patches/features/all/line6/0009-Staging-line6-midi.c-Fixed-call-of-obsolete-function.patch 2013-02-24 03:52:35.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/line6/0009-Staging-line6-midi.c-Fixed-call-of-obsolete-function.patch 2013-07-26 19:28:09.000000000 +0000 @@ -19,11 +19,11 @@ drivers/staging/line6/midi.h | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) -diff --git a/drivers/staging/line6/midi.c b/drivers/staging/line6/midi.c -index 3d1ada6..3013fb5 100644 ---- a/drivers/staging/line6/midi.c -+++ b/drivers/staging/line6/midi.c -@@ -339,10 +339,10 @@ static ssize_t midi_set_midi_mask_receive(struct device *dev, +Index: linux-3.2.46/drivers/staging/line6/midi.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/midi.c 2013-07-26 19:28:07.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/midi.c 2013-07-26 19:28:08.000000000 +0000 +@@ -339,10 +339,10 @@ { struct usb_interface *interface = to_usb_interface(dev); struct usb_line6 *line6 = usb_get_intfdata(interface); @@ -36,11 +36,11 @@ if (ret) return ret; -diff --git a/drivers/staging/line6/midi.h b/drivers/staging/line6/midi.h -index 2c0a663..4a9e9f9 100644 ---- a/drivers/staging/line6/midi.h -+++ b/drivers/staging/line6/midi.h -@@ -62,7 +62,7 @@ struct snd_line6_midi { +Index: linux-3.2.46/drivers/staging/line6/midi.h +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/midi.h 2013-07-26 19:28:07.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/midi.h 2013-07-26 19:28:08.000000000 +0000 +@@ -62,7 +62,7 @@ /** Bit mask for input MIDI channels. */ diff -Nru linux-3.2.46/debian/patches/features/all/line6/0010-staging-line6-Remove-obsolete-code.patch linux-3.2.46/debian/patches/features/all/line6/0010-staging-line6-Remove-obsolete-code.patch --- linux-3.2.46/debian/patches/features/all/line6/0010-staging-line6-Remove-obsolete-code.patch 2013-02-24 03:52:35.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/line6/0010-staging-line6-Remove-obsolete-code.patch 2013-07-26 19:28:11.000000000 +0000 @@ -15,11 +15,11 @@ drivers/staging/line6/playback.c | 8 -------- 4 files changed, 32 deletions(-) -diff --git a/drivers/staging/line6/capture.c b/drivers/staging/line6/capture.c -index d9da7ed..ba441ed 100644 ---- a/drivers/staging/line6/capture.c -+++ b/drivers/staging/line6/capture.c -@@ -244,11 +244,7 @@ static void audio_in_callback(struct urb *urb) +Index: linux-3.2.46/drivers/staging/line6/capture.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/capture.c 2013-07-26 19:28:03.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/capture.c 2013-07-26 19:28:10.000000000 +0000 +@@ -244,11 +244,7 @@ length += fsize; /* the following assumes LINE6_ISO_PACKETS == 1: */ @@ -31,11 +31,11 @@ line6pcm->prev_fsize = fsize; #ifdef CONFIG_LINE6_USB_IMPULSE_RESPONSE -diff --git a/drivers/staging/line6/pcm.c b/drivers/staging/line6/pcm.c -index 2e4e164..a70c087 100644 ---- a/drivers/staging/line6/pcm.c -+++ b/drivers/staging/line6/pcm.c -@@ -93,21 +93,7 @@ int line6_pcm_start(struct snd_line6_pcm *line6pcm, int channels) +Index: linux-3.2.46/drivers/staging/line6/pcm.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/pcm.c 2013-07-26 19:28:03.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/pcm.c 2013-07-26 19:28:10.000000000 +0000 +@@ -93,21 +93,7 @@ unsigned long flags_new = flags_old | channels; int err = 0; @@ -57,7 +57,7 @@ if (((flags_old & MASK_CAPTURE) == 0) && ((flags_new & MASK_CAPTURE) != 0)) { -@@ -164,9 +150,6 @@ int line6_pcm_stop(struct snd_line6_pcm *line6pcm, int channels) +@@ -164,9 +150,6 @@ ((flags_new & MASK_PLAYBACK) == 0)) { line6_unlink_audio_out_urbs(line6pcm); } @@ -67,10 +67,10 @@ return 0; } -diff --git a/drivers/staging/line6/pcm.h b/drivers/staging/line6/pcm.h -index 77055b3..05f4ef3 100644 ---- a/drivers/staging/line6/pcm.h -+++ b/drivers/staging/line6/pcm.h +Index: linux-3.2.46/drivers/staging/line6/pcm.h +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/pcm.h 2013-07-26 18:53:00.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/pcm.h 2013-07-26 19:28:10.000000000 +0000 @@ -39,9 +39,6 @@ #define LINE6_IMPULSE_DEFAULT_PERIOD 100 #endif @@ -81,11 +81,11 @@ /* Get substream from Line6 PCM data structure */ -diff --git a/drivers/staging/line6/playback.c b/drivers/staging/line6/playback.c -index b344527..e495b32 100644 ---- a/drivers/staging/line6/playback.c -+++ b/drivers/staging/line6/playback.c -@@ -223,18 +223,10 @@ static int submit_audio_out_urb(struct snd_line6_pcm *line6pcm) +Index: linux-3.2.46/drivers/staging/line6/playback.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/playback.c 2013-07-26 19:28:03.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/playback.c 2013-07-26 19:28:10.000000000 +0000 +@@ -223,18 +223,10 @@ } else dev_err(line6pcm->line6->ifcdev, "driver bug: len = %d\n", len); /* this is somewhat paranoid */ } else { diff -Nru linux-3.2.46/debian/patches/features/all/line6/0011-staging-line6-refactor-device-information-and-add-PO.patch linux-3.2.46/debian/patches/features/all/line6/0011-staging-line6-refactor-device-information-and-add-PO.patch --- linux-3.2.46/debian/patches/features/all/line6/0011-staging-line6-refactor-device-information-and-add-PO.patch 2013-02-24 03:52:35.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/line6/0011-staging-line6-refactor-device-information-and-add-PO.patch 2013-07-26 19:28:12.000000000 +0000 @@ -17,11 +17,11 @@ drivers/staging/line6/usbdefs.h | 93 ++++++++++++++++++++++++--------------- 5 files changed, 109 insertions(+), 61 deletions(-) -diff --git a/drivers/staging/line6/driver.c b/drivers/staging/line6/driver.c -index a2f48ee..6a1959e 100644 ---- a/drivers/staging/line6/driver.c -+++ b/drivers/staging/line6/driver.c -@@ -38,6 +38,8 @@ static const struct usb_device_id line6_id_table[] = { +Index: linux-3.2.46/drivers/staging/line6/driver.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/driver.c 2013-07-26 19:28:06.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/driver.c 2013-07-26 19:28:11.000000000 +0000 +@@ -38,6 +38,8 @@ {USB_DEVICE(LINE6_VENDOR_ID, LINE6_DEVID_BASSPODXTPRO)}, {USB_DEVICE(LINE6_VENDOR_ID, LINE6_DEVID_GUITARPORT)}, {USB_DEVICE(LINE6_VENDOR_ID, LINE6_DEVID_POCKETPOD)}, @@ -30,7 +30,7 @@ {USB_DEVICE(LINE6_VENDOR_ID, LINE6_DEVID_PODSTUDIO_GX)}, {USB_DEVICE(LINE6_VENDOR_ID, LINE6_DEVID_PODSTUDIO_UX1)}, {USB_DEVICE(LINE6_VENDOR_ID, LINE6_DEVID_PODSTUDIO_UX2)}, -@@ -50,7 +52,6 @@ static const struct usb_device_id line6_id_table[] = { +@@ -50,7 +52,6 @@ {USB_DEVICE(LINE6_VENDOR_ID, LINE6_DEVID_TONEPORT_UX1)}, {USB_DEVICE(LINE6_VENDOR_ID, LINE6_DEVID_TONEPORT_UX2)}, {USB_DEVICE(LINE6_VENDOR_ID, LINE6_DEVID_VARIAX)}, @@ -38,7 +38,7 @@ {}, }; -@@ -58,24 +59,25 @@ MODULE_DEVICE_TABLE(usb, line6_id_table); +@@ -58,24 +59,25 @@ /* *INDENT-OFF* */ static struct line6_properties line6_properties_table[] = { @@ -82,7 +82,7 @@ }; /* *INDENT-ON* */ -@@ -441,6 +443,7 @@ static void line6_data_received(struct urb *urb) +@@ -441,6 +443,7 @@ break; case LINE6_DEVID_PODHD300: @@ -90,7 +90,7 @@ break; /* let userspace handle MIDI */ case LINE6_DEVID_PODXTLIVE: -@@ -800,6 +803,7 @@ static int line6_probe(struct usb_interface *interface, +@@ -800,6 +803,7 @@ } break; @@ -98,7 +98,7 @@ case LINE6_DEVID_PODX3: case LINE6_DEVID_PODX3LIVE: switch (interface_number) { -@@ -878,6 +882,12 @@ static int line6_probe(struct usb_interface *interface, +@@ -878,6 +882,12 @@ ep_write = 0x03; break; @@ -111,7 +111,7 @@ case LINE6_DEVID_POCKETPOD: size = sizeof(struct usb_line6_pod); ep_read = 0x82; -@@ -1031,6 +1041,7 @@ static int line6_probe(struct usb_interface *interface, +@@ -1031,6 +1041,7 @@ break; case LINE6_DEVID_PODHD300: @@ -119,7 +119,7 @@ ret = line6_podhd_init(interface, (struct usb_line6_podhd *)line6); break; -@@ -1158,6 +1169,7 @@ static void line6_disconnect(struct usb_interface *interface) +@@ -1158,6 +1169,7 @@ break; case LINE6_DEVID_PODHD300: @@ -127,11 +127,11 @@ line6_podhd_disconnect(interface); break; -diff --git a/drivers/staging/line6/driver.h b/drivers/staging/line6/driver.h -index 553192f..117bf99 100644 ---- a/drivers/staging/line6/driver.h -+++ b/drivers/staging/line6/driver.h -@@ -88,6 +88,11 @@ static const int SYSEX_EXTRA_SIZE = sizeof(line6_midi_id) + 4; +Index: linux-3.2.46/drivers/staging/line6/driver.h +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/driver.h 2013-07-26 18:53:00.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/driver.h 2013-07-26 19:28:11.000000000 +0000 +@@ -88,6 +88,11 @@ */ struct line6_properties { /** @@ -143,7 +143,7 @@ Card id string (maximum 16 characters). This can be used to address the device in ALSA programs as "default:CARD=" -@@ -100,11 +105,6 @@ struct line6_properties { +@@ -100,11 +105,6 @@ const char *name; /** @@ -155,11 +155,11 @@ Bit vector defining this device's capabilities in the line6usb driver. */ -diff --git a/drivers/staging/line6/midi.c b/drivers/staging/line6/midi.c -index 3013fb5..13d0293 100644 ---- a/drivers/staging/line6/midi.c -+++ b/drivers/staging/line6/midi.c -@@ -173,6 +173,7 @@ static int send_midi_async(struct usb_line6 *line6, unsigned char *data, +Index: linux-3.2.46/drivers/staging/line6/midi.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/midi.c 2013-07-26 19:28:08.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/midi.c 2013-07-26 19:28:11.000000000 +0000 +@@ -173,6 +173,7 @@ case LINE6_DEVID_VARIAX: case LINE6_DEVID_PODHD300: @@ -167,7 +167,7 @@ break; default: -@@ -404,8 +405,19 @@ int line6_init_midi(struct usb_line6 *line6) +@@ -404,8 +405,19 @@ } line6midi->line6 = line6; @@ -189,11 +189,11 @@ line6->line6midi = line6midi; err = snd_device_new(line6->card, SNDRV_DEV_RAWMIDI, line6midi, -diff --git a/drivers/staging/line6/pcm.c b/drivers/staging/line6/pcm.c -index a70c087..c3e5002 100644 ---- a/drivers/staging/line6/pcm.c -+++ b/drivers/staging/line6/pcm.c -@@ -367,6 +367,7 @@ int line6_init_pcm(struct usb_line6 *line6, +Index: linux-3.2.46/drivers/staging/line6/pcm.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/pcm.c 2013-07-26 19:28:10.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/pcm.c 2013-07-26 19:28:11.000000000 +0000 +@@ -367,6 +367,7 @@ ep_write = 0x01; break; @@ -201,10 +201,10 @@ case LINE6_DEVID_PODX3: case LINE6_DEVID_PODX3LIVE: ep_read = 0x86; -diff --git a/drivers/staging/line6/usbdefs.h b/drivers/staging/line6/usbdefs.h -index 4e13364..aff9e5c 100644 ---- a/drivers/staging/line6/usbdefs.h -+++ b/drivers/staging/line6/usbdefs.h +Index: linux-3.2.46/drivers/staging/line6/usbdefs.h +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/usbdefs.h 2013-07-26 19:27:59.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/usbdefs.h 2013-07-26 19:28:11.000000000 +0000 @@ -24,6 +24,8 @@ #define LINE6_DEVID_BASSPODXTPRO 0x4252 #define LINE6_DEVID_GUITARPORT 0x4750 @@ -238,6 +238,18 @@ -#define LINE6_BIT_TONEPORT_UX2 (1 << 15) -#define LINE6_BIT_VARIAX (1 << 16) -#define LINE6_BIT_PODHD300 (1 << 17) +- +-#define LINE6_BITS_PRO (LINE6_BIT_BASSPODXTPRO | \ +- LINE6_BIT_PODXTPRO) +-#define LINE6_BITS_LIVE (LINE6_BIT_BASSPODXTLIVE | \ +- LINE6_BIT_PODXTLIVE | \ +- LINE6_BIT_PODX3LIVE) +-#define LINE6_BITS_PODXTALL (LINE6_BIT_PODXT | \ +- LINE6_BIT_PODXTLIVE | \ +- LINE6_BIT_PODXTPRO) +-#define LINE6_BITS_BASSPODXTALL (LINE6_BIT_BASSPODXT | \ +- LINE6_BIT_BASSPODXTLIVE | \ +- LINE6_BIT_BASSPODXTPRO) +enum { + LINE6_ID_BASSPODXT, + LINE6_ID_BASSPODXTLIVE, @@ -282,18 +294,7 @@ + LINE6_BIT(TONEPORT_UX1), + LINE6_BIT(TONEPORT_UX2), + LINE6_BIT(VARIAX), - --#define LINE6_BITS_PRO (LINE6_BIT_BASSPODXTPRO | \ -- LINE6_BIT_PODXTPRO) --#define LINE6_BITS_LIVE (LINE6_BIT_BASSPODXTLIVE | \ -- LINE6_BIT_PODXTLIVE | \ -- LINE6_BIT_PODX3LIVE) --#define LINE6_BITS_PODXTALL (LINE6_BIT_PODXT | \ -- LINE6_BIT_PODXTLIVE | \ -- LINE6_BIT_PODXTPRO) --#define LINE6_BITS_BASSPODXTALL (LINE6_BIT_BASSPODXT | \ -- LINE6_BIT_BASSPODXTLIVE | \ -- LINE6_BIT_BASSPODXTPRO) ++ + LINE6_BITS_PRO = LINE6_BIT_BASSPODXTPRO | LINE6_BIT_PODXTPRO, + LINE6_BITS_LIVE = LINE6_BIT_BASSPODXTLIVE | LINE6_BIT_PODXTLIVE | LINE6_BIT_PODX3LIVE, + LINE6_BITS_PODXTALL = LINE6_BIT_PODXT | LINE6_BIT_PODXTLIVE | LINE6_BIT_PODXTPRO, diff -Nru linux-3.2.46/debian/patches/features/all/line6/0012-staging-line6-fix-memory-leak-in-.hw_params.patch linux-3.2.46/debian/patches/features/all/line6/0012-staging-line6-fix-memory-leak-in-.hw_params.patch --- linux-3.2.46/debian/patches/features/all/line6/0012-staging-line6-fix-memory-leak-in-.hw_params.patch 2013-02-24 03:52:35.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/line6/0012-staging-line6-fix-memory-leak-in-.hw_params.patch 2013-07-26 19:28:14.000000000 +0000 @@ -15,11 +15,11 @@ drivers/staging/line6/playback.c | 7 +++++-- 2 files changed, 10 insertions(+), 4 deletions(-) -diff --git a/drivers/staging/line6/capture.c b/drivers/staging/line6/capture.c -index ba441ed..8f59ff3 100644 ---- a/drivers/staging/line6/capture.c -+++ b/drivers/staging/line6/capture.c -@@ -316,8 +316,11 @@ static int snd_line6_capture_hw_params(struct snd_pcm_substream *substream, +Index: linux-3.2.46/drivers/staging/line6/capture.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/capture.c 2013-07-26 19:28:10.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/capture.c 2013-07-26 19:28:13.000000000 +0000 +@@ -316,8 +316,11 @@ } /* -- [FD] end */ @@ -33,11 +33,11 @@ if (!line6pcm->buffer_in) { dev_err(line6pcm->line6->ifcdev, -diff --git a/drivers/staging/line6/playback.c b/drivers/staging/line6/playback.c -index e495b32..ed1b9bd 100644 ---- a/drivers/staging/line6/playback.c -+++ b/drivers/staging/line6/playback.c -@@ -462,8 +462,11 @@ static int snd_line6_playback_hw_params(struct snd_pcm_substream *substream, +Index: linux-3.2.46/drivers/staging/line6/playback.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/playback.c 2013-07-26 19:28:10.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/playback.c 2013-07-26 19:28:13.000000000 +0000 +@@ -462,8 +462,11 @@ } /* -- [FD] end */ diff -Nru linux-3.2.46/debian/patches/features/all/line6/0013-staging-line6-fix-playback-urb-transfer-buffer-calcu.patch linux-3.2.46/debian/patches/features/all/line6/0013-staging-line6-fix-playback-urb-transfer-buffer-calcu.patch --- linux-3.2.46/debian/patches/features/all/line6/0013-staging-line6-fix-playback-urb-transfer-buffer-calcu.patch 2013-02-24 03:52:35.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/line6/0013-staging-line6-fix-playback-urb-transfer-buffer-calcu.patch 2013-07-26 19:28:15.000000000 +0000 @@ -22,11 +22,11 @@ drivers/staging/line6/playback.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -diff --git a/drivers/staging/line6/playback.c b/drivers/staging/line6/playback.c -index ed1b9bd..b17c0a7 100644 ---- a/drivers/staging/line6/playback.c -+++ b/drivers/staging/line6/playback.c -@@ -192,7 +192,7 @@ static int submit_audio_out_urb(struct snd_line6_pcm *line6pcm) +Index: linux-3.2.46/drivers/staging/line6/playback.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/playback.c 2013-07-26 19:28:13.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/playback.c 2013-07-26 19:28:14.000000000 +0000 +@@ -192,7 +192,7 @@ urb_frames = urb_size / bytes_per_frame; urb_out->transfer_buffer = line6pcm->buffer_out + diff -Nru linux-3.2.46/debian/patches/features/all/line6/0014-staging-line6-eliminate-useless-index_out-variable.patch linux-3.2.46/debian/patches/features/all/line6/0014-staging-line6-eliminate-useless-index_out-variable.patch --- linux-3.2.46/debian/patches/features/all/line6/0014-staging-line6-eliminate-useless-index_out-variable.patch 2013-02-24 03:52:35.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/line6/0014-staging-line6-eliminate-useless-index_out-variable.patch 2013-07-26 19:28:16.000000000 +0000 @@ -21,11 +21,11 @@ drivers/staging/line6/playback.c | 5 +---- 2 files changed, 1 insertion(+), 9 deletions(-) -diff --git a/drivers/staging/line6/pcm.h b/drivers/staging/line6/pcm.h -index 05f4ef3..55d8297 100644 ---- a/drivers/staging/line6/pcm.h -+++ b/drivers/staging/line6/pcm.h -@@ -146,11 +146,6 @@ struct snd_line6_pcm { +Index: linux-3.2.46/drivers/staging/line6/pcm.h +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/pcm.h 2013-07-26 19:28:10.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/pcm.h 2013-07-26 19:28:15.000000000 +0000 +@@ -146,11 +146,6 @@ unsigned char *buffer_in; /** @@ -37,11 +37,11 @@ Previously captured frame (for software monitoring). */ unsigned char *prev_fbuf; -diff --git a/drivers/staging/line6/playback.c b/drivers/staging/line6/playback.c -index b17c0a7..9a51b92 100644 ---- a/drivers/staging/line6/playback.c -+++ b/drivers/staging/line6/playback.c -@@ -192,13 +192,10 @@ static int submit_audio_out_urb(struct snd_line6_pcm *line6pcm) +Index: linux-3.2.46/drivers/staging/line6/playback.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/playback.c 2013-07-26 19:28:14.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/playback.c 2013-07-26 19:28:15.000000000 +0000 +@@ -192,13 +192,10 @@ urb_frames = urb_size / bytes_per_frame; urb_out->transfer_buffer = line6pcm->buffer_out + diff -Nru linux-3.2.46/debian/patches/features/all/line6/0015-staging-line6-eliminate-useless-NULL-checks.patch linux-3.2.46/debian/patches/features/all/line6/0015-staging-line6-eliminate-useless-NULL-checks.patch --- linux-3.2.46/debian/patches/features/all/line6/0015-staging-line6-eliminate-useless-NULL-checks.patch 2013-02-24 03:52:35.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/line6/0015-staging-line6-eliminate-useless-NULL-checks.patch 2013-07-26 19:28:18.000000000 +0000 @@ -19,11 +19,11 @@ drivers/staging/line6/variax.c | 6 +----- 4 files changed, 4 insertions(+), 20 deletions(-) -diff --git a/drivers/staging/line6/pod.c b/drivers/staging/line6/pod.c -index d9b3021..4dadc57 100644 ---- a/drivers/staging/line6/pod.c -+++ b/drivers/staging/line6/pod.c -@@ -1149,14 +1149,10 @@ static struct snd_kcontrol_new pod_control_monitor = { +Index: linux-3.2.46/drivers/staging/line6/pod.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/pod.c 2013-07-26 18:52:59.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/pod.c 2013-07-26 19:28:17.000000000 +0000 +@@ -1149,14 +1149,10 @@ static void pod_destruct(struct usb_interface *interface) { struct usb_line6_pod *pod = usb_get_intfdata(interface); @@ -39,11 +39,11 @@ del_timer(&pod->startup_timer); cancel_work_sync(&pod->startup_work); -diff --git a/drivers/staging/line6/podhd.c b/drivers/staging/line6/podhd.c -index 6c0f7f2..7ef4543 100644 ---- a/drivers/staging/line6/podhd.c -+++ b/drivers/staging/line6/podhd.c -@@ -80,14 +80,10 @@ static struct line6_pcm_properties podhd_pcm_properties = { +Index: linux-3.2.46/drivers/staging/line6/podhd.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/podhd.c 2013-07-26 19:27:59.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/podhd.c 2013-07-26 19:28:17.000000000 +0000 +@@ -80,14 +80,10 @@ static void podhd_destruct(struct usb_interface *interface) { struct usb_line6_podhd *podhd = usb_get_intfdata(interface); @@ -59,11 +59,11 @@ } /* -diff --git a/drivers/staging/line6/toneport.c b/drivers/staging/line6/toneport.c -index 879e699..f310578 100644 ---- a/drivers/staging/line6/toneport.c -+++ b/drivers/staging/line6/toneport.c -@@ -295,14 +295,10 @@ static struct snd_kcontrol_new toneport_control_source = { +Index: linux-3.2.46/drivers/staging/line6/toneport.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/toneport.c 2013-07-26 18:52:59.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/toneport.c 2013-07-26 19:28:17.000000000 +0000 +@@ -295,14 +295,10 @@ static void toneport_destruct(struct usb_interface *interface) { struct usb_line6_toneport *toneport = usb_get_intfdata(interface); @@ -79,11 +79,11 @@ } /* -diff --git a/drivers/staging/line6/variax.c b/drivers/staging/line6/variax.c -index 81241cd..d366222 100644 ---- a/drivers/staging/line6/variax.c -+++ b/drivers/staging/line6/variax.c -@@ -572,14 +572,10 @@ static DEVICE_ATTR(raw2, S_IWUSR, line6_nop_read, variax_set_raw2); +Index: linux-3.2.46/drivers/staging/line6/variax.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/variax.c 2013-07-26 18:52:59.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/variax.c 2013-07-26 19:28:17.000000000 +0000 +@@ -572,14 +572,10 @@ static void variax_destruct(struct usb_interface *interface) { struct usb_line6_variax *variax = usb_get_intfdata(interface); diff -Nru linux-3.2.46/debian/patches/features/all/line6/0016-staging-line6-wait-for-urbs-in-snd_line6_prepare.patch linux-3.2.46/debian/patches/features/all/line6/0016-staging-line6-wait-for-urbs-in-snd_line6_prepare.patch --- linux-3.2.46/debian/patches/features/all/line6/0016-staging-line6-wait-for-urbs-in-snd_line6_prepare.patch 2013-02-24 03:52:35.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/line6/0016-staging-line6-wait-for-urbs-in-snd_line6_prepare.patch 2013-07-26 19:28:19.000000000 +0000 @@ -24,11 +24,11 @@ drivers/staging/line6/pcm.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) -diff --git a/drivers/staging/line6/pcm.c b/drivers/staging/line6/pcm.c -index c3e5002..68727b2 100644 ---- a/drivers/staging/line6/pcm.c -+++ b/drivers/staging/line6/pcm.c -@@ -474,6 +474,20 @@ int snd_line6_prepare(struct snd_pcm_substream *substream) +Index: linux-3.2.46/drivers/staging/line6/pcm.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/pcm.c 2013-07-26 19:28:11.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/pcm.c 2013-07-26 19:28:18.000000000 +0000 +@@ -474,6 +474,20 @@ { struct snd_line6_pcm *line6pcm = snd_pcm_substream_chip(substream); diff -Nru linux-3.2.46/debian/patches/features/all/line6/0017-staging-line6-fixed-ALSA-PCM-interaction.patch linux-3.2.46/debian/patches/features/all/line6/0017-staging-line6-fixed-ALSA-PCM-interaction.patch --- linux-3.2.46/debian/patches/features/all/line6/0017-staging-line6-fixed-ALSA-PCM-interaction.patch 2013-02-24 03:52:35.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/line6/0017-staging-line6-fixed-ALSA-PCM-interaction.patch 2013-07-26 19:28:21.000000000 +0000 @@ -22,11 +22,11 @@ drivers/staging/line6/revision.h | 2 +- 6 files changed, 118 insertions(+), 45 deletions(-) -diff --git a/drivers/staging/line6/capture.c b/drivers/staging/line6/capture.c -index 8f59ff3..127f952 100644 ---- a/drivers/staging/line6/capture.c -+++ b/drivers/staging/line6/capture.c -@@ -193,6 +193,31 @@ void line6_capture_check_period(struct snd_line6_pcm *line6pcm, int length) +Index: linux-3.2.46/drivers/staging/line6/capture.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/capture.c 2013-07-26 19:28:13.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/capture.c 2013-07-26 19:28:20.000000000 +0000 +@@ -193,6 +193,31 @@ } } @@ -58,7 +58,7 @@ /* * Callback for completed capture URB. */ -@@ -316,16 +341,11 @@ static int snd_line6_capture_hw_params(struct snd_pcm_substream *substream, +@@ -316,16 +341,11 @@ } /* -- [FD] end */ @@ -79,7 +79,7 @@ } ret = snd_pcm_lib_malloc_pages(substream, -@@ -342,9 +362,11 @@ static int snd_line6_capture_hw_free(struct snd_pcm_substream *substream) +@@ -342,9 +362,11 @@ { struct snd_line6_pcm *line6pcm = snd_pcm_substream_chip(substream); @@ -94,10 +94,10 @@ return snd_pcm_lib_free_pages(substream); } -diff --git a/drivers/staging/line6/capture.h b/drivers/staging/line6/capture.h -index a7509fb..366cbaa 100644 ---- a/drivers/staging/line6/capture.h -+++ b/drivers/staging/line6/capture.h +Index: linux-3.2.46/drivers/staging/line6/capture.h +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/capture.h 2013-07-26 18:52:58.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/capture.h 2013-07-26 19:28:20.000000000 +0000 @@ -19,11 +19,13 @@ extern struct snd_pcm_ops snd_line6_capture_ops; @@ -112,11 +112,11 @@ extern int line6_submit_audio_in_all_urbs(struct snd_line6_pcm *line6pcm); extern void line6_unlink_audio_in_urbs(struct snd_line6_pcm *line6pcm); extern void line6_unlink_wait_clear_audio_in_urbs(struct snd_line6_pcm -diff --git a/drivers/staging/line6/pcm.c b/drivers/staging/line6/pcm.c -index 68727b2..37675e6 100644 ---- a/drivers/staging/line6/pcm.c -+++ b/drivers/staging/line6/pcm.c -@@ -86,17 +86,22 @@ static DEVICE_ATTR(impulse_period, S_IWUSR | S_IRUGO, pcm_get_impulse_period, +Index: linux-3.2.46/drivers/staging/line6/pcm.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/pcm.c 2013-07-26 19:28:18.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/pcm.c 2013-07-26 19:28:20.000000000 +0000 +@@ -86,17 +86,22 @@ #endif @@ -142,7 +142,7 @@ /* Waiting for completion of active URBs in the stop handler is a bug, we therefore report an error if capturing is restarted -@@ -105,34 +110,47 @@ int line6_pcm_start(struct snd_line6_pcm *line6pcm, int channels) +@@ -105,34 +110,47 @@ if (line6pcm->active_urb_in | line6pcm->unlink_urb_in) return -EBUSY; @@ -200,7 +200,7 @@ } int line6_pcm_stop(struct snd_line6_pcm *line6pcm, int channels) -@@ -141,14 +159,18 @@ int line6_pcm_stop(struct snd_line6_pcm *line6pcm, int channels) +@@ -141,14 +159,18 @@ __sync_fetch_and_and(&line6pcm->flags, ~channels); unsigned long flags_new = flags_old & ~channels; @@ -223,7 +223,7 @@ } return 0; -@@ -476,18 +498,21 @@ int snd_line6_prepare(struct snd_pcm_substream *substream) +@@ -476,18 +498,21 @@ switch (substream->stream) { case SNDRV_PCM_STREAM_PLAYBACK: @@ -248,11 +248,11 @@ if (!test_and_set_bit(BIT_PREPARED, &line6pcm->flags)) { line6pcm->count_out = 0; line6pcm->pos_out = 0; -diff --git a/drivers/staging/line6/playback.c b/drivers/staging/line6/playback.c -index 9a51b92..4152db2 100644 ---- a/drivers/staging/line6/playback.c -+++ b/drivers/staging/line6/playback.c -@@ -351,6 +351,31 @@ void line6_unlink_wait_clear_audio_out_urbs(struct snd_line6_pcm *line6pcm) +Index: linux-3.2.46/drivers/staging/line6/playback.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/playback.c 2013-07-26 19:28:15.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/playback.c 2013-07-26 19:28:20.000000000 +0000 +@@ -351,6 +351,31 @@ wait_clear_audio_out_urbs(line6pcm); } @@ -284,7 +284,7 @@ /* Callback for completed playback URB. */ -@@ -459,16 +484,11 @@ static int snd_line6_playback_hw_params(struct snd_pcm_substream *substream, +@@ -459,16 +484,11 @@ } /* -- [FD] end */ @@ -305,7 +305,7 @@ } ret = snd_pcm_lib_malloc_pages(substream, -@@ -485,9 +505,11 @@ static int snd_line6_playback_hw_free(struct snd_pcm_substream *substream) +@@ -485,9 +505,11 @@ { struct snd_line6_pcm *line6pcm = snd_pcm_substream_chip(substream); @@ -320,10 +320,10 @@ return snd_pcm_lib_free_pages(substream); } -diff --git a/drivers/staging/line6/playback.h b/drivers/staging/line6/playback.h -index f2fc8c0..02487ff 100644 ---- a/drivers/staging/line6/playback.h -+++ b/drivers/staging/line6/playback.h +Index: linux-3.2.46/drivers/staging/line6/playback.h +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/playback.h 2013-07-26 18:52:58.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/playback.h 2013-07-26 19:28:20.000000000 +0000 @@ -29,7 +29,9 @@ extern struct snd_pcm_ops snd_line6_playback_ops; @@ -334,10 +334,10 @@ extern int line6_submit_audio_out_all_urbs(struct snd_line6_pcm *line6pcm); extern void line6_unlink_audio_out_urbs(struct snd_line6_pcm *line6pcm); extern void line6_unlink_wait_clear_audio_out_urbs(struct snd_line6_pcm -diff --git a/drivers/staging/line6/revision.h b/drivers/staging/line6/revision.h -index 350d0df..b4eee2b 100644 ---- a/drivers/staging/line6/revision.h -+++ b/drivers/staging/line6/revision.h +Index: linux-3.2.46/drivers/staging/line6/revision.h +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/revision.h 2013-07-26 18:52:58.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/revision.h 2013-07-26 19:28:20.000000000 +0000 @@ -1,4 +1,4 @@ #ifndef DRIVER_REVISION /* current subversion revision */ diff -Nru linux-3.2.46/debian/patches/features/all/line6/0018-staging-line6-removed-obsolete-code.patch linux-3.2.46/debian/patches/features/all/line6/0018-staging-line6-removed-obsolete-code.patch --- linux-3.2.46/debian/patches/features/all/line6/0018-staging-line6-removed-obsolete-code.patch 2013-02-24 03:52:35.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/line6/0018-staging-line6-removed-obsolete-code.patch 2013-07-26 19:28:22.000000000 +0000 @@ -10,11 +10,11 @@ drivers/staging/line6/pcm.h | 9 --------- 1 file changed, 9 deletions(-) -diff --git a/drivers/staging/line6/pcm.h b/drivers/staging/line6/pcm.h -index 55d8297..47c6d69 100644 ---- a/drivers/staging/line6/pcm.h -+++ b/drivers/staging/line6/pcm.h -@@ -305,13 +305,4 @@ extern void line6_pcm_disconnect(struct snd_line6_pcm *line6pcm); +Index: linux-3.2.46/drivers/staging/line6/pcm.h +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/pcm.h 2013-07-26 19:28:15.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/pcm.h 2013-07-26 19:28:21.000000000 +0000 +@@ -305,13 +305,4 @@ extern int line6_pcm_start(struct snd_line6_pcm *line6pcm, int channels); extern int line6_pcm_stop(struct snd_line6_pcm *line6pcm, int channels); diff -Nru linux-3.2.46/debian/patches/features/all/line6/0019-staging-line6-use-source-select-control-for-UX2-devi.patch linux-3.2.46/debian/patches/features/all/line6/0019-staging-line6-use-source-select-control-for-UX2-devi.patch --- linux-3.2.46/debian/patches/features/all/line6/0019-staging-line6-use-source-select-control-for-UX2-devi.patch 2013-02-24 03:52:35.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/line6/0019-staging-line6-use-source-select-control-for-UX2-devi.patch 2013-07-26 19:28:23.000000000 +0000 @@ -10,11 +10,11 @@ drivers/staging/line6/toneport.c | 4 ++++ 1 file changed, 4 insertions(+) -diff --git a/drivers/staging/line6/toneport.c b/drivers/staging/line6/toneport.c -index f310578..b776130 100644 ---- a/drivers/staging/line6/toneport.c -+++ b/drivers/staging/line6/toneport.c -@@ -320,7 +320,9 @@ static void toneport_setup(struct usb_line6_toneport *toneport) +Index: linux-3.2.46/drivers/staging/line6/toneport.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/toneport.c 2013-07-26 19:28:17.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/toneport.c 2013-07-26 19:28:23.000000000 +0000 +@@ -320,7 +320,9 @@ /* initialize source select: */ switch (usbdev->descriptor.idProduct) { case LINE6_DEVID_TONEPORT_UX1: @@ -24,7 +24,7 @@ toneport_send_cmd(usbdev, toneport_source_info[toneport->source].code, 0x0000); -@@ -363,7 +365,9 @@ static int toneport_try_init(struct usb_interface *interface, +@@ -363,7 +365,9 @@ /* register source select control: */ switch (usbdev->descriptor.idProduct) { case LINE6_DEVID_TONEPORT_UX1: diff -Nru linux-3.2.46/debian/patches/features/all/line6/0020-staging-line6-separate-handling-of-buffer-allocation.patch linux-3.2.46/debian/patches/features/all/line6/0020-staging-line6-separate-handling-of-buffer-allocation.patch --- linux-3.2.46/debian/patches/features/all/line6/0020-staging-line6-separate-handling-of-buffer-allocation.patch 2013-02-24 03:52:35.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/line6/0020-staging-line6-separate-handling-of-buffer-allocation.patch 2013-07-26 19:28:25.000000000 +0000 @@ -50,11 +50,11 @@ drivers/staging/line6/usbdefs.h | 44 +++++------ 9 files changed, 254 insertions(+), 193 deletions(-) -diff --git a/drivers/staging/line6/capture.c b/drivers/staging/line6/capture.c -index 127f952..c85c5b6 100644 ---- a/drivers/staging/line6/capture.c -+++ b/drivers/staging/line6/capture.c -@@ -107,7 +107,7 @@ void line6_unlink_audio_in_urbs(struct snd_line6_pcm *line6pcm) +Index: linux-3.2.46/drivers/staging/line6/capture.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/capture.c 2013-07-26 19:28:20.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/capture.c 2013-07-26 19:28:24.000000000 +0000 +@@ -107,7 +107,7 @@ Wait until unlinking of all currently active capture URBs has been finished. */ @@ -63,7 +63,7 @@ { int timeout = HZ; unsigned int i; -@@ -134,7 +134,7 @@ static void wait_clear_audio_in_urbs(struct snd_line6_pcm *line6pcm) +@@ -134,7 +134,7 @@ void line6_unlink_wait_clear_audio_in_urbs(struct snd_line6_pcm *line6pcm) { line6_unlink_audio_in_urbs(line6pcm); @@ -72,7 +72,7 @@ } /* -@@ -193,25 +193,6 @@ void line6_capture_check_period(struct snd_line6_pcm *line6pcm, int length) +@@ -193,25 +193,6 @@ } } @@ -98,7 +98,7 @@ void line6_free_capture_buffer(struct snd_line6_pcm *line6pcm) { kfree(line6pcm->buffer_in); -@@ -273,9 +254,9 @@ static void audio_in_callback(struct urb *urb) +@@ -273,9 +254,9 @@ line6pcm->prev_fsize = fsize; #ifdef CONFIG_LINE6_USB_IMPULSE_RESPONSE @@ -110,7 +110,7 @@ && (fsize > 0)) line6_capture_copy(line6pcm, fbuf, fsize); } -@@ -291,9 +272,9 @@ static void audio_in_callback(struct urb *urb) +@@ -291,9 +272,9 @@ submit_audio_in_urb(line6pcm); #ifdef CONFIG_LINE6_USB_IMPULSE_RESPONSE @@ -122,7 +122,7 @@ line6_capture_check_period(line6pcm, length); } } -@@ -341,17 +322,17 @@ static int snd_line6_capture_hw_params(struct snd_pcm_substream *substream, +@@ -341,17 +322,17 @@ } /* -- [FD] end */ @@ -146,7 +146,7 @@ line6pcm->period_in = params_period_bytes(hw_params); return 0; -@@ -361,12 +342,7 @@ static int snd_line6_capture_hw_params(struct snd_pcm_substream *substream, +@@ -361,12 +342,7 @@ static int snd_line6_capture_hw_free(struct snd_pcm_substream *substream) { struct snd_line6_pcm *line6pcm = snd_pcm_substream_chip(substream); @@ -160,7 +160,7 @@ return snd_pcm_lib_free_pages(substream); } -@@ -380,7 +356,7 @@ int snd_line6_capture_trigger(struct snd_line6_pcm *line6pcm, int cmd) +@@ -380,7 +356,7 @@ #ifdef CONFIG_PM case SNDRV_PCM_TRIGGER_RESUME: #endif @@ -169,7 +169,7 @@ if (err < 0) return err; -@@ -391,7 +367,7 @@ int snd_line6_capture_trigger(struct snd_line6_pcm *line6pcm, int cmd) +@@ -391,7 +367,7 @@ #ifdef CONFIG_PM case SNDRV_PCM_TRIGGER_SUSPEND: #endif @@ -178,10 +178,10 @@ if (err < 0) return err; -diff --git a/drivers/staging/line6/capture.h b/drivers/staging/line6/capture.h -index 366cbaa..4157bcb 100644 ---- a/drivers/staging/line6/capture.h -+++ b/drivers/staging/line6/capture.h +Index: linux-3.2.46/drivers/staging/line6/capture.h +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/capture.h 2013-07-26 19:28:20.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/capture.h 2013-07-26 19:28:24.000000000 +0000 @@ -19,7 +19,6 @@ extern struct snd_pcm_ops snd_line6_capture_ops; @@ -190,7 +190,7 @@ extern void line6_capture_copy(struct snd_line6_pcm *line6pcm, char *fbuf, int fsize); extern void line6_capture_check_period(struct snd_line6_pcm *line6pcm, -@@ -30,6 +29,7 @@ extern int line6_submit_audio_in_all_urbs(struct snd_line6_pcm *line6pcm); +@@ -30,6 +29,7 @@ extern void line6_unlink_audio_in_urbs(struct snd_line6_pcm *line6pcm); extern void line6_unlink_wait_clear_audio_in_urbs(struct snd_line6_pcm *line6pcm); @@ -198,11 +198,11 @@ extern int snd_line6_capture_trigger(struct snd_line6_pcm *line6pcm, int cmd); #endif -diff --git a/drivers/staging/line6/driver.c b/drivers/staging/line6/driver.c -index 6a1959e..e8023af 100644 ---- a/drivers/staging/line6/driver.c -+++ b/drivers/staging/line6/driver.c -@@ -1346,7 +1346,7 @@ static void __exit line6_exit(void) +Index: linux-3.2.46/drivers/staging/line6/driver.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/driver.c 2013-07-26 19:28:11.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/driver.c 2013-07-26 19:28:24.000000000 +0000 +@@ -1346,7 +1346,7 @@ if (line6pcm == NULL) continue; @@ -211,11 +211,11 @@ } usb_deregister(&line6_driver); -diff --git a/drivers/staging/line6/pcm.c b/drivers/staging/line6/pcm.c -index 37675e6..90d2d44 100644 ---- a/drivers/staging/line6/pcm.c -+++ b/drivers/staging/line6/pcm.c -@@ -52,9 +52,9 @@ static ssize_t pcm_set_impulse_volume(struct device *dev, +Index: linux-3.2.46/drivers/staging/line6/pcm.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/pcm.c 2013-07-26 19:28:20.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/pcm.c 2013-07-26 19:28:24.000000000 +0000 +@@ -52,9 +52,9 @@ line6pcm->impulse_volume = value; if (value > 0) @@ -227,7 +227,7 @@ return count; } -@@ -92,29 +92,43 @@ static bool test_flags(unsigned long flags0, unsigned long flags1, +@@ -92,29 +92,43 @@ return ((flags0 & mask) == 0) && ((flags1 & mask) != 0); } @@ -280,7 +280,7 @@ } line6pcm->count_in = 0; -@@ -122,55 +136,78 @@ int line6_pcm_start(struct snd_line6_pcm *line6pcm, int channels) +@@ -122,55 +136,78 @@ err = line6_submit_audio_in_all_urbs(line6pcm); if (err < 0) @@ -380,7 +380,7 @@ } return 0; -@@ -185,7 +222,7 @@ int snd_line6_trigger(struct snd_pcm_substream *substream, int cmd) +@@ -185,7 +222,7 @@ unsigned long flags; spin_lock_irqsave(&line6pcm->lock_trigger, flags); @@ -389,7 +389,7 @@ snd_pcm_group_for_each_entry(s, substream) { switch (s->stream) { -@@ -498,13 +535,13 @@ int snd_line6_prepare(struct snd_pcm_substream *substream) +@@ -498,13 +535,13 @@ switch (substream->stream) { case SNDRV_PCM_STREAM_PLAYBACK: @@ -405,7 +405,7 @@ line6_unlink_wait_clear_audio_in_urbs(line6pcm); break; -@@ -513,7 +550,7 @@ int snd_line6_prepare(struct snd_pcm_substream *substream) +@@ -513,7 +550,7 @@ MISSING_CASE; } @@ -414,10 +414,10 @@ line6pcm->count_out = 0; line6pcm->pos_out = 0; line6pcm->pos_out_done = 0; -diff --git a/drivers/staging/line6/pcm.h b/drivers/staging/line6/pcm.h -index 47c6d69..5210ec8 100644 ---- a/drivers/staging/line6/pcm.h -+++ b/drivers/staging/line6/pcm.h +Index: linux-3.2.46/drivers/staging/line6/pcm.h +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/pcm.h 2013-07-26 19:28:21.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/pcm.h 2013-07-26 19:28:24.000000000 +0000 @@ -46,57 +46,131 @@ (line6pcm->pcm->streams[stream].substream) @@ -474,23 +474,12 @@ + LINE6_INDEX_PCM_MONITOR_PLAYBACK_STREAM, + LINE6_INDEX_PCM_MONITOR_CAPTURE_BUFFER, + LINE6_INDEX_PCM_MONITOR_CAPTURE_STREAM, - #ifdef CONFIG_LINE6_USB_IMPULSE_RESPONSE -- BIT_PCM_IMPULSE_PLAYBACK, -- BIT_PCM_IMPULSE_CAPTURE, ++#ifdef CONFIG_LINE6_USB_IMPULSE_RESPONSE + LINE6_INDEX_PCM_IMPULSE_PLAYBACK_BUFFER, + LINE6_INDEX_PCM_IMPULSE_PLAYBACK_STREAM, + LINE6_INDEX_PCM_IMPULSE_CAPTURE_BUFFER, + LINE6_INDEX_PCM_IMPULSE_CAPTURE_STREAM, - #endif -- BIT_PAUSE_PLAYBACK, -- BIT_PREPARED, -- -- /* individual masks: */ --/* *INDENT-OFF* */ -- MASK_PCM_ALSA_PLAYBACK = 1 << BIT_PCM_ALSA_PLAYBACK, -- MASK_PCM_ALSA_CAPTURE = 1 << BIT_PCM_ALSA_CAPTURE, -- MASK_PCM_MONITOR_PLAYBACK = 1 << BIT_PCM_MONITOR_PLAYBACK, -- MASK_PCM_MONITOR_CAPTURE = 1 << BIT_PCM_MONITOR_CAPTURE, ++#endif + LINE6_INDEX_PAUSE_PLAYBACK, + LINE6_INDEX_PREPARED, + @@ -503,23 +492,15 @@ + LINE6_BIT(PCM_MONITOR_PLAYBACK_STREAM), + LINE6_BIT(PCM_MONITOR_CAPTURE_BUFFER), + LINE6_BIT(PCM_MONITOR_CAPTURE_STREAM), - #ifdef CONFIG_LINE6_USB_IMPULSE_RESPONSE -- MASK_PCM_IMPULSE_PLAYBACK = 1 << BIT_PCM_IMPULSE_PLAYBACK, -- MASK_PCM_IMPULSE_CAPTURE = 1 << BIT_PCM_IMPULSE_CAPTURE, ++#ifdef CONFIG_LINE6_USB_IMPULSE_RESPONSE + LINE6_BIT(PCM_IMPULSE_PLAYBACK_BUFFER), + LINE6_BIT(PCM_IMPULSE_PLAYBACK_STREAM), + LINE6_BIT(PCM_IMPULSE_CAPTURE_BUFFER), + LINE6_BIT(PCM_IMPULSE_CAPTURE_STREAM), - #endif -- MASK_PAUSE_PLAYBACK = 1 << BIT_PAUSE_PLAYBACK, -- MASK_PREPARED = 1 << BIT_PREPARED, --/* *INDENT-ON* */ ++#endif + LINE6_BIT(PAUSE_PLAYBACK), + LINE6_BIT(PREPARED), - -- /* combined masks (by operation): */ -- MASK_PCM_ALSA = MASK_PCM_ALSA_PLAYBACK | MASK_PCM_ALSA_CAPTURE, -- MASK_PCM_MONITOR = MASK_PCM_MONITOR_PLAYBACK | MASK_PCM_MONITOR_CAPTURE, ++ + /* combined bit masks (by operation): */ + LINE6_BITS_PCM_ALSA_BUFFER = + LINE6_BIT_PCM_ALSA_PLAYBACK_BUFFER | @@ -545,16 +526,35 @@ + + /* combined bit masks (by direction): */ + LINE6_BITS_PLAYBACK_BUFFER = -+#ifdef CONFIG_LINE6_USB_IMPULSE_RESPONSE + #ifdef CONFIG_LINE6_USB_IMPULSE_RESPONSE +- BIT_PCM_IMPULSE_PLAYBACK, +- BIT_PCM_IMPULSE_CAPTURE, + LINE6_BIT_PCM_IMPULSE_PLAYBACK_BUFFER | -+#endif + #endif +- BIT_PAUSE_PLAYBACK, +- BIT_PREPARED, + LINE6_BIT_PCM_ALSA_PLAYBACK_BUFFER | + LINE6_BIT_PCM_MONITOR_PLAYBACK_BUFFER , -+ + +- /* individual masks: */ +-/* *INDENT-OFF* */ +- MASK_PCM_ALSA_PLAYBACK = 1 << BIT_PCM_ALSA_PLAYBACK, +- MASK_PCM_ALSA_CAPTURE = 1 << BIT_PCM_ALSA_CAPTURE, +- MASK_PCM_MONITOR_PLAYBACK = 1 << BIT_PCM_MONITOR_PLAYBACK, +- MASK_PCM_MONITOR_CAPTURE = 1 << BIT_PCM_MONITOR_CAPTURE, + LINE6_BITS_PLAYBACK_STREAM = -+#ifdef CONFIG_LINE6_USB_IMPULSE_RESPONSE + #ifdef CONFIG_LINE6_USB_IMPULSE_RESPONSE +- MASK_PCM_IMPULSE_PLAYBACK = 1 << BIT_PCM_IMPULSE_PLAYBACK, +- MASK_PCM_IMPULSE_CAPTURE = 1 << BIT_PCM_IMPULSE_CAPTURE, + LINE6_BIT_PCM_IMPULSE_PLAYBACK_STREAM | -+#endif + #endif +- MASK_PAUSE_PLAYBACK = 1 << BIT_PAUSE_PLAYBACK, +- MASK_PREPARED = 1 << BIT_PREPARED, +-/* *INDENT-ON* */ +- +- /* combined masks (by operation): */ +- MASK_PCM_ALSA = MASK_PCM_ALSA_PLAYBACK | MASK_PCM_ALSA_CAPTURE, +- MASK_PCM_MONITOR = MASK_PCM_MONITOR_PLAYBACK | MASK_PCM_MONITOR_CAPTURE, + LINE6_BIT_PCM_ALSA_PLAYBACK_STREAM | + LINE6_BIT_PCM_MONITOR_PLAYBACK_STREAM , + @@ -589,7 +589,7 @@ }; struct line6_pcm_properties { -@@ -290,7 +364,7 @@ struct snd_line6_pcm { +@@ -290,7 +364,7 @@ #endif /** @@ -598,7 +598,7 @@ */ unsigned long flags; -@@ -302,7 +376,7 @@ extern int line6_init_pcm(struct usb_line6 *line6, +@@ -302,7 +376,7 @@ extern int snd_line6_trigger(struct snd_pcm_substream *substream, int cmd); extern int snd_line6_prepare(struct snd_pcm_substream *substream); extern void line6_pcm_disconnect(struct snd_line6_pcm *line6pcm); @@ -608,11 +608,11 @@ +extern int line6_pcm_release(struct snd_line6_pcm *line6pcm, int channels); #endif -diff --git a/drivers/staging/line6/playback.c b/drivers/staging/line6/playback.c -index 4152db2..a0ab9d0 100644 ---- a/drivers/staging/line6/playback.c -+++ b/drivers/staging/line6/playback.c -@@ -166,7 +166,7 @@ static int submit_audio_out_urb(struct snd_line6_pcm *line6pcm) +Index: linux-3.2.46/drivers/staging/line6/playback.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/playback.c 2013-07-26 19:28:20.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/playback.c 2013-07-26 19:28:24.000000000 +0000 +@@ -166,7 +166,7 @@ struct usb_iso_packet_descriptor *fout = &urb_out->iso_frame_desc[i]; @@ -621,7 +621,7 @@ fsize = line6pcm->prev_fsize; if (fsize == 0) { -@@ -196,8 +196,8 @@ static int submit_audio_out_urb(struct snd_line6_pcm *line6pcm) +@@ -196,8 +196,8 @@ urb_out->transfer_buffer_length = urb_size; urb_out->context = line6pcm; @@ -632,7 +632,7 @@ struct snd_pcm_runtime *runtime = get_substream(line6pcm, SNDRV_PCM_STREAM_PLAYBACK)->runtime; -@@ -238,10 +238,10 @@ static int submit_audio_out_urb(struct snd_line6_pcm *line6pcm) +@@ -238,10 +238,10 @@ if (line6pcm->prev_fbuf != NULL) { #ifdef CONFIG_LINE6_USB_IMPULSE_RESPONSE @@ -645,7 +645,7 @@ line6_capture_copy(line6pcm, urb_out->transfer_buffer, urb_out-> -@@ -254,8 +254,8 @@ static int submit_audio_out_urb(struct snd_line6_pcm *line6pcm) +@@ -254,8 +254,8 @@ if (! (line6pcm->line6-> properties->capabilities & LINE6_BIT_HWMON) @@ -656,7 +656,7 @@ add_monitor_signal(urb_out, line6pcm->prev_fbuf, line6pcm->volume_monitor, bytes_per_frame); -@@ -321,7 +321,7 @@ void line6_unlink_audio_out_urbs(struct snd_line6_pcm *line6pcm) +@@ -321,7 +321,7 @@ /* Wait until unlinking of all currently active playback URBs has been finished. */ @@ -665,7 +665,7 @@ { int timeout = HZ; unsigned int i; -@@ -348,26 +348,7 @@ static void wait_clear_audio_out_urbs(struct snd_line6_pcm *line6pcm) +@@ -348,26 +348,7 @@ void line6_unlink_wait_clear_audio_out_urbs(struct snd_line6_pcm *line6pcm) { line6_unlink_audio_out_urbs(line6pcm); @@ -693,7 +693,7 @@ } void line6_free_playback_buffer(struct snd_line6_pcm *line6pcm) -@@ -407,7 +388,7 @@ static void audio_out_callback(struct urb *urb) +@@ -407,7 +388,7 @@ spin_lock_irqsave(&line6pcm->lock_audio_out, flags); @@ -702,7 +702,7 @@ struct snd_pcm_runtime *runtime = substream->runtime; line6pcm->pos_out_done += length / line6pcm->properties->bytes_per_frame; -@@ -432,7 +413,7 @@ static void audio_out_callback(struct urb *urb) +@@ -432,7 +413,7 @@ if (!shutdown) { submit_audio_out_urb(line6pcm); @@ -711,7 +711,7 @@ line6pcm->bytes_out += length; if (line6pcm->bytes_out >= line6pcm->period_out) { line6pcm->bytes_out %= line6pcm->period_out; -@@ -484,17 +465,17 @@ static int snd_line6_playback_hw_params(struct snd_pcm_substream *substream, +@@ -484,17 +465,17 @@ } /* -- [FD] end */ @@ -735,7 +735,7 @@ line6pcm->period_out = params_period_bytes(hw_params); return 0; -@@ -504,12 +485,7 @@ static int snd_line6_playback_hw_params(struct snd_pcm_substream *substream, +@@ -504,12 +485,7 @@ static int snd_line6_playback_hw_free(struct snd_pcm_substream *substream) { struct snd_line6_pcm *line6pcm = snd_pcm_substream_chip(substream); @@ -749,7 +749,7 @@ return snd_pcm_lib_free_pages(substream); } -@@ -523,7 +499,7 @@ int snd_line6_playback_trigger(struct snd_line6_pcm *line6pcm, int cmd) +@@ -523,7 +499,7 @@ #ifdef CONFIG_PM case SNDRV_PCM_TRIGGER_RESUME: #endif @@ -758,7 +758,7 @@ if (err < 0) return err; -@@ -534,7 +510,7 @@ int snd_line6_playback_trigger(struct snd_line6_pcm *line6pcm, int cmd) +@@ -534,7 +510,7 @@ #ifdef CONFIG_PM case SNDRV_PCM_TRIGGER_SUSPEND: #endif @@ -767,7 +767,7 @@ if (err < 0) return err; -@@ -542,11 +518,11 @@ int snd_line6_playback_trigger(struct snd_line6_pcm *line6pcm, int cmd) +@@ -542,11 +518,11 @@ break; case SNDRV_PCM_TRIGGER_PAUSE_PUSH: @@ -781,10 +781,10 @@ break; default: -diff --git a/drivers/staging/line6/playback.h b/drivers/staging/line6/playback.h -index 02487ff..743bd6f 100644 ---- a/drivers/staging/line6/playback.h -+++ b/drivers/staging/line6/playback.h +Index: linux-3.2.46/drivers/staging/line6/playback.h +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/playback.h 2013-07-26 19:28:20.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/playback.h 2013-07-26 19:28:24.000000000 +0000 @@ -29,13 +29,13 @@ extern struct snd_pcm_ops snd_line6_playback_ops; @@ -800,11 +800,11 @@ extern int snd_line6_playback_trigger(struct snd_line6_pcm *line6pcm, int cmd); #endif -diff --git a/drivers/staging/line6/toneport.c b/drivers/staging/line6/toneport.c -index b776130..b754f69 100644 ---- a/drivers/staging/line6/toneport.c -+++ b/drivers/staging/line6/toneport.c -@@ -207,9 +207,9 @@ static int snd_toneport_monitor_put(struct snd_kcontrol *kcontrol, +Index: linux-3.2.46/drivers/staging/line6/toneport.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/toneport.c 2013-07-26 19:28:23.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/toneport.c 2013-07-26 19:28:24.000000000 +0000 +@@ -207,9 +207,9 @@ line6pcm->volume_monitor = ucontrol->value.integer.value[0]; if (line6pcm->volume_monitor > 0) @@ -816,7 +816,7 @@ return 1; } -@@ -264,7 +264,7 @@ static void toneport_start_pcm(unsigned long arg) +@@ -264,7 +264,7 @@ { struct usb_line6_toneport *toneport = (struct usb_line6_toneport *)arg; struct usb_line6 *line6 = &toneport->line6; @@ -825,7 +825,7 @@ } /* control definition */ -@@ -446,7 +446,7 @@ void line6_toneport_disconnect(struct usb_interface *interface) +@@ -446,7 +446,7 @@ struct snd_line6_pcm *line6pcm = toneport->line6.line6pcm; if (line6pcm != NULL) { @@ -834,10 +834,10 @@ line6_pcm_disconnect(line6pcm); } } -diff --git a/drivers/staging/line6/usbdefs.h b/drivers/staging/line6/usbdefs.h -index aff9e5c..353d59d 100644 ---- a/drivers/staging/line6/usbdefs.h -+++ b/drivers/staging/line6/usbdefs.h +Index: linux-3.2.46/drivers/staging/line6/usbdefs.h +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/usbdefs.h 2013-07-26 19:28:11.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/usbdefs.h 2013-07-26 19:28:24.000000000 +0000 @@ -39,31 +39,29 @@ #define LINE6_DEVID_TONEPORT_UX2 0x4142 #define LINE6_DEVID_VARIAX 0x534d diff -Nru linux-3.2.46/debian/patches/features/all/line6/0021-Staging-line6-remove-unneeded-initialization.patch linux-3.2.46/debian/patches/features/all/line6/0021-Staging-line6-remove-unneeded-initialization.patch --- linux-3.2.46/debian/patches/features/all/line6/0021-Staging-line6-remove-unneeded-initialization.patch 2013-02-24 03:52:35.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/line6/0021-Staging-line6-remove-unneeded-initialization.patch 2013-07-26 19:28:26.000000000 +0000 @@ -16,11 +16,11 @@ drivers/staging/line6/driver.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) -diff --git a/drivers/staging/line6/driver.c b/drivers/staging/line6/driver.c -index e8023af..312905a 100644 ---- a/drivers/staging/line6/driver.c -+++ b/drivers/staging/line6/driver.c -@@ -1297,13 +1297,10 @@ static struct usb_driver line6_driver = { +Index: linux-3.2.46/drivers/staging/line6/driver.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/driver.c 2013-07-26 19:28:24.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/driver.c 2013-07-26 19:28:26.000000000 +0000 +@@ -1297,13 +1297,10 @@ */ static int __init line6_init(void) { diff -Nru linux-3.2.46/debian/patches/features/all/line6/0022-Staging-line6-only-allocate-a-buffer-if-it-is-needed.patch linux-3.2.46/debian/patches/features/all/line6/0022-Staging-line6-only-allocate-a-buffer-if-it-is-needed.patch --- linux-3.2.46/debian/patches/features/all/line6/0022-Staging-line6-only-allocate-a-buffer-if-it-is-needed.patch 2013-02-24 03:52:35.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/line6/0022-Staging-line6-only-allocate-a-buffer-if-it-is-needed.patch 2013-07-26 19:28:28.000000000 +0000 @@ -17,11 +17,11 @@ drivers/staging/line6/driver.c | 47 +++++++++++++++------------------------- 1 file changed, 17 insertions(+), 30 deletions(-) -diff --git a/drivers/staging/line6/driver.c b/drivers/staging/line6/driver.c -index 312905a..351e860 100644 ---- a/drivers/staging/line6/driver.c -+++ b/drivers/staging/line6/driver.c -@@ -92,15 +92,10 @@ const unsigned char line6_midi_id[] = { +Index: linux-3.2.46/drivers/staging/line6/driver.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/driver.c 2013-07-26 19:28:26.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/driver.c 2013-07-26 19:28:27.000000000 +0000 +@@ -92,15 +92,10 @@ Code to request version of POD, Variax interface (and maybe other devices). */ @@ -38,7 +38,7 @@ struct usb_line6 *line6_devices[LINE6_MAX_DEVICES]; /** -@@ -336,8 +331,21 @@ int line6_send_raw_message_async(struct usb_line6 *line6, const char *buffer, +@@ -336,8 +331,21 @@ */ int line6_version_request_async(struct usb_line6 *line6) { @@ -62,7 +62,7 @@ } /* -@@ -1297,29 +1305,9 @@ static struct usb_driver line6_driver = { +@@ -1297,29 +1305,9 @@ */ static int __init line6_init(void) { @@ -93,7 +93,7 @@ } /* -@@ -1347,7 +1335,6 @@ static void __exit line6_exit(void) +@@ -1347,7 +1335,6 @@ } usb_deregister(&line6_driver); diff -Nru linux-3.2.46/debian/patches/features/all/line6/0023-Staging-line6-remove-teardown-code-from-module_exit-.patch linux-3.2.46/debian/patches/features/all/line6/0023-Staging-line6-remove-teardown-code-from-module_exit-.patch --- linux-3.2.46/debian/patches/features/all/line6/0023-Staging-line6-remove-teardown-code-from-module_exit-.patch 2013-02-24 03:52:35.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/line6/0023-Staging-line6-remove-teardown-code-from-module_exit-.patch 2013-07-26 19:28:29.000000000 +0000 @@ -17,11 +17,11 @@ drivers/staging/line6/driver.c | 19 ------------------- 1 file changed, 19 deletions(-) -diff --git a/drivers/staging/line6/driver.c b/drivers/staging/line6/driver.c -index 351e860..c476fcc 100644 ---- a/drivers/staging/line6/driver.c -+++ b/drivers/staging/line6/driver.c -@@ -1315,25 +1315,6 @@ static int __init line6_init(void) +Index: linux-3.2.46/drivers/staging/line6/driver.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/driver.c 2013-07-26 19:28:27.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/driver.c 2013-07-26 19:28:28.000000000 +0000 +@@ -1315,25 +1315,6 @@ */ static void __exit line6_exit(void) { diff -Nru linux-3.2.46/debian/patches/features/all/line6/0024-Staging-line6-use-module_usb_driver.patch linux-3.2.46/debian/patches/features/all/line6/0024-Staging-line6-use-module_usb_driver.patch --- linux-3.2.46/debian/patches/features/all/line6/0024-Staging-line6-use-module_usb_driver.patch 2013-02-24 03:52:35.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/line6/0024-Staging-line6-use-module_usb_driver.patch 2013-07-26 19:28:30.000000000 +0000 @@ -18,11 +18,11 @@ drivers/staging/line6/driver.c | 21 +-------------------- 1 file changed, 1 insertion(+), 20 deletions(-) -diff --git a/drivers/staging/line6/driver.c b/drivers/staging/line6/driver.c -index c476fcc..4513f78 100644 ---- a/drivers/staging/line6/driver.c -+++ b/drivers/staging/line6/driver.c -@@ -1300,26 +1300,7 @@ static struct usb_driver line6_driver = { +Index: linux-3.2.46/drivers/staging/line6/driver.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/driver.c 2013-07-26 19:28:28.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/driver.c 2013-07-26 19:28:29.000000000 +0000 +@@ -1300,26 +1300,7 @@ .id_table = line6_id_table, }; diff -Nru linux-3.2.46/debian/patches/features/all/line6/0025-staging-line6-toneport.c-remove-err-usage.patch linux-3.2.46/debian/patches/features/all/line6/0025-staging-line6-toneport.c-remove-err-usage.patch --- linux-3.2.46/debian/patches/features/all/line6/0025-staging-line6-toneport.c-remove-err-usage.patch 2013-02-24 03:52:35.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/line6/0025-staging-line6-toneport.c-remove-err-usage.patch 2013-07-26 19:28:32.000000000 +0000 @@ -15,11 +15,11 @@ drivers/staging/line6/toneport.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -diff --git a/drivers/staging/line6/toneport.c b/drivers/staging/line6/toneport.c -index b754f69..31b624b 100644 ---- a/drivers/staging/line6/toneport.c -+++ b/drivers/staging/line6/toneport.c -@@ -168,7 +168,7 @@ static int toneport_send_cmd(struct usb_device *usbdev, int cmd1, int cmd2) +Index: linux-3.2.46/drivers/staging/line6/toneport.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/toneport.c 2013-07-26 19:28:24.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/toneport.c 2013-07-26 19:28:31.000000000 +0000 +@@ -168,7 +168,7 @@ cmd1, cmd2, NULL, 0, LINE6_TIMEOUT * HZ); if (ret < 0) { diff -Nru linux-3.2.46/debian/patches/features/all/line6/0026-staging-line6-midibuf.c-changed-printk-KERN_DEBUG-.-.patch linux-3.2.46/debian/patches/features/all/line6/0026-staging-line6-midibuf.c-changed-printk-KERN_DEBUG-.-.patch --- linux-3.2.46/debian/patches/features/all/line6/0026-staging-line6-midibuf.c-changed-printk-KERN_DEBUG-.-.patch 2013-02-24 03:52:35.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/line6/0026-staging-line6-midibuf.c-changed-printk-KERN_DEBUG-.-.patch 2013-07-26 19:28:33.000000000 +0000 @@ -14,11 +14,11 @@ drivers/staging/line6/midibuf.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -diff --git a/drivers/staging/line6/midibuf.c b/drivers/staging/line6/midibuf.c -index 7b532e5..836e8c8 100644 ---- a/drivers/staging/line6/midibuf.c -+++ b/drivers/staging/line6/midibuf.c -@@ -64,7 +64,7 @@ int line6_midibuf_init(struct MidiBuffer *this, int size, int split) +Index: linux-3.2.46/drivers/staging/line6/midibuf.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/midibuf.c 2013-07-26 18:52:54.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/midibuf.c 2013-07-26 19:28:32.000000000 +0000 +@@ -64,7 +64,7 @@ void line6_midibuf_status(struct MidiBuffer *this) { diff -Nru linux-3.2.46/debian/patches/features/all/line6/0027-staging-line6-midi.c-Added-space-between-switch-and-.patch linux-3.2.46/debian/patches/features/all/line6/0027-staging-line6-midi.c-Added-space-between-switch-and-.patch --- linux-3.2.46/debian/patches/features/all/line6/0027-staging-line6-midi.c-Added-space-between-switch-and-.patch 2013-02-24 03:52:35.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/line6/0027-staging-line6-midi.c-Added-space-between-switch-and-.patch 2013-07-26 19:28:34.000000000 +0000 @@ -13,11 +13,11 @@ drivers/staging/line6/midi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -diff --git a/drivers/staging/line6/midi.c b/drivers/staging/line6/midi.c -index 13d0293..5040729 100644 ---- a/drivers/staging/line6/midi.c -+++ b/drivers/staging/line6/midi.c -@@ -406,7 +406,7 @@ int line6_init_midi(struct usb_line6 *line6) +Index: linux-3.2.46/drivers/staging/line6/midi.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/midi.c 2013-07-26 19:28:11.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/midi.c 2013-07-26 19:28:33.000000000 +0000 +@@ -406,7 +406,7 @@ line6midi->line6 = line6; diff -Nru linux-3.2.46/debian/patches/features/all/line6/0028-staging-line6-pcm.c-Removed-trailing-whitespace.patch linux-3.2.46/debian/patches/features/all/line6/0028-staging-line6-pcm.c-Removed-trailing-whitespace.patch --- linux-3.2.46/debian/patches/features/all/line6/0028-staging-line6-pcm.c-Removed-trailing-whitespace.patch 2013-02-24 03:52:35.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/line6/0028-staging-line6-pcm.c-Removed-trailing-whitespace.patch 2013-07-26 19:28:36.000000000 +0000 @@ -12,11 +12,11 @@ drivers/staging/line6/pcm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -diff --git a/drivers/staging/line6/pcm.c b/drivers/staging/line6/pcm.c -index 90d2d44..5e319e3 100644 ---- a/drivers/staging/line6/pcm.c -+++ b/drivers/staging/line6/pcm.c -@@ -99,7 +99,7 @@ int line6_pcm_acquire(struct snd_line6_pcm *line6pcm, int channels) +Index: linux-3.2.46/drivers/staging/line6/pcm.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/pcm.c 2013-07-26 19:28:24.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/pcm.c 2013-07-26 19:28:35.000000000 +0000 +@@ -99,7 +99,7 @@ unsigned long flags_new = flags_old | channels; unsigned long flags_final = flags_old; int err = 0; diff -Nru linux-3.2.46/debian/patches/features/all/line6/0029-staging-line6-config.h-Remove-CHECKPOINT-macro.patch linux-3.2.46/debian/patches/features/all/line6/0029-staging-line6-config.h-Remove-CHECKPOINT-macro.patch --- linux-3.2.46/debian/patches/features/all/line6/0029-staging-line6-config.h-Remove-CHECKPOINT-macro.patch 2013-02-24 03:52:35.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/line6/0029-staging-line6-config.h-Remove-CHECKPOINT-macro.patch 2013-07-26 19:28:37.000000000 +0000 @@ -12,10 +12,10 @@ drivers/staging/line6/config.h | 5 ----- 1 file changed, 5 deletions(-) -diff --git a/drivers/staging/line6/config.h b/drivers/staging/line6/config.h -index f8a5149..2493491 100644 ---- a/drivers/staging/line6/config.h -+++ b/drivers/staging/line6/config.h +Index: linux-3.2.46/drivers/staging/line6/config.h +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/config.h 2013-07-26 18:52:53.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/config.h 2013-07-26 19:28:36.000000000 +0000 @@ -34,11 +34,6 @@ #define CREATE_RAW_FILE 0 diff -Nru linux-3.2.46/debian/patches/features/all/line6/0030-staging-line6-config.h-Delete-unused-header.patch linux-3.2.46/debian/patches/features/all/line6/0030-staging-line6-config.h-Delete-unused-header.patch --- linux-3.2.46/debian/patches/features/all/line6/0030-staging-line6-config.h-Delete-unused-header.patch 2013-02-24 03:52:35.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/line6/0030-staging-line6-config.h-Delete-unused-header.patch 2013-07-26 19:28:38.000000000 +0000 @@ -13,11 +13,10 @@ 1 file changed, 43 deletions(-) delete mode 100644 drivers/staging/line6/config.h -diff --git a/drivers/staging/line6/config.h b/drivers/staging/line6/config.h -deleted file mode 100644 -index 2493491..0000000 ---- a/drivers/staging/line6/config.h -+++ /dev/null +Index: linux-3.2.46/drivers/staging/line6/config.h +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/config.h 2013-07-26 19:28:36.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 @@ -1,43 +0,0 @@ -/* - * Line6 Linux USB driver - 0.8.0 diff -Nru linux-3.2.46/debian/patches/features/all/line6/0031-staging-line6-changed-interface-of-line6_transmit_pa.patch linux-3.2.46/debian/patches/features/all/line6/0031-staging-line6-changed-interface-of-line6_transmit_pa.patch --- linux-3.2.46/debian/patches/features/all/line6/0031-staging-line6-changed-interface-of-line6_transmit_pa.patch 2013-02-24 03:52:35.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/line6/0031-staging-line6-changed-interface-of-line6_transmit_pa.patch 2013-07-26 19:28:39.000000000 +0000 @@ -14,11 +14,11 @@ drivers/staging/line6/driver.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) -diff --git a/drivers/staging/line6/driver.c b/drivers/staging/line6/driver.c -index 4513f78..d861230 100644 ---- a/drivers/staging/line6/driver.c -+++ b/drivers/staging/line6/driver.c -@@ -526,7 +526,7 @@ int line6_send_program(struct usb_line6 *line6, int value) +Index: linux-3.2.46/drivers/staging/line6/driver.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/driver.c 2013-07-26 19:28:29.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/driver.c 2013-07-26 19:28:38.000000000 +0000 +@@ -526,7 +526,7 @@ /* Transmit Line6 control parameter. */ @@ -27,11 +27,11 @@ { int retval; unsigned char *buffer; -diff --git a/drivers/staging/line6/driver.h b/drivers/staging/line6/driver.h -index 117bf99..140ccfe 100644 ---- a/drivers/staging/line6/driver.h -+++ b/drivers/staging/line6/driver.h -@@ -224,7 +224,7 @@ extern void line6_start_timer(struct timer_list *timer, unsigned int msecs, +Index: linux-3.2.46/drivers/staging/line6/driver.h +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/driver.h 2013-07-26 19:28:11.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/driver.h 2013-07-26 19:28:38.000000000 +0000 +@@ -224,7 +224,7 @@ void (*function) (unsigned long), unsigned long data); extern int line6_transmit_parameter(struct usb_line6 *line6, int param, diff -Nru linux-3.2.46/debian/patches/features/all/line6/0032-staging-line6-Changed-some-strict_strtouls-to-kstrto.patch linux-3.2.46/debian/patches/features/all/line6/0032-staging-line6-Changed-some-strict_strtouls-to-kstrto.patch --- linux-3.2.46/debian/patches/features/all/line6/0032-staging-line6-Changed-some-strict_strtouls-to-kstrto.patch 2013-02-24 03:52:35.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/line6/0032-staging-line6-Changed-some-strict_strtouls-to-kstrto.patch 2013-07-26 19:28:41.000000000 +0000 @@ -13,11 +13,11 @@ drivers/staging/line6/variax.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) -diff --git a/drivers/staging/line6/variax.c b/drivers/staging/line6/variax.c -index d366222..bb99ee4 100644 ---- a/drivers/staging/line6/variax.c -+++ b/drivers/staging/line6/variax.c -@@ -319,10 +319,10 @@ static ssize_t variax_set_volume(struct device *dev, +Index: linux-3.2.46/drivers/staging/line6/variax.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/variax.c 2013-07-26 19:28:17.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/variax.c 2013-07-26 19:28:40.000000000 +0000 +@@ -319,10 +319,10 @@ { struct usb_line6_variax *variax = usb_get_intfdata(to_usb_interface(dev)); @@ -30,7 +30,7 @@ if (ret) return ret; -@@ -418,10 +418,10 @@ static ssize_t variax_set_tone(struct device *dev, +@@ -418,10 +418,10 @@ { struct usb_line6_variax *variax = usb_get_intfdata(to_usb_interface(dev)); diff -Nru linux-3.2.46/debian/patches/features/all/line6/0033-staging-line6-changed-interface-of-line6_pod_transmi.patch linux-3.2.46/debian/patches/features/all/line6/0033-staging-line6-changed-interface-of-line6_pod_transmi.patch --- linux-3.2.46/debian/patches/features/all/line6/0033-staging-line6-changed-interface-of-line6_pod_transmi.patch 2013-02-24 03:52:35.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/line6/0033-staging-line6-changed-interface-of-line6_pod_transmi.patch 2013-07-26 19:28:42.000000000 +0000 @@ -15,11 +15,11 @@ drivers/staging/line6/pod.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) -diff --git a/drivers/staging/line6/pod.c b/drivers/staging/line6/pod.c -index 4dadc57..8667aaf 100644 ---- a/drivers/staging/line6/pod.c -+++ b/drivers/staging/line6/pod.c -@@ -419,7 +419,7 @@ static void pod_send_channel(struct usb_line6_pod *pod, int value) +Index: linux-3.2.46/drivers/staging/line6/pod.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/pod.c 2013-07-26 19:28:17.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/pod.c 2013-07-26 19:28:41.000000000 +0000 +@@ -419,7 +419,7 @@ Transmit PODxt Pro control parameter. */ void line6_pod_transmit_parameter(struct usb_line6_pod *pod, int param, @@ -28,11 +28,11 @@ { if (line6_transmit_parameter(&pod->line6, param, value) == 0) pod_store_parameter(pod, param, value); -diff --git a/drivers/staging/line6/pod.h b/drivers/staging/line6/pod.h -index 18b9d08..47e0d1a 100644 ---- a/drivers/staging/line6/pod.h -+++ b/drivers/staging/line6/pod.h -@@ -200,6 +200,6 @@ extern void line6_pod_midi_postprocess(struct usb_line6_pod *pod, +Index: linux-3.2.46/drivers/staging/line6/pod.h +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/pod.h 2013-07-26 18:52:52.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/pod.h 2013-07-26 19:28:41.000000000 +0000 +@@ -200,6 +200,6 @@ unsigned char *data, int length); extern void line6_pod_process_message(struct usb_line6_pod *pod); extern void line6_pod_transmit_parameter(struct usb_line6_pod *pod, int param, diff -Nru linux-3.2.46/debian/patches/features/all/line6/0034-staging-line6-adjusted-interface-of-line6_send_progr.patch linux-3.2.46/debian/patches/features/all/line6/0034-staging-line6-adjusted-interface-of-line6_send_progr.patch --- linux-3.2.46/debian/patches/features/all/line6/0034-staging-line6-adjusted-interface-of-line6_send_progr.patch 2013-02-24 03:52:35.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/line6/0034-staging-line6-adjusted-interface-of-line6_send_progr.patch 2013-07-26 19:28:43.000000000 +0000 @@ -13,11 +13,11 @@ drivers/staging/line6/driver.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) -diff --git a/drivers/staging/line6/driver.c b/drivers/staging/line6/driver.c -index d861230..b8358ca 100644 ---- a/drivers/staging/line6/driver.c -+++ b/drivers/staging/line6/driver.c -@@ -490,7 +490,7 @@ static void line6_data_received(struct urb *urb) +Index: linux-3.2.46/drivers/staging/line6/driver.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/driver.c 2013-07-26 19:28:38.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/driver.c 2013-07-26 19:28:42.000000000 +0000 +@@ -490,7 +490,7 @@ /* Send channel number (i.e., switch to a different sound). */ @@ -26,11 +26,11 @@ { int retval; unsigned char *buffer; -diff --git a/drivers/staging/line6/driver.h b/drivers/staging/line6/driver.h -index 140ccfe..a3029eb 100644 ---- a/drivers/staging/line6/driver.h -+++ b/drivers/staging/line6/driver.h -@@ -209,7 +209,7 @@ extern int line6_read_data(struct usb_line6 *line6, int address, void *data, +Index: linux-3.2.46/drivers/staging/line6/driver.h +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/driver.h 2013-07-26 19:28:38.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/driver.h 2013-07-26 19:28:42.000000000 +0000 +@@ -209,7 +209,7 @@ size_t datalen); extern int line6_read_serial_number(struct usb_line6 *line6, int *serial_number); diff -Nru linux-3.2.46/debian/patches/features/all/line6/0035-staging-line6-changed-interface-of-pod_send_channel.patch linux-3.2.46/debian/patches/features/all/line6/0035-staging-line6-changed-interface-of-pod_send_channel.patch --- linux-3.2.46/debian/patches/features/all/line6/0035-staging-line6-changed-interface-of-pod_send_channel.patch 2013-02-24 03:52:35.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/line6/0035-staging-line6-changed-interface-of-pod_send_channel.patch 2013-07-26 19:28:45.000000000 +0000 @@ -13,11 +13,11 @@ drivers/staging/line6/pod.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -diff --git a/drivers/staging/line6/pod.c b/drivers/staging/line6/pod.c -index 8667aaf..459f325 100644 ---- a/drivers/staging/line6/pod.c -+++ b/drivers/staging/line6/pod.c -@@ -405,7 +405,7 @@ void line6_pod_midi_postprocess(struct usb_line6_pod *pod, unsigned char *data, +Index: linux-3.2.46/drivers/staging/line6/pod.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/pod.c 2013-07-26 19:28:41.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/pod.c 2013-07-26 19:28:44.000000000 +0000 +@@ -405,7 +405,7 @@ /* Send channel number (i.e., switch to a different sound). */ diff -Nru linux-3.2.46/debian/patches/features/all/line6/0036-staging-line6-control.c-eliminate-strict_strtoul-in-.patch linux-3.2.46/debian/patches/features/all/line6/0036-staging-line6-control.c-eliminate-strict_strtoul-in-.patch --- linux-3.2.46/debian/patches/features/all/line6/0036-staging-line6-control.c-eliminate-strict_strtoul-in-.patch 2013-02-24 03:52:35.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/line6/0036-staging-line6-control.c-eliminate-strict_strtoul-in-.patch 2013-07-26 19:28:46.000000000 +0000 @@ -15,11 +15,11 @@ drivers/staging/line6/control.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -diff --git a/drivers/staging/line6/control.c b/drivers/staging/line6/control.c -index 67e23b6..f8326f5 100644 ---- a/drivers/staging/line6/control.c -+++ b/drivers/staging/line6/control.c -@@ -55,10 +55,10 @@ static ssize_t pod_set_param_int(struct device *dev, const char *buf, +Index: linux-3.2.46/drivers/staging/line6/control.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/control.c 2013-07-26 18:52:51.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/control.c 2013-07-26 19:28:45.000000000 +0000 +@@ -55,10 +55,10 @@ { struct usb_interface *interface = to_usb_interface(dev); struct usb_line6_pod *pod = usb_get_intfdata(interface); diff -Nru linux-3.2.46/debian/patches/features/all/line6/0037-staging-line6-Exchanged-strict_strtoul-with-kstrtou8.patch linux-3.2.46/debian/patches/features/all/line6/0037-staging-line6-Exchanged-strict_strtoul-with-kstrtou8.patch --- linux-3.2.46/debian/patches/features/all/line6/0037-staging-line6-Exchanged-strict_strtoul-with-kstrtou8.patch 2013-02-24 03:52:35.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/line6/0037-staging-line6-Exchanged-strict_strtoul-with-kstrtou8.patch 2013-07-26 19:28:47.000000000 +0000 @@ -13,11 +13,11 @@ drivers/staging/line6/pod.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -diff --git a/drivers/staging/line6/pod.c b/drivers/staging/line6/pod.c -index 459f325..4c81914 100644 ---- a/drivers/staging/line6/pod.c -+++ b/drivers/staging/line6/pod.c -@@ -434,11 +434,11 @@ void line6_pod_transmit_parameter(struct usb_line6_pod *pod, int param, +Index: linux-3.2.46/drivers/staging/line6/pod.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/pod.c 2013-07-26 19:28:44.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/pod.c 2013-07-26 19:28:46.000000000 +0000 +@@ -434,11 +434,11 @@ static int pod_resolve(const char *buf, short block0, short block1, unsigned char *location) { diff -Nru linux-3.2.46/debian/patches/features/all/line6/0038-staging-line6-Changed-strict_strtoul-to-kstrtou8-in-.patch linux-3.2.46/debian/patches/features/all/line6/0038-staging-line6-Changed-strict_strtoul-to-kstrtou8-in-.patch --- linux-3.2.46/debian/patches/features/all/line6/0038-staging-line6-Changed-strict_strtoul-to-kstrtou8-in-.patch 2013-02-24 03:52:35.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/line6/0038-staging-line6-Changed-strict_strtoul-to-kstrtou8-in-.patch 2013-07-26 19:28:49.000000000 +0000 @@ -14,11 +14,11 @@ drivers/staging/line6/pod.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -diff --git a/drivers/staging/line6/pod.c b/drivers/staging/line6/pod.c -index 4c81914..2a85ec3 100644 ---- a/drivers/staging/line6/pod.c -+++ b/drivers/staging/line6/pod.c -@@ -560,10 +560,10 @@ static ssize_t pod_set_channel(struct device *dev, +Index: linux-3.2.46/drivers/staging/line6/pod.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/pod.c 2013-07-26 19:28:46.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/pod.c 2013-07-26 19:28:48.000000000 +0000 +@@ -560,10 +560,10 @@ { struct usb_interface *interface = to_usb_interface(dev); struct usb_line6_pod *pod = usb_get_intfdata(interface); diff -Nru linux-3.2.46/debian/patches/features/all/line6/0039-staging-line6-Changed-strict_strtoul-to-kstrtou8-in-.patch linux-3.2.46/debian/patches/features/all/line6/0039-staging-line6-Changed-strict_strtoul-to-kstrtou8-in-.patch --- linux-3.2.46/debian/patches/features/all/line6/0039-staging-line6-Changed-strict_strtoul-to-kstrtou8-in-.patch 2013-02-24 03:52:35.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/line6/0039-staging-line6-Changed-strict_strtoul-to-kstrtou8-in-.patch 2013-07-26 19:28:50.000000000 +0000 @@ -14,11 +14,11 @@ drivers/staging/line6/pod.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -diff --git a/drivers/staging/line6/pod.c b/drivers/staging/line6/pod.c -index 2a85ec3..9edd053 100644 ---- a/drivers/staging/line6/pod.c -+++ b/drivers/staging/line6/pod.c -@@ -892,10 +892,10 @@ static ssize_t pod_set_midi_postprocess(struct device *dev, +Index: linux-3.2.46/drivers/staging/line6/pod.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/pod.c 2013-07-26 19:28:48.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/pod.c 2013-07-26 19:28:49.000000000 +0000 +@@ -892,10 +892,10 @@ { struct usb_interface *interface = to_usb_interface(dev); struct usb_line6_pod *pod = usb_get_intfdata(interface); diff -Nru linux-3.2.46/debian/patches/features/all/line6/0040-staging-line6-pcm.c-Changed-simple_strtoul-to-kstrto.patch linux-3.2.46/debian/patches/features/all/line6/0040-staging-line6-pcm.c-Changed-simple_strtoul-to-kstrto.patch --- linux-3.2.46/debian/patches/features/all/line6/0040-staging-line6-pcm.c-Changed-simple_strtoul-to-kstrto.patch 2013-02-24 03:52:35.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/line6/0040-staging-line6-pcm.c-Changed-simple_strtoul-to-kstrto.patch 2013-07-26 19:28:51.000000000 +0000 @@ -13,11 +13,11 @@ drivers/staging/line6/pcm.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) -diff --git a/drivers/staging/line6/pcm.c b/drivers/staging/line6/pcm.c -index 5e319e3..7fe44a6 100644 ---- a/drivers/staging/line6/pcm.c -+++ b/drivers/staging/line6/pcm.c -@@ -48,7 +48,13 @@ static ssize_t pcm_set_impulse_volume(struct device *dev, +Index: linux-3.2.46/drivers/staging/line6/pcm.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/pcm.c 2013-07-26 19:28:35.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/pcm.c 2013-07-26 19:28:50.000000000 +0000 +@@ -48,7 +48,13 @@ const char *buf, size_t count) { struct snd_line6_pcm *line6pcm = dev2pcm(dev); diff -Nru linux-3.2.46/debian/patches/features/all/line6/0041-staging-line6-variax.c-Eliminated-remaining-strict_s.patch linux-3.2.46/debian/patches/features/all/line6/0041-staging-line6-variax.c-Eliminated-remaining-strict_s.patch --- linux-3.2.46/debian/patches/features/all/line6/0041-staging-line6-variax.c-Eliminated-remaining-strict_s.patch 2013-02-24 03:52:35.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/line6/0041-staging-line6-variax.c-Eliminated-remaining-strict_s.patch 2013-07-26 19:28:52.000000000 +0000 @@ -14,11 +14,11 @@ drivers/staging/line6/variax.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) -diff --git a/drivers/staging/line6/variax.c b/drivers/staging/line6/variax.c -index bb99ee4..f97416b 100644 ---- a/drivers/staging/line6/variax.c -+++ b/drivers/staging/line6/variax.c -@@ -353,10 +353,10 @@ static ssize_t variax_set_model(struct device *dev, +Index: linux-3.2.46/drivers/staging/line6/variax.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/variax.c 2013-07-26 19:28:40.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/variax.c 2013-07-26 19:28:51.000000000 +0000 +@@ -353,10 +353,10 @@ { struct usb_line6_variax *variax = usb_get_intfdata(to_usb_interface(dev)); @@ -31,7 +31,7 @@ if (ret) return ret; -@@ -387,10 +387,10 @@ static ssize_t variax_set_active(struct device *dev, +@@ -387,10 +387,10 @@ { struct usb_line6_variax *variax = usb_get_intfdata(to_usb_interface(dev)); diff -Nru linux-3.2.46/debian/patches/features/all/line6/0042-staging-line6-drop-unused-line6_devices-array.patch linux-3.2.46/debian/patches/features/all/line6/0042-staging-line6-drop-unused-line6_devices-array.patch --- linux-3.2.46/debian/patches/features/all/line6/0042-staging-line6-drop-unused-line6_devices-array.patch 2013-02-24 03:52:35.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/line6/0042-staging-line6-drop-unused-line6_devices-array.patch 2013-07-26 19:28:54.000000000 +0000 @@ -14,11 +14,11 @@ drivers/staging/line6/driver.h | 2 -- 2 files changed, 1 insertion(+), 21 deletions(-) -diff --git a/drivers/staging/line6/driver.c b/drivers/staging/line6/driver.c -index b8358ca..ac11a3b 100644 ---- a/drivers/staging/line6/driver.c -+++ b/drivers/staging/line6/driver.c -@@ -96,8 +96,6 @@ static const char line6_request_version[] = { +Index: linux-3.2.46/drivers/staging/line6/driver.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/driver.c 2013-07-26 19:28:42.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/driver.c 2013-07-26 19:28:53.000000000 +0000 +@@ -96,8 +96,6 @@ 0xf0, 0x7e, 0x7f, 0x06, 0x01, 0xf7 }; @@ -27,7 +27,7 @@ /** Class for asynchronous messages. */ -@@ -740,7 +738,6 @@ static int line6_probe(struct usb_interface *interface, +@@ -740,7 +738,6 @@ struct usb_device *usbdev; struct usb_line6 *line6; const struct line6_properties *properties; @@ -35,7 +35,7 @@ int interface_number, alternate = 0; int product; int size = 0; -@@ -774,16 +771,6 @@ static int line6_probe(struct usb_interface *interface, +@@ -774,16 +771,6 @@ goto err_put; } @@ -52,7 +52,7 @@ /* initialize device info: */ properties = &line6_properties_table[devtype]; dev_info(&interface->dev, "Line6 %s found\n", properties->name); -@@ -1112,7 +1099,6 @@ static int line6_probe(struct usb_interface *interface, +@@ -1112,7 +1099,6 @@ dev_info(&interface->dev, "Line6 %s now attached\n", line6->properties->name); @@ -60,7 +60,7 @@ switch (product) { case LINE6_DEVID_PODX3: -@@ -1141,7 +1127,7 @@ static void line6_disconnect(struct usb_interface *interface) +@@ -1141,7 +1127,7 @@ { struct usb_line6 *line6; struct usb_device *usbdev; @@ -69,7 +69,7 @@ if (interface == NULL) return; -@@ -1214,10 +1200,6 @@ static void line6_disconnect(struct usb_interface *interface) +@@ -1214,10 +1200,6 @@ dev_info(&interface->dev, "Line6 %s now disconnected\n", line6->properties->name); @@ -80,10 +80,10 @@ } line6_destruct(interface); -diff --git a/drivers/staging/line6/driver.h b/drivers/staging/line6/driver.h -index a3029eb..35246cf 100644 ---- a/drivers/staging/line6/driver.h -+++ b/drivers/staging/line6/driver.h +Index: linux-3.2.46/drivers/staging/line6/driver.h +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/driver.h 2013-07-26 19:28:42.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/driver.h 2013-07-26 19:28:53.000000000 +0000 @@ -25,7 +25,6 @@ #endif @@ -92,7 +92,7 @@ #define LINE6_BUFSIZE_LISTEN 32 #define LINE6_MESSAGE_MAXLEN 256 -@@ -78,7 +77,6 @@ do { \ +@@ -78,7 +77,6 @@ } while (0) extern const unsigned char line6_midi_id[3]; diff -Nru linux-3.2.46/debian/patches/features/all/line6/0043-staging-line6-drop-unused-line6_index-and-line6_id-a.patch linux-3.2.46/debian/patches/features/all/line6/0043-staging-line6-drop-unused-line6_index-and-line6_id-a.patch --- linux-3.2.46/debian/patches/features/all/line6/0043-staging-line6-drop-unused-line6_index-and-line6_id-a.patch 2013-02-24 03:52:35.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/line6/0043-staging-line6-drop-unused-line6_index-and-line6_id-a.patch 2013-07-26 19:28:55.000000000 +0000 @@ -15,10 +15,10 @@ drivers/staging/line6/audio.c | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) -diff --git a/drivers/staging/line6/audio.c b/drivers/staging/line6/audio.c -index 8e73983..a92e21f 100644 ---- a/drivers/staging/line6/audio.c -+++ b/drivers/staging/line6/audio.c +Index: linux-3.2.46/drivers/staging/line6/audio.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/audio.c 2013-07-26 18:52:48.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/audio.c 2013-07-26 19:28:54.000000000 +0000 @@ -16,20 +16,16 @@ #include "driver.h" #include "audio.h" diff -Nru linux-3.2.46/debian/patches/features/all/line6/0044-staging-line6-wrap-80-char-lines-in-capture.c.patch linux-3.2.46/debian/patches/features/all/line6/0044-staging-line6-wrap-80-char-lines-in-capture.c.patch --- linux-3.2.46/debian/patches/features/all/line6/0044-staging-line6-wrap-80-char-lines-in-capture.c.patch 2013-02-24 03:52:35.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/line6/0044-staging-line6-wrap-80-char-lines-in-capture.c.patch 2013-07-26 19:28:56.000000000 +0000 @@ -10,11 +10,11 @@ drivers/staging/line6/capture.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) -diff --git a/drivers/staging/line6/capture.c b/drivers/staging/line6/capture.c -index c85c5b6..389c41f 100644 ---- a/drivers/staging/line6/capture.c -+++ b/drivers/staging/line6/capture.c -@@ -256,8 +256,8 @@ static void audio_in_callback(struct urb *urb) +Index: linux-3.2.46/drivers/staging/line6/capture.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/capture.c 2013-07-26 19:28:24.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/capture.c 2013-07-26 19:28:55.000000000 +0000 +@@ -256,8 +256,8 @@ #ifdef CONFIG_LINE6_USB_IMPULSE_RESPONSE if (!(line6pcm->flags & LINE6_BITS_PCM_IMPULSE)) #endif @@ -25,7 +25,7 @@ line6_capture_copy(line6pcm, fbuf, fsize); } -@@ -274,7 +274,8 @@ static void audio_in_callback(struct urb *urb) +@@ -274,7 +274,8 @@ #ifdef CONFIG_LINE6_USB_IMPULSE_RESPONSE if (!(line6pcm->flags & LINE6_BITS_PCM_IMPULSE)) #endif @@ -35,7 +35,7 @@ line6_capture_check_period(line6pcm, length); } } -@@ -356,7 +357,8 @@ int snd_line6_capture_trigger(struct snd_line6_pcm *line6pcm, int cmd) +@@ -356,7 +357,8 @@ #ifdef CONFIG_PM case SNDRV_PCM_TRIGGER_RESUME: #endif @@ -45,7 +45,7 @@ if (err < 0) return err; -@@ -367,7 +369,8 @@ int snd_line6_capture_trigger(struct snd_line6_pcm *line6pcm, int cmd) +@@ -367,7 +369,8 @@ #ifdef CONFIG_PM case SNDRV_PCM_TRIGGER_SUSPEND: #endif diff -Nru linux-3.2.46/debian/patches/features/all/line6/0045-staging-line6-fix-quoted-string-across-lines-in-midi.patch linux-3.2.46/debian/patches/features/all/line6/0045-staging-line6-fix-quoted-string-across-lines-in-midi.patch --- linux-3.2.46/debian/patches/features/all/line6/0045-staging-line6-fix-quoted-string-across-lines-in-midi.patch 2013-02-24 03:52:35.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/line6/0045-staging-line6-fix-quoted-string-across-lines-in-midi.patch 2013-07-26 19:28:58.000000000 +0000 @@ -16,11 +16,11 @@ drivers/staging/line6/midibuf.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) -diff --git a/drivers/staging/line6/midibuf.c b/drivers/staging/line6/midibuf.c -index 836e8c8..968e0de 100644 ---- a/drivers/staging/line6/midibuf.c -+++ b/drivers/staging/line6/midibuf.c -@@ -64,9 +64,9 @@ int line6_midibuf_init(struct MidiBuffer *this, int size, int split) +Index: linux-3.2.46/drivers/staging/line6/midibuf.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/midibuf.c 2013-07-26 19:28:32.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/midibuf.c 2013-07-26 19:28:57.000000000 +0000 +@@ -64,9 +64,9 @@ void line6_midibuf_status(struct MidiBuffer *this) { diff -Nru linux-3.2.46/debian/patches/features/all/line6/0046-staging-line6-shorten-comment-below-80-chars-in-pcm..patch linux-3.2.46/debian/patches/features/all/line6/0046-staging-line6-shorten-comment-below-80-chars-in-pcm..patch --- linux-3.2.46/debian/patches/features/all/line6/0046-staging-line6-shorten-comment-below-80-chars-in-pcm..patch 2013-02-24 03:52:35.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/line6/0046-staging-line6-shorten-comment-below-80-chars-in-pcm..patch 2013-07-26 19:28:59.000000000 +0000 @@ -10,11 +10,11 @@ drivers/staging/line6/pcm.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -diff --git a/drivers/staging/line6/pcm.c b/drivers/staging/line6/pcm.c -index 7fe44a6..6c1e313 100644 ---- a/drivers/staging/line6/pcm.c -+++ b/drivers/staging/line6/pcm.c -@@ -109,7 +109,7 @@ int line6_pcm_acquire(struct snd_line6_pcm *line6pcm, int channels) +Index: linux-3.2.46/drivers/staging/line6/pcm.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/pcm.c 2013-07-26 19:28:50.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/pcm.c 2013-07-26 19:28:58.000000000 +0000 +@@ -109,7 +109,7 @@ line6pcm->prev_fbuf = NULL; if (test_flags(flags_old, flags_new, LINE6_BITS_CAPTURE_BUFFER)) { @@ -23,7 +23,7 @@ if (!line6pcm->buffer_in) { line6pcm->buffer_in = kmalloc(LINE6_ISO_BUFFERS * LINE6_ISO_PACKETS * -@@ -148,7 +148,7 @@ int line6_pcm_acquire(struct snd_line6_pcm *line6pcm, int channels) +@@ -148,7 +148,7 @@ } if (test_flags(flags_old, flags_new, LINE6_BITS_PLAYBACK_BUFFER)) { diff -Nru linux-3.2.46/debian/patches/features/all/line6/0047-staging-line6-drop-trailing-whitespace-in-pcm.h.patch linux-3.2.46/debian/patches/features/all/line6/0047-staging-line6-drop-trailing-whitespace-in-pcm.h.patch --- linux-3.2.46/debian/patches/features/all/line6/0047-staging-line6-drop-trailing-whitespace-in-pcm.h.patch 2013-02-24 03:52:35.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/line6/0047-staging-line6-drop-trailing-whitespace-in-pcm.h.patch 2013-07-26 19:29:00.000000000 +0000 @@ -10,11 +10,11 @@ drivers/staging/line6/pcm.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -diff --git a/drivers/staging/line6/pcm.h b/drivers/staging/line6/pcm.h -index 5210ec8..6aa0d46 100644 ---- a/drivers/staging/line6/pcm.h -+++ b/drivers/staging/line6/pcm.h -@@ -167,7 +167,7 @@ enum { +Index: linux-3.2.46/drivers/staging/line6/pcm.h +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/pcm.h 2013-07-26 19:28:24.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/pcm.h 2013-07-26 19:28:59.000000000 +0000 +@@ -167,7 +167,7 @@ #endif LINE6_BIT_PCM_ALSA_CAPTURE_STREAM | LINE6_BIT_PCM_MONITOR_CAPTURE_STREAM, diff -Nru linux-3.2.46/debian/patches/features/all/line6/0048-staging-line6-wrap-lines-to-80-chars-in-playback.c.patch linux-3.2.46/debian/patches/features/all/line6/0048-staging-line6-wrap-lines-to-80-chars-in-playback.c.patch --- linux-3.2.46/debian/patches/features/all/line6/0048-staging-line6-wrap-lines-to-80-chars-in-playback.c.patch 2013-02-24 03:52:35.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/line6/0048-staging-line6-wrap-lines-to-80-chars-in-playback.c.patch 2013-07-26 19:29:01.000000000 +0000 @@ -15,11 +15,11 @@ drivers/staging/line6/playback.c | 17 +++++++++++------ 1 file changed, 11 insertions(+), 6 deletions(-) -diff --git a/drivers/staging/line6/playback.c b/drivers/staging/line6/playback.c -index a0ab9d0..4cf23af 100644 ---- a/drivers/staging/line6/playback.c -+++ b/drivers/staging/line6/playback.c -@@ -185,7 +185,7 @@ static int submit_audio_out_urb(struct snd_line6_pcm *line6pcm) +Index: linux-3.2.46/drivers/staging/line6/playback.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/playback.c 2013-07-26 19:28:24.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/playback.c 2013-07-26 19:29:00.000000000 +0000 +@@ -185,7 +185,7 @@ if (urb_size == 0) { /* can't determine URB size */ spin_unlock_irqrestore(&line6pcm->lock_audio_out, flags); @@ -28,7 +28,7 @@ return -EINVAL; } -@@ -218,7 +218,8 @@ static int submit_audio_out_urb(struct snd_line6_pcm *line6pcm) +@@ -218,7 +218,8 @@ len * bytes_per_frame, runtime->dma_area, (urb_frames - len) * bytes_per_frame); } else @@ -38,7 +38,7 @@ } else { memcpy(urb_out->transfer_buffer, runtime->dma_area + -@@ -319,7 +320,8 @@ void line6_unlink_audio_out_urbs(struct snd_line6_pcm *line6pcm) +@@ -319,7 +320,8 @@ } /* @@ -48,7 +48,7 @@ */ void line6_wait_clear_audio_out_urbs(struct snd_line6_pcm *line6pcm) { -@@ -413,7 +415,8 @@ static void audio_out_callback(struct urb *urb) +@@ -413,7 +415,8 @@ if (!shutdown) { submit_audio_out_urb(line6pcm); @@ -58,7 +58,7 @@ line6pcm->bytes_out += length; if (line6pcm->bytes_out >= line6pcm->period_out) { line6pcm->bytes_out %= line6pcm->period_out; -@@ -499,7 +502,8 @@ int snd_line6_playback_trigger(struct snd_line6_pcm *line6pcm, int cmd) +@@ -499,7 +502,8 @@ #ifdef CONFIG_PM case SNDRV_PCM_TRIGGER_RESUME: #endif @@ -68,7 +68,7 @@ if (err < 0) return err; -@@ -510,7 +514,8 @@ int snd_line6_playback_trigger(struct snd_line6_pcm *line6pcm, int cmd) +@@ -510,7 +514,8 @@ #ifdef CONFIG_PM case SNDRV_PCM_TRIGGER_SUSPEND: #endif diff -Nru linux-3.2.46/debian/patches/features/all/line6/0049-staging-line6-replace-deprecated-strict_strtol-in-to.patch linux-3.2.46/debian/patches/features/all/line6/0049-staging-line6-replace-deprecated-strict_strtol-in-to.patch --- linux-3.2.46/debian/patches/features/all/line6/0049-staging-line6-replace-deprecated-strict_strtol-in-to.patch 2013-02-24 03:52:35.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/line6/0049-staging-line6-replace-deprecated-strict_strtol-in-to.patch 2013-07-26 19:29:03.000000000 +0000 @@ -16,11 +16,11 @@ drivers/staging/line6/toneport.c | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) -diff --git a/drivers/staging/line6/toneport.c b/drivers/staging/line6/toneport.c -index 31b624b..a529dd3 100644 ---- a/drivers/staging/line6/toneport.c -+++ b/drivers/staging/line6/toneport.c -@@ -127,13 +127,11 @@ static ssize_t toneport_set_led_red(struct device *dev, +Index: linux-3.2.46/drivers/staging/line6/toneport.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/toneport.c 2013-07-26 19:28:31.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/toneport.c 2013-07-26 19:29:02.000000000 +0000 +@@ -127,13 +127,11 @@ const char *buf, size_t count) { int retval; @@ -35,7 +35,7 @@ toneport_update_led(dev); return count; } -@@ -143,13 +141,11 @@ static ssize_t toneport_set_led_green(struct device *dev, +@@ -143,13 +141,11 @@ const char *buf, size_t count) { int retval; diff -Nru linux-3.2.46/debian/patches/features/all/line6/0050-staging-line6-wrap-lines-to-80-chars-in-usbdefs.h.patch linux-3.2.46/debian/patches/features/all/line6/0050-staging-line6-wrap-lines-to-80-chars-in-usbdefs.h.patch --- linux-3.2.46/debian/patches/features/all/line6/0050-staging-line6-wrap-lines-to-80-chars-in-usbdefs.h.patch 2013-02-24 03:52:35.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/line6/0050-staging-line6-wrap-lines-to-80-chars-in-usbdefs.h.patch 2013-07-26 19:29:04.000000000 +0000 @@ -10,11 +10,11 @@ drivers/staging/line6/usbdefs.h | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) -diff --git a/drivers/staging/line6/usbdefs.h b/drivers/staging/line6/usbdefs.h -index 353d59d..43eb540 100644 ---- a/drivers/staging/line6/usbdefs.h -+++ b/drivers/staging/line6/usbdefs.h -@@ -83,11 +83,15 @@ enum { +Index: linux-3.2.46/drivers/staging/line6/usbdefs.h +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/usbdefs.h 2013-07-26 19:28:24.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/usbdefs.h 2013-07-26 19:29:03.000000000 +0000 +@@ -83,11 +83,15 @@ LINE6_BIT(VARIAX), LINE6_BITS_PRO = LINE6_BIT_BASSPODXTPRO | LINE6_BIT_PODXTPRO, diff -Nru linux-3.2.46/debian/patches/features/all/line6/0051-staging-line6-wrap-comment-to-80-chars-in-variax.c.patch linux-3.2.46/debian/patches/features/all/line6/0051-staging-line6-wrap-comment-to-80-chars-in-variax.c.patch --- linux-3.2.46/debian/patches/features/all/line6/0051-staging-line6-wrap-comment-to-80-chars-in-variax.c.patch 2013-02-24 03:52:35.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/line6/0051-staging-line6-wrap-comment-to-80-chars-in-variax.c.patch 2013-07-26 19:29:05.000000000 +0000 @@ -10,11 +10,11 @@ drivers/staging/line6/variax.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) -diff --git a/drivers/staging/line6/variax.c b/drivers/staging/line6/variax.c -index f97416b..1b85ecc 100644 ---- a/drivers/staging/line6/variax.c -+++ b/drivers/staging/line6/variax.c -@@ -160,7 +160,9 @@ static void variax_startup5(unsigned long data) +Index: linux-3.2.46/drivers/staging/line6/variax.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/variax.c 2013-07-26 19:28:51.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/variax.c 2013-07-26 19:29:04.000000000 +0000 +@@ -160,7 +160,9 @@ /* current model dump: */ line6_dump_request_async(&variax->dumpreq, &variax->line6, 0, VARIAX_DUMP_PASS1); diff -Nru linux-3.2.46/debian/patches/features/all/line6/0052-staging-line6-replace-DEBUG_MESSAGES-with-dev_dbg.patch linux-3.2.46/debian/patches/features/all/line6/0052-staging-line6-replace-DEBUG_MESSAGES-with-dev_dbg.patch --- linux-3.2.46/debian/patches/features/all/line6/0052-staging-line6-replace-DEBUG_MESSAGES-with-dev_dbg.patch 2013-02-24 03:52:35.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/line6/0052-staging-line6-replace-DEBUG_MESSAGES-with-dev_dbg.patch 2013-07-26 19:29:07.000000000 +0000 @@ -16,11 +16,11 @@ drivers/staging/line6/variax.c | 12 ++++----- 3 files changed, 28 insertions(+), 47 deletions(-) -diff --git a/drivers/staging/line6/driver.c b/drivers/staging/line6/driver.c -index ac11a3b..571f2ce 100644 ---- a/drivers/staging/line6/driver.c -+++ b/drivers/staging/line6/driver.c -@@ -412,10 +412,8 @@ static void line6_data_received(struct urb *urb) +Index: linux-3.2.46/drivers/staging/line6/driver.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/driver.c 2013-07-26 19:28:53.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/driver.c 2013-07-26 19:29:06.000000000 +0000 +@@ -412,10 +412,8 @@ if (done < urb->actual_length) { line6_midibuf_ignore(mb, done); @@ -33,11 +33,11 @@ } for (;;) { -diff --git a/drivers/staging/line6/pod.c b/drivers/staging/line6/pod.c -index 9edd053..4a86f7a 100644 ---- a/drivers/staging/line6/pod.c -+++ b/drivers/staging/line6/pod.c -@@ -252,25 +252,19 @@ void line6_pod_process_message(struct usb_line6_pod *pod) +Index: linux-3.2.46/drivers/staging/line6/pod.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/pod.c 2013-07-26 19:28:49.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/pod.c 2013-07-26 19:29:06.000000000 +0000 +@@ -252,25 +252,19 @@ break; default: @@ -71,7 +71,7 @@ break; -@@ -302,11 +296,9 @@ void line6_pod_process_message(struct usb_line6_pod *pod) +@@ -302,11 +296,9 @@ #undef PROCESS_SYSTEM_PARAM default: @@ -86,7 +86,7 @@ } break; -@@ -321,25 +313,21 @@ void line6_pod_process_message(struct usb_line6_pod *pod) +@@ -321,25 +313,21 @@ break; case POD_SYSEX_CLIP: @@ -119,7 +119,7 @@ } } else if (memcmp -@@ -352,9 +340,7 @@ void line6_pod_process_message(struct usb_line6_pod *pod) +@@ -352,9 +340,7 @@ buf[10]; pod_startup4(pod); } else @@ -130,7 +130,7 @@ break; -@@ -362,9 +348,8 @@ void line6_pod_process_message(struct usb_line6_pod *pod) +@@ -362,9 +348,8 @@ break; default: @@ -142,11 +142,11 @@ } } -diff --git a/drivers/staging/line6/variax.c b/drivers/staging/line6/variax.c -index 1b85ecc..8df529f 100644 ---- a/drivers/staging/line6/variax.c -+++ b/drivers/staging/line6/variax.c -@@ -262,10 +262,9 @@ void line6_variax_process_message(struct usb_line6_variax *variax) +Index: linux-3.2.46/drivers/staging/line6/variax.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/variax.c 2013-07-26 19:29:04.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/variax.c 2013-07-26 19:29:06.000000000 +0000 +@@ -262,10 +262,9 @@ 2, VARIAX_DUMP_PASS3); } } else { @@ -160,7 +160,7 @@ line6_dump_finished(&variax->dumpreq); } } else if (memcmp(buf + 1, variax_request_bank + 1, -@@ -295,9 +294,8 @@ void line6_variax_process_message(struct usb_line6_variax *variax) +@@ -295,9 +294,8 @@ break; default: diff -Nru linux-3.2.46/debian/patches/features/all/line6/0053-staging-line6-drop-unused-DEBUG_MESSAGES-macro.patch linux-3.2.46/debian/patches/features/all/line6/0053-staging-line6-drop-unused-DEBUG_MESSAGES-macro.patch --- linux-3.2.46/debian/patches/features/all/line6/0053-staging-line6-drop-unused-DEBUG_MESSAGES-macro.patch 2013-02-24 03:52:35.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/line6/0053-staging-line6-drop-unused-DEBUG_MESSAGES-macro.patch 2013-07-26 19:29:08.000000000 +0000 @@ -13,10 +13,10 @@ drivers/staging/line6/driver.h | 6 ------ 1 file changed, 6 deletions(-) -diff --git a/drivers/staging/line6/driver.h b/drivers/staging/line6/driver.h -index 35246cf..9dd8ff4 100644 ---- a/drivers/staging/line6/driver.h -+++ b/drivers/staging/line6/driver.h +Index: linux-3.2.46/drivers/staging/line6/driver.h +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/driver.h 2013-07-26 19:28:53.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/driver.h 2013-07-26 19:29:07.000000000 +0000 @@ -52,12 +52,6 @@ #define LINE6_CHANNEL_MASK 0x0f diff -Nru linux-3.2.46/debian/patches/features/all/line6/0054-staging-line6-drop-unused-CONFIG_LINE6_USB_DEBUG.patch linux-3.2.46/debian/patches/features/all/line6/0054-staging-line6-drop-unused-CONFIG_LINE6_USB_DEBUG.patch --- linux-3.2.46/debian/patches/features/all/line6/0054-staging-line6-drop-unused-CONFIG_LINE6_USB_DEBUG.patch 2013-02-24 03:52:35.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/line6/0054-staging-line6-drop-unused-CONFIG_LINE6_USB_DEBUG.patch 2013-07-26 19:29:09.000000000 +0000 @@ -14,11 +14,11 @@ drivers/staging/line6/Kconfig | 8 -------- 1 file changed, 8 deletions(-) -diff --git a/drivers/staging/line6/Kconfig b/drivers/staging/line6/Kconfig -index 43120ff..a5ded12 100644 ---- a/drivers/staging/line6/Kconfig -+++ b/drivers/staging/line6/Kconfig -@@ -23,14 +23,6 @@ menuconfig LINE6_USB +Index: linux-3.2.46/drivers/staging/line6/Kconfig +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/Kconfig 2013-07-26 18:52:45.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/Kconfig 2013-07-26 19:29:08.000000000 +0000 +@@ -23,14 +23,6 @@ if LINE6_USB diff -Nru linux-3.2.46/debian/patches/features/all/line6/0055-staging-line6-drop-control-URB-dumping-code.patch linux-3.2.46/debian/patches/features/all/line6/0055-staging-line6-drop-control-URB-dumping-code.patch --- linux-3.2.46/debian/patches/features/all/line6/0055-staging-line6-drop-control-URB-dumping-code.patch 2013-02-24 03:52:35.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/line6/0055-staging-line6-drop-control-URB-dumping-code.patch 2013-07-26 19:29:11.000000000 +0000 @@ -19,11 +19,11 @@ drivers/staging/line6/midi.c | 3 --- 2 files changed, 39 deletions(-) -diff --git a/drivers/staging/line6/driver.c b/drivers/staging/line6/driver.c -index 571f2ce..fda92d1e 100644 ---- a/drivers/staging/line6/driver.c -+++ b/drivers/staging/line6/driver.c -@@ -177,22 +177,6 @@ void line6_write_hexdump(struct usb_line6 *line6, char dir, +Index: linux-3.2.46/drivers/staging/line6/driver.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/driver.c 2013-07-26 19:29:06.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/driver.c 2013-07-26 19:29:10.000000000 +0000 +@@ -177,22 +177,6 @@ } #endif @@ -46,7 +46,7 @@ /* Send raw message in pieces of wMaxPacketSize bytes. */ -@@ -201,10 +185,6 @@ int line6_send_raw_message(struct usb_line6 *line6, const char *buffer, +@@ -201,10 +185,6 @@ { int i, done = 0; @@ -57,7 +57,7 @@ for (i = 0; i < size; i += line6->max_packet_size) { int partial; const char *frag_buf = buffer + i; -@@ -259,10 +239,6 @@ static int line6_send_raw_message_async_part(struct message *msg, +@@ -259,10 +239,6 @@ (char *)msg->buffer + done, bytes, line6_async_request_sent, msg, line6->interval); @@ -68,7 +68,7 @@ msg->done += bytes; retval = usb_submit_urb(urb, GFP_ATOMIC); -@@ -403,10 +379,6 @@ static void line6_data_received(struct urb *urb) +@@ -403,10 +379,6 @@ if (urb->status == -ESHUTDOWN) return; @@ -79,7 +79,7 @@ done = line6_midibuf_write(mb, urb->transfer_buffer, urb->actual_length); -@@ -502,10 +474,6 @@ int line6_send_program(struct usb_line6 *line6, u8 value) +@@ -502,10 +474,6 @@ buffer[0] = LINE6_PROGRAM_CHANGE | LINE6_CHANNEL_HOST; buffer[1] = value; @@ -90,7 +90,7 @@ retval = usb_interrupt_msg(line6->usbdev, usb_sndintpipe(line6->usbdev, line6->ep_control_write), -@@ -539,10 +507,6 @@ int line6_transmit_parameter(struct usb_line6 *line6, int param, u8 value) +@@ -539,10 +507,6 @@ buffer[1] = param; buffer[2] = value; @@ -101,11 +101,11 @@ retval = usb_interrupt_msg(line6->usbdev, usb_sndintpipe(line6->usbdev, line6->ep_control_write), -diff --git a/drivers/staging/line6/midi.c b/drivers/staging/line6/midi.c -index 5040729..348d425 100644 ---- a/drivers/staging/line6/midi.c -+++ b/drivers/staging/line6/midi.c -@@ -131,9 +131,6 @@ static int send_midi_async(struct usb_line6 *line6, unsigned char *data, +Index: linux-3.2.46/drivers/staging/line6/midi.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/midi.c 2013-07-26 19:28:33.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/midi.c 2013-07-26 19:29:10.000000000 +0000 +@@ -131,9 +131,6 @@ dev_err(line6->ifcdev, "Out of memory\n"); return -ENOMEM; } diff -Nru linux-3.2.46/debian/patches/features/all/line6/0056-staging-line6-drop-CONTROL-from-CONFIG_LINE6_USB_DUM.patch linux-3.2.46/debian/patches/features/all/line6/0056-staging-line6-drop-CONTROL-from-CONFIG_LINE6_USB_DUM.patch --- linux-3.2.46/debian/patches/features/all/line6/0056-staging-line6-drop-CONTROL-from-CONFIG_LINE6_USB_DUM.patch 2013-02-24 03:52:35.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/line6/0056-staging-line6-drop-CONTROL-from-CONFIG_LINE6_USB_DUM.patch 2013-07-26 19:29:12.000000000 +0000 @@ -14,10 +14,10 @@ drivers/staging/line6/driver.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -diff --git a/drivers/staging/line6/driver.h b/drivers/staging/line6/driver.h -index 9dd8ff4..7770635 100644 ---- a/drivers/staging/line6/driver.h -+++ b/drivers/staging/line6/driver.h +Index: linux-3.2.46/drivers/staging/line6/driver.h +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/driver.h 2013-07-26 19:29:07.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/driver.h 2013-07-26 19:29:11.000000000 +0000 @@ -20,7 +20,7 @@ #define DRIVER_NAME "line6usb" diff -Nru linux-3.2.46/debian/patches/features/all/line6/0057-staging-line6-drop-unused-CONFIG_LINE6_USB_DUMP_CTRL.patch linux-3.2.46/debian/patches/features/all/line6/0057-staging-line6-drop-unused-CONFIG_LINE6_USB_DUMP_CTRL.patch --- linux-3.2.46/debian/patches/features/all/line6/0057-staging-line6-drop-unused-CONFIG_LINE6_USB_DUMP_CTRL.patch 2013-02-24 03:52:35.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/line6/0057-staging-line6-drop-unused-CONFIG_LINE6_USB_DUMP_CTRL.patch 2013-07-26 19:29:13.000000000 +0000 @@ -10,11 +10,11 @@ drivers/staging/line6/Kconfig | 9 --------- 1 file changed, 9 deletions(-) -diff --git a/drivers/staging/line6/Kconfig b/drivers/staging/line6/Kconfig -index a5ded12..2101799 100644 ---- a/drivers/staging/line6/Kconfig -+++ b/drivers/staging/line6/Kconfig -@@ -23,15 +23,6 @@ menuconfig LINE6_USB +Index: linux-3.2.46/drivers/staging/line6/Kconfig +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/Kconfig 2013-07-26 19:29:08.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/Kconfig 2013-07-26 19:29:12.000000000 +0000 +@@ -23,15 +23,6 @@ if LINE6_USB diff -Nru linux-3.2.46/debian/patches/features/all/line6/0058-staging-line6-drop-MIDI-dumping-code.patch linux-3.2.46/debian/patches/features/all/line6/0058-staging-line6-drop-MIDI-dumping-code.patch --- linux-3.2.46/debian/patches/features/all/line6/0058-staging-line6-drop-MIDI-dumping-code.patch 2013-02-24 03:52:35.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/line6/0058-staging-line6-drop-MIDI-dumping-code.patch 2013-07-26 19:29:15.000000000 +0000 @@ -16,11 +16,11 @@ drivers/staging/line6/midi.c | 3 --- 2 files changed, 6 deletions(-) -diff --git a/drivers/staging/line6/driver.c b/drivers/staging/line6/driver.c -index fda92d1e..0bc838d 100644 ---- a/drivers/staging/line6/driver.c -+++ b/drivers/staging/line6/driver.c -@@ -402,9 +402,6 @@ static void line6_data_received(struct urb *urb) +Index: linux-3.2.46/drivers/staging/line6/driver.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/driver.c 2013-07-26 19:29:10.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/driver.c 2013-07-26 19:29:14.000000000 +0000 +@@ -402,9 +402,6 @@ continue; line6->message_length = done; @@ -30,11 +30,11 @@ line6_midi_receive(line6, line6->buffer_message, done); switch (line6->usbdev->descriptor.idProduct) { -diff --git a/drivers/staging/line6/midi.c b/drivers/staging/line6/midi.c -index 348d425..c8e099b 100644 ---- a/drivers/staging/line6/midi.c -+++ b/drivers/staging/line6/midi.c -@@ -59,9 +59,6 @@ static void line6_midi_transmit(struct snd_rawmidi_substream *substream) +Index: linux-3.2.46/drivers/staging/line6/midi.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/midi.c 2013-07-26 19:29:10.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/midi.c 2013-07-26 19:29:14.000000000 +0000 +@@ -59,9 +59,6 @@ if (done == 0) break; diff -Nru linux-3.2.46/debian/patches/features/all/line6/0059-staging-line6-drop-MIDI-from-CONFIG_LINE6_USB_DUMP_A.patch linux-3.2.46/debian/patches/features/all/line6/0059-staging-line6-drop-MIDI-from-CONFIG_LINE6_USB_DUMP_A.patch --- linux-3.2.46/debian/patches/features/all/line6/0059-staging-line6-drop-MIDI-from-CONFIG_LINE6_USB_DUMP_A.patch 2013-02-24 03:52:35.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/line6/0059-staging-line6-drop-MIDI-from-CONFIG_LINE6_USB_DUMP_A.patch 2013-07-26 19:29:16.000000000 +0000 @@ -13,10 +13,10 @@ drivers/staging/line6/driver.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -diff --git a/drivers/staging/line6/driver.h b/drivers/staging/line6/driver.h -index 7770635..f0be5a2 100644 ---- a/drivers/staging/line6/driver.h -+++ b/drivers/staging/line6/driver.h +Index: linux-3.2.46/drivers/staging/line6/driver.h +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/driver.h 2013-07-26 19:29:11.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/driver.h 2013-07-26 19:29:15.000000000 +0000 @@ -20,7 +20,7 @@ #define DRIVER_NAME "line6usb" diff -Nru linux-3.2.46/debian/patches/features/all/line6/0060-staging-line6-drop-unused-CONFIG_LINE6_USB_DUMP_MIDI.patch linux-3.2.46/debian/patches/features/all/line6/0060-staging-line6-drop-unused-CONFIG_LINE6_USB_DUMP_MIDI.patch --- linux-3.2.46/debian/patches/features/all/line6/0060-staging-line6-drop-unused-CONFIG_LINE6_USB_DUMP_MIDI.patch 2013-02-24 03:52:35.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/line6/0060-staging-line6-drop-unused-CONFIG_LINE6_USB_DUMP_MIDI.patch 2013-07-26 19:29:17.000000000 +0000 @@ -10,11 +10,11 @@ drivers/staging/line6/Kconfig | 9 --------- 1 file changed, 9 deletions(-) -diff --git a/drivers/staging/line6/Kconfig b/drivers/staging/line6/Kconfig -index 2101799..80a7202 100644 ---- a/drivers/staging/line6/Kconfig -+++ b/drivers/staging/line6/Kconfig -@@ -23,15 +23,6 @@ menuconfig LINE6_USB +Index: linux-3.2.46/drivers/staging/line6/Kconfig +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/Kconfig 2013-07-26 19:29:12.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/Kconfig 2013-07-26 19:29:16.000000000 +0000 +@@ -23,15 +23,6 @@ if LINE6_USB diff -Nru linux-3.2.46/debian/patches/features/all/line6/0061-staging-line6-drop-channel-sysfs-attr.patch linux-3.2.46/debian/patches/features/all/line6/0061-staging-line6-drop-channel-sysfs-attr.patch --- linux-3.2.46/debian/patches/features/all/line6/0061-staging-line6-drop-channel-sysfs-attr.patch 2013-02-24 03:52:35.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/line6/0061-staging-line6-drop-channel-sysfs-attr.patch 2013-07-26 19:29:18.000000000 +0000 @@ -11,11 +11,11 @@ drivers/staging/line6/pod.h | 5 ----- 2 files changed, 56 deletions(-) -diff --git a/drivers/staging/line6/pod.c b/drivers/staging/line6/pod.c -index 4a86f7a..e3e2247 100644 ---- a/drivers/staging/line6/pod.c -+++ b/drivers/staging/line6/pod.c -@@ -223,7 +223,6 @@ void line6_pod_process_message(struct usb_line6_pod *pod) +Index: linux-3.2.46/drivers/staging/line6/pod.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/pod.c 2013-07-26 19:29:06.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/pod.c 2013-07-26 19:29:17.000000000 +0000 +@@ -223,7 +223,6 @@ case LINE6_PROGRAM_CHANGE | LINE6_CHANNEL_DEVICE: case LINE6_PROGRAM_CHANGE | LINE6_CHANNEL_HOST: @@ -23,7 +23,7 @@ pod->dirty = 0; set_bit(POD_CHANNEL_DIRTY, &pod->atomic_flags); line6_dump_request_async(&pod->dumpreq, &pod->line6, 0, -@@ -388,19 +387,6 @@ void line6_pod_midi_postprocess(struct usb_line6_pod *pod, unsigned char *data, +@@ -388,19 +387,6 @@ } /* @@ -43,7 +43,7 @@ Transmit PODxt Pro control parameter. */ void line6_pod_transmit_parameter(struct usb_line6_pod *pod, int param, -@@ -526,37 +512,6 @@ static ssize_t get_name_generic(struct usb_line6_pod *pod, const char *str, +@@ -526,37 +512,6 @@ } /* @@ -81,7 +81,7 @@ "read" request on "name" special file. */ static ssize_t pod_get_name(struct device *dev, struct device_attribute *attr, -@@ -1036,8 +991,6 @@ POD_GET_SYSTEM_PARAM(tuner_pitch, 1); +@@ -1036,8 +991,6 @@ #undef GET_SYSTEM_PARAM /* POD special files: */ @@ -90,7 +90,7 @@ static DEVICE_ATTR(clip, S_IRUGO, pod_wait_for_clip, line6_nop_write); static DEVICE_ATTR(device_id, S_IRUGO, pod_get_device_id, line6_nop_write); static DEVICE_ATTR(dirty, S_IRUGO, pod_get_dirty, line6_nop_write); -@@ -1153,7 +1106,6 @@ static int pod_create_files2(struct device *dev) +@@ -1153,7 +1106,6 @@ { int err; @@ -98,7 +98,7 @@ CHECK_RETURN(device_create_file(dev, &dev_attr_clip)); CHECK_RETURN(device_create_file(dev, &dev_attr_device_id)); CHECK_RETURN(device_create_file(dev, &dev_attr_dirty)); -@@ -1200,8 +1152,6 @@ static int pod_try_init(struct usb_interface *interface, +@@ -1200,8 +1152,6 @@ if ((interface == NULL) || (pod == NULL)) return -ENODEV; @@ -107,7 +107,7 @@ /* initialize wait queues: */ init_waitqueue_head(&pod->monitor_level.wait); init_waitqueue_head(&pod->routing.wait); -@@ -1300,7 +1250,6 @@ void line6_pod_disconnect(struct usb_interface *interface) +@@ -1300,7 +1250,6 @@ pod->line6. properties->device_bit, dev); @@ -115,11 +115,11 @@ device_remove_file(dev, &dev_attr_clip); device_remove_file(dev, &dev_attr_device_id); device_remove_file(dev, &dev_attr_dirty); -diff --git a/drivers/staging/line6/pod.h b/drivers/staging/line6/pod.h -index 47e0d1a..0f9e83d 100644 ---- a/drivers/staging/line6/pod.h -+++ b/drivers/staging/line6/pod.h -@@ -89,11 +89,6 @@ struct usb_line6_pod { +Index: linux-3.2.46/drivers/staging/line6/pod.h +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/pod.h 2013-07-26 19:28:41.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/pod.h 2013-07-26 19:29:17.000000000 +0000 +@@ -89,11 +89,6 @@ struct line6_dump_request dumpreq; /** diff -Nru linux-3.2.46/debian/patches/features/all/line6/0062-staging-line6-drop-clip-sysfs-attr.patch linux-3.2.46/debian/patches/features/all/line6/0062-staging-line6-drop-clip-sysfs-attr.patch --- linux-3.2.46/debian/patches/features/all/line6/0062-staging-line6-drop-clip-sysfs-attr.patch 2013-02-24 03:52:35.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/line6/0062-staging-line6-drop-clip-sysfs-attr.patch 2013-07-26 19:29:20.000000000 +0000 @@ -11,10 +11,10 @@ drivers/staging/line6/pod.h | 5 ----- 2 files changed, 28 deletions(-) -diff --git a/drivers/staging/line6/pod.c b/drivers/staging/line6/pod.c -index e3e2247..4abe2de 100644 ---- a/drivers/staging/line6/pod.c -+++ b/drivers/staging/line6/pod.c +Index: linux-3.2.46/drivers/staging/line6/pod.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/pod.c 2013-07-26 19:29:17.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/pod.c 2013-07-26 19:29:19.000000000 +0000 @@ -26,7 +26,6 @@ /* *INDENT-OFF* */ @@ -23,7 +23,7 @@ POD_SYSEX_SAVE = 0x24, POD_SYSEX_SYSTEM = 0x56, POD_SYSEX_SYSTEMREQ = 0x57, -@@ -311,12 +310,6 @@ void line6_pod_process_message(struct usb_line6_pod *pod) +@@ -311,12 +310,6 @@ pod_save_button_pressed(pod, buf[6], buf[7]); break; @@ -36,7 +36,7 @@ case POD_SYSEX_STORE: dev_dbg(pod->line6.ifcdev, "message %02X not yet implemented\n", -@@ -879,18 +872,6 @@ static ssize_t pod_get_device_id(struct device *dev, +@@ -879,18 +872,6 @@ } /* @@ -55,7 +55,7 @@ POD startup procedure. This is a sequence of functions with special requirements (e.g., must not run immediately after initialization, must not run in interrupt -@@ -991,7 +972,6 @@ POD_GET_SYSTEM_PARAM(tuner_pitch, 1); +@@ -991,7 +972,6 @@ #undef GET_SYSTEM_PARAM /* POD special files: */ @@ -63,7 +63,7 @@ static DEVICE_ATTR(device_id, S_IRUGO, pod_get_device_id, line6_nop_write); static DEVICE_ATTR(dirty, S_IRUGO, pod_get_dirty, line6_nop_write); static DEVICE_ATTR(dump, S_IWUSR | S_IRUGO, pod_get_dump, pod_set_dump); -@@ -1106,7 +1086,6 @@ static int pod_create_files2(struct device *dev) +@@ -1106,7 +1086,6 @@ { int err; @@ -71,7 +71,7 @@ CHECK_RETURN(device_create_file(dev, &dev_attr_device_id)); CHECK_RETURN(device_create_file(dev, &dev_attr_dirty)); CHECK_RETURN(device_create_file(dev, &dev_attr_dump)); -@@ -1159,7 +1138,6 @@ static int pod_try_init(struct usb_interface *interface, +@@ -1159,7 +1138,6 @@ init_waitqueue_head(&pod->tuner_freq.wait); init_waitqueue_head(&pod->tuner_note.wait); init_waitqueue_head(&pod->tuner_pitch.wait); @@ -79,7 +79,7 @@ memset(pod->param_dirty, 0xff, sizeof(pod->param_dirty)); -@@ -1250,7 +1228,6 @@ void line6_pod_disconnect(struct usb_interface *interface) +@@ -1250,7 +1228,6 @@ pod->line6. properties->device_bit, dev); @@ -87,11 +87,11 @@ device_remove_file(dev, &dev_attr_device_id); device_remove_file(dev, &dev_attr_dirty); device_remove_file(dev, &dev_attr_dump); -diff --git a/drivers/staging/line6/pod.h b/drivers/staging/line6/pod.h -index 0f9e83d..fa247b8 100644 ---- a/drivers/staging/line6/pod.h -+++ b/drivers/staging/line6/pod.h -@@ -133,11 +133,6 @@ struct usb_line6_pod { +Index: linux-3.2.46/drivers/staging/line6/pod.h +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/pod.h 2013-07-26 19:29:17.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/pod.h 2013-07-26 19:29:19.000000000 +0000 +@@ -133,11 +133,6 @@ struct ValueWait routing; /** diff -Nru linux-3.2.46/debian/patches/features/all/line6/0063-staging-line6-drop-unused-param_dirty-bitmap.patch linux-3.2.46/debian/patches/features/all/line6/0063-staging-line6-drop-unused-param_dirty-bitmap.patch --- linux-3.2.46/debian/patches/features/all/line6/0063-staging-line6-drop-unused-param_dirty-bitmap.patch 2013-02-24 03:52:35.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/line6/0063-staging-line6-drop-unused-param_dirty-bitmap.patch 2013-07-26 19:29:21.000000000 +0000 @@ -15,11 +15,11 @@ drivers/staging/line6/pod.h | 5 ----- 2 files changed, 21 deletions(-) -diff --git a/drivers/staging/line6/pod.c b/drivers/staging/line6/pod.c -index 4abe2de..8fdbe9f 100644 ---- a/drivers/staging/line6/pod.c -+++ b/drivers/staging/line6/pod.c -@@ -130,17 +130,6 @@ static void pod_startup2(unsigned long data); +Index: linux-3.2.46/drivers/staging/line6/pod.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/pod.c 2013-07-26 19:29:19.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/pod.c 2013-07-26 19:29:20.000000000 +0000 +@@ -130,17 +130,6 @@ static void pod_startup3(struct usb_line6_pod *pod); static void pod_startup4(struct usb_line6_pod *pod); @@ -37,7 +37,7 @@ static char *pod_alloc_sysex_buffer(struct usb_line6_pod *pod, int code, int size) { -@@ -163,7 +152,6 @@ static void pod_dump(struct usb_line6_pod *pod, const unsigned char *data) +@@ -163,7 +152,6 @@ memcpy(sysex + SYSEX_DATA_OFS + 1, data, sizeof(pod->prog_data)); line6_send_sysex_message(&pod->line6, sysex, size); memcpy(&pod->prog_data, data, sizeof(pod->prog_data)); @@ -45,7 +45,7 @@ kfree(sysex); } -@@ -173,7 +161,6 @@ static void pod_dump(struct usb_line6_pod *pod, const unsigned char *data) +@@ -173,7 +161,6 @@ static void pod_store_parameter(struct usb_line6_pod *pod, int param, int value) { pod->prog_data.control[param] = value; @@ -53,7 +53,7 @@ pod->dirty = 1; } -@@ -239,7 +226,6 @@ void line6_pod_process_message(struct usb_line6_pod *pod) +@@ -239,7 +226,6 @@ case LINE6_DUMP_CURRENT: memcpy(&pod->prog_data, buf + 7, sizeof(pod->prog_data)); @@ -61,7 +61,7 @@ break; case POD_DUMP_MEMORY: -@@ -1139,8 +1125,6 @@ static int pod_try_init(struct usb_interface *interface, +@@ -1139,8 +1125,6 @@ init_waitqueue_head(&pod->tuner_note.wait); init_waitqueue_head(&pod->tuner_pitch.wait); @@ -70,11 +70,11 @@ /* initialize USB buffers: */ err = line6_dumpreq_init(&pod->dumpreq, pod_request_channel, sizeof(pod_request_channel)); -diff --git a/drivers/staging/line6/pod.h b/drivers/staging/line6/pod.h -index fa247b8..dd6c318 100644 ---- a/drivers/staging/line6/pod.h -+++ b/drivers/staging/line6/pod.h -@@ -148,11 +148,6 @@ struct usb_line6_pod { +Index: linux-3.2.46/drivers/staging/line6/pod.h +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/pod.h 2013-07-26 19:29:19.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/pod.h 2013-07-26 19:29:20.000000000 +0000 +@@ -148,11 +148,6 @@ int startup_progress; /** diff -Nru linux-3.2.46/debian/patches/features/all/line6/0064-staging-line6-drop-dirty-sysfs-attr.patch linux-3.2.46/debian/patches/features/all/line6/0064-staging-line6-drop-dirty-sysfs-attr.patch --- linux-3.2.46/debian/patches/features/all/line6/0064-staging-line6-drop-dirty-sysfs-attr.patch 2013-02-24 03:52:35.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/line6/0064-staging-line6-drop-dirty-sysfs-attr.patch 2013-07-26 19:29:22.000000000 +0000 @@ -11,11 +11,11 @@ drivers/staging/line6/pod.h | 5 ----- 2 files changed, 1 insertion(+), 25 deletions(-) -diff --git a/drivers/staging/line6/pod.c b/drivers/staging/line6/pod.c -index 8fdbe9f..7c76b65 100644 ---- a/drivers/staging/line6/pod.c -+++ b/drivers/staging/line6/pod.c -@@ -156,12 +156,11 @@ static void pod_dump(struct usb_line6_pod *pod, const unsigned char *data) +Index: linux-3.2.46/drivers/staging/line6/pod.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/pod.c 2013-07-26 19:29:20.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/pod.c 2013-07-26 19:29:21.000000000 +0000 +@@ -156,12 +156,11 @@ } /* @@ -29,7 +29,7 @@ } /* -@@ -170,7 +169,6 @@ static void pod_store_parameter(struct usb_line6_pod *pod, int param, int value) +@@ -170,7 +169,6 @@ static void pod_save_button_pressed(struct usb_line6_pod *pod, int type, int index) { @@ -37,7 +37,7 @@ set_bit(POD_SAVE_PRESSED, &pod->atomic_flags); } -@@ -209,7 +207,6 @@ void line6_pod_process_message(struct usb_line6_pod *pod) +@@ -209,7 +207,6 @@ case LINE6_PROGRAM_CHANGE | LINE6_CHANNEL_DEVICE: case LINE6_PROGRAM_CHANGE | LINE6_CHANNEL_HOST: @@ -45,7 +45,7 @@ set_bit(POD_CHANNEL_DIRTY, &pod->atomic_flags); line6_dump_request_async(&pod->dumpreq, &pod->line6, 0, LINE6_DUMP_CURRENT); -@@ -778,19 +775,6 @@ static ssize_t pod_set_retrieve_amp_setup(struct device *dev, +@@ -778,19 +775,6 @@ } /* @@ -65,7 +65,7 @@ "read" request on "midi_postprocess" special file. */ static ssize_t pod_get_midi_postprocess(struct device *dev, -@@ -959,7 +943,6 @@ POD_GET_SYSTEM_PARAM(tuner_pitch, 1); +@@ -959,7 +943,6 @@ /* POD special files: */ static DEVICE_ATTR(device_id, S_IRUGO, pod_get_device_id, line6_nop_write); @@ -73,7 +73,7 @@ static DEVICE_ATTR(dump, S_IWUSR | S_IRUGO, pod_get_dump, pod_set_dump); static DEVICE_ATTR(dump_buf, S_IWUSR | S_IRUGO, pod_get_dump_buf, pod_set_dump_buf); -@@ -1073,7 +1056,6 @@ static int pod_create_files2(struct device *dev) +@@ -1073,7 +1056,6 @@ int err; CHECK_RETURN(device_create_file(dev, &dev_attr_device_id)); @@ -81,7 +81,7 @@ CHECK_RETURN(device_create_file(dev, &dev_attr_dump)); CHECK_RETURN(device_create_file(dev, &dev_attr_dump_buf)); CHECK_RETURN(device_create_file(dev, &dev_attr_finish)); -@@ -1213,7 +1195,6 @@ void line6_pod_disconnect(struct usb_interface *interface) +@@ -1213,7 +1195,6 @@ properties->device_bit, dev); device_remove_file(dev, &dev_attr_device_id); @@ -89,11 +89,11 @@ device_remove_file(dev, &dev_attr_dump); device_remove_file(dev, &dev_attr_dump_buf); device_remove_file(dev, &dev_attr_finish); -diff --git a/drivers/staging/line6/pod.h b/drivers/staging/line6/pod.h -index dd6c318..b3bf243 100644 ---- a/drivers/staging/line6/pod.h -+++ b/drivers/staging/line6/pod.h -@@ -168,11 +168,6 @@ struct usb_line6_pod { +Index: linux-3.2.46/drivers/staging/line6/pod.h +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/pod.h 2013-07-26 19:29:20.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/pod.h 2013-07-26 19:29:21.000000000 +0000 +@@ -168,11 +168,6 @@ int device_id; /** diff -Nru linux-3.2.46/debian/patches/features/all/line6/0065-staging-line6-drop-dump-sysfs-attr.patch linux-3.2.46/debian/patches/features/all/line6/0065-staging-line6-drop-dump-sysfs-attr.patch --- linux-3.2.46/debian/patches/features/all/line6/0065-staging-line6-drop-dump-sysfs-attr.patch 2013-02-24 03:52:35.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/line6/0065-staging-line6-drop-dump-sysfs-attr.patch 2013-07-26 19:29:24.000000000 +0000 @@ -13,11 +13,11 @@ drivers/staging/line6/pod.c | 60 +++---------------------------------------- 1 file changed, 3 insertions(+), 57 deletions(-) -diff --git a/drivers/staging/line6/pod.c b/drivers/staging/line6/pod.c -index 7c76b65..56eab0a 100644 ---- a/drivers/staging/line6/pod.c -+++ b/drivers/staging/line6/pod.c -@@ -138,24 +138,6 @@ static char *pod_alloc_sysex_buffer(struct usb_line6_pod *pod, int code, +Index: linux-3.2.46/drivers/staging/line6/pod.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/pod.c 2013-07-26 19:29:21.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/pod.c 2013-07-26 19:29:23.000000000 +0000 +@@ -138,24 +138,6 @@ } /* @@ -42,7 +42,7 @@ Store parameter value in driver memory. */ static void pod_store_parameter(struct usb_line6_pod *pod, int param, int value) -@@ -411,7 +393,9 @@ static ssize_t pod_send_store_command(struct device *dev, const char *buf, +@@ -411,7 +393,9 @@ if (!sysex) return 0; @@ -53,7 +53,7 @@ ret = pod_resolve(buf, block0, block1, sysex + SYSEX_DATA_OFS + 1); if (ret) { kfree(sysex); -@@ -513,41 +497,6 @@ static ssize_t pod_get_name_buf(struct device *dev, +@@ -513,41 +497,6 @@ } /* @@ -95,7 +95,7 @@ Identify system parameters related to the tuner. */ static bool pod_is_tuner(int code) -@@ -943,7 +892,6 @@ POD_GET_SYSTEM_PARAM(tuner_pitch, 1); +@@ -943,7 +892,6 @@ /* POD special files: */ static DEVICE_ATTR(device_id, S_IRUGO, pod_get_device_id, line6_nop_write); @@ -103,7 +103,7 @@ static DEVICE_ATTR(dump_buf, S_IWUSR | S_IRUGO, pod_get_dump_buf, pod_set_dump_buf); static DEVICE_ATTR(finish, S_IWUSR, line6_nop_read, pod_set_finish); -@@ -1056,7 +1004,6 @@ static int pod_create_files2(struct device *dev) +@@ -1056,7 +1004,6 @@ int err; CHECK_RETURN(device_create_file(dev, &dev_attr_device_id)); @@ -111,7 +111,7 @@ CHECK_RETURN(device_create_file(dev, &dev_attr_dump_buf)); CHECK_RETURN(device_create_file(dev, &dev_attr_finish)); CHECK_RETURN(device_create_file(dev, &dev_attr_firmware_version)); -@@ -1195,7 +1142,6 @@ void line6_pod_disconnect(struct usb_interface *interface) +@@ -1195,7 +1142,6 @@ properties->device_bit, dev); device_remove_file(dev, &dev_attr_device_id); diff -Nru linux-3.2.46/debian/patches/features/all/line6/0066-staging-line6-drop-dump_buf-sysfs-attr.patch linux-3.2.46/debian/patches/features/all/line6/0066-staging-line6-drop-dump_buf-sysfs-attr.patch --- linux-3.2.46/debian/patches/features/all/line6/0066-staging-line6-drop-dump_buf-sysfs-attr.patch 2013-02-24 03:52:35.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/line6/0066-staging-line6-drop-dump_buf-sysfs-attr.patch 2013-07-26 19:29:25.000000000 +0000 @@ -10,11 +10,11 @@ drivers/staging/line6/pod.c | 40 ---------------------------------------- 1 file changed, 40 deletions(-) -diff --git a/drivers/staging/line6/pod.c b/drivers/staging/line6/pod.c -index 56eab0a..c1eb145 100644 ---- a/drivers/staging/line6/pod.c -+++ b/drivers/staging/line6/pod.c -@@ -610,42 +610,6 @@ static ssize_t pod_set_system_param_string(struct usb_line6_pod *pod, +Index: linux-3.2.46/drivers/staging/line6/pod.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/pod.c 2013-07-26 19:29:23.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/pod.c 2013-07-26 19:29:24.000000000 +0000 +@@ -610,42 +610,6 @@ } /* @@ -57,7 +57,7 @@ "write" request on "finish" special file. */ static ssize_t pod_set_finish(struct device *dev, -@@ -892,8 +856,6 @@ POD_GET_SYSTEM_PARAM(tuner_pitch, 1); +@@ -892,8 +856,6 @@ /* POD special files: */ static DEVICE_ATTR(device_id, S_IRUGO, pod_get_device_id, line6_nop_write); @@ -66,7 +66,7 @@ static DEVICE_ATTR(finish, S_IWUSR, line6_nop_read, pod_set_finish); static DEVICE_ATTR(firmware_version, S_IRUGO, pod_get_firmware_version, line6_nop_write); -@@ -1004,7 +966,6 @@ static int pod_create_files2(struct device *dev) +@@ -1004,7 +966,6 @@ int err; CHECK_RETURN(device_create_file(dev, &dev_attr_device_id)); @@ -74,7 +74,7 @@ CHECK_RETURN(device_create_file(dev, &dev_attr_finish)); CHECK_RETURN(device_create_file(dev, &dev_attr_firmware_version)); CHECK_RETURN(device_create_file(dev, &dev_attr_midi_postprocess)); -@@ -1142,7 +1103,6 @@ void line6_pod_disconnect(struct usb_interface *interface) +@@ -1142,7 +1103,6 @@ properties->device_bit, dev); device_remove_file(dev, &dev_attr_device_id); diff -Nru linux-3.2.46/debian/patches/features/all/line6/0067-staging-line6-drop-monitor_level-sysfs-attr.patch linux-3.2.46/debian/patches/features/all/line6/0067-staging-line6-drop-monitor_level-sysfs-attr.patch --- linux-3.2.46/debian/patches/features/all/line6/0067-staging-line6-drop-monitor_level-sysfs-attr.patch 2013-02-24 03:52:35.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/line6/0067-staging-line6-drop-monitor_level-sysfs-attr.patch 2013-07-26 19:29:26.000000000 +0000 @@ -15,11 +15,11 @@ drivers/staging/line6/pod.c | 12 ++++-------- 1 file changed, 4 insertions(+), 8 deletions(-) -diff --git a/drivers/staging/line6/pod.c b/drivers/staging/line6/pod.c -index c1eb145..5a941fa 100644 ---- a/drivers/staging/line6/pod.c -+++ b/drivers/staging/line6/pod.c -@@ -244,8 +244,10 @@ void line6_pod_process_message(struct usb_line6_pod *pod) +Index: linux-3.2.46/drivers/staging/line6/pod.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/pod.c 2013-07-26 19:29:24.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/pod.c 2013-07-26 19:29:25.000000000 +0000 +@@ -244,8 +244,10 @@ break; switch (buf[6]) { @@ -32,7 +32,7 @@ PROCESS_SYSTEM_PARAM(routing); PROCESS_SYSTEM_PARAM (tuner_mute); -@@ -844,7 +846,6 @@ static ssize_t pod_set_ ## code(struct device *dev, \ +@@ -844,7 +846,6 @@ return pod_set_system_param_string(pod, buf, count, POD_ ## code, mask); \ } @@ -40,7 +40,7 @@ POD_GET_SET_SYSTEM_PARAM(routing, 0x0003, 0); POD_GET_SET_SYSTEM_PARAM(tuner_mute, 0x0001, 0); POD_GET_SET_SYSTEM_PARAM(tuner_freq, 0xffff, 0); -@@ -861,8 +862,6 @@ static DEVICE_ATTR(firmware_version, S_IRUGO, pod_get_firmware_version, +@@ -861,8 +862,6 @@ line6_nop_write); static DEVICE_ATTR(midi_postprocess, S_IWUSR | S_IRUGO, pod_get_midi_postprocess, pod_set_midi_postprocess); @@ -49,7 +49,7 @@ static DEVICE_ATTR(name, S_IRUGO, pod_get_name, line6_nop_write); static DEVICE_ATTR(name_buf, S_IRUGO, pod_get_name_buf, line6_nop_write); static DEVICE_ATTR(retrieve_amp_setup, S_IWUSR, line6_nop_read, -@@ -969,7 +968,6 @@ static int pod_create_files2(struct device *dev) +@@ -969,7 +968,6 @@ CHECK_RETURN(device_create_file(dev, &dev_attr_finish)); CHECK_RETURN(device_create_file(dev, &dev_attr_firmware_version)); CHECK_RETURN(device_create_file(dev, &dev_attr_midi_postprocess)); @@ -57,7 +57,7 @@ CHECK_RETURN(device_create_file(dev, &dev_attr_name)); CHECK_RETURN(device_create_file(dev, &dev_attr_name_buf)); CHECK_RETURN(device_create_file(dev, &dev_attr_retrieve_amp_setup)); -@@ -1008,7 +1006,6 @@ static int pod_try_init(struct usb_interface *interface, +@@ -1008,7 +1006,6 @@ return -ENODEV; /* initialize wait queues: */ @@ -65,7 +65,7 @@ init_waitqueue_head(&pod->routing.wait); init_waitqueue_head(&pod->tuner_mute.wait); init_waitqueue_head(&pod->tuner_freq.wait); -@@ -1106,7 +1103,6 @@ void line6_pod_disconnect(struct usb_interface *interface) +@@ -1106,7 +1103,6 @@ device_remove_file(dev, &dev_attr_finish); device_remove_file(dev, &dev_attr_firmware_version); device_remove_file(dev, &dev_attr_midi_postprocess); diff -Nru linux-3.2.46/debian/patches/features/all/line6/0068-staging-line6-change-monitor_level-type-ValueWait-in.patch linux-3.2.46/debian/patches/features/all/line6/0068-staging-line6-change-monitor_level-type-ValueWait-in.patch --- linux-3.2.46/debian/patches/features/all/line6/0068-staging-line6-change-monitor_level-type-ValueWait-in.patch 2013-02-24 03:52:35.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/line6/0068-staging-line6-change-monitor_level-type-ValueWait-in.patch 2013-07-26 19:29:28.000000000 +0000 @@ -15,11 +15,11 @@ drivers/staging/line6/pod.h | 2 +- 2 files changed, 6 insertions(+), 6 deletions(-) -diff --git a/drivers/staging/line6/pod.c b/drivers/staging/line6/pod.c -index 5a941fa..165c7ad 100644 ---- a/drivers/staging/line6/pod.c -+++ b/drivers/staging/line6/pod.c -@@ -245,7 +245,7 @@ void line6_pod_process_message(struct usb_line6_pod *pod) +Index: linux-3.2.46/drivers/staging/line6/pod.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/pod.c 2013-07-26 19:29:25.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/pod.c 2013-07-26 19:29:27.000000000 +0000 +@@ -245,7 +245,7 @@ switch (buf[6]) { case POD_monitor_level: @@ -28,7 +28,7 @@ break; PROCESS_SYSTEM_PARAM(routing); -@@ -908,7 +908,7 @@ static int snd_pod_control_monitor_get(struct snd_kcontrol *kcontrol, +@@ -908,7 +908,7 @@ { struct snd_line6_pcm *line6pcm = snd_kcontrol_chip(kcontrol); struct usb_line6_pod *pod = (struct usb_line6_pod *)line6pcm->line6; @@ -37,7 +37,7 @@ return 0; } -@@ -919,10 +919,10 @@ static int snd_pod_control_monitor_put(struct snd_kcontrol *kcontrol, +@@ -919,10 +919,10 @@ struct snd_line6_pcm *line6pcm = snd_kcontrol_chip(kcontrol); struct usb_line6_pod *pod = (struct usb_line6_pod *)line6pcm->line6; @@ -50,7 +50,7 @@ pod_set_system_param_int(pod, ucontrol->value.integer.value[0], POD_monitor_level); return 1; -@@ -1053,7 +1053,7 @@ static int pod_try_init(struct usb_interface *interface, +@@ -1053,7 +1053,7 @@ */ if (pod->line6.properties->capabilities & LINE6_BIT_CONTROL) { @@ -59,11 +59,11 @@ /* initiate startup procedure: */ pod_startup1(pod); -diff --git a/drivers/staging/line6/pod.h b/drivers/staging/line6/pod.h -index b3bf243..d5bbd2f 100644 ---- a/drivers/staging/line6/pod.h -+++ b/drivers/staging/line6/pod.h -@@ -121,7 +121,7 @@ struct usb_line6_pod { +Index: linux-3.2.46/drivers/staging/line6/pod.h +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/pod.h 2013-07-26 19:29:21.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/pod.h 2013-07-26 19:29:27.000000000 +0000 +@@ -121,7 +121,7 @@ /** Instrument monitor level. */ diff -Nru linux-3.2.46/debian/patches/features/all/line6/0069-staging-line6-drop-name-sysfs-attr.patch linux-3.2.46/debian/patches/features/all/line6/0069-staging-line6-drop-name-sysfs-attr.patch --- linux-3.2.46/debian/patches/features/all/line6/0069-staging-line6-drop-name-sysfs-attr.patch 2013-02-24 03:52:35.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/line6/0069-staging-line6-drop-name-sysfs-attr.patch 2013-07-26 19:29:29.000000000 +0000 @@ -10,11 +10,11 @@ drivers/staging/line6/pod.c | 15 --------------- 1 file changed, 15 deletions(-) -diff --git a/drivers/staging/line6/pod.c b/drivers/staging/line6/pod.c -index 165c7ad..76525c5 100644 ---- a/drivers/staging/line6/pod.c -+++ b/drivers/staging/line6/pod.c -@@ -476,18 +476,6 @@ static ssize_t get_name_generic(struct usb_line6_pod *pod, const char *str, +Index: linux-3.2.46/drivers/staging/line6/pod.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/pod.c 2013-07-26 19:29:27.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/pod.c 2013-07-26 19:29:28.000000000 +0000 +@@ -476,18 +476,6 @@ /* "read" request on "name" special file. */ @@ -33,7 +33,7 @@ static ssize_t pod_get_name_buf(struct device *dev, struct device_attribute *attr, char *buf) { -@@ -862,7 +850,6 @@ static DEVICE_ATTR(firmware_version, S_IRUGO, pod_get_firmware_version, +@@ -862,7 +850,6 @@ line6_nop_write); static DEVICE_ATTR(midi_postprocess, S_IWUSR | S_IRUGO, pod_get_midi_postprocess, pod_set_midi_postprocess); @@ -41,7 +41,7 @@ static DEVICE_ATTR(name_buf, S_IRUGO, pod_get_name_buf, line6_nop_write); static DEVICE_ATTR(retrieve_amp_setup, S_IWUSR, line6_nop_read, pod_set_retrieve_amp_setup); -@@ -968,7 +955,6 @@ static int pod_create_files2(struct device *dev) +@@ -968,7 +955,6 @@ CHECK_RETURN(device_create_file(dev, &dev_attr_finish)); CHECK_RETURN(device_create_file(dev, &dev_attr_firmware_version)); CHECK_RETURN(device_create_file(dev, &dev_attr_midi_postprocess)); @@ -49,7 +49,7 @@ CHECK_RETURN(device_create_file(dev, &dev_attr_name_buf)); CHECK_RETURN(device_create_file(dev, &dev_attr_retrieve_amp_setup)); CHECK_RETURN(device_create_file(dev, &dev_attr_retrieve_channel)); -@@ -1103,7 +1089,6 @@ void line6_pod_disconnect(struct usb_interface *interface) +@@ -1103,7 +1089,6 @@ device_remove_file(dev, &dev_attr_finish); device_remove_file(dev, &dev_attr_firmware_version); device_remove_file(dev, &dev_attr_midi_postprocess); diff -Nru linux-3.2.46/debian/patches/features/all/line6/0070-staging-line6-drop-name_buf-sysfs-attr.patch linux-3.2.46/debian/patches/features/all/line6/0070-staging-line6-drop-name_buf-sysfs-attr.patch --- linux-3.2.46/debian/patches/features/all/line6/0070-staging-line6-drop-name_buf-sysfs-attr.patch 2013-02-24 03:52:35.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/line6/0070-staging-line6-drop-name_buf-sysfs-attr.patch 2013-07-26 19:29:30.000000000 +0000 @@ -10,11 +10,11 @@ drivers/staging/line6/pod.c | 43 ------------------------------------------- 1 file changed, 43 deletions(-) -diff --git a/drivers/staging/line6/pod.c b/drivers/staging/line6/pod.c -index 76525c5..dbf821e 100644 ---- a/drivers/staging/line6/pod.c -+++ b/drivers/staging/line6/pod.c -@@ -447,46 +447,6 @@ static ssize_t pod_send_retrieve_command(struct device *dev, const char *buf, +Index: linux-3.2.46/drivers/staging/line6/pod.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/pod.c 2013-07-26 19:29:28.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/pod.c 2013-07-26 19:29:29.000000000 +0000 +@@ -447,46 +447,6 @@ } /* @@ -61,7 +61,7 @@ Identify system parameters related to the tuner. */ static bool pod_is_tuner(int code) -@@ -850,7 +810,6 @@ static DEVICE_ATTR(firmware_version, S_IRUGO, pod_get_firmware_version, +@@ -850,7 +810,6 @@ line6_nop_write); static DEVICE_ATTR(midi_postprocess, S_IWUSR | S_IRUGO, pod_get_midi_postprocess, pod_set_midi_postprocess); @@ -69,7 +69,7 @@ static DEVICE_ATTR(retrieve_amp_setup, S_IWUSR, line6_nop_read, pod_set_retrieve_amp_setup); static DEVICE_ATTR(retrieve_channel, S_IWUSR, line6_nop_read, -@@ -955,7 +914,6 @@ static int pod_create_files2(struct device *dev) +@@ -955,7 +914,6 @@ CHECK_RETURN(device_create_file(dev, &dev_attr_finish)); CHECK_RETURN(device_create_file(dev, &dev_attr_firmware_version)); CHECK_RETURN(device_create_file(dev, &dev_attr_midi_postprocess)); @@ -77,7 +77,7 @@ CHECK_RETURN(device_create_file(dev, &dev_attr_retrieve_amp_setup)); CHECK_RETURN(device_create_file(dev, &dev_attr_retrieve_channel)); CHECK_RETURN(device_create_file(dev, &dev_attr_retrieve_effects_setup)); -@@ -1089,7 +1047,6 @@ void line6_pod_disconnect(struct usb_interface *interface) +@@ -1089,7 +1047,6 @@ device_remove_file(dev, &dev_attr_finish); device_remove_file(dev, &dev_attr_firmware_version); device_remove_file(dev, &dev_attr_midi_postprocess); diff -Nru linux-3.2.46/debian/patches/features/all/line6/0071-staging-line6-drop-retrieve_amp_setup-sysfs-attr.patch linux-3.2.46/debian/patches/features/all/line6/0071-staging-line6-drop-retrieve_amp_setup-sysfs-attr.patch --- linux-3.2.46/debian/patches/features/all/line6/0071-staging-line6-drop-retrieve_amp_setup-sysfs-attr.patch 2013-02-24 03:52:35.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/line6/0071-staging-line6-drop-retrieve_amp_setup-sysfs-attr.patch 2013-07-26 19:29:32.000000000 +0000 @@ -10,11 +10,11 @@ drivers/staging/line6/pod.c | 14 -------------- 1 file changed, 14 deletions(-) -diff --git a/drivers/staging/line6/pod.c b/drivers/staging/line6/pod.c -index dbf821e..6d6cd5a 100644 ---- a/drivers/staging/line6/pod.c -+++ b/drivers/staging/line6/pod.c -@@ -628,16 +628,6 @@ static ssize_t pod_set_retrieve_effects_setup(struct device *dev, +Index: linux-3.2.46/drivers/staging/line6/pod.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/pod.c 2013-07-26 19:29:29.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/pod.c 2013-07-26 19:29:31.000000000 +0000 +@@ -628,16 +628,6 @@ } /* @@ -31,7 +31,7 @@ "read" request on "midi_postprocess" special file. */ static ssize_t pod_get_midi_postprocess(struct device *dev, -@@ -810,8 +800,6 @@ static DEVICE_ATTR(firmware_version, S_IRUGO, pod_get_firmware_version, +@@ -810,8 +800,6 @@ line6_nop_write); static DEVICE_ATTR(midi_postprocess, S_IWUSR | S_IRUGO, pod_get_midi_postprocess, pod_set_midi_postprocess); @@ -40,7 +40,7 @@ static DEVICE_ATTR(retrieve_channel, S_IWUSR, line6_nop_read, pod_set_retrieve_channel); static DEVICE_ATTR(retrieve_effects_setup, S_IWUSR, line6_nop_read, -@@ -914,7 +902,6 @@ static int pod_create_files2(struct device *dev) +@@ -914,7 +902,6 @@ CHECK_RETURN(device_create_file(dev, &dev_attr_finish)); CHECK_RETURN(device_create_file(dev, &dev_attr_firmware_version)); CHECK_RETURN(device_create_file(dev, &dev_attr_midi_postprocess)); @@ -48,7 +48,7 @@ CHECK_RETURN(device_create_file(dev, &dev_attr_retrieve_channel)); CHECK_RETURN(device_create_file(dev, &dev_attr_retrieve_effects_setup)); CHECK_RETURN(device_create_file(dev, &dev_attr_routing)); -@@ -1047,7 +1034,6 @@ void line6_pod_disconnect(struct usb_interface *interface) +@@ -1047,7 +1034,6 @@ device_remove_file(dev, &dev_attr_finish); device_remove_file(dev, &dev_attr_firmware_version); device_remove_file(dev, &dev_attr_midi_postprocess); diff -Nru linux-3.2.46/debian/patches/features/all/line6/0072-staging-line6-drop-retrieve_channel-sysfs-attr.patch linux-3.2.46/debian/patches/features/all/line6/0072-staging-line6-drop-retrieve_channel-sysfs-attr.patch --- linux-3.2.46/debian/patches/features/all/line6/0072-staging-line6-drop-retrieve_channel-sysfs-attr.patch 2013-02-24 03:52:35.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/line6/0072-staging-line6-drop-retrieve_channel-sysfs-attr.patch 2013-07-26 19:29:33.000000000 +0000 @@ -10,11 +10,11 @@ drivers/staging/line6/pod.c | 14 -------------- 1 file changed, 14 deletions(-) -diff --git a/drivers/staging/line6/pod.c b/drivers/staging/line6/pod.c -index 6d6cd5a..bc65fc7 100644 ---- a/drivers/staging/line6/pod.c -+++ b/drivers/staging/line6/pod.c -@@ -608,16 +608,6 @@ static ssize_t pod_set_store_amp_setup(struct device *dev, +Index: linux-3.2.46/drivers/staging/line6/pod.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/pod.c 2013-07-26 19:29:31.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/pod.c 2013-07-26 19:29:32.000000000 +0000 +@@ -608,16 +608,6 @@ } /* @@ -31,7 +31,7 @@ "write" request on "retrieve_effects_setup" special file. */ static ssize_t pod_set_retrieve_effects_setup(struct device *dev, -@@ -800,8 +790,6 @@ static DEVICE_ATTR(firmware_version, S_IRUGO, pod_get_firmware_version, +@@ -800,8 +790,6 @@ line6_nop_write); static DEVICE_ATTR(midi_postprocess, S_IWUSR | S_IRUGO, pod_get_midi_postprocess, pod_set_midi_postprocess); @@ -40,7 +40,7 @@ static DEVICE_ATTR(retrieve_effects_setup, S_IWUSR, line6_nop_read, pod_set_retrieve_effects_setup); static DEVICE_ATTR(routing, S_IWUSR | S_IRUGO, pod_get_routing, -@@ -902,7 +890,6 @@ static int pod_create_files2(struct device *dev) +@@ -902,7 +890,6 @@ CHECK_RETURN(device_create_file(dev, &dev_attr_finish)); CHECK_RETURN(device_create_file(dev, &dev_attr_firmware_version)); CHECK_RETURN(device_create_file(dev, &dev_attr_midi_postprocess)); @@ -48,7 +48,7 @@ CHECK_RETURN(device_create_file(dev, &dev_attr_retrieve_effects_setup)); CHECK_RETURN(device_create_file(dev, &dev_attr_routing)); CHECK_RETURN(device_create_file(dev, &dev_attr_serial_number)); -@@ -1034,7 +1021,6 @@ void line6_pod_disconnect(struct usb_interface *interface) +@@ -1034,7 +1021,6 @@ device_remove_file(dev, &dev_attr_finish); device_remove_file(dev, &dev_attr_firmware_version); device_remove_file(dev, &dev_attr_midi_postprocess); diff -Nru linux-3.2.46/debian/patches/features/all/line6/0073-staging-line6-drop-retrieve_effects_setup-sysfs-attr.patch linux-3.2.46/debian/patches/features/all/line6/0073-staging-line6-drop-retrieve_effects_setup-sysfs-attr.patch --- linux-3.2.46/debian/patches/features/all/line6/0073-staging-line6-drop-retrieve_effects_setup-sysfs-attr.patch 2013-02-24 03:52:35.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/line6/0073-staging-line6-drop-retrieve_effects_setup-sysfs-attr.patch 2013-07-26 19:29:34.000000000 +0000 @@ -10,11 +10,11 @@ drivers/staging/line6/pod.c | 48 ------------------------------------------- 1 file changed, 48 deletions(-) -diff --git a/drivers/staging/line6/pod.c b/drivers/staging/line6/pod.c -index bc65fc7..95769c5 100644 ---- a/drivers/staging/line6/pod.c -+++ b/drivers/staging/line6/pod.c -@@ -381,39 +381,6 @@ static int pod_resolve(const char *buf, short block0, short block1, +Index: linux-3.2.46/drivers/staging/line6/pod.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/pod.c 2013-07-26 19:29:32.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/pod.c 2013-07-26 19:29:33.000000000 +0000 +@@ -381,39 +381,6 @@ } /* @@ -54,7 +54,7 @@ Send command to retrieve channel/effects setup/amp setup to PODxt Pro. */ static ssize_t pod_send_retrieve_command(struct device *dev, const char *buf, -@@ -608,16 +575,6 @@ static ssize_t pod_set_store_amp_setup(struct device *dev, +@@ -608,16 +575,6 @@ } /* @@ -71,7 +71,7 @@ "read" request on "midi_postprocess" special file. */ static ssize_t pod_get_midi_postprocess(struct device *dev, -@@ -790,8 +747,6 @@ static DEVICE_ATTR(firmware_version, S_IRUGO, pod_get_firmware_version, +@@ -790,8 +747,6 @@ line6_nop_write); static DEVICE_ATTR(midi_postprocess, S_IWUSR | S_IRUGO, pod_get_midi_postprocess, pod_set_midi_postprocess); @@ -80,7 +80,7 @@ static DEVICE_ATTR(routing, S_IWUSR | S_IRUGO, pod_get_routing, pod_set_routing); static DEVICE_ATTR(serial_number, S_IRUGO, pod_get_serial_number, -@@ -890,7 +845,6 @@ static int pod_create_files2(struct device *dev) +@@ -890,7 +845,6 @@ CHECK_RETURN(device_create_file(dev, &dev_attr_finish)); CHECK_RETURN(device_create_file(dev, &dev_attr_firmware_version)); CHECK_RETURN(device_create_file(dev, &dev_attr_midi_postprocess)); @@ -88,7 +88,7 @@ CHECK_RETURN(device_create_file(dev, &dev_attr_routing)); CHECK_RETURN(device_create_file(dev, &dev_attr_serial_number)); CHECK_RETURN(device_create_file(dev, &dev_attr_store_amp_setup)); -@@ -1021,8 +975,6 @@ void line6_pod_disconnect(struct usb_interface *interface) +@@ -1021,8 +975,6 @@ device_remove_file(dev, &dev_attr_finish); device_remove_file(dev, &dev_attr_firmware_version); device_remove_file(dev, &dev_attr_midi_postprocess); diff -Nru linux-3.2.46/debian/patches/features/all/line6/0074-staging-line6-drop-store_amp_setup-sysfs-attr.patch linux-3.2.46/debian/patches/features/all/line6/0074-staging-line6-drop-store_amp_setup-sysfs-attr.patch --- linux-3.2.46/debian/patches/features/all/line6/0074-staging-line6-drop-store_amp_setup-sysfs-attr.patch 2013-02-24 03:52:35.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/line6/0074-staging-line6-drop-store_amp_setup-sysfs-attr.patch 2013-07-26 19:29:36.000000000 +0000 @@ -10,11 +10,11 @@ drivers/staging/line6/pod.c | 14 -------------- 1 file changed, 14 deletions(-) -diff --git a/drivers/staging/line6/pod.c b/drivers/staging/line6/pod.c -index 95769c5..deafee9 100644 ---- a/drivers/staging/line6/pod.c -+++ b/drivers/staging/line6/pod.c -@@ -565,16 +565,6 @@ static ssize_t pod_set_store_effects_setup(struct device *dev, +Index: linux-3.2.46/drivers/staging/line6/pod.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/pod.c 2013-07-26 19:29:33.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/pod.c 2013-07-26 19:29:35.000000000 +0000 +@@ -565,16 +565,6 @@ } /* @@ -31,7 +31,7 @@ "read" request on "midi_postprocess" special file. */ static ssize_t pod_get_midi_postprocess(struct device *dev, -@@ -751,8 +741,6 @@ static DEVICE_ATTR(routing, S_IWUSR | S_IRUGO, pod_get_routing, +@@ -751,8 +741,6 @@ pod_set_routing); static DEVICE_ATTR(serial_number, S_IRUGO, pod_get_serial_number, line6_nop_write); @@ -40,7 +40,7 @@ static DEVICE_ATTR(store_channel, S_IWUSR, line6_nop_read, pod_set_store_channel); static DEVICE_ATTR(store_effects_setup, S_IWUSR, line6_nop_read, -@@ -847,7 +835,6 @@ static int pod_create_files2(struct device *dev) +@@ -847,7 +835,6 @@ CHECK_RETURN(device_create_file(dev, &dev_attr_midi_postprocess)); CHECK_RETURN(device_create_file(dev, &dev_attr_routing)); CHECK_RETURN(device_create_file(dev, &dev_attr_serial_number)); @@ -48,7 +48,7 @@ CHECK_RETURN(device_create_file(dev, &dev_attr_store_channel)); CHECK_RETURN(device_create_file(dev, &dev_attr_store_effects_setup)); CHECK_RETURN(device_create_file(dev, &dev_attr_tuner_freq)); -@@ -977,7 +964,6 @@ void line6_pod_disconnect(struct usb_interface *interface) +@@ -977,7 +964,6 @@ device_remove_file(dev, &dev_attr_midi_postprocess); device_remove_file(dev, &dev_attr_routing); device_remove_file(dev, &dev_attr_serial_number); diff -Nru linux-3.2.46/debian/patches/features/all/line6/0075-staging-line6-drop-store_channel-sysfs-attr.patch linux-3.2.46/debian/patches/features/all/line6/0075-staging-line6-drop-store_channel-sysfs-attr.patch --- linux-3.2.46/debian/patches/features/all/line6/0075-staging-line6-drop-store_channel-sysfs-attr.patch 2013-02-24 03:52:35.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/line6/0075-staging-line6-drop-store_channel-sysfs-attr.patch 2013-07-26 19:29:37.000000000 +0000 @@ -10,11 +10,11 @@ drivers/staging/line6/pod.c | 14 -------------- 1 file changed, 14 deletions(-) -diff --git a/drivers/staging/line6/pod.c b/drivers/staging/line6/pod.c -index deafee9..abf7ebe 100644 ---- a/drivers/staging/line6/pod.c -+++ b/drivers/staging/line6/pod.c -@@ -545,16 +545,6 @@ static ssize_t pod_set_finish(struct device *dev, +Index: linux-3.2.46/drivers/staging/line6/pod.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/pod.c 2013-07-26 19:29:35.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/pod.c 2013-07-26 19:29:36.000000000 +0000 +@@ -545,16 +545,6 @@ } /* @@ -31,7 +31,7 @@ "write" request on "store_effects_setup" special file. */ static ssize_t pod_set_store_effects_setup(struct device *dev, -@@ -741,8 +731,6 @@ static DEVICE_ATTR(routing, S_IWUSR | S_IRUGO, pod_get_routing, +@@ -741,8 +731,6 @@ pod_set_routing); static DEVICE_ATTR(serial_number, S_IRUGO, pod_get_serial_number, line6_nop_write); @@ -40,7 +40,7 @@ static DEVICE_ATTR(store_effects_setup, S_IWUSR, line6_nop_read, pod_set_store_effects_setup); static DEVICE_ATTR(tuner_freq, S_IWUSR | S_IRUGO, pod_get_tuner_freq, -@@ -835,7 +823,6 @@ static int pod_create_files2(struct device *dev) +@@ -835,7 +823,6 @@ CHECK_RETURN(device_create_file(dev, &dev_attr_midi_postprocess)); CHECK_RETURN(device_create_file(dev, &dev_attr_routing)); CHECK_RETURN(device_create_file(dev, &dev_attr_serial_number)); @@ -48,7 +48,7 @@ CHECK_RETURN(device_create_file(dev, &dev_attr_store_effects_setup)); CHECK_RETURN(device_create_file(dev, &dev_attr_tuner_freq)); CHECK_RETURN(device_create_file(dev, &dev_attr_tuner_mute)); -@@ -964,7 +951,6 @@ void line6_pod_disconnect(struct usb_interface *interface) +@@ -964,7 +951,6 @@ device_remove_file(dev, &dev_attr_midi_postprocess); device_remove_file(dev, &dev_attr_routing); device_remove_file(dev, &dev_attr_serial_number); diff -Nru linux-3.2.46/debian/patches/features/all/line6/0076-staging-line6-drop-store_effects_setup-sysfs-attr.patch linux-3.2.46/debian/patches/features/all/line6/0076-staging-line6-drop-store_effects_setup-sysfs-attr.patch --- linux-3.2.46/debian/patches/features/all/line6/0076-staging-line6-drop-store_effects_setup-sysfs-attr.patch 2013-02-24 03:52:35.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/line6/0076-staging-line6-drop-store_effects_setup-sysfs-attr.patch 2013-07-26 19:29:38.000000000 +0000 @@ -10,11 +10,11 @@ drivers/staging/line6/pod.c | 68 ------------------------------------------- 1 file changed, 68 deletions(-) -diff --git a/drivers/staging/line6/pod.c b/drivers/staging/line6/pod.c -index abf7ebe..949b8f7 100644 ---- a/drivers/staging/line6/pod.c -+++ b/drivers/staging/line6/pod.c -@@ -360,60 +360,6 @@ void line6_pod_transmit_parameter(struct usb_line6_pod *pod, int param, +Index: linux-3.2.46/drivers/staging/line6/pod.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/pod.c 2013-07-26 19:29:36.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/pod.c 2013-07-26 19:29:37.000000000 +0000 +@@ -360,60 +360,6 @@ } /* @@ -75,7 +75,7 @@ Identify system parameters related to the tuner. */ static bool pod_is_tuner(int code) -@@ -545,16 +491,6 @@ static ssize_t pod_set_finish(struct device *dev, +@@ -545,16 +491,6 @@ } /* @@ -92,7 +92,7 @@ "read" request on "midi_postprocess" special file. */ static ssize_t pod_get_midi_postprocess(struct device *dev, -@@ -731,8 +667,6 @@ static DEVICE_ATTR(routing, S_IWUSR | S_IRUGO, pod_get_routing, +@@ -731,8 +667,6 @@ pod_set_routing); static DEVICE_ATTR(serial_number, S_IRUGO, pod_get_serial_number, line6_nop_write); @@ -101,7 +101,7 @@ static DEVICE_ATTR(tuner_freq, S_IWUSR | S_IRUGO, pod_get_tuner_freq, pod_set_tuner_freq); static DEVICE_ATTR(tuner_mute, S_IWUSR | S_IRUGO, pod_get_tuner_mute, -@@ -823,7 +757,6 @@ static int pod_create_files2(struct device *dev) +@@ -823,7 +757,6 @@ CHECK_RETURN(device_create_file(dev, &dev_attr_midi_postprocess)); CHECK_RETURN(device_create_file(dev, &dev_attr_routing)); CHECK_RETURN(device_create_file(dev, &dev_attr_serial_number)); @@ -109,7 +109,7 @@ CHECK_RETURN(device_create_file(dev, &dev_attr_tuner_freq)); CHECK_RETURN(device_create_file(dev, &dev_attr_tuner_mute)); CHECK_RETURN(device_create_file(dev, &dev_attr_tuner_note)); -@@ -951,7 +884,6 @@ void line6_pod_disconnect(struct usb_interface *interface) +@@ -951,7 +884,6 @@ device_remove_file(dev, &dev_attr_midi_postprocess); device_remove_file(dev, &dev_attr_routing); device_remove_file(dev, &dev_attr_serial_number); diff -Nru linux-3.2.46/debian/patches/features/all/line6/0077-staging-line6-drop-routing-sysfs-attr.patch linux-3.2.46/debian/patches/features/all/line6/0077-staging-line6-drop-routing-sysfs-attr.patch --- linux-3.2.46/debian/patches/features/all/line6/0077-staging-line6-drop-routing-sysfs-attr.patch 2013-02-24 03:52:35.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/line6/0077-staging-line6-drop-routing-sysfs-attr.patch 2013-07-26 19:29:40.000000000 +0000 @@ -11,11 +11,11 @@ drivers/staging/line6/pod.h | 9 --------- 2 files changed, 17 deletions(-) -diff --git a/drivers/staging/line6/pod.c b/drivers/staging/line6/pod.c -index 949b8f7..f84a4ea 100644 ---- a/drivers/staging/line6/pod.c -+++ b/drivers/staging/line6/pod.c -@@ -40,7 +40,6 @@ enum { +Index: linux-3.2.46/drivers/staging/line6/pod.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/pod.c 2013-07-26 19:29:37.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/pod.c 2013-07-26 19:29:39.000000000 +0000 +@@ -40,7 +40,6 @@ enum { POD_monitor_level = 0x04, @@ -23,7 +23,7 @@ POD_tuner_mute = 0x13, POD_tuner_freq = 0x15, POD_tuner_note = 0x16, -@@ -248,7 +247,6 @@ void line6_pod_process_message(struct usb_line6_pod *pod) +@@ -248,7 +247,6 @@ pod->monitor_level = value; break; @@ -31,7 +31,7 @@ PROCESS_SYSTEM_PARAM (tuner_mute); PROCESS_SYSTEM_PARAM -@@ -647,7 +645,6 @@ static ssize_t pod_set_ ## code(struct device *dev, \ +@@ -647,7 +645,6 @@ return pod_set_system_param_string(pod, buf, count, POD_ ## code, mask); \ } @@ -39,7 +39,7 @@ POD_GET_SET_SYSTEM_PARAM(tuner_mute, 0x0001, 0); POD_GET_SET_SYSTEM_PARAM(tuner_freq, 0xffff, 0); POD_GET_SYSTEM_PARAM(tuner_note, 1); -@@ -663,8 +660,6 @@ static DEVICE_ATTR(firmware_version, S_IRUGO, pod_get_firmware_version, +@@ -663,8 +660,6 @@ line6_nop_write); static DEVICE_ATTR(midi_postprocess, S_IWUSR | S_IRUGO, pod_get_midi_postprocess, pod_set_midi_postprocess); @@ -48,7 +48,7 @@ static DEVICE_ATTR(serial_number, S_IRUGO, pod_get_serial_number, line6_nop_write); static DEVICE_ATTR(tuner_freq, S_IWUSR | S_IRUGO, pod_get_tuner_freq, -@@ -755,7 +750,6 @@ static int pod_create_files2(struct device *dev) +@@ -755,7 +750,6 @@ CHECK_RETURN(device_create_file(dev, &dev_attr_finish)); CHECK_RETURN(device_create_file(dev, &dev_attr_firmware_version)); CHECK_RETURN(device_create_file(dev, &dev_attr_midi_postprocess)); @@ -56,7 +56,7 @@ CHECK_RETURN(device_create_file(dev, &dev_attr_serial_number)); CHECK_RETURN(device_create_file(dev, &dev_attr_tuner_freq)); CHECK_RETURN(device_create_file(dev, &dev_attr_tuner_mute)); -@@ -785,7 +779,6 @@ static int pod_try_init(struct usb_interface *interface, +@@ -785,7 +779,6 @@ return -ENODEV; /* initialize wait queues: */ @@ -64,7 +64,7 @@ init_waitqueue_head(&pod->tuner_mute.wait); init_waitqueue_head(&pod->tuner_freq.wait); init_waitqueue_head(&pod->tuner_note.wait); -@@ -882,7 +875,6 @@ void line6_pod_disconnect(struct usb_interface *interface) +@@ -882,7 +875,6 @@ device_remove_file(dev, &dev_attr_finish); device_remove_file(dev, &dev_attr_firmware_version); device_remove_file(dev, &dev_attr_midi_postprocess); @@ -72,11 +72,11 @@ device_remove_file(dev, &dev_attr_serial_number); device_remove_file(dev, &dev_attr_tuner_freq); device_remove_file(dev, &dev_attr_tuner_mute); -diff --git a/drivers/staging/line6/pod.h b/drivers/staging/line6/pod.h -index d5bbd2f..732311a 100644 ---- a/drivers/staging/line6/pod.h -+++ b/drivers/staging/line6/pod.h -@@ -124,15 +124,6 @@ struct usb_line6_pod { +Index: linux-3.2.46/drivers/staging/line6/pod.h +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/pod.h 2013-07-26 19:29:27.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/pod.h 2013-07-26 19:29:39.000000000 +0000 +@@ -124,15 +124,6 @@ int monitor_level; /** diff -Nru linux-3.2.46/debian/patches/features/all/line6/0078-staging-line6-drop-tuner_freq-sysfs-attr.patch linux-3.2.46/debian/patches/features/all/line6/0078-staging-line6-drop-tuner_freq-sysfs-attr.patch --- linux-3.2.46/debian/patches/features/all/line6/0078-staging-line6-drop-tuner_freq-sysfs-attr.patch 2013-02-24 03:52:35.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/line6/0078-staging-line6-drop-tuner_freq-sysfs-attr.patch 2013-07-26 19:29:41.000000000 +0000 @@ -11,11 +11,11 @@ drivers/staging/line6/pod.h | 5 ----- 2 files changed, 13 deletions(-) -diff --git a/drivers/staging/line6/pod.c b/drivers/staging/line6/pod.c -index f84a4ea..3184570 100644 ---- a/drivers/staging/line6/pod.c -+++ b/drivers/staging/line6/pod.c -@@ -250,8 +250,6 @@ void line6_pod_process_message(struct usb_line6_pod *pod) +Index: linux-3.2.46/drivers/staging/line6/pod.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/pod.c 2013-07-26 19:29:39.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/pod.c 2013-07-26 19:29:40.000000000 +0000 +@@ -250,8 +250,6 @@ PROCESS_SYSTEM_PARAM (tuner_mute); PROCESS_SYSTEM_PARAM @@ -24,7 +24,7 @@ (tuner_note); PROCESS_SYSTEM_PARAM (tuner_pitch); -@@ -646,7 +644,6 @@ static ssize_t pod_set_ ## code(struct device *dev, \ +@@ -646,7 +644,6 @@ } POD_GET_SET_SYSTEM_PARAM(tuner_mute, 0x0001, 0); @@ -32,7 +32,7 @@ POD_GET_SYSTEM_PARAM(tuner_note, 1); POD_GET_SYSTEM_PARAM(tuner_pitch, 1); -@@ -662,8 +659,6 @@ static DEVICE_ATTR(midi_postprocess, S_IWUSR | S_IRUGO, +@@ -662,8 +659,6 @@ pod_get_midi_postprocess, pod_set_midi_postprocess); static DEVICE_ATTR(serial_number, S_IRUGO, pod_get_serial_number, line6_nop_write); @@ -41,7 +41,7 @@ static DEVICE_ATTR(tuner_mute, S_IWUSR | S_IRUGO, pod_get_tuner_mute, pod_set_tuner_mute); static DEVICE_ATTR(tuner_note, S_IRUGO, pod_get_tuner_note, line6_nop_write); -@@ -751,7 +746,6 @@ static int pod_create_files2(struct device *dev) +@@ -751,7 +746,6 @@ CHECK_RETURN(device_create_file(dev, &dev_attr_firmware_version)); CHECK_RETURN(device_create_file(dev, &dev_attr_midi_postprocess)); CHECK_RETURN(device_create_file(dev, &dev_attr_serial_number)); @@ -49,7 +49,7 @@ CHECK_RETURN(device_create_file(dev, &dev_attr_tuner_mute)); CHECK_RETURN(device_create_file(dev, &dev_attr_tuner_note)); CHECK_RETURN(device_create_file(dev, &dev_attr_tuner_pitch)); -@@ -780,7 +774,6 @@ static int pod_try_init(struct usb_interface *interface, +@@ -780,7 +774,6 @@ /* initialize wait queues: */ init_waitqueue_head(&pod->tuner_mute.wait); @@ -57,7 +57,7 @@ init_waitqueue_head(&pod->tuner_note.wait); init_waitqueue_head(&pod->tuner_pitch.wait); -@@ -876,7 +869,6 @@ void line6_pod_disconnect(struct usb_interface *interface) +@@ -876,7 +869,6 @@ device_remove_file(dev, &dev_attr_firmware_version); device_remove_file(dev, &dev_attr_midi_postprocess); device_remove_file(dev, &dev_attr_serial_number); @@ -65,11 +65,11 @@ device_remove_file(dev, &dev_attr_tuner_mute); device_remove_file(dev, &dev_attr_tuner_note); device_remove_file(dev, &dev_attr_tuner_pitch); -diff --git a/drivers/staging/line6/pod.h b/drivers/staging/line6/pod.h -index 732311a..91f2661 100644 ---- a/drivers/staging/line6/pod.h -+++ b/drivers/staging/line6/pod.h -@@ -104,11 +104,6 @@ struct usb_line6_pod { +Index: linux-3.2.46/drivers/staging/line6/pod.h +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/pod.h 2013-07-26 19:29:39.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/pod.h 2013-07-26 19:29:40.000000000 +0000 +@@ -104,11 +104,6 @@ struct ValueWait tuner_mute; /** diff -Nru linux-3.2.46/debian/patches/features/all/line6/0079-staging-line6-drop-tuner_note-sysfs-attr.patch linux-3.2.46/debian/patches/features/all/line6/0079-staging-line6-drop-tuner_note-sysfs-attr.patch --- linux-3.2.46/debian/patches/features/all/line6/0079-staging-line6-drop-tuner_note-sysfs-attr.patch 2013-02-24 03:52:35.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/line6/0079-staging-line6-drop-tuner_note-sysfs-attr.patch 2013-07-26 19:29:42.000000000 +0000 @@ -11,11 +11,11 @@ drivers/staging/line6/pod.h | 5 ----- 2 files changed, 12 deletions(-) -diff --git a/drivers/staging/line6/pod.c b/drivers/staging/line6/pod.c -index 3184570..57fbe27 100644 ---- a/drivers/staging/line6/pod.c -+++ b/drivers/staging/line6/pod.c -@@ -250,8 +250,6 @@ void line6_pod_process_message(struct usb_line6_pod *pod) +Index: linux-3.2.46/drivers/staging/line6/pod.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/pod.c 2013-07-26 19:29:40.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/pod.c 2013-07-26 19:29:41.000000000 +0000 +@@ -250,8 +250,6 @@ PROCESS_SYSTEM_PARAM (tuner_mute); PROCESS_SYSTEM_PARAM @@ -24,7 +24,7 @@ (tuner_pitch); #undef PROCESS_SYSTEM_PARAM -@@ -644,7 +642,6 @@ static ssize_t pod_set_ ## code(struct device *dev, \ +@@ -644,7 +642,6 @@ } POD_GET_SET_SYSTEM_PARAM(tuner_mute, 0x0001, 0); @@ -32,7 +32,7 @@ POD_GET_SYSTEM_PARAM(tuner_pitch, 1); #undef GET_SET_SYSTEM_PARAM -@@ -661,7 +658,6 @@ static DEVICE_ATTR(serial_number, S_IRUGO, pod_get_serial_number, +@@ -661,7 +658,6 @@ line6_nop_write); static DEVICE_ATTR(tuner_mute, S_IWUSR | S_IRUGO, pod_get_tuner_mute, pod_set_tuner_mute); @@ -40,7 +40,7 @@ static DEVICE_ATTR(tuner_pitch, S_IRUGO, pod_get_tuner_pitch, line6_nop_write); #ifdef CONFIG_LINE6_USB_RAW -@@ -747,7 +743,6 @@ static int pod_create_files2(struct device *dev) +@@ -747,7 +743,6 @@ CHECK_RETURN(device_create_file(dev, &dev_attr_midi_postprocess)); CHECK_RETURN(device_create_file(dev, &dev_attr_serial_number)); CHECK_RETURN(device_create_file(dev, &dev_attr_tuner_mute)); @@ -48,7 +48,7 @@ CHECK_RETURN(device_create_file(dev, &dev_attr_tuner_pitch)); #ifdef CONFIG_LINE6_USB_RAW -@@ -774,7 +769,6 @@ static int pod_try_init(struct usb_interface *interface, +@@ -774,7 +769,6 @@ /* initialize wait queues: */ init_waitqueue_head(&pod->tuner_mute.wait); @@ -56,7 +56,7 @@ init_waitqueue_head(&pod->tuner_pitch.wait); /* initialize USB buffers: */ -@@ -870,7 +864,6 @@ void line6_pod_disconnect(struct usb_interface *interface) +@@ -870,7 +864,6 @@ device_remove_file(dev, &dev_attr_midi_postprocess); device_remove_file(dev, &dev_attr_serial_number); device_remove_file(dev, &dev_attr_tuner_mute); @@ -64,11 +64,11 @@ device_remove_file(dev, &dev_attr_tuner_pitch); #ifdef CONFIG_LINE6_USB_RAW -diff --git a/drivers/staging/line6/pod.h b/drivers/staging/line6/pod.h -index 91f2661..1659120 100644 ---- a/drivers/staging/line6/pod.h -+++ b/drivers/staging/line6/pod.h -@@ -104,11 +104,6 @@ struct usb_line6_pod { +Index: linux-3.2.46/drivers/staging/line6/pod.h +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/pod.h 2013-07-26 19:29:40.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/pod.h 2013-07-26 19:29:41.000000000 +0000 +@@ -104,11 +104,6 @@ struct ValueWait tuner_mute; /** diff -Nru linux-3.2.46/debian/patches/features/all/line6/0080-staging-line6-drop-tuner_mute-sysfs-attr.patch linux-3.2.46/debian/patches/features/all/line6/0080-staging-line6-drop-tuner_mute-sysfs-attr.patch --- linux-3.2.46/debian/patches/features/all/line6/0080-staging-line6-drop-tuner_mute-sysfs-attr.patch 2013-02-24 03:52:35.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/line6/0080-staging-line6-drop-tuner_mute-sysfs-attr.patch 2013-07-26 19:29:44.000000000 +0000 @@ -11,11 +11,11 @@ drivers/staging/line6/pod.h | 5 ----- 2 files changed, 39 deletions(-) -diff --git a/drivers/staging/line6/pod.c b/drivers/staging/line6/pod.c -index 57fbe27..df2f37a 100644 ---- a/drivers/staging/line6/pod.c -+++ b/drivers/staging/line6/pod.c -@@ -248,8 +248,6 @@ void line6_pod_process_message(struct usb_line6_pod *pod) +Index: linux-3.2.46/drivers/staging/line6/pod.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/pod.c 2013-07-26 19:29:41.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/pod.c 2013-07-26 19:29:43.000000000 +0000 +@@ -248,8 +248,6 @@ break; PROCESS_SYSTEM_PARAM @@ -24,7 +24,7 @@ (tuner_pitch); #undef PROCESS_SYSTEM_PARAM -@@ -453,20 +451,6 @@ static int pod_set_system_param_int(struct usb_line6_pod *pod, int value, +@@ -453,20 +451,6 @@ } /* @@ -45,7 +45,7 @@ "write" request on "finish" special file. */ static ssize_t pod_set_finish(struct device *dev, -@@ -630,21 +614,8 @@ static ssize_t pod_get_ ## code(struct device *dev, \ +@@ -630,21 +614,8 @@ &pod->code, sign); \ } @@ -67,7 +67,7 @@ #undef GET_SYSTEM_PARAM /* POD special files: */ -@@ -656,8 +627,6 @@ static DEVICE_ATTR(midi_postprocess, S_IWUSR | S_IRUGO, +@@ -656,8 +627,6 @@ pod_get_midi_postprocess, pod_set_midi_postprocess); static DEVICE_ATTR(serial_number, S_IRUGO, pod_get_serial_number, line6_nop_write); @@ -76,7 +76,7 @@ static DEVICE_ATTR(tuner_pitch, S_IRUGO, pod_get_tuner_pitch, line6_nop_write); #ifdef CONFIG_LINE6_USB_RAW -@@ -742,7 +711,6 @@ static int pod_create_files2(struct device *dev) +@@ -742,7 +711,6 @@ CHECK_RETURN(device_create_file(dev, &dev_attr_firmware_version)); CHECK_RETURN(device_create_file(dev, &dev_attr_midi_postprocess)); CHECK_RETURN(device_create_file(dev, &dev_attr_serial_number)); @@ -84,7 +84,7 @@ CHECK_RETURN(device_create_file(dev, &dev_attr_tuner_pitch)); #ifdef CONFIG_LINE6_USB_RAW -@@ -768,7 +736,6 @@ static int pod_try_init(struct usb_interface *interface, +@@ -768,7 +736,6 @@ return -ENODEV; /* initialize wait queues: */ @@ -92,7 +92,7 @@ init_waitqueue_head(&pod->tuner_pitch.wait); /* initialize USB buffers: */ -@@ -863,7 +830,6 @@ void line6_pod_disconnect(struct usb_interface *interface) +@@ -863,7 +830,6 @@ device_remove_file(dev, &dev_attr_firmware_version); device_remove_file(dev, &dev_attr_midi_postprocess); device_remove_file(dev, &dev_attr_serial_number); @@ -100,11 +100,11 @@ device_remove_file(dev, &dev_attr_tuner_pitch); #ifdef CONFIG_LINE6_USB_RAW -diff --git a/drivers/staging/line6/pod.h b/drivers/staging/line6/pod.h -index 1659120..4930742 100644 ---- a/drivers/staging/line6/pod.h -+++ b/drivers/staging/line6/pod.h -@@ -99,11 +99,6 @@ struct usb_line6_pod { +Index: linux-3.2.46/drivers/staging/line6/pod.h +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/pod.h 2013-07-26 19:29:41.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/pod.h 2013-07-26 19:29:43.000000000 +0000 +@@ -99,11 +99,6 @@ struct pod_program prog_data_buf; /** diff -Nru linux-3.2.46/debian/patches/features/all/line6/0081-staging-line6-drop-tuner_pitch-sysfs-attr.patch linux-3.2.46/debian/patches/features/all/line6/0081-staging-line6-drop-tuner_pitch-sysfs-attr.patch --- linux-3.2.46/debian/patches/features/all/line6/0081-staging-line6-drop-tuner_pitch-sysfs-attr.patch 2013-02-24 03:52:35.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/line6/0081-staging-line6-drop-tuner_pitch-sysfs-attr.patch 2013-07-26 19:29:45.000000000 +0000 @@ -22,11 +22,11 @@ drivers/staging/line6/pod.h | 15 ------- 2 files changed, 1 insertion(+), 116 deletions(-) -diff --git a/drivers/staging/line6/pod.c b/drivers/staging/line6/pod.c -index df2f37a..052db4a 100644 ---- a/drivers/staging/line6/pod.c -+++ b/drivers/staging/line6/pod.c -@@ -236,28 +236,8 @@ void line6_pod_process_message(struct usb_line6_pod *pod) +Index: linux-3.2.46/drivers/staging/line6/pod.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/pod.c 2013-07-26 19:29:43.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/pod.c 2013-07-26 19:29:44.000000000 +0000 +@@ -236,28 +236,8 @@ << 8) | ((int)buf[9] << 4) | (int)buf[10]; @@ -56,7 +56,7 @@ break; } -@@ -363,66 +343,6 @@ static bool pod_is_tuner(int code) +@@ -363,66 +343,6 @@ } /* @@ -123,7 +123,7 @@ Send system parameter (from integer). @param tuner non-zero, if code refers to a tuner parameter */ -@@ -604,20 +524,6 @@ static void pod_startup5(struct work_struct *work) +@@ -604,20 +524,6 @@ line6->properties->device_bit, line6->ifcdev); } @@ -144,7 +144,7 @@ /* POD special files: */ static DEVICE_ATTR(device_id, S_IRUGO, pod_get_device_id, line6_nop_write); static DEVICE_ATTR(finish, S_IWUSR, line6_nop_read, pod_set_finish); -@@ -627,7 +533,6 @@ static DEVICE_ATTR(midi_postprocess, S_IWUSR | S_IRUGO, +@@ -627,7 +533,6 @@ pod_get_midi_postprocess, pod_set_midi_postprocess); static DEVICE_ATTR(serial_number, S_IRUGO, pod_get_serial_number, line6_nop_write); @@ -152,7 +152,7 @@ #ifdef CONFIG_LINE6_USB_RAW static DEVICE_ATTR(raw, S_IWUSR, line6_nop_read, line6_set_raw); -@@ -711,7 +616,6 @@ static int pod_create_files2(struct device *dev) +@@ -711,7 +616,6 @@ CHECK_RETURN(device_create_file(dev, &dev_attr_firmware_version)); CHECK_RETURN(device_create_file(dev, &dev_attr_midi_postprocess)); CHECK_RETURN(device_create_file(dev, &dev_attr_serial_number)); @@ -160,7 +160,7 @@ #ifdef CONFIG_LINE6_USB_RAW CHECK_RETURN(device_create_file(dev, &dev_attr_raw)); -@@ -735,9 +639,6 @@ static int pod_try_init(struct usb_interface *interface, +@@ -735,9 +639,6 @@ if ((interface == NULL) || (pod == NULL)) return -ENODEV; @@ -170,7 +170,7 @@ /* initialize USB buffers: */ err = line6_dumpreq_init(&pod->dumpreq, pod_request_channel, sizeof(pod_request_channel)); -@@ -830,7 +731,6 @@ void line6_pod_disconnect(struct usb_interface *interface) +@@ -830,7 +731,6 @@ device_remove_file(dev, &dev_attr_firmware_version); device_remove_file(dev, &dev_attr_midi_postprocess); device_remove_file(dev, &dev_attr_serial_number); @@ -178,10 +178,10 @@ #ifdef CONFIG_LINE6_USB_RAW device_remove_file(dev, &dev_attr_raw); -diff --git a/drivers/staging/line6/pod.h b/drivers/staging/line6/pod.h -index 4930742..481cce6 100644 ---- a/drivers/staging/line6/pod.h -+++ b/drivers/staging/line6/pod.h +Index: linux-3.2.46/drivers/staging/line6/pod.h +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/pod.h 2013-07-26 19:29:43.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/pod.h 2013-07-26 19:29:44.000000000 +0000 @@ -15,7 +15,6 @@ #include #include @@ -190,7 +190,7 @@ #include -@@ -54,15 +53,6 @@ enum { +@@ -54,15 +53,6 @@ }; /** @@ -206,7 +206,7 @@ Binary PODxt Pro program dump */ struct pod_program { -@@ -99,11 +89,6 @@ struct usb_line6_pod { +@@ -99,11 +89,6 @@ struct pod_program prog_data_buf; /** diff -Nru linux-3.2.46/debian/patches/features/all/line6/0082-staging-line6-drop-finish-sysfs-attr.patch linux-3.2.46/debian/patches/features/all/line6/0082-staging-line6-drop-finish-sysfs-attr.patch --- linux-3.2.46/debian/patches/features/all/line6/0082-staging-line6-drop-finish-sysfs-attr.patch 2013-02-24 03:52:35.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/line6/0082-staging-line6-drop-finish-sysfs-attr.patch 2013-07-26 19:29:46.000000000 +0000 @@ -10,11 +10,11 @@ drivers/staging/line6/pod.c | 21 --------------------- 1 file changed, 21 deletions(-) -diff --git a/drivers/staging/line6/pod.c b/drivers/staging/line6/pod.c -index 052db4a..797f6e0 100644 ---- a/drivers/staging/line6/pod.c -+++ b/drivers/staging/line6/pod.c -@@ -371,24 +371,6 @@ static int pod_set_system_param_int(struct usb_line6_pod *pod, int value, +Index: linux-3.2.46/drivers/staging/line6/pod.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/pod.c 2013-07-26 19:29:44.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/pod.c 2013-07-26 19:29:45.000000000 +0000 +@@ -371,24 +371,6 @@ } /* @@ -39,7 +39,7 @@ "read" request on "midi_postprocess" special file. */ static ssize_t pod_get_midi_postprocess(struct device *dev, -@@ -526,7 +508,6 @@ static void pod_startup5(struct work_struct *work) +@@ -526,7 +508,6 @@ /* POD special files: */ static DEVICE_ATTR(device_id, S_IRUGO, pod_get_device_id, line6_nop_write); @@ -47,7 +47,7 @@ static DEVICE_ATTR(firmware_version, S_IRUGO, pod_get_firmware_version, line6_nop_write); static DEVICE_ATTR(midi_postprocess, S_IWUSR | S_IRUGO, -@@ -612,7 +593,6 @@ static int pod_create_files2(struct device *dev) +@@ -612,7 +593,6 @@ int err; CHECK_RETURN(device_create_file(dev, &dev_attr_device_id)); @@ -55,7 +55,7 @@ CHECK_RETURN(device_create_file(dev, &dev_attr_firmware_version)); CHECK_RETURN(device_create_file(dev, &dev_attr_midi_postprocess)); CHECK_RETURN(device_create_file(dev, &dev_attr_serial_number)); -@@ -727,7 +707,6 @@ void line6_pod_disconnect(struct usb_interface *interface) +@@ -727,7 +707,6 @@ properties->device_bit, dev); device_remove_file(dev, &dev_attr_device_id); diff -Nru linux-3.2.46/debian/patches/features/all/line6/0083-staging-line6-drop-midi_postprocess-sysfs-attr.patch linux-3.2.46/debian/patches/features/all/line6/0083-staging-line6-drop-midi_postprocess-sysfs-attr.patch --- linux-3.2.46/debian/patches/features/all/line6/0083-staging-line6-drop-midi_postprocess-sysfs-attr.patch 2013-02-24 03:52:35.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/line6/0083-staging-line6-drop-midi_postprocess-sysfs-attr.patch 2013-07-26 19:29:48.000000000 +0000 @@ -10,11 +10,11 @@ drivers/staging/line6/pod.c | 36 ------------------------------------ 1 file changed, 36 deletions(-) -diff --git a/drivers/staging/line6/pod.c b/drivers/staging/line6/pod.c -index 797f6e0..37b20d7 100644 ---- a/drivers/staging/line6/pod.c -+++ b/drivers/staging/line6/pod.c -@@ -371,38 +371,6 @@ static int pod_set_system_param_int(struct usb_line6_pod *pod, int value, +Index: linux-3.2.46/drivers/staging/line6/pod.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/pod.c 2013-07-26 19:29:45.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/pod.c 2013-07-26 19:29:47.000000000 +0000 +@@ -371,38 +371,6 @@ } /* @@ -53,7 +53,7 @@ "read" request on "serial_number" special file. */ static ssize_t pod_get_serial_number(struct device *dev, -@@ -510,8 +478,6 @@ static void pod_startup5(struct work_struct *work) +@@ -510,8 +478,6 @@ static DEVICE_ATTR(device_id, S_IRUGO, pod_get_device_id, line6_nop_write); static DEVICE_ATTR(firmware_version, S_IRUGO, pod_get_firmware_version, line6_nop_write); @@ -62,7 +62,7 @@ static DEVICE_ATTR(serial_number, S_IRUGO, pod_get_serial_number, line6_nop_write); -@@ -594,7 +560,6 @@ static int pod_create_files2(struct device *dev) +@@ -594,7 +560,6 @@ CHECK_RETURN(device_create_file(dev, &dev_attr_device_id)); CHECK_RETURN(device_create_file(dev, &dev_attr_firmware_version)); @@ -70,7 +70,7 @@ CHECK_RETURN(device_create_file(dev, &dev_attr_serial_number)); #ifdef CONFIG_LINE6_USB_RAW -@@ -708,7 +673,6 @@ void line6_pod_disconnect(struct usb_interface *interface) +@@ -708,7 +673,6 @@ device_remove_file(dev, &dev_attr_device_id); device_remove_file(dev, &dev_attr_firmware_version); diff -Nru linux-3.2.46/debian/patches/features/all/line6/0084-staging-line6-drop-midi_mask_receive.patch linux-3.2.46/debian/patches/features/all/line6/0084-staging-line6-drop-midi_mask_receive.patch --- linux-3.2.46/debian/patches/features/all/line6/0084-staging-line6-drop-midi_mask_receive.patch 2013-02-24 03:52:35.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/line6/0084-staging-line6-drop-midi_mask_receive.patch 2013-07-26 19:29:49.000000000 +0000 @@ -19,11 +19,11 @@ drivers/staging/line6/midi.h | 5 ----- 3 files changed, 52 deletions(-) -diff --git a/drivers/staging/line6/driver.c b/drivers/staging/line6/driver.c -index 0bc838d..e0e0779 100644 ---- a/drivers/staging/line6/driver.c -+++ b/drivers/staging/line6/driver.c -@@ -396,11 +396,6 @@ static void line6_data_received(struct urb *urb) +Index: linux-3.2.46/drivers/staging/line6/driver.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/driver.c 2013-07-26 19:29:14.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/driver.c 2013-07-26 19:29:48.000000000 +0000 +@@ -396,11 +396,6 @@ if (done == 0) break; @@ -35,11 +35,11 @@ line6->message_length = done; line6_midi_receive(line6, line6->buffer_message, done); -diff --git a/drivers/staging/line6/midi.c b/drivers/staging/line6/midi.c -index c8e099b..c543c48 100644 ---- a/drivers/staging/line6/midi.c -+++ b/drivers/staging/line6/midi.c -@@ -313,42 +313,8 @@ static ssize_t midi_set_midi_mask_transmit(struct device *dev, +Index: linux-3.2.46/drivers/staging/line6/midi.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/midi.c 2013-07-26 19:29:14.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/midi.c 2013-07-26 19:29:48.000000000 +0000 +@@ -313,42 +313,8 @@ return count; } @@ -82,7 +82,7 @@ /* MIDI device destructor */ static int snd_line6_midi_free(struct snd_device *device) -@@ -356,8 +322,6 @@ static int snd_line6_midi_free(struct snd_device *device) +@@ -356,8 +322,6 @@ struct snd_line6_midi *line6midi = device->device_data; device_remove_file(line6midi->line6->ifcdev, &dev_attr_midi_mask_transmit); @@ -91,7 +91,7 @@ line6_midibuf_destroy(&line6midi->midibuf_in); line6_midibuf_destroy(&line6midi->midibuf_out); return 0; -@@ -404,12 +368,10 @@ int line6_init_midi(struct usb_line6 *line6) +@@ -404,12 +368,10 @@ case LINE6_DEVID_PODHD300: case LINE6_DEVID_PODHD500: line6midi->midi_mask_transmit = 1; @@ -104,7 +104,7 @@ } line6->line6midi = line6midi; -@@ -429,10 +391,6 @@ int line6_init_midi(struct usb_line6 *line6) +@@ -429,10 +391,6 @@ if (err < 0) return err; @@ -115,11 +115,11 @@ init_waitqueue_head(&line6midi->send_wait); spin_lock_init(&line6midi->send_urb_lock); spin_lock_init(&line6midi->midi_transmit_lock); -diff --git a/drivers/staging/line6/midi.h b/drivers/staging/line6/midi.h -index 4a9e9f9..cf32d77 100644 ---- a/drivers/staging/line6/midi.h -+++ b/drivers/staging/line6/midi.h -@@ -60,11 +60,6 @@ struct snd_line6_midi { +Index: linux-3.2.46/drivers/staging/line6/midi.h +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/midi.h 2013-07-26 19:28:08.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/midi.h 2013-07-26 19:29:48.000000000 +0000 +@@ -60,11 +60,6 @@ unsigned short midi_mask_transmit; /** diff -Nru linux-3.2.46/debian/patches/features/all/line6/0085-staging-line6-drop-midi_mask_transmit.patch linux-3.2.46/debian/patches/features/all/line6/0085-staging-line6-drop-midi_mask_transmit.patch --- linux-3.2.46/debian/patches/features/all/line6/0085-staging-line6-drop-midi_mask_transmit.patch 2013-02-24 03:52:35.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/line6/0085-staging-line6-drop-midi_mask_transmit.patch 2013-07-26 19:29:50.000000000 +0000 @@ -18,11 +18,11 @@ drivers/staging/line6/midi.h | 5 ---- 2 files changed, 61 deletions(-) -diff --git a/drivers/staging/line6/midi.c b/drivers/staging/line6/midi.c -index c543c48..6d9ecb9 100644 ---- a/drivers/staging/line6/midi.c -+++ b/drivers/staging/line6/midi.c -@@ -69,10 +69,6 @@ static void line6_midi_transmit(struct snd_rawmidi_substream *substream) +Index: linux-3.2.46/drivers/staging/line6/midi.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/midi.c 2013-07-26 19:29:48.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/midi.c 2013-07-26 19:29:49.000000000 +0000 +@@ -69,10 +69,6 @@ if (done == 0) break; @@ -33,7 +33,7 @@ send_midi_async(line6, chunk, done); } -@@ -281,47 +277,10 @@ static int snd_line6_new_midi(struct snd_line6_midi *line6midi) +@@ -281,47 +277,10 @@ return 0; } @@ -81,7 +81,7 @@ line6_midibuf_destroy(&line6midi->midibuf_in); line6_midibuf_destroy(&line6midi->midibuf_out); return 0; -@@ -363,17 +322,6 @@ int line6_init_midi(struct usb_line6 *line6) +@@ -363,17 +322,6 @@ } line6midi->line6 = line6; @@ -99,7 +99,7 @@ line6->line6midi = line6midi; err = snd_device_new(line6->card, SNDRV_DEV_RAWMIDI, line6midi, -@@ -387,10 +335,6 @@ int line6_init_midi(struct usb_line6 *line6) +@@ -387,10 +335,6 @@ if (err < 0) return err; @@ -110,11 +110,11 @@ init_waitqueue_head(&line6midi->send_wait); spin_lock_init(&line6midi->send_urb_lock); spin_lock_init(&line6midi->midi_transmit_lock); -diff --git a/drivers/staging/line6/midi.h b/drivers/staging/line6/midi.h -index cf32d77..19dabd5 100644 ---- a/drivers/staging/line6/midi.h -+++ b/drivers/staging/line6/midi.h -@@ -55,11 +55,6 @@ struct snd_line6_midi { +Index: linux-3.2.46/drivers/staging/line6/midi.h +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/midi.h 2013-07-26 19:29:48.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/midi.h 2013-07-26 19:29:49.000000000 +0000 +@@ -55,11 +55,6 @@ wait_queue_head_t send_wait; /** diff -Nru linux-3.2.46/debian/patches/features/all/line6/0086-staging-line6-drop-midi_postprocess-flag.patch linux-3.2.46/debian/patches/features/all/line6/0086-staging-line6-drop-midi_postprocess-flag.patch --- linux-3.2.46/debian/patches/features/all/line6/0086-staging-line6-drop-midi_postprocess-flag.patch 2013-02-24 03:52:35.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/line6/0086-staging-line6-drop-midi_postprocess-flag.patch 2013-07-26 19:29:52.000000000 +0000 @@ -23,11 +23,11 @@ drivers/staging/line6/pod.h | 7 ------- 3 files changed, 63 deletions(-) -diff --git a/drivers/staging/line6/midi.c b/drivers/staging/line6/midi.c -index 6d9ecb9..6982eca 100644 ---- a/drivers/staging/line6/midi.c -+++ b/drivers/staging/line6/midi.c -@@ -148,28 +148,6 @@ static int send_midi_async(struct usb_line6 *line6, unsigned char *data, +Index: linux-3.2.46/drivers/staging/line6/midi.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/midi.c 2013-07-26 19:29:49.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/midi.c 2013-07-26 19:29:51.000000000 +0000 +@@ -148,28 +148,6 @@ } ++line6->line6midi->num_active_send_urbs; @@ -56,11 +56,11 @@ return 0; } -diff --git a/drivers/staging/line6/pod.c b/drivers/staging/line6/pod.c -index 37b20d7..ddd0e54 100644 ---- a/drivers/staging/line6/pod.c -+++ b/drivers/staging/line6/pod.c -@@ -285,40 +285,6 @@ void line6_pod_process_message(struct usb_line6_pod *pod) +Index: linux-3.2.46/drivers/staging/line6/pod.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/pod.c 2013-07-26 19:29:47.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/pod.c 2013-07-26 19:29:51.000000000 +0000 +@@ -285,40 +285,6 @@ } /* @@ -101,11 +101,11 @@ Transmit PODxt Pro control parameter. */ void line6_pod_transmit_parameter(struct usb_line6_pod *pod, int param, -diff --git a/drivers/staging/line6/pod.h b/drivers/staging/line6/pod.h -index 481cce6..8543bae 100644 ---- a/drivers/staging/line6/pod.h -+++ b/drivers/staging/line6/pod.h -@@ -127,18 +127,11 @@ struct usb_line6_pod { +Index: linux-3.2.46/drivers/staging/line6/pod.h +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/pod.h 2013-07-26 19:29:44.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/pod.h 2013-07-26 19:29:51.000000000 +0000 +@@ -127,18 +127,11 @@ Device ID. */ int device_id; diff -Nru linux-3.2.46/debian/patches/features/all/line6/0087-staging-line6-drop-pod.c-raw-sysfs-attr.patch linux-3.2.46/debian/patches/features/all/line6/0087-staging-line6-drop-pod.c-raw-sysfs-attr.patch --- linux-3.2.46/debian/patches/features/all/line6/0087-staging-line6-drop-pod.c-raw-sysfs-attr.patch 2013-02-24 03:52:35.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/line6/0087-staging-line6-drop-pod.c-raw-sysfs-attr.patch 2013-07-26 19:29:53.000000000 +0000 @@ -15,11 +15,11 @@ drivers/staging/line6/pod.c | 13 ------------- 1 file changed, 13 deletions(-) -diff --git a/drivers/staging/line6/pod.c b/drivers/staging/line6/pod.c -index ddd0e54..db9c905 100644 ---- a/drivers/staging/line6/pod.c -+++ b/drivers/staging/line6/pod.c -@@ -447,10 +447,6 @@ static DEVICE_ATTR(firmware_version, S_IRUGO, pod_get_firmware_version, +Index: linux-3.2.46/drivers/staging/line6/pod.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/pod.c 2013-07-26 19:29:51.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/pod.c 2013-07-26 19:29:52.000000000 +0000 +@@ -447,10 +447,6 @@ static DEVICE_ATTR(serial_number, S_IRUGO, pod_get_serial_number, line6_nop_write); @@ -30,7 +30,7 @@ /* control info callback */ static int snd_pod_control_monitor_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) -@@ -527,11 +523,6 @@ static int pod_create_files2(struct device *dev) +@@ -527,11 +523,6 @@ CHECK_RETURN(device_create_file(dev, &dev_attr_device_id)); CHECK_RETURN(device_create_file(dev, &dev_attr_firmware_version)); CHECK_RETURN(device_create_file(dev, &dev_attr_serial_number)); @@ -42,7 +42,7 @@ return 0; } -@@ -640,10 +631,6 @@ void line6_pod_disconnect(struct usb_interface *interface) +@@ -640,10 +631,6 @@ device_remove_file(dev, &dev_attr_device_id); device_remove_file(dev, &dev_attr_firmware_version); device_remove_file(dev, &dev_attr_serial_number); diff -Nru linux-3.2.46/debian/patches/features/all/line6/0088-staging-line6-drop-tuner-param-filtering.patch linux-3.2.46/debian/patches/features/all/line6/0088-staging-line6-drop-tuner-param-filtering.patch --- linux-3.2.46/debian/patches/features/all/line6/0088-staging-line6-drop-tuner-param-filtering.patch 2013-02-24 03:52:35.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/line6/0088-staging-line6-drop-tuner-param-filtering.patch 2013-07-26 19:29:54.000000000 +0000 @@ -15,11 +15,11 @@ drivers/staging/line6/pod.c | 21 --------------------- 1 file changed, 21 deletions(-) -diff --git a/drivers/staging/line6/pod.c b/drivers/staging/line6/pod.c -index db9c905..157ef68 100644 ---- a/drivers/staging/line6/pod.c -+++ b/drivers/staging/line6/pod.c -@@ -40,10 +40,6 @@ enum { +Index: linux-3.2.46/drivers/staging/line6/pod.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/pod.c 2013-07-26 19:29:52.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/pod.c 2013-07-26 19:29:54.000000000 +0000 +@@ -40,10 +40,6 @@ enum { POD_monitor_level = 0x04, @@ -30,7 +30,7 @@ POD_system_invalid = 0x10000 }; -@@ -298,19 +294,7 @@ void line6_pod_transmit_parameter(struct usb_line6_pod *pod, int param, +@@ -298,19 +294,7 @@ } /* @@ -50,7 +50,7 @@ */ static int pod_set_system_param_int(struct usb_line6_pod *pod, int value, int code) -@@ -318,11 +302,6 @@ static int pod_set_system_param_int(struct usb_line6_pod *pod, int value, +@@ -318,11 +302,6 @@ char *sysex; static const int size = 5; diff -Nru linux-3.2.46/debian/patches/features/all/line6/0089-staging-line6-drop-variax-model-sysfs-attr.patch linux-3.2.46/debian/patches/features/all/line6/0089-staging-line6-drop-variax-model-sysfs-attr.patch --- linux-3.2.46/debian/patches/features/all/line6/0089-staging-line6-drop-variax-model-sysfs-attr.patch 2013-02-24 03:52:35.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/line6/0089-staging-line6-drop-variax-model-sysfs-attr.patch 2013-07-26 19:29:56.000000000 +0000 @@ -11,11 +11,11 @@ drivers/staging/line6/variax.h | 5 ----- 2 files changed, 43 deletions(-) -diff --git a/drivers/staging/line6/variax.c b/drivers/staging/line6/variax.c -index 8df529f..e76255b 100644 ---- a/drivers/staging/line6/variax.c -+++ b/drivers/staging/line6/variax.c -@@ -212,7 +212,6 @@ void line6_variax_process_message(struct usb_line6_variax *variax) +Index: linux-3.2.46/drivers/staging/line6/variax.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/variax.c 2013-07-26 19:29:06.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/variax.c 2013-07-26 19:29:55.000000000 +0000 +@@ -212,7 +212,6 @@ case LINE6_PROGRAM_CHANGE | LINE6_CHANNEL_DEVICE: case LINE6_PROGRAM_CHANGE | LINE6_CHANNEL_HOST: @@ -23,7 +23,7 @@ line6_dump_request_async(&variax->dumpreq, &variax->line6, 0, VARIAX_DUMP_PASS1); break; -@@ -334,39 +333,6 @@ static ssize_t variax_set_volume(struct device *dev, +@@ -334,39 +333,6 @@ } /* @@ -63,7 +63,7 @@ "read" request on "active" special file. */ static ssize_t variax_get_active(struct device *dev, -@@ -549,8 +515,6 @@ static ssize_t variax_set_raw2(struct device *dev, +@@ -549,8 +515,6 @@ #endif /* Variax workbench special files: */ @@ -72,7 +72,7 @@ static DEVICE_ATTR(volume, S_IWUSR | S_IRUGO, variax_get_volume, variax_set_volume); static DEVICE_ATTR(tone, S_IWUSR | S_IRUGO, variax_get_tone, variax_set_tone); -@@ -595,7 +559,6 @@ static void variax_destruct(struct usb_interface *interface) +@@ -595,7 +559,6 @@ static int variax_create_files2(struct device *dev) { int err; @@ -80,7 +80,7 @@ CHECK_RETURN(device_create_file(dev, &dev_attr_volume)); CHECK_RETURN(device_create_file(dev, &dev_attr_tone)); CHECK_RETURN(device_create_file(dev, &dev_attr_name)); -@@ -701,7 +664,6 @@ void line6_variax_disconnect(struct usb_interface *interface) +@@ -701,7 +664,6 @@ if (dev != NULL) { /* remove sysfs entries: */ line6_variax_remove_files(0, 0, dev); @@ -88,11 +88,11 @@ device_remove_file(dev, &dev_attr_volume); device_remove_file(dev, &dev_attr_tone); device_remove_file(dev, &dev_attr_name); -diff --git a/drivers/staging/line6/variax.h b/drivers/staging/line6/variax.h -index e2999ab..4151c14 100644 ---- a/drivers/staging/line6/variax.h -+++ b/drivers/staging/line6/variax.h -@@ -78,11 +78,6 @@ struct usb_line6_variax { +Index: linux-3.2.46/drivers/staging/line6/variax.h +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/variax.h 2013-07-26 18:52:32.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/variax.h 2013-07-26 19:29:55.000000000 +0000 +@@ -78,11 +78,6 @@ unsigned char *buffer_activate; /** diff -Nru linux-3.2.46/debian/patches/features/all/line6/0090-staging-line6-drop-variax-volume-sysfs-attr.patch linux-3.2.46/debian/patches/features/all/line6/0090-staging-line6-drop-variax-volume-sysfs-attr.patch --- linux-3.2.46/debian/patches/features/all/line6/0090-staging-line6-drop-variax-volume-sysfs-attr.patch 2013-02-24 03:52:35.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/line6/0090-staging-line6-drop-variax-volume-sysfs-attr.patch 2013-07-26 19:29:57.000000000 +0000 @@ -11,11 +11,11 @@ drivers/staging/line6/variax.h | 5 ----- 2 files changed, 47 deletions(-) -diff --git a/drivers/staging/line6/variax.c b/drivers/staging/line6/variax.c -index e76255b..ef78f5a 100644 ---- a/drivers/staging/line6/variax.c -+++ b/drivers/staging/line6/variax.c -@@ -200,10 +200,6 @@ void line6_variax_process_message(struct usb_line6_variax *variax) +Index: linux-3.2.46/drivers/staging/line6/variax.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/variax.c 2013-07-26 19:29:55.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/variax.c 2013-07-26 19:29:56.000000000 +0000 +@@ -200,10 +200,6 @@ switch (buf[0]) { case LINE6_PARAM_CHANGE | LINE6_CHANNEL_HOST: switch (buf[1]) { @@ -26,7 +26,7 @@ case VARIAXMIDI_tone: variax->tone = buf[2]; } -@@ -299,40 +295,6 @@ void line6_variax_process_message(struct usb_line6_variax *variax) +@@ -299,40 +295,6 @@ } /* @@ -67,7 +67,7 @@ "read" request on "active" special file. */ static ssize_t variax_get_active(struct device *dev, -@@ -515,8 +477,6 @@ static ssize_t variax_set_raw2(struct device *dev, +@@ -515,8 +477,6 @@ #endif /* Variax workbench special files: */ @@ -76,7 +76,7 @@ static DEVICE_ATTR(tone, S_IWUSR | S_IRUGO, variax_get_tone, variax_set_tone); static DEVICE_ATTR(name, S_IRUGO, variax_get_name, line6_nop_write); static DEVICE_ATTR(bank, S_IRUGO, variax_get_bank, line6_nop_write); -@@ -559,7 +519,6 @@ static void variax_destruct(struct usb_interface *interface) +@@ -559,7 +519,6 @@ static int variax_create_files2(struct device *dev) { int err; @@ -84,7 +84,7 @@ CHECK_RETURN(device_create_file(dev, &dev_attr_tone)); CHECK_RETURN(device_create_file(dev, &dev_attr_name)); CHECK_RETURN(device_create_file(dev, &dev_attr_bank)); -@@ -664,7 +623,6 @@ void line6_variax_disconnect(struct usb_interface *interface) +@@ -664,7 +623,6 @@ if (dev != NULL) { /* remove sysfs entries: */ line6_variax_remove_files(0, 0, dev); @@ -92,11 +92,11 @@ device_remove_file(dev, &dev_attr_tone); device_remove_file(dev, &dev_attr_name); device_remove_file(dev, &dev_attr_bank); -diff --git a/drivers/staging/line6/variax.h b/drivers/staging/line6/variax.h -index 4151c14..426c90c 100644 ---- a/drivers/staging/line6/variax.h -+++ b/drivers/staging/line6/variax.h -@@ -93,11 +93,6 @@ struct usb_line6_variax { +Index: linux-3.2.46/drivers/staging/line6/variax.h +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/variax.h 2013-07-26 19:29:55.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/variax.h 2013-07-26 19:29:56.000000000 +0000 +@@ -93,11 +93,6 @@ unsigned char bank[18]; /** diff -Nru linux-3.2.46/debian/patches/features/all/line6/0091-staging-line6-drop-variax-tone-sysfs-attr.patch linux-3.2.46/debian/patches/features/all/line6/0091-staging-line6-drop-variax-tone-sysfs-attr.patch --- linux-3.2.46/debian/patches/features/all/line6/0091-staging-line6-drop-variax-tone-sysfs-attr.patch 2013-02-24 03:52:35.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/line6/0091-staging-line6-drop-variax-tone-sysfs-attr.patch 2013-07-26 19:29:58.000000000 +0000 @@ -11,11 +11,11 @@ drivers/staging/line6/variax.h | 5 ----- 2 files changed, 47 deletions(-) -diff --git a/drivers/staging/line6/variax.c b/drivers/staging/line6/variax.c -index ef78f5a..31ece34 100644 ---- a/drivers/staging/line6/variax.c -+++ b/drivers/staging/line6/variax.c -@@ -199,11 +199,6 @@ void line6_variax_process_message(struct usb_line6_variax *variax) +Index: linux-3.2.46/drivers/staging/line6/variax.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/variax.c 2013-07-26 19:29:56.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/variax.c 2013-07-26 19:29:57.000000000 +0000 +@@ -199,11 +199,6 @@ switch (buf[0]) { case LINE6_PARAM_CHANGE | LINE6_CHANNEL_HOST: @@ -27,7 +27,7 @@ break; case LINE6_PROGRAM_CHANGE | LINE6_CHANNEL_DEVICE: -@@ -326,40 +321,6 @@ static ssize_t variax_set_active(struct device *dev, +@@ -326,40 +321,6 @@ return count; } @@ -68,7 +68,7 @@ static ssize_t get_string(char *buf, const char *data, int length) { int i; -@@ -477,7 +438,6 @@ static ssize_t variax_set_raw2(struct device *dev, +@@ -477,7 +438,6 @@ #endif /* Variax workbench special files: */ @@ -76,7 +76,7 @@ static DEVICE_ATTR(name, S_IRUGO, variax_get_name, line6_nop_write); static DEVICE_ATTR(bank, S_IRUGO, variax_get_bank, line6_nop_write); static DEVICE_ATTR(dump, S_IRUGO, variax_get_dump, line6_nop_write); -@@ -519,7 +479,6 @@ static void variax_destruct(struct usb_interface *interface) +@@ -519,7 +479,6 @@ static int variax_create_files2(struct device *dev) { int err; @@ -84,7 +84,7 @@ CHECK_RETURN(device_create_file(dev, &dev_attr_name)); CHECK_RETURN(device_create_file(dev, &dev_attr_bank)); CHECK_RETURN(device_create_file(dev, &dev_attr_dump)); -@@ -623,7 +582,6 @@ void line6_variax_disconnect(struct usb_interface *interface) +@@ -623,7 +582,6 @@ if (dev != NULL) { /* remove sysfs entries: */ line6_variax_remove_files(0, 0, dev); @@ -92,11 +92,11 @@ device_remove_file(dev, &dev_attr_name); device_remove_file(dev, &dev_attr_bank); device_remove_file(dev, &dev_attr_dump); -diff --git a/drivers/staging/line6/variax.h b/drivers/staging/line6/variax.h -index 426c90c..745b5a1 100644 ---- a/drivers/staging/line6/variax.h -+++ b/drivers/staging/line6/variax.h -@@ -93,11 +93,6 @@ struct usb_line6_variax { +Index: linux-3.2.46/drivers/staging/line6/variax.h +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/variax.h 2013-07-26 19:29:56.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/variax.h 2013-07-26 19:29:57.000000000 +0000 +@@ -93,11 +93,6 @@ unsigned char bank[18]; /** diff -Nru linux-3.2.46/debian/patches/features/all/line6/0092-staging-line6-drop-variax-name-sysfs-attr.patch linux-3.2.46/debian/patches/features/all/line6/0092-staging-line6-drop-variax-name-sysfs-attr.patch --- linux-3.2.46/debian/patches/features/all/line6/0092-staging-line6-drop-variax-name-sysfs-attr.patch 2013-02-24 03:52:35.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/line6/0092-staging-line6-drop-variax-name-sysfs-attr.patch 2013-07-26 19:30:00.000000000 +0000 @@ -10,11 +10,11 @@ drivers/staging/line6/variax.c | 27 --------------------------- 1 file changed, 27 deletions(-) -diff --git a/drivers/staging/line6/variax.c b/drivers/staging/line6/variax.c -index 31ece34..94a9f71 100644 ---- a/drivers/staging/line6/variax.c -+++ b/drivers/staging/line6/variax.c -@@ -218,17 +218,6 @@ void line6_variax_process_message(struct usb_line6_variax *variax) +Index: linux-3.2.46/drivers/staging/line6/variax.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/variax.c 2013-07-26 19:29:57.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/variax.c 2013-07-26 19:29:59.000000000 +0000 +@@ -218,17 +218,6 @@ VARIAX_MODEL_MESSAGE_LENGTH) { switch (variax->dumpreq.in_progress) { case VARIAX_DUMP_PASS1: @@ -32,7 +32,7 @@ line6_dump_request_async (&variax->dumpreq, &variax->line6, 1, VARIAX_DUMP_PASS2); -@@ -338,19 +327,6 @@ static ssize_t get_string(char *buf, const char *data, int length) +@@ -338,19 +327,6 @@ } /* @@ -52,7 +52,7 @@ "read" request on "bank" special file. */ static ssize_t variax_get_bank(struct device *dev, -@@ -438,7 +414,6 @@ static ssize_t variax_set_raw2(struct device *dev, +@@ -438,7 +414,6 @@ #endif /* Variax workbench special files: */ @@ -60,7 +60,7 @@ static DEVICE_ATTR(bank, S_IRUGO, variax_get_bank, line6_nop_write); static DEVICE_ATTR(dump, S_IRUGO, variax_get_dump, line6_nop_write); static DEVICE_ATTR(active, S_IWUSR | S_IRUGO, variax_get_active, -@@ -479,7 +454,6 @@ static void variax_destruct(struct usb_interface *interface) +@@ -479,7 +454,6 @@ static int variax_create_files2(struct device *dev) { int err; @@ -68,7 +68,7 @@ CHECK_RETURN(device_create_file(dev, &dev_attr_bank)); CHECK_RETURN(device_create_file(dev, &dev_attr_dump)); CHECK_RETURN(device_create_file(dev, &dev_attr_active)); -@@ -582,7 +556,6 @@ void line6_variax_disconnect(struct usb_interface *interface) +@@ -582,7 +556,6 @@ if (dev != NULL) { /* remove sysfs entries: */ line6_variax_remove_files(0, 0, dev); diff -Nru linux-3.2.46/debian/patches/features/all/line6/0093-staging-line6-drop-variax-bank-sysfs-attr.patch linux-3.2.46/debian/patches/features/all/line6/0093-staging-line6-drop-variax-bank-sysfs-attr.patch --- linux-3.2.46/debian/patches/features/all/line6/0093-staging-line6-drop-variax-bank-sysfs-attr.patch 2013-02-24 03:52:35.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/line6/0093-staging-line6-drop-variax-bank-sysfs-attr.patch 2013-07-26 19:30:01.000000000 +0000 @@ -13,11 +13,11 @@ drivers/staging/line6/variax.h | 5 ----- 2 files changed, 39 deletions(-) -diff --git a/drivers/staging/line6/variax.c b/drivers/staging/line6/variax.c -index 94a9f71..8eec139 100644 ---- a/drivers/staging/line6/variax.c -+++ b/drivers/staging/line6/variax.c -@@ -248,9 +248,6 @@ void line6_variax_process_message(struct usb_line6_variax *variax) +Index: linux-3.2.46/drivers/staging/line6/variax.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/variax.c 2013-07-26 19:29:59.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/variax.c 2013-07-26 19:30:00.000000000 +0000 +@@ -248,9 +248,6 @@ } } else if (memcmp(buf + 1, variax_request_bank + 1, sizeof(variax_request_bank) - 2) == 0) { @@ -27,7 +27,7 @@ line6_dump_finished(&variax->dumpreq); variax_startup6(variax); } else if (memcmp(buf + 1, variax_init_model + 1, -@@ -310,34 +307,6 @@ static ssize_t variax_set_active(struct device *dev, +@@ -310,34 +307,6 @@ return count; } @@ -62,7 +62,7 @@ /* "read" request on "dump" special file. */ -@@ -414,7 +383,6 @@ static ssize_t variax_set_raw2(struct device *dev, +@@ -414,7 +383,6 @@ #endif /* Variax workbench special files: */ @@ -70,7 +70,7 @@ static DEVICE_ATTR(dump, S_IRUGO, variax_get_dump, line6_nop_write); static DEVICE_ATTR(active, S_IWUSR | S_IRUGO, variax_get_active, variax_set_active); -@@ -454,7 +422,6 @@ static void variax_destruct(struct usb_interface *interface) +@@ -454,7 +422,6 @@ static int variax_create_files2(struct device *dev) { int err; @@ -78,7 +78,7 @@ CHECK_RETURN(device_create_file(dev, &dev_attr_dump)); CHECK_RETURN(device_create_file(dev, &dev_attr_active)); CHECK_RETURN(device_create_file(dev, &dev_attr_guitar)); -@@ -556,7 +523,6 @@ void line6_variax_disconnect(struct usb_interface *interface) +@@ -556,7 +523,6 @@ if (dev != NULL) { /* remove sysfs entries: */ line6_variax_remove_files(0, 0, dev); @@ -86,11 +86,11 @@ device_remove_file(dev, &dev_attr_dump); device_remove_file(dev, &dev_attr_active); device_remove_file(dev, &dev_attr_guitar); -diff --git a/drivers/staging/line6/variax.h b/drivers/staging/line6/variax.h -index 745b5a1..b5d6a66 100644 ---- a/drivers/staging/line6/variax.h -+++ b/drivers/staging/line6/variax.h -@@ -88,11 +88,6 @@ struct usb_line6_variax { +Index: linux-3.2.46/drivers/staging/line6/variax.h +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/variax.h 2013-07-26 19:29:57.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/variax.h 2013-07-26 19:30:00.000000000 +0000 +@@ -88,11 +88,6 @@ unsigned char guitar[18]; /** diff -Nru linux-3.2.46/debian/patches/features/all/line6/0094-staging-line6-drop-variax-dump-sysfs-attr.patch linux-3.2.46/debian/patches/features/all/line6/0094-staging-line6-drop-variax-dump-sysfs-attr.patch --- linux-3.2.46/debian/patches/features/all/line6/0094-staging-line6-drop-variax-dump-sysfs-attr.patch 2013-02-24 03:52:35.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/line6/0094-staging-line6-drop-variax-dump-sysfs-attr.patch 2013-07-26 19:30:02.000000000 +0000 @@ -10,11 +10,11 @@ drivers/staging/line6/variax.c | 20 -------------------- 1 file changed, 20 deletions(-) -diff --git a/drivers/staging/line6/variax.c b/drivers/staging/line6/variax.c -index 8eec139..0f1846e 100644 ---- a/drivers/staging/line6/variax.c -+++ b/drivers/staging/line6/variax.c -@@ -308,23 +308,6 @@ static ssize_t variax_set_active(struct device *dev, +Index: linux-3.2.46/drivers/staging/line6/variax.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/variax.c 2013-07-26 19:30:00.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/variax.c 2013-07-26 19:30:01.000000000 +0000 +@@ -308,23 +308,6 @@ } /* @@ -38,7 +38,7 @@ "read" request on "guitar" special file. */ static ssize_t variax_get_guitar(struct device *dev, -@@ -383,7 +366,6 @@ static ssize_t variax_set_raw2(struct device *dev, +@@ -383,7 +366,6 @@ #endif /* Variax workbench special files: */ @@ -46,7 +46,7 @@ static DEVICE_ATTR(active, S_IWUSR | S_IRUGO, variax_get_active, variax_set_active); static DEVICE_ATTR(guitar, S_IRUGO, variax_get_guitar, line6_nop_write); -@@ -422,7 +404,6 @@ static void variax_destruct(struct usb_interface *interface) +@@ -422,7 +404,6 @@ static int variax_create_files2(struct device *dev) { int err; @@ -54,7 +54,7 @@ CHECK_RETURN(device_create_file(dev, &dev_attr_active)); CHECK_RETURN(device_create_file(dev, &dev_attr_guitar)); #ifdef CONFIG_LINE6_USB_RAW -@@ -523,7 +504,6 @@ void line6_variax_disconnect(struct usb_interface *interface) +@@ -523,7 +504,6 @@ if (dev != NULL) { /* remove sysfs entries: */ line6_variax_remove_files(0, 0, dev); diff -Nru linux-3.2.46/debian/patches/features/all/line6/0095-staging-line6-drop-variax-active-sysfs-attr.patch linux-3.2.46/debian/patches/features/all/line6/0095-staging-line6-drop-variax-active-sysfs-attr.patch --- linux-3.2.46/debian/patches/features/all/line6/0095-staging-line6-drop-variax-active-sysfs-attr.patch 2013-02-24 03:52:35.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/line6/0095-staging-line6-drop-variax-active-sysfs-attr.patch 2013-07-26 19:30:04.000000000 +0000 @@ -12,11 +12,11 @@ drivers/staging/line6/variax.c | 36 ------------------------------------ 1 file changed, 36 deletions(-) -diff --git a/drivers/staging/line6/variax.c b/drivers/staging/line6/variax.c -index 0f1846e..4600d24 100644 ---- a/drivers/staging/line6/variax.c -+++ b/drivers/staging/line6/variax.c -@@ -276,38 +276,6 @@ void line6_variax_process_message(struct usb_line6_variax *variax) +Index: linux-3.2.46/drivers/staging/line6/variax.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/variax.c 2013-07-26 19:30:01.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/variax.c 2013-07-26 19:30:03.000000000 +0000 +@@ -276,38 +276,6 @@ } /* @@ -55,7 +55,7 @@ "read" request on "guitar" special file. */ static ssize_t variax_get_guitar(struct device *dev, -@@ -366,8 +334,6 @@ static ssize_t variax_set_raw2(struct device *dev, +@@ -366,8 +334,6 @@ #endif /* Variax workbench special files: */ @@ -64,7 +64,7 @@ static DEVICE_ATTR(guitar, S_IRUGO, variax_get_guitar, line6_nop_write); #ifdef CONFIG_LINE6_USB_RAW -@@ -404,7 +370,6 @@ static void variax_destruct(struct usb_interface *interface) +@@ -404,7 +370,6 @@ static int variax_create_files2(struct device *dev) { int err; @@ -72,7 +72,7 @@ CHECK_RETURN(device_create_file(dev, &dev_attr_guitar)); #ifdef CONFIG_LINE6_USB_RAW CHECK_RETURN(device_create_file(dev, &dev_attr_raw)); -@@ -504,7 +469,6 @@ void line6_variax_disconnect(struct usb_interface *interface) +@@ -504,7 +469,6 @@ if (dev != NULL) { /* remove sysfs entries: */ line6_variax_remove_files(0, 0, dev); diff -Nru linux-3.2.46/debian/patches/features/all/line6/0096-staging-line6-drop-variax-guitar-sysfs-attr.patch linux-3.2.46/debian/patches/features/all/line6/0096-staging-line6-drop-variax-guitar-sysfs-attr.patch --- linux-3.2.46/debian/patches/features/all/line6/0096-staging-line6-drop-variax-guitar-sysfs-attr.patch 2013-02-24 03:52:35.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/line6/0096-staging-line6-drop-variax-guitar-sysfs-attr.patch 2013-07-26 19:30:05.000000000 +0000 @@ -11,11 +11,11 @@ drivers/staging/line6/variax.h | 5 ----- 2 files changed, 27 deletions(-) -diff --git a/drivers/staging/line6/variax.c b/drivers/staging/line6/variax.c -index 4600d24..4db21a3 100644 ---- a/drivers/staging/line6/variax.c -+++ b/drivers/staging/line6/variax.c -@@ -250,11 +250,6 @@ void line6_variax_process_message(struct usb_line6_variax *variax) +Index: linux-3.2.46/drivers/staging/line6/variax.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/variax.c 2013-07-26 19:30:03.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/variax.c 2013-07-26 19:30:04.000000000 +0000 +@@ -250,11 +250,6 @@ sizeof(variax_request_bank) - 2) == 0) { line6_dump_finished(&variax->dumpreq); variax_startup6(variax); @@ -27,7 +27,7 @@ } else if (memcmp(buf + 1, variax_init_version + 1, sizeof(variax_init_version) - 1) == 0) { variax_startup3(variax); -@@ -275,17 +270,6 @@ void line6_variax_process_message(struct usb_line6_variax *variax) +@@ -275,17 +270,6 @@ } } @@ -45,7 +45,7 @@ #ifdef CONFIG_LINE6_USB_RAW static char *variax_alloc_sysex_buffer(struct usb_line6_variax *variax, -@@ -333,9 +317,6 @@ static ssize_t variax_set_raw2(struct device *dev, +@@ -333,9 +317,6 @@ #endif @@ -55,7 +55,7 @@ #ifdef CONFIG_LINE6_USB_RAW static DEVICE_ATTR(raw, S_IWUSR, line6_nop_read, line6_set_raw); static DEVICE_ATTR(raw2, S_IWUSR, line6_nop_read, variax_set_raw2); -@@ -369,8 +350,6 @@ static void variax_destruct(struct usb_interface *interface) +@@ -369,8 +350,6 @@ */ static int variax_create_files2(struct device *dev) { @@ -64,7 +64,7 @@ #ifdef CONFIG_LINE6_USB_RAW CHECK_RETURN(device_create_file(dev, &dev_attr_raw)); CHECK_RETURN(device_create_file(dev, &dev_attr_raw2)); -@@ -469,7 +448,6 @@ void line6_variax_disconnect(struct usb_interface *interface) +@@ -469,7 +448,6 @@ if (dev != NULL) { /* remove sysfs entries: */ line6_variax_remove_files(0, 0, dev); @@ -72,11 +72,11 @@ #ifdef CONFIG_LINE6_USB_RAW device_remove_file(dev, &dev_attr_raw); device_remove_file(dev, &dev_attr_raw2); -diff --git a/drivers/staging/line6/variax.h b/drivers/staging/line6/variax.h -index b5d6a66..f3d95fa 100644 ---- a/drivers/staging/line6/variax.h -+++ b/drivers/staging/line6/variax.h -@@ -83,11 +83,6 @@ struct usb_line6_variax { +Index: linux-3.2.46/drivers/staging/line6/variax.h +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/variax.h 2013-07-26 19:30:00.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/variax.h 2013-07-26 19:30:04.000000000 +0000 +@@ -83,11 +83,6 @@ struct variax_model model_data; /** diff -Nru linux-3.2.46/debian/patches/features/all/line6/0097-staging-line6-drop-variax-raw-sysfs-attrs.patch linux-3.2.46/debian/patches/features/all/line6/0097-staging-line6-drop-variax-raw-sysfs-attrs.patch --- linux-3.2.46/debian/patches/features/all/line6/0097-staging-line6-drop-variax-raw-sysfs-attrs.patch 2013-02-24 03:52:35.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/line6/0097-staging-line6-drop-variax-raw-sysfs-attrs.patch 2013-07-26 19:30:06.000000000 +0000 @@ -13,10 +13,10 @@ drivers/staging/line6/variax.c | 73 ---------------------------------------- 1 file changed, 73 deletions(-) -diff --git a/drivers/staging/line6/variax.c b/drivers/staging/line6/variax.c -index 4db21a3..ff55ad37 100644 ---- a/drivers/staging/line6/variax.c -+++ b/drivers/staging/line6/variax.c +Index: linux-3.2.46/drivers/staging/line6/variax.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/variax.c 2013-07-26 19:30:04.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/variax.c 2013-07-26 19:30:05.000000000 +0000 @@ -16,9 +16,6 @@ #include "driver.h" #include "variax.h" @@ -27,7 +27,7 @@ #define VARIAX_MODEL_HEADER_LENGTH 7 #define VARIAX_MODEL_MESSAGE_LENGTH 199 #define VARIAX_OFFSET_ACTIVATE 7 -@@ -70,7 +67,6 @@ static const char variax_request_model2[] = { +@@ -70,7 +67,6 @@ }; /* forward declarations: */ @@ -35,7 +35,7 @@ static void variax_startup2(unsigned long data); static void variax_startup4(unsigned long data); static void variax_startup5(unsigned long data); -@@ -187,7 +183,6 @@ static void variax_startup7(struct work_struct *work) +@@ -187,7 +183,6 @@ /* device files: */ line6_variax_create_files(0, 0, line6->ifcdev); @@ -43,7 +43,7 @@ } /* -@@ -270,58 +265,6 @@ void line6_variax_process_message(struct usb_line6_variax *variax) +@@ -270,58 +265,6 @@ } } @@ -102,7 +102,7 @@ /* Variax destructor. */ -@@ -346,18 +289,6 @@ static void variax_destruct(struct usb_interface *interface) +@@ -346,18 +289,6 @@ } /* @@ -121,7 +121,7 @@ Try to init workbench device. */ static int variax_try_init(struct usb_interface *interface, -@@ -448,10 +379,6 @@ void line6_variax_disconnect(struct usb_interface *interface) +@@ -448,10 +379,6 @@ if (dev != NULL) { /* remove sysfs entries: */ line6_variax_remove_files(0, 0, dev); diff -Nru linux-3.2.46/debian/patches/features/all/line6/0098-staging-line6-drop-CONFIG_LINE6_USB_RAW.patch linux-3.2.46/debian/patches/features/all/line6/0098-staging-line6-drop-CONFIG_LINE6_USB_RAW.patch --- linux-3.2.46/debian/patches/features/all/line6/0098-staging-line6-drop-CONFIG_LINE6_USB_RAW.patch 2013-02-24 03:52:35.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/line6/0098-staging-line6-drop-CONFIG_LINE6_USB_RAW.patch 2013-07-26 19:30:08.000000000 +0000 @@ -17,11 +17,11 @@ drivers/staging/line6/driver.c | 14 -------------- 2 files changed, 25 deletions(-) -diff --git a/drivers/staging/line6/Kconfig b/drivers/staging/line6/Kconfig -index 80a7202..b635436 100644 ---- a/drivers/staging/line6/Kconfig -+++ b/drivers/staging/line6/Kconfig -@@ -33,17 +33,6 @@ config LINE6_USB_DUMP_PCM +Index: linux-3.2.46/drivers/staging/line6/Kconfig +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/Kconfig 2013-07-26 19:29:16.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/Kconfig 2013-07-26 19:30:07.000000000 +0000 +@@ -33,17 +33,6 @@ If unsure, say N. @@ -39,11 +39,11 @@ config LINE6_USB_IMPULSE_RESPONSE bool "measure impulse response" default n -diff --git a/drivers/staging/line6/driver.c b/drivers/staging/line6/driver.c -index e0e0779..6f07a06c 100644 ---- a/drivers/staging/line6/driver.c -+++ b/drivers/staging/line6/driver.c -@@ -642,20 +642,6 @@ ssize_t line6_nop_write(struct device *dev, struct device_attribute *attr, +Index: linux-3.2.46/drivers/staging/line6/driver.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/driver.c 2013-07-26 19:29:48.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/driver.c 2013-07-26 19:30:07.000000000 +0000 +@@ -642,20 +642,6 @@ } /* diff -Nru linux-3.2.46/debian/patches/features/all/line6/0099-staging-line6-drop-amp-effects-dump-request-triggers.patch linux-3.2.46/debian/patches/features/all/line6/0099-staging-line6-drop-amp-effects-dump-request-triggers.patch --- linux-3.2.46/debian/patches/features/all/line6/0099-staging-line6-drop-amp-effects-dump-request-triggers.patch 2013-02-24 03:52:35.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/line6/0099-staging-line6-drop-amp-effects-dump-request-triggers.patch 2013-07-26 19:30:09.000000000 +0000 @@ -15,11 +15,11 @@ drivers/staging/line6/pod.c | 9 --------- 1 file changed, 9 deletions(-) -diff --git a/drivers/staging/line6/pod.c b/drivers/staging/line6/pod.c -index 157ef68..aa3a547 100644 ---- a/drivers/staging/line6/pod.c -+++ b/drivers/staging/line6/pod.c -@@ -174,12 +174,6 @@ void line6_pod_process_message(struct usb_line6_pod *pod) +Index: linux-3.2.46/drivers/staging/line6/pod.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/pod.c 2013-07-26 19:29:54.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/pod.c 2013-07-26 19:30:08.000000000 +0000 +@@ -174,12 +174,6 @@ /* intentionally no break here! */ case LINE6_PARAM_CHANGE | LINE6_CHANNEL_HOST: @@ -32,7 +32,7 @@ break; case LINE6_PROGRAM_CHANGE | LINE6_CHANNEL_DEVICE: -@@ -288,9 +282,6 @@ void line6_pod_transmit_parameter(struct usb_line6_pod *pod, int param, +@@ -288,9 +282,6 @@ { if (line6_transmit_parameter(&pod->line6, param, value) == 0) pod_store_parameter(pod, param, value); diff -Nru linux-3.2.46/debian/patches/features/all/line6/0100-staging-line6-drop-MIDI-parameter-sysfs-attrs.patch linux-3.2.46/debian/patches/features/all/line6/0100-staging-line6-drop-MIDI-parameter-sysfs-attrs.patch --- linux-3.2.46/debian/patches/features/all/line6/0100-staging-line6-drop-MIDI-parameter-sysfs-attrs.patch 2013-02-24 03:52:35.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/line6/0100-staging-line6-drop-MIDI-parameter-sysfs-attrs.patch 2013-07-26 19:30:10.000000000 +0000 @@ -22,11 +22,11 @@ delete mode 100644 drivers/staging/line6/control.c delete mode 100644 drivers/staging/line6/control.h -diff --git a/drivers/staging/line6/Makefile b/drivers/staging/line6/Makefile -index 34a2dda..44ee5ae 100644 ---- a/drivers/staging/line6/Makefile -+++ b/drivers/staging/line6/Makefile -@@ -3,7 +3,6 @@ obj-$(CONFIG_LINE6_USB) += line6usb.o +Index: linux-3.2.46/drivers/staging/line6/Makefile +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/Makefile 2013-07-26 19:27:59.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/Makefile 2013-07-26 19:30:09.000000000 +0000 +@@ -3,7 +3,6 @@ line6usb-y := \ audio.o \ capture.o \ @@ -34,11 +34,10 @@ driver.o \ dumprequest.o \ midi.o \ -diff --git a/drivers/staging/line6/control.c b/drivers/staging/line6/control.c -deleted file mode 100644 -index f8326f5..0000000 ---- a/drivers/staging/line6/control.c -+++ /dev/null +Index: linux-3.2.46/drivers/staging/line6/control.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/control.c 2013-07-26 19:28:45.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 @@ -1,995 +0,0 @@ -/* - * Line6 Linux USB driver - 0.9.1beta @@ -1035,11 +1034,10 @@ - device_remove_file(dev, &dev_attr_mix1); - device_remove_file(dev, &dev_attr_pickup_wiring); -} -diff --git a/drivers/staging/line6/control.h b/drivers/staging/line6/control.h -deleted file mode 100644 -index e4c5d2c..0000000 ---- a/drivers/staging/line6/control.h -+++ /dev/null +Index: linux-3.2.46/drivers/staging/line6/control.h +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/control.h 2013-07-26 18:52:28.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 @@ -1,195 +0,0 @@ -/* - * Line6 Linux USB driver - 0.9.1beta @@ -1236,10 +1234,10 @@ - struct device *dev); - -#endif -diff --git a/drivers/staging/line6/driver.c b/drivers/staging/line6/driver.c -index 6f07a06c..1e4ce500 100644 ---- a/drivers/staging/line6/driver.c -+++ b/drivers/staging/line6/driver.c +Index: linux-3.2.46/drivers/staging/line6/driver.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/driver.c 2013-07-26 19:30:07.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/driver.c 2013-07-26 19:30:09.000000000 +0000 @@ -16,7 +16,6 @@ #include "audio.h" @@ -1248,10 +1246,10 @@ #include "driver.h" #include "midi.h" #include "playback.h" -diff --git a/drivers/staging/line6/pod.c b/drivers/staging/line6/pod.c -index aa3a547..278976d 100644 ---- a/drivers/staging/line6/pod.c -+++ b/drivers/staging/line6/pod.c +Index: linux-3.2.46/drivers/staging/line6/pod.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/pod.c 2013-07-26 19:30:08.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/pod.c 2013-07-26 19:30:09.000000000 +0000 @@ -15,7 +15,6 @@ #include "audio.h" @@ -1260,7 +1258,7 @@ #include "driver.h" #include "playback.h" #include "pod.h" -@@ -404,10 +403,6 @@ static void pod_startup5(struct work_struct *work) +@@ -404,10 +403,6 @@ /* ALSA audio interface: */ line6_register_audio(line6); @@ -1271,7 +1269,7 @@ } /* POD special files: */ -@@ -594,10 +589,6 @@ void line6_pod_disconnect(struct usb_interface *interface) +@@ -594,10 +589,6 @@ if (dev != NULL) { /* remove sysfs entries: */ @@ -1282,10 +1280,10 @@ device_remove_file(dev, &dev_attr_device_id); device_remove_file(dev, &dev_attr_firmware_version); device_remove_file(dev, &dev_attr_serial_number); -diff --git a/drivers/staging/line6/variax.c b/drivers/staging/line6/variax.c -index ff55ad37..0adba32 100644 ---- a/drivers/staging/line6/variax.c -+++ b/drivers/staging/line6/variax.c +Index: linux-3.2.46/drivers/staging/line6/variax.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/variax.c 2013-07-26 19:30:05.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/variax.c 2013-07-26 19:30:09.000000000 +0000 @@ -12,7 +12,6 @@ #include @@ -1294,7 +1292,7 @@ #include "driver.h" #include "variax.h" -@@ -174,15 +173,11 @@ static void variax_startup7(struct work_struct *work) +@@ -174,15 +173,11 @@ { struct usb_line6_variax *variax = container_of(work, struct usb_line6_variax, startup_work); @@ -1310,7 +1308,7 @@ } /* -@@ -370,16 +365,8 @@ int line6_variax_init(struct usb_interface *interface, +@@ -370,16 +365,8 @@ */ void line6_variax_disconnect(struct usb_interface *interface) { diff -Nru linux-3.2.46/debian/patches/features/all/line6/0101-staging-line6-drop-pod-prog_data-buffers.patch linux-3.2.46/debian/patches/features/all/line6/0101-staging-line6-drop-pod-prog_data-buffers.patch --- linux-3.2.46/debian/patches/features/all/line6/0101-staging-line6-drop-pod-prog_data-buffers.patch 2013-02-24 03:52:35.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/line6/0101-staging-line6-drop-pod-prog_data-buffers.patch 2013-07-26 19:30:12.000000000 +0000 @@ -16,11 +16,11 @@ drivers/staging/line6/pod.h | 25 ----------------------- 2 files changed, 3 insertions(+), 68 deletions(-) -diff --git a/drivers/staging/line6/pod.c b/drivers/staging/line6/pod.c -index 278976d..e892b4a 100644 ---- a/drivers/staging/line6/pod.c -+++ b/drivers/staging/line6/pod.c -@@ -132,14 +132,6 @@ static char *pod_alloc_sysex_buffer(struct usb_line6_pod *pod, int code, +Index: linux-3.2.46/drivers/staging/line6/pod.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/pod.c 2013-07-26 19:30:09.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/pod.c 2013-07-26 19:30:11.000000000 +0000 +@@ -132,14 +132,6 @@ } /* @@ -35,7 +35,7 @@ Handle SAVE button. */ static void pod_save_button_pressed(struct usb_line6_pod *pod, int type, -@@ -169,9 +161,6 @@ void line6_pod_process_message(struct usb_line6_pod *pod) +@@ -169,9 +161,6 @@ /* process all remaining messages */ switch (buf[0]) { case LINE6_PARAM_CHANGE | LINE6_CHANNEL_DEVICE: @@ -45,7 +45,7 @@ case LINE6_PARAM_CHANGE | LINE6_CHANNEL_HOST: break; -@@ -187,36 +176,8 @@ void line6_pod_process_message(struct usb_line6_pod *pod) +@@ -187,36 +176,8 @@ if (memcmp(buf + 1, line6_midi_id, sizeof(line6_midi_id)) == 0) { switch (buf[5]) { case POD_SYSEX_DUMP: @@ -84,7 +84,7 @@ break; case POD_SYSEX_SYSTEM:{ -@@ -279,8 +240,7 @@ void line6_pod_process_message(struct usb_line6_pod *pod) +@@ -279,8 +240,7 @@ void line6_pod_transmit_parameter(struct usb_line6_pod *pod, int param, u8 value) { @@ -94,11 +94,11 @@ } /* -diff --git a/drivers/staging/line6/pod.h b/drivers/staging/line6/pod.h -index 8543bae..52534ca 100644 ---- a/drivers/staging/line6/pod.h -+++ b/drivers/staging/line6/pod.h -@@ -52,21 +52,6 @@ enum { +Index: linux-3.2.46/drivers/staging/line6/pod.h +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/pod.h 2013-07-26 19:29:51.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/pod.h 2013-07-26 19:30:11.000000000 +0000 +@@ -52,21 +52,6 @@ POD_STARTUP_LAST = POD_STARTUP_SETUP - 1 }; @@ -120,7 +120,7 @@ struct usb_line6_pod { /** Generic Line6 USB data. -@@ -79,16 +64,6 @@ struct usb_line6_pod { +@@ -79,16 +64,6 @@ struct line6_dump_request dumpreq; /** diff -Nru linux-3.2.46/debian/patches/features/all/line6/0102-staging-line6-drop-unused-pod-atomic_flags-field.patch linux-3.2.46/debian/patches/features/all/line6/0102-staging-line6-drop-unused-pod-atomic_flags-field.patch --- linux-3.2.46/debian/patches/features/all/line6/0102-staging-line6-drop-unused-pod-atomic_flags-field.patch 2013-02-24 03:52:35.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/line6/0102-staging-line6-drop-unused-pod-atomic_flags-field.patch 2013-07-26 19:30:13.000000000 +0000 @@ -11,11 +11,11 @@ drivers/staging/line6/pod.h | 5 ----- 2 files changed, 16 deletions(-) -diff --git a/drivers/staging/line6/pod.c b/drivers/staging/line6/pod.c -index e892b4a..f8257be 100644 ---- a/drivers/staging/line6/pod.c -+++ b/drivers/staging/line6/pod.c -@@ -132,15 +132,6 @@ static char *pod_alloc_sysex_buffer(struct usb_line6_pod *pod, int code, +Index: linux-3.2.46/drivers/staging/line6/pod.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/pod.c 2013-07-26 19:30:11.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/pod.c 2013-07-26 19:30:12.000000000 +0000 +@@ -132,15 +132,6 @@ } /* @@ -31,7 +31,7 @@ Process a completely received message. */ void line6_pod_process_message(struct usb_line6_pod *pod) -@@ -166,7 +157,6 @@ void line6_pod_process_message(struct usb_line6_pod *pod) +@@ -166,7 +157,6 @@ case LINE6_PROGRAM_CHANGE | LINE6_CHANNEL_DEVICE: case LINE6_PROGRAM_CHANGE | LINE6_CHANNEL_HOST: @@ -39,7 +39,7 @@ line6_dump_request_async(&pod->dumpreq, &pod->line6, 0, LINE6_DUMP_CURRENT); break; -@@ -196,7 +186,6 @@ void line6_pod_process_message(struct usb_line6_pod *pod) +@@ -196,7 +186,6 @@ break; case POD_SYSEX_SAVE: @@ -47,11 +47,11 @@ break; case POD_SYSEX_STORE: -diff --git a/drivers/staging/line6/pod.h b/drivers/staging/line6/pod.h -index 52534ca..843eb4e 100644 ---- a/drivers/staging/line6/pod.h -+++ b/drivers/staging/line6/pod.h -@@ -84,11 +84,6 @@ struct usb_line6_pod { +Index: linux-3.2.46/drivers/staging/line6/pod.h +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/pod.h 2013-07-26 19:30:11.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/pod.h 2013-07-26 19:30:12.000000000 +0000 +@@ -84,11 +84,6 @@ int startup_progress; /** diff -Nru linux-3.2.46/debian/patches/features/all/line6/0103-staging-line6-drop-variax-model_data-field.patch linux-3.2.46/debian/patches/features/all/line6/0103-staging-line6-drop-variax-model_data-field.patch --- linux-3.2.46/debian/patches/features/all/line6/0103-staging-line6-drop-variax-model_data-field.patch 2013-02-24 03:52:35.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/line6/0103-staging-line6-drop-variax-model_data-field.patch 2013-07-26 19:30:14.000000000 +0000 @@ -16,11 +16,11 @@ drivers/staging/line6/variax.h | 20 -------------------- 2 files changed, 47 deletions(-) -diff --git a/drivers/staging/line6/variax.c b/drivers/staging/line6/variax.c -index 0adba32..0262d7d 100644 ---- a/drivers/staging/line6/variax.c -+++ b/drivers/staging/line6/variax.c -@@ -70,21 +70,6 @@ static void variax_startup2(unsigned long data); +Index: linux-3.2.46/drivers/staging/line6/variax.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/variax.c 2013-07-26 19:30:09.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/variax.c 2013-07-26 19:30:14.000000000 +0000 +@@ -70,21 +70,6 @@ static void variax_startup4(unsigned long data); static void variax_startup5(unsigned long data); @@ -42,7 +42,7 @@ static void variax_activate_async(struct usb_line6_variax *variax, int a) { variax->buffer_activate[VARIAX_OFFSET_ACTIVATE] = a; -@@ -214,18 +199,6 @@ void line6_variax_process_message(struct usb_line6_variax *variax) +@@ -214,18 +199,6 @@ break; case VARIAX_DUMP_PASS2: @@ -61,11 +61,11 @@ line6_dump_request_async (&variax->dumpreq, &variax->line6, 2, VARIAX_DUMP_PASS3); -diff --git a/drivers/staging/line6/variax.h b/drivers/staging/line6/variax.h -index f3d95fa..13d5680 100644 ---- a/drivers/staging/line6/variax.h -+++ b/drivers/staging/line6/variax.h -@@ -44,21 +44,6 @@ enum { +Index: linux-3.2.46/drivers/staging/line6/variax.h +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/variax.h 2013-07-26 19:30:04.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/variax.h 2013-07-26 19:30:14.000000000 +0000 +@@ -44,21 +44,6 @@ VARIAX_DUMP_PASS3 }; @@ -87,7 +87,7 @@ struct usb_line6_variax { /** Generic Line6 USB data. -@@ -78,11 +63,6 @@ struct usb_line6_variax { +@@ -78,11 +63,6 @@ unsigned char *buffer_activate; /** diff -Nru linux-3.2.46/debian/patches/features/all/line6/0104-staging-line6-drop-dump-requests-from-variax-startup.patch linux-3.2.46/debian/patches/features/all/line6/0104-staging-line6-drop-dump-requests-from-variax-startup.patch --- linux-3.2.46/debian/patches/features/all/line6/0104-staging-line6-drop-dump-requests-from-variax-startup.patch 2013-02-24 03:52:35.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/line6/0104-staging-line6-drop-dump-requests-from-variax-startup.patch 2013-07-26 19:30:16.000000000 +0000 @@ -15,10 +15,10 @@ drivers/staging/line6/variax.h | 15 ------ 2 files changed, 4 insertions(+), 117 deletions(-) -diff --git a/drivers/staging/line6/variax.c b/drivers/staging/line6/variax.c -index 0262d7d..4fca58f 100644 ---- a/drivers/staging/line6/variax.c -+++ b/drivers/staging/line6/variax.c +Index: linux-3.2.46/drivers/staging/line6/variax.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/variax.c 2013-07-26 19:30:14.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/variax.c 2013-07-26 19:30:15.000000000 +0000 @@ -15,21 +15,10 @@ #include "driver.h" #include "variax.h" @@ -41,7 +41,7 @@ the connected guitar version. */ static const char variax_init_version[] = { -@@ -49,22 +38,6 @@ static const char variax_activate[] = { +@@ -49,22 +38,6 @@ 0xf7 }; @@ -64,7 +64,7 @@ /* forward declarations: */ static void variax_startup2(unsigned long data); static void variax_startup4(unsigned long data); -@@ -135,26 +108,13 @@ static void variax_startup5(unsigned long data) +@@ -135,26 +108,13 @@ { struct usb_line6_variax *variax = (struct usb_line6_variax *)data; CHECK_STARTUP_PROGRESS(variax->startup_progress, @@ -92,7 +92,7 @@ { struct usb_line6_variax *variax = container_of(work, struct usb_line6_variax, startup_work); -@@ -178,8 +138,6 @@ void line6_variax_process_message(struct usb_line6_variax *variax) +@@ -178,8 +138,6 @@ case LINE6_PROGRAM_CHANGE | LINE6_CHANNEL_DEVICE: case LINE6_PROGRAM_CHANGE | LINE6_CHANNEL_HOST: @@ -101,7 +101,7 @@ break; case LINE6_RESET: -@@ -187,41 +145,14 @@ void line6_variax_process_message(struct usb_line6_variax *variax) +@@ -187,41 +145,14 @@ break; case LINE6_SYSEX_BEGIN: @@ -145,7 +145,7 @@ break; case LINE6_SYSEX_END: -@@ -248,11 +179,6 @@ static void variax_destruct(struct usb_interface *interface) +@@ -248,11 +179,6 @@ del_timer(&variax->startup_timer2); cancel_work_sync(&variax->startup_work); @@ -157,7 +157,7 @@ kfree(variax->buffer_activate); } -@@ -266,36 +192,12 @@ static int variax_try_init(struct usb_interface *interface, +@@ -266,36 +192,12 @@ init_timer(&variax->startup_timer1); init_timer(&variax->startup_timer2); @@ -195,10 +195,10 @@ variax->buffer_activate = kmemdup(variax_activate, sizeof(variax_activate), GFP_KERNEL); -diff --git a/drivers/staging/line6/variax.h b/drivers/staging/line6/variax.h -index 13d5680..24de796 100644 ---- a/drivers/staging/line6/variax.h -+++ b/drivers/staging/line6/variax.h +Index: linux-3.2.46/drivers/staging/line6/variax.h +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/variax.h 2013-07-26 19:30:14.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/variax.h 2013-07-26 19:30:15.000000000 +0000 @@ -18,7 +18,6 @@ #include @@ -207,7 +207,7 @@ #define VARIAX_STARTUP_DELAY1 1000 #define VARIAX_STARTUP_DELAY3 100 -@@ -32,18 +31,11 @@ enum { +@@ -32,18 +31,11 @@ VARIAX_STARTUP_VERSIONREQ, VARIAX_STARTUP_WAIT, VARIAX_STARTUP_ACTIVATE, @@ -226,7 +226,7 @@ struct usb_line6_variax { /** Generic Line6 USB data. -@@ -51,13 +43,6 @@ struct usb_line6_variax { +@@ -51,13 +43,6 @@ struct usb_line6 line6; /** diff -Nru linux-3.2.46/debian/patches/features/all/line6/0105-staging-line6-drop-dump-requests-from-pod-startup.patch linux-3.2.46/debian/patches/features/all/line6/0105-staging-line6-drop-dump-requests-from-pod-startup.patch --- linux-3.2.46/debian/patches/features/all/line6/0105-staging-line6-drop-dump-requests-from-pod-startup.patch 2013-02-24 03:52:35.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/line6/0105-staging-line6-drop-dump-requests-from-pod-startup.patch 2013-07-26 19:30:17.000000000 +0000 @@ -15,11 +15,11 @@ drivers/staging/line6/pod.h | 7 ------- 2 files changed, 4 insertions(+), 47 deletions(-) -diff --git a/drivers/staging/line6/pod.c b/drivers/staging/line6/pod.c -index f8257be..e542540 100644 ---- a/drivers/staging/line6/pod.c -+++ b/drivers/staging/line6/pod.c -@@ -111,10 +111,6 @@ static struct line6_pcm_properties pod_pcm_properties = { +Index: linux-3.2.46/drivers/staging/line6/pod.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/pod.c 2013-07-26 19:30:12.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/pod.c 2013-07-26 19:30:16.000000000 +0000 +@@ -111,10 +111,6 @@ .bytes_per_frame = POD_BYTES_PER_FRAME }; @@ -30,7 +30,7 @@ static const char pod_version_header[] = { 0xf2, 0x7e, 0x7f, 0x06, 0x02 }; -@@ -122,7 +118,6 @@ static const char pod_version_header[] = { +@@ -122,7 +118,6 @@ /* forward declarations: */ static void pod_startup2(unsigned long data); static void pod_startup3(struct usb_line6_pod *pod); @@ -38,7 +38,7 @@ static char *pod_alloc_sysex_buffer(struct usb_line6_pod *pod, int code, int size) -@@ -157,8 +152,6 @@ void line6_pod_process_message(struct usb_line6_pod *pod) +@@ -157,8 +152,6 @@ case LINE6_PROGRAM_CHANGE | LINE6_CHANNEL_DEVICE: case LINE6_PROGRAM_CHANGE | LINE6_CHANNEL_HOST: @@ -47,7 +47,7 @@ break; case LINE6_SYSEX_BEGIN | LINE6_CHANNEL_DEVICE: -@@ -166,8 +159,6 @@ void line6_pod_process_message(struct usb_line6_pod *pod) +@@ -166,8 +159,6 @@ if (memcmp(buf + 1, line6_midi_id, sizeof(line6_midi_id)) == 0) { switch (buf[5]) { case POD_SYSEX_DUMP: @@ -56,7 +56,7 @@ break; case POD_SYSEX_SYSTEM:{ -@@ -208,7 +199,7 @@ void line6_pod_process_message(struct usb_line6_pod *pod) +@@ -208,7 +199,7 @@ pod->device_id = ((int)buf[8] << 16) | ((int)buf[9] << 8) | (int) buf[10]; @@ -65,7 +65,7 @@ } else dev_dbg(pod->line6.ifcdev, "unknown sysex header\n"); -@@ -308,22 +299,6 @@ static void pod_startup1(struct usb_line6_pod *pod) +@@ -308,22 +299,6 @@ static void pod_startup2(unsigned long data) { struct usb_line6_pod *pod = (struct usb_line6_pod *)data; @@ -88,7 +88,7 @@ struct usb_line6 *line6 = &pod->line6; CHECK_STARTUP_PROGRESS(pod->startup_progress, POD_STARTUP_VERSIONREQ); -@@ -331,7 +306,7 @@ static void pod_startup3(struct usb_line6_pod *pod) +@@ -331,7 +306,7 @@ line6_version_request_async(line6); } @@ -97,7 +97,7 @@ { CHECK_STARTUP_PROGRESS(pod->startup_progress, POD_STARTUP_WORKQUEUE); -@@ -339,7 +314,7 @@ static void pod_startup4(struct usb_line6_pod *pod) +@@ -339,7 +314,7 @@ schedule_work(&pod->startup_work); } @@ -106,7 +106,7 @@ { struct usb_line6_pod *pod = container_of(work, struct usb_line6_pod, startup_work); -@@ -422,9 +397,6 @@ static void pod_destruct(struct usb_interface *interface) +@@ -422,9 +397,6 @@ del_timer(&pod->startup_timer); cancel_work_sync(&pod->startup_work); @@ -116,7 +116,7 @@ } /* -@@ -450,19 +422,11 @@ static int pod_try_init(struct usb_interface *interface, +@@ -450,19 +422,11 @@ struct usb_line6 *line6 = &pod->line6; init_timer(&pod->startup_timer); @@ -137,10 +137,10 @@ /* create sysfs entries: */ err = pod_create_files2(&interface->dev); if (err < 0) -diff --git a/drivers/staging/line6/pod.h b/drivers/staging/line6/pod.h -index 843eb4e..3e3f167 100644 ---- a/drivers/staging/line6/pod.h -+++ b/drivers/staging/line6/pod.h +Index: linux-3.2.46/drivers/staging/line6/pod.h +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/pod.h 2013-07-26 19:30:12.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/pod.h 2013-07-26 19:30:16.000000000 +0000 @@ -19,7 +19,6 @@ #include @@ -157,7 +157,7 @@ POD_STARTUP_VERSIONREQ, POD_STARTUP_WORKQUEUE, POD_STARTUP_SETUP, -@@ -59,11 +57,6 @@ struct usb_line6_pod { +@@ -59,11 +57,6 @@ struct usb_line6 line6; /** diff -Nru linux-3.2.46/debian/patches/features/all/line6/0106-staging-line6-drop-unused-dumprequest-code.patch linux-3.2.46/debian/patches/features/all/line6/0106-staging-line6-drop-unused-dumprequest-code.patch --- linux-3.2.46/debian/patches/features/all/line6/0106-staging-line6-drop-unused-dumprequest-code.patch 2013-02-24 03:52:35.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/line6/0106-staging-line6-drop-unused-dumprequest-code.patch 2013-07-26 19:30:19.000000000 +0000 @@ -17,11 +17,11 @@ delete mode 100644 drivers/staging/line6/dumprequest.c delete mode 100644 drivers/staging/line6/dumprequest.h -diff --git a/drivers/staging/line6/Makefile b/drivers/staging/line6/Makefile -index 44ee5ae..ae5c374 100644 ---- a/drivers/staging/line6/Makefile -+++ b/drivers/staging/line6/Makefile -@@ -4,7 +4,6 @@ line6usb-y := \ +Index: linux-3.2.46/drivers/staging/line6/Makefile +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/Makefile 2013-07-26 19:30:09.000000000 +0000 ++++ linux-3.2.46/drivers/staging/line6/Makefile 2013-07-26 19:30:18.000000000 +0000 +@@ -4,7 +4,6 @@ audio.o \ capture.o \ driver.o \ @@ -29,11 +29,10 @@ midi.o \ midibuf.o \ pcm.o \ -diff --git a/drivers/staging/line6/dumprequest.c b/drivers/staging/line6/dumprequest.c -deleted file mode 100644 -index 60c7bae..0000000 ---- a/drivers/staging/line6/dumprequest.c -+++ /dev/null +Index: linux-3.2.46/drivers/staging/line6/dumprequest.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/dumprequest.c 2013-07-26 18:52:26.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 @@ -1,135 +0,0 @@ -/* - * Line6 Linux USB driver - 0.9.1beta @@ -170,11 +169,10 @@ - return; - line6_dumpreq_destructbuf(l6dr, 0); -} -diff --git a/drivers/staging/line6/dumprequest.h b/drivers/staging/line6/dumprequest.h -deleted file mode 100644 -index c17a262..0000000 ---- a/drivers/staging/line6/dumprequest.h -+++ /dev/null +Index: linux-3.2.46/drivers/staging/line6/dumprequest.h +=================================================================== +--- linux-3.2.46.orig/drivers/staging/line6/dumprequest.h 2013-07-26 18:52:26.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 @@ -1,76 +0,0 @@ -/* - * Line6 Linux USB driver - 0.9.1beta diff -Nru linux-3.2.46/debian/patches/features/all/net-define-netdev_features_t.patch linux-3.2.46/debian/patches/features/all/net-define-netdev_features_t.patch --- linux-3.2.46/debian/patches/features/all/net-define-netdev_features_t.patch 2013-02-24 03:52:39.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/net-define-netdev_features_t.patch 2013-07-26 19:26:08.000000000 +0000 @@ -7,9 +7,11 @@ This was added by commit c8f44affb7244f2ac3e703cab13d55ede27621bb upstream. --- ---- a/include/linux/netdevice.h -+++ b/include/linux/netdevice.h -@@ -57,6 +57,8 @@ struct netpoll_info; +Index: linux-3.2.46/include/linux/netdevice.h +=================================================================== +--- linux-3.2.46.orig/include/linux/netdevice.h 2013-07-26 19:24:47.000000000 +0000 ++++ linux-3.2.46/include/linux/netdevice.h 2013-07-26 19:26:07.000000000 +0000 +@@ -57,6 +57,8 @@ struct phy_device; /* 802.11 specific */ struct wireless_dev; diff -Nru linux-3.2.46/debian/patches/features/all/net-flow_dissector.c-missing-include-linux-export.h.patch linux-3.2.46/debian/patches/features/all/net-flow_dissector.c-missing-include-linux-export.h.patch --- linux-3.2.46/debian/patches/features/all/net-flow_dissector.c-missing-include-linux-export.h.patch 2013-02-24 03:52:32.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/net-flow_dissector.c-missing-include-linux-export.h.patch 2013-07-26 19:22:31.000000000 +0000 @@ -10,16 +10,13 @@ Signed-off-by: Jesper Dangaard Brouer Signed-off-by: David S. Miller -diff --git a/net/core/flow_dissector.c b/net/core/flow_dissector.c -index 0985b9b..a225089 100644 ---- a/net/core/flow_dissector.c -+++ b/net/core/flow_dissector.c +Index: linux-3.2.46/net/core/flow_dissector.c +=================================================================== +--- linux-3.2.46.orig/net/core/flow_dissector.c 2013-07-26 19:22:28.000000000 +0000 ++++ linux-3.2.46/net/core/flow_dissector.c 2013-07-26 19:22:30.000000000 +0000 @@ -1,4 +1,5 @@ #include +#include #include #include #include --- -1.7.10 - diff -Nru linux-3.2.46/debian/patches/features/all/net-introduce-skb_flow_dissect.patch linux-3.2.46/debian/patches/features/all/net-introduce-skb_flow_dissect.patch --- linux-3.2.46/debian/patches/features/all/net-introduce-skb_flow_dissect.patch 2013-02-24 03:52:33.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/net-introduce-skb_flow_dissect.patch 2013-07-26 19:22:28.000000000 +0000 @@ -16,11 +16,10 @@ Signed-off-by: Eric Dumazet Signed-off-by: David S. Miller -diff --git a/include/net/flow_keys.h b/include/net/flow_keys.h -new file mode 100644 -index 0000000..e4cb285 ---- /dev/null -+++ b/include/net/flow_keys.h +Index: linux-3.2.46/include/net/flow_keys.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/include/net/flow_keys.h 2013-07-26 19:22:27.000000000 +0000 @@ -0,0 +1,15 @@ +#ifndef _NET_FLOW_KEYS_H +#define _NET_FLOW_KEYS_H @@ -37,10 +36,10 @@ + +extern bool skb_flow_dissect(const struct sk_buff *skb, struct flow_keys *flow); +#endif -diff --git a/net/core/Makefile b/net/core/Makefile -index 3606d40..c4ecc86 100644 ---- a/net/core/Makefile -+++ b/net/core/Makefile +Index: linux-3.2.46/net/core/Makefile +=================================================================== +--- linux-3.2.46.orig/net/core/Makefile 2013-07-26 18:54:56.000000000 +0000 ++++ linux-3.2.46/net/core/Makefile 2013-07-26 19:22:27.000000000 +0000 @@ -3,7 +3,7 @@ # @@ -50,11 +49,10 @@ obj-$(CONFIG_SYSCTL) += sysctl_net_core.o -diff --git a/net/core/flow_dissector.c b/net/core/flow_dissector.c -new file mode 100644 -index 0000000..f0516d9 ---- /dev/null -+++ b/net/core/flow_dissector.c +Index: linux-3.2.46/net/core/flow_dissector.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/net/core/flow_dissector.c 2013-07-26 19:22:27.000000000 +0000 @@ -0,0 +1,134 @@ +#include +#include @@ -190,6 +188,3 @@ + return true; +} +EXPORT_SYMBOL(skb_flow_dissect); --- -1.7.10 - diff -Nru linux-3.2.46/debian/patches/features/all/PCI-Add-helper-macro-for-pci_register_driver-boilerp.patch linux-3.2.46/debian/patches/features/all/PCI-Add-helper-macro-for-pci_register_driver-boilerp.patch --- linux-3.2.46/debian/patches/features/all/PCI-Add-helper-macro-for-pci_register_driver-boilerp.patch 2013-02-24 03:52:42.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/PCI-Add-helper-macro-for-pci_register_driver-boilerp.patch 2013-07-26 19:25:49.000000000 +0000 @@ -21,11 +21,11 @@ include/linux/pci.h | 13 +++++++++++++ 1 file changed, 13 insertions(+) -diff --git a/include/linux/pci.h b/include/linux/pci.h -index a16b1df..d4afd70 100644 ---- a/include/linux/pci.h -+++ b/include/linux/pci.h -@@ -946,6 +946,19 @@ int __must_check __pci_register_driver(struct pci_driver *, struct module *, +Index: linux-3.2.46/include/linux/pci.h +=================================================================== +--- linux-3.2.46.orig/include/linux/pci.h 2013-07-26 18:53:45.000000000 +0000 ++++ linux-3.2.46/include/linux/pci.h 2013-07-26 19:25:48.000000000 +0000 +@@ -941,6 +941,19 @@ __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME) void pci_unregister_driver(struct pci_driver *dev); diff -Nru linux-3.2.46/debian/patches/features/all/rt2800-add-chipset-revision-RT5390R-support.patch linux-3.2.46/debian/patches/features/all/rt2800-add-chipset-revision-RT5390R-support.patch --- linux-3.2.46/debian/patches/features/all/rt2800-add-chipset-revision-RT5390R-support.patch 2013-02-24 03:52:42.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/rt2800-add-chipset-revision-RT5390R-support.patch 2013-07-26 19:26:05.000000000 +0000 @@ -25,10 +25,10 @@ drivers/net/wireless/rt2x00/rt2800lib.c | 12 ++++++++++++ 2 files changed, 13 insertions(+) -diff --git a/drivers/net/wireless/rt2x00/rt2800.h b/drivers/net/wireless/rt2x00/rt2800.h -index 1c4d750..d91f4f6 100644 ---- a/drivers/net/wireless/rt2x00/rt2800.h -+++ b/drivers/net/wireless/rt2x00/rt2800.h +Index: linux-3.2.46/drivers/net/wireless/rt2x00/rt2800.h +=================================================================== +--- linux-3.2.46.orig/drivers/net/wireless/rt2x00/rt2800.h 2013-07-26 19:20:49.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rt2x00/rt2800.h 2013-07-26 19:26:04.000000000 +0000 @@ -83,6 +83,7 @@ #define REV_RT3090E 0x0211 #define REV_RT3390E 0x0211 @@ -37,11 +37,11 @@ /* * Signal information. -diff --git a/drivers/net/wireless/rt2x00/rt2800lib.c b/drivers/net/wireless/rt2x00/rt2800lib.c -index bd19802..1cd16b4 100644 ---- a/drivers/net/wireless/rt2x00/rt2800lib.c -+++ b/drivers/net/wireless/rt2x00/rt2800lib.c -@@ -3356,6 +3356,13 @@ static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev) +Index: linux-3.2.46/drivers/net/wireless/rt2x00/rt2800lib.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/wireless/rt2x00/rt2800lib.c 2013-07-26 19:20:49.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rt2x00/rt2800lib.c 2013-07-26 19:26:04.000000000 +0000 +@@ -3185,6 +3185,13 @@ rt2800_register_write(rt2x00dev, GPIO_CTRL_CFG, reg); } @@ -55,7 +55,7 @@ rt2800_bbp_read(rt2x00dev, 152, &value); if (ant == 0) rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1); -@@ -4291,6 +4298,11 @@ int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev) +@@ -4099,6 +4106,11 @@ rt2x00dev->default_ant.rx = ANTENNA_A; } diff -Nru linux-3.2.46/debian/patches/features/all/rt2x00-add-debug-message-for-new-chipset.patch linux-3.2.46/debian/patches/features/all/rt2x00-add-debug-message-for-new-chipset.patch --- linux-3.2.46/debian/patches/features/all/rt2x00-add-debug-message-for-new-chipset.patch 2013-02-24 03:52:33.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/rt2x00-add-debug-message-for-new-chipset.patch 2013-07-26 19:20:48.000000000 +0000 @@ -14,11 +14,11 @@ drivers/net/wireless/rt2x00/rt2800lib.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -diff --git a/drivers/net/wireless/rt2x00/rt2800lib.c b/drivers/net/wireless/rt2x00/rt2800lib.c -index 1ba079dffb11..1ff428ba060e 100644 ---- a/drivers/net/wireless/rt2x00/rt2800lib.c -+++ b/drivers/net/wireless/rt2x00/rt2800lib.c -@@ -3939,7 +3939,7 @@ int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev) +Index: linux-3.2.46/drivers/net/wireless/rt2x00/rt2800lib.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/wireless/rt2x00/rt2800lib.c 2013-07-26 18:55:28.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rt2x00/rt2800lib.c 2013-07-26 19:20:48.000000000 +0000 +@@ -3939,7 +3939,7 @@ !rt2x00_rt(rt2x00dev, RT3390) && !rt2x00_rt(rt2x00dev, RT3572) && !rt2x00_rt(rt2x00dev, RT5390)) { @@ -27,7 +27,7 @@ return -ENODEV; } -@@ -3958,7 +3958,7 @@ int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev) +@@ -3958,7 +3958,7 @@ case RF5390: break; default: @@ -36,6 +36,3 @@ rt2x00dev->chip.rf); return -ENODEV; } --- -1.7.10.2 - diff -Nru linux-3.2.46/debian/patches/features/all/rt2x00-add-rt5372-chipset-support.patch linux-3.2.46/debian/patches/features/all/rt2x00-add-rt5372-chipset-support.patch --- linux-3.2.46/debian/patches/features/all/rt2x00-add-rt5372-chipset-support.patch 2013-02-24 03:52:42.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/rt2x00-add-rt5372-chipset-support.patch 2013-07-26 19:20:50.000000000 +0000 @@ -18,8 +18,10 @@ drivers/net/wireless/rt2x00/rt2x00.h | 1 + 5 files changed, 148 insertions(+), 26 deletions(-) ---- a/drivers/net/wireless/rt2x00/rt2800.h -+++ b/drivers/net/wireless/rt2x00/rt2800.h +Index: linux-3.2.46/drivers/net/wireless/rt2x00/rt2800.h +=================================================================== +--- linux-3.2.46.orig/drivers/net/wireless/rt2x00/rt2800.h 2013-07-26 18:55:28.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rt2x00/rt2800.h 2013-07-26 19:20:49.000000000 +0000 @@ -68,6 +68,7 @@ #define RF3322 0x000c #define RF3853 0x000d @@ -28,9 +30,11 @@ #define RF5390 0x5390 /* ---- a/drivers/net/wireless/rt2x00/rt2800lib.c -+++ b/drivers/net/wireless/rt2x00/rt2800lib.c -@@ -402,7 +402,8 @@ int rt2800_load_firmware(struct rt2x00_d +Index: linux-3.2.46/drivers/net/wireless/rt2x00/rt2800lib.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/wireless/rt2x00/rt2800lib.c 2013-07-26 19:20:48.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rt2x00/rt2800lib.c 2013-07-26 19:20:49.000000000 +0000 +@@ -402,7 +402,8 @@ if (rt2x00_is_pci(rt2x00dev)) { if (rt2x00_rt(rt2x00dev, RT3572) || @@ -40,7 +44,7 @@ rt2800_register_read(rt2x00dev, AUX_CTRL, ®); rt2x00_set_field32(®, AUX_CTRL_FORCE_PCIE_CLK, 1); rt2x00_set_field32(®, AUX_CTRL_WAKE_PCIE_EN, 1); -@@ -1904,7 +1905,8 @@ static void rt2800_config_channel_rf53xx +@@ -1904,7 +1905,8 @@ r55_nonbt_rev[idx]); rt2800_rfcsr_write(rt2x00dev, 59, r59_nonbt_rev[idx]); @@ -50,7 +54,7 @@ static const char r59_non_bt[] = {0x8f, 0x8f, 0x8f, 0x8f, 0x8f, 0x8f, 0x8f, 0x8d, 0x8a, 0x88, 0x88, 0x87, 0x87, 0x86}; -@@ -1951,6 +1953,7 @@ static void rt2800_config_channel(struct +@@ -1951,6 +1953,7 @@ else if (rt2x00_rf(rt2x00dev, RF3052)) rt2800_config_channel_rf3052(rt2x00dev, conf, rf, info); else if (rt2x00_rf(rt2x00dev, RF5370) || @@ -58,7 +62,7 @@ rt2x00_rf(rt2x00dev, RF5390)) rt2800_config_channel_rf53xx(rt2x00dev, conf, rf, info); else -@@ -1965,7 +1968,8 @@ static void rt2800_config_channel(struct +@@ -1965,7 +1968,8 @@ rt2800_bbp_write(rt2x00dev, 86, 0); if (rf->channel <= 14) { @@ -68,7 +72,7 @@ if (test_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags)) { rt2800_bbp_write(rt2x00dev, 82, 0x62); -@@ -2495,7 +2499,8 @@ static u8 rt2800_get_default_vgc(struct +@@ -2495,7 +2499,8 @@ rt2x00_rt(rt2x00dev, RT3071) || rt2x00_rt(rt2x00dev, RT3090) || rt2x00_rt(rt2x00dev, RT3390) || @@ -78,7 +82,7 @@ return 0x1c + (2 * rt2x00dev->lna_gain); else return 0x2e + rt2x00dev->lna_gain; -@@ -2630,7 +2635,8 @@ static int rt2800_init_registers(struct +@@ -2630,7 +2635,8 @@ } else if (rt2x00_rt(rt2x00dev, RT3572)) { rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400); rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606); @@ -88,7 +92,7 @@ rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404); rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606); rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000); -@@ -3006,7 +3012,8 @@ static int rt2800_init_bbp(struct rt2x00 +@@ -3006,7 +3012,8 @@ rt2800_wait_bbp_ready(rt2x00dev))) return -EACCES; @@ -98,7 +102,7 @@ rt2800_bbp_read(rt2x00dev, 4, &value); rt2x00_set_field8(&value, BBP4_MAC_IF_CTRL, 1); rt2800_bbp_write(rt2x00dev, 4, value); -@@ -3014,19 +3021,22 @@ static int rt2800_init_bbp(struct rt2x00 +@@ -3014,19 +3021,22 @@ if (rt2800_is_305x_soc(rt2x00dev) || rt2x00_rt(rt2x00dev, RT3572) || @@ -124,7 +128,7 @@ rt2800_bbp_write(rt2x00dev, 69, 0x12); rt2800_bbp_write(rt2x00dev, 73, 0x13); rt2800_bbp_write(rt2x00dev, 75, 0x46); -@@ -3044,7 +3054,8 @@ static int rt2800_init_bbp(struct rt2x00 +@@ -3044,7 +3054,8 @@ rt2x00_rt(rt2x00dev, RT3090) || rt2x00_rt(rt2x00dev, RT3390) || rt2x00_rt(rt2x00dev, RT3572) || @@ -134,7 +138,7 @@ rt2800_bbp_write(rt2x00dev, 79, 0x13); rt2800_bbp_write(rt2x00dev, 80, 0x05); rt2800_bbp_write(rt2x00dev, 81, 0x33); -@@ -3056,64 +3067,88 @@ static int rt2800_init_bbp(struct rt2x00 +@@ -3056,64 +3067,88 @@ } rt2800_bbp_write(rt2x00dev, 82, 0x62); @@ -231,7 +235,7 @@ rt2800_bbp_read(rt2x00dev, 138, &value); rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom); -@@ -3125,7 +3160,8 @@ static int rt2800_init_bbp(struct rt2x00 +@@ -3125,7 +3160,8 @@ rt2800_bbp_write(rt2x00dev, 138, value); } @@ -241,7 +245,7 @@ int ant, div_mode; rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom); -@@ -3251,13 +3287,15 @@ static int rt2800_init_rfcsr(struct rt2x +@@ -3251,13 +3287,15 @@ !rt2x00_rt(rt2x00dev, RT3390) && !rt2x00_rt(rt2x00dev, RT3572) && !rt2x00_rt(rt2x00dev, RT5390) && @@ -258,7 +262,7 @@ rt2800_rfcsr_read(rt2x00dev, 2, &rfcsr); rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 1); rt2800_rfcsr_write(rt2x00dev, 2, rfcsr); -@@ -3475,6 +3513,66 @@ static int rt2800_init_rfcsr(struct rt2x +@@ -3475,6 +3513,66 @@ rt2800_rfcsr_write(rt2x00dev, 61, 0xdd); rt2800_rfcsr_write(rt2x00dev, 62, 0x00); rt2800_rfcsr_write(rt2x00dev, 63, 0x00); @@ -325,7 +329,7 @@ } if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) { -@@ -3542,7 +3640,8 @@ static int rt2800_init_rfcsr(struct rt2x +@@ -3542,7 +3640,8 @@ rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x15); } @@ -335,7 +339,7 @@ /* * Set back to initial state */ -@@ -3570,7 +3669,8 @@ static int rt2800_init_rfcsr(struct rt2x +@@ -3570,7 +3669,8 @@ rt2x00_set_field32(®, OPT_14_CSR_BIT0, 1); rt2800_register_write(rt2x00dev, OPT_14_CSR, reg); @@ -345,7 +349,7 @@ rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr); rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0); if (rt2x00_rt(rt2x00dev, RT3070) || -@@ -3638,7 +3738,8 @@ static int rt2800_init_rfcsr(struct rt2x +@@ -3638,7 +3738,8 @@ rt2800_rfcsr_write(rt2x00dev, 27, rfcsr); } @@ -355,7 +359,7 @@ rt2800_rfcsr_read(rt2x00dev, 38, &rfcsr); rt2x00_set_field8(&rfcsr, RFCSR38_RX_LO1_EN, 0); rt2800_rfcsr_write(rt2x00dev, 38, rfcsr); -@@ -3922,7 +4023,8 @@ int rt2800_init_eeprom(struct rt2x00_dev +@@ -3922,7 +4023,8 @@ * RT53xx: defined in "EEPROM_CHIP_ID" field */ rt2800_register_read(rt2x00dev, MAC_CSR0, ®); @@ -365,7 +369,7 @@ rt2x00_eeprom_read(rt2x00dev, EEPROM_CHIP_ID, &value); else value = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RF_TYPE); -@@ -3938,7 +4040,8 @@ int rt2800_init_eeprom(struct rt2x00_dev +@@ -3938,7 +4040,8 @@ !rt2x00_rt(rt2x00dev, RT3090) && !rt2x00_rt(rt2x00dev, RT3390) && !rt2x00_rt(rt2x00dev, RT3572) && @@ -375,7 +379,7 @@ ERROR(rt2x00dev, "Invalid RT chipset 0x%04x detected.\n", rt2x00dev->chip.rt); return -ENODEV; } -@@ -3955,6 +4058,7 @@ int rt2800_init_eeprom(struct rt2x00_dev +@@ -3955,6 +4058,7 @@ case RF3052: case RF3320: case RF5370: @@ -383,7 +387,7 @@ case RF5390: break; default: -@@ -4261,6 +4365,7 @@ int rt2800_probe_hw_mode(struct rt2x00_d +@@ -4262,6 +4366,7 @@ rt2x00_rf(rt2x00dev, RF3022) || rt2x00_rf(rt2x00dev, RF3320) || rt2x00_rf(rt2x00dev, RF5370) || @@ -391,9 +395,11 @@ rt2x00_rf(rt2x00dev, RF5390)) { spec->num_channels = 14; spec->channels = rf_vals_3x; ---- a/drivers/net/wireless/rt2x00/rt2800pci.c -+++ b/drivers/net/wireless/rt2x00/rt2800pci.c -@@ -480,7 +480,8 @@ static int rt2800pci_init_registers(stru +Index: linux-3.2.46/drivers/net/wireless/rt2x00/rt2800pci.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/wireless/rt2x00/rt2800pci.c 2013-07-26 18:55:28.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rt2x00/rt2800pci.c 2013-07-26 19:20:49.000000000 +0000 +@@ -480,7 +480,8 @@ if (rt2x00_is_pcie(rt2x00dev) && (rt2x00_rt(rt2x00dev, RT3572) || @@ -403,9 +409,11 @@ rt2x00pci_register_read(rt2x00dev, AUX_CTRL, ®); rt2x00_set_field32(®, AUX_CTRL_FORCE_PCIE_CLK, 1); rt2x00_set_field32(®, AUX_CTRL_WAKE_PCIE_EN, 1); ---- a/drivers/net/wireless/rt2x00/rt2800usb.c -+++ b/drivers/net/wireless/rt2x00/rt2800usb.c -@@ -1133,15 +1133,29 @@ static struct usb_device_id rt2800usb_de +Index: linux-3.2.46/drivers/net/wireless/rt2x00/rt2800usb.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/wireless/rt2x00/rt2800usb.c 2013-07-26 18:55:28.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rt2x00/rt2800usb.c 2013-07-26 19:20:49.000000000 +0000 +@@ -1155,15 +1155,29 @@ { USB_DEVICE(0x5a57, 0x0284) }, #endif #ifdef CONFIG_RT2800USB_RT53XX @@ -435,9 +443,11 @@ #endif #ifdef CONFIG_RT2800USB_UNKNOWN /* ---- a/drivers/net/wireless/rt2x00/rt2x00.h -+++ b/drivers/net/wireless/rt2x00/rt2x00.h -@@ -192,6 +192,7 @@ struct rt2x00_chip { +Index: linux-3.2.46/drivers/net/wireless/rt2x00/rt2x00.h +=================================================================== +--- linux-3.2.46.orig/drivers/net/wireless/rt2x00/rt2x00.h 2013-07-26 18:55:28.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rt2x00/rt2x00.h 2013-07-26 19:20:49.000000000 +0000 +@@ -192,6 +192,7 @@ #define RT3593 0x3593 /* PCIe */ #define RT3883 0x3883 /* WSOC */ #define RT5390 0x5390 /* 2.4GHz */ diff -Nru linux-3.2.46/debian/patches/features/all/rt2x00-Add-RT539b-chipset-support.patch linux-3.2.46/debian/patches/features/all/rt2x00-Add-RT539b-chipset-support.patch --- linux-3.2.46/debian/patches/features/all/rt2x00-Add-RT539b-chipset-support.patch 2013-02-24 03:52:31.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/rt2x00-Add-RT539b-chipset-support.patch 2013-07-26 19:25:16.000000000 +0000 @@ -11,11 +11,11 @@ drivers/net/wireless/rt2x00/rt2800pci.c | 1 + 1 file changed, 1 insertion(+) -diff --git a/drivers/net/wireless/rt2x00/rt2800pci.c b/drivers/net/wireless/rt2x00/rt2800pci.c -index 931331d..cad25bf 100644 ---- a/drivers/net/wireless/rt2x00/rt2800pci.c -+++ b/drivers/net/wireless/rt2x00/rt2800pci.c -@@ -1192,6 +1192,7 @@ static DEFINE_PCI_DEVICE_TABLE(rt2800pci_device_table) = { +Index: linux-3.2.46/drivers/net/wireless/rt2x00/rt2800pci.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/wireless/rt2x00/rt2800pci.c 2013-07-26 19:25:14.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rt2x00/rt2800pci.c 2013-07-26 19:25:15.000000000 +0000 +@@ -1158,6 +1158,7 @@ { PCI_DEVICE(0x1814, 0x5390) }, { PCI_DEVICE(0x1814, 0x5392) }, { PCI_DEVICE(0x1814, 0x539a) }, diff -Nru linux-3.2.46/debian/patches/features/all/sound-pci-cs46xx-request_firmware.patch linux-3.2.46/debian/patches/features/all/sound-pci-cs46xx-request_firmware.patch --- linux-3.2.46/debian/patches/features/all/sound-pci-cs46xx-request_firmware.patch 2013-02-24 03:52:36.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/sound-pci-cs46xx-request_firmware.patch 2013-07-26 19:16:51.000000000 +0000 @@ -6,11 +6,11 @@ Tested by Antonio Ospite . Unfortunately we cannot currently distribute the firmware. -diff --git a/sound/pci/Kconfig b/sound/pci/Kconfig -index 17e03b9..124b3a0 100644 ---- a/sound/pci/Kconfig -+++ b/sound/pci/Kconfig -@@ -229,7 +229,7 @@ config SND_CS4281 +Index: linux-3.2.46/sound/pci/Kconfig +=================================================================== +--- linux-3.2.46.orig/sound/pci/Kconfig 2013-07-26 18:56:43.000000000 +0000 ++++ linux-3.2.46/sound/pci/Kconfig 2013-07-26 19:16:50.000000000 +0000 +@@ -257,7 +257,7 @@ config SND_CS46XX tristate "Cirrus Logic (Sound Fusion) CS4280/CS461x/CS462x/CS463x" @@ -19,7 +19,7 @@ select SND_RAWMIDI select SND_AC97_CODEC help -@@ -241,6 +241,7 @@ config SND_CS46XX +@@ -269,6 +269,7 @@ config SND_CS46XX_NEW_DSP bool "Cirrus Logic (Sound Fusion) New DSP support" @@ -27,10 +27,10 @@ depends on SND_CS46XX default y help -diff --git a/sound/pci/cs46xx/cs46xx_lib.c b/sound/pci/cs46xx/cs46xx_lib.c -index 1be96ea..b12b930 100644 ---- a/sound/pci/cs46xx/cs46xx_lib.c -+++ b/sound/pci/cs46xx/cs46xx_lib.c +Index: linux-3.2.46/sound/pci/cs46xx/cs46xx_lib.c +=================================================================== +--- linux-3.2.46.orig/sound/pci/cs46xx/cs46xx_lib.c 2013-07-26 18:56:43.000000000 +0000 ++++ linux-3.2.46/sound/pci/cs46xx/cs46xx_lib.c 2013-07-26 19:16:50.000000000 +0000 @@ -54,6 +54,8 @@ #include #include @@ -40,7 +40,7 @@ #include -@@ -308,7 +309,7 @@ static void snd_cs46xx_ac97_write(struct snd_ac97 *ac97, +@@ -309,7 +311,7 @@ */ int snd_cs46xx_download(struct snd_cs46xx *chip, @@ -49,7 +49,7 @@ unsigned long offset, unsigned long len) { -@@ -321,9 +322,9 @@ int snd_cs46xx_download(struct snd_cs46xx *chip, +@@ -322,9 +324,9 @@ dst = chip->region.idx[bank+1].remap_addr + offset; len /= sizeof(u32); @@ -61,7 +61,7 @@ dst += sizeof(u32); } return 0; -@@ -360,23 +361,77 @@ int snd_cs46xx_clear_BA1(struct snd_cs46xx *chip, +@@ -361,23 +363,77 @@ #else /* old DSP image */ @@ -150,17 +150,17 @@ #endif /* CONFIG_SND_CS46XX_NEW_DSP */ /* -@@ -3874,3 +3929,5 @@ int __devinit snd_cs46xx_create(struct snd_card *card, +@@ -3880,3 +3936,5 @@ *rchip = chip; return 0; } + +MODULE_FIRMWARE("cs46xx/cs46xx-old.fw"); -diff --git a/sound/pci/cs46xx/cs46xx_lib.h b/sound/pci/cs46xx/cs46xx_lib.h -index 4eb55aa..85babb5 100644 ---- a/sound/pci/cs46xx/cs46xx_lib.h -+++ b/sound/pci/cs46xx/cs46xx_lib.h -@@ -103,8 +103,8 @@ int cs46xx_dsp_proc_done (struct snd_cs46xx *chip); +Index: linux-3.2.46/sound/pci/cs46xx/cs46xx_lib.h +=================================================================== +--- linux-3.2.46.orig/sound/pci/cs46xx/cs46xx_lib.h 2013-07-26 18:56:43.000000000 +0000 ++++ linux-3.2.46/sound/pci/cs46xx/cs46xx_lib.h 2013-07-26 19:16:50.000000000 +0000 +@@ -103,8 +103,8 @@ #define cs46xx_dsp_proc_done(chip) #endif int cs46xx_dsp_scb_and_task_init (struct snd_cs46xx *chip); diff -Nru linux-3.2.46/debian/patches/features/all/USB-Add-helper-macro-for-usb_driver-boilerplate.patch linux-3.2.46/debian/patches/features/all/USB-Add-helper-macro-for-usb_driver-boilerplate.patch --- linux-3.2.46/debian/patches/features/all/USB-Add-helper-macro-for-usb_driver-boilerplate.patch 2013-02-24 03:52:39.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/USB-Add-helper-macro-for-usb_driver-boilerplate.patch 2013-07-26 19:25:48.000000000 +0000 @@ -19,11 +19,11 @@ include/linux/usb.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) -diff --git a/include/linux/usb.h b/include/linux/usb.h -index d3d0c13..5d258c3 100644 ---- a/include/linux/usb.h -+++ b/include/linux/usb.h -@@ -953,6 +953,18 @@ extern int usb_register_driver(struct usb_driver *, struct module *, +Index: linux-3.2.46/include/linux/usb.h +=================================================================== +--- linux-3.2.46.orig/include/linux/usb.h 2013-07-26 19:24:55.000000000 +0000 ++++ linux-3.2.46/include/linux/usb.h 2013-07-26 19:25:47.000000000 +0000 +@@ -995,6 +995,18 @@ extern void usb_deregister(struct usb_driver *); diff -Nru linux-3.2.46/debian/patches/features/all/USB-add-USB_VENDOR_AND_INTERFACE_INFO-macro.patch linux-3.2.46/debian/patches/features/all/USB-add-USB_VENDOR_AND_INTERFACE_INFO-macro.patch --- linux-3.2.46/debian/patches/features/all/USB-add-USB_VENDOR_AND_INTERFACE_INFO-macro.patch 2013-02-24 03:52:32.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/USB-add-USB_VENDOR_AND_INTERFACE_INFO-macro.patch 2013-07-26 19:24:55.000000000 +0000 @@ -22,11 +22,11 @@ include/linux/usb.h | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) -diff --git a/include/linux/usb.h b/include/linux/usb.h -index 873956b..30d1ae3 100644 ---- a/include/linux/usb.h -+++ b/include/linux/usb.h -@@ -861,6 +861,27 @@ static inline int usb_make_path(struct usb_device *dev, char *buf, size_t size) +Index: linux-3.2.46/include/linux/usb.h +=================================================================== +--- linux-3.2.46.orig/include/linux/usb.h 2013-07-26 18:54:06.000000000 +0000 ++++ linux-3.2.46/include/linux/usb.h 2013-07-26 19:24:55.000000000 +0000 +@@ -796,6 +796,27 @@ .bInterfaceSubClass = (sc), \ .bInterfaceProtocol = (pr) diff -Nru linux-3.2.46/debian/patches/features/all/virtio_scsi/0001-SCSI-virtio-scsi-SCSI-driver-for-QEMU-based-virtual-.patch linux-3.2.46/debian/patches/features/all/virtio_scsi/0001-SCSI-virtio-scsi-SCSI-driver-for-QEMU-based-virtual-.patch --- linux-3.2.46/debian/patches/features/all/virtio_scsi/0001-SCSI-virtio-scsi-SCSI-driver-for-QEMU-based-virtual-.patch 2013-02-24 03:52:42.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/virtio_scsi/0001-SCSI-virtio-scsi-SCSI-driver-for-QEMU-based-virtual-.patch 2013-07-26 19:27:41.000000000 +0000 @@ -29,9 +29,11 @@ create mode 100644 drivers/scsi/virtio_scsi.c create mode 100644 include/linux/virtio_scsi.h ---- a/drivers/scsi/Kconfig -+++ b/drivers/scsi/Kconfig -@@ -1910,6 +1910,14 @@ config SCSI_BFA_FC +Index: linux-3.2.46/drivers/scsi/Kconfig +=================================================================== +--- linux-3.2.46.orig/drivers/scsi/Kconfig 2013-07-26 19:19:22.000000000 +0000 ++++ linux-3.2.46/drivers/scsi/Kconfig 2013-07-26 19:27:40.000000000 +0000 +@@ -1910,6 +1910,14 @@ To compile this driver as a module, choose M here. The module will be called bfa. @@ -46,9 +48,11 @@ endif # SCSI_LOWLEVEL source "drivers/scsi/pcmcia/Kconfig" ---- a/drivers/scsi/Makefile -+++ b/drivers/scsi/Makefile -@@ -141,6 +141,7 @@ obj-$(CONFIG_SCSI_CXGB4_ISCSI) += libisc +Index: linux-3.2.46/drivers/scsi/Makefile +=================================================================== +--- linux-3.2.46.orig/drivers/scsi/Makefile 2013-07-26 19:19:22.000000000 +0000 ++++ linux-3.2.46/drivers/scsi/Makefile 2013-07-26 19:27:40.000000000 +0000 +@@ -141,6 +141,7 @@ obj-$(CONFIG_SCSI_BNX2_ISCSI) += libiscsi.o bnx2i/ obj-$(CONFIG_BE2ISCSI) += libiscsi.o be2iscsi/ obj-$(CONFIG_SCSI_PMCRAID) += pmcraid.o @@ -56,8 +60,10 @@ obj-$(CONFIG_VMWARE_PVSCSI) += vmw_pvscsi.o obj-$(CONFIG_HYPERV_STORAGE) += hv_storvsc.o ---- /dev/null -+++ b/drivers/scsi/virtio_scsi.c +Index: linux-3.2.46/drivers/scsi/virtio_scsi.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/scsi/virtio_scsi.c 2013-07-26 19:27:40.000000000 +0000 @@ -0,0 +1,594 @@ +/* + * Virtio SCSI HBA driver @@ -653,8 +659,10 @@ +MODULE_DEVICE_TABLE(virtio, id_table); +MODULE_DESCRIPTION("Virtio SCSI HBA driver"); +MODULE_LICENSE("GPL"); ---- a/include/linux/virtio_ids.h -+++ b/include/linux/virtio_ids.h +Index: linux-3.2.46/include/linux/virtio_ids.h +=================================================================== +--- linux-3.2.46.orig/include/linux/virtio_ids.h 2013-07-26 18:53:10.000000000 +0000 ++++ linux-3.2.46/include/linux/virtio_ids.h 2013-07-26 19:27:40.000000000 +0000 @@ -34,6 +34,7 @@ #define VIRTIO_ID_CONSOLE 3 /* virtio console */ #define VIRTIO_ID_RNG 4 /* virtio ring */ @@ -663,8 +671,10 @@ #define VIRTIO_ID_9P 9 /* 9p virtio console */ #endif /* _LINUX_VIRTIO_IDS_H */ ---- /dev/null -+++ b/include/linux/virtio_scsi.h +Index: linux-3.2.46/include/linux/virtio_scsi.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/include/linux/virtio_scsi.h 2013-07-26 19:27:40.000000000 +0000 @@ -0,0 +1,114 @@ +#ifndef _LINUX_VIRTIO_SCSI_H +#define _LINUX_VIRTIO_SCSI_H diff -Nru linux-3.2.46/debian/patches/features/all/virtio_scsi/0002-SCSI-virtio_scsi-fix-TMF-use-after-free.patch linux-3.2.46/debian/patches/features/all/virtio_scsi/0002-SCSI-virtio_scsi-fix-TMF-use-after-free.patch --- linux-3.2.46/debian/patches/features/all/virtio_scsi/0002-SCSI-virtio_scsi-fix-TMF-use-after-free.patch 2013-02-24 03:52:42.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/virtio_scsi/0002-SCSI-virtio_scsi-fix-TMF-use-after-free.patch 2013-07-26 19:27:42.000000000 +0000 @@ -19,11 +19,11 @@ drivers/scsi/virtio_scsi.c | 24 +++++++++++++----------- 1 file changed, 13 insertions(+), 11 deletions(-) -diff --git a/drivers/scsi/virtio_scsi.c b/drivers/scsi/virtio_scsi.c -index efccd72..1b38431 100644 ---- a/drivers/scsi/virtio_scsi.c -+++ b/drivers/scsi/virtio_scsi.c -@@ -175,7 +175,8 @@ static void virtscsi_complete_free(void *buf) +Index: linux-3.2.46/drivers/scsi/virtio_scsi.c +=================================================================== +--- linux-3.2.46.orig/drivers/scsi/virtio_scsi.c 2013-07-26 19:27:40.000000000 +0000 ++++ linux-3.2.46/drivers/scsi/virtio_scsi.c 2013-07-26 19:27:41.000000000 +0000 +@@ -175,7 +175,8 @@ if (cmd->comp) complete_all(cmd->comp); @@ -33,7 +33,7 @@ } static void virtscsi_ctrl_done(struct virtqueue *vq) -@@ -311,21 +312,22 @@ out: +@@ -311,21 +312,22 @@ static int virtscsi_tmf(struct virtio_scsi *vscsi, struct virtio_scsi_cmd *cmd) { DECLARE_COMPLETION_ONSTACK(comp); diff -Nru linux-3.2.46/debian/patches/features/all/virtio_scsi/0003-SCSI-virtio-scsi-unlock-during-kick.patch linux-3.2.46/debian/patches/features/all/virtio_scsi/0003-SCSI-virtio-scsi-unlock-during-kick.patch --- linux-3.2.46/debian/patches/features/all/virtio_scsi/0003-SCSI-virtio-scsi-unlock-during-kick.patch 2013-02-24 03:52:42.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/virtio_scsi/0003-SCSI-virtio-scsi-unlock-during-kick.patch 2013-07-26 19:27:45.000000000 +0000 @@ -13,9 +13,11 @@ drivers/scsi/virtio_scsi.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) ---- a/drivers/scsi/virtio_scsi.c -+++ b/drivers/scsi/virtio_scsi.c -@@ -264,9 +264,11 @@ static int virtscsi_kick_cmd(struct virt +Index: linux-3.2.46/drivers/scsi/virtio_scsi.c +=================================================================== +--- linux-3.2.46.orig/drivers/scsi/virtio_scsi.c 2013-07-26 19:27:41.000000000 +0000 ++++ linux-3.2.46/drivers/scsi/virtio_scsi.c 2013-07-26 19:27:44.000000000 +0000 +@@ -264,9 +264,11 @@ ret = virtqueue_add_buf_gfp(vq, vscsi->sg, out_num, in_num, cmd, gfp); if (ret >= 0) diff -Nru linux-3.2.46/debian/patches/features/all/virtio_scsi/0004-SCSI-virtio-scsi-split-locking-per-vq.patch linux-3.2.46/debian/patches/features/all/virtio_scsi/0004-SCSI-virtio-scsi-split-locking-per-vq.patch --- linux-3.2.46/debian/patches/features/all/virtio_scsi/0004-SCSI-virtio-scsi-split-locking-per-vq.patch 2013-02-24 03:52:42.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/virtio_scsi/0004-SCSI-virtio-scsi-split-locking-per-vq.patch 2013-07-26 19:27:46.000000000 +0000 @@ -16,9 +16,11 @@ drivers/scsi/virtio_scsi.c | 77 ++++++++++++++++++++++++++++++-------------- 1 file changed, 52 insertions(+), 25 deletions(-) ---- a/drivers/scsi/virtio_scsi.c -+++ b/drivers/scsi/virtio_scsi.c -@@ -43,15 +43,22 @@ struct virtio_scsi_cmd { +Index: linux-3.2.46/drivers/scsi/virtio_scsi.c +=================================================================== +--- linux-3.2.46.orig/drivers/scsi/virtio_scsi.c 2013-07-26 19:27:44.000000000 +0000 ++++ linux-3.2.46/drivers/scsi/virtio_scsi.c 2013-07-26 19:27:45.000000000 +0000 +@@ -43,15 +43,22 @@ } resp; } ____cacheline_aligned_in_smp; @@ -46,7 +48,7 @@ /* For sglist construction when adding commands to the virtqueue. */ struct scatterlist sg[]; -@@ -147,26 +154,25 @@ static void virtscsi_complete_cmd(void * +@@ -147,26 +154,25 @@ static void virtscsi_vq_done(struct virtqueue *vq, void (*fn)(void *buf)) { @@ -79,7 +81,7 @@ }; static void virtscsi_complete_free(void *buf) -@@ -181,12 +187,24 @@ static void virtscsi_complete_free(void +@@ -181,12 +187,24 @@ static void virtscsi_ctrl_done(struct virtqueue *vq) { @@ -104,7 +106,7 @@ }; static void virtscsi_map_sgl(struct scatterlist *sg, unsigned int *p_idx, -@@ -250,7 +268,7 @@ static void virtscsi_map_cmd(struct virt +@@ -250,7 +268,7 @@ *in_num = idx - *out_num; } @@ -113,7 +115,7 @@ struct virtio_scsi_cmd *cmd, size_t req_size, size_t resp_size, gfp_t gfp) { -@@ -258,17 +276,19 @@ static int virtscsi_kick_cmd(struct virt +@@ -258,17 +276,19 @@ unsigned long flags; int ret; @@ -139,7 +141,7 @@ return ret; } -@@ -302,7 +322,7 @@ static int virtscsi_queuecommand(struct +@@ -302,7 +322,7 @@ BUG_ON(sc->cmd_len > VIRTIO_SCSI_CDB_SIZE); memcpy(cmd->req.cmd.cdb, sc->cmnd, sc->cmd_len); @@ -148,7 +150,7 @@ sizeof cmd->req.cmd, sizeof cmd->resp.cmd, GFP_ATOMIC) >= 0) ret = 0; -@@ -317,7 +337,7 @@ static int virtscsi_tmf(struct virtio_sc +@@ -317,7 +337,7 @@ int ret = FAILED; cmd->comp = ∁ @@ -157,7 +159,7 @@ sizeof cmd->req.tmf, sizeof cmd->resp.tmf, GFP_NOIO) < 0) goto out; -@@ -410,6 +430,13 @@ static struct scsi_host_template virtscs +@@ -410,6 +430,13 @@ &__val, sizeof(__val)); \ }) @@ -171,7 +173,7 @@ static int virtscsi_init(struct virtio_device *vdev, struct virtio_scsi *vscsi) { -@@ -431,9 +458,9 @@ static int virtscsi_init(struct virtio_d +@@ -431,9 +458,9 @@ if (err) return err; @@ -184,7 +186,7 @@ virtscsi_config_set(vdev, cdb_size, VIRTIO_SCSI_CDB_SIZE); virtscsi_config_set(vdev, sense_size, VIRTIO_SCSI_SENSE_SIZE); -@@ -466,7 +493,7 @@ static int __devinit virtscsi_probe(stru +@@ -466,7 +493,7 @@ vdev->priv = shost; /* Random initializations. */ diff -Nru linux-3.2.46/debian/patches/features/all/virtio_scsi/0005-SCSI-virtio-scsi-release-sg_lock-after-add_buf.patch linux-3.2.46/debian/patches/features/all/virtio_scsi/0005-SCSI-virtio-scsi-release-sg_lock-after-add_buf.patch --- linux-3.2.46/debian/patches/features/all/virtio_scsi/0005-SCSI-virtio-scsi-release-sg_lock-after-add_buf.patch 2013-02-24 03:52:42.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/virtio_scsi/0005-SCSI-virtio-scsi-release-sg_lock-after-add_buf.patch 2013-07-26 19:27:48.000000000 +0000 @@ -29,11 +29,11 @@ drivers/scsi/virtio_scsi.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -diff --git a/drivers/scsi/virtio_scsi.c b/drivers/scsi/virtio_scsi.c -index 0ecf95e..facfc90 100644 ---- a/drivers/scsi/virtio_scsi.c -+++ b/drivers/scsi/virtio_scsi.c -@@ -281,11 +281,11 @@ static int virtscsi_kick_cmd(struct virtio_scsi *vscsi, struct virtio_scsi_vq *v +Index: linux-3.2.46/drivers/scsi/virtio_scsi.c +=================================================================== +--- linux-3.2.46.orig/drivers/scsi/virtio_scsi.c 2013-07-26 19:27:45.000000000 +0000 ++++ linux-3.2.46/drivers/scsi/virtio_scsi.c 2013-07-26 19:27:47.000000000 +0000 +@@ -281,11 +281,11 @@ spin_lock(&vq->vq_lock); ret = virtqueue_add_buf_gfp(vq->vq, vscsi->sg, out_num, in_num, cmd, gfp); diff -Nru linux-3.2.46/debian/patches/features/all/virtio_scsi/0006-SCSI-virtio-scsi-split-scatterlist-per-target.patch linux-3.2.46/debian/patches/features/all/virtio_scsi/0006-SCSI-virtio-scsi-split-scatterlist-per-target.patch --- linux-3.2.46/debian/patches/features/all/virtio_scsi/0006-SCSI-virtio-scsi-split-scatterlist-per-target.patch 2013-02-24 03:52:42.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/virtio_scsi/0006-SCSI-virtio-scsi-split-scatterlist-per-target.patch 2013-07-26 19:27:49.000000000 +0000 @@ -14,9 +14,11 @@ drivers/scsi/virtio_scsi.c | 141 +++++++++++++++++++++++++++++--------------- 1 file changed, 94 insertions(+), 47 deletions(-) ---- a/drivers/scsi/virtio_scsi.c -+++ b/drivers/scsi/virtio_scsi.c -@@ -50,18 +50,24 @@ struct virtio_scsi_vq { +Index: linux-3.2.46/drivers/scsi/virtio_scsi.c +=================================================================== +--- linux-3.2.46.orig/drivers/scsi/virtio_scsi.c 2013-07-26 19:27:47.000000000 +0000 ++++ linux-3.2.46/drivers/scsi/virtio_scsi.c 2013-07-26 19:27:48.000000000 +0000 +@@ -50,18 +50,24 @@ struct virtqueue *vq; }; @@ -46,7 +48,7 @@ }; static struct kmem_cache *virtscsi_cmd_cache; -@@ -230,25 +236,17 @@ static void virtscsi_map_sgl(struct scat +@@ -230,25 +236,17 @@ * @req_size : size of the request buffer * @resp_size : size of the response buffer * @@ -75,7 +77,7 @@ /* Request header. */ sg_set_buf(&sg[idx++], &cmd->req, req_size); -@@ -268,7 +266,8 @@ static void virtscsi_map_cmd(struct virt +@@ -268,7 +266,8 @@ *in_num = idx - *out_num; } @@ -85,7 +87,7 @@ struct virtio_scsi_cmd *cmd, size_t req_size, size_t resp_size, gfp_t gfp) { -@@ -276,12 +275,12 @@ static int virtscsi_kick_cmd(struct virt +@@ -276,12 +275,12 @@ unsigned long flags; int ret; @@ -102,7 +104,7 @@ if (ret >= 0) ret = virtqueue_kick_prepare(vq->vq); -@@ -295,9 +294,16 @@ static int virtscsi_kick_cmd(struct virt +@@ -295,9 +294,16 @@ static int virtscsi_queuecommand(struct Scsi_Host *sh, struct scsi_cmnd *sc) { struct virtio_scsi *vscsi = shost_priv(sh); @@ -119,7 +121,7 @@ dev_dbg(&sc->device->sdev_gendev, "cmd %p CDB: %#02x\n", sc, sc->cmnd[0]); -@@ -322,7 +328,7 @@ static int virtscsi_queuecommand(struct +@@ -322,7 +328,7 @@ BUG_ON(sc->cmd_len > VIRTIO_SCSI_CDB_SIZE); memcpy(cmd->req.cmd.cdb, sc->cmnd, sc->cmd_len); @@ -128,7 +130,7 @@ sizeof cmd->req.cmd, sizeof cmd->resp.cmd, GFP_ATOMIC) >= 0) ret = 0; -@@ -334,10 +340,11 @@ out: +@@ -334,10 +340,11 @@ static int virtscsi_tmf(struct virtio_scsi *vscsi, struct virtio_scsi_cmd *cmd) { DECLARE_COMPLETION_ONSTACK(comp); @@ -141,7 +143,7 @@ sizeof cmd->req.tmf, sizeof cmd->resp.tmf, GFP_NOIO) < 0) goto out; -@@ -437,11 +444,49 @@ static void virtscsi_init_vq(struct virt +@@ -437,11 +444,49 @@ virtscsi_vq->vq = vq; } @@ -192,7 +194,7 @@ vq_callback_t *callbacks[] = { virtscsi_ctrl_done, virtscsi_event_done, -@@ -464,7 +509,23 @@ static int virtscsi_init(struct virtio_d +@@ -464,7 +509,23 @@ virtscsi_config_set(vdev, cdb_size, VIRTIO_SCSI_CDB_SIZE); virtscsi_config_set(vdev, sense_size, VIRTIO_SCSI_SENSE_SIZE); @@ -217,7 +219,7 @@ } static int __devinit virtscsi_probe(struct virtio_device *vdev) -@@ -472,31 +533,25 @@ static int __devinit virtscsi_probe(stru +@@ -472,31 +533,25 @@ struct Scsi_Host *shost; struct virtio_scsi *vscsi; int err; @@ -255,7 +257,7 @@ if (err) goto virtscsi_init_failed; -@@ -504,7 +559,7 @@ static int __devinit virtscsi_probe(stru +@@ -504,7 +559,7 @@ shost->cmd_per_lun = min_t(u32, cmd_per_lun, shost->can_queue); shost->max_sectors = virtscsi_config_get(vdev, max_sectors) ?: 0xFFFF; shost->max_lun = virtscsi_config_get(vdev, max_lun) + 1; @@ -264,7 +266,7 @@ shost->max_channel = 0; shost->max_cmd_len = VIRTIO_SCSI_CDB_SIZE; err = scsi_add_host(shost, &vdev->dev); -@@ -522,14 +577,6 @@ virtscsi_init_failed: +@@ -522,14 +577,6 @@ return err; } @@ -279,7 +281,7 @@ static void __devexit virtscsi_remove(struct virtio_device *vdev) { struct Scsi_Host *shost = virtio_scsi_host(vdev); -@@ -552,7 +599,7 @@ static int virtscsi_restore(struct virti +@@ -552,7 +599,7 @@ struct Scsi_Host *sh = virtio_scsi_host(vdev); struct virtio_scsi *vscsi = shost_priv(sh); diff -Nru linux-3.2.46/debian/patches/features/all/virtio_scsi/0007-SCSI-virtio-scsi-hotplug-support-for-virtio-scsi.patch linux-3.2.46/debian/patches/features/all/virtio_scsi/0007-SCSI-virtio-scsi-hotplug-support-for-virtio-scsi.patch --- linux-3.2.46/debian/patches/features/all/virtio_scsi/0007-SCSI-virtio-scsi-hotplug-support-for-virtio-scsi.patch 2013-02-24 03:52:42.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/virtio_scsi/0007-SCSI-virtio-scsi-hotplug-support-for-virtio-scsi.patch 2013-07-26 19:27:50.000000000 +0000 @@ -19,8 +19,10 @@ include/linux/virtio_scsi.h | 9 ++++ 2 files changed, 132 insertions(+), 1 deletion(-) ---- a/drivers/scsi/virtio_scsi.c -+++ b/drivers/scsi/virtio_scsi.c +Index: linux-3.2.46/drivers/scsi/virtio_scsi.c +=================================================================== +--- linux-3.2.46.orig/drivers/scsi/virtio_scsi.c 2013-07-26 19:27:48.000000000 +0000 ++++ linux-3.2.46/drivers/scsi/virtio_scsi.c 2013-07-26 19:27:49.000000000 +0000 @@ -25,6 +25,7 @@ #include @@ -29,7 +31,7 @@ /* Command queue element */ struct virtio_scsi_cmd { -@@ -43,6 +44,12 @@ struct virtio_scsi_cmd { +@@ -43,6 +44,12 @@ } resp; } ____cacheline_aligned_in_smp; @@ -42,7 +44,7 @@ struct virtio_scsi_vq { /* Protects vq */ spinlock_t vq_lock; -@@ -67,6 +74,9 @@ struct virtio_scsi { +@@ -67,6 +74,9 @@ struct virtio_scsi_vq event_vq; struct virtio_scsi_vq req_vq; @@ -52,7 +54,7 @@ struct virtio_scsi_target_state *tgt[]; }; -@@ -202,6 +212,105 @@ static void virtscsi_ctrl_done(struct vi +@@ -202,6 +212,105 @@ spin_unlock_irqrestore(&vscsi->ctrl_vq.vq_lock, flags); }; @@ -158,7 +160,7 @@ static void virtscsi_event_done(struct virtqueue *vq) { struct Scsi_Host *sh = virtio_scsi_host(vq->vdev); -@@ -209,7 +318,7 @@ static void virtscsi_event_done(struct v +@@ -209,7 +318,7 @@ unsigned long flags; spin_lock_irqsave(&vscsi->event_vq.vq_lock, flags); @@ -167,7 +169,7 @@ spin_unlock_irqrestore(&vscsi->event_vq.vq_lock, flags); }; -@@ -510,6 +619,9 @@ static int virtscsi_init(struct virtio_d +@@ -510,6 +619,9 @@ virtscsi_config_set(vdev, cdb_size, VIRTIO_SCSI_CDB_SIZE); virtscsi_config_set(vdev, sense_size, VIRTIO_SCSI_SENSE_SIZE); @@ -177,7 +179,7 @@ /* We need to know how many segments before we allocate. */ sg_elems = virtscsi_config_get(vdev, seg_max) ?: 1; -@@ -580,6 +692,10 @@ virtscsi_init_failed: +@@ -580,6 +692,10 @@ static void __devexit virtscsi_remove(struct virtio_device *vdev) { struct Scsi_Host *shost = virtio_scsi_host(vdev); @@ -188,7 +190,7 @@ scsi_remove_host(shost); -@@ -608,7 +724,13 @@ static struct virtio_device_id id_table[ +@@ -608,7 +724,13 @@ { 0 }, }; @@ -202,9 +204,11 @@ .driver.name = KBUILD_MODNAME, .driver.owner = THIS_MODULE, .id_table = id_table, ---- a/include/linux/virtio_scsi.h -+++ b/include/linux/virtio_scsi.h -@@ -69,6 +69,10 @@ struct virtio_scsi_config { +Index: linux-3.2.46/include/linux/virtio_scsi.h +=================================================================== +--- linux-3.2.46.orig/include/linux/virtio_scsi.h 2013-07-26 19:27:40.000000000 +0000 ++++ linux-3.2.46/include/linux/virtio_scsi.h 2013-07-26 19:27:49.000000000 +0000 +@@ -69,6 +69,10 @@ u32 max_lun; } __packed; @@ -215,7 +219,7 @@ /* Response codes */ #define VIRTIO_SCSI_S_OK 0 #define VIRTIO_SCSI_S_OVERRUN 1 -@@ -105,6 +109,11 @@ struct virtio_scsi_config { +@@ -105,6 +109,11 @@ #define VIRTIO_SCSI_T_TRANSPORT_RESET 1 #define VIRTIO_SCSI_T_ASYNC_NOTIFY 2 diff -Nru linux-3.2.46/debian/patches/features/all/virtio_scsi/0008-SCSI-virtio-scsi-Add-vdrv-scan-for-post-VIRTIO_CONFI.patch linux-3.2.46/debian/patches/features/all/virtio_scsi/0008-SCSI-virtio-scsi-Add-vdrv-scan-for-post-VIRTIO_CONFI.patch --- linux-3.2.46/debian/patches/features/all/virtio_scsi/0008-SCSI-virtio-scsi-Add-vdrv-scan-for-post-VIRTIO_CONFI.patch 2013-02-24 03:52:42.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/virtio_scsi/0008-SCSI-virtio-scsi-Add-vdrv-scan-for-post-VIRTIO_CONFI.patch 2013-07-26 19:27:52.000000000 +0000 @@ -27,9 +27,11 @@ include/linux/virtio.h | 1 + 3 files changed, 17 insertions(+), 4 deletions(-) ---- a/drivers/scsi/virtio_scsi.c -+++ b/drivers/scsi/virtio_scsi.c -@@ -571,6 +571,13 @@ static struct virtio_scsi_target_state * +Index: linux-3.2.46/drivers/scsi/virtio_scsi.c +=================================================================== +--- linux-3.2.46.orig/drivers/scsi/virtio_scsi.c 2013-07-26 19:27:49.000000000 +0000 ++++ linux-3.2.46/drivers/scsi/virtio_scsi.c 2013-07-26 19:27:51.000000000 +0000 +@@ -571,6 +571,13 @@ return tgt; } @@ -43,7 +45,7 @@ static void virtscsi_remove_vqs(struct virtio_device *vdev) { struct Scsi_Host *sh = virtio_scsi_host(vdev); -@@ -677,9 +684,10 @@ static int __devinit virtscsi_probe(stru +@@ -677,9 +684,10 @@ err = scsi_add_host(shost, &vdev->dev); if (err) goto scsi_add_host_failed; @@ -57,7 +59,7 @@ return 0; scsi_add_host_failed: -@@ -735,6 +743,7 @@ static struct virtio_driver virtio_scsi_ +@@ -735,6 +743,7 @@ .driver.owner = THIS_MODULE, .id_table = id_table, .probe = virtscsi_probe, @@ -65,9 +67,11 @@ #if 0 .freeze = virtscsi_freeze, .restore = virtscsi_restore, ---- a/drivers/virtio/virtio.c -+++ b/drivers/virtio/virtio.c -@@ -140,8 +140,11 @@ static int virtio_dev_probe(struct devic +Index: linux-3.2.46/drivers/virtio/virtio.c +=================================================================== +--- linux-3.2.46.orig/drivers/virtio/virtio.c 2013-07-26 18:53:07.000000000 +0000 ++++ linux-3.2.46/drivers/virtio/virtio.c 2013-07-26 19:27:51.000000000 +0000 +@@ -140,8 +140,11 @@ err = drv->probe(dev); if (err) add_status(dev, VIRTIO_CONFIG_S_FAILED); @@ -80,9 +84,11 @@ return err; } ---- a/include/linux/virtio.h -+++ b/include/linux/virtio.h -@@ -148,6 +148,7 @@ struct virtio_driver { +Index: linux-3.2.46/include/linux/virtio.h +=================================================================== +--- linux-3.2.46.orig/include/linux/virtio.h 2013-07-26 19:27:43.000000000 +0000 ++++ linux-3.2.46/include/linux/virtio.h 2013-07-26 19:27:51.000000000 +0000 +@@ -148,6 +148,7 @@ const unsigned int *feature_table; unsigned int feature_table_size; int (*probe)(struct virtio_device *dev); diff -Nru linux-3.2.46/debian/patches/features/all/virtio_scsi/0009-SCSI-scsi-virtio-scsi-Fix-address-translation-failur.patch linux-3.2.46/debian/patches/features/all/virtio_scsi/0009-SCSI-scsi-virtio-scsi-Fix-address-translation-failur.patch --- linux-3.2.46/debian/patches/features/all/virtio_scsi/0009-SCSI-scsi-virtio-scsi-Fix-address-translation-failur.patch 2013-02-24 03:52:42.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/virtio_scsi/0009-SCSI-scsi-virtio-scsi-Fix-address-translation-failur.patch 2013-07-26 19:27:53.000000000 +0000 @@ -39,11 +39,11 @@ drivers/scsi/virtio_scsi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -diff --git a/drivers/scsi/virtio_scsi.c b/drivers/scsi/virtio_scsi.c -index c7030fb..3e79a2f 100644 ---- a/drivers/scsi/virtio_scsi.c -+++ b/drivers/scsi/virtio_scsi.c -@@ -331,7 +331,7 @@ static void virtscsi_map_sgl(struct scatterlist *sg, unsigned int *p_idx, +Index: linux-3.2.46/drivers/scsi/virtio_scsi.c +=================================================================== +--- linux-3.2.46.orig/drivers/scsi/virtio_scsi.c 2013-07-26 19:27:51.000000000 +0000 ++++ linux-3.2.46/drivers/scsi/virtio_scsi.c 2013-07-26 19:27:52.000000000 +0000 +@@ -331,7 +331,7 @@ int i; for_each_sg(table->sgl, sg_elem, table->nents, i) diff -Nru linux-3.2.46/debian/patches/features/all/virtio_scsi/0010-SCSI-virtio-scsi-initialize-scatterlist-structure.patch linux-3.2.46/debian/patches/features/all/virtio_scsi/0010-SCSI-virtio-scsi-initialize-scatterlist-structure.patch --- linux-3.2.46/debian/patches/features/all/virtio_scsi/0010-SCSI-virtio-scsi-initialize-scatterlist-structure.patch 2013-02-24 03:52:42.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/virtio_scsi/0010-SCSI-virtio-scsi-initialize-scatterlist-structure.patch 2013-07-26 19:27:54.000000000 +0000 @@ -14,11 +14,11 @@ drivers/scsi/virtio_scsi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -diff --git a/drivers/scsi/virtio_scsi.c b/drivers/scsi/virtio_scsi.c -index 3e79a2f..7554d78 100644 ---- a/drivers/scsi/virtio_scsi.c -+++ b/drivers/scsi/virtio_scsi.c -@@ -219,7 +219,7 @@ static int virtscsi_kick_event(struct virtio_scsi *vscsi, +Index: linux-3.2.46/drivers/scsi/virtio_scsi.c +=================================================================== +--- linux-3.2.46.orig/drivers/scsi/virtio_scsi.c 2013-07-26 19:27:52.000000000 +0000 ++++ linux-3.2.46/drivers/scsi/virtio_scsi.c 2013-07-26 19:27:54.000000000 +0000 +@@ -219,7 +219,7 @@ struct scatterlist sg; unsigned long flags; diff -Nru linux-3.2.46/debian/patches/features/all/virtio_scsi/0011-SCSI-virtio-scsi-fix-LUNs-greater-than-255.patch linux-3.2.46/debian/patches/features/all/virtio_scsi/0011-SCSI-virtio-scsi-fix-LUNs-greater-than-255.patch --- linux-3.2.46/debian/patches/features/all/virtio_scsi/0011-SCSI-virtio-scsi-fix-LUNs-greater-than-255.patch 2013-02-24 03:52:42.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/virtio_scsi/0011-SCSI-virtio-scsi-fix-LUNs-greater-than-255.patch 2013-07-26 19:27:56.000000000 +0000 @@ -16,11 +16,11 @@ drivers/scsi/virtio_scsi.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) -diff --git a/drivers/scsi/virtio_scsi.c b/drivers/scsi/virtio_scsi.c -index 7554d78..a7cf726 100644 ---- a/drivers/scsi/virtio_scsi.c -+++ b/drivers/scsi/virtio_scsi.c -@@ -677,7 +677,11 @@ static int __devinit virtscsi_probe(struct virtio_device *vdev) +Index: linux-3.2.46/drivers/scsi/virtio_scsi.c +=================================================================== +--- linux-3.2.46.orig/drivers/scsi/virtio_scsi.c 2013-07-26 19:27:54.000000000 +0000 ++++ linux-3.2.46/drivers/scsi/virtio_scsi.c 2013-07-26 19:27:55.000000000 +0000 +@@ -677,7 +677,11 @@ cmd_per_lun = virtscsi_config_get(vdev, cmd_per_lun) ?: 1; shost->cmd_per_lun = min_t(u32, cmd_per_lun, shost->can_queue); shost->max_sectors = virtscsi_config_get(vdev, max_sectors) ?: 0xFFFF; diff -Nru linux-3.2.46/debian/patches/features/all/virtio_scsi/0012-SCSI-virtio-scsi-support-online-resizing-of-disks.patch linux-3.2.46/debian/patches/features/all/virtio_scsi/0012-SCSI-virtio-scsi-support-online-resizing-of-disks.patch --- linux-3.2.46/debian/patches/features/all/virtio_scsi/0012-SCSI-virtio-scsi-support-online-resizing-of-disks.patch 2013-02-24 03:52:42.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/virtio_scsi/0012-SCSI-virtio-scsi-support-online-resizing-of-disks.patch 2013-07-26 19:27:57.000000000 +0000 @@ -18,11 +18,11 @@ include/linux/virtio_scsi.h | 2 ++ 2 files changed, 32 insertions(+), 1 deletion(-) -diff --git a/drivers/scsi/virtio_scsi.c b/drivers/scsi/virtio_scsi.c -index a7cf726..595af1a 100644 ---- a/drivers/scsi/virtio_scsi.c -+++ b/drivers/scsi/virtio_scsi.c -@@ -279,6 +279,31 @@ static void virtscsi_handle_transport_reset(struct virtio_scsi *vscsi, +Index: linux-3.2.46/drivers/scsi/virtio_scsi.c +=================================================================== +--- linux-3.2.46.orig/drivers/scsi/virtio_scsi.c 2013-07-26 19:27:55.000000000 +0000 ++++ linux-3.2.46/drivers/scsi/virtio_scsi.c 2013-07-26 19:27:56.000000000 +0000 +@@ -279,6 +279,31 @@ } } @@ -54,7 +54,7 @@ static void virtscsi_handle_event(struct work_struct *work) { struct virtio_scsi_event_node *event_node = -@@ -297,6 +322,9 @@ static void virtscsi_handle_event(struct work_struct *work) +@@ -297,6 +322,9 @@ case VIRTIO_SCSI_T_TRANSPORT_RESET: virtscsi_handle_transport_reset(vscsi, event); break; @@ -64,7 +64,7 @@ default: pr_err("Unsupport virtio scsi event %x\n", event->event); } -@@ -737,7 +765,8 @@ static struct virtio_device_id id_table[] = { +@@ -737,7 +765,8 @@ }; static unsigned int features[] = { @@ -74,11 +74,11 @@ }; static struct virtio_driver virtio_scsi_driver = { -diff --git a/include/linux/virtio_scsi.h b/include/linux/virtio_scsi.h -index dc8d305..d6b4440 100644 ---- a/include/linux/virtio_scsi.h -+++ b/include/linux/virtio_scsi.h -@@ -72,6 +72,7 @@ struct virtio_scsi_config { +Index: linux-3.2.46/include/linux/virtio_scsi.h +=================================================================== +--- linux-3.2.46.orig/include/linux/virtio_scsi.h 2013-07-26 19:27:49.000000000 +0000 ++++ linux-3.2.46/include/linux/virtio_scsi.h 2013-07-26 19:27:56.000000000 +0000 +@@ -72,6 +72,7 @@ /* Feature Bits */ #define VIRTIO_SCSI_F_INOUT 0 #define VIRTIO_SCSI_F_HOTPLUG 1 @@ -86,7 +86,7 @@ /* Response codes */ #define VIRTIO_SCSI_S_OK 0 -@@ -108,6 +109,7 @@ struct virtio_scsi_config { +@@ -108,6 +109,7 @@ #define VIRTIO_SCSI_T_NO_EVENT 0 #define VIRTIO_SCSI_T_TRANSPORT_RESET 1 #define VIRTIO_SCSI_T_ASYNC_NOTIFY 2 diff -Nru linux-3.2.46/debian/patches/features/all/virtio_scsi/virtio-support-unlocked-queue-kick.patch linux-3.2.46/debian/patches/features/all/virtio_scsi/virtio-support-unlocked-queue-kick.patch --- linux-3.2.46/debian/patches/features/all/virtio_scsi/virtio-support-unlocked-queue-kick.patch 2013-02-24 03:52:42.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/virtio_scsi/virtio-support-unlocked-queue-kick.patch 2013-07-26 19:27:44.000000000 +0000 @@ -27,9 +27,11 @@ include/linux/virtio.h | 4 +++ 2 files changed, 52 insertions(+), 12 deletions(-) ---- a/drivers/virtio/virtio_ring.c -+++ b/drivers/virtio/virtio_ring.c -@@ -245,10 +245,23 @@ add_head: +Index: linux-3.2.46/drivers/virtio/virtio_ring.c +=================================================================== +--- linux-3.2.46.orig/drivers/virtio/virtio_ring.c 2013-07-26 18:53:10.000000000 +0000 ++++ linux-3.2.46/drivers/virtio/virtio_ring.c 2013-07-26 19:27:43.000000000 +0000 +@@ -245,10 +245,23 @@ } EXPORT_SYMBOL_GPL(virtqueue_add_buf_gfp); @@ -54,7 +56,7 @@ START_USE(vq); /* Descriptors and available array need to be set before we expose the * new available array entries. */ -@@ -261,13 +274,46 @@ void virtqueue_kick(struct virtqueue *_v +@@ -261,13 +274,46 @@ /* Need to update avail index before checking if we should notify */ virtio_mb(); @@ -107,9 +109,11 @@ } EXPORT_SYMBOL_GPL(virtqueue_kick); ---- a/include/linux/virtio.h -+++ b/include/linux/virtio.h -@@ -90,6 +90,10 @@ static inline int virtqueue_add_buf(stru +Index: linux-3.2.46/include/linux/virtio.h +=================================================================== +--- linux-3.2.46.orig/include/linux/virtio.h 2013-07-26 18:53:10.000000000 +0000 ++++ linux-3.2.46/include/linux/virtio.h 2013-07-26 19:27:43.000000000 +0000 +@@ -90,6 +90,10 @@ void virtqueue_kick(struct virtqueue *vq); diff -Nru linux-3.2.46/debian/patches/features/all/wacom/0001-Input-wacom-cleanup-feature-report-for-bamboos.patch linux-3.2.46/debian/patches/features/all/wacom/0001-Input-wacom-cleanup-feature-report-for-bamboos.patch --- linux-3.2.46/debian/patches/features/all/wacom/0001-Input-wacom-cleanup-feature-report-for-bamboos.patch 2013-02-24 03:52:33.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/wacom/0001-Input-wacom-cleanup-feature-report-for-bamboos.patch 2013-07-26 19:20:08.000000000 +0000 @@ -20,11 +20,11 @@ drivers/input/tablet/wacom_sys.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) -diff --git a/drivers/input/tablet/wacom_sys.c b/drivers/input/tablet/wacom_sys.c -index 1c1b7b43cf92..8669096a8ea1 100644 ---- a/drivers/input/tablet/wacom_sys.c -+++ b/drivers/input/tablet/wacom_sys.c -@@ -66,7 +66,8 @@ static int wacom_get_report(struct usb_interface *intf, u8 type, u8 id, +Index: linux-3.2.46/drivers/input/tablet/wacom_sys.c +=================================================================== +--- linux-3.2.46.orig/drivers/input/tablet/wacom_sys.c 2013-07-26 18:55:40.000000000 +0000 ++++ linux-3.2.46/drivers/input/tablet/wacom_sys.c 2013-07-26 19:20:08.000000000 +0000 +@@ -66,7 +66,8 @@ do { retval = usb_control_msg(dev, usb_rcvctrlpipe(dev, 0), USB_REQ_GET_REPORT, @@ -34,7 +34,7 @@ (type << 8) + id, intf->altsetting[0].desc.bInterfaceNumber, buf, size, 100); -@@ -348,7 +349,8 @@ static int wacom_query_tablet_data(struct usb_interface *intf, struct wacom_feat +@@ -348,7 +349,8 @@ WAC_HID_FEATURE_REPORT, report_id, rep_data, 4, 1); } while ((error < 0 || rep_data[1] != 4) && limit++ < WAC_MSG_RETRIES); @@ -44,6 +44,3 @@ do { rep_data[0] = 2; rep_data[1] = 2; --- -1.7.10.1 - diff -Nru linux-3.2.46/debian/patches/features/all/wacom/0002-Input-wacom-remove-unused-bamboo-HID-parsing.patch linux-3.2.46/debian/patches/features/all/wacom/0002-Input-wacom-remove-unused-bamboo-HID-parsing.patch --- linux-3.2.46/debian/patches/features/all/wacom/0002-Input-wacom-remove-unused-bamboo-HID-parsing.patch 2013-02-24 03:52:33.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/wacom/0002-Input-wacom-remove-unused-bamboo-HID-parsing.patch 2013-07-26 19:20:10.000000000 +0000 @@ -16,11 +16,11 @@ drivers/input/tablet/wacom_sys.c | 4 ---- 1 file changed, 4 deletions(-) -diff --git a/drivers/input/tablet/wacom_sys.c b/drivers/input/tablet/wacom_sys.c -index 8669096a8ea1..f3dfb827437a 100644 ---- a/drivers/input/tablet/wacom_sys.c -+++ b/drivers/input/tablet/wacom_sys.c -@@ -245,8 +245,6 @@ static int wacom_parse_hid(struct usb_interface *intf, struct hid_descriptor *hi +Index: linux-3.2.46/drivers/input/tablet/wacom_sys.c +=================================================================== +--- linux-3.2.46.orig/drivers/input/tablet/wacom_sys.c 2013-07-26 19:20:08.000000000 +0000 ++++ linux-3.2.46/drivers/input/tablet/wacom_sys.c 2013-07-26 19:20:09.000000000 +0000 +@@ -245,8 +245,6 @@ /* penabled only accepts exact bytes of data */ if (features->type == TABLETPC2FG) features->pktlen = WACOM_PKGLEN_GRAPHIRE; @@ -29,7 +29,7 @@ features->device_type = BTN_TOOL_PEN; features->x_max = get_unaligned_le16(&report[i + 3]); -@@ -288,8 +286,6 @@ static int wacom_parse_hid(struct usb_interface *intf, struct hid_descriptor *hi +@@ -288,8 +286,6 @@ /* penabled only accepts exact bytes of data */ if (features->type == TABLETPC2FG) features->pktlen = WACOM_PKGLEN_GRAPHIRE; @@ -38,6 +38,3 @@ features->device_type = BTN_TOOL_PEN; features->y_max = get_unaligned_le16(&report[i + 3]); --- -1.7.10.1 - diff -Nru linux-3.2.46/debian/patches/features/all/wacom/0003-Input-wacom-add-some-comments-to-wacom_parse_hid.patch linux-3.2.46/debian/patches/features/all/wacom/0003-Input-wacom-add-some-comments-to-wacom_parse_hid.patch --- linux-3.2.46/debian/patches/features/all/wacom/0003-Input-wacom-add-some-comments-to-wacom_parse_hid.patch 2013-02-24 03:52:33.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/wacom/0003-Input-wacom-add-some-comments-to-wacom_parse_hid.patch 2013-07-26 19:20:11.000000000 +0000 @@ -12,11 +12,11 @@ drivers/input/tablet/wacom_sys.c | 37 ++++++++++++++++++++++++++++++++++++- 1 file changed, 36 insertions(+), 1 deletion(-) -diff --git a/drivers/input/tablet/wacom_sys.c b/drivers/input/tablet/wacom_sys.c -index f3dfb827437a..e648f9ac4d82 100644 ---- a/drivers/input/tablet/wacom_sys.c -+++ b/drivers/input/tablet/wacom_sys.c -@@ -165,7 +165,37 @@ static void wacom_close(struct input_dev *dev) +Index: linux-3.2.46/drivers/input/tablet/wacom_sys.c +=================================================================== +--- linux-3.2.46.orig/drivers/input/tablet/wacom_sys.c 2013-07-26 19:20:09.000000000 +0000 ++++ linux-3.2.46/drivers/input/tablet/wacom_sys.c 2013-07-26 19:20:10.000000000 +0000 +@@ -165,7 +165,37 @@ usb_autopm_put_interface(wacom->intf); } @@ -55,7 +55,7 @@ struct wacom_features *features) { struct usb_device *dev = interface_to_usbdev(intf); -@@ -299,6 +329,11 @@ static int wacom_parse_hid(struct usb_interface *intf, struct hid_descriptor *hi +@@ -299,6 +329,11 @@ i++; break; @@ -67,6 +67,3 @@ case HID_USAGE_STYLUS: pen = 1; i++; --- -1.7.10.1 - diff -Nru linux-3.2.46/debian/patches/features/all/wacom/0005-Input-wacom-read-3rd-gen-Bamboo-Touch-HID-data.patch linux-3.2.46/debian/patches/features/all/wacom/0005-Input-wacom-read-3rd-gen-Bamboo-Touch-HID-data.patch --- linux-3.2.46/debian/patches/features/all/wacom/0005-Input-wacom-read-3rd-gen-Bamboo-Touch-HID-data.patch 2013-02-24 03:52:33.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/wacom/0005-Input-wacom-read-3rd-gen-Bamboo-Touch-HID-data.patch 2013-07-26 19:20:12.000000000 +0000 @@ -20,10 +20,10 @@ drivers/input/tablet/wacom_wac.h | 1 + 2 files changed, 48 insertions(+), 2 deletions(-) -diff --git a/drivers/input/tablet/wacom_sys.c b/drivers/input/tablet/wacom_sys.c -index e648f9ac4d82..2fe21d1a18b7 100644 ---- a/drivers/input/tablet/wacom_sys.c -+++ b/drivers/input/tablet/wacom_sys.c +Index: linux-3.2.46/drivers/input/tablet/wacom_sys.c +=================================================================== +--- linux-3.2.46.orig/drivers/input/tablet/wacom_sys.c 2013-07-26 19:20:10.000000000 +0000 ++++ linux-3.2.46/drivers/input/tablet/wacom_sys.c 2013-07-26 19:20:11.000000000 +0000 @@ -28,7 +28,9 @@ #define HID_USAGE_Y_TILT 0x3e #define HID_USAGE_FINGER 0x22 @@ -35,7 +35,7 @@ enum { WCM_UNDEFINED = 0, -@@ -165,6 +167,35 @@ static void wacom_close(struct input_dev *dev) +@@ -165,6 +167,35 @@ usb_autopm_put_interface(wacom->intf); } @@ -71,7 +71,7 @@ /* * Interface Descriptor of wacom devices can be incomplete and * inconsistent so wacom_features table is used to store stylus -@@ -193,6 +224,10 @@ static void wacom_close(struct input_dev *dev) +@@ -193,6 +224,10 @@ * X/Y maximum as well as the physical size of tablet. Since touch * interfaces haven't supported pressure or distance, this is enough * information to override invalid values in the wacom_features table. @@ -82,7 +82,7 @@ */ static int wacom_parse_hid(struct usb_interface *intf, struct hid_descriptor *hid_desc, -@@ -341,10 +376,20 @@ static int wacom_parse_hid(struct usb_interface *intf, +@@ -341,10 +376,20 @@ } break; @@ -104,10 +104,10 @@ } } -diff --git a/drivers/input/tablet/wacom_wac.h b/drivers/input/tablet/wacom_wac.h -index 53eb71b68330..af94e6d9d6a9 100644 ---- a/drivers/input/tablet/wacom_wac.h -+++ b/drivers/input/tablet/wacom_wac.h +Index: linux-3.2.46/drivers/input/tablet/wacom_wac.h +=================================================================== +--- linux-3.2.46.orig/drivers/input/tablet/wacom_wac.h 2013-07-26 18:55:39.000000000 +0000 ++++ linux-3.2.46/drivers/input/tablet/wacom_wac.h 2013-07-26 19:20:11.000000000 +0000 @@ -22,6 +22,7 @@ #define WACOM_PKGLEN_TPC1FG 5 #define WACOM_PKGLEN_TPC2FG 14 @@ -116,6 +116,3 @@ /* device IDs */ #define STYLUS_DEVICE_ID 0x02 --- -1.7.10.1 - diff -Nru linux-3.2.46/debian/patches/features/all/wacom/0006-Input-wacom-3rd-gen-Bamboo-P-Touch-packet-support.patch linux-3.2.46/debian/patches/features/all/wacom/0006-Input-wacom-3rd-gen-Bamboo-P-Touch-packet-support.patch --- linux-3.2.46/debian/patches/features/all/wacom/0006-Input-wacom-3rd-gen-Bamboo-P-Touch-packet-support.patch 2013-02-24 03:52:33.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/wacom/0006-Input-wacom-3rd-gen-Bamboo-P-Touch-packet-support.patch 2013-07-26 19:20:14.000000000 +0000 @@ -21,11 +21,11 @@ drivers/input/tablet/wacom_wac.h | 3 +- 2 files changed, 92 insertions(+), 5 deletions(-) -diff --git a/drivers/input/tablet/wacom_wac.c b/drivers/input/tablet/wacom_wac.c -index f00c70e1adb0..c456ab04efcf 100644 ---- a/drivers/input/tablet/wacom_wac.c -+++ b/drivers/input/tablet/wacom_wac.c -@@ -837,6 +837,64 @@ static int wacom_bpt_touch(struct wacom_wac *wacom) +Index: linux-3.2.46/drivers/input/tablet/wacom_wac.c +=================================================================== +--- linux-3.2.46.orig/drivers/input/tablet/wacom_wac.c 2013-07-26 18:55:39.000000000 +0000 ++++ linux-3.2.46/drivers/input/tablet/wacom_wac.c 2013-07-26 19:20:13.000000000 +0000 +@@ -837,6 +837,64 @@ return 0; } @@ -90,7 +90,7 @@ static int wacom_bpt_pen(struct wacom_wac *wacom) { struct input_dev *input = wacom->input; -@@ -907,7 +965,9 @@ static int wacom_bpt_irq(struct wacom_wac *wacom, size_t len) +@@ -907,7 +965,9 @@ { if (len == WACOM_PKGLEN_BBTOUCH) return wacom_bpt_touch(wacom); @@ -101,7 +101,7 @@ return wacom_bpt_pen(wacom); return 0; -@@ -1026,9 +1086,9 @@ void wacom_setup_device_quirks(struct wacom_features *features) +@@ -1026,9 +1086,9 @@ features->type == BAMBOO_PT) features->quirks |= WACOM_QUIRK_MULTI_INPUT; @@ -113,7 +113,7 @@ features->x_max <<= 5; features->y_max <<= 5; features->x_fuzz <<= 5; -@@ -1235,7 +1295,21 @@ void wacom_setup_input_capabilities(struct input_dev *input_dev, +@@ -1235,7 +1295,21 @@ __set_bit(BTN_TOOL_FINGER, input_dev->keybit); __set_bit(BTN_TOOL_DOUBLETAP, input_dev->keybit); @@ -136,7 +136,7 @@ input_set_abs_params(input_dev, ABS_MT_POSITION_X, 0, features->x_max, features->x_fuzz, 0); -@@ -1504,6 +1578,15 @@ static const struct wacom_features wacom_features_0xDA = +@@ -1504,6 +1578,15 @@ static struct wacom_features wacom_features_0xDB = { "Wacom Bamboo 2FG 6x8 SE", WACOM_PKGLEN_BBFUN, 21648, 13700, 1023, 31, BAMBOO_PT, WACOM_INTUOS_RES, WACOM_INTUOS_RES }; @@ -152,7 +152,7 @@ static const struct wacom_features wacom_features_0x6004 = { "ISD-V4", WACOM_PKGLEN_GRAPHIRE, 12800, 8000, 255, 0, TABLETPC, WACOM_INTUOS_RES, WACOM_INTUOS_RES }; -@@ -1599,6 +1682,9 @@ const struct usb_device_id wacom_ids[] = { +@@ -1599,6 +1682,9 @@ { USB_DEVICE_WACOM(0xD8) }, { USB_DEVICE_WACOM(0xDA) }, { USB_DEVICE_WACOM(0xDB) }, @@ -162,10 +162,10 @@ { USB_DEVICE_WACOM(0xF0) }, { USB_DEVICE_WACOM(0xCC) }, { USB_DEVICE_WACOM(0x90) }, -diff --git a/drivers/input/tablet/wacom_wac.h b/drivers/input/tablet/wacom_wac.h -index af94e6d9d6a9..27f1d1c203a1 100644 ---- a/drivers/input/tablet/wacom_wac.h -+++ b/drivers/input/tablet/wacom_wac.h +Index: linux-3.2.46/drivers/input/tablet/wacom_wac.h +=================================================================== +--- linux-3.2.46.orig/drivers/input/tablet/wacom_wac.h 2013-07-26 19:20:11.000000000 +0000 ++++ linux-3.2.46/drivers/input/tablet/wacom_wac.h 2013-07-26 19:20:13.000000000 +0000 @@ -12,7 +12,7 @@ #include @@ -183,6 +183,3 @@ /* device IDs */ #define STYLUS_DEVICE_ID 0x02 --- -1.7.10.1 - diff -Nru linux-3.2.46/debian/patches/features/all/wacom/0007-Input-wacom-ignore-unwanted-bamboo-packets.patch linux-3.2.46/debian/patches/features/all/wacom/0007-Input-wacom-ignore-unwanted-bamboo-packets.patch --- linux-3.2.46/debian/patches/features/all/wacom/0007-Input-wacom-ignore-unwanted-bamboo-packets.patch 2013-02-24 03:52:33.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/wacom/0007-Input-wacom-ignore-unwanted-bamboo-packets.patch 2013-07-26 19:20:15.000000000 +0000 @@ -24,11 +24,11 @@ drivers/input/tablet/wacom_wac.c | 9 +++++++++ 1 file changed, 9 insertions(+) -diff --git a/drivers/input/tablet/wacom_wac.c b/drivers/input/tablet/wacom_wac.c -index c456ab04efcf..551f3a3156dc 100644 ---- a/drivers/input/tablet/wacom_wac.c -+++ b/drivers/input/tablet/wacom_wac.c -@@ -799,6 +799,9 @@ static int wacom_bpt_touch(struct wacom_wac *wacom) +Index: linux-3.2.46/drivers/input/tablet/wacom_wac.c +=================================================================== +--- linux-3.2.46.orig/drivers/input/tablet/wacom_wac.c 2013-07-26 19:20:13.000000000 +0000 ++++ linux-3.2.46/drivers/input/tablet/wacom_wac.c 2013-07-26 19:20:14.000000000 +0000 +@@ -799,6 +799,9 @@ unsigned char *data = wacom->data; int i; @@ -38,7 +38,7 @@ for (i = 0; i < 2; i++) { int offset = (data[1] & 0x80) ? (8 * i) : (9 * i); bool touch = data[offset + 3] & 0x80; -@@ -876,6 +879,9 @@ static int wacom_bpt3_touch(struct wacom_wac *wacom) +@@ -876,6 +879,9 @@ int count = data[1] & 0x03; int i; @@ -48,7 +48,7 @@ /* data has up to 7 fixed sized 8-byte messages starting at data[2] */ for (i = 0; i < count; i++) { int offset = (8 * i) + 2; -@@ -901,6 +907,9 @@ static int wacom_bpt_pen(struct wacom_wac *wacom) +@@ -901,6 +907,9 @@ unsigned char *data = wacom->data; int prox = 0, x = 0, y = 0, p = 0, d = 0, pen = 0, btn1 = 0, btn2 = 0; @@ -58,6 +58,3 @@ prox = (data[1] & 0x20) == 0x20; /* --- -1.7.10.1 - diff -Nru linux-3.2.46/debian/patches/features/all/wacom/0008-Input-wacom-add-support-for-Cintiq-24HD.patch linux-3.2.46/debian/patches/features/all/wacom/0008-Input-wacom-add-support-for-Cintiq-24HD.patch --- linux-3.2.46/debian/patches/features/all/wacom/0008-Input-wacom-add-support-for-Cintiq-24HD.patch 2013-02-24 03:52:33.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/wacom/0008-Input-wacom-add-support-for-Cintiq-24HD.patch 2013-07-26 19:20:16.000000000 +0000 @@ -20,11 +20,11 @@ drivers/input/tablet/wacom_wac.h | 1 + 2 files changed, 77 insertions(+), 1 deletion(-) -diff --git a/drivers/input/tablet/wacom_wac.c b/drivers/input/tablet/wacom_wac.c -index 551f3a3156dc..88672ec296c1 100644 ---- a/drivers/input/tablet/wacom_wac.c -+++ b/drivers/input/tablet/wacom_wac.c -@@ -452,7 +452,7 @@ static void wacom_intuos_general(struct wacom_wac *wacom) +Index: linux-3.2.46/drivers/input/tablet/wacom_wac.c +=================================================================== +--- linux-3.2.46.orig/drivers/input/tablet/wacom_wac.c 2013-07-26 19:20:14.000000000 +0000 ++++ linux-3.2.46/drivers/input/tablet/wacom_wac.c 2013-07-26 19:20:15.000000000 +0000 +@@ -452,7 +452,7 @@ if ((data[1] & 0xb8) == 0xa0) { t = (data[6] << 2) | ((data[7] >> 6) & 3); if ((features->type >= INTUOS4S && features->type <= INTUOS4L) || @@ -33,7 +33,7 @@ t = (t << 1) | (data[1] & 1); } input_report_abs(input, ABS_PRESSURE, t); -@@ -519,6 +519,56 @@ static int wacom_intuos_irq(struct wacom_wac *wacom) +@@ -519,6 +519,56 @@ input_report_key(input, wacom->tool[1], 0); input_report_abs(input, ABS_MISC, 0); } @@ -90,7 +90,7 @@ } else { if (features->type == WACOM_21UX2) { input_report_key(input, BTN_0, (data[5] & 0x01)); -@@ -1019,6 +1069,7 @@ void wacom_wac_irq(struct wacom_wac *wacom_wac, size_t len) +@@ -1019,6 +1069,7 @@ case CINTIQ: case WACOM_BEE: case WACOM_21UX2: @@ -98,7 +98,7 @@ sync = wacom_intuos_irq(wacom_wac); break; -@@ -1174,6 +1225,26 @@ void wacom_setup_input_capabilities(struct input_dev *input_dev, +@@ -1174,6 +1225,26 @@ __set_bit(INPUT_PROP_POINTER, input_dev->propbit); break; @@ -125,7 +125,7 @@ case WACOM_21UX2: __set_bit(BTN_A, input_dev->keybit); __set_bit(BTN_B, input_dev->keybit); -@@ -1503,6 +1574,9 @@ static const struct wacom_features wacom_features_0xBB = +@@ -1503,6 +1574,9 @@ static const struct wacom_features wacom_features_0xBC = { "Wacom Intuos4 WL", WACOM_PKGLEN_INTUOS, 40840, 25400, 2047, 63, INTUOS4, WACOM_INTUOS3_RES, WACOM_INTUOS3_RES }; @@ -135,7 +135,7 @@ static const struct wacom_features wacom_features_0x3F = { "Wacom Cintiq 21UX", WACOM_PKGLEN_INTUOS, 87200, 65600, 1023, 63, CINTIQ, WACOM_INTUOS3_RES, WACOM_INTUOS3_RES }; -@@ -1706,6 +1780,7 @@ const struct usb_device_id wacom_ids[] = { +@@ -1706,6 +1780,7 @@ { USB_DEVICE_WACOM(0xE6) }, { USB_DEVICE_WACOM(0xEC) }, { USB_DEVICE_WACOM(0x47) }, @@ -143,11 +143,11 @@ { USB_DEVICE_LENOVO(0x6004) }, { } }; -diff --git a/drivers/input/tablet/wacom_wac.h b/drivers/input/tablet/wacom_wac.h -index 27f1d1c203a1..050acaefee7d 100644 ---- a/drivers/input/tablet/wacom_wac.h -+++ b/drivers/input/tablet/wacom_wac.h -@@ -59,6 +59,7 @@ enum { +Index: linux-3.2.46/drivers/input/tablet/wacom_wac.h +=================================================================== +--- linux-3.2.46.orig/drivers/input/tablet/wacom_wac.h 2013-07-26 19:20:13.000000000 +0000 ++++ linux-3.2.46/drivers/input/tablet/wacom_wac.h 2013-07-26 19:20:15.000000000 +0000 +@@ -59,6 +59,7 @@ INTUOS4S, INTUOS4, INTUOS4L, @@ -155,6 +155,3 @@ WACOM_21UX2, CINTIQ, WACOM_BEE, --- -1.7.10.1 - diff -Nru linux-3.2.46/debian/patches/features/all/wacom/0009-Input-wacom-add-LED-support-for-Cintiq-24HD.patch linux-3.2.46/debian/patches/features/all/wacom/0009-Input-wacom-add-LED-support-for-Cintiq-24HD.patch --- linux-3.2.46/debian/patches/features/all/wacom/0009-Input-wacom-add-LED-support-for-Cintiq-24HD.patch 2013-02-24 03:52:33.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/wacom/0009-Input-wacom-add-LED-support-for-Cintiq-24HD.patch 2013-07-26 19:20:18.000000000 +0000 @@ -18,11 +18,11 @@ drivers/input/tablet/wacom_sys.c | 5 ++++- 2 files changed, 13 insertions(+), 9 deletions(-) -diff --git a/Documentation/ABI/testing/sysfs-driver-wacom b/Documentation/ABI/testing/sysfs-driver-wacom -index 82d4df136444..0130d6683c14 100644 ---- a/Documentation/ABI/testing/sysfs-driver-wacom -+++ b/Documentation/ABI/testing/sysfs-driver-wacom -@@ -15,9 +15,9 @@ Contact: linux-input@vger.kernel.org +Index: linux-3.2.46/Documentation/ABI/testing/sysfs-driver-wacom +=================================================================== +--- linux-3.2.46.orig/Documentation/ABI/testing/sysfs-driver-wacom 2013-07-26 18:55:38.000000000 +0000 ++++ linux-3.2.46/Documentation/ABI/testing/sysfs-driver-wacom 2013-07-26 19:20:17.000000000 +0000 +@@ -15,9 +15,9 @@ Description: Attribute group for control of the status LEDs and the OLEDs. This attribute group is only available for Intuos 4 M, L, @@ -35,7 +35,7 @@ What: /sys/bus/usb/devices/-:./wacom_led/status0_luminance Date: August 2011 -@@ -41,16 +41,17 @@ Date: August 2011 +@@ -41,16 +41,17 @@ Contact: linux-input@vger.kernel.org Description: Writing to this file sets which one of the four (for Intuos 4) @@ -58,11 +58,11 @@ What: /sys/bus/usb/devices/-:./wacom_led/buttons_luminance Date: August 2011 -diff --git a/drivers/input/tablet/wacom_sys.c b/drivers/input/tablet/wacom_sys.c -index 2fe21d1a18b7..7e63183a6c68 100644 ---- a/drivers/input/tablet/wacom_sys.c -+++ b/drivers/input/tablet/wacom_sys.c -@@ -563,7 +563,8 @@ static int wacom_led_control(struct wacom *wacom) +Index: linux-3.2.46/drivers/input/tablet/wacom_sys.c +=================================================================== +--- linux-3.2.46.orig/drivers/input/tablet/wacom_sys.c 2013-07-26 19:20:11.000000000 +0000 ++++ linux-3.2.46/drivers/input/tablet/wacom_sys.c 2013-07-26 19:20:17.000000000 +0000 +@@ -563,7 +563,8 @@ if (!buf) return -ENOMEM; @@ -72,7 +72,7 @@ led = (wacom->led.select[1] << 4) | 0x40; led |= wacom->led.select[0] | 0x4; -@@ -782,6 +783,7 @@ static int wacom_initialize_leds(struct wacom *wacom) +@@ -782,6 +783,7 @@ &intuos4_led_attr_group); break; @@ -80,7 +80,7 @@ case WACOM_21UX2: wacom->led.select[0] = 0; wacom->led.select[1] = 0; -@@ -816,6 +818,7 @@ static void wacom_destroy_leds(struct wacom *wacom) +@@ -816,6 +818,7 @@ &intuos4_led_attr_group); break; @@ -88,6 +88,3 @@ case WACOM_21UX2: sysfs_remove_group(&wacom->intf->dev.kobj, &cintiq_led_attr_group); --- -1.7.10.1 - diff -Nru linux-3.2.46/debian/patches/features/all/wacom/0010-Input-wacom-use-BTN_TOOL_FINGER-to-indicate-touch-de.patch linux-3.2.46/debian/patches/features/all/wacom/0010-Input-wacom-use-BTN_TOOL_FINGER-to-indicate-touch-de.patch --- linux-3.2.46/debian/patches/features/all/wacom/0010-Input-wacom-use-BTN_TOOL_FINGER-to-indicate-touch-de.patch 2013-02-24 03:52:33.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/wacom/0010-Input-wacom-use-BTN_TOOL_FINGER-to-indicate-touch-de.patch 2013-07-26 19:20:19.000000000 +0000 @@ -14,11 +14,11 @@ drivers/input/tablet/wacom_wac.c | 4 ++-- 2 files changed, 3 insertions(+), 7 deletions(-) -diff --git a/drivers/input/tablet/wacom_sys.c b/drivers/input/tablet/wacom_sys.c -index 7e63183a6c68..c9588eececfb 100644 ---- a/drivers/input/tablet/wacom_sys.c -+++ b/drivers/input/tablet/wacom_sys.c -@@ -176,7 +176,7 @@ static int wacom_parse_logical_collection(unsigned char *report, +Index: linux-3.2.46/drivers/input/tablet/wacom_sys.c +=================================================================== +--- linux-3.2.46.orig/drivers/input/tablet/wacom_sys.c 2013-07-26 19:20:17.000000000 +0000 ++++ linux-3.2.46/drivers/input/tablet/wacom_sys.c 2013-07-26 19:20:18.000000000 +0000 +@@ -176,7 +176,7 @@ /* Logical collection is only used by 3rd gen Bamboo Touch */ features->pktlen = WACOM_PKGLEN_BBTOUCH3; @@ -27,7 +27,7 @@ /* * Stylus and Touch have same active area -@@ -286,12 +286,10 @@ static int wacom_parse_hid(struct usb_interface *intf, +@@ -286,12 +286,10 @@ if (features->type == TABLETPC2FG) { /* need to reset back */ features->pktlen = WACOM_PKGLEN_TPC2FG; @@ -40,7 +40,7 @@ features->x_phy = get_unaligned_le16(&report[i + 5]); features->x_max = -@@ -325,7 +323,6 @@ static int wacom_parse_hid(struct usb_interface *intf, +@@ -325,7 +323,6 @@ if (features->type == TABLETPC2FG) { /* need to reset back */ features->pktlen = WACOM_PKGLEN_TPC2FG; @@ -48,7 +48,7 @@ features->y_max = get_unaligned_le16(&report[i + 3]); features->y_phy = -@@ -334,7 +331,6 @@ static int wacom_parse_hid(struct usb_interface *intf, +@@ -334,7 +331,6 @@ } else if (features->type == BAMBOO_PT) { /* need to reset back */ features->pktlen = WACOM_PKGLEN_BBTOUCH; @@ -56,11 +56,11 @@ features->y_phy = get_unaligned_le16(&report[i + 3]); features->y_max = -diff --git a/drivers/input/tablet/wacom_wac.c b/drivers/input/tablet/wacom_wac.c -index 88672ec296c1..3c9f4b8cfe8f 100644 ---- a/drivers/input/tablet/wacom_wac.c -+++ b/drivers/input/tablet/wacom_wac.c -@@ -1317,7 +1317,7 @@ void wacom_setup_input_capabilities(struct input_dev *input_dev, +Index: linux-3.2.46/drivers/input/tablet/wacom_wac.c +=================================================================== +--- linux-3.2.46.orig/drivers/input/tablet/wacom_wac.c 2013-07-26 19:20:15.000000000 +0000 ++++ linux-3.2.46/drivers/input/tablet/wacom_wac.c 2013-07-26 19:20:18.000000000 +0000 +@@ -1317,7 +1317,7 @@ break; case TABLETPC2FG: @@ -69,7 +69,7 @@ input_mt_init_slots(input_dev, 2); input_set_abs_params(input_dev, ABS_MT_TOOL_TYPE, -@@ -1366,7 +1366,7 @@ void wacom_setup_input_capabilities(struct input_dev *input_dev, +@@ -1366,7 +1366,7 @@ __set_bit(INPUT_PROP_POINTER, input_dev->propbit); @@ -78,6 +78,3 @@ __set_bit(BTN_LEFT, input_dev->keybit); __set_bit(BTN_FORWARD, input_dev->keybit); __set_bit(BTN_BACK, input_dev->keybit); --- -1.7.10.1 - diff -Nru linux-3.2.46/debian/patches/features/all/wacom/0011-Input-wacom-use-switch-statement-for-wacom_tpc_irq.patch linux-3.2.46/debian/patches/features/all/wacom/0011-Input-wacom-use-switch-statement-for-wacom_tpc_irq.patch --- linux-3.2.46/debian/patches/features/all/wacom/0011-Input-wacom-use-switch-statement-for-wacom_tpc_irq.patch 2013-02-24 03:52:33.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/wacom/0011-Input-wacom-use-switch-statement-for-wacom_tpc_irq.patch 2013-07-26 19:20:21.000000000 +0000 @@ -16,11 +16,11 @@ drivers/input/tablet/wacom_wac.h | 2 ++ 2 files changed, 20 insertions(+), 6 deletions(-) -diff --git a/drivers/input/tablet/wacom_wac.c b/drivers/input/tablet/wacom_wac.c -index 3c9f4b8cfe8f..07a1f218b5c1 100644 ---- a/drivers/input/tablet/wacom_wac.c -+++ b/drivers/input/tablet/wacom_wac.c -@@ -832,12 +832,24 @@ static int wacom_tpc_irq(struct wacom_wac *wacom, size_t len) +Index: linux-3.2.46/drivers/input/tablet/wacom_wac.c +=================================================================== +--- linux-3.2.46.orig/drivers/input/tablet/wacom_wac.c 2013-07-26 19:20:18.000000000 +0000 ++++ linux-3.2.46/drivers/input/tablet/wacom_wac.c 2013-07-26 19:20:20.000000000 +0000 +@@ -832,12 +832,24 @@ dbg("wacom_tpc_irq: received report #%d", data[0]); @@ -51,10 +51,10 @@ return 0; } -diff --git a/drivers/input/tablet/wacom_wac.h b/drivers/input/tablet/wacom_wac.h -index 050acaefee7d..4f0ba21b0196 100644 ---- a/drivers/input/tablet/wacom_wac.h -+++ b/drivers/input/tablet/wacom_wac.h +Index: linux-3.2.46/drivers/input/tablet/wacom_wac.h +=================================================================== +--- linux-3.2.46.orig/drivers/input/tablet/wacom_wac.h 2013-07-26 19:20:15.000000000 +0000 ++++ linux-3.2.46/drivers/input/tablet/wacom_wac.h 2013-07-26 19:20:20.000000000 +0000 @@ -39,6 +39,8 @@ #define WACOM_REPORT_INTUOSPAD 12 #define WACOM_REPORT_TPC1FG 6 @@ -64,6 +64,3 @@ /* device quirks */ #define WACOM_QUIRK_MULTI_INPUT 0x0001 --- -1.7.10.1 - diff -Nru linux-3.2.46/debian/patches/features/all/wacom/0012-Input-wacom-add-missing-LEDS_CLASS-to-Kconfig.patch linux-3.2.46/debian/patches/features/all/wacom/0012-Input-wacom-add-missing-LEDS_CLASS-to-Kconfig.patch --- linux-3.2.46/debian/patches/features/all/wacom/0012-Input-wacom-add-missing-LEDS_CLASS-to-Kconfig.patch 2013-02-24 03:52:33.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/wacom/0012-Input-wacom-add-missing-LEDS_CLASS-to-Kconfig.patch 2013-07-26 19:20:22.000000000 +0000 @@ -11,11 +11,11 @@ drivers/input/tablet/Kconfig | 2 ++ 1 file changed, 2 insertions(+) -diff --git a/drivers/input/tablet/Kconfig b/drivers/input/tablet/Kconfig -index 58a87755b936..e53f4081a586 100644 ---- a/drivers/input/tablet/Kconfig -+++ b/drivers/input/tablet/Kconfig -@@ -77,6 +77,8 @@ config TABLET_USB_WACOM +Index: linux-3.2.46/drivers/input/tablet/Kconfig +=================================================================== +--- linux-3.2.46.orig/drivers/input/tablet/Kconfig 2013-07-26 18:55:36.000000000 +0000 ++++ linux-3.2.46/drivers/input/tablet/Kconfig 2013-07-26 19:20:21.000000000 +0000 +@@ -77,6 +77,8 @@ tristate "Wacom Intuos/Graphire tablet support (USB)" depends on USB_ARCH_HAS_HCD select USB @@ -24,6 +24,3 @@ help Say Y here if you want to use the USB version of the Wacom Intuos or Graphire tablet. Make sure to say Y to "Mouse support" --- -1.7.10.1 - diff -Nru linux-3.2.46/debian/patches/features/all/wacom/0013-Input-wacom-fix-3rd-gen-Bamboo-MT-when-4-fingers-are.patch linux-3.2.46/debian/patches/features/all/wacom/0013-Input-wacom-fix-3rd-gen-Bamboo-MT-when-4-fingers-are.patch --- linux-3.2.46/debian/patches/features/all/wacom/0013-Input-wacom-fix-3rd-gen-Bamboo-MT-when-4-fingers-are.patch 2013-02-24 03:52:33.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/wacom/0013-Input-wacom-fix-3rd-gen-Bamboo-MT-when-4-fingers-are.patch 2013-07-26 19:20:23.000000000 +0000 @@ -14,11 +14,11 @@ drivers/input/tablet/wacom_wac.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -diff --git a/drivers/input/tablet/wacom_wac.c b/drivers/input/tablet/wacom_wac.c -index 07a1f218b5c1..89a96427faa0 100644 ---- a/drivers/input/tablet/wacom_wac.c -+++ b/drivers/input/tablet/wacom_wac.c -@@ -938,7 +938,7 @@ static int wacom_bpt3_touch(struct wacom_wac *wacom) +Index: linux-3.2.46/drivers/input/tablet/wacom_wac.c +=================================================================== +--- linux-3.2.46.orig/drivers/input/tablet/wacom_wac.c 2013-07-26 19:20:20.000000000 +0000 ++++ linux-3.2.46/drivers/input/tablet/wacom_wac.c 2013-07-26 19:20:22.000000000 +0000 +@@ -938,7 +938,7 @@ { struct input_dev *input = wacom->input; unsigned char *data = wacom->data; @@ -27,6 +27,3 @@ int i; if (data[0] != 0x02) --- -1.7.10.1 - diff -Nru linux-3.2.46/debian/patches/features/all/wacom/0014-Input-wacom-fix-physical-size-calculation-for-3rd-ge.patch linux-3.2.46/debian/patches/features/all/wacom/0014-Input-wacom-fix-physical-size-calculation-for-3rd-ge.patch --- linux-3.2.46/debian/patches/features/all/wacom/0014-Input-wacom-fix-physical-size-calculation-for-3rd-ge.patch 2013-02-24 03:52:33.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/wacom/0014-Input-wacom-fix-physical-size-calculation-for-3rd-ge.patch 2013-07-26 19:20:24.000000000 +0000 @@ -21,11 +21,11 @@ drivers/input/tablet/wacom_sys.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -diff --git a/drivers/input/tablet/wacom_sys.c b/drivers/input/tablet/wacom_sys.c -index c9588eececfb..dc07821fdae3 100644 ---- a/drivers/input/tablet/wacom_sys.c -+++ b/drivers/input/tablet/wacom_sys.c -@@ -184,9 +184,9 @@ static int wacom_parse_logical_collection(unsigned char *report, +Index: linux-3.2.46/drivers/input/tablet/wacom_sys.c +=================================================================== +--- linux-3.2.46.orig/drivers/input/tablet/wacom_sys.c 2013-07-26 19:20:18.000000000 +0000 ++++ linux-3.2.46/drivers/input/tablet/wacom_sys.c 2013-07-26 19:20:23.000000000 +0000 +@@ -184,9 +184,9 @@ * data before its overwritten. */ features->x_phy = @@ -37,6 +37,3 @@ features->x_max = features->y_max = get_unaligned_le16(&report[10]); --- -1.7.10.1 - diff -Nru linux-3.2.46/debian/patches/features/all/wacom/0015-Input-wacom-isolate-input-registration.patch linux-3.2.46/debian/patches/features/all/wacom/0015-Input-wacom-isolate-input-registration.patch --- linux-3.2.46/debian/patches/features/all/wacom/0015-Input-wacom-isolate-input-registration.patch 2013-02-24 03:52:33.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/wacom/0015-Input-wacom-isolate-input-registration.patch 2013-07-26 19:20:26.000000000 +0000 @@ -17,11 +17,11 @@ drivers/input/tablet/wacom_sys.c | 53 ++++++++++++++++++++++++-------------- 1 file changed, 33 insertions(+), 20 deletions(-) -diff --git a/drivers/input/tablet/wacom_sys.c b/drivers/input/tablet/wacom_sys.c -index dc07821fdae3..59a42e23ddfa 100644 ---- a/drivers/input/tablet/wacom_sys.c -+++ b/drivers/input/tablet/wacom_sys.c -@@ -822,6 +822,37 @@ static void wacom_destroy_leds(struct wacom *wacom) +Index: linux-3.2.46/drivers/input/tablet/wacom_sys.c +=================================================================== +--- linux-3.2.46.orig/drivers/input/tablet/wacom_sys.c 2013-07-26 19:20:23.000000000 +0000 ++++ linux-3.2.46/drivers/input/tablet/wacom_sys.c 2013-07-26 19:20:25.000000000 +0000 +@@ -822,6 +822,37 @@ } } @@ -59,7 +59,7 @@ static int wacom_probe(struct usb_interface *intf, const struct usb_device_id *id) { struct usb_device *dev = interface_to_usbdev(intf); -@@ -829,18 +860,12 @@ static int wacom_probe(struct usb_interface *intf, const struct usb_device_id *i +@@ -829,18 +860,12 @@ struct wacom *wacom; struct wacom_wac *wacom_wac; struct wacom_features *features; @@ -78,7 +78,7 @@ wacom_wac = &wacom->wacom_wac; wacom_wac->features = *((struct wacom_features *)id->driver_info); -@@ -869,8 +894,6 @@ static int wacom_probe(struct usb_interface *intf, const struct usb_device_id *i +@@ -869,8 +894,6 @@ usb_make_path(dev, wacom->phys, sizeof(wacom->phys)); strlcat(wacom->phys, "/input0", sizeof(wacom->phys)); @@ -87,7 +87,7 @@ endpoint = &intf->cur_altsetting->endpoint[0].desc; /* Retrieve the physical and logical size for OEM devices */ -@@ -894,15 +917,6 @@ static int wacom_probe(struct usb_interface *intf, const struct usb_device_id *i +@@ -894,15 +917,6 @@ goto fail3; } @@ -103,7 +103,7 @@ usb_fill_int_urb(wacom->irq, dev, usb_rcvintpipe(dev, endpoint->bEndpointAddress), wacom_wac->data, features->pktlen, -@@ -914,7 +928,7 @@ static int wacom_probe(struct usb_interface *intf, const struct usb_device_id *i +@@ -914,7 +928,7 @@ if (error) goto fail4; @@ -112,7 +112,7 @@ if (error) goto fail5; -@@ -928,8 +942,7 @@ static int wacom_probe(struct usb_interface *intf, const struct usb_device_id *i +@@ -928,8 +942,7 @@ fail4: wacom_remove_shared_data(wacom_wac); fail3: usb_free_urb(wacom->irq); fail2: usb_free_coherent(dev, WACOM_PKGLEN_MAX, wacom_wac->data, wacom->data_dma); @@ -122,6 +122,3 @@ return error; } --- -1.7.10.1 - diff -Nru linux-3.2.46/debian/patches/features/all/wacom/0016-Input-wacom-check-for-allocation-failure-in-probe.patch linux-3.2.46/debian/patches/features/all/wacom/0016-Input-wacom-check-for-allocation-failure-in-probe.patch --- linux-3.2.46/debian/patches/features/all/wacom/0016-Input-wacom-check-for-allocation-failure-in-probe.patch 2013-02-24 03:52:33.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/wacom/0016-Input-wacom-check-for-allocation-failure-in-probe.patch 2013-07-26 19:20:27.000000000 +0000 @@ -15,11 +15,11 @@ drivers/input/tablet/wacom_sys.c | 2 ++ 1 file changed, 2 insertions(+) -diff --git a/drivers/input/tablet/wacom_sys.c b/drivers/input/tablet/wacom_sys.c -index 59a42e23ddfa..bf2462132c5c 100644 ---- a/drivers/input/tablet/wacom_sys.c -+++ b/drivers/input/tablet/wacom_sys.c -@@ -866,6 +866,8 @@ static int wacom_probe(struct usb_interface *intf, const struct usb_device_id *i +Index: linux-3.2.46/drivers/input/tablet/wacom_sys.c +=================================================================== +--- linux-3.2.46.orig/drivers/input/tablet/wacom_sys.c 2013-07-26 19:20:25.000000000 +0000 ++++ linux-3.2.46/drivers/input/tablet/wacom_sys.c 2013-07-26 19:20:26.000000000 +0000 +@@ -866,6 +866,8 @@ return -EINVAL; wacom = kzalloc(sizeof(struct wacom), GFP_KERNEL); @@ -28,6 +28,3 @@ wacom_wac = &wacom->wacom_wac; wacom_wac->features = *((struct wacom_features *)id->driver_info); --- -1.7.10.1 - diff -Nru linux-3.2.46/debian/patches/features/all/wacom/0017-Input-wacom-wireless-monitor-framework.patch linux-3.2.46/debian/patches/features/all/wacom/0017-Input-wacom-wireless-monitor-framework.patch --- linux-3.2.46/debian/patches/features/all/wacom/0017-Input-wacom-wireless-monitor-framework.patch 2013-02-24 03:52:33.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/wacom/0017-Input-wacom-wireless-monitor-framework.patch 2013-07-26 19:20:28.000000000 +0000 @@ -31,11 +31,11 @@ drivers/input/tablet/wacom_wac.h | 4 ++++ 3 files changed, 62 insertions(+), 6 deletions(-) -diff --git a/drivers/input/tablet/wacom_sys.c b/drivers/input/tablet/wacom_sys.c -index bf2462132c5c..223246575860 100644 ---- a/drivers/input/tablet/wacom_sys.c -+++ b/drivers/input/tablet/wacom_sys.c -@@ -422,6 +422,7 @@ static int wacom_query_tablet_data(struct usb_interface *intf, struct wacom_feat +Index: linux-3.2.46/drivers/input/tablet/wacom_sys.c +=================================================================== +--- linux-3.2.46.orig/drivers/input/tablet/wacom_sys.c 2013-07-26 19:20:26.000000000 +0000 ++++ linux-3.2.46/drivers/input/tablet/wacom_sys.c 2013-07-26 19:20:27.000000000 +0000 +@@ -422,6 +422,7 @@ report_id, rep_data, 4, 1); } while ((error < 0 || rep_data[1] != 4) && limit++ < WAC_MSG_RETRIES); } else if (features->type != TABLETPC && @@ -43,7 +43,7 @@ features->device_type == BTN_TOOL_PEN) { do { rep_data[0] = 2; -@@ -454,6 +455,21 @@ static int wacom_retrieve_hid_descriptor(struct usb_interface *intf, +@@ -454,6 +455,21 @@ features->pressure_fuzz = 0; features->distance_fuzz = 0; @@ -65,7 +65,7 @@ /* only Tablet PCs and Bamboo P&T need to retrieve the info */ if ((features->type != TABLETPC) && (features->type != TABLETPC2FG) && (features->type != BAMBOO_PT)) -@@ -930,14 +946,22 @@ static int wacom_probe(struct usb_interface *intf, const struct usb_device_id *i +@@ -930,14 +946,22 @@ if (error) goto fail4; @@ -91,7 +91,7 @@ return 0; fail5: wacom_destroy_leds(wacom); -@@ -955,7 +979,8 @@ static void wacom_disconnect(struct usb_interface *intf) +@@ -955,7 +979,8 @@ usb_set_intfdata(intf, NULL); usb_kill_urb(wacom->irq); @@ -101,7 +101,7 @@ wacom_destroy_leds(wacom); usb_free_urb(wacom->irq); usb_free_coherent(interface_to_usbdev(intf), WACOM_PKGLEN_MAX, -@@ -987,7 +1012,8 @@ static int wacom_resume(struct usb_interface *intf) +@@ -987,7 +1012,8 @@ wacom_query_tablet_data(intf, features); wacom_led_control(wacom); @@ -111,11 +111,11 @@ rv = -EIO; mutex_unlock(&wacom->lock); -diff --git a/drivers/input/tablet/wacom_wac.c b/drivers/input/tablet/wacom_wac.c -index 89a96427faa0..8b73b05f5aef 100644 ---- a/drivers/input/tablet/wacom_wac.c -+++ b/drivers/input/tablet/wacom_wac.c -@@ -1044,6 +1044,14 @@ static int wacom_bpt_irq(struct wacom_wac *wacom, size_t len) +Index: linux-3.2.46/drivers/input/tablet/wacom_wac.c +=================================================================== +--- linux-3.2.46.orig/drivers/input/tablet/wacom_wac.c 2013-07-26 19:20:22.000000000 +0000 ++++ linux-3.2.46/drivers/input/tablet/wacom_wac.c 2013-07-26 19:20:27.000000000 +0000 +@@ -1044,6 +1044,14 @@ return 0; } @@ -130,7 +130,7 @@ void wacom_wac_irq(struct wacom_wac *wacom_wac, size_t len) { bool sync; -@@ -1094,6 +1102,10 @@ void wacom_wac_irq(struct wacom_wac *wacom_wac, size_t len) +@@ -1094,6 +1102,10 @@ sync = wacom_bpt_irq(wacom_wac, len); break; @@ -141,7 +141,7 @@ default: sync = false; break; -@@ -1155,7 +1167,7 @@ void wacom_setup_device_quirks(struct wacom_features *features) +@@ -1155,7 +1167,7 @@ /* these device have multiple inputs */ if (features->type == TABLETPC || features->type == TABLETPC2FG || @@ -150,7 +150,7 @@ features->quirks |= WACOM_QUIRK_MULTI_INPUT; /* quirk for bamboo touch with 2 low res touches */ -@@ -1167,6 +1179,16 @@ void wacom_setup_device_quirks(struct wacom_features *features) +@@ -1167,6 +1179,16 @@ features->y_fuzz <<= 5; features->quirks |= WACOM_QUIRK_BBTOUCH_LOWRES; } @@ -167,7 +167,7 @@ } static unsigned int wacom_calculate_touch_res(unsigned int logical_max, -@@ -1640,6 +1662,9 @@ static const struct wacom_features wacom_features_0xEC = +@@ -1640,6 +1662,9 @@ static const struct wacom_features wacom_features_0x47 = { "Wacom Intuos2 6x8", WACOM_PKGLEN_INTUOS, 20320, 16240, 1023, 31, INTUOS, WACOM_INTUOS_RES, WACOM_INTUOS_RES }; @@ -177,7 +177,7 @@ static const struct wacom_features wacom_features_0xD0 = { "Wacom Bamboo 2FG", WACOM_PKGLEN_BBFUN, 14720, 9200, 1023, 31, BAMBOO_PT, WACOM_INTUOS_RES, WACOM_INTUOS_RES }; -@@ -1766,6 +1791,7 @@ const struct usb_device_id wacom_ids[] = { +@@ -1766,6 +1791,7 @@ { USB_DEVICE_DETAILED(0xCE, USB_CLASS_HID, USB_INTERFACE_SUBCLASS_BOOT, USB_INTERFACE_PROTOCOL_MOUSE) }, @@ -185,10 +185,10 @@ { USB_DEVICE_WACOM(0xD0) }, { USB_DEVICE_WACOM(0xD1) }, { USB_DEVICE_WACOM(0xD2) }, -diff --git a/drivers/input/tablet/wacom_wac.h b/drivers/input/tablet/wacom_wac.h -index 4f0ba21b0196..2c04b6248a56 100644 ---- a/drivers/input/tablet/wacom_wac.h -+++ b/drivers/input/tablet/wacom_wac.h +Index: linux-3.2.46/drivers/input/tablet/wacom_wac.h +=================================================================== +--- linux-3.2.46.orig/drivers/input/tablet/wacom_wac.h 2013-07-26 19:20:20.000000000 +0000 ++++ linux-3.2.46/drivers/input/tablet/wacom_wac.h 2013-07-26 19:20:27.000000000 +0000 @@ -24,6 +24,7 @@ #define WACOM_PKGLEN_BBTOUCH 20 #define WACOM_PKGLEN_BBTOUCH3 64 @@ -206,7 +206,7 @@ enum { PENPARTNER = 0, -@@ -54,6 +57,7 @@ enum { +@@ -54,6 +57,7 @@ PL, DTU, BAMBOO_PT, @@ -214,6 +214,3 @@ INTUOS, INTUOS3S, INTUOS3, --- -1.7.10.1 - diff -Nru linux-3.2.46/debian/patches/features/all/wacom/0018-Input-wacom-create-inputs-when-wireless-connect.patch linux-3.2.46/debian/patches/features/all/wacom/0018-Input-wacom-create-inputs-when-wireless-connect.patch --- linux-3.2.46/debian/patches/features/all/wacom/0018-Input-wacom-create-inputs-when-wireless-connect.patch 2013-02-24 03:52:33.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/wacom/0018-Input-wacom-create-inputs-when-wireless-connect.patch 2013-07-26 19:20:30.000000000 +0000 @@ -29,11 +29,11 @@ drivers/input/tablet/wacom_wac.h | 1 + 4 files changed, 109 insertions(+), 10 deletions(-) -diff --git a/drivers/input/tablet/wacom.h b/drivers/input/tablet/wacom.h -index 0783864a7dc2..febbfd9f3a84 100644 ---- a/drivers/input/tablet/wacom.h -+++ b/drivers/input/tablet/wacom.h -@@ -112,6 +112,7 @@ struct wacom { +Index: linux-3.2.46/drivers/input/tablet/wacom.h +=================================================================== +--- linux-3.2.46.orig/drivers/input/tablet/wacom.h 2013-07-26 18:55:34.000000000 +0000 ++++ linux-3.2.46/drivers/input/tablet/wacom.h 2013-07-26 19:20:29.000000000 +0000 +@@ -112,6 +112,7 @@ struct urb *irq; struct wacom_wac wacom_wac; struct mutex lock; @@ -41,7 +41,7 @@ bool open; char phys[32]; struct wacom_led { -@@ -122,6 +123,12 @@ struct wacom { +@@ -122,6 +123,12 @@ } led; }; @@ -54,11 +54,11 @@ extern const struct usb_device_id wacom_ids[]; void wacom_wac_irq(struct wacom_wac *wacom_wac, size_t len); -diff --git a/drivers/input/tablet/wacom_sys.c b/drivers/input/tablet/wacom_sys.c -index 223246575860..1bcf555ff340 100644 ---- a/drivers/input/tablet/wacom_sys.c -+++ b/drivers/input/tablet/wacom_sys.c -@@ -167,6 +167,19 @@ static void wacom_close(struct input_dev *dev) +Index: linux-3.2.46/drivers/input/tablet/wacom_sys.c +=================================================================== +--- linux-3.2.46.orig/drivers/input/tablet/wacom_sys.c 2013-07-26 19:20:27.000000000 +0000 ++++ linux-3.2.46/drivers/input/tablet/wacom_sys.c 2013-07-26 19:20:29.000000000 +0000 +@@ -167,6 +167,19 @@ usb_autopm_put_interface(wacom->intf); } @@ -78,7 +78,7 @@ static int wacom_parse_logical_collection(unsigned char *report, struct wacom_features *features) { -@@ -178,15 +191,7 @@ static int wacom_parse_logical_collection(unsigned char *report, +@@ -178,15 +191,7 @@ features->pktlen = WACOM_PKGLEN_BBTOUCH3; features->device_type = BTN_TOOL_FINGER; @@ -95,7 +95,7 @@ features->x_max = features->y_max = get_unaligned_le16(&report[10]); -@@ -869,6 +874,72 @@ static int wacom_register_input(struct wacom *wacom) +@@ -869,6 +874,72 @@ return error; } @@ -168,7 +168,7 @@ static int wacom_probe(struct usb_interface *intf, const struct usb_device_id *id) { struct usb_device *dev = interface_to_usbdev(intf); -@@ -909,6 +980,7 @@ static int wacom_probe(struct usb_interface *intf, const struct usb_device_id *i +@@ -909,6 +980,7 @@ wacom->usbdev = dev; wacom->intf = intf; mutex_init(&wacom->lock); @@ -176,7 +176,7 @@ usb_make_path(dev, wacom->phys, sizeof(wacom->phys)); strlcat(wacom->phys, "/input0", sizeof(wacom->phys)); -@@ -979,6 +1051,7 @@ static void wacom_disconnect(struct usb_interface *intf) +@@ -979,6 +1051,7 @@ usb_set_intfdata(intf, NULL); usb_kill_urb(wacom->irq); @@ -184,11 +184,11 @@ if (wacom->wacom_wac.input) input_unregister_device(wacom->wacom_wac.input); wacom_destroy_leds(wacom); -diff --git a/drivers/input/tablet/wacom_wac.c b/drivers/input/tablet/wacom_wac.c -index 8b73b05f5aef..1013ac345781 100644 ---- a/drivers/input/tablet/wacom_wac.c -+++ b/drivers/input/tablet/wacom_wac.c -@@ -1046,9 +1046,27 @@ static int wacom_bpt_irq(struct wacom_wac *wacom, size_t len) +Index: linux-3.2.46/drivers/input/tablet/wacom_wac.c +=================================================================== +--- linux-3.2.46.orig/drivers/input/tablet/wacom_wac.c 2013-07-26 19:20:27.000000000 +0000 ++++ linux-3.2.46/drivers/input/tablet/wacom_wac.c 2013-07-26 19:20:29.000000000 +0000 +@@ -1046,9 +1046,27 @@ static int wacom_wireless_irq(struct wacom_wac *wacom, size_t len) { @@ -217,11 +217,11 @@ return 0; } -diff --git a/drivers/input/tablet/wacom_wac.h b/drivers/input/tablet/wacom_wac.h -index 2c04b6248a56..cffaf6b7e6e9 100644 ---- a/drivers/input/tablet/wacom_wac.h -+++ b/drivers/input/tablet/wacom_wac.h -@@ -111,6 +111,7 @@ struct wacom_wac { +Index: linux-3.2.46/drivers/input/tablet/wacom_wac.h +=================================================================== +--- linux-3.2.46.orig/drivers/input/tablet/wacom_wac.h 2013-07-26 19:20:27.000000000 +0000 ++++ linux-3.2.46/drivers/input/tablet/wacom_wac.h 2013-07-26 19:20:29.000000000 +0000 +@@ -111,6 +111,7 @@ struct wacom_features features; struct wacom_shared *shared; struct input_dev *input; @@ -229,6 +229,3 @@ }; #endif --- -1.7.10.1 - diff -Nru linux-3.2.46/debian/patches/features/all/wacom/0019-Input-wacom-wireless-battery-status.patch linux-3.2.46/debian/patches/features/all/wacom/0019-Input-wacom-wireless-battery-status.patch --- linux-3.2.46/debian/patches/features/all/wacom/0019-Input-wacom-wireless-battery-status.patch 2013-02-24 03:52:33.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/wacom/0019-Input-wacom-wireless-battery-status.patch 2013-07-26 19:20:31.000000000 +0000 @@ -17,11 +17,11 @@ drivers/input/tablet/wacom_wac.h | 1 + 5 files changed, 64 insertions(+), 2 deletions(-) -diff --git a/drivers/input/tablet/Kconfig b/drivers/input/tablet/Kconfig -index e53f4081a586..bed7cbf84cfd 100644 ---- a/drivers/input/tablet/Kconfig -+++ b/drivers/input/tablet/Kconfig -@@ -76,6 +76,7 @@ config TABLET_USB_KBTAB +Index: linux-3.2.46/drivers/input/tablet/Kconfig +=================================================================== +--- linux-3.2.46.orig/drivers/input/tablet/Kconfig 2013-07-26 19:20:21.000000000 +0000 ++++ linux-3.2.46/drivers/input/tablet/Kconfig 2013-07-26 19:20:30.000000000 +0000 +@@ -76,6 +76,7 @@ config TABLET_USB_WACOM tristate "Wacom Intuos/Graphire tablet support (USB)" depends on USB_ARCH_HAS_HCD @@ -29,10 +29,10 @@ select USB select NEW_LEDS select LEDS_CLASS -diff --git a/drivers/input/tablet/wacom.h b/drivers/input/tablet/wacom.h -index febbfd9f3a84..b4842d0e61dd 100644 ---- a/drivers/input/tablet/wacom.h -+++ b/drivers/input/tablet/wacom.h +Index: linux-3.2.46/drivers/input/tablet/wacom.h +=================================================================== +--- linux-3.2.46.orig/drivers/input/tablet/wacom.h 2013-07-26 19:20:29.000000000 +0000 ++++ linux-3.2.46/drivers/input/tablet/wacom.h 2013-07-26 19:20:30.000000000 +0000 @@ -88,6 +88,7 @@ #include #include @@ -41,7 +41,7 @@ #include /* -@@ -121,6 +122,7 @@ struct wacom { +@@ -121,6 +122,7 @@ u8 hlv; /* status led brightness button pressed (1..127) */ u8 img_lum; /* OLED matrix display brightness */ } led; @@ -49,11 +49,11 @@ }; static inline void wacom_schedule_work(struct wacom_wac *wacom_wac) -diff --git a/drivers/input/tablet/wacom_sys.c b/drivers/input/tablet/wacom_sys.c -index 1bcf555ff340..8a5fad186140 100644 ---- a/drivers/input/tablet/wacom_sys.c -+++ b/drivers/input/tablet/wacom_sys.c -@@ -843,6 +843,55 @@ static void wacom_destroy_leds(struct wacom *wacom) +Index: linux-3.2.46/drivers/input/tablet/wacom_sys.c +=================================================================== +--- linux-3.2.46.orig/drivers/input/tablet/wacom_sys.c 2013-07-26 19:20:29.000000000 +0000 ++++ linux-3.2.46/drivers/input/tablet/wacom_sys.c 2013-07-26 19:20:30.000000000 +0000 +@@ -843,6 +843,55 @@ } } @@ -109,7 +109,7 @@ static int wacom_register_input(struct wacom *wacom) { struct input_dev *input_dev; -@@ -1018,10 +1067,14 @@ static int wacom_probe(struct usb_interface *intf, const struct usb_device_id *i +@@ -1018,10 +1067,14 @@ if (error) goto fail4; @@ -125,7 +125,7 @@ } /* Note that if query fails it is not a hard failure */ -@@ -1036,6 +1089,7 @@ static int wacom_probe(struct usb_interface *intf, const struct usb_device_id *i +@@ -1036,6 +1089,7 @@ return 0; @@ -133,7 +133,7 @@ fail5: wacom_destroy_leds(wacom); fail4: wacom_remove_shared_data(wacom_wac); fail3: usb_free_urb(wacom->irq); -@@ -1054,6 +1108,7 @@ static void wacom_disconnect(struct usb_interface *intf) +@@ -1054,6 +1108,7 @@ cancel_work_sync(&wacom->work); if (wacom->wacom_wac.input) input_unregister_device(wacom->wacom_wac.input); @@ -141,11 +141,11 @@ wacom_destroy_leds(wacom); usb_free_urb(wacom->irq); usb_free_coherent(interface_to_usbdev(intf), WACOM_PKGLEN_MAX, -diff --git a/drivers/input/tablet/wacom_wac.c b/drivers/input/tablet/wacom_wac.c -index 1013ac345781..cecd35c8f0b3 100644 ---- a/drivers/input/tablet/wacom_wac.c -+++ b/drivers/input/tablet/wacom_wac.c -@@ -1054,17 +1054,20 @@ static int wacom_wireless_irq(struct wacom_wac *wacom, size_t len) +Index: linux-3.2.46/drivers/input/tablet/wacom_wac.c +=================================================================== +--- linux-3.2.46.orig/drivers/input/tablet/wacom_wac.c 2013-07-26 19:20:29.000000000 +0000 ++++ linux-3.2.46/drivers/input/tablet/wacom_wac.c 2013-07-26 19:20:30.000000000 +0000 +@@ -1054,17 +1054,20 @@ connected = data[1] & 0x01; if (connected) { @@ -167,11 +167,11 @@ } return 0; -diff --git a/drivers/input/tablet/wacom_wac.h b/drivers/input/tablet/wacom_wac.h -index cffaf6b7e6e9..ba5a334e54d6 100644 ---- a/drivers/input/tablet/wacom_wac.h -+++ b/drivers/input/tablet/wacom_wac.h -@@ -112,6 +112,7 @@ struct wacom_wac { +Index: linux-3.2.46/drivers/input/tablet/wacom_wac.h +=================================================================== +--- linux-3.2.46.orig/drivers/input/tablet/wacom_wac.h 2013-07-26 19:20:29.000000000 +0000 ++++ linux-3.2.46/drivers/input/tablet/wacom_wac.h 2013-07-26 19:20:30.000000000 +0000 +@@ -112,6 +112,7 @@ struct wacom_shared *shared; struct input_dev *input; int pid; @@ -179,6 +179,3 @@ }; #endif --- -1.7.10.1 - diff -Nru linux-3.2.46/debian/patches/features/all/wacom/0020-Input-wacom-add-basic-Intuos5-support.patch linux-3.2.46/debian/patches/features/all/wacom/0020-Input-wacom-add-basic-Intuos5-support.patch --- linux-3.2.46/debian/patches/features/all/wacom/0020-Input-wacom-add-basic-Intuos5-support.patch 2013-02-24 03:52:33.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/wacom/0020-Input-wacom-add-basic-Intuos5-support.patch 2013-07-26 19:20:32.000000000 +0000 @@ -18,11 +18,11 @@ drivers/input/tablet/wacom_wac.h | 3 +++ 2 files changed, 36 insertions(+), 3 deletions(-) -diff --git a/drivers/input/tablet/wacom_wac.c b/drivers/input/tablet/wacom_wac.c -index cecd35c8f0b3..f159e9d90d4a 100644 ---- a/drivers/input/tablet/wacom_wac.c -+++ b/drivers/input/tablet/wacom_wac.c -@@ -452,6 +452,7 @@ static void wacom_intuos_general(struct wacom_wac *wacom) +Index: linux-3.2.46/drivers/input/tablet/wacom_wac.c +=================================================================== +--- linux-3.2.46.orig/drivers/input/tablet/wacom_wac.c 2013-07-26 19:20:30.000000000 +0000 ++++ linux-3.2.46/drivers/input/tablet/wacom_wac.c 2013-07-26 19:20:32.000000000 +0000 +@@ -452,6 +452,7 @@ if ((data[1] & 0xb8) == 0xa0) { t = (data[6] << 2) | ((data[7] >> 6) & 3); if ((features->type >= INTUOS4S && features->type <= INTUOS4L) || @@ -30,7 +30,7 @@ features->type == WACOM_21UX2 || features->type == WACOM_24HD) { t = (t << 1) | (data[1] & 1); } -@@ -632,7 +633,9 @@ static int wacom_intuos_irq(struct wacom_wac *wacom) +@@ -632,7 +633,9 @@ (features->type == INTUOS3 || features->type == INTUOS3S || features->type == INTUOS4 || @@ -41,7 +41,7 @@ return 0; } -@@ -685,7 +688,8 @@ static int wacom_intuos_irq(struct wacom_wac *wacom) +@@ -685,7 +688,8 @@ } else if (wacom->tool[idx] == BTN_TOOL_MOUSE) { /* I4 mouse */ @@ -51,7 +51,7 @@ input_report_key(input, BTN_LEFT, data[6] & 0x01); input_report_key(input, BTN_MIDDLE, data[6] & 0x02); input_report_key(input, BTN_RIGHT, data[6] & 0x04); -@@ -712,7 +716,7 @@ static int wacom_intuos_irq(struct wacom_wac *wacom) +@@ -712,7 +716,7 @@ } } } else if ((features->type < INTUOS3S || features->type == INTUOS3L || @@ -60,7 +60,7 @@ wacom->tool[idx] == BTN_TOOL_LENS) { /* Lens cursor packets */ input_report_key(input, BTN_LEFT, data[8] & 0x01); -@@ -1107,6 +1111,9 @@ void wacom_wac_irq(struct wacom_wac *wacom_wac, size_t len) +@@ -1107,6 +1111,9 @@ case INTUOS4S: case INTUOS4: case INTUOS4L: @@ -70,7 +70,7 @@ case CINTIQ: case WACOM_BEE: case WACOM_21UX2: -@@ -1355,12 +1362,15 @@ void wacom_setup_input_capabilities(struct input_dev *input_dev, +@@ -1355,12 +1362,15 @@ wacom_setup_intuos(wacom_wac); break; @@ -86,7 +86,7 @@ case INTUOS4S: for (i = 0; i < 7; i++) __set_bit(BTN_0 + i, input_dev->keybit); -@@ -1629,6 +1639,21 @@ static const struct wacom_features wacom_features_0xBB = +@@ -1629,6 +1639,21 @@ static const struct wacom_features wacom_features_0xBC = { "Wacom Intuos4 WL", WACOM_PKGLEN_INTUOS, 40840, 25400, 2047, 63, INTUOS4, WACOM_INTUOS3_RES, WACOM_INTUOS3_RES }; @@ -108,7 +108,7 @@ static const struct wacom_features wacom_features_0xF4 = { "Wacom Cintiq 24HD", WACOM_PKGLEN_INTUOS, 104480, 65600, 2047, 63, WACOM_24HD, WACOM_INTUOS3_RES, WACOM_INTUOS3_RES }; -@@ -1801,6 +1826,11 @@ const struct usb_device_id wacom_ids[] = { +@@ -1801,6 +1826,11 @@ { USB_DEVICE_WACOM(0xBA) }, { USB_DEVICE_WACOM(0xBB) }, { USB_DEVICE_WACOM(0xBC) }, @@ -120,11 +120,11 @@ { USB_DEVICE_WACOM(0x3F) }, { USB_DEVICE_WACOM(0xC5) }, { USB_DEVICE_WACOM(0xC6) }, -diff --git a/drivers/input/tablet/wacom_wac.h b/drivers/input/tablet/wacom_wac.h -index ba5a334e54d6..0aa00ce5fd7d 100644 ---- a/drivers/input/tablet/wacom_wac.h -+++ b/drivers/input/tablet/wacom_wac.h -@@ -65,6 +65,9 @@ enum { +Index: linux-3.2.46/drivers/input/tablet/wacom_wac.h +=================================================================== +--- linux-3.2.46.orig/drivers/input/tablet/wacom_wac.h 2013-07-26 19:20:30.000000000 +0000 ++++ linux-3.2.46/drivers/input/tablet/wacom_wac.h 2013-07-26 19:20:32.000000000 +0000 +@@ -65,6 +65,9 @@ INTUOS4S, INTUOS4, INTUOS4L, @@ -134,6 +134,3 @@ WACOM_24HD, WACOM_21UX2, CINTIQ, --- -1.7.10.1 - diff -Nru linux-3.2.46/debian/patches/features/all/wacom/0021-Input-wacom-add-Intuos5-Touch-Ring-ExpressKey-suppor.patch linux-3.2.46/debian/patches/features/all/wacom/0021-Input-wacom-add-Intuos5-Touch-Ring-ExpressKey-suppor.patch --- linux-3.2.46/debian/patches/features/all/wacom/0021-Input-wacom-add-Intuos5-Touch-Ring-ExpressKey-suppor.patch 2013-02-24 03:52:33.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/wacom/0021-Input-wacom-add-Intuos5-Touch-Ring-ExpressKey-suppor.patch 2013-07-26 19:20:34.000000000 +0000 @@ -18,11 +18,11 @@ drivers/input/tablet/wacom_wac.h | 1 + 2 files changed, 32 insertions(+), 2 deletions(-) -diff --git a/drivers/input/tablet/wacom_wac.c b/drivers/input/tablet/wacom_wac.c -index f159e9d90d4a..b5176a073c83 100644 ---- a/drivers/input/tablet/wacom_wac.c -+++ b/drivers/input/tablet/wacom_wac.c -@@ -484,7 +484,8 @@ static int wacom_intuos_irq(struct wacom_wac *wacom) +Index: linux-3.2.46/drivers/input/tablet/wacom_wac.c +=================================================================== +--- linux-3.2.46.orig/drivers/input/tablet/wacom_wac.c 2013-07-26 19:20:32.000000000 +0000 ++++ linux-3.2.46/drivers/input/tablet/wacom_wac.c 2013-07-26 19:20:33.000000000 +0000 +@@ -484,7 +484,8 @@ int idx = 0, result; if (data[0] != WACOM_REPORT_PENABLED && data[0] != WACOM_REPORT_INTUOSREAD @@ -32,7 +32,7 @@ dbg("wacom_intuos_irq: received unknown report #%d", data[0]); return 0; } -@@ -494,7 +495,7 @@ static int wacom_intuos_irq(struct wacom_wac *wacom) +@@ -494,7 +495,7 @@ idx = data[1] & 0x01; /* pad packets. Works as a second tool and is always in prox */ @@ -41,10 +41,13 @@ if (features->type >= INTUOS4S && features->type <= INTUOS4L) { input_report_key(input, BTN_0, (data[2] & 0x01)); input_report_key(input, BTN_1, (data[3] & 0x01)); -@@ -570,6 +571,34 @@ static int wacom_intuos_irq(struct wacom_wac *wacom) - input_report_key(input, wacom->tool[1], 0); - input_report_abs(input, ABS_MISC, 0); - } +@@ -567,6 +568,34 @@ + input_report_key(input, wacom->tool[1], 1); + input_report_abs(input, ABS_MISC, PAD_DEVICE_ID); + } else { ++ input_report_key(input, wacom->tool[1], 0); ++ input_report_abs(input, ABS_MISC, 0); ++ } + } else if (features->type >= INTUOS5S && features->type <= INTUOS5L) { + int i; + @@ -70,16 +73,13 @@ + input_report_key(input, wacom->tool[1], 1); + input_report_abs(input, ABS_MISC, PAD_DEVICE_ID); + } else { -+ input_report_key(input, wacom->tool[1], 0); -+ input_report_abs(input, ABS_MISC, 0); -+ } - } else { - if (features->type == WACOM_21UX2) { - input_report_key(input, BTN_0, (data[5] & 0x01)); -diff --git a/drivers/input/tablet/wacom_wac.h b/drivers/input/tablet/wacom_wac.h -index 0aa00ce5fd7d..17ba1868f0cd 100644 ---- a/drivers/input/tablet/wacom_wac.h -+++ b/drivers/input/tablet/wacom_wac.h + input_report_key(input, wacom->tool[1], 0); + input_report_abs(input, ABS_MISC, 0); + } +Index: linux-3.2.46/drivers/input/tablet/wacom_wac.h +=================================================================== +--- linux-3.2.46.orig/drivers/input/tablet/wacom_wac.h 2013-07-26 19:20:32.000000000 +0000 ++++ linux-3.2.46/drivers/input/tablet/wacom_wac.h 2013-07-26 19:20:33.000000000 +0000 @@ -38,6 +38,7 @@ #define WACOM_REPORT_INTUOSREAD 5 #define WACOM_REPORT_INTUOSWRITE 6 @@ -88,6 +88,3 @@ #define WACOM_REPORT_TPC1FG 6 #define WACOM_REPORT_TPC2FG 13 #define WACOM_REPORT_TPCHID 15 --- -1.7.10.1 - diff -Nru linux-3.2.46/debian/patches/features/all/wacom/0022-Input-wacom-add-Intuos5-Touch-Ring-LED-support.patch linux-3.2.46/debian/patches/features/all/wacom/0022-Input-wacom-add-Intuos5-Touch-Ring-LED-support.patch --- linux-3.2.46/debian/patches/features/all/wacom/0022-Input-wacom-add-Intuos5-Touch-Ring-LED-support.patch 2013-02-24 03:52:33.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/wacom/0022-Input-wacom-add-Intuos5-Touch-Ring-LED-support.patch 2013-07-26 19:20:35.000000000 +0000 @@ -19,11 +19,11 @@ drivers/input/tablet/wacom_sys.c | 67 ++++++++++++++++++++++---- 2 files changed, 65 insertions(+), 17 deletions(-) -diff --git a/Documentation/ABI/testing/sysfs-driver-wacom b/Documentation/ABI/testing/sysfs-driver-wacom -index 0130d6683c14..5e9cbdc7486e 100644 ---- a/Documentation/ABI/testing/sysfs-driver-wacom -+++ b/Documentation/ABI/testing/sysfs-driver-wacom -@@ -15,9 +15,10 @@ Contact: linux-input@vger.kernel.org +Index: linux-3.2.46/Documentation/ABI/testing/sysfs-driver-wacom +=================================================================== +--- linux-3.2.46.orig/Documentation/ABI/testing/sysfs-driver-wacom 2013-07-26 19:20:17.000000000 +0000 ++++ linux-3.2.46/Documentation/ABI/testing/sysfs-driver-wacom 2013-07-26 19:20:34.000000000 +0000 +@@ -15,9 +15,10 @@ Description: Attribute group for control of the status LEDs and the OLEDs. This attribute group is only available for Intuos 4 M, L, @@ -37,7 +37,7 @@ What: /sys/bus/usb/devices/-:./wacom_led/status0_luminance Date: August 2011 -@@ -40,10 +41,10 @@ What: /sys/bus/usb/devices/-:./wacom_led/status_led0 +@@ -40,10 +41,10 @@ Date: August 2011 Contact: linux-input@vger.kernel.org Description: @@ -52,11 +52,11 @@ What: /sys/bus/usb/devices/-:./wacom_led/status_led1_select Date: September 2011 -diff --git a/drivers/input/tablet/wacom_sys.c b/drivers/input/tablet/wacom_sys.c -index 8a5fad186140..f470e41d23e7 100644 ---- a/drivers/input/tablet/wacom_sys.c -+++ b/drivers/input/tablet/wacom_sys.c -@@ -574,23 +574,39 @@ static void wacom_remove_shared_data(struct wacom_wac *wacom) +Index: linux-3.2.46/drivers/input/tablet/wacom_sys.c +=================================================================== +--- linux-3.2.46.orig/drivers/input/tablet/wacom_sys.c 2013-07-26 19:20:30.000000000 +0000 ++++ linux-3.2.46/drivers/input/tablet/wacom_sys.c 2013-07-26 19:20:34.000000000 +0000 +@@ -574,23 +574,39 @@ static int wacom_led_control(struct wacom *wacom) { unsigned char *buf; @@ -70,6 +70,14 @@ - if (wacom->wacom_wac.features.type == WACOM_21UX2 || - wacom->wacom_wac.features.type == WACOM_24HD) - led = (wacom->led.select[1] << 4) | 0x40; +- +- led |= wacom->led.select[0] | 0x4; +- +- buf[0] = WAC_CMD_LED_CONTROL; +- buf[1] = led; +- buf[2] = wacom->led.llv; +- buf[3] = wacom->led.hlv; +- buf[4] = wacom->led.img_lum; + if (wacom->wacom_wac.features.type >= INTUOS5S && + wacom->wacom_wac.features.type <= INTUOS5L) { + /* @@ -80,19 +88,13 @@ + int ring_led = wacom->led.select[0] & 0x03; + int ring_lum = (((wacom->led.llv & 0x60) >> 5) - 1) & 0x03; + int crop_lum = 0; - -- led |= wacom->led.select[0] | 0x4; ++ + buf[0] = WAC_CMD_LED_CONTROL; + buf[1] = (crop_lum << 4) | (ring_lum << 2) | (ring_led); + } + else { + int led = wacom->led.select[0] | 0x4; - -- buf[0] = WAC_CMD_LED_CONTROL; -- buf[1] = led; -- buf[2] = wacom->led.llv; -- buf[3] = wacom->led.hlv; -- buf[4] = wacom->led.img_lum; ++ + if (wacom->wacom_wac.features.type == WACOM_21UX2 || + wacom->wacom_wac.features.type == WACOM_24HD) + led |= (wacom->led.select[1] << 4) | 0x40; @@ -106,7 +108,7 @@ retval = wacom_set_report(wacom->intf, 0x03, WAC_CMD_LED_CONTROL, buf, 9, WAC_CMD_RETRIES); -@@ -783,6 +799,17 @@ static struct attribute_group intuos4_led_attr_group = { +@@ -783,6 +799,17 @@ .attrs = intuos4_led_attrs, }; @@ -124,7 +126,7 @@ static int wacom_initialize_leds(struct wacom *wacom) { int error; -@@ -812,6 +839,19 @@ static int wacom_initialize_leds(struct wacom *wacom) +@@ -812,6 +839,19 @@ &cintiq_led_attr_group); break; @@ -144,7 +146,7 @@ default: return 0; } -@@ -840,6 +880,13 @@ static void wacom_destroy_leds(struct wacom *wacom) +@@ -840,6 +880,13 @@ sysfs_remove_group(&wacom->intf->dev.kobj, &cintiq_led_attr_group); break; @@ -158,6 +160,3 @@ } } --- -1.7.10.1 - diff -Nru linux-3.2.46/debian/patches/features/all/wacom/0023-Input-wacom-add-Intuos5-multitouch-sensor-support.patch linux-3.2.46/debian/patches/features/all/wacom/0023-Input-wacom-add-Intuos5-multitouch-sensor-support.patch --- linux-3.2.46/debian/patches/features/all/wacom/0023-Input-wacom-add-Intuos5-multitouch-sensor-support.patch 2013-02-24 03:52:33.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/wacom/0023-Input-wacom-add-Intuos5-multitouch-sensor-support.patch 2013-07-26 19:20:37.000000000 +0000 @@ -19,11 +19,11 @@ drivers/input/tablet/wacom_wac.c | 64 +++++++++++++++++++++++++++++++++++--- 2 files changed, 84 insertions(+), 5 deletions(-) -diff --git a/drivers/input/tablet/wacom_sys.c b/drivers/input/tablet/wacom_sys.c -index f470e41d23e7..4d52e5924801 100644 ---- a/drivers/input/tablet/wacom_sys.c -+++ b/drivers/input/tablet/wacom_sys.c -@@ -233,6 +233,9 @@ static int wacom_parse_logical_collection(unsigned char *report, +Index: linux-3.2.46/drivers/input/tablet/wacom_sys.c +=================================================================== +--- linux-3.2.46.orig/drivers/input/tablet/wacom_sys.c 2013-07-26 19:20:34.000000000 +0000 ++++ linux-3.2.46/drivers/input/tablet/wacom_sys.c 2013-07-26 19:20:36.000000000 +0000 +@@ -233,6 +233,9 @@ * 3rd gen Bamboo Touch no longer define a Digitizer-Finger Pysical * Collection. Instead they define a Logical Collection with a single * Logical Maximum for both X and Y. @@ -33,7 +33,7 @@ */ static int wacom_parse_hid(struct usb_interface *intf, struct hid_descriptor *hid_desc, -@@ -1087,6 +1090,28 @@ static int wacom_probe(struct usb_interface *intf, const struct usb_device_id *i +@@ -1087,6 +1090,28 @@ if (error) goto fail3; @@ -62,11 +62,11 @@ wacom_setup_device_quirks(features); strlcpy(wacom_wac->name, features->name, sizeof(wacom_wac->name)); -diff --git a/drivers/input/tablet/wacom_wac.c b/drivers/input/tablet/wacom_wac.c -index b5176a073c83..d96e186f71dc 100644 ---- a/drivers/input/tablet/wacom_wac.c -+++ b/drivers/input/tablet/wacom_wac.c -@@ -321,6 +321,9 @@ static int wacom_intuos_inout(struct wacom_wac *wacom) +Index: linux-3.2.46/drivers/input/tablet/wacom_wac.c +=================================================================== +--- linux-3.2.46.orig/drivers/input/tablet/wacom_wac.c 2013-07-26 19:20:33.000000000 +0000 ++++ linux-3.2.46/drivers/input/tablet/wacom_wac.c 2013-07-26 19:20:36.000000000 +0000 +@@ -321,6 +321,9 @@ /* Enter report */ if ((data[1] & 0xfc) == 0xc0) { @@ -76,7 +76,7 @@ /* serial number of the tool */ wacom->serial[idx] = ((data[3] & 0x0f) << 28) + (data[4] << 20) + (data[5] << 12) + -@@ -406,6 +409,9 @@ static int wacom_intuos_inout(struct wacom_wac *wacom) +@@ -406,6 +409,9 @@ /* Exit report */ if ((data[1] & 0xfe) == 0x80) { @@ -86,7 +86,7 @@ /* * Reset all states otherwise we lose the initial states * when in-prox next time -@@ -1140,9 +1146,6 @@ void wacom_wac_irq(struct wacom_wac *wacom_wac, size_t len) +@@ -1140,9 +1146,6 @@ case INTUOS4S: case INTUOS4: case INTUOS4L: @@ -96,7 +96,7 @@ case CINTIQ: case WACOM_BEE: case WACOM_21UX2: -@@ -1150,6 +1153,15 @@ void wacom_wac_irq(struct wacom_wac *wacom_wac, size_t len) +@@ -1150,6 +1153,15 @@ sync = wacom_intuos_irq(wacom_wac); break; @@ -112,7 +112,7 @@ case TABLETPC: case TABLETPC2FG: sync = wacom_tpc_irq(wacom_wac, len); -@@ -1224,7 +1236,8 @@ void wacom_setup_device_quirks(struct wacom_features *features) +@@ -1224,7 +1236,8 @@ /* these device have multiple inputs */ if (features->type == TABLETPC || features->type == TABLETPC2FG || @@ -122,7 +122,7 @@ features->quirks |= WACOM_QUIRK_MULTI_INPUT; /* quirk for bamboo touch with 2 low res touches */ -@@ -1393,13 +1406,54 @@ void wacom_setup_input_capabilities(struct input_dev *input_dev, +@@ -1393,13 +1406,54 @@ case INTUOS5: case INTUOS5L: @@ -178,6 +178,3 @@ case INTUOS4S: for (i = 0; i < 7; i++) __set_bit(BTN_0 + i, input_dev->keybit); --- -1.7.10.1 - diff -Nru linux-3.2.46/debian/patches/features/all/wacom/0024-Input-wacom-retrieve-maximum-number-of-touch-points.patch linux-3.2.46/debian/patches/features/all/wacom/0024-Input-wacom-retrieve-maximum-number-of-touch-points.patch --- linux-3.2.46/debian/patches/features/all/wacom/0024-Input-wacom-retrieve-maximum-number-of-touch-points.patch 2013-02-24 03:52:33.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/wacom/0024-Input-wacom-retrieve-maximum-number-of-touch-points.patch 2013-07-26 19:20:38.000000000 +0000 @@ -17,10 +17,10 @@ drivers/input/tablet/wacom_wac.h | 1 + 3 files changed, 65 insertions(+), 24 deletions(-) -diff --git a/drivers/input/tablet/wacom_sys.c b/drivers/input/tablet/wacom_sys.c -index 4d52e5924801..53598c2065cf 100644 ---- a/drivers/input/tablet/wacom_sys.c -+++ b/drivers/input/tablet/wacom_sys.c +Index: linux-3.2.46/drivers/input/tablet/wacom_sys.c +=================================================================== +--- linux-3.2.46.orig/drivers/input/tablet/wacom_sys.c 2013-07-26 19:20:36.000000000 +0000 ++++ linux-3.2.46/drivers/input/tablet/wacom_sys.c 2013-07-26 19:20:37.000000000 +0000 @@ -28,6 +28,7 @@ #define HID_USAGE_Y_TILT 0x3e #define HID_USAGE_FINGER 0x22 @@ -29,7 +29,7 @@ #define HID_COLLECTION 0xa1 #define HID_COLLECTION_LOGICAL 0x02 #define HID_COLLECTION_END 0xc0 -@@ -201,6 +202,27 @@ static int wacom_parse_logical_collection(unsigned char *report, +@@ -201,6 +202,27 @@ return length; } @@ -57,7 +57,7 @@ /* * Interface Descriptor of wacom devices can be incomplete and * inconsistent so wacom_features table is used to store stylus -@@ -377,6 +399,11 @@ static int wacom_parse_hid(struct usb_interface *intf, +@@ -377,6 +399,11 @@ pen = 1; i++; break; @@ -69,7 +69,7 @@ } break; -@@ -1085,7 +1112,7 @@ static int wacom_probe(struct usb_interface *intf, const struct usb_device_id *i +@@ -1085,7 +1112,7 @@ endpoint = &intf->cur_altsetting->endpoint[0].desc; @@ -78,11 +78,11 @@ error = wacom_retrieve_hid_descriptor(intf, features); if (error) goto fail3; -diff --git a/drivers/input/tablet/wacom_wac.c b/drivers/input/tablet/wacom_wac.c -index d96e186f71dc..e5cd0e57d178 100644 ---- a/drivers/input/tablet/wacom_wac.c -+++ b/drivers/input/tablet/wacom_wac.c -@@ -1434,7 +1434,7 @@ void wacom_setup_input_capabilities(struct input_dev *input_dev, +Index: linux-3.2.46/drivers/input/tablet/wacom_wac.c +=================================================================== +--- linux-3.2.46.orig/drivers/input/tablet/wacom_wac.c 2013-07-26 19:20:36.000000000 +0000 ++++ linux-3.2.46/drivers/input/tablet/wacom_wac.c 2013-07-26 19:20:37.000000000 +0000 +@@ -1434,7 +1434,7 @@ __set_bit(BTN_TOOL_TRIPLETAP, input_dev->keybit); __set_bit(BTN_TOOL_QUADTAP, input_dev->keybit); @@ -91,7 +91,7 @@ input_set_abs_params(input_dev, ABS_MT_TOUCH_MAJOR, 0, 255, 0, 0); -@@ -1467,7 +1467,7 @@ void wacom_setup_input_capabilities(struct input_dev *input_dev, +@@ -1467,7 +1467,7 @@ case TABLETPC2FG: if (features->device_type == BTN_TOOL_FINGER) { @@ -100,7 +100,7 @@ input_set_abs_params(input_dev, ABS_MT_TOOL_TYPE, 0, MT_TOOL_MAX, 0, 0); input_set_abs_params(input_dev, ABS_MT_POSITION_X, -@@ -1522,6 +1522,7 @@ void wacom_setup_input_capabilities(struct input_dev *input_dev, +@@ -1522,6 +1522,7 @@ __set_bit(BTN_TOOL_FINGER, input_dev->keybit); __set_bit(BTN_TOOL_DOUBLETAP, input_dev->keybit); @@ -108,7 +108,7 @@ if (features->pktlen == WACOM_PKGLEN_BBTOUCH3) { __set_bit(BTN_TOOL_TRIPLETAP, -@@ -1529,13 +1530,9 @@ void wacom_setup_input_capabilities(struct input_dev *input_dev, +@@ -1529,13 +1530,9 @@ __set_bit(BTN_TOOL_QUADTAP, input_dev->keybit); @@ -122,7 +122,7 @@ } input_set_abs_params(input_dev, ABS_MT_POSITION_X, -@@ -1724,13 +1721,16 @@ static const struct wacom_features wacom_features_0xBC = +@@ -1724,13 +1721,16 @@ 63, INTUOS4, WACOM_INTUOS3_RES, WACOM_INTUOS3_RES }; static const struct wacom_features wacom_features_0x26 = { "Wacom Intuos5 touch S", WACOM_PKGLEN_INTUOS, 31496, 19685, 2047, @@ -142,7 +142,7 @@ static const struct wacom_features wacom_features_0x29 = { "Wacom Intuos5 S", WACOM_PKGLEN_INTUOS, 31496, 19685, 2047, 63, INTUOS5S, WACOM_INTUOS3_RES, WACOM_INTUOS3_RES }; -@@ -1778,13 +1778,16 @@ static const struct wacom_features wacom_features_0x9F = +@@ -1778,13 +1778,16 @@ 0, TABLETPC, WACOM_INTUOS_RES, WACOM_INTUOS_RES }; static const struct wacom_features wacom_features_0xE2 = { "Wacom ISDv4 E2", WACOM_PKGLEN_TPC2FG, 26202, 16325, 255, @@ -162,7 +162,7 @@ static const struct wacom_features wacom_features_0xEC = { "Wacom ISDv4 EC", WACOM_PKGLEN_GRAPHIRE, 25710, 14500, 255, 0, TABLETPC, WACOM_INTUOS_RES, WACOM_INTUOS_RES }; -@@ -1793,19 +1796,22 @@ static const struct wacom_features wacom_features_0x47 = +@@ -1793,19 +1796,22 @@ 31, INTUOS, WACOM_INTUOS_RES, WACOM_INTUOS_RES }; static const struct wacom_features wacom_features_0x84 = { "Wacom Wireless Receiver", WACOM_PKGLEN_WIRELESS, 0, 0, 0, @@ -189,7 +189,7 @@ static const struct wacom_features wacom_features_0xD4 = { "Wacom Bamboo Pen", WACOM_PKGLEN_BBFUN, 14720, 9200, 1023, 31, BAMBOO_PT, WACOM_INTUOS_RES, WACOM_INTUOS_RES }; -@@ -1814,28 +1820,35 @@ static const struct wacom_features wacom_features_0xD5 = +@@ -1814,28 +1820,35 @@ 31, BAMBOO_PT, WACOM_INTUOS_RES, WACOM_INTUOS_RES }; static const struct wacom_features wacom_features_0xD6 = { "Wacom BambooPT 2FG 4x5", WACOM_PKGLEN_BBFUN, 14720, 9200, 1023, @@ -232,11 +232,11 @@ static const struct wacom_features wacom_features_0x6004 = { "ISD-V4", WACOM_PKGLEN_GRAPHIRE, 12800, 8000, 255, 0, TABLETPC, WACOM_INTUOS_RES, WACOM_INTUOS_RES }; -diff --git a/drivers/input/tablet/wacom_wac.h b/drivers/input/tablet/wacom_wac.h -index 17ba1868f0cd..321269c1ac4c 100644 ---- a/drivers/input/tablet/wacom_wac.h -+++ b/drivers/input/tablet/wacom_wac.h -@@ -99,6 +99,7 @@ struct wacom_features { +Index: linux-3.2.46/drivers/input/tablet/wacom_wac.h +=================================================================== +--- linux-3.2.46.orig/drivers/input/tablet/wacom_wac.h 2013-07-26 19:20:33.000000000 +0000 ++++ linux-3.2.46/drivers/input/tablet/wacom_wac.h 2013-07-26 19:20:37.000000000 +0000 +@@ -99,6 +99,7 @@ int pressure_fuzz; int distance_fuzz; unsigned quirks; @@ -244,6 +244,3 @@ }; struct wacom_shared { --- -1.7.10.1 - diff -Nru linux-3.2.46/debian/patches/features/all/wacom/0025-Input-wacom-add-0xE5-MT-device-support.patch linux-3.2.46/debian/patches/features/all/wacom/0025-Input-wacom-add-0xE5-MT-device-support.patch --- linux-3.2.46/debian/patches/features/all/wacom/0025-Input-wacom-add-0xE5-MT-device-support.patch 2013-02-24 03:52:33.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/wacom/0025-Input-wacom-add-0xE5-MT-device-support.patch 2013-07-26 19:20:39.000000000 +0000 @@ -28,11 +28,11 @@ drivers/input/tablet/wacom_wac.h | 8 +++ 4 files changed, 157 insertions(+), 45 deletions(-) -diff --git a/drivers/input/tablet/wacom.h b/drivers/input/tablet/wacom.h -index b4842d0e61dd..b79d45198d82 100644 ---- a/drivers/input/tablet/wacom.h -+++ b/drivers/input/tablet/wacom.h -@@ -135,6 +135,6 @@ extern const struct usb_device_id wacom_ids[]; +Index: linux-3.2.46/drivers/input/tablet/wacom.h +=================================================================== +--- linux-3.2.46.orig/drivers/input/tablet/wacom.h 2013-07-26 19:20:30.000000000 +0000 ++++ linux-3.2.46/drivers/input/tablet/wacom.h 2013-07-26 19:20:38.000000000 +0000 +@@ -135,6 +135,6 @@ void wacom_wac_irq(struct wacom_wac *wacom_wac, size_t len); void wacom_setup_device_quirks(struct wacom_features *features); @@ -41,11 +41,11 @@ +int wacom_setup_input_capabilities(struct input_dev *input_dev, + struct wacom_wac *wacom_wac); #endif -diff --git a/drivers/input/tablet/wacom_sys.c b/drivers/input/tablet/wacom_sys.c -index 53598c2065cf..734671aeb572 100644 ---- a/drivers/input/tablet/wacom_sys.c -+++ b/drivers/input/tablet/wacom_sys.c -@@ -317,6 +317,10 @@ static int wacom_parse_hid(struct usb_interface *intf, +Index: linux-3.2.46/drivers/input/tablet/wacom_sys.c +=================================================================== +--- linux-3.2.46.orig/drivers/input/tablet/wacom_sys.c 2013-07-26 19:20:37.000000000 +0000 ++++ linux-3.2.46/drivers/input/tablet/wacom_sys.c 2013-07-26 19:20:38.000000000 +0000 +@@ -317,6 +317,10 @@ /* need to reset back */ features->pktlen = WACOM_PKGLEN_TPC2FG; } @@ -56,7 +56,7 @@ if (features->type == BAMBOO_PT) { /* need to reset back */ features->pktlen = WACOM_PKGLEN_BBTOUCH; -@@ -349,18 +353,15 @@ static int wacom_parse_hid(struct usb_interface *intf, +@@ -349,18 +353,15 @@ case HID_USAGE_Y: if (usage == WCM_DESKTOP) { if (finger) { @@ -79,7 +79,7 @@ features->y_phy = get_unaligned_le16(&report[i + 3]); features->y_max = -@@ -374,10 +375,6 @@ static int wacom_parse_hid(struct usb_interface *intf, +@@ -374,10 +375,6 @@ i += 4; } } else if (pen) { @@ -90,7 +90,7 @@ features->y_max = get_unaligned_le16(&report[i + 3]); i += 4; -@@ -440,22 +437,29 @@ static int wacom_query_tablet_data(struct usb_interface *intf, struct wacom_feat +@@ -440,22 +437,29 @@ if (!rep_data) return error; @@ -136,7 +136,7 @@ } else if (features->type != TABLETPC && features->type != WIRELESS && features->device_type == BTN_TOOL_PEN) { -@@ -477,7 +481,7 @@ static int wacom_query_tablet_data(struct usb_interface *intf, struct wacom_feat +@@ -477,7 +481,7 @@ } static int wacom_retrieve_hid_descriptor(struct usb_interface *intf, @@ -145,7 +145,7 @@ { int error = 0; struct usb_host_interface *interface = intf->cur_altsetting; -@@ -505,10 +509,13 @@ static int wacom_retrieve_hid_descriptor(struct usb_interface *intf, +@@ -505,10 +509,13 @@ } } @@ -162,7 +162,7 @@ if (usb_get_extra_descriptor(interface, HID_DEVICET_HID, &hid_desc)) { if (usb_get_extra_descriptor(&interface->endpoint[0], -@@ -978,8 +985,10 @@ static int wacom_register_input(struct wacom *wacom) +@@ -978,8 +985,10 @@ int error; input_dev = input_allocate_device(); @@ -175,7 +175,7 @@ input_dev->name = wacom_wac->name; input_dev->dev.parent = &intf->dev; -@@ -989,14 +998,20 @@ static int wacom_register_input(struct wacom *wacom) +@@ -989,14 +998,20 @@ input_set_drvdata(input_dev, wacom); wacom_wac->input = input_dev; @@ -191,9 +191,9 @@ - } + if (error) + goto fail2; - -+ return 0; + ++ return 0; + +fail2: + input_free_device(input_dev); + wacom_wac->input = NULL; @@ -201,11 +201,11 @@ return error; } -diff --git a/drivers/input/tablet/wacom_wac.c b/drivers/input/tablet/wacom_wac.c -index e5cd0e57d178..10e5cf870359 100644 ---- a/drivers/input/tablet/wacom_wac.c -+++ b/drivers/input/tablet/wacom_wac.c -@@ -768,6 +768,72 @@ static int wacom_intuos_irq(struct wacom_wac *wacom) +Index: linux-3.2.46/drivers/input/tablet/wacom_wac.c +=================================================================== +--- linux-3.2.46.orig/drivers/input/tablet/wacom_wac.c 2013-07-26 19:20:37.000000000 +0000 ++++ linux-3.2.46/drivers/input/tablet/wacom_wac.c 2013-07-26 19:20:38.000000000 +0000 +@@ -768,6 +768,72 @@ return 1; } @@ -278,7 +278,7 @@ static int wacom_tpc_mt_touch(struct wacom_wac *wacom) { struct input_dev *input = wacom->input; -@@ -806,6 +872,9 @@ static int wacom_tpc_single_touch(struct wacom_wac *wacom, size_t len) +@@ -806,6 +872,9 @@ bool prox; int x = 0, y = 0; @@ -288,7 +288,7 @@ if (!wacom->shared->stylus_in_proximity) { if (len == WACOM_PKGLEN_TPC1FG) { prox = data[0] & 0x01; -@@ -873,10 +942,10 @@ static int wacom_tpc_irq(struct wacom_wac *wacom, size_t len) +@@ -873,10 +942,10 @@ switch (len) { case WACOM_PKGLEN_TPC1FG: @@ -301,7 +301,7 @@ default: switch (data[0]) { -@@ -885,6 +954,9 @@ static int wacom_tpc_irq(struct wacom_wac *wacom, size_t len) +@@ -885,6 +954,9 @@ case WACOM_REPORT_TPCST: return wacom_tpc_single_touch(wacom, len); @@ -311,7 +311,7 @@ case WACOM_REPORT_PENABLED: return wacom_tpc_pen(wacom); } -@@ -1164,6 +1236,7 @@ void wacom_wac_irq(struct wacom_wac *wacom_wac, size_t len) +@@ -1164,6 +1236,7 @@ case TABLETPC: case TABLETPC2FG: @@ -319,7 +319,7 @@ sync = wacom_tpc_irq(wacom_wac, len); break; -@@ -1237,7 +1310,8 @@ void wacom_setup_device_quirks(struct wacom_features *features) +@@ -1237,7 +1310,8 @@ /* these device have multiple inputs */ if (features->type == TABLETPC || features->type == TABLETPC2FG || features->type == BAMBOO_PT || features->type == WIRELESS || @@ -329,7 +329,7 @@ features->quirks |= WACOM_QUIRK_MULTI_INPUT; /* quirk for bamboo touch with 2 low res touches */ -@@ -1268,8 +1342,8 @@ static unsigned int wacom_calculate_touch_res(unsigned int logical_max, +@@ -1268,8 +1342,8 @@ return (logical_max * 100) / physical_max; } @@ -340,7 +340,7 @@ { struct wacom_features *features = &wacom_wac->features; int i; -@@ -1465,8 +1539,18 @@ void wacom_setup_input_capabilities(struct input_dev *input_dev, +@@ -1465,8 +1539,18 @@ break; case TABLETPC2FG: @@ -359,7 +359,7 @@ input_mt_init_slots(input_dev, features->touch_max); input_set_abs_params(input_dev, ABS_MT_TOOL_TYPE, 0, MT_TOOL_MAX, 0, 0); -@@ -1552,6 +1636,7 @@ void wacom_setup_input_capabilities(struct input_dev *input_dev, +@@ -1552,6 +1636,7 @@ } break; } @@ -367,7 +367,7 @@ } static const struct wacom_features wacom_features_0x00 = -@@ -1784,6 +1869,9 @@ static const struct wacom_features wacom_features_0xE3 = +@@ -1784,6 +1869,9 @@ { "Wacom ISDv4 E3", WACOM_PKGLEN_TPC2FG, 26202, 16325, 255, 0, TABLETPC2FG, WACOM_INTUOS_RES, WACOM_INTUOS_RES, .touch_max = 2 }; @@ -377,7 +377,7 @@ static const struct wacom_features wacom_features_0xE6 = { "Wacom ISDv4 E6", WACOM_PKGLEN_TPC2FG, 27760, 15694, 255, 0, TABLETPC2FG, WACOM_INTUOS_RES, WACOM_INTUOS_RES, -@@ -1962,6 +2050,7 @@ const struct usb_device_id wacom_ids[] = { +@@ -1962,6 +2050,7 @@ { USB_DEVICE_WACOM(0x9F) }, { USB_DEVICE_WACOM(0xE2) }, { USB_DEVICE_WACOM(0xE3) }, @@ -385,10 +385,10 @@ { USB_DEVICE_WACOM(0xE6) }, { USB_DEVICE_WACOM(0xEC) }, { USB_DEVICE_WACOM(0x47) }, -diff --git a/drivers/input/tablet/wacom_wac.h b/drivers/input/tablet/wacom_wac.h -index 321269c1ac4c..78fbd3f42009 100644 ---- a/drivers/input/tablet/wacom_wac.h -+++ b/drivers/input/tablet/wacom_wac.h +Index: linux-3.2.46/drivers/input/tablet/wacom_wac.h +=================================================================== +--- linux-3.2.46.orig/drivers/input/tablet/wacom_wac.h 2013-07-26 19:20:37.000000000 +0000 ++++ linux-3.2.46/drivers/input/tablet/wacom_wac.h 2013-07-26 19:20:38.000000000 +0000 @@ -25,6 +25,10 @@ #define WACOM_PKGLEN_BBTOUCH3 64 #define WACOM_PKGLEN_BBPEN 10 @@ -408,7 +408,7 @@ #define WACOM_REPORT_TPCHID 15 #define WACOM_REPORT_TPCST 16 -@@ -76,6 +81,7 @@ enum { +@@ -76,6 +81,7 @@ WACOM_MO, TABLETPC, TABLETPC2FG, @@ -416,7 +416,7 @@ MAX_TYPE }; -@@ -118,6 +124,8 @@ struct wacom_wac { +@@ -118,6 +124,8 @@ struct input_dev *input; int pid; int battery_capacity; @@ -425,6 +425,3 @@ }; #endif --- -1.7.10.1 - diff -Nru linux-3.2.46/debian/patches/features/all/wacom/0026-Input-wacom-return-proper-error-if-usb_get_extra_des.patch linux-3.2.46/debian/patches/features/all/wacom/0026-Input-wacom-return-proper-error-if-usb_get_extra_des.patch --- linux-3.2.46/debian/patches/features/all/wacom/0026-Input-wacom-return-proper-error-if-usb_get_extra_des.patch 2013-02-24 03:52:33.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/wacom/0026-Input-wacom-return-proper-error-if-usb_get_extra_des.patch 2013-07-26 19:20:41.000000000 +0000 @@ -14,11 +14,11 @@ drivers/input/tablet/wacom_sys.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) -diff --git a/drivers/input/tablet/wacom_sys.c b/drivers/input/tablet/wacom_sys.c -index 364f2c343..8f3b30b 100644 ---- a/drivers/input/tablet/wacom_sys.c -+++ b/drivers/input/tablet/wacom_sys.c -@@ -517,11 +517,12 @@ static int wacom_retrieve_hid_descriptor(struct usb_interface *intf, +Index: linux-3.2.46/drivers/input/tablet/wacom_sys.c +=================================================================== +--- linux-3.2.46.orig/drivers/input/tablet/wacom_sys.c 2013-07-26 19:20:38.000000000 +0000 ++++ linux-3.2.46/drivers/input/tablet/wacom_sys.c 2013-07-26 19:20:40.000000000 +0000 +@@ -517,11 +517,12 @@ goto out; } diff -Nru linux-3.2.46/debian/patches/features/all/wacom/0027-wacom-do-not-crash-when-retrieving-touch_max.patch linux-3.2.46/debian/patches/features/all/wacom/0027-wacom-do-not-crash-when-retrieving-touch_max.patch --- linux-3.2.46/debian/patches/features/all/wacom/0027-wacom-do-not-crash-when-retrieving-touch_max.patch 2013-04-11 03:27:33.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/wacom/0027-wacom-do-not-crash-when-retrieving-touch_max.patch 2013-07-26 19:20:42.000000000 +0000 @@ -15,9 +15,11 @@ drivers/input/tablet/wacom_sys.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) ---- a/drivers/input/tablet/wacom_sys.c -+++ b/drivers/input/tablet/wacom_sys.c -@@ -216,7 +216,7 @@ static void wacom_retrieve_report_data(struct usb_interface *intf, +Index: linux-3.2.46/drivers/input/tablet/wacom_sys.c +=================================================================== +--- linux-3.2.46.orig/drivers/input/tablet/wacom_sys.c 2013-07-26 19:20:40.000000000 +0000 ++++ linux-3.2.46/drivers/input/tablet/wacom_sys.c 2013-07-26 19:20:41.000000000 +0000 +@@ -213,7 +213,7 @@ rep_data[0] = 12; result = wacom_get_report(intf, WAC_HID_FEATURE_REPORT, diff -Nru linux-3.2.46/debian/patches/features/all/wacom/0028-wacom-leave-touch_max-as-is-if-predefined.patch linux-3.2.46/debian/patches/features/all/wacom/0028-wacom-leave-touch_max-as-is-if-predefined.patch --- linux-3.2.46/debian/patches/features/all/wacom/0028-wacom-leave-touch_max-as-is-if-predefined.patch 2013-04-11 03:27:33.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/wacom/0028-wacom-leave-touch_max-as-is-if-predefined.patch 2013-07-26 19:20:43.000000000 +0000 @@ -16,9 +16,11 @@ drivers/input/tablet/wacom_sys.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) ---- a/drivers/input/tablet/wacom_sys.c -+++ b/drivers/input/tablet/wacom_sys.c -@@ -401,7 +401,9 @@ static int wacom_parse_hid(struct usb_interface *intf, +Index: linux-3.2.46/drivers/input/tablet/wacom_sys.c +=================================================================== +--- linux-3.2.46.orig/drivers/input/tablet/wacom_sys.c 2013-07-26 19:20:41.000000000 +0000 ++++ linux-3.2.46/drivers/input/tablet/wacom_sys.c 2013-07-26 19:20:42.000000000 +0000 +@@ -398,7 +398,9 @@ break; case HID_USAGE_CONTACTMAX: diff -Nru linux-3.2.46/debian/patches/features/all/wacom/0029-wacom-do-not-request-tablet-data-on-MT-Tablet-PC-pen.patch linux-3.2.46/debian/patches/features/all/wacom/0029-wacom-do-not-request-tablet-data-on-MT-Tablet-PC-pen.patch --- linux-3.2.46/debian/patches/features/all/wacom/0029-wacom-do-not-request-tablet-data-on-MT-Tablet-PC-pen.patch 2013-04-11 03:27:33.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/wacom/0029-wacom-do-not-request-tablet-data-on-MT-Tablet-PC-pen.patch 2013-07-26 19:20:45.000000000 +0000 @@ -21,11 +21,11 @@ drivers/input/tablet/wacom_sys.c | 1 + 1 file changed, 1 insertion(+) -diff --git a/drivers/input/tablet/wacom_sys.c b/drivers/input/tablet/wacom_sys.c -index 8b31473a81fe..19e4725858dd 100644 ---- a/drivers/input/tablet/wacom_sys.c -+++ b/drivers/input/tablet/wacom_sys.c -@@ -467,6 +467,7 @@ static int wacom_query_tablet_data(struct usb_interface *intf, struct wacom_feat +Index: linux-3.2.46/drivers/input/tablet/wacom_sys.c +=================================================================== +--- linux-3.2.46.orig/drivers/input/tablet/wacom_sys.c 2013-07-26 19:20:42.000000000 +0000 ++++ linux-3.2.46/drivers/input/tablet/wacom_sys.c 2013-07-26 19:20:44.000000000 +0000 +@@ -464,6 +464,7 @@ } } else if (features->type != TABLETPC && features->type != WIRELESS && @@ -33,6 +33,3 @@ features->device_type == BTN_TOOL_PEN) { do { rep_data[0] = 2; --- -1.7.11.rc3 - diff -Nru linux-3.2.46/debian/patches/features/all/wacom/0030-wacom-ignore-new-style-Wacom-multi-touch-packets-on-.patch linux-3.2.46/debian/patches/features/all/wacom/0030-wacom-ignore-new-style-Wacom-multi-touch-packets-on-.patch --- linux-3.2.46/debian/patches/features/all/wacom/0030-wacom-ignore-new-style-Wacom-multi-touch-packets-on-.patch 2013-04-11 03:27:33.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/wacom/0030-wacom-ignore-new-style-Wacom-multi-touch-packets-on-.patch 2013-07-26 19:20:46.000000000 +0000 @@ -12,9 +12,11 @@ drivers/input/tablet/wacom_wac.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) ---- a/drivers/input/tablet/wacom_wac.c -+++ b/drivers/input/tablet/wacom_wac.c -@@ -1547,7 +1547,6 @@ int wacom_setup_input_capabilities(struct input_dev *input_dev, +Index: linux-3.2.46/drivers/input/tablet/wacom_wac.c +=================================================================== +--- linux-3.2.46.orig/drivers/input/tablet/wacom_wac.c 2013-07-26 19:20:38.000000000 +0000 ++++ linux-3.2.46/drivers/input/tablet/wacom_wac.c 2013-07-26 19:20:45.000000000 +0000 +@@ -1538,7 +1538,6 @@ __set_bit(INPUT_PROP_POINTER, input_dev->propbit); break; @@ -22,7 +24,7 @@ case MTSCREEN: if (features->device_type == BTN_TOOL_FINGER) { -@@ -1559,6 +1558,11 @@ int wacom_setup_input_capabilities(struct input_dev *input_dev, +@@ -1550,6 +1549,11 @@ for (i = 0; i < features->touch_max; i++) wacom_wac->slots[i] = -1; diff -Nru linux-3.2.46/debian/patches/features/all/wacom/0031-input-wacom-fix-touch-support-for-bamboo-fun-cth-461.patch linux-3.2.46/debian/patches/features/all/wacom/0031-input-wacom-fix-touch-support-for-bamboo-fun-cth-461.patch --- linux-3.2.46/debian/patches/features/all/wacom/0031-input-wacom-fix-touch-support-for-bamboo-fun-cth-461.patch 2013-02-24 03:52:33.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/wacom/0031-input-wacom-fix-touch-support-for-bamboo-fun-cth-461.patch 2013-07-26 19:20:47.000000000 +0000 @@ -19,11 +19,11 @@ drivers/input/tablet/wacom_wac.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) -diff --git a/drivers/input/tablet/wacom_wac.c b/drivers/input/tablet/wacom_wac.c -index 0a67031..c2bfe92 100644 ---- a/drivers/input/tablet/wacom_wac.c -+++ b/drivers/input/tablet/wacom_wac.c -@@ -2034,7 +2034,8 @@ static const struct wacom_features wacom_features_0xD1 = +Index: linux-3.2.46/drivers/input/tablet/wacom_wac.c +=================================================================== +--- linux-3.2.46.orig/drivers/input/tablet/wacom_wac.c 2013-07-26 19:20:45.000000000 +0000 ++++ linux-3.2.46/drivers/input/tablet/wacom_wac.c 2013-07-26 19:20:46.000000000 +0000 +@@ -1899,7 +1899,8 @@ .touch_max = 2 }; static const struct wacom_features wacom_features_0xD2 = { "Wacom Bamboo Craft", WACOM_PKGLEN_BBFUN, 14720, 9200, 1023, diff -Nru linux-3.2.46/debian/patches/features/all/wireless-rt2x00-rt2800pci-add-more-RT539x-ids.patch linux-3.2.46/debian/patches/features/all/wireless-rt2x00-rt2800pci-add-more-RT539x-ids.patch --- linux-3.2.46/debian/patches/features/all/wireless-rt2x00-rt2800pci-add-more-RT539x-ids.patch 2013-02-24 03:52:33.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/wireless-rt2x00-rt2800pci-add-more-RT539x-ids.patch 2013-07-26 19:25:15.000000000 +0000 @@ -17,11 +17,11 @@ drivers/net/wireless/rt2x00/rt2800pci.c | 2 ++ 1 file changed, 2 insertions(+) -diff --git a/drivers/net/wireless/rt2x00/rt2800pci.c b/drivers/net/wireless/rt2x00/rt2800pci.c -index f9f36cf..931331d 100644 ---- a/drivers/net/wireless/rt2x00/rt2800pci.c -+++ b/drivers/net/wireless/rt2x00/rt2800pci.c -@@ -1188,7 +1188,9 @@ static DEFINE_PCI_DEVICE_TABLE(rt2800pci_device_table) = { +Index: linux-3.2.46/drivers/net/wireless/rt2x00/rt2800pci.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/wireless/rt2x00/rt2800pci.c 2013-07-26 19:20:49.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rt2x00/rt2800pci.c 2013-07-26 19:25:14.000000000 +0000 +@@ -1154,7 +1154,9 @@ { PCI_DEVICE(0x1814, 0x3593) }, #endif #ifdef CONFIG_RT2800PCI_RT53XX diff -Nru linux-3.2.46/debian/patches/features/all/xen/microcode-amd-fam15plus.patch linux-3.2.46/debian/patches/features/all/xen/microcode-amd-fam15plus.patch --- linux-3.2.46/debian/patches/features/all/xen/microcode-amd-fam15plus.patch 2013-02-24 03:52:42.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/xen/microcode-amd-fam15plus.patch 2013-07-26 19:25:18.000000000 +0000 @@ -8,11 +8,11 @@ arch/x86/kernel/microcode_xen.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) -diff --git a/arch/x86/kernel/microcode_xen.c b/arch/x86/kernel/microcode_xen.c -index 9d2a06b..5fe87a6 100644 ---- a/arch/x86/kernel/microcode_xen.c -+++ b/arch/x86/kernel/microcode_xen.c -@@ -58,7 +58,7 @@ static int xen_microcode_update(int cpu) +Index: linux-3.2.46/arch/x86/kernel/microcode_xen.c +=================================================================== +--- linux-3.2.46.orig/arch/x86/kernel/microcode_xen.c 2013-07-26 19:25:07.000000000 +0000 ++++ linux-3.2.46/arch/x86/kernel/microcode_xen.c 2013-07-26 19:25:17.000000000 +0000 +@@ -58,7 +58,7 @@ static enum ucode_state xen_request_microcode_fw(int cpu, struct device *device) { @@ -21,7 +21,7 @@ struct cpuinfo_x86 *c = &cpu_data(cpu); const struct firmware *firmware; struct ucode_cpu_info *uci = ucode_cpu_info + cpu; -@@ -74,7 +74,11 @@ static enum ucode_state xen_request_microcode_fw(int cpu, struct device *device) +@@ -74,7 +74,11 @@ break; case X86_VENDOR_AMD: @@ -34,6 +34,3 @@ break; default: --- -1.7.10.4 - diff -Nru linux-3.2.46/debian/patches/features/all/xen/microcode.patch linux-3.2.46/debian/patches/features/all/xen/microcode.patch --- linux-3.2.46/debian/patches/features/all/xen/microcode.patch 2013-02-24 03:52:42.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/xen/microcode.patch 2013-07-26 19:25:08.000000000 +0000 @@ -25,10 +25,10 @@ 5 files changed, 216 insertions(+), 1 deletion(-) create mode 100644 arch/x86/kernel/microcode_xen.c -Index: linux/arch/x86/include/asm/microcode.h +Index: linux-3.2.46/arch/x86/include/asm/microcode.h =================================================================== ---- linux.orig/arch/x86/include/asm/microcode.h 2012-10-30 23:27:11.000000000 +0000 -+++ linux/arch/x86/include/asm/microcode.h 2012-11-09 10:59:49.000000000 +0000 +--- linux-3.2.46.orig/arch/x86/include/asm/microcode.h 2013-07-26 18:54:03.000000000 +0000 ++++ linux-3.2.46/arch/x86/include/asm/microcode.h 2013-07-26 19:25:07.000000000 +0000 @@ -61,4 +61,13 @@ } #endif @@ -43,10 +43,10 @@ +#endif + #endif /* _ASM_X86_MICROCODE_H */ -Index: linux/arch/x86/kernel/Makefile +Index: linux-3.2.46/arch/x86/kernel/Makefile =================================================================== ---- linux.orig/arch/x86/kernel/Makefile 2012-10-30 23:27:11.000000000 +0000 -+++ linux/arch/x86/kernel/Makefile 2012-11-09 10:59:49.000000000 +0000 +--- linux-3.2.46.orig/arch/x86/kernel/Makefile 2013-07-26 18:54:03.000000000 +0000 ++++ linux-3.2.46/arch/x86/kernel/Makefile 2013-07-26 19:25:07.000000000 +0000 @@ -92,6 +92,7 @@ microcode-y := microcode_core.o microcode-$(CONFIG_MICROCODE_INTEL) += microcode_intel.o @@ -55,10 +55,10 @@ obj-$(CONFIG_MICROCODE) += microcode.o obj-$(CONFIG_X86_CHECK_BIOS_CORRUPTION) += check.o -Index: linux/arch/x86/kernel/microcode_core.c +Index: linux-3.2.46/arch/x86/kernel/microcode_core.c =================================================================== ---- linux.orig/arch/x86/kernel/microcode_core.c 2012-11-09 10:18:15.000000000 +0000 -+++ linux/arch/x86/kernel/microcode_core.c 2012-11-09 10:59:49.000000000 +0000 +--- linux-3.2.46.orig/arch/x86/kernel/microcode_core.c 2013-07-26 19:22:54.000000000 +0000 ++++ linux-3.2.46/arch/x86/kernel/microcode_core.c 2013-07-26 19:25:07.000000000 +0000 @@ -84,6 +84,7 @@ #include #include @@ -78,10 +78,10 @@ microcode_ops = init_intel_microcode(); else if (c->x86_vendor == X86_VENDOR_AMD) microcode_ops = init_amd_microcode(); -Index: linux/arch/x86/kernel/microcode_xen.c +Index: linux-3.2.46/arch/x86/kernel/microcode_xen.c =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 -+++ linux/arch/x86/kernel/microcode_xen.c 2012-11-09 10:59:49.000000000 +0000 ++++ linux-3.2.46/arch/x86/kernel/microcode_xen.c 2013-07-26 19:25:07.000000000 +0000 @@ -0,0 +1,198 @@ +/* + * Xen microcode update driver @@ -281,10 +281,10 @@ + return NULL; + return µcode_xen_ops; +} -Index: linux/arch/x86/xen/Kconfig +Index: linux-3.2.46/arch/x86/xen/Kconfig =================================================================== ---- linux.orig/arch/x86/xen/Kconfig 2012-10-30 23:27:11.000000000 +0000 -+++ linux/arch/x86/xen/Kconfig 2012-11-09 11:00:42.000000000 +0000 +--- linux-3.2.46.orig/arch/x86/xen/Kconfig 2013-07-26 18:54:03.000000000 +0000 ++++ linux-3.2.46/arch/x86/xen/Kconfig 2013-07-26 19:25:07.000000000 +0000 @@ -48,3 +48,7 @@ help Enable statistics output and various tuning options in debugfs. diff -Nru linux-3.2.46/debian/patches/features/all/xen/microcode-typo.patch linux-3.2.46/debian/patches/features/all/xen/microcode-typo.patch --- linux-3.2.46/debian/patches/features/all/xen/microcode-typo.patch 2013-02-24 03:52:42.000000000 +0000 +++ linux-3.2.46/debian/patches/features/all/xen/microcode-typo.patch 2013-07-26 19:25:19.000000000 +0000 @@ -1,9 +1,9 @@ http://git.kernel.org/?p=linux/kernel/git/konrad/xen.git;a=commitdiff;h=f6c958ff0d00ffbf1cdc8fcf2f2a82f06fbbb5f4 -Index: linux/arch/x86/kernel/microcode_xen.c +Index: linux-3.2.46/arch/x86/kernel/microcode_xen.c =================================================================== ---- linux.orig/arch/x86/kernel/microcode_xen.c 2012-12-05 13:31:49.000000000 +0000 -+++ linux/arch/x86/kernel/microcode_xen.c 2012-12-05 13:32:10.000000000 +0000 +--- linux-3.2.46.orig/arch/x86/kernel/microcode_xen.c 2013-07-26 19:25:17.000000000 +0000 ++++ linux-3.2.46/arch/x86/kernel/microcode_xen.c 2013-07-26 19:25:18.000000000 +0000 @@ -161,7 +161,7 @@ ret = UCODE_OK; diff -Nru linux-3.2.46/debian/patches/features/arm/ahci-Add-JMicron-362-device-IDs.patch linux-3.2.46/debian/patches/features/arm/ahci-Add-JMicron-362-device-IDs.patch --- linux-3.2.46/debian/patches/features/arm/ahci-Add-JMicron-362-device-IDs.patch 2013-02-24 03:52:25.000000000 +0000 +++ linux-3.2.46/debian/patches/features/arm/ahci-Add-JMicron-362-device-IDs.patch 2013-07-26 19:24:58.000000000 +0000 @@ -17,11 +17,11 @@ drivers/ata/ahci.c | 3 +++ 1 file changed, 3 insertions(+) -diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c -index 50d5dea..c3f52eb 100644 ---- a/drivers/ata/ahci.c -+++ b/drivers/ata/ahci.c -@@ -268,6 +268,9 @@ static const struct pci_device_id ahci_pci_tbl[] = { +Index: linux-3.2.46/drivers/ata/ahci.c +=================================================================== +--- linux-3.2.46.orig/drivers/ata/ahci.c 2013-07-26 18:54:05.000000000 +0000 ++++ linux-3.2.46/drivers/ata/ahci.c 2013-07-26 19:24:57.000000000 +0000 +@@ -306,6 +306,9 @@ /* JMicron 360/1/3/5/6, match class to avoid IDE function */ { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr }, diff -Nru linux-3.2.46/debian/patches/features/arm/ARM-7259-3-net-JIT-compiler-for-packet-filters.patch linux-3.2.46/debian/patches/features/arm/ARM-7259-3-net-JIT-compiler-for-packet-filters.patch --- linux-3.2.46/debian/patches/features/arm/ARM-7259-3-net-JIT-compiler-for-packet-filters.patch 2013-04-11 03:27:32.000000000 +0000 +++ linux-3.2.46/debian/patches/features/arm/ARM-7259-3-net-JIT-compiler-for-packet-filters.patch 2013-07-26 19:24:03.000000000 +0000 @@ -35,10 +35,10 @@ create mode 100644 arch/arm/net/bpf_jit_32.c create mode 100644 arch/arm/net/bpf_jit_32.h -Index: linux/arch/arm/Kconfig +Index: linux-3.2.46/arch/arm/Kconfig =================================================================== ---- linux.orig/arch/arm/Kconfig 2012-06-20 00:18:30.000000000 +0200 -+++ linux/arch/arm/Kconfig 2012-06-24 23:38:52.000000000 +0200 +--- linux-3.2.46.orig/arch/arm/Kconfig 2013-07-26 18:54:24.000000000 +0000 ++++ linux-3.2.46/arch/arm/Kconfig 2013-07-26 19:24:01.000000000 +0000 @@ -30,6 +30,7 @@ select HAVE_SPARSE_IRQ select GENERIC_IRQ_SHOW @@ -47,10 +47,10 @@ help The ARM series is a line of low-power-consumption RISC chip designs licensed by ARM Ltd and targeted at embedded applications and -Index: linux/arch/arm/Makefile +Index: linux-3.2.46/arch/arm/Makefile =================================================================== ---- linux.orig/arch/arm/Makefile 2012-06-20 00:18:30.000000000 +0200 -+++ linux/arch/arm/Makefile 2012-06-24 23:38:52.000000000 +0200 +--- linux-3.2.46.orig/arch/arm/Makefile 2013-07-26 18:54:24.000000000 +0000 ++++ linux-3.2.46/arch/arm/Makefile 2013-07-26 19:24:01.000000000 +0000 @@ -255,6 +255,7 @@ # If we have a machine-specific directory, then include it in the build. @@ -59,18 +59,18 @@ core-y += $(machdirs) $(platdirs) drivers-$(CONFIG_OPROFILE) += arch/arm/oprofile/ -Index: linux/arch/arm/net/Makefile +Index: linux-3.2.46/arch/arm/net/Makefile =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 -+++ linux/arch/arm/net/Makefile 2012-06-24 23:38:52.000000000 +0200 ++++ linux-3.2.46/arch/arm/net/Makefile 2013-07-26 19:24:01.000000000 +0000 @@ -0,0 +1,3 @@ +# ARM-specific networking code + +obj-$(CONFIG_BPF_JIT) += bpf_jit_32.o -Index: linux/arch/arm/net/bpf_jit_32.c +Index: linux-3.2.46/arch/arm/net/bpf_jit_32.c =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 -+++ linux/arch/arm/net/bpf_jit_32.c 2012-06-24 23:38:52.000000000 +0200 ++++ linux-3.2.46/arch/arm/net/bpf_jit_32.c 2013-07-26 19:24:01.000000000 +0000 @@ -0,0 +1,915 @@ +/* + * Just-In-Time compiler for BPF filters on 32bit ARM @@ -987,10 +987,10 @@ + schedule_work(work); + } +} -Index: linux/arch/arm/net/bpf_jit_32.h +Index: linux-3.2.46/arch/arm/net/bpf_jit_32.h =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 -+++ linux/arch/arm/net/bpf_jit_32.h 2012-06-24 23:38:52.000000000 +0200 ++++ linux-3.2.46/arch/arm/net/bpf_jit_32.h 2013-07-26 19:24:01.000000000 +0000 @@ -0,0 +1,190 @@ +/* + * Just-In-Time compiler for BPF filters on 32bit ARM diff -Nru linux-3.2.46/debian/patches/features/arm/ARM-fix-Kconfig-warning-for-HAVE_BPF_JIT.patch linux-3.2.46/debian/patches/features/arm/ARM-fix-Kconfig-warning-for-HAVE_BPF_JIT.patch --- linux-3.2.46/debian/patches/features/arm/ARM-fix-Kconfig-warning-for-HAVE_BPF_JIT.patch 2013-04-11 03:27:32.000000000 +0000 +++ linux-3.2.46/debian/patches/features/arm/ARM-fix-Kconfig-warning-for-HAVE_BPF_JIT.patch 2013-07-26 19:24:04.000000000 +0000 @@ -15,10 +15,10 @@ arch/arm/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -Index: linux/arch/arm/Kconfig +Index: linux-3.2.46/arch/arm/Kconfig =================================================================== ---- linux.orig/arch/arm/Kconfig 2012-06-24 23:38:52.000000000 +0200 -+++ linux/arch/arm/Kconfig 2012-06-24 23:41:24.000000000 +0200 +--- linux-3.2.46.orig/arch/arm/Kconfig 2013-07-26 19:24:01.000000000 +0000 ++++ linux-3.2.46/arch/arm/Kconfig 2013-07-26 19:24:03.000000000 +0000 @@ -30,7 +30,7 @@ select HAVE_SPARSE_IRQ select GENERIC_IRQ_SHOW diff -Nru linux-3.2.46/debian/patches/features/arm/ARM-kirkwood-6282A1.patch linux-3.2.46/debian/patches/features/arm/ARM-kirkwood-6282A1.patch --- linux-3.2.46/debian/patches/features/arm/ARM-kirkwood-6282A1.patch 2013-02-24 03:52:25.000000000 +0000 +++ linux-3.2.46/debian/patches/features/arm/ARM-kirkwood-6282A1.patch 2013-07-26 19:17:40.000000000 +0000 @@ -11,11 +11,11 @@ Acked-by: Lennert Buytenhek Signed-off-by: Nicolas Pitre -diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c -index f3248cf..b9632ee 100644 ---- a/arch/arm/mach-kirkwood/common.c -+++ b/arch/arm/mach-kirkwood/common.c -@@ -430,6 +430,8 @@ static char * __init kirkwood_id(void) +Index: linux-3.2.46/arch/arm/mach-kirkwood/common.c +=================================================================== +--- linux-3.2.46.orig/arch/arm/mach-kirkwood/common.c 2013-07-26 18:56:27.000000000 +0000 ++++ linux-3.2.46/arch/arm/mach-kirkwood/common.c 2013-07-26 19:17:39.000000000 +0000 +@@ -431,6 +431,8 @@ } else if (dev == MV88F6282_DEV_ID) { if (rev == MV88F6282_REV_A0) return "MV88F6282-Rev-A0"; @@ -24,10 +24,10 @@ else return "MV88F6282-Rev-Unsupported"; } else { -diff --git a/arch/arm/mach-kirkwood/include/mach/kirkwood.h b/arch/arm/mach-kirkwood/include/mach/kirkwood.h -index 010bdeb..fede3d5 100644 ---- a/arch/arm/mach-kirkwood/include/mach/kirkwood.h -+++ b/arch/arm/mach-kirkwood/include/mach/kirkwood.h +Index: linux-3.2.46/arch/arm/mach-kirkwood/include/mach/kirkwood.h +=================================================================== +--- linux-3.2.46.orig/arch/arm/mach-kirkwood/include/mach/kirkwood.h 2013-07-26 18:56:27.000000000 +0000 ++++ linux-3.2.46/arch/arm/mach-kirkwood/include/mach/kirkwood.h 2013-07-26 19:17:39.000000000 +0000 @@ -135,4 +135,5 @@ #define MV88F6282_DEV_ID 0x6282 diff -Nru linux-3.2.46/debian/patches/features/arm/kirkwood-add-configuration-for-mpp12-as-gpio.patch linux-3.2.46/debian/patches/features/arm/kirkwood-add-configuration-for-mpp12-as-gpio.patch --- linux-3.2.46/debian/patches/features/arm/kirkwood-add-configuration-for-mpp12-as-gpio.patch 2013-04-11 03:27:32.000000000 +0000 +++ linux-3.2.46/debian/patches/features/arm/kirkwood-add-configuration-for-mpp12-as-gpio.patch 2013-07-26 19:23:58.000000000 +0000 @@ -13,10 +13,10 @@ Signed-off-by: Arnaud Patard Signed-off-by: Nicolas Pitre -Index: sid/arch/arm/mach-kirkwood/mpp.h +Index: linux-3.2.46/arch/arm/mach-kirkwood/mpp.h =================================================================== ---- sid.orig/arch/arm/mach-kirkwood/mpp.h 2012-05-31 01:44:12.000000000 +0200 -+++ sid/arch/arm/mach-kirkwood/mpp.h 2012-06-10 10:18:11.502678583 +0200 +--- linux-3.2.46.orig/arch/arm/mach-kirkwood/mpp.h 2013-07-26 18:54:26.000000000 +0000 ++++ linux-3.2.46/arch/arm/mach-kirkwood/mpp.h 2013-07-26 19:23:57.000000000 +0000 @@ -102,6 +102,7 @@ #define MPP11_SATA0_ACTn MPP( 11, 0x5, 0, 0, 0, 1, 1, 1, 1 ) diff -Nru linux-3.2.46/debian/patches/features/arm/kirkwood-add-dreamplug-fdt-support.patch linux-3.2.46/debian/patches/features/arm/kirkwood-add-dreamplug-fdt-support.patch --- linux-3.2.46/debian/patches/features/arm/kirkwood-add-dreamplug-fdt-support.patch 2013-04-11 03:27:32.000000000 +0000 +++ linux-3.2.46/debian/patches/features/arm/kirkwood-add-dreamplug-fdt-support.patch 2013-07-26 19:23:43.000000000 +0000 @@ -22,11 +22,10 @@ Acked-by: Nicolas Pitre Signed-off-by: Arnd Bergmann -diff --git a/arch/arm/boot/dts/kirkwood-dreamplug.dts b/arch/arm/boot/dts/kirkwood-dreamplug.dts -new file mode 100644 -index 0000000..0424d99 ---- /dev/null -+++ b/arch/arm/boot/dts/kirkwood-dreamplug.dts +Index: linux-3.2.46/arch/arm/boot/dts/kirkwood-dreamplug.dts +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/arch/arm/boot/dts/kirkwood-dreamplug.dts 2013-07-26 19:23:41.000000000 +0000 @@ -0,0 +1,18 @@ +/dts-v1/; + @@ -46,11 +45,10 @@ + }; + +}; -diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi -new file mode 100644 -index 0000000..771c6bb ---- /dev/null -+++ b/arch/arm/boot/dts/kirkwood.dtsi +Index: linux-3.2.46/arch/arm/boot/dts/kirkwood.dtsi +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/arch/arm/boot/dts/kirkwood.dtsi 2013-07-26 19:23:41.000000000 +0000 @@ -0,0 +1,6 @@ +/include/ "skeleton.dtsi" + @@ -58,11 +56,11 @@ + compatible = "marvell,kirkwood"; +}; + -diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig -index 7fc603b..90ceab7 100644 ---- a/arch/arm/mach-kirkwood/Kconfig -+++ b/arch/arm/mach-kirkwood/Kconfig -@@ -44,6 +44,20 @@ config MACH_GURUPLUG +Index: linux-3.2.46/arch/arm/mach-kirkwood/Kconfig +=================================================================== +--- linux-3.2.46.orig/arch/arm/mach-kirkwood/Kconfig 2013-07-26 18:54:31.000000000 +0000 ++++ linux-3.2.46/arch/arm/mach-kirkwood/Kconfig 2013-07-26 19:23:41.000000000 +0000 +@@ -44,6 +44,20 @@ Say 'Y' here if you want your kernel to support the Marvell GuruPlug Reference Board. @@ -83,30 +81,29 @@ config MACH_TS219 bool "QNAP TS-110, TS-119, TS-119P+, TS-210, TS-219, TS-219P and TS-219P+ Turbo NAS" help -diff --git a/arch/arm/mach-kirkwood/Makefile b/arch/arm/mach-kirkwood/Makefile -index 5dcaa81..acbc5e1 100644 ---- a/arch/arm/mach-kirkwood/Makefile -+++ b/arch/arm/mach-kirkwood/Makefile -@@ -20,3 +20,4 @@ obj-$(CONFIG_MACH_NET5BIG_V2) += netxbig_v2-setup.o lacie_v2-common.o +Index: linux-3.2.46/arch/arm/mach-kirkwood/Makefile +=================================================================== +--- linux-3.2.46.orig/arch/arm/mach-kirkwood/Makefile 2013-07-26 18:54:31.000000000 +0000 ++++ linux-3.2.46/arch/arm/mach-kirkwood/Makefile 2013-07-26 19:23:41.000000000 +0000 +@@ -20,3 +20,4 @@ obj-$(CONFIG_MACH_T5325) += t5325-setup.o obj-$(CONFIG_CPU_IDLE) += cpuidle.o +obj-$(CONFIG_ARCH_KIRKWOOD_DT) += board-dt.o -diff --git a/arch/arm/mach-kirkwood/Makefile.boot b/arch/arm/mach-kirkwood/Makefile.boot -index 760a0ef..16f9385 100644 ---- a/arch/arm/mach-kirkwood/Makefile.boot -+++ b/arch/arm/mach-kirkwood/Makefile.boot +Index: linux-3.2.46/arch/arm/mach-kirkwood/Makefile.boot +=================================================================== +--- linux-3.2.46.orig/arch/arm/mach-kirkwood/Makefile.boot 2013-07-26 18:54:31.000000000 +0000 ++++ linux-3.2.46/arch/arm/mach-kirkwood/Makefile.boot 2013-07-26 19:23:41.000000000 +0000 @@ -1,3 +1,5 @@ zreladdr-y += 0x00008000 params_phys-y := 0x00000100 initrd_phys-y := 0x00800000 + +dtb-$(CONFIG_MACH_DREAMPLUG_DT) += kirkwood-dreamplug.dtb -diff --git a/arch/arm/mach-kirkwood/board-dt.c b/arch/arm/mach-kirkwood/board-dt.c -new file mode 100644 -index 0000000..76392af ---- /dev/null -+++ b/arch/arm/mach-kirkwood/board-dt.c +Index: linux-3.2.46/arch/arm/mach-kirkwood/board-dt.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/arch/arm/mach-kirkwood/board-dt.c 2013-07-26 19:23:41.000000000 +0000 @@ -0,0 +1,181 @@ +/* + * Copyright 2012 (C), Jason Cooper diff -Nru linux-3.2.46/debian/patches/features/arm/kirkwood-add-iconnect-support.patch linux-3.2.46/debian/patches/features/arm/kirkwood-add-iconnect-support.patch --- linux-3.2.46/debian/patches/features/arm/kirkwood-add-iconnect-support.patch 2013-04-11 03:27:32.000000000 +0000 +++ linux-3.2.46/debian/patches/features/arm/kirkwood-add-iconnect-support.patch 2013-07-26 19:23:59.000000000 +0000 @@ -10,10 +10,10 @@ Tested-By: Adam Baker Signed-off-by: Jason Cooper -Index: sid/arch/arm/boot/dts/kirkwood-iconnect.dts +Index: linux-3.2.46/arch/arm/boot/dts/kirkwood-iconnect.dts =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 -+++ sid/arch/arm/boot/dts/kirkwood-iconnect.dts 2012-06-10 01:24:28.300087489 +0200 ++++ linux-3.2.46/arch/arm/boot/dts/kirkwood-iconnect.dts 2013-07-26 19:23:58.000000000 +0000 @@ -0,0 +1,26 @@ +/dts-v1/; + @@ -41,11 +41,11 @@ + }; + }; +}; -Index: sid/arch/arm/mach-kirkwood/Kconfig +Index: linux-3.2.46/arch/arm/mach-kirkwood/Kconfig =================================================================== ---- sid.orig/arch/arm/mach-kirkwood/Kconfig 2012-06-10 01:13:01.000000000 +0200 -+++ sid/arch/arm/mach-kirkwood/Kconfig 2012-06-10 01:24:28.300087489 +0200 -@@ -58,6 +58,12 @@ config MACH_DREAMPLUG_DT +--- linux-3.2.46.orig/arch/arm/mach-kirkwood/Kconfig 2013-07-26 19:23:41.000000000 +0000 ++++ linux-3.2.46/arch/arm/mach-kirkwood/Kconfig 2013-07-26 19:23:58.000000000 +0000 +@@ -58,6 +58,12 @@ Say 'Y' here if you want your kernel to support the Marvell DreamPlug (Flattened Device Tree). @@ -58,29 +58,29 @@ config MACH_TS219 bool "QNAP TS-110, TS-119, TS-119P+, TS-210, TS-219, TS-219P and TS-219P+ Turbo NAS" help -Index: sid/arch/arm/mach-kirkwood/Makefile +Index: linux-3.2.46/arch/arm/mach-kirkwood/Makefile =================================================================== ---- sid.orig/arch/arm/mach-kirkwood/Makefile 2012-06-10 01:13:58.000000000 +0200 -+++ sid/arch/arm/mach-kirkwood/Makefile 2012-06-10 01:24:28.300087489 +0200 -@@ -22,3 +22,4 @@ obj-$(CONFIG_MACH_T5325) += t5325-setup +--- linux-3.2.46.orig/arch/arm/mach-kirkwood/Makefile 2013-07-26 19:23:47.000000000 +0000 ++++ linux-3.2.46/arch/arm/mach-kirkwood/Makefile 2013-07-26 19:23:58.000000000 +0000 +@@ -22,3 +22,4 @@ obj-$(CONFIG_CPU_IDLE) += cpuidle.o obj-$(CONFIG_ARCH_KIRKWOOD_DT) += board-dt.o obj-$(CONFIG_MACH_DREAMPLUG_DT) += board-dreamplug.o +obj-$(CONFIG_MACH_ICONNECT_DT) += board-iconnect.o -Index: sid/arch/arm/mach-kirkwood/Makefile.boot +Index: linux-3.2.46/arch/arm/mach-kirkwood/Makefile.boot =================================================================== ---- sid.orig/arch/arm/mach-kirkwood/Makefile.boot 2012-06-10 01:13:01.000000000 +0200 -+++ sid/arch/arm/mach-kirkwood/Makefile.boot 2012-06-10 01:24:28.300087489 +0200 -@@ -3,3 +3,4 @@ params_phys-y := 0x00000100 +--- linux-3.2.46.orig/arch/arm/mach-kirkwood/Makefile.boot 2013-07-26 19:23:41.000000000 +0000 ++++ linux-3.2.46/arch/arm/mach-kirkwood/Makefile.boot 2013-07-26 19:23:58.000000000 +0000 +@@ -3,3 +3,4 @@ initrd_phys-y := 0x00800000 dtb-$(CONFIG_MACH_DREAMPLUG_DT) += kirkwood-dreamplug.dtb +dtb-$(CONFIG_MACH_ICONNECT_DT) += kirkwood-iconnect.dtb -Index: sid/arch/arm/mach-kirkwood/board-dt.c +Index: linux-3.2.46/arch/arm/mach-kirkwood/board-dt.c =================================================================== ---- sid.orig/arch/arm/mach-kirkwood/board-dt.c 2012-06-10 01:14:30.000000000 +0200 -+++ sid/arch/arm/mach-kirkwood/board-dt.c 2012-06-10 01:24:28.300087489 +0200 -@@ -56,11 +56,15 @@ static void __init kirkwood_dt_init(void +--- linux-3.2.46.orig/arch/arm/mach-kirkwood/board-dt.c 2013-07-26 19:23:53.000000000 +0000 ++++ linux-3.2.46/arch/arm/mach-kirkwood/board-dt.c 2013-07-26 19:23:58.000000000 +0000 +@@ -56,11 +56,15 @@ if (of_machine_is_compatible("globalscale,dreamplug")) dreamplug_init(); @@ -96,10 +96,10 @@ NULL }; -Index: sid/arch/arm/mach-kirkwood/board-iconnect.c +Index: linux-3.2.46/arch/arm/mach-kirkwood/board-iconnect.c =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 -+++ sid/arch/arm/mach-kirkwood/board-iconnect.c 2012-06-10 01:24:28.300087489 +0200 ++++ linux-3.2.46/arch/arm/mach-kirkwood/board-iconnect.c 2013-07-26 19:23:58.000000000 +0000 @@ -0,0 +1,165 @@ +/* + * arch/arm/mach-kirkwood/board-iconnect.c @@ -266,11 +266,11 @@ + return 0; +} +subsys_initcall(iconnect_pci_init); -Index: sid/arch/arm/mach-kirkwood/common.h +Index: linux-3.2.46/arch/arm/mach-kirkwood/common.h =================================================================== ---- sid.orig/arch/arm/mach-kirkwood/common.h 2012-06-10 01:14:15.000000000 +0200 -+++ sid/arch/arm/mach-kirkwood/common.h 2012-06-10 01:24:28.300087489 +0200 -@@ -58,6 +58,12 @@ void dreamplug_init(void); +--- linux-3.2.46.orig/arch/arm/mach-kirkwood/common.h 2013-07-26 19:23:51.000000000 +0000 ++++ linux-3.2.46/arch/arm/mach-kirkwood/common.h 2013-07-26 19:23:58.000000000 +0000 +@@ -58,6 +58,12 @@ static inline void dreamplug_init(void) {}; #endif diff -Nru linux-3.2.46/debian/patches/features/arm/kirkwood_add_missing_kexec_h.patch linux-3.2.46/debian/patches/features/arm/kirkwood_add_missing_kexec_h.patch --- linux-3.2.46/debian/patches/features/arm/kirkwood_add_missing_kexec_h.patch 2013-04-11 03:27:32.000000000 +0000 +++ linux-3.2.46/debian/patches/features/arm/kirkwood_add_missing_kexec_h.patch 2013-07-26 19:23:53.000000000 +0000 @@ -16,10 +16,10 @@ [v2, using linux/kexec.h not asm/kexec.h] Signed-off-by: Jason Cooper -diff --git a/arch/arm/mach-kirkwood/board-dt.c b/arch/arm/mach-kirkwood/board-dt.c -index 1c672d9..f7fe1b9 100644 ---- a/arch/arm/mach-kirkwood/board-dt.c -+++ b/arch/arm/mach-kirkwood/board-dt.c +Index: linux-3.2.46/arch/arm/mach-kirkwood/board-dt.c +=================================================================== +--- linux-3.2.46.orig/arch/arm/mach-kirkwood/board-dt.c 2013-07-26 19:23:51.000000000 +0000 ++++ linux-3.2.46/arch/arm/mach-kirkwood/board-dt.c 2013-07-26 19:23:53.000000000 +0000 @@ -14,6 +14,7 @@ #include #include diff -Nru linux-3.2.46/debian/patches/features/arm/kirkwood-create-a-generic-function-for-gpio-led-blinking.patch linux-3.2.46/debian/patches/features/arm/kirkwood-create-a-generic-function-for-gpio-led-blinking.patch --- linux-3.2.46/debian/patches/features/arm/kirkwood-create-a-generic-function-for-gpio-led-blinking.patch 2013-04-11 03:27:32.000000000 +0000 +++ linux-3.2.46/debian/patches/features/arm/kirkwood-create-a-generic-function-for-gpio-led-blinking.patch 2013-07-26 19:23:56.000000000 +0000 @@ -12,11 +12,11 @@ Tested-By: Adam Baker Signed-off-by: Jason Cooper -diff --git a/arch/arm/mach-orion5x/dns323-setup.c b/arch/arm/mach-orion5x/dns323-setup.c -index c3ed15b..13d2bec 100644 ---- a/arch/arm/mach-orion5x/dns323-setup.c -+++ b/arch/arm/mach-orion5x/dns323-setup.c -@@ -253,27 +253,6 @@ error_fail: +Index: linux-3.2.46/arch/arm/mach-orion5x/dns323-setup.c +=================================================================== +--- linux-3.2.46.orig/arch/arm/mach-orion5x/dns323-setup.c 2013-07-26 18:54:26.000000000 +0000 ++++ linux-3.2.46/arch/arm/mach-orion5x/dns323-setup.c 2013-07-26 19:23:55.000000000 +0000 +@@ -252,27 +252,6 @@ * GPIO LEDs (simple - doesn't use hardware blinking support) */ @@ -44,7 +44,7 @@ static struct gpio_led dns323ab_leds[] = { { .name = "power:blue", -@@ -312,13 +291,13 @@ static struct gpio_led dns323c_leds[] = { +@@ -311,13 +290,13 @@ static struct gpio_led_platform_data dns323ab_led_data = { .num_leds = ARRAY_SIZE(dns323ab_leds), .leds = dns323ab_leds, @@ -60,10 +60,10 @@ }; static struct platform_device dns323_gpio_leds = { -diff --git a/arch/arm/plat-orion/gpio.c b/arch/arm/plat-orion/gpio.c -index d3401e7..af95af2 100644 ---- a/arch/arm/plat-orion/gpio.c -+++ b/arch/arm/plat-orion/gpio.c +Index: linux-3.2.46/arch/arm/plat-orion/gpio.c +=================================================================== +--- linux-3.2.46.orig/arch/arm/plat-orion/gpio.c 2013-07-26 19:23:54.000000000 +0000 ++++ linux-3.2.46/arch/arm/plat-orion/gpio.c 2013-07-26 19:23:55.000000000 +0000 @@ -16,6 +16,7 @@ #include #include @@ -72,7 +72,7 @@ /* * GPIO unit register offsets. -@@ -295,6 +296,28 @@ void orion_gpio_set_blink(unsigned pin, int blink) +@@ -295,6 +296,28 @@ } EXPORT_SYMBOL(orion_gpio_set_blink); @@ -101,10 +101,10 @@ /***************************************************************************** * Orion GPIO IRQ -diff --git a/arch/arm/plat-orion/include/plat/gpio.h b/arch/arm/plat-orion/include/plat/gpio.h -index 3abf304..bec0c98 100644 ---- a/arch/arm/plat-orion/include/plat/gpio.h -+++ b/arch/arm/plat-orion/include/plat/gpio.h +Index: linux-3.2.46/arch/arm/plat-orion/include/plat/gpio.h +=================================================================== +--- linux-3.2.46.orig/arch/arm/plat-orion/include/plat/gpio.h 2013-07-26 18:54:26.000000000 +0000 ++++ linux-3.2.46/arch/arm/plat-orion/include/plat/gpio.h 2013-07-26 19:23:55.000000000 +0000 @@ -19,6 +19,8 @@ */ void orion_gpio_set_unused(unsigned pin); diff -Nru linux-3.2.46/debian/patches/features/arm/kirkwood-fdt-absorb-kirkwood_init.patch linux-3.2.46/debian/patches/features/arm/kirkwood-fdt-absorb-kirkwood_init.patch --- linux-3.2.46/debian/patches/features/arm/kirkwood-fdt-absorb-kirkwood_init.patch 2013-04-11 03:27:32.000000000 +0000 +++ linux-3.2.46/debian/patches/features/arm/kirkwood-fdt-absorb-kirkwood_init.patch 2013-07-26 19:23:47.000000000 +0000 @@ -14,10 +14,10 @@ Signed-off-by: Jason Cooper -Index: sid/arch/arm/mach-kirkwood/board-dt.c +Index: linux-3.2.46/arch/arm/mach-kirkwood/board-dt.c =================================================================== ---- sid.orig/arch/arm/mach-kirkwood/board-dt.c 2012-06-10 20:02:17.000000000 +0200 -+++ sid/arch/arm/mach-kirkwood/board-dt.c 2012-06-10 20:02:22.677136456 +0200 +--- linux-3.2.46.orig/arch/arm/mach-kirkwood/board-dt.c 2013-07-26 19:23:43.000000000 +0000 ++++ linux-3.2.46/arch/arm/mach-kirkwood/board-dt.c 2013-07-26 19:23:46.000000000 +0000 @@ -29,7 +29,9 @@ #include #include @@ -28,7 +28,7 @@ #include #include "common.h" #include "mpp.h" -@@ -155,7 +157,32 @@ static void __init dreamplug_init(void) +@@ -155,7 +157,32 @@ static void __init kirkwood_dt_init(void) { @@ -62,11 +62,11 @@ if (of_machine_is_compatible("globalscale,dreamplug")) dreamplug_init(); -Index: sid/arch/arm/mach-kirkwood/common.c +Index: linux-3.2.46/arch/arm/mach-kirkwood/common.c =================================================================== ---- sid.orig/arch/arm/mach-kirkwood/common.c 2012-06-10 19:52:45.000000000 +0200 -+++ sid/arch/arm/mach-kirkwood/common.c 2012-06-10 20:02:22.677136456 +0200 -@@ -164,7 +164,7 @@ void __init kirkwood_nand_init_rnb(struc +--- linux-3.2.46.orig/arch/arm/mach-kirkwood/common.c 2013-07-26 19:17:39.000000000 +0000 ++++ linux-3.2.46/arch/arm/mach-kirkwood/common.c 2013-07-26 19:23:46.000000000 +0000 +@@ -164,7 +164,7 @@ /***************************************************************************** * SoC RTC ****************************************************************************/ @@ -75,7 +75,7 @@ { orion_rtc_init(RTC_PHYS_BASE, IRQ_KIRKWOOD_RTC); } -@@ -282,7 +282,7 @@ void __init kirkwood_crypto_init(void) +@@ -282,7 +282,7 @@ /***************************************************************************** * XOR0 ****************************************************************************/ @@ -84,7 +84,7 @@ { kirkwood_clk_ctrl |= CGC_XOR0; -@@ -295,7 +295,7 @@ static void __init kirkwood_xor0_init(vo +@@ -295,7 +295,7 @@ /***************************************************************************** * XOR1 ****************************************************************************/ @@ -93,7 +93,7 @@ { kirkwood_clk_ctrl |= CGC_XOR1; -@@ -307,7 +307,7 @@ static void __init kirkwood_xor1_init(vo +@@ -307,7 +307,7 @@ /***************************************************************************** * Watchdog ****************************************************************************/ @@ -102,7 +102,7 @@ { orion_wdt_init(kirkwood_tclk); } -@@ -397,7 +397,7 @@ void __init kirkwood_audio_init(void) +@@ -397,7 +397,7 @@ /* * Identify device ID and revision. */ @@ -111,7 +111,7 @@ { u32 dev, rev; -@@ -440,7 +440,7 @@ static char * __init kirkwood_id(void) +@@ -440,7 +440,7 @@ } } @@ -120,11 +120,11 @@ { #ifdef CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH writel(readl(L2_CONFIG_REG) | L2_WRITETHROUGH, L2_CONFIG_REG); -Index: sid/arch/arm/mach-kirkwood/common.h +Index: linux-3.2.46/arch/arm/mach-kirkwood/common.h =================================================================== ---- sid.orig/arch/arm/mach-kirkwood/common.h 2012-06-10 19:52:45.000000000 +0200 -+++ sid/arch/arm/mach-kirkwood/common.h 2012-06-10 20:02:22.677136456 +0200 -@@ -51,6 +51,14 @@ void kirkwood_nand_init(struct mtd_parti +--- linux-3.2.46.orig/arch/arm/mach-kirkwood/common.h 2013-07-26 18:54:30.000000000 +0000 ++++ linux-3.2.46/arch/arm/mach-kirkwood/common.h 2013-07-26 19:23:46.000000000 +0000 +@@ -51,6 +51,14 @@ void kirkwood_nand_init_rnb(struct mtd_partition *parts, int nr_parts, int (*dev_ready)(struct mtd_info *)); void kirkwood_audio_init(void); diff -Nru linux-3.2.46/debian/patches/features/arm/kirkwood-fdt-convert-uart0-to-devicetree.patch linux-3.2.46/debian/patches/features/arm/kirkwood-fdt-convert-uart0-to-devicetree.patch --- linux-3.2.46/debian/patches/features/arm/kirkwood-fdt-convert-uart0-to-devicetree.patch 2013-04-11 03:27:32.000000000 +0000 +++ linux-3.2.46/debian/patches/features/arm/kirkwood-fdt-convert-uart0-to-devicetree.patch 2013-07-26 19:23:44.000000000 +0000 @@ -12,10 +12,10 @@ Acked-by: Nicolas Pitre Signed-off-by: Arnd Bergmann -diff --git a/arch/arm/boot/dts/kirkwood-dreamplug.dts b/arch/arm/boot/dts/kirkwood-dreamplug.dts -index 0424d99..8a5dff8 100644 ---- a/arch/arm/boot/dts/kirkwood-dreamplug.dts -+++ b/arch/arm/boot/dts/kirkwood-dreamplug.dts +Index: linux-3.2.46/arch/arm/boot/dts/kirkwood-dreamplug.dts +=================================================================== +--- linux-3.2.46.orig/arch/arm/boot/dts/kirkwood-dreamplug.dts 2013-07-26 19:23:41.000000000 +0000 ++++ linux-3.2.46/arch/arm/boot/dts/kirkwood-dreamplug.dts 2013-07-26 19:23:43.000000000 +0000 @@ -15,4 +15,11 @@ bootargs = "console=ttyS0,115200n8 earlyprintk"; }; @@ -28,11 +28,11 @@ + clock-frequency = <200000000>; + }; }; -diff --git a/arch/arm/mach-kirkwood/board-dt.c b/arch/arm/mach-kirkwood/board-dt.c -index 76392af..fbe6405 100644 ---- a/arch/arm/mach-kirkwood/board-dt.c -+++ b/arch/arm/mach-kirkwood/board-dt.c -@@ -140,8 +140,6 @@ static void __init dreamplug_init(void) +Index: linux-3.2.46/arch/arm/mach-kirkwood/board-dt.c +=================================================================== +--- linux-3.2.46.orig/arch/arm/mach-kirkwood/board-dt.c 2013-07-26 19:23:41.000000000 +0000 ++++ linux-3.2.46/arch/arm/mach-kirkwood/board-dt.c 2013-07-26 19:23:43.000000000 +0000 +@@ -140,8 +140,6 @@ */ kirkwood_mpp_conf(dreamplug_mpp_config); diff -Nru linux-3.2.46/debian/patches/features/arm/kirkwood-fdt-define-uart01-as-disabled.patch linux-3.2.46/debian/patches/features/arm/kirkwood-fdt-define-uart01-as-disabled.patch --- linux-3.2.46/debian/patches/features/arm/kirkwood-fdt-define-uart01-as-disabled.patch 2013-04-11 03:27:32.000000000 +0000 +++ linux-3.2.46/debian/patches/features/arm/kirkwood-fdt-define-uart01-as-disabled.patch 2013-07-26 19:23:49.000000000 +0000 @@ -13,10 +13,10 @@ Signed-off-by: Jason Cooper -diff --git a/arch/arm/boot/dts/kirkwood-dreamplug.dts b/arch/arm/boot/dts/kirkwood-dreamplug.dts -index 333f11b..a5376b8 100644 ---- a/arch/arm/boot/dts/kirkwood-dreamplug.dts -+++ b/arch/arm/boot/dts/kirkwood-dreamplug.dts +Index: linux-3.2.46/arch/arm/boot/dts/kirkwood-dreamplug.dts +=================================================================== +--- linux-3.2.46.orig/arch/arm/boot/dts/kirkwood-dreamplug.dts 2013-07-26 19:23:44.000000000 +0000 ++++ linux-3.2.46/arch/arm/boot/dts/kirkwood-dreamplug.dts 2013-07-26 19:23:48.000000000 +0000 @@ -15,11 +15,10 @@ bootargs = "console=ttyS0,115200n8 earlyprintk"; }; @@ -34,10 +34,10 @@ + }; }; }; -diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi -index 702b955..825310b 100644 ---- a/arch/arm/boot/dts/kirkwood.dtsi -+++ b/arch/arm/boot/dts/kirkwood.dtsi +Index: linux-3.2.46/arch/arm/boot/dts/kirkwood.dtsi +=================================================================== +--- linux-3.2.46.orig/arch/arm/boot/dts/kirkwood.dtsi 2013-07-26 19:23:44.000000000 +0000 ++++ linux-3.2.46/arch/arm/boot/dts/kirkwood.dtsi 2013-07-26 19:23:48.000000000 +0000 @@ -2,5 +2,29 @@ / { diff -Nru linux-3.2.46/debian/patches/features/arm/kirkwood-fdt-facilitate-new-boards-during-fdt-migration.patch linux-3.2.46/debian/patches/features/arm/kirkwood-fdt-facilitate-new-boards-during-fdt-migration.patch --- linux-3.2.46/debian/patches/features/arm/kirkwood-fdt-facilitate-new-boards-during-fdt-migration.patch 2013-04-11 03:27:32.000000000 +0000 +++ linux-3.2.46/debian/patches/features/arm/kirkwood-fdt-facilitate-new-boards-during-fdt-migration.patch 2013-07-26 19:23:48.000000000 +0000 @@ -10,19 +10,19 @@ Signed-off-by: Jason Cooper -Index: sid/arch/arm/mach-kirkwood/Makefile +Index: linux-3.2.46/arch/arm/mach-kirkwood/Makefile =================================================================== ---- sid.orig/arch/arm/mach-kirkwood/Makefile 2012-06-10 20:02:17.000000000 +0200 -+++ sid/arch/arm/mach-kirkwood/Makefile 2012-06-10 20:02:33.717135970 +0200 -@@ -21,3 +21,4 @@ obj-$(CONFIG_MACH_T5325) += t5325-setup +--- linux-3.2.46.orig/arch/arm/mach-kirkwood/Makefile 2013-07-26 19:23:41.000000000 +0000 ++++ linux-3.2.46/arch/arm/mach-kirkwood/Makefile 2013-07-26 19:23:47.000000000 +0000 +@@ -21,3 +21,4 @@ obj-$(CONFIG_CPU_IDLE) += cpuidle.o obj-$(CONFIG_ARCH_KIRKWOOD_DT) += board-dt.o +obj-$(CONFIG_MACH_DREAMPLUG_DT) += board-dreamplug.o -Index: sid/arch/arm/mach-kirkwood/board-dreamplug.c +Index: linux-3.2.46/arch/arm/mach-kirkwood/board-dreamplug.c =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 -+++ sid/arch/arm/mach-kirkwood/board-dreamplug.c 2012-06-10 20:02:33.717135970 +0200 ++++ linux-3.2.46/arch/arm/mach-kirkwood/board-dreamplug.c 2013-07-26 19:23:47.000000000 +0000 @@ -0,0 +1,152 @@ +/* + * Copyright 2012 (C), Jason Cooper @@ -176,10 +176,10 @@ + + platform_device_register(&dreamplug_leds); +} -Index: sid/arch/arm/mach-kirkwood/board-dt.c +Index: linux-3.2.46/arch/arm/mach-kirkwood/board-dt.c =================================================================== ---- sid.orig/arch/arm/mach-kirkwood/board-dt.c 2012-06-10 20:02:22.000000000 +0200 -+++ sid/arch/arm/mach-kirkwood/board-dt.c 2012-06-10 20:02:33.721135970 +0200 +--- linux-3.2.46.orig/arch/arm/mach-kirkwood/board-dt.c 2013-07-26 19:23:46.000000000 +0000 ++++ linux-3.2.46/arch/arm/mach-kirkwood/board-dt.c 2013-07-26 19:23:47.000000000 +0000 @@ -3,7 +3,7 @@ * * arch/arm/mach-kirkwood/board-dt.c @@ -339,11 +339,11 @@ static void __init kirkwood_dt_init(void) { pr_info("Kirkwood: %s, TCLK=%d.\n", kirkwood_id(), kirkwood_tclk); -Index: sid/arch/arm/mach-kirkwood/common.h +Index: linux-3.2.46/arch/arm/mach-kirkwood/common.h =================================================================== ---- sid.orig/arch/arm/mach-kirkwood/common.h 2012-06-10 20:02:22.000000000 +0200 -+++ sid/arch/arm/mach-kirkwood/common.h 2012-06-10 20:02:33.721135970 +0200 -@@ -51,6 +51,14 @@ void kirkwood_nand_init(struct mtd_parti +--- linux-3.2.46.orig/arch/arm/mach-kirkwood/common.h 2013-07-26 19:23:46.000000000 +0000 ++++ linux-3.2.46/arch/arm/mach-kirkwood/common.h 2013-07-26 19:23:47.000000000 +0000 +@@ -51,6 +51,14 @@ void kirkwood_nand_init_rnb(struct mtd_partition *parts, int nr_parts, int (*dev_ready)(struct mtd_info *)); void kirkwood_audio_init(void); diff -Nru linux-3.2.46/debian/patches/features/arm/kirkwood-fdt-use-mrvl-ticker-symbol.patch linux-3.2.46/debian/patches/features/arm/kirkwood-fdt-use-mrvl-ticker-symbol.patch --- linux-3.2.46/debian/patches/features/arm/kirkwood-fdt-use-mrvl-ticker-symbol.patch 2013-04-11 03:27:32.000000000 +0000 +++ linux-3.2.46/debian/patches/features/arm/kirkwood-fdt-use-mrvl-ticker-symbol.patch 2013-07-26 19:23:45.000000000 +0000 @@ -8,10 +8,10 @@ Signed-off-by: Jason Cooper -diff --git a/arch/arm/boot/dts/kirkwood-dreamplug.dts b/arch/arm/boot/dts/kirkwood-dreamplug.dts -index 8a5dff8..333f11b 100644 ---- a/arch/arm/boot/dts/kirkwood-dreamplug.dts -+++ b/arch/arm/boot/dts/kirkwood-dreamplug.dts +Index: linux-3.2.46/arch/arm/boot/dts/kirkwood-dreamplug.dts +=================================================================== +--- linux-3.2.46.orig/arch/arm/boot/dts/kirkwood-dreamplug.dts 2013-07-26 19:23:43.000000000 +0000 ++++ linux-3.2.46/arch/arm/boot/dts/kirkwood-dreamplug.dts 2013-07-26 19:23:44.000000000 +0000 @@ -4,7 +4,7 @@ / { @@ -30,10 +30,10 @@ reg-shift = <2>; interrupts = <33>; clock-frequency = <200000000>; -diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi -index 771c6bb..702b955 100644 ---- a/arch/arm/boot/dts/kirkwood.dtsi -+++ b/arch/arm/boot/dts/kirkwood.dtsi +Index: linux-3.2.46/arch/arm/boot/dts/kirkwood.dtsi +=================================================================== +--- linux-3.2.46.orig/arch/arm/boot/dts/kirkwood.dtsi 2013-07-26 19:23:41.000000000 +0000 ++++ linux-3.2.46/arch/arm/boot/dts/kirkwood.dtsi 2013-07-26 19:23:44.000000000 +0000 @@ -1,6 +1,6 @@ /include/ "skeleton.dtsi" diff -Nru linux-3.2.46/debian/patches/features/arm/kirkwood-fix-orion_gpio_set_blink.patch linux-3.2.46/debian/patches/features/arm/kirkwood-fix-orion_gpio_set_blink.patch --- linux-3.2.46/debian/patches/features/arm/kirkwood-fix-orion_gpio_set_blink.patch 2013-04-11 03:27:32.000000000 +0000 +++ linux-3.2.46/debian/patches/features/arm/kirkwood-fix-orion_gpio_set_blink.patch 2013-07-26 19:23:55.000000000 +0000 @@ -12,11 +12,11 @@ Tested-By: Adam Baker Signed-off-by: Jason Cooper -diff --git a/arch/arm/plat-orion/gpio.c b/arch/arm/plat-orion/gpio.c -index 10d1608..d3401e7 100644 ---- a/arch/arm/plat-orion/gpio.c -+++ b/arch/arm/plat-orion/gpio.c -@@ -289,8 +289,8 @@ void orion_gpio_set_blink(unsigned pin, int blink) +Index: linux-3.2.46/arch/arm/plat-orion/gpio.c +=================================================================== +--- linux-3.2.46.orig/arch/arm/plat-orion/gpio.c 2013-07-26 18:54:27.000000000 +0000 ++++ linux-3.2.46/arch/arm/plat-orion/gpio.c 2013-07-26 19:23:54.000000000 +0000 +@@ -289,8 +289,8 @@ return; spin_lock_irqsave(&ochip->lock, flags); diff -Nru linux-3.2.46/debian/patches/features/arm/kirkwood-rtc-mv-devicetree-bindings.patch linux-3.2.46/debian/patches/features/arm/kirkwood-rtc-mv-devicetree-bindings.patch --- linux-3.2.46/debian/patches/features/arm/kirkwood-rtc-mv-devicetree-bindings.patch 2013-04-11 03:27:32.000000000 +0000 +++ linux-3.2.46/debian/patches/features/arm/kirkwood-rtc-mv-devicetree-bindings.patch 2013-07-26 19:23:51.000000000 +0000 @@ -8,10 +8,10 @@ Signed-off-by: Jason Cooper -diff --git a/drivers/rtc/rtc-mv.c b/drivers/rtc/rtc-mv.c -index 768e2ed..0dd8421 100644 ---- a/drivers/rtc/rtc-mv.c -+++ b/drivers/rtc/rtc-mv.c +Index: linux-3.2.46/drivers/rtc/rtc-mv.c +=================================================================== +--- linux-3.2.46.orig/drivers/rtc/rtc-mv.c 2013-07-26 18:54:28.000000000 +0000 ++++ linux-3.2.46/drivers/rtc/rtc-mv.c 2013-07-26 19:23:50.000000000 +0000 @@ -12,6 +12,7 @@ #include #include @@ -20,7 +20,7 @@ #include #include #include -@@ -294,11 +295,19 @@ static int __exit mv_rtc_remove(struct platform_device *pdev) +@@ -294,11 +295,19 @@ return 0; } diff -Nru linux-3.2.46/debian/patches/features/arm/kirkwood-use-devicetree-for-rtc-mv.patch linux-3.2.46/debian/patches/features/arm/kirkwood-use-devicetree-for-rtc-mv.patch --- linux-3.2.46/debian/patches/features/arm/kirkwood-use-devicetree-for-rtc-mv.patch 2013-04-11 03:27:32.000000000 +0000 +++ linux-3.2.46/debian/patches/features/arm/kirkwood-use-devicetree-for-rtc-mv.patch 2013-07-26 19:23:52.000000000 +0000 @@ -7,10 +7,10 @@ Signed-off-by: Jason Cooper Acked-by: Arnd Bergmann -diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi -index 825310b..3474ef8 100644 ---- a/arch/arm/boot/dts/kirkwood.dtsi -+++ b/arch/arm/boot/dts/kirkwood.dtsi +Index: linux-3.2.46/arch/arm/boot/dts/kirkwood.dtsi +=================================================================== +--- linux-3.2.46.orig/arch/arm/boot/dts/kirkwood.dtsi 2013-07-26 19:23:48.000000000 +0000 ++++ linux-3.2.46/arch/arm/boot/dts/kirkwood.dtsi 2013-07-26 19:23:51.000000000 +0000 @@ -26,5 +26,11 @@ /* set clock-frequency in board dts */ status = "disabled"; @@ -23,11 +23,11 @@ + }; }; }; -diff --git a/arch/arm/mach-kirkwood/board-dt.c b/arch/arm/mach-kirkwood/board-dt.c -index 975ad01..1c672d9 100644 ---- a/arch/arm/mach-kirkwood/board-dt.c -+++ b/arch/arm/mach-kirkwood/board-dt.c -@@ -43,7 +43,6 @@ static void __init kirkwood_dt_init(void) +Index: linux-3.2.46/arch/arm/mach-kirkwood/board-dt.c +=================================================================== +--- linux-3.2.46.orig/arch/arm/mach-kirkwood/board-dt.c 2013-07-26 19:23:47.000000000 +0000 ++++ linux-3.2.46/arch/arm/mach-kirkwood/board-dt.c 2013-07-26 19:23:51.000000000 +0000 +@@ -43,7 +43,6 @@ #endif /* internal devices that every board has */ @@ -35,11 +35,11 @@ kirkwood_wdt_init(); kirkwood_xor0_init(); kirkwood_xor1_init(); -diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c -index 04a7eb9..a02cae8 100644 ---- a/arch/arm/mach-kirkwood/common.c -+++ b/arch/arm/mach-kirkwood/common.c -@@ -163,7 +163,7 @@ void __init kirkwood_nand_init_rnb(struct mtd_partition *parts, int nr_parts, +Index: linux-3.2.46/arch/arm/mach-kirkwood/common.c +=================================================================== +--- linux-3.2.46.orig/arch/arm/mach-kirkwood/common.c 2013-07-26 19:23:46.000000000 +0000 ++++ linux-3.2.46/arch/arm/mach-kirkwood/common.c 2013-07-26 19:23:51.000000000 +0000 +@@ -164,7 +164,7 @@ /***************************************************************************** * SoC RTC ****************************************************************************/ @@ -48,11 +48,11 @@ { orion_rtc_init(RTC_PHYS_BASE, IRQ_KIRKWOOD_RTC); } -diff --git a/arch/arm/mach-kirkwood/common.h b/arch/arm/mach-kirkwood/common.h -index 4737578..fa8e768 100644 ---- a/arch/arm/mach-kirkwood/common.h -+++ b/arch/arm/mach-kirkwood/common.h -@@ -61,7 +61,6 @@ static inline void dreamplug_init(void) {}; +Index: linux-3.2.46/arch/arm/mach-kirkwood/common.h +=================================================================== +--- linux-3.2.46.orig/arch/arm/mach-kirkwood/common.h 2013-07-26 19:23:47.000000000 +0000 ++++ linux-3.2.46/arch/arm/mach-kirkwood/common.h 2013-07-26 19:23:51.000000000 +0000 +@@ -61,7 +61,6 @@ /* early init functions not converted to fdt yet */ char *kirkwood_id(void); void kirkwood_l2_init(void); diff -Nru linux-3.2.46/debian/patches/features/arm/net-drop-NET-dependency-from-HAVE_BPF_JIT.patch linux-3.2.46/debian/patches/features/arm/net-drop-NET-dependency-from-HAVE_BPF_JIT.patch --- linux-3.2.46/debian/patches/features/arm/net-drop-NET-dependency-from-HAVE_BPF_JIT.patch 2013-04-11 03:27:32.000000000 +0000 +++ linux-3.2.46/debian/patches/features/arm/net-drop-NET-dependency-from-HAVE_BPF_JIT.patch 2013-07-26 19:24:05.000000000 +0000 @@ -24,10 +24,10 @@ net/Kconfig | 7 ++++--- 5 files changed, 8 insertions(+), 7 deletions(-) -Index: linux/arch/arm/Kconfig +Index: linux-3.2.46/arch/arm/Kconfig =================================================================== ---- linux.orig/arch/arm/Kconfig 2012-06-24 23:41:24.000000000 +0200 -+++ linux/arch/arm/Kconfig 2012-06-24 23:49:03.000000000 +0200 +--- linux-3.2.46.orig/arch/arm/Kconfig 2013-07-26 19:24:03.000000000 +0000 ++++ linux-3.2.46/arch/arm/Kconfig 2013-07-26 19:24:04.000000000 +0000 @@ -30,7 +30,7 @@ select HAVE_SPARSE_IRQ select GENERIC_IRQ_SHOW @@ -37,10 +37,10 @@ help The ARM series is a line of low-power-consumption RISC chip designs licensed by ARM Ltd and targeted at embedded applications and -Index: linux/arch/powerpc/Kconfig +Index: linux-3.2.46/arch/powerpc/Kconfig =================================================================== ---- linux.orig/arch/powerpc/Kconfig 2012-06-20 00:18:30.000000000 +0200 -+++ linux/arch/powerpc/Kconfig 2012-06-24 23:49:03.000000000 +0200 +--- linux-3.2.46.orig/arch/powerpc/Kconfig 2013-07-26 18:54:23.000000000 +0000 ++++ linux-3.2.46/arch/powerpc/Kconfig 2013-07-26 19:24:04.000000000 +0000 @@ -134,7 +134,7 @@ select GENERIC_IRQ_SHOW_LEVEL select HAVE_RCU_TABLE_FREE if SMP @@ -50,10 +50,10 @@ select HAVE_ARCH_JUMP_LABEL select ARCH_HAVE_NMI_SAFE_CMPXCHG -Index: linux/arch/x86/Kconfig +Index: linux-3.2.46/arch/x86/Kconfig =================================================================== ---- linux.orig/arch/x86/Kconfig 2012-06-23 17:09:51.000000000 +0200 -+++ linux/arch/x86/Kconfig 2012-06-24 23:49:03.000000000 +0200 +--- linux-3.2.46.orig/arch/x86/Kconfig 2013-07-26 19:23:10.000000000 +0000 ++++ linux-3.2.46/arch/x86/Kconfig 2013-07-26 19:24:04.000000000 +0000 @@ -72,7 +72,7 @@ select GENERIC_CLOCKEVENTS_MIN_ADJUST select IRQ_FORCED_THREADING @@ -63,10 +63,10 @@ select CLKEVT_I8253 select ARCH_HAVE_NMI_SAFE_CMPXCHG -Index: linux/net/Kconfig +Index: linux-3.2.46/net/Kconfig =================================================================== ---- linux.orig/net/Kconfig 2012-06-20 00:18:30.000000000 +0200 -+++ linux/net/Kconfig 2012-06-24 23:49:03.000000000 +0200 +--- linux-3.2.46.orig/net/Kconfig 2013-07-26 18:54:23.000000000 +0000 ++++ linux-3.2.46/net/Kconfig 2013-07-26 19:24:04.000000000 +0000 @@ -232,9 +232,6 @@ depends on SMP && SYSFS && USE_GENERIC_SMP_HELPERS default y diff -Nru linux-3.2.46/debian/patches/features/arm/rtc-s35390a-wakealarm.patch linux-3.2.46/debian/patches/features/arm/rtc-s35390a-wakealarm.patch --- linux-3.2.46/debian/patches/features/arm/rtc-s35390a-wakealarm.patch 2013-02-24 03:52:25.000000000 +0000 +++ linux-3.2.46/debian/patches/features/arm/rtc-s35390a-wakealarm.patch 2013-07-26 19:26:16.000000000 +0000 @@ -15,10 +15,10 @@ drivers/rtc/rtc-s35390a.c | 116 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 116 insertions(+) -diff --git a/drivers/rtc/rtc-s35390a.c b/drivers/rtc/rtc-s35390a.c -index cc5c516..8a09232 100644 ---- a/drivers/rtc/rtc-s35390a.c -+++ b/drivers/rtc/rtc-s35390a.c +Index: linux-3.2.46/drivers/rtc/rtc-s35390a.c +=================================================================== +--- linux-3.2.46.orig/drivers/rtc/rtc-s35390a.c 2013-07-26 18:53:36.000000000 +0000 ++++ linux-3.2.46/drivers/rtc/rtc-s35390a.c 2013-07-26 19:26:15.000000000 +0000 @@ -19,6 +19,8 @@ #define S35390A_CMD_STATUS1 0 #define S35390A_CMD_STATUS2 1 @@ -52,7 +52,7 @@ static const struct i2c_device_id s35390a_id[] = { { "s35390a", 0 }, { } -@@ -193,6 +206,104 @@ static int s35390a_get_datetime(struct i2c_client *client, struct rtc_time *tm) +@@ -184,6 +197,104 @@ return rtc_valid_tm(tm); } @@ -157,7 +157,7 @@ static int s35390a_rtc_read_time(struct device *dev, struct rtc_time *tm) { return s35390a_get_datetime(to_i2c_client(dev), tm); -@@ -206,6 +317,9 @@ static int s35390a_rtc_set_time(struct device *dev, struct rtc_time *tm) +@@ -197,6 +308,9 @@ static const struct rtc_class_ops s35390a_rtc_ops = { .read_time = s35390a_rtc_read_time, .set_time = s35390a_rtc_set_time, @@ -167,7 +167,7 @@ }; static struct i2c_driver s35390a_driver; -@@ -270,6 +384,8 @@ static int s35390a_probe(struct i2c_client *client, +@@ -261,6 +375,8 @@ if (s35390a_get_datetime(client, &tm) < 0) dev_warn(&client->dev, "clock needs to be set\n"); diff -Nru linux-3.2.46/debian/patches/features/x86/efi-stub/0001-x86-Add-missing-bzImage-fields-to-struct-setup_heade.patch linux-3.2.46/debian/patches/features/x86/efi-stub/0001-x86-Add-missing-bzImage-fields-to-struct-setup_heade.patch --- linux-3.2.46/debian/patches/features/x86/efi-stub/0001-x86-Add-missing-bzImage-fields-to-struct-setup_heade.patch 2013-02-24 03:52:26.000000000 +0000 +++ linux-3.2.46/debian/patches/features/x86/efi-stub/0001-x86-Add-missing-bzImage-fields-to-struct-setup_heade.patch 2013-07-26 19:19:42.000000000 +0000 @@ -16,11 +16,11 @@ arch/x86/include/asm/bootparam.h | 2 ++ 1 file changed, 2 insertions(+) -diff --git a/arch/x86/include/asm/bootparam.h b/arch/x86/include/asm/bootparam.h -index e020d88..2f90c51 100644 ---- a/arch/x86/include/asm/bootparam.h -+++ b/arch/x86/include/asm/bootparam.h -@@ -64,6 +64,8 @@ struct setup_header { +Index: linux-3.2.46/arch/x86/include/asm/bootparam.h +=================================================================== +--- linux-3.2.46.orig/arch/x86/include/asm/bootparam.h 2013-07-26 18:55:48.000000000 +0000 ++++ linux-3.2.46/arch/x86/include/asm/bootparam.h 2013-07-26 19:19:42.000000000 +0000 +@@ -64,6 +64,8 @@ __u32 payload_offset; __u32 payload_length; __u64 setup_data; @@ -29,6 +29,3 @@ } __attribute__((packed)); struct sys_desc_table { --- -1.7.10 - diff -Nru linux-3.2.46/debian/patches/features/x86/efi-stub/0002-x86-Don-t-use-magic-strings-for-EFI-loader-signature.patch linux-3.2.46/debian/patches/features/x86/efi-stub/0002-x86-Don-t-use-magic-strings-for-EFI-loader-signature.patch --- linux-3.2.46/debian/patches/features/x86/efi-stub/0002-x86-Don-t-use-magic-strings-for-EFI-loader-signature.patch 2013-02-24 03:52:26.000000000 +0000 +++ linux-3.2.46/debian/patches/features/x86/efi-stub/0002-x86-Don-t-use-magic-strings-for-EFI-loader-signature.patch 2013-07-26 19:19:44.000000000 +0000 @@ -18,8 +18,10 @@ arch/x86/kernel/setup.c | 7 +------ 2 files changed, 5 insertions(+), 6 deletions(-) ---- a/arch/x86/include/asm/efi.h -+++ b/arch/x86/include/asm/efi.h +Index: linux-3.2.46/arch/x86/include/asm/efi.h +=================================================================== +--- linux-3.2.46.orig/arch/x86/include/asm/efi.h 2013-07-26 18:55:48.000000000 +0000 ++++ linux-3.2.46/arch/x86/include/asm/efi.h 2013-07-26 19:19:43.000000000 +0000 @@ -3,6 +3,8 @@ #ifdef CONFIG_X86_32 @@ -29,7 +31,7 @@ extern unsigned long asmlinkage efi_call_phys(void *, ...); #define efi_call_phys0(f) efi_call_phys(f) -@@ -37,6 +39,8 @@ extern unsigned long asmlinkage efi_call +@@ -37,6 +39,8 @@ #else /* !CONFIG_X86_32 */ diff -Nru linux-3.2.46/debian/patches/features/x86/efi-stub/0003-efi.h-Add-struct-definition-for-boot-time-services.patch linux-3.2.46/debian/patches/features/x86/efi-stub/0003-efi.h-Add-struct-definition-for-boot-time-services.patch --- linux-3.2.46/debian/patches/features/x86/efi-stub/0003-efi.h-Add-struct-definition-for-boot-time-services.patch 2013-02-24 03:52:26.000000000 +0000 +++ linux-3.2.46/debian/patches/features/x86/efi-stub/0003-efi.h-Add-struct-definition-for-boot-time-services.patch 2013-07-26 19:19:45.000000000 +0000 @@ -15,11 +15,11 @@ include/linux/efi.h | 53 ++++++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 52 insertions(+), 1 deletion(-) -diff --git a/include/linux/efi.h b/include/linux/efi.h -index 2362a0b..9547597 100644 ---- a/include/linux/efi.h -+++ b/include/linux/efi.h -@@ -139,6 +139,57 @@ typedef struct { +Index: linux-3.2.46/include/linux/efi.h +=================================================================== +--- linux-3.2.46.orig/include/linux/efi.h 2013-07-26 18:55:47.000000000 +0000 ++++ linux-3.2.46/include/linux/efi.h 2013-07-26 19:19:44.000000000 +0000 +@@ -144,6 +144,57 @@ } efi_time_cap_t; /* @@ -77,7 +77,7 @@ * Types and defines for EFI ResetSystem */ #define EFI_RESET_COLD 0 -@@ -261,7 +312,7 @@ typedef struct { +@@ -267,7 +318,7 @@ unsigned long stderr_handle; unsigned long stderr; efi_runtime_services_t *runtime; @@ -86,6 +86,3 @@ unsigned long nr_tables; unsigned long tables; } efi_system_table_t; --- -1.7.10 - diff -Nru linux-3.2.46/debian/patches/features/x86/efi-stub/0004-efi.h-Add-efi_image_loaded_t.patch linux-3.2.46/debian/patches/features/x86/efi-stub/0004-efi.h-Add-efi_image_loaded_t.patch --- linux-3.2.46/debian/patches/features/x86/efi-stub/0004-efi.h-Add-efi_image_loaded_t.patch 2013-02-24 03:52:26.000000000 +0000 +++ linux-3.2.46/debian/patches/features/x86/efi-stub/0004-efi.h-Add-efi_image_loaded_t.patch 2013-07-26 19:19:46.000000000 +0000 @@ -17,11 +17,11 @@ include/linux/efi.h | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) -diff --git a/include/linux/efi.h b/include/linux/efi.h -index 9547597..e35005f 100644 ---- a/include/linux/efi.h -+++ b/include/linux/efi.h -@@ -287,6 +287,9 @@ typedef efi_status_t efi_query_capsule_caps_t(efi_capsule_header_t **capsules, +Index: linux-3.2.46/include/linux/efi.h +=================================================================== +--- linux-3.2.46.orig/include/linux/efi.h 2013-07-26 19:19:44.000000000 +0000 ++++ linux-3.2.46/include/linux/efi.h 2013-07-26 19:19:45.000000000 +0000 +@@ -293,6 +293,9 @@ #define LINUX_EFI_CRASH_GUID \ EFI_GUID( 0xcfc8fc79, 0xbe2e, 0x4ddc, 0x97, 0xf0, 0x9f, 0x98, 0xbf, 0xe2, 0x98, 0xa0 ) @@ -31,7 +31,7 @@ typedef struct { efi_guid_t guid; unsigned long table; -@@ -326,6 +329,22 @@ struct efi_memory_map { +@@ -332,6 +335,22 @@ unsigned long desc_size; }; @@ -54,6 +54,3 @@ #define EFI_INVALID_TABLE_ADDR (~0UL) /* --- -1.7.10 - diff -Nru linux-3.2.46/debian/patches/features/x86/efi-stub/0005-efi.h-Add-allocation-types-for-boottime-allocate_pag.patch linux-3.2.46/debian/patches/features/x86/efi-stub/0005-efi.h-Add-allocation-types-for-boottime-allocate_pag.patch --- linux-3.2.46/debian/patches/features/x86/efi-stub/0005-efi.h-Add-allocation-types-for-boottime-allocate_pag.patch 2013-02-24 03:52:26.000000000 +0000 +++ linux-3.2.46/debian/patches/features/x86/efi-stub/0005-efi.h-Add-allocation-types-for-boottime-allocate_pag.patch 2013-07-26 19:19:48.000000000 +0000 @@ -17,11 +17,11 @@ include/linux/efi.h | 8 ++++++++ 1 file changed, 8 insertions(+) -diff --git a/include/linux/efi.h b/include/linux/efi.h -index e35005f..378f2cd 100644 ---- a/include/linux/efi.h -+++ b/include/linux/efi.h -@@ -109,6 +109,14 @@ typedef struct { +Index: linux-3.2.46/include/linux/efi.h +=================================================================== +--- linux-3.2.46.orig/include/linux/efi.h 2013-07-26 19:19:45.000000000 +0000 ++++ linux-3.2.46/include/linux/efi.h 2013-07-26 19:19:47.000000000 +0000 +@@ -114,6 +114,14 @@ u32 imagesize; } efi_capsule_header_t; @@ -36,6 +36,3 @@ typedef int (*efi_freemem_callback_t) (u64 start, u64 end, void *arg); /* --- -1.7.10 - diff -Nru linux-3.2.46/debian/patches/features/x86/efi-stub/0006-efi.h-Add-graphics-protocol-guids.patch linux-3.2.46/debian/patches/features/x86/efi-stub/0006-efi.h-Add-graphics-protocol-guids.patch --- linux-3.2.46/debian/patches/features/x86/efi-stub/0006-efi.h-Add-graphics-protocol-guids.patch 2013-02-24 03:52:26.000000000 +0000 +++ linux-3.2.46/debian/patches/features/x86/efi-stub/0006-efi.h-Add-graphics-protocol-guids.patch 2013-07-26 19:19:49.000000000 +0000 @@ -16,11 +16,11 @@ include/linux/efi.h | 9 +++++++++ 1 file changed, 9 insertions(+) -diff --git a/include/linux/efi.h b/include/linux/efi.h -index 378f2cd..e46d771 100644 ---- a/include/linux/efi.h -+++ b/include/linux/efi.h -@@ -298,6 +298,15 @@ typedef efi_status_t efi_query_capsule_caps_t(efi_capsule_header_t **capsules, +Index: linux-3.2.46/include/linux/efi.h +=================================================================== +--- linux-3.2.46.orig/include/linux/efi.h 2013-07-26 19:19:47.000000000 +0000 ++++ linux-3.2.46/include/linux/efi.h 2013-07-26 19:19:48.000000000 +0000 +@@ -304,6 +304,15 @@ #define LOADED_IMAGE_PROTOCOL_GUID \ EFI_GUID( 0x5b1b31a1, 0x9562, 0x11d2, 0x8e, 0x3f, 0x00, 0xa0, 0xc9, 0x69, 0x72, 0x3b ) @@ -36,6 +36,3 @@ typedef struct { efi_guid_t guid; unsigned long table; --- -1.7.10 - diff -Nru linux-3.2.46/debian/patches/features/x86/efi-stub/0007-efi.h-Add-boottime-locate_handle-search-types.patch linux-3.2.46/debian/patches/features/x86/efi-stub/0007-efi.h-Add-boottime-locate_handle-search-types.patch --- linux-3.2.46/debian/patches/features/x86/efi-stub/0007-efi.h-Add-boottime-locate_handle-search-types.patch 2013-02-24 03:52:26.000000000 +0000 +++ linux-3.2.46/debian/patches/features/x86/efi-stub/0007-efi.h-Add-boottime-locate_handle-search-types.patch 2013-07-26 19:19:50.000000000 +0000 @@ -17,9 +17,11 @@ include/linux/efi.h | 7 +++++++ 1 file changed, 7 insertions(+) ---- a/include/linux/efi.h -+++ b/include/linux/efi.h -@@ -472,6 +472,13 @@ extern int __init efi_setup_pcdp_console(char *); +Index: linux-3.2.46/include/linux/efi.h +=================================================================== +--- linux-3.2.46.orig/include/linux/efi.h 2013-07-26 19:19:48.000000000 +0000 ++++ linux-3.2.46/include/linux/efi.h 2013-07-26 19:19:49.000000000 +0000 +@@ -510,6 +510,13 @@ EFI_VARIABLE_TIME_BASED_AUTHENTICATED_WRITE_ACCESS | \ EFI_VARIABLE_APPEND_WRITE) /* diff -Nru linux-3.2.46/debian/patches/features/x86/efi-stub/0008-efi-Add-EFI-file-I-O-data-types.patch linux-3.2.46/debian/patches/features/x86/efi-stub/0008-efi-Add-EFI-file-I-O-data-types.patch --- linux-3.2.46/debian/patches/features/x86/efi-stub/0008-efi-Add-EFI-file-I-O-data-types.patch 2013-02-24 03:52:26.000000000 +0000 +++ linux-3.2.46/debian/patches/features/x86/efi-stub/0008-efi-Add-EFI-file-I-O-data-types.patch 2013-07-26 19:19:51.000000000 +0000 @@ -15,11 +15,11 @@ include/linux/efi.h | 40 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) -diff --git a/include/linux/efi.h b/include/linux/efi.h -index d407c88..37c3007 100644 ---- a/include/linux/efi.h -+++ b/include/linux/efi.h -@@ -307,6 +307,12 @@ typedef efi_status_t efi_query_capsule_caps_t(efi_capsule_header_t **capsules, +Index: linux-3.2.46/include/linux/efi.h +=================================================================== +--- linux-3.2.46.orig/include/linux/efi.h 2013-07-26 19:19:49.000000000 +0000 ++++ linux-3.2.46/include/linux/efi.h 2013-07-26 19:19:51.000000000 +0000 +@@ -313,6 +313,12 @@ #define EFI_PCI_IO_PROTOCOL_GUID \ EFI_GUID( 0x4cf5b200, 0x68b8, 0x4ca5, 0x9e, 0xec, 0xb2, 0x3e, 0x3f, 0x50, 0x2, 0x9a ) @@ -32,7 +32,7 @@ typedef struct { efi_guid_t guid; unsigned long table; -@@ -362,6 +368,40 @@ typedef struct { +@@ -368,6 +374,40 @@ unsigned long unload; } efi_loaded_image_t; @@ -73,6 +73,3 @@ #define EFI_INVALID_TABLE_ADDR (~0UL) /* --- -1.7.10 - diff -Nru linux-3.2.46/debian/patches/features/x86/efi-stub/0009-x86-efi-EFI-boot-stub-support.patch linux-3.2.46/debian/patches/features/x86/efi-stub/0009-x86-efi-EFI-boot-stub-support.patch --- linux-3.2.46/debian/patches/features/x86/efi-stub/0009-x86-efi-EFI-boot-stub-support.patch 2013-02-24 03:52:26.000000000 +0000 +++ linux-3.2.46/debian/patches/features/x86/efi-stub/0009-x86-efi-EFI-boot-stub-support.patch 2013-07-26 19:19:54.000000000 +0000 @@ -113,11 +113,11 @@ create mode 100644 arch/x86/boot/compressed/efi_stub_32.S create mode 100644 arch/x86/boot/compressed/efi_stub_64.S -diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig -index efb4294..d71b656 100644 ---- a/arch/x86/Kconfig -+++ b/arch/x86/Kconfig -@@ -1478,6 +1478,13 @@ config EFI +Index: linux-3.2.46/arch/x86/Kconfig +=================================================================== +--- linux-3.2.46.orig/arch/x86/Kconfig 2013-07-26 18:55:45.000000000 +0000 ++++ linux-3.2.46/arch/x86/Kconfig 2013-07-26 19:19:52.000000000 +0000 +@@ -1478,6 +1478,13 @@ resultant kernel should continue to boot on existing non-EFI platforms. @@ -131,11 +131,11 @@ config SECCOMP def_bool y prompt "Enable seccomp to safely compute untrusted bytecode" -diff --git a/arch/x86/boot/compressed/Makefile b/arch/x86/boot/compressed/Makefile -index 09664ef..b123b9a 100644 ---- a/arch/x86/boot/compressed/Makefile -+++ b/arch/x86/boot/compressed/Makefile -@@ -23,7 +23,15 @@ LDFLAGS_vmlinux := -T +Index: linux-3.2.46/arch/x86/boot/compressed/Makefile +=================================================================== +--- linux-3.2.46.orig/arch/x86/boot/compressed/Makefile 2013-07-26 18:55:45.000000000 +0000 ++++ linux-3.2.46/arch/x86/boot/compressed/Makefile 2013-07-26 19:19:52.000000000 +0000 +@@ -23,7 +23,15 @@ hostprogs-y := mkpiggy @@ -152,11 +152,10 @@ $(call if_changed,ld) @: -diff --git a/arch/x86/boot/compressed/eboot.c b/arch/x86/boot/compressed/eboot.c -new file mode 100644 -index 0000000..4055e63 ---- /dev/null -+++ b/arch/x86/boot/compressed/eboot.c +Index: linux-3.2.46/arch/x86/boot/compressed/eboot.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/arch/x86/boot/compressed/eboot.c 2013-07-26 19:19:52.000000000 +0000 @@ -0,0 +1,1014 @@ +/* ----------------------------------------------------------------------- + * @@ -1172,11 +1171,10 @@ +fail: + return NULL; +} -diff --git a/arch/x86/boot/compressed/eboot.h b/arch/x86/boot/compressed/eboot.h -new file mode 100644 -index 0000000..f66d023 ---- /dev/null -+++ b/arch/x86/boot/compressed/eboot.h +Index: linux-3.2.46/arch/x86/boot/compressed/eboot.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/arch/x86/boot/compressed/eboot.h 2013-07-26 19:19:52.000000000 +0000 @@ -0,0 +1,60 @@ +#ifndef BOOT_COMPRESSED_EBOOT_H +#define BOOT_COMPRESSED_EBOOT_H @@ -1238,11 +1236,10 @@ +}; + +#endif /* BOOT_COMPRESSED_EBOOT_H */ -diff --git a/arch/x86/boot/compressed/efi_stub_32.S b/arch/x86/boot/compressed/efi_stub_32.S -new file mode 100644 -index 0000000..a53440e ---- /dev/null -+++ b/arch/x86/boot/compressed/efi_stub_32.S +Index: linux-3.2.46/arch/x86/boot/compressed/efi_stub_32.S +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/arch/x86/boot/compressed/efi_stub_32.S 2013-07-26 19:19:52.000000000 +0000 @@ -0,0 +1,86 @@ +/* + * EFI call stub for IA32. @@ -1330,17 +1327,16 @@ + .long 0 +efi_rt_function_ptr: + .long 0 -diff --git a/arch/x86/boot/compressed/efi_stub_64.S b/arch/x86/boot/compressed/efi_stub_64.S -new file mode 100644 -index 0000000..cedc60d ---- /dev/null -+++ b/arch/x86/boot/compressed/efi_stub_64.S +Index: linux-3.2.46/arch/x86/boot/compressed/efi_stub_64.S +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/arch/x86/boot/compressed/efi_stub_64.S 2013-07-26 19:19:52.000000000 +0000 @@ -0,0 +1 @@ +#include "../../platform/efi/efi_stub_64.S" -diff --git a/arch/x86/boot/compressed/head_32.S b/arch/x86/boot/compressed/head_32.S -index 67a655a..a055993 100644 ---- a/arch/x86/boot/compressed/head_32.S -+++ b/arch/x86/boot/compressed/head_32.S +Index: linux-3.2.46/arch/x86/boot/compressed/head_32.S +=================================================================== +--- linux-3.2.46.orig/arch/x86/boot/compressed/head_32.S 2013-07-26 18:55:45.000000000 +0000 ++++ linux-3.2.46/arch/x86/boot/compressed/head_32.S 2013-07-26 19:19:52.000000000 +0000 @@ -32,6 +32,28 @@ __HEAD @@ -1370,11 +1366,11 @@ cld /* * Test KEEP_SEGMENTS flag to see if the bootloader is asking -diff --git a/arch/x86/boot/compressed/head_64.S b/arch/x86/boot/compressed/head_64.S -index 35af09d..558d76c 100644 ---- a/arch/x86/boot/compressed/head_64.S -+++ b/arch/x86/boot/compressed/head_64.S -@@ -199,6 +199,26 @@ ENTRY(startup_64) +Index: linux-3.2.46/arch/x86/boot/compressed/head_64.S +=================================================================== +--- linux-3.2.46.orig/arch/x86/boot/compressed/head_64.S 2013-07-26 18:55:45.000000000 +0000 ++++ linux-3.2.46/arch/x86/boot/compressed/head_64.S 2013-07-26 19:19:52.000000000 +0000 +@@ -199,6 +199,26 @@ * an identity mapped page table being provied that maps our * entire text+data+bss and hopefully all of memory. */ @@ -1401,10 +1397,10 @@ /* Setup data segments. */ xorl %eax, %eax -diff --git a/arch/x86/boot/compressed/string.c b/arch/x86/boot/compressed/string.c -index 19b3e69..ffb9c5c 100644 ---- a/arch/x86/boot/compressed/string.c -+++ b/arch/x86/boot/compressed/string.c +Index: linux-3.2.46/arch/x86/boot/compressed/string.c +=================================================================== +--- linux-3.2.46.orig/arch/x86/boot/compressed/string.c 2013-07-26 18:55:45.000000000 +0000 ++++ linux-3.2.46/arch/x86/boot/compressed/string.c 2013-07-26 19:19:52.000000000 +0000 @@ -1,2 +1,11 @@ #include "misc.h" + @@ -1417,11 +1413,11 @@ +} + #include "../string.c" -diff --git a/arch/x86/boot/header.S b/arch/x86/boot/header.S -index bdb4d45..f1bbeeb 100644 ---- a/arch/x86/boot/header.S -+++ b/arch/x86/boot/header.S -@@ -45,6 +45,11 @@ SYSSEG = 0x1000 /* historical load address >> 4 */ +Index: linux-3.2.46/arch/x86/boot/header.S +=================================================================== +--- linux-3.2.46.orig/arch/x86/boot/header.S 2013-07-26 18:55:45.000000000 +0000 ++++ linux-3.2.46/arch/x86/boot/header.S 2013-07-26 19:19:52.000000000 +0000 +@@ -45,6 +45,11 @@ .global bootsect_start bootsect_start: @@ -1433,7 +1429,7 @@ # Normalize the start address ljmp $BOOTSEG, $start2 -@@ -79,6 +84,14 @@ bs_die: +@@ -79,6 +84,14 @@ # invoke the BIOS reset code... ljmp $0xf000,$0xfff0 @@ -1448,7 +1444,7 @@ .section ".bsdata", "a" bugger_off_msg: .ascii "Direct booting from floppy is no longer supported.\r\n" -@@ -87,6 +100,141 @@ bugger_off_msg: +@@ -87,6 +100,141 @@ .ascii "Remove disk and press any key to reboot . . .\r\n" .byte 0 @@ -1590,7 +1586,7 @@ # Kernel attributes; used by setup. This is part 1 of the # header, from the old boot sector. -@@ -318,3 +466,13 @@ die: +@@ -318,3 +466,13 @@ setup_corrupt: .byte 7 .string "No setup signature found...\n" @@ -1604,11 +1600,11 @@ + .long 10 + .word 0 +reloc_end: -diff --git a/arch/x86/boot/string.c b/arch/x86/boot/string.c -index 3cbc405..574dedf 100644 ---- a/arch/x86/boot/string.c -+++ b/arch/x86/boot/string.c -@@ -111,3 +111,38 @@ unsigned long long simple_strtoull(const char *cp, char **endp, unsigned int bas +Index: linux-3.2.46/arch/x86/boot/string.c +=================================================================== +--- linux-3.2.46.orig/arch/x86/boot/string.c 2013-07-26 18:55:45.000000000 +0000 ++++ linux-3.2.46/arch/x86/boot/string.c 2013-07-26 19:19:52.000000000 +0000 +@@ -111,3 +111,38 @@ return result; } @@ -1647,11 +1643,11 @@ + } + return NULL; +} -diff --git a/arch/x86/boot/tools/build.c b/arch/x86/boot/tools/build.c -index fdc60a0..4e9bd6b 100644 ---- a/arch/x86/boot/tools/build.c -+++ b/arch/x86/boot/tools/build.c -@@ -135,6 +135,9 @@ static void usage(void) +Index: linux-3.2.46/arch/x86/boot/tools/build.c +=================================================================== +--- linux-3.2.46.orig/arch/x86/boot/tools/build.c 2013-07-26 18:55:45.000000000 +0000 ++++ linux-3.2.46/arch/x86/boot/tools/build.c 2013-07-26 19:19:52.000000000 +0000 +@@ -135,6 +135,9 @@ int main(int argc, char ** argv) { @@ -1661,7 +1657,7 @@ unsigned int i, sz, setup_sectors; int c; u32 sys_size; -@@ -194,6 +197,42 @@ int main(int argc, char ** argv) +@@ -194,6 +197,42 @@ buf[0x1f6] = sys_size >> 16; buf[0x1f7] = sys_size >> 24; @@ -1704,17 +1700,14 @@ crc = partial_crc32(buf, i, crc); if (fwrite(buf, 1, i, stdout) != i) die("Writing setup failed"); -diff --git a/arch/x86/kernel/asm-offsets.c b/arch/x86/kernel/asm-offsets.c -index 4f13faf..68de2dc 100644 ---- a/arch/x86/kernel/asm-offsets.c -+++ b/arch/x86/kernel/asm-offsets.c -@@ -67,4 +67,6 @@ void common(void) { +Index: linux-3.2.46/arch/x86/kernel/asm-offsets.c +=================================================================== +--- linux-3.2.46.orig/arch/x86/kernel/asm-offsets.c 2013-07-26 18:55:45.000000000 +0000 ++++ linux-3.2.46/arch/x86/kernel/asm-offsets.c 2013-07-26 19:19:52.000000000 +0000 +@@ -67,4 +67,6 @@ OFFSET(BP_hardware_subarch, boot_params, hdr.hardware_subarch); OFFSET(BP_version, boot_params, hdr.version); OFFSET(BP_kernel_alignment, boot_params, hdr.kernel_alignment); + OFFSET(BP_pref_address, boot_params, hdr.pref_address); + OFFSET(BP_code32_start, boot_params, hdr.code32_start); } --- -1.7.10 - diff -Nru linux-3.2.46/debian/patches/features/x86/efi-stub/0010-x86-efi-Break-up-large-initrd-reads.patch linux-3.2.46/debian/patches/features/x86/efi-stub/0010-x86-efi-Break-up-large-initrd-reads.patch --- linux-3.2.46/debian/patches/features/x86/efi-stub/0010-x86-efi-Break-up-large-initrd-reads.patch 2013-02-24 03:52:26.000000000 +0000 +++ linux-3.2.46/debian/patches/features/x86/efi-stub/0010-x86-efi-Break-up-large-initrd-reads.patch 2013-07-26 19:19:55.000000000 +0000 @@ -22,11 +22,11 @@ arch/x86/boot/compressed/eboot.h | 1 + 2 files changed, 15 insertions(+), 6 deletions(-) -diff --git a/arch/x86/boot/compressed/eboot.c b/arch/x86/boot/compressed/eboot.c -index 4055e63..fec216f 100644 ---- a/arch/x86/boot/compressed/eboot.c -+++ b/arch/x86/boot/compressed/eboot.c -@@ -643,14 +643,22 @@ grow: +Index: linux-3.2.46/arch/x86/boot/compressed/eboot.c +=================================================================== +--- linux-3.2.46.orig/arch/x86/boot/compressed/eboot.c 2013-07-26 19:19:52.000000000 +0000 ++++ linux-3.2.46/arch/x86/boot/compressed/eboot.c 2013-07-26 19:19:54.000000000 +0000 +@@ -643,14 +643,22 @@ u64 size; size = initrds[j].size; @@ -55,10 +55,10 @@ } } -diff --git a/arch/x86/boot/compressed/eboot.h b/arch/x86/boot/compressed/eboot.h -index f66d023..3925166 100644 ---- a/arch/x86/boot/compressed/eboot.h -+++ b/arch/x86/boot/compressed/eboot.h +Index: linux-3.2.46/arch/x86/boot/compressed/eboot.h +=================================================================== +--- linux-3.2.46.orig/arch/x86/boot/compressed/eboot.h 2013-07-26 19:19:52.000000000 +0000 ++++ linux-3.2.46/arch/x86/boot/compressed/eboot.h 2013-07-26 19:19:54.000000000 +0000 @@ -12,6 +12,7 @@ #define DESC_TYPE_CODE_DATA (1 << 0) @@ -67,6 +67,3 @@ #define PIXEL_RGB_RESERVED_8BIT_PER_COLOR 0 #define PIXEL_BGR_RESERVED_8BIT_PER_COLOR 1 --- -1.7.10 - diff -Nru linux-3.2.46/debian/patches/features/x86/efi-stub/0011-x86-efi-Fix-pointer-math-issue-in-handle_ramdisks.patch linux-3.2.46/debian/patches/features/x86/efi-stub/0011-x86-efi-Fix-pointer-math-issue-in-handle_ramdisks.patch --- linux-3.2.46/debian/patches/features/x86/efi-stub/0011-x86-efi-Fix-pointer-math-issue-in-handle_ramdisks.patch 2013-02-24 03:52:26.000000000 +0000 +++ linux-3.2.46/debian/patches/features/x86/efi-stub/0011-x86-efi-Fix-pointer-math-issue-in-handle_ramdisks.patch 2013-07-26 19:19:56.000000000 +0000 @@ -19,11 +19,11 @@ arch/x86/boot/compressed/eboot.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) -diff --git a/arch/x86/boot/compressed/eboot.c b/arch/x86/boot/compressed/eboot.c -index fec216f..0cdfc0d 100644 ---- a/arch/x86/boot/compressed/eboot.c -+++ b/arch/x86/boot/compressed/eboot.c -@@ -539,7 +539,7 @@ static efi_status_t handle_ramdisks(efi_loaded_image_t *image, +Index: linux-3.2.46/arch/x86/boot/compressed/eboot.c +=================================================================== +--- linux-3.2.46.orig/arch/x86/boot/compressed/eboot.c 2013-07-26 19:19:54.000000000 +0000 ++++ linux-3.2.46/arch/x86/boot/compressed/eboot.c 2013-07-26 19:19:55.000000000 +0000 +@@ -539,7 +539,7 @@ struct initrd *initrd; efi_file_handle_t *h; efi_file_info_t *info; @@ -32,7 +32,7 @@ unsigned long info_sz; efi_guid_t info_guid = EFI_FILE_INFO_ID; efi_char16_t *p; -@@ -552,14 +552,14 @@ static efi_status_t handle_ramdisks(efi_loaded_image_t *image, +@@ -552,14 +552,14 @@ str += 7; initrd = &initrds[i]; @@ -49,7 +49,7 @@ break; *p++ = *str++; -@@ -583,7 +583,7 @@ static efi_status_t handle_ramdisks(efi_loaded_image_t *image, +@@ -583,7 +583,7 @@ goto free_initrds; } @@ -58,6 +58,3 @@ EFI_FILE_MODE_READ, (u64)0); if (status != EFI_SUCCESS) goto close_handles; --- -1.7.10 - diff -Nru linux-3.2.46/debian/patches/features/x86/efi-stub/0012-tools-include-Add-byteshift-headers-for-endian-acces.patch linux-3.2.46/debian/patches/features/x86/efi-stub/0012-tools-include-Add-byteshift-headers-for-endian-acces.patch --- linux-3.2.46/debian/patches/features/x86/efi-stub/0012-tools-include-Add-byteshift-headers-for-endian-acces.patch 2013-02-24 03:52:26.000000000 +0000 +++ linux-3.2.46/debian/patches/features/x86/efi-stub/0012-tools-include-Add-byteshift-headers-for-endian-acces.patch 2013-07-26 19:19:58.000000000 +0000 @@ -22,11 +22,10 @@ create mode 100644 tools/include/tools/be_byteshift.h create mode 100644 tools/include/tools/le_byteshift.h -diff --git a/tools/include/tools/be_byteshift.h b/tools/include/tools/be_byteshift.h -new file mode 100644 -index 0000000..f4912e2 ---- /dev/null -+++ b/tools/include/tools/be_byteshift.h +Index: linux-3.2.46/tools/include/tools/be_byteshift.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/tools/include/tools/be_byteshift.h 2013-07-26 19:19:57.000000000 +0000 @@ -0,0 +1,70 @@ +#ifndef _TOOLS_BE_BYTESHIFT_H +#define _TOOLS_BE_BYTESHIFT_H @@ -98,11 +97,10 @@ +} + +#endif /* _TOOLS_BE_BYTESHIFT_H */ -diff --git a/tools/include/tools/le_byteshift.h b/tools/include/tools/le_byteshift.h -new file mode 100644 -index 0000000..c99d45a ---- /dev/null -+++ b/tools/include/tools/le_byteshift.h +Index: linux-3.2.46/tools/include/tools/le_byteshift.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/tools/include/tools/le_byteshift.h 2013-07-26 19:19:57.000000000 +0000 @@ -0,0 +1,70 @@ +#ifndef _TOOLS_LE_BYTESHIFT_H +#define _TOOLS_LE_BYTESHIFT_H @@ -174,6 +172,3 @@ +} + +#endif /* _TOOLS_LE_BYTESHIFT_H */ --- -1.7.10 - diff -Nru linux-3.2.46/debian/patches/features/x86/efi-stub/0013-x86-mkpiggy-Don-t-open-code-put_unaligned_le32.patch linux-3.2.46/debian/patches/features/x86/efi-stub/0013-x86-mkpiggy-Don-t-open-code-put_unaligned_le32.patch --- linux-3.2.46/debian/patches/features/x86/efi-stub/0013-x86-mkpiggy-Don-t-open-code-put_unaligned_le32.patch 2013-02-24 03:52:26.000000000 +0000 +++ linux-3.2.46/debian/patches/features/x86/efi-stub/0013-x86-mkpiggy-Don-t-open-code-put_unaligned_le32.patch 2013-07-26 19:19:59.000000000 +0000 @@ -16,11 +16,11 @@ arch/x86/boot/compressed/mkpiggy.c | 11 ++--------- 2 files changed, 3 insertions(+), 9 deletions(-) -diff --git a/arch/x86/boot/compressed/Makefile b/arch/x86/boot/compressed/Makefile -index b123b9a..fd55a2f 100644 ---- a/arch/x86/boot/compressed/Makefile -+++ b/arch/x86/boot/compressed/Makefile -@@ -22,6 +22,7 @@ LDFLAGS := -m elf_$(UTS_MACHINE) +Index: linux-3.2.46/arch/x86/boot/compressed/Makefile +=================================================================== +--- linux-3.2.46.orig/arch/x86/boot/compressed/Makefile 2013-07-26 19:19:52.000000000 +0000 ++++ linux-3.2.46/arch/x86/boot/compressed/Makefile 2013-07-26 19:19:58.000000000 +0000 +@@ -22,6 +22,7 @@ LDFLAGS_vmlinux := -T hostprogs-y := mkpiggy @@ -28,10 +28,10 @@ VMLINUX_OBJS = $(obj)/vmlinux.lds $(obj)/head_$(BITS).o $(obj)/misc.o \ $(obj)/string.o $(obj)/cmdline.o $(obj)/early_serial_console.o \ -diff --git a/arch/x86/boot/compressed/mkpiggy.c b/arch/x86/boot/compressed/mkpiggy.c -index 46a8238..958a641 100644 ---- a/arch/x86/boot/compressed/mkpiggy.c -+++ b/arch/x86/boot/compressed/mkpiggy.c +Index: linux-3.2.46/arch/x86/boot/compressed/mkpiggy.c +=================================================================== +--- linux-3.2.46.orig/arch/x86/boot/compressed/mkpiggy.c 2013-07-26 18:55:43.000000000 +0000 ++++ linux-3.2.46/arch/x86/boot/compressed/mkpiggy.c 2013-07-26 19:19:58.000000000 +0000 @@ -29,14 +29,7 @@ #include #include @@ -48,7 +48,7 @@ int main(int argc, char *argv[]) { -@@ -69,7 +62,7 @@ int main(int argc, char *argv[]) +@@ -69,7 +62,7 @@ } ilen = ftell(f); @@ -57,6 +57,3 @@ fclose(f); /* --- -1.7.10 - diff -Nru linux-3.2.46/debian/patches/features/x86/efi-stub/0014-x86-boot-Restrict-CFLAGS-for-hostprogs.patch linux-3.2.46/debian/patches/features/x86/efi-stub/0014-x86-boot-Restrict-CFLAGS-for-hostprogs.patch --- linux-3.2.46/debian/patches/features/x86/efi-stub/0014-x86-boot-Restrict-CFLAGS-for-hostprogs.patch 2013-02-24 03:52:26.000000000 +0000 +++ linux-3.2.46/debian/patches/features/x86/efi-stub/0014-x86-boot-Restrict-CFLAGS-for-hostprogs.patch 2013-07-26 19:20:00.000000000 +0000 @@ -20,11 +20,11 @@ arch/x86/boot/Makefile | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) -diff --git a/arch/x86/boot/Makefile b/arch/x86/boot/Makefile -index 95365a8..3e02148 100644 ---- a/arch/x86/boot/Makefile -+++ b/arch/x86/boot/Makefile -@@ -37,8 +37,9 @@ setup-y += video-bios.o +Index: linux-3.2.46/arch/x86/boot/Makefile +=================================================================== +--- linux-3.2.46.orig/arch/x86/boot/Makefile 2013-07-26 18:55:42.000000000 +0000 ++++ linux-3.2.46/arch/x86/boot/Makefile 2013-07-26 19:19:59.000000000 +0000 +@@ -37,8 +37,9 @@ targets += $(setup-y) hostprogs-y := mkcpustr tools/build @@ -36,6 +36,3 @@ $(obj)/cpu.o: $(obj)/cpustr.h quiet_cmd_cpustr = CPUSTR $@ --- -1.7.10 - diff -Nru linux-3.2.46/debian/patches/features/x86/efi-stub/0015-x86-efi-Fix-endian-issues-and-unaligned-accesses.patch linux-3.2.46/debian/patches/features/x86/efi-stub/0015-x86-efi-Fix-endian-issues-and-unaligned-accesses.patch --- linux-3.2.46/debian/patches/features/x86/efi-stub/0015-x86-efi-Fix-endian-issues-and-unaligned-accesses.patch 2013-02-24 03:52:26.000000000 +0000 +++ linux-3.2.46/debian/patches/features/x86/efi-stub/0015-x86-efi-Fix-endian-issues-and-unaligned-accesses.patch 2013-07-26 19:20:01.000000000 +0000 @@ -25,10 +25,10 @@ arch/x86/boot/tools/build.c | 31 +++++++++++++++---------------- 1 file changed, 15 insertions(+), 16 deletions(-) -diff --git a/arch/x86/boot/tools/build.c b/arch/x86/boot/tools/build.c -index 4e9bd6b..f2ac95e 100644 ---- a/arch/x86/boot/tools/build.c -+++ b/arch/x86/boot/tools/build.c +Index: linux-3.2.46/arch/x86/boot/tools/build.c +=================================================================== +--- linux-3.2.46.orig/arch/x86/boot/tools/build.c 2013-07-26 19:19:52.000000000 +0000 ++++ linux-3.2.46/arch/x86/boot/tools/build.c 2013-07-26 19:20:01.000000000 +0000 @@ -34,6 +34,7 @@ #include #include @@ -37,7 +37,7 @@ typedef unsigned char u8; typedef unsigned short u16; -@@ -41,6 +42,7 @@ typedef unsigned long u32; +@@ -41,6 +42,7 @@ #define DEFAULT_MAJOR_ROOT 0 #define DEFAULT_MINOR_ROOT 0 @@ -45,7 +45,7 @@ /* Minimal number of setup sectors */ #define SETUP_SECT_MIN 5 -@@ -159,7 +161,7 @@ int main(int argc, char ** argv) +@@ -159,7 +161,7 @@ die("read-error on `setup'"); if (c < 1024) die("The setup must be at least 1024 bytes"); @@ -54,7 +54,7 @@ die("Boot block hasn't got boot flag (0xAA55)"); fclose(file); -@@ -171,8 +173,7 @@ int main(int argc, char ** argv) +@@ -171,8 +173,7 @@ memset(buf+c, 0, i-c); /* Set the default root device */ @@ -64,7 +64,7 @@ fprintf(stderr, "Setup is %d bytes (padded to %d bytes).\n", c, i); -@@ -192,44 +193,42 @@ int main(int argc, char ** argv) +@@ -192,44 +193,42 @@ /* Patch the setup code with the appropriate size parameters */ buf[0x1f1] = setup_sectors-1; @@ -120,6 +120,3 @@ #endif /* CONFIG_X86_32 */ #endif /* CONFIG_EFI_STUB */ --- -1.7.10 - diff -Nru linux-3.2.46/debian/patches/features/x86/efi-stub/0016-x86-boot-Correct-CFLAGS-for-hostprogs.patch linux-3.2.46/debian/patches/features/x86/efi-stub/0016-x86-boot-Correct-CFLAGS-for-hostprogs.patch --- linux-3.2.46/debian/patches/features/x86/efi-stub/0016-x86-boot-Correct-CFLAGS-for-hostprogs.patch 2013-02-24 03:52:26.000000000 +0000 +++ linux-3.2.46/debian/patches/features/x86/efi-stub/0016-x86-boot-Correct-CFLAGS-for-hostprogs.patch 2013-07-26 19:20:04.000000000 +0000 @@ -28,11 +28,11 @@ arch/x86/boot/Makefile | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) -diff --git a/arch/x86/boot/Makefile b/arch/x86/boot/Makefile -index 3e02148..5a747dd 100644 ---- a/arch/x86/boot/Makefile -+++ b/arch/x86/boot/Makefile -@@ -37,9 +37,9 @@ setup-y += video-bios.o +Index: linux-3.2.46/arch/x86/boot/Makefile +=================================================================== +--- linux-3.2.46.orig/arch/x86/boot/Makefile 2013-07-26 19:19:59.000000000 +0000 ++++ linux-3.2.46/arch/x86/boot/Makefile 2013-07-26 19:20:02.000000000 +0000 +@@ -37,9 +37,9 @@ targets += $(setup-y) hostprogs-y := mkcpustr tools/build @@ -45,6 +45,3 @@ $(obj)/cpu.o: $(obj)/cpustr.h quiet_cmd_cpustr = CPUSTR $@ --- -1.7.10 - diff -Nru linux-3.2.46/debian/patches/features/x86/efi-stub/0017-x86-efi-Add-dedicated-EFI-stub-entry-point.patch linux-3.2.46/debian/patches/features/x86/efi-stub/0017-x86-efi-Add-dedicated-EFI-stub-entry-point.patch --- linux-3.2.46/debian/patches/features/x86/efi-stub/0017-x86-efi-Add-dedicated-EFI-stub-entry-point.patch 2013-02-24 03:52:26.000000000 +0000 +++ linux-3.2.46/debian/patches/features/x86/efi-stub/0017-x86-efi-Add-dedicated-EFI-stub-entry-point.patch 2013-07-26 19:20:06.000000000 +0000 @@ -30,10 +30,10 @@ arch/x86/boot/tools/build.c | 15 +++++++++++---- 3 files changed, 38 insertions(+), 13 deletions(-) -diff --git a/arch/x86/boot/compressed/head_32.S b/arch/x86/boot/compressed/head_32.S -index a055993..c85e3ac 100644 ---- a/arch/x86/boot/compressed/head_32.S -+++ b/arch/x86/boot/compressed/head_32.S +Index: linux-3.2.46/arch/x86/boot/compressed/head_32.S +=================================================================== +--- linux-3.2.46.orig/arch/x86/boot/compressed/head_32.S 2013-07-26 19:19:52.000000000 +0000 ++++ linux-3.2.46/arch/x86/boot/compressed/head_32.S 2013-07-26 19:20:04.000000000 +0000 @@ -33,6 +33,9 @@ __HEAD ENTRY(startup_32) @@ -44,7 +44,7 @@ /* * We don't need the return address, so set up the stack so * efi_main() can find its arugments. -@@ -41,12 +44,17 @@ ENTRY(startup_32) +@@ -41,12 +44,17 @@ call efi_main cmpl $0, %eax @@ -65,11 +65,11 @@ subl BP_pref_address(%esi), %eax add BP_code32_start(%esi), %eax leal preferred_addr(%eax), %eax -diff --git a/arch/x86/boot/compressed/head_64.S b/arch/x86/boot/compressed/head_64.S -index 558d76c..87e03a1 100644 ---- a/arch/x86/boot/compressed/head_64.S -+++ b/arch/x86/boot/compressed/head_64.S -@@ -200,18 +200,28 @@ ENTRY(startup_64) +Index: linux-3.2.46/arch/x86/boot/compressed/head_64.S +=================================================================== +--- linux-3.2.46.orig/arch/x86/boot/compressed/head_64.S 2013-07-26 19:19:52.000000000 +0000 ++++ linux-3.2.46/arch/x86/boot/compressed/head_64.S 2013-07-26 19:20:04.000000000 +0000 +@@ -200,18 +200,28 @@ * entire text+data+bss and hopefully all of memory. */ #ifdef CONFIG_EFI_STUB @@ -104,11 +104,11 @@ subq BP_pref_address(%rsi), %rax add BP_code32_start(%esi), %eax leaq preferred_addr(%rax), %rax -diff --git a/arch/x86/boot/tools/build.c b/arch/x86/boot/tools/build.c -index ed54976..24443a3 100644 ---- a/arch/x86/boot/tools/build.c -+++ b/arch/x86/boot/tools/build.c -@@ -205,8 +205,13 @@ int main(int argc, char ** argv) +Index: linux-3.2.46/arch/x86/boot/tools/build.c +=================================================================== +--- linux-3.2.46.orig/arch/x86/boot/tools/build.c 2013-07-26 19:20:01.000000000 +0000 ++++ linux-3.2.46/arch/x86/boot/tools/build.c 2013-07-26 19:20:04.000000000 +0000 +@@ -207,8 +207,13 @@ put_unaligned_le32(file_sz, &buf[pe_header + 0x50]); #ifdef CONFIG_X86_32 @@ -124,7 +124,7 @@ /* .text size */ put_unaligned_le32(file_sz, &buf[pe_header + 0xb0]); -@@ -217,9 +222,11 @@ int main(int argc, char ** argv) +@@ -219,9 +224,11 @@ /* * Address of entry point. startup_32 is at the beginning and * the 64-bit entry point (startup_64) is always 512 bytes @@ -138,6 +138,3 @@ /* .text size */ put_unaligned_le32(file_sz, &buf[pe_header + 0xc0]); --- -1.7.10 - diff -Nru linux-3.2.46/debian/patches/features/x86/efi-stub/0018-efi-Build-EFI-stub-with-EFI-appropriate-options.patch linux-3.2.46/debian/patches/features/x86/efi-stub/0018-efi-Build-EFI-stub-with-EFI-appropriate-options.patch --- linux-3.2.46/debian/patches/features/x86/efi-stub/0018-efi-Build-EFI-stub-with-EFI-appropriate-options.patch 2013-02-24 03:52:26.000000000 +0000 +++ linux-3.2.46/debian/patches/features/x86/efi-stub/0018-efi-Build-EFI-stub-with-EFI-appropriate-options.patch 2013-07-26 19:20:07.000000000 +0000 @@ -15,11 +15,11 @@ arch/x86/boot/compressed/Makefile | 3 +++ 1 file changed, 3 insertions(+) -diff --git a/arch/x86/boot/compressed/Makefile b/arch/x86/boot/compressed/Makefile -index e398bb5..8a84501 100644 ---- a/arch/x86/boot/compressed/Makefile -+++ b/arch/x86/boot/compressed/Makefile -@@ -28,6 +28,9 @@ VMLINUX_OBJS = $(obj)/vmlinux.lds $(obj)/head_$(BITS).o $(obj)/misc.o \ +Index: linux-3.2.46/arch/x86/boot/compressed/Makefile +=================================================================== +--- linux-3.2.46.orig/arch/x86/boot/compressed/Makefile 2013-07-26 19:19:58.000000000 +0000 ++++ linux-3.2.46/arch/x86/boot/compressed/Makefile 2013-07-26 19:20:06.000000000 +0000 +@@ -28,6 +28,9 @@ $(obj)/string.o $(obj)/cmdline.o $(obj)/early_serial_console.o \ $(obj)/piggy.o diff -Nru linux-3.2.46/debian/patches/features/x86/efi-stub/0019-x86-efi-Fix-processor-specific-memcpy-build-error.patch linux-3.2.46/debian/patches/features/x86/efi-stub/0019-x86-efi-Fix-processor-specific-memcpy-build-error.patch --- linux-3.2.46/debian/patches/features/x86/efi-stub/0019-x86-efi-Fix-processor-specific-memcpy-build-error.patch 2013-04-11 03:27:32.000000000 +0000 +++ linux-3.2.46/debian/patches/features/x86/efi-stub/0019-x86-efi-Fix-processor-specific-memcpy-build-error.patch 2013-07-26 19:30:23.000000000 +0000 @@ -27,10 +27,10 @@ arch/x86/boot/compressed/eboot.c | 2 ++ 1 file changed, 2 insertions(+) -diff --git a/arch/x86/boot/compressed/eboot.c b/arch/x86/boot/compressed/eboot.c -index c760e07..e87b0ca 100644 ---- a/arch/x86/boot/compressed/eboot.c -+++ b/arch/x86/boot/compressed/eboot.c +Index: linux-3.2.46/arch/x86/boot/compressed/eboot.c +=================================================================== +--- linux-3.2.46.orig/arch/x86/boot/compressed/eboot.c 2013-07-26 19:19:55.000000000 +0000 ++++ linux-3.2.46/arch/x86/boot/compressed/eboot.c 2013-07-26 19:30:22.000000000 +0000 @@ -12,6 +12,8 @@ #include #include diff -Nru linux-3.2.46/debian/patches/features/x86/hyperv/0002-HID-Move-the-hid-hyperv-driver-out-of-staging.patch linux-3.2.46/debian/patches/features/x86/hyperv/0002-HID-Move-the-hid-hyperv-driver-out-of-staging.patch --- linux-3.2.46/debian/patches/features/x86/hyperv/0002-HID-Move-the-hid-hyperv-driver-out-of-staging.patch 2013-02-24 03:52:26.000000000 +0000 +++ linux-3.2.46/debian/patches/features/x86/hyperv/0002-HID-Move-the-hid-hyperv-driver-out-of-staging.patch 2013-07-26 19:17:58.000000000 +0000 @@ -24,11 +24,11 @@ 3 files changed, 589 insertions(+) create mode 100644 drivers/hid/hid-hyperv.c -diff --git a/drivers/hid/Kconfig b/drivers/hid/Kconfig -index d21f6d0..4c09210 100644 ---- a/drivers/hid/Kconfig -+++ b/drivers/hid/Kconfig -@@ -646,6 +646,12 @@ config HID_ZYDACRON +Index: linux-3.2.46/drivers/hid/Kconfig +=================================================================== +--- linux-3.2.46.orig/drivers/hid/Kconfig 2013-07-26 18:56:21.000000000 +0000 ++++ linux-3.2.46/drivers/hid/Kconfig 2013-07-26 19:17:57.000000000 +0000 +@@ -647,6 +647,12 @@ ---help--- Support for Zydacron remote control. @@ -41,11 +41,11 @@ endmenu endif # HID_SUPPORT -diff --git a/drivers/hid/Makefile b/drivers/hid/Makefile -index 1e0d2a6..fbb1ee6 100644 ---- a/drivers/hid/Makefile -+++ b/drivers/hid/Makefile -@@ -78,6 +78,7 @@ obj-$(CONFIG_HID_ZYDACRON) += hid-zydacron.o +Index: linux-3.2.46/drivers/hid/Makefile +=================================================================== +--- linux-3.2.46.orig/drivers/hid/Makefile 2013-07-26 18:56:21.000000000 +0000 ++++ linux-3.2.46/drivers/hid/Makefile 2013-07-26 19:17:57.000000000 +0000 +@@ -78,6 +78,7 @@ obj-$(CONFIG_HID_WACOM) += hid-wacom.o obj-$(CONFIG_HID_WALTOP) += hid-waltop.o obj-$(CONFIG_HID_WIIMOTE) += hid-wiimote.o @@ -53,11 +53,10 @@ obj-$(CONFIG_USB_HID) += usbhid/ obj-$(CONFIG_USB_MOUSE) += usbhid/ -diff --git a/drivers/hid/hid-hyperv.c b/drivers/hid/hid-hyperv.c -new file mode 100644 -index 0000000..d503cbb ---- /dev/null -+++ b/drivers/hid/hid-hyperv.c +Index: linux-3.2.46/drivers/hid/hid-hyperv.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/hid/hid-hyperv.c 2013-07-26 19:17:57.000000000 +0000 @@ -0,0 +1,582 @@ +/* + * Copyright (c) 2009, Citrix Systems, Inc. @@ -641,6 +640,3 @@ +MODULE_VERSION(HV_DRV_VERSION); +module_init(mousevsc_init); +module_exit(mousevsc_exit); --- -1.7.9.5 - diff -Nru linux-3.2.46/debian/patches/features/x86/hyperv/0003-Staging-hv-storvsc-Use-mempools-to-allocate-struct-s.patch linux-3.2.46/debian/patches/features/x86/hyperv/0003-Staging-hv-storvsc-Use-mempools-to-allocate-struct-s.patch --- linux-3.2.46/debian/patches/features/x86/hyperv/0003-Staging-hv-storvsc-Use-mempools-to-allocate-struct-s.patch 2013-02-24 03:52:26.000000000 +0000 +++ linux-3.2.46/debian/patches/features/x86/hyperv/0003-Staging-hv-storvsc-Use-mempools-to-allocate-struct-s.patch 2013-07-26 19:18:00.000000000 +0000 @@ -15,10 +15,10 @@ drivers/staging/hv/storvsc_drv.c | 30 +++++++++++++++++++++++++----- 1 file changed, 25 insertions(+), 5 deletions(-) -diff --git a/drivers/staging/hv/storvsc_drv.c b/drivers/staging/hv/storvsc_drv.c -index ae8c33e..6a255e9 100644 ---- a/drivers/staging/hv/storvsc_drv.c -+++ b/drivers/staging/hv/storvsc_drv.c +Index: linux-3.2.46/drivers/staging/hv/storvsc_drv.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/hv/storvsc_drv.c 2013-07-26 18:56:20.000000000 +0000 ++++ linux-3.2.46/drivers/staging/hv/storvsc_drv.c 2013-07-26 19:17:59.000000000 +0000 @@ -32,6 +32,7 @@ #include #include @@ -35,7 +35,7 @@ #define STORVSC_RING_BUFFER_SIZE (20*PAGE_SIZE) static int storvsc_ringbuffer_size = STORVSC_RING_BUFFER_SIZE; -@@ -287,6 +289,7 @@ struct storvsc_device { +@@ -287,6 +289,7 @@ struct hv_host_device { struct hv_device *dev; struct kmem_cache *request_pool; @@ -43,7 +43,7 @@ unsigned int port; unsigned char path; unsigned char target; -@@ -974,8 +977,10 @@ static int storvsc_remove(struct hv_device *dev) +@@ -975,8 +978,10 @@ storvsc_dev_remove(dev); if (host_dev->request_pool) { @@ -54,7 +54,7 @@ } return 0; } -@@ -1120,7 +1125,7 @@ static void storvsc_command_completion(struct hv_storvsc_request *request) +@@ -1126,7 +1131,7 @@ scsi_done_fn(scmnd); @@ -63,7 +63,7 @@ } static bool storvsc_check_scsi_cmd(struct scsi_cmnd *scmnd) -@@ -1176,12 +1181,13 @@ static int storvsc_queuecommand_lck(struct scsi_cmnd *scmnd, +@@ -1182,12 +1187,13 @@ request_size = sizeof(struct storvsc_cmd_request); @@ -78,7 +78,7 @@ /* Setup the cmd request */ cmd_request->bounce_sgl_count = 0; -@@ -1235,8 +1241,8 @@ static int storvsc_queuecommand_lck(struct scsi_cmnd *scmnd, +@@ -1241,8 +1247,8 @@ if (!cmd_request->bounce_sgl) { scmnd->scsi_done = NULL; scmnd->host_scribble = NULL; @@ -89,7 +89,7 @@ return SCSI_MLQUEUE_HOST_BUSY; } -@@ -1278,7 +1284,7 @@ retry_request: +@@ -1284,7 +1290,7 @@ destroy_bounce_buffer(cmd_request->bounce_sgl, cmd_request->bounce_sgl_count); @@ -98,7 +98,7 @@ scmnd->scsi_done = NULL; scmnd->host_scribble = NULL; -@@ -1348,6 +1354,7 @@ static int storvsc_probe(struct hv_device *device, +@@ -1354,6 +1360,7 @@ const struct hv_vmbus_device_id *dev_id) { int ret; @@ -106,7 +106,7 @@ struct Scsi_Host *host; struct hv_host_device *host_dev; bool dev_is_ide = ((dev_id->driver_data == IDE_GUID) ? true : false); -@@ -1376,8 +1383,19 @@ static int storvsc_probe(struct hv_device *device, +@@ -1382,8 +1389,19 @@ return -ENOMEM; } @@ -126,7 +126,7 @@ kmem_cache_destroy(host_dev->request_pool); scsi_host_put(host); return -ENOMEM; -@@ -1392,6 +1410,7 @@ static int storvsc_probe(struct hv_device *device, +@@ -1398,6 +1416,7 @@ stor_device->port_number = host->host_no; ret = storvsc_connect_to_vsp(device, storvsc_ringbuffer_size); if (ret) { @@ -134,7 +134,7 @@ kmem_cache_destroy(host_dev->request_pool); scsi_host_put(host); kfree(stor_device); -@@ -1431,6 +1450,7 @@ static int storvsc_probe(struct hv_device *device, +@@ -1437,6 +1456,7 @@ err_out: storvsc_dev_remove(device); @@ -142,6 +142,3 @@ kmem_cache_destroy(host_dev->request_pool); scsi_host_put(host); return -ENODEV; --- -1.7.9.5 - diff -Nru linux-3.2.46/debian/patches/features/x86/hyperv/0004-Staging-hv-storvsc-Cleanup-error-handling-in-the-pro.patch linux-3.2.46/debian/patches/features/x86/hyperv/0004-Staging-hv-storvsc-Cleanup-error-handling-in-the-pro.patch --- linux-3.2.46/debian/patches/features/x86/hyperv/0004-Staging-hv-storvsc-Cleanup-error-handling-in-the-pro.patch 2013-02-24 03:52:26.000000000 +0000 +++ linux-3.2.46/debian/patches/features/x86/hyperv/0004-Staging-hv-storvsc-Cleanup-error-handling-in-the-pro.patch 2013-07-26 19:18:01.000000000 +0000 @@ -14,11 +14,11 @@ drivers/staging/hv/storvsc_drv.c | 42 ++++++++++++++++++++++---------------- 1 file changed, 24 insertions(+), 18 deletions(-) -diff --git a/drivers/staging/hv/storvsc_drv.c b/drivers/staging/hv/storvsc_drv.c -index 6a255e9..a72cc22 100644 ---- a/drivers/staging/hv/storvsc_drv.c -+++ b/drivers/staging/hv/storvsc_drv.c -@@ -1388,17 +1388,14 @@ static int storvsc_probe(struct hv_device *device, +Index: linux-3.2.46/drivers/staging/hv/storvsc_drv.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/hv/storvsc_drv.c 2013-07-26 19:17:59.000000000 +0000 ++++ linux-3.2.46/drivers/staging/hv/storvsc_drv.c 2013-07-26 19:18:00.000000000 +0000 +@@ -1394,17 +1394,14 @@ host_dev->request_pool); if (!host_dev->request_mempool) { @@ -40,7 +40,7 @@ } stor_device->destroy = false; -@@ -1409,13 +1406,8 @@ static int storvsc_probe(struct hv_device *device, +@@ -1415,13 +1412,8 @@ stor_device->port_number = host->host_no; ret = storvsc_connect_to_vsp(device, storvsc_ringbuffer_size); @@ -56,7 +56,7 @@ if (dev_is_ide) storvsc_get_ide_info(device, &target, &path); -@@ -1435,7 +1427,7 @@ static int storvsc_probe(struct hv_device *device, +@@ -1441,7 +1433,7 @@ /* Register the HBA and start the scsi bus scan */ ret = scsi_add_host(host, &device->device); if (ret != 0) @@ -65,7 +65,7 @@ if (!dev_is_ide) { scsi_scan_host(host); -@@ -1444,16 +1436,30 @@ static int storvsc_probe(struct hv_device *device, +@@ -1450,16 +1442,30 @@ ret = scsi_add_device(host, 0, target, 0); if (ret) { scsi_remove_host(host); @@ -99,6 +99,3 @@ } /* The one and only one */ --- -1.7.9.5 - diff -Nru linux-3.2.46/debian/patches/features/x86/hyperv/0005-Staging-hv-storvsc-Fixup-the-error-when-processing-S.patch linux-3.2.46/debian/patches/features/x86/hyperv/0005-Staging-hv-storvsc-Fixup-the-error-when-processing-S.patch --- linux-3.2.46/debian/patches/features/x86/hyperv/0005-Staging-hv-storvsc-Fixup-the-error-when-processing-S.patch 2013-02-24 03:52:26.000000000 +0000 +++ linux-3.2.46/debian/patches/features/x86/hyperv/0005-Staging-hv-storvsc-Fixup-the-error-when-processing-S.patch 2013-07-26 19:18:02.000000000 +0000 @@ -14,11 +14,11 @@ drivers/staging/hv/storvsc_drv.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -diff --git a/drivers/staging/hv/storvsc_drv.c b/drivers/staging/hv/storvsc_drv.c -index a72cc22..e16c7a3 100644 ---- a/drivers/staging/hv/storvsc_drv.c -+++ b/drivers/staging/hv/storvsc_drv.c -@@ -1136,7 +1136,7 @@ static bool storvsc_check_scsi_cmd(struct scsi_cmnd *scmnd) +Index: linux-3.2.46/drivers/staging/hv/storvsc_drv.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/hv/storvsc_drv.c 2013-07-26 19:18:00.000000000 +0000 ++++ linux-3.2.46/drivers/staging/hv/storvsc_drv.c 2013-07-26 19:18:01.000000000 +0000 +@@ -1142,7 +1142,7 @@ switch (scsi_op) { /* smartd sends this command, which will offline the device */ case SET_WINDOW: @@ -27,6 +27,3 @@ allowed = false; break; default: --- -1.7.9.5 - diff -Nru linux-3.2.46/debian/patches/features/x86/hyperv/0006-Staging-hv-storvsc-Fix-error-handling-storvsc_host_r.patch linux-3.2.46/debian/patches/features/x86/hyperv/0006-Staging-hv-storvsc-Fix-error-handling-storvsc_host_r.patch --- linux-3.2.46/debian/patches/features/x86/hyperv/0006-Staging-hv-storvsc-Fix-error-handling-storvsc_host_r.patch 2013-02-24 03:52:26.000000000 +0000 +++ linux-3.2.46/debian/patches/features/x86/hyperv/0006-Staging-hv-storvsc-Fix-error-handling-storvsc_host_r.patch 2013-07-26 19:18:03.000000000 +0000 @@ -16,9 +16,11 @@ drivers/staging/hv/storvsc_drv.c | 20 ++++++-------------- 1 file changed, 6 insertions(+), 14 deletions(-) ---- a/drivers/staging/hv/storvsc_drv.c -+++ b/drivers/staging/hv/storvsc_drv.c -@@ -1019,7 +1019,7 @@ static int storvsc_host_reset(struct hv_ +Index: linux-3.2.46/drivers/staging/hv/storvsc_drv.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/hv/storvsc_drv.c 2013-07-26 19:18:01.000000000 +0000 ++++ linux-3.2.46/drivers/staging/hv/storvsc_drv.c 2013-07-26 19:18:03.000000000 +0000 +@@ -1020,7 +1020,7 @@ stor_device = get_out_stor_device(device); if (!stor_device) @@ -27,7 +29,7 @@ request = &stor_device->reset_request; vstor_packet = &request->vstor_packet; -@@ -1036,13 +1036,11 @@ static int storvsc_host_reset(struct hv_ +@@ -1037,13 +1037,11 @@ VM_PKT_DATA_INBAND, VMBUS_DATA_PACKET_FLAG_COMPLETION_REQUESTED); if (ret != 0) @@ -44,7 +46,7 @@ /* -@@ -1055,8 +1053,7 @@ static int storvsc_host_reset(struct hv_ +@@ -1056,8 +1054,7 @@ */ storvsc_wait_to_drain(stor_device); @@ -54,7 +56,7 @@ } -@@ -1065,16 +1062,11 @@ cleanup: +@@ -1066,16 +1063,11 @@ */ static int storvsc_host_reset_handler(struct scsi_cmnd *scmnd) { diff -Nru linux-3.2.46/debian/patches/features/x86/hyperv/0007-Staging-hv-storvsc-Use-the-accessor-function-shost_p.patch linux-3.2.46/debian/patches/features/x86/hyperv/0007-Staging-hv-storvsc-Use-the-accessor-function-shost_p.patch --- linux-3.2.46/debian/patches/features/x86/hyperv/0007-Staging-hv-storvsc-Use-the-accessor-function-shost_p.patch 2013-02-24 03:52:26.000000000 +0000 +++ linux-3.2.46/debian/patches/features/x86/hyperv/0007-Staging-hv-storvsc-Use-the-accessor-function-shost_p.patch 2013-07-26 19:18:05.000000000 +0000 @@ -14,11 +14,11 @@ drivers/staging/hv/storvsc_drv.c | 14 +++++--------- 1 file changed, 5 insertions(+), 9 deletions(-) -diff --git a/drivers/staging/hv/storvsc_drv.c b/drivers/staging/hv/storvsc_drv.c -index a145245..b21e85f 100644 ---- a/drivers/staging/hv/storvsc_drv.c -+++ b/drivers/staging/hv/storvsc_drv.c -@@ -968,8 +968,7 @@ static int storvsc_remove(struct hv_device *dev) +Index: linux-3.2.46/drivers/staging/hv/storvsc_drv.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/hv/storvsc_drv.c 2013-07-26 19:18:03.000000000 +0000 ++++ linux-3.2.46/drivers/staging/hv/storvsc_drv.c 2013-07-26 19:18:04.000000000 +0000 +@@ -969,8 +969,7 @@ { struct storvsc_device *stor_device = hv_get_drvdata(dev); struct Scsi_Host *host = stor_device->host; @@ -28,7 +28,7 @@ scsi_remove_host(host); -@@ -1057,8 +1056,7 @@ static int storvsc_host_reset(struct hv_device *device) +@@ -1063,8 +1062,7 @@ */ static int storvsc_host_reset_handler(struct scsi_cmnd *scmnd) { @@ -38,7 +38,7 @@ struct hv_device *dev = host_dev->dev; return storvsc_host_reset(dev); -@@ -1073,8 +1071,7 @@ static void storvsc_command_completion(struct hv_storvsc_request *request) +@@ -1079,8 +1077,7 @@ struct storvsc_cmd_request *cmd_request = (struct storvsc_cmd_request *)request->context; struct scsi_cmnd *scmnd = cmd_request->cmd; @@ -48,7 +48,7 @@ void (*scsi_done_fn)(struct scsi_cmnd *); struct scsi_sense_hdr sense_hdr; struct vmscsi_request *vm_srb; -@@ -1144,8 +1141,7 @@ static int storvsc_queuecommand_lck(struct scsi_cmnd *scmnd, +@@ -1150,8 +1147,7 @@ void (*done)(struct scsi_cmnd *)) { int ret; @@ -58,7 +58,7 @@ struct hv_device *dev = host_dev->dev; struct hv_storvsc_request *request; struct storvsc_cmd_request *cmd_request; -@@ -1359,7 +1355,7 @@ static int storvsc_probe(struct hv_device *device, +@@ -1365,7 +1361,7 @@ if (!host) return -ENOMEM; @@ -67,6 +67,3 @@ memset(host_dev, 0, sizeof(struct hv_host_device)); host_dev->port = host->host_no; --- -1.7.9.5 - diff -Nru linux-3.2.46/debian/patches/features/x86/hyperv/0008-Staging-hv-storvsc-Use-the-unlocked-version-queuecom.patch linux-3.2.46/debian/patches/features/x86/hyperv/0008-Staging-hv-storvsc-Use-the-unlocked-version-queuecom.patch --- linux-3.2.46/debian/patches/features/x86/hyperv/0008-Staging-hv-storvsc-Use-the-unlocked-version-queuecom.patch 2013-02-24 03:52:26.000000000 +0000 +++ linux-3.2.46/debian/patches/features/x86/hyperv/0008-Staging-hv-storvsc-Use-the-unlocked-version-queuecom.patch 2013-07-26 19:18:06.000000000 +0000 @@ -14,11 +14,11 @@ drivers/staging/hv/storvsc_drv.c | 19 +++++-------------- 1 file changed, 5 insertions(+), 14 deletions(-) -diff --git a/drivers/staging/hv/storvsc_drv.c b/drivers/staging/hv/storvsc_drv.c -index b21e85f..827bc68 100644 ---- a/drivers/staging/hv/storvsc_drv.c -+++ b/drivers/staging/hv/storvsc_drv.c -@@ -1137,11 +1137,10 @@ static bool storvsc_check_scsi_cmd(struct scsi_cmnd *scmnd) +Index: linux-3.2.46/drivers/staging/hv/storvsc_drv.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/hv/storvsc_drv.c 2013-07-26 19:18:04.000000000 +0000 ++++ linux-3.2.46/drivers/staging/hv/storvsc_drv.c 2013-07-26 19:18:05.000000000 +0000 +@@ -1143,11 +1143,10 @@ /* * storvsc_queuecommand - Initiate command processing */ @@ -32,7 +32,7 @@ struct hv_device *dev = host_dev->dev; struct hv_storvsc_request *request; struct storvsc_cmd_request *cmd_request; -@@ -1152,7 +1151,7 @@ static int storvsc_queuecommand_lck(struct scsi_cmnd *scmnd, +@@ -1158,7 +1157,7 @@ struct vmscsi_request *vm_srb; if (storvsc_check_scsi_cmd(scmnd) == false) { @@ -41,7 +41,7 @@ return 0; } -@@ -1165,16 +1164,13 @@ static int storvsc_queuecommand_lck(struct scsi_cmnd *scmnd, +@@ -1171,16 +1170,13 @@ goto retry_request; } @@ -60,7 +60,7 @@ memset(cmd_request, 0, sizeof(struct storvsc_cmd_request)); /* Setup the cmd request */ -@@ -1227,7 +1223,6 @@ static int storvsc_queuecommand_lck(struct scsi_cmnd *scmnd, +@@ -1233,7 +1229,6 @@ create_bounce_buffer(sgl, scsi_sg_count(scmnd), scsi_bufflen(scmnd)); if (!cmd_request->bounce_sgl) { @@ -68,7 +68,7 @@ scmnd->host_scribble = NULL; mempool_free(cmd_request, host_dev->request_mempool); -@@ -1274,7 +1269,6 @@ retry_request: +@@ -1280,7 +1275,6 @@ mempool_free(cmd_request, host_dev->request_mempool); @@ -76,7 +76,7 @@ scmnd->host_scribble = NULL; ret = SCSI_MLQUEUE_DEVICE_BUSY; -@@ -1283,9 +1277,6 @@ retry_request: +@@ -1289,9 +1283,6 @@ return ret; } @@ -86,6 +86,3 @@ /* Scsi driver */ static struct scsi_host_template scsi_driver = { .module = THIS_MODULE, --- -1.7.9.5 - diff -Nru linux-3.2.46/debian/patches/features/x86/hyperv/0009-Staging-hv-storvsc-use-the-macro-KBUILD_MODNAME.patch linux-3.2.46/debian/patches/features/x86/hyperv/0009-Staging-hv-storvsc-use-the-macro-KBUILD_MODNAME.patch --- linux-3.2.46/debian/patches/features/x86/hyperv/0009-Staging-hv-storvsc-use-the-macro-KBUILD_MODNAME.patch 2013-02-24 03:52:26.000000000 +0000 +++ linux-3.2.46/debian/patches/features/x86/hyperv/0009-Staging-hv-storvsc-use-the-macro-KBUILD_MODNAME.patch 2013-07-26 19:18:07.000000000 +0000 @@ -13,11 +13,11 @@ drivers/staging/hv/storvsc_drv.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -diff --git a/drivers/staging/hv/storvsc_drv.c b/drivers/staging/hv/storvsc_drv.c -index 827bc68..916f5d0 100644 ---- a/drivers/staging/hv/storvsc_drv.c -+++ b/drivers/staging/hv/storvsc_drv.c -@@ -1444,7 +1444,7 @@ err_out0: +Index: linux-3.2.46/drivers/staging/hv/storvsc_drv.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/hv/storvsc_drv.c 2013-07-26 19:18:05.000000000 +0000 ++++ linux-3.2.46/drivers/staging/hv/storvsc_drv.c 2013-07-26 19:18:06.000000000 +0000 +@@ -1450,7 +1450,7 @@ /* The one and only one */ static struct hv_driver storvsc_drv = { @@ -26,6 +26,3 @@ .id_table = id_table, .probe = storvsc_probe, .remove = storvsc_remove, --- -1.7.9.5 - diff -Nru linux-3.2.46/debian/patches/features/x86/hyperv/0010-Staging-hv-storvsc-Get-rid-of-an-unnecessary-forward.patch linux-3.2.46/debian/patches/features/x86/hyperv/0010-Staging-hv-storvsc-Get-rid-of-an-unnecessary-forward.patch --- linux-3.2.46/debian/patches/features/x86/hyperv/0010-Staging-hv-storvsc-Get-rid-of-an-unnecessary-forward.patch 2013-02-24 03:52:26.000000000 +0000 +++ linux-3.2.46/debian/patches/features/x86/hyperv/0010-Staging-hv-storvsc-Get-rid-of-an-unnecessary-forward.patch 2013-07-26 19:18:08.000000000 +0000 @@ -14,11 +14,11 @@ drivers/staging/hv/storvsc_drv.c | 2 -- 1 file changed, 2 deletions(-) -diff --git a/drivers/staging/hv/storvsc_drv.c b/drivers/staging/hv/storvsc_drv.c -index 916f5d0..4cdb417 100644 ---- a/drivers/staging/hv/storvsc_drv.c -+++ b/drivers/staging/hv/storvsc_drv.c -@@ -236,8 +236,6 @@ struct vstor_packet { +Index: linux-3.2.46/drivers/staging/hv/storvsc_drv.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/hv/storvsc_drv.c 2013-07-26 19:18:06.000000000 +0000 ++++ linux-3.2.46/drivers/staging/hv/storvsc_drv.c 2013-07-26 19:18:08.000000000 +0000 +@@ -236,8 +236,6 @@ #define STORVSC_MAX_CHANNELS 1 #define STORVSC_MAX_CMD_LEN 16 @@ -27,6 +27,3 @@ /* Matches Windows-end */ enum storvsc_request_type { WRITE_TYPE, --- -1.7.9.5 - diff -Nru linux-3.2.46/debian/patches/features/x86/hyperv/0011-Staging-hv-storvsc-Upgrade-the-vmstor-protocol-versi.patch linux-3.2.46/debian/patches/features/x86/hyperv/0011-Staging-hv-storvsc-Upgrade-the-vmstor-protocol-versi.patch --- linux-3.2.46/debian/patches/features/x86/hyperv/0011-Staging-hv-storvsc-Upgrade-the-vmstor-protocol-versi.patch 2013-02-24 03:52:26.000000000 +0000 +++ linux-3.2.46/debian/patches/features/x86/hyperv/0011-Staging-hv-storvsc-Upgrade-the-vmstor-protocol-versi.patch 2013-07-26 19:18:10.000000000 +0000 @@ -15,11 +15,11 @@ drivers/staging/hv/storvsc_drv.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) -diff --git a/drivers/staging/hv/storvsc_drv.c b/drivers/staging/hv/storvsc_drv.c -index 4cdb417..9153641 100644 ---- a/drivers/staging/hv/storvsc_drv.c -+++ b/drivers/staging/hv/storvsc_drv.c -@@ -80,7 +80,7 @@ MODULE_PARM_DESC(storvsc_ringbuffer_size, "Ring buffer size (bytes)"); +Index: linux-3.2.46/drivers/staging/hv/storvsc_drv.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/hv/storvsc_drv.c 2013-07-26 19:18:08.000000000 +0000 ++++ linux-3.2.46/drivers/staging/hv/storvsc_drv.c 2013-07-26 19:18:09.000000000 +0000 +@@ -80,7 +80,7 @@ /* V1 Beta 0.1 */ /* V1 RC < 2008/1/31 1.0 */ /* V1 RC > 2008/1/31 2.0 */ @@ -28,7 +28,7 @@ -@@ -106,7 +106,8 @@ enum vstor_packet_operation { +@@ -106,7 +106,8 @@ VSTOR_OPERATION_END_INITIALIZATION = 8, VSTOR_OPERATION_QUERY_PROTOCOL_VERSION = 9, VSTOR_OPERATION_QUERY_PROPERTIES = 10, @@ -38,6 +38,3 @@ }; /* --- -1.7.9.5 - diff -Nru linux-3.2.46/debian/patches/features/x86/hyperv/0012-Staging-hv-storvsc-Support-hot-add-of-scsi-disks.patch linux-3.2.46/debian/patches/features/x86/hyperv/0012-Staging-hv-storvsc-Support-hot-add-of-scsi-disks.patch --- linux-3.2.46/debian/patches/features/x86/hyperv/0012-Staging-hv-storvsc-Support-hot-add-of-scsi-disks.patch 2013-02-24 03:52:26.000000000 +0000 +++ linux-3.2.46/debian/patches/features/x86/hyperv/0012-Staging-hv-storvsc-Support-hot-add-of-scsi-disks.patch 2013-07-26 19:18:11.000000000 +0000 @@ -13,11 +13,11 @@ drivers/staging/hv/storvsc_drv.c | 38 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) -diff --git a/drivers/staging/hv/storvsc_drv.c b/drivers/staging/hv/storvsc_drv.c -index 9153641..7c82d14 100644 ---- a/drivers/staging/hv/storvsc_drv.c -+++ b/drivers/staging/hv/storvsc_drv.c -@@ -304,6 +304,30 @@ struct storvsc_cmd_request { +Index: linux-3.2.46/drivers/staging/hv/storvsc_drv.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/hv/storvsc_drv.c 2013-07-26 19:18:09.000000000 +0000 ++++ linux-3.2.46/drivers/staging/hv/storvsc_drv.c 2013-07-26 19:18:10.000000000 +0000 +@@ -304,6 +304,30 @@ struct hv_storvsc_request request; }; @@ -48,7 +48,7 @@ static inline struct storvsc_device *get_out_stor_device( struct hv_device *device) { -@@ -551,11 +575,25 @@ static void storvsc_on_receive(struct hv_device *device, +@@ -551,11 +575,25 @@ struct vstor_packet *vstor_packet, struct hv_storvsc_request *request) { @@ -74,6 +74,3 @@ default: break; --- -1.7.9.5 - diff -Nru linux-3.2.46/debian/patches/features/x86/hyperv/0013-Staging-hv-storvsc-Support-hot-removing-of-scsi-devi.patch linux-3.2.46/debian/patches/features/x86/hyperv/0013-Staging-hv-storvsc-Support-hot-removing-of-scsi-devi.patch --- linux-3.2.46/debian/patches/features/x86/hyperv/0013-Staging-hv-storvsc-Support-hot-removing-of-scsi-devi.patch 2013-02-24 03:52:26.000000000 +0000 +++ linux-3.2.46/debian/patches/features/x86/hyperv/0013-Staging-hv-storvsc-Support-hot-removing-of-scsi-devi.patch 2013-07-26 19:18:12.000000000 +0000 @@ -14,11 +14,11 @@ drivers/staging/hv/storvsc_drv.c | 45 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) -diff --git a/drivers/staging/hv/storvsc_drv.c b/drivers/staging/hv/storvsc_drv.c -index 7c82d14..0245143 100644 ---- a/drivers/staging/hv/storvsc_drv.c -+++ b/drivers/staging/hv/storvsc_drv.c -@@ -328,6 +328,27 @@ static void storvsc_bus_scan(struct work_struct *work) +Index: linux-3.2.46/drivers/staging/hv/storvsc_drv.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/hv/storvsc_drv.c 2013-07-26 19:18:10.000000000 +0000 ++++ linux-3.2.46/drivers/staging/hv/storvsc_drv.c 2013-07-26 19:18:11.000000000 +0000 +@@ -328,6 +328,27 @@ kfree(wrk); } @@ -46,7 +46,7 @@ static inline struct storvsc_device *get_out_stor_device( struct hv_device *device) { -@@ -1112,6 +1133,7 @@ static void storvsc_command_completion(struct hv_storvsc_request *request) +@@ -1118,6 +1139,7 @@ void (*scsi_done_fn)(struct scsi_cmnd *); struct scsi_sense_hdr sense_hdr; struct vmscsi_request *vm_srb; @@ -54,7 +54,7 @@ vm_srb = &request->vstor_packet.vm_srb; if (cmd_request->bounce_sgl_count) { -@@ -1134,6 +1156,29 @@ static void storvsc_command_completion(struct hv_storvsc_request *request) +@@ -1140,6 +1162,29 @@ else scmnd->result = vm_srb->scsi_status; @@ -84,6 +84,3 @@ if (scmnd->result) { if (scsi_normalize_sense(scmnd->sense_buffer, SCSI_SENSE_BUFFERSIZE, &sense_hdr)) --- -1.7.9.5 - diff -Nru linux-3.2.46/debian/patches/features/x86/hyperv/0014-staging-hv-Use-kmemdup-rather-than-duplicating-its-i.patch linux-3.2.46/debian/patches/features/x86/hyperv/0014-staging-hv-Use-kmemdup-rather-than-duplicating-its-i.patch --- linux-3.2.46/debian/patches/features/x86/hyperv/0014-staging-hv-Use-kmemdup-rather-than-duplicating-its-i.patch 2013-02-24 03:52:26.000000000 +0000 +++ linux-3.2.46/debian/patches/features/x86/hyperv/0014-staging-hv-Use-kmemdup-rather-than-duplicating-its-i.patch 2013-07-26 19:18:14.000000000 +0000 @@ -17,11 +17,11 @@ drivers/staging/hv/netvsc.c | 11 +++-------- 2 files changed, 4 insertions(+), 11 deletions(-) -diff --git a/drivers/staging/hv/hv_mouse.c b/drivers/staging/hv/hv_mouse.c -index ccd39c7..3689217 100644 ---- a/drivers/staging/hv/hv_mouse.c -+++ b/drivers/staging/hv/hv_mouse.c -@@ -205,13 +205,11 @@ static void mousevsc_on_receive_device_info(struct mousevsc_dev *input_device, +Index: linux-3.2.46/drivers/staging/hv/hv_mouse.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/hv/hv_mouse.c 2013-07-26 18:56:16.000000000 +0000 ++++ linux-3.2.46/drivers/staging/hv/hv_mouse.c 2013-07-26 19:18:13.000000000 +0000 +@@ -205,13 +205,11 @@ desc = &device_info->hid_descriptor; WARN_ON(desc->bLength == 0); @@ -36,11 +36,11 @@ input_device->report_desc_size = desc->desc[0].wDescriptorLength; if (input_device->report_desc_size == 0) goto cleanup; -diff --git a/drivers/staging/hv/netvsc.c b/drivers/staging/hv/netvsc.c -index b902579..28e69a6 100644 ---- a/drivers/staging/hv/netvsc.c -+++ b/drivers/staging/hv/netvsc.c -@@ -230,19 +230,14 @@ static int netvsc_init_recv_buf(struct hv_device *device) +Index: linux-3.2.46/drivers/staging/hv/netvsc.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/hv/netvsc.c 2013-07-26 18:56:16.000000000 +0000 ++++ linux-3.2.46/drivers/staging/hv/netvsc.c 2013-07-26 19:18:13.000000000 +0000 +@@ -230,19 +230,14 @@ net_device->recv_section_cnt = init_packet->msg. v1_msg.send_recv_buf_complete.num_sections; @@ -63,6 +63,3 @@ /* * For 1st release, there should only be 1 section that represents the * entire receive buffer --- -1.7.9.5 - diff -Nru linux-3.2.46/debian/patches/features/x86/hyperv/0015-Staging-hv-vmbus-Support-building-the-vmbus-driver-a.patch linux-3.2.46/debian/patches/features/x86/hyperv/0015-Staging-hv-vmbus-Support-building-the-vmbus-driver-a.patch --- linux-3.2.46/debian/patches/features/x86/hyperv/0015-Staging-hv-vmbus-Support-building-the-vmbus-driver-a.patch 2013-02-24 03:52:26.000000000 +0000 +++ linux-3.2.46/debian/patches/features/x86/hyperv/0015-Staging-hv-vmbus-Support-building-the-vmbus-driver-a.patch 2013-07-26 19:18:15.000000000 +0000 @@ -17,16 +17,13 @@ drivers/hv/vmbus_drv.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -diff --git a/drivers/hv/vmbus_drv.c b/drivers/hv/vmbus_drv.c -index d2d0a2a..05168eb 100644 ---- a/drivers/hv/vmbus_drv.c -+++ b/drivers/hv/vmbus_drv.c -@@ -796,4 +796,4 @@ cleanup: +Index: linux-3.2.46/drivers/hv/vmbus_drv.c +=================================================================== +--- linux-3.2.46.orig/drivers/hv/vmbus_drv.c 2013-07-26 18:56:16.000000000 +0000 ++++ linux-3.2.46/drivers/hv/vmbus_drv.c 2013-07-26 19:18:14.000000000 +0000 +@@ -796,4 +796,4 @@ MODULE_LICENSE("GPL"); MODULE_VERSION(HV_DRV_VERSION); -module_init(hv_acpi_init); +subsys_initcall(hv_acpi_init); --- -1.7.9.5 - diff -Nru linux-3.2.46/debian/patches/features/x86/hyperv/0016-hv-Add-Kconfig-menu-entry.patch linux-3.2.46/debian/patches/features/x86/hyperv/0016-hv-Add-Kconfig-menu-entry.patch --- linux-3.2.46/debian/patches/features/x86/hyperv/0016-hv-Add-Kconfig-menu-entry.patch 2013-02-24 03:52:26.000000000 +0000 +++ linux-3.2.46/debian/patches/features/x86/hyperv/0016-hv-Add-Kconfig-menu-entry.patch 2013-07-26 19:18:16.000000000 +0000 @@ -17,22 +17,19 @@ drivers/hv/Kconfig | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) -diff --git a/drivers/hv/Kconfig b/drivers/hv/Kconfig -index 9fa09ac..70f5dde 100644 ---- a/drivers/hv/Kconfig -+++ b/drivers/hv/Kconfig +Index: linux-3.2.46/drivers/hv/Kconfig +=================================================================== +--- linux-3.2.46.orig/drivers/hv/Kconfig 2013-07-26 18:56:15.000000000 +0000 ++++ linux-3.2.46/drivers/hv/Kconfig 2013-07-26 19:18:15.000000000 +0000 @@ -1,3 +1,5 @@ +menu "Microsoft Hyper-V guest support" + config HYPERV tristate "Microsoft Hyper-V client drivers" depends on X86 && ACPI && PCI -@@ -11,4 +13,4 @@ config HYPERV_UTILS +@@ -11,4 +13,4 @@ help Select this option to enable the Hyper-V Utilities. - +endmenu --- -1.7.9.5 - diff -Nru linux-3.2.46/debian/patches/features/x86/hyperv/0017-Staging-hv-mousevsc-Remove-the-mouse-driver-from-the.patch linux-3.2.46/debian/patches/features/x86/hyperv/0017-Staging-hv-mousevsc-Remove-the-mouse-driver-from-the.patch --- linux-3.2.46/debian/patches/features/x86/hyperv/0017-Staging-hv-mousevsc-Remove-the-mouse-driver-from-the.patch 2013-02-24 03:52:26.000000000 +0000 +++ linux-3.2.46/debian/patches/features/x86/hyperv/0017-Staging-hv-mousevsc-Remove-the-mouse-driver-from-the.patch 2013-07-26 19:18:17.000000000 +0000 @@ -23,11 +23,11 @@ 3 files changed, 604 deletions(-) delete mode 100644 drivers/staging/hv/hv_mouse.c -diff --git a/drivers/staging/hv/Kconfig b/drivers/staging/hv/Kconfig -index 072185e..6c0dc30 100644 ---- a/drivers/staging/hv/Kconfig -+++ b/drivers/staging/hv/Kconfig -@@ -9,9 +9,3 @@ config HYPERV_NET +Index: linux-3.2.46/drivers/staging/hv/Kconfig +=================================================================== +--- linux-3.2.46.orig/drivers/staging/hv/Kconfig 2013-07-26 18:56:15.000000000 +0000 ++++ linux-3.2.46/drivers/staging/hv/Kconfig 2013-07-26 19:18:16.000000000 +0000 +@@ -9,9 +9,3 @@ depends on HYPERV && NET help Select this option to enable the Hyper-V virtual network driver. @@ -37,10 +37,10 @@ - depends on HYPERV && HID - help - Select this option to enable the Hyper-V mouse driver. -diff --git a/drivers/staging/hv/Makefile b/drivers/staging/hv/Makefile -index 0f55cee..fbe9a42 100644 ---- a/drivers/staging/hv/Makefile -+++ b/drivers/staging/hv/Makefile +Index: linux-3.2.46/drivers/staging/hv/Makefile +=================================================================== +--- linux-3.2.46.orig/drivers/staging/hv/Makefile 2013-07-26 18:56:15.000000000 +0000 ++++ linux-3.2.46/drivers/staging/hv/Makefile 2013-07-26 19:18:16.000000000 +0000 @@ -1,6 +1,5 @@ obj-$(CONFIG_HYPERV_STORAGE) += hv_storvsc.o obj-$(CONFIG_HYPERV_NET) += hv_netvsc.o @@ -48,11 +48,10 @@ hv_storvsc-y := storvsc_drv.o hv_netvsc-y := netvsc_drv.o netvsc.o rndis_filter.o -diff --git a/drivers/staging/hv/hv_mouse.c b/drivers/staging/hv/hv_mouse.c -deleted file mode 100644 -index 3689217..0000000 ---- a/drivers/staging/hv/hv_mouse.c -+++ /dev/null +Index: linux-3.2.46/drivers/staging/hv/hv_mouse.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/hv/hv_mouse.c 2013-07-26 19:18:13.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 @@ -1,597 +0,0 @@ -/* - * Copyright (c) 2009, Citrix Systems, Inc. @@ -651,6 +650,3 @@ -MODULE_VERSION(HV_DRV_VERSION); -module_init(mousevsc_init); -module_exit(mousevsc_exit); --- -1.7.9.5 - diff -Nru linux-3.2.46/debian/patches/features/x86/hyperv/0018-staging-hv-move-hv_netvsc-out-of-staging-area.patch linux-3.2.46/debian/patches/features/x86/hyperv/0018-staging-hv-move-hv_netvsc-out-of-staging-area.patch --- linux-3.2.46/debian/patches/features/x86/hyperv/0018-staging-hv-move-hv_netvsc-out-of-staging-area.patch 2013-02-24 03:52:26.000000000 +0000 +++ linux-3.2.46/debian/patches/features/x86/hyperv/0018-staging-hv-move-hv_netvsc-out-of-staging-area.patch 2013-07-26 19:18:20.000000000 +0000 @@ -45,52 +45,49 @@ delete mode 100644 drivers/staging/hv/netvsc_drv.c delete mode 100644 drivers/staging/hv/rndis_filter.c -diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig -index 654a5e9..99aa7fa 100644 ---- a/drivers/net/Kconfig -+++ b/drivers/net/Kconfig -@@ -338,4 +338,6 @@ config VMXNET3 +Index: linux-3.2.46/drivers/net/Kconfig +=================================================================== +--- linux-3.2.46.orig/drivers/net/Kconfig 2013-07-26 18:56:14.000000000 +0000 ++++ linux-3.2.46/drivers/net/Kconfig 2013-07-26 19:18:18.000000000 +0000 +@@ -338,4 +338,6 @@ To compile this driver as a module, choose M here: the module will be called vmxnet3. +source "drivers/net/hyperv/Kconfig" + endif # NETDEVICES -diff --git a/drivers/net/Makefile b/drivers/net/Makefile -index fa877cd..a81192b 100644 ---- a/drivers/net/Makefile -+++ b/drivers/net/Makefile -@@ -66,3 +66,5 @@ obj-$(CONFIG_USB_USBNET) += usb/ +Index: linux-3.2.46/drivers/net/Makefile +=================================================================== +--- linux-3.2.46.orig/drivers/net/Makefile 2013-07-26 18:56:14.000000000 +0000 ++++ linux-3.2.46/drivers/net/Makefile 2013-07-26 19:18:18.000000000 +0000 +@@ -66,3 +66,5 @@ obj-$(CONFIG_USB_ZD1201) += usb/ obj-$(CONFIG_USB_IPHETH) += usb/ obj-$(CONFIG_USB_CDC_PHONET) += usb/ + +obj-$(CONFIG_HYPERV_NET) += hyperv/ -diff --git a/drivers/net/hyperv/Kconfig b/drivers/net/hyperv/Kconfig -new file mode 100644 -index 0000000..936968d ---- /dev/null -+++ b/drivers/net/hyperv/Kconfig +Index: linux-3.2.46/drivers/net/hyperv/Kconfig +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/hyperv/Kconfig 2013-07-26 19:18:18.000000000 +0000 @@ -0,0 +1,5 @@ +config HYPERV_NET + tristate "Microsoft Hyper-V virtual network driver" + depends on HYPERV + help + Select this option to enable the Hyper-V virtual network driver. -diff --git a/drivers/net/hyperv/Makefile b/drivers/net/hyperv/Makefile -new file mode 100644 -index 0000000..c8a6682 ---- /dev/null -+++ b/drivers/net/hyperv/Makefile +Index: linux-3.2.46/drivers/net/hyperv/Makefile +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/hyperv/Makefile 2013-07-26 19:18:18.000000000 +0000 @@ -0,0 +1,3 @@ +obj-$(CONFIG_HYPERV_NET) += hv_netvsc.o + +hv_netvsc-y := netvsc_drv.o netvsc.o rndis_filter.o -diff --git a/drivers/net/hyperv/hyperv_net.h b/drivers/net/hyperv/hyperv_net.h -new file mode 100644 -index 0000000..ac1ec84 ---- /dev/null -+++ b/drivers/net/hyperv/hyperv_net.h +Index: linux-3.2.46/drivers/net/hyperv/hyperv_net.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/hyperv/hyperv_net.h 2013-07-26 19:18:18.000000000 +0000 @@ -0,0 +1,1058 @@ +/* + * @@ -1150,11 +1147,10 @@ + + +#endif /* _HYPERV_NET_H */ -diff --git a/drivers/net/hyperv/netvsc.c b/drivers/net/hyperv/netvsc.c -new file mode 100644 -index 0000000..28e69a6 ---- /dev/null -+++ b/drivers/net/hyperv/netvsc.c +Index: linux-3.2.46/drivers/net/hyperv/netvsc.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/hyperv/netvsc.c 2013-07-26 19:18:18.000000000 +0000 @@ -0,0 +1,939 @@ +/* + * Copyright (c) 2009, Microsoft Corporation. @@ -2095,11 +2091,10 @@ + + return ret; +} -diff --git a/drivers/net/hyperv/netvsc_drv.c b/drivers/net/hyperv/netvsc_drv.c -new file mode 100644 -index 0000000..93b0e91 ---- /dev/null -+++ b/drivers/net/hyperv/netvsc_drv.c +Index: linux-3.2.46/drivers/net/hyperv/netvsc_drv.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/hyperv/netvsc_drv.c 2013-07-26 19:18:18.000000000 +0000 @@ -0,0 +1,456 @@ +/* + * Copyright (c) 2009, Microsoft Corporation. @@ -2557,11 +2552,10 @@ + +module_init(netvsc_drv_init); +module_exit(netvsc_drv_exit); -diff --git a/drivers/net/hyperv/rndis_filter.c b/drivers/net/hyperv/rndis_filter.c -new file mode 100644 -index 0000000..bafccb3 ---- /dev/null -+++ b/drivers/net/hyperv/rndis_filter.c +Index: linux-3.2.46/drivers/net/hyperv/rndis_filter.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/hyperv/rndis_filter.c 2013-07-26 19:18:18.000000000 +0000 @@ -0,0 +1,855 @@ +/* + * Copyright (c) 2009, Microsoft Corporation. @@ -3418,11 +3412,11 @@ +{ + /* Noop */ +} -diff --git a/drivers/staging/hv/Kconfig b/drivers/staging/hv/Kconfig -index 6c0dc30..60ac479 100644 ---- a/drivers/staging/hv/Kconfig -+++ b/drivers/staging/hv/Kconfig -@@ -3,9 +3,3 @@ config HYPERV_STORAGE +Index: linux-3.2.46/drivers/staging/hv/Kconfig +=================================================================== +--- linux-3.2.46.orig/drivers/staging/hv/Kconfig 2013-07-26 19:18:16.000000000 +0000 ++++ linux-3.2.46/drivers/staging/hv/Kconfig 2013-07-26 19:18:18.000000000 +0000 +@@ -3,9 +3,3 @@ depends on HYPERV && SCSI help Select this option to enable the Hyper-V virtual storage driver. @@ -3432,31 +3426,30 @@ - depends on HYPERV && NET - help - Select this option to enable the Hyper-V virtual network driver. -diff --git a/drivers/staging/hv/Makefile b/drivers/staging/hv/Makefile -index fbe9a42..af95a6b 100644 ---- a/drivers/staging/hv/Makefile -+++ b/drivers/staging/hv/Makefile +Index: linux-3.2.46/drivers/staging/hv/Makefile +=================================================================== +--- linux-3.2.46.orig/drivers/staging/hv/Makefile 2013-07-26 19:18:16.000000000 +0000 ++++ linux-3.2.46/drivers/staging/hv/Makefile 2013-07-26 19:18:18.000000000 +0000 @@ -1,5 +1,3 @@ obj-$(CONFIG_HYPERV_STORAGE) += hv_storvsc.o -obj-$(CONFIG_HYPERV_NET) += hv_netvsc.o hv_storvsc-y := storvsc_drv.o -hv_netvsc-y := netvsc_drv.o netvsc.o rndis_filter.o -diff --git a/drivers/staging/hv/TODO b/drivers/staging/hv/TODO -index ed4d636..fd080cb 100644 ---- a/drivers/staging/hv/TODO -+++ b/drivers/staging/hv/TODO +Index: linux-3.2.46/drivers/staging/hv/TODO +=================================================================== +--- linux-3.2.46.orig/drivers/staging/hv/TODO 2013-07-26 18:56:14.000000000 +0000 ++++ linux-3.2.46/drivers/staging/hv/TODO 2013-07-26 19:18:18.000000000 +0000 @@ -1,5 +1,4 @@ TODO: - - audit the network driver - audit the scsi driver Please send patches for this code to Greg Kroah-Hartman , -diff --git a/drivers/staging/hv/hyperv_net.h b/drivers/staging/hv/hyperv_net.h -deleted file mode 100644 -index ac1ec84..0000000 ---- a/drivers/staging/hv/hyperv_net.h -+++ /dev/null +Index: linux-3.2.46/drivers/staging/hv/hyperv_net.h +=================================================================== +--- linux-3.2.46.orig/drivers/staging/hv/hyperv_net.h 2013-07-26 18:56:14.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 @@ -1,1058 +0,0 @@ -/* - * @@ -4516,11 +4509,10 @@ - - -#endif /* _HYPERV_NET_H */ -diff --git a/drivers/staging/hv/netvsc.c b/drivers/staging/hv/netvsc.c -deleted file mode 100644 -index 28e69a6..0000000 ---- a/drivers/staging/hv/netvsc.c -+++ /dev/null +Index: linux-3.2.46/drivers/staging/hv/netvsc.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/hv/netvsc.c 2013-07-26 19:18:13.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 @@ -1,939 +0,0 @@ -/* - * Copyright (c) 2009, Microsoft Corporation. @@ -5461,11 +5453,10 @@ - - return ret; -} -diff --git a/drivers/staging/hv/netvsc_drv.c b/drivers/staging/hv/netvsc_drv.c -deleted file mode 100644 -index 93b0e91..0000000 ---- a/drivers/staging/hv/netvsc_drv.c -+++ /dev/null +Index: linux-3.2.46/drivers/staging/hv/netvsc_drv.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/hv/netvsc_drv.c 2013-07-26 18:56:14.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 @@ -1,456 +0,0 @@ -/* - * Copyright (c) 2009, Microsoft Corporation. @@ -5923,11 +5914,10 @@ - -module_init(netvsc_drv_init); -module_exit(netvsc_drv_exit); -diff --git a/drivers/staging/hv/rndis_filter.c b/drivers/staging/hv/rndis_filter.c -deleted file mode 100644 -index bafccb3..0000000 ---- a/drivers/staging/hv/rndis_filter.c -+++ /dev/null +Index: linux-3.2.46/drivers/staging/hv/rndis_filter.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/hv/rndis_filter.c 2013-07-26 18:56:14.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 @@ -1,855 +0,0 @@ -/* - * Copyright (c) 2009, Microsoft Corporation. @@ -6784,6 +6774,3 @@ -{ - /* Noop */ -} --- -1.7.9.5 - diff -Nru linux-3.2.46/debian/patches/features/x86/hyperv/0019-net-hyperv-Fix-long-lines-in-netvsc.c.patch linux-3.2.46/debian/patches/features/x86/hyperv/0019-net-hyperv-Fix-long-lines-in-netvsc.c.patch --- linux-3.2.46/debian/patches/features/x86/hyperv/0019-net-hyperv-Fix-long-lines-in-netvsc.c.patch 2013-02-24 03:52:26.000000000 +0000 +++ linux-3.2.46/debian/patches/features/x86/hyperv/0019-net-hyperv-Fix-long-lines-in-netvsc.c.patch 2013-07-26 19:18:21.000000000 +0000 @@ -11,11 +11,11 @@ drivers/net/hyperv/netvsc.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) -diff --git a/drivers/net/hyperv/netvsc.c b/drivers/net/hyperv/netvsc.c -index 28e69a6..4a807e4 100644 ---- a/drivers/net/hyperv/netvsc.c -+++ b/drivers/net/hyperv/netvsc.c -@@ -230,9 +230,11 @@ static int netvsc_init_recv_buf(struct hv_device *device) +Index: linux-3.2.46/drivers/net/hyperv/netvsc.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/hyperv/netvsc.c 2013-07-26 19:18:18.000000000 +0000 ++++ linux-3.2.46/drivers/net/hyperv/netvsc.c 2013-07-26 19:18:20.000000000 +0000 +@@ -230,9 +230,11 @@ net_device->recv_section_cnt = init_packet->msg. v1_msg.send_recv_buf_complete.num_sections; @@ -30,6 +30,3 @@ if (net_device->recv_section == NULL) { ret = -EINVAL; goto cleanup; --- -1.7.9.5 - diff -Nru linux-3.2.46/debian/patches/features/x86/hyperv/0020-net-hyperv-Add-support-for-promiscuous-mode-setting.patch linux-3.2.46/debian/patches/features/x86/hyperv/0020-net-hyperv-Add-support-for-promiscuous-mode-setting.patch --- linux-3.2.46/debian/patches/features/x86/hyperv/0020-net-hyperv-Add-support-for-promiscuous-mode-setting.patch 2013-02-24 03:52:26.000000000 +0000 +++ linux-3.2.46/debian/patches/features/x86/hyperv/0020-net-hyperv-Add-support-for-promiscuous-mode-setting.patch 2013-07-26 19:18:22.000000000 +0000 @@ -16,11 +16,11 @@ drivers/net/hyperv/rndis_filter.c | 23 +------------------ 3 files changed, 68 insertions(+), 25 deletions(-) -diff --git a/drivers/net/hyperv/hyperv_net.h b/drivers/net/hyperv/hyperv_net.h -index ac1ec84..49b131f 100644 ---- a/drivers/net/hyperv/hyperv_net.h -+++ b/drivers/net/hyperv/hyperv_net.h -@@ -87,6 +87,27 @@ struct netvsc_device_info { +Index: linux-3.2.46/drivers/net/hyperv/hyperv_net.h +=================================================================== +--- linux-3.2.46.orig/drivers/net/hyperv/hyperv_net.h 2013-07-26 19:18:18.000000000 +0000 ++++ linux-3.2.46/drivers/net/hyperv/hyperv_net.h 2013-07-26 19:18:21.000000000 +0000 +@@ -87,6 +87,27 @@ int ring_size; }; @@ -48,7 +48,7 @@ /* Interface */ int netvsc_device_add(struct hv_device *device, void *additional_info); int netvsc_device_remove(struct hv_device *device); -@@ -109,6 +130,9 @@ int rndis_filter_receive(struct hv_device *dev, +@@ -109,6 +130,9 @@ int rndis_filter_send(struct hv_device *dev, struct hv_netvsc_packet *pkt); @@ -58,11 +58,11 @@ #define NVSP_INVALID_PROTOCOL_VERSION ((u32)0xFFFFFFFF) #define NVSP_PROTOCOL_VERSION_1 2 -diff --git a/drivers/net/hyperv/netvsc_drv.c b/drivers/net/hyperv/netvsc_drv.c -index 93b0e91..b69c3a4 100644 ---- a/drivers/net/hyperv/netvsc_drv.c -+++ b/drivers/net/hyperv/netvsc_drv.c -@@ -56,11 +56,51 @@ static int ring_size = 128; +Index: linux-3.2.46/drivers/net/hyperv/netvsc_drv.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/hyperv/netvsc_drv.c 2013-07-26 19:18:18.000000000 +0000 ++++ linux-3.2.46/drivers/net/hyperv/netvsc_drv.c 2013-07-26 19:18:21.000000000 +0000 +@@ -56,11 +56,51 @@ module_param(ring_size, int, S_IRUGO); MODULE_PARM_DESC(ring_size, "Ring buffer size (# of pages)"); @@ -117,10 +117,10 @@ } static int netvsc_open(struct net_device *net) -diff --git a/drivers/net/hyperv/rndis_filter.c b/drivers/net/hyperv/rndis_filter.c -index bafccb3..418e7aa 100644 ---- a/drivers/net/hyperv/rndis_filter.c -+++ b/drivers/net/hyperv/rndis_filter.c +Index: linux-3.2.46/drivers/net/hyperv/rndis_filter.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/hyperv/rndis_filter.c 2013-07-26 19:18:18.000000000 +0000 ++++ linux-3.2.46/drivers/net/hyperv/rndis_filter.c 2013-07-26 19:18:21.000000000 +0000 @@ -30,26 +30,6 @@ #include "hyperv_net.h" @@ -148,7 +148,7 @@ struct rndis_request { struct list_head list_ent; struct completion wait_event; -@@ -522,8 +502,7 @@ static int rndis_filter_query_device_link_status(struct rndis_device *dev) +@@ -522,8 +502,7 @@ return ret; } @@ -158,6 +158,3 @@ { struct rndis_request *request; struct rndis_set_request *set; --- -1.7.9.5 - diff -Nru linux-3.2.46/debian/patches/features/x86/hyperv/0021-Staging-hv-storvsc-Disable-clustering.patch linux-3.2.46/debian/patches/features/x86/hyperv/0021-Staging-hv-storvsc-Disable-clustering.patch --- linux-3.2.46/debian/patches/features/x86/hyperv/0021-Staging-hv-storvsc-Disable-clustering.patch 2013-02-24 03:52:26.000000000 +0000 +++ linux-3.2.46/debian/patches/features/x86/hyperv/0021-Staging-hv-storvsc-Disable-clustering.patch 2013-07-26 19:18:24.000000000 +0000 @@ -17,11 +17,11 @@ drivers/staging/hv/storvsc_drv.c | 18 +----------------- 1 file changed, 1 insertion(+), 17 deletions(-) -diff --git a/drivers/staging/hv/storvsc_drv.c b/drivers/staging/hv/storvsc_drv.c -index 0245143..9153f98 100644 ---- a/drivers/staging/hv/storvsc_drv.c -+++ b/drivers/staging/hv/storvsc_drv.c -@@ -798,13 +798,6 @@ static int storvsc_device_alloc(struct scsi_device *sdevice) +Index: linux-3.2.46/drivers/staging/hv/storvsc_drv.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/hv/storvsc_drv.c 2013-07-26 19:18:11.000000000 +0000 ++++ linux-3.2.46/drivers/staging/hv/storvsc_drv.c 2013-07-26 19:18:23.000000000 +0000 +@@ -798,13 +798,6 @@ return 0; } @@ -35,7 +35,7 @@ static int storvsc_device_configure(struct scsi_device *sdevice) { scsi_adjust_queue_depth(sdevice, MSG_SIMPLE_TAG, -@@ -812,8 +805,6 @@ static int storvsc_device_configure(struct scsi_device *sdevice) +@@ -812,8 +805,6 @@ blk_queue_max_segment_size(sdevice->request_queue, PAGE_SIZE); @@ -44,7 +44,7 @@ blk_queue_bounce_limit(sdevice->request_queue, BLK_BOUNCE_ANY); return 0; -@@ -1375,14 +1366,7 @@ static struct scsi_host_template scsi_driver = { +@@ -1381,14 +1372,7 @@ /* no use setting to 0 since ll_blk_rw reset it to 1 */ /* currently 32 */ .sg_tablesize = MAX_MULTIPAGE_BUFFER_COUNT, @@ -60,6 +60,3 @@ /* Make sure we dont get a sg segment crosses a page boundary */ .dma_boundary = PAGE_SIZE-1, }; --- -1.7.9.5 - diff -Nru linux-3.2.46/debian/patches/features/x86/hyperv/0022-Staging-hv-storvsc-Cleanup-storvsc_device_alloc.patch linux-3.2.46/debian/patches/features/x86/hyperv/0022-Staging-hv-storvsc-Cleanup-storvsc_device_alloc.patch --- linux-3.2.46/debian/patches/features/x86/hyperv/0022-Staging-hv-storvsc-Cleanup-storvsc_device_alloc.patch 2013-02-24 03:52:26.000000000 +0000 +++ linux-3.2.46/debian/patches/features/x86/hyperv/0022-Staging-hv-storvsc-Cleanup-storvsc_device_alloc.patch 2013-07-26 19:18:25.000000000 +0000 @@ -15,11 +15,11 @@ drivers/staging/hv/storvsc_drv.c | 5 ----- 1 file changed, 5 deletions(-) -diff --git a/drivers/staging/hv/storvsc_drv.c b/drivers/staging/hv/storvsc_drv.c -index 9153f98..14ecb69 100644 ---- a/drivers/staging/hv/storvsc_drv.c -+++ b/drivers/staging/hv/storvsc_drv.c -@@ -790,11 +790,6 @@ static void storvsc_get_ide_info(struct hv_device *dev, int *target, int *path) +Index: linux-3.2.46/drivers/staging/hv/storvsc_drv.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/hv/storvsc_drv.c 2013-07-26 19:18:23.000000000 +0000 ++++ linux-3.2.46/drivers/staging/hv/storvsc_drv.c 2013-07-26 19:18:24.000000000 +0000 +@@ -790,11 +790,6 @@ static int storvsc_device_alloc(struct scsi_device *sdevice) { @@ -31,6 +31,3 @@ return 0; } --- -1.7.9.5 - diff -Nru linux-3.2.46/debian/patches/features/x86/hyperv/0023-Staging-hv-storvsc-Fix-a-bug-in-storvsc_command_comp.patch linux-3.2.46/debian/patches/features/x86/hyperv/0023-Staging-hv-storvsc-Fix-a-bug-in-storvsc_command_comp.patch --- linux-3.2.46/debian/patches/features/x86/hyperv/0023-Staging-hv-storvsc-Fix-a-bug-in-storvsc_command_comp.patch 2013-02-24 03:52:26.000000000 +0000 +++ linux-3.2.46/debian/patches/features/x86/hyperv/0023-Staging-hv-storvsc-Fix-a-bug-in-storvsc_command_comp.patch 2013-07-26 19:18:26.000000000 +0000 @@ -15,11 +15,11 @@ drivers/staging/hv/storvsc_drv.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) -diff --git a/drivers/staging/hv/storvsc_drv.c b/drivers/staging/hv/storvsc_drv.c -index 14ecb69..8dafe52 100644 ---- a/drivers/staging/hv/storvsc_drv.c -+++ b/drivers/staging/hv/storvsc_drv.c -@@ -1123,13 +1123,12 @@ static void storvsc_command_completion(struct hv_storvsc_request *request) +Index: linux-3.2.46/drivers/staging/hv/storvsc_drv.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/hv/storvsc_drv.c 2013-07-26 19:18:24.000000000 +0000 ++++ linux-3.2.46/drivers/staging/hv/storvsc_drv.c 2013-07-26 19:18:25.000000000 +0000 +@@ -1129,13 +1129,12 @@ vm_srb = &request->vstor_packet.vm_srb; if (cmd_request->bounce_sgl_count) { @@ -35,6 +35,3 @@ } /* --- -1.7.9.5 - diff -Nru linux-3.2.46/debian/patches/features/x86/hyperv/0024-Staging-hv-storvsc-Fix-a-bug-in-copy_from_bounce_buf.patch linux-3.2.46/debian/patches/features/x86/hyperv/0024-Staging-hv-storvsc-Fix-a-bug-in-copy_from_bounce_buf.patch --- linux-3.2.46/debian/patches/features/x86/hyperv/0024-Staging-hv-storvsc-Fix-a-bug-in-copy_from_bounce_buf.patch 2013-02-24 03:52:26.000000000 +0000 +++ linux-3.2.46/debian/patches/features/x86/hyperv/0024-Staging-hv-storvsc-Fix-a-bug-in-copy_from_bounce_buf.patch 2013-07-26 19:18:27.000000000 +0000 @@ -14,11 +14,11 @@ drivers/staging/hv/storvsc_drv.c | 24 ++++++++++++++++++++++-- 1 file changed, 22 insertions(+), 2 deletions(-) -diff --git a/drivers/staging/hv/storvsc_drv.c b/drivers/staging/hv/storvsc_drv.c -index 8dafe52..c22de06 100644 ---- a/drivers/staging/hv/storvsc_drv.c -+++ b/drivers/staging/hv/storvsc_drv.c -@@ -880,7 +880,8 @@ cleanup: +Index: linux-3.2.46/drivers/staging/hv/storvsc_drv.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/hv/storvsc_drv.c 2013-07-26 19:18:25.000000000 +0000 ++++ linux-3.2.46/drivers/staging/hv/storvsc_drv.c 2013-07-26 19:18:26.000000000 +0000 +@@ -881,7 +881,8 @@ /* Assume the original sgl has enough room */ static unsigned int copy_from_bounce_buffer(struct scatterlist *orig_sgl, struct scatterlist *bounce_sgl, @@ -28,7 +28,7 @@ { int i; int j = 0; -@@ -921,6 +922,24 @@ static unsigned int copy_from_bounce_buffer(struct scatterlist *orig_sgl, +@@ -922,6 +923,24 @@ kunmap_atomic((void *)bounce_addr, KM_IRQ0); j++; @@ -53,7 +53,7 @@ /* if we need to use another bounce buffer */ if (destlen || i != orig_sgl_count - 1) bounce_addr = -@@ -1126,7 +1145,8 @@ static void storvsc_command_completion(struct hv_storvsc_request *request) +@@ -1132,7 +1151,8 @@ if (vm_srb->data_in == READ_TYPE) copy_from_bounce_buffer(scsi_sglist(scmnd), cmd_request->bounce_sgl, @@ -63,6 +63,3 @@ destroy_bounce_buffer(cmd_request->bounce_sgl, cmd_request->bounce_sgl_count); } --- -1.7.9.5 - diff -Nru linux-3.2.46/debian/patches/features/x86/hyperv/0025-Staging-hv-storvsc-Implement-per-device-memory-pools.patch linux-3.2.46/debian/patches/features/x86/hyperv/0025-Staging-hv-storvsc-Implement-per-device-memory-pools.patch --- linux-3.2.46/debian/patches/features/x86/hyperv/0025-Staging-hv-storvsc-Implement-per-device-memory-pools.patch 2013-02-24 03:52:26.000000000 +0000 +++ linux-3.2.46/debian/patches/features/x86/hyperv/0025-Staging-hv-storvsc-Implement-per-device-memory-pools.patch 2013-07-26 19:18:29.000000000 +0000 @@ -18,11 +18,11 @@ drivers/staging/hv/storvsc_drv.c | 106 ++++++++++++++++++++++---------------- 1 file changed, 62 insertions(+), 44 deletions(-) -diff --git a/drivers/staging/hv/storvsc_drv.c b/drivers/staging/hv/storvsc_drv.c -index c22de06..18f8771 100644 ---- a/drivers/staging/hv/storvsc_drv.c -+++ b/drivers/staging/hv/storvsc_drv.c -@@ -285,10 +285,13 @@ struct storvsc_device { +Index: linux-3.2.46/drivers/staging/hv/storvsc_drv.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/hv/storvsc_drv.c 2013-07-26 19:18:26.000000000 +0000 ++++ linux-3.2.46/drivers/staging/hv/storvsc_drv.c 2013-07-26 19:18:28.000000000 +0000 +@@ -285,10 +285,13 @@ struct hv_storvsc_request reset_request; }; @@ -38,7 +38,7 @@ unsigned int port; unsigned char path; unsigned char target; -@@ -790,7 +793,48 @@ static void storvsc_get_ide_info(struct hv_device *dev, int *target, int *path) +@@ -790,7 +793,48 @@ static int storvsc_device_alloc(struct scsi_device *sdevice) { @@ -87,7 +87,7 @@ } static int storvsc_device_configure(struct scsi_device *sdevice) -@@ -1031,19 +1075,13 @@ static int storvsc_remove(struct hv_device *dev) +@@ -1032,19 +1076,13 @@ { struct storvsc_device *stor_device = hv_get_drvdata(dev); struct Scsi_Host *host = stor_device->host; @@ -108,7 +108,7 @@ return 0; } -@@ -1139,6 +1177,7 @@ static void storvsc_command_completion(struct hv_storvsc_request *request) +@@ -1145,6 +1183,7 @@ struct scsi_sense_hdr sense_hdr; struct vmscsi_request *vm_srb; struct storvsc_scan_work *wrk; @@ -116,7 +116,7 @@ vm_srb = &request->vstor_packet.vm_srb; if (cmd_request->bounce_sgl_count) { -@@ -1201,7 +1240,7 @@ static void storvsc_command_completion(struct hv_storvsc_request *request) +@@ -1207,7 +1246,7 @@ scsi_done_fn(scmnd); @@ -125,7 +125,7 @@ } static bool storvsc_check_scsi_cmd(struct scsi_cmnd *scmnd) -@@ -1236,6 +1275,7 @@ static int storvsc_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *scmnd) +@@ -1242,6 +1281,7 @@ struct scatterlist *sgl; unsigned int sg_count = 0; struct vmscsi_request *vm_srb; @@ -133,7 +133,7 @@ if (storvsc_check_scsi_cmd(scmnd) == false) { scmnd->scsi_done(scmnd); -@@ -1253,7 +1293,7 @@ static int storvsc_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *scmnd) +@@ -1259,7 +1299,7 @@ request_size = sizeof(struct storvsc_cmd_request); @@ -142,7 +142,7 @@ GFP_ATOMIC); if (!cmd_request) return SCSI_MLQUEUE_DEVICE_BUSY; -@@ -1312,7 +1352,7 @@ static int storvsc_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *scmnd) +@@ -1318,7 +1358,7 @@ if (!cmd_request->bounce_sgl) { scmnd->host_scribble = NULL; mempool_free(cmd_request, @@ -151,7 +151,7 @@ return SCSI_MLQUEUE_HOST_BUSY; } -@@ -1354,7 +1394,7 @@ retry_request: +@@ -1360,7 +1400,7 @@ destroy_bounce_buffer(cmd_request->bounce_sgl, cmd_request->bounce_sgl_count); @@ -160,7 +160,7 @@ scmnd->host_scribble = NULL; -@@ -1372,6 +1412,7 @@ static struct scsi_host_template scsi_driver = { +@@ -1378,6 +1418,7 @@ .queuecommand = storvsc_queuecommand, .eh_host_reset_handler = storvsc_host_reset_handler, .slave_alloc = storvsc_device_alloc, @@ -168,7 +168,7 @@ .slave_configure = storvsc_device_configure, .cmd_per_lun = 1, /* 64 max_queue * 1 target */ -@@ -1413,7 +1454,6 @@ static int storvsc_probe(struct hv_device *device, +@@ -1419,7 +1460,6 @@ const struct hv_vmbus_device_id *dev_id) { int ret; @@ -176,7 +176,7 @@ struct Scsi_Host *host; struct hv_host_device *host_dev; bool dev_is_ide = ((dev_id->driver_data == IDE_GUID) ? true : false); -@@ -1432,29 +1472,11 @@ static int storvsc_probe(struct hv_device *device, +@@ -1438,29 +1478,11 @@ host_dev->port = host->host_no; host_dev->dev = device; @@ -207,7 +207,7 @@ } stor_device->destroy = false; -@@ -1466,7 +1488,7 @@ static int storvsc_probe(struct hv_device *device, +@@ -1472,7 +1494,7 @@ stor_device->port_number = host->host_no; ret = storvsc_connect_to_vsp(device, storvsc_ringbuffer_size); if (ret) @@ -216,7 +216,7 @@ if (dev_is_ide) storvsc_get_ide_info(device, &target, &path); -@@ -1486,7 +1508,7 @@ static int storvsc_probe(struct hv_device *device, +@@ -1492,7 +1514,7 @@ /* Register the HBA and start the scsi bus scan */ ret = scsi_add_host(host, &device->device); if (ret != 0) @@ -225,7 +225,7 @@ if (!dev_is_ide) { scsi_scan_host(host); -@@ -1495,28 +1517,24 @@ static int storvsc_probe(struct hv_device *device, +@@ -1501,28 +1523,24 @@ ret = scsi_add_device(host, 0, target, 0); if (ret) { scsi_remove_host(host); @@ -259,6 +259,3 @@ scsi_host_put(host); return ret; } --- -1.7.9.5 - diff -Nru linux-3.2.46/debian/patches/features/x86/hyperv/0026-Staging-hv-update-TODO-file.patch linux-3.2.46/debian/patches/features/x86/hyperv/0026-Staging-hv-update-TODO-file.patch --- linux-3.2.46/debian/patches/features/x86/hyperv/0026-Staging-hv-update-TODO-file.patch 2013-02-24 03:52:26.000000000 +0000 +++ linux-3.2.46/debian/patches/features/x86/hyperv/0026-Staging-hv-update-TODO-file.patch 2013-07-26 19:18:30.000000000 +0000 @@ -13,17 +13,14 @@ drivers/staging/hv/TODO | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) -diff --git a/drivers/staging/hv/TODO b/drivers/staging/hv/TODO -index fd080cb..dea7d92 100644 ---- a/drivers/staging/hv/TODO -+++ b/drivers/staging/hv/TODO -@@ -2,5 +2,4 @@ TODO: +Index: linux-3.2.46/drivers/staging/hv/TODO +=================================================================== +--- linux-3.2.46.orig/drivers/staging/hv/TODO 2013-07-26 19:18:18.000000000 +0000 ++++ linux-3.2.46/drivers/staging/hv/TODO 2013-07-26 19:18:29.000000000 +0000 +@@ -2,5 +2,4 @@ - audit the scsi driver Please send patches for this code to Greg Kroah-Hartman , -Hank Janssen , Haiyang Zhang , -K. Y. Srinivasan +Haiyang Zhang , and K. Y. Srinivasan --- -1.7.9.5 - diff -Nru linux-3.2.46/debian/patches/features/x86/hyperv/0027-HID-hv_mouse-Properly-add-the-hid-device.patch linux-3.2.46/debian/patches/features/x86/hyperv/0027-HID-hv_mouse-Properly-add-the-hid-device.patch --- linux-3.2.46/debian/patches/features/x86/hyperv/0027-HID-hv_mouse-Properly-add-the-hid-device.patch 2013-02-24 03:52:26.000000000 +0000 +++ linux-3.2.46/debian/patches/features/x86/hyperv/0027-HID-hv_mouse-Properly-add-the-hid-device.patch 2013-07-26 19:18:31.000000000 +0000 @@ -14,11 +14,11 @@ drivers/hid/hid-hyperv.c | 4 ++++ 1 file changed, 4 insertions(+) -diff --git a/drivers/hid/hid-hyperv.c b/drivers/hid/hid-hyperv.c -index d503cbb..0c33ae9 100644 ---- a/drivers/hid/hid-hyperv.c -+++ b/drivers/hid/hid-hyperv.c -@@ -506,6 +506,10 @@ static int mousevsc_probe(struct hv_device *device, +Index: linux-3.2.46/drivers/hid/hid-hyperv.c +=================================================================== +--- linux-3.2.46.orig/drivers/hid/hid-hyperv.c 2013-07-26 19:17:57.000000000 +0000 ++++ linux-3.2.46/drivers/hid/hid-hyperv.c 2013-07-26 19:18:30.000000000 +0000 +@@ -506,6 +506,10 @@ sprintf(hid_dev->name, "%s", "Microsoft Vmbus HID-compliant Mouse"); @@ -29,6 +29,3 @@ ret = hid_parse_report(hid_dev, input_dev->report_desc, input_dev->report_desc_size); --- -1.7.9.5 - diff -Nru linux-3.2.46/debian/patches/features/x86/hyperv/0028-Staging-hv-storvsc-Fix-a-bug-in-create_bounce_buffer.patch linux-3.2.46/debian/patches/features/x86/hyperv/0028-Staging-hv-storvsc-Fix-a-bug-in-create_bounce_buffer.patch --- linux-3.2.46/debian/patches/features/x86/hyperv/0028-Staging-hv-storvsc-Fix-a-bug-in-create_bounce_buffer.patch 2013-02-24 03:52:26.000000000 +0000 +++ linux-3.2.46/debian/patches/features/x86/hyperv/0028-Staging-hv-storvsc-Fix-a-bug-in-create_bounce_buffer.patch 2013-07-26 19:18:32.000000000 +0000 @@ -21,11 +21,11 @@ drivers/staging/hv/storvsc_drv.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) -diff --git a/drivers/staging/hv/storvsc_drv.c b/drivers/staging/hv/storvsc_drv.c -index 18f8771..eb853f7 100644 ---- a/drivers/staging/hv/storvsc_drv.c -+++ b/drivers/staging/hv/storvsc_drv.c -@@ -893,12 +893,14 @@ static int do_bounce_buffer(struct scatterlist *sgl, unsigned int sg_count) +Index: linux-3.2.46/drivers/staging/hv/storvsc_drv.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/hv/storvsc_drv.c 2013-07-26 19:18:28.000000000 +0000 ++++ linux-3.2.46/drivers/staging/hv/storvsc_drv.c 2013-07-26 19:18:31.000000000 +0000 +@@ -893,12 +893,14 @@ static struct scatterlist *create_bounce_buffer(struct scatterlist *sgl, unsigned int sg_count, @@ -41,7 +41,7 @@ num_pages = ALIGN(len, PAGE_SIZE) >> PAGE_SHIFT; -@@ -910,7 +912,7 @@ static struct scatterlist *create_bounce_buffer(struct scatterlist *sgl, +@@ -911,7 +913,7 @@ page_buf = alloc_page(GFP_ATOMIC); if (!page_buf) goto cleanup; @@ -50,7 +50,7 @@ } return bounce_sgl; -@@ -1348,7 +1350,8 @@ static int storvsc_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *scmnd) +@@ -1354,7 +1356,8 @@ if (do_bounce_buffer(sgl, scsi_sg_count(scmnd)) != -1) { cmd_request->bounce_sgl = create_bounce_buffer(sgl, scsi_sg_count(scmnd), @@ -60,6 +60,3 @@ if (!cmd_request->bounce_sgl) { scmnd->host_scribble = NULL; mempool_free(cmd_request, --- -1.7.9.5 - diff -Nru linux-3.2.46/debian/patches/features/x86/hyperv/0029-net-hyperv-Fix-the-stop-wake-queue-mechanism.patch linux-3.2.46/debian/patches/features/x86/hyperv/0029-net-hyperv-Fix-the-stop-wake-queue-mechanism.patch --- linux-3.2.46/debian/patches/features/x86/hyperv/0029-net-hyperv-Fix-the-stop-wake-queue-mechanism.patch 2013-02-24 03:52:26.000000000 +0000 +++ linux-3.2.46/debian/patches/features/x86/hyperv/0029-net-hyperv-Fix-the-stop-wake-queue-mechanism.patch 2013-07-26 19:18:34.000000000 +0000 @@ -24,11 +24,11 @@ drivers/net/hyperv/netvsc_drv.c | 24 +----------------------- 2 files changed, 12 insertions(+), 26 deletions(-) -diff --git a/drivers/net/hyperv/netvsc.c b/drivers/net/hyperv/netvsc.c -index 4a807e4..b6ac152 100644 ---- a/drivers/net/hyperv/netvsc.c -+++ b/drivers/net/hyperv/netvsc.c -@@ -435,6 +435,9 @@ static void netvsc_send_completion(struct hv_device *device, +Index: linux-3.2.46/drivers/net/hyperv/netvsc.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/hyperv/netvsc.c 2013-07-26 19:18:20.000000000 +0000 ++++ linux-3.2.46/drivers/net/hyperv/netvsc.c 2013-07-26 19:18:33.000000000 +0000 +@@ -435,6 +435,9 @@ nvsc_packet->completion.send.send_completion_ctx); atomic_dec(&net_device->num_outstanding_sends); @@ -38,7 +38,7 @@ } else { netdev_err(ndev, "Unknown send completion packet type- " "%d received!!\n", nvsp_packet->hdr.msg_type); -@@ -485,11 +488,16 @@ int netvsc_send(struct hv_device *device, +@@ -485,11 +488,16 @@ } @@ -58,10 +58,10 @@ return ret; } -diff --git a/drivers/net/hyperv/netvsc_drv.c b/drivers/net/hyperv/netvsc_drv.c -index b69c3a4..7da85eb 100644 ---- a/drivers/net/hyperv/netvsc_drv.c -+++ b/drivers/net/hyperv/netvsc_drv.c +Index: linux-3.2.46/drivers/net/hyperv/netvsc_drv.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/hyperv/netvsc_drv.c 2013-07-26 19:18:21.000000000 +0000 ++++ linux-3.2.46/drivers/net/hyperv/netvsc_drv.c 2013-07-26 19:18:33.000000000 +0000 @@ -43,15 +43,10 @@ struct net_device_context { /* point back to our device context */ @@ -78,7 +78,7 @@ static int ring_size = 128; module_param(ring_size, int, S_IRUGO); MODULE_PARM_DESC(ring_size, "Ring buffer size (# of pages)"); -@@ -144,18 +139,8 @@ static void netvsc_xmit_completion(void *context) +@@ -144,18 +139,8 @@ kfree(packet); @@ -98,7 +98,7 @@ } static int netvsc_start_xmit(struct sk_buff *skb, struct net_device *net) -@@ -167,8 +152,6 @@ static int netvsc_start_xmit(struct sk_buff *skb, struct net_device *net) +@@ -167,8 +152,6 @@ /* Add 1 for skb->data and additional one for RNDIS */ num_pages = skb_shinfo(skb)->nr_frags + 1 + 1; @@ -107,7 +107,7 @@ /* Allocate a netvsc packet based on # of frags. */ packet = kzalloc(sizeof(struct hv_netvsc_packet) + -@@ -218,10 +201,6 @@ static int netvsc_start_xmit(struct sk_buff *skb, struct net_device *net) +@@ -218,10 +201,6 @@ if (ret == 0) { net->stats.tx_bytes += skb->len; net->stats.tx_packets++; @@ -118,7 +118,7 @@ } else { /* we are shutting down or bus overloaded, just drop packet */ net->stats.tx_dropped++; -@@ -391,7 +370,6 @@ static int netvsc_probe(struct hv_device *dev, +@@ -391,7 +370,6 @@ net_device_ctx = netdev_priv(net); net_device_ctx->device_ctx = dev; @@ -126,6 +126,3 @@ hv_set_drvdata(dev, net); INIT_DELAYED_WORK(&net_device_ctx->dwork, netvsc_send_garp); --- -1.7.9.5 - diff -Nru linux-3.2.46/debian/patches/features/x86/hyperv/0030-Drivers-hv-Fix-a-memory-leak.patch linux-3.2.46/debian/patches/features/x86/hyperv/0030-Drivers-hv-Fix-a-memory-leak.patch --- linux-3.2.46/debian/patches/features/x86/hyperv/0030-Drivers-hv-Fix-a-memory-leak.patch 2013-02-24 03:52:26.000000000 +0000 +++ linux-3.2.46/debian/patches/features/x86/hyperv/0030-Drivers-hv-Fix-a-memory-leak.patch 2013-07-26 19:18:35.000000000 +0000 @@ -14,11 +14,11 @@ drivers/hv/channel_mgmt.c | 1 + 1 file changed, 1 insertion(+) -diff --git a/drivers/hv/channel_mgmt.c b/drivers/hv/channel_mgmt.c -index 12b85ff..b91af50 100644 ---- a/drivers/hv/channel_mgmt.c -+++ b/drivers/hv/channel_mgmt.c -@@ -287,6 +287,7 @@ static void vmbus_process_offer(struct work_struct *work) +Index: linux-3.2.46/drivers/hv/channel_mgmt.c +=================================================================== +--- linux-3.2.46.orig/drivers/hv/channel_mgmt.c 2013-07-26 18:56:09.000000000 +0000 ++++ linux-3.2.46/drivers/hv/channel_mgmt.c 2013-07-26 19:18:34.000000000 +0000 +@@ -287,6 +287,7 @@ spin_lock_irqsave(&vmbus_connection.channel_lock, flags); list_del(&newchannel->listentry); spin_unlock_irqrestore(&vmbus_connection.channel_lock, flags); @@ -26,6 +26,3 @@ free_channel(newchannel); } else { --- -1.7.9.5 - diff -Nru linux-3.2.46/debian/patches/features/x86/hyperv/0031-Drivers-hv-Make-the-vmbus-driver-unloadable.patch linux-3.2.46/debian/patches/features/x86/hyperv/0031-Drivers-hv-Make-the-vmbus-driver-unloadable.patch --- linux-3.2.46/debian/patches/features/x86/hyperv/0031-Drivers-hv-Make-the-vmbus-driver-unloadable.patch 2013-02-24 03:52:26.000000000 +0000 +++ linux-3.2.46/debian/patches/features/x86/hyperv/0031-Drivers-hv-Make-the-vmbus-driver-unloadable.patch 2013-07-26 19:18:36.000000000 +0000 @@ -17,11 +17,11 @@ drivers/hv/vmbus_drv.c | 11 +++++++++++ 4 files changed, 26 insertions(+) -diff --git a/drivers/hv/channel_mgmt.c b/drivers/hv/channel_mgmt.c -index b91af50..36484db 100644 ---- a/drivers/hv/channel_mgmt.c -+++ b/drivers/hv/channel_mgmt.c -@@ -223,6 +223,17 @@ static void vmbus_process_rescind_offer(struct work_struct *work) +Index: linux-3.2.46/drivers/hv/channel_mgmt.c +=================================================================== +--- linux-3.2.46.orig/drivers/hv/channel_mgmt.c 2013-07-26 19:18:34.000000000 +0000 ++++ linux-3.2.46/drivers/hv/channel_mgmt.c 2013-07-26 19:18:35.000000000 +0000 +@@ -223,6 +223,17 @@ vmbus_device_unregister(channel->device_obj); } @@ -39,11 +39,11 @@ /* * vmbus_process_offer - Process the offer by creating a channel/device * associated with this offer -diff --git a/drivers/hv/hv.c b/drivers/hv/hv.c -index 0fb100e..f8a77d0 100644 ---- a/drivers/hv/hv.c -+++ b/drivers/hv/hv.c -@@ -237,6 +237,9 @@ void hv_cleanup(void) +Index: linux-3.2.46/drivers/hv/hv.c +=================================================================== +--- linux-3.2.46.orig/drivers/hv/hv.c 2013-07-26 18:56:09.000000000 +0000 ++++ linux-3.2.46/drivers/hv/hv.c 2013-07-26 19:18:35.000000000 +0000 +@@ -237,6 +237,9 @@ { union hv_x64_msr_hypercall_contents hypercall_msr; @@ -53,11 +53,11 @@ kfree(hv_context.signal_event_buffer); hv_context.signal_event_buffer = NULL; hv_context.signal_event_param = NULL; -diff --git a/drivers/hv/hyperv_vmbus.h b/drivers/hv/hyperv_vmbus.h -index 0aee112..6d7d286 100644 ---- a/drivers/hv/hyperv_vmbus.h -+++ b/drivers/hv/hyperv_vmbus.h -@@ -611,6 +611,7 @@ void vmbus_device_unregister(struct hv_device *device_obj); +Index: linux-3.2.46/drivers/hv/hyperv_vmbus.h +=================================================================== +--- linux-3.2.46.orig/drivers/hv/hyperv_vmbus.h 2013-07-26 18:56:09.000000000 +0000 ++++ linux-3.2.46/drivers/hv/hyperv_vmbus.h 2013-07-26 19:18:35.000000000 +0000 +@@ -611,6 +611,7 @@ struct vmbus_channel *relid2channel(u32 relid); @@ -65,11 +65,11 @@ /* Connection interface */ -diff --git a/drivers/hv/vmbus_drv.c b/drivers/hv/vmbus_drv.c -index 05168eb..a220e57 100644 ---- a/drivers/hv/vmbus_drv.c -+++ b/drivers/hv/vmbus_drv.c -@@ -792,8 +792,19 @@ cleanup: +Index: linux-3.2.46/drivers/hv/vmbus_drv.c +=================================================================== +--- linux-3.2.46.orig/drivers/hv/vmbus_drv.c 2013-07-26 19:18:14.000000000 +0000 ++++ linux-3.2.46/drivers/hv/vmbus_drv.c 2013-07-26 19:18:35.000000000 +0000 +@@ -792,8 +792,19 @@ return ret; } @@ -89,6 +89,3 @@ subsys_initcall(hv_acpi_init); +module_exit(vmbus_exit); --- -1.7.9.5 - diff -Nru linux-3.2.46/debian/patches/features/x86/hyperv/0032-Drivers-hv-Get-rid-of-an-unnecessary-check-in-hv.c.patch linux-3.2.46/debian/patches/features/x86/hyperv/0032-Drivers-hv-Get-rid-of-an-unnecessary-check-in-hv.c.patch --- linux-3.2.46/debian/patches/features/x86/hyperv/0032-Drivers-hv-Get-rid-of-an-unnecessary-check-in-hv.c.patch 2013-02-24 03:52:26.000000000 +0000 +++ linux-3.2.46/debian/patches/features/x86/hyperv/0032-Drivers-hv-Get-rid-of-an-unnecessary-check-in-hv.c.patch 2013-07-26 19:18:38.000000000 +0000 @@ -14,11 +14,11 @@ drivers/hv/hv.c | 5 ----- 1 file changed, 5 deletions(-) -diff --git a/drivers/hv/hv.c b/drivers/hv/hv.c -index f8a77d0..12aa97f 100644 ---- a/drivers/hv/hv.c -+++ b/drivers/hv/hv.c -@@ -164,11 +164,6 @@ int hv_init(void) +Index: linux-3.2.46/drivers/hv/hv.c +=================================================================== +--- linux-3.2.46.orig/drivers/hv/hv.c 2013-07-26 19:18:35.000000000 +0000 ++++ linux-3.2.46/drivers/hv/hv.c 2013-07-26 19:18:37.000000000 +0000 +@@ -164,11 +164,6 @@ max_leaf = query_hypervisor_info(); @@ -30,6 +30,3 @@ /* Write our OS info */ wrmsrl(HV_X64_MSR_GUEST_OS_ID, HV_LINUX_GUEST_ID); hv_context.guestid = HV_LINUX_GUEST_ID; --- -1.7.9.5 - diff -Nru linux-3.2.46/debian/patches/features/x86/hyperv/0033-net-hyperv-Remove-unnecessary-kmap_atomic-in-netvsc-.patch linux-3.2.46/debian/patches/features/x86/hyperv/0033-net-hyperv-Remove-unnecessary-kmap_atomic-in-netvsc-.patch --- linux-3.2.46/debian/patches/features/x86/hyperv/0033-net-hyperv-Remove-unnecessary-kmap_atomic-in-netvsc-.patch 2013-02-24 03:52:26.000000000 +0000 +++ linux-3.2.46/debian/patches/features/x86/hyperv/0033-net-hyperv-Remove-unnecessary-kmap_atomic-in-netvsc-.patch 2013-07-26 19:18:39.000000000 +0000 @@ -19,11 +19,11 @@ drivers/net/hyperv/rndis_filter.c | 21 ++------------- 4 files changed, 10 insertions(+), 92 deletions(-) -diff --git a/drivers/net/hyperv/hyperv_net.h b/drivers/net/hyperv/hyperv_net.h -index 49b131f..ff1b520 100644 ---- a/drivers/net/hyperv/hyperv_net.h -+++ b/drivers/net/hyperv/hyperv_net.h -@@ -39,9 +39,6 @@ struct xferpage_packet { +Index: linux-3.2.46/drivers/net/hyperv/hyperv_net.h +=================================================================== +--- linux-3.2.46.orig/drivers/net/hyperv/hyperv_net.h 2013-07-26 19:18:21.000000000 +0000 ++++ linux-3.2.46/drivers/net/hyperv/hyperv_net.h 2013-07-26 19:18:38.000000000 +0000 +@@ -39,9 +39,6 @@ u32 count; }; @@ -33,7 +33,7 @@ /* * Represent netvsc packet which contains 1 RNDIS and 1 ethernet frame * within the RNDIS -@@ -77,8 +74,9 @@ struct hv_netvsc_packet { +@@ -77,8 +74,9 @@ u32 total_data_buflen; /* Points to the send/receive buffer where the ethernet frame is */ @@ -44,11 +44,11 @@ }; struct netvsc_device_info { -diff --git a/drivers/net/hyperv/netvsc.c b/drivers/net/hyperv/netvsc.c -index b6ac152..bab627f 100644 ---- a/drivers/net/hyperv/netvsc.c -+++ b/drivers/net/hyperv/netvsc.c -@@ -603,12 +603,10 @@ static void netvsc_receive(struct hv_device *device, +Index: linux-3.2.46/drivers/net/hyperv/netvsc.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/hyperv/netvsc.c 2013-07-26 19:18:33.000000000 +0000 ++++ linux-3.2.46/drivers/net/hyperv/netvsc.c 2013-07-26 19:18:38.000000000 +0000 +@@ -603,12 +603,10 @@ struct vmtransfer_page_packet_header *vmxferpage_packet; struct nvsp_message *nvsp_packet; struct hv_netvsc_packet *netvsc_packet = NULL; @@ -63,7 +63,7 @@ unsigned long flags; struct net_device *ndev; -@@ -717,53 +715,10 @@ static void netvsc_receive(struct hv_device *device, +@@ -717,53 +715,10 @@ netvsc_packet->completion.recv.recv_completion_tid = vmxferpage_packet->d.trans_id; @@ -119,11 +119,11 @@ /* Pass it to the upper layer */ rndis_filter_receive(device, netvsc_packet); -diff --git a/drivers/net/hyperv/netvsc_drv.c b/drivers/net/hyperv/netvsc_drv.c -index 7da85eb..b7cbd12 100644 ---- a/drivers/net/hyperv/netvsc_drv.c -+++ b/drivers/net/hyperv/netvsc_drv.c -@@ -251,9 +251,6 @@ int netvsc_recv_callback(struct hv_device *device_obj, +Index: linux-3.2.46/drivers/net/hyperv/netvsc_drv.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/hyperv/netvsc_drv.c 2013-07-26 19:18:33.000000000 +0000 ++++ linux-3.2.46/drivers/net/hyperv/netvsc_drv.c 2013-07-26 19:18:38.000000000 +0000 +@@ -251,9 +251,6 @@ { struct net_device *net = dev_get_drvdata(&device_obj->device); struct sk_buff *skb; @@ -133,7 +133,7 @@ struct netvsc_device *net_device; net_device = hv_get_drvdata(device_obj); -@@ -272,27 +269,12 @@ int netvsc_recv_callback(struct hv_device *device_obj, +@@ -272,27 +269,12 @@ return 0; } @@ -163,11 +163,11 @@ skb->protocol = eth_type_trans(skb, net); skb->ip_summed = CHECKSUM_NONE; -diff --git a/drivers/net/hyperv/rndis_filter.c b/drivers/net/hyperv/rndis_filter.c -index 418e7aa..da181f9 100644 ---- a/drivers/net/hyperv/rndis_filter.c -+++ b/drivers/net/hyperv/rndis_filter.c -@@ -309,7 +309,6 @@ static void rndis_filter_receive_data(struct rndis_device *dev, +Index: linux-3.2.46/drivers/net/hyperv/rndis_filter.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/hyperv/rndis_filter.c 2013-07-26 19:18:21.000000000 +0000 ++++ linux-3.2.46/drivers/net/hyperv/rndis_filter.c 2013-07-26 19:18:38.000000000 +0000 +@@ -309,7 +309,6 @@ { struct rndis_packet *rndis_pkt; u32 data_offset; @@ -175,7 +175,7 @@ rndis_pkt = &msg->msg.pkt; -@@ -322,17 +321,7 @@ static void rndis_filter_receive_data(struct rndis_device *dev, +@@ -322,17 +321,7 @@ data_offset = RNDIS_HEADER_SIZE + rndis_pkt->data_offset; pkt->total_data_buflen -= data_offset; @@ -194,7 +194,7 @@ pkt->is_data_pkt = true; -@@ -367,11 +356,7 @@ int rndis_filter_receive(struct hv_device *dev, +@@ -367,11 +356,7 @@ return -ENODEV; } @@ -207,7 +207,7 @@ /* Make sure we got a valid rndis message */ if ((rndis_hdr->ndis_msg_type != REMOTE_NDIS_PACKET_MSG) && -@@ -387,8 +372,6 @@ int rndis_filter_receive(struct hv_device *dev, +@@ -387,8 +372,6 @@ sizeof(struct rndis_message) : rndis_hdr->msg_len); @@ -216,6 +216,3 @@ dump_rndis_message(dev, &rndis_msg); switch (rndis_msg.ndis_msg_type) { --- -1.7.9.5 - diff -Nru linux-3.2.46/debian/patches/features/x86/hyperv/0034-net-hyperv-Add-NETVSP-protocol-version-negotiation.patch linux-3.2.46/debian/patches/features/x86/hyperv/0034-net-hyperv-Add-NETVSP-protocol-version-negotiation.patch --- linux-3.2.46/debian/patches/features/x86/hyperv/0034-net-hyperv-Add-NETVSP-protocol-version-negotiation.patch 2013-02-24 03:52:26.000000000 +0000 +++ linux-3.2.46/debian/patches/features/x86/hyperv/0034-net-hyperv-Add-NETVSP-protocol-version-negotiation.patch 2013-07-26 19:18:41.000000000 +0000 @@ -15,11 +15,11 @@ drivers/net/hyperv/netvsc.c | 82 ++++++++++++++++++++----------- 2 files changed, 149 insertions(+), 34 deletions(-) -diff --git a/drivers/net/hyperv/hyperv_net.h b/drivers/net/hyperv/hyperv_net.h -index ff1b520..2877670 100644 ---- a/drivers/net/hyperv/hyperv_net.h -+++ b/drivers/net/hyperv/hyperv_net.h -@@ -134,8 +134,7 @@ int rndis_filter_set_packet_filter(struct rndis_device *dev, u32 new_filter); +Index: linux-3.2.46/drivers/net/hyperv/hyperv_net.h +=================================================================== +--- linux-3.2.46.orig/drivers/net/hyperv/hyperv_net.h 2013-07-26 19:18:38.000000000 +0000 ++++ linux-3.2.46/drivers/net/hyperv/hyperv_net.h 2013-07-26 19:18:40.000000000 +0000 +@@ -134,8 +134,7 @@ #define NVSP_INVALID_PROTOCOL_VERSION ((u32)0xFFFFFFFF) #define NVSP_PROTOCOL_VERSION_1 2 @@ -29,7 +29,7 @@ enum { NVSP_MSG_TYPE_NONE = 0, -@@ -160,11 +159,36 @@ enum { +@@ -160,11 +159,36 @@ NVSP_MSG1_TYPE_SEND_RNDIS_PKT, NVSP_MSG1_TYPE_SEND_RNDIS_PKT_COMPLETE, @@ -71,7 +71,7 @@ }; enum { -@@ -175,6 +199,7 @@ enum { +@@ -175,6 +199,7 @@ NVSP_STAT_PROTOCOL_TOO_OLD, NVSP_STAT_INVALID_RNDIS_PKT, NVSP_STAT_BUSY, @@ -79,7 +79,7 @@ NVSP_STAT_MAX, }; -@@ -359,9 +384,69 @@ union nvsp_1_message_uber { +@@ -359,9 +384,69 @@ send_rndis_pkt_complete; } __packed; @@ -149,7 +149,7 @@ } __packed; /* ALL Messages */ -@@ -391,6 +476,8 @@ struct nvsp_message { +@@ -391,6 +476,8 @@ struct netvsc_device { struct hv_device *dev; @@ -158,10 +158,10 @@ atomic_t num_outstanding_sends; bool destroy; /* -diff --git a/drivers/net/hyperv/netvsc.c b/drivers/net/hyperv/netvsc.c -index bab627f..46828b4 100644 ---- a/drivers/net/hyperv/netvsc.c -+++ b/drivers/net/hyperv/netvsc.c +Index: linux-3.2.46/drivers/net/hyperv/netvsc.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/hyperv/netvsc.c 2013-07-26 19:18:38.000000000 +0000 ++++ linux-3.2.46/drivers/net/hyperv/netvsc.c 2013-07-26 19:18:40.000000000 +0000 @@ -28,6 +28,7 @@ #include #include @@ -170,7 +170,7 @@ #include "hyperv_net.h" -@@ -260,27 +261,18 @@ exit: +@@ -260,27 +261,18 @@ } @@ -205,7 +205,7 @@ /* Send the init request */ ret = vmbus_sendpacket(device->channel, init_packet, -@@ -290,26 +282,62 @@ static int netvsc_connect_vsp(struct hv_device *device) +@@ -290,26 +282,62 @@ VMBUS_DATA_PACKET_FLAG_COMPLETION_REQUESTED); if (ret != 0) @@ -228,9 +228,7 @@ - } + NVSP_STAT_SUCCESS) + return -EINVAL; - -- if (init_packet->msg.init_msg.init_complete. -- negotiated_protocol_ver != NVSP_PROTOCOL_VERSION_1) { ++ + if (nvsp_ver != NVSP_PROTOCOL_VERSION_2) + return 0; + @@ -238,7 +236,9 @@ + memset(init_packet, 0, sizeof(struct nvsp_message)); + init_packet->hdr.msg_type = NVSP_MSG2_TYPE_SEND_NDIS_CONFIG; + init_packet->msg.v2_msg.send_ndis_config.mtu = ETH_DATA_LEN; -+ + +- if (init_packet->msg.init_msg.init_complete. +- negotiated_protocol_ver != NVSP_PROTOCOL_VERSION_1) { + ret = vmbus_sendpacket(device->channel, init_packet, + sizeof(struct nvsp_message), + (unsigned long)init_packet, @@ -279,6 +279,3 @@ /* Send the ndis version */ memset(init_packet, 0, sizeof(struct nvsp_message)); --- -1.7.9.5 - diff -Nru linux-3.2.46/debian/patches/features/x86/hyperv/0035-net-hyperv-Add-support-for-jumbo-frame-up-to-64KB.patch linux-3.2.46/debian/patches/features/x86/hyperv/0035-net-hyperv-Add-support-for-jumbo-frame-up-to-64KB.patch --- linux-3.2.46/debian/patches/features/x86/hyperv/0035-net-hyperv-Add-support-for-jumbo-frame-up-to-64KB.patch 2013-02-24 03:52:26.000000000 +0000 +++ linux-3.2.46/debian/patches/features/x86/hyperv/0035-net-hyperv-Add-support-for-jumbo-frame-up-to-64KB.patch 2013-07-26 19:18:42.000000000 +0000 @@ -17,11 +17,11 @@ include/linux/hyperv.h | 2 +- 4 files changed, 68 insertions(+), 18 deletions(-) -diff --git a/drivers/net/hyperv/hyperv_net.h b/drivers/net/hyperv/hyperv_net.h -index 2877670..dec5836 100644 ---- a/drivers/net/hyperv/hyperv_net.h -+++ b/drivers/net/hyperv/hyperv_net.h -@@ -456,12 +456,9 @@ struct nvsp_message { +Index: linux-3.2.46/drivers/net/hyperv/hyperv_net.h +=================================================================== +--- linux-3.2.46.orig/drivers/net/hyperv/hyperv_net.h 2013-07-26 19:18:40.000000000 +0000 ++++ linux-3.2.46/drivers/net/hyperv/hyperv_net.h 2013-07-26 19:18:41.000000000 +0000 +@@ -456,12 +456,9 @@ } __packed; @@ -36,7 +36,7 @@ #define NETVSC_RECEIVE_BUFFER_ID 0xcafe -@@ -479,6 +476,7 @@ struct netvsc_device { +@@ -479,6 +476,7 @@ u32 nvsp_version; atomic_t num_outstanding_sends; @@ -44,11 +44,11 @@ bool destroy; /* * List of free preallocated hv_netvsc_packet to represent receive -diff --git a/drivers/net/hyperv/netvsc.c b/drivers/net/hyperv/netvsc.c -index 46828b4..8965b45 100644 ---- a/drivers/net/hyperv/netvsc.c -+++ b/drivers/net/hyperv/netvsc.c -@@ -42,7 +42,7 @@ static struct netvsc_device *alloc_net_device(struct hv_device *device) +Index: linux-3.2.46/drivers/net/hyperv/netvsc.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/hyperv/netvsc.c 2013-07-26 19:18:40.000000000 +0000 ++++ linux-3.2.46/drivers/net/hyperv/netvsc.c 2013-07-26 19:18:41.000000000 +0000 +@@ -42,7 +42,7 @@ if (!net_device) return NULL; @@ -57,7 +57,7 @@ net_device->destroy = false; net_device->dev = device; net_device->ndev = ndev; -@@ -299,7 +299,7 @@ static int negotiate_nvsp_ver(struct hv_device *device, +@@ -299,7 +299,7 @@ /* NVSPv2 only: Send NDIS config */ memset(init_packet, 0, sizeof(struct nvsp_message)); init_packet->hdr.msg_type = NVSP_MSG2_TYPE_SEND_NDIS_CONFIG; @@ -66,7 +66,7 @@ ret = vmbus_sendpacket(device->channel, init_packet, sizeof(struct nvsp_message), -@@ -464,7 +464,7 @@ static void netvsc_send_completion(struct hv_device *device, +@@ -464,7 +464,7 @@ atomic_dec(&net_device->num_outstanding_sends); @@ -75,11 +75,11 @@ netif_wake_queue(ndev); } else { netdev_err(ndev, "Unknown send completion packet type- " -diff --git a/drivers/net/hyperv/netvsc_drv.c b/drivers/net/hyperv/netvsc_drv.c -index b7cbd12..462d05f 100644 ---- a/drivers/net/hyperv/netvsc_drv.c -+++ b/drivers/net/hyperv/netvsc_drv.c -@@ -148,10 +148,12 @@ static int netvsc_start_xmit(struct sk_buff *skb, struct net_device *net) +Index: linux-3.2.46/drivers/net/hyperv/netvsc_drv.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/hyperv/netvsc_drv.c 2013-07-26 19:18:38.000000000 +0000 ++++ linux-3.2.46/drivers/net/hyperv/netvsc_drv.c 2013-07-26 19:18:41.000000000 +0000 +@@ -148,10 +148,12 @@ struct net_device_context *net_device_ctx = netdev_priv(net); struct hv_netvsc_packet *packet; int ret; @@ -95,7 +95,7 @@ /* Allocate a netvsc packet based on # of frags. */ packet = kzalloc(sizeof(struct hv_netvsc_packet) + -@@ -174,21 +176,36 @@ static int netvsc_start_xmit(struct sk_buff *skb, struct net_device *net) +@@ -174,21 +176,36 @@ packet->page_buf_cnt = num_pages; /* Initialize it from the skb */ @@ -137,7 +137,7 @@ } /* Set the completion routine */ -@@ -300,6 +317,39 @@ static void netvsc_get_drvinfo(struct net_device *net, +@@ -300,6 +317,39 @@ strcpy(info->fw_version, "N/A"); } @@ -177,7 +177,7 @@ static const struct ethtool_ops ethtool_ops = { .get_drvinfo = netvsc_get_drvinfo, .get_link = ethtool_op_get_link, -@@ -310,7 +360,7 @@ static const struct net_device_ops device_ops = { +@@ -310,7 +360,7 @@ .ndo_stop = netvsc_close, .ndo_start_xmit = netvsc_start_xmit, .ndo_set_rx_mode = netvsc_set_multicast_list, @@ -186,7 +186,7 @@ .ndo_validate_addr = eth_validate_addr, .ndo_set_mac_address = eth_mac_addr, }; -@@ -403,6 +453,8 @@ static int netvsc_remove(struct hv_device *dev) +@@ -403,6 +453,8 @@ return 0; } @@ -195,10 +195,10 @@ ndev_ctx = netdev_priv(net); cancel_delayed_work_sync(&ndev_ctx->dwork); -diff --git a/include/linux/hyperv.h b/include/linux/hyperv.h -index 12ec328..62b908e 100644 ---- a/include/linux/hyperv.h -+++ b/include/linux/hyperv.h +Index: linux-3.2.46/include/linux/hyperv.h +=================================================================== +--- linux-3.2.46.orig/include/linux/hyperv.h 2013-07-26 18:56:07.000000000 +0000 ++++ linux-3.2.46/include/linux/hyperv.h 2013-07-26 19:18:41.000000000 +0000 @@ -35,7 +35,7 @@ #include @@ -208,6 +208,3 @@ #define MAX_MULTIPAGE_BUFFER_COUNT 32 /* 128K */ #pragma pack(push, 1) --- -1.7.9.5 - diff -Nru linux-3.2.46/debian/patches/features/x86/hyperv/0036-net-hyperv-fix-possible-memory-leak-in-do_set_multic.patch linux-3.2.46/debian/patches/features/x86/hyperv/0036-net-hyperv-fix-possible-memory-leak-in-do_set_multic.patch --- linux-3.2.46/debian/patches/features/x86/hyperv/0036-net-hyperv-fix-possible-memory-leak-in-do_set_multic.patch 2013-02-24 03:52:26.000000000 +0000 +++ linux-3.2.46/debian/patches/features/x86/hyperv/0036-net-hyperv-fix-possible-memory-leak-in-do_set_multic.patch 2013-07-26 19:18:44.000000000 +0000 @@ -16,11 +16,11 @@ drivers/net/hyperv/netvsc_drv.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) -diff --git a/drivers/net/hyperv/netvsc_drv.c b/drivers/net/hyperv/netvsc_drv.c -index 462d05f..1a1ca6c 100644 ---- a/drivers/net/hyperv/netvsc_drv.c -+++ b/drivers/net/hyperv/netvsc_drv.c -@@ -68,11 +68,11 @@ static void do_set_multicast(struct work_struct *w) +Index: linux-3.2.46/drivers/net/hyperv/netvsc_drv.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/hyperv/netvsc_drv.c 2013-07-26 19:18:41.000000000 +0000 ++++ linux-3.2.46/drivers/net/hyperv/netvsc_drv.c 2013-07-26 19:18:43.000000000 +0000 +@@ -68,11 +68,11 @@ nvdev = hv_get_drvdata(ndevctx->device_ctx); if (nvdev == NULL) @@ -34,7 +34,7 @@ if (net->flags & IFF_PROMISC) rndis_filter_set_packet_filter(rdev, -@@ -83,6 +83,7 @@ static void do_set_multicast(struct work_struct *w) +@@ -83,6 +83,7 @@ NDIS_PACKET_TYPE_ALL_MULTICAST | NDIS_PACKET_TYPE_DIRECTED); @@ -42,6 +42,3 @@ kfree(w); } --- -1.7.9.5 - diff -Nru linux-3.2.46/debian/patches/features/x86/hyperv/0037-drivers-hv-Get-rid-of-some-unnecessary-code.patch linux-3.2.46/debian/patches/features/x86/hyperv/0037-drivers-hv-Get-rid-of-some-unnecessary-code.patch --- linux-3.2.46/debian/patches/features/x86/hyperv/0037-drivers-hv-Get-rid-of-some-unnecessary-code.patch 2013-02-24 03:52:26.000000000 +0000 +++ linux-3.2.46/debian/patches/features/x86/hyperv/0037-drivers-hv-Get-rid-of-some-unnecessary-code.patch 2013-07-26 19:18:45.000000000 +0000 @@ -15,11 +15,11 @@ drivers/hv/channel_mgmt.c | 87 --------------------------------------------- 1 file changed, 87 deletions(-) -diff --git a/drivers/hv/channel_mgmt.c b/drivers/hv/channel_mgmt.c -index 36484db..9ffbfc5 100644 ---- a/drivers/hv/channel_mgmt.c -+++ b/drivers/hv/channel_mgmt.c -@@ -37,81 +37,6 @@ struct vmbus_channel_message_table_entry { +Index: linux-3.2.46/drivers/hv/channel_mgmt.c +=================================================================== +--- linux-3.2.46.orig/drivers/hv/channel_mgmt.c 2013-07-26 19:18:35.000000000 +0000 ++++ linux-3.2.46/drivers/hv/channel_mgmt.c 2013-07-26 19:18:44.000000000 +0000 +@@ -37,81 +37,6 @@ void (*message_handler)(struct vmbus_channel_message_header *msg); }; @@ -101,7 +101,7 @@ /** * vmbus_prep_negotiate_resp() - Create default response for Hyper-V Negotiate message -@@ -321,20 +246,8 @@ static void vmbus_onoffer(struct vmbus_channel_message_header *hdr) +@@ -321,20 +246,8 @@ struct vmbus_channel *newchannel; uuid_le *guidtype; uuid_le *guidinstance; @@ -122,6 +122,3 @@ guidtype = &offer->offer.if_type; guidinstance = &offer->offer.if_instance; --- -1.7.9.5 - diff -Nru linux-3.2.46/debian/patches/features/x86/hyperv/0038-net-hyperv-rx_bytes-should-account-the-ether-header-.patch linux-3.2.46/debian/patches/features/x86/hyperv/0038-net-hyperv-rx_bytes-should-account-the-ether-header-.patch --- linux-3.2.46/debian/patches/features/x86/hyperv/0038-net-hyperv-rx_bytes-should-account-the-ether-header-.patch 2013-02-24 03:52:26.000000000 +0000 +++ linux-3.2.46/debian/patches/features/x86/hyperv/0038-net-hyperv-rx_bytes-should-account-the-ether-header-.patch 2013-07-26 19:18:46.000000000 +0000 @@ -14,11 +14,11 @@ drivers/net/hyperv/netvsc_drv.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -diff --git a/drivers/net/hyperv/netvsc_drv.c b/drivers/net/hyperv/netvsc_drv.c -index 1a1ca6c..9dccc7a 100644 ---- a/drivers/net/hyperv/netvsc_drv.c -+++ b/drivers/net/hyperv/netvsc_drv.c -@@ -298,7 +298,7 @@ int netvsc_recv_callback(struct hv_device *device_obj, +Index: linux-3.2.46/drivers/net/hyperv/netvsc_drv.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/hyperv/netvsc_drv.c 2013-07-26 19:18:43.000000000 +0000 ++++ linux-3.2.46/drivers/net/hyperv/netvsc_drv.c 2013-07-26 19:18:45.000000000 +0000 +@@ -298,7 +298,7 @@ skb->ip_summed = CHECKSUM_NONE; net->stats.rx_packets++; @@ -27,6 +27,3 @@ /* * Pass the skb back up. Network stack will deallocate the skb when it --- -1.7.9.5 - diff -Nru linux-3.2.46/debian/patches/features/x86/hyperv/0039-HID-hyperv-Properly-disconnect-the-input-device.patch linux-3.2.46/debian/patches/features/x86/hyperv/0039-HID-hyperv-Properly-disconnect-the-input-device.patch --- linux-3.2.46/debian/patches/features/x86/hyperv/0039-HID-hyperv-Properly-disconnect-the-input-device.patch 2013-02-24 03:52:26.000000000 +0000 +++ linux-3.2.46/debian/patches/features/x86/hyperv/0039-HID-hyperv-Properly-disconnect-the-input-device.patch 2013-07-26 19:18:47.000000000 +0000 @@ -15,11 +15,11 @@ drivers/hid/hid-hyperv.c | 1 + 1 file changed, 1 insertion(+) -diff --git a/drivers/hid/hid-hyperv.c b/drivers/hid/hid-hyperv.c -index 0c33ae9..4066324 100644 ---- a/drivers/hid/hid-hyperv.c -+++ b/drivers/hid/hid-hyperv.c -@@ -548,6 +548,7 @@ static int mousevsc_remove(struct hv_device *dev) +Index: linux-3.2.46/drivers/hid/hid-hyperv.c +=================================================================== +--- linux-3.2.46.orig/drivers/hid/hid-hyperv.c 2013-07-26 19:18:30.000000000 +0000 ++++ linux-3.2.46/drivers/hid/hid-hyperv.c 2013-07-26 19:18:46.000000000 +0000 +@@ -548,6 +548,7 @@ struct mousevsc_dev *input_dev = hv_get_drvdata(dev); vmbus_close(dev->channel); @@ -27,6 +27,3 @@ hid_destroy_device(input_dev->hid_device); mousevsc_free_device(input_dev); --- -1.7.9.5 - diff -Nru linux-3.2.46/debian/patches/features/x86/hyperv/0040-net-hyperv-fix-the-issue-that-large-packets-be-dropp.patch linux-3.2.46/debian/patches/features/x86/hyperv/0040-net-hyperv-fix-the-issue-that-large-packets-be-dropp.patch --- linux-3.2.46/debian/patches/features/x86/hyperv/0040-net-hyperv-fix-the-issue-that-large-packets-be-dropp.patch 2013-02-24 03:52:26.000000000 +0000 +++ linux-3.2.46/debian/patches/features/x86/hyperv/0040-net-hyperv-fix-the-issue-that-large-packets-be-dropp.patch 2013-07-26 19:18:49.000000000 +0000 @@ -33,11 +33,11 @@ drivers/net/hyperv/rndis_filter.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) -diff --git a/drivers/net/hyperv/rndis_filter.c b/drivers/net/hyperv/rndis_filter.c -index da181f9..dc2e384 100644 ---- a/drivers/net/hyperv/rndis_filter.c -+++ b/drivers/net/hyperv/rndis_filter.c -@@ -321,6 +321,25 @@ static void rndis_filter_receive_data(struct rndis_device *dev, +Index: linux-3.2.46/drivers/net/hyperv/rndis_filter.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/hyperv/rndis_filter.c 2013-07-26 19:18:38.000000000 +0000 ++++ linux-3.2.46/drivers/net/hyperv/rndis_filter.c 2013-07-26 19:18:48.000000000 +0000 +@@ -321,6 +321,25 @@ data_offset = RNDIS_HEADER_SIZE + rndis_pkt->data_offset; pkt->total_data_buflen -= data_offset; @@ -63,6 +63,3 @@ pkt->data = (void *)((unsigned long)pkt->data + data_offset); pkt->is_data_pkt = true; --- -1.7.9.5 - diff -Nru linux-3.2.46/debian/patches/features/x86/hyperv/0041-net-hyperv-Use-netif_tx_disable-instead-of-netif_sto.patch linux-3.2.46/debian/patches/features/x86/hyperv/0041-net-hyperv-Use-netif_tx_disable-instead-of-netif_sto.patch --- linux-3.2.46/debian/patches/features/x86/hyperv/0041-net-hyperv-Use-netif_tx_disable-instead-of-netif_sto.patch 2013-02-24 03:52:26.000000000 +0000 +++ linux-3.2.46/debian/patches/features/x86/hyperv/0041-net-hyperv-Use-netif_tx_disable-instead-of-netif_sto.patch 2013-07-26 19:18:50.000000000 +0000 @@ -15,11 +15,11 @@ drivers/net/hyperv/netvsc_drv.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) -diff --git a/drivers/net/hyperv/netvsc_drv.c b/drivers/net/hyperv/netvsc_drv.c -index 9dccc7a..69193fc 100644 ---- a/drivers/net/hyperv/netvsc_drv.c -+++ b/drivers/net/hyperv/netvsc_drv.c -@@ -123,7 +123,7 @@ static int netvsc_close(struct net_device *net) +Index: linux-3.2.46/drivers/net/hyperv/netvsc_drv.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/hyperv/netvsc_drv.c 2013-07-26 19:18:45.000000000 +0000 ++++ linux-3.2.46/drivers/net/hyperv/netvsc_drv.c 2013-07-26 19:18:49.000000000 +0000 +@@ -123,7 +123,7 @@ struct hv_device *device_obj = net_device_ctx->device_ctx; int ret; @@ -28,7 +28,7 @@ ret = rndis_filter_close(device_obj); if (ret != 0) -@@ -256,7 +256,7 @@ void netvsc_linkstatus_callback(struct hv_device *device_obj, +@@ -256,7 +256,7 @@ schedule_delayed_work(&ndev_ctx->dwork, msecs_to_jiffies(20)); } else { netif_carrier_off(net); @@ -37,7 +37,7 @@ } } -@@ -337,7 +337,7 @@ static int netvsc_change_mtu(struct net_device *ndev, int mtu) +@@ -337,7 +337,7 @@ nvdev->start_remove = true; cancel_delayed_work_sync(&ndevctx->dwork); @@ -46,7 +46,7 @@ rndis_filter_device_remove(hdev); ndev->mtu = mtu; -@@ -460,7 +460,7 @@ static int netvsc_remove(struct hv_device *dev) +@@ -460,7 +460,7 @@ cancel_delayed_work_sync(&ndev_ctx->dwork); /* Stop outbound asap */ @@ -55,6 +55,3 @@ unregister_netdev(net); --- -1.7.9.5 - diff -Nru linux-3.2.46/debian/patches/features/x86/hyperv/0042-net-hyperv-Fix-the-page-buffer-when-an-RNDIS-message.patch linux-3.2.46/debian/patches/features/x86/hyperv/0042-net-hyperv-Fix-the-page-buffer-when-an-RNDIS-message.patch --- linux-3.2.46/debian/patches/features/x86/hyperv/0042-net-hyperv-Fix-the-page-buffer-when-an-RNDIS-message.patch 2013-02-24 03:52:26.000000000 +0000 +++ linux-3.2.46/debian/patches/features/x86/hyperv/0042-net-hyperv-Fix-the-page-buffer-when-an-RNDIS-message.patch 2013-07-26 19:18:51.000000000 +0000 @@ -17,11 +17,11 @@ include/linux/hyperv.h | 2 +- 3 files changed, 18 insertions(+), 5 deletions(-) -diff --git a/drivers/net/hyperv/netvsc_drv.c b/drivers/net/hyperv/netvsc_drv.c -index 69193fc..466c58a 100644 ---- a/drivers/net/hyperv/netvsc_drv.c -+++ b/drivers/net/hyperv/netvsc_drv.c -@@ -151,10 +151,10 @@ static int netvsc_start_xmit(struct sk_buff *skb, struct net_device *net) +Index: linux-3.2.46/drivers/net/hyperv/netvsc_drv.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/hyperv/netvsc_drv.c 2013-07-26 19:18:49.000000000 +0000 ++++ linux-3.2.46/drivers/net/hyperv/netvsc_drv.c 2013-07-26 19:18:50.000000000 +0000 +@@ -151,10 +151,10 @@ int ret; unsigned int i, num_pages, npg_data; @@ -34,7 +34,7 @@ /* Allocate a netvsc packet based on # of frags. */ packet = kzalloc(sizeof(struct hv_netvsc_packet) + -@@ -173,8 +173,8 @@ static int netvsc_start_xmit(struct sk_buff *skb, struct net_device *net) +@@ -173,8 +173,8 @@ sizeof(struct hv_netvsc_packet) + (num_pages * sizeof(struct hv_page_buffer)); @@ -45,11 +45,11 @@ /* Initialize it from the skb */ packet->total_data_buflen = skb->len; -diff --git a/drivers/net/hyperv/rndis_filter.c b/drivers/net/hyperv/rndis_filter.c -index dc2e384..133b7fb 100644 ---- a/drivers/net/hyperv/rndis_filter.c -+++ b/drivers/net/hyperv/rndis_filter.c -@@ -797,6 +797,19 @@ int rndis_filter_send(struct hv_device *dev, +Index: linux-3.2.46/drivers/net/hyperv/rndis_filter.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/hyperv/rndis_filter.c 2013-07-26 19:18:48.000000000 +0000 ++++ linux-3.2.46/drivers/net/hyperv/rndis_filter.c 2013-07-26 19:18:50.000000000 +0000 +@@ -797,6 +797,19 @@ (unsigned long)rndisMessage & (PAGE_SIZE-1); pkt->page_buf[0].len = rndisMessageSize; @@ -69,10 +69,10 @@ /* Save the packet send completion and context */ filterPacket->completion = pkt->completion.send.send_completion; filterPacket->completion_ctx = -diff --git a/include/linux/hyperv.h b/include/linux/hyperv.h -index 62b908e..0ae065a 100644 ---- a/include/linux/hyperv.h -+++ b/include/linux/hyperv.h +Index: linux-3.2.46/include/linux/hyperv.h +=================================================================== +--- linux-3.2.46.orig/include/linux/hyperv.h 2013-07-26 19:18:41.000000000 +0000 ++++ linux-3.2.46/include/linux/hyperv.h 2013-07-26 19:18:50.000000000 +0000 @@ -35,7 +35,7 @@ #include @@ -82,6 +82,3 @@ #define MAX_MULTIPAGE_BUFFER_COUNT 32 /* 128K */ #pragma pack(push, 1) --- -1.7.9.5 - diff -Nru linux-3.2.46/debian/patches/features/x86/hyperv/0043-drivers-hv-kvp-Add-cleanup-connector-defines.patch linux-3.2.46/debian/patches/features/x86/hyperv/0043-drivers-hv-kvp-Add-cleanup-connector-defines.patch --- linux-3.2.46/debian/patches/features/x86/hyperv/0043-drivers-hv-kvp-Add-cleanup-connector-defines.patch 2013-02-24 03:52:26.000000000 +0000 +++ linux-3.2.46/debian/patches/features/x86/hyperv/0043-drivers-hv-kvp-Add-cleanup-connector-defines.patch 2013-07-26 19:18:53.000000000 +0000 @@ -17,10 +17,10 @@ tools/hv/hv_kvp_daemon.c | 4 ---- 3 files changed, 1 insertion(+), 7 deletions(-) -diff --git a/drivers/hv/hv_kvp.h b/drivers/hv/hv_kvp.h -index 9b765d7..c2c5bba 100644 ---- a/drivers/hv/hv_kvp.h -+++ b/drivers/hv/hv_kvp.h +Index: linux-3.2.46/drivers/hv/hv_kvp.h +=================================================================== +--- linux-3.2.46.orig/drivers/hv/hv_kvp.h 2013-07-26 18:56:04.000000000 +0000 ++++ linux-3.2.46/drivers/hv/hv_kvp.h 2013-07-26 19:18:51.000000000 +0000 @@ -107,9 +107,6 @@ * the KVP user-mode component. */ @@ -31,10 +31,10 @@ enum hv_ku_op { KVP_REGISTER = 0, /* Register the user mode component */ KVP_KERNEL_GET, /* Kernel is requesting the value */ -diff --git a/include/linux/connector.h b/include/linux/connector.h -index 3c9c54f..7638407 100644 ---- a/include/linux/connector.h -+++ b/include/linux/connector.h +Index: linux-3.2.46/include/linux/connector.h +=================================================================== +--- linux-3.2.46.orig/include/linux/connector.h 2013-07-26 18:56:04.000000000 +0000 ++++ linux-3.2.46/include/linux/connector.h 2013-07-26 19:18:52.000000000 +0000 @@ -43,6 +43,7 @@ #define CN_IDX_DRBD 0x8 #define CN_VAL_DRBD 0x1 @@ -43,10 +43,10 @@ #define CN_NETLINK_USERS 10 /* Highest index + 1 */ -diff --git a/tools/hv/hv_kvp_daemon.c b/tools/hv/hv_kvp_daemon.c -index 11224ed..2b6a2d9 100644 ---- a/tools/hv/hv_kvp_daemon.c -+++ b/tools/hv/hv_kvp_daemon.c +Index: linux-3.2.46/tools/hv/hv_kvp_daemon.c +=================================================================== +--- linux-3.2.46.orig/tools/hv/hv_kvp_daemon.c 2013-07-26 18:56:04.000000000 +0000 ++++ linux-3.2.46/tools/hv/hv_kvp_daemon.c 2013-07-26 19:18:52.000000000 +0000 @@ -40,15 +40,11 @@ #include @@ -63,6 +63,3 @@ /* * KVP protocol: The user mode component first registers with the --- -1.7.9.5 - diff -Nru linux-3.2.46/debian/patches/features/x86/hyperv/0044-drivers-hv-kvp-Move-the-contents-of-hv_kvp.h-to-hype.patch linux-3.2.46/debian/patches/features/x86/hyperv/0044-drivers-hv-kvp-Move-the-contents-of-hv_kvp.h-to-hype.patch --- linux-3.2.46/debian/patches/features/x86/hyperv/0044-drivers-hv-kvp-Move-the-contents-of-hv_kvp.h-to-hype.patch 2013-02-24 03:52:26.000000000 +0000 +++ linux-3.2.46/debian/patches/features/x86/hyperv/0044-drivers-hv-kvp-Move-the-contents-of-hv_kvp.h-to-hype.patch 2013-07-26 19:18:54.000000000 +0000 @@ -20,10 +20,10 @@ 4 files changed, 165 insertions(+), 186 deletions(-) delete mode 100644 drivers/hv/hv_kvp.h -diff --git a/drivers/hv/hv_kvp.c b/drivers/hv/hv_kvp.c -index 0e8343f..4a6971e 100644 ---- a/drivers/hv/hv_kvp.c -+++ b/drivers/hv/hv_kvp.c +Index: linux-3.2.46/drivers/hv/hv_kvp.c +=================================================================== +--- linux-3.2.46.orig/drivers/hv/hv_kvp.c 2013-07-26 18:56:04.000000000 +0000 ++++ linux-3.2.46/drivers/hv/hv_kvp.c 2013-07-26 19:18:53.000000000 +0000 @@ -28,8 +28,6 @@ #include #include @@ -33,11 +33,10 @@ /* -diff --git a/drivers/hv/hv_kvp.h b/drivers/hv/hv_kvp.h -deleted file mode 100644 -index c2c5bba..0000000 ---- a/drivers/hv/hv_kvp.h -+++ /dev/null +Index: linux-3.2.46/drivers/hv/hv_kvp.h +=================================================================== +--- linux-3.2.46.orig/drivers/hv/hv_kvp.h 2013-07-26 19:18:51.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 @@ -1,181 +0,0 @@ -/* - * An implementation of HyperV key value pair (KVP) functionality for Linux. @@ -220,10 +219,10 @@ -#endif /* __KERNEL__ */ -#endif /* _KVP_H */ - -diff --git a/drivers/hv/hv_util.c b/drivers/hv/hv_util.c -index 55d58f2..dbb8b8e 100644 ---- a/drivers/hv/hv_util.c -+++ b/drivers/hv/hv_util.c +Index: linux-3.2.46/drivers/hv/hv_util.c +=================================================================== +--- linux-3.2.46.orig/drivers/hv/hv_util.c 2013-07-26 18:56:04.000000000 +0000 ++++ linux-3.2.46/drivers/hv/hv_util.c 2013-07-26 19:18:53.000000000 +0000 @@ -28,9 +28,6 @@ #include #include @@ -234,10 +233,10 @@ static void shutdown_onchannelcallback(void *context); static struct hv_util_service util_shutdown = { .util_cb = shutdown_onchannelcallback, -diff --git a/include/linux/hyperv.h b/include/linux/hyperv.h -index 0ae065a..c445ead 100644 ---- a/include/linux/hyperv.h -+++ b/include/linux/hyperv.h +Index: linux-3.2.46/include/linux/hyperv.h +=================================================================== +--- linux-3.2.46.orig/include/linux/hyperv.h 2013-07-26 19:18:50.000000000 +0000 ++++ linux-3.2.46/include/linux/hyperv.h 2013-07-26 19:18:53.000000000 +0000 @@ -25,6 +25,166 @@ #ifndef _HYPERV_H #define _HYPERV_H @@ -405,7 +404,7 @@ #include #include #include -@@ -870,4 +1030,9 @@ struct hyperv_service_callback { +@@ -870,4 +1030,9 @@ extern void vmbus_prep_negotiate_resp(struct icmsg_hdr *, struct icmsg_negotiate *, u8 *); @@ -415,6 +414,3 @@ + +#endif /* __KERNEL__ */ #endif /* _HYPERV_H */ --- -1.7.9.5 - diff -Nru linux-3.2.46/debian/patches/features/x86/hyperv/0045-net-hyperv-Convert-camel-cased-variables-in-rndis_fi.patch linux-3.2.46/debian/patches/features/x86/hyperv/0045-net-hyperv-Convert-camel-cased-variables-in-rndis_fi.patch --- linux-3.2.46/debian/patches/features/x86/hyperv/0045-net-hyperv-Convert-camel-cased-variables-in-rndis_fi.patch 2013-02-24 03:52:26.000000000 +0000 +++ linux-3.2.46/debian/patches/features/x86/hyperv/0045-net-hyperv-Convert-camel-cased-variables-in-rndis_fi.patch 2013-07-26 19:18:55.000000000 +0000 @@ -13,11 +13,11 @@ drivers/net/hyperv/rndis_filter.c | 60 ++++++++++++++++++------------------- 1 file changed, 30 insertions(+), 30 deletions(-) -diff --git a/drivers/net/hyperv/rndis_filter.c b/drivers/net/hyperv/rndis_filter.c -index 133b7fb..a60e5e2 100644 ---- a/drivers/net/hyperv/rndis_filter.c -+++ b/drivers/net/hyperv/rndis_filter.c -@@ -758,66 +758,66 @@ int rndis_filter_open(struct hv_device *dev) +Index: linux-3.2.46/drivers/net/hyperv/rndis_filter.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/hyperv/rndis_filter.c 2013-07-26 19:18:50.000000000 +0000 ++++ linux-3.2.46/drivers/net/hyperv/rndis_filter.c 2013-07-26 19:18:54.000000000 +0000 +@@ -758,66 +758,66 @@ int rndis_filter_close(struct hv_device *dev) { @@ -110,7 +110,7 @@ ret = netvsc_send(dev, pkt); if (ret != 0) { -@@ -826,9 +826,9 @@ int rndis_filter_send(struct hv_device *dev, +@@ -826,9 +826,9 @@ * above */ pkt->completion.send.send_completion = @@ -122,7 +122,7 @@ } return ret; -@@ -836,10 +836,10 @@ int rndis_filter_send(struct hv_device *dev, +@@ -836,10 +836,10 @@ static void rndis_filter_send_completion(void *ctx) { @@ -135,6 +135,3 @@ } --- -1.7.9.5 - diff -Nru linux-3.2.46/debian/patches/features/x86/hyperv/0046-net-hyperv-Correct-the-assignment-in-netvsc_recv_cal.patch linux-3.2.46/debian/patches/features/x86/hyperv/0046-net-hyperv-Correct-the-assignment-in-netvsc_recv_cal.patch --- linux-3.2.46/debian/patches/features/x86/hyperv/0046-net-hyperv-Correct-the-assignment-in-netvsc_recv_cal.patch 2013-02-24 03:52:26.000000000 +0000 +++ linux-3.2.46/debian/patches/features/x86/hyperv/0046-net-hyperv-Correct-the-assignment-in-netvsc_recv_cal.patch 2013-07-26 19:18:57.000000000 +0000 @@ -15,11 +15,11 @@ drivers/net/hyperv/netvsc_drv.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) -diff --git a/drivers/net/hyperv/netvsc_drv.c b/drivers/net/hyperv/netvsc_drv.c -index 466c58a..0ae7a1a 100644 ---- a/drivers/net/hyperv/netvsc_drv.c -+++ b/drivers/net/hyperv/netvsc_drv.c -@@ -267,13 +267,10 @@ void netvsc_linkstatus_callback(struct hv_device *device_obj, +Index: linux-3.2.46/drivers/net/hyperv/netvsc_drv.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/hyperv/netvsc_drv.c 2013-07-26 19:18:50.000000000 +0000 ++++ linux-3.2.46/drivers/net/hyperv/netvsc_drv.c 2013-07-26 19:18:56.000000000 +0000 +@@ -267,13 +267,10 @@ int netvsc_recv_callback(struct hv_device *device_obj, struct hv_netvsc_packet *packet) { @@ -35,6 +35,3 @@ if (!net) { netdev_err(net, "got receive callback but net device" " not initialized yet\n"); --- -1.7.9.5 - diff -Nru linux-3.2.46/debian/patches/features/x86/hyperv/0047-net-hyperv-Remove-the-unnecessary-memset-in-rndis_fi.patch linux-3.2.46/debian/patches/features/x86/hyperv/0047-net-hyperv-Remove-the-unnecessary-memset-in-rndis_fi.patch --- linux-3.2.46/debian/patches/features/x86/hyperv/0047-net-hyperv-Remove-the-unnecessary-memset-in-rndis_fi.patch 2013-02-24 03:52:26.000000000 +0000 +++ linux-3.2.46/debian/patches/features/x86/hyperv/0047-net-hyperv-Remove-the-unnecessary-memset-in-rndis_fi.patch 2013-07-26 19:18:58.000000000 +0000 @@ -15,11 +15,11 @@ drivers/net/hyperv/rndis_filter.c | 2 -- 1 file changed, 2 deletions(-) -diff --git a/drivers/net/hyperv/rndis_filter.c b/drivers/net/hyperv/rndis_filter.c -index a60e5e2..136efd8 100644 ---- a/drivers/net/hyperv/rndis_filter.c -+++ b/drivers/net/hyperv/rndis_filter.c -@@ -778,8 +778,6 @@ int rndis_filter_send(struct hv_device *dev, +Index: linux-3.2.46/drivers/net/hyperv/rndis_filter.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/hyperv/rndis_filter.c 2013-07-26 19:18:54.000000000 +0000 ++++ linux-3.2.46/drivers/net/hyperv/rndis_filter.c 2013-07-26 19:18:57.000000000 +0000 +@@ -778,8 +778,6 @@ /* Add the rndis header */ filter_pkt = (struct rndis_filter_packet *)pkt->extension; @@ -28,6 +28,3 @@ rndis_msg = &filter_pkt->msg; rndis_msg_size = RNDIS_MESSAGE_SIZE(struct rndis_packet); --- -1.7.9.5 - diff -Nru linux-3.2.46/debian/patches/features/x86/hyperv/0048-Staging-hv-storvsc-Cleanup-some-comments.patch linux-3.2.46/debian/patches/features/x86/hyperv/0048-Staging-hv-storvsc-Cleanup-some-comments.patch --- linux-3.2.46/debian/patches/features/x86/hyperv/0048-Staging-hv-storvsc-Cleanup-some-comments.patch 2013-02-24 03:52:26.000000000 +0000 +++ linux-3.2.46/debian/patches/features/x86/hyperv/0048-Staging-hv-storvsc-Cleanup-some-comments.patch 2013-07-26 19:18:59.000000000 +0000 @@ -13,11 +13,11 @@ drivers/staging/hv/storvsc_drv.c | 57 +++++++++++++++++--------------------- 1 file changed, 26 insertions(+), 31 deletions(-) -diff --git a/drivers/staging/hv/storvsc_drv.c b/drivers/staging/hv/storvsc_drv.c -index eb853f7..1633b03 100644 ---- a/drivers/staging/hv/storvsc_drv.c -+++ b/drivers/staging/hv/storvsc_drv.c -@@ -50,8 +50,10 @@ static int storvsc_ringbuffer_size = STORVSC_RING_BUFFER_SIZE; +Index: linux-3.2.46/drivers/staging/hv/storvsc_drv.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/hv/storvsc_drv.c 2013-07-26 19:18:31.000000000 +0000 ++++ linux-3.2.46/drivers/staging/hv/storvsc_drv.c 2013-07-26 19:18:58.000000000 +0000 +@@ -50,8 +50,10 @@ module_param(storvsc_ringbuffer_size, int, S_IRUGO); MODULE_PARM_DESC(storvsc_ringbuffer_size, "Ring buffer size (bytes)"); @@ -30,7 +30,7 @@ #define REVISION_STRING(REVISION_) #REVISION_ -@@ -68,26 +70,36 @@ MODULE_PARM_DESC(storvsc_ringbuffer_size, "Ring buffer size (bytes)"); +@@ -68,26 +70,36 @@ } \ } while (0) @@ -76,7 +76,7 @@ #define MAX_TRANSFER_LENGTH 0x40000 #define DEFAULT_PACKET_SIZE (sizeof(struct vmdata_gpa_direct) + \ sizeof(struct vstor_packet) + \ -@@ -211,18 +223,19 @@ struct vstor_packet { +@@ -211,18 +223,19 @@ }; } __packed; @@ -98,7 +98,7 @@ #define STORVSC_MAX_IO_REQUESTS 128 -@@ -674,7 +687,6 @@ static int storvsc_connect_to_vsp(struct hv_device *device, u32 ring_size) +@@ -674,7 +687,6 @@ memset(&props, 0, sizeof(struct vmstorage_channel_properties)); @@ -106,7 +106,7 @@ ret = vmbus_open(device->channel, ring_size, ring_size, -@@ -1154,9 +1166,6 @@ static int storvsc_host_reset(struct hv_device *device) +@@ -1160,9 +1172,6 @@ } @@ -116,7 +116,7 @@ static int storvsc_host_reset_handler(struct scsi_cmnd *scmnd) { struct hv_host_device *host_dev = shost_priv(scmnd->device->host); -@@ -1166,9 +1175,6 @@ static int storvsc_host_reset_handler(struct scsi_cmnd *scmnd) +@@ -1172,9 +1181,6 @@ } @@ -126,7 +126,7 @@ static void storvsc_command_completion(struct hv_storvsc_request *request) { struct storvsc_cmd_request *cmd_request = -@@ -1262,9 +1268,6 @@ static bool storvsc_check_scsi_cmd(struct scsi_cmnd *scmnd) +@@ -1268,9 +1274,6 @@ return allowed; } @@ -136,7 +136,7 @@ static int storvsc_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *scmnd) { int ret; -@@ -1407,7 +1410,6 @@ retry_request: +@@ -1413,7 +1416,6 @@ return ret; } @@ -144,7 +144,7 @@ static struct scsi_host_template scsi_driver = { .module = THIS_MODULE, .name = "storvsc_host_t", -@@ -1448,11 +1450,6 @@ static const struct hv_vmbus_device_id id_table[] = { +@@ -1454,11 +1456,6 @@ MODULE_DEVICE_TABLE(vmbus, id_table); @@ -156,7 +156,7 @@ static int storvsc_probe(struct hv_device *device, const struct hv_vmbus_device_id *dev_id) { -@@ -1542,8 +1539,6 @@ err_out0: +@@ -1548,8 +1545,6 @@ return ret; } @@ -165,6 +165,3 @@ static struct hv_driver storvsc_drv = { .name = KBUILD_MODNAME, .id_table = id_table, --- -1.7.9.5 - diff -Nru linux-3.2.46/debian/patches/features/x86/hyperv/0049-Staging-hv-storvsc-Cleanup-storvsc_probe.patch linux-3.2.46/debian/patches/features/x86/hyperv/0049-Staging-hv-storvsc-Cleanup-storvsc_probe.patch --- linux-3.2.46/debian/patches/features/x86/hyperv/0049-Staging-hv-storvsc-Cleanup-storvsc_probe.patch 2013-02-24 03:52:26.000000000 +0000 +++ linux-3.2.46/debian/patches/features/x86/hyperv/0049-Staging-hv-storvsc-Cleanup-storvsc_probe.patch 2013-07-26 19:19:00.000000000 +0000 @@ -13,11 +13,11 @@ drivers/staging/hv/storvsc_drv.c | 30 ++++++++---------------------- 1 file changed, 8 insertions(+), 22 deletions(-) -diff --git a/drivers/staging/hv/storvsc_drv.c b/drivers/staging/hv/storvsc_drv.c -index 1633b03..7561d29 100644 ---- a/drivers/staging/hv/storvsc_drv.c -+++ b/drivers/staging/hv/storvsc_drv.c -@@ -791,18 +791,6 @@ static int storvsc_do_io(struct hv_device *device, +Index: linux-3.2.46/drivers/staging/hv/storvsc_drv.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/hv/storvsc_drv.c 2013-07-26 19:18:58.000000000 +0000 ++++ linux-3.2.46/drivers/staging/hv/storvsc_drv.c 2013-07-26 19:18:59.000000000 +0000 +@@ -791,18 +791,6 @@ return ret; } @@ -36,7 +36,7 @@ static int storvsc_device_alloc(struct scsi_device *sdevice) { struct stor_mem_pools *memp; -@@ -1457,7 +1445,6 @@ static int storvsc_probe(struct hv_device *device, +@@ -1463,7 +1451,6 @@ struct Scsi_Host *host; struct hv_host_device *host_dev; bool dev_is_ide = ((dev_id->driver_data == IDE_GUID) ? true : false); @@ -44,7 +44,7 @@ int target = 0; struct storvsc_device *stor_device; -@@ -1490,9 +1477,6 @@ static int storvsc_probe(struct hv_device *device, +@@ -1496,9 +1483,6 @@ if (ret) goto err_out1; @@ -54,7 +54,7 @@ host_dev->path = stor_device->path_id; host_dev->target = stor_device->target_id; -@@ -1512,12 +1496,14 @@ static int storvsc_probe(struct hv_device *device, +@@ -1518,12 +1502,14 @@ if (!dev_is_ide) { scsi_scan_host(host); @@ -75,6 +75,3 @@ } return 0; --- -1.7.9.5 - diff -Nru linux-3.2.46/debian/patches/features/x86/hyperv/0050-Staging-hv-storvsc-Cleanup-storvsc_queuecommand.patch linux-3.2.46/debian/patches/features/x86/hyperv/0050-Staging-hv-storvsc-Cleanup-storvsc_queuecommand.patch --- linux-3.2.46/debian/patches/features/x86/hyperv/0050-Staging-hv-storvsc-Cleanup-storvsc_queuecommand.patch 2013-02-24 03:52:26.000000000 +0000 +++ linux-3.2.46/debian/patches/features/x86/hyperv/0050-Staging-hv-storvsc-Cleanup-storvsc_queuecommand.patch 2013-07-26 19:19:02.000000000 +0000 @@ -14,11 +14,11 @@ drivers/staging/hv/storvsc_drv.c | 48 +++++++++++++++++--------------------- 1 file changed, 22 insertions(+), 26 deletions(-) -diff --git a/drivers/staging/hv/storvsc_drv.c b/drivers/staging/hv/storvsc_drv.c -index 7561d29..71e50c3 100644 ---- a/drivers/staging/hv/storvsc_drv.c -+++ b/drivers/staging/hv/storvsc_drv.c -@@ -1239,13 +1239,16 @@ static void storvsc_command_completion(struct hv_storvsc_request *request) +Index: linux-3.2.46/drivers/staging/hv/storvsc_drv.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/hv/storvsc_drv.c 2013-07-26 19:18:59.000000000 +0000 ++++ linux-3.2.46/drivers/staging/hv/storvsc_drv.c 2013-07-26 19:19:01.000000000 +0000 +@@ -1245,13 +1245,16 @@ mempool_free(cmd_request, memp->request_mempool); } @@ -37,7 +37,7 @@ case SET_WINDOW: scmnd->result = ILLEGAL_REQUEST << 16; allowed = false; -@@ -1270,32 +1273,26 @@ static int storvsc_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *scmnd) +@@ -1276,32 +1279,26 @@ struct vmscsi_request *vm_srb; struct stor_mem_pools *memp = scmnd->device->hostdata; @@ -76,7 +76,7 @@ cmd_request->cmd = scmnd; scmnd->host_scribble = (unsigned char *)cmd_request; -@@ -1344,11 +1341,8 @@ static int storvsc_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *scmnd) +@@ -1350,11 +1347,8 @@ scsi_bufflen(scmnd), vm_srb->data_in); if (!cmd_request->bounce_sgl) { @@ -90,7 +90,7 @@ } cmd_request->bounce_sgl_count = -@@ -1377,24 +1371,26 @@ static int storvsc_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *scmnd) +@@ -1383,24 +1377,26 @@ virt_to_phys(scsi_sglist(scmnd)) >> PAGE_SHIFT; } @@ -124,6 +124,3 @@ return ret; } --- -1.7.9.5 - diff -Nru linux-3.2.46/debian/patches/features/x86/hyperv/0051-Staging-hv-storvsc-Introduce-defines-for-srb-status-.patch linux-3.2.46/debian/patches/features/x86/hyperv/0051-Staging-hv-storvsc-Introduce-defines-for-srb-status-.patch --- linux-3.2.46/debian/patches/features/x86/hyperv/0051-Staging-hv-storvsc-Introduce-defines-for-srb-status-.patch 2013-02-24 03:52:26.000000000 +0000 +++ linux-3.2.46/debian/patches/features/x86/hyperv/0051-Staging-hv-storvsc-Introduce-defines-for-srb-status-.patch 2013-07-26 19:19:03.000000000 +0000 @@ -13,11 +13,11 @@ drivers/staging/hv/storvsc_drv.c | 21 ++++++++++++++++----- 1 file changed, 16 insertions(+), 5 deletions(-) -diff --git a/drivers/staging/hv/storvsc_drv.c b/drivers/staging/hv/storvsc_drv.c -index 71e50c3..979f25b 100644 ---- a/drivers/staging/hv/storvsc_drv.c -+++ b/drivers/staging/hv/storvsc_drv.c -@@ -257,6 +257,16 @@ enum storvsc_request_type { +Index: linux-3.2.46/drivers/staging/hv/storvsc_drv.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/hv/storvsc_drv.c 2013-07-26 19:19:01.000000000 +0000 ++++ linux-3.2.46/drivers/staging/hv/storvsc_drv.c 2013-07-26 19:19:02.000000000 +0000 +@@ -257,6 +257,16 @@ UNKNOWN_TYPE, }; @@ -34,7 +34,7 @@ struct hv_storvsc_request { struct hv_device *device; -@@ -561,7 +571,7 @@ static void storvsc_on_io_completion(struct hv_device *device, +@@ -561,7 +571,7 @@ if ((stor_pkt->vm_srb.cdb[0] == INQUIRY) || (stor_pkt->vm_srb.cdb[0] == MODE_SENSE)) { vstor_packet->vm_srb.scsi_status = 0; @@ -43,7 +43,7 @@ } -@@ -572,7 +582,7 @@ static void storvsc_on_io_completion(struct hv_device *device, +@@ -572,7 +582,7 @@ vstor_packet->vm_srb.sense_info_length; if (vstor_packet->vm_srb.scsi_status != 0 || @@ -52,7 +52,7 @@ dev_warn(&device->device, "cmd 0x%x scsi status 0x%x srb status 0x%x\n", stor_pkt->vm_srb.cdb[0], -@@ -582,7 +592,8 @@ static void storvsc_on_io_completion(struct hv_device *device, +@@ -582,7 +592,8 @@ if ((vstor_packet->vm_srb.scsi_status & 0xFF) == 0x02) { /* CHECK_CONDITION */ @@ -62,7 +62,7 @@ /* autosense data available */ dev_warn(&device->device, "stor pkt %p autosense data valid - len %d\n", -@@ -1191,7 +1202,7 @@ static void storvsc_command_completion(struct hv_storvsc_request *request) +@@ -1197,7 +1208,7 @@ * error recovery strategies would have already been * deployed on the host side. */ @@ -71,7 +71,7 @@ scmnd->result = DID_TARGET_FAILURE << 16; else scmnd->result = vm_srb->scsi_status; -@@ -1199,7 +1210,7 @@ static void storvsc_command_completion(struct hv_storvsc_request *request) +@@ -1205,7 +1216,7 @@ /* * If the LUN is invalid; remove the device. */ @@ -80,6 +80,3 @@ struct storvsc_device *stor_dev; struct hv_device *dev = host_dev->dev; struct Scsi_Host *host; --- -1.7.9.5 - diff -Nru linux-3.2.46/debian/patches/features/x86/hyperv/0052-Staging-hv-storvsc-Cleanup-storvsc_host_reset_handle.patch linux-3.2.46/debian/patches/features/x86/hyperv/0052-Staging-hv-storvsc-Cleanup-storvsc_host_reset_handle.patch --- linux-3.2.46/debian/patches/features/x86/hyperv/0052-Staging-hv-storvsc-Cleanup-storvsc_host_reset_handle.patch 2013-02-24 03:52:26.000000000 +0000 +++ linux-3.2.46/debian/patches/features/x86/hyperv/0052-Staging-hv-storvsc-Cleanup-storvsc_host_reset_handle.patch 2013-07-26 19:19:04.000000000 +0000 @@ -13,11 +13,11 @@ drivers/staging/hv/storvsc_drv.c | 14 ++++---------- 1 file changed, 4 insertions(+), 10 deletions(-) -diff --git a/drivers/staging/hv/storvsc_drv.c b/drivers/staging/hv/storvsc_drv.c -index 979f25b..8340387 100644 ---- a/drivers/staging/hv/storvsc_drv.c -+++ b/drivers/staging/hv/storvsc_drv.c -@@ -1122,8 +1122,11 @@ static int storvsc_get_chs(struct scsi_device *sdev, struct block_device * bdev, +Index: linux-3.2.46/drivers/staging/hv/storvsc_drv.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/hv/storvsc_drv.c 2013-07-26 19:19:02.000000000 +0000 ++++ linux-3.2.46/drivers/staging/hv/storvsc_drv.c 2013-07-26 19:19:03.000000000 +0000 +@@ -1123,8 +1123,11 @@ return 0; } @@ -30,7 +30,7 @@ struct storvsc_device *stor_device; struct hv_storvsc_request *request; struct vstor_packet *vstor_packet; -@@ -1165,15 +1168,6 @@ static int storvsc_host_reset(struct hv_device *device) +@@ -1171,15 +1174,6 @@ } @@ -46,6 +46,3 @@ static void storvsc_command_completion(struct hv_storvsc_request *request) { struct storvsc_cmd_request *cmd_request = --- -1.7.9.5 - diff -Nru linux-3.2.46/debian/patches/features/x86/hyperv/0053-Staging-hv-storvsc-Move-and-cleanup-storvsc_remove.patch linux-3.2.46/debian/patches/features/x86/hyperv/0053-Staging-hv-storvsc-Move-and-cleanup-storvsc_remove.patch --- linux-3.2.46/debian/patches/features/x86/hyperv/0053-Staging-hv-storvsc-Move-and-cleanup-storvsc_remove.patch 2013-02-24 03:52:26.000000000 +0000 +++ linux-3.2.46/debian/patches/features/x86/hyperv/0053-Staging-hv-storvsc-Move-and-cleanup-storvsc_remove.patch 2013-07-26 19:19:05.000000000 +0000 @@ -14,11 +14,11 @@ drivers/staging/hv/storvsc_drv.c | 28 ++++++++++++---------------- 1 file changed, 12 insertions(+), 16 deletions(-) -diff --git a/drivers/staging/hv/storvsc_drv.c b/drivers/staging/hv/storvsc_drv.c -index 8340387..e0e471c 100644 ---- a/drivers/staging/hv/storvsc_drv.c -+++ b/drivers/staging/hv/storvsc_drv.c -@@ -1083,22 +1083,6 @@ static unsigned int copy_to_bounce_buffer(struct scatterlist *orig_sgl, +Index: linux-3.2.46/drivers/staging/hv/storvsc_drv.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/hv/storvsc_drv.c 2013-07-26 19:19:03.000000000 +0000 ++++ linux-3.2.46/drivers/staging/hv/storvsc_drv.c 2013-07-26 19:19:04.000000000 +0000 +@@ -1084,22 +1084,6 @@ return total_copied; } @@ -41,7 +41,7 @@ static int storvsc_get_chs(struct scsi_device *sdev, struct block_device * bdev, sector_t capacity, int *info) { -@@ -1526,6 +1510,18 @@ err_out0: +@@ -1532,6 +1516,18 @@ return ret; } @@ -60,6 +60,3 @@ static struct hv_driver storvsc_drv = { .name = KBUILD_MODNAME, .id_table = id_table, --- -1.7.9.5 - diff -Nru linux-3.2.46/debian/patches/features/x86/hyperv/0054-Staging-hv-storvsc-Add-a-comment-to-explain-life-cyc.patch linux-3.2.46/debian/patches/features/x86/hyperv/0054-Staging-hv-storvsc-Add-a-comment-to-explain-life-cyc.patch --- linux-3.2.46/debian/patches/features/x86/hyperv/0054-Staging-hv-storvsc-Add-a-comment-to-explain-life-cyc.patch 2013-02-24 03:52:26.000000000 +0000 +++ linux-3.2.46/debian/patches/features/x86/hyperv/0054-Staging-hv-storvsc-Add-a-comment-to-explain-life-cyc.patch 2013-07-26 19:19:07.000000000 +0000 @@ -13,11 +13,11 @@ drivers/staging/hv/storvsc_drv.c | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) -diff --git a/drivers/staging/hv/storvsc_drv.c b/drivers/staging/hv/storvsc_drv.c -index e0e471c..204b3ca 100644 ---- a/drivers/staging/hv/storvsc_drv.c -+++ b/drivers/staging/hv/storvsc_drv.c -@@ -375,6 +375,21 @@ done: +Index: linux-3.2.46/drivers/staging/hv/storvsc_drv.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/hv/storvsc_drv.c 2013-07-26 19:19:04.000000000 +0000 ++++ linux-3.2.46/drivers/staging/hv/storvsc_drv.c 2013-07-26 19:19:06.000000000 +0000 +@@ -375,6 +375,21 @@ kfree(wrk); } @@ -39,7 +39,7 @@ static inline struct storvsc_device *get_out_stor_device( struct hv_device *device) { -@@ -569,7 +584,7 @@ static void storvsc_on_io_completion(struct hv_device *device, +@@ -569,7 +584,7 @@ */ if ((stor_pkt->vm_srb.cdb[0] == INQUIRY) || @@ -48,6 +48,3 @@ vstor_packet->vm_srb.scsi_status = 0; vstor_packet->vm_srb.srb_status = SRB_STATUS_SUCCESS; } --- -1.7.9.5 - diff -Nru linux-3.2.46/debian/patches/features/x86/hyperv/0055-Staging-hv-storvsc-Get-rid-of-the-on_io_completion-i.patch linux-3.2.46/debian/patches/features/x86/hyperv/0055-Staging-hv-storvsc-Get-rid-of-the-on_io_completion-i.patch --- linux-3.2.46/debian/patches/features/x86/hyperv/0055-Staging-hv-storvsc-Get-rid-of-the-on_io_completion-i.patch 2013-03-21 00:39:42.000000000 +0000 +++ linux-3.2.46/debian/patches/features/x86/hyperv/0055-Staging-hv-storvsc-Get-rid-of-the-on_io_completion-i.patch 2013-07-26 19:19:08.000000000 +0000 @@ -16,9 +16,11 @@ drivers/staging/hv/storvsc_drv.c | 630 +++++++++++++++++++------------------- 1 file changed, 313 insertions(+), 317 deletions(-) ---- a/drivers/staging/hv/storvsc_drv.c -+++ b/drivers/staging/hv/storvsc_drv.c -@@ -276,7 +276,6 @@ struct hv_storvsc_request { +Index: linux-3.2.46/drivers/staging/hv/storvsc_drv.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/hv/storvsc_drv.c 2013-07-26 19:19:06.000000000 +0000 ++++ linux-3.2.46/drivers/staging/hv/storvsc_drv.c 2013-07-26 19:19:07.000000000 +0000 +@@ -276,7 +276,6 @@ unsigned char *sense_buffer; void *context; @@ -26,7 +28,7 @@ struct hv_multipage_buffer data_buffer; struct vstor_packet vstor_packet; -@@ -436,6 +435,228 @@ get_in_err: +@@ -436,6 +435,228 @@ } @@ -255,7 +257,7 @@ static int storvsc_channel_init(struct hv_device *device) { struct storvsc_device *stor_device; -@@ -562,23 +783,100 @@ cleanup: +@@ -562,23 +783,100 @@ return ret; } @@ -369,7 +371,7 @@ * We do this so we can distinguish truly fatal failues * (srb status == 0x4) and off-line the device in that case. */ -@@ -625,7 +923,7 @@ static void storvsc_on_io_completion(str +@@ -625,7 +923,7 @@ stor_pkt->vm_srb.data_transfer_length = vstor_packet->vm_srb.data_transfer_length; @@ -378,7 +380,7 @@ if (atomic_dec_and_test(&stor_device->num_outstanding_req) && stor_device->drain_notify) -@@ -875,230 +1173,6 @@ static int storvsc_device_configure(stru +@@ -875,230 +1173,6 @@ return 0; } @@ -609,7 +611,7 @@ static int storvsc_get_chs(struct scsi_device *sdev, struct block_device * bdev, sector_t capacity, int *info) { -@@ -1172,83 +1246,6 @@ static int storvsc_host_reset_handler(st +@@ -1172,83 +1246,6 @@ return SUCCESS; } @@ -693,7 +695,7 @@ static bool storvsc_scsi_cmd_ok(struct scsi_cmnd *scmnd) { bool allowed = true; -@@ -1324,7 +1321,6 @@ static int storvsc_queuecommand(struct S +@@ -1324,7 +1321,6 @@ break; } diff -Nru linux-3.2.46/debian/patches/features/x86/hyperv/0056-Staging-hv-storvsc-Rename-the-context-field-in-hv_st.patch linux-3.2.46/debian/patches/features/x86/hyperv/0056-Staging-hv-storvsc-Rename-the-context-field-in-hv_st.patch --- linux-3.2.46/debian/patches/features/x86/hyperv/0056-Staging-hv-storvsc-Rename-the-context-field-in-hv_st.patch 2013-02-24 03:52:26.000000000 +0000 +++ linux-3.2.46/debian/patches/features/x86/hyperv/0056-Staging-hv-storvsc-Rename-the-context-field-in-hv_st.patch 2013-07-26 19:19:09.000000000 +0000 @@ -14,11 +14,11 @@ drivers/staging/hv/storvsc_drv.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) -diff --git a/drivers/staging/hv/storvsc_drv.c b/drivers/staging/hv/storvsc_drv.c -index 7c9fa19..0515707 100644 ---- a/drivers/staging/hv/storvsc_drv.c -+++ b/drivers/staging/hv/storvsc_drv.c -@@ -275,7 +275,7 @@ struct hv_storvsc_request { +Index: linux-3.2.46/drivers/staging/hv/storvsc_drv.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/hv/storvsc_drv.c 2013-07-26 19:19:07.000000000 +0000 ++++ linux-3.2.46/drivers/staging/hv/storvsc_drv.c 2013-07-26 19:19:08.000000000 +0000 +@@ -275,7 +275,7 @@ struct completion wait_event; unsigned char *sense_buffer; @@ -27,7 +27,7 @@ struct hv_multipage_buffer data_buffer; struct vstor_packet vstor_packet; -@@ -785,8 +785,7 @@ cleanup: +@@ -786,8 +786,7 @@ static void storvsc_command_completion(struct hv_storvsc_request *request) { @@ -37,7 +37,7 @@ struct scsi_cmnd *scmnd = cmd_request->cmd; struct hv_host_device *host_dev = shost_priv(scmnd->device->host); void (*scsi_done_fn)(struct scsi_cmnd *); -@@ -1315,7 +1314,7 @@ static int storvsc_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *scmnd) +@@ -1321,7 +1320,7 @@ break; } @@ -46,6 +46,3 @@ vm_srb->port_number = host_dev->port; vm_srb->path_id = scmnd->device->channel; --- -1.7.9.5 - diff -Nru linux-3.2.46/debian/patches/features/x86/hyperv/0057-Staging-hv-storvsc-Miscellaneous-cleanup-of-storvsc-.patch linux-3.2.46/debian/patches/features/x86/hyperv/0057-Staging-hv-storvsc-Miscellaneous-cleanup-of-storvsc-.patch --- linux-3.2.46/debian/patches/features/x86/hyperv/0057-Staging-hv-storvsc-Miscellaneous-cleanup-of-storvsc-.patch 2013-02-24 03:52:26.000000000 +0000 +++ linux-3.2.46/debian/patches/features/x86/hyperv/0057-Staging-hv-storvsc-Miscellaneous-cleanup-of-storvsc-.patch 2013-07-26 19:19:10.000000000 +0000 @@ -14,10 +14,10 @@ drivers/staging/hv/storvsc_drv.c | 94 ++++++++++++++++---------------------- 1 file changed, 39 insertions(+), 55 deletions(-) -diff --git a/drivers/staging/hv/storvsc_drv.c b/drivers/staging/hv/storvsc_drv.c -index 0515707..da71294 100644 ---- a/drivers/staging/hv/storvsc_drv.c -+++ b/drivers/staging/hv/storvsc_drv.c +Index: linux-3.2.46/drivers/staging/hv/storvsc_drv.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/hv/storvsc_drv.c 2013-07-26 19:19:08.000000000 +0000 ++++ linux-3.2.46/drivers/staging/hv/storvsc_drv.c 2013-07-26 19:19:09.000000000 +0000 @@ -43,32 +43,18 @@ #include @@ -58,7 +58,7 @@ /* * Major/minor macros. Minor version is in LSB, meaning that earlier flat -@@ -79,7 +65,6 @@ MODULE_PARM_DESC(storvsc_ringbuffer_size, "Ring buffer size (bytes)"); +@@ -79,7 +65,6 @@ #define VMSTOR_PROTOCOL_MINOR(VERSION_) (((VERSION_)) & 0xff) #define VMSTOR_PROTOCOL_VERSION(MAJOR_, MINOR_) ((((MAJOR_) & 0xff) << 8) | \ (((MINOR_) & 0xff))) @@ -66,35 +66,37 @@ /* * Version history: -@@ -136,26 +121,26 @@ enum vstor_packet_operation { +@@ -136,26 +121,26 @@ #define MAX_DATA_BUF_LEN_WITH_PADDING 0x14 struct vmscsi_request { - unsigned short length; - unsigned char srb_status; - unsigned char scsi_status; -+ u16 length; -+ u8 srb_status; -+ u8 scsi_status; - +- - unsigned char port_number; - unsigned char path_id; - unsigned char target_id; - unsigned char lun; ++ u16 length; ++ u8 srb_status; ++ u8 scsi_status; ++ + u8 port_number; + u8 path_id; + u8 target_id; + u8 lun; - -- unsigned char cdb_length; -- unsigned char sense_info_length; -- unsigned char data_in; -- unsigned char reserved; ++ + u8 cdb_length; + u8 sense_info_length; + u8 data_in; + u8 reserved; +- unsigned char cdb_length; +- unsigned char sense_info_length; +- unsigned char data_in; +- unsigned char reserved; +- - unsigned int data_transfer_length; + u32 data_transfer_length; @@ -108,7 +110,7 @@ }; } __attribute((packed)); -@@ -165,18 +150,21 @@ struct vmscsi_request { +@@ -165,18 +150,21 @@ * properties of the channel. */ struct vmstorage_channel_properties { @@ -126,20 +128,20 @@ + u32 port_number; + u32 flags; + u32 max_transfer_bytes; - -- /* This id is unique for each channel and will correspond with */ -- /* vendor specific data in the inquirydata */ -- unsigned long long unique_id; ++ + /* + * This id is unique for each channel and will correspond with + * vendor specific data in the inquiry data. + */ -+ + +- /* This id is unique for each channel and will correspond with */ +- /* vendor specific data in the inquirydata */ +- unsigned long long unique_id; + u64 unique_id; } __packed; /* This structure is sent during the storage protocol negotiations. */ -@@ -189,6 +177,7 @@ struct vmstorage_protocol_version { +@@ -189,6 +177,7 @@ * (See FILL_VMSTOR_REVISION macro above). Mismatch does not * definitely indicate incompatibility--but it does indicate mismatched * builds. @@ -147,7 +149,7 @@ */ unsigned short revision; } __packed; -@@ -202,10 +191,10 @@ struct vstor_packet { +@@ -202,10 +191,10 @@ enum vstor_packet_operation operation; /* Flags - see below for values */ @@ -160,7 +162,7 @@ /* Data payload area */ union { -@@ -232,11 +221,6 @@ struct vstor_packet { +@@ -232,11 +221,6 @@ #define REQUEST_COMPLETION_FLAG 0x1 @@ -172,7 +174,7 @@ #define STORVSC_MAX_IO_REQUESTS 128 /* -@@ -252,7 +236,7 @@ struct vstor_packet { +@@ -252,7 +236,7 @@ /* Matches Windows-end */ enum storvsc_request_type { @@ -181,7 +183,7 @@ READ_TYPE, UNKNOWN_TYPE, }; -@@ -704,7 +688,7 @@ static int storvsc_channel_init(struct hv_device *device) +@@ -705,7 +689,7 @@ vstor_packet->flags = REQUEST_COMPLETION_FLAG; vstor_packet->version.major_minor = VMSTOR_PROTOCOL_VERSION_CURRENT; @@ -190,6 +192,3 @@ ret = vmbus_sendpacket(device->channel, vstor_packet, sizeof(struct vstor_packet), --- -1.7.9.5 - diff -Nru linux-3.2.46/debian/patches/features/x86/hyperv/0058-Staging-hv-storvsc-Cleanup-the-code-for-generating-p.patch linux-3.2.46/debian/patches/features/x86/hyperv/0058-Staging-hv-storvsc-Cleanup-the-code-for-generating-p.patch --- linux-3.2.46/debian/patches/features/x86/hyperv/0058-Staging-hv-storvsc-Cleanup-the-code-for-generating-p.patch 2013-02-24 03:52:26.000000000 +0000 +++ linux-3.2.46/debian/patches/features/x86/hyperv/0058-Staging-hv-storvsc-Cleanup-the-code-for-generating-p.patch 2013-07-26 19:19:12.000000000 +0000 @@ -13,11 +13,11 @@ drivers/staging/hv/storvsc_drv.c | 27 +++++++++++++++++---------- 1 file changed, 17 insertions(+), 10 deletions(-) -diff --git a/drivers/staging/hv/storvsc_drv.c b/drivers/staging/hv/storvsc_drv.c -index da71294..629edd1 100644 ---- a/drivers/staging/hv/storvsc_drv.c -+++ b/drivers/staging/hv/storvsc_drv.c -@@ -61,10 +61,13 @@ MODULE_PARM_DESC(storvsc_ringbuffer_size, "Ring buffer size (bytes)"); +Index: linux-3.2.46/drivers/staging/hv/storvsc_drv.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/hv/storvsc_drv.c 2013-07-26 19:19:09.000000000 +0000 ++++ linux-3.2.46/drivers/staging/hv/storvsc_drv.c 2013-07-26 19:19:11.000000000 +0000 +@@ -61,10 +61,13 @@ * version numbers will be interpreted as "0.x" (i.e., 1 becomes 0.1). */ @@ -35,7 +35,7 @@ /* * Version history: -@@ -74,9 +77,8 @@ MODULE_PARM_DESC(storvsc_ringbuffer_size, "Ring buffer size (bytes)"); +@@ -74,9 +77,8 @@ * Win7: 4.2 */ @@ -47,7 +47,7 @@ /* -@@ -170,7 +172,7 @@ struct vmstorage_channel_properties { +@@ -170,7 +172,7 @@ /* This structure is sent during the storage protocol negotiations. */ struct vmstorage_protocol_version { /* Major (MSW) and minor (LSW) version numbers. */ @@ -56,7 +56,7 @@ /* * Revision number is auto-incremented whenever this file is changed -@@ -179,7 +181,7 @@ struct vmstorage_protocol_version { +@@ -179,7 +181,7 @@ * builds. * This is only used on the windows side. Just set it to 0. */ @@ -65,7 +65,7 @@ } __packed; /* Channel Property Flags */ -@@ -687,7 +689,12 @@ static int storvsc_channel_init(struct hv_device *device) +@@ -688,7 +690,12 @@ vstor_packet->operation = VSTOR_OPERATION_QUERY_PROTOCOL_VERSION; vstor_packet->flags = REQUEST_COMPLETION_FLAG; @@ -79,6 +79,3 @@ vstor_packet->version.revision = 0; ret = vmbus_sendpacket(device->channel, vstor_packet, --- -1.7.9.5 - diff -Nru linux-3.2.46/debian/patches/features/x86/hyperv/0059-Staging-hv-storvsc-Cleanup-some-protocol-related-con.patch linux-3.2.46/debian/patches/features/x86/hyperv/0059-Staging-hv-storvsc-Cleanup-some-protocol-related-con.patch --- linux-3.2.46/debian/patches/features/x86/hyperv/0059-Staging-hv-storvsc-Cleanup-some-protocol-related-con.patch 2013-02-24 03:52:26.000000000 +0000 +++ linux-3.2.46/debian/patches/features/x86/hyperv/0059-Staging-hv-storvsc-Cleanup-some-protocol-related-con.patch 2013-07-26 19:19:13.000000000 +0000 @@ -13,11 +13,11 @@ drivers/staging/hv/storvsc_drv.c | 19 +++++++------------ 1 file changed, 7 insertions(+), 12 deletions(-) -diff --git a/drivers/staging/hv/storvsc_drv.c b/drivers/staging/hv/storvsc_drv.c -index 629edd1..9f07458 100644 ---- a/drivers/staging/hv/storvsc_drv.c -+++ b/drivers/staging/hv/storvsc_drv.c -@@ -114,13 +114,9 @@ enum vstor_packet_operation { +Index: linux-3.2.46/drivers/staging/hv/storvsc_drv.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/hv/storvsc_drv.c 2013-07-26 19:19:11.000000000 +0000 ++++ linux-3.2.46/drivers/staging/hv/storvsc_drv.c 2013-07-26 19:19:12.000000000 +0000 +@@ -114,13 +114,9 @@ * this remains the same across the write regardless of 32/64 bit * note: it's patterned off the SCSI_PASS_THROUGH structure */ @@ -34,7 +34,7 @@ struct vmscsi_request { u16 length; -@@ -140,9 +136,9 @@ struct vmscsi_request { +@@ -140,9 +136,9 @@ u32 data_transfer_length; union { @@ -47,7 +47,7 @@ }; } __attribute((packed)); -@@ -234,7 +230,6 @@ struct vstor_packet { +@@ -234,7 +230,6 @@ #define STORVSC_MAX_LUNS_PER_TARGET 64 #define STORVSC_MAX_TARGETS 1 #define STORVSC_MAX_CHANNELS 1 @@ -55,7 +55,7 @@ /* Matches Windows-end */ enum storvsc_request_type { -@@ -1074,7 +1069,7 @@ static int storvsc_do_io(struct hv_device *device, +@@ -1075,7 +1070,7 @@ vstor_packet->vm_srb.length = sizeof(struct vmscsi_request); @@ -64,6 +64,3 @@ vstor_packet->vm_srb.data_transfer_length = --- -1.7.9.5 - diff -Nru linux-3.2.46/debian/patches/features/x86/hyperv/0060-Staging-hv-storvsc-Get-rid-of-some-unused-defines.patch linux-3.2.46/debian/patches/features/x86/hyperv/0060-Staging-hv-storvsc-Get-rid-of-some-unused-defines.patch --- linux-3.2.46/debian/patches/features/x86/hyperv/0060-Staging-hv-storvsc-Get-rid-of-some-unused-defines.patch 2013-02-24 03:52:26.000000000 +0000 +++ linux-3.2.46/debian/patches/features/x86/hyperv/0060-Staging-hv-storvsc-Get-rid-of-some-unused-defines.patch 2013-07-26 19:19:14.000000000 +0000 @@ -12,11 +12,11 @@ drivers/staging/hv/storvsc_drv.c | 12 ------------ 1 file changed, 12 deletions(-) -diff --git a/drivers/staging/hv/storvsc_drv.c b/drivers/staging/hv/storvsc_drv.c -index 9f07458..d34e3ca 100644 ---- a/drivers/staging/hv/storvsc_drv.c -+++ b/drivers/staging/hv/storvsc_drv.c -@@ -81,18 +81,6 @@ static inline u16 storvsc_get_version(u8 major, u8 minor) +Index: linux-3.2.46/drivers/staging/hv/storvsc_drv.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/hv/storvsc_drv.c 2013-07-26 19:19:12.000000000 +0000 ++++ linux-3.2.46/drivers/staging/hv/storvsc_drv.c 2013-07-26 19:19:13.000000000 +0000 +@@ -81,18 +81,6 @@ #define VMSTOR_CURRENT_MINOR 2 @@ -35,6 +35,3 @@ /* Packet structure describing virtual storage requests. */ enum vstor_packet_operation { VSTOR_OPERATION_COMPLETE_IO = 1, --- -1.7.9.5 - diff -Nru linux-3.2.46/debian/patches/features/x86/hyperv/0061-Staging-hv-storvsc-Consolidate-the-request-structure.patch linux-3.2.46/debian/patches/features/x86/hyperv/0061-Staging-hv-storvsc-Consolidate-the-request-structure.patch --- linux-3.2.46/debian/patches/features/x86/hyperv/0061-Staging-hv-storvsc-Consolidate-the-request-structure.patch 2013-02-24 03:52:26.000000000 +0000 +++ linux-3.2.46/debian/patches/features/x86/hyperv/0061-Staging-hv-storvsc-Consolidate-the-request-structure.patch 2013-07-26 19:19:15.000000000 +0000 @@ -13,11 +13,11 @@ drivers/staging/hv/storvsc_drv.c | 65 ++++++++++++++++---------------------- 1 file changed, 27 insertions(+), 38 deletions(-) -diff --git a/drivers/staging/hv/storvsc_drv.c b/drivers/staging/hv/storvsc_drv.c -index d34e3ca..9ccc1c4 100644 ---- a/drivers/staging/hv/storvsc_drv.c -+++ b/drivers/staging/hv/storvsc_drv.c -@@ -236,17 +236,20 @@ enum storvsc_request_type { +Index: linux-3.2.46/drivers/staging/hv/storvsc_drv.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/hv/storvsc_drv.c 2013-07-26 19:19:13.000000000 +0000 ++++ linux-3.2.46/drivers/staging/hv/storvsc_drv.c 2013-07-26 19:19:15.000000000 +0000 +@@ -236,17 +236,20 @@ #define SRB_STATUS_ERROR 0x04 @@ -41,7 +41,7 @@ struct vstor_packet vstor_packet; }; -@@ -272,8 +275,8 @@ struct storvsc_device { +@@ -272,8 +275,8 @@ unsigned char target_id; /* Used for vsc/vsp channel reset process */ @@ -52,7 +52,7 @@ }; struct stor_mem_pools { -@@ -288,16 +291,6 @@ struct hv_host_device { +@@ -288,16 +291,6 @@ unsigned char target; }; @@ -69,7 +69,7 @@ struct storvsc_scan_work { struct work_struct work; struct Scsi_Host *host; -@@ -628,7 +621,7 @@ static unsigned int copy_to_bounce_buffer(struct scatterlist *orig_sgl, +@@ -629,7 +622,7 @@ static int storvsc_channel_init(struct hv_device *device) { struct storvsc_device *stor_device; @@ -78,7 +78,7 @@ struct vstor_packet *vstor_packet; int ret, t; -@@ -643,7 +636,7 @@ static int storvsc_channel_init(struct hv_device *device) +@@ -644,7 +637,7 @@ * Now, initiate the vsc/vsp initialization protocol on the open * channel */ @@ -87,7 +87,7 @@ init_completion(&request->wait_event); vstor_packet->operation = VSTOR_OPERATION_BEGIN_INITIALIZATION; vstor_packet->flags = REQUEST_COMPLETION_FLAG; -@@ -757,9 +750,8 @@ cleanup: +@@ -758,9 +751,8 @@ } @@ -98,7 +98,7 @@ struct scsi_cmnd *scmnd = cmd_request->cmd; struct hv_host_device *host_dev = shost_priv(scmnd->device->host); void (*scsi_done_fn)(struct scsi_cmnd *); -@@ -768,7 +760,7 @@ static void storvsc_command_completion(struct hv_storvsc_request *request) +@@ -769,7 +761,7 @@ struct storvsc_scan_work *wrk; struct stor_mem_pools *memp = scmnd->device->hostdata; @@ -107,7 +107,7 @@ if (cmd_request->bounce_sgl_count) { if (vm_srb->data_in == READ_TYPE) copy_from_bounce_buffer(scsi_sglist(scmnd), -@@ -819,7 +811,7 @@ static void storvsc_command_completion(struct hv_storvsc_request *request) +@@ -820,7 +812,7 @@ } scsi_set_resid(scmnd, @@ -116,7 +116,7 @@ vm_srb->data_transfer_length); scsi_done_fn = scmnd->scsi_done; -@@ -834,7 +826,7 @@ static void storvsc_command_completion(struct hv_storvsc_request *request) +@@ -835,7 +827,7 @@ static void storvsc_on_io_completion(struct hv_device *device, struct vstor_packet *vstor_packet, @@ -125,7 +125,7 @@ { struct storvsc_device *stor_device; struct vstor_packet *stor_pkt; -@@ -906,7 +898,7 @@ static void storvsc_on_io_completion(struct hv_device *device, +@@ -907,7 +899,7 @@ static void storvsc_on_receive(struct hv_device *device, struct vstor_packet *vstor_packet, @@ -134,7 +134,7 @@ { struct storvsc_scan_work *work; struct storvsc_device *stor_device; -@@ -940,7 +932,7 @@ static void storvsc_on_channel_callback(void *context) +@@ -941,7 +933,7 @@ u32 bytes_recvd; u64 request_id; unsigned char packet[ALIGN(sizeof(struct vstor_packet), 8)]; @@ -143,7 +143,7 @@ int ret; -@@ -954,7 +946,7 @@ static void storvsc_on_channel_callback(void *context) +@@ -955,7 +947,7 @@ &bytes_recvd, &request_id); if (ret == 0 && bytes_recvd > 0) { @@ -152,7 +152,7 @@ (unsigned long)request_id; if ((request == &stor_device->init_request) || -@@ -1036,7 +1028,7 @@ static int storvsc_dev_remove(struct hv_device *device) +@@ -1037,7 +1029,7 @@ } static int storvsc_do_io(struct hv_device *device, @@ -161,7 +161,7 @@ { struct storvsc_device *stor_device; struct vstor_packet *vstor_packet; -@@ -1174,7 +1166,7 @@ static int storvsc_host_reset_handler(struct scsi_cmnd *scmnd) +@@ -1175,7 +1167,7 @@ struct hv_device *device = host_dev->dev; struct storvsc_device *stor_device; @@ -170,7 +170,7 @@ struct vstor_packet *vstor_packet; int ret, t; -@@ -1238,7 +1230,6 @@ static int storvsc_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *scmnd) +@@ -1244,7 +1236,6 @@ int ret; struct hv_host_device *host_dev = shost_priv(host); struct hv_device *dev = host_dev->dev; @@ -178,7 +178,7 @@ struct storvsc_cmd_request *cmd_request; unsigned int request_size = 0; int i; -@@ -1271,8 +1262,7 @@ static int storvsc_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *scmnd) +@@ -1277,8 +1268,7 @@ scmnd->host_scribble = (unsigned char *)cmd_request; @@ -188,7 +188,7 @@ /* Build the SRB */ -@@ -1288,7 +1278,6 @@ static int storvsc_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *scmnd) +@@ -1294,7 +1284,6 @@ break; } @@ -196,7 +196,7 @@ vm_srb->port_number = host_dev->port; vm_srb->path_id = scmnd->device->channel; -@@ -1299,10 +1288,10 @@ static int storvsc_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *scmnd) +@@ -1305,10 +1294,10 @@ memcpy(vm_srb->cdb, scmnd->cmnd, vm_srb->cdb_length); @@ -209,7 +209,7 @@ if (scsi_sg_count(scmnd)) { sgl = (struct scatterlist *)scsi_sglist(scmnd); sg_count = scsi_sg_count(scmnd); -@@ -1331,21 +1320,21 @@ static int storvsc_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *scmnd) +@@ -1337,21 +1326,21 @@ sg_count = cmd_request->bounce_sgl_count; } @@ -236,6 +236,3 @@ if (ret == -EAGAIN) { /* no more space */ --- -1.7.9.5 - diff -Nru linux-3.2.46/debian/patches/features/x86/hyperv/0062-Staging-hv-storvsc-Consolidate-all-the-wire-protocol.patch linux-3.2.46/debian/patches/features/x86/hyperv/0062-Staging-hv-storvsc-Consolidate-all-the-wire-protocol.patch --- linux-3.2.46/debian/patches/features/x86/hyperv/0062-Staging-hv-storvsc-Consolidate-all-the-wire-protocol.patch 2013-02-24 03:52:26.000000000 +0000 +++ linux-3.2.46/debian/patches/features/x86/hyperv/0062-Staging-hv-storvsc-Consolidate-all-the-wire-protocol.patch 2013-07-26 19:19:17.000000000 +0000 @@ -13,10 +13,10 @@ drivers/staging/hv/storvsc_drv.c | 83 +++++++++++++++++++++----------------- 1 file changed, 47 insertions(+), 36 deletions(-) -diff --git a/drivers/staging/hv/storvsc_drv.c b/drivers/staging/hv/storvsc_drv.c -index 9ccc1c4..695ffc3 100644 ---- a/drivers/staging/hv/storvsc_drv.c -+++ b/drivers/staging/hv/storvsc_drv.c +Index: linux-3.2.46/drivers/staging/hv/storvsc_drv.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/hv/storvsc_drv.c 2013-07-26 19:19:15.000000000 +0000 ++++ linux-3.2.46/drivers/staging/hv/storvsc_drv.c 2013-07-26 19:19:16.000000000 +0000 @@ -42,33 +42,13 @@ #include #include @@ -55,7 +55,7 @@ /* * Version history: * V1 Beta: 0.1 -@@ -207,18 +187,6 @@ struct vstor_packet { +@@ -207,18 +187,6 @@ #define REQUEST_COMPLETION_FLAG 0x1 @@ -74,7 +74,7 @@ /* Matches Windows-end */ enum storvsc_request_type { WRITE_TYPE = 0, -@@ -235,6 +203,36 @@ enum storvsc_request_type { +@@ -235,6 +203,36 @@ #define SRB_STATUS_SUCCESS 0x01 #define SRB_STATUS_ERROR 0x04 @@ -111,7 +111,7 @@ struct storvsc_cmd_request { struct list_head entry; -@@ -337,6 +335,19 @@ done: +@@ -337,6 +335,19 @@ } /* @@ -131,6 +131,3 @@ * We can get incoming messages from the host that are not in response to * messages that we have sent out. An example of this would be messages * received by the guest to notify dynamic addition/removal of LUNs. To --- -1.7.9.5 - diff -Nru linux-3.2.46/debian/patches/features/x86/hyperv/0063-drivers-hv-Cleanup-the-kvp-related-state-in-hyperv.h.patch linux-3.2.46/debian/patches/features/x86/hyperv/0063-drivers-hv-Cleanup-the-kvp-related-state-in-hyperv.h.patch --- linux-3.2.46/debian/patches/features/x86/hyperv/0063-drivers-hv-Cleanup-the-kvp-related-state-in-hyperv.h.patch 2013-02-24 03:52:26.000000000 +0000 +++ linux-3.2.46/debian/patches/features/x86/hyperv/0063-drivers-hv-Cleanup-the-kvp-related-state-in-hyperv.h.patch 2013-07-26 19:19:18.000000000 +0000 @@ -13,11 +13,11 @@ include/linux/hyperv.h | 27 ++++++++++++++------------- 1 file changed, 14 insertions(+), 13 deletions(-) -diff --git a/include/linux/hyperv.h b/include/linux/hyperv.h -index c445ead..dd0e3ee 100644 ---- a/include/linux/hyperv.h -+++ b/include/linux/hyperv.h -@@ -137,7 +137,6 @@ struct hv_ku_msg { +Index: linux-3.2.46/include/linux/hyperv.h +=================================================================== +--- linux-3.2.46.orig/include/linux/hyperv.h 2013-07-26 19:18:53.000000000 +0000 ++++ linux-3.2.46/include/linux/hyperv.h 2013-07-26 19:19:17.000000000 +0000 +@@ -137,7 +137,6 @@ @@ -25,7 +25,7 @@ /* * Registry value types. -@@ -163,28 +162,30 @@ enum hv_kvp_exchg_pool { +@@ -163,28 +162,30 @@ }; struct hv_kvp_hdr { @@ -68,6 +68,3 @@ #include #include #include --- -1.7.9.5 - diff -Nru linux-3.2.46/debian/patches/features/x86/hyperv/0064-tools-hv-Use-hyperv.h-to-get-the-KVP-definitions.patch linux-3.2.46/debian/patches/features/x86/hyperv/0064-tools-hv-Use-hyperv.h-to-get-the-KVP-definitions.patch --- linux-3.2.46/debian/patches/features/x86/hyperv/0064-tools-hv-Use-hyperv.h-to-get-the-KVP-definitions.patch 2013-02-24 03:52:26.000000000 +0000 +++ linux-3.2.46/debian/patches/features/x86/hyperv/0064-tools-hv-Use-hyperv.h-to-get-the-KVP-definitions.patch 2013-07-26 19:19:19.000000000 +0000 @@ -13,10 +13,10 @@ tools/hv/hv_kvp_daemon.c | 28 +--------------------------- 1 file changed, 1 insertion(+), 27 deletions(-) -diff --git a/tools/hv/hv_kvp_daemon.c b/tools/hv/hv_kvp_daemon.c -index 2b6a2d9..b75523c 100644 ---- a/tools/hv/hv_kvp_daemon.c -+++ b/tools/hv/hv_kvp_daemon.c +Index: linux-3.2.46/tools/hv/hv_kvp_daemon.c +=================================================================== +--- linux-3.2.46.orig/tools/hv/hv_kvp_daemon.c 2013-07-26 19:18:52.000000000 +0000 ++++ linux-3.2.46/tools/hv/hv_kvp_daemon.c 2013-07-26 19:19:18.000000000 +0000 @@ -34,17 +34,12 @@ #include #include @@ -62,7 +62,7 @@ enum key_index { FullyQualifiedDomainName = 0, -@@ -89,10 +67,6 @@ enum key_index { +@@ -89,10 +67,6 @@ ProcessorArchitecture }; @@ -73,6 +73,3 @@ static char kvp_send_buffer[4096]; static char kvp_recv_buffer[4096]; static struct sockaddr_nl addr; --- -1.7.9.5 - diff -Nru linux-3.2.46/debian/patches/features/x86/hyperv/0065-drivers-hv-kvp-Cleanup-the-kernel-user-protocol.patch linux-3.2.46/debian/patches/features/x86/hyperv/0065-drivers-hv-kvp-Cleanup-the-kernel-user-protocol.patch --- linux-3.2.46/debian/patches/features/x86/hyperv/0065-drivers-hv-kvp-Cleanup-the-kernel-user-protocol.patch 2013-02-24 03:52:26.000000000 +0000 +++ linux-3.2.46/debian/patches/features/x86/hyperv/0065-drivers-hv-kvp-Cleanup-the-kernel-user-protocol.patch 2013-07-26 19:19:21.000000000 +0000 @@ -16,11 +16,11 @@ tools/hv/hv_kvp_daemon.c | 30 +++++++++++++++--------------- 3 files changed, 45 insertions(+), 56 deletions(-) -diff --git a/drivers/hv/hv_kvp.c b/drivers/hv/hv_kvp.c -index 4a6971e..0ef4c1f 100644 ---- a/drivers/hv/hv_kvp.c -+++ b/drivers/hv/hv_kvp.c -@@ -71,15 +71,20 @@ kvp_register(void) +Index: linux-3.2.46/drivers/hv/hv_kvp.c +=================================================================== +--- linux-3.2.46.orig/drivers/hv/hv_kvp.c 2013-07-26 19:18:53.000000000 +0000 ++++ linux-3.2.46/drivers/hv/hv_kvp.c 2013-07-26 19:19:20.000000000 +0000 +@@ -71,15 +71,20 @@ { struct cn_msg *msg; @@ -45,7 +45,7 @@ cn_netlink_send(msg, 0, GFP_ATOMIC); kfree(msg); } -@@ -101,23 +106,24 @@ kvp_work_func(struct work_struct *dummy) +@@ -101,23 +106,24 @@ static void kvp_cn_callback(struct cn_msg *msg, struct netlink_skb_parms *nsp) { @@ -77,7 +77,7 @@ } } -@@ -125,6 +131,7 @@ static void +@@ -125,6 +131,7 @@ kvp_send_key(struct work_struct *dummy) { struct cn_msg *msg; @@ -85,7 +85,7 @@ int index = kvp_transaction.index; msg = kzalloc(sizeof(*msg) + sizeof(struct hv_kvp_msg) , GFP_ATOMIC); -@@ -132,9 +139,11 @@ kvp_send_key(struct work_struct *dummy) +@@ -132,9 +139,11 @@ if (msg) { msg->id.idx = CN_KVP_IDX; msg->id.val = CN_KVP_VAL; @@ -100,7 +100,7 @@ cn_netlink_send(msg, 0, GFP_ATOMIC); kfree(msg); } -@@ -191,7 +200,7 @@ kvp_respond_to_host(char *key, char *value, int error) +@@ -191,7 +200,7 @@ kvp_msg = (struct hv_kvp_msg *) &recv_buffer[sizeof(struct vmbuspipe_hdr) + sizeof(struct icmsg_hdr)]; @@ -109,7 +109,7 @@ key_name = key; /* -@@ -266,7 +275,7 @@ void hv_kvp_onchannelcallback(void *context) +@@ -266,7 +275,7 @@ sizeof(struct vmbuspipe_hdr) + sizeof(struct icmsg_hdr)]; @@ -118,10 +118,10 @@ /* * We only support the "get" operation on -diff --git a/include/linux/hyperv.h b/include/linux/hyperv.h -index dd0e3ee..e57a6c6 100644 ---- a/include/linux/hyperv.h -+++ b/include/linux/hyperv.h +Index: linux-3.2.46/include/linux/hyperv.h +=================================================================== +--- linux-3.2.46.orig/include/linux/hyperv.h 2013-07-26 19:19:17.000000000 +0000 ++++ linux-3.2.46/include/linux/hyperv.h 2013-07-26 19:19:20.000000000 +0000 @@ -113,30 +113,6 @@ * (not supported), a NULL key string is returned. */ @@ -153,7 +153,7 @@ /* * Registry value types. -@@ -149,6 +125,7 @@ enum hv_kvp_exchg_op { +@@ -149,6 +125,7 @@ KVP_OP_SET, KVP_OP_DELETE, KVP_OP_ENUMERATE, @@ -161,7 +161,7 @@ KVP_OP_COUNT /* Number of operations, must be last. */ }; -@@ -182,7 +159,10 @@ struct hv_kvp_msg_enumerate { +@@ -182,7 +159,10 @@ struct hv_kvp_msg { struct hv_kvp_hdr kvp_hdr; @@ -173,11 +173,11 @@ } __attribute__((packed)); #ifdef __KERNEL__ -diff --git a/tools/hv/hv_kvp_daemon.c b/tools/hv/hv_kvp_daemon.c -index b75523c..4ebf703 100644 ---- a/tools/hv/hv_kvp_daemon.c -+++ b/tools/hv/hv_kvp_daemon.c -@@ -302,7 +302,7 @@ int main(void) +Index: linux-3.2.46/tools/hv/hv_kvp_daemon.c +=================================================================== +--- linux-3.2.46.orig/tools/hv/hv_kvp_daemon.c 2013-07-26 19:19:18.000000000 +0000 ++++ linux-3.2.46/tools/hv/hv_kvp_daemon.c 2013-07-26 19:19:20.000000000 +0000 +@@ -302,7 +302,7 @@ struct pollfd pfd; struct nlmsghdr *incoming_msg; struct cn_msg *incoming_cn_msg; @@ -186,7 +186,7 @@ char *p; char *key_value; char *key_name; -@@ -340,9 +340,11 @@ int main(void) +@@ -340,9 +340,11 @@ message = (struct cn_msg *)kvp_send_buffer; message->id.idx = CN_KVP_IDX; message->id.val = CN_KVP_VAL; @@ -200,7 +200,7 @@ len = netlink_send(fd, message); if (len < 0) { -@@ -368,14 +370,15 @@ int main(void) +@@ -378,14 +380,15 @@ incoming_msg = (struct nlmsghdr *)kvp_recv_buffer; incoming_cn_msg = (struct cn_msg *)NLMSG_DATA(incoming_msg); @@ -219,7 +219,7 @@ lic_version = malloc(strlen(p) + 1); if (lic_version) { strcpy(lic_version, p); -@@ -386,17 +389,15 @@ int main(void) +@@ -396,17 +399,15 @@ } continue; @@ -242,7 +242,7 @@ case FullyQualifiedDomainName: kvp_get_domain_name(key_value, HV_KVP_EXCHANGE_MAX_VALUE_SIZE); -@@ -456,9 +457,8 @@ int main(void) +@@ -466,9 +467,8 @@ incoming_cn_msg->id.idx = CN_KVP_IDX; incoming_cn_msg->id.val = CN_KVP_VAL; @@ -253,6 +253,3 @@ len = netlink_send(fd, incoming_cn_msg); if (len < 0) { --- -1.7.9.5 - diff -Nru linux-3.2.46/debian/patches/features/x86/hyperv/0066-drivers-hv-Increase-the-number-of-VCPUs-supported-in.patch linux-3.2.46/debian/patches/features/x86/hyperv/0066-drivers-hv-Increase-the-number-of-VCPUs-supported-in.patch --- linux-3.2.46/debian/patches/features/x86/hyperv/0066-drivers-hv-Increase-the-number-of-VCPUs-supported-in.patch 2013-02-24 03:52:26.000000000 +0000 +++ linux-3.2.46/debian/patches/features/x86/hyperv/0066-drivers-hv-Increase-the-number-of-VCPUs-supported-in.patch 2013-07-26 19:19:22.000000000 +0000 @@ -21,11 +21,11 @@ drivers/hv/hyperv_vmbus.h | 5 ++--- 2 files changed, 4 insertions(+), 5 deletions(-) -diff --git a/drivers/hv/hv.c b/drivers/hv/hv.c -index 12aa97f..15956bd 100644 ---- a/drivers/hv/hv.c -+++ b/drivers/hv/hv.c -@@ -155,9 +155,9 @@ int hv_init(void) +Index: linux-3.2.46/drivers/hv/hv.c +=================================================================== +--- linux-3.2.46.orig/drivers/hv/hv.c 2013-07-26 19:18:37.000000000 +0000 ++++ linux-3.2.46/drivers/hv/hv.c 2013-07-26 19:19:21.000000000 +0000 +@@ -155,9 +155,9 @@ union hv_x64_msr_hypercall_contents hypercall_msr; void *virtaddr = NULL; @@ -37,11 +37,11 @@ if (!query_hypervisor_presence()) goto cleanup; -diff --git a/drivers/hv/hyperv_vmbus.h b/drivers/hv/hyperv_vmbus.h -index 6d7d286..699f0d8 100644 ---- a/drivers/hv/hyperv_vmbus.h -+++ b/drivers/hv/hyperv_vmbus.h -@@ -457,7 +457,6 @@ static const uuid_le VMBUS_SERVICE_ID = { +Index: linux-3.2.46/drivers/hv/hyperv_vmbus.h +=================================================================== +--- linux-3.2.46.orig/drivers/hv/hyperv_vmbus.h 2013-07-26 19:18:35.000000000 +0000 ++++ linux-3.2.46/drivers/hv/hyperv_vmbus.h 2013-07-26 19:19:21.000000000 +0000 +@@ -457,7 +457,6 @@ }, }; @@ -49,7 +49,7 @@ struct hv_input_signal_event_buffer { -@@ -483,8 +482,8 @@ struct hv_context { +@@ -483,8 +482,8 @@ /* 8-bytes aligned of the buffer above */ struct hv_input_signal_event *signal_event_param; @@ -60,6 +60,3 @@ }; extern struct hv_context hv_context; --- -1.7.9.5 - diff -Nru linux-3.2.46/debian/patches/features/x86/hyperv/0067-Staging-hv-storvsc-Move-the-storage-driver-out-of-th.patch linux-3.2.46/debian/patches/features/x86/hyperv/0067-Staging-hv-storvsc-Move-the-storage-driver-out-of-th.patch --- linux-3.2.46/debian/patches/features/x86/hyperv/0067-Staging-hv-storvsc-Move-the-storage-driver-out-of-th.patch 2013-03-21 00:39:41.000000000 +0000 +++ linux-3.2.46/debian/patches/features/x86/hyperv/0067-Staging-hv-storvsc-Move-the-storage-driver-out-of-th.patch 2013-07-26 19:19:24.000000000 +0000 @@ -23,9 +23,11 @@ '[SCSI] storvsc: Account for in-transit packets in the RESET path' and 9d2696e658ef '[SCSI] storvsc: Initialize the sglist'] --- ---- a/drivers/scsi/Kconfig -+++ b/drivers/scsi/Kconfig -@@ -663,6 +663,13 @@ config VMWARE_PVSCSI +Index: linux-3.2.46/drivers/scsi/Kconfig +=================================================================== +--- linux-3.2.46.orig/drivers/scsi/Kconfig 2013-07-26 19:17:07.000000000 +0000 ++++ linux-3.2.46/drivers/scsi/Kconfig 2013-07-26 19:19:22.000000000 +0000 +@@ -663,6 +663,13 @@ To compile this driver as a module, choose M here: the module will be called vmw_pvscsi. @@ -39,9 +41,11 @@ config LIBFC tristate "LibFC module" select SCSI_FC_ATTRS ---- a/drivers/scsi/Makefile -+++ b/drivers/scsi/Makefile -@@ -142,6 +142,7 @@ obj-$(CONFIG_SCSI_BNX2_ISCSI) += libiscs +Index: linux-3.2.46/drivers/scsi/Makefile +=================================================================== +--- linux-3.2.46.orig/drivers/scsi/Makefile 2013-07-26 18:55:54.000000000 +0000 ++++ linux-3.2.46/drivers/scsi/Makefile 2013-07-26 19:19:22.000000000 +0000 +@@ -142,6 +142,7 @@ obj-$(CONFIG_BE2ISCSI) += libiscsi.o be2iscsi/ obj-$(CONFIG_SCSI_PMCRAID) += pmcraid.o obj-$(CONFIG_VMWARE_PVSCSI) += vmw_pvscsi.o @@ -49,7 +53,7 @@ obj-$(CONFIG_ARM) += arm/ -@@ -170,6 +171,8 @@ scsi_mod-$(CONFIG_SCSI_PROC_FS) += scsi_ +@@ -170,6 +171,8 @@ scsi_mod-y += scsi_trace.o scsi_mod-$(CONFIG_PM) += scsi_pm.o @@ -58,8 +62,10 @@ scsi_tgt-y += scsi_tgt_lib.o scsi_tgt_if.o sd_mod-objs := sd.o ---- /dev/null -+++ b/drivers/scsi/storvsc_drv.c +Index: linux-3.2.46/drivers/scsi/storvsc_drv.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/scsi/storvsc_drv.c 2013-07-26 19:19:22.000000000 +0000 @@ -0,0 +1,1554 @@ +/* + * Copyright (c) 2009, Microsoft Corporation. @@ -1615,9 +1621,11 @@ +MODULE_DESCRIPTION("Microsoft Hyper-V virtual storage driver"); +module_init(storvsc_drv_init); +module_exit(storvsc_drv_exit); ---- a/drivers/staging/Kconfig -+++ b/drivers/staging/Kconfig -@@ -80,8 +80,6 @@ source "drivers/staging/vt6655/Kconfig" +Index: linux-3.2.46/drivers/staging/Kconfig +=================================================================== +--- linux-3.2.46.orig/drivers/staging/Kconfig 2013-07-26 18:55:54.000000000 +0000 ++++ linux-3.2.46/drivers/staging/Kconfig 2013-07-26 19:19:22.000000000 +0000 +@@ -80,8 +80,6 @@ source "drivers/staging/vt6656/Kconfig" @@ -1626,9 +1634,11 @@ source "drivers/staging/vme/Kconfig" source "drivers/staging/sep/Kconfig" ---- a/drivers/staging/Makefile -+++ b/drivers/staging/Makefile -@@ -31,7 +31,6 @@ obj-$(CONFIG_USB_SERIAL_QUATECH_USB2) += +Index: linux-3.2.46/drivers/staging/Makefile +=================================================================== +--- linux-3.2.46.orig/drivers/staging/Makefile 2013-07-26 18:55:54.000000000 +0000 ++++ linux-3.2.46/drivers/staging/Makefile 2013-07-26 19:19:22.000000000 +0000 +@@ -31,7 +31,6 @@ obj-$(CONFIG_OCTEON_ETHERNET) += octeon/ obj-$(CONFIG_VT6655) += vt6655/ obj-$(CONFIG_VT6656) += vt6656/ @@ -1636,30 +1646,38 @@ obj-$(CONFIG_VME_BUS) += vme/ obj-$(CONFIG_DX_SEP) += sep/ obj-$(CONFIG_IIO) += iio/ ---- a/drivers/staging/hv/Kconfig -+++ /dev/null +Index: linux-3.2.46/drivers/staging/hv/Kconfig +=================================================================== +--- linux-3.2.46.orig/drivers/staging/hv/Kconfig 2013-07-26 19:18:18.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 @@ -1,5 +0,0 @@ -config HYPERV_STORAGE - tristate "Microsoft Hyper-V virtual storage driver" - depends on HYPERV && SCSI - help - Select this option to enable the Hyper-V virtual storage driver. ---- a/drivers/staging/hv/Makefile -+++ /dev/null +Index: linux-3.2.46/drivers/staging/hv/Makefile +=================================================================== +--- linux-3.2.46.orig/drivers/staging/hv/Makefile 2013-07-26 19:18:18.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 @@ -1,3 +0,0 @@ -obj-$(CONFIG_HYPERV_STORAGE) += hv_storvsc.o - -hv_storvsc-y := storvsc_drv.o ---- a/drivers/staging/hv/TODO -+++ /dev/null +Index: linux-3.2.46/drivers/staging/hv/TODO +=================================================================== +--- linux-3.2.46.orig/drivers/staging/hv/TODO 2013-07-26 19:18:29.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 @@ -1,5 +0,0 @@ -TODO: - - audit the scsi driver - -Please send patches for this code to Greg Kroah-Hartman , -Haiyang Zhang , and K. Y. Srinivasan ---- a/drivers/staging/hv/storvsc_drv.c -+++ /dev/null +Index: linux-3.2.46/drivers/staging/hv/storvsc_drv.c +=================================================================== +--- linux-3.2.46.orig/drivers/staging/hv/storvsc_drv.c 2013-07-26 19:19:16.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 @@ -1,1554 +0,0 @@ -/* - * Copyright (c) 2009, Microsoft Corporation. diff -Nru linux-3.2.46/debian/patches/features/x86/hyperv/0068-net-hyperv-Use-the-built-in-macro-KBUILD_MODNAME-for.patch linux-3.2.46/debian/patches/features/x86/hyperv/0068-net-hyperv-Use-the-built-in-macro-KBUILD_MODNAME-for.patch --- linux-3.2.46/debian/patches/features/x86/hyperv/0068-net-hyperv-Use-the-built-in-macro-KBUILD_MODNAME-for.patch 2013-02-24 03:52:26.000000000 +0000 +++ linux-3.2.46/debian/patches/features/x86/hyperv/0068-net-hyperv-Use-the-built-in-macro-KBUILD_MODNAME-for.patch 2013-07-26 19:19:25.000000000 +0000 @@ -13,11 +13,11 @@ drivers/net/hyperv/netvsc_drv.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -diff --git a/drivers/net/hyperv/netvsc_drv.c b/drivers/net/hyperv/netvsc_drv.c -index 0ae7a1a..217dfed 100644 ---- a/drivers/net/hyperv/netvsc_drv.c -+++ b/drivers/net/hyperv/netvsc_drv.c -@@ -310,7 +310,7 @@ int netvsc_recv_callback(struct hv_device *device_obj, +Index: linux-3.2.46/drivers/net/hyperv/netvsc_drv.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/hyperv/netvsc_drv.c 2013-07-26 19:18:56.000000000 +0000 ++++ linux-3.2.46/drivers/net/hyperv/netvsc_drv.c 2013-07-26 19:19:24.000000000 +0000 +@@ -310,7 +310,7 @@ static void netvsc_get_drvinfo(struct net_device *net, struct ethtool_drvinfo *info) { @@ -26,7 +26,7 @@ strcpy(info->version, HV_DRV_VERSION); strcpy(info->fw_version, "N/A"); } -@@ -482,7 +482,7 @@ MODULE_DEVICE_TABLE(vmbus, id_table); +@@ -482,7 +482,7 @@ /* The one and only one */ static struct hv_driver netvsc_drv = { @@ -35,6 +35,3 @@ .id_table = id_table, .probe = netvsc_probe, .remove = netvsc_remove, --- -1.7.9.5 - diff -Nru linux-3.2.46/debian/patches/features/x86/hyperv/0069-net-hyperv-Fix-data-corruption-in-rndis_filter_recei.patch linux-3.2.46/debian/patches/features/x86/hyperv/0069-net-hyperv-Fix-data-corruption-in-rndis_filter_recei.patch --- linux-3.2.46/debian/patches/features/x86/hyperv/0069-net-hyperv-Fix-data-corruption-in-rndis_filter_recei.patch 2013-02-24 03:52:26.000000000 +0000 +++ linux-3.2.46/debian/patches/features/x86/hyperv/0069-net-hyperv-Fix-data-corruption-in-rndis_filter_recei.patch 2013-07-26 19:19:26.000000000 +0000 @@ -20,11 +20,11 @@ drivers/net/hyperv/rndis_filter.c | 33 +++++++++------------------------ 1 file changed, 9 insertions(+), 24 deletions(-) -diff --git a/drivers/net/hyperv/rndis_filter.c b/drivers/net/hyperv/rndis_filter.c -index 136efd8..0c3d7d9 100644 ---- a/drivers/net/hyperv/rndis_filter.c -+++ b/drivers/net/hyperv/rndis_filter.c -@@ -352,8 +352,7 @@ int rndis_filter_receive(struct hv_device *dev, +Index: linux-3.2.46/drivers/net/hyperv/rndis_filter.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/hyperv/rndis_filter.c 2013-07-26 19:18:57.000000000 +0000 ++++ linux-3.2.46/drivers/net/hyperv/rndis_filter.c 2013-07-26 19:19:25.000000000 +0000 +@@ -352,8 +352,7 @@ { struct netvsc_device *net_dev = hv_get_drvdata(dev); struct rndis_device *rndis_dev; @@ -34,12 +34,13 @@ struct net_device *ndev; if (!net_dev) -@@ -375,46 +374,32 @@ int rndis_filter_receive(struct hv_device *dev, +@@ -375,46 +374,32 @@ return -ENODEV; } - rndis_hdr = pkt->data; -- ++ rndis_msg = pkt->data; + - /* Make sure we got a valid rndis message */ - if ((rndis_hdr->ndis_msg_type != REMOTE_NDIS_PACKET_MSG) && - (rndis_hdr->msg_len > sizeof(struct rndis_message))) { @@ -48,16 +49,15 @@ - rndis_hdr->msg_len, - sizeof(struct rndis_message)); - } -+ rndis_msg = pkt->data; - +- - memcpy(&rndis_msg, rndis_hdr, - (rndis_hdr->msg_len > sizeof(struct rndis_message)) ? - sizeof(struct rndis_message) : - rndis_hdr->msg_len); +- +- dump_rndis_message(dev, &rndis_msg); + dump_rndis_message(dev, rndis_msg); -- dump_rndis_message(dev, &rndis_msg); -- - switch (rndis_msg.ndis_msg_type) { + switch (rndis_msg->ndis_msg_type) { case REMOTE_NDIS_PACKET_MSG: @@ -89,6 +89,3 @@ break; } --- -1.7.9.5 - diff -Nru linux-3.2.46/debian/patches/features/x86/hyperv/0070-net-hyperv-Add-support-for-vlan-trunking-from-guests.patch linux-3.2.46/debian/patches/features/x86/hyperv/0070-net-hyperv-Add-support-for-vlan-trunking-from-guests.patch --- linux-3.2.46/debian/patches/features/x86/hyperv/0070-net-hyperv-Add-support-for-vlan-trunking-from-guests.patch 2013-02-24 03:52:26.000000000 +0000 +++ linux-3.2.46/debian/patches/features/x86/hyperv/0070-net-hyperv-Add-support-for-vlan-trunking-from-guests.patch 2013-07-26 19:19:28.000000000 +0000 @@ -17,11 +17,11 @@ drivers/net/hyperv/rndis_filter.c | 60 +++++++++++++++++++++++++++++++++++++ 4 files changed, 101 insertions(+), 4 deletions(-) -diff --git a/drivers/net/hyperv/hyperv_net.h b/drivers/net/hyperv/hyperv_net.h -index dec5836..c358245 100644 ---- a/drivers/net/hyperv/hyperv_net.h -+++ b/drivers/net/hyperv/hyperv_net.h -@@ -49,6 +49,7 @@ struct hv_netvsc_packet { +Index: linux-3.2.46/drivers/net/hyperv/hyperv_net.h +=================================================================== +--- linux-3.2.46.orig/drivers/net/hyperv/hyperv_net.h 2013-07-26 19:18:41.000000000 +0000 ++++ linux-3.2.46/drivers/net/hyperv/hyperv_net.h 2013-07-26 19:19:27.000000000 +0000 +@@ -49,6 +49,7 @@ struct hv_device *device; bool is_data_pkt; @@ -29,7 +29,7 @@ /* * Valid only for receives when we break a xfer page packet -@@ -926,9 +927,40 @@ struct rndis_oobd { +@@ -926,9 +927,40 @@ struct rndis_per_packet_info { u32 size; u32 type; @@ -71,11 +71,11 @@ /* Format of Information buffer passed in a SetRequest for the OID */ /* OID_GEN_RNDIS_CONFIG_PARAMETER. */ struct rndis_config_parameter_info { -diff --git a/drivers/net/hyperv/netvsc.c b/drivers/net/hyperv/netvsc.c -index 8965b45..d025c83 100644 ---- a/drivers/net/hyperv/netvsc.c -+++ b/drivers/net/hyperv/netvsc.c -@@ -300,6 +300,7 @@ static int negotiate_nvsp_ver(struct hv_device *device, +Index: linux-3.2.46/drivers/net/hyperv/netvsc.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/hyperv/netvsc.c 2013-07-26 19:18:41.000000000 +0000 ++++ linux-3.2.46/drivers/net/hyperv/netvsc.c 2013-07-26 19:19:27.000000000 +0000 +@@ -300,6 +300,7 @@ memset(init_packet, 0, sizeof(struct nvsp_message)); init_packet->hdr.msg_type = NVSP_MSG2_TYPE_SEND_NDIS_CONFIG; init_packet->msg.v2_msg.send_ndis_config.mtu = net_device->ndev->mtu; @@ -83,7 +83,7 @@ ret = vmbus_sendpacket(device->channel, init_packet, sizeof(struct nvsp_message), -@@ -341,7 +342,7 @@ static int netvsc_connect_vsp(struct hv_device *device) +@@ -341,7 +342,7 @@ /* Send the ndis version */ memset(init_packet, 0, sizeof(struct nvsp_message)); @@ -92,11 +92,11 @@ init_packet->hdr.msg_type = NVSP_MSG1_TYPE_SEND_NDIS_VER; init_packet->msg.v1_msg. -diff --git a/drivers/net/hyperv/netvsc_drv.c b/drivers/net/hyperv/netvsc_drv.c -index 217dfed..0f8e834 100644 ---- a/drivers/net/hyperv/netvsc_drv.c -+++ b/drivers/net/hyperv/netvsc_drv.c -@@ -159,7 +159,8 @@ static int netvsc_start_xmit(struct sk_buff *skb, struct net_device *net) +Index: linux-3.2.46/drivers/net/hyperv/netvsc_drv.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/hyperv/netvsc_drv.c 2013-07-26 19:19:24.000000000 +0000 ++++ linux-3.2.46/drivers/net/hyperv/netvsc_drv.c 2013-07-26 19:19:27.000000000 +0000 +@@ -159,7 +159,8 @@ /* Allocate a netvsc packet based on # of frags. */ packet = kzalloc(sizeof(struct hv_netvsc_packet) + (num_pages * sizeof(struct hv_page_buffer)) + @@ -106,7 +106,7 @@ if (!packet) { /* out of memory, drop packet */ netdev_err(net, "unable to allocate hv_netvsc_packet\n"); -@@ -169,6 +170,8 @@ static int netvsc_start_xmit(struct sk_buff *skb, struct net_device *net) +@@ -169,6 +170,8 @@ return NETDEV_TX_BUSY; } @@ -115,7 +115,7 @@ packet->extension = (void *)(unsigned long)packet + sizeof(struct hv_netvsc_packet) + (num_pages * sizeof(struct hv_page_buffer)); -@@ -293,6 +296,7 @@ int netvsc_recv_callback(struct hv_device *device_obj, +@@ -293,6 +296,7 @@ skb->protocol = eth_type_trans(skb, net); skb->ip_summed = CHECKSUM_NONE; @@ -123,7 +123,7 @@ net->stats.rx_packets++; net->stats.rx_bytes += packet->total_data_buflen; -@@ -407,7 +411,7 @@ static int netvsc_probe(struct hv_device *dev, +@@ -407,7 +411,7 @@ /* TODO: Add GSO and Checksum offload */ net->hw_features = NETIF_F_SG; @@ -132,10 +132,10 @@ SET_ETHTOOL_OPS(net, ðtool_ops); SET_NETDEV_DEV(net, &dev->device); -diff --git a/drivers/net/hyperv/rndis_filter.c b/drivers/net/hyperv/rndis_filter.c -index 0c3d7d9..d6be64b 100644 ---- a/drivers/net/hyperv/rndis_filter.c -+++ b/drivers/net/hyperv/rndis_filter.c +Index: linux-3.2.46/drivers/net/hyperv/rndis_filter.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/hyperv/rndis_filter.c 2013-07-26 19:19:25.000000000 +0000 ++++ linux-3.2.46/drivers/net/hyperv/rndis_filter.c 2013-07-26 19:19:27.000000000 +0000 @@ -26,6 +26,7 @@ #include #include @@ -144,7 +144,7 @@ #include "hyperv_net.h" -@@ -303,12 +304,39 @@ static void rndis_filter_receive_indicate_status(struct rndis_device *dev, +@@ -303,12 +304,39 @@ } } @@ -184,7 +184,7 @@ rndis_pkt = &msg->msg.pkt; -@@ -344,6 +372,14 @@ static void rndis_filter_receive_data(struct rndis_device *dev, +@@ -344,6 +372,14 @@ pkt->is_data_pkt = true; @@ -199,7 +199,7 @@ netvsc_recv_callback(dev->net_dev->dev, pkt); } -@@ -759,12 +795,15 @@ int rndis_filter_send(struct hv_device *dev, +@@ -759,12 +795,15 @@ struct rndis_message *rndis_msg; struct rndis_packet *rndis_pkt; u32 rndis_msg_size; @@ -215,7 +215,7 @@ rndis_msg->ndis_msg_type = REMOTE_NDIS_PACKET_MSG; rndis_msg->msg_len = pkt->total_data_buflen + -@@ -772,8 +811,29 @@ int rndis_filter_send(struct hv_device *dev, +@@ -772,8 +811,29 @@ rndis_pkt = &rndis_msg->msg.pkt; rndis_pkt->data_offset = sizeof(struct rndis_packet); @@ -245,6 +245,3 @@ pkt->is_data_pkt = true; pkt->page_buf[0].pfn = virt_to_phys(rndis_msg) >> PAGE_SHIFT; pkt->page_buf[0].offset = --- -1.7.9.5 - diff -Nru linux-3.2.46/debian/patches/features/x86/hyperv/0071-Drivers-hv-Add-new-message-types-to-enhance-KVP.patch linux-3.2.46/debian/patches/features/x86/hyperv/0071-Drivers-hv-Add-new-message-types-to-enhance-KVP.patch --- linux-3.2.46/debian/patches/features/x86/hyperv/0071-Drivers-hv-Add-new-message-types-to-enhance-KVP.patch 2013-02-24 03:52:26.000000000 +0000 +++ linux-3.2.46/debian/patches/features/x86/hyperv/0071-Drivers-hv-Add-new-message-types-to-enhance-KVP.patch 2013-07-26 19:19:29.000000000 +0000 @@ -17,11 +17,11 @@ tools/hv/hv_kvp_daemon.c | 2 +- 3 files changed, 31 insertions(+), 6 deletions(-) -diff --git a/drivers/hv/hv_kvp.c b/drivers/hv/hv_kvp.c -index 0ef4c1f..779109b 100644 ---- a/drivers/hv/hv_kvp.c -+++ b/drivers/hv/hv_kvp.c -@@ -78,7 +78,7 @@ kvp_register(void) +Index: linux-3.2.46/drivers/hv/hv_kvp.c +=================================================================== +--- linux-3.2.46.orig/drivers/hv/hv_kvp.c 2013-07-26 19:19:20.000000000 +0000 ++++ linux-3.2.46/drivers/hv/hv_kvp.c 2013-07-26 19:19:28.000000000 +0000 +@@ -78,7 +78,7 @@ if (msg) { kvp_msg = (struct hv_kvp_msg *)msg->data; @@ -30,7 +30,7 @@ msg->id.idx = CN_KVP_IDX; msg->id.val = CN_KVP_VAL; -@@ -122,7 +122,8 @@ kvp_cn_callback(struct cn_msg *msg, struct netlink_skb_parms *nsp) +@@ -122,7 +122,8 @@ * to the host. But first, cancel the timeout. */ if (cancel_delayed_work_sync(&kvp_work)) @@ -40,11 +40,11 @@ !strlen(data->data.key)); } } -diff --git a/include/linux/hyperv.h b/include/linux/hyperv.h -index e57a6c6..a2d8c54 100644 ---- a/include/linux/hyperv.h -+++ b/include/linux/hyperv.h -@@ -149,7 +149,11 @@ struct hv_kvp_exchg_msg_value { +Index: linux-3.2.46/include/linux/hyperv.h +=================================================================== +--- linux-3.2.46.orig/include/linux/hyperv.h 2013-07-26 19:19:20.000000000 +0000 ++++ linux-3.2.46/include/linux/hyperv.h 2013-07-26 19:19:28.000000000 +0000 +@@ -149,7 +149,11 @@ __u32 key_size; __u32 value_size; __u8 key[HV_KVP_EXCHANGE_MAX_KEY_SIZE]; @@ -57,7 +57,7 @@ } __attribute__((packed)); struct hv_kvp_msg_enumerate { -@@ -157,11 +161,31 @@ struct hv_kvp_msg_enumerate { +@@ -157,11 +161,31 @@ struct hv_kvp_exchg_msg_value data; } __attribute__((packed)); @@ -91,11 +91,11 @@ } body; } __attribute__((packed)); -diff --git a/tools/hv/hv_kvp_daemon.c b/tools/hv/hv_kvp_daemon.c -index 4ebf703..00d3f7c 100644 ---- a/tools/hv/hv_kvp_daemon.c -+++ b/tools/hv/hv_kvp_daemon.c -@@ -378,7 +378,7 @@ int main(void) +Index: linux-3.2.46/tools/hv/hv_kvp_daemon.c +=================================================================== +--- linux-3.2.46.orig/tools/hv/hv_kvp_daemon.c 2013-07-26 19:19:20.000000000 +0000 ++++ linux-3.2.46/tools/hv/hv_kvp_daemon.c 2013-07-26 19:19:28.000000000 +0000 +@@ -388,7 +388,7 @@ * Driver is registering with us; stash away the version * information. */ @@ -104,6 +104,3 @@ lic_version = malloc(strlen(p) + 1); if (lic_version) { strcpy(lic_version, p); --- -1.7.9.5 - diff -Nru linux-3.2.46/debian/patches/features/x86/hyperv/0072-net-hyperv-fix-erroneous-NETDEV_TX_BUSY-use.patch linux-3.2.46/debian/patches/features/x86/hyperv/0072-net-hyperv-fix-erroneous-NETDEV_TX_BUSY-use.patch --- linux-3.2.46/debian/patches/features/x86/hyperv/0072-net-hyperv-fix-erroneous-NETDEV_TX_BUSY-use.patch 2013-02-24 03:52:26.000000000 +0000 +++ linux-3.2.46/debian/patches/features/x86/hyperv/0072-net-hyperv-fix-erroneous-NETDEV_TX_BUSY-use.patch 2013-07-26 19:19:30.000000000 +0000 @@ -26,11 +26,11 @@ drivers/net/hyperv/netvsc_drv.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -diff --git a/drivers/net/hyperv/netvsc_drv.c b/drivers/net/hyperv/netvsc_drv.c -index 0f8e834..2517d20 100644 ---- a/drivers/net/hyperv/netvsc_drv.c -+++ b/drivers/net/hyperv/netvsc_drv.c -@@ -167,7 +167,7 @@ static int netvsc_start_xmit(struct sk_buff *skb, struct net_device *net) +Index: linux-3.2.46/drivers/net/hyperv/netvsc_drv.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/hyperv/netvsc_drv.c 2013-07-26 19:19:27.000000000 +0000 ++++ linux-3.2.46/drivers/net/hyperv/netvsc_drv.c 2013-07-26 19:19:30.000000000 +0000 +@@ -167,7 +167,7 @@ dev_kfree_skb(skb); net->stats.tx_dropped++; @@ -39,7 +39,7 @@ } packet->vlan_tci = skb->vlan_tci; -@@ -229,7 +229,7 @@ static int netvsc_start_xmit(struct sk_buff *skb, struct net_device *net) +@@ -229,7 +229,7 @@ dev_kfree_skb_any(skb); } @@ -48,6 +48,3 @@ } /* --- -1.7.9.5 - diff -Nru linux-3.2.46/debian/patches/features/x86/hyperv/0073-Drivers-hv-Support-the-newly-introduced-KVP-messages.patch linux-3.2.46/debian/patches/features/x86/hyperv/0073-Drivers-hv-Support-the-newly-introduced-KVP-messages.patch --- linux-3.2.46/debian/patches/features/x86/hyperv/0073-Drivers-hv-Support-the-newly-introduced-KVP-messages.patch 2013-02-24 03:52:26.000000000 +0000 +++ linux-3.2.46/debian/patches/features/x86/hyperv/0073-Drivers-hv-Support-the-newly-introduced-KVP-messages.patch 2013-07-26 19:19:32.000000000 +0000 @@ -20,10 +20,10 @@ tools/hv/hv_kvp_daemon.c | 7 ++ 3 files changed, 176 insertions(+), 51 deletions(-) -diff --git a/drivers/hv/hv_kvp.c b/drivers/hv/hv_kvp.c -index 779109b..cfe60b0 100644 ---- a/drivers/hv/hv_kvp.c -+++ b/drivers/hv/hv_kvp.c +Index: linux-3.2.46/drivers/hv/hv_kvp.c +=================================================================== +--- linux-3.2.46.orig/drivers/hv/hv_kvp.c 2013-07-26 19:19:28.000000000 +0000 ++++ linux-3.2.46/drivers/hv/hv_kvp.c 2013-07-26 19:19:31.000000000 +0000 @@ -42,9 +42,10 @@ static struct { bool active; /* transaction status - active or not */ @@ -36,7 +36,7 @@ } kvp_transaction; static void kvp_send_key(struct work_struct *dummy); -@@ -110,12 +111,15 @@ kvp_cn_callback(struct cn_msg *msg, struct netlink_skb_parms *nsp) +@@ -110,12 +111,15 @@ struct hv_kvp_msg_enumerate *data; message = (struct hv_kvp_msg *)msg->data; @@ -55,7 +55,7 @@ data = &message->body.kvp_enum_data; /* * Complete the transaction by forwarding the key value -@@ -133,21 +137,104 @@ kvp_send_key(struct work_struct *dummy) +@@ -133,21 +137,104 @@ { struct cn_msg *msg; struct hv_kvp_msg *message; @@ -170,7 +170,7 @@ return; } -@@ -159,10 +246,11 @@ static void +@@ -159,10 +246,11 @@ kvp_respond_to_host(char *key, char *value, int error) { struct hv_kvp_msg *kvp_msg; @@ -184,7 +184,7 @@ u32 buf_len; struct vmbus_channel *channel; u64 req_id; -@@ -189,6 +277,9 @@ kvp_respond_to_host(char *key, char *value, int error) +@@ -189,6 +277,9 @@ kvp_transaction.active = false; @@ -194,7 +194,7 @@ if (channel->onchannel_callback == NULL) /* * We have raced with util driver being unloaded; -@@ -196,41 +287,66 @@ kvp_respond_to_host(char *key, char *value, int error) +@@ -196,41 +287,66 @@ */ return; @@ -278,7 +278,7 @@ response_done: icmsghdrp->icflags = ICMSGHDRFLAG_TRANSACTION | ICMSGHDRFLAG_RESPONSE; -@@ -257,11 +373,18 @@ void hv_kvp_onchannelcallback(void *context) +@@ -257,11 +373,18 @@ u64 requestid; struct hv_kvp_msg *kvp_msg; @@ -298,7 +298,7 @@ vmbus_recvpacket(channel, recv_buffer, PAGE_SIZE, &recvlen, &requestid); -@@ -276,29 +399,16 @@ void hv_kvp_onchannelcallback(void *context) +@@ -276,29 +399,16 @@ sizeof(struct vmbuspipe_hdr) + sizeof(struct icmsg_hdr)]; @@ -330,7 +330,7 @@ /* * Get the information from the -@@ -316,8 +426,6 @@ void hv_kvp_onchannelcallback(void *context) +@@ -316,8 +426,6 @@ } @@ -339,7 +339,7 @@ icmsghdrp->icflags = ICMSGHDRFLAG_TRANSACTION | ICMSGHDRFLAG_RESPONSE; -@@ -338,6 +446,14 @@ hv_kvp_init(struct hv_util_service *srv) +@@ -338,6 +446,14 @@ return err; recv_buffer = srv->recv_buffer; @@ -354,10 +354,10 @@ return 0; } -diff --git a/include/linux/hyperv.h b/include/linux/hyperv.h -index a2d8c54..e88a979 100644 ---- a/include/linux/hyperv.h -+++ b/include/linux/hyperv.h +Index: linux-3.2.46/include/linux/hyperv.h +=================================================================== +--- linux-3.2.46.orig/include/linux/hyperv.h 2013-07-26 19:19:28.000000000 +0000 ++++ linux-3.2.46/include/linux/hyperv.h 2013-07-26 19:19:31.000000000 +0000 @@ -119,6 +119,8 @@ */ @@ -367,11 +367,11 @@ enum hv_kvp_exchg_op { KVP_OP_GET = 0, -diff --git a/tools/hv/hv_kvp_daemon.c b/tools/hv/hv_kvp_daemon.c -index 00d3f7c..a98878c 100644 ---- a/tools/hv/hv_kvp_daemon.c -+++ b/tools/hv/hv_kvp_daemon.c -@@ -389,10 +389,16 @@ int main(void) +Index: linux-3.2.46/tools/hv/hv_kvp_daemon.c +=================================================================== +--- linux-3.2.46.orig/tools/hv/hv_kvp_daemon.c 2013-07-26 19:19:28.000000000 +0000 ++++ linux-3.2.46/tools/hv/hv_kvp_daemon.c 2013-07-26 19:19:31.000000000 +0000 +@@ -399,10 +399,16 @@ } continue; @@ -388,7 +388,7 @@ hv_msg = (struct hv_kvp_msg *)incoming_cn_msg->data; key_name = (char *)hv_msg->body.kvp_enum_data.data.key; key_value = (char *)hv_msg->body.kvp_enum_data.data.value; -@@ -454,6 +460,7 @@ int main(void) +@@ -464,6 +470,7 @@ * already in the receive buffer. Update the cn_msg header to * reflect the key value that has been added to the message */ @@ -396,6 +396,3 @@ incoming_cn_msg->id.idx = CN_KVP_IDX; incoming_cn_msg->id.val = CN_KVP_VAL; --- -1.7.9.5 - diff -Nru linux-3.2.46/debian/patches/features/x86/hyperv/0074-Tools-hv-Fully-support-the-new-KVP-verbs-in-the-user.patch linux-3.2.46/debian/patches/features/x86/hyperv/0074-Tools-hv-Fully-support-the-new-KVP-verbs-in-the-user.patch --- linux-3.2.46/debian/patches/features/x86/hyperv/0074-Tools-hv-Fully-support-the-new-KVP-verbs-in-the-user.patch 2013-02-24 03:52:26.000000000 +0000 +++ linux-3.2.46/debian/patches/features/x86/hyperv/0074-Tools-hv-Fully-support-the-new-KVP-verbs-in-the-user.patch 2013-07-26 19:19:33.000000000 +0000 @@ -18,10 +18,10 @@ tools/hv/hv_kvp_daemon.c | 281 +++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 280 insertions(+), 1 deletion(-) -diff --git a/tools/hv/hv_kvp_daemon.c b/tools/hv/hv_kvp_daemon.c -index a98878c..2fb9c3d 100644 ---- a/tools/hv/hv_kvp_daemon.c -+++ b/tools/hv/hv_kvp_daemon.c +Index: linux-3.2.46/tools/hv/hv_kvp_daemon.c +=================================================================== +--- linux-3.2.46.orig/tools/hv/hv_kvp_daemon.c 2013-07-26 19:19:31.000000000 +0000 ++++ linux-3.2.46/tools/hv/hv_kvp_daemon.c 2013-07-26 19:19:32.000000000 +0000 @@ -39,7 +39,8 @@ #include #include @@ -32,7 +32,7 @@ /* * KVP protocol: The user mode component first registers with the -@@ -79,6 +80,250 @@ static char *os_build; +@@ -79,6 +80,250 @@ static char *lic_version; static struct utsname uts_buf; @@ -283,7 +283,7 @@ void kvp_get_os_info(void) { FILE *file; -@@ -315,6 +560,11 @@ int main(void) +@@ -315,6 +560,11 @@ */ kvp_get_os_info(); @@ -295,7 +295,7 @@ fd = socket(AF_NETLINK, SOCK_DGRAM, NETLINK_CONNECTOR); if (fd < 0) { syslog(LOG_ERR, "netlink socket creation failed; error:%d", fd); -@@ -389,9 +639,38 @@ int main(void) +@@ -399,9 +649,38 @@ } continue; @@ -334,6 +334,3 @@ default: break; } --- -1.7.9.5 - diff -Nru linux-3.2.46/debian/patches/features/x86/hyperv/0075-Tools-hv-Support-enumeration-from-all-the-pools.patch linux-3.2.46/debian/patches/features/x86/hyperv/0075-Tools-hv-Support-enumeration-from-all-the-pools.patch --- linux-3.2.46/debian/patches/features/x86/hyperv/0075-Tools-hv-Support-enumeration-from-all-the-pools.patch 2013-02-24 03:52:26.000000000 +0000 +++ linux-3.2.46/debian/patches/features/x86/hyperv/0075-Tools-hv-Support-enumeration-from-all-the-pools.patch 2013-07-26 19:19:35.000000000 +0000 @@ -17,11 +17,11 @@ tools/hv/hv_kvp_daemon.c | 124 +++++++++++++++++++++++++++++++++++++++++++--- 3 files changed, 122 insertions(+), 10 deletions(-) -diff --git a/drivers/hv/hv_kvp.c b/drivers/hv/hv_kvp.c -index cfe60b0..6186025 100644 ---- a/drivers/hv/hv_kvp.c -+++ b/drivers/hv/hv_kvp.c -@@ -289,14 +289,15 @@ kvp_respond_to_host(char *key, char *value, int error) +Index: linux-3.2.46/drivers/hv/hv_kvp.c +=================================================================== +--- linux-3.2.46.orig/drivers/hv/hv_kvp.c 2013-07-26 19:19:31.000000000 +0000 ++++ linux-3.2.46/drivers/hv/hv_kvp.c 2013-07-26 19:19:33.000000000 +0000 +@@ -289,14 +289,15 @@ /* @@ -40,11 +40,11 @@ goto response_done; } -diff --git a/include/linux/hyperv.h b/include/linux/hyperv.h -index e88a979..5852545 100644 ---- a/include/linux/hyperv.h -+++ b/include/linux/hyperv.h -@@ -952,6 +952,7 @@ void vmbus_driver_unregister(struct hv_driver *hv_driver); +Index: linux-3.2.46/include/linux/hyperv.h +=================================================================== +--- linux-3.2.46.orig/include/linux/hyperv.h 2013-07-26 19:19:31.000000000 +0000 ++++ linux-3.2.46/include/linux/hyperv.h 2013-07-26 19:19:33.000000000 +0000 +@@ -952,6 +952,7 @@ #define HV_S_OK 0x00000000 #define HV_E_FAIL 0x80004005 @@ -52,11 +52,11 @@ #define HV_ERROR_NOT_SUPPORTED 0x80070032 #define HV_ERROR_MACHINE_LOCKED 0x800704F7 -diff --git a/tools/hv/hv_kvp_daemon.c b/tools/hv/hv_kvp_daemon.c -index 2fb9c3d..146fd61 100644 ---- a/tools/hv/hv_kvp_daemon.c -+++ b/tools/hv/hv_kvp_daemon.c -@@ -148,6 +148,51 @@ static void kvp_update_file(int pool) +Index: linux-3.2.46/tools/hv/hv_kvp_daemon.c +=================================================================== +--- linux-3.2.46.orig/tools/hv/hv_kvp_daemon.c 2013-07-26 19:19:32.000000000 +0000 ++++ linux-3.2.46/tools/hv/hv_kvp_daemon.c 2013-07-26 19:19:33.000000000 +0000 +@@ -148,6 +148,51 @@ kvp_release_lock(pool); } @@ -108,7 +108,7 @@ static int kvp_file_init(void) { int ret, fd; -@@ -223,8 +268,16 @@ static int kvp_key_delete(int pool, __u8 *key, int key_size) +@@ -223,8 +268,16 @@ { int i; int j, k; @@ -127,7 +127,7 @@ for (i = 0; i < num_records; i++) { if (memcmp(key, record[i].key, key_size)) -@@ -259,14 +312,23 @@ static int kvp_key_add_or_modify(int pool, __u8 *key, int key_size, __u8 *value, +@@ -259,14 +312,23 @@ { int i; int j, k; @@ -154,7 +154,7 @@ for (i = 0; i < num_records; i++) { if (memcmp(key, record[i].key, key_size)) continue; -@@ -304,13 +366,21 @@ static int kvp_get_value(int pool, __u8 *key, int key_size, __u8 *value, +@@ -304,13 +366,21 @@ int value_size) { int i; @@ -178,7 +178,7 @@ for (i = 0; i < num_records; i++) { if (memcmp(key, record[i].key, key_size)) continue; -@@ -324,6 +394,31 @@ static int kvp_get_value(int pool, __u8 *key, int key_size, __u8 *value, +@@ -324,6 +394,31 @@ return 1; } @@ -210,7 +210,7 @@ void kvp_get_os_info(void) { FILE *file; -@@ -678,6 +773,21 @@ int main(void) +@@ -688,6 +783,21 @@ if (hv_msg->kvp_hdr.operation != KVP_OP_ENUMERATE) goto kvp_done; @@ -232,6 +232,3 @@ hv_msg = (struct hv_kvp_msg *)incoming_cn_msg->data; key_name = (char *)hv_msg->body.kvp_enum_data.data.key; key_value = (char *)hv_msg->body.kvp_enum_data.data.value; --- -1.7.9.5 - diff -Nru linux-3.2.46/debian/patches/features/x86/hyperv/0076-net-hyperv-Fix-the-code-handling-tx-busy.patch linux-3.2.46/debian/patches/features/x86/hyperv/0076-net-hyperv-Fix-the-code-handling-tx-busy.patch --- linux-3.2.46/debian/patches/features/x86/hyperv/0076-net-hyperv-Fix-the-code-handling-tx-busy.patch 2013-02-24 03:52:26.000000000 +0000 +++ linux-3.2.46/debian/patches/features/x86/hyperv/0076-net-hyperv-Fix-the-code-handling-tx-busy.patch 2013-07-26 19:19:36.000000000 +0000 @@ -22,11 +22,11 @@ drivers/net/hyperv/netvsc_drv.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) -diff --git a/drivers/net/hyperv/netvsc_drv.c b/drivers/net/hyperv/netvsc_drv.c -index 2517d20..dd29478 100644 ---- a/drivers/net/hyperv/netvsc_drv.c -+++ b/drivers/net/hyperv/netvsc_drv.c -@@ -223,13 +223,10 @@ static int netvsc_start_xmit(struct sk_buff *skb, struct net_device *net) +Index: linux-3.2.46/drivers/net/hyperv/netvsc_drv.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/hyperv/netvsc_drv.c 2013-07-26 19:19:30.000000000 +0000 ++++ linux-3.2.46/drivers/net/hyperv/netvsc_drv.c 2013-07-26 19:19:35.000000000 +0000 +@@ -223,13 +223,10 @@ net->stats.tx_bytes += skb->len; net->stats.tx_packets++; } else { @@ -41,6 +41,3 @@ } /* --- -1.7.9.5 - diff -Nru linux-3.2.46/debian/patches/features/x86/hyperv/0077-hv-remove-the-second-argument-of-k-un-map_atomic.patch linux-3.2.46/debian/patches/features/x86/hyperv/0077-hv-remove-the-second-argument-of-k-un-map_atomic.patch --- linux-3.2.46/debian/patches/features/x86/hyperv/0077-hv-remove-the-second-argument-of-k-un-map_atomic.patch 2013-02-24 03:52:26.000000000 +0000 +++ linux-3.2.46/debian/patches/features/x86/hyperv/0077-hv-remove-the-second-argument-of-k-un-map_atomic.patch 2013-07-26 19:19:37.000000000 +0000 @@ -12,11 +12,11 @@ drivers/scsi/storvsc_drv.c | 52 ++++++++++++++++++++++---------------------- 1 file changed, 26 insertions(+), 26 deletions(-) -diff --git a/drivers/scsi/storvsc_drv.c b/drivers/scsi/storvsc_drv.c -index 695ffc3..83a1972 100644 ---- a/drivers/scsi/storvsc_drv.c -+++ b/drivers/scsi/storvsc_drv.c -@@ -481,6 +481,19 @@ cleanup: +Index: linux-3.2.46/drivers/scsi/storvsc_drv.c +=================================================================== +--- linux-3.2.46.orig/drivers/scsi/storvsc_drv.c 2013-07-26 19:19:22.000000000 +0000 ++++ linux-3.2.46/drivers/scsi/storvsc_drv.c 2013-07-26 19:19:36.000000000 +0000 +@@ -482,6 +482,19 @@ return NULL; } @@ -36,7 +36,7 @@ /* Assume the original sgl has enough room */ static unsigned int copy_from_bounce_buffer(struct scatterlist *orig_sgl, struct scatterlist *bounce_sgl, -@@ -499,15 +512,12 @@ static unsigned int copy_from_bounce_buffer(struct scatterlist *orig_sgl, +@@ -500,15 +513,12 @@ local_irq_save(flags); for (i = 0; i < orig_sgl_count; i++) { @@ -54,7 +54,7 @@ while (destlen) { src = bounce_addr + bounce_sgl[j].offset; -@@ -523,7 +533,7 @@ static unsigned int copy_from_bounce_buffer(struct scatterlist *orig_sgl, +@@ -524,7 +534,7 @@ if (bounce_sgl[j].offset == bounce_sgl[j].length) { /* full */ @@ -63,7 +63,7 @@ j++; /* -@@ -537,26 +547,21 @@ static unsigned int copy_from_bounce_buffer(struct scatterlist *orig_sgl, +@@ -538,26 +548,21 @@ /* * We are done; cleanup and return. */ @@ -94,7 +94,7 @@ } local_irq_restore(flags); -@@ -581,15 +586,12 @@ static unsigned int copy_to_bounce_buffer(struct scatterlist *orig_sgl, +@@ -582,15 +587,12 @@ local_irq_save(flags); for (i = 0; i < orig_sgl_count; i++) { @@ -112,7 +112,7 @@ while (srclen) { /* assume bounce offset always == 0 */ -@@ -606,22 +608,20 @@ static unsigned int copy_to_bounce_buffer(struct scatterlist *orig_sgl, +@@ -607,22 +609,20 @@ if (bounce_sgl[j].length == PAGE_SIZE) { /* full..move to next entry */ @@ -139,6 +139,3 @@ } local_irq_restore(flags); --- -1.7.9.5 - diff -Nru linux-3.2.46/debian/patches/features/x86/hyperv/0078-libata-add-a-host-flag-to-ignore-detected-ATA-device.patch linux-3.2.46/debian/patches/features/x86/hyperv/0078-libata-add-a-host-flag-to-ignore-detected-ATA-device.patch --- linux-3.2.46/debian/patches/features/x86/hyperv/0078-libata-add-a-host-flag-to-ignore-detected-ATA-device.patch 2013-02-24 03:52:26.000000000 +0000 +++ linux-3.2.46/debian/patches/features/x86/hyperv/0078-libata-add-a-host-flag-to-ignore-detected-ATA-device.patch 2013-07-26 19:19:38.000000000 +0000 @@ -15,11 +15,11 @@ include/linux/libata.h | 1 + 2 files changed, 7 insertions(+) -diff --git a/drivers/ata/libata-core.c b/drivers/ata/libata-core.c -index 23763a1..d31ee55 100644 ---- a/drivers/ata/libata-core.c -+++ b/drivers/ata/libata-core.c -@@ -1973,6 +1973,12 @@ retry: +Index: linux-3.2.46/drivers/ata/libata-core.c +=================================================================== +--- linux-3.2.46.orig/drivers/ata/libata-core.c 2013-07-26 18:55:49.000000000 +0000 ++++ linux-3.2.46/drivers/ata/libata-core.c 2013-07-26 19:19:37.000000000 +0000 +@@ -1972,6 +1972,12 @@ if (class == ATA_DEV_ATA) { if (!ata_id_is_ata(id) && !ata_id_is_cfa(id)) goto err_out; @@ -32,11 +32,11 @@ } else { if (ata_id_is_ata(id)) goto err_out; -diff --git a/include/linux/libata.h b/include/linux/libata.h -index e926df7..6e887c7 100644 ---- a/include/linux/libata.h -+++ b/include/linux/libata.h -@@ -247,6 +247,7 @@ enum { +Index: linux-3.2.46/include/linux/libata.h +=================================================================== +--- linux-3.2.46.orig/include/linux/libata.h 2013-07-26 18:55:49.000000000 +0000 ++++ linux-3.2.46/include/linux/libata.h 2013-07-26 19:19:37.000000000 +0000 +@@ -247,6 +247,7 @@ ATA_HOST_SIMPLEX = (1 << 0), /* Host is simplex, one DMA channel per host only */ ATA_HOST_STARTED = (1 << 1), /* Host started */ ATA_HOST_PARALLEL_SCAN = (1 << 2), /* Ports on this host can be scanned in parallel */ @@ -44,6 +44,3 @@ /* bits 24:31 of host->flags are reserved for LLD specific flags */ --- -1.7.10 - diff -Nru linux-3.2.46/debian/patches/features/x86/hyperv/0079-ata_piix-defer-disks-to-the-Hyper-V-drivers-by-defau.patch linux-3.2.46/debian/patches/features/x86/hyperv/0079-ata_piix-defer-disks-to-the-Hyper-V-drivers-by-defau.patch --- linux-3.2.46/debian/patches/features/x86/hyperv/0079-ata_piix-defer-disks-to-the-Hyper-V-drivers-by-defau.patch 2013-02-24 03:52:26.000000000 +0000 +++ linux-3.2.46/debian/patches/features/x86/hyperv/0079-ata_piix-defer-disks-to-the-Hyper-V-drivers-by-defau.patch 2013-07-26 19:19:40.000000000 +0000 @@ -23,11 +23,11 @@ drivers/ata/ata_piix.c | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) -diff --git a/drivers/ata/ata_piix.c b/drivers/ata/ata_piix.c -index 7857e8f..3c809bf 100644 ---- a/drivers/ata/ata_piix.c -+++ b/drivers/ata/ata_piix.c -@@ -1554,6 +1554,39 @@ static bool piix_broken_system_poweroff(struct pci_dev *pdev) +Index: linux-3.2.46/drivers/ata/ata_piix.c +=================================================================== +--- linux-3.2.46.orig/drivers/ata/ata_piix.c 2013-07-26 18:55:49.000000000 +0000 ++++ linux-3.2.46/drivers/ata/ata_piix.c 2013-07-26 19:19:39.000000000 +0000 +@@ -1584,6 +1584,39 @@ return false; } @@ -67,7 +67,7 @@ /** * piix_init_one - Register PIIX ATA PCI device with kernel services * @pdev: PCI device to register -@@ -1669,6 +1702,9 @@ static int __devinit piix_init_one(struct pci_dev *pdev, +@@ -1699,6 +1732,9 @@ } host->flags |= ATA_HOST_PARALLEL_SCAN; @@ -77,6 +77,3 @@ pci_set_master(pdev); return ata_pci_sff_activate_host(host, ata_bmdma_interrupt, sht); } --- -1.7.10 - diff -Nru linux-3.2.46/debian/patches/features/x86/hyperv/0080-ata_piix-reenable-ms-virtual-pc-guests.patch linux-3.2.46/debian/patches/features/x86/hyperv/0080-ata_piix-reenable-ms-virtual-pc-guests.patch --- linux-3.2.46/debian/patches/features/x86/hyperv/0080-ata_piix-reenable-ms-virtual-pc-guests.patch 2013-03-02 23:56:24.000000000 +0000 +++ linux-3.2.46/debian/patches/features/x86/hyperv/0080-ata_piix-reenable-ms-virtual-pc-guests.patch 2013-07-26 19:19:41.000000000 +0000 @@ -104,11 +104,11 @@ drivers/ata/ata_piix.c | 25 ++++++++++++++++++++++--- 1 file changed, 22 insertions(+), 3 deletions(-) -diff --git a/drivers/ata/ata_piix.c b/drivers/ata/ata_piix.c -index ef773e1..bec35f4 100644 ---- a/drivers/ata/ata_piix.c -+++ b/drivers/ata/ata_piix.c -@@ -1585,12 +1585,31 @@ static void piix_ignore_devices_quirk(struct ata_host *host) +Index: linux-3.2.46/drivers/ata/ata_piix.c +=================================================================== +--- linux-3.2.46.orig/drivers/ata/ata_piix.c 2013-07-26 19:19:39.000000000 +0000 ++++ linux-3.2.46/drivers/ata/ata_piix.c 2013-07-26 19:19:40.000000000 +0000 +@@ -1607,12 +1607,31 @@ }, { } /* terminate list */ }; diff -Nru linux-3.2.46/debian/patches/features/x86/x86-Add-amilo-rfkill-driver-for-some-Fujitsu-Siemens.patch linux-3.2.46/debian/patches/features/x86/x86-Add-amilo-rfkill-driver-for-some-Fujitsu-Siemens.patch --- linux-3.2.46/debian/patches/features/x86/x86-Add-amilo-rfkill-driver-for-some-Fujitsu-Siemens.patch 2013-04-11 03:27:32.000000000 +0000 +++ linux-3.2.46/debian/patches/features/x86/x86-Add-amilo-rfkill-driver-for-some-Fujitsu-Siemens.patch 2013-07-26 19:17:27.000000000 +0000 @@ -22,11 +22,11 @@ 3 files changed, 181 insertions(+), 0 deletions(-) create mode 100644 drivers/platform/x86/amilo-rfkill.c -diff --git a/drivers/platform/x86/Kconfig b/drivers/platform/x86/Kconfig -index 7f43cf8..cb2c255 100644 ---- a/drivers/platform/x86/Kconfig -+++ b/drivers/platform/x86/Kconfig -@@ -143,6 +143,13 @@ config FUJITSU_LAPTOP_DEBUG +Index: linux-3.2.46/drivers/platform/x86/Kconfig +=================================================================== +--- linux-3.2.46.orig/drivers/platform/x86/Kconfig 2013-07-26 18:56:32.000000000 +0000 ++++ linux-3.2.46/drivers/platform/x86/Kconfig 2013-07-26 19:17:26.000000000 +0000 +@@ -143,6 +143,13 @@ If you are not sure, say N here. @@ -40,11 +40,11 @@ config TC1100_WMI tristate "HP Compaq TC1100 Tablet WMI Extras (EXPERIMENTAL)" depends on !X86_64 -diff --git a/drivers/platform/x86/Makefile b/drivers/platform/x86/Makefile -index 293a320..3acbaad 100644 ---- a/drivers/platform/x86/Makefile -+++ b/drivers/platform/x86/Makefile -@@ -17,6 +17,7 @@ obj-$(CONFIG_ACER_WMI) += acer-wmi.o +Index: linux-3.2.46/drivers/platform/x86/Makefile +=================================================================== +--- linux-3.2.46.orig/drivers/platform/x86/Makefile 2013-07-26 18:56:32.000000000 +0000 ++++ linux-3.2.46/drivers/platform/x86/Makefile 2013-07-26 19:17:26.000000000 +0000 +@@ -17,6 +17,7 @@ obj-$(CONFIG_ACERHDF) += acerhdf.o obj-$(CONFIG_HP_ACCEL) += hp_accel.o obj-$(CONFIG_HP_WMI) += hp-wmi.o @@ -52,11 +52,10 @@ obj-$(CONFIG_TC1100_WMI) += tc1100-wmi.o obj-$(CONFIG_SONY_LAPTOP) += sony-laptop.o obj-$(CONFIG_IDEAPAD_LAPTOP) += ideapad-laptop.o -diff --git a/drivers/platform/x86/amilo-rfkill.c b/drivers/platform/x86/amilo-rfkill.c -new file mode 100644 -index 0000000..19170bb ---- /dev/null -+++ b/drivers/platform/x86/amilo-rfkill.c +Index: linux-3.2.46/drivers/platform/x86/amilo-rfkill.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/platform/x86/amilo-rfkill.c 2013-07-26 19:17:26.000000000 +0000 @@ -0,0 +1,173 @@ +/* + * Support for rfkill on some Fujitsu-Siemens Amilo laptops. @@ -231,6 +230,3 @@ + +module_init(amilo_rfkill_init); +module_exit(amilo_rfkill_exit); --- -1.7.7.3 - diff -Nru linux-3.2.46/debian/patches/rpi/rpi_100_ec2ea6bacf5427a2cebac2aae4c359db286510c9.patch linux-3.2.46/debian/patches/rpi/rpi_100_ec2ea6bacf5427a2cebac2aae4c359db286510c9.patch --- linux-3.2.46/debian/patches/rpi/rpi_100_ec2ea6bacf5427a2cebac2aae4c359db286510c9.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_100_ec2ea6bacf5427a2cebac2aae4c359db286510c9.patch 2013-07-26 19:31:51.000000000 +0000 @@ -0,0 +1,126752 @@ +commit ec2ea6bacf5427a2cebac2aae4c359db286510c9 +Author: popcornmix +Date: Tue Jan 17 19:14:08 2012 +0000 + + Add dwc_otg driver + + Signed-off-by: popcornmix + +Index: linux-3.2.46/drivers/usb/Makefile +=================================================================== +--- linux-3.2.46.orig/drivers/usb/Makefile 2013-07-26 18:52:05.000000000 +0000 ++++ linux-3.2.46/drivers/usb/Makefile 2013-07-26 19:31:19.000000000 +0000 +@@ -23,6 +23,7 @@ + obj-$(CONFIG_USB_R8A66597_HCD) += host/ + obj-$(CONFIG_USB_HWA_HCD) += host/ + obj-$(CONFIG_USB_ISP1760_HCD) += host/ ++obj-$(CONFIG_USB_DWCOTG) += host/ + obj-$(CONFIG_USB_IMX21_HCD) += host/ + obj-$(CONFIG_USB_FSL_MPH_DR_OF) += host/ + +Index: linux-3.2.46/drivers/usb/core/generic.c +=================================================================== +--- linux-3.2.46.orig/drivers/usb/core/generic.c 2013-07-26 18:52:05.000000000 +0000 ++++ linux-3.2.46/drivers/usb/core/generic.c 2013-07-26 19:31:19.000000000 +0000 +@@ -149,6 +149,7 @@ + dev_warn(&udev->dev, + "no configuration chosen from %d choice%s\n", + num_configs, plural(num_configs)); ++ dev_warn(&udev->dev, "No support over %dmA\n", udev->bus_mA); + } + return i; + } +Index: linux-3.2.46/drivers/usb/core/hub.c +=================================================================== +--- linux-3.2.46.orig/drivers/usb/core/hub.c 2013-07-26 18:52:05.000000000 +0000 ++++ linux-3.2.46/drivers/usb/core/hub.c 2013-07-26 19:31:19.000000000 +0000 +@@ -24,7 +24,6 @@ + #include + #include + #include +-#include + + #include + #include +@@ -1138,6 +1137,8 @@ + INIT_WORK(&hub->tt.clear_work, hub_tt_work); + switch (hdev->descriptor.bDeviceProtocol) { + case 0: ++ dev_dbg(hub_dev, "TT with no hub-specific protocol - " ++ "no TT\n"); + break; + case 1: + dev_dbg(hub_dev, "Single TT\n"); +@@ -1154,6 +1155,7 @@ + hub->tt.hub = hdev; + break; + case 3: ++ dev_dbg(hub_dev, "USB 3.0 hub - no TT\n"); + /* USB 3.0 hubs don't have a TT */ + break; + default: +@@ -1783,6 +1785,12 @@ + #endif + + #ifdef CONFIG_USB_OTG ++ ++static int enable_whitelist; ++module_param(enable_whitelist, bool, S_IRUGO | S_IWUSR); ++MODULE_PARM_DESC(enable_whitelist, ++ "only recognize devices in OTG whitelist if true"); ++ + #include "otg_whitelist.h" + #endif + +@@ -1837,9 +1845,15 @@ + dev_info(&udev->dev, + "can't set HNP mode: %d\n", + err); ++ dev_printk(KERN_CRIT, &udev->dev, ++ "Not Connected/Responding\n"); ++ + bus->b_hnp_enable = 0; ++ } else { ++ dev_info(&udev->dev, ++ "HNP Not Supported\n"); + } +- } ++ } + } + } + +@@ -1848,12 +1862,27 @@ + /* Maybe it can talk to us, though we can't talk to it. + * (Includes HNP test device.) + */ +- if (udev->bus->b_hnp_enable || udev->bus->is_b_host) { ++ if (udev->bus->b_hnp_enable || udev->bus->is_b_host || ++ udev->descriptor.idVendor == 0x1a0a) { + err = usb_port_suspend(udev, PMSG_SUSPEND); +- if (err < 0) ++ if (err < 0) { + dev_dbg(&udev->dev, "HNP fail, %d\n", err); ++ } else { ++ /* Return Connection Refused(ECONNREFUSED) ++ * instead of No Device(ENODEV) so that the ++ * retry loop in hub_port_connect_change() is ++ * exited without disabling the port ++ */ ++ err = -ECONNREFUSED; ++ goto fail; ++ } + } +- err = -ENOTSUPP; ++ //err = -ENOTSUPP; ++ /* Return Not Connected (ENOTCONN) instead of No ++ * Device(ENODEV) so that the retry loop in ++ * hub_port_connect_change() is exited ++ */ ++ err = -ENOTCONN; + goto fail; + } + fail: +@@ -1964,14 +1993,6 @@ + /* Tell the world! */ + announce_device(udev); + +- if (udev->serial) +- add_device_randomness(udev->serial, strlen(udev->serial)); +- if (udev->product) +- add_device_randomness(udev->product, strlen(udev->product)); +- if (udev->manufacturer) +- add_device_randomness(udev->manufacturer, +- strlen(udev->manufacturer)); +- + device_enable_async_suspend(&udev->dev); + /* Register the device. The device driver is responsible + * for configuring the device and invoking the add-device +@@ -2511,9 +2532,9 @@ + status = 0; + } else { + /* device has up to 10 msec to fully suspend */ +- dev_dbg(&udev->dev, "usb %ssuspend, wakeup %d\n", ++ /*dev_dbg(&udev->dev, "usb %ssuspend, wakeup %d\n", + (PMSG_IS_AUTO(msg) ? "auto-" : ""), +- udev->do_remote_wakeup); ++ udev->do_remote_wakeup);*/ + usb_set_device_state(udev, USB_STATE_SUSPENDED); + msleep(10); + } +@@ -3069,7 +3090,9 @@ + buf->bMaxPacketSize0 = 0; + r = usb_control_msg(udev, usb_rcvaddr0pipe(), + USB_REQ_GET_DESCRIPTOR, USB_DIR_IN, +- USB_DT_DEVICE << 8, 0, ++ USB_DT_DEVICE << 8, ++ //USB_DT_DEVICE << 64, // DWC patch suggestion! ++ 0, + buf, GET_DESCRIPTOR_BUFSIZE, + initial_descriptor_timeout); + switch (buf->bMaxPacketSize0) { +@@ -3515,8 +3538,10 @@ + release_devnum(udev); + hub_free_dev(udev); + usb_put_dev(udev); +- if ((status == -ENOTCONN) || (status == -ENOTSUPP)) +- break; ++ if (status == -ENOTCONN || status == -ENOTSUPP || ++ status == -ECONNREFUSED) ++ // break; //DWC patch ++ return; + } + if (hub->hdev->parent || + !hcd->driver->port_handed_over || +Index: linux-3.2.46/drivers/usb/core/message.c +=================================================================== +--- linux-3.2.46.orig/drivers/usb/core/message.c 2013-07-26 18:52:05.000000000 +0000 ++++ linux-3.2.46/drivers/usb/core/message.c 2013-07-26 19:31:19.000000000 +0000 +@@ -1847,6 +1847,85 @@ + if (cp->string == NULL && + !(dev->quirks & USB_QUIRK_CONFIG_INTF_STRINGS)) + cp->string = usb_cache_string(dev, cp->desc.iConfiguration); ++/* Uncomment this define to enable the HS Electrical Test support */ ++#define DWC_HS_ELECT_TST 1 ++#ifdef DWC_HS_ELECT_TST ++ /* Here we implement the HS Electrical Test support. The ++ * tester uses a vendor ID of 0x1A0A to indicate we should ++ * run a special test sequence. The product ID tells us ++ * which sequence to run. We invoke the test sequence by ++ * sending a non-standard SetFeature command to our root ++ * hub port. Our dwc_otg_hcd_hub_control() routine will ++ * recognize the command and perform the desired test ++ * sequence. ++ */ ++ if (dev->descriptor.idVendor == 0x1A0A) { ++ /* HSOTG Electrical Test */ ++ dev_warn(&dev->dev, "VID from HSOTG Electrical Test Fixture\n"); ++ ++ if (dev->bus && dev->bus->root_hub) { ++ struct usb_device *hdev = dev->bus->root_hub; ++ dev_warn(&dev->dev, "Got PID 0x%x\n", dev->descriptor.idProduct); ++ ++ switch (dev->descriptor.idProduct) { ++ case 0x0101: /* TEST_SE0_NAK */ ++ dev_warn(&dev->dev, "TEST_SE0_NAK\n"); ++ usb_control_msg(hdev, usb_sndctrlpipe(hdev, 0), ++ USB_REQ_SET_FEATURE, USB_RT_PORT, ++ USB_PORT_FEAT_TEST, 0x300, NULL, 0, HZ); ++ break; ++ ++ case 0x0102: /* TEST_J */ ++ dev_warn(&dev->dev, "TEST_J\n"); ++ usb_control_msg(hdev, usb_sndctrlpipe(hdev, 0), ++ USB_REQ_SET_FEATURE, USB_RT_PORT, ++ USB_PORT_FEAT_TEST, 0x100, NULL, 0, HZ); ++ break; ++ ++ case 0x0103: /* TEST_K */ ++ dev_warn(&dev->dev, "TEST_K\n"); ++ usb_control_msg(hdev, usb_sndctrlpipe(hdev, 0), ++ USB_REQ_SET_FEATURE, USB_RT_PORT, ++ USB_PORT_FEAT_TEST, 0x200, NULL, 0, HZ); ++ break; ++ ++ case 0x0104: /* TEST_PACKET */ ++ dev_warn(&dev->dev, "TEST_PACKET\n"); ++ usb_control_msg(hdev, usb_sndctrlpipe(hdev, 0), ++ USB_REQ_SET_FEATURE, USB_RT_PORT, ++ USB_PORT_FEAT_TEST, 0x400, NULL, 0, HZ); ++ break; ++ ++ case 0x0105: /* TEST_FORCE_ENABLE */ ++ dev_warn(&dev->dev, "TEST_FORCE_ENABLE\n"); ++ usb_control_msg(hdev, usb_sndctrlpipe(hdev, 0), ++ USB_REQ_SET_FEATURE, USB_RT_PORT, ++ USB_PORT_FEAT_TEST, 0x500, NULL, 0, HZ); ++ break; ++ ++ case 0x0106: /* HS_HOST_PORT_SUSPEND_RESUME */ ++ dev_warn(&dev->dev, "HS_HOST_PORT_SUSPEND_RESUME\n"); ++ usb_control_msg(hdev, usb_sndctrlpipe(hdev, 0), ++ USB_REQ_SET_FEATURE, USB_RT_PORT, ++ USB_PORT_FEAT_TEST, 0x600, NULL, 0, 40 * HZ); ++ break; ++ ++ case 0x0107: /* SINGLE_STEP_GET_DEVICE_DESCRIPTOR setup */ ++ dev_warn(&dev->dev, "SINGLE_STEP_GET_DEVICE_DESCRIPTOR setup\n"); ++ usb_control_msg(hdev, usb_sndctrlpipe(hdev, 0), ++ USB_REQ_SET_FEATURE, USB_RT_PORT, ++ USB_PORT_FEAT_TEST, 0x700, NULL, 0, 40 * HZ); ++ break; ++ ++ case 0x0108: /* SINGLE_STEP_GET_DEVICE_DESCRIPTOR execute */ ++ dev_warn(&dev->dev, "SINGLE_STEP_GET_DEVICE_DESCRIPTOR execute\n"); ++ usb_control_msg(hdev, usb_sndctrlpipe(hdev, 0), ++ USB_REQ_SET_FEATURE, USB_RT_PORT, ++ USB_PORT_FEAT_TEST, 0x800, NULL, 0, 40 * HZ); ++ } ++ } ++ } ++#endif /* DWC_HS_ELECT_TST */ + + /* Now that all the interfaces are set up, register them + * to trigger binding of drivers to interfaces. probe() +Index: linux-3.2.46/drivers/usb/core/otg_whitelist.h +=================================================================== +--- linux-3.2.46.orig/drivers/usb/core/otg_whitelist.h 2013-07-26 18:52:05.000000000 +0000 ++++ linux-3.2.46/drivers/usb/core/otg_whitelist.h 2013-07-26 19:31:19.000000000 +0000 +@@ -19,33 +19,82 @@ + static struct usb_device_id whitelist_table [] = { + + /* hubs are optional in OTG, but very handy ... */ ++#define CERT_WITHOUT_HUBS ++#if defined(CERT_WITHOUT_HUBS) ++{ USB_DEVICE( 0x0000, 0x0000 ), }, /* Root HUB Only*/ ++#else + { USB_DEVICE_INFO(USB_CLASS_HUB, 0, 0), }, + { USB_DEVICE_INFO(USB_CLASS_HUB, 0, 1), }, ++{ USB_DEVICE_INFO(USB_CLASS_HUB, 0, 2), }, ++#endif + + #ifdef CONFIG_USB_PRINTER /* ignoring nonstatic linkage! */ + /* FIXME actually, printers are NOT supposed to use device classes; + * they're supposed to use interface classes... + */ +-{ USB_DEVICE_INFO(7, 1, 1) }, +-{ USB_DEVICE_INFO(7, 1, 2) }, +-{ USB_DEVICE_INFO(7, 1, 3) }, ++//{ USB_DEVICE_INFO(7, 1, 1) }, ++//{ USB_DEVICE_INFO(7, 1, 2) }, ++//{ USB_DEVICE_INFO(7, 1, 3) }, + #endif + + #ifdef CONFIG_USB_NET_CDCETHER + /* Linux-USB CDC Ethernet gadget */ +-{ USB_DEVICE(0x0525, 0xa4a1), }, ++//{ USB_DEVICE(0x0525, 0xa4a1), }, + /* Linux-USB CDC Ethernet + RNDIS gadget */ +-{ USB_DEVICE(0x0525, 0xa4a2), }, ++//{ USB_DEVICE(0x0525, 0xa4a2), }, + #endif + + #if defined(CONFIG_USB_TEST) || defined(CONFIG_USB_TEST_MODULE) + /* gadget zero, for testing */ +-{ USB_DEVICE(0x0525, 0xa4a0), }, ++//{ USB_DEVICE(0x0525, 0xa4a0), }, + #endif ++ ++/* OPT Tester */ ++{ USB_DEVICE( 0x1a0a, 0x0101 ), }, /* TEST_SE0_NAK */ ++{ USB_DEVICE( 0x1a0a, 0x0102 ), }, /* Test_J */ ++{ USB_DEVICE( 0x1a0a, 0x0103 ), }, /* Test_K */ ++{ USB_DEVICE( 0x1a0a, 0x0104 ), }, /* Test_PACKET */ ++{ USB_DEVICE( 0x1a0a, 0x0105 ), }, /* Test_FORCE_ENABLE */ ++{ USB_DEVICE( 0x1a0a, 0x0106 ), }, /* HS_PORT_SUSPEND_RESUME */ ++{ USB_DEVICE( 0x1a0a, 0x0107 ), }, /* SINGLE_STEP_GET_DESCRIPTOR setup */ ++{ USB_DEVICE( 0x1a0a, 0x0108 ), }, /* SINGLE_STEP_GET_DESCRIPTOR execute */ ++ ++/* Sony cameras */ ++{ USB_DEVICE_VER(0x054c,0x0010,0x0410, 0x0500), }, ++ ++/* Memory Devices */ ++//{ USB_DEVICE( 0x0781, 0x5150 ), }, /* SanDisk */ ++//{ USB_DEVICE( 0x05DC, 0x0080 ), }, /* Lexar */ ++//{ USB_DEVICE( 0x4146, 0x9281 ), }, /* IOMEGA */ ++//{ USB_DEVICE( 0x067b, 0x2507 ), }, /* Hammer 20GB External HD */ ++{ USB_DEVICE( 0x0EA0, 0x2168 ), }, /* Ours Technology Inc. (BUFFALO ClipDrive)*/ ++//{ USB_DEVICE( 0x0457, 0x0150 ), }, /* Silicon Integrated Systems Corp. */ ++ ++/* HP Printers */ ++//{ USB_DEVICE( 0x03F0, 0x1102 ), }, /* HP Photosmart 245 */ ++//{ USB_DEVICE( 0x03F0, 0x1302 ), }, /* HP Photosmart 370 Series */ ++ ++/* Speakers */ ++//{ USB_DEVICE( 0x0499, 0x3002 ), }, /* YAMAHA YST-MS35D USB Speakers */ ++//{ USB_DEVICE( 0x0672, 0x1041 ), }, /* Labtec USB Headset */ + + { } /* Terminating entry */ + }; + ++static inline void report_errors(struct usb_device *dev) ++{ ++ /* OTG MESSAGE: report errors here, customize to match your product */ ++ dev_info(&dev->dev, "device Vendor:%04x Product:%04x is not supported\n", ++ le16_to_cpu(dev->descriptor.idVendor), ++ le16_to_cpu(dev->descriptor.idProduct)); ++ if (USB_CLASS_HUB == dev->descriptor.bDeviceClass){ ++ dev_printk(KERN_CRIT, &dev->dev, "Unsupported Hub Topology\n"); ++ } else { ++ dev_printk(KERN_CRIT, &dev->dev, "Attached Device is not Supported\n"); ++ } ++} ++ ++ + static int is_targeted(struct usb_device *dev) + { + struct usb_device_id *id = whitelist_table; +@@ -55,58 +104,83 @@ + return 1; + + /* HNP test device is _never_ targeted (see OTG spec 6.6.6) */ +- if ((le16_to_cpu(dev->descriptor.idVendor) == 0x1a0a && +- le16_to_cpu(dev->descriptor.idProduct) == 0xbadd)) +- return 0; ++ if (dev->descriptor.idVendor == 0x1a0a && ++ dev->descriptor.idProduct == 0xbadd) { ++ return 0; ++ } else if (!enable_whitelist) { ++ return 1; ++ } else { + +- /* NOTE: can't use usb_match_id() since interface caches +- * aren't set up yet. this is cut/paste from that code. +- */ +- for (id = whitelist_table; id->match_flags; id++) { +- if ((id->match_flags & USB_DEVICE_ID_MATCH_VENDOR) && +- id->idVendor != le16_to_cpu(dev->descriptor.idVendor)) +- continue; +- +- if ((id->match_flags & USB_DEVICE_ID_MATCH_PRODUCT) && +- id->idProduct != le16_to_cpu(dev->descriptor.idProduct)) +- continue; +- +- /* No need to test id->bcdDevice_lo != 0, since 0 is never +- greater than any unsigned number. */ +- if ((id->match_flags & USB_DEVICE_ID_MATCH_DEV_LO) && +- (id->bcdDevice_lo > le16_to_cpu(dev->descriptor.bcdDevice))) +- continue; +- +- if ((id->match_flags & USB_DEVICE_ID_MATCH_DEV_HI) && +- (id->bcdDevice_hi < le16_to_cpu(dev->descriptor.bcdDevice))) +- continue; +- +- if ((id->match_flags & USB_DEVICE_ID_MATCH_DEV_CLASS) && +- (id->bDeviceClass != dev->descriptor.bDeviceClass)) +- continue; +- +- if ((id->match_flags & USB_DEVICE_ID_MATCH_DEV_SUBCLASS) && +- (id->bDeviceSubClass != dev->descriptor.bDeviceSubClass)) +- continue; +- +- if ((id->match_flags & USB_DEVICE_ID_MATCH_DEV_PROTOCOL) && +- (id->bDeviceProtocol != dev->descriptor.bDeviceProtocol)) +- continue; ++#ifdef DEBUG ++ dev_dbg(&dev->dev, "device V:%04x P:%04x DC:%04x SC:%04x PR:%04x \n", ++ dev->descriptor.idVendor, ++ dev->descriptor.idProduct, ++ dev->descriptor.bDeviceClass, ++ dev->descriptor.bDeviceSubClass, ++ dev->descriptor.bDeviceProtocol); ++#endif + + return 1; ++ /* NOTE: can't use usb_match_id() since interface caches ++ * aren't set up yet. this is cut/paste from that code. ++ */ ++ for (id = whitelist_table; id->match_flags; id++) { ++#ifdef DEBUG ++ dev_dbg(&dev->dev, ++ "ID: V:%04x P:%04x DC:%04x SC:%04x PR:%04x \n", ++ id->idVendor, ++ id->idProduct, ++ id->bDeviceClass, ++ id->bDeviceSubClass, ++ id->bDeviceProtocol); ++#endif ++ ++ if ((id->match_flags & USB_DEVICE_ID_MATCH_VENDOR) && ++ id->idVendor != le16_to_cpu(dev->descriptor.idVendor)) ++ continue; ++ ++ if ((id->match_flags & USB_DEVICE_ID_MATCH_PRODUCT) && ++ id->idProduct != le16_to_cpu(dev->descriptor.idProduct)) ++ continue; ++ ++ /* No need to test id->bcdDevice_lo != 0, since 0 is never ++ greater than any unsigned number. */ ++ if ((id->match_flags & USB_DEVICE_ID_MATCH_DEV_LO) && ++ (id->bcdDevice_lo > le16_to_cpu(dev->descriptor.bcdDevice))) ++ continue; ++ ++ if ((id->match_flags & USB_DEVICE_ID_MATCH_DEV_HI) && ++ (id->bcdDevice_hi < le16_to_cpu(dev->descriptor.bcdDevice))) ++ continue; ++ ++ if ((id->match_flags & USB_DEVICE_ID_MATCH_DEV_CLASS) && ++ (id->bDeviceClass != dev->descriptor.bDeviceClass)) ++ continue; ++ ++ if ((id->match_flags & USB_DEVICE_ID_MATCH_DEV_SUBCLASS) && ++ (id->bDeviceSubClass != dev->descriptor.bDeviceSubClass)) ++ continue; ++ ++ if ((id->match_flags & USB_DEVICE_ID_MATCH_DEV_PROTOCOL) && ++ (id->bDeviceProtocol != dev->descriptor.bDeviceProtocol)) ++ continue; ++ ++ return 1; ++ } + } + + /* add other match criteria here ... */ + +- +- /* OTG MESSAGE: report errors here, customize to match your product */ +- dev_err(&dev->dev, "device v%04x p%04x is not supported\n", +- le16_to_cpu(dev->descriptor.idVendor), +- le16_to_cpu(dev->descriptor.idProduct)); + #ifdef CONFIG_USB_OTG_WHITELIST ++ report_errors(dev); + return 0; + #else +- return 1; ++ if (enable_whitelist) { ++ report_errors(dev); ++ return 0; ++ } else { ++ return 1; ++ } + #endif + } + +Index: linux-3.2.46/drivers/usb/gadget/Kconfig +=================================================================== +--- linux-3.2.46.orig/drivers/usb/gadget/Kconfig 2013-07-26 18:52:05.000000000 +0000 ++++ linux-3.2.46/drivers/usb/gadget/Kconfig 2013-07-26 19:31:19.000000000 +0000 +@@ -552,6 +552,34 @@ + depends on USB_GADGET + depends on USB_GADGET_DUALSPEED + ++config USB_GADGET_SNPS_DWC_OTG ++ boolean "Synopsys Driver for DWC_otg Controller" ++ depends on USB && EXPERIMENTAL ++ select USB_OTG ++ select USB_GADGET_DUALSPEED ++ help ++ Selects the Synopsys Driver for the DWC_otg Controller. ++ ++config USB_DWC_OTG_LPM ++ boolean "Enable LPM support" ++ depends on USB && EXPERIMENTAL ++ help ++ Enables LPM support. ++ ++config USB_GADGET_SNPS_DWC_OTG ++ boolean "Synopsys Driver for DWC_otg Controller" ++ depends on USB && EXPERIMENTAL ++ select USB_OTG ++ select USB_GADGET_DUALSPEED ++ help ++ Selects the Synopsys Driver for the DWC_otg Controller. ++ ++config USB_DWC_OTG_LPM ++ boolean "Enable LPM support" ++ depends on USB && EXPERIMENTAL ++ help ++ Enables LPM support. ++ + # + # USB Gadget Drivers + # +Index: linux-3.2.46/drivers/usb/gadget/file_storage.c +=================================================================== +--- linux-3.2.46.orig/drivers/usb/gadget/file_storage.c 2013-07-26 18:52:05.000000000 +0000 ++++ linux-3.2.46/drivers/usb/gadget/file_storage.c 2013-07-26 19:31:19.000000000 +0000 +@@ -573,8 +573,37 @@ + .iConfiguration = FSG_STRING_CONFIG, + .bmAttributes = USB_CONFIG_ATT_ONE | USB_CONFIG_ATT_SELFPOWER, + .bMaxPower = CONFIG_USB_GADGET_VBUS_DRAW / 2, ++ //.bMaxPower = 0, //unused suggestion by DWC patch + }; + ++#ifdef CONFIG_USB_DWC_OTG_LPM ++#define USB_DEVICE_CAPABILITY_20_EXTENSION 0x02 ++#define USB_20_EXT_LPM 0x02 ++typedef struct usb_dev_cap_20_ext_desc { ++ __u8 bLength; ++ __u8 bDescriptorType; ++ __u8 bDevCapabilityType; ++ __le32 bmAttributes; ++} __attribute__ ((__packed__)) usb_dev_cap_20_ext_desc_t; ++ ++static struct usb_bos_20_ext_desc { ++ struct usb_bos_descriptor bos_desc; ++ struct usb_dev_cap_20_ext_desc dev_cap_20_ext_desc; ++} __attribute__ ((__packed__)) bos_20_ext_desc = { ++ { ++ .bLength = sizeof(struct usb_bos_descriptor), ++ .bDescriptorType = USB_DT_BOS, ++ .wTotalLength = sizeof(struct usb_bos_20_ext_desc), ++ .bNumDeviceCaps = 1, ++ }, ++ { ++ .bLength = sizeof(struct usb_dev_cap_20_ext_desc), ++ .bDescriptorType = USB_DT_DEVICE_CAPABILITY, ++ .bDevCapabilityType = USB_DEVICE_CAPABILITY_20_EXTENSION, ++ .bmAttributes = USB_20_EXT_LPM, ++ }, ++}; ++#endif + + static struct usb_qualifier_descriptor + dev_qualifier = { +@@ -984,13 +1013,29 @@ + break; + + case USB_DT_BOS: ++#ifdef CONFIG_USB_DWC_OTG_LPM ++ /* When the PCD has LPM enabled set the LPM ++ * Feature bit to 1 when not enabled set the ++ * bit to 0. */ ++ if (usb_gadget_test_lpm_support(fsg->gadget)) { ++ VDBG(fsg, "LPM support enabled in DWC UDC PCD\n"); ++ bos_20_ext_desc.dev_cap_20_ext_desc.bmAttributes |= USB_20_EXT_LPM; ++ } else { ++ VDBG(fsg, "LPM support disabled in DWC UDC PCD\n"); ++ bos_20_ext_desc.dev_cap_20_ext_desc.bmAttributes &= ~USB_20_EXT_LPM; ++ } ++ DBG(fsg, "sending BOS descriptor to host\n"); ++ value = sizeof bos_20_ext_desc; ++ memcpy(req->buf, &bos_20_ext_desc, value); ++ break; ++#else + VDBG(fsg, "get bos descriptor\n"); + + if (gadget_is_superspeed(fsg->gadget)) + value = populate_bos(fsg, req->buf); + break; ++#endif + } +- + break; + + /* One config, two speeds */ +@@ -2640,6 +2685,9 @@ + fsg_set_halt(fsg, fsg->bulk_out); + halt_bulk_in_endpoint(fsg); + } ++ fsg->bulk_in->ops->set_halt(fsg->bulk_in, 3); ++ fsg_set_halt(fsg, fsg->bulk_out); ++ fsg->bulk_out->ops->set_halt(fsg->bulk_out, 3); + return -EINVAL; + } + +@@ -2991,7 +3039,8 @@ + * bulk endpoint, clear the halt now. (The SuperH UDC + * requires this.) */ + if (test_and_clear_bit(IGNORE_BULK_OUT, &fsg->atomic_bitflags)) +- usb_ep_clear_halt(fsg->bulk_in); ++ //usb_ep_clear_halt(fsg->bulk_in); //DWC patch: ++ fsg->bulk_in->ops->set_halt(fsg->bulk_in, 2); + + if (transport_is_bbb()) { + if (fsg->ep0_req_tag == exception_req_tag) +@@ -3065,6 +3114,9 @@ + * that expects a __user pointer and it will work okay. */ + set_fs(get_ds()); + ++ /* Setting this thread high priority */ ++ set_user_nice(current, -20); ++ + /* The main loop */ + while (fsg->state != FSG_STATE_TERMINATED) { + if (exception_in_progress(fsg) || signal_pending(current)) { +@@ -3212,6 +3264,13 @@ + gcnum = usb_gadget_controller_number(fsg->gadget); + if (gcnum >= 0) + mod_data.release = 0x0300 + gcnum; ++ else if (gadget_is_dwc_otg(fsg->gadget)) { ++ mod_data.release = __constant_cpu_to_le16 (0x0200); ++ mod_data.vendor = __constant_cpu_to_le16 (0x053f); ++ if (mod_data.product == DRIVER_PRODUCT_ID) { ++ mod_data.product = __constant_cpu_to_le16 (0x0000); ++ } ++ } + else { + WARNING(fsg, "controller '%s' not recognized\n", + fsg->gadget->name); +@@ -3473,6 +3532,13 @@ + + rc = -ENOMEM; + ++#ifdef CONFIG_USB_DWC_OTG_LPM ++ /* When LPM is enabled, Inform the host that the remote wake ++ * up capability is supported. */ ++ if (usb_gadget_test_lpm_support(fsg->gadget)) ++ config_desc.bmAttributes |= USB_CONFIG_ATT_WAKEUP; ++#endif ++ + /* Allocate the request and buffer for endpoint 0 */ + fsg->ep0req = req = usb_ep_alloc_request(fsg->ep0, GFP_KERNEL); + if (!req) +Index: linux-3.2.46/drivers/usb/host/Kconfig +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/Kconfig 2013-07-26 18:52:05.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/Kconfig 2013-07-26 19:31:19.000000000 +0000 +@@ -556,6 +556,19 @@ + To compile this driver a module, choose M here: the module + will be called "hwa-hc". + ++config USB_DWCOTG ++ tristate "Synopsis DWC host support" ++ depends on USB ++ help ++ The Synopsis DWC controller is a dual-role ++ host/peripheral/OTG ("On The Go") USB controllers. ++ ++ Enable this option to support this IP in host controller mode. ++ If unsure, say N. ++ ++ To compile this driver as a module, choose M here: the ++ modules built will be called dwc_otg and dwc_common_port. ++ + config USB_IMX21_HCD + tristate "i.MX21 HCD support" + depends on USB && ARM && ARCH_MXC +Index: linux-3.2.46/drivers/usb/host/Makefile +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/Makefile 2013-07-26 18:52:05.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/Makefile 2013-07-26 19:31:19.000000000 +0000 +@@ -33,6 +33,8 @@ + obj-$(CONFIG_USB_R8A66597_HCD) += r8a66597-hcd.o + obj-$(CONFIG_USB_ISP1760_HCD) += isp1760.o + obj-$(CONFIG_USB_HWA_HCD) += hwa-hc.o ++ ++obj-$(CONFIG_USB_DWCOTG) += dwc_otg/ dwc_common_port/ + obj-$(CONFIG_USB_IMX21_HCD) += imx21-hcd.o + obj-$(CONFIG_USB_FSL_MPH_DR_OF) += fsl-mph-dr-of.o + obj-$(CONFIG_USB_OCTEON2_COMMON) += octeon2-common.o +Index: linux-3.2.46/drivers/usb/host/dwc_common_port/Makefile +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_common_port/Makefile 2013-07-26 19:31:19.000000000 +0000 +@@ -0,0 +1,44 @@ ++# ++# Makefile for DWC_common library ++# ++ ++ifneq ($(KERNELRELEASE),) ++ ++#CPPFLAGS += -DDEBUG_MEMORY ++ ++CPPFLAGS += -DDEBUG ++CPPFLAGS += -DDWC_LINUX ++ ++obj-$(CONFIG_USB_DWCOTG) += dwc_common_port_lib.o ++dwc_common_port_lib-objs := dwc_cc.o dwc_modpow.o dwc_dh.o \ ++ dwc_crypto.o dwc_notifier.o \ ++ dwc_common_linux.o dwc_mem.o ++ ++kernrelwd := $(subst ., ,$(KERNELRELEASE)) ++kernrel3 := $(word 1,$(kernrelwd)).$(word 2,$(kernrelwd)).$(word 3,$(kernrelwd)) ++ ++ifneq ($(kernrel3),2.6.20) ++# grayg - I only know that we use EXTRA_CFLAGS in 2.6.31 actually ++EXTRA_CFLAGS += $(CPPFLAGS) ++endif ++ ++else ++ ++ifeq ($(DOXYGEN),) ++DOXYGEN := $(DOXYGEN) ++endif ++ ++default: ++ $(MAKE) -C$(KDIR) M=$(PWD) modules ++ ++docs: $(wildcard *.[hc]) doc/doxygen.cfg ++ $(DOXYGEN) doc/doxygen.cfg ++ ++tags: $(wildcard *.[hc]) ++ $(CTAGS) -e $(wildcard *.[hc]) $(wildcard linux/*.[hc]) $(wildcard $(KDIR)/include/linux/usb*.h) ++ ++endif ++ ++clean: ++ rm -rf *.o *.ko .*cmd *.mod.c .tmp_versions Module.symvers ++ +Index: linux-3.2.46/drivers/usb/host/dwc_common_port/Makefile.linux +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_common_port/Makefile.linux 2013-07-26 19:31:19.000000000 +0000 +@@ -0,0 +1,36 @@ ++# ++# Makefile for DWC_common library ++# ++ifneq ($(KERNELRELEASE),) ++ ++#CPPFLAGS += -DDEBUG_MEMORY ++ ++#CPPFLAGS += -DDEBUG ++CPPFLAGS += -DDWC_LINUX ++ ++obj-m := dwc_common_port_lib.o ++dwc_common_port_lib-objs := dwc_cc.o dwc_modpow.o dwc_dh.o \ ++ dwc_crypto.o dwc_notifier.o \ ++ dwc_common_linux.o dwc_mem.o ++ ++else ++ ++ ++ifeq ($(DOXYGEN),) ++DOXYGEN := $(DOXYGEN) ++endif ++ ++default: ++ $(MAKE) -C$(KDIR) M=$(PWD) modules ++ ++docs: $(wildcard *.[hc]) doc/doxygen.cfg ++ $(DOXYGEN) doc/doxygen.cfg ++ ++tags: $(wildcard *.[hc]) ++ $(CTAGS) -e $(wildcard *.[hc]) $(wildcard linux/*.[hc]) $(wildcard $(KDIR)/include/linux/usb*.h) ++ ++endif ++ ++clean: ++ rm -rf *.o *.ko .*cmd *.mod.c .tmp_versions Module.symvers ++ +Index: linux-3.2.46/drivers/usb/host/dwc_common_port/doc/doxygen.cfg +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_common_port/doc/doxygen.cfg 2013-07-26 19:31:19.000000000 +0000 +@@ -0,0 +1,270 @@ ++# Doxyfile 1.4.5 ++ ++#--------------------------------------------------------------------------- ++# Project related configuration options ++#--------------------------------------------------------------------------- ++PROJECT_NAME = "Synopsys DWC Portability and Common Library for UWB" ++PROJECT_NUMBER = ++OUTPUT_DIRECTORY = doc ++CREATE_SUBDIRS = NO ++OUTPUT_LANGUAGE = English ++BRIEF_MEMBER_DESC = YES ++REPEAT_BRIEF = YES ++ABBREVIATE_BRIEF = "The $name class" \ ++ "The $name widget" \ ++ "The $name file" \ ++ is \ ++ provides \ ++ specifies \ ++ contains \ ++ represents \ ++ a \ ++ an \ ++ the ++ALWAYS_DETAILED_SEC = YES ++INLINE_INHERITED_MEMB = NO ++FULL_PATH_NAMES = NO ++STRIP_FROM_PATH = .. ++STRIP_FROM_INC_PATH = ++SHORT_NAMES = NO ++JAVADOC_AUTOBRIEF = YES ++MULTILINE_CPP_IS_BRIEF = NO ++DETAILS_AT_TOP = YES ++INHERIT_DOCS = YES ++SEPARATE_MEMBER_PAGES = NO ++TAB_SIZE = 8 ++ALIASES = ++OPTIMIZE_OUTPUT_FOR_C = YES ++OPTIMIZE_OUTPUT_JAVA = NO ++BUILTIN_STL_SUPPORT = NO ++DISTRIBUTE_GROUP_DOC = NO ++SUBGROUPING = NO ++#--------------------------------------------------------------------------- ++# Build related configuration options ++#--------------------------------------------------------------------------- ++EXTRACT_ALL = NO ++EXTRACT_PRIVATE = NO ++EXTRACT_STATIC = YES ++EXTRACT_LOCAL_CLASSES = NO ++EXTRACT_LOCAL_METHODS = NO ++HIDE_UNDOC_MEMBERS = NO ++HIDE_UNDOC_CLASSES = NO ++HIDE_FRIEND_COMPOUNDS = NO ++HIDE_IN_BODY_DOCS = NO ++INTERNAL_DOCS = NO ++CASE_SENSE_NAMES = YES ++HIDE_SCOPE_NAMES = NO ++SHOW_INCLUDE_FILES = NO ++INLINE_INFO = YES ++SORT_MEMBER_DOCS = NO ++SORT_BRIEF_DOCS = NO ++SORT_BY_SCOPE_NAME = NO ++GENERATE_TODOLIST = YES ++GENERATE_TESTLIST = YES ++GENERATE_BUGLIST = YES ++GENERATE_DEPRECATEDLIST= YES ++ENABLED_SECTIONS = ++MAX_INITIALIZER_LINES = 30 ++SHOW_USED_FILES = YES ++SHOW_DIRECTORIES = YES ++FILE_VERSION_FILTER = ++#--------------------------------------------------------------------------- ++# configuration options related to warning and progress messages ++#--------------------------------------------------------------------------- ++QUIET = YES ++WARNINGS = YES ++WARN_IF_UNDOCUMENTED = NO ++WARN_IF_DOC_ERROR = YES ++WARN_NO_PARAMDOC = YES ++WARN_FORMAT = "$file:$line: $text" ++WARN_LOGFILE = ++#--------------------------------------------------------------------------- ++# configuration options related to the input files ++#--------------------------------------------------------------------------- ++INPUT = . ++FILE_PATTERNS = *.c \ ++ *.cc \ ++ *.cxx \ ++ *.cpp \ ++ *.c++ \ ++ *.d \ ++ *.java \ ++ *.ii \ ++ *.ixx \ ++ *.ipp \ ++ *.i++ \ ++ *.inl \ ++ *.h \ ++ *.hh \ ++ *.hxx \ ++ *.hpp \ ++ *.h++ \ ++ *.idl \ ++ *.odl \ ++ *.cs \ ++ *.php \ ++ *.php3 \ ++ *.inc \ ++ *.m \ ++ *.mm \ ++ *.dox \ ++ *.py \ ++ *.C \ ++ *.CC \ ++ *.C++ \ ++ *.II \ ++ *.I++ \ ++ *.H \ ++ *.HH \ ++ *.H++ \ ++ *.CS \ ++ *.PHP \ ++ *.PHP3 \ ++ *.M \ ++ *.MM \ ++ *.PY ++RECURSIVE = NO ++EXCLUDE = ++EXCLUDE_SYMLINKS = NO ++EXCLUDE_PATTERNS = ++EXAMPLE_PATH = ++EXAMPLE_PATTERNS = * ++EXAMPLE_RECURSIVE = NO ++IMAGE_PATH = ++INPUT_FILTER = ++FILTER_PATTERNS = ++FILTER_SOURCE_FILES = NO ++#--------------------------------------------------------------------------- ++# configuration options related to source browsing ++#--------------------------------------------------------------------------- ++SOURCE_BROWSER = NO ++INLINE_SOURCES = NO ++STRIP_CODE_COMMENTS = YES ++REFERENCED_BY_RELATION = YES ++REFERENCES_RELATION = YES ++USE_HTAGS = NO ++VERBATIM_HEADERS = NO ++#--------------------------------------------------------------------------- ++# configuration options related to the alphabetical class index ++#--------------------------------------------------------------------------- ++ALPHABETICAL_INDEX = NO ++COLS_IN_ALPHA_INDEX = 5 ++IGNORE_PREFIX = ++#--------------------------------------------------------------------------- ++# configuration options related to the HTML output ++#--------------------------------------------------------------------------- ++GENERATE_HTML = YES ++HTML_OUTPUT = html ++HTML_FILE_EXTENSION = .html ++HTML_HEADER = ++HTML_FOOTER = ++HTML_STYLESHEET = ++HTML_ALIGN_MEMBERS = YES ++GENERATE_HTMLHELP = NO ++CHM_FILE = ++HHC_LOCATION = ++GENERATE_CHI = NO ++BINARY_TOC = NO ++TOC_EXPAND = NO ++DISABLE_INDEX = NO ++ENUM_VALUES_PER_LINE = 4 ++GENERATE_TREEVIEW = YES ++TREEVIEW_WIDTH = 250 ++#--------------------------------------------------------------------------- ++# configuration options related to the LaTeX output ++#--------------------------------------------------------------------------- ++GENERATE_LATEX = NO ++LATEX_OUTPUT = latex ++LATEX_CMD_NAME = latex ++MAKEINDEX_CMD_NAME = makeindex ++COMPACT_LATEX = NO ++PAPER_TYPE = a4wide ++EXTRA_PACKAGES = ++LATEX_HEADER = ++PDF_HYPERLINKS = NO ++USE_PDFLATEX = NO ++LATEX_BATCHMODE = NO ++LATEX_HIDE_INDICES = NO ++#--------------------------------------------------------------------------- ++# configuration options related to the RTF output ++#--------------------------------------------------------------------------- ++GENERATE_RTF = NO ++RTF_OUTPUT = rtf ++COMPACT_RTF = NO ++RTF_HYPERLINKS = NO ++RTF_STYLESHEET_FILE = ++RTF_EXTENSIONS_FILE = ++#--------------------------------------------------------------------------- ++# configuration options related to the man page output ++#--------------------------------------------------------------------------- ++GENERATE_MAN = NO ++MAN_OUTPUT = man ++MAN_EXTENSION = .3 ++MAN_LINKS = NO ++#--------------------------------------------------------------------------- ++# configuration options related to the XML output ++#--------------------------------------------------------------------------- ++GENERATE_XML = NO ++XML_OUTPUT = xml ++XML_SCHEMA = ++XML_DTD = ++XML_PROGRAMLISTING = YES ++#--------------------------------------------------------------------------- ++# configuration options for the AutoGen Definitions output ++#--------------------------------------------------------------------------- ++GENERATE_AUTOGEN_DEF = NO ++#--------------------------------------------------------------------------- ++# configuration options related to the Perl module output ++#--------------------------------------------------------------------------- ++GENERATE_PERLMOD = NO ++PERLMOD_LATEX = NO ++PERLMOD_PRETTY = YES ++PERLMOD_MAKEVAR_PREFIX = ++#--------------------------------------------------------------------------- ++# Configuration options related to the preprocessor ++#--------------------------------------------------------------------------- ++ENABLE_PREPROCESSING = YES ++MACRO_EXPANSION = NO ++EXPAND_ONLY_PREDEF = NO ++SEARCH_INCLUDES = YES ++INCLUDE_PATH = ++INCLUDE_FILE_PATTERNS = ++PREDEFINED = DEBUG DEBUG_MEMORY ++EXPAND_AS_DEFINED = ++SKIP_FUNCTION_MACROS = YES ++#--------------------------------------------------------------------------- ++# Configuration::additions related to external references ++#--------------------------------------------------------------------------- ++TAGFILES = ++GENERATE_TAGFILE = ++ALLEXTERNALS = NO ++EXTERNAL_GROUPS = YES ++PERL_PATH = /usr/bin/perl ++#--------------------------------------------------------------------------- ++# Configuration options related to the dot tool ++#--------------------------------------------------------------------------- ++CLASS_DIAGRAMS = YES ++HIDE_UNDOC_RELATIONS = YES ++HAVE_DOT = NO ++CLASS_GRAPH = YES ++COLLABORATION_GRAPH = YES ++GROUP_GRAPHS = YES ++UML_LOOK = NO ++TEMPLATE_RELATIONS = NO ++INCLUDE_GRAPH = NO ++INCLUDED_BY_GRAPH = YES ++CALL_GRAPH = NO ++GRAPHICAL_HIERARCHY = YES ++DIRECTORY_GRAPH = YES ++DOT_IMAGE_FORMAT = png ++DOT_PATH = ++DOTFILE_DIRS = ++MAX_DOT_GRAPH_DEPTH = 1000 ++DOT_TRANSPARENT = NO ++DOT_MULTI_TARGETS = NO ++GENERATE_LEGEND = YES ++DOT_CLEANUP = YES ++#--------------------------------------------------------------------------- ++# Configuration::additions related to the search engine ++#--------------------------------------------------------------------------- ++SEARCHENGINE = NO +Index: linux-3.2.46/drivers/usb/host/dwc_common_port/doc/html/dir_c13d72e45af28cdc461a5f284d3d36fc.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_common_port/doc/html/dir_c13d72e45af28cdc461a5f284d3d36fc.html 2013-07-26 19:31:19.000000000 +0000 +@@ -0,0 +1,81 @@ ++ ++ ++Synopsys DWC Portability and Common Library for UWB: dwc_common_port/ Directory Reference ++ ++ ++ ++ ++
++
++
++dwc_common_port
++

dwc_common_port Directory Reference

++

++ ++ ++ ++ ++ ++ ++ ++ ++ ++

++

++ ++ ++ ++ ++ ++

++

++ ++ ++ ++

++

++ ++ ++ ++ ++ ++

++

++ ++ ++ ++

++

++ ++ ++ ++ ++ ++ ++ ++

++

++ ++ ++ ++ ++ ++

++

++ ++ ++ ++

++

++ ++

Files

file  dwc_cc.c
file  dwc_cc.h
 This file defines the Context Context library.
file  dwc_common_linux.c
file  dwc_crypto.c
 This file contains the WUSB cryptographic routines.
file  dwc_crypto.h
 This file contains declarations for the WUSB Cryptographic routines as defined in the WUSB spec.
file  dwc_dh.c
file  dwc_dh.h
 This file defines the common functions on device and host for performing numeric association as defined in the WUSB spec.
file  dwc_list.h
 This file defines linked list operations.
file  dwc_mem.c
file  dwc_modpow.c
file  dwc_modpow.h
 This file defines the module exponentiation function which is only used internally by the DWC UWB modules for calculation of PKs during numeric association.
file  dwc_notifier.c
file  dwc_notifier.h
 A simple implementation of the Observer pattern.
file  dwc_os.h
 DWC portability library, low level os-wrapper functions.
file  usb.h
++

Generated on Tue May 5 02:22:50 2009 for Synopsys DWC Portability and Common Library for UWB by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_common_port/doc/html/dirs.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_common_port/doc/html/dirs.html 2013-07-26 19:31:19.000000000 +0000 +@@ -0,0 +1,22 @@ ++ ++ ++Synopsys DWC Portability and Common Library for UWB: Directory Hierarchy ++ ++ ++ ++ ++
++
++

Synopsys DWC Portability and Common Library for UWB Directories

This directory hierarchy is sorted roughly, but not completely, alphabetically: ++
Generated on Tue May 5 02:22:50 2009 for Synopsys DWC Portability and Common Library for UWB by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_common_port/doc/html/doxygen.css +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_common_port/doc/html/doxygen.css 2013-07-26 19:31:19.000000000 +0000 +@@ -0,0 +1,358 @@ ++BODY,H1,H2,H3,H4,H5,H6,P,CENTER,TD,TH,UL,DL,DIV { ++ font-family: Geneva, Arial, Helvetica, sans-serif; ++} ++BODY,TD { ++ font-size: 90%; ++} ++H1 { ++ text-align: center; ++ font-size: 160%; ++} ++H2 { ++ font-size: 120%; ++} ++H3 { ++ font-size: 100%; ++} ++CAPTION { font-weight: bold } ++DIV.qindex { ++ width: 100%; ++ background-color: #e8eef2; ++ border: 1px solid #84b0c7; ++ text-align: center; ++ margin: 2px; ++ padding: 2px; ++ line-height: 140%; ++} ++DIV.nav { ++ width: 100%; ++ background-color: #e8eef2; ++ border: 1px solid #84b0c7; ++ text-align: center; ++ margin: 2px; ++ padding: 2px; ++ line-height: 140%; ++} ++DIV.navtab { ++ background-color: #e8eef2; ++ border: 1px solid #84b0c7; ++ text-align: center; ++ margin: 2px; ++ margin-right: 15px; ++ padding: 2px; ++} ++TD.navtab { ++ font-size: 70%; ++} ++A.qindex { ++ text-decoration: none; ++ font-weight: bold; ++ color: #1A419D; ++} ++A.qindex:visited { ++ text-decoration: none; ++ font-weight: bold; ++ color: #1A419D ++} ++A.qindex:hover { ++ text-decoration: none; ++ background-color: #ddddff; ++} ++A.qindexHL { ++ text-decoration: none; ++ font-weight: bold; ++ background-color: #6666cc; ++ color: #ffffff; ++ border: 1px double #9295C2; ++} ++A.qindexHL:hover { ++ text-decoration: none; ++ background-color: #6666cc; ++ color: #ffffff; ++} ++A.qindexHL:visited { text-decoration: none; background-color: #6666cc; color: #ffffff } ++A.el { text-decoration: none; font-weight: bold } ++A.elRef { font-weight: bold } ++A.code:link { text-decoration: none; font-weight: normal; color: #0000FF} ++A.code:visited { text-decoration: none; font-weight: normal; color: #0000FF} ++A.codeRef:link { font-weight: normal; color: #0000FF} ++A.codeRef:visited { font-weight: normal; color: #0000FF} ++A:hover { text-decoration: none; background-color: #f2f2ff } ++DL.el { margin-left: -1cm } ++.fragment { ++ font-family: monospace, fixed; ++ font-size: 95%; ++} ++PRE.fragment { ++ border: 1px solid #CCCCCC; ++ background-color: #f5f5f5; ++ margin-top: 4px; ++ margin-bottom: 4px; ++ margin-left: 2px; ++ margin-right: 8px; ++ padding-left: 6px; ++ padding-right: 6px; ++ padding-top: 4px; ++ padding-bottom: 4px; ++} ++DIV.ah { background-color: black; font-weight: bold; color: #ffffff; margin-bottom: 3px; margin-top: 3px } ++ ++DIV.groupHeader { ++ margin-left: 16px; ++ margin-top: 12px; ++ margin-bottom: 6px; ++ font-weight: bold; ++} ++DIV.groupText { margin-left: 16px; font-style: italic; font-size: 90% } ++BODY { ++ background: white; ++ color: black; ++ margin-right: 20px; ++ margin-left: 20px; ++} ++TD.indexkey { ++ background-color: #e8eef2; ++ font-weight: bold; ++ padding-right : 10px; ++ padding-top : 2px; ++ padding-left : 10px; ++ padding-bottom : 2px; ++ margin-left : 0px; ++ margin-right : 0px; ++ margin-top : 2px; ++ margin-bottom : 2px; ++ border: 1px solid #CCCCCC; ++} ++TD.indexvalue { ++ background-color: #e8eef2; ++ font-style: italic; ++ padding-right : 10px; ++ padding-top : 2px; ++ padding-left : 10px; ++ padding-bottom : 2px; ++ margin-left : 0px; ++ margin-right : 0px; ++ margin-top : 2px; ++ margin-bottom : 2px; ++ border: 1px solid #CCCCCC; ++} ++TR.memlist { ++ background-color: #f0f0f0; ++} ++P.formulaDsp { text-align: center; } ++IMG.formulaDsp { } ++IMG.formulaInl { vertical-align: middle; } ++SPAN.keyword { color: #008000 } ++SPAN.keywordtype { color: #604020 } ++SPAN.keywordflow { color: #e08000 } ++SPAN.comment { color: #800000 } ++SPAN.preprocessor { color: #806020 } ++SPAN.stringliteral { color: #002080 } ++SPAN.charliteral { color: #008080 } ++.mdescLeft { ++ padding: 0px 8px 4px 8px; ++ font-size: 80%; ++ font-style: italic; ++ background-color: #FAFAFA; ++ border-top: 1px none #E0E0E0; ++ border-right: 1px none #E0E0E0; ++ border-bottom: 1px none #E0E0E0; ++ border-left: 1px none #E0E0E0; ++ margin: 0px; ++} ++.mdescRight { ++ padding: 0px 8px 4px 8px; ++ font-size: 80%; ++ font-style: italic; ++ background-color: #FAFAFA; ++ border-top: 1px none #E0E0E0; ++ border-right: 1px none #E0E0E0; ++ border-bottom: 1px none #E0E0E0; ++ border-left: 1px none #E0E0E0; ++ margin: 0px; ++} ++.memItemLeft { ++ padding: 1px 0px 0px 8px; ++ margin: 4px; ++ border-top-width: 1px; ++ border-right-width: 1px; ++ border-bottom-width: 1px; ++ border-left-width: 1px; ++ border-top-color: #E0E0E0; ++ border-right-color: #E0E0E0; ++ border-bottom-color: #E0E0E0; ++ border-left-color: #E0E0E0; ++ border-top-style: solid; ++ border-right-style: none; ++ border-bottom-style: none; ++ border-left-style: none; ++ background-color: #FAFAFA; ++ font-size: 80%; ++} ++.memItemRight { ++ padding: 1px 8px 0px 8px; ++ margin: 4px; ++ border-top-width: 1px; ++ border-right-width: 1px; ++ border-bottom-width: 1px; ++ border-left-width: 1px; ++ border-top-color: #E0E0E0; ++ border-right-color: #E0E0E0; ++ border-bottom-color: #E0E0E0; ++ border-left-color: #E0E0E0; ++ border-top-style: solid; ++ border-right-style: none; ++ border-bottom-style: none; ++ border-left-style: none; ++ background-color: #FAFAFA; ++ font-size: 80%; ++} ++.memTemplItemLeft { ++ padding: 1px 0px 0px 8px; ++ margin: 4px; ++ border-top-width: 1px; ++ border-right-width: 1px; ++ border-bottom-width: 1px; ++ border-left-width: 1px; ++ border-top-color: #E0E0E0; ++ border-right-color: #E0E0E0; ++ border-bottom-color: #E0E0E0; ++ border-left-color: #E0E0E0; ++ border-top-style: none; ++ border-right-style: none; ++ border-bottom-style: none; ++ border-left-style: none; ++ background-color: #FAFAFA; ++ font-size: 80%; ++} ++.memTemplItemRight { ++ padding: 1px 8px 0px 8px; ++ margin: 4px; ++ border-top-width: 1px; ++ border-right-width: 1px; ++ border-bottom-width: 1px; ++ border-left-width: 1px; ++ border-top-color: #E0E0E0; ++ border-right-color: #E0E0E0; ++ border-bottom-color: #E0E0E0; ++ border-left-color: #E0E0E0; ++ border-top-style: none; ++ border-right-style: none; ++ border-bottom-style: none; ++ border-left-style: none; ++ background-color: #FAFAFA; ++ font-size: 80%; ++} ++.memTemplParams { ++ padding: 1px 0px 0px 8px; ++ margin: 4px; ++ border-top-width: 1px; ++ border-right-width: 1px; ++ border-bottom-width: 1px; ++ border-left-width: 1px; ++ border-top-color: #E0E0E0; ++ border-right-color: #E0E0E0; ++ border-bottom-color: #E0E0E0; ++ border-left-color: #E0E0E0; ++ border-top-style: solid; ++ border-right-style: none; ++ border-bottom-style: none; ++ border-left-style: none; ++ color: #606060; ++ background-color: #FAFAFA; ++ font-size: 80%; ++} ++.search { color: #003399; ++ font-weight: bold; ++} ++FORM.search { ++ margin-bottom: 0px; ++ margin-top: 0px; ++} ++INPUT.search { font-size: 75%; ++ color: #000080; ++ font-weight: normal; ++ background-color: #e8eef2; ++} ++TD.tiny { font-size: 75%; ++} ++a { ++ color: #1A41A8; ++} ++a:visited { ++ color: #2A3798; ++} ++.dirtab { padding: 4px; ++ border-collapse: collapse; ++ border: 1px solid #84b0c7; ++} ++TH.dirtab { background: #e8eef2; ++ font-weight: bold; ++} ++HR { height: 1px; ++ border: none; ++ border-top: 1px solid black; ++} ++ ++/* Style for detailed member documentation */ ++.memtemplate { ++ font-size: 80%; ++ color: #606060; ++ font-weight: normal; ++} ++.memnav { ++ background-color: #e8eef2; ++ border: 1px solid #84b0c7; ++ text-align: center; ++ margin: 2px; ++ margin-right: 15px; ++ padding: 2px; ++} ++.memitem { ++ padding: 4px; ++ background-color: #eef3f5; ++ border-width: 1px; ++ border-style: solid; ++ border-color: #dedeee; ++ -moz-border-radius: 8px 8px 8px 8px; ++} ++.memname { ++ white-space: nowrap; ++ font-weight: bold; ++} ++.memdoc{ ++ padding-left: 10px; ++} ++.memproto { ++ background-color: #d5e1e8; ++ width: 100%; ++ border-width: 1px; ++ border-style: solid; ++ border-color: #84b0c7; ++ font-weight: bold; ++ -moz-border-radius: 8px 8px 8px 8px; ++} ++.paramkey { ++ text-align: right; ++} ++.paramtype { ++ white-space: nowrap; ++} ++.paramname { ++ color: #602020; ++ font-style: italic; ++} ++/* End Styling for detailed member documentation */ ++ ++/* for the tree view */ ++.ftvtree { ++ font-family: sans-serif; ++ margin:0.5em; ++} ++.directory { font-size: 9pt; font-weight: bold; } ++.directory h3 { margin: 0px; margin-top: 1em; font-size: 11pt; } ++.directory > h3 { margin-top: 0; } ++.directory p { margin: 0px; white-space: nowrap; } ++.directory div { display: none; margin: 0px; } ++.directory img { vertical-align: -30%; } ++ +Index: linux-3.2.46/drivers/usb/host/dwc_common_port/doc/html/dwc__cc_8h.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_common_port/doc/html/dwc__cc_8h.html 2013-07-26 19:31:19.000000000 +0000 +@@ -0,0 +1,709 @@ ++ ++ ++Synopsys DWC Portability and Common Library for UWB: dwc_cc.h File Reference ++ ++ ++ ++ ++
++
++
++
++
++dwc_common_port
++

dwc_cc.h File Reference

Detailed Description

++This file defines the Context Context library. ++

++The main data structure is dwc_cc_if_t which is returned by either the dwc_cc_if_alloc function or returned by the module to the user via a provided function. The data structure is opaque and should only be manipulated via the functions provied in this API.

++It manages a list of connection contexts and operations can be performed to add, remove, query, search, and change, those contexts. Additionally, a dwc_notifier_t object can be requested from the manager so that the user can be notified whenever the context list has changed. ++

++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++

Connection Context Operations

dwc_cc_if_t * dwc_cc_if_alloc (dwc_notifier_t *notifier, unsigned is_host)
 This function allocates memory for a dwc_cc_if_t structure, initializes fields to default values, and returns a pointer to the structure or NULL on error.
void dwc_cc_if_free (dwc_cc_if_t *cc_if)
 Frees the memory for the specified CC structure allocated from dwc_cc_if_alloc().
void dwc_cc_clear (dwc_cc_if_t *cc_if)
 Removes all contexts from the connection context list.
int32_t dwc_cc_add (dwc_cc_if_t *cc_if, uint8_t *chid, uint8_t *cdid, uint8_t *ck, uint8_t *name, uint8_t length)
 Adds a connection context (CHID, CK, CDID, Name) to the connection context list.
void dwc_cc_change (dwc_cc_if_t *cc_if, int32_t id, uint8_t *chid, uint8_t *cdid, uint8_t *ck, uint8_t *name, uint8_t length)
 Changes the CHID, CK, CDID, or Name values of a connection context in the list, preserving any accumulated statistics.
void dwc_cc_remove (dwc_cc_if_t *cc_if, int32_t id)
 Remove the specified connection context.
uint8_t * dwc_cc_data_for_save (dwc_cc_if_t *cc_if, unsigned int *length)
 Get a binary block of data for the connection context list and attributes.
void dwc_cc_restore_from_data (dwc_cc_if_t *cc_if, uint8_t *data, unsigned int length)
 Restore the connection context list from the binary data that was previously returned from a call to dwc_cc_data_for_save.
uint32_t dwc_cc_match_chid (dwc_cc_if_t *cc_if, uint8_t *chid)
 Find the connection context from the specified CHID.
uint32_t dwc_cc_match_cdid (dwc_cc_if_t *cc_if, uint8_t *cdid)
 Find the connection context from the specified CDID.
uint8_t * dwc_cc_ck (dwc_cc_if_t *cc_if, int32_t id)
 Retrieve the CK from the specified connection context.
uint8_t * dwc_cc_chid (dwc_cc_if_t *cc_if, int32_t id)
 Retrieve the CHID from the specified connection context.
uint8_t * dwc_cc_cdid (dwc_cc_if_t *cc_if, int32_t id)
 Retrieve the CDID from the specified connection context.
++uint8_t * dwc_cc_name (dwc_cc_if_t *cc_if, int32_t id, uint8_t *length)
static unsigned dwc_assoc_is_not_zero_id (uint8_t *id)
 Checks a buffer for non-zero.
static unsigned dwc_assoc_is_zero_id (uint8_t *id)
 Checks a buffer for zero.
static int dwc_print_id_string (char *buffer, uint8_t *id)
 Prints an ASCII representation for the 16-byte chid, cdid, or ck, into buffer.

Defines

++#define DWC_CC_LIST_CHANGED_NOTIFICATION   "DWC_CC_LIST_CHANGED_NOTIFICATION"

Typedefs

++typedef dwc_cc_if dwc_cc_if_t
++

Function Documentation

++ ++
++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
dwc_cc_if_t* dwc_cc_if_alloc (dwc_notifier_t *  notifier,
unsigned  is_host 
)
++
++
++ ++

++This function allocates memory for a dwc_cc_if_t structure, initializes fields to default values, and returns a pointer to the structure or NULL on error. ++

++ ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_cc_if_free (dwc_cc_if_t *  cc_if  ) 
++
++
++ ++

++Frees the memory for the specified CC structure allocated from dwc_cc_if_alloc(). ++

++ ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_cc_clear (dwc_cc_if_t *  cc_if  ) 
++
++
++ ++

++Removes all contexts from the connection context list. ++

++ ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int32_t dwc_cc_add (dwc_cc_if_t *  cc_if,
uint8_t *  chid,
uint8_t *  cdid,
uint8_t *  ck,
uint8_t *  name,
uint8_t  length 
)
++
++
++ ++

++Adds a connection context (CHID, CK, CDID, Name) to the connection context list. ++

++If a CHID already exists, the CK and name are overwritten. Statistics are not overwritten.

++

Parameters:
++ ++ ++ ++ ++ ++ ++ ++
cc_if The cc_if structure.
chid A pointer to the 16-byte CHID. This value will be copied.
ck A pointer to the 16-byte CK. This value will be copied.
cdid A pointer to the 16-byte CDID. This value will be copied.
name An optional host friendly name as defined in the association model spec. Must be a UTF16-LE unicode string. Can be NULL to indicated no name.
length The length othe unicode string.
++
++
Returns:
A unique identifier used to refer to this context that is valid for as long as this context is still in the list.
++ ++
++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_cc_change (dwc_cc_if_t *  cc_if,
int32_t  id,
uint8_t *  chid,
uint8_t *  cdid,
uint8_t *  ck,
uint8_t *  name,
uint8_t  length 
)
++
++
++ ++

++Changes the CHID, CK, CDID, or Name values of a connection context in the list, preserving any accumulated statistics. ++

++This would typically be called if the host decideds to change the context with a SET_CONNECTION request.

++

Parameters:
++ ++ ++ ++ ++ ++ ++ ++ ++
cc_if The cc_if structure.
id The identifier of the connection context.
chid A pointer to the 16-byte CHID. This value will be copied. NULL indicates no change.
cdid A pointer to the 16-byte CDID. This value will be copied. NULL indicates no change.
ck A pointer to the 16-byte CK. This value will be copied. NULL indicates no change.
name Host friendly name UTF16-LE. NULL indicates no change.
length Length of name.
++
++ ++
++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_cc_remove (dwc_cc_if_t *  cc_if,
int32_t  id 
)
++
++
++ ++

++Remove the specified connection context. ++

++

Parameters:
++ ++ ++ ++
cc_if The cc_if structure.
id The identifier of the connection context to remove.
++
++ ++
++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
uint8_t* dwc_cc_data_for_save (dwc_cc_if_t *  cc_if,
unsigned int *  length 
)
++
++
++ ++

++Get a binary block of data for the connection context list and attributes. ++

++This data can be used by the OS specific driver to save the connection context list into non-volatile memory.

++

Parameters:
++ ++ ++ ++
cc_if The cc_if structure.
length Return the length of the data buffer.
++
++
Returns:
A pointer to the data buffer. The memory for this buffer should be freed with DWC_FREE() after use.
++ ++
++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_cc_restore_from_data (dwc_cc_if_t *  cc_if,
uint8_t *  data,
unsigned int  length 
)
++
++
++ ++

++Restore the connection context list from the binary data that was previously returned from a call to dwc_cc_data_for_save. ++

++This can be used by the OS specific driver to load a connection context list from non-volatile memory.

++

Parameters:
++ ++ ++ ++ ++
cc_if The cc_if structure.
data The data bytes as returned from dwc_cc_data_for_save.
length The length of the data.
++
++ ++
++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
uint32_t dwc_cc_match_chid (dwc_cc_if_t *  cc_if,
uint8_t *  chid 
)
++
++
++ ++

++Find the connection context from the specified CHID. ++

++

Parameters:
++ ++ ++ ++
cc_if The cc_if structure.
chid A pointer to the CHID data.
++
++
Returns:
A non-zero identifier of the connection context if the CHID matches. Otherwise returns 0.
++ ++
++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
uint32_t dwc_cc_match_cdid (dwc_cc_if_t *  cc_if,
uint8_t *  cdid 
)
++
++
++ ++

++Find the connection context from the specified CDID. ++

++

Parameters:
++ ++ ++ ++
cc_if The cc_if structure.
cdid A pointer to the CDID data.
++
++
Returns:
A non-zero identifier of the connection context if the CHID matches. Otherwise returns 0.
++ ++
++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
uint8_t* dwc_cc_ck (dwc_cc_if_t *  cc_if,
int32_t  id 
)
++
++
++ ++

++Retrieve the CK from the specified connection context. ++

++

Parameters:
++ ++ ++ ++
cc_if The cc_if structure.
id The identifier of the connection context.
++
++
Returns:
A pointer to the CK data. The memory does not need to be freed.
++ ++
++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
uint8_t* dwc_cc_chid (dwc_cc_if_t *  cc_if,
int32_t  id 
)
++
++
++ ++

++Retrieve the CHID from the specified connection context. ++

++

Parameters:
++ ++ ++ ++
cc_if The cc_if structure.
id The identifier of the connection context.
++
++
Returns:
A pointer to the CHID data. The memory does not need to be freed.
++ ++
++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
uint8_t* dwc_cc_cdid (dwc_cc_if_t *  cc_if,
int32_t  id 
)
++
++
++ ++

++Retrieve the CDID from the specified connection context. ++

++

Parameters:
++ ++ ++ ++
cc_if The cc_if structure.
id The identifier of the connection context.
++
++
Returns:
A pointer to the CDID data. The memory does not need to be freed.
++ ++
++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
static unsigned dwc_assoc_is_not_zero_id (uint8_t *  id  )  [inline, static]
++
++
++ ++

++Checks a buffer for non-zero. ++

++

Parameters:
++ ++ ++
id A pointer to a 16 byte buffer.
++
++
Returns:
true if the 16 byte value is non-zero.
++ ++
++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
static unsigned dwc_assoc_is_zero_id (uint8_t *  id  )  [inline, static]
++
++
++ ++

++Checks a buffer for zero. ++

++

Parameters:
++ ++ ++
id A pointer to a 16 byte buffer.
++
++
Returns:
true if the 16 byte value is zero.
++ ++
++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
static int dwc_print_id_string (char *  buffer,
uint8_t *  id 
) [inline, static]
++
++
++ ++

++Prints an ASCII representation for the 16-byte chid, cdid, or ck, into buffer. ++

++ ++

++

++

Generated on Tue May 5 02:22:50 2009 for Synopsys DWC Portability and Common Library for UWB by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_common_port/doc/html/dwc__crypto_8c.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_common_port/doc/html/dwc__crypto_8c.html 2013-07-26 19:31:19.000000000 +0000 +@@ -0,0 +1,435 @@ ++ ++ ++Synopsys DWC Portability and Common Library for UWB: dwc_crypto.c File Reference ++ ++ ++ ++ ++
++
++
++
++
++dwc_common_port
++

dwc_crypto.c File Reference

Detailed Description

++This file contains the WUSB cryptographic routines. ++

++ ++

++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++

Functions

++static void dump_bytes (char *name, uint8_t *bytes, int len)
++void show_block (const u8 *blk, const char *prefix, const char *suffix, int a)
int dwc_wusb_aes_encrypt (u8 *src, u8 *key, u8 *dst)
 Encrypts an array of bytes using the AES encryption engine.
void dwc_wusb_cmf (u8 *key, u8 *nonce, char *label, u8 *bytes, int len, u8 *result)
 The CCM-MAC-FUNCTION described in section 6.5 of the WUSB spec.
void dwc_wusb_prf (int prf_len, u8 *key, u8 *nonce, char *label, u8 *bytes, int len, u8 *result)
 The PRF function described in section 6.5 of the WUSB spec.
void dwc_wusb_fill_ccm_nonce (uint16_t haddr, uint16_t daddr, uint8_t *tkid, uint8_t *nonce)
 Fills in CCM Nonce per the WUSB spec.
void dwc_wusb_gen_nonce (uint16_t addr, uint8_t *nonce)
 Generates a 16-byte cryptographic-grade random number for the Host/Device Nonce.
void dwc_wusb_gen_key (uint8_t *ccm_nonce, uint8_t *mk, uint8_t *hnonce, uint8_t *dnonce, uint8_t *kck, uint8_t *ptk)
 Generates the Session Key (PTK) and Key Confirmation Key (KCK) per the WUSB spec.
void dwc_wusb_gen_mic (uint8_t *ccm_nonce, uint8_t *kck, uint8_t *data, uint8_t *mic)
 Generates the Message Integrity Code over the Handshake data per the WUSB spec.
++

Function Documentation

++ ++
++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int dwc_wusb_aes_encrypt (u8 *  src,
u8 *  key,
u8 *  dst 
)
++
++
++ ++

++Encrypts an array of bytes using the AES encryption engine. ++

++If dst == src, then the bytes will be encrypted in-place.

++

Returns:
0 on success, negative error code on error.
++ ++
++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_wusb_cmf (u8 *  key,
u8 *  nonce,
char *  label,
u8 *  bytes,
int  len,
u8 *  result 
)
++
++
++ ++

++The CCM-MAC-FUNCTION described in section 6.5 of the WUSB spec. ++

++This function takes a data string and returns the encrypted CBC Counter-mode MIC.

++

Parameters:
++ ++ ++ ++ ++ ++ ++ ++
key The 128-bit symmetric key.
nonce The CCM nonce.
label The unique 14-byte ASCII text label.
bytes The byte array to be encrypted.
len Length of the byte array.
result Byte array to receive the 8-byte encrypted MIC.
++
++ ++
++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_wusb_prf (int  prf_len,
u8 *  key,
u8 *  nonce,
char *  label,
u8 *  bytes,
int  len,
u8 *  result 
)
++
++
++ ++

++The PRF function described in section 6.5 of the WUSB spec. ++

++This function concatenates MIC values returned from dwc_cmf() to create a value of the requested length.

++

Parameters:
++ ++ ++ ++ ++
prf_len Length of the PRF function in bits (64, 128, or 256).
key,nonce,label,bytes,len Same as for dwc_cmf().
result Byte array to receive the result.
++
++ ++
++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_wusb_fill_ccm_nonce (uint16_t  haddr,
uint16_t  daddr,
uint8_t *  tkid,
uint8_t *  nonce 
)
++
++
++ ++

++Fills in CCM Nonce per the WUSB spec. ++

++

Parameters:
++ ++ ++ ++ ++ ++
[in] haddr Host address.
[in] daddr Device address.
[in] tkid Session Key(PTK) identifier.
[out] nonce Pointer to where the CCM Nonce output is to be written.
++
++ ++
++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_wusb_gen_nonce (uint16_t  addr,
uint8_t *  nonce 
)
++
++
++ ++

++Generates a 16-byte cryptographic-grade random number for the Host/Device Nonce. ++

++ ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_wusb_gen_key (uint8_t *  ccm_nonce,
uint8_t *  mk,
uint8_t *  hnonce,
uint8_t *  dnonce,
uint8_t *  kck,
uint8_t *  ptk 
)
++
++
++ ++

++Generates the Session Key (PTK) and Key Confirmation Key (KCK) per the WUSB spec. ++

++

Parameters:
++ ++ ++ ++ ++ ++ ++ ++
[in] ccm_nonce Pointer to CCM Nonce.
[in] mk Master Key to derive the session from
[in] hnonce Pointer to Host Nonce.
[in] dnonce Pointer to Device Nonce.
[out] kck Pointer to where the KCK output is to be written.
[out] ptk Pointer to where the PTK output is to be written.
++
++ ++
++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_wusb_gen_mic (uint8_t *  ccm_nonce,
uint8_t *  kck,
uint8_t *  data,
uint8_t *  mic 
)
++
++
++ ++

++Generates the Message Integrity Code over the Handshake data per the WUSB spec. ++

++

Parameters:
++ ++ ++ ++ ++ ++
ccm_nonce Pointer to CCM Nonce.
kck Pointer to Key Confirmation Key.
data Pointer to Handshake data to be checked.
mic Pointer to where the MIC output is to be written.
++
++ ++
++

++

Generated on Tue May 5 02:22:50 2009 for Synopsys DWC Portability and Common Library for UWB by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_common_port/doc/html/dwc__crypto_8h.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_common_port/doc/html/dwc__crypto_8h.html 2013-07-26 19:31:19.000000000 +0000 +@@ -0,0 +1,618 @@ ++ ++ ++Synopsys DWC Portability and Common Library for UWB: dwc_crypto.h File Reference ++ ++ ++ ++ ++
++
++
++
++
++dwc_common_port
++

dwc_crypto.h File Reference

Detailed Description

++This file contains declarations for the WUSB Cryptographic routines as defined in the WUSB spec. ++

++They are only to be used internally by the DWC UWB modules. ++

++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++

Functions

int dwc_wusb_aes_encrypt (u8 *src, u8 *key, u8 *dst)
 Encrypts an array of bytes using the AES encryption engine.
void dwc_wusb_cmf (u8 *key, u8 *nonce, char *label, u8 *bytes, int len, u8 *result)
 The CCM-MAC-FUNCTION described in section 6.5 of the WUSB spec.
void dwc_wusb_prf (int prf_len, u8 *key, u8 *nonce, char *label, u8 *bytes, int len, u8 *result)
 The PRF function described in section 6.5 of the WUSB spec.
static void dwc_wusb_prf_64 (u8 *key, u8 *nonce, char *label, u8 *bytes, int len, u8 *result)
 The PRF-64 function described in section 6.5 of the WUSB spec.
static void dwc_wusb_prf_128 (u8 *key, u8 *nonce, char *label, u8 *bytes, int len, u8 *result)
 The PRF-128 function described in section 6.5 of the WUSB spec.
static void dwc_wusb_prf_256 (u8 *key, u8 *nonce, char *label, u8 *bytes, int len, u8 *result)
 The PRF-256 function described in section 6.5 of the WUSB spec.
void dwc_wusb_fill_ccm_nonce (uint16_t haddr, uint16_t daddr, uint8_t *tkid, uint8_t *nonce)
 Fills in CCM Nonce per the WUSB spec.
void dwc_wusb_gen_nonce (uint16_t addr, uint8_t *nonce)
 Generates a 16-byte cryptographic-grade random number for the Host/Device Nonce.
void dwc_wusb_gen_key (uint8_t *ccm_nonce, uint8_t *mk, uint8_t *hnonce, uint8_t *dnonce, uint8_t *kck, uint8_t *ptk)
 Generates the Session Key (PTK) and Key Confirmation Key (KCK) per the WUSB spec.
void dwc_wusb_gen_mic (uint8_t *ccm_nonce, uint8_t *kck, uint8_t *data, uint8_t *mic)
 Generates the Message Integrity Code over the Handshake data per the WUSB spec.
++

Function Documentation

++ ++
++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int dwc_wusb_aes_encrypt (u8 *  src,
u8 *  key,
u8 *  dst 
)
++
++
++ ++

++Encrypts an array of bytes using the AES encryption engine. ++

++If dst == src, then the bytes will be encrypted in-place.

++

Returns:
0 on success, negative error code on error.
++ ++
++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_wusb_cmf (u8 *  key,
u8 *  nonce,
char *  label,
u8 *  bytes,
int  len,
u8 *  result 
)
++
++
++ ++

++The CCM-MAC-FUNCTION described in section 6.5 of the WUSB spec. ++

++This function takes a data string and returns the encrypted CBC Counter-mode MIC.

++

Parameters:
++ ++ ++ ++ ++ ++ ++ ++
key The 128-bit symmetric key.
nonce The CCM nonce.
label The unique 14-byte ASCII text label.
bytes The byte array to be encrypted.
len Length of the byte array.
result Byte array to receive the 8-byte encrypted MIC.
++
++ ++
++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_wusb_prf (int  prf_len,
u8 *  key,
u8 *  nonce,
char *  label,
u8 *  bytes,
int  len,
u8 *  result 
)
++
++
++ ++

++The PRF function described in section 6.5 of the WUSB spec. ++

++This function concatenates MIC values returned from dwc_cmf() to create a value of the requested length.

++

Parameters:
++ ++ ++ ++ ++
prf_len Length of the PRF function in bits (64, 128, or 256).
key,nonce,label,bytes,len Same as for dwc_cmf().
result Byte array to receive the result.
++
++ ++
++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
static void dwc_wusb_prf_64 (u8 *  key,
u8 *  nonce,
char *  label,
u8 *  bytes,
int  len,
u8 *  result 
) [inline, static]
++
++
++ ++

++The PRF-64 function described in section 6.5 of the WUSB spec. ++

++

Parameters:
++ ++ ++
key,nonce,label,bytes,len,result Same as for dwc_prf().
++
++ ++
++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
static void dwc_wusb_prf_128 (u8 *  key,
u8 *  nonce,
char *  label,
u8 *  bytes,
int  len,
u8 *  result 
) [inline, static]
++
++
++ ++

++The PRF-128 function described in section 6.5 of the WUSB spec. ++

++

Parameters:
++ ++ ++
key,nonce,label,bytes,len,result Same as for dwc_prf().
++
++ ++
++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
static void dwc_wusb_prf_256 (u8 *  key,
u8 *  nonce,
char *  label,
u8 *  bytes,
int  len,
u8 *  result 
) [inline, static]
++
++
++ ++

++The PRF-256 function described in section 6.5 of the WUSB spec. ++

++

Parameters:
++ ++ ++
key,nonce,label,bytes,len,result Same as for dwc_prf().
++
++ ++
++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_wusb_fill_ccm_nonce (uint16_t  haddr,
uint16_t  daddr,
uint8_t *  tkid,
uint8_t *  nonce 
)
++
++
++ ++

++Fills in CCM Nonce per the WUSB spec. ++

++

Parameters:
++ ++ ++ ++ ++ ++
[in] haddr Host address.
[in] daddr Device address.
[in] tkid Session Key(PTK) identifier.
[out] nonce Pointer to where the CCM Nonce output is to be written.
++
++ ++
++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_wusb_gen_nonce (uint16_t  addr,
uint8_t *  nonce 
)
++
++
++ ++

++Generates a 16-byte cryptographic-grade random number for the Host/Device Nonce. ++

++ ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_wusb_gen_key (uint8_t *  ccm_nonce,
uint8_t *  mk,
uint8_t *  hnonce,
uint8_t *  dnonce,
uint8_t *  kck,
uint8_t *  ptk 
)
++
++
++ ++

++Generates the Session Key (PTK) and Key Confirmation Key (KCK) per the WUSB spec. ++

++

Parameters:
++ ++ ++ ++ ++ ++ ++ ++
[in] ccm_nonce Pointer to CCM Nonce.
[in] mk Master Key to derive the session from
[in] hnonce Pointer to Host Nonce.
[in] dnonce Pointer to Device Nonce.
[out] kck Pointer to where the KCK output is to be written.
[out] ptk Pointer to where the PTK output is to be written.
++
++ ++
++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_wusb_gen_mic (uint8_t *  ccm_nonce,
uint8_t *  kck,
uint8_t *  data,
uint8_t *  mic 
)
++
++
++ ++

++Generates the Message Integrity Code over the Handshake data per the WUSB spec. ++

++

Parameters:
++ ++ ++ ++ ++ ++
ccm_nonce Pointer to CCM Nonce.
kck Pointer to Key Confirmation Key.
data Pointer to Handshake data to be checked.
mic Pointer to where the MIC output is to be written.
++
++ ++
++

++

Generated on Tue May 5 02:22:50 2009 for Synopsys DWC Portability and Common Library for UWB by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_common_port/doc/html/dwc__dh_8h.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_common_port/doc/html/dwc__dh_8h.html 2013-07-26 19:31:19.000000000 +0000 +@@ -0,0 +1,166 @@ ++ ++ ++Synopsys DWC Portability and Common Library for UWB: dwc_dh.h File Reference ++ ++ ++ ++ ++
++
++
++
++
++dwc_common_port
++

dwc_dh.h File Reference

Detailed Description

++This file defines the common functions on device and host for performing numeric association as defined in the WUSB spec. ++

++They are only to be used internally by the DWC UWB modules. ++

++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++

Functions

++int dwc_dh_sha256 (uint8_t *message, uint32_t len, uint8_t *out)
++int dwc_dh_hmac_sha256 (uint8_t *message, uint32_t messagelen, uint8_t *key, uint32_t keylen, uint8_t *out)
++int dwc_dh_modpow (void *num, uint32_t num_len, void *exp, uint32_t exp_len, void *mod, uint32_t mod_len, void *out)
int dwc_dh_pk (uint8_t nd, uint8_t *exp, uint8_t *pkd, uint8_t *hash)
 Computes PKD or PKH, and SHA-256(PKd || Nd).
int dwc_dh_derive_keys (uint8_t nd, uint8_t *pkh, uint8_t *pkd, uint8_t *exp, int is_host, char *dd, uint8_t *ck, uint8_t *kdk)
 Computes the DHKEY, and VD.
++

Function Documentation

++ ++
++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int dwc_dh_pk (uint8_t  nd,
uint8_t *  exp,
uint8_t *  pkd,
uint8_t *  hash 
)
++
++
++ ++

++Computes PKD or PKH, and SHA-256(PKd || Nd). ++

++PK = g^exp mod p.

++Input: Nd = Number of digits on the device.

++Output: exp = A 32-byte buffer to be filled with a randomly generated number. used as either A or B. pk = A 384-byte buffer to be filled with the PKH or PKD. hash = A 32-byte buffer to be filled with SHA-256(PK || ND). ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int dwc_dh_derive_keys (uint8_t  nd,
uint8_t *  pkh,
uint8_t *  pkd,
uint8_t *  exp,
int  is_host,
char *  dd,
uint8_t *  ck,
uint8_t *  kdk 
)
++
++
++ ++

++Computes the DHKEY, and VD. ++

++If called from host, then it will comput DHKEY=PKD^exp % p. If called from device, then it will comput DHKEY=PKH^exp % p.

++Input: pkd = The PKD value. pkh = The PKH value. exp = The A value (if device) or B value (if host) generated in dwc_wudev_dh_pk. is_host = Set to non zero if a WUSB host is calling this function.

++Output:

++dd = A pointer to an buffer to be set to the displayed digits string to be shown to the user. This buffer should be at 5 bytes long to hold 4 digits plus a null termination character. This buffer can be used directly for display. ck = A 16-byte buffer to be filled with the CK. kdk = A 32-byte buffer to be filled with the KDK. ++

++

++

Generated on Tue May 5 02:22:50 2009 for Synopsys DWC Portability and Common Library for UWB by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_common_port/doc/html/dwc__list_8h.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_common_port/doc/html/dwc__list_8h.html 2013-07-26 19:31:19.000000000 +0000 +@@ -0,0 +1,1844 @@ ++ ++ ++Synopsys DWC Portability and Common Library for UWB: dwc_list.h File Reference ++ ++ ++ ++ ++
++
++
++
++
++dwc_common_port
++

dwc_list.h File Reference

Detailed Description

++This file defines linked list operations. ++

++It is derived from BSD with only the MACRO names being prefixed with DWC_. This is because a few of these names conflict with those on Linux. For documentation on use, see the inline comments in the source code. The original license for this source code applies and is preserved in the dwc_list.h source file. ++

++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++

Data Structures

struct  dwc_list_link

Defines

#define DWC_LIST_INIT(link)
++#define DWC_LIST_FIRST(link)   ((link)->next)
++#define DWC_LIST_LAST(link)   ((link)->prev)
++#define DWC_LIST_END(link)   (link)
++#define DWC_LIST_NEXT(link)   ((link)->next)
++#define DWC_LIST_PREV(link)   ((link)->prev)
++#define DWC_LIST_EMPTY(link)   (DWC_LIST_FIRST(link) == DWC_LIST_END(link))
#define DWC_LIST_ENTRY(link, type, field)
#define DWC_LIST_INSERT_HEAD(list, link)
#define DWC_LIST_INSERT_TAIL(list, link)
#define DWC_LIST_REMOVE(link)
#define DWC_LIST_REMOVE_INIT(link)
#define DWC_LIST_MOVE_HEAD(list, link)
#define DWC_LIST_MOVE_TAIL(list, link)
#define DWC_LIST_FOREACH(var, list)
#define DWC_LIST_FOREACH_SAFE(var, var2, list)
#define DWC_LIST_FOREACH_REVERSE(var, list)
#define DWC_SLIST_HEAD(name, type)
++#define DWC_SLIST_HEAD_INITIALIZER(head)   { NULL }
#define DWC_SLIST_ENTRY(type)
++#define DWC_SLIST_FIRST(head)   ((head)->slh_first)
++#define DWC_SLIST_END(head)   NULL
++#define DWC_SLIST_EMPTY(head)   (SLIST_FIRST(head) == SLIST_END(head))
++#define DWC_SLIST_NEXT(elm, field)   ((elm)->field.sle_next)
#define DWC_SLIST_FOREACH(var, head, field)
#define DWC_SLIST_FOREACH_PREVPTR(var, varp, head, field)
#define DWC_SLIST_INIT(head)
#define DWC_SLIST_INSERT_AFTER(slistelm, elm, field)
#define DWC_SLIST_INSERT_HEAD(head, elm, field)
#define DWC_SLIST_REMOVE_NEXT(head, elm, field)
#define DWC_SLIST_REMOVE_HEAD(head, field)
#define DWC_SLIST_REMOVE(head, elm, type, field)
#define DWC_SIMPLEQ_HEAD(name, type)
++#define DWC_SIMPLEQ_HEAD_INITIALIZER(head)   { NULL, &(head).sqh_first }
#define DWC_SIMPLEQ_ENTRY(type)
++#define DWC_SIMPLEQ_FIRST(head)   ((head)->sqh_first)
++#define DWC_SIMPLEQ_END(head)   NULL
++#define DWC_SIMPLEQ_EMPTY(head)   (SIMPLEQ_FIRST(head) == SIMPLEQ_END(head))
++#define DWC_SIMPLEQ_NEXT(elm, field)   ((elm)->field.sqe_next)
#define DWC_SIMPLEQ_FOREACH(var, head, field)
#define DWC_SIMPLEQ_INIT(head)
#define DWC_SIMPLEQ_INSERT_HEAD(head, elm, field)
#define DWC_SIMPLEQ_INSERT_TAIL(head, elm, field)
#define DWC_SIMPLEQ_INSERT_AFTER(head, listelm, elm, field)
#define DWC_SIMPLEQ_REMOVE_HEAD(head, field)
#define DWC_TAILQ_HEAD(name, type)
++#define DWC_TAILQ_HEAD_INITIALIZER(head)   { NULL, &(head).tqh_first }
#define DWC_TAILQ_ENTRY(type)
++#define DWC_TAILQ_FIRST(head)   ((head)->tqh_first)
++#define DWC_TAILQ_END(head)   NULL
++#define DWC_TAILQ_NEXT(elm, field)   ((elm)->field.tqe_next)
++#define DWC_TAILQ_LAST(head, headname)   (*(((struct headname *)((head)->tqh_last))->tqh_last))
++#define DWC_TAILQ_PREV(elm, headname, field)   (*(((struct headname *)((elm)->field.tqe_prev))->tqh_last))
++#define DWC_TAILQ_EMPTY(head)   (TAILQ_FIRST(head) == TAILQ_END(head))
#define DWC_TAILQ_FOREACH(var, head, field)
#define DWC_TAILQ_FOREACH_REVERSE(var, head, headname, field)
#define DWC_TAILQ_INIT(head)
#define DWC_TAILQ_INSERT_HEAD(head, elm, field)
#define DWC_TAILQ_INSERT_TAIL(head, elm, field)
#define DWC_TAILQ_INSERT_AFTER(head, listelm, elm, field)
#define DWC_TAILQ_INSERT_BEFORE(listelm, elm, field)
#define DWC_TAILQ_REMOVE(head, elm, field)
#define DWC_TAILQ_REPLACE(head, elm, elm2, field)
#define DWC_CIRCLEQ_HEAD(name, type)
++#define DWC_CIRCLEQ_HEAD_INITIALIZER(head)   { DWC_CIRCLEQ_END(&head), DWC_CIRCLEQ_END(&head) }
#define DWC_CIRCLEQ_ENTRY(type)
++#define DWC_CIRCLEQ_FIRST(head)   ((head)->cqh_first)
++#define DWC_CIRCLEQ_LAST(head)   ((head)->cqh_last)
++#define DWC_CIRCLEQ_END(head)   ((void *)(head))
++#define DWC_CIRCLEQ_NEXT(elm, field)   ((elm)->field.cqe_next)
++#define DWC_CIRCLEQ_PREV(elm, field)   ((elm)->field.cqe_prev)
++#define DWC_CIRCLEQ_EMPTY(head)   (DWC_CIRCLEQ_FIRST(head) == DWC_CIRCLEQ_END(head))
++#define DWC_CIRCLEQ_EMPTY_ENTRY(elm, field)   (((elm)->field.cqe_next == NULL) && ((elm)->field.cqe_prev == NULL))
#define DWC_CIRCLEQ_FOREACH(var, head, field)
#define DWC_CIRCLEQ_FOREACH_SAFE(var, var2, head, field)
#define DWC_CIRCLEQ_FOREACH_REVERSE(var, head, field)
#define DWC_CIRCLEQ_INIT(head)
#define DWC_CIRCLEQ_INIT_ENTRY(elm, field)
#define DWC_CIRCLEQ_INSERT_AFTER(head, listelm, elm, field)
#define DWC_CIRCLEQ_INSERT_BEFORE(head, listelm, elm, field)
#define DWC_CIRCLEQ_INSERT_HEAD(head, elm, field)
#define DWC_CIRCLEQ_INSERT_TAIL(head, elm, field)
#define DWC_CIRCLEQ_REMOVE(head, elm, field)
#define DWC_CIRCLEQ_REMOVE_INIT(head, elm, field)
#define DWC_CIRCLEQ_REPLACE(head, elm, elm2, field)

Typedefs

++typedef dwc_list_link dwc_list_link_t
++

Define Documentation

++ ++
++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
#define DWC_LIST_INIT (link   ) 
++
++
++ ++

++Value:

do{             \
++        (link)->next = (link);          \
++        (link)->prev = (link);          \
++} while(0)
++
++
++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
#define DWC_LIST_ENTRY (link,
type,
field   ) 
++
++
++ ++

++Value:

(type *)                \
++        ((uint8_t *)(link) - (size_t)(&((type *)0)->field))
++
++
++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
#define DWC_LIST_INSERT_HEAD (list,
link   ) 
++
++
++ ++

++Value:

do {                    \
++        (link)->next = (list)->next;                            \
++        (link)->prev = (list);                                  \
++        (list)->next->prev = link;                              \
++        (list)->next = link;                                    \
++} while(0)
++
++
++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
#define DWC_LIST_INSERT_TAIL (list,
link   ) 
++
++
++ ++

++Value:

do {                    \
++        (link)->next = list;                                    \
++        (link)->prev = (list)->prev;                            \
++        (list)->prev->next = link;                              \
++        (list)->prev = link;                                    \
++} while(0)
++
++
++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
#define DWC_LIST_REMOVE (link   ) 
++
++
++ ++

++Value:

do {                            \
++        (link)->next->prev = (link)->prev;                      \
++        (link)->prev->next = (link)->next;                      \
++} while(0)
++
++
++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
#define DWC_LIST_REMOVE_INIT (link   ) 
++
++
++ ++

++Value:

do {                            \
++        DWC_LIST_REMOVE(link);                                  \
++        DWC_LIST_INIT(link);                                    \
++} while(0)
++
++
++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
#define DWC_LIST_MOVE_HEAD (list,
link   ) 
++
++
++ ++

++Value:

do {                    \
++        DWC_LIST_REMOVE(link);                                  \
++        DWC_LIST_INSERT_HEAD(list, link);                       \
++} while(0)
++
++
++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
#define DWC_LIST_MOVE_TAIL (list,
link   ) 
++
++
++ ++

++Value:

do {                    \
++        DWC_LIST_REMOVE(link);                                  \
++        DWC_LIST_INSERT_TAIL(list, link);                       \
++} while(0)
++
++
++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
#define DWC_LIST_FOREACH (var,
list   ) 
++
++
++ ++

++Value:

for((var) = DWC_LIST_FIRST(list);                       \
++            (var) != DWC_LIST_END(list);                        \
++            (var) = DWC_LIST_NEXT(var))
++
++
++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
#define DWC_LIST_FOREACH_SAFE (var,
var2,
list   ) 
++
++
++ ++

++Value:

for((var) = DWC_LIST_FIRST(list), var2 = DWC_LIST_NEXT(var);    \
++            (var) != DWC_LIST_END(list);                        \
++            (var) = (var2), var2 = DWC_LIST_NEXT(var2))
++
++
++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
#define DWC_LIST_FOREACH_REVERSE (var,
list   ) 
++
++
++ ++

++Value:

for((var) = DWC_LIST_LAST(list);                        \
++            (var) != DWC_LIST_END(list);                        \
++            (var) = DWC_LIST_PREV(var))
++
++
++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
#define DWC_SLIST_HEAD (name,
type   ) 
++
++
++ ++

++Value:

struct name {                                                           \
++        struct type *slh_first; /* first element */                     \
++}
++
++
++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
#define DWC_SLIST_ENTRY (type   ) 
++
++
++ ++

++Value:

struct {                                                                \
++        struct type *sle_next;  /* next element */                      \
++}
++
++
++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
#define DWC_SLIST_FOREACH (var,
head,
field   ) 
++
++
++ ++

++Value:

for((var) = SLIST_FIRST(head);                                  \
++            (var) != SLIST_END(head);                                   \
++            (var) = SLIST_NEXT(var, field))
++
++
++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
#define DWC_SLIST_FOREACH_PREVPTR (var,
varp,
head,
field   ) 
++
++
++ ++

++Value:

for ((varp) = &SLIST_FIRST((head));                             \
++            ((var) = *(varp)) != SLIST_END(head);                       \
++            (varp) = &SLIST_NEXT((var), field))
++
++
++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
#define DWC_SLIST_INIT (head   ) 
++
++
++ ++

++Value:

{                                               \
++        SLIST_FIRST(head) = SLIST_END(head);                            \
++}
++
++
++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
#define DWC_SLIST_INSERT_AFTER (slistelm,
elm,
field   ) 
++
++
++ ++

++Value:

do {                    \
++        (elm)->field.sle_next = (slistelm)->field.sle_next;             \
++        (slistelm)->field.sle_next = (elm);                             \
++} while (0)
++
++
++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
#define DWC_SLIST_INSERT_HEAD (head,
elm,
field   ) 
++
++
++ ++

++Value:

do {                    \
++        (elm)->field.sle_next = (head)->slh_first;                      \
++        (head)->slh_first = (elm);                                      \
++} while (0)
++
++
++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
#define DWC_SLIST_REMOVE_NEXT (head,
elm,
field   ) 
++
++
++ ++

++Value:

do {                    \
++        (elm)->field.sle_next = (elm)->field.sle_next->field.sle_next;  \
++} while (0)
++
++
++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
#define DWC_SLIST_REMOVE_HEAD (head,
field   ) 
++
++
++ ++

++Value:

do {                            \
++        (head)->slh_first = (head)->slh_first->field.sle_next;          \
++} while (0)
++
++
++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
#define DWC_SLIST_REMOVE (head,
elm,
type,
field   ) 
++
++
++ ++

++Value:

do {                    \
++        if ((head)->slh_first == (elm)) {                               \
++                SLIST_REMOVE_HEAD((head), field);                       \
++        }                                                               \
++        else {                                                          \
++                struct type *curelm = (head)->slh_first;                \
++                while( curelm->field.sle_next != (elm) )                \
++                        curelm = curelm->field.sle_next;                \
++                curelm->field.sle_next =                                \
++                    curelm->field.sle_next->field.sle_next;             \
++        }                                                               \
++} while (0)
++
++
++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
#define DWC_SIMPLEQ_HEAD (name,
type   ) 
++
++
++ ++

++Value:

struct name {                                                           \
++        struct type *sqh_first; /* first element */                     \
++        struct type **sqh_last; /* addr of last next element */         \
++}
++
++
++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
#define DWC_SIMPLEQ_ENTRY (type   ) 
++
++
++ ++

++Value:

struct {                                                                \
++        struct type *sqe_next;  /* next element */                      \
++}
++
++
++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
#define DWC_SIMPLEQ_FOREACH (var,
head,
field   ) 
++
++
++ ++

++Value:

for((var) = SIMPLEQ_FIRST(head);                                \
++            (var) != SIMPLEQ_END(head);                                 \
++            (var) = SIMPLEQ_NEXT(var, field))
++
++
++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
#define DWC_SIMPLEQ_INIT (head   ) 
++
++
++ ++

++Value:

do {                                            \
++        (head)->sqh_first = NULL;                                       \
++        (head)->sqh_last = &(head)->sqh_first;                          \
++} while (0)
++
++
++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
#define DWC_SIMPLEQ_INSERT_HEAD (head,
elm,
field   ) 
++
++
++ ++

++Value:

do {                    \
++        if (((elm)->field.sqe_next = (head)->sqh_first) == NULL)        \
++                (head)->sqh_last = &(elm)->field.sqe_next;              \
++        (head)->sqh_first = (elm);                                      \
++} while (0)
++
++
++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
#define DWC_SIMPLEQ_INSERT_TAIL (head,
elm,
field   ) 
++
++
++ ++

++Value:

do {                    \
++        (elm)->field.sqe_next = NULL;                                   \
++        *(head)->sqh_last = (elm);                                      \
++        (head)->sqh_last = &(elm)->field.sqe_next;                      \
++} while (0)
++
++
++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
#define DWC_SIMPLEQ_INSERT_AFTER (head,
listelm,
elm,
field   ) 
++
++
++ ++

++Value:

do {            \
++        if (((elm)->field.sqe_next = (listelm)->field.sqe_next) == NULL)\
++                (head)->sqh_last = &(elm)->field.sqe_next;              \
++        (listelm)->field.sqe_next = (elm);                              \
++} while (0)
++
++
++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
#define DWC_SIMPLEQ_REMOVE_HEAD (head,
field   ) 
++
++
++ ++

++Value:

do {                    \
++        if (((head)->sqh_first = (head)->sqh_first->field.sqe_next) == NULL) \
++                (head)->sqh_last = &(head)->sqh_first;                  \
++} while (0)
++
++
++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
#define DWC_TAILQ_HEAD (name,
type   ) 
++
++
++ ++

++Value:

struct name {                                                           \
++        struct type *tqh_first; /* first element */                     \
++        struct type **tqh_last; /* addr of last next element */         \
++}
++
++
++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
#define DWC_TAILQ_ENTRY (type   ) 
++
++
++ ++

++Value:

struct {                                                                \
++        struct type *tqe_next;  /* next element */                      \
++        struct type **tqe_prev; /* address of previous next element */  \
++}
++
++
++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
#define DWC_TAILQ_FOREACH (var,
head,
field   ) 
++
++
++ ++

++Value:

for((var) = TAILQ_FIRST(head);                                  \
++            (var) != TAILQ_END(head);                                   \
++            (var) = TAILQ_NEXT(var, field))
++
++
++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
#define DWC_TAILQ_FOREACH_REVERSE (var,
head,
headname,
field   ) 
++
++
++ ++

++Value:

for((var) = TAILQ_LAST(head, headname);                         \
++            (var) != TAILQ_END(head);                                   \
++            (var) = TAILQ_PREV(var, headname, field))
++
++
++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
#define DWC_TAILQ_INIT (head   ) 
++
++
++ ++

++Value:

do {                                            \
++        (head)->tqh_first = NULL;                                       \
++        (head)->tqh_last = &(head)->tqh_first;                          \
++} while (0)
++
++
++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
#define DWC_TAILQ_INSERT_HEAD (head,
elm,
field   ) 
++
++
++ ++

++Value:

do {                    \
++        if (((elm)->field.tqe_next = (head)->tqh_first) != NULL)        \
++                (head)->tqh_first->field.tqe_prev =                     \
++                    &(elm)->field.tqe_next;                             \
++        else                                                            \
++                (head)->tqh_last = &(elm)->field.tqe_next;              \
++        (head)->tqh_first = (elm);                                      \
++        (elm)->field.tqe_prev = &(head)->tqh_first;                     \
++} while (0)
++
++
++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
#define DWC_TAILQ_INSERT_TAIL (head,
elm,
field   ) 
++
++
++ ++

++Value:

do {                    \
++        (elm)->field.tqe_next = NULL;                                   \
++        (elm)->field.tqe_prev = (head)->tqh_last;                       \
++        *(head)->tqh_last = (elm);                                      \
++        (head)->tqh_last = &(elm)->field.tqe_next;                      \
++} while (0)
++
++
++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
#define DWC_TAILQ_INSERT_AFTER (head,
listelm,
elm,
field   ) 
++
++
++ ++

++Value:

do {            \
++        if (((elm)->field.tqe_next = (listelm)->field.tqe_next) != NULL)\
++                (elm)->field.tqe_next->field.tqe_prev =                 \
++                    &(elm)->field.tqe_next;                             \
++        else                                                            \
++                (head)->tqh_last = &(elm)->field.tqe_next;              \
++        (listelm)->field.tqe_next = (elm);                              \
++        (elm)->field.tqe_prev = &(listelm)->field.tqe_next;             \
++} while (0)
++
++
++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
#define DWC_TAILQ_INSERT_BEFORE (listelm,
elm,
field   ) 
++
++
++ ++

++Value:

do {                    \
++        (elm)->field.tqe_prev = (listelm)->field.tqe_prev;              \
++        (elm)->field.tqe_next = (listelm);                              \
++        *(listelm)->field.tqe_prev = (elm);                             \
++        (listelm)->field.tqe_prev = &(elm)->field.tqe_next;             \
++} while (0)
++
++
++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
#define DWC_TAILQ_REMOVE (head,
elm,
field   ) 
++
++
++ ++

++Value:

do {                            \
++        if (((elm)->field.tqe_next) != NULL)                            \
++                (elm)->field.tqe_next->field.tqe_prev =                 \
++                    (elm)->field.tqe_prev;                              \
++        else                                                            \
++                (head)->tqh_last = (elm)->field.tqe_prev;               \
++        *(elm)->field.tqe_prev = (elm)->field.tqe_next;                 \
++} while (0)
++
++
++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
#define DWC_TAILQ_REPLACE (head,
elm,
elm2,
field   ) 
++
++
++ ++

++Value:

do {                    \
++        if (((elm2)->field.tqe_next = (elm)->field.tqe_next) != NULL)   \
++                (elm2)->field.tqe_next->field.tqe_prev =                \
++                    &(elm2)->field.tqe_next;                            \
++        else                                                            \
++                (head)->tqh_last = &(elm2)->field.tqe_next;             \
++        (elm2)->field.tqe_prev = (elm)->field.tqe_prev;                 \
++        *(elm2)->field.tqe_prev = (elm2);                               \
++} while (0)
++
++
++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
#define DWC_CIRCLEQ_HEAD (name,
type   ) 
++
++
++ ++

++Value:

struct name {                                                           \
++        struct type *cqh_first;         /* first element */             \
++        struct type *cqh_last;          /* last element */              \
++}
++
++
++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
#define DWC_CIRCLEQ_ENTRY (type   ) 
++
++
++ ++

++Value:

struct {                                                                \
++        struct type *cqe_next;          /* next element */              \
++        struct type *cqe_prev;          /* previous element */          \
++}
++
++
++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
#define DWC_CIRCLEQ_FOREACH (var,
head,
field   ) 
++
++
++ ++

++Value:

for((var) = DWC_CIRCLEQ_FIRST(head);                            \
++            (var) != DWC_CIRCLEQ_END(head);                                     \
++            (var) = DWC_CIRCLEQ_NEXT(var, field))
++
++
++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
#define DWC_CIRCLEQ_FOREACH_SAFE (var,
var2,
head,
field   ) 
++
++
++ ++

++Value:

for((var) = DWC_CIRCLEQ_FIRST(head), var2 = DWC_CIRCLEQ_NEXT(var, field);                               \
++            (var) != DWC_CIRCLEQ_END(head);                                     \
++            (var) = var2, var2 = DWC_CIRCLEQ_NEXT(var, field))
++
++
++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
#define DWC_CIRCLEQ_FOREACH_REVERSE (var,
head,
field   ) 
++
++
++ ++

++Value:

for((var) = DWC_CIRCLEQ_LAST(head);                                     \
++            (var) != DWC_CIRCLEQ_END(head);                                     \
++            (var) = DWC_CIRCLEQ_PREV(var, field))
++
++
++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
#define DWC_CIRCLEQ_INIT (head   ) 
++
++
++ ++

++Value:

do {                                            \
++        (head)->cqh_first = DWC_CIRCLEQ_END(head);                              \
++        (head)->cqh_last = DWC_CIRCLEQ_END(head);                               \
++} while (0)
++
++
++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
#define DWC_CIRCLEQ_INIT_ENTRY (elm,
field   ) 
++
++
++ ++

++Value:

do { \
++        (elm)->field.cqe_next = NULL; \
++        (elm)->field.cqe_prev = NULL; \
++} while (0)
++
++
++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
#define DWC_CIRCLEQ_INSERT_AFTER (head,
listelm,
elm,
field   ) 
++
++
++ ++

++Value:

do {            \
++        (elm)->field.cqe_next = (listelm)->field.cqe_next;              \
++        (elm)->field.cqe_prev = (listelm);                              \
++        if ((listelm)->field.cqe_next == DWC_CIRCLEQ_END(head))         \
++                (head)->cqh_last = (elm);                               \
++        else                                                            \
++                (listelm)->field.cqe_next->field.cqe_prev = (elm);      \
++        (listelm)->field.cqe_next = (elm);                              \
++} while (0)
++
++
++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
#define DWC_CIRCLEQ_INSERT_BEFORE (head,
listelm,
elm,
field   ) 
++
++
++ ++

++Value:

do {            \
++        (elm)->field.cqe_next = (listelm);                              \
++        (elm)->field.cqe_prev = (listelm)->field.cqe_prev;              \
++        if ((listelm)->field.cqe_prev == DWC_CIRCLEQ_END(head))         \
++                (head)->cqh_first = (elm);                              \
++        else                                                            \
++                (listelm)->field.cqe_prev->field.cqe_next = (elm);      \
++        (listelm)->field.cqe_prev = (elm);                              \
++} while (0)
++
++
++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
#define DWC_CIRCLEQ_INSERT_HEAD (head,
elm,
field   ) 
++
++
++ ++

++Value:

do {                    \
++        (elm)->field.cqe_next = (head)->cqh_first;                      \
++        (elm)->field.cqe_prev = DWC_CIRCLEQ_END(head);                  \
++        if ((head)->cqh_last == DWC_CIRCLEQ_END(head))                  \
++                (head)->cqh_last = (elm);                               \
++        else                                                            \
++                (head)->cqh_first->field.cqe_prev = (elm);              \
++        (head)->cqh_first = (elm);                                      \
++} while (0)
++
++
++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
#define DWC_CIRCLEQ_INSERT_TAIL (head,
elm,
field   ) 
++
++
++ ++

++Value:

do {                    \
++        (elm)->field.cqe_next = DWC_CIRCLEQ_END(head);                  \
++        (elm)->field.cqe_prev = (head)->cqh_last;                       \
++        if ((head)->cqh_first == DWC_CIRCLEQ_END(head))                 \
++                (head)->cqh_first = (elm);                              \
++        else                                                            \
++                (head)->cqh_last->field.cqe_next = (elm);               \
++        (head)->cqh_last = (elm);                                       \
++} while (0)
++
++
++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
#define DWC_CIRCLEQ_REMOVE (head,
elm,
field   ) 
++
++
++ ++

++Value:

do {                            \
++        if ((elm)->field.cqe_next == DWC_CIRCLEQ_END(head))                     \
++                (head)->cqh_last = (elm)->field.cqe_prev;               \
++        else                                                            \
++                (elm)->field.cqe_next->field.cqe_prev =                 \
++                    (elm)->field.cqe_prev;                              \
++        if ((elm)->field.cqe_prev == DWC_CIRCLEQ_END(head))                     \
++                (head)->cqh_first = (elm)->field.cqe_next;              \
++        else                                                            \
++                (elm)->field.cqe_prev->field.cqe_next =                 \
++                    (elm)->field.cqe_next;                              \
++} while (0)
++
++
++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
#define DWC_CIRCLEQ_REMOVE_INIT (head,
elm,
field   ) 
++
++
++ ++

++Value:

do { \
++        DWC_CIRCLEQ_REMOVE(head, elm, field); \
++        DWC_CIRCLEQ_INIT_ENTRY(elm, field); \
++} while (0)
++
++
++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
#define DWC_CIRCLEQ_REPLACE (head,
elm,
elm2,
field   ) 
++
++
++ ++

++Value:

do {                    \
++        if (((elm2)->field.cqe_next = (elm)->field.cqe_next) ==         \
++            DWC_CIRCLEQ_END(head))                                              \
++                (head).cqh_last = (elm2);                               \
++        else                                                            \
++                (elm2)->field.cqe_next->field.cqe_prev = (elm2);        \
++        if (((elm2)->field.cqe_prev = (elm)->field.cqe_prev) ==         \
++            DWC_CIRCLEQ_END(head))                                              \
++                (head).cqh_first = (elm2);                              \
++        else                                                            \
++                (elm2)->field.cqe_prev->field.cqe_next = (elm2);        \
++} while (0)
++
++
++

++

Generated on Tue May 5 02:22:50 2009 for Synopsys DWC Portability and Common Library for UWB by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_common_port/doc/html/dwc__modpow_8h.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_common_port/doc/html/dwc__modpow_8h.html 2013-07-26 19:31:19.000000000 +0000 +@@ -0,0 +1,48 @@ ++ ++ ++Synopsys DWC Portability and Common Library for UWB: dwc_modpow.h File Reference ++ ++ ++ ++ ++
++
++
++
++
++dwc_common_port
++

dwc_modpow.h File Reference

Detailed Description

++This file defines the module exponentiation function which is only used internally by the DWC UWB modules for calculation of PKs during numeric association. ++

++The routine is taken from the PUTTY, an open source terminal emulator. The PUTTY License is preserved in the dwc_modpow.c file. ++

++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++

Typedefs

++typedef uint32_t BignumInt
++typedef uint64_t BignumDblInt
++typedef BignumInt * Bignum

Functions

++Bignum dwc_modpow (Bignum base_in, Bignum exp, Bignum mod)
++

Generated on Tue May 5 02:22:50 2009 for Synopsys DWC Portability and Common Library for UWB by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_common_port/doc/html/dwc__notifier_8h.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_common_port/doc/html/dwc__notifier_8h.html 2013-07-26 19:31:19.000000000 +0000 +@@ -0,0 +1,306 @@ ++ ++ ++Synopsys DWC Portability and Common Library for UWB: dwc_notifier.h File Reference ++ ++ ++ ++ ++
++
++
++
++
++dwc_common_port
++

dwc_notifier.h File Reference

Detailed Description

++A simple implementation of the Observer pattern. ++

++Any "module" can register as an observer or notifier. The notion of "module" is abstract and can mean anything used to identify either an observer or notifier. Usually it will be a pointer to a data structure which contains some state, ie an object.

++Before any notifiers can be added, the global notification manager must be brought up with dwc_alloc_notification_manager(). dwc_free_notification_manager() will bring it down and free all resources. These would typically be called upon module load and unload. The notification manager is a single global instance that handles all registered observable modules and observers so this should be done only once.

++A module can be observable by using Notifications to publicize some general information about it's state or operation. It does not care who listens, or even if anyone listens, or what they do with the information. The observable modules do not need to know any information about it's observers or their interface, or their state or data.

++Any module can register to emit Notifications. It should publish a list of notifications that it can emit and their behavior, such as when they will get triggered, and what information will be provided to the observer. Then it should register itself as an observable module. See dwc_register_notifier().

++Any module can observe any observable, registered module, provided it has a handle to the other module and knows what notifications to observe. See dwc_add_observer().

++A function of type dwc_notifier_callback_t is called whenever a notification is triggered with one or more observers observing it. This function is called in it's own process so it may sleep or block if needed. It is guaranteed to be called sometime after the notification has occurred and will be called once per each time the notification is triggered. It will NOT be called in the same process context used to trigger the notification.

++Limitiations

++Keep in mind that Notifications that can be triggered in rapid sucession may schedule too many processes too handle. Be aware of this limitation when designing to use notifications, and only add notifications for appropriate observable information.

++Also Notification callbacks are not synchronous. If you need to synchronize the behavior between module/observer you must use other means. And perhaps that will mean Notifications are not the proper solution. ++

++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++

Typedefs

++typedef dwc_notifier dwc_notifier_t
typedef void(*) dwc_notifier_callback_t (void *object, char *notification, void *observer, void *notification_data, void *user_data)
 The callback function must be of this type.

Functions

void dwc_alloc_notification_manager (void)
 Brings up the notification manager.
void dwc_free_notification_manager (void)
 Brings down the notification manager.
dwc_notifier_t * dwc_register_notifier (void *object)
 This function register an observable module.
void dwc_unregister_notifier (dwc_notifier_t *notifier)
 This function unregister an observable module.
int dwc_add_observer (void *observer, void *object, char *notification, dwc_notifier_callback_t callback, void *user_data)
 Add a module as an observer to the observable module.
int dwc_remove_observer (void *observer)
 Removes the specified observer from all notifications that it is currently observing.
void dwc_notify (dwc_notifier_t *notifier, char *notification, void *notification_data)
 This function triggers a Notification.
++

Typedef Documentation

++ ++
++
++ ++ ++ ++ ++
typedef void(*) dwc_notifier_callback_t(void *object, char *notification, void *observer, void *notification_data, void *user_data)
++
++
++ ++

++The callback function must be of this type. ++

++

Parameters:
++ ++ ++ ++ ++ ++ ++
object This is the object that is being observed.
notification This is the notification that was triggered.
observer This is the observer
notification_data This is notification-specific data that the notifier has included in this notification. The value of this should be published in the documentation of the observable module with the notifications.
user_data This is any custom data that the observer provided when adding itself as an observer to the notification.
++
++ ++
++

++

Function Documentation

++ ++
++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_alloc_notification_manager (void   ) 
++
++
++ ++

++Brings up the notification manager. ++

++ ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_free_notification_manager (void   ) 
++
++
++ ++

++Brings down the notification manager. ++

++ ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
dwc_notifier_t* dwc_register_notifier (void *  object  ) 
++
++
++ ++

++This function register an observable module. ++

++A dwc_notifier_t object is returned to the observable module. This is an opaque object that is used by the observable module to trigger notifications. This object should only be accessible to functions that are authorized to trigger notifications for this module. Observers do not need this object. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_unregister_notifier (dwc_notifier_t *  notifier  ) 
++
++
++ ++

++This function unregister an observable module. ++

++All observers have to be removed prior to unregistration. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int dwc_add_observer (void *  observer,
void *  object,
char *  notification,
dwc_notifier_callback_t  callback,
void *  user_data 
)
++
++
++ ++

++Add a module as an observer to the observable module. ++

++The observable module needs to have previously registered with the notification manager.

++

Parameters:
++ ++ ++ ++ ++ ++ ++
observer The observer module
object The module to observe
notification The notification to observe
callback The callback function to call
user_data Any additional user data to pass into the callback function
++
++ ++
++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int dwc_remove_observer (void *  observer  ) 
++
++
++ ++

++Removes the specified observer from all notifications that it is currently observing. ++

++ ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_notify (dwc_notifier_t *  notifier,
char *  notification,
void *  notification_data 
)
++
++
++ ++

++This function triggers a Notification. ++

++It should be called by the observable module, or any module or library which the observable module allows to trigger notification on it's behalf. Such as the dwc_cc_t.

++dwc_notify is a non-blocking function. Callbacks are scheduled called in their own process context for each trigger. Callbacks can be blocking. dwc_notify can be called from interrupt context if needed. ++

++

++

Generated on Tue May 5 02:22:50 2009 for Synopsys DWC Portability and Common Library for UWB by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_common_port/doc/html/dwc__os_8h.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_common_port/doc/html/dwc__os_8h.html 2013-07-26 19:31:19.000000000 +0000 +@@ -0,0 +1,3090 @@ ++ ++ ++Synopsys DWC Portability and Common Library for UWB: dwc_os.h File Reference ++ ++ ++ ++ ++
++
++
++
++
++dwc_common_port
++

dwc_os.h File Reference

Detailed Description

++DWC portability library, low level os-wrapper functions. ++

++ ++

++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++

Primitive Types and Values

++#define YES   1
++#define NO   0
typedef uint8_t dwc_bool_t
 We define a boolean type for consistency.

Error Codes

++#define DWC_E_INVALID   1001
++#define DWC_E_NO_MEMORY   1002
++#define DWC_E_NO_DEVICE   1003
++#define DWC_E_NOT_SUPPORTED   1004
++#define DWC_E_TIMEOUT   1005
++#define DWC_E_BUSY   1006
++#define DWC_E_AGAIN   1007
++#define DWC_E_RESTART   1008
++#define DWC_E_ABORT   1009
++#define DWC_E_SHUTDOWN   1010
++#define DWC_E_NO_DATA   1011
++#define DWC_E_DISCONNECT   2000
++#define DWC_E_UNKNOWN   3000
++#define DWC_E_NO_STREAM_RES   4001
++#define DWC_E_COMMUNICATION   4002
++#define DWC_E_OVERFLOW   4003
++#define DWC_E_PROTOCOL   4004
++#define DWC_E_IN_PROGRESS   4005
++#define DWC_E_PIPE   4006
++#define DWC_E_IO   4007
++#define DWC_E_NO_SPACE   4008

Tracing/Logging Functions

These function provide the capability to add tracing, debugging, and error messages, as well exceptions as assertions. The WUDEV uses these extensively. These could be logged to the main console, the serial port, an internal buffer, etc. These functions could also be no-op if they are too expensive on your system. By default undefining the DEBUG macro already no-ops some of these functions.

++#define dwc_in_irq   DWC_IN_IRQ
++#define dwc_vprintf   DWC_VPRINTF
++#define dwc_vsnprintf   DWC_VSNPRINTF
++#define dwc_printf   DWC_PRINTF
++#define dwc_sprintf   DWC_SPRINTF
++#define dwc_snprintf   DWC_SNPRINTF
++#define dwc_exception   DWC_EXCEPTION
#define DWC_DEBUG(_format, _args...)   __DWC_DEBUG("DEBUG:%s:%s: " _format "\n", __func__, dwc_irq(), ## _args)
 Prints out a Debug message.
++#define dwc_debug   DWC_DEBUG
#define DWC_INFO(_format, _args...)   DWC_PRINTF("INFO:%s: " _format "\n", dwc_irq(), ## _args)
 Prints out an informative message.
++#define dwc_info   DWC_INFO
#define DWC_WARN(_format, _args...)   __DWC_WARN("WARN:%s:%s:%d: " _format "\n", dwc_irq(), __func__, __LINE__, ## _args)
 Prints out a warning message.
++#define dwc_warn   DWC_WARN
#define DWC_ERROR(_format, _args...)   __DWC_ERROR("ERROR:%s:%s:%d: " _format "\n", dwc_irq(), __func__, __LINE__, ## _args)
 Prints out an error message.
++#define dwc_error   DWC_ERROR
++#define DWC_PROTO_ERROR(_format, _args...)   __DWC_WARN("ERROR:%s:%s:%d: " _format "\n", dwc_irq(), __func__, __LINE__, ## _args)
++#define dwc_proto_error   DWC_PROTO_ERROR
#define DWC_ASSERT(_expr, _format, _args...)   if (!(_expr)) { DWC_EXCEPTION("%s:%s:%d: " _format "\n", dwc_irq(), __FILE__, __LINE__, ## _args); }
 Prints out a exception error message if the _expr expression fails.
++#define dwc_assert   DWC_ASSERT
dwc_bool_t DWC_IN_IRQ (void)
 Returns non-zero if in interrupt context.
static char * dwc_irq (void)
 Returns "IRQ" if DWC_IN_IRQ is true.
void DWC_VPRINTF (char *format, va_list args)
 A vprintf() clone.
int DWC_VSNPRINTF (char *str, int size, char *format, va_list args)
 A vsnprintf() clone.
void DWC_PRINTF (char *format,...)
 printf() clone.
int DWC_SPRINTF (char *string, char *format,...)
 sprintf() clone.
int DWC_SNPRINTF (char *string, int size, char *format,...)
 snprintf() clone.
void __DWC_WARN (char *format,...)
 Prints a WARNING message.
void __DWC_ERROR (char *format,...)
 Prints an error message.
void DWC_EXCEPTION (char *format,...)
 Prints an exception error message and takes some user-defined action such as print out a backtrace or trigger a breakpoint.
void __DWC_DEBUG (char *format,...)
 Prints out a debug message.

Byter Ordering

The following functions are for conversions between processor's byte ordering and specific ordering you want.

++#define dwc_cpu_to_le32   DWC_CPU_TO_LE32
++#define dwc_cpu_to_be32   DWC_CPU_TO_BE32
++#define dwc_le32_to_cpu   DWC_LE32_TO_CPU
++#define dwc_be32_to_cpu   DWC_BE32_TO_CPU
++#define dwc_cpu_to_le16   DWC_CPU_TO_LE16
++#define dwc_cpu_to_be16   DWC_CPU_TO_BE16
++#define dwc_le16_to_cpu   DWC_LE16_TO_CPU
++#define dwc_be16_to_cpu   DWC_BE16_TO_CPU
uint32_t DWC_CPU_TO_LE32 (void *p)
 Converts 32 bit data in CPU byte ordering to little endian.
uint32_t DWC_CPU_TO_BE32 (void *p)
 Converts 32 bit data in CPU byte orderint to big endian.
uint32_t DWC_LE32_TO_CPU (void *p)
 Converts 32 bit little endian data to CPU byte ordering.
uint32_t DWC_BE32_TO_CPU (void *p)
 Converts 32 bit big endian data to CPU byte ordering.
uint16_t DWC_CPU_TO_LE16 (void *p)
 Converts 16 bit data in CPU byte ordering to little endian.
uint16_t DWC_CPU_TO_BE16 (void *p)
 Converts 16 bit data in CPU byte orderint to big endian.
uint16_t DWC_LE16_TO_CPU (void *p)
 Converts 16 bit little endian data to CPU byte ordering.
uint16_t DWC_BE16_TO_CPU (void *p)
 Converts 16 bit bi endian data to CPU byte ordering.

Register Read/Write

The following five functions should be implemented to read/write registers of 32-bit and 64-bit sizes. All modules use this to read/write register values. The reg value is a pointer to the register calculated from the void *base variable passed into the driver when it is started.

++#define dwc_read_reg32   DWC_READ_REG32
++#define dwc_read_reg64   DWC_READ_REG64
++#define dwc_write_reg32   DWC_WRITE_REG32
++#define dwc_write_reg64   DWC_WRITE_REG64
++#define dwc_modify_reg32   DWC_MODIFY_REG32
uint32_t DWC_READ_REG32 (uint32_t volatile *reg)
 Reads the content of a 32-bit register.
uint64_t DWC_READ_REG64 (uint64_t volatile *reg)
 Reads the content of a 64-bit register.
void DWC_WRITE_REG32 (uint32_t volatile *reg, uint32_t value)
 Writes to a 32-bit register.
void DWC_WRITE_REG64 (uint64_t volatile *reg, uint64_t value)
 Writes to a 64-bit register.
void DWC_MODIFY_REG32 (uint32_t volatile *reg, uint32_t clear_mask, uint32_t set_mask)
 Modify bit values in a register.

Crypto Functions

These are the low-level cryptographic functions used by the driver.

++#define dwc_aes_cbc   DWC_AES_CBC
++#define dwc_random_bytes   DWC_RANDOM_BYTES
++#define dwc_sha256   DWC_SHA256
++#define dwc_hmac_sha256   DWC_HMAC_SHA256
int DWC_AES_CBC (uint8_t *message, uint32_t messagelen, uint8_t *key, uint32_t keylen, uint8_t iv[16], uint8_t *out)
 Perform AES CBC.
void DWC_RANDOM_BYTES (uint8_t *buffer, uint32_t length)
 Fill the provided buffer with random bytes.
int DWC_SHA256 (uint8_t *message, uint32_t len, uint8_t *out)
 Perform the SHA-256 hash function.
int DWC_HMAC_SHA256 (uint8_t *message, uint32_t messagelen, uint8_t *key, uint32_t keylen, uint8_t *out)
 Calculated the HMAC-SHA256.

Memory Allocation

These function provide access to memory allocation. There are only 2 DMA functions and 3 Regular memory functions that need to be implemented. None of the memory debugging routines need to be implemented. The allocation routines all ZERO the contents of the memory.

++Defining DEBUG_MEMORY turns on memory debugging and statistic gathering. This checks for memory leaks, keeping track of alloc/free pairs. It also keeps track of how much memory the driver is using at any given time.

++#define DWC_PAGE_SIZE   4096
++#define DWC_PAGE_OFFSET(addr)   (((uint32_t)addr) & 0xfff)
++#define DWC_PAGE_ALIGNED(addr)   ((((uint32_t)addr) & 0xfff) == 0)
++#define DWC_INVALID_DMA_ADDR   0x0
++#define DWC_ALLOC(_size_)   (dwc_alloc_debug(_size_, __func__, __LINE__))
++#define DWC_ALLOC_ATOMIC(_size_)   (dwc_alloc_atomic_debug(_size_, __func__, __LINE__))
++#define DWC_FREE(_addr_)   (dwc_free_debug(_addr_, __func__, __LINE__))
++#define DWC_DMA_ALLOC(_size_, _dma_)   dwc_dma_alloc_debug(_size_, _dma_, __func__, __LINE__)
++#define DWC_DMA_FREE(_size_, _virt_, _dma_)   dwc_dma_free_debug(_size_, _virt_, _dma_, __func__, __LINE__)
++#define dwc_alloc   DWC_ALLOC
++#define dwc_alloc_atomic   DWC_ALLOC_ATOMIC
++#define dwc_free   DWC_FREE
++#define dwc_dma_alloc   DWC_DMA_ALLOC
++#define dwc_dma_free   DWC_DMA_FREE
++typedef uint32_t dwc_dma_t
void * __DWC_DMA_ALLOC (uint32_t size, dwc_dma_t *dma_addr)
 Allocates a DMA capable buffer and zeroes its contents.
void __DWC_DMA_FREE (uint32_t size, void *virt_addr, dwc_dma_t dma_addr)
 Frees a previosly allocated buffer.
void * __DWC_ALLOC (uint32_t size)
 Allocates a block of memory and zeroes its contents.
void * __DWC_ALLOC_ATOMIC (uint32_t size)
 Allocates a block of memory and zeroes its contents, in an atomic manner which can be used inside interrupt context.
void __DWC_FREE (void *addr)
 Frees a previously allocated buffer.
++void * dwc_alloc_debug (uint32_t size, char const *func, int line)
++void * dwc_alloc_atomic_debug (uint32_t size, char const *func, int line)
++void dwc_free_debug (void *addr, char const *func, int line)
++void * dwc_dma_alloc_debug (uint32_t size, dwc_dma_t *dma_addr, char const *func, int line)
++void dwc_dma_free_debug (uint32_t size, void *virt_addr, dwc_dma_t dma_addr, char const *func, int line)
++void dwc_memory_debug_start (void)
++void dwc_memory_debug_stop (void)
++void dwc_memory_debug_report (void)

Memory and String Processing

++#define dwc_memset   DWC_MEMSET
++#define dwc_memcpy   DWC_MEMCPY
++#define dwc_memmove   DWC_MEMMOVE
++#define dwc_memcmp   DWC_MEMCMP
++#define dwc_strcmp   DWC_STRCMP
++#define dwc_strncmp   DWC_STRNCMP
++#define dwc_strlen   DWC_STRLEN
++#define dwc_strcpy   DWC_STRCPY
++#define dwc_strdup   DWC_STRDUP
++#define dwc_atoi   DWC_ATOI
++#define dwc_atoui   DWC_ATOUI
++#define dwc_utf8_to_utf16le   DWC_UTF8_TO_UTF16LE
void * DWC_MEMSET (void *dest, uint8_t byte, uint32_t size)
 memset() clone
void * DWC_MEMCPY (void *dest, void const *src, uint32_t size)
 memcpy() clone
void * DWC_MEMMOVE (void *dest, void *src, uint32_t size)
 memmove() clone
int DWC_MEMCMP (void *m1, void *m2, uint32_t size)
 memcmp() clone
int DWC_STRCMP (void *s1, void *s2)
 strcmp() clone
int DWC_STRNCMP (void *s1, void *s2, uint32_t size)
 strncmp() clone
int DWC_STRLEN (char const *str)
 strlen() clone, for NULL terminated ASCII strings
char * DWC_STRCPY (char *to, const char *from)
 strcpy() clone, for NULL terminated ASCII strings
char * DWC_STRDUP (char const *str)
 strdup() clone.
int DWC_ATOI (char *str, int32_t *value)
 NOT an atoi() clone.
int DWC_ATOUI (char *str, uint32_t *value)
 Same as above but for unsigned.
int DWC_UTF8_TO_UTF16LE (uint8_t const *utf8string, uint16_t *utf16string, unsigned len)
 This routine returns a UTF16LE unicode encoded string from a UTF8 string.

Wait queues

Wait queues provide a means of synchronizing between threads or processes. A process can block on a waitq if some condition is not true, waiting for it to become true. When the waitq is triggered all waiting process will get unblocked and the condition will be check again. Waitqs should be triggered every time a condition can potentially change.

++#define dwc_waitq_alloc   DWC_WAITQ_ALLOC
++#define dwc_waitq_free   DWC_WAITQ_FREE
++#define dwc_waitq_wait   DWC_WAITQ_WAIT;
++#define dwc_waitq_wait_timeout   DWC_WAITQ_WAIT_TIMEOUT
++#define dwc_waitq_trigger   DWC_WAITQ_TRIGGER
++#define dwc_waitq_abort   DWC_WAITQ_ABORT
++typedef dwc_waitq dwc_waitq_t
typedef int(*) dwc_waitq_condition_t (void *data)
 The type of waitq condition callback function.
dwc_waitq_t * DWC_WAITQ_ALLOC (void)
 Allocate a waitq.
void DWC_WAITQ_FREE (dwc_waitq_t *wq)
 Free a waitq.
int32_t DWC_WAITQ_WAIT (dwc_waitq_t *wq, dwc_waitq_condition_t condition, void *data)
 Check the condition and if it is false, block on the waitq.
int32_t DWC_WAITQ_WAIT_TIMEOUT (dwc_waitq_t *wq, dwc_waitq_condition_t condition, void *data, int32_t msecs)
 Check the condition and if it is false, block on the waitq.
void DWC_WAITQ_TRIGGER (dwc_waitq_t *wq)
 Trigger a waitq, unblocking all processes.
void DWC_WAITQ_ABORT (dwc_waitq_t *wq)
 Unblock all processes waiting on the waitq with an ABORTED result.

Threads

A thread must be explicitly stopped. It must check DWC_THREAD_SHOULD_STOP whenever it is woken up, and then return. The DWC_THREAD_STOP function returns the value from the thread.

++#define dwc_thread_run   DWC_THREAD_RUN
++#define dwc_thread_stop   DWC_THREAD_STOP
++#define dwc_thread_should_stop   DWC_THREAD_SHOULD_STOP
++typedef dwc_thread dwc_thread_t
typedef int(*) dwc_thread_function_t (void *data)
 The thread function.
dwc_thread_t * DWC_THREAD_RUN (dwc_thread_function_t thread_function, char *name, void *data)
 Create a thread and start it running the thread_function.
int DWC_THREAD_STOP (dwc_thread_t *thread)
 Stops a thread.
dwc_bool_t DWC_THREAD_SHOULD_STOP (void)
 Signifies to the thread that it must stop.

Work queues

Workqs are used to queue a callback function to be called at some later time, in another thread.

++#define dwc_workq_alloc   DWC_WORKQ_ALLOC
++#define dwc_workq_free   DWC_WORKQ_FREE
++#define dwc_workq_schedule   DWC_WORKQ_SCHEDULE
++#define dwc_workq_schedule_delayed   DWC_WORKQ_SCHEDULE_DELAYED
++#define dwc_workq_pending   DWC_WORKQ_PENDING
++#define dwc_workq_wait_work_done   DWC_WORKQ_WAIT_WORK_DONE
++typedef dwc_workq dwc_workq_t
typedef void(*) dwc_work_callback_t (void *data)
 The type of the callback function to be called.
dwc_workq_t * DWC_WORKQ_ALLOC (char *name)
 Allocate a workq.
void DWC_WORKQ_FREE (dwc_workq_t *workq)
 Free a workq.
void DWC_WORKQ_SCHEDULE (dwc_workq_t *workq, dwc_work_callback_t work_cb, void *data, char *format,...)
 Schedule a callback on the workq, passing in data.
void DWC_WORKQ_SCHEDULE_DELAYED (dwc_workq_t *workq, dwc_work_callback_t work_cb, void *data, uint32_t time, char *format,...)
 Schedule a callback on the workq, that will be called until at least given number miliseconds have passed.
int DWC_WORKQ_PENDING (dwc_workq_t *workq)
 The number of processes in the workq.
int DWC_WORKQ_WAIT_WORK_DONE (dwc_workq_t *workq, int timeout)
 Blocks until all the work in the workq is complete or timed out.

Tasklets

++#define dwc_task_alloc   DWC_TASK_ALLOC
++#define dwc_task_free   DWC_TASK_FREE
++#define dwc_task_schedule   DWC_TASK_SCHEDULE
++typedef dwc_tasklet dwc_tasklet_t
++typedef void(*) dwc_tasklet_callback_t (void *data)
++dwc_tasklet_t * DWC_TASK_ALLOC (dwc_tasklet_callback_t cb, void *data)
++void DWC_TASK_FREE (dwc_tasklet_t *t)
++void DWC_TASK_SCHEDULE (dwc_tasklet_t *task)

Timer

Callbacks must be small and atomic.

++#define dwc_timer_alloc   DWC_TIMER_ALLOC
++#define dwc_timer_free   DWC_TIMER_FREE
++#define dwc_timer_schedule   DWC_TIMER_SCHEDULE
++#define dwc_timer_cancel   DWC_TIMER_CANCEL
++typedef dwc_timer dwc_timer_t
++typedef void(*) dwc_timer_callback_t (void *data)
++dwc_timer_t * DWC_TIMER_ALLOC (char *name, dwc_timer_callback_t cb, void *data)
++void DWC_TIMER_FREE (dwc_timer_t *timer)
void DWC_TIMER_SCHEDULE (dwc_timer_t *timer, uint32_t time)
 Schedules the timer to run at time ms from now.
void DWC_TIMER_CANCEL (dwc_timer_t *timer)
 Disables the timer from execution.

Spinlocks

These locks are used when the work between the lock/unlock is atomic and short. Interrupts are also disabled during the lock/unlock and thus they are suitable to lock between interrupt/non-interrupt context. They also lock between processes if you have multiple CPUs or Preemption. If you don't have multiple CPUS or Preemption, then the you can simply implement the DWC_SPINLOCK and DWC_SPINUNLOCK to disable and enable interrupts. Because the work between the lock/unlock is atomic, the process context will never change, and so you never have to lock between processes.

++#define dwc_spinlock_alloc   DWC_SPINLOCK_ALLOC
++#define dwc_spinlock_free   DWC_SPINLOCK_FREE
++#define dwc_spinlock_irqsave   DWC_SPINLOCK_IRQSAVE
++#define dwc_spinunlock_irqrestore   DWC_SPINUNLOCK_IRQRESTORE
++#define dwc_spinlock   DWC_SPINLOCK
++#define dwc_spinunlock   DWC_SPINUNLOCK
++typedef dwc_spinlock dwc_spinlock_t
dwc_spinlock_t * DWC_SPINLOCK_ALLOC (void)
 Returns an initialized lock variable.
void DWC_SPINLOCK_FREE (dwc_spinlock_t *lock)
 Frees an initialized lock variable.
void DWC_SPINLOCK_IRQSAVE (dwc_spinlock_t *lock, uint64_t *flags)
 Disables interrupts and blocks until it acquires the lock.
void DWC_SPINUNLOCK_IRQRESTORE (dwc_spinlock_t *lock, uint64_t flags)
 Re-enables the interrupt and releases the lock.
void DWC_SPINLOCK (dwc_spinlock_t *lock)
 Blocks until it acquires the lock.
void DWC_SPINUNLOCK (dwc_spinlock_t *lock)
 Releases the lock.

Mutexes

Unlike spinlocks Mutexes lock only between processes and the work between the lock/unlock CAN block, therefore it CANNOT be called from interrupt context.

++#define dwc_mutex_alloc   DWC_MUTEX_ALLOC
++#define dwc_mutex_free   DWC_MUTEX_FREE
++#define dwc_mutex_lock   DWC_MUTEX_LOCK
++#define dwc_mutex_trylock   DWC_MUTEX_TRYLOCK
++#define dwc_mutex_unlock   DWC_MUTEX_UNLOCK
++typedef dwc_mutex dwc_mutex_t
++dwc_mutex_t * DWC_MUTEX_ALLOC (void)
++void DWC_MUTEX_FREE (dwc_mutex_t *mutex)
++void DWC_MUTEX_LOCK (dwc_mutex_t *mutex)
int DWC_MUTEX_TRYLOCK (dwc_mutex_t *mutex)
 Non-blocking lock returns 1 on successful lock.
++void DWC_MUTEX_UNLOCK (dwc_mutex_t *mutex)

Time

++#define dwc_udelay   DWC_UDELAY
++#define dwc_mdelay   DWC_MDELAY
++#define dwc_msleep   DWC_MSLEEP
++#define dwc_time   DWC_TIME
void DWC_UDELAY (uint32_t usecs)
 Microsecond delay.
void DWC_MDELAY (uint32_t msecs)
 Millisecond delay.
void DWC_MSLEEP (uint32_t msecs)
 Non-busy waiting.
++uint32_t DWC_TIME (void)
++

Define Documentation

++ ++
++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
#define DWC_DEBUG (_format,
_args...   )    __DWC_DEBUG("DEBUG:%s:%s: " _format "\n", __func__, dwc_irq(), ## _args)
++
++
++ ++

++Prints out a Debug message. ++

++ ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
#define DWC_INFO (_format,
_args...   )    DWC_PRINTF("INFO:%s: " _format "\n", dwc_irq(), ## _args)
++
++
++ ++

++Prints out an informative message. ++

++ ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
#define DWC_WARN (_format,
_args...   )    __DWC_WARN("WARN:%s:%s:%d: " _format "\n", dwc_irq(), __func__, __LINE__, ## _args)
++
++
++ ++

++Prints out a warning message. ++

++ ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
#define DWC_ERROR (_format,
_args...   )    __DWC_ERROR("ERROR:%s:%s:%d: " _format "\n", dwc_irq(), __func__, __LINE__, ## _args)
++
++
++ ++

++Prints out an error message. ++

++ ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
#define DWC_ASSERT (_expr,
_format,
_args...   )    if (!(_expr)) { DWC_EXCEPTION("%s:%s:%d: " _format "\n", dwc_irq(), __FILE__, __LINE__, ## _args); }
++
++
++ ++

++Prints out a exception error message if the _expr expression fails. ++

++Disabled if DEBUG is not enabled. ++

++

++

Typedef Documentation

++ ++
++
++ ++ ++ ++ ++
typedef uint8_t dwc_bool_t
++
++
++ ++

++We define a boolean type for consistency. ++

++Can be either YES or NO ++

++

++ ++

++
++ ++ ++ ++ ++
typedef int(*) dwc_waitq_condition_t(void *data)
++
++
++ ++

++The type of waitq condition callback function. ++

++This is called every time condition is evaluated. ++

++

++ ++

++
++ ++ ++ ++ ++
typedef int(*) dwc_thread_function_t(void *data)
++
++
++ ++

++The thread function. ++

++ ++

++

++ ++

++
++ ++ ++ ++ ++
typedef void(*) dwc_work_callback_t(void *data)
++
++
++ ++

++The type of the callback function to be called. ++

++ ++

++

++

Function Documentation

++ ++
++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
dwc_bool_t DWC_IN_IRQ (void   ) 
++
++
++ ++

++Returns non-zero if in interrupt context. ++

++ ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
static char* dwc_irq (void   )  [inline, static]
++
++
++ ++

++Returns "IRQ" if DWC_IN_IRQ is true. ++

++ ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void DWC_VPRINTF (char *  format,
va_list  args 
)
++
++
++ ++

++A vprintf() clone. ++

++Just call vprintf if you've got it. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int DWC_VSNPRINTF (char *  str,
int  size,
char *  format,
va_list  args 
)
++
++
++ ++

++A vsnprintf() clone. ++

++Just call vprintf if you've got it. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void DWC_PRINTF (char *  format,
  ... 
)
++
++
++ ++

++printf() clone. ++

++Just call printf if you've go it. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int DWC_SPRINTF (char *  string,
char *  format,
  ... 
)
++
++
++ ++

++sprintf() clone. ++

++Just call sprintf if you've got it. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int DWC_SNPRINTF (char *  string,
int  size,
char *  format,
  ... 
)
++
++
++ ++

++snprintf() clone. ++

++Just call snprintf if you've got it. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void __DWC_WARN (char *  format,
  ... 
)
++
++
++ ++

++Prints a WARNING message. ++

++On systems that don't differentiate between warnings and regular log messages, just print it. Indicates that something may be wrong with the driver. Works like printf().

++Use the DWC_WARN macro to call this function. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void __DWC_ERROR (char *  format,
  ... 
)
++
++
++ ++

++Prints an error message. ++

++On systems that don't differentiate between errors and regular log messages, just print it. Indicates that something went wrong with the driver, but it can be recovered from. Works like printf().

++Use the DWC_ERROR macro to call this function. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void DWC_EXCEPTION (char *  format,
  ... 
)
++
++
++ ++

++Prints an exception error message and takes some user-defined action such as print out a backtrace or trigger a breakpoint. ++

++Indicates that something went abnormally wrong with the driver such as programmer error, or other exceptional condition. It should not be ignored so even on systems without printing capability, some action should be taken to notify the developer of it. Works like printf(). ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void __DWC_DEBUG (char *  format,
  ... 
)
++
++
++ ++

++Prints out a debug message. ++

++Used for logging/trace messages.

++Use the DWC_DEBUG macro to call this function ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
uint32_t DWC_CPU_TO_LE32 (void *  p  ) 
++
++
++ ++

++Converts 32 bit data in CPU byte ordering to little endian. ++

++ ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
uint32_t DWC_CPU_TO_BE32 (void *  p  ) 
++
++
++ ++

++Converts 32 bit data in CPU byte orderint to big endian. ++

++ ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
uint32_t DWC_LE32_TO_CPU (void *  p  ) 
++
++
++ ++

++Converts 32 bit little endian data to CPU byte ordering. ++

++ ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
uint32_t DWC_BE32_TO_CPU (void *  p  ) 
++
++
++ ++

++Converts 32 bit big endian data to CPU byte ordering. ++

++ ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
uint16_t DWC_CPU_TO_LE16 (void *  p  ) 
++
++
++ ++

++Converts 16 bit data in CPU byte ordering to little endian. ++

++ ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
uint16_t DWC_CPU_TO_BE16 (void *  p  ) 
++
++
++ ++

++Converts 16 bit data in CPU byte orderint to big endian. ++

++ ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
uint16_t DWC_LE16_TO_CPU (void *  p  ) 
++
++
++ ++

++Converts 16 bit little endian data to CPU byte ordering. ++

++ ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
uint16_t DWC_BE16_TO_CPU (void *  p  ) 
++
++
++ ++

++Converts 16 bit bi endian data to CPU byte ordering. ++

++ ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
uint32_t DWC_READ_REG32 (uint32_t volatile *  reg  ) 
++
++
++ ++

++Reads the content of a 32-bit register. ++

++ ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
uint64_t DWC_READ_REG64 (uint64_t volatile *  reg  ) 
++
++
++ ++

++Reads the content of a 64-bit register. ++

++ ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void DWC_WRITE_REG32 (uint32_t volatile *  reg,
uint32_t  value 
)
++
++
++ ++

++Writes to a 32-bit register. ++

++ ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void DWC_WRITE_REG64 (uint64_t volatile *  reg,
uint64_t  value 
)
++
++
++ ++

++Writes to a 64-bit register. ++

++ ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void DWC_MODIFY_REG32 (uint32_t volatile *  reg,
uint32_t  clear_mask,
uint32_t  set_mask 
)
++
++
++ ++

++Modify bit values in a register. ++

++Using the algorithm: (reg_contents & ~clear_mask) | set_mask. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int DWC_AES_CBC (uint8_t *  message,
uint32_t  messagelen,
uint8_t *  key,
uint32_t  keylen,
uint8_t  iv[16],
uint8_t *  out 
)
++
++
++ ++

++Perform AES CBC. ++

++ ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void DWC_RANDOM_BYTES (uint8_t *  buffer,
uint32_t  length 
)
++
++
++ ++

++Fill the provided buffer with random bytes. ++

++These should be cryptographic grade random numbers. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int DWC_SHA256 (uint8_t *  message,
uint32_t  len,
uint8_t *  out 
)
++
++
++ ++

++Perform the SHA-256 hash function. ++

++ ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int DWC_HMAC_SHA256 (uint8_t *  message,
uint32_t  messagelen,
uint8_t *  key,
uint32_t  keylen,
uint8_t *  out 
)
++
++
++ ++

++Calculated the HMAC-SHA256. ++

++ ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void* __DWC_DMA_ALLOC (uint32_t  size,
dwc_dma_t *  dma_addr 
)
++
++
++ ++

++Allocates a DMA capable buffer and zeroes its contents. ++

++ ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void __DWC_DMA_FREE (uint32_t  size,
void *  virt_addr,
dwc_dma_t  dma_addr 
)
++
++
++ ++

++Frees a previosly allocated buffer. ++

++ ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void* __DWC_ALLOC (uint32_t  size  ) 
++
++
++ ++

++Allocates a block of memory and zeroes its contents. ++

++ ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void* __DWC_ALLOC_ATOMIC (uint32_t  size  ) 
++
++
++ ++

++Allocates a block of memory and zeroes its contents, in an atomic manner which can be used inside interrupt context. ++

++The size should be sufficiently small, a few KB at most, such that failures are not likely to occur. Can just call __DWC_ALLOC if it is atomic. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void __DWC_FREE (void *  addr  ) 
++
++
++ ++

++Frees a previously allocated buffer. ++

++ ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void* DWC_MEMSET (void *  dest,
uint8_t  byte,
uint32_t  size 
)
++
++
++ ++

++memset() clone ++

++ ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void* DWC_MEMCPY (void *  dest,
void const *  src,
uint32_t  size 
)
++
++
++ ++

++memcpy() clone ++

++ ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void* DWC_MEMMOVE (void *  dest,
void *  src,
uint32_t  size 
)
++
++
++ ++

++memmove() clone ++

++ ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int DWC_MEMCMP (void *  m1,
void *  m2,
uint32_t  size 
)
++
++
++ ++

++memcmp() clone ++

++ ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int DWC_STRCMP (void *  s1,
void *  s2 
)
++
++
++ ++

++strcmp() clone ++

++ ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int DWC_STRNCMP (void *  s1,
void *  s2,
uint32_t  size 
)
++
++
++ ++

++strncmp() clone ++

++ ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int DWC_STRLEN (char const *  str  ) 
++
++
++ ++

++strlen() clone, for NULL terminated ASCII strings ++

++ ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
char* DWC_STRCPY (char *  to,
const char *  from 
)
++
++
++ ++

++strcpy() clone, for NULL terminated ASCII strings ++

++ ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
char* DWC_STRDUP (char const *  str  ) 
++
++
++ ++

++strdup() clone. ++

++If you wish to use memory allocation debugging, this implementation of strdup should use the DWC_* memory routines instead of calling a predefined strdup. Otherwise the memory allocated by this routine will not be seen by the debugging routines. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int DWC_ATOI (char *  str,
int32_t *  value 
)
++
++
++ ++

++NOT an atoi() clone. ++

++Read the description carefully. Returns an integer converted from the string str in base 10 unless the string begins with a "0x" in which case it is base 16. String must be a NULL terminated sequence of ASCII characters and may optionally begin with whitespace, a + or -, and a "0x" prefix if base 16. The remaining characters must be valid digits for the number and end with a NULL character. If any invalid characters are encountered or it returns with a negative error code and the results of the conversion are undefined. On sucess it returns 0. Overflow conditions are undefined. An example implementation using atoi() can be referenced from the Linux implementation. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int DWC_ATOUI (char *  str,
uint32_t *  value 
)
++
++
++ ++

++Same as above but for unsigned. ++

++ ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int DWC_UTF8_TO_UTF16LE (uint8_t const *  utf8string,
uint16_t *  utf16string,
unsigned  len 
)
++
++
++ ++

++This routine returns a UTF16LE unicode encoded string from a UTF8 string. ++

++ ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
dwc_waitq_t* DWC_WAITQ_ALLOC (void   ) 
++
++
++ ++

++Allocate a waitq. ++

++ ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void DWC_WAITQ_FREE (dwc_waitq_t *  wq  ) 
++
++
++ ++

++Free a waitq. ++

++ ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int32_t DWC_WAITQ_WAIT (dwc_waitq_t *  wq,
dwc_waitq_condition_t  condition,
void *  data 
)
++
++
++ ++

++Check the condition and if it is false, block on the waitq. ++

++When unblocked, check the condition again. The function returns when the condition becomes true. The return value is 0 on condition true, DWC_WAITQ_ABORTED on abort or killed, or DWC_WAITQ_UNKNOWN on error. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int32_t DWC_WAITQ_WAIT_TIMEOUT (dwc_waitq_t *  wq,
dwc_waitq_condition_t  condition,
void *  data,
int32_t  msecs 
)
++
++
++ ++

++Check the condition and if it is false, block on the waitq. ++

++When unblocked, check the condition again. The function returns when the condition become true or the timeout has passed. The return value is 0 on condition true or DWC_TIMED_OUT on timeout, or DWC_WAITQ_ABORTED, or DWC_WAITQ_UNKNOWN on error. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void DWC_WAITQ_TRIGGER (dwc_waitq_t *  wq  ) 
++
++
++ ++

++Trigger a waitq, unblocking all processes. ++

++This should be called whenever a condition has potentially changed. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void DWC_WAITQ_ABORT (dwc_waitq_t *  wq  ) 
++
++
++ ++

++Unblock all processes waiting on the waitq with an ABORTED result. ++

++ ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
dwc_thread_t* DWC_THREAD_RUN (dwc_thread_function_t  thread_function,
char *  name,
void *  data 
)
++
++
++ ++

++Create a thread and start it running the thread_function. ++

++Returns a handle to the thread ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int DWC_THREAD_STOP (dwc_thread_t *  thread  ) 
++
++
++ ++

++Stops a thread. ++

++Return the value returned by the thread. Or will return DWC_ABORT if the thread never started. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
dwc_bool_t DWC_THREAD_SHOULD_STOP (void   ) 
++
++
++ ++

++Signifies to the thread that it must stop. ++

++ ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
dwc_workq_t* DWC_WORKQ_ALLOC (char *  name  ) 
++
++
++ ++

++Allocate a workq. ++

++ ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void DWC_WORKQ_FREE (dwc_workq_t *  workq  ) 
++
++
++ ++

++Free a workq. ++

++All work must be completed before being freed. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void DWC_WORKQ_SCHEDULE (dwc_workq_t *  workq,
dwc_work_callback_t  work_cb,
void *  data,
char *  format,
  ... 
)
++
++
++ ++

++Schedule a callback on the workq, passing in data. ++

++The function will be scheduled at some later time. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void DWC_WORKQ_SCHEDULE_DELAYED (dwc_workq_t *  workq,
dwc_work_callback_t  work_cb,
void *  data,
uint32_t  time,
char *  format,
  ... 
)
++
++
++ ++

++Schedule a callback on the workq, that will be called until at least given number miliseconds have passed. ++

++ ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int DWC_WORKQ_PENDING (dwc_workq_t *  workq  ) 
++
++
++ ++

++The number of processes in the workq. ++

++ ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int DWC_WORKQ_WAIT_WORK_DONE (dwc_workq_t *  workq,
int  timeout 
)
++
++
++ ++

++Blocks until all the work in the workq is complete or timed out. ++

++Returns < 0 on timeout. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void DWC_TIMER_SCHEDULE (dwc_timer_t *  timer,
uint32_t  time 
)
++
++
++ ++

++Schedules the timer to run at time ms from now. ++

++And will repeat at every repeat_interval msec therafter

++Modifies a timer that is still awaiting execution to a new expiration time. The mod_time is added to the old time. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void DWC_TIMER_CANCEL (dwc_timer_t *  timer  ) 
++
++
++ ++

++Disables the timer from execution. ++

++ ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
dwc_spinlock_t* DWC_SPINLOCK_ALLOC (void   ) 
++
++
++ ++

++Returns an initialized lock variable. ++

++This function should allocate and initialize the OS-specific data structure used for locking. This data structure is to be used for the DWC_LOCK and DWC_UNLOCK functions and should be freed by the DWC_FREE_LOCK when it is no longer used. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void DWC_SPINLOCK_FREE (dwc_spinlock_t *  lock  ) 
++
++
++ ++

++Frees an initialized lock variable. ++

++ ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void DWC_SPINLOCK_IRQSAVE (dwc_spinlock_t *  lock,
uint64_t *  flags 
)
++
++
++ ++

++Disables interrupts and blocks until it acquires the lock. ++

++

Parameters:
++ ++ ++ ++
lock Pointer to the spinlock.
flags Unsigned long for irq flags storage.
++
++ ++
++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void DWC_SPINUNLOCK_IRQRESTORE (dwc_spinlock_t *  lock,
uint64_t  flags 
)
++
++
++ ++

++Re-enables the interrupt and releases the lock. ++

++

Parameters:
++ ++ ++ ++
lock Pointer to the spinlock.
flags Unsigned long for irq flags storage. Must be the same as was passed into DWC_LOCK.
++
++ ++
++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void DWC_SPINLOCK (dwc_spinlock_t *  lock  ) 
++
++
++ ++

++Blocks until it acquires the lock. ++

++

Parameters:
++ ++ ++
lock Pointer to the spinlock.
++
++ ++
++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void DWC_SPINUNLOCK (dwc_spinlock_t *  lock  ) 
++
++
++ ++

++Releases the lock. ++

++

Parameters:
++ ++ ++
lock Pointer to the spinlock.
++
++ ++
++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int DWC_MUTEX_TRYLOCK (dwc_mutex_t *  mutex  ) 
++
++
++ ++

++Non-blocking lock returns 1 on successful lock. ++

++ ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void DWC_UDELAY (uint32_t  usecs  ) 
++
++
++ ++

++Microsecond delay. ++

++

Parameters:
++ ++ ++
usecs Microseconds to delay.
++
++ ++
++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void DWC_MDELAY (uint32_t  msecs  ) 
++
++
++ ++

++Millisecond delay. ++

++

Parameters:
++ ++ ++
msecs Milliseconds to delay.
++
++ ++
++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void DWC_MSLEEP (uint32_t  msecs  ) 
++
++
++ ++

++Non-busy waiting. ++

++Sleeps for specified number of milliseconds.

++

Parameters:
++ ++ ++
msecs Milliseconds to sleep.
++
++ ++
++

++

Generated on Tue May 5 02:22:50 2009 for Synopsys DWC Portability and Common Library for UWB by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_common_port/doc/html/files.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_common_port/doc/html/files.html 2013-07-26 19:31:19.000000000 +0000 +@@ -0,0 +1,34 @@ ++ ++ ++Synopsys DWC Portability and Common Library for UWB: File Index ++ ++ ++ ++ ++
++
++
++
++

Synopsys DWC Portability and Common Library for UWB File List

Here is a list of all documented files with brief descriptions: ++ ++ ++ ++ ++ ++ ++ ++ ++
dwc_cc.hThis file defines the Context Context library
dwc_crypto.cThis file contains the WUSB cryptographic routines
dwc_crypto.hThis file contains declarations for the WUSB Cryptographic routines as defined in the WUSB spec
dwc_dh.hThis file defines the common functions on device and host for performing numeric association as defined in the WUSB spec
dwc_list.hThis file defines linked list operations
dwc_modpow.hThis file defines the module exponentiation function which is only used internally by the DWC UWB modules for calculation of PKs during numeric association
dwc_notifier.hA simple implementation of the Observer pattern
dwc_os.hDWC portability library, low level os-wrapper functions
++
Generated on Tue May 5 02:22:50 2009 for Synopsys DWC Portability and Common Library for UWB by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_common_port/doc/html/globals.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_common_port/doc/html/globals.html 2013-07-26 19:31:19.000000000 +0000 +@@ -0,0 +1,163 @@ ++ ++ ++Synopsys DWC Portability and Common Library for UWB: Data Fields ++ ++ ++ ++ ++
++
++
++
++
++ ++
++
++
    ++
  • _
    • ++
  • d
    • ++
++
++ ++

++Here is a list of all documented functions, variables, defines, enums, and typedefs with links to the documentation: ++

++

- _ -

++

- d -

++
Generated on Tue May 5 02:22:50 2009 for Synopsys DWC Portability and Common Library for UWB by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_common_port/doc/html/globals_defs.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_common_port/doc/html/globals_defs.html 2013-07-26 19:31:19.000000000 +0000 +@@ -0,0 +1,41 @@ ++ ++ ++Synopsys DWC Portability and Common Library for UWB: Data Fields ++ ++ ++ ++ ++
++
++
++
++
++ ++
++  ++

++

++
Generated on Tue May 5 02:22:50 2009 for Synopsys DWC Portability and Common Library for UWB by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_common_port/doc/html/globals_func.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_common_port/doc/html/globals_func.html 2013-07-26 19:31:19.000000000 +0000 +@@ -0,0 +1,153 @@ ++ ++ ++Synopsys DWC Portability and Common Library for UWB: Data Fields ++ ++ ++ ++ ++
++
++
++
++
++ ++
++
++
    ++
  • _
    • ++
  • d
    • ++
++
++ ++

++  ++

++

- _ -

++

- d -

++
Generated on Tue May 5 02:22:50 2009 for Synopsys DWC Portability and Common Library for UWB by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_common_port/doc/html/globals_type.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_common_port/doc/html/globals_type.html 2013-07-26 19:31:19.000000000 +0000 +@@ -0,0 +1,41 @@ ++ ++ ++Synopsys DWC Portability and Common Library for UWB: Data Fields ++ ++ ++ ++ ++
++
++
++
++
++ ++
++  ++

++

++
Generated on Tue May 5 02:22:50 2009 for Synopsys DWC Portability and Common Library for UWB by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_common_port/doc/html/index.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_common_port/doc/html/index.html 2013-07-26 19:31:19.000000000 +0000 +@@ -0,0 +1,8 @@ ++ ++ ++Synopsys DWC Portability and Common Library for UWB ++ ++ ++ ++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_common_port/doc/html/main.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_common_port/doc/html/main.html 2013-07-26 19:31:19.000000000 +0000 +@@ -0,0 +1,45 @@ ++ ++ ++Synopsys DWC Portability and Common Library for UWB: DWC Portability and Common Library ++ ++ ++ ++ ++
++
++

DWC Portability and Common Library

++

++This is the documentation for the DWC Portability and Common Library.

++Introduction

++The DWC Portability library consists of wrapper calls and data structures to all low-level functions which are typically provided by the OS. The WUDEV driver uses only these functions. In order to port the WUDEV driver, only the functions in this library need to be re-implemented, with the same behavior as documented here.

++The Common library consists of higher level functions, which rely only on calling the functions from the DWC Portability library. These common routines are shared across modules. Some of the common libraries need to be used directly by the driver programmer when porting WUDEV. Such as the parameter and notification libraries.

++Portability Library OS Wrapper Functions

++Any function starting with DWC and in all CAPS is a low-level OS-wrapper that needs to be implemented when porting, for example DWC_MUTEX_ALLOC(). All of these functions are included in the dwc_os.h file.

++There are many functions here covering a wide array of OS services. Please see dwc_os.h for details, and implementation notes for each function.

++Common Library Functions

++Any function starting with dwc and in all lowercase is a common library routine. These functions have a portable implementation and do not need to be reimplemented when porting. The common routines can be used by any driver, and some must be used by the end user to control the drivers. For example, you must use the Parameter common library in order to set the parameters in the WUDEV module.

++The common libraries consist of the following:

++

    ++
  • Connection Contexts - Used internally and can be used by end-user. See dwc_cc.h
  • Parameters - Used internally and can be used by end-user. See dwc_params.h
  • Notifications - Used internally and can be used by end-user. See dwc_notifier.h
  • Lists - Used internally and can be used by end-user. See dwc_list.h
  • Memory Debugging - Used internally and can be used by end-user. See dwc_os.h
  • Modpow - Used internally only. See dwc_modpow.h
  • DH - Used internally only. See dwc_dh.h
  • Crypto - Used internally only. See dwc_crypto.h
++

++Prerequistes For dwc_os.h

++

++Data Types

++The dwc_os.h file assumes that several low-level data types are pre defined for the compilation environment. These data types are:

++

    ++
  • uint8_t - unsigned 8-bit data type
  • int8_t - signed 8-bit data type
  • uint16_t - unsigned 16-bit data type
  • int16_t - signed 16-bit data type
  • uint32_t - unsigned 32-bit data type
  • int32_t - signed 32-bit data type
  • uint64_t - unsigned 64-bit data type
  • int64_t - signed 64-bit data type
++

++Ensure that these are defined before using dwc_os.h. The easiest way to do that is to modify the top of the file to include the appropriate header. This is already done for the Linux environment. If the DWC_LINUX macro is defined, the correct header will be added. A standard header <stdint.h> is also used for environments where standard C headers are available.

++Variable Arguments

++Variable arguments are provided by a standard C header <stdarg.h>. it is available in Both the Linux and ANSI C enviornment. An equivalent must be provided in your enviornment in order to use dwc_os.h with the debug and tracing message functionality.

++Threading

++WUDEV Core must be run on an operating system that provides for multiple threads/processes. Threading can be implemented in many ways, even in embedded systems without an operating system. At the bare minimum, the system should be able to start any number of processes at any time to handle special work. It need not be a pre-emptive system. Process context can change upon a call to a blocking function. The hardware interrupt context that calls the module's ISR() function must be differentiable from process context, even if your processes are impemented via a hardware interrupt. Further locking mechanism between process must exist (or be implemented), and process context must have a way to disable interrupts for a period of time to lock them out. If all of this exists, the functions in dwc_os.h related to threading should be able to be implemented with the defined behavior.
Generated on Tue May 5 02:22:50 2009 for Synopsys DWC Portability and Common Library for UWB by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_common_port/doc/html/pages.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_common_port/doc/html/pages.html 2013-07-26 19:31:19.000000000 +0000 +@@ -0,0 +1,23 @@ ++ ++ ++Synopsys DWC Portability and Common Library for UWB: Page Index ++ ++ ++ ++ ++
++
++

Synopsys DWC Portability and Common Library for UWB Related Pages

Here is a list of all related documentation pages: ++
Generated on Tue May 5 02:22:50 2009 for Synopsys DWC Portability and Common Library for UWB by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_common_port/doc/html/tabs.css +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_common_port/doc/html/tabs.css 2013-07-26 19:31:19.000000000 +0000 +@@ -0,0 +1,102 @@ ++/* tabs styles, based on http://www.alistapart.com/articles/slidingdoors */ ++ ++DIV.tabs ++{ ++ float : left; ++ width : 100%; ++ background : url("tab_b.gif") repeat-x bottom; ++ margin-bottom : 4px; ++} ++ ++DIV.tabs UL ++{ ++ margin : 0px; ++ padding-left : 10px; ++ list-style : none; ++} ++ ++DIV.tabs LI, DIV.tabs FORM ++{ ++ display : inline; ++ margin : 0px; ++ padding : 0px; ++} ++ ++DIV.tabs FORM ++{ ++ float : right; ++} ++ ++DIV.tabs A ++{ ++ float : left; ++ background : url("tab_r.gif") no-repeat right top; ++ border-bottom : 1px solid #84B0C7; ++ font-size : x-small; ++ font-weight : bold; ++ text-decoration : none; ++} ++ ++DIV.tabs A:hover ++{ ++ background-position: 100% -150px; ++} ++ ++DIV.tabs A:link, DIV.tabs A:visited, ++DIV.tabs A:active, DIV.tabs A:hover ++{ ++ color: #1A419D; ++} ++ ++DIV.tabs SPAN ++{ ++ float : left; ++ display : block; ++ background : url("tab_l.gif") no-repeat left top; ++ padding : 5px 9px; ++ white-space : nowrap; ++} ++ ++DIV.tabs INPUT ++{ ++ float : right; ++ display : inline; ++ font-size : 1em; ++} ++ ++DIV.tabs TD ++{ ++ font-size : x-small; ++ font-weight : bold; ++ text-decoration : none; ++} ++ ++ ++ ++/* Commented Backslash Hack hides rule from IE5-Mac \*/ ++DIV.tabs SPAN {float : none;} ++/* End IE5-Mac hack */ ++ ++DIV.tabs A:hover SPAN ++{ ++ background-position: 0% -150px; ++} ++ ++DIV.tabs LI#current A ++{ ++ background-position: 100% -150px; ++ border-width : 0px; ++} ++ ++DIV.tabs LI#current SPAN ++{ ++ background-position: 0% -150px; ++ padding-bottom : 6px; ++} ++ ++DIV.nav ++{ ++ background : none; ++ border : none; ++ border-bottom : 1px solid #84B0C7; ++} +Index: linux-3.2.46/drivers/usb/host/dwc_common_port/doc/html/todo.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_common_port/doc/html/todo.html 2013-07-26 19:31:19.000000000 +0000 +@@ -0,0 +1,23 @@ ++ ++ ++Synopsys DWC Portability and Common Library for UWB: Todo List ++ ++ ++ ++ ++
++
++

Todo List

++
Global __DWC_DMA_ALLOC
++
these functions will be added in the future
++
++
Generated on Tue May 5 02:22:50 2009 for Synopsys DWC Portability and Common Library for UWB by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_common_port/doc/html/tree.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_common_port/doc/html/tree.html 2013-07-26 19:31:19.000000000 +0000 +@@ -0,0 +1,90 @@ ++ ++ ++ ++ ++ ++ ++ TreeView ++ ++ ++ ++ ++
++

Synopsys DWC Portability and Common Library for UWB

++ ++
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_common_port/dwc_cc.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_common_port/dwc_cc.c 2013-07-26 19:31:19.000000000 +0000 +@@ -0,0 +1,506 @@ ++/* ========================================================================= ++ * $File: //dwh/usb_iip/dev/software/dwc_common_port/dwc_cc.c $ ++ * $Revision: #1 $ ++ * $Date: 2008/12/21 $ ++ * $Change: 1156609 $ ++ * ++ * Synopsys Portability Library Software and documentation ++ * (hereinafter, "Software") is an Unsupported proprietary work of ++ * Synopsys, Inc. unless otherwise expressly agreed to in writing ++ * between Synopsys and you. ++ * ++ * The Software IS NOT an item of Licensed Software or Licensed Product ++ * under any End User Software License Agreement or Agreement for ++ * Licensed Product with Synopsys or any supplement thereto. You are ++ * permitted to use and redistribute this Software in source and binary ++ * forms, with or without modification, provided that redistributions ++ * of source code must retain this notice. You may not view, use, ++ * disclose, copy or distribute this file or any information contained ++ * herein except pursuant to this license grant from Synopsys. If you ++ * do not agree with this notice, including the disclaimer below, then ++ * you are not authorized to use the Software. ++ * ++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" ++ * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT ++ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ++ * FOR A PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL ++ * SYNOPSYS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, ++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, ++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR ++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY ++ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE ++ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH ++ * DAMAGE. ++ * ========================================================================= */ ++#include "dwc_cc.h" ++ ++typedef struct dwc_cc ++{ ++ uint32_t uid; ++ uint8_t chid[16]; ++ uint8_t cdid[16]; ++ uint8_t ck[16]; ++ uint8_t *name; ++ uint8_t length; ++ DWC_CIRCLEQ_ENTRY(dwc_cc) list_entry; ++} dwc_cc_t; ++ ++DWC_CIRCLEQ_HEAD(context_list, dwc_cc); ++ ++/** The main structure for CC management. */ ++struct dwc_cc_if ++{ ++ dwc_mutex_t *mutex; ++ char *filename; ++ ++ unsigned is_host:1; ++ ++ dwc_notifier_t *notifier; ++ ++ struct context_list list; ++}; ++ ++#ifdef DEBUG ++static inline void dump_bytes(char *name, uint8_t *bytes, int len) ++{ ++ int i; ++ DWC_PRINTF("%s: ", name); ++ for (i=0; ilength = length; ++ cc->name = DWC_ALLOC(length); ++ DWC_MEMCPY(cc->name, name, length); ++ } ++ ++ return cc; ++} ++ ++static void free_cc(dwc_cc_t *cc) ++{ ++ if (cc->name) { ++ DWC_FREE(cc->name); ++ } ++ DWC_FREE(cc); ++} ++ ++static uint32_t next_uid(dwc_cc_if_t *cc_if) ++{ ++ uint32_t uid = 0; ++ dwc_cc_t *cc; ++ DWC_CIRCLEQ_FOREACH(cc, &cc_if->list, list_entry) { ++ if (cc->uid > uid) { ++ uid = cc->uid; ++ } ++ } ++ ++ if (uid == 0) { ++ uid = 255; ++ } ++ ++ return uid + 1; ++} ++ ++static dwc_cc_t *cc_find(dwc_cc_if_t *cc_if, uint32_t uid) ++{ ++ dwc_cc_t *cc; ++ DWC_CIRCLEQ_FOREACH(cc, &cc_if->list, list_entry) { ++ if (cc->uid == uid) { ++ return cc; ++ } ++ } ++ return NULL; ++} ++ ++static unsigned int cc_data_size(dwc_cc_if_t *cc_if) ++{ ++ unsigned int size = 0; ++ dwc_cc_t *cc; ++ DWC_CIRCLEQ_FOREACH(cc, &cc_if->list, list_entry) { ++ size += (48 + 1); ++ if (cc->name) { ++ size += cc->length; ++ } ++ } ++ return size; ++} ++ ++static uint32_t cc_match_chid(dwc_cc_if_t *cc_if, uint8_t *chid) ++{ ++ uint32_t uid = 0; ++ dwc_cc_t *cc; ++ ++ DWC_CIRCLEQ_FOREACH(cc, &cc_if->list, list_entry) { ++ if (DWC_MEMCMP(cc->chid, chid, 16) == 0) { ++ uid = cc->uid; ++ break; ++ } ++ } ++ return uid; ++} ++static uint32_t cc_match_cdid(dwc_cc_if_t *cc_if, uint8_t *cdid) ++{ ++ uint32_t uid = 0; ++ dwc_cc_t *cc; ++ ++ DWC_CIRCLEQ_FOREACH(cc, &cc_if->list, list_entry) { ++ if (DWC_MEMCMP(cc->cdid, cdid, 16) == 0) { ++ uid = cc->uid; ++ break; ++ } ++ } ++ return uid; ++} ++ ++/* Internal cc_add */ ++static int32_t cc_add(dwc_cc_if_t *cc_if, uint8_t *chid, uint8_t *cdid, uint8_t *ck, uint8_t *name, uint8_t length) ++{ ++ dwc_cc_t *cc; ++ uint32_t uid; ++ ++ if (cc_if->is_host) { ++ uid = cc_match_cdid(cc_if, cdid); ++ } ++ else { ++ uid = cc_match_chid(cc_if, chid); ++ } ++ ++ if (uid) { ++ DWC_DEBUG("Replacing previous connection context id=%d name=%p name_len=%d", uid, name, length); ++ cc = cc_find(cc_if, uid); ++ } ++ else { ++ cc = alloc_cc(name, length); ++ cc->uid = next_uid(cc_if); ++ DWC_CIRCLEQ_INSERT_TAIL(&cc_if->list, cc, list_entry); ++ } ++ ++ DWC_MEMCPY(&(cc->chid[0]), chid, 16); ++ DWC_MEMCPY(&(cc->cdid[0]), cdid, 16); ++ DWC_MEMCPY(&(cc->ck[0]), ck, 16); ++ ++ DWC_DEBUG("Added connection context id=%d name=%p name_len=%d", cc->uid, name, length); ++ dump_bytes("CHID", cc->chid, 16); ++ dump_bytes("CDID", cc->cdid, 16); ++ dump_bytes("CK", cc->ck, 16); ++ return cc->uid; ++} ++ ++/* Internal cc_clear */ ++static void cc_clear(dwc_cc_if_t *cc_if) ++{ ++ while (!DWC_CIRCLEQ_EMPTY(&cc_if->list)) { ++ dwc_cc_t *cc = DWC_CIRCLEQ_FIRST(&cc_if->list); ++ DWC_CIRCLEQ_REMOVE_INIT(&cc_if->list, cc, list_entry); ++ free_cc(cc); ++ } ++} ++ ++dwc_cc_if_t *dwc_cc_if_alloc(dwc_notifier_t *notifier, unsigned is_host) ++{ ++ dwc_cc_if_t *cc_if = NULL; ++ ++ /* Allocate a common_cc_if structure */ ++ cc_if = DWC_ALLOC(sizeof(dwc_cc_if_t)); ++ ++ if(!cc_if) ++ return NULL; ++ ++#if (defined(DWC_LINUX) && defined(CONFIG_DEBUG_MUTEXES)) ++ DWC_MUTEX_ALLOC_LINUX_DEBUG(cc_if->mutex); ++#else ++ cc_if->mutex = DWC_MUTEX_ALLOC(); ++#endif ++ DWC_CIRCLEQ_INIT(&cc_if->list); ++ cc_if->is_host = is_host; ++ cc_if->notifier = notifier; ++ return cc_if; ++} ++ ++void dwc_cc_if_free(dwc_cc_if_t *cc_if) ++{ ++ DWC_MUTEX_FREE(cc_if->mutex); ++ cc_clear(cc_if); ++ DWC_FREE(cc_if); ++} ++ ++static void cc_changed(dwc_cc_if_t *cc_if) ++{ ++ if (cc_if->notifier) { ++ dwc_notify(cc_if->notifier, DWC_CC_LIST_CHANGED_NOTIFICATION, cc_if); ++ } ++} ++ ++void dwc_cc_clear(dwc_cc_if_t *cc_if) ++{ ++ DWC_MUTEX_LOCK(cc_if->mutex); ++ cc_clear(cc_if); ++ DWC_MUTEX_UNLOCK(cc_if->mutex); ++ cc_changed(cc_if); ++} ++ ++int32_t dwc_cc_add(dwc_cc_if_t *cc_if, uint8_t *chid, uint8_t *cdid, uint8_t *ck, uint8_t *name, uint8_t length) ++{ ++ uint32_t uid; ++ ++ DWC_MUTEX_LOCK(cc_if->mutex); ++ uid = cc_add(cc_if, chid, cdid, ck, name, length); ++ DWC_MUTEX_UNLOCK(cc_if->mutex); ++ cc_changed(cc_if); ++ ++ return uid; ++} ++ ++void dwc_cc_change(dwc_cc_if_t *cc_if, int32_t id, ++ uint8_t *chid, uint8_t *cdid, uint8_t *ck, uint8_t *name, uint8_t length) ++{ ++ dwc_cc_t* cc; ++ ++ DWC_DEBUG("Change connection context %d", id); ++ ++ DWC_MUTEX_LOCK(cc_if->mutex); ++ cc = cc_find(cc_if, id); ++ if (!cc) { ++ DWC_ERROR("Uid %d not found in cc list", id); ++ DWC_MUTEX_UNLOCK(cc_if->mutex); ++ return; ++ } ++ ++ if (chid) { ++ DWC_MEMCPY(&(cc->chid[0]), chid, 16); ++ } ++ if (cdid) { ++ DWC_MEMCPY(&(cc->cdid[0]), cdid, 16); ++ } ++ if (ck) { ++ DWC_MEMCPY(&(cc->ck[0]), ck, 16); ++ } ++ ++ if (name) { ++ if (cc->name) { ++ DWC_FREE(cc->name); ++ } ++ cc->name = DWC_ALLOC(length); ++ cc->length = length; ++ DWC_MEMCPY(cc->name, name, length); ++ } ++ ++ DWC_MUTEX_UNLOCK(cc_if->mutex); ++ ++ cc_changed(cc_if); ++ ++ DWC_DEBUG("Changed connection context id=%d\n", id); ++ dump_bytes("New CHID", cc->chid, 16); ++ dump_bytes("New CDID", cc->cdid, 16); ++ dump_bytes("New CK", cc->ck, 16); ++} ++ ++void dwc_cc_remove(dwc_cc_if_t *cc_if, int32_t id) ++{ ++ dwc_cc_t *cc; ++ ++ DWC_DEBUG("Removing connection context %d", id); ++ ++ DWC_MUTEX_LOCK(cc_if->mutex); ++ cc = cc_find(cc_if, id); ++ if (!cc) { ++ DWC_ERROR("Uid %d not found in cc list", id); ++ DWC_MUTEX_UNLOCK(cc_if->mutex); ++ return; ++ } ++ ++ DWC_CIRCLEQ_REMOVE_INIT(&cc_if->list, cc, list_entry); ++ DWC_MUTEX_UNLOCK(cc_if->mutex); ++ free_cc(cc); ++ ++ cc_changed(cc_if); ++} ++ ++uint8_t *dwc_cc_data_for_save(dwc_cc_if_t *cc_if, unsigned int *length) ++{ ++ uint8_t *buf, *x; ++ uint8_t zero = 0; ++ dwc_cc_t *cc; ++ ++ DWC_MUTEX_LOCK(cc_if->mutex); ++ *length = cc_data_size(cc_if); ++ if (!(*length)) { ++ DWC_MUTEX_UNLOCK(cc_if->mutex); ++ return NULL; ++ } ++ ++ DWC_DEBUG("Creating data for saving (length=%d)", *length); ++ ++ buf = DWC_ALLOC(*length); ++ if (!buf) { ++ *length = 0; ++ DWC_MUTEX_UNLOCK(cc_if->mutex); ++ return NULL; ++ } ++ ++ x = buf; ++ DWC_CIRCLEQ_FOREACH(cc, &cc_if->list, list_entry) { ++ DWC_MEMCPY(x, cc->chid, 16); ++ x += 16; ++ DWC_MEMCPY(x, cc->cdid, 16); ++ x += 16; ++ DWC_MEMCPY(x, cc->ck, 16); ++ x += 16; ++ if (cc->name) { ++ DWC_MEMCPY(x, &cc->length, 1); ++ x += 1; ++ DWC_MEMCPY(x, cc->name, cc->length); ++ x += cc->length; ++ } ++ else { ++ DWC_MEMCPY(x, &zero, 1); ++ x += 1; ++ } ++ } ++ DWC_MUTEX_UNLOCK(cc_if->mutex); ++ ++ return buf; ++} ++ ++void dwc_cc_restore_from_data(dwc_cc_if_t *cc_if, uint8_t *data, uint32_t length) ++{ ++ uint8_t name_length; ++ uint8_t *name; ++ uint8_t *chid; ++ uint8_t *cdid; ++ uint8_t *ck; ++ uint32_t i = 0; ++ ++ DWC_MUTEX_LOCK(cc_if->mutex); ++ cc_clear(cc_if); ++ ++ while (i < length) { ++ chid = &data[i]; ++ i += 16; ++ cdid = &data[i]; ++ i += 16; ++ ck = &data[i]; ++ i += 16; ++ ++ name_length = data[i]; ++ i ++; ++ ++ if (name_length) { ++ name = &data[i]; ++ i += name_length; ++ } ++ else { ++ name = NULL; ++ } ++ ++ /* check to see if we haven't overflown the buffer */ ++ if (i > length) { ++ DWC_ERROR("Data format error while attempting to load CCs " ++ "(nlen=%d, iter=%d, buflen=%d).", name_length, i, length); ++ break; ++ } ++ ++ cc_add(cc_if, chid, cdid, ck, name, name_length); ++ } ++ DWC_MUTEX_UNLOCK(cc_if->mutex); ++ ++ cc_changed(cc_if); ++} ++ ++uint32_t dwc_cc_match_chid(dwc_cc_if_t *cc_if, uint8_t *chid) ++{ ++ uint32_t uid = 0; ++ ++ DWC_MUTEX_LOCK(cc_if->mutex); ++ uid = cc_match_chid(cc_if, chid); ++ DWC_MUTEX_UNLOCK(cc_if->mutex); ++ return uid; ++} ++uint32_t dwc_cc_match_cdid(dwc_cc_if_t *cc_if, uint8_t *cdid) ++{ ++ uint32_t uid = 0; ++ ++ DWC_MUTEX_LOCK(cc_if->mutex); ++ uid = cc_match_cdid(cc_if, cdid); ++ DWC_MUTEX_UNLOCK(cc_if->mutex); ++ return uid; ++} ++ ++uint8_t *dwc_cc_ck(dwc_cc_if_t *cc_if, int32_t id) ++{ ++ uint8_t *ck = NULL; ++ dwc_cc_t *cc; ++ ++ DWC_MUTEX_LOCK(cc_if->mutex); ++ cc = cc_find(cc_if, id); ++ if (cc) { ++ ck = cc->ck; ++ } ++ DWC_MUTEX_UNLOCK(cc_if->mutex); ++ ++ return ck; ++ ++} ++ ++uint8_t *dwc_cc_chid(dwc_cc_if_t *cc_if, int32_t id) ++{ ++ uint8_t *retval = NULL; ++ dwc_cc_t *cc; ++ ++ DWC_MUTEX_LOCK(cc_if->mutex); ++ cc = cc_find(cc_if, id); ++ if (cc) { ++ retval = cc->chid; ++ } ++ DWC_MUTEX_UNLOCK(cc_if->mutex); ++ ++ return retval; ++} ++ ++uint8_t *dwc_cc_cdid(dwc_cc_if_t *cc_if, int32_t id) ++{ ++ uint8_t *retval = NULL; ++ dwc_cc_t *cc; ++ ++ DWC_MUTEX_LOCK(cc_if->mutex); ++ cc = cc_find(cc_if, id); ++ if (cc) { ++ retval = cc->cdid; ++ } ++ DWC_MUTEX_UNLOCK(cc_if->mutex); ++ ++ return retval; ++} ++ ++uint8_t *dwc_cc_name(dwc_cc_if_t *cc_if, int32_t id, uint8_t *length) ++{ ++ uint8_t *retval = NULL; ++ dwc_cc_t *cc; ++ ++ DWC_MUTEX_LOCK(cc_if->mutex); ++ *length = 0; ++ cc = cc_find(cc_if, id); ++ if (cc) { ++ *length = cc->length; ++ retval = cc->name; ++ } ++ DWC_MUTEX_UNLOCK(cc_if->mutex); ++ ++ return retval; ++} +Index: linux-3.2.46/drivers/usb/host/dwc_common_port/dwc_cc.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_common_port/dwc_cc.h 2013-07-26 19:31:19.000000000 +0000 +@@ -0,0 +1,209 @@ ++/* ========================================================================= ++ * $File: //dwh/usb_iip/dev/software/dwc_common_port/dwc_cc.h $ ++ * $Revision: #1 $ ++ * $Date: 2008/12/21 $ ++ * $Change: 1156609 $ ++ * ++ * Synopsys Portability Library Software and documentation ++ * (hereinafter, "Software") is an Unsupported proprietary work of ++ * Synopsys, Inc. unless otherwise expressly agreed to in writing ++ * between Synopsys and you. ++ * ++ * The Software IS NOT an item of Licensed Software or Licensed Product ++ * under any End User Software License Agreement or Agreement for ++ * Licensed Product with Synopsys or any supplement thereto. You are ++ * permitted to use and redistribute this Software in source and binary ++ * forms, with or without modification, provided that redistributions ++ * of source code must retain this notice. You may not view, use, ++ * disclose, copy or distribute this file or any information contained ++ * herein except pursuant to this license grant from Synopsys. If you ++ * do not agree with this notice, including the disclaimer below, then ++ * you are not authorized to use the Software. ++ * ++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" ++ * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT ++ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ++ * FOR A PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL ++ * SYNOPSYS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, ++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, ++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR ++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY ++ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE ++ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH ++ * DAMAGE. ++ * ========================================================================= */ ++#ifndef _DWC_CC_H_ ++#define _DWC_CC_H_ ++ ++/** @file ++ * ++ * This file defines the Context Context library. ++ * ++ * The main data structure is dwc_cc_if_t which is returned by either the ++ * dwc_cc_if_alloc function or returned by the module to the user via a provided ++ * function. The data structure is opaque and should only be manipulated via the ++ * functions provied in this API. ++ * ++ * It manages a list of connection contexts and operations can be performed to ++ * add, remove, query, search, and change, those contexts. Additionally, ++ * a dwc_notifier_t object can be requested from the manager so that ++ * the user can be notified whenever the context list has changed. ++ */ ++ ++#include "dwc_os.h" ++#include "dwc_list.h" ++#include "dwc_notifier.h" ++ ++ ++/* Notifications */ ++#define DWC_CC_LIST_CHANGED_NOTIFICATION "DWC_CC_LIST_CHANGED_NOTIFICATION" ++ ++struct dwc_cc_if; ++typedef struct dwc_cc_if dwc_cc_if_t; ++ ++ ++/** @name Connection Context Operations */ ++/** @{ */ ++ ++/** This function allocates memory for a dwc_cc_if_t structure, initializes ++ * fields to default values, and returns a pointer to the structure or NULL on ++ * error. */ ++extern dwc_cc_if_t *dwc_cc_if_alloc(dwc_notifier_t *notifier, unsigned is_host); ++ ++/** Frees the memory for the specified CC structure allocated from ++ * dwc_cc_if_alloc(). */ ++extern void dwc_cc_if_free(dwc_cc_if_t *cc_if); ++ ++/** Removes all contexts from the connection context list */ ++extern void dwc_cc_clear(dwc_cc_if_t *cc_if); ++ ++/** Adds a connection context (CHID, CK, CDID, Name) to the connection context list. ++ * If a CHID already exists, the CK and name are overwritten. Statistics are ++ * not overwritten. ++ * ++ * @param cc_if The cc_if structure. ++ * @param chid A pointer to the 16-byte CHID. This value will be copied. ++ * @param ck A pointer to the 16-byte CK. This value will be copied. ++ * @param cdid A pointer to the 16-byte CDID. This value will be copied. ++ * @param name An optional host friendly name as defined in the association model ++ * spec. Must be a UTF16-LE unicode string. Can be NULL to indicated no name. ++ * @param length The length othe unicode string. ++ * @return A unique identifier used to refer to this context that is valid for ++ * as long as this context is still in the list. */ ++extern int32_t dwc_cc_add(dwc_cc_if_t *cc_if, uint8_t *chid, uint8_t *cdid, uint8_t *ck, uint8_t *name, uint8_t length); ++ ++/** Changes the CHID, CK, CDID, or Name values of a connection context in the ++ * list, preserving any accumulated statistics. This would typically be called ++ * if the host decideds to change the context with a SET_CONNECTION request. ++ * ++ * @param cc_if The cc_if structure. ++ * @param id The identifier of the connection context. ++ * @param chid A pointer to the 16-byte CHID. This value will be copied. NULL ++ * indicates no change. ++ * @param cdid A pointer to the 16-byte CDID. This value will be copied. NULL ++ * indicates no change. ++ * @param ck A pointer to the 16-byte CK. This value will be copied. NULL ++ * indicates no change. ++ * @param name Host friendly name UTF16-LE. NULL indicates no change. ++ * @param length Length of name. */ ++extern void dwc_cc_change(dwc_cc_if_t *cc_if, int32_t id, uint8_t *chid, uint8_t *cdid, uint8_t *ck, uint8_t *name, uint8_t length); ++ ++/** Remove the specified connection context. ++ * @param cc_if The cc_if structure. ++ * @param id The identifier of the connection context to remove. */ ++extern void dwc_cc_remove(dwc_cc_if_t *cc_if, int32_t id); ++ ++/** Get a binary block of data for the connection context list and attributes. ++ * This data can be used by the OS specific driver to save the connection ++ * context list into non-volatile memory. ++ * ++ * @param cc_if The cc_if structure. ++ * @param length Return the length of the data buffer. ++ * @return A pointer to the data buffer. The memory for this buffer should be freed with DWC_FREE() after use. */ ++extern uint8_t *dwc_cc_data_for_save(dwc_cc_if_t *cc_if, unsigned int *length); ++ ++/** Restore the connection context list from the binary data that was previously ++ * returned from a call to dwc_cc_data_for_save. This can be used by the OS specific ++ * driver to load a connection context list from non-volatile memory. ++ * ++ * @param cc_if The cc_if structure. ++ * @param data The data bytes as returned from dwc_cc_data_for_save. ++ * @param length The length of the data. */ ++extern void dwc_cc_restore_from_data(dwc_cc_if_t *cc_if, uint8_t *data, unsigned int length); ++ ++/** Find the connection context from the specified CHID. ++ * ++ * @param cc_if The cc_if structure. ++ * @param chid A pointer to the CHID data. ++ * @return A non-zero identifier of the connection context if the CHID matches. ++ * Otherwise returns 0. */ ++extern uint32_t dwc_cc_match_chid(dwc_cc_if_t *cc_if, uint8_t *chid); ++ ++/** Find the connection context from the specified CDID. ++ * ++ * @param cc_if The cc_if structure. ++ * @param cdid A pointer to the CDID data. ++ * @return A non-zero identifier of the connection context if the CHID matches. ++ * Otherwise returns 0. */ ++extern uint32_t dwc_cc_match_cdid(dwc_cc_if_t *cc_if, uint8_t *cdid); ++ ++/** Retrieve the CK from the specified connection context. ++ * ++ * @param cc_if The cc_if structure. ++ * @param id The identifier of the connection context. ++ * @return A pointer to the CK data. The memory does not need to be freed. */ ++extern uint8_t *dwc_cc_ck(dwc_cc_if_t *cc_if, int32_t id); ++ ++/** Retrieve the CHID from the specified connection context. ++ * ++ * @param cc_if The cc_if structure. ++ * @param id The identifier of the connection context. ++ * @return A pointer to the CHID data. The memory does not need to be freed. */ ++extern uint8_t *dwc_cc_chid(dwc_cc_if_t *cc_if, int32_t id); ++ ++/** Retrieve the CDID from the specified connection context. ++ * ++ * @param cc_if The cc_if structure. ++ * @param id The identifier of the connection context. ++ * @return A pointer to the CDID data. The memory does not need to be freed. */ ++extern uint8_t *dwc_cc_cdid(dwc_cc_if_t *cc_if, int32_t id); ++ ++extern uint8_t *dwc_cc_name(dwc_cc_if_t *cc_if, int32_t id, uint8_t *length); ++ ++/** Checks a buffer for non-zero. ++ * @param id A pointer to a 16 byte buffer. ++ * @return true if the 16 byte value is non-zero. */ ++static inline unsigned dwc_assoc_is_not_zero_id(uint8_t *id) { ++ int i; ++ for (i=0; i<16; i++) { ++ if (id[i]) return 1; ++ } ++ return 0; ++} ++ ++/** Checks a buffer for zero. ++ * @param id A pointer to a 16 byte buffer. ++ * @return true if the 16 byte value is zero. */ ++static inline unsigned dwc_assoc_is_zero_id(uint8_t *id) { ++ return !dwc_assoc_is_not_zero_id(id); ++} ++ ++/** Prints an ASCII representation for the 16-byte chid, cdid, or ck, into ++ * buffer. */ ++static inline int dwc_print_id_string(char *buffer, uint8_t *id) { ++ char *ptr = buffer; ++ int i; ++ for (i=0; i<16; i++) { ++ ptr += DWC_SPRINTF(ptr, "%02x", id[i]); ++ if (i < 15) { ++ ptr += DWC_SPRINTF(ptr, " "); ++ } ++ } ++ return ptr - buffer; ++} ++ ++/** @} */ ++ ++#endif /* _DWC_CC_H_ */ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_common_port/dwc_common_linux.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_common_port/dwc_common_linux.c 2013-07-26 19:31:19.000000000 +0000 +@@ -0,0 +1,1247 @@ ++#include "dwc_cc.h" ++#include "dwc_modpow.h" ++#include "dwc_dh.h" ++#include "dwc_crypto.h" ++#include "dwc_notifier.h" ++ ++#include ++#include ++#include ++#include ++ ++MODULE_DESCRIPTION("DWC Common Library - Portable version"); ++MODULE_AUTHOR("Synopsys Inc."); ++MODULE_LICENSE ("GPL"); ++ ++static int dwc_common_port_init_module(void) ++{ ++ printk( KERN_DEBUG "Module dwc_common_port init\n" ); ++#ifdef DEBUG_MEMORY ++ dwc_memory_debug_start(); ++#endif ++ dwc_alloc_notification_manager(); ++ return 0; ++} ++ ++static void dwc_common_port_exit_module(void) ++{ ++ printk( KERN_DEBUG "Module dwc_common_port exit\n" ); ++ dwc_free_notification_manager(); ++#ifdef DEBUG_MEMORY ++ dwc_memory_debug_stop(); ++#endif ++} ++ ++module_init(dwc_common_port_init_module); ++module_exit(dwc_common_port_exit_module); ++ ++/* CC */ ++EXPORT_SYMBOL(dwc_cc_if_alloc); ++EXPORT_SYMBOL(dwc_cc_if_free); ++EXPORT_SYMBOL(dwc_cc_clear); ++EXPORT_SYMBOL(dwc_cc_add); ++EXPORT_SYMBOL(dwc_cc_remove); ++EXPORT_SYMBOL(dwc_cc_change); ++EXPORT_SYMBOL(dwc_cc_data_for_save); ++EXPORT_SYMBOL(dwc_cc_restore_from_data); ++EXPORT_SYMBOL(dwc_cc_match_chid); ++EXPORT_SYMBOL(dwc_cc_match_cdid); ++EXPORT_SYMBOL(dwc_cc_ck); ++EXPORT_SYMBOL(dwc_cc_chid); ++EXPORT_SYMBOL(dwc_cc_cdid); ++EXPORT_SYMBOL(dwc_cc_name); ++ ++#ifndef CONFIG_MACH_IPMATE ++/* Modpow */ ++EXPORT_SYMBOL(dwc_modpow); ++/* DH */ ++EXPORT_SYMBOL(dwc_dh_modpow); ++EXPORT_SYMBOL(dwc_dh_derive_keys); ++EXPORT_SYMBOL(dwc_dh_pk); ++#endif /* CONFIG_MACH_IPMATE */ ++/* Crypto */ ++EXPORT_SYMBOL(dwc_wusb_aes_encrypt); ++EXPORT_SYMBOL(dwc_wusb_cmf); ++EXPORT_SYMBOL(dwc_wusb_prf); ++EXPORT_SYMBOL(dwc_wusb_fill_ccm_nonce); ++EXPORT_SYMBOL(dwc_wusb_gen_nonce); ++EXPORT_SYMBOL(dwc_wusb_gen_key); ++EXPORT_SYMBOL(dwc_wusb_gen_mic); ++ ++ ++/* Notification */ ++EXPORT_SYMBOL(dwc_alloc_notification_manager); ++EXPORT_SYMBOL(dwc_free_notification_manager); ++EXPORT_SYMBOL(dwc_register_notifier); ++EXPORT_SYMBOL(dwc_unregister_notifier); ++EXPORT_SYMBOL(dwc_add_observer); ++EXPORT_SYMBOL(dwc_remove_observer); ++EXPORT_SYMBOL(dwc_notify); ++ ++/* Memory Debugging Routines */ ++#ifdef DEBUG_MEMORY ++EXPORT_SYMBOL(dwc_alloc_debug); ++EXPORT_SYMBOL(dwc_alloc_atomic_debug); ++EXPORT_SYMBOL(dwc_free_debug); ++EXPORT_SYMBOL(dwc_dma_alloc_debug); ++EXPORT_SYMBOL(dwc_dma_alloc_atomic_debug); ++EXPORT_SYMBOL(dwc_dma_free_debug); ++#endif ++ ++/* OS-Level Implementations */ ++ ++/* This is the Linux kernel implementation of the DWC platform library. */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30)) ++#include ++#else ++#include ++#endif ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++/* MISC */ ++ ++void *DWC_MEMSET(void *dest, uint8_t byte, uint32_t size) ++{ ++ return memset(dest, byte, size); ++} ++EXPORT_SYMBOL(DWC_MEMSET); ++ ++void *DWC_MEMCPY(void *dest, void const *src, uint32_t size) ++{ ++ return memcpy(dest, src, size); ++} ++EXPORT_SYMBOL(DWC_MEMCPY); ++ ++void *DWC_MEMMOVE(void *dest, void *src, uint32_t size) ++{ ++ return memmove(dest, src, size); ++} ++EXPORT_SYMBOL(DWC_MEMMOVE); ++ ++int DWC_MEMCMP(void *m1, void *m2, uint32_t size) ++{ ++ return memcmp(m1, m2, size); ++} ++EXPORT_SYMBOL(DWC_MEMCMP); ++ ++int DWC_STRNCMP(void *s1, void *s2, uint32_t size) ++{ ++ return strncmp(s1, s2, size); ++} ++EXPORT_SYMBOL(DWC_STRNCMP); ++ ++int DWC_STRCMP(void *s1, void *s2) ++{ ++ return strcmp(s1, s2); ++} ++EXPORT_SYMBOL(DWC_STRCMP); ++ ++int DWC_STRLEN(char const *str) ++{ ++ return strlen(str); ++} ++EXPORT_SYMBOL(DWC_STRLEN); ++ ++char *DWC_STRCPY(char *to, const char *from) ++{ ++ return strcpy(to, from); ++} ++EXPORT_SYMBOL(DWC_STRCPY); ++ ++char *DWC_STRDUP(char const *str) ++{ ++ int len = DWC_STRLEN(str) + 1; ++ char *new = DWC_ALLOC_ATOMIC(len); ++ if (!new) { ++ return NULL; ++ } ++ DWC_MEMCPY(new, str, len); ++ return new; ++} ++EXPORT_SYMBOL(DWC_STRDUP); ++ ++int DWC_ATOI(char *str, int32_t *value) ++{ ++ char *end = NULL; ++ *value = simple_strtol(str, &end, 0); ++ if (*end == '\0') { ++ return 0; ++ } ++ return -1; ++} ++EXPORT_SYMBOL(DWC_ATOI); ++ ++int DWC_ATOUI(char *str, uint32_t *value) ++{ ++ char *end = NULL; ++ *value = simple_strtoul(str, &end, 0); ++ if (*end == '\0') { ++ return 0; ++ } ++ return -1; ++} ++EXPORT_SYMBOL(DWC_ATOUI); ++ ++ ++/* From usbstring.c */ ++int DWC_UTF8_TO_UTF16LE(uint8_t const *s, uint16_t *cp, unsigned len) ++{ ++ int count = 0; ++ u8 c; ++ u16 uchar; ++ ++ /* this insists on correct encodings, though not minimal ones. ++ * BUT it currently rejects legit 4-byte UTF-8 code points, ++ * which need surrogate pairs. (Unicode 3.1 can use them.) ++ */ ++ while (len != 0 && (c = (u8) *s++) != 0) { ++ if (unlikely(c & 0x80)) { ++ // 2-byte sequence: ++ // 00000yyyyyxxxxxx = 110yyyyy 10xxxxxx ++ if ((c & 0xe0) == 0xc0) { ++ uchar = (c & 0x1f) << 6; ++ ++ c = (u8) *s++; ++ if ((c & 0xc0) != 0xc0) ++ goto fail; ++ c &= 0x3f; ++ uchar |= c; ++ ++ // 3-byte sequence (most CJKV characters): ++ // zzzzyyyyyyxxxxxx = 1110zzzz 10yyyyyy 10xxxxxx ++ } else if ((c & 0xf0) == 0xe0) { ++ uchar = (c & 0x0f) << 12; ++ ++ c = (u8) *s++; ++ if ((c & 0xc0) != 0xc0) ++ goto fail; ++ c &= 0x3f; ++ uchar |= c << 6; ++ ++ c = (u8) *s++; ++ if ((c & 0xc0) != 0xc0) ++ goto fail; ++ c &= 0x3f; ++ uchar |= c; ++ ++ /* no bogus surrogates */ ++ if (0xd800 <= uchar && uchar <= 0xdfff) ++ goto fail; ++ ++ // 4-byte sequence (surrogate pairs, currently rare): ++ // 11101110wwwwzzzzyy + 110111yyyyxxxxxx ++ // = 11110uuu 10uuzzzz 10yyyyyy 10xxxxxx ++ // (uuuuu = wwww + 1) ++ // FIXME accept the surrogate code points (only) ++ ++ } else ++ goto fail; ++ } else ++ uchar = c; ++ put_unaligned (cpu_to_le16 (uchar), cp++); ++ count++; ++ len--; ++ } ++ return count; ++fail: ++ return -1; ++} ++EXPORT_SYMBOL(DWC_UTF8_TO_UTF16LE); ++ ++/* dwc_debug.h */ ++ ++dwc_bool_t DWC_IN_IRQ(void) ++{ ++ return in_irq(); ++} ++EXPORT_SYMBOL(DWC_IN_IRQ); ++ ++int DWC_IN_BH(void) ++{ ++ return in_softirq(); ++} ++EXPORT_SYMBOL(DWC_IN_BH); ++ ++void DWC_VPRINTF(char *format, va_list args) ++{ ++ vprintk(format, args); ++} ++EXPORT_SYMBOL(DWC_VPRINTF); ++ ++int DWC_VSNPRINTF(char *str, int size, char *format, va_list args) ++{ ++ return vsnprintf(str, size, format, args); ++} ++ ++void DWC_PRINTF(char *format, ...) ++{ ++ va_list args; ++ va_start(args, format); ++ DWC_VPRINTF(format, args); ++ va_end(args); ++} ++EXPORT_SYMBOL(DWC_PRINTF); ++ ++int DWC_SPRINTF(char *buffer, char *format, ...) ++{ ++ int retval; ++ va_list args; ++ va_start(args, format); ++ retval = vsprintf(buffer, format, args); ++ va_end(args); ++ return retval; ++} ++EXPORT_SYMBOL(DWC_SPRINTF); ++ ++int DWC_SNPRINTF(char *buffer, int size, char *format, ...) ++{ ++ int retval; ++ va_list args; ++ va_start(args, format); ++ retval = vsnprintf(buffer, size, format, args); ++ va_end(args); ++ return retval; ++} ++EXPORT_SYMBOL(DWC_SNPRINTF); ++ ++void __DWC_WARN(char *format, ...) ++{ ++ va_list args; ++ va_start(args, format); ++ DWC_PRINTF(KERN_WARNING); ++ DWC_VPRINTF(format, args); ++ va_end(args); ++} ++EXPORT_SYMBOL(__DWC_WARN); ++ ++void __DWC_ERROR(char *format, ...) ++{ ++ va_list args; ++ va_start(args, format); ++ DWC_PRINTF(KERN_ERR); ++ DWC_VPRINTF(format, args); ++ va_end(args); ++} ++EXPORT_SYMBOL(__DWC_ERROR); ++ ++void DWC_EXCEPTION(char *format, ...) ++{ ++ va_list args; ++ va_start(args, format); ++ DWC_PRINTF(KERN_ERR); ++ DWC_VPRINTF(format, args); ++ va_end(args); ++ BUG_ON(1); ++} ++EXPORT_SYMBOL(DWC_EXCEPTION); ++ ++#ifdef DEBUG ++void __DWC_DEBUG(char *format, ...) ++{ ++ va_list args; ++ va_start(args, format); ++ DWC_PRINTF(KERN_DEBUG); ++ DWC_VPRINTF(format, args); ++ va_end(args); ++} ++EXPORT_SYMBOL(__DWC_DEBUG); ++#endif ++ ++ ++ ++/* dwc_mem.h */ ++ ++#if 0 ++dwc_pool_t *DWC_DMA_POOL_CREATE(uint32_t size, ++ uint32_t align, ++ uint32_t alloc) ++{ ++ struct dma_pool *pool = dma_pool_create("Pool", NULL, ++ size, align, alloc); ++ return (dwc_pool_t *)pool; ++} ++ ++void DWC_DMA_POOL_DESTROY(dwc_pool_t *pool) ++{ ++ dma_pool_destroy((struct dma_pool *)pool); ++} ++ ++void *DWC_DMA_POOL_ALLOC(dwc_pool_t *pool, U64 *dma_addr) ++{ ++ return dma_pool_alloc((struct dma_pool *)pool, GFP_KERNEL, dma_addr); ++} ++ ++void *DWC_DMA_POOL_ZALLOC(dwc_pool_t *pool, U64 *dma_addr) ++{ ++ void *vaddr = DWC_DMA_POOL_ALLOC(pool, dma_addr); ++ memset(); ++} ++ ++void DWC_DMA_POOL_FREE(dwc_pool_t *pool, void *vaddr, void *daddr) ++{ ++ dma_pool_free(pool, vaddr, daddr); ++} ++ ++#endif ++ ++void *__DWC_DMA_ALLOC(uint32_t size, dwc_dma_t *dma_addr) ++{ ++ void *buf = dma_alloc_coherent(NULL, (size_t)size, dma_addr, GFP_KERNEL); ++ if (!buf) { ++ return NULL; ++ } ++ memset(buf, 0, (size_t)size); ++ return buf; ++} ++EXPORT_SYMBOL(__DWC_DMA_ALLOC); ++ ++void __DWC_DMA_FREE(uint32_t size, void *virt_addr, dwc_dma_t dma_addr) ++{ ++ dma_free_coherent(NULL, size, virt_addr, dma_addr); ++} ++EXPORT_SYMBOL(__DWC_DMA_FREE); ++ ++void *__DWC_DMA_ALLOC_ATOMIC(uint32_t size, dwc_dma_t *dma_addr) ++{ ++ void *buf = dma_alloc_coherent(NULL, (size_t)size, dma_addr, GFP_ATOMIC); ++ if (!buf) { ++ return NULL; ++ } ++ memset(buf, 0, (size_t)size); ++ return buf; ++} ++EXPORT_SYMBOL(__DWC_DMA_ALLOC_ATOMIC); ++ ++void *__DWC_ALLOC(uint32_t size) ++{ ++ return kzalloc(size, GFP_KERNEL); ++} ++EXPORT_SYMBOL(__DWC_ALLOC); ++ ++void *__DWC_ALLOC_ATOMIC(uint32_t size) ++{ ++ return kzalloc(size, GFP_ATOMIC); ++} ++EXPORT_SYMBOL(__DWC_ALLOC_ATOMIC); ++ ++void __DWC_FREE(void *addr) ++{ ++ kfree(addr); ++} ++EXPORT_SYMBOL(__DWC_FREE); ++ ++/* dwc_crypto.h */ ++ ++void DWC_RANDOM_BYTES(uint8_t *buffer, uint32_t length) ++{ ++ get_random_bytes(buffer, length); ++} ++EXPORT_SYMBOL(DWC_RANDOM_BYTES); ++ ++int DWC_AES_CBC(uint8_t *message, uint32_t messagelen, uint8_t *key, uint32_t keylen, uint8_t iv[16], uint8_t *out) ++{ ++ struct crypto_blkcipher *tfm; ++ struct blkcipher_desc desc; ++ struct scatterlist sgd; ++ struct scatterlist sgs; ++ ++ tfm = crypto_alloc_blkcipher("cbc(aes)", 0, CRYPTO_ALG_ASYNC); ++ if (tfm == NULL) { ++ printk("failed to load transform for aes CBC\n"); ++ return -1; ++ } ++ ++ crypto_blkcipher_setkey(tfm, key, keylen); ++ crypto_blkcipher_set_iv(tfm, iv, 16); ++ ++ sg_init_one(&sgd, out, messagelen); ++ sg_init_one(&sgs, message, messagelen); ++ ++ desc.tfm = tfm; ++ desc.flags = 0; ++ ++ if(crypto_blkcipher_encrypt(&desc, &sgd, &sgs, messagelen)) { ++ crypto_free_blkcipher(tfm); ++ DWC_ERROR("AES CBC encryption failed"); ++ return -1; ++ } ++ ++ crypto_free_blkcipher(tfm); ++ return 0; ++} ++EXPORT_SYMBOL(DWC_AES_CBC); ++ ++int DWC_SHA256(uint8_t *message, uint32_t len, uint8_t *out) ++{ ++ struct crypto_hash *tfm; ++ struct hash_desc desc; ++ struct scatterlist sg; ++ ++ tfm = crypto_alloc_hash("sha256", 0, CRYPTO_ALG_ASYNC); ++ if (IS_ERR(tfm)) { ++ DWC_ERROR("Failed to load transform for sha256: %ld\n", PTR_ERR(tfm)); ++ return 0; ++ } ++ desc.tfm = tfm; ++ desc.flags = 0; ++ ++ sg_init_one(&sg, message, len); ++ crypto_hash_digest(&desc, &sg, len, out); ++ crypto_free_hash(tfm); ++ ++ return 1; ++} ++EXPORT_SYMBOL(DWC_SHA256); ++ ++int DWC_HMAC_SHA256(uint8_t *message, uint32_t messagelen, ++ uint8_t *key, uint32_t keylen, uint8_t *out) ++{ ++ struct crypto_hash *tfm; ++ struct hash_desc desc; ++ struct scatterlist sg; ++ ++ tfm = crypto_alloc_hash("hmac(sha256)", 0, CRYPTO_ALG_ASYNC); ++ if (IS_ERR(tfm)) { ++ DWC_ERROR("Failed to load transform for hmac(sha256): %ld\n", PTR_ERR(tfm)); ++ return 0; ++ } ++ desc.tfm = tfm; ++ desc.flags = 0; ++ ++ sg_init_one(&sg, message, messagelen); ++ crypto_hash_setkey(tfm, key, keylen); ++ crypto_hash_digest(&desc, &sg, messagelen, out); ++ crypto_free_hash(tfm); ++ ++ return 1; ++} ++EXPORT_SYMBOL(DWC_HMAC_SHA256); ++ ++/* Byte Ordering Conversions. */ ++uint32_t DWC_CPU_TO_LE32(void *p) ++{ ++#ifdef __LITTLE_ENDIAN ++ return *((uint32_t *)p); ++#else ++ uint8_t *u_p = (uint8_t *)p; ++ ++ return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24)); ++#endif ++} ++EXPORT_SYMBOL(DWC_CPU_TO_LE32); ++ ++uint32_t DWC_CPU_TO_BE32(void *p) ++{ ++#ifdef __BIG_ENDIAN ++ return *((uint32_t *)p); ++#else ++ uint8_t *u_p = (uint8_t *)p; ++ ++ return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24)); ++#endif ++} ++EXPORT_SYMBOL(DWC_CPU_TO_BE32); ++ ++uint32_t DWC_LE32_TO_CPU(void *p) ++{ ++#ifdef __LITTLE_ENDIAN ++ return *((uint32_t *)p); ++#else ++ uint8_t *u_p = (uint8_t *)p; ++ ++ return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24)); ++ ++#endif ++} ++EXPORT_SYMBOL(DWC_LE32_TO_CPU); ++ ++uint32_t DWC_BE32_TO_CPU(void *p) ++{ ++#ifdef __BIG_ENDIAN ++ return *((uint32_t *)p); ++#else ++ uint8_t *u_p = (uint8_t *)p; ++ ++ return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24)); ++#endif ++} ++EXPORT_SYMBOL(DWC_BE32_TO_CPU); ++ ++uint16_t DWC_CPU_TO_LE16(void *p) ++{ ++#ifdef __LITTLE_ENDIAN ++ return *((uint16_t *)p); ++#else ++ uint8_t *u_p = (uint8_t *)p; ++ return (u_p[1] | (u_p[0] << 8)); ++#endif ++} ++EXPORT_SYMBOL(DWC_CPU_TO_LE16); ++ ++uint16_t DWC_CPU_TO_BE16(void *p) ++{ ++#ifdef __BIG_ENDIAN ++ return *((uint16_t *)p); ++#else ++ uint8_t *u_p = (uint8_t *)p; ++ return (u_p[1] | (u_p[0] << 8)); ++#endif ++} ++EXPORT_SYMBOL(DWC_CPU_TO_BE16); ++ ++uint16_t DWC_LE16_TO_CPU(void *p) ++{ ++#ifdef __LITTLE_ENDIAN ++ return *((uint16_t *)p); ++#else ++ uint8_t *u_p = (uint8_t *)p; ++ return (u_p[1] | (u_p[0] << 8)); ++#endif ++} ++EXPORT_SYMBOL(DWC_LE16_TO_CPU); ++ ++uint16_t DWC_BE16_TO_CPU(void *p) ++{ ++#ifdef __BIG_ENDIAN ++ return *((uint16_t *p)p); ++#else ++ uint8_t *u_p = (uint8_t *)p; ++ return (u_p[1] | (u_p[0] << 8)); ++#endif ++} ++EXPORT_SYMBOL(DWC_BE16_TO_CPU); ++ ++ ++/* Registers */ ++ ++uint32_t DWC_READ_REG32(uint32_t volatile *reg) ++{ ++ return readl(reg); ++} ++EXPORT_SYMBOL(DWC_READ_REG32); ++ ++#if 0 ++uint64_t DWC_READ_REG64(uint64_t volatile *reg) ++{ ++} ++#endif ++ ++void DWC_WRITE_REG32(uint32_t volatile *reg, uint32_t value) ++{ ++ writel(value, reg); ++} ++EXPORT_SYMBOL(DWC_WRITE_REG32); ++ ++#if 0 ++void DWC_WRITE_REG64(uint64_t volatile *reg, uint64_t value) ++{ ++} ++#endif ++ ++void DWC_MODIFY_REG32(uint32_t volatile *reg, uint32_t clear_mask, uint32_t set_mask) ++{ ++ writel( (readl(reg) & ~clear_mask) | set_mask, reg ); ++} ++EXPORT_SYMBOL(DWC_MODIFY_REG32); ++ ++#if 0 ++void DWC_MODIFY_REG64(uint64_t volatile *reg, uint64_t value) ++{ ++} ++#endif ++ ++ ++ ++/* Threading */ ++ ++typedef struct work_container ++{ ++ dwc_work_callback_t cb; ++ void *data; ++ dwc_workq_t *wq; ++ char *name; ++ ++#ifdef DEBUG ++ DWC_CIRCLEQ_ENTRY(work_container) entry; ++#endif ++ ++ struct delayed_work work; ++} work_container_t; ++ ++#ifdef DEBUG ++DWC_CIRCLEQ_HEAD(work_container_queue, work_container); ++#endif ++ ++struct dwc_workq ++{ ++ struct workqueue_struct *wq; ++ int pending; ++ dwc_spinlock_t *lock; ++ dwc_waitq_t *waitq; ++ ++#ifdef DEBUG ++ struct work_container_queue entries; ++#endif ++}; ++ ++static void do_work(struct work_struct *work) ++{ ++ int64_t flags; ++ struct delayed_work *dw = container_of(work, struct delayed_work, work); ++ work_container_t *container = container_of(dw, struct work_container, work); ++ dwc_workq_t *wq = container->wq; ++ ++ container->cb(container->data); ++ ++#ifdef DEBUG ++ DWC_CIRCLEQ_REMOVE(&wq->entries, container, entry); ++#endif ++ ++ if (container->name) { ++ DWC_DEBUG("Work done: %s, container=%p", ++ container->name, container); //GRAYG ++ DWC_FREE(container->name); ++ } ++ DWC_FREE(container); ++ ++ DWC_SPINLOCK_IRQSAVE(wq->lock, &flags); ++ wq->pending --; ++ DWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags); ++ DWC_WAITQ_TRIGGER(wq->waitq); ++} ++ ++static int work_done(void *data) ++{ ++ dwc_workq_t *workq = (dwc_workq_t *)data; ++ return workq->pending == 0; ++} ++ ++int DWC_WORKQ_WAIT_WORK_DONE(dwc_workq_t *workq, int timeout) ++{ ++ return DWC_WAITQ_WAIT_TIMEOUT(workq->waitq, work_done, workq, timeout); ++} ++EXPORT_SYMBOL(DWC_WORKQ_WAIT_WORK_DONE); ++ ++dwc_workq_t *DWC_WORKQ_ALLOC(char *name) ++{ ++ dwc_workq_t *wq = DWC_ALLOC(sizeof(*wq)); ++ wq->wq = create_singlethread_workqueue(name); ++ wq->pending = 0; ++ wq->lock = DWC_SPINLOCK_ALLOC(); ++ wq->waitq = DWC_WAITQ_ALLOC(); ++#ifdef DEBUG ++ DWC_CIRCLEQ_INIT(&wq->entries); ++#endif ++ return wq; ++} ++EXPORT_SYMBOL(DWC_WORKQ_ALLOC); ++ ++void DWC_WORKQ_FREE(dwc_workq_t *wq) ++{ ++#ifdef DEBUG ++ if (wq->pending != 0) { ++ struct work_container *wc; ++ DWC_ERROR("Destroying work queue with pending work"); ++ DWC_CIRCLEQ_FOREACH(wc, &wq->entries, entry) { ++ DWC_ERROR("Work %s still pending", wc->name); ++ } ++ } ++#endif ++ destroy_workqueue((struct workqueue_struct *)wq->wq); ++ DWC_SPINLOCK_FREE(wq->lock); ++ DWC_WAITQ_FREE(wq->waitq); ++ DWC_FREE(wq); ++} ++EXPORT_SYMBOL(DWC_WORKQ_FREE); ++ ++void DWC_WORKQ_SCHEDULE(dwc_workq_t *wq, dwc_work_callback_t work_cb, void *data, char *format, ...) ++{ ++ int64_t flags; ++ work_container_t *container; ++ static char name[128]; ++ ++ va_list args; ++ va_start(args, format); ++ if (format) ++ DWC_VSNPRINTF(name, 128, format, args); ++ va_end(args); ++ ++ DWC_SPINLOCK_IRQSAVE(wq->lock, &flags); ++ wq->pending ++; ++ DWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags); ++ DWC_WAITQ_TRIGGER(wq->waitq); ++ ++ container = DWC_ALLOC_ATOMIC(sizeof(*container)); ++ ++ container->data = data; ++ container->cb = work_cb; ++ container->wq = wq; ++ if (format) { ++ container->name = DWC_STRDUP(name); ++ DWC_DEBUG("Queueing work: %s, contianer=%p", ++ container->name, container); ++ } else ++ container->name = NULL; ++ ++ INIT_WORK(&container->work.work, do_work); ++ ++#ifdef DEBUG ++ DWC_CIRCLEQ_INSERT_TAIL(&wq->entries, container, entry); ++#endif ++ ++ queue_work(wq->wq, &container->work.work); ++ ++} ++EXPORT_SYMBOL(DWC_WORKQ_SCHEDULE); ++ ++void DWC_WORKQ_SCHEDULE_DELAYED(dwc_workq_t *wq, dwc_work_callback_t work_cb, void *data, uint32_t time, char *format, ...) ++{ ++ int64_t flags; ++ work_container_t *container; ++ static char name[128]; ++ ++ va_list args; ++ va_start(args, format); ++ if (format) ++ DWC_VSNPRINTF(name, 128, format, args); ++ va_end(args); ++ ++ DWC_SPINLOCK_IRQSAVE(wq->lock, &flags); ++ wq->pending ++; ++ DWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags); ++ DWC_WAITQ_TRIGGER(wq->waitq); ++ ++ container = DWC_ALLOC_ATOMIC(sizeof(*container)); ++ ++ container->data = data; ++ container->cb = work_cb; ++ container->wq = wq; ++ if (format) { //GRAYG ++ container->name = DWC_STRDUP(name); ++ DWC_DEBUG("Queueing work: %s, contianer=%p", ++ container->name, container); ++ } else ++ container->name = NULL; ++ INIT_DELAYED_WORK(&container->work, do_work); ++ ++#ifdef DEBUG ++ DWC_CIRCLEQ_INSERT_TAIL(&wq->entries, container, entry); ++#endif ++ ++ queue_delayed_work(wq->wq, &container->work, msecs_to_jiffies(time)); ++ ++} ++EXPORT_SYMBOL(DWC_WORKQ_SCHEDULE_DELAYED); ++ ++ ++int DWC_WORKQ_PENDING(dwc_workq_t *wq) ++{ ++ return wq->pending; ++} ++EXPORT_SYMBOL(DWC_WORKQ_PENDING); ++ ++dwc_spinlock_t *DWC_SPINLOCK_ALLOC(void) ++{ ++ spinlock_t *sl = (spinlock_t *)1; ++#if defined(CONFIG_PREEMPT) || defined(CONFIG_SMP) ++ sl = DWC_ALLOC(sizeof(*sl)); ++ spin_lock_init(sl); ++#endif ++ return (dwc_spinlock_t *)sl; ++} ++EXPORT_SYMBOL(DWC_SPINLOCK_ALLOC); ++ ++void DWC_SPINLOCK_FREE(dwc_spinlock_t *lock) ++{ ++#if defined(CONFIG_PREEMPT) || defined(CONFIG_SMP) ++ DWC_FREE(lock); ++#endif ++} ++EXPORT_SYMBOL(DWC_SPINLOCK_FREE); ++ ++void DWC_SPINLOCK(dwc_spinlock_t *lock) ++{ ++#if defined(CONFIG_PREEMPT) || defined(CONFIG_SMP) ++ spin_lock((spinlock_t *)lock); ++#endif ++} ++EXPORT_SYMBOL(DWC_SPINLOCK); ++ ++void DWC_SPINUNLOCK(dwc_spinlock_t *lock) ++{ ++#if defined(CONFIG_PREEMPT) || defined(CONFIG_SMP) ++ spin_unlock((spinlock_t *)lock); ++#endif ++} ++EXPORT_SYMBOL(DWC_SPINUNLOCK); ++ ++void DWC_SPINLOCK_IRQSAVE(dwc_spinlock_t *lock, uint64_t *flags) ++{ ++ unsigned long f; ++#if defined(CONFIG_PREEMPT) || defined(CONFIG_SMP) ++ spin_lock_irqsave((spinlock_t *)lock, f); ++#else ++ local_irq_save(f); ++#endif ++ *flags = f; ++} ++EXPORT_SYMBOL(DWC_SPINLOCK_IRQSAVE); ++ ++void DWC_SPINUNLOCK_IRQRESTORE(dwc_spinlock_t *lock, uint64_t flags) ++{ ++#if defined(CONFIG_PREEMPT) || defined(CONFIG_SMP) ++ spin_unlock_irqrestore((spinlock_t *)lock, flags); ++#else ++ // in kernel 2.6.31, at least, we check for unsigned long ++ local_irq_restore((unsigned long)flags); ++#endif ++} ++EXPORT_SYMBOL(DWC_SPINUNLOCK_IRQRESTORE); ++ ++dwc_mutex_t *DWC_MUTEX_ALLOC(void) ++{ ++ dwc_mutex_t *mutex = (dwc_mutex_t*)DWC_ALLOC(sizeof(struct mutex)); ++ struct mutex *m = (struct mutex *)mutex; ++ mutex_init(m); ++ return mutex; ++} ++EXPORT_SYMBOL(DWC_MUTEX_ALLOC); ++ ++#if (defined(DWC_LINUX) && defined(CONFIG_DEBUG_MUTEXES)) ++#else ++void DWC_MUTEX_FREE(dwc_mutex_t *mutex) ++{ ++ mutex_destroy((struct mutex *)mutex); ++ DWC_FREE(mutex); ++} ++EXPORT_SYMBOL(DWC_MUTEX_FREE); ++#endif ++ ++void DWC_MUTEX_LOCK(dwc_mutex_t *mutex) ++{ ++ struct mutex *m = (struct mutex *)mutex; ++ mutex_lock(m); ++} ++EXPORT_SYMBOL(DWC_MUTEX_LOCK); ++ ++int DWC_MUTEX_TRYLOCK(dwc_mutex_t *mutex) ++{ ++ struct mutex *m = (struct mutex *)mutex; ++ return mutex_trylock(m); ++} ++EXPORT_SYMBOL(DWC_MUTEX_TRYLOCK); ++ ++void DWC_MUTEX_UNLOCK(dwc_mutex_t *mutex) ++{ ++ struct mutex *m = (struct mutex *)mutex; ++ mutex_unlock(m); ++} ++EXPORT_SYMBOL(DWC_MUTEX_UNLOCK); ++ ++dwc_thread_t *DWC_THREAD_RUN(dwc_thread_function_t thread_function, char *name, void *data) ++{ ++ struct task_struct *thread = kthread_run(thread_function, data, name); ++ if (thread == ERR_PTR(-ENOMEM)) { ++ return NULL; ++ } ++ return (dwc_thread_t *)thread; ++} ++EXPORT_SYMBOL(DWC_THREAD_RUN); ++ ++int DWC_THREAD_STOP(dwc_thread_t *thread) ++{ ++ return kthread_stop((struct task_struct *)thread); ++} ++EXPORT_SYMBOL(DWC_THREAD_STOP); ++ ++dwc_bool_t DWC_THREAD_SHOULD_STOP() ++{ ++ return kthread_should_stop(); ++} ++EXPORT_SYMBOL(DWC_THREAD_SHOULD_STOP); ++ ++/* Timers */ ++ ++struct dwc_timer ++{ ++ struct timer_list *t; ++ char *name; ++ dwc_timer_callback_t cb; ++ void *data; ++ uint8_t scheduled; ++ dwc_spinlock_t *lock; ++}; ++ ++static void set_scheduled(dwc_timer_t *t, int s) ++{ ++ uint64_t flags; ++ DWC_SPINLOCK_IRQSAVE(t->lock, &flags); ++ t->scheduled = s; ++ DWC_SPINUNLOCK_IRQRESTORE(t->lock, flags); ++} ++ ++static int get_scheduled(dwc_timer_t *t) ++{ ++ int s; ++ uint64_t flags; ++ DWC_SPINLOCK_IRQSAVE(t->lock, &flags); ++ s = t->scheduled; ++ DWC_SPINUNLOCK_IRQRESTORE(t->lock, flags); ++ return s; ++} ++ ++static void timer_callback(unsigned long data) ++{ ++ dwc_timer_t *timer = (dwc_timer_t *)data; ++ set_scheduled(timer, 0); ++ DWC_DEBUG("Timer %s callback", timer->name); ++ timer->cb(timer->data); ++} ++ ++dwc_timer_t *DWC_TIMER_ALLOC(char *name, dwc_timer_callback_t cb, void *data) ++{ ++ dwc_timer_t *t = DWC_ALLOC(sizeof(*t)); ++ if (!t) { ++ DWC_ERROR("Cannot allocate memory for timer"); ++ return NULL; ++ } ++ t->t = DWC_ALLOC(sizeof(*t->t)); ++ if (!t->t) { ++ DWC_ERROR("Cannot allocate memory for timer->t"); ++ goto no_timer; ++ } ++ ++ t->name = DWC_STRDUP(name); ++ if (!t->name) { ++ DWC_ERROR("Cannot allocate memory for timer->name"); ++ goto no_name; ++ } ++ ++ t->lock = DWC_SPINLOCK_ALLOC(); ++ if (!t->lock) { ++ DWC_ERROR("Cannot allocate memory for lock"); ++ goto no_lock; ++ } ++ t->scheduled = 0; ++ t->t->base = &boot_tvec_bases; ++ t->t->expires = jiffies; ++ setup_timer(t->t, timer_callback, (unsigned long)t); ++ ++ t->cb = cb; ++ t->data = data; ++ ++ return t; ++ ++ no_lock: ++ DWC_FREE(t->name); ++ no_name: ++ DWC_FREE(t->t); ++ no_timer: ++ DWC_FREE(t); ++ return NULL; ++} ++EXPORT_SYMBOL(DWC_TIMER_ALLOC); ++ ++void DWC_TIMER_FREE(dwc_timer_t *timer) ++{ ++ if (get_scheduled(timer)) { ++ del_timer(timer->t); ++ } ++ ++ DWC_SPINLOCK_FREE(timer->lock); ++ DWC_FREE(timer->t); ++ DWC_FREE(timer->name); ++ DWC_FREE(timer); ++} ++EXPORT_SYMBOL(DWC_TIMER_FREE); ++ ++void DWC_TIMER_SCHEDULE(dwc_timer_t *timer, uint32_t time) ++{ ++ if (!get_scheduled(timer)) { ++ set_scheduled(timer, 1); ++ //cgg: DWC_DEBUG("Scheduling timer %s to expire in +%d msec", timer->name, time); ++ timer->t->expires = jiffies + msecs_to_jiffies(time); ++ add_timer(timer->t); ++ } ++ else { ++ //cgg: DWC_DEBUG("Modifying timer %s to expire in +%d msec", timer->name, time); ++ mod_timer(timer->t, jiffies + msecs_to_jiffies(time)); ++ } ++} ++EXPORT_SYMBOL(DWC_TIMER_SCHEDULE); ++ ++void DWC_TIMER_CANCEL(dwc_timer_t *timer) ++{ ++ del_timer(timer->t); ++} ++EXPORT_SYMBOL(DWC_TIMER_CANCEL); ++ ++struct dwc_tasklet ++{ ++ struct tasklet_struct t; ++ dwc_tasklet_callback_t cb; ++ void *data; ++}; ++ ++static void tasklet_callback(unsigned long data) ++{ ++ dwc_tasklet_t *t = (dwc_tasklet_t *)data; ++ t->cb(t->data); ++} ++ ++dwc_tasklet_t *DWC_TASK_ALLOC(dwc_tasklet_callback_t cb, void *data) ++{ ++ dwc_tasklet_t *t = DWC_ALLOC(sizeof(*t)); ++ ++ if(t) { ++ t->data = data; ++ t->cb = cb; ++ tasklet_init(&t->t, tasklet_callback, (unsigned long)t); ++ } else { ++ DWC_ERROR("Cannot allocate memory for tasklet\n"); ++ } ++ ++ return t; ++} ++EXPORT_SYMBOL(DWC_TASK_ALLOC); ++ ++void DWC_TASK_FREE(dwc_tasklet_t *t) ++{ ++ DWC_FREE(t); ++} ++EXPORT_SYMBOL(DWC_TASK_FREE); ++ ++void DWC_TASK_SCHEDULE(dwc_tasklet_t *task) ++{ ++ tasklet_schedule(&task->t); ++} ++EXPORT_SYMBOL(DWC_TASK_SCHEDULE); ++ ++/* Timing */ ++ ++void DWC_UDELAY(uint32_t usecs) ++{ ++ udelay(usecs); ++} ++EXPORT_SYMBOL(DWC_UDELAY); ++ ++void DWC_MDELAY(uint32_t msecs) ++{ ++ mdelay(msecs); ++} ++EXPORT_SYMBOL(DWC_MDELAY); ++ ++void DWC_MSLEEP(uint32_t msecs) ++{ ++ msleep(msecs); ++} ++EXPORT_SYMBOL(DWC_MSLEEP); ++ ++uint32_t DWC_TIME(void) ++{ ++ return jiffies_to_msecs(jiffies); ++} ++EXPORT_SYMBOL(DWC_TIME); ++ ++ ++/* Wait Queues */ ++ ++struct dwc_waitq ++{ ++ wait_queue_head_t queue; ++ int abort; ++}; ++ ++dwc_waitq_t *DWC_WAITQ_ALLOC(void) ++{ ++ dwc_waitq_t *wq = DWC_ALLOC(sizeof(*wq)); ++ init_waitqueue_head(&wq->queue); ++ wq->abort = 0; ++ return wq; ++} ++EXPORT_SYMBOL(DWC_WAITQ_ALLOC); ++ ++void DWC_WAITQ_FREE(dwc_waitq_t *wq) ++{ ++ DWC_FREE(wq); ++} ++EXPORT_SYMBOL(DWC_WAITQ_FREE); ++ ++static int32_t check_result(dwc_waitq_t *wq, int result) ++{ int32_t msecs; ++ if (result > 0) { ++ msecs = jiffies_to_msecs(result); ++ if (!msecs) { ++ return 1; ++ } ++ return msecs; ++ } ++ ++ if (result == 0) { ++ return -DWC_E_TIMEOUT; ++ } ++ ++ if ((result == -ERESTARTSYS) || (wq->abort == 1)) { ++ return -DWC_E_ABORT; ++ } ++ ++ return -DWC_E_UNKNOWN; ++} ++ ++int32_t DWC_WAITQ_WAIT(dwc_waitq_t *wq, dwc_waitq_condition_t condition, void *data) ++{ ++ int result = wait_event_interruptible(wq->queue, ++ condition(data) || wq->abort); ++ return check_result(wq, result); ++} ++EXPORT_SYMBOL(DWC_WAITQ_WAIT); ++ ++int32_t DWC_WAITQ_WAIT_TIMEOUT(dwc_waitq_t *wq, dwc_waitq_condition_t condition, ++ void *data, int32_t msecs) ++{ ++ int result = wait_event_interruptible_timeout(wq->queue, ++ condition(data) || wq->abort, ++ msecs_to_jiffies(msecs)); ++ return check_result(wq, result); ++} ++EXPORT_SYMBOL(DWC_WAITQ_WAIT_TIMEOUT); ++ ++void DWC_WAITQ_TRIGGER(dwc_waitq_t *wq) ++{ ++ wake_up_interruptible(&wq->queue); ++} ++EXPORT_SYMBOL(DWC_WAITQ_TRIGGER); ++ ++void DWC_WAITQ_ABORT(dwc_waitq_t *wq) ++{ ++ wq->abort = 1; ++ DWC_WAITQ_TRIGGER(wq); ++} ++EXPORT_SYMBOL(DWC_WAITQ_ABORT); +Index: linux-3.2.46/drivers/usb/host/dwc_common_port/dwc_crypto.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_common_port/dwc_crypto.c 2013-07-26 19:31:19.000000000 +0000 +@@ -0,0 +1,306 @@ ++/* ========================================================================= ++ * $File: //dwh/usb_iip/dev/software/dwc_common_port/dwc_crypto.c $ ++ * $Revision: #1 $ ++ * $Date: 2008/12/21 $ ++ * $Change: 1156609 $ ++ * ++ * Synopsys Portability Library Software and documentation ++ * (hereinafter, "Software") is an Unsupported proprietary work of ++ * Synopsys, Inc. unless otherwise expressly agreed to in writing ++ * between Synopsys and you. ++ * ++ * The Software IS NOT an item of Licensed Software or Licensed Product ++ * under any End User Software License Agreement or Agreement for ++ * Licensed Product with Synopsys or any supplement thereto. You are ++ * permitted to use and redistribute this Software in source and binary ++ * forms, with or without modification, provided that redistributions ++ * of source code must retain this notice. You may not view, use, ++ * disclose, copy or distribute this file or any information contained ++ * herein except pursuant to this license grant from Synopsys. If you ++ * do not agree with this notice, including the disclaimer below, then ++ * you are not authorized to use the Software. ++ * ++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" ++ * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT ++ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ++ * FOR A PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL ++ * SYNOPSYS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, ++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, ++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR ++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY ++ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE ++ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH ++ * DAMAGE. ++ * ========================================================================= */ ++ ++/** @file ++ * This file contains the WUSB cryptographic routines. ++ */ ++ ++#include "dwc_crypto.h" ++#include "usb.h" ++ ++#ifdef DEBUG ++static inline void dump_bytes(char *name, uint8_t *bytes, int len) ++{ ++ int i; ++ DWC_PRINTF("%s: ", name); ++ for (i=0; idst == src, then the bytes will be encrypted ++ * in-place. ++ * ++ * @return 0 on success, negative error code on error. ++ */ ++int dwc_wusb_aes_encrypt(u8 *src, u8 *key, u8 *dst) ++{ ++ u8 block_t[16]; ++ DWC_MEMSET(block_t, 0, 16); ++ ++ return DWC_AES_CBC(src, 16, key, 16, block_t, dst); ++} ++ ++/** ++ * The CCM-MAC-FUNCTION described in section 6.5 of the WUSB spec. ++ * This function takes a data string and returns the encrypted CBC ++ * Counter-mode MIC. ++ * ++ * @param key The 128-bit symmetric key. ++ * @param nonce The CCM nonce. ++ * @param label The unique 14-byte ASCII text label. ++ * @param bytes The byte array to be encrypted. ++ * @param len Length of the byte array. ++ * @param result Byte array to receive the 8-byte encrypted MIC. ++ */ ++void dwc_wusb_cmf(u8 *key, u8 *nonce, ++ char *label, u8 *bytes, int len, u8 *result) ++{ ++ u8 block_m[16]; ++ u8 block_x[16]; ++ u8 block_t[8]; ++ int idx, blkNum; ++ u16 la = (u16)(len + 14); ++ ++ /* Set the AES-128 key */ ++ //dwc_aes_setkey(tfm, key, 16); ++ ++ /* Fill block B0 from flags = 0x59, N, and l(m) = 0 */ ++ block_m[0] = 0x59; ++ for (idx = 0; idx < 13; idx++) ++ block_m[idx + 1] = nonce[idx]; ++ block_m[14] = 0; ++ block_m[15] = 0; ++ ++ /* Produce the CBC IV */ ++ dwc_wusb_aes_encrypt(block_m, key, block_x); ++ show_block(block_m, "CBC IV in: ", "\n", 0); ++ show_block(block_x, "CBC IV out:", "\n", 0); ++ ++ /* Fill block B1 from l(a) = Blen + 14, and A */ ++ block_x[0] ^= (u8)(la >> 8); ++ block_x[1] ^= (u8)la; ++ for (idx = 0; idx < 14; idx++) ++ block_x[idx + 2] ^= label[idx]; ++ show_block(block_x, "After xor: ", "b1\n", 16); ++ ++ dwc_wusb_aes_encrypt(block_x, key, block_x); ++ show_block(block_x, "After AES: ", "b1\n", 16); ++ ++ idx = 0; ++ blkNum = 0; ++ ++ /* Fill remaining blocks with B */ ++ while (len-- > 0) { ++ block_x[idx] ^= *bytes++; ++ if (++idx >= 16) { ++ idx = 0; ++ show_block(block_x, "After xor: ", "\n", blkNum); ++ dwc_wusb_aes_encrypt(block_x, key, block_x); ++ show_block(block_x, "After AES: ", "\n", blkNum); ++ blkNum++; ++ } ++ } ++ ++ /* Handle partial last block */ ++ if (idx > 0) { ++ show_block(block_x, "After xor: ", "\n", blkNum); ++ dwc_wusb_aes_encrypt(block_x, key, block_x); ++ show_block(block_x, "After AES: ", "\n", blkNum); ++ } ++ ++ /* Save the MIC tag */ ++ DWC_MEMCPY(block_t, block_x, 8); ++ show_block(block_t, "MIC tag : ", NULL, 8); ++ ++ /* Fill block A0 from flags = 0x01, N, and counter = 0 */ ++ block_m[0] = 0x01; ++ block_m[14] = 0; ++ block_m[15] = 0; ++ ++ /* Encrypt the counter */ ++ dwc_wusb_aes_encrypt(block_m, key, block_x); ++ show_block(block_x, "CTR[MIC] : ", NULL, 8); ++ ++ /* XOR with MIC tag */ ++ for (idx = 0; idx < 8; idx++) { ++ block_t[idx] ^= block_x[idx]; ++ } ++ ++ /* Return result to caller */ ++ DWC_MEMCPY(result, block_t, 8); ++ show_block(result, "CCM-MIC : ", NULL, 8); ++ ++} ++ ++/** ++ * The PRF function described in section 6.5 of the WUSB spec. This function ++ * concatenates MIC values returned from dwc_cmf() to create a value of ++ * the requested length. ++ * ++ * @param prf_len Length of the PRF function in bits (64, 128, or 256). ++ * @param key, nonce, label, bytes, len Same as for dwc_cmf(). ++ * @param result Byte array to receive the result. ++ */ ++void dwc_wusb_prf(int prf_len, u8 *key, ++ u8 *nonce, char *label, u8 *bytes, int len, u8 *result) ++{ ++ int i; ++ ++ nonce[0] = 0; ++ for (i = 0; i < prf_len >> 6; i++, nonce[0]++) { ++ dwc_wusb_cmf(key, nonce, label, bytes, len, result); ++ result += 8; ++ } ++} ++ ++/** ++ * Fills in CCM Nonce per the WUSB spec. ++ * ++ * @param[in] haddr Host address. ++ * @param[in] daddr Device address. ++ * @param[in] tkid Session Key(PTK) identifier. ++ * @param[out] nonce Pointer to where the CCM Nonce output is to be written. ++ */ ++void dwc_wusb_fill_ccm_nonce(uint16_t haddr, uint16_t daddr, uint8_t *tkid, ++ uint8_t *nonce) ++{ ++ ++ DWC_DEBUG("%s %x %x\n", __func__, daddr, haddr); ++ ++ DWC_MEMSET(&nonce[0], 0, 16); ++ ++ DWC_MEMCPY(&nonce[6], tkid, 3); ++ nonce[9] = daddr & 0xFF; ++ nonce[10] = (daddr >> 8) & 0xFF; ++ nonce[11] = haddr & 0xFF; ++ nonce[12] = (haddr >> 8) & 0xFF; ++ ++ dump_bytes("CCM nonce", nonce, 16); ++} ++ ++/** ++ * Generates a 16-byte cryptographic-grade random number for the Host/Device ++ * Nonce. ++ */ ++void dwc_wusb_gen_nonce(uint16_t addr, uint8_t *nonce) ++{ ++ uint8_t inonce[16]; ++ uint32_t temp[4]; ++ ++ /* Fill in the Nonce */ ++ DWC_MEMSET(&inonce[0], 0, sizeof(inonce)); ++ inonce[9] = addr & 0xFF; ++ inonce[10] = (addr >> 8) & 0xFF; ++ inonce[11] = inonce[9]; ++ inonce[12] = inonce[10]; ++ ++ /* Collect "randomness samples" */ ++ DWC_RANDOM_BYTES((uint8_t *)temp, 16); ++ ++ dwc_wusb_prf_128((uint8_t *)temp, nonce, ++ "Random Numbers", (uint8_t *)temp, sizeof(temp), ++ nonce); ++} ++ ++/** ++ * Generates the Session Key (PTK) and Key Confirmation Key (KCK) per the ++ * WUSB spec. ++ * ++ * @param[in] ccm_nonce Pointer to CCM Nonce. ++ * @param[in] mk Master Key to derive the session from ++ * @param[in] hnonce Pointer to Host Nonce. ++ * @param[in] dnonce Pointer to Device Nonce. ++ * @param[out] kck Pointer to where the KCK output is to be written. ++ * @param[out] ptk Pointer to where the PTK output is to be written. ++ */ ++void dwc_wusb_gen_key(uint8_t *ccm_nonce, uint8_t *mk, uint8_t *hnonce, ++ uint8_t *dnonce, uint8_t *kck, uint8_t *ptk) ++{ ++ uint8_t idata[32]; ++ uint8_t odata[32]; ++ ++ dump_bytes("ck", mk, 16); ++ dump_bytes("hnonce", hnonce, 16); ++ dump_bytes("dnonce", dnonce, 16); ++ ++ /* The data is the HNonce and DNonce concatenated */ ++ DWC_MEMCPY(&idata[0], hnonce, 16); ++ DWC_MEMCPY(&idata[16], dnonce, 16); ++ ++ dwc_wusb_prf_256(mk, ccm_nonce, "Pair-wise keys", idata, 32, odata); ++ ++ /* Low 16 bytes of the result is the KCK, high 16 is the PTK */ ++ DWC_MEMCPY(kck, &odata[0], 16); ++ DWC_MEMCPY(ptk, &odata[16], 16); ++ ++ dump_bytes("kck", kck, 16); ++ dump_bytes("ptk", ptk, 16); ++} ++ ++/** ++ * Generates the Message Integrity Code over the Handshake data per the ++ * WUSB spec. ++ * ++ * @param ccm_nonce Pointer to CCM Nonce. ++ * @param kck Pointer to Key Confirmation Key. ++ * @param data Pointer to Handshake data to be checked. ++ * @param mic Pointer to where the MIC output is to be written. ++ */ ++void dwc_wusb_gen_mic(uint8_t *ccm_nonce, uint8_t *kck, ++ uint8_t *data, uint8_t *mic) ++{ ++ ++ dwc_wusb_prf_64(kck, ccm_nonce, "out-of-bandMIC", ++ data, WUSB_HANDSHAKE_LEN_FOR_MIC, mic); ++} ++ +Index: linux-3.2.46/drivers/usb/host/dwc_common_port/dwc_crypto.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_common_port/dwc_crypto.h 2013-07-26 19:31:19.000000000 +0000 +@@ -0,0 +1,103 @@ ++/* ========================================================================= ++ * $File: //dwh/usb_iip/dev/software/dwc_common_port/dwc_crypto.h $ ++ * $Revision: #1 $ ++ * $Date: 2008/12/21 $ ++ * $Change: 1156609 $ ++ * ++ * Synopsys Portability Library Software and documentation ++ * (hereinafter, "Software") is an Unsupported proprietary work of ++ * Synopsys, Inc. unless otherwise expressly agreed to in writing ++ * between Synopsys and you. ++ * ++ * The Software IS NOT an item of Licensed Software or Licensed Product ++ * under any End User Software License Agreement or Agreement for ++ * Licensed Product with Synopsys or any supplement thereto. You are ++ * permitted to use and redistribute this Software in source and binary ++ * forms, with or without modification, provided that redistributions ++ * of source code must retain this notice. You may not view, use, ++ * disclose, copy or distribute this file or any information contained ++ * herein except pursuant to this license grant from Synopsys. If you ++ * do not agree with this notice, including the disclaimer below, then ++ * you are not authorized to use the Software. ++ * ++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" ++ * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT ++ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ++ * FOR A PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL ++ * SYNOPSYS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, ++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, ++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR ++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY ++ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE ++ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH ++ * DAMAGE. ++ * ========================================================================= */ ++ ++#ifndef _DWC_CRYPTO_H_ ++#define _DWC_CRYPTO_H_ ++ ++/** @file ++ * ++ * This file contains declarations for the WUSB Cryptographic routines as ++ * defined in the WUSB spec. They are only to be used internally by the DWC UWB ++ * modules. ++ */ ++ ++#include "dwc_os.h" ++ ++int dwc_wusb_aes_encrypt(u8 *src, u8 *key, u8 *dst); ++ ++void dwc_wusb_cmf(u8 *key, u8 *nonce, ++ char *label, u8 *bytes, int len, u8 *result); ++void dwc_wusb_prf(int prf_len, u8 *key, ++ u8 *nonce, char *label, u8 *bytes, int len, u8 *result); ++ ++/** ++ * The PRF-64 function described in section 6.5 of the WUSB spec. ++ * ++ * @param key, nonce, label, bytes, len, result Same as for dwc_prf(). ++ */ ++static inline void dwc_wusb_prf_64(u8 *key, u8 *nonce, ++ char *label, u8 *bytes, int len, u8 *result) ++{ ++ dwc_wusb_prf(64, key, nonce, label, bytes, len, result); ++} ++ ++/** ++ * The PRF-128 function described in section 6.5 of the WUSB spec. ++ * ++ * @param key, nonce, label, bytes, len, result Same as for dwc_prf(). ++ */ ++static inline void dwc_wusb_prf_128(u8 *key, u8 *nonce, ++ char *label, u8 *bytes, int len, u8 *result) ++{ ++ dwc_wusb_prf(128, key, nonce, label, bytes, len, result); ++} ++ ++/** ++ * The PRF-256 function described in section 6.5 of the WUSB spec. ++ * ++ * @param key, nonce, label, bytes, len, result Same as for dwc_prf(). ++ */ ++static inline void dwc_wusb_prf_256(u8 *key, u8 *nonce, ++ char *label, u8 *bytes, int len, u8 *result) ++{ ++ dwc_wusb_prf(256, key, nonce, label, bytes, len, result); ++} ++ ++ ++void dwc_wusb_fill_ccm_nonce(uint16_t haddr, uint16_t daddr, uint8_t *tkid, ++ uint8_t *nonce); ++void dwc_wusb_gen_nonce(uint16_t addr, ++ uint8_t *nonce); ++ ++void dwc_wusb_gen_key(uint8_t *ccm_nonce, uint8_t *mk, ++ uint8_t *hnonce, uint8_t *dnonce, ++ uint8_t *kck, uint8_t *ptk); ++ ++ ++void dwc_wusb_gen_mic(uint8_t *ccm_nonce, uint8_t ++ *kck, uint8_t *data, uint8_t *mic); ++ ++#endif /* _DWC_CRYPTO_H_ */ +Index: linux-3.2.46/drivers/usb/host/dwc_common_port/dwc_dh.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_common_port/dwc_dh.c 2013-07-26 19:31:19.000000000 +0000 +@@ -0,0 +1,286 @@ ++/* ========================================================================= ++ * $File: //dwh/usb_iip/dev/software/dwc_common_port/dwc_dh.c $ ++ * $Revision: #1 $ ++ * $Date: 2008/12/21 $ ++ * $Change: 1156609 $ ++ * ++ * Synopsys Portability Library Software and documentation ++ * (hereinafter, "Software") is an Unsupported proprietary work of ++ * Synopsys, Inc. unless otherwise expressly agreed to in writing ++ * between Synopsys and you. ++ * ++ * The Software IS NOT an item of Licensed Software or Licensed Product ++ * under any End User Software License Agreement or Agreement for ++ * Licensed Product with Synopsys or any supplement thereto. You are ++ * permitted to use and redistribute this Software in source and binary ++ * forms, with or without modification, provided that redistributions ++ * of source code must retain this notice. You may not view, use, ++ * disclose, copy or distribute this file or any information contained ++ * herein except pursuant to this license grant from Synopsys. If you ++ * do not agree with this notice, including the disclaimer below, then ++ * you are not authorized to use the Software. ++ * ++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" ++ * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT ++ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ++ * FOR A PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL ++ * SYNOPSYS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, ++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, ++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR ++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY ++ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE ++ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH ++ * DAMAGE. ++ * ========================================================================= */ ++#ifndef CONFIG_MACH_IPMATE ++#include "dwc_dh.h" ++#include "dwc_modpow.h" ++ ++#ifdef DEBUG ++/* This function prints out a buffer in the format described in the Association ++ * Model specification. */ ++static void dh_dump(char *str, void *_num, int len) ++{ ++ uint8_t *num = _num; ++ int i; ++ DWC_PRINTF("%s\n", str); ++ for (i = 0; i < len; i ++) { ++ DWC_PRINTF("%02x", num[i]); ++ if (((i + 1) % 2) == 0) DWC_PRINTF(" "); ++ if (((i + 1) % 26) == 0) DWC_PRINTF("\n"); ++ } ++ ++ DWC_PRINTF("\n"); ++} ++#else ++#define dh_dump(_x...) do {; } while(0) ++#endif ++ ++/* Constant g value */ ++static __u32 dh_g[] = { ++ 0x02000000, ++}; ++ ++/* Constant p value */ ++static __u32 dh_p[] = { ++ 0xFFFFFFFF, 0xFFFFFFFF, 0xA2DA0FC9, 0x34C26821, 0x8B62C6C4, 0xD11CDC80, 0x084E0229, 0x74CC678A, ++ 0xA6BE0B02, 0x229B133B, 0x79084A51, 0xDD04348E, 0xB31995EF, 0x1B433ACD, 0x6D0A2B30, 0x37145FF2, ++ 0x6D35E14F, 0x45C2516D, 0x76B585E4, 0xC67E5E62, 0xE9424CF4, 0x6BED37A6, 0xB65CFF0B, 0xEDB706F4, ++ 0xFB6B38EE, 0xA59F895A, 0x11249FAE, 0xE61F4B7C, 0x51662849, 0x3D5BE4EC, 0xB87C00C2, 0x05BF63A1, ++ 0x3648DA98, 0x9AD3551C, 0xA83F1669, 0x5FCF24FD, 0x235D6583, 0x96ADA3DC, 0x56F3621C, 0xBB528520, ++ 0x0729D59E, 0x6D969670, 0x4E350C67, 0x0498BC4A, 0x086C74F1, 0x7C2118CA, 0x465E9032, 0x3BCE362E, ++ 0x2C779EE3, 0x03860E18, 0xA283279B, 0x8FA207EC, 0xF05DC5B5, 0xC9524C6F, 0xF6CB2BDE, 0x18175895, ++ 0x7C499539, 0xE56A95EA, 0x1826D215, 0x1005FA98, 0x5A8E7215, 0x2DC4AA8A, 0x0D1733AD, 0x337A5004, ++ 0xAB2155A8, 0x64BA1CDF, 0x0485FBEC, 0x0AEFDB58, 0x5771EA8A, 0x7D0C065D, 0x850F97B3, 0xC7E4E1A6, ++ 0x8CAEF5AB, 0xD73309DB, 0xE0948C1E, 0x9D61254A, 0x26D2E3CE, 0x6BEED21A, 0x06FA2FF1, 0x64088AD9, ++ 0x730276D8, 0x646AC83E, 0x182B1F52, 0x0C207B17, 0x5717E1BB, 0x6C5D617A, 0xC0880977, 0xE246D9BA, ++ 0xA04FE208, 0x31ABE574, 0xFC5BDB43, 0x8E10FDE0, 0x20D1824B, 0xCAD23AA9, 0xFFFFFFFF, 0xFFFFFFFF, ++}; ++ ++static void dh_swap_bytes(void *_in, void *_out, uint32_t len) ++{ ++ uint8_t *in = _in; ++ uint8_t *out = _out; ++ int i; ++ for (i=0; inext = (link); \ ++ (link)->prev = (link); \ ++} while(0) ++ ++#define DWC_LIST_FIRST(link) ((link)->next) ++#define DWC_LIST_LAST(link) ((link)->prev) ++#define DWC_LIST_END(link) (link) ++#define DWC_LIST_NEXT(link) ((link)->next) ++#define DWC_LIST_PREV(link) ((link)->prev) ++#define DWC_LIST_EMPTY(link) \ ++ (DWC_LIST_FIRST(link) == DWC_LIST_END(link)) ++#define DWC_LIST_ENTRY(link, type, field) (type *) \ ++ ((uint8_t *)(link) - (size_t)(&((type *)0)->field)) ++ ++#define DWC_LIST_INSERT_HEAD(list, link) do { \ ++ (link)->next = (list)->next; \ ++ (link)->prev = (list); \ ++ (list)->next->prev = link; \ ++ (list)->next = link; \ ++} while(0) ++ ++#define DWC_LIST_INSERT_TAIL(list, link) do { \ ++ (link)->next = list; \ ++ (link)->prev = (list)->prev; \ ++ (list)->prev->next = link; \ ++ (list)->prev = link; \ ++} while(0) ++ ++#define DWC_LIST_REMOVE(link) do { \ ++ (link)->next->prev = (link)->prev; \ ++ (link)->prev->next = (link)->next; \ ++} while(0) ++ ++#define DWC_LIST_REMOVE_INIT(link) do { \ ++ DWC_LIST_REMOVE(link); \ ++ DWC_LIST_INIT(link); \ ++} while(0) ++ ++#define DWC_LIST_MOVE_HEAD(list, link) do { \ ++ DWC_LIST_REMOVE(link); \ ++ DWC_LIST_INSERT_HEAD(list, link); \ ++} while(0) ++ ++#define DWC_LIST_MOVE_TAIL(list, link) do { \ ++ DWC_LIST_REMOVE(link); \ ++ DWC_LIST_INSERT_TAIL(list, link); \ ++} while(0) ++ ++#define DWC_LIST_FOREACH(var, list) \ ++ for((var) = DWC_LIST_FIRST(list); \ ++ (var) != DWC_LIST_END(list); \ ++ (var) = DWC_LIST_NEXT(var)) ++ ++#define DWC_LIST_FOREACH_SAFE(var, var2, list) \ ++ for((var) = DWC_LIST_FIRST(list), var2 = DWC_LIST_NEXT(var); \ ++ (var) != DWC_LIST_END(list); \ ++ (var) = (var2), var2 = DWC_LIST_NEXT(var2)) ++ ++#define DWC_LIST_FOREACH_REVERSE(var, list) \ ++ for((var) = DWC_LIST_LAST(list); \ ++ (var) != DWC_LIST_END(list); \ ++ (var) = DWC_LIST_PREV(var)) ++ ++/* ++ * Singly-linked List definitions. ++ */ ++#define DWC_SLIST_HEAD(name, type) \ ++struct name { \ ++ struct type *slh_first; /* first element */ \ ++} ++ ++#define DWC_SLIST_HEAD_INITIALIZER(head) \ ++ { NULL } ++ ++#define DWC_SLIST_ENTRY(type) \ ++struct { \ ++ struct type *sle_next; /* next element */ \ ++} ++ ++/* ++ * Singly-linked List access methods. ++ */ ++#define DWC_SLIST_FIRST(head) ((head)->slh_first) ++#define DWC_SLIST_END(head) NULL ++#define DWC_SLIST_EMPTY(head) (SLIST_FIRST(head) == SLIST_END(head)) ++#define DWC_SLIST_NEXT(elm, field) ((elm)->field.sle_next) ++ ++#define DWC_SLIST_FOREACH(var, head, field) \ ++ for((var) = SLIST_FIRST(head); \ ++ (var) != SLIST_END(head); \ ++ (var) = SLIST_NEXT(var, field)) ++ ++#define DWC_SLIST_FOREACH_PREVPTR(var, varp, head, field) \ ++ for ((varp) = &SLIST_FIRST((head)); \ ++ ((var) = *(varp)) != SLIST_END(head); \ ++ (varp) = &SLIST_NEXT((var), field)) ++ ++/* ++ * Singly-linked List functions. ++ */ ++#define DWC_SLIST_INIT(head) { \ ++ SLIST_FIRST(head) = SLIST_END(head); \ ++} ++ ++#define DWC_SLIST_INSERT_AFTER(slistelm, elm, field) do { \ ++ (elm)->field.sle_next = (slistelm)->field.sle_next; \ ++ (slistelm)->field.sle_next = (elm); \ ++} while (0) ++ ++#define DWC_SLIST_INSERT_HEAD(head, elm, field) do { \ ++ (elm)->field.sle_next = (head)->slh_first; \ ++ (head)->slh_first = (elm); \ ++} while (0) ++ ++#define DWC_SLIST_REMOVE_NEXT(head, elm, field) do { \ ++ (elm)->field.sle_next = (elm)->field.sle_next->field.sle_next; \ ++} while (0) ++ ++#define DWC_SLIST_REMOVE_HEAD(head, field) do { \ ++ (head)->slh_first = (head)->slh_first->field.sle_next; \ ++} while (0) ++ ++#define DWC_SLIST_REMOVE(head, elm, type, field) do { \ ++ if ((head)->slh_first == (elm)) { \ ++ SLIST_REMOVE_HEAD((head), field); \ ++ } \ ++ else { \ ++ struct type *curelm = (head)->slh_first; \ ++ while( curelm->field.sle_next != (elm) ) \ ++ curelm = curelm->field.sle_next; \ ++ curelm->field.sle_next = \ ++ curelm->field.sle_next->field.sle_next; \ ++ } \ ++} while (0) ++ ++#if 0 ++ ++/* ++ * List definitions. ++ */ ++#define DWC_LIST_HEAD(name, type) \ ++struct name { \ ++ struct type *lh_first; /* first element */ \ ++} ++ ++#define DWC_LIST_HEAD_INITIALIZER(head) \ ++ { NULL } ++ ++#define DWC_LIST_ENTRY(type) \ ++struct { \ ++ struct type *le_next; /* next element */ \ ++ struct type **le_prev; /* address of previous next element */ \ ++} ++ ++/* ++ * List access methods ++ */ ++#define DWC_LIST_FIRST(head) ((head)->lh_first) ++#define DWC_LIST_END(head) NULL ++#define DWC_LIST_EMPTY(head) (DWC_LIST_FIRST(head) == DWC_LIST_END(head)) ++#define DWC_LIST_NEXT(elm, field) ((elm)->field.le_next) ++ ++#define DWC_LIST_FOREACH(var, head, field) \ ++ for((var) = DWC_LIST_FIRST(head); \ ++ (var)!= DWC_LIST_END(head); \ ++ (var) = DWC_LIST_NEXT(var, field)) ++#define DWC_LIST_FOREACH_SAFE(var, var2, head, field) \ ++ for((var) = DWC_LIST_FIRST(head), var2 = DWC_LIST_NEXT(var, field); \ ++ (var) != DWC_LIST_END(head); \ ++ (var) = var2, var2 = DWC_LIST_NEXT(var, field)) ++ ++/* ++ * List functions. ++ */ ++#define DWC_LIST_INIT(head) do { \ ++ DWC_LIST_FIRST(head) = DWC_LIST_END(head); \ ++} while (0) ++ ++#define DWC_LIST_INSERT_AFTER(listelm, elm, field) do { \ ++ if (((elm)->field.le_next = (listelm)->field.le_next) != NULL) \ ++ (listelm)->field.le_next->field.le_prev = \ ++ &(elm)->field.le_next; \ ++ (listelm)->field.le_next = (elm); \ ++ (elm)->field.le_prev = &(listelm)->field.le_next; \ ++} while (0) ++ ++#define DWC_LIST_INSERT_BEFORE(listelm, elm, field) do { \ ++ (elm)->field.le_prev = (listelm)->field.le_prev; \ ++ (elm)->field.le_next = (listelm); \ ++ *(listelm)->field.le_prev = (elm); \ ++ (listelm)->field.le_prev = &(elm)->field.le_next; \ ++} while (0) ++ ++#define DWC_LIST_INSERT_HEAD(head, elm, field) do { \ ++ if (((elm)->field.le_next = (head)->lh_first) != NULL) \ ++ (head)->lh_first->field.le_prev = &(elm)->field.le_next;\ ++ (head)->lh_first = (elm); \ ++ (elm)->field.le_prev = &(head)->lh_first; \ ++} while (0) ++ ++#define DWC_LIST_REMOVE(elm, field) do { \ ++ if ((elm)->field.le_next != NULL) \ ++ (elm)->field.le_next->field.le_prev = \ ++ (elm)->field.le_prev; \ ++ *(elm)->field.le_prev = (elm)->field.le_next; \ ++} while (0) ++ ++#define DWC_LIST_REPLACE(elm, elm2, field) do { \ ++ if (((elm2)->field.le_next = (elm)->field.le_next) != NULL) \ ++ (elm2)->field.le_next->field.le_prev = \ ++ &(elm2)->field.le_next; \ ++ (elm2)->field.le_prev = (elm)->field.le_prev; \ ++ *(elm2)->field.le_prev = (elm2); \ ++} while (0) ++ ++#endif ++ ++/* ++ * Simple queue definitions. ++ */ ++#define DWC_SIMPLEQ_HEAD(name, type) \ ++struct name { \ ++ struct type *sqh_first; /* first element */ \ ++ struct type **sqh_last; /* addr of last next element */ \ ++} ++ ++#define DWC_SIMPLEQ_HEAD_INITIALIZER(head) \ ++ { NULL, &(head).sqh_first } ++ ++#define DWC_SIMPLEQ_ENTRY(type) \ ++struct { \ ++ struct type *sqe_next; /* next element */ \ ++} ++ ++/* ++ * Simple queue access methods. ++ */ ++#define DWC_SIMPLEQ_FIRST(head) ((head)->sqh_first) ++#define DWC_SIMPLEQ_END(head) NULL ++#define DWC_SIMPLEQ_EMPTY(head) (SIMPLEQ_FIRST(head) == SIMPLEQ_END(head)) ++#define DWC_SIMPLEQ_NEXT(elm, field) ((elm)->field.sqe_next) ++ ++#define DWC_SIMPLEQ_FOREACH(var, head, field) \ ++ for((var) = SIMPLEQ_FIRST(head); \ ++ (var) != SIMPLEQ_END(head); \ ++ (var) = SIMPLEQ_NEXT(var, field)) ++ ++/* ++ * Simple queue functions. ++ */ ++#define DWC_SIMPLEQ_INIT(head) do { \ ++ (head)->sqh_first = NULL; \ ++ (head)->sqh_last = &(head)->sqh_first; \ ++} while (0) ++ ++#define DWC_SIMPLEQ_INSERT_HEAD(head, elm, field) do { \ ++ if (((elm)->field.sqe_next = (head)->sqh_first) == NULL) \ ++ (head)->sqh_last = &(elm)->field.sqe_next; \ ++ (head)->sqh_first = (elm); \ ++} while (0) ++ ++#define DWC_SIMPLEQ_INSERT_TAIL(head, elm, field) do { \ ++ (elm)->field.sqe_next = NULL; \ ++ *(head)->sqh_last = (elm); \ ++ (head)->sqh_last = &(elm)->field.sqe_next; \ ++} while (0) ++ ++#define DWC_SIMPLEQ_INSERT_AFTER(head, listelm, elm, field) do { \ ++ if (((elm)->field.sqe_next = (listelm)->field.sqe_next) == NULL)\ ++ (head)->sqh_last = &(elm)->field.sqe_next; \ ++ (listelm)->field.sqe_next = (elm); \ ++} while (0) ++ ++#define DWC_SIMPLEQ_REMOVE_HEAD(head, field) do { \ ++ if (((head)->sqh_first = (head)->sqh_first->field.sqe_next) == NULL) \ ++ (head)->sqh_last = &(head)->sqh_first; \ ++} while (0) ++ ++/* ++ * Tail queue definitions. ++ */ ++#define DWC_TAILQ_HEAD(name, type) \ ++struct name { \ ++ struct type *tqh_first; /* first element */ \ ++ struct type **tqh_last; /* addr of last next element */ \ ++} ++ ++#define DWC_TAILQ_HEAD_INITIALIZER(head) \ ++ { NULL, &(head).tqh_first } ++ ++#define DWC_TAILQ_ENTRY(type) \ ++struct { \ ++ struct type *tqe_next; /* next element */ \ ++ struct type **tqe_prev; /* address of previous next element */ \ ++} ++ ++/* ++ * tail queue access methods ++ */ ++#define DWC_TAILQ_FIRST(head) ((head)->tqh_first) ++#define DWC_TAILQ_END(head) NULL ++#define DWC_TAILQ_NEXT(elm, field) ((elm)->field.tqe_next) ++#define DWC_TAILQ_LAST(head, headname) \ ++ (*(((struct headname *)((head)->tqh_last))->tqh_last)) ++/* XXX */ ++#define DWC_TAILQ_PREV(elm, headname, field) \ ++ (*(((struct headname *)((elm)->field.tqe_prev))->tqh_last)) ++#define DWC_TAILQ_EMPTY(head) \ ++ (TAILQ_FIRST(head) == TAILQ_END(head)) ++ ++#define DWC_TAILQ_FOREACH(var, head, field) \ ++ for((var) = TAILQ_FIRST(head); \ ++ (var) != TAILQ_END(head); \ ++ (var) = TAILQ_NEXT(var, field)) ++ ++#define DWC_TAILQ_FOREACH_REVERSE(var, head, headname, field) \ ++ for((var) = TAILQ_LAST(head, headname); \ ++ (var) != TAILQ_END(head); \ ++ (var) = TAILQ_PREV(var, headname, field)) ++ ++/* ++ * Tail queue functions. ++ */ ++#define DWC_TAILQ_INIT(head) do { \ ++ (head)->tqh_first = NULL; \ ++ (head)->tqh_last = &(head)->tqh_first; \ ++} while (0) ++ ++#define DWC_TAILQ_INSERT_HEAD(head, elm, field) do { \ ++ if (((elm)->field.tqe_next = (head)->tqh_first) != NULL) \ ++ (head)->tqh_first->field.tqe_prev = \ ++ &(elm)->field.tqe_next; \ ++ else \ ++ (head)->tqh_last = &(elm)->field.tqe_next; \ ++ (head)->tqh_first = (elm); \ ++ (elm)->field.tqe_prev = &(head)->tqh_first; \ ++} while (0) ++ ++#define DWC_TAILQ_INSERT_TAIL(head, elm, field) do { \ ++ (elm)->field.tqe_next = NULL; \ ++ (elm)->field.tqe_prev = (head)->tqh_last; \ ++ *(head)->tqh_last = (elm); \ ++ (head)->tqh_last = &(elm)->field.tqe_next; \ ++} while (0) ++ ++#define DWC_TAILQ_INSERT_AFTER(head, listelm, elm, field) do { \ ++ if (((elm)->field.tqe_next = (listelm)->field.tqe_next) != NULL)\ ++ (elm)->field.tqe_next->field.tqe_prev = \ ++ &(elm)->field.tqe_next; \ ++ else \ ++ (head)->tqh_last = &(elm)->field.tqe_next; \ ++ (listelm)->field.tqe_next = (elm); \ ++ (elm)->field.tqe_prev = &(listelm)->field.tqe_next; \ ++} while (0) ++ ++#define DWC_TAILQ_INSERT_BEFORE(listelm, elm, field) do { \ ++ (elm)->field.tqe_prev = (listelm)->field.tqe_prev; \ ++ (elm)->field.tqe_next = (listelm); \ ++ *(listelm)->field.tqe_prev = (elm); \ ++ (listelm)->field.tqe_prev = &(elm)->field.tqe_next; \ ++} while (0) ++ ++#define DWC_TAILQ_REMOVE(head, elm, field) do { \ ++ if (((elm)->field.tqe_next) != NULL) \ ++ (elm)->field.tqe_next->field.tqe_prev = \ ++ (elm)->field.tqe_prev; \ ++ else \ ++ (head)->tqh_last = (elm)->field.tqe_prev; \ ++ *(elm)->field.tqe_prev = (elm)->field.tqe_next; \ ++} while (0) ++ ++#define DWC_TAILQ_REPLACE(head, elm, elm2, field) do { \ ++ if (((elm2)->field.tqe_next = (elm)->field.tqe_next) != NULL) \ ++ (elm2)->field.tqe_next->field.tqe_prev = \ ++ &(elm2)->field.tqe_next; \ ++ else \ ++ (head)->tqh_last = &(elm2)->field.tqe_next; \ ++ (elm2)->field.tqe_prev = (elm)->field.tqe_prev; \ ++ *(elm2)->field.tqe_prev = (elm2); \ ++} while (0) ++ ++/* ++ * Circular queue definitions. ++ */ ++#define DWC_CIRCLEQ_HEAD(name, type) \ ++struct name { \ ++ struct type *cqh_first; /* first element */ \ ++ struct type *cqh_last; /* last element */ \ ++} ++ ++#define DWC_CIRCLEQ_HEAD_INITIALIZER(head) \ ++ { DWC_CIRCLEQ_END(&head), DWC_CIRCLEQ_END(&head) } ++ ++#define DWC_CIRCLEQ_ENTRY(type) \ ++struct { \ ++ struct type *cqe_next; /* next element */ \ ++ struct type *cqe_prev; /* previous element */ \ ++} ++ ++/* ++ * Circular queue access methods ++ */ ++#define DWC_CIRCLEQ_FIRST(head) ((head)->cqh_first) ++#define DWC_CIRCLEQ_LAST(head) ((head)->cqh_last) ++#define DWC_CIRCLEQ_END(head) ((void *)(head)) ++#define DWC_CIRCLEQ_NEXT(elm, field) ((elm)->field.cqe_next) ++#define DWC_CIRCLEQ_PREV(elm, field) ((elm)->field.cqe_prev) ++#define DWC_CIRCLEQ_EMPTY(head) \ ++ (DWC_CIRCLEQ_FIRST(head) == DWC_CIRCLEQ_END(head)) ++ ++#define DWC_CIRCLEQ_EMPTY_ENTRY(elm, field) (((elm)->field.cqe_next == NULL) && ((elm)->field.cqe_prev == NULL)) ++ ++#define DWC_CIRCLEQ_FOREACH(var, head, field) \ ++ for((var) = DWC_CIRCLEQ_FIRST(head); \ ++ (var) != DWC_CIRCLEQ_END(head); \ ++ (var) = DWC_CIRCLEQ_NEXT(var, field)) ++ ++#define DWC_CIRCLEQ_FOREACH_SAFE(var, var2, head, field) \ ++ for((var) = DWC_CIRCLEQ_FIRST(head), var2 = DWC_CIRCLEQ_NEXT(var, field); \ ++ (var) != DWC_CIRCLEQ_END(head); \ ++ (var) = var2, var2 = DWC_CIRCLEQ_NEXT(var, field)) ++ ++#define DWC_CIRCLEQ_FOREACH_REVERSE(var, head, field) \ ++ for((var) = DWC_CIRCLEQ_LAST(head); \ ++ (var) != DWC_CIRCLEQ_END(head); \ ++ (var) = DWC_CIRCLEQ_PREV(var, field)) ++ ++/* ++ * Circular queue functions. ++ */ ++#define DWC_CIRCLEQ_INIT(head) do { \ ++ (head)->cqh_first = DWC_CIRCLEQ_END(head); \ ++ (head)->cqh_last = DWC_CIRCLEQ_END(head); \ ++} while (0) ++ ++#define DWC_CIRCLEQ_INIT_ENTRY(elm, field) do { \ ++ (elm)->field.cqe_next = NULL; \ ++ (elm)->field.cqe_prev = NULL; \ ++} while (0) ++ ++#define DWC_CIRCLEQ_INSERT_AFTER(head, listelm, elm, field) do { \ ++ (elm)->field.cqe_next = (listelm)->field.cqe_next; \ ++ (elm)->field.cqe_prev = (listelm); \ ++ if ((listelm)->field.cqe_next == DWC_CIRCLEQ_END(head)) \ ++ (head)->cqh_last = (elm); \ ++ else \ ++ (listelm)->field.cqe_next->field.cqe_prev = (elm); \ ++ (listelm)->field.cqe_next = (elm); \ ++} while (0) ++ ++#define DWC_CIRCLEQ_INSERT_BEFORE(head, listelm, elm, field) do { \ ++ (elm)->field.cqe_next = (listelm); \ ++ (elm)->field.cqe_prev = (listelm)->field.cqe_prev; \ ++ if ((listelm)->field.cqe_prev == DWC_CIRCLEQ_END(head)) \ ++ (head)->cqh_first = (elm); \ ++ else \ ++ (listelm)->field.cqe_prev->field.cqe_next = (elm); \ ++ (listelm)->field.cqe_prev = (elm); \ ++} while (0) ++ ++#define DWC_CIRCLEQ_INSERT_HEAD(head, elm, field) do { \ ++ (elm)->field.cqe_next = (head)->cqh_first; \ ++ (elm)->field.cqe_prev = DWC_CIRCLEQ_END(head); \ ++ if ((head)->cqh_last == DWC_CIRCLEQ_END(head)) \ ++ (head)->cqh_last = (elm); \ ++ else \ ++ (head)->cqh_first->field.cqe_prev = (elm); \ ++ (head)->cqh_first = (elm); \ ++} while (0) ++ ++#define DWC_CIRCLEQ_INSERT_TAIL(head, elm, field) do { \ ++ (elm)->field.cqe_next = DWC_CIRCLEQ_END(head); \ ++ (elm)->field.cqe_prev = (head)->cqh_last; \ ++ if ((head)->cqh_first == DWC_CIRCLEQ_END(head)) \ ++ (head)->cqh_first = (elm); \ ++ else \ ++ (head)->cqh_last->field.cqe_next = (elm); \ ++ (head)->cqh_last = (elm); \ ++} while (0) ++ ++#define DWC_CIRCLEQ_REMOVE(head, elm, field) do { \ ++ if ((elm)->field.cqe_next == DWC_CIRCLEQ_END(head)) \ ++ (head)->cqh_last = (elm)->field.cqe_prev; \ ++ else \ ++ (elm)->field.cqe_next->field.cqe_prev = \ ++ (elm)->field.cqe_prev; \ ++ if ((elm)->field.cqe_prev == DWC_CIRCLEQ_END(head)) \ ++ (head)->cqh_first = (elm)->field.cqe_next; \ ++ else \ ++ (elm)->field.cqe_prev->field.cqe_next = \ ++ (elm)->field.cqe_next; \ ++} while (0) ++ ++#define DWC_CIRCLEQ_REMOVE_INIT(head, elm, field) do { \ ++ DWC_CIRCLEQ_REMOVE(head, elm, field); \ ++ DWC_CIRCLEQ_INIT_ENTRY(elm, field); \ ++} while (0) ++ ++#define DWC_CIRCLEQ_REPLACE(head, elm, elm2, field) do { \ ++ if (((elm2)->field.cqe_next = (elm)->field.cqe_next) == \ ++ DWC_CIRCLEQ_END(head)) \ ++ (head).cqh_last = (elm2); \ ++ else \ ++ (elm2)->field.cqe_next->field.cqe_prev = (elm2); \ ++ if (((elm2)->field.cqe_prev = (elm)->field.cqe_prev) == \ ++ DWC_CIRCLEQ_END(head)) \ ++ (head).cqh_first = (elm2); \ ++ else \ ++ (elm2)->field.cqe_prev->field.cqe_next = (elm2); \ ++} while (0) ++ ++#endif /* !_SYS_QUEUE_H_ */ +Index: linux-3.2.46/drivers/usb/host/dwc_common_port/dwc_mem.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_common_port/dwc_mem.c 2013-07-26 19:31:19.000000000 +0000 +@@ -0,0 +1,172 @@ ++#include "dwc_os.h" ++#include "dwc_list.h" ++ ++/* Memory Debugging */ ++#ifdef DEBUG_MEMORY ++ ++struct allocation ++{ ++ void *addr; ++ char *func; ++ int line; ++ uint32_t size; ++ int dma; ++ DWC_CIRCLEQ_ENTRY(allocation) entry; ++}; ++ ++DWC_CIRCLEQ_HEAD(allocation_queue, allocation); ++ ++struct allocation_manager ++{ ++ struct allocation_queue allocations; ++ ++ /* statistics */ ++ int num; ++ int num_freed; ++ int num_active; ++ uint32_t total; ++ uint32_t current; ++ uint32_t max; ++}; ++ ++ ++static struct allocation_manager *manager = NULL; ++ ++static void add_allocation(uint32_t size, char const* func, int line, void *addr, int dma) ++{ ++ struct allocation *a = __DWC_ALLOC_ATOMIC(sizeof(*a)); ++ a->func = __DWC_ALLOC_ATOMIC(DWC_STRLEN(func)+1); ++ DWC_MEMCPY(a->func, func, DWC_STRLEN(func)+1); ++ a->line = line; ++ a->size = size; ++ a->addr = addr; ++ a->dma = dma; ++ DWC_CIRCLEQ_INSERT_TAIL(&manager->allocations, a, entry); ++ ++ /* Update stats */ ++ manager->num ++; ++ manager->num_active ++; ++ manager->total += size; ++ manager->current += size; ++ if (manager->max < manager->current) { ++ manager->max = manager->current; ++ } ++} ++ ++static struct allocation *find_allocation(void *addr) ++{ ++ struct allocation *a; ++ DWC_CIRCLEQ_FOREACH(a, &manager->allocations, entry) { ++ if (a->addr == addr) { ++ return a; ++ } ++ } ++ return NULL; ++} ++ ++static void free_allocation(void *addr, char const* func, int line) ++{ ++ struct allocation *a = find_allocation(addr); ++ if (!a && func && (line >= 0)) { ++ DWC_ASSERT(0, "Free of address %p that was never allocated or already freed %s:%d", addr, func, line); ++ return; ++ } ++ DWC_CIRCLEQ_REMOVE(&manager->allocations, a, entry); ++ ++ manager->num_active --; ++ manager->num_freed ++; ++ manager->current -= a->size; ++ __DWC_FREE(a->func); ++ __DWC_FREE(a); ++} ++ ++void dwc_memory_debug_start(void) ++{ ++ DWC_ASSERT(manager == NULL, "Memory debugging has already started\n"); ++ if (manager == NULL) { ++ manager = __DWC_ALLOC(sizeof(*manager)); ++ } ++ ++ DWC_CIRCLEQ_INIT(&manager->allocations); ++ manager->num = 0; ++ manager->num_freed = 0; ++ manager->num_active = 0; ++ manager->total = 0; ++ manager->current = 0; ++ manager->max = 0; ++} ++ ++void dwc_memory_debug_stop(void) ++{ ++ struct allocation *a; ++ dwc_memory_debug_report(); ++ ++ DWC_CIRCLEQ_FOREACH(a, &manager->allocations, entry) { ++ DWC_ERROR("Memory leaked from %s:%d\n", a->func, a->line); ++ free_allocation(a->addr, NULL, -1); ++ } ++ ++ __DWC_FREE(manager); ++} ++ ++void dwc_memory_debug_report(void) ++{ ++ struct allocation *a; ++ DWC_PRINTF("\n\n\n----------------- Memory Debugging Report -----------------\n\n"); ++ DWC_PRINTF("Num Allocations = %d\n", manager->num); ++ DWC_PRINTF("Freed = %d\n", manager->num_freed); ++ DWC_PRINTF("Active = %d\n", manager->num_active); ++ DWC_PRINTF("Current Memory Used = %d\n", manager->current); ++ DWC_PRINTF("Total Memory Used = %d\n", manager->total); ++ DWC_PRINTF("Maximum Memory Used at Once = %d\n", manager->max); ++ DWC_PRINTF("Unfreed allocations:\n"); ++ ++ DWC_CIRCLEQ_FOREACH(a, &manager->allocations, entry) { ++ DWC_PRINTF(" addr=%p, size=%d from %s:%d, DMA=%d\n", a->addr, a->size, a->func, a->line, a->dma); ++ } ++} ++ ++ ++ ++/* The replacement functions */ ++void *dwc_alloc_debug(uint32_t size, char const* func, int line) ++{ ++ void *addr = __DWC_ALLOC(size); ++ add_allocation(size, func, line, addr, 0); ++ return addr; ++} ++ ++void *dwc_alloc_atomic_debug(uint32_t size, char const* func, int line) ++{ ++ void *addr = __DWC_ALLOC_ATOMIC(size); ++ add_allocation(size, func, line, addr, 0); ++ return addr; ++} ++ ++void dwc_free_debug(void *addr, char const* func, int line) ++{ ++ free_allocation(addr, func, line); ++ __DWC_FREE(addr); ++} ++ ++void *dwc_dma_alloc_debug(uint32_t size, dwc_dma_t *dma_addr, char const *func, int line) ++{ ++ void *addr = __DWC_DMA_ALLOC(size, dma_addr); ++ add_allocation(size, func, line, addr, 1); ++ return addr; ++} ++ ++void *dwc_dma_alloc_atomic_debug(uint32_t size, dwc_dma_t *dma_addr, char const *func, int line) ++{ ++ void *addr = __DWC_DMA_ALLOC_ATOMIC(size, dma_addr); ++ add_allocation(size, func, line, addr, 1); ++ return addr; ++} ++ ++void dwc_dma_free_debug(uint32_t size, void *virt_addr, dwc_dma_t dma_addr, char const *func, int line) ++{ ++ free_allocation(virt_addr, func, line); ++ __DWC_DMA_FREE(size, virt_addr, dma_addr); ++} ++ ++#endif /* DEBUG_MEMORY */ +Index: linux-3.2.46/drivers/usb/host/dwc_common_port/dwc_modpow.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_common_port/dwc_modpow.c 2013-07-26 19:31:20.000000000 +0000 +@@ -0,0 +1,622 @@ ++/* Bignum routines adapted from PUTTY sources. PuTTY copyright notice follows. ++ * ++ * PuTTY is copyright 1997-2007 Simon Tatham. ++ * ++ * Portions copyright Robert de Bath, Joris van Rantwijk, Delian ++ * Delchev, Andreas Schultz, Jeroen Massar, Wez Furlong, Nicolas Barry, ++ * Justin Bradford, Ben Harris, Malcolm Smith, Ahmad Khalifa, Markus ++ * Kuhn, and CORE SDI S.A. ++ * ++ * Permission is hereby granted, free of charge, to any person ++ * obtaining a copy of this software and associated documentation files ++ * (the "Software"), to deal in the Software without restriction, ++ * including without limitation the rights to use, copy, modify, merge, ++ * publish, distribute, sublicense, and/or sell copies of the Software, ++ * and to permit persons to whom the Software is furnished to do so, ++ * subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be ++ * included in all copies or substantial portions of the Software. ++ ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, ++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF ++ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND ++ * NONINFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE ++ * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF ++ * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION ++ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. ++ * ++ */ ++ ++#ifndef CONFIG_MACH_IPMATE ++ ++ ++#include "dwc_modpow.h" ++ ++#define BIGNUM_INT_MASK 0xFFFFFFFFUL ++#define BIGNUM_TOP_BIT 0x80000000UL ++#define BIGNUM_INT_BITS 32 ++ ++ ++static void *snmalloc(size_t n, size_t size) ++{ ++ void *p; ++ size *= n; ++ if (size == 0) size = 1; ++ p = DWC_ALLOC(size); ++ return p; ++} ++ ++#define snewn(n, type) ((type *)snmalloc((n), sizeof(type))) ++#define sfree DWC_FREE ++ ++/* ++ * Usage notes: ++ * * Do not call the DIVMOD_WORD macro with expressions such as array ++ * subscripts, as some implementations object to this (see below). ++ * * Note that none of the division methods below will cope if the ++ * quotient won't fit into BIGNUM_INT_BITS. Callers should be careful ++ * to avoid this case. ++ * If this condition occurs, in the case of the x86 DIV instruction, ++ * an overflow exception will occur, which (according to a correspondent) ++ * will manifest on Windows as something like ++ * 0xC0000095: Integer overflow ++ * The C variant won't give the right answer, either. ++ */ ++ ++#define MUL_WORD(w1, w2) ((BignumDblInt)w1 * w2) ++ ++#if defined __GNUC__ && defined __i386__ ++#define DIVMOD_WORD(q, r, hi, lo, w) \ ++ __asm__("div %2" : \ ++ "=d" (r), "=a" (q) : \ ++ "r" (w), "d" (hi), "a" (lo)) ++#else ++#define DIVMOD_WORD(q, r, hi, lo, w) do { \ ++ BignumDblInt n = (((BignumDblInt)hi) << BIGNUM_INT_BITS) | lo; \ ++ q = n / w; \ ++ r = n % w; \ ++} while (0) ++#endif ++ ++// q = n / w; ++// r = n % w; ++ ++#define BIGNUM_INT_BYTES (BIGNUM_INT_BITS / 8) ++ ++#define BIGNUM_INTERNAL ++ ++static Bignum newbn(int length) ++{ ++ Bignum b = snewn(length + 1, BignumInt); ++ //if (!b) ++ //abort(); /* FIXME */ ++ DWC_MEMSET(b, 0, (length + 1) * sizeof(*b)); ++ b[0] = length; ++ return b; ++} ++ ++void freebn(Bignum b) ++{ ++ /* ++ * Burn the evidence, just in case. ++ */ ++ DWC_MEMSET(b, 0, sizeof(b[0]) * (b[0] + 1)); ++ sfree(b); ++} ++ ++/* ++ * Compute c = a * b. ++ * Input is in the first len words of a and b. ++ * Result is returned in the first 2*len words of c. ++ */ ++static void internal_mul(BignumInt *a, BignumInt *b, ++ BignumInt *c, int len) ++{ ++ int i, j; ++ BignumDblInt t; ++ ++ for (j = 0; j < 2 * len; j++) ++ c[j] = 0; ++ ++ for (i = len - 1; i >= 0; i--) { ++ t = 0; ++ for (j = len - 1; j >= 0; j--) { ++ t += MUL_WORD(a[i], (BignumDblInt) b[j]); ++ t += (BignumDblInt) c[i + j + 1]; ++ c[i + j + 1] = (BignumInt) t; ++ t = t >> BIGNUM_INT_BITS; ++ } ++ c[i] = (BignumInt) t; ++ } ++} ++ ++static void internal_add_shifted(BignumInt *number, ++ unsigned n, int shift) ++{ ++ int word = 1 + (shift / BIGNUM_INT_BITS); ++ int bshift = shift % BIGNUM_INT_BITS; ++ BignumDblInt addend; ++ ++ addend = (BignumDblInt)n << bshift; ++ ++ while (addend) { ++ addend += number[word]; ++ number[word] = (BignumInt) addend & BIGNUM_INT_MASK; ++ addend >>= BIGNUM_INT_BITS; ++ word++; ++ } ++} ++ ++/* ++ * Compute a = a % m. ++ * Input in first alen words of a and first mlen words of m. ++ * Output in first alen words of a ++ * (of which first alen-mlen words will be zero). ++ * The MSW of m MUST have its high bit set. ++ * Quotient is accumulated in the `quotient' array, which is a Bignum ++ * rather than the internal bigendian format. Quotient parts are shifted ++ * left by `qshift' before adding into quot. ++ */ ++static void internal_mod(BignumInt *a, int alen, ++ BignumInt *m, int mlen, ++ BignumInt *quot, int qshift) ++{ ++ BignumInt m0, m1; ++ unsigned int h; ++ int i, k; ++ ++ m0 = m[0]; ++ if (mlen > 1) ++ m1 = m[1]; ++ else ++ m1 = 0; ++ ++ for (i = 0; i <= alen - mlen; i++) { ++ BignumDblInt t; ++ unsigned int q, r, c, ai1; ++ ++ if (i == 0) { ++ h = 0; ++ } else { ++ h = a[i - 1]; ++ a[i - 1] = 0; ++ } ++ ++ if (i == alen - 1) ++ ai1 = 0; ++ else ++ ai1 = a[i + 1]; ++ ++ /* Find q = h:a[i] / m0 */ ++ if (h >= m0) { ++ /* ++ * Special case. ++ * ++ * To illustrate it, suppose a BignumInt is 8 bits, and ++ * we are dividing (say) A1:23:45:67 by A1:B2:C3. Then ++ * our initial division will be 0xA123 / 0xA1, which ++ * will give a quotient of 0x100 and a divide overflow. ++ * However, the invariants in this division algorithm ++ * are not violated, since the full number A1:23:... is ++ * _less_ than the quotient prefix A1:B2:... and so the ++ * following correction loop would have sorted it out. ++ * ++ * In this situation we set q to be the largest ++ * quotient we _can_ stomach (0xFF, of course). ++ */ ++ q = BIGNUM_INT_MASK; ++ } else { ++ /* Macro doesn't want an array subscript expression passed ++ * into it (see definition), so use a temporary. */ ++ BignumInt tmplo = a[i]; ++ DIVMOD_WORD(q, r, h, tmplo, m0); ++ ++ /* Refine our estimate of q by looking at ++ h:a[i]:a[i+1] / m0:m1 */ ++ t = MUL_WORD(m1, q); ++ if (t > ((BignumDblInt) r << BIGNUM_INT_BITS) + ai1) { ++ q--; ++ t -= m1; ++ r = (r + m0) & BIGNUM_INT_MASK; /* overflow? */ ++ if (r >= (BignumDblInt) m0 && ++ t > ((BignumDblInt) r << BIGNUM_INT_BITS) + ai1) q--; ++ } ++ } ++ ++ /* Subtract q * m from a[i...] */ ++ c = 0; ++ for (k = mlen - 1; k >= 0; k--) { ++ t = MUL_WORD(q, m[k]); ++ t += c; ++ c = (unsigned)(t >> BIGNUM_INT_BITS); ++ if ((BignumInt) t > a[i + k]) ++ c++; ++ a[i + k] -= (BignumInt) t; ++ } ++ ++ /* Add back m in case of borrow */ ++ if (c != h) { ++ t = 0; ++ for (k = mlen - 1; k >= 0; k--) { ++ t += m[k]; ++ t += a[i + k]; ++ a[i + k] = (BignumInt) t; ++ t = t >> BIGNUM_INT_BITS; ++ } ++ q--; ++ } ++ if (quot) ++ internal_add_shifted(quot, q, qshift + BIGNUM_INT_BITS * (alen - mlen - i)); ++ } ++} ++ ++/* ++ * Compute p % mod. ++ * The most significant word of mod MUST be non-zero. ++ * We assume that the result array is the same size as the mod array. ++ * We optionally write out a quotient if `quotient' is non-NULL. ++ * We can avoid writing out the result if `result' is NULL. ++ */ ++void bigdivmod(Bignum p, Bignum mod, Bignum result, Bignum quotient) ++{ ++ BignumInt *n, *m; ++ int mshift; ++ int plen, mlen, i, j; ++ ++ /* Allocate m of size mlen, copy mod to m */ ++ /* We use big endian internally */ ++ mlen = mod[0]; ++ m = snewn(mlen, BignumInt); ++ for (j = 0; j < mlen; j++) ++ m[j] = mod[mod[0] - j]; ++ ++ /* Shift m left to make msb bit set */ ++ for (mshift = 0; mshift < BIGNUM_INT_BITS-1; mshift++) ++ if ((m[0] << mshift) & BIGNUM_TOP_BIT) ++ break; ++ if (mshift) { ++ for (i = 0; i < mlen - 1; i++) ++ m[i] = (m[i] << mshift) | (m[i + 1] >> (BIGNUM_INT_BITS - mshift)); ++ m[mlen - 1] = m[mlen - 1] << mshift; ++ } ++ ++ plen = p[0]; ++ /* Ensure plen > mlen */ ++ if (plen <= mlen) ++ plen = mlen + 1; ++ ++ /* Allocate n of size plen, copy p to n */ ++ n = snewn(plen, BignumInt); ++ for (j = 0; j < plen; j++) ++ n[j] = 0; ++ for (j = 1; j <= (int)p[0]; j++) ++ n[plen - j] = p[j]; ++ ++ /* Main computation */ ++ internal_mod(n, plen, m, mlen, quotient, mshift); ++ ++ /* Fixup result in case the modulus was shifted */ ++ if (mshift) { ++ for (i = plen - mlen - 1; i < plen - 1; i++) ++ n[i] = (n[i] << mshift) | (n[i + 1] >> (BIGNUM_INT_BITS - mshift)); ++ n[plen - 1] = n[plen - 1] << mshift; ++ internal_mod(n, plen, m, mlen, quotient, 0); ++ for (i = plen - 1; i >= plen - mlen; i--) ++ n[i] = (n[i] >> mshift) | (n[i - 1] << (BIGNUM_INT_BITS - mshift)); ++ } ++ ++ /* Copy result to buffer */ ++ if (result) { ++ for (i = 1; i <= (int)result[0]; i++) { ++ int j = plen - i; ++ result[i] = j >= 0 ? n[j] : 0; ++ } ++ } ++ ++ /* Free temporary arrays */ ++ for (i = 0; i < mlen; i++) ++ m[i] = 0; ++ sfree(m); ++ for (i = 0; i < plen; i++) ++ n[i] = 0; ++ sfree(n); ++} ++ ++/* ++ * Simple remainder. ++ */ ++Bignum bigmod(Bignum a, Bignum b) ++{ ++ Bignum r = newbn(b[0]); ++ bigdivmod(a, b, r, NULL); ++ return r; ++} ++ ++/* ++ * Compute (base ^ exp) % mod. ++ */ ++Bignum dwc_modpow(Bignum base_in, Bignum exp, Bignum mod) ++{ ++ BignumInt *a, *b, *n, *m; ++ int mshift; ++ int mlen, i, j; ++ Bignum base, result; ++ ++ /* ++ * The most significant word of mod needs to be non-zero. It ++ * should already be, but let's make sure. ++ */ ++ //assert(mod[mod[0]] != 0); ++ ++ /* ++ * Make sure the base is smaller than the modulus, by reducing ++ * it modulo the modulus if not. ++ */ ++ base = bigmod(base_in, mod); ++ ++ /* Allocate m of size mlen, copy mod to m */ ++ /* We use big endian internally */ ++ mlen = mod[0]; ++ m = snewn(mlen, BignumInt); ++ for (j = 0; j < mlen; j++) ++ m[j] = mod[mod[0] - j]; ++ ++ /* Shift m left to make msb bit set */ ++ for (mshift = 0; mshift < BIGNUM_INT_BITS - 1; mshift++) ++ if ((m[0] << mshift) & BIGNUM_TOP_BIT) ++ break; ++ if (mshift) { ++ for (i = 0; i < mlen - 1; i++) ++ m[i] = ++ (m[i] << mshift) | (m[i + 1] >> ++ (BIGNUM_INT_BITS - mshift)); ++ m[mlen - 1] = m[mlen - 1] << mshift; ++ } ++ ++ /* Allocate n of size mlen, copy base to n */ ++ n = snewn(mlen, BignumInt); ++ i = mlen - base[0]; ++ for (j = 0; j < i; j++) ++ n[j] = 0; ++ for (j = 0; j < base[0]; j++) ++ n[i + j] = base[base[0] - j]; ++ ++ /* Allocate a and b of size 2*mlen. Set a = 1 */ ++ a = snewn(2 * mlen, BignumInt); ++ b = snewn(2 * mlen, BignumInt); ++ for (i = 0; i < 2 * mlen; i++) ++ a[i] = 0; ++ a[2 * mlen - 1] = 1; ++ ++ /* Skip leading zero bits of exp. */ ++ i = 0; ++ j = BIGNUM_INT_BITS - 1; ++ while (i < exp[0] && (exp[exp[0] - i] & (1 << j)) == 0) { ++ j--; ++ if (j < 0) { ++ i++; ++ j = BIGNUM_INT_BITS - 1; ++ } ++ } ++ ++ /* Main computation */ ++ while (i < exp[0]) { ++ while (j >= 0) { ++ internal_mul(a + mlen, a + mlen, b, mlen); ++ internal_mod(b, mlen * 2, m, mlen, NULL, 0); ++ if ((exp[exp[0] - i] & (1 << j)) != 0) { ++ internal_mul(b + mlen, n, a, mlen); ++ internal_mod(a, mlen * 2, m, mlen, NULL, 0); ++ } else { ++ BignumInt *t; ++ t = a; ++ a = b; ++ b = t; ++ } ++ j--; ++ } ++ i++; ++ j = BIGNUM_INT_BITS - 1; ++ } ++ ++ /* Fixup result in case the modulus was shifted */ ++ if (mshift) { ++ for (i = mlen - 1; i < 2 * mlen - 1; i++) ++ a[i] = ++ (a[i] << mshift) | (a[i + 1] >> ++ (BIGNUM_INT_BITS - mshift)); ++ a[2 * mlen - 1] = a[2 * mlen - 1] << mshift; ++ internal_mod(a, mlen * 2, m, mlen, NULL, 0); ++ for (i = 2 * mlen - 1; i >= mlen; i--) ++ a[i] = ++ (a[i] >> mshift) | (a[i - 1] << ++ (BIGNUM_INT_BITS - mshift)); ++ } ++ ++ /* Copy result to buffer */ ++ result = newbn(mod[0]); ++ for (i = 0; i < mlen; i++) ++ result[result[0] - i] = a[i + mlen]; ++ while (result[0] > 1 && result[result[0]] == 0) ++ result[0]--; ++ ++ /* Free temporary arrays */ ++ for (i = 0; i < 2 * mlen; i++) ++ a[i] = 0; ++ sfree(a); ++ for (i = 0; i < 2 * mlen; i++) ++ b[i] = 0; ++ sfree(b); ++ for (i = 0; i < mlen; i++) ++ m[i] = 0; ++ sfree(m); ++ for (i = 0; i < mlen; i++) ++ n[i] = 0; ++ sfree(n); ++ ++ freebn(base); ++ ++ return result; ++} ++ ++ ++#ifdef UNITTEST ++ ++static __u32 dh_p[] = { ++ 96, ++ 0xFFFFFFFF, ++ 0xFFFFFFFF, ++ 0xA93AD2CA, ++ 0x4B82D120, ++ 0xE0FD108E, ++ 0x43DB5BFC, ++ 0x74E5AB31, ++ 0x08E24FA0, ++ 0xBAD946E2, ++ 0x770988C0, ++ 0x7A615D6C, ++ 0xBBE11757, ++ 0x177B200C, ++ 0x521F2B18, ++ 0x3EC86A64, ++ 0xD8760273, ++ 0xD98A0864, ++ 0xF12FFA06, ++ 0x1AD2EE6B, ++ 0xCEE3D226, ++ 0x4A25619D, ++ 0x1E8C94E0, ++ 0xDB0933D7, ++ 0xABF5AE8C, ++ 0xA6E1E4C7, ++ 0xB3970F85, ++ 0x5D060C7D, ++ 0x8AEA7157, ++ 0x58DBEF0A, ++ 0xECFB8504, ++ 0xDF1CBA64, ++ 0xA85521AB, ++ 0x04507A33, ++ 0xAD33170D, ++ 0x8AAAC42D, ++ 0x15728E5A, ++ 0x98FA0510, ++ 0x15D22618, ++ 0xEA956AE5, ++ 0x3995497C, ++ 0x95581718, ++ 0xDE2BCBF6, ++ 0x6F4C52C9, ++ 0xB5C55DF0, ++ 0xEC07A28F, ++ 0x9B2783A2, ++ 0x180E8603, ++ 0xE39E772C, ++ 0x2E36CE3B, ++ 0x32905E46, ++ 0xCA18217C, ++ 0xF1746C08, ++ 0x4ABC9804, ++ 0x670C354E, ++ 0x7096966D, ++ 0x9ED52907, ++ 0x208552BB, ++ 0x1C62F356, ++ 0xDCA3AD96, ++ 0x83655D23, ++ 0xFD24CF5F, ++ 0x69163FA8, ++ 0x1C55D39A, ++ 0x98DA4836, ++ 0xA163BF05, ++ 0xC2007CB8, ++ 0xECE45B3D, ++ 0x49286651, ++ 0x7C4B1FE6, ++ 0xAE9F2411, ++ 0x5A899FA5, ++ 0xEE386BFB, ++ 0xF406B7ED, ++ 0x0BFF5CB6, ++ 0xA637ED6B, ++ 0xF44C42E9, ++ 0x625E7EC6, ++ 0xE485B576, ++ 0x6D51C245, ++ 0x4FE1356D, ++ 0xF25F1437, ++ 0x302B0A6D, ++ 0xCD3A431B, ++ 0xEF9519B3, ++ 0x8E3404DD, ++ 0x514A0879, ++ 0x3B139B22, ++ 0x020BBEA6, ++ 0x8A67CC74, ++ 0x29024E08, ++ 0x80DC1CD1, ++ 0xC4C6628B, ++ 0x2168C234, ++ 0xC90FDAA2, ++ 0xFFFFFFFF, ++ 0xFFFFFFFF, ++}; ++ ++static __u32 dh_a[] = { ++ 8, ++ 0xdf367516, ++ 0x86459caa, ++ 0xe2d459a4, ++ 0xd910dae0, ++ 0x8a8b5e37, ++ 0x67ab31c6, ++ 0xf0b55ea9, ++ 0x440051d6, ++}; ++ ++static __u32 dh_b[] = { ++ 8, ++ 0xded92656, ++ 0xe07a048a, ++ 0x6fa452cd, ++ 0x2df89d30, ++ 0xc75f1b0f, ++ 0x8ce3578f, ++ 0x7980a324, ++ 0x5daec786, ++}; ++ ++static __u32 dh_g[] = { ++ 1, ++ 2, ++}; ++ ++int main(void) ++{ ++ int i; ++ __u32 *k; ++ k = modpow(dh_g, dh_a, dh_p); ++ ++ printf("\n\n"); ++ for (i=0; i> 16; ++ printf("%04x %04x ", m, l); ++ if (!((i + 1)%13)) printf("\n"); ++ } ++ printf("\n\n"); ++ ++ if ((k[0] == 0x60) && (k[1] == 0x28e490e5) && (k[0x60] == 0x5a0d3d4e)) { ++ printf("PASS\n\n"); ++ } ++ else { ++ printf("FAIL\n\n"); ++ } ++ ++} ++ ++#endif /* UNITTEST */ ++ ++#endif /* CONFIG_MACH_IPMATE */ +Index: linux-3.2.46/drivers/usb/host/dwc_common_port/dwc_modpow.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_common_port/dwc_modpow.h 2013-07-26 19:31:20.000000000 +0000 +@@ -0,0 +1,26 @@ ++/* ++ * dwc_modpow.h ++ * See dwc_modpow.c for license and changes ++ */ ++#ifndef _DWC_MODPOW_H ++#define _DWC_MODPOW_H ++ ++#include "dwc_os.h" ++ ++/** @file ++ * ++ * This file defines the module exponentiation function which is only used ++ * internally by the DWC UWB modules for calculation of PKs during numeric ++ * association. The routine is taken from the PUTTY, an open source terminal ++ * emulator. The PUTTY License is preserved in the dwc_modpow.c file. ++ * ++ */ ++ ++typedef uint32_t BignumInt; ++typedef uint64_t BignumDblInt; ++typedef BignumInt *Bignum; ++ ++/* Compute modular exponentiaion */ ++extern Bignum dwc_modpow(Bignum base_in, Bignum exp, Bignum mod); ++ ++#endif /* _LINUX_BIGNUM_H */ +Index: linux-3.2.46/drivers/usb/host/dwc_common_port/dwc_notifier.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_common_port/dwc_notifier.c 2013-07-26 19:31:20.000000000 +0000 +@@ -0,0 +1,256 @@ ++#include "dwc_notifier.h" ++#include "dwc_list.h" ++ ++typedef struct dwc_observer ++{ ++ void *observer; ++ dwc_notifier_callback_t callback; ++ void *data; ++ char *notification; ++ DWC_CIRCLEQ_ENTRY(dwc_observer) list_entry; ++} observer_t; ++ ++DWC_CIRCLEQ_HEAD(observer_queue, dwc_observer); ++ ++typedef struct dwc_notifier ++{ ++ void *object; ++ struct observer_queue observers; ++ DWC_CIRCLEQ_ENTRY(dwc_notifier) list_entry; ++} notifier_t; ++ ++DWC_CIRCLEQ_HEAD(notifier_queue, dwc_notifier); ++ ++typedef struct manager ++{ ++ dwc_workq_t *wq; ++ dwc_mutex_t *mutex; ++ struct notifier_queue notifiers; ++} manager_t; ++ ++static manager_t *manager = NULL; ++ ++static void create_manager(void) ++{ ++ manager = DWC_ALLOC(sizeof(manager_t)); ++ DWC_CIRCLEQ_INIT(&manager->notifiers); ++ manager->wq = DWC_WORKQ_ALLOC("DWC Notification WorkQ"); ++} ++ ++static void free_manager(void) ++{ ++ DWC_WORKQ_FREE(manager->wq); ++ /* All notifiers must have unregistered themselves before this module ++ * can be removed. Hitting this assertion indicates a programmer ++ * error. */ ++ DWC_ASSERT(DWC_CIRCLEQ_EMPTY(&manager->notifiers), "Notification manager being freed before all notifiers have been removed"); ++ DWC_FREE(manager); ++} ++ ++#ifdef DEBUG ++static void dump_manager(void) ++{ ++ notifier_t *n; ++ observer_t *o; ++ DWC_ASSERT(manager, "Notification manager not found"); ++ DWC_DEBUG("List of all notifiers and observers:"); ++ DWC_CIRCLEQ_FOREACH(n, &manager->notifiers, list_entry) { ++ DWC_DEBUG("Notifier %p has observers:", n->object); ++ DWC_CIRCLEQ_FOREACH(o, &n->observers, list_entry) { ++ DWC_DEBUG(" %p watching %s", o->observer, o->notification); ++ } ++ } ++} ++#else ++#define dump_manager(...) ++#endif ++ ++static observer_t *alloc_observer(void *observer, char *notification, dwc_notifier_callback_t callback, void *data) ++{ ++ observer_t *new_observer = DWC_ALLOC(sizeof(observer_t)); ++ DWC_CIRCLEQ_INIT_ENTRY(new_observer, list_entry); ++ new_observer->observer = observer; ++ new_observer->notification = notification; ++ new_observer->callback = callback; ++ new_observer->data = data; ++ return new_observer; ++} ++ ++static void free_observer(observer_t *observer) ++{ ++ DWC_FREE(observer); ++} ++ ++static notifier_t *alloc_notifier(void *object) ++{ ++ notifier_t *notifier; ++ ++ if (!object) { ++ return NULL; ++ } ++ ++ notifier = DWC_ALLOC(sizeof(notifier_t)); ++ DWC_CIRCLEQ_INIT(¬ifier->observers); ++ DWC_CIRCLEQ_INIT_ENTRY(notifier, list_entry); ++ ++ notifier->object = object; ++ return notifier; ++} ++ ++static void free_notifier(notifier_t *notifier) ++{ ++ observer_t *observer; ++ DWC_CIRCLEQ_FOREACH(observer, ¬ifier->observers, list_entry) { ++ free_observer(observer); ++ } ++ DWC_FREE(notifier); ++} ++ ++static notifier_t *find_notifier(void *object) ++{ ++ notifier_t *notifier; ++ if (!object) { ++ return NULL; ++ } ++ DWC_ASSERT(manager, "Notification manager not found"); ++ DWC_CIRCLEQ_FOREACH(notifier, &manager->notifiers, list_entry) { ++ if (notifier->object == object) { ++ return notifier; ++ } ++ } ++ return NULL; ++} ++ ++void dwc_alloc_notification_manager(void) ++{ ++ create_manager(); ++} ++ ++void dwc_free_notification_manager(void) ++{ ++ free_manager(); ++} ++ ++dwc_notifier_t *dwc_register_notifier(void *object) ++{ ++ notifier_t *notifier = find_notifier(object); ++ DWC_ASSERT(manager, "Notification manager not found"); ++ if (notifier) { ++ DWC_ERROR("Notifier %p is already registered", object); ++ return NULL; ++ } ++ ++ notifier = alloc_notifier(object); ++ DWC_CIRCLEQ_INSERT_TAIL(&manager->notifiers, notifier, list_entry); ++ ++ ++ DWC_INFO("Notifier %p registered", object); ++ dump_manager(); ++ ++ return notifier; ++} ++ ++void dwc_unregister_notifier(dwc_notifier_t *notifier) ++{ ++ DWC_ASSERT(manager, "Notification manager not found"); ++ if (!DWC_CIRCLEQ_EMPTY(¬ifier->observers)) { ++ observer_t *o; ++ DWC_ERROR("Notifier %p has active observers when removing", notifier->object); ++ DWC_CIRCLEQ_FOREACH(o, ¬ifier->observers, list_entry) { ++ DWC_DEBUG(" %p watching %s", o->observer, o->notification); ++ } ++ DWC_ASSERT(DWC_CIRCLEQ_EMPTY(¬ifier->observers), "Notifier %p has active observers when removing", notifier); ++ } ++ ++ DWC_CIRCLEQ_REMOVE_INIT(&manager->notifiers, notifier, list_entry); ++ free_notifier(notifier); ++ ++ DWC_INFO("Notifier unregistered"); ++ dump_manager(); ++} ++ ++/* Add an observer to observe the notifier for a particular state, event, or notification. */ ++int dwc_add_observer(void *observer, void *object, char *notification, dwc_notifier_callback_t callback, void *data) ++{ ++ notifier_t *notifier = find_notifier(object); ++ observer_t *new_observer; ++ if (!notifier) { ++ DWC_ERROR("Notifier %p is not found when adding observer", object); ++ return -1; ++ } ++ ++ new_observer = alloc_observer(observer, notification, callback, data); ++ ++ DWC_CIRCLEQ_INSERT_TAIL(¬ifier->observers, new_observer, list_entry); ++ ++ DWC_INFO("Added observer %p to notifier %p observing notification %s, callback=%p, data=%p", ++ observer, object, notification, callback, data); ++ ++ dump_manager(); ++ return 0; ++} ++ ++int dwc_remove_observer(void *observer) ++{ ++ notifier_t *n; ++ DWC_ASSERT(manager, "Notification manager not found"); ++ DWC_CIRCLEQ_FOREACH(n, &manager->notifiers, list_entry) { ++ observer_t *o; ++ observer_t *o2; ++ DWC_CIRCLEQ_FOREACH_SAFE(o, o2, &n->observers, list_entry) { ++ if (o->observer == observer) { ++ DWC_CIRCLEQ_REMOVE_INIT(&n->observers, o, list_entry); ++ DWC_INFO("Removing observer %p from notifier %p watching notification %s:", ++ o->observer, n->object, o->notification); ++ free_observer(o); ++ } ++ } ++ } ++ ++ dump_manager(); ++ return 0; ++} ++ ++typedef struct callback_data ++{ ++ dwc_notifier_callback_t cb; ++ void *observer; ++ void *data; ++ void *object; ++ void *notification; ++ void *notification_data; ++} cb_data_t; ++ ++static void cb_task(void *data) ++{ ++ cb_data_t *cb = (cb_data_t *)data; ++ cb->cb(cb->object, cb->notification, cb->observer, cb->notification_data, cb->data); ++ DWC_FREE(cb); ++} ++ ++void dwc_notify(dwc_notifier_t *notifier, char *notification, void *notification_data) ++{ ++ observer_t *o; ++ DWC_ASSERT(manager, "Notification manager not found"); ++ DWC_CIRCLEQ_FOREACH(o, ¬ifier->observers, list_entry) { ++ int len = DWC_STRLEN(notification); ++ if (DWC_STRLEN(o->notification) != len) { ++ continue; ++ } ++ ++ if (DWC_STRNCMP(o->notification, notification, len) == 0) { ++ cb_data_t *cb_data = DWC_ALLOC(sizeof(cb_data_t)); ++ cb_data->cb = o->callback; ++ cb_data->observer = o->observer; ++ cb_data->data = o->data; ++ cb_data->object = notifier->object; ++ cb_data->notification = notification; ++ cb_data->notification_data = notification_data; ++ DWC_DEBUG("Observer found %p for notification %s", o->observer, notification); ++ DWC_WORKQ_SCHEDULE(manager->wq, cb_task, cb_data, ++ "Notify callback from %p for Notification %s, to observer %p", ++ cb_data->object, notification, cb_data->observer); ++ } ++ } ++} ++ +Index: linux-3.2.46/drivers/usb/host/dwc_common_port/dwc_notifier.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_common_port/dwc_notifier.h 2013-07-26 19:31:20.000000000 +0000 +@@ -0,0 +1,112 @@ ++ ++#ifndef __DWC_NOTIFIER_H__ ++#define __DWC_NOTIFIER_H__ ++ ++#include "dwc_os.h" ++ ++/** @file ++ * ++ * A simple implementation of the Observer pattern. Any "module" can ++ * register as an observer or notifier. The notion of "module" is abstract and ++ * can mean anything used to identify either an observer or notifier. Usually ++ * it will be a pointer to a data structure which contains some state, ie an ++ * object. ++ * ++ * Before any notifiers can be added, the global notification manager must be ++ * brought up with dwc_alloc_notification_manager(). ++ * dwc_free_notification_manager() will bring it down and free all resources. ++ * These would typically be called upon module load and unload. The ++ * notification manager is a single global instance that handles all registered ++ * observable modules and observers so this should be done only once. ++ * ++ * A module can be observable by using Notifications to publicize some general ++ * information about it's state or operation. It does not care who listens, or ++ * even if anyone listens, or what they do with the information. The observable ++ * modules do not need to know any information about it's observers or their ++ * interface, or their state or data. ++ * ++ * Any module can register to emit Notifications. It should publish a list of ++ * notifications that it can emit and their behavior, such as when they will get ++ * triggered, and what information will be provided to the observer. Then it ++ * should register itself as an observable module. See dwc_register_notifier(). ++ * ++ * Any module can observe any observable, registered module, provided it has a ++ * handle to the other module and knows what notifications to observe. See ++ * dwc_add_observer(). ++ * ++ * A function of type dwc_notifier_callback_t is called whenever a notification ++ * is triggered with one or more observers observing it. This function is ++ * called in it's own process so it may sleep or block if needed. It is ++ * guaranteed to be called sometime after the notification has occurred and will ++ * be called once per each time the notification is triggered. It will NOT be ++ * called in the same process context used to trigger the notification. ++ * ++ * @section Limitiations ++ * ++ * Keep in mind that Notifications that can be triggered in rapid sucession may ++ * schedule too many processes too handle. Be aware of this limitation when ++ * designing to use notifications, and only add notifications for appropriate ++ * observable information. ++ * ++ * Also Notification callbacks are not synchronous. If you need to synchronize ++ * the behavior between module/observer you must use other means. And perhaps ++ * that will mean Notifications are not the proper solution. ++ */ ++ ++struct dwc_notifier; ++typedef struct dwc_notifier dwc_notifier_t; ++ ++/** The callback function must be of this type. ++ * ++ * @param object This is the object that is being observed. ++ * @param notification This is the notification that was triggered. ++ * @param observer This is the observer ++ * @param notification_data This is notification-specific data that the notifier ++ * has included in this notification. The value of this should be published in ++ * the documentation of the observable module with the notifications. ++ * @param user_data This is any custom data that the observer provided when ++ * adding itself as an observer to the notification. */ ++typedef void (*dwc_notifier_callback_t)(void *object, char *notification, void *observer, void *notification_data, void *user_data); ++ ++/** Brings up the notification manager. */ ++extern void dwc_alloc_notification_manager(void); ++/** Brings down the notification manager. */ ++extern void dwc_free_notification_manager(void); ++ ++/** This function register an observable module. A dwc_notifier_t object is ++ * returned to the observable module. This is an opaque object that is used by ++ * the observable module to trigger notifications. This object should only be ++ * accessible to functions that are authorized to trigger notifications for this ++ * module. Observers do not need this object. */ ++extern dwc_notifier_t *dwc_register_notifier(void *object); ++ ++/** This function unregister an observable module. All observers have to be ++ * removed prior to unregistration. */ ++extern void dwc_unregister_notifier(dwc_notifier_t *notifier); ++ ++/** Add a module as an observer to the observable module. The observable module ++ * needs to have previously registered with the notification manager. ++ * ++ * @param observer The observer module ++ * @param object The module to observe ++ * @param notification The notification to observe ++ * @param callback The callback function to call ++ * @param user_data Any additional user data to pass into the callback function */ ++extern int dwc_add_observer(void *observer, void *object, char *notification, dwc_notifier_callback_t callback, void *user_data); ++ ++/** Removes the specified observer from all notifications that it is currently ++ * observing. */ ++extern int dwc_remove_observer(void *observer); ++ ++/** This function triggers a Notification. It should be called by the ++ * observable module, or any module or library which the observable module ++ * allows to trigger notification on it's behalf. Such as the dwc_cc_t. ++ * ++ * dwc_notify is a non-blocking function. Callbacks are scheduled called in ++ * their own process context for each trigger. Callbacks can be blocking. ++ * dwc_notify can be called from interrupt context if needed. ++ * ++ */ ++void dwc_notify(dwc_notifier_t *notifier, char *notification, void *notification_data); ++ ++#endif /* __DWC_NOTIFIER_H__ */ +Index: linux-3.2.46/drivers/usb/host/dwc_common_port/dwc_os.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_common_port/dwc_os.h 2013-07-26 19:31:20.000000000 +0000 +@@ -0,0 +1,924 @@ ++/* ========================================================================= ++ * $File: //dwh/usb_iip/dev/software/dwc_common_port/dwc_os.h $ ++ * $Revision: #2 $ ++ * $Date: 2009/04/02 $ ++ * $Change: 1224130 $ ++ * ++ * Synopsys Portability Library Software and documentation ++ * (hereinafter, "Software") is an Unsupported proprietary work of ++ * Synopsys, Inc. unless otherwise expressly agreed to in writing ++ * between Synopsys and you. ++ * ++ * The Software IS NOT an item of Licensed Software or Licensed Product ++ * under any End User Software License Agreement or Agreement for ++ * Licensed Product with Synopsys or any supplement thereto. You are ++ * permitted to use and redistribute this Software in source and binary ++ * forms, with or without modification, provided that redistributions ++ * of source code must retain this notice. You may not view, use, ++ * disclose, copy or distribute this file or any information contained ++ * herein except pursuant to this license grant from Synopsys. If you ++ * do not agree with this notice, including the disclaimer below, then ++ * you are not authorized to use the Software. ++ * ++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" ++ * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT ++ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ++ * FOR A PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL ++ * SYNOPSYS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, ++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, ++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR ++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY ++ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE ++ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH ++ * DAMAGE. ++ * ========================================================================= */ ++#ifndef _DWC_OS_H_ ++#define _DWC_OS_H_ ++ ++/** @file ++ * ++ * DWC portability library, low level os-wrapper functions ++ * ++ */ ++ ++/* These basic types need to be defined by some OS header file or custom header ++ * file for your specific target architecture. ++ * ++ * uint8_t, int8_t, uint16_t, int16_t, uint32_t, int32_t, uint64_t, int64_t ++ * ++ * Any custom or alternate header file must be added and enabled here. ++ */ ++ ++#ifdef DWC_LINUX ++# include ++# ifdef CONFIG_DEBUG_MUTEXES ++# include ++# endif ++#else ++# include ++#endif ++ ++ ++/** @name Primitive Types and Values */ ++ ++/** We define a boolean type for consistency. Can be either YES or NO */ ++typedef uint8_t dwc_bool_t; ++#define YES 1 ++#define NO 0 ++ ++/** @todo make them positive and return the negative error code */ ++/** @name Error Codes */ ++#define DWC_E_INVALID 1001 ++#define DWC_E_NO_MEMORY 1002 ++#define DWC_E_NO_DEVICE 1003 ++#define DWC_E_NOT_SUPPORTED 1004 ++#define DWC_E_TIMEOUT 1005 ++#define DWC_E_BUSY 1006 ++#define DWC_E_AGAIN 1007 ++#define DWC_E_RESTART 1008 ++#define DWC_E_ABORT 1009 ++#define DWC_E_SHUTDOWN 1010 ++#define DWC_E_NO_DATA 1011 ++#define DWC_E_DISCONNECT 2000 ++#define DWC_E_UNKNOWN 3000 ++#define DWC_E_NO_STREAM_RES 4001 ++#define DWC_E_COMMUNICATION 4002 ++#define DWC_E_OVERFLOW 4003 ++#define DWC_E_PROTOCOL 4004 ++#define DWC_E_IN_PROGRESS 4005 ++#define DWC_E_PIPE 4006 ++#define DWC_E_IO 4007 ++#define DWC_E_NO_SPACE 4008 ++ ++/** @name Tracing/Logging Functions ++ * ++ * These function provide the capability to add tracing, debugging, and error ++ * messages, as well exceptions as assertions. The WUDEV uses these ++ * extensively. These could be logged to the main console, the serial port, an ++ * internal buffer, etc. These functions could also be no-op if they are too ++ * expensive on your system. By default undefining the DEBUG macro already ++ * no-ops some of these functions. */ ++ ++#include ++ ++/** Returns non-zero if in interrupt context. */ ++extern dwc_bool_t DWC_IN_IRQ(void); ++#define dwc_in_irq DWC_IN_IRQ ++ ++/** Returns "IRQ" if DWC_IN_IRQ is true. */ ++static inline char *dwc_irq(void) { ++ return DWC_IN_IRQ() ? "IRQ" : ""; ++} ++ ++/** ++ * A vprintf() clone. Just call vprintf if you've got it. ++ */ ++extern void DWC_VPRINTF(char *format, va_list args); ++#define dwc_vprintf DWC_VPRINTF ++ ++/** ++ * A vsnprintf() clone. Just call vprintf if you've got it. ++ */ ++extern int DWC_VSNPRINTF(char *str, int size, char *format, va_list args); ++#define dwc_vsnprintf DWC_VSNPRINTF ++ ++/** ++ * printf() clone. Just call printf if you've go it. ++ */ ++extern void DWC_PRINTF(char *format, ...) ++/* This provides compiler level static checking of the parameters if you're ++ * using GCC. */ ++#ifdef __GNUC__ ++ __attribute__ ((format(printf, 1, 2))); ++#else ++ ; ++#endif ++#define dwc_printf DWC_PRINTF ++ ++/** ++ * sprintf() clone. Just call sprintf if you've got it. ++ */ ++extern int DWC_SPRINTF(char *string, char *format, ...) ++#ifdef __GNUC__ ++ __attribute__ ((format(printf, 2, 3))); ++#else ++ ; ++#endif ++#define dwc_sprintf DWC_SPRINTF ++ ++/** ++ * snprintf() clone. Just call snprintf if you've got it. ++ */ ++extern int DWC_SNPRINTF(char *string, int size, char *format, ...) ++#ifdef __GNUC__ ++ __attribute__ ((format(printf, 3, 4))); ++#else ++ ; ++#endif ++#define dwc_snprintf DWC_SNPRINTF ++ ++/** ++ * Prints a WARNING message. On systems that don't differentiate between ++ * warnings and regular log messages, just print it. Indicates that something ++ * may be wrong with the driver. Works like printf(). ++ * ++ * Use the DWC_WARN macro to call this function. ++ */ ++extern void __DWC_WARN(char *format, ...) ++#ifdef __GNUC__ ++ __attribute__ ((format(printf, 1, 2))); ++#else ++ ; ++#endif ++ ++/** ++ * Prints an error message. On systems that don't differentiate between errors ++ * and regular log messages, just print it. Indicates that something went wrong ++ * with the driver, but it can be recovered from. Works like printf(). ++ * ++ * Use the DWC_ERROR macro to call this function. ++ */ ++extern void __DWC_ERROR(char *format, ...) ++#ifdef __GNUC__ ++ __attribute__ ((format(printf, 1, 2))); ++#else ++ ; ++#endif ++ ++/** ++ * Prints an exception error message and takes some user-defined action such as ++ * print out a backtrace or trigger a breakpoint. Indicates that something went ++ * abnormally wrong with the driver such as programmer error, or other ++ * exceptional condition. It should not be ignored so even on systems without ++ * printing capability, some action should be taken to notify the developer of ++ * it. Works like printf(). ++ */ ++extern void DWC_EXCEPTION(char *format, ...) ++#ifdef __GNUC__ ++ __attribute__ ((format(printf, 1, 2))); ++#else ++ ; ++#endif ++#define dwc_exception DWC_EXCEPTION ++ ++#ifdef DEBUG ++/** ++ * Prints out a debug message. Used for logging/trace messages. ++ * ++ * Use the DWC_DEBUG macro to call this function ++ */ ++extern void __DWC_DEBUG(char *format, ...) ++#ifdef __GNUC__ ++ __attribute__ ((format(printf, 1, 2))); ++#else ++ ; ++#endif ++#else ++#define __DWC_DEBUG printk ++#endif ++ ++/** ++ * Prints out a Debug message. ++ */ ++#define DWC_DEBUG(_format, _args...) __DWC_DEBUG("DEBUG:%s:%s: " _format "\n", __func__, dwc_irq(), ## _args) ++#define dwc_debug DWC_DEBUG ++/** ++ * Prints out an informative message. ++ */ ++#define DWC_INFO(_format, _args...) DWC_PRINTF("INFO:%s: " _format "\n", dwc_irq(), ## _args) ++#define dwc_info DWC_INFO ++/** ++ * Prints out a warning message. ++ */ ++#define DWC_WARN(_format, _args...) __DWC_WARN("WARN:%s:%s:%d: " _format "\n", dwc_irq(), __func__, __LINE__, ## _args) ++#define dwc_warn DWC_WARN ++/** ++ * Prints out an error message. ++ */ ++#define DWC_ERROR(_format, _args...) __DWC_ERROR("ERROR:%s:%s:%d: " _format "\n", dwc_irq(), __func__, __LINE__, ## _args) ++#define dwc_error DWC_ERROR ++ ++#define DWC_PROTO_ERROR(_format, _args...) __DWC_WARN("ERROR:%s:%s:%d: " _format "\n", dwc_irq(), __func__, __LINE__, ## _args) ++#define dwc_proto_error DWC_PROTO_ERROR ++ ++#ifdef DEBUG ++/** Prints out a exception error message if the _expr expression fails. Disabled ++ * if DEBUG is not enabled. */ ++#define DWC_ASSERT(_expr, _format, _args...) if (!(_expr)) { DWC_EXCEPTION("%s:%s:%d: " _format "\n", dwc_irq(), __FILE__, __LINE__, ## _args); } ++#else ++#define DWC_ASSERT(_x...) ++#endif ++#define dwc_assert DWC_ASSERT ++ ++/** @name Byter Ordering ++ * The following functions are for conversions between processor's byte ordering ++ * and specific ordering you want. ++ */ ++ ++/** Converts 32 bit data in CPU byte ordering to little endian. */ ++extern uint32_t DWC_CPU_TO_LE32(void *p); ++#define dwc_cpu_to_le32 DWC_CPU_TO_LE32 ++/** Converts 32 bit data in CPU byte orderint to big endian. */ ++extern uint32_t DWC_CPU_TO_BE32(void *p); ++#define dwc_cpu_to_be32 DWC_CPU_TO_BE32 ++ ++/** Converts 32 bit little endian data to CPU byte ordering. */ ++extern uint32_t DWC_LE32_TO_CPU(void *p); ++#define dwc_le32_to_cpu DWC_LE32_TO_CPU ++/** Converts 32 bit big endian data to CPU byte ordering. */ ++extern uint32_t DWC_BE32_TO_CPU(void *p); ++#define dwc_be32_to_cpu DWC_BE32_TO_CPU ++ ++/** Converts 16 bit data in CPU byte ordering to little endian. */ ++extern uint16_t DWC_CPU_TO_LE16(void *p); ++#define dwc_cpu_to_le16 DWC_CPU_TO_LE16 ++/** Converts 16 bit data in CPU byte orderint to big endian. */ ++extern uint16_t DWC_CPU_TO_BE16(void *p); ++#define dwc_cpu_to_be16 DWC_CPU_TO_BE16 ++ ++/** Converts 16 bit little endian data to CPU byte ordering. */ ++extern uint16_t DWC_LE16_TO_CPU(void *p); ++#define dwc_le16_to_cpu DWC_LE16_TO_CPU ++/** Converts 16 bit bi endian data to CPU byte ordering. */ ++extern uint16_t DWC_BE16_TO_CPU(void *p); ++#define dwc_be16_to_cpu DWC_BE16_TO_CPU ++ ++/** @name Register Read/Write ++ * ++ * The following five functions should be implemented to read/write registers of ++ * 32-bit and 64-bit sizes. All modules use this to read/write register values. ++ * The reg value is a pointer to the register calculated from the void *base ++ * variable passed into the driver when it is started. */ ++ ++/** Reads the content of a 32-bit register. */ ++extern uint32_t DWC_READ_REG32(uint32_t volatile *reg); ++#define dwc_read_reg32 DWC_READ_REG32 ++/** Reads the content of a 64-bit register. */ ++extern uint64_t DWC_READ_REG64(uint64_t volatile *reg); ++#define dwc_read_reg64 DWC_READ_REG64 ++/** Writes to a 32-bit register. */ ++extern void DWC_WRITE_REG32(uint32_t volatile *reg, uint32_t value); ++#define dwc_write_reg32 DWC_WRITE_REG32 ++/** Writes to a 64-bit register. */ ++extern void DWC_WRITE_REG64(uint64_t volatile *reg, uint64_t value); ++#define dwc_write_reg64 DWC_WRITE_REG64 ++/** ++ * Modify bit values in a register. Using the ++ * algorithm: (reg_contents & ~clear_mask) | set_mask. ++ */ ++extern void DWC_MODIFY_REG32(uint32_t volatile *reg, uint32_t clear_mask, uint32_t set_mask); ++#define dwc_modify_reg32 DWC_MODIFY_REG32 ++ ++/** @cond */ ++ ++/** @name Some convenience MACROS used internally. Define DEBUG_REGS to log the ++ * register writes. */ ++ ++#ifdef DEBUG_REGS ++ ++#define dwc_define_read_write_reg_n(_reg,_container_type) \ ++static inline uint32_t dwc_read_##_reg##_n(_container_type *container, int num) { \ ++ return DWC_READ_REG32(&container->regs->_reg[num]); \ ++} \ ++static inline void dwc_write_##_reg##_n(_container_type *container, int num, uint32_t data) { \ ++ DWC_DEBUG("WRITING %8s[%d]: %p: %08x", #_reg, num, &(((uint32_t*)container->regs->_reg)[num]), data); \ ++ DWC_WRITE_REG32(&(((uint32_t*)container->regs->_reg)[num]), data); \ ++} ++ ++#define dwc_define_read_write_reg(_reg,_container_type) \ ++static inline uint32_t dwc_read_##_reg(_container_type *container) { \ ++ return DWC_READ_REG32(&container->regs->_reg); \ ++} \ ++static inline void dwc_write_##_reg(_container_type *container, uint32_t data) { \ ++ DWC_DEBUG("WRITING %11s: %p: %08x", #_reg, &container->regs->_reg, data); \ ++ DWC_WRITE_REG32(&container->regs->_reg, data); \ ++} ++ ++#else ++ ++#define dwc_define_read_write_reg_n(_reg,_container_type) \ ++static inline uint32_t dwc_read_##_reg##_n(_container_type *container, int num) { \ ++ return DWC_READ_REG32(&container->regs->_reg[num]); \ ++} \ ++static inline void dwc_write_##_reg##_n(_container_type *container, int num, uint32_t data) { \ ++ DWC_WRITE_REG32(&(((uint32_t*)container->regs->_reg)[num]), data); \ ++} ++ ++#define dwc_define_read_write_reg(_reg,_container_type) \ ++static inline uint32_t dwc_read_##_reg(_container_type *container) { \ ++ return DWC_READ_REG32(&container->regs->_reg); \ ++} \ ++static inline void dwc_write_##_reg(_container_type *container, uint32_t data) { \ ++ DWC_WRITE_REG32(&container->regs->_reg, data); \ ++} ++ ++#endif ++ ++/** @endcond */ ++ ++ ++/** @name Crypto Functions ++ * ++ * These are the low-level cryptographic functions used by the driver. */ ++ ++/** Perform AES CBC */ ++extern int DWC_AES_CBC(uint8_t *message, uint32_t messagelen, uint8_t *key, uint32_t keylen, uint8_t iv[16], uint8_t *out); ++#define dwc_aes_cbc DWC_AES_CBC ++/** Fill the provided buffer with random bytes. These should be cryptographic grade random numbers. */ ++extern void DWC_RANDOM_BYTES(uint8_t *buffer, uint32_t length); ++#define dwc_random_bytes DWC_RANDOM_BYTES ++/** Perform the SHA-256 hash function */ ++extern int DWC_SHA256(uint8_t *message, uint32_t len, uint8_t *out); ++#define dwc_sha256 DWC_SHA256 ++/** Calculated the HMAC-SHA256 */ ++extern int DWC_HMAC_SHA256(uint8_t *message, uint32_t messagelen, uint8_t *key, uint32_t keylen, uint8_t *out); ++#define dwc_hmac_sha256 DWC_HMAC_SHA256 ++ ++ ++/** @name Memory Allocation ++ * ++ * These function provide access to memory allocation. There are only 2 DMA ++ * functions and 3 Regular memory functions that need to be implemented. None ++ * of the memory debugging routines need to be implemented. The allocation ++ * routines all ZERO the contents of the memory. ++ * ++ * Defining DEBUG_MEMORY turns on memory debugging and statistic gathering. ++ * This checks for memory leaks, keeping track of alloc/free pairs. It also ++ * keeps track of how much memory the driver is using at any given time. */ ++ ++#define DWC_PAGE_SIZE 4096 ++#define DWC_PAGE_OFFSET(addr) (((uint32_t)addr) & 0xfff) ++#define DWC_PAGE_ALIGNED(addr) ((((uint32_t)addr) & 0xfff) == 0) ++ ++#define DWC_INVALID_DMA_ADDR 0x0 ++ ++typedef uint32_t dwc_dma_t; ++ ++/** @todo these functions will be added in the future */ ++#if 0 ++/** ++ * Creates a DMA pool from which you can allocate DMA buffers. Buffers ++ * allocated from this pool will be guaranteed to meet the size, alignment, and ++ * boundary requirements specified. ++ * ++ * @param[in] size Specifies the size of the buffers that will be allocated from ++ * this pool. ++ * @param[in] align Specifies the byte alignment requirements of the buffers ++ * allocated from this pool. Must be a power of 2. ++ * @param[in] boundary Specifies the N-byte boundary that buffers allocated from ++ * this pool must not cross. ++ * ++ * @returns A pointer to an internal opaque structure which is not to be ++ * accessed outside of these library functions. Use this handle to specify ++ * which pools to allocate/free DMA buffers from and also to destroy the pool, ++ * when you are done with it. ++ */ ++extern dwc_pool_t *DWC_DMA_POOL_CREATE(uint32_t size, uint32_t align, uint32_t boundary); ++/** ++ * Destroy a DMA pool. All buffers allocated from that pool must be freed first. ++ */ ++extern void DWC_DMA_POOL_DESTROY(dwc_pool_t *pool); ++/** ++ * Allocate a buffer from the specified DMA pool and zeros its contents. ++ */ ++extern void *DWC_DMA_POOL_ALLOC(dwc_pool_t *pool, uint64_t *dma_addr); ++/** ++ * Free a previously allocated buffer from the DMA pool. ++ */ ++extern void DWC_DMA_POOL_FREE(dwc_pool_t *pool, void *vaddr, void *daddr); ++#endif ++ ++ ++/** Allocates a DMA capable buffer and zeroes its contents. */ ++extern void *__DWC_DMA_ALLOC(uint32_t size, dwc_dma_t *dma_addr); ++ ++/** Allocates a DMA capable buffer and zeroes its contents in atomic contest */ ++extern void *__DWC_DMA_ALLOC_ATOMIC(uint32_t size, dwc_dma_t *dma_addr); ++ ++/** Frees a previosly allocated buffer. */ ++extern void __DWC_DMA_FREE(uint32_t size, void *virt_addr, dwc_dma_t dma_addr); ++ ++/** Allocates a block of memory and zeroes its contents. */ ++extern void *__DWC_ALLOC(uint32_t size); ++ ++/** Allocates a block of memory and zeroes its contents, in an atomic manner ++ * which can be used inside interrupt context. The size should be sufficiently ++ * small, a few KB at most, such that failures are not likely to occur. Can just call ++ * __DWC_ALLOC if it is atomic. */ ++extern void *__DWC_ALLOC_ATOMIC(uint32_t size); ++ ++/** Frees a previously allocated buffer. */ ++extern void __DWC_FREE(void *addr); ++ ++#ifndef DEBUG_MEMORY ++ ++#define DWC_ALLOC(_size_) __DWC_ALLOC(_size_) ++#define DWC_ALLOC_ATOMIC(_size_) __DWC_ALLOC_ATOMIC(_size_) ++#define DWC_FREE(_addr_) __DWC_FREE(_addr_) ++#define DWC_DMA_ALLOC(_size_,_dma_) __DWC_DMA_ALLOC(_size_,_dma_) ++#define DWC_DMA_ALLOC_ATOMIC(_size_,_dma_) __DWC_DMA_ALLOC_ATOMIC(_size_,_dma_) ++#define DWC_DMA_FREE(_size_,_virt_,_dma_) __DWC_DMA_FREE(_size_,_virt_,_dma_) ++ ++#else ++ ++extern void *dwc_alloc_debug(uint32_t size, char const *func, int line); ++extern void *dwc_alloc_atomic_debug(uint32_t size, char const *func, int line); ++extern void dwc_free_debug(void *addr, char const *func, int line); ++extern void *dwc_dma_alloc_debug(uint32_t size, dwc_dma_t *dma_addr, char const *func, int line); ++extern void *dwc_dma_alloc_atomic_debug(uint32_t size, dwc_dma_t *dma_addr, char const *func, int line); ++extern void dwc_dma_free_debug(uint32_t size, void *virt_addr, dwc_dma_t dma_addr, char const *func, int line); ++ ++extern void dwc_memory_debug_start(void); ++extern void dwc_memory_debug_stop(void); ++extern void dwc_memory_debug_report(void); ++ ++#define DWC_ALLOC(_size_) (dwc_alloc_debug(_size_, __func__, __LINE__)) ++#define DWC_ALLOC_ATOMIC(_size_) (dwc_alloc_atomic_debug(_size_, __func__, __LINE__)) ++#define DWC_FREE(_addr_) (dwc_free_debug(_addr_, __func__, __LINE__)) ++#define DWC_DMA_ALLOC(_size_,_dma_) dwc_dma_alloc_debug(_size_, _dma_, __func__, __LINE__) ++#define DWC_DMA_ALLOC_ATOMIC(_size_,_dma_) dwc_dma_alloc_atomic_debug(_size_, _dma_, __func__, __LINE__) ++#define DWC_DMA_FREE(_size_,_virt_,_dma_) dwc_dma_free_debug(_size_, _virt_, _dma_, __func__, __LINE__) ++ ++#endif /* DEBUG_MEMORY */ ++ ++#define dwc_alloc DWC_ALLOC ++#define dwc_alloc_atomic DWC_ALLOC_ATOMIC ++#define dwc_free DWC_FREE ++#define dwc_dma_alloc DWC_DMA_ALLOC ++#define dwc_dma_alloc_atomic DWC_DMA_ALLOC_ATOMIC ++#define dwc_dma_free DWC_DMA_FREE ++ ++ ++/** @name Memory and String Processing */ ++ ++/** memset() clone */ ++extern void *DWC_MEMSET(void *dest, uint8_t byte, uint32_t size); ++#define dwc_memset DWC_MEMSET ++/** memcpy() clone */ ++extern void *DWC_MEMCPY(void *dest, void const *src, uint32_t size); ++#define dwc_memcpy DWC_MEMCPY ++/** memmove() clone */ ++extern void *DWC_MEMMOVE(void *dest, void *src, uint32_t size); ++#define dwc_memmove DWC_MEMMOVE ++/** memcmp() clone */ ++extern int DWC_MEMCMP(void *m1, void *m2, uint32_t size); ++#define dwc_memcmp DWC_MEMCMP ++/** strcmp() clone */ ++extern int DWC_STRCMP(void *s1, void *s2); ++#define dwc_strcmp DWC_STRCMP ++/** strncmp() clone */ ++extern int DWC_STRNCMP(void *s1, void *s2, uint32_t size); ++#define dwc_strncmp DWC_STRNCMP ++/** strlen() clone, for NULL terminated ASCII strings */ ++extern int DWC_STRLEN(char const *str); ++#define dwc_strlen DWC_STRLEN ++/** strcpy() clone, for NULL terminated ASCII strings */ ++extern char *DWC_STRCPY(char *to, const char *from); ++#define dwc_strcpy DWC_STRCPY ++ ++/** strdup() clone. If you wish to use memory allocation debugging, this ++ * implementation of strdup should use the DWC_* memory routines instead of ++ * calling a predefined strdup. Otherwise the memory allocated by this routine ++ * will not be seen by the debugging routines. */ ++extern char *DWC_STRDUP(char const *str); ++#define dwc_strdup DWC_STRDUP ++ ++/** NOT an atoi() clone. Read the description carefully. Returns an integer ++ * converted from the string str in base 10 unless the string begins with a "0x" ++ * in which case it is base 16. String must be a NULL terminated sequence of ++ * ASCII characters and may optionally begin with whitespace, a + or -, and a ++ * "0x" prefix if base 16. The remaining characters must be valid digits for ++ * the number and end with a NULL character. If any invalid characters are ++ * encountered or it returns with a negative error code and the results of the ++ * conversion are undefined. On sucess it returns 0. Overflow conditions are ++ * undefined. An example implementation using atoi() can be referenced from the ++ * Linux implementation. */ ++extern int DWC_ATOI(char *str, int32_t *value); ++#define dwc_atoi DWC_ATOI ++/** Same as above but for unsigned. */ ++extern int DWC_ATOUI(char *str, uint32_t *value); ++#define dwc_atoui DWC_ATOUI ++/** This routine returns a UTF16LE unicode encoded string from a UTF8 string. */ ++extern int DWC_UTF8_TO_UTF16LE(uint8_t const *utf8string, uint16_t *utf16string, unsigned len); ++#define dwc_utf8_to_utf16le DWC_UTF8_TO_UTF16LE ++ ++/** @name Wait queues ++ * ++ * Wait queues provide a means of synchronizing between threads or processes. A ++ * process can block on a waitq if some condition is not true, waiting for it to ++ * become true. When the waitq is triggered all waiting process will get ++ * unblocked and the condition will be check again. Waitqs should be triggered ++ * every time a condition can potentially change.*/ ++struct dwc_waitq; ++typedef struct dwc_waitq dwc_waitq_t; ++ ++/** The type of waitq condition callback function. This is called every time ++ * condition is evaluated. */ ++typedef int (*dwc_waitq_condition_t)(void *data); ++ ++/** Allocate a waitq */ ++extern dwc_waitq_t *DWC_WAITQ_ALLOC(void); ++#define dwc_waitq_alloc DWC_WAITQ_ALLOC ++/** Free a waitq */ ++extern void DWC_WAITQ_FREE(dwc_waitq_t *wq); ++#define dwc_waitq_free DWC_WAITQ_FREE ++ ++/** Check the condition and if it is false, block on the waitq. When unblocked, check the ++ * condition again. The function returns when the condition becomes true. The return value ++ * is 0 on condition true, DWC_WAITQ_ABORTED on abort or killed, or DWC_WAITQ_UNKNOWN on error. */ ++extern int32_t DWC_WAITQ_WAIT(dwc_waitq_t *wq, dwc_waitq_condition_t condition, void *data); ++#define dwc_waitq_wait DWC_WAITQ_WAIT; ++/** Check the condition and if it is false, block on the waitq. When unblocked, ++ * check the condition again. The function returns when the condition become ++ * true or the timeout has passed. The return value is 0 on condition true or ++ * DWC_TIMED_OUT on timeout, or DWC_WAITQ_ABORTED, or DWC_WAITQ_UNKNOWN on ++ * error. */ ++extern int32_t DWC_WAITQ_WAIT_TIMEOUT(dwc_waitq_t *wq, dwc_waitq_condition_t condition, void *data, int32_t msecs); ++#define dwc_waitq_wait_timeout DWC_WAITQ_WAIT_TIMEOUT ++/** Trigger a waitq, unblocking all processes. This should be called whenever a condition ++ * has potentially changed. */ ++extern void DWC_WAITQ_TRIGGER(dwc_waitq_t *wq); ++#define dwc_waitq_trigger DWC_WAITQ_TRIGGER ++/** Unblock all processes waiting on the waitq with an ABORTED result. */ ++extern void DWC_WAITQ_ABORT(dwc_waitq_t *wq); ++#define dwc_waitq_abort DWC_WAITQ_ABORT ++ ++/** @name Threads ++ * ++ * A thread must be explicitly stopped. It must check DWC_THREAD_SHOULD_STOP ++ * whenever it is woken up, and then return. The DWC_THREAD_STOP function ++ * returns the value from the thread. ++ */ ++ ++struct dwc_thread; ++typedef struct dwc_thread dwc_thread_t; ++ ++/** The thread function */ ++typedef int (*dwc_thread_function_t)(void *data); ++ ++/** Create a thread and start it running the thread_function. Returns a handle ++ * to the thread */ ++extern dwc_thread_t *DWC_THREAD_RUN(dwc_thread_function_t thread_function, char *name, void *data); ++#define dwc_thread_run DWC_THREAD_RUN ++/** Stops a thread. Return the value returned by the thread. Or will return ++ * DWC_ABORT if the thread never started. */ ++extern int DWC_THREAD_STOP(dwc_thread_t *thread); ++#define dwc_thread_stop DWC_THREAD_STOP ++/** Signifies to the thread that it must stop. */ ++extern dwc_bool_t DWC_THREAD_SHOULD_STOP(void); ++#define dwc_thread_should_stop DWC_THREAD_SHOULD_STOP ++ ++/** @name Work queues ++ * ++ * Workqs are used to queue a callback function to be called at some later time, ++ * in another thread. */ ++struct dwc_workq; ++typedef struct dwc_workq dwc_workq_t; ++ ++/** The type of the callback function to be called. */ ++typedef void (*dwc_work_callback_t)(void *data); ++ ++/** Allocate a workq */ ++extern dwc_workq_t *DWC_WORKQ_ALLOC(char *name); ++#define dwc_workq_alloc DWC_WORKQ_ALLOC ++/** Free a workq. All work must be completed before being freed. */ ++extern void DWC_WORKQ_FREE(dwc_workq_t *workq); ++#define dwc_workq_free DWC_WORKQ_FREE ++/** Schedule a callback on the workq, passing in data. The function will be ++ * scheduled at some later time. */ ++extern void DWC_WORKQ_SCHEDULE(dwc_workq_t *workq, dwc_work_callback_t work_cb, void *data, char *format, ...) ++#ifdef __GNUC__ ++ __attribute__ ((format(printf, 4, 5))); ++#else ++ ; ++#endif ++#define dwc_workq_schedule DWC_WORKQ_SCHEDULE ++ ++/** Schedule a callback on the workq, that will be called until at least ++ * given number miliseconds have passed. */ ++extern void DWC_WORKQ_SCHEDULE_DELAYED(dwc_workq_t *workq, dwc_work_callback_t work_cb, void *data, uint32_t time, char *format, ...) ++#ifdef __GNUC__ ++ __attribute__ ((format(printf, 5, 6))); ++#else ++ ; ++#endif ++#define dwc_workq_schedule_delayed DWC_WORKQ_SCHEDULE_DELAYED ++ ++/** The number of processes in the workq */ ++extern int DWC_WORKQ_PENDING(dwc_workq_t *workq); ++#define dwc_workq_pending DWC_WORKQ_PENDING ++/** Blocks until all the work in the workq is complete or timed out. Returns < ++ * 0 on timeout. */ ++extern int DWC_WORKQ_WAIT_WORK_DONE(dwc_workq_t *workq, int timeout); ++#define dwc_workq_wait_work_done DWC_WORKQ_WAIT_WORK_DONE ++ ++ ++/** @name Tasklets ++ * ++ */ ++struct dwc_tasklet; ++typedef struct dwc_tasklet dwc_tasklet_t; ++ ++typedef void (*dwc_tasklet_callback_t)(void *data); ++ ++extern dwc_tasklet_t *DWC_TASK_ALLOC(dwc_tasklet_callback_t cb, void *data); ++#define dwc_task_alloc DWC_TASK_ALLOC ++extern void DWC_TASK_FREE(dwc_tasklet_t *t); ++#define dwc_task_free DWC_TASK_FREE ++extern void DWC_TASK_SCHEDULE(dwc_tasklet_t *task); ++#define dwc_task_schedule DWC_TASK_SCHEDULE ++ ++ ++/** @name Timer ++ * ++ * Callbacks must be small and atomic. ++ */ ++struct dwc_timer; ++typedef struct dwc_timer dwc_timer_t; ++ ++typedef void (*dwc_timer_callback_t)(void *data); ++ ++extern dwc_timer_t *DWC_TIMER_ALLOC(char *name, dwc_timer_callback_t cb, void *data); ++#define dwc_timer_alloc DWC_TIMER_ALLOC ++extern void DWC_TIMER_FREE(dwc_timer_t *timer); ++#define dwc_timer_free DWC_TIMER_FREE ++ ++/** Schedules the timer to run at time ms from now. And will repeat at every ++ * repeat_interval msec therafter ++ * ++ * Modifies a timer that is still awaiting execution to a new expiration time. ++ * The mod_time is added to the old time. */ ++extern void DWC_TIMER_SCHEDULE(dwc_timer_t *timer, uint32_t time); ++#define dwc_timer_schedule DWC_TIMER_SCHEDULE ++ ++/** Disables the timer from execution. */ ++extern void DWC_TIMER_CANCEL(dwc_timer_t *timer); ++#define dwc_timer_cancel DWC_TIMER_CANCEL ++ ++ ++ ++/** @name Spinlocks ++ * ++ * These locks are used when the work between the lock/unlock is atomic and ++ * short. Interrupts are also disabled during the lock/unlock and thus they are ++ * suitable to lock between interrupt/non-interrupt context. They also lock ++ * between processes if you have multiple CPUs or Preemption. If you don't have ++ * multiple CPUS or Preemption, then the you can simply implement the ++ * DWC_SPINLOCK and DWC_SPINUNLOCK to disable and enable interrupts. Because ++ * the work between the lock/unlock is atomic, the process context will never ++ * change, and so you never have to lock between processes. */ ++ ++struct dwc_spinlock; ++typedef struct dwc_spinlock dwc_spinlock_t; ++ ++/** Returns an initialized lock variable. This function should allocate and ++ * initialize the OS-specific data structure used for locking. This data ++ * structure is to be used for the DWC_LOCK and DWC_UNLOCK functions and should ++ * be freed by the DWC_FREE_LOCK when it is no longer used. */ ++extern dwc_spinlock_t *DWC_SPINLOCK_ALLOC(void); ++#define dwc_spinlock_alloc DWC_SPINLOCK_ALLOC ++ ++/** Frees an initialized lock variable. */ ++extern void DWC_SPINLOCK_FREE(dwc_spinlock_t *lock); ++#define dwc_spinlock_free DWC_SPINLOCK_FREE ++ ++/** Disables interrupts and blocks until it acquires the lock. ++ * ++ * @param lock Pointer to the spinlock. ++ * @param flags Unsigned long for irq flags storage. ++ */ ++extern void DWC_SPINLOCK_IRQSAVE(dwc_spinlock_t *lock, uint64_t *flags); ++#define dwc_spinlock_irqsave DWC_SPINLOCK_IRQSAVE ++ ++/** Re-enables the interrupt and releases the lock. ++ * ++ * @param lock Pointer to the spinlock. ++ * @param flags Unsigned long for irq flags storage. Must be the same as was ++ * passed into DWC_LOCK. ++ */ ++extern void DWC_SPINUNLOCK_IRQRESTORE(dwc_spinlock_t *lock, uint64_t flags); ++#define dwc_spinunlock_irqrestore DWC_SPINUNLOCK_IRQRESTORE ++ ++/** Blocks until it acquires the lock. ++ * ++ * @param lock Pointer to the spinlock. ++ */ ++extern void DWC_SPINLOCK(dwc_spinlock_t *lock); ++#define dwc_spinlock DWC_SPINLOCK ++ ++/** Releases the lock. ++ * ++ * @param lock Pointer to the spinlock. ++ */ ++extern void DWC_SPINUNLOCK(dwc_spinlock_t *lock); ++#define dwc_spinunlock DWC_SPINUNLOCK ++ ++/** @name Mutexes ++ * ++ * Unlike spinlocks Mutexes lock only between processes and the work between the ++ * lock/unlock CAN block, therefore it CANNOT be called from interrupt context. ++ */ ++ ++struct dwc_mutex; ++typedef struct dwc_mutex dwc_mutex_t; ++ ++ ++/* For Linux Mutex Debugging make it inline because the debugging routines use ++ * the symbol to determine recursive locking. This makes it falsely think ++ * recursive locking occurs. */ ++#if (defined(DWC_LINUX) && defined(CONFIG_DEBUG_MUTEXES)) ++#define DWC_MUTEX_ALLOC_LINUX_DEBUG(__mutexp) ({ \ ++ __mutexp = (dwc_mutex_t *)DWC_ALLOC(sizeof(struct mutex)); \ ++ mutex_init((struct mutex *)__mutexp); \ ++}) ++#endif ++extern dwc_mutex_t *DWC_MUTEX_ALLOC(void); ++#define dwc_mutex_alloc DWC_MUTEX_ALLOC ++ ++/* For memory leak debugging when using Linux Mutex Debugging */ ++#if (defined(DWC_LINUX) && defined(CONFIG_DEBUG_MUTEXES)) ++#define DWC_MUTEX_FREE(__mutexp) do { \ ++ mutex_destroy((struct mutex *)__mutexp); \ ++ DWC_FREE(__mutexp); \ ++} while(0) ++#else ++extern void DWC_MUTEX_FREE(dwc_mutex_t *mutex); ++#define dwc_mutex_free DWC_MUTEX_FREE ++#endif ++ ++extern void DWC_MUTEX_LOCK(dwc_mutex_t *mutex); ++#define dwc_mutex_lock DWC_MUTEX_LOCK ++/** Non-blocking lock returns 1 on successful lock. */ ++extern int DWC_MUTEX_TRYLOCK(dwc_mutex_t *mutex); ++#define dwc_mutex_trylock DWC_MUTEX_TRYLOCK ++extern void DWC_MUTEX_UNLOCK(dwc_mutex_t *mutex); ++#define dwc_mutex_unlock DWC_MUTEX_UNLOCK ++ ++ ++ ++ ++/** @name Time */ ++ ++/** Microsecond delay. ++ * ++ * @param usecs Microseconds to delay. ++ */ ++extern void DWC_UDELAY(uint32_t usecs); ++#define dwc_udelay DWC_UDELAY ++ ++/** Millisecond delay. ++ * ++ * @param msecs Milliseconds to delay. ++ */ ++extern void DWC_MDELAY(uint32_t msecs); ++#define dwc_mdelay DWC_MDELAY ++ ++/** Non-busy waiting. ++ * Sleeps for specified number of milliseconds. ++ * ++ * @param msecs Milliseconds to sleep. ++ */ ++extern void DWC_MSLEEP(uint32_t msecs); ++#define dwc_msleep DWC_MSLEEP ++ ++extern uint32_t DWC_TIME(void); ++#define dwc_time DWC_TIME ++ ++#endif // _DWC_OS_H_ ++ ++ ++ ++ ++/** @mainpage DWC Portability and Common Library ++ * ++ * This is the documentation for the DWC Portability and Common Library. ++ * ++ * @section intro Introduction ++ * ++ * The DWC Portability library consists of wrapper calls and data structures to ++ * all low-level functions which are typically provided by the OS. The WUDEV ++ * driver uses only these functions. In order to port the WUDEV driver, only ++ * the functions in this library need to be re-implemented, with the same ++ * behavior as documented here. ++ * ++ * The Common library consists of higher level functions, which rely only on ++ * calling the functions from the DWC Portability library. These common ++ * routines are shared across modules. Some of the common libraries need to be ++ * used directly by the driver programmer when porting WUDEV. Such as the ++ * parameter and notification libraries. ++ * ++ * @section low Portability Library OS Wrapper Functions ++ * ++ * Any function starting with DWC and in all CAPS is a low-level OS-wrapper that ++ * needs to be implemented when porting, for example DWC_MUTEX_ALLOC(). All of ++ * these functions are included in the dwc_os.h file. ++ * ++ * There are many functions here covering a wide array of OS services. Please ++ * see dwc_os.h for details, and implementation notes for each function. ++ * ++ * @section common Common Library Functions ++ * ++ * Any function starting with dwc and in all lowercase is a common library ++ * routine. These functions have a portable implementation and do not need to ++ * be reimplemented when porting. The common routines can be used by any ++ * driver, and some must be used by the end user to control the drivers. For ++ * example, you must use the Parameter common library in order to set the ++ * parameters in the WUDEV module. ++ * ++ * The common libraries consist of the following: ++ * ++ * - Connection Contexts - Used internally and can be used by end-user. See dwc_cc.h ++ * - Parameters - Used internally and can be used by end-user. See dwc_params.h ++ * - Notifications - Used internally and can be used by end-user. See dwc_notifier.h ++ * - Lists - Used internally and can be used by end-user. See dwc_list.h ++ * - Memory Debugging - Used internally and can be used by end-user. See dwc_os.h ++ * - Modpow - Used internally only. See dwc_modpow.h ++ * - DH - Used internally only. See dwc_dh.h ++ * - Crypto - Used internally only. See dwc_crypto.h ++ * ++ * ++ * @section prereq Prerequistes For dwc_os.h ++ * @subsection types Data Types ++ * ++ * The dwc_os.h file assumes that several low-level data types are pre defined for the ++ * compilation environment. These data types are: ++ * ++ * - uint8_t - unsigned 8-bit data type ++ * - int8_t - signed 8-bit data type ++ * - uint16_t - unsigned 16-bit data type ++ * - int16_t - signed 16-bit data type ++ * - uint32_t - unsigned 32-bit data type ++ * - int32_t - signed 32-bit data type ++ * - uint64_t - unsigned 64-bit data type ++ * - int64_t - signed 64-bit data type ++ * ++ * Ensure that these are defined before using dwc_os.h. The easiest way to do ++ * that is to modify the top of the file to include the appropriate header. ++ * This is already done for the Linux environment. If the DWC_LINUX macro is ++ * defined, the correct header will be added. A standard header is ++ * also used for environments where standard C headers are available. ++ * ++ * @subsection stdarg Variable Arguments ++ * ++ * Variable arguments are provided by a standard C header . it is ++ * available in Both the Linux and ANSI C enviornment. An equivalent must be ++ * provided in your enviornment in order to use dwc_os.h with the debug and ++ * tracing message functionality. ++ * ++ * @subsection thread Threading ++ * ++ * WUDEV Core must be run on an operating system that provides for multiple ++ * threads/processes. Threading can be implemented in many ways, even in ++ * embedded systems without an operating system. At the bare minimum, the ++ * system should be able to start any number of processes at any time to handle ++ * special work. It need not be a pre-emptive system. Process context can ++ * change upon a call to a blocking function. The hardware interrupt context ++ * that calls the module's ISR() function must be differentiable from process ++ * context, even if your processes are impemented via a hardware interrupt. ++ * Further locking mechanism between process must exist (or be implemented), and ++ * process context must have a way to disable interrupts for a period of time to ++ * lock them out. If all of this exists, the functions in dwc_os.h related to ++ * threading should be able to be implemented with the defined behavior. ++ * ++ */ +Index: linux-3.2.46/drivers/usb/host/dwc_common_port/usb.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_common_port/usb.h 2013-07-26 19:31:20.000000000 +0000 +@@ -0,0 +1,850 @@ ++/* ++ * Copyright (c) 1998 The NetBSD Foundation, Inc. ++ * All rights reserved. ++ * ++ * This code is derived from software contributed to The NetBSD Foundation ++ * by Lennart Augustsson (lennart@augustsson.net) at ++ * Carlstedt Research & Technology. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions and the following disclaimer. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. All advertising materials mentioning features or use of this software ++ * must display the following acknowledgement: ++ * This product includes software developed by the NetBSD ++ * Foundation, Inc. and its contributors. ++ * 4. Neither the name of The NetBSD Foundation nor the names of its ++ * contributors may be used to endorse or promote products derived ++ * from this software without specific prior written permission. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS ++ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ++ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR ++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS ++ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR ++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF ++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN ++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ++ * POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++/* Modified by Synopsys, Inc, 12/12/2007 */ ++ ++ ++#ifndef _USB_H_ ++#define _USB_H_ ++ ++#include "dwc_os.h" ++ ++/* ++ * The USB records contain some unaligned little-endian word ++ * components. The U[SG]ETW macros take care of both the alignment ++ * and endian problem and should always be used to access non-byte ++ * values. ++ */ ++typedef u_int8_t uByte; ++typedef u_int8_t uWord[2]; ++typedef u_int8_t uDWord[4]; ++ ++#define USETW2(w,h,l) ((w)[0] = (u_int8_t)(l), (w)[1] = (u_int8_t)(h)) ++ ++#if 1 ++#define UGETW(w) ((w)[0] | ((w)[1] << 8)) ++#define USETW(w,v) ((w)[0] = (u_int8_t)(v), (w)[1] = (u_int8_t)((v) >> 8)) ++#define UGETDW(w) ((w)[0] | ((w)[1] << 8) | ((w)[2] << 16) | ((w)[3] << 24)) ++#define USETDW(w,v) ((w)[0] = (u_int8_t)(v), \ ++ (w)[1] = (u_int8_t)((v) >> 8), \ ++ (w)[2] = (u_int8_t)((v) >> 16), \ ++ (w)[3] = (u_int8_t)((v) >> 24)) ++#else ++/* ++ * On little-endian machines that can handle unanliged accesses ++ * (e.g. i386) these macros can be replaced by the following. ++ */ ++#define UGETW(w) (*(u_int16_t *)(w)) ++#define USETW(w,v) (*(u_int16_t *)(w) = (v)) ++#define UGETDW(w) (*(u_int32_t *)(w)) ++#define USETDW(w,v) (*(u_int32_t *)(w) = (v)) ++#endif ++ ++#define UPACKED __attribute__((__packed__)) ++ ++typedef struct { ++ uByte bmRequestType; ++ uByte bRequest; ++ uWord wValue; ++ uWord wIndex; ++ uWord wLength; ++} UPACKED usb_device_request_t; ++ ++#define UT_GET_DIR(a) ((a) & 0x80) ++#define UT_WRITE 0x00 ++#define UT_READ 0x80 ++ ++#define UT_GET_TYPE(a) ((a) & 0x60) ++#define UT_STANDARD 0x00 ++#define UT_CLASS 0x20 ++#define UT_VENDOR 0x40 ++ ++#define UT_GET_RECIPIENT(a) ((a) & 0x1f) ++#define UT_DEVICE 0x00 ++#define UT_INTERFACE 0x01 ++#define UT_ENDPOINT 0x02 ++#define UT_OTHER 0x03 ++ ++#define UT_READ_DEVICE (UT_READ | UT_STANDARD | UT_DEVICE) ++#define UT_READ_INTERFACE (UT_READ | UT_STANDARD | UT_INTERFACE) ++#define UT_READ_ENDPOINT (UT_READ | UT_STANDARD | UT_ENDPOINT) ++#define UT_WRITE_DEVICE (UT_WRITE | UT_STANDARD | UT_DEVICE) ++#define UT_WRITE_INTERFACE (UT_WRITE | UT_STANDARD | UT_INTERFACE) ++#define UT_WRITE_ENDPOINT (UT_WRITE | UT_STANDARD | UT_ENDPOINT) ++#define UT_READ_CLASS_DEVICE (UT_READ | UT_CLASS | UT_DEVICE) ++#define UT_READ_CLASS_INTERFACE (UT_READ | UT_CLASS | UT_INTERFACE) ++#define UT_READ_CLASS_OTHER (UT_READ | UT_CLASS | UT_OTHER) ++#define UT_READ_CLASS_ENDPOINT (UT_READ | UT_CLASS | UT_ENDPOINT) ++#define UT_WRITE_CLASS_DEVICE (UT_WRITE | UT_CLASS | UT_DEVICE) ++#define UT_WRITE_CLASS_INTERFACE (UT_WRITE | UT_CLASS | UT_INTERFACE) ++#define UT_WRITE_CLASS_OTHER (UT_WRITE | UT_CLASS | UT_OTHER) ++#define UT_WRITE_CLASS_ENDPOINT (UT_WRITE | UT_CLASS | UT_ENDPOINT) ++#define UT_READ_VENDOR_DEVICE (UT_READ | UT_VENDOR | UT_DEVICE) ++#define UT_READ_VENDOR_INTERFACE (UT_READ | UT_VENDOR | UT_INTERFACE) ++#define UT_READ_VENDOR_OTHER (UT_READ | UT_VENDOR | UT_OTHER) ++#define UT_READ_VENDOR_ENDPOINT (UT_READ | UT_VENDOR | UT_ENDPOINT) ++#define UT_WRITE_VENDOR_DEVICE (UT_WRITE | UT_VENDOR | UT_DEVICE) ++#define UT_WRITE_VENDOR_INTERFACE (UT_WRITE | UT_VENDOR | UT_INTERFACE) ++#define UT_WRITE_VENDOR_OTHER (UT_WRITE | UT_VENDOR | UT_OTHER) ++#define UT_WRITE_VENDOR_ENDPOINT (UT_WRITE | UT_VENDOR | UT_ENDPOINT) ++ ++/* Requests */ ++#define UR_GET_STATUS 0x00 ++#define USTAT_STANDARD_STATUS 0x00 ++#define WUSTAT_WUSB_FEATURE 0x01 ++#define WUSTAT_CHANNEL_INFO 0x02 ++#define WUSTAT_RECEIVED_DATA 0x03 ++#define WUSTAT_MAS_AVAILABILITY 0x04 ++#define WUSTAT_CURRENT_TRANSMIT_POWER 0x05 ++#define UR_CLEAR_FEATURE 0x01 ++#define UR_SET_FEATURE 0x03 ++#define UR_SET_AND_TEST_FEATURE 0x0c ++#define UR_SET_ADDRESS 0x05 ++#define UR_GET_DESCRIPTOR 0x06 ++#define UDESC_DEVICE 0x01 ++#define UDESC_CONFIG 0x02 ++#define UDESC_STRING 0x03 ++#define UDESC_INTERFACE 0x04 ++#define UDESC_ENDPOINT 0x05 ++#define UDESC_DEVICE_QUALIFIER 0x06 ++#define UDESC_OTHER_SPEED_CONFIGURATION 0x07 ++#define UDESC_INTERFACE_POWER 0x08 ++#define UDESC_OTG 0x09 ++#define WUDESC_SECURITY 0x0c ++#define WUDESC_KEY 0x0d ++#define WUD_GET_KEY_INDEX(_wValue_) ((_wValue_) & 0xf) ++#define WUD_GET_KEY_TYPE(_wValue_) (((_wValue_) & 0x30) >> 4) ++#define WUD_KEY_TYPE_ASSOC 0x01 ++#define WUD_KEY_TYPE_GTK 0x02 ++#define WUD_GET_KEY_ORIGIN(_wValue_) (((_wValue_) & 0x40) >> 6) ++#define WUD_KEY_ORIGIN_HOST 0x00 ++#define WUD_KEY_ORIGIN_DEVICE 0x01 ++#define WUDESC_ENCRYPTION_TYPE 0x0e ++#define WUDESC_BOS 0x0f ++#define WUDESC_DEVICE_CAPABILITY 0x10 ++#define WUDESC_WIRELESS_ENDPOINT_COMPANION 0x11 ++#define UDESC_CS_DEVICE 0x21 /* class specific */ ++#define UDESC_CS_CONFIG 0x22 ++#define UDESC_CS_STRING 0x23 ++#define UDESC_CS_INTERFACE 0x24 ++#define UDESC_CS_ENDPOINT 0x25 ++#define UDESC_HUB 0x29 ++#define UR_SET_DESCRIPTOR 0x07 ++#define UR_GET_CONFIG 0x08 ++#define UR_SET_CONFIG 0x09 ++#define UR_GET_INTERFACE 0x0a ++#define UR_SET_INTERFACE 0x0b ++#define UR_SYNCH_FRAME 0x0c ++#define WUR_SET_ENCRYPTION 0x0d ++#define WUR_GET_ENCRYPTION 0x0e ++#define WUR_SET_HANDSHAKE 0x0f ++#define WUR_GET_HANDSHAKE 0x10 ++#define WUR_SET_CONNECTION 0x11 ++#define WUR_SET_SECURITY_DATA 0x12 ++#define WUR_GET_SECURITY_DATA 0x13 ++#define WUR_SET_WUSB_DATA 0x14 ++#define WUDATA_DRPIE_INFO 0x01 ++#define WUDATA_TRANSMIT_DATA 0x02 ++#define WUDATA_TRANSMIT_PARAMS 0x03 ++#define WUDATA_RECEIVE_PARAMS 0x04 ++#define WUDATA_TRANSMIT_POWER 0x05 ++#define WUR_LOOPBACK_DATA_WRITE 0x15 ++#define WUR_LOOPBACK_DATA_READ 0x16 ++#define WUR_SET_INTERFACE_DS 0x17 ++ ++/* Feature numbers */ ++#define UF_ENDPOINT_HALT 0 ++#define UF_DEVICE_REMOTE_WAKEUP 1 ++#define UF_TEST_MODE 2 ++#define UF_DEVICE_B_HNP_ENABLE 3 ++#define UF_DEVICE_A_HNP_SUPPORT 4 ++#define UF_DEVICE_A_ALT_HNP_SUPPORT 5 ++#define WUF_WUSB 3 ++#define WUF_TX_DRPIE 0x0 ++#define WUF_DEV_XMIT_PACKET 0x1 ++#define WUF_COUNT_PACKETS 0x2 ++#define WUF_CAPTURE_PACKETS 0x3 ++ ++/* Class requests from the USB 2.0 hub spec, table 11-15 */ ++#define UCR_CLEAR_HUB_FEATURE (0x2000 | UR_CLEAR_FEATURE) ++#define UCR_CLEAR_PORT_FEATURE (0x2300 | UR_CLEAR_FEATURE) ++#define UCR_GET_HUB_DESCRIPTOR (0xa000 | UR_GET_DESCRIPTOR) ++#define UCR_GET_HUB_STATUS (0xa000 | UR_GET_STATUS) ++#define UCR_GET_PORT_STATUS (0xa300 | UR_GET_STATUS) ++#define UCR_SET_HUB_FEATURE (0x2000 | UR_SET_FEATURE) ++#define UCR_SET_PORT_FEATURE (0x2300 | UR_SET_FEATURE) ++#define UCR_SET_AND_TEST_PORT_FEATURE (0xa300 | UR_SET_AND_TEST_FEATURE) ++ ++typedef struct { ++ uByte bLength; ++ uByte bDescriptorType; ++ uByte bDescriptorSubtype; ++} UPACKED usb_descriptor_t; ++ ++typedef struct { ++ uByte bLength; ++ uByte bDescriptorType; ++ uWord bcdUSB; ++#define UD_USB_2_0 0x0200 ++#define UD_IS_USB2(d) (UGETW((d)->bcdUSB) >= UD_USB_2_0) ++ uByte bDeviceClass; ++ uByte bDeviceSubClass; ++ uByte bDeviceProtocol; ++ uByte bMaxPacketSize; ++ /* The fields below are not part of the initial descriptor. */ ++ uWord idVendor; ++ uWord idProduct; ++ uWord bcdDevice; ++ uByte iManufacturer; ++ uByte iProduct; ++ uByte iSerialNumber; ++ uByte bNumConfigurations; ++} UPACKED usb_device_descriptor_t; ++#define USB_DEVICE_DESCRIPTOR_SIZE 18 ++ ++typedef struct { ++ uByte bLength; ++ uByte bDescriptorType; ++ uWord wTotalLength; ++ uByte bNumInterface; ++ uByte bConfigurationValue; ++ uByte iConfiguration; ++ uByte bmAttributes; ++#define UC_BUS_POWERED 0x80 ++#define UC_SELF_POWERED 0x40 ++#define UC_REMOTE_WAKEUP 0x20 ++ uByte bMaxPower; /* max current in 2 mA units */ ++#define UC_POWER_FACTOR 2 ++} UPACKED usb_config_descriptor_t; ++#define USB_CONFIG_DESCRIPTOR_SIZE 9 ++ ++typedef struct { ++ uByte bLength; ++ uByte bDescriptorType; ++ uByte bInterfaceNumber; ++ uByte bAlternateSetting; ++ uByte bNumEndpoints; ++ uByte bInterfaceClass; ++ uByte bInterfaceSubClass; ++ uByte bInterfaceProtocol; ++ uByte iInterface; ++} UPACKED usb_interface_descriptor_t; ++#define USB_INTERFACE_DESCRIPTOR_SIZE 9 ++ ++typedef struct { ++ uByte bLength; ++ uByte bDescriptorType; ++ uByte bEndpointAddress; ++#define UE_GET_DIR(a) ((a) & 0x80) ++#define UE_SET_DIR(a,d) ((a) | (((d)&1) << 7)) ++#define UE_DIR_IN 0x80 ++#define UE_DIR_OUT 0x00 ++#define UE_ADDR 0x0f ++#define UE_GET_ADDR(a) ((a) & UE_ADDR) ++ uByte bmAttributes; ++#define UE_XFERTYPE 0x03 ++#define UE_CONTROL 0x00 ++#define UE_ISOCHRONOUS 0x01 ++#define UE_BULK 0x02 ++#define UE_INTERRUPT 0x03 ++#define UE_GET_XFERTYPE(a) ((a) & UE_XFERTYPE) ++#define UE_ISO_TYPE 0x0c ++#define UE_ISO_ASYNC 0x04 ++#define UE_ISO_ADAPT 0x08 ++#define UE_ISO_SYNC 0x0c ++#define UE_GET_ISO_TYPE(a) ((a) & UE_ISO_TYPE) ++ uWord wMaxPacketSize; ++ uByte bInterval; ++} UPACKED usb_endpoint_descriptor_t; ++#define USB_ENDPOINT_DESCRIPTOR_SIZE 7 ++ ++typedef struct { ++ uByte bLength; ++ uByte bDescriptorType; ++ uWord bString[127]; ++} UPACKED usb_string_descriptor_t; ++#define USB_MAX_STRING_LEN 128 ++#define USB_LANGUAGE_TABLE 0 /* # of the string language id table */ ++ ++/* Hub specific request */ ++#define UR_GET_BUS_STATE 0x02 ++#define UR_CLEAR_TT_BUFFER 0x08 ++#define UR_RESET_TT 0x09 ++#define UR_GET_TT_STATE 0x0a ++#define UR_STOP_TT 0x0b ++ ++/* Hub features */ ++#define UHF_C_HUB_LOCAL_POWER 0 ++#define UHF_C_HUB_OVER_CURRENT 1 ++#define UHF_PORT_CONNECTION 0 ++#define UHF_PORT_ENABLE 1 ++#define UHF_PORT_SUSPEND 2 ++#define UHF_PORT_OVER_CURRENT 3 ++#define UHF_PORT_RESET 4 ++#define UHF_PORT_L1 5 ++#define UHF_PORT_POWER 8 ++#define UHF_PORT_LOW_SPEED 9 ++#define UHF_PORT_HIGH_SPEED 10 ++#define UHF_C_PORT_CONNECTION 16 ++#define UHF_C_PORT_ENABLE 17 ++#define UHF_C_PORT_SUSPEND 18 ++#define UHF_C_PORT_OVER_CURRENT 19 ++#define UHF_C_PORT_RESET 20 ++#define UHF_C_PORT_L1 23 ++#define UHF_PORT_TEST 21 ++#define UHF_PORT_INDICATOR 22 ++ ++typedef struct { ++ uByte bDescLength; ++ uByte bDescriptorType; ++ uByte bNbrPorts; ++ uWord wHubCharacteristics; ++#define UHD_PWR 0x0003 ++#define UHD_PWR_GANGED 0x0000 ++#define UHD_PWR_INDIVIDUAL 0x0001 ++#define UHD_PWR_NO_SWITCH 0x0002 ++#define UHD_COMPOUND 0x0004 ++#define UHD_OC 0x0018 ++#define UHD_OC_GLOBAL 0x0000 ++#define UHD_OC_INDIVIDUAL 0x0008 ++#define UHD_OC_NONE 0x0010 ++#define UHD_TT_THINK 0x0060 ++#define UHD_TT_THINK_8 0x0000 ++#define UHD_TT_THINK_16 0x0020 ++#define UHD_TT_THINK_24 0x0040 ++#define UHD_TT_THINK_32 0x0060 ++#define UHD_PORT_IND 0x0080 ++ uByte bPwrOn2PwrGood; /* delay in 2 ms units */ ++#define UHD_PWRON_FACTOR 2 ++ uByte bHubContrCurrent; ++ uByte DeviceRemovable[32]; /* max 255 ports */ ++#define UHD_NOT_REMOV(desc, i) \ ++ (((desc)->DeviceRemovable[(i)/8] >> ((i) % 8)) & 1) ++ /* deprecated */ uByte PortPowerCtrlMask[1]; ++} UPACKED usb_hub_descriptor_t; ++#define USB_HUB_DESCRIPTOR_SIZE 9 /* includes deprecated PortPowerCtrlMask */ ++ ++typedef struct { ++ uByte bLength; ++ uByte bDescriptorType; ++ uWord bcdUSB; ++ uByte bDeviceClass; ++ uByte bDeviceSubClass; ++ uByte bDeviceProtocol; ++ uByte bMaxPacketSize0; ++ uByte bNumConfigurations; ++ uByte bReserved; ++} UPACKED usb_device_qualifier_t; ++#define USB_DEVICE_QUALIFIER_SIZE 10 ++ ++typedef struct { ++ uByte bLength; ++ uByte bDescriptorType; ++ uByte bmAttributes; ++#define UOTG_SRP 0x01 ++#define UOTG_HNP 0x02 ++} UPACKED usb_otg_descriptor_t; ++ ++/* OTG feature selectors */ ++#define UOTG_B_HNP_ENABLE 3 ++#define UOTG_A_HNP_SUPPORT 4 ++#define UOTG_A_ALT_HNP_SUPPORT 5 ++ ++typedef struct { ++ uWord wStatus; ++/* Device status flags */ ++#define UDS_SELF_POWERED 0x0001 ++#define UDS_REMOTE_WAKEUP 0x0002 ++/* Endpoint status flags */ ++#define UES_HALT 0x0001 ++} UPACKED usb_status_t; ++ ++typedef struct { ++ uWord wHubStatus; ++#define UHS_LOCAL_POWER 0x0001 ++#define UHS_OVER_CURRENT 0x0002 ++ uWord wHubChange; ++} UPACKED usb_hub_status_t; ++ ++typedef struct { ++ uWord wPortStatus; ++#define UPS_CURRENT_CONNECT_STATUS 0x0001 ++#define UPS_PORT_ENABLED 0x0002 ++#define UPS_SUSPEND 0x0004 ++#define UPS_OVERCURRENT_INDICATOR 0x0008 ++#define UPS_RESET 0x0010 ++#define UPS_PORT_POWER 0x0100 ++#define UPS_LOW_SPEED 0x0200 ++#define UPS_HIGH_SPEED 0x0400 ++#define UPS_PORT_TEST 0x0800 ++#define UPS_PORT_INDICATOR 0x1000 ++ uWord wPortChange; ++#define UPS_C_CONNECT_STATUS 0x0001 ++#define UPS_C_PORT_ENABLED 0x0002 ++#define UPS_C_SUSPEND 0x0004 ++#define UPS_C_OVERCURRENT_INDICATOR 0x0008 ++#define UPS_C_PORT_RESET 0x0010 ++} UPACKED usb_port_status_t; ++ ++/* Device class codes */ ++#define UDCLASS_IN_INTERFACE 0x00 ++#define UDCLASS_COMM 0x02 ++#define UDCLASS_HUB 0x09 ++#define UDSUBCLASS_HUB 0x00 ++#define UDPROTO_FSHUB 0x00 ++#define UDPROTO_HSHUBSTT 0x01 ++#define UDPROTO_HSHUBMTT 0x02 ++#define UDCLASS_DIAGNOSTIC 0xdc ++#define UDCLASS_WIRELESS 0xe0 ++#define UDSUBCLASS_RF 0x01 ++#define UDPROTO_BLUETOOTH 0x01 ++#define UDCLASS_VENDOR 0xff ++ ++/* Interface class codes */ ++#define UICLASS_UNSPEC 0x00 ++ ++#define UICLASS_AUDIO 0x01 ++#define UISUBCLASS_AUDIOCONTROL 1 ++#define UISUBCLASS_AUDIOSTREAM 2 ++#define UISUBCLASS_MIDISTREAM 3 ++ ++#define UICLASS_CDC 0x02 /* communication */ ++#define UISUBCLASS_DIRECT_LINE_CONTROL_MODEL 1 ++#define UISUBCLASS_ABSTRACT_CONTROL_MODEL 2 ++#define UISUBCLASS_TELEPHONE_CONTROL_MODEL 3 ++#define UISUBCLASS_MULTICHANNEL_CONTROL_MODEL 4 ++#define UISUBCLASS_CAPI_CONTROLMODEL 5 ++#define UISUBCLASS_ETHERNET_NETWORKING_CONTROL_MODEL 6 ++#define UISUBCLASS_ATM_NETWORKING_CONTROL_MODEL 7 ++#define UIPROTO_CDC_AT 1 ++ ++#define UICLASS_HID 0x03 ++#define UISUBCLASS_BOOT 1 ++#define UIPROTO_BOOT_KEYBOARD 1 ++ ++#define UICLASS_PHYSICAL 0x05 ++ ++#define UICLASS_IMAGE 0x06 ++ ++#define UICLASS_PRINTER 0x07 ++#define UISUBCLASS_PRINTER 1 ++#define UIPROTO_PRINTER_UNI 1 ++#define UIPROTO_PRINTER_BI 2 ++#define UIPROTO_PRINTER_1284 3 ++ ++#define UICLASS_MASS 0x08 ++#define UISUBCLASS_RBC 1 ++#define UISUBCLASS_SFF8020I 2 ++#define UISUBCLASS_QIC157 3 ++#define UISUBCLASS_UFI 4 ++#define UISUBCLASS_SFF8070I 5 ++#define UISUBCLASS_SCSI 6 ++#define UIPROTO_MASS_CBI_I 0 ++#define UIPROTO_MASS_CBI 1 ++#define UIPROTO_MASS_BBB_OLD 2 /* Not in the spec anymore */ ++#define UIPROTO_MASS_BBB 80 /* 'P' for the Iomega Zip drive */ ++ ++#define UICLASS_HUB 0x09 ++#define UISUBCLASS_HUB 0 ++#define UIPROTO_FSHUB 0 ++#define UIPROTO_HSHUBSTT 0 /* Yes, same as previous */ ++#define UIPROTO_HSHUBMTT 1 ++ ++#define UICLASS_CDC_DATA 0x0a ++#define UISUBCLASS_DATA 0 ++#define UIPROTO_DATA_ISDNBRI 0x30 /* Physical iface */ ++#define UIPROTO_DATA_HDLC 0x31 /* HDLC */ ++#define UIPROTO_DATA_TRANSPARENT 0x32 /* Transparent */ ++#define UIPROTO_DATA_Q921M 0x50 /* Management for Q921 */ ++#define UIPROTO_DATA_Q921 0x51 /* Data for Q921 */ ++#define UIPROTO_DATA_Q921TM 0x52 /* TEI multiplexer for Q921 */ ++#define UIPROTO_DATA_V42BIS 0x90 /* Data compression */ ++#define UIPROTO_DATA_Q931 0x91 /* Euro-ISDN */ ++#define UIPROTO_DATA_V120 0x92 /* V.24 rate adaption */ ++#define UIPROTO_DATA_CAPI 0x93 /* CAPI 2.0 commands */ ++#define UIPROTO_DATA_HOST_BASED 0xfd /* Host based driver */ ++#define UIPROTO_DATA_PUF 0xfe /* see Prot. Unit Func. Desc.*/ ++#define UIPROTO_DATA_VENDOR 0xff /* Vendor specific */ ++ ++#define UICLASS_SMARTCARD 0x0b ++ ++/*#define UICLASS_FIRM_UPD 0x0c*/ ++ ++#define UICLASS_SECURITY 0x0d ++ ++#define UICLASS_DIAGNOSTIC 0xdc ++ ++#define UICLASS_WIRELESS 0xe0 ++#define UISUBCLASS_RF 0x01 ++#define UIPROTO_BLUETOOTH 0x01 ++ ++#define UICLASS_APPL_SPEC 0xfe ++#define UISUBCLASS_FIRMWARE_DOWNLOAD 1 ++#define UISUBCLASS_IRDA 2 ++#define UIPROTO_IRDA 0 ++ ++#define UICLASS_VENDOR 0xff ++ ++ ++#define USB_HUB_MAX_DEPTH 5 ++ ++/* ++ * Minimum time a device needs to be powered down to go through ++ * a power cycle. XXX Are these time in the spec? ++ */ ++#define USB_POWER_DOWN_TIME 200 /* ms */ ++#define USB_PORT_POWER_DOWN_TIME 100 /* ms */ ++ ++#if 0 ++/* These are the values from the spec. */ ++#define USB_PORT_RESET_DELAY 10 /* ms */ ++#define USB_PORT_ROOT_RESET_DELAY 50 /* ms */ ++#define USB_PORT_RESET_RECOVERY 10 /* ms */ ++#define USB_PORT_POWERUP_DELAY 100 /* ms */ ++#define USB_SET_ADDRESS_SETTLE 2 /* ms */ ++#define USB_RESUME_DELAY (20*5) /* ms */ ++#define USB_RESUME_WAIT 10 /* ms */ ++#define USB_RESUME_RECOVERY 10 /* ms */ ++#define USB_EXTRA_POWER_UP_TIME 0 /* ms */ ++#else ++/* Allow for marginal (i.e. non-conforming) devices. */ ++#define USB_PORT_RESET_DELAY 50 /* ms */ ++#define USB_PORT_ROOT_RESET_DELAY 250 /* ms */ ++#define USB_PORT_RESET_RECOVERY 250 /* ms */ ++#define USB_PORT_POWERUP_DELAY 300 /* ms */ ++#define USB_SET_ADDRESS_SETTLE 10 /* ms */ ++#define USB_RESUME_DELAY (50*5) /* ms */ ++#define USB_RESUME_WAIT 50 /* ms */ ++#define USB_RESUME_RECOVERY 50 /* ms */ ++#define USB_EXTRA_POWER_UP_TIME 20 /* ms */ ++#endif ++ ++#define USB_MIN_POWER 100 /* mA */ ++#define USB_MAX_POWER 500 /* mA */ ++ ++#define USB_BUS_RESET_DELAY 100 /* ms XXX?*/ ++ ++ ++#define USB_UNCONFIG_NO 0 ++#define USB_UNCONFIG_INDEX (-1) ++ ++/*** ioctl() related stuff ***/ ++ ++struct usb_ctl_request { ++ int ucr_addr; ++ usb_device_request_t ucr_request; ++ void *ucr_data; ++ int ucr_flags; ++#define USBD_SHORT_XFER_OK 0x04 /* allow short reads */ ++ int ucr_actlen; /* actual length transferred */ ++}; ++ ++struct usb_alt_interface { ++ int uai_config_index; ++ int uai_interface_index; ++ int uai_alt_no; ++}; ++ ++#define USB_CURRENT_CONFIG_INDEX (-1) ++#define USB_CURRENT_ALT_INDEX (-1) ++ ++struct usb_config_desc { ++ int ucd_config_index; ++ usb_config_descriptor_t ucd_desc; ++}; ++ ++struct usb_interface_desc { ++ int uid_config_index; ++ int uid_interface_index; ++ int uid_alt_index; ++ usb_interface_descriptor_t uid_desc; ++}; ++ ++struct usb_endpoint_desc { ++ int ued_config_index; ++ int ued_interface_index; ++ int ued_alt_index; ++ int ued_endpoint_index; ++ usb_endpoint_descriptor_t ued_desc; ++}; ++ ++struct usb_full_desc { ++ int ufd_config_index; ++ u_int ufd_size; ++ u_char *ufd_data; ++}; ++ ++struct usb_string_desc { ++ int usd_string_index; ++ int usd_language_id; ++ usb_string_descriptor_t usd_desc; ++}; ++ ++struct usb_ctl_report_desc { ++ int ucrd_size; ++ u_char ucrd_data[1024]; /* filled data size will vary */ ++}; ++ ++typedef struct { u_int32_t cookie; } usb_event_cookie_t; ++ ++#define USB_MAX_DEVNAMES 4 ++#define USB_MAX_DEVNAMELEN 16 ++struct usb_device_info { ++ u_int8_t udi_bus; ++ u_int8_t udi_addr; /* device address */ ++ usb_event_cookie_t udi_cookie; ++ char udi_product[USB_MAX_STRING_LEN]; ++ char udi_vendor[USB_MAX_STRING_LEN]; ++ char udi_release[8]; ++ u_int16_t udi_productNo; ++ u_int16_t udi_vendorNo; ++ u_int16_t udi_releaseNo; ++ u_int8_t udi_class; ++ u_int8_t udi_subclass; ++ u_int8_t udi_protocol; ++ u_int8_t udi_config; ++ u_int8_t udi_speed; ++#define USB_SPEED_LOW 1 ++#define USB_SPEED_FULL 2 ++#define USB_SPEED_HIGH 3 ++ int udi_power; /* power consumption in mA, 0 if selfpowered */ ++ int udi_nports; ++ char udi_devnames[USB_MAX_DEVNAMES][USB_MAX_DEVNAMELEN]; ++ u_int8_t udi_ports[16];/* hub only: addresses of devices on ports */ ++#define USB_PORT_ENABLED 0xff ++#define USB_PORT_SUSPENDED 0xfe ++#define USB_PORT_POWERED 0xfd ++#define USB_PORT_DISABLED 0xfc ++}; ++ ++struct usb_ctl_report { ++ int ucr_report; ++ u_char ucr_data[1024]; /* filled data size will vary */ ++}; ++ ++struct usb_device_stats { ++ u_long uds_requests[4]; /* indexed by transfer type UE_* */ ++}; ++ ++ ++ ++ ++#define WUSB_MIN_IE 0x80 ++#define WUSB_WCTA_IE 0x80 ++#define WUSB_WCONNECTACK_IE 0x81 ++#define WUSB_WHOSTINFO_IE 0x82 ++#define WUHI_GET_CA(_bmAttributes_) ((_bmAttributes_) & 0x3) ++#define WUHI_CA_RECONN 0x00 ++#define WUHI_CA_LIMITED 0x01 ++#define WUHI_CA_ALL 0x03 ++#define WUHI_GET_MLSI(_bmAttributes_) (((_bmAttributes_) & 0x38) >> 3) ++#define WUSB_WCHCHANGEANNOUNCE_IE 0x83 ++#define WUSB_WDEV_DISCONNECT_IE 0x84 ++#define WUSB_WHOST_DISCONNECT_IE 0x85 ++#define WUSB_WRELEASE_CHANNEL_IE 0x86 ++#define WUSB_WWORK_IE 0x87 ++#define WUSB_WCHANNEL_STOP_IE 0x88 ++#define WUSB_WDEV_KEEPALIVE_IE 0x89 ++#define WUSB_WISOCH_DISCARD_IE 0x8A ++#define WUSB_WRESETDEVICE_IE 0x8B ++#define WUSB_WXMIT_PACKET_ADJUST_IE 0x8C ++#define WUSB_MAX_IE 0x8C ++ ++/* Device Notification Types */ ++ ++#define WUSB_DN_MIN 0x01 ++#define WUSB_DN_CONNECT 0x01 ++# define WUSB_DA_OLDCONN 0x00 ++# define WUSB_DA_NEWCONN 0x01 ++# define WUSB_DA_SELF_BEACON 0x02 ++# define WUSB_DA_DIR_BEACON 0x04 ++# define WUSB_DA_NO_BEACON 0x06 ++#define WUSB_DN_DISCONNECT 0x02 ++#define WUSB_DN_EPRDY 0x03 ++#define WUSB_DN_MASAVAILCHANGED 0x04 ++#define WUSB_DN_REMOTEWAKEUP 0x05 ++#define WUSB_DN_SLEEP 0x06 ++#define WUSB_DN_ALIVE 0x07 ++#define WUSB_DN_MAX 0x07 ++ ++ ++/* WUSB Handshake Data. Used during the SET/GET HANDSHAKE requests */ ++typedef struct wusb_hndshk_data { ++ uint8_t bMessageNumber; ++ uint8_t bStatus; ++ uint8_t tTKID[3]; ++ uint8_t bReserved; ++ uint8_t CDID[16]; ++ uint8_t Nonce[16]; ++ uint8_t MIC[8]; ++} UPACKED wusb_hndshk_data_t; ++#define WUSB_HANDSHAKE_LEN_FOR_MIC 38 ++ ++/* WUSB Connection Context */ ++typedef struct wusb_conn_context { ++ uint8_t CHID [16]; ++ uint8_t CDID [16]; ++ uint8_t CK [16]; ++} UPACKED wusb_conn_context_t; ++ ++/* WUSB Security Descriptor */ ++typedef struct wusb_security_desc { ++ uint8_t bLength; ++ uint8_t bDescriptorType; ++ uint16_t wTotalLength; ++ uint8_t bNumEncryptionTypes; ++} UPACKED wusb_security_desc_t; ++ ++/* WUSB Encryption Type Descriptor */ ++typedef struct wusb_encrypt_type_desc { ++ uint8_t bLength; ++ uint8_t bDescriptorType; ++ ++ uint8_t bEncryptionType; ++#define WUETD_UNSECURE 0 ++#define WUETD_WIRED 1 ++#define WUETD_CCM_1 2 ++#define WUETD_RSA_1 3 ++ ++ uint8_t bEncryptionValue; ++ uint8_t bAuthKeyIndex; ++} UPACKED wusb_encrypt_type_desc_t; ++ ++/* WUSB Key Descriptor */ ++typedef struct wusb_key_desc { ++ uint8_t bLength; ++ uint8_t bDescriptorType; ++ uint8_t tTKID[3]; ++ uint8_t bReserved; ++ uint8_t KeyData[1]; /* variable length */ ++} UPACKED wusb_key_desc_t; ++ ++/* WUSB BOS Descriptor (Binary device Object Store) */ ++typedef struct wusb_bos_desc { ++ uint8_t bLength; ++ uint8_t bDescriptorType; ++ uint16_t wTotalLength; ++ uint8_t bNumDeviceCaps; ++} UPACKED wusb_bos_desc_t; ++ ++ ++/* Device Capability Type Codes */ ++#define WUSB_DEVICE_CAPABILITY_WIRELESS_USB 0x01 ++ ++/* Device Capability Descriptor */ ++typedef struct wusb_dev_cap_desc { ++ uint8_t bLength; ++ uint8_t bDescriptorType; ++ uint8_t bDevCapabilityType; ++ uint8_t caps[1]; /* Variable length */ ++} UPACKED wusb_dev_cap_desc_t; ++ ++/* Device Capability Descriptor */ ++typedef struct wusb_dev_cap_uwb_desc { ++ uint8_t bLength; ++ uint8_t bDescriptorType; ++ uint8_t bDevCapabilityType; ++ uint8_t bmAttributes; ++ uint16_t wPHYRates; /* Bitmap */ ++ uint8_t bmTFITXPowerInfo; ++ uint8_t bmFFITXPowerInfo; ++ uint16_t bmBandGroup; ++ uint8_t bReserved; ++} UPACKED wusb_dev_cap_uwb_desc_t; ++ ++/* Wireless USB Endpoint Companion Descriptor */ ++typedef struct wusb_endpoint_companion_desc { ++ uint8_t bLength; ++ uint8_t bDescriptorType; ++ uint8_t bMaxBurst; ++ uint8_t bMaxSequence; ++ uint16_t wMaxStreamDelay; ++ uint16_t wOverTheAirPacketSize; ++ uint8_t bOverTheAirInterval; ++ uint8_t bmCompAttributes; ++} UPACKED wusb_endpoint_companion_desc_t; ++ ++ ++/* Wireless USB Numeric Association M1 Data Structure */ ++typedef struct wusb_m1_data { ++ uint8_t version; ++ uint16_t langId; ++ uint8_t deviceFriendlyNameLength; ++ uint8_t sha_256_m3[32]; ++ uint8_t deviceFriendlyName[256]; ++} UPACKED wusb_m1_data_t; ++ ++typedef struct wusb_m2_data { ++ uint8_t version; ++ uint16_t langId; ++ uint8_t hostFriendlyNameLength; ++ uint8_t pkh[384]; ++ uint8_t hostFriendlyName[256]; ++} UPACKED wusb_m2_data_t; ++ ++typedef struct wusb_m3_data { ++ uint8_t pkd[384]; ++ uint8_t nd; ++} UPACKED wusb_m3_data_t; ++ ++typedef struct wusb_m4_data { ++ uint32_t _attributeTypeIdAndLength_1; ++ uint16_t associationTypeId; ++ ++ uint32_t _attributeTypeIdAndLength_2; ++ uint16_t associationSubTypeId; ++ ++ uint32_t _attributeTypeIdAndLength_3; ++ uint32_t length; ++ ++ uint32_t _attributeTypeIdAndLength_4; ++ uint32_t associationStatus; ++ ++ uint32_t _attributeTypeIdAndLength_5; ++ uint8_t chid[16]; ++ ++ uint32_t _attributeTypeIdAndLength_6; ++ uint8_t cdid[16]; ++ ++ uint32_t _attributeTypeIdAndLength_7; ++ uint8_t bandGroups[2]; ++} UPACKED wusb_m4_data_t; ++ ++ ++ ++ ++#endif /* _USB_H_ */ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/Makefile +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/Makefile 2013-07-26 19:31:20.000000000 +0000 +@@ -0,0 +1,78 @@ ++# ++# Makefile for DWC_otg Highspeed USB controller driver ++# ++ ++ifneq ($(KERNELRELEASE),) ++ ++ifeq ($(BUS_INTERFACE),) ++ # BUS_INTERFACE = -DLM_INTERFACE ++ BUS_INTERFACE = -DPLATFORM_INTERFACE=1 ++endif ++ ++CPPFLAGS += -DDEBUG ++ ++# Use one of the following flags to compile the software in host-only or ++# device-only mode. ++#CPPFLAGS += -DDWC_HOST_ONLY ++#CPPFLAGS += -DDWC_DEVICE_ONLY ++ ++CPPFLAGS += -Dlinux -DDWC_HS_ELECT_TST ++#CGG: CPPFLAGS += -DDWC_EN_ISOC ++CPPFLAGS += -I$(obj)/../dwc_common_port ++#CPPFLAGS += -I$(PORTLIB) ++CPPFLAGS += -DDWC_LINUX ++CPPFLAGS += $(CFI) ++CPPFLAGS += $(BUS_INTERFACE) ++ ++obj-$(CONFIG_USB_DWCOTG) += dwc_otg.o ++ ++dwc_otg-objs := dwc_otg_driver.o dwc_otg_attr.o ++dwc_otg-objs += dwc_otg_cil.o dwc_otg_cil_intr.o ++dwc_otg-objs += dwc_otg_pcd_linux.o dwc_otg_pcd.o dwc_otg_pcd_intr.o ++dwc_otg-objs += dwc_otg_hcd.o dwc_otg_hcd_linux.o dwc_otg_hcd_intr.o dwc_otg_hcd_queue.o dwc_otg_hcd_ddma.o ++ifneq ($(CFI),) ++dwc_otg-objs += dwc_otg_cfi.o ++endif ++ ++kernrelwd := $(subst ., ,$(KERNELRELEASE)) ++kernrel3 := $(word 1,$(kernrelwd)).$(word 2,$(kernrelwd)).$(word 3,$(kernrelwd)) ++ ++ifneq ($(kernrel3),2.6.20) ++EXTRA_CFLAGS += $(CPPFLAGS) ++endif ++ ++else ++ ++PWD := $(shell pwd) ++PORTLIB := $(PWD)/../dwc_common_port ++ ++# Command paths ++CTAGS := $(CTAGS) ++DOXYGEN := $(DOXYGEN) ++ ++default: portlib ++ $(MAKE) -C$(KDIR) M=$(PWD) ARCH=$(ARCH) CROSS_COMPILE=$(CROSS_COMPILE) modules ++ ++install: default ++ifneq ($(INSTALL_MOD_PATH),) ++ $(MAKE) -C$(KDIR) M=$(PORTLIB) modules_install ++ $(MAKE) -C$(KDIR) M=$(PWD) modules_install ++else ++ @echo "No install path defined" ++endif ++ ++portlib: ++ $(MAKE) -C$(KDIR) M=$(PORTLIB) ARCH=$(ARCH) CROSS_COMPILE=$(CROSS_COMPILE) modules ++ cp $(PORTLIB)/Module.symvers $(PWD)/ ++ ++docs: $(wildcard *.[hc]) doc/doxygen.cfg ++ $(DOXYGEN) doc/doxygen.cfg ++ ++tags: $(wildcard *.[hc]) ++ $(CTAGS) -e $(wildcard *.[hc]) $(wildcard linux/*.[hc]) $(wildcard $(KDIR)/include/linux/usb*.h) ++ ++ ++clean: ++ rm -rf *.o *.ko .*cmd *.mod.c .tmp_versions ++ ++endif +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/doxygen.cfg +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/doxygen.cfg 2013-07-26 19:31:20.000000000 +0000 +@@ -0,0 +1,224 @@ ++# Doxyfile 1.3.9.1 ++ ++#--------------------------------------------------------------------------- ++# Project related configuration options ++#--------------------------------------------------------------------------- ++PROJECT_NAME = "DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver" ++PROJECT_NUMBER = v2.90a ++OUTPUT_DIRECTORY = ./doc/ ++CREATE_SUBDIRS = NO ++OUTPUT_LANGUAGE = English ++BRIEF_MEMBER_DESC = YES ++REPEAT_BRIEF = YES ++ABBREVIATE_BRIEF = "The $name class" \ ++ "The $name widget" \ ++ "The $name file" \ ++ is \ ++ provides \ ++ specifies \ ++ contains \ ++ represents \ ++ a \ ++ an \ ++ the ++ALWAYS_DETAILED_SEC = NO ++INLINE_INHERITED_MEMB = NO ++FULL_PATH_NAMES = NO ++STRIP_FROM_PATH = ++STRIP_FROM_INC_PATH = ++SHORT_NAMES = NO ++JAVADOC_AUTOBRIEF = YES ++MULTILINE_CPP_IS_BRIEF = NO ++INHERIT_DOCS = YES ++DISTRIBUTE_GROUP_DOC = NO ++TAB_SIZE = 8 ++ALIASES = ++OPTIMIZE_OUTPUT_FOR_C = YES ++OPTIMIZE_OUTPUT_JAVA = NO ++SUBGROUPING = YES ++#--------------------------------------------------------------------------- ++# Build related configuration options ++#--------------------------------------------------------------------------- ++EXTRACT_ALL = NO ++EXTRACT_PRIVATE = YES ++EXTRACT_STATIC = YES ++EXTRACT_LOCAL_CLASSES = YES ++EXTRACT_LOCAL_METHODS = NO ++HIDE_UNDOC_MEMBERS = NO ++HIDE_UNDOC_CLASSES = NO ++HIDE_FRIEND_COMPOUNDS = NO ++HIDE_IN_BODY_DOCS = NO ++INTERNAL_DOCS = NO ++CASE_SENSE_NAMES = NO ++HIDE_SCOPE_NAMES = NO ++SHOW_INCLUDE_FILES = YES ++INLINE_INFO = YES ++SORT_MEMBER_DOCS = NO ++SORT_BRIEF_DOCS = NO ++SORT_BY_SCOPE_NAME = NO ++GENERATE_TODOLIST = YES ++GENERATE_TESTLIST = YES ++GENERATE_BUGLIST = YES ++GENERATE_DEPRECATEDLIST= YES ++ENABLED_SECTIONS = ++MAX_INITIALIZER_LINES = 30 ++SHOW_USED_FILES = YES ++SHOW_DIRECTORIES = YES ++#--------------------------------------------------------------------------- ++# configuration options related to warning and progress messages ++#--------------------------------------------------------------------------- ++QUIET = YES ++WARNINGS = YES ++WARN_IF_UNDOCUMENTED = NO ++WARN_IF_DOC_ERROR = YES ++WARN_FORMAT = "$file:$line: $text" ++WARN_LOGFILE = ++#--------------------------------------------------------------------------- ++# configuration options related to the input files ++#--------------------------------------------------------------------------- ++INPUT = . ++FILE_PATTERNS = *.c \ ++ *.h \ ++ ./linux/*.c \ ++ ./linux/*.h ++RECURSIVE = NO ++EXCLUDE = ./test/ \ ++ ./dwc_otg/.AppleDouble/ ++EXCLUDE_SYMLINKS = YES ++EXCLUDE_PATTERNS = *.mod.* ++EXAMPLE_PATH = ++EXAMPLE_PATTERNS = * ++EXAMPLE_RECURSIVE = NO ++IMAGE_PATH = ++INPUT_FILTER = ++FILTER_PATTERNS = ++FILTER_SOURCE_FILES = NO ++#--------------------------------------------------------------------------- ++# configuration options related to source browsing ++#--------------------------------------------------------------------------- ++SOURCE_BROWSER = YES ++INLINE_SOURCES = NO ++STRIP_CODE_COMMENTS = YES ++REFERENCED_BY_RELATION = NO ++REFERENCES_RELATION = NO ++VERBATIM_HEADERS = NO ++#--------------------------------------------------------------------------- ++# configuration options related to the alphabetical class index ++#--------------------------------------------------------------------------- ++ALPHABETICAL_INDEX = NO ++COLS_IN_ALPHA_INDEX = 5 ++IGNORE_PREFIX = ++#--------------------------------------------------------------------------- ++# configuration options related to the HTML output ++#--------------------------------------------------------------------------- ++GENERATE_HTML = YES ++HTML_OUTPUT = html ++HTML_FILE_EXTENSION = .html ++HTML_HEADER = ++HTML_FOOTER = ++HTML_STYLESHEET = ++HTML_ALIGN_MEMBERS = YES ++GENERATE_HTMLHELP = NO ++CHM_FILE = ++HHC_LOCATION = ++GENERATE_CHI = NO ++BINARY_TOC = NO ++TOC_EXPAND = NO ++DISABLE_INDEX = NO ++ENUM_VALUES_PER_LINE = 4 ++GENERATE_TREEVIEW = YES ++TREEVIEW_WIDTH = 250 ++#--------------------------------------------------------------------------- ++# configuration options related to the LaTeX output ++#--------------------------------------------------------------------------- ++GENERATE_LATEX = NO ++LATEX_OUTPUT = latex ++LATEX_CMD_NAME = latex ++MAKEINDEX_CMD_NAME = makeindex ++COMPACT_LATEX = NO ++PAPER_TYPE = a4wide ++EXTRA_PACKAGES = ++LATEX_HEADER = ++PDF_HYPERLINKS = NO ++USE_PDFLATEX = NO ++LATEX_BATCHMODE = NO ++LATEX_HIDE_INDICES = NO ++#--------------------------------------------------------------------------- ++# configuration options related to the RTF output ++#--------------------------------------------------------------------------- ++GENERATE_RTF = NO ++RTF_OUTPUT = rtf ++COMPACT_RTF = NO ++RTF_HYPERLINKS = NO ++RTF_STYLESHEET_FILE = ++RTF_EXTENSIONS_FILE = ++#--------------------------------------------------------------------------- ++# configuration options related to the man page output ++#--------------------------------------------------------------------------- ++GENERATE_MAN = NO ++MAN_OUTPUT = man ++MAN_EXTENSION = .3 ++MAN_LINKS = NO ++#--------------------------------------------------------------------------- ++# configuration options related to the XML output ++#--------------------------------------------------------------------------- ++GENERATE_XML = NO ++XML_OUTPUT = xml ++XML_SCHEMA = ++XML_DTD = ++XML_PROGRAMLISTING = YES ++#--------------------------------------------------------------------------- ++# configuration options for the AutoGen Definitions output ++#--------------------------------------------------------------------------- ++GENERATE_AUTOGEN_DEF = NO ++#--------------------------------------------------------------------------- ++# configuration options related to the Perl module output ++#--------------------------------------------------------------------------- ++GENERATE_PERLMOD = NO ++PERLMOD_LATEX = NO ++PERLMOD_PRETTY = YES ++PERLMOD_MAKEVAR_PREFIX = ++#--------------------------------------------------------------------------- ++# Configuration options related to the preprocessor ++#--------------------------------------------------------------------------- ++ENABLE_PREPROCESSING = YES ++MACRO_EXPANSION = YES ++EXPAND_ONLY_PREDEF = YES ++SEARCH_INCLUDES = YES ++INCLUDE_PATH = ++INCLUDE_FILE_PATTERNS = ++PREDEFINED = DEVICE_ATTR DWC_EN_ISOC ++EXPAND_AS_DEFINED = DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW DWC_OTG_DEVICE_ATTR_BITFIELD_STORE DWC_OTG_DEVICE_ATTR_BITFIELD_RW DWC_OTG_DEVICE_ATTR_BITFIELD_RO DWC_OTG_DEVICE_ATTR_REG_SHOW DWC_OTG_DEVICE_ATTR_REG_STORE DWC_OTG_DEVICE_ATTR_REG32_RW DWC_OTG_DEVICE_ATTR_REG32_RO DWC_EN_ISOC ++SKIP_FUNCTION_MACROS = NO ++#--------------------------------------------------------------------------- ++# Configuration::additions related to external references ++#--------------------------------------------------------------------------- ++TAGFILES = ++GENERATE_TAGFILE = ++ALLEXTERNALS = NO ++EXTERNAL_GROUPS = YES ++PERL_PATH = /usr/bin/perl ++#--------------------------------------------------------------------------- ++# Configuration options related to the dot tool ++#--------------------------------------------------------------------------- ++CLASS_DIAGRAMS = YES ++HIDE_UNDOC_RELATIONS = YES ++HAVE_DOT = NO ++CLASS_GRAPH = YES ++COLLABORATION_GRAPH = YES ++UML_LOOK = NO ++TEMPLATE_RELATIONS = NO ++INCLUDE_GRAPH = YES ++INCLUDED_BY_GRAPH = YES ++CALL_GRAPH = NO ++GRAPHICAL_HIERARCHY = YES ++DOT_IMAGE_FORMAT = png ++DOT_PATH = ++DOTFILE_DIRS = ++MAX_DOT_GRAPH_DEPTH = 1000 ++GENERATE_LEGEND = YES ++DOT_CLEANUP = YES ++#--------------------------------------------------------------------------- ++# Configuration::additions related to the search engine ++#--------------------------------------------------------------------------- ++SEARCHENGINE = NO +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/annotated.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/annotated.html 2013-07-26 19:31:20.000000000 +0000 +@@ -0,0 +1,120 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Structures ++ ++ ++ ++ ++
++
++
++
++

DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver Data Structures

Here are the data structures with brief descriptions: ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
_ddma_align_buffer_setupDescriptor DMA Alignment Buffer setup structure
_ddma_concat_buffer_setupDescriptor DMA Concatenation Buffer setup structure
_ddma_concat_buffer_setup_hdrDescriptor DMA Concatenation Buffer setup structure
_ddma_sg_buffer_setupDescriptor DMA SG Buffer setup structure (SG buffer)
_rx_fifo_size_setupTransmit FIFO Size setup structure
_tx_fifo_size_setupTransmit FIFO Size setup structure
cfi_all_features_headerThis structure is the header of the Core Features dataset returned to the Host
cfi_dma_buff
cfi_epThe CFI wrapper of the enabled and activated dwc_otg_pcd_ep structures
cfi_feature_desc_headerThis structure is a header of the Core Feature descriptor dataset returned to the Host after the VEN_CORE_GET_FEATURES request
cfi_opsThis is the interface for the CFI operations
cfi_stringThis structure describes a NULL terminated string referenced by its id field
cfi_usb_ctrlrequestStruct cfi_usb_ctrlrequest - the CFI implementation of the struct usb_ctrlrequest This structure encapsulates the standard usb_ctrlrequest and adds a pointer to the data returned in the data stage of a 3-stage Control Write requests
cfiobject
daint_dataThis union represents the bit fields in the Device All EP Interrupt and Mask Registers
dcfg_dataThis union represents the bit fields in the Device Configuration Register
dctl_dataThis union represents the bit fields in the Device Control Register
depctl_dataThis union represents the bit fields in the Device EP Control Register
deptsiz0_dataThis union represents the bit fields in the Device EP 0 Transfer Size Register
deptsiz_dataThis union represents the bit fields in the Device EP Transfer Size Register
dev_dma_desc_stsThis union represents the bit fields in the DMA Descriptor status quadlet
device_grxsts_dataThis union represents the bit fields in the Device Receive Status Read and Pop Registers (GRXSTSR, GRXSTSP) Read the register into the d32 element then read out the bits using the bit elements
diepint_dataThis union represents the bit fields in the Device IN EP Interrupt Register and the Device IN EP Common Mask Register
doepint_dataThis union represents the bit fields in the Device OUT EP Interrupt Registerand Device OUT EP Common Interrupt Mask Register
dsts_dataThis union represents the bit fields in the Device Status Register
dthrctl_dataThis union represents Threshold control Register
    ++
  • Read and write the register into the d32 member
++
dtknq1_dataThis union represents the bit fields in the Device IN Token Queue Read Registers
dtxfsts_dataThis union represents the bit fields in the Transmit FIFO Status Register (DTXFSTS)
dwc_epThe dwc_ep structure represents the state of a single endpoint when acting in device mode
dwc_hcHost channel descriptor
dwc_otg_cil_callbacksDWC_otg CIL callback structure
dwc_otg_core_global_regsDWC_otg Core registers
dwc_otg_core_ifThe dwc_otg_core_if structure contains information needed to manage the DWC_otg controller acting in either host or device mode
dwc_otg_core_paramsThe following parameters may be specified when starting the module
dwc_otg_dev_dma_descDMA Descriptor structure
dwc_otg_dev_global_regsDevice Global Registers
dwc_otg_dev_ifThe dwc_otg_dev_if structure contains information needed to manage the DWC_otg controller acting in device mode
dwc_otg_dev_in_ep_regsDevice Logical IN Endpoint-Specific Registers
dwc_otg_dev_out_ep_regsDevice Logical OUT Endpoint-Specific Registers
dwc_otg_deviceThis structure is a wrapper that encapsulates the driver components used to manage a single DWC_otg controller
dwc_otg_driver_module_params
dwc_otg_hc_regsHost Channel Specific Registers
dwc_otg_hcdThis structure holds the state of the HCD, including the non-periodic and periodic schedules
dwc_otg_hcd::dwc_otg_hcd_internal_flagsInternal DWC HCD Flags
dwc_otg_hcd_function_ops
dwc_otg_hcd_iso_packet_desc
dwc_otg_hcd_pipe_info
dwc_otg_hcd_urb
dwc_otg_host_dma_descHost-mode DMA Descriptor structure
dwc_otg_host_global_regsThe Host Global Registers structure defines the size and relative field offsets for the Host Mode Global Registers
dwc_otg_host_ifOTG Host Interface Structure
dwc_otg_pcdDWC_otg PCD Structure
dwc_otg_pcd_epPCD EP structure
dwc_otg_pcd_function_opsFunction Driver Ops Data Structure
dwc_otg_pcd_requestDWC_otg request structure
dwc_otg_qhA Queue Head (QH) holds the static characteristics of an endpoint and maintains a list of transfers (QTDs) for that endpoint
dwc_otg_qtdA Queue Transfer Descriptor (QTD) holds the state of a bulk, control, interrupt, or isochronous transfer
fifosize_dataThis union represents the bit fields in the FIFO Size Registers (HPTXFSIZ, GNPTXFSIZ, DPTXFSIZn, DIEPTXFn)
gadget_wrapper
gahbcfg_dataThis union represents the bit fields of the Core AHB Configuration Register (GAHBCFG)
gi2cctl_dataThis union represents the bit fields in the I2C Control Register (I2CCTL)
gintmsk_dataThis union represents the bit fields of the Core Interrupt Mask Register (GINTMSK)
gintsts_dataThis union represents the bit fields of the Core Interrupt Register (GINTSTS)
glpmctl_dataThis union represents the bit fields of the Core LPM Configuration Register (GLPMCFG)
gnptxsts_dataThis union represents the bit fields in the Non-Periodic Transmit FIFO/Queue Status Register (GNPTXSTS)
gotgctl_dataThis union represents the bit fields of the Core OTG Control and Status Register (GOTGCTL)
gotgint_dataThis union represents the bit fields of the Core OTG Interrupt Register (GOTGINT)
grstctl_dataThis union represents the bit fields of the Core Reset Register (GRSTCTL)
gusbcfg_dataThis union represents the bit fields of the Core USB Configuration Register (GUSBCFG)
haint_dataThis union represents the bit fields in the Host All Interrupt Register
haintmsk_dataThis union represents the bit fields in the Host All Interrupt Register
hcchar_dataThis union represents the bit fields in the Host Channel Characteristics Register
hcdma_dataThis union represents the bit fields in the Host DMA Address Register used in Descriptor DMA mode
hcfg_dataThis union represents the bit fields in the Host Configuration Register
hcint_dataThis union represents the bit fields in the Host All Interrupt Register
hcintmsk_dataThis union represents the bit fields in the Host Channel Interrupt Mask Register
hcsplt_data
hctsiz_dataThis union represents the bit fields in the Host Channel Transfer Size Register
hfir_dataThis union represents the bit fields in the Host Frame Remaing/Number Register
hfnum_dataThis union represents the bit fields in the Host Frame Remaing/Number Register
host_dma_desc_stsThis union represents the bit fields in the DMA Descriptor status quadlet for host mode
host_grxsts_dataThis union represents the bit fields in the Host Receive Status Read and Pop Registers (GRXSTSR, GRXSTSP) Read the register into the d32 element then read out the bits using the bit elements
hprt0_dataThis union represents the bit fields in the Host Port Control and Status Register
hptxsts_data
hwcfg1_dataThis union represents the bit fields in the User HW Config1 Register
hwcfg2_dataThis union represents the bit fields in the User HW Config2 Register
hwcfg3_dataThis union represents the bit fields in the User HW Config3 Register
hwcfg4_dataThis union represents the bit fields in the User HW Config4 Register
iso_pkt_infoInformation for each ISOC packet
pcgcctl_dataThis union represents the bit fields in the Power and Clock Gating Control Register
wrapper_priv_data
zero_dev
++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/doxygen.css +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/doxygen.css 2013-07-26 19:31:20.000000000 +0000 +@@ -0,0 +1,358 @@ ++BODY,H1,H2,H3,H4,H5,H6,P,CENTER,TD,TH,UL,DL,DIV { ++ font-family: Geneva, Arial, Helvetica, sans-serif; ++} ++BODY,TD { ++ font-size: 90%; ++} ++H1 { ++ text-align: center; ++ font-size: 160%; ++} ++H2 { ++ font-size: 120%; ++} ++H3 { ++ font-size: 100%; ++} ++CAPTION { font-weight: bold } ++DIV.qindex { ++ width: 100%; ++ background-color: #e8eef2; ++ border: 1px solid #84b0c7; ++ text-align: center; ++ margin: 2px; ++ padding: 2px; ++ line-height: 140%; ++} ++DIV.nav { ++ width: 100%; ++ background-color: #e8eef2; ++ border: 1px solid #84b0c7; ++ text-align: center; ++ margin: 2px; ++ padding: 2px; ++ line-height: 140%; ++} ++DIV.navtab { ++ background-color: #e8eef2; ++ border: 1px solid #84b0c7; ++ text-align: center; ++ margin: 2px; ++ margin-right: 15px; ++ padding: 2px; ++} ++TD.navtab { ++ font-size: 70%; ++} ++A.qindex { ++ text-decoration: none; ++ font-weight: bold; ++ color: #1A419D; ++} ++A.qindex:visited { ++ text-decoration: none; ++ font-weight: bold; ++ color: #1A419D ++} ++A.qindex:hover { ++ text-decoration: none; ++ background-color: #ddddff; ++} ++A.qindexHL { ++ text-decoration: none; ++ font-weight: bold; ++ background-color: #6666cc; ++ color: #ffffff; ++ border: 1px double #9295C2; ++} ++A.qindexHL:hover { ++ text-decoration: none; ++ background-color: #6666cc; ++ color: #ffffff; ++} ++A.qindexHL:visited { text-decoration: none; background-color: #6666cc; color: #ffffff } ++A.el { text-decoration: none; font-weight: bold } ++A.elRef { font-weight: bold } ++A.code:link { text-decoration: none; font-weight: normal; color: #0000FF} ++A.code:visited { text-decoration: none; font-weight: normal; color: #0000FF} ++A.codeRef:link { font-weight: normal; color: #0000FF} ++A.codeRef:visited { font-weight: normal; color: #0000FF} ++A:hover { text-decoration: none; background-color: #f2f2ff } ++DL.el { margin-left: -1cm } ++.fragment { ++ font-family: monospace, fixed; ++ font-size: 95%; ++} ++PRE.fragment { ++ border: 1px solid #CCCCCC; ++ background-color: #f5f5f5; ++ margin-top: 4px; ++ margin-bottom: 4px; ++ margin-left: 2px; ++ margin-right: 8px; ++ padding-left: 6px; ++ padding-right: 6px; ++ padding-top: 4px; ++ padding-bottom: 4px; ++} ++DIV.ah { background-color: black; font-weight: bold; color: #ffffff; margin-bottom: 3px; margin-top: 3px } ++ ++DIV.groupHeader { ++ margin-left: 16px; ++ margin-top: 12px; ++ margin-bottom: 6px; ++ font-weight: bold; ++} ++DIV.groupText { margin-left: 16px; font-style: italic; font-size: 90% } ++BODY { ++ background: white; ++ color: black; ++ margin-right: 20px; ++ margin-left: 20px; ++} ++TD.indexkey { ++ background-color: #e8eef2; ++ font-weight: bold; ++ padding-right : 10px; ++ padding-top : 2px; ++ padding-left : 10px; ++ padding-bottom : 2px; ++ margin-left : 0px; ++ margin-right : 0px; ++ margin-top : 2px; ++ margin-bottom : 2px; ++ border: 1px solid #CCCCCC; ++} ++TD.indexvalue { ++ background-color: #e8eef2; ++ font-style: italic; ++ padding-right : 10px; ++ padding-top : 2px; ++ padding-left : 10px; ++ padding-bottom : 2px; ++ margin-left : 0px; ++ margin-right : 0px; ++ margin-top : 2px; ++ margin-bottom : 2px; ++ border: 1px solid #CCCCCC; ++} ++TR.memlist { ++ background-color: #f0f0f0; ++} ++P.formulaDsp { text-align: center; } ++IMG.formulaDsp { } ++IMG.formulaInl { vertical-align: middle; } ++SPAN.keyword { color: #008000 } ++SPAN.keywordtype { color: #604020 } ++SPAN.keywordflow { color: #e08000 } ++SPAN.comment { color: #800000 } ++SPAN.preprocessor { color: #806020 } ++SPAN.stringliteral { color: #002080 } ++SPAN.charliteral { color: #008080 } ++.mdescLeft { ++ padding: 0px 8px 4px 8px; ++ font-size: 80%; ++ font-style: italic; ++ background-color: #FAFAFA; ++ border-top: 1px none #E0E0E0; ++ border-right: 1px none #E0E0E0; ++ border-bottom: 1px none #E0E0E0; ++ border-left: 1px none #E0E0E0; ++ margin: 0px; ++} ++.mdescRight { ++ padding: 0px 8px 4px 8px; ++ font-size: 80%; ++ font-style: italic; ++ background-color: #FAFAFA; ++ border-top: 1px none #E0E0E0; ++ border-right: 1px none #E0E0E0; ++ border-bottom: 1px none #E0E0E0; ++ border-left: 1px none #E0E0E0; ++ margin: 0px; ++} ++.memItemLeft { ++ padding: 1px 0px 0px 8px; ++ margin: 4px; ++ border-top-width: 1px; ++ border-right-width: 1px; ++ border-bottom-width: 1px; ++ border-left-width: 1px; ++ border-top-color: #E0E0E0; ++ border-right-color: #E0E0E0; ++ border-bottom-color: #E0E0E0; ++ border-left-color: #E0E0E0; ++ border-top-style: solid; ++ border-right-style: none; ++ border-bottom-style: none; ++ border-left-style: none; ++ background-color: #FAFAFA; ++ font-size: 80%; ++} ++.memItemRight { ++ padding: 1px 8px 0px 8px; ++ margin: 4px; ++ border-top-width: 1px; ++ border-right-width: 1px; ++ border-bottom-width: 1px; ++ border-left-width: 1px; ++ border-top-color: #E0E0E0; ++ border-right-color: #E0E0E0; ++ border-bottom-color: #E0E0E0; ++ border-left-color: #E0E0E0; ++ border-top-style: solid; ++ border-right-style: none; ++ border-bottom-style: none; ++ border-left-style: none; ++ background-color: #FAFAFA; ++ font-size: 80%; ++} ++.memTemplItemLeft { ++ padding: 1px 0px 0px 8px; ++ margin: 4px; ++ border-top-width: 1px; ++ border-right-width: 1px; ++ border-bottom-width: 1px; ++ border-left-width: 1px; ++ border-top-color: #E0E0E0; ++ border-right-color: #E0E0E0; ++ border-bottom-color: #E0E0E0; ++ border-left-color: #E0E0E0; ++ border-top-style: none; ++ border-right-style: none; ++ border-bottom-style: none; ++ border-left-style: none; ++ background-color: #FAFAFA; ++ font-size: 80%; ++} ++.memTemplItemRight { ++ padding: 1px 8px 0px 8px; ++ margin: 4px; ++ border-top-width: 1px; ++ border-right-width: 1px; ++ border-bottom-width: 1px; ++ border-left-width: 1px; ++ border-top-color: #E0E0E0; ++ border-right-color: #E0E0E0; ++ border-bottom-color: #E0E0E0; ++ border-left-color: #E0E0E0; ++ border-top-style: none; ++ border-right-style: none; ++ border-bottom-style: none; ++ border-left-style: none; ++ background-color: #FAFAFA; ++ font-size: 80%; ++} ++.memTemplParams { ++ padding: 1px 0px 0px 8px; ++ margin: 4px; ++ border-top-width: 1px; ++ border-right-width: 1px; ++ border-bottom-width: 1px; ++ border-left-width: 1px; ++ border-top-color: #E0E0E0; ++ border-right-color: #E0E0E0; ++ border-bottom-color: #E0E0E0; ++ border-left-color: #E0E0E0; ++ border-top-style: solid; ++ border-right-style: none; ++ border-bottom-style: none; ++ border-left-style: none; ++ color: #606060; ++ background-color: #FAFAFA; ++ font-size: 80%; ++} ++.search { color: #003399; ++ font-weight: bold; ++} ++FORM.search { ++ margin-bottom: 0px; ++ margin-top: 0px; ++} ++INPUT.search { font-size: 75%; ++ color: #000080; ++ font-weight: normal; ++ background-color: #e8eef2; ++} ++TD.tiny { font-size: 75%; ++} ++a { ++ color: #1A41A8; ++} ++a:visited { ++ color: #2A3798; ++} ++.dirtab { padding: 4px; ++ border-collapse: collapse; ++ border: 1px solid #84b0c7; ++} ++TH.dirtab { background: #e8eef2; ++ font-weight: bold; ++} ++HR { height: 1px; ++ border: none; ++ border-top: 1px solid black; ++} ++ ++/* Style for detailed member documentation */ ++.memtemplate { ++ font-size: 80%; ++ color: #606060; ++ font-weight: normal; ++} ++.memnav { ++ background-color: #e8eef2; ++ border: 1px solid #84b0c7; ++ text-align: center; ++ margin: 2px; ++ margin-right: 15px; ++ padding: 2px; ++} ++.memitem { ++ padding: 4px; ++ background-color: #eef3f5; ++ border-width: 1px; ++ border-style: solid; ++ border-color: #dedeee; ++ -moz-border-radius: 8px 8px 8px 8px; ++} ++.memname { ++ white-space: nowrap; ++ font-weight: bold; ++} ++.memdoc{ ++ padding-left: 10px; ++} ++.memproto { ++ background-color: #d5e1e8; ++ width: 100%; ++ border-width: 1px; ++ border-style: solid; ++ border-color: #84b0c7; ++ font-weight: bold; ++ -moz-border-radius: 8px 8px 8px 8px; ++} ++.paramkey { ++ text-align: right; ++} ++.paramtype { ++ white-space: nowrap; ++} ++.paramname { ++ color: #602020; ++ font-style: italic; ++} ++/* End Styling for detailed member documentation */ ++ ++/* for the tree view */ ++.ftvtree { ++ font-family: sans-serif; ++ margin:0.5em; ++} ++.directory { font-size: 9pt; font-weight: bold; } ++.directory h3 { margin: 0px; margin-top: 1em; font-size: 11pt; } ++.directory > h3 { margin-top: 0; } ++.directory p { margin: 0px; white-space: nowrap; } ++.directory div { display: none; margin: 0px; } ++.directory img { vertical-align: -30%; } ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dummy__audio_8c-source.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dummy__audio_8c-source.html 2013-07-26 19:31:20.000000000 +0000 +@@ -0,0 +1,1550 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dummy_audio.c Source File ++ ++ ++ ++ ++
++
++
++
++

dummy_audio.c

00001 /*
++00002  * zero.c -- Gadget Zero, for USB development
++00003  *
++00004  * Copyright (C) 2003-2004 David Brownell
++00005  * All rights reserved.
++00006  *
++00007  * Redistribution and use in source and binary forms, with or without
++00008  * modification, are permitted provided that the following conditions
++00009  * are met:
++00010  * 1. Redistributions of source code must retain the above copyright
++00011  *    notice, this list of conditions, and the following disclaimer,
++00012  *    without modification.
++00013  * 2. Redistributions in binary form must reproduce the above copyright
++00014  *    notice, this list of conditions and the following disclaimer in the
++00015  *    documentation and/or other materials provided with the distribution.
++00016  * 3. The names of the above-listed copyright holders may not be used
++00017  *    to endorse or promote products derived from this software without
++00018  *    specific prior written permission.
++00019  *
++00020  * ALTERNATIVELY, this software may be distributed under the terms of the
++00021  * GNU General Public License ("GPL") as published by the Free Software
++00022  * Foundation, either version 2 of that License or (at your option) any
++00023  * later version.
++00024  *
++00025  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
++00026  * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
++00027  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
++00028  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
++00029  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
++00030  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
++00031  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
++00032  * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
++00033  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
++00034  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
++00035  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++00036  */
++00037 
++00038 
++00039 /*
++00040  * Gadget Zero only needs two bulk endpoints, and is an example of how you
++00041  * can write a hardware-agnostic gadget driver running inside a USB device.
++00042  *
++00043  * Hardware details are visible (see CONFIG_USB_ZERO_* below) but don't
++00044  * affect most of the driver.
++00045  *
++00046  * Use it with the Linux host/master side "usbtest" driver to get a basic
++00047  * functional test of your device-side usb stack, or with "usb-skeleton".
++00048  *
++00049  * It supports two similar configurations.  One sinks whatever the usb host
++00050  * writes, and in return sources zeroes.  The other loops whatever the host
++00051  * writes back, so the host can read it.  Module options include:
++00052  *
++00053  *   buflen=N           default N=4096, buffer size used
++00054  *   qlen=N             default N=32, how many buffers in the loopback queue
++00055  *   loopdefault        default false, list loopback config first
++00056  *
++00057  * Many drivers will only have one configuration, letting them be much
++00058  * simpler if they also don't support high speed operation (like this
++00059  * driver does).
++00060  */
++00061 
++00062 #include <linux/config.h>
++00063 #include <linux/module.h>
++00064 #include <linux/kernel.h>
++00065 #include <linux/delay.h>
++00066 #include <linux/ioport.h>
++00067 #include <linux/sched.h>
++00068 #include <linux/slab.h>
++00069 #include <linux/smp_lock.h>
++00070 #include <linux/errno.h>
++00071 #include <linux/init.h>
++00072 #include <linux/timer.h>
++00073 #include <linux/list.h>
++00074 #include <linux/interrupt.h>
++00075 #include <linux/uts.h>
++00076 #include <linux/version.h>
++00077 #include <linux/device.h>
++00078 #include <linux/moduleparam.h>
++00079 #include <linux/proc_fs.h>
++00080 
++00081 #include <asm/byteorder.h>
++00082 #include <asm/io.h>
++00083 #include <asm/irq.h>
++00084 #include <asm/system.h>
++00085 #include <asm/unaligned.h>
++00086 
++00087 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,21)
++00088 # include <linux/usb/ch9.h>
++00089 #else
++00090 # include <linux/usb_ch9.h>
++00091 #endif
++00092 
++00093 #include <linux/usb_gadget.h>
++00094 
++00095 
++00096 /*-------------------------------------------------------------------------*/
++00097 /*-------------------------------------------------------------------------*/
++00098 
++00099 
++00100 static int utf8_to_utf16le(const char *s, u16 *cp, unsigned len)
++00101 {
++00102         int     count = 0;
++00103         u8      c;
++00104         u16     uchar;
++00105 
++00106         /* this insists on correct encodings, though not minimal ones.
++00107          * BUT it currently rejects legit 4-byte UTF-8 code points,
++00108          * which need surrogate pairs.  (Unicode 3.1 can use them.)
++00109          */
++00110         while (len != 0 && (c = (u8) *s++) != 0) {
++00111                 if (unlikely(c & 0x80)) {
++00112                         // 2-byte sequence:
++00113                         // 00000yyyyyxxxxxx = 110yyyyy 10xxxxxx
++00114                         if ((c & 0xe0) == 0xc0) {
++00115                                 uchar = (c & 0x1f) << 6;
++00116 
++00117                                 c = (u8) *s++;
++00118                                 if ((c & 0xc0) != 0xc0)
++00119                                         goto fail;
++00120                                 c &= 0x3f;
++00121                                 uchar |= c;
++00122 
++00123                         // 3-byte sequence (most CJKV characters):
++00124                         // zzzzyyyyyyxxxxxx = 1110zzzz 10yyyyyy 10xxxxxx
++00125                         } else if ((c & 0xf0) == 0xe0) {
++00126                                 uchar = (c & 0x0f) << 12;
++00127 
++00128                                 c = (u8) *s++;
++00129                                 if ((c & 0xc0) != 0xc0)
++00130                                         goto fail;
++00131                                 c &= 0x3f;
++00132                                 uchar |= c << 6;
++00133 
++00134                                 c = (u8) *s++;
++00135                                 if ((c & 0xc0) != 0xc0)
++00136                                         goto fail;
++00137                                 c &= 0x3f;
++00138                                 uchar |= c;
++00139 
++00140                                 /* no bogus surrogates */
++00141                                 if (0xd800 <= uchar && uchar <= 0xdfff)
++00142                                         goto fail;
++00143 
++00144                         // 4-byte sequence (surrogate pairs, currently rare):
++00145                         // 11101110wwwwzzzzyy + 110111yyyyxxxxxx
++00146                         //     = 11110uuu 10uuzzzz 10yyyyyy 10xxxxxx
++00147                         // (uuuuu = wwww + 1)
++00148                         // FIXME accept the surrogate code points (only)
++00149 
++00150                         } else
++00151                                 goto fail;
++00152                 } else
++00153                         uchar = c;
++00154                 put_unaligned (cpu_to_le16 (uchar), cp++);
++00155                 count++;
++00156                 len--;
++00157         }
++00158         return count;
++00159 fail:
++00160         return -1;
++00161 }
++00162 
++00163 
++00181 int
++00182 usb_gadget_get_string (struct usb_gadget_strings *table, int id, u8 *buf)
++00183 {
++00184         struct usb_string       *s;
++00185         int                     len;
++00186 
++00187         /* descriptor 0 has the language id */
++00188         if (id == 0) {
++00189                 buf [0] = 4;
++00190                 buf [1] = USB_DT_STRING;
++00191                 buf [2] = (u8) table->language;
++00192                 buf [3] = (u8) (table->language >> 8);
++00193                 return 4;
++00194         }
++00195         for (s = table->strings; s && s->s; s++)
++00196                 if (s->id == id)
++00197                         break;
++00198 
++00199         /* unrecognized: stall. */
++00200         if (!s || !s->s)
++00201                 return -EINVAL;
++00202 
++00203         /* string descriptors have length, tag, then UTF16-LE text */
++00204         len = min ((size_t) 126, strlen (s->s));
++00205         memset (buf + 2, 0, 2 * len);   /* zero all the bytes */
++00206         len = utf8_to_utf16le(s->s, (u16 *)&buf[2], len);
++00207         if (len < 0)
++00208                 return -EINVAL;
++00209         buf [0] = (len + 1) * 2;
++00210         buf [1] = USB_DT_STRING;
++00211         return buf [0];
++00212 }
++00213 
++00214 
++00215 /*-------------------------------------------------------------------------*/
++00216 /*-------------------------------------------------------------------------*/
++00217 
++00218 
++00231 int
++00232 usb_descriptor_fillbuf(void *buf, unsigned buflen,
++00233                 const struct usb_descriptor_header **src)
++00234 {
++00235         u8      *dest = buf;
++00236 
++00237         if (!src)
++00238                 return -EINVAL;
++00239 
++00240         /* fill buffer from src[] until null descriptor ptr */
++00241         for (; 0 != *src; src++) {
++00242                 unsigned                len = (*src)->bLength;
++00243 
++00244                 if (len > buflen)
++00245                         return -EINVAL;
++00246                 memcpy(dest, *src, len);
++00247                 buflen -= len;
++00248                 dest += len;
++00249         }
++00250         return dest - (u8 *)buf;
++00251 }
++00252 
++00253 
++00274 int usb_gadget_config_buf(
++00275         const struct usb_config_descriptor      *config,
++00276         void                                    *buf,
++00277         unsigned                                length,
++00278         const struct usb_descriptor_header      **desc
++00279 )
++00280 {
++00281         struct usb_config_descriptor            *cp = buf;
++00282         int                                     len;
++00283 
++00284         /* config descriptor first */
++00285         if (length < USB_DT_CONFIG_SIZE || !desc)
++00286                 return -EINVAL;
++00287         *cp = *config; 
++00288 
++00289         /* then interface/endpoint/class/vendor/... */
++00290         len = usb_descriptor_fillbuf(USB_DT_CONFIG_SIZE + (u8*)buf,
++00291                         length - USB_DT_CONFIG_SIZE, desc);
++00292         if (len < 0)
++00293                 return len;
++00294         len += USB_DT_CONFIG_SIZE;
++00295         if (len > 0xffff)
++00296                 return -EINVAL;
++00297 
++00298         /* patch up the config descriptor */
++00299         cp->bLength = USB_DT_CONFIG_SIZE;
++00300         cp->bDescriptorType = USB_DT_CONFIG;
++00301         cp->wTotalLength = cpu_to_le16(len);
++00302         cp->bmAttributes |= USB_CONFIG_ATT_ONE;
++00303         return len;
++00304 }
++00305 
++00306 /*-------------------------------------------------------------------------*/
++00307 /*-------------------------------------------------------------------------*/
++00308 
++00309 
++00310 #define RBUF_LEN (1024*1024)
++00311 static int rbuf_start;
++00312 static int rbuf_len;
++00313 static __u8 rbuf[RBUF_LEN];
++00314 
++00315 /*-------------------------------------------------------------------------*/
++00316 
++00317 #define DRIVER_VERSION          "St Patrick's Day 2004"
++00318 
++00319 static const char shortname [] = "zero";
++00320 static const char longname [] = "YAMAHA YST-MS35D USB Speaker  ";
++00321 
++00322 static const char source_sink [] = "source and sink data";
++00323 static const char loopback [] = "loop input to output";
++00324 
++00325 /*-------------------------------------------------------------------------*/
++00326 
++00327 /*
++00328  * driver assumes self-powered hardware, and
++00329  * has no way for users to trigger remote wakeup.
++00330  *
++00331  * this version autoconfigures as much as possible,
++00332  * which is reasonable for most "bulk-only" drivers.
++00333  */
++00334 static const char *EP_IN_NAME;          /* source */
++00335 static const char *EP_OUT_NAME;         /* sink */
++00336 
++00337 /*-------------------------------------------------------------------------*/
++00338 
++00339 /* big enough to hold our biggest descriptor */
++00340 #define USB_BUFSIZ      512
++00341 
++00342 struct zero_dev {
++00343         spinlock_t              lock;
++00344         struct usb_gadget       *gadget;
++00345         struct usb_request      *req;           /* for control responses */
++00346 
++00347         /* when configured, we have one of two configs:
++00348          * - source data (in to host) and sink it (out from host)
++00349          * - or loop it back (out from host back in to host)
++00350          */
++00351         u8                      config;
++00352         struct usb_ep           *in_ep, *out_ep;
++00353 
++00354         /* autoresume timer */
++00355         struct timer_list       resume;
++00356 };
++00357 
++00358 #define xprintk(d,level,fmt,args...) \
++00359         dev_printk(level , &(d)->gadget->dev , fmt , ## args)
++00360 
++00361 #ifdef DEBUG
++00362 #define DBG(dev,fmt,args...) \
++00363         xprintk(dev , KERN_DEBUG , fmt , ## args)
++00364 #else
++00365 #define DBG(dev,fmt,args...) \
++00366         do { } while (0)
++00367 #endif /* DEBUG */
++00368 
++00369 #ifdef VERBOSE
++00370 #define VDBG    DBG
++00371 #else
++00372 #define VDBG(dev,fmt,args...) \
++00373         do { } while (0)
++00374 #endif /* VERBOSE */
++00375 
++00376 #define ERROR(dev,fmt,args...) \
++00377         xprintk(dev , KERN_ERR , fmt , ## args)
++00378 #define WARN(dev,fmt,args...) \
++00379         xprintk(dev , KERN_WARNING , fmt , ## args)
++00380 #define INFO(dev,fmt,args...) \
++00381         xprintk(dev , KERN_INFO , fmt , ## args)
++00382 
++00383 /*-------------------------------------------------------------------------*/
++00384 
++00385 static unsigned buflen = 4096;
++00386 static unsigned qlen = 32;
++00387 static unsigned pattern = 0;
++00388 
++00389 module_param (buflen, uint, S_IRUGO|S_IWUSR);
++00390 module_param (qlen, uint, S_IRUGO|S_IWUSR);
++00391 module_param (pattern, uint, S_IRUGO|S_IWUSR);
++00392 
++00393 /*
++00394  * if it's nonzero, autoresume says how many seconds to wait
++00395  * before trying to wake up the host after suspend.
++00396  */
++00397 static unsigned autoresume = 0;
++00398 module_param (autoresume, uint, 0);
++00399 
++00400 /*
++00401  * Normally the "loopback" configuration is second (index 1) so
++00402  * it's not the default.  Here's where to change that order, to
++00403  * work better with hosts where config changes are problematic.
++00404  * Or controllers (like superh) that only support one config.
++00405  */
++00406 static int loopdefault = 0;
++00407 
++00408 module_param (loopdefault, bool, S_IRUGO|S_IWUSR);
++00409 
++00410 /*-------------------------------------------------------------------------*/
++00411 
++00412 /* Thanks to NetChip Technologies for donating this product ID.
++00413  *
++00414  * DO NOT REUSE THESE IDs with a protocol-incompatible driver!!  Ever!!
++00415  * Instead:  allocate your own, using normal USB-IF procedures.
++00416  */
++00417 #ifndef CONFIG_USB_ZERO_HNPTEST
++00418 #define DRIVER_VENDOR_NUM       0x0525          /* NetChip */
++00419 #define DRIVER_PRODUCT_NUM      0xa4a0          /* Linux-USB "Gadget Zero" */
++00420 #else
++00421 #define DRIVER_VENDOR_NUM       0x1a0a          /* OTG test device IDs */
++00422 #define DRIVER_PRODUCT_NUM      0xbadd
++00423 #endif
++00424 
++00425 /*-------------------------------------------------------------------------*/
++00426 
++00427 /*
++00428  * DESCRIPTORS ... most are static, but strings and (full)
++00429  * configuration descriptors are built on demand.
++00430  */
++00431 
++00432 /*
++00433 #define STRING_MANUFACTURER             25
++00434 #define STRING_PRODUCT                  42
++00435 #define STRING_SERIAL                   101
++00436 */
++00437 #define STRING_MANUFACTURER             1
++00438 #define STRING_PRODUCT                  2
++00439 #define STRING_SERIAL                   3
++00440 
++00441 #define STRING_SOURCE_SINK              250
++00442 #define STRING_LOOPBACK                 251
++00443 
++00444 /*
++00445  * This device advertises two configurations; these numbers work
++00446  * on a pxa250 as well as more flexible hardware.
++00447  */
++00448 #define CONFIG_SOURCE_SINK      3
++00449 #define CONFIG_LOOPBACK         2
++00450 
++00451 /*
++00452 static struct usb_device_descriptor
++00453 device_desc = {
++00454         .bLength =              sizeof device_desc,
++00455         .bDescriptorType =      USB_DT_DEVICE,
++00456 
++00457         .bcdUSB =               __constant_cpu_to_le16 (0x0200),
++00458         .bDeviceClass =         USB_CLASS_VENDOR_SPEC,
++00459 
++00460         .idVendor =             __constant_cpu_to_le16 (DRIVER_VENDOR_NUM),
++00461         .idProduct =            __constant_cpu_to_le16 (DRIVER_PRODUCT_NUM),
++00462         .iManufacturer =        STRING_MANUFACTURER,
++00463         .iProduct =             STRING_PRODUCT,
++00464         .iSerialNumber =        STRING_SERIAL,
++00465         .bNumConfigurations =   2,
++00466 };
++00467 */
++00468 static struct usb_device_descriptor
++00469 device_desc = {
++00470         .bLength =              sizeof device_desc,
++00471         .bDescriptorType =      USB_DT_DEVICE,
++00472         .bcdUSB =               __constant_cpu_to_le16 (0x0100),
++00473         .bDeviceClass =         USB_CLASS_PER_INTERFACE,
++00474         .bDeviceSubClass =      0,
++00475         .bDeviceProtocol =      0,
++00476         .bMaxPacketSize0 =      64,
++00477         .bcdDevice =            __constant_cpu_to_le16 (0x0100),
++00478         .idVendor =             __constant_cpu_to_le16 (0x0499),
++00479         .idProduct =            __constant_cpu_to_le16 (0x3002),
++00480         .iManufacturer =        STRING_MANUFACTURER,
++00481         .iProduct =             STRING_PRODUCT,
++00482         .iSerialNumber =        STRING_SERIAL,
++00483         .bNumConfigurations =   1,
++00484 };
++00485 
++00486 static struct usb_config_descriptor
++00487 z_config = {
++00488         .bLength =              sizeof z_config,
++00489         .bDescriptorType =      USB_DT_CONFIG,
++00490 
++00491         /* compute wTotalLength on the fly */
++00492         .bNumInterfaces =       2,
++00493         .bConfigurationValue =  1,
++00494         .iConfiguration =       0,
++00495         .bmAttributes =         0x40,
++00496         .bMaxPower =            0,      /* self-powered */
++00497 };
++00498 
++00499 
++00500 static struct usb_otg_descriptor
++00501 otg_descriptor = {
++00502         .bLength =              sizeof otg_descriptor,
++00503         .bDescriptorType =      USB_DT_OTG,
++00504 
++00505         .bmAttributes =         USB_OTG_SRP,
++00506 };
++00507 
++00508 /* one interface in each configuration */
++00509 #ifdef  CONFIG_USB_GADGET_DUALSPEED
++00510 
++00511 /*
++00512  * usb 2.0 devices need to expose both high speed and full speed
++00513  * descriptors, unless they only run at full speed.
++00514  *
++00515  * that means alternate endpoint descriptors (bigger packets)
++00516  * and a "device qualifier" ... plus more construction options
++00517  * for the config descriptor.
++00518  */
++00519 
++00520 static struct usb_qualifier_descriptor
++00521 dev_qualifier = {
++00522         .bLength =              sizeof dev_qualifier,
++00523         .bDescriptorType =      USB_DT_DEVICE_QUALIFIER,
++00524 
++00525         .bcdUSB =               __constant_cpu_to_le16 (0x0200),
++00526         .bDeviceClass =         USB_CLASS_VENDOR_SPEC,
++00527 
++00528         .bNumConfigurations =   2,
++00529 };
++00530 
++00531 
++00532 struct usb_cs_as_general_descriptor {
++00533         __u8  bLength;
++00534         __u8  bDescriptorType;
++00535 
++00536         __u8  bDescriptorSubType;
++00537         __u8  bTerminalLink;
++00538         __u8  bDelay;
++00539         __u16  wFormatTag;
++00540 } __attribute__ ((packed));
++00541 
++00542 struct usb_cs_as_format_descriptor {
++00543         __u8  bLength;
++00544         __u8  bDescriptorType;
++00545 
++00546         __u8  bDescriptorSubType;
++00547         __u8  bFormatType;
++00548         __u8  bNrChannels;
++00549         __u8  bSubframeSize;
++00550         __u8  bBitResolution;
++00551         __u8  bSamfreqType;
++00552         __u8  tLowerSamFreq[3];
++00553         __u8  tUpperSamFreq[3];
++00554 } __attribute__ ((packed));
++00555 
++00556 static const struct usb_interface_descriptor
++00557 z_audio_control_if_desc = {
++00558         .bLength =              sizeof z_audio_control_if_desc,
++00559         .bDescriptorType =      USB_DT_INTERFACE,
++00560         .bInterfaceNumber = 0,
++00561         .bAlternateSetting = 0,
++00562         .bNumEndpoints = 0,
++00563         .bInterfaceClass = USB_CLASS_AUDIO,
++00564         .bInterfaceSubClass = 0x1,
++00565         .bInterfaceProtocol = 0,
++00566         .iInterface = 0,
++00567 };
++00568 
++00569 static const struct usb_interface_descriptor
++00570 z_audio_if_desc = {
++00571         .bLength =              sizeof z_audio_if_desc,
++00572         .bDescriptorType =      USB_DT_INTERFACE,
++00573         .bInterfaceNumber = 1,
++00574         .bAlternateSetting = 0,
++00575         .bNumEndpoints = 0,
++00576         .bInterfaceClass = USB_CLASS_AUDIO,
++00577         .bInterfaceSubClass = 0x2,
++00578         .bInterfaceProtocol = 0,
++00579         .iInterface = 0,
++00580 };
++00581 
++00582 static const struct usb_interface_descriptor
++00583 z_audio_if_desc2 = {
++00584         .bLength =              sizeof z_audio_if_desc,
++00585         .bDescriptorType =      USB_DT_INTERFACE,
++00586         .bInterfaceNumber = 1,
++00587         .bAlternateSetting = 1,
++00588         .bNumEndpoints = 1,
++00589         .bInterfaceClass = USB_CLASS_AUDIO,
++00590         .bInterfaceSubClass = 0x2,
++00591         .bInterfaceProtocol = 0,
++00592         .iInterface = 0,
++00593 };
++00594 
++00595 static const struct usb_cs_as_general_descriptor
++00596 z_audio_cs_as_if_desc = {
++00597         .bLength = 7,
++00598         .bDescriptorType = 0x24,
++00599         
++00600         .bDescriptorSubType = 0x01,
++00601         .bTerminalLink = 0x01,
++00602         .bDelay = 0x0,
++00603         .wFormatTag = __constant_cpu_to_le16 (0x0001)
++00604 };
++00605 
++00606 
++00607 static const struct usb_cs_as_format_descriptor 
++00608 z_audio_cs_as_format_desc = {
++00609         .bLength = 0xe,
++00610         .bDescriptorType = 0x24,
++00611         
++00612         .bDescriptorSubType = 2,
++00613         .bFormatType = 1,
++00614         .bNrChannels = 1,
++00615         .bSubframeSize = 1,
++00616         .bBitResolution = 8,
++00617         .bSamfreqType = 0,
++00618         .tLowerSamFreq = {0x7e, 0x13, 0x00},
++00619         .tUpperSamFreq = {0xe2, 0xd6, 0x00},
++00620 };
++00621 
++00622 static const struct usb_endpoint_descriptor 
++00623 z_iso_ep = {
++00624         .bLength = 0x09,
++00625         .bDescriptorType = 0x05,
++00626         .bEndpointAddress = 0x04,
++00627         .bmAttributes = 0x09,
++00628         .wMaxPacketSize = 0x0038,
++00629         .bInterval = 0x01,
++00630         .bRefresh = 0x00,
++00631         .bSynchAddress = 0x00,  
++00632 };
++00633 
++00634 static char z_iso_ep2[] = {0x07, 0x25, 0x01, 0x00, 0x02, 0x00, 0x02};
++00635 
++00636 // 9 bytes
++00637 static char z_ac_interface_header_desc[] = 
++00638 { 0x09, 0x24, 0x01, 0x00, 0x01, 0x2b, 0x00, 0x01, 0x01 };
++00639 
++00640 // 12 bytes
++00641 static char z_0[] = {0x0c, 0x24, 0x02, 0x01, 0x01, 0x01, 0x00, 0x02, 
++00642                      0x03, 0x00, 0x00, 0x00};
++00643 // 13 bytes
++00644 static char z_1[] = {0x0d, 0x24, 0x06, 0x02, 0x01, 0x02, 0x15, 0x00, 
++00645                      0x02, 0x00, 0x02, 0x00, 0x00};
++00646 // 9 bytes
++00647 static char z_2[] = {0x09, 0x24, 0x03, 0x03, 0x01, 0x03, 0x00, 0x02, 
++00648                      0x00};
++00649 
++00650 static char za_0[] = {0x09, 0x04, 0x01, 0x02, 0x01, 0x01, 0x02, 0x00, 
++00651                       0x00};
++00652 
++00653 static char za_1[] = {0x07, 0x24, 0x01, 0x01, 0x00, 0x01, 0x00};
++00654 
++00655 static char za_2[] = {0x0e, 0x24, 0x02, 0x01, 0x02, 0x01, 0x08, 0x00, 
++00656                       0x7e, 0x13, 0x00, 0xe2, 0xd6, 0x00};
++00657 
++00658 static char za_3[] = {0x09, 0x05, 0x04, 0x09, 0x70, 0x00, 0x01, 0x00,
++00659                       0x00};
++00660 
++00661 static char za_4[] = {0x07, 0x25, 0x01, 0x00, 0x02, 0x00, 0x02};
++00662 
++00663 static char za_5[] = {0x09, 0x04, 0x01, 0x03, 0x01, 0x01, 0x02, 0x00,
++00664                       0x00};
++00665 
++00666 static char za_6[] = {0x07, 0x24, 0x01, 0x01, 0x00, 0x01, 0x00};
++00667 
++00668 static char za_7[] = {0x0e, 0x24, 0x02, 0x01, 0x01, 0x02, 0x10, 0x00,
++00669                       0x7e, 0x13, 0x00, 0xe2, 0xd6, 0x00};
++00670 
++00671 static char za_8[] = {0x09, 0x05, 0x04, 0x09, 0x70, 0x00, 0x01, 0x00,
++00672                       0x00};
++00673 
++00674 static char za_9[] = {0x07, 0x25, 0x01, 0x00, 0x02, 0x00, 0x02};
++00675 
++00676 static char za_10[] = {0x09, 0x04, 0x01, 0x04, 0x01, 0x01, 0x02, 0x00,
++00677                        0x00};
++00678 
++00679 static char za_11[] = {0x07, 0x24, 0x01, 0x01, 0x00, 0x01, 0x00};
++00680 
++00681 static char za_12[] = {0x0e, 0x24, 0x02, 0x01, 0x02, 0x02, 0x10, 0x00,
++00682                        0x73, 0x13, 0x00, 0xe2, 0xd6, 0x00};
++00683 
++00684 static char za_13[] = {0x09, 0x05, 0x04, 0x09, 0xe0, 0x00, 0x01, 0x00,
++00685                        0x00};
++00686 
++00687 static char za_14[] = {0x07, 0x25, 0x01, 0x00, 0x02, 0x00, 0x02};
++00688 
++00689 static char za_15[] = {0x09, 0x04, 0x01, 0x05, 0x01, 0x01, 0x02, 0x00, 
++00690                        0x00};
++00691 
++00692 static char za_16[] = {0x07, 0x24, 0x01, 0x01, 0x00, 0x01, 0x00};
++00693 
++00694 static char za_17[] = {0x0e, 0x24, 0x02, 0x01, 0x01, 0x03, 0x14, 0x00, 
++00695                        0x7e, 0x13, 0x00, 0xe2, 0xd6, 0x00};
++00696 
++00697 static char za_18[] = {0x09, 0x05, 0x04, 0x09, 0xa8, 0x00, 0x01, 0x00,
++00698                        0x00};
++00699 
++00700 static char za_19[] = {0x07, 0x25, 0x01, 0x00, 0x02, 0x00, 0x02};
++00701 
++00702 static char za_20[] = {0x09, 0x04, 0x01, 0x06, 0x01, 0x01, 0x02, 0x00,
++00703                        0x00};
++00704 
++00705 static char za_21[] = {0x07, 0x24, 0x01, 0x01, 0x00, 0x01, 0x00};
++00706 
++00707 static char za_22[] = {0x0e, 0x24, 0x02, 0x01, 0x02, 0x03, 0x14, 0x00, 
++00708                        0x7e, 0x13, 0x00, 0xe2, 0xd6, 0x00};
++00709 
++00710 static char za_23[] = {0x09, 0x05, 0x04, 0x09, 0x50, 0x01, 0x01, 0x00,
++00711                        0x00};
++00712 
++00713 static char za_24[] = {0x07, 0x25, 0x01, 0x00, 0x02, 0x00, 0x02};
++00714 
++00715 
++00716 
++00717 static const struct usb_descriptor_header *z_function [] = {
++00718         (struct usb_descriptor_header *) &z_audio_control_if_desc,
++00719         (struct usb_descriptor_header *) &z_ac_interface_header_desc,
++00720         (struct usb_descriptor_header *) &z_0,
++00721         (struct usb_descriptor_header *) &z_1,
++00722         (struct usb_descriptor_header *) &z_2,
++00723         (struct usb_descriptor_header *) &z_audio_if_desc,
++00724         (struct usb_descriptor_header *) &z_audio_if_desc2,
++00725         (struct usb_descriptor_header *) &z_audio_cs_as_if_desc,
++00726         (struct usb_descriptor_header *) &z_audio_cs_as_format_desc,
++00727         (struct usb_descriptor_header *) &z_iso_ep,
++00728         (struct usb_descriptor_header *) &z_iso_ep2,
++00729         (struct usb_descriptor_header *) &za_0,
++00730         (struct usb_descriptor_header *) &za_1,
++00731         (struct usb_descriptor_header *) &za_2,
++00732         (struct usb_descriptor_header *) &za_3,
++00733         (struct usb_descriptor_header *) &za_4,
++00734         (struct usb_descriptor_header *) &za_5,
++00735         (struct usb_descriptor_header *) &za_6,
++00736         (struct usb_descriptor_header *) &za_7,
++00737         (struct usb_descriptor_header *) &za_8,
++00738         (struct usb_descriptor_header *) &za_9,
++00739         (struct usb_descriptor_header *) &za_10,
++00740         (struct usb_descriptor_header *) &za_11,
++00741         (struct usb_descriptor_header *) &za_12,
++00742         (struct usb_descriptor_header *) &za_13,
++00743         (struct usb_descriptor_header *) &za_14,
++00744         (struct usb_descriptor_header *) &za_15,
++00745         (struct usb_descriptor_header *) &za_16,
++00746         (struct usb_descriptor_header *) &za_17,
++00747         (struct usb_descriptor_header *) &za_18,
++00748         (struct usb_descriptor_header *) &za_19,
++00749         (struct usb_descriptor_header *) &za_20,
++00750         (struct usb_descriptor_header *) &za_21,
++00751         (struct usb_descriptor_header *) &za_22,
++00752         (struct usb_descriptor_header *) &za_23,
++00753         (struct usb_descriptor_header *) &za_24,
++00754         NULL,
++00755 };
++00756 
++00757 /* maxpacket and other transfer characteristics vary by speed. */
++00758 #define ep_desc(g,hs,fs) (((g)->speed==USB_SPEED_HIGH)?(hs):(fs))
++00759 
++00760 #else
++00761 
++00762 /* if there's no high speed support, maxpacket doesn't change. */
++00763 #define ep_desc(g,hs,fs) fs
++00764 
++00765 #endif  /* !CONFIG_USB_GADGET_DUALSPEED */
++00766 
++00767 static char                             manufacturer [40];
++00768 //static char                           serial [40];
++00769 static char                             serial [] = "Ser 00 em";
++00770 
++00771 /* static strings, in UTF-8 */
++00772 static struct usb_string                strings [] = {
++00773         { STRING_MANUFACTURER, manufacturer, },
++00774         { STRING_PRODUCT, longname, },
++00775         { STRING_SERIAL, serial, },
++00776         { STRING_LOOPBACK, loopback, },
++00777         { STRING_SOURCE_SINK, source_sink, },
++00778         {  }                    /* end of list */
++00779 };
++00780 
++00781 static struct usb_gadget_strings        stringtab = {
++00782         .language       = 0x0409,       /* en-us */
++00783         .strings        = strings,
++00784 };
++00785 
++00786 /*
++00787  * config descriptors are also handcrafted.  these must agree with code
++00788  * that sets configurations, and with code managing interfaces and their
++00789  * altsettings.  other complexity may come from:
++00790  *
++00791  *  - high speed support, including "other speed config" rules
++00792  *  - multiple configurations
++00793  *  - interfaces with alternate settings
++00794  *  - embedded class or vendor-specific descriptors
++00795  *
++00796  * this handles high speed, and has a second config that could as easily
++00797  * have been an alternate interface setting (on most hardware).
++00798  *
++00799  * NOTE:  to demonstrate (and test) more USB capabilities, this driver
++00800  * should include an altsetting to test interrupt transfers, including
++00801  * high bandwidth modes at high speed.  (Maybe work like Intel's test
++00802  * device?)
++00803  */
++00804 static int
++00805 config_buf (struct usb_gadget *gadget, u8 *buf, u8 type, unsigned index)
++00806 {
++00807         int len;
++00808         const struct usb_descriptor_header **function;
++00809         
++00810         function = z_function;
++00811         len = usb_gadget_config_buf (&z_config, buf, USB_BUFSIZ, function);
++00812         if (len < 0)
++00813                 return len;
++00814         ((struct usb_config_descriptor *) buf)->bDescriptorType = type;
++00815         return len;
++00816 }
++00817 
++00818 /*-------------------------------------------------------------------------*/
++00819 
++00820 static struct usb_request *
++00821 alloc_ep_req (struct usb_ep *ep, unsigned length)
++00822 {
++00823         struct usb_request      *req;
++00824 
++00825         req = usb_ep_alloc_request (ep, GFP_ATOMIC);
++00826         if (req) {
++00827                 req->length = length;
++00828                 req->buf = usb_ep_alloc_buffer (ep, length,
++00829                                 &req->dma, GFP_ATOMIC);
++00830                 if (!req->buf) {
++00831                         usb_ep_free_request (ep, req);
++00832                         req = NULL;
++00833                 }
++00834         }
++00835         return req;
++00836 }
++00837 
++00838 static void free_ep_req (struct usb_ep *ep, struct usb_request *req)
++00839 {
++00840         if (req->buf)
++00841                 usb_ep_free_buffer (ep, req->buf, req->dma, req->length);
++00842         usb_ep_free_request (ep, req);
++00843 }
++00844 
++00845 /*-------------------------------------------------------------------------*/
++00846 
++00847 /* optionally require specific source/sink data patterns  */
++00848 
++00849 static int
++00850 check_read_data (
++00851         struct zero_dev         *dev,
++00852         struct usb_ep           *ep,
++00853         struct usb_request      *req
++00854 )
++00855 {
++00856         unsigned        i;
++00857         u8              *buf = req->buf;
++00858 
++00859         for (i = 0; i < req->actual; i++, buf++) {
++00860                 switch (pattern) {
++00861                 /* all-zeroes has no synchronization issues */
++00862                 case 0:
++00863                         if (*buf == 0)
++00864                                 continue;
++00865                         break;
++00866                 /* mod63 stays in sync with short-terminated transfers,
++00867                  * or otherwise when host and gadget agree on how large
++00868                  * each usb transfer request should be.  resync is done
++00869                  * with set_interface or set_config.
++00870                  */
++00871                 case 1:
++00872                         if (*buf == (u8)(i % 63))
++00873                                 continue;
++00874                         break;
++00875                 }
++00876                 ERROR (dev, "bad OUT byte, buf [%d] = %d\n", i, *buf);
++00877                 usb_ep_set_halt (ep);
++00878                 return -EINVAL;
++00879         }
++00880         return 0;
++00881 }
++00882 
++00883 /*-------------------------------------------------------------------------*/
++00884 
++00885 static void zero_reset_config (struct zero_dev *dev)
++00886 {
++00887         if (dev->config == 0)
++00888                 return;
++00889 
++00890         DBG (dev, "reset config\n");
++00891 
++00892         /* just disable endpoints, forcing completion of pending i/o.
++00893          * all our completion handlers free their requests in this case.
++00894          */
++00895         if (dev->in_ep) {
++00896                 usb_ep_disable (dev->in_ep);
++00897                 dev->in_ep = NULL;
++00898         }
++00899         if (dev->out_ep) {
++00900                 usb_ep_disable (dev->out_ep);
++00901                 dev->out_ep = NULL;
++00902         }
++00903         dev->config = 0;
++00904         del_timer (&dev->resume);
++00905 }
++00906 
++00907 #define _write(f, buf, sz) (f->f_op->write(f, buf, sz, &f->f_pos))
++00908 
++00909 static void 
++00910 zero_isoc_complete (struct usb_ep *ep, struct usb_request *req)
++00911 {
++00912         struct zero_dev *dev = ep->driver_data;
++00913         int             status = req->status;
++00914         int i, j;
++00915 
++00916         switch (status) {
++00917 
++00918         case 0:                         /* normal completion? */
++00919                 //printk ("\nzero ---------------> isoc normal completion %d bytes\n", req->actual);
++00920                 for (i=0, j=rbuf_start; i<req->actual; i++) {
++00921                         //printk ("%02x ", ((__u8*)req->buf)[i]);
++00922                         rbuf[j] = ((__u8*)req->buf)[i];
++00923                         j++;
++00924                         if (j >= RBUF_LEN) j=0;
++00925                 }
++00926                 rbuf_start = j;
++00927                 //printk ("\n\n");
++00928 
++00929                 if (rbuf_len < RBUF_LEN) {
++00930                         rbuf_len += req->actual;
++00931                         if (rbuf_len > RBUF_LEN) {
++00932                                 rbuf_len = RBUF_LEN;
++00933                         }
++00934                 }
++00935 
++00936                 break;
++00937 
++00938         /* this endpoint is normally active while we're configured */
++00939         case -ECONNABORTED:             /* hardware forced ep reset */
++00940         case -ECONNRESET:               /* request dequeued */
++00941         case -ESHUTDOWN:                /* disconnect from host */
++00942                 VDBG (dev, "%s gone (%d), %d/%d\n", ep->name, status,
++00943                                 req->actual, req->length);
++00944                 if (ep == dev->out_ep)
++00945                         check_read_data (dev, ep, req);
++00946                 free_ep_req (ep, req);
++00947                 return;
++00948 
++00949         case -EOVERFLOW:                /* buffer overrun on read means that
++00950                                          * we didn't provide a big enough
++00951                                          * buffer.
++00952                                          */
++00953         default:
++00954 #if 1
++00955                 DBG (dev, "%s complete --> %d, %d/%d\n", ep->name,
++00956                                 status, req->actual, req->length);
++00957 #endif
++00958         case -EREMOTEIO:                /* short read */
++00959                 break;
++00960         }
++00961 
++00962         status = usb_ep_queue (ep, req, GFP_ATOMIC);
++00963         if (status) {
++00964                 ERROR (dev, "kill %s:  resubmit %d bytes --> %d\n",
++00965                                 ep->name, req->length, status);
++00966                 usb_ep_set_halt (ep);
++00967                 /* FIXME recover later ... somehow */
++00968         }
++00969 }
++00970 
++00971 static struct usb_request *
++00972 zero_start_isoc_ep (struct usb_ep *ep, int gfp_flags)
++00973 {
++00974         struct usb_request      *req;
++00975         int                     status;
++00976 
++00977         req = alloc_ep_req (ep, 512);
++00978         if (!req)
++00979                 return NULL;
++00980 
++00981         req->complete = zero_isoc_complete;
++00982 
++00983         status = usb_ep_queue (ep, req, gfp_flags);
++00984         if (status) {
++00985                 struct zero_dev *dev = ep->driver_data;
++00986 
++00987                 ERROR (dev, "start %s --> %d\n", ep->name, status);
++00988                 free_ep_req (ep, req);
++00989                 req = NULL;
++00990         }
++00991 
++00992         return req;
++00993 }
++00994 
++00995 /* change our operational config.  this code must agree with the code
++00996  * that returns config descriptors, and altsetting code.
++00997  *
++00998  * it's also responsible for power management interactions. some
++00999  * configurations might not work with our current power sources.
++01000  *
++01001  * note that some device controller hardware will constrain what this
++01002  * code can do, perhaps by disallowing more than one configuration or
++01003  * by limiting configuration choices (like the pxa2xx).
++01004  */
++01005 static int
++01006 zero_set_config (struct zero_dev *dev, unsigned number, int gfp_flags)
++01007 {
++01008         int                     result = 0;
++01009         struct usb_gadget       *gadget = dev->gadget;
++01010         const struct usb_endpoint_descriptor    *d;
++01011         struct usb_ep           *ep;
++01012 
++01013         if (number == dev->config)
++01014                 return 0;
++01015 
++01016         zero_reset_config (dev);
++01017 
++01018         gadget_for_each_ep (ep, gadget) {
++01019 
++01020                 if (strcmp (ep->name, "ep4") == 0) {
++01021 
++01022                         d = (struct usb_endpoint_descripter *)&za_23; // isoc ep desc for audio i/f alt setting 6
++01023                         result = usb_ep_enable (ep, d);
++01024 
++01025                         if (result == 0) {
++01026                                 ep->driver_data = dev;
++01027                                 dev->in_ep = ep;
++01028 
++01029                                 if (zero_start_isoc_ep (ep, gfp_flags) != 0) {
++01030 
++01031                                         dev->in_ep = ep;
++01032                                         continue;
++01033                                 }
++01034 
++01035                                 usb_ep_disable (ep);
++01036                                 result = -EIO;
++01037                         }
++01038                 }
++01039 
++01040         }
++01041 
++01042         dev->config = number;
++01043         return result;
++01044 }
++01045 
++01046 /*-------------------------------------------------------------------------*/
++01047 
++01048 static void zero_setup_complete (struct usb_ep *ep, struct usb_request *req)
++01049 {
++01050         if (req->status || req->actual != req->length)
++01051                 DBG ((struct zero_dev *) ep->driver_data,
++01052                                 "setup complete --> %d, %d/%d\n",
++01053                                 req->status, req->actual, req->length);
++01054 }
++01055 
++01056 /*
++01057  * The setup() callback implements all the ep0 functionality that's
++01058  * not handled lower down, in hardware or the hardware driver (like
++01059  * device and endpoint feature flags, and their status).  It's all
++01060  * housekeeping for the gadget function we're implementing.  Most of
++01061  * the work is in config-specific setup.
++01062  */
++01063 static int
++01064 zero_setup (struct usb_gadget *gadget, const struct usb_ctrlrequest *ctrl)
++01065 {
++01066         struct zero_dev         *dev = get_gadget_data (gadget);
++01067         struct usb_request      *req = dev->req;
++01068         int                     value = -EOPNOTSUPP;
++01069 
++01070         /* usually this stores reply data in the pre-allocated ep0 buffer,
++01071          * but config change events will reconfigure hardware.
++01072          */
++01073         req->zero = 0;
++01074         switch (ctrl->bRequest) {
++01075 
++01076         case USB_REQ_GET_DESCRIPTOR:
++01077 
++01078                 switch (ctrl->wValue >> 8) {
++01079 
++01080                 case USB_DT_DEVICE:
++01081                         value = min (ctrl->wLength, (u16) sizeof device_desc);
++01082                         memcpy (req->buf, &device_desc, value);
++01083                         break;
++01084 #ifdef CONFIG_USB_GADGET_DUALSPEED
++01085                 case USB_DT_DEVICE_QUALIFIER:
++01086                         if (!gadget->is_dualspeed)
++01087                                 break;
++01088                         value = min (ctrl->wLength, (u16) sizeof dev_qualifier);
++01089                         memcpy (req->buf, &dev_qualifier, value);
++01090                         break;
++01091 
++01092                 case USB_DT_OTHER_SPEED_CONFIG:
++01093                         if (!gadget->is_dualspeed)
++01094                                 break;
++01095                         // FALLTHROUGH
++01096 #endif /* CONFIG_USB_GADGET_DUALSPEED */
++01097                 case USB_DT_CONFIG:
++01098                         value = config_buf (gadget, req->buf,
++01099                                         ctrl->wValue >> 8,
++01100                                         ctrl->wValue & 0xff);
++01101                         if (value >= 0)
++01102                                 value = min (ctrl->wLength, (u16) value);
++01103                         break;
++01104 
++01105                 case USB_DT_STRING:
++01106                         /* wIndex == language code.
++01107                          * this driver only handles one language, you can
++01108                          * add string tables for other languages, using
++01109                          * any UTF-8 characters
++01110                          */
++01111                         value = usb_gadget_get_string (&stringtab,
++01112                                         ctrl->wValue & 0xff, req->buf);
++01113                         if (value >= 0) {
++01114                                 value = min (ctrl->wLength, (u16) value);
++01115                         }
++01116                         break;
++01117                 }
++01118                 break;
++01119 
++01120         /* currently two configs, two speeds */
++01121         case USB_REQ_SET_CONFIGURATION:
++01122                 if (ctrl->bRequestType != 0)
++01123                         goto unknown;
++01124 
++01125                 spin_lock (&dev->lock);
++01126                 value = zero_set_config (dev, ctrl->wValue, GFP_ATOMIC);
++01127                 spin_unlock (&dev->lock);
++01128                 break;
++01129         case USB_REQ_GET_CONFIGURATION:
++01130                 if (ctrl->bRequestType != USB_DIR_IN)
++01131                         goto unknown;
++01132                 *(u8 *)req->buf = dev->config;
++01133                 value = min (ctrl->wLength, (u16) 1);
++01134                 break;
++01135 
++01136         /* until we add altsetting support, or other interfaces,
++01137          * only 0/0 are possible.  pxa2xx only supports 0/0 (poorly)
++01138          * and already killed pending endpoint I/O.
++01139          */
++01140         case USB_REQ_SET_INTERFACE:
++01141 
++01142                 if (ctrl->bRequestType != USB_RECIP_INTERFACE)
++01143                         goto unknown;
++01144                 spin_lock (&dev->lock);
++01145                 if (dev->config) {
++01146                         u8              config = dev->config;
++01147 
++01148                         /* resets interface configuration, forgets about
++01149                          * previous transaction state (queued bufs, etc)
++01150                          * and re-inits endpoint state (toggle etc)
++01151                          * no response queued, just zero status == success.
++01152                          * if we had more than one interface we couldn't
++01153                          * use this "reset the config" shortcut.
++01154                          */
++01155                         zero_reset_config (dev);
++01156                         zero_set_config (dev, config, GFP_ATOMIC);
++01157                         value = 0;
++01158                 }
++01159                 spin_unlock (&dev->lock);
++01160                 break;
++01161         case USB_REQ_GET_INTERFACE:
++01162                 if ((ctrl->bRequestType == 0x21) && (ctrl->wIndex == 0x02)) {
++01163                         value = ctrl->wLength;
++01164                         break;
++01165                 }
++01166                 else {
++01167                         if (ctrl->bRequestType != (USB_DIR_IN|USB_RECIP_INTERFACE))
++01168                                 goto unknown;
++01169                         if (!dev->config)
++01170                                 break;
++01171                         if (ctrl->wIndex != 0) {
++01172                                 value = -EDOM;
++01173                                 break;
++01174                         }
++01175                         *(u8 *)req->buf = 0;
++01176                         value = min (ctrl->wLength, (u16) 1);
++01177                 }
++01178                 break;
++01179 
++01180         /*
++01181          * These are the same vendor-specific requests supported by
++01182          * Intel's USB 2.0 compliance test devices.  We exceed that
++01183          * device spec by allowing multiple-packet requests.
++01184          */
++01185         case 0x5b:      /* control WRITE test -- fill the buffer */
++01186                 if (ctrl->bRequestType != (USB_DIR_OUT|USB_TYPE_VENDOR))
++01187                         goto unknown;
++01188                 if (ctrl->wValue || ctrl->wIndex)
++01189                         break;
++01190                 /* just read that many bytes into the buffer */
++01191                 if (ctrl->wLength > USB_BUFSIZ)
++01192                         break;
++01193                 value = ctrl->wLength;
++01194                 break;
++01195         case 0x5c:      /* control READ test -- return the buffer */
++01196                 if (ctrl->bRequestType != (USB_DIR_IN|USB_TYPE_VENDOR))
++01197                         goto unknown;
++01198                 if (ctrl->wValue || ctrl->wIndex)
++01199                         break;
++01200                 /* expect those bytes are still in the buffer; send back */
++01201                 if (ctrl->wLength > USB_BUFSIZ
++01202                                 || ctrl->wLength != req->length)
++01203                         break;
++01204                 value = ctrl->wLength;
++01205                 break;
++01206 
++01207         case 0x01: // SET_CUR
++01208         case 0x02:
++01209         case 0x03:
++01210         case 0x04:
++01211         case 0x05:
++01212                 value = ctrl->wLength;
++01213                 break;
++01214         case 0x81:
++01215                 switch (ctrl->wValue) {
++01216                 case 0x0201:
++01217                 case 0x0202:
++01218                         ((u8*)req->buf)[0] = 0x00;
++01219                         ((u8*)req->buf)[1] = 0xe3;
++01220                         break;
++01221                 case 0x0300:
++01222                 case 0x0500:
++01223                         ((u8*)req->buf)[0] = 0x00;
++01224                         break;
++01225                 }
++01226                 //((u8*)req->buf)[0] = 0x81;
++01227                 //((u8*)req->buf)[1] = 0x81;
++01228                 value = ctrl->wLength;
++01229                 break;
++01230         case 0x82:
++01231                 switch (ctrl->wValue) {
++01232                 case 0x0201:
++01233                 case 0x0202:
++01234                         ((u8*)req->buf)[0] = 0x00;
++01235                         ((u8*)req->buf)[1] = 0xc3;
++01236                         break;
++01237                 case 0x0300:
++01238                 case 0x0500:
++01239                         ((u8*)req->buf)[0] = 0x00;
++01240                         break;
++01241                 }
++01242                 //((u8*)req->buf)[0] = 0x82;
++01243                 //((u8*)req->buf)[1] = 0x82;
++01244                 value = ctrl->wLength;
++01245                 break;
++01246         case 0x83:
++01247                 switch (ctrl->wValue) {
++01248                 case 0x0201:
++01249                 case 0x0202:
++01250                         ((u8*)req->buf)[0] = 0x00;
++01251                         ((u8*)req->buf)[1] = 0x00;
++01252                         break;
++01253                 case 0x0300:
++01254                         ((u8*)req->buf)[0] = 0x60;
++01255                         break;
++01256                 case 0x0500:    
++01257                         ((u8*)req->buf)[0] = 0x18;
++01258                         break;
++01259                 }
++01260                 //((u8*)req->buf)[0] = 0x83;
++01261                 //((u8*)req->buf)[1] = 0x83;
++01262                 value = ctrl->wLength;
++01263                 break;
++01264         case 0x84:
++01265                 switch (ctrl->wValue) {
++01266                 case 0x0201:
++01267                 case 0x0202:
++01268                         ((u8*)req->buf)[0] = 0x00;
++01269                         ((u8*)req->buf)[1] = 0x01;
++01270                         break;
++01271                 case 0x0300:
++01272                 case 0x0500:
++01273                         ((u8*)req->buf)[0] = 0x08;
++01274                         break;
++01275                 }
++01276                 //((u8*)req->buf)[0] = 0x84;
++01277                 //((u8*)req->buf)[1] = 0x84;
++01278                 value = ctrl->wLength;
++01279                 break;
++01280         case 0x85:
++01281                 ((u8*)req->buf)[0] = 0x85;
++01282                 ((u8*)req->buf)[1] = 0x85;
++01283                 value = ctrl->wLength;
++01284                 break;
++01285 
++01286         
++01287         default:
++01288 unknown:
++01289                 printk("unknown control req%02x.%02x v%04x i%04x l%d\n",
++01290                         ctrl->bRequestType, ctrl->bRequest,
++01291                         ctrl->wValue, ctrl->wIndex, ctrl->wLength);
++01292         }
++01293 
++01294         /* respond with data transfer before status phase? */
++01295         if (value >= 0) {
++01296                 req->length = value;
++01297                 req->zero = value < ctrl->wLength
++01298                                 && (value % gadget->ep0->maxpacket) == 0;
++01299                 value = usb_ep_queue (gadget->ep0, req, GFP_ATOMIC);
++01300                 if (value < 0) {
++01301                         DBG (dev, "ep_queue < 0 --> %d\n", value);
++01302                         req->status = 0;
++01303                         zero_setup_complete (gadget->ep0, req);
++01304                 }
++01305         }
++01306 
++01307         /* device either stalls (value < 0) or reports success */
++01308         return value;
++01309 }
++01310 
++01311 static void
++01312 zero_disconnect (struct usb_gadget *gadget)
++01313 {
++01314         struct zero_dev         *dev = get_gadget_data (gadget);
++01315         unsigned long           flags;
++01316 
++01317         spin_lock_irqsave (&dev->lock, flags);
++01318         zero_reset_config (dev);
++01319 
++01320         /* a more significant application might have some non-usb
++01321          * activities to quiesce here, saving resources like power
++01322          * or pushing the notification up a network stack.
++01323          */
++01324         spin_unlock_irqrestore (&dev->lock, flags);
++01325 
++01326         /* next we may get setup() calls to enumerate new connections;
++01327          * or an unbind() during shutdown (including removing module).
++01328          */
++01329 }
++01330 
++01331 static void
++01332 zero_autoresume (unsigned long _dev)
++01333 {
++01334         struct zero_dev *dev = (struct zero_dev *) _dev;
++01335         int             status;
++01336 
++01337         /* normally the host would be woken up for something
++01338          * more significant than just a timer firing...
++01339          */
++01340         if (dev->gadget->speed != USB_SPEED_UNKNOWN) {
++01341                 status = usb_gadget_wakeup (dev->gadget);
++01342                 DBG (dev, "wakeup --> %d\n", status);
++01343         }
++01344 }
++01345 
++01346 /*-------------------------------------------------------------------------*/
++01347 
++01348 static void
++01349 zero_unbind (struct usb_gadget *gadget)
++01350 {
++01351         struct zero_dev         *dev = get_gadget_data (gadget);
++01352 
++01353         DBG (dev, "unbind\n");
++01354 
++01355         /* we've already been disconnected ... no i/o is active */
++01356         if (dev->req)
++01357                 free_ep_req (gadget->ep0, dev->req);
++01358         del_timer_sync (&dev->resume);
++01359         kfree (dev);
++01360         set_gadget_data (gadget, NULL);
++01361 }
++01362 
++01363 static int
++01364 zero_bind (struct usb_gadget *gadget)
++01365 {
++01366         struct zero_dev         *dev;
++01367         //struct usb_ep         *ep;
++01368 
++01369         printk("binding\n");
++01370         /*
++01371          * DRIVER POLICY CHOICE:  you may want to do this differently.
++01372          * One thing to avoid is reusing a bcdDevice revision code
++01373          * with different host-visible configurations or behavior
++01374          * restrictions -- using ep1in/ep2out vs ep1out/ep3in, etc
++01375          */
++01376         //device_desc.bcdDevice = __constant_cpu_to_le16 (0x0201);
++01377 
++01378 
++01379         /* ok, we made sense of the hardware ... */
++01380         dev = kmalloc (sizeof *dev, SLAB_KERNEL);
++01381         if (!dev)
++01382                 return -ENOMEM;
++01383         memset (dev, 0, sizeof *dev);
++01384         spin_lock_init (&dev->lock);
++01385         dev->gadget = gadget;
++01386         set_gadget_data (gadget, dev);
++01387 
++01388         /* preallocate control response and buffer */
++01389         dev->req = usb_ep_alloc_request (gadget->ep0, GFP_KERNEL);
++01390         if (!dev->req)
++01391                 goto enomem;
++01392         dev->req->buf = usb_ep_alloc_buffer (gadget->ep0, USB_BUFSIZ,
++01393                                 &dev->req->dma, GFP_KERNEL);
++01394         if (!dev->req->buf)
++01395                 goto enomem;
++01396 
++01397         dev->req->complete = zero_setup_complete;
++01398 
++01399         device_desc.bMaxPacketSize0 = gadget->ep0->maxpacket;
++01400 
++01401 #ifdef CONFIG_USB_GADGET_DUALSPEED
++01402         /* assume ep0 uses the same value for both speeds ... */
++01403         dev_qualifier.bMaxPacketSize0 = device_desc.bMaxPacketSize0;
++01404 
++01405         /* and that all endpoints are dual-speed */
++01406         //hs_source_desc.bEndpointAddress = fs_source_desc.bEndpointAddress;
++01407         //hs_sink_desc.bEndpointAddress = fs_sink_desc.bEndpointAddress;
++01408 #endif
++01409 
++01410         usb_gadget_set_selfpowered (gadget);
++01411 
++01412         init_timer (&dev->resume);
++01413         dev->resume.function = zero_autoresume;
++01414         dev->resume.data = (unsigned long) dev;
++01415 
++01416         gadget->ep0->driver_data = dev;
++01417 
++01418         INFO (dev, "%s, version: " DRIVER_VERSION "\n", longname);
++01419         INFO (dev, "using %s, OUT %s IN %s\n", gadget->name,
++01420                 EP_OUT_NAME, EP_IN_NAME);
++01421 
++01422         snprintf (manufacturer, sizeof manufacturer,
++01423                 UTS_SYSNAME " " UTS_RELEASE " with %s",
++01424                 gadget->name);
++01425 
++01426         return 0;
++01427 
++01428 enomem:
++01429         zero_unbind (gadget);
++01430         return -ENOMEM;
++01431 }
++01432 
++01433 /*-------------------------------------------------------------------------*/
++01434 
++01435 static void
++01436 zero_suspend (struct usb_gadget *gadget)
++01437 {
++01438         struct zero_dev         *dev = get_gadget_data (gadget);
++01439 
++01440         if (gadget->speed == USB_SPEED_UNKNOWN)
++01441                 return;
++01442 
++01443         if (autoresume) {
++01444                 mod_timer (&dev->resume, jiffies + (HZ * autoresume));
++01445                 DBG (dev, "suspend, wakeup in %d seconds\n", autoresume);
++01446         } else
++01447                 DBG (dev, "suspend\n");
++01448 }
++01449 
++01450 static void
++01451 zero_resume (struct usb_gadget *gadget)
++01452 {
++01453         struct zero_dev         *dev = get_gadget_data (gadget);
++01454 
++01455         DBG (dev, "resume\n");
++01456         del_timer (&dev->resume);
++01457 }
++01458 
++01459 
++01460 /*-------------------------------------------------------------------------*/
++01461 
++01462 static struct usb_gadget_driver zero_driver = {
++01463 #ifdef CONFIG_USB_GADGET_DUALSPEED
++01464         .speed          = USB_SPEED_HIGH,
++01465 #else
++01466         .speed          = USB_SPEED_FULL,
++01467 #endif
++01468         .function       = (char *) longname,
++01469         .bind           = zero_bind,
++01470         .unbind         = zero_unbind,
++01471 
++01472         .setup          = zero_setup,
++01473         .disconnect     = zero_disconnect,
++01474 
++01475         .suspend        = zero_suspend,
++01476         .resume         = zero_resume,
++01477 
++01478         .driver         = {
++01479                 .name           = (char *) shortname,
++01480                 // .shutdown = ...
++01481                 // .suspend = ...
++01482                 // .resume = ...
++01483         },
++01484 };
++01485 
++01486 MODULE_AUTHOR ("David Brownell");
++01487 MODULE_LICENSE ("Dual BSD/GPL");
++01488 
++01489 static struct proc_dir_entry *pdir, *pfile;
++01490 
++01491 static int isoc_read_data (char *page, char **start,
++01492                            off_t off, int count,
++01493                            int *eof, void *data)
++01494 {
++01495         int i;
++01496         static int c = 0;
++01497         static int done = 0;
++01498         static int s = 0;
++01499 
++01500 /*
++01501         printk ("\ncount: %d\n", count);
++01502         printk ("rbuf_start: %d\n", rbuf_start);
++01503         printk ("rbuf_len: %d\n", rbuf_len);
++01504         printk ("off: %d\n", off);
++01505         printk ("start: %p\n\n", *start);
++01506 */
++01507         if (done) {
++01508                 c = 0;
++01509                 done = 0;
++01510                 *eof = 1;
++01511                 return 0;
++01512         }
++01513 
++01514         if (c == 0) {
++01515                 if (rbuf_len == RBUF_LEN)
++01516                         s = rbuf_start;
++01517                 else s = 0;
++01518         }
++01519 
++01520         for (i=0; i<count && c<rbuf_len; i++, c++) {
++01521                 page[i] = rbuf[(c+s) % RBUF_LEN];
++01522         }
++01523         *start = page;
++01524         
++01525         if (c >= rbuf_len) {
++01526                 *eof = 1;
++01527                 done = 1;
++01528         }
++01529 
++01530 
++01531         return i;
++01532 }
++01533 
++01534 static int __init init (void)
++01535 {
++01536 
++01537         int retval = 0;
++01538 
++01539         pdir = proc_mkdir("isoc_test", NULL);
++01540         if(pdir == NULL) {
++01541                 retval = -ENOMEM;
++01542                 printk("Error creating dir\n");
++01543                 goto done;
++01544         }
++01545         pdir->owner = THIS_MODULE;
++01546 
++01547         pfile = create_proc_read_entry("isoc_data",
++01548                                        0444, pdir,
++01549                                        isoc_read_data,
++01550                                        NULL);
++01551         if (pfile == NULL) {
++01552                 retval = -ENOMEM;
++01553                 printk("Error creating file\n");
++01554                 goto no_file;
++01555         }
++01556         pfile->owner = THIS_MODULE;
++01557 
++01558         return usb_gadget_register_driver (&zero_driver);
++01559 
++01560  no_file:
++01561         remove_proc_entry("isoc_data", NULL);
++01562  done:
++01563         return retval;
++01564 }
++01565 module_init (init);
++01566 
++01567 static void __exit cleanup (void)
++01568 {
++01569 
++01570         usb_gadget_unregister_driver (&zero_driver);
++01571         
++01572         remove_proc_entry("isoc_data", pdir);
++01573         remove_proc_entry("isoc_test", NULL);
++01574 }
++01575 module_exit (cleanup);
++
Generated on Tue May 5 02:22:48 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__cfi__common_8h-source.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__cfi__common_8h-source.html 2013-07-26 19:31:20.000000000 +0000 +@@ -0,0 +1,115 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_cfi_common.h Source File ++ ++ ++ ++ ++
++
++
++
++

dwc_cfi_common.h

Go to the documentation of this file.
00001 /* ==========================================================================
++00002  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
++00003  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
++00004  * otherwise expressly agreed to in writing between Synopsys and you.
++00005  * 
++00006  * The Software IS NOT an item of Licensed Software or Licensed Product under
++00007  * any End User Software License Agreement or Agreement for Licensed Product
++00008  * with Synopsys or any supplement thereto. You are permitted to use and
++00009  * redistribute this Software in source and binary forms, with or without
++00010  * modification, provided that redistributions of source code must retain this
++00011  * notice. You may not view, use, disclose, copy or distribute this file or
++00012  * any information contained herein except pursuant to this license grant from
++00013  * Synopsys. If you do not agree with this notice, including the disclaimer
++00014  * below, then you are not authorized to use the Software.
++00015  * 
++00016  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
++00017  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++00018  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++00019  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
++00020  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++00021  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
++00022  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
++00023  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
++00024  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
++00025  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
++00026  * DAMAGE.
++00027  * ========================================================================== */
++00028 
++00029 #if !defined(__DWC_CFI_COMMON_H__)
++00030 #define __DWC_CFI_COMMON_H__
++00031 
++00032 //#include <linux/types.h>
++00033 
++00044 #define VEN_CORE_GET_FEATURES           0xB1
++00045 
++00047 #define VEN_CORE_GET_FEATURE            0xB2
++00048 
++00050 #define VEN_CORE_SET_FEATURE            0xB3
++00051 
++00055 #define VEN_CORE_RESET_FEATURES         0xB4
++00056 
++00058 #define VEN_CORE_ACTIVATE_FEATURES      0xB5
++00059 
++00061 #define VEN_CORE_READ_REGISTER          0xB6
++00062 
++00064 #define VEN_CORE_WRITE_REGISTER         0xB7
++00065 
++00069 struct cfi_all_features_header {
++00071 #define CFI_ALL_FEATURES_HDR_LEN                8
++00072 
++00075         uint16_t wTotalLen;
++00076 
++00082         uint16_t wVersion;
++00083 
++00085         uint16_t wCoreID;
++00086 #define CFI_CORE_ID_UDC         1
++00087 #define CFI_CORE_ID_OTG         2
++00088 #define CFI_CORE_ID_WUDEV       3
++00089 
++00091         uint16_t wNumFeatures;
++00092 } UPACKED;
++00093 
++00094 typedef struct cfi_all_features_header cfi_all_features_header_t;
++00095 
++00099 struct cfi_feature_desc_header {
++00100 #define CFI_FEATURE_DESC_HDR_LEN        8
++00101 
++00103         uint16_t wFeatureID;
++00104 
++00108         uint16_t wLength;
++00109 
++00111         uint16_t wDataLength;
++00112 
++00119         uint8_t bmAttributes;
++00120 #define CFI_FEATURE_ATTR_RO             1
++00121 #define CFI_FEATURE_ATTR_RW             0
++00122 
++00124         uint8_t bNameLen;
++00125 
++00127         //uint8_t *name;
++00128 } UPACKED;
++00129 
++00130 typedef struct cfi_feature_desc_header cfi_feature_desc_header_t;
++00131 
++00136 struct cfi_string {
++00137         uint16_t id;
++00138         const uint8_t *s;
++00139 };
++00140 typedef struct cfi_string cfi_string_t;
++00141 
++00142 #endif
++
Generated on Tue May 5 02:22:48 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__cfi__common_8h.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__cfi__common_8h.html 2013-07-26 19:31:20.000000000 +0000 +@@ -0,0 +1,119 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_cfi_common.h File Reference ++ ++ ++ ++ ++
++
++
++
++

dwc_cfi_common.h File Reference

This file contains the CFI specific common constants, interfaces (functions and macros) and structures for Linux. More... ++

++ ++

++Go to the source code of this file. ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++

Data Structures

struct  cfi_all_features_header
 This structure is the header of the Core Features dataset returned to the Host. More...
struct  cfi_feature_desc_header
 This structure is a header of the Core Feature descriptor dataset returned to the Host after the VEN_CORE_GET_FEATURES request. More...
struct  cfi_string
 This structure describes a NULL terminated string referenced by its id field. More...

Defines

++#define __DWC_CFI_COMMON_H__
++#define VEN_CORE_GET_FEATURES   0xB1
 This is a request for all Core Features.
++#define VEN_CORE_GET_FEATURE   0xB2
 This is a request to get the value of a specific Core Feature.
++#define VEN_CORE_SET_FEATURE   0xB3
 This command allows the host to set the value of a specific Core Feature.
++#define VEN_CORE_RESET_FEATURES   0xB4
 This command allows the host to set the default values of either all or any specific Core Feature.
++#define VEN_CORE_ACTIVATE_FEATURES   0xB5
 This command forces the PCD to write the deferred values of a Core Features.
++#define VEN_CORE_READ_REGISTER   0xB6
 This request reads a DWORD value from a register at the specified offset.
++#define VEN_CORE_WRITE_REGISTER   0xB7
 This request writes a DWORD value into a register at the specified offset.
++#define CFI_ALL_FEATURES_HDR_LEN   8
 The features header structure length is.
++#define CFI_CORE_ID_UDC   1
++#define CFI_CORE_ID_OTG   2
++#define CFI_CORE_ID_WUDEV   3
++#define CFI_FEATURE_DESC_HDR_LEN   8
++#define CFI_FEATURE_ATTR_RO   1
++#define CFI_FEATURE_ATTR_RW   0

Typedefs

++typedef cfi_all_features_header cfi_all_features_header_t
++typedef cfi_feature_desc_header cfi_feature_desc_header_t
++typedef cfi_string cfi_string_t

Variables

++cfi_all_features_header UPACKED
 This structure is the header of the Core Features dataset returned to the Host.
++cfi_feature_desc_header UPACKED
 This structure is a header of the Core Feature descriptor dataset returned to the Host after the VEN_CORE_GET_FEATURES request.
++

Detailed Description

++This file contains the CFI specific common constants, interfaces (functions and macros) and structures for Linux. ++

++No PCD specific data structure or definition is to be included in this file. ++

++Definition in file dwc_cfi_common.h.

Generated on Tue May 5 02:22:48 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__attr_8c-source.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__attr_8c-source.html 2013-07-26 19:31:20.000000000 +0000 +@@ -0,0 +1,828 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_attr.c Source File ++ ++ ++ ++ ++
++
++
++
++

dwc_otg_attr.c

Go to the documentation of this file.
00001 /* ==========================================================================
++00002  * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_attr.c $
++00003  * $Revision: #35 $
++00004  * $Date: 2009/04/03 $
++00005  * $Change: 1225160 $
++00006  *
++00007  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
++00008  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
++00009  * otherwise expressly agreed to in writing between Synopsys and you.
++00010  *
++00011  * The Software IS NOT an item of Licensed Software or Licensed Product under
++00012  * any End User Software License Agreement or Agreement for Licensed Product
++00013  * with Synopsys or any supplement thereto. You are permitted to use and
++00014  * redistribute this Software in source and binary forms, with or without
++00015  * modification, provided that redistributions of source code must retain this
++00016  * notice. You may not view, use, disclose, copy or distribute this file or
++00017  * any information contained herein except pursuant to this license grant from
++00018  * Synopsys. If you do not agree with this notice, including the disclaimer
++00019  * below, then you are not authorized to use the Software.
++00020  *
++00021  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
++00022  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++00023  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++00024  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
++00025  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++00026  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
++00027  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
++00028  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
++00029  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
++00030  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
++00031  * DAMAGE.
++00032  * ========================================================================== */
++00033 
++00286 #include <linux/kernel.h>
++00287 #include <linux/module.h>
++00288 #include <linux/moduleparam.h>
++00289 #include <linux/init.h>
++00290 #include <linux/device.h>
++00291 #include <linux/errno.h>
++00292 #include <linux/types.h>
++00293 #include <linux/stat.h>         /* permission constants */
++00294 #include <linux/version.h>
++00295 #include <linux/param.h>
++00296 #include <linux/delay.h>
++00297 #include <linux/jiffies.h>
++00298 
++00299 
++00300 #ifdef LM_INTERFACE
++00301 #include <asm/sizes.h>
++00302 #include <asm/arch/lm.h>
++00303 #endif
++00304 
++00305 #include <asm/io.h>
++00306 
++00307 #include "dwc_os.h"
++00308 #include "dwc_otg_driver.h"
++00309 #include "dwc_otg_attr.h"
++00310 #include "dwc_otg_core_if.h"
++00311 #include "dwc_otg_pcd_if.h"
++00312 #include "dwc_otg_hcd_if.h"
++00313 
++00314 /*
++00315  * MACROs for defining sysfs attribute
++00316  */
++00317 #ifdef LM_INTERFACE
++00318 
++00319 #define DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_string_) \
++00320 static ssize_t _otg_attr_name_##_show (struct device *_dev, struct device_attribute *attr, char *buf) \
++00321 { \
++00322         struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev); \
++00323         dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);             \
++00324         uint32_t val; \
++00325         val = dwc_otg_get_##_otg_attr_name_ (otg_dev->core_if); \
++00326         return sprintf (buf, "%s = 0x%x\n", _string_, val); \
++00327 }
++00328 #define DWC_OTG_DEVICE_ATTR_BITFIELD_STORE(_otg_attr_name_,_string_) \
++00329 static ssize_t _otg_attr_name_##_store (struct device *_dev, struct device_attribute *attr, \
++00330                                         const char *buf, size_t count) \
++00331 { \
++00332         struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev); \
++00333         dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev); \
++00334         uint32_t set = simple_strtoul(buf, NULL, 16); \
++00335         dwc_otg_set_##_otg_attr_name_(otg_dev->core_if, set);\
++00336         return count; \
++00337 }
++00338 
++00339 #elif PCI_INTERFACE
++00340 
++00341 #define DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_string_) \
++00342 static ssize_t _otg_attr_name_##_show (struct device *_dev, struct device_attribute *attr, char *buf) \
++00343 { \
++00344         dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);      \
++00345         uint32_t val; \
++00346         val = dwc_otg_get_##_otg_attr_name_ (otg_dev->core_if); \
++00347         return sprintf (buf, "%s = 0x%x\n", _string_, val); \
++00348 }
++00349 #define DWC_OTG_DEVICE_ATTR_BITFIELD_STORE(_otg_attr_name_,_string_) \
++00350 static ssize_t _otg_attr_name_##_store (struct device *_dev, struct device_attribute *attr, \
++00351                                         const char *buf, size_t count) \
++00352 { \
++00353         dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);  \
++00354         uint32_t set = simple_strtoul(buf, NULL, 16); \
++00355         dwc_otg_set_##_otg_attr_name_(otg_dev->core_if, set);\
++00356         return count; \
++00357 }
++00358 
++00359 #endif
++00360 
++00361 /*
++00362  * MACROs for defining sysfs attribute for 32-bit registers
++00363  */
++00364 #ifdef LM_INTERFACE
++00365 #define DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_string_) \
++00366 static ssize_t _otg_attr_name_##_show (struct device *_dev, struct device_attribute *attr, char *buf) \
++00367 { \
++00368         struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev); \
++00369         dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev); \
++00370         uint32_t val; \
++00371         val = dwc_otg_get_##_otg_attr_name_ (otg_dev->core_if); \
++00372         return sprintf (buf, "%s = 0x%08x\n", _string_, val); \
++00373 }
++00374 #define DWC_OTG_DEVICE_ATTR_REG_STORE(_otg_attr_name_,_string_) \
++00375 static ssize_t _otg_attr_name_##_store (struct device *_dev, struct device_attribute *attr, \
++00376                                         const char *buf, size_t count) \
++00377 { \
++00378         struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev); \
++00379         dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev); \
++00380         uint32_t val = simple_strtoul(buf, NULL, 16); \
++00381         dwc_otg_set_##_otg_attr_name_ (otg_dev->core_if, val); \
++00382         return count; \
++00383 }
++00384 #elif PCI_INTERFACE
++00385 #define DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_string_) \
++00386 static ssize_t _otg_attr_name_##_show (struct device *_dev, struct device_attribute *attr, char *buf) \
++00387 { \
++00388         dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);  \
++00389         uint32_t val; \
++00390         val = dwc_otg_get_##_otg_attr_name_ (otg_dev->core_if); \
++00391         return sprintf (buf, "%s = 0x%08x\n", _string_, val); \
++00392 }
++00393 #define DWC_OTG_DEVICE_ATTR_REG_STORE(_otg_attr_name_,_string_) \
++00394 static ssize_t _otg_attr_name_##_store (struct device *_dev, struct device_attribute *attr, \
++00395                                         const char *buf, size_t count) \
++00396 { \
++00397         dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);  \
++00398         uint32_t val = simple_strtoul(buf, NULL, 16); \
++00399         dwc_otg_set_##_otg_attr_name_ (otg_dev->core_if, val); \
++00400         return count; \
++00401 }
++00402 
++00403 #endif
++00404 
++00405 #define DWC_OTG_DEVICE_ATTR_BITFIELD_RW(_otg_attr_name_,_string_) \
++00406 DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_string_) \
++00407 DWC_OTG_DEVICE_ATTR_BITFIELD_STORE(_otg_attr_name_,_string_) \
++00408 DEVICE_ATTR(_otg_attr_name_,0644,_otg_attr_name_##_show,_otg_attr_name_##_store);
++00409 
++00410 #define DWC_OTG_DEVICE_ATTR_BITFIELD_RO(_otg_attr_name_,_string_) \
++00411 DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_string_) \
++00412 DEVICE_ATTR(_otg_attr_name_,0444,_otg_attr_name_##_show,NULL);
++00413 
++00414 #define DWC_OTG_DEVICE_ATTR_REG32_RW(_otg_attr_name_,_addr_,_string_) \
++00415 DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_string_) \
++00416 DWC_OTG_DEVICE_ATTR_REG_STORE(_otg_attr_name_,_string_) \
++00417 DEVICE_ATTR(_otg_attr_name_,0644,_otg_attr_name_##_show,_otg_attr_name_##_store);
++00418 
++00419 #define DWC_OTG_DEVICE_ATTR_REG32_RO(_otg_attr_name_,_addr_,_string_) \
++00420 DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_string_) \
++00421 DEVICE_ATTR(_otg_attr_name_,0444,_otg_attr_name_##_show,NULL);
++00422 
++00429 static ssize_t regoffset_show(struct device *_dev,
++00430                               struct device_attribute *attr, char *buf)
++00431 {
++00432 #ifdef LM_INTERFACE
++00433         struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
++00434         dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
++00435 #elif PCI_INTERFACE
++00436         dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
++00437 #endif
++00438 
++00439         return snprintf(buf, sizeof("0xFFFFFFFF\n") + 1, "0x%08x\n",
++00440                         otg_dev->reg_offset);
++00441 }
++00442 
++00446 static ssize_t regoffset_store(struct device *_dev,
++00447                                struct device_attribute *attr,
++00448                                const char *buf, size_t count)
++00449 {
++00450 #ifdef LM_INTERFACE
++00451         struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
++00452         dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
++00453 #elif PCI_INTERFACE
++00454         dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
++00455 #endif
++00456 
++00457         uint32_t offset = simple_strtoul(buf, NULL, 16);
++00458 #ifdef LM_INTERFACE
++00459         if (offset < SZ_256K) {
++00460 #elif  PCI_INTERFACE
++00461         if (offset < 0x00040000) {
++00462 #endif
++00463                 otg_dev->reg_offset = offset;
++00464         } else {
++00465                 dev_err(_dev, "invalid offset\n");
++00466         }
++00467 
++00468         return count;
++00469 }
++00470 
++00471 DEVICE_ATTR(regoffset, S_IRUGO | S_IWUSR, regoffset_show, regoffset_store);
++00472 
++00477 static ssize_t regvalue_show(struct device *_dev,
++00478                              struct device_attribute *attr, char *buf)
++00479 {
++00480 #ifdef LM_INTERFACE
++00481         struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
++00482         dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
++00483 #elif PCI_INTERFACE
++00484         dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
++00485 #endif
++00486 
++00487         uint32_t val;
++00488         volatile uint32_t *addr;
++00489 
++00490         if (otg_dev->reg_offset != 0xFFFFFFFF && 0 != otg_dev->base) {
++00491                 /* Calculate the address */
++00492                 addr = (uint32_t *) (otg_dev->reg_offset +
++00493                                      (uint8_t *) otg_dev->base);
++00494                 val = dwc_read_reg32(addr);
++00495                 return snprintf(buf,
++00496                                 sizeof("Reg@0xFFFFFFFF = 0xFFFFFFFF\n") + 1,
++00497                                 "Reg@0x%06x = 0x%08x\n", otg_dev->reg_offset,
++00498                                 val);
++00499         } else {
++00500                 dev_err(_dev, "Invalid offset (0x%0x)\n", otg_dev->reg_offset);
++00501                 return sprintf(buf, "invalid offset\n");
++00502         }
++00503 }
++00504 
++00510 static ssize_t regvalue_store(struct device *_dev,
++00511                               struct device_attribute *attr,
++00512                               const char *buf, size_t count)
++00513 {
++00514 #ifdef LM_INTERFACE
++00515         struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
++00516         dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
++00517 #elif PCI_INTERFACE
++00518         dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
++00519 #endif
++00520 
++00521         volatile uint32_t *addr;
++00522         uint32_t val = simple_strtoul(buf, NULL, 16);
++00523         //dev_dbg(_dev, "Offset=0x%08x Val=0x%08x\n", otg_dev->reg_offset, val);
++00524         if (otg_dev->reg_offset != 0xFFFFFFFF && 0 != otg_dev->base) {
++00525                 /* Calculate the address */
++00526                 addr = (uint32_t *) (otg_dev->reg_offset +
++00527                                      (uint8_t *) otg_dev->base);
++00528                 dwc_write_reg32(addr, val);
++00529         } else {
++00530                 dev_err(_dev, "Invalid Register Offset (0x%08x)\n",
++00531                         otg_dev->reg_offset);
++00532         }
++00533         return count;
++00534 }
++00535 
++00536 DEVICE_ATTR(regvalue, S_IRUGO | S_IWUSR, regvalue_show, regvalue_store);
++00537 
++00538 /*
++00539  * Attributes
++00540  */
++00541 DWC_OTG_DEVICE_ATTR_BITFIELD_RO(mode, "Mode");
++00542 DWC_OTG_DEVICE_ATTR_BITFIELD_RW(hnpcapable, "HNPCapable");
++00543 DWC_OTG_DEVICE_ATTR_BITFIELD_RW(srpcapable, "Mode");
++00544 DWC_OTG_DEVICE_ATTR_BITFIELD_RW(hsic_connect, "HSIC Connect");
++00545 DWC_OTG_DEVICE_ATTR_BITFIELD_RW(inv_sel_hsic, "Invert Select HSIC");
++00546 
++00547 //DWC_OTG_DEVICE_ATTR_BITFIELD_RW(buspower,&(otg_dev->core_if->core_global_regs->gotgctl),(1<<8),8,"Mode");
++00548 //DWC_OTG_DEVICE_ATTR_BITFIELD_RW(bussuspend,&(otg_dev->core_if->core_global_regs->gotgctl),(1<<8),8,"Mode");
++00549 DWC_OTG_DEVICE_ATTR_BITFIELD_RO(busconnected, "Bus Connected");
++00550 
++00551 DWC_OTG_DEVICE_ATTR_REG32_RW(gotgctl, 0, "GOTGCTL");
++00552 DWC_OTG_DEVICE_ATTR_REG32_RW(gusbcfg,
++00553                              &(otg_dev->core_if->core_global_regs->gusbcfg),
++00554                              "GUSBCFG");
++00555 DWC_OTG_DEVICE_ATTR_REG32_RW(grxfsiz,
++00556                              &(otg_dev->core_if->core_global_regs->grxfsiz),
++00557                              "GRXFSIZ");
++00558 DWC_OTG_DEVICE_ATTR_REG32_RW(gnptxfsiz,
++00559                              &(otg_dev->core_if->core_global_regs->gnptxfsiz),
++00560                              "GNPTXFSIZ");
++00561 DWC_OTG_DEVICE_ATTR_REG32_RW(gpvndctl,
++00562                              &(otg_dev->core_if->core_global_regs->gpvndctl),
++00563                              "GPVNDCTL");
++00564 DWC_OTG_DEVICE_ATTR_REG32_RW(ggpio,
++00565                              &(otg_dev->core_if->core_global_regs->ggpio),
++00566                              "GGPIO");
++00567 DWC_OTG_DEVICE_ATTR_REG32_RW(guid, &(otg_dev->core_if->core_global_regs->guid),
++00568                              "GUID");
++00569 DWC_OTG_DEVICE_ATTR_REG32_RO(gsnpsid,
++00570                              &(otg_dev->core_if->core_global_regs->gsnpsid),
++00571                              "GSNPSID");
++00572 DWC_OTG_DEVICE_ATTR_BITFIELD_RW(devspeed, "Device Speed");
++00573 DWC_OTG_DEVICE_ATTR_BITFIELD_RO(enumspeed, "Device Enumeration Speed");
++00574 
++00575 DWC_OTG_DEVICE_ATTR_REG32_RO(hptxfsiz,
++00576                              &(otg_dev->core_if->core_global_regs->hptxfsiz),
++00577                              "HPTXFSIZ");
++00578 DWC_OTG_DEVICE_ATTR_REG32_RW(hprt0, otg_dev->core_if->host_if->hprt0, "HPRT0");
++00579 
++00586 static ssize_t hnp_show(struct device *_dev,
++00587                         struct device_attribute *attr, char *buf)
++00588 {
++00589 #ifdef LM_INTERFACE
++00590         struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
++00591         dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
++00592 #elif PCI_INTERFACE
++00593         dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
++00594 #endif
++00595         return sprintf(buf, "HstNegScs = 0x%x\n",
++00596                        dwc_otg_get_hnpstatus(otg_dev->core_if));
++00597 }
++00598 
++00602 static ssize_t hnp_store(struct device *_dev,
++00603                          struct device_attribute *attr,
++00604                          const char *buf, size_t count)
++00605 {
++00606 #ifdef LM_INTERFACE
++00607         struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
++00608         dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
++00609 #elif PCI_INTERFACE
++00610         dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
++00611 #endif
++00612         uint32_t in = simple_strtoul(buf, NULL, 16);
++00613         dwc_otg_set_hnpreq(otg_dev->core_if, in);
++00614         return count;
++00615 }
++00616 
++00617 DEVICE_ATTR(hnp, 0644, hnp_show, hnp_store);
++00618 
++00625 static ssize_t srp_show(struct device *_dev,
++00626                         struct device_attribute *attr, char *buf)
++00627 {
++00628 #ifndef DWC_HOST_ONLY
++00629 #ifdef LM_INTERFACE
++00630         struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
++00631         dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
++00632 #elif PCI_INTERFACE
++00633         dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
++00634 #endif
++00635         return sprintf(buf, "SesReqScs = 0x%x\n",
++00636                        dwc_otg_get_srpstatus(otg_dev->core_if));
++00637 #else
++00638         return sprintf(buf, "Host Only Mode!\n");
++00639 #endif
++00640 }
++00641 
++00645 static ssize_t srp_store(struct device *_dev,
++00646                          struct device_attribute *attr,
++00647                          const char *buf, size_t count)
++00648 {
++00649 #ifndef DWC_HOST_ONLY
++00650 #ifdef LM_INTERFACE
++00651         struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
++00652         dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
++00653 #elif PCI_INTERFACE
++00654         dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
++00655 #endif
++00656         dwc_otg_pcd_initiate_srp(otg_dev->pcd);
++00657 #endif
++00658         return count;
++00659 }
++00660 
++00661 DEVICE_ATTR(srp, 0644, srp_show, srp_store);
++00662 
++00669 static ssize_t buspower_show(struct device *_dev,
++00670                              struct device_attribute *attr, char *buf)
++00671 {
++00672 #ifdef LM_INTERFACE
++00673         struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
++00674         dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
++00675 #elif PCI_INTERFACE
++00676         dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
++00677 #endif
++00678         return sprintf(buf, "Bus Power = 0x%x\n",
++00679                        dwc_otg_get_prtpower(otg_dev->core_if));
++00680 }
++00681 
++00685 static ssize_t buspower_store(struct device *_dev,
++00686                               struct device_attribute *attr,
++00687                               const char *buf, size_t count)
++00688 {
++00689 #ifdef LM_INTERFACE
++00690         struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
++00691         dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
++00692 #elif PCI_INTERFACE
++00693         dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
++00694 #endif
++00695         uint32_t on = simple_strtoul(buf, NULL, 16);
++00696         dwc_otg_set_prtpower(otg_dev->core_if, on);
++00697         return count;
++00698 }
++00699 
++00700 DEVICE_ATTR(buspower, 0644, buspower_show, buspower_store);
++00701 
++00708 static ssize_t bussuspend_show(struct device *_dev,
++00709                                struct device_attribute *attr, char *buf)
++00710 {
++00711 #ifdef LM_INTERFACE
++00712         struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
++00713         dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
++00714 #elif PCI_INTERFACE
++00715         dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
++00716 #endif
++00717 
++00718         return sprintf(buf, "Bus Suspend = 0x%x\n",
++00719                        dwc_otg_get_prtsuspend(otg_dev->core_if));
++00720 }
++00721 
++00725 static ssize_t bussuspend_store(struct device *_dev,
++00726                                 struct device_attribute *attr,
++00727                                 const char *buf, size_t count)
++00728 {
++00729 #ifdef LM_INTERFACE
++00730         struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
++00731         dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
++00732 #elif PCI_INTERFACE
++00733         dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
++00734 #endif
++00735 
++00736         uint32_t in = simple_strtoul(buf, NULL, 16);
++00737         dwc_otg_set_prtsuspend(otg_dev->core_if, in);
++00738         return count;
++00739 }
++00740 
++00741 DEVICE_ATTR(bussuspend, 0644, bussuspend_show, bussuspend_store);
++00742 
++00746 static ssize_t remote_wakeup_show(struct device *_dev,
++00747                                   struct device_attribute *attr, char *buf)
++00748 {
++00749 #ifndef DWC_HOST_ONLY
++00750 #ifdef LM_INTERFACE
++00751         struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
++00752         dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
++00753 #elif PCI_INTERFACE
++00754         dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
++00755 #endif
++00756 
++00757         return sprintf(buf,
++00758                        "Remote Wakeup Sig = %d Enabled = %d LPM Remote Wakeup = %d\n",
++00759                        dwc_otg_get_remotewakesig(otg_dev->core_if),
++00760                        dwc_otg_pcd_get_rmwkup_enable(otg_dev->pcd),
++00761                        dwc_otg_get_lpm_remotewakeenabled(otg_dev->core_if));
++00762 #else
++00763         return sprintf(buf, "Host Only Mode!\n");
++00764 #endif /* DWC_HOST_ONLY */
++00765 }
++00766 
++00773 static ssize_t remote_wakeup_store(struct device *_dev,
++00774                                    struct device_attribute *attr,
++00775                                    const char *buf, size_t count)
++00776 {
++00777 #ifndef DWC_HOST_ONLY
++00778 #ifdef LM_INTERFACE
++00779         struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
++00780         dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
++00781 #elif PCI_INTERFACE
++00782         dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
++00783 #endif
++00784 
++00785         uint32_t val = simple_strtoul(buf, NULL, 16);
++00786 
++00787         if (val & 1) {
++00788                 dwc_otg_pcd_remote_wakeup(otg_dev->pcd, 1);
++00789         } else {
++00790                 dwc_otg_pcd_remote_wakeup(otg_dev->pcd, 0);
++00791         }
++00792 #endif /* DWC_HOST_ONLY */
++00793         return count;
++00794 }
++00795 
++00796 DEVICE_ATTR(remote_wakeup, S_IRUGO | S_IWUSR, remote_wakeup_show,
++00797             remote_wakeup_store);
++00798 
++00803 static ssize_t regdump_show(struct device *_dev,
++00804                             struct device_attribute *attr, char *buf)
++00805 {
++00806 #ifdef LM_INTERFACE
++00807         struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
++00808         dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
++00809 #elif PCI_INTERFACE
++00810         dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
++00811 #endif
++00812 
++00813         dwc_otg_dump_global_registers(otg_dev->core_if);
++00814         if (dwc_otg_is_host_mode(otg_dev->core_if)) {
++00815                 dwc_otg_dump_host_registers(otg_dev->core_if);
++00816         } else {
++00817                 dwc_otg_dump_dev_registers(otg_dev->core_if);
++00818 
++00819         }
++00820         return sprintf(buf, "Register Dump\n");
++00821 }
++00822 
++00823 DEVICE_ATTR(regdump, S_IRUGO | S_IWUSR, regdump_show, 0);
++00824 
++00829 static ssize_t spramdump_show(struct device *_dev,
++00830                               struct device_attribute *attr, char *buf)
++00831 {
++00832 #ifdef LM_INTERFACE
++00833         struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
++00834         dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
++00835 #elif PCI_INTERFACE
++00836         dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
++00837 #endif
++00838 
++00839         dwc_otg_dump_spram(otg_dev->core_if);
++00840 
++00841         return sprintf(buf, "SPRAM Dump\n");
++00842 }
++00843 
++00844 DEVICE_ATTR(spramdump, S_IRUGO | S_IWUSR, spramdump_show, 0);
++00845 
++00849 static ssize_t hcddump_show(struct device *_dev,
++00850                             struct device_attribute *attr, char *buf)
++00851 {
++00852 #ifndef DWC_DEVICE_ONLY
++00853 #ifdef LM_INTERFACE
++00854         struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
++00855         dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
++00856 #elif PCI_INTERFACE
++00857         dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
++00858 #endif
++00859 
++00860         dwc_otg_hcd_dump_state(otg_dev->hcd);
++00861 #endif /* DWC_DEVICE_ONLY */
++00862         return sprintf(buf, "HCD Dump\n");
++00863 }
++00864 
++00865 DEVICE_ATTR(hcddump, S_IRUGO | S_IWUSR, hcddump_show, 0);
++00866 
++00872 static ssize_t hcd_frrem_show(struct device *_dev,
++00873                               struct device_attribute *attr, char *buf)
++00874 {
++00875 #ifndef DWC_DEVICE_ONLY
++00876 #ifdef LM_INTERFACE
++00877         struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
++00878         dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
++00879 #elif PCI_INTERFACE
++00880         dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
++00881 #endif
++00882 
++00883         dwc_otg_hcd_dump_frrem(otg_dev->hcd);
++00884 #endif /* DWC_DEVICE_ONLY */
++00885         return sprintf(buf, "HCD Dump Frame Remaining\n");
++00886 }
++00887 
++00888 DEVICE_ATTR(hcd_frrem, S_IRUGO | S_IWUSR, hcd_frrem_show, 0);
++00889 
++00894 #define RW_REG_COUNT 10000000
++00895 #define MSEC_PER_JIFFIE 1000/HZ
++00896 static ssize_t rd_reg_test_show(struct device *_dev,
++00897                                 struct device_attribute *attr, char *buf)
++00898 {
++00899 #ifdef LM_INTERFACE
++00900         struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
++00901         dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
++00902 #elif PCI_INTERFACE
++00903         dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
++00904 #endif
++00905 
++00906         int i;
++00907         int time;
++00908         int start_jiffies;
++00909 
++00910         printk("HZ %d, MSEC_PER_JIFFIE %d, loops_per_jiffy %lu\n",
++00911                HZ, MSEC_PER_JIFFIE, loops_per_jiffy);
++00912         start_jiffies = jiffies;
++00913         for (i = 0; i < RW_REG_COUNT; i++) {
++00914                 dwc_otg_get_gnptxfsiz(otg_dev->core_if);
++00915         }
++00916         time = jiffies - start_jiffies;
++00917         return sprintf(buf,
++00918                        "Time to read GNPTXFSIZ reg %d times: %d msecs (%d jiffies)\n",
++00919                        RW_REG_COUNT, time * MSEC_PER_JIFFIE, time);
++00920 }
++00921 
++00922 DEVICE_ATTR(rd_reg_test, S_IRUGO | S_IWUSR, rd_reg_test_show, 0);
++00923 
++00928 static ssize_t wr_reg_test_show(struct device *_dev,
++00929                                 struct device_attribute *attr, char *buf)
++00930 {
++00931 #ifdef LM_INTERFACE
++00932         struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
++00933         dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
++00934 #elif PCI_INTERFACE
++00935         dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
++00936 #endif
++00937 
++00938         uint32_t reg_val;
++00939         int i;
++00940         int time;
++00941         int start_jiffies;
++00942 
++00943         printk("HZ %d, MSEC_PER_JIFFIE %d, loops_per_jiffy %lu\n",
++00944                HZ, MSEC_PER_JIFFIE, loops_per_jiffy);
++00945         reg_val = dwc_otg_get_gnptxfsiz(otg_dev->core_if);
++00946         start_jiffies = jiffies;
++00947         for (i = 0; i < RW_REG_COUNT; i++) {
++00948                 dwc_otg_set_gnptxfsiz(otg_dev->core_if, reg_val);
++00949         }
++00950         time = jiffies - start_jiffies;
++00951         return sprintf(buf,
++00952                        "Time to write GNPTXFSIZ reg %d times: %d msecs (%d jiffies)\n",
++00953                        RW_REG_COUNT, time * MSEC_PER_JIFFIE, time);
++00954 }
++00955 
++00956 DEVICE_ATTR(wr_reg_test, S_IRUGO | S_IWUSR, wr_reg_test_show, 0);
++00957 
++00958 #ifdef CONFIG_USB_DWC_OTG_LPM
++00959 
++00963 static ssize_t lpmresp_show(struct device *_dev,
++00964                             struct device_attribute *attr, char *buf)
++00965 {
++00966 #ifdef LM_INTERFACE
++00967         struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
++00968         dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
++00969 #elif PCI_INTERFACE
++00970         dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
++00971 #endif
++00972 
++00973         if (!dwc_otg_get_param_lpm_enable(otg_dev->core_if))
++00974                 return sprintf(buf, "** LPM is DISABLED **\n");
++00975 
++00976         if (!dwc_otg_is_device_mode(otg_dev->core_if)) {
++00977                 return sprintf(buf, "** Current mode is not device mode\n");
++00978         }
++00979         return sprintf(buf, "lpm_response = %d\n",
++00980                        dwc_otg_get_lpmresponse(otg_dev->core_if));
++00981 }
++00982 
++00986 static ssize_t lpmresp_store(struct device *_dev,
++00987                              struct device_attribute *attr,
++00988                              const char *buf, size_t count)
++00989 {
++00990 #ifdef LM_INTERFACE
++00991         struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
++00992         dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
++00993 #elif PCI_INTERFACE
++00994         dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
++00995 #endif
++00996 
++00997         uint32_t val = simple_strtoul(buf, NULL, 16);
++00998 
++00999         if (!dwc_otg_get_param_lpm_enable(otg_dev->core_if)) {
++01000                 return 0;
++01001         }
++01002 
++01003         if (!dwc_otg_is_device_mode(otg_dev->core_if)) {
++01004                 return 0;
++01005         }
++01006 
++01007         dwc_otg_set_lpmresponse(otg_dev->core_if, val);
++01008         return count;
++01009 }
++01010 
++01011 DEVICE_ATTR(lpm_response, S_IRUGO | S_IWUSR, lpmresp_show, lpmresp_store);
++01012 
++01016 static ssize_t sleepstatus_show(struct device *_dev,
++01017                                 struct device_attribute *attr, char *buf)
++01018 {
++01019 #ifdef LM_INTERFACE
++01020         struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
++01021         dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
++01022 #elif PCI_INTERFACE
++01023         dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
++01024 #endif
++01025 
++01026 
++01027         return sprintf(buf, "Sleep Status = %d\n",
++01028                        dwc_otg_get_lpm_portsleepstatus(otg_dev->core_if));
++01029 }
++01030 
++01034 static ssize_t sleepstatus_store(struct device *_dev,
++01035                                  struct device_attribute *attr,
++01036                                  const char *buf, size_t count)
++01037 {
++01038 #ifdef LM_INTERFACE
++01039         struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
++01040         dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
++01041 #elif PCI_INTERFACE
++01042         dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
++01043 #endif
++01044 
++01045         dwc_otg_core_if_t *core_if = otg_dev->core_if;
++01046 
++01047         if (dwc_otg_get_lpm_portsleepstatus(otg_dev->core_if)) {
++01048                 if (dwc_otg_is_host_mode(core_if)) {
++01049 
++01050                         DWC_PRINTF("Host initiated resume\n");
++01051                         dwc_otg_set_prtresume(otg_dev->core_if, 1);
++01052                 }
++01053         }
++01054 
++01055         return count;
++01056 }
++01057 
++01058 DEVICE_ATTR(sleep_status, S_IRUGO | S_IWUSR, sleepstatus_show,
++01059             sleepstatus_store);
++01060 
++01061 #endif                          /* CONFIG_USB_DWC_OTG_LPM_ENABLE */
++01062 
++01068 void dwc_otg_attr_create (
++01069 #ifdef LM_INTERFACE
++01070         struct lm_device *dev
++01071 #elif  PCI_INTERFACE
++01072         struct pci_dev *dev
++01073 #endif
++01074         )
++01075 
++01076 {
++01077         int error;
++01078 
++01079         error = device_create_file(&dev->dev, &dev_attr_regoffset);
++01080         error = device_create_file(&dev->dev, &dev_attr_regvalue);
++01081         error = device_create_file(&dev->dev, &dev_attr_mode);
++01082         error = device_create_file(&dev->dev, &dev_attr_hnpcapable);
++01083         error = device_create_file(&dev->dev, &dev_attr_srpcapable);
++01084         error = device_create_file(&dev->dev, &dev_attr_hsic_connect);
++01085         error = device_create_file(&dev->dev, &dev_attr_inv_sel_hsic);
++01086         error = device_create_file(&dev->dev, &dev_attr_hnp);
++01087         error = device_create_file(&dev->dev, &dev_attr_srp);
++01088         error = device_create_file(&dev->dev, &dev_attr_buspower);
++01089         error = device_create_file(&dev->dev, &dev_attr_bussuspend);
++01090         error = device_create_file(&dev->dev, &dev_attr_busconnected);
++01091         error = device_create_file(&dev->dev, &dev_attr_gotgctl);
++01092         error = device_create_file(&dev->dev, &dev_attr_gusbcfg);
++01093         error = device_create_file(&dev->dev, &dev_attr_grxfsiz);
++01094         error = device_create_file(&dev->dev, &dev_attr_gnptxfsiz);
++01095         error = device_create_file(&dev->dev, &dev_attr_gpvndctl);
++01096         error = device_create_file(&dev->dev, &dev_attr_ggpio);
++01097         error = device_create_file(&dev->dev, &dev_attr_guid);
++01098         error = device_create_file(&dev->dev, &dev_attr_gsnpsid);
++01099         error = device_create_file(&dev->dev, &dev_attr_devspeed);
++01100         error = device_create_file(&dev->dev, &dev_attr_enumspeed);
++01101         error = device_create_file(&dev->dev, &dev_attr_hptxfsiz);
++01102         error = device_create_file(&dev->dev, &dev_attr_hprt0);
++01103         error = device_create_file(&dev->dev, &dev_attr_remote_wakeup);
++01104         error = device_create_file(&dev->dev, &dev_attr_regdump);
++01105         error = device_create_file(&dev->dev, &dev_attr_spramdump);
++01106         error = device_create_file(&dev->dev, &dev_attr_hcddump);
++01107         error = device_create_file(&dev->dev, &dev_attr_hcd_frrem);
++01108         error = device_create_file(&dev->dev, &dev_attr_rd_reg_test);
++01109         error = device_create_file(&dev->dev, &dev_attr_wr_reg_test);
++01110 #ifdef CONFIG_USB_DWC_OTG_LPM
++01111         error = device_create_file(&dev->dev, &dev_attr_lpm_response);
++01112         error = device_create_file(&dev->dev, &dev_attr_sleep_status);
++01113 #endif
++01114 }
++01115 
++01119 void dwc_otg_attr_remove (
++01120 #ifdef LM_INTERFACE
++01121         struct lm_device *dev
++01122 #elif  PCI_INTERFACE
++01123         struct pci_dev *dev
++01124 #endif
++01125        )
++01126 
++01127 {
++01128         device_remove_file(&dev->dev, &dev_attr_regoffset);
++01129         device_remove_file(&dev->dev, &dev_attr_regvalue);
++01130         device_remove_file(&dev->dev, &dev_attr_mode);
++01131         device_remove_file(&dev->dev, &dev_attr_hnpcapable);
++01132         device_remove_file(&dev->dev, &dev_attr_srpcapable);
++01133         device_remove_file(&dev->dev, &dev_attr_hsic_connect);
++01134         device_remove_file(&dev->dev, &dev_attr_inv_sel_hsic);
++01135         device_remove_file(&dev->dev, &dev_attr_hnp);
++01136         device_remove_file(&dev->dev, &dev_attr_srp);
++01137         device_remove_file(&dev->dev, &dev_attr_buspower);
++01138         device_remove_file(&dev->dev, &dev_attr_bussuspend);
++01139         device_remove_file(&dev->dev, &dev_attr_busconnected);
++01140         device_remove_file(&dev->dev, &dev_attr_gotgctl);
++01141         device_remove_file(&dev->dev, &dev_attr_gusbcfg);
++01142         device_remove_file(&dev->dev, &dev_attr_grxfsiz);
++01143         device_remove_file(&dev->dev, &dev_attr_gnptxfsiz);
++01144         device_remove_file(&dev->dev, &dev_attr_gpvndctl);
++01145         device_remove_file(&dev->dev, &dev_attr_ggpio);
++01146         device_remove_file(&dev->dev, &dev_attr_guid);
++01147         device_remove_file(&dev->dev, &dev_attr_gsnpsid);
++01148         device_remove_file(&dev->dev, &dev_attr_devspeed);
++01149         device_remove_file(&dev->dev, &dev_attr_enumspeed);
++01150         device_remove_file(&dev->dev, &dev_attr_hptxfsiz);
++01151         device_remove_file(&dev->dev, &dev_attr_hprt0);
++01152         device_remove_file(&dev->dev, &dev_attr_remote_wakeup);
++01153         device_remove_file(&dev->dev, &dev_attr_regdump);
++01154         device_remove_file(&dev->dev, &dev_attr_spramdump);
++01155         device_remove_file(&dev->dev, &dev_attr_hcddump);
++01156         device_remove_file(&dev->dev, &dev_attr_hcd_frrem);
++01157         device_remove_file(&dev->dev, &dev_attr_rd_reg_test);
++01158         device_remove_file(&dev->dev, &dev_attr_wr_reg_test);
++01159 #ifdef CONFIG_USB_DWC_OTG_LPM
++01160         device_remove_file(&dev->dev, &dev_attr_lpm_response);
++01161         device_remove_file(&dev->dev, &dev_attr_sleep_status);
++01162 #endif
++01163 }
++
Generated on Tue May 5 02:22:48 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__attr_8c.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__attr_8c.html 2013-07-26 19:31:20.000000000 +0000 +@@ -0,0 +1,485 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_attr.c File Reference ++ ++ ++ ++ ++
++
++
++
++

dwc_otg_attr.c File Reference

The diagnostic interface will provide access to the controller for bringing up the hardware and testing. More... ++

++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/moduleparam.h>
++#include <linux/init.h>
++#include <linux/device.h>
++#include <linux/errno.h>
++#include <linux/types.h>
++#include <linux/stat.h>
++#include <linux/version.h>
++#include <linux/param.h>
++#include <linux/delay.h>
++#include <linux/jiffies.h>
++#include <asm/io.h>
++#include "dwc_os.h"
++#include "dwc_otg_driver.h"
++#include "dwc_otg_attr.h"
++#include "dwc_otg_core_if.h"
++#include "dwc_otg_pcd_if.h"
++#include "dwc_otg_hcd_if.h"
++ ++

++Go to the source code of this file. ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++

Functions for Show/Store of Attributes

++#define RW_REG_COUNT   10000000
 Displays the time required to read the GNPTXFSIZ register many times (the output shows the number of times the register is read).
++#define MSEC_PER_JIFFIE   1000/HZ
++static ssize_t regoffset_show (struct device *_dev, struct device_attribute *attr, char *buf)
 Show the register offset of the Register Access.
++static ssize_t regoffset_store (struct device *_dev, struct device_attribute *attr, const char *buf, size_t count)
 Set the register offset for the next Register Access Read/Write.
++static ssize_t regvalue_show (struct device *_dev, struct device_attribute *attr, char *buf)
 Show the value of the register at the offset in the reg_offset attribute.
++static ssize_t regvalue_store (struct device *_dev, struct device_attribute *attr, const char *buf, size_t count)
 Store the value in the register at the offset in the reg_offset attribute.
++ DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW (mode,"Mode")
++static ssize_t hnp_store (struct device *_dev, struct device_attribute *attr, const char *buf, size_t count)
 Set the HNP Request bit.
++static ssize_t srp_show (struct device *_dev, struct device_attribute *attr, char *buf)
 Show the SRP status bit.
++static ssize_t srp_store (struct device *_dev, struct device_attribute *attr, const char *buf, size_t count)
 Set the SRP Request bit.
++static ssize_t buspower_show (struct device *_dev, struct device_attribute *attr, char *buf)
 Show the Bus Power status.
++static ssize_t buspower_store (struct device *_dev, struct device_attribute *attr, const char *buf, size_t count)
 Set the Bus Power status.
++static ssize_t bussuspend_show (struct device *_dev, struct device_attribute *attr, char *buf)
 Show the Bus Suspend status.
++static ssize_t bussuspend_store (struct device *_dev, struct device_attribute *attr, const char *buf, size_t count)
 Set the Bus Suspend status.
++static ssize_t remote_wakeup_show (struct device *_dev, struct device_attribute *attr, char *buf)
 Show the status of Remote Wakeup.
static ssize_t remote_wakeup_store (struct device *_dev, struct device_attribute *attr, const char *buf, size_t count)
 Initiate a remote wakeup of the host.
++static ssize_t regdump_show (struct device *_dev, struct device_attribute *attr, char *buf)
 Dump global registers and either host or device registers (depending on the current mode of the core).
++S_IRUGO static ssize_t spramdump_show (struct device *_dev, struct device_attribute *attr, char *buf)
 Dump global registers and either host or device registers (depending on the current mode of the core).
++S_IRUGO static ssize_t hcddump_show (struct device *_dev, struct device_attribute *attr, char *buf)
 Dump the current hcd state.
S_IRUGO static ssize_t hcd_frrem_show (struct device *_dev, struct device_attribute *attr, char *buf)
 Dump the average frame remaining at SOF.
++static ssize_t rd_reg_test_show (struct device *_dev, struct device_attribute *attr, char *buf)
++S_IRUGO static ssize_t wr_reg_test_show (struct device *_dev, struct device_attribute *attr, char *buf)
 Displays the time required to write the GNPTXFSIZ register many times (the output shows the number of times the register is written).
++ regoffset
++S_IRUGO S_IWUSR
++S_IRUGO regoffset_show
++S_IRUGO regoffset_store
++ regvalue
++S_IRUGO S_IWUSR
++S_IRUGO regvalue_show
++S_IRUGO regvalue_store
++ hnp
++ hnp_show
++ hnp_store
++ srp
++ srp_show
++ srp_store
++ buspower
++ buspower_show
++ buspower_store
++ bussuspend
++ bussuspend_show
++ bussuspend_store
++ remote_wakeup
++S_IRUGO S_IWUSR
++S_IRUGO remote_wakeup_show
++S_IRUGO remote_wakeup_store
++ regdump
++S_IRUGO S_IWUSR
++S_IRUGO regdump_show
++ spramdump
++S_IRUGO S_IWUSR
++S_IRUGO spramdump_show
++ hcddump
++S_IRUGO S_IWUSR
++S_IRUGO hcddump_show
++ hcd_frrem
++S_IRUGO S_IWUSR
++S_IRUGO hcd_frrem_show
++ rd_reg_test
++S_IRUGO S_IWUSR
++S_IRUGO rd_reg_test_show
++ wr_reg_test
++S_IRUGO S_IWUSR
++S_IRUGO wr_reg_test_show

Defines

#define DWC_OTG_DEVICE_ATTR_BITFIELD_RW(_otg_attr_name_, _string_)
#define DWC_OTG_DEVICE_ATTR_BITFIELD_RO(_otg_attr_name_, _string_)
#define DWC_OTG_DEVICE_ATTR_REG32_RW(_otg_attr_name_, _addr_, _string_)
#define DWC_OTG_DEVICE_ATTR_REG32_RO(_otg_attr_name_, _addr_, _string_)

Functions

++S_IRUGO void dwc_otg_attr_create ()
 Create the device files.
++void dwc_otg_attr_remove ()
 Remove the device files.
++

Detailed Description

++The diagnostic interface will provide access to the controller for bringing up the hardware and testing. ++

++The Linux driver attributes feature will be used to provide the Linux Diagnostic Interface. These attributes are accessed through sysfs. ++

++Definition in file dwc_otg_attr.c.

Define Documentation

++ ++
++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
#define DWC_OTG_DEVICE_ATTR_BITFIELD_RW (_otg_attr_name_,
_string_   ) 
++
++
++ ++

++Value:

DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_string_) \
++DWC_OTG_DEVICE_ATTR_BITFIELD_STORE(_otg_attr_name_,_string_) \
++DEVICE_ATTR(_otg_attr_name_,0644,_otg_attr_name_##_show,_otg_attr_name_##_store);
++
++

++Definition at line 405 of file dwc_otg_attr.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
#define DWC_OTG_DEVICE_ATTR_BITFIELD_RO (_otg_attr_name_,
_string_   ) 
++
++
++ ++

++Value:

DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_string_) \
++DEVICE_ATTR(_otg_attr_name_,0444,_otg_attr_name_##_show,NULL);
++
++

++Definition at line 410 of file dwc_otg_attr.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
#define DWC_OTG_DEVICE_ATTR_REG32_RW (_otg_attr_name_,
_addr_,
_string_   ) 
++
++
++ ++

++Value:

DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_string_) \
++DWC_OTG_DEVICE_ATTR_REG_STORE(_otg_attr_name_,_string_) \
++DEVICE_ATTR(_otg_attr_name_,0644,_otg_attr_name_##_show,_otg_attr_name_##_store);
++
++

++Definition at line 414 of file dwc_otg_attr.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
#define DWC_OTG_DEVICE_ATTR_REG32_RO (_otg_attr_name_,
_addr_,
_string_   ) 
++
++
++ ++

++Value:

DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_string_) \
++DEVICE_ATTR(_otg_attr_name_,0444,_otg_attr_name_##_show,NULL);
++
++

++Definition at line 419 of file dwc_otg_attr.c. ++

++

++

Function Documentation

++ ++
++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
static ssize_t remote_wakeup_store (struct device *  _dev,
struct device_attribute *  attr,
const char *  buf,
size_t  count 
) [static]
++
++
++ ++

++Initiate a remote wakeup of the host. ++

++The Device control register Remote Wakeup Signal bit is written if the PCD Remote wakeup enable flag is set. ++

++Definition at line 773 of file dwc_otg_attr.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
S_IRUGO static ssize_t hcd_frrem_show (struct device *  _dev,
struct device_attribute *  attr,
char *  buf 
) [static]
++
++
++ ++

++Dump the average frame remaining at SOF. ++

++This can be used to determine average interrupt latency. Frame remaining is also shown for start transfer and two additional sample points. ++

++Definition at line 872 of file dwc_otg_attr.c. ++

++

++

Generated on Tue May 5 02:22:48 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__attr_8h-source.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__attr_8h-source.html 2013-07-26 19:31:20.000000000 +0000 +@@ -0,0 +1,105 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_attr.h Source File ++ ++ ++ ++ ++
++
++
++
++

dwc_otg_attr.h

Go to the documentation of this file.
00001 /* ==========================================================================
++00002  * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_attr.h $
++00003  * $Revision: #11 $
++00004  * $Date: 2009/04/03 $
++00005  * $Change: 1225160 $
++00006  *
++00007  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
++00008  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
++00009  * otherwise expressly agreed to in writing between Synopsys and you.
++00010  * 
++00011  * The Software IS NOT an item of Licensed Software or Licensed Product under
++00012  * any End User Software License Agreement or Agreement for Licensed Product
++00013  * with Synopsys or any supplement thereto. You are permitted to use and
++00014  * redistribute this Software in source and binary forms, with or without
++00015  * modification, provided that redistributions of source code must retain this
++00016  * notice. You may not view, use, disclose, copy or distribute this file or
++00017  * any information contained herein except pursuant to this license grant from
++00018  * Synopsys. If you do not agree with this notice, including the disclaimer
++00019  * below, then you are not authorized to use the Software.
++00020  * 
++00021  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
++00022  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++00023  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++00024  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
++00025  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++00026  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
++00027  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
++00028  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
++00029  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
++00030  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
++00031  * DAMAGE.
++00032  * ========================================================================== */
++00033 
++00034 #if !defined(__DWC_OTG_ATTR_H__)
++00035 #define __DWC_OTG_ATTR_H__
++00036 
++00040 extern struct device_attribute dev_attr_regoffset;
++00041 extern struct device_attribute dev_attr_regvalue;
++00042 
++00043 extern struct device_attribute dev_attr_mode;
++00044 extern struct device_attribute dev_attr_hnpcapable;
++00045 extern struct device_attribute dev_attr_srpcapable;
++00046 extern struct device_attribute dev_attr_hnp;
++00047 extern struct device_attribute dev_attr_srp;
++00048 extern struct device_attribute dev_attr_buspower;
++00049 extern struct device_attribute dev_attr_bussuspend;
++00050 extern struct device_attribute dev_attr_busconnected;
++00051 extern struct device_attribute dev_attr_gotgctl;
++00052 extern struct device_attribute dev_attr_gusbcfg;
++00053 extern struct device_attribute dev_attr_grxfsiz;
++00054 extern struct device_attribute dev_attr_gnptxfsiz;
++00055 extern struct device_attribute dev_attr_gpvndctl;
++00056 extern struct device_attribute dev_attr_ggpio;
++00057 extern struct device_attribute dev_attr_guid;
++00058 extern struct device_attribute dev_attr_gsnpsid;
++00059 extern struct device_attribute dev_attr_devspeed;
++00060 extern struct device_attribute dev_attr_enumspeed;
++00061 extern struct device_attribute dev_attr_hptxfsiz;
++00062 extern struct device_attribute dev_attr_hprt0;
++00063 #ifdef CONFIG_USB_DWC_OTG_LPM
++00064 extern struct device_attribute dev_attr_lpm_response;
++00065 extern struct device_attribute dev_attr_sleep_local_dev;
++00066 extern struct device_attribute devi_attr_sleep_status;
++00067 #endif
++00068 
++00069 void dwc_otg_attr_create (
++00070 #ifdef LM_INTERFACE
++00071         struct lm_device *dev
++00072 #elif  PCI_INTERFACE
++00073         struct pci_dev *dev
++00074 #endif
++00075         );
++00076 
++00077 void dwc_otg_attr_remove (
++00078 #ifdef LM_INTERFACE
++00079         struct lm_device *dev
++00080 #elif  PCI_INTERFACE
++00081         struct pci_dev *dev
++00082 #endif
++00083         );
++00084 #endif
++
Generated on Tue May 5 02:22:48 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__attr_8h.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__attr_8h.html 2013-07-26 19:31:20.000000000 +0000 +@@ -0,0 +1,116 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_attr.h File Reference ++ ++ ++ ++ ++
++
++
++
++

dwc_otg_attr.h File Reference

This file contains the interface to the Linux device attributes. More... ++

++ ++

++Go to the source code of this file. ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++

Defines

++#define __DWC_OTG_ATTR_H__

Functions

++void dwc_otg_attr_create ()
 Create the device files.
++void dwc_otg_attr_remove ()
 Remove the device files.

Variables

++device_attribute dev_attr_regoffset
++device_attribute dev_attr_regvalue
++device_attribute dev_attr_mode
++device_attribute dev_attr_hnpcapable
++device_attribute dev_attr_srpcapable
++device_attribute dev_attr_hnp
++device_attribute dev_attr_srp
++device_attribute dev_attr_buspower
++device_attribute dev_attr_bussuspend
++device_attribute dev_attr_busconnected
++device_attribute dev_attr_gotgctl
++device_attribute dev_attr_gusbcfg
++device_attribute dev_attr_grxfsiz
++device_attribute dev_attr_gnptxfsiz
++device_attribute dev_attr_gpvndctl
++device_attribute dev_attr_ggpio
++device_attribute dev_attr_guid
++device_attribute dev_attr_gsnpsid
++device_attribute dev_attr_devspeed
++device_attribute dev_attr_enumspeed
++device_attribute dev_attr_hptxfsiz
++device_attribute dev_attr_hprt0
++

Detailed Description

++This file contains the interface to the Linux device attributes. ++

++ ++

++Definition in file dwc_otg_attr.h.

Generated on Tue May 5 02:22:48 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__cfi_8c-source.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__cfi_8c-source.html 2013-07-26 19:31:20.000000000 +0000 +@@ -0,0 +1,1724 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_cfi.c Source File ++ ++ ++ ++ ++
++
++
++
++

dwc_otg_cfi.c

Go to the documentation of this file.
00001 /* ==========================================================================
++00002  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
++00003  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
++00004  * otherwise expressly agreed to in writing between Synopsys and you.
++00005  * 
++00006  * The Software IS NOT an item of Licensed Software or Licensed Product under
++00007  * any End User Software License Agreement or Agreement for Licensed Product
++00008  * with Synopsys or any supplement thereto. You are permitted to use and
++00009  * redistribute this Software in source and binary forms, with or without
++00010  * modification, provided that redistributions of source code must retain this
++00011  * notice. You may not view, use, disclose, copy or distribute this file or
++00012  * any information contained herein except pursuant to this license grant from
++00013  * Synopsys. If you do not agree with this notice, including the disclaimer
++00014  * below, then you are not authorized to use the Software.
++00015  * 
++00016  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
++00017  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++00018  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++00019  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
++00020  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++00021  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
++00022  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
++00023  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
++00024  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
++00025  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
++00026  * DAMAGE.
++00027  * ========================================================================== */
++00028 
++00034 #ifdef DWC_UTE_CFI
++00035 
++00036 #include "dwc_otg_pcd.h"
++00037 #include "dwc_otg_cfi.h"
++00038 
++00040 #define DWC_CONSTANT_CPU_TO_LE16(x) (x)
++00041 
++00042 extern dwc_otg_pcd_ep_t *get_ep_by_addr(dwc_otg_pcd_t * pcd, u16 wIndex);
++00043 
++00044 static int cfi_core_features_buf(uint8_t * buf, uint16_t buflen);
++00045 static int cfi_get_feature_value(uint8_t * buf, uint16_t buflen,
++00046                                  struct dwc_otg_pcd *pcd,
++00047                                  struct cfi_usb_ctrlrequest *ctrl_req);
++00048 static int cfi_set_feature_value(struct dwc_otg_pcd *pcd);
++00049 static int cfi_ep_get_sg_val(uint8_t * buf, struct dwc_otg_pcd *pcd,
++00050                              struct cfi_usb_ctrlrequest *req);
++00051 static int cfi_ep_get_concat_val(uint8_t * buf, struct dwc_otg_pcd *pcd,
++00052                                  struct cfi_usb_ctrlrequest *req);
++00053 static int cfi_ep_get_align_val(uint8_t * buf, struct dwc_otg_pcd *pcd,
++00054                                 struct cfi_usb_ctrlrequest *req);
++00055 static int cfi_preproc_reset(struct dwc_otg_pcd *pcd,
++00056                              struct cfi_usb_ctrlrequest *req);
++00057 static void cfi_free_ep_bs_dyn_data(cfi_ep_t * cfiep);
++00058 
++00059 static uint16_t get_dfifo_size(dwc_otg_core_if_t * core_if);
++00060 static int32_t get_rxfifo_size(dwc_otg_core_if_t * core_if, uint16_t wValue);
++00061 static int32_t get_txfifo_size(struct dwc_otg_pcd *pcd, uint16_t wValue);
++00062 
++00063 static uint8_t resize_fifos(dwc_otg_core_if_t * core_if);
++00064 
++00066 static cfi_all_features_header_t all_props_desc_header = {
++00067         .wVersion = DWC_CONSTANT_CPU_TO_LE16(0x100),
++00068         .wCoreID = DWC_CONSTANT_CPU_TO_LE16(CFI_CORE_ID_OTG),
++00069         .wNumFeatures = DWC_CONSTANT_CPU_TO_LE16(9),
++00070 };
++00071 
++00073 static cfi_feature_desc_header_t prop_descs[] = {
++00074 
++00075         /* FT_ID_DMA_MODE */
++00076         {
++00077          .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_DMA_MODE),
++00078          .bmAttributes = CFI_FEATURE_ATTR_RW,
++00079          .wDataLength = DWC_CONSTANT_CPU_TO_LE16(1),
++00080          },
++00081 
++00082         /* FT_ID_DMA_BUFFER_SETUP */
++00083         {
++00084          .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_DMA_BUFFER_SETUP),
++00085          .bmAttributes = CFI_FEATURE_ATTR_RW,
++00086          .wDataLength = DWC_CONSTANT_CPU_TO_LE16(6),
++00087          },
++00088 
++00089         /* FT_ID_DMA_BUFF_ALIGN */
++00090         {
++00091          .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_DMA_BUFF_ALIGN),
++00092          .bmAttributes = CFI_FEATURE_ATTR_RW,
++00093          .wDataLength = DWC_CONSTANT_CPU_TO_LE16(2),
++00094          },
++00095 
++00096         /* FT_ID_DMA_CONCAT_SETUP */
++00097         {
++00098          .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_DMA_CONCAT_SETUP),
++00099          .bmAttributes = CFI_FEATURE_ATTR_RW,
++00100          //.wDataLength  = DWC_CONSTANT_CPU_TO_LE16(6),
++00101          },
++00102 
++00103         /* FT_ID_DMA_CIRCULAR */
++00104         {
++00105          .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_DMA_CIRCULAR),
++00106          .bmAttributes = CFI_FEATURE_ATTR_RW,
++00107          .wDataLength = DWC_CONSTANT_CPU_TO_LE16(6),
++00108          },
++00109 
++00110         /* FT_ID_THRESHOLD_SETUP */
++00111         {
++00112          .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_THRESHOLD_SETUP),
++00113          .bmAttributes = CFI_FEATURE_ATTR_RW,
++00114          .wDataLength = DWC_CONSTANT_CPU_TO_LE16(6),
++00115          },
++00116 
++00117         /* FT_ID_DFIFO_DEPTH */
++00118         {
++00119          .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_DFIFO_DEPTH),
++00120          .bmAttributes = CFI_FEATURE_ATTR_RO,
++00121          .wDataLength = DWC_CONSTANT_CPU_TO_LE16(2),
++00122          },
++00123 
++00124         /* FT_ID_TX_FIFO_DEPTH */
++00125         {
++00126          .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_TX_FIFO_DEPTH),
++00127          .bmAttributes = CFI_FEATURE_ATTR_RW,
++00128          .wDataLength = DWC_CONSTANT_CPU_TO_LE16(2),
++00129          },
++00130 
++00131         /* FT_ID_RX_FIFO_DEPTH */
++00132         {
++00133          .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_RX_FIFO_DEPTH),
++00134          .bmAttributes = CFI_FEATURE_ATTR_RW,
++00135          .wDataLength = DWC_CONSTANT_CPU_TO_LE16(2),
++00136          }
++00137 };
++00138 
++00140 cfi_string_t prop_name_table[] = {
++00141         {FT_ID_DMA_MODE, "dma_mode"},
++00142         {FT_ID_DMA_BUFFER_SETUP, "buffer_setup"},
++00143         {FT_ID_DMA_BUFF_ALIGN, "buffer_align"},
++00144         {FT_ID_DMA_CONCAT_SETUP, "concat_setup"},
++00145         {FT_ID_DMA_CIRCULAR, "buffer_circular"},
++00146         {FT_ID_THRESHOLD_SETUP, "threshold_setup"},
++00147         {FT_ID_DFIFO_DEPTH, "dfifo_depth"},
++00148         {FT_ID_TX_FIFO_DEPTH, "txfifo_depth"},
++00149         {FT_ID_RX_FIFO_DEPTH, "rxfifo_depth"},
++00150         {}
++00151 };
++00152 
++00153 /************************************************************************/
++00154 
++00160 const uint8_t *get_prop_name(uint16_t prop_id, int *len)
++00161 {
++00162         cfi_string_t *pstr;
++00163         *len = 0;
++00164 
++00165         for (pstr = prop_name_table; pstr && pstr->s; pstr++) {
++00166                 if (pstr->id == prop_id) {
++00167                         *len = DWC_STRLEN(pstr->s);
++00168                         return pstr->s;
++00169                 }
++00170         }
++00171         return NULL;
++00172 }
++00173 
++00179 int cfi_setup(struct dwc_otg_pcd *pcd, struct cfi_usb_ctrlrequest *ctrl)
++00180 {
++00181         int retval = 0;
++00182         dwc_otg_pcd_ep_t *ep = NULL;
++00183         cfiobject_t *cfi = pcd->cfi;
++00184         struct dwc_otg_core_if *coreif = GET_CORE_IF(pcd);
++00185         uint16_t wLen = DWC_LE16_TO_CPU(&ctrl->wLength);
++00186         uint16_t wValue = DWC_LE16_TO_CPU(&ctrl->wValue);
++00187         uint16_t wIndex = DWC_LE16_TO_CPU(&ctrl->wIndex);
++00188         uint32_t regaddr = 0;
++00189         uint32_t regval = 0;
++00190 
++00191         /* Save this Control Request in the CFI object. 
++00192          * The data field will be assigned in the data stage completion CB function.
++00193          */
++00194         cfi->ctrl_req = *ctrl;
++00195         cfi->ctrl_req.data = NULL;
++00196 
++00197         cfi->need_gadget_att = 0;
++00198         cfi->need_status_in_complete = 0;
++00199 
++00200         switch (ctrl->bRequest) {
++00201         case VEN_CORE_GET_FEATURES:
++00202                 retval = cfi_core_features_buf(cfi->buf_in.buf, CFI_IN_BUF_LEN);
++00203                 if (retval >= 0) {
++00204                         //dump_msg(cfi->buf_in.buf, retval);
++00205                         ep = &pcd->ep0;
++00206 
++00207                         retval = min((uint16_t) retval, wLen);
++00208                         /* Transfer this buffer to the host through the EP0-IN EP */
++00209                         ep->dwc_ep.dma_addr = cfi->buf_in.addr;
++00210                         ep->dwc_ep.start_xfer_buff = cfi->buf_in.buf;
++00211                         ep->dwc_ep.xfer_buff = cfi->buf_in.buf;
++00212                         ep->dwc_ep.xfer_len = retval;
++00213                         ep->dwc_ep.xfer_count = 0;
++00214                         ep->dwc_ep.sent_zlp = 0;
++00215                         ep->dwc_ep.total_len = ep->dwc_ep.xfer_len;
++00216 
++00217                         pcd->ep0_pending = 1;
++00218                         dwc_otg_ep0_start_transfer(coreif, &ep->dwc_ep);
++00219                 }
++00220                 retval = 0;
++00221                 break;
++00222 
++00223         case VEN_CORE_GET_FEATURE:
++00224                 CFI_INFO("VEN_CORE_GET_FEATURE\n");
++00225                 retval = cfi_get_feature_value(cfi->buf_in.buf, CFI_IN_BUF_LEN,
++00226                                                pcd, ctrl);
++00227                 if (retval >= 0) {
++00228                         ep = &pcd->ep0;
++00229 
++00230                         retval = min((uint16_t) retval, wLen);
++00231                         /* Transfer this buffer to the host through the EP0-IN EP */
++00232                         ep->dwc_ep.dma_addr = cfi->buf_in.addr;
++00233                         ep->dwc_ep.start_xfer_buff = cfi->buf_in.buf;
++00234                         ep->dwc_ep.xfer_buff = cfi->buf_in.buf;
++00235                         ep->dwc_ep.xfer_len = retval;
++00236                         ep->dwc_ep.xfer_count = 0;
++00237                         ep->dwc_ep.sent_zlp = 0;
++00238                         ep->dwc_ep.total_len = ep->dwc_ep.xfer_len;
++00239 
++00240                         pcd->ep0_pending = 1;
++00241                         dwc_otg_ep0_start_transfer(coreif, &ep->dwc_ep);
++00242                 }
++00243                 CFI_INFO("VEN_CORE_GET_FEATURE=%d\n", retval);
++00244                 dump_msg(cfi->buf_in.buf, retval);
++00245                 break;
++00246 
++00247         case VEN_CORE_SET_FEATURE:
++00248                 CFI_INFO("VEN_CORE_SET_FEATURE\n");
++00249                 /* Set up an XFER to get the data stage of the control request,
++00250                  * which is the new value of the feature to be modified.
++00251                  */
++00252                 ep = &pcd->ep0;
++00253                 ep->dwc_ep.is_in = 0;
++00254                 ep->dwc_ep.dma_addr = cfi->buf_out.addr;
++00255                 ep->dwc_ep.start_xfer_buff = cfi->buf_out.buf;
++00256                 ep->dwc_ep.xfer_buff = cfi->buf_out.buf;
++00257                 ep->dwc_ep.xfer_len = wLen;
++00258                 ep->dwc_ep.xfer_count = 0;
++00259                 ep->dwc_ep.sent_zlp = 0;
++00260                 ep->dwc_ep.total_len = ep->dwc_ep.xfer_len;
++00261 
++00262                 pcd->ep0_pending = 1;
++00263                 /* Read the control write's data stage */
++00264                 dwc_otg_ep0_start_transfer(coreif, &ep->dwc_ep);
++00265                 retval = 0;
++00266                 break;
++00267 
++00268         case VEN_CORE_RESET_FEATURES:
++00269                 CFI_INFO("VEN_CORE_RESET_FEATURES\n");
++00270                 cfi->need_gadget_att = 1;
++00271                 cfi->need_status_in_complete = 1;
++00272                 retval = cfi_preproc_reset(pcd, ctrl);
++00273                 CFI_INFO("VEN_CORE_RESET_FEATURES = (%d)\n", retval);
++00274                 break;
++00275 
++00276         case VEN_CORE_ACTIVATE_FEATURES:
++00277                 CFI_INFO("VEN_CORE_ACTIVATE_FEATURES\n");
++00278                 break;
++00279 
++00280         case VEN_CORE_READ_REGISTER:
++00281                 CFI_INFO("VEN_CORE_READ_REGISTER\n");
++00282                 /* wValue optionally contains the HI WORD of the register offset and
++00283                  * wIndex contains the LOW WORD of the register offset 
++00284                  */
++00285                 if (wValue == 0) {
++00286                         /* @TODO - MAS - fix the access to the base field */
++00287                         regaddr = 0;
++00288                         //regaddr = (uint32_t) pcd->otg_dev->base;
++00289                         //GET_CORE_IF(pcd)->co
++00290                         regaddr |= wIndex;
++00291                 } else {
++00292                         regaddr = (wValue << 16) | wIndex;
++00293                 }
++00294 
++00295                 /* Read a 32-bit value of the memory at the regaddr */
++00296                 regval = dwc_read_reg32((uint32_t *) regaddr);
++00297 
++00298                 ep = &pcd->ep0;
++00299                 dwc_memcpy(cfi->buf_in.buf, &regval, sizeof(uint32_t));
++00300                 ep->dwc_ep.is_in = 1;
++00301                 ep->dwc_ep.dma_addr = cfi->buf_in.addr;
++00302                 ep->dwc_ep.start_xfer_buff = cfi->buf_in.buf;
++00303                 ep->dwc_ep.xfer_buff = cfi->buf_in.buf;
++00304                 ep->dwc_ep.xfer_len = wLen;
++00305                 ep->dwc_ep.xfer_count = 0;
++00306                 ep->dwc_ep.sent_zlp = 0;
++00307                 ep->dwc_ep.total_len = ep->dwc_ep.xfer_len;
++00308 
++00309                 pcd->ep0_pending = 1;
++00310                 dwc_otg_ep0_start_transfer(coreif, &ep->dwc_ep);
++00311                 cfi->need_gadget_att = 0;
++00312                 retval = 0;
++00313                 break;
++00314 
++00315         case VEN_CORE_WRITE_REGISTER:
++00316                 CFI_INFO("VEN_CORE_WRITE_REGISTER\n");
++00317                 /* Set up an XFER to get the data stage of the control request,
++00318                  * which is the new value of the register to be modified.
++00319                  */
++00320                 ep = &pcd->ep0;
++00321                 ep->dwc_ep.is_in = 0;
++00322                 ep->dwc_ep.dma_addr = cfi->buf_out.addr;
++00323                 ep->dwc_ep.start_xfer_buff = cfi->buf_out.buf;
++00324                 ep->dwc_ep.xfer_buff = cfi->buf_out.buf;
++00325                 ep->dwc_ep.xfer_len = wLen;
++00326                 ep->dwc_ep.xfer_count = 0;
++00327                 ep->dwc_ep.sent_zlp = 0;
++00328                 ep->dwc_ep.total_len = ep->dwc_ep.xfer_len;
++00329 
++00330                 pcd->ep0_pending = 1;
++00331                 /* Read the control write's data stage */
++00332                 dwc_otg_ep0_start_transfer(coreif, &ep->dwc_ep);
++00333                 retval = 0;
++00334                 break;
++00335 
++00336         default:
++00337                 retval = -DWC_E_NOT_SUPPORTED;
++00338                 break;
++00339         }
++00340 
++00341         return retval;
++00342 }
++00343 
++00355 static int cfi_core_features_buf(uint8_t * buf, uint16_t buflen)
++00356 {
++00357         cfi_feature_desc_header_t *prop_hdr = prop_descs;
++00358         cfi_feature_desc_header_t *prop;
++00359         cfi_all_features_header_t *all_props_hdr = &all_props_desc_header;
++00360         cfi_all_features_header_t *tmp;
++00361         uint8_t *tmpbuf = buf;
++00362         const uint8_t *pname = NULL;
++00363         int i, j, namelen = 0, totlen;
++00364 
++00365         /* Prepare and copy the core features into the buffer */
++00366         CFI_INFO("%s:\n", __func__);
++00367 
++00368         tmp = (cfi_all_features_header_t *) tmpbuf;
++00369         *tmp = *all_props_hdr;
++00370         tmpbuf += CFI_ALL_FEATURES_HDR_LEN;
++00371 
++00372         j = sizeof(prop_descs) / sizeof(cfi_all_features_header_t);
++00373         for (i = 0; i < j; i++, prop_hdr++) {
++00374                 pname = get_prop_name(prop_hdr->wFeatureID, &namelen);
++00375                 prop = (cfi_feature_desc_header_t *) tmpbuf;
++00376                 *prop = *prop_hdr;
++00377 
++00378                 prop->bNameLen = namelen;
++00379                 prop->wLength =
++00380                     DWC_CONSTANT_CPU_TO_LE16(CFI_FEATURE_DESC_HDR_LEN +
++00381                                              namelen);
++00382 
++00383                 tmpbuf += CFI_FEATURE_DESC_HDR_LEN;
++00384                 dwc_memcpy(tmpbuf, pname, namelen);
++00385                 tmpbuf += namelen;
++00386         }
++00387 
++00388         totlen = tmpbuf - buf;
++00389 
++00390         if (totlen > 0) {
++00391                 tmp = (cfi_all_features_header_t *) buf;
++00392                 tmp->wTotalLen = DWC_CONSTANT_CPU_TO_LE16(totlen);
++00393         }
++00394 
++00395         return totlen;
++00396 }
++00397 
++00401 static void cfi_release(cfiobject_t * cfiobj)
++00402 {
++00403         cfi_ep_t *cfiep;
++00404         dwc_list_link_t *tmp;
++00405 
++00406         CFI_INFO("%s\n", __func__);
++00407 
++00408         if (cfiobj->buf_in.buf) {
++00409                 dwc_dma_free(CFI_IN_BUF_LEN, cfiobj->buf_in.buf,
++00410                              cfiobj->buf_in.addr);
++00411                 cfiobj->buf_in.buf = NULL;
++00412         }
++00413 
++00414         if (cfiobj->buf_out.buf) {
++00415                 dwc_dma_free(CFI_OUT_BUF_LEN, cfiobj->buf_out.buf,
++00416                              cfiobj->buf_out.addr);
++00417                 cfiobj->buf_out.buf = NULL;
++00418         }
++00419 
++00420         /* Free the Buffer Setup values for each EP */
++00421         //list_for_each_entry(cfiep, &cfiobj->active_eps, lh) {
++00422         DWC_LIST_FOREACH(tmp, &cfiobj->active_eps) {
++00423                 cfiep = DWC_LIST_ENTRY(tmp, struct cfi_ep, lh);
++00424                 cfi_free_ep_bs_dyn_data(cfiep);
++00425         }
++00426 }
++00427 
++00431 static void cfi_free_ep_bs_dyn_data(cfi_ep_t * cfiep)
++00432 {
++00433         if (cfiep->bm_sg) {
++00434                 dwc_free(cfiep->bm_sg);
++00435                 cfiep->bm_sg = NULL;
++00436         }
++00437 
++00438         if (cfiep->bm_align) {
++00439                 dwc_free(cfiep->bm_align);
++00440                 cfiep->bm_align = NULL;
++00441         }
++00442 
++00443         if (cfiep->bm_concat) {
++00444                 if (NULL != cfiep->bm_concat->wTxBytes) {
++00445                         dwc_free(cfiep->bm_concat->wTxBytes);
++00446                         cfiep->bm_concat->wTxBytes = NULL;
++00447                 }
++00448                 dwc_free(cfiep->bm_concat);
++00449                 cfiep->bm_concat = NULL;
++00450         }
++00451 }
++00452 
++00458 static int cfi_ep_init_defaults(struct dwc_otg_pcd *pcd, cfi_ep_t * cfiep)
++00459 {
++00460         int retval = 0;
++00461 
++00462         cfiep->bm_sg = dwc_alloc(sizeof(ddma_sg_buffer_setup_t));
++00463         if (NULL == cfiep->bm_sg) {
++00464                 CFI_INFO("Failed to allocate memory for SG feature value\n");
++00465                 return -DWC_E_NO_MEMORY;
++00466         }
++00467         dwc_memset(cfiep->bm_sg, 0, sizeof(ddma_sg_buffer_setup_t));
++00468 
++00469         /* For the Concatenation feature's default value we do not allocate
++00470          * memory for the wTxBytes field - it will be done in the set_feature_value
++00471          * request handler.
++00472          */
++00473         cfiep->bm_concat = dwc_alloc(sizeof(ddma_concat_buffer_setup_t));
++00474         if (NULL == cfiep->bm_concat) {
++00475                 CFI_INFO
++00476                     ("Failed to allocate memory for CONCATENATION feature value\n");
++00477                 dwc_free(cfiep->bm_sg);
++00478                 return -DWC_E_NO_MEMORY;
++00479         }
++00480         dwc_memset(cfiep->bm_concat, 0, sizeof(ddma_concat_buffer_setup_t));
++00481 
++00482         cfiep->bm_align = dwc_alloc(sizeof(ddma_align_buffer_setup_t));
++00483         if (NULL == cfiep->bm_align) {
++00484                 CFI_INFO
++00485                     ("Failed to allocate memory for Alignment feature value\n");
++00486                 dwc_free(cfiep->bm_sg);
++00487                 dwc_free(cfiep->bm_concat);
++00488                 return -DWC_E_NO_MEMORY;
++00489         }
++00490         dwc_memset(cfiep->bm_align, 0, sizeof(ddma_align_buffer_setup_t));
++00491 
++00492         return retval;
++00493 }
++00494 
++00506 static int cfi_ep_enable(struct cfiobject *cfi, struct dwc_otg_pcd *pcd,
++00507                          struct dwc_otg_pcd_ep *ep)
++00508 {
++00509         cfi_ep_t *cfiep;
++00510         int retval = -DWC_E_NOT_SUPPORTED;
++00511 
++00512         CFI_INFO("%s: epname=%s; epnum=0x%02x\n", __func__,
++00513                  "EP_" /*ep->ep.name */ , ep->desc->bEndpointAddress);
++00514         /* MAS - Check whether this endpoint already is in the list */
++00515         cfiep = get_cfi_ep_by_pcd_ep(cfi, ep);
++00516 
++00517         if (NULL == cfiep) {
++00518                 /* Allocate a cfi_ep_t object */
++00519                 cfiep = dwc_alloc(sizeof(cfi_ep_t));
++00520                 if (NULL == cfiep) {
++00521                         CFI_INFO
++00522                             ("Unable to allocate memory for <cfiep> in function %s\n",
++00523                              __func__);
++00524                         return -DWC_E_NO_MEMORY;
++00525                 }
++00526                 dwc_memset(cfiep, 0, sizeof(cfi_ep_t));
++00527 
++00528                 /* Save the dwc_otg_pcd_ep pointer in the cfiep object */
++00529                 cfiep->ep = ep;
++00530 
++00531                 /* Allocate the DMA Descriptors chain of MAX_DMA_DESCS_PER_EP count */
++00532                 ep->dwc_ep.descs =
++00533                     dwc_dma_alloc(MAX_DMA_DESCS_PER_EP *
++00534                                   sizeof(dwc_otg_dma_desc_t),
++00535                                   &ep->dwc_ep.descs_dma_addr);
++00536 
++00537                 if (NULL == ep->dwc_ep.descs) {
++00538                         dwc_free(cfiep);
++00539                         return -DWC_E_NO_MEMORY;
++00540                 }
++00541 
++00542                 DWC_LIST_INIT(&cfiep->lh);
++00543 
++00544                 /* Set the buffer mode to BM_STANDARD. It will be modified 
++00545                  * when building descriptors for a specific buffer mode */
++00546                 ep->dwc_ep.buff_mode = BM_STANDARD;
++00547 
++00548                 /* Create and initialize the default values for this EP's Buffer modes */
++00549                 if ((retval = cfi_ep_init_defaults(pcd, cfiep)) < 0)
++00550                         return retval;
++00551 
++00552                 /* Add the cfi_ep_t object to the CFI object's list of active endpoints */
++00553                 DWC_LIST_INSERT_TAIL(&cfi->active_eps, &cfiep->lh);
++00554                 retval = 0;
++00555         } else {                /* The sought EP already is in the list */
++00556                 CFI_INFO("%s: The sought EP already is in the list\n",
++00557                          __func__);
++00558         }
++00559 
++00560         return retval;
++00561 }
++00562 
++00568 static int cfi_ctrl_write_complete(struct cfiobject *cfi,
++00569                                    struct dwc_otg_pcd *pcd)
++00570 {
++00571         uint32_t addr, reg_value;
++00572         uint16_t wIndex, wValue;
++00573         uint8_t bRequest;
++00574         uint8_t *buf = cfi->buf_out.buf;
++00575         //struct usb_ctrlrequest *ctrl_req = &cfi->ctrl_req_saved;
++00576         struct cfi_usb_ctrlrequest *ctrl_req = &cfi->ctrl_req;
++00577         int retval = -DWC_E_NOT_SUPPORTED;
++00578 
++00579         CFI_INFO("%s\n", __func__);
++00580 
++00581         bRequest = ctrl_req->bRequest;
++00582         wIndex = DWC_CONSTANT_CPU_TO_LE16(ctrl_req->wIndex);
++00583         wValue = DWC_CONSTANT_CPU_TO_LE16(ctrl_req->wValue);
++00584 
++00585         /* 
++00586          * Save the pointer to the data stage in the ctrl_req's <data> field.
++00587          * The request should be already saved in the command stage by now.
++00588          */
++00589         ctrl_req->data = cfi->buf_out.buf;
++00590         cfi->need_status_in_complete = 0;
++00591         cfi->need_gadget_att = 0;
++00592 
++00593         switch (bRequest) {
++00594         case VEN_CORE_WRITE_REGISTER:
++00595                 /* The buffer contains raw data of the new value for the register */
++00596                 reg_value = *((uint32_t *) buf);
++00597                 if (wValue == 0) {
++00598                         addr = 0;
++00599                         //addr = (uint32_t) pcd->otg_dev->base;
++00600                         addr += wIndex;
++00601                 } else {
++00602                         addr = (wValue << 16) | wIndex;
++00603                 }
++00604 
++00605                 //writel(reg_value, addr);
++00606 
++00607                 retval = 0;
++00608                 cfi->need_status_in_complete = 1;
++00609                 break;
++00610 
++00611         case VEN_CORE_SET_FEATURE:
++00612                 /* The buffer contains raw data of the new value of the feature */
++00613                 retval = cfi_set_feature_value(pcd);
++00614                 if (retval < 0)
++00615                         return retval;
++00616 
++00617                 cfi->need_status_in_complete = 1;
++00618                 break;
++00619 
++00620         default:
++00621                 break;
++00622         }
++00623 
++00624         return retval;
++00625 }
++00626 
++00630 static void cfi_build_sg_descs(struct cfiobject *cfi, cfi_ep_t * cfiep,
++00631                                dwc_otg_pcd_request_t * req)
++00632 {
++00633         struct dwc_otg_pcd_ep *ep = cfiep->ep;
++00634         ddma_sg_buffer_setup_t *sgval = cfiep->bm_sg;
++00635         struct dwc_otg_dma_desc *desc = cfiep->ep->dwc_ep.descs;
++00636         struct dwc_otg_dma_desc *desc_last = cfiep->ep->dwc_ep.descs;
++00637         dma_addr_t buff_addr = req->dma;
++00638         int i;
++00639         uint32_t txsize, off;
++00640 
++00641         txsize = sgval->wSize;
++00642         off = sgval->bOffset;
++00643 
++00644 //      CFI_INFO("%s: %s TXSIZE=0x%08x; OFFSET=0x%08x\n", 
++00645 //              __func__, cfiep->ep->ep.name, txsize, off);
++00646 
++00647         for (i = 0; i < sgval->bCount; i++) {
++00648                 desc->status.b.bs = BS_HOST_BUSY;
++00649                 desc->buf = buff_addr;
++00650                 desc->status.b.l = 0;
++00651                 desc->status.b.ioc = 0;
++00652                 desc->status.b.sp = 0;
++00653                 desc->status.b.bytes = txsize;
++00654                 desc->status.b.bs = BS_HOST_READY;
++00655 
++00656                 /* Set the next address of the buffer */
++00657                 buff_addr += txsize + off;
++00658                 desc_last = desc;
++00659                 desc++;
++00660         }
++00661 
++00662         /* Set the last, ioc and sp bits on the Last DMA Descriptor */
++00663         desc_last->status.b.l = 1;
++00664         desc_last->status.b.ioc = 1;
++00665         desc_last->status.b.sp = ep->dwc_ep.sent_zlp;
++00666         /* Save the last DMA descriptor pointer */
++00667         cfiep->dma_desc_last = desc_last;
++00668         cfiep->desc_count = sgval->bCount;
++00669 }
++00670 
++00674 static void cfi_build_concat_descs(struct cfiobject *cfi, cfi_ep_t * cfiep,
++00675                                    dwc_otg_pcd_request_t * req)
++00676 {
++00677         struct dwc_otg_pcd_ep *ep = cfiep->ep;
++00678         ddma_concat_buffer_setup_t *concatval = cfiep->bm_concat;
++00679         struct dwc_otg_dma_desc *desc = cfiep->ep->dwc_ep.descs;
++00680         struct dwc_otg_dma_desc *desc_last = cfiep->ep->dwc_ep.descs;
++00681         dma_addr_t buff_addr = req->dma;
++00682         int i;
++00683         uint16_t *txsize;
++00684 
++00685         txsize = concatval->wTxBytes;
++00686 
++00687         for (i = 0; i < concatval->hdr.bDescCount; i++) {
++00688                 desc->buf = buff_addr;
++00689                 desc->status.b.bs = BS_HOST_BUSY;
++00690                 desc->status.b.l = 0;
++00691                 desc->status.b.ioc = 0;
++00692                 desc->status.b.sp = 0;
++00693                 desc->status.b.bytes = *txsize;
++00694                 desc->status.b.bs = BS_HOST_READY;
++00695 
++00696                 txsize++;
++00697                 /* Set the next address of the buffer */
++00698                 buff_addr += UGETW(ep->desc->wMaxPacketSize);
++00699                 desc_last = desc;
++00700                 desc++;
++00701         }
++00702 
++00703         /* Set the last, ioc and sp bits on the Last DMA Descriptor */
++00704         desc_last->status.b.l = 1;
++00705         desc_last->status.b.ioc = 1;
++00706         desc_last->status.b.sp = ep->dwc_ep.sent_zlp;
++00707         cfiep->dma_desc_last = desc_last;
++00708         cfiep->desc_count = concatval->hdr.bDescCount;
++00709 }
++00710 
++00714 static void cfi_build_circ_descs(struct cfiobject *cfi, cfi_ep_t * cfiep,
++00715                                  dwc_otg_pcd_request_t * req)
++00716 {
++00717         /* @todo: MAS - add implementation when this feature needs to be tested */
++00718 }
++00719 
++00723 static void cfi_build_align_descs(struct cfiobject *cfi, cfi_ep_t * cfiep,
++00724                                   dwc_otg_pcd_request_t * req)
++00725 {
++00726         struct dwc_otg_pcd_ep *ep = cfiep->ep;
++00727         ddma_align_buffer_setup_t *alignval = cfiep->bm_align;
++00728         struct dwc_otg_dma_desc *desc = cfiep->ep->dwc_ep.descs;
++00729         dma_addr_t buff_addr = req->dma;
++00730 
++00731         desc->status.b.bs = BS_HOST_BUSY;
++00732         desc->status.b.l = 1;
++00733         desc->status.b.ioc = 1;
++00734         desc->status.b.sp = ep->dwc_ep.sent_zlp;
++00735         desc->status.b.bytes = req->length;
++00736         /* Adjust the buffer alignment */
++00737         desc->buf = (buff_addr + alignval->bAlign);
++00738         desc->status.b.bs = BS_HOST_READY;
++00739         cfiep->dma_desc_last = desc;
++00740         cfiep->desc_count = 1;
++00741 }
++00742 
++00747 static void cfi_build_descriptors(struct cfiobject *cfi,
++00748                                   struct dwc_otg_pcd *pcd,
++00749                                   struct dwc_otg_pcd_ep *ep,
++00750                                   dwc_otg_pcd_request_t * req)
++00751 {
++00752         cfi_ep_t *cfiep;
++00753 
++00754         /* Get the cfiep by the dwc_otg_pcd_ep */
++00755         cfiep = get_cfi_ep_by_pcd_ep(cfi, ep);
++00756         if (NULL == cfiep) {
++00757                 CFI_INFO("%s: Unable to find a matching active endpoint\n",
++00758                          __func__);
++00759                 return;
++00760         }
++00761 
++00762         cfiep->xfer_len = req->length;
++00763 
++00764         /* Iterate through all the DMA descriptors */
++00765         switch (cfiep->ep->dwc_ep.buff_mode) {
++00766         case BM_SG:
++00767                 cfi_build_sg_descs(cfi, cfiep, req);
++00768                 break;
++00769 
++00770         case BM_CONCAT:
++00771                 cfi_build_concat_descs(cfi, cfiep, req);
++00772                 break;
++00773 
++00774         case BM_CIRCULAR:
++00775                 cfi_build_circ_descs(cfi, cfiep, req);
++00776                 break;
++00777 
++00778         case BM_ALIGN:
++00779                 cfi_build_align_descs(cfi, cfiep, req);
++00780                 break;
++00781 
++00782         default:
++00783                 break;
++00784         }
++00785 }
++00786 
++00790 static void *cfi_ep_alloc_buf(struct cfiobject *cfi, struct dwc_otg_pcd *pcd,
++00791                               struct dwc_otg_pcd_ep *ep, dma_addr_t * dma,
++00792                               unsigned size, gfp_t flags)
++00793 {
++00794         return dwc_dma_alloc(size, dma);
++00795 }
++00796 
++00800 int init_cfi(cfiobject_t * cfiobj)
++00801 {
++00802         CFI_INFO("%s\n", __func__);
++00803 
++00804         /* Allocate a buffer for IN XFERs */
++00805         cfiobj->buf_in.buf =
++00806             dwc_dma_alloc(CFI_IN_BUF_LEN, &cfiobj->buf_in.addr);
++00807         if (NULL == cfiobj->buf_in.buf) {
++00808                 CFI_INFO("Unable to allocate buffer for INs\n");
++00809                 return -DWC_E_NO_MEMORY;
++00810         }
++00811 
++00812         /* Allocate a buffer for OUT XFERs */
++00813         cfiobj->buf_out.buf =
++00814             dwc_dma_alloc(CFI_OUT_BUF_LEN, &cfiobj->buf_out.addr);
++00815         if (NULL == cfiobj->buf_out.buf) {
++00816                 CFI_INFO("Unable to allocate buffer for OUT\n");
++00817                 return -DWC_E_NO_MEMORY;
++00818         }
++00819 
++00820         /* Initialize the callback function pointers */
++00821         cfiobj->ops.release = cfi_release;
++00822         cfiobj->ops.ep_enable = cfi_ep_enable;
++00823         cfiobj->ops.ctrl_write_complete = cfi_ctrl_write_complete;
++00824         cfiobj->ops.build_descriptors = cfi_build_descriptors;
++00825         cfiobj->ops.ep_alloc_buf = cfi_ep_alloc_buf;
++00826 
++00827         /* Initialize the list of active endpoints in the CFI object */
++00828         DWC_LIST_INIT(&cfiobj->active_eps);
++00829 
++00830         return 0;
++00831 }
++00832 
++00838 static int cfi_get_feature_value(uint8_t * buf, uint16_t buflen,
++00839                                  struct dwc_otg_pcd *pcd,
++00840                                  struct cfi_usb_ctrlrequest *ctrl_req)
++00841 {
++00842         int retval = -DWC_E_NOT_SUPPORTED;
++00843         struct dwc_otg_core_if *coreif = GET_CORE_IF(pcd);
++00844         uint16_t dfifo, rxfifo, txfifo;
++00845 
++00846         switch (ctrl_req->wIndex) {
++00847                 /* Whether the DDMA is enabled or not */
++00848         case FT_ID_DMA_MODE:
++00849                 *buf = (coreif->dma_enable && coreif->dma_desc_enable) ? 1 : 0;
++00850                 retval = 1;
++00851                 break;
++00852 
++00853         case FT_ID_DMA_BUFFER_SETUP:
++00854                 retval = cfi_ep_get_sg_val(buf, pcd, ctrl_req);
++00855                 break;
++00856 
++00857         case FT_ID_DMA_BUFF_ALIGN:
++00858                 retval = cfi_ep_get_align_val(buf, pcd, ctrl_req);
++00859                 break;
++00860 
++00861         case FT_ID_DMA_CONCAT_SETUP:
++00862                 retval = cfi_ep_get_concat_val(buf, pcd, ctrl_req);
++00863                 break;
++00864 
++00865         case FT_ID_DMA_CIRCULAR:
++00866                 CFI_INFO("GetFeature value (FT_ID_DMA_CIRCULAR)\n");
++00867                 break;
++00868 
++00869         case FT_ID_THRESHOLD_SETUP:
++00870                 CFI_INFO("GetFeature value (FT_ID_THRESHOLD_SETUP)\n");
++00871                 break;
++00872 
++00873         case FT_ID_DFIFO_DEPTH:
++00874                 dfifo = get_dfifo_size(coreif);
++00875                 *((uint16_t *) buf) = dfifo;
++00876                 retval = sizeof(uint16_t);
++00877                 break;
++00878 
++00879         case FT_ID_TX_FIFO_DEPTH:
++00880                 retval = get_txfifo_size(pcd, ctrl_req->wValue);
++00881                 if (retval >= 0) {
++00882                         txfifo = retval;
++00883                         *((uint16_t *) buf) = txfifo;
++00884                         retval = sizeof(uint16_t);
++00885                 }
++00886                 break;
++00887 
++00888         case FT_ID_RX_FIFO_DEPTH:
++00889                 retval = get_rxfifo_size(coreif, ctrl_req->wValue);
++00890                 if (retval >= 0) {
++00891                         rxfifo = retval;
++00892                         *((uint16_t *) buf) = rxfifo;
++00893                         retval = sizeof(uint16_t);
++00894                 }
++00895                 break;
++00896         }
++00897 
++00898         return retval;
++00899 }
++00900 
++00904 static int cfi_reset_sg_val(cfi_ep_t * cfiep)
++00905 {
++00906         dwc_memset(cfiep->bm_sg, 0, sizeof(ddma_sg_buffer_setup_t));
++00907         return 0;
++00908 }
++00909 
++00913 static int cfi_reset_align_val(cfi_ep_t * cfiep)
++00914 {
++00915         dwc_memset(cfiep->bm_sg, 0, sizeof(ddma_sg_buffer_setup_t));
++00916         return 0;
++00917 }
++00918 
++00924 static int cfi_reset_concat_val(cfi_ep_t * cfiep)
++00925 {
++00926         /* First we need to free the wTxBytes field */
++00927         if (cfiep->bm_concat->wTxBytes) {
++00928                 dwc_free(cfiep->bm_concat->wTxBytes);
++00929                 cfiep->bm_concat->wTxBytes = NULL;
++00930         }
++00931 
++00932         dwc_memset(cfiep->bm_concat, 0, sizeof(ddma_concat_buffer_setup_t));
++00933         return 0;
++00934 }
++00935 
++00939 static int cfi_ep_reset_all_setup_vals(cfi_ep_t * cfiep)
++00940 {
++00941         cfi_reset_sg_val(cfiep);
++00942         cfi_reset_align_val(cfiep);
++00943         cfi_reset_concat_val(cfiep);
++00944         return 0;
++00945 }
++00946 
++00947 static int cfi_handle_reset_fifo_val(struct dwc_otg_pcd *pcd, uint8_t ep_addr,
++00948                                      uint8_t rx_rst, uint8_t tx_rst)
++00949 {
++00950         int retval = -DWC_E_INVALID;
++00951         uint16_t tx_siz[15];
++00952         uint16_t rx_siz = 0;
++00953         dwc_otg_pcd_ep_t *ep = NULL;
++00954         dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
++00955         dwc_otg_core_params_t *params = GET_CORE_IF(pcd)->core_params;
++00956 
++00957         if (rx_rst) {
++00958                 rx_siz = params->dev_rx_fifo_size;
++00959                 params->dev_rx_fifo_size = GET_CORE_IF(pcd)->init_rxfsiz;
++00960         }
++00961 
++00962         if (tx_rst) {
++00963                 if (ep_addr == 0) {
++00964                         int i;
++00965 
++00966                         for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {
++00967                                 tx_siz[i] =
++00968                                     core_if->core_params->dev_tx_fifo_size[i];
++00969                                 core_if->core_params->dev_tx_fifo_size[i] =
++00970                                     core_if->init_txfsiz[i];
++00971                         }
++00972                 } else {
++00973 
++00974                         ep = get_ep_by_addr(pcd, ep_addr);
++00975 
++00976                         if (NULL == ep) {
++00977                                 CFI_INFO
++00978                                     ("%s: Unable to get the endpoint addr=0x%02x\n",
++00979                                      __func__, ep_addr);
++00980                                 return -DWC_E_INVALID;
++00981                         }
++00982 
++00983                         tx_siz[0] =
++00984                             params->dev_tx_fifo_size[ep->dwc_ep.tx_fifo_num -
++00985                                                      1];
++00986                         params->dev_tx_fifo_size[ep->dwc_ep.tx_fifo_num - 1] =
++00987                             GET_CORE_IF(pcd)->init_txfsiz[ep->dwc_ep.
++00988                                                           tx_fifo_num - 1];
++00989                 }
++00990         }
++00991 
++00992         if (resize_fifos(GET_CORE_IF(pcd))) {
++00993                 retval = 0;
++00994         } else {
++00995                 CFI_INFO
++00996                     ("%s: Error resetting the feature Reset All(FIFO size)\n",
++00997                      __func__);
++00998                 if (rx_rst) {
++00999                         params->dev_rx_fifo_size = rx_siz;
++01000                 }
++01001 
++01002                 if (tx_rst) {
++01003                         if (ep_addr == 0) {
++01004                                 int i;
++01005                                 for (i = 0; i < core_if->hwcfg4.b.num_in_eps;
++01006                                      i++) {
++01007                                         core_if->core_params->
++01008                                             dev_tx_fifo_size[i] = tx_siz[i];
++01009                                 }
++01010                         } else {
++01011                                 params->dev_tx_fifo_size[ep->dwc_ep.
++01012                                                          tx_fifo_num - 1] =
++01013                                     tx_siz[0];
++01014                         }
++01015                 }
++01016                 retval = -DWC_E_INVALID;
++01017         }
++01018         return retval;
++01019 }
++01020 
++01021 static int cfi_handle_reset_all(struct dwc_otg_pcd *pcd, uint8_t addr)
++01022 {
++01023         int retval = 0;
++01024         cfi_ep_t *cfiep;
++01025         cfiobject_t *cfi = pcd->cfi;
++01026         dwc_list_link_t *tmp;
++01027 
++01028         retval = cfi_handle_reset_fifo_val(pcd, addr, 1, 1);
++01029         if (retval < 0) {
++01030                 return retval;
++01031         }
++01032 
++01033         /* If the EP address is known then reset the features for only that EP */
++01034         if (addr) {
++01035                 cfiep = get_cfi_ep_by_addr(pcd->cfi, addr);
++01036                 if (NULL == cfiep) {
++01037                         CFI_INFO("%s: Error getting the EP address 0x%02x\n",
++01038                                  __func__, addr);
++01039                         return -DWC_E_INVALID;
++01040                 }
++01041                 retval = cfi_ep_reset_all_setup_vals(cfiep);
++01042                 cfiep->ep->dwc_ep.buff_mode = BM_STANDARD;
++01043         }
++01044         /* Otherwise (wValue == 0), reset all features of all EP's */
++01045         else {
++01046                 /* Traverse all the active EP's and reset the feature(s) value(s) */
++01047                 //list_for_each_entry(cfiep, &cfi->active_eps, lh) {
++01048                 DWC_LIST_FOREACH(tmp, &cfi->active_eps) {
++01049                         cfiep = DWC_LIST_ENTRY(tmp, struct cfi_ep, lh);
++01050                         retval = cfi_ep_reset_all_setup_vals(cfiep);
++01051                         cfiep->ep->dwc_ep.buff_mode = BM_STANDARD;
++01052                         if (retval < 0) {
++01053                                 CFI_INFO
++01054                                     ("%s: Error resetting the feature Reset All\n",
++01055                                      __func__);
++01056                                 return retval;
++01057                         }
++01058                 }
++01059         }
++01060         return retval;
++01061 }
++01062 
++01063 static int cfi_handle_reset_dma_buff_setup(struct dwc_otg_pcd *pcd,
++01064                                            uint8_t addr)
++01065 {
++01066         int retval = 0;
++01067         cfi_ep_t *cfiep;
++01068         cfiobject_t *cfi = pcd->cfi;
++01069         dwc_list_link_t *tmp;
++01070 
++01071         /* If the EP address is known then reset the features for only that EP */
++01072         if (addr) {
++01073                 cfiep = get_cfi_ep_by_addr(pcd->cfi, addr);
++01074                 if (NULL == cfiep) {
++01075                         CFI_INFO("%s: Error getting the EP address 0x%02x\n",
++01076                                  __func__, addr);
++01077                         return -DWC_E_INVALID;
++01078                 }
++01079                 retval = cfi_reset_sg_val(cfiep);
++01080         }
++01081         /* Otherwise (wValue == 0), reset all features of all EP's */
++01082         else {
++01083                 /* Traverse all the active EP's and reset the feature(s) value(s) */
++01084                 //list_for_each_entry(cfiep, &cfi->active_eps, lh) {
++01085                 DWC_LIST_FOREACH(tmp, &cfi->active_eps) {
++01086                         cfiep = DWC_LIST_ENTRY(tmp, struct cfi_ep, lh);
++01087                         retval = cfi_reset_sg_val(cfiep);
++01088                         if (retval < 0) {
++01089                                 CFI_INFO
++01090                                     ("%s: Error resetting the feature Buffer Setup\n",
++01091                                      __func__);
++01092                                 return retval;
++01093                         }
++01094                 }
++01095         }
++01096         return retval;
++01097 }
++01098 
++01099 static int cfi_handle_reset_concat_val(struct dwc_otg_pcd *pcd, uint8_t addr)
++01100 {
++01101         int retval = 0;
++01102         cfi_ep_t *cfiep;
++01103         cfiobject_t *cfi = pcd->cfi;
++01104         dwc_list_link_t *tmp;
++01105 
++01106         /* If the EP address is known then reset the features for only that EP */
++01107         if (addr) {
++01108                 cfiep = get_cfi_ep_by_addr(pcd->cfi, addr);
++01109                 if (NULL == cfiep) {
++01110                         CFI_INFO("%s: Error getting the EP address 0x%02x\n",
++01111                                  __func__, addr);
++01112                         return -DWC_E_INVALID;
++01113                 }
++01114                 retval = cfi_reset_concat_val(cfiep);
++01115         }
++01116         /* Otherwise (wValue == 0), reset all features of all EP's */
++01117         else {
++01118                 /* Traverse all the active EP's and reset the feature(s) value(s) */
++01119                 //list_for_each_entry(cfiep, &cfi->active_eps, lh) {
++01120                 DWC_LIST_FOREACH(tmp, &cfi->active_eps) {
++01121                         cfiep = DWC_LIST_ENTRY(tmp, struct cfi_ep, lh);
++01122                         retval = cfi_reset_concat_val(cfiep);
++01123                         if (retval < 0) {
++01124                                 CFI_INFO
++01125                                     ("%s: Error resetting the feature Concatenation Value\n",
++01126                                      __func__);
++01127                                 return retval;
++01128                         }
++01129                 }
++01130         }
++01131         return retval;
++01132 }
++01133 
++01134 static int cfi_handle_reset_align_val(struct dwc_otg_pcd *pcd, uint8_t addr)
++01135 {
++01136         int retval = 0;
++01137         cfi_ep_t *cfiep;
++01138         cfiobject_t *cfi = pcd->cfi;
++01139         dwc_list_link_t *tmp;
++01140 
++01141         /* If the EP address is known then reset the features for only that EP */
++01142         if (addr) {
++01143                 cfiep = get_cfi_ep_by_addr(pcd->cfi, addr);
++01144                 if (NULL == cfiep) {
++01145                         CFI_INFO("%s: Error getting the EP address 0x%02x\n",
++01146                                  __func__, addr);
++01147                         return -DWC_E_INVALID;
++01148                 }
++01149                 retval = cfi_reset_align_val(cfiep);
++01150         }
++01151         /* Otherwise (wValue == 0), reset all features of all EP's */
++01152         else {
++01153                 /* Traverse all the active EP's and reset the feature(s) value(s) */
++01154                 //list_for_each_entry(cfiep, &cfi->active_eps, lh) {
++01155                 DWC_LIST_FOREACH(tmp, &cfi->active_eps) {
++01156                         cfiep = DWC_LIST_ENTRY(tmp, struct cfi_ep, lh);
++01157                         retval = cfi_reset_align_val(cfiep);
++01158                         if (retval < 0) {
++01159                                 CFI_INFO
++01160                                     ("%s: Error resetting the feature Aliignment Value\n",
++01161                                      __func__);
++01162                                 return retval;
++01163                         }
++01164                 }
++01165         }
++01166         return retval;
++01167 
++01168 }
++01169 
++01170 static int cfi_preproc_reset(struct dwc_otg_pcd *pcd,
++01171                              struct cfi_usb_ctrlrequest *req)
++01172 {
++01173         int retval = 0;
++01174 
++01175         switch (req->wIndex) {
++01176         case 0:
++01177                 /* Reset all features */
++01178                 retval = cfi_handle_reset_all(pcd, req->wValue & 0xff);
++01179                 break;
++01180 
++01181         case FT_ID_DMA_BUFFER_SETUP:
++01182                 /* Reset the SG buffer setup */
++01183                 retval =
++01184                     cfi_handle_reset_dma_buff_setup(pcd, req->wValue & 0xff);
++01185                 break;
++01186 
++01187         case FT_ID_DMA_CONCAT_SETUP:
++01188                 /* Reset the Concatenation buffer setup */
++01189                 retval = cfi_handle_reset_concat_val(pcd, req->wValue & 0xff);
++01190                 break;
++01191 
++01192         case FT_ID_DMA_BUFF_ALIGN:
++01193                 /* Reset the Alignment buffer setup */
++01194                 retval = cfi_handle_reset_align_val(pcd, req->wValue & 0xff);
++01195                 break;
++01196 
++01197         case FT_ID_TX_FIFO_DEPTH:
++01198                 retval =
++01199                     cfi_handle_reset_fifo_val(pcd, req->wValue & 0xff, 0, 1);
++01200                 pcd->cfi->need_gadget_att = 0;
++01201                 break;
++01202 
++01203         case FT_ID_RX_FIFO_DEPTH:
++01204                 retval = cfi_handle_reset_fifo_val(pcd, 0, 1, 0);
++01205                 pcd->cfi->need_gadget_att = 0;
++01206                 break;
++01207         default:
++01208                 break;
++01209         }
++01210         return retval;
++01211 }
++01212 
++01216 static int cfi_ep_set_sg_val(uint8_t * buf, struct dwc_otg_pcd *pcd)
++01217 {
++01218         uint8_t inaddr, outaddr;
++01219         cfi_ep_t *epin, *epout;
++01220         ddma_sg_buffer_setup_t *psgval;
++01221         uint32_t desccount, size;
++01222 
++01223         CFI_INFO("%s\n", __func__);
++01224 
++01225         psgval = (ddma_sg_buffer_setup_t *) buf;
++01226         desccount = (uint32_t) psgval->bCount;
++01227         size = (uint32_t) psgval->wSize;
++01228 
++01229         /* Check the DMA descriptor count */
++01230         if ((desccount > MAX_DMA_DESCS_PER_EP) || (desccount == 0)) {
++01231                 CFI_INFO
++01232                     ("%s: The count of DMA Descriptors should be between 1 and %d\n",
++01233                      __func__, MAX_DMA_DESCS_PER_EP);
++01234                 return -DWC_E_INVALID;
++01235         }
++01236 
++01237         /* Check the DMA descriptor count */
++01238 
++01239         if (size == 0) {
++01240 
++01241                 CFI_INFO("%s: The transfer size should be at least 1 byte\n",
++01242                          __func__);
++01243 
++01244                 return -DWC_E_INVALID;
++01245 
++01246         }
++01247 
++01248         inaddr = psgval->bInEndpointAddress;
++01249         outaddr = psgval->bOutEndpointAddress;
++01250 
++01251         epin = get_cfi_ep_by_addr(pcd->cfi, inaddr);
++01252         epout = get_cfi_ep_by_addr(pcd->cfi, outaddr);
++01253 
++01254         if (NULL == epin || NULL == epout) {
++01255                 CFI_INFO
++01256                     ("%s: Unable to get the endpoints inaddr=0x%02x outaddr=0x%02x\n",
++01257                      __func__, inaddr, outaddr);
++01258                 return -DWC_E_INVALID;
++01259         }
++01260 
++01261         epin->ep->dwc_ep.buff_mode = BM_SG;
++01262         dwc_memcpy(epin->bm_sg, psgval, sizeof(ddma_sg_buffer_setup_t));
++01263 
++01264         epout->ep->dwc_ep.buff_mode = BM_SG;
++01265         dwc_memcpy(epout->bm_sg, psgval, sizeof(ddma_sg_buffer_setup_t));
++01266 
++01267         return 0;
++01268 }
++01269 
++01273 static int cfi_ep_set_alignment_val(uint8_t * buf, struct dwc_otg_pcd *pcd)
++01274 {
++01275         cfi_ep_t *ep;
++01276         uint8_t addr;
++01277         ddma_align_buffer_setup_t *palignval;
++01278 
++01279         palignval = (ddma_align_buffer_setup_t *) buf;
++01280         addr = palignval->bEndpointAddress;
++01281 
++01282         ep = get_cfi_ep_by_addr(pcd->cfi, addr);
++01283 
++01284         if (NULL == ep) {
++01285                 CFI_INFO("%s: Unable to get the endpoint addr=0x%02x\n",
++01286                          __func__, addr);
++01287                 return -DWC_E_INVALID;
++01288         }
++01289 
++01290         ep->ep->dwc_ep.buff_mode = BM_ALIGN;
++01291         dwc_memcpy(ep->bm_align, palignval, sizeof(ddma_align_buffer_setup_t));
++01292 
++01293         return 0;
++01294 }
++01295 
++01299 static int cfi_ep_set_concat_val(uint8_t * buf, struct dwc_otg_pcd *pcd)
++01300 {
++01301         uint8_t addr;
++01302         cfi_ep_t *ep;
++01303         struct _ddma_concat_buffer_setup_hdr *pConcatValHdr;
++01304         uint16_t *pVals;
++01305         uint32_t desccount;
++01306         int i;
++01307         uint16_t mps;
++01308 
++01309         pConcatValHdr = (struct _ddma_concat_buffer_setup_hdr *)buf;
++01310         desccount = (uint32_t) pConcatValHdr->bDescCount;
++01311         pVals = (uint16_t *) (buf + BS_CONCAT_VAL_HDR_LEN);
++01312 
++01313         /* Check the DMA descriptor count */
++01314         if (desccount > MAX_DMA_DESCS_PER_EP) {
++01315                 CFI_INFO("%s: Maximum DMA Descriptor count should be %d\n",
++01316                          __func__, MAX_DMA_DESCS_PER_EP);
++01317                 return -DWC_E_INVALID;
++01318         }
++01319 
++01320         addr = pConcatValHdr->bEndpointAddress;
++01321         ep = get_cfi_ep_by_addr(pcd->cfi, addr);
++01322         if (NULL == ep) {
++01323                 CFI_INFO("%s: Unable to get the endpoint addr=0x%02x\n",
++01324                          __func__, addr);
++01325                 return -DWC_E_INVALID;
++01326         }
++01327 
++01328         mps = UGETW(ep->ep->desc->wMaxPacketSize);
++01329 
++01330 #if 0
++01331         for (i = 0; i < desccount; i++) {
++01332                 CFI_INFO("%s: wTxSize[%d]=0x%04x\n", __func__, i, pVals[i]);
++01333         }
++01334         CFI_INFO("%s: epname=%s; mps=%d\n", __func__, ep->ep->ep.name, mps);
++01335 #endif
++01336 
++01337         /* Check the wTxSizes to be less than or equal to the mps */
++01338         for (i = 0; i < desccount; i++) {
++01339                 if (pVals[i] > mps) {
++01340                         CFI_INFO
++01341                             ("%s: ERROR - the wTxSize[%d] should be <= MPS (wTxSize=%d)\n",
++01342                              __func__, i, pVals[i]);
++01343                         return -DWC_E_INVALID;
++01344                 }
++01345         }
++01346 
++01347         ep->ep->dwc_ep.buff_mode = BM_CONCAT;
++01348         dwc_memcpy(ep->bm_concat, pConcatValHdr, BS_CONCAT_VAL_HDR_LEN);
++01349 
++01350         /* Free the previously allocated storage for the wTxBytes */
++01351         if (ep->bm_concat->wTxBytes) {
++01352                 dwc_free(ep->bm_concat->wTxBytes);
++01353         }
++01354 
++01355         /* Allocate a new storage for the wTxBytes field */
++01356         ep->bm_concat->wTxBytes =
++01357             dwc_alloc(sizeof(uint16_t) * pConcatValHdr->bDescCount);
++01358         if (NULL == ep->bm_concat->wTxBytes) {
++01359                 CFI_INFO("%s: Unable to allocate memory\n", __func__);
++01360                 return -DWC_E_NO_MEMORY;
++01361         }
++01362 
++01363         /* Copy the new values into the wTxBytes filed */
++01364         dwc_memcpy(ep->bm_concat->wTxBytes, buf + BS_CONCAT_VAL_HDR_LEN,
++01365                    sizeof(uint16_t) * pConcatValHdr->bDescCount);
++01366 
++01367         return 0;
++01368 }
++01369 
++01378 static uint16_t get_dfifo_size(dwc_otg_core_if_t * core_if)
++01379 {
++01380         dwc_otg_core_params_t *params = core_if->core_params;
++01381         uint16_t dfifo_total = 0;
++01382         int i;
++01383 
++01384         /* The shared RxFIFO size */
++01385         dfifo_total =
++01386             params->dev_rx_fifo_size + params->dev_nperio_tx_fifo_size;
++01387 
++01388         /* Add up each TxFIFO size to the total */
++01389         for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {
++01390                 dfifo_total += params->dev_tx_fifo_size[i];
++01391         }
++01392 
++01393         return dfifo_total;
++01394 }
++01395 
++01404 static int32_t get_rxfifo_size(dwc_otg_core_if_t * core_if, uint16_t wValue)
++01405 {
++01406         switch (wValue >> 8) {
++01407         case 0:
++01408                 return (core_if->pwron_rxfsiz <
++01409                         32768) ? core_if->pwron_rxfsiz : 32768;
++01410                 break;
++01411         case 1:
++01412                 return core_if->core_params->dev_rx_fifo_size;
++01413                 break;
++01414         default:
++01415                 return -DWC_E_INVALID;
++01416                 break;
++01417         }
++01418 }
++01419 
++01428 static int32_t get_txfifo_size(struct dwc_otg_pcd *pcd, uint16_t wValue)
++01429 {
++01430         dwc_otg_pcd_ep_t *ep;
++01431 
++01432         ep = get_ep_by_addr(pcd, wValue & 0xff);
++01433 
++01434         if (NULL == ep) {
++01435                 CFI_INFO("%s: Unable to get the endpoint addr=0x%02x\n",
++01436                          __func__, wValue & 0xff);
++01437                 return -DWC_E_INVALID;
++01438         }
++01439 
++01440         if (!ep->dwc_ep.is_in) {
++01441                 CFI_INFO
++01442                     ("%s: No Tx FIFO assingned to the Out endpoint addr=0x%02x\n",
++01443                      __func__, wValue & 0xff);
++01444                 return -DWC_E_INVALID;
++01445         }
++01446 
++01447         switch (wValue >> 8) {
++01448         case 0:
++01449                 return (GET_CORE_IF(pcd)->
++01450                         pwron_txfsiz[ep->dwc_ep.tx_fifo_num - 1] <
++01451                         768) ? GET_CORE_IF(pcd)->pwron_txfsiz[ep->dwc_ep.
++01452                                                               tx_fifo_num -
++01453                                                               1] : 32768;
++01454                 break;
++01455         case 1:
++01456                 return GET_CORE_IF(pcd)->core_params->dev_tx_fifo_size[ep->
++01457                                                                        dwc_ep.
++01458                                                                        num - 1];
++01459                 break;
++01460         default:
++01461                 return -DWC_E_INVALID;
++01462                 break;
++01463         }
++01464 }
++01465 
++01475 static uint8_t check_fifo_sizes(dwc_otg_core_if_t * core_if)
++01476 {
++01477         uint16_t dfifo_actual = 0;
++01478         dwc_otg_core_params_t *params = core_if->core_params;
++01479         uint16_t start_addr = 0;
++01480         int i;
++01481 
++01482         dfifo_actual =
++01483             params->dev_rx_fifo_size + params->dev_nperio_tx_fifo_size;
++01484 
++01485         for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {
++01486                 dfifo_actual += params->dev_tx_fifo_size[i];
++01487         }
++01488 
++01489         if (dfifo_actual > core_if->total_fifo_size) {
++01490                 return 0;
++01491         }
++01492 
++01493         if (params->dev_rx_fifo_size > 32768 || params->dev_rx_fifo_size < 16)
++01494                 return 0;
++01495 
++01496         if (params->dev_nperio_tx_fifo_size > 32768
++01497             || params->dev_nperio_tx_fifo_size < 16)
++01498                 return 0;
++01499 
++01500         for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {
++01501 
++01502                 if (params->dev_tx_fifo_size[i] > 768
++01503                     || params->dev_tx_fifo_size[i] < 4)
++01504                         return 0;
++01505         }
++01506 
++01507         if (params->dev_rx_fifo_size > core_if->pwron_rxfsiz)
++01508                 return 0;
++01509         start_addr = params->dev_rx_fifo_size;
++01510 
++01511         if (params->dev_nperio_tx_fifo_size > core_if->pwron_gnptxfsiz)
++01512                 return 0;
++01513         start_addr += params->dev_nperio_tx_fifo_size;
++01514 
++01515         for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {
++01516 
++01517                 if (params->dev_tx_fifo_size[i] > core_if->pwron_txfsiz[i])
++01518                         return 0;
++01519                 start_addr += params->dev_tx_fifo_size[i];
++01520         }
++01521 
++01522         return 1;
++01523 }
++01524 
++01533 static uint8_t resize_fifos(dwc_otg_core_if_t * core_if)
++01534 {
++01535         int i = 0;
++01536         dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
++01537         dwc_otg_core_params_t *params = core_if->core_params;
++01538         uint32_t rx_fifo_size;
++01539         fifosize_data_t nptxfifosize;
++01540         fifosize_data_t txfifosize[15];
++01541 
++01542         uint32_t rx_fsz_bak;
++01543         uint32_t nptxfsz_bak;
++01544         uint32_t txfsz_bak[15];
++01545 
++01546         uint16_t start_address;
++01547         uint8_t retval = 1;
++01548 
++01549         if (!check_fifo_sizes(core_if)) {
++01550                 return 0;
++01551         }
++01552 
++01553         /* Configure data FIFO sizes */
++01554         if (core_if->hwcfg2.b.dynamic_fifo && params->enable_dynamic_fifo) {
++01555                 rx_fsz_bak = dwc_read_reg32(&global_regs->grxfsiz);
++01556                 rx_fifo_size = params->dev_rx_fifo_size;
++01557                 dwc_write_reg32(&global_regs->grxfsiz, rx_fifo_size);
++01558 
++01559                 /*
++01560                  * Tx FIFOs These FIFOs are numbered from 1 to 15.
++01561                  * Indexes of the FIFO size module parameters in the
++01562                  * dev_tx_fifo_size array and the FIFO size registers in
++01563                  * the dptxfsiz_dieptxf array run from 0 to 14.
++01564                  */
++01565 
++01566                 /* Non-periodic Tx FIFO */
++01567                 nptxfsz_bak = dwc_read_reg32(&global_regs->gnptxfsiz);
++01568                 nptxfifosize.b.depth = params->dev_nperio_tx_fifo_size;
++01569                 start_address = params->dev_rx_fifo_size;
++01570                 nptxfifosize.b.startaddr = start_address;
++01571 
++01572                 dwc_write_reg32(&global_regs->gnptxfsiz, nptxfifosize.d32);
++01573 
++01574                 start_address += nptxfifosize.b.depth;
++01575 
++01576                 for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {
++01577                         txfsz_bak[i] =
++01578                             dwc_read_reg32(&global_regs->dptxfsiz_dieptxf[i]);
++01579 
++01580                         txfifosize[i].b.depth = params->dev_tx_fifo_size[i];
++01581                         txfifosize[i].b.startaddr = start_address;
++01582                         dwc_write_reg32(&global_regs->dptxfsiz_dieptxf[i],
++01583                                         txfifosize[i].d32);
++01584 
++01585                         start_address += txfifosize[i].b.depth;
++01586                 }
++01587 
++01589                 if (rx_fifo_size != dwc_read_reg32(&global_regs->grxfsiz)) {
++01590                         retval = 0;
++01591                 }
++01592 
++01593                 if (nptxfifosize.d32 != dwc_read_reg32(&global_regs->gnptxfsiz)) {
++01594                         retval = 0;
++01595                 }
++01596 
++01597                 for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {
++01598                         if (txfifosize[i].d32 !=
++01599                             dwc_read_reg32(&global_regs->dptxfsiz_dieptxf[i])) {
++01600                                 retval = 0;
++01601                         }
++01602                 }
++01603 
++01605                 if (retval == 0) {
++01606                         dwc_write_reg32(&global_regs->grxfsiz, rx_fsz_bak);
++01607 
++01608                         /* Non-periodic Tx FIFO */
++01609                         dwc_write_reg32(&global_regs->gnptxfsiz, nptxfsz_bak);
++01610 
++01611                         for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {
++01612                                 dwc_write_reg32(&global_regs->
++01613                                                 dptxfsiz_dieptxf[i],
++01614                                                 txfsz_bak[i]);
++01615                         }
++01616                 }
++01617         } else {
++01618                 return 0;
++01619         }
++01620 
++01621         /* Flush the FIFOs */
++01622         dwc_otg_flush_tx_fifo(core_if, 0x10);   /* all Tx FIFOs */
++01623         dwc_otg_flush_rx_fifo(core_if);
++01624 
++01625         return retval;
++01626 }
++01627 
++01631 static int cfi_ep_set_tx_fifo_val(uint8_t * buf, dwc_otg_pcd_t * pcd)
++01632 {
++01633         int retval;
++01634         uint32_t fsiz;
++01635         uint16_t size;
++01636         uint16_t ep_addr;
++01637         dwc_otg_pcd_ep_t *ep;
++01638         dwc_otg_core_params_t *params = GET_CORE_IF(pcd)->core_params;
++01639         tx_fifo_size_setup_t *ptxfifoval;
++01640 
++01641         ptxfifoval = (tx_fifo_size_setup_t *) buf;
++01642         ep_addr = ptxfifoval->bEndpointAddress;
++01643         size = ptxfifoval->wDepth;
++01644 
++01645         ep = get_ep_by_addr(pcd, ep_addr);
++01646 
++01647         CFI_INFO
++01648             ("%s: Set Tx FIFO size: endpoint addr=0x%02x, depth=%d, FIFO Num=%d\n",
++01649              __func__, ep_addr, size, ep->dwc_ep.tx_fifo_num);
++01650 
++01651         if (NULL == ep) {
++01652                 CFI_INFO("%s: Unable to get the endpoint addr=0x%02x\n",
++01653                          __func__, ep_addr);
++01654                 return -DWC_E_INVALID;
++01655         }
++01656 
++01657         fsiz = params->dev_tx_fifo_size[ep->dwc_ep.tx_fifo_num - 1];
++01658         params->dev_tx_fifo_size[ep->dwc_ep.tx_fifo_num - 1] = size;
++01659 
++01660         if (resize_fifos(GET_CORE_IF(pcd))) {
++01661                 retval = 0;
++01662         } else {
++01663                 CFI_INFO
++01664                     ("%s: Error setting the feature Tx FIFO Size for EP%d\n",
++01665                      __func__, ep_addr);
++01666                 params->dev_tx_fifo_size[ep->dwc_ep.tx_fifo_num - 1] = fsiz;
++01667                 retval = -DWC_E_INVALID;
++01668         }
++01669 
++01670         return retval;
++01671 }
++01672 
++01676 static int cfi_set_rx_fifo_val(uint8_t * buf, dwc_otg_pcd_t * pcd)
++01677 {
++01678         int retval;
++01679         uint32_t fsiz;
++01680         uint16_t size;
++01681         dwc_otg_core_params_t *params = GET_CORE_IF(pcd)->core_params;
++01682         rx_fifo_size_setup_t *prxfifoval;
++01683 
++01684         prxfifoval = (rx_fifo_size_setup_t *) buf;
++01685         size = prxfifoval->wDepth;
++01686 
++01687         fsiz = params->dev_rx_fifo_size;
++01688         params->dev_rx_fifo_size = size;
++01689 
++01690         if (resize_fifos(GET_CORE_IF(pcd))) {
++01691                 retval = 0;
++01692         } else {
++01693                 CFI_INFO("%s: Error setting the feature Rx FIFO Size\n",
++01694                          __func__);
++01695                 params->dev_rx_fifo_size = fsiz;
++01696                 retval = -DWC_E_INVALID;
++01697         }
++01698 
++01699         return retval;
++01700 }
++01701 
++01705 static int cfi_ep_get_sg_val(uint8_t * buf, struct dwc_otg_pcd *pcd,
++01706                              struct cfi_usb_ctrlrequest *req)
++01707 {
++01708         int retval = -DWC_E_INVALID;
++01709         uint8_t addr;
++01710         cfi_ep_t *ep;
++01711 
++01712         /* The Low Byte of the wValue contains a non-zero address of the endpoint */
++01713         addr = req->wValue & 0xFF;
++01714         if (addr == 0)          /* The address should be non-zero */
++01715                 return retval;
++01716 
++01717         ep = get_cfi_ep_by_addr(pcd->cfi, addr);
++01718         if (NULL == ep) {
++01719                 CFI_INFO("%s: Unable to get the endpoint address(0x%02x)\n",
++01720                          __func__, addr);
++01721                 return retval;
++01722         }
++01723 
++01724         dwc_memcpy(buf, ep->bm_sg, BS_SG_VAL_DESC_LEN);
++01725         retval = BS_SG_VAL_DESC_LEN;
++01726         return retval;
++01727 }
++01728 
++01733 static int cfi_ep_get_concat_val(uint8_t * buf, struct dwc_otg_pcd *pcd,
++01734                                  struct cfi_usb_ctrlrequest *req)
++01735 {
++01736         int retval = -DWC_E_INVALID;
++01737         uint8_t addr;
++01738         cfi_ep_t *ep;
++01739         uint8_t desc_count;
++01740 
++01741         /* The Low Byte of the wValue contains a non-zero address of the endpoint */
++01742         addr = req->wValue & 0xFF;
++01743         if (addr == 0)          /* The address should be non-zero */
++01744                 return retval;
++01745 
++01746         ep = get_cfi_ep_by_addr(pcd->cfi, addr);
++01747         if (NULL == ep) {
++01748                 CFI_INFO("%s: Unable to get the endpoint address(0x%02x)\n",
++01749                          __func__, addr);
++01750                 return retval;
++01751         }
++01752 
++01753         /* Copy the header to the buffer */
++01754         dwc_memcpy(buf, ep->bm_concat, BS_CONCAT_VAL_HDR_LEN);
++01755         /* Advance the buffer pointer by the header size */
++01756         buf += BS_CONCAT_VAL_HDR_LEN;
++01757 
++01758         desc_count = ep->bm_concat->hdr.bDescCount;
++01759         /* Copy alll the wTxBytes to the buffer */
++01760         dwc_memcpy(buf, ep->bm_concat->wTxBytes, sizeof(uid16_t) * desc_count);
++01761 
++01762         retval = BS_CONCAT_VAL_HDR_LEN + sizeof(uid16_t) * desc_count;
++01763         return retval;
++01764 }
++01765 
++01772 static int cfi_ep_get_align_val(uint8_t * buf, struct dwc_otg_pcd *pcd,
++01773                                 struct cfi_usb_ctrlrequest *req)
++01774 {
++01775         int retval = -DWC_E_INVALID;
++01776         uint8_t addr;
++01777         cfi_ep_t *ep;
++01778 
++01779         /* The Low Byte of the wValue contains a non-zero address of the endpoint */
++01780         addr = req->wValue & 0xFF;
++01781         if (addr == 0)          /* The address should be non-zero */
++01782                 return retval;
++01783 
++01784         ep = get_cfi_ep_by_addr(pcd->cfi, addr);
++01785         if (NULL == ep) {
++01786                 CFI_INFO("%s: Unable to get the endpoint address(0x%02x)\n",
++01787                          __func__, addr);
++01788                 return retval;
++01789         }
++01790 
++01791         dwc_memcpy(buf, ep->bm_align, BS_ALIGN_VAL_HDR_LEN);
++01792         retval = BS_ALIGN_VAL_HDR_LEN;
++01793 
++01794         return retval;
++01795 }
++01796 
++01804 static int cfi_set_feature_value(struct dwc_otg_pcd *pcd)
++01805 {
++01806         int retval = -DWC_E_NOT_SUPPORTED;
++01807         uint16_t wIndex, wValue;
++01808         uint8_t bRequest;
++01809         struct dwc_otg_core_if *coreif;
++01810         cfiobject_t *cfi = pcd->cfi;
++01811         struct cfi_usb_ctrlrequest *ctrl_req;
++01812         uint8_t *buf;
++01813         ctrl_req = &cfi->ctrl_req;
++01814 
++01815         buf = pcd->cfi->ctrl_req.data;
++01816 
++01817         coreif = GET_CORE_IF(pcd);
++01818         bRequest = ctrl_req->bRequest;
++01819         wIndex = DWC_CONSTANT_CPU_TO_LE16(ctrl_req->wIndex);
++01820         wValue = DWC_CONSTANT_CPU_TO_LE16(ctrl_req->wValue);
++01821 
++01822         /* See which feature is to be modified */
++01823         switch (wIndex) {
++01824         case FT_ID_DMA_BUFFER_SETUP:
++01825                 /* Modify the feature */
++01826                 if ((retval = cfi_ep_set_sg_val(buf, pcd)) < 0)
++01827                         return retval;
++01828 
++01829                 /* And send this request to the gadget */
++01830                 cfi->need_gadget_att = 1;
++01831                 break;
++01832 
++01833         case FT_ID_DMA_BUFF_ALIGN:
++01834                 if ((retval = cfi_ep_set_alignment_val(buf, pcd)) < 0)
++01835                         return retval;
++01836                 cfi->need_gadget_att = 1;
++01837                 break;
++01838 
++01839         case FT_ID_DMA_CONCAT_SETUP:
++01840                 /* Modify the feature */
++01841                 if ((retval = cfi_ep_set_concat_val(buf, pcd)) < 0)
++01842                         return retval;
++01843                 cfi->need_gadget_att = 1;
++01844                 break;
++01845 
++01846         case FT_ID_DMA_CIRCULAR:
++01847                 CFI_INFO("FT_ID_DMA_CIRCULAR\n");
++01848                 break;
++01849 
++01850         case FT_ID_THRESHOLD_SETUP:
++01851                 CFI_INFO("FT_ID_THRESHOLD_SETUP\n");
++01852                 break;
++01853 
++01854         case FT_ID_DFIFO_DEPTH:
++01855                 CFI_INFO("FT_ID_DFIFO_DEPTH\n");
++01856                 break;
++01857 
++01858         case FT_ID_TX_FIFO_DEPTH:
++01859                 CFI_INFO("FT_ID_TX_FIFO_DEPTH\n");
++01860                 if ((retval = cfi_ep_set_tx_fifo_val(buf, pcd)) < 0)
++01861                         return retval;
++01862                 cfi->need_gadget_att = 0;
++01863                 break;
++01864 
++01865         case FT_ID_RX_FIFO_DEPTH:
++01866                 CFI_INFO("FT_ID_RX_FIFO_DEPTH\n");
++01867                 if ((retval = cfi_set_rx_fifo_val(buf, pcd)) < 0)
++01868                         return retval;
++01869                 cfi->need_gadget_att = 0;
++01870                 break;
++01871         }
++01872 
++01873         return retval;
++01874 }
++01875 
++01876 #endif                          //DWC_UTE_CFI
++
Generated on Tue May 5 02:22:48 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__cfi_8c.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__cfi_8c.html 2013-07-26 19:31:20.000000000 +0000 +@@ -0,0 +1,36 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_cfi.c File Reference ++ ++ ++ ++ ++
++
++
++
++

dwc_otg_cfi.c File Reference

This file contains the most of the CFI implementation for the OTG. More... ++

++ ++

++Go to the source code of this file. ++ ++
++

Detailed Description

++This file contains the most of the CFI implementation for the OTG. ++

++ ++

++Definition in file dwc_otg_cfi.c.

Generated on Tue May 5 02:22:48 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__cfi_8h-source.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__cfi_8h-source.html 2013-07-26 19:31:20.000000000 +0000 +@@ -0,0 +1,299 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_cfi.h Source File ++ ++ ++ ++ ++
++
++
++
++

dwc_otg_cfi.h

Go to the documentation of this file.
00001 /* ==========================================================================
++00002  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
++00003  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
++00004  * otherwise expressly agreed to in writing between Synopsys and you.
++00005  * 
++00006  * The Software IS NOT an item of Licensed Software or Licensed Product under
++00007  * any End User Software License Agreement or Agreement for Licensed Product
++00008  * with Synopsys or any supplement thereto. You are permitted to use and
++00009  * redistribute this Software in source and binary forms, with or without
++00010  * modification, provided that redistributions of source code must retain this
++00011  * notice. You may not view, use, disclose, copy or distribute this file or
++00012  * any information contained herein except pursuant to this license grant from
++00013  * Synopsys. If you do not agree with this notice, including the disclaimer
++00014  * below, then you are not authorized to use the Software.
++00015  * 
++00016  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
++00017  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++00018  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++00019  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
++00020  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++00021  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
++00022  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
++00023  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
++00024  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
++00025  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
++00026  * DAMAGE.
++00027  * ========================================================================== */
++00028 
++00029 #if !defined(__DWC_OTG_CFI_H__)
++00030 #define __DWC_OTG_CFI_H__
++00031 
++00032 #include "dwc_otg_pcd.h"
++00033 #include "dwc_cfi_common.h"
++00034 
++00043 struct dwc_otg_pcd;
++00044 struct dwc_otg_pcd_ep;
++00045 
++00048 #define FT_ID_DMA_MODE                                  0x0001
++00049 #define FT_ID_DMA_BUFFER_SETUP                  0x0002
++00050 #define FT_ID_DMA_BUFF_ALIGN                    0x0003
++00051 #define FT_ID_DMA_CONCAT_SETUP                  0x0004
++00052 #define FT_ID_DMA_CIRCULAR                              0x0005
++00053 #define FT_ID_THRESHOLD_SETUP                   0x0006
++00054 #define FT_ID_DFIFO_DEPTH                               0x0007
++00055 #define FT_ID_TX_FIFO_DEPTH                             0x0008
++00056 #define FT_ID_RX_FIFO_DEPTH                             0x0009
++00057 
++00058 /**********************************************************/
++00059 #define CFI_INFO_DEF
++00060 
++00061 #ifdef CFI_INFO_DEF
++00062 #define CFI_INFO(fmt...)        DWC_PRINTF("CFI: " fmt);
++00063 #else
++00064 #define CFI_INFO(fmt...)
++00065 #endif
++00066 
++00067 #define min(x,y) ({ \
++00068         x < y ? x : y; })
++00069 
++00070 #define max(x,y) ({ \
++00071         x > y ? x : y; })
++00072 
++00077 struct _ddma_sg_buffer_setup {
++00078 #define BS_SG_VAL_DESC_LEN      6
++00079         /* The OUT EP address */
++00080         uint8_t bOutEndpointAddress;
++00081         /* The IN EP address */
++00082         uint8_t bInEndpointAddress;
++00083         /* Number of bytes to put between transfer segments (must be DWORD boundaries) */
++00084         uint8_t bOffset;
++00085         /* The number of transfer segments (a DMA descriptors per each segment) */
++00086         uint8_t bCount;
++00087         /* Size (in byte) of each transfer segment */
++00088         uint16_t wSize;
++00089 } __attribute__ ((packed));
++00090 typedef struct _ddma_sg_buffer_setup ddma_sg_buffer_setup_t;
++00091 
++00093 struct _ddma_concat_buffer_setup_hdr {
++00094 #define BS_CONCAT_VAL_HDR_LEN   4
++00095         /* The endpoint for which the buffer is to be set up */
++00096         uint8_t bEndpointAddress;
++00097         /* The count of descriptors to be used */
++00098         uint8_t bDescCount;
++00099         /* The total size of the transfer */
++00100         uint16_t wSize;
++00101 } __attribute__ ((packed));
++00102 typedef struct _ddma_concat_buffer_setup_hdr ddma_concat_buffer_setup_hdr_t;
++00103 
++00105 struct _ddma_concat_buffer_setup {
++00106         /* The SG header */
++00107         ddma_concat_buffer_setup_hdr_t hdr;
++00108 
++00109         /* The XFER sizes pointer (allocated dynamically) */
++00110         uint16_t *wTxBytes;
++00111 } __attribute__ ((packed));
++00112 typedef struct _ddma_concat_buffer_setup ddma_concat_buffer_setup_t;
++00113 
++00115 struct _ddma_align_buffer_setup {
++00116 #define BS_ALIGN_VAL_HDR_LEN    2
++00117         uint8_t bEndpointAddress;
++00118         uint8_t bAlign;
++00119 } __attribute__ ((packed));
++00120 typedef struct _ddma_align_buffer_setup ddma_align_buffer_setup_t;
++00121 
++00123 struct _tx_fifo_size_setup {
++00124         uint8_t bEndpointAddress;
++00125         uint16_t wDepth;
++00126 } __attribute__ ((packed));
++00127 typedef struct _tx_fifo_size_setup tx_fifo_size_setup_t;
++00128 
++00130 struct _rx_fifo_size_setup {
++00131         uint16_t wDepth;
++00132 } __attribute__ ((packed));
++00133 typedef struct _rx_fifo_size_setup rx_fifo_size_setup_t;
++00134 
++00140 struct cfi_usb_ctrlrequest {
++00141         uint8_t bRequestType;
++00142         uint8_t bRequest;
++00143         uint16_t wValue;
++00144         uint16_t wIndex;
++00145         uint16_t wLength;
++00146         uint8_t *data;
++00147 } UPACKED;
++00148 
++00149 /*---------------------------------------------------------------------------*/
++00150 
++00156 struct cfi_ep {
++00157         /* Entry for the list container */
++00158         dwc_list_link_t lh;
++00159         /* Pointer to the active PCD endpoint structure */
++00160         struct dwc_otg_pcd_ep *ep;
++00161         /* The last descriptor in the chain of DMA descriptors of the endpoint */
++00162         struct dwc_otg_dma_desc *dma_desc_last;
++00163         /* The SG feature value */
++00164         ddma_sg_buffer_setup_t *bm_sg;
++00165         /* The Circular feature value */
++00166         ddma_sg_buffer_setup_t *bm_circ;
++00167         /* The Concatenation feature value */
++00168         ddma_concat_buffer_setup_t *bm_concat;
++00169         /* The Alignment feature value */
++00170         ddma_align_buffer_setup_t *bm_align;
++00171         /* XFER length */
++00172         uint32_t xfer_len;
++00173         /* 
++00174          * Count of DMA descriptors currently used.
++00175          * The total should not exceed the MAX_DMA_DESCS_PER_EP value
++00176          * defined in the dwc_otg_cil.h
++00177          */
++00178         uint32_t desc_count;
++00179 };
++00180 typedef struct cfi_ep cfi_ep_t;
++00181 
++00182 typedef struct cfi_dma_buff {
++00183 #define CFI_IN_BUF_LEN  1024
++00184 #define CFI_OUT_BUF_LEN 1024
++00185         dma_addr_t addr;
++00186         uint8_t *buf;
++00187 } cfi_dma_buff_t;
++00188 
++00189 struct cfiobject;
++00190 
++00199 typedef struct cfi_ops {
++00200         int (*ep_enable) (struct cfiobject * cfi, struct dwc_otg_pcd * pcd,
++00201                           struct dwc_otg_pcd_ep * ep);
++00202         void *(*ep_alloc_buf) (struct cfiobject * cfi, struct dwc_otg_pcd * pcd,
++00203                                struct dwc_otg_pcd_ep * ep, dma_addr_t * dma,
++00204                                unsigned size, gfp_t flags);
++00205         void (*release) (struct cfiobject * cfi);
++00206         int (*ctrl_write_complete) (struct cfiobject * cfi,
++00207                                     struct dwc_otg_pcd * pcd);
++00208         void (*build_descriptors) (struct cfiobject * cfi,
++00209                                    struct dwc_otg_pcd * pcd,
++00210                                    struct dwc_otg_pcd_ep * ep,
++00211                                    dwc_otg_pcd_request_t * req);
++00212 } cfi_ops_t;
++00213 
++00214 struct cfiobject {
++00215         cfi_ops_t ops;
++00216         struct dwc_otg_pcd *pcd;
++00217         struct usb_gadget *gadget;
++00218 
++00219         /* Buffers used to send/receive CFI-related request data */
++00220         cfi_dma_buff_t buf_in;
++00221         cfi_dma_buff_t buf_out;
++00222 
++00223         /* CFI specific Control request wrapper */
++00224         struct cfi_usb_ctrlrequest ctrl_req;
++00225 
++00226         /* The list of active EP's in the PCD of type cfi_ep_t */
++00227         dwc_list_link_t active_eps;
++00228 
++00229         /* This flag shall control the propagation of a specific request
++00230          * to the gadget's processing routines.
++00231          * 0 - no gadget handling
++00232          * 1 - the gadget needs to know about this request (w/o completing a status 
++00233          * phase - just return a 0 to the _setup callback)
++00234          */
++00235         uint8_t need_gadget_att;
++00236 
++00237         /* Flag indicating whether the status IN phase needs to be 
++00238          * completed by the PCD
++00239          */
++00240         uint8_t need_status_in_complete;
++00241 };
++00242 typedef struct cfiobject cfiobject_t;
++00243 
++00244 #define DUMP_MSG
++00245 
++00246 #if defined(DUMP_MSG)
++00247 static inline void dump_msg(const u8 * buf, unsigned int length)
++00248 {
++00249         unsigned int start, num, i;
++00250         char line[52], *p;
++00251 
++00252         if (length >= 512)
++00253                 return;
++00254 
++00255         start = 0;
++00256         while (length > 0) {
++00257                 num = min(length, 16u);
++00258                 p = line;
++00259                 for (i = 0; i < num; ++i) {
++00260                         if (i == 8)
++00261                                 *p++ = ' ';
++00262                         DWC_SPRINTF(p, " %02x", buf[i]);
++00263                         p += 3;
++00264                 }
++00265                 *p = 0;
++00266                 DWC_DEBUG("%6x: %s\n", start, line);
++00267                 buf += num;
++00268                 start += num;
++00269                 length -= num;
++00270         }
++00271 }
++00272 #else
++00273 static inline void dump_msg(const u8 * buf, unsigned int length)
++00274 {
++00275 }
++00276 #endif
++00277 
++00281 static inline struct cfi_ep *get_cfi_ep_by_addr(struct cfiobject *cfi,
++00282                                                 uint8_t addr)
++00283 {
++00284         struct cfi_ep *pcfiep;
++00285         dwc_list_link_t *tmp;
++00286 
++00287         DWC_LIST_FOREACH(tmp, &cfi->active_eps) {
++00288                 pcfiep = DWC_LIST_ENTRY(tmp, struct cfi_ep, lh);
++00289 
++00290                 if (pcfiep->ep->desc->bEndpointAddress == addr) {
++00291                         return pcfiep;
++00292                 }
++00293         }
++00294 
++00295         return NULL;
++00296 }
++00297 
++00302 static inline struct cfi_ep *get_cfi_ep_by_pcd_ep(struct cfiobject *cfi,
++00303                                                   struct dwc_otg_pcd_ep *ep)
++00304 {
++00305         struct cfi_ep *pcfiep = NULL;
++00306         dwc_list_link_t *tmp;
++00307 
++00308         DWC_LIST_FOREACH(tmp, &cfi->active_eps) {
++00309                 pcfiep = DWC_LIST_ENTRY(tmp, struct cfi_ep, lh);
++00310                 if (pcfiep->ep == ep) {
++00311                         return pcfiep;
++00312                 }
++00313         }
++00314         return NULL;
++00315 }
++00316 
++00317 int cfi_setup(struct dwc_otg_pcd *pcd, struct cfi_usb_ctrlrequest *ctrl);
++00318 
++00319 #endif                          /* (__DWC_OTG_CFI_H__) */
++
Generated on Tue May 5 02:22:48 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__cfi_8h.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__cfi_8h.html 2013-07-26 19:31:20.000000000 +0000 +@@ -0,0 +1,302 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_cfi.h File Reference ++ ++ ++ ++ ++
++
++
++
++

dwc_otg_cfi.h File Reference

This file contains the CFI related OTG PCD specific common constants, interfaces (functions and macros) and data structures. More... ++

++#include "dwc_otg_pcd.h"
++#include "dwc_cfi_common.h"
++ ++

++Go to the source code of this file. ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++

Data Structures

struct  _ddma_sg_buffer_setup
 Descriptor DMA SG Buffer setup structure (SG buffer). More...
struct  _ddma_concat_buffer_setup_hdr
 Descriptor DMA Concatenation Buffer setup structure. More...
struct  _ddma_concat_buffer_setup
 Descriptor DMA Concatenation Buffer setup structure. More...
struct  _ddma_align_buffer_setup
 Descriptor DMA Alignment Buffer setup structure. More...
struct  _tx_fifo_size_setup
 Transmit FIFO Size setup structure. More...
struct  _rx_fifo_size_setup
 Transmit FIFO Size setup structure. More...
struct  cfi_usb_ctrlrequest
 struct cfi_usb_ctrlrequest - the CFI implementation of the struct usb_ctrlrequest This structure encapsulates the standard usb_ctrlrequest and adds a pointer to the data returned in the data stage of a 3-stage Control Write requests. More...
struct  cfi_ep
 The CFI wrapper of the enabled and activated dwc_otg_pcd_ep structures. More...
struct  cfi_dma_buff
struct  cfi_ops
 This is the interface for the CFI operations. More...
struct  cfiobject

Defines

++#define __DWC_OTG_CFI_H__
++#define FT_ID_DMA_MODE   0x0001
 This is a request for all Core Features.
++#define FT_ID_DMA_BUFFER_SETUP   0x0002
++#define FT_ID_DMA_BUFF_ALIGN   0x0003
++#define FT_ID_DMA_CONCAT_SETUP   0x0004
++#define FT_ID_DMA_CIRCULAR   0x0005
++#define FT_ID_THRESHOLD_SETUP   0x0006
++#define FT_ID_DFIFO_DEPTH   0x0007
++#define FT_ID_TX_FIFO_DEPTH   0x0008
++#define FT_ID_RX_FIFO_DEPTH   0x0009
++#define CFI_INFO_DEF
++#define CFI_INFO(fmt...)   DWC_PRINTF("CFI: " fmt);
#define min(x, y)
#define max(x, y)
++#define BS_SG_VAL_DESC_LEN   6
++#define BS_CONCAT_VAL_HDR_LEN   4
++#define BS_ALIGN_VAL_HDR_LEN   2
++#define CFI_IN_BUF_LEN   1024
++#define CFI_OUT_BUF_LEN   1024
++#define DUMP_MSG

Typedefs

++typedef _ddma_sg_buffer_setup ddma_sg_buffer_setup_t
++typedef _ddma_concat_buffer_setup_hdr ddma_concat_buffer_setup_hdr_t
++typedef _ddma_concat_buffer_setup ddma_concat_buffer_setup_t
++typedef _ddma_align_buffer_setup ddma_align_buffer_setup_t
++typedef _tx_fifo_size_setup tx_fifo_size_setup_t
++typedef _rx_fifo_size_setup rx_fifo_size_setup_t
++typedef cfi_ep cfi_ep_t
++typedef cfi_dma_buff cfi_dma_buff_t
typedef cfi_ops cfi_ops_t
 This is the interface for the CFI operations.
++typedef cfiobject cfiobject_t

Functions

++static void dump_msg (const u8 *buf, unsigned int length)
++static struct cfi_ep * get_cfi_ep_by_addr (struct cfiobject *cfi, uint8_t addr)
 This function returns a pointer to cfi_ep_t object with the addr address.
++static struct cfi_ep * get_cfi_ep_by_pcd_ep (struct cfiobject *cfi, struct dwc_otg_pcd_ep *ep)
 This function returns a pointer to cfi_ep_t object that matches the dwc_otg_pcd_ep object.
++int cfi_setup (struct dwc_otg_pcd *pcd, struct cfi_usb_ctrlrequest *ctrl)

Variables

_ddma_sg_buffer_setup packed
 Descriptor DMA SG Buffer setup structure (SG buffer).
++_ddma_concat_buffer_setup_hdr packed
 Descriptor DMA Concatenation Buffer setup structure.
++_ddma_concat_buffer_setup packed
 Descriptor DMA Concatenation Buffer setup structure.
++_ddma_align_buffer_setup packed
 Descriptor DMA Alignment Buffer setup structure.
++_tx_fifo_size_setup packed
 Transmit FIFO Size setup structure.
++_rx_fifo_size_setup packed
 Transmit FIFO Size setup structure.
++cfi_usb_ctrlrequest UPACKED
 struct cfi_usb_ctrlrequest - the CFI implementation of the struct usb_ctrlrequest This structure encapsulates the standard usb_ctrlrequest and adds a pointer to the data returned in the data stage of a 3-stage Control Write requests.
++

Detailed Description

++This file contains the CFI related OTG PCD specific common constants, interfaces (functions and macros) and data structures. ++

++ ++

++Definition in file dwc_otg_cfi.h.

Define Documentation

++ ++
++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
#define min (x,
y   ) 
++
++
++ ++

++Value:

({ \
++        x < y ? x : y; })
++
++

++Definition at line 67 of file dwc_otg_cfi.h. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
#define max (x,
y   ) 
++
++
++ ++

++Value:

({ \
++        x > y ? x : y; })
++
++

++Definition at line 70 of file dwc_otg_cfi.h. ++

++

++

Typedef Documentation

++ ++
++
++ ++ ++ ++ ++
typedef struct cfi_ops cfi_ops_t
++
++
++ ++

++This is the interface for the CFI operations. ++

++

Parameters:
++ ++ ++ ++ ++
ep_enable Called when any endpoint is enabled and activated.
release Called when the CFI object is released and it needs to correctly deallocate the dynamic memory
ctrl_write_complete Called when the data stage of the request is complete
++
++ ++
++

++

Variable Documentation

++ ++
++
++ ++ ++ ++ ++
struct _ddma_sg_buffer_setup packed
++
++
++ ++

++Descriptor DMA SG Buffer setup structure (SG buffer). ++

++This structure is also used for setting up a buffer for Circular DDMA. ++

++

++

Generated on Tue May 5 02:22:48 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__cil_8c-source.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__cil_8c-source.html 2013-07-26 19:31:20.000000000 +0000 +@@ -0,0 +1,4922 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_cil.c Source File ++ ++ ++ ++ ++
++
++
++
++

dwc_otg_cil.c

Go to the documentation of this file.
00001 /* ==========================================================================
++00002  * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_cil.c $
++00003  * $Revision: #159 $
++00004  * $Date: 2009/04/21 $
++00005  * $Change: 1237465 $
++00006  *
++00007  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
++00008  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
++00009  * otherwise expressly agreed to in writing between Synopsys and you.
++00010  * 
++00011  * The Software IS NOT an item of Licensed Software or Licensed Product under
++00012  * any End User Software License Agreement or Agreement for Licensed Product
++00013  * with Synopsys or any supplement thereto. You are permitted to use and
++00014  * redistribute this Software in source and binary forms, with or without
++00015  * modification, provided that redistributions of source code must retain this
++00016  * notice. You may not view, use, disclose, copy or distribute this file or
++00017  * any information contained herein except pursuant to this license grant from
++00018  * Synopsys. If you do not agree with this notice, including the disclaimer
++00019  * below, then you are not authorized to use the Software.
++00020  * 
++00021  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
++00022  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++00023  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++00024  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
++00025  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++00026  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
++00027  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
++00028  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
++00029  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
++00030  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
++00031  * DAMAGE.
++00032  * ========================================================================== */
++00033 
++00060 #include "dwc_os.h"
++00061 #include "dwc_otg_regs.h"
++00062 #include "dwc_otg_cil.h"
++00063 
++00064 static int dwc_otg_setup_params(dwc_otg_core_if_t * core_if);
++00065 
++00078 dwc_otg_core_if_t *dwc_otg_cil_init(const uint32_t * reg_base_addr)
++00079 {
++00080         dwc_otg_core_if_t *core_if = 0;
++00081         dwc_otg_dev_if_t *dev_if = 0;
++00082         dwc_otg_host_if_t *host_if = 0;
++00083         uint8_t *reg_base = (uint8_t *) reg_base_addr;
++00084         int i = 0;
++00085 
++00086         DWC_DEBUGPL(DBG_CILV, "%s(%p)\n", __func__, reg_base_addr);
++00087 
++00088         core_if = dwc_alloc(sizeof(dwc_otg_core_if_t));
++00089 
++00090         if (core_if == 0) {
++00091                 DWC_DEBUGPL(DBG_CIL,
++00092                             "Allocation of dwc_otg_core_if_t failed\n");
++00093                 return 0;
++00094         }
++00095         core_if->core_global_regs = (dwc_otg_core_global_regs_t *) reg_base;
++00096 
++00097         /*
++00098          * Allocate the Device Mode structures.
++00099          */
++00100         dev_if = dwc_alloc(sizeof(dwc_otg_dev_if_t));
++00101 
++00102         if (dev_if == 0) {
++00103                 DWC_DEBUGPL(DBG_CIL, "Allocation of dwc_otg_dev_if_t failed\n");
++00104                 dwc_free(core_if);
++00105                 return 0;
++00106         }
++00107 
++00108         dev_if->dev_global_regs =
++00109             (dwc_otg_device_global_regs_t *) (reg_base +
++00110                                               DWC_DEV_GLOBAL_REG_OFFSET);
++00111 
++00112         for (i = 0; i < MAX_EPS_CHANNELS; i++) {
++00113                 dev_if->in_ep_regs[i] = (dwc_otg_dev_in_ep_regs_t *)
++00114                     (reg_base + DWC_DEV_IN_EP_REG_OFFSET +
++00115                      (i * DWC_EP_REG_OFFSET));
++00116 
++00117                 dev_if->out_ep_regs[i] = (dwc_otg_dev_out_ep_regs_t *)
++00118                     (reg_base + DWC_DEV_OUT_EP_REG_OFFSET +
++00119                      (i * DWC_EP_REG_OFFSET));
++00120                 DWC_DEBUGPL(DBG_CILV, "in_ep_regs[%d]->diepctl=%p\n",
++00121                             i, &dev_if->in_ep_regs[i]->diepctl);
++00122                 DWC_DEBUGPL(DBG_CILV, "out_ep_regs[%d]->doepctl=%p\n",
++00123                             i, &dev_if->out_ep_regs[i]->doepctl);
++00124         }
++00125 
++00126         dev_if->speed = 0;      // unknown
++00127 
++00128         core_if->dev_if = dev_if;
++00129 
++00130         /*
++00131          * Allocate the Host Mode structures.
++00132          */
++00133         host_if = dwc_alloc(sizeof(dwc_otg_host_if_t));
++00134 
++00135         if (host_if == 0) {
++00136                 DWC_DEBUGPL(DBG_CIL,
++00137                             "Allocation of dwc_otg_host_if_t failed\n");
++00138                 dwc_free(dev_if);
++00139                 dwc_free(core_if);
++00140                 return 0;
++00141         }
++00142 
++00143         host_if->host_global_regs = (dwc_otg_host_global_regs_t *)
++00144             (reg_base + DWC_OTG_HOST_GLOBAL_REG_OFFSET);
++00145 
++00146         host_if->hprt0 =
++00147             (uint32_t *) (reg_base + DWC_OTG_HOST_PORT_REGS_OFFSET);
++00148 
++00149         for (i = 0; i < MAX_EPS_CHANNELS; i++) {
++00150                 host_if->hc_regs[i] = (dwc_otg_hc_regs_t *)
++00151                     (reg_base + DWC_OTG_HOST_CHAN_REGS_OFFSET +
++00152                      (i * DWC_OTG_CHAN_REGS_OFFSET));
++00153                 DWC_DEBUGPL(DBG_CILV, "hc_reg[%d]->hcchar=%p\n",
++00154                             i, &host_if->hc_regs[i]->hcchar);
++00155         }
++00156 
++00157         host_if->num_host_channels = MAX_EPS_CHANNELS;
++00158         core_if->host_if = host_if;
++00159 
++00160         for (i = 0; i < MAX_EPS_CHANNELS; i++) {
++00161                 core_if->data_fifo[i] =
++00162                     (uint32_t *) (reg_base + DWC_OTG_DATA_FIFO_OFFSET +
++00163                                   (i * DWC_OTG_DATA_FIFO_SIZE));
++00164                 DWC_DEBUGPL(DBG_CILV, "data_fifo[%d]=0x%08x\n",
++00165                             i, (unsigned)core_if->data_fifo[i]);
++00166         }
++00167 
++00168         core_if->pcgcctl = (uint32_t *) (reg_base + DWC_OTG_PCGCCTL_OFFSET);
++00169 
++00170         /* Initiate lx_state to L3 disconnected state */
++00171         core_if->lx_state = DWC_OTG_L3;
++00172         /*
++00173          * Store the contents of the hardware configuration registers here for
++00174          * easy access later.
++00175          */
++00176         core_if->hwcfg1.d32 =
++00177             dwc_read_reg32(&core_if->core_global_regs->ghwcfg1);
++00178         core_if->hwcfg2.d32 =
++00179             dwc_read_reg32(&core_if->core_global_regs->ghwcfg2);
++00180         core_if->hwcfg3.d32 =
++00181             dwc_read_reg32(&core_if->core_global_regs->ghwcfg3);
++00182         core_if->hwcfg4.d32 =
++00183             dwc_read_reg32(&core_if->core_global_regs->ghwcfg4);
++00184 
++00185         DWC_DEBUGPL(DBG_CILV, "hwcfg1=%08x\n", core_if->hwcfg1.d32);
++00186         DWC_DEBUGPL(DBG_CILV, "hwcfg2=%08x\n", core_if->hwcfg2.d32);
++00187         DWC_DEBUGPL(DBG_CILV, "hwcfg3=%08x\n", core_if->hwcfg3.d32);
++00188         DWC_DEBUGPL(DBG_CILV, "hwcfg4=%08x\n", core_if->hwcfg4.d32);
++00189 
++00190         core_if->hcfg.d32 =
++00191             dwc_read_reg32(&core_if->host_if->host_global_regs->hcfg);
++00192         core_if->dcfg.d32 =
++00193             dwc_read_reg32(&core_if->dev_if->dev_global_regs->dcfg);
++00194 
++00195         DWC_DEBUGPL(DBG_CILV, "hcfg=%08x\n", core_if->hcfg.d32);
++00196         DWC_DEBUGPL(DBG_CILV, "dcfg=%08x\n", core_if->dcfg.d32);
++00197 
++00198         DWC_DEBUGPL(DBG_CILV, "op_mode=%0x\n", core_if->hwcfg2.b.op_mode);
++00199         DWC_DEBUGPL(DBG_CILV, "arch=%0x\n", core_if->hwcfg2.b.architecture);
++00200         DWC_DEBUGPL(DBG_CILV, "num_dev_ep=%d\n", core_if->hwcfg2.b.num_dev_ep);
++00201         DWC_DEBUGPL(DBG_CILV, "num_host_chan=%d\n",
++00202                     core_if->hwcfg2.b.num_host_chan);
++00203         DWC_DEBUGPL(DBG_CILV, "nonperio_tx_q_depth=0x%0x\n",
++00204                     core_if->hwcfg2.b.nonperio_tx_q_depth);
++00205         DWC_DEBUGPL(DBG_CILV, "host_perio_tx_q_depth=0x%0x\n",
++00206                     core_if->hwcfg2.b.host_perio_tx_q_depth);
++00207         DWC_DEBUGPL(DBG_CILV, "dev_token_q_depth=0x%0x\n",
++00208                     core_if->hwcfg2.b.dev_token_q_depth);
++00209 
++00210         DWC_DEBUGPL(DBG_CILV, "Total FIFO SZ=%d\n",
++00211                     core_if->hwcfg3.b.dfifo_depth);
++00212         DWC_DEBUGPL(DBG_CILV, "xfer_size_cntr_width=%0x\n",
++00213                     core_if->hwcfg3.b.xfer_size_cntr_width);
++00214 
++00215         /*
++00216          * Set the SRP sucess bit for FS-I2c
++00217          */
++00218         core_if->srp_success = 0;
++00219         core_if->srp_timer_started = 0;
++00220 
++00221         /*
++00222          * Create new workqueue and init works
++00223          */
++00224         core_if->wq_otg = DWC_WORKQ_ALLOC("dwc_otg");
++00225         if (core_if->wq_otg == 0) {
++00226                 DWC_WARN("DWC_WORKQ_ALLOC failed\n");
++00227                 dwc_free(host_if);
++00228                 dwc_free(dev_if);
++00229                 dwc_free(core_if);
++00230                 return 0;
++00231         }
++00232 
++00233         core_if->snpsid = dwc_read_reg32(&core_if->core_global_regs->gsnpsid);
++00234 
++00235         DWC_PRINTF("Core Release: %x.%x%x%x\n",
++00236                    (core_if->snpsid >> 12 & 0xF),
++00237                    (core_if->snpsid >> 8 & 0xF),
++00238                    (core_if->snpsid >> 4 & 0xF), (core_if->snpsid & 0xF));
++00239 
++00240         core_if->wkp_timer = DWC_TIMER_ALLOC("Wake Up Timer",
++00241                                              w_wakeup_detected, core_if);
++00242         if (core_if->wkp_timer == 0) {
++00243                 DWC_WARN("DWC_TIMER_ALLOC failed\n");
++00244                 dwc_free(host_if);
++00245                 dwc_free(dev_if);
++00246                 DWC_WORKQ_FREE(core_if->wq_otg);
++00247                 dwc_free(core_if);
++00248                 return 0;
++00249         }
++00250 
++00251         if (dwc_otg_setup_params(core_if)) {
++00252                 DWC_WARN("Error while setting core params\n");
++00253         }
++00254 
++00255         return core_if;
++00256 }
++00257 
++00265 void dwc_otg_cil_remove(dwc_otg_core_if_t * core_if)
++00266 {
++00267         /* Disable all interrupts */
++00268         dwc_modify_reg32(&core_if->core_global_regs->gahbcfg, 1, 0);
++00269         dwc_write_reg32(&core_if->core_global_regs->gintmsk, 0);
++00270 
++00271         if (core_if->wq_otg) {
++00272                 DWC_WORKQ_WAIT_WORK_DONE(core_if->wq_otg, 500);
++00273                 DWC_WORKQ_FREE(core_if->wq_otg);
++00274         }
++00275         if (core_if->dev_if) {
++00276                 dwc_free(core_if->dev_if);
++00277         }
++00278         if (core_if->host_if) {
++00279                 dwc_free(core_if->host_if);
++00280         }
++00281         dwc_free(core_if);
++00282         DWC_TIMER_FREE(core_if->wkp_timer);
++00283         DWC_FREE(core_if->core_params);
++00284 }
++00285 
++00292 void dwc_otg_enable_global_interrupts(dwc_otg_core_if_t * core_if)
++00293 {
++00294         gahbcfg_data_t ahbcfg = {.d32 = 0 };
++00295         ahbcfg.b.glblintrmsk = 1;       /* Enable interrupts */
++00296         dwc_modify_reg32(&core_if->core_global_regs->gahbcfg, 0, ahbcfg.d32);
++00297 }
++00298 
++00305 void dwc_otg_disable_global_interrupts(dwc_otg_core_if_t * core_if)
++00306 {
++00307         gahbcfg_data_t ahbcfg = {.d32 = 0 };
++00308         ahbcfg.b.glblintrmsk = 1;       /* Enable interrupts */
++00309         dwc_modify_reg32(&core_if->core_global_regs->gahbcfg, ahbcfg.d32, 0);
++00310 }
++00311 
++00319 static void dwc_otg_enable_common_interrupts(dwc_otg_core_if_t * core_if)
++00320 {
++00321         dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
++00322         gintmsk_data_t intr_mask = {.d32 = 0 };
++00323 
++00324         /* Clear any pending OTG Interrupts */
++00325         dwc_write_reg32(&global_regs->gotgint, 0xFFFFFFFF);
++00326 
++00327         /* Clear any pending interrupts */
++00328         dwc_write_reg32(&global_regs->gintsts, 0xFFFFFFFF);
++00329 
++00330         /* 
++00331          * Enable the interrupts in the GINTMSK. 
++00332          */
++00333         intr_mask.b.modemismatch = 1;
++00334         intr_mask.b.otgintr = 1;
++00335 
++00336         if (!core_if->dma_enable) {
++00337                 intr_mask.b.rxstsqlvl = 1;
++00338         }
++00339 
++00340         intr_mask.b.conidstschng = 1;
++00341         intr_mask.b.wkupintr = 1;
++00342         intr_mask.b.disconnect = 1;
++00343         intr_mask.b.usbsuspend = 1;
++00344         intr_mask.b.sessreqintr = 1;
++00345 #ifdef CONFIG_USB_DWC_OTG_LPM
++00346         if (core_if->core_params->lpm_enable) {
++00347                 intr_mask.b.lpmtranrcvd = 1;
++00348         }
++00349 #endif
++00350         dwc_write_reg32(&global_regs->gintmsk, intr_mask.d32);
++00351 }
++00352 
++00357 static void init_fslspclksel(dwc_otg_core_if_t * core_if)
++00358 {
++00359         uint32_t val;
++00360         hcfg_data_t hcfg;
++00361 
++00362         if (((core_if->hwcfg2.b.hs_phy_type == 2) &&
++00363              (core_if->hwcfg2.b.fs_phy_type == 1) &&
++00364              (core_if->core_params->ulpi_fs_ls)) ||
++00365             (core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS)) {
++00366                 /* Full speed PHY */
++00367                 val = DWC_HCFG_48_MHZ;
++00368         } else {
++00369                 /* High speed PHY running at full speed or high speed */
++00370                 val = DWC_HCFG_30_60_MHZ;
++00371         }
++00372 
++00373         DWC_DEBUGPL(DBG_CIL, "Initializing HCFG.FSLSPClkSel to 0x%1x\n", val);
++00374         hcfg.d32 = dwc_read_reg32(&core_if->host_if->host_global_regs->hcfg);
++00375         hcfg.b.fslspclksel = val;
++00376         dwc_write_reg32(&core_if->host_if->host_global_regs->hcfg, hcfg.d32);
++00377 }
++00378 
++00383 static void init_devspd(dwc_otg_core_if_t * core_if)
++00384 {
++00385         uint32_t val;
++00386         dcfg_data_t dcfg;
++00387 
++00388         if (((core_if->hwcfg2.b.hs_phy_type == 2) &&
++00389              (core_if->hwcfg2.b.fs_phy_type == 1) &&
++00390              (core_if->core_params->ulpi_fs_ls)) ||
++00391             (core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS)) {
++00392                 /* Full speed PHY */
++00393                 val = 0x3;
++00394         } else if (core_if->core_params->speed == DWC_SPEED_PARAM_FULL) {
++00395                 /* High speed PHY running at full speed */
++00396                 val = 0x1;
++00397         } else {
++00398                 /* High speed PHY running at high speed */
++00399                 val = 0x0;
++00400         }
++00401 
++00402         DWC_DEBUGPL(DBG_CIL, "Initializing DCFG.DevSpd to 0x%1x\n", val);
++00403 
++00404         dcfg.d32 = dwc_read_reg32(&core_if->dev_if->dev_global_regs->dcfg);
++00405         dcfg.b.devspd = val;
++00406         dwc_write_reg32(&core_if->dev_if->dev_global_regs->dcfg, dcfg.d32);
++00407 }
++00408 
++00415 static uint32_t calc_num_in_eps(dwc_otg_core_if_t * core_if)
++00416 {
++00417         uint32_t num_in_eps = 0;
++00418         uint32_t num_eps = core_if->hwcfg2.b.num_dev_ep;
++00419         uint32_t hwcfg1 = core_if->hwcfg1.d32 >> 3;
++00420         uint32_t num_tx_fifos = core_if->hwcfg4.b.num_in_eps;
++00421         int i;
++00422 
++00423         for (i = 0; i < num_eps; ++i) {
++00424                 if (!(hwcfg1 & 0x1))
++00425                         num_in_eps++;
++00426 
++00427                 hwcfg1 >>= 2;
++00428         }
++00429 
++00430         if (core_if->hwcfg4.b.ded_fifo_en) {
++00431                 num_in_eps =
++00432                     (num_in_eps > num_tx_fifos) ? num_tx_fifos : num_in_eps;
++00433         }
++00434 
++00435         return num_in_eps;
++00436 }
++00437 
++00444 static uint32_t calc_num_out_eps(dwc_otg_core_if_t * core_if)
++00445 {
++00446         uint32_t num_out_eps = 0;
++00447         uint32_t num_eps = core_if->hwcfg2.b.num_dev_ep;
++00448         uint32_t hwcfg1 = core_if->hwcfg1.d32 >> 2;
++00449         int i;
++00450 
++00451         for (i = 0; i < num_eps; ++i) {
++00452                 if (!(hwcfg1 & 0x1))
++00453                         num_out_eps++;
++00454 
++00455                 hwcfg1 >>= 2;
++00456         }
++00457         return num_out_eps;
++00458 }
++00459 
++00467 void dwc_otg_core_init(dwc_otg_core_if_t * core_if)
++00468 {
++00469         int i = 0;
++00470         dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
++00471         dwc_otg_dev_if_t *dev_if = core_if->dev_if;
++00472         gahbcfg_data_t ahbcfg = {.d32 = 0 };
++00473         gusbcfg_data_t usbcfg = {.d32 = 0 };
++00474         gi2cctl_data_t i2cctl = {.d32 = 0 };
++00475 
++00476         DWC_DEBUGPL(DBG_CILV, "dwc_otg_core_init(%p)\n", core_if);
++00477 
++00478         /* Common Initialization */
++00479 
++00480         usbcfg.d32 = dwc_read_reg32(&global_regs->gusbcfg);
++00481 
++00482         /* Program the ULPI External VBUS bit if needed */
++00483         usbcfg.b.ulpi_ext_vbus_drv =
++00484             (core_if->core_params->phy_ulpi_ext_vbus ==
++00485              DWC_PHY_ULPI_EXTERNAL_VBUS) ? 1 : 0;
++00486 
++00487         /* Set external TS Dline pulsing */
++00488         usbcfg.b.term_sel_dl_pulse =
++00489             (core_if->core_params->ts_dline == 1) ? 1 : 0;
++00490         dwc_write_reg32(&global_regs->gusbcfg, usbcfg.d32);
++00491 
++00492         /* Reset the Controller */
++00493         dwc_otg_core_reset(core_if);
++00494 
++00495         /* Initialize parameters from Hardware configuration registers. */
++00496         dev_if->num_in_eps = calc_num_in_eps(core_if);
++00497         dev_if->num_out_eps = calc_num_out_eps(core_if);
++00498 
++00499         DWC_DEBUGPL(DBG_CIL, "num_dev_perio_in_ep=%d\n",
++00500                     core_if->hwcfg4.b.num_dev_perio_in_ep);
++00501 
++00502         for (i = 0; i < core_if->hwcfg4.b.num_dev_perio_in_ep; i++) {
++00503                 dev_if->perio_tx_fifo_size[i] =
++00504                     dwc_read_reg32(&global_regs->dptxfsiz_dieptxf[i]) >> 16;
++00505                 DWC_DEBUGPL(DBG_CIL, "Periodic Tx FIFO SZ #%d=0x%0x\n",
++00506                             i, dev_if->perio_tx_fifo_size[i]);
++00507         }
++00508 
++00509         for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {
++00510                 dev_if->tx_fifo_size[i] =
++00511                     dwc_read_reg32(&global_regs->dptxfsiz_dieptxf[i]) >> 16;
++00512                 DWC_DEBUGPL(DBG_CIL, "Tx FIFO SZ #%d=0x%0x\n",
++00513                             i, dev_if->perio_tx_fifo_size[i]);
++00514         }
++00515 
++00516         core_if->total_fifo_size = core_if->hwcfg3.b.dfifo_depth;
++00517         core_if->rx_fifo_size = dwc_read_reg32(&global_regs->grxfsiz);
++00518         core_if->nperio_tx_fifo_size =
++00519             dwc_read_reg32(&global_regs->gnptxfsiz) >> 16;
++00520 
++00521         DWC_DEBUGPL(DBG_CIL, "Total FIFO SZ=%d\n", core_if->total_fifo_size);
++00522         DWC_DEBUGPL(DBG_CIL, "Rx FIFO SZ=%d\n", core_if->rx_fifo_size);
++00523         DWC_DEBUGPL(DBG_CIL, "NP Tx FIFO SZ=%d\n",
++00524                     core_if->nperio_tx_fifo_size);
++00525 
++00526         /* This programming sequence needs to happen in FS mode before any other
++00527          * programming occurs */
++00528         if ((core_if->core_params->speed == DWC_SPEED_PARAM_FULL) &&
++00529             (core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS)) {
++00530                 /* If FS mode with FS PHY */
++00531 
++00532                 /* core_init() is now called on every switch so only call the
++00533                  * following for the first time through. */
++00534                 if (!core_if->phy_init_done) {
++00535                         core_if->phy_init_done = 1;
++00536                         DWC_DEBUGPL(DBG_CIL, "FS_PHY detected\n");
++00537                         usbcfg.d32 = dwc_read_reg32(&global_regs->gusbcfg);
++00538                         usbcfg.b.physel = 1;
++00539                         dwc_write_reg32(&global_regs->gusbcfg, usbcfg.d32);
++00540 
++00541                         /* Reset after a PHY select */
++00542                         dwc_otg_core_reset(core_if);
++00543                 }
++00544 
++00545                 /* Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS.      Also
++00546                  * do this on HNP Dev/Host mode switches (done in dev_init and
++00547                  * host_init). */
++00548                 if (dwc_otg_is_host_mode(core_if)) {
++00549                         init_fslspclksel(core_if);
++00550                 } else {
++00551                         init_devspd(core_if);
++00552                 }
++00553 
++00554                 if (core_if->core_params->i2c_enable) {
++00555                         DWC_DEBUGPL(DBG_CIL, "FS_PHY Enabling I2c\n");
++00556                         /* Program GUSBCFG.OtgUtmifsSel to I2C */
++00557                         usbcfg.d32 = dwc_read_reg32(&global_regs->gusbcfg);
++00558                         usbcfg.b.otgutmifssel = 1;
++00559                         dwc_write_reg32(&global_regs->gusbcfg, usbcfg.d32);
++00560 
++00561                         /* Program GI2CCTL.I2CEn */
++00562                         i2cctl.d32 = dwc_read_reg32(&global_regs->gi2cctl);
++00563                         i2cctl.b.i2cdevaddr = 1;
++00564                         i2cctl.b.i2cen = 0;
++00565                         dwc_write_reg32(&global_regs->gi2cctl, i2cctl.d32);
++00566                         i2cctl.b.i2cen = 1;
++00567                         dwc_write_reg32(&global_regs->gi2cctl, i2cctl.d32);
++00568                 }
++00569 
++00570         } /* endif speed == DWC_SPEED_PARAM_FULL */
++00571         else {
++00572                 /* High speed PHY. */
++00573                 if (!core_if->phy_init_done) {
++00574                         core_if->phy_init_done = 1;
++00575                         /* HS PHY parameters.  These parameters are preserved
++00576                          * during soft reset so only program the first time.  Do
++00577                          * a soft reset immediately after setting phyif.  */
++00578                         usbcfg.b.ulpi_utmi_sel = core_if->core_params->phy_type;
++00579                         if (usbcfg.b.ulpi_utmi_sel == 1) {
++00580                                 /* ULPI interface */
++00581                                 usbcfg.b.phyif = 0;
++00582                                 usbcfg.b.ddrsel =
++00583                                     core_if->core_params->phy_ulpi_ddr;
++00584                         } else {
++00585                                 /* UTMI+ interface */
++00586                                 if (core_if->core_params->phy_utmi_width == 16) {
++00587                                         usbcfg.b.phyif = 1;
++00588 
++00589                                 } else {
++00590                                         usbcfg.b.phyif = 0;
++00591                                 }
++00592 
++00593                         }
++00594 
++00595                         dwc_write_reg32(&global_regs->gusbcfg, usbcfg.d32);
++00596                         /* Reset after setting the PHY parameters */
++00597                         dwc_otg_core_reset(core_if);
++00598                 }
++00599         }
++00600 
++00601         if ((core_if->hwcfg2.b.hs_phy_type == 2) &&
++00602             (core_if->hwcfg2.b.fs_phy_type == 1) &&
++00603             (core_if->core_params->ulpi_fs_ls)) {
++00604                 DWC_DEBUGPL(DBG_CIL, "Setting ULPI FSLS\n");
++00605                 usbcfg.d32 = dwc_read_reg32(&global_regs->gusbcfg);
++00606                 usbcfg.b.ulpi_fsls = 1;
++00607                 usbcfg.b.ulpi_clk_sus_m = 1;
++00608                 dwc_write_reg32(&global_regs->gusbcfg, usbcfg.d32);
++00609         } else {
++00610                 usbcfg.d32 = dwc_read_reg32(&global_regs->gusbcfg);
++00611                 usbcfg.b.ulpi_fsls = 0;
++00612                 usbcfg.b.ulpi_clk_sus_m = 0;
++00613                 dwc_write_reg32(&global_regs->gusbcfg, usbcfg.d32);
++00614         }
++00615 
++00616         /* Program the GAHBCFG Register. */
++00617         switch (core_if->hwcfg2.b.architecture) {
++00618 
++00619         case DWC_SLAVE_ONLY_ARCH:
++00620                 DWC_DEBUGPL(DBG_CIL, "Slave Only Mode\n");
++00621                 ahbcfg.b.nptxfemplvl_txfemplvl =
++00622                     DWC_GAHBCFG_TXFEMPTYLVL_HALFEMPTY;
++00623                 ahbcfg.b.ptxfemplvl = DWC_GAHBCFG_TXFEMPTYLVL_HALFEMPTY;
++00624                 core_if->dma_enable = 0;
++00625                 core_if->dma_desc_enable = 0;
++00626                 break;
++00627 
++00628         case DWC_EXT_DMA_ARCH:
++00629                 DWC_DEBUGPL(DBG_CIL, "External DMA Mode\n");
++00630                 {
++00631                         uint8_t brst_sz = core_if->core_params->dma_burst_size;
++00632                         ahbcfg.b.hburstlen = 0;
++00633                         while (brst_sz > 1) {
++00634                                 ahbcfg.b.hburstlen++;
++00635                                 brst_sz >>= 1;
++00636                         }
++00637                 }
++00638                 core_if->dma_enable = (core_if->core_params->dma_enable != 0);
++00639                 core_if->dma_desc_enable =
++00640                     (core_if->core_params->dma_desc_enable != 0);
++00641                 break;
++00642 
++00643         case DWC_INT_DMA_ARCH:
++00644                 DWC_DEBUGPL(DBG_CIL, "Internal DMA Mode\n");
++00645                 ahbcfg.b.hburstlen = DWC_GAHBCFG_INT_DMA_BURST_INCR;
++00646                 core_if->dma_enable = (core_if->core_params->dma_enable != 0);
++00647                 core_if->dma_desc_enable =
++00648                     (core_if->core_params->dma_desc_enable != 0);
++00649                 break;
++00650 
++00651         }
++00652         if (core_if->dma_enable) {
++00653                 if (core_if->dma_desc_enable) {
++00654                         DWC_PRINTF("Using Descriptor DMA mode\n");
++00655                 } else {
++00656                         DWC_PRINTF("Using Buffer DMA mode\n");
++00657 
++00658                 }
++00659         } else {
++00660                 DWC_PRINTF("Using Slave mode\n");
++00661                 core_if->dma_desc_enable = 0;
++00662         }
++00663         
++00664         ahbcfg.b.dmaenable = core_if->dma_enable;
++00665         dwc_write_reg32(&global_regs->gahbcfg, ahbcfg.d32);
++00666 
++00667         core_if->en_multiple_tx_fifo = core_if->hwcfg4.b.ded_fifo_en;
++00668 
++00669         core_if->pti_enh_enable = core_if->core_params->pti_enable != 0;
++00670         core_if->multiproc_int_enable = core_if->core_params->mpi_enable;
++00671         DWC_PRINTF("Periodic Transfer Interrupt Enhancement - %s\n",
++00672                    ((core_if->pti_enh_enable) ? "enabled" : "disabled"));
++00673         DWC_PRINTF("Multiprocessor Interrupt Enhancement - %s\n",
++00674                    ((core_if->multiproc_int_enable) ? "enabled" : "disabled"));
++00675 
++00676         /* 
++00677          * Program the GUSBCFG register. 
++00678          */
++00679         usbcfg.d32 = dwc_read_reg32(&global_regs->gusbcfg);
++00680 
++00681         switch (core_if->hwcfg2.b.op_mode) {
++00682         case DWC_MODE_HNP_SRP_CAPABLE:
++00683                 usbcfg.b.hnpcap = (core_if->core_params->otg_cap ==
++00684                                    DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE);
++00685                 usbcfg.b.srpcap = (core_if->core_params->otg_cap !=
++00686                                    DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE);
++00687                 break;
++00688 
++00689         case DWC_MODE_SRP_ONLY_CAPABLE:
++00690                 usbcfg.b.hnpcap = 0;
++00691                 usbcfg.b.srpcap = (core_if->core_params->otg_cap !=
++00692                                    DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE);
++00693                 break;
++00694 
++00695         case DWC_MODE_NO_HNP_SRP_CAPABLE:
++00696                 usbcfg.b.hnpcap = 0;
++00697                 usbcfg.b.srpcap = 0;
++00698                 break;
++00699 
++00700         case DWC_MODE_SRP_CAPABLE_DEVICE:
++00701                 usbcfg.b.hnpcap = 0;
++00702                 usbcfg.b.srpcap = (core_if->core_params->otg_cap !=
++00703                                    DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE);
++00704                 break;
++00705 
++00706         case DWC_MODE_NO_SRP_CAPABLE_DEVICE:
++00707                 usbcfg.b.hnpcap = 0;
++00708                 usbcfg.b.srpcap = 0;
++00709                 break;
++00710 
++00711         case DWC_MODE_SRP_CAPABLE_HOST:
++00712                 usbcfg.b.hnpcap = 0;
++00713                 usbcfg.b.srpcap = (core_if->core_params->otg_cap !=
++00714                                    DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE);
++00715                 break;
++00716 
++00717         case DWC_MODE_NO_SRP_CAPABLE_HOST:
++00718                 usbcfg.b.hnpcap = 0;
++00719                 usbcfg.b.srpcap = 0;
++00720                 break;
++00721         }
++00722 
++00723         dwc_write_reg32(&global_regs->gusbcfg, usbcfg.d32);
++00724 
++00725 #ifdef CONFIG_USB_DWC_OTG_LPM
++00726         if (core_if->core_params->lpm_enable) {
++00727                 glpmcfg_data_t lpmcfg = {.d32 = 0 };
++00728 
++00729                 /* To enable LPM support set lpm_cap_en bit */
++00730                 lpmcfg.b.lpm_cap_en = 1;
++00731 
++00732                 /* Make AppL1Res ACK */
++00733                 lpmcfg.b.appl_resp = 1;
++00734 
++00735                 /* Retry 3 times */
++00736                 lpmcfg.b.retry_count = 3;
++00737 
++00738                 dwc_modify_reg32(&core_if->core_global_regs->glpmcfg,
++00739                                  0, lpmcfg.d32);
++00740 
++00741         }
++00742 #endif
++00743         if (core_if->core_params->ic_usb_cap) {
++00744                 gusbcfg_data_t gusbcfg = {.d32 = 0 };
++00745                 gusbcfg.b.ic_usb_cap = 1;
++00746                 dwc_modify_reg32(&core_if->core_global_regs->gusbcfg,
++00747                                  0, gusbcfg.d32);
++00748         }
++00749 
++00750         /* Enable common interrupts */
++00751         dwc_otg_enable_common_interrupts(core_if);
++00752 
++00753         /* Do device or host intialization based on mode during PCD
++00754          * and HCD initialization  */
++00755         if (dwc_otg_is_host_mode(core_if)) {
++00756                 DWC_DEBUGPL(DBG_ANY, "Host Mode\n");
++00757                 core_if->op_state = A_HOST;
++00758         } else {
++00759                 DWC_DEBUGPL(DBG_ANY, "Device Mode\n");
++00760                 core_if->op_state = B_PERIPHERAL;
++00761 #ifdef DWC_DEVICE_ONLY
++00762                 dwc_otg_core_dev_init(core_if);
++00763 #endif
++00764         }
++00765 }
++00766 
++00772 void dwc_otg_enable_device_interrupts(dwc_otg_core_if_t * core_if)
++00773 {
++00774         gintmsk_data_t intr_mask = {.d32 = 0 };
++00775         dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
++00776 
++00777         DWC_DEBUGPL(DBG_CIL, "%s()\n", __func__);
++00778 
++00779         /* Disable all interrupts. */
++00780         dwc_write_reg32(&global_regs->gintmsk, 0);
++00781 
++00782         /* Clear any pending interrupts */
++00783         dwc_write_reg32(&global_regs->gintsts, 0xFFFFFFFF);
++00784 
++00785         /* Enable the common interrupts */
++00786         dwc_otg_enable_common_interrupts(core_if);
++00787 
++00788         /* Enable interrupts */
++00789         intr_mask.b.usbreset = 1;
++00790         intr_mask.b.enumdone = 1;
++00791 
++00792         if (!core_if->multiproc_int_enable) {
++00793                 intr_mask.b.inepintr = 1;
++00794                 intr_mask.b.outepintr = 1;
++00795         }
++00796 
++00797         intr_mask.b.erlysuspend = 1;
++00798 
++00799         if (core_if->en_multiple_tx_fifo == 0) {
++00800                 intr_mask.b.epmismatch = 1;
++00801         }
++00802 #ifdef DWC_EN_ISOC
++00803         if (core_if->dma_enable) {
++00804                 if (core_if->dma_desc_enable == 0) {
++00805                         if (core_if->pti_enh_enable) {
++00806                                 dctl_data_t dctl = {.d32 = 0 };
++00807                                 dctl.b.ifrmnum = 1;
++00808                                 dwc_modify_reg32(&core_if->dev_if->
++00809                                                  dev_global_regs->dctl, 0,
++00810                                                  dctl.d32);
++00811                         } else {
++00812                                 intr_mask.b.incomplisoin = 1;
++00813                                 intr_mask.b.incomplisoout = 1;
++00814                         }
++00815                 }
++00816         } else {
++00817                 intr_mask.b.incomplisoin = 1;
++00818                 intr_mask.b.incomplisoout = 1;
++00819         }
++00820 #endif                          /* DWC_EN_ISOC */
++00821 
++00823 #ifdef USE_PERIODIC_EP
++00824         intr_mask.b.isooutdrop = 1;
++00825         intr_mask.b.eopframe = 1;
++00826         intr_mask.b.incomplisoin = 1;
++00827         intr_mask.b.incomplisoout = 1;
++00828 #endif
++00829 
++00830         dwc_modify_reg32(&global_regs->gintmsk, intr_mask.d32, intr_mask.d32);
++00831 
++00832         DWC_DEBUGPL(DBG_CIL, "%s() gintmsk=%0x\n", __func__,
++00833                     dwc_read_reg32(&global_regs->gintmsk));
++00834 }
++00835 
++00843 void dwc_otg_core_dev_init(dwc_otg_core_if_t * core_if)
++00844 {
++00845         int i;
++00846         dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
++00847         dwc_otg_dev_if_t *dev_if = core_if->dev_if;
++00848         dwc_otg_core_params_t *params = core_if->core_params;
++00849         dcfg_data_t dcfg = {.d32 = 0 };
++00850         grstctl_t resetctl = {.d32 = 0 };
++00851         uint32_t rx_fifo_size;
++00852         fifosize_data_t nptxfifosize;
++00853         fifosize_data_t txfifosize;
++00854         dthrctl_data_t dthrctl;
++00855         fifosize_data_t ptxfifosize;
++00856 
++00857         /* Restart the Phy Clock */
++00858         dwc_write_reg32(core_if->pcgcctl, 0);
++00859 
++00860         /* Device configuration register */
++00861         init_devspd(core_if);
++00862         dcfg.d32 = dwc_read_reg32(&dev_if->dev_global_regs->dcfg);
++00863         dcfg.b.descdma = (core_if->dma_desc_enable) ? 1 : 0;
++00864         dcfg.b.perfrint = DWC_DCFG_FRAME_INTERVAL_80;
++00865 
++00866         dwc_write_reg32(&dev_if->dev_global_regs->dcfg, dcfg.d32);
++00867 
++00868         /* Configure data FIFO sizes */
++00869         if (core_if->hwcfg2.b.dynamic_fifo && params->enable_dynamic_fifo) {
++00870                 DWC_DEBUGPL(DBG_CIL, "Total FIFO Size=%d\n",
++00871                             core_if->total_fifo_size);
++00872                 DWC_DEBUGPL(DBG_CIL, "Rx FIFO Size=%d\n",
++00873                             params->dev_rx_fifo_size);
++00874                 DWC_DEBUGPL(DBG_CIL, "NP Tx FIFO Size=%d\n",
++00875                             params->dev_nperio_tx_fifo_size);
++00876 
++00877                 /* Rx FIFO */
++00878                 DWC_DEBUGPL(DBG_CIL, "initial grxfsiz=%08x\n",
++00879                             dwc_read_reg32(&global_regs->grxfsiz));
++00880 
++00881 #ifdef DWC_UTE_CFI
++00882                 core_if->pwron_rxfsiz = dwc_read_reg32(&global_regs->grxfsiz);
++00883                 core_if->init_rxfsiz = params->dev_rx_fifo_size;
++00884 #endif
++00885                 rx_fifo_size = params->dev_rx_fifo_size;
++00886                 dwc_write_reg32(&global_regs->grxfsiz, rx_fifo_size);
++00887 
++00888                 DWC_DEBUGPL(DBG_CIL, "new grxfsiz=%08x\n",
++00889                             dwc_read_reg32(&global_regs->grxfsiz));
++00890 
++00892                 core_if->p_tx_msk = 0;
++00893 
++00895                 core_if->tx_msk = 0;
++00896 
++00897                 if (core_if->en_multiple_tx_fifo == 0) {
++00898                         /* Non-periodic Tx FIFO */
++00899                         DWC_DEBUGPL(DBG_CIL, "initial gnptxfsiz=%08x\n",
++00900                                     dwc_read_reg32(&global_regs->gnptxfsiz));
++00901 
++00902                         nptxfifosize.b.depth = params->dev_nperio_tx_fifo_size;
++00903                         nptxfifosize.b.startaddr = params->dev_rx_fifo_size;
++00904 
++00905                         dwc_write_reg32(&global_regs->gnptxfsiz,
++00906                                         nptxfifosize.d32);
++00907 
++00908                         DWC_DEBUGPL(DBG_CIL, "new gnptxfsiz=%08x\n",
++00909                                     dwc_read_reg32(&global_regs->gnptxfsiz));
++00910 
++00912                         /*
++00913                          * Periodic Tx FIFOs These FIFOs are numbered from 1 to 15.
++00914                          * Indexes of the FIFO size module parameters in the
++00915                          * dev_perio_tx_fifo_size array and the FIFO size registers in
++00916                          * the dptxfsiz array run from 0 to 14.
++00917                          */
++00919                         ptxfifosize.b.startaddr =
++00920                             nptxfifosize.b.startaddr + nptxfifosize.b.depth;
++00921                         for (i = 0; i < core_if->hwcfg4.b.num_dev_perio_in_ep;
++00922                              i++) {
++00923                                 ptxfifosize.b.depth =
++00924                                     params->dev_perio_tx_fifo_size[i];
++00925                                 DWC_DEBUGPL(DBG_CIL,
++00926                                             "initial dptxfsiz_dieptxf[%d]=%08x\n",
++00927                                             i,
++00928                                             dwc_read_reg32(&global_regs->
++00929                                                            dptxfsiz_dieptxf
++00930                                                            [i]));
++00931                                 dwc_write_reg32(&global_regs->
++00932                                                 dptxfsiz_dieptxf[i],
++00933                                                 ptxfifosize.d32);
++00934                                 DWC_DEBUGPL(DBG_CIL,
++00935                                             "new dptxfsiz_dieptxf[%d]=%08x\n",
++00936                                             i,
++00937                                             dwc_read_reg32(&global_regs->
++00938                                                            dptxfsiz_dieptxf
++00939                                                            [i]));
++00940                                 ptxfifosize.b.startaddr += ptxfifosize.b.depth;
++00941                         }
++00942                 } else {
++00943                         /*
++00944                          * Tx FIFOs These FIFOs are numbered from 1 to 15.
++00945                          * Indexes of the FIFO size module parameters in the
++00946                          * dev_tx_fifo_size array and the FIFO size registers in
++00947                          * the dptxfsiz_dieptxf array run from 0 to 14.
++00948                          */
++00949 
++00950                         /* Non-periodic Tx FIFO */
++00951                         DWC_DEBUGPL(DBG_CIL, "initial gnptxfsiz=%08x\n",
++00952                                     dwc_read_reg32(&global_regs->gnptxfsiz));
++00953 
++00954 #ifdef DWC_UTE_CFI
++00955                         core_if->pwron_gnptxfsiz =
++00956                             (dwc_read_reg32(&global_regs->gnptxfsiz) >> 16);
++00957                         core_if->init_gnptxfsiz =
++00958                             params->dev_nperio_tx_fifo_size;
++00959 #endif
++00960                         nptxfifosize.b.depth = params->dev_nperio_tx_fifo_size;
++00961                         nptxfifosize.b.startaddr = params->dev_rx_fifo_size;
++00962 
++00963                         dwc_write_reg32(&global_regs->gnptxfsiz,
++00964                                         nptxfifosize.d32);
++00965 
++00966                         DWC_DEBUGPL(DBG_CIL, "new gnptxfsiz=%08x\n",
++00967                                     dwc_read_reg32(&global_regs->gnptxfsiz));
++00968 
++00969                         txfifosize.b.startaddr =
++00970                             nptxfifosize.b.startaddr + nptxfifosize.b.depth;
++00971 
++00972                         for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {
++00973 
++00974                                 txfifosize.b.depth =
++00975                                     params->dev_tx_fifo_size[i];
++00976 
++00977                                 DWC_DEBUGPL(DBG_CIL,
++00978                                             "initial dptxfsiz_dieptxf[%d]=%08x\n",
++00979                                             i,
++00980                                             dwc_read_reg32(&global_regs->
++00981                                                            dptxfsiz_dieptxf
++00982                                                            [i]));
++00983 
++00984 #ifdef DWC_UTE_CFI
++00985                                 core_if->pwron_txfsiz[i] =
++00986                                     (dwc_read_reg32
++00987                                      (&global_regs->dptxfsiz_dieptxf[i]) >> 16);
++00988                                 core_if->init_txfsiz[i] =
++00989                                     params->dev_tx_fifo_size[i];
++00990 #endif
++00991                                 dwc_write_reg32(&global_regs->
++00992                                                 dptxfsiz_dieptxf[i],
++00993                                                 txfifosize.d32);
++00994 
++00995                                 DWC_DEBUGPL(DBG_CIL,
++00996                                             "new dptxfsiz_dieptxf[%d]=%08x\n",
++00997                                             i,
++00998                                             dwc_read_reg32(&global_regs->
++00999                                                            dptxfsiz_dieptxf
++01000                                                            [i]));
++01001 
++01002                                 txfifosize.b.startaddr += txfifosize.b.depth;
++01003                         }
++01004                 }
++01005         }
++01006         /* Flush the FIFOs */
++01007         dwc_otg_flush_tx_fifo(core_if, 0x10);   /* all Tx FIFOs */
++01008         dwc_otg_flush_rx_fifo(core_if);
++01009 
++01010         /* Flush the Learning Queue. */
++01011         resetctl.b.intknqflsh = 1;
++01012         dwc_write_reg32(&core_if->core_global_regs->grstctl, resetctl.d32);
++01013 
++01014         /* Clear all pending Device Interrupts */
++01018         if (core_if->multiproc_int_enable) {
++01019                 for (i = 0; i < core_if->dev_if->num_in_eps; ++i) {
++01020                         dwc_write_reg32(&dev_if->dev_global_regs->
++01021                                         diepeachintmsk[i], 0);
++01022                 }
++01023 
++01024                 for (i = 0; i < core_if->dev_if->num_out_eps; ++i) {
++01025                         dwc_write_reg32(&dev_if->dev_global_regs->
++01026                                         doepeachintmsk[i], 0);
++01027                 }
++01028 
++01029                 dwc_write_reg32(&dev_if->dev_global_regs->deachint, 0xFFFFFFFF);
++01030                 dwc_write_reg32(&dev_if->dev_global_regs->deachintmsk, 0);
++01031         } else {
++01032                 dwc_write_reg32(&dev_if->dev_global_regs->diepmsk, 0);
++01033                 dwc_write_reg32(&dev_if->dev_global_regs->doepmsk, 0);
++01034                 dwc_write_reg32(&dev_if->dev_global_regs->daint, 0xFFFFFFFF);
++01035                 dwc_write_reg32(&dev_if->dev_global_regs->daintmsk, 0);
++01036         }
++01037 
++01038         for (i = 0; i <= dev_if->num_in_eps; i++) {
++01039                 depctl_data_t depctl;
++01040                 depctl.d32 = dwc_read_reg32(&dev_if->in_ep_regs[i]->diepctl);
++01041                 if (depctl.b.epena) {
++01042                         depctl.d32 = 0;
++01043                         depctl.b.epdis = 1;
++01044                         depctl.b.snak = 1;
++01045                 } else {
++01046                         depctl.d32 = 0;
++01047                 }
++01048 
++01049                 dwc_write_reg32(&dev_if->in_ep_regs[i]->diepctl, depctl.d32);
++01050 
++01051                 dwc_write_reg32(&dev_if->in_ep_regs[i]->dieptsiz, 0);
++01052                 dwc_write_reg32(&dev_if->in_ep_regs[i]->diepdma, 0);
++01053                 dwc_write_reg32(&dev_if->in_ep_regs[i]->diepint, 0xFF);
++01054         }
++01055 
++01056         for (i = 0; i <= dev_if->num_out_eps; i++) {
++01057                 depctl_data_t depctl;
++01058                 depctl.d32 = dwc_read_reg32(&dev_if->out_ep_regs[i]->doepctl);
++01059                 if (depctl.b.epena) {
++01060                         depctl.d32 = 0;
++01061                         depctl.b.epdis = 1;
++01062                         depctl.b.snak = 1;
++01063                 } else {
++01064                         depctl.d32 = 0;
++01065                 }
++01066 
++01067                 dwc_write_reg32(&dev_if->out_ep_regs[i]->doepctl, depctl.d32);
++01068 
++01069                 dwc_write_reg32(&dev_if->out_ep_regs[i]->doeptsiz, 0);
++01070                 dwc_write_reg32(&dev_if->out_ep_regs[i]->doepdma, 0);
++01071                 dwc_write_reg32(&dev_if->out_ep_regs[i]->doepint, 0xFF);
++01072         }
++01073 
++01074         if (core_if->en_multiple_tx_fifo && core_if->dma_enable) {
++01075                 dev_if->non_iso_tx_thr_en = params->thr_ctl & 0x1;
++01076                 dev_if->iso_tx_thr_en = (params->thr_ctl >> 1) & 0x1;
++01077                 dev_if->rx_thr_en = (params->thr_ctl >> 2) & 0x1;
++01078 
++01079                 dev_if->rx_thr_length = params->rx_thr_length;
++01080                 dev_if->tx_thr_length = params->tx_thr_length;
++01081 
++01082                 dev_if->setup_desc_index = 0;
++01083 
++01084                 dthrctl.d32 = 0;
++01085                 dthrctl.b.non_iso_thr_en = dev_if->non_iso_tx_thr_en;
++01086                 dthrctl.b.iso_thr_en = dev_if->iso_tx_thr_en;
++01087                 dthrctl.b.tx_thr_len = dev_if->tx_thr_length;
++01088                 dthrctl.b.rx_thr_en = dev_if->rx_thr_en;
++01089                 dthrctl.b.rx_thr_len = dev_if->rx_thr_length;
++01090                 dthrctl.b.ahb_thr_ratio = params->ahb_thr_ratio;
++01091 
++01092                 dwc_write_reg32(&dev_if->dev_global_regs->dtknqr3_dthrctl,
++01093                                 dthrctl.d32);
++01094 
++01095                 DWC_DEBUGPL(DBG_CIL,
++01096                             "Non ISO Tx Thr - %d\nISO Tx Thr - %d\nRx Thr - %d\nTx Thr Len - %d\nRx Thr Len - %d\n",
++01097                             dthrctl.b.non_iso_thr_en, dthrctl.b.iso_thr_en,
++01098                             dthrctl.b.rx_thr_en, dthrctl.b.tx_thr_len,
++01099                             dthrctl.b.rx_thr_len);
++01100 
++01101         }
++01102 
++01103         dwc_otg_enable_device_interrupts(core_if);
++01104 
++01105         {
++01106                 diepmsk_data_t msk = {.d32 = 0 };
++01107                 msk.b.txfifoundrn = 1;
++01108                 if (core_if->multiproc_int_enable) {
++01109                         dwc_modify_reg32(&dev_if->dev_global_regs->
++01110                                          diepeachintmsk[0], msk.d32, msk.d32);
++01111                 } else {
++01112                         dwc_modify_reg32(&dev_if->dev_global_regs->diepmsk,
++01113                                          msk.d32, msk.d32);
++01114                 }
++01115         }
++01116 
++01117         if (core_if->multiproc_int_enable) {
++01118                 /* Set NAK on Babble */
++01119                 dctl_data_t dctl = {.d32 = 0 };
++01120                 dctl.b.nakonbble = 1;
++01121                 dwc_modify_reg32(&dev_if->dev_global_regs->dctl, 0, dctl.d32);
++01122         }
++01123 }
++01124 
++01130 void dwc_otg_enable_host_interrupts(dwc_otg_core_if_t * core_if)
++01131 {
++01132         dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
++01133         gintmsk_data_t intr_mask = {.d32 = 0 };
++01134 
++01135         DWC_DEBUGPL(DBG_CIL, "%s()\n", __func__);
++01136 
++01137         /* Disable all interrupts. */
++01138         dwc_write_reg32(&global_regs->gintmsk, 0);
++01139 
++01140         /* Clear any pending interrupts. */
++01141         dwc_write_reg32(&global_regs->gintsts, 0xFFFFFFFF);
++01142 
++01143         /* Enable the common interrupts */
++01144         dwc_otg_enable_common_interrupts(core_if);
++01145 
++01146         /*
++01147          * Enable host mode interrupts without disturbing common
++01148          * interrupts.
++01149          */
++01150          
++01151         /* Do not need sof interrupt for Descriptor DMA*/ 
++01152         if (!core_if->dma_desc_enable) 
++01153         intr_mask.b.sofintr = 1;
++01154         intr_mask.b.portintr = 1;
++01155         intr_mask.b.hcintr = 1;
++01156 
++01157         dwc_modify_reg32(&global_regs->gintmsk, intr_mask.d32, intr_mask.d32);
++01158 }
++01159 
++01165 void dwc_otg_disable_host_interrupts(dwc_otg_core_if_t * core_if)
++01166 {
++01167         dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
++01168         gintmsk_data_t intr_mask = {.d32 = 0 };
++01169 
++01170         DWC_DEBUGPL(DBG_CILV, "%s()\n", __func__);
++01171 
++01172         /*
++01173          * Disable host mode interrupts without disturbing common
++01174          * interrupts.
++01175          */
++01176         intr_mask.b.sofintr = 1;
++01177         intr_mask.b.portintr = 1;
++01178         intr_mask.b.hcintr = 1;
++01179         intr_mask.b.ptxfempty = 1;
++01180         intr_mask.b.nptxfempty = 1;
++01181 
++01182         dwc_modify_reg32(&global_regs->gintmsk, intr_mask.d32, 0);
++01183 }
++01184 
++01196 void dwc_otg_core_host_init(dwc_otg_core_if_t * core_if)
++01197 {
++01198         dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
++01199         dwc_otg_host_if_t *host_if = core_if->host_if;
++01200         dwc_otg_core_params_t *params = core_if->core_params;
++01201         hprt0_data_t hprt0 = {.d32 = 0 };
++01202         fifosize_data_t nptxfifosize;
++01203         fifosize_data_t ptxfifosize;
++01204         int i;
++01205         hcchar_data_t hcchar;
++01206         hcfg_data_t hcfg;
++01207         dwc_otg_hc_regs_t *hc_regs;
++01208         int num_channels;
++01209         gotgctl_data_t gotgctl = {.d32 = 0 };
++01210 
++01211         DWC_DEBUGPL(DBG_CILV, "%s(%p)\n", __func__, core_if);
++01212 
++01213         /* Restart the Phy Clock */
++01214         dwc_write_reg32(core_if->pcgcctl, 0);
++01215 
++01216         /* Initialize Host Configuration Register */
++01217         init_fslspclksel(core_if);
++01218         if (core_if->core_params->speed == DWC_SPEED_PARAM_FULL) {
++01219                 hcfg.d32 = dwc_read_reg32(&host_if->host_global_regs->hcfg);
++01220                 hcfg.b.fslssupp = 1;
++01221                 dwc_write_reg32(&host_if->host_global_regs->hcfg, hcfg.d32);
++01222                 
++01223         }
++01224 
++01225         if (core_if->core_params->dma_desc_enable) {
++01226                 uint8_t op_mode = core_if->hwcfg2.b.op_mode;    
++01227                 if (!(core_if->hwcfg4.b.desc_dma && (core_if->snpsid >= OTG_CORE_REV_2_90a) &&
++01228                                 ((op_mode == DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG) ||
++01229                                 (op_mode == DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG) || 
++01230                                 (op_mode == DWC_HWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE_OTG) ||
++01231                                 (op_mode == DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST) ||
++01232                                 (op_mode == DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST)))) {
++01233                                 
++01234                                 DWC_ERROR("Host can't operate in Descriptor DMA mode.\n"
++01235                                           "Either core version is below 2.90a or "
++01236                                           "GHWCFG2, GHWCFG4 registers' values do not allow Descriptor DMA in host mode.\n"
++01237                                           "To run the driver in Buffer DMA host mode set dma_desc_enable "
++01238                                           "module parameter to 0.\n");
++01239                                 return;
++01240                 }               
++01241                 hcfg.d32 = dwc_read_reg32(&host_if->host_global_regs->hcfg);
++01242                 hcfg.b.descdma = 1;
++01243                 dwc_write_reg32(&host_if->host_global_regs->hcfg, hcfg.d32);
++01244         }
++01245         
++01246         /* Configure data FIFO sizes */
++01247         if (core_if->hwcfg2.b.dynamic_fifo && params->enable_dynamic_fifo) {
++01248                 DWC_DEBUGPL(DBG_CIL, "Total FIFO Size=%d\n",
++01249                             core_if->total_fifo_size);
++01250                 DWC_DEBUGPL(DBG_CIL, "Rx FIFO Size=%d\n",
++01251                             params->host_rx_fifo_size);
++01252                 DWC_DEBUGPL(DBG_CIL, "NP Tx FIFO Size=%d\n",
++01253                             params->host_nperio_tx_fifo_size);
++01254                 DWC_DEBUGPL(DBG_CIL, "P Tx FIFO Size=%d\n",
++01255                             params->host_perio_tx_fifo_size);
++01256 
++01257                 /* Rx FIFO */
++01258                 DWC_DEBUGPL(DBG_CIL, "initial grxfsiz=%08x\n",
++01259                             dwc_read_reg32(&global_regs->grxfsiz));
++01260                 dwc_write_reg32(&global_regs->grxfsiz,
++01261                                 params->host_rx_fifo_size);
++01262                 DWC_DEBUGPL(DBG_CIL, "new grxfsiz=%08x\n",
++01263                             dwc_read_reg32(&global_regs->grxfsiz));
++01264 
++01265                 /* Non-periodic Tx FIFO */
++01266                 DWC_DEBUGPL(DBG_CIL, "initial gnptxfsiz=%08x\n",
++01267                             dwc_read_reg32(&global_regs->gnptxfsiz));
++01268                 nptxfifosize.b.depth = params->host_nperio_tx_fifo_size;
++01269                 nptxfifosize.b.startaddr = params->host_rx_fifo_size;
++01270                 dwc_write_reg32(&global_regs->gnptxfsiz, nptxfifosize.d32);
++01271                 DWC_DEBUGPL(DBG_CIL, "new gnptxfsiz=%08x\n",
++01272                             dwc_read_reg32(&global_regs->gnptxfsiz));
++01273 
++01274                 /* Periodic Tx FIFO */
++01275                 DWC_DEBUGPL(DBG_CIL, "initial hptxfsiz=%08x\n",
++01276                             dwc_read_reg32(&global_regs->hptxfsiz));
++01277                 ptxfifosize.b.depth = params->host_perio_tx_fifo_size;
++01278                 ptxfifosize.b.startaddr =
++01279                     nptxfifosize.b.startaddr + nptxfifosize.b.depth;
++01280                 dwc_write_reg32(&global_regs->hptxfsiz, ptxfifosize.d32);
++01281                 DWC_DEBUGPL(DBG_CIL, "new hptxfsiz=%08x\n",
++01282                             dwc_read_reg32(&global_regs->hptxfsiz));
++01283         }
++01284 
++01285         /* Clear Host Set HNP Enable in the OTG Control Register */
++01286         gotgctl.b.hstsethnpen = 1;
++01287         dwc_modify_reg32(&global_regs->gotgctl, gotgctl.d32, 0);
++01288 
++01289         /* Make sure the FIFOs are flushed. */
++01290         dwc_otg_flush_tx_fifo(core_if, 0x10 /* all Tx FIFOs */ );
++01291         dwc_otg_flush_rx_fifo(core_if);
++01292 
++01293         if(!core_if->core_params->dma_desc_enable) {
++01294                 /* Flush out any leftover queued requests. */
++01295                 num_channels = core_if->core_params->host_channels;
++01296         
++01297                 for (i = 0; i < num_channels; i++) {
++01298                         hc_regs = core_if->host_if->hc_regs[i];
++01299                         hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
++01300                         hcchar.b.chen = 0;
++01301                         hcchar.b.chdis = 1;
++01302                         hcchar.b.epdir = 0;
++01303                         dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
++01304                 }
++01305 
++01306                 /* Halt all channels to put them into a known state. */
++01307                 for (i = 0; i < num_channels; i++) {
++01308                         int count = 0;
++01309                         hc_regs = core_if->host_if->hc_regs[i];
++01310                         hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
++01311                         hcchar.b.chen = 1;
++01312                         hcchar.b.chdis = 1;
++01313                         hcchar.b.epdir = 0;
++01314                         dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
++01315                         DWC_DEBUGPL(DBG_HCDV, "%s: Halt channel %d\n", __func__, i);
++01316                         do {
++01317                                 hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
++01318                                 if (++count > 1000) {
++01319                                         DWC_ERROR
++01320                                             ("%s: Unable to clear halt on channel %d\n",
++01321                                              __func__, i);
++01322                                         break;
++01323                                 }
++01324                                 dwc_udelay(1);
++01325                         } while (hcchar.b.chen);
++01326                 }
++01327         }
++01328         
++01329         /* Turn on the vbus power. */
++01330         DWC_PRINTF("Init: Port Power? op_state=%d\n", core_if->op_state);
++01331         if (core_if->op_state == A_HOST) {
++01332                 hprt0.d32 = dwc_otg_read_hprt0(core_if);
++01333                 DWC_PRINTF("Init: Power Port (%d)\n", hprt0.b.prtpwr);
++01334                 if (hprt0.b.prtpwr == 0) {
++01335                         hprt0.b.prtpwr = 1;
++01336                         dwc_write_reg32(host_if->hprt0, hprt0.d32);
++01337                 }
++01338         }
++01339 
++01340         dwc_otg_enable_host_interrupts(core_if);
++01341 }
++01342 
++01352 void dwc_otg_hc_init(dwc_otg_core_if_t * core_if, dwc_hc_t * hc)
++01353 {
++01354         uint32_t intr_enable;
++01355         hcintmsk_data_t hc_intr_mask;
++01356         gintmsk_data_t gintmsk = {.d32 = 0 };
++01357         hcchar_data_t hcchar;
++01358         hcsplt_data_t hcsplt;
++01359 
++01360         uint8_t hc_num = hc->hc_num;
++01361         dwc_otg_host_if_t *host_if = core_if->host_if;
++01362         dwc_otg_hc_regs_t *hc_regs = host_if->hc_regs[hc_num];
++01363 
++01364         /* Clear old interrupt conditions for this host channel. */
++01365         hc_intr_mask.d32 = 0xFFFFFFFF;
++01366         hc_intr_mask.b.reserved14_31 = 0;
++01367         dwc_write_reg32(&hc_regs->hcint, hc_intr_mask.d32);
++01368 
++01369         /* Enable channel interrupts required for this transfer. */
++01370         hc_intr_mask.d32 = 0;
++01371         hc_intr_mask.b.chhltd = 1;
++01372         if (core_if->dma_enable) {
++01373                 /* For Descriptor DMA mode core halts the channel on AHB error. Interrupt is not required */
++01374                 if (!core_if->dma_desc_enable)
++01375                         hc_intr_mask.b.ahberr = 1;
++01376                 else {
++01377                         if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC) 
++01378                                 hc_intr_mask.b.xfercompl = 1;
++01379                 }
++01380                 
++01381                 if (hc->error_state && !hc->do_split &&
++01382                     hc->ep_type != DWC_OTG_EP_TYPE_ISOC) {
++01383                         hc_intr_mask.b.ack = 1;
++01384                         if (hc->ep_is_in) {
++01385                                 hc_intr_mask.b.datatglerr = 1;
++01386                                 if (hc->ep_type != DWC_OTG_EP_TYPE_INTR) {
++01387                                         hc_intr_mask.b.nak = 1;
++01388                                 }
++01389                         }
++01390                 }
++01391         } else {
++01392                 switch (hc->ep_type) {
++01393                 case DWC_OTG_EP_TYPE_CONTROL:
++01394                 case DWC_OTG_EP_TYPE_BULK:
++01395                         hc_intr_mask.b.xfercompl = 1;
++01396                         hc_intr_mask.b.stall = 1;
++01397                         hc_intr_mask.b.xacterr = 1;
++01398                         hc_intr_mask.b.datatglerr = 1;
++01399                         if (hc->ep_is_in) {
++01400                                 hc_intr_mask.b.bblerr = 1;
++01401                         } else {
++01402                                 hc_intr_mask.b.nak = 1;
++01403                                 hc_intr_mask.b.nyet = 1;
++01404                                 if (hc->do_ping) {
++01405                                         hc_intr_mask.b.ack = 1;
++01406                                 }
++01407                         }
++01408 
++01409                         if (hc->do_split) {
++01410                                 hc_intr_mask.b.nak = 1;
++01411                                 if (hc->complete_split) {
++01412                                         hc_intr_mask.b.nyet = 1;
++01413                                 } else {
++01414                                         hc_intr_mask.b.ack = 1;
++01415                                 }
++01416                         }
++01417 
++01418                         if (hc->error_state) {
++01419                                 hc_intr_mask.b.ack = 1;
++01420                         }
++01421                         break;
++01422                 case DWC_OTG_EP_TYPE_INTR:
++01423                         hc_intr_mask.b.xfercompl = 1;
++01424                         hc_intr_mask.b.nak = 1;
++01425                         hc_intr_mask.b.stall = 1;
++01426                         hc_intr_mask.b.xacterr = 1;
++01427                         hc_intr_mask.b.datatglerr = 1;
++01428                         hc_intr_mask.b.frmovrun = 1;
++01429 
++01430                         if (hc->ep_is_in) {
++01431                                 hc_intr_mask.b.bblerr = 1;
++01432                         }
++01433                         if (hc->error_state) {
++01434                                 hc_intr_mask.b.ack = 1;
++01435                         }
++01436                         if (hc->do_split) {
++01437                                 if (hc->complete_split) {
++01438                                         hc_intr_mask.b.nyet = 1;
++01439                                 } else {
++01440                                         hc_intr_mask.b.ack = 1;
++01441                                 }
++01442                         }
++01443                         break;
++01444                 case DWC_OTG_EP_TYPE_ISOC:
++01445                         hc_intr_mask.b.xfercompl = 1;
++01446                         hc_intr_mask.b.frmovrun = 1;
++01447                         hc_intr_mask.b.ack = 1;
++01448 
++01449                         if (hc->ep_is_in) {
++01450                                 hc_intr_mask.b.xacterr = 1;
++01451                                 hc_intr_mask.b.bblerr = 1;
++01452                         }
++01453                         break;
++01454                 }
++01455         }
++01456         dwc_write_reg32(&hc_regs->hcintmsk, hc_intr_mask.d32);
++01457 
++01458         /* Enable the top level host channel interrupt. */
++01459         intr_enable = (1 << hc_num);
++01460         dwc_modify_reg32(&host_if->host_global_regs->haintmsk, 0, intr_enable);
++01461 
++01462         /* Make sure host channel interrupts are enabled. */
++01463         gintmsk.b.hcintr = 1;
++01464         dwc_modify_reg32(&core_if->core_global_regs->gintmsk, 0, gintmsk.d32);
++01465 
++01466         /*
++01467          * Program the HCCHARn register with the endpoint characteristics for
++01468          * the current transfer.
++01469          */
++01470         hcchar.d32 = 0;
++01471         hcchar.b.devaddr = hc->dev_addr;
++01472         hcchar.b.epnum = hc->ep_num;
++01473         hcchar.b.epdir = hc->ep_is_in;
++01474         hcchar.b.lspddev = (hc->speed == DWC_OTG_EP_SPEED_LOW);
++01475         hcchar.b.eptype = hc->ep_type;
++01476         hcchar.b.mps = hc->max_packet;
++01477 
++01478         dwc_write_reg32(&host_if->hc_regs[hc_num]->hcchar, hcchar.d32);
++01479 
++01480         DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num);
++01481         DWC_DEBUGPL(DBG_HCDV, "  Dev Addr: %d\n", hcchar.b.devaddr);
++01482         DWC_DEBUGPL(DBG_HCDV, "  Ep Num: %d\n", hcchar.b.epnum);
++01483         DWC_DEBUGPL(DBG_HCDV, "  Is In: %d\n", hcchar.b.epdir);
++01484         DWC_DEBUGPL(DBG_HCDV, "  Is Low Speed: %d\n", hcchar.b.lspddev);
++01485         DWC_DEBUGPL(DBG_HCDV, "  Ep Type: %d\n", hcchar.b.eptype);
++01486         DWC_DEBUGPL(DBG_HCDV, "  Max Pkt: %d\n", hcchar.b.mps);
++01487         DWC_DEBUGPL(DBG_HCDV, "  Multi Cnt: %d\n", hcchar.b.multicnt);
++01488 
++01489         /*
++01490          * Program the HCSPLIT register for SPLITs
++01491          */
++01492         hcsplt.d32 = 0;
++01493         if (hc->do_split) {
++01494                 DWC_DEBUGPL(DBG_HCDV, "Programming HC %d with split --> %s\n",
++01495                             hc->hc_num,
++01496                             hc->complete_split ? "CSPLIT" : "SSPLIT");
++01497                 hcsplt.b.compsplt = hc->complete_split;
++01498                 hcsplt.b.xactpos = hc->xact_pos;
++01499                 hcsplt.b.hubaddr = hc->hub_addr;
++01500                 hcsplt.b.prtaddr = hc->port_addr;
++01501                 DWC_DEBUGPL(DBG_HCDV, "   comp split %d\n", hc->complete_split);
++01502                 DWC_DEBUGPL(DBG_HCDV, "   xact pos %d\n", hc->xact_pos);
++01503                 DWC_DEBUGPL(DBG_HCDV, "   hub addr %d\n", hc->hub_addr);
++01504                 DWC_DEBUGPL(DBG_HCDV, "   port addr %d\n", hc->port_addr);
++01505                 DWC_DEBUGPL(DBG_HCDV, "   is_in %d\n", hc->ep_is_in);
++01506                 DWC_DEBUGPL(DBG_HCDV, "   Max Pkt: %d\n", hcchar.b.mps);
++01507                 DWC_DEBUGPL(DBG_HCDV, "   xferlen: %d\n", hc->xfer_len);
++01508         }
++01509         dwc_write_reg32(&host_if->hc_regs[hc_num]->hcsplt, hcsplt.d32);
++01510 
++01511 }
++01512 
++01540 void dwc_otg_hc_halt(dwc_otg_core_if_t * core_if,
++01541                      dwc_hc_t * hc, dwc_otg_halt_status_e halt_status)
++01542 {
++01543         gnptxsts_data_t nptxsts;
++01544         hptxsts_data_t hptxsts;
++01545         hcchar_data_t hcchar;
++01546         dwc_otg_hc_regs_t *hc_regs;
++01547         dwc_otg_core_global_regs_t *global_regs;
++01548         dwc_otg_host_global_regs_t *host_global_regs;
++01549 
++01550         hc_regs = core_if->host_if->hc_regs[hc->hc_num];
++01551         global_regs = core_if->core_global_regs;
++01552         host_global_regs = core_if->host_if->host_global_regs;
++01553 
++01554         DWC_ASSERT(!(halt_status == DWC_OTG_HC_XFER_NO_HALT_STATUS),
++01555                    "halt_status = %d\n", halt_status);
++01556 
++01557         if (halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE ||
++01558             halt_status == DWC_OTG_HC_XFER_AHB_ERR) {
++01559                 /*
++01560                  * Disable all channel interrupts except Ch Halted. The QTD
++01561                  * and QH state associated with this transfer has been cleared
++01562                  * (in the case of URB_DEQUEUE), so the channel needs to be
++01563                  * shut down carefully to prevent crashes.
++01564                  */
++01565                 hcintmsk_data_t hcintmsk;
++01566                 hcintmsk.d32 = 0;
++01567                 hcintmsk.b.chhltd = 1;
++01568                 dwc_write_reg32(&hc_regs->hcintmsk, hcintmsk.d32);
++01569 
++01570                 /*
++01571                  * Make sure no other interrupts besides halt are currently
++01572                  * pending. Handling another interrupt could cause a crash due
++01573                  * to the QTD and QH state.
++01574                  */
++01575                 dwc_write_reg32(&hc_regs->hcint, ~hcintmsk.d32);
++01576 
++01577                 /*
++01578                  * Make sure the halt status is set to URB_DEQUEUE or AHB_ERR
++01579                  * even if the channel was already halted for some other
++01580                  * reason.
++01581                  */
++01582                 hc->halt_status = halt_status;
++01583 
++01584                 hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
++01585                 if (hcchar.b.chen == 0) {
++01586                         /*
++01587                          * The channel is either already halted or it hasn't
++01588                          * started yet. In DMA mode, the transfer may halt if
++01589                          * it finishes normally or a condition occurs that
++01590                          * requires driver intervention. Don't want to halt
++01591                          * the channel again. In either Slave or DMA mode,
++01592                          * it's possible that the transfer has been assigned
++01593                          * to a channel, but not started yet when an URB is
++01594                          * dequeued. Don't want to halt a channel that hasn't
++01595                          * started yet.
++01596                          */
++01597                         return;
++01598                 }
++01599         }
++01600         if (hc->halt_pending) {
++01601                 /*
++01602                  * A halt has already been issued for this channel. This might
++01603                  * happen when a transfer is aborted by a higher level in
++01604                  * the stack.
++01605                  */
++01606 #ifdef DEBUG
++01607                 DWC_PRINTF
++01608                     ("*** %s: Channel %d, _hc->halt_pending already set ***\n",
++01609                      __func__, hc->hc_num);
++01610 
++01611 #endif
++01612                 return;
++01613         }
++01614 
++01615         hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
++01616         
++01617         /* No need to set the bit in DDMA for disabling the channel */
++01618         //TODO check it everywhere channel is disabled          
++01619         if(!core_if->core_params->dma_desc_enable)
++01620                 hcchar.b.chen = 1;
++01621         hcchar.b.chdis = 1;
++01622         
++01623         if (!core_if->dma_enable) {
++01624                 /* Check for space in the request queue to issue the halt. */
++01625                 if (hc->ep_type == DWC_OTG_EP_TYPE_CONTROL ||
++01626                     hc->ep_type == DWC_OTG_EP_TYPE_BULK) {
++01627                         nptxsts.d32 = dwc_read_reg32(&global_regs->gnptxsts);
++01628                         if (nptxsts.b.nptxqspcavail == 0) {
++01629                                 hcchar.b.chen = 0;
++01630                         }
++01631                 } else {
++01632                         hptxsts.d32 =
++01633                             dwc_read_reg32(&host_global_regs->hptxsts);
++01634                         if ((hptxsts.b.ptxqspcavail == 0)
++01635                             || (core_if->queuing_high_bandwidth)) {
++01636                                 hcchar.b.chen = 0;
++01637                         }
++01638                 }
++01639         }
++01640         dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
++01641 
++01642         hc->halt_status = halt_status;
++01643 
++01644         if (hcchar.b.chen) {
++01645                 hc->halt_pending = 1;
++01646                 hc->halt_on_queue = 0;
++01647         } else {
++01648                 hc->halt_on_queue = 1;
++01649         }
++01650 
++01651         DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num);
++01652         DWC_DEBUGPL(DBG_HCDV, "  hcchar: 0x%08x\n", hcchar.d32);
++01653         DWC_DEBUGPL(DBG_HCDV, "  halt_pending: %d\n", hc->halt_pending);
++01654         DWC_DEBUGPL(DBG_HCDV, "  halt_on_queue: %d\n", hc->halt_on_queue);
++01655         DWC_DEBUGPL(DBG_HCDV, "  halt_status: %d\n", hc->halt_status);
++01656 
++01657         return;
++01658 }
++01659 
++01667 void dwc_otg_hc_cleanup(dwc_otg_core_if_t * core_if, dwc_hc_t * hc)
++01668 {
++01669         dwc_otg_hc_regs_t *hc_regs;
++01670 
++01671         hc->xfer_started = 0;
++01672 
++01673         /*
++01674          * Clear channel interrupt enables and any unhandled channel interrupt
++01675          * conditions.
++01676          */
++01677         hc_regs = core_if->host_if->hc_regs[hc->hc_num];
++01678         dwc_write_reg32(&hc_regs->hcintmsk, 0);
++01679         dwc_write_reg32(&hc_regs->hcint, 0xFFFFFFFF);
++01680 #ifdef DEBUG
++01681         DWC_TIMER_CANCEL(core_if->hc_xfer_timer[hc->hc_num]);
++01682 #endif
++01683 }
++01684 
++01695 static inline void hc_set_even_odd_frame(dwc_otg_core_if_t * core_if,
++01696                                          dwc_hc_t * hc, hcchar_data_t * hcchar)
++01697 {
++01698         if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
++01699             hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
++01700                 hfnum_data_t hfnum;
++01701                 hfnum.d32 =
++01702                     dwc_read_reg32(&core_if->host_if->host_global_regs->hfnum);
++01703 
++01704                 /* 1 if _next_ frame is odd, 0 if it's even */
++01705                 hcchar->b.oddfrm = (hfnum.b.frnum & 0x1) ? 0 : 1;
++01706 #ifdef DEBUG
++01707                 if (hc->ep_type == DWC_OTG_EP_TYPE_INTR && hc->do_split
++01708                     && !hc->complete_split) {
++01709                         switch (hfnum.b.frnum & 0x7) {
++01710                         case 7:
++01711                                 core_if->hfnum_7_samples++;
++01712                                 core_if->hfnum_7_frrem_accum += hfnum.b.frrem;
++01713                                 break;
++01714                         case 0:
++01715                                 core_if->hfnum_0_samples++;
++01716                                 core_if->hfnum_0_frrem_accum += hfnum.b.frrem;
++01717                                 break;
++01718                         default:
++01719                                 core_if->hfnum_other_samples++;
++01720                                 core_if->hfnum_other_frrem_accum +=
++01721                                     hfnum.b.frrem;
++01722                                 break;
++01723                         }
++01724                 }
++01725 #endif
++01726         }
++01727 }
++01728 
++01729 #ifdef DEBUG
++01730 void hc_xfer_timeout(void *ptr)
++01731 {
++01732         hc_xfer_info_t *xfer_info = (hc_xfer_info_t *) ptr;
++01733         int hc_num = xfer_info->hc->hc_num;
++01734         DWC_WARN("%s: timeout on channel %d\n", __func__, hc_num);
++01735         DWC_WARN("      start_hcchar_val 0x%08x\n",
++01736                  xfer_info->core_if->start_hcchar_val[hc_num]);
++01737 }
++01738 #endif
++01739 
++01740 void set_pid_isoc(dwc_hc_t * hc)
++01741 {
++01742         /* Set up the initial PID for the transfer. */
++01743         if (hc->speed == DWC_OTG_EP_SPEED_HIGH) {
++01744                 if (hc->ep_is_in) {
++01745                         if (hc->multi_count == 1) {
++01746                                 hc->data_pid_start =
++01747                                     DWC_OTG_HC_PID_DATA0;
++01748                         } else if (hc->multi_count == 2) {
++01749                                 hc->data_pid_start =
++01750                                     DWC_OTG_HC_PID_DATA1;
++01751                         } else {
++01752                                 hc->data_pid_start =
++01753                                     DWC_OTG_HC_PID_DATA2;
++01754                         }
++01755                 } else {
++01756                         if (hc->multi_count == 1) {
++01757                                 hc->data_pid_start =
++01758                                     DWC_OTG_HC_PID_DATA0;
++01759                         } else {
++01760                                 hc->data_pid_start =
++01761                                     DWC_OTG_HC_PID_MDATA;
++01762                         }
++01763                 }
++01764         } else {
++01765                 hc->data_pid_start = DWC_OTG_HC_PID_DATA0;
++01766         }
++01767 }
++01768 
++01800 void dwc_otg_hc_start_transfer(dwc_otg_core_if_t * core_if, dwc_hc_t * hc)
++01801 {
++01802         hcchar_data_t hcchar;
++01803         hctsiz_data_t hctsiz;
++01804         uint16_t num_packets;
++01805         uint32_t max_hc_xfer_size = core_if->core_params->max_transfer_size;
++01806         uint16_t max_hc_pkt_count = core_if->core_params->max_packet_count;
++01807         dwc_otg_hc_regs_t *hc_regs = core_if->host_if->hc_regs[hc->hc_num];
++01808 
++01809         hctsiz.d32 = 0;
++01810 
++01811         if (hc->do_ping) {
++01812                 if (!core_if->dma_enable) {
++01813                         dwc_otg_hc_do_ping(core_if, hc);
++01814                         hc->xfer_started = 1;
++01815                         return;
++01816                 } else {
++01817                         hctsiz.b.dopng = 1;
++01818                 }
++01819         }
++01820 
++01821         if (hc->do_split) {
++01822                 num_packets = 1;
++01823 
++01824                 if (hc->complete_split && !hc->ep_is_in) {
++01825                         /* For CSPLIT OUT Transfer, set the size to 0 so the
++01826                          * core doesn't expect any data written to the FIFO */
++01827                         hc->xfer_len = 0;
++01828                 } else if (hc->ep_is_in || (hc->xfer_len > hc->max_packet)) {
++01829                         hc->xfer_len = hc->max_packet;
++01830                 } else if (!hc->ep_is_in && (hc->xfer_len > 188)) {
++01831                         hc->xfer_len = 188;
++01832                 }
++01833 
++01834                 hctsiz.b.xfersize = hc->xfer_len;
++01835         } else {
++01836                 /*
++01837                  * Ensure that the transfer length and packet count will fit
++01838                  * in the widths allocated for them in the HCTSIZn register.
++01839                  */
++01840                 if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
++01841                     hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
++01842                         /*
++01843                          * Make sure the transfer size is no larger than one
++01844                          * (micro)frame's worth of data. (A check was done
++01845                          * when the periodic transfer was accepted to ensure
++01846                          * that a (micro)frame's worth of data can be
++01847                          * programmed into a channel.)
++01848                          */
++01849                         uint32_t max_periodic_len =
++01850                             hc->multi_count * hc->max_packet;
++01851                         if (hc->xfer_len > max_periodic_len) {
++01852                                 hc->xfer_len = max_periodic_len;
++01853                         } else {
++01854                         }
++01855                 } else if (hc->xfer_len > max_hc_xfer_size) {
++01856                         /* Make sure that xfer_len is a multiple of max packet size. */
++01857                         hc->xfer_len = max_hc_xfer_size - hc->max_packet + 1;
++01858                 }
++01859 
++01860                 if (hc->xfer_len > 0) {
++01861                         num_packets =
++01862                             (hc->xfer_len + hc->max_packet -
++01863                              1) / hc->max_packet;
++01864                         if (num_packets > max_hc_pkt_count) {
++01865                                 num_packets = max_hc_pkt_count;
++01866                                 hc->xfer_len = num_packets * hc->max_packet;
++01867                         }
++01868                 } else {
++01869                         /* Need 1 packet for transfer length of 0. */
++01870                         num_packets = 1;
++01871                 }
++01872 
++01873                 if (hc->ep_is_in) {
++01874                         /* Always program an integral # of max packets for IN transfers. */
++01875                         hc->xfer_len = num_packets * hc->max_packet;
++01876                 }
++01877 
++01878                 if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
++01879                     hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
++01880                         /*
++01881                          * Make sure that the multi_count field matches the
++01882                          * actual transfer length.
++01883                          */
++01884                         hc->multi_count = num_packets;
++01885                 }
++01886 
++01887                 if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC)
++01888                         set_pid_isoc(hc);
++01889 
++01890                 hctsiz.b.xfersize = hc->xfer_len;
++01891         }
++01892 
++01893         hc->start_pkt_count = num_packets;
++01894         hctsiz.b.pktcnt = num_packets;
++01895         hctsiz.b.pid = hc->data_pid_start;
++01896         dwc_write_reg32(&hc_regs->hctsiz, hctsiz.d32);
++01897 
++01898         DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num);
++01899         DWC_DEBUGPL(DBG_HCDV, "  Xfer Size: %d\n", hctsiz.b.xfersize);
++01900         DWC_DEBUGPL(DBG_HCDV, "  Num Pkts: %d\n", hctsiz.b.pktcnt);
++01901         DWC_DEBUGPL(DBG_HCDV, "  Start PID: %d\n", hctsiz.b.pid);
++01902 
++01903         if (core_if->dma_enable) {
++01904                 dwc_dma_t dma_addr;
++01905                 if (hc->align_buff) {
++01906                         dma_addr = hc->align_buff;
++01907                 } else {
++01908                         dma_addr = (uint32_t)hc->xfer_buff;
++01909                 }
++01910                 dwc_write_reg32(&hc_regs->hcdma, dma_addr);
++01911         }
++01912 
++01913         /* Start the split */
++01914         if (hc->do_split) {
++01915                 hcsplt_data_t hcsplt;
++01916                 hcsplt.d32 = dwc_read_reg32(&hc_regs->hcsplt);
++01917                 hcsplt.b.spltena = 1;
++01918                 dwc_write_reg32(&hc_regs->hcsplt, hcsplt.d32);
++01919         }
++01920 
++01921         hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
++01922         hcchar.b.multicnt = hc->multi_count;
++01923         hc_set_even_odd_frame(core_if, hc, &hcchar);
++01924 #ifdef DEBUG
++01925         core_if->start_hcchar_val[hc->hc_num] = hcchar.d32;
++01926         if (hcchar.b.chdis) {
++01927                 DWC_WARN("%s: chdis set, channel %d, hcchar 0x%08x\n",
++01928                          __func__, hc->hc_num, hcchar.d32);
++01929         }
++01930 #endif
++01931 
++01932         /* Set host channel enable after all other setup is complete. */
++01933         hcchar.b.chen = 1;
++01934         hcchar.b.chdis = 0;
++01935         dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
++01936 
++01937         hc->xfer_started = 1;
++01938         hc->requests++;
++01939 
++01940         if (!core_if->dma_enable && !hc->ep_is_in && hc->xfer_len > 0) {
++01941                 /* Load OUT packet into the appropriate Tx FIFO. */
++01942                 dwc_otg_hc_write_packet(core_if, hc);
++01943         }
++01944 #ifdef DEBUG
++01945         if (hc->ep_type != DWC_OTG_EP_TYPE_INTR) {
++01946                 core_if->hc_xfer_info[hc->hc_num].core_if = core_if;
++01947                 core_if->hc_xfer_info[hc->hc_num].hc = hc;
++01948                 /* Start a timer for this transfer. */
++01949                 DWC_TIMER_SCHEDULE(core_if->hc_xfer_timer[hc->hc_num], 10000);
++01950         }
++01951 #endif
++01952 }
++01953 
++01968 void dwc_otg_hc_start_transfer_ddma(dwc_otg_core_if_t * core_if, dwc_hc_t * hc)
++01969 {
++01970         dwc_otg_hc_regs_t *hc_regs = core_if->host_if->hc_regs[hc->hc_num];     
++01971         hcchar_data_t hcchar;
++01972         hctsiz_data_t hctsiz;
++01973         hcdma_data_t  hcdma;
++01974         
++01975         hctsiz.d32 = 0;
++01976 
++01977         if (hc->do_ping && !hc->ep_is_in)
++01978                 hctsiz.b_ddma.dopng = 1;
++01979 
++01980         if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC)
++01981                 set_pid_isoc(hc);
++01982         
++01983         /* Packet Count and Xfer Size are not used in Descriptor DMA mode */
++01984         hctsiz.b_ddma.pid = hc->data_pid_start;
++01985         hctsiz.b_ddma.ntd = hc->ntd - 1; /* 0 - 1 descriptor, 1 - 2 descriptors, etc. */
++01986         hctsiz.b_ddma.schinfo = hc->schinfo; /* Non-zero only for high-speed interrupt endpoints */
++01987         
++01988         DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num);
++01989         DWC_DEBUGPL(DBG_HCDV, "  Start PID: %d\n", hctsiz.b.pid);
++01990         DWC_DEBUGPL(DBG_HCDV, "  NTD: %d\n", hctsiz.b_ddma.ntd);        
++01991 
++01992         dwc_write_reg32(&hc_regs->hctsiz, hctsiz.d32);
++01993 
++01994         hcdma.d32 = 0;
++01995         hcdma.b.dma_addr = ((uint32_t)hc->desc_list_addr) >> 11;
++01996                 
++01997         /* Always start from first descriptor. */
++01998         hcdma.b.ctd = 0;
++01999         dwc_write_reg32(&hc_regs->hcdma, hcdma.d32);
++02000 
++02001         hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
++02002         hcchar.b.multicnt = hc->multi_count;
++02003         
++02004 #ifdef DEBUG
++02005         core_if->start_hcchar_val[hc->hc_num] = hcchar.d32;
++02006         if (hcchar.b.chdis) {
++02007                 DWC_WARN("%s: chdis set, channel %d, hcchar 0x%08x\n",
++02008                          __func__, hc->hc_num, hcchar.d32);
++02009         }
++02010 #endif
++02011 
++02012         /* Set host channel enable after all other setup is complete. */
++02013         hcchar.b.chen = 1;
++02014         hcchar.b.chdis = 0;
++02015         
++02016         dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
++02017 
++02018         hc->xfer_started = 1;
++02019         hc->requests++;
++02020         
++02021 #ifdef DEBUG
++02022         if ((hc->ep_type != DWC_OTG_EP_TYPE_INTR) && (hc->ep_type != DWC_OTG_EP_TYPE_ISOC)) {
++02023                 core_if->hc_xfer_info[hc->hc_num].core_if = core_if;
++02024                 core_if->hc_xfer_info[hc->hc_num].hc = hc;
++02025                 /* Start a timer for this transfer. */
++02026                 DWC_TIMER_SCHEDULE(core_if->hc_xfer_timer[hc->hc_num], 10000);
++02027         }
++02028 
++02029 #endif
++02030         
++02031 }
++02032         
++02048 int dwc_otg_hc_continue_transfer(dwc_otg_core_if_t * core_if, dwc_hc_t * hc)
++02049 {
++02050         DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num);
++02051 
++02052         if (hc->do_split) {
++02053                 /* SPLITs always queue just once per channel */
++02054                 return 0;
++02055         } else if (hc->data_pid_start == DWC_OTG_HC_PID_SETUP) {
++02056                 /* SETUPs are queued only once since they can't be NAKed. */
++02057                 return 0;
++02058         } else if (hc->ep_is_in) {
++02059                 /*
++02060                  * Always queue another request for other IN transfers. If
++02061                  * back-to-back INs are issued and NAKs are received for both,
++02062                  * the driver may still be processing the first NAK when the
++02063                  * second NAK is received. When the interrupt handler clears
++02064                  * the NAK interrupt for the first NAK, the second NAK will
++02065                  * not be seen. So we can't depend on the NAK interrupt
++02066                  * handler to requeue a NAKed request. Instead, IN requests
++02067                  * are issued each time this function is called. When the
++02068                  * transfer completes, the extra requests for the channel will
++02069                  * be flushed.
++02070                  */
++02071                 hcchar_data_t hcchar;
++02072                 dwc_otg_hc_regs_t *hc_regs =
++02073                     core_if->host_if->hc_regs[hc->hc_num];
++02074 
++02075                 hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
++02076                 hc_set_even_odd_frame(core_if, hc, &hcchar);
++02077                 hcchar.b.chen = 1;
++02078                 hcchar.b.chdis = 0;
++02079                 DWC_DEBUGPL(DBG_HCDV, "  IN xfer: hcchar = 0x%08x\n",
++02080                             hcchar.d32);
++02081                 dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
++02082                 hc->requests++;
++02083                 return 1;
++02084         } else {
++02085                 /* OUT transfers. */
++02086                 if (hc->xfer_count < hc->xfer_len) {
++02087                         if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
++02088                             hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
++02089                                 hcchar_data_t hcchar;
++02090                                 dwc_otg_hc_regs_t *hc_regs;
++02091                                 hc_regs = core_if->host_if->hc_regs[hc->hc_num];
++02092                                 hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
++02093                                 hc_set_even_odd_frame(core_if, hc, &hcchar);
++02094                         }
++02095 
++02096                         /* Load OUT packet into the appropriate Tx FIFO. */
++02097                         dwc_otg_hc_write_packet(core_if, hc);
++02098                         hc->requests++;
++02099                         return 1;
++02100                 } else {
++02101                         return 0;
++02102                 }
++02103         }
++02104 }
++02105 
++02110 void dwc_otg_hc_do_ping(dwc_otg_core_if_t * core_if, dwc_hc_t * hc)
++02111 {
++02112         hcchar_data_t hcchar;
++02113         hctsiz_data_t hctsiz;
++02114         dwc_otg_hc_regs_t *hc_regs = core_if->host_if->hc_regs[hc->hc_num];
++02115 
++02116         DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num);
++02117 
++02118         hctsiz.d32 = 0;
++02119         hctsiz.b.dopng = 1;
++02120         hctsiz.b.pktcnt = 1;
++02121         dwc_write_reg32(&hc_regs->hctsiz, hctsiz.d32);
++02122 
++02123         hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
++02124         hcchar.b.chen = 1;
++02125         hcchar.b.chdis = 0;
++02126         dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
++02127 }
++02128 
++02129 /*
++02130  * This function writes a packet into the Tx FIFO associated with the Host
++02131  * Channel. For a channel associated with a non-periodic EP, the non-periodic
++02132  * Tx FIFO is written. For a channel associated with a periodic EP, the
++02133  * periodic Tx FIFO is written. This function should only be called in Slave
++02134  * mode.
++02135  *
++02136  * Upon return the xfer_buff and xfer_count fields in _hc are incremented by
++02137  * then number of bytes written to the Tx FIFO.
++02138  */
++02139 void dwc_otg_hc_write_packet(dwc_otg_core_if_t * core_if, dwc_hc_t * hc)
++02140 {
++02141         uint32_t i;
++02142         uint32_t remaining_count;
++02143         uint32_t byte_count;
++02144         uint32_t dword_count;
++02145 
++02146         uint32_t *data_buff = (uint32_t *) (hc->xfer_buff);
++02147         uint32_t *data_fifo = core_if->data_fifo[hc->hc_num];
++02148 
++02149         remaining_count = hc->xfer_len - hc->xfer_count;
++02150         if (remaining_count > hc->max_packet) {
++02151                 byte_count = hc->max_packet;
++02152         } else {
++02153                 byte_count = remaining_count;
++02154         }
++02155 
++02156         dword_count = (byte_count + 3) / 4;
++02157 
++02158         if ((((unsigned long)data_buff) & 0x3) == 0) {
++02159                 /* xfer_buff is DWORD aligned. */
++02160                 for (i = 0; i < dword_count; i++, data_buff++) {
++02161                         dwc_write_reg32(data_fifo, *data_buff);
++02162                 }
++02163         } else {
++02164                 /* xfer_buff is not DWORD aligned. */
++02165                 for (i = 0; i < dword_count; i++, data_buff++) {
++02166                         uint32_t data;
++02167                         data =
++02168                             (data_buff[0] | data_buff[1] << 8 | data_buff[2] <<
++02169                              16 | data_buff[3] << 24);
++02170                         dwc_write_reg32(data_fifo, data);
++02171                 }
++02172         }
++02173 
++02174         hc->xfer_count += byte_count;
++02175         hc->xfer_buff += byte_count;
++02176 }
++02177 
++02182 uint32_t dwc_otg_get_frame_number(dwc_otg_core_if_t * core_if)
++02183 {
++02184         dsts_data_t dsts;
++02185         dsts.d32 = dwc_read_reg32(&core_if->dev_if->dev_global_regs->dsts);
++02186 
++02187         /* read current frame/microframe number from DSTS register */
++02188         return dsts.b.soffn;
++02189 }
++02190 
++02199 void dwc_otg_read_setup_packet(dwc_otg_core_if_t * core_if, uint32_t * dest)
++02200 {
++02201         /* Get the 8 bytes of a setup transaction data */
++02202 
++02203         /* Pop 2 DWORDS off the receive data FIFO into memory */
++02204         dest[0] = dwc_read_reg32(core_if->data_fifo[0]);
++02205         dest[1] = dwc_read_reg32(core_if->data_fifo[0]);
++02206 }
++02207 
++02216 void dwc_otg_ep0_activate(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
++02217 {
++02218         dwc_otg_dev_if_t *dev_if = core_if->dev_if;
++02219         dsts_data_t dsts;
++02220         depctl_data_t diepctl;
++02221         depctl_data_t doepctl;
++02222         dctl_data_t dctl = {.d32 = 0 };
++02223 
++02224         /* Read the Device Status and Endpoint 0 Control registers */
++02225         dsts.d32 = dwc_read_reg32(&dev_if->dev_global_regs->dsts);
++02226         diepctl.d32 = dwc_read_reg32(&dev_if->in_ep_regs[0]->diepctl);
++02227         doepctl.d32 = dwc_read_reg32(&dev_if->out_ep_regs[0]->doepctl);
++02228 
++02229         /* Set the MPS of the IN EP based on the enumeration speed */
++02230         switch (dsts.b.enumspd) {
++02231         case DWC_DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ:
++02232         case DWC_DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ:
++02233         case DWC_DSTS_ENUMSPD_FS_PHY_48MHZ:
++02234                 diepctl.b.mps = DWC_DEP0CTL_MPS_64;
++02235                 break;
++02236         case DWC_DSTS_ENUMSPD_LS_PHY_6MHZ:
++02237                 diepctl.b.mps = DWC_DEP0CTL_MPS_8;
++02238                 break;
++02239         }
++02240 
++02241         dwc_write_reg32(&dev_if->in_ep_regs[0]->diepctl, diepctl.d32);
++02242 
++02243         /* Enable OUT EP for receive */
++02244         doepctl.b.epena = 1;
++02245         dwc_write_reg32(&dev_if->out_ep_regs[0]->doepctl, doepctl.d32);
++02246 
++02247 #ifdef VERBOSE
++02248         DWC_DEBUGPL(DBG_PCDV, "doepctl0=%0x\n",
++02249                     dwc_read_reg32(&dev_if->out_ep_regs[0]->doepctl));
++02250         DWC_DEBUGPL(DBG_PCDV, "diepctl0=%0x\n",
++02251                     dwc_read_reg32(&dev_if->in_ep_regs[0]->diepctl));
++02252 #endif
++02253         dctl.b.cgnpinnak = 1;
++02254 
++02255         dwc_modify_reg32(&dev_if->dev_global_regs->dctl, dctl.d32, dctl.d32);
++02256         DWC_DEBUGPL(DBG_PCDV, "dctl=%0x\n",
++02257                     dwc_read_reg32(&dev_if->dev_global_regs->dctl));
++02258 }
++02259 
++02268 void dwc_otg_ep_activate(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
++02269 {
++02270         dwc_otg_dev_if_t *dev_if = core_if->dev_if;
++02271         depctl_data_t depctl;
++02272         volatile uint32_t *addr;
++02273         daint_data_t daintmsk = {.d32 = 0 };
++02274 
++02275         DWC_DEBUGPL(DBG_PCDV, "%s() EP%d-%s\n", __func__, ep->num,
++02276                     (ep->is_in ? "IN" : "OUT"));
++02277 
++02278         /* Read DEPCTLn register */
++02279         if (ep->is_in == 1) {
++02280                 addr = &dev_if->in_ep_regs[ep->num]->diepctl;
++02281                 daintmsk.ep.in = 1 << ep->num;
++02282         } else {
++02283                 addr = &dev_if->out_ep_regs[ep->num]->doepctl;
++02284                 daintmsk.ep.out = 1 << ep->num;
++02285         }
++02286 
++02287         /* If the EP is already active don't change the EP Control
++02288          * register. */
++02289         depctl.d32 = dwc_read_reg32(addr);
++02290         if (!depctl.b.usbactep) {
++02291                 depctl.b.mps = ep->maxpacket;
++02292                 depctl.b.eptype = ep->type;
++02293                 depctl.b.txfnum = ep->tx_fifo_num;
++02294 
++02295                 if (ep->type == DWC_OTG_EP_TYPE_ISOC) {
++02296                         depctl.b.setd0pid = 1;  // ??? 
++02297                 } else {
++02298                         depctl.b.setd0pid = 1;
++02299                 }
++02300                 depctl.b.usbactep = 1;
++02301 
++02302                 dwc_write_reg32(addr, depctl.d32);
++02303                 DWC_DEBUGPL(DBG_PCDV, "DEPCTL=%08x\n", dwc_read_reg32(addr));
++02304         }
++02305 
++02306         /* Enable the Interrupt for this EP */
++02307         if (core_if->multiproc_int_enable) {
++02308                 if (ep->is_in == 1) {
++02309                         diepmsk_data_t diepmsk = {.d32 = 0 };
++02310                         diepmsk.b.xfercompl = 1;
++02311                         diepmsk.b.timeout = 1;
++02312                         diepmsk.b.epdisabled = 1;
++02313                         diepmsk.b.ahberr = 1;
++02314                         diepmsk.b.intknepmis = 1;
++02315                         diepmsk.b.txfifoundrn = 1;      //?????
++02316 
++02317                         if (core_if->dma_desc_enable) {
++02318                                 diepmsk.b.bna = 1;
++02319                         }
++02320 /*                      
++02321                         if(core_if->dma_enable) {
++02322                                 doepmsk.b.nak = 1;
++02323                         }
++02324 */
++02325                         dwc_write_reg32(&dev_if->dev_global_regs->
++02326                                         diepeachintmsk[ep->num], diepmsk.d32);
++02327 
++02328                 } else {
++02329                         doepmsk_data_t doepmsk = {.d32 = 0 };
++02330                         doepmsk.b.xfercompl = 1;
++02331                         doepmsk.b.ahberr = 1;
++02332                         doepmsk.b.epdisabled = 1;
++02333 
++02334                         if (core_if->dma_desc_enable) {
++02335                                 doepmsk.b.bna = 1;
++02336                         }
++02337 /*                      
++02338                         doepmsk.b.babble = 1;
++02339                         doepmsk.b.nyet = 1;
++02340                         doepmsk.b.nak = 1;
++02341 */
++02342                         dwc_write_reg32(&dev_if->dev_global_regs->
++02343                                         doepeachintmsk[ep->num], doepmsk.d32);
++02344                 }
++02345                 dwc_modify_reg32(&dev_if->dev_global_regs->deachintmsk,
++02346                                  0, daintmsk.d32);
++02347         } else {
++02348                 dwc_modify_reg32(&dev_if->dev_global_regs->daintmsk,
++02349                                  0, daintmsk.d32);
++02350         }
++02351 
++02352         DWC_DEBUGPL(DBG_PCDV, "DAINTMSK=%0x\n",
++02353                     dwc_read_reg32(&dev_if->dev_global_regs->daintmsk));
++02354 
++02355         ep->stall_clear_flag = 0;
++02356         return;
++02357 }
++02358 
++02367 void dwc_otg_ep_deactivate(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
++02368 {
++02369         depctl_data_t depctl = {.d32 = 0 };
++02370         volatile uint32_t *addr;
++02371         daint_data_t daintmsk = {.d32 = 0 };
++02372 
++02373         /* Read DEPCTLn register */
++02374         if (ep->is_in == 1) {
++02375                 addr = &core_if->dev_if->in_ep_regs[ep->num]->diepctl;
++02376                 daintmsk.ep.in = 1 << ep->num;
++02377         } else {
++02378                 addr = &core_if->dev_if->out_ep_regs[ep->num]->doepctl;
++02379                 daintmsk.ep.out = 1 << ep->num;
++02380         }
++02381 
++02382         depctl.d32 = dwc_read_reg32(addr);
++02383 
++02384         depctl.b.usbactep = 0;
++02385 
++02386         if (core_if->dma_desc_enable)
++02387                 depctl.b.epdis = 1;
++02388 
++02389         dwc_write_reg32(addr, depctl.d32);
++02390 
++02391         /* Disable the Interrupt for this EP */
++02392         if (core_if->multiproc_int_enable) {
++02393                 dwc_modify_reg32(&core_if->dev_if->dev_global_regs->deachintmsk,
++02394                                  daintmsk.d32, 0);
++02395 
++02396                 if (ep->is_in == 1) {
++02397                         dwc_write_reg32(&core_if->dev_if->dev_global_regs->
++02398                                         diepeachintmsk[ep->num], 0);
++02399                 } else {
++02400                         dwc_write_reg32(&core_if->dev_if->dev_global_regs->
++02401                                         doepeachintmsk[ep->num], 0);
++02402                 }
++02403         } else {
++02404                 dwc_modify_reg32(&core_if->dev_if->dev_global_regs->daintmsk,
++02405                                  daintmsk.d32, 0);
++02406         }
++02407 }
++02408 
++02415 static void init_dma_desc_chain(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
++02416 {
++02417         dwc_otg_dev_dma_desc_t *dma_desc;
++02418         uint32_t offset;
++02419         uint32_t xfer_est;
++02420         int i;
++02421 
++02422         ep->desc_cnt = (ep->total_len / ep->maxxfer) +
++02423             ((ep->total_len % ep->maxxfer) ? 1 : 0);
++02424         if (!ep->desc_cnt)
++02425                 ep->desc_cnt = 1;
++02426 
++02427         dma_desc = ep->desc_addr;
++02428         xfer_est = ep->total_len;
++02429         offset = 0;
++02430         for (i = 0; i < ep->desc_cnt; ++i) {
++02432                 if (xfer_est > ep->maxxfer) {
++02433                         dma_desc->status.b.bs = BS_HOST_BUSY;
++02434                         dma_desc->status.b.l = 0;
++02435                         dma_desc->status.b.ioc = 0;
++02436                         dma_desc->status.b.sp = 0;
++02437                         dma_desc->status.b.bytes = ep->maxxfer;
++02438                         dma_desc->buf = ep->dma_addr + offset;
++02439                         dma_desc->status.b.bs = BS_HOST_READY;
++02440 
++02441                         xfer_est -= ep->maxxfer;
++02442                         offset += ep->maxxfer;
++02443                 } else {
++02444                         dma_desc->status.b.bs = BS_HOST_BUSY;
++02445                         dma_desc->status.b.l = 1;
++02446                         dma_desc->status.b.ioc = 1;
++02447                         if (ep->is_in) {
++02448                                 dma_desc->status.b.sp =
++02449                                     (xfer_est %
++02450                                      ep->maxpacket) ? 1 : ((ep->
++02451                                                             sent_zlp) ? 1 : 0);
++02452                                 dma_desc->status.b.bytes = xfer_est;
++02453                         } else {
++02454                                 dma_desc->status.b.bytes =
++02455                                     xfer_est + ((4 - (xfer_est & 0x3)) & 0x3);
++02456                         }
++02457 
++02458                         dma_desc->buf = ep->dma_addr + offset;
++02459                         dma_desc->status.b.bs = BS_HOST_READY;
++02460                 }
++02461                 dma_desc++;
++02462         }
++02463 }
++02464 
++02475 void dwc_otg_ep_start_transfer(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
++02476 {
++02477         depctl_data_t depctl;
++02478         deptsiz_data_t deptsiz;
++02479         gintmsk_data_t intr_mask = {.d32 = 0 };
++02480 
++02481         DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "%s()\n", __func__);
++02482         DWC_DEBUGPL(DBG_PCD, "ep%d-%s xfer_len=%d xfer_cnt=%d "
++02483                     "xfer_buff=%p start_xfer_buff=%p, total_len = %d\n",
++02484                     ep->num, (ep->is_in ? "IN" : "OUT"), ep->xfer_len,
++02485                     ep->xfer_count, ep->xfer_buff, ep->start_xfer_buff,
++02486                     ep->total_len);
++02487         /* IN endpoint */
++02488         if (ep->is_in == 1) {
++02489                 dwc_otg_dev_in_ep_regs_t *in_regs =
++02490                     core_if->dev_if->in_ep_regs[ep->num];
++02491 
++02492                 gnptxsts_data_t gtxstatus;
++02493 
++02494                 gtxstatus.d32 =
++02495                     dwc_read_reg32(&core_if->core_global_regs->gnptxsts);
++02496 
++02497                 if (core_if->en_multiple_tx_fifo == 0
++02498                     && gtxstatus.b.nptxqspcavail == 0) {
++02499 #ifdef DEBUG
++02500                         DWC_PRINTF("TX Queue Full (0x%0x)\n", gtxstatus.d32);
++02501 #endif
++02502                         return;
++02503                 }
++02504 
++02505                 depctl.d32 = dwc_read_reg32(&(in_regs->diepctl));
++02506                 deptsiz.d32 = dwc_read_reg32(&(in_regs->dieptsiz));
++02507 
++02508                 ep->xfer_len += (ep->maxxfer < (ep->total_len - ep->xfer_len)) ?
++02509                     ep->maxxfer : (ep->total_len - ep->xfer_len);
++02510 
++02511                 /* Zero Length Packet? */
++02512                 if ((ep->xfer_len - ep->xfer_count) == 0) {
++02513                         deptsiz.b.xfersize = 0;
++02514                         deptsiz.b.pktcnt = 1;
++02515                 } else {
++02516                         /* Program the transfer size and packet count
++02517                          *      as follows: xfersize = N * maxpacket +
++02518                          *      short_packet pktcnt = N + (short_packet
++02519                          *      exist ? 1 : 0)  
++02520                          */
++02521                         deptsiz.b.xfersize = ep->xfer_len - ep->xfer_count;
++02522                         deptsiz.b.pktcnt =
++02523                             (ep->xfer_len - ep->xfer_count - 1 +
++02524                              ep->maxpacket) / ep->maxpacket;
++02525                 }
++02526 
++02527                 /* Write the DMA register */
++02528                 if (core_if->dma_enable) {
++02529                         if (core_if->dma_desc_enable == 0) {
++02530                                 dwc_write_reg32(&in_regs->dieptsiz,
++02531                                                 deptsiz.d32);
++02532                                 dwc_write_reg32(&(in_regs->diepdma),
++02533                                                 (uint32_t) ep->dma_addr);
++02534                         } else {
++02535 #ifdef DWC_UTE_CFI
++02536                                 /* The descriptor chain should be already initialized by now */
++02537                                 if (ep->buff_mode != BM_STANDARD) {
++02538                                         dwc_write_reg32(&in_regs->diepdma,
++02539                                                         ep->descs_dma_addr);
++02540                                 } else {
++02541 #endif
++02542                                 init_dma_desc_chain(core_if, ep);
++02544                                 dwc_write_reg32(&in_regs->diepdma,
++02545                                                 ep->dma_desc_addr);
++02546 #ifdef DWC_UTE_CFI
++02547                         }
++02548 #endif
++02549                         }
++02550                 } else {
++02551                         dwc_write_reg32(&in_regs->dieptsiz, deptsiz.d32);
++02552                         if (ep->type != DWC_OTG_EP_TYPE_ISOC) {
++02558                                 if (core_if->en_multiple_tx_fifo == 0) {
++02559                                         intr_mask.b.nptxfempty = 1;
++02560                                         dwc_modify_reg32(&core_if->
++02561                                                          core_global_regs->
++02562                                                          gintmsk, intr_mask.d32,
++02563                                                          intr_mask.d32);
++02564                                 } else {
++02565                                         /* Enable the Tx FIFO Empty Interrupt for this EP */
++02566                                         if (ep->xfer_len > 0) {
++02567                                                 uint32_t fifoemptymsk = 0;
++02568                                                 fifoemptymsk = 1 << ep->num;
++02569                                                 dwc_modify_reg32(&core_if->
++02570                                                                  dev_if->
++02571                                                                  dev_global_regs->
++02572                                                                  dtknqr4_fifoemptymsk,
++02573                                                                  0,
++02574                                                                  fifoemptymsk);
++02575 
++02576                                         }
++02577                                 }
++02578                         }
++02579                 }
++02580 
++02581                 /* EP enable, IN data in FIFO */
++02582                 depctl.b.cnak = 1;
++02583                 depctl.b.epena = 1;
++02584                 dwc_write_reg32(&in_regs->diepctl, depctl.d32);
++02585 
++02586                 depctl.d32 =
++02587                     dwc_read_reg32(&core_if->dev_if->in_ep_regs[0]->diepctl);
++02588                 depctl.b.nextep = ep->num;
++02589                 dwc_write_reg32(&core_if->dev_if->in_ep_regs[0]->diepctl,
++02590                                 depctl.d32);
++02591 
++02592         } else {
++02593                 /* OUT endpoint */
++02594                 dwc_otg_dev_out_ep_regs_t *out_regs =
++02595                     core_if->dev_if->out_ep_regs[ep->num];
++02596 
++02597                 depctl.d32 = dwc_read_reg32(&(out_regs->doepctl));
++02598                 deptsiz.d32 = dwc_read_reg32(&(out_regs->doeptsiz));
++02599 
++02600                 ep->xfer_len += (ep->maxxfer < (ep->total_len - ep->xfer_len)) ?
++02601                     ep->maxxfer : (ep->total_len - ep->xfer_len);
++02602 
++02603                 /* Program the transfer size and packet count as follows:
++02604                  * 
++02605                  *      pktcnt = N                                                                                 
++02606                  *      xfersize = N * maxpacket
++02607                  */
++02608                 if ((ep->xfer_len - ep->xfer_count) == 0) {
++02609                         /* Zero Length Packet */
++02610                         deptsiz.b.xfersize = ep->maxpacket;
++02611                         deptsiz.b.pktcnt = 1;
++02612                 } else {
++02613                         deptsiz.b.pktcnt =
++02614                             (ep->xfer_len - ep->xfer_count +
++02615                              (ep->maxpacket - 1)) / ep->maxpacket;
++02616                         ep->xfer_len =
++02617                             deptsiz.b.pktcnt * ep->maxpacket + ep->xfer_count;
++02618                         deptsiz.b.xfersize = ep->xfer_len - ep->xfer_count;
++02619                 }
++02620 
++02621                 DWC_DEBUGPL(DBG_PCDV, "ep%d xfersize=%d pktcnt=%d\n",
++02622                             ep->num, deptsiz.b.xfersize, deptsiz.b.pktcnt);
++02623 
++02624                 if (core_if->dma_enable) {
++02625                         if (!core_if->dma_desc_enable) {
++02626                                 dwc_write_reg32(&out_regs->doeptsiz,
++02627                                                 deptsiz.d32);
++02628 
++02629                                 dwc_write_reg32(&(out_regs->doepdma),
++02630                                                 (uint32_t) ep->dma_addr);
++02631                         } else {
++02632 #ifdef DWC_UTE_CFI
++02633                                 /* The descriptor chain should be already initialized by now */
++02634                                 if (ep->buff_mode != BM_STANDARD) {
++02635                                         dwc_write_reg32(&out_regs->doepdma,
++02636                                                         ep->descs_dma_addr);
++02637                                 } else {
++02638 #endif
++02639 
++02640                                 init_dma_desc_chain(core_if, ep);
++02641 
++02643                                 dwc_write_reg32(&out_regs->doepdma,
++02644                                                 ep->dma_desc_addr);
++02645 #ifdef DWC_UTE_CFI
++02646                                 }
++02647 #endif
++02648                         }
++02649                 } else {
++02650                         dwc_write_reg32(&out_regs->doeptsiz, deptsiz.d32);
++02651                 }
++02652 
++02653                 /* EP enable */
++02654                 depctl.b.cnak = 1;
++02655                 depctl.b.epena = 1;
++02656 
++02657                 dwc_write_reg32(&out_regs->doepctl, depctl.d32);
++02658 
++02659                 DWC_DEBUGPL(DBG_PCD, "DOEPCTL=%08x DOEPTSIZ=%08x\n",
++02660                             dwc_read_reg32(&out_regs->doepctl),
++02661                             dwc_read_reg32(&out_regs->doeptsiz));
++02662                 DWC_DEBUGPL(DBG_PCD, "DAINTMSK=%08x GINTMSK=%08x\n",
++02663                             dwc_read_reg32(&core_if->dev_if->dev_global_regs->
++02664                                            daintmsk),
++02665                             dwc_read_reg32(&core_if->core_global_regs->
++02666                                            gintmsk));
++02667         }
++02668 }
++02669 
++02678 void dwc_otg_ep_start_zl_transfer(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
++02679 {
++02680 
++02681         depctl_data_t depctl;
++02682         deptsiz_data_t deptsiz;
++02683         gintmsk_data_t intr_mask = {.d32 = 0 };
++02684 
++02685         DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "%s()\n", __func__);
++02686         DWC_PRINTF("zero length transfer is called\n");
++02687 
++02688         /* IN endpoint */
++02689         if (ep->is_in == 1) {
++02690                 dwc_otg_dev_in_ep_regs_t *in_regs =
++02691                     core_if->dev_if->in_ep_regs[ep->num];
++02692 
++02693                 depctl.d32 = dwc_read_reg32(&(in_regs->diepctl));
++02694                 deptsiz.d32 = dwc_read_reg32(&(in_regs->dieptsiz));
++02695 
++02696                 deptsiz.b.xfersize = 0;
++02697                 deptsiz.b.pktcnt = 1;
++02698 
++02699                 /* Write the DMA register */
++02700                 if (core_if->dma_enable) {
++02701                         if (core_if->dma_desc_enable == 0) {
++02702                                 dwc_write_reg32(&in_regs->dieptsiz,
++02703                                                 deptsiz.d32);
++02704                                 dwc_write_reg32(&(in_regs->diepdma),
++02705                                                 (uint32_t) ep->dma_addr);
++02706                         }
++02707                 } else {
++02708                         dwc_write_reg32(&in_regs->dieptsiz, deptsiz.d32);
++02714                         if (core_if->en_multiple_tx_fifo == 0) {
++02715                                 intr_mask.b.nptxfempty = 1;
++02716                                 dwc_modify_reg32(&core_if->core_global_regs->
++02717                                                  gintmsk, intr_mask.d32,
++02718                                                  intr_mask.d32);
++02719                         } else {
++02720                                 /* Enable the Tx FIFO Empty Interrupt for this EP */
++02721                                 if (ep->xfer_len > 0) {
++02722                                         uint32_t fifoemptymsk = 0;
++02723                                         fifoemptymsk = 1 << ep->num;
++02724                                         dwc_modify_reg32(&core_if->dev_if->
++02725                                                          dev_global_regs->
++02726                                                          dtknqr4_fifoemptymsk,
++02727                                                          0, fifoemptymsk);
++02728                                 }
++02729                         }
++02730                 }
++02731 
++02732                 /* EP enable, IN data in FIFO */
++02733                 depctl.b.cnak = 1;
++02734                 depctl.b.epena = 1;
++02735                 dwc_write_reg32(&in_regs->diepctl, depctl.d32);
++02736 
++02737                 depctl.d32 =
++02738                     dwc_read_reg32(&core_if->dev_if->in_ep_regs[0]->diepctl);
++02739                 depctl.b.nextep = ep->num;
++02740                 dwc_write_reg32(&core_if->dev_if->in_ep_regs[0]->diepctl,
++02741                                 depctl.d32);
++02742 
++02743         } else {
++02744                 /* OUT endpoint */
++02745                 dwc_otg_dev_out_ep_regs_t *out_regs =
++02746                     core_if->dev_if->out_ep_regs[ep->num];
++02747 
++02748                 depctl.d32 = dwc_read_reg32(&(out_regs->doepctl));
++02749                 deptsiz.d32 = dwc_read_reg32(&(out_regs->doeptsiz));
++02750 
++02751                 /* Zero Length Packet */
++02752                 deptsiz.b.xfersize = ep->maxpacket;
++02753                 deptsiz.b.pktcnt = 1;
++02754 
++02755                 if (core_if->dma_enable) {
++02756                         if (!core_if->dma_desc_enable) {
++02757                                 dwc_write_reg32(&out_regs->doeptsiz,
++02758                                                 deptsiz.d32);
++02759 
++02760                                 dwc_write_reg32(&(out_regs->doepdma),
++02761                                                 (uint32_t) ep->dma_addr);
++02762                         }
++02763                 } else {
++02764                         dwc_write_reg32(&out_regs->doeptsiz, deptsiz.d32);
++02765                 }
++02766 
++02767                 /* EP enable */
++02768                 depctl.b.cnak = 1;
++02769                 depctl.b.epena = 1;
++02770 
++02771                 dwc_write_reg32(&out_regs->doepctl, depctl.d32);
++02772 
++02773         }
++02774 }
++02775 
++02785 void dwc_otg_ep0_start_transfer(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
++02786 {
++02787         depctl_data_t depctl;
++02788         deptsiz0_data_t deptsiz;
++02789         gintmsk_data_t intr_mask = {.d32 = 0 };
++02790         dwc_otg_dev_dma_desc_t *dma_desc;
++02791 
++02792         DWC_DEBUGPL(DBG_PCD, "ep%d-%s xfer_len=%d xfer_cnt=%d "
++02793                     "xfer_buff=%p start_xfer_buff=%p \n",
++02794                     ep->num, (ep->is_in ? "IN" : "OUT"), ep->xfer_len,
++02795                     ep->xfer_count, ep->xfer_buff, ep->start_xfer_buff);
++02796 
++02797         ep->total_len = ep->xfer_len;
++02798 
++02799         /* IN endpoint */
++02800         if (ep->is_in == 1) {
++02801                 dwc_otg_dev_in_ep_regs_t *in_regs =
++02802                     core_if->dev_if->in_ep_regs[0];
++02803 
++02804                 gnptxsts_data_t gtxstatus;
++02805 
++02806                 gtxstatus.d32 =
++02807                     dwc_read_reg32(&core_if->core_global_regs->gnptxsts);
++02808 
++02809                 if (core_if->en_multiple_tx_fifo == 0
++02810                     && gtxstatus.b.nptxqspcavail == 0) {
++02811 #ifdef DEBUG
++02812                         deptsiz.d32 = dwc_read_reg32(&in_regs->dieptsiz);
++02813                         DWC_DEBUGPL(DBG_PCD, "DIEPCTL0=%0x\n",
++02814                                     dwc_read_reg32(&in_regs->diepctl));
++02815                         DWC_DEBUGPL(DBG_PCD, "DIEPTSIZ0=%0x (sz=%d, pcnt=%d)\n",
++02816                                     deptsiz.d32,
++02817                                     deptsiz.b.xfersize, deptsiz.b.pktcnt);
++02818                         DWC_PRINTF("TX Queue or FIFO Full (0x%0x)\n",
++02819                                    gtxstatus.d32);
++02820 #endif
++02821                         return;
++02822                 }
++02823 
++02824                 depctl.d32 = dwc_read_reg32(&in_regs->diepctl);
++02825                 deptsiz.d32 = dwc_read_reg32(&in_regs->dieptsiz);
++02826 
++02827                 /* Zero Length Packet? */
++02828                 if (ep->xfer_len == 0) {
++02829                         deptsiz.b.xfersize = 0;
++02830                         deptsiz.b.pktcnt = 1;
++02831                 } else {
++02832                         /* Program the transfer size and packet count
++02833                          *      as follows: xfersize = N * maxpacket +
++02834                          *      short_packet pktcnt = N + (short_packet
++02835                          *      exist ? 1 : 0)  
++02836                          */
++02837                         if (ep->xfer_len > ep->maxpacket) {
++02838                                 ep->xfer_len = ep->maxpacket;
++02839                                 deptsiz.b.xfersize = ep->maxpacket;
++02840                         } else {
++02841                                 deptsiz.b.xfersize = ep->xfer_len;
++02842                         }
++02843                         deptsiz.b.pktcnt = 1;
++02844 
++02845                 }
++02846                 DWC_DEBUGPL(DBG_PCDV,
++02847                             "IN len=%d  xfersize=%d pktcnt=%d [%08x]\n",
++02848                             ep->xfer_len, deptsiz.b.xfersize, deptsiz.b.pktcnt,
++02849                             deptsiz.d32);
++02850 
++02851                 /* Write the DMA register */
++02852                 if (core_if->dma_enable) {
++02853                         if (core_if->dma_desc_enable == 0) {
++02854                                 dwc_write_reg32(&in_regs->dieptsiz,
++02855                                                 deptsiz.d32);
++02856 
++02857                                 dwc_write_reg32(&(in_regs->diepdma),
++02858                                                 (uint32_t) ep->dma_addr);
++02859                         } else {
++02860                                 dma_desc = core_if->dev_if->in_desc_addr;
++02861 
++02863                                 dma_desc->status.b.bs = BS_HOST_BUSY;
++02864                                 dma_desc->status.b.l = 1;
++02865                                 dma_desc->status.b.ioc = 1;
++02866                                 dma_desc->status.b.sp =
++02867                                     (ep->xfer_len == ep->maxpacket) ? 0 : 1;
++02868                                 dma_desc->status.b.bytes = ep->xfer_len;
++02869                                 dma_desc->buf = ep->dma_addr;
++02870                                 dma_desc->status.b.bs = BS_HOST_READY;
++02871 
++02873                                 dwc_write_reg32(&in_regs->diepdma,
++02874                                                 core_if->dev_if->
++02875                                                 dma_in_desc_addr);
++02876                         }
++02877                 } else {
++02878                         dwc_write_reg32(&in_regs->dieptsiz, deptsiz.d32);
++02879                 }
++02880 
++02881                 /* EP enable, IN data in FIFO */
++02882                 depctl.b.cnak = 1;
++02883                 depctl.b.epena = 1;
++02884                 dwc_write_reg32(&in_regs->diepctl, depctl.d32);
++02885 
++02890                 if (!core_if->dma_enable) {
++02891                         if (core_if->en_multiple_tx_fifo == 0) {
++02892                                 intr_mask.b.nptxfempty = 1;
++02893                                 dwc_modify_reg32(&core_if->core_global_regs->
++02894                                                  gintmsk, intr_mask.d32,
++02895                                                  intr_mask.d32);
++02896                         } else {
++02897                                 /* Enable the Tx FIFO Empty Interrupt for this EP */
++02898                                 if (ep->xfer_len > 0) {
++02899                                         uint32_t fifoemptymsk = 0;
++02900                                         fifoemptymsk |= 1 << ep->num;
++02901                                         dwc_modify_reg32(&core_if->dev_if->
++02902                                                          dev_global_regs->
++02903                                                          dtknqr4_fifoemptymsk,
++02904                                                          0, fifoemptymsk);
++02905                                 }
++02906                         }
++02907                 }
++02908         } else {
++02909                 /* OUT endpoint */
++02910                 dwc_otg_dev_out_ep_regs_t *out_regs =
++02911                     core_if->dev_if->out_ep_regs[0];
++02912 
++02913                 depctl.d32 = dwc_read_reg32(&out_regs->doepctl);
++02914                 deptsiz.d32 = dwc_read_reg32(&out_regs->doeptsiz);
++02915 
++02916                 /* Program the transfer size and packet count as follows:
++02917                  *      xfersize = N * (maxpacket + 4 - (maxpacket % 4))
++02918                  *      pktcnt = N                                                                                      */
++02919                 /* Zero Length Packet */
++02920                 deptsiz.b.xfersize = ep->maxpacket;
++02921                 deptsiz.b.pktcnt = 1;
++02922 
++02923                 DWC_DEBUGPL(DBG_PCDV, "len=%d  xfersize=%d pktcnt=%d\n",
++02924                             ep->xfer_len, deptsiz.b.xfersize, deptsiz.b.pktcnt);
++02925 
++02926                 if (core_if->dma_enable) {
++02927                         if (!core_if->dma_desc_enable) {
++02928                                 dwc_write_reg32(&out_regs->doeptsiz,
++02929                                                 deptsiz.d32);
++02930 
++02931                                 dwc_write_reg32(&(out_regs->doepdma),
++02932                                                 (uint32_t) ep->dma_addr);
++02933                         } else {
++02934                                 dma_desc = core_if->dev_if->out_desc_addr;
++02935 
++02937                                 dma_desc->status.b.bs = BS_HOST_BUSY;
++02938                                 dma_desc->status.b.l = 1;
++02939                                 dma_desc->status.b.ioc = 1;
++02940                                 dma_desc->status.b.bytes = ep->maxpacket;
++02941                                 dma_desc->buf = ep->dma_addr;
++02942                                 dma_desc->status.b.bs = BS_HOST_READY;
++02943 
++02945                                 dwc_write_reg32(&out_regs->doepdma,
++02946                                                 core_if->dev_if->
++02947                                                 dma_out_desc_addr);
++02948                         }
++02949                 } else {
++02950                         dwc_write_reg32(&out_regs->doeptsiz, deptsiz.d32);
++02951                 }
++02952 
++02953                 /* EP enable */
++02954                 depctl.b.cnak = 1;
++02955                 depctl.b.epena = 1;
++02956                 dwc_write_reg32(&(out_regs->doepctl), depctl.d32);
++02957         }
++02958 }
++02959 
++02969 void dwc_otg_ep0_continue_transfer(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
++02970 {
++02971         depctl_data_t depctl;
++02972         deptsiz0_data_t deptsiz;
++02973         gintmsk_data_t intr_mask = {.d32 = 0 };
++02974         dwc_otg_dev_dma_desc_t *dma_desc;
++02975 
++02976         if (ep->is_in == 1) {
++02977                 dwc_otg_dev_in_ep_regs_t *in_regs =
++02978                     core_if->dev_if->in_ep_regs[0];
++02979                 gnptxsts_data_t tx_status = {.d32 = 0 };
++02980 
++02981                 tx_status.d32 =
++02982                     dwc_read_reg32(&core_if->core_global_regs->gnptxsts);
++02986                 depctl.d32 = dwc_read_reg32(&in_regs->diepctl);
++02987                 deptsiz.d32 = dwc_read_reg32(&in_regs->dieptsiz);
++02988 
++02989                 /* Program the transfer size and packet count
++02990                  *      as follows: xfersize = N * maxpacket +
++02991                  *      short_packet pktcnt = N + (short_packet
++02992                  *      exist ? 1 : 0)  
++02993                  */
++02994 
++02995                 if (core_if->dma_desc_enable == 0) {
++02996                         deptsiz.b.xfersize =
++02997                             (ep->total_len - ep->xfer_count) >
++02998                             ep->maxpacket ? ep->maxpacket : (ep->total_len -
++02999                                                              ep->xfer_count);
++03000                         deptsiz.b.pktcnt = 1;
++03001                         if (core_if->dma_enable == 0) {
++03002                                 ep->xfer_len += deptsiz.b.xfersize;
++03003                         } else {
++03004                                 ep->xfer_len = deptsiz.b.xfersize;
++03005                         }
++03006                         dwc_write_reg32(&in_regs->dieptsiz, deptsiz.d32);
++03007                 } else {
++03008                         ep->xfer_len =
++03009                             (ep->total_len - ep->xfer_count) >
++03010                             ep->maxpacket ? ep->maxpacket : (ep->total_len -
++03011                                                              ep->xfer_count);
++03012 
++03013                         dma_desc = core_if->dev_if->in_desc_addr;
++03014 
++03016                         dma_desc->status.b.bs = BS_HOST_BUSY;
++03017                         dma_desc->status.b.l = 1;
++03018                         dma_desc->status.b.ioc = 1;
++03019                         dma_desc->status.b.sp =
++03020                             (ep->xfer_len == ep->maxpacket) ? 0 : 1;
++03021                         dma_desc->status.b.bytes = ep->xfer_len;
++03022                         dma_desc->buf = ep->dma_addr;
++03023                         dma_desc->status.b.bs = BS_HOST_READY;
++03024 
++03026                         dwc_write_reg32(&in_regs->diepdma,
++03027                                         core_if->dev_if->dma_in_desc_addr);
++03028                 }
++03029 
++03030                 DWC_DEBUGPL(DBG_PCDV,
++03031                             "IN len=%d  xfersize=%d pktcnt=%d [%08x]\n",
++03032                             ep->xfer_len, deptsiz.b.xfersize, deptsiz.b.pktcnt,
++03033                             deptsiz.d32);
++03034 
++03035                 /* Write the DMA register */
++03036                 if (core_if->hwcfg2.b.architecture == DWC_INT_DMA_ARCH) {
++03037                         if (core_if->dma_desc_enable == 0)
++03038                                 dwc_write_reg32(&(in_regs->diepdma),
++03039                                                 (uint32_t) ep->dma_addr);
++03040                 }
++03041 
++03042                 /* EP enable, IN data in FIFO */
++03043                 depctl.b.cnak = 1;
++03044                 depctl.b.epena = 1;
++03045                 dwc_write_reg32(&in_regs->diepctl, depctl.d32);
++03046 
++03051                 if (!core_if->dma_enable) {
++03052                         if (core_if->en_multiple_tx_fifo == 0) {
++03053                                 /* First clear it from GINTSTS */
++03054                                 intr_mask.b.nptxfempty = 1;
++03055                                 dwc_modify_reg32(&core_if->core_global_regs->
++03056                                                  gintmsk, intr_mask.d32,
++03057                                                  intr_mask.d32);
++03058 
++03059                         } else {
++03060                                 /* Enable the Tx FIFO Empty Interrupt for this EP */
++03061                                 if (ep->xfer_len > 0) {
++03062                                         uint32_t fifoemptymsk = 0;
++03063                                         fifoemptymsk |= 1 << ep->num;
++03064                                         dwc_modify_reg32(&core_if->dev_if->
++03065                                                          dev_global_regs->
++03066                                                          dtknqr4_fifoemptymsk,
++03067                                                          0, fifoemptymsk);
++03068                                 }
++03069                         }
++03070                 }
++03071         } else {
++03072                 dwc_otg_dev_out_ep_regs_t *out_regs =
++03073                     core_if->dev_if->out_ep_regs[0];
++03074 
++03075                 depctl.d32 = dwc_read_reg32(&out_regs->doepctl);
++03076                 deptsiz.d32 = dwc_read_reg32(&out_regs->doeptsiz);
++03077 
++03078                 /* Program the transfer size and packet count
++03079                  *      as follows: xfersize = N * maxpacket +
++03080                  *      short_packet pktcnt = N + (short_packet
++03081                  *      exist ? 1 : 0)  
++03082                  */
++03083                 deptsiz.b.xfersize = ep->maxpacket;
++03084                 deptsiz.b.pktcnt = 1;
++03085 
++03086                 if (core_if->dma_desc_enable == 0) {
++03087                         dwc_write_reg32(&out_regs->doeptsiz, deptsiz.d32);
++03088                 } else {
++03089                         dma_desc = core_if->dev_if->out_desc_addr;
++03090 
++03092                         dma_desc->status.b.bs = BS_HOST_BUSY;
++03093                         dma_desc->status.b.l = 1;
++03094                         dma_desc->status.b.ioc = 1;
++03095                         dma_desc->status.b.bytes = ep->maxpacket;
++03096                         dma_desc->buf = ep->dma_addr;
++03097                         dma_desc->status.b.bs = BS_HOST_READY;
++03098 
++03100                         dwc_write_reg32(&out_regs->doepdma,
++03101                                         core_if->dev_if->dma_out_desc_addr);
++03102                 }
++03103 
++03104                 DWC_DEBUGPL(DBG_PCDV,
++03105                             "IN len=%d  xfersize=%d pktcnt=%d [%08x]\n",
++03106                             ep->xfer_len, deptsiz.b.xfersize, deptsiz.b.pktcnt,
++03107                             deptsiz.d32);
++03108 
++03109                 /* Write the DMA register */
++03110                 if (core_if->hwcfg2.b.architecture == DWC_INT_DMA_ARCH) {
++03111                         if (core_if->dma_desc_enable == 0)
++03112                                 dwc_write_reg32(&(out_regs->doepdma),
++03113                                                 (uint32_t) ep->dma_addr);
++03114                 }
++03115 
++03116                 /* EP enable, IN data in FIFO */
++03117                 depctl.b.cnak = 1;
++03118                 depctl.b.epena = 1;
++03119                 dwc_write_reg32(&out_regs->doepctl, depctl.d32);
++03120 
++03121         }
++03122 }
++03123 
++03124 #ifdef DEBUG
++03125 void dump_msg(const u8 * buf, unsigned int length)
++03126 {
++03127         unsigned int start, num, i;
++03128         char line[52], *p;
++03129 
++03130         if (length >= 512)
++03131                 return;
++03132         start = 0;
++03133         while (length > 0) {
++03134                 num = length < 16u ? length : 16u;
++03135                 p = line;
++03136                 for (i = 0; i < num; ++i) {
++03137                         if (i == 8)
++03138                                 *p++ = ' ';
++03139                         DWC_SPRINTF(p, " %02x", buf[i]);
++03140                         p += 3;
++03141                 }
++03142                 *p = 0;
++03143                 DWC_PRINTF("%6x: %s\n", start, line);
++03144                 buf += num;
++03145                 start += num;
++03146                 length -= num;
++03147         }
++03148 }
++03149 #else
++03150 static inline void dump_msg(const u8 * buf, unsigned int length)
++03151 {
++03152 }
++03153 #endif
++03154 
++03165 void dwc_otg_ep_write_packet(dwc_otg_core_if_t * core_if, dwc_ep_t * ep,
++03166                              int dma)
++03167 {
++03183         uint32_t i;
++03184         uint32_t byte_count;
++03185         uint32_t dword_count;
++03186         uint32_t *fifo;
++03187         uint32_t *data_buff = (uint32_t *) ep->xfer_buff;
++03188 
++03189         DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "%s(%p,%p)\n", __func__, core_if,
++03190                     ep);
++03191         if (ep->xfer_count >= ep->xfer_len) {
++03192                 DWC_WARN("%s() No data for EP%d!!!\n", __func__, ep->num);
++03193                 return;
++03194         }
++03195 
++03196         /* Find the byte length of the packet either short packet or MPS */
++03197         if ((ep->xfer_len - ep->xfer_count) < ep->maxpacket) {
++03198                 byte_count = ep->xfer_len - ep->xfer_count;
++03199         } else {
++03200                 byte_count = ep->maxpacket;
++03201         }
++03202 
++03203         /* Find the DWORD length, padded by extra bytes as neccessary if MPS
++03204          * is not a multiple of DWORD */
++03205         dword_count = (byte_count + 3) / 4;
++03206 
++03207 #ifdef VERBOSE
++03208         dump_msg(ep->xfer_buff, byte_count);
++03209 #endif
++03210 
++03214         fifo = core_if->data_fifo[ep->num];
++03215 
++03216         DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "fifo=%p buff=%p *p=%08x bc=%d\n",
++03217                     fifo, data_buff, *data_buff, byte_count);
++03218 
++03219         if (!dma) {
++03220                 for (i = 0; i < dword_count; i++, data_buff++) {
++03221                         dwc_write_reg32(fifo, *data_buff);
++03222                 }
++03223         }
++03224 
++03225         ep->xfer_count += byte_count;
++03226         ep->xfer_buff += byte_count;
++03227         ep->dma_addr += byte_count;
++03228 }
++03229 
++03236 void dwc_otg_ep_set_stall(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
++03237 {
++03238         depctl_data_t depctl;
++03239         volatile uint32_t *depctl_addr;
++03240 
++03241         DWC_DEBUGPL(DBG_PCD, "%s ep%d-%s\n", __func__, ep->num,
++03242                     (ep->is_in ? "IN" : "OUT"));
++03243 
++03244         if (ep->is_in == 1) {
++03245                 depctl_addr = &(core_if->dev_if->in_ep_regs[ep->num]->diepctl);
++03246                 depctl.d32 = dwc_read_reg32(depctl_addr);
++03247 
++03248                 /* set the disable and stall bits */
++03249                 if (depctl.b.epena) {
++03250                         depctl.b.epdis = 1;
++03251                 }
++03252                 depctl.b.stall = 1;
++03253                 dwc_write_reg32(depctl_addr, depctl.d32);
++03254         } else {
++03255                 depctl_addr = &(core_if->dev_if->out_ep_regs[ep->num]->doepctl);
++03256                 depctl.d32 = dwc_read_reg32(depctl_addr);
++03257 
++03258                 /* set the stall bit */
++03259                 depctl.b.stall = 1;
++03260                 dwc_write_reg32(depctl_addr, depctl.d32);
++03261         }
++03262 
++03263         DWC_DEBUGPL(DBG_PCD, "DEPCTL=%0x\n", dwc_read_reg32(depctl_addr));
++03264 
++03265         return;
++03266 }
++03267 
++03274 void dwc_otg_ep_clear_stall(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
++03275 {
++03276         depctl_data_t depctl;
++03277         volatile uint32_t *depctl_addr;
++03278 
++03279         DWC_DEBUGPL(DBG_PCD, "%s ep%d-%s\n", __func__, ep->num,
++03280                     (ep->is_in ? "IN" : "OUT"));
++03281 
++03282         if (ep->is_in == 1) {
++03283                 depctl_addr = &(core_if->dev_if->in_ep_regs[ep->num]->diepctl);
++03284         } else {
++03285                 depctl_addr = &(core_if->dev_if->out_ep_regs[ep->num]->doepctl);
++03286         }
++03287 
++03288         depctl.d32 = dwc_read_reg32(depctl_addr);
++03289 
++03290         /* clear the stall bits */
++03291         depctl.b.stall = 0;
++03292 
++03293         /* 
++03294          * USB Spec 9.4.5: For endpoints using data toggle, regardless
++03295          * of whether an endpoint has the Halt feature set, a
++03296          * ClearFeature(ENDPOINT_HALT) request always results in the
++03297          * data toggle being reinitialized to DATA0.
++03298          */
++03299         if (ep->type == DWC_OTG_EP_TYPE_INTR ||
++03300             ep->type == DWC_OTG_EP_TYPE_BULK) {
++03301                 depctl.b.setd0pid = 1;  /* DATA0 */
++03302         }
++03303 
++03304         dwc_write_reg32(depctl_addr, depctl.d32);
++03305         DWC_DEBUGPL(DBG_PCD, "DEPCTL=%0x\n", dwc_read_reg32(depctl_addr));
++03306         return;
++03307 }
++03308 
++03317 void dwc_otg_read_packet(dwc_otg_core_if_t * core_if,
++03318                          uint8_t * dest, uint16_t bytes)
++03319 {
++03320         int i;
++03321         int word_count = (bytes + 3) / 4;
++03322 
++03323         volatile uint32_t *fifo = core_if->data_fifo[0];
++03324         uint32_t *data_buff = (uint32_t *) dest;
++03325 
++03332         DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "%s(%p,%p,%d)\n", __func__,
++03333                     core_if, dest, bytes);
++03334 
++03335         for (i = 0; i < word_count; i++, data_buff++) {
++03336                 *data_buff = dwc_read_reg32(fifo);
++03337         }
++03338 
++03339         return;
++03340 }
++03341 
++03347 void dwc_otg_dump_dev_registers(dwc_otg_core_if_t * core_if)
++03348 {
++03349         int i;
++03350         volatile uint32_t *addr;
++03351 
++03352         DWC_PRINTF("Device Global Registers\n");
++03353         addr = &core_if->dev_if->dev_global_regs->dcfg;
++03354         DWC_PRINTF("DCFG                 @0x%08X : 0x%08X\n", (uint32_t) addr,
++03355                    dwc_read_reg32(addr));
++03356         addr = &core_if->dev_if->dev_global_regs->dctl;
++03357         DWC_PRINTF("DCTL                 @0x%08X : 0x%08X\n", (uint32_t) addr,
++03358                    dwc_read_reg32(addr));
++03359         addr = &core_if->dev_if->dev_global_regs->dsts;
++03360         DWC_PRINTF("DSTS                 @0x%08X : 0x%08X\n", (uint32_t) addr,
++03361                    dwc_read_reg32(addr));
++03362         addr = &core_if->dev_if->dev_global_regs->diepmsk;
++03363         DWC_PRINTF("DIEPMSK      @0x%08X : 0x%08X\n", (uint32_t) addr,
++03364                    dwc_read_reg32(addr));
++03365         addr = &core_if->dev_if->dev_global_regs->doepmsk;
++03366         DWC_PRINTF("DOEPMSK      @0x%08X : 0x%08X\n", (uint32_t) addr,
++03367                    dwc_read_reg32(addr));
++03368         addr = &core_if->dev_if->dev_global_regs->daint;
++03369         DWC_PRINTF("DAINT        @0x%08X : 0x%08X\n", (uint32_t) addr,
++03370                    dwc_read_reg32(addr));
++03371         addr = &core_if->dev_if->dev_global_regs->daintmsk;
++03372         DWC_PRINTF("DAINTMSK     @0x%08X : 0x%08X\n", (uint32_t) addr,
++03373                    dwc_read_reg32(addr));
++03374         addr = &core_if->dev_if->dev_global_regs->dtknqr1;
++03375         DWC_PRINTF("DTKNQR1      @0x%08X : 0x%08X\n", (uint32_t) addr,
++03376                    dwc_read_reg32(addr));
++03377         if (core_if->hwcfg2.b.dev_token_q_depth > 6) {
++03378                 addr = &core_if->dev_if->dev_global_regs->dtknqr2;
++03379                 DWC_PRINTF("DTKNQR2      @0x%08X : 0x%08X\n",
++03380                            (uint32_t) addr, dwc_read_reg32(addr));
++03381         }
++03382 
++03383         addr = &core_if->dev_if->dev_global_regs->dvbusdis;
++03384         DWC_PRINTF("DVBUSID      @0x%08X : 0x%08X\n", (uint32_t) addr,
++03385                    dwc_read_reg32(addr));
++03386 
++03387         addr = &core_if->dev_if->dev_global_regs->dvbuspulse;
++03388         DWC_PRINTF("DVBUSPULSE  @0x%08X : 0x%08X\n",
++03389                    (uint32_t) addr, dwc_read_reg32(addr));
++03390 
++03391                 addr = &core_if->dev_if->dev_global_regs->dtknqr3_dthrctl;
++03392                 DWC_PRINTF("DTKNQR3_DTHRCTL      @0x%08X : 0x%08X\n",
++03393                            (uint32_t) addr, dwc_read_reg32(addr));
++03394 
++03395         if (core_if->hwcfg2.b.dev_token_q_depth > 22) {
++03396                 addr = &core_if->dev_if->dev_global_regs->dtknqr4_fifoemptymsk;
++03397                 DWC_PRINTF("DTKNQR4      @0x%08X : 0x%08X\n",
++03398                            (uint32_t) addr, dwc_read_reg32(addr));
++03399         }
++03400 
++03401         addr = &core_if->dev_if->dev_global_regs->dtknqr4_fifoemptymsk;
++03402         DWC_PRINTF("FIFOEMPMSK   @0x%08X : 0x%08X\n", (uint32_t) addr,
++03403                    dwc_read_reg32(addr));
++03404 
++03405         addr = &core_if->dev_if->dev_global_regs->deachint;
++03406         DWC_PRINTF("DEACHINT     @0x%08X : 0x%08X\n", (uint32_t) addr,
++03407                    dwc_read_reg32(addr));
++03408         addr = &core_if->dev_if->dev_global_regs->deachintmsk;
++03409         DWC_PRINTF("DEACHINTMSK  @0x%08X : 0x%08X\n", (uint32_t) addr,
++03410                    dwc_read_reg32(addr));
++03411 
++03412         for (i = 0; i <= core_if->dev_if->num_in_eps; i++) {
++03413                 addr = &core_if->dev_if->dev_global_regs->diepeachintmsk[i];
++03414                 DWC_PRINTF("DIEPEACHINTMSK[%d]   @0x%08X : 0x%08X\n", i,
++03415                            (uint32_t) addr, dwc_read_reg32(addr));
++03416         }
++03417 
++03418         for (i = 0; i <= core_if->dev_if->num_out_eps; i++) {
++03419                 addr = &core_if->dev_if->dev_global_regs->doepeachintmsk[i];
++03420                 DWC_PRINTF("DOEPEACHINTMSK[%d]   @0x%08X : 0x%08X\n", i,
++03421                            (uint32_t) addr, dwc_read_reg32(addr));
++03422         }
++03423 
++03424         for (i = 0; i <= core_if->dev_if->num_in_eps; i++) {
++03425                 DWC_PRINTF("Device IN EP %d Registers\n", i);
++03426                 addr = &core_if->dev_if->in_ep_regs[i]->diepctl;
++03427                 DWC_PRINTF("DIEPCTL      @0x%08X : 0x%08X\n", (uint32_t) addr,
++03428                            dwc_read_reg32(addr));
++03429                 addr = &core_if->dev_if->in_ep_regs[i]->diepint;
++03430                 DWC_PRINTF("DIEPINT      @0x%08X : 0x%08X\n", (uint32_t) addr,
++03431                            dwc_read_reg32(addr));
++03432                 addr = &core_if->dev_if->in_ep_regs[i]->dieptsiz;
++03433                 DWC_PRINTF("DIETSIZ      @0x%08X : 0x%08X\n", (uint32_t) addr,
++03434                            dwc_read_reg32(addr));
++03435                 addr = &core_if->dev_if->in_ep_regs[i]->diepdma;
++03436                 DWC_PRINTF("DIEPDMA      @0x%08X : 0x%08X\n", (uint32_t) addr,
++03437                            dwc_read_reg32(addr));
++03438                 addr = &core_if->dev_if->in_ep_regs[i]->dtxfsts;
++03439                 DWC_PRINTF("DTXFSTS      @0x%08X : 0x%08X\n", (uint32_t) addr,
++03440                            dwc_read_reg32(addr));
++03441                 addr = &core_if->dev_if->in_ep_regs[i]->diepdmab;
++03442                 DWC_PRINTF("DIEPDMAB     @0x%08X : 0x%08X\n", (uint32_t) addr,
++03443                            0 /*dwc_read_reg32(addr) */ );
++03444         }
++03445 
++03446         for (i = 0; i <= core_if->dev_if->num_out_eps; i++) {
++03447                 DWC_PRINTF("Device OUT EP %d Registers\n", i);
++03448                 addr = &core_if->dev_if->out_ep_regs[i]->doepctl;
++03449                 DWC_PRINTF("DOEPCTL      @0x%08X : 0x%08X\n", (uint32_t) addr,
++03450                            dwc_read_reg32(addr));
++03451                 addr = &core_if->dev_if->out_ep_regs[i]->doepfn;
++03452                 DWC_PRINTF("DOEPFN       @0x%08X : 0x%08X\n", (uint32_t) addr,
++03453                            dwc_read_reg32(addr));
++03454                 addr = &core_if->dev_if->out_ep_regs[i]->doepint;
++03455                 DWC_PRINTF("DOEPINT      @0x%08X : 0x%08X\n", (uint32_t) addr,
++03456                            dwc_read_reg32(addr));
++03457                 addr = &core_if->dev_if->out_ep_regs[i]->doeptsiz;
++03458                 DWC_PRINTF("DOETSIZ      @0x%08X : 0x%08X\n", (uint32_t) addr,
++03459                            dwc_read_reg32(addr));
++03460                 addr = &core_if->dev_if->out_ep_regs[i]->doepdma;
++03461                 DWC_PRINTF("DOEPDMA      @0x%08X : 0x%08X\n", (uint32_t) addr,
++03462                            dwc_read_reg32(addr));
++03463                 if (core_if->dma_enable) {      /* Don't access this register in SLAVE mode */
++03464                         addr = &core_if->dev_if->out_ep_regs[i]->doepdmab;
++03465                         DWC_PRINTF("DOEPDMAB     @0x%08X : 0x%08X\n",
++03466                                    (uint32_t) addr, dwc_read_reg32(addr));
++03467                 }
++03468 
++03469         }
++03470 }
++03471 
++03477 void dwc_otg_dump_spram(dwc_otg_core_if_t * core_if)
++03478 {
++03479         volatile uint8_t *addr, *start_addr, *end_addr;
++03480 
++03481         DWC_PRINTF("SPRAM Data:\n");
++03482         start_addr = (void *)core_if->core_global_regs;
++03483         DWC_PRINTF("Base Address: 0x%8X\n", (uint32_t) start_addr);
++03484         start_addr += 0x00028000;
++03485         end_addr = (void *)core_if->core_global_regs;
++03486         end_addr += 0x000280e0;
++03487 
++03488         for (addr = start_addr; addr < end_addr; addr += 16) {
++03489                 DWC_PRINTF
++03490                     ("0x%8X:\t%2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X\n",
++03491                      (uint32_t) addr, addr[0], addr[1], addr[2], addr[3],
++03492                      addr[4], addr[5], addr[6], addr[7], addr[8], addr[9],
++03493                      addr[10], addr[11], addr[12], addr[13], addr[14], addr[15]
++03494                     );
++03495         }
++03496 
++03497         return;
++03498 }
++03499 
++03505 void dwc_otg_dump_host_registers(dwc_otg_core_if_t * core_if)
++03506 {
++03507         int i;
++03508         volatile uint32_t *addr;
++03509 
++03510         DWC_PRINTF("Host Global Registers\n");
++03511         addr = &core_if->host_if->host_global_regs->hcfg;
++03512         DWC_PRINTF("HCFG                 @0x%08X : 0x%08X\n", (uint32_t) addr,
++03513                    dwc_read_reg32(addr));
++03514         addr = &core_if->host_if->host_global_regs->hfir;
++03515         DWC_PRINTF("HFIR                 @0x%08X : 0x%08X\n", (uint32_t) addr,
++03516                    dwc_read_reg32(addr));
++03517         addr = &core_if->host_if->host_global_regs->hfnum;
++03518         DWC_PRINTF("HFNUM        @0x%08X : 0x%08X\n", (uint32_t) addr,
++03519                    dwc_read_reg32(addr));
++03520         addr = &core_if->host_if->host_global_regs->hptxsts;
++03521         DWC_PRINTF("HPTXSTS      @0x%08X : 0x%08X\n", (uint32_t) addr,
++03522                    dwc_read_reg32(addr));
++03523         addr = &core_if->host_if->host_global_regs->haint;
++03524         DWC_PRINTF("HAINT        @0x%08X : 0x%08X\n", (uint32_t) addr,
++03525                    dwc_read_reg32(addr));
++03526         addr = &core_if->host_if->host_global_regs->haintmsk;
++03527         DWC_PRINTF("HAINTMSK     @0x%08X : 0x%08X\n", (uint32_t) addr,
++03528                    dwc_read_reg32(addr));
++03529         if (core_if->dma_desc_enable) {
++03530                 addr = &core_if->host_if->host_global_regs->hflbaddr;
++03531                 DWC_PRINTF("HFLBADDR     @0x%08X : 0x%08X\n",(uint32_t) addr,
++03532                            dwc_read_reg32(addr));
++03533         }
++03534         
++03535         addr = core_if->host_if->hprt0;
++03536         DWC_PRINTF("HPRT0        @0x%08X : 0x%08X\n", (uint32_t) addr,
++03537                    dwc_read_reg32(addr));
++03538 
++03539         for (i = 0; i < core_if->core_params->host_channels; i++) {
++03540                 DWC_PRINTF("Host Channel %d Specific Registers\n", i);
++03541                 addr = &core_if->host_if->hc_regs[i]->hcchar;
++03542                 DWC_PRINTF("HCCHAR       @0x%08X : 0x%08X\n", (uint32_t) addr,
++03543                            dwc_read_reg32(addr));
++03544                 addr = &core_if->host_if->hc_regs[i]->hcsplt;
++03545                 DWC_PRINTF("HCSPLT       @0x%08X : 0x%08X\n", (uint32_t) addr,
++03546                            dwc_read_reg32(addr));
++03547                 addr = &core_if->host_if->hc_regs[i]->hcint;
++03548                 DWC_PRINTF("HCINT        @0x%08X : 0x%08X\n", (uint32_t) addr,
++03549                            dwc_read_reg32(addr));
++03550                 addr = &core_if->host_if->hc_regs[i]->hcintmsk;
++03551                 DWC_PRINTF("HCINTMSK     @0x%08X : 0x%08X\n", (uint32_t) addr,
++03552                            dwc_read_reg32(addr));
++03553                 addr = &core_if->host_if->hc_regs[i]->hctsiz;
++03554                 DWC_PRINTF("HCTSIZ       @0x%08X : 0x%08X\n", (uint32_t) addr,
++03555                            dwc_read_reg32(addr));
++03556                 addr = &core_if->host_if->hc_regs[i]->hcdma;
++03557                 DWC_PRINTF("HCDMA        @0x%08X : 0x%08X\n", (uint32_t) addr,
++03558                            dwc_read_reg32(addr));
++03559                 if (core_if->dma_desc_enable) {
++03560                         addr=&core_if->host_if->hc_regs[i]->hcdmab;
++03561                         DWC_PRINTF("HCDMAB       @0x%08X : 0x%08X\n",(uint32_t) addr, dwc_read_reg32(addr));
++03562         }
++03563 
++03564         }
++03565         return;
++03566 }
++03567 
++03573 void dwc_otg_dump_global_registers(dwc_otg_core_if_t * core_if)
++03574 {
++03575         int i;
++03576         volatile uint32_t *addr;
++03577 
++03578         DWC_PRINTF("Core Global Registers\n");
++03579         addr = &core_if->core_global_regs->gotgctl;
++03580         DWC_PRINTF("GOTGCTL      @0x%08X : 0x%08X\n", (uint32_t) addr,
++03581                    dwc_read_reg32(addr));
++03582         addr = &core_if->core_global_regs->gotgint;
++03583         DWC_PRINTF("GOTGINT      @0x%08X : 0x%08X\n", (uint32_t) addr,
++03584                    dwc_read_reg32(addr));
++03585         addr = &core_if->core_global_regs->gahbcfg;
++03586         DWC_PRINTF("GAHBCFG      @0x%08X : 0x%08X\n", (uint32_t) addr,
++03587                    dwc_read_reg32(addr));
++03588         addr = &core_if->core_global_regs->gusbcfg;
++03589         DWC_PRINTF("GUSBCFG      @0x%08X : 0x%08X\n", (uint32_t) addr,
++03590                    dwc_read_reg32(addr));
++03591         addr = &core_if->core_global_regs->grstctl;
++03592         DWC_PRINTF("GRSTCTL      @0x%08X : 0x%08X\n", (uint32_t) addr,
++03593                    dwc_read_reg32(addr));
++03594         addr = &core_if->core_global_regs->gintsts;
++03595         DWC_PRINTF("GINTSTS      @0x%08X : 0x%08X\n", (uint32_t) addr,
++03596                    dwc_read_reg32(addr));
++03597         addr = &core_if->core_global_regs->gintmsk;
++03598         DWC_PRINTF("GINTMSK      @0x%08X : 0x%08X\n", (uint32_t) addr,
++03599                    dwc_read_reg32(addr));
++03600         addr = &core_if->core_global_regs->grxstsr;
++03601         DWC_PRINTF("GRXSTSR      @0x%08X : 0x%08X\n", (uint32_t) addr,
++03602                    dwc_read_reg32(addr));
++03603         addr = &core_if->core_global_regs->grxfsiz;
++03604         DWC_PRINTF("GRXFSIZ      @0x%08X : 0x%08X\n", (uint32_t) addr,
++03605                    dwc_read_reg32(addr));
++03606         addr = &core_if->core_global_regs->gnptxfsiz;
++03607         DWC_PRINTF("GNPTXFSIZ @0x%08X : 0x%08X\n", (uint32_t) addr,
++03608                    dwc_read_reg32(addr));
++03609         addr = &core_if->core_global_regs->gnptxsts;
++03610         DWC_PRINTF("GNPTXSTS     @0x%08X : 0x%08X\n", (uint32_t) addr,
++03611                    dwc_read_reg32(addr));
++03612         addr = &core_if->core_global_regs->gi2cctl;
++03613         DWC_PRINTF("GI2CCTL      @0x%08X : 0x%08X\n", (uint32_t) addr,
++03614                    dwc_read_reg32(addr));
++03615         addr = &core_if->core_global_regs->gpvndctl;
++03616         DWC_PRINTF("GPVNDCTL     @0x%08X : 0x%08X\n", (uint32_t) addr,
++03617                    dwc_read_reg32(addr));
++03618         addr = &core_if->core_global_regs->ggpio;
++03619         DWC_PRINTF("GGPIO        @0x%08X : 0x%08X\n", (uint32_t) addr,
++03620                    dwc_read_reg32(addr));
++03621         addr = &core_if->core_global_regs->guid;
++03622         DWC_PRINTF("GUID                 @0x%08X : 0x%08X\n", (uint32_t) addr,
++03623                    dwc_read_reg32(addr));
++03624         addr = &core_if->core_global_regs->gsnpsid;
++03625         DWC_PRINTF("GSNPSID      @0x%08X : 0x%08X\n", (uint32_t) addr,
++03626                    dwc_read_reg32(addr));
++03627         addr = &core_if->core_global_regs->ghwcfg1;
++03628         DWC_PRINTF("GHWCFG1      @0x%08X : 0x%08X\n", (uint32_t) addr,
++03629                    dwc_read_reg32(addr));
++03630         addr = &core_if->core_global_regs->ghwcfg2;
++03631         DWC_PRINTF("GHWCFG2      @0x%08X : 0x%08X\n", (uint32_t) addr,
++03632                    dwc_read_reg32(addr));
++03633         addr = &core_if->core_global_regs->ghwcfg3;
++03634         DWC_PRINTF("GHWCFG3      @0x%08X : 0x%08X\n", (uint32_t) addr,
++03635                    dwc_read_reg32(addr));
++03636         addr = &core_if->core_global_regs->ghwcfg4;
++03637         DWC_PRINTF("GHWCFG4      @0x%08X : 0x%08X\n", (uint32_t) addr,
++03638                    dwc_read_reg32(addr));
++03639         addr = &core_if->core_global_regs->glpmcfg;
++03640         DWC_PRINTF("GLPMCFG      @0x%08X : 0x%08X\n", (uint32_t) addr,
++03641                    dwc_read_reg32(addr));
++03642         addr = &core_if->core_global_regs->hptxfsiz;
++03643         DWC_PRINTF("HPTXFSIZ     @0x%08X : 0x%08X\n", (uint32_t) addr,
++03644                    dwc_read_reg32(addr));
++03645 
++03646         for (i = 0; i < core_if->hwcfg4.b.num_dev_perio_in_ep; i++) {
++03647                 addr = &core_if->core_global_regs->dptxfsiz_dieptxf[i];
++03648                 DWC_PRINTF("DPTXFSIZ[%d] @0x%08X : 0x%08X\n", i,
++03649                            (uint32_t) addr, dwc_read_reg32(addr));
++03650         }
++03651         addr = core_if->pcgcctl;
++03652         DWC_PRINTF("PCGCCTL      @0x%08X : 0x%08X\n", (uint32_t) addr,
++03653                    dwc_read_reg32(addr));
++03654 }
++03655 
++03662 void dwc_otg_flush_tx_fifo(dwc_otg_core_if_t * core_if, const int num)
++03663 {
++03664         dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
++03665         volatile grstctl_t greset = {.d32 = 0 };
++03666         int count = 0;
++03667 
++03668         DWC_DEBUGPL((DBG_CIL | DBG_PCDV), "Flush Tx FIFO %d\n", num);
++03669 
++03670         greset.b.txfflsh = 1;
++03671         greset.b.txfnum = num;
++03672         dwc_write_reg32(&global_regs->grstctl, greset.d32);
++03673 
++03674         do {
++03675                 greset.d32 = dwc_read_reg32(&global_regs->grstctl);
++03676                 if (++count > 10000) {
++03677                         DWC_WARN("%s() HANG! GRSTCTL=%0x GNPTXSTS=0x%08x\n",
++03678                                  __func__, greset.d32,
++03679                                  dwc_read_reg32(&global_regs->gnptxsts));
++03680                         break;
++03681                 }
++03682                 dwc_udelay(1);
++03683         } while (greset.b.txfflsh == 1);
++03684 
++03685         /* Wait for 3 PHY Clocks */
++03686         dwc_udelay(1);
++03687 }
++03688 
++03694 void dwc_otg_flush_rx_fifo(dwc_otg_core_if_t * core_if)
++03695 {
++03696         dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
++03697         volatile grstctl_t greset = {.d32 = 0 };
++03698         int count = 0;
++03699 
++03700         DWC_DEBUGPL((DBG_CIL | DBG_PCDV), "%s\n", __func__);
++03701         /*
++03702          * 
++03703          */
++03704         greset.b.rxfflsh = 1;
++03705         dwc_write_reg32(&global_regs->grstctl, greset.d32);
++03706 
++03707         do {
++03708                 greset.d32 = dwc_read_reg32(&global_regs->grstctl);
++03709                 if (++count > 10000) {
++03710                         DWC_WARN("%s() HANG! GRSTCTL=%0x\n", __func__,
++03711                                  greset.d32);
++03712                         break;
++03713                 }
++03714                 dwc_udelay(1);
++03715         } while (greset.b.rxfflsh == 1);
++03716 
++03717         /* Wait for 3 PHY Clocks */
++03718         dwc_udelay(1);
++03719 }
++03720 
++03725 void dwc_otg_core_reset(dwc_otg_core_if_t * core_if)
++03726 {
++03727         dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
++03728         volatile grstctl_t greset = {.d32 = 0 };
++03729         int count = 0;
++03730 
++03731         DWC_DEBUGPL(DBG_CILV, "%s\n", __func__);
++03732         /* Wait for AHB master IDLE state. */
++03733         do {
++03734                 dwc_udelay(10);
++03735                 greset.d32 = dwc_read_reg32(&global_regs->grstctl);
++03736                 if (++count > 100000) {
++03737                         DWC_WARN("%s() HANG! AHB Idle GRSTCTL=%0x\n", __func__,
++03738                                  greset.d32);
++03739                         return;
++03740                 }
++03741         }
++03742         while (greset.b.ahbidle == 0);
++03743 
++03744         /* Core Soft Reset */
++03745         count = 0;
++03746         greset.b.csftrst = 1;
++03747         dwc_write_reg32(&global_regs->grstctl, greset.d32);
++03748         do {
++03749                 greset.d32 = dwc_read_reg32(&global_regs->grstctl);
++03750                 if (++count > 10000) {
++03751                         DWC_WARN("%s() HANG! Soft Reset GRSTCTL=%0x\n",
++03752                                  __func__, greset.d32);
++03753                         break;
++03754                 }
++03755                 dwc_udelay(1);
++03756         }
++03757         while (greset.b.csftrst == 1);
++03758 
++03759         /* Wait for 3 PHY Clocks */
++03760         dwc_mdelay(100);
++03761 }
++03762 
++03763 uint8_t dwc_otg_is_device_mode(dwc_otg_core_if_t * _core_if)
++03764 {
++03765         return (dwc_otg_mode(_core_if) != DWC_HOST_MODE);
++03766 }
++03767 
++03768 uint8_t dwc_otg_is_host_mode(dwc_otg_core_if_t * _core_if)
++03769 {
++03770         return (dwc_otg_mode(_core_if) == DWC_HOST_MODE);
++03771 }
++03772 
++03781 void dwc_otg_cil_register_hcd_callbacks(dwc_otg_core_if_t * core_if,
++03782                                         dwc_otg_cil_callbacks_t * cb, void *p)
++03783 {
++03784         core_if->hcd_cb = cb;
++03785         cb->p = p;
++03786 }
++03787 
++03796 void dwc_otg_cil_register_pcd_callbacks(dwc_otg_core_if_t * core_if,
++03797                                         dwc_otg_cil_callbacks_t * cb, void *p)
++03798 {
++03799         core_if->pcd_cb = cb;
++03800         cb->p = p;
++03801 }
++03802 
++03803 #ifdef DWC_EN_ISOC
++03804 
++03812 void write_isoc_frame_data(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
++03813 {
++03814         dwc_otg_dev_in_ep_regs_t *ep_regs;
++03815         dtxfsts_data_t txstatus = {.d32 = 0 };
++03816         uint32_t len = 0;
++03817         uint32_t dwords;
++03818 
++03819         ep->xfer_len = ep->data_per_frame;
++03820         ep->xfer_count = 0;
++03821 
++03822         ep_regs = core_if->dev_if->in_ep_regs[ep->num];
++03823 
++03824         len = ep->xfer_len - ep->xfer_count;
++03825 
++03826         if (len > ep->maxpacket) {
++03827                 len = ep->maxpacket;
++03828         }
++03829 
++03830         dwords = (len + 3) / 4;
++03831 
++03832         /* While there is space in the queue and space in the FIFO and
++03833          * More data to tranfer, Write packets to the Tx FIFO */
++03834         txstatus.d32 =
++03835             dwc_read_reg32(&core_if->dev_if->in_ep_regs[ep->num]->dtxfsts);
++03836         DWC_DEBUGPL(DBG_PCDV, "b4 dtxfsts[%d]=0x%08x\n", ep->num, txstatus.d32);
++03837 
++03838         while (txstatus.b.txfspcavail > dwords &&
++03839                ep->xfer_count < ep->xfer_len && ep->xfer_len != 0) {
++03840                 /* Write the FIFO */
++03841                 dwc_otg_ep_write_packet(core_if, ep, 0);
++03842 
++03843                 len = ep->xfer_len - ep->xfer_count;
++03844                 if (len > ep->maxpacket) {
++03845                         len = ep->maxpacket;
++03846                 }
++03847 
++03848                 dwords = (len + 3) / 4;
++03849                 txstatus.d32 =
++03850                     dwc_read_reg32(&core_if->dev_if->in_ep_regs[ep->num]->
++03851                                    dtxfsts);
++03852                 DWC_DEBUGPL(DBG_PCDV, "dtxfsts[%d]=0x%08x\n", ep->num,
++03853                             txstatus.d32);
++03854         }
++03855 }
++03856 
++03864 void dwc_otg_iso_ep_start_frm_transfer(dwc_otg_core_if_t * core_if,
++03865                                        dwc_ep_t * ep)
++03866 {
++03867         deptsiz_data_t deptsiz = {.d32 = 0 };
++03868         depctl_data_t depctl = {.d32 = 0 };
++03869         dsts_data_t dsts = {.d32 = 0 };
++03870         volatile uint32_t *addr;
++03871 
++03872         if (ep->is_in) {
++03873                 addr = &core_if->dev_if->in_ep_regs[ep->num]->diepctl;
++03874         } else {
++03875                 addr = &core_if->dev_if->out_ep_regs[ep->num]->doepctl;
++03876         }
++03877 
++03878         ep->xfer_len = ep->data_per_frame;
++03879         ep->xfer_count = 0;
++03880         ep->xfer_buff = ep->cur_pkt_addr;
++03881         ep->dma_addr = ep->cur_pkt_dma_addr;
++03882 
++03883         if (ep->is_in) {
++03884                 /* Program the transfer size and packet count
++03885                  *      as follows: xfersize = N * maxpacket +
++03886                  *      short_packet pktcnt = N + (short_packet
++03887                  *      exist ? 1 : 0)  
++03888                  */
++03889                 deptsiz.b.xfersize = ep->xfer_len;
++03890                 deptsiz.b.pktcnt =
++03891                     (ep->xfer_len - 1 + ep->maxpacket) / ep->maxpacket;
++03892                 deptsiz.b.mc = deptsiz.b.pktcnt;
++03893                 dwc_write_reg32(&core_if->dev_if->in_ep_regs[ep->num]->dieptsiz,
++03894                                 deptsiz.d32);
++03895 
++03896                 /* Write the DMA register */
++03897                 if (core_if->dma_enable) {
++03898                         dwc_write_reg32(&
++03899                                         (core_if->dev_if->in_ep_regs[ep->num]->
++03900                                          diepdma), (uint32_t) ep->dma_addr);
++03901                 }
++03902         } else {
++03903                 deptsiz.b.pktcnt =
++03904                     (ep->xfer_len + (ep->maxpacket - 1)) / ep->maxpacket;
++03905                 deptsiz.b.xfersize = deptsiz.b.pktcnt * ep->maxpacket;
++03906 
++03907                 dwc_write_reg32(&core_if->dev_if->out_ep_regs[ep->num]->
++03908                                 doeptsiz, deptsiz.d32);
++03909 
++03910                 if (core_if->dma_enable) {
++03911                         dwc_write_reg32(&
++03912                                         (core_if->dev_if->out_ep_regs[ep->num]->
++03913                                          doepdma), (uint32_t) ep->dma_addr);
++03914                 }
++03915         }
++03916 
++03919         depctl.d32 = 0;
++03920         if (ep->bInterval == 1) {
++03921                 dsts.d32 =
++03922                     dwc_read_reg32(&core_if->dev_if->dev_global_regs->dsts);
++03923                 ep->next_frame = dsts.b.soffn + ep->bInterval;
++03924 
++03925                 if (ep->next_frame & 0x1) {
++03926                         depctl.b.setd1pid = 1;
++03927                 } else {
++03928                         depctl.b.setd0pid = 1;
++03929                 }
++03930         } else {
++03931                 ep->next_frame += ep->bInterval;
++03932 
++03933                 if (ep->next_frame & 0x1) {
++03934                         depctl.b.setd1pid = 1;
++03935                 } else {
++03936                         depctl.b.setd0pid = 1;
++03937                 }
++03938         }
++03939         depctl.b.epena = 1;
++03940         depctl.b.cnak = 1;
++03941 
++03942         dwc_modify_reg32(addr, 0, depctl.d32);
++03943         depctl.d32 = dwc_read_reg32(addr);
++03944 
++03945         if (ep->is_in && core_if->dma_enable == 0) {
++03946                 write_isoc_frame_data(core_if, ep);
++03947         }
++03948 
++03949 }
++03950 #endif                          /* DWC_EN_ISOC */
++03951 
++03952 static void dwc_otg_set_uninitialized(int32_t * p, int size)
++03953 {
++03954         int i;
++03955         for (i = 0; i < size; i++) {
++03956                 p[i] = -1;
++03957         }
++03958 }
++03959 
++03960 static int dwc_otg_param_initialized(int32_t val)
++03961 {
++03962         return val != -1;
++03963 }
++03964 
++03965 static int dwc_otg_setup_params(dwc_otg_core_if_t * core_if)
++03966 {
++03967         int i;
++03968         core_if->core_params = DWC_ALLOC(sizeof(*core_if->core_params));
++03969         if (!core_if->core_params) {
++03970                 return -DWC_E_NO_MEMORY;
++03971         }
++03972         dwc_otg_set_uninitialized((int32_t *) core_if->core_params,
++03973                                   sizeof(*core_if->core_params) /
++03974                                   sizeof(int32_t));
++03975         DWC_PRINTF("Setting default values for core params\n");
++03976         dwc_otg_set_param_otg_cap(core_if, dwc_param_otg_cap_default);
++03977         dwc_otg_set_param_dma_enable(core_if, dwc_param_dma_enable_default);
++03978         dwc_otg_set_param_dma_desc_enable(core_if,
++03979                                           dwc_param_dma_desc_enable_default);
++03980         dwc_otg_set_param_opt(core_if, dwc_param_opt_default);
++03981         dwc_otg_set_param_dma_burst_size(core_if,
++03982                                          dwc_param_dma_burst_size_default);
++03983         dwc_otg_set_param_host_support_fs_ls_low_power(core_if,
++03984                                                        dwc_param_host_support_fs_ls_low_power_default);
++03985         dwc_otg_set_param_enable_dynamic_fifo(core_if,
++03986                                               dwc_param_enable_dynamic_fifo_default);
++03987         dwc_otg_set_param_data_fifo_size(core_if,
++03988                                          dwc_param_data_fifo_size_default);
++03989         dwc_otg_set_param_dev_rx_fifo_size(core_if,
++03990                                            dwc_param_dev_rx_fifo_size_default);
++03991         dwc_otg_set_param_dev_nperio_tx_fifo_size(core_if,
++03992                                                   dwc_param_dev_nperio_tx_fifo_size_default);
++03993         dwc_otg_set_param_host_rx_fifo_size(core_if,
++03994                                             dwc_param_host_rx_fifo_size_default);
++03995         dwc_otg_set_param_host_nperio_tx_fifo_size(core_if,
++03996                                                    dwc_param_host_nperio_tx_fifo_size_default);
++03997         dwc_otg_set_param_host_perio_tx_fifo_size(core_if,
++03998                                                   dwc_param_host_perio_tx_fifo_size_default);
++03999         dwc_otg_set_param_max_transfer_size(core_if,
++04000                                             dwc_param_max_transfer_size_default);
++04001         dwc_otg_set_param_max_packet_count(core_if,
++04002                                            dwc_param_max_packet_count_default);
++04003         dwc_otg_set_param_host_channels(core_if,
++04004                                         dwc_param_host_channels_default);
++04005         dwc_otg_set_param_dev_endpoints(core_if,
++04006                                         dwc_param_dev_endpoints_default);
++04007         dwc_otg_set_param_phy_type(core_if, dwc_param_phy_type_default);
++04008         dwc_otg_set_param_speed(core_if, dwc_param_speed_default);
++04009         dwc_otg_set_param_host_ls_low_power_phy_clk(core_if,
++04010                                                     dwc_param_host_ls_low_power_phy_clk_default);
++04011         dwc_otg_set_param_phy_ulpi_ddr(core_if, dwc_param_phy_ulpi_ddr_default);
++04012         dwc_otg_set_param_phy_ulpi_ext_vbus(core_if,
++04013                                             dwc_param_phy_ulpi_ext_vbus_default);
++04014         dwc_otg_set_param_phy_utmi_width(core_if,
++04015                                          dwc_param_phy_utmi_width_default);
++04016         dwc_otg_set_param_ts_dline(core_if, dwc_param_ts_dline_default);
++04017         dwc_otg_set_param_i2c_enable(core_if, dwc_param_i2c_enable_default);
++04018         dwc_otg_set_param_ulpi_fs_ls(core_if, dwc_param_ulpi_fs_ls_default);
++04019         dwc_otg_set_param_en_multiple_tx_fifo(core_if,
++04020                                               dwc_param_en_multiple_tx_fifo_default);
++04021         for (i = 0; i < 15; i++) {
++04022                 dwc_otg_set_param_dev_perio_tx_fifo_size(core_if,
++04023                                                          dwc_param_dev_perio_tx_fifo_size_default,
++04024                                                          i);
++04025         }
++04026 
++04027         for (i = 0; i < 15; i++) {
++04028                 dwc_otg_set_param_dev_tx_fifo_size(core_if,
++04029                                                    dwc_param_dev_tx_fifo_size_default,
++04030                                                    i);
++04031         }
++04032         dwc_otg_set_param_thr_ctl(core_if, dwc_param_thr_ctl_default);
++04033         dwc_otg_set_param_mpi_enable(core_if, dwc_param_mpi_enable_default);
++04034         dwc_otg_set_param_pti_enable(core_if, dwc_param_pti_enable_default);
++04035         dwc_otg_set_param_lpm_enable(core_if, dwc_param_lpm_enable_default);
++04036         dwc_otg_set_param_ic_usb_cap(core_if, dwc_param_ic_usb_cap_default);
++04037         dwc_otg_set_param_tx_thr_length(core_if,
++04038                                         dwc_param_tx_thr_length_default);
++04039         dwc_otg_set_param_rx_thr_length(core_if,
++04040                                         dwc_param_rx_thr_length_default);
++04041         dwc_otg_set_param_ahb_thr_ratio(core_if, dwc_param_ahb_thr_ratio_default);
++04042         return 0;
++04043 }
++04044 
++04045 uint8_t dwc_otg_is_dma_enable(dwc_otg_core_if_t * core_if)
++04046 {
++04047         return core_if->dma_enable;
++04048 }
++04049 
++04050 /* Checks if the parameter is outside of its valid range of values */
++04051 #define DWC_OTG_PARAM_TEST(_param_, _low_, _high_) \
++04052                 (((_param_) < (_low_)) || \
++04053                 ((_param_) > (_high_)))
++04054 
++04055 /* Parameter access functions */
++04056 int dwc_otg_set_param_otg_cap(dwc_otg_core_if_t * core_if, int32_t val)
++04057 {
++04058         int valid;
++04059         int retval = 0;
++04060         if (DWC_OTG_PARAM_TEST(val, 0, 2)) {
++04061                 DWC_WARN("Wrong value for otg_cap parameter\n");
++04062                 DWC_WARN("otg_cap parameter must be 0,1 or 2\n");
++04063                 retval = -DWC_E_INVALID;
++04064                 goto out;
++04065         }
++04066 
++04067         valid = 1;
++04068         switch (val) {
++04069         case DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE:
++04070                 if (core_if->hwcfg2.b.op_mode !=
++04071                     DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG)
++04072                         valid = 0;
++04073                 break;
++04074         case DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE:
++04075                 if ((core_if->hwcfg2.b.op_mode !=
++04076                      DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG)
++04077                     && (core_if->hwcfg2.b.op_mode !=
++04078                         DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG)
++04079                     && (core_if->hwcfg2.b.op_mode !=
++04080                         DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE)
++04081                     && (core_if->hwcfg2.b.op_mode !=
++04082                       DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST)) {
++04083                         valid = 0;
++04084                 }
++04085                 break;
++04086         case DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE:
++04087                 /* always valid */
++04088                 break;
++04089         }
++04090         if (!valid) {
++04091                 if (dwc_otg_param_initialized(core_if->core_params->otg_cap)) {
++04092                         DWC_ERROR
++04093                             ("%d invalid for otg_cap paremter. Check HW configuration.\n",
++04094                              val);
++04095                 }
++04096                 val =
++04097                     (((core_if->hwcfg2.b.op_mode ==
++04098                        DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG)
++04099                       || (core_if->hwcfg2.b.op_mode ==
++04100                           DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG)
++04101                       || (core_if->hwcfg2.b.op_mode ==
++04102                           DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE)
++04103                       || (core_if->hwcfg2.b.op_mode ==
++04104                           DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST)) ?
++04105                      DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE :
++04106                      DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE);
++04107                 retval = -DWC_E_INVALID;
++04108         }
++04109 
++04110         core_if->core_params->otg_cap = val;
++04111       out:
++04112         return retval;
++04113 }
++04114 
++04115 int32_t dwc_otg_get_param_otg_cap(dwc_otg_core_if_t * core_if)
++04116 {
++04117         return core_if->core_params->otg_cap;
++04118 }
++04119 
++04120 int dwc_otg_set_param_opt(dwc_otg_core_if_t * core_if, int32_t val)
++04121 {
++04122         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
++04123                 DWC_WARN("Wrong value for opt parameter\n");
++04124                 return -DWC_E_INVALID;
++04125         }
++04126         core_if->core_params->opt = val;
++04127         return 0;
++04128 }
++04129 
++04130 int32_t dwc_otg_get_param_opt(dwc_otg_core_if_t * core_if)
++04131 {
++04132         return core_if->core_params->opt;
++04133 }
++04134 
++04135 int dwc_otg_set_param_dma_enable(dwc_otg_core_if_t * core_if, int32_t val)
++04136 {
++04137         int retval = 0;
++04138         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
++04139                 DWC_WARN("Wrong value for dma enable\n");
++04140                 return -DWC_E_INVALID;
++04141         }
++04142 
++04143         if ((val == 1) && (core_if->hwcfg2.b.architecture == 0)) {
++04144                 if (dwc_otg_param_initialized(core_if->core_params->dma_enable)) {
++04145                         DWC_ERROR
++04146                             ("%d invalid for dma_enable paremter. Check HW configuration.\n",
++04147                              val);
++04148                 }
++04149                 val = 0;
++04150                 retval = -DWC_E_INVALID;
++04151         }
++04152 
++04153         core_if->core_params->dma_enable = val;
++04154         if (val == 0) {
++04155                 dwc_otg_set_param_dma_desc_enable(core_if, 0);
++04156         }
++04157         return retval;
++04158 }
++04159 
++04160 int32_t dwc_otg_get_param_dma_enable(dwc_otg_core_if_t * core_if)
++04161 {
++04162         return core_if->core_params->dma_enable;
++04163 }
++04164 
++04165 int dwc_otg_set_param_dma_desc_enable(dwc_otg_core_if_t * core_if, int32_t val)
++04166 {
++04167         int retval = 0;
++04168         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
++04169                 DWC_WARN("Wrong value for dma_enable\n");
++04170                 DWC_WARN("dma_desc_enable must be 0 or 1\n");
++04171                 return -DWC_E_INVALID;
++04172         }
++04173 
++04174         if ((val == 1)
++04175             && ((dwc_otg_get_param_dma_enable(core_if) == 0)
++04176                 || (core_if->hwcfg4.b.desc_dma == 0))) {
++04177                 if (dwc_otg_param_initialized
++04178                     (core_if->core_params->dma_desc_enable)) {
++04179                         DWC_ERROR
++04180                             ("%d invalid for dma_desc_enable paremter. Check HW configuration.\n",
++04181                              val);
++04182                 }
++04183                 val = 0;
++04184                 retval = -DWC_E_INVALID;
++04185         }
++04186         core_if->core_params->dma_desc_enable = val;
++04187         return retval;
++04188 }
++04189 
++04190 int32_t dwc_otg_get_param_dma_desc_enable(dwc_otg_core_if_t * core_if)
++04191 {
++04192         return core_if->core_params->dma_desc_enable;
++04193 }
++04194 
++04195 int dwc_otg_set_param_host_support_fs_ls_low_power(dwc_otg_core_if_t * core_if,
++04196                                                    int32_t val)
++04197 {
++04198         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
++04199                 DWC_WARN("Wrong value for host_support_fs_low_power\n");
++04200                 DWC_WARN("host_support_fs_low_power must be 0 or 1\n");
++04201                 return -DWC_E_INVALID;
++04202         }
++04203         core_if->core_params->host_support_fs_ls_low_power = val;
++04204         return 0;
++04205 }
++04206 
++04207 int32_t dwc_otg_get_param_host_support_fs_ls_low_power(dwc_otg_core_if_t *
++04208                                                        core_if)
++04209 {
++04210         return core_if->core_params->host_support_fs_ls_low_power;
++04211 }
++04212 
++04213 int dwc_otg_set_param_enable_dynamic_fifo(dwc_otg_core_if_t * core_if,
++04214                                           int32_t val)
++04215 {
++04216         int retval = 0;
++04217         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
++04218                 DWC_WARN("Wrong value for enable_dynamic_fifo\n");
++04219                 DWC_WARN("enable_dynamic_fifo must be 0 or 1\n");
++04220                 return -DWC_E_INVALID;
++04221         }
++04222 
++04223         if ((val == 1) && (core_if->hwcfg2.b.dynamic_fifo == 0)) {
++04224                 if (dwc_otg_param_initialized
++04225                     (core_if->core_params->enable_dynamic_fifo)) {
++04226                         DWC_ERROR
++04227                             ("%d invalid for enable_dynamic_fifo paremter. Check HW configuration.\n",
++04228                              val);
++04229                 }
++04230                 val = 0;
++04231                 retval = -DWC_E_INVALID;
++04232         }
++04233         core_if->core_params->enable_dynamic_fifo = val;
++04234         return retval;
++04235 }
++04236 
++04237 int32_t dwc_otg_get_param_enable_dynamic_fifo(dwc_otg_core_if_t * core_if)
++04238 {
++04239         return core_if->core_params->enable_dynamic_fifo;
++04240 }
++04241 
++04242 int dwc_otg_set_param_data_fifo_size(dwc_otg_core_if_t * core_if, int32_t val)
++04243 {
++04244         int retval = 0;
++04245         if (DWC_OTG_PARAM_TEST(val, 32, 32768)) {
++04246                 DWC_WARN("Wrong value for data_fifo_size\n");
++04247                 DWC_WARN("data_fifo_size must be 32-32768\n");
++04248                 return -DWC_E_INVALID;
++04249         }
++04250 
++04251         if (val > core_if->hwcfg3.b.dfifo_depth) {
++04252                 if (dwc_otg_param_initialized
++04253                     (core_if->core_params->data_fifo_size)) {
++04254                         DWC_ERROR
++04255                             ("%d invalid for data_fifo_size parameter. Check HW configuration.\n",
++04256                              val);
++04257                 }
++04258                 val = core_if->hwcfg3.b.dfifo_depth;
++04259                 retval = -DWC_E_INVALID;
++04260         }
++04261 
++04262         core_if->core_params->data_fifo_size = val;
++04263         return retval;
++04264 }
++04265 
++04266 int32_t dwc_otg_get_param_data_fifo_size(dwc_otg_core_if_t * core_if)
++04267 {
++04268         return core_if->core_params->data_fifo_size;
++04269 }
++04270 
++04271 int dwc_otg_set_param_dev_rx_fifo_size(dwc_otg_core_if_t * core_if, int32_t val)
++04272 {
++04273         int retval = 0;
++04274         if (DWC_OTG_PARAM_TEST(val, 16, 32768)) {
++04275                 DWC_WARN("Wrong value for dev_rx_fifo_size\n");
++04276                 DWC_WARN("dev_rx_fifo_size must be 16-32768\n");
++04277                 return -DWC_E_INVALID;
++04278         }
++04279 
++04280         if (val > dwc_read_reg32(&core_if->core_global_regs->grxfsiz)) {
++04281                 if(dwc_otg_param_initialized(core_if->core_params->dev_rx_fifo_size)) {
++04282                 DWC_WARN("%d invalid for dev_rx_fifo_size parameter\n", val);
++04283                 }
++04284                 val = dwc_read_reg32(&core_if->core_global_regs->grxfsiz);
++04285                 retval = -DWC_E_INVALID;
++04286         }
++04287 
++04288         core_if->core_params->dev_rx_fifo_size = val;
++04289         return retval;
++04290 }
++04291 
++04292 int32_t dwc_otg_get_param_dev_rx_fifo_size(dwc_otg_core_if_t * core_if)
++04293 {
++04294         return core_if->core_params->dev_rx_fifo_size;
++04295 }
++04296 
++04297 int dwc_otg_set_param_dev_nperio_tx_fifo_size(dwc_otg_core_if_t * core_if,
++04298                                               int32_t val)
++04299 {
++04300         int retval = 0;
++04301 
++04302         if (DWC_OTG_PARAM_TEST(val, 16, 32768)) {
++04303                 DWC_WARN("Wrong value for dev_nperio_tx_fifo\n");
++04304                 DWC_WARN("dev_nperio_tx_fifo must be 16-32768\n");
++04305                 return -DWC_E_INVALID;
++04306         }
++04307 
++04308         if (val > (dwc_read_reg32(&core_if->core_global_regs->gnptxfsiz) >> 16)) {
++04309                 if (dwc_otg_param_initialized
++04310                     (core_if->core_params->dev_nperio_tx_fifo_size)) {
++04311                         DWC_ERROR
++04312                             ("%d invalid for dev_nperio_tx_fifo_size. Check HW configuration.\n",
++04313                              val);
++04314                 }
++04315                 val =
++04316                     (dwc_read_reg32(&core_if->core_global_regs->gnptxfsiz) >>
++04317                      16);
++04318                 retval = -DWC_E_INVALID;
++04319         }
++04320 
++04321         core_if->core_params->dev_nperio_tx_fifo_size = val;
++04322         return retval;
++04323 }
++04324 
++04325 int32_t dwc_otg_get_param_dev_nperio_tx_fifo_size(dwc_otg_core_if_t * core_if)
++04326 {
++04327         return core_if->core_params->dev_nperio_tx_fifo_size;
++04328 }
++04329 
++04330 int dwc_otg_set_param_host_rx_fifo_size(dwc_otg_core_if_t * core_if,
++04331                                         int32_t val)
++04332 {
++04333         int retval = 0;
++04334 
++04335         if (DWC_OTG_PARAM_TEST(val, 16, 32768)) {
++04336                 DWC_WARN("Wrong value for host_rx_fifo_size\n");
++04337                 DWC_WARN("host_rx_fifo_size must be 16-32768\n");
++04338                 return -DWC_E_INVALID;
++04339         }
++04340 
++04341         if (val > dwc_read_reg32(&core_if->core_global_regs->grxfsiz)) {
++04342                 if (dwc_otg_param_initialized
++04343                     (core_if->core_params->host_rx_fifo_size)) {
++04344                         DWC_ERROR
++04345                             ("%d invalid for host_rx_fifo_size. Check HW configuration.\n",
++04346                              val);
++04347                 }
++04348                 val = dwc_read_reg32(&core_if->core_global_regs->grxfsiz);
++04349                 retval = -DWC_E_INVALID;
++04350         }
++04351 
++04352         core_if->core_params->host_rx_fifo_size = val;
++04353         return retval;
++04354 
++04355 }
++04356 
++04357 int32_t dwc_otg_get_param_host_rx_fifo_size(dwc_otg_core_if_t * core_if)
++04358 {
++04359         return core_if->core_params->host_rx_fifo_size;
++04360 }
++04361 
++04362 int dwc_otg_set_param_host_nperio_tx_fifo_size(dwc_otg_core_if_t * core_if,
++04363                                                int32_t val)
++04364 {
++04365         int retval = 0;
++04366 
++04367         if (DWC_OTG_PARAM_TEST(val, 16, 32768)) {
++04368                 DWC_WARN("Wrong value for host_nperio_tx_fifo_size\n");
++04369                 DWC_WARN("host_nperio_tx_fifo_size must be 16-32768\n");
++04370                 return -DWC_E_INVALID;
++04371         }
++04372 
++04373         if (val > (dwc_read_reg32(&core_if->core_global_regs->gnptxfsiz) >> 16)) {
++04374                 if (dwc_otg_param_initialized
++04375                     (core_if->core_params->host_nperio_tx_fifo_size)) {
++04376                         DWC_ERROR
++04377                             ("%d invalid for host_nperio_tx_fifo_size. Check HW configuration.\n",
++04378                              val);
++04379                 }
++04380                 val =
++04381                     (dwc_read_reg32(&core_if->core_global_regs->gnptxfsiz) >>
++04382                      16);
++04383                 retval = -DWC_E_INVALID;
++04384         }
++04385 
++04386         core_if->core_params->host_nperio_tx_fifo_size = val;
++04387         return retval;
++04388 }
++04389 
++04390 int32_t dwc_otg_get_param_host_nperio_tx_fifo_size(dwc_otg_core_if_t * core_if)
++04391 {
++04392         return core_if->core_params->host_nperio_tx_fifo_size;
++04393 }
++04394 
++04395 int dwc_otg_set_param_host_perio_tx_fifo_size(dwc_otg_core_if_t * core_if,
++04396                                               int32_t val)
++04397 {
++04398         int retval = 0;
++04399         if (DWC_OTG_PARAM_TEST(val, 16, 32768)) {
++04400                 DWC_WARN("Wrong value for host_perio_tx_fifo_size\n");
++04401                 DWC_WARN("host_perio_tx_fifo_size must be 16-32768\n");
++04402                 return -DWC_E_INVALID;
++04403         }
++04404 
++04405         if (val >
++04406             ((dwc_read_reg32(&core_if->core_global_regs->hptxfsiz) >> 16))) {
++04407                 if (dwc_otg_param_initialized
++04408                     (core_if->core_params->host_perio_tx_fifo_size)) {
++04409                         DWC_ERROR
++04410                             ("%d invalid for host_perio_tx_fifo_size. Check HW configuration.\n",
++04411                              val);
++04412                 }
++04413                 val =
++04414                     (dwc_read_reg32(&core_if->core_global_regs->hptxfsiz) >>
++04415                      16);
++04416                 retval = -DWC_E_INVALID;
++04417         }
++04418 
++04419         core_if->core_params->host_perio_tx_fifo_size = val;
++04420         return retval;
++04421 }
++04422 
++04423 int32_t dwc_otg_get_param_host_perio_tx_fifo_size(dwc_otg_core_if_t * core_if)
++04424 {
++04425         return core_if->core_params->host_perio_tx_fifo_size;
++04426 }
++04427 
++04428 int dwc_otg_set_param_max_transfer_size(dwc_otg_core_if_t * core_if,
++04429                                         int32_t val)
++04430 {
++04431         int retval = 0;
++04432 
++04433         if (DWC_OTG_PARAM_TEST(val, 2047, 524288)) {
++04434                 DWC_WARN("Wrong value for max_transfer_size\n");
++04435                 DWC_WARN("max_transfer_size must be 2047-524288\n");
++04436                 return -DWC_E_INVALID;
++04437         }
++04438 
++04439         if (val >= (1 << (core_if->hwcfg3.b.xfer_size_cntr_width + 11))) {
++04440                 if (dwc_otg_param_initialized
++04441                     (core_if->core_params->max_transfer_size)) {
++04442                         DWC_ERROR
++04443                             ("%d invalid for max_transfer_size. Check HW configuration.\n",
++04444                              val);
++04445                 }
++04446                 val =
++04447                     ((1 << (core_if->hwcfg3.b.packet_size_cntr_width + 11)) -
++04448                      1);
++04449                 retval = -DWC_E_INVALID;
++04450         }
++04451 
++04452         core_if->core_params->max_transfer_size = val;
++04453         return retval;
++04454 }
++04455 
++04456 int32_t dwc_otg_get_param_max_transfer_size(dwc_otg_core_if_t * core_if)
++04457 {
++04458         return core_if->core_params->max_transfer_size;
++04459 }
++04460 
++04461 int dwc_otg_set_param_max_packet_count(dwc_otg_core_if_t * core_if, int32_t val)
++04462 {
++04463         int retval = 0;
++04464 
++04465         if (DWC_OTG_PARAM_TEST(val, 15, 511)) {
++04466                 DWC_WARN("Wrong value for max_packet_count\n");
++04467                 DWC_WARN("max_packet_count must be 15-511\n");
++04468                 return -DWC_E_INVALID;
++04469         }
++04470 
++04471         if (val > (1 << (core_if->hwcfg3.b.packet_size_cntr_width + 4))) {
++04472                 if (dwc_otg_param_initialized
++04473                     (core_if->core_params->max_packet_count)) {
++04474                         DWC_ERROR
++04475                             ("%d invalid for max_packet_count. Check HW configuration.\n",
++04476                              val);
++04477                 }
++04478                 val =
++04479                     ((1 << (core_if->hwcfg3.b.packet_size_cntr_width + 4)) - 1);
++04480                 retval = -DWC_E_INVALID;
++04481         }
++04482 
++04483         core_if->core_params->max_packet_count = val;
++04484         return retval;
++04485 }
++04486 
++04487 int32_t dwc_otg_get_param_max_packet_count(dwc_otg_core_if_t * core_if)
++04488 {
++04489         return core_if->core_params->max_packet_count;
++04490 }
++04491 
++04492 int dwc_otg_set_param_host_channels(dwc_otg_core_if_t * core_if, int32_t val)
++04493 {
++04494         int retval = 0;
++04495 
++04496         if (DWC_OTG_PARAM_TEST(val, 1, 16)) {
++04497                 DWC_WARN("Wrong value for host_channels\n");
++04498                 DWC_WARN("host_channels must be 1-16\n");
++04499                 return -DWC_E_INVALID;
++04500         }
++04501 
++04502         if (val > (core_if->hwcfg2.b.num_host_chan + 1)) {
++04503                 if (dwc_otg_param_initialized
++04504                     (core_if->core_params->host_channels)) {
++04505                         DWC_ERROR
++04506                             ("%d invalid for host_channels. Check HW configurations.\n",
++04507                              val);
++04508                 }
++04509                 val = (core_if->hwcfg2.b.num_host_chan + 1);
++04510                 retval = -DWC_E_INVALID;
++04511         }
++04512 
++04513         core_if->core_params->host_channels = val;
++04514         return retval;
++04515 }
++04516 
++04517 int32_t dwc_otg_get_param_host_channels(dwc_otg_core_if_t * core_if)
++04518 {
++04519         return core_if->core_params->host_channels;
++04520 }
++04521 
++04522 int dwc_otg_set_param_dev_endpoints(dwc_otg_core_if_t * core_if, int32_t val)
++04523 {
++04524         int retval = 0;
++04525 
++04526         if (DWC_OTG_PARAM_TEST(val, 1, 15)) {
++04527                 DWC_WARN("Wrong value for dev_endpoints\n");
++04528                 DWC_WARN("dev_endpoints must be 1-15\n");
++04529                 return -DWC_E_INVALID;
++04530         }
++04531 
++04532         if (val > (core_if->hwcfg2.b.num_dev_ep)) {
++04533                 if (dwc_otg_param_initialized
++04534                     (core_if->core_params->dev_endpoints)) {
++04535                         DWC_ERROR
++04536                             ("%d invalid for dev_endpoints. Check HW configurations.\n",
++04537                              val);
++04538                 }
++04539                 val = core_if->hwcfg2.b.num_dev_ep;
++04540                 retval = -DWC_E_INVALID;
++04541         }
++04542 
++04543         core_if->core_params->dev_endpoints = val;
++04544         return retval;
++04545 }
++04546 
++04547 int32_t dwc_otg_get_param_dev_endpoints(dwc_otg_core_if_t * core_if)
++04548 {
++04549         return core_if->core_params->dev_endpoints;
++04550 }
++04551 
++04552 int dwc_otg_set_param_phy_type(dwc_otg_core_if_t * core_if, int32_t val)
++04553 {
++04554         int retval = 0;
++04555         int valid = 0;
++04556 
++04557         if (DWC_OTG_PARAM_TEST(val, 0, 2)) {
++04558                 DWC_WARN("Wrong value for phy_type\n");
++04559                 DWC_WARN("phy_type must be 0,1 or 2\n");
++04560                 return -DWC_E_INVALID;
++04561         }
++04562 #ifndef NO_FS_PHY_HW_CHECKS
++04563         if ((val == DWC_PHY_TYPE_PARAM_UTMI) &&
++04564             ((core_if->hwcfg2.b.hs_phy_type == 1) ||
++04565              (core_if->hwcfg2.b.hs_phy_type == 3))) {
++04566                 valid = 1;
++04567         } else if ((val == DWC_PHY_TYPE_PARAM_ULPI) &&
++04568                    ((core_if->hwcfg2.b.hs_phy_type == 2) ||
++04569                     (core_if->hwcfg2.b.hs_phy_type == 3))) {
++04570                 valid = 1;
++04571         } else if ((val == DWC_PHY_TYPE_PARAM_FS) &&
++04572                    (core_if->hwcfg2.b.fs_phy_type == 1)) {
++04573                 valid = 1;
++04574         }
++04575         if (!valid) {
++04576                 if (dwc_otg_param_initialized(core_if->core_params->phy_type)) {
++04577                         DWC_ERROR
++04578                             ("%d invalid for phy_type. Check HW configurations.\n",
++04579                              val);
++04580                 }
++04581                 if (core_if->hwcfg2.b.hs_phy_type) {
++04582                         if ((core_if->hwcfg2.b.hs_phy_type == 3) ||
++04583                             (core_if->hwcfg2.b.hs_phy_type == 1)) {
++04584                                 val = DWC_PHY_TYPE_PARAM_UTMI;
++04585                         } else {
++04586                                 val = DWC_PHY_TYPE_PARAM_ULPI;
++04587                         }
++04588                 }
++04589                 retval = -DWC_E_INVALID;
++04590         }
++04591 #endif
++04592         core_if->core_params->phy_type = val;
++04593         return retval;
++04594 }
++04595 
++04596 int32_t dwc_otg_get_param_phy_type(dwc_otg_core_if_t * core_if)
++04597 {
++04598         return core_if->core_params->phy_type;
++04599 }
++04600 
++04601 int dwc_otg_set_param_speed(dwc_otg_core_if_t * core_if, int32_t val)
++04602 {
++04603         int retval = 0;
++04604         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
++04605                 DWC_WARN("Wrong value for speed parameter\n");
++04606                 DWC_WARN("max_speed parameter must be 0 or 1\n");
++04607                 return -DWC_E_INVALID;
++04608         }
++04609         if ((val == 0)
++04610             && dwc_otg_get_param_phy_type(core_if) == DWC_PHY_TYPE_PARAM_FS) {
++04611                 if (dwc_otg_param_initialized(core_if->core_params->speed)) {
++04612                         DWC_ERROR
++04613                             ("%d invalid for speed paremter. Check HW configuration.\n",
++04614                              val);
++04615                 }
++04616                 val =
++04617                     (dwc_otg_get_param_phy_type(core_if) ==
++04618                      DWC_PHY_TYPE_PARAM_FS ? 1 : 0);
++04619                 retval = -DWC_E_INVALID;
++04620         }
++04621         core_if->core_params->speed = val;
++04622         return retval;
++04623 }
++04624 
++04625 int32_t dwc_otg_get_param_speed(dwc_otg_core_if_t * core_if)
++04626 {
++04627         return core_if->core_params->speed;
++04628 }
++04629 
++04630 int dwc_otg_set_param_host_ls_low_power_phy_clk(dwc_otg_core_if_t * core_if,
++04631                                                 int32_t val)
++04632 {
++04633         int retval = 0;
++04634 
++04635         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
++04636                 DWC_WARN
++04637                     ("Wrong value for host_ls_low_power_phy_clk parameter\n");
++04638                 DWC_WARN("host_ls_low_power_phy_clk must be 0 or 1\n");
++04639                 return -DWC_E_INVALID;
++04640         }
++04641 
++04642         if ((val == DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ)
++04643             && (dwc_otg_get_param_phy_type(core_if) == DWC_PHY_TYPE_PARAM_FS)) {
++04644                 if(dwc_otg_param_initialized(core_if->core_params->host_ls_low_power_phy_clk)) {
++04645                         DWC_ERROR("%d invalid for host_ls_low_power_phy_clk. Check HW configuration.\n",
++04646                      val);
++04647                 }
++04648                 val =
++04649                     (dwc_otg_get_param_phy_type(core_if) ==
++04650                      DWC_PHY_TYPE_PARAM_FS) ?
++04651                     DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ :
++04652                     DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ;
++04653                 retval = -DWC_E_INVALID;
++04654         }
++04655 
++04656         core_if->core_params->host_ls_low_power_phy_clk = val;
++04657         return retval;
++04658 }
++04659 
++04660 int32_t dwc_otg_get_param_host_ls_low_power_phy_clk(dwc_otg_core_if_t * core_if)
++04661 {
++04662         return core_if->core_params->host_ls_low_power_phy_clk;
++04663 }
++04664 
++04665 int dwc_otg_set_param_phy_ulpi_ddr(dwc_otg_core_if_t * core_if, int32_t val)
++04666 {
++04667         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
++04668                 DWC_WARN("Wrong value for phy_ulpi_ddr\n");
++04669                 DWC_WARN("phy_upli_ddr must be 0 or 1\n");
++04670                 return -DWC_E_INVALID;
++04671         }
++04672 
++04673         core_if->core_params->phy_ulpi_ddr = val;
++04674         return 0;
++04675 }
++04676 
++04677 int32_t dwc_otg_get_param_phy_ulpi_ddr(dwc_otg_core_if_t * core_if)
++04678 {
++04679         return core_if->core_params->phy_ulpi_ddr;
++04680 }
++04681 
++04682 int dwc_otg_set_param_phy_ulpi_ext_vbus(dwc_otg_core_if_t * core_if,
++04683                                         int32_t val)
++04684 {
++04685         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
++04686                 DWC_WARN("Wrong valaue for phy_ulpi_ext_vbus\n");
++04687                 DWC_WARN("phy_ulpi_ext_vbus must be 0 or 1\n");
++04688                 return -DWC_E_INVALID;
++04689         }
++04690 
++04691         core_if->core_params->phy_ulpi_ext_vbus = val;
++04692         return 0;
++04693 }
++04694 
++04695 int32_t dwc_otg_get_param_phy_ulpi_ext_vbus(dwc_otg_core_if_t * core_if)
++04696 {
++04697         return core_if->core_params->phy_ulpi_ext_vbus;
++04698 }
++04699 
++04700 int dwc_otg_set_param_phy_utmi_width(dwc_otg_core_if_t * core_if, int32_t val)
++04701 {
++04702         if (DWC_OTG_PARAM_TEST(val, 8, 8) && DWC_OTG_PARAM_TEST(val, 16, 16)) {
++04703                 DWC_WARN("Wrong valaue for phy_utmi_width\n");
++04704                 DWC_WARN("phy_utmi_width must be 8 or 16\n");
++04705                 return -DWC_E_INVALID;
++04706         }
++04707 
++04708         core_if->core_params->phy_utmi_width = val;
++04709         return 0;
++04710 }
++04711 
++04712 int32_t dwc_otg_get_param_phy_utmi_width(dwc_otg_core_if_t * core_if)
++04713 {
++04714         return core_if->core_params->phy_utmi_width;
++04715 }
++04716 
++04717 int dwc_otg_set_param_ulpi_fs_ls(dwc_otg_core_if_t * core_if, int32_t val)
++04718 {
++04719         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
++04720                 DWC_WARN("Wrong valaue for ulpi_fs_ls\n");
++04721                 DWC_WARN("ulpi_fs_ls must be 0 or 1\n");
++04722                 return -DWC_E_INVALID;
++04723         }
++04724 
++04725         core_if->core_params->ulpi_fs_ls = val;
++04726         return 0;
++04727 }
++04728 
++04729 int32_t dwc_otg_get_param_ulpi_fs_ls(dwc_otg_core_if_t * core_if)
++04730 {
++04731         return core_if->core_params->ulpi_fs_ls;
++04732 }
++04733 
++04734 int dwc_otg_set_param_ts_dline(dwc_otg_core_if_t * core_if, int32_t val)
++04735 {
++04736         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
++04737                 DWC_WARN("Wrong valaue for ts_dline\n");
++04738                 DWC_WARN("ts_dline must be 0 or 1\n");
++04739                 return -DWC_E_INVALID;
++04740         }
++04741 
++04742         core_if->core_params->ts_dline = val;
++04743         return 0;
++04744 }
++04745 
++04746 int32_t dwc_otg_get_param_ts_dline(dwc_otg_core_if_t * core_if)
++04747 {
++04748         return core_if->core_params->ts_dline;
++04749 }
++04750 
++04751 int dwc_otg_set_param_i2c_enable(dwc_otg_core_if_t * core_if, int32_t val)
++04752 {
++04753         int retval = 0;
++04754         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
++04755                 DWC_WARN("Wrong valaue for i2c_enable\n");
++04756                 DWC_WARN("i2c_enable must be 0 or 1\n");
++04757                 return -DWC_E_INVALID;
++04758         }
++04759 #ifndef NO_FS_PHY_HW_CHECK
++04760         if (val == 1 && core_if->hwcfg3.b.i2c == 0) {
++04761                 if(dwc_otg_param_initialized(core_if->core_params->i2c_enable)) {
++04762                         DWC_ERROR("%d invalid for i2c_enable. Check HW configuration.\n",
++04763                      val);
++04764                 }
++04765                 val = 0;
++04766                 retval = -DWC_E_INVALID;
++04767         }
++04768 #endif
++04769 
++04770         core_if->core_params->i2c_enable = val;
++04771         return retval;
++04772 }
++04773 
++04774 int32_t dwc_otg_get_param_i2c_enable(dwc_otg_core_if_t * core_if)
++04775 {
++04776         return core_if->core_params->i2c_enable;
++04777 }
++04778 
++04779 int dwc_otg_set_param_dev_perio_tx_fifo_size(dwc_otg_core_if_t * core_if,
++04780                                              int32_t val, int fifo_num)
++04781 {
++04782         int retval = 0;
++04783 
++04784         if (DWC_OTG_PARAM_TEST(val, 4, 768)) {
++04785                 DWC_WARN("Wrong value for dev_perio_tx_fifo_size\n");
++04786                 DWC_WARN("dev_perio_tx_fifo_size must be 4-768\n");
++04787                 return -DWC_E_INVALID;
++04788         }
++04789 
++04790         if (val > (dwc_read_reg32(&core_if->core_global_regs->dptxfsiz_dieptxf[fifo_num]))) {
++04791                 if(dwc_otg_param_initialized(core_if->core_params->dev_perio_tx_fifo_size[fifo_num])) {
++04792                         DWC_ERROR("`%d' invalid for parameter `dev_perio_fifo_size_%d'. Check HW configuration.\n",
++04793                      val, fifo_num);
++04794                 }
++04795                 val = (dwc_read_reg32(&core_if->core_global_regs->dptxfsiz_dieptxf[fifo_num]));
++04796                 retval = -DWC_E_INVALID;
++04797         }
++04798 
++04799         core_if->core_params->dev_perio_tx_fifo_size[fifo_num] = val;
++04800         return retval;
++04801 }
++04802 
++04803 int32_t dwc_otg_get_param_dev_perio_tx_fifo_size(dwc_otg_core_if_t * core_if,
++04804                                                  int fifo_num)
++04805 {
++04806         return core_if->core_params->dev_perio_tx_fifo_size[fifo_num];
++04807 }
++04808 
++04809 int dwc_otg_set_param_en_multiple_tx_fifo(dwc_otg_core_if_t * core_if,
++04810                                           int32_t val)
++04811 {
++04812         int retval = 0;
++04813         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
++04814                 DWC_WARN("Wrong valaue for en_multiple_tx_fifo,\n");
++04815                 DWC_WARN("en_multiple_tx_fifo must be 0 or 1\n");
++04816                 return -DWC_E_INVALID;
++04817         }
++04818 
++04819         if (val == 1 && core_if->hwcfg4.b.ded_fifo_en == 0) {
++04820                 if(dwc_otg_param_initialized(core_if->core_params->en_multiple_tx_fifo)) {
++04821                         DWC_ERROR("%d invalid for parameter en_multiple_tx_fifo. Check HW configuration.\n",
++04822                      val);
++04823                 }
++04824                 val = 0;
++04825                 retval = -DWC_E_INVALID;
++04826         }
++04827 
++04828         core_if->core_params->en_multiple_tx_fifo = val;
++04829         return retval;
++04830 }
++04831 
++04832 int32_t dwc_otg_get_param_en_multiple_tx_fifo(dwc_otg_core_if_t * core_if)
++04833 {
++04834         return core_if->core_params->en_multiple_tx_fifo;
++04835 }
++04836 
++04837 int dwc_otg_set_param_dev_tx_fifo_size(dwc_otg_core_if_t * core_if, int32_t val,
++04838                                        int fifo_num)
++04839 {
++04840         int retval = 0;
++04841 
++04842         if (DWC_OTG_PARAM_TEST(val, 4, 768)) {
++04843                 DWC_WARN("Wrong value for dev_tx_fifo_size\n");
++04844                 DWC_WARN("dev_tx_fifo_size must be 4-768\n");
++04845                 return -DWC_E_INVALID;
++04846         }
++04847 
++04848         if (val > (dwc_read_reg32(&core_if->core_global_regs->dptxfsiz_dieptxf[fifo_num]))) {
++04849                 if(dwc_otg_param_initialized(core_if->core_params->dev_tx_fifo_size[fifo_num])) {
++04850                         DWC_ERROR("`%d' invalid for parameter `dev_tx_fifo_size_%d'. Check HW configuration.\n",
++04851                      val, fifo_num);
++04852                 }
++04853                 val = (dwc_read_reg32(&core_if->core_global_regs->dptxfsiz_dieptxf[fifo_num]));
++04854                 retval = -DWC_E_INVALID;
++04855         }
++04856 
++04857         core_if->core_params->dev_tx_fifo_size[fifo_num] = val;
++04858         return retval;
++04859 }
++04860 
++04861 int32_t dwc_otg_get_param_dev_tx_fifo_size(dwc_otg_core_if_t * core_if,
++04862                                            int fifo_num)
++04863 {
++04864         return core_if->core_params->dev_tx_fifo_size[fifo_num];
++04865 }
++04866 
++04867 int dwc_otg_set_param_thr_ctl(dwc_otg_core_if_t * core_if, int32_t val)
++04868 {
++04869         int retval = 0;
++04870 
++04871         if (DWC_OTG_PARAM_TEST(val, 0, 7)) {
++04872                 DWC_WARN("Wrong value for thr_ctl\n");
++04873                 DWC_WARN("thr_ctl must be 0-7\n");
++04874                 return -DWC_E_INVALID;
++04875         }
++04876 
++04877         if ((val != 0) &&
++04878             (!dwc_otg_get_param_dma_enable(core_if) ||
++04879              !core_if->hwcfg4.b.ded_fifo_en)) {
++04880                 if(dwc_otg_param_initialized(core_if->core_params->thr_ctl)) {
++04881                         DWC_ERROR("%d invalid for parameter thr_ctl. Check HW configuration.\n",
++04882                      val);
++04883                 }
++04884                 val = 0;
++04885                 retval = -DWC_E_INVALID;
++04886         }
++04887 
++04888         core_if->core_params->thr_ctl = val;
++04889         return retval;
++04890 }
++04891 
++04892 int32_t dwc_otg_get_param_thr_ctl(dwc_otg_core_if_t * core_if)
++04893 {
++04894         return core_if->core_params->thr_ctl;
++04895 }
++04896 
++04897 int dwc_otg_set_param_lpm_enable(dwc_otg_core_if_t * core_if, int32_t val)
++04898 {
++04899         int retval = 0;
++04900 
++04901         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
++04902                 DWC_WARN("Wrong value for lpm_enable\n");
++04903                 DWC_WARN("lpm_enable must be 0 or 1\n");
++04904                 return -DWC_E_INVALID;
++04905         }
++04906 
++04907         if (val && !core_if->hwcfg3.b.otg_lpm_en) {
++04908                 if(dwc_otg_param_initialized(core_if->core_params->lpm_enable)) {
++04909                         DWC_ERROR("%d invalid for parameter lpm_enable. Check HW configuration.\n",
++04910                      val);
++04911                 }
++04912                 val = 0;
++04913                 retval = -DWC_E_INVALID;
++04914         }
++04915 
++04916         core_if->core_params->lpm_enable = val;
++04917         return retval;
++04918 }
++04919 
++04920 int32_t dwc_otg_get_param_lpm_enable(dwc_otg_core_if_t * core_if)
++04921 {
++04922         return core_if->core_params->lpm_enable;
++04923 }
++04924 
++04925 int dwc_otg_set_param_tx_thr_length(dwc_otg_core_if_t * core_if, int32_t val)
++04926 {
++04927         if (DWC_OTG_PARAM_TEST(val, 8, 128)) {
++04928                 DWC_WARN("Wrong valaue for tx_thr_length\n");
++04929                 DWC_WARN("tx_thr_length must be 8 - 128\n");
++04930                 return -DWC_E_INVALID;
++04931         }
++04932 
++04933         core_if->core_params->tx_thr_length = val;
++04934         return 0;
++04935 }
++04936 
++04937 int32_t dwc_otg_get_param_tx_thr_length(dwc_otg_core_if_t * core_if)
++04938 {
++04939         return core_if->core_params->tx_thr_length;
++04940 }
++04941 
++04942 int dwc_otg_set_param_rx_thr_length(dwc_otg_core_if_t * core_if, int32_t val)
++04943 {
++04944         if (DWC_OTG_PARAM_TEST(val, 8, 128)) {
++04945                 DWC_WARN("Wrong valaue for rx_thr_length\n");
++04946                 DWC_WARN("rx_thr_length must be 8 - 128\n");
++04947                 return -DWC_E_INVALID;
++04948         }
++04949 
++04950         core_if->core_params->rx_thr_length = val;
++04951         return 0;
++04952 }
++04953 
++04954 int32_t dwc_otg_get_param_rx_thr_length(dwc_otg_core_if_t * core_if)
++04955 {
++04956         return core_if->core_params->rx_thr_length;
++04957 }
++04958 
++04959 int dwc_otg_set_param_dma_burst_size(dwc_otg_core_if_t * core_if, int32_t val)
++04960 {
++04961         if (DWC_OTG_PARAM_TEST(val, 1, 1) &&
++04962             DWC_OTG_PARAM_TEST(val, 4, 4) &&
++04963             DWC_OTG_PARAM_TEST(val, 8, 8) &&
++04964             DWC_OTG_PARAM_TEST(val, 16, 16) &&
++04965             DWC_OTG_PARAM_TEST(val, 32, 32) &&
++04966             DWC_OTG_PARAM_TEST(val, 64, 64) &&
++04967             DWC_OTG_PARAM_TEST(val, 128, 128) &&
++04968             DWC_OTG_PARAM_TEST(val, 256, 256)) {
++04969                 DWC_WARN("`%d' invalid for parameter `dma_burst_size'\n", val);
++04970                 return -DWC_E_INVALID;
++04971         }
++04972         core_if->core_params->dma_burst_size = val;
++04973         return 0;
++04974 }
++04975 
++04976 int32_t dwc_otg_get_param_dma_burst_size(dwc_otg_core_if_t * core_if)
++04977 {
++04978         return core_if->core_params->dma_burst_size;
++04979 }
++04980 
++04981 int dwc_otg_set_param_pti_enable(dwc_otg_core_if_t * core_if, int32_t val)
++04982 {
++04983         int retval = 0;
++04984         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
++04985                 DWC_WARN("`%d' invalid for parameter `pti_enable'\n", val);
++04986                 return -DWC_E_INVALID;
++04987         }
++04988         if (val && (core_if->snpsid < OTG_CORE_REV_2_72a)) {
++04989                 if (dwc_otg_param_initialized(core_if->core_params->pti_enable)) {
++04990                         DWC_ERROR("%d invalid for parameter pti_enable. Check HW configuration.\n",
++04991                              val);
++04992                 }
++04993                 retval = -DWC_E_INVALID;
++04994                 val = 0;
++04995         }
++04996         core_if->core_params->pti_enable = val;
++04997         return retval;
++04998 }
++04999 
++05000 int32_t dwc_otg_get_param_pti_enable(dwc_otg_core_if_t * core_if)
++05001 {
++05002         return core_if->core_params->pti_enable;
++05003 }
++05004 
++05005 int dwc_otg_set_param_mpi_enable(dwc_otg_core_if_t * core_if, int32_t val)
++05006 {
++05007         int retval = 0;
++05008         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
++05009                 DWC_WARN("`%d' invalid for parameter `mpi_enable'\n", val);
++05010                 return -DWC_E_INVALID;
++05011         }
++05012         if (val && (core_if->hwcfg2.b.multi_proc_int == 0)) {
++05013                 if (dwc_otg_param_initialized(core_if->core_params->mpi_enable)) {
++05014                         DWC_ERROR("%d invalid for parameter mpi_enable. Check HW configuration.\n",
++05015                              val);
++05016                 }
++05017                 retval = -DWC_E_INVALID;
++05018                 val = 0;
++05019         }
++05020         core_if->core_params->mpi_enable = val;
++05021         return retval;
++05022 }
++05023 
++05024 int32_t dwc_otg_get_param_mpi_enable(dwc_otg_core_if_t * core_if)
++05025 {
++05026         return core_if->core_params->mpi_enable;
++05027 }
++05028 
++05029 int dwc_otg_set_param_ic_usb_cap(dwc_otg_core_if_t * core_if,
++05030                                         int32_t val)
++05031 {
++05032         int retval = 0;
++05033         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
++05034                 DWC_WARN("`%d' invalid for parameter `ic_usb_cap'\n", val);
++05035                 DWC_WARN("ic_usb_cap must be 0 or 1\n");
++05036                 return -DWC_E_INVALID;
++05037         }
++05038 
++05039         if (val && (core_if->hwcfg3.b.otg_enable_ic_usb == 0)) {
++05040                 if (dwc_otg_param_initialized(core_if->core_params->ic_usb_cap)) {
++05041                         DWC_ERROR("%d invalid for parameter ic_usb_cap. Check HW configuration.\n",
++05042                              val);
++05043                 }
++05044                 retval = -DWC_E_INVALID;
++05045                 val = 0;
++05046         }
++05047         core_if->core_params->ic_usb_cap = val;
++05048         return retval;
++05049 }
++05050 int32_t dwc_otg_get_param_ic_usb_cap(dwc_otg_core_if_t * core_if)
++05051 {
++05052         return core_if->core_params->ic_usb_cap;
++05053 }
++05054 
++05055 int dwc_otg_set_param_ahb_thr_ratio(dwc_otg_core_if_t * core_if, int32_t val)
++05056 {
++05057         int retval = 0;
++05058         int valid = 1;
++05059 
++05060         if(DWC_OTG_PARAM_TEST(val, 0, 3)) {
++05061                 DWC_WARN("`%d' invalid for parameter `ahb_thr_ratio'\n", val);
++05062                 DWC_WARN("ahb_thr_ratio must be 0 - 3\n");
++05063                 return -DWC_E_INVALID;
++05064         }
++05065 
++05066         if(val && (core_if->snpsid < OTG_CORE_REV_2_81a || !dwc_otg_get_param_thr_ctl(core_if))) {
++05067                 valid = 0;
++05068         } else if(val && ((dwc_otg_get_param_tx_thr_length(core_if) / (1 << val)) < 4)) {
++05069                 valid = 0;
++05070         }
++05071         if(valid == 0) {
++05072                 if(dwc_otg_param_initialized(core_if->core_params->ahb_thr_ratio)) {
++05073                         DWC_ERROR("%d invalid for parameter ahb_thr_ratio. Chack HW configuration.\n", val);
++05074                 }
++05075                 retval = -DWC_E_INVALID;
++05076                 val = 0;
++05077         }
++05078 
++05079         core_if->core_params->ahb_thr_ratio = val;
++05080         return retval;
++05081 }
++05082 int32_t dwc_otg_get_param_ahb_thr_ratio(dwc_otg_core_if_t * core_if)
++05083 {
++05084         return core_if->core_params->ahb_thr_ratio;
++05085 }
++05086 
++05087 
++05088 uint32_t dwc_otg_get_hnpstatus(dwc_otg_core_if_t * core_if)
++05089 {
++05090         gotgctl_data_t otgctl;
++05091         otgctl.d32 = dwc_read_reg32(&core_if->core_global_regs->gotgctl);
++05092         return otgctl.b.hstnegscs;
++05093 }
++05094 
++05095 uint32_t dwc_otg_get_srpstatus(dwc_otg_core_if_t * core_if)
++05096 {
++05097         gotgctl_data_t otgctl;
++05098         otgctl.d32 = dwc_read_reg32(&core_if->core_global_regs->gotgctl);
++05099         return otgctl.b.sesreqscs;
++05100 }
++05101 
++05102 void dwc_otg_set_hnpreq(dwc_otg_core_if_t * core_if, uint32_t val)
++05103 {
++05104         gotgctl_data_t otgctl;
++05105         otgctl.d32 = dwc_read_reg32(&core_if->core_global_regs->gotgctl);
++05106         otgctl.b.hnpreq = val;
++05107         dwc_write_reg32(&core_if->core_global_regs->gotgctl, otgctl.d32);
++05108 }
++05109 
++05110 uint32_t dwc_otg_get_gsnpsid(dwc_otg_core_if_t * core_if)
++05111 {
++05112         return core_if->snpsid;
++05113 }
++05114 
++05115 uint32_t dwc_otg_get_mode(dwc_otg_core_if_t * core_if)
++05116 {
++05117         gotgctl_data_t otgctl;
++05118         otgctl.d32 = dwc_read_reg32(&core_if->core_global_regs->gotgctl);
++05119         return otgctl.b.currmod;
++05120 }
++05121 
++05122 uint32_t dwc_otg_get_hnpcapable(dwc_otg_core_if_t * core_if)
++05123 {
++05124         gusbcfg_data_t usbcfg;
++05125         usbcfg.d32 = dwc_read_reg32(&core_if->core_global_regs->gusbcfg);
++05126         return usbcfg.b.hnpcap;
++05127 }
++05128 
++05129 void dwc_otg_set_hnpcapable(dwc_otg_core_if_t * core_if, uint32_t val)
++05130 {
++05131         gusbcfg_data_t usbcfg;
++05132         usbcfg.d32 = dwc_read_reg32(&core_if->core_global_regs->gusbcfg);
++05133         usbcfg.b.hnpcap = val;
++05134         dwc_write_reg32(&core_if->core_global_regs->gusbcfg, usbcfg.d32);
++05135 }
++05136 
++05137 uint32_t dwc_otg_get_srpcapable(dwc_otg_core_if_t * core_if)
++05138 {
++05139         gusbcfg_data_t usbcfg;
++05140         usbcfg.d32 = dwc_read_reg32(&core_if->core_global_regs->gusbcfg);
++05141         return usbcfg.b.srpcap;
++05142 }
++05143 
++05144 void dwc_otg_set_srpcapable(dwc_otg_core_if_t * core_if, uint32_t val)
++05145 {
++05146         gusbcfg_data_t usbcfg;
++05147         usbcfg.d32 = dwc_read_reg32(&core_if->core_global_regs->gusbcfg);
++05148         usbcfg.b.srpcap = val;
++05149         dwc_write_reg32(&core_if->core_global_regs->gusbcfg, usbcfg.d32);
++05150 }
++05151 
++05152 uint32_t dwc_otg_get_devspeed(dwc_otg_core_if_t * core_if)
++05153 {
++05154         dcfg_data_t dcfg;
++05155         dcfg.d32 = dwc_read_reg32(&core_if->dev_if->dev_global_regs->dcfg);
++05156         return dcfg.b.devspd;
++05157 }
++05158 
++05159 void dwc_otg_set_devspeed(dwc_otg_core_if_t * core_if, uint32_t val)
++05160 {
++05161         dcfg_data_t dcfg;
++05162         dcfg.d32 = dwc_read_reg32(&core_if->dev_if->dev_global_regs->dcfg);
++05163         dcfg.b.devspd = val;
++05164         dwc_write_reg32(&core_if->dev_if->dev_global_regs->dcfg, dcfg.d32);
++05165 }
++05166 
++05167 uint32_t dwc_otg_get_busconnected(dwc_otg_core_if_t * core_if)
++05168 {
++05169         hprt0_data_t hprt0;
++05170         hprt0.d32 = dwc_read_reg32(core_if->host_if->hprt0);
++05171         return hprt0.b.prtconnsts;
++05172 }
++05173 
++05174 uint32_t dwc_otg_get_enumspeed(dwc_otg_core_if_t * core_if)
++05175 {
++05176         dsts_data_t dsts;
++05177         dsts.d32 = dwc_read_reg32(&core_if->dev_if->dev_global_regs->dsts);
++05178         return dsts.b.enumspd;
++05179 }
++05180 
++05181 uint32_t dwc_otg_get_prtpower(dwc_otg_core_if_t * core_if)
++05182 {
++05183         hprt0_data_t hprt0;
++05184         hprt0.d32 = dwc_read_reg32(core_if->host_if->hprt0);
++05185         return hprt0.b.prtpwr;
++05186 
++05187 }
++05188 
++05189 void dwc_otg_set_prtpower(dwc_otg_core_if_t * core_if, uint32_t val)
++05190 {
++05191         hprt0_data_t hprt0;
++05192         hprt0.d32 = dwc_read_reg32(core_if->host_if->hprt0);
++05193         hprt0.b.prtpwr = val;
++05194         dwc_write_reg32(core_if->host_if->hprt0, val);
++05195 }
++05196 
++05197 uint32_t dwc_otg_get_prtsuspend(dwc_otg_core_if_t * core_if)
++05198 {
++05199         hprt0_data_t hprt0;
++05200         hprt0.d32 = dwc_read_reg32(core_if->host_if->hprt0);
++05201         return hprt0.b.prtsusp;
++05202 
++05203 }
++05204 
++05205 void dwc_otg_set_prtsuspend(dwc_otg_core_if_t * core_if, uint32_t val)
++05206 {
++05207         hprt0_data_t hprt0;
++05208         hprt0.d32 = dwc_read_reg32(core_if->host_if->hprt0);
++05209         hprt0.b.prtsusp = val;
++05210         dwc_write_reg32(core_if->host_if->hprt0, val);
++05211 }
++05212 
++05213 void dwc_otg_set_prtresume(dwc_otg_core_if_t * core_if, uint32_t val)
++05214 {
++05215         hprt0_data_t hprt0;
++05216         hprt0.d32 = dwc_read_reg32(core_if->host_if->hprt0);
++05217         hprt0.b.prtres = val;
++05218         dwc_write_reg32(core_if->host_if->hprt0, val);
++05219 }
++05220 
++05221 uint32_t dwc_otg_get_remotewakesig(dwc_otg_core_if_t * core_if)
++05222 {
++05223         dctl_data_t dctl;
++05224         dctl.d32 = dwc_read_reg32(&core_if->dev_if->dev_global_regs->dctl);
++05225         return dctl.b.rmtwkupsig;
++05226 }
++05227 
++05228 uint32_t dwc_otg_get_lpm_portsleepstatus(dwc_otg_core_if_t * core_if)
++05229 {
++05230         glpmcfg_data_t lpmcfg;
++05231         lpmcfg.d32 = dwc_read_reg32(&core_if->core_global_regs->glpmcfg);
++05232 
++05233         DWC_ASSERT(!
++05234                    ((core_if->lx_state == DWC_OTG_L1) ^ lpmcfg.b.prt_sleep_sts),
++05235                    "lx_state = %d, lmpcfg.prt_sleep_sts = %d\n",
++05236                    core_if->lx_state, lpmcfg.b.prt_sleep_sts);
++05237 
++05238         return lpmcfg.b.prt_sleep_sts;
++05239 }
++05240 
++05241 uint32_t dwc_otg_get_lpm_remotewakeenabled(dwc_otg_core_if_t * core_if)
++05242 {
++05243         glpmcfg_data_t lpmcfg;
++05244         lpmcfg.d32 = dwc_read_reg32(&core_if->core_global_regs->glpmcfg);
++05245         return lpmcfg.b.rem_wkup_en;
++05246 }
++05247 
++05248 uint32_t dwc_otg_get_lpmresponse(dwc_otg_core_if_t * core_if)
++05249 {
++05250         glpmcfg_data_t lpmcfg;
++05251         lpmcfg.d32 = dwc_read_reg32(&core_if->core_global_regs->glpmcfg);
++05252         return lpmcfg.b.appl_resp;
++05253 }
++05254 
++05255 void dwc_otg_set_lpmresponse(dwc_otg_core_if_t * core_if, uint32_t val)
++05256 {
++05257         glpmcfg_data_t lpmcfg;
++05258         lpmcfg.d32 = dwc_read_reg32(&core_if->core_global_regs->glpmcfg);
++05259         lpmcfg.b.appl_resp = val;
++05260         dwc_write_reg32(&core_if->core_global_regs->glpmcfg, lpmcfg.d32);
++05261 }
++05262 
++05263 uint32_t dwc_otg_get_hsic_connect(dwc_otg_core_if_t * core_if)
++05264 {
++05265         glpmcfg_data_t lpmcfg;
++05266         lpmcfg.d32 = dwc_read_reg32(&core_if->core_global_regs->glpmcfg);
++05267         return lpmcfg.b.hsic_connect;
++05268 }
++05269 
++05270 void dwc_otg_set_hsic_connect(dwc_otg_core_if_t * core_if, uint32_t val)
++05271 {
++05272         glpmcfg_data_t lpmcfg;
++05273         lpmcfg.d32 = dwc_read_reg32(&core_if->core_global_regs->glpmcfg);
++05274         lpmcfg.b.hsic_connect = val;
++05275         dwc_write_reg32(&core_if->core_global_regs->glpmcfg, lpmcfg.d32);
++05276 }
++05277 
++05278 uint32_t dwc_otg_get_inv_sel_hsic(dwc_otg_core_if_t * core_if)
++05279 {
++05280         glpmcfg_data_t lpmcfg;
++05281         lpmcfg.d32 = dwc_read_reg32(&core_if->core_global_regs->glpmcfg);
++05282         return lpmcfg.b.inv_sel_hsic;
++05283 
++05284 }
++05285 
++05286 void dwc_otg_set_inv_sel_hsic(dwc_otg_core_if_t * core_if, uint32_t val)
++05287 {
++05288         glpmcfg_data_t lpmcfg;
++05289         lpmcfg.d32 = dwc_read_reg32(&core_if->core_global_regs->glpmcfg);
++05290         lpmcfg.b.inv_sel_hsic = val;
++05291         dwc_write_reg32(&core_if->core_global_regs->glpmcfg, lpmcfg.d32);
++05292 }
++05293 
++05294 uint32_t dwc_otg_get_gotgctl(dwc_otg_core_if_t * core_if)
++05295 {
++05296         return dwc_read_reg32(&core_if->core_global_regs->gotgctl);
++05297 }
++05298 
++05299 void dwc_otg_set_gotgctl(dwc_otg_core_if_t * core_if, uint32_t val)
++05300 {
++05301         dwc_write_reg32(&core_if->core_global_regs->gotgctl, val);
++05302 }
++05303 
++05304 uint32_t dwc_otg_get_gusbcfg(dwc_otg_core_if_t * core_if)
++05305 {
++05306         return dwc_read_reg32(&core_if->core_global_regs->gusbcfg);
++05307 }
++05308 
++05309 void dwc_otg_set_gusbcfg(dwc_otg_core_if_t * core_if, uint32_t val)
++05310 {
++05311         dwc_write_reg32(&core_if->core_global_regs->gusbcfg, val);
++05312 }
++05313 
++05314 uint32_t dwc_otg_get_grxfsiz(dwc_otg_core_if_t * core_if)
++05315 {
++05316         return dwc_read_reg32(&core_if->core_global_regs->grxfsiz);
++05317 }
++05318 
++05319 void dwc_otg_set_grxfsiz(dwc_otg_core_if_t * core_if, uint32_t val)
++05320 {
++05321         dwc_write_reg32(&core_if->core_global_regs->grxfsiz, val);
++05322 }
++05323 
++05324 uint32_t dwc_otg_get_gnptxfsiz(dwc_otg_core_if_t * core_if)
++05325 {
++05326         return dwc_read_reg32(&core_if->core_global_regs->gnptxfsiz);
++05327 }
++05328 
++05329 void dwc_otg_set_gnptxfsiz(dwc_otg_core_if_t * core_if, uint32_t val)
++05330 {
++05331         dwc_write_reg32(&core_if->core_global_regs->gnptxfsiz, val);
++05332 }
++05333 
++05334 uint32_t dwc_otg_get_gpvndctl(dwc_otg_core_if_t * core_if)
++05335 {
++05336         return dwc_read_reg32(&core_if->core_global_regs->gpvndctl);
++05337 }
++05338 
++05339 void dwc_otg_set_gpvndctl(dwc_otg_core_if_t * core_if, uint32_t val)
++05340 {
++05341         dwc_write_reg32(&core_if->core_global_regs->gpvndctl, val);
++05342 }
++05343 
++05344 uint32_t dwc_otg_get_ggpio(dwc_otg_core_if_t * core_if)
++05345 {
++05346         return dwc_read_reg32(&core_if->core_global_regs->ggpio);
++05347 }
++05348 
++05349 void dwc_otg_set_ggpio(dwc_otg_core_if_t * core_if, uint32_t val)
++05350 {
++05351         dwc_write_reg32(&core_if->core_global_regs->ggpio, val);
++05352 }
++05353 
++05354 uint32_t dwc_otg_get_hprt0(dwc_otg_core_if_t * core_if)
++05355 {
++05356         return dwc_read_reg32(core_if->host_if->hprt0);
++05357 
++05358 }
++05359 
++05360 void dwc_otg_set_hprt0(dwc_otg_core_if_t * core_if, uint32_t val)
++05361 {
++05362         dwc_write_reg32(core_if->host_if->hprt0, val);
++05363 }
++05364 
++05365 uint32_t dwc_otg_get_guid(dwc_otg_core_if_t * core_if)
++05366 {
++05367         return dwc_read_reg32(&core_if->core_global_regs->guid);
++05368 }
++05369 
++05370 void dwc_otg_set_guid(dwc_otg_core_if_t * core_if, uint32_t val)
++05371 {
++05372         dwc_write_reg32(&core_if->core_global_regs->guid, val);
++05373 }
++05374 
++05375 uint32_t dwc_otg_get_hptxfsiz(dwc_otg_core_if_t * core_if)
++05376 {
++05377         return dwc_read_reg32(&core_if->core_global_regs->hptxfsiz);
++05378 }
++
Generated on Tue May 5 02:22:48 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__cil_8c.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__cil_8c.html 2013-07-26 19:31:20.000000000 +0000 +@@ -0,0 +1,3103 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_cil.c File Reference ++ ++ ++ ++ ++
++
++
++
++

dwc_otg_cil.c File Reference

The Core Interface Layer provides basic services for accessing and managing the DWC_otg hardware. More... ++

++#include "dwc_os.h"
++#include "dwc_otg_regs.h"
++#include "dwc_otg_cil.h"
++ ++

++Go to the source code of this file. ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++

Defines

#define DWC_OTG_PARAM_TEST(_param_, _low_, _high_)

Functions

++static int dwc_otg_setup_params (dwc_otg_core_if_t *core_if)
dwc_otg_core_if_t * dwc_otg_cil_init (const uint32_t *reg_base_addr)
 This function is called to initialize the DWC_otg CSR data structures.
void dwc_otg_cil_remove (dwc_otg_core_if_t *core_if)
 This function frees the structures allocated by dwc_otg_cil_init().
void dwc_otg_enable_global_interrupts (dwc_otg_core_if_t *core_if)
 This function enables the controller's Global Interrupt in the AHB Config register.
void dwc_otg_disable_global_interrupts (dwc_otg_core_if_t *core_if)
 This function disables the controller's Global Interrupt in the AHB Config register.
static void dwc_otg_enable_common_interrupts (dwc_otg_core_if_t *core_if)
 This function initializes the commmon interrupts, used in both device and host modes.
++static void init_fslspclksel (dwc_otg_core_if_t *core_if)
 Initializes the FSLSPClkSel field of the HCFG register depending on the PHY type.
++static void init_devspd (dwc_otg_core_if_t *core_if)
 Initializes the DevSpd field of the DCFG register depending on the PHY type and the enumeration speed of the device.
static uint32_t calc_num_in_eps (dwc_otg_core_if_t *core_if)
 This function calculates the number of IN EPS using GHWCFG1 and GHWCFG2 registers values.
static uint32_t calc_num_out_eps (dwc_otg_core_if_t *core_if)
 This function calculates the number of OUT EPS using GHWCFG1 and GHWCFG2 registers values.
void dwc_otg_core_init (dwc_otg_core_if_t *core_if)
 This function initializes the DWC_otg controller registers and prepares the core for device mode or host mode operation.
void dwc_otg_enable_device_interrupts (dwc_otg_core_if_t *core_if)
 This function enables the Device mode interrupts.
void dwc_otg_core_dev_init (dwc_otg_core_if_t *core_if)
 This function initializes the DWC_otg controller registers for device mode.
void dwc_otg_enable_host_interrupts (dwc_otg_core_if_t *core_if)
 This function enables the Host mode interrupts.
void dwc_otg_disable_host_interrupts (dwc_otg_core_if_t *core_if)
 This function disables the Host Mode interrupts.
void dwc_otg_core_host_init (dwc_otg_core_if_t *core_if)
 This function initializes the DWC_otg controller registers for host mode.
void dwc_otg_hc_init (dwc_otg_core_if_t *core_if, dwc_hc_t *hc)
 Prepares a host channel for transferring packets to/from a specific endpoint.
void dwc_otg_hc_halt (dwc_otg_core_if_t *core_if, dwc_hc_t *hc, dwc_otg_halt_status_e halt_status)
 Attempts to halt a host channel.
void dwc_otg_hc_cleanup (dwc_otg_core_if_t *core_if, dwc_hc_t *hc)
 Clears the transfer state for a host channel.
static void hc_set_even_odd_frame (dwc_otg_core_if_t *core_if, dwc_hc_t *hc, hcchar_data_t *hcchar)
 Sets the channel property that indicates in which frame a periodic transfer should occur.
++void set_pid_isoc (dwc_hc_t *hc)
void dwc_otg_hc_start_transfer (dwc_otg_core_if_t *core_if, dwc_hc_t *hc)
 This function does the setup for a data transfer for a host channel and starts the transfer.
void dwc_otg_hc_start_transfer_ddma (dwc_otg_core_if_t *core_if, dwc_hc_t *hc)
 This function does the setup for a data transfer for a host channel and starts the transfer in Descriptor DMA mode.
int dwc_otg_hc_continue_transfer (dwc_otg_core_if_t *core_if, dwc_hc_t *hc)
 This function continues a data transfer that was started by previous call to dwc_otg_hc_start_transfer.
void dwc_otg_hc_do_ping (dwc_otg_core_if_t *core_if, dwc_hc_t *hc)
 Starts a PING transfer.
++void dwc_otg_hc_write_packet (dwc_otg_core_if_t *core_if, dwc_hc_t *hc)
uint32_t dwc_otg_get_frame_number (dwc_otg_core_if_t *core_if)
 Gets the current USB frame number.
void dwc_otg_read_setup_packet (dwc_otg_core_if_t *core_if, uint32_t *dest)
 This function reads a setup packet from the Rx FIFO into the destination buffer.
void dwc_otg_ep0_activate (dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
 This function enables EP0 OUT to receive SETUP packets and configures EP0 IN for transmitting packets.
void dwc_otg_ep_activate (dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
 This function activates an EP.
void dwc_otg_ep_deactivate (dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
 This function deactivates an EP.
static void init_dma_desc_chain (dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
 This function initializes dma descriptor chain.
void dwc_otg_ep_start_transfer (dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
 This function does the setup for a data transfer for an EP and starts the transfer.
void dwc_otg_ep_start_zl_transfer (dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
 This function setup a zero length transfer in Buffer DMA and Slave modes for usb requests with zero field set.
void dwc_otg_ep0_start_transfer (dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
 This function does the setup for a data transfer for EP0 and starts the transfer.
void dwc_otg_ep0_continue_transfer (dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
 This function continues control IN transfers started by dwc_otg_ep0_start_transfer, when the transfer does not fit in a single packet.
++static void dump_msg (const u8 *buf, unsigned int length)
void dwc_otg_ep_write_packet (dwc_otg_core_if_t *core_if, dwc_ep_t *ep, int dma)
 This function writes a packet into the Tx FIFO associated with the EP.
void dwc_otg_ep_set_stall (dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
 Set the EP STALL.
void dwc_otg_ep_clear_stall (dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
 Clear the EP STALL.
void dwc_otg_read_packet (dwc_otg_core_if_t *core_if, uint8_t *dest, uint16_t bytes)
 This function reads a packet from the Rx FIFO into the destination buffer.
void dwc_otg_dump_dev_registers (dwc_otg_core_if_t *core_if)
 Dump core registers and SPRAM.
void dwc_otg_dump_spram (dwc_otg_core_if_t *core_if)
 This functions reads the SPRAM and prints its content.
void dwc_otg_dump_host_registers (dwc_otg_core_if_t *core_if)
 This function reads the host registers and prints them.
void dwc_otg_dump_global_registers (dwc_otg_core_if_t *core_if)
 This function reads the core global registers and prints them.
void dwc_otg_flush_tx_fifo (dwc_otg_core_if_t *core_if, const int num)
 Flush a Tx FIFO.
void dwc_otg_flush_rx_fifo (dwc_otg_core_if_t *core_if)
 Flush Rx FIFO.
void dwc_otg_core_reset (dwc_otg_core_if_t *core_if)
 Do core a soft reset of the core.
++uint8_t dwc_otg_is_device_mode (dwc_otg_core_if_t *_core_if)
++uint8_t dwc_otg_is_host_mode (dwc_otg_core_if_t *_core_if)
void dwc_otg_cil_register_hcd_callbacks (dwc_otg_core_if_t *core_if, dwc_otg_cil_callbacks_t *cb, void *p)
 Register HCD callbacks.
void dwc_otg_cil_register_pcd_callbacks (dwc_otg_core_if_t *core_if, dwc_otg_cil_callbacks_t *cb, void *p)
 Register PCD callbacks.
void write_isoc_frame_data (dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
 This function writes isoc data per 1 (micro)frame into tx fifo.
void dwc_otg_iso_ep_start_frm_transfer (dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
 This function initializes a descriptor chain for Isochronous transfer.
++static void dwc_otg_set_uninitialized (int32_t *p, int size)
++static int dwc_otg_param_initialized (int32_t val)
++uint8_t dwc_otg_is_dma_enable (dwc_otg_core_if_t *core_if)
int dwc_otg_set_param_otg_cap (dwc_otg_core_if_t *core_if, int32_t val)
 Specifies the OTG capabilities.
++int32_t dwc_otg_get_param_otg_cap (dwc_otg_core_if_t *core_if)
++int dwc_otg_set_param_opt (dwc_otg_core_if_t *core_if, int32_t val)
++int32_t dwc_otg_get_param_opt (dwc_otg_core_if_t *core_if)
int dwc_otg_set_param_dma_enable (dwc_otg_core_if_t *core_if, int32_t val)
 Specifies whether to use slave or DMA mode for accessing the data FIFOs.
++int32_t dwc_otg_get_param_dma_enable (dwc_otg_core_if_t *core_if)
int dwc_otg_set_param_dma_desc_enable (dwc_otg_core_if_t *core_if, int32_t val)
 When DMA mode is enabled specifies whether to use address DMA or DMA Descritor mode for accessing the data FIFOs in device mode.
++int32_t dwc_otg_get_param_dma_desc_enable (dwc_otg_core_if_t *core_if)
int dwc_otg_set_param_host_support_fs_ls_low_power (dwc_otg_core_if_t *core_if, int32_t val)
 Specifies whether low power mode is supported when attached to a Full Speed or Low Speed device in host mode.
++int32_t dwc_otg_get_param_host_support_fs_ls_low_power (dwc_otg_core_if_t *core_if)
++int dwc_otg_set_param_enable_dynamic_fifo (dwc_otg_core_if_t *core_if, int32_t val)
 0 - Use cC FIFO size parameters 1 - Allow dynamic FIFO sizing (default)
++int32_t dwc_otg_get_param_enable_dynamic_fifo (dwc_otg_core_if_t *core_if)
int dwc_otg_set_param_data_fifo_size (dwc_otg_core_if_t *core_if, int32_t val)
 Total number of 4-byte words in the data FIFO memory.
++int32_t dwc_otg_get_param_data_fifo_size (dwc_otg_core_if_t *core_if)
int dwc_otg_set_param_dev_rx_fifo_size (dwc_otg_core_if_t *core_if, int32_t val)
 Number of 4-byte words in the Rx FIFO in device mode when dynamic FIFO sizing is enabled.
++int32_t dwc_otg_get_param_dev_rx_fifo_size (dwc_otg_core_if_t *core_if)
int dwc_otg_set_param_dev_nperio_tx_fifo_size (dwc_otg_core_if_t *core_if, int32_t val)
 Number of 4-byte words in the non-periodic Tx FIFO in device mode when dynamic FIFO sizing is enabled.
++int32_t dwc_otg_get_param_dev_nperio_tx_fifo_size (dwc_otg_core_if_t *core_if)
int dwc_otg_set_param_host_rx_fifo_size (dwc_otg_core_if_t *core_if, int32_t val)
 Number of 4-byte words in the Rx FIFO in host mode when dynamic FIFO sizing is enabled.
++int32_t dwc_otg_get_param_host_rx_fifo_size (dwc_otg_core_if_t *core_if)
int dwc_otg_set_param_host_nperio_tx_fifo_size (dwc_otg_core_if_t *core_if, int32_t val)
 Number of 4-byte words in the non-periodic Tx FIFO in host mode when Dynamic FIFO sizing is enabled in the core.
++int32_t dwc_otg_get_param_host_nperio_tx_fifo_size (dwc_otg_core_if_t *core_if)
int dwc_otg_set_param_host_perio_tx_fifo_size (dwc_otg_core_if_t *core_if, int32_t val)
 Number of 4-byte words in the host periodic Tx FIFO when dynamic FIFO sizing is enabled.
++int32_t dwc_otg_get_param_host_perio_tx_fifo_size (dwc_otg_core_if_t *core_if)
int dwc_otg_set_param_max_transfer_size (dwc_otg_core_if_t *core_if, int32_t val)
 The maximum transfer size supported in bytes.
++int32_t dwc_otg_get_param_max_transfer_size (dwc_otg_core_if_t *core_if)
int dwc_otg_set_param_max_packet_count (dwc_otg_core_if_t *core_if, int32_t val)
 The maximum number of packets in a transfer.
++int32_t dwc_otg_get_param_max_packet_count (dwc_otg_core_if_t *core_if)
int dwc_otg_set_param_host_channels (dwc_otg_core_if_t *core_if, int32_t val)
 The number of host channel registers to use.
++int32_t dwc_otg_get_param_host_channels (dwc_otg_core_if_t *core_if)
int dwc_otg_set_param_dev_endpoints (dwc_otg_core_if_t *core_if, int32_t val)
 The number of endpoints in addition to EP0 available for device mode operations.
++int32_t dwc_otg_get_param_dev_endpoints (dwc_otg_core_if_t *core_if)
int dwc_otg_set_param_phy_type (dwc_otg_core_if_t *core_if, int32_t val)
 Specifies the type of PHY interface to use.
++int32_t dwc_otg_get_param_phy_type (dwc_otg_core_if_t *core_if)
int dwc_otg_set_param_speed (dwc_otg_core_if_t *core_if, int32_t val)
 Specifies the maximum speed of operation in host and device mode.
++int32_t dwc_otg_get_param_speed (dwc_otg_core_if_t *core_if)
int dwc_otg_set_param_host_ls_low_power_phy_clk (dwc_otg_core_if_t *core_if, int32_t val)
 Specifies the PHY clock rate in low power mode when connected to a Low Speed device in host mode.
++int32_t dwc_otg_get_param_host_ls_low_power_phy_clk (dwc_otg_core_if_t *core_if)
int dwc_otg_set_param_phy_ulpi_ddr (dwc_otg_core_if_t *core_if, int32_t val)
 Specifies whether the ULPI operates at double or single data rate.
++int32_t dwc_otg_get_param_phy_ulpi_ddr (dwc_otg_core_if_t *core_if)
++int dwc_otg_set_param_phy_ulpi_ext_vbus (dwc_otg_core_if_t *core_if, int32_t val)
 Specifies whether to use the internal or external supply to drive the vbus with a ULPI phy.
++int32_t dwc_otg_get_param_phy_ulpi_ext_vbus (dwc_otg_core_if_t *core_if)
int dwc_otg_set_param_phy_utmi_width (dwc_otg_core_if_t *core_if, int32_t val)
 Specifies the UTMI+ Data Width.
++int32_t dwc_otg_get_param_phy_utmi_width (dwc_otg_core_if_t *core_if)
++int dwc_otg_set_param_ulpi_fs_ls (dwc_otg_core_if_t *core_if, int32_t val)
++int32_t dwc_otg_get_param_ulpi_fs_ls (dwc_otg_core_if_t *core_if)
++int dwc_otg_set_param_ts_dline (dwc_otg_core_if_t *core_if, int32_t val)
++int32_t dwc_otg_get_param_ts_dline (dwc_otg_core_if_t *core_if)
int dwc_otg_set_param_i2c_enable (dwc_otg_core_if_t *core_if, int32_t val)
 Specifies whether to use the I2Cinterface for full speed PHY.
++int32_t dwc_otg_get_param_i2c_enable (dwc_otg_core_if_t *core_if)
int dwc_otg_set_param_dev_perio_tx_fifo_size (dwc_otg_core_if_t *core_if, int32_t val, int fifo_num)
 Number of 4-byte words in each of the periodic Tx FIFOs in device mode when dynamic FIFO sizing is enabled.
++int32_t dwc_otg_get_param_dev_perio_tx_fifo_size (dwc_otg_core_if_t *core_if, int fifo_num)
++int dwc_otg_set_param_en_multiple_tx_fifo (dwc_otg_core_if_t *core_if, int32_t val)
 Specifies whether dedicated transmit FIFOs are enabled for non periodic IN endpoints in device mode 0 - No 1 - Yes.
++int32_t dwc_otg_get_param_en_multiple_tx_fifo (dwc_otg_core_if_t *core_if)
++int dwc_otg_set_param_dev_tx_fifo_size (dwc_otg_core_if_t *core_if, int32_t val, int fifo_num)
++int32_t dwc_otg_get_param_dev_tx_fifo_size (dwc_otg_core_if_t *core_if, int fifo_num)
++int dwc_otg_set_param_thr_ctl (dwc_otg_core_if_t *core_if, int32_t val)
 Thresholding enable flag- bit 0 - enable non-ISO Tx thresholding bit 1 - enable ISO Tx thresholding bit 2 - enable Rx thresholding.
++int32_t dwc_otg_get_param_thr_ctl (dwc_otg_core_if_t *core_if)
++int dwc_otg_set_param_lpm_enable (dwc_otg_core_if_t *core_if, int32_t val)
 Specifies whether LPM (Link Power Management) support is enabled.
++int32_t dwc_otg_get_param_lpm_enable (dwc_otg_core_if_t *core_if)
++int dwc_otg_set_param_tx_thr_length (dwc_otg_core_if_t *core_if, int32_t val)
 Thresholding length for Tx FIFOs in 32 bit DWORDs.
++int32_t dwc_otg_get_param_tx_thr_length (dwc_otg_core_if_t *core_if)
++int dwc_otg_set_param_rx_thr_length (dwc_otg_core_if_t *core_if, int32_t val)
 Thresholding length for Rx FIFOs in 32 bit DWORDs.
++int32_t dwc_otg_get_param_rx_thr_length (dwc_otg_core_if_t *core_if)
int dwc_otg_set_param_dma_burst_size (dwc_otg_core_if_t *core_if, int32_t val)
 The DMA Burst size (applicable only for External DMA Mode).
++int32_t dwc_otg_get_param_dma_burst_size (dwc_otg_core_if_t *core_if)
++int dwc_otg_set_param_pti_enable (dwc_otg_core_if_t *core_if, int32_t val)
 Specifies whether PTI enhancement is enabled.
++int32_t dwc_otg_get_param_pti_enable (dwc_otg_core_if_t *core_if)
++int dwc_otg_set_param_mpi_enable (dwc_otg_core_if_t *core_if, int32_t val)
 Specifies whether MPI enhancement is enabled.
++int32_t dwc_otg_get_param_mpi_enable (dwc_otg_core_if_t *core_if)
++int dwc_otg_set_param_ic_usb_cap (dwc_otg_core_if_t *core_if, int32_t val)
 Specifies whether IC_USB capability is enabled.
++int32_t dwc_otg_get_param_ic_usb_cap (dwc_otg_core_if_t *core_if)
++int dwc_otg_set_param_ahb_thr_ratio (dwc_otg_core_if_t *core_if, int32_t val)
++int32_t dwc_otg_get_param_ahb_thr_ratio (dwc_otg_core_if_t *core_if)
++uint32_t dwc_otg_get_hnpstatus (dwc_otg_core_if_t *core_if)
 Get host negotiation status.
++uint32_t dwc_otg_get_srpstatus (dwc_otg_core_if_t *core_if)
 Get srp status.
++void dwc_otg_set_hnpreq (dwc_otg_core_if_t *core_if, uint32_t val)
 Set hnpreq bit in the GOTGCTL register.
++uint32_t dwc_otg_get_gsnpsid (dwc_otg_core_if_t *core_if)
 Get Content of SNPSID register.
uint32_t dwc_otg_get_mode (dwc_otg_core_if_t *core_if)
 Get current mode.
++uint32_t dwc_otg_get_hnpcapable (dwc_otg_core_if_t *core_if)
 Get value of hnpcapable field in the GUSBCFG register.
++void dwc_otg_set_hnpcapable (dwc_otg_core_if_t *core_if, uint32_t val)
 Set value of hnpcapable field in the GUSBCFG register.
++uint32_t dwc_otg_get_srpcapable (dwc_otg_core_if_t *core_if)
 Get value of srpcapable field in the GUSBCFG register.
++void dwc_otg_set_srpcapable (dwc_otg_core_if_t *core_if, uint32_t val)
 Set value of srpcapable field in the GUSBCFG register.
++uint32_t dwc_otg_get_devspeed (dwc_otg_core_if_t *core_if)
 Get value of devspeed field in the DCFG register.
++void dwc_otg_set_devspeed (dwc_otg_core_if_t *core_if, uint32_t val)
 Set value of devspeed field in the DCFG register.
++uint32_t dwc_otg_get_busconnected (dwc_otg_core_if_t *core_if)
 Get the value of busconnected field from the HPRT0 register.
++uint32_t dwc_otg_get_enumspeed (dwc_otg_core_if_t *core_if)
 Gets the device enumeration Speed.
++uint32_t dwc_otg_get_prtpower (dwc_otg_core_if_t *core_if)
 Get value of prtpwr field from the HPRT0 register.
++void dwc_otg_set_prtpower (dwc_otg_core_if_t *core_if, uint32_t val)
 Set value of prtpwr field from the HPRT0 register.
++uint32_t dwc_otg_get_prtsuspend (dwc_otg_core_if_t *core_if)
 Get value of prtsusp field from the HPRT0 regsiter.
++void dwc_otg_set_prtsuspend (dwc_otg_core_if_t *core_if, uint32_t val)
 Set value of prtpwr field from the HPRT0 register.
++void dwc_otg_set_prtresume (dwc_otg_core_if_t *core_if, uint32_t val)
 Set value of prtres field from the HPRT0 register FIXME Remove?
++uint32_t dwc_otg_get_remotewakesig (dwc_otg_core_if_t *core_if)
 Get value of rmtwkupsig bit in DCTL register.
++uint32_t dwc_otg_get_lpm_portsleepstatus (dwc_otg_core_if_t *core_if)
 Get value of prt_sleep_sts field from the GLPMCFG register.
++uint32_t dwc_otg_get_lpm_remotewakeenabled (dwc_otg_core_if_t *core_if)
 Get value of rem_wkup_en field from the GLPMCFG register.
++uint32_t dwc_otg_get_lpmresponse (dwc_otg_core_if_t *core_if)
 Get value of appl_resp field from the GLPMCFG register.
++void dwc_otg_set_lpmresponse (dwc_otg_core_if_t *core_if, uint32_t val)
 Set value of appl_resp field from the GLPMCFG register.
++uint32_t dwc_otg_get_hsic_connect (dwc_otg_core_if_t *core_if)
 Get value of hsic_connect field from the GLPMCFG register.
++void dwc_otg_set_hsic_connect (dwc_otg_core_if_t *core_if, uint32_t val)
 Set value of hsic_connect field from the GLPMCFG register.
++uint32_t dwc_otg_get_inv_sel_hsic (dwc_otg_core_if_t *core_if)
 Get value of inv_sel_hsic field from the GLPMCFG register.
++void dwc_otg_set_inv_sel_hsic (dwc_otg_core_if_t *core_if, uint32_t val)
 Set value of inv_sel_hsic field from the GLPMFG register.
++uint32_t dwc_otg_get_gotgctl (dwc_otg_core_if_t *core_if)
 GOTGCTL register.
++void dwc_otg_set_gotgctl (dwc_otg_core_if_t *core_if, uint32_t val)
++uint32_t dwc_otg_get_gusbcfg (dwc_otg_core_if_t *core_if)
 GUSBCFG register.
++void dwc_otg_set_gusbcfg (dwc_otg_core_if_t *core_if, uint32_t val)
++uint32_t dwc_otg_get_grxfsiz (dwc_otg_core_if_t *core_if)
 GRXFSIZ register.
++void dwc_otg_set_grxfsiz (dwc_otg_core_if_t *core_if, uint32_t val)
++uint32_t dwc_otg_get_gnptxfsiz (dwc_otg_core_if_t *core_if)
 GNPTXFSIZ register.
++void dwc_otg_set_gnptxfsiz (dwc_otg_core_if_t *core_if, uint32_t val)
++uint32_t dwc_otg_get_gpvndctl (dwc_otg_core_if_t *core_if)
++void dwc_otg_set_gpvndctl (dwc_otg_core_if_t *core_if, uint32_t val)
++uint32_t dwc_otg_get_ggpio (dwc_otg_core_if_t *core_if)
 GGPIO register.
++void dwc_otg_set_ggpio (dwc_otg_core_if_t *core_if, uint32_t val)
++uint32_t dwc_otg_get_hprt0 (dwc_otg_core_if_t *core_if)
 HPRT0 register.
++void dwc_otg_set_hprt0 (dwc_otg_core_if_t *core_if, uint32_t val)
++uint32_t dwc_otg_get_guid (dwc_otg_core_if_t *core_if)
 GUID register.
++void dwc_otg_set_guid (dwc_otg_core_if_t *core_if, uint32_t val)
++uint32_t dwc_otg_get_hptxfsiz (dwc_otg_core_if_t *core_if)
 GHPTXFSIZE.
++

Detailed Description

++The Core Interface Layer provides basic services for accessing and managing the DWC_otg hardware. ++

++These services are used by both the Host Controller Driver and the Peripheral Controller Driver.

++The CIL manages the memory map for the core so that the HCD and PCD don't have to do this separately. It also handles basic tasks like reading/writing the registers and data FIFOs in the controller. Some of the data access functions provide encapsulation of several operations required to perform a task, such as writing multiple registers to start a transfer. Finally, the CIL performs basic services that are not specific to either the host or device modes of operation. These services include management of the OTG Host Negotiation Protocol (HNP) and Session Request Protocol (SRP). A Diagnostic API is also provided to allow testing of the controller hardware.

++The Core Interface Layer has the following requirements:

    ++
  • Provides basic controller operations.
  • Minimal use of OS services.
  • The OS services used will be abstracted by using inline functions or macros.
++ ++

++Definition in file dwc_otg_cil.c.

Define Documentation

++ ++
++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
#define DWC_OTG_PARAM_TEST (_param_,
_low_,
_high_   ) 
++
++
++ ++

++Value:

(((_param_) < (_low_)) || \
++                ((_param_) > (_high_)))
++
++

++Definition at line 4051 of file dwc_otg_cil.c. ++

++

++

Function Documentation

++ ++
++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
dwc_otg_core_if_t* dwc_otg_cil_init (const uint32_t *  reg_base_addr  ) 
++
++
++ ++

++This function is called to initialize the DWC_otg CSR data structures. ++

++The register addresses in the device and host structures are initialized from the base address supplied by the caller. The calling function must make the OS calls to get the base address of the DWC_otg controller registers. The core_params argument holds the parameters that specify how the core should be configured.

++

Parameters:
++ ++ ++
reg_base_addr Base address of DWC_otg core registers
++
++ ++

++Definition at line 78 of file dwc_otg_cil.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_otg_cil_remove (dwc_otg_core_if_t *  core_if  ) 
++
++
++ ++

++This function frees the structures allocated by dwc_otg_cil_init(). ++

++

Parameters:
++ ++ ++
core_if The core interface pointer returned from dwc_otg_cil_init().
++
++ ++

++Definition at line 265 of file dwc_otg_cil.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_otg_enable_global_interrupts (dwc_otg_core_if_t *  core_if  ) 
++
++
++ ++

++This function enables the controller's Global Interrupt in the AHB Config register. ++

++

Parameters:
++ ++ ++
core_if Programming view of DWC_otg controller.
++
++ ++

++Definition at line 292 of file dwc_otg_cil.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_otg_disable_global_interrupts (dwc_otg_core_if_t *  core_if  ) 
++
++
++ ++

++This function disables the controller's Global Interrupt in the AHB Config register. ++

++

Parameters:
++ ++ ++
core_if Programming view of DWC_otg controller.
++
++ ++

++Definition at line 305 of file dwc_otg_cil.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
static void dwc_otg_enable_common_interrupts (dwc_otg_core_if_t *  core_if  )  [static]
++
++
++ ++

++This function initializes the commmon interrupts, used in both device and host modes. ++

++

Parameters:
++ ++ ++
core_if Programming view of the DWC_otg controller
++
++ ++

++Definition at line 319 of file dwc_otg_cil.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
static uint32_t calc_num_in_eps (dwc_otg_core_if_t *  core_if  )  [static]
++
++
++ ++

++This function calculates the number of IN EPS using GHWCFG1 and GHWCFG2 registers values. ++

++

Parameters:
++ ++ ++
core_if Programming view of the DWC_otg controller
++
++ ++

++Definition at line 415 of file dwc_otg_cil.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
static uint32_t calc_num_out_eps (dwc_otg_core_if_t *  core_if  )  [static]
++
++
++ ++

++This function calculates the number of OUT EPS using GHWCFG1 and GHWCFG2 registers values. ++

++

Parameters:
++ ++ ++
core_if Programming view of the DWC_otg controller
++
++ ++

++Definition at line 444 of file dwc_otg_cil.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_otg_core_init (dwc_otg_core_if_t *  core_if  ) 
++
++
++ ++

++This function initializes the DWC_otg controller registers and prepares the core for device mode or host mode operation. ++

++

Parameters:
++ ++ ++
core_if Programming view of the DWC_otg controller
++
++ ++

++Definition at line 467 of file dwc_otg_cil.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_otg_enable_device_interrupts (dwc_otg_core_if_t *  core_if  ) 
++
++
++ ++

++This function enables the Device mode interrupts. ++

++

Parameters:
++ ++ ++
core_if Programming view of DWC_otg controller
++
++ ++

++

Todo:
NGS: Should this be a module parameter?
++ ++

++Definition at line 772 of file dwc_otg_cil.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_otg_core_dev_init (dwc_otg_core_if_t *  core_if  ) 
++
++
++ ++

++This function initializes the DWC_otg controller registers for device mode. ++

++

Parameters:
++ ++ ++
core_if Programming view of DWC_otg controller
++
++ ++

++Set Periodic Tx FIFO Mask all bits 0

++Set Tx FIFO Mask all bits 0

++

Todo:
NGS: Fix Periodic FIFO Sizing!
++

++

Todo:
Finish debug of this
++

++

Todo:
    ++
  • if the condition needed to be checked or in any case all pending interrutps should be cleared?
++
++ ++

++Definition at line 843 of file dwc_otg_cil.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_otg_enable_host_interrupts (dwc_otg_core_if_t *  core_if  ) 
++
++
++ ++

++This function enables the Host mode interrupts. ++

++

Parameters:
++ ++ ++
core_if Programming view of DWC_otg controller
++
++ ++

++Definition at line 1130 of file dwc_otg_cil.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_otg_disable_host_interrupts (dwc_otg_core_if_t *  core_if  ) 
++
++
++ ++

++This function disables the Host Mode interrupts. ++

++

Parameters:
++ ++ ++
core_if Programming view of DWC_otg controller
++
++ ++

++Definition at line 1165 of file dwc_otg_cil.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_otg_core_host_init (dwc_otg_core_if_t *  core_if  ) 
++
++
++ ++

++This function initializes the DWC_otg controller registers for host mode. ++

++This function flushes the Tx and Rx FIFOs and it flushes any entries in the request queues. Host channels are reset to ensure that they are ready for performing transfers.

++

Parameters:
++ ++ ++
core_if Programming view of DWC_otg controller
++
++ ++

++Definition at line 1196 of file dwc_otg_cil.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_otg_hc_init (dwc_otg_core_if_t *  core_if,
dwc_hc_t *  hc 
)
++
++
++ ++

++Prepares a host channel for transferring packets to/from a specific endpoint. ++

++The HCCHARn register is set up with the characteristics specified in _hc. Host channel interrupts that may need to be serviced while this transfer is in progress are enabled.

++

Parameters:
++ ++ ++ ++
core_if Programming view of DWC_otg controller
hc Information needed to initialize the host channel
++
++ ++

++Definition at line 1352 of file dwc_otg_cil.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_otg_hc_halt (dwc_otg_core_if_t *  core_if,
dwc_hc_t *  hc,
dwc_otg_halt_status_e  halt_status 
)
++
++
++ ++

++Attempts to halt a host channel. ++

++This function should only be called in Slave mode or to abort a transfer in either Slave mode or DMA mode. Under normal circumstances in DMA mode, the controller halts the channel when the transfer is complete or a condition occurs that requires application intervention.

++In slave mode, checks for a free request queue entry, then sets the Channel Enable and Channel Disable bits of the Host Channel Characteristics register of the specified channel to intiate the halt. If there is no free request queue entry, sets only the Channel Disable bit of the HCCHARn register to flush requests for this channel. In the latter case, sets a flag to indicate that the host channel needs to be halted when a request queue slot is open.

++In DMA mode, always sets the Channel Enable and Channel Disable bits of the HCCHARn register. The controller ensures there is space in the request queue before submitting the halt request.

++Some time may elapse before the core flushes any posted requests for this host channel and halts. The Channel Halted interrupt handler completes the deactivation of the host channel.

++

Parameters:
++ ++ ++ ++ ++
core_if Controller register interface.
hc Host channel to halt.
halt_status Reason for halting the channel.
++
++ ++

++Definition at line 1540 of file dwc_otg_cil.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_otg_hc_cleanup (dwc_otg_core_if_t *  core_if,
dwc_hc_t *  hc 
)
++
++
++ ++

++Clears the transfer state for a host channel. ++

++This function is normally called after a transfer is done and the host channel is being released.

++

Parameters:
++ ++ ++ ++
core_if Programming view of DWC_otg controller.
hc Identifies the host channel to clean up.
++
++ ++

++Definition at line 1667 of file dwc_otg_cil.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
static void hc_set_even_odd_frame (dwc_otg_core_if_t *  core_if,
dwc_hc_t *  hc,
hcchar_data_t *  hcchar 
) [inline, static]
++
++
++ ++

++Sets the channel property that indicates in which frame a periodic transfer should occur. ++

++This is always set to the _next_ frame. This function has no effect on non-periodic transfers.

++

Parameters:
++ ++ ++ ++ ++
core_if Programming view of DWC_otg controller.
hc Identifies the host channel to set up and its properties.
hcchar Current value of the HCCHAR register for the specified host channel.
++
++ ++

++Definition at line 1695 of file dwc_otg_cil.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_otg_hc_start_transfer (dwc_otg_core_if_t *  core_if,
dwc_hc_t *  hc 
)
++
++
++ ++

++This function does the setup for a data transfer for a host channel and starts the transfer. ++

++May be called in either Slave mode or DMA mode. In Slave mode, the caller must ensure that there is sufficient space in the request queue and Tx Data FIFO.

++For an OUT transfer in Slave mode, it loads a data packet into the appropriate FIFO. If necessary, additional data packets will be loaded in the Host ISR.

++For an IN transfer in Slave mode, a data packet is requested. The data packets are unloaded from the Rx FIFO in the Host ISR. If necessary, additional data packets are requested in the Host ISR.

++For a PING transfer in Slave mode, the Do Ping bit is set in the HCTSIZ register along with a packet count of 1 and the channel is enabled. This causes a single PING transaction to occur. Other fields in HCTSIZ are simply set to 0 since no data transfer occurs in this case.

++For a PING transfer in DMA mode, the HCTSIZ register is initialized with all the information required to perform the subsequent data transfer. In addition, the Do Ping bit is set in the HCTSIZ register. In this case, the controller performs the entire PING protocol, then starts the data transfer.

++

Parameters:
++ ++ ++ ++
core_if Programming view of DWC_otg controller.
hc Information needed to initialize the host channel. The xfer_len value may be reduced to accommodate the max widths of the XferSize and PktCnt fields in the HCTSIZn register. The multi_count value may be changed to reflect the final xfer_len value.
++
++ ++

++Definition at line 1800 of file dwc_otg_cil.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_otg_hc_start_transfer_ddma (dwc_otg_core_if_t *  core_if,
dwc_hc_t *  hc 
)
++
++
++ ++

++This function does the setup for a data transfer for a host channel and starts the transfer in Descriptor DMA mode. ++

++Initializes HCTSIZ register. For a PING transfer the Do Ping bit is set. Sets PID and NTD values. For periodic transfers initializes SCHED_INFO field with micro-frame bitmap.

++Initializes HCDMA register with descriptor list address and CTD value then starts the transfer via enabling the channel.

++

Parameters:
++ ++ ++ ++
core_if Programming view of DWC_otg controller.
hc Information needed to initialize the host channel.
++
++ ++

++Definition at line 1968 of file dwc_otg_cil.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int dwc_otg_hc_continue_transfer (dwc_otg_core_if_t *  core_if,
dwc_hc_t *  hc 
)
++
++
++ ++

++This function continues a data transfer that was started by previous call to dwc_otg_hc_start_transfer. ++

++The caller must ensure there is sufficient space in the request queue and Tx Data FIFO. This function should only be called in Slave mode. In DMA mode, the controller acts autonomously to complete transfers programmed to a host channel.

++For an OUT transfer, a new data packet is loaded into the appropriate FIFO if there is any data remaining to be queued. For an IN transfer, another data packet is always requested. For the SETUP phase of a control transfer, this function does nothing.

++

Returns:
1 if a new request is queued, 0 if no more requests are required for this transfer.
++ ++

++Definition at line 2048 of file dwc_otg_cil.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_otg_hc_do_ping (dwc_otg_core_if_t *  core_if,
dwc_hc_t *  hc 
)
++
++
++ ++

++Starts a PING transfer. ++

++This function should only be called in Slave mode. The Do Ping bit is set in the HCTSIZ register, then the channel is enabled. ++

++Definition at line 2110 of file dwc_otg_cil.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
uint32_t dwc_otg_get_frame_number (dwc_otg_core_if_t *  core_if  ) 
++
++
++ ++

++Gets the current USB frame number. ++

++This is the frame number from the last SOF packet. ++

++Definition at line 2182 of file dwc_otg_cil.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_otg_read_setup_packet (dwc_otg_core_if_t *  core_if,
uint32_t *  dest 
)
++
++
++ ++

++This function reads a setup packet from the Rx FIFO into the destination buffer. ++

++This function is called from the Rx Status Queue Level (RxStsQLvl) Interrupt routine when a SETUP packet has been received in Slave mode.

++

Parameters:
++ ++ ++ ++
core_if Programming view of DWC_otg controller.
dest Destination buffer for packet data.
++
++ ++

++Definition at line 2199 of file dwc_otg_cil.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_otg_ep0_activate (dwc_otg_core_if_t *  core_if,
dwc_ep_t *  ep 
)
++
++
++ ++

++This function enables EP0 OUT to receive SETUP packets and configures EP0 IN for transmitting packets. ++

++It is normally called when the "Enumeration Done" interrupt occurs.

++

Parameters:
++ ++ ++ ++
core_if Programming view of DWC_otg controller.
ep The EP0 data.
++
++ ++

++Definition at line 2216 of file dwc_otg_cil.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_otg_ep_activate (dwc_otg_core_if_t *  core_if,
dwc_ep_t *  ep 
)
++
++
++ ++

++This function activates an EP. ++

++The Device EP control register for the EP is configured as defined in the ep structure. Note: This function is not used for EP0.

++

Parameters:
++ ++ ++ ++
core_if Programming view of DWC_otg controller.
ep The EP to activate.
++
++ ++

++Definition at line 2268 of file dwc_otg_cil.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_otg_ep_deactivate (dwc_otg_core_if_t *  core_if,
dwc_ep_t *  ep 
)
++
++
++ ++

++This function deactivates an EP. ++

++This is done by clearing the USB Active EP bit in the Device EP control register. Note: This function is not used for EP0. EP0 cannot be deactivated.

++

Parameters:
++ ++ ++ ++
core_if Programming view of DWC_otg controller.
ep The EP to deactivate.
++
++ ++

++Definition at line 2367 of file dwc_otg_cil.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
static void init_dma_desc_chain (dwc_otg_core_if_t *  core_if,
dwc_ep_t *  ep 
) [static]
++
++
++ ++

++This function initializes dma descriptor chain. ++

++

Parameters:
++ ++ ++ ++
core_if Programming view of DWC_otg controller.
ep The EP to start the transfer on.
++
++ ++

++DMA Descriptor Setup ++

++Definition at line 2415 of file dwc_otg_cil.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_otg_ep_start_transfer (dwc_otg_core_if_t *  core_if,
dwc_ep_t *  ep 
)
++
++
++ ++

++This function does the setup for a data transfer for an EP and starts the transfer. ++

++For an IN transfer, the packets will be loaded into the appropriate Tx FIFO in the ISR. For OUT transfers, the packets are unloaded from the Rx FIFO in the ISR. the ISR.

++

Parameters:
++ ++ ++ ++
core_if Programming view of DWC_otg controller.
ep The EP to start the transfer on.
++
++ ++

++DIEPDMAn Register write

++Enable the Non-Periodic Tx FIFO empty interrupt, or the Tx FIFO epmty interrupt in dedicated Tx FIFO mode, the data will be written into the fifo by the ISR.

++DOEPDMAn Register write ++

++Definition at line 2475 of file dwc_otg_cil.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_otg_ep_start_zl_transfer (dwc_otg_core_if_t *  core_if,
dwc_ep_t *  ep 
)
++
++
++ ++

++This function setup a zero length transfer in Buffer DMA and Slave modes for usb requests with zero field set. ++

++

Parameters:
++ ++ ++ ++
core_if Programming view of DWC_otg controller.
ep The EP to start the transfer on.
++
++ ++

++Enable the Non-Periodic Tx FIFO empty interrupt, or the Tx FIFO epmty interrupt in dedicated Tx FIFO mode, the data will be written into the fifo by the ISR. ++

++Definition at line 2678 of file dwc_otg_cil.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_otg_ep0_start_transfer (dwc_otg_core_if_t *  core_if,
dwc_ep_t *  ep 
)
++
++
++ ++

++This function does the setup for a data transfer for EP0 and starts the transfer. ++

++For an IN transfer, the packets will be loaded into the appropriate Tx FIFO in the ISR. For OUT transfers, the packets are unloaded from the Rx FIFO in the ISR.

++

Parameters:
++ ++ ++ ++
core_if Programming view of DWC_otg controller.
ep The EP0 data.
++
++ ++

++DMA Descriptor Setup

++DIEPDMA0 Register write

++Enable the Non-Periodic Tx FIFO empty interrupt, the data will be written into the fifo by the ISR.

++DMA Descriptor Setup

++DOEPDMA0 Register write ++

++Definition at line 2785 of file dwc_otg_cil.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_otg_ep0_continue_transfer (dwc_otg_core_if_t *  core_if,
dwc_ep_t *  ep 
)
++
++
++ ++

++This function continues control IN transfers started by dwc_otg_ep0_start_transfer, when the transfer does not fit in a single packet. ++

++NOTE: The DIEPCTL0/DOEPCTL0 registers only have one bit for the packet count.

++

Parameters:
++ ++ ++ ++
core_if Programming view of DWC_otg controller.
ep The EP0 data.
++
++ ++

++

Todo:
Should there be check for room in the Tx Status Queue. If not remove the code above this comment.
++

++DMA Descriptor Setup

++DIEPDMA0 Register write

++Enable the Non-Periodic Tx FIFO empty interrupt, the data will be written into the fifo by the ISR.

++DMA Descriptor Setup

++DOEPDMA0 Register write ++

++Definition at line 2969 of file dwc_otg_cil.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_otg_ep_write_packet (dwc_otg_core_if_t *  core_if,
dwc_ep_t *  ep,
int  dma 
)
++
++
++ ++

++This function writes a packet into the Tx FIFO associated with the EP. ++

++For non-periodic EPs the non-periodic Tx FIFO is written. For periodic EPs the periodic Tx FIFO associated with the EP is written with all packets for the next micro-frame.

++

Parameters:
++ ++ ++ ++ ++
core_if Programming view of DWC_otg controller.
ep The EP to write packet for.
dma Indicates if DMA is being used.
++
++ ++

++The buffer is padded to DWORD on a per packet basis in slave/dma mode if the MPS is not DWORD aligned. The last packet, if short, is also padded to a multiple of DWORD.

++ep->xfer_buff always starts DWORD aligned in memory and is a multiple of DWORD in length

++ep->xfer_len can be any number of bytes

++ep->xfer_count is a multiple of ep->maxpacket until the last packet

++FIFO access is DWORD

++

Todo:
NGS Where are the Periodic Tx FIFO addresses intialized? What should this be?
++ ++

++Definition at line 3165 of file dwc_otg_cil.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_otg_ep_set_stall (dwc_otg_core_if_t *  core_if,
dwc_ep_t *  ep 
)
++
++
++ ++

++Set the EP STALL. ++

++

Parameters:
++ ++ ++ ++
core_if Programming view of DWC_otg controller.
ep The EP to set the stall on.
++
++ ++

++Definition at line 3236 of file dwc_otg_cil.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_otg_ep_clear_stall (dwc_otg_core_if_t *  core_if,
dwc_ep_t *  ep 
)
++
++
++ ++

++Clear the EP STALL. ++

++

Parameters:
++ ++ ++ ++
core_if Programming view of DWC_otg controller.
ep The EP to clear stall from.
++
++ ++

++Definition at line 3274 of file dwc_otg_cil.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_otg_read_packet (dwc_otg_core_if_t *  core_if,
uint8_t *  dest,
uint16_t  bytes 
)
++
++
++ ++

++This function reads a packet from the Rx FIFO into the destination buffer. ++

++To read SETUP data use dwc_otg_read_setup_packet.

++

Parameters:
++ ++ ++ ++ ++
core_if Programming view of DWC_otg controller.
dest Destination buffer for the packet.
bytes Number of bytes to copy to the destination.
++
++ ++

++

Todo:
Account for the case where _dest is not dword aligned. This requires reading data from the FIFO into a uint32_t temp buffer, then moving it into the data buffer.
++ ++

++Definition at line 3317 of file dwc_otg_cil.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_otg_dump_dev_registers (dwc_otg_core_if_t *  core_if  ) 
++
++
++ ++

++Dump core registers and SPRAM. ++

++

Parameters:
++ ++ ++
core_if Programming view of DWC_otg controller.
++
++ ++

++Definition at line 3347 of file dwc_otg_cil.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_otg_dump_spram (dwc_otg_core_if_t *  core_if  ) 
++
++
++ ++

++This functions reads the SPRAM and prints its content. ++

++

Parameters:
++ ++ ++
core_if Programming view of DWC_otg controller.
++
++ ++

++Definition at line 3477 of file dwc_otg_cil.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_otg_dump_host_registers (dwc_otg_core_if_t *  core_if  ) 
++
++
++ ++

++This function reads the host registers and prints them. ++

++

Parameters:
++ ++ ++
core_if Programming view of DWC_otg controller.
++
++ ++

++Definition at line 3505 of file dwc_otg_cil.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_otg_dump_global_registers (dwc_otg_core_if_t *  core_if  ) 
++
++
++ ++

++This function reads the core global registers and prints them. ++

++

Parameters:
++ ++ ++
core_if Programming view of DWC_otg controller.
++
++ ++

++Definition at line 3573 of file dwc_otg_cil.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_otg_flush_tx_fifo (dwc_otg_core_if_t *  core_if,
const int  num 
)
++
++
++ ++

++Flush a Tx FIFO. ++

++

Parameters:
++ ++ ++ ++
core_if Programming view of DWC_otg controller.
num Tx FIFO to flush.
++
++ ++

++Definition at line 3662 of file dwc_otg_cil.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_otg_flush_rx_fifo (dwc_otg_core_if_t *  core_if  ) 
++
++
++ ++

++Flush Rx FIFO. ++

++

Parameters:
++ ++ ++
core_if Programming view of DWC_otg controller.
++
++ ++

++Definition at line 3694 of file dwc_otg_cil.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_otg_core_reset (dwc_otg_core_if_t *  core_if  ) 
++
++
++ ++

++Do core a soft reset of the core. ++

++Be careful with this because it resets all the internal state machines of the core. ++

++Definition at line 3725 of file dwc_otg_cil.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_otg_cil_register_hcd_callbacks (dwc_otg_core_if_t *  core_if,
dwc_otg_cil_callbacks_t *  cb,
void *  p 
)
++
++
++ ++

++Register HCD callbacks. ++

++The callbacks are used to start and stop the HCD for interrupt processing.

++

Parameters:
++ ++ ++ ++ ++
core_if Programming view of DWC_otg controller.
cb the HCD callback structure.
p pointer to be passed to callback function (usb_hcd*).
++
++ ++

++Definition at line 3781 of file dwc_otg_cil.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_otg_cil_register_pcd_callbacks (dwc_otg_core_if_t *  core_if,
dwc_otg_cil_callbacks_t *  cb,
void *  p 
)
++
++
++ ++

++Register PCD callbacks. ++

++The callbacks are used to start and stop the PCD for interrupt processing.

++

Parameters:
++ ++ ++ ++ ++
core_if Programming view of DWC_otg controller.
cb the PCD callback structure.
p pointer to be passed to callback function (pcd*).
++
++ ++

++Definition at line 3796 of file dwc_otg_cil.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void write_isoc_frame_data (dwc_otg_core_if_t *  core_if,
dwc_ep_t *  ep 
)
++
++
++ ++

++This function writes isoc data per 1 (micro)frame into tx fifo. ++

++

Parameters:
++ ++ ++ ++
core_if Programming view of DWC_otg controller.
ep The EP to start the transfer on.
++
++ ++

++Definition at line 3812 of file dwc_otg_cil.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_otg_iso_ep_start_frm_transfer (dwc_otg_core_if_t *  core_if,
dwc_ep_t *  ep 
)
++
++
++ ++

++This function initializes a descriptor chain for Isochronous transfer. ++

++

Parameters:
++ ++ ++ ++
core_if Programming view of DWC_otg controller.
ep The EP to start the transfer on.
++
++ ++

++Enable endpoint, clear nak ++

++Definition at line 3864 of file dwc_otg_cil.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int dwc_otg_set_param_otg_cap (dwc_otg_core_if_t *  core_if,
int32_t  val 
)
++
++
++ ++

++Specifies the OTG capabilities. ++

++The driver will automatically detect the value for this parameter if none is specified. 0 - HNP and SRP capable (default) 1 - SRP Only capable 2 - No HNP/SRP capable ++

++Definition at line 4056 of file dwc_otg_cil.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int dwc_otg_set_param_dma_enable (dwc_otg_core_if_t *  core_if,
int32_t  val 
)
++
++
++ ++

++Specifies whether to use slave or DMA mode for accessing the data FIFOs. ++

++The driver will automatically detect the value for this parameter if none is specified. 0 - Slave 1 - DMA (default, if available) ++

++Definition at line 4135 of file dwc_otg_cil.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int dwc_otg_set_param_dma_desc_enable (dwc_otg_core_if_t *  core_if,
int32_t  val 
)
++
++
++ ++

++When DMA mode is enabled specifies whether to use address DMA or DMA Descritor mode for accessing the data FIFOs in device mode. ++

++The driver will automatically detect the value for this parameter if none is specified. 0 - address DMA 1 - DMA Descriptor(default, if available) ++

++Definition at line 4165 of file dwc_otg_cil.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int dwc_otg_set_param_host_support_fs_ls_low_power (dwc_otg_core_if_t *  core_if,
int32_t  val 
)
++
++
++ ++

++Specifies whether low power mode is supported when attached to a Full Speed or Low Speed device in host mode. ++

++0 - Don't support low power mode (default) 1 - Support low power mode ++

++Definition at line 4195 of file dwc_otg_cil.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int dwc_otg_set_param_data_fifo_size (dwc_otg_core_if_t *  core_if,
int32_t  val 
)
++
++
++ ++

++Total number of 4-byte words in the data FIFO memory. ++

++This memory includes the Rx FIFO, non-periodic Tx FIFO, and periodic Tx FIFOs. 32 to 32768 (default 8192) Note: The total FIFO memory depth in the FPGA configuration is 8192. ++

++Definition at line 4242 of file dwc_otg_cil.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int dwc_otg_set_param_dev_rx_fifo_size (dwc_otg_core_if_t *  core_if,
int32_t  val 
)
++
++
++ ++

++Number of 4-byte words in the Rx FIFO in device mode when dynamic FIFO sizing is enabled. ++

++16 to 32768 (default 1064) ++

++Definition at line 4271 of file dwc_otg_cil.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int dwc_otg_set_param_dev_nperio_tx_fifo_size (dwc_otg_core_if_t *  core_if,
int32_t  val 
)
++
++
++ ++

++Number of 4-byte words in the non-periodic Tx FIFO in device mode when dynamic FIFO sizing is enabled. ++

++16 to 32768 (default 1024) ++

++Definition at line 4297 of file dwc_otg_cil.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int dwc_otg_set_param_host_rx_fifo_size (dwc_otg_core_if_t *  core_if,
int32_t  val 
)
++
++
++ ++

++Number of 4-byte words in the Rx FIFO in host mode when dynamic FIFO sizing is enabled. ++

++16 to 32768 (default 1024) ++

++Definition at line 4330 of file dwc_otg_cil.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int dwc_otg_set_param_host_nperio_tx_fifo_size (dwc_otg_core_if_t *  core_if,
int32_t  val 
)
++
++
++ ++

++Number of 4-byte words in the non-periodic Tx FIFO in host mode when Dynamic FIFO sizing is enabled in the core. ++

++16 to 32768 (default 1024) ++

++Definition at line 4362 of file dwc_otg_cil.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int dwc_otg_set_param_host_perio_tx_fifo_size (dwc_otg_core_if_t *  core_if,
int32_t  val 
)
++
++
++ ++

++Number of 4-byte words in the host periodic Tx FIFO when dynamic FIFO sizing is enabled. ++

++16 to 32768 (default 1024) ++

++Definition at line 4395 of file dwc_otg_cil.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int dwc_otg_set_param_max_transfer_size (dwc_otg_core_if_t *  core_if,
int32_t  val 
)
++
++
++ ++

++The maximum transfer size supported in bytes. ++

++2047 to 65,535 (default 65,535) ++

++Definition at line 4428 of file dwc_otg_cil.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int dwc_otg_set_param_max_packet_count (dwc_otg_core_if_t *  core_if,
int32_t  val 
)
++
++
++ ++

++The maximum number of packets in a transfer. ++

++15 to 511 (default 511) ++

++Definition at line 4461 of file dwc_otg_cil.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int dwc_otg_set_param_host_channels (dwc_otg_core_if_t *  core_if,
int32_t  val 
)
++
++
++ ++

++The number of host channel registers to use. ++

++1 to 16 (default 12) Note: The FPGA configuration supports a maximum of 12 host channels. ++

++Definition at line 4492 of file dwc_otg_cil.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int dwc_otg_set_param_dev_endpoints (dwc_otg_core_if_t *  core_if,
int32_t  val 
)
++
++
++ ++

++The number of endpoints in addition to EP0 available for device mode operations. ++

++1 to 15 (default 6 IN and OUT) Note: The FPGA configuration supports a maximum of 6 IN and OUT endpoints in addition to EP0. ++

++Definition at line 4522 of file dwc_otg_cil.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int dwc_otg_set_param_phy_type (dwc_otg_core_if_t *  core_if,
int32_t  val 
)
++
++
++ ++

++Specifies the type of PHY interface to use. ++

++By default, the driver will automatically detect the phy_type.

++0 - Full Speed PHY 1 - UTMI+ (default) 2 - ULPI ++

++Definition at line 4552 of file dwc_otg_cil.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int dwc_otg_set_param_speed (dwc_otg_core_if_t *  core_if,
int32_t  val 
)
++
++
++ ++

++Specifies the maximum speed of operation in host and device mode. ++

++The actual speed depends on the speed of the attached device and the value of phy_type. The actual speed depends on the speed of the attached device. 0 - High Speed (default) 1 - Full Speed ++

++Definition at line 4601 of file dwc_otg_cil.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int dwc_otg_set_param_host_ls_low_power_phy_clk (dwc_otg_core_if_t *  core_if,
int32_t  val 
)
++
++
++ ++

++Specifies the PHY clock rate in low power mode when connected to a Low Speed device in host mode. ++

++This parameter is applicable only if HOST_SUPPORT_FS_LS_LOW_POWER is enabled. If PHY_TYPE is set to FS then defaults to 6 MHZ otherwise 48 MHZ.

++0 - 48 MHz 1 - 6 MHz ++

++Definition at line 4630 of file dwc_otg_cil.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int dwc_otg_set_param_phy_ulpi_ddr (dwc_otg_core_if_t *  core_if,
int32_t  val 
)
++
++
++ ++

++Specifies whether the ULPI operates at double or single data rate. ++

++This parameter is only applicable if PHY_TYPE is ULPI.

++0 - single data rate ULPI interface with 8 bit wide data bus (default) 1 - double data rate ULPI interface with 4 bit wide data bus ++

++Definition at line 4665 of file dwc_otg_cil.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int dwc_otg_set_param_phy_utmi_width (dwc_otg_core_if_t *  core_if,
int32_t  val 
)
++
++
++ ++

++Specifies the UTMI+ Data Width. ++

++This parameter is applicable for a PHY_TYPE of UTMI+ or ULPI. (For a ULPI PHY_TYPE, this parameter indicates the data width between the MAC and the ULPI Wrapper.) Also, this parameter is applicable only if the OTG_HSPHY_WIDTH cC parameter was set to "8 and 16 bits", meaning that the core has been configured to work at either data path width.

++8 or 16 bits (default 16) ++

++Definition at line 4700 of file dwc_otg_cil.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int dwc_otg_set_param_i2c_enable (dwc_otg_core_if_t *  core_if,
int32_t  val 
)
++
++
++ ++

++Specifies whether to use the I2Cinterface for full speed PHY. ++

++This parameter is only applicable if PHY_TYPE is FS. 0 - No (default) 1 - Yes ++

++Definition at line 4751 of file dwc_otg_cil.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int dwc_otg_set_param_dev_perio_tx_fifo_size (dwc_otg_core_if_t *  core_if,
int32_t  val,
int  fifo_num 
)
++
++
++ ++

++Number of 4-byte words in each of the periodic Tx FIFOs in device mode when dynamic FIFO sizing is enabled. ++

++4 to 768 (default 256) ++

++Definition at line 4779 of file dwc_otg_cil.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int dwc_otg_set_param_dma_burst_size (dwc_otg_core_if_t *  core_if,
int32_t  val 
)
++
++
++ ++

++The DMA Burst size (applicable only for External DMA Mode). ++

++1, 4, 8 16, 32, 64, 128, 256 (default 32) ++

++Definition at line 4959 of file dwc_otg_cil.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
uint32_t dwc_otg_get_mode (dwc_otg_core_if_t *  core_if  ) 
++
++
++ ++

++Get current mode. ++

++Returns 0 if in device mode, and 1 if in host mode. ++

++Definition at line 5115 of file dwc_otg_cil.c. ++

++

++

Generated on Tue May 5 02:22:48 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__cil_8h-source.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__cil_8h-source.html 2013-07-26 19:31:20.000000000 +0000 +@@ -0,0 +1,709 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_cil.h Source File ++ ++ ++ ++ ++
++
++
++
++

dwc_otg_cil.h

Go to the documentation of this file.
00001 /* ==========================================================================
++00002  * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_cil.h $
++00003  * $Revision: #99 $
++00004  * $Date: 2009/04/21 $
++00005  * $Change: 1237466 $
++00006  *
++00007  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
++00008  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
++00009  * otherwise expressly agreed to in writing between Synopsys and you.
++00010  * 
++00011  * The Software IS NOT an item of Licensed Software or Licensed Product under
++00012  * any End User Software License Agreement or Agreement for Licensed Product
++00013  * with Synopsys or any supplement thereto. You are permitted to use and
++00014  * redistribute this Software in source and binary forms, with or without
++00015  * modification, provided that redistributions of source code must retain this
++00016  * notice. You may not view, use, disclose, copy or distribute this file or
++00017  * any information contained herein except pursuant to this license grant from
++00018  * Synopsys. If you do not agree with this notice, including the disclaimer
++00019  * below, then you are not authorized to use the Software.
++00020  * 
++00021  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
++00022  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++00023  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++00024  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
++00025  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++00026  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
++00027  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
++00028  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
++00029  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
++00030  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
++00031  * DAMAGE.
++00032  * ========================================================================== */
++00033 
++00034 #if !defined(__DWC_CIL_H__)
++00035 #define __DWC_CIL_H__
++00036 
++00037 #include "dwc_os.h"
++00038 #include "dwc_list.h"
++00039 #include "dwc_otg_dbg.h"
++00040 #include "dwc_otg_regs.h"
++00041 
++00042 #include "dwc_otg_core_if.h"
++00043 
++00049 #ifdef DWC_UTE_CFI
++00050 
++00051 #define MAX_DMA_DESCS_PER_EP    256
++00052 
++00056 typedef enum _data_buffer_mode {
++00057         BM_STANDARD = 0,        /* data buffer is in normal mode */
++00058         BM_SG = 1,              /* data buffer uses the scatter/gather mode */
++00059         BM_CONCAT = 2,          /* data buffer uses the concatenation mode */
++00060         BM_CIRCULAR = 3,        /* data buffer uses the circular DMA mode */
++00061         BM_ALIGN = 4            /* data buffer is in buffer alignment mode */
++00062 } data_buffer_mode_e;
++00063 #endif                          //DWC_UTE_CFI
++00064 
++00067 #define OTG_CORE_REV_2_60a      0x4F54260A
++00068 #define OTG_CORE_REV_2_71a      0x4F54271A
++00069 #define OTG_CORE_REV_2_72a      0x4F54272A
++00070 #define OTG_CORE_REV_2_80a      0x4F54280A
++00071 #define OTG_CORE_REV_2_81a      0x4F54281A
++00072 #define OTG_CORE_REV_2_90a      0x4F54290A              
++00073 
++00077 typedef struct iso_pkt_info {
++00078         uint32_t offset;
++00079         uint32_t length;
++00080         int32_t status;
++00081 } iso_pkt_info_t;
++00082 
++00088 typedef struct dwc_ep {
++00090         uint8_t num;
++00092         unsigned is_in:1;
++00094         unsigned active:1;
++00095 
++00098         unsigned tx_fifo_num:4;
++00100         unsigned type:2;
++00101 #define DWC_OTG_EP_TYPE_CONTROL    0
++00102 #define DWC_OTG_EP_TYPE_ISOC       1
++00103 #define DWC_OTG_EP_TYPE_BULK       2
++00104 #define DWC_OTG_EP_TYPE_INTR       3
++00105 
++00107         unsigned data_pid_start:1;
++00109         unsigned even_odd_frame:1;
++00111         unsigned maxpacket:11;
++00112 
++00114         uint32_t maxxfer;
++00115 
++00124         dwc_dma_t dma_addr;
++00125 
++00126         dwc_dma_t dma_desc_addr;
++00127         dwc_otg_dev_dma_desc_t *desc_addr;
++00128 
++00129         uint8_t *start_xfer_buff;
++00131         uint8_t *xfer_buff;
++00133         unsigned xfer_len:19;
++00135         unsigned xfer_count:19;
++00137         unsigned sent_zlp:1;
++00139         unsigned total_len:19;
++00140 
++00142         unsigned stall_clear_flag:1;
++00143 
++00144 #ifdef DWC_UTE_CFI
++00145         /* The buffer mode */
++00146         data_buffer_mode_e buff_mode;
++00147 
++00148         /* The chain of DMA descriptors.
++00149          * MAX_DMA_DESCS_PER_EP will be allocated for each active EP.
++00150          */
++00151         dwc_otg_dma_desc_t *descs;
++00152 
++00153         /* The DMA address of the descriptors chain start */
++00154         dma_addr_t descs_dma_addr;
++00156         uint32_t cfi_req_len;
++00157 #endif                          //DWC_UTE_CFI
++00158 
++00160         uint32_t desc_cnt;
++00161 
++00162 #ifdef DWC_EN_ISOC
++00163 
++00168         dwc_dma_t dma_addr0;
++00169         dwc_dma_t dma_addr1;
++00170 
++00171         dwc_dma_t iso_dma_desc_addr;
++00172         dwc_otg_dev_dma_desc_t *iso_desc_addr;
++00173 
++00175         uint8_t *xfer_buff0;
++00176         uint8_t *xfer_buff1;
++00177 
++00179         uint32_t proc_buf_num;
++00181         uint32_t buf_proc_intrvl;
++00183         uint32_t data_per_frame;
++00184 
++00185         /* todo - pattern data support is to be implemented in the future */
++00187         uint32_t data_pattern_frame;
++00189         uint32_t sync_frame;
++00190 
++00192         uint32_t bInterval;
++00194         uint32_t pkt_per_frm;
++00196         uint32_t next_frame;
++00198         uint32_t pkt_cnt;
++00200         iso_pkt_info_t *pkt_info;
++00202         uint32_t cur_pkt;
++00204         uint8_t *cur_pkt_addr;
++00206         uint32_t cur_pkt_dma_addr;
++00207 #endif                          /* DWC_EN_ISOC */
++00208 
++00210 } dwc_ep_t;
++00211 
++00212 /*
++00213  * Reasons for halting a host channel.
++00214  */
++00215 typedef enum dwc_otg_halt_status {
++00216         DWC_OTG_HC_XFER_NO_HALT_STATUS,
++00217         DWC_OTG_HC_XFER_COMPLETE,
++00218         DWC_OTG_HC_XFER_URB_COMPLETE,
++00219         DWC_OTG_HC_XFER_ACK,
++00220         DWC_OTG_HC_XFER_NAK,
++00221         DWC_OTG_HC_XFER_NYET,
++00222         DWC_OTG_HC_XFER_STALL,
++00223         DWC_OTG_HC_XFER_XACT_ERR,
++00224         DWC_OTG_HC_XFER_FRAME_OVERRUN,
++00225         DWC_OTG_HC_XFER_BABBLE_ERR,
++00226         DWC_OTG_HC_XFER_DATA_TOGGLE_ERR,
++00227         DWC_OTG_HC_XFER_AHB_ERR,
++00228         DWC_OTG_HC_XFER_PERIODIC_INCOMPLETE,
++00229         DWC_OTG_HC_XFER_URB_DEQUEUE
++00230 } dwc_otg_halt_status_e;
++00231 
++00237 typedef struct dwc_hc {
++00239         uint8_t hc_num;
++00240 
++00242         unsigned dev_addr:7;
++00243 
++00245         unsigned ep_num:4;
++00246 
++00248         unsigned ep_is_in:1;
++00249 
++00257         unsigned speed:2;
++00258 #define DWC_OTG_EP_SPEED_LOW    0
++00259 #define DWC_OTG_EP_SPEED_FULL   1
++00260 #define DWC_OTG_EP_SPEED_HIGH   2
++00261 
++00270         unsigned ep_type:2;
++00271 
++00273         unsigned max_packet:11;
++00274 
++00283         unsigned data_pid_start:2;
++00284 #define DWC_OTG_HC_PID_DATA0 0
++00285 #define DWC_OTG_HC_PID_DATA2 1
++00286 #define DWC_OTG_HC_PID_DATA1 2
++00287 #define DWC_OTG_HC_PID_MDATA 3
++00288 #define DWC_OTG_HC_PID_SETUP 3
++00289 
++00291         unsigned multi_count:2;
++00292 
++00297         uint8_t *xfer_buff;
++00302         dwc_dma_t align_buff;
++00304         uint32_t xfer_len;
++00306         uint32_t xfer_count;
++00308         uint16_t start_pkt_count;
++00309 
++00314         uint8_t xfer_started;
++00315 
++00320         uint8_t do_ping;
++00321 
++00326         uint8_t error_state;
++00327 
++00334         uint8_t halt_on_queue;
++00335 
++00340         uint8_t halt_pending;
++00341 
++00345         dwc_otg_halt_status_e halt_status;
++00346 
++00347         /*
++00348          * Split settings for the host channel
++00349          */
++00350         uint8_t do_split;                  
++00351         uint8_t complete_split;    
++00352         uint8_t hub_addr;                  
++00354         uint8_t port_addr;                 
++00361         uint8_t xact_pos;
++00362 
++00364         uint8_t short_read;
++00365 
++00370         uint8_t requests;
++00371 
++00375         struct dwc_otg_qh *qh;
++00376 
++00380          DWC_CIRCLEQ_ENTRY(dwc_hc) hc_list_entry;
++00381         
++00386         uint16_t ntd;
++00387         
++00389         dwc_dma_t desc_list_addr;
++00390         
++00392         uint8_t schinfo;
++00393         
++00395 } dwc_hc_t;
++00396 
++00401 typedef struct dwc_otg_core_params {
++00402         int32_t opt;
++00403 
++00411         int32_t otg_cap;
++00412 
++00420         int32_t dma_enable;
++00421 
++00429         int32_t dma_desc_enable;
++00433         int32_t dma_burst_size; /* Translate this to GAHBCFG values */
++00434 
++00443         int32_t speed;
++00449         int32_t host_support_fs_ls_low_power;
++00450 
++00459         int32_t host_ls_low_power_phy_clk;
++00460 
++00465         int32_t enable_dynamic_fifo;
++00466 
++00473         int32_t data_fifo_size;
++00474 
++00479         int32_t dev_rx_fifo_size;
++00480 
++00485         int32_t dev_nperio_tx_fifo_size;
++00486 
++00491         uint32_t dev_perio_tx_fifo_size[MAX_PERIO_FIFOS];
++00492 
++00497         int32_t host_rx_fifo_size;
++00498 
++00503         int32_t host_nperio_tx_fifo_size;
++00504 
++00509         int32_t host_perio_tx_fifo_size;
++00510 
++00514         int32_t max_transfer_size;
++00515 
++00519         int32_t max_packet_count;
++00520 
++00525         int32_t host_channels;
++00526 
++00533         int32_t dev_endpoints;
++00534 
++00543         int32_t phy_type;
++00544 
++00556         int32_t phy_utmi_width;
++00557 
++00568         int32_t phy_ulpi_ddr;
++00569 
++00574         int32_t phy_ulpi_ext_vbus;
++00575 
++00582         int32_t i2c_enable;
++00583 
++00584         int32_t ulpi_fs_ls;
++00585 
++00586         int32_t ts_dline;
++00587 
++00594         int32_t en_multiple_tx_fifo;
++00595 
++00600         uint32_t dev_tx_fifo_size[MAX_TX_FIFOS];
++00601 
++00607         uint32_t thr_ctl;
++00608 
++00612         uint32_t tx_thr_length;
++00613 
++00617         uint32_t rx_thr_length;
++00618 
++00622         int32_t lpm_enable;
++00623 
++00629         int32_t pti_enable;
++00630 
++00636         int32_t mpi_enable;
++00637 
++00642         int32_t ic_usb_cap;
++00643 
++00650         int32_t ahb_thr_ratio;
++00651 
++00652 } dwc_otg_core_params_t;
++00653 
++00654 #ifdef DEBUG
++00655 struct dwc_otg_core_if;
++00656 typedef struct hc_xfer_info {
++00657         struct dwc_otg_core_if *core_if;
++00658         dwc_hc_t *hc;
++00659 } hc_xfer_info_t;
++00660 #endif
++00661 /*
++00662  * Device States
++00663  */
++00664 typedef enum dwc_otg_lx_state {
++00666         DWC_OTG_L0,
++00668         DWC_OTG_L1,
++00670         DWC_OTG_L2,
++00672         DWC_OTG_L3
++00673 } dwc_otg_lx_state_e;
++00674 
++00680 struct dwc_otg_core_if {
++00682         dwc_otg_core_params_t *core_params;
++00683 
++00685         dwc_otg_core_global_regs_t *core_global_regs;
++00686 
++00688         dwc_otg_dev_if_t *dev_if;
++00690         dwc_otg_host_if_t *host_if;
++00691 
++00693         uint32_t snpsid;
++00694 
++00695         /*
++00696          * Set to 1 if the core PHY interface bits in USBCFG have been
++00697          * initialized.
++00698          */
++00699         uint8_t phy_init_done;
++00700 
++00701         /*
++00702          * SRP Success flag, set by srp success interrupt in FS I2C mode
++00703          */
++00704         uint8_t srp_success;
++00705         uint8_t srp_timer_started;
++00706 
++00707         /* Common configuration information */
++00709         volatile uint32_t *pcgcctl;
++00710 #define DWC_OTG_PCGCCTL_OFFSET 0xE00
++00711 
++00713         uint32_t *data_fifo[MAX_EPS_CHANNELS];
++00714 #define DWC_OTG_DATA_FIFO_OFFSET 0x1000
++00715 #define DWC_OTG_DATA_FIFO_SIZE 0x1000
++00716 
++00718         uint16_t total_fifo_size;
++00720         uint16_t rx_fifo_size;
++00722         uint16_t nperio_tx_fifo_size;
++00723 
++00725         uint8_t dma_enable;
++00726 
++00728         uint8_t dma_desc_enable;
++00729 
++00731         uint8_t pti_enh_enable;
++00732 
++00734         uint8_t multiproc_int_enable;
++00735 
++00737         uint8_t en_multiple_tx_fifo;
++00738 
++00741         uint8_t queuing_high_bandwidth;
++00742 
++00744         hwcfg1_data_t hwcfg1;
++00745         hwcfg2_data_t hwcfg2;
++00746         hwcfg3_data_t hwcfg3;
++00747         hwcfg4_data_t hwcfg4;
++00748 
++00750         hcfg_data_t hcfg;
++00751         dcfg_data_t dcfg;
++00752 
++00758         uint8_t op_state;
++00759 
++00765         uint8_t restart_hcd_on_session_req;
++00766 
++00769 #define A_HOST          (1)
++00770 
++00771 #define A_SUSPEND       (2)
++00772 
++00773 #define A_PERIPHERAL    (3)
++00774 
++00775 #define B_PERIPHERAL    (4)
++00776 
++00777 #define B_HOST          (5)
++00778 
++00780         struct dwc_otg_cil_callbacks *hcd_cb;
++00782         struct dwc_otg_cil_callbacks *pcd_cb;
++00783 
++00785         uint32_t p_tx_msk;
++00787         uint32_t tx_msk;
++00788 
++00790         dwc_workq_t *wq_otg;
++00791 
++00793         dwc_timer_t *wkp_timer;
++00794 
++00795 #ifdef DEBUG
++00796         uint32_t start_hcchar_val[MAX_EPS_CHANNELS];
++00797 
++00798         hc_xfer_info_t hc_xfer_info[MAX_EPS_CHANNELS];
++00799         dwc_timer_t *hc_xfer_timer[MAX_EPS_CHANNELS];
++00800 
++00801         uint32_t hfnum_7_samples;
++00802         uint64_t hfnum_7_frrem_accum;
++00803         uint32_t hfnum_0_samples;
++00804         uint64_t hfnum_0_frrem_accum;
++00805         uint32_t hfnum_other_samples;
++00806         uint64_t hfnum_other_frrem_accum;
++00807 #endif
++00808 
++00809 #ifdef DWC_UTE_CFI
++00810         uint16_t pwron_rxfsiz;
++00811         uint16_t pwron_gnptxfsiz;
++00812         uint16_t pwron_txfsiz[15];
++00813 
++00814         uint16_t init_rxfsiz;
++00815         uint16_t init_gnptxfsiz;
++00816         uint16_t init_txfsiz[15];
++00817 #endif
++00818 
++00820         dwc_otg_lx_state_e lx_state;
++00821 
++00822 };
++00823 
++00824 #ifdef DEBUG
++00825 /*
++00826  * This function is called when transfer is timed out.
++00827  */
++00828 extern void hc_xfer_timeout(void *ptr);
++00829 #endif
++00830 
++00831 /*
++00832  * The following functions are functions for works 
++00833  * using during handling some interrupts
++00834  */
++00835 extern void w_conn_id_status_change(void *p);
++00836 
++00837 extern void w_wakeup_detected(void *p);
++00838 
++00839 /*
++00840  * The following functions support initialization of the CIL driver component
++00841  * and the DWC_otg controller.
++00842  */
++00843 extern void dwc_otg_core_host_init(dwc_otg_core_if_t * _core_if);
++00844 extern void dwc_otg_core_dev_init(dwc_otg_core_if_t * _core_if);
++00845 
++00851 extern void dwc_otg_wakeup(dwc_otg_core_if_t * _core_if);
++00852 extern void dwc_otg_read_setup_packet(dwc_otg_core_if_t * _core_if,
++00853                                       uint32_t * _dest);
++00854 extern uint32_t dwc_otg_get_frame_number(dwc_otg_core_if_t * _core_if);
++00855 extern void dwc_otg_ep0_activate(dwc_otg_core_if_t * _core_if, dwc_ep_t * _ep);
++00856 extern void dwc_otg_ep_activate(dwc_otg_core_if_t * _core_if, dwc_ep_t * _ep);
++00857 extern void dwc_otg_ep_deactivate(dwc_otg_core_if_t * _core_if, dwc_ep_t * _ep);
++00858 extern void dwc_otg_ep_start_transfer(dwc_otg_core_if_t * _core_if,
++00859                                       dwc_ep_t * _ep);
++00860 extern void dwc_otg_ep_start_zl_transfer(dwc_otg_core_if_t * _core_if,
++00861                                          dwc_ep_t * _ep);
++00862 extern void dwc_otg_ep0_start_transfer(dwc_otg_core_if_t * _core_if,
++00863                                        dwc_ep_t * _ep);
++00864 extern void dwc_otg_ep0_continue_transfer(dwc_otg_core_if_t * _core_if,
++00865                                           dwc_ep_t * _ep);
++00866 extern void dwc_otg_ep_write_packet(dwc_otg_core_if_t * _core_if,
++00867                                     dwc_ep_t * _ep, int _dma);
++00868 extern void dwc_otg_ep_set_stall(dwc_otg_core_if_t * _core_if, dwc_ep_t * _ep);
++00869 extern void dwc_otg_ep_clear_stall(dwc_otg_core_if_t * _core_if,
++00870                                    dwc_ep_t * _ep);
++00871 extern void dwc_otg_enable_device_interrupts(dwc_otg_core_if_t * _core_if);
++00872 
++00873 #ifdef DWC_EN_ISOC
++00874 extern void dwc_otg_iso_ep_start_frm_transfer(dwc_otg_core_if_t * core_if,
++00875                                               dwc_ep_t * ep);
++00876 extern void dwc_otg_iso_ep_start_buf_transfer(dwc_otg_core_if_t * core_if,
++00877                                               dwc_ep_t * ep);
++00878 #endif                          /* DWC_EN_ISOC */
++00879 
++00886 extern void dwc_otg_hc_init(dwc_otg_core_if_t * _core_if, dwc_hc_t * _hc);
++00887 extern void dwc_otg_hc_halt(dwc_otg_core_if_t * _core_if,
++00888                             dwc_hc_t * _hc, dwc_otg_halt_status_e _halt_status);
++00889 extern void dwc_otg_hc_cleanup(dwc_otg_core_if_t * _core_if, dwc_hc_t * _hc);
++00890 extern void dwc_otg_hc_start_transfer(dwc_otg_core_if_t * _core_if,
++00891                                       dwc_hc_t * _hc);
++00892 extern int dwc_otg_hc_continue_transfer(dwc_otg_core_if_t * _core_if,
++00893                                         dwc_hc_t * _hc);
++00894 extern void dwc_otg_hc_do_ping(dwc_otg_core_if_t * _core_if, dwc_hc_t * _hc);
++00895 extern void dwc_otg_hc_write_packet(dwc_otg_core_if_t * _core_if,
++00896                                     dwc_hc_t * _hc);
++00897 extern void dwc_otg_enable_host_interrupts(dwc_otg_core_if_t * _core_if);
++00898 extern void dwc_otg_disable_host_interrupts(dwc_otg_core_if_t * _core_if);
++00899 
++00900 extern void dwc_otg_hc_start_transfer_ddma(dwc_otg_core_if_t * core_if, dwc_hc_t * hc);
++00901 
++00902 /* Macro used to clear one channel interrupt */
++00903 #define clear_hc_int(_hc_regs_, _intr_) \
++00904 do { \
++00905         hcint_data_t hcint_clear = {.d32 = 0}; \
++00906         hcint_clear.b._intr_ = 1; \
++00907         dwc_write_reg32(&(_hc_regs_)->hcint, hcint_clear.d32); \
++00908 } while (0)
++00909 
++00910 /*
++00911  * Macro used to disable one channel interrupt. Channel interrupts are
++00912  * disabled when the channel is halted or released by the interrupt handler.
++00913  * There is no need to handle further interrupts of that type until the
++00914  * channel is re-assigned. In fact, subsequent handling may cause crashes
++00915  * because the channel structures are cleaned up when the channel is released.
++00916  */
++00917 #define disable_hc_int(_hc_regs_, _intr_) \
++00918 do { \
++00919         hcintmsk_data_t hcintmsk = {.d32 = 0}; \
++00920         hcintmsk.b._intr_ = 1; \
++00921         dwc_modify_reg32(&(_hc_regs_)->hcintmsk, hcintmsk.d32, 0); \
++00922 } while (0)
++00923                 
++00929 static inline uint32_t dwc_otg_read_hprt0(dwc_otg_core_if_t * _core_if)
++00930 {
++00931         hprt0_data_t hprt0;
++00932         hprt0.d32 = dwc_read_reg32(_core_if->host_if->hprt0);
++00933         hprt0.b.prtena = 0;
++00934         hprt0.b.prtconndet = 0;
++00935         hprt0.b.prtenchng = 0;
++00936         hprt0.b.prtovrcurrchng = 0;
++00937         return hprt0.d32;
++00938 }
++00939 
++00948 extern void dwc_otg_read_packet(dwc_otg_core_if_t * core_if,
++00949                                 uint8_t * dest, uint16_t bytes);
++00950 
++00951 extern void dwc_otg_flush_tx_fifo(dwc_otg_core_if_t * _core_if, const int _num);
++00952 extern void dwc_otg_flush_rx_fifo(dwc_otg_core_if_t * _core_if);
++00953 extern void dwc_otg_core_reset(dwc_otg_core_if_t * _core_if);
++00954 
++00958 static inline uint32_t dwc_otg_read_core_intr(dwc_otg_core_if_t * core_if)
++00959 {
++00960         return (dwc_read_reg32(&core_if->core_global_regs->gintsts) &
++00961                 dwc_read_reg32(&core_if->core_global_regs->gintmsk));
++00962 }
++00963 
++00967 static inline uint32_t dwc_otg_read_otg_intr(dwc_otg_core_if_t * core_if)
++00968 {
++00969         return (dwc_read_reg32(&core_if->core_global_regs->gotgint));
++00970 }
++00971 
++00976 static inline uint32_t dwc_otg_read_dev_all_in_ep_intr(dwc_otg_core_if_t *
++00977                                                        core_if)
++00978 {
++00979 
++00980         uint32_t v;
++00981 
++00982         if (core_if->multiproc_int_enable) {
++00983                 v = dwc_read_reg32(&core_if->dev_if->dev_global_regs->
++00984                                    deachint) & dwc_read_reg32(&core_if->dev_if->
++00985                                                               dev_global_regs->
++00986                                                               deachintmsk);
++00987         } else {
++00988                 v = dwc_read_reg32(&core_if->dev_if->dev_global_regs->daint) &
++00989                     dwc_read_reg32(&core_if->dev_if->dev_global_regs->daintmsk);
++00990         }
++00991         return (v & 0xffff);
++00992 }
++00993 
++00998 static inline uint32_t dwc_otg_read_dev_all_out_ep_intr(dwc_otg_core_if_t *
++00999                                                         core_if)
++01000 {
++01001         uint32_t v;
++01002 
++01003         if (core_if->multiproc_int_enable) {
++01004                 v = dwc_read_reg32(&core_if->dev_if->dev_global_regs->
++01005                                    deachint) & dwc_read_reg32(&core_if->dev_if->
++01006                                                               dev_global_regs->
++01007                                                               deachintmsk);
++01008         } else {
++01009                 v = dwc_read_reg32(&core_if->dev_if->dev_global_regs->daint) &
++01010                     dwc_read_reg32(&core_if->dev_if->dev_global_regs->daintmsk);
++01011         }
++01012 
++01013         return ((v & 0xffff0000) >> 16);
++01014 }
++01015 
++01019 static inline uint32_t dwc_otg_read_dev_in_ep_intr(dwc_otg_core_if_t * core_if,
++01020                                                    dwc_ep_t * ep)
++01021 {
++01022         dwc_otg_dev_if_t *dev_if = core_if->dev_if;
++01023         uint32_t v, msk, emp;
++01024 
++01025         if (core_if->multiproc_int_enable) {
++01026                 msk =
++01027                     dwc_read_reg32(&dev_if->dev_global_regs->
++01028                                    diepeachintmsk[ep->num]);
++01029                 emp =
++01030                     dwc_read_reg32(&dev_if->dev_global_regs->
++01031                                    dtknqr4_fifoemptymsk);
++01032                 msk |= ((emp >> ep->num) & 0x1) << 7;
++01033                 v = dwc_read_reg32(&dev_if->in_ep_regs[ep->num]->diepint) & msk;
++01034         } else {
++01035                 msk = dwc_read_reg32(&dev_if->dev_global_regs->diepmsk);
++01036                 emp =
++01037                     dwc_read_reg32(&dev_if->dev_global_regs->
++01038                                    dtknqr4_fifoemptymsk);
++01039                 msk |= ((emp >> ep->num) & 0x1) << 7;
++01040                 v = dwc_read_reg32(&dev_if->in_ep_regs[ep->num]->diepint) & msk;
++01041         }
++01042 
++01043         return v;
++01044 }
++01045 
++01049 static inline uint32_t dwc_otg_read_dev_out_ep_intr(dwc_otg_core_if_t *
++01050                                                     _core_if, dwc_ep_t * _ep)
++01051 {
++01052         dwc_otg_dev_if_t *dev_if = _core_if->dev_if;
++01053         uint32_t v;
++01054         doepmsk_data_t msk = {.d32 = 0 };
++01055 
++01056         if (_core_if->multiproc_int_enable) {
++01057                 msk.d32 =
++01058                     dwc_read_reg32(&dev_if->dev_global_regs->
++01059                                    doepeachintmsk[_ep->num]);
++01060                 if (_core_if->pti_enh_enable) {
++01061                         msk.b.pktdrpsts = 1;
++01062                 }
++01063                 v = dwc_read_reg32(&dev_if->out_ep_regs[_ep->num]->
++01064                                    doepint) & msk.d32;
++01065         } else {
++01066                 msk.d32 = dwc_read_reg32(&dev_if->dev_global_regs->doepmsk);
++01067                 if (_core_if->pti_enh_enable) {
++01068                         msk.b.pktdrpsts = 1;
++01069                 }
++01070                 v = dwc_read_reg32(&dev_if->out_ep_regs[_ep->num]->
++01071                                    doepint) & msk.d32;
++01072         }
++01073         return v;
++01074 }
++01075 
++01079 static inline uint32_t dwc_otg_read_host_all_channels_intr(dwc_otg_core_if_t *
++01080                                                            _core_if)
++01081 {
++01082         return (dwc_read_reg32(&_core_if->host_if->host_global_regs->haint));
++01083 }
++01084 
++01085 static inline uint32_t dwc_otg_read_host_channel_intr(dwc_otg_core_if_t *
++01086                                                       _core_if, dwc_hc_t * _hc)
++01087 {
++01088         return (dwc_read_reg32
++01089                 (&_core_if->host_if->hc_regs[_hc->hc_num]->hcint));
++01090 }
++01091 
++01097 static inline uint32_t dwc_otg_mode(dwc_otg_core_if_t * _core_if)
++01098 {
++01099         return (dwc_read_reg32(&_core_if->core_global_regs->gintsts) & 0x1);
++01100 }
++01101 
++01109 typedef struct dwc_otg_cil_callbacks {
++01111         int (*start) (void *_p);
++01113         int (*stop) (void *_p);
++01115         int (*disconnect) (void *_p);
++01117         int (*resume_wakeup) (void *_p);
++01119         int (*suspend) (void *_p);
++01121         int (*session_start) (void *_p);
++01122 #ifdef CONFIG_USB_DWC_OTG_LPM
++01123 
++01124         int (*sleep) (void *_p);
++01125 #endif
++01126 
++01127         void *p;
++01128 } dwc_otg_cil_callbacks_t;
++01129 
++01130 extern void dwc_otg_cil_register_pcd_callbacks(dwc_otg_core_if_t * _core_if,
++01131                                                dwc_otg_cil_callbacks_t * _cb,
++01132                                                void *_p);
++01133 extern void dwc_otg_cil_register_hcd_callbacks(dwc_otg_core_if_t * _core_if,
++01134                                                dwc_otg_cil_callbacks_t * _cb,
++01135                                                void *_p);
++01136 
++01137 #endif
++
Generated on Tue May 5 02:22:48 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__cil_8h.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__cil_8h.html 2013-07-26 19:31:20.000000000 +0000 +@@ -0,0 +1,1844 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_cil.h File Reference ++ ++ ++ ++ ++
++
++
++
++

dwc_otg_cil.h File Reference

This file contains the interface to the Core Interface Layer. More... ++

++#include "dwc_os.h"
++#include "dwc_list.h"
++#include "dwc_otg_dbg.h"
++#include "dwc_otg_regs.h"
++#include "dwc_otg_core_if.h"
++ ++

++Go to the source code of this file. ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++

Data Structures

struct  iso_pkt_info
 Information for each ISOC packet. More...
struct  dwc_ep
 The dwc_ep structure represents the state of a single endpoint when acting in device mode. More...
struct  dwc_hc
 Host channel descriptor. More...
struct  dwc_otg_core_params
 The following parameters may be specified when starting the module. More...
struct  dwc_otg_core_if
 The dwc_otg_core_if structure contains information needed to manage the DWC_otg controller acting in either host or device mode. More...
struct  dwc_otg_cil_callbacks
 DWC_otg CIL callback structure. More...

Host CIL Functions

The following functions support managing the DWC_otg controller in host mode.

#define clear_hc_int(_hc_regs_, _intr_)
#define disable_hc_int(_hc_regs_, _intr_)
void dwc_otg_hc_init (dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc)
 Prepares a host channel for transferring packets to/from a specific endpoint.
void dwc_otg_hc_halt (dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc, dwc_otg_halt_status_e _halt_status)
 Attempts to halt a host channel.
void dwc_otg_hc_cleanup (dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc)
 Clears the transfer state for a host channel.
void dwc_otg_hc_start_transfer (dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc)
 This function does the setup for a data transfer for a host channel and starts the transfer.
int dwc_otg_hc_continue_transfer (dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc)
 This function continues a data transfer that was started by previous call to dwc_otg_hc_start_transfer.
void dwc_otg_hc_do_ping (dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc)
 Starts a PING transfer.
++void dwc_otg_hc_write_packet (dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc)
void dwc_otg_enable_host_interrupts (dwc_otg_core_if_t *_core_if)
 This function enables the Host mode interrupts.
void dwc_otg_disable_host_interrupts (dwc_otg_core_if_t *_core_if)
 This function disables the Host Mode interrupts.
void dwc_otg_hc_start_transfer_ddma (dwc_otg_core_if_t *core_if, dwc_hc_t *hc)
 This function does the setup for a data transfer for a host channel and starts the transfer in Descriptor DMA mode.
static uint32_t dwc_otg_read_hprt0 (dwc_otg_core_if_t *_core_if)
 This function Reads HPRT0 in preparation to modify.

Device CIL Functions

The following functions support managing the DWC_otg controller in device mode.

++void dwc_otg_wakeup (dwc_otg_core_if_t *_core_if)
void dwc_otg_read_setup_packet (dwc_otg_core_if_t *_core_if, uint32_t *_dest)
 This function reads a setup packet from the Rx FIFO into the destination buffer.
uint32_t dwc_otg_get_frame_number (dwc_otg_core_if_t *_core_if)
 Gets the current USB frame number.
void dwc_otg_ep0_activate (dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep)
 This function enables EP0 OUT to receive SETUP packets and configures EP0 IN for transmitting packets.
void dwc_otg_ep_activate (dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep)
 This function activates an EP.
void dwc_otg_ep_deactivate (dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep)
 This function deactivates an EP.
void dwc_otg_ep_start_transfer (dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep)
 This function does the setup for a data transfer for an EP and starts the transfer.
void dwc_otg_ep_start_zl_transfer (dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep)
 This function setup a zero length transfer in Buffer DMA and Slave modes for usb requests with zero field set.
void dwc_otg_ep0_start_transfer (dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep)
 This function does the setup for a data transfer for EP0 and starts the transfer.
void dwc_otg_ep0_continue_transfer (dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep)
 This function continues control IN transfers started by dwc_otg_ep0_start_transfer, when the transfer does not fit in a single packet.
void dwc_otg_ep_write_packet (dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep, int _dma)
 This function writes a packet into the Tx FIFO associated with the EP.
void dwc_otg_ep_set_stall (dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep)
 Set the EP STALL.
void dwc_otg_ep_clear_stall (dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep)
 Clear the EP STALL.
void dwc_otg_enable_device_interrupts (dwc_otg_core_if_t *_core_if)
 This function enables the Device mode interrupts.
void dwc_otg_iso_ep_start_frm_transfer (dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
 This function initializes a descriptor chain for Isochronous transfer.
void dwc_otg_iso_ep_start_buf_transfer (dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
 This function initializes a descriptor chain for Isochronous transfer.

Common CIL Functions

The following functions support managing the DWC_otg controller in either device or host mode.

void dwc_otg_read_packet (dwc_otg_core_if_t *core_if, uint8_t *dest, uint16_t bytes)
 This function reads a packet from the Rx FIFO into the destination buffer.
void dwc_otg_flush_tx_fifo (dwc_otg_core_if_t *_core_if, const int _num)
 Flush a Tx FIFO.
void dwc_otg_flush_rx_fifo (dwc_otg_core_if_t *_core_if)
 Flush Rx FIFO.
void dwc_otg_core_reset (dwc_otg_core_if_t *_core_if)
 Do core a soft reset of the core.
++static uint32_t dwc_otg_read_core_intr (dwc_otg_core_if_t *core_if)
 This function returns the Core Interrupt register.
++static uint32_t dwc_otg_read_otg_intr (dwc_otg_core_if_t *core_if)
 This function returns the OTG Interrupt register.
++static uint32_t dwc_otg_read_dev_all_in_ep_intr (dwc_otg_core_if_t *core_if)
 This function reads the Device All Endpoints Interrupt register and returns the IN endpoint interrupt bits.
++static uint32_t dwc_otg_read_dev_all_out_ep_intr (dwc_otg_core_if_t *core_if)
 This function reads the Device All Endpoints Interrupt register and returns the OUT endpoint interrupt bits.
++static uint32_t dwc_otg_read_dev_in_ep_intr (dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
 This function returns the Device IN EP Interrupt register.
++static uint32_t dwc_otg_read_dev_out_ep_intr (dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep)
 This function returns the Device OUT EP Interrupt register.
++static uint32_t dwc_otg_read_host_all_channels_intr (dwc_otg_core_if_t *_core_if)
 This function returns the Host All Channel Interrupt register.
++static uint32_t dwc_otg_read_host_channel_intr (dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc)
static uint32_t dwc_otg_mode (dwc_otg_core_if_t *_core_if)
 This function returns the mode of the operation, host or device.

Defines

++#define __DWC_CIL_H__
++#define OTG_CORE_REV_2_60a   0x4F54260A
 Macros defined for DWC OTG HW Release verison.
++#define OTG_CORE_REV_2_71a   0x4F54271A
++#define OTG_CORE_REV_2_72a   0x4F54272A
++#define OTG_CORE_REV_2_80a   0x4F54280A
++#define OTG_CORE_REV_2_81a   0x4F54281A
++#define OTG_CORE_REV_2_90a   0x4F54290A
++#define DWC_OTG_EP_TYPE_CONTROL   0
++#define DWC_OTG_EP_TYPE_ISOC   1
++#define DWC_OTG_EP_TYPE_BULK   2
++#define DWC_OTG_EP_TYPE_INTR   3
++#define DWC_OTG_EP_SPEED_LOW   0
++#define DWC_OTG_EP_SPEED_FULL   1
++#define DWC_OTG_EP_SPEED_HIGH   2
++#define DWC_OTG_HC_PID_DATA0   0
++#define DWC_OTG_HC_PID_DATA2   1
++#define DWC_OTG_HC_PID_DATA1   2
++#define DWC_OTG_HC_PID_MDATA   3
++#define DWC_OTG_HC_PID_SETUP   3
++#define DWC_OTG_PCGCCTL_OFFSET   0xE00
++#define DWC_OTG_DATA_FIFO_OFFSET   0x1000
++#define DWC_OTG_DATA_FIFO_SIZE   0x1000
++#define A_HOST   (1)
 A-Device is a_host.
++#define A_SUSPEND   (2)
 A-Device is a_suspend.
++#define A_PERIPHERAL   (3)
 A-Device is a_peripherial.
++#define B_PERIPHERAL   (4)
 B-Device is operating as a Peripheral.
++#define B_HOST   (5)
 B-Device is operating as a Host.

Typedefs

++typedef iso_pkt_info iso_pkt_info_t
 Information for each ISOC packet.
typedef dwc_ep dwc_ep_t
 The dwc_ep structure represents the state of a single endpoint when acting in device mode.
++typedef enum dwc_otg_halt_status dwc_otg_halt_status_e
typedef dwc_hc dwc_hc_t
 Host channel descriptor.
typedef dwc_otg_core_params dwc_otg_core_params_t
 The following parameters may be specified when starting the module.
++typedef enum dwc_otg_lx_state dwc_otg_lx_state_e
typedef dwc_otg_cil_callbacks dwc_otg_cil_callbacks_t
 DWC_otg CIL callback structure.

Enumerations

enum  dwc_otg_halt_status {
++  DWC_OTG_HC_XFER_NO_HALT_STATUS, ++DWC_OTG_HC_XFER_COMPLETE, ++DWC_OTG_HC_XFER_URB_COMPLETE, ++DWC_OTG_HC_XFER_ACK, ++
++  DWC_OTG_HC_XFER_NAK, ++DWC_OTG_HC_XFER_NYET, ++DWC_OTG_HC_XFER_STALL, ++DWC_OTG_HC_XFER_XACT_ERR, ++
++  DWC_OTG_HC_XFER_FRAME_OVERRUN, ++DWC_OTG_HC_XFER_BABBLE_ERR, ++DWC_OTG_HC_XFER_DATA_TOGGLE_ERR, ++DWC_OTG_HC_XFER_AHB_ERR, ++
++  DWC_OTG_HC_XFER_PERIODIC_INCOMPLETE, ++DWC_OTG_HC_XFER_URB_DEQUEUE ++
++ }
enum  dwc_otg_lx_state { DWC_OTG_L0, ++DWC_OTG_L1, ++DWC_OTG_L2, ++DWC_OTG_L3 ++ }

Functions

++void w_conn_id_status_change (void *p)
void w_wakeup_detected (void *p)
void dwc_otg_core_host_init (dwc_otg_core_if_t *_core_if)
 This function initializes the DWC_otg controller registers for host mode.
void dwc_otg_core_dev_init (dwc_otg_core_if_t *_core_if)
 This function initializes the DWC_otg controller registers for device mode.
void dwc_otg_cil_register_pcd_callbacks (dwc_otg_core_if_t *_core_if, dwc_otg_cil_callbacks_t *_cb, void *_p)
 Register PCD callbacks.
void dwc_otg_cil_register_hcd_callbacks (dwc_otg_core_if_t *_core_if, dwc_otg_cil_callbacks_t *_cb, void *_p)
 Register HCD callbacks.
++

Detailed Description

++This file contains the interface to the Core Interface Layer. ++

++ ++

++Definition in file dwc_otg_cil.h.

Define Documentation

++ ++
++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
#define clear_hc_int (_hc_regs_,
_intr_   ) 
++
++
++ ++

++Value:

do { \
++        hcint_data_t hcint_clear = {.d32 = 0}; \
++        hcint_clear.b._intr_ = 1; \
++        dwc_write_reg32(&(_hc_regs_)->hcint, hcint_clear.d32); \
++} while (0)
++
++

++Definition at line 903 of file dwc_otg_cil.h. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
#define disable_hc_int (_hc_regs_,
_intr_   ) 
++
++
++ ++

++Value:

do { \
++        hcintmsk_data_t hcintmsk = {.d32 = 0}; \
++        hcintmsk.b._intr_ = 1; \
++        dwc_modify_reg32(&(_hc_regs_)->hcintmsk, hcintmsk.d32, 0); \
++} while (0)
++
++

++Definition at line 917 of file dwc_otg_cil.h. ++

++

++

Typedef Documentation

++ ++
++
++ ++ ++ ++ ++
typedef struct dwc_ep dwc_ep_t
++
++
++ ++

++The dwc_ep structure represents the state of a single endpoint when acting in device mode. ++

++It contains the data items needed for an endpoint to be activated and transfer packets. ++

++

++ ++

++
++ ++ ++ ++ ++
typedef struct dwc_hc dwc_hc_t
++
++
++ ++

++Host channel descriptor. ++

++This structure represents the state of a single host channel when acting in host mode. It contains the data items needed to transfer packets to an endpoint via a host channel. ++

++

++ ++

++
++ ++ ++ ++ ++
typedef struct dwc_otg_core_params dwc_otg_core_params_t
++
++
++ ++

++The following parameters may be specified when starting the module. ++

++These parameters define how the DWC_otg controller should be configured. ++

++

++ ++

++
++ ++ ++ ++ ++
typedef struct dwc_otg_cil_callbacks dwc_otg_cil_callbacks_t
++
++
++ ++

++DWC_otg CIL callback structure. ++

++This structure allows the HCD and PCD to register functions used for starting and stopping the PCD and HCD for role change on for a DRD. ++

++

++

Enumeration Type Documentation

++ ++
++
++ ++ ++ ++ ++
enum dwc_otg_lx_state
++
++
++ ++

++

Enumerator:
++ ++ ++ ++ ++ ++
DWC_OTG_L0  ++On state.
DWC_OTG_L1  ++LPM sleep state.
DWC_OTG_L2  ++USB suspend state.
DWC_OTG_L3  ++Off state.
++
++ ++

++Definition at line 664 of file dwc_otg_cil.h. ++

++

++

Function Documentation

++ ++
++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void w_wakeup_detected (void *  p  ) 
++
++
++ ++

++ ++

++Definition at line 473 of file dwc_otg_cil_intr.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_otg_core_host_init (dwc_otg_core_if_t *  core_if  ) 
++
++
++ ++

++This function initializes the DWC_otg controller registers for host mode. ++

++This function flushes the Tx and Rx FIFOs and it flushes any entries in the request queues. Host channels are reset to ensure that they are ready for performing transfers.

++

Parameters:
++ ++ ++
core_if Programming view of DWC_otg controller
++
++ ++

++Definition at line 1196 of file dwc_otg_cil.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_otg_core_dev_init (dwc_otg_core_if_t *  core_if  ) 
++
++
++ ++

++This function initializes the DWC_otg controller registers for device mode. ++

++

Parameters:
++ ++ ++
core_if Programming view of DWC_otg controller
++
++ ++

++Set Periodic Tx FIFO Mask all bits 0

++Set Tx FIFO Mask all bits 0

++

Todo:
NGS: Fix Periodic FIFO Sizing!
++

++

Todo:
Finish debug of this
++

++

Todo:
    ++
  • if the condition needed to be checked or in any case all pending interrutps should be cleared?
++
++ ++

++Definition at line 843 of file dwc_otg_cil.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_otg_read_setup_packet (dwc_otg_core_if_t *  core_if,
uint32_t *  dest 
)
++
++
++ ++

++This function reads a setup packet from the Rx FIFO into the destination buffer. ++

++This function is called from the Rx Status Queue Level (RxStsQLvl) Interrupt routine when a SETUP packet has been received in Slave mode.

++

Parameters:
++ ++ ++ ++
core_if Programming view of DWC_otg controller.
dest Destination buffer for packet data.
++
++ ++

++Definition at line 2199 of file dwc_otg_cil.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
uint32_t dwc_otg_get_frame_number (dwc_otg_core_if_t *  core_if  ) 
++
++
++ ++

++Gets the current USB frame number. ++

++This is the frame number from the last SOF packet. ++

++Definition at line 2182 of file dwc_otg_cil.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_otg_ep0_activate (dwc_otg_core_if_t *  core_if,
dwc_ep_t *  ep 
)
++
++
++ ++

++This function enables EP0 OUT to receive SETUP packets and configures EP0 IN for transmitting packets. ++

++It is normally called when the "Enumeration Done" interrupt occurs.

++

Parameters:
++ ++ ++ ++
core_if Programming view of DWC_otg controller.
ep The EP0 data.
++
++ ++

++Definition at line 2216 of file dwc_otg_cil.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_otg_ep_activate (dwc_otg_core_if_t *  core_if,
dwc_ep_t *  ep 
)
++
++
++ ++

++This function activates an EP. ++

++The Device EP control register for the EP is configured as defined in the ep structure. Note: This function is not used for EP0.

++

Parameters:
++ ++ ++ ++
core_if Programming view of DWC_otg controller.
ep The EP to activate.
++
++ ++

++Definition at line 2268 of file dwc_otg_cil.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_otg_ep_deactivate (dwc_otg_core_if_t *  core_if,
dwc_ep_t *  ep 
)
++
++
++ ++

++This function deactivates an EP. ++

++This is done by clearing the USB Active EP bit in the Device EP control register. Note: This function is not used for EP0. EP0 cannot be deactivated.

++

Parameters:
++ ++ ++ ++
core_if Programming view of DWC_otg controller.
ep The EP to deactivate.
++
++ ++

++Definition at line 2367 of file dwc_otg_cil.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_otg_ep_start_transfer (dwc_otg_core_if_t *  core_if,
dwc_ep_t *  ep 
)
++
++
++ ++

++This function does the setup for a data transfer for an EP and starts the transfer. ++

++For an IN transfer, the packets will be loaded into the appropriate Tx FIFO in the ISR. For OUT transfers, the packets are unloaded from the Rx FIFO in the ISR. the ISR.

++

Parameters:
++ ++ ++ ++
core_if Programming view of DWC_otg controller.
ep The EP to start the transfer on.
++
++ ++

++DIEPDMAn Register write

++Enable the Non-Periodic Tx FIFO empty interrupt, or the Tx FIFO epmty interrupt in dedicated Tx FIFO mode, the data will be written into the fifo by the ISR.

++DOEPDMAn Register write ++

++Definition at line 2475 of file dwc_otg_cil.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_otg_ep_start_zl_transfer (dwc_otg_core_if_t *  core_if,
dwc_ep_t *  ep 
)
++
++
++ ++

++This function setup a zero length transfer in Buffer DMA and Slave modes for usb requests with zero field set. ++

++

Parameters:
++ ++ ++ ++
core_if Programming view of DWC_otg controller.
ep The EP to start the transfer on.
++
++ ++

++Enable the Non-Periodic Tx FIFO empty interrupt, or the Tx FIFO epmty interrupt in dedicated Tx FIFO mode, the data will be written into the fifo by the ISR. ++

++Definition at line 2678 of file dwc_otg_cil.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_otg_ep0_start_transfer (dwc_otg_core_if_t *  core_if,
dwc_ep_t *  ep 
)
++
++
++ ++

++This function does the setup for a data transfer for EP0 and starts the transfer. ++

++For an IN transfer, the packets will be loaded into the appropriate Tx FIFO in the ISR. For OUT transfers, the packets are unloaded from the Rx FIFO in the ISR.

++

Parameters:
++ ++ ++ ++
core_if Programming view of DWC_otg controller.
ep The EP0 data.
++
++ ++

++DMA Descriptor Setup

++DIEPDMA0 Register write

++Enable the Non-Periodic Tx FIFO empty interrupt, the data will be written into the fifo by the ISR.

++DMA Descriptor Setup

++DOEPDMA0 Register write ++

++Definition at line 2785 of file dwc_otg_cil.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_otg_ep0_continue_transfer (dwc_otg_core_if_t *  core_if,
dwc_ep_t *  ep 
)
++
++
++ ++

++This function continues control IN transfers started by dwc_otg_ep0_start_transfer, when the transfer does not fit in a single packet. ++

++NOTE: The DIEPCTL0/DOEPCTL0 registers only have one bit for the packet count.

++

Parameters:
++ ++ ++ ++
core_if Programming view of DWC_otg controller.
ep The EP0 data.
++
++ ++

++

Todo:
Should there be check for room in the Tx Status Queue. If not remove the code above this comment.
++

++DMA Descriptor Setup

++DIEPDMA0 Register write

++Enable the Non-Periodic Tx FIFO empty interrupt, the data will be written into the fifo by the ISR.

++DMA Descriptor Setup

++DOEPDMA0 Register write ++

++Definition at line 2969 of file dwc_otg_cil.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_otg_ep_write_packet (dwc_otg_core_if_t *  core_if,
dwc_ep_t *  ep,
int  dma 
)
++
++
++ ++

++This function writes a packet into the Tx FIFO associated with the EP. ++

++For non-periodic EPs the non-periodic Tx FIFO is written. For periodic EPs the periodic Tx FIFO associated with the EP is written with all packets for the next micro-frame.

++

Parameters:
++ ++ ++ ++ ++
core_if Programming view of DWC_otg controller.
ep The EP to write packet for.
dma Indicates if DMA is being used.
++
++ ++

++The buffer is padded to DWORD on a per packet basis in slave/dma mode if the MPS is not DWORD aligned. The last packet, if short, is also padded to a multiple of DWORD.

++ep->xfer_buff always starts DWORD aligned in memory and is a multiple of DWORD in length

++ep->xfer_len can be any number of bytes

++ep->xfer_count is a multiple of ep->maxpacket until the last packet

++FIFO access is DWORD

++

Todo:
NGS Where are the Periodic Tx FIFO addresses intialized? What should this be?
++ ++

++Definition at line 3165 of file dwc_otg_cil.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_otg_ep_set_stall (dwc_otg_core_if_t *  core_if,
dwc_ep_t *  ep 
)
++
++
++ ++

++Set the EP STALL. ++

++

Parameters:
++ ++ ++ ++
core_if Programming view of DWC_otg controller.
ep The EP to set the stall on.
++
++ ++

++Definition at line 3236 of file dwc_otg_cil.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_otg_ep_clear_stall (dwc_otg_core_if_t *  core_if,
dwc_ep_t *  ep 
)
++
++
++ ++

++Clear the EP STALL. ++

++

Parameters:
++ ++ ++ ++
core_if Programming view of DWC_otg controller.
ep The EP to clear stall from.
++
++ ++

++Definition at line 3274 of file dwc_otg_cil.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_otg_enable_device_interrupts (dwc_otg_core_if_t *  core_if  ) 
++
++
++ ++

++This function enables the Device mode interrupts. ++

++

Parameters:
++ ++ ++
core_if Programming view of DWC_otg controller
++
++ ++

++

Todo:
NGS: Should this be a module parameter?
++ ++

++Definition at line 772 of file dwc_otg_cil.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_otg_iso_ep_start_frm_transfer (dwc_otg_core_if_t *  core_if,
dwc_ep_t *  ep 
)
++
++
++ ++

++This function initializes a descriptor chain for Isochronous transfer. ++

++

Parameters:
++ ++ ++ ++
core_if Programming view of DWC_otg controller.
ep The EP to start the transfer on.
++
++ ++

++Enable endpoint, clear nak ++

++Definition at line 3864 of file dwc_otg_cil.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_otg_iso_ep_start_buf_transfer (dwc_otg_core_if_t *  core_if,
dwc_ep_t *  ep 
)
++
++
++ ++

++This function initializes a descriptor chain for Isochronous transfer. ++

++

Parameters:
++ ++ ++ ++
core_if Programming view of DWC_otg controller.
ep The EP to start the transfer on.
++
++ ++

++Enable endpoint, clear nak ++

++Definition at line 517 of file dwc_otg_pcd.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_otg_hc_init (dwc_otg_core_if_t *  core_if,
dwc_hc_t *  hc 
)
++
++
++ ++

++Prepares a host channel for transferring packets to/from a specific endpoint. ++

++The HCCHARn register is set up with the characteristics specified in _hc. Host channel interrupts that may need to be serviced while this transfer is in progress are enabled.

++

Parameters:
++ ++ ++ ++
core_if Programming view of DWC_otg controller
hc Information needed to initialize the host channel
++
++ ++

++Definition at line 1352 of file dwc_otg_cil.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_otg_hc_halt (dwc_otg_core_if_t *  core_if,
dwc_hc_t *  hc,
dwc_otg_halt_status_e  halt_status 
)
++
++
++ ++

++Attempts to halt a host channel. ++

++This function should only be called in Slave mode or to abort a transfer in either Slave mode or DMA mode. Under normal circumstances in DMA mode, the controller halts the channel when the transfer is complete or a condition occurs that requires application intervention.

++In slave mode, checks for a free request queue entry, then sets the Channel Enable and Channel Disable bits of the Host Channel Characteristics register of the specified channel to intiate the halt. If there is no free request queue entry, sets only the Channel Disable bit of the HCCHARn register to flush requests for this channel. In the latter case, sets a flag to indicate that the host channel needs to be halted when a request queue slot is open.

++In DMA mode, always sets the Channel Enable and Channel Disable bits of the HCCHARn register. The controller ensures there is space in the request queue before submitting the halt request.

++Some time may elapse before the core flushes any posted requests for this host channel and halts. The Channel Halted interrupt handler completes the deactivation of the host channel.

++

Parameters:
++ ++ ++ ++ ++
core_if Controller register interface.
hc Host channel to halt.
halt_status Reason for halting the channel.
++
++ ++

++Definition at line 1540 of file dwc_otg_cil.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_otg_hc_cleanup (dwc_otg_core_if_t *  core_if,
dwc_hc_t *  hc 
)
++
++
++ ++

++Clears the transfer state for a host channel. ++

++This function is normally called after a transfer is done and the host channel is being released.

++

Parameters:
++ ++ ++ ++
core_if Programming view of DWC_otg controller.
hc Identifies the host channel to clean up.
++
++ ++

++Definition at line 1667 of file dwc_otg_cil.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_otg_hc_start_transfer (dwc_otg_core_if_t *  core_if,
dwc_hc_t *  hc 
)
++
++
++ ++

++This function does the setup for a data transfer for a host channel and starts the transfer. ++

++May be called in either Slave mode or DMA mode. In Slave mode, the caller must ensure that there is sufficient space in the request queue and Tx Data FIFO.

++For an OUT transfer in Slave mode, it loads a data packet into the appropriate FIFO. If necessary, additional data packets will be loaded in the Host ISR.

++For an IN transfer in Slave mode, a data packet is requested. The data packets are unloaded from the Rx FIFO in the Host ISR. If necessary, additional data packets are requested in the Host ISR.

++For a PING transfer in Slave mode, the Do Ping bit is set in the HCTSIZ register along with a packet count of 1 and the channel is enabled. This causes a single PING transaction to occur. Other fields in HCTSIZ are simply set to 0 since no data transfer occurs in this case.

++For a PING transfer in DMA mode, the HCTSIZ register is initialized with all the information required to perform the subsequent data transfer. In addition, the Do Ping bit is set in the HCTSIZ register. In this case, the controller performs the entire PING protocol, then starts the data transfer.

++

Parameters:
++ ++ ++ ++
core_if Programming view of DWC_otg controller.
hc Information needed to initialize the host channel. The xfer_len value may be reduced to accommodate the max widths of the XferSize and PktCnt fields in the HCTSIZn register. The multi_count value may be changed to reflect the final xfer_len value.
++
++ ++

++Definition at line 1800 of file dwc_otg_cil.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int dwc_otg_hc_continue_transfer (dwc_otg_core_if_t *  core_if,
dwc_hc_t *  hc 
)
++
++
++ ++

++This function continues a data transfer that was started by previous call to dwc_otg_hc_start_transfer. ++

++The caller must ensure there is sufficient space in the request queue and Tx Data FIFO. This function should only be called in Slave mode. In DMA mode, the controller acts autonomously to complete transfers programmed to a host channel.

++For an OUT transfer, a new data packet is loaded into the appropriate FIFO if there is any data remaining to be queued. For an IN transfer, another data packet is always requested. For the SETUP phase of a control transfer, this function does nothing.

++

Returns:
1 if a new request is queued, 0 if no more requests are required for this transfer.
++ ++

++Definition at line 2048 of file dwc_otg_cil.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_otg_hc_do_ping (dwc_otg_core_if_t *  core_if,
dwc_hc_t *  hc 
)
++
++
++ ++

++Starts a PING transfer. ++

++This function should only be called in Slave mode. The Do Ping bit is set in the HCTSIZ register, then the channel is enabled. ++

++Definition at line 2110 of file dwc_otg_cil.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_otg_enable_host_interrupts (dwc_otg_core_if_t *  core_if  ) 
++
++
++ ++

++This function enables the Host mode interrupts. ++

++

Parameters:
++ ++ ++
core_if Programming view of DWC_otg controller
++
++ ++

++Definition at line 1130 of file dwc_otg_cil.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_otg_disable_host_interrupts (dwc_otg_core_if_t *  core_if  ) 
++
++
++ ++

++This function disables the Host Mode interrupts. ++

++

Parameters:
++ ++ ++
core_if Programming view of DWC_otg controller
++
++ ++

++Definition at line 1165 of file dwc_otg_cil.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_otg_hc_start_transfer_ddma (dwc_otg_core_if_t *  core_if,
dwc_hc_t *  hc 
)
++
++
++ ++

++This function does the setup for a data transfer for a host channel and starts the transfer in Descriptor DMA mode. ++

++Initializes HCTSIZ register. For a PING transfer the Do Ping bit is set. Sets PID and NTD values. For periodic transfers initializes SCHED_INFO field with micro-frame bitmap.

++Initializes HCDMA register with descriptor list address and CTD value then starts the transfer via enabling the channel.

++

Parameters:
++ ++ ++ ++
core_if Programming view of DWC_otg controller.
hc Information needed to initialize the host channel.
++
++ ++

++Definition at line 1968 of file dwc_otg_cil.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
static uint32_t dwc_otg_read_hprt0 (dwc_otg_core_if_t *  _core_if  )  [inline, static]
++
++
++ ++

++This function Reads HPRT0 in preparation to modify. ++

++It keeps the WC bits 0 so that if they are read as 1, they won't clear when you write it back ++

++Definition at line 929 of file dwc_otg_cil.h. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_otg_read_packet (dwc_otg_core_if_t *  core_if,
uint8_t *  dest,
uint16_t  bytes 
)
++
++
++ ++

++This function reads a packet from the Rx FIFO into the destination buffer. ++

++To read SETUP data use dwc_otg_read_setup_packet.

++

Parameters:
++ ++ ++ ++ ++
core_if Programming view of DWC_otg controller.
dest Destination buffer for the packet.
bytes Number of bytes to copy to the destination.
++
++ ++

++

Todo:
Account for the case where _dest is not dword aligned. This requires reading data from the FIFO into a uint32_t temp buffer, then moving it into the data buffer.
++ ++

++Definition at line 3317 of file dwc_otg_cil.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_otg_flush_tx_fifo (dwc_otg_core_if_t *  core_if,
const int  num 
)
++
++
++ ++

++Flush a Tx FIFO. ++

++

Parameters:
++ ++ ++ ++
core_if Programming view of DWC_otg controller.
num Tx FIFO to flush.
++
++ ++

++Definition at line 3662 of file dwc_otg_cil.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_otg_flush_rx_fifo (dwc_otg_core_if_t *  core_if  ) 
++
++
++ ++

++Flush Rx FIFO. ++

++

Parameters:
++ ++ ++
core_if Programming view of DWC_otg controller.
++
++ ++

++Definition at line 3694 of file dwc_otg_cil.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_otg_core_reset (dwc_otg_core_if_t *  core_if  ) 
++
++
++ ++

++Do core a soft reset of the core. ++

++Be careful with this because it resets all the internal state machines of the core. ++

++Definition at line 3725 of file dwc_otg_cil.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
static uint32_t dwc_otg_mode (dwc_otg_core_if_t *  _core_if  )  [inline, static]
++
++
++ ++

++This function returns the mode of the operation, host or device. ++

++

Returns:
0 - Device Mode, 1 - Host Mode
++ ++

++Definition at line 1097 of file dwc_otg_cil.h. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_otg_cil_register_pcd_callbacks (dwc_otg_core_if_t *  core_if,
dwc_otg_cil_callbacks_t *  cb,
void *  p 
)
++
++
++ ++

++Register PCD callbacks. ++

++The callbacks are used to start and stop the PCD for interrupt processing.

++

Parameters:
++ ++ ++ ++ ++
core_if Programming view of DWC_otg controller.
cb the PCD callback structure.
p pointer to be passed to callback function (pcd*).
++
++ ++

++Definition at line 3796 of file dwc_otg_cil.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_otg_cil_register_hcd_callbacks (dwc_otg_core_if_t *  core_if,
dwc_otg_cil_callbacks_t *  cb,
void *  p 
)
++
++
++ ++

++Register HCD callbacks. ++

++The callbacks are used to start and stop the HCD for interrupt processing.

++

Parameters:
++ ++ ++ ++ ++
core_if Programming view of DWC_otg controller.
cb the HCD callback structure.
p pointer to be passed to callback function (usb_hcd*).
++
++ ++

++Definition at line 3781 of file dwc_otg_cil.c. ++

++

++

Generated on Tue May 5 02:22:48 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__cil__intr_8c-source.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__cil__intr_8c-source.html 2013-07-26 19:31:20.000000000 +0000 +@@ -0,0 +1,742 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_cil_intr.c Source File ++ ++ ++ ++ ++
++
++
++
++

dwc_otg_cil_intr.c

Go to the documentation of this file.
00001 /* ==========================================================================
++00002  * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_cil_intr.c $
++00003  * $Revision: #15 $
++00004  * $Date: 2009/04/15 $
++00005  * $Change: 1234129 $
++00006  *
++00007  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
++00008  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
++00009  * otherwise expressly agreed to in writing between Synopsys and you.
++00010  *
++00011  * The Software IS NOT an item of Licensed Software or Licensed Product under
++00012  * any End User Software License Agreement or Agreement for Licensed Product
++00013  * with Synopsys or any supplement thereto. You are permitted to use and
++00014  * redistribute this Software in source and binary forms, with or without
++00015  * modification, provided that redistributions of source code must retain this
++00016  * notice. You may not view, use, disclose, copy or distribute this file or
++00017  * any information contained herein except pursuant to this license grant from
++00018  * Synopsys. If you do not agree with this notice, including the disclaimer
++00019  * below, then you are not authorized to use the Software.
++00020  *
++00021  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
++00022  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++00023  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++00024  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
++00025  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++00026  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
++00027  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
++00028  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
++00029  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
++00030  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
++00031  * DAMAGE.
++00032  * ========================================================================== */
++00033 
++00042 #include "dwc_os.h"
++00043 #include "dwc_otg_regs.h"
++00044 #include "dwc_otg_cil.h"
++00045 
++00046 #ifdef DEBUG
++00047 inline const char *op_state_str(dwc_otg_core_if_t * core_if)
++00048 {
++00049         return (core_if->op_state == A_HOST ? "a_host" :
++00050                 (core_if->op_state == A_SUSPEND ? "a_suspend" :
++00051                  (core_if->op_state == A_PERIPHERAL ? "a_peripheral" :
++00052                   (core_if->op_state == B_PERIPHERAL ? "b_peripheral" :
++00053                    (core_if->op_state == B_HOST ? "b_host" : "unknown")))));
++00054 }
++00055 #endif
++00056 
++00061 int32_t dwc_otg_handle_mode_mismatch_intr(dwc_otg_core_if_t * core_if)
++00062 {
++00063         gintsts_data_t gintsts;
++00064         DWC_WARN("Mode Mismatch Interrupt: currently in %s mode\n",
++00065                  dwc_otg_mode(core_if) ? "Host" : "Device");
++00066 
++00067         /* Clear interrupt */
++00068         gintsts.d32 = 0;
++00069         gintsts.b.modemismatch = 1;
++00070         dwc_write_reg32(&core_if->core_global_regs->gintsts, gintsts.d32);
++00071         return 1;
++00072 }
++00073 
++00078 static inline void hcd_start(dwc_otg_core_if_t * core_if)
++00079 {
++00080         if (core_if->hcd_cb && core_if->hcd_cb->start) {
++00081                 core_if->hcd_cb->start(core_if->hcd_cb->p);
++00082         }
++00083 }
++00084 
++00089 static inline void hcd_stop(dwc_otg_core_if_t * core_if)
++00090 {
++00091         if (core_if->hcd_cb && core_if->hcd_cb->stop) {
++00092                 core_if->hcd_cb->stop(core_if->hcd_cb->p);
++00093         }
++00094 }
++00095 
++00100 static inline void hcd_disconnect(dwc_otg_core_if_t * core_if)
++00101 {
++00102         if (core_if->hcd_cb && core_if->hcd_cb->disconnect) {
++00103                 core_if->hcd_cb->disconnect(core_if->hcd_cb->p);
++00104         }
++00105 }
++00106 
++00112 static inline void hcd_session_start(dwc_otg_core_if_t * core_if)
++00113 {
++00114         if (core_if->hcd_cb && core_if->hcd_cb->session_start) {
++00115                 core_if->hcd_cb->session_start(core_if->hcd_cb->p);
++00116         }
++00117 }
++00118 
++00119 #ifdef CONFIG_USB_DWC_OTG_LPM
++00120 
++00126 static inline void hcd_sleep(dwc_otg_core_if_t * core_if)
++00127 {
++00128         if (core_if->hcd_cb && core_if->hcd_cb->sleep) {
++00129                 core_if->hcd_cb->sleep(core_if->hcd_cb->p);
++00130         }
++00131 }
++00132 #endif
++00133 
++00138 static inline void hcd_resume(dwc_otg_core_if_t * core_if)
++00139 {
++00140         if (core_if->hcd_cb && core_if->hcd_cb->resume_wakeup) {
++00141                 core_if->hcd_cb->resume_wakeup(core_if->hcd_cb->p);
++00142         }
++00143 }
++00144 
++00149 static inline void pcd_start(dwc_otg_core_if_t * core_if)
++00150 {
++00151         if (core_if->pcd_cb && core_if->pcd_cb->start) {
++00152                 core_if->pcd_cb->start(core_if->pcd_cb->p);
++00153         }
++00154 }
++00155 
++00160 static inline void pcd_stop(dwc_otg_core_if_t * core_if)
++00161 {
++00162         if (core_if->pcd_cb && core_if->pcd_cb->stop) {
++00163                 core_if->pcd_cb->stop(core_if->pcd_cb->p);
++00164         }
++00165 }
++00166 
++00171 static inline void pcd_suspend(dwc_otg_core_if_t * core_if)
++00172 {
++00173         if (core_if->pcd_cb && core_if->pcd_cb->suspend) {
++00174                 core_if->pcd_cb->suspend(core_if->pcd_cb->p);
++00175         }
++00176 }
++00177 
++00182 static inline void pcd_resume(dwc_otg_core_if_t * core_if)
++00183 {
++00184         if (core_if->pcd_cb && core_if->pcd_cb->resume_wakeup) {
++00185                 core_if->pcd_cb->resume_wakeup(core_if->pcd_cb->p);
++00186         }
++00187 }
++00188 
++00196 int32_t dwc_otg_handle_otg_intr(dwc_otg_core_if_t * core_if)
++00197 {
++00198         dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
++00199         gotgint_data_t gotgint;
++00200         gotgctl_data_t gotgctl;
++00201         gintmsk_data_t gintmsk;
++00202 
++00203         gotgint.d32 = dwc_read_reg32(&global_regs->gotgint);
++00204         gotgctl.d32 = dwc_read_reg32(&global_regs->gotgctl);
++00205         DWC_DEBUGPL(DBG_CIL, "++OTG Interrupt gotgint=%0x [%s]\n", gotgint.d32,
++00206                     op_state_str(core_if));
++00207 
++00208         if (gotgint.b.sesenddet) {
++00209                 DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: "
++00210                             "Session End Detected++ (%s)\n",
++00211                             op_state_str(core_if));
++00212                 gotgctl.d32 = dwc_read_reg32(&global_regs->gotgctl);
++00213 
++00214                 if (core_if->op_state == B_HOST) {
++00215                         pcd_start(core_if);
++00216                         core_if->op_state = B_PERIPHERAL;
++00217                 } else {
++00218                         /* If not B_HOST and Device HNP still set. HNP
++00219                          * Did not succeed!*/
++00220                         if (gotgctl.b.devhnpen) {
++00221                                 DWC_DEBUGPL(DBG_ANY, "Session End Detected\n");
++00222                                 __DWC_ERROR("Device Not Connected/Responding!\n");
++00223                         }
++00224 
++00225                         /* If Session End Detected the B-Cable has
++00226                          * been disconnected. */
++00227                         /* Reset PCD and Gadget driver to a
++00228                          * clean state. */
++00229                         core_if->lx_state = DWC_OTG_L0;
++00230                         pcd_stop(core_if);
++00231                 }
++00232                 gotgctl.d32 = 0;
++00233                 gotgctl.b.devhnpen = 1;
++00234                 dwc_modify_reg32(&global_regs->gotgctl, gotgctl.d32, 0);
++00235         }
++00236         if (gotgint.b.sesreqsucstschng) {
++00237                 DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: "
++00238                             "Session Reqeust Success Status Change++\n");
++00239                 gotgctl.d32 = dwc_read_reg32(&global_regs->gotgctl);
++00240                 if (gotgctl.b.sesreqscs) {
++00241                         if ((core_if->core_params->phy_type ==
++00242                              DWC_PHY_TYPE_PARAM_FS) && (core_if->core_params->i2c_enable)) {
++00243                                 core_if->srp_success = 1;
++00244                         } else {
++00245                                 pcd_resume(core_if);
++00246                                 /* Clear Session Request */
++00247                                 gotgctl.d32 = 0;
++00248                                 gotgctl.b.sesreq = 1;
++00249                                 dwc_modify_reg32(&global_regs->gotgctl,
++00250                                                  gotgctl.d32, 0);
++00251                         }
++00252                 }
++00253         }
++00254         if (gotgint.b.hstnegsucstschng) {
++00255                 /* Print statements during the HNP interrupt handling
++00256                  * can cause it to fail.*/
++00257                 gotgctl.d32 = dwc_read_reg32(&global_regs->gotgctl);
++00258                 if (gotgctl.b.hstnegscs) {
++00259                         if (dwc_otg_is_host_mode(core_if)) {
++00260                                 core_if->op_state = B_HOST;
++00261                                 /*
++00262                                  * Need to disable SOF interrupt immediately.
++00263                                  * When switching from device to host, the PCD
++00264                                  * interrupt handler won't handle the
++00265                                  * interrupt if host mode is already set. The
++00266                                  * HCD interrupt handler won't get called if
++00267                                  * the HCD state is HALT. This means that the
++00268                                  * interrupt does not get handled and Linux
++00269                                  * complains loudly.
++00270                                  */
++00271                                 gintmsk.d32 = 0;
++00272                                 gintmsk.b.sofintr = 1;
++00273                                 dwc_modify_reg32(&global_regs->gintmsk,
++00274                                                  gintmsk.d32, 0);
++00275                                 pcd_stop(core_if);
++00276                                 /*
++00277                                  * Initialize the Core for Host mode.
++00278                                  */
++00279                                 hcd_start(core_if);
++00280                                 core_if->op_state = B_HOST;
++00281                         }
++00282                 } else {
++00283                         gotgctl.d32 = 0;
++00284                         gotgctl.b.hnpreq = 1;
++00285                         gotgctl.b.devhnpen = 1;
++00286                         dwc_modify_reg32(&global_regs->gotgctl, gotgctl.d32, 0);
++00287                         DWC_DEBUGPL(DBG_ANY, "HNP Failed\n");
++00288                         __DWC_ERROR("Device Not Connected/Responding\n");
++00289                 }
++00290         }
++00291         if (gotgint.b.hstnegdet) {
++00292                 /* The disconnect interrupt is set at the same time as
++00293                  * Host Negotiation Detected.  During the mode
++00294                  * switch all interrupts are cleared so the disconnect
++00295                  * interrupt handler will not get executed.
++00296                  */
++00297                 DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: "
++00298                             "Host Negotiation Detected++ (%s)\n",
++00299                             (dwc_otg_is_host_mode(core_if) ? "Host" :
++00300                              "Device"));
++00301                 if (dwc_otg_is_device_mode(core_if)) {
++00302                         DWC_DEBUGPL(DBG_ANY, "a_suspend->a_peripheral (%d)\n",
++00303                                     core_if->op_state);
++00304                         hcd_disconnect(core_if);
++00305                         pcd_start(core_if);
++00306                         core_if->op_state = A_PERIPHERAL;
++00307                 } else {
++00308                         /*
++00309                          * Need to disable SOF interrupt immediately. When
++00310                          * switching from device to host, the PCD interrupt
++00311                          * handler won't handle the interrupt if host mode is
++00312                          * already set. The HCD interrupt handler won't get
++00313                          * called if the HCD state is HALT. This means that
++00314                          * the interrupt does not get handled and Linux
++00315                          * complains loudly.
++00316                          */
++00317                         gintmsk.d32 = 0;
++00318                         gintmsk.b.sofintr = 1;
++00319                         dwc_modify_reg32(&global_regs->gintmsk, gintmsk.d32, 0);
++00320                         pcd_stop(core_if);
++00321                         hcd_start(core_if);
++00322                         core_if->op_state = A_HOST;
++00323                 }
++00324         }
++00325         if (gotgint.b.adevtoutchng) {
++00326                 DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: "
++00327                             "A-Device Timeout Change++\n");
++00328         }
++00329         if (gotgint.b.debdone) {
++00330                 DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: " "Debounce Done++\n");
++00331         }
++00332 
++00333         /* Clear GOTGINT */
++00334         dwc_write_reg32(&core_if->core_global_regs->gotgint, gotgint.d32);
++00335 
++00336         return 1;
++00337 }
++00338 
++00339 void w_conn_id_status_change(void *p)
++00340 {
++00341         dwc_otg_core_if_t *core_if = p;
++00342         uint32_t count = 0;
++00343         gotgctl_data_t gotgctl = {.d32 = 0 };
++00344 
++00345         gotgctl.d32 = dwc_read_reg32(&core_if->core_global_regs->gotgctl);
++00346         DWC_DEBUGPL(DBG_CIL, "gotgctl=%0x\n", gotgctl.d32);
++00347         DWC_DEBUGPL(DBG_CIL, "gotgctl.b.conidsts=%d\n", gotgctl.b.conidsts);
++00348 
++00349         /* B-Device connector (Device Mode) */
++00350         if (gotgctl.b.conidsts) {
++00351                 /* Wait for switch to device mode. */
++00352                 while (!dwc_otg_is_device_mode(core_if)) {
++00353                         DWC_PRINTF("Waiting for Peripheral Mode, Mode=%s\n",
++00354                                    (dwc_otg_is_host_mode(core_if) ? "Host" :
++00355                                     "Peripheral"));
++00356                         dwc_mdelay(100);
++00357                         if (++count > 10000)
++00358                                 break;
++00359                 }
++00360                 DWC_ASSERT(++count < 10000,
++00361                            "Connection id status change timed out");
++00362                 core_if->op_state = B_PERIPHERAL;
++00363                 dwc_otg_core_init(core_if);
++00364                 dwc_otg_enable_global_interrupts(core_if);
++00365                 pcd_start(core_if);
++00366         } else {
++00367                 /* A-Device connector (Host Mode) */
++00368                 while (!dwc_otg_is_host_mode(core_if)) {
++00369                         DWC_PRINTF("Waiting for Host Mode, Mode=%s\n",
++00370                                    (dwc_otg_is_host_mode(core_if) ? "Host" :
++00371                                     "Peripheral"));
++00372                         dwc_mdelay(100);
++00373                         if (++count > 10000)
++00374                                 break;
++00375                 }
++00376                 DWC_ASSERT(++count < 10000,
++00377                            "Connection id status change timed out");
++00378                 core_if->op_state = A_HOST;
++00379                 /*
++00380                  * Initialize the Core for Host mode.
++00381                  */
++00382                 dwc_otg_core_init(core_if);
++00383                 dwc_otg_enable_global_interrupts(core_if);
++00384                 hcd_start(core_if);
++00385         }
++00386 }
++00387 
++00399 int32_t dwc_otg_handle_conn_id_status_change_intr(dwc_otg_core_if_t * core_if)
++00400 {
++00401 
++00402         /*
++00403          * Need to disable SOF interrupt immediately. If switching from device
++00404          * to host, the PCD interrupt handler won't handle the interrupt if
++00405          * host mode is already set. The HCD interrupt handler won't get
++00406          * called if the HCD state is HALT. This means that the interrupt does
++00407          * not get handled and Linux complains loudly.
++00408          */
++00409         gintmsk_data_t gintmsk = {.d32 = 0 };
++00410         gintsts_data_t gintsts = {.d32 = 0 };
++00411 
++00412         gintmsk.b.sofintr = 1;
++00413         dwc_modify_reg32(&core_if->core_global_regs->gintmsk, gintmsk.d32, 0);
++00414 
++00415         DWC_DEBUGPL(DBG_CIL,
++00416                     " ++Connector ID Status Change Interrupt++  (%s)\n",
++00417                     (dwc_otg_is_host_mode(core_if) ? "Host" : "Device"));
++00418 
++00419         /*
++00420          * Need to schedule a work, as there are possible DELAY function calls
++00421          */
++00422         DWC_WORKQ_SCHEDULE(core_if->wq_otg, w_conn_id_status_change,
++00423                            core_if, "connection id status change");
++00424 
++00425         /* Set flag and clear interrupt */
++00426         gintsts.b.conidstschng = 1;
++00427         dwc_write_reg32(&core_if->core_global_regs->gintsts, gintsts.d32);
++00428 
++00429         return 1;
++00430 }
++00431 
++00441 int32_t dwc_otg_handle_session_req_intr(dwc_otg_core_if_t * core_if)
++00442 {
++00443         hprt0_data_t hprt0;
++00444         gintsts_data_t gintsts;
++00445 
++00446 #ifndef DWC_HOST_ONLY
++00447         DWC_DEBUGPL(DBG_ANY, "++Session Request Interrupt++\n");
++00448 
++00449         if (dwc_otg_is_device_mode(core_if)) {
++00450                 DWC_PRINTF("SRP: Device mode\n");
++00451         } else {
++00452                 DWC_PRINTF("SRP: Host mode\n");
++00453 
++00454                 /* Turn on the port power bit. */
++00455                 hprt0.d32 = dwc_otg_read_hprt0(core_if);
++00456                 hprt0.b.prtpwr = 1;
++00457                 dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
++00458 
++00459                 /* Start the Connection timer. So a message can be displayed
++00460                  * if connect does not occur within 10 seconds. */
++00461                 hcd_session_start(core_if);
++00462         }
++00463 #endif
++00464 
++00465         /* Clear interrupt */
++00466         gintsts.d32 = 0;
++00467         gintsts.b.sessreqintr = 1;
++00468         dwc_write_reg32(&core_if->core_global_regs->gintsts, gintsts.d32);
++00469 
++00470         return 1;
++00471 }
++00472 
++00473 void w_wakeup_detected(void *p)
++00474 {
++00475         dwc_otg_core_if_t *core_if = (dwc_otg_core_if_t *) p;
++00476         /*
++00477          * Clear the Resume after 70ms. (Need 20 ms minimum. Use 70 ms
++00478          * so that OPT tests pass with all PHYs).
++00479          */
++00480         hprt0_data_t hprt0 = {.d32 = 0 };
++00481 #if 0
++00482         pcgcctl_data_t pcgcctl = {.d32 = 0 };
++00483         /* Restart the Phy Clock */
++00484         pcgcctl.b.stoppclk = 1;
++00485         dwc_modify_reg32(core_if->pcgcctl, pcgcctl.d32, 0);
++00486         dwc_udelay(10);
++00487 #endif                          //0
++00488         hprt0.d32 = dwc_otg_read_hprt0(core_if);
++00489         DWC_DEBUGPL(DBG_ANY, "Resume: HPRT0=%0x\n", hprt0.d32);
++00490 //      dwc_mdelay(70);
++00491         hprt0.b.prtres = 0;     /* Resume */
++00492         dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
++00493         DWC_DEBUGPL(DBG_ANY, "Clear Resume: HPRT0=%0x\n",
++00494                     dwc_read_reg32(core_if->host_if->hprt0));
++00495 
++00496         hcd_resume(core_if);
++00497 
++00499         core_if->lx_state = DWC_OTG_L0;
++00500 
++00501 }
++00502 
++00510 int32_t dwc_otg_handle_wakeup_detected_intr(dwc_otg_core_if_t * core_if)
++00511 {
++00512         gintsts_data_t gintsts;
++00513 
++00514         DWC_DEBUGPL(DBG_ANY,
++00515                     "++Resume and Remote Wakeup Detected Interrupt++\n");
++00516 
++00517         DWC_PRINTF("%s lxstate = %d\n", __func__, core_if->lx_state);
++00518 
++00519         if (dwc_otg_is_device_mode(core_if)) {
++00520                 dctl_data_t dctl = {.d32 = 0 };
++00521                 DWC_DEBUGPL(DBG_PCD, "DSTS=0x%0x\n",
++00522                             dwc_read_reg32(&core_if->dev_if->dev_global_regs->
++00523                                            dsts));
++00524                 if (core_if->lx_state == DWC_OTG_L2) {
++00525 #ifdef PARTIAL_POWER_DOWN
++00526                         if (core_if->hwcfg4.b.power_optimiz) {
++00527                                 pcgcctl_data_t power = {.d32 = 0 };
++00528 
++00529                                 power.d32 = dwc_read_reg32(core_if->pcgcctl);
++00530                                 DWC_DEBUGPL(DBG_CIL, "PCGCCTL=%0x\n",
++00531                                             power.d32);
++00532 
++00533                                 power.b.stoppclk = 0;
++00534                                 dwc_write_reg32(core_if->pcgcctl, power.d32);
++00535 
++00536                                 power.b.pwrclmp = 0;
++00537                                 dwc_write_reg32(core_if->pcgcctl, power.d32);
++00538 
++00539                                 power.b.rstpdwnmodule = 0;
++00540                                 dwc_write_reg32(core_if->pcgcctl, power.d32);
++00541                         }
++00542 #endif
++00543                         /* Clear the Remote Wakeup Signalling */
++00544                         dctl.b.rmtwkupsig = 1;
++00545                         dwc_modify_reg32(&core_if->dev_if->dev_global_regs->
++00546                                          dctl, dctl.d32, 0);
++00547 
++00548                         if (core_if->pcd_cb && core_if->pcd_cb->resume_wakeup) {
++00549                                 core_if->pcd_cb->resume_wakeup(core_if->pcd_cb->
++00550                                                                p);
++00551                         }
++00552                 } else {
++00553                         glpmcfg_data_t lpmcfg;
++00554                         lpmcfg.d32 =
++00555                             dwc_read_reg32(&core_if->core_global_regs->glpmcfg);
++00556                         lpmcfg.b.hird_thres &= (~(1 << 4));
++00557                         dwc_write_reg32(&core_if->core_global_regs->glpmcfg,
++00558                                         lpmcfg.d32);
++00559                 }
++00561                 core_if->lx_state = DWC_OTG_L0;
++00562         } else {
++00563                 if (core_if->lx_state != DWC_OTG_L1) {
++00564                         pcgcctl_data_t pcgcctl = {.d32 = 0 };
++00565 
++00566                         /* Restart the Phy Clock */
++00567                         pcgcctl.b.stoppclk = 1;
++00568                         dwc_modify_reg32(core_if->pcgcctl, pcgcctl.d32, 0);
++00569 
++00570                         DWC_TIMER_SCHEDULE(core_if->wkp_timer, 71);
++00571                 } else {
++00573                         core_if->lx_state = DWC_OTG_L0;
++00574                 }
++00575         }
++00576 
++00577         /* Clear interrupt */
++00578         gintsts.d32 = 0;
++00579         gintsts.b.wkupintr = 1;
++00580         dwc_write_reg32(&core_if->core_global_regs->gintsts, gintsts.d32);
++00581 
++00582         return 1;
++00583 }
++00584 
++00589 int32_t dwc_otg_handle_disconnect_intr(dwc_otg_core_if_t * core_if)
++00590 {
++00591         gintsts_data_t gintsts;
++00592 
++00593         DWC_DEBUGPL(DBG_ANY, "++Disconnect Detected Interrupt++ (%s) %s\n",
++00594                     (dwc_otg_is_host_mode(core_if) ? "Host" : "Device"),
++00595                     op_state_str(core_if));
++00596 
++00598 #ifndef DWC_HOST_ONLY
++00599         if (core_if->op_state == B_HOST) {
++00600                 /* If in device mode Disconnect and stop the HCD, then
++00601                  * start the PCD. */
++00602                 hcd_disconnect(core_if);
++00603                 pcd_start(core_if);
++00604                 core_if->op_state = B_PERIPHERAL;
++00605         } else if (dwc_otg_is_device_mode(core_if)) {
++00606                 gotgctl_data_t gotgctl = {.d32 = 0 };
++00607                 gotgctl.d32 =
++00608                     dwc_read_reg32(&core_if->core_global_regs->gotgctl);
++00609                 if (gotgctl.b.hstsethnpen == 1) {
++00610                         /* Do nothing, if HNP in process the OTG
++00611                          * interrupt "Host Negotiation Detected"
++00612                          * interrupt will do the mode switch.
++00613                          */
++00614                 } else if (gotgctl.b.devhnpen == 0) {
++00615                         /* If in device mode Disconnect and stop the HCD, then
++00616                          * start the PCD. */
++00617                         hcd_disconnect(core_if);
++00618                         pcd_start(core_if);
++00619                         core_if->op_state = B_PERIPHERAL;
++00620                 } else {
++00621                         DWC_DEBUGPL(DBG_ANY, "!a_peripheral && !devhnpen\n");
++00622                 }
++00623         } else {
++00624                 if (core_if->op_state == A_HOST) {
++00625                         /* A-Cable still connected but device disconnected. */
++00626                         hcd_disconnect(core_if);
++00627                 }
++00628         }
++00629 #endif
++00630         /* Change to L3(OFF) state */
++00631         core_if->lx_state = DWC_OTG_L3;
++00632 
++00633         gintsts.d32 = 0;
++00634         gintsts.b.disconnect = 1;
++00635         dwc_write_reg32(&core_if->core_global_regs->gintsts, gintsts.d32);
++00636         return 1;
++00637 }
++00638 
++00649 int32_t dwc_otg_handle_usb_suspend_intr(dwc_otg_core_if_t * core_if)
++00650 {
++00651         dsts_data_t dsts;
++00652         gintsts_data_t gintsts;
++00653 
++00654         DWC_DEBUGPL(DBG_ANY, "USB SUSPEND\n");
++00655 
++00656         if (dwc_otg_is_device_mode(core_if)) {
++00657                 /* Check the Device status register to determine if the Suspend
++00658                  * state is active. */
++00659                 dsts.d32 =
++00660                     dwc_read_reg32(&core_if->dev_if->dev_global_regs->dsts);
++00661                 DWC_DEBUGPL(DBG_PCD, "DSTS=0x%0x\n", dsts.d32);
++00662                 DWC_DEBUGPL(DBG_PCD, "DSTS.Suspend Status=%d "
++00663                             "HWCFG4.power Optimize=%d\n",
++00664                             dsts.b.suspsts, core_if->hwcfg4.b.power_optimiz);
++00665 
++00666 #ifdef PARTIAL_POWER_DOWN
++00667 
++00669                 if (dsts.b.suspsts && core_if->hwcfg4.b.power_optimiz) {
++00670                         pcgcctl_data_t power = {.d32 = 0 };
++00671                         DWC_DEBUGPL(DBG_CIL, "suspend\n");
++00672 
++00673                         power.b.pwrclmp = 1;
++00674                         dwc_write_reg32(core_if->pcgcctl, power.d32);
++00675 
++00676                         power.b.rstpdwnmodule = 1;
++00677                         dwc_modify_reg32(core_if->pcgcctl, 0, power.d32);
++00678 
++00679                         power.b.stoppclk = 1;
++00680                         dwc_modify_reg32(core_if->pcgcctl, 0, power.d32);
++00681 
++00682                 } else {
++00683                         DWC_DEBUGPL(DBG_ANY, "disconnect?\n");
++00684                 }
++00685 #endif
++00686                 /* PCD callback for suspend. */
++00687                 pcd_suspend(core_if);
++00688         } else {
++00689                 if (core_if->op_state == A_PERIPHERAL) {
++00690                         DWC_DEBUGPL(DBG_ANY, "a_peripheral->a_host\n");
++00691                         /* Clear the a_peripheral flag, back to a_host. */
++00692                         pcd_stop(core_if);
++00693                         hcd_start(core_if);
++00694                         core_if->op_state = A_HOST;
++00695                 }
++00696         }
++00697 
++00698         /* Change to L2(suspend) state */
++00699         core_if->lx_state = DWC_OTG_L2;
++00700 
++00701         /* Clear interrupt */
++00702         gintsts.d32 = 0;
++00703         gintsts.b.usbsuspend = 1;
++00704         dwc_write_reg32(&core_if->core_global_regs->gintsts, gintsts.d32);
++00705 
++00706         return 1;
++00707 }
++00708 
++00709 #ifdef CONFIG_USB_DWC_OTG_LPM
++00710 
++00713 static int32_t dwc_otg_handle_lpm_intr(dwc_otg_core_if_t * core_if)
++00714 {
++00715         glpmcfg_data_t lpmcfg;
++00716         gintsts_data_t gintsts;
++00717 
++00718         if (!core_if->core_params->lpm_enable) {
++00719                 DWC_PRINTF("Unexpected LPM interrupt\n");
++00720         }
++00721 
++00722         lpmcfg.d32 = dwc_read_reg32(&core_if->core_global_regs->glpmcfg);
++00723         DWC_PRINTF("LPM config register = 0x%08x\n", lpmcfg.d32);
++00724 
++00725         if (dwc_otg_is_host_mode(core_if)) {
++00726                 hcd_sleep(core_if);
++00727         } else {
++00728                 lpmcfg.b.hird_thres |= (1 << 4);
++00729                 dwc_write_reg32(&core_if->core_global_regs->glpmcfg,
++00730                                 lpmcfg.d32);
++00731         }
++00732 
++00733         /* Examine prt_sleep_sts after TL1TokenTetry period max (10 us) */      
++00734         dwc_udelay(10);
++00735         lpmcfg.d32 = dwc_read_reg32(&core_if->core_global_regs->glpmcfg);
++00736         if (lpmcfg.b.prt_sleep_sts) {
++00737                 /* Save the current state */
++00738                 core_if->lx_state = DWC_OTG_L1;
++00739         }
++00740 
++00741         /* Clear interrupt  */
++00742         gintsts.d32 = 0;
++00743         gintsts.b.lpmtranrcvd = 1;
++00744         dwc_write_reg32(&core_if->core_global_regs->gintsts, gintsts.d32);
++00745         return 1;
++00746 }
++00747 #endif                          /* CONFIG_USB_DWC_OTG_LPM */
++00748 
++00752 static inline uint32_t dwc_otg_read_common_intr(dwc_otg_core_if_t * core_if)
++00753 {
++00754         gintsts_data_t gintsts;
++00755         gintmsk_data_t gintmsk;
++00756         gintmsk_data_t gintmsk_common = {.d32 = 0 };
++00757         gintmsk_common.b.wkupintr = 1;
++00758         gintmsk_common.b.sessreqintr = 1;
++00759         gintmsk_common.b.conidstschng = 1;
++00760         gintmsk_common.b.otgintr = 1;
++00761         gintmsk_common.b.modemismatch = 1;
++00762         gintmsk_common.b.disconnect = 1;
++00763         gintmsk_common.b.usbsuspend = 1;
++00764 #ifdef CONFIG_USB_DWC_OTG_LPM
++00765         gintmsk_common.b.lpmtranrcvd = 1;
++00766 #endif
++00767 
++00770         gintmsk_common.b.portintr = 1;
++00771 
++00772         gintsts.d32 = dwc_read_reg32(&core_if->core_global_regs->gintsts);
++00773         gintmsk.d32 = dwc_read_reg32(&core_if->core_global_regs->gintmsk);
++00774 #ifdef DEBUG
++00775         /* if any common interrupts set */
++00776         if (gintsts.d32 & gintmsk_common.d32) {
++00777                 DWC_DEBUGPL(DBG_ANY, "gintsts=%08x  gintmsk=%08x\n",
++00778                             gintsts.d32, gintmsk.d32);
++00779         }
++00780 #endif
++00781 
++00782         return ((gintsts.d32 & gintmsk.d32) & gintmsk_common.d32);
++00783 
++00784 }
++00785 
++00800 int32_t dwc_otg_handle_common_intr(dwc_otg_core_if_t * core_if)
++00801 {
++00802         int retval = 0;
++00803         gintsts_data_t gintsts;
++00804 
++00805         gintsts.d32 = dwc_otg_read_common_intr(core_if);
++00806 
++00807         if (gintsts.b.modemismatch) {
++00808                 retval |= dwc_otg_handle_mode_mismatch_intr(core_if);
++00809         }
++00810         if (gintsts.b.otgintr) {
++00811                 retval |= dwc_otg_handle_otg_intr(core_if);
++00812         }
++00813         if (gintsts.b.conidstschng) {
++00814                 retval |= dwc_otg_handle_conn_id_status_change_intr(core_if);
++00815         }
++00816         if (gintsts.b.disconnect) {
++00817                 retval |= dwc_otg_handle_disconnect_intr(core_if);
++00818         }
++00819         if (gintsts.b.sessreqintr) {
++00820                 retval |= dwc_otg_handle_session_req_intr(core_if);
++00821         }
++00822         if (gintsts.b.wkupintr) {
++00823                 retval |= dwc_otg_handle_wakeup_detected_intr(core_if);
++00824         }
++00825         if (gintsts.b.usbsuspend) {
++00826                 retval |= dwc_otg_handle_usb_suspend_intr(core_if);
++00827         }
++00828 #ifdef CONFIG_USB_DWC_OTG_LPM
++00829         if (gintsts.b.lpmtranrcvd) {
++00830                 retval |= dwc_otg_handle_lpm_intr(core_if);
++00831         }
++00832 #endif
++00833 
++00834         if (gintsts.b.portintr && dwc_otg_is_device_mode(core_if)) {
++00835                 /* The port interrupt occurs while in device mode with HPRT0
++00836                  * Port Enable/Disable.
++00837                  */
++00838                 gintsts.d32 = 0;
++00839                 gintsts.b.portintr = 1;
++00840                 dwc_write_reg32(&core_if->core_global_regs->gintsts,
++00841                                 gintsts.d32);
++00842                 retval |= 1;
++00843 
++00844         }
++00845         return retval;
++00846 }
++
Generated on Tue May 5 02:22:48 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__cil__intr_8c.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__cil__intr_8c.html 2013-07-26 19:31:20.000000000 +0000 +@@ -0,0 +1,645 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_cil_intr.c File Reference ++ ++ ++ ++ ++
++
++
++
++

dwc_otg_cil_intr.c File Reference

The Core Interface Layer provides basic services for accessing and managing the DWC_otg hardware. More... ++

++#include "dwc_os.h"
++#include "dwc_otg_regs.h"
++#include "dwc_otg_cil.h"
++ ++

++Go to the source code of this file. ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++

Functions

int32_t dwc_otg_handle_mode_mismatch_intr (dwc_otg_core_if_t *core_if)
 This function will log a debug message.
static void hcd_start (dwc_otg_core_if_t *core_if)
 Start the HCD.
static void hcd_stop (dwc_otg_core_if_t *core_if)
 Stop the HCD.
static void hcd_disconnect (dwc_otg_core_if_t *core_if)
 Disconnect the HCD.
static void hcd_session_start (dwc_otg_core_if_t *core_if)
 Inform the HCD the a New Session has begun.
static void hcd_resume (dwc_otg_core_if_t *core_if)
 Resume the HCD.
static void pcd_start (dwc_otg_core_if_t *core_if)
 Start the PCD.
static void pcd_stop (dwc_otg_core_if_t *core_if)
 Stop the PCD.
static void pcd_suspend (dwc_otg_core_if_t *core_if)
 Suspend the PCD.
static void pcd_resume (dwc_otg_core_if_t *core_if)
 Resume the PCD.
int32_t dwc_otg_handle_otg_intr (dwc_otg_core_if_t *core_if)
 This function handles the OTG Interrupts.
++void w_conn_id_status_change (void *p)
int32_t dwc_otg_handle_conn_id_status_change_intr (dwc_otg_core_if_t *core_if)
 This function handles the Connector ID Status Change Interrupt.
int32_t dwc_otg_handle_session_req_intr (dwc_otg_core_if_t *core_if)
 This interrupt indicates that a device is initiating the Session Request Protocol to request the host to turn on bus power so a new session can begin.
void w_wakeup_detected (void *p)
int32_t dwc_otg_handle_wakeup_detected_intr (dwc_otg_core_if_t *core_if)
 This interrupt indicates that the DWC_otg controller has detected a resume or remote wakeup sequence.
int32_t dwc_otg_handle_disconnect_intr (dwc_otg_core_if_t *core_if)
 This interrupt indicates that a device has been disconnected from the root port.
int32_t dwc_otg_handle_usb_suspend_intr (dwc_otg_core_if_t *core_if)
 This interrupt indicates that SUSPEND state has been detected on the USB.
static uint32_t dwc_otg_read_common_intr (dwc_otg_core_if_t *core_if)
 This function returns the Core Interrupt register.
int32_t dwc_otg_handle_common_intr (dwc_otg_core_if_t *core_if)
 This function should be called on every hardware interrupt.
++

Detailed Description

++The Core Interface Layer provides basic services for accessing and managing the DWC_otg hardware. ++

++These services are used by both the Host Controller Driver and the Peripheral Controller Driver.

++This file contains the Common Interrupt handlers. ++

++Definition in file dwc_otg_cil_intr.c.

Function Documentation

++ ++
++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int32_t dwc_otg_handle_mode_mismatch_intr (dwc_otg_core_if_t *  core_if  ) 
++
++
++ ++

++This function will log a debug message. ++

++

Parameters:
++ ++ ++
core_if Programming view of DWC_otg controller.
++
++ ++

++Definition at line 61 of file dwc_otg_cil_intr.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
static void hcd_start (dwc_otg_core_if_t *  core_if  )  [inline, static]
++
++
++ ++

++Start the HCD. ++

++Helper function for using the HCD callbacks.

++

Parameters:
++ ++ ++
core_if Programming view of DWC_otg controller.
++
++ ++

++Definition at line 78 of file dwc_otg_cil_intr.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
static void hcd_stop (dwc_otg_core_if_t *  core_if  )  [inline, static]
++
++
++ ++

++Stop the HCD. ++

++Helper function for using the HCD callbacks.

++

Parameters:
++ ++ ++
core_if Programming view of DWC_otg controller.
++
++ ++

++Definition at line 89 of file dwc_otg_cil_intr.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
static void hcd_disconnect (dwc_otg_core_if_t *  core_if  )  [inline, static]
++
++
++ ++

++Disconnect the HCD. ++

++Helper function for using the HCD callbacks.

++

Parameters:
++ ++ ++
core_if Programming view of DWC_otg controller.
++
++ ++

++Definition at line 100 of file dwc_otg_cil_intr.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
static void hcd_session_start (dwc_otg_core_if_t *  core_if  )  [inline, static]
++
++
++ ++

++Inform the HCD the a New Session has begun. ++

++Helper function for using the HCD callbacks.

++

Parameters:
++ ++ ++
core_if Programming view of DWC_otg controller.
++
++ ++

++Definition at line 112 of file dwc_otg_cil_intr.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
static void hcd_resume (dwc_otg_core_if_t *  core_if  )  [inline, static]
++
++
++ ++

++Resume the HCD. ++

++Helper function for using the HCD callbacks.

++

Parameters:
++ ++ ++
core_if Programming view of DWC_otg controller.
++
++ ++

++Definition at line 138 of file dwc_otg_cil_intr.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
static void pcd_start (dwc_otg_core_if_t *  core_if  )  [inline, static]
++
++
++ ++

++Start the PCD. ++

++Helper function for using the PCD callbacks.

++

Parameters:
++ ++ ++
core_if Programming view of DWC_otg controller.
++
++ ++

++Definition at line 149 of file dwc_otg_cil_intr.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
static void pcd_stop (dwc_otg_core_if_t *  core_if  )  [inline, static]
++
++
++ ++

++Stop the PCD. ++

++Helper function for using the PCD callbacks.

++

Parameters:
++ ++ ++
core_if Programming view of DWC_otg controller.
++
++ ++

++Definition at line 160 of file dwc_otg_cil_intr.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
static void pcd_suspend (dwc_otg_core_if_t *  core_if  )  [inline, static]
++
++
++ ++

++Suspend the PCD. ++

++Helper function for using the PCD callbacks.

++

Parameters:
++ ++ ++
core_if Programming view of DWC_otg controller.
++
++ ++

++Definition at line 171 of file dwc_otg_cil_intr.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
static void pcd_resume (dwc_otg_core_if_t *  core_if  )  [inline, static]
++
++
++ ++

++Resume the PCD. ++

++Helper function for using the PCD callbacks.

++

Parameters:
++ ++ ++
core_if Programming view of DWC_otg controller.
++
++ ++

++Definition at line 182 of file dwc_otg_cil_intr.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int32_t dwc_otg_handle_otg_intr (dwc_otg_core_if_t *  core_if  ) 
++
++
++ ++

++This function handles the OTG Interrupts. ++

++It reads the OTG Interrupt Register (GOTGINT) to determine what interrupt has occurred.

++

Parameters:
++ ++ ++
core_if Programming view of DWC_otg controller.
++
++ ++

++Definition at line 196 of file dwc_otg_cil_intr.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int32_t dwc_otg_handle_conn_id_status_change_intr (dwc_otg_core_if_t *  core_if  ) 
++
++
++ ++

++This function handles the Connector ID Status Change Interrupt. ++

++It reads the OTG Interrupt Register (GOTCTL) to determine whether this is a Device to Host Mode transition or a Host Mode to Device Transition.

++This only occurs when the cable is connected/removed from the PHY connector.

++

Parameters:
++ ++ ++
core_if Programming view of DWC_otg controller.
++
++ ++

++Definition at line 399 of file dwc_otg_cil_intr.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int32_t dwc_otg_handle_session_req_intr (dwc_otg_core_if_t *  core_if  ) 
++
++
++ ++

++This interrupt indicates that a device is initiating the Session Request Protocol to request the host to turn on bus power so a new session can begin. ++

++The handler responds by turning on bus power. If the DWC_otg controller is in low power mode, the handler brings the controller out of low power mode before turning on bus power.

++

Parameters:
++ ++ ++
core_if Programming view of DWC_otg controller.
++
++ ++

++Definition at line 441 of file dwc_otg_cil_intr.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void w_wakeup_detected (void *  p  ) 
++
++
++ ++

++ ++

++Definition at line 473 of file dwc_otg_cil_intr.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int32_t dwc_otg_handle_wakeup_detected_intr (dwc_otg_core_if_t *  core_if  ) 
++
++
++ ++

++This interrupt indicates that the DWC_otg controller has detected a resume or remote wakeup sequence. ++

++If the DWC_otg controller is in low power mode, the handler must brings the controller out of low power mode. The controller automatically begins resume signaling. The handler schedules a time to stop resume signaling. ++

++Change to L0 state

++Change to L0 state ++

++Definition at line 510 of file dwc_otg_cil_intr.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int32_t dwc_otg_handle_disconnect_intr (dwc_otg_core_if_t *  core_if  ) 
++
++
++ ++

++This interrupt indicates that a device has been disconnected from the root port. ++

++ ++

++

Todo:
Consolidate this if statement.
++ ++

++Definition at line 589 of file dwc_otg_cil_intr.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int32_t dwc_otg_handle_usb_suspend_intr (dwc_otg_core_if_t *  core_if  ) 
++
++
++ ++

++This interrupt indicates that SUSPEND state has been detected on the USB. ++

++For HNP the USB Suspend interrupt signals the change from "a_peripheral" to "a_host".

++When power management is enabled the core will be put in low power mode. ++

++Definition at line 649 of file dwc_otg_cil_intr.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
static uint32_t dwc_otg_read_common_intr (dwc_otg_core_if_t *  core_if  )  [inline, static]
++
++
++ ++

++This function returns the Core Interrupt register. ++

++ ++

++

Todo:
: The port interrupt occurs while in device mode. Added code to CIL to clear the interrupt for now!
++ ++

++Definition at line 752 of file dwc_otg_cil_intr.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int32_t dwc_otg_handle_common_intr (dwc_otg_core_if_t *  core_if  ) 
++
++
++ ++

++This function should be called on every hardware interrupt. ++

++The common interrupts are those that occur in both Host and Device mode. This handler handles the following interrupts:

    ++
  • Mode Mismatch Interrupt
  • Disconnect Interrupt
  • OTG Interrupt
  • Connector ID Status Change Interrupt
  • Session Request Interrupt.
  • Resume / Remote Wakeup Detected Interrupt.
  • LPM Transaction Received Interrutp
++ ++

++Definition at line 800 of file dwc_otg_cil_intr.c. ++

++

++

Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__core__if_8h-source.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__core__if_8h-source.html 2013-07-26 19:31:20.000000000 +0000 +@@ -0,0 +1,365 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_core_if.h Source File ++ ++ ++ ++ ++
++
++
++
++

dwc_otg_core_if.h

Go to the documentation of this file.
00001 /* ==========================================================================
++00002  * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_core_if.h $
++00003  * $Revision: #4 $
++00004  * $Date: 2008/12/18 $
++00005  * $Change: 1155299 $
++00006  *
++00007  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
++00008  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
++00009  * otherwise expressly agreed to in writing between Synopsys and you.
++00010  *
++00011  * The Software IS NOT an item of Licensed Software or Licensed Product under
++00012  * any End User Software License Agreement or Agreement for Licensed Product
++00013  * with Synopsys or any supplement thereto. You are permitted to use and
++00014  * redistribute this Software in source and binary forms, with or without
++00015  * modification, provided that redistributions of source code must retain this
++00016  * notice. You may not view, use, disclose, copy or distribute this file or
++00017  * any information contained herein except pursuant to this license grant from
++00018  * Synopsys. If you do not agree with this notice, including the disclaimer
++00019  * below, then you are not authorized to use the Software.
++00020  *
++00021  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
++00022  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++00023  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++00024  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
++00025  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++00026  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
++00027  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
++00028  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
++00029  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
++00030  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
++00031  * DAMAGE.
++00032  * ========================================================================== */
++00033 #if !defined(__DWC_CORE_IF_H__)
++00034 #define __DWC_CORE_IF_H__
++00035 
++00036 #include "dwc_os.h"
++00037 
++00042 struct dwc_otg_core_if;
++00043 typedef struct dwc_otg_core_if dwc_otg_core_if_t;
++00044 
++00046 #define MAX_PERIO_FIFOS 15
++00047 
++00048 #define MAX_TX_FIFOS 15
++00049 
++00051 #define MAX_EPS_CHANNELS 16
++00052 
++00053 extern dwc_otg_core_if_t *dwc_otg_cil_init(const uint32_t * _reg_base_addr);
++00054 extern void dwc_otg_core_init(dwc_otg_core_if_t * _core_if);
++00055 extern void dwc_otg_cil_remove(dwc_otg_core_if_t * _core_if);
++00056 
++00057 extern void dwc_otg_enable_global_interrupts(dwc_otg_core_if_t * _core_if);
++00058 extern void dwc_otg_disable_global_interrupts(dwc_otg_core_if_t * _core_if);
++00059 
++00060 extern uint8_t dwc_otg_is_device_mode(dwc_otg_core_if_t * _core_if);
++00061 extern uint8_t dwc_otg_is_host_mode(dwc_otg_core_if_t * _core_if);
++00062 
++00063 extern uint8_t dwc_otg_is_dma_enable(dwc_otg_core_if_t * core_if);
++00064 
++00066 extern int32_t dwc_otg_handle_common_intr(dwc_otg_core_if_t * _core_if);
++00067 
++00078 extern int dwc_otg_set_param_otg_cap(dwc_otg_core_if_t * core_if, int32_t val);
++00079 extern int32_t dwc_otg_get_param_otg_cap(dwc_otg_core_if_t * core_if);
++00080 #define DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE 0
++00081 #define DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE 1
++00082 #define DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE 2
++00083 #define dwc_param_otg_cap_default DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE
++00084 
++00085 extern int dwc_otg_set_param_opt(dwc_otg_core_if_t * core_if, int32_t val);
++00086 extern int32_t dwc_otg_get_param_opt(dwc_otg_core_if_t * core_if);
++00087 #define dwc_param_opt_default 1
++00088 
++00096 extern int dwc_otg_set_param_dma_enable(dwc_otg_core_if_t * core_if,
++00097                                         int32_t val);
++00098 extern int32_t dwc_otg_get_param_dma_enable(dwc_otg_core_if_t * core_if);
++00099 #define dwc_param_dma_enable_default 1
++00100 
++00109 extern int dwc_otg_set_param_dma_desc_enable(dwc_otg_core_if_t * core_if,
++00110                                              int32_t val);
++00111 extern int32_t dwc_otg_get_param_dma_desc_enable(dwc_otg_core_if_t * core_if);
++00112 #define dwc_param_dma_desc_enable_default 1
++00113 
++00117 extern int dwc_otg_set_param_dma_burst_size(dwc_otg_core_if_t * core_if,
++00118                                             int32_t val);
++00119 extern int32_t dwc_otg_get_param_dma_burst_size(dwc_otg_core_if_t * core_if);
++00120 #define dwc_param_dma_burst_size_default 32
++00121 
++00130 extern int dwc_otg_set_param_speed(dwc_otg_core_if_t * core_if, int32_t val);
++00131 extern int32_t dwc_otg_get_param_speed(dwc_otg_core_if_t * core_if);
++00132 #define dwc_param_speed_default 0
++00133 #define DWC_SPEED_PARAM_HIGH 0
++00134 #define DWC_SPEED_PARAM_FULL 1
++00135 
++00141 extern int dwc_otg_set_param_host_support_fs_ls_low_power(dwc_otg_core_if_t *
++00142                                                           core_if, int32_t val);
++00143 extern int32_t dwc_otg_get_param_host_support_fs_ls_low_power(dwc_otg_core_if_t
++00144                                                               * core_if);
++00145 #define dwc_param_host_support_fs_ls_low_power_default 0
++00146 
++00155 extern int dwc_otg_set_param_host_ls_low_power_phy_clk(dwc_otg_core_if_t *
++00156                                                        core_if, int32_t val);
++00157 extern int32_t dwc_otg_get_param_host_ls_low_power_phy_clk(dwc_otg_core_if_t *
++00158                                                            core_if);
++00159 #define dwc_param_host_ls_low_power_phy_clk_default 0
++00160 #define DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ 0
++00161 #define DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ 1
++00162 
++00167 extern int dwc_otg_set_param_enable_dynamic_fifo(dwc_otg_core_if_t * core_if,
++00168                                                  int32_t val);
++00169 extern int32_t dwc_otg_get_param_enable_dynamic_fifo(dwc_otg_core_if_t *
++00170                                                      core_if);
++00171 #define dwc_param_enable_dynamic_fifo_default 1
++00172 
++00179 extern int dwc_otg_set_param_data_fifo_size(dwc_otg_core_if_t * core_if,
++00180                                             int32_t val);
++00181 extern int32_t dwc_otg_get_param_data_fifo_size(dwc_otg_core_if_t * core_if);
++00182 #define dwc_param_data_fifo_size_default 8192
++00183 
++00188 extern int dwc_otg_set_param_dev_rx_fifo_size(dwc_otg_core_if_t * core_if,
++00189                                               int32_t val);
++00190 extern int32_t dwc_otg_get_param_dev_rx_fifo_size(dwc_otg_core_if_t * core_if);
++00191 #define dwc_param_dev_rx_fifo_size_default 1064
++00192 
++00197 extern int dwc_otg_set_param_dev_nperio_tx_fifo_size(dwc_otg_core_if_t *
++00198                                                      core_if, int32_t val);
++00199 extern int32_t dwc_otg_get_param_dev_nperio_tx_fifo_size(dwc_otg_core_if_t *
++00200                                                          core_if);
++00201 #define dwc_param_dev_nperio_tx_fifo_size_default 1024
++00202 
++00207 extern int dwc_otg_set_param_dev_perio_tx_fifo_size(dwc_otg_core_if_t * core_if,
++00208                                                     int32_t val, int fifo_num);
++00209 extern int32_t dwc_otg_get_param_dev_perio_tx_fifo_size(dwc_otg_core_if_t *
++00210                                                         core_if, int fifo_num);
++00211 #define dwc_param_dev_perio_tx_fifo_size_default 256
++00212 
++00217 extern int dwc_otg_set_param_host_rx_fifo_size(dwc_otg_core_if_t * core_if,
++00218                                                int32_t val);
++00219 extern int32_t dwc_otg_get_param_host_rx_fifo_size(dwc_otg_core_if_t * core_if);
++00220 #define dwc_param_host_rx_fifo_size_default 1024
++00221 
++00226 extern int dwc_otg_set_param_host_nperio_tx_fifo_size(dwc_otg_core_if_t *
++00227                                                       core_if, int32_t val);
++00228 extern int32_t dwc_otg_get_param_host_nperio_tx_fifo_size(dwc_otg_core_if_t *
++00229                                                           core_if);
++00230 #define dwc_param_host_nperio_tx_fifo_size_default 1024
++00231 
++00236 extern int dwc_otg_set_param_host_perio_tx_fifo_size(dwc_otg_core_if_t *
++00237                                                      core_if, int32_t val);
++00238 extern int32_t dwc_otg_get_param_host_perio_tx_fifo_size(dwc_otg_core_if_t *
++00239                                                          core_if);
++00240 #define dwc_param_host_perio_tx_fifo_size_default 1024
++00241 
++00245 extern int dwc_otg_set_param_max_transfer_size(dwc_otg_core_if_t * core_if,
++00246                                                int32_t val);
++00247 extern int32_t dwc_otg_get_param_max_transfer_size(dwc_otg_core_if_t * core_if);
++00248 #define dwc_param_max_transfer_size_default 65535
++00249 
++00253 extern int dwc_otg_set_param_max_packet_count(dwc_otg_core_if_t * core_if,
++00254                                               int32_t val);
++00255 extern int32_t dwc_otg_get_param_max_packet_count(dwc_otg_core_if_t * core_if);
++00256 #define dwc_param_max_packet_count_default 511
++00257 
++00262 extern int dwc_otg_set_param_host_channels(dwc_otg_core_if_t * core_if,
++00263                                            int32_t val);
++00264 extern int32_t dwc_otg_get_param_host_channels(dwc_otg_core_if_t * core_if);
++00265 #define dwc_param_host_channels_default 12
++00266 
++00273 extern int dwc_otg_set_param_dev_endpoints(dwc_otg_core_if_t * core_if,
++00274                                            int32_t val);
++00275 extern int32_t dwc_otg_get_param_dev_endpoints(dwc_otg_core_if_t * core_if);
++00276 #define dwc_param_dev_endpoints_default 6
++00277 
++00286 extern int dwc_otg_set_param_phy_type(dwc_otg_core_if_t * core_if, int32_t val);
++00287 extern int32_t dwc_otg_get_param_phy_type(dwc_otg_core_if_t * core_if);
++00288 #define DWC_PHY_TYPE_PARAM_FS 0
++00289 #define DWC_PHY_TYPE_PARAM_UTMI 1
++00290 #define DWC_PHY_TYPE_PARAM_ULPI 2
++00291 #define dwc_param_phy_type_default DWC_PHY_TYPE_PARAM_UTMI
++00292 
++00304 extern int dwc_otg_set_param_phy_utmi_width(dwc_otg_core_if_t * core_if,
++00305                                             int32_t val);
++00306 extern int32_t dwc_otg_get_param_phy_utmi_width(dwc_otg_core_if_t * core_if);
++00307 #define dwc_param_phy_utmi_width_default 16
++00308 
++00319 extern int dwc_otg_set_param_phy_ulpi_ddr(dwc_otg_core_if_t * core_if,
++00320                                           int32_t val);
++00321 extern int32_t dwc_otg_get_param_phy_ulpi_ddr(dwc_otg_core_if_t * core_if);
++00322 #define dwc_param_phy_ulpi_ddr_default 0
++00323 
++00328 extern int dwc_otg_set_param_phy_ulpi_ext_vbus(dwc_otg_core_if_t * core_if,
++00329                                                int32_t val);
++00330 extern int32_t dwc_otg_get_param_phy_ulpi_ext_vbus(dwc_otg_core_if_t * core_if);
++00331 #define DWC_PHY_ULPI_INTERNAL_VBUS 0
++00332 #define DWC_PHY_ULPI_EXTERNAL_VBUS 1
++00333 #define dwc_param_phy_ulpi_ext_vbus_default DWC_PHY_ULPI_INTERNAL_VBUS
++00334 
++00341 extern int dwc_otg_set_param_i2c_enable(dwc_otg_core_if_t * core_if,
++00342                                         int32_t val);
++00343 extern int32_t dwc_otg_get_param_i2c_enable(dwc_otg_core_if_t * core_if);
++00344 #define dwc_param_i2c_enable_default 0
++00345 
++00346 extern int dwc_otg_set_param_ulpi_fs_ls(dwc_otg_core_if_t * core_if,
++00347                                         int32_t val);
++00348 extern int32_t dwc_otg_get_param_ulpi_fs_ls(dwc_otg_core_if_t * core_if);
++00349 #define dwc_param_ulpi_fs_ls_default 0
++00350 
++00351 extern int dwc_otg_set_param_ts_dline(dwc_otg_core_if_t * core_if, int32_t val);
++00352 extern int32_t dwc_otg_get_param_ts_dline(dwc_otg_core_if_t * core_if);
++00353 #define dwc_param_ts_dline_default 0
++00354 
++00361 extern int dwc_otg_set_param_en_multiple_tx_fifo(dwc_otg_core_if_t * core_if,
++00362                                                  int32_t val);
++00363 extern int32_t dwc_otg_get_param_en_multiple_tx_fifo(dwc_otg_core_if_t *
++00364                                                      core_if);
++00365 #define dwc_param_en_multiple_tx_fifo_default 1
++00366 
++00371 extern int dwc_otg_set_param_dev_tx_fifo_size(dwc_otg_core_if_t * core_if,
++00372                                               int fifo_num, int32_t val);
++00373 extern int32_t dwc_otg_get_param_dev_tx_fifo_size(dwc_otg_core_if_t * core_if,
++00374                                                   int fifo_num);
++00375 #define dwc_param_dev_tx_fifo_size_default 256
++00376 
++00382 extern int dwc_otg_set_param_thr_ctl(dwc_otg_core_if_t * core_if, int32_t val);
++00383 extern int32_t dwc_otg_get_thr_ctl(dwc_otg_core_if_t * core_if, int fifo_num);
++00384 #define dwc_param_thr_ctl_default 0
++00385 
++00389 extern int dwc_otg_set_param_tx_thr_length(dwc_otg_core_if_t * core_if,
++00390                                            int32_t val);
++00391 extern int32_t dwc_otg_get_tx_thr_length(dwc_otg_core_if_t * core_if);
++00392 #define dwc_param_tx_thr_length_default 64
++00393 
++00397 extern int dwc_otg_set_param_rx_thr_length(dwc_otg_core_if_t * core_if,
++00398                                            int32_t val);
++00399 extern int32_t dwc_otg_get_rx_thr_length(dwc_otg_core_if_t * core_if);
++00400 #define dwc_param_rx_thr_length_default 64
++00401 
++00405 extern int dwc_otg_set_param_lpm_enable(dwc_otg_core_if_t * core_if,
++00406                                         int32_t val);
++00407 extern int32_t dwc_otg_get_param_lpm_enable(dwc_otg_core_if_t * core_if);
++00408 #define dwc_param_lpm_enable_default 1
++00409 
++00413 extern int dwc_otg_set_param_pti_enable(dwc_otg_core_if_t * core_if,
++00414                                         int32_t val);
++00415 extern int32_t dwc_otg_get_param_pti_enable(dwc_otg_core_if_t * core_if);
++00416 #define dwc_param_pti_enable_default 0
++00417 
++00421 extern int dwc_otg_set_param_mpi_enable(dwc_otg_core_if_t * core_if,
++00422                                         int32_t val);
++00423 extern int32_t dwc_otg_get_param_mpi_enable(dwc_otg_core_if_t * core_if);
++00424 #define dwc_param_mpi_enable_default 0
++00425 
++00429 extern int dwc_otg_set_param_ic_usb_cap(dwc_otg_core_if_t * core_if,
++00430                                         int32_t val);
++00431 extern int32_t dwc_otg_get_param_ic_usb_cap(dwc_otg_core_if_t * core_if);
++00432 #define dwc_param_ic_usb_cap_default 0
++00433 
++00434 extern int dwc_otg_set_param_ahb_thr_ratio(dwc_otg_core_if_t * core_if, int32_t val);
++00435 extern int32_t dwc_otg_get_param_ahb_thr_ratio(dwc_otg_core_if_t * core_if);
++00436 #define dwc_param_ahb_thr_ratio_default 0
++00437 
++00445 extern void dwc_otg_dump_dev_registers(dwc_otg_core_if_t * _core_if);
++00446 extern void dwc_otg_dump_spram(dwc_otg_core_if_t * _core_if);
++00447 extern void dwc_otg_dump_host_registers(dwc_otg_core_if_t * _core_if);
++00448 extern void dwc_otg_dump_global_registers(dwc_otg_core_if_t * _core_if);
++00449 
++00453 extern uint32_t dwc_otg_get_hnpstatus(dwc_otg_core_if_t * core_if);
++00454 
++00458 extern uint32_t dwc_otg_get_srpstatus(dwc_otg_core_if_t * core_if);
++00459 
++00463 extern void dwc_otg_set_hnpreq(dwc_otg_core_if_t * core_if, uint32_t val);
++00464 
++00468 extern uint32_t dwc_otg_get_gsnpsid(dwc_otg_core_if_t * core_if);
++00469 
++00474 extern uint32_t dwc_otg_get_mode(dwc_otg_core_if_t * core_if);
++00475 
++00479 extern uint32_t dwc_otg_get_hnpcapable(dwc_otg_core_if_t * core_if);
++00483 extern void dwc_otg_set_hnpcapable(dwc_otg_core_if_t * core_if, uint32_t val);
++00484 
++00488 extern uint32_t dwc_otg_get_srpcapable(dwc_otg_core_if_t * core_if);
++00492 extern void dwc_otg_set_srpcapable(dwc_otg_core_if_t * core_if, uint32_t val);
++00493 
++00497 extern uint32_t dwc_otg_get_devspeed(dwc_otg_core_if_t * core_if);
++00501 extern void dwc_otg_set_devspeed(dwc_otg_core_if_t * core_if, uint32_t val);
++00502 
++00506 extern uint32_t dwc_otg_get_busconnected(dwc_otg_core_if_t * core_if);
++00507 
++00511 extern uint32_t dwc_otg_get_enumspeed(dwc_otg_core_if_t * core_if);
++00512 
++00516 extern uint32_t dwc_otg_get_prtpower(dwc_otg_core_if_t * core_if);
++00520 extern void dwc_otg_set_prtpower(dwc_otg_core_if_t * core_if, uint32_t val);
++00521 
++00525 extern uint32_t dwc_otg_get_prtsuspend(dwc_otg_core_if_t * core_if);
++00529 extern void dwc_otg_set_prtsuspend(dwc_otg_core_if_t * core_if, uint32_t val);
++00530 
++00535 extern void dwc_otg_set_prtresume(dwc_otg_core_if_t * core_if, uint32_t val);
++00536 
++00540 extern uint32_t dwc_otg_get_remotewakesig(dwc_otg_core_if_t * core_if);
++00541 
++00545 extern uint32_t dwc_otg_get_lpm_portsleepstatus(dwc_otg_core_if_t * core_if);
++00546 
++00550 extern uint32_t dwc_otg_get_lpm_remotewakeenabled(dwc_otg_core_if_t * core_if);
++00551 
++00555 extern uint32_t dwc_otg_get_lpmresponse(dwc_otg_core_if_t * core_if);
++00559 extern void dwc_otg_set_lpmresponse(dwc_otg_core_if_t * core_if, uint32_t val);
++00560 
++00564 extern uint32_t dwc_otg_get_hsic_connect(dwc_otg_core_if_t * core_if);
++00568 extern void dwc_otg_set_hsic_connect(dwc_otg_core_if_t * core_if, uint32_t val);
++00569 
++00573 extern uint32_t dwc_otg_get_inv_sel_hsic(dwc_otg_core_if_t * core_if);
++00577 extern void dwc_otg_set_inv_sel_hsic(dwc_otg_core_if_t * core_if, uint32_t val);
++00578 
++00579 /*
++00580  * Some functions for accessing registers
++00581  */
++00582 
++00586 extern uint32_t dwc_otg_get_gotgctl(dwc_otg_core_if_t * core_if);
++00587 extern void dwc_otg_set_gotgctl(dwc_otg_core_if_t * core_if, uint32_t val);
++00588 
++00592 extern uint32_t dwc_otg_get_gusbcfg(dwc_otg_core_if_t * core_if);
++00593 extern void dwc_otg_set_gusbcfg(dwc_otg_core_if_t * core_if, uint32_t val);
++00594 
++00598 extern uint32_t dwc_otg_get_grxfsiz(dwc_otg_core_if_t * core_if);
++00599 extern void dwc_otg_set_grxfsiz(dwc_otg_core_if_t * core_if, uint32_t val);
++00600 
++00604 extern uint32_t dwc_otg_get_gnptxfsiz(dwc_otg_core_if_t * core_if);
++00605 extern void dwc_otg_set_gnptxfsiz(dwc_otg_core_if_t * core_if, uint32_t val);
++00606 
++00607 extern uint32_t dwc_otg_get_gpvndctl(dwc_otg_core_if_t * core_if);
++00608 extern void dwc_otg_set_gpvndctl(dwc_otg_core_if_t * core_if, uint32_t val);
++00609 
++00613 extern uint32_t dwc_otg_get_ggpio(dwc_otg_core_if_t * core_if);
++00614 extern void dwc_otg_set_ggpio(dwc_otg_core_if_t * core_if, uint32_t val);
++00615 
++00619 extern uint32_t dwc_otg_get_guid(dwc_otg_core_if_t * core_if);
++00620 extern void dwc_otg_set_guid(dwc_otg_core_if_t * core_if, uint32_t val);
++00621 
++00625 extern uint32_t dwc_otg_get_hprt0(dwc_otg_core_if_t * core_if);
++00626 extern void dwc_otg_set_hprt0(dwc_otg_core_if_t * core_if, uint32_t val);
++00627 
++00631 extern uint32_t dwc_otg_get_hptxfsiz(dwc_otg_core_if_t * core_if);
++00632 
++00635 #endif                          /* __DWC_CORE_IF_H__ */
++
Generated on Tue May 5 02:22:48 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__core__if_8h.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__core__if_8h.html 2013-07-26 19:31:20.000000000 +0000 +@@ -0,0 +1,1730 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_core_if.h File Reference ++ ++ ++ ++ ++
++
++
++
++

dwc_otg_core_if.h File Reference

This file defines DWC_OTG Core API. More... ++

++#include "dwc_os.h"
++ ++

++Go to the source code of this file. ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++

OTG Core Parameters

++#define DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE   0
++#define DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE   1
++#define DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE   2
++#define dwc_param_otg_cap_default   DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE
++#define dwc_param_opt_default   1
++#define dwc_param_dma_enable_default   1
++#define dwc_param_dma_desc_enable_default   1
++#define dwc_param_dma_burst_size_default   32
++#define dwc_param_speed_default   0
++#define DWC_SPEED_PARAM_HIGH   0
++#define DWC_SPEED_PARAM_FULL   1
++#define dwc_param_host_support_fs_ls_low_power_default   0
++#define dwc_param_host_ls_low_power_phy_clk_default   0
++#define DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ   0
++#define DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ   1
++#define dwc_param_enable_dynamic_fifo_default   1
++#define dwc_param_data_fifo_size_default   8192
++#define dwc_param_dev_rx_fifo_size_default   1064
++#define dwc_param_dev_nperio_tx_fifo_size_default   1024
++#define dwc_param_dev_perio_tx_fifo_size_default   256
++#define dwc_param_host_rx_fifo_size_default   1024
++#define dwc_param_host_nperio_tx_fifo_size_default   1024
++#define dwc_param_host_perio_tx_fifo_size_default   1024
++#define dwc_param_max_transfer_size_default   65535
++#define dwc_param_max_packet_count_default   511
++#define dwc_param_host_channels_default   12
++#define dwc_param_dev_endpoints_default   6
++#define DWC_PHY_TYPE_PARAM_FS   0
++#define DWC_PHY_TYPE_PARAM_UTMI   1
++#define DWC_PHY_TYPE_PARAM_ULPI   2
++#define dwc_param_phy_type_default   DWC_PHY_TYPE_PARAM_UTMI
++#define dwc_param_phy_utmi_width_default   16
++#define dwc_param_phy_ulpi_ddr_default   0
++#define DWC_PHY_ULPI_INTERNAL_VBUS   0
++#define DWC_PHY_ULPI_EXTERNAL_VBUS   1
++#define dwc_param_phy_ulpi_ext_vbus_default   DWC_PHY_ULPI_INTERNAL_VBUS
++#define dwc_param_i2c_enable_default   0
++#define dwc_param_ulpi_fs_ls_default   0
++#define dwc_param_ts_dline_default   0
++#define dwc_param_en_multiple_tx_fifo_default   1
++#define dwc_param_dev_tx_fifo_size_default   256
++#define dwc_param_thr_ctl_default   0
++#define dwc_param_tx_thr_length_default   64
++#define dwc_param_rx_thr_length_default   64
++#define dwc_param_lpm_enable_default   1
++#define dwc_param_pti_enable_default   0
++#define dwc_param_mpi_enable_default   0
++#define dwc_param_ic_usb_cap_default   0
++#define dwc_param_ahb_thr_ratio_default   0
int dwc_otg_set_param_otg_cap (dwc_otg_core_if_t *core_if, int32_t val)
 Specifies the OTG capabilities.
++int32_t dwc_otg_get_param_otg_cap (dwc_otg_core_if_t *core_if)
++int dwc_otg_set_param_opt (dwc_otg_core_if_t *core_if, int32_t val)
++int32_t dwc_otg_get_param_opt (dwc_otg_core_if_t *core_if)
int dwc_otg_set_param_dma_enable (dwc_otg_core_if_t *core_if, int32_t val)
 Specifies whether to use slave or DMA mode for accessing the data FIFOs.
++int32_t dwc_otg_get_param_dma_enable (dwc_otg_core_if_t *core_if)
int dwc_otg_set_param_dma_desc_enable (dwc_otg_core_if_t *core_if, int32_t val)
 When DMA mode is enabled specifies whether to use address DMA or DMA Descritor mode for accessing the data FIFOs in device mode.
++int32_t dwc_otg_get_param_dma_desc_enable (dwc_otg_core_if_t *core_if)
int dwc_otg_set_param_dma_burst_size (dwc_otg_core_if_t *core_if, int32_t val)
 The DMA Burst size (applicable only for External DMA Mode).
++int32_t dwc_otg_get_param_dma_burst_size (dwc_otg_core_if_t *core_if)
int dwc_otg_set_param_speed (dwc_otg_core_if_t *core_if, int32_t val)
 Specifies the maximum speed of operation in host and device mode.
++int32_t dwc_otg_get_param_speed (dwc_otg_core_if_t *core_if)
int dwc_otg_set_param_host_support_fs_ls_low_power (dwc_otg_core_if_t *core_if, int32_t val)
 Specifies whether low power mode is supported when attached to a Full Speed or Low Speed device in host mode.
++int32_t dwc_otg_get_param_host_support_fs_ls_low_power (dwc_otg_core_if_t *core_if)
int dwc_otg_set_param_host_ls_low_power_phy_clk (dwc_otg_core_if_t *core_if, int32_t val)
 Specifies the PHY clock rate in low power mode when connected to a Low Speed device in host mode.
++int32_t dwc_otg_get_param_host_ls_low_power_phy_clk (dwc_otg_core_if_t *core_if)
++int dwc_otg_set_param_enable_dynamic_fifo (dwc_otg_core_if_t *core_if, int32_t val)
 0 - Use cC FIFO size parameters 1 - Allow dynamic FIFO sizing (default)
++int32_t dwc_otg_get_param_enable_dynamic_fifo (dwc_otg_core_if_t *core_if)
int dwc_otg_set_param_data_fifo_size (dwc_otg_core_if_t *core_if, int32_t val)
 Total number of 4-byte words in the data FIFO memory.
++int32_t dwc_otg_get_param_data_fifo_size (dwc_otg_core_if_t *core_if)
int dwc_otg_set_param_dev_rx_fifo_size (dwc_otg_core_if_t *core_if, int32_t val)
 Number of 4-byte words in the Rx FIFO in device mode when dynamic FIFO sizing is enabled.
++int32_t dwc_otg_get_param_dev_rx_fifo_size (dwc_otg_core_if_t *core_if)
int dwc_otg_set_param_dev_nperio_tx_fifo_size (dwc_otg_core_if_t *core_if, int32_t val)
 Number of 4-byte words in the non-periodic Tx FIFO in device mode when dynamic FIFO sizing is enabled.
++int32_t dwc_otg_get_param_dev_nperio_tx_fifo_size (dwc_otg_core_if_t *core_if)
int dwc_otg_set_param_dev_perio_tx_fifo_size (dwc_otg_core_if_t *core_if, int32_t val, int fifo_num)
 Number of 4-byte words in each of the periodic Tx FIFOs in device mode when dynamic FIFO sizing is enabled.
++int32_t dwc_otg_get_param_dev_perio_tx_fifo_size (dwc_otg_core_if_t *core_if, int fifo_num)
int dwc_otg_set_param_host_rx_fifo_size (dwc_otg_core_if_t *core_if, int32_t val)
 Number of 4-byte words in the Rx FIFO in host mode when dynamic FIFO sizing is enabled.
++int32_t dwc_otg_get_param_host_rx_fifo_size (dwc_otg_core_if_t *core_if)
int dwc_otg_set_param_host_nperio_tx_fifo_size (dwc_otg_core_if_t *core_if, int32_t val)
 Number of 4-byte words in the non-periodic Tx FIFO in host mode when Dynamic FIFO sizing is enabled in the core.
++int32_t dwc_otg_get_param_host_nperio_tx_fifo_size (dwc_otg_core_if_t *core_if)
int dwc_otg_set_param_host_perio_tx_fifo_size (dwc_otg_core_if_t *core_if, int32_t val)
 Number of 4-byte words in the host periodic Tx FIFO when dynamic FIFO sizing is enabled.
++int32_t dwc_otg_get_param_host_perio_tx_fifo_size (dwc_otg_core_if_t *core_if)
int dwc_otg_set_param_max_transfer_size (dwc_otg_core_if_t *core_if, int32_t val)
 The maximum transfer size supported in bytes.
++int32_t dwc_otg_get_param_max_transfer_size (dwc_otg_core_if_t *core_if)
int dwc_otg_set_param_max_packet_count (dwc_otg_core_if_t *core_if, int32_t val)
 The maximum number of packets in a transfer.
++int32_t dwc_otg_get_param_max_packet_count (dwc_otg_core_if_t *core_if)
int dwc_otg_set_param_host_channels (dwc_otg_core_if_t *core_if, int32_t val)
 The number of host channel registers to use.
++int32_t dwc_otg_get_param_host_channels (dwc_otg_core_if_t *core_if)
int dwc_otg_set_param_dev_endpoints (dwc_otg_core_if_t *core_if, int32_t val)
 The number of endpoints in addition to EP0 available for device mode operations.
++int32_t dwc_otg_get_param_dev_endpoints (dwc_otg_core_if_t *core_if)
int dwc_otg_set_param_phy_type (dwc_otg_core_if_t *core_if, int32_t val)
 Specifies the type of PHY interface to use.
++int32_t dwc_otg_get_param_phy_type (dwc_otg_core_if_t *core_if)
int dwc_otg_set_param_phy_utmi_width (dwc_otg_core_if_t *core_if, int32_t val)
 Specifies the UTMI+ Data Width.
++int32_t dwc_otg_get_param_phy_utmi_width (dwc_otg_core_if_t *core_if)
int dwc_otg_set_param_phy_ulpi_ddr (dwc_otg_core_if_t *core_if, int32_t val)
 Specifies whether the ULPI operates at double or single data rate.
++int32_t dwc_otg_get_param_phy_ulpi_ddr (dwc_otg_core_if_t *core_if)
++int dwc_otg_set_param_phy_ulpi_ext_vbus (dwc_otg_core_if_t *core_if, int32_t val)
 Specifies whether to use the internal or external supply to drive the vbus with a ULPI phy.
++int32_t dwc_otg_get_param_phy_ulpi_ext_vbus (dwc_otg_core_if_t *core_if)
int dwc_otg_set_param_i2c_enable (dwc_otg_core_if_t *core_if, int32_t val)
 Specifies whether to use the I2Cinterface for full speed PHY.
++int32_t dwc_otg_get_param_i2c_enable (dwc_otg_core_if_t *core_if)
++int dwc_otg_set_param_ulpi_fs_ls (dwc_otg_core_if_t *core_if, int32_t val)
++int32_t dwc_otg_get_param_ulpi_fs_ls (dwc_otg_core_if_t *core_if)
++int dwc_otg_set_param_ts_dline (dwc_otg_core_if_t *core_if, int32_t val)
++int32_t dwc_otg_get_param_ts_dline (dwc_otg_core_if_t *core_if)
++int dwc_otg_set_param_en_multiple_tx_fifo (dwc_otg_core_if_t *core_if, int32_t val)
 Specifies whether dedicated transmit FIFOs are enabled for non periodic IN endpoints in device mode 0 - No 1 - Yes.
++int32_t dwc_otg_get_param_en_multiple_tx_fifo (dwc_otg_core_if_t *core_if)
int dwc_otg_set_param_dev_tx_fifo_size (dwc_otg_core_if_t *core_if, int fifo_num, int32_t val)
 Number of 4-byte words in each of the Tx FIFOs in device mode when dynamic FIFO sizing is enabled.
++int32_t dwc_otg_get_param_dev_tx_fifo_size (dwc_otg_core_if_t *core_if, int fifo_num)
++int dwc_otg_set_param_thr_ctl (dwc_otg_core_if_t *core_if, int32_t val)
 Thresholding enable flag- bit 0 - enable non-ISO Tx thresholding bit 1 - enable ISO Tx thresholding bit 2 - enable Rx thresholding.
++int32_t dwc_otg_get_thr_ctl (dwc_otg_core_if_t *core_if, int fifo_num)
++int dwc_otg_set_param_tx_thr_length (dwc_otg_core_if_t *core_if, int32_t val)
 Thresholding length for Tx FIFOs in 32 bit DWORDs.
++int32_t dwc_otg_get_tx_thr_length (dwc_otg_core_if_t *core_if)
++int dwc_otg_set_param_rx_thr_length (dwc_otg_core_if_t *core_if, int32_t val)
 Thresholding length for Rx FIFOs in 32 bit DWORDs.
++int32_t dwc_otg_get_rx_thr_length (dwc_otg_core_if_t *core_if)
++int dwc_otg_set_param_lpm_enable (dwc_otg_core_if_t *core_if, int32_t val)
 Specifies whether LPM (Link Power Management) support is enabled.
++int32_t dwc_otg_get_param_lpm_enable (dwc_otg_core_if_t *core_if)
++int dwc_otg_set_param_pti_enable (dwc_otg_core_if_t *core_if, int32_t val)
 Specifies whether PTI enhancement is enabled.
++int32_t dwc_otg_get_param_pti_enable (dwc_otg_core_if_t *core_if)
++int dwc_otg_set_param_mpi_enable (dwc_otg_core_if_t *core_if, int32_t val)
 Specifies whether MPI enhancement is enabled.
++int32_t dwc_otg_get_param_mpi_enable (dwc_otg_core_if_t *core_if)
++int dwc_otg_set_param_ic_usb_cap (dwc_otg_core_if_t *core_if, int32_t val)
 Specifies whether IC_USB capability is enabled.
++int32_t dwc_otg_get_param_ic_usb_cap (dwc_otg_core_if_t *core_if)
++int dwc_otg_set_param_ahb_thr_ratio (dwc_otg_core_if_t *core_if, int32_t val)
++int32_t dwc_otg_get_param_ahb_thr_ratio (dwc_otg_core_if_t *core_if)

Access to registers and bit-fields

void dwc_otg_dump_dev_registers (dwc_otg_core_if_t *_core_if)
 Dump core registers and SPRAM.
void dwc_otg_dump_spram (dwc_otg_core_if_t *_core_if)
 This functions reads the SPRAM and prints its content.
void dwc_otg_dump_host_registers (dwc_otg_core_if_t *_core_if)
 This function reads the host registers and prints them.
void dwc_otg_dump_global_registers (dwc_otg_core_if_t *_core_if)
 This function reads the core global registers and prints them.
++uint32_t dwc_otg_get_hnpstatus (dwc_otg_core_if_t *core_if)
 Get host negotiation status.
++uint32_t dwc_otg_get_srpstatus (dwc_otg_core_if_t *core_if)
 Get srp status.
++void dwc_otg_set_hnpreq (dwc_otg_core_if_t *core_if, uint32_t val)
 Set hnpreq bit in the GOTGCTL register.
++uint32_t dwc_otg_get_gsnpsid (dwc_otg_core_if_t *core_if)
 Get Content of SNPSID register.
uint32_t dwc_otg_get_mode (dwc_otg_core_if_t *core_if)
 Get current mode.
++uint32_t dwc_otg_get_hnpcapable (dwc_otg_core_if_t *core_if)
 Get value of hnpcapable field in the GUSBCFG register.
++void dwc_otg_set_hnpcapable (dwc_otg_core_if_t *core_if, uint32_t val)
 Set value of hnpcapable field in the GUSBCFG register.
++uint32_t dwc_otg_get_srpcapable (dwc_otg_core_if_t *core_if)
 Get value of srpcapable field in the GUSBCFG register.
++void dwc_otg_set_srpcapable (dwc_otg_core_if_t *core_if, uint32_t val)
 Set value of srpcapable field in the GUSBCFG register.
++uint32_t dwc_otg_get_devspeed (dwc_otg_core_if_t *core_if)
 Get value of devspeed field in the DCFG register.
++void dwc_otg_set_devspeed (dwc_otg_core_if_t *core_if, uint32_t val)
 Set value of devspeed field in the DCFG register.
++uint32_t dwc_otg_get_busconnected (dwc_otg_core_if_t *core_if)
 Get the value of busconnected field from the HPRT0 register.
++uint32_t dwc_otg_get_enumspeed (dwc_otg_core_if_t *core_if)
 Gets the device enumeration Speed.
++uint32_t dwc_otg_get_prtpower (dwc_otg_core_if_t *core_if)
 Get value of prtpwr field from the HPRT0 register.
++void dwc_otg_set_prtpower (dwc_otg_core_if_t *core_if, uint32_t val)
 Set value of prtpwr field from the HPRT0 register.
++uint32_t dwc_otg_get_prtsuspend (dwc_otg_core_if_t *core_if)
 Get value of prtsusp field from the HPRT0 regsiter.
++void dwc_otg_set_prtsuspend (dwc_otg_core_if_t *core_if, uint32_t val)
 Set value of prtpwr field from the HPRT0 register.
++void dwc_otg_set_prtresume (dwc_otg_core_if_t *core_if, uint32_t val)
 Set value of prtres field from the HPRT0 register FIXME Remove?
++uint32_t dwc_otg_get_remotewakesig (dwc_otg_core_if_t *core_if)
 Get value of rmtwkupsig bit in DCTL register.
++uint32_t dwc_otg_get_lpm_portsleepstatus (dwc_otg_core_if_t *core_if)
 Get value of prt_sleep_sts field from the GLPMCFG register.
++uint32_t dwc_otg_get_lpm_remotewakeenabled (dwc_otg_core_if_t *core_if)
 Get value of rem_wkup_en field from the GLPMCFG register.
++uint32_t dwc_otg_get_lpmresponse (dwc_otg_core_if_t *core_if)
 Get value of appl_resp field from the GLPMCFG register.
++void dwc_otg_set_lpmresponse (dwc_otg_core_if_t *core_if, uint32_t val)
 Set value of appl_resp field from the GLPMCFG register.
++uint32_t dwc_otg_get_hsic_connect (dwc_otg_core_if_t *core_if)
 Get value of hsic_connect field from the GLPMCFG register.
++void dwc_otg_set_hsic_connect (dwc_otg_core_if_t *core_if, uint32_t val)
 Set value of hsic_connect field from the GLPMCFG register.
++uint32_t dwc_otg_get_inv_sel_hsic (dwc_otg_core_if_t *core_if)
 Get value of inv_sel_hsic field from the GLPMCFG register.
++void dwc_otg_set_inv_sel_hsic (dwc_otg_core_if_t *core_if, uint32_t val)
 Set value of inv_sel_hsic field from the GLPMFG register.
++uint32_t dwc_otg_get_gotgctl (dwc_otg_core_if_t *core_if)
 GOTGCTL register.
++void dwc_otg_set_gotgctl (dwc_otg_core_if_t *core_if, uint32_t val)
++uint32_t dwc_otg_get_gusbcfg (dwc_otg_core_if_t *core_if)
 GUSBCFG register.
++void dwc_otg_set_gusbcfg (dwc_otg_core_if_t *core_if, uint32_t val)
++uint32_t dwc_otg_get_grxfsiz (dwc_otg_core_if_t *core_if)
 GRXFSIZ register.
++void dwc_otg_set_grxfsiz (dwc_otg_core_if_t *core_if, uint32_t val)
++uint32_t dwc_otg_get_gnptxfsiz (dwc_otg_core_if_t *core_if)
 GNPTXFSIZ register.
++void dwc_otg_set_gnptxfsiz (dwc_otg_core_if_t *core_if, uint32_t val)
++uint32_t dwc_otg_get_gpvndctl (dwc_otg_core_if_t *core_if)
++void dwc_otg_set_gpvndctl (dwc_otg_core_if_t *core_if, uint32_t val)
++uint32_t dwc_otg_get_ggpio (dwc_otg_core_if_t *core_if)
 GGPIO register.
++void dwc_otg_set_ggpio (dwc_otg_core_if_t *core_if, uint32_t val)
++uint32_t dwc_otg_get_guid (dwc_otg_core_if_t *core_if)
 GUID register.
++void dwc_otg_set_guid (dwc_otg_core_if_t *core_if, uint32_t val)
++uint32_t dwc_otg_get_hprt0 (dwc_otg_core_if_t *core_if)
 HPRT0 register.
++void dwc_otg_set_hprt0 (dwc_otg_core_if_t *core_if, uint32_t val)
++uint32_t dwc_otg_get_hptxfsiz (dwc_otg_core_if_t *core_if)
 GHPTXFSIZE.

Defines

++#define __DWC_CORE_IF_H__
++#define MAX_PERIO_FIFOS   15
 Maximum number of Periodic FIFOs.
++#define MAX_TX_FIFOS   15
 Maximum number of Periodic FIFOs.
++#define MAX_EPS_CHANNELS   16
 Maximum number of Endpoints/HostChannels.

Typedefs

++typedef dwc_otg_core_if dwc_otg_core_if_t

Functions

dwc_otg_core_if_t * dwc_otg_cil_init (const uint32_t *_reg_base_addr)
 This function is called to initialize the DWC_otg CSR data structures.
void dwc_otg_core_init (dwc_otg_core_if_t *_core_if)
 This function initializes the DWC_otg controller registers and prepares the core for device mode or host mode operation.
void dwc_otg_cil_remove (dwc_otg_core_if_t *_core_if)
 This function frees the structures allocated by dwc_otg_cil_init().
void dwc_otg_enable_global_interrupts (dwc_otg_core_if_t *_core_if)
 This function enables the controller's Global Interrupt in the AHB Config register.
void dwc_otg_disable_global_interrupts (dwc_otg_core_if_t *_core_if)
 This function disables the controller's Global Interrupt in the AHB Config register.
++uint8_t dwc_otg_is_device_mode (dwc_otg_core_if_t *_core_if)
++uint8_t dwc_otg_is_host_mode (dwc_otg_core_if_t *_core_if)
++uint8_t dwc_otg_is_dma_enable (dwc_otg_core_if_t *core_if)
int32_t dwc_otg_handle_common_intr (dwc_otg_core_if_t *_core_if)
 This function should be called on every hardware interrupt.
++

Detailed Description

++This file defines DWC_OTG Core API. ++

++ ++

++Definition in file dwc_otg_core_if.h.

Function Documentation

++ ++
++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
dwc_otg_core_if_t* dwc_otg_cil_init (const uint32_t *  reg_base_addr  ) 
++
++
++ ++

++This function is called to initialize the DWC_otg CSR data structures. ++

++The register addresses in the device and host structures are initialized from the base address supplied by the caller. The calling function must make the OS calls to get the base address of the DWC_otg controller registers. The core_params argument holds the parameters that specify how the core should be configured.

++

Parameters:
++ ++ ++
reg_base_addr Base address of DWC_otg core registers
++
++ ++

++Definition at line 78 of file dwc_otg_cil.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_otg_core_init (dwc_otg_core_if_t *  core_if  ) 
++
++
++ ++

++This function initializes the DWC_otg controller registers and prepares the core for device mode or host mode operation. ++

++

Parameters:
++ ++ ++
core_if Programming view of the DWC_otg controller
++
++ ++

++Definition at line 467 of file dwc_otg_cil.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_otg_cil_remove (dwc_otg_core_if_t *  core_if  ) 
++
++
++ ++

++This function frees the structures allocated by dwc_otg_cil_init(). ++

++

Parameters:
++ ++ ++
core_if The core interface pointer returned from dwc_otg_cil_init().
++
++ ++

++Definition at line 265 of file dwc_otg_cil.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_otg_enable_global_interrupts (dwc_otg_core_if_t *  core_if  ) 
++
++
++ ++

++This function enables the controller's Global Interrupt in the AHB Config register. ++

++

Parameters:
++ ++ ++
core_if Programming view of DWC_otg controller.
++
++ ++

++Definition at line 292 of file dwc_otg_cil.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_otg_disable_global_interrupts (dwc_otg_core_if_t *  core_if  ) 
++
++
++ ++

++This function disables the controller's Global Interrupt in the AHB Config register. ++

++

Parameters:
++ ++ ++
core_if Programming view of DWC_otg controller.
++
++ ++

++Definition at line 305 of file dwc_otg_cil.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int32_t dwc_otg_handle_common_intr (dwc_otg_core_if_t *  core_if  ) 
++
++
++ ++

++This function should be called on every hardware interrupt. ++

++The common interrupts are those that occur in both Host and Device mode. This handler handles the following interrupts:

    ++
  • Mode Mismatch Interrupt
  • Disconnect Interrupt
  • OTG Interrupt
  • Connector ID Status Change Interrupt
  • Session Request Interrupt.
  • Resume / Remote Wakeup Detected Interrupt.
  • LPM Transaction Received Interrutp
++ ++

++Definition at line 800 of file dwc_otg_cil_intr.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int dwc_otg_set_param_otg_cap (dwc_otg_core_if_t *  core_if,
int32_t  val 
)
++
++
++ ++

++Specifies the OTG capabilities. ++

++The driver will automatically detect the value for this parameter if none is specified. 0 - HNP and SRP capable (default) 1 - SRP Only capable 2 - No HNP/SRP capable ++

++Definition at line 4056 of file dwc_otg_cil.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int dwc_otg_set_param_dma_enable (dwc_otg_core_if_t *  core_if,
int32_t  val 
)
++
++
++ ++

++Specifies whether to use slave or DMA mode for accessing the data FIFOs. ++

++The driver will automatically detect the value for this parameter if none is specified. 0 - Slave 1 - DMA (default, if available) ++

++Definition at line 4135 of file dwc_otg_cil.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int dwc_otg_set_param_dma_desc_enable (dwc_otg_core_if_t *  core_if,
int32_t  val 
)
++
++
++ ++

++When DMA mode is enabled specifies whether to use address DMA or DMA Descritor mode for accessing the data FIFOs in device mode. ++

++The driver will automatically detect the value for this parameter if none is specified. 0 - address DMA 1 - DMA Descriptor(default, if available) ++

++Definition at line 4165 of file dwc_otg_cil.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int dwc_otg_set_param_dma_burst_size (dwc_otg_core_if_t *  core_if,
int32_t  val 
)
++
++
++ ++

++The DMA Burst size (applicable only for External DMA Mode). ++

++1, 4, 8 16, 32, 64, 128, 256 (default 32) ++

++Definition at line 4959 of file dwc_otg_cil.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int dwc_otg_set_param_speed (dwc_otg_core_if_t *  core_if,
int32_t  val 
)
++
++
++ ++

++Specifies the maximum speed of operation in host and device mode. ++

++The actual speed depends on the speed of the attached device and the value of phy_type. The actual speed depends on the speed of the attached device. 0 - High Speed (default) 1 - Full Speed ++

++Definition at line 4601 of file dwc_otg_cil.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int dwc_otg_set_param_host_support_fs_ls_low_power (dwc_otg_core_if_t *  core_if,
int32_t  val 
)
++
++
++ ++

++Specifies whether low power mode is supported when attached to a Full Speed or Low Speed device in host mode. ++

++0 - Don't support low power mode (default) 1 - Support low power mode ++

++Definition at line 4195 of file dwc_otg_cil.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int dwc_otg_set_param_host_ls_low_power_phy_clk (dwc_otg_core_if_t *  core_if,
int32_t  val 
)
++
++
++ ++

++Specifies the PHY clock rate in low power mode when connected to a Low Speed device in host mode. ++

++This parameter is applicable only if HOST_SUPPORT_FS_LS_LOW_POWER is enabled. If PHY_TYPE is set to FS then defaults to 6 MHZ otherwise 48 MHZ.

++0 - 48 MHz 1 - 6 MHz ++

++Definition at line 4630 of file dwc_otg_cil.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int dwc_otg_set_param_data_fifo_size (dwc_otg_core_if_t *  core_if,
int32_t  val 
)
++
++
++ ++

++Total number of 4-byte words in the data FIFO memory. ++

++This memory includes the Rx FIFO, non-periodic Tx FIFO, and periodic Tx FIFOs. 32 to 32768 (default 8192) Note: The total FIFO memory depth in the FPGA configuration is 8192. ++

++Definition at line 4242 of file dwc_otg_cil.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int dwc_otg_set_param_dev_rx_fifo_size (dwc_otg_core_if_t *  core_if,
int32_t  val 
)
++
++
++ ++

++Number of 4-byte words in the Rx FIFO in device mode when dynamic FIFO sizing is enabled. ++

++16 to 32768 (default 1064) ++

++Definition at line 4271 of file dwc_otg_cil.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int dwc_otg_set_param_dev_nperio_tx_fifo_size (dwc_otg_core_if_t *  core_if,
int32_t  val 
)
++
++
++ ++

++Number of 4-byte words in the non-periodic Tx FIFO in device mode when dynamic FIFO sizing is enabled. ++

++16 to 32768 (default 1024) ++

++Definition at line 4297 of file dwc_otg_cil.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int dwc_otg_set_param_dev_perio_tx_fifo_size (dwc_otg_core_if_t *  core_if,
int32_t  val,
int  fifo_num 
)
++
++
++ ++

++Number of 4-byte words in each of the periodic Tx FIFOs in device mode when dynamic FIFO sizing is enabled. ++

++4 to 768 (default 256) ++

++Definition at line 4779 of file dwc_otg_cil.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int dwc_otg_set_param_host_rx_fifo_size (dwc_otg_core_if_t *  core_if,
int32_t  val 
)
++
++
++ ++

++Number of 4-byte words in the Rx FIFO in host mode when dynamic FIFO sizing is enabled. ++

++16 to 32768 (default 1024) ++

++Definition at line 4330 of file dwc_otg_cil.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int dwc_otg_set_param_host_nperio_tx_fifo_size (dwc_otg_core_if_t *  core_if,
int32_t  val 
)
++
++
++ ++

++Number of 4-byte words in the non-periodic Tx FIFO in host mode when Dynamic FIFO sizing is enabled in the core. ++

++16 to 32768 (default 1024) ++

++Definition at line 4362 of file dwc_otg_cil.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int dwc_otg_set_param_host_perio_tx_fifo_size (dwc_otg_core_if_t *  core_if,
int32_t  val 
)
++
++
++ ++

++Number of 4-byte words in the host periodic Tx FIFO when dynamic FIFO sizing is enabled. ++

++16 to 32768 (default 1024) ++

++Definition at line 4395 of file dwc_otg_cil.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int dwc_otg_set_param_max_transfer_size (dwc_otg_core_if_t *  core_if,
int32_t  val 
)
++
++
++ ++

++The maximum transfer size supported in bytes. ++

++2047 to 65,535 (default 65,535) ++

++Definition at line 4428 of file dwc_otg_cil.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int dwc_otg_set_param_max_packet_count (dwc_otg_core_if_t *  core_if,
int32_t  val 
)
++
++
++ ++

++The maximum number of packets in a transfer. ++

++15 to 511 (default 511) ++

++Definition at line 4461 of file dwc_otg_cil.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int dwc_otg_set_param_host_channels (dwc_otg_core_if_t *  core_if,
int32_t  val 
)
++
++
++ ++

++The number of host channel registers to use. ++

++1 to 16 (default 12) Note: The FPGA configuration supports a maximum of 12 host channels. ++

++Definition at line 4492 of file dwc_otg_cil.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int dwc_otg_set_param_dev_endpoints (dwc_otg_core_if_t *  core_if,
int32_t  val 
)
++
++
++ ++

++The number of endpoints in addition to EP0 available for device mode operations. ++

++1 to 15 (default 6 IN and OUT) Note: The FPGA configuration supports a maximum of 6 IN and OUT endpoints in addition to EP0. ++

++Definition at line 4522 of file dwc_otg_cil.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int dwc_otg_set_param_phy_type (dwc_otg_core_if_t *  core_if,
int32_t  val 
)
++
++
++ ++

++Specifies the type of PHY interface to use. ++

++By default, the driver will automatically detect the phy_type.

++0 - Full Speed PHY 1 - UTMI+ (default) 2 - ULPI ++

++Definition at line 4552 of file dwc_otg_cil.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int dwc_otg_set_param_phy_utmi_width (dwc_otg_core_if_t *  core_if,
int32_t  val 
)
++
++
++ ++

++Specifies the UTMI+ Data Width. ++

++This parameter is applicable for a PHY_TYPE of UTMI+ or ULPI. (For a ULPI PHY_TYPE, this parameter indicates the data width between the MAC and the ULPI Wrapper.) Also, this parameter is applicable only if the OTG_HSPHY_WIDTH cC parameter was set to "8 and 16 bits", meaning that the core has been configured to work at either data path width.

++8 or 16 bits (default 16) ++

++Definition at line 4700 of file dwc_otg_cil.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int dwc_otg_set_param_phy_ulpi_ddr (dwc_otg_core_if_t *  core_if,
int32_t  val 
)
++
++
++ ++

++Specifies whether the ULPI operates at double or single data rate. ++

++This parameter is only applicable if PHY_TYPE is ULPI.

++0 - single data rate ULPI interface with 8 bit wide data bus (default) 1 - double data rate ULPI interface with 4 bit wide data bus ++

++Definition at line 4665 of file dwc_otg_cil.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int dwc_otg_set_param_i2c_enable (dwc_otg_core_if_t *  core_if,
int32_t  val 
)
++
++
++ ++

++Specifies whether to use the I2Cinterface for full speed PHY. ++

++This parameter is only applicable if PHY_TYPE is FS. 0 - No (default) 1 - Yes ++

++Definition at line 4751 of file dwc_otg_cil.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int dwc_otg_set_param_dev_tx_fifo_size (dwc_otg_core_if_t *  core_if,
int  fifo_num,
int32_t  val 
)
++
++
++ ++

++Number of 4-byte words in each of the Tx FIFOs in device mode when dynamic FIFO sizing is enabled. ++

++4 to 768 (default 256) ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_otg_dump_dev_registers (dwc_otg_core_if_t *  core_if  ) 
++
++
++ ++

++Dump core registers and SPRAM. ++

++

Parameters:
++ ++ ++
core_if Programming view of DWC_otg controller.
++
++ ++

++Definition at line 3347 of file dwc_otg_cil.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_otg_dump_spram (dwc_otg_core_if_t *  core_if  ) 
++
++
++ ++

++This functions reads the SPRAM and prints its content. ++

++

Parameters:
++ ++ ++
core_if Programming view of DWC_otg controller.
++
++ ++

++Definition at line 3477 of file dwc_otg_cil.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_otg_dump_host_registers (dwc_otg_core_if_t *  core_if  ) 
++
++
++ ++

++This function reads the host registers and prints them. ++

++

Parameters:
++ ++ ++
core_if Programming view of DWC_otg controller.
++
++ ++

++Definition at line 3505 of file dwc_otg_cil.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_otg_dump_global_registers (dwc_otg_core_if_t *  core_if  ) 
++
++
++ ++

++This function reads the core global registers and prints them. ++

++

Parameters:
++ ++ ++
core_if Programming view of DWC_otg controller.
++
++ ++

++Definition at line 3573 of file dwc_otg_cil.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
uint32_t dwc_otg_get_mode (dwc_otg_core_if_t *  core_if  ) 
++
++
++ ++

++Get current mode. ++

++Returns 0 if in device mode, and 1 if in host mode. ++

++Definition at line 5115 of file dwc_otg_cil.c. ++

++

++

Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__dbg_8h-source.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__dbg_8h-source.html 2013-07-26 19:31:20.000000000 +0000 +@@ -0,0 +1,100 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_dbg.h Source File ++ ++ ++ ++ ++
++
++
++
++

dwc_otg_dbg.h

Go to the documentation of this file.
00001 /* ==========================================================================
++00002  *
++00003  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
++00004  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
++00005  * otherwise expressly agreed to in writing between Synopsys and you.
++00006  * 
++00007  * The Software IS NOT an item of Licensed Software or Licensed Product under
++00008  * any End User Software License Agreement or Agreement for Licensed Product
++00009  * with Synopsys or any supplement thereto. You are permitted to use and
++00010  * redistribute this Software in source and binary forms, with or without
++00011  * modification, provided that redistributions of source code must retain this
++00012  * notice. You may not view, use, disclose, copy or distribute this file or
++00013  * any information contained herein except pursuant to this license grant from
++00014  * Synopsys. If you do not agree with this notice, including the disclaimer
++00015  * below, then you are not authorized to use the Software.
++00016  * 
++00017  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
++00018  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++00019  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++00020  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
++00021  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++00022  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
++00023  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
++00024  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
++00025  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
++00026  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
++00027  * DAMAGE.
++00028  * ========================================================================== */
++00029 
++00030 #ifndef __DWC_OTG_DBG_H__
++00031 #define __DWC_OTG_DBG_H__
++00032 
++00041 extern uint32_t g_dbg_lvl;
++00045 static inline uint32_t SET_DEBUG_LEVEL(const uint32_t new)
++00046 {
++00047         uint32_t old = g_dbg_lvl;
++00048         g_dbg_lvl = new;
++00049         return old;
++00050 }
++00051 
++00053 #define DBG_CIL         (0x2)
++00054 
++00056 #define DBG_CILV        (0x20)
++00057 
++00059 #define DBG_PCD         (0x4)
++00060 
++00062 #define DBG_PCDV        (0x40)
++00063 
++00064 #define DBG_HCD         (0x8)
++00065 
++00067 #define DBG_HCDV        (0x80)
++00068 
++00070 #define DBG_HCD_URB     (0x800)
++00071 
++00073 #define DBG_ANY         (0xFF)
++00074 
++00076 #define DBG_OFF         0
++00077 
++00079 #define USB_DWC "DWC_otg: "
++00080 
++00098 #ifdef DEBUG
++00099 
++00100 # define DWC_DEBUGPL(lvl, x...) do{ if ((lvl)&g_dbg_lvl)__DWC_DEBUG(USB_DWC x ); }while(0)
++00101 # define DWC_DEBUGP(x...)       DWC_DEBUGPL(DBG_ANY, x )
++00102 
++00103 # define CHK_DEBUG_LEVEL(level) ((level) & g_dbg_lvl)
++00104 
++00105 #else
++00106 
++00107 # define DWC_DEBUGPL(lvl, x...) do{}while(0)
++00108 # define DWC_DEBUGP(x...)
++00109 
++00110 # define CHK_DEBUG_LEVEL(level) (0)
++00111 
++00112 #endif /*DEBUG*/
++00113 #endif
++
Generated on Tue May 5 02:22:48 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__dbg_8h.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__dbg_8h.html 2013-07-26 19:31:20.000000000 +0000 +@@ -0,0 +1,133 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_dbg.h File Reference ++ ++ ++ ++ ++
++
++
++
++

dwc_otg_dbg.h File Reference

This file defines debug levels. More... ++

++ ++

++Go to the source code of this file. ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++

Defines

++#define DBG_CIL   (0x2)
 When debug level has the DBG_CIL bit set, display CIL Debug messages.
++#define DBG_CILV   (0x20)
 When debug level has the DBG_CILV bit set, display CIL Verbose debug messages.
++#define DBG_PCD   (0x4)
 When debug level has the DBG_PCD bit set, display PCD (Device) debug messages.
++#define DBG_PCDV   (0x40)
 When debug level has the DBG_PCDV set, display PCD (Device) Verbose debug messages.
++#define DBG_HCD   (0x8)
 When debug level has the DBG_HCD bit set, display Host debug messages.
++#define DBG_HCDV   (0x80)
 When debug level has the DBG_HCDV bit set, display Verbose Host debug messages.
++#define DBG_HCD_URB   (0x800)
 When debug level has the DBG_HCD_URB bit set, display enqueued URBs in host mode.
++#define DBG_ANY   (0xFF)
 When debug level has any bit set, display debug messages.
++#define DBG_OFF   0
 All debug messages off.
++#define USB_DWC   "DWC_otg: "
 Prefix string for DWC_DEBUG print macros.
#define DWC_DEBUGPL(lvl, x...)   do{}while(0)
 Print a debug message when the Global debug level variable contains the bit defined in lvl.
++#define DWC_DEBUGP(x...)
++#define CHK_DEBUG_LEVEL(level)   (0)

Functions

++static uint32_t SET_DEBUG_LEVEL (const uint32_t new)
 Set the Debug Level variable.

Variables

++uint32_t g_dbg_lvl
 The Debug Level bit-mask variable.
++

Detailed Description

++This file defines debug levels. ++

++Debugging support vanishes in non-debug builds. ++

++Definition in file dwc_otg_dbg.h.

Define Documentation

++ ++
++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
#define DWC_DEBUGPL (lvl,
x...   )    do{}while(0)
++
++
++ ++

++Print a debug message when the Global debug level variable contains the bit defined in lvl. ++

++

Parameters:
++ ++ ++ ++
[in] lvl - Debug level, use one of the DBG_ constants above.
[in] x - like printf
++
++Example:

++ DWC_DEBUGPL( DBG_ANY, "%s(%p)\n", __func__, _reg_base_addr);
++ results in:
++ usb-DWC_otg: dwc_otg_cil_init(ca867000) ++

++Definition at line 107 of file dwc_otg_dbg.h. ++

++

++

Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__driver_8c-source.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__driver_8c-source.html 2013-07-26 19:31:20.000000000 +0000 +@@ -0,0 +1,1079 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_driver.c Source File ++ ++ ++ ++ ++
++
++
++
++

dwc_otg_driver.c

Go to the documentation of this file.
00001 /* ==========================================================================
++00002  * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_driver.c $
++00003  * $Revision: #76 $
++00004  * $Date: 2009/05/03 $
++00005  * $Change: 1245589 $
++00006  *
++00007  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
++00008  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
++00009  * otherwise expressly agreed to in writing between Synopsys and you.
++00010  *
++00011  * The Software IS NOT an item of Licensed Software or Licensed Product under
++00012  * any End User Software License Agreement or Agreement for Licensed Product
++00013  * with Synopsys or any supplement thereto. You are permitted to use and
++00014  * redistribute this Software in source and binary forms, with or without
++00015  * modification, provided that redistributions of source code must retain this
++00016  * notice. You may not view, use, disclose, copy or distribute this file or
++00017  * any information contained herein except pursuant to this license grant from
++00018  * Synopsys. If you do not agree with this notice, including the disclaimer
++00019  * below, then you are not authorized to use the Software.
++00020  *
++00021  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
++00022  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++00023  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++00024  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
++00025  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++00026  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
++00027  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
++00028  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
++00029  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
++00030  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
++00031  * DAMAGE.
++00032  * ========================================================================== */
++00033 
++00051 #include <linux/kernel.h>
++00052 #include <linux/module.h>
++00053 #include <linux/moduleparam.h>
++00054 #include <linux/init.h>
++00055 #include <linux/device.h>
++00056 #include <linux/errno.h>
++00057 #include <linux/types.h>
++00058 #include <linux/stat.h>         /* permission constants */
++00059 #include <linux/version.h>
++00060 #include <linux/interrupt.h>
++00061 
++00062 #ifdef LM_INTERFACE
++00063 #include <asm/arch/regs-irq.h>
++00064 #include <asm/arch/lm.h>
++00065 #include <asm/sizes.h>
++00066 #endif
++00067 
++00068 # include <linux/irq.h>
++00069 
++00070 #include <asm/io.h>
++00071 
++00072 
++00073 #include "dwc_os.h"
++00074 #include "dwc_otg_dbg.h"
++00075 #include "dwc_otg_driver.h"
++00076 #include "dwc_otg_attr.h"
++00077 #include "dwc_otg_core_if.h"
++00078 #include "dwc_otg_pcd_if.h"
++00079 #include "dwc_otg_hcd_if.h"
++00080 
++00081 #define DWC_DRIVER_VERSION      "2.90a 23-APR-2009"
++00082 #define DWC_DRIVER_DESC         "HS OTG USB Controller driver"
++00083 
++00084 static const char dwc_driver_name[] = "dwc_otg";
++00085 
++00086 extern int pcd_init(
++00087 #ifdef LM_INTERFACE
++00088         struct lm_device *_dev
++00089 #elif  PCI_INTERFACE
++00090         struct pci_dev *_dev
++00091 #endif
++00092         );
++00093 extern int hcd_init(
++00094 #ifdef LM_INTERFACE
++00095         struct lm_device *_dev
++00096 #elif  PCI_INTERFACE
++00097         struct pci_dev *_dev
++00098 #endif
++00099         );
++00100 
++00101 extern int pcd_remove(
++00102 #ifdef LM_INTERFACE
++00103         struct lm_device *_dev
++00104 #elif  PCI_INTERFACE
++00105         struct pci_dev *_dev
++00106 #endif
++00107         );
++00108 
++00109 extern void hcd_remove(
++00110 #ifdef LM_INTERFACE
++00111         struct lm_device *_dev
++00112 #elif  PCI_INTERFACE
++00113         struct pci_dev *_dev
++00114 #endif
++00115         );
++00116 
++00117 /*-------------------------------------------------------------------------*/
++00118 /* Encapsulate the module parameter settings */
++00119 
++00120 struct dwc_otg_driver_module_params {
++00121         int32_t opt;
++00122         int32_t otg_cap;
++00123         int32_t dma_enable;
++00124         int32_t dma_desc_enable;
++00125         int32_t dma_burst_size;
++00126         int32_t speed;
++00127         int32_t host_support_fs_ls_low_power;
++00128         int32_t host_ls_low_power_phy_clk;
++00129         int32_t enable_dynamic_fifo;
++00130         int32_t data_fifo_size;
++00131         int32_t dev_rx_fifo_size;
++00132         int32_t dev_nperio_tx_fifo_size;
++00133         uint32_t dev_perio_tx_fifo_size[MAX_PERIO_FIFOS];
++00134         int32_t host_rx_fifo_size;
++00135         int32_t host_nperio_tx_fifo_size;
++00136         int32_t host_perio_tx_fifo_size;
++00137         int32_t max_transfer_size;
++00138         int32_t max_packet_count;
++00139         int32_t host_channels;
++00140         int32_t dev_endpoints;
++00141         int32_t phy_type;
++00142         int32_t phy_utmi_width;
++00143         int32_t phy_ulpi_ddr;
++00144         int32_t phy_ulpi_ext_vbus;
++00145         int32_t i2c_enable;
++00146         int32_t ulpi_fs_ls;
++00147         int32_t ts_dline;
++00148         int32_t en_multiple_tx_fifo;
++00149         uint32_t dev_tx_fifo_size[MAX_TX_FIFOS];
++00150         uint32_t thr_ctl;
++00151         uint32_t tx_thr_length;
++00152         uint32_t rx_thr_length;
++00153         int32_t pti_enable;
++00154         int32_t mpi_enable;
++00155         int32_t lpm_enable;
++00156         int32_t ic_usb_cap;
++00157         int32_t ahb_thr_ratio;
++00158 };
++00159 
++00160 static struct dwc_otg_driver_module_params dwc_otg_module_params = {
++00161         .opt = -1,
++00162         .otg_cap = -1,
++00163         .dma_enable = -1,
++00164         .dma_desc_enable = -1,
++00165         .dma_burst_size = -1,
++00166         .speed = -1,
++00167         .host_support_fs_ls_low_power = -1,
++00168         .host_ls_low_power_phy_clk = -1,
++00169         .enable_dynamic_fifo = -1,
++00170         .data_fifo_size = -1,
++00171         .dev_rx_fifo_size = -1,
++00172         .dev_nperio_tx_fifo_size = -1,
++00173         .dev_perio_tx_fifo_size = {
++00174                                    /* dev_perio_tx_fifo_size_1 */
++00175                                    -1,
++00176                                    -1,
++00177                                    -1,
++00178                                    -1,
++00179                                    -1,
++00180                                    -1,
++00181                                    -1,
++00182                                    -1,
++00183                                    -1,
++00184                                    -1,
++00185                                    -1,
++00186                                    -1,
++00187                                    -1,
++00188                                    -1,
++00189                                    -1
++00190                                    /* 15 */
++00191                                    },
++00192         .host_rx_fifo_size = -1,
++00193         .host_nperio_tx_fifo_size = -1,
++00194         .host_perio_tx_fifo_size = -1,
++00195         .max_transfer_size = -1,
++00196         .max_packet_count = -1,
++00197         .host_channels = -1,
++00198         .dev_endpoints = -1,
++00199         .phy_type = -1,
++00200         .phy_utmi_width = -1,
++00201         .phy_ulpi_ddr = -1,
++00202         .phy_ulpi_ext_vbus = -1,
++00203         .i2c_enable = -1,
++00204         .ulpi_fs_ls = -1,
++00205         .ts_dline = -1,
++00206         .en_multiple_tx_fifo = -1,
++00207         .dev_tx_fifo_size = {
++00208                              /* dev_tx_fifo_size */
++00209                              -1,
++00210                              -1,
++00211                              -1,
++00212                              -1,
++00213                              -1,
++00214                              -1,
++00215                              -1,
++00216                              -1,
++00217                              -1,
++00218                              -1,
++00219                              -1,
++00220                              -1,
++00221                              -1,
++00222                              -1,
++00223                              -1
++00224                              /* 15 */
++00225                              },
++00226         .thr_ctl = -1,
++00227         .tx_thr_length = -1,
++00228         .rx_thr_length = -1,
++00229         .pti_enable = -1,
++00230         .mpi_enable = -1,
++00231         .lpm_enable = -1,
++00232         .ic_usb_cap = -1,
++00233         .ahb_thr_ratio = -1,
++00234 };
++00235 
++00239 static ssize_t version_show(struct device_driver *dev, char *buf)
++00240 {
++00241         return snprintf(buf, sizeof(DWC_DRIVER_VERSION) + 2, "%s\n",
++00242                         DWC_DRIVER_VERSION);
++00243 }
++00244 
++00245 static DRIVER_ATTR(version, S_IRUGO, version_show, NULL);
++00246 
++00250 uint32_t g_dbg_lvl = 0;         /* OFF */
++00251 
++00255 static ssize_t dbg_level_show(struct device_driver *drv, char *buf)
++00256 {
++00257         return sprintf(buf, "0x%0x\n", g_dbg_lvl);
++00258 }
++00259 
++00263 static ssize_t dbg_level_store(struct device_driver *drv, const char *buf,
++00264                                size_t count)
++00265 {
++00266         g_dbg_lvl = simple_strtoul(buf, NULL, 16);
++00267         return count;
++00268 }
++00269 
++00270 static DRIVER_ATTR(debuglevel, S_IRUGO | S_IWUSR, dbg_level_show,
++00271                    dbg_level_store);
++00272 
++00277 static int set_parameters(dwc_otg_core_if_t * core_if)
++00278 {
++00279         int retval = 0;
++00280         int i;
++00281 
++00282         if (dwc_otg_module_params.otg_cap != -1) {
++00283                 retval +=
++00284                     dwc_otg_set_param_otg_cap(core_if,
++00285                                               dwc_otg_module_params.otg_cap);
++00286         }
++00287         if (dwc_otg_module_params.dma_enable != -1) {
++00288                 retval +=
++00289                     dwc_otg_set_param_dma_enable(core_if,
++00290                                                  dwc_otg_module_params.
++00291                                                  dma_enable);
++00292         }
++00293         if (dwc_otg_module_params.dma_desc_enable != -1) {
++00294                 retval +=
++00295                     dwc_otg_set_param_dma_desc_enable(core_if,
++00296                                                       dwc_otg_module_params.
++00297                                                       dma_desc_enable);
++00298         }
++00299         if (dwc_otg_module_params.opt != -1) {
++00300                 retval +=
++00301                     dwc_otg_set_param_opt(core_if, dwc_otg_module_params.opt);
++00302         }
++00303         if (dwc_otg_module_params.dma_burst_size != -1) {
++00304                 retval +=
++00305                     dwc_otg_set_param_dma_burst_size(core_if,
++00306                                                      dwc_otg_module_params.
++00307                                                      dma_burst_size);
++00308         }
++00309         if (dwc_otg_module_params.host_support_fs_ls_low_power != -1) {
++00310                 retval +=
++00311                     dwc_otg_set_param_host_support_fs_ls_low_power(core_if,
++00312                                                                    dwc_otg_module_params.
++00313                                                                    host_support_fs_ls_low_power);
++00314         }
++00315         if (dwc_otg_module_params.enable_dynamic_fifo != -1) {
++00316                 retval +=
++00317                     dwc_otg_set_param_enable_dynamic_fifo(core_if,
++00318                                                           dwc_otg_module_params.
++00319                                                           enable_dynamic_fifo);
++00320         }
++00321         if (dwc_otg_module_params.data_fifo_size != -1) {
++00322                 retval +=
++00323                     dwc_otg_set_param_data_fifo_size(core_if,
++00324                                                      dwc_otg_module_params.
++00325                                                      data_fifo_size);
++00326         }
++00327         if (dwc_otg_module_params.dev_rx_fifo_size != -1) {
++00328                 retval +=
++00329                     dwc_otg_set_param_dev_rx_fifo_size(core_if,
++00330                                                        dwc_otg_module_params.
++00331                                                        dev_rx_fifo_size);
++00332         }
++00333         if (dwc_otg_module_params.dev_nperio_tx_fifo_size != -1) {
++00334                 retval +=
++00335                     dwc_otg_set_param_dev_nperio_tx_fifo_size(core_if,
++00336                                                               dwc_otg_module_params.
++00337                                                               dev_nperio_tx_fifo_size);
++00338         }
++00339         if (dwc_otg_module_params.host_rx_fifo_size != -1) {
++00340                 retval +=
++00341                     dwc_otg_set_param_host_rx_fifo_size(core_if,
++00342                                                         dwc_otg_module_params.host_rx_fifo_size);
++00343         }
++00344         if (dwc_otg_module_params.host_nperio_tx_fifo_size != -1) {
++00345                 retval +=
++00346                     dwc_otg_set_param_host_nperio_tx_fifo_size(core_if,
++00347                                                                dwc_otg_module_params.
++00348                                                                host_nperio_tx_fifo_size);
++00349         }
++00350         if (dwc_otg_module_params.host_perio_tx_fifo_size != -1) {
++00351                 retval +=
++00352                     dwc_otg_set_param_host_perio_tx_fifo_size(core_if,
++00353                                                               dwc_otg_module_params.
++00354                                                               host_perio_tx_fifo_size);
++00355         }
++00356         if (dwc_otg_module_params.max_transfer_size != -1) {
++00357                 retval +=
++00358                     dwc_otg_set_param_max_transfer_size(core_if,
++00359                                                         dwc_otg_module_params.
++00360                                                         max_transfer_size);
++00361         }
++00362         if (dwc_otg_module_params.max_packet_count != -1) {
++00363                 retval +=
++00364                     dwc_otg_set_param_max_packet_count(core_if,
++00365                                                        dwc_otg_module_params.
++00366                                                        max_packet_count);
++00367         }
++00368         if (dwc_otg_module_params.host_channels != -1) {
++00369                 retval +=
++00370                     dwc_otg_set_param_host_channels(core_if,
++00371                                                     dwc_otg_module_params.
++00372                                                     host_channels);
++00373         }
++00374         if (dwc_otg_module_params.dev_endpoints != -1) {
++00375                 retval +=
++00376                     dwc_otg_set_param_dev_endpoints(core_if,
++00377                                                     dwc_otg_module_params.
++00378                                                     dev_endpoints);
++00379         }
++00380         if (dwc_otg_module_params.phy_type != -1) {
++00381                 retval +=
++00382                     dwc_otg_set_param_phy_type(core_if,
++00383                                                dwc_otg_module_params.phy_type);
++00384         }
++00385         if (dwc_otg_module_params.speed != -1) {
++00386                 retval +=
++00387                     dwc_otg_set_param_speed(core_if,
++00388                                             dwc_otg_module_params.speed);
++00389         }
++00390         if (dwc_otg_module_params.host_ls_low_power_phy_clk != -1) {
++00391                 retval +=
++00392                     dwc_otg_set_param_host_ls_low_power_phy_clk(core_if,
++00393                                                                 dwc_otg_module_params.
++00394                                                                 host_ls_low_power_phy_clk);
++00395         }
++00396         if (dwc_otg_module_params.phy_ulpi_ddr != -1) {
++00397                 retval +=
++00398                     dwc_otg_set_param_phy_ulpi_ddr(core_if,
++00399                                                    dwc_otg_module_params.
++00400                                                    phy_ulpi_ddr);
++00401         }
++00402         if (dwc_otg_module_params.phy_ulpi_ext_vbus != -1) {
++00403                 retval +=
++00404                     dwc_otg_set_param_phy_ulpi_ext_vbus(core_if,
++00405                                                         dwc_otg_module_params.
++00406                                                         phy_ulpi_ext_vbus);
++00407         }
++00408         if (dwc_otg_module_params.phy_utmi_width != -1) {
++00409                 retval +=
++00410                     dwc_otg_set_param_phy_utmi_width(core_if,
++00411                                                      dwc_otg_module_params.
++00412                                                      phy_utmi_width);
++00413         }
++00414         if (dwc_otg_module_params.ulpi_fs_ls != -1) {
++00415                 retval +=
++00416                     dwc_otg_set_param_ulpi_fs_ls(core_if, dwc_otg_module_params.ulpi_fs_ls);
++00417         }
++00418         if (dwc_otg_module_params.ts_dline != -1) {
++00419                 retval +=
++00420                     dwc_otg_set_param_ts_dline(core_if,
++00421                                                dwc_otg_module_params.ts_dline);
++00422         }
++00423         if (dwc_otg_module_params.i2c_enable != -1) {
++00424                 retval +=
++00425                     dwc_otg_set_param_i2c_enable(core_if,
++00426                                                  dwc_otg_module_params.
++00427                                                  i2c_enable);
++00428         }
++00429         if (dwc_otg_module_params.en_multiple_tx_fifo != -1) {
++00430                 retval +=
++00431                     dwc_otg_set_param_en_multiple_tx_fifo(core_if,
++00432                                                           dwc_otg_module_params.
++00433                                                           en_multiple_tx_fifo);
++00434         }
++00435         for (i = 0; i < 15; i++) {
++00436                 if (dwc_otg_module_params.dev_perio_tx_fifo_size[i] != -1) {
++00437                         retval +=
++00438                             dwc_otg_set_param_dev_perio_tx_fifo_size(core_if,
++00439                                                                      dwc_otg_module_params.
++00440                                                                      dev_perio_tx_fifo_size
++00441                                                                      [i], i);
++00442                 }
++00443         }
++00444 
++00445         for (i = 0; i < 15; i++) {
++00446                 if (dwc_otg_module_params.dev_tx_fifo_size[i] != -1) {
++00447                         retval += dwc_otg_set_param_dev_tx_fifo_size(core_if,
++00448                                                                      dwc_otg_module_params.
++00449                                                                      dev_tx_fifo_size
++00450                                                                      [i], i);
++00451                 }
++00452         }
++00453         if (dwc_otg_module_params.thr_ctl != -1) {
++00454                 retval +=
++00455                     dwc_otg_set_param_thr_ctl(core_if,
++00456                                               dwc_otg_module_params.thr_ctl);
++00457         }
++00458         if (dwc_otg_module_params.mpi_enable != -1) {
++00459                 retval +=
++00460                     dwc_otg_set_param_mpi_enable(core_if,
++00461                                                  dwc_otg_module_params.
++00462                                                  mpi_enable);
++00463         }
++00464         if (dwc_otg_module_params.pti_enable != -1) {
++00465                 retval +=
++00466                     dwc_otg_set_param_pti_enable(core_if,
++00467                                                  dwc_otg_module_params.
++00468                                                  pti_enable);
++00469         }
++00470         if (dwc_otg_module_params.lpm_enable != -1) {
++00471                 retval +=
++00472                     dwc_otg_set_param_lpm_enable(core_if,
++00473                                                  dwc_otg_module_params.
++00474                                                  lpm_enable);
++00475         }
++00476         if (dwc_otg_module_params.ic_usb_cap != -1) {
++00477                 retval +=
++00478                     dwc_otg_set_param_ic_usb_cap(core_if,
++00479                                                  dwc_otg_module_params.
++00480                                                  ic_usb_cap);
++00481         }
++00482         if (dwc_otg_module_params.tx_thr_length != -1) {
++00483                 retval +=
++00484                     dwc_otg_set_param_tx_thr_length(core_if,
++00485                                                     dwc_otg_module_params.tx_thr_length);
++00486         }
++00487         if (dwc_otg_module_params.rx_thr_length != -1) {
++00488                 retval +=
++00489                     dwc_otg_set_param_rx_thr_length(core_if,
++00490                                                     dwc_otg_module_params.
++00491                                                     rx_thr_length);
++00492         }
++00493         if(dwc_otg_module_params.ahb_thr_ratio != -1) {
++00494                 retval +=
++00495                     dwc_otg_set_param_ahb_thr_ratio(core_if, dwc_otg_module_params.ahb_thr_ratio);
++00496         }
++00497         return retval;
++00498 }
++00499 
++00504 static irqreturn_t dwc_otg_common_irq(int irq, void *dev)
++00505 {
++00506         dwc_otg_device_t *otg_dev = dev;
++00507         int32_t retval = IRQ_NONE;
++00508 
++00509         retval = dwc_otg_handle_common_intr(otg_dev->core_if);
++00510         if (retval != 0) {
++00511                 S3C2410X_CLEAR_EINTPEND();
++00512         }
++00513         return IRQ_RETVAL(retval);
++00514 }
++00515 
++00525 static void dwc_otg_driver_remove(
++00526 #ifdef LM_INTERFACE
++00527      struct lm_device *_dev
++00528 #elif PCI_INTERFACE
++00529      struct pci_dev *_dev
++00530 #endif
++00531 )
++00532 
++00533 {
++00534 #ifdef LM_INTERFACE
++00535         dwc_otg_device_t *otg_dev = lm_get_drvdata(_dev);
++00536 #elif PCI_INTERFACE
++00537         dwc_otg_device_t *otg_dev = pci_get_drvdata(_dev);
++00538 #endif
++00539 
++00540 
++00541         DWC_DEBUGPL(DBG_ANY, "%s(%p)\n", __func__, _dev);
++00542 
++00543         if (!otg_dev) {
++00544                 /* Memory allocation for the dwc_otg_device failed. */
++00545                 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev NULL!\n", __func__);
++00546                 return;
++00547         }
++00548 #ifndef DWC_DEVICE_ONLY
++00549         if (otg_dev->hcd) {
++00550                 hcd_remove(_dev);
++00551         } else {
++00552                 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->hcd NULL!\n", __func__);
++00553                 return;
++00554         }
++00555 #endif
++00556 
++00557 #ifndef DWC_HOST_ONLY
++00558         if (otg_dev->pcd) {
++00559                 pcd_remove(_dev);
++00560         }
++00561 #endif
++00562         /*
++00563          * Free the IRQ
++00564          */
++00565         if (otg_dev->common_irq_installed) {
++00566                 free_irq(_dev->irq, otg_dev);
++00567         }
++00568 
++00569         if (otg_dev->core_if) {
++00570                 dwc_otg_cil_remove(otg_dev->core_if);
++00571         }
++00572 
++00573         /*
++00574          * Remove the device attributes
++00575          */
++00576         dwc_otg_attr_remove(_dev);
++00577 
++00578         /*
++00579          * Return the memory.
++00580          */
++00581         if (otg_dev->base) {
++00582                 iounmap(otg_dev->base);
++00583         }
++00584         dwc_free(otg_dev);
++00585 
++00586         /*
++00587          * Clear the drvdata pointer.
++00588          */
++00589 #ifdef LM_INTERFACE
++00590         lm_set_drvdata(_dev, 0);
++00591 #elif PCI_INTERFACE
++00592         release_mem_region(otg_dev->rsrc_start, otg_dev->rsrc_len);
++00593         pci_set_drvdata(_dev, 0);
++00594 #endif
++00595 }
++00596 
++00608 static int dwc_otg_driver_probe(
++00609 #ifdef LM_INTERFACE
++00610 struct lm_device *_dev
++00611 #elif PCI_INTERFACE
++00612 struct pci_dev *_dev,  const struct pci_device_id *id
++00613 #endif
++00614 )
++00615 {
++00616         int retval = 0;
++00617         dwc_otg_device_t *dwc_otg_device;
++00618 
++00619         dev_dbg(&_dev->dev, "dwc_otg_driver_probe(%p)\n", _dev);
++00620 #ifdef LM_INTERFACE
++00621         dev_dbg(&_dev->dev, "start=0x%08x\n", (unsigned)_dev->resource.start);
++00622 #elif PCI_INTERFACE
++00623         if (!id) {
++00624         DWC_ERROR("Invalid pci_device_id %p", id);
++00625                 return -EINVAL;
++00626         }
++00627 
++00628         if (!_dev || (pci_enable_device(_dev) < 0)) {
++00629                 DWC_ERROR("Invalid pci_device %p", _dev);
++00630                 return -ENODEV;
++00631         }
++00632         dev_dbg(&_dev->dev, "start=0x%08x\n", (unsigned)pci_resource_start(_dev,0));
++00633         /* other stuff needed as well? */
++00634 
++00635 #endif
++00636 
++00637 
++00638         dwc_otg_device = dwc_alloc(sizeof(dwc_otg_device_t));
++00639 
++00640         if (!dwc_otg_device) {
++00641                 dev_err(&_dev->dev, "kmalloc of dwc_otg_device failed\n");
++00642                 retval = -ENOMEM;
++00643                 goto fail;
++00644         }
++00645 
++00646         memset(dwc_otg_device, 0, sizeof(*dwc_otg_device));
++00647         dwc_otg_device->reg_offset = 0xFFFFFFFF;
++00648 
++00649         /*
++00650          * Map the DWC_otg Core memory into virtual address space.
++00651          */
++00652 #ifdef LM_INTERFACE
++00653         dwc_otg_device->base = ioremap(_dev->resource.start, SZ_256K);
++00654 
++00655         if (!dwc_otg_device->base) {
++00656                 dev_err(&_dev->dev, "ioremap() failed\n");
++00657                 retval = -ENOMEM;
++00658                 goto fail;
++00659         }
++00660         dev_dbg(&_dev->dev, "base=0x%08x\n", (unsigned)dwc_otg_device->base);
++00661 #elif PCI_INTERFACE
++00662         _dev->current_state = PCI_D0;
++00663         _dev->dev.power.power_state = PMSG_ON;
++00664         
++00665         if (!_dev->irq) {
++00666                 DWC_ERROR("Found HC with no IRQ. Check BIOS/PCI %s setup!", pci_name(_dev));
++00667                 retval = -ENODEV;
++00668                 goto fail;
++00669         }
++00670 
++00671         dwc_otg_device->rsrc_start = pci_resource_start(_dev,0);
++00672         dwc_otg_device->rsrc_len = pci_resource_len(_dev,0);
++00673         DWC_DEBUGPL(DBG_ANY,"PCI resource: start=%08x, len=%08x\n",
++00674                     dwc_otg_device->rsrc_start,
++00675                     dwc_otg_device->rsrc_len);
++00676         if (!request_mem_region(dwc_otg_device->rsrc_start, dwc_otg_device->rsrc_len, "dwc_otg")) {
++00677           dev_dbg(&_dev->dev, "error mapping memory\n");
++00678           retval = -EFAULT;
++00679           goto fail;
++00680         }
++00681 
++00682         dwc_otg_device->base = ioremap_nocache(dwc_otg_device->rsrc_start, dwc_otg_device->rsrc_len);
++00683         if (dwc_otg_device->base == NULL) {
++00684                 dev_dbg(&_dev->dev, "error mapping memory\n");
++00685                 retval = -EFAULT;
++00686                 goto fail;
++00687         }
++00688         dev_dbg(&_dev->dev, "base=0x%p (before adjust) \n", dwc_otg_device->base);
++00689         dwc_otg_device->base = (char *)dwc_otg_device->base;
++00690         dev_dbg(&_dev->dev, "base=0x%p (after adjust) \n", dwc_otg_device->base);
++00691         dev_dbg(&_dev->dev, "%s: mapped PA 0x%x to VA 0x%p\n", __func__,
++00692                 (unsigned)dwc_otg_device->rsrc_start, dwc_otg_device->base);
++00693         //
++00694         pci_set_drvdata(_dev, dwc_otg_device); 
++00695         pci_set_master(_dev);
++00696 #endif
++00697 
++00698         /*
++00699          * Initialize driver data to point to the global DWC_otg
++00700          * Device structure.
++00701          */
++00702 #ifdef LM_INTERFACE
++00703         lm_set_drvdata(_dev, dwc_otg_device);
++00704 #endif
++00705         dev_dbg(&_dev->dev, "dwc_otg_device=0x%p\n", dwc_otg_device);
++00706 
++00707         dwc_otg_device->core_if = dwc_otg_cil_init(dwc_otg_device->base);
++00708         if (!dwc_otg_device->core_if) {
++00709                 dev_err(&_dev->dev, "CIL initialization failed!\n");
++00710                 retval = -ENOMEM;
++00711                 goto fail;
++00712         }
++00713 
++00714         /*
++00715          * Attempt to ensure this device is really a DWC_otg Controller.
++00716          * Read and verify the SNPSID register contents. The value should be
++00717          * 0x45F42XXX, which corresponds to "OT2", as in "OTG version 2.XX".
++00718          */
++00719 
++00720         if ((dwc_otg_get_gsnpsid(dwc_otg_device->core_if) & 0xFFFFF000) !=
++00721             0x4F542000) {
++00722                 dev_err(&_dev->dev, "Bad value for SNPSID: 0x%08x\n",
++00723                         dwc_otg_get_gsnpsid(dwc_otg_device->core_if));
++00724                 dwc_otg_cil_remove(dwc_otg_device->core_if);
++00725                 dwc_free(dwc_otg_device);
++00726                 retval = -EINVAL;
++00727                 goto fail;
++00728         }
++00729 
++00730         /*
++00731          * Validate parameter values.
++00732          */
++00733         if (set_parameters(dwc_otg_device->core_if)) {
++00734                 dwc_otg_cil_remove(dwc_otg_device->core_if);
++00735                 retval = -EINVAL;
++00736                 goto fail;
++00737         }
++00738 
++00739         /*
++00740          * Create Device Attributes in sysfs
++00741          */
++00742         dwc_otg_attr_create(_dev);
++00743 
++00744         /*
++00745          * Disable the global interrupt until all the interrupt
++00746          * handlers are installed.
++00747          */
++00748         dwc_otg_disable_global_interrupts(dwc_otg_device->core_if);
++00749 
++00750         /*
++00751          * Install the interrupt handler for the common interrupts before
++00752          * enabling common interrupts in core_init below.
++00753          */
++00754         DWC_DEBUGPL(DBG_CIL, "registering (common) handler for irq%d\n",
++00755                     _dev->irq);
++00756         retval = request_irq(_dev->irq, dwc_otg_common_irq,
++00757                              SA_SHIRQ, "dwc_otg", dwc_otg_device);
++00758         if (retval) {
++00759                 DWC_ERROR("request of irq%d failed\n", _dev->irq);
++00760                 retval = -EBUSY;
++00761                 goto fail;
++00762         } else {
++00763                 dwc_otg_device->common_irq_installed = 1;
++00764         }
++00765 
++00766 #ifdef LM_INTERFACE
++00767         set_irq_type(_dev->irq, IRQT_LOW);
++00768 #endif
++00769 
++00770         /*
++00771          * Initialize the DWC_otg core.
++00772          */
++00773         dwc_otg_core_init(dwc_otg_device->core_if);
++00774 
++00775 #ifndef DWC_HOST_ONLY
++00776         /*
++00777          * Initialize the PCD
++00778          */
++00779         retval = pcd_init(_dev);
++00780         if (retval != 0) {
++00781                 DWC_ERROR("pcd_init failed\n");
++00782                 dwc_otg_device->pcd = NULL;
++00783                 goto fail;
++00784         }
++00785 #endif
++00786 #ifndef DWC_DEVICE_ONLY
++00787         /*
++00788          * Initialize the HCD
++00789          */
++00790         retval = hcd_init(_dev);
++00791         if (retval != 0) {
++00792                 DWC_ERROR("hcd_init failed\n");
++00793                 dwc_otg_device->hcd = NULL;
++00794                 goto fail;
++00795         }
++00796 #endif
++00797 #ifdef PCI_INTERFACE    
++00798         pci_set_drvdata(_dev, dwc_otg_device);
++00799 #endif
++00800 
++00801         /*
++00802          * Enable the global interrupt after all the interrupt
++00803          * handlers are installed.
++00804          */
++00805         dwc_otg_enable_global_interrupts(dwc_otg_device->core_if);
++00806 
++00807         return 0;
++00808 
++00809       fail:
++00810         dwc_otg_driver_remove(_dev);
++00811         return retval;
++00812 }
++00813 
++00825 #ifdef LM_INTERFACE
++00826 static struct lm_driver dwc_otg_driver = {
++00827         .drv = {
++00828                 .name = (char *)dwc_driver_name,
++00829                 },
++00830         .probe = dwc_otg_driver_probe,
++00831         .remove = dwc_otg_driver_remove,
++00832 };
++00833 #elif PCI_INTERFACE
++00834 static const struct pci_device_id pci_ids[] = { {
++00835         PCI_DEVICE(0x16c3, 0xabcd),
++00836         .driver_data = (unsigned long) 0xdeadbeef,
++00837         }, { /* end: all zeroes */ }
++00838 };
++00839 MODULE_DEVICE_TABLE(pci, pci_ids);
++00840 
++00841 /* pci driver glue; this is a "new style" PCI driver module */
++00842 static struct pci_driver dwc_otg_driver = {
++00843         .name =         "dwc_otg",
++00844         .id_table =     pci_ids,
++00845 
++00846         .probe =        dwc_otg_driver_probe,
++00847         .remove =       dwc_otg_driver_remove,
++00848 
++00849         .driver = {
++00850                 .name   = (char*)dwc_driver_name,
++00851         },
++00852 };
++00853 #endif
++00854 
++00855 
++00866 static int __init dwc_otg_driver_init(void)
++00867 {
++00868         int retval = 0;
++00869         int error;
++00870         printk(KERN_INFO "%s: version %s\n", dwc_driver_name,
++00871                DWC_DRIVER_VERSION);
++00872 #ifdef LM_INTERFACE
++00873         retval = lm_driver_register(&dwc_otg_driver);
++00874 #elif PCI_INTERFACE
++00875         retval = pci_register_driver(&dwc_otg_driver);
++00876 #endif
++00877         if (retval < 0) {
++00878                 printk(KERN_ERR "%s retval=%d\n", __func__, retval);
++00879                 return retval;
++00880         }
++00881 #ifdef LM_INTERFACE
++00882         error = driver_create_file(&dwc_otg_driver.drv, &driver_attr_version);
++00883         error = driver_create_file(&dwc_otg_driver.drv, &driver_attr_debuglevel);
++00884 #elif PCI_INTERFACE
++00885         error = driver_create_file(&dwc_otg_driver.driver, &driver_attr_version);
++00886         error = driver_create_file(&dwc_otg_driver.driver, &driver_attr_debuglevel);
++00887 #endif
++00888         return retval;
++00889 }
++00890 
++00891 module_init(dwc_otg_driver_init);
++00892 
++00899 static void __exit dwc_otg_driver_cleanup(void)
++00900 {
++00901         printk(KERN_DEBUG "dwc_otg_driver_cleanup()\n");
++00902 
++00903 #ifdef LM_INTERFACE
++00904         driver_remove_file(&dwc_otg_driver.drv, &driver_attr_debuglevel);
++00905         driver_remove_file(&dwc_otg_driver.drv, &driver_attr_version);
++00906         lm_driver_unregister(&dwc_otg_driver);
++00907 #elif PCI_INTERFACE
++00908         driver_remove_file(&dwc_otg_driver.driver, &driver_attr_debuglevel);
++00909         driver_remove_file(&dwc_otg_driver.driver, &driver_attr_version);
++00910         pci_unregister_driver(&dwc_otg_driver);
++00911 #endif
++00912 
++00913         printk(KERN_INFO "%s module removed\n", dwc_driver_name);
++00914 }
++00915 module_exit(dwc_otg_driver_cleanup);
++00916 
++00917 MODULE_DESCRIPTION(DWC_DRIVER_DESC);
++00918 MODULE_AUTHOR("Synopsys Inc.");
++00919 MODULE_LICENSE("GPL");
++00920 
++00921 module_param_named(otg_cap, dwc_otg_module_params.otg_cap, int, 0444);
++00922 MODULE_PARM_DESC(otg_cap, "OTG Capabilities 0=HNP&SRP 1=SRP Only 2=None");
++00923 module_param_named(opt, dwc_otg_module_params.opt, int, 0444);
++00924 MODULE_PARM_DESC(opt, "OPT Mode");
++00925 module_param_named(dma_enable, dwc_otg_module_params.dma_enable, int, 0444);
++00926 MODULE_PARM_DESC(dma_enable, "DMA Mode 0=Slave 1=DMA enabled");
++00927 
++00928 module_param_named(dma_desc_enable, dwc_otg_module_params.dma_desc_enable, int,
++00929                    0444);
++00930 MODULE_PARM_DESC(dma_desc_enable,
++00931                  "DMA Desc Mode 0=Address DMA 1=DMA Descriptor enabled");
++00932 
++00933 module_param_named(dma_burst_size, dwc_otg_module_params.dma_burst_size, int,
++00934                    0444);
++00935 MODULE_PARM_DESC(dma_burst_size,
++00936                  "DMA Burst Size 1, 4, 8, 16, 32, 64, 128, 256");
++00937 module_param_named(speed, dwc_otg_module_params.speed, int, 0444);
++00938 MODULE_PARM_DESC(speed, "Speed 0=High Speed 1=Full Speed");
++00939 module_param_named(host_support_fs_ls_low_power,
++00940                    dwc_otg_module_params.host_support_fs_ls_low_power, int,
++00941                    0444);
++00942 MODULE_PARM_DESC(host_support_fs_ls_low_power,
++00943                  "Support Low Power w/FS or LS 0=Support 1=Don't Support");
++00944 module_param_named(host_ls_low_power_phy_clk,
++00945                    dwc_otg_module_params.host_ls_low_power_phy_clk, int, 0444);
++00946 MODULE_PARM_DESC(host_ls_low_power_phy_clk,
++00947                  "Low Speed Low Power Clock 0=48Mhz 1=6Mhz");
++00948 module_param_named(enable_dynamic_fifo,
++00949                    dwc_otg_module_params.enable_dynamic_fifo, int, 0444);
++00950 MODULE_PARM_DESC(enable_dynamic_fifo, "0=cC Setting 1=Allow Dynamic Sizing");
++00951 module_param_named(data_fifo_size, dwc_otg_module_params.data_fifo_size, int,
++00952                    0444);
++00953 MODULE_PARM_DESC(data_fifo_size,
++00954                  "Total number of words in the data FIFO memory 32-32768");
++00955 module_param_named(dev_rx_fifo_size, dwc_otg_module_params.dev_rx_fifo_size,
++00956                    int, 0444);
++00957 MODULE_PARM_DESC(dev_rx_fifo_size, "Number of words in the Rx FIFO 16-32768");
++00958 module_param_named(dev_nperio_tx_fifo_size,
++00959                    dwc_otg_module_params.dev_nperio_tx_fifo_size, int, 0444);
++00960 MODULE_PARM_DESC(dev_nperio_tx_fifo_size,
++00961                  "Number of words in the non-periodic Tx FIFO 16-32768");
++00962 module_param_named(dev_perio_tx_fifo_size_1,
++00963                    dwc_otg_module_params.dev_perio_tx_fifo_size[0], int, 0444);
++00964 MODULE_PARM_DESC(dev_perio_tx_fifo_size_1,
++00965                  "Number of words in the periodic Tx FIFO 4-768");
++00966 module_param_named(dev_perio_tx_fifo_size_2,
++00967                    dwc_otg_module_params.dev_perio_tx_fifo_size[1], int, 0444);
++00968 MODULE_PARM_DESC(dev_perio_tx_fifo_size_2,
++00969                  "Number of words in the periodic Tx FIFO 4-768");
++00970 module_param_named(dev_perio_tx_fifo_size_3,
++00971                    dwc_otg_module_params.dev_perio_tx_fifo_size[2], int, 0444);
++00972 MODULE_PARM_DESC(dev_perio_tx_fifo_size_3,
++00973                  "Number of words in the periodic Tx FIFO 4-768");
++00974 module_param_named(dev_perio_tx_fifo_size_4,
++00975                    dwc_otg_module_params.dev_perio_tx_fifo_size[3], int, 0444);
++00976 MODULE_PARM_DESC(dev_perio_tx_fifo_size_4,
++00977                  "Number of words in the periodic Tx FIFO 4-768");
++00978 module_param_named(dev_perio_tx_fifo_size_5,
++00979                    dwc_otg_module_params.dev_perio_tx_fifo_size[4], int, 0444);
++00980 MODULE_PARM_DESC(dev_perio_tx_fifo_size_5,
++00981                  "Number of words in the periodic Tx FIFO 4-768");
++00982 module_param_named(dev_perio_tx_fifo_size_6,
++00983                    dwc_otg_module_params.dev_perio_tx_fifo_size[5], int, 0444);
++00984 MODULE_PARM_DESC(dev_perio_tx_fifo_size_6,
++00985                  "Number of words in the periodic Tx FIFO 4-768");
++00986 module_param_named(dev_perio_tx_fifo_size_7,
++00987                    dwc_otg_module_params.dev_perio_tx_fifo_size[6], int, 0444);
++00988 MODULE_PARM_DESC(dev_perio_tx_fifo_size_7,
++00989                  "Number of words in the periodic Tx FIFO 4-768");
++00990 module_param_named(dev_perio_tx_fifo_size_8,
++00991                    dwc_otg_module_params.dev_perio_tx_fifo_size[7], int, 0444);
++00992 MODULE_PARM_DESC(dev_perio_tx_fifo_size_8,
++00993                  "Number of words in the periodic Tx FIFO 4-768");
++00994 module_param_named(dev_perio_tx_fifo_size_9,
++00995                    dwc_otg_module_params.dev_perio_tx_fifo_size[8], int, 0444);
++00996 MODULE_PARM_DESC(dev_perio_tx_fifo_size_9,
++00997                  "Number of words in the periodic Tx FIFO 4-768");
++00998 module_param_named(dev_perio_tx_fifo_size_10,
++00999                    dwc_otg_module_params.dev_perio_tx_fifo_size[9], int, 0444);
++01000 MODULE_PARM_DESC(dev_perio_tx_fifo_size_10,
++01001                  "Number of words in the periodic Tx FIFO 4-768");
++01002 module_param_named(dev_perio_tx_fifo_size_11,
++01003                    dwc_otg_module_params.dev_perio_tx_fifo_size[10], int, 0444);
++01004 MODULE_PARM_DESC(dev_perio_tx_fifo_size_11,
++01005                  "Number of words in the periodic Tx FIFO 4-768");
++01006 module_param_named(dev_perio_tx_fifo_size_12,
++01007                    dwc_otg_module_params.dev_perio_tx_fifo_size[11], int, 0444);
++01008 MODULE_PARM_DESC(dev_perio_tx_fifo_size_12,
++01009                  "Number of words in the periodic Tx FIFO 4-768");
++01010 module_param_named(dev_perio_tx_fifo_size_13,
++01011                    dwc_otg_module_params.dev_perio_tx_fifo_size[12], int, 0444);
++01012 MODULE_PARM_DESC(dev_perio_tx_fifo_size_13,
++01013                  "Number of words in the periodic Tx FIFO 4-768");
++01014 module_param_named(dev_perio_tx_fifo_size_14,
++01015                    dwc_otg_module_params.dev_perio_tx_fifo_size[13], int, 0444);
++01016 MODULE_PARM_DESC(dev_perio_tx_fifo_size_14,
++01017                  "Number of words in the periodic Tx FIFO 4-768");
++01018 module_param_named(dev_perio_tx_fifo_size_15,
++01019                    dwc_otg_module_params.dev_perio_tx_fifo_size[14], int, 0444);
++01020 MODULE_PARM_DESC(dev_perio_tx_fifo_size_15,
++01021                  "Number of words in the periodic Tx FIFO 4-768");
++01022 module_param_named(host_rx_fifo_size, dwc_otg_module_params.host_rx_fifo_size,
++01023                    int, 0444);
++01024 MODULE_PARM_DESC(host_rx_fifo_size, "Number of words in the Rx FIFO 16-32768");
++01025 module_param_named(host_nperio_tx_fifo_size,
++01026                    dwc_otg_module_params.host_nperio_tx_fifo_size, int, 0444);
++01027 MODULE_PARM_DESC(host_nperio_tx_fifo_size,
++01028                  "Number of words in the non-periodic Tx FIFO 16-32768");
++01029 module_param_named(host_perio_tx_fifo_size,
++01030                    dwc_otg_module_params.host_perio_tx_fifo_size, int, 0444);
++01031 MODULE_PARM_DESC(host_perio_tx_fifo_size,
++01032                  "Number of words in the host periodic Tx FIFO 16-32768");
++01033 module_param_named(max_transfer_size, dwc_otg_module_params.max_transfer_size,
++01034                    int, 0444);
++01036 MODULE_PARM_DESC(max_transfer_size,
++01037                  "The maximum transfer size supported in bytes 2047-65535");
++01038 module_param_named(max_packet_count, dwc_otg_module_params.max_packet_count,
++01039                    int, 0444);
++01040 MODULE_PARM_DESC(max_packet_count,
++01041                  "The maximum number of packets in a transfer 15-511");
++01042 module_param_named(host_channels, dwc_otg_module_params.host_channels, int,
++01043                    0444);
++01044 MODULE_PARM_DESC(host_channels,
++01045                  "The number of host channel registers to use 1-16");
++01046 module_param_named(dev_endpoints, dwc_otg_module_params.dev_endpoints, int,
++01047                    0444);
++01048 MODULE_PARM_DESC(dev_endpoints,
++01049                  "The number of endpoints in addition to EP0 available for device mode 1-15");
++01050 module_param_named(phy_type, dwc_otg_module_params.phy_type, int, 0444);
++01051 MODULE_PARM_DESC(phy_type, "0=Reserved 1=UTMI+ 2=ULPI");
++01052 module_param_named(phy_utmi_width, dwc_otg_module_params.phy_utmi_width, int,
++01053                    0444);
++01054 MODULE_PARM_DESC(phy_utmi_width, "Specifies the UTMI+ Data Width 8 or 16 bits");
++01055 module_param_named(phy_ulpi_ddr, dwc_otg_module_params.phy_ulpi_ddr, int, 0444);
++01056 MODULE_PARM_DESC(phy_ulpi_ddr,
++01057                  "ULPI at double or single data rate 0=Single 1=Double");
++01058 module_param_named(phy_ulpi_ext_vbus, dwc_otg_module_params.phy_ulpi_ext_vbus,
++01059                    int, 0444);
++01060 MODULE_PARM_DESC(phy_ulpi_ext_vbus,
++01061                  "ULPI PHY using internal or external vbus 0=Internal");
++01062 module_param_named(i2c_enable, dwc_otg_module_params.i2c_enable, int, 0444);
++01063 MODULE_PARM_DESC(i2c_enable, "FS PHY Interface");
++01064 module_param_named(ulpi_fs_ls, dwc_otg_module_params.ulpi_fs_ls, int, 0444);
++01065 MODULE_PARM_DESC(ulpi_fs_ls, "ULPI PHY FS/LS mode only");
++01066 module_param_named(ts_dline, dwc_otg_module_params.ts_dline, int, 0444);
++01067 MODULE_PARM_DESC(ts_dline, "Term select Dline pulsing for all PHYs");
++01068 module_param_named(debug, g_dbg_lvl, int, 0444);
++01069 MODULE_PARM_DESC(debug, "");
++01070 
++01071 module_param_named(en_multiple_tx_fifo,
++01072                    dwc_otg_module_params.en_multiple_tx_fifo, int, 0444);
++01073 MODULE_PARM_DESC(en_multiple_tx_fifo,
++01074                  "Dedicated Non Periodic Tx FIFOs 0=disabled 1=enabled");
++01075 module_param_named(dev_tx_fifo_size_1,
++01076                    dwc_otg_module_params.dev_tx_fifo_size[0], int, 0444);
++01077 MODULE_PARM_DESC(dev_tx_fifo_size_1, "Number of words in the Tx FIFO 4-768");
++01078 module_param_named(dev_tx_fifo_size_2,
++01079                    dwc_otg_module_params.dev_tx_fifo_size[1], int, 0444);
++01080 MODULE_PARM_DESC(dev_tx_fifo_size_2, "Number of words in the Tx FIFO 4-768");
++01081 module_param_named(dev_tx_fifo_size_3,
++01082                    dwc_otg_module_params.dev_tx_fifo_size[2], int, 0444);
++01083 MODULE_PARM_DESC(dev_tx_fifo_size_3, "Number of words in the Tx FIFO 4-768");
++01084 module_param_named(dev_tx_fifo_size_4,
++01085                    dwc_otg_module_params.dev_tx_fifo_size[3], int, 0444);
++01086 MODULE_PARM_DESC(dev_tx_fifo_size_4, "Number of words in the Tx FIFO 4-768");
++01087 module_param_named(dev_tx_fifo_size_5,
++01088                    dwc_otg_module_params.dev_tx_fifo_size[4], int, 0444);
++01089 MODULE_PARM_DESC(dev_tx_fifo_size_5, "Number of words in the Tx FIFO 4-768");
++01090 module_param_named(dev_tx_fifo_size_6,
++01091                    dwc_otg_module_params.dev_tx_fifo_size[5], int, 0444);
++01092 MODULE_PARM_DESC(dev_tx_fifo_size_6, "Number of words in the Tx FIFO 4-768");
++01093 module_param_named(dev_tx_fifo_size_7,
++01094                    dwc_otg_module_params.dev_tx_fifo_size[6], int, 0444);
++01095 MODULE_PARM_DESC(dev_tx_fifo_size_7, "Number of words in the Tx FIFO 4-768");
++01096 module_param_named(dev_tx_fifo_size_8,
++01097                    dwc_otg_module_params.dev_tx_fifo_size[7], int, 0444);
++01098 MODULE_PARM_DESC(dev_tx_fifo_size_8, "Number of words in the Tx FIFO 4-768");
++01099 module_param_named(dev_tx_fifo_size_9,
++01100                    dwc_otg_module_params.dev_tx_fifo_size[8], int, 0444);
++01101 MODULE_PARM_DESC(dev_tx_fifo_size_9, "Number of words in the Tx FIFO 4-768");
++01102 module_param_named(dev_tx_fifo_size_10,
++01103                    dwc_otg_module_params.dev_tx_fifo_size[9], int, 0444);
++01104 MODULE_PARM_DESC(dev_tx_fifo_size_10, "Number of words in the Tx FIFO 4-768");
++01105 module_param_named(dev_tx_fifo_size_11,
++01106                    dwc_otg_module_params.dev_tx_fifo_size[10], int, 0444);
++01107 MODULE_PARM_DESC(dev_tx_fifo_size_11, "Number of words in the Tx FIFO 4-768");
++01108 module_param_named(dev_tx_fifo_size_12,
++01109                    dwc_otg_module_params.dev_tx_fifo_size[11], int, 0444);
++01110 MODULE_PARM_DESC(dev_tx_fifo_size_12, "Number of words in the Tx FIFO 4-768");
++01111 module_param_named(dev_tx_fifo_size_13,
++01112                    dwc_otg_module_params.dev_tx_fifo_size[12], int, 0444);
++01113 MODULE_PARM_DESC(dev_tx_fifo_size_13, "Number of words in the Tx FIFO 4-768");
++01114 module_param_named(dev_tx_fifo_size_14,
++01115                    dwc_otg_module_params.dev_tx_fifo_size[13], int, 0444);
++01116 MODULE_PARM_DESC(dev_tx_fifo_size_14, "Number of words in the Tx FIFO 4-768");
++01117 module_param_named(dev_tx_fifo_size_15,
++01118                    dwc_otg_module_params.dev_tx_fifo_size[14], int, 0444);
++01119 MODULE_PARM_DESC(dev_tx_fifo_size_15, "Number of words in the Tx FIFO 4-768");
++01120 
++01121 module_param_named(thr_ctl, dwc_otg_module_params.thr_ctl, int, 0444);
++01122 MODULE_PARM_DESC(thr_ctl,
++01123                  "Thresholding enable flag bit 0 - non ISO Tx thr., 1 - ISO Tx thr., 2 - Rx thr.- bit 0=disabled 1=enabled");
++01124 module_param_named(tx_thr_length, dwc_otg_module_params.tx_thr_length, int,
++01125                    0444);
++01126 MODULE_PARM_DESC(tx_thr_length, "Tx Threshold length in 32 bit DWORDs");
++01127 module_param_named(rx_thr_length, dwc_otg_module_params.rx_thr_length, int,
++01128                    0444);
++01129 MODULE_PARM_DESC(rx_thr_length, "Rx Threshold length in 32 bit DWORDs");
++01130 
++01131 module_param_named(pti_enable, dwc_otg_module_params.pti_enable, int, 0444);
++01132 module_param_named(mpi_enable, dwc_otg_module_params.mpi_enable, int, 0444);
++01133 module_param_named(lpm_enable, dwc_otg_module_params.lpm_enable, int, 0444);
++01134 MODULE_PARM_DESC(lpm_enable, "LPM Enable 0=LPM Disabled 1=LPM Enabled");
++01135 module_param_named(ic_usb_cap, dwc_otg_module_params.ic_usb_cap, int, 0444);
++01136 MODULE_PARM_DESC(ic_usb_cap,
++01137                  "IC_USB Capability 0=IC_USB Disabled 1=IC_USB Enabled");
++01138 module_param_named(ahb_thr_ratio, dwc_otg_module_params.ahb_thr_ratio, int, 0444);
++01139 MODULE_PARM_DESC(ahb_thr_ratio, "AHB Threshold Ratio");
++01140 
++
Generated on Tue May 5 02:22:48 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__driver_8c.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__driver_8c.html 2013-07-26 19:31:20.000000000 +0000 +@@ -0,0 +1,719 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_driver.c File Reference ++ ++ ++ ++ ++
++
++
++
++

dwc_otg_driver.c File Reference

The dwc_otg_driver module provides the initialization and cleanup entry points for the DWC_otg driver. More... ++

++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/moduleparam.h>
++#include <linux/init.h>
++#include <linux/device.h>
++#include <linux/errno.h>
++#include <linux/types.h>
++#include <linux/stat.h>
++#include <linux/version.h>
++#include <linux/interrupt.h>
++#include <linux/irq.h>
++#include <asm/io.h>
++#include "dwc_os.h"
++#include "dwc_otg_dbg.h"
++#include "dwc_otg_driver.h"
++#include "dwc_otg_attr.h"
++#include "dwc_otg_core_if.h"
++#include "dwc_otg_pcd_if.h"
++#include "dwc_otg_hcd_if.h"
++ ++

++Go to the source code of this file. ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++

Data Structures

struct  dwc_otg_driver_module_params

Defines

++#define DWC_DRIVER_VERSION   "2.90a 23-APR-2009"
++#define DWC_DRIVER_DESC   "HS OTG USB Controller driver"

Functions

++int pcd_init ()
 This function initialized the PCD portion of the driver.
int hcd_init ()
 Initializes the HCD.
++int pcd_remove ()
 Cleanup the PCD.
void hcd_remove ()
 Removes the HCD.
++static ssize_t version_show (struct device_driver *dev, char *buf)
 This function shows the Driver Version.
++static DRIVER_ATTR (version, S_IRUGO, version_show, NULL)
++static ssize_t dbg_level_show (struct device_driver *drv, char *buf)
 This function shows the driver Debug Level.
++static ssize_t dbg_level_store (struct device_driver *drv, const char *buf, size_t count)
 This function stores the driver Debug Level.
++static DRIVER_ATTR (debuglevel, S_IRUGO|S_IWUSR, dbg_level_show, dbg_level_store)
++static int set_parameters (dwc_otg_core_if_t *core_if)
 This function is called during module intialization to pass module parameters to the DWC_OTG CORE.
++static irqreturn_t dwc_otg_common_irq (int irq, void *dev)
 This function is the top level interrupt handler for the Common (Device and host modes) interrupts.
static void dwc_otg_driver_remove ()
 This function is called when a lm_device is unregistered with the dwc_otg_driver.
static int dwc_otg_driver_probe ()
 This function is called when an lm_device is bound to a dwc_otg_driver.
static int __init dwc_otg_driver_init (void)
 This function is called when the dwc_otg_driver is installed with the insmod command.
++ module_init (dwc_otg_driver_init)
static void __exit dwc_otg_driver_cleanup (void)
 This function is called when the driver is removed from the kernel with the rmmod command.
++ module_exit (dwc_otg_driver_cleanup)
++ MODULE_DESCRIPTION (DWC_DRIVER_DESC)
++ MODULE_AUTHOR ("Synopsys Inc.")
++ MODULE_LICENSE ("GPL")
++ module_param_named (otg_cap, dwc_otg_module_params.otg_cap, int, 0444)
++ MODULE_PARM_DESC (otg_cap,"OTG Capabilities 0=HNP&SRP 1=SRP Only 2=None")
++ module_param_named (opt, dwc_otg_module_params.opt, int, 0444)
++ MODULE_PARM_DESC (opt,"OPT Mode")
++ module_param_named (dma_enable, dwc_otg_module_params.dma_enable, int, 0444)
++ MODULE_PARM_DESC (dma_enable,"DMA Mode 0=Slave 1=DMA enabled")
++ module_param_named (dma_desc_enable, dwc_otg_module_params.dma_desc_enable, int, 0444)
++ MODULE_PARM_DESC (dma_desc_enable,"DMA Desc Mode 0=Address DMA 1=DMA Descriptor enabled")
++ module_param_named (dma_burst_size, dwc_otg_module_params.dma_burst_size, int, 0444)
++ MODULE_PARM_DESC (dma_burst_size,"DMA Burst Size 1, 4, 8, 16, 32, 64, 128, 256")
++ module_param_named (speed, dwc_otg_module_params.speed, int, 0444)
++ MODULE_PARM_DESC (speed,"Speed 0=High Speed 1=Full Speed")
++ module_param_named (host_support_fs_ls_low_power, dwc_otg_module_params.host_support_fs_ls_low_power, int, 0444)
++ MODULE_PARM_DESC (host_support_fs_ls_low_power,"Support Low Power w/FS or LS 0=Support 1=Don't Support")
++ module_param_named (host_ls_low_power_phy_clk, dwc_otg_module_params.host_ls_low_power_phy_clk, int, 0444)
++ MODULE_PARM_DESC (host_ls_low_power_phy_clk,"Low Speed Low Power Clock 0=48Mhz 1=6Mhz")
++ module_param_named (enable_dynamic_fifo, dwc_otg_module_params.enable_dynamic_fifo, int, 0444)
++ MODULE_PARM_DESC (enable_dynamic_fifo,"0=cC Setting 1=Allow Dynamic Sizing")
++ module_param_named (data_fifo_size, dwc_otg_module_params.data_fifo_size, int, 0444)
++ MODULE_PARM_DESC (data_fifo_size,"Total number of words in the data FIFO memory 32-32768")
++ module_param_named (dev_rx_fifo_size, dwc_otg_module_params.dev_rx_fifo_size, int, 0444)
++ MODULE_PARM_DESC (dev_rx_fifo_size,"Number of words in the Rx FIFO 16-32768")
++ module_param_named (dev_nperio_tx_fifo_size, dwc_otg_module_params.dev_nperio_tx_fifo_size, int, 0444)
++ MODULE_PARM_DESC (dev_nperio_tx_fifo_size,"Number of words in the non-periodic Tx FIFO 16-32768")
++ module_param_named (dev_perio_tx_fifo_size_1, dwc_otg_module_params.dev_perio_tx_fifo_size[0], int, 0444)
++ MODULE_PARM_DESC (dev_perio_tx_fifo_size_1,"Number of words in the periodic Tx FIFO 4-768")
++ module_param_named (dev_perio_tx_fifo_size_2, dwc_otg_module_params.dev_perio_tx_fifo_size[1], int, 0444)
++ MODULE_PARM_DESC (dev_perio_tx_fifo_size_2,"Number of words in the periodic Tx FIFO 4-768")
++ module_param_named (dev_perio_tx_fifo_size_3, dwc_otg_module_params.dev_perio_tx_fifo_size[2], int, 0444)
++ MODULE_PARM_DESC (dev_perio_tx_fifo_size_3,"Number of words in the periodic Tx FIFO 4-768")
++ module_param_named (dev_perio_tx_fifo_size_4, dwc_otg_module_params.dev_perio_tx_fifo_size[3], int, 0444)
++ MODULE_PARM_DESC (dev_perio_tx_fifo_size_4,"Number of words in the periodic Tx FIFO 4-768")
++ module_param_named (dev_perio_tx_fifo_size_5, dwc_otg_module_params.dev_perio_tx_fifo_size[4], int, 0444)
++ MODULE_PARM_DESC (dev_perio_tx_fifo_size_5,"Number of words in the periodic Tx FIFO 4-768")
++ module_param_named (dev_perio_tx_fifo_size_6, dwc_otg_module_params.dev_perio_tx_fifo_size[5], int, 0444)
++ MODULE_PARM_DESC (dev_perio_tx_fifo_size_6,"Number of words in the periodic Tx FIFO 4-768")
++ module_param_named (dev_perio_tx_fifo_size_7, dwc_otg_module_params.dev_perio_tx_fifo_size[6], int, 0444)
++ MODULE_PARM_DESC (dev_perio_tx_fifo_size_7,"Number of words in the periodic Tx FIFO 4-768")
++ module_param_named (dev_perio_tx_fifo_size_8, dwc_otg_module_params.dev_perio_tx_fifo_size[7], int, 0444)
++ MODULE_PARM_DESC (dev_perio_tx_fifo_size_8,"Number of words in the periodic Tx FIFO 4-768")
++ module_param_named (dev_perio_tx_fifo_size_9, dwc_otg_module_params.dev_perio_tx_fifo_size[8], int, 0444)
++ MODULE_PARM_DESC (dev_perio_tx_fifo_size_9,"Number of words in the periodic Tx FIFO 4-768")
++ module_param_named (dev_perio_tx_fifo_size_10, dwc_otg_module_params.dev_perio_tx_fifo_size[9], int, 0444)
++ MODULE_PARM_DESC (dev_perio_tx_fifo_size_10,"Number of words in the periodic Tx FIFO 4-768")
++ module_param_named (dev_perio_tx_fifo_size_11, dwc_otg_module_params.dev_perio_tx_fifo_size[10], int, 0444)
++ MODULE_PARM_DESC (dev_perio_tx_fifo_size_11,"Number of words in the periodic Tx FIFO 4-768")
++ module_param_named (dev_perio_tx_fifo_size_12, dwc_otg_module_params.dev_perio_tx_fifo_size[11], int, 0444)
++ MODULE_PARM_DESC (dev_perio_tx_fifo_size_12,"Number of words in the periodic Tx FIFO 4-768")
++ module_param_named (dev_perio_tx_fifo_size_13, dwc_otg_module_params.dev_perio_tx_fifo_size[12], int, 0444)
++ MODULE_PARM_DESC (dev_perio_tx_fifo_size_13,"Number of words in the periodic Tx FIFO 4-768")
++ module_param_named (dev_perio_tx_fifo_size_14, dwc_otg_module_params.dev_perio_tx_fifo_size[13], int, 0444)
++ MODULE_PARM_DESC (dev_perio_tx_fifo_size_14,"Number of words in the periodic Tx FIFO 4-768")
++ module_param_named (dev_perio_tx_fifo_size_15, dwc_otg_module_params.dev_perio_tx_fifo_size[14], int, 0444)
++ MODULE_PARM_DESC (dev_perio_tx_fifo_size_15,"Number of words in the periodic Tx FIFO 4-768")
++ module_param_named (host_rx_fifo_size, dwc_otg_module_params.host_rx_fifo_size, int, 0444)
++ MODULE_PARM_DESC (host_rx_fifo_size,"Number of words in the Rx FIFO 16-32768")
++ module_param_named (host_nperio_tx_fifo_size, dwc_otg_module_params.host_nperio_tx_fifo_size, int, 0444)
++ MODULE_PARM_DESC (host_nperio_tx_fifo_size,"Number of words in the non-periodic Tx FIFO 16-32768")
++ module_param_named (host_perio_tx_fifo_size, dwc_otg_module_params.host_perio_tx_fifo_size, int, 0444)
++ MODULE_PARM_DESC (host_perio_tx_fifo_size,"Number of words in the host periodic Tx FIFO 16-32768")
++ module_param_named (max_transfer_size, dwc_otg_module_params.max_transfer_size, int, 0444)
 MODULE_PARM_DESC (max_transfer_size,"The maximum transfer size supported in bytes 2047-65535")
++ module_param_named (max_packet_count, dwc_otg_module_params.max_packet_count, int, 0444)
++ MODULE_PARM_DESC (max_packet_count,"The maximum number of packets in a transfer 15-511")
++ module_param_named (host_channels, dwc_otg_module_params.host_channels, int, 0444)
++ MODULE_PARM_DESC (host_channels,"The number of host channel registers to use 1-16")
++ module_param_named (dev_endpoints, dwc_otg_module_params.dev_endpoints, int, 0444)
++ MODULE_PARM_DESC (dev_endpoints,"The number of endpoints in addition to EP0 available for device mode 1-15")
++ module_param_named (phy_type, dwc_otg_module_params.phy_type, int, 0444)
++ MODULE_PARM_DESC (phy_type,"0=Reserved 1=UTMI+ 2=ULPI")
++ module_param_named (phy_utmi_width, dwc_otg_module_params.phy_utmi_width, int, 0444)
++ MODULE_PARM_DESC (phy_utmi_width,"Specifies the UTMI+ Data Width 8 or 16 bits")
++ module_param_named (phy_ulpi_ddr, dwc_otg_module_params.phy_ulpi_ddr, int, 0444)
++ MODULE_PARM_DESC (phy_ulpi_ddr,"ULPI at double or single data rate 0=Single 1=Double")
++ module_param_named (phy_ulpi_ext_vbus, dwc_otg_module_params.phy_ulpi_ext_vbus, int, 0444)
++ MODULE_PARM_DESC (phy_ulpi_ext_vbus,"ULPI PHY using internal or external vbus 0=Internal")
++ module_param_named (i2c_enable, dwc_otg_module_params.i2c_enable, int, 0444)
++ MODULE_PARM_DESC (i2c_enable,"FS PHY Interface")
++ module_param_named (ulpi_fs_ls, dwc_otg_module_params.ulpi_fs_ls, int, 0444)
++ MODULE_PARM_DESC (ulpi_fs_ls,"ULPI PHY FS/LS mode only")
++ module_param_named (ts_dline, dwc_otg_module_params.ts_dline, int, 0444)
++ MODULE_PARM_DESC (ts_dline,"Term select Dline pulsing for all PHYs")
++ module_param_named (debug, g_dbg_lvl, int, 0444)
++ MODULE_PARM_DESC (debug,"")
++ module_param_named (en_multiple_tx_fifo, dwc_otg_module_params.en_multiple_tx_fifo, int, 0444)
++ MODULE_PARM_DESC (en_multiple_tx_fifo,"Dedicated Non Periodic Tx FIFOs 0=disabled 1=enabled")
++ module_param_named (dev_tx_fifo_size_1, dwc_otg_module_params.dev_tx_fifo_size[0], int, 0444)
++ MODULE_PARM_DESC (dev_tx_fifo_size_1,"Number of words in the Tx FIFO 4-768")
++ module_param_named (dev_tx_fifo_size_2, dwc_otg_module_params.dev_tx_fifo_size[1], int, 0444)
++ MODULE_PARM_DESC (dev_tx_fifo_size_2,"Number of words in the Tx FIFO 4-768")
++ module_param_named (dev_tx_fifo_size_3, dwc_otg_module_params.dev_tx_fifo_size[2], int, 0444)
++ MODULE_PARM_DESC (dev_tx_fifo_size_3,"Number of words in the Tx FIFO 4-768")
++ module_param_named (dev_tx_fifo_size_4, dwc_otg_module_params.dev_tx_fifo_size[3], int, 0444)
++ MODULE_PARM_DESC (dev_tx_fifo_size_4,"Number of words in the Tx FIFO 4-768")
++ module_param_named (dev_tx_fifo_size_5, dwc_otg_module_params.dev_tx_fifo_size[4], int, 0444)
++ MODULE_PARM_DESC (dev_tx_fifo_size_5,"Number of words in the Tx FIFO 4-768")
++ module_param_named (dev_tx_fifo_size_6, dwc_otg_module_params.dev_tx_fifo_size[5], int, 0444)
++ MODULE_PARM_DESC (dev_tx_fifo_size_6,"Number of words in the Tx FIFO 4-768")
++ module_param_named (dev_tx_fifo_size_7, dwc_otg_module_params.dev_tx_fifo_size[6], int, 0444)
++ MODULE_PARM_DESC (dev_tx_fifo_size_7,"Number of words in the Tx FIFO 4-768")
++ module_param_named (dev_tx_fifo_size_8, dwc_otg_module_params.dev_tx_fifo_size[7], int, 0444)
++ MODULE_PARM_DESC (dev_tx_fifo_size_8,"Number of words in the Tx FIFO 4-768")
++ module_param_named (dev_tx_fifo_size_9, dwc_otg_module_params.dev_tx_fifo_size[8], int, 0444)
++ MODULE_PARM_DESC (dev_tx_fifo_size_9,"Number of words in the Tx FIFO 4-768")
++ module_param_named (dev_tx_fifo_size_10, dwc_otg_module_params.dev_tx_fifo_size[9], int, 0444)
++ MODULE_PARM_DESC (dev_tx_fifo_size_10,"Number of words in the Tx FIFO 4-768")
++ module_param_named (dev_tx_fifo_size_11, dwc_otg_module_params.dev_tx_fifo_size[10], int, 0444)
++ MODULE_PARM_DESC (dev_tx_fifo_size_11,"Number of words in the Tx FIFO 4-768")
++ module_param_named (dev_tx_fifo_size_12, dwc_otg_module_params.dev_tx_fifo_size[11], int, 0444)
++ MODULE_PARM_DESC (dev_tx_fifo_size_12,"Number of words in the Tx FIFO 4-768")
++ module_param_named (dev_tx_fifo_size_13, dwc_otg_module_params.dev_tx_fifo_size[12], int, 0444)
++ MODULE_PARM_DESC (dev_tx_fifo_size_13,"Number of words in the Tx FIFO 4-768")
++ module_param_named (dev_tx_fifo_size_14, dwc_otg_module_params.dev_tx_fifo_size[13], int, 0444)
++ MODULE_PARM_DESC (dev_tx_fifo_size_14,"Number of words in the Tx FIFO 4-768")
++ module_param_named (dev_tx_fifo_size_15, dwc_otg_module_params.dev_tx_fifo_size[14], int, 0444)
++ MODULE_PARM_DESC (dev_tx_fifo_size_15,"Number of words in the Tx FIFO 4-768")
++ module_param_named (thr_ctl, dwc_otg_module_params.thr_ctl, int, 0444)
++ MODULE_PARM_DESC (thr_ctl,"Thresholding enable flag bit 0 - non ISO Tx thr., 1 - ISO Tx thr., 2 - Rx thr.- bit 0=disabled 1=enabled")
++ module_param_named (tx_thr_length, dwc_otg_module_params.tx_thr_length, int, 0444)
++ MODULE_PARM_DESC (tx_thr_length,"Tx Threshold length in 32 bit DWORDs")
++ module_param_named (rx_thr_length, dwc_otg_module_params.rx_thr_length, int, 0444)
++ MODULE_PARM_DESC (rx_thr_length,"Rx Threshold length in 32 bit DWORDs")
++ module_param_named (pti_enable, dwc_otg_module_params.pti_enable, int, 0444)
++ module_param_named (mpi_enable, dwc_otg_module_params.mpi_enable, int, 0444)
++ module_param_named (lpm_enable, dwc_otg_module_params.lpm_enable, int, 0444)
++ MODULE_PARM_DESC (lpm_enable,"LPM Enable 0=LPM Disabled 1=LPM Enabled")
++ module_param_named (ic_usb_cap, dwc_otg_module_params.ic_usb_cap, int, 0444)
++ MODULE_PARM_DESC (ic_usb_cap,"IC_USB Capability 0=IC_USB Disabled 1=IC_USB Enabled")
++ module_param_named (ahb_thr_ratio, dwc_otg_module_params.ahb_thr_ratio, int, 0444)
++ MODULE_PARM_DESC (ahb_thr_ratio,"AHB Threshold Ratio")

Variables

++static const char dwc_driver_name [] = "dwc_otg"
++static struct dwc_otg_driver_module_params dwc_otg_module_params
++uint32_t g_dbg_lvl = 0
 The Debug Level bit-mask variable.
++

Detailed Description

++The dwc_otg_driver module provides the initialization and cleanup entry points for the DWC_otg driver. ++

++This module will be dynamically installed after Linux is booted using the insmod command. When the module is installed, the dwc_otg_driver_init function is called. When the module is removed (using rmmod), the dwc_otg_driver_cleanup function is called.

++This module also defines a data structure for the dwc_otg_driver, which is used in conjunction with the standard ARM lm_device structure. These structures allow the OTG driver to comply with the standard Linux driver model in which devices and drivers are registered with a bus driver. This has the benefit that Linux can expose attributes of the driver and device in its special sysfs file system. Users can then read or write files in this file system to perform diagnostics on the driver components or the device. ++

++Definition in file dwc_otg_driver.c.

Function Documentation

++ ++
++
++ ++ ++ ++ ++ ++ ++ ++ ++
int hcd_init (  ) 
++
++
++ ++

++Initializes the HCD. ++

++This function allocates memory for and initializes the static parts of the usb_hcd and dwc_otg_hcd structures. It also registers the USB bus with the core and calls the hc_driver->start() function. It returns a negative error on failure. ++

++Definition at line 327 of file dwc_otg_hcd_linux.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++
void hcd_remove (  ) 
++
++
++ ++

++Removes the HCD. ++

++Frees memory and resources associated with the HCD and deregisters the bus. ++

++Definition at line 417 of file dwc_otg_hcd_linux.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++
static void dwc_otg_driver_remove (  )  [static]
++
++
++ ++

++This function is called when a lm_device is unregistered with the dwc_otg_driver. ++

++This happens, for example, when the rmmod command is executed. The device may or may not be electrically present. If it is present, the driver stops device processing. Any resources used on behalf of this device are freed.

++

Parameters:
++ ++ ++
_dev 
++
++ ++

++Definition at line 525 of file dwc_otg_driver.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++
static int dwc_otg_driver_probe (  )  [static]
++
++
++ ++

++This function is called when an lm_device is bound to a dwc_otg_driver. ++

++It creates the driver components required to control the device (CIL, HCD, and PCD) and it initializes the device. The driver components are stored in a dwc_otg_device structure. A reference to the dwc_otg_device is saved in the lm_device. This allows the driver to access the dwc_otg_device structure on subsequent calls to driver methods for this device.

++

Parameters:
++ ++ ++
_dev Bus device
++
++ ++

++Definition at line 608 of file dwc_otg_driver.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
static int __init dwc_otg_driver_init (void   )  [static]
++
++
++ ++

++This function is called when the dwc_otg_driver is installed with the insmod command. ++

++It registers the dwc_otg_driver structure with the appropriate bus driver. This will cause the dwc_otg_driver_probe function to be called. In addition, the bus driver will automatically expose attributes defined for the device and driver in the special sysfs file system.

++

Returns:
++ ++

++Definition at line 866 of file dwc_otg_driver.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
static void __exit dwc_otg_driver_cleanup (void   )  [static]
++
++
++ ++

++This function is called when the driver is removed from the kernel with the rmmod command. ++

++The driver unregisters itself with its bus driver. ++

++Definition at line 899 of file dwc_otg_driver.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
MODULE_PARM_DESC (max_transfer_size ,
"The maximum transfer size supported in bytes 2047-65535"  
)
++
++
++ ++

++

Todo:
Set the max to 512K, modify checks
++ ++
++

++

Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__driver_8h-source.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__driver_8h-source.html 2013-07-26 19:31:20.000000000 +0000 +@@ -0,0 +1,110 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_driver.h Source File ++ ++ ++ ++ ++
++
++
++
++

dwc_otg_driver.h

Go to the documentation of this file.
00001 /* ==========================================================================
++00002  * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_driver.h $
++00003  * $Revision: #16 $
++00004  * $Date: 2009/04/03 $
++00005  * $Change: 1225160 $
++00006  *
++00007  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
++00008  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
++00009  * otherwise expressly agreed to in writing between Synopsys and you.
++00010  * 
++00011  * The Software IS NOT an item of Licensed Software or Licensed Product under
++00012  * any End User Software License Agreement or Agreement for Licensed Product
++00013  * with Synopsys or any supplement thereto. You are permitted to use and
++00014  * redistribute this Software in source and binary forms, with or without
++00015  * modification, provided that redistributions of source code must retain this
++00016  * notice. You may not view, use, disclose, copy or distribute this file or
++00017  * any information contained herein except pursuant to this license grant from
++00018  * Synopsys. If you do not agree with this notice, including the disclaimer
++00019  * below, then you are not authorized to use the Software.
++00020  * 
++00021  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
++00022  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++00023  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++00024  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
++00025  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++00026  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
++00027  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
++00028  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
++00029  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
++00030  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
++00031  * DAMAGE.
++00032  * ========================================================================== */
++00033 
++00034 #ifndef __DWC_OTG_DRIVER_H__
++00035 #define __DWC_OTG_DRIVER_H__
++00036 
++00040 #include "dwc_otg_core_if.h"
++00041 
++00042 /* Type declarations */
++00043 struct dwc_otg_pcd;
++00044 struct dwc_otg_hcd;
++00045 
++00046 #ifdef  PCI_INTERFACE
++00047 #include <linux/pci.h>
++00048 #endif
++00049 
++00050 
++00051 
++00056 typedef struct dwc_otg_device {
++00058         void *base;
++00059 
++00060 #ifdef LM_INTERFACE
++00061         struct lm_device *lmdev;
++00062 #elif  PCI_INTERFACE
++00063         int rsrc_start;
++00064         int rsrc_len;
++00065 #endif
++00066 
++00068         dwc_otg_core_if_t *core_if;
++00069 
++00071         uint32_t reg_offset;
++00072 
++00074         struct dwc_otg_pcd *pcd;
++00075 
++00077         struct dwc_otg_hcd *hcd;
++00078 
++00080         uint8_t common_irq_installed;
++00081 
++00082 } dwc_otg_device_t;
++00083 
++00084 /*We must clear S3C24XX_EINTPEND external interrupt register 
++00085  * because after clearing in this register trigerred IRQ from 
++00086  * H/W core in kernel interrupt can be occured again before OTG
++00087  * handlers clear all IRQ sources of Core registers because of
++00088  * timing latencies and Low Level IRQ Type.
++00089  */
++00090 #ifdef CONFIG_MACH_IPMATE
++00091 #define  S3C2410X_CLEAR_EINTPEND()   \
++00092 do { \
++00093         __raw_writel(1UL << 11,S3C24XX_EINTPEND); \
++00094 } while (0)
++00095 #else
++00096 #define  S3C2410X_CLEAR_EINTPEND()   do { } while (0)
++00097 #endif
++00098 
++00099 #endif
++
Generated on Tue May 5 02:22:48 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__driver_8h.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__driver_8h.html 2013-07-26 19:31:20.000000000 +0000 +@@ -0,0 +1,50 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_driver.h File Reference ++ ++ ++ ++ ++
++
++
++
++

dwc_otg_driver.h File Reference

This file contains the interface to the Linux driver. More... ++

++#include "dwc_otg_core_if.h"
++ ++

++Go to the source code of this file. ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++

Data Structures

struct  dwc_otg_device
 This structure is a wrapper that encapsulates the driver components used to manage a single DWC_otg controller. More...

Defines

++#define S3C2410X_CLEAR_EINTPEND()   do { } while (0)

Typedefs

++typedef dwc_otg_device dwc_otg_device_t
 This structure is a wrapper that encapsulates the driver components used to manage a single DWC_otg controller.
++

Detailed Description

++This file contains the interface to the Linux driver. ++

++ ++

++Definition in file dwc_otg_driver.h.

Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__hcd_8c-source.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__hcd_8c-source.html 2013-07-26 19:31:21.000000000 +0000 +@@ -0,0 +1,2946 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_hcd.c Source File ++ ++ ++ ++ ++
++
++
++
++

dwc_otg_hcd.c

Go to the documentation of this file.
00001 /* ==========================================================================
++00002  * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd.c $
++00003  * $Revision: #87 $
++00004  * $Date: 2009/04/23 $
++00005  * $Change: 1239143 $
++00006  *
++00007  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
++00008  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
++00009  * otherwise expressly agreed to in writing between Synopsys and you.
++00010  *
++00011  * The Software IS NOT an item of Licensed Software or Licensed Product under
++00012  * any End User Software License Agreement or Agreement for Licensed Product
++00013  * with Synopsys or any supplement thereto. You are permitted to use and
++00014  * redistribute this Software in source and binary forms, with or without
++00015  * modification, provided that redistributions of source code must retain this
++00016  * notice. You may not view, use, disclose, copy or distribute this file or
++00017  * any information contained herein except pursuant to this license grant from
++00018  * Synopsys. If you do not agree with this notice, including the disclaimer
++00019  * below, then you are not authorized to use the Software.
++00020  *
++00021  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
++00022  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++00023  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++00024  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
++00025  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++00026  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
++00027  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
++00028  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
++00029  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
++00030  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
++00031  * DAMAGE.
++00032  * ========================================================================== */
++00033 #ifndef DWC_DEVICE_ONLY
++00034 
++00042 #include "dwc_otg_hcd.h"
++00043 #include "dwc_otg_regs.h"
++00044                 
++00045 dwc_otg_hcd_t *dwc_otg_hcd_alloc_hcd(void)
++00046 {
++00047         return dwc_alloc(sizeof(dwc_otg_hcd_t));
++00048 }
++00049 
++00054 void dwc_otg_hcd_connect_timeout(void *ptr)
++00055 {
++00056         DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, ptr);
++00057         DWC_PRINTF("Connect Timeout\n");
++00058         __DWC_ERROR("Device Not Connected/Responding\n");
++00059 }
++00060 
++00061 #ifdef DEBUG
++00062 static void dump_channel_info(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
++00063 {
++00064         if (qh->channel != NULL) {
++00065                 dwc_hc_t *hc = qh->channel;
++00066                 dwc_list_link_t *item;
++00067                 dwc_otg_qh_t *qh_item;
++00068                 int num_channels = hcd->core_if->core_params->host_channels;
++00069                 int i;
++00070 
++00071                 dwc_otg_hc_regs_t *hc_regs;
++00072                 hcchar_data_t hcchar;
++00073                 hcsplt_data_t hcsplt;
++00074                 hctsiz_data_t hctsiz;
++00075                 uint32_t hcdma;
++00076 
++00077                 hc_regs = hcd->core_if->host_if->hc_regs[hc->hc_num];
++00078                 hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
++00079                 hcsplt.d32 = dwc_read_reg32(&hc_regs->hcsplt);
++00080                 hctsiz.d32 = dwc_read_reg32(&hc_regs->hctsiz);
++00081                 hcdma = dwc_read_reg32(&hc_regs->hcdma);
++00082 
++00083                 DWC_PRINTF("  Assigned to channel %p:\n", hc);
++00084                 DWC_PRINTF("    hcchar 0x%08x, hcsplt 0x%08x\n", hcchar.d32,
++00085                            hcsplt.d32);
++00086                 DWC_PRINTF("    hctsiz 0x%08x, hcdma 0x%08x\n", hctsiz.d32,
++00087                            hcdma);
++00088                 DWC_PRINTF("    dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
++00089                            hc->dev_addr, hc->ep_num, hc->ep_is_in);
++00090                 DWC_PRINTF("    ep_type: %d\n", hc->ep_type);
++00091                 DWC_PRINTF("    max_packet: %d\n", hc->max_packet);
++00092                 DWC_PRINTF("    data_pid_start: %d\n", hc->data_pid_start);
++00093                 DWC_PRINTF("    xfer_started: %d\n", hc->xfer_started);
++00094                 DWC_PRINTF("    halt_status: %d\n", hc->halt_status);
++00095                 DWC_PRINTF("    xfer_buff: %p\n", hc->xfer_buff);
++00096                 DWC_PRINTF("    xfer_len: %d\n", hc->xfer_len);
++00097                 DWC_PRINTF("    qh: %p\n", hc->qh);
++00098                 DWC_PRINTF("  NP inactive sched:\n");
++00099                 DWC_LIST_FOREACH(item, &hcd->non_periodic_sched_inactive) {
++00100                         qh_item =
++00101                             DWC_LIST_ENTRY(item, dwc_otg_qh_t, qh_list_entry);
++00102                         DWC_PRINTF("    %p\n", qh_item);
++00103                 }
++00104                 DWC_PRINTF("  NP active sched:\n");
++00105                 DWC_LIST_FOREACH(item, &hcd->non_periodic_sched_active) {
++00106                         qh_item =
++00107                             DWC_LIST_ENTRY(item, dwc_otg_qh_t, qh_list_entry);
++00108                         DWC_PRINTF("    %p\n", qh_item);
++00109                 }
++00110                 DWC_PRINTF("  Channels: \n");
++00111                 for (i = 0; i < num_channels; i++) {
++00112                         dwc_hc_t *hc = hcd->hc_ptr_array[i];
++00113                         DWC_PRINTF("    %2d: %p\n", i, hc);
++00114                 }
++00115         }
++00116 }
++00117 #endif                          /* DEBUG */
++00118 
++00123 static void hcd_start_func(void *_vp)
++00124 {
++00125         dwc_otg_hcd_t *hcd = (dwc_otg_hcd_t *) _vp;
++00126 
++00127         DWC_DEBUGPL(DBG_HCDV, "%s() %p\n", __func__, hcd);
++00128         if (hcd) {
++00129                 hcd->fops->start(hcd);
++00130         }
++00131 }
++00132 
++00133 static void del_xfer_timers(dwc_otg_hcd_t * hcd)
++00134 {
++00135 #ifdef DEBUG
++00136         int i;
++00137         int num_channels = hcd->core_if->core_params->host_channels;
++00138         for (i = 0; i < num_channels; i++) {
++00139                 DWC_TIMER_CANCEL(hcd->core_if->hc_xfer_timer[i]);
++00140         }
++00141 #endif
++00142 }
++00143 
++00144 static void del_timers(dwc_otg_hcd_t * hcd)
++00145 {
++00146         del_xfer_timers(hcd);
++00147         DWC_TIMER_CANCEL(hcd->conn_timer);
++00148 }
++00149 
++00154 static void kill_urbs_in_qh_list(dwc_otg_hcd_t * hcd, dwc_list_link_t * qh_list)
++00155 {
++00156         dwc_list_link_t *qh_item;
++00157         dwc_otg_qh_t *qh;
++00158         dwc_otg_qtd_t *qtd, *qtd_tmp;
++00159 
++00160         DWC_LIST_FOREACH(qh_item, qh_list) {
++00161                 qh = DWC_LIST_ENTRY(qh_item, dwc_otg_qh_t, qh_list_entry);
++00162                 DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp,
++00163                                          &qh->qtd_list, qtd_list_entry) {
++00164                         qtd = DWC_CIRCLEQ_FIRST(&qh->qtd_list);
++00165                         if (qtd->urb != NULL) {
++00166                                 hcd->fops->complete(hcd, qtd->urb->priv,
++00167                                                     qtd->urb,
++00168                                                     -DWC_E_TIMEOUT);
++00169                                 dwc_otg_hcd_qtd_remove_and_free(hcd, qtd, qh);
++00170                         }
++00171 
++00172                 }
++00173         }
++00174 }
++00175 
++00182 static void kill_all_urbs(dwc_otg_hcd_t * hcd)
++00183 {
++00184         kill_urbs_in_qh_list(hcd, &hcd->non_periodic_sched_inactive);
++00185         kill_urbs_in_qh_list(hcd, &hcd->non_periodic_sched_active);
++00186         kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_inactive);
++00187         kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_ready);
++00188         kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_assigned);
++00189         kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_queued);
++00190 }
++00191 
++00198 static void dwc_otg_hcd_start_connect_timer(dwc_otg_hcd_t * hcd)
++00199 {
++00200         DWC_TIMER_SCHEDULE(hcd->conn_timer, 10000 /* 10 secs */ );
++00201 }
++00202 
++00208 static int32_t dwc_otg_hcd_session_start_cb(void *p)
++00209 {
++00210         dwc_otg_hcd_t *dwc_otg_hcd;
++00211         DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, p);
++00212         dwc_otg_hcd = p;
++00213         dwc_otg_hcd_start_connect_timer(dwc_otg_hcd);
++00214         return 1;
++00215 }
++00216 
++00223 static int32_t dwc_otg_hcd_start_cb(void *p)
++00224 {
++00225         dwc_otg_hcd_t *dwc_otg_hcd = p;
++00226         dwc_otg_core_if_t *core_if;
++00227         hprt0_data_t hprt0;
++00228 
++00229         core_if = dwc_otg_hcd->core_if;
++00230 
++00231         if (core_if->op_state == B_HOST) {
++00232                 /*
++00233                  * Reset the port.  During a HNP mode switch the reset
++00234                  * needs to occur within 1ms and have a duration of at
++00235                  * least 50ms.
++00236                  */
++00237                 hprt0.d32 = dwc_otg_read_hprt0(core_if);
++00238                 hprt0.b.prtrst = 1;
++00239                 dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
++00240         }
++00241         DWC_WORKQ_SCHEDULE_DELAYED(core_if->wq_otg,
++00242                                    hcd_start_func, dwc_otg_hcd, 50,
++00243                                    "start hcd");
++00244 
++00245         return 1;
++00246 }
++00247 
++00253 static int32_t dwc_otg_hcd_disconnect_cb(void *p)
++00254 {
++00255         gintsts_data_t intr;
++00256         dwc_otg_hcd_t *dwc_otg_hcd = p;
++00257 
++00258         /*
++00259          * Set status flags for the hub driver.
++00260          */
++00261         dwc_otg_hcd->flags.b.port_connect_status_change = 1;
++00262         dwc_otg_hcd->flags.b.port_connect_status = 0;
++00263 
++00264         /*
++00265          * Shutdown any transfers in process by clearing the Tx FIFO Empty
++00266          * interrupt mask and status bits and disabling subsequent host
++00267          * channel interrupts.
++00268          */
++00269         intr.d32 = 0;
++00270         intr.b.nptxfempty = 1;
++00271         intr.b.ptxfempty = 1;
++00272         intr.b.hcintr = 1;
++00273         dwc_modify_reg32(&dwc_otg_hcd->core_if->core_global_regs->gintmsk,
++00274                          intr.d32, 0);
++00275         dwc_modify_reg32(&dwc_otg_hcd->core_if->core_global_regs->gintsts,
++00276                          intr.d32, 0);
++00277 
++00278         del_timers(dwc_otg_hcd);
++00279 
++00280         /*
++00281          * Turn off the vbus power only if the core has transitioned to device
++00282          * mode. If still in host mode, need to keep power on to detect a
++00283          * reconnection.
++00284          */
++00285         if (dwc_otg_is_device_mode(dwc_otg_hcd->core_if)) {
++00286                 if (dwc_otg_hcd->core_if->op_state != A_SUSPEND) {
++00287                         hprt0_data_t hprt0 = {.d32 = 0 };
++00288                         DWC_PRINTF("Disconnect: PortPower off\n");
++00289                         hprt0.b.prtpwr = 0;
++00290                         dwc_write_reg32(dwc_otg_hcd->core_if->host_if->hprt0,
++00291                                         hprt0.d32);
++00292                 }
++00293 
++00294                 dwc_otg_disable_host_interrupts(dwc_otg_hcd->core_if);
++00295         }
++00296 
++00297         /* Respond with an error status to all URBs in the schedule. */
++00298         kill_all_urbs(dwc_otg_hcd);
++00299 
++00300         if (dwc_otg_is_host_mode(dwc_otg_hcd->core_if)) {
++00301                 /* Clean up any host channels that were in use. */
++00302                 int num_channels;
++00303                 int i;
++00304                 dwc_hc_t *channel;
++00305                 dwc_otg_hc_regs_t *hc_regs;
++00306                 hcchar_data_t hcchar;
++00307 
++00308                 num_channels = dwc_otg_hcd->core_if->core_params->host_channels;
++00309 
++00310                 if (!dwc_otg_hcd->core_if->dma_enable) {
++00311                         /* Flush out any channel requests in slave mode. */
++00312                         for (i = 0; i < num_channels; i++) {
++00313                                 channel = dwc_otg_hcd->hc_ptr_array[i];
++00314                                 if (DWC_CIRCLEQ_EMPTY_ENTRY
++00315                                     (channel, hc_list_entry)) {
++00316                                         hc_regs =
++00317                                             dwc_otg_hcd->core_if->host_if->
++00318                                             hc_regs[i];
++00319                                         hcchar.d32 =
++00320                                             dwc_read_reg32(&hc_regs->hcchar);
++00321                                         if (hcchar.b.chen) {
++00322                                                 hcchar.b.chen = 0;
++00323                                                 hcchar.b.chdis = 1;
++00324                                                 hcchar.b.epdir = 0;
++00325                                                 dwc_write_reg32(&hc_regs->
++00326                                                                 hcchar,
++00327                                                                 hcchar.d32);
++00328                                         }
++00329                                 }
++00330                         }
++00331                 }
++00332 
++00333                 for (i = 0; i < num_channels; i++) {
++00334                         channel = dwc_otg_hcd->hc_ptr_array[i];
++00335                         if (DWC_CIRCLEQ_EMPTY_ENTRY(channel, hc_list_entry)) {
++00336                                 hc_regs =
++00337                                     dwc_otg_hcd->core_if->host_if->hc_regs[i];
++00338                                 hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
++00339                                 if (hcchar.b.chen) {
++00340                                         /* Halt the channel. */
++00341                                         hcchar.b.chdis = 1;
++00342                                         dwc_write_reg32(&hc_regs->hcchar,
++00343                                                         hcchar.d32);
++00344                                 }
++00345 
++00346                                 dwc_otg_hc_cleanup(dwc_otg_hcd->core_if,
++00347                                                    channel);
++00348                                 DWC_CIRCLEQ_INSERT_TAIL(&dwc_otg_hcd->
++00349                                                         free_hc_list, channel,
++00350                                                         hc_list_entry);
++00351                                 /* 
++00352                                  * Added for Descriptor DMA to prevent channel double cleanup 
++00353                                  * in release_channel_ddma(). Which called from ep_disable
++00354                                  * when device disconnect.
++00355                                  */                     
++00356                                 channel->qh = NULL;                     
++00357                         }
++00358                 }
++00359         }
++00360 
++00361         if (dwc_otg_hcd->fops->disconnect) {
++00362                 dwc_otg_hcd->fops->disconnect(dwc_otg_hcd);
++00363         }
++00364 
++00365         return 1;
++00366 }
++00367 
++00373 static int32_t dwc_otg_hcd_stop_cb(void *p)
++00374 {
++00375         dwc_otg_hcd_t *dwc_otg_hcd = p;
++00376 
++00377         DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, p);
++00378         dwc_otg_hcd_stop(dwc_otg_hcd);
++00379         return 1;
++00380 }
++00381 
++00382 #ifdef CONFIG_USB_DWC_OTG_LPM
++00383 
++00388 static int dwc_otg_hcd_sleep_cb(void *p)
++00389 {
++00390         dwc_otg_hcd_t *hcd = p;
++00391 
++00392         dwc_otg_hcd_free_hc_from_lpm(hcd);
++00393 
++00394         return 0;
++00395 }
++00396 #endif
++00397 
++00403 static int dwc_otg_hcd_rem_wakeup_cb(void *p)
++00404 {
++00405         dwc_otg_hcd_t *hcd = p;
++00406 
++00407         if (hcd->core_if->lx_state == DWC_OTG_L2) {
++00408                 hcd->flags.b.port_suspend_change = 1;
++00409         }
++00410 #ifdef CONFIG_USB_DWC_OTG_LPM
++00411         else {
++00412                 hcd->flags.b.port_l1_change = 1;
++00413         }
++00414 #endif
++00415         return 0;
++00416 }
++00417 
++00422 void dwc_otg_hcd_stop(dwc_otg_hcd_t * hcd)
++00423 {
++00424         hprt0_data_t hprt0 = {.d32 = 0 };
++00425 
++00426         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD STOP\n");
++00427 
++00428         /*
++00429          * The root hub should be disconnected before this function is called.
++00430          * The disconnect will clear the QTD lists (via ..._hcd_urb_dequeue)
++00431          * and the QH lists (via ..._hcd_endpoint_disable).
++00432          */
++00433 
++00434         /* Turn off all host-specific interrupts. */
++00435         dwc_otg_disable_host_interrupts(hcd->core_if);
++00436 
++00437         /* Turn off the vbus power */
++00438         DWC_PRINTF("PortPower off\n");
++00439         hprt0.b.prtpwr = 0;
++00440         dwc_write_reg32(hcd->core_if->host_if->hprt0, hprt0.d32);
++00441         dwc_mdelay(1);
++00442 }
++00443 
++00444 int dwc_otg_hcd_urb_enqueue(dwc_otg_hcd_t * hcd,
++00445                             dwc_otg_hcd_urb_t * dwc_otg_urb, void **ep_handle)
++00446 {
++00447         uint64_t flags;
++00448         int retval = 0;
++00449         dwc_otg_qtd_t *qtd;
++00450 
++00451         if (!hcd->flags.b.port_connect_status) {
++00452                 /* No longer connected. */
++00453                 return -DWC_E_NO_DEVICE;
++00454         }
++00455 
++00456         qtd = dwc_otg_hcd_qtd_create(dwc_otg_urb);
++00457         if (qtd == NULL) {
++00458                 DWC_ERROR("DWC OTG HCD URB Enqueue failed creating QTD\n");
++00459                 return -DWC_E_NO_MEMORY;
++00460         }
++00461 
++00462         retval =
++00463             dwc_otg_hcd_qtd_add(qtd, hcd, (dwc_otg_qh_t **) ep_handle);
++00464         if (retval < 0) {
++00465                 DWC_ERROR("DWC OTG HCD URB Enqueue failed adding QTD. "
++00466                           "Error status %d\n", retval);
++00467                 dwc_otg_hcd_qtd_free(qtd);
++00468         } else {
++00469                 qtd->qh = *ep_handle;
++00470         }
++00471         
++00472         if (hcd->core_if->dma_desc_enable && retval == 0) {
++00473                 dwc_otg_transaction_type_e tr_type;     
++00474                 if ((qtd->qh->ep_type == UE_BULK) && !(qtd->urb->flags & URB_GIVEBACK_ASAP)) {
++00475                         /* Do not schedule SG transcations until qtd has URB_GIVEBACK_ASAP set */
++00476                         return 0;
++00477                 }
++00478                 DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
++00479                 tr_type = dwc_otg_hcd_select_transactions(hcd);
++00480                 if (tr_type != DWC_OTG_TRANSACTION_NONE) {
++00481                         dwc_otg_hcd_queue_transactions(hcd, tr_type);
++00482                 }
++00483                 DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
++00484         }
++00485 
++00486         return retval;
++00487 }
++00488 
++00489 int dwc_otg_hcd_urb_dequeue(dwc_otg_hcd_t * hcd,
++00490                             dwc_otg_hcd_urb_t * dwc_otg_urb)
++00491 {
++00492         uint64_t flags;
++00493 
++00494         dwc_otg_qh_t *qh;
++00495         dwc_otg_qtd_t *urb_qtd;
++00496 
++00497         DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
++00498         
++00499         urb_qtd = dwc_otg_urb->qtd;
++00500         qh = urb_qtd->qh;
++00501 #ifdef DEBUG
++00502         if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
++00503                 if (urb_qtd->in_process) {
++00504                         dump_channel_info(hcd, qh);
++00505                 }
++00506         }
++00507 #endif
++00508         if (urb_qtd->in_process && qh->channel) {
++00509                 /* The QTD is in process (it has been assigned to a channel). */
++00510                 if (hcd->flags.b.port_connect_status) {
++00511                         /*
++00512                          * If still connected (i.e. in host mode), halt the
++00513                          * channel so it can be used for other transfers. If
++00514                          * no longer connected, the host registers can't be
++00515                          * written to halt the channel since the core is in
++00516                          * device mode.
++00517                          */
++00518                         dwc_otg_hc_halt(hcd->core_if, qh->channel,
++00519                                         DWC_OTG_HC_XFER_URB_DEQUEUE);
++00520                 }
++00521         }
++00522 
++00523         /*
++00524          * Free the QTD and clean up the associated QH. Leave the QH in the
++00525          * schedule if it has any remaining QTDs.
++00526          */
++00527          
++00528         if (!hcd->core_if->dma_desc_enable) {
++00529                 uint8_t b = urb_qtd->in_process;        
++00530                 dwc_otg_hcd_qtd_remove_and_free(hcd, urb_qtd, qh);
++00531                 if (b) {
++00532                         dwc_otg_hcd_qh_deactivate(hcd, qh, 0);
++00533                         qh->channel = NULL;
++00534                 } else if (DWC_CIRCLEQ_EMPTY(&qh->qtd_list)) {
++00535                         dwc_otg_hcd_qh_remove(hcd, qh);
++00536                 }
++00537         }
++00538         else {
++00539                 dwc_otg_hcd_qtd_remove_and_free(hcd, urb_qtd, qh);
++00540         }
++00541         
++00542         DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
++00543 
++00544         return 0;
++00545 }
++00546 
++00547 int dwc_otg_hcd_endpoint_disable(dwc_otg_hcd_t * hcd, void *ep_handle,
++00548                                  int retry)
++00549 {
++00550         dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle;
++00551         int retval = 0;
++00552         uint64_t flags;
++00553 
++00554         if (retry < 0) {
++00555                 retval = -DWC_E_INVALID;
++00556                 goto done;
++00557         }
++00558 
++00559         if (!qh) {
++00560                 goto done;
++00561         }
++00562 
++00563         DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
++00564         
++00565         while (!DWC_CIRCLEQ_EMPTY(&qh->qtd_list) && retry) {
++00566                 DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
++00567                 retry--;
++00568                 dwc_msleep(5);
++00569                 DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
++00570         }
++00571 
++00572         dwc_otg_hcd_qh_remove(hcd, qh);
++00573         
++00574         DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
++00575         /* 
++00576          * Split dwc_otg_hcd_qh_remove_and_free() into qh_remove 
++00577          * and qh_free to prevent stack dump on dwc_dma_free() with 
++00578          * irq_disabled (spinlock_irqsave) in dwc_otg_hcd_desc_list_free() 
++00579          * and dwc_otg_hcd_frame_list_alloc().
++00580          */
++00581         dwc_otg_hcd_qh_free(hcd, qh);
++00582 
++00583       done:
++00584         return retval;
++00585 }
++00586 
++00590 static dwc_otg_cil_callbacks_t hcd_cil_callbacks = {
++00591         .start = dwc_otg_hcd_start_cb,
++00592         .stop = dwc_otg_hcd_stop_cb,
++00593         .disconnect = dwc_otg_hcd_disconnect_cb,
++00594         .session_start = dwc_otg_hcd_session_start_cb,
++00595         .resume_wakeup = dwc_otg_hcd_rem_wakeup_cb,
++00596 #ifdef CONFIG_USB_DWC_OTG_LPM
++00597         .sleep = dwc_otg_hcd_sleep_cb,
++00598 #endif
++00599         .p = 0,
++00600 };
++00601 
++00605 static void reset_tasklet_func(void *data)
++00606 {
++00607         dwc_otg_hcd_t *dwc_otg_hcd = (dwc_otg_hcd_t *) data;
++00608         dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;
++00609         hprt0_data_t hprt0;
++00610 
++00611         DWC_DEBUGPL(DBG_HCDV, "USB RESET tasklet called\n");
++00612 
++00613         hprt0.d32 = dwc_otg_read_hprt0(core_if);
++00614         hprt0.b.prtrst = 1;
++00615         dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
++00616         dwc_mdelay(60);
++00617 
++00618         hprt0.b.prtrst = 0;
++00619         dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
++00620         dwc_otg_hcd->flags.b.port_reset_change = 1;
++00621 }
++00622 
++00623 static void qh_list_free(dwc_otg_hcd_t * hcd, dwc_list_link_t * qh_list)
++00624 {
++00625         dwc_list_link_t *item;
++00626         dwc_otg_qh_t *qh;
++00627 
++00628         if (!qh_list->next) {
++00629                 /* The list hasn't been initialized yet. */
++00630                 return;
++00631         }
++00632 
++00633         /* Ensure there are no QTDs or URBs left. */
++00634         kill_urbs_in_qh_list(hcd, qh_list);
++00635 
++00636         DWC_LIST_FOREACH(item, qh_list) {
++00637                 qh = DWC_LIST_ENTRY(item, dwc_otg_qh_t, qh_list_entry);
++00638                 dwc_otg_hcd_qh_remove_and_free(hcd, qh);
++00639         }
++00640 }
++00641 
++00646 static void dwc_otg_hcd_free(dwc_otg_hcd_t * dwc_otg_hcd)
++00647 {
++00648         int i;
++00649 
++00650         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD FREE\n");
++00651 
++00652         del_timers(dwc_otg_hcd);
++00653 
++00654         /* Free memory for QH/QTD lists */
++00655         qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->non_periodic_sched_inactive);
++00656         qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->non_periodic_sched_active);
++00657         qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_inactive);
++00658         qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_ready);
++00659         qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_assigned);
++00660         qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_queued);
++00661 
++00662         /* Free memory for the host channels. */
++00663         for (i = 0; i < MAX_EPS_CHANNELS; i++) {
++00664                 dwc_hc_t *hc = dwc_otg_hcd->hc_ptr_array[i];
++00665 
++00666 #ifdef DEBUG
++00667                 if (dwc_otg_hcd->core_if->hc_xfer_timer[i]) {
++00668                         DWC_TIMER_FREE(dwc_otg_hcd->core_if->hc_xfer_timer[i]);
++00669                 }
++00670 #endif
++00671                 if (hc != NULL) {
++00672                         DWC_DEBUGPL(DBG_HCDV, "HCD Free channel #%i, hc=%p\n",
++00673                                     i, hc);
++00674                         dwc_free(hc);
++00675                 }
++00676         }
++00677 
++00678         if (dwc_otg_hcd->core_if->dma_enable) {
++00679                 if (dwc_otg_hcd->status_buf_dma) {
++00680                         dwc_dma_free(DWC_OTG_HCD_STATUS_BUF_SIZE,
++00681                                      dwc_otg_hcd->status_buf,
++00682                                      dwc_otg_hcd->status_buf_dma);
++00683                 }
++00684         } else if (dwc_otg_hcd->status_buf != NULL) {
++00685                 dwc_free(dwc_otg_hcd->status_buf);
++00686         }
++00687         DWC_SPINLOCK_FREE(dwc_otg_hcd->lock);
++00688         DWC_TIMER_FREE(dwc_otg_hcd->conn_timer);
++00689         DWC_TASK_FREE(dwc_otg_hcd->reset_tasklet);
++00690         dwc_free(dwc_otg_hcd);
++00691 }
++00692 
++00693 int dwc_otg_hcd_init(dwc_otg_hcd_t * hcd, dwc_otg_core_if_t * core_if)
++00694 {
++00695         int retval = 0;
++00696         int num_channels;
++00697         int i;
++00698         dwc_hc_t *channel;
++00699 
++00700         hcd->lock = DWC_SPINLOCK_ALLOC();
++00701 
++00702         hcd->core_if = core_if;
++00703         /* Register the HCD CIL Callbacks */
++00704         dwc_otg_cil_register_hcd_callbacks(hcd->core_if,
++00705                                            &hcd_cil_callbacks, hcd);
++00706 
++00707         /* Initialize the non-periodic schedule. */
++00708         DWC_LIST_INIT(&hcd->non_periodic_sched_inactive);
++00709         DWC_LIST_INIT(&hcd->non_periodic_sched_active);
++00710 
++00711         /* Initialize the periodic schedule. */
++00712         DWC_LIST_INIT(&hcd->periodic_sched_inactive);
++00713         DWC_LIST_INIT(&hcd->periodic_sched_ready);
++00714         DWC_LIST_INIT(&hcd->periodic_sched_assigned);
++00715         DWC_LIST_INIT(&hcd->periodic_sched_queued);
++00716 
++00717         /*
++00718          * Create a host channel descriptor for each host channel implemented
++00719          * in the controller. Initialize the channel descriptor array.
++00720          */
++00721         DWC_CIRCLEQ_INIT(&hcd->free_hc_list);
++00722         num_channels = hcd->core_if->core_params->host_channels;
++00723         DWC_MEMSET(hcd->hc_ptr_array, 0, sizeof(hcd->hc_ptr_array));
++00724         for (i = 0; i < num_channels; i++) {
++00725                 channel = dwc_alloc(sizeof(dwc_hc_t));
++00726                 if (channel == NULL) {
++00727                         retval = -DWC_E_NO_MEMORY;
++00728                         DWC_ERROR("%s: host channel allocation failed\n",
++00729                                   __func__);
++00730                         dwc_otg_hcd_free(hcd);
++00731                         goto out;
++00732                 }
++00733                 channel->hc_num = i;
++00734                 hcd->hc_ptr_array[i] = channel;
++00735 #ifdef DEBUG
++00736                 hcd->core_if->hc_xfer_timer[i] =
++00737                     DWC_TIMER_ALLOC("hc timer", hc_xfer_timeout,
++00738                                     &hcd->core_if->hc_xfer_info[i]);
++00739 #endif
++00740                 DWC_DEBUGPL(DBG_HCDV, "HCD Added channel #%d, hc=%p\n", i,
++00741                             channel);
++00742         }
++00743 
++00744         /* Initialize the Connection timeout timer. */
++00745         hcd->conn_timer = DWC_TIMER_ALLOC("Connection timer",
++00746                                           dwc_otg_hcd_connect_timeout, 0);
++00747 
++00748         /* Initialize reset tasklet. */
++00749         hcd->reset_tasklet = DWC_TASK_ALLOC(reset_tasklet_func, hcd);
++00750 
++00751         /*
++00752          * Allocate space for storing data on status transactions. Normally no
++00753          * data is sent, but this space acts as a bit bucket. This must be
++00754          * done after usb_add_hcd since that function allocates the DMA buffer
++00755          * pool.
++00756          */
++00757         if (hcd->core_if->dma_enable) {
++00758                 hcd->status_buf =
++00759                     dwc_dma_alloc(DWC_OTG_HCD_STATUS_BUF_SIZE,
++00760                                   &hcd->status_buf_dma);
++00761         } else {
++00762                 hcd->status_buf = dwc_alloc(DWC_OTG_HCD_STATUS_BUF_SIZE);
++00763         }
++00764         if (!hcd->status_buf) {
++00765                 retval = -DWC_E_NO_MEMORY;
++00766                 DWC_ERROR("%s: status_buf allocation failed\n", __func__);
++00767                 dwc_otg_hcd_free(hcd);
++00768                 goto out;
++00769         }
++00770 
++00771         hcd->otg_port = 1;
++00772         hcd->frame_list = NULL;
++00773         hcd->frame_list_dma = 0;
++00774 out:
++00775         return retval;
++00776 }
++00777 
++00778 void dwc_otg_hcd_remove(dwc_otg_hcd_t * hcd)
++00779 {
++00780         /* Turn off all host-specific interrupts. */
++00781         dwc_otg_disable_host_interrupts(hcd->core_if);
++00782 
++00783         dwc_otg_hcd_free(hcd);
++00784 }
++00785 
++00789 static void dwc_otg_hcd_reinit(dwc_otg_hcd_t * hcd)
++00790 {
++00791         int num_channels;
++00792         int i;
++00793         dwc_hc_t *channel;
++00794         dwc_hc_t *channel_tmp;
++00795 
++00796         hcd->flags.d32 = 0;
++00797 
++00798         hcd->non_periodic_qh_ptr = &hcd->non_periodic_sched_active;
++00799         hcd->non_periodic_channels = 0;
++00800         hcd->periodic_channels = 0;
++00801 
++00802         /*
++00803          * Put all channels in the free channel list and clean up channel
++00804          * states.
++00805          */
++00806         DWC_CIRCLEQ_FOREACH_SAFE(channel, channel_tmp,
++00807                                  &hcd->free_hc_list, hc_list_entry) {
++00808                 DWC_CIRCLEQ_REMOVE(&hcd->free_hc_list, channel, hc_list_entry);
++00809         }
++00810 
++00811         num_channels = hcd->core_if->core_params->host_channels;
++00812         for (i = 0; i < num_channels; i++) {
++00813                 channel = hcd->hc_ptr_array[i];
++00814                 DWC_CIRCLEQ_INSERT_TAIL(&hcd->free_hc_list, channel,
++00815                                         hc_list_entry);
++00816                 dwc_otg_hc_cleanup(hcd->core_if, channel);
++00817         }
++00818 
++00819         /* Initialize the DWC core for host mode operation. */
++00820         dwc_otg_core_host_init(hcd->core_if);
++00821 }
++00822 
++00832 static void assign_and_init_hc(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
++00833 {
++00834         dwc_hc_t *hc;
++00835         dwc_otg_qtd_t *qtd;
++00836         dwc_otg_hcd_urb_t *urb;
++00837         void* ptr = NULL;
++00838 
++00839         DWC_DEBUGPL(DBG_HCDV, "%s(%p,%p)\n", __func__, hcd, qh);
++00840 
++00841         hc = DWC_CIRCLEQ_FIRST(&hcd->free_hc_list);
++00842 
++00843         /* Remove the host channel from the free list. */
++00844         DWC_CIRCLEQ_REMOVE_INIT(&hcd->free_hc_list, hc, hc_list_entry);
++00845 
++00846         qtd = DWC_CIRCLEQ_FIRST(&qh->qtd_list);
++00847         
++00848         urb = qtd->urb;
++00849         qh->channel = hc;
++00850         
++00851         qtd->in_process = 1;
++00852 
++00853         /*
++00854          * Use usb_pipedevice to determine device address. This address is
++00855          * 0 before the SET_ADDRESS command and the correct address afterward.
++00856          */
++00857         hc->dev_addr = dwc_otg_hcd_get_dev_addr(&urb->pipe_info);
++00858         hc->ep_num = dwc_otg_hcd_get_ep_num(&urb->pipe_info);
++00859         hc->speed = qh->dev_speed;
++00860         hc->max_packet = dwc_max_packet(qh->maxp);
++00861 
++00862         hc->xfer_started = 0;
++00863         hc->halt_status = DWC_OTG_HC_XFER_NO_HALT_STATUS;
++00864         hc->error_state = (qtd->error_count > 0);
++00865         hc->halt_on_queue = 0;
++00866         hc->halt_pending = 0;
++00867         hc->requests = 0;
++00868 
++00869         /*
++00870          * The following values may be modified in the transfer type section
++00871          * below. The xfer_len value may be reduced when the transfer is
++00872          * started to accommodate the max widths of the XferSize and PktCnt
++00873          * fields in the HCTSIZn register.
++00874          */
++00875         hc->do_ping = qh->ping_state;
++00876         hc->ep_is_in = (dwc_otg_hcd_is_pipe_in(&urb->pipe_info) != 0);
++00877         hc->data_pid_start = qh->data_toggle;
++00878         hc->multi_count = 1;
++00879 
++00880         if (hcd->core_if->dma_enable) {
++00881                 hc->xfer_buff = (uint8_t *) urb->dma + urb->actual_length;
++00882         
++00883                 /* For non-dword aligned case */
++00884                 if (((uint32_t)hc->xfer_buff & 0x3) && !hcd->core_if->dma_desc_enable) {
++00885                         ptr = (uint8_t *) urb->buf + urb->actual_length;
++00886                 }
++00887         } else {
++00888                 hc->xfer_buff = (uint8_t *) urb->buf + urb->actual_length;
++00889         }
++00890         hc->xfer_len = urb->length - urb->actual_length;
++00891         hc->xfer_count = 0;
++00892 
++00893         /*
++00894          * Set the split attributes
++00895          */
++00896         hc->do_split = 0;
++00897         if (qh->do_split) {
++00898                 uint32_t hub_addr, port_addr;
++00899                 hc->do_split = 1;
++00900                 hc->xact_pos = qtd->isoc_split_pos;
++00901                 hc->complete_split = qtd->complete_split;
++00902                 hcd->fops->hub_info(hcd, urb->priv, &hub_addr, &port_addr);
++00903                 hc->hub_addr = (uint8_t) hub_addr;
++00904                 hc->port_addr = (uint8_t) port_addr;
++00905         }
++00906 
++00907         switch (dwc_otg_hcd_get_pipe_type(&urb->pipe_info)) {
++00908         case UE_CONTROL:
++00909                 hc->ep_type = DWC_OTG_EP_TYPE_CONTROL;
++00910                 switch (qtd->control_phase) {
++00911                 case DWC_OTG_CONTROL_SETUP:
++00912                         DWC_DEBUGPL(DBG_HCDV, "  Control setup transaction\n");
++00913                         hc->do_ping = 0;
++00914                         hc->ep_is_in = 0;
++00915                         hc->data_pid_start = DWC_OTG_HC_PID_SETUP;
++00916                         if (hcd->core_if->dma_enable) {
++00917                                 hc->xfer_buff = (uint8_t *) urb->setup_dma;
++00918                         } else {
++00919                                 hc->xfer_buff = (uint8_t *) urb->setup_packet;
++00920                         }
++00921                         hc->xfer_len = 8;
++00922                         ptr = NULL;
++00923                         break;
++00924                 case DWC_OTG_CONTROL_DATA:
++00925                         DWC_DEBUGPL(DBG_HCDV, "  Control data transaction\n");
++00926                         hc->data_pid_start = qtd->data_toggle;
++00927                         break;
++00928                 case DWC_OTG_CONTROL_STATUS:
++00929                         /*
++00930                          * Direction is opposite of data direction or IN if no
++00931                          * data.
++00932                          */
++00933                         DWC_DEBUGPL(DBG_HCDV, "  Control status transaction\n");
++00934                         if (urb->length == 0) {
++00935                                 hc->ep_is_in = 1;
++00936                         } else {
++00937                                 hc->ep_is_in =
++00938                                     dwc_otg_hcd_is_pipe_out(&urb->pipe_info);
++00939                         }
++00940                         if (hc->ep_is_in) {
++00941                                 hc->do_ping = 0;
++00942                         }
++00943                         
++00944                         hc->data_pid_start = DWC_OTG_HC_PID_DATA1;
++00945 
++00946                         hc->xfer_len = 0;
++00947                         if (hcd->core_if->dma_enable) {
++00948                                 hc->xfer_buff = (uint8_t *) hcd->status_buf_dma;
++00949                         } else {
++00950                                 hc->xfer_buff = (uint8_t *) hcd->status_buf;
++00951                         }
++00952                         ptr = NULL;
++00953                         break;
++00954                 }
++00955                 break;
++00956         case UE_BULK:
++00957                 hc->ep_type = DWC_OTG_EP_TYPE_BULK;
++00958                 break;
++00959         case UE_INTERRUPT:
++00960                 hc->ep_type = DWC_OTG_EP_TYPE_INTR;
++00961                 break;
++00962         case UE_ISOCHRONOUS:
++00963                 {
++00964                         struct dwc_otg_hcd_iso_packet_desc *frame_desc;
++00965                         
++00966                         hc->ep_type = DWC_OTG_EP_TYPE_ISOC;
++00967                         
++00968                         if (hcd->core_if->dma_desc_enable)
++00969                                 break;
++00970                                 
++00971                         frame_desc = &urb->iso_descs[qtd->isoc_frame_index];
++00972                         
++00973                         frame_desc->status = 0;
++00974                         
++00975                         if (hcd->core_if->dma_enable) {
++00976                                 hc->xfer_buff = (uint8_t *) urb->dma;
++00977                         } else {
++00978                                 hc->xfer_buff = (uint8_t *) urb->buf;
++00979                         }
++00980                         hc->xfer_buff +=
++00981                             frame_desc->offset + qtd->isoc_split_offset;
++00982                         hc->xfer_len =
++00983                             frame_desc->length - qtd->isoc_split_offset;
++00984 
++00985                         /* For non-dword aligned buffers */
++00986                         if (((uint32_t)hc->xfer_buff & 0x3) && hcd->core_if->dma_enable) {
++00987                                 ptr = (uint8_t *) urb->buf + frame_desc->offset + qtd->isoc_split_offset;
++00988                         }       
++00989                         else
++00990                             ptr = NULL;
++00991                         
++00992                         if (hc->xact_pos == DWC_HCSPLIT_XACTPOS_ALL) {
++00993                                 if (hc->xfer_len <= 188) {
++00994                                         hc->xact_pos = DWC_HCSPLIT_XACTPOS_ALL;
++00995                                 } else {
++00996                                         hc->xact_pos =
++00997                                             DWC_HCSPLIT_XACTPOS_BEGIN;
++00998                                 }
++00999                         }
++01000                 }
++01001                 break;
++01002         }
++01003         /* non DWORD-aligned buffer case */     
++01004         if (ptr) {
++01005                 uint32_t buf_size;
++01006                 if (hc->ep_type != DWC_OTG_EP_TYPE_ISOC) {
++01007                         buf_size = hcd->core_if->core_params->max_transfer_size;
++01008                 } else {                                
++01009                         buf_size = 4096;
++01010                 }
++01011                 if (!qh->dw_align_buf) {
++01012                         qh->dw_align_buf = dwc_dma_alloc(buf_size,
++01013                                                          &qh->dw_align_buf_dma);
++01014                         if (!qh->dw_align_buf) {
++01015                                 DWC_ERROR("%s: Failed to allocate memory to handle "
++01016                                           "non-dword aligned buffer case\n", __func__);
++01017                                 return;
++01018                         }
++01019                 }
++01020                 if (!hc->ep_is_in) {
++01021                         dwc_memcpy(qh->dw_align_buf, ptr, hc->xfer_len);
++01022                 }
++01023                 hc->align_buff = qh->dw_align_buf_dma;
++01024         }
++01025         else {
++01026                 hc->align_buff = 0;
++01027         }
++01028 
++01029         if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
++01030             hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
++01031                 /*
++01032                  * This value may be modified when the transfer is started to
++01033                  * reflect the actual transfer length.
++01034                  */
++01035                 hc->multi_count = dwc_hb_mult(qh->maxp);
++01036         }
++01037         
++01038         if (hcd->core_if->dma_desc_enable)
++01039                 hc->desc_list_addr = qh->desc_list_dma;
++01040         
++01041         dwc_otg_hc_init(hcd->core_if, hc);
++01042         hc->qh = qh;
++01043 }
++01044 
++01045 
++01055 dwc_otg_transaction_type_e dwc_otg_hcd_select_transactions(dwc_otg_hcd_t * hcd)
++01056 {
++01057         dwc_list_link_t *qh_ptr;
++01058         dwc_otg_qh_t *qh;
++01059         int num_channels;
++01060         dwc_otg_transaction_type_e ret_val = DWC_OTG_TRANSACTION_NONE;
++01061 
++01062 #ifdef DEBUG_SOF
++01063         DWC_DEBUGPL(DBG_HCD, "  Select Transactions\n");
++01064 #endif
++01065 
++01066         /* Process entries in the periodic ready list. */
++01067         qh_ptr = DWC_LIST_FIRST(&hcd->periodic_sched_ready);
++01068 
++01069         while (qh_ptr != &hcd->periodic_sched_ready &&
++01070                !DWC_CIRCLEQ_EMPTY(&hcd->free_hc_list)) {
++01071 
++01072                 qh = DWC_LIST_ENTRY(qh_ptr, dwc_otg_qh_t, qh_list_entry);
++01073                 assign_and_init_hc(hcd, qh);
++01074 
++01075                 /*
++01076                  * Move the QH from the periodic ready schedule to the
++01077                  * periodic assigned schedule.
++01078                  */
++01079                 qh_ptr = DWC_LIST_NEXT(qh_ptr);
++01080                 DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_assigned,
++01081                                    &qh->qh_list_entry);
++01082 
++01083                 ret_val = DWC_OTG_TRANSACTION_PERIODIC;
++01084         }
++01085 
++01086         /*
++01087          * Process entries in the inactive portion of the non-periodic
++01088          * schedule. Some free host channels may not be used if they are
++01089          * reserved for periodic transfers.
++01090          */
++01091         qh_ptr = hcd->non_periodic_sched_inactive.next;
++01092         num_channels = hcd->core_if->core_params->host_channels;
++01093         while (qh_ptr != &hcd->non_periodic_sched_inactive &&
++01094                (hcd->non_periodic_channels <
++01095                 num_channels - hcd->periodic_channels) &&
++01096                !DWC_CIRCLEQ_EMPTY(&hcd->free_hc_list)) {
++01097 
++01098                 qh = DWC_LIST_ENTRY(qh_ptr, dwc_otg_qh_t, qh_list_entry);
++01099 
++01100                 assign_and_init_hc(hcd, qh);
++01101 
++01102                 /*
++01103                  * Move the QH from the non-periodic inactive schedule to the
++01104                  * non-periodic active schedule.
++01105                  */
++01106                 qh_ptr = DWC_LIST_NEXT(qh_ptr);
++01107                 DWC_LIST_MOVE_HEAD(&hcd->non_periodic_sched_active,
++01108                                    &qh->qh_list_entry);
++01109 
++01110                 if (ret_val == DWC_OTG_TRANSACTION_NONE) {
++01111                         ret_val = DWC_OTG_TRANSACTION_NON_PERIODIC;
++01112                 } else {
++01113                         ret_val = DWC_OTG_TRANSACTION_ALL;
++01114                 }
++01115 
++01116                 hcd->non_periodic_channels++;
++01117         }
++01118 
++01119         return ret_val;
++01120 }
++01139 static int queue_transaction(dwc_otg_hcd_t * hcd,
++01140                              dwc_hc_t * hc, uint16_t fifo_dwords_avail)
++01141 {
++01142         int retval;
++01143 
++01144         if (hcd->core_if->dma_enable) {
++01145                 if (hcd->core_if->dma_desc_enable) {
++01146                         if (!hc->xfer_started || (hc->ep_type == DWC_OTG_EP_TYPE_ISOC)) {       
++01147                                 dwc_otg_hcd_start_xfer_ddma(hcd, hc->qh);
++01148                                 hc->qh->ping_state = 0;
++01149                         }
++01150                 }
++01151                 else if (!hc->xfer_started) {
++01152                         dwc_otg_hc_start_transfer(hcd->core_if, hc);
++01153                         hc->qh->ping_state = 0;
++01154                 }
++01155                 retval = 0;
++01156         } else if (hc->halt_pending) {
++01157                 /* Don't queue a request if the channel has been halted. */
++01158                 retval = 0;
++01159         } else if (hc->halt_on_queue) {
++01160                 dwc_otg_hc_halt(hcd->core_if, hc, hc->halt_status);
++01161                 retval = 0;
++01162         } else if (hc->do_ping) {
++01163                 if (!hc->xfer_started) {
++01164                         dwc_otg_hc_start_transfer(hcd->core_if, hc);
++01165                 }
++01166                 retval = 0;
++01167         } else if (!hc->ep_is_in || hc->data_pid_start == DWC_OTG_HC_PID_SETUP) {
++01168                 if ((fifo_dwords_avail * 4) >= hc->max_packet) {
++01169                         if (!hc->xfer_started) {
++01170                                 dwc_otg_hc_start_transfer(hcd->core_if, hc);
++01171                                 retval = 1;
++01172                         } else {
++01173                                 retval =
++01174                                     dwc_otg_hc_continue_transfer(hcd->core_if,
++01175                                                                  hc);
++01176                         }
++01177                 } else {
++01178                         retval = -1;
++01179                 }
++01180         } else {
++01181                 if (!hc->xfer_started) {
++01182                         dwc_otg_hc_start_transfer(hcd->core_if, hc);
++01183                         retval = 1;
++01184                 } else {
++01185                         retval = dwc_otg_hc_continue_transfer(hcd->core_if, hc);
++01186                 }
++01187         }
++01188 
++01189         return retval;
++01190 }
++01191 
++01199 static void process_periodic_channels(dwc_otg_hcd_t * hcd)
++01200 {
++01201         hptxsts_data_t tx_status;
++01202         dwc_list_link_t *qh_ptr;
++01203         dwc_otg_qh_t *qh;
++01204         int status;
++01205         int no_queue_space = 0;
++01206         int no_fifo_space = 0;
++01207 
++01208         dwc_otg_host_global_regs_t *host_regs;
++01209         host_regs = hcd->core_if->host_if->host_global_regs;
++01210 
++01211         DWC_DEBUGPL(DBG_HCDV, "Queue periodic transactions\n");
++01212 #ifdef DEBUG
++01213         tx_status.d32 = dwc_read_reg32(&host_regs->hptxsts);
++01214         DWC_DEBUGPL(DBG_HCDV,
++01215                     "  P Tx Req Queue Space Avail (before queue): %d\n",
++01216                     tx_status.b.ptxqspcavail);
++01217         DWC_DEBUGPL(DBG_HCDV, "  P Tx FIFO Space Avail (before queue): %d\n",
++01218                     tx_status.b.ptxfspcavail);
++01219 #endif
++01220 
++01221         qh_ptr = hcd->periodic_sched_assigned.next;
++01222         while (qh_ptr != &hcd->periodic_sched_assigned) {
++01223                 tx_status.d32 = dwc_read_reg32(&host_regs->hptxsts);
++01224                 if (tx_status.b.ptxqspcavail == 0) {
++01225                         no_queue_space = 1;
++01226                         break;
++01227                 }
++01228 
++01229                 qh = DWC_LIST_ENTRY(qh_ptr, dwc_otg_qh_t, qh_list_entry);
++01230 
++01231                 /*
++01232                  * Set a flag if we're queuing high-bandwidth in slave mode.
++01233                  * The flag prevents any halts to get into the request queue in
++01234                  * the middle of multiple high-bandwidth packets getting queued.
++01235                  */
++01236                 if (!hcd->core_if->dma_enable && qh->channel->multi_count > 1) {
++01237                         hcd->core_if->queuing_high_bandwidth = 1;
++01238                 }
++01239                 status =
++01240                     queue_transaction(hcd, qh->channel,
++01241                                       tx_status.b.ptxfspcavail);
++01242                 if (status < 0) {
++01243                         no_fifo_space = 1;
++01244                         break;
++01245                 }
++01246 
++01247                 /*
++01248                  * In Slave mode, stay on the current transfer until there is
++01249                  * nothing more to do or the high-bandwidth request count is
++01250                  * reached. In DMA mode, only need to queue one request. The
++01251                  * controller automatically handles multiple packets for
++01252                  * high-bandwidth transfers.
++01253                  */
++01254                 if (hcd->core_if->dma_enable || status == 0 ||
++01255                     qh->channel->requests == qh->channel->multi_count) {
++01256                         qh_ptr = qh_ptr->next;
++01257                         /*
++01258                          * Move the QH from the periodic assigned schedule to
++01259                          * the periodic queued schedule.
++01260                          */
++01261                         DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_queued,
++01262                                            &qh->qh_list_entry);
++01263 
++01264                         /* done queuing high bandwidth */
++01265                         hcd->core_if->queuing_high_bandwidth = 0;
++01266                 }
++01267         }
++01268 
++01269         if (!hcd->core_if->dma_enable) {
++01270                 dwc_otg_core_global_regs_t *global_regs;
++01271                 gintmsk_data_t intr_mask = {.d32 = 0 };
++01272 
++01273                 global_regs = hcd->core_if->core_global_regs;
++01274                 intr_mask.b.ptxfempty = 1;
++01275 #ifdef DEBUG
++01276                 tx_status.d32 = dwc_read_reg32(&host_regs->hptxsts);
++01277                 DWC_DEBUGPL(DBG_HCDV,
++01278                             "  P Tx Req Queue Space Avail (after queue): %d\n",
++01279                             tx_status.b.ptxqspcavail);
++01280                 DWC_DEBUGPL(DBG_HCDV,
++01281                             "  P Tx FIFO Space Avail (after queue): %d\n",
++01282                             tx_status.b.ptxfspcavail);
++01283 #endif
++01284                 if (!DWC_LIST_EMPTY(&hcd->periodic_sched_assigned) ||
++01285                     no_queue_space || no_fifo_space) {
++01286                         /*
++01287                          * May need to queue more transactions as the request
++01288                          * queue or Tx FIFO empties. Enable the periodic Tx
++01289                          * FIFO empty interrupt. (Always use the half-empty
++01290                          * level to ensure that new requests are loaded as
++01291                          * soon as possible.)
++01292                          */
++01293                         dwc_modify_reg32(&global_regs->gintmsk, 0,
++01294                                          intr_mask.d32);
++01295                 } else {
++01296                         /*
++01297                          * Disable the Tx FIFO empty interrupt since there are
++01298                          * no more transactions that need to be queued right
++01299                          * now. This function is called from interrupt
++01300                          * handlers to queue more transactions as transfer
++01301                          * states change.
++01302                          */
++01303                         dwc_modify_reg32(&global_regs->gintmsk, intr_mask.d32,
++01304                                          0);
++01305                 }
++01306         }
++01307 }
++01308 
++01316 static void process_non_periodic_channels(dwc_otg_hcd_t * hcd)
++01317 {
++01318         gnptxsts_data_t tx_status;
++01319         dwc_list_link_t *orig_qh_ptr;
++01320         dwc_otg_qh_t *qh;
++01321         int status;
++01322         int no_queue_space = 0;
++01323         int no_fifo_space = 0;
++01324         int more_to_do = 0;
++01325 
++01326         dwc_otg_core_global_regs_t *global_regs =
++01327             hcd->core_if->core_global_regs;
++01328 
++01329         DWC_DEBUGPL(DBG_HCDV, "Queue non-periodic transactions\n");
++01330 #ifdef DEBUG
++01331         tx_status.d32 = dwc_read_reg32(&global_regs->gnptxsts);
++01332         DWC_DEBUGPL(DBG_HCDV,
++01333                     "  NP Tx Req Queue Space Avail (before queue): %d\n",
++01334                     tx_status.b.nptxqspcavail);
++01335         DWC_DEBUGPL(DBG_HCDV, "  NP Tx FIFO Space Avail (before queue): %d\n",
++01336                     tx_status.b.nptxfspcavail);
++01337 #endif
++01338         /*
++01339          * Keep track of the starting point. Skip over the start-of-list
++01340          * entry.
++01341          */
++01342         if (hcd->non_periodic_qh_ptr == &hcd->non_periodic_sched_active) {
++01343                 hcd->non_periodic_qh_ptr = hcd->non_periodic_qh_ptr->next;
++01344         }
++01345         orig_qh_ptr = hcd->non_periodic_qh_ptr;
++01346 
++01347         /*
++01348          * Process once through the active list or until no more space is
++01349          * available in the request queue or the Tx FIFO.
++01350          */
++01351         do {
++01352                 tx_status.d32 = dwc_read_reg32(&global_regs->gnptxsts);
++01353                 if (!hcd->core_if->dma_enable && tx_status.b.nptxqspcavail == 0) {
++01354                         no_queue_space = 1;
++01355                         break;
++01356                 }
++01357 
++01358                 qh = DWC_LIST_ENTRY(hcd->non_periodic_qh_ptr, dwc_otg_qh_t,
++01359                                     qh_list_entry);
++01360                 status =
++01361                     queue_transaction(hcd, qh->channel,
++01362                                       tx_status.b.nptxfspcavail);
++01363 
++01364                 if (status > 0) {
++01365                         more_to_do = 1;
++01366                 } else if (status < 0) {
++01367                         no_fifo_space = 1;
++01368                         break;
++01369                 }
++01370 
++01371                 /* Advance to next QH, skipping start-of-list entry. */
++01372                 hcd->non_periodic_qh_ptr = hcd->non_periodic_qh_ptr->next;
++01373                 if (hcd->non_periodic_qh_ptr == &hcd->non_periodic_sched_active) {
++01374                         hcd->non_periodic_qh_ptr =
++01375                             hcd->non_periodic_qh_ptr->next;
++01376                 }
++01377 
++01378         } while (hcd->non_periodic_qh_ptr != orig_qh_ptr);
++01379 
++01380         if (!hcd->core_if->dma_enable) {
++01381                 gintmsk_data_t intr_mask = {.d32 = 0 };
++01382                 intr_mask.b.nptxfempty = 1;
++01383 
++01384 #ifdef DEBUG
++01385                 tx_status.d32 = dwc_read_reg32(&global_regs->gnptxsts);
++01386                 DWC_DEBUGPL(DBG_HCDV,
++01387                             "  NP Tx Req Queue Space Avail (after queue): %d\n",
++01388                             tx_status.b.nptxqspcavail);
++01389                 DWC_DEBUGPL(DBG_HCDV,
++01390                             "  NP Tx FIFO Space Avail (after queue): %d\n",
++01391                             tx_status.b.nptxfspcavail);
++01392 #endif
++01393                 if (more_to_do || no_queue_space || no_fifo_space) {
++01394                         /*
++01395                          * May need to queue more transactions as the request
++01396                          * queue or Tx FIFO empties. Enable the non-periodic
++01397                          * Tx FIFO empty interrupt. (Always use the half-empty
++01398                          * level to ensure that new requests are loaded as
++01399                          * soon as possible.)
++01400                          */
++01401                         dwc_modify_reg32(&global_regs->gintmsk, 0,
++01402                                          intr_mask.d32);
++01403                 } else {
++01404                         /*
++01405                          * Disable the Tx FIFO empty interrupt since there are
++01406                          * no more transactions that need to be queued right
++01407                          * now. This function is called from interrupt
++01408                          * handlers to queue more transactions as transfer
++01409                          * states change.
++01410                          */
++01411                         dwc_modify_reg32(&global_regs->gintmsk, intr_mask.d32,
++01412                                          0);
++01413                 }
++01414         }
++01415 }
++01416 
++01426 void dwc_otg_hcd_queue_transactions(dwc_otg_hcd_t * hcd,
++01427                                            dwc_otg_transaction_type_e tr_type)
++01428 {
++01429 #ifdef DEBUG_SOF
++01430         DWC_DEBUGPL(DBG_HCD, "Queue Transactions\n");
++01431 #endif
++01432         /* Process host channels associated with periodic transfers. */
++01433         if ((tr_type == DWC_OTG_TRANSACTION_PERIODIC ||
++01434              tr_type == DWC_OTG_TRANSACTION_ALL) &&
++01435             !DWC_LIST_EMPTY(&hcd->periodic_sched_assigned)) {
++01436 
++01437                 process_periodic_channels(hcd);
++01438         }
++01439 
++01440         /* Process host channels associated with non-periodic transfers. */
++01441         if (tr_type == DWC_OTG_TRANSACTION_NON_PERIODIC ||
++01442             tr_type == DWC_OTG_TRANSACTION_ALL) {
++01443                 if (!DWC_LIST_EMPTY(&hcd->non_periodic_sched_active)) {
++01444                         process_non_periodic_channels(hcd);
++01445                 } else {
++01446                         /*
++01447                          * Ensure NP Tx FIFO empty interrupt is disabled when
++01448                          * there are no non-periodic transfers to process.
++01449                          */
++01450                         gintmsk_data_t gintmsk = {.d32 = 0 };
++01451                         gintmsk.b.nptxfempty = 1;
++01452                         dwc_modify_reg32(&hcd->core_if->core_global_regs->
++01453                                          gintmsk, gintmsk.d32, 0);
++01454                 }
++01455         }
++01456 }
++01457  
++01458 #ifdef DWC_HS_ELECT_TST
++01459 /*
++01460  * Quick and dirty hack to implement the HS Electrical Test
++01461  * SINGLE_STEP_GET_DEVICE_DESCRIPTOR feature.
++01462  *
++01463  * This code was copied from our userspace app "hset". It sends a
++01464  * Get Device Descriptor control sequence in two parts, first the
++01465  * Setup packet by itself, followed some time later by the In and
++01466  * Ack packets. Rather than trying to figure out how to add this
++01467  * functionality to the normal driver code, we just hijack the
++01468  * hardware, using these two function to drive the hardware
++01469  * directly.
++01470  */
++01471 
++01472 static dwc_otg_core_global_regs_t *global_regs;
++01473 static dwc_otg_host_global_regs_t *hc_global_regs;
++01474 static dwc_otg_hc_regs_t *hc_regs;
++01475 static uint32_t *data_fifo;
++01476 
++01477 static void do_setup(void)
++01478 {
++01479         gintsts_data_t gintsts;
++01480         hctsiz_data_t hctsiz;
++01481         hcchar_data_t hcchar;
++01482         haint_data_t haint;
++01483         hcint_data_t hcint;
++01484 
++01485         /* Enable HAINTs */
++01486         dwc_write_reg32(&hc_global_regs->haintmsk, 0x0001);
++01487 
++01488         /* Enable HCINTs */
++01489         dwc_write_reg32(&hc_regs->hcintmsk, 0x04a3);
++01490 
++01491         /* Read GINTSTS */
++01492         gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
++01493 
++01494         /* Read HAINT */
++01495         haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
++01496 
++01497         /* Read HCINT */
++01498         hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
++01499 
++01500         /* Read HCCHAR */
++01501         hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
++01502 
++01503         /* Clear HCINT */
++01504         dwc_write_reg32(&hc_regs->hcint, hcint.d32);
++01505 
++01506         /* Clear HAINT */
++01507         dwc_write_reg32(&hc_global_regs->haint, haint.d32);
++01508 
++01509         /* Clear GINTSTS */
++01510         dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
++01511 
++01512         /* Read GINTSTS */
++01513         gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
++01514 
++01515         /*
++01516          * Send Setup packet (Get Device Descriptor)
++01517          */
++01518 
++01519         /* Make sure channel is disabled */
++01520         hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
++01521         if (hcchar.b.chen) {
++01522                 hcchar.b.chdis = 1;
++01523 //              hcchar.b.chen = 1;
++01524                 dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
++01525                 //sleep(1);
++01526                 dwc_mdelay(1000);
++01527 
++01528                 /* Read GINTSTS */
++01529                 gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
++01530 
++01531                 /* Read HAINT */
++01532                 haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
++01533 
++01534                 /* Read HCINT */
++01535                 hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
++01536 
++01537                 /* Read HCCHAR */
++01538                 hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
++01539 
++01540                 /* Clear HCINT */
++01541                 dwc_write_reg32(&hc_regs->hcint, hcint.d32);
++01542 
++01543                 /* Clear HAINT */
++01544                 dwc_write_reg32(&hc_global_regs->haint, haint.d32);
++01545 
++01546                 /* Clear GINTSTS */
++01547                 dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
++01548 
++01549                 hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
++01550         }
++01551 
++01552         /* Set HCTSIZ */
++01553         hctsiz.d32 = 0;
++01554         hctsiz.b.xfersize = 8;
++01555         hctsiz.b.pktcnt = 1;
++01556         hctsiz.b.pid = DWC_OTG_HC_PID_SETUP;
++01557         dwc_write_reg32(&hc_regs->hctsiz, hctsiz.d32);
++01558 
++01559         /* Set HCCHAR */
++01560         hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
++01561         hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
++01562         hcchar.b.epdir = 0;
++01563         hcchar.b.epnum = 0;
++01564         hcchar.b.mps = 8;
++01565         hcchar.b.chen = 1;
++01566         dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
++01567 
++01568         /* Fill FIFO with Setup data for Get Device Descriptor */
++01569         data_fifo = (uint32_t *) ((char *)global_regs + 0x1000);
++01570         dwc_write_reg32(data_fifo++, 0x01000680);
++01571         dwc_write_reg32(data_fifo++, 0x00080000);
++01572 
++01573         gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
++01574 
++01575         /* Wait for host channel interrupt */
++01576         do {
++01577                 gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
++01578         } while (gintsts.b.hcintr == 0);
++01579 
++01580 
++01581         /* Disable HCINTs */
++01582         dwc_write_reg32(&hc_regs->hcintmsk, 0x0000);
++01583 
++01584         /* Disable HAINTs */
++01585         dwc_write_reg32(&hc_global_regs->haintmsk, 0x0000);
++01586 
++01587         /* Read HAINT */
++01588         haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
++01589 
++01590         /* Read HCINT */
++01591         hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
++01592 
++01593         /* Read HCCHAR */
++01594         hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
++01595 
++01596         /* Clear HCINT */
++01597         dwc_write_reg32(&hc_regs->hcint, hcint.d32);
++01598 
++01599         /* Clear HAINT */
++01600         dwc_write_reg32(&hc_global_regs->haint, haint.d32);
++01601 
++01602         /* Clear GINTSTS */
++01603         dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
++01604 
++01605         /* Read GINTSTS */
++01606         gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
++01607 }
++01608 
++01609 static void do_in_ack(void)
++01610 {
++01611         gintsts_data_t gintsts;
++01612         hctsiz_data_t hctsiz;
++01613         hcchar_data_t hcchar;
++01614         haint_data_t haint;
++01615         hcint_data_t hcint;
++01616         host_grxsts_data_t grxsts;
++01617 
++01618         /* Enable HAINTs */
++01619         dwc_write_reg32(&hc_global_regs->haintmsk, 0x0001);
++01620 
++01621         /* Enable HCINTs */
++01622         dwc_write_reg32(&hc_regs->hcintmsk, 0x04a3);
++01623 
++01624         /* Read GINTSTS */
++01625         gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
++01626 
++01627         /* Read HAINT */
++01628         haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
++01629 
++01630         /* Read HCINT */
++01631         hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
++01632 
++01633         /* Read HCCHAR */
++01634         hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
++01635 
++01636         /* Clear HCINT */
++01637         dwc_write_reg32(&hc_regs->hcint, hcint.d32);
++01638 
++01639         /* Clear HAINT */
++01640         dwc_write_reg32(&hc_global_regs->haint, haint.d32);
++01641 
++01642         /* Clear GINTSTS */
++01643         dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
++01644 
++01645         /* Read GINTSTS */
++01646         gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
++01647 
++01648         /*
++01649          * Receive Control In packet
++01650          */
++01651 
++01652         /* Make sure channel is disabled */
++01653         hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
++01654         if (hcchar.b.chen) {
++01655                 hcchar.b.chdis = 1;
++01656                 hcchar.b.chen = 1;
++01657                 dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
++01658                 //sleep(1);
++01659                 dwc_mdelay(1000);
++01660 
++01661                 /* Read GINTSTS */
++01662                 gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
++01663 
++01664                 /* Read HAINT */
++01665                 haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
++01666 
++01667                 /* Read HCINT */
++01668                 hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
++01669 
++01670                 /* Read HCCHAR */
++01671                 hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
++01672 
++01673                 /* Clear HCINT */
++01674                 dwc_write_reg32(&hc_regs->hcint, hcint.d32);
++01675 
++01676                 /* Clear HAINT */
++01677                 dwc_write_reg32(&hc_global_regs->haint, haint.d32);
++01678 
++01679                 /* Clear GINTSTS */
++01680                 dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
++01681 
++01682                 hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
++01683         }
++01684 
++01685         /* Set HCTSIZ */
++01686         hctsiz.d32 = 0;
++01687         hctsiz.b.xfersize = 8;
++01688         hctsiz.b.pktcnt = 1;
++01689         hctsiz.b.pid = DWC_OTG_HC_PID_DATA1;
++01690         dwc_write_reg32(&hc_regs->hctsiz, hctsiz.d32);
++01691 
++01692         /* Set HCCHAR */
++01693         hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
++01694         hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
++01695         hcchar.b.epdir = 1;
++01696         hcchar.b.epnum = 0;
++01697         hcchar.b.mps = 8;
++01698         hcchar.b.chen = 1;
++01699         dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
++01700 
++01701         gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
++01702 
++01703         /* Wait for receive status queue interrupt */
++01704         do {
++01705                 gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
++01706         } while (gintsts.b.rxstsqlvl == 0);
++01707 
++01708 
++01709         /* Read RXSTS */
++01710         grxsts.d32 = dwc_read_reg32(&global_regs->grxstsp);
++01711 
++01712         /* Clear RXSTSQLVL in GINTSTS */
++01713         gintsts.d32 = 0;
++01714         gintsts.b.rxstsqlvl = 1;
++01715         dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
++01716 
++01717         switch (grxsts.b.pktsts) {
++01718         case DWC_GRXSTS_PKTSTS_IN:
++01719                 /* Read the data into the host buffer */
++01720                 if (grxsts.b.bcnt > 0) {
++01721                         int i;
++01722                         int word_count = (grxsts.b.bcnt + 3) / 4;
++01723 
++01724                         data_fifo = (uint32_t *) ((char *)global_regs + 0x1000);
++01725 
++01726                         for (i = 0; i < word_count; i++) {
++01727                                 (void)dwc_read_reg32(data_fifo++);
++01728                         }
++01729                 }
++01730                 break;
++01731 
++01732         default:
++01733                 break;
++01734         }
++01735 
++01736         gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
++01737 
++01738         /* Wait for receive status queue interrupt */
++01739         do {
++01740                 gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
++01741         } while (gintsts.b.rxstsqlvl == 0);
++01742 
++01743 
++01744         /* Read RXSTS */
++01745         grxsts.d32 = dwc_read_reg32(&global_regs->grxstsp);
++01746 
++01747         /* Clear RXSTSQLVL in GINTSTS */
++01748         gintsts.d32 = 0;
++01749         gintsts.b.rxstsqlvl = 1;
++01750         dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
++01751 
++01752         switch (grxsts.b.pktsts) {
++01753         case DWC_GRXSTS_PKTSTS_IN_XFER_COMP:
++01754                 break;
++01755 
++01756         default:
++01757                 break;
++01758         }
++01759 
++01760         gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
++01761 
++01762         /* Wait for host channel interrupt */
++01763         do {
++01764                 gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
++01765         } while (gintsts.b.hcintr == 0);
++01766 
++01767 
++01768         /* Read HAINT */
++01769         haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
++01770 
++01771         /* Read HCINT */
++01772         hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
++01773 
++01774         /* Read HCCHAR */
++01775         hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
++01776 
++01777         /* Clear HCINT */
++01778         dwc_write_reg32(&hc_regs->hcint, hcint.d32);
++01779 
++01780         /* Clear HAINT */
++01781         dwc_write_reg32(&hc_global_regs->haint, haint.d32);
++01782 
++01783         /* Clear GINTSTS */
++01784         dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
++01785 
++01786         /* Read GINTSTS */
++01787         gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
++01788 
++01789 //      usleep(100000);
++01790 //      mdelay(100);
++01791         dwc_mdelay(1);
++01792 
++01793         /*
++01794          * Send handshake packet
++01795          */
++01796 
++01797         /* Read HAINT */
++01798         haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
++01799 
++01800         /* Read HCINT */
++01801         hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
++01802 
++01803         /* Read HCCHAR */
++01804         hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
++01805 
++01806         /* Clear HCINT */
++01807         dwc_write_reg32(&hc_regs->hcint, hcint.d32);
++01808 
++01809         /* Clear HAINT */
++01810         dwc_write_reg32(&hc_global_regs->haint, haint.d32);
++01811 
++01812         /* Clear GINTSTS */
++01813         dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
++01814 
++01815         /* Read GINTSTS */
++01816         gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
++01817 
++01818         /* Make sure channel is disabled */
++01819         hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
++01820         if (hcchar.b.chen) {
++01821                 hcchar.b.chdis = 1;
++01822                 hcchar.b.chen = 1;
++01823                 dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
++01824                 //sleep(1);
++01825                 dwc_mdelay(1000);
++01826 
++01827                 /* Read GINTSTS */
++01828                 gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
++01829 
++01830                 /* Read HAINT */
++01831                 haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
++01832 
++01833                 /* Read HCINT */
++01834                 hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
++01835 
++01836                 /* Read HCCHAR */
++01837                 hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
++01838 
++01839                 /* Clear HCINT */
++01840                 dwc_write_reg32(&hc_regs->hcint, hcint.d32);
++01841 
++01842                 /* Clear HAINT */
++01843                 dwc_write_reg32(&hc_global_regs->haint, haint.d32);
++01844 
++01845                 /* Clear GINTSTS */
++01846                 dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
++01847 
++01848                 hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
++01849         }
++01850 
++01851         /* Set HCTSIZ */
++01852         hctsiz.d32 = 0;
++01853         hctsiz.b.xfersize = 0;
++01854         hctsiz.b.pktcnt = 1;
++01855         hctsiz.b.pid = DWC_OTG_HC_PID_DATA1;
++01856         dwc_write_reg32(&hc_regs->hctsiz, hctsiz.d32);
++01857 
++01858         /* Set HCCHAR */
++01859         hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
++01860         hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
++01861         hcchar.b.epdir = 0;
++01862         hcchar.b.epnum = 0;
++01863         hcchar.b.mps = 8;
++01864         hcchar.b.chen = 1;
++01865         dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
++01866 
++01867         gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
++01868 
++01869         /* Wait for host channel interrupt */
++01870         do {
++01871                 gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
++01872         } while (gintsts.b.hcintr == 0);
++01873 
++01874 
++01875         /* Disable HCINTs */
++01876         dwc_write_reg32(&hc_regs->hcintmsk, 0x0000);
++01877 
++01878         /* Disable HAINTs */
++01879         dwc_write_reg32(&hc_global_regs->haintmsk, 0x0000);
++01880 
++01881         /* Read HAINT */
++01882         haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
++01883 
++01884         /* Read HCINT */
++01885         hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
++01886 
++01887         /* Read HCCHAR */
++01888         hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
++01889 
++01890         /* Clear HCINT */
++01891         dwc_write_reg32(&hc_regs->hcint, hcint.d32);
++01892 
++01893         /* Clear HAINT */
++01894         dwc_write_reg32(&hc_global_regs->haint, haint.d32);
++01895 
++01896         /* Clear GINTSTS */
++01897         dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
++01898 
++01899         /* Read GINTSTS */
++01900         gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
++01901 }
++01902 #endif
++01903 
++01905 int dwc_otg_hcd_hub_control(dwc_otg_hcd_t * dwc_otg_hcd,
++01906                             uint16_t typeReq,
++01907                             uint16_t wValue,
++01908                             uint16_t wIndex, uint8_t * buf, uint16_t wLength)
++01909 {
++01910         int retval = 0;
++01911 
++01912         dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;
++01913         usb_hub_descriptor_t *hub_desc;
++01914         hprt0_data_t hprt0 = {.d32 = 0 };
++01915 
++01916         uint32_t port_status;
++01917 
++01918         switch (typeReq) {
++01919         case UCR_CLEAR_HUB_FEATURE:
++01920                 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
++01921                             "ClearHubFeature 0x%x\n", wValue);
++01922                 switch (wValue) {
++01923                 case UHF_C_HUB_LOCAL_POWER:
++01924                 case UHF_C_HUB_OVER_CURRENT:
++01925                         /* Nothing required here */
++01926                         break;
++01927                 default:
++01928                         retval = -DWC_E_INVALID;
++01929                         DWC_ERROR("DWC OTG HCD - "
++01930                                   "ClearHubFeature request %xh unknown\n",
++01931                                   wValue);
++01932                 }
++01933                 break;
++01934         case UCR_CLEAR_PORT_FEATURE:
++01935 #ifdef CONFIG_USB_DWC_OTG_LPM
++01936                 if (wValue != UHF_PORT_L1)
++01937 #endif
++01938                         if (!wIndex || wIndex > 1)
++01939                                 goto error;
++01940 
++01941                 switch (wValue) {
++01942                 case UHF_PORT_ENABLE:
++01943                         DWC_DEBUGPL(DBG_ANY, "DWC OTG HCD HUB CONTROL - "
++01944                                     "ClearPortFeature USB_PORT_FEAT_ENABLE\n");
++01945                         hprt0.d32 = dwc_otg_read_hprt0(core_if);
++01946                         hprt0.b.prtena = 1;
++01947                         dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
++01948                         break;
++01949                 case UHF_PORT_SUSPEND:
++01950                         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
++01951                                     "ClearPortFeature USB_PORT_FEAT_SUSPEND\n");
++01952 
++01953                         dwc_write_reg32(core_if->pcgcctl, 0);
++01954                         dwc_mdelay(5);
++01955 
++01956                         hprt0.d32 = dwc_otg_read_hprt0(core_if);
++01957                         hprt0.b.prtres = 1;
++01958                         dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
++01959                         hprt0.b.prtsusp = 0;
++01960                         /* Clear Resume bit */
++01961                         dwc_mdelay(100);
++01962                         hprt0.b.prtres = 0;
++01963                         dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
++01964                         break;
++01965 #ifdef CONFIG_USB_DWC_OTG_LPM
++01966                 case UHF_PORT_L1:
++01967                         {
++01968                                 pcgcctl_data_t pcgcctl = {.d32 = 0 };
++01969                                 glpmcfg_data_t lpmcfg = {.d32 = 0 };
++01970 
++01971                                 lpmcfg.d32 =
++01972                                     dwc_read_reg32(&core_if->core_global_regs->
++01973                                                    glpmcfg);
++01974                                 lpmcfg.b.en_utmi_sleep = 0;
++01975                                 lpmcfg.b.hird_thres &= (~(1 << 4));
++01976                                 lpmcfg.b.prt_sleep_sts = 1;
++01977                                 dwc_write_reg32(&core_if->core_global_regs->
++01978                                                 glpmcfg, lpmcfg.d32);
++01979 
++01980                                 /* Clear Enbl_L1Gating bit. */
++01981                                 pcgcctl.b.enbl_sleep_gating = 1;
++01982                                 dwc_modify_reg32(core_if->pcgcctl, pcgcctl.d32,
++01983                                                  0);
++01984 
++01985                                 dwc_mdelay(5);
++01986 
++01987                                 hprt0.d32 = dwc_otg_read_hprt0(core_if);
++01988                                 hprt0.b.prtres = 1;
++01989                                 dwc_write_reg32(core_if->host_if->hprt0,
++01990                                                 hprt0.d32);
++01991                                 /* This bit will be cleared in wakeup interrupt handle */
++01992                                 break;
++01993                         }
++01994 #endif
++01995                 case UHF_PORT_POWER:
++01996                         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
++01997                                     "ClearPortFeature USB_PORT_FEAT_POWER\n");
++01998                         hprt0.d32 = dwc_otg_read_hprt0(core_if);
++01999                         hprt0.b.prtpwr = 0;
++02000                         dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
++02001                         break;
++02002                 case UHF_PORT_INDICATOR:
++02003                         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
++02004                                     "ClearPortFeature USB_PORT_FEAT_INDICATOR\n");
++02005                         /* Port inidicator not supported */
++02006                         break;
++02007                 case UHF_C_PORT_CONNECTION:
++02008                         /* Clears drivers internal connect status change
++02009                          * flag */
++02010                         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
++02011                                     "ClearPortFeature USB_PORT_FEAT_C_CONNECTION\n");
++02012                         dwc_otg_hcd->flags.b.port_connect_status_change = 0;
++02013                         break;
++02014                 case UHF_C_PORT_RESET:
++02015                         /* Clears the driver's internal Port Reset Change
++02016                          * flag */
++02017                         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
++02018                                     "ClearPortFeature USB_PORT_FEAT_C_RESET\n");
++02019                         dwc_otg_hcd->flags.b.port_reset_change = 0;
++02020                         break;
++02021                 case UHF_C_PORT_ENABLE:
++02022                         /* Clears the driver's internal Port
++02023                          * Enable/Disable Change flag */
++02024                         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
++02025                                     "ClearPortFeature USB_PORT_FEAT_C_ENABLE\n");
++02026                         dwc_otg_hcd->flags.b.port_enable_change = 0;
++02027                         break;
++02028                 case UHF_C_PORT_SUSPEND:
++02029                         /* Clears the driver's internal Port Suspend
++02030                          * Change flag, which is set when resume signaling on
++02031                          * the host port is complete */
++02032                         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
++02033                                     "ClearPortFeature USB_PORT_FEAT_C_SUSPEND\n");
++02034                         dwc_otg_hcd->flags.b.port_suspend_change = 0;
++02035                         break;
++02036 #ifdef CONFIG_USB_DWC_OTG_LPM
++02037                 case UHF_C_PORT_L1:
++02038                         dwc_otg_hcd->flags.b.port_l1_change = 0;
++02039                         break;
++02040 #endif
++02041                 case UHF_C_PORT_OVER_CURRENT:
++02042                         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
++02043                                     "ClearPortFeature USB_PORT_FEAT_C_OVER_CURRENT\n");
++02044                         dwc_otg_hcd->flags.b.port_over_current_change = 0;
++02045                         break;
++02046                 default:
++02047                         retval = -DWC_E_INVALID;
++02048                         DWC_ERROR("DWC OTG HCD - "
++02049                                   "ClearPortFeature request %xh "
++02050                                   "unknown or unsupported\n", wValue);
++02051                 }
++02052                 break;
++02053         case UCR_GET_HUB_DESCRIPTOR:
++02054                 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
++02055                             "GetHubDescriptor\n");
++02056                 hub_desc = (usb_hub_descriptor_t *) buf;
++02057                 hub_desc->bDescLength = 9;
++02058                 hub_desc->bDescriptorType = 0x29;
++02059                 hub_desc->bNbrPorts = 1;
++02060                 USETW(hub_desc->wHubCharacteristics, 0x08);
++02061                 hub_desc->bPwrOn2PwrGood = 1;
++02062                 hub_desc->bHubContrCurrent = 0;
++02063                 hub_desc->DeviceRemovable[0] = 0;
++02064                 hub_desc->DeviceRemovable[1] = 0xff;
++02065                 break;
++02066         case UCR_GET_HUB_STATUS:
++02067                 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
++02068                             "GetHubStatus\n");
++02069                 DWC_MEMSET(buf, 0, 4);
++02070                 break;
++02071         case UCR_GET_PORT_STATUS:
++02072                 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
++02073                             "GetPortStatus\n");
++02074                 if (!wIndex || wIndex > 1)
++02075                         goto error;
++02076 
++02077                 port_status = 0;
++02078 
++02079                 if (dwc_otg_hcd->flags.b.port_connect_status_change)
++02080                         port_status |= (1 << UHF_C_PORT_CONNECTION);
++02081 
++02082                 if (dwc_otg_hcd->flags.b.port_enable_change)
++02083                         port_status |= (1 << UHF_C_PORT_ENABLE);
++02084 
++02085                 if (dwc_otg_hcd->flags.b.port_suspend_change)
++02086                         port_status |= (1 << UHF_C_PORT_SUSPEND);
++02087 
++02088                 if (dwc_otg_hcd->flags.b.port_l1_change)
++02089                         port_status |= (1 << UHF_C_PORT_L1);
++02090 
++02091                 if (dwc_otg_hcd->flags.b.port_reset_change) {
++02092                         port_status |= (1 << UHF_C_PORT_RESET);
++02093                 }
++02094 
++02095                 if (dwc_otg_hcd->flags.b.port_over_current_change) {
++02096                         DWC_ERROR("Device Not Supported\n");
++02097                         port_status |= (1 << UHF_C_PORT_OVER_CURRENT);
++02098                 }
++02099 
++02100                 if (!dwc_otg_hcd->flags.b.port_connect_status) {
++02101                         /*
++02102                          * The port is disconnected, which means the core is
++02103                          * either in device mode or it soon will be. Just
++02104                          * return 0's for the remainder of the port status
++02105                          * since the port register can't be read if the core
++02106                          * is in device mode.
++02107                          */
++02108                         *((__le32 *) buf) = dwc_cpu_to_le32(&port_status);
++02109                         break;
++02110                 }
++02111 
++02112                 hprt0.d32 = dwc_read_reg32(core_if->host_if->hprt0);
++02113                 DWC_DEBUGPL(DBG_HCDV, "  HPRT0: 0x%08x\n", hprt0.d32);
++02114 
++02115                 if (hprt0.b.prtconnsts)
++02116                         port_status |= (1 << UHF_PORT_CONNECTION);
++02117 
++02118                 if (hprt0.b.prtena)
++02119                         port_status |= (1 << UHF_PORT_ENABLE);
++02120 
++02121                 if (hprt0.b.prtsusp)
++02122                         port_status |= (1 << UHF_PORT_SUSPEND);
++02123 
++02124                 if (hprt0.b.prtovrcurract)
++02125                         port_status |= (1 << UHF_PORT_OVER_CURRENT);
++02126 
++02127                 if (hprt0.b.prtrst)
++02128                         port_status |= (1 << UHF_PORT_RESET);
++02129 
++02130                 if (hprt0.b.prtpwr)
++02131                         port_status |= (1 << UHF_PORT_POWER);
++02132 
++02133                 if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_HIGH_SPEED)
++02134                         port_status |= (1 << UHF_PORT_HIGH_SPEED);
++02135                 else if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_LOW_SPEED)
++02136                         port_status |= (1 << UHF_PORT_LOW_SPEED);
++02137 
++02138                 if (hprt0.b.prttstctl)
++02139                         port_status |= (1 << UHF_PORT_TEST);
++02140                 if (dwc_otg_get_lpm_portsleepstatus(dwc_otg_hcd->core_if)) {
++02141                         port_status |= (1 << UHF_PORT_L1);
++02142                 }
++02143 
++02144                 /* USB_PORT_FEAT_INDICATOR unsupported always 0 */
++02145 
++02146                 *((__le32 *) buf) = dwc_cpu_to_le32(&port_status);
++02147 
++02148                 break;
++02149         case UCR_SET_HUB_FEATURE:
++02150                 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
++02151                             "SetHubFeature\n");
++02152                 /* No HUB features supported */
++02153                 break;
++02154         case UCR_SET_PORT_FEATURE:
++02155                 if (wValue != UHF_PORT_TEST && (!wIndex || wIndex > 1))
++02156                         goto error;
++02157 
++02158                 if (!dwc_otg_hcd->flags.b.port_connect_status) {
++02159                         /*
++02160                          * The port is disconnected, which means the core is
++02161                          * either in device mode or it soon will be. Just
++02162                          * return without doing anything since the port
++02163                          * register can't be written if the core is in device
++02164                          * mode.
++02165                          */
++02166                         break;
++02167                 }
++02168 
++02169                 switch (wValue) {
++02170                 case UHF_PORT_SUSPEND:
++02171                         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
++02172                                     "SetPortFeature - USB_PORT_FEAT_SUSPEND\n");
++02173                         if (dwc_otg_hcd_otg_port(dwc_otg_hcd) == wIndex &&
++02174                             dwc_otg_hcd->fops->get_b_hnp_enable(dwc_otg_hcd)) {
++02175                                 gotgctl_data_t gotgctl = {.d32 = 0 };
++02176                                 gotgctl.b.hstsethnpen = 1;
++02177                                 dwc_modify_reg32(&core_if->core_global_regs->
++02178                                                  gotgctl, 0, gotgctl.d32);
++02179                                 core_if->op_state = A_SUSPEND;
++02180                         }
++02181                         hprt0.d32 = dwc_otg_read_hprt0(core_if);
++02182                         hprt0.b.prtsusp = 1;
++02183                         dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
++02184                         {
++02185                                 uint64_t flags;
++02186                                 /* Update lx_state */
++02187                                 DWC_SPINLOCK_IRQSAVE(dwc_otg_hcd->lock, &flags);
++02188                                 core_if->lx_state = DWC_OTG_L2;
++02189                                 DWC_SPINUNLOCK_IRQRESTORE(dwc_otg_hcd->lock, flags);
++02190                         }
++02191                         /* Suspend the Phy Clock */
++02192                         {
++02193                                 pcgcctl_data_t pcgcctl = {.d32 = 0 };
++02194                                 pcgcctl.b.stoppclk = 1;
++02195                                 dwc_modify_reg32(core_if->pcgcctl, 0,
++02196                                                  pcgcctl.d32);
++02197                         }
++02198 
++02199                         /* For HNP the bus must be suspended for at least 200ms. */
++02200                         if (dwc_otg_hcd->fops->get_b_hnp_enable(dwc_otg_hcd)) {
++02201                                 dwc_mdelay(200);
++02202                         }
++02203                         break;
++02204                 case UHF_PORT_POWER:
++02205                         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
++02206                                     "SetPortFeature - USB_PORT_FEAT_POWER\n");
++02207                         hprt0.d32 = dwc_otg_read_hprt0(core_if);
++02208                         hprt0.b.prtpwr = 1;
++02209                         dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
++02210                         break;
++02211                 case UHF_PORT_RESET:
++02212                         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
++02213                                     "SetPortFeature - USB_PORT_FEAT_RESET\n");
++02214                         {
++02215                                 pcgcctl_data_t pcgcctl = {.d32 = 0 };
++02216                                 pcgcctl.b.enbl_sleep_gating = 1;
++02217                                 pcgcctl.b.stoppclk = 1;
++02218                                 dwc_modify_reg32(core_if->pcgcctl, pcgcctl.d32,
++02219                                                  0);
++02220                                 dwc_write_reg32(core_if->pcgcctl, 0);
++02221                         }
++02222 #ifdef CONFIG_USB_DWC_OTG_LPM
++02223                         {
++02224                                 glpmcfg_data_t lpmcfg;
++02225                                 lpmcfg.d32 =
++02226                                     dwc_read_reg32(&core_if->core_global_regs->
++02227                                                    glpmcfg);
++02228                                 if (lpmcfg.b.prt_sleep_sts) {
++02229                                         lpmcfg.b.en_utmi_sleep = 0;
++02230                                         lpmcfg.b.hird_thres &= (~(1 << 4));
++02231                                         dwc_write_reg32(&core_if->
++02232                                                         core_global_regs->
++02233                                                         glpmcfg, lpmcfg.d32);
++02234                                         dwc_mdelay(1);
++02235                                 }
++02236                         }
++02237 #endif
++02238                         hprt0.d32 = dwc_otg_read_hprt0(core_if);
++02239                         /* When B-Host the Port reset bit is set in
++02240                          * the Start HCD Callback function, so that
++02241                          * the reset is started within 1ms of the HNP
++02242                          * success interrupt. */
++02243                         if (!dwc_otg_hcd_is_b_host(dwc_otg_hcd)) {
++02244                                 hprt0.b.prtrst = 1;
++02245                                 dwc_write_reg32(core_if->host_if->hprt0,
++02246                                                 hprt0.d32);
++02247                         }
++02248                         /* Clear reset bit in 10ms (FS/LS) or 50ms (HS) */
++02249                         dwc_mdelay(60);
++02250                         hprt0.b.prtrst = 0;
++02251                         dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
++02252                         core_if->lx_state = DWC_OTG_L0; /* Now back to the on state */
++02253                         break;
++02254 #ifdef DWC_HS_ELECT_TST
++02255                 case UHF_PORT_TEST:
++02256                         {
++02257                                 uint32_t t;
++02258                                 gintmsk_data_t gintmsk;
++02259 
++02260                                 t = (wIndex >> 8);      /* MSB wIndex USB */
++02261                                 DWC_DEBUGPL(DBG_HCD,
++02262                                             "DWC OTG HCD HUB CONTROL - "
++02263                                             "SetPortFeature - USB_PORT_FEAT_TEST %d\n",
++02264                                             t);
++02265                                 DWC_WARN("USB_PORT_FEAT_TEST %d\n", t);
++02266                                 if (t < 6) {
++02267                                         hprt0.d32 = dwc_otg_read_hprt0(core_if);
++02268                                         hprt0.b.prttstctl = t;
++02269                                         dwc_write_reg32(core_if->host_if->hprt0,
++02270                                                         hprt0.d32);
++02271                                 } else {
++02272                                         /* Setup global vars with reg addresses (quick and
++02273                                          * dirty hack, should be cleaned up)
++02274                                          */
++02275                                         global_regs = core_if->core_global_regs;
++02276                                         hc_global_regs =
++02277                                             core_if->host_if->host_global_regs;
++02278                                         hc_regs =
++02279                                             (dwc_otg_hc_regs_t *) ((char *)
++02280                                                                    global_regs +
++02281                                                                    0x500);
++02282                                         data_fifo =
++02283                                             (uint32_t *) ((char *)global_regs +
++02284                                                           0x1000);
++02285 
++02286                                         if (t == 6) {   /* HS_HOST_PORT_SUSPEND_RESUME */
++02287                                                 /* Save current interrupt mask */
++02288                                                 gintmsk.d32 =
++02289                                                     dwc_read_reg32
++02290                                                     (&global_regs->gintmsk);
++02291 
++02292                                                 /* Disable all interrupts while we muck with
++02293                                                  * the hardware directly
++02294                                                  */
++02295                                                 dwc_write_reg32(&global_regs->
++02296                                                                 gintmsk, 0);
++02297 
++02298                                                 /* 15 second delay per the test spec */
++02299                                                 dwc_mdelay(15000);
++02300 
++02301                                                 /* Drive suspend on the root port */
++02302                                                 hprt0.d32 =
++02303                                                     dwc_otg_read_hprt0(core_if);
++02304                                                 hprt0.b.prtsusp = 1;
++02305                                                 hprt0.b.prtres = 0;
++02306                                                 dwc_write_reg32(core_if->
++02307                                                                 host_if->hprt0,
++02308                                                                 hprt0.d32);
++02309 
++02310                                                 /* 15 second delay per the test spec */
++02311                                                 dwc_mdelay(15000);
++02312 
++02313                                                 /* Drive resume on the root port */
++02314                                                 hprt0.d32 =
++02315                                                     dwc_otg_read_hprt0(core_if);
++02316                                                 hprt0.b.prtsusp = 0;
++02317                                                 hprt0.b.prtres = 1;
++02318                                                 dwc_write_reg32(core_if->
++02319                                                                 host_if->hprt0,
++02320                                                                 hprt0.d32);
++02321                                                 dwc_mdelay(100);
++02322 
++02323                                                 /* Clear the resume bit */
++02324                                                 hprt0.b.prtres = 0;
++02325                                                 dwc_write_reg32(core_if->
++02326                                                                 host_if->hprt0,
++02327                                                                 hprt0.d32);
++02328 
++02329                                                 /* Restore interrupts */
++02330                                                 dwc_write_reg32(&global_regs->
++02331                                                                 gintmsk,
++02332                                                                 gintmsk.d32);
++02333                                         } else if (t == 7) {    /* SINGLE_STEP_GET_DEVICE_DESCRIPTOR setup */
++02334                                                 /* Save current interrupt mask */
++02335                                                 gintmsk.d32 =
++02336                                                     dwc_read_reg32
++02337                                                     (&global_regs->gintmsk);
++02338 
++02339                                                 /* Disable all interrupts while we muck with
++02340                                                  * the hardware directly
++02341                                                  */
++02342                                                 dwc_write_reg32(&global_regs->
++02343                                                                 gintmsk, 0);
++02344 
++02345                                                 /* 15 second delay per the test spec */
++02346                                                 dwc_mdelay(15000);
++02347 
++02348                                                 /* Send the Setup packet */
++02349                                                 do_setup();
++02350 
++02351                                                 /* 15 second delay so nothing else happens for awhile */
++02352                                                 dwc_mdelay(15000);
++02353 
++02354                                                 /* Restore interrupts */
++02355                                                 dwc_write_reg32(&global_regs->
++02356                                                                 gintmsk,
++02357                                                                 gintmsk.d32);
++02358                                         } else if (t == 8) {    /* SINGLE_STEP_GET_DEVICE_DESCRIPTOR execute */
++02359                                                 /* Save current interrupt mask */
++02360                                                 gintmsk.d32 =
++02361                                                     dwc_read_reg32
++02362                                                     (&global_regs->gintmsk);
++02363 
++02364                                                 /* Disable all interrupts while we muck with
++02365                                                  * the hardware directly
++02366                                                  */
++02367                                                 dwc_write_reg32(&global_regs->
++02368                                                                 gintmsk, 0);
++02369 
++02370                                                 /* Send the Setup packet */
++02371                                                 do_setup();
++02372 
++02373                                                 /* 15 second delay so nothing else happens for awhile */
++02374                                                 dwc_mdelay(15000);
++02375 
++02376                                                 /* Send the In and Ack packets */
++02377                                                 do_in_ack();
++02378 
++02379                                                 /* 15 second delay so nothing else happens for awhile */
++02380                                                 dwc_mdelay(15000);
++02381 
++02382                                                 /* Restore interrupts */
++02383                                                 dwc_write_reg32(&global_regs->
++02384                                                                 gintmsk,
++02385                                                                 gintmsk.d32);
++02386                                         }
++02387                                 }
++02388                                 break;
++02389                         }
++02390 #endif                          /* DWC_HS_ELECT_TST */
++02391 
++02392                 case UHF_PORT_INDICATOR:
++02393                         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
++02394                                     "SetPortFeature - USB_PORT_FEAT_INDICATOR\n");
++02395                         /* Not supported */
++02396                         break;
++02397                 default:
++02398                         retval = -DWC_E_INVALID;
++02399                         DWC_ERROR("DWC OTG HCD - "
++02400                                   "SetPortFeature request %xh "
++02401                                   "unknown or unsupported\n", wValue);
++02402                         break;
++02403                 }
++02404                 break;
++02405 #ifdef CONFIG_USB_DWC_OTG_LPM
++02406         case UCR_SET_AND_TEST_PORT_FEATURE:
++02407                 if (wValue != UHF_PORT_L1) {
++02408                         goto error;
++02409                 }
++02410                 {
++02411                         int portnum, hird, devaddr, remwake;
++02412                         glpmcfg_data_t lpmcfg;
++02413                         uint32_t time_usecs;
++02414                         gintsts_data_t gintsts;
++02415                         gintmsk_data_t gintmsk;
++02416 
++02417                         if (!dwc_otg_get_param_lpm_enable(core_if)) {
++02418                                 goto error;
++02419                         }
++02420                         if (wValue != UHF_PORT_L1 || wLength != 1) {
++02421                                 goto error;
++02422                         }
++02423                         /* Check if the port currently is in SLEEP state */
++02424                         lpmcfg.d32 =
++02425                             dwc_read_reg32(&core_if->core_global_regs->glpmcfg);
++02426                         if (lpmcfg.b.prt_sleep_sts) {
++02427                                 DWC_INFO("Port is already in sleep mode\n");
++02428                                 buf[0] = 0;     /* Return success */
++02429                                 break;
++02430                         }
++02431 
++02432                         portnum = wIndex & 0xf;
++02433                         hird = (wIndex >> 4) & 0xf;
++02434                         devaddr = (wIndex >> 8) & 0x7f;
++02435                         remwake = (wIndex >> 15);
++02436 
++02437                         if (portnum != 1) {
++02438                                 retval = -DWC_E_INVALID;
++02439                                 DWC_WARN
++02440                                     ("Wrong port number(%d) in SetandTestPortFeature request\n",
++02441                                      portnum);
++02442                                 break;
++02443                         }
++02444 
++02445                         DWC_PRINTF
++02446                             ("SetandTestPortFeature request: portnum = %d, hird = %d, devaddr = %d, rewake = %d\n",
++02447                              portnum, hird, devaddr, remwake);
++02448                         /* Disable LPM interrupt */
++02449                         gintmsk.d32 = 0;
++02450                         gintmsk.b.lpmtranrcvd = 1;
++02451                         dwc_modify_reg32(&core_if->core_global_regs->gintmsk,
++02452                                          gintmsk.d32, 0);
++02453 
++02454                         if (dwc_otg_hcd_send_lpm
++02455                             (dwc_otg_hcd, devaddr, hird, remwake)) {
++02456                                 retval = -DWC_E_INVALID;
++02457                                 break;
++02458                         }
++02459 
++02460                         time_usecs = 10 * (lpmcfg.b.retry_count + 1);
++02461                         /* We will consider timeout if time_usecs microseconds pass,
++02462                          * and we don't receive LPM transaction status.
++02463                          * After receiving non-error responce(ACK/NYET/STALL) from device,
++02464                          *  core will set lpmtranrcvd bit.
++02465                          */
++02466                         do {
++02467                                 gintsts.d32 =
++02468                                     dwc_read_reg32(&core_if->core_global_regs->
++02469                                                    gintsts);
++02470                                 if (gintsts.b.lpmtranrcvd) {
++02471                                         break;
++02472                                 }
++02473                                 dwc_udelay(1);
++02474                         } while (--time_usecs);
++02475                         /* lpm_int bit will be cleared in LPM interrupt handler */
++02476 
++02477                         /* Now fill status
++02478                          * 0x00 - Success
++02479                          * 0x10 - NYET
++02480                          * 0x11 - Timeout
++02481                          */
++02482                         if (!gintsts.b.lpmtranrcvd) {
++02483                                 buf[0] = 0x3;   /* Completion code is Timeout */
++02484                                 dwc_otg_hcd_free_hc_from_lpm(dwc_otg_hcd);
++02485                         } else {
++02486                                 lpmcfg.d32 =
++02487                                     dwc_read_reg32(&core_if->core_global_regs->
++02488                                                    glpmcfg);
++02489                                 if (lpmcfg.b.lpm_resp == 0x3) {
++02490                                         /* ACK responce from the device */
++02491                                         buf[0] = 0x00;  /* Success */
++02492                                 } else if (lpmcfg.b.lpm_resp == 0x2) {
++02493                                         /* NYET responce from the device */
++02494                                         buf[0] = 0x2;
++02495                                 } else {
++02496                                         /* Otherwise responce with Timeout */
++02497                                         buf[0] = 0x3;
++02498                                 }
++02499                         }
++02500                         DWC_PRINTF("Device responce to LPM trans is %x\n",
++02501                                    lpmcfg.b.lpm_resp);
++02502                         dwc_modify_reg32(&core_if->core_global_regs->gintmsk, 0,
++02503                                          gintmsk.d32);
++02504 
++02505                         break;
++02506                 }
++02507 #endif                          /* CONFIG_USB_DWC_OTG_LPM */
++02508         default:
++02509               error:
++02510                 retval = -DWC_E_INVALID;
++02511                 DWC_WARN("DWC OTG HCD - "
++02512                          "Unknown hub control request type or invalid typeReq: %xh wIndex: %xh wValue: %xh\n",
++02513                          typeReq, wIndex, wValue);
++02514                 break;
++02515         }
++02516 
++02517         return retval;
++02518 }
++02519 
++02520 #ifdef CONFIG_USB_DWC_OTG_LPM
++02521 
++02522 int dwc_otg_hcd_get_hc_for_lpm_tran(dwc_otg_hcd_t * hcd, uint8_t devaddr)
++02523 {
++02524         dwc_otg_core_if_t *core_if = hcd->core_if;
++02525         dwc_hc_t *hc;
++02526         hcchar_data_t hcchar;
++02527         gintmsk_data_t gintmsk = {.d32 = 0 };
++02528 
++02529         if (DWC_CIRCLEQ_EMPTY(&hcd->free_hc_list)) {
++02530                 DWC_PRINTF("No free channel to select for LPM transaction\n");
++02531                 return -1;
++02532         }
++02533 
++02534         hc = DWC_CIRCLEQ_FIRST(&hcd->free_hc_list);
++02535 
++02536         /* Mask host channel interrupts. */
++02537         gintmsk.b.hcintr = 1;
++02538         dwc_modify_reg32(&core_if->core_global_regs->gintmsk, gintmsk.d32, 0);
++02539 
++02540         /* Fill fields that core needs for LPM transaction */
++02541         hcchar.b.devaddr = devaddr;
++02542         hcchar.b.epnum = 0;
++02543         hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
++02544         hcchar.b.mps = 64;
++02545         hcchar.b.lspddev = (hc->speed == DWC_OTG_EP_SPEED_LOW);
++02546         hcchar.b.epdir = 0;     /* OUT */
++02547         dwc_write_reg32(&core_if->host_if->hc_regs[hc->hc_num]->hcchar,
++02548                         hcchar.d32);
++02549 
++02550         /* Remove the host channel from the free list. */
++02551         DWC_CIRCLEQ_REMOVE_INIT(&hcd->free_hc_list, hc, hc_list_entry);
++02552 
++02553         DWC_PRINTF("hcnum = %d devaddr = %d\n", hc->hc_num, devaddr);
++02554 
++02555         return hc->hc_num;
++02556 }
++02557 
++02559 void dwc_otg_hcd_free_hc_from_lpm(dwc_otg_hcd_t * hcd)
++02560 {
++02561         dwc_hc_t *hc;
++02562         glpmcfg_data_t lpmcfg;
++02563         uint8_t hc_num;
++02564 
++02565         lpmcfg.d32 = dwc_read_reg32(&hcd->core_if->core_global_regs->glpmcfg);
++02566         hc_num = lpmcfg.b.lpm_chan_index;
++02567 
++02568         hc = hcd->hc_ptr_array[hc_num];
++02569 
++02570         DWC_PRINTF("Freeing channel %d after LPM\n", hc_num);
++02571         /* Return host channel to free list */
++02572         DWC_CIRCLEQ_INSERT_TAIL(&hcd->free_hc_list, hc, hc_list_entry);
++02573 }
++02574 
++02575 int dwc_otg_hcd_send_lpm(dwc_otg_hcd_t * hcd, uint8_t devaddr, uint8_t hird,
++02576                          uint8_t bRemoteWake)
++02577 {
++02578         glpmcfg_data_t lpmcfg;
++02579         pcgcctl_data_t pcgcctl = {.d32 = 0 };
++02580         int channel;
++02581 
++02582         channel = dwc_otg_hcd_get_hc_for_lpm_tran(hcd, devaddr);
++02583         if (channel < 0) {
++02584                 return channel;
++02585         }
++02586 
++02587         pcgcctl.b.enbl_sleep_gating = 1;
++02588         dwc_modify_reg32(hcd->core_if->pcgcctl, 0, pcgcctl.d32);
++02589 
++02590         /* Read LPM config register */
++02591         lpmcfg.d32 = dwc_read_reg32(&hcd->core_if->core_global_regs->glpmcfg);
++02592 
++02593         /* Program LPM transaction fields */
++02594         lpmcfg.b.rem_wkup_en = bRemoteWake;
++02595         lpmcfg.b.hird = hird;
++02596         lpmcfg.b.hird_thres = 0x1c;
++02597         lpmcfg.b.lpm_chan_index = channel;
++02598         lpmcfg.b.en_utmi_sleep = 1;
++02599         /* Program LPM config register */
++02600         dwc_write_reg32(&hcd->core_if->core_global_regs->glpmcfg, lpmcfg.d32);
++02601 
++02602         /* Send LPM transaction */
++02603         lpmcfg.b.send_lpm = 1;
++02604         dwc_write_reg32(&hcd->core_if->core_global_regs->glpmcfg, lpmcfg.d32);
++02605 
++02606         return 0;
++02607 }
++02608 
++02609 #endif                          /* CONFIG_USB_DWC_OTG_LPM */
++02610 
++02611 int dwc_otg_hcd_is_status_changed(dwc_otg_hcd_t * hcd, int port)
++02612 {
++02613         int retval;
++02614 
++02615         if (port != 1) {
++02616                 return -DWC_E_INVALID;
++02617         }
++02618 
++02619         retval = (hcd->flags.b.port_connect_status_change ||
++02620                   hcd->flags.b.port_reset_change ||
++02621                   hcd->flags.b.port_enable_change ||
++02622                   hcd->flags.b.port_suspend_change ||
++02623                   hcd->flags.b.port_over_current_change);
++02624 #ifdef DEBUG
++02625         if (retval) {
++02626                 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB STATUS DATA:"
++02627                             " Root port status changed\n");
++02628                 DWC_DEBUGPL(DBG_HCDV, "  port_connect_status_change: %d\n",
++02629                             hcd->flags.b.port_connect_status_change);
++02630                 DWC_DEBUGPL(DBG_HCDV, "  port_reset_change: %d\n",
++02631                             hcd->flags.b.port_reset_change);
++02632                 DWC_DEBUGPL(DBG_HCDV, "  port_enable_change: %d\n",
++02633                             hcd->flags.b.port_enable_change);
++02634                 DWC_DEBUGPL(DBG_HCDV, "  port_suspend_change: %d\n",
++02635                             hcd->flags.b.port_suspend_change);
++02636                 DWC_DEBUGPL(DBG_HCDV, "  port_over_current_change: %d\n",
++02637                             hcd->flags.b.port_over_current_change);
++02638         }
++02639 #endif
++02640         return retval;
++02641 }
++02642 
++02643 int dwc_otg_hcd_get_frame_number(dwc_otg_hcd_t * dwc_otg_hcd)
++02644 {
++02645         hfnum_data_t hfnum;
++02646         hfnum.d32 = dwc_read_reg32(&dwc_otg_hcd->core_if->
++02647                                    host_if->host_global_regs->hfnum);
++02648 
++02649 #ifdef DEBUG_SOF
++02650         DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD GET FRAME NUMBER %d\n",
++02651                     hfnum.b.frnum);
++02652 #endif
++02653         return hfnum.b.frnum;
++02654 }
++02655 
++02656 int dwc_otg_hcd_start(dwc_otg_hcd_t * hcd,
++02657                       struct dwc_otg_hcd_function_ops *fops)
++02658 {
++02659         int retval = 0;
++02660 
++02661         hcd->fops = fops;
++02662         if (!dwc_otg_is_device_mode(hcd->core_if)) {
++02663                 dwc_otg_hcd_reinit(hcd);
++02664         } else {
++02665                 retval = -DWC_E_NO_DEVICE;
++02666         }
++02667 
++02668         return retval;
++02669 }
++02670 
++02671 void *dwc_otg_hcd_get_priv_data(dwc_otg_hcd_t * hcd)
++02672 {
++02673         return hcd->priv;
++02674 }
++02675 
++02676 void dwc_otg_hcd_set_priv_data(dwc_otg_hcd_t * hcd, void *priv_data)
++02677 {
++02678         hcd->priv = priv_data;
++02679 }
++02680 
++02681 uint32_t dwc_otg_hcd_otg_port(dwc_otg_hcd_t * hcd)
++02682 {
++02683         return hcd->otg_port;
++02684 }
++02685 
++02686 uint32_t dwc_otg_hcd_is_b_host(dwc_otg_hcd_t * hcd)
++02687 {
++02688         uint32_t is_b_host;
++02689         if (hcd->core_if->op_state == B_HOST) {
++02690                 is_b_host = 1;
++02691         } else {
++02692                 is_b_host = 0;
++02693         }
++02694 
++02695         return is_b_host;
++02696 }
++02697 
++02698 dwc_otg_hcd_urb_t *dwc_otg_hcd_urb_alloc(dwc_otg_hcd_t * hcd,
++02699                                          int iso_desc_count, int atomic_alloc)
++02700 {
++02701         dwc_otg_hcd_urb_t *dwc_otg_urb;
++02702         uint32_t size;
++02703 
++02704         size =
++02705             sizeof(*dwc_otg_urb) +
++02706             iso_desc_count * sizeof(struct dwc_otg_hcd_iso_packet_desc);
++02707         if (atomic_alloc) {
++02708                 dwc_otg_urb = dwc_alloc_atomic(size);
++02709         } else {
++02710                 dwc_otg_urb = dwc_alloc(size);
++02711         }
++02712         dwc_otg_urb->packet_count = iso_desc_count;
++02713 
++02714         return dwc_otg_urb;
++02715 }
++02716 
++02717 void dwc_otg_hcd_urb_set_pipeinfo(dwc_otg_hcd_urb_t * dwc_otg_urb,
++02718                                   uint8_t dev_addr, uint8_t ep_num,
++02719                                   uint8_t ep_type, uint8_t ep_dir, uint16_t mps)
++02720 {
++02721         dwc_otg_hcd_fill_pipe(&dwc_otg_urb->pipe_info, dev_addr, ep_num,
++02722                               ep_type, ep_dir, mps);
++02723 #if 0
++02724         DWC_PRINTF
++02725             ("addr = %d, ep_num = %d, ep_dir = 0x%x, ep_type = 0x%x, mps = %d\n",
++02726              dev_addr, ep_num, ep_dir, ep_type, mps);
++02727 #endif
++02728 }
++02729 
++02730 void dwc_otg_hcd_urb_set_params(dwc_otg_hcd_urb_t * dwc_otg_urb,
++02731                                 void *urb_handle, void *buf, dwc_dma_t dma,
++02732                                 uint32_t buflen, void *setup_packet,
++02733                                 dwc_dma_t setup_dma, uint32_t flags,
++02734                                 uint16_t interval)
++02735 {
++02736         dwc_otg_urb->priv = urb_handle;
++02737         dwc_otg_urb->buf = buf;
++02738         dwc_otg_urb->dma = dma;
++02739         dwc_otg_urb->length = buflen;
++02740         dwc_otg_urb->setup_packet = setup_packet;
++02741         dwc_otg_urb->setup_dma = setup_dma;
++02742         dwc_otg_urb->flags = flags;
++02743         dwc_otg_urb->interval = interval;
++02744         dwc_otg_urb->status = -DWC_E_IN_PROGRESS;
++02745 }
++02746 
++02747 uint32_t dwc_otg_hcd_urb_get_status(dwc_otg_hcd_urb_t * dwc_otg_urb)
++02748 {
++02749         return dwc_otg_urb->status;
++02750 }
++02751 
++02752 uint32_t dwc_otg_hcd_urb_get_actual_length(dwc_otg_hcd_urb_t * dwc_otg_urb)
++02753 {
++02754         return dwc_otg_urb->actual_length;
++02755 }
++02756 
++02757 uint32_t dwc_otg_hcd_urb_get_error_count(dwc_otg_hcd_urb_t * dwc_otg_urb)
++02758 {
++02759         return dwc_otg_urb->error_count;
++02760 }
++02761 
++02762 void dwc_otg_hcd_urb_set_iso_desc_params(dwc_otg_hcd_urb_t * dwc_otg_urb,
++02763                                          int desc_num, uint32_t offset,
++02764                                          uint32_t length)
++02765 {
++02766         dwc_otg_urb->iso_descs[desc_num].offset = offset;
++02767         dwc_otg_urb->iso_descs[desc_num].length = length;
++02768 }
++02769 
++02770 uint32_t dwc_otg_hcd_urb_get_iso_desc_status(dwc_otg_hcd_urb_t * dwc_otg_urb,
++02771                                              int desc_num)
++02772 {
++02773         return dwc_otg_urb->iso_descs[desc_num].status;
++02774 }
++02775 
++02776 uint32_t dwc_otg_hcd_urb_get_iso_desc_actual_length(dwc_otg_hcd_urb_t *
++02777                                                     dwc_otg_urb, int desc_num)
++02778 {
++02779         return dwc_otg_urb->iso_descs[desc_num].actual_length;
++02780 }
++02781 
++02782 int dwc_otg_hcd_is_bandwidth_allocated(dwc_otg_hcd_t * hcd, void *ep_handle)
++02783 {
++02784         int allocated = 0;
++02785         dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle;
++02786 
++02787         if (qh) {
++02788                 if (!DWC_LIST_EMPTY(&qh->qh_list_entry)) {
++02789                         allocated = 1;
++02790                 }
++02791         }
++02792         return allocated;
++02793 }
++02794 
++02795 int dwc_otg_hcd_is_bandwidth_freed(dwc_otg_hcd_t * hcd, void *ep_handle)
++02796 {
++02797         dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle;
++02798         int freed = 0;
++02799         DWC_ASSERT(qh, "qh is not allocated\n");
++02800 
++02801         if (DWC_LIST_EMPTY(&qh->qh_list_entry)) {
++02802                 freed = 1;
++02803         }
++02804 
++02805         return freed;
++02806 }
++02807 
++02808 uint8_t dwc_otg_hcd_get_ep_bandwidth(dwc_otg_hcd_t * hcd, void *ep_handle)
++02809 {
++02810         dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle;
++02811         DWC_ASSERT(qh, "qh is not allocated\n");
++02812         return qh->usecs;
++02813 }
++02814 
++02815 void dwc_otg_hcd_dump_state(dwc_otg_hcd_t * hcd)
++02816 {
++02817 #ifdef DEBUG
++02818         int num_channels;
++02819         int i;
++02820         gnptxsts_data_t np_tx_status;
++02821         hptxsts_data_t p_tx_status;
++02822 
++02823         num_channels = hcd->core_if->core_params->host_channels;
++02824         DWC_PRINTF("\n");
++02825         DWC_PRINTF
++02826             ("************************************************************\n");
++02827         DWC_PRINTF("HCD State:\n");
++02828         DWC_PRINTF("  Num channels: %d\n", num_channels);
++02829         for (i = 0; i < num_channels; i++) {
++02830                 dwc_hc_t *hc = hcd->hc_ptr_array[i];
++02831                 DWC_PRINTF("  Channel %d:\n", i);
++02832                 DWC_PRINTF("    dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
++02833                            hc->dev_addr, hc->ep_num, hc->ep_is_in);
++02834                 DWC_PRINTF("    speed: %d\n", hc->speed);
++02835                 DWC_PRINTF("    ep_type: %d\n", hc->ep_type);
++02836                 DWC_PRINTF("    max_packet: %d\n", hc->max_packet);
++02837                 DWC_PRINTF("    data_pid_start: %d\n", hc->data_pid_start);
++02838                 DWC_PRINTF("    multi_count: %d\n", hc->multi_count);
++02839                 DWC_PRINTF("    xfer_started: %d\n", hc->xfer_started);
++02840                 DWC_PRINTF("    xfer_buff: %p\n", hc->xfer_buff);
++02841                 DWC_PRINTF("    xfer_len: %d\n", hc->xfer_len);
++02842                 DWC_PRINTF("    xfer_count: %d\n", hc->xfer_count);
++02843                 DWC_PRINTF("    halt_on_queue: %d\n", hc->halt_on_queue);
++02844                 DWC_PRINTF("    halt_pending: %d\n", hc->halt_pending);
++02845                 DWC_PRINTF("    halt_status: %d\n", hc->halt_status);
++02846                 DWC_PRINTF("    do_split: %d\n", hc->do_split);
++02847                 DWC_PRINTF("    complete_split: %d\n", hc->complete_split);
++02848                 DWC_PRINTF("    hub_addr: %d\n", hc->hub_addr);
++02849                 DWC_PRINTF("    port_addr: %d\n", hc->port_addr);
++02850                 DWC_PRINTF("    xact_pos: %d\n", hc->xact_pos);
++02851                 DWC_PRINTF("    requests: %d\n", hc->requests);
++02852                 DWC_PRINTF("    qh: %p\n", hc->qh);
++02853                 if (hc->xfer_started) {
++02854                         hfnum_data_t hfnum;
++02855                         hcchar_data_t hcchar;
++02856                         hctsiz_data_t hctsiz;
++02857                         hcint_data_t hcint;
++02858                         hcintmsk_data_t hcintmsk;
++02859                         hfnum.d32 =
++02860                             dwc_read_reg32(&hcd->core_if->host_if->
++02861                                            host_global_regs->hfnum);
++02862                         hcchar.d32 =
++02863                             dwc_read_reg32(&hcd->core_if->host_if->hc_regs[i]->
++02864                                            hcchar);
++02865                         hctsiz.d32 =
++02866                             dwc_read_reg32(&hcd->core_if->host_if->hc_regs[i]->
++02867                                            hctsiz);
++02868                         hcint.d32 =
++02869                             dwc_read_reg32(&hcd->core_if->host_if->hc_regs[i]->
++02870                                            hcint);
++02871                         hcintmsk.d32 =
++02872                             dwc_read_reg32(&hcd->core_if->host_if->hc_regs[i]->
++02873                                            hcintmsk);
++02874                         DWC_PRINTF("    hfnum: 0x%08x\n", hfnum.d32);
++02875                         DWC_PRINTF("    hcchar: 0x%08x\n", hcchar.d32);
++02876                         DWC_PRINTF("    hctsiz: 0x%08x\n", hctsiz.d32);
++02877                         DWC_PRINTF("    hcint: 0x%08x\n", hcint.d32);
++02878                         DWC_PRINTF("    hcintmsk: 0x%08x\n", hcintmsk.d32);
++02879                 }
++02880                 if (hc->xfer_started && hc->qh) {
++02881                         dwc_otg_qtd_t *qtd;
++02882                         dwc_otg_hcd_urb_t *urb;
++02883                         
++02884                         DWC_CIRCLEQ_FOREACH(qtd, &hc->qh->qtd_list, qtd_list_entry) {
++02885                                 if(!qtd->in_process)
++02886                                         break;
++02887                                 
++02888                                 urb = qtd->urb;
++02889                         DWC_PRINTF("    URB Info:\n");
++02890                         DWC_PRINTF("      qtd: %p, urb: %p\n", qtd, urb);
++02891                         if (urb) {
++02892                                 DWC_PRINTF("      Dev: %d, EP: %d %s\n",
++02893                                            dwc_otg_hcd_get_dev_addr(&urb->
++02894                                                                     pipe_info),
++02895                                            dwc_otg_hcd_get_ep_num(&urb->
++02896                                                                   pipe_info),
++02897                                            dwc_otg_hcd_is_pipe_in(&urb->
++02898                                                                   pipe_info) ?
++02899                                            "IN" : "OUT");
++02900                                 DWC_PRINTF("      Max packet size: %d\n",
++02901                                            dwc_otg_hcd_get_mps(&urb->
++02902                                                                pipe_info));
++02903                                 DWC_PRINTF("      transfer_buffer: %p\n",
++02904                                            urb->buf);
++02905                                 DWC_PRINTF("      transfer_dma: %p\n",
++02906                                            (void *)urb->dma);
++02907                                 DWC_PRINTF("      transfer_buffer_length: %d\n",
++02908                                            urb->length);
++02909                                 DWC_PRINTF("      actual_length: %d\n",
++02910                                            urb->actual_length);
++02911                         }
++02912                 }
++02913         }
++02914         }
++02915         DWC_PRINTF("  non_periodic_channels: %d\n", hcd->non_periodic_channels);
++02916         DWC_PRINTF("  periodic_channels: %d\n", hcd->periodic_channels);
++02917         DWC_PRINTF("  periodic_usecs: %d\n", hcd->periodic_usecs);
++02918         np_tx_status.d32 =
++02919             dwc_read_reg32(&hcd->core_if->core_global_regs->gnptxsts);
++02920         DWC_PRINTF("  NP Tx Req Queue Space Avail: %d\n",
++02921                    np_tx_status.b.nptxqspcavail);
++02922         DWC_PRINTF("  NP Tx FIFO Space Avail: %d\n",
++02923                    np_tx_status.b.nptxfspcavail);
++02924         p_tx_status.d32 =
++02925             dwc_read_reg32(&hcd->core_if->host_if->host_global_regs->hptxsts);
++02926         DWC_PRINTF("  P Tx Req Queue Space Avail: %d\n",
++02927                    p_tx_status.b.ptxqspcavail);
++02928         DWC_PRINTF("  P Tx FIFO Space Avail: %d\n", p_tx_status.b.ptxfspcavail);
++02929         dwc_otg_hcd_dump_frrem(hcd);
++02930         dwc_otg_dump_global_registers(hcd->core_if);
++02931         dwc_otg_dump_host_registers(hcd->core_if);
++02932         DWC_PRINTF
++02933             ("************************************************************\n");
++02934         DWC_PRINTF("\n");
++02935 #endif
++02936 }
++02937 
++02938 #ifdef DEBUG
++02939 void dwc_print_setup_data(uint8_t * setup)
++02940 {
++02941         int i;
++02942         if (CHK_DEBUG_LEVEL(DBG_HCD)) {
++02943                 DWC_PRINTF("Setup Data = MSB ");
++02944                 for (i = 7; i >= 0; i--)
++02945                         DWC_PRINTF("%02x ", setup[i]);
++02946                 DWC_PRINTF("\n");
++02947                 DWC_PRINTF("  bmRequestType Tranfer = %s\n",
++02948                            (setup[0] & 0x80) ? "Device-to-Host" :
++02949                            "Host-to-Device");
++02950                 DWC_PRINTF("  bmRequestType Type = ");
++02951                 switch ((setup[0] & 0x60) >> 5) {
++02952                 case 0:
++02953                         DWC_PRINTF("Standard\n");
++02954                         break;
++02955                 case 1:
++02956                         DWC_PRINTF("Class\n");
++02957                         break;
++02958                 case 2:
++02959                         DWC_PRINTF("Vendor\n");
++02960                         break;
++02961                 case 3:
++02962                         DWC_PRINTF("Reserved\n");
++02963                         break;
++02964                 }
++02965                 DWC_PRINTF("  bmRequestType Recipient = ");
++02966                 switch (setup[0] & 0x1f) {
++02967                 case 0:
++02968                         DWC_PRINTF("Device\n");
++02969                         break;
++02970                 case 1:
++02971                         DWC_PRINTF("Interface\n");
++02972                         break;
++02973                 case 2:
++02974                         DWC_PRINTF("Endpoint\n");
++02975                         break;
++02976                 case 3:
++02977                         DWC_PRINTF("Other\n");
++02978                         break;
++02979                 default:
++02980                         DWC_PRINTF("Reserved\n");
++02981                         break;
++02982                 }
++02983                 DWC_PRINTF("  bRequest = 0x%0x\n", setup[1]);
++02984                 DWC_PRINTF("  wValue = 0x%0x\n", *((uint16_t *) & setup[2]));
++02985                 DWC_PRINTF("  wIndex = 0x%0x\n", *((uint16_t *) & setup[4]));
++02986                 DWC_PRINTF("  wLength = 0x%0x\n\n", *((uint16_t *) & setup[6]));
++02987         }
++02988 }
++02989 #endif
++02990 
++02991 void dwc_otg_hcd_dump_frrem(dwc_otg_hcd_t * hcd)
++02992 {
++02993 #if 0
++02994         DWC_PRINTF("Frame remaining at SOF:\n");
++02995         DWC_PRINTF("  samples %u, accum %llu, avg %llu\n",
++02996                    hcd->frrem_samples, hcd->frrem_accum,
++02997                    (hcd->frrem_samples > 0) ?
++02998                    hcd->frrem_accum / hcd->frrem_samples : 0);
++02999 
++03000         DWC_PRINTF("\n");
++03001         DWC_PRINTF("Frame remaining at start_transfer (uframe 7):\n");
++03002         DWC_PRINTF("  samples %u, accum %llu, avg %llu\n",
++03003                    hcd->core_if->hfnum_7_samples,
++03004                    hcd->core_if->hfnum_7_frrem_accum,
++03005                    (hcd->core_if->hfnum_7_samples >
++03006                     0) ? hcd->core_if->hfnum_7_frrem_accum /
++03007                    hcd->core_if->hfnum_7_samples : 0);
++03008         DWC_PRINTF("Frame remaining at start_transfer (uframe 0):\n");
++03009         DWC_PRINTF("  samples %u, accum %llu, avg %llu\n",
++03010                    hcd->core_if->hfnum_0_samples,
++03011                    hcd->core_if->hfnum_0_frrem_accum,
++03012                    (hcd->core_if->hfnum_0_samples >
++03013                     0) ? hcd->core_if->hfnum_0_frrem_accum /
++03014                    hcd->core_if->hfnum_0_samples : 0);
++03015         DWC_PRINTF("Frame remaining at start_transfer (uframe 1-6):\n");
++03016         DWC_PRINTF("  samples %u, accum %llu, avg %llu\n",
++03017                    hcd->core_if->hfnum_other_samples,
++03018                    hcd->core_if->hfnum_other_frrem_accum,
++03019                    (hcd->core_if->hfnum_other_samples >
++03020                     0) ? hcd->core_if->hfnum_other_frrem_accum /
++03021                    hcd->core_if->hfnum_other_samples : 0);
++03022 
++03023         DWC_PRINTF("\n");
++03024         DWC_PRINTF("Frame remaining at sample point A (uframe 7):\n");
++03025         DWC_PRINTF("  samples %u, accum %llu, avg %llu\n",
++03026                    hcd->hfnum_7_samples_a, hcd->hfnum_7_frrem_accum_a,
++03027                    (hcd->hfnum_7_samples_a > 0) ?
++03028                    hcd->hfnum_7_frrem_accum_a / hcd->hfnum_7_samples_a : 0);
++03029         DWC_PRINTF("Frame remaining at sample point A (uframe 0):\n");
++03030         DWC_PRINTF("  samples %u, accum %llu, avg %llu\n",
++03031                    hcd->hfnum_0_samples_a, hcd->hfnum_0_frrem_accum_a,
++03032                    (hcd->hfnum_0_samples_a > 0) ?
++03033                    hcd->hfnum_0_frrem_accum_a / hcd->hfnum_0_samples_a : 0);
++03034         DWC_PRINTF("Frame remaining at sample point A (uframe 1-6):\n");
++03035         DWC_PRINTF("  samples %u, accum %llu, avg %llu\n",
++03036                    hcd->hfnum_other_samples_a, hcd->hfnum_other_frrem_accum_a,
++03037                    (hcd->hfnum_other_samples_a > 0) ?
++03038                    hcd->hfnum_other_frrem_accum_a /
++03039                    hcd->hfnum_other_samples_a : 0);
++03040 
++03041         DWC_PRINTF("\n");
++03042         DWC_PRINTF("Frame remaining at sample point B (uframe 7):\n");
++03043         DWC_PRINTF("  samples %u, accum %llu, avg %llu\n",
++03044                    hcd->hfnum_7_samples_b, hcd->hfnum_7_frrem_accum_b,
++03045                    (hcd->hfnum_7_samples_b > 0) ?
++03046                    hcd->hfnum_7_frrem_accum_b / hcd->hfnum_7_samples_b : 0);
++03047         DWC_PRINTF("Frame remaining at sample point B (uframe 0):\n");
++03048         DWC_PRINTF("  samples %u, accum %llu, avg %llu\n",
++03049                    hcd->hfnum_0_samples_b, hcd->hfnum_0_frrem_accum_b,
++03050                    (hcd->hfnum_0_samples_b > 0) ?
++03051                    hcd->hfnum_0_frrem_accum_b / hcd->hfnum_0_samples_b : 0);
++03052         DWC_PRINTF("Frame remaining at sample point B (uframe 1-6):\n");
++03053         DWC_PRINTF("  samples %u, accum %llu, avg %llu\n",
++03054                    hcd->hfnum_other_samples_b, hcd->hfnum_other_frrem_accum_b,
++03055                    (hcd->hfnum_other_samples_b > 0) ?
++03056                    hcd->hfnum_other_frrem_accum_b /
++03057                    hcd->hfnum_other_samples_b : 0);
++03058 #endif
++03059 }
++03060 
++03061 #endif                          /* DWC_DEVICE_ONLY */
++
Generated on Tue May 5 02:22:48 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__hcd_8c.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__hcd_8c.html 2013-07-26 19:31:21.000000000 +0000 +@@ -0,0 +1,1837 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_hcd.c File Reference ++ ++ ++ ++ ++
++
++
++
++

dwc_otg_hcd.c File Reference

This file implements HCD Core. More... ++

++#include "dwc_otg_hcd.h"
++#include "dwc_otg_regs.h"
++ ++

++Go to the source code of this file. ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++

Functions

++dwc_otg_hcd_t * dwc_otg_hcd_alloc_hcd (void)
 This function allocates dwc_otg_hcd structure and returns pointer on it.
void dwc_otg_hcd_connect_timeout (void *ptr)
 Connection timeout function.
static void hcd_start_func (void *_vp)
 Work queue function for starting the HCD when A-Cable is connected.
++static void del_xfer_timers (dwc_otg_hcd_t *hcd)
++static void del_timers (dwc_otg_hcd_t *hcd)
static void kill_urbs_in_qh_list (dwc_otg_hcd_t *hcd, dwc_list_link_t *qh_list)
 Processes all the URBs in a single list of QHs.
static void kill_all_urbs (dwc_otg_hcd_t *hcd)
 Responds with an error status of ETIMEDOUT to all URBs in the non-periodic and periodic schedules.
static void dwc_otg_hcd_start_connect_timer (dwc_otg_hcd_t *hcd)
 Start the connection timer.
static int32_t dwc_otg_hcd_session_start_cb (void *p)
 HCD Callback function for disconnect of the HCD.
static int32_t dwc_otg_hcd_start_cb (void *p)
 HCD Callback function for starting the HCD when A-Cable is connected.
static int32_t dwc_otg_hcd_disconnect_cb (void *p)
 HCD Callback function for disconnect of the HCD.
static int32_t dwc_otg_hcd_stop_cb (void *p)
 HCD Callback function for stopping the HCD.
static int dwc_otg_hcd_rem_wakeup_cb (void *p)
 HCD Callback function for Remote Wakeup.
void dwc_otg_hcd_stop (dwc_otg_hcd_t *hcd)
 Halts the DWC_otg host mode operations in a clean manner.
int dwc_otg_hcd_urb_enqueue (dwc_otg_hcd_t *hcd, dwc_otg_hcd_urb_t *dwc_otg_urb, void **ep_handle)
 Queue URB.
int dwc_otg_hcd_urb_dequeue (dwc_otg_hcd_t *hcd, dwc_otg_hcd_urb_t *dwc_otg_urb)
 De-queue the specified URB.
int dwc_otg_hcd_endpoint_disable (dwc_otg_hcd_t *hcd, void *ep_handle, int retry)
 Frees resources in the DWC_otg controller related to a given endpoint.
++static void reset_tasklet_func (void *data)
 Reset tasklet function.
++static void qh_list_free (dwc_otg_hcd_t *hcd, dwc_list_link_t *qh_list)
++static void dwc_otg_hcd_free (dwc_otg_hcd_t *dwc_otg_hcd)
 Frees secondary storage associated with the dwc_otg_hcd structure contained in the struct usb_hcd field.
int dwc_otg_hcd_init (dwc_otg_hcd_t *hcd, dwc_otg_core_if_t *core_if)
 This function should be called to initiate HCD Core.
void dwc_otg_hcd_remove (dwc_otg_hcd_t *hcd)
 Frees HCD.
++static void dwc_otg_hcd_reinit (dwc_otg_hcd_t *hcd)
 Initializes dynamic portions of the DWC_otg HCD state.
static void assign_and_init_hc (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
 Assigns transactions from a QTD to a free host channel and initializes the host channel to perform the transactions.
dwc_otg_transaction_type_e dwc_otg_hcd_select_transactions (dwc_otg_hcd_t *hcd)
 This function selects transactions from the HCD transfer schedule and assigns them to available host channels.
static int queue_transaction (dwc_otg_hcd_t *hcd, dwc_hc_t *hc, uint16_t fifo_dwords_avail)
 Attempts to queue a single transaction request for a host channel associated with either a periodic or non-periodic transfer.
static void process_periodic_channels (dwc_otg_hcd_t *hcd)
 Processes periodic channels for the next frame and queues transactions for these channels to the DWC_otg controller.
static void process_non_periodic_channels (dwc_otg_hcd_t *hcd)
 Processes active non-periodic channels and queues transactions for these channels to the DWC_otg controller.
void dwc_otg_hcd_queue_transactions (dwc_otg_hcd_t *hcd, dwc_otg_transaction_type_e tr_type)
 This function processes the currently active host channels and queues transactions for these channels to the DWC_otg controller.
int dwc_otg_hcd_hub_control (dwc_otg_hcd_t *dwc_otg_hcd, uint16_t typeReq, uint16_t wValue, uint16_t wIndex, uint8_t *buf, uint16_t wLength)
 Handles hub class-specific requests.
int dwc_otg_hcd_is_status_changed (dwc_otg_hcd_t *hcd, int port)
 Returns 1 if status of specified port is changed and 0 otherwise.
int dwc_otg_hcd_get_frame_number (dwc_otg_hcd_t *dwc_otg_hcd)
 Returns current frame number.
int dwc_otg_hcd_start (dwc_otg_hcd_t *hcd, struct dwc_otg_hcd_function_ops *fops)
 This function initializes the HCD Core.
void * dwc_otg_hcd_get_priv_data (dwc_otg_hcd_t *hcd)
 Returns private data set by dwc_otg_hcd_set_priv_data function.
void dwc_otg_hcd_set_priv_data (dwc_otg_hcd_t *hcd, void *priv_data)
 Set private data.
uint32_t dwc_otg_hcd_otg_port (dwc_otg_hcd_t *hcd)
 Returns otg port number.
uint32_t dwc_otg_hcd_is_b_host (dwc_otg_hcd_t *hcd)
 Returns 1 if currently core is acting as B host, and 0 otherwise.
dwc_otg_hcd_urb_t * dwc_otg_hcd_urb_alloc (dwc_otg_hcd_t *hcd, int iso_desc_count, int atomic_alloc)
 Allocates memory for dwc_otg_hcd_urb structure.
void dwc_otg_hcd_urb_set_pipeinfo (dwc_otg_hcd_urb_t *dwc_otg_urb, uint8_t dev_addr, uint8_t ep_num, uint8_t ep_type, uint8_t ep_dir, uint16_t mps)
 Set pipe information in URB.
void dwc_otg_hcd_urb_set_params (dwc_otg_hcd_urb_t *dwc_otg_urb, void *urb_handle, void *buf, dwc_dma_t dma, uint32_t buflen, void *setup_packet, dwc_dma_t setup_dma, uint32_t flags, uint16_t interval)
 Sets dwc_otg_hcd_urb parameters.
uint32_t dwc_otg_hcd_urb_get_status (dwc_otg_hcd_urb_t *dwc_otg_urb)
 Gets status from dwc_otg_hcd_urb.
uint32_t dwc_otg_hcd_urb_get_actual_length (dwc_otg_hcd_urb_t *dwc_otg_urb)
 Gets actual length from dwc_otg_hcd_urb.
uint32_t dwc_otg_hcd_urb_get_error_count (dwc_otg_hcd_urb_t *dwc_otg_urb)
 Gets error count from dwc_otg_hcd_urb.
void dwc_otg_hcd_urb_set_iso_desc_params (dwc_otg_hcd_urb_t *dwc_otg_urb, int desc_num, uint32_t offset, uint32_t length)
 Set ISOC descriptor offset and length.
uint32_t dwc_otg_hcd_urb_get_iso_desc_status (dwc_otg_hcd_urb_t *dwc_otg_urb, int desc_num)
 Get status of ISOC descriptor, specified by desc_num.
uint32_t dwc_otg_hcd_urb_get_iso_desc_actual_length (dwc_otg_hcd_urb_t *dwc_otg_urb, int desc_num)
 Get actual length of ISOC descriptor, specified by desc_num.
int dwc_otg_hcd_is_bandwidth_allocated (dwc_otg_hcd_t *hcd, void *ep_handle)
 Call this function to check if bandwidth was allocated for specified endpoint.
int dwc_otg_hcd_is_bandwidth_freed (dwc_otg_hcd_t *hcd, void *ep_handle)
 Call this function to check if bandwidth was freed for specified endpoint.
uint8_t dwc_otg_hcd_get_ep_bandwidth (dwc_otg_hcd_t *hcd, void *ep_handle)
 Returns bandwidth allocated for specified endpoint in microseconds.
void dwc_otg_hcd_dump_state (dwc_otg_hcd_t *hcd)
 Dumps hcd state.
void dwc_otg_hcd_dump_frrem (dwc_otg_hcd_t *hcd)
 Dump the average frame remaining at SOF.

Variables

static dwc_otg_cil_callbacks_t hcd_cil_callbacks
 HCD Callback structure for handling mode switching.
++

Detailed Description

++This file implements HCD Core. ++

++All code in this file is portable and don't use any OS specific functions. Interface provided by HCD Core is defined in <hcd_if.h> header file. ++

++Definition in file dwc_otg_hcd.c.

Function Documentation

++ ++
++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_otg_hcd_connect_timeout (void *  ptr  ) 
++
++
++ ++

++Connection timeout function. ++

++An OTG host is required to display a message if the device does not connect within 10 seconds. ++

++Definition at line 54 of file dwc_otg_hcd.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
static void hcd_start_func (void *  _vp  )  [static]
++
++
++ ++

++Work queue function for starting the HCD when A-Cable is connected. ++

++The hcd_start() must be called in a process context. ++

++Definition at line 123 of file dwc_otg_hcd.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
static void kill_urbs_in_qh_list (dwc_otg_hcd_t *  hcd,
dwc_list_link_t *  qh_list 
) [static]
++
++
++ ++

++Processes all the URBs in a single list of QHs. ++

++Completes them with -ETIMEDOUT and frees the QTD. ++

++Definition at line 154 of file dwc_otg_hcd.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
static void kill_all_urbs (dwc_otg_hcd_t *  hcd  )  [static]
++
++
++ ++

++Responds with an error status of ETIMEDOUT to all URBs in the non-periodic and periodic schedules. ++

++The QTD associated with each URB is removed from the schedule and freed. This function may be called when a disconnect is detected or when the HCD is being stopped. ++

++Definition at line 182 of file dwc_otg_hcd.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
static void dwc_otg_hcd_start_connect_timer (dwc_otg_hcd_t *  hcd  )  [static]
++
++
++ ++

++Start the connection timer. ++

++An OTG host is required to display a message if the device does not connect within 10 seconds. The timer is deleted if a port connect interrupt occurs before the timer expires. ++

++Definition at line 198 of file dwc_otg_hcd.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
static int32_t dwc_otg_hcd_session_start_cb (void *  p  )  [static]
++
++
++ ++

++HCD Callback function for disconnect of the HCD. ++

++

Parameters:
++ ++ ++
p void pointer to the struct usb_hcd
++
++ ++

++Definition at line 208 of file dwc_otg_hcd.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
static int32_t dwc_otg_hcd_start_cb (void *  p  )  [static]
++
++
++ ++

++HCD Callback function for starting the HCD when A-Cable is connected. ++

++

Parameters:
++ ++ ++
p void pointer to the struct usb_hcd
++
++ ++

++Definition at line 223 of file dwc_otg_hcd.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
static int32_t dwc_otg_hcd_disconnect_cb (void *  p  )  [static]
++
++
++ ++

++HCD Callback function for disconnect of the HCD. ++

++

Parameters:
++ ++ ++
p void pointer to the struct usb_hcd
++
++ ++

++Definition at line 253 of file dwc_otg_hcd.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
static int32_t dwc_otg_hcd_stop_cb (void *  p  )  [static]
++
++
++ ++

++HCD Callback function for stopping the HCD. ++

++

Parameters:
++ ++ ++
p void pointer to the struct usb_hcd
++
++ ++

++Definition at line 373 of file dwc_otg_hcd.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
static int dwc_otg_hcd_rem_wakeup_cb (void *  p  )  [static]
++
++
++ ++

++HCD Callback function for Remote Wakeup. ++

++

Parameters:
++ ++ ++
p void pointer to the struct usb_hcd
++
++ ++

++Definition at line 403 of file dwc_otg_hcd.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_otg_hcd_stop (dwc_otg_hcd_t *  hcd  ) 
++
++
++ ++

++Halts the DWC_otg host mode operations in a clean manner. ++

++USB transfers are stopped. ++

++Definition at line 422 of file dwc_otg_hcd.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int dwc_otg_hcd_urb_enqueue (dwc_otg_hcd_t *  dwc_otg_hcd,
dwc_otg_hcd_urb_t *  dwc_otg_urb,
void **  ep_handle 
)
++
++
++ ++

++Queue URB. ++

++After transfer is completes, the complete callback will be called with the URB status

++

Parameters:
++ ++ ++ ++ ++
dwc_otg_hcd The HCD
dwc_otg_urb DWC_OTG URB
ep_handle Out parameter for returning endpoint handle
++
++Returns -DWC_E_NO_DEVICE if no device is connected. Returns -DWC_E_NO_MEMORY if there is no enough memory. Returns 0 on success. ++

++Definition at line 444 of file dwc_otg_hcd.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int dwc_otg_hcd_urb_dequeue (dwc_otg_hcd_t *  dwc_otg_hcd,
dwc_otg_hcd_urb_t *  dwc_otg_urb 
)
++
++
++ ++

++De-queue the specified URB. ++

++

Parameters:
++ ++ ++ ++
dwc_otg_hcd The HCD
dwc_otg_urb DWC_OTG URB
++
++ ++

++Definition at line 489 of file dwc_otg_hcd.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int dwc_otg_hcd_endpoint_disable (dwc_otg_hcd_t *  hcd,
void *  ep_handle,
int  retry 
)
++
++
++ ++

++Frees resources in the DWC_otg controller related to a given endpoint. ++

++Any URBs for the endpoint must already be dequeued.

++

Parameters:
++ ++ ++ ++ ++
hcd The HCD
ep_handle Endpoint handle, returned by dwc_otg_hcd_urb_enqueue function
retry Number of retries if there are queued transfers.
++
++Returns -DWC_E_INVALID if invalid arguments are passed. Returns 0 on success ++

++Definition at line 547 of file dwc_otg_hcd.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int dwc_otg_hcd_init (dwc_otg_hcd_t *  hcd,
dwc_otg_core_if_t *  core_if 
)
++
++
++ ++

++This function should be called to initiate HCD Core. ++

++

Parameters:
++ ++ ++ ++
hcd The HCD
core_if The DWC_OTG Core
++
++Returns -DWC_E_NO_MEMORY if no enough memory. Returns 0 on success ++

++Definition at line 693 of file dwc_otg_hcd.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_otg_hcd_remove (dwc_otg_hcd_t *  hcd  ) 
++
++
++ ++

++Frees HCD. ++

++

Parameters:
++ ++ ++
hcd The HCD
++
++ ++

++Definition at line 778 of file dwc_otg_hcd.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
static void assign_and_init_hc (dwc_otg_hcd_t *  hcd,
dwc_otg_qh_t *  qh 
) [static]
++
++
++ ++

++Assigns transactions from a QTD to a free host channel and initializes the host channel to perform the transactions. ++

++The host channel is removed from the free list.

++

Parameters:
++ ++ ++ ++
hcd The HCD state structure.
qh Transactions from the first QTD for this QH are selected and assigned to a free host channel.
++
++ ++

++Definition at line 832 of file dwc_otg_hcd.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
dwc_otg_transaction_type_e dwc_otg_hcd_select_transactions (dwc_otg_hcd_t *  hcd  ) 
++
++
++ ++

++This function selects transactions from the HCD transfer schedule and assigns them to available host channels. ++

++It is called from HCD interrupt handler functions.

++

Parameters:
++ ++ ++
hcd The HCD state structure.
++
++
Returns:
The types of new transactions that were assigned to host channels.
++ ++

++Definition at line 1055 of file dwc_otg_hcd.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
static int queue_transaction (dwc_otg_hcd_t *  hcd,
dwc_hc_t *  hc,
uint16_t  fifo_dwords_avail 
) [static]
++
++
++ ++

++Attempts to queue a single transaction request for a host channel associated with either a periodic or non-periodic transfer. ++

++This function assumes that there is space available in the appropriate request queue. For an OUT transfer or SETUP transaction in Slave mode, it checks whether space is available in the appropriate Tx FIFO.

++

Parameters:
++ ++ ++ ++ ++
hcd The HCD state structure.
hc Host channel descriptor associated with either a periodic or non-periodic transfer.
fifo_dwords_avail Number of DWORDs available in the periodic Tx FIFO for periodic transfers or the non-periodic Tx FIFO for non-periodic transfers.
++
++
Returns:
1 if a request is queued and more requests may be needed to complete the transfer, 0 if no more requests are required for this transfer, -1 if there is insufficient space in the Tx FIFO.
++ ++

++Definition at line 1139 of file dwc_otg_hcd.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
static void process_periodic_channels (dwc_otg_hcd_t *  hcd  )  [static]
++
++
++ ++

++Processes periodic channels for the next frame and queues transactions for these channels to the DWC_otg controller. ++

++After queueing transactions, the Periodic Tx FIFO Empty interrupt is enabled if there are more transactions to queue as Periodic Tx FIFO or request queue space becomes available. Otherwise, the Periodic Tx FIFO Empty interrupt is disabled. ++

++Definition at line 1199 of file dwc_otg_hcd.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
static void process_non_periodic_channels (dwc_otg_hcd_t *  hcd  )  [static]
++
++
++ ++

++Processes active non-periodic channels and queues transactions for these channels to the DWC_otg controller. ++

++After queueing transactions, the NP Tx FIFO Empty interrupt is enabled if there are more transactions to queue as NP Tx FIFO or request queue space becomes available. Otherwise, the NP Tx FIFO Empty interrupt is disabled. ++

++Definition at line 1316 of file dwc_otg_hcd.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_otg_hcd_queue_transactions (dwc_otg_hcd_t *  hcd,
dwc_otg_transaction_type_e  tr_type 
)
++
++
++ ++

++This function processes the currently active host channels and queues transactions for these channels to the DWC_otg controller. ++

++It is called from HCD interrupt handler functions.

++

Parameters:
++ ++ ++ ++
hcd The HCD state structure.
tr_type The type(s) of transactions to queue (non-periodic, periodic, or both).
++
++ ++

++Definition at line 1426 of file dwc_otg_hcd.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int dwc_otg_hcd_hub_control (dwc_otg_hcd_t *  dwc_otg_hcd,
uint16_t  typeReq,
uint16_t  wValue,
uint16_t  wIndex,
uint8_t *  buf,
uint16_t  wLength 
)
++
++
++ ++

++Handles hub class-specific requests. ++

++

Parameters:
++ ++ ++ ++ ++ ++ ++ ++
dwc_otg_hcd The HCD
typeReq Request Type
wValue wValue from control request
wIndex wIndex from control request
buf data buffer
wLength data buffer length
++
++Returns -DWC_E_INVALID if invalid argument is passed Returns 0 on success ++

++Definition at line 1905 of file dwc_otg_hcd.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int dwc_otg_hcd_is_status_changed (dwc_otg_hcd_t *  hcd,
int  port 
)
++
++
++ ++

++Returns 1 if status of specified port is changed and 0 otherwise. ++

++

Parameters:
++ ++ ++ ++
hcd The HCD
port Port number
++
++ ++

++Definition at line 2611 of file dwc_otg_hcd.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int dwc_otg_hcd_get_frame_number (dwc_otg_hcd_t *  hcd  ) 
++
++
++ ++

++Returns current frame number. ++

++

Parameters:
++ ++ ++
hcd The HCD
++
++ ++

++Definition at line 2643 of file dwc_otg_hcd.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int dwc_otg_hcd_start (dwc_otg_hcd_t *  hcd,
struct dwc_otg_hcd_function_ops *  fops 
)
++
++
++ ++

++This function initializes the HCD Core. ++

++

Parameters:
++ ++ ++ ++
hcd The HCD
fops The Function Driver Operations data structure containing pointers to all callbacks.
++
++Returns -DWC_E_NO_DEVICE if Core is currently is in device mode. Returns 0 on success ++

++Definition at line 2656 of file dwc_otg_hcd.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void* dwc_otg_hcd_get_priv_data (dwc_otg_hcd_t *  hcd  ) 
++
++
++ ++

++Returns private data set by dwc_otg_hcd_set_priv_data function. ++

++

Parameters:
++ ++ ++
hcd The HCD
++
++ ++

++Definition at line 2671 of file dwc_otg_hcd.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_otg_hcd_set_priv_data (dwc_otg_hcd_t *  hcd,
void *  priv_data 
)
++
++
++ ++

++Set private data. ++

++

Parameters:
++ ++ ++ ++
hcd The HCD
priv_data pointer to be stored in private data
++
++ ++

++Definition at line 2676 of file dwc_otg_hcd.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
uint32_t dwc_otg_hcd_otg_port (dwc_otg_hcd_t *  hcd  ) 
++
++
++ ++

++Returns otg port number. ++

++

Parameters:
++ ++ ++
hcd The HCD
++
++ ++

++Definition at line 2681 of file dwc_otg_hcd.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
uint32_t dwc_otg_hcd_is_b_host (dwc_otg_hcd_t *  hcd  ) 
++
++
++ ++

++Returns 1 if currently core is acting as B host, and 0 otherwise. ++

++

Parameters:
++ ++ ++
hcd The HCD
++
++ ++

++Definition at line 2686 of file dwc_otg_hcd.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
dwc_otg_hcd_urb_t* dwc_otg_hcd_urb_alloc (dwc_otg_hcd_t *  hcd,
int  iso_desc_count,
int  atomic_alloc 
)
++
++
++ ++

++Allocates memory for dwc_otg_hcd_urb structure. ++

++Allocated memory should be freed by call dwc_free function.

++

Parameters:
++ ++ ++ ++ ++
hcd The HCD
iso_desc_count Count of ISOC descriptors
atomic_alloc Specefies whether to perform atomic allocation.
++
++ ++

++Definition at line 2698 of file dwc_otg_hcd.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_otg_hcd_urb_set_pipeinfo (dwc_otg_hcd_urb_t *  hcd_urb,
uint8_t  devaddr,
uint8_t  ep_num,
uint8_t  ep_type,
uint8_t  ep_dir,
uint16_t  mps 
)
++
++
++ ++

++Set pipe information in URB. ++

++

Parameters:
++ ++ ++ ++ ++ ++ ++ ++
hcd_urb DWC_OTG URB
devaddr Device Address
ep_num Endpoint Number
ep_type Endpoint Type
ep_dir Endpoint Direction
mps Max Packet Size
++
++ ++

++Definition at line 2717 of file dwc_otg_hcd.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_otg_hcd_urb_set_params (dwc_otg_hcd_urb_t *  urb,
void *  urb_handle,
void *  buf,
dwc_dma_t  dma,
uint32_t  buflen,
void *  sp,
dwc_dma_t  sp_dma,
uint32_t  flags,
uint16_t  interval 
)
++
++
++ ++

++Sets dwc_otg_hcd_urb parameters. ++

++

Parameters:
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
urb DWC_OTG URB allocated by dwc_otg_hcd_urb_alloc function.
urb_handle Unique handle for request, this will be passed back to function driver in completion callback.
buf The buffer for the data
dma The DMA buffer for the data
buflen Transfer length
sp Buffer for setup data
sp_dma DMA address of setup data buffer
flags Transfer flags
interval Polling interval for interrupt or isochronous transfers.
++
++ ++

++Definition at line 2730 of file dwc_otg_hcd.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
uint32_t dwc_otg_hcd_urb_get_status (dwc_otg_hcd_urb_t *  dwc_otg_urb  ) 
++
++
++ ++

++Gets status from dwc_otg_hcd_urb. ++

++

Parameters:
++ ++ ++
dwc_otg_urb DWC_OTG URB
++
++ ++

++Definition at line 2747 of file dwc_otg_hcd.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
uint32_t dwc_otg_hcd_urb_get_actual_length (dwc_otg_hcd_urb_t *  dwc_otg_urb  ) 
++
++
++ ++

++Gets actual length from dwc_otg_hcd_urb. ++

++

Parameters:
++ ++ ++
dwc_otg_urb DWC_OTG URB
++
++ ++

++Definition at line 2752 of file dwc_otg_hcd.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
uint32_t dwc_otg_hcd_urb_get_error_count (dwc_otg_hcd_urb_t *  dwc_otg_urb  ) 
++
++
++ ++

++Gets error count from dwc_otg_hcd_urb. ++

++Only for ISOC URBs

++

Parameters:
++ ++ ++
dwc_otg_urb DWC_OTG URB
++
++ ++

++Definition at line 2757 of file dwc_otg_hcd.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_otg_hcd_urb_set_iso_desc_params (dwc_otg_hcd_urb_t *  dwc_otg_urb,
int  desc_num,
uint32_t  offset,
uint32_t  length 
)
++
++
++ ++

++Set ISOC descriptor offset and length. ++

++

Parameters:
++ ++ ++ ++ ++ ++
dwc_otg_urb DWC_OTG URB
desc_num ISOC descriptor number
offset Offset from beginig of buffer.
length Transaction length
++
++ ++

++Definition at line 2762 of file dwc_otg_hcd.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
uint32_t dwc_otg_hcd_urb_get_iso_desc_status (dwc_otg_hcd_urb_t *  dwc_otg_urb,
int  desc_num 
)
++
++
++ ++

++Get status of ISOC descriptor, specified by desc_num. ++

++

Parameters:
++ ++ ++ ++
dwc_otg_urb DWC_OTG URB
desc_num ISOC descriptor number
++
++ ++

++Definition at line 2770 of file dwc_otg_hcd.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
uint32_t dwc_otg_hcd_urb_get_iso_desc_actual_length (dwc_otg_hcd_urb_t *  dwc_otg_urb,
int  desc_num 
)
++
++
++ ++

++Get actual length of ISOC descriptor, specified by desc_num. ++

++

Parameters:
++ ++ ++ ++
dwc_otg_urb DWC_OTG URB
desc_num ISOC descriptor number
++
++ ++

++Definition at line 2776 of file dwc_otg_hcd.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int dwc_otg_hcd_is_bandwidth_allocated (dwc_otg_hcd_t *  hcd,
void *  ep_handle 
)
++
++
++ ++

++Call this function to check if bandwidth was allocated for specified endpoint. ++

++Only for ISOC and INTERRUPT endpoints.

++

Parameters:
++ ++ ++ ++
hcd The HCD
ep_handle Endpoint handle
++
++ ++

++Definition at line 2782 of file dwc_otg_hcd.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int dwc_otg_hcd_is_bandwidth_freed (dwc_otg_hcd_t *  hcd,
void *  ep_handle 
)
++
++
++ ++

++Call this function to check if bandwidth was freed for specified endpoint. ++

++

Parameters:
++ ++ ++ ++
hcd The HCD
ep_handle Endpoint handle
++
++ ++

++Definition at line 2795 of file dwc_otg_hcd.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
uint8_t dwc_otg_hcd_get_ep_bandwidth (dwc_otg_hcd_t *  hcd,
void *  ep_handle 
)
++
++
++ ++

++Returns bandwidth allocated for specified endpoint in microseconds. ++

++Only for ISOC and INTERRUPT endpoints.

++

Parameters:
++ ++ ++ ++
hcd The HCD
ep_handle Endpoint handle
++
++ ++

++Definition at line 2808 of file dwc_otg_hcd.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_otg_hcd_dump_state (dwc_otg_hcd_t *  hcd  ) 
++
++
++ ++

++Dumps hcd state. ++

++

Parameters:
++ ++ ++
hcd The HCD
++
++ ++

++Definition at line 2815 of file dwc_otg_hcd.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_otg_hcd_dump_frrem (dwc_otg_hcd_t *  hcd  ) 
++
++
++ ++

++Dump the average frame remaining at SOF. ++

++This can be used to determine average interrupt latency. Frame remaining is also shown for start transfer and two additional sample points. Currently this function is not implemented.

++

Parameters:
++ ++ ++
hcd The HCD
++
++ ++

++Definition at line 2991 of file dwc_otg_hcd.c. ++

++

++

Variable Documentation

++ ++
++
++ ++ ++ ++ ++
dwc_otg_cil_callbacks_t hcd_cil_callbacks [static]
++
++
++ ++

++Initial value:

 {
++        .start = dwc_otg_hcd_start_cb,
++        .stop = dwc_otg_hcd_stop_cb,
++        .disconnect = dwc_otg_hcd_disconnect_cb,
++        .session_start = dwc_otg_hcd_session_start_cb,
++        .resume_wakeup = dwc_otg_hcd_rem_wakeup_cb,
++
++
++
++        .p = 0,
++}
++
HCD Callback structure for handling mode switching. ++

++ ++

++Definition at line 590 of file dwc_otg_hcd.c. ++

++

++

Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__hcd_8h-source.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__hcd_8h-source.html 2013-07-26 19:31:21.000000000 +0000 +@@ -0,0 +1,517 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_hcd.h Source File ++ ++ ++ ++ ++
++
++
++
++

dwc_otg_hcd.h

Go to the documentation of this file.
00001 /* ==========================================================================
++00002  * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd.h $
++00003  * $Revision: #52 $
++00004  * $Date: 2009/04/21 $
++00005  * $Change: 1237472 $
++00006  *
++00007  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
++00008  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
++00009  * otherwise expressly agreed to in writing between Synopsys and you.
++00010  *
++00011  * The Software IS NOT an item of Licensed Software or Licensed Product under
++00012  * any End User Software License Agreement or Agreement for Licensed Product
++00013  * with Synopsys or any supplement thereto. You are permitted to use and
++00014  * redistribute this Software in source and binary forms, with or without
++00015  * modification, provided that redistributions of source code must retain this
++00016  * notice. You may not view, use, disclose, copy or distribute this file or
++00017  * any information contained herein except pursuant to this license grant from
++00018  * Synopsys. If you do not agree with this notice, including the disclaimer
++00019  * below, then you are not authorized to use the Software.
++00020  *
++00021  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
++00022  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++00023  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++00024  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
++00025  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++00026  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
++00027  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
++00028  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
++00029  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
++00030  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
++00031  * DAMAGE.
++00032  * ========================================================================== */
++00033 #ifndef DWC_DEVICE_ONLY
++00034 #ifndef __DWC_HCD_H__
++00035 #define __DWC_HCD_H__
++00036 
++00037 #include <usb.h>
++00038 #include "dwc_otg_hcd_if.h"
++00039 #include "dwc_otg_core_if.h"
++00040 #include "dwc_list.h"
++00041 #include "dwc_otg_cil.h"
++00042 
++00055 struct dwc_otg_hcd_pipe_info {
++00056         uint8_t dev_addr;
++00057         uint8_t ep_num;
++00058         uint8_t pipe_type;
++00059         uint8_t pipe_dir;
++00060         uint16_t mps;
++00061 };
++00062 
++00063 struct dwc_otg_hcd_iso_packet_desc {
++00064         uint32_t offset;
++00065         uint32_t length;
++00066         uint32_t actual_length;
++00067         uint32_t status;
++00068 };
++00069 
++00070 struct dwc_otg_qtd;
++00071 
++00072 struct dwc_otg_hcd_urb {
++00073         void *priv;
++00074         struct dwc_otg_qtd *qtd;
++00075         void *buf;
++00076         dwc_dma_t dma;
++00077         void *setup_packet;
++00078         dwc_dma_t setup_dma;
++00079         uint32_t length;
++00080         uint32_t actual_length;
++00081         uint32_t status;
++00082         uint32_t error_count;
++00083         uint32_t packet_count;
++00084         uint32_t flags;
++00085         uint16_t interval;
++00086         struct dwc_otg_hcd_pipe_info pipe_info;
++00087         struct dwc_otg_hcd_iso_packet_desc iso_descs[0];
++00088 };
++00089 
++00090 static inline uint8_t dwc_otg_hcd_get_ep_num(struct dwc_otg_hcd_pipe_info *pipe)
++00091 {
++00092         return pipe->ep_num;
++00093 }
++00094 
++00095 static inline uint8_t dwc_otg_hcd_get_pipe_type(struct dwc_otg_hcd_pipe_info
++00096                                                 *pipe)
++00097 {
++00098         return pipe->pipe_type;
++00099 }
++00100 
++00101 static inline uint16_t dwc_otg_hcd_get_mps(struct dwc_otg_hcd_pipe_info *pipe)
++00102 {
++00103         return pipe->mps;
++00104 }
++00105 
++00106 static inline uint8_t dwc_otg_hcd_get_dev_addr(struct dwc_otg_hcd_pipe_info
++00107                                                *pipe)
++00108 {
++00109         return pipe->dev_addr;
++00110 }
++00111 
++00112 static inline uint8_t dwc_otg_hcd_is_pipe_isoc(struct dwc_otg_hcd_pipe_info
++00113                                                *pipe)
++00114 {
++00115         return (pipe->pipe_type == UE_ISOCHRONOUS);
++00116 }
++00117 
++00118 static inline uint8_t dwc_otg_hcd_is_pipe_int(struct dwc_otg_hcd_pipe_info
++00119                                               *pipe)
++00120 {
++00121         return (pipe->pipe_type == UE_INTERRUPT);
++00122 }
++00123 
++00124 static inline uint8_t dwc_otg_hcd_is_pipe_bulk(struct dwc_otg_hcd_pipe_info
++00125                                                *pipe)
++00126 {
++00127         return (pipe->pipe_type == UE_BULK);
++00128 }
++00129 
++00130 static inline uint8_t dwc_otg_hcd_is_pipe_control(struct dwc_otg_hcd_pipe_info
++00131                                                   *pipe)
++00132 {
++00133         return (pipe->pipe_type == UE_CONTROL);
++00134 }
++00135 
++00136 static inline uint8_t dwc_otg_hcd_is_pipe_in(struct dwc_otg_hcd_pipe_info *pipe)
++00137 {
++00138         return (pipe->pipe_dir == UE_DIR_IN);
++00139 }
++00140 
++00141 static inline uint8_t dwc_otg_hcd_is_pipe_out(struct dwc_otg_hcd_pipe_info
++00142                                               *pipe)
++00143 {
++00144         return (!dwc_otg_hcd_is_pipe_in(pipe));
++00145 }
++00146 
++00147 static inline void dwc_otg_hcd_fill_pipe(struct dwc_otg_hcd_pipe_info *pipe,
++00148                                          uint8_t devaddr, uint8_t ep_num,
++00149                                          uint8_t pipe_type, uint8_t pipe_dir,
++00150                                          uint16_t mps)
++00151 {
++00152         pipe->dev_addr = devaddr;
++00153         pipe->ep_num = ep_num;
++00154         pipe->pipe_type = pipe_type;
++00155         pipe->pipe_dir = pipe_dir;
++00156         pipe->mps = mps;
++00157 }
++00158 
++00162 typedef enum dwc_otg_control_phase {
++00163         DWC_OTG_CONTROL_SETUP,
++00164         DWC_OTG_CONTROL_DATA,
++00165         DWC_OTG_CONTROL_STATUS
++00166 } dwc_otg_control_phase_e;
++00167 
++00169 typedef enum dwc_otg_transaction_type {
++00170         DWC_OTG_TRANSACTION_NONE,
++00171         DWC_OTG_TRANSACTION_PERIODIC,
++00172         DWC_OTG_TRANSACTION_NON_PERIODIC,
++00173         DWC_OTG_TRANSACTION_ALL
++00174 } dwc_otg_transaction_type_e;
++00175 
++00176 struct dwc_otg_qh;
++00177 
++00191 typedef struct dwc_otg_qtd {
++00199         uint8_t data_toggle;
++00200 
++00202         dwc_otg_control_phase_e control_phase;
++00203 
++00206         uint8_t complete_split;
++00207 
++00209         uint32_t ssplit_out_xfer_count;
++00210 
++00215         uint8_t error_count;
++00216 
++00224         uint16_t isoc_frame_index;
++00225 
++00227         uint8_t isoc_split_pos;
++00228 
++00230         uint16_t isoc_split_offset;
++00231 
++00233         struct dwc_otg_hcd_urb *urb;
++00234 
++00235         struct dwc_otg_qh *qh;
++00236 
++00238          DWC_CIRCLEQ_ENTRY(dwc_otg_qtd) qtd_list_entry;
++00239 
++00241         uint8_t in_process;
++00242 
++00244         uint8_t n_desc;
++00245         
++00250         uint16_t isoc_frame_index_last;
++00251         
++00252 } dwc_otg_qtd_t;
++00253 
++00254 DWC_CIRCLEQ_HEAD(dwc_otg_qtd_list, dwc_otg_qtd);
++00255 
++00261 typedef struct dwc_otg_qh {
++00270         uint8_t ep_type;
++00271         uint8_t ep_is_in;
++00272 
++00274         uint16_t maxp;
++00275 
++00283         uint8_t dev_speed;
++00284 
++00292         uint8_t data_toggle;
++00293 
++00295         uint8_t ping_state;
++00296 
++00300         struct dwc_otg_qtd_list qtd_list;
++00301 
++00303         struct dwc_hc *channel;
++00304 
++00306         uint8_t do_split;
++00307 
++00312         uint16_t usecs;
++00313 
++00315         uint16_t interval;
++00316 
++00321         uint16_t sched_frame;
++00322 
++00324         uint16_t start_split_frame;
++00325 
++00332         uint8_t *dw_align_buf;
++00333         dwc_dma_t dw_align_buf_dma;
++00334         
++00336         dwc_list_link_t qh_list_entry;
++00337         
++00342         dwc_otg_host_dma_desc_t *desc_list;
++00343         
++00345         dwc_dma_t desc_list_dma;
++00346         
++00352         uint32_t *n_bytes;
++00353         
++00355         uint16_t ntd;
++00356         
++00358         uint8_t td_first;
++00360         uint8_t td_last;
++00361         
++00364 } dwc_otg_qh_t;
++00365 
++00366 DWC_CIRCLEQ_HEAD(hc_list, dwc_hc);
++00367 
++00372 struct dwc_otg_hcd {
++00374         dwc_otg_core_if_t *core_if;
++00375 
++00377         struct dwc_otg_hcd_function_ops *fops;
++00378 
++00380         volatile union dwc_otg_hcd_internal_flags {
++00381                 uint32_t d32;
++00382                 struct {
++00383                         unsigned port_connect_status_change:1;
++00384                         unsigned port_connect_status:1;
++00385                         unsigned port_reset_change:1;
++00386                         unsigned port_enable_change:1;
++00387                         unsigned port_suspend_change:1;
++00388                         unsigned port_over_current_change:1;
++00389                         unsigned port_l1_change:1;
++00390                         unsigned reserved:26;
++00391                 } b;
++00392         } flags;
++00393 
++00399         dwc_list_link_t non_periodic_sched_inactive;
++00400 
++00406         dwc_list_link_t non_periodic_sched_active;
++00407 
++00412         dwc_list_link_t *non_periodic_qh_ptr;
++00413 
++00428         dwc_list_link_t periodic_sched_inactive;
++00429 
++00437         dwc_list_link_t periodic_sched_ready;
++00438 
++00446         dwc_list_link_t periodic_sched_assigned;
++00447 
++00457         dwc_list_link_t periodic_sched_queued;
++00458 
++00464         uint16_t periodic_usecs;
++00465 
++00470         uint16_t frame_number;
++00471 
++00476         struct hc_list free_hc_list;
++00483         int periodic_channels;
++00484 
++00488         int non_periodic_channels;
++00489 
++00495         struct dwc_hc *hc_ptr_array[MAX_EPS_CHANNELS];
++00496 
++00502         uint8_t *status_buf;
++00503 
++00507         dma_addr_t status_buf_dma;
++00508 #define DWC_OTG_HCD_STATUS_BUF_SIZE 64
++00509 
++00515         dwc_timer_t *conn_timer;
++00516 
++00517         /* Tasket to do a reset */
++00518         dwc_tasklet_t *reset_tasklet;
++00519 
++00520         /*  */
++00521         dwc_spinlock_t *lock;
++00522 
++00526         void *priv;
++00527 
++00528         uint8_t otg_port;
++00529 
++00531         uint32_t *frame_list;
++00532 
++00534         dma_addr_t frame_list_dma;
++00535 
++00536 #ifdef DEBUG
++00537         uint32_t frrem_samples;
++00538         uint64_t frrem_accum;
++00539 
++00540         uint32_t hfnum_7_samples_a;
++00541         uint64_t hfnum_7_frrem_accum_a;
++00542         uint32_t hfnum_0_samples_a;
++00543         uint64_t hfnum_0_frrem_accum_a;
++00544         uint32_t hfnum_other_samples_a;
++00545         uint64_t hfnum_other_frrem_accum_a;
++00546 
++00547         uint32_t hfnum_7_samples_b;
++00548         uint64_t hfnum_7_frrem_accum_b;
++00549         uint32_t hfnum_0_samples_b;
++00550         uint64_t hfnum_0_frrem_accum_b;
++00551         uint32_t hfnum_other_samples_b;
++00552         uint64_t hfnum_other_frrem_accum_b;
++00553 #endif
++00554 };
++00555 
++00558 extern dwc_otg_transaction_type_e dwc_otg_hcd_select_transactions(dwc_otg_hcd_t
++00559                                                                   * hcd);
++00560 extern void dwc_otg_hcd_queue_transactions(dwc_otg_hcd_t * hcd,
++00561                                     dwc_otg_transaction_type_e tr_type);
++00562 
++00567 extern int32_t dwc_otg_hcd_handle_intr(dwc_otg_hcd_t * dwc_otg_hcd);
++00568 extern int32_t dwc_otg_hcd_handle_sof_intr(dwc_otg_hcd_t * dwc_otg_hcd);
++00569 extern int32_t dwc_otg_hcd_handle_rx_status_q_level_intr(dwc_otg_hcd_t *
++00570                                                          dwc_otg_hcd);
++00571 extern int32_t dwc_otg_hcd_handle_np_tx_fifo_empty_intr(dwc_otg_hcd_t *
++00572                                                         dwc_otg_hcd);
++00573 extern int32_t dwc_otg_hcd_handle_perio_tx_fifo_empty_intr(dwc_otg_hcd_t *
++00574                                                            dwc_otg_hcd);
++00575 extern int32_t dwc_otg_hcd_handle_incomplete_periodic_intr(dwc_otg_hcd_t *
++00576                                                            dwc_otg_hcd);
++00577 extern int32_t dwc_otg_hcd_handle_port_intr(dwc_otg_hcd_t * dwc_otg_hcd);
++00578 extern int32_t dwc_otg_hcd_handle_conn_id_status_change_intr(dwc_otg_hcd_t *
++00579                                                              dwc_otg_hcd);
++00580 extern int32_t dwc_otg_hcd_handle_disconnect_intr(dwc_otg_hcd_t * dwc_otg_hcd);
++00581 extern int32_t dwc_otg_hcd_handle_hc_intr(dwc_otg_hcd_t * dwc_otg_hcd);
++00582 extern int32_t dwc_otg_hcd_handle_hc_n_intr(dwc_otg_hcd_t * dwc_otg_hcd,
++00583                                             uint32_t num);
++00584 extern int32_t dwc_otg_hcd_handle_session_req_intr(dwc_otg_hcd_t * dwc_otg_hcd);
++00585 extern int32_t dwc_otg_hcd_handle_wakeup_detected_intr(dwc_otg_hcd_t *
++00586                                                        dwc_otg_hcd);
++00592 /* Implemented in dwc_otg_hcd_queue.c */
++00593 extern dwc_otg_qh_t *dwc_otg_hcd_qh_create(dwc_otg_hcd_t * hcd,
++00594                                            dwc_otg_hcd_urb_t * urb);
++00595 extern void dwc_otg_hcd_qh_free(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh);
++00596 extern int dwc_otg_hcd_qh_add(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh);
++00597 extern void dwc_otg_hcd_qh_remove(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh);
++00598 extern void dwc_otg_hcd_qh_deactivate(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh,
++00599                                       int sched_csplit);
++00600 
++00602 static inline void dwc_otg_hcd_qh_remove_and_free(dwc_otg_hcd_t * hcd,
++00603                                                   dwc_otg_qh_t * qh)
++00604 {
++00605         dwc_otg_hcd_qh_remove(hcd, qh);
++00606         dwc_otg_hcd_qh_free(hcd, qh);
++00607 }
++00608 
++00611 static inline dwc_otg_qh_t *dwc_otg_hcd_qh_alloc(void)
++00612 {
++00613         return (dwc_otg_qh_t *) dwc_alloc(sizeof(dwc_otg_qh_t));
++00614 }
++00615 
++00616 extern dwc_otg_qtd_t *dwc_otg_hcd_qtd_create(dwc_otg_hcd_urb_t * urb);
++00617 extern void dwc_otg_hcd_qtd_init(dwc_otg_qtd_t * qtd, dwc_otg_hcd_urb_t * urb);
++00618 extern int dwc_otg_hcd_qtd_add(dwc_otg_qtd_t * qtd, dwc_otg_hcd_t * dwc_otg_hcd,
++00619                                dwc_otg_qh_t ** qh);
++00620 
++00623 static inline dwc_otg_qtd_t *dwc_otg_hcd_qtd_alloc(void)
++00624 {
++00625         return (dwc_otg_qtd_t *) dwc_alloc(sizeof(dwc_otg_qtd_t));
++00626 }
++00627 
++00631 static inline void dwc_otg_hcd_qtd_free(dwc_otg_qtd_t * qtd)
++00632 {
++00633         dwc_free(qtd);
++00634 }
++00635 
++00641 static inline void dwc_otg_hcd_qtd_remove(dwc_otg_hcd_t * hcd,
++00642                                           dwc_otg_qtd_t * qtd,
++00643                                           dwc_otg_qh_t * qh)
++00644 {
++00645         uint64_t flags;
++00646         DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
++00647         DWC_CIRCLEQ_REMOVE(&qh->qtd_list, qtd, qtd_list_entry);
++00648         DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
++00649 }
++00650 
++00652 static inline void dwc_otg_hcd_qtd_remove_and_free(dwc_otg_hcd_t * hcd,
++00653                                                    dwc_otg_qtd_t * qtd,
++00654                                                    dwc_otg_qh_t * qh)
++00655 {
++00656         dwc_otg_hcd_qtd_remove(hcd, qtd, qh);
++00657         dwc_otg_hcd_qtd_free(qtd);
++00658 }
++00659 
++00665 extern void dwc_otg_hcd_start_xfer_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh);
++00666 extern void dwc_otg_hcd_complete_xfer_ddma(dwc_otg_hcd_t * hcd,
++00667                                            dwc_hc_t * hc,
++00668                                            dwc_otg_hc_regs_t * hc_regs,
++00669                                            dwc_otg_halt_status_e halt_status);
++00670 
++00671 extern int dwc_otg_hcd_qh_init_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh);
++00672 extern void dwc_otg_hcd_qh_free_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh);
++00673 
++00678 dwc_otg_qh_t *dwc_urb_to_qh(dwc_otg_hcd_urb_t * urb);
++00681 #ifdef CONFIG_USB_DWC_OTG_LPM
++00682 extern int dwc_otg_hcd_get_hc_for_lpm_tran(dwc_otg_hcd_t * hcd,
++00683                                            uint8_t devaddr);
++00684 extern void dwc_otg_hcd_free_hc_from_lpm(dwc_otg_hcd_t * hcd);
++00685 #endif
++00686 
++00688 #define dwc_list_to_qh(_list_head_ptr_) container_of(_list_head_ptr_, dwc_otg_qh_t, qh_list_entry)
++00689 
++00691 #define dwc_list_to_qtd(_list_head_ptr_) container_of(_list_head_ptr_, dwc_otg_qtd_t, qtd_list_entry)
++00692 
++00694 #define dwc_qh_is_non_per(_qh_ptr_) ((_qh_ptr_->ep_type == UE_BULK) || \
++00695                                      (_qh_ptr_->ep_type == UE_CONTROL))
++00696 
++00698 #define dwc_hb_mult(wMaxPacketSize) (1 + (((wMaxPacketSize) >> 11) & 0x03))
++00699 
++00701 #define dwc_max_packet(wMaxPacketSize) ((wMaxPacketSize) & 0x07ff)
++00702 
++00708 static inline int dwc_frame_num_le(uint16_t frame1, uint16_t frame2)
++00709 {
++00710         return ((frame2 - frame1) & DWC_HFNUM_MAX_FRNUM) <=
++00711             (DWC_HFNUM_MAX_FRNUM >> 1);
++00712 }
++00713 
++00719 static inline int dwc_frame_num_gt(uint16_t frame1, uint16_t frame2)
++00720 {
++00721         return (frame1 != frame2) &&
++00722             (((frame1 - frame2) & DWC_HFNUM_MAX_FRNUM) <
++00723              (DWC_HFNUM_MAX_FRNUM >> 1));
++00724 }
++00725 
++00730 static inline uint16_t dwc_frame_num_inc(uint16_t frame, uint16_t inc)
++00731 {
++00732         return (frame + inc) & DWC_HFNUM_MAX_FRNUM;
++00733 }
++00734 
++00735 static inline uint16_t dwc_full_frame_num(uint16_t frame)
++00736 {
++00737         return (frame & DWC_HFNUM_MAX_FRNUM) >> 3;
++00738 }
++00739 
++00740 static inline uint16_t dwc_micro_frame_num(uint16_t frame)
++00741 {
++00742         return frame & 0x7;
++00743 }
++00744 
++00745 void dwc_otg_hcd_save_data_toggle(dwc_hc_t * hc,
++00746                                   dwc_otg_hc_regs_t * hc_regs, 
++00747                                   dwc_otg_qtd_t * qtd);
++00748 
++00749 #ifdef DEBUG
++00750 
++00759 #define dwc_sample_frrem(_hcd, _qh, _letter) \
++00760 { \
++00761         hfnum_data_t hfnum; \
++00762         dwc_otg_qtd_t *qtd; \
++00763         qtd = list_entry(_qh->qtd_list.next, dwc_otg_qtd_t, qtd_list_entry); \
++00764         if (usb_pipeint(qtd->urb->pipe) && _qh->start_split_frame != 0 && !qtd->complete_split) { \
++00765                 hfnum.d32 = dwc_read_reg32(&_hcd->core_if->host_if->host_global_regs->hfnum); \
++00766                 switch (hfnum.b.frnum & 0x7) { \
++00767                 case 7: \
++00768                         _hcd->hfnum_7_samples_##_letter++; \
++00769                         _hcd->hfnum_7_frrem_accum_##_letter += hfnum.b.frrem; \
++00770                         break; \
++00771                 case 0: \
++00772                         _hcd->hfnum_0_samples_##_letter++; \
++00773                         _hcd->hfnum_0_frrem_accum_##_letter += hfnum.b.frrem; \
++00774                         break; \
++00775                 default: \
++00776                         _hcd->hfnum_other_samples_##_letter++; \
++00777                         _hcd->hfnum_other_frrem_accum_##_letter += hfnum.b.frrem; \
++00778                         break; \
++00779                 } \
++00780         } \
++00781 }
++00782 #else
++00783 #define dwc_sample_frrem(_hcd, _qh, _letter)
++00784 #endif
++00785 #endif
++00786 #endif                          /* DWC_DEVICE_ONLY */
++
Generated on Tue May 5 02:22:48 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__hcd_8h.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__hcd_8h.html 2013-07-26 19:31:21.000000000 +0000 +@@ -0,0 +1,1310 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_hcd.h File Reference ++ ++ ++ ++ ++
++
++
++
++

dwc_otg_hcd.h File Reference

This file contains the structures, constants, and interfaces for the Host Contoller Driver (HCD). More... ++

++#include <usb.h>
++#include "dwc_otg_hcd_if.h"
++#include "dwc_otg_core_if.h"
++#include "dwc_list.h"
++#include "dwc_otg_cil.h"
++ ++

++Go to the source code of this file. ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++

Data Structures

struct  dwc_otg_hcd_pipe_info
struct  dwc_otg_hcd_iso_packet_desc
struct  dwc_otg_hcd_urb
struct  dwc_otg_qtd
 A Queue Transfer Descriptor (QTD) holds the state of a bulk, control, interrupt, or isochronous transfer. More...
struct  dwc_otg_qh
 A Queue Head (QH) holds the static characteristics of an endpoint and maintains a list of transfers (QTDs) for that endpoint. More...
struct  dwc_otg_hcd
 This structure holds the state of the HCD, including the non-periodic and periodic schedules. More...
union  dwc_otg_hcd::dwc_otg_hcd_internal_flags
 Internal DWC HCD Flags. More...

Transaction Execution Functions

dwc_otg_transaction_type_e dwc_otg_hcd_select_transactions (dwc_otg_hcd_t *hcd)
 This function selects transactions from the HCD transfer schedule and assigns them to available host channels.
void dwc_otg_hcd_queue_transactions (dwc_otg_hcd_t *hcd, dwc_otg_transaction_type_e tr_type)
 This function processes the currently active host channels and queues transactions for these channels to the DWC_otg controller.

Interrupt Handler Functions

int32_t dwc_otg_hcd_handle_intr (dwc_otg_hcd_t *dwc_otg_hcd)
 This function handles interrupts for the HCD.
int32_t dwc_otg_hcd_handle_sof_intr (dwc_otg_hcd_t *dwc_otg_hcd)
 Handles the start-of-frame interrupt in host mode.
int32_t dwc_otg_hcd_handle_rx_status_q_level_intr (dwc_otg_hcd_t *dwc_otg_hcd)
 Handles the Rx Status Queue Level Interrupt, which indicates that there is at least one packet in the Rx FIFO.
int32_t dwc_otg_hcd_handle_np_tx_fifo_empty_intr (dwc_otg_hcd_t *dwc_otg_hcd)
 This interrupt occurs when the non-periodic Tx FIFO is half-empty.
int32_t dwc_otg_hcd_handle_perio_tx_fifo_empty_intr (dwc_otg_hcd_t *dwc_otg_hcd)
 This interrupt occurs when the periodic Tx FIFO is half-empty.
++int32_t dwc_otg_hcd_handle_incomplete_periodic_intr (dwc_otg_hcd_t *dwc_otg_hcd)
int32_t dwc_otg_hcd_handle_port_intr (dwc_otg_hcd_t *dwc_otg_hcd)
 There are multiple conditions that can cause a port interrupt.
++int32_t dwc_otg_hcd_handle_conn_id_status_change_intr (dwc_otg_hcd_t *dwc_otg_hcd)
++int32_t dwc_otg_hcd_handle_disconnect_intr (dwc_otg_hcd_t *dwc_otg_hcd)
int32_t dwc_otg_hcd_handle_hc_intr (dwc_otg_hcd_t *dwc_otg_hcd)
 This interrupt indicates that one or more host channels has a pending interrupt.
++int32_t dwc_otg_hcd_handle_hc_n_intr (dwc_otg_hcd_t *dwc_otg_hcd, uint32_t num)
 Handles interrupt for a specific Host Channel.
++int32_t dwc_otg_hcd_handle_session_req_intr (dwc_otg_hcd_t *dwc_otg_hcd)
++int32_t dwc_otg_hcd_handle_wakeup_detected_intr (dwc_otg_hcd_t *dwc_otg_hcd)

Schedule Queue Functions

dwc_otg_qh_t * dwc_otg_hcd_qh_create (dwc_otg_hcd_t *hcd, dwc_otg_hcd_urb_t *urb)
 This function allocates and initializes a QH.
void dwc_otg_hcd_qh_free (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
 Free each QTD in the QH's QTD-list then free the QH.
int dwc_otg_hcd_qh_add (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
 This function adds a QH to either the non periodic or periodic schedule if it is not already in the schedule.
void dwc_otg_hcd_qh_remove (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
 Removes a QH from either the non-periodic or periodic schedule.
void dwc_otg_hcd_qh_deactivate (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh, int sched_csplit)
 Deactivates a QH.
++static void dwc_otg_hcd_qh_remove_and_free (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
 Remove and free a QH.
static dwc_otg_qh_t * dwc_otg_hcd_qh_alloc (void)
 Allocates memory for a QH structure.
dwc_otg_qtd_t * dwc_otg_hcd_qtd_create (dwc_otg_hcd_urb_t *urb)
 This function allocates and initializes a QTD.
void dwc_otg_hcd_qtd_init (dwc_otg_qtd_t *qtd, dwc_otg_hcd_urb_t *urb)
 Initializes a QTD structure.
int dwc_otg_hcd_qtd_add (dwc_otg_qtd_t *qtd, dwc_otg_hcd_t *dwc_otg_hcd, dwc_otg_qh_t **qh)
 This function adds a QTD to the QTD-list of a QH.
static dwc_otg_qtd_t * dwc_otg_hcd_qtd_alloc (void)
 Allocates memory for a QTD structure.
static void dwc_otg_hcd_qtd_free (dwc_otg_qtd_t *qtd)
 Frees the memory for a QTD structure.
static void dwc_otg_hcd_qtd_remove (dwc_otg_hcd_t *hcd, dwc_otg_qtd_t *qtd, dwc_otg_qh_t *qh)
 Removes a QTD from list.
++static void dwc_otg_hcd_qtd_remove_and_free (dwc_otg_hcd_t *hcd, dwc_otg_qtd_t *qtd, dwc_otg_qh_t *qh)
 Remove and free a QTD.

Descriptor DMA Supporting Functions

void dwc_otg_hcd_start_xfer_ddma (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
 For Control and Bulk endpoints initializes descriptor list and starts the transfer.
void dwc_otg_hcd_complete_xfer_ddma (dwc_otg_hcd_t *hcd, dwc_hc_t *hc, dwc_otg_hc_regs_t *hc_regs, dwc_otg_halt_status_e halt_status)
 This function is called from interrupt handlers.
int dwc_otg_hcd_qh_init_ddma (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
 Initializes a QH structure's Descriptor DMA related members.
void dwc_otg_hcd_qh_free_ddma (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
 Frees descriptor list memory associated with the QH.

Internal Functions

++dwc_otg_qh_t * dwc_urb_to_qh (dwc_otg_hcd_urb_t *urb)

Defines

++#define DWC_OTG_HCD_STATUS_BUF_SIZE   64
++#define dwc_list_to_qh(_list_head_ptr_)   container_of(_list_head_ptr_, dwc_otg_qh_t, qh_list_entry)
 Gets the QH that contains the list_head.
++#define dwc_list_to_qtd(_list_head_ptr_)   container_of(_list_head_ptr_, dwc_otg_qtd_t, qtd_list_entry)
 Gets the QTD that contains the list_head.
#define dwc_qh_is_non_per(_qh_ptr_)
 Check if QH is non-periodic.
++#define dwc_hb_mult(wMaxPacketSize)   (1 + (((wMaxPacketSize) >> 11) & 0x03))
 High bandwidth multiplier as encoded in highspeed endpoint descriptors.
++#define dwc_max_packet(wMaxPacketSize)   ((wMaxPacketSize) & 0x07ff)
 Packet size for any kind of endpoint descriptor.
++#define dwc_sample_frrem(_hcd, _qh, _letter)

Typedefs

++typedef enum dwc_otg_control_phase dwc_otg_control_phase_e
 Phases for control transfers.
++typedef enum dwc_otg_transaction_type dwc_otg_transaction_type_e
 Transaction types.
typedef dwc_otg_qtd dwc_otg_qtd_t
 A Queue Transfer Descriptor (QTD) holds the state of a bulk, control, interrupt, or isochronous transfer.
typedef dwc_otg_qh dwc_otg_qh_t
 A Queue Head (QH) holds the static characteristics of an endpoint and maintains a list of transfers (QTDs) for that endpoint.

Enumerations

enum  dwc_otg_control_phase { DWC_OTG_CONTROL_SETUP, ++DWC_OTG_CONTROL_DATA, ++DWC_OTG_CONTROL_STATUS ++ }
 Phases for control transfers.
enum  dwc_otg_transaction_type { DWC_OTG_TRANSACTION_NONE, ++DWC_OTG_TRANSACTION_PERIODIC, ++DWC_OTG_TRANSACTION_NON_PERIODIC, ++DWC_OTG_TRANSACTION_ALL ++ }
 Transaction types.

Functions

++static uint8_t dwc_otg_hcd_get_ep_num (struct dwc_otg_hcd_pipe_info *pipe)
++static uint8_t dwc_otg_hcd_get_pipe_type (struct dwc_otg_hcd_pipe_info *pipe)
++static uint16_t dwc_otg_hcd_get_mps (struct dwc_otg_hcd_pipe_info *pipe)
++static uint8_t dwc_otg_hcd_get_dev_addr (struct dwc_otg_hcd_pipe_info *pipe)
++static uint8_t dwc_otg_hcd_is_pipe_isoc (struct dwc_otg_hcd_pipe_info *pipe)
++static uint8_t dwc_otg_hcd_is_pipe_int (struct dwc_otg_hcd_pipe_info *pipe)
++static uint8_t dwc_otg_hcd_is_pipe_bulk (struct dwc_otg_hcd_pipe_info *pipe)
++static uint8_t dwc_otg_hcd_is_pipe_control (struct dwc_otg_hcd_pipe_info *pipe)
++static uint8_t dwc_otg_hcd_is_pipe_in (struct dwc_otg_hcd_pipe_info *pipe)
++static uint8_t dwc_otg_hcd_is_pipe_out (struct dwc_otg_hcd_pipe_info *pipe)
++static void dwc_otg_hcd_fill_pipe (struct dwc_otg_hcd_pipe_info *pipe, uint8_t devaddr, uint8_t ep_num, uint8_t pipe_type, uint8_t pipe_dir, uint16_t mps)
++ DWC_CIRCLEQ_HEAD (dwc_otg_qtd_list, dwc_otg_qtd)
++ DWC_CIRCLEQ_HEAD (hc_list, dwc_hc)
static int dwc_frame_num_le (uint16_t frame1, uint16_t frame2)
 Returns true if _frame1 is less than or equal to _frame2.
static int dwc_frame_num_gt (uint16_t frame1, uint16_t frame2)
 Returns true if _frame1 is greater than _frame2.
static uint16_t dwc_frame_num_inc (uint16_t frame, uint16_t inc)
 Increments _frame by the amount specified by _inc.
++static uint16_t dwc_full_frame_num (uint16_t frame)
++static uint16_t dwc_micro_frame_num (uint16_t frame)
++void dwc_otg_hcd_save_data_toggle (dwc_hc_t *hc, dwc_otg_hc_regs_t *hc_regs, dwc_otg_qtd_t *qtd)
++

Detailed Description

++This file contains the structures, constants, and interfaces for the Host Contoller Driver (HCD). ++

++The Host Controller Driver (HCD) is responsible for translating requests from the USB Driver into the appropriate actions on the DWC_otg controller. It isolates the USBD from the specifics of the controller by providing an API to the USBD. ++

++Definition in file dwc_otg_hcd.h.

Define Documentation

++ ++
++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
#define dwc_qh_is_non_per (_qh_ptr_   ) 
++
++
++ ++

++Value:

((_qh_ptr_->ep_type == UE_BULK) || \
++                                     (_qh_ptr_->ep_type == UE_CONTROL))
++
Check if QH is non-periodic. ++

++ ++

++Definition at line 694 of file dwc_otg_hcd.h. ++

++

++

Typedef Documentation

++ ++
++
++ ++ ++ ++ ++
typedef struct dwc_otg_qtd dwc_otg_qtd_t
++
++
++ ++

++A Queue Transfer Descriptor (QTD) holds the state of a bulk, control, interrupt, or isochronous transfer. ++

++A single QTD is created for each URB (of one of these types) submitted to the HCD. The transfer associated with a QTD may require one or multiple transactions.

++A QTD is linked to a Queue Head, which is entered in either the non-periodic or periodic schedule for execution. When a QTD is chosen for execution, some or all of its transactions may be executed. After execution, the state of the QTD is updated. The QTD may be retired if all its transactions are complete or if an error occurred. Otherwise, it remains in the schedule so more transactions can be executed later. ++

++

++ ++

++
++ ++ ++ ++ ++
typedef struct dwc_otg_qh dwc_otg_qh_t
++
++
++ ++

++A Queue Head (QH) holds the static characteristics of an endpoint and maintains a list of transfers (QTDs) for that endpoint. ++

++A QH structure may be entered in either the non-periodic or periodic schedule. ++

++

++

Function Documentation

++ ++
++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
dwc_otg_transaction_type_e dwc_otg_hcd_select_transactions (dwc_otg_hcd_t *  hcd  ) 
++
++
++ ++

++This function selects transactions from the HCD transfer schedule and assigns them to available host channels. ++

++It is called from HCD interrupt handler functions.

++

Parameters:
++ ++ ++
hcd The HCD state structure.
++
++
Returns:
The types of new transactions that were assigned to host channels.
++ ++

++Definition at line 1055 of file dwc_otg_hcd.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_otg_hcd_queue_transactions (dwc_otg_hcd_t *  hcd,
dwc_otg_transaction_type_e  tr_type 
)
++
++
++ ++

++This function processes the currently active host channels and queues transactions for these channels to the DWC_otg controller. ++

++It is called from HCD interrupt handler functions.

++

Parameters:
++ ++ ++ ++
hcd The HCD state structure.
tr_type The type(s) of transactions to queue (non-periodic, periodic, or both).
++
++ ++

++Definition at line 1426 of file dwc_otg_hcd.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int32_t dwc_otg_hcd_handle_intr (dwc_otg_hcd_t *  dwc_otg_hcd  ) 
++
++
++ ++

++This function handles interrupts for the HCD. ++

++ ++

++

Todo:
Implement i2cintr handler.
++ ++

++Definition at line 43 of file dwc_otg_hcd_intr.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int32_t dwc_otg_hcd_handle_sof_intr (dwc_otg_hcd_t *  hcd  ) 
++
++
++ ++

++Handles the start-of-frame interrupt in host mode. ++

++Non-periodic transactions may be queued to the DWC_otg controller for the current (micro)frame. Periodic transactions may be queued to the controller for the next (micro)frame. ++

++Definition at line 169 of file dwc_otg_hcd_intr.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int32_t dwc_otg_hcd_handle_rx_status_q_level_intr (dwc_otg_hcd_t *  dwc_otg_hcd  ) 
++
++
++ ++

++Handles the Rx Status Queue Level Interrupt, which indicates that there is at least one packet in the Rx FIFO. ++

++The packets are moved from the FIFO to memory if the DWC_otg controller is operating in Slave mode. ++

++Definition at line 222 of file dwc_otg_hcd_intr.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int32_t dwc_otg_hcd_handle_np_tx_fifo_empty_intr (dwc_otg_hcd_t *  dwc_otg_hcd  ) 
++
++
++ ++

++This interrupt occurs when the non-periodic Tx FIFO is half-empty. ++

++More data packets may be written to the FIFO for OUT transfers. More requests may be written to the non-periodic request queue for IN transfers. This interrupt is enabled only in Slave mode. ++

++Definition at line 271 of file dwc_otg_hcd_intr.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int32_t dwc_otg_hcd_handle_perio_tx_fifo_empty_intr (dwc_otg_hcd_t *  dwc_otg_hcd  ) 
++
++
++ ++

++This interrupt occurs when the periodic Tx FIFO is half-empty. ++

++More data packets may be written to the FIFO for OUT transfers. More requests may be written to the periodic request queue for IN transfers. This interrupt is enabled only in Slave mode. ++

++Definition at line 283 of file dwc_otg_hcd_intr.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int32_t dwc_otg_hcd_handle_port_intr (dwc_otg_hcd_t *  dwc_otg_hcd  ) 
++
++
++ ++

++There are multiple conditions that can cause a port interrupt. ++

++This function determines which interrupt conditions have occurred and handles them appropriately. ++

++Overcurrent Change Interrupt ++

++Definition at line 294 of file dwc_otg_hcd_intr.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int32_t dwc_otg_hcd_handle_hc_intr (dwc_otg_hcd_t *  dwc_otg_hcd  ) 
++
++
++ ++

++This interrupt indicates that one or more host channels has a pending interrupt. ++

++There are multiple conditions that can cause each host channel interrupt. This function determines which conditions have occurred for each host channel interrupt and handles them appropriately. ++

++Definition at line 453 of file dwc_otg_hcd_intr.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
dwc_otg_qh_t* dwc_otg_hcd_qh_create (dwc_otg_hcd_t *  hcd,
dwc_otg_hcd_urb_t *  urb 
)
++
++
++ ++

++This function allocates and initializes a QH. ++

++

Parameters:
++ ++ ++ ++
hcd The HCD state structure for the DWC OTG controller.
urb Holds the information about the device/endpoint that we need to initialize the QH.
++
++
Returns:
Returns pointer to the newly allocated QH, or NULL on error.
++ ++

++

Todo:
add memflags argument
++ ++

++Definition at line 296 of file dwc_otg_hcd_queue.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_otg_hcd_qh_free (dwc_otg_hcd_t *  hcd,
dwc_otg_qh_t *  qh 
)
++
++
++ ++

++Free each QTD in the QH's QTD-list then free the QH. ++

++QH should already be removed from a list. QTD list should already be empty if called from URB Dequeue.

++

Parameters:
++ ++ ++ ++
hcd HCD instance.
qh The QH to free.
++
++ ++

++Definition at line 53 of file dwc_otg_hcd_queue.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int dwc_otg_hcd_qh_add (dwc_otg_hcd_t *  hcd,
dwc_otg_qh_t *  qh 
)
++
++
++ ++

++This function adds a QH to either the non periodic or periodic schedule if it is not already in the schedule. ++

++If the QH is already in the schedule, no action is taken.

++

Returns:
0 if successful, negative error code otherwise.
++ ++

++Definition at line 472 of file dwc_otg_hcd_queue.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_otg_hcd_qh_remove (dwc_otg_hcd_t *  hcd,
dwc_otg_qh_t *  qh 
)
++
++
++ ++

++Removes a QH from either the non-periodic or periodic schedule. ++

++Memory is not freed.

++

Parameters:
++ ++ ++ ++
hcd The HCD state structure.
qh QH to remove from schedule.
++
++ ++

++Definition at line 522 of file dwc_otg_hcd_queue.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_otg_hcd_qh_deactivate (dwc_otg_hcd_t *  hcd,
dwc_otg_qh_t *  qh,
int  sched_next_periodic_split 
)
++
++
++ ++

++Deactivates a QH. ++

++For non-periodic QHs, removes the QH from the active non-periodic schedule. The QH is added to the inactive non-periodic schedule if any QTDs are still attached to the QH.

++For periodic QHs, the QH is removed from the periodic queued schedule. If there are any QTDs still attached to the QH, the QH is added to either the periodic inactive schedule or the periodic ready schedule and its next scheduled frame is calculated. The QH is placed in the ready schedule if the scheduled frame has been reached already. Otherwise it's placed in the inactive schedule. If there are no QTDs attached to the QH, the QH is completely removed from the periodic schedule. ++

++Definition at line 559 of file dwc_otg_hcd_queue.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
static dwc_otg_qh_t* dwc_otg_hcd_qh_alloc (void   )  [inline, static]
++
++
++ ++

++Allocates memory for a QH structure. ++

++

Returns:
Returns the memory allocate or NULL on error.
++ ++

++Definition at line 611 of file dwc_otg_hcd.h. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
dwc_otg_qtd_t* dwc_otg_hcd_qtd_create (dwc_otg_hcd_urb_t *  urb  ) 
++
++
++ ++

++This function allocates and initializes a QTD. ++

++

Parameters:
++ ++ ++
urb The URB to create a QTD from. Each URB-QTD pair will end up pointing to each other so each pair should have a unique correlation.
++
++
Returns:
Returns pointer to the newly allocated QTD, or NULL on error.
++ ++

++Definition at line 643 of file dwc_otg_hcd_queue.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_otg_hcd_qtd_init (dwc_otg_qtd_t *  qtd,
dwc_otg_hcd_urb_t *  urb 
)
++
++
++ ++

++Initializes a QTD structure. ++

++

Parameters:
++ ++ ++ ++
qtd The QTD to initialize.
urb The URB to use for initialization.
++
++ ++

++Definition at line 661 of file dwc_otg_hcd_queue.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int dwc_otg_hcd_qtd_add (dwc_otg_qtd_t *  qtd,
dwc_otg_hcd_t *  hcd,
dwc_otg_qh_t **  qh 
)
++
++
++ ++

++This function adds a QTD to the QTD-list of a QH. ++

++It will find the correct QH to place the QTD into. If it does not find a QH, then it will create a new QH. If the QH to which the QTD is added is not currently scheduled, it is placed into the proper schedule based on its EP type.

++

Parameters:
++ ++ ++ ++ ++
[in] qtd The QTD to add
[in] hcd The DWC HCD structure
[out] qh out parameter to return queue head
++
++
Returns:
0 if successful, negative error code otherwise.
++ ++

++Definition at line 698 of file dwc_otg_hcd_queue.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
static dwc_otg_qtd_t* dwc_otg_hcd_qtd_alloc (void   )  [inline, static]
++
++
++ ++

++Allocates memory for a QTD structure. ++

++

Returns:
Returns the memory allocate or NULL on error.
++ ++

++Definition at line 623 of file dwc_otg_hcd.h. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
static void dwc_otg_hcd_qtd_free (dwc_otg_qtd_t *  qtd  )  [inline, static]
++
++
++ ++

++Frees the memory for a QTD structure. ++

++QTD should already be removed from list.

Parameters:
++ ++ ++
qtd QTD to free.
++
++ ++

++Definition at line 631 of file dwc_otg_hcd.h. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
static void dwc_otg_hcd_qtd_remove (dwc_otg_hcd_t *  hcd,
dwc_otg_qtd_t *  qtd,
dwc_otg_qh_t *  qh 
) [inline, static]
++
++
++ ++

++Removes a QTD from list. ++

++

Parameters:
++ ++ ++ ++ ++
hcd HCD instance.
qtd QTD to remove from list.
qh QTD belongs to.
++
++ ++

++Definition at line 641 of file dwc_otg_hcd.h. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_otg_hcd_start_xfer_ddma (dwc_otg_hcd_t *  hcd,
dwc_otg_qh_t *  qh 
)
++
++
++ ++

++For Control and Bulk endpoints initializes descriptor list and starts the transfer. ++

++For Interrupt and Isochronous endpoints initializes descriptor list then updates FrameList, marking appropriate entries as active. In case of Isochronous, the starting descriptor index is calculated based on the scheduled frame, but only on the first transfer descriptor within a session. Then starts the transfer via enabling the channel. For Isochronous endpoint the channel is not halted on XferComplete interrupt so remains assigned to the endpoint(QH) until session is done.

++

Parameters:
++ ++ ++ ++
hcd The HCD state structure for the DWC OTG controller.
qh The QH to init.
++
++
Returns:
0 if successful, negative error code otherwise.
++ ++

++Definition at line 675 of file dwc_otg_hcd_ddma.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_otg_hcd_complete_xfer_ddma (dwc_otg_hcd_t *  hcd,
dwc_hc_t *  hc,
dwc_otg_hc_regs_t *  hc_regs,
dwc_otg_halt_status_e  halt_status 
)
++
++
++ ++

++This function is called from interrupt handlers. ++

++Scans the descriptor list, updates URB's status and calls completion routine for the URB if it's done. Releases the channel to be used by other transfers. In case of Isochronous endpoint the channel is not halted until the end of the session, i.e. QTD list is empty. If periodic channel released the FrameList is updated accordingly.

++Calls transaction selection routines to activate pending transfers.

++

Parameters:
++ ++ ++ ++ ++ ++
hcd The HCD state structure for the DWC OTG controller.
hc Host channel, the transfer is completed on.
hc_regs Host channel registers.
halt_status Reason the channel is being halted, or just XferComplete for isochronous transfer
++
++ ++

++

Todo:
Consider the case when period exceeds FrameList size. Frame Rollover interrupt should be used.
++ ++

++Definition at line 1042 of file dwc_otg_hcd_ddma.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int dwc_otg_hcd_qh_init_ddma (dwc_otg_hcd_t *  hcd,
dwc_otg_qh_t *  qh 
)
++
++
++ ++

++Initializes a QH structure's Descriptor DMA related members. ++

++Allocates memory for descriptor list. On first periodic QH, allocates memory for FrameList and enables periodic scheduling.

++

Parameters:
++ ++ ++ ++
hcd The HCD state structure for the DWC OTG controller.
qh The QH to init.
++
++
Returns:
0 if successful, negative error code otherwise.
++ ++

++Definition at line 294 of file dwc_otg_hcd_ddma.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_otg_hcd_qh_free_ddma (dwc_otg_hcd_t *  hcd,
dwc_otg_qh_t *  qh 
)
++
++
++ ++

++Frees descriptor list memory associated with the QH. ++

++If QH is periodic and the last, frees FrameList memory and disables periodic scheduling.

++

Parameters:
++ ++ ++ ++
hcd The HCD state structure for the DWC OTG controller.
qh The QH to init.
++
++ ++

++Definition at line 327 of file dwc_otg_hcd_ddma.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
static int dwc_frame_num_le (uint16_t  frame1,
uint16_t  frame2 
) [inline, static]
++
++
++ ++

++Returns true if _frame1 is less than or equal to _frame2. ++

++The comparison is done modulo DWC_HFNUM_MAX_FRNUM. This accounts for the rollover of the frame number when the max frame number is reached. ++

++Definition at line 708 of file dwc_otg_hcd.h. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
static int dwc_frame_num_gt (uint16_t  frame1,
uint16_t  frame2 
) [inline, static]
++
++
++ ++

++Returns true if _frame1 is greater than _frame2. ++

++The comparison is done modulo DWC_HFNUM_MAX_FRNUM. This accounts for the rollover of the frame number when the max frame number is reached. ++

++Definition at line 719 of file dwc_otg_hcd.h. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
static uint16_t dwc_frame_num_inc (uint16_t  frame,
uint16_t  inc 
) [inline, static]
++
++
++ ++

++Increments _frame by the amount specified by _inc. ++

++The addition is done modulo DWC_HFNUM_MAX_FRNUM. Returns the incremented value. ++

++Definition at line 730 of file dwc_otg_hcd.h. ++

++

++

Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__hcd__ddma_8c-source.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__hcd__ddma_8c-source.html 2013-07-26 19:31:21.000000000 +0000 +@@ -0,0 +1,1070 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_hcd_ddma.c Source File ++ ++ ++ ++ ++
++
++
++
++

dwc_otg_hcd_ddma.c

Go to the documentation of this file.
00001 /*==========================================================================
++00002  * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd_ddma.c $
++00003  * $Revision: #2 $
++00004  * $Date: 2009/04/21 $
++00005  * $Change: 1237473 $
++00006  *
++00007  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
++00008  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
++00009  * otherwise expressly agreed to in writing between Synopsys and you.
++00010  *
++00011  * The Software IS NOT an item of Licensed Software or Licensed Product under
++00012  * any End User Software License Agreement or Agreement for Licensed Product
++00013  * with Synopsys or any supplement thereto. You are permitted to use and
++00014  * redistribute this Software in source and binary forms, with or without
++00015  * modification, provided that redistributions of source code must retain this
++00016  * notice. You may not view, use, disclose, copy or distribute this file or
++00017  * any information contained herein except pursuant to this license grant from
++00018  * Synopsys. If you do not agree with this notice, including the disclaimer
++00019  * below, then you are not authorized to use the Software.
++00020  *
++00021  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
++00022  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++00023  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++00024  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
++00025  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++00026  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
++00027  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
++00028  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
++00029  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
++00030  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
++00031  * DAMAGE.
++00032  * ========================================================================== */
++00033 #ifndef DWC_DEVICE_ONLY
++00034 
++00039 #include "dwc_otg_hcd.h"
++00040 #include "dwc_otg_regs.h"
++00041                 
++00042                 
++00043 static inline uint8_t frame_list_idx(uint16_t frame)
++00044 {
++00045         return (frame & (MAX_FRLIST_EN_NUM - 1));
++00046 }
++00047 
++00048 static inline uint16_t desclist_idx_inc(uint16_t idx, uint16_t inc, uint8_t speed)
++00049 {
++00050         return (idx + inc) & 
++00051                 (((speed == DWC_OTG_EP_SPEED_HIGH) ? MAX_DMA_DESC_NUM_HS_ISOC : MAX_DMA_DESC_NUM_GENERIC) - 1);
++00052 }
++00053 
++00054 static inline uint16_t desclist_idx_dec(uint16_t idx, uint16_t inc, uint8_t speed)
++00055 {
++00056         return (idx - inc) & 
++00057                 (((speed == DWC_OTG_EP_SPEED_HIGH) ? MAX_DMA_DESC_NUM_HS_ISOC : MAX_DMA_DESC_NUM_GENERIC) - 1);
++00058 }
++00059 
++00060 static inline uint16_t max_desc_num(dwc_otg_qh_t * qh)
++00061 {
++00062         return (((qh->ep_type == UE_ISOCHRONOUS) && (qh->dev_speed == DWC_OTG_EP_SPEED_HIGH)) 
++00063                                                         ?
++00064                                                         MAX_DMA_DESC_NUM_HS_ISOC
++00065                                                         :
++00066                                                         MAX_DMA_DESC_NUM_GENERIC);
++00067 }
++00068 static inline uint16_t frame_incr_val(dwc_otg_qh_t * qh)
++00069 {
++00070         return ((qh->dev_speed == DWC_OTG_EP_SPEED_HIGH) 
++00071                                                 ? ((qh->interval + 8 - 1) / 8)
++00072                                                 :
++00073                                                 qh->interval);
++00074 }
++00075 
++00076 static int desc_list_alloc(dwc_otg_qh_t * qh)
++00077 {
++00078         int retval = 0;
++00079         
++00080         qh->desc_list = (dwc_otg_host_dma_desc_t *) 
++00081                                 dwc_dma_alloc(sizeof(dwc_otg_host_dma_desc_t) * max_desc_num(qh),
++00082                                               &qh->desc_list_dma
++00083                                               );
++00084         
++00085         if (!qh->desc_list) {
++00086                 retval = -DWC_E_NO_MEMORY;
++00087                 DWC_ERROR("%s: DMA descriptor list allocation failed\n", __func__);
++00088                 
++00089         }
++00090         
++00091         dwc_memset(qh->desc_list, 0x00, sizeof(dwc_otg_host_dma_desc_t) * max_desc_num(qh));
++00092          
++00093 
++00094         qh->n_bytes = (uint32_t *) dwc_alloc(sizeof(uint32_t) * max_desc_num(qh));
++00095         
++00096         if (!qh->n_bytes) {
++00097                 retval = -DWC_E_NO_MEMORY;
++00098                 DWC_ERROR("%s: Failed to allocate array for descriptors' size actual values\n",
++00099                           __func__);
++00100                 
++00101         }       
++00102         return retval;
++00103 
++00104 }
++00105 
++00106 static void desc_list_free(dwc_otg_qh_t * qh)
++00107 {
++00108         if(qh->desc_list) {
++00109                 dwc_dma_free(max_desc_num(qh), qh->desc_list, qh->desc_list_dma);
++00110                 qh->desc_list = NULL;
++00111         }
++00112         
++00113         if (qh->n_bytes) {
++00114                 dwc_free(qh->n_bytes);
++00115                 qh->n_bytes = NULL;
++00116         }
++00117 }
++00118 
++00119 static int frame_list_alloc(dwc_otg_hcd_t * hcd)
++00120 {
++00121         int retval = 0; 
++00122         if (hcd->frame_list)
++00123                 return 0;
++00124         
++00125         hcd->frame_list = dwc_dma_alloc(4 * MAX_FRLIST_EN_NUM,
++00126                                         &hcd->frame_list_dma
++00127                                         );
++00128         if (!hcd->frame_list) {
++00129                 retval = -DWC_E_NO_MEMORY;
++00130                 DWC_ERROR("%s: Frame List allocation failed\n", __func__);
++00131         }
++00132         
++00133         dwc_memset(hcd->frame_list, 0x00, 4 * MAX_FRLIST_EN_NUM);
++00134         
++00135         return retval;
++00136 }
++00137 
++00138 static void frame_list_free(dwc_otg_hcd_t * hcd)
++00139 {
++00140         if (!hcd->frame_list)
++00141                 return;
++00142         
++00143         dwc_dma_free(4 * MAX_FRLIST_EN_NUM, hcd->frame_list, hcd->frame_list_dma);
++00144         hcd->frame_list = NULL;
++00145 }
++00146 
++00147 static void per_sched_enable(dwc_otg_hcd_t * hcd, uint16_t fr_list_en)
++00148 {
++00149                 
++00150         hcfg_data_t hcfg;
++00151 
++00152         hcfg.d32 = dwc_read_reg32(&hcd->core_if->host_if->host_global_regs->hcfg);
++00153 
++00154         if (hcfg.b.perschedstat) {
++00155                 /* already enabled*/    
++00156                 return;
++00157         }
++00158         
++00159         dwc_write_reg32(&hcd->core_if->host_if->host_global_regs->hflbaddr, hcd->frame_list_dma);
++00160         
++00161         switch(fr_list_en) {
++00162         case 64:
++00163             hcfg.b.frlisten = 3;
++00164             break;
++00165         case 32:
++00166             hcfg.b.frlisten = 2;
++00167             break;
++00168         case 16:
++00169             hcfg.b.frlisten = 1;    
++00170         case 8:
++00171             hcfg.b.frlisten = 0;
++00172         default:
++00173             break;        
++00174         }
++00175         
++00176         hcfg.b.perschedena = 1;
++00177 
++00178         DWC_DEBUGPL(DBG_HCD, "Enabling Periodic schedule\n");
++00179         dwc_write_reg32(&hcd->core_if->host_if->host_global_regs->hcfg, hcfg.d32);
++00180 
++00181 }
++00182  
++00183 static void per_sched_disable(dwc_otg_hcd_t * hcd)
++00184 {
++00185         hcfg_data_t hcfg;
++00186 
++00187         hcfg.d32 = dwc_read_reg32(&hcd->core_if->host_if->host_global_regs->hcfg);
++00188         
++00189         if (!hcfg.b.perschedstat) {
++00190                 /* already disabled */  
++00191                 return;
++00192         }
++00193         hcfg.b.perschedena = 0;
++00194         
++00195         DWC_DEBUGPL(DBG_HCD, "Disabling Periodic schedule\n");
++00196         dwc_write_reg32(&hcd->core_if->host_if->host_global_regs->hcfg, hcfg.d32);
++00197 }
++00198 
++00199 /* 
++00200  * Activates/Deactivates FrameList entries for the channel 
++00201  * based on endpoint servicing period.
++00202  */
++00203 void update_frame_list(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh, uint8_t enable)
++00204 {
++00205         uint16_t i, j, inc;
++00206         dwc_hc_t *hc = qh->channel;
++00207         
++00208         inc = frame_incr_val(qh);
++00209         
++00210         if (qh->ep_type == UE_ISOCHRONOUS)
++00211                 i = frame_list_idx(qh->sched_frame);
++00212         else
++00213                 i = 0;
++00214 
++00215         j = i;
++00216         do {
++00217                 if (enable)
++00218                         hcd->frame_list[j] |= (1 << hc->hc_num);
++00219                 else
++00220                         hcd->frame_list[j] &= ~(1 << hc->hc_num);
++00221                 j = (j + inc) & (MAX_FRLIST_EN_NUM - 1);
++00222         }
++00223         while (j != i);
++00224         
++00225         if (!enable)
++00226                 return;
++00227         
++00228         hc->schinfo = 0;
++00229         if (qh->channel->speed == DWC_OTG_EP_SPEED_HIGH) {
++00230                 j = 1;
++00231                 for (i = 0 ; i < 8 / qh->interval; i++) {
++00232                         hc->schinfo |= j;
++00233                         j = j << qh->interval;
++00234                 }
++00235         }
++00236         else {
++00237                 hc->schinfo = 0xff;
++00238         }       
++00239 }               
++00240 #if 1
++00241 void dump_frame_list(dwc_otg_hcd_t * hcd)
++00242 {
++00243         int i = 0;
++00244         DWC_PRINTF("--FRAME LIST (hex) --\n");          
++00245         for (i = 0; i < MAX_FRLIST_EN_NUM; i++) {
++00246                 DWC_PRINTF("%x\t",hcd->frame_list[i]);
++00247                 if (!(i % 8) && i)    
++00248                         DWC_PRINTF("\n");
++00249         }
++00250         DWC_PRINTF("\n----\n");
++00251 
++00252 }
++00253 #endif
++00254 
++00255 static void release_channel_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
++00256 {
++00257         dwc_hc_t *hc = qh->channel;
++00258         if (dwc_qh_is_non_per(qh)) {
++00259                 hcd->non_periodic_channels--;                   
++00260         }
++00261         else {
++00262                 update_frame_list(hcd, qh, 0);
++00263         }
++00264         /* 
++00265          * The condition is added to prevent double cleanup try in case of device
++00266          * disconnect. See channel cleanup in dwc_otg_hcd_disconnect_cb().
++00267          */
++00268         if (hc->qh) {   
++00269                 dwc_otg_hc_cleanup(hcd->core_if, hc);
++00270                 DWC_CIRCLEQ_INSERT_TAIL(&hcd->free_hc_list, hc, hc_list_entry);
++00271                 hc->qh = NULL;
++00272         }
++00273         
++00274         qh->channel = NULL;
++00275         qh->ntd = 0;
++00276         
++00277         if (qh->desc_list) {
++00278                 dwc_memset(qh->desc_list, 0x00, 
++00279                             sizeof(dwc_otg_host_dma_desc_t) * max_desc_num(qh));
++00280         }
++00281 }
++00282 
++00294 int dwc_otg_hcd_qh_init_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
++00295 {
++00296         int retval = 0;
++00297         
++00298         if (qh->do_split) {
++00299                 DWC_ERROR("SPLIT Transfers are not supported in Descriptor DMA.\n");
++00300                 return -1;
++00301         }
++00302 
++00303         retval = desc_list_alloc(qh);
++00304         
++00305         if ((retval == 0) && (qh->ep_type == UE_ISOCHRONOUS || qh->ep_type == UE_INTERRUPT)) {
++00306                 if(!hcd->frame_list) {
++00307                         retval = frame_list_alloc(hcd); 
++00308                         /* Enable periodic schedule on first periodic QH */
++00309                         if (retval == 0)                
++00310                                 per_sched_enable(hcd, MAX_FRLIST_EN_NUM);
++00311                 }
++00312         }
++00313         
++00314         qh->ntd = 0;
++00315         
++00316         return retval;
++00317 }
++00318 
++00327 void dwc_otg_hcd_qh_free_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
++00328 {
++00329         desc_list_free(qh);
++00330 
++00331         /* 
++00332          * Channel still assigned due to some reasons. 
++00333          * Seen on Isoc URB dequeue. Channel halted but no subsequent
++00334          * ChHalted interrupt to release the channel. Afterwards
++00335          * when it comes here from endpoint disable routine
++00336          * channel remains assigned.
++00337          */
++00338         if (qh->channel)
++00339                 release_channel_ddma(hcd, qh);
++00340 
++00341         if ((qh->ep_type == UE_ISOCHRONOUS || qh->ep_type == UE_INTERRUPT) 
++00342                         && !hcd->periodic_channels && hcd->frame_list) {
++00343                 
++00344                 per_sched_disable(hcd); 
++00345                 frame_list_free(hcd);   
++00346         }
++00347 }       
++00348 
++00349 static uint8_t frame_to_desc_idx(dwc_otg_qh_t * qh, uint16_t frame_idx)
++00350 {
++00351         if (qh->dev_speed == DWC_OTG_EP_SPEED_HIGH) {
++00352                 /* 
++00353                  * Descriptor set(8 descriptors) index
++00354                  * which is 8-aligned.
++00355                  */     
++00356                 return (frame_idx & ((MAX_DMA_DESC_NUM_HS_ISOC / 8) - 1)) * 8;
++00357         }
++00358         else {
++00359                 return (frame_idx & (MAX_DMA_DESC_NUM_GENERIC - 1));
++00360         }       
++00361 }
++00362 
++00363 /* 
++00364  * Determine starting frame for Isochronous transfer. 
++00365  * Few frames skipped to prevent race condition with HC. 
++00366  */
++00367 static uint8_t calc_starting_frame(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh, uint8_t* skip_frames)
++00368 {
++00369         uint16_t frame = 0;
++00370         hcd->frame_number = dwc_otg_hcd_get_frame_number(hcd);
++00371         
++00372         /* sched_frame is always frame number(not uFrame) both in FS and HS !! */
++00373         
++00374         /* 
++00375          * skip_frames is used to limit activated descriptors number
++00376          * to avoid the situation when HC services the last activated
++00377          * descriptor firstly.
++00378          * Example for FS:
++00379          * Current frame is 1, scheduled frame is 3. Since HC always fetches the descriptor
++00380          * corresponding to curr_frame+1, the descriptor corresponding to frame 2
++00381          * will be fetched. If the number of descriptors is max=64 (or greather) the list will
++00382          * be fully programmed with Active descriptors and it is possible case(rare) that the latest 
++00383          * descriptor(considering rollback) corresponding to frame 2 will be serviced first.
++00384          * HS case is more probable because, in fact, up to 11 uframes(16 in the code)
++00385          * may be skipped.
++00386          */
++00387         if (qh->dev_speed == DWC_OTG_EP_SPEED_HIGH) {
++00388                 /* 
++00389                  * Consider uframe counter also, to start xfer asap.
++00390                  * If half of the frame elapsed skip 2 frames otherwise
++00391                  * just 1 frame. 
++00392                  * Starting descriptor index must be 8-aligned, so
++00393                  * if the current frame is near to complete the next one
++00394                  * is skipped as well.
++00395                  */
++00396                         
++00397                 if (dwc_micro_frame_num(hcd->frame_number)  >= 5) {
++00398                         *skip_frames = 2 * 8;
++00399                         frame = dwc_frame_num_inc(hcd->frame_number, *skip_frames);
++00400                 }       
++00401                 else {
++00402                         *skip_frames = 1 * 8;
++00403                         frame = dwc_frame_num_inc(hcd->frame_number, *skip_frames);
++00404                 }       
++00405                                  
++00406                 frame = dwc_full_frame_num(frame); 
++00407         } else {
++00408                 /* 
++00409                  * Two frames are skipped for FS - the current and the next.
++00410                  * But for descriptor programming, 1 frame(descriptor) is enough,
++00411                  * see example above.
++00412                  */
++00413                 *skip_frames = 1;        
++00414                 frame = dwc_frame_num_inc(hcd->frame_number, 2);
++00415         }
++00416         
++00417         return frame;
++00418 }
++00419 /* 
++00420  * Calculate initial descriptor index for isochronous transfer
++00421  * based on scheduled frame. 
++00422  */
++00423 static uint8_t recalc_initial_desc_idx(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
++00424 {
++00425         uint16_t frame = 0, fr_idx, fr_idx_tmp; 
++00426         uint8_t skip_frames = 0 ;
++00427         /* 
++00428          * With current ISOC processing algorithm the channel is being
++00429          * released when no more QTDs in the list(qh->ntd == 0).
++00430          * Thus this function is called only when qh->ntd == 0 and qh->channel == 0. 
++00431          *
++00432          * So qh->channel != NULL branch is not used and just not removed from the
++00433          * source file. It is required for another possible approach which is,
++00434          * do not disable and release the channel when ISOC session completed, 
++00435          * just move QH to inactive schedule until new QTD arrives. 
++00436          * On new QTD, the QH moved back to 'ready' schedule,
++00437          * starting frame and therefore starting desc_index are recalculated.
++00438          * In this case channel is released only on ep_disable.
++00439          */
++00440          
++00441         /* Calculate starting descriptor index. For INTERRUPT endpoint it is always 0. */
++00442         if (qh->channel) {
++00443                 frame = calc_starting_frame(hcd, qh, &skip_frames);     
++00444                 /* 
++00445                  * Calculate initial descriptor index based on FrameList current bitmap
++00446                  * and servicing period.
++00447                  */
++00448                 fr_idx_tmp = frame_list_idx(frame);
++00449                 fr_idx = (MAX_FRLIST_EN_NUM + frame_list_idx(qh->sched_frame) - fr_idx_tmp) 
++00450                                 % frame_incr_val(qh);
++00451                 fr_idx = (fr_idx + fr_idx_tmp) % MAX_FRLIST_EN_NUM;
++00452         }
++00453         else {
++00454                 qh->sched_frame = calc_starting_frame(hcd, qh, &skip_frames);   
++00455                 fr_idx = frame_list_idx(qh->sched_frame);
++00456         }
++00457         
++00458         qh->td_first = qh->td_last =  frame_to_desc_idx(qh, fr_idx);
++00459         
++00460         return skip_frames;
++00461 }
++00462  
++00463 #define ISOC_URB_GIVEBACK_ASAP
++00464  
++00465 #define MAX_ISOC_XFER_SIZE_FS 1023
++00466 #define MAX_ISOC_XFER_SIZE_HS 3072
++00467 #define DESCNUM_THRESHOLD 4
++00468 
++00469 static void init_isoc_dma_desc(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh, uint8_t skip_frames)
++00470 {
++00471         struct dwc_otg_hcd_iso_packet_desc *frame_desc;
++00472         dwc_otg_qtd_t *qtd;
++00473         dwc_otg_host_dma_desc_t *dma_desc;
++00474         uint16_t idx, inc, n_desc, ntd_max, max_xfer_size;
++00475         
++00476         idx = qh->td_last;
++00477         inc = qh->interval;
++00478         n_desc = 0;
++00479         
++00480         ntd_max = (max_desc_num(qh) + qh->interval - 1) / qh->interval;
++00481         if (skip_frames && !qh->channel)
++00482                 ntd_max = ntd_max - skip_frames / qh->interval; 
++00483         
++00484         max_xfer_size = (qh->dev_speed == DWC_OTG_EP_SPEED_HIGH) ? MAX_ISOC_XFER_SIZE_HS 
++00485                                                                  : MAX_ISOC_XFER_SIZE_FS;
++00486                         
++00487         DWC_CIRCLEQ_FOREACH(qtd, &qh->qtd_list, qtd_list_entry) {
++00488                 while ((qh->ntd < ntd_max) && (qtd->isoc_frame_index_last < qtd->urb->packet_count)) {
++00489                                 
++00490                         dma_desc = &qh->desc_list[idx];
++00491                         dwc_memset(dma_desc, 0x00, sizeof(dwc_otg_host_dma_desc_t));
++00492 
++00493                         frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index_last];
++00494                         
++00495                         if (frame_desc->length > max_xfer_size)
++00496                                 qh->n_bytes[idx] = max_xfer_size;
++00497                         else
++00498                                 qh->n_bytes[idx] = frame_desc->length;
++00499                         dma_desc->status.b_isoc.n_bytes = qh->n_bytes[idx];
++00500                         dma_desc->status.b_isoc.a = 1;
++00501                         
++00502                         dma_desc->buf = qtd->urb->dma + frame_desc->offset;
++00503                         
++00504                         qh->ntd++;
++00505 
++00506                         qtd->isoc_frame_index_last++;
++00507                         
++00508                 #ifdef  ISOC_URB_GIVEBACK_ASAP
++00509                         /* 
++00510                          * Set IOC for each descriptor corresponding to the 
++00511                          * last frame of the URB.
++00512                          */     
++00513                         if (qtd->isoc_frame_index_last == qtd->urb->packet_count)
++00514                                 dma_desc->status.b_isoc.ioc = 1;
++00515                         
++00516                 #endif  
++00517                         idx = desclist_idx_inc(idx, inc, qh->dev_speed);
++00518                         n_desc++;
++00519                         
++00520                 }
++00521                 qtd->in_process = 1;
++00522         }
++00523         
++00524         qh->td_last = idx;
++00525         
++00526 #ifdef  ISOC_URB_GIVEBACK_ASAP
++00527         /* Set IOC for the last descriptor if descriptor list is full */        
++00528         if (qh->ntd == ntd_max) {
++00529                 idx = desclist_idx_dec(qh->td_last, inc, qh->dev_speed);
++00530                 qh->desc_list[idx].status.b_isoc.ioc = 1;
++00531         }
++00532 #else   
++00533         /* 
++00534          * Set IOC bit only for one descriptor. 
++00535          * Always try to be ahead of HW processing,
++00536          * i.e. on IOC generation driver activates next descriptors but
++00537          * core continues to process descriptors followed the one with IOC set.
++00538          */
++00539 
++00540         if (n_desc > DESCNUM_THRESHOLD) {
++00541                 /* 
++00542                  * Move IOC "up". Required even if there is only one QTD 
++00543                  * in the list, cause QTDs migth continue to be queued,
++00544                  * but during the activation it was only one queued.
++00545                  * Actually more than one QTD might be in the list if this function called 
++00546                  * from XferCompletion - QTDs was queued during HW processing of the previous
++00547                  * descriptor chunk.
++00548                  */     
++00549                 idx = dwc_desclist_idx_dec(idx, inc * ((qh->ntd + 1) / 2), qh->dev_speed);
++00550         }
++00551         else {
++00552                 /* 
++00553                  * Set the IOC for the latest descriptor
++00554                  * if either number of descriptor is not greather than threshold
++00555                  * or no more new descriptors activated.
++00556                  */     
++00557                 idx = dwc_desclist_idx_dec(qh->td_last, inc, qh->dev_speed);
++00558         }
++00559         
++00560         qh->desc_list[idx].status.b_isoc.ioc = 1;
++00561 #endif
++00562 }
++00563 
++00564 
++00565 static void init_non_isoc_dma_desc(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
++00566 {
++00567 
++00568         dwc_hc_t *hc;
++00569         dwc_otg_host_dma_desc_t *dma_desc;
++00570         dwc_otg_qtd_t *qtd;
++00571         int     num_packets, len, n_desc = 0;
++00572         
++00573         hc =  qh->channel;
++00574          
++00575         /* 
++00576          * Start with hc->xfer_buff initialized in 
++00577          * assign_and_init_hc(), then if SG transfer consists of multiple URBs,
++00578          * this pointer re-assigned to the buffer of the currently processed QTD.
++00579          * For non-SG request there is always one QTD active.
++00580          */
++00581         
++00582         DWC_CIRCLEQ_FOREACH(qtd, &qh->qtd_list, qtd_list_entry) {
++00583                         
++00584                 if (n_desc) {
++00585                         /* SG request - more than 1 QTDs */
++00586                         hc->xfer_buff = (uint8_t *)qtd->urb->dma + qtd->urb->actual_length;
++00587                         hc->xfer_len = qtd->urb->length - qtd->urb->actual_length;
++00588                 }
++00589 
++00590                 qtd->n_desc = 0;
++00591                 
++00592                 do {
++00593                         dma_desc = &qh->desc_list[n_desc];
++00594                         len = hc->xfer_len;
++00595                         
++00596 
++00597                         if (len > MAX_DMA_DESC_SIZE)
++00598                                 len = MAX_DMA_DESC_SIZE - hc->max_packet + 1;
++00599                         
++00600                         if (hc->ep_is_in) {
++00601                                 if (len > 0) {
++00602                                         num_packets = (len + hc->max_packet - 1) / hc->max_packet;
++00603                                 }
++00604                                 else {
++00605                                         /* Need 1 packet for transfer length of 0. */
++00606                                         num_packets = 1;
++00607                                 }
++00608                                 /* Always program an integral # of max packets for IN transfers. */
++00609                                 len = num_packets * hc->max_packet;     
++00610                         }                               
++00611                                 
++00612                         dma_desc->status.b.n_bytes = len;
++00613                         
++00614                         qh->n_bytes[n_desc] = len;
++00615                         
++00616 
++00617                         if ((qh->ep_type == UE_CONTROL) && (qtd->control_phase == DWC_OTG_CONTROL_SETUP))
++00618                                 dma_desc->status.b.sup = 1; /* Setup Packet */
++00619                                 
++00620                         dma_desc->status.b.a = 1; /* Active descriptor */
++00621                         
++00622                         dma_desc->buf = (uint32_t) hc->xfer_buff;
++00623 
++00624                         /* 
++00625                          * Last descriptor(or single) of IN transfer 
++00626                          * with actual size less than MaxPacket.
++00627                          */
++00628                         if (len > hc->xfer_len) {
++00629                                 hc->xfer_len = 0;
++00630                         }
++00631                         else {
++00632                                 hc->xfer_buff += len;
++00633                                 hc->xfer_len -= len;
++00634                         }
++00635                         
++00636                         qtd->n_desc++;
++00637                         n_desc++;
++00638                 }
++00639                 while ((hc->xfer_len > 0) && (n_desc != MAX_DMA_DESC_NUM_GENERIC));
++00640                 
++00641 
++00642                 qtd->in_process = 1;
++00643                 
++00644                 if (n_desc == MAX_DMA_DESC_NUM_GENERIC)
++00645                         break;
++00646         }
++00647 
++00648         if (n_desc) {
++00649                 /* Request Transfer Complete interrupt for the last descriptor */
++00650                 qh->desc_list[n_desc-1].status.b.ioc = 1;
++00651                 /* End of List indicator */
++00652                 qh->desc_list[n_desc-1].status.b.eol = 1;
++00653                 
++00654                 hc->ntd = n_desc;
++00655         }
++00656 }
++00657 
++00675 void dwc_otg_hcd_start_xfer_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
++00676 {
++00677         /* Channel is already assigned */
++00678         dwc_hc_t *hc = qh->channel;
++00679         uint8_t skip_frames = 0;
++00680         
++00681         switch (hc->ep_type) {
++00682         case DWC_OTG_EP_TYPE_CONTROL:
++00683         case DWC_OTG_EP_TYPE_BULK:
++00684                 init_non_isoc_dma_desc(hcd, qh);
++00685                 
++00686                 dwc_otg_hc_start_transfer_ddma(hcd->core_if, hc);
++00687                 break;
++00688         case DWC_OTG_EP_TYPE_INTR:
++00689                 init_non_isoc_dma_desc(hcd, qh);
++00690                 
++00691                 update_frame_list(hcd, qh, 1);
++00692                 
++00693                 dwc_otg_hc_start_transfer_ddma(hcd->core_if, hc);
++00694                 break;
++00695         case DWC_OTG_EP_TYPE_ISOC:
++00696                         
++00697                 if(!qh->ntd)
++00698                         skip_frames = recalc_initial_desc_idx(hcd, qh);
++00699                 
++00700                 init_isoc_dma_desc(hcd, qh, skip_frames);
++00701 
++00702                 if (!hc->xfer_started) {
++00703 
++00704                         update_frame_list(hcd, qh, 1);
++00705                 
++00706                         /* 
++00707                          * Always set to max, instead of actual size.
++00708                          * Otherwise ntd will be changed with 
++00709                          * channel being enabled. Not recommended.
++00710                          *
++00711                          */     
++00712                         hc->ntd = max_desc_num(qh);
++00713                         /* Enable channel only once for ISOC */ 
++00714                         dwc_otg_hc_start_transfer_ddma(hcd->core_if, hc);
++00715                 }
++00716                 
++00717                 break;
++00718         default:
++00719                 
++00720                 break;
++00721         }
++00722 }
++00723 
++00724 static void complete_isoc_xfer_ddma(dwc_otg_hcd_t *hcd,
++00725                                    dwc_hc_t *hc,
++00726                                    dwc_otg_hc_regs_t *hc_regs,
++00727                                    dwc_otg_halt_status_e halt_status)
++00728 {
++00729         struct dwc_otg_hcd_iso_packet_desc      *frame_desc;            
++00730         dwc_otg_qtd_t                           *qtd, *qtd_tmp;
++00731         dwc_otg_qh_t                            *qh;
++00732         dwc_otg_host_dma_desc_t                 *dma_desc;
++00733         uint16_t                                idx, remain;
++00734         uint8_t                                 urb_compl;      
++00735         
++00736         qh = hc->qh;
++00737         idx = qh->td_first;
++00738         
++00739 
++00740         if (hc->halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE) {
++00741                 DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp, &hc->qh->qtd_list, qtd_list_entry)
++00742                         qtd->in_process = 0;
++00743                 return; 
++00744         }
++00745         else if ((halt_status == DWC_OTG_HC_XFER_AHB_ERR) || 
++00746                         (halt_status == DWC_OTG_HC_XFER_BABBLE_ERR)) {
++00747                 /* 
++00748                  * Channel is halted in these error cases.
++00749                  * Considered as serious issues.
++00750                  * Complete all URBs marking all frames as failed, 
++00751                  * irrespective whether some of the descriptors(frames) succeeded or no.
++00752                  * Pass error code to completion routine as well, to
++00753                  * update urb->status, some of class drivers might use it to stop
++00754                  * queing transfer requests.
++00755                  */     
++00756                 int err = (halt_status == DWC_OTG_HC_XFER_AHB_ERR) 
++00757                                                         ? (-DWC_E_IO)
++00758                                                         : (-DWC_E_OVERFLOW);
++00759                                                 
++00760                 DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp, &hc->qh->qtd_list, qtd_list_entry) {
++00761                         for(idx = 0; idx < qtd->urb->packet_count; idx++) {
++00762                                 frame_desc = &qtd->urb->iso_descs[idx];
++00763                                 frame_desc->status = err;
++00764                         }
++00765                         hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, err);
++00766                         dwc_otg_hcd_qtd_remove_and_free(hcd, qtd, qh);
++00767                 }
++00768                 return; 
++00769         }
++00770         
++00771         
++00772         DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp, &hc->qh->qtd_list, qtd_list_entry) {
++00773                 
++00774                 if (!qtd->in_process)
++00775                     break;
++00776                 
++00777                 urb_compl = 0;
++00778                 
++00779                 do {
++00780 
++00781                         dma_desc = &qh->desc_list[idx];
++00782                         
++00783                         frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index];
++00784                         remain = hc->ep_is_in ? dma_desc->status.b_isoc.n_bytes : 0;
++00785         
++00786                         if (dma_desc->status.b_isoc.sts == DMA_DESC_STS_PKTERR) {
++00787                                 /* 
++00788                                  * XactError or, unable to complete all the transactions 
++00789                                  * in the scheduled micro-frame/frame, 
++00790                                  * both indicated by DMA_DESC_STS_PKTERR.
++00791                                  */     
++00792                                 qtd->urb->error_count++;
++00793                                 frame_desc->actual_length = qh->n_bytes[idx] - remain;
++00794                                 frame_desc->status = -DWC_E_PROTOCOL;
++00795                         }
++00796                         else {
++00797                                 /* Success */   
++00798                                                                 
++00799                                 frame_desc->actual_length = qh->n_bytes[idx] - remain;
++00800                                 frame_desc->status = 0;
++00801                         }
++00802                         
++00803                         if (++qtd->isoc_frame_index == qtd->urb->packet_count) {
++00804                                 /*
++00805                                  * urb->status is not used for isoc transfers here.
++00806                                  * The individual frame_desc status are used instead.
++00807                                  */
++00808 
++00809                                 hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, 0);
++00810                                 dwc_otg_hcd_qtd_remove_and_free(hcd, qtd, qh);
++00811                                 
++00812                                 /* 
++00813                                  * This check is necessary because urb_dequeue can be called 
++00814                                  * from urb complete callback(sound driver example).
++00815                                  * All pending URBs are dequeued there, so no need for
++00816                                  * further processing.
++00817                                  */
++00818                                 if (hc->halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE) {   
++00819                                         return;
++00820                                 }
++00821                                 
++00822                                 urb_compl = 1;          
++00823                                 
++00824                         }
++00825                         
++00826                         qh->ntd--;
++00827                         
++00828                         /* Stop if IOC requested descriptor reached */
++00829                         if (dma_desc->status.b_isoc.ioc) {
++00830                                 idx = desclist_idx_inc(idx, qh->interval, hc->speed);   
++00831                                 goto stop_scan;
++00832                         }
++00833                         
++00834                         idx = desclist_idx_inc(idx, qh->interval, hc->speed);
++00835                         
++00836                         if (urb_compl)
++00837                                 break;
++00838                 }
++00839                 while(idx != qh->td_first);
++00840         }
++00841 stop_scan:      
++00842         qh->td_first = idx;
++00843 }
++00844         
++00845 uint8_t update_non_isoc_urb_state_ddma(dwc_otg_hcd_t * hcd,
++00846                            dwc_hc_t * hc,
++00847                            dwc_otg_qtd_t * qtd,
++00848                            dwc_otg_host_dma_desc_t * dma_desc,
++00849                            dwc_otg_halt_status_e halt_status,
++00850                            uint32_t n_bytes,
++00851                            uint8_t *xfer_done)
++00852 {
++00853 
++00854         uint16_t remain = hc->ep_is_in ? dma_desc->status.b.n_bytes : 0;
++00855         dwc_otg_hcd_urb_t *urb = qtd->urb;
++00856         
++00857         
++00858         if (halt_status == DWC_OTG_HC_XFER_AHB_ERR) {
++00859                 urb->status = -DWC_E_IO;
++00860                 return 1;
++00861         }
++00862         if (dma_desc->status.b.sts == DMA_DESC_STS_PKTERR) {
++00863                 switch (halt_status) {
++00864                 case DWC_OTG_HC_XFER_STALL:
++00865                         urb->status = -DWC_E_PIPE;
++00866                         break;
++00867                 case DWC_OTG_HC_XFER_BABBLE_ERR:
++00868                         urb->status = -DWC_E_OVERFLOW;
++00869                         break;
++00870                 case DWC_OTG_HC_XFER_XACT_ERR:
++00871                         urb->status = -DWC_E_PROTOCOL;
++00872                         break;
++00873                 default:        
++00874                         DWC_ERROR("%s: Unhandled descriptor error status (%d)\n", __func__,
++00875                                   halt_status);
++00876                         break;
++00877                 }
++00878                 return 1;
++00879         }
++00880         
++00881         if (dma_desc->status.b.a == 1) {
++00882                 DWC_DEBUGPL(DBG_HCDV, "Active descriptor encountered on channel %d\n", hc->hc_num);
++00883                 return 0;
++00884         }
++00885         
++00886         if (hc->ep_type == DWC_OTG_EP_TYPE_CONTROL) {
++00887             if (qtd->control_phase == DWC_OTG_CONTROL_DATA) {
++00888                 urb->actual_length += n_bytes - remain;
++00889                 if (remain || urb->actual_length == urb->length) {
++00890                         /* 
++00891                          * For Control Data stage do not set urb->status=0 to prevent
++00892                          * URB callback. Set it when Status phase done. See below.
++00893                          */
++00894                         *xfer_done = 1;
++00895                 }               
++00896             
++00897             }
++00898             else if (qtd->control_phase == DWC_OTG_CONTROL_STATUS) {
++00899                 urb->status = 0;
++00900                 *xfer_done = 1;
++00901             }
++00902             /* No handling for SETUP stage */
++00903 
++00904         }
++00905         else { 
++00906             /* BULK and INTR */
++00907             urb->actual_length += n_bytes - remain;
++00908             if (remain || urb->actual_length == urb->length) {
++00909                 urb->status = 0;
++00910                 *xfer_done = 1;
++00911             }
++00912         }
++00913 
++00914         return 0;
++00915 }
++00916 
++00917 static void complete_non_isoc_xfer_ddma(dwc_otg_hcd_t * hcd,
++00918                                         dwc_hc_t * hc,
++00919                                         dwc_otg_hc_regs_t * hc_regs,
++00920                                         dwc_otg_halt_status_e halt_status)
++00921 {
++00922         dwc_otg_hcd_urb_t       *urb = NULL;
++00923         dwc_otg_qtd_t           *qtd, *qtd_tmp;
++00924         dwc_otg_qh_t            *qh;
++00925         dwc_otg_host_dma_desc_t *dma_desc;
++00926         uint32_t                n_bytes, n_desc, i;
++00927         uint8_t                 failed = 0, xfer_done;
++00928         
++00929         n_desc = 0;
++00930         
++00931         qh = hc->qh;
++00932 
++00933         
++00934         if (hc->halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE) {
++00935                 DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp, &hc->qh->qtd_list, qtd_list_entry) {
++00936                         qtd->in_process = 0;
++00937                 }
++00938                 return;
++00939         }
++00940         
++00941         DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp, &qh->qtd_list, qtd_list_entry) {
++00942                 
++00943                 urb = qtd->urb;
++00944 
++00945                 n_bytes = 0; 
++00946                 xfer_done = 0; 
++00947                 
++00948                 for (i = 0; i < qtd->n_desc; i++) {
++00949                         dma_desc = &qh->desc_list[n_desc];
++00950                 
++00951                         n_bytes = qh->n_bytes[n_desc];
++00952                         
++00953                         
++00954                         failed = update_non_isoc_urb_state_ddma(hcd, hc, qtd, dma_desc, 
++00955                                                                 halt_status, n_bytes, &xfer_done);
++00956                         
++00957                         if (failed || (xfer_done && (urb->status != -DWC_E_IN_PROGRESS))) {
++00958                                 
++00959                                 hcd->fops->complete(hcd, urb->priv, urb, urb->status);
++00960                                 dwc_otg_hcd_qtd_remove_and_free(hcd, qtd, qh);
++00961 
++00962                                 if (failed)
++00963                                         goto stop_scan;
++00964                         }
++00965                         else if (qh->ep_type == UE_CONTROL) {
++00966                                 if (qtd->control_phase == DWC_OTG_CONTROL_SETUP) {
++00967                                         if (urb->length > 0) {
++00968                                                 qtd->control_phase = DWC_OTG_CONTROL_DATA;
++00969                                         } else {
++00970                                                 qtd->control_phase = DWC_OTG_CONTROL_STATUS;
++00971                                         }
++00972                                         DWC_DEBUGPL(DBG_HCDV, "  Control setup transaction done\n");
++00973                                 }
++00974                                 else if(qtd->control_phase == DWC_OTG_CONTROL_DATA) {
++00975                                         if (xfer_done) {
++00976                                                 qtd->control_phase = DWC_OTG_CONTROL_STATUS;
++00977                                                 DWC_DEBUGPL(DBG_HCDV, "  Control data transfer done\n");
++00978                                         } else if (i+1 == qtd->n_desc){
++00979                                                 /* 
++00980                                                  * Last descriptor for Control data stage which is
++00981                                                  * not completed yet.
++00982                                                  */     
++00983                                                 dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
++00984                                         }
++00985                                 }
++00986                         }
++00987                         
++00988                         n_desc++;
++00989                 }
++00990                 
++00991         }
++00992         
++00993 stop_scan:      
++00994         
++00995         if (qh->ep_type != UE_CONTROL) {
++00996                 /* 
++00997                  * Resetting the data toggle for bulk
++00998                  * and interrupt endpoints in case of stall. See handle_hc_stall_intr() 
++00999                  */     
++01000                 if (halt_status == DWC_OTG_HC_XFER_STALL) {     
++01001                         qh->data_toggle = DWC_OTG_HC_PID_DATA0; 
++01002                 }
++01003                 else {
++01004                         dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
++01005                 }
++01006         }
++01007         
++01008         if (halt_status == DWC_OTG_HC_XFER_COMPLETE) {
++01009                 hcint_data_t hcint;
++01010                 hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
++01011                 if (hcint.b.nyet) {
++01012                         /*
++01013                          * Got a NYET on the last transaction of the transfer. It
++01014                          * means that the endpoint should be in the PING state at the
++01015                          * beginning of the next transfer.
++01016                          */
++01017                         qh->ping_state = 1;
++01018                         clear_hc_int(hc_regs, nyet);
++01019                 }
++01020 
++01021         }
++01022 
++01023 }
++01024 
++01042 void dwc_otg_hcd_complete_xfer_ddma(dwc_otg_hcd_t *hcd,
++01043                             dwc_hc_t *hc,
++01044                             dwc_otg_hc_regs_t *hc_regs,
++01045                             dwc_otg_halt_status_e halt_status)
++01046 {
++01047         uint8_t continue_isoc_xfer = 0;
++01048         dwc_otg_transaction_type_e tr_type;
++01049         dwc_otg_qh_t *qh = hc->qh;
++01050         
++01051         if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
++01052 
++01053                 complete_isoc_xfer_ddma(hcd, hc, hc_regs, halt_status);
++01054                 
++01055                 /* Release the channel if halted or session completed */        
++01056                 if (halt_status != DWC_OTG_HC_XFER_COMPLETE ||
++01057                                 DWC_CIRCLEQ_EMPTY(&qh->qtd_list)) {
++01058 
++01059                         /* Halt the channel if session completed */     
++01060                         if (halt_status == DWC_OTG_HC_XFER_COMPLETE) {
++01061                                 dwc_otg_hc_halt(hcd->core_if, hc, halt_status);
++01062                         }       
++01063                         
++01064                         release_channel_ddma(hcd, qh);
++01065                         dwc_otg_hcd_qh_remove(hcd, qh);
++01066                 }
++01067                 else {
++01068                         /* Keep in assigned schedule to continue transfer */
++01069                         DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_assigned,
++01070                                            &qh->qh_list_entry);
++01071                         continue_isoc_xfer = 1;
++01072                                 
++01073                 }
++01077         }
++01078         else {
++01079                 /* Scan descriptor list to complete the URB(s), then release the channel */     
++01080                 complete_non_isoc_xfer_ddma(hcd, hc, hc_regs, halt_status);
++01081                 
++01082                 release_channel_ddma(hcd, qh);
++01083                 
++01084                 dwc_otg_hcd_qh_remove(hcd, qh);
++01085                 
++01086                 if (!DWC_CIRCLEQ_EMPTY(&qh->qtd_list)) {
++01087                         /* Add back to inactive non-periodic schedule on normal completion */
++01088                         dwc_otg_hcd_qh_add(hcd, qh);
++01089                 }
++01090         
++01091 
++01092         }
++01093         tr_type = dwc_otg_hcd_select_transactions(hcd);
++01094         if (tr_type != DWC_OTG_TRANSACTION_NONE || continue_isoc_xfer) {
++01095                 if (continue_isoc_xfer) {
++01096                         if (tr_type == DWC_OTG_TRANSACTION_NONE) {
++01097                                 tr_type = DWC_OTG_TRANSACTION_PERIODIC;
++01098                         } else if (tr_type == DWC_OTG_TRANSACTION_NON_PERIODIC) {
++01099                                 tr_type = DWC_OTG_TRANSACTION_ALL;
++01100                         }
++01101                 }
++01102                 dwc_otg_hcd_queue_transactions(hcd, tr_type);
++01103         }
++01104 }
++01105         
++01106 #endif  /* DWC_DEVICE_ONLY */
++
Generated on Tue May 5 02:22:48 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__hcd__ddma_8c.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__hcd__ddma_8c.html 2013-07-26 19:31:21.000000000 +0000 +@@ -0,0 +1,311 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_hcd_ddma.c File Reference ++ ++ ++ ++ ++
++
++
++
++

dwc_otg_hcd_ddma.c File Reference

This file contains Descriptor DMA support implementation for host mode. More... ++

++#include "dwc_otg_hcd.h"
++#include "dwc_otg_regs.h"
++ ++

++Go to the source code of this file. ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++

Defines

++#define ISOC_URB_GIVEBACK_ASAP
++#define MAX_ISOC_XFER_SIZE_FS   1023
++#define MAX_ISOC_XFER_SIZE_HS   3072
++#define DESCNUM_THRESHOLD   4

Functions

++static uint8_t frame_list_idx (uint16_t frame)
++static uint16_t desclist_idx_inc (uint16_t idx, uint16_t inc, uint8_t speed)
++static uint16_t desclist_idx_dec (uint16_t idx, uint16_t inc, uint8_t speed)
++static uint16_t max_desc_num (dwc_otg_qh_t *qh)
++static uint16_t frame_incr_val (dwc_otg_qh_t *qh)
++static int desc_list_alloc (dwc_otg_qh_t *qh)
++static void desc_list_free (dwc_otg_qh_t *qh)
++static int frame_list_alloc (dwc_otg_hcd_t *hcd)
++static void frame_list_free (dwc_otg_hcd_t *hcd)
++static void per_sched_enable (dwc_otg_hcd_t *hcd, uint16_t fr_list_en)
++static void per_sched_disable (dwc_otg_hcd_t *hcd)
++void update_frame_list (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh, uint8_t enable)
++void dump_frame_list (dwc_otg_hcd_t *hcd)
++static void release_channel_ddma (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
int dwc_otg_hcd_qh_init_ddma (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
 Initializes a QH structure's Descriptor DMA related members.
void dwc_otg_hcd_qh_free_ddma (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
 Frees descriptor list memory associated with the QH.
++static uint8_t frame_to_desc_idx (dwc_otg_qh_t *qh, uint16_t frame_idx)
++static uint8_t calc_starting_frame (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh, uint8_t *skip_frames)
++static uint8_t recalc_initial_desc_idx (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
++static void init_isoc_dma_desc (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh, uint8_t skip_frames)
++static void init_non_isoc_dma_desc (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
void dwc_otg_hcd_start_xfer_ddma (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
 For Control and Bulk endpoints initializes descriptor list and starts the transfer.
++static void complete_isoc_xfer_ddma (dwc_otg_hcd_t *hcd, dwc_hc_t *hc, dwc_otg_hc_regs_t *hc_regs, dwc_otg_halt_status_e halt_status)
++uint8_t update_non_isoc_urb_state_ddma (dwc_otg_hcd_t *hcd, dwc_hc_t *hc, dwc_otg_qtd_t *qtd, dwc_otg_host_dma_desc_t *dma_desc, dwc_otg_halt_status_e halt_status, uint32_t n_bytes, uint8_t *xfer_done)
++static void complete_non_isoc_xfer_ddma (dwc_otg_hcd_t *hcd, dwc_hc_t *hc, dwc_otg_hc_regs_t *hc_regs, dwc_otg_halt_status_e halt_status)
void dwc_otg_hcd_complete_xfer_ddma (dwc_otg_hcd_t *hcd, dwc_hc_t *hc, dwc_otg_hc_regs_t *hc_regs, dwc_otg_halt_status_e halt_status)
 This function is called from interrupt handlers.
++

Detailed Description

++This file contains Descriptor DMA support implementation for host mode. ++

++ ++

++Definition in file dwc_otg_hcd_ddma.c.

Function Documentation

++ ++
++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int dwc_otg_hcd_qh_init_ddma (dwc_otg_hcd_t *  hcd,
dwc_otg_qh_t *  qh 
)
++
++
++ ++

++Initializes a QH structure's Descriptor DMA related members. ++

++Allocates memory for descriptor list. On first periodic QH, allocates memory for FrameList and enables periodic scheduling.

++

Parameters:
++ ++ ++ ++
hcd The HCD state structure for the DWC OTG controller.
qh The QH to init.
++
++
Returns:
0 if successful, negative error code otherwise.
++ ++

++Definition at line 294 of file dwc_otg_hcd_ddma.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_otg_hcd_qh_free_ddma (dwc_otg_hcd_t *  hcd,
dwc_otg_qh_t *  qh 
)
++
++
++ ++

++Frees descriptor list memory associated with the QH. ++

++If QH is periodic and the last, frees FrameList memory and disables periodic scheduling.

++

Parameters:
++ ++ ++ ++
hcd The HCD state structure for the DWC OTG controller.
qh The QH to init.
++
++ ++

++Definition at line 327 of file dwc_otg_hcd_ddma.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_otg_hcd_start_xfer_ddma (dwc_otg_hcd_t *  hcd,
dwc_otg_qh_t *  qh 
)
++
++
++ ++

++For Control and Bulk endpoints initializes descriptor list and starts the transfer. ++

++For Interrupt and Isochronous endpoints initializes descriptor list then updates FrameList, marking appropriate entries as active. In case of Isochronous, the starting descriptor index is calculated based on the scheduled frame, but only on the first transfer descriptor within a session. Then starts the transfer via enabling the channel. For Isochronous endpoint the channel is not halted on XferComplete interrupt so remains assigned to the endpoint(QH) until session is done.

++

Parameters:
++ ++ ++ ++
hcd The HCD state structure for the DWC OTG controller.
qh The QH to init.
++
++
Returns:
0 if successful, negative error code otherwise.
++ ++

++Definition at line 675 of file dwc_otg_hcd_ddma.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_otg_hcd_complete_xfer_ddma (dwc_otg_hcd_t *  hcd,
dwc_hc_t *  hc,
dwc_otg_hc_regs_t *  hc_regs,
dwc_otg_halt_status_e  halt_status 
)
++
++
++ ++

++This function is called from interrupt handlers. ++

++Scans the descriptor list, updates URB's status and calls completion routine for the URB if it's done. Releases the channel to be used by other transfers. In case of Isochronous endpoint the channel is not halted until the end of the session, i.e. QTD list is empty. If periodic channel released the FrameList is updated accordingly.

++Calls transaction selection routines to activate pending transfers.

++

Parameters:
++ ++ ++ ++ ++ ++
hcd The HCD state structure for the DWC OTG controller.
hc Host channel, the transfer is completed on.
hc_regs Host channel registers.
halt_status Reason the channel is being halted, or just XferComplete for isochronous transfer
++
++ ++

++

Todo:
Consider the case when period exceeds FrameList size. Frame Rollover interrupt should be used.
++ ++

++Definition at line 1042 of file dwc_otg_hcd_ddma.c. ++

++

++

Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__hcd__if_8h-source.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__hcd__if_8h-source.html 2013-07-26 19:31:21.000000000 +0000 +@@ -0,0 +1,191 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_hcd_if.h Source File ++ ++ ++ ++ ++
++
++
++
++

dwc_otg_hcd_if.h

Go to the documentation of this file.
00001 /* ==========================================================================
++00002  * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd_if.h $
++00003  * $Revision: #6 $
++00004  * $Date: 2009/04/21 $
++00005  * $Change: 1237474 $
++00006  *
++00007  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
++00008  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
++00009  * otherwise expressly agreed to in writing between Synopsys and you.
++00010  *
++00011  * The Software IS NOT an item of Licensed Software or Licensed Product under
++00012  * any End User Software License Agreement or Agreement for Licensed Product
++00013  * with Synopsys or any supplement thereto. You are permitted to use and
++00014  * redistribute this Software in source and binary forms, with or without
++00015  * modification, provided that redistributions of source code must retain this
++00016  * notice. You may not view, use, disclose, copy or distribute this file or
++00017  * any information contained herein except pursuant to this license grant from
++00018  * Synopsys. If you do not agree with this notice, including the disclaimer
++00019  * below, then you are not authorized to use the Software.
++00020  *
++00021  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
++00022  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++00023  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++00024  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
++00025  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++00026  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
++00027  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
++00028  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
++00029  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
++00030  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
++00031  * DAMAGE.
++00032  * ========================================================================== */
++00033 #ifndef DWC_DEVICE_ONLY
++00034 #ifndef __DWC_HCD_IF_H__
++00035 #define __DWC_HCD_IF_H__
++00036 
++00037 #include "dwc_otg_core_if.h"
++00038 
++00043 struct dwc_otg_hcd;
++00044 typedef struct dwc_otg_hcd dwc_otg_hcd_t;
++00045 
++00046 struct dwc_otg_hcd_urb;
++00047 typedef struct dwc_otg_hcd_urb dwc_otg_hcd_urb_t;
++00048 
++00053 typedef int (*dwc_otg_hcd_start_cb_t) (dwc_otg_hcd_t * hcd);
++00054 
++00056 typedef int (*dwc_otg_hcd_disconnect_cb_t) (dwc_otg_hcd_t * hcd);
++00057 
++00059 typedef int (*dwc_otg_hcd_hub_info_from_urb_cb_t) (dwc_otg_hcd_t * hcd,
++00060                                                    void *urb_handle,
++00061                                                    uint32_t * hub_addr,
++00062                                                    uint32_t * port_addr);
++00064 typedef int (*dwc_otg_hcd_speed_from_urb_cb_t) (dwc_otg_hcd_t * hcd,
++00065                                                 void *urb_handle);
++00066 
++00068 typedef int (*dwc_otg_hcd_complete_urb_cb_t) (dwc_otg_hcd_t * hcd,
++00069                                               void *urb_handle,
++00070                                               dwc_otg_hcd_urb_t * dwc_otg_urb,
++00071                                               int32_t status);
++00072 
++00074 typedef int (*dwc_otg_hcd_get_b_hnp_enable) (dwc_otg_hcd_t * hcd);
++00075 
++00076 struct dwc_otg_hcd_function_ops {
++00077         dwc_otg_hcd_start_cb_t start;
++00078         dwc_otg_hcd_disconnect_cb_t disconnect;
++00079         dwc_otg_hcd_hub_info_from_urb_cb_t hub_info;
++00080         dwc_otg_hcd_speed_from_urb_cb_t speed;
++00081         dwc_otg_hcd_complete_urb_cb_t complete;
++00082         dwc_otg_hcd_get_b_hnp_enable get_b_hnp_enable;
++00083 };
++00089 extern dwc_otg_hcd_t *dwc_otg_hcd_alloc_hcd(void);
++00090 
++00099 extern int dwc_otg_hcd_init(dwc_otg_hcd_t * hcd, dwc_otg_core_if_t * core_if);
++00100 
++00105 extern void dwc_otg_hcd_remove(dwc_otg_hcd_t * hcd);
++00106 
++00114 extern int32_t dwc_otg_hcd_handle_intr(dwc_otg_hcd_t * dwc_otg_hcd);
++00115 
++00122 extern void *dwc_otg_hcd_get_priv_data(dwc_otg_hcd_t * hcd);
++00123 
++00130 extern void dwc_otg_hcd_set_priv_data(dwc_otg_hcd_t * hcd, void *priv_data);
++00131 
++00141 extern int dwc_otg_hcd_start(dwc_otg_hcd_t * hcd,
++00142                              struct dwc_otg_hcd_function_ops *fops);
++00143 
++00150 extern void dwc_otg_hcd_stop(dwc_otg_hcd_t * hcd);
++00151 
++00165 extern int dwc_otg_hcd_hub_control(dwc_otg_hcd_t * dwc_otg_hcd,
++00166                                    uint16_t typeReq, uint16_t wValue,
++00167                                    uint16_t wIndex, uint8_t * buf,
++00168                                    uint16_t wLength);
++00169 
++00175 extern uint32_t dwc_otg_hcd_otg_port(dwc_otg_hcd_t * hcd);
++00176 
++00182 extern uint32_t dwc_otg_hcd_is_b_host(dwc_otg_hcd_t * hcd);
++00183 
++00189 extern int dwc_otg_hcd_get_frame_number(dwc_otg_hcd_t * hcd);
++00190 
++00196 extern void dwc_otg_hcd_dump_state(dwc_otg_hcd_t * hcd);
++00197 
++00206 extern void dwc_otg_hcd_dump_frrem(dwc_otg_hcd_t * hcd);
++00207 
++00219 extern int dwc_otg_hcd_send_lpm(dwc_otg_hcd_t * hcd, uint8_t devaddr,
++00220                                 uint8_t hird, uint8_t bRemoteWake);
++00221 
++00222 /* URB interface */
++00223 
++00232 extern dwc_otg_hcd_urb_t *dwc_otg_hcd_urb_alloc(dwc_otg_hcd_t * hcd,
++00233                                                 int iso_desc_count,
++00234                                                 int atomic_alloc);
++00235 
++00246 extern void dwc_otg_hcd_urb_set_pipeinfo(dwc_otg_hcd_urb_t * hcd_urb,
++00247                                          uint8_t devaddr, uint8_t ep_num,
++00248                                          uint8_t ep_type, uint8_t ep_dir,
++00249                                          uint16_t mps);
++00250 
++00251 /* Transfer flags */ 
++00252 #define URB_GIVEBACK_ASAP 0x1
++00253 #define URB_SEND_ZERO_PACKET 0x2
++00254 
++00269 extern void dwc_otg_hcd_urb_set_params(dwc_otg_hcd_urb_t * urb,
++00270                                        void *urb_handle, void *buf,
++00271                                        dwc_dma_t dma, uint32_t buflen, void *sp,
++00272                                        dwc_dma_t sp_dma, uint32_t flags,
++00273                                        uint16_t interval);
++00274 
++00279 extern uint32_t dwc_otg_hcd_urb_get_status(dwc_otg_hcd_urb_t * dwc_otg_urb);
++00280 
++00285 extern uint32_t dwc_otg_hcd_urb_get_actual_length(dwc_otg_hcd_urb_t *
++00286                                                   dwc_otg_urb);
++00287 
++00292 extern uint32_t dwc_otg_hcd_urb_get_error_count(dwc_otg_hcd_urb_t *
++00293                                                 dwc_otg_urb);
++00294 
++00302 extern void dwc_otg_hcd_urb_set_iso_desc_params(dwc_otg_hcd_urb_t * dwc_otg_urb,
++00303                                                 int desc_num, uint32_t offset,
++00304                                                 uint32_t length);
++00305 
++00311 extern uint32_t dwc_otg_hcd_urb_get_iso_desc_status(dwc_otg_hcd_urb_t *
++00312                                                     dwc_otg_urb, int desc_num);
++00313 
++00319 extern uint32_t dwc_otg_hcd_urb_get_iso_desc_actual_length(dwc_otg_hcd_urb_t *
++00320                                                            dwc_otg_urb,
++00321                                                            int desc_num);
++00322 
++00333 extern int dwc_otg_hcd_urb_enqueue(dwc_otg_hcd_t * dwc_otg_hcd,
++00334                                    dwc_otg_hcd_urb_t * dwc_otg_urb,
++00335                                    void **ep_handle);
++00336 
++00342 extern int dwc_otg_hcd_urb_dequeue(dwc_otg_hcd_t * dwc_otg_hcd,
++00343                                    dwc_otg_hcd_urb_t * dwc_otg_urb);
++00344 
++00355 extern int dwc_otg_hcd_endpoint_disable(dwc_otg_hcd_t * hcd, void *ep_handle,
++00356                                         int retry);
++00357 
++00363 extern int dwc_otg_hcd_is_status_changed(dwc_otg_hcd_t * hcd, int port);
++00364 
++00371 extern int dwc_otg_hcd_is_bandwidth_allocated(dwc_otg_hcd_t * hcd,
++00372                                               void *ep_handle);
++00373 
++00379 extern int dwc_otg_hcd_is_bandwidth_freed(dwc_otg_hcd_t * hcd, void *ep_handle);
++00380 
++00387 extern uint8_t dwc_otg_hcd_get_ep_bandwidth(dwc_otg_hcd_t * hcd,
++00388                                             void *ep_handle);
++00389 
++00392 #endif                          /* __DWC_HCD_IF_H__ */
++00393 #endif                          /* DWC_DEVICE_ONLY */
++
Generated on Tue May 5 02:22:48 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__hcd__if_8h.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__hcd__if_8h.html 2013-07-26 19:31:21.000000000 +0000 +@@ -0,0 +1,1381 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_hcd_if.h File Reference ++ ++ ++ ++ ++
++
++
++
++

dwc_otg_hcd_if.h File Reference

This file defines DWC_OTG HCD Core API. More... ++

++#include "dwc_otg_core_if.h"
++ ++

++Go to the source code of this file. ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++

Data Structures

struct  dwc_otg_hcd_function_ops

HCD Core API

++#define URB_GIVEBACK_ASAP   0x1
++#define URB_SEND_ZERO_PACKET   0x2
++dwc_otg_hcd_t * dwc_otg_hcd_alloc_hcd (void)
 This function allocates dwc_otg_hcd structure and returns pointer on it.
int dwc_otg_hcd_init (dwc_otg_hcd_t *hcd, dwc_otg_core_if_t *core_if)
 This function should be called to initiate HCD Core.
void dwc_otg_hcd_remove (dwc_otg_hcd_t *hcd)
 Frees HCD.
int32_t dwc_otg_hcd_handle_intr (dwc_otg_hcd_t *dwc_otg_hcd)
 This function should be called on every hardware interrupt.
void * dwc_otg_hcd_get_priv_data (dwc_otg_hcd_t *hcd)
 Returns private data set by dwc_otg_hcd_set_priv_data function.
void dwc_otg_hcd_set_priv_data (dwc_otg_hcd_t *hcd, void *priv_data)
 Set private data.
int dwc_otg_hcd_start (dwc_otg_hcd_t *hcd, struct dwc_otg_hcd_function_ops *fops)
 This function initializes the HCD Core.
void dwc_otg_hcd_stop (dwc_otg_hcd_t *hcd)
 Halts the DWC_otg host mode operations in a clean manner.
int dwc_otg_hcd_hub_control (dwc_otg_hcd_t *dwc_otg_hcd, uint16_t typeReq, uint16_t wValue, uint16_t wIndex, uint8_t *buf, uint16_t wLength)
 Handles hub class-specific requests.
uint32_t dwc_otg_hcd_otg_port (dwc_otg_hcd_t *hcd)
 Returns otg port number.
uint32_t dwc_otg_hcd_is_b_host (dwc_otg_hcd_t *hcd)
 Returns 1 if currently core is acting as B host, and 0 otherwise.
int dwc_otg_hcd_get_frame_number (dwc_otg_hcd_t *hcd)
 Returns current frame number.
void dwc_otg_hcd_dump_state (dwc_otg_hcd_t *hcd)
 Dumps hcd state.
void dwc_otg_hcd_dump_frrem (dwc_otg_hcd_t *hcd)
 Dump the average frame remaining at SOF.
int dwc_otg_hcd_send_lpm (dwc_otg_hcd_t *hcd, uint8_t devaddr, uint8_t hird, uint8_t bRemoteWake)
 Sends LPM transaction to the local device.
dwc_otg_hcd_urb_t * dwc_otg_hcd_urb_alloc (dwc_otg_hcd_t *hcd, int iso_desc_count, int atomic_alloc)
 Allocates memory for dwc_otg_hcd_urb structure.
void dwc_otg_hcd_urb_set_pipeinfo (dwc_otg_hcd_urb_t *hcd_urb, uint8_t devaddr, uint8_t ep_num, uint8_t ep_type, uint8_t ep_dir, uint16_t mps)
 Set pipe information in URB.
void dwc_otg_hcd_urb_set_params (dwc_otg_hcd_urb_t *urb, void *urb_handle, void *buf, dwc_dma_t dma, uint32_t buflen, void *sp, dwc_dma_t sp_dma, uint32_t flags, uint16_t interval)
 Sets dwc_otg_hcd_urb parameters.
uint32_t dwc_otg_hcd_urb_get_status (dwc_otg_hcd_urb_t *dwc_otg_urb)
 Gets status from dwc_otg_hcd_urb.
uint32_t dwc_otg_hcd_urb_get_actual_length (dwc_otg_hcd_urb_t *dwc_otg_urb)
 Gets actual length from dwc_otg_hcd_urb.
uint32_t dwc_otg_hcd_urb_get_error_count (dwc_otg_hcd_urb_t *dwc_otg_urb)
 Gets error count from dwc_otg_hcd_urb.
void dwc_otg_hcd_urb_set_iso_desc_params (dwc_otg_hcd_urb_t *dwc_otg_urb, int desc_num, uint32_t offset, uint32_t length)
 Set ISOC descriptor offset and length.
uint32_t dwc_otg_hcd_urb_get_iso_desc_status (dwc_otg_hcd_urb_t *dwc_otg_urb, int desc_num)
 Get status of ISOC descriptor, specified by desc_num.
uint32_t dwc_otg_hcd_urb_get_iso_desc_actual_length (dwc_otg_hcd_urb_t *dwc_otg_urb, int desc_num)
 Get actual length of ISOC descriptor, specified by desc_num.
int dwc_otg_hcd_urb_enqueue (dwc_otg_hcd_t *dwc_otg_hcd, dwc_otg_hcd_urb_t *dwc_otg_urb, void **ep_handle)
 Queue URB.
int dwc_otg_hcd_urb_dequeue (dwc_otg_hcd_t *dwc_otg_hcd, dwc_otg_hcd_urb_t *dwc_otg_urb)
 De-queue the specified URB.
int dwc_otg_hcd_endpoint_disable (dwc_otg_hcd_t *hcd, void *ep_handle, int retry)
 Frees resources in the DWC_otg controller related to a given endpoint.
int dwc_otg_hcd_is_status_changed (dwc_otg_hcd_t *hcd, int port)
 Returns 1 if status of specified port is changed and 0 otherwise.
int dwc_otg_hcd_is_bandwidth_allocated (dwc_otg_hcd_t *hcd, void *ep_handle)
 Call this function to check if bandwidth was allocated for specified endpoint.
int dwc_otg_hcd_is_bandwidth_freed (dwc_otg_hcd_t *hcd, void *ep_handle)
 Call this function to check if bandwidth was freed for specified endpoint.
uint8_t dwc_otg_hcd_get_ep_bandwidth (dwc_otg_hcd_t *hcd, void *ep_handle)
 Returns bandwidth allocated for specified endpoint in microseconds.

HCD Function Driver Callbacks

++typedef int(*) dwc_otg_hcd_start_cb_t (dwc_otg_hcd_t *hcd)
 This function is called whenever core switches to host mode.
++typedef int(*) dwc_otg_hcd_disconnect_cb_t (dwc_otg_hcd_t *hcd)
 This function is called when device has been disconnected.
++typedef int(*) dwc_otg_hcd_hub_info_from_urb_cb_t (dwc_otg_hcd_t *hcd, void *urb_handle, uint32_t *hub_addr, uint32_t *port_addr)
 Wrapper provides this function to HCD to core, so it can get hub information to which device is connected.
++typedef int(*) dwc_otg_hcd_speed_from_urb_cb_t (dwc_otg_hcd_t *hcd, void *urb_handle)
 Via this function HCD core gets device speed.
++typedef int(*) dwc_otg_hcd_complete_urb_cb_t (dwc_otg_hcd_t *hcd, void *urb_handle, dwc_otg_hcd_urb_t *dwc_otg_urb, int32_t status)
 This function is called when urb is completed.
++typedef int(*) dwc_otg_hcd_get_b_hnp_enable (dwc_otg_hcd_t *hcd)
 Via this function HCD core gets b_hnp_enable parameter.

Typedefs

++typedef dwc_otg_hcd dwc_otg_hcd_t
++typedef dwc_otg_hcd_urb dwc_otg_hcd_urb_t
++

Detailed Description

++This file defines DWC_OTG HCD Core API. ++

++ ++

++Definition in file dwc_otg_hcd_if.h.

Function Documentation

++ ++
++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int dwc_otg_hcd_init (dwc_otg_hcd_t *  hcd,
dwc_otg_core_if_t *  core_if 
)
++
++
++ ++

++This function should be called to initiate HCD Core. ++

++

Parameters:
++ ++ ++ ++
hcd The HCD
core_if The DWC_OTG Core
++
++Returns -DWC_E_NO_MEMORY if no enough memory. Returns 0 on success ++

++Definition at line 693 of file dwc_otg_hcd.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_otg_hcd_remove (dwc_otg_hcd_t *  hcd  ) 
++
++
++ ++

++Frees HCD. ++

++

Parameters:
++ ++ ++
hcd The HCD
++
++ ++

++Definition at line 778 of file dwc_otg_hcd.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int32_t dwc_otg_hcd_handle_intr (dwc_otg_hcd_t *  dwc_otg_hcd  ) 
++
++
++ ++

++This function should be called on every hardware interrupt. ++

++

Parameters:
++ ++ ++
dwc_otg_hcd The HCD
++
++Returns non zero if interrupt is handled Return 0 if interrupt is not handled ++

++

Todo:
Implement i2cintr handler.
++ ++

++Definition at line 43 of file dwc_otg_hcd_intr.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void* dwc_otg_hcd_get_priv_data (dwc_otg_hcd_t *  hcd  ) 
++
++
++ ++

++Returns private data set by dwc_otg_hcd_set_priv_data function. ++

++

Parameters:
++ ++ ++
hcd The HCD
++
++ ++

++Definition at line 2671 of file dwc_otg_hcd.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_otg_hcd_set_priv_data (dwc_otg_hcd_t *  hcd,
void *  priv_data 
)
++
++
++ ++

++Set private data. ++

++

Parameters:
++ ++ ++ ++
hcd The HCD
priv_data pointer to be stored in private data
++
++ ++

++Definition at line 2676 of file dwc_otg_hcd.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int dwc_otg_hcd_start (dwc_otg_hcd_t *  hcd,
struct dwc_otg_hcd_function_ops *  fops 
)
++
++
++ ++

++This function initializes the HCD Core. ++

++

Parameters:
++ ++ ++ ++
hcd The HCD
fops The Function Driver Operations data structure containing pointers to all callbacks.
++
++Returns -DWC_E_NO_DEVICE if Core is currently is in device mode. Returns 0 on success ++

++Definition at line 2656 of file dwc_otg_hcd.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_otg_hcd_stop (dwc_otg_hcd_t *  hcd  ) 
++
++
++ ++

++Halts the DWC_otg host mode operations in a clean manner. ++

++USB transfers are stopped. ++

++Definition at line 422 of file dwc_otg_hcd.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int dwc_otg_hcd_hub_control (dwc_otg_hcd_t *  dwc_otg_hcd,
uint16_t  typeReq,
uint16_t  wValue,
uint16_t  wIndex,
uint8_t *  buf,
uint16_t  wLength 
)
++
++
++ ++

++Handles hub class-specific requests. ++

++

Parameters:
++ ++ ++ ++ ++ ++ ++ ++
dwc_otg_hcd The HCD
typeReq Request Type
wValue wValue from control request
wIndex wIndex from control request
buf data buffer
wLength data buffer length
++
++Returns -DWC_E_INVALID if invalid argument is passed Returns 0 on success ++

++Definition at line 1905 of file dwc_otg_hcd.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
uint32_t dwc_otg_hcd_otg_port (dwc_otg_hcd_t *  hcd  ) 
++
++
++ ++

++Returns otg port number. ++

++

Parameters:
++ ++ ++
hcd The HCD
++
++ ++

++Definition at line 2681 of file dwc_otg_hcd.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
uint32_t dwc_otg_hcd_is_b_host (dwc_otg_hcd_t *  hcd  ) 
++
++
++ ++

++Returns 1 if currently core is acting as B host, and 0 otherwise. ++

++

Parameters:
++ ++ ++
hcd The HCD
++
++ ++

++Definition at line 2686 of file dwc_otg_hcd.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int dwc_otg_hcd_get_frame_number (dwc_otg_hcd_t *  hcd  ) 
++
++
++ ++

++Returns current frame number. ++

++

Parameters:
++ ++ ++
hcd The HCD
++
++ ++

++Definition at line 2643 of file dwc_otg_hcd.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_otg_hcd_dump_state (dwc_otg_hcd_t *  hcd  ) 
++
++
++ ++

++Dumps hcd state. ++

++

Parameters:
++ ++ ++
hcd The HCD
++
++ ++

++Definition at line 2815 of file dwc_otg_hcd.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_otg_hcd_dump_frrem (dwc_otg_hcd_t *  hcd  ) 
++
++
++ ++

++Dump the average frame remaining at SOF. ++

++This can be used to determine average interrupt latency. Frame remaining is also shown for start transfer and two additional sample points. Currently this function is not implemented.

++

Parameters:
++ ++ ++
hcd The HCD
++
++ ++

++Definition at line 2991 of file dwc_otg_hcd.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int dwc_otg_hcd_send_lpm (dwc_otg_hcd_t *  hcd,
uint8_t  devaddr,
uint8_t  hird,
uint8_t  bRemoteWake 
)
++
++
++ ++

++Sends LPM transaction to the local device. ++

++

Parameters:
++ ++ ++ ++ ++ ++
hcd The HCD
devaddr Device Address
hird Host initiated resume duration
bRemoteWake Value of bRemoteWake field in LPM transaction
++
++Returns negative value if sending LPM transaction was not succeeded. Returns 0 on success. ++
++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
dwc_otg_hcd_urb_t* dwc_otg_hcd_urb_alloc (dwc_otg_hcd_t *  hcd,
int  iso_desc_count,
int  atomic_alloc 
)
++
++
++ ++

++Allocates memory for dwc_otg_hcd_urb structure. ++

++Allocated memory should be freed by call dwc_free function.

++

Parameters:
++ ++ ++ ++ ++
hcd The HCD
iso_desc_count Count of ISOC descriptors
atomic_alloc Specefies whether to perform atomic allocation.
++
++ ++

++Definition at line 2698 of file dwc_otg_hcd.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_otg_hcd_urb_set_pipeinfo (dwc_otg_hcd_urb_t *  hcd_urb,
uint8_t  devaddr,
uint8_t  ep_num,
uint8_t  ep_type,
uint8_t  ep_dir,
uint16_t  mps 
)
++
++
++ ++

++Set pipe information in URB. ++

++

Parameters:
++ ++ ++ ++ ++ ++ ++ ++
hcd_urb DWC_OTG URB
devaddr Device Address
ep_num Endpoint Number
ep_type Endpoint Type
ep_dir Endpoint Direction
mps Max Packet Size
++
++ ++

++Definition at line 2717 of file dwc_otg_hcd.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_otg_hcd_urb_set_params (dwc_otg_hcd_urb_t *  urb,
void *  urb_handle,
void *  buf,
dwc_dma_t  dma,
uint32_t  buflen,
void *  sp,
dwc_dma_t  sp_dma,
uint32_t  flags,
uint16_t  interval 
)
++
++
++ ++

++Sets dwc_otg_hcd_urb parameters. ++

++

Parameters:
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
urb DWC_OTG URB allocated by dwc_otg_hcd_urb_alloc function.
urb_handle Unique handle for request, this will be passed back to function driver in completion callback.
buf The buffer for the data
dma The DMA buffer for the data
buflen Transfer length
sp Buffer for setup data
sp_dma DMA address of setup data buffer
flags Transfer flags
interval Polling interval for interrupt or isochronous transfers.
++
++ ++

++Definition at line 2730 of file dwc_otg_hcd.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
uint32_t dwc_otg_hcd_urb_get_status (dwc_otg_hcd_urb_t *  dwc_otg_urb  ) 
++
++
++ ++

++Gets status from dwc_otg_hcd_urb. ++

++

Parameters:
++ ++ ++
dwc_otg_urb DWC_OTG URB
++
++ ++

++Definition at line 2747 of file dwc_otg_hcd.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
uint32_t dwc_otg_hcd_urb_get_actual_length (dwc_otg_hcd_urb_t *  dwc_otg_urb  ) 
++
++
++ ++

++Gets actual length from dwc_otg_hcd_urb. ++

++

Parameters:
++ ++ ++
dwc_otg_urb DWC_OTG URB
++
++ ++

++Definition at line 2752 of file dwc_otg_hcd.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
uint32_t dwc_otg_hcd_urb_get_error_count (dwc_otg_hcd_urb_t *  dwc_otg_urb  ) 
++
++
++ ++

++Gets error count from dwc_otg_hcd_urb. ++

++Only for ISOC URBs

++

Parameters:
++ ++ ++
dwc_otg_urb DWC_OTG URB
++
++ ++

++Definition at line 2757 of file dwc_otg_hcd.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_otg_hcd_urb_set_iso_desc_params (dwc_otg_hcd_urb_t *  dwc_otg_urb,
int  desc_num,
uint32_t  offset,
uint32_t  length 
)
++
++
++ ++

++Set ISOC descriptor offset and length. ++

++

Parameters:
++ ++ ++ ++ ++ ++
dwc_otg_urb DWC_OTG URB
desc_num ISOC descriptor number
offset Offset from beginig of buffer.
length Transaction length
++
++ ++

++Definition at line 2762 of file dwc_otg_hcd.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
uint32_t dwc_otg_hcd_urb_get_iso_desc_status (dwc_otg_hcd_urb_t *  dwc_otg_urb,
int  desc_num 
)
++
++
++ ++

++Get status of ISOC descriptor, specified by desc_num. ++

++

Parameters:
++ ++ ++ ++
dwc_otg_urb DWC_OTG URB
desc_num ISOC descriptor number
++
++ ++

++Definition at line 2770 of file dwc_otg_hcd.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
uint32_t dwc_otg_hcd_urb_get_iso_desc_actual_length (dwc_otg_hcd_urb_t *  dwc_otg_urb,
int  desc_num 
)
++
++
++ ++

++Get actual length of ISOC descriptor, specified by desc_num. ++

++

Parameters:
++ ++ ++ ++
dwc_otg_urb DWC_OTG URB
desc_num ISOC descriptor number
++
++ ++

++Definition at line 2776 of file dwc_otg_hcd.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int dwc_otg_hcd_urb_enqueue (dwc_otg_hcd_t *  dwc_otg_hcd,
dwc_otg_hcd_urb_t *  dwc_otg_urb,
void **  ep_handle 
)
++
++
++ ++

++Queue URB. ++

++After transfer is completes, the complete callback will be called with the URB status

++

Parameters:
++ ++ ++ ++ ++
dwc_otg_hcd The HCD
dwc_otg_urb DWC_OTG URB
ep_handle Out parameter for returning endpoint handle
++
++Returns -DWC_E_NO_DEVICE if no device is connected. Returns -DWC_E_NO_MEMORY if there is no enough memory. Returns 0 on success. ++

++Definition at line 444 of file dwc_otg_hcd.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int dwc_otg_hcd_urb_dequeue (dwc_otg_hcd_t *  dwc_otg_hcd,
dwc_otg_hcd_urb_t *  dwc_otg_urb 
)
++
++
++ ++

++De-queue the specified URB. ++

++

Parameters:
++ ++ ++ ++
dwc_otg_hcd The HCD
dwc_otg_urb DWC_OTG URB
++
++ ++

++Definition at line 489 of file dwc_otg_hcd.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int dwc_otg_hcd_endpoint_disable (dwc_otg_hcd_t *  hcd,
void *  ep_handle,
int  retry 
)
++
++
++ ++

++Frees resources in the DWC_otg controller related to a given endpoint. ++

++Any URBs for the endpoint must already be dequeued.

++

Parameters:
++ ++ ++ ++ ++
hcd The HCD
ep_handle Endpoint handle, returned by dwc_otg_hcd_urb_enqueue function
retry Number of retries if there are queued transfers.
++
++Returns -DWC_E_INVALID if invalid arguments are passed. Returns 0 on success ++

++Definition at line 547 of file dwc_otg_hcd.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int dwc_otg_hcd_is_status_changed (dwc_otg_hcd_t *  hcd,
int  port 
)
++
++
++ ++

++Returns 1 if status of specified port is changed and 0 otherwise. ++

++

Parameters:
++ ++ ++ ++
hcd The HCD
port Port number
++
++ ++

++Definition at line 2611 of file dwc_otg_hcd.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int dwc_otg_hcd_is_bandwidth_allocated (dwc_otg_hcd_t *  hcd,
void *  ep_handle 
)
++
++
++ ++

++Call this function to check if bandwidth was allocated for specified endpoint. ++

++Only for ISOC and INTERRUPT endpoints.

++

Parameters:
++ ++ ++ ++
hcd The HCD
ep_handle Endpoint handle
++
++ ++

++Definition at line 2782 of file dwc_otg_hcd.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int dwc_otg_hcd_is_bandwidth_freed (dwc_otg_hcd_t *  hcd,
void *  ep_handle 
)
++
++
++ ++

++Call this function to check if bandwidth was freed for specified endpoint. ++

++

Parameters:
++ ++ ++ ++
hcd The HCD
ep_handle Endpoint handle
++
++ ++

++Definition at line 2795 of file dwc_otg_hcd.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
uint8_t dwc_otg_hcd_get_ep_bandwidth (dwc_otg_hcd_t *  hcd,
void *  ep_handle 
)
++
++
++ ++

++Returns bandwidth allocated for specified endpoint in microseconds. ++

++Only for ISOC and INTERRUPT endpoints.

++

Parameters:
++ ++ ++ ++
hcd The HCD
ep_handle Endpoint handle
++
++ ++

++Definition at line 2808 of file dwc_otg_hcd.c. ++

++

++

Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__hcd__intr_8c-source.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__hcd__intr_8c-source.html 2013-07-26 19:31:21.000000000 +0000 +@@ -0,0 +1,1873 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_hcd_intr.c Source File ++ ++ ++ ++ ++
++
++
++
++

dwc_otg_hcd_intr.c

Go to the documentation of this file.
00001 /* ==========================================================================
++00002  * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd_intr.c $
++00003  * $Revision: #77 $
++00004  * $Date: 2009/04/21 $
++00005  * $Change: 1237475 $
++00006  *
++00007  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
++00008  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
++00009  * otherwise expressly agreed to in writing between Synopsys and you.
++00010  *
++00011  * The Software IS NOT an item of Licensed Software or Licensed Product under
++00012  * any End User Software License Agreement or Agreement for Licensed Product
++00013  * with Synopsys or any supplement thereto. You are permitted to use and
++00014  * redistribute this Software in source and binary forms, with or without
++00015  * modification, provided that redistributions of source code must retain this
++00016  * notice. You may not view, use, disclose, copy or distribute this file or
++00017  * any information contained herein except pursuant to this license grant from
++00018  * Synopsys. If you do not agree with this notice, including the disclaimer
++00019  * below, then you are not authorized to use the Software.
++00020  *
++00021  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
++00022  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++00023  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++00024  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
++00025  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++00026  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
++00027  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
++00028  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
++00029  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
++00030  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
++00031  * DAMAGE.
++00032  * ========================================================================== */
++00033 #ifndef DWC_DEVICE_ONLY
++00034 
++00035 #include "dwc_otg_hcd.h"
++00036 #include "dwc_otg_regs.h"
++00037 
++00043 int32_t dwc_otg_hcd_handle_intr(dwc_otg_hcd_t * dwc_otg_hcd)
++00044 {
++00045         int retval = 0;
++00046 
++00047         dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;
++00048         gintsts_data_t gintsts;
++00049 #ifdef DEBUG
++00050         dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
++00051 #endif
++00052 
++00053         /* Check if HOST Mode */
++00054         if (dwc_otg_is_host_mode(core_if)) {
++00055                 gintsts.d32 = dwc_otg_read_core_intr(core_if);
++00056                 if (!gintsts.d32) {
++00057                         return 0;
++00058                 }
++00059 #ifdef DEBUG
++00060                 /* Don't print debug message in the interrupt handler on SOF */
++00061 #ifndef DEBUG_SOF
++00062                 if (gintsts.d32 != DWC_SOF_INTR_MASK)
++00063 #endif
++00064                         DWC_DEBUGPL(DBG_HCD, "\n");
++00065 #endif
++00066 
++00067 #ifdef DEBUG
++00068 #ifndef DEBUG_SOF
++00069                 if (gintsts.d32 != DWC_SOF_INTR_MASK)
++00070 #endif
++00071                         DWC_DEBUGPL(DBG_HCD,
++00072                                     "DWC OTG HCD Interrupt Detected gintsts&gintmsk=0x%08x\n",
++00073                                     gintsts.d32);
++00074 #endif
++00075 
++00076                 if (gintsts.b.sofintr) {
++00077                         retval |= dwc_otg_hcd_handle_sof_intr(dwc_otg_hcd);
++00078                 }
++00079                 if (gintsts.b.rxstsqlvl) {
++00080                         retval |=
++00081                             dwc_otg_hcd_handle_rx_status_q_level_intr
++00082                             (dwc_otg_hcd);
++00083                 }
++00084                 if (gintsts.b.nptxfempty) {
++00085                         retval |=
++00086                             dwc_otg_hcd_handle_np_tx_fifo_empty_intr
++00087                             (dwc_otg_hcd);
++00088                 }
++00089                 if (gintsts.b.i2cintr) {
++00091                 }
++00092                 if (gintsts.b.portintr) {
++00093                         retval |= dwc_otg_hcd_handle_port_intr(dwc_otg_hcd);
++00094                 }
++00095                 if (gintsts.b.hcintr) {
++00096                         retval |= dwc_otg_hcd_handle_hc_intr(dwc_otg_hcd);
++00097                 }
++00098                 if (gintsts.b.ptxfempty) {
++00099                         retval |=
++00100                             dwc_otg_hcd_handle_perio_tx_fifo_empty_intr
++00101                             (dwc_otg_hcd);
++00102                 }
++00103 #ifdef DEBUG
++00104 #ifndef DEBUG_SOF
++00105                 if (gintsts.d32 != DWC_SOF_INTR_MASK)
++00106 #endif
++00107                 {
++00108                         DWC_DEBUGPL(DBG_HCD,
++00109                                     "DWC OTG HCD Finished Servicing Interrupts\n");
++00110                         DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD gintsts=0x%08x\n",
++00111                                     dwc_read_reg32(&global_regs->gintsts));
++00112                         DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD gintmsk=0x%08x\n",
++00113                                     dwc_read_reg32(&global_regs->gintmsk));
++00114                 }
++00115 #endif
++00116 
++00117 #ifdef DEBUG
++00118 #ifndef DEBUG_SOF
++00119                 if (gintsts.d32 != DWC_SOF_INTR_MASK)
++00120 #endif
++00121                         DWC_DEBUGPL(DBG_HCD, "\n");
++00122 #endif
++00123 
++00124         }
++00125 
++00126         return retval;
++00127 }
++00128 
++00129 #ifdef DWC_TRACK_MISSED_SOFS
++00130 #warning Compiling code to track missed SOFs
++00131 #define FRAME_NUM_ARRAY_SIZE 1000
++00132 
++00135 static inline void track_missed_sofs(uint16_t curr_frame_number)
++00136 {
++00137         static uint16_t frame_num_array[FRAME_NUM_ARRAY_SIZE];
++00138         static uint16_t last_frame_num_array[FRAME_NUM_ARRAY_SIZE];
++00139         static int frame_num_idx = 0;
++00140         static uint16_t last_frame_num = DWC_HFNUM_MAX_FRNUM;
++00141         static int dumped_frame_num_array = 0;
++00142 
++00143         if (frame_num_idx < FRAME_NUM_ARRAY_SIZE) {
++00144                 if (((last_frame_num + 1) & DWC_HFNUM_MAX_FRNUM) !=
++00145                     curr_frame_number) {
++00146                         frame_num_array[frame_num_idx] = curr_frame_number;
++00147                         last_frame_num_array[frame_num_idx++] = last_frame_num;
++00148                 }
++00149         } else if (!dumped_frame_num_array) {
++00150                 int i;
++00151                 DWC_PRINTF("Frame     Last Frame\n");
++00152                 DWC_PRINTF("-----     ----------\n");
++00153                 for (i = 0; i < FRAME_NUM_ARRAY_SIZE; i++) {
++00154                         DWC_PRINTF("0x%04x    0x%04x\n",
++00155                                    frame_num_array[i], last_frame_num_array[i]);
++00156                 }
++00157                 dumped_frame_num_array = 1;
++00158         }
++00159         last_frame_num = curr_frame_number;
++00160 }
++00161 #endif
++00162 
++00169 int32_t dwc_otg_hcd_handle_sof_intr(dwc_otg_hcd_t * hcd)
++00170 {
++00171         hfnum_data_t hfnum;
++00172         dwc_list_link_t *qh_entry;
++00173         dwc_otg_qh_t *qh;
++00174         dwc_otg_transaction_type_e tr_type;
++00175         gintsts_data_t gintsts = {.d32 = 0 };
++00176 
++00177         hfnum.d32 =
++00178             dwc_read_reg32(&hcd->core_if->host_if->host_global_regs->hfnum);
++00179 
++00180 #ifdef DEBUG_SOF
++00181         DWC_DEBUGPL(DBG_HCD, "--Start of Frame Interrupt--\n");
++00182 #endif
++00183         hcd->frame_number = hfnum.b.frnum;
++00184 
++00185 #ifdef DEBUG
++00186         hcd->frrem_accum += hfnum.b.frrem;
++00187         hcd->frrem_samples++;
++00188 #endif
++00189 
++00190 #ifdef DWC_TRACK_MISSED_SOFS
++00191         track_missed_sofs(hcd->frame_number);
++00192 #endif
++00193         /* Determine whether any periodic QHs should be executed. */
++00194         qh_entry = DWC_LIST_FIRST(&hcd->periodic_sched_inactive);
++00195         while (qh_entry != &hcd->periodic_sched_inactive) {
++00196                 qh = DWC_LIST_ENTRY(qh_entry, dwc_otg_qh_t, qh_list_entry);
++00197                 qh_entry = qh_entry->next;
++00198                 if (dwc_frame_num_le(qh->sched_frame, hcd->frame_number)) {
++00199                         /*
++00200                          * Move QH to the ready list to be executed next
++00201                          * (micro)frame.
++00202                          */
++00203                         DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_ready,
++00204                                            &qh->qh_list_entry);
++00205                 }
++00206         }
++00207         tr_type = dwc_otg_hcd_select_transactions(hcd);
++00208         if (tr_type != DWC_OTG_TRANSACTION_NONE) {
++00209                 dwc_otg_hcd_queue_transactions(hcd, tr_type);
++00210         }
++00211 
++00212         /* Clear interrupt */
++00213         gintsts.b.sofintr = 1;
++00214         dwc_write_reg32(&hcd->core_if->core_global_regs->gintsts, gintsts.d32);
++00215 
++00216         return 1;
++00217 }
++00218 
++00222 int32_t dwc_otg_hcd_handle_rx_status_q_level_intr(dwc_otg_hcd_t * dwc_otg_hcd)
++00223 {
++00224         host_grxsts_data_t grxsts;
++00225         dwc_hc_t *hc = NULL;
++00226 
++00227         DWC_DEBUGPL(DBG_HCD, "--RxStsQ Level Interrupt--\n");
++00228 
++00229         grxsts.d32 =
++00230             dwc_read_reg32(&dwc_otg_hcd->core_if->core_global_regs->grxstsp);
++00231 
++00232         hc = dwc_otg_hcd->hc_ptr_array[grxsts.b.chnum];
++00233 
++00234         /* Packet Status */
++00235         DWC_DEBUGPL(DBG_HCDV, "    Ch num = %d\n", grxsts.b.chnum);
++00236         DWC_DEBUGPL(DBG_HCDV, "    Count = %d\n", grxsts.b.bcnt);
++00237         DWC_DEBUGPL(DBG_HCDV, "    DPID = %d, hc.dpid = %d\n", grxsts.b.dpid,
++00238                     hc->data_pid_start);
++00239         DWC_DEBUGPL(DBG_HCDV, "    PStatus = %d\n", grxsts.b.pktsts);
++00240 
++00241         switch (grxsts.b.pktsts) {
++00242         case DWC_GRXSTS_PKTSTS_IN:
++00243                 /* Read the data into the host buffer. */
++00244                 if (grxsts.b.bcnt > 0) {
++00245                         dwc_otg_read_packet(dwc_otg_hcd->core_if,
++00246                                             hc->xfer_buff, grxsts.b.bcnt);
++00247 
++00248                         /* Update the HC fields for the next packet received. */
++00249                         hc->xfer_count += grxsts.b.bcnt;
++00250                         hc->xfer_buff += grxsts.b.bcnt;
++00251                 }
++00252 
++00253         case DWC_GRXSTS_PKTSTS_IN_XFER_COMP:
++00254         case DWC_GRXSTS_PKTSTS_DATA_TOGGLE_ERR:
++00255         case DWC_GRXSTS_PKTSTS_CH_HALTED:
++00256                 /* Handled in interrupt, just ignore data */
++00257                 break;
++00258         default:
++00259                 DWC_ERROR("RX_STS_Q Interrupt: Unknown status %d\n",
++00260                           grxsts.b.pktsts);
++00261                 break;
++00262         }
++00263 
++00264         return 1;
++00265 }
++00266 
++00271 int32_t dwc_otg_hcd_handle_np_tx_fifo_empty_intr(dwc_otg_hcd_t * dwc_otg_hcd)
++00272 {
++00273         DWC_DEBUGPL(DBG_HCD, "--Non-Periodic TxFIFO Empty Interrupt--\n");
++00274         dwc_otg_hcd_queue_transactions(dwc_otg_hcd,
++00275                                        DWC_OTG_TRANSACTION_NON_PERIODIC);
++00276         return 1;
++00277 }
++00278 
++00283 int32_t dwc_otg_hcd_handle_perio_tx_fifo_empty_intr(dwc_otg_hcd_t * dwc_otg_hcd)
++00284 {
++00285         DWC_DEBUGPL(DBG_HCD, "--Periodic TxFIFO Empty Interrupt--\n");
++00286         dwc_otg_hcd_queue_transactions(dwc_otg_hcd,
++00287                                        DWC_OTG_TRANSACTION_PERIODIC);
++00288         return 1;
++00289 }
++00290 
++00294 int32_t dwc_otg_hcd_handle_port_intr(dwc_otg_hcd_t * dwc_otg_hcd)
++00295 {
++00296         int retval = 0;
++00297         hprt0_data_t hprt0;
++00298         hprt0_data_t hprt0_modify;
++00299 
++00300         hprt0.d32 = dwc_read_reg32(dwc_otg_hcd->core_if->host_if->hprt0);
++00301         hprt0_modify.d32 = dwc_read_reg32(dwc_otg_hcd->core_if->host_if->hprt0);
++00302 
++00303         /* Clear appropriate bits in HPRT0 to clear the interrupt bit in
++00304          * GINTSTS */
++00305 
++00306         hprt0_modify.b.prtena = 0;
++00307         hprt0_modify.b.prtconndet = 0;
++00308         hprt0_modify.b.prtenchng = 0;
++00309         hprt0_modify.b.prtovrcurrchng = 0;
++00310 
++00311         /* Port Connect Detected
++00312          * Set flag and clear if detected */
++00313         if (hprt0.b.prtconndet) {
++00314                 DWC_DEBUGPL(DBG_HCD, "--Port Interrupt HPRT0=0x%08x "
++00315                             "Port Connect Detected--\n", hprt0.d32);
++00316                 dwc_otg_hcd->flags.b.port_connect_status_change = 1;
++00317                 dwc_otg_hcd->flags.b.port_connect_status = 1;
++00318                 hprt0_modify.b.prtconndet = 1;
++00319 
++00320                 /* B-Device has connected, Delete the connection timer. */
++00321                 DWC_TIMER_CANCEL(dwc_otg_hcd->conn_timer);
++00322 
++00323                 /* The Hub driver asserts a reset when it sees port connect
++00324                  * status change flag */
++00325                 retval |= 1;
++00326         }
++00327 
++00328         /* Port Enable Changed
++00329          * Clear if detected - Set internal flag if disabled */
++00330         if (hprt0.b.prtenchng) {
++00331                 DWC_DEBUGPL(DBG_HCD, "  --Port Interrupt HPRT0=0x%08x "
++00332                             "Port Enable Changed--\n", hprt0.d32);
++00333                 hprt0_modify.b.prtenchng = 1;
++00334                 if (hprt0.b.prtena == 1) {
++00335                         int do_reset = 0;
++00336                         dwc_otg_core_params_t *params =
++00337                             dwc_otg_hcd->core_if->core_params;
++00338                         dwc_otg_core_global_regs_t *global_regs =
++00339                             dwc_otg_hcd->core_if->core_global_regs;
++00340                         dwc_otg_host_if_t *host_if =
++00341                             dwc_otg_hcd->core_if->host_if;
++00342 
++00343                         /* Check if we need to adjust the PHY clock speed for
++00344                          * low power and adjust it */
++00345                         if (params->host_support_fs_ls_low_power) {
++00346                                 gusbcfg_data_t usbcfg;
++00347 
++00348                                 usbcfg.d32 =
++00349                                     dwc_read_reg32(&global_regs->gusbcfg);
++00350 
++00351                                 if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_LOW_SPEED
++00352                                     || hprt0.b.prtspd ==
++00353                                     DWC_HPRT0_PRTSPD_FULL_SPEED) {
++00354                                         /*
++00355                                          * Low power
++00356                                          */
++00357                                         hcfg_data_t hcfg;
++00358                                         if (usbcfg.b.phylpwrclksel == 0) {
++00359                                                 /* Set PHY low power clock select for FS/LS devices */
++00360                                                 usbcfg.b.phylpwrclksel = 1;
++00361                                                 dwc_write_reg32(&global_regs->
++00362                                                                 gusbcfg,
++00363                                                                 usbcfg.d32);
++00364                                                 do_reset = 1;
++00365                                         }
++00366 
++00367                                         hcfg.d32 =
++00368                                             dwc_read_reg32(&host_if->
++00369                                                            host_global_regs->hcfg);
++00370 
++00371                                         if (hprt0.b.prtspd ==
++00372                                             DWC_HPRT0_PRTSPD_LOW_SPEED
++00373                                             && params->
++00374                                             host_ls_low_power_phy_clk ==
++00375                                             DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ)
++00376                                         {
++00377                                                 /* 6 MHZ */
++00378                                                 DWC_DEBUGPL(DBG_CIL,
++00379                                                             "FS_PHY programming HCFG to 6 MHz (Low Power)\n");
++00380                                                 if (hcfg.b.fslspclksel !=
++00381                                                     DWC_HCFG_6_MHZ) {
++00382                                                         hcfg.b.fslspclksel =
++00383                                                             DWC_HCFG_6_MHZ;
++00384                                                         dwc_write_reg32
++00385                                                             (&host_if->
++00386                                                              host_global_regs->
++00387                                                              hcfg, hcfg.d32);
++00388                                                         do_reset = 1;
++00389                                                 }
++00390                                         } else {
++00391                                                 /* 48 MHZ */
++00392                                                 DWC_DEBUGPL(DBG_CIL,
++00393                                                             "FS_PHY programming HCFG to 48 MHz ()\n");
++00394                                                 if (hcfg.b.fslspclksel !=
++00395                                                     DWC_HCFG_48_MHZ) {
++00396                                                         hcfg.b.fslspclksel =
++00397                                                             DWC_HCFG_48_MHZ;
++00398                                                         dwc_write_reg32
++00399                                                             (&host_if->
++00400                                                              host_global_regs->
++00401                                                              hcfg, hcfg.d32);
++00402                                                         do_reset = 1;
++00403                                                 }
++00404                                         }
++00405                                 } else {
++00406                                         /*
++00407                                          * Not low power
++00408                                          */
++00409                                         if (usbcfg.b.phylpwrclksel == 1) {
++00410                                                 usbcfg.b.phylpwrclksel = 0;
++00411                                                 dwc_write_reg32(&global_regs->
++00412                                                                 gusbcfg,
++00413                                                                 usbcfg.d32);
++00414                                                 do_reset = 1;
++00415                                         }
++00416                                 }
++00417 
++00418                                 if (do_reset) {
++00419                                         DWC_TASK_SCHEDULE(dwc_otg_hcd->
++00420                                                           reset_tasklet);
++00421                                 }
++00422                         }
++00423 
++00424                         if (!do_reset) {
++00425                                 /* Port has been enabled set the reset change flag */
++00426                                 dwc_otg_hcd->flags.b.port_reset_change = 1;
++00427                         }
++00428                 } else {
++00429                         dwc_otg_hcd->flags.b.port_enable_change = 1;
++00430                 }
++00431                 retval |= 1;
++00432         }
++00433 
++00435         if (hprt0.b.prtovrcurrchng) {
++00436                 DWC_DEBUGPL(DBG_HCD, "  --Port Interrupt HPRT0=0x%08x "
++00437                             "Port Overcurrent Changed--\n", hprt0.d32);
++00438                 dwc_otg_hcd->flags.b.port_over_current_change = 1;
++00439                 hprt0_modify.b.prtovrcurrchng = 1;
++00440                 retval |= 1;
++00441         }
++00442 
++00443         /* Clear Port Interrupts */
++00444         dwc_write_reg32(dwc_otg_hcd->core_if->host_if->hprt0, hprt0_modify.d32);
++00445 
++00446         return retval;
++00447 }
++00448 
++00453 int32_t dwc_otg_hcd_handle_hc_intr(dwc_otg_hcd_t * dwc_otg_hcd)
++00454 {
++00455         int i;
++00456         int retval = 0;
++00457         haint_data_t haint;
++00458 
++00459         /* Clear appropriate bits in HCINTn to clear the interrupt bit in
++00460          * GINTSTS */
++00461 
++00462         haint.d32 = dwc_otg_read_host_all_channels_intr(dwc_otg_hcd->core_if);
++00463 
++00464         for (i = 0; i < dwc_otg_hcd->core_if->core_params->host_channels; i++) {
++00465                 if (haint.b2.chint & (1 << i)) {
++00466                         retval |= dwc_otg_hcd_handle_hc_n_intr(dwc_otg_hcd, i);
++00467                 }
++00468         }
++00469 
++00470         return retval;
++00471 }
++00472 
++00473 
++00474 
++00485 static uint32_t get_actual_xfer_length(dwc_hc_t * hc,
++00486                                        dwc_otg_hc_regs_t * hc_regs,
++00487                                        dwc_otg_qtd_t * qtd,
++00488                                        dwc_otg_halt_status_e halt_status,
++00489                                        int *short_read)
++00490 {
++00491         hctsiz_data_t hctsiz;
++00492         uint32_t length;
++00493 
++00494         if (short_read != NULL) {
++00495                 *short_read = 0;
++00496         }
++00497         hctsiz.d32 = dwc_read_reg32(&hc_regs->hctsiz);
++00498 
++00499         if (halt_status == DWC_OTG_HC_XFER_COMPLETE) {
++00500                 if (hc->ep_is_in) {
++00501                         length = hc->xfer_len - hctsiz.b.xfersize;
++00502                         if (short_read != NULL) {
++00503                                 *short_read = (hctsiz.b.xfersize != 0);
++00504                         }
++00505                 } else if (hc->qh->do_split) {
++00506                         length = qtd->ssplit_out_xfer_count;
++00507                 } else {
++00508                         length = hc->xfer_len;
++00509                 }
++00510         } else {
++00511                 /*
++00512                  * Must use the hctsiz.pktcnt field to determine how much data
++00513                  * has been transferred. This field reflects the number of
++00514                  * packets that have been transferred via the USB. This is
++00515                  * always an integral number of packets if the transfer was
++00516                  * halted before its normal completion. (Can't use the
++00517                  * hctsiz.xfersize field because that reflects the number of
++00518                  * bytes transferred via the AHB, not the USB).
++00519                  */
++00520                 length =
++00521                     (hc->start_pkt_count - hctsiz.b.pktcnt) * hc->max_packet;
++00522         }
++00523 
++00524         return length;
++00525 }
++00526 
++00536 static int update_urb_state_xfer_comp(dwc_hc_t * hc,
++00537                                       dwc_otg_hc_regs_t * hc_regs,
++00538                                       dwc_otg_hcd_urb_t * urb,
++00539                                       dwc_otg_qtd_t * qtd)
++00540 {
++00541         int xfer_done = 0;
++00542         int short_read = 0;
++00543 
++00544         int xfer_length;
++00545 
++00546         xfer_length = get_actual_xfer_length(hc, hc_regs, qtd,                                               
++00547                                                      DWC_OTG_HC_XFER_COMPLETE,
++00548                                                      &short_read);
++00549 
++00550 
++00551         /* non DWORD-aligned buffer case handling. */
++00552         if (hc->align_buff && xfer_length && hc->ep_is_in) {
++00553                 dwc_memcpy(urb->buf + urb->actual_length, hc->qh->dw_align_buf, xfer_length);
++00554         }
++00555 
++00556         urb->actual_length += xfer_length;
++00557 
++00558         if(xfer_length && (hc->ep_type == DWC_OTG_EP_TYPE_BULK) &&
++00559            (urb->flags & URB_SEND_ZERO_PACKET) && (urb->actual_length == urb->length) &&
++00560            !(urb->length % hc->max_packet)) {
++00561                 xfer_done = 0;
++00562         } else if (short_read || urb->actual_length == urb->length) {
++00563                 xfer_done = 1;
++00564                 urb->status = 0;
++00565         }
++00566         
++00567 #ifdef DEBUG
++00568         {
++00569                 hctsiz_data_t hctsiz;
++00570                 hctsiz.d32 = dwc_read_reg32(&hc_regs->hctsiz);
++00571                 DWC_DEBUGPL(DBG_HCDV, "DWC_otg: %s: %s, channel %d\n",
++00572                             __func__, (hc->ep_is_in ? "IN" : "OUT"),
++00573                             hc->hc_num);
++00574                 DWC_DEBUGPL(DBG_HCDV, "  hc->xfer_len %d\n", hc->xfer_len);
++00575                 DWC_DEBUGPL(DBG_HCDV, "  hctsiz.xfersize %d\n",
++00576                             hctsiz.b.xfersize);
++00577                 DWC_DEBUGPL(DBG_HCDV, "  urb->transfer_buffer_length %d\n",
++00578                             urb->length);
++00579                 DWC_DEBUGPL(DBG_HCDV, "  urb->actual_length %d\n",
++00580                             urb->actual_length);
++00581                 DWC_DEBUGPL(DBG_HCDV, "  short_read %d, xfer_done %d\n",
++00582                             short_read, xfer_done);
++00583         }
++00584 #endif
++00585 
++00586         return xfer_done;
++00587 }
++00588 
++00589 /*
++00590  * Save the starting data toggle for the next transfer. The data toggle is
++00591  * saved in the QH for non-control transfers and it's saved in the QTD for
++00592  * control transfers.
++00593  */
++00594 void dwc_otg_hcd_save_data_toggle(dwc_hc_t * hc,
++00595                              dwc_otg_hc_regs_t * hc_regs, dwc_otg_qtd_t * qtd)
++00596 {
++00597         hctsiz_data_t hctsiz;
++00598         hctsiz.d32 = dwc_read_reg32(&hc_regs->hctsiz);
++00599 
++00600         if (hc->ep_type != DWC_OTG_EP_TYPE_CONTROL) {
++00601                 dwc_otg_qh_t *qh = hc->qh;
++00602                 if (hctsiz.b.pid == DWC_HCTSIZ_DATA0) {
++00603                         qh->data_toggle = DWC_OTG_HC_PID_DATA0;
++00604                 } else {
++00605                         qh->data_toggle = DWC_OTG_HC_PID_DATA1;
++00606                 }
++00607         } else {
++00608                 if (hctsiz.b.pid == DWC_HCTSIZ_DATA0) {
++00609                         qtd->data_toggle = DWC_OTG_HC_PID_DATA0;
++00610                 } else {
++00611                         qtd->data_toggle = DWC_OTG_HC_PID_DATA1;
++00612                 }
++00613         }
++00614 }
++00615 
++00625 static dwc_otg_halt_status_e
++00626 update_isoc_urb_state(dwc_otg_hcd_t * hcd,
++00627                       dwc_hc_t * hc,
++00628                       dwc_otg_hc_regs_t * hc_regs,
++00629                       dwc_otg_qtd_t * qtd, dwc_otg_halt_status_e halt_status)
++00630 {
++00631         dwc_otg_hcd_urb_t *urb = qtd->urb;
++00632         dwc_otg_halt_status_e ret_val = halt_status;
++00633         struct dwc_otg_hcd_iso_packet_desc *frame_desc;
++00634 
++00635         frame_desc = &urb->iso_descs[qtd->isoc_frame_index];
++00636         switch (halt_status) {
++00637         case DWC_OTG_HC_XFER_COMPLETE:
++00638                 frame_desc->status = 0;
++00639                 frame_desc->actual_length =
++00640                     get_actual_xfer_length(hc, hc_regs, qtd, halt_status, NULL);
++00641                     
++00642                 /* non DWORD-aligned buffer case handling. */
++00643                 if (hc->align_buff && frame_desc->actual_length && hc->ep_is_in) {
++00644                         dwc_memcpy(urb->buf + frame_desc->offset + qtd->isoc_split_offset, 
++00645                                    hc->qh->dw_align_buf, frame_desc->actual_length);
++00646                 }
++00647                 
++00648                 break;
++00649         case DWC_OTG_HC_XFER_FRAME_OVERRUN:
++00650                 urb->error_count++;
++00651                 if (hc->ep_is_in) {
++00652                         frame_desc->status = -DWC_E_NO_STREAM_RES;
++00653                 } else {
++00654                         frame_desc->status = -DWC_E_COMMUNICATION;
++00655                 }
++00656                 frame_desc->actual_length = 0;
++00657                 break;
++00658         case DWC_OTG_HC_XFER_BABBLE_ERR:
++00659                 urb->error_count++;
++00660                 frame_desc->status = -DWC_E_OVERFLOW;
++00661                 /* Don't need to update actual_length in this case. */
++00662                 break;
++00663         case DWC_OTG_HC_XFER_XACT_ERR:
++00664                 urb->error_count++;
++00665                 frame_desc->status = -DWC_E_PROTOCOL;
++00666                 frame_desc->actual_length =
++00667                     get_actual_xfer_length(hc, hc_regs, qtd, halt_status, NULL);
++00668                 
++00669                 /* non DWORD-aligned buffer case handling. */
++00670                 if (hc->align_buff && frame_desc->actual_length && hc->ep_is_in) {
++00671                         dwc_memcpy(urb->buf + frame_desc->offset + qtd->isoc_split_offset, 
++00672                                    hc->qh->dw_align_buf, frame_desc->actual_length);
++00673                 }
++00674                 /* Skip whole frame */
++00675                 if (hc->qh->do_split && (hc->ep_type == DWC_OTG_EP_TYPE_ISOC) && 
++00676                                 hc->ep_is_in && hcd->core_if->dma_enable) {
++00677                         qtd->complete_split = 0;
++00678                         qtd->isoc_split_offset = 0;
++00679                 }
++00680                         
++00681                 break;
++00682         default:
++00683                 DWC_ASSERT(1, "Unhandled _halt_status (%d)\n", halt_status);
++00684                 break;
++00685         }
++00686         if (++qtd->isoc_frame_index == urb->packet_count) {
++00687                 /*
++00688                  * urb->status is not used for isoc transfers.
++00689                  * The individual frame_desc statuses are used instead.
++00690                  */
++00691                 hcd->fops->complete(hcd, urb->priv, urb, 0);
++00692                 ret_val = DWC_OTG_HC_XFER_URB_COMPLETE;
++00693         } else {
++00694                 ret_val = DWC_OTG_HC_XFER_COMPLETE;
++00695         }
++00696         return ret_val;
++00697 }
++00698 
++00706 static void deactivate_qh(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh, int free_qtd)
++00707 {
++00708         int continue_split = 0;
++00709         dwc_otg_qtd_t *qtd;
++00710 
++00711         DWC_DEBUGPL(DBG_HCDV, "  %s(%p,%p,%d)\n", __func__, hcd, qh, free_qtd);
++00712 
++00713         qtd = DWC_CIRCLEQ_FIRST(&qh->qtd_list);
++00714 
++00715         if (qtd->complete_split) {
++00716                 continue_split = 1;
++00717         } else if (qtd->isoc_split_pos == DWC_HCSPLIT_XACTPOS_MID ||
++00718                    qtd->isoc_split_pos == DWC_HCSPLIT_XACTPOS_END) {
++00719                 continue_split = 1;
++00720         }
++00721 
++00722         if (free_qtd) {
++00723                 dwc_otg_hcd_qtd_remove_and_free(hcd, qtd, qh);
++00724                 continue_split = 0;
++00725         }
++00726 
++00727         qh->channel = NULL;
++00728         dwc_otg_hcd_qh_deactivate(hcd, qh, continue_split);
++00729 }
++00730 
++00742 static void release_channel(dwc_otg_hcd_t * hcd,
++00743                             dwc_hc_t * hc,
++00744                             dwc_otg_qtd_t * qtd,
++00745                             dwc_otg_halt_status_e halt_status)
++00746 {
++00747         dwc_otg_transaction_type_e tr_type;
++00748         int free_qtd;
++00749 
++00750         DWC_DEBUGPL(DBG_HCDV, "  %s: channel %d, halt_status %d\n",
++00751                     __func__, hc->hc_num, halt_status);
++00752 
++00753         switch (halt_status) {
++00754         case DWC_OTG_HC_XFER_URB_COMPLETE:
++00755                 free_qtd = 1;
++00756                 break;
++00757         case DWC_OTG_HC_XFER_AHB_ERR:
++00758         case DWC_OTG_HC_XFER_STALL:
++00759         case DWC_OTG_HC_XFER_BABBLE_ERR:
++00760                 free_qtd = 1;
++00761                 break;
++00762         case DWC_OTG_HC_XFER_XACT_ERR:
++00763                 if (qtd->error_count >= 3) {
++00764                         DWC_DEBUGPL(DBG_HCDV,
++00765                                     "  Complete URB with transaction error\n");
++00766                         free_qtd = 1;
++00767                         qtd->urb->status = -DWC_E_PROTOCOL;
++00768                         hcd->fops->complete(hcd, qtd->urb->priv,
++00769                                             qtd->urb, -DWC_E_PROTOCOL);
++00770                 } else {
++00771                         free_qtd = 0;
++00772                 }
++00773                 break;
++00774         case DWC_OTG_HC_XFER_URB_DEQUEUE:
++00775                 /*
++00776                  * The QTD has already been removed and the QH has been
++00777                  * deactivated. Don't want to do anything except release the
++00778                  * host channel and try to queue more transfers.
++00779                  */
++00780                 goto cleanup;
++00781         case DWC_OTG_HC_XFER_NO_HALT_STATUS:
++00782                 free_qtd = 0;
++00783                 break;
++00784         default:
++00785                 free_qtd = 0;
++00786                 break;
++00787         }
++00788 
++00789         deactivate_qh(hcd, hc->qh, free_qtd);
++00790 
++00791       cleanup:
++00792         /*
++00793          * Release the host channel for use by other transfers. The cleanup
++00794          * function clears the channel interrupt enables and conditions, so
++00795          * there's no need to clear the Channel Halted interrupt separately.
++00796          */
++00797         dwc_otg_hc_cleanup(hcd->core_if, hc);
++00798         DWC_CIRCLEQ_INSERT_TAIL(&hcd->free_hc_list, hc, hc_list_entry);
++00799 
++00800         switch (hc->ep_type) {
++00801         case DWC_OTG_EP_TYPE_CONTROL:
++00802         case DWC_OTG_EP_TYPE_BULK:
++00803                 hcd->non_periodic_channels--;
++00804                 break;
++00805 
++00806         default:
++00807                 /*
++00808                  * Don't release reservations for periodic channels here.
++00809                  * That's done when a periodic transfer is descheduled (i.e.
++00810                  * when the QH is removed from the periodic schedule).
++00811                  */
++00812                 break;
++00813         }
++00814 
++00815         /* Try to queue more transfers now that there's a free channel. */
++00816         tr_type = dwc_otg_hcd_select_transactions(hcd);
++00817         if (tr_type != DWC_OTG_TRANSACTION_NONE) {
++00818                 dwc_otg_hcd_queue_transactions(hcd, tr_type);
++00819         }
++00820 }
++00821 
++00822 
++00833 static void halt_channel(dwc_otg_hcd_t * hcd,
++00834                          dwc_hc_t * hc,
++00835                          dwc_otg_qtd_t * qtd, dwc_otg_halt_status_e halt_status)
++00836 {
++00837         if (hcd->core_if->dma_enable) {
++00838                 release_channel(hcd, hc, qtd, halt_status);
++00839                 return;
++00840         }
++00841 
++00842         /* Slave mode processing... */
++00843         dwc_otg_hc_halt(hcd->core_if, hc, halt_status);
++00844 
++00845         if (hc->halt_on_queue) {
++00846                 gintmsk_data_t gintmsk = {.d32 = 0 };
++00847                 dwc_otg_core_global_regs_t *global_regs;
++00848                 global_regs = hcd->core_if->core_global_regs;
++00849 
++00850                 if (hc->ep_type == DWC_OTG_EP_TYPE_CONTROL ||
++00851                     hc->ep_type == DWC_OTG_EP_TYPE_BULK) {
++00852                         /*
++00853                          * Make sure the Non-periodic Tx FIFO empty interrupt
++00854                          * is enabled so that the non-periodic schedule will
++00855                          * be processed.
++00856                          */
++00857                         gintmsk.b.nptxfempty = 1;
++00858                         dwc_modify_reg32(&global_regs->gintmsk, 0, gintmsk.d32);
++00859                 } else {
++00860                         /*
++00861                          * Move the QH from the periodic queued schedule to
++00862                          * the periodic assigned schedule. This allows the
++00863                          * halt to be queued when the periodic schedule is
++00864                          * processed.
++00865                          */
++00866                         DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_assigned,
++00867                                            &hc->qh->qh_list_entry);
++00868 
++00869                         /*
++00870                          * Make sure the Periodic Tx FIFO Empty interrupt is
++00871                          * enabled so that the periodic schedule will be
++00872                          * processed.
++00873                          */
++00874                         gintmsk.b.ptxfempty = 1;
++00875                         dwc_modify_reg32(&global_regs->gintmsk, 0, gintmsk.d32);
++00876                 }
++00877         }
++00878 }
++00879 
++00885 static void complete_non_periodic_xfer(dwc_otg_hcd_t * hcd,
++00886                                        dwc_hc_t * hc,
++00887                                        dwc_otg_hc_regs_t * hc_regs,
++00888                                        dwc_otg_qtd_t * qtd,
++00889                                        dwc_otg_halt_status_e halt_status)
++00890 {
++00891         hcint_data_t hcint;
++00892 
++00893         qtd->error_count = 0;
++00894 
++00895         hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
++00896         if (hcint.b.nyet) {
++00897                 /*
++00898                  * Got a NYET on the last transaction of the transfer. This
++00899                  * means that the endpoint should be in the PING state at the
++00900                  * beginning of the next transfer.
++00901                  */
++00902                 hc->qh->ping_state = 1;
++00903                 clear_hc_int(hc_regs, nyet);
++00904         }
++00905 
++00906         /*
++00907          * Always halt and release the host channel to make it available for
++00908          * more transfers. There may still be more phases for a control
++00909          * transfer or more data packets for a bulk transfer at this point,
++00910          * but the host channel is still halted. A channel will be reassigned
++00911          * to the transfer when the non-periodic schedule is processed after
++00912          * the channel is released. This allows transactions to be queued
++00913          * properly via dwc_otg_hcd_queue_transactions, which also enables the
++00914          * Tx FIFO Empty interrupt if necessary.
++00915          */
++00916         if (hc->ep_is_in) {
++00917                 /*
++00918                  * IN transfers in Slave mode require an explicit disable to
++00919                  * halt the channel. (In DMA mode, this call simply releases
++00920                  * the channel.)
++00921                  */
++00922                 halt_channel(hcd, hc, qtd, halt_status);
++00923         } else {
++00924                 /*
++00925                  * The channel is automatically disabled by the core for OUT
++00926                  * transfers in Slave mode.
++00927                  */
++00928                 release_channel(hcd, hc, qtd, halt_status);
++00929         }
++00930 }
++00931 
++00937 static void complete_periodic_xfer(dwc_otg_hcd_t * hcd,
++00938                                    dwc_hc_t * hc,
++00939                                    dwc_otg_hc_regs_t * hc_regs,
++00940                                    dwc_otg_qtd_t * qtd,
++00941                                    dwc_otg_halt_status_e halt_status)
++00942 {
++00943         hctsiz_data_t hctsiz;
++00944         qtd->error_count = 0;
++00945 
++00946         hctsiz.d32 = dwc_read_reg32(&hc_regs->hctsiz);
++00947         if (!hc->ep_is_in || hctsiz.b.pktcnt == 0) {
++00948                 /* Core halts channel in these cases. */
++00949                 release_channel(hcd, hc, qtd, halt_status);
++00950         } else {
++00951                 /* Flush any outstanding requests from the Tx queue. */
++00952                 halt_channel(hcd, hc, qtd, halt_status);
++00953         }
++00954 }
++00955 
++00956 static int32_t handle_xfercomp_isoc_split_in(dwc_otg_hcd_t * hcd,
++00957                                              dwc_hc_t * hc,
++00958                                              dwc_otg_hc_regs_t * hc_regs,
++00959                                              dwc_otg_qtd_t * qtd)
++00960 {
++00961         uint32_t len;   
++00962         struct dwc_otg_hcd_iso_packet_desc *frame_desc;
++00963         frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index];
++00964                                 
++00965         len = get_actual_xfer_length(hc, hc_regs, qtd,
++00966                                      DWC_OTG_HC_XFER_COMPLETE,
++00967                                      NULL);
++00968                      
++00969         if (!len) {
++00970                 qtd->complete_split = 0;
++00971                 qtd->isoc_split_offset = 0;
++00972                 return 0;
++00973         }
++00974         frame_desc->actual_length += len;
++00975         
++00976         if (hc->align_buff && len)
++00977                 dwc_memcpy(qtd->urb->buf + frame_desc->offset + qtd->isoc_split_offset, 
++00978                                                                 hc->qh->dw_align_buf, 
++00979                                                                 len);
++00980         qtd->isoc_split_offset += len;
++00981         
++00982         if (frame_desc->length == frame_desc->actual_length) {
++00983                 frame_desc->status = 0;
++00984                 qtd->isoc_frame_index++;
++00985                 qtd->complete_split = 0;
++00986                 qtd->isoc_split_offset = 0;
++00987         }
++00988                         
++00989         if (qtd->isoc_frame_index == qtd->urb->packet_count) {
++00990                 hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, 0);
++00991                 release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE);
++00992         } else {
++00993                 release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NO_HALT_STATUS);
++00994         }
++00995         
++00996         return 1; /* Indicates that channel released */
++00997 }
++01002 static int32_t handle_hc_xfercomp_intr(dwc_otg_hcd_t * hcd,
++01003                                        dwc_hc_t * hc,
++01004                                        dwc_otg_hc_regs_t * hc_regs,
++01005                                        dwc_otg_qtd_t * qtd)
++01006 {
++01007         int urb_xfer_done;
++01008         dwc_otg_halt_status_e halt_status = DWC_OTG_HC_XFER_COMPLETE;
++01009         dwc_otg_hcd_urb_t *urb = qtd->urb;
++01010         int pipe_type = dwc_otg_hcd_get_pipe_type(&urb->pipe_info);
++01011 
++01012         DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
++01013                     "Transfer Complete--\n", hc->hc_num);
++01014 
++01015         if (hcd->core_if->dma_desc_enable) {
++01016                 dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs, halt_status);
++01017                 if (pipe_type == UE_ISOCHRONOUS) {
++01018                         /* Do not disable the interrupt, just clear it */       
++01019                         clear_hc_int(hc_regs, xfercomp);
++01020                         return 1;
++01021                 }
++01022                 goto handle_xfercomp_done;
++01023         }
++01024 
++01025         /*
++01026          * Handle xfer complete on CSPLIT.
++01027          */
++01028 
++01029         if (hc->qh->do_split) {
++01030                 if ((hc->ep_type == DWC_OTG_EP_TYPE_ISOC) && hc->ep_is_in && hcd->core_if->dma_enable) {
++01031                         if (qtd->complete_split && handle_xfercomp_isoc_split_in(hcd, hc, hc_regs, qtd))
++01032                                 goto handle_xfercomp_done;
++01033                 }
++01034                 else {
++01035                 qtd->complete_split = 0;
++01036         }
++01037         }       
++01038 
++01039         /* Update the QTD and URB states. */
++01040         switch (pipe_type) {
++01041         case UE_CONTROL:
++01042                 switch (qtd->control_phase) {
++01043                 case DWC_OTG_CONTROL_SETUP:
++01044                         if (urb->length > 0) {
++01045                                 qtd->control_phase = DWC_OTG_CONTROL_DATA;
++01046                         } else {
++01047                                 qtd->control_phase = DWC_OTG_CONTROL_STATUS;
++01048                         }
++01049                         DWC_DEBUGPL(DBG_HCDV,
++01050                                     "  Control setup transaction done\n");
++01051                         halt_status = DWC_OTG_HC_XFER_COMPLETE;
++01052                         break;
++01053                 case DWC_OTG_CONTROL_DATA:{
++01054                                 urb_xfer_done =
++01055                                     update_urb_state_xfer_comp(hc, hc_regs, urb,
++01056                                                                qtd);
++01057                                 if (urb_xfer_done) {
++01058                                         qtd->control_phase =
++01059                                             DWC_OTG_CONTROL_STATUS;
++01060                                         DWC_DEBUGPL(DBG_HCDV,
++01061                                                     "  Control data transfer done\n");
++01062                                 } else {
++01063                                         dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
++01064                                 }
++01065                                 halt_status = DWC_OTG_HC_XFER_COMPLETE;
++01066                                 break;
++01067                         }
++01068                 case DWC_OTG_CONTROL_STATUS:
++01069                         DWC_DEBUGPL(DBG_HCDV, "  Control transfer complete\n");
++01070                         if (urb->status == -DWC_E_IN_PROGRESS) {
++01071                                 urb->status = 0;
++01072                         }
++01073                         hcd->fops->complete(hcd, urb->priv, urb, urb->status);
++01074                         halt_status = DWC_OTG_HC_XFER_URB_COMPLETE;
++01075                         break;
++01076                 }
++01077 
++01078                 complete_non_periodic_xfer(hcd, hc, hc_regs, qtd, halt_status);
++01079                 break;
++01080         case UE_BULK:
++01081                 DWC_DEBUGPL(DBG_HCDV, "  Bulk transfer complete\n");
++01082                 urb_xfer_done =
++01083                     update_urb_state_xfer_comp(hc, hc_regs, urb, qtd);
++01084                 if (urb_xfer_done) {
++01085                         hcd->fops->complete(hcd, urb->priv, urb, urb->status);
++01086                         halt_status = DWC_OTG_HC_XFER_URB_COMPLETE;
++01087                 } else {
++01088                         halt_status = DWC_OTG_HC_XFER_COMPLETE;
++01089                 }
++01090 
++01091                 dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
++01092                 complete_non_periodic_xfer(hcd, hc, hc_regs, qtd, halt_status);
++01093                 break;
++01094         case UE_INTERRUPT:
++01095                 DWC_DEBUGPL(DBG_HCDV, "  Interrupt transfer complete\n");
++01096                 update_urb_state_xfer_comp(hc, hc_regs, urb, qtd);
++01097 
++01098                 /*
++01099                  * Interrupt URB is done on the first transfer complete
++01100                  * interrupt.
++01101                  */
++01102                 hcd->fops->complete(hcd, urb->priv, urb, urb->status);
++01103                 dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
++01104                 complete_periodic_xfer(hcd, hc, hc_regs, qtd,
++01105                                        DWC_OTG_HC_XFER_URB_COMPLETE);
++01106                 break;
++01107         case UE_ISOCHRONOUS:
++01108                 DWC_DEBUGPL(DBG_HCDV, "  Isochronous transfer complete\n");
++01109                 if (qtd->isoc_split_pos == DWC_HCSPLIT_XACTPOS_ALL) {
++01110                         halt_status =
++01111                             update_isoc_urb_state(hcd, hc, hc_regs, qtd,
++01112                                                   DWC_OTG_HC_XFER_COMPLETE);
++01113                 }
++01114                 complete_periodic_xfer(hcd, hc, hc_regs, qtd, halt_status);
++01115                 break;
++01116         }
++01117 
++01118 handle_xfercomp_done:
++01119         disable_hc_int(hc_regs, xfercompl);
++01120 
++01121         return 1;
++01122 }
++01123 
++01128 static int32_t handle_hc_stall_intr(dwc_otg_hcd_t * hcd,
++01129                                     dwc_hc_t * hc,
++01130                                     dwc_otg_hc_regs_t * hc_regs,
++01131                                     dwc_otg_qtd_t * qtd)
++01132 {
++01133         dwc_otg_hcd_urb_t *urb = qtd->urb;
++01134         int pipe_type = dwc_otg_hcd_get_pipe_type(&urb->pipe_info);
++01135 
++01136         DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
++01137                     "STALL Received--\n", hc->hc_num);
++01138 
++01139         if (hcd->core_if->dma_desc_enable) {
++01140                 dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs, DWC_OTG_HC_XFER_STALL);
++01141                 goto handle_stall_done;
++01142         }
++01143 
++01144         if (pipe_type == UE_CONTROL) {
++01145                 hcd->fops->complete(hcd, urb->priv, urb, -DWC_E_PIPE);
++01146         }
++01147 
++01148         if (pipe_type == UE_BULK || pipe_type == UE_INTERRUPT) {
++01149                 hcd->fops->complete(hcd, urb->priv, urb, -DWC_E_PIPE);
++01150                 /*
++01151                  * USB protocol requires resetting the data toggle for bulk
++01152                  * and interrupt endpoints when a CLEAR_FEATURE(ENDPOINT_HALT)
++01153                  * setup command is issued to the endpoint. Anticipate the
++01154                  * CLEAR_FEATURE command since a STALL has occurred and reset
++01155                  * the data toggle now.
++01156                  */
++01157                 hc->qh->data_toggle = 0;
++01158         }
++01159 
++01160         halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_STALL);
++01161 
++01162 handle_stall_done:
++01163         disable_hc_int(hc_regs, stall);
++01164 
++01165         return 1;
++01166 }
++01167 
++01168 /*
++01169  * Updates the state of the URB when a transfer has been stopped due to an
++01170  * abnormal condition before the transfer completes. Modifies the
++01171  * actual_length field of the URB to reflect the number of bytes that have
++01172  * actually been transferred via the host channel.
++01173  */
++01174 static void update_urb_state_xfer_intr(dwc_hc_t * hc,
++01175                                        dwc_otg_hc_regs_t * hc_regs,
++01176                                        dwc_otg_hcd_urb_t * urb,
++01177                                        dwc_otg_qtd_t * qtd,
++01178                                        dwc_otg_halt_status_e halt_status)
++01179 {
++01180         uint32_t bytes_transferred = get_actual_xfer_length(hc, hc_regs, qtd,
++01181                                                             halt_status, NULL);
++01182         /* non DWORD-aligned buffer case handling. */
++01183         if (hc->align_buff && bytes_transferred && hc->ep_is_in) {
++01184                 dwc_memcpy(urb->buf + urb->actual_length, hc->qh->dw_align_buf, bytes_transferred);
++01185         }
++01186         
++01187         urb->actual_length += bytes_transferred;
++01188 
++01189 #ifdef DEBUG
++01190         {
++01191                 hctsiz_data_t hctsiz;
++01192                 hctsiz.d32 = dwc_read_reg32(&hc_regs->hctsiz);
++01193                 DWC_DEBUGPL(DBG_HCDV, "DWC_otg: %s: %s, channel %d\n",
++01194                             __func__, (hc->ep_is_in ? "IN" : "OUT"),
++01195                             hc->hc_num);
++01196                 DWC_DEBUGPL(DBG_HCDV, "  hc->start_pkt_count %d\n",
++01197                             hc->start_pkt_count);
++01198                 DWC_DEBUGPL(DBG_HCDV, "  hctsiz.pktcnt %d\n", hctsiz.b.pktcnt);
++01199                 DWC_DEBUGPL(DBG_HCDV, "  hc->max_packet %d\n", hc->max_packet);
++01200                 DWC_DEBUGPL(DBG_HCDV, "  bytes_transferred %d\n",
++01201                             bytes_transferred);
++01202                 DWC_DEBUGPL(DBG_HCDV, "  urb->actual_length %d\n",
++01203                             urb->actual_length);
++01204                 DWC_DEBUGPL(DBG_HCDV, "  urb->transfer_buffer_length %d\n",
++01205                             urb->length);
++01206         }
++01207 #endif
++01208 }
++01209 
++01214 static int32_t handle_hc_nak_intr(dwc_otg_hcd_t * hcd,
++01215                                   dwc_hc_t * hc,
++01216                                   dwc_otg_hc_regs_t * hc_regs,
++01217                                   dwc_otg_qtd_t * qtd)
++01218 {
++01219         DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
++01220                     "NAK Received--\n", hc->hc_num);
++01221 
++01222         /*
++01223          * Handle NAK for IN/OUT SSPLIT/CSPLIT transfers, bulk, control, and
++01224          * interrupt.  Re-start the SSPLIT transfer.
++01225          */
++01226         if (hc->do_split) {
++01227                 if (hc->complete_split) {
++01228                         qtd->error_count = 0;
++01229                 }
++01230                 qtd->complete_split = 0;
++01231                 halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NAK);
++01232                 goto handle_nak_done;
++01233         }
++01234 
++01235         switch (dwc_otg_hcd_get_pipe_type(&qtd->urb->pipe_info)) {
++01236         case UE_CONTROL:
++01237         case UE_BULK:
++01238                 if (hcd->core_if->dma_enable && hc->ep_is_in) {
++01239                         /*
++01240                          * NAK interrupts are enabled on bulk/control IN
++01241                          * transfers in DMA mode for the sole purpose of
++01242                          * resetting the error count after a transaction error
++01243                          * occurs. The core will continue transferring data.
++01244                          */
++01245                         qtd->error_count = 0;
++01246                         goto handle_nak_done;
++01247                 }
++01248 
++01249                 /*
++01250                  * NAK interrupts normally occur during OUT transfers in DMA
++01251                  * or Slave mode. For IN transfers, more requests will be
++01252                  * queued as request queue space is available.
++01253                  */
++01254                 qtd->error_count = 0;
++01255 
++01256                 if (!hc->qh->ping_state) {
++01257                         update_urb_state_xfer_intr(hc, hc_regs,
++01258                                                    qtd->urb, qtd,
++01259                                                    DWC_OTG_HC_XFER_NAK);
++01260                         dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
++01261 
++01262                         if (hc->speed == DWC_OTG_EP_SPEED_HIGH)
++01263                                 hc->qh->ping_state = 1;
++01264                         }
++01265 
++01266                 /*
++01267                  * Halt the channel so the transfer can be re-started from
++01268                  * the appropriate point or the PING protocol will
++01269                  * start/continue.
++01270                  */
++01271                 halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NAK);
++01272                 break;
++01273         case UE_INTERRUPT:
++01274                 qtd->error_count = 0;
++01275                 halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NAK);
++01276                 break;
++01277         case UE_ISOCHRONOUS:
++01278                 /* Should never get called for isochronous transfers. */
++01279                 DWC_ASSERT(1, "NACK interrupt for ISOC transfer\n");
++01280                 break;
++01281         }
++01282 
++01283       handle_nak_done:
++01284         disable_hc_int(hc_regs, nak);
++01285 
++01286         return 1;
++01287 }
++01288 
++01294 static int32_t handle_hc_ack_intr(dwc_otg_hcd_t * hcd,
++01295                                   dwc_hc_t * hc,
++01296                                   dwc_otg_hc_regs_t * hc_regs,
++01297                                   dwc_otg_qtd_t * qtd)
++01298 {
++01299         DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
++01300                     "ACK Received--\n", hc->hc_num);
++01301 
++01302         if (hc->do_split) {
++01303                 /*
++01304                  * Handle ACK on SSPLIT.
++01305                  * ACK should not occur in CSPLIT.
++01306                  */
++01307                 if (!hc->ep_is_in && hc->data_pid_start != DWC_OTG_HC_PID_SETUP) {
++01308                         qtd->ssplit_out_xfer_count = hc->xfer_len;
++01309                 }
++01310                 if (!(hc->ep_type == DWC_OTG_EP_TYPE_ISOC && !hc->ep_is_in)) {
++01311                         /* Don't need complete for isochronous out transfers. */
++01312                         qtd->complete_split = 1;
++01313                 }
++01314 
++01315                 /* ISOC OUT */
++01316                 if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC && !hc->ep_is_in) {
++01317                         switch (hc->xact_pos) {
++01318                         case DWC_HCSPLIT_XACTPOS_ALL:
++01319                                 break;
++01320                         case DWC_HCSPLIT_XACTPOS_END:
++01321                                 qtd->isoc_split_pos = DWC_HCSPLIT_XACTPOS_ALL;
++01322                                 qtd->isoc_split_offset = 0;
++01323                                 break;
++01324                         case DWC_HCSPLIT_XACTPOS_BEGIN:
++01325                         case DWC_HCSPLIT_XACTPOS_MID:
++01326                                 /*
++01327                                  * For BEGIN or MID, calculate the length for
++01328                                  * the next microframe to determine the correct
++01329                                  * SSPLIT token, either MID or END.
++01330                                  */
++01331                                 {
++01332                                         struct dwc_otg_hcd_iso_packet_desc
++01333                                             *frame_desc;
++01334 
++01335                                         frame_desc =
++01336                                             &qtd->urb->iso_descs[qtd->
++01337                                                                          isoc_frame_index];
++01338                                         qtd->isoc_split_offset += 188;
++01339 
++01340                                         if ((frame_desc->length -
++01341                                              qtd->isoc_split_offset) <= 188) {
++01342                                                 qtd->isoc_split_pos =
++01343                                                     DWC_HCSPLIT_XACTPOS_END;
++01344                                         } else {
++01345                                                 qtd->isoc_split_pos =
++01346                                                     DWC_HCSPLIT_XACTPOS_MID;
++01347                                         }
++01348 
++01349                                 }
++01350                                 break;
++01351                         }
++01352                 } else {
++01353                         halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_ACK);
++01354                 }
++01355         } else {
++01356                 qtd->error_count = 0;
++01357 
++01358                 if (hc->qh->ping_state) {
++01359                         hc->qh->ping_state = 0;
++01360                         /*
++01361                          * Halt the channel so the transfer can be re-started
++01362                          * from the appropriate point. This only happens in
++01363                          * Slave mode. In DMA mode, the ping_state is cleared
++01364                          * when the transfer is started because the core
++01365                          * automatically executes the PING, then the transfer.
++01366                          */
++01367                         halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_ACK);
++01368                 }
++01369         }
++01370 
++01371         /*
++01372          * If the ACK occurred when _not_ in the PING state, let the channel
++01373          * continue transferring data after clearing the error count.
++01374          */
++01375 
++01376         disable_hc_int(hc_regs, ack);
++01377 
++01378         return 1;
++01379 }
++01380 
++01388 static int32_t handle_hc_nyet_intr(dwc_otg_hcd_t * hcd,
++01389                                    dwc_hc_t * hc,
++01390                                    dwc_otg_hc_regs_t * hc_regs,
++01391                                    dwc_otg_qtd_t * qtd)
++01392 {
++01393         DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
++01394                     "NYET Received--\n", hc->hc_num);
++01395 
++01396         /*
++01397          * NYET on CSPLIT
++01398          * re-do the CSPLIT immediately on non-periodic
++01399          */
++01400         if (hc->do_split && hc->complete_split) {
++01401                 if (hc->ep_is_in && (hc->ep_type == DWC_OTG_EP_TYPE_ISOC) && hcd->core_if->dma_enable) {        
++01402                         qtd->complete_split = 0;
++01403                         qtd->isoc_split_offset = 0;
++01404                         if (++qtd->isoc_frame_index == qtd->urb->packet_count) {
++01405                                 hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, 0);
++01406                                 release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE);    
++01407                         }
++01408                         else
++01409                                 release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NO_HALT_STATUS);  
++01410                         goto handle_nyet_done;
++01411                 }
++01412                 
++01413                 if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
++01414                     hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
++01415                         int frnum = dwc_otg_hcd_get_frame_number(hcd);
++01416 
++01417                         if (dwc_full_frame_num(frnum) !=
++01418                             dwc_full_frame_num(hc->qh->sched_frame)) {
++01419                                 /*
++01420                                  * No longer in the same full speed frame.
++01421                                  * Treat this as a transaction error.
++01422                                  */
++01423 #if 0
++01424 
++01430                                 qtd->error_count++;
++01431 #endif
++01432                                 qtd->complete_split = 0;
++01433                                 halt_channel(hcd, hc, qtd,
++01434                                              DWC_OTG_HC_XFER_XACT_ERR);
++01436                                 goto handle_nyet_done;
++01437                         }
++01438                 }
++01439 
++01440                 halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NYET);
++01441                 goto handle_nyet_done;
++01442         }
++01443 
++01444         hc->qh->ping_state = 1;
++01445         qtd->error_count = 0;
++01446 
++01447         update_urb_state_xfer_intr(hc, hc_regs, qtd->urb, qtd,
++01448                                    DWC_OTG_HC_XFER_NYET);
++01449         dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
++01450 
++01451         /*
++01452          * Halt the channel and re-start the transfer so the PING
++01453          * protocol will start.
++01454          */
++01455         halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NYET);
++01456 
++01457       handle_nyet_done:
++01458         disable_hc_int(hc_regs, nyet);
++01459         return 1;
++01460 }
++01461 
++01466 static int32_t handle_hc_babble_intr(dwc_otg_hcd_t * hcd,
++01467                                      dwc_hc_t * hc,
++01468                                      dwc_otg_hc_regs_t * hc_regs,
++01469                                      dwc_otg_qtd_t * qtd)
++01470 {
++01471         DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
++01472                     "Babble Error--\n", hc->hc_num);
++01473         
++01474         if (hcd->core_if->dma_desc_enable) {
++01475                 dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs, DWC_OTG_HC_XFER_BABBLE_ERR);
++01476                 goto handle_babble_done;
++01477         }
++01478 
++01479         if (hc->ep_type != DWC_OTG_EP_TYPE_ISOC) {
++01480                 hcd->fops->complete(hcd, qtd->urb->priv,
++01481                                     qtd->urb, -DWC_E_OVERFLOW);
++01482                 halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_BABBLE_ERR);
++01483         } else {
++01484                 dwc_otg_halt_status_e halt_status;
++01485                 halt_status = update_isoc_urb_state(hcd, hc, hc_regs, qtd,
++01486                                                     DWC_OTG_HC_XFER_BABBLE_ERR);
++01487                 halt_channel(hcd, hc, qtd, halt_status);
++01488         }
++01489         
++01490 handle_babble_done:
++01491         disable_hc_int(hc_regs, bblerr);
++01492         return 1;
++01493 }
++01494 
++01499 static int32_t handle_hc_ahberr_intr(dwc_otg_hcd_t * hcd,
++01500                                      dwc_hc_t * hc,
++01501                                      dwc_otg_hc_regs_t * hc_regs,
++01502                                      dwc_otg_qtd_t * qtd)
++01503 {
++01504         hcchar_data_t hcchar;
++01505         hcsplt_data_t hcsplt;
++01506         hctsiz_data_t hctsiz;
++01507         uint32_t hcdma;
++01508         char *pipetype, *speed;
++01509 
++01510         dwc_otg_hcd_urb_t *urb = qtd->urb;
++01511 
++01512         DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
++01513                     "AHB Error--\n", hc->hc_num);
++01514 
++01515         hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
++01516         hcsplt.d32 = dwc_read_reg32(&hc_regs->hcsplt);
++01517         hctsiz.d32 = dwc_read_reg32(&hc_regs->hctsiz);
++01518         hcdma = dwc_read_reg32(&hc_regs->hcdma);
++01519 
++01520         DWC_ERROR("AHB ERROR, Channel %d\n", hc->hc_num);
++01521         DWC_ERROR("  hcchar 0x%08x, hcsplt 0x%08x\n", hcchar.d32, hcsplt.d32);
++01522         DWC_ERROR("  hctsiz 0x%08x, hcdma 0x%08x\n", hctsiz.d32, hcdma);
++01523         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD URB Enqueue\n");
++01524         DWC_ERROR("  Device address: %d\n",
++01525                   dwc_otg_hcd_get_dev_addr(&urb->pipe_info));
++01526         DWC_ERROR("  Endpoint: %d, %s\n",
++01527                   dwc_otg_hcd_get_ep_num(&urb->pipe_info),
++01528                   (dwc_otg_hcd_is_pipe_in(&urb->pipe_info) ? "IN" : "OUT"));
++01529         
++01530 
++01531         switch (dwc_otg_hcd_get_pipe_type(&urb->pipe_info)) {
++01532 case UE_CONTROL:
++01533                 pipetype = "CONTROL"; 
++01534                 break; 
++01535         case UE_BULK:
++01536                 pipetype = "BULK"; 
++01537                 break; 
++01538         case UE_INTERRUPT:
++01539                 pipetype = "INTERRUPT"; 
++01540                 break; 
++01541         case UE_ISOCHRONOUS:
++01542                 pipetype = "ISOCHRONOUS"; 
++01543                 break; 
++01544         default:
++01545                 pipetype = "UNKNOWN"; 
++01546                 break;
++01547         }
++01548         
++01549         DWC_ERROR("  Endpoint type: %s\n", pipetype);
++01550 
++01551         switch (hc->speed) {
++01552         case DWC_OTG_EP_SPEED_HIGH:
++01553                 speed = "HIGH"; 
++01554                 break; 
++01555         case DWC_OTG_EP_SPEED_FULL:
++01556                 speed = "FULL"; 
++01557                 break; 
++01558         case DWC_OTG_EP_SPEED_LOW:
++01559                 speed = "LOW"; 
++01560                 break; 
++01561         default:
++01562                 speed = "UNKNOWN"; 
++01563                 break;
++01564         };      
++01565 
++01566         DWC_ERROR("  Speed: %s\n", speed);
++01567         
++01568         DWC_ERROR("  Max packet size: %d\n",
++01569                   dwc_otg_hcd_get_mps(&urb->pipe_info));
++01570         DWC_ERROR("  Data buffer length: %d\n", urb->length);
++01571         DWC_ERROR("  Transfer buffer: %p, Transfer DMA: %p\n",
++01572                   urb->buf, (void *)urb->dma);
++01573         DWC_ERROR("  Setup buffer: %p, Setup DMA: %p\n",
++01574                   urb->setup_packet, (void *)urb->setup_dma);
++01575         DWC_ERROR("  Interval: %d\n", urb->interval);
++01576 
++01577         /* Core haltes the channel for Descriptor DMA mode */
++01578         if (hcd->core_if->dma_desc_enable) {
++01579                 dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs, DWC_OTG_HC_XFER_AHB_ERR);
++01580                 goto handle_ahberr_done;
++01581         }
++01582 
++01583         hcd->fops->complete(hcd, urb->priv, urb, -DWC_E_IO);
++01584 
++01585         /*
++01586          * Force a channel halt. Don't call halt_channel because that won't
++01587          * write to the HCCHARn register in DMA mode to force the halt.
++01588          */
++01589         dwc_otg_hc_halt(hcd->core_if, hc, DWC_OTG_HC_XFER_AHB_ERR);
++01590 handle_ahberr_done:
++01591         disable_hc_int(hc_regs, ahberr);
++01592         return 1;
++01593 }
++01594 
++01599 static int32_t handle_hc_xacterr_intr(dwc_otg_hcd_t * hcd,
++01600                                       dwc_hc_t * hc,
++01601                                       dwc_otg_hc_regs_t * hc_regs,
++01602                                       dwc_otg_qtd_t * qtd)
++01603 {
++01604         DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
++01605                     "Transaction Error--\n", hc->hc_num);
++01606 
++01607         if (hcd->core_if->dma_desc_enable) {
++01608                 dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs, DWC_OTG_HC_XFER_XACT_ERR);
++01609                 goto handle_xacterr_done;
++01610         }
++01611 
++01612         switch (dwc_otg_hcd_get_pipe_type(&qtd->urb->pipe_info)) {
++01613         case UE_CONTROL:
++01614         case UE_BULK:
++01615                 qtd->error_count++;
++01616                 if (!hc->qh->ping_state) {
++01617 
++01618                         update_urb_state_xfer_intr(hc, hc_regs,
++01619                                                    qtd->urb, qtd,
++01620                                                    DWC_OTG_HC_XFER_XACT_ERR);
++01621                         dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
++01622                         if (!hc->ep_is_in && hc->speed == DWC_OTG_EP_SPEED_HIGH) {
++01623                                 hc->qh->ping_state = 1;
++01624                         }
++01625                 }
++01626 
++01627                 /*
++01628                  * Halt the channel so the transfer can be re-started from
++01629                  * the appropriate point or the PING protocol will start.
++01630                  */
++01631                 halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_XACT_ERR);
++01632                 break;
++01633         case UE_INTERRUPT:
++01634                 qtd->error_count++;
++01635                 if (hc->do_split && hc->complete_split) {
++01636                         qtd->complete_split = 0;
++01637                 }
++01638                 halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_XACT_ERR);
++01639                 break;
++01640         case UE_ISOCHRONOUS:
++01641                 {
++01642                         dwc_otg_halt_status_e halt_status;
++01643                         halt_status =
++01644                             update_isoc_urb_state(hcd, hc, hc_regs, qtd,
++01645                                                   DWC_OTG_HC_XFER_XACT_ERR);
++01646 
++01647                         halt_channel(hcd, hc, qtd, halt_status);
++01648                 }
++01649                 break;
++01650         }
++01651 handle_xacterr_done:
++01652         disable_hc_int(hc_regs, xacterr);
++01653 
++01654         return 1;
++01655 }
++01656 
++01661 static int32_t handle_hc_frmovrun_intr(dwc_otg_hcd_t * hcd,
++01662                                        dwc_hc_t * hc,
++01663                                        dwc_otg_hc_regs_t * hc_regs,
++01664                                        dwc_otg_qtd_t * qtd)
++01665 {
++01666         DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
++01667                     "Frame Overrun--\n", hc->hc_num);
++01668 
++01669         switch (dwc_otg_hcd_get_pipe_type(&qtd->urb->pipe_info)) {
++01670         case UE_CONTROL:
++01671         case UE_BULK:
++01672                 break;
++01673         case UE_INTERRUPT:
++01674                 halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_FRAME_OVERRUN);
++01675                 break;
++01676         case UE_ISOCHRONOUS:
++01677                 {
++01678                         dwc_otg_halt_status_e halt_status;
++01679                         halt_status =
++01680                             update_isoc_urb_state(hcd, hc, hc_regs, qtd,
++01681                                                   DWC_OTG_HC_XFER_FRAME_OVERRUN);
++01682 
++01683                         halt_channel(hcd, hc, qtd, halt_status);
++01684                 }
++01685                 break;
++01686         }
++01687 
++01688         disable_hc_int(hc_regs, frmovrun);
++01689 
++01690         return 1;
++01691 }
++01692 
++01697 static int32_t handle_hc_datatglerr_intr(dwc_otg_hcd_t * hcd,
++01698                                          dwc_hc_t * hc,
++01699                                          dwc_otg_hc_regs_t * hc_regs,
++01700                                          dwc_otg_qtd_t * qtd)
++01701 {
++01702         DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
++01703                     "Data Toggle Error--\n", hc->hc_num);
++01704 
++01705         if (hc->ep_is_in) {
++01706                 qtd->error_count = 0;
++01707         } else {
++01708                 DWC_ERROR("Data Toggle Error on OUT transfer,"
++01709                           "channel %d\n", hc->hc_num);
++01710         }
++01711 
++01712         disable_hc_int(hc_regs, datatglerr);
++01713 
++01714         return 1;
++01715 }
++01716 
++01717 #ifdef DEBUG
++01718 
++01724 static inline int halt_status_ok(dwc_otg_hcd_t * hcd,
++01725                                  dwc_hc_t * hc,
++01726                                  dwc_otg_hc_regs_t * hc_regs,
++01727                                  dwc_otg_qtd_t * qtd)
++01728 {
++01729         hcchar_data_t hcchar;
++01730         hctsiz_data_t hctsiz;
++01731         hcint_data_t hcint;
++01732         hcintmsk_data_t hcintmsk;
++01733         hcsplt_data_t hcsplt;
++01734 
++01735         if (hc->halt_status == DWC_OTG_HC_XFER_NO_HALT_STATUS) {
++01736                 /*
++01737                  * This code is here only as a check. This condition should
++01738                  * never happen. Ignore the halt if it does occur.
++01739                  */
++01740                 hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
++01741                 hctsiz.d32 = dwc_read_reg32(&hc_regs->hctsiz);
++01742                 hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
++01743                 hcintmsk.d32 = dwc_read_reg32(&hc_regs->hcintmsk);
++01744                 hcsplt.d32 = dwc_read_reg32(&hc_regs->hcsplt);
++01745                 DWC_WARN
++01746                     ("%s: hc->halt_status == DWC_OTG_HC_XFER_NO_HALT_STATUS, "
++01747                      "channel %d, hcchar 0x%08x, hctsiz 0x%08x, "
++01748                      "hcint 0x%08x, hcintmsk 0x%08x, "
++01749                      "hcsplt 0x%08x, qtd->complete_split %d\n", __func__,
++01750                      hc->hc_num, hcchar.d32, hctsiz.d32, hcint.d32,
++01751                      hcintmsk.d32, hcsplt.d32, qtd->complete_split);
++01752 
++01753                 DWC_WARN("%s: no halt status, channel %d, ignoring interrupt\n",
++01754                          __func__, hc->hc_num);
++01755                 DWC_WARN("\n");
++01756                 clear_hc_int(hc_regs, chhltd);
++01757                 return 0;
++01758         }
++01759 
++01760         /*
++01761          * This code is here only as a check. hcchar.chdis should
++01762          * never be set when the halt interrupt occurs. Halt the
++01763          * channel again if it does occur.
++01764          */
++01765         hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
++01766         if (hcchar.b.chdis) {
++01767                 DWC_WARN("%s: hcchar.chdis set unexpectedly, "
++01768                          "hcchar 0x%08x, trying to halt again\n",
++01769                          __func__, hcchar.d32);
++01770                 clear_hc_int(hc_regs, chhltd);
++01771                 hc->halt_pending = 0;
++01772                 halt_channel(hcd, hc, qtd, hc->halt_status);
++01773                 return 0;
++01774         }
++01775 
++01776         return 1;
++01777 }
++01778 #endif
++01779 
++01784 static void handle_hc_chhltd_intr_dma(dwc_otg_hcd_t * hcd,
++01785                                       dwc_hc_t * hc,
++01786                                       dwc_otg_hc_regs_t * hc_regs,
++01787                                       dwc_otg_qtd_t * qtd)
++01788 {
++01789         hcint_data_t hcint;
++01790         hcintmsk_data_t hcintmsk;
++01791         int out_nak_enh = 0;
++01792 
++01793         /* For core with OUT NAK enhancement, the flow for high-
++01794          * speed CONTROL/BULK OUT is handled a little differently.
++01795          */
++01796         if (hcd->core_if->snpsid >= OTG_CORE_REV_2_71a) {
++01797                 if (hc->speed == DWC_OTG_EP_SPEED_HIGH && !hc->ep_is_in &&
++01798                     (hc->ep_type == DWC_OTG_EP_TYPE_CONTROL ||
++01799                      hc->ep_type == DWC_OTG_EP_TYPE_BULK)) {
++01800                         out_nak_enh = 1;
++01801                 }
++01802         }
++01803 
++01804         if (hc->halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE ||
++01805             (hc->halt_status == DWC_OTG_HC_XFER_AHB_ERR && !hcd->core_if->dma_desc_enable)) {
++01806                 /*
++01807                  * Just release the channel. A dequeue can happen on a
++01808                  * transfer timeout. In the case of an AHB Error, the channel
++01809                  * was forced to halt because there's no way to gracefully
++01810                  * recover.
++01811                  */
++01812                 if (hcd->core_if->dma_desc_enable)
++01813                         dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs, hc->halt_status);
++01814                 else
++01815                         release_channel(hcd, hc, qtd, hc->halt_status);
++01816                 return;
++01817         }
++01818 
++01819         /* Read the HCINTn register to determine the cause for the halt. */
++01820         hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
++01821         hcintmsk.d32 = dwc_read_reg32(&hc_regs->hcintmsk);
++01822 
++01823         if (hcint.b.xfercomp) {
++01830                 if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC && !hc->ep_is_in) {
++01831                         handle_hc_ack_intr(hcd, hc, hc_regs, qtd);
++01832                 }
++01833                 handle_hc_xfercomp_intr(hcd, hc, hc_regs, qtd);
++01834         } else if (hcint.b.stall) {
++01835                 handle_hc_stall_intr(hcd, hc, hc_regs, qtd);
++01836         } else if (hcint.b.xacterr && !hcd->core_if->dma_desc_enable) {
++01837                 if (out_nak_enh) {
++01838                         if (hcint.b.nyet || hcint.b.nak || hcint.b.ack) {
++01839                                 DWC_DEBUG("XactErr with NYET/NAK/ACK\n");
++01840                                 qtd->error_count = 0;
++01841                         } else {
++01842                                 DWC_DEBUG("XactErr without NYET/NAK/ACK\n");
++01843                         }
++01844                 }
++01845 
++01846                 /*
++01847                  * Must handle xacterr before nak or ack. Could get a xacterr
++01848                  * at the same time as either of these on a BULK/CONTROL OUT
++01849                  * that started with a PING. The xacterr takes precedence.
++01850                  */
++01851                 handle_hc_xacterr_intr(hcd, hc, hc_regs, qtd);
++01852         } else if (hcint.b.xcs_xact && hcd->core_if->dma_desc_enable) {
++01853                 handle_hc_xacterr_intr(hcd, hc, hc_regs, qtd);
++01854         } else if (hcint.b.ahberr && hcd->core_if->dma_desc_enable) {    
++01855                 handle_hc_ahberr_intr(hcd, hc, hc_regs, qtd);
++01856         } else if (hcint.b.bblerr) {
++01857                 handle_hc_babble_intr(hcd, hc, hc_regs, qtd);
++01858         } else if (hcint.b.frmovrun) {
++01859                 handle_hc_frmovrun_intr(hcd, hc, hc_regs, qtd);
++01860         } else if (!out_nak_enh) {
++01861                 if (hcint.b.nyet) {
++01862                         /*
++01863                          * Must handle nyet before nak or ack. Could get a nyet at the
++01864                          * same time as either of those on a BULK/CONTROL OUT that
++01865                          * started with a PING. The nyet takes precedence.
++01866                          */
++01867                         handle_hc_nyet_intr(hcd, hc, hc_regs, qtd);
++01868                 } else if (hcint.b.nak && !hcintmsk.b.nak) {
++01869                         /*
++01870                          * If nak is not masked, it's because a non-split IN transfer
++01871                          * is in an error state. In that case, the nak is handled by
++01872                          * the nak interrupt handler, not here. Handle nak here for
++01873                          * BULK/CONTROL OUT transfers, which halt on a NAK to allow
++01874                          * rewinding the buffer pointer.
++01875                          */
++01876                         handle_hc_nak_intr(hcd, hc, hc_regs, qtd);
++01877                 } else if (hcint.b.ack && !hcintmsk.b.ack) {
++01878                         /*
++01879                          * If ack is not masked, it's because a non-split IN transfer
++01880                          * is in an error state. In that case, the ack is handled by
++01881                          * the ack interrupt handler, not here. Handle ack here for
++01882                          * split transfers. Start splits halt on ACK.
++01883                          */
++01884                         handle_hc_ack_intr(hcd, hc, hc_regs, qtd);
++01885                 } else {
++01886                         if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
++01887                             hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
++01888                                 /*
++01889                                  * A periodic transfer halted with no other channel
++01890                                  * interrupts set. Assume it was halted by the core
++01891                                  * because it could not be completed in its scheduled
++01892                                  * (micro)frame.
++01893                                  */
++01894 #ifdef DEBUG
++01895                                 DWC_PRINTF
++01896                                     ("%s: Halt channel %d (assume incomplete periodic transfer)\n",
++01897                                      __func__, hc->hc_num);
++01898 #endif
++01899                                 halt_channel(hcd, hc, qtd,
++01900                                              DWC_OTG_HC_XFER_PERIODIC_INCOMPLETE);
++01901                         } else {
++01902                                 DWC_ERROR
++01903                                     ("%s: Channel %d, DMA Mode -- ChHltd set, but reason "
++01904                                      "for halting is unknown, hcint 0x%08x, intsts 0x%08x\n",
++01905                                      __func__, hc->hc_num, hcint.d32,
++01906                                      dwc_read_reg32(&hcd->core_if->
++01907                                                     core_global_regs->gintsts));
++01908                         }
++01909         
++01910                 }
++01911         } else {
++01912                 DWC_PRINTF("NYET/NAK/ACK/other in non-error case, 0x%08x\n",
++01913                            hcint.d32);
++01914         }
++01915 }
++01916 
++01928 static int32_t handle_hc_chhltd_intr(dwc_otg_hcd_t * hcd,
++01929                                      dwc_hc_t * hc,
++01930                                      dwc_otg_hc_regs_t * hc_regs,
++01931                                      dwc_otg_qtd_t * qtd)
++01932 {
++01933         DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
++01934                     "Channel Halted--\n", hc->hc_num);
++01935 
++01936         if (hcd->core_if->dma_enable) {
++01937                 handle_hc_chhltd_intr_dma(hcd, hc, hc_regs, qtd);
++01938         } else {
++01939 #ifdef DEBUG
++01940                 if (!halt_status_ok(hcd, hc, hc_regs, qtd)) {
++01941                         return 1;
++01942                 }
++01943 #endif
++01944                 release_channel(hcd, hc, qtd, hc->halt_status);
++01945         }
++01946 
++01947         return 1;
++01948 }
++01949 
++01951 int32_t dwc_otg_hcd_handle_hc_n_intr(dwc_otg_hcd_t * dwc_otg_hcd, uint32_t num)
++01952 {
++01953         int retval = 0;
++01954         hcint_data_t hcint;
++01955         hcintmsk_data_t hcintmsk;
++01956         dwc_hc_t *hc;
++01957         dwc_otg_hc_regs_t *hc_regs;
++01958         dwc_otg_qtd_t *qtd;
++01959 
++01960         DWC_DEBUGPL(DBG_HCDV, "--Host Channel Interrupt--, Channel %d\n", num);
++01961 
++01962         hc = dwc_otg_hcd->hc_ptr_array[num];
++01963         hc_regs = dwc_otg_hcd->core_if->host_if->hc_regs[num];
++01964         qtd = DWC_CIRCLEQ_FIRST(&hc->qh->qtd_list);
++01965 
++01966         hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
++01967         hcintmsk.d32 = dwc_read_reg32(&hc_regs->hcintmsk);
++01968         DWC_DEBUGPL(DBG_HCDV,
++01969                     "  hcint 0x%08x, hcintmsk 0x%08x, hcint&hcintmsk 0x%08x\n",
++01970                     hcint.d32, hcintmsk.d32, (hcint.d32 & hcintmsk.d32));
++01971         hcint.d32 = hcint.d32 & hcintmsk.d32;
++01972 
++01973         if (!dwc_otg_hcd->core_if->dma_enable) {
++01974                 if (hcint.b.chhltd && hcint.d32 != 0x2) {
++01975                         hcint.b.chhltd = 0;
++01976                 }
++01977         }
++01978 
++01979         if (hcint.b.xfercomp) {
++01980                 retval |=
++01981                     handle_hc_xfercomp_intr(dwc_otg_hcd, hc, hc_regs, qtd);
++01982                 /*
++01983                  * If NYET occurred at same time as Xfer Complete, the NYET is
++01984                  * handled by the Xfer Complete interrupt handler. Don't want
++01985                  * to call the NYET interrupt handler in this case.
++01986                  */
++01987                 hcint.b.nyet = 0;
++01988         }
++01989         if (hcint.b.chhltd) {
++01990                 retval |= handle_hc_chhltd_intr(dwc_otg_hcd, hc, hc_regs, qtd);
++01991         }
++01992         if (hcint.b.ahberr) {
++01993                 retval |= handle_hc_ahberr_intr(dwc_otg_hcd, hc, hc_regs, qtd);
++01994         }
++01995         if (hcint.b.stall) {
++01996                 retval |= handle_hc_stall_intr(dwc_otg_hcd, hc, hc_regs, qtd);
++01997         }
++01998         if (hcint.b.nak) {
++01999                 retval |= handle_hc_nak_intr(dwc_otg_hcd, hc, hc_regs, qtd);
++02000         }
++02001         if (hcint.b.ack) {
++02002                 retval |= handle_hc_ack_intr(dwc_otg_hcd, hc, hc_regs, qtd);
++02003         }
++02004         if (hcint.b.nyet) {
++02005                 retval |= handle_hc_nyet_intr(dwc_otg_hcd, hc, hc_regs, qtd);
++02006         }
++02007         if (hcint.b.xacterr) {
++02008                 retval |= handle_hc_xacterr_intr(dwc_otg_hcd, hc, hc_regs, qtd);
++02009         }
++02010         if (hcint.b.bblerr) {
++02011                 retval |= handle_hc_babble_intr(dwc_otg_hcd, hc, hc_regs, qtd);
++02012         }
++02013         if (hcint.b.frmovrun) {
++02014                 retval |=
++02015                     handle_hc_frmovrun_intr(dwc_otg_hcd, hc, hc_regs, qtd);
++02016         }
++02017         if (hcint.b.datatglerr) {
++02018                 retval |=
++02019                     handle_hc_datatglerr_intr(dwc_otg_hcd, hc, hc_regs, qtd);
++02020         }
++02021 
++02022         return retval;
++02023 }
++02024 
++02025 #endif                          /* DWC_DEVICE_ONLY */
++
Generated on Tue May 5 02:22:48 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__hcd__intr_8c.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__hcd__intr_8c.html 2013-07-26 19:31:21.000000000 +0000 +@@ -0,0 +1,1252 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_hcd_intr.c File Reference ++ ++ ++ ++ ++
++
++
++
++

dwc_otg_hcd_intr.c File Reference

This file contains the implementation of the HCD Interrupt handlers. More... ++

++#include "dwc_otg_hcd.h"
++#include "dwc_otg_regs.h"
++ ++

++Go to the source code of this file. ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++

Functions

int32_t dwc_otg_hcd_handle_intr (dwc_otg_hcd_t *dwc_otg_hcd)
 This function should be called on every hardware interrupt.
int32_t dwc_otg_hcd_handle_sof_intr (dwc_otg_hcd_t *hcd)
 Handles the start-of-frame interrupt in host mode.
int32_t dwc_otg_hcd_handle_rx_status_q_level_intr (dwc_otg_hcd_t *dwc_otg_hcd)
 Handles the Rx Status Queue Level Interrupt, which indicates that there is at least one packet in the Rx FIFO.
int32_t dwc_otg_hcd_handle_np_tx_fifo_empty_intr (dwc_otg_hcd_t *dwc_otg_hcd)
 This interrupt occurs when the non-periodic Tx FIFO is half-empty.
int32_t dwc_otg_hcd_handle_perio_tx_fifo_empty_intr (dwc_otg_hcd_t *dwc_otg_hcd)
 This interrupt occurs when the periodic Tx FIFO is half-empty.
int32_t dwc_otg_hcd_handle_port_intr (dwc_otg_hcd_t *dwc_otg_hcd)
 There are multiple conditions that can cause a port interrupt.
int32_t dwc_otg_hcd_handle_hc_intr (dwc_otg_hcd_t *dwc_otg_hcd)
 This interrupt indicates that one or more host channels has a pending interrupt.
static uint32_t get_actual_xfer_length (dwc_hc_t *hc, dwc_otg_hc_regs_t *hc_regs, dwc_otg_qtd_t *qtd, dwc_otg_halt_status_e halt_status, int *short_read)
 Gets the actual length of a transfer after the transfer halts.
static int update_urb_state_xfer_comp (dwc_hc_t *hc, dwc_otg_hc_regs_t *hc_regs, dwc_otg_hcd_urb_t *urb, dwc_otg_qtd_t *qtd)
 Updates the state of the URB after a Transfer Complete interrupt on the host channel.
++void dwc_otg_hcd_save_data_toggle (dwc_hc_t *hc, dwc_otg_hc_regs_t *hc_regs, dwc_otg_qtd_t *qtd)
static dwc_otg_halt_status_e update_isoc_urb_state (dwc_otg_hcd_t *hcd, dwc_hc_t *hc, dwc_otg_hc_regs_t *hc_regs, dwc_otg_qtd_t *qtd, dwc_otg_halt_status_e halt_status)
 Updates the state of an Isochronous URB when the transfer is stopped for any reason.
static void deactivate_qh (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh, int free_qtd)
 Frees the first QTD in the QH's list if free_qtd is 1.
static void release_channel (dwc_otg_hcd_t *hcd, dwc_hc_t *hc, dwc_otg_qtd_t *qtd, dwc_otg_halt_status_e halt_status)
 Releases a host channel for use by other transfers.
static void halt_channel (dwc_otg_hcd_t *hcd, dwc_hc_t *hc, dwc_otg_qtd_t *qtd, dwc_otg_halt_status_e halt_status)
 Halts a host channel.
static void complete_non_periodic_xfer (dwc_otg_hcd_t *hcd, dwc_hc_t *hc, dwc_otg_hc_regs_t *hc_regs, dwc_otg_qtd_t *qtd, dwc_otg_halt_status_e halt_status)
 Performs common cleanup for non-periodic transfers after a Transfer Complete interrupt.
static void complete_periodic_xfer (dwc_otg_hcd_t *hcd, dwc_hc_t *hc, dwc_otg_hc_regs_t *hc_regs, dwc_otg_qtd_t *qtd, dwc_otg_halt_status_e halt_status)
 Performs common cleanup for periodic transfers after a Transfer Complete interrupt.
++static int32_t handle_xfercomp_isoc_split_in (dwc_otg_hcd_t *hcd, dwc_hc_t *hc, dwc_otg_hc_regs_t *hc_regs, dwc_otg_qtd_t *qtd)
static int32_t handle_hc_xfercomp_intr (dwc_otg_hcd_t *hcd, dwc_hc_t *hc, dwc_otg_hc_regs_t *hc_regs, dwc_otg_qtd_t *qtd)
 Handles a host channel Transfer Complete interrupt.
static int32_t handle_hc_stall_intr (dwc_otg_hcd_t *hcd, dwc_hc_t *hc, dwc_otg_hc_regs_t *hc_regs, dwc_otg_qtd_t *qtd)
 Handles a host channel STALL interrupt.
++static void update_urb_state_xfer_intr (dwc_hc_t *hc, dwc_otg_hc_regs_t *hc_regs, dwc_otg_hcd_urb_t *urb, dwc_otg_qtd_t *qtd, dwc_otg_halt_status_e halt_status)
static int32_t handle_hc_nak_intr (dwc_otg_hcd_t *hcd, dwc_hc_t *hc, dwc_otg_hc_regs_t *hc_regs, dwc_otg_qtd_t *qtd)
 Handles a host channel NAK interrupt.
static int32_t handle_hc_ack_intr (dwc_otg_hcd_t *hcd, dwc_hc_t *hc, dwc_otg_hc_regs_t *hc_regs, dwc_otg_qtd_t *qtd)
 Handles a host channel ACK interrupt.
static int32_t handle_hc_nyet_intr (dwc_otg_hcd_t *hcd, dwc_hc_t *hc, dwc_otg_hc_regs_t *hc_regs, dwc_otg_qtd_t *qtd)
 Handles a host channel NYET interrupt.
static int32_t handle_hc_babble_intr (dwc_otg_hcd_t *hcd, dwc_hc_t *hc, dwc_otg_hc_regs_t *hc_regs, dwc_otg_qtd_t *qtd)
 Handles a host channel babble interrupt.
static int32_t handle_hc_ahberr_intr (dwc_otg_hcd_t *hcd, dwc_hc_t *hc, dwc_otg_hc_regs_t *hc_regs, dwc_otg_qtd_t *qtd)
 Handles a host channel AHB error interrupt.
static int32_t handle_hc_xacterr_intr (dwc_otg_hcd_t *hcd, dwc_hc_t *hc, dwc_otg_hc_regs_t *hc_regs, dwc_otg_qtd_t *qtd)
 Handles a host channel transaction error interrupt.
static int32_t handle_hc_frmovrun_intr (dwc_otg_hcd_t *hcd, dwc_hc_t *hc, dwc_otg_hc_regs_t *hc_regs, dwc_otg_qtd_t *qtd)
 Handles a host channel frame overrun interrupt.
static int32_t handle_hc_datatglerr_intr (dwc_otg_hcd_t *hcd, dwc_hc_t *hc, dwc_otg_hc_regs_t *hc_regs, dwc_otg_qtd_t *qtd)
 Handles a host channel data toggle error interrupt.
static void handle_hc_chhltd_intr_dma (dwc_otg_hcd_t *hcd, dwc_hc_t *hc, dwc_otg_hc_regs_t *hc_regs, dwc_otg_qtd_t *qtd)
 Handles a host Channel Halted interrupt in DMA mode.
static int32_t handle_hc_chhltd_intr (dwc_otg_hcd_t *hcd, dwc_hc_t *hc, dwc_otg_hc_regs_t *hc_regs, dwc_otg_qtd_t *qtd)
 Handles a host channel Channel Halted interrupt.
++int32_t dwc_otg_hcd_handle_hc_n_intr (dwc_otg_hcd_t *dwc_otg_hcd, uint32_t num)
 Handles interrupt for a specific Host Channel.
++

Detailed Description

++This file contains the implementation of the HCD Interrupt handlers. ++

++ ++

++Definition in file dwc_otg_hcd_intr.c.

Function Documentation

++ ++
++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int32_t dwc_otg_hcd_handle_intr (dwc_otg_hcd_t *  dwc_otg_hcd  ) 
++
++
++ ++

++This function should be called on every hardware interrupt. ++

++

Parameters:
++ ++ ++
dwc_otg_hcd The HCD
++
++Returns non zero if interrupt is handled Return 0 if interrupt is not handled ++

++

Todo:
Implement i2cintr handler.
++ ++

++Definition at line 43 of file dwc_otg_hcd_intr.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int32_t dwc_otg_hcd_handle_sof_intr (dwc_otg_hcd_t *  hcd  ) 
++
++
++ ++

++Handles the start-of-frame interrupt in host mode. ++

++Non-periodic transactions may be queued to the DWC_otg controller for the current (micro)frame. Periodic transactions may be queued to the controller for the next (micro)frame. ++

++Definition at line 169 of file dwc_otg_hcd_intr.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int32_t dwc_otg_hcd_handle_rx_status_q_level_intr (dwc_otg_hcd_t *  dwc_otg_hcd  ) 
++
++
++ ++

++Handles the Rx Status Queue Level Interrupt, which indicates that there is at least one packet in the Rx FIFO. ++

++The packets are moved from the FIFO to memory if the DWC_otg controller is operating in Slave mode. ++

++Definition at line 222 of file dwc_otg_hcd_intr.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int32_t dwc_otg_hcd_handle_np_tx_fifo_empty_intr (dwc_otg_hcd_t *  dwc_otg_hcd  ) 
++
++
++ ++

++This interrupt occurs when the non-periodic Tx FIFO is half-empty. ++

++More data packets may be written to the FIFO for OUT transfers. More requests may be written to the non-periodic request queue for IN transfers. This interrupt is enabled only in Slave mode. ++

++Definition at line 271 of file dwc_otg_hcd_intr.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int32_t dwc_otg_hcd_handle_perio_tx_fifo_empty_intr (dwc_otg_hcd_t *  dwc_otg_hcd  ) 
++
++
++ ++

++This interrupt occurs when the periodic Tx FIFO is half-empty. ++

++More data packets may be written to the FIFO for OUT transfers. More requests may be written to the periodic request queue for IN transfers. This interrupt is enabled only in Slave mode. ++

++Definition at line 283 of file dwc_otg_hcd_intr.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int32_t dwc_otg_hcd_handle_port_intr (dwc_otg_hcd_t *  dwc_otg_hcd  ) 
++
++
++ ++

++There are multiple conditions that can cause a port interrupt. ++

++This function determines which interrupt conditions have occurred and handles them appropriately. ++

++Overcurrent Change Interrupt ++

++Definition at line 294 of file dwc_otg_hcd_intr.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int32_t dwc_otg_hcd_handle_hc_intr (dwc_otg_hcd_t *  dwc_otg_hcd  ) 
++
++
++ ++

++This interrupt indicates that one or more host channels has a pending interrupt. ++

++There are multiple conditions that can cause each host channel interrupt. This function determines which conditions have occurred for each host channel interrupt and handles them appropriately. ++

++Definition at line 453 of file dwc_otg_hcd_intr.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
static uint32_t get_actual_xfer_length (dwc_hc_t *  hc,
dwc_otg_hc_regs_t *  hc_regs,
dwc_otg_qtd_t *  qtd,
dwc_otg_halt_status_e  halt_status,
int *  short_read 
) [static]
++
++
++ ++

++Gets the actual length of a transfer after the transfer halts. ++

++_halt_status holds the reason for the halt.

++For IN transfers where halt_status is DWC_OTG_HC_XFER_COMPLETE, *short_read is set to 1 upon return if less than the requested number of bytes were transferred. Otherwise, *short_read is set to 0 upon return. short_read may also be NULL on entry, in which case it remains unchanged. ++

++Definition at line 485 of file dwc_otg_hcd_intr.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
static int update_urb_state_xfer_comp (dwc_hc_t *  hc,
dwc_otg_hc_regs_t *  hc_regs,
dwc_otg_hcd_urb_t *  urb,
dwc_otg_qtd_t *  qtd 
) [static]
++
++
++ ++

++Updates the state of the URB after a Transfer Complete interrupt on the host channel. ++

++Updates the actual_length field of the URB based on the number of bytes transferred via the host channel. Sets the URB status if the data transfer is finished.

++

Returns:
1 if the data transfer specified by the URB is completely finished, 0 otherwise.
++ ++

++Definition at line 536 of file dwc_otg_hcd_intr.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
static dwc_otg_halt_status_e update_isoc_urb_state (dwc_otg_hcd_t *  hcd,
dwc_hc_t *  hc,
dwc_otg_hc_regs_t *  hc_regs,
dwc_otg_qtd_t *  qtd,
dwc_otg_halt_status_e  halt_status 
) [static]
++
++
++ ++

++Updates the state of an Isochronous URB when the transfer is stopped for any reason. ++

++The fields of the current entry in the frame descriptor array are set based on the transfer state and the input _halt_status. Completes the Isochronous URB if all the URB frames have been completed.

++

Returns:
DWC_OTG_HC_XFER_COMPLETE if there are more frames remaining to be transferred in the URB. Otherwise return DWC_OTG_HC_XFER_URB_COMPLETE.
++ ++

++Definition at line 626 of file dwc_otg_hcd_intr.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
static void deactivate_qh (dwc_otg_hcd_t *  hcd,
dwc_otg_qh_t *  qh,
int  free_qtd 
) [static]
++
++
++ ++

++Frees the first QTD in the QH's list if free_qtd is 1. ++

++For non-periodic QHs, removes the QH from the active non-periodic schedule. If any QTDs are still linked to the QH, the QH is added to the end of the inactive non-periodic schedule. For periodic QHs, removes the QH from the periodic schedule if no more QTDs are linked to the QH. ++

++Definition at line 706 of file dwc_otg_hcd_intr.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
static void release_channel (dwc_otg_hcd_t *  hcd,
dwc_hc_t *  hc,
dwc_otg_qtd_t *  qtd,
dwc_otg_halt_status_e  halt_status 
) [static]
++
++
++ ++

++Releases a host channel for use by other transfers. ++

++Attempts to select and queue more transactions since at least one host channel is available.

++

Parameters:
++ ++ ++ ++ ++ ++
hcd The HCD state structure.
hc The host channel to release.
qtd The QTD associated with the host channel. This QTD may be freed if the transfer is complete or an error has occurred.
halt_status Reason the channel is being released. This status determines the actions taken by this function.
++
++ ++

++Definition at line 742 of file dwc_otg_hcd_intr.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
static void halt_channel (dwc_otg_hcd_t *  hcd,
dwc_hc_t *  hc,
dwc_otg_qtd_t *  qtd,
dwc_otg_halt_status_e  halt_status 
) [static]
++
++
++ ++

++Halts a host channel. ++

++If the channel cannot be halted immediately because the request queue is full, this function ensures that the FIFO empty interrupt for the appropriate queue is enabled so that the halt request can be queued when there is space in the request queue.

++This function may also be called in DMA mode. In that case, the channel is simply released since the core always halts the channel automatically in DMA mode. ++

++Definition at line 833 of file dwc_otg_hcd_intr.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
static void complete_non_periodic_xfer (dwc_otg_hcd_t *  hcd,
dwc_hc_t *  hc,
dwc_otg_hc_regs_t *  hc_regs,
dwc_otg_qtd_t *  qtd,
dwc_otg_halt_status_e  halt_status 
) [static]
++
++
++ ++

++Performs common cleanup for non-periodic transfers after a Transfer Complete interrupt. ++

++This function should be called after any endpoint type specific handling is finished to release the host channel. ++

++Definition at line 885 of file dwc_otg_hcd_intr.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
static void complete_periodic_xfer (dwc_otg_hcd_t *  hcd,
dwc_hc_t *  hc,
dwc_otg_hc_regs_t *  hc_regs,
dwc_otg_qtd_t *  qtd,
dwc_otg_halt_status_e  halt_status 
) [static]
++
++
++ ++

++Performs common cleanup for periodic transfers after a Transfer Complete interrupt. ++

++This function should be called after any endpoint type specific handling is finished to release the host channel. ++

++Definition at line 937 of file dwc_otg_hcd_intr.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
static int32_t handle_hc_xfercomp_intr (dwc_otg_hcd_t *  hcd,
dwc_hc_t *  hc,
dwc_otg_hc_regs_t *  hc_regs,
dwc_otg_qtd_t *  qtd 
) [static]
++
++
++ ++

++Handles a host channel Transfer Complete interrupt. ++

++This handler may be called in either DMA mode or Slave mode. ++

++Definition at line 1002 of file dwc_otg_hcd_intr.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
static int32_t handle_hc_stall_intr (dwc_otg_hcd_t *  hcd,
dwc_hc_t *  hc,
dwc_otg_hc_regs_t *  hc_regs,
dwc_otg_qtd_t *  qtd 
) [static]
++
++
++ ++

++Handles a host channel STALL interrupt. ++

++This handler may be called in either DMA mode or Slave mode. ++

++Definition at line 1128 of file dwc_otg_hcd_intr.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
static int32_t handle_hc_nak_intr (dwc_otg_hcd_t *  hcd,
dwc_hc_t *  hc,
dwc_otg_hc_regs_t *  hc_regs,
dwc_otg_qtd_t *  qtd 
) [static]
++
++
++ ++

++Handles a host channel NAK interrupt. ++

++This handler may be called in either DMA mode or Slave mode. ++

++Definition at line 1214 of file dwc_otg_hcd_intr.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
static int32_t handle_hc_ack_intr (dwc_otg_hcd_t *  hcd,
dwc_hc_t *  hc,
dwc_otg_hc_regs_t *  hc_regs,
dwc_otg_qtd_t *  qtd 
) [static]
++
++
++ ++

++Handles a host channel ACK interrupt. ++

++This interrupt is enabled when performing the PING protocol in Slave mode, when errors occur during either Slave mode or DMA mode, and during Start Split transactions. ++

++Definition at line 1294 of file dwc_otg_hcd_intr.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
static int32_t handle_hc_nyet_intr (dwc_otg_hcd_t *  hcd,
dwc_hc_t *  hc,
dwc_otg_hc_regs_t *  hc_regs,
dwc_otg_qtd_t *  qtd 
) [static]
++
++
++ ++

++Handles a host channel NYET interrupt. ++

++This interrupt should only occur on Bulk and Control OUT endpoints and for complete split transactions. If a NYET occurs at the same time as a Transfer Complete interrupt, it is handled in the xfercomp interrupt handler, not here. This handler may be called in either DMA mode or Slave mode. ++

++

Todo:
add support for isoc release
++ ++

++Definition at line 1388 of file dwc_otg_hcd_intr.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
static int32_t handle_hc_babble_intr (dwc_otg_hcd_t *  hcd,
dwc_hc_t *  hc,
dwc_otg_hc_regs_t *  hc_regs,
dwc_otg_qtd_t *  qtd 
) [static]
++
++
++ ++

++Handles a host channel babble interrupt. ++

++This handler may be called in either DMA mode or Slave mode. ++

++Definition at line 1466 of file dwc_otg_hcd_intr.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
static int32_t handle_hc_ahberr_intr (dwc_otg_hcd_t *  hcd,
dwc_hc_t *  hc,
dwc_otg_hc_regs_t *  hc_regs,
dwc_otg_qtd_t *  qtd 
) [static]
++
++
++ ++

++Handles a host channel AHB error interrupt. ++

++This handler is only called in DMA mode. ++

++Definition at line 1499 of file dwc_otg_hcd_intr.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
static int32_t handle_hc_xacterr_intr (dwc_otg_hcd_t *  hcd,
dwc_hc_t *  hc,
dwc_otg_hc_regs_t *  hc_regs,
dwc_otg_qtd_t *  qtd 
) [static]
++
++
++ ++

++Handles a host channel transaction error interrupt. ++

++This handler may be called in either DMA mode or Slave mode. ++

++Definition at line 1599 of file dwc_otg_hcd_intr.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
static int32_t handle_hc_frmovrun_intr (dwc_otg_hcd_t *  hcd,
dwc_hc_t *  hc,
dwc_otg_hc_regs_t *  hc_regs,
dwc_otg_qtd_t *  qtd 
) [static]
++
++
++ ++

++Handles a host channel frame overrun interrupt. ++

++This handler may be called in either DMA mode or Slave mode. ++

++Definition at line 1661 of file dwc_otg_hcd_intr.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
static int32_t handle_hc_datatglerr_intr (dwc_otg_hcd_t *  hcd,
dwc_hc_t *  hc,
dwc_otg_hc_regs_t *  hc_regs,
dwc_otg_qtd_t *  qtd 
) [static]
++
++
++ ++

++Handles a host channel data toggle error interrupt. ++

++This handler may be called in either DMA mode or Slave mode. ++

++Definition at line 1697 of file dwc_otg_hcd_intr.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
static void handle_hc_chhltd_intr_dma (dwc_otg_hcd_t *  hcd,
dwc_hc_t *  hc,
dwc_otg_hc_regs_t *  hc_regs,
dwc_otg_qtd_t *  qtd 
) [static]
++
++
++ ++

++Handles a host Channel Halted interrupt in DMA mode. ++

++This handler determines the reason the channel halted and proceeds accordingly. ++

++

Todo:
This is here because of a possible hardware bug. Spec says that on SPLIT-ISOC OUT transfers in DMA mode that a HALT interrupt w/ACK bit set should occur, but I only see the XFERCOMP bit, even with it masked out. This is a workaround for that behavior. Should fix this when hardware is fixed.
++ ++

++Definition at line 1784 of file dwc_otg_hcd_intr.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
static int32_t handle_hc_chhltd_intr (dwc_otg_hcd_t *  hcd,
dwc_hc_t *  hc,
dwc_otg_hc_regs_t *  hc_regs,
dwc_otg_qtd_t *  qtd 
) [static]
++
++
++ ++

++Handles a host channel Channel Halted interrupt. ++

++In slave mode, this handler is called only when the driver specifically requests a halt. This occurs during handling other host channel interrupts (e.g. nak, xacterr, stall, nyet, etc.).

++In DMA mode, this is the interrupt that occurs when the core has finished processing a transfer on a channel. Other host channel interrupts (except ahberr) are disabled in DMA mode. ++

++Definition at line 1928 of file dwc_otg_hcd_intr.c. ++

++

++

Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__hcd__linux_8c-source.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__hcd__linux_8c-source.html 2013-07-26 19:31:21.000000000 +0000 +@@ -0,0 +1,726 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_hcd_linux.c Source File ++ ++ ++ ++ ++
++
++
++
++

dwc_otg_hcd_linux.c

Go to the documentation of this file.
00001 /* ==========================================================================
++00002  * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd_linux.c $
++00003  * $Revision: #11 $
++00004  * $Date: 2009/04/21 $
++00005  * $Change: 1237476 $
++00006  *
++00007  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
++00008  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
++00009  * otherwise expressly agreed to in writing between Synopsys and you.
++00010  *
++00011  * The Software IS NOT an item of Licensed Software or Licensed Product under
++00012  * any End User Software License Agreement or Agreement for Licensed Product
++00013  * with Synopsys or any supplement thereto. You are permitted to use and
++00014  * redistribute this Software in source and binary forms, with or without
++00015  * modification, provided that redistributions of source code must retain this
++00016  * notice. You may not view, use, disclose, copy or distribute this file or
++00017  * any information contained herein except pursuant to this license grant from
++00018  * Synopsys. If you do not agree with this notice, including the disclaimer
++00019  * below, then you are not authorized to use the Software.
++00020  *
++00021  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
++00022  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++00023  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++00024  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
++00025  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++00026  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
++00027  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
++00028  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
++00029  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
++00030  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
++00031  * DAMAGE.
++00032  * ========================================================================== */
++00033 #ifndef DWC_DEVICE_ONLY
++00034 
++00041 #include <linux/kernel.h>
++00042 #include <linux/module.h>
++00043 #include <linux/moduleparam.h>
++00044 #include <linux/init.h>
++00045 #include <linux/device.h>
++00046 #include <linux/errno.h>
++00047 #include <linux/list.h>
++00048 #include <linux/interrupt.h>
++00049 #include <linux/string.h>
++00050 #include <linux/dma-mapping.h>
++00051 #include <linux/version.h>
++00052 #include <asm/io.h>
++00053 
++00054 #ifdef LM_INTERFACE
++00055 #include <asm/arch/regs-irq.h>
++00056 #include <asm/arch/lm.h>
++00057 #include <asm/arch/irqs.h>
++00058 #endif
++00059 
++00060 #include <linux/usb.h>
++00061 #include <../drivers/usb/core/hcd.h>
++00062 
++00063 #include "dwc_otg_hcd_if.h"
++00064 #include "dwc_otg_dbg.h"
++00065 #include "dwc_otg_driver.h"
++00066 
++00071 #define dwc_ep_addr_to_endpoint(_bEndpointAddress_) ((_bEndpointAddress_ & USB_ENDPOINT_NUMBER_MASK) | \
++00072                                                      ((_bEndpointAddress_ & USB_DIR_IN) != 0) << 4)
++00073 
++00074 static const char dwc_otg_hcd_name[] = "dwc_otg_hcd";
++00075 
++00078 static int urb_enqueue(struct usb_hcd *hcd,
++00079                        struct usb_host_endpoint *ep,
++00080                        struct urb *urb, gfp_t mem_flags);
++00081 
++00082 static int urb_dequeue(struct usb_hcd *hcd, struct urb *urb);
++00083 
++00084 static void endpoint_disable(struct usb_hcd *hcd, struct usb_host_endpoint *ep);
++00085 
++00086 static irqreturn_t dwc_otg_hcd_irq(struct usb_hcd *hcd);
++00087 extern int hcd_start(struct usb_hcd *hcd);
++00088 extern void hcd_stop(struct usb_hcd *hcd);
++00089 static int get_frame_number(struct usb_hcd *hcd);
++00090 extern int hub_status_data(struct usb_hcd *hcd, char *buf);
++00091 extern int hub_control(struct usb_hcd *hcd,
++00092                        u16 typeReq,
++00093                        u16 wValue, u16 wIndex, char *buf, u16 wLength);
++00094 
++00095 struct wrapper_priv_data {
++00096         dwc_otg_hcd_t *dwc_otg_hcd;
++00097 };
++00098 
++00101 static struct hc_driver dwc_otg_hc_driver = {
++00102 
++00103         .description = dwc_otg_hcd_name,
++00104         .product_desc = "DWC OTG Controller",
++00105         .hcd_priv_size = sizeof(struct wrapper_priv_data),
++00106 
++00107         .irq = dwc_otg_hcd_irq,
++00108 
++00109         .flags = HCD_MEMORY | HCD_USB2,
++00110 
++00111         //.reset =              
++00112         .start = hcd_start,
++00113         //.suspend =            
++00114         //.resume =             
++00115         .stop = hcd_stop,
++00116 
++00117         .urb_enqueue = urb_enqueue,
++00118         .urb_dequeue = urb_dequeue,
++00119         .endpoint_disable = endpoint_disable,
++00120 
++00121         .get_frame_number = get_frame_number,
++00122 
++00123         .hub_status_data = hub_status_data,
++00124         .hub_control = hub_control,
++00125         //.bus_suspend =                
++00126         //.bus_resume =         
++00127 };
++00128 
++00130 static inline dwc_otg_hcd_t *hcd_to_dwc_otg_hcd(struct usb_hcd *hcd)
++00131 {
++00132         struct wrapper_priv_data *p;
++00133         p = (struct wrapper_priv_data *)(hcd->hcd_priv);
++00134         return p->dwc_otg_hcd;
++00135 }
++00136 
++00138 static inline struct usb_hcd *dwc_otg_hcd_to_hcd(dwc_otg_hcd_t * dwc_otg_hcd)
++00139 {
++00140         return dwc_otg_hcd_get_priv_data(dwc_otg_hcd);
++00141 }
++00142 
++00144 inline struct usb_host_endpoint *dwc_urb_to_endpoint(struct urb *urb)
++00145 {
++00146         struct usb_device *dev = urb->dev;
++00147         int ep_num = usb_pipeendpoint(urb->pipe);
++00148 
++00149         if (usb_pipein(urb->pipe))
++00150                 return dev->ep_in[ep_num];
++00151         else
++00152                 return dev->ep_out[ep_num];
++00153 }
++00154 
++00155 static int _disconnect(dwc_otg_hcd_t * hcd)
++00156 {
++00157         struct usb_hcd *usb_hcd = dwc_otg_hcd_to_hcd(hcd);
++00158 
++00159         usb_hcd->self.is_b_host = 0;
++00160         return 0;
++00161 }
++00162 
++00163 static int _start(dwc_otg_hcd_t * hcd)
++00164 {
++00165         struct usb_hcd *usb_hcd = dwc_otg_hcd_to_hcd(hcd);
++00166 
++00167         usb_hcd->self.is_b_host = dwc_otg_hcd_is_b_host(hcd);
++00168         hcd_start(usb_hcd);
++00169 
++00170         return 0;
++00171 }
++00172 
++00173 static int _hub_info(dwc_otg_hcd_t * hcd, void *urb_handle, uint32_t * hub_addr,
++00174                      uint32_t * port_addr)
++00175 {
++00176         struct urb *urb = (struct urb *)urb_handle;
++00177         if (urb->dev->tt) {
++00178                 *hub_addr = urb->dev->tt->hub->devnum;
++00179         } else {
++00180                 *hub_addr = 0;
++00181         }
++00182         *port_addr = urb->dev->ttport;
++00183         return 0;
++00184 }
++00185 
++00186 static int _speed(dwc_otg_hcd_t * hcd, void *urb_handle)
++00187 {
++00188         struct urb *urb = (struct urb *)urb_handle;
++00189         return urb->dev->speed;
++00190 }
++00191 
++00192 static int _get_b_hnp_enable(dwc_otg_hcd_t * hcd)
++00193 {
++00194         struct usb_hcd *usb_hcd = dwc_otg_hcd_to_hcd(hcd);
++00195         return usb_hcd->self.b_hnp_enable;
++00196 }
++00197 
++00198 static void allocate_bus_bandwidth(struct usb_hcd *hcd, uint32_t bw,
++00199                                    struct urb *urb)
++00200 {
++00201         hcd_to_bus(hcd)->bandwidth_allocated += bw / urb->interval;
++00202         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
++00203                 hcd_to_bus(hcd)->bandwidth_isoc_reqs++;
++00204         } else {
++00205                 hcd_to_bus(hcd)->bandwidth_int_reqs++;
++00206         }
++00207 }
++00208 
++00209 static void free_bus_bandwidth(struct usb_hcd *hcd, uint32_t bw,
++00210                                struct urb *urb)
++00211 {
++00212         hcd_to_bus(hcd)->bandwidth_allocated -= bw / urb->interval;
++00213         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
++00214                 hcd_to_bus(hcd)->bandwidth_isoc_reqs--;
++00215         } else {
++00216                 hcd_to_bus(hcd)->bandwidth_int_reqs--;
++00217         }
++00218 }
++00219 
++00224 static int _complete(dwc_otg_hcd_t * hcd, void *urb_handle,
++00225                      dwc_otg_hcd_urb_t * dwc_otg_urb, int32_t status)
++00226 {
++00227         struct urb *urb = (struct urb *)urb_handle;
++00228 #ifdef DEBUG
++00229         if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
++00230                 DWC_PRINTF("%s: urb %p, device %d, ep %d %s, status=%d\n",
++00231                            __func__, urb, usb_pipedevice(urb->pipe),
++00232                            usb_pipeendpoint(urb->pipe),
++00233                            usb_pipein(urb->pipe) ? "IN" : "OUT", status);
++00234                 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
++00235                         int i;
++00236                         for (i = 0; i < urb->number_of_packets; i++) {
++00237                                 DWC_PRINTF("  ISO Desc %d status: %d\n",
++00238                                            i, urb->iso_frame_desc[i].status);
++00239                         }
++00240                 }
++00241         }
++00242 #endif
++00243 
++00244         urb->actual_length = dwc_otg_hcd_urb_get_actual_length(dwc_otg_urb);
++00245         /* Convert status value. */
++00246         switch (status) {
++00247         case -DWC_E_PROTOCOL:
++00248                 status = -EPROTO;
++00249                 break;
++00250         case -DWC_E_IN_PROGRESS:
++00251                 status = -EINPROGRESS;
++00252                 break;
++00253         case -DWC_E_PIPE:
++00254                 status = -EPIPE;
++00255                 break;
++00256         case -DWC_E_IO:
++00257                 status = -EIO;
++00258                 break;
++00259         case -DWC_E_TIMEOUT:
++00260                 status = -ETIMEDOUT;
++00261                 break;
++00262         case -DWC_E_OVERFLOW:
++00263                 status = -EOVERFLOW;
++00264                 break;
++00265         default:
++00266                 if (status) {
++00267                         DWC_PRINTF("Uknown urb status %d\n", status);
++00268 
++00269                 }
++00270         }
++00271 
++00272         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
++00273                 int i;
++00274 
++00275                 urb->error_count = dwc_otg_hcd_urb_get_error_count(dwc_otg_urb);
++00276                 for (i = 0; i < urb->number_of_packets; ++i) {
++00277                         urb->iso_frame_desc[i].actual_length =
++00278                             dwc_otg_hcd_urb_get_iso_desc_actual_length
++00279                             (dwc_otg_urb, i);
++00280                         urb->iso_frame_desc[i].status =
++00281                             dwc_otg_hcd_urb_get_iso_desc_status
++00282                             (dwc_otg_urb, i);
++00283                 }
++00284         }
++00285 
++00286         urb->status = status;
++00287         urb->hcpriv = NULL;
++00288         if (!status) {
++00289                 if ((urb->transfer_flags & URB_SHORT_NOT_OK) &&
++00290                     (urb->actual_length < urb->transfer_buffer_length)) {
++00291                         urb->status = -EREMOTEIO;
++00292                 }
++00293         }
++00294 
++00295         if ((usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) ||
++00296             (usb_pipetype(urb->pipe) == PIPE_INTERRUPT)) {
++00297                 struct usb_host_endpoint *ep = dwc_urb_to_endpoint(urb);
++00298                 if (ep) {
++00299                         free_bus_bandwidth(dwc_otg_hcd_to_hcd(hcd),
++00300                                            dwc_otg_hcd_get_ep_bandwidth(hcd,
++00301                                                                         ep->
++00302                                                                         hcpriv),
++00303                                            urb);
++00304                 }
++00305         }
++00306 
++00307         dwc_free(dwc_otg_urb);
++00308         usb_hcd_giveback_urb(dwc_otg_hcd_to_hcd(hcd), urb);
++00309         return 0;
++00310 }
++00311 
++00312 static struct dwc_otg_hcd_function_ops hcd_fops = {
++00313         .start = _start,
++00314         .disconnect = _disconnect,
++00315         .hub_info = _hub_info,
++00316         .speed = _speed,
++00317         .complete = _complete,
++00318         .get_b_hnp_enable = _get_b_hnp_enable,
++00319 };
++00320 
++00327 int hcd_init(
++00328 #ifdef LM_INTERFACE
++00329         struct lm_device *_dev
++00330 #elif  PCI_INTERFACE
++00331         struct pci_dev *_dev
++00332 #endif
++00333         )
++00334 {
++00335         struct usb_hcd *hcd = NULL;
++00336         dwc_otg_hcd_t *dwc_otg_hcd = NULL;
++00337 #ifdef LM_INTERFACE
++00338         dwc_otg_device_t *otg_dev = lm_get_drvdata(_dev);
++00339 #elif  PCI_INTERFACE
++00340         dwc_otg_device_t *otg_dev = pci_get_drvdata(_dev);
++00341 #endif
++00342 
++00343         int retval = 0;
++00344 
++00345         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD INIT\n");
++00346 
++00347         /* Set device flags indicating whether the HCD supports DMA. */
++00348         if (dwc_otg_is_dma_enable(otg_dev->core_if)) {
++00349 #ifdef LM_INTERFACE
++00350                 _dev->dev.dma_mask = (void *)~0;
++00351                 _dev->dev.coherent_dma_mask = ~0;
++00352 #elif  PCI_INTERFACE
++00353                 pci_set_dma_mask(_dev,DMA_32BIT_MASK);          
++00354                 pci_set_consistent_dma_mask(_dev,DMA_32BIT_MASK);
++00355 #endif
++00356 
++00357         } else {
++00358 #ifdef LM_INTERFACE
++00359                 _dev->dev.dma_mask = (void *)0;
++00360                 _dev->dev.coherent_dma_mask = 0;
++00361 #elif  PCI_INTERFACE
++00362                 pci_set_dma_mask(_dev,0);               
++00363                 pci_set_consistent_dma_mask(_dev,0);
++00364 #endif
++00365         }
++00366 
++00367         /*
++00368          * Allocate memory for the base HCD plus the DWC OTG HCD.
++00369          * Initialize the base HCD.
++00370          */
++00371         hcd = usb_create_hcd(&dwc_otg_hc_driver, &_dev->dev, _dev->dev.bus_id);
++00372         if (!hcd) {
++00373                 retval = -ENOMEM;
++00374                 goto error1;
++00375         }
++00376 
++00377         hcd->regs = otg_dev->base;
++00378 
++00379         /* Initialize the DWC OTG HCD. */
++00380         dwc_otg_hcd = dwc_otg_hcd_alloc_hcd();
++00381         if (!dwc_otg_hcd) {
++00382                 goto error2;
++00383         }
++00384         ((struct wrapper_priv_data *)(hcd->hcd_priv))->dwc_otg_hcd =
++00385             dwc_otg_hcd;
++00386         otg_dev->hcd = dwc_otg_hcd;
++00387 
++00388         if (dwc_otg_hcd_init(dwc_otg_hcd, otg_dev->core_if)) {
++00389                 goto error2;
++00390         }
++00391 
++00392         hcd->self.otg_port = dwc_otg_hcd_otg_port(dwc_otg_hcd);
++00393 
++00394         /*
++00395          * Finish generic HCD initialization and start the HCD. This function
++00396          * allocates the DMA buffer pool, registers the USB bus, requests the
++00397          * IRQ line, and calls hcd_start method.
++00398          */
++00399         retval = usb_add_hcd(hcd, _dev->irq, SA_SHIRQ);
++00400         if (retval < 0) {
++00401                 goto error2;
++00402         }
++00403 
++00404         dwc_otg_hcd_set_priv_data(dwc_otg_hcd, hcd);
++00405         return 0;
++00406 
++00407       error2:
++00408         usb_put_hcd(hcd);
++00409       error1:
++00410         return retval;
++00411 }
++00412 
++00417 void hcd_remove(
++00418 #ifdef LM_INTERFACE
++00419         struct lm_device *_dev
++00420 #elif  PCI_INTERFACE
++00421         struct pci_dev *_dev
++00422 #endif
++00423         )
++00424 {
++00425 #ifdef LM_INTERFACE
++00426         dwc_otg_device_t *otg_dev = lm_get_drvdata(_dev);
++00427 #elif  PCI_INTERFACE
++00428         dwc_otg_device_t *otg_dev = pci_get_drvdata(_dev);
++00429 #endif
++00430 
++00431         dwc_otg_hcd_t *dwc_otg_hcd;
++00432         struct usb_hcd *hcd;
++00433 
++00434         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD REMOVE\n");
++00435 
++00436         if (!otg_dev) {
++00437                 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev NULL!\n", __func__);
++00438                 return;
++00439         }
++00440 
++00441         dwc_otg_hcd = otg_dev->hcd;
++00442 
++00443         if (!dwc_otg_hcd) {
++00444                 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->hcd NULL!\n", __func__);
++00445                 return;
++00446         }
++00447 
++00448         hcd = dwc_otg_hcd_to_hcd(dwc_otg_hcd);
++00449 
++00450         if (!hcd) {
++00451                 DWC_DEBUGPL(DBG_ANY,
++00452                             "%s: dwc_otg_hcd_to_hcd(dwc_otg_hcd) NULL!\n",
++00453                             __func__);
++00454                 return;
++00455         }
++00456         usb_remove_hcd(hcd);
++00457         dwc_otg_hcd_set_priv_data(dwc_otg_hcd, NULL);
++00458         dwc_otg_hcd_remove(dwc_otg_hcd);
++00459         usb_put_hcd(hcd);
++00460 }
++00461 
++00462 /* =========================================================================
++00463  *  Linux HC Driver Functions
++00464  * ========================================================================= */
++00465 
++00469 int hcd_start(struct usb_hcd *hcd)
++00470 {
++00471         dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
++00472         struct usb_bus *bus;
++00473 
++00474         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD START\n");
++00475         bus = hcd_to_bus(hcd);
++00476 
++00477         hcd->state = HC_STATE_RUNNING;
++00478         if (dwc_otg_hcd_start(dwc_otg_hcd, &hcd_fops)) {
++00479                 return 0;
++00480         }
++00481 
++00482         /* Initialize and connect root hub if one is not already attached */
++00483         if (bus->root_hub) {
++00484                 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Has Root Hub\n");
++00485                 /* Inform the HUB driver to resume. */
++00486                 usb_hcd_resume_root_hub(hcd);
++00487         }
++00488 
++00489         return 0;
++00490 }
++00491 
++00496 void hcd_stop(struct usb_hcd *hcd)
++00497 {
++00498         dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
++00499 
++00500         dwc_otg_hcd_stop(dwc_otg_hcd);
++00501 }
++00502 
++00504 static int get_frame_number(struct usb_hcd *hcd)
++00505 {
++00506         dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
++00507 
++00508         return dwc_otg_hcd_get_frame_number(dwc_otg_hcd);
++00509 }
++00510 
++00511 #ifdef DEBUG
++00512 static void dump_urb_info(struct urb *urb, char *fn_name)
++00513 {
++00514         DWC_PRINTF("%s, urb %p\n", fn_name, urb);
++00515         DWC_PRINTF("  Device address: %d\n", usb_pipedevice(urb->pipe));
++00516         DWC_PRINTF("  Endpoint: %d, %s\n", usb_pipeendpoint(urb->pipe),
++00517                    (usb_pipein(urb->pipe) ? "IN" : "OUT"));
++00518         DWC_PRINTF("  Endpoint type: %s\n", ( {
++00519                                              char *pipetype;
++00520                                              switch (usb_pipetype(urb->pipe)) {
++00521 case PIPE_CONTROL:
++00522 pipetype = "CONTROL"; break; case PIPE_BULK:
++00523 pipetype = "BULK"; break; case PIPE_INTERRUPT:
++00524 pipetype = "INTERRUPT"; break; case PIPE_ISOCHRONOUS:
++00525 pipetype = "ISOCHRONOUS"; break; default:
++00526                                              pipetype = "UNKNOWN"; break;};
++00527                                              pipetype;}
++00528                    )) ;
++00529         DWC_PRINTF("  Speed: %s\n", ( {
++00530                                      char *speed; switch (urb->dev->speed) {
++00531 case USB_SPEED_HIGH:
++00532 speed = "HIGH"; break; case USB_SPEED_FULL:
++00533 speed = "FULL"; break; case USB_SPEED_LOW:
++00534 speed = "LOW"; break; default:
++00535                                      speed = "UNKNOWN"; break;};
++00536                                      speed;}
++00537                    )) ;
++00538         DWC_PRINTF("  Max packet size: %d\n",
++00539                    usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe)));
++00540         DWC_PRINTF("  Data buffer length: %d\n", urb->transfer_buffer_length);
++00541         DWC_PRINTF("  Transfer buffer: %p, Transfer DMA: %p\n",
++00542                    urb->transfer_buffer, (void *)urb->transfer_dma);
++00543         DWC_PRINTF("  Setup buffer: %p, Setup DMA: %p\n",
++00544                    urb->setup_packet, (void *)urb->setup_dma);
++00545         DWC_PRINTF("  Interval: %d\n", urb->interval);
++00546         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
++00547                 int i;
++00548                 for (i = 0; i < urb->number_of_packets; i++) {
++00549                         DWC_PRINTF("  ISO Desc %d:\n", i);
++00550                         DWC_PRINTF("    offset: %d, length %d\n",
++00551                                    urb->iso_frame_desc[i].offset,
++00552                                    urb->iso_frame_desc[i].length);
++00553                 }
++00554         }
++00555 }
++00556 
++00557 #endif
++00558 
++00562 static int urb_enqueue(struct usb_hcd *hcd,
++00563                        struct usb_host_endpoint *ep,
++00564                        struct urb *urb, gfp_t mem_flags)
++00565 {
++00566         int retval = 0;
++00567         dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
++00568         dwc_otg_hcd_urb_t *dwc_otg_urb;
++00569         int i;
++00570         int alloc_bandwidth = 0;
++00571         uint8_t ep_type = 0;
++00572         uint32_t flags = 0;
++00573         void *buf;
++00574 
++00575 #ifdef DEBUG
++00576         if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
++00577                 dump_urb_info(urb, "urb_enqueue");
++00578         }
++00579 #endif
++00580 
++00581         if ((usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
++00582             || (usb_pipetype(urb->pipe) == PIPE_INTERRUPT)) {
++00583                 if (!dwc_otg_hcd_is_bandwidth_allocated
++00584                     (dwc_otg_hcd, &ep->hcpriv)) {
++00585                         alloc_bandwidth = 1;
++00586                 }
++00587         }
++00588 
++00589         switch (usb_pipetype(urb->pipe)) {
++00590         case PIPE_CONTROL:
++00591                 ep_type = USB_ENDPOINT_XFER_CONTROL;
++00592                 break;
++00593         case PIPE_ISOCHRONOUS:
++00594                 ep_type = USB_ENDPOINT_XFER_ISOC;
++00595                 break;
++00596         case PIPE_BULK:
++00597                 ep_type = USB_ENDPOINT_XFER_BULK;
++00598                 break;
++00599         case PIPE_INTERRUPT:
++00600                 ep_type = USB_ENDPOINT_XFER_INT;
++00601                 break;
++00602         default:
++00603                 DWC_WARN("Wrong ep type\n");
++00604         }
++00605 
++00606         dwc_otg_urb = dwc_otg_hcd_urb_alloc(dwc_otg_hcd,
++00607                                             urb->number_of_packets,
++00608                                             mem_flags == GFP_ATOMIC ? 1 : 0);
++00609 
++00610         dwc_otg_hcd_urb_set_pipeinfo(dwc_otg_urb, usb_pipedevice(urb->pipe),
++00611                                      usb_pipeendpoint(urb->pipe), ep_type,
++00612                                      usb_pipein(urb->pipe),
++00613                                      usb_maxpacket(urb->dev, urb->pipe,
++00614                                                    !(usb_pipein(urb->pipe))));
++00615 
++00616         buf = urb->transfer_buffer;
++00617         if (hcd->self.uses_dma) {
++00618                 /*
++00619                  * Calculate virtual address from physical address,
++00620                  * because some class driver may not fill transfer_buffer.
++00621                  * In Buffer DMA mode virual address is used,
++00622                  * when handling non DWORD aligned buffers.
++00623                  */
++00624                 buf = phys_to_virt(urb->transfer_dma);
++00625         }
++00626         
++00627         if (!(urb->transfer_flags & URB_NO_INTERRUPT))
++00628                 flags |= URB_GIVEBACK_ASAP;
++00629         if (urb->transfer_flags & URB_ZERO_PACKET)
++00630                 flags |= URB_SEND_ZERO_PACKET;
++00631 
++00632         dwc_otg_hcd_urb_set_params(dwc_otg_urb, urb, buf,
++00633                                    urb->transfer_dma,
++00634                                    urb->transfer_buffer_length,
++00635                                    urb->setup_packet, 
++00636                                    urb->setup_dma,
++00637                                    flags,
++00638                                    urb->interval);
++00639 
++00640         for (i = 0; i < urb->number_of_packets; ++i) {
++00641                 dwc_otg_hcd_urb_set_iso_desc_params(dwc_otg_urb, i,
++00642                                                     urb->iso_frame_desc[i].
++00643                                                     offset,
++00644                                                     urb->iso_frame_desc[i].
++00645                                                     length);
++00646         }
++00647 
++00648         urb->hcpriv = dwc_otg_urb;
++00649         retval = dwc_otg_hcd_urb_enqueue(dwc_otg_hcd, dwc_otg_urb, &ep->hcpriv);
++00650         if (!retval) {
++00651                 if (alloc_bandwidth) {
++00652                         allocate_bus_bandwidth(hcd,
++00653                                                dwc_otg_hcd_get_ep_bandwidth
++00654                                                (dwc_otg_hcd, ep->hcpriv), urb);
++00655                 }
++00656         } else {
++00657                 if (retval == -DWC_E_NO_DEVICE) {
++00658                         retval = -ENODEV;
++00659                 }
++00660         }
++00661 
++00662         return retval;
++00663 }
++00664 
++00667 static int urb_dequeue(struct usb_hcd *hcd, struct urb *urb)
++00668 {
++00669         dwc_otg_hcd_t *dwc_otg_hcd;
++00670         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD URB Dequeue\n");
++00671 
++00672         dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
++00673 
++00674 #ifdef DEBUG
++00675         if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
++00676                 dump_urb_info(urb, "urb_dequeue");
++00677         }
++00678 #endif
++00679         dwc_otg_hcd_urb_dequeue(dwc_otg_hcd, urb->hcpriv);
++00680 
++00681         dwc_free(urb->hcpriv);
++00682         urb->hcpriv = NULL;
++00683 
++00684         /* Higher layer software sets URB status. */
++00685         usb_hcd_giveback_urb(hcd, urb);
++00686         if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
++00687                 DWC_PRINTF("Called usb_hcd_giveback_urb()\n");
++00688                 DWC_PRINTF("  urb->status = %d\n", urb->status);
++00689         }
++00690 
++00691         return 0;
++00692 }
++00693 
++00694 /* Frees resources in the DWC_otg controller related to a given endpoint. Also
++00695  * clears state in the HCD related to the endpoint. Any URBs for the endpoint
++00696  * must already be dequeued. */
++00697 static void endpoint_disable(struct usb_hcd *hcd, struct usb_host_endpoint *ep)
++00698 {
++00699         dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
++00700 
++00701         DWC_DEBUGPL(DBG_HCD,
++00702                     "DWC OTG HCD EP DISABLE: _bEndpointAddress=0x%02x, "
++00703                     "endpoint=%d\n", ep->desc.bEndpointAddress,
++00704                     dwc_ep_addr_to_endpoint(ep->desc.bEndpointAddress));
++00705         dwc_otg_hcd_endpoint_disable(dwc_otg_hcd, ep->hcpriv, 250);
++00706         ep->hcpriv = NULL;
++00707 }
++00708 
++00714 static irqreturn_t dwc_otg_hcd_irq(struct usb_hcd *hcd)
++00715 {
++00716         dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
++00717         int32_t retval = dwc_otg_hcd_handle_intr(dwc_otg_hcd);
++00718         if (retval != 0) {
++00719                 S3C2410X_CLEAR_EINTPEND();
++00720         }
++00721         return IRQ_RETVAL(retval);
++00722 }
++00723 
++00728 int hub_status_data(struct usb_hcd *hcd, char *buf)
++00729 {
++00730         dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
++00731 
++00732         buf[0] = 0;
++00733         buf[0] |= (dwc_otg_hcd_is_status_changed(dwc_otg_hcd, 1)) << 1;
++00734 
++00735         return (buf[0] != 0);
++00736 }
++00737 
++00739 int hub_control(struct usb_hcd *hcd,
++00740                 u16 typeReq, u16 wValue, u16 wIndex, char *buf, u16 wLength)
++00741 {
++00742         int retval;
++00743 
++00744         retval = dwc_otg_hcd_hub_control(hcd_to_dwc_otg_hcd(hcd),
++00745                                          typeReq, wValue, wIndex, buf, wLength);
++00746 
++00747         switch (retval) {
++00748         case -DWC_E_INVALID:
++00749                 retval = -EINVAL;
++00750                 break;
++00751         }
++00752 
++00753         return retval;
++00754 }
++00755 
++00756 #endif                          /* DWC_DEVICE_ONLY */
++
Generated on Tue May 5 02:22:48 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__hcd__linux_8c.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__hcd__linux_8c.html 2013-07-26 19:31:21.000000000 +0000 +@@ -0,0 +1,514 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_hcd_linux.c File Reference ++ ++ ++ ++ ++
++
++
++
++

dwc_otg_hcd_linux.c File Reference

This file contains the implementation of the HCD. More... ++

++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/moduleparam.h>
++#include <linux/init.h>
++#include <linux/device.h>
++#include <linux/errno.h>
++#include <linux/list.h>
++#include <linux/interrupt.h>
++#include <linux/string.h>
++#include <linux/dma-mapping.h>
++#include <linux/version.h>
++#include <asm/io.h>
++#include <linux/usb.h>
++#include <../drivers/usb/core/hcd.h>
++#include "dwc_otg_hcd_if.h"
++#include "dwc_otg_dbg.h"
++#include "dwc_otg_driver.h"
++ ++

++Go to the source code of this file. ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++

Data Structures

struct  wrapper_priv_data

Linux HC Driver API Functions

static int urb_enqueue (struct usb_hcd *hcd, struct usb_host_endpoint *ep, struct urb *urb, gfp_t mem_flags)
 Starts processing a USB transfer request specified by a USB Request Block (URB).
static int urb_dequeue (struct usb_hcd *hcd, struct urb *urb)
 Aborts/cancels a USB transfer request.
++static void endpoint_disable (struct usb_hcd *hcd, struct usb_host_endpoint *ep)
static irqreturn_t dwc_otg_hcd_irq (struct usb_hcd *hcd)
 Handles host mode interrupts for the DWC_otg controller.
int hcd_start (struct usb_hcd *hcd)
 Initializes the DWC_otg controller and its root hub and prepares it for host mode operation.
void hcd_stop (struct usb_hcd *hcd)
 Halts the DWC_otg host mode operations in a clean manner.
++static int get_frame_number (struct usb_hcd *hcd)
 Returns the current frame number.
int hub_status_data (struct usb_hcd *hcd, char *buf)
 Creates Status Change bitmap for the root hub and root port.
++int hub_control (struct usb_hcd *hcd, u16 typeReq, u16 wValue, u16 wIndex, char *buf, u16 wLength)
 Handles hub class-specific requests.

Defines

#define dwc_ep_addr_to_endpoint(_bEndpointAddress_)
 Gets the endpoint number from a _bEndpointAddress argument.

Functions

++static dwc_otg_hcd_t * hcd_to_dwc_otg_hcd (struct usb_hcd *hcd)
 Gets the dwc_otg_hcd from a struct usb_hcd.
++static struct usb_hcd * dwc_otg_hcd_to_hcd (dwc_otg_hcd_t *dwc_otg_hcd)
 Gets the struct usb_hcd that contains a dwc_otg_hcd_t.
++usb_host_endpoint * dwc_urb_to_endpoint (struct urb *urb)
 Gets the usb_host_endpoint associated with an URB.
++static int _disconnect (dwc_otg_hcd_t *hcd)
++static int _start (dwc_otg_hcd_t *hcd)
++static int _hub_info (dwc_otg_hcd_t *hcd, void *urb_handle, uint32_t *hub_addr, uint32_t *port_addr)
++static int _speed (dwc_otg_hcd_t *hcd, void *urb_handle)
++static int _get_b_hnp_enable (dwc_otg_hcd_t *hcd)
++static void allocate_bus_bandwidth (struct usb_hcd *hcd, uint32_t bw, struct urb *urb)
++static void free_bus_bandwidth (struct usb_hcd *hcd, uint32_t bw, struct urb *urb)
static int _complete (dwc_otg_hcd_t *hcd, void *urb_handle, dwc_otg_hcd_urb_t *dwc_otg_urb, int32_t status)
 Sets the final status of an URB and returns it to the device driver.
int hcd_init ()
 Initializes the HCD.
void hcd_remove ()
 Removes the HCD.

Variables

++static const char dwc_otg_hcd_name [] = "dwc_otg_hcd"
static struct hc_driver dwc_otg_hc_driver
static struct dwc_otg_hcd_function_ops hcd_fops
++

Detailed Description

++This file contains the implementation of the HCD. ++

++In Linux, the HCD implements the hc_driver API. ++

++Definition in file dwc_otg_hcd_linux.c.

Define Documentation

++ ++
++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
#define dwc_ep_addr_to_endpoint (_bEndpointAddress_   ) 
++
++
++ ++

++Value:

((_bEndpointAddress_ & USB_ENDPOINT_NUMBER_MASK) | \
++                                                     ((_bEndpointAddress_ & USB_DIR_IN) != 0) << 4)
++
Gets the endpoint number from a _bEndpointAddress argument. ++

++The endpoint is qualified with its direction (possible 32 endpoints per device). ++

++Definition at line 71 of file dwc_otg_hcd_linux.c. ++

++

++

Function Documentation

++ ++
++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
static int urb_enqueue (struct usb_hcd *  hcd,
struct usb_host_endpoint *  ep,
struct urb *  urb,
gfp_t  mem_flags 
) [static]
++
++
++ ++

++Starts processing a USB transfer request specified by a USB Request Block (URB). ++

++mem_flags indicates the type of memory allocation to use while processing this URB. ++

++Definition at line 562 of file dwc_otg_hcd_linux.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
static int urb_dequeue (struct usb_hcd *  hcd,
struct urb *  urb 
) [static]
++
++
++ ++

++Aborts/cancels a USB transfer request. ++

++Always returns 0 to indicate success. ++

++Definition at line 667 of file dwc_otg_hcd_linux.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
static irqreturn_t dwc_otg_hcd_irq (struct usb_hcd *  hcd  )  [static]
++
++
++ ++

++Handles host mode interrupts for the DWC_otg controller. ++

++Returns IRQ_NONE if there was no interrupt to handle. Returns IRQ_HANDLED if there was a valid interrupt.

++This function is called by the USB core when an interrupt occurs ++

++Definition at line 714 of file dwc_otg_hcd_linux.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int hcd_start (struct usb_hcd *  hcd  ) 
++
++
++ ++

++Initializes the DWC_otg controller and its root hub and prepares it for host mode operation. ++

++Activates the root port. Returns 0 on success and a negative error code on failure. ++

++Definition at line 469 of file dwc_otg_hcd_linux.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void hcd_stop (struct usb_hcd *  hcd  ) 
++
++
++ ++

++Halts the DWC_otg host mode operations in a clean manner. ++

++USB transfers are stopped. ++

++Definition at line 496 of file dwc_otg_hcd_linux.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int hub_status_data (struct usb_hcd *  hcd,
char *  buf 
)
++
++
++ ++

++Creates Status Change bitmap for the root hub and root port. ++

++The bitmap is returned in buf. Bit 0 is the status change indicator for the root hub. Bit 1 is the status change indicator for the single root port. Returns 1 if either change indicator is 1, otherwise returns 0. ++

++Definition at line 728 of file dwc_otg_hcd_linux.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
static int _complete (dwc_otg_hcd_t *  hcd,
void *  urb_handle,
dwc_otg_hcd_urb_t *  dwc_otg_urb,
int32_t  status 
) [static]
++
++
++ ++

++Sets the final status of an URB and returns it to the device driver. ++

++Any required cleanup of the URB is performed. ++

++Definition at line 224 of file dwc_otg_hcd_linux.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++
int hcd_init (  ) 
++
++
++ ++

++Initializes the HCD. ++

++This function allocates memory for and initializes the static parts of the usb_hcd and dwc_otg_hcd structures. It also registers the USB bus with the core and calls the hc_driver->start() function. It returns a negative error on failure. ++

++Definition at line 327 of file dwc_otg_hcd_linux.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++
void hcd_remove (  ) 
++
++
++ ++

++Removes the HCD. ++

++Frees memory and resources associated with the HCD and deregisters the bus. ++

++Definition at line 417 of file dwc_otg_hcd_linux.c. ++

++

++

Variable Documentation

++ ++
++
++ ++ ++ ++ ++
struct hc_driver dwc_otg_hc_driver [static]
++
++
++ ++

++Initial value:

 {
++
++        .description = dwc_otg_hcd_name,
++        .product_desc = "DWC OTG Controller",
++        .hcd_priv_size = sizeof(struct wrapper_priv_data),
++
++        .irq = dwc_otg_hcd_irq,
++
++        .flags = HCD_MEMORY | HCD_USB2,
++
++        
++        .start = hcd_start,
++        
++        
++        .stop = hcd_stop,
++
++        .urb_enqueue = urb_enqueue,
++        .urb_dequeue = urb_dequeue,
++        .endpoint_disable = endpoint_disable,
++
++        .get_frame_number = get_frame_number,
++
++        .hub_status_data = hub_status_data,
++        .hub_control = hub_control,
++        
++        
++}
++
++

++Definition at line 101 of file dwc_otg_hcd_linux.c. ++

++

++ ++

++
++ ++ ++ ++ ++
struct dwc_otg_hcd_function_ops hcd_fops [static]
++
++
++ ++

++Initial value:

 {
++        .start = _start,
++        .disconnect = _disconnect,
++        .hub_info = _hub_info,
++        .speed = _speed,
++        .complete = _complete,
++        .get_b_hnp_enable = _get_b_hnp_enable,
++}
++
++

++Definition at line 312 of file dwc_otg_hcd_linux.c. ++

++

++

Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__hcd__queue_8c-source.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__hcd__queue_8c-source.html 2013-07-26 19:31:21.000000000 +0000 +@@ -0,0 +1,633 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_hcd_queue.c Source File ++ ++ ++ ++ ++
++
++
++
++

dwc_otg_hcd_queue.c

Go to the documentation of this file.
00001 /* ==========================================================================
++00002  * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd_queue.c $
++00003  * $Revision: #39 $
++00004  * $Date: 2009/04/21 $
++00005  * $Change: 1237477 $
++00006  *
++00007  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
++00008  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
++00009  * otherwise expressly agreed to in writing between Synopsys and you.
++00010  * 
++00011  * The Software IS NOT an item of Licensed Software or Licensed Product under
++00012  * any End User Software License Agreement or Agreement for Licensed Product
++00013  * with Synopsys or any supplement thereto. You are permitted to use and
++00014  * redistribute this Software in source and binary forms, with or without
++00015  * modification, provided that redistributions of source code must retain this
++00016  * notice. You may not view, use, disclose, copy or distribute this file or
++00017  * any information contained herein except pursuant to this license grant from
++00018  * Synopsys. If you do not agree with this notice, including the disclaimer
++00019  * below, then you are not authorized to use the Software.
++00020  * 
++00021  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
++00022  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++00023  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++00024  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
++00025  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++00026  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
++00027  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
++00028  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
++00029  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
++00030  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
++00031  * DAMAGE.
++00032  * ========================================================================== */
++00033 #ifndef DWC_DEVICE_ONLY
++00034 
++00042 #include "dwc_otg_hcd.h"
++00043 #include "dwc_otg_regs.h"
++00044 
++00053 void dwc_otg_hcd_qh_free(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
++00054 {
++00055         dwc_otg_qtd_t *qtd, *qtd_tmp;
++00056         uint64_t flags;
++00057 
++00058         /* Free each QTD in the QTD list */
++00059         DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
++00060         DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp, &qh->qtd_list, qtd_list_entry) {
++00061                 DWC_CIRCLEQ_REMOVE(&qh->qtd_list, qtd, qtd_list_entry);
++00062                 dwc_otg_hcd_qtd_free(qtd);
++00063         }
++00064         DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
++00065 
++00066         if (hcd->core_if->dma_desc_enable) {
++00067                 dwc_otg_hcd_qh_free_ddma(hcd, qh);
++00068         }
++00069         else if (qh->dw_align_buf) {
++00070                 uint32_t buf_size;
++00071                 if(qh->ep_type == UE_ISOCHRONOUS) {
++00072                         buf_size = 4096;
++00073                 } else {
++00074                         buf_size = hcd->core_if->core_params->max_transfer_size;
++00075                 }
++00076                 dwc_dma_free(buf_size, qh->dw_align_buf, qh->dw_align_buf_dma);
++00077         }
++00078         
++00079         
++00080         
++00081         dwc_free(qh);
++00082         return;
++00083 }
++00084 
++00085 #define BitStuffTime(bytecount)  ((8 * 7* bytecount) / 6)
++00086 #define HS_HOST_DELAY           5       /* nanoseconds */
++00087 #define FS_LS_HOST_DELAY        1000    /* nanoseconds */
++00088 #define HUB_LS_SETUP            333     /* nanoseconds */
++00089 #define NS_TO_US(ns)            ((ns + 500) / 1000)
++00090                                 /* convert & round nanoseconds to microseconds */
++00091 
++00092 static uint32_t calc_bus_time(int speed, int is_in, int is_isoc,
++00093                                           int bytecount)
++00094 {
++00095         unsigned long retval;
++00096 
++00097         switch (speed) {
++00098         case USB_SPEED_HIGH:
++00099                 if (is_isoc) {
++00100                         retval =
++00101                             ((38 * 8 * 2083) +
++00102                              (2083 * (3 + BitStuffTime(bytecount)))) / 1000 +
++00103                             HS_HOST_DELAY;
++00104                 } else {
++00105                         retval =
++00106                             ((55 * 8 * 2083) +
++00107                              (2083 * (3 + BitStuffTime(bytecount)))) / 1000 +
++00108                             HS_HOST_DELAY;
++00109                 }
++00110                 break;
++00111         case USB_SPEED_FULL:
++00112                 if (is_isoc) {
++00113                         retval =
++00114                             (8354 * (31 + 10 * BitStuffTime(bytecount))) / 1000;
++00115                         if (is_in) {
++00116                                 retval = 7268 + FS_LS_HOST_DELAY + retval;
++00117                         } else {
++00118                                 retval = 6265 + FS_LS_HOST_DELAY + retval;
++00119                         }
++00120                 } else {
++00121                         retval =
++00122                             (8354 * (31 + 10 * BitStuffTime(bytecount))) / 1000;
++00123                         retval = 9107 + FS_LS_HOST_DELAY + retval;
++00124                 }
++00125                 break;
++00126         case USB_SPEED_LOW:
++00127                 if (is_in) {
++00128                         retval =
++00129                             (67667 * (31 + 10 * BitStuffTime(bytecount))) /
++00130                             1000;
++00131                         retval =
++00132                             64060 + (2 * HUB_LS_SETUP) + FS_LS_HOST_DELAY +
++00133                             retval;
++00134                 } else {
++00135                         retval =
++00136                             (66700 * (31 + 10 * BitStuffTime(bytecount))) /
++00137                             1000;
++00138                         retval =
++00139                             64107 + (2 * HUB_LS_SETUP) + FS_LS_HOST_DELAY +
++00140                             retval;
++00141                 }
++00142                 break;
++00143         default:
++00144                 DWC_WARN("Unknown device speed\n");
++00145                 retval = -1;
++00146         }
++00147         
++00148         return NS_TO_US(retval);
++00149 }
++00150 
++00159 #define SCHEDULE_SLOP 10
++00160 void qh_init(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh,
++00161                          dwc_otg_hcd_urb_t * urb)
++00162 {
++00163         char *speed, *type;
++00164         int dev_speed;
++00165         uint32_t hub_addr, hub_port;
++00166 
++00167         dwc_memset(qh, 0, sizeof(dwc_otg_qh_t));
++00168         
++00169         /* Initialize QH */
++00170         qh->ep_type = dwc_otg_hcd_get_pipe_type(&urb->pipe_info);
++00171 
++00172         qh->ep_is_in = dwc_otg_hcd_is_pipe_in(&urb->pipe_info) ? 1 : 0;
++00173 
++00174         qh->data_toggle = DWC_OTG_HC_PID_DATA0;
++00175         qh->maxp = dwc_otg_hcd_get_mps(&urb->pipe_info);
++00176         DWC_CIRCLEQ_INIT(&qh->qtd_list);
++00177         DWC_LIST_INIT(&qh->qh_list_entry);
++00178         qh->channel = NULL;
++00179 
++00180         /* FS/LS Enpoint on HS Hub 
++00181          * NOT virtual root hub */
++00182         dev_speed = hcd->fops->speed(hcd, urb->priv);
++00183         hcd->fops->hub_info(hcd, urb->priv, &hub_addr, &hub_port);
++00184         qh->do_split = 0;
++00185         if (((dev_speed == USB_SPEED_LOW) ||
++00186              (dev_speed == USB_SPEED_FULL)) &&
++00187             (hub_addr != 0 && hub_addr != 1)) {
++00188                 
++00189                 DWC_DEBUGPL(DBG_HCD,
++00190                             "QH init: EP %d: TT found at hub addr %d, for port %d\n",
++00191                             dwc_otg_hcd_get_ep_num(&urb->pipe_info), hub_addr,
++00192                             hub_port);
++00193                 
++00194                 qh->do_split = 1;
++00195         }
++00196 
++00197         if (qh->ep_type == UE_INTERRUPT || qh->ep_type == UE_ISOCHRONOUS) {
++00198                 /* Compute scheduling parameters once and save them. */
++00199                 hprt0_data_t hprt;
++00200 
++00202                 int bytecount =
++00203                     dwc_hb_mult(qh->maxp) * dwc_max_packet(qh->maxp);
++00204 
++00205                 qh->usecs = calc_bus_time((qh->do_split ? USB_SPEED_HIGH : dev_speed),
++00206                                           qh->ep_is_in,
++00207                                           (qh->ep_type == UE_ISOCHRONOUS),
++00208                                           bytecount);
++00209                 /* Start in a slightly future (micro)frame. */
++00210                 qh->sched_frame = dwc_frame_num_inc(hcd->frame_number,
++00211                                                     SCHEDULE_SLOP);
++00212                 qh->interval = urb->interval;
++00213                 
++00214 #if 0
++00215                 /* Increase interrupt polling rate for debugging. */
++00216                 if (qh->ep_type == UE_INTERRUPT) {
++00217                         qh->interval = 8;
++00218                 }
++00219 #endif
++00220                 hprt.d32 = dwc_read_reg32(hcd->core_if->host_if->hprt0);
++00221                 if ((hprt.b.prtspd == DWC_HPRT0_PRTSPD_HIGH_SPEED) &&
++00222                     ((dev_speed == USB_SPEED_LOW) ||
++00223                      (dev_speed == USB_SPEED_FULL))) {
++00224                         qh->interval *= 8;
++00225                         qh->sched_frame |= 0x7;
++00226                         qh->start_split_frame = qh->sched_frame;
++00227                 }
++00228 
++00229         }
++00230 
++00231         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD QH Initialized\n");
++00232         DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH  - qh = %p\n", qh);
++00233         DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH  - Device Address = %d\n",
++00234                     dwc_otg_hcd_get_dev_addr(&urb->pipe_info));
++00235         DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH  - Endpoint %d, %s\n",
++00236                     dwc_otg_hcd_get_ep_num(&urb->pipe_info),
++00237                     dwc_otg_hcd_is_pipe_in(&urb->pipe_info) ? "IN" : "OUT");
++00238         switch (dev_speed) {
++00239         case USB_SPEED_LOW:
++00240                 qh->dev_speed = DWC_OTG_EP_SPEED_LOW;
++00241                 speed = "low";
++00242                 break;
++00243         case USB_SPEED_FULL:
++00244                 qh->dev_speed = DWC_OTG_EP_SPEED_FULL;
++00245                 speed = "full";
++00246                 break;
++00247         case USB_SPEED_HIGH:
++00248                 qh->dev_speed = DWC_OTG_EP_SPEED_HIGH;
++00249                 speed = "high";
++00250                 break;
++00251         default:
++00252                 speed = "?";
++00253                 break;
++00254         }
++00255         DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH  - Speed = %s\n", speed);
++00256 
++00257         switch (qh->ep_type) {
++00258         case UE_ISOCHRONOUS:
++00259                 type = "isochronous";
++00260                 break;
++00261         case UE_INTERRUPT:
++00262                 type = "interrupt";
++00263                 break;
++00264         case UE_CONTROL:
++00265                 type = "control";
++00266                 break;
++00267         case UE_BULK:
++00268                 type = "bulk";
++00269                 break;
++00270         default:
++00271                 type = "?";
++00272                 break;
++00273         }
++00274         
++00275         DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH  - Type = %s\n", type);
++00276 
++00277 #ifdef DEBUG
++00278         if (qh->ep_type == UE_INTERRUPT) {
++00279                 DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - usecs = %d\n",
++00280                             qh->usecs);
++00281                 DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - interval = %d\n",
++00282                             qh->interval);
++00283         }
++00284 #endif
++00285 
++00286 }
++00287 
++00296 dwc_otg_qh_t *dwc_otg_hcd_qh_create(dwc_otg_hcd_t * hcd,
++00297                                     dwc_otg_hcd_urb_t * urb)
++00298 {
++00299         dwc_otg_qh_t *qh;
++00300 
++00301         /* Allocate memory */
++00303         qh = dwc_otg_hcd_qh_alloc();
++00304         if (qh == NULL) {
++00305                 return NULL;
++00306         }
++00307 
++00308         qh_init(hcd, qh, urb);
++00309         
++00310         if (hcd->core_if->dma_desc_enable && (dwc_otg_hcd_qh_init_ddma(hcd, qh) < 0)) {
++00311                 dwc_otg_hcd_qh_free(hcd, qh);   
++00312                 return NULL;
++00313         }
++00314         
++00315         return qh;
++00316 }
++00317 
++00323 static int periodic_channel_available(dwc_otg_hcd_t * hcd)
++00324 {
++00325         /*
++00326          * Currently assuming that there is a dedicated host channnel for each
++00327          * periodic transaction plus at least one host channel for
++00328          * non-periodic transactions.
++00329          */
++00330         int status;
++00331         int num_channels;
++00332 
++00333         num_channels = hcd->core_if->core_params->host_channels;
++00334         if ((hcd->periodic_channels + hcd->non_periodic_channels < num_channels) &&
++00335             (hcd->periodic_channels < num_channels - 1)) {
++00336                 status = 0;
++00337         } else {
++00338                 DWC_INFO("%s: Total channels: %d, Periodic: %d, Non-periodic: %d\n",
++00339                         __func__, num_channels, hcd->periodic_channels, hcd->non_periodic_channels);    //NOTICE
++00340                 status = -DWC_E_NO_SPACE;
++00341         }
++00342 
++00343         return status;
++00344 }
++00345 
++00356 static int check_periodic_bandwidth(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
++00357 {
++00358         int status;
++00359         int16_t max_claimed_usecs;
++00360 
++00361         status = 0;
++00362 
++00363         if ((qh->dev_speed == DWC_OTG_EP_SPEED_HIGH) || qh->do_split) {
++00364                 /*
++00365                  * High speed mode.
++00366                  * Max periodic usecs is 80% x 125 usec = 100 usec.
++00367                  */
++00368 
++00369                 max_claimed_usecs = 100 - qh->usecs;
++00370         } else {
++00371                 /*
++00372                  * Full speed mode.
++00373                  * Max periodic usecs is 90% x 1000 usec = 900 usec.
++00374                  */
++00375                 max_claimed_usecs = 900 - qh->usecs;
++00376         }
++00377 
++00378         if (hcd->periodic_usecs > max_claimed_usecs) {
++00379                 DWC_INFO("%s: already claimed usecs %d, required usecs %d\n", __func__, hcd->periodic_usecs, qh->usecs);        //NOTICE
++00380                 status = -DWC_E_NO_SPACE;
++00381         }
++00382 
++00383         return status;
++00384 }
++00385 
++00396 static int check_max_xfer_size(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
++00397 {
++00398         int status;
++00399         uint32_t max_xfer_size;
++00400         uint32_t max_channel_xfer_size;
++00401 
++00402         status = 0;
++00403 
++00404         max_xfer_size = dwc_max_packet(qh->maxp) * dwc_hb_mult(qh->maxp);
++00405         max_channel_xfer_size = hcd->core_if->core_params->max_transfer_size;
++00406 
++00407         if (max_xfer_size > max_channel_xfer_size) {
++00408                 DWC_INFO("%s: Periodic xfer length %d > " "max xfer length for channel %d\n",
++00409                                 __func__, max_xfer_size, max_channel_xfer_size);        //NOTICE
++00410                 status = -DWC_E_NO_SPACE;
++00411         }
++00412 
++00413         return status;
++00414 }
++00415 
++00425 static int schedule_periodic(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
++00426 {
++00427         int status = 0;
++00428 
++00429         status = periodic_channel_available(hcd);
++00430         if (status) {
++00431                 DWC_INFO("%s: No host channel available for periodic " "transfer.\n", __func__);        //NOTICE
++00432                 return status;
++00433         }
++00434 
++00435         status = check_periodic_bandwidth(hcd, qh);
++00436         if (status) {
++00437                 DWC_INFO("%s: Insufficient periodic bandwidth for " "periodic transfer.\n", __func__);  //NOTICE
++00438                 return status;
++00439         }
++00440 
++00441         status = check_max_xfer_size(hcd, qh);
++00442         if (status) {
++00443                 DWC_INFO("%s: Channel max transfer size too small " "for periodic transfer.\n", __func__);      //NOTICE
++00444                 return status;
++00445         }
++00446 
++00447         if (hcd->core_if->dma_desc_enable) {
++00448                 /* Don't rely on SOF and start in ready schedule */
++00449                 DWC_LIST_INSERT_TAIL(&hcd->periodic_sched_ready, &qh->qh_list_entry);
++00450         }
++00451         else {
++00452         /* Always start in the inactive schedule. */
++00453         DWC_LIST_INSERT_TAIL(&hcd->periodic_sched_inactive, &qh->qh_list_entry);
++00454         }
++00455 
++00456         /* Reserve the periodic channel. */
++00457         hcd->periodic_channels++;
++00458 
++00459         /* Update claimed usecs per (micro)frame. */
++00460         hcd->periodic_usecs += qh->usecs;
++00461 
++00462         return status;
++00463 }
++00464 
++00472 int dwc_otg_hcd_qh_add(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
++00473 {
++00474         int status = 0;
++00475         uint64_t flags;
++00476 
++00477         DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
++00478 
++00479         if (!DWC_LIST_EMPTY(&qh->qh_list_entry)) {
++00480                 /* QH already in a schedule. */
++00481                 goto done;
++00482         }
++00483 
++00484         /* Add the new QH to the appropriate schedule */
++00485         if (dwc_qh_is_non_per(qh)) {
++00486                 /* Always start in the inactive schedule. */
++00487                 DWC_LIST_INSERT_TAIL(&hcd->non_periodic_sched_inactive,
++00488                                      &qh->qh_list_entry);
++00489         } else {
++00490                 status = schedule_periodic(hcd, qh);
++00491         }
++00492 
++00493       done:
++00494         DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
++00495 
++00496         return status;
++00497 }
++00498 
++00505 static void deschedule_periodic(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
++00506 {
++00507         DWC_LIST_REMOVE_INIT(&qh->qh_list_entry);
++00508 
++00509         /* Release the periodic channel reservation. */
++00510         hcd->periodic_channels--;
++00511 
++00512         /* Update claimed usecs per (micro)frame. */
++00513         hcd->periodic_usecs -= qh->usecs;
++00514 }
++00515 
++00522 void dwc_otg_hcd_qh_remove(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
++00523 {
++00524         uint64_t flags;
++00525         DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
++00526 
++00527         if (DWC_LIST_EMPTY(&qh->qh_list_entry)) {
++00528                 /* QH is not in a schedule. */
++00529                 goto done;
++00530         }
++00531 
++00532         if (dwc_qh_is_non_per(qh)) {
++00533                 if (hcd->non_periodic_qh_ptr == &qh->qh_list_entry) {
++00534                         hcd->non_periodic_qh_ptr =
++00535                             hcd->non_periodic_qh_ptr->next;
++00536                 }
++00537                 DWC_LIST_REMOVE_INIT(&qh->qh_list_entry);
++00538         } else {
++00539                 deschedule_periodic(hcd, qh);
++00540         }
++00541 
++00542       done:
++00543         DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
++00544 }
++00545 
++00559 void dwc_otg_hcd_qh_deactivate(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh,
++00560                                int sched_next_periodic_split)
++00561 {
++00562         uint64_t flags;
++00563         DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
++00564 
++00565         if (dwc_qh_is_non_per(qh)) {
++00566                 dwc_otg_hcd_qh_remove(hcd, qh);
++00567                 if (!DWC_CIRCLEQ_EMPTY(&qh->qtd_list)) {
++00568                         /* Add back to inactive non-periodic schedule. */
++00569                         dwc_otg_hcd_qh_add(hcd, qh);
++00570                 }
++00571         } else {
++00572                 uint16_t frame_number = dwc_otg_hcd_get_frame_number(hcd);
++00573 
++00574                 if (qh->do_split) {
++00575                         /* Schedule the next continuing periodic split transfer */
++00576                         if (sched_next_periodic_split) {
++00577 
++00578                                 qh->sched_frame = frame_number;
++00579                                 if (dwc_frame_num_le(frame_number,
++00580                                                      dwc_frame_num_inc(qh->
++00581                                                                        start_split_frame,
++00582                                                                        1))) {
++00583                                         /*
++00584                                          * Allow one frame to elapse after start
++00585                                          * split microframe before scheduling
++00586                                          * complete split, but DONT if we are
++00587                                          * doing the next start split in the
++00588                                          * same frame for an ISOC out.
++00589                                          */
++00590                                         if ((qh->ep_type != UE_ISOCHRONOUS) ||
++00591                                             (qh->ep_is_in != 0)) {
++00592                                                 qh->sched_frame =
++00593                                                     dwc_frame_num_inc(qh->sched_frame, 1);
++00594                                         }
++00595                                 }
++00596                         } else {
++00597                                 qh->sched_frame =
++00598                                     dwc_frame_num_inc(qh->start_split_frame,
++00599                                                       qh->interval);
++00600                                 if (dwc_frame_num_le
++00601                                     (qh->sched_frame, frame_number)) {
++00602                                         qh->sched_frame = frame_number;
++00603                                 }
++00604                                 qh->sched_frame |= 0x7;
++00605                                 qh->start_split_frame = qh->sched_frame;
++00606                         }
++00607                 } else {
++00608                         qh->sched_frame =
++00609                             dwc_frame_num_inc(qh->sched_frame, qh->interval);
++00610                         if (dwc_frame_num_le(qh->sched_frame, frame_number)) {
++00611                                 qh->sched_frame = frame_number;
++00612                         }
++00613                 }
++00614 
++00615                 if (DWC_CIRCLEQ_EMPTY(&qh->qtd_list)) {
++00616                         dwc_otg_hcd_qh_remove(hcd, qh);
++00617                 } else {
++00618                         /*
++00619                          * Remove from periodic_sched_queued and move to
++00620                          * appropriate queue.
++00621                          */
++00622                         if (qh->sched_frame == frame_number) {
++00623                                 DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_ready,
++00624                                                    &qh->qh_list_entry);
++00625                         } else {
++00626                                 DWC_LIST_MOVE_HEAD(&hcd->
++00627                                                    periodic_sched_inactive,
++00628                                                    &qh->qh_list_entry);
++00629                         }
++00630                 }
++00631         }
++00632 
++00633         DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
++00634 }
++00635 
++00643 dwc_otg_qtd_t *dwc_otg_hcd_qtd_create(dwc_otg_hcd_urb_t * urb)
++00644 {
++00645         dwc_otg_qtd_t *qtd;
++00646 
++00647         qtd = dwc_otg_hcd_qtd_alloc();
++00648         if (qtd == NULL) {
++00649                 return NULL;
++00650         }
++00651 
++00652         dwc_otg_hcd_qtd_init(qtd, urb);
++00653         return qtd;
++00654 }
++00655 
++00661 void dwc_otg_hcd_qtd_init(dwc_otg_qtd_t * qtd, dwc_otg_hcd_urb_t * urb)
++00662 {
++00663         dwc_memset(qtd, 0, sizeof(dwc_otg_qtd_t));
++00664         qtd->urb = urb;
++00665         if (dwc_otg_hcd_get_pipe_type(&urb->pipe_info) == UE_CONTROL) {
++00666                 /*
++00667                  * The only time the QTD data toggle is used is on the data
++00668                  * phase of control transfers. This phase always starts with
++00669                  * DATA1.
++00670                  */
++00671                 qtd->data_toggle = DWC_OTG_HC_PID_DATA1;
++00672                 qtd->control_phase = DWC_OTG_CONTROL_SETUP;
++00673         }
++00674 
++00675         /* start split */
++00676         qtd->complete_split = 0;
++00677         qtd->isoc_split_pos = DWC_HCSPLIT_XACTPOS_ALL;
++00678         qtd->isoc_split_offset = 0;
++00679         qtd->in_process = 0;
++00680 
++00681         /* Store the qtd ptr in the urb to reference what QTD. */
++00682         urb->qtd = qtd;
++00683         return;
++00684 }
++00685 
++00698 int dwc_otg_hcd_qtd_add(dwc_otg_qtd_t * qtd,
++00699                         dwc_otg_hcd_t * hcd, dwc_otg_qh_t ** qh)
++00700 {
++00701         int retval = 0;
++00702         uint64_t flags;
++00703 
++00704         dwc_otg_hcd_urb_t *urb = qtd->urb;
++00705 
++00706         DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
++00707 
++00708         /*
++00709          * Get the QH which holds the QTD-list to insert to. Create QH if it
++00710          * doesn't exist.
++00711          */
++00712         if (*qh == NULL) {
++00713                 *qh = dwc_otg_hcd_qh_create(hcd, urb);
++00714                 if (*qh == NULL) {
++00715                         retval = -1;
++00716                         goto done;
++00717                 }
++00718         }
++00719 
++00720         retval = dwc_otg_hcd_qh_add(hcd, *qh);
++00721         if (retval == 0) {
++00722                 DWC_CIRCLEQ_INSERT_TAIL(&((*qh)->qtd_list), qtd,
++00723                                         qtd_list_entry);
++00724         }
++00725 
++00726       done:
++00727         DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
++00728 
++00729         return retval;
++00730 }
++00731 
++00732 #endif                          /* DWC_DEVICE_ONLY */
++
Generated on Tue May 5 02:22:48 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__hcd__queue_8c.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__hcd__queue_8c.html 2013-07-26 19:31:21.000000000 +0000 +@@ -0,0 +1,667 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_hcd_queue.c File Reference ++ ++ ++ ++ ++
++
++
++
++

dwc_otg_hcd_queue.c File Reference

This file contains the functions to manage Queue Heads and Queue Transfer Descriptors. More... ++

++#include "dwc_otg_hcd.h"
++#include "dwc_otg_regs.h"
++ ++

++Go to the source code of this file. ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++

Defines

++#define BitStuffTime(bytecount)   ((8 * 7* bytecount) / 6)
++#define HS_HOST_DELAY   5
++#define FS_LS_HOST_DELAY   1000
++#define HUB_LS_SETUP   333
++#define NS_TO_US(ns)   ((ns + 500) / 1000)
#define SCHEDULE_SLOP   10
 Initializes a QH structure.

Functions

void dwc_otg_hcd_qh_free (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
 Free each QTD in the QH's QTD-list then free the QH.
++static uint32_t calc_bus_time (int speed, int is_in, int is_isoc, int bytecount)
void qh_init (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh, dwc_otg_hcd_urb_t *urb)
dwc_otg_qh_t * dwc_otg_hcd_qh_create (dwc_otg_hcd_t *hcd, dwc_otg_hcd_urb_t *urb)
 This function allocates and initializes a QH.
static int periodic_channel_available (dwc_otg_hcd_t *hcd)
 Checks that a channel is available for a periodic transfer.
static int check_periodic_bandwidth (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
 Checks that there is sufficient bandwidth for the specified QH in the periodic schedule.
static int check_max_xfer_size (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
 Checks that the max transfer size allowed in a host channel is large enough to handle the maximum data transfer in a single (micro)frame for a periodic transfer.
static int schedule_periodic (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
 Schedules an interrupt or isochronous transfer in the periodic schedule.
int dwc_otg_hcd_qh_add (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
 This function adds a QH to either the non periodic or periodic schedule if it is not already in the schedule.
static void deschedule_periodic (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
 Removes an interrupt or isochronous transfer from the periodic schedule.
void dwc_otg_hcd_qh_remove (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
 Removes a QH from either the non-periodic or periodic schedule.
void dwc_otg_hcd_qh_deactivate (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh, int sched_next_periodic_split)
 Deactivates a QH.
dwc_otg_qtd_t * dwc_otg_hcd_qtd_create (dwc_otg_hcd_urb_t *urb)
 This function allocates and initializes a QTD.
void dwc_otg_hcd_qtd_init (dwc_otg_qtd_t *qtd, dwc_otg_hcd_urb_t *urb)
 Initializes a QTD structure.
int dwc_otg_hcd_qtd_add (dwc_otg_qtd_t *qtd, dwc_otg_hcd_t *hcd, dwc_otg_qh_t **qh)
 This function adds a QTD to the QTD-list of a QH.
++

Detailed Description

++This file contains the functions to manage Queue Heads and Queue Transfer Descriptors. ++

++ ++

++Definition in file dwc_otg_hcd_queue.c.

Define Documentation

++ ++
++
++ ++ ++ ++ ++
#define SCHEDULE_SLOP   10
++
++
++ ++

++Initializes a QH structure. ++

++

Parameters:
++ ++ ++ ++ ++
hcd The HCD state structure for the DWC OTG controller.
qh The QH to init.
urb Holds the information about the device/endpoint that we need to initialize the QH.
++
++ ++

++Definition at line 159 of file dwc_otg_hcd_queue.c. ++

++

++

Function Documentation

++ ++
++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_otg_hcd_qh_free (dwc_otg_hcd_t *  hcd,
dwc_otg_qh_t *  qh 
)
++
++
++ ++

++Free each QTD in the QH's QTD-list then free the QH. ++

++QH should already be removed from a list. QTD list should already be empty if called from URB Dequeue.

++

Parameters:
++ ++ ++ ++
hcd HCD instance.
qh The QH to free.
++
++ ++

++Definition at line 53 of file dwc_otg_hcd_queue.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void qh_init (dwc_otg_hcd_t *  hcd,
dwc_otg_qh_t *  qh,
dwc_otg_hcd_urb_t *  urb 
)
++
++
++ ++

++ ++

++Definition at line 160 of file dwc_otg_hcd_queue.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
dwc_otg_qh_t* dwc_otg_hcd_qh_create (dwc_otg_hcd_t *  hcd,
dwc_otg_hcd_urb_t *  urb 
)
++
++
++ ++

++This function allocates and initializes a QH. ++

++

Parameters:
++ ++ ++ ++
hcd The HCD state structure for the DWC OTG controller.
urb Holds the information about the device/endpoint that we need to initialize the QH.
++
++
Returns:
Returns pointer to the newly allocated QH, or NULL on error.
++ ++

++

Todo:
add memflags argument
++ ++

++Definition at line 296 of file dwc_otg_hcd_queue.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
static int periodic_channel_available (dwc_otg_hcd_t *  hcd  )  [static]
++
++
++ ++

++Checks that a channel is available for a periodic transfer. ++

++

Returns:
0 if successful, negative error code otherise.
++ ++

++Definition at line 323 of file dwc_otg_hcd_queue.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
static int check_periodic_bandwidth (dwc_otg_hcd_t *  hcd,
dwc_otg_qh_t *  qh 
) [static]
++
++
++ ++

++Checks that there is sufficient bandwidth for the specified QH in the periodic schedule. ++

++For simplicity, this calculation assumes that all the transfers in the periodic schedule may occur in the same (micro)frame.

++

Parameters:
++ ++ ++ ++
hcd The HCD state structure for the DWC OTG controller.
qh QH containing periodic bandwidth required.
++
++
Returns:
0 if successful, negative error code otherwise.
++ ++

++Definition at line 356 of file dwc_otg_hcd_queue.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
static int check_max_xfer_size (dwc_otg_hcd_t *  hcd,
dwc_otg_qh_t *  qh 
) [static]
++
++
++ ++

++Checks that the max transfer size allowed in a host channel is large enough to handle the maximum data transfer in a single (micro)frame for a periodic transfer. ++

++

Parameters:
++ ++ ++ ++
hcd The HCD state structure for the DWC OTG controller.
qh QH for a periodic endpoint.
++
++
Returns:
0 if successful, negative error code otherwise.
++ ++

++Definition at line 396 of file dwc_otg_hcd_queue.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
static int schedule_periodic (dwc_otg_hcd_t *  hcd,
dwc_otg_qh_t *  qh 
) [static]
++
++
++ ++

++Schedules an interrupt or isochronous transfer in the periodic schedule. ++

++

Parameters:
++ ++ ++ ++
hcd The HCD state structure for the DWC OTG controller.
qh QH for the periodic transfer. The QH should already contain the scheduling information.
++
++
Returns:
0 if successful, negative error code otherwise.
++ ++

++Definition at line 425 of file dwc_otg_hcd_queue.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int dwc_otg_hcd_qh_add (dwc_otg_hcd_t *  hcd,
dwc_otg_qh_t *  qh 
)
++
++
++ ++

++This function adds a QH to either the non periodic or periodic schedule if it is not already in the schedule. ++

++If the QH is already in the schedule, no action is taken.

++

Returns:
0 if successful, negative error code otherwise.
++ ++

++Definition at line 472 of file dwc_otg_hcd_queue.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
static void deschedule_periodic (dwc_otg_hcd_t *  hcd,
dwc_otg_qh_t *  qh 
) [static]
++
++
++ ++

++Removes an interrupt or isochronous transfer from the periodic schedule. ++

++

Parameters:
++ ++ ++ ++
hcd The HCD state structure for the DWC OTG controller.
qh QH for the periodic transfer.
++
++ ++

++Definition at line 505 of file dwc_otg_hcd_queue.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_otg_hcd_qh_remove (dwc_otg_hcd_t *  hcd,
dwc_otg_qh_t *  qh 
)
++
++
++ ++

++Removes a QH from either the non-periodic or periodic schedule. ++

++Memory is not freed.

++

Parameters:
++ ++ ++ ++
hcd The HCD state structure.
qh QH to remove from schedule.
++
++ ++

++Definition at line 522 of file dwc_otg_hcd_queue.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_otg_hcd_qh_deactivate (dwc_otg_hcd_t *  hcd,
dwc_otg_qh_t *  qh,
int  sched_next_periodic_split 
)
++
++
++ ++

++Deactivates a QH. ++

++For non-periodic QHs, removes the QH from the active non-periodic schedule. The QH is added to the inactive non-periodic schedule if any QTDs are still attached to the QH.

++For periodic QHs, the QH is removed from the periodic queued schedule. If there are any QTDs still attached to the QH, the QH is added to either the periodic inactive schedule or the periodic ready schedule and its next scheduled frame is calculated. The QH is placed in the ready schedule if the scheduled frame has been reached already. Otherwise it's placed in the inactive schedule. If there are no QTDs attached to the QH, the QH is completely removed from the periodic schedule. ++

++Definition at line 559 of file dwc_otg_hcd_queue.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
dwc_otg_qtd_t* dwc_otg_hcd_qtd_create (dwc_otg_hcd_urb_t *  urb  ) 
++
++
++ ++

++This function allocates and initializes a QTD. ++

++

Parameters:
++ ++ ++
urb The URB to create a QTD from. Each URB-QTD pair will end up pointing to each other so each pair should have a unique correlation.
++
++
Returns:
Returns pointer to the newly allocated QTD, or NULL on error.
++ ++

++Definition at line 643 of file dwc_otg_hcd_queue.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_otg_hcd_qtd_init (dwc_otg_qtd_t *  qtd,
dwc_otg_hcd_urb_t *  urb 
)
++
++
++ ++

++Initializes a QTD structure. ++

++

Parameters:
++ ++ ++ ++
qtd The QTD to initialize.
urb The URB to use for initialization.
++
++ ++

++Definition at line 661 of file dwc_otg_hcd_queue.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int dwc_otg_hcd_qtd_add (dwc_otg_qtd_t *  qtd,
dwc_otg_hcd_t *  hcd,
dwc_otg_qh_t **  qh 
)
++
++
++ ++

++This function adds a QTD to the QTD-list of a QH. ++

++It will find the correct QH to place the QTD into. If it does not find a QH, then it will create a new QH. If the QH to which the QTD is added is not currently scheduled, it is placed into the proper schedule based on its EP type.

++

Parameters:
++ ++ ++ ++ ++
[in] qtd The QTD to add
[in] hcd The DWC HCD structure
[out] qh out parameter to return queue head
++
++
Returns:
0 if successful, negative error code otherwise.
++ ++

++Definition at line 698 of file dwc_otg_hcd_queue.c. ++

++

++

Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__pcd_8c-source.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__pcd_8c-source.html 2013-07-26 19:31:21.000000000 +0000 +@@ -0,0 +1,1851 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_pcd.c Source File ++ ++ ++ ++ ++
++
++
++
++

dwc_otg_pcd.c

Go to the documentation of this file.
00001 /* ==========================================================================
++00002  * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_pcd.c $
++00003  * $Revision: #79 $
++00004  * $Date: 2009/04/10 $
++00005  * $Change: 1230501 $
++00006  *
++00007  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
++00008  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
++00009  * otherwise expressly agreed to in writing between Synopsys and you.
++00010  *
++00011  * The Software IS NOT an item of Licensed Software or Licensed Product under
++00012  * any End User Software License Agreement or Agreement for Licensed Product
++00013  * with Synopsys or any supplement thereto. You are permitted to use and
++00014  * redistribute this Software in source and binary forms, with or without
++00015  * modification, provided that redistributions of source code must retain this
++00016  * notice. You may not view, use, disclose, copy or distribute this file or
++00017  * any information contained herein except pursuant to this license grant from
++00018  * Synopsys. If you do not agree with this notice, including the disclaimer
++00019  * below, then you are not authorized to use the Software.
++00020  *
++00021  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
++00022  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++00023  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++00024  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
++00025  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++00026  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
++00027  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
++00028  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
++00029  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
++00030  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
++00031  * DAMAGE.
++00032  * ========================================================================== */
++00033 #ifndef DWC_HOST_ONLY
++00034 
++00051 #include "dwc_otg_pcd.h"
++00052 
++00053 #ifdef DWC_UTE_CFI
++00054 #include "dwc_otg_cfi.h"
++00055 
++00056 extern int init_cfi(cfiobject_t * cfiobj);
++00057 #endif
++00058 
++00059 static dwc_otg_pcd_ep_t *get_ep_from_handle(dwc_otg_pcd_t * pcd, void *handle)
++00060 {
++00061         int i;
++00062         if (pcd->ep0.priv == handle) {
++00063                 return &pcd->ep0;
++00064         }
++00065         for (i = 0; i < MAX_EPS_CHANNELS - 1; i++) {
++00066                 if (pcd->in_ep[i].priv == handle)
++00067                         return &pcd->in_ep[i];
++00068                 if (pcd->out_ep[i].priv == handle)
++00069                         return &pcd->out_ep[i];
++00070         }
++00071 
++00072         return NULL;
++00073 }
++00074 
++00078 void dwc_otg_request_done(dwc_otg_pcd_ep_t * ep, dwc_otg_pcd_request_t * req,
++00079                           int32_t status)
++00080 {
++00081         unsigned stopped = ep->stopped;
++00082 
++00083         DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, ep);
++00084         DWC_CIRCLEQ_REMOVE_INIT(&ep->queue, req, queue_entry);
++00085 
++00086         /* don't modify queue heads during completion callback */
++00087         ep->stopped = 1;
++00088         DWC_SPINUNLOCK(ep->pcd->lock);
++00089         ep->pcd->fops->complete(ep->pcd, ep->priv, req->priv, status,
++00090                                 req->actual);
++00091         DWC_SPINLOCK(ep->pcd->lock);
++00092 
++00093         if (ep->pcd->request_pending > 0) {
++00094                 --ep->pcd->request_pending;
++00095         }
++00096 
++00097         ep->stopped = stopped;
++00098         dwc_free(req);
++00099 }
++00100 
++00104 void dwc_otg_request_nuke(dwc_otg_pcd_ep_t * ep)
++00105 {
++00106         dwc_otg_pcd_request_t *req;
++00107 
++00108         ep->stopped = 1;
++00109 
++00110         /* called with irqs blocked?? */
++00111         while (!DWC_CIRCLEQ_EMPTY(&ep->queue)) {
++00112                 req = DWC_CIRCLEQ_FIRST(&ep->queue);
++00113                 dwc_otg_request_done(ep, req, -DWC_E_SHUTDOWN);
++00114         }
++00115 }
++00116 
++00117 void dwc_otg_pcd_start(dwc_otg_pcd_t * pcd,
++00118                        const struct dwc_otg_pcd_function_ops *fops)
++00119 {
++00120         pcd->fops = fops;
++00121 }
++00122 
++00129 static int32_t dwc_otg_pcd_start_cb(void *p)
++00130 {
++00131         dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *) p;
++00132 
++00133         /*
++00134          * Initialized the Core for Device mode.
++00135          */
++00136         if (dwc_otg_is_device_mode(GET_CORE_IF(pcd))) {
++00137                 dwc_otg_core_dev_init(GET_CORE_IF(pcd));
++00138         }
++00139         return 1;
++00140 }
++00141 
++00143 #ifdef DWC_UTE_CFI
++00144 uint8_t *cfiw_ep_alloc_buffer(dwc_otg_pcd_t * pcd, void *pep, dwc_dma_t * addr,
++00145                               size_t buflen, int flags)
++00146 {
++00147         dwc_otg_pcd_ep_t *ep;
++00148         ep = get_ep_from_handle(pcd, pep);
++00149         return pcd->cfi->ops.ep_alloc_buf(pcd->cfi, pcd, ep, addr, buflen,
++00150                                           flags);
++00151 }
++00152 #else
++00153 uint8_t *cfiw_ep_alloc_buffer(dwc_otg_pcd_t * pcd, void *pep, dwc_dma_t * addr,
++00154                               size_t buflen, int flags);
++00155 #endif
++00156 
++00163 static int32_t dwc_otg_pcd_resume_cb(void *p)
++00164 {
++00165         dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *) p;
++00166 
++00167         if (pcd->fops->resume) {
++00168                 pcd->fops->resume(pcd);
++00169         }
++00170 
++00171         /* Stop the SRP timeout timer. */
++00172         if ((GET_CORE_IF(pcd)->core_params->phy_type != DWC_PHY_TYPE_PARAM_FS)
++00173             || (!GET_CORE_IF(pcd)->core_params->i2c_enable)) {
++00174                 if (GET_CORE_IF(pcd)->srp_timer_started) {
++00175                         GET_CORE_IF(pcd)->srp_timer_started = 0;
++00176                         DWC_TIMER_CANCEL(pcd->srp_timer);
++00177                 }
++00178         }
++00179         return 1;
++00180 }
++00181 
++00187 static int32_t dwc_otg_pcd_suspend_cb(void *p)
++00188 {
++00189         dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *) p;
++00190 
++00191         if (pcd->fops->suspend) {
++00192                 pcd->fops->suspend(pcd);
++00193         }
++00194 
++00195         return 1;
++00196 }
++00197 
++00204 static int32_t dwc_otg_pcd_stop_cb(void *p)
++00205 {
++00206         dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *) p;
++00207         extern void dwc_otg_pcd_stop(dwc_otg_pcd_t * _pcd);
++00208 
++00209         dwc_otg_pcd_stop(pcd);
++00210         return 1;
++00211 }
++00212 
++00216 static dwc_otg_cil_callbacks_t pcd_callbacks = {
++00217         .start = dwc_otg_pcd_start_cb,
++00218         .stop = dwc_otg_pcd_stop_cb,
++00219         .suspend = dwc_otg_pcd_suspend_cb,
++00220         .resume_wakeup = dwc_otg_pcd_resume_cb,
++00221         .p = 0,                 /* Set at registration */
++00222 };
++00223 
++00228 dwc_otg_dev_dma_desc_t *dwc_otg_ep_alloc_desc_chain(uint32_t * dma_desc_addr,
++00229                                                 uint32_t count)
++00230 {
++00231 
++00232         return dwc_dma_alloc(count * sizeof(dwc_otg_dev_dma_desc_t), dma_desc_addr);
++00233 }
++00234 
++00238 void dwc_otg_ep_free_desc_chain(dwc_otg_dev_dma_desc_t * desc_addr,
++00239                                 uint32_t dma_desc_addr, uint32_t count)
++00240 {
++00241         dwc_dma_free(count * sizeof(dwc_otg_dev_dma_desc_t), desc_addr,
++00242                      dma_desc_addr);
++00243 }
++00244 
++00245 #ifdef DWC_EN_ISOC
++00246 
++00254 void dwc_otg_iso_ep_start_ddma_transfer(dwc_otg_core_if_t * core_if,
++00255                                         dwc_ep_t * dwc_ep)
++00256 {
++00257 
++00258         dsts_data_t dsts = {.d32 = 0 };
++00259         depctl_data_t depctl = {.d32 = 0 };
++00260         volatile uint32_t *addr;
++00261         int i, j;
++00262 
++00263         if (dwc_ep->is_in)
++00264                 dwc_ep->desc_cnt = dwc_ep->buf_proc_intrvl / dwc_ep->bInterval;
++00265         else
++00266                 dwc_ep->desc_cnt =
++00267                     dwc_ep->buf_proc_intrvl * dwc_ep->pkt_per_frm /
++00268                     dwc_ep->bInterval;
++00269 
++00271         dwc_ep->iso_desc_addr =
++00272             dwc_otg_ep_alloc_desc_chain(&dwc_ep->iso_dma_desc_addr,
++00273                                         dwc_ep->desc_cnt * 2);
++00274         if (dwc_ep->desc_addr) {
++00275                 DWC_WARN("%s, can't allocate DMA descriptor chain\n", __func__);
++00276                 return;
++00277         }
++00278 
++00279         dsts.d32 = dwc_read_reg32(&core_if->dev_if->dev_global_regs->dsts);
++00280 
++00282         if (dwc_ep->is_in == 0) {
++00283                 dev_dma_desc_sts_t sts = {.d32 = 0 };
++00284                 dwc_otg_dev_dma_desc_t *dma_desc = dwc_ep->iso_desc_addr;
++00285                 dma_addr_t dma_ad;
++00286                 uint32_t data_per_desc;
++00287                 dwc_otg_dev_out_ep_regs_t *out_regs =
++00288                     core_if->dev_if->out_ep_regs[dwc_ep->num];
++00289                 int offset;
++00290 
++00291                 addr = &core_if->dev_if->out_ep_regs[dwc_ep->num]->doepctl;
++00292                 dma_ad = (dma_addr_t) dwc_read_reg32(&(out_regs->doepdma));
++00293 
++00295                 dma_ad = dwc_ep->dma_addr0;
++00296 
++00297                 sts.b_iso_out.bs = BS_HOST_READY;
++00298                 sts.b_iso_out.rxsts = 0;
++00299                 sts.b_iso_out.l = 0;
++00300                 sts.b_iso_out.sp = 0;
++00301                 sts.b_iso_out.ioc = 0;
++00302                 sts.b_iso_out.pid = 0;
++00303                 sts.b_iso_out.framenum = 0;
++00304 
++00305                 offset = 0;
++00306                 for (i = 0; i < dwc_ep->desc_cnt - dwc_ep->pkt_per_frm;
++00307                      i += dwc_ep->pkt_per_frm) {
++00308 
++00309                         for (j = 0; j < dwc_ep->pkt_per_frm; ++j) {
++00310                                 data_per_desc =
++00311                                     ((j + 1) * dwc_ep->maxpacket >
++00312                                      dwc_ep->data_per_frame) ? dwc_ep->
++00313                                     data_per_frame -
++00314                                     j * dwc_ep->maxpacket : dwc_ep->maxpacket;
++00315 
++00316                                 data_per_desc +=
++00317                                     (data_per_desc % 4) ? (4 -
++00318                                                            data_per_desc %
++00319                                                            4) : 0;
++00320                                 sts.b_iso_out.rxbytes = data_per_desc;
++00321                                 dma_desc->buf = dma_ad;
++00322                                 dma_desc->status.d32 = sts.d32;
++00323 
++00324                                 offset += data_per_desc;
++00325                                 dma_desc++;
++00326                                 dma_ad += data_per_desc;
++00327                         }
++00328                 }
++00329 
++00330                 for (j = 0; j < dwc_ep->pkt_per_frm - 1; ++j) {
++00331                         data_per_desc =
++00332                             ((j + 1) * dwc_ep->maxpacket >
++00333                              dwc_ep->data_per_frame) ? dwc_ep->data_per_frame -
++00334                             j * dwc_ep->maxpacket : dwc_ep->maxpacket;
++00335                         data_per_desc +=
++00336                             (data_per_desc % 4) ? (4 - data_per_desc % 4) : 0;
++00337                         sts.b_iso_out.rxbytes = data_per_desc;
++00338                         dma_desc->buf = dma_ad;
++00339                         dma_desc->status.d32 = sts.d32;
++00340 
++00341                         offset += data_per_desc;
++00342                         dma_desc++;
++00343                         dma_ad += data_per_desc;
++00344                 }
++00345 
++00346                 sts.b_iso_out.ioc = 1;
++00347                 data_per_desc =
++00348                     ((j + 1) * dwc_ep->maxpacket >
++00349                      dwc_ep->data_per_frame) ? dwc_ep->data_per_frame -
++00350                     j * dwc_ep->maxpacket : dwc_ep->maxpacket;
++00351                 data_per_desc +=
++00352                     (data_per_desc % 4) ? (4 - data_per_desc % 4) : 0;
++00353                 sts.b_iso_out.rxbytes = data_per_desc;
++00354 
++00355                 dma_desc->buf = dma_ad;
++00356                 dma_desc->status.d32 = sts.d32;
++00357                 dma_desc++;
++00358 
++00360                 sts.b_iso_out.ioc = 0;
++00361                 dma_ad = dwc_ep->dma_addr1;
++00362 
++00363                 offset = 0;
++00364                 for (i = 0; i < dwc_ep->desc_cnt - dwc_ep->pkt_per_frm;
++00365                      i += dwc_ep->pkt_per_frm) {
++00366                         for (j = 0; j < dwc_ep->pkt_per_frm; ++j) {
++00367                                 data_per_desc =
++00368                                     ((j + 1) * dwc_ep->maxpacket >
++00369                                      dwc_ep->data_per_frame) ? dwc_ep->
++00370                                     data_per_frame -
++00371                                     j * dwc_ep->maxpacket : dwc_ep->maxpacket;
++00372                                 data_per_desc +=
++00373                                     (data_per_desc % 4) ? (4 -
++00374                                                            data_per_desc %
++00375                                                            4) : 0;
++00376                                 sts.b_iso_out.rxbytes = data_per_desc;
++00377                                 dma_desc->buf = dma_ad;
++00378                                 dma_desc->status.d32 = sts.d32;
++00379 
++00380                                 offset += data_per_desc;
++00381                                 dma_desc++;
++00382                                 dma_ad += data_per_desc;
++00383                         }
++00384                 }
++00385                 for (j = 0; j < dwc_ep->pkt_per_frm - 1; ++j) {
++00386                         data_per_desc =
++00387                             ((j + 1) * dwc_ep->maxpacket >
++00388                              dwc_ep->data_per_frame) ? dwc_ep->data_per_frame -
++00389                             j * dwc_ep->maxpacket : dwc_ep->maxpacket;
++00390                         data_per_desc +=
++00391                             (data_per_desc % 4) ? (4 - data_per_desc % 4) : 0;
++00392                         sts.b_iso_out.rxbytes = data_per_desc;
++00393                         dma_desc->buf = dma_ad;
++00394                         dma_desc->status.d32 = sts.d32;
++00395 
++00396                         offset += data_per_desc;
++00397                         dma_desc++;
++00398                         dma_ad += data_per_desc;
++00399                 }
++00400 
++00401                 sts.b_iso_out.ioc = 1;
++00402                 sts.b_iso_out.l = 1;
++00403                 data_per_desc =
++00404                     ((j + 1) * dwc_ep->maxpacket >
++00405                      dwc_ep->data_per_frame) ? dwc_ep->data_per_frame -
++00406                     j * dwc_ep->maxpacket : dwc_ep->maxpacket;
++00407                 data_per_desc +=
++00408                     (data_per_desc % 4) ? (4 - data_per_desc % 4) : 0;
++00409                 sts.b_iso_out.rxbytes = data_per_desc;
++00410 
++00411                 dma_desc->buf = dma_ad;
++00412                 dma_desc->status.d32 = sts.d32;
++00413 
++00414                 dwc_ep->next_frame = 0;
++00415 
++00417                 dwc_write_reg32(&(out_regs->doepdma),
++00418                                 (uint32_t) dwc_ep->iso_dma_desc_addr);
++00419 
++00420         }
++00422         else {
++00423                 dev_dma_desc_sts_t sts = {.d32 = 0 };
++00424                 dwc_otg_dev_dma_desc_t *dma_desc = dwc_ep->iso_desc_addr;
++00425                 dma_addr_t dma_ad;
++00426                 dwc_otg_dev_in_ep_regs_t *in_regs =
++00427                     core_if->dev_if->in_ep_regs[dwc_ep->num];
++00428                 unsigned int frmnumber;
++00429                 fifosize_data_t txfifosize, rxfifosize;
++00430 
++00431                 txfifosize.d32 =
++00432                     dwc_read_reg32(&core_if->dev_if->in_ep_regs[dwc_ep->num]->
++00433                                    dtxfsts);
++00434                 rxfifosize.d32 =
++00435                     dwc_read_reg32(&core_if->core_global_regs->grxfsiz);
++00436 
++00437                 addr = &core_if->dev_if->in_ep_regs[dwc_ep->num]->diepctl;
++00438 
++00439                 dma_ad = dwc_ep->dma_addr0;
++00440 
++00441                 dsts.d32 =
++00442                     dwc_read_reg32(&core_if->dev_if->dev_global_regs->dsts);
++00443 
++00444                 sts.b_iso_in.bs = BS_HOST_READY;
++00445                 sts.b_iso_in.txsts = 0;
++00446                 sts.b_iso_in.sp =
++00447                     (dwc_ep->data_per_frame % dwc_ep->maxpacket) ? 1 : 0;
++00448                 sts.b_iso_in.ioc = 0;
++00449                 sts.b_iso_in.pid = dwc_ep->pkt_per_frm;
++00450 
++00451                 frmnumber = dwc_ep->next_frame;
++00452 
++00453                 sts.b_iso_in.framenum = frmnumber;
++00454                 sts.b_iso_in.txbytes = dwc_ep->data_per_frame;
++00455                 sts.b_iso_in.l = 0;
++00456 
++00458                 for (i = 0; i < dwc_ep->desc_cnt - 1; i++) {
++00459                         dma_desc->buf = dma_ad;
++00460                         dma_desc->status.d32 = sts.d32;
++00461                         dma_desc++;
++00462 
++00463                         dma_ad += dwc_ep->data_per_frame;
++00464                         sts.b_iso_in.framenum += dwc_ep->bInterval;
++00465                 }
++00466 
++00467                 sts.b_iso_in.ioc = 1;
++00468                 dma_desc->buf = dma_ad;
++00469                 dma_desc->status.d32 = sts.d32;
++00470                 ++dma_desc;
++00471 
++00473                 sts.b_iso_in.ioc = 0;
++00474                 dma_ad = dwc_ep->dma_addr1;
++00475 
++00476                 for (i = 0; i < dwc_ep->desc_cnt - dwc_ep->pkt_per_frm;
++00477                      i += dwc_ep->pkt_per_frm) {
++00478                         dma_desc->buf = dma_ad;
++00479                         dma_desc->status.d32 = sts.d32;
++00480                         dma_desc++;
++00481 
++00482                         dma_ad += dwc_ep->data_per_frame;
++00483                         sts.b_iso_in.framenum += dwc_ep->bInterval;
++00484 
++00485                         sts.b_iso_in.ioc = 0;
++00486                 }
++00487                 sts.b_iso_in.ioc = 1;
++00488                 sts.b_iso_in.l = 1;
++00489 
++00490                 dma_desc->buf = dma_ad;
++00491                 dma_desc->status.d32 = sts.d32;
++00492 
++00493                 dwc_ep->next_frame = sts.b_iso_in.framenum + dwc_ep->bInterval;
++00494 
++00496                 dwc_write_reg32(&(in_regs->diepdma),
++00497                                 (uint32_t) dwc_ep->iso_dma_desc_addr);
++00498         }
++00500         depctl.d32 = 0;
++00501         depctl.b.epena = 1;
++00502         depctl.b.usbactep = 1;
++00503         depctl.b.cnak = 1;
++00504 
++00505         dwc_modify_reg32(addr, depctl.d32, depctl.d32);
++00506         depctl.d32 = dwc_read_reg32(addr);
++00507 }
++00508 
++00517 void dwc_otg_iso_ep_start_buf_transfer(dwc_otg_core_if_t * core_if,
++00518                                        dwc_ep_t * ep)
++00519 {
++00520         depctl_data_t depctl = {.d32 = 0 };
++00521         volatile uint32_t *addr;
++00522 
++00523         if (ep->is_in) {
++00524                 addr = &core_if->dev_if->in_ep_regs[ep->num]->diepctl;
++00525         } else {
++00526                 addr = &core_if->dev_if->out_ep_regs[ep->num]->doepctl;
++00527         }
++00528 
++00529         if (core_if->dma_enable == 0 || core_if->dma_desc_enable != 0) {
++00530                 return;
++00531         } else {
++00532                 deptsiz_data_t deptsiz = {.d32 = 0 };
++00533 
++00534                 ep->xfer_len =
++00535                     ep->data_per_frame * ep->buf_proc_intrvl / ep->bInterval;
++00536                 ep->pkt_cnt =
++00537                     (ep->xfer_len - 1 + ep->maxpacket) / ep->maxpacket;
++00538                 ep->xfer_count = 0;
++00539                 ep->xfer_buff =
++00540                     (ep->proc_buf_num) ? ep->xfer_buff1 : ep->xfer_buff0;
++00541                 ep->dma_addr =
++00542                     (ep->proc_buf_num) ? ep->dma_addr1 : ep->dma_addr0;
++00543 
++00544                 if (ep->is_in) {
++00545                         /* Program the transfer size and packet count
++00546                          *      as follows: xfersize = N * maxpacket +
++00547                          *      short_packet pktcnt = N + (short_packet
++00548                          *      exist ? 1 : 0)  
++00549                          */
++00550                         deptsiz.b.mc = ep->pkt_per_frm;
++00551                         deptsiz.b.xfersize = ep->xfer_len;
++00552                         deptsiz.b.pktcnt =
++00553                             (ep->xfer_len - 1 + ep->maxpacket) / ep->maxpacket;
++00554                         dwc_write_reg32(&core_if->dev_if->in_ep_regs[ep->num]->
++00555                                         dieptsiz, deptsiz.d32);
++00556 
++00557                         /* Write the DMA register */
++00558                         dwc_write_reg32(&
++00559                                         (core_if->dev_if->in_ep_regs[ep->num]->
++00560                                          diepdma), (uint32_t) ep->dma_addr);
++00561 
++00562                 } else {
++00563                         deptsiz.b.pktcnt =
++00564                             (ep->xfer_len + (ep->maxpacket - 1)) /
++00565                             ep->maxpacket;
++00566                         deptsiz.b.xfersize = deptsiz.b.pktcnt * ep->maxpacket;
++00567 
++00568                         dwc_write_reg32(&core_if->dev_if->out_ep_regs[ep->num]->
++00569                                         doeptsiz, deptsiz.d32);
++00570 
++00571                         /* Write the DMA register */
++00572                         dwc_write_reg32(&
++00573                                         (core_if->dev_if->out_ep_regs[ep->num]->
++00574                                          doepdma), (uint32_t) ep->dma_addr);
++00575 
++00576                 }
++00578                 depctl.d32 = 0;
++00579                 dwc_modify_reg32(addr, depctl.d32, depctl.d32);
++00580 
++00581                 depctl.b.epena = 1;
++00582                 depctl.b.cnak = 1;
++00583 
++00584                 dwc_modify_reg32(addr, depctl.d32, depctl.d32);
++00585         }
++00586 }
++00587 
++00598 static void dwc_otg_iso_ep_start_transfer(dwc_otg_core_if_t * core_if,
++00599                                           dwc_ep_t * ep)
++00600 {
++00601         if (core_if->dma_enable) {
++00602                 if (core_if->dma_desc_enable) {
++00603                         if (ep->is_in) {
++00604                                 ep->desc_cnt = ep->pkt_cnt / ep->pkt_per_frm;
++00605                         } else {
++00606                                 ep->desc_cnt = ep->pkt_cnt;
++00607                         }
++00608                         dwc_otg_iso_ep_start_ddma_transfer(core_if, ep);
++00609                 } else {
++00610                         if (core_if->pti_enh_enable) {
++00611                                 dwc_otg_iso_ep_start_buf_transfer(core_if, ep);
++00612                         } else {
++00613                                 ep->cur_pkt_addr =
++00614                                     (ep->proc_buf_num) ? ep->xfer_buff1 : ep->
++00615                                     xfer_buff0;
++00616                                 ep->cur_pkt_dma_addr =
++00617                                     (ep->proc_buf_num) ? ep->dma_addr1 : ep->
++00618                                     dma_addr0;
++00619                                 dwc_otg_iso_ep_start_frm_transfer(core_if, ep);
++00620                         }
++00621                 }
++00622         } else {
++00623                 ep->cur_pkt_addr =
++00624                     (ep->proc_buf_num) ? ep->xfer_buff1 : ep->xfer_buff0;
++00625                 ep->cur_pkt_dma_addr =
++00626                     (ep->proc_buf_num) ? ep->dma_addr1 : ep->dma_addr0;
++00627                 dwc_otg_iso_ep_start_frm_transfer(core_if, ep);
++00628         }
++00629 }
++00630 
++00641 void dwc_otg_iso_ep_stop_transfer(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
++00642 {
++00643         depctl_data_t depctl = {.d32 = 0 };
++00644         volatile uint32_t *addr;
++00645 
++00646         if (ep->is_in == 1) {
++00647                 addr = &core_if->dev_if->in_ep_regs[ep->num]->diepctl;
++00648         } else {
++00649                 addr = &core_if->dev_if->out_ep_regs[ep->num]->doepctl;
++00650         }
++00651 
++00652         /* disable the ep */
++00653         depctl.d32 = dwc_read_reg32(addr);
++00654 
++00655         depctl.b.epdis = 1;
++00656         depctl.b.snak = 1;
++00657 
++00658         dwc_write_reg32(addr, depctl.d32);
++00659 
++00660         if (core_if->dma_desc_enable &&
++00661             ep->iso_desc_addr && ep->iso_dma_desc_addr) {
++00662                 dwc_otg_ep_free_desc_chain(ep->iso_desc_addr,
++00663                                            ep->iso_dma_desc_addr,
++00664                                            ep->desc_cnt * 2);
++00665         }
++00666 
++00667         /* reset varibales */
++00668         ep->dma_addr0 = 0;
++00669         ep->dma_addr1 = 0;
++00670         ep->xfer_buff0 = 0;
++00671         ep->xfer_buff1 = 0;
++00672         ep->data_per_frame = 0;
++00673         ep->data_pattern_frame = 0;
++00674         ep->sync_frame = 0;
++00675         ep->buf_proc_intrvl = 0;
++00676         ep->bInterval = 0;
++00677         ep->proc_buf_num = 0;
++00678         ep->pkt_per_frm = 0;
++00679         ep->pkt_per_frm = 0;
++00680         ep->desc_cnt = 0;
++00681         ep->iso_desc_addr = 0;
++00682         ep->iso_dma_desc_addr = 0;
++00683 }
++00684 
++00685 int dwc_otg_pcd_iso_ep_start(dwc_otg_pcd_t * pcd, void *ep_handle,
++00686                              uint8_t * buf0, uint8_t * buf1, dwc_dma_t dma0,
++00687                              dwc_dma_t dma1, int sync_frame, int dp_frame,
++00688                              int data_per_frame, int start_frame,
++00689                              int buf_proc_intrvl, void *req_handle,
++00690                              int atomic_alloc)
++00691 {
++00692         dwc_otg_pcd_ep_t *ep;
++00693         uint64_t flags = 0;
++00694         dwc_ep_t *dwc_ep;
++00695         int32_t frm_data;
++00696         dsts_data_t dsts;
++00697         dwc_otg_core_if_t *core_if;
++00698 
++00699         ep = get_ep_from_handle(pcd, ep_handle);
++00700 
++00701         if (!ep->desc || ep->dwc_ep.num == 0) {
++00702                 DWC_WARN("bad ep\n");
++00703                 return -DWC_E_INVALID;
++00704         }
++00705 
++00706         DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
++00707         core_if = GET_CORE_IF(pcd);
++00708         dwc_ep = &ep->dwc_ep;
++00709 
++00710         if (ep->iso_req_handle) {
++00711                 DWC_WARN("ISO request in progress\n");
++00712         }
++00713 
++00714         dwc_ep->dma_addr0 = dma0;
++00715         dwc_ep->dma_addr1 = dma1;
++00716 
++00717         dwc_ep->xfer_buff0 = buf0;
++00718         dwc_ep->xfer_buff1 = buf1;
++00719 
++00720         dwc_ep->data_per_frame = data_per_frame;
++00721 
++00723         dwc_ep->data_pattern_frame = dp_frame;
++00724         dwc_ep->sync_frame = sync_frame;
++00725 
++00726         dwc_ep->buf_proc_intrvl = buf_proc_intrvl;
++00727 
++00728         dwc_ep->bInterval = 1 << (ep->desc->bInterval - 1);
++00729 
++00730         dwc_ep->proc_buf_num = 0;
++00731 
++00732         dwc_ep->pkt_per_frm = 0;
++00733         frm_data = ep->dwc_ep.data_per_frame;
++00734         while (frm_data > 0) {
++00735                 dwc_ep->pkt_per_frm++;
++00736                 frm_data -= ep->dwc_ep.maxpacket;
++00737         }
++00738 
++00739         dsts.d32 = dwc_read_reg32(&core_if->dev_if->dev_global_regs->dsts);
++00740 
++00741         if (start_frame == -1) {
++00742                 dwc_ep->next_frame = dsts.b.soffn + 1;
++00743                 if (dwc_ep->bInterval != 1) {
++00744                         dwc_ep->next_frame =
++00745                             dwc_ep->next_frame + (dwc_ep->bInterval - 1 -
++00746                                                   dwc_ep->next_frame %
++00747                                                   dwc_ep->bInterval);
++00748                 }
++00749         } else {
++00750                 dwc_ep->next_frame = start_frame;
++00751         }
++00752 
++00753         if (!core_if->pti_enh_enable) {
++00754                 dwc_ep->pkt_cnt =
++00755                     dwc_ep->buf_proc_intrvl * dwc_ep->pkt_per_frm /
++00756                     dwc_ep->bInterval;
++00757         } else {
++00758                 dwc_ep->pkt_cnt =
++00759                     (dwc_ep->data_per_frame *
++00760                      (dwc_ep->buf_proc_intrvl / dwc_ep->bInterval)
++00761                      - 1 + dwc_ep->maxpacket) / dwc_ep->maxpacket;
++00762         }
++00763 
++00764         if (core_if->dma_desc_enable) {
++00765                 dwc_ep->desc_cnt =
++00766                     dwc_ep->buf_proc_intrvl * dwc_ep->pkt_per_frm /
++00767                     dwc_ep->bInterval;
++00768         }
++00769 
++00770         if (atomic_alloc) {
++00771                 dwc_ep->pkt_info =
++00772                     dwc_alloc_atomic(sizeof(iso_pkt_info_t) * dwc_ep->pkt_cnt);
++00773         } else {
++00774                 dwc_ep->pkt_info =
++00775                     dwc_alloc(sizeof(iso_pkt_info_t) * dwc_ep->pkt_cnt);
++00776         }
++00777         if (!dwc_ep->pkt_info) {
++00778                 DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
++00779                 return -DWC_E_NO_MEMORY;
++00780         }
++00781         if (core_if->pti_enh_enable) {
++00782                 dwc_memset(dwc_ep->pkt_info, 0,
++00783                            sizeof(iso_pkt_info_t) * dwc_ep->pkt_cnt);
++00784         }
++00785 
++00786         dwc_ep->cur_pkt = 0;
++00787         ep->iso_req_handle = req_handle;
++00788 
++00789         DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
++00790         dwc_otg_iso_ep_start_transfer(core_if, dwc_ep);
++00791         return 0;
++00792 }
++00793 
++00794 int dwc_otg_pcd_iso_ep_stop(dwc_otg_pcd_t * pcd, void *ep_handle,
++00795                             void *req_handle)
++00796 {
++00797         uint64_t flags = 0;
++00798         dwc_otg_pcd_ep_t *ep;
++00799         dwc_ep_t *dwc_ep;
++00800 
++00801         ep = get_ep_from_handle(pcd, ep_handle);
++00802         if (!ep || !ep->desc || ep->dwc_ep.num == 0) {
++00803                 DWC_WARN("bad ep\n");
++00804                 return -DWC_E_INVALID;
++00805         }
++00806         dwc_ep = &ep->dwc_ep;
++00807 
++00808         dwc_otg_iso_ep_stop_transfer(GET_CORE_IF(pcd), dwc_ep);
++00809 
++00810         dwc_free(dwc_ep->pkt_info);
++00811         DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
++00812         if (ep->iso_req_handle != req_handle) {
++00813                 DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
++00814                 return -DWC_E_INVALID;
++00815         }
++00816 
++00817         DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
++00818 
++00819         ep->iso_req_handle = 0;
++00820         return 0;
++00821 }
++00822 
++00830 void dwc_otg_iso_buffer_done(dwc_otg_pcd_t * pcd, dwc_otg_pcd_ep_t * ep,
++00831                              void *req_handle)
++00832 {
++00833         int i;
++00834         dwc_ep_t *dwc_ep;
++00835 
++00836         dwc_ep = &ep->dwc_ep;
++00837 
++00838         DWC_SPINUNLOCK(ep->pcd->lock);
++00839         pcd->fops->isoc_complete(pcd, ep->priv, ep->iso_req_handle,
++00840                                  dwc_ep->proc_buf_num ^ 0x1);
++00841         DWC_SPINLOCK(ep->pcd->lock);
++00842 
++00843         for (i = 0; i < dwc_ep->pkt_cnt; ++i) {
++00844                 dwc_ep->pkt_info[i].status = 0;
++00845                 dwc_ep->pkt_info[i].offset = 0;
++00846                 dwc_ep->pkt_info[i].length = 0;
++00847         }
++00848 }
++00849 
++00850 int dwc_otg_pcd_get_iso_packet_count(dwc_otg_pcd_t * pcd, void *ep_handle,
++00851                                      void *iso_req_handle)
++00852 {
++00853         dwc_otg_pcd_ep_t *ep;
++00854         dwc_ep_t *dwc_ep;
++00855 
++00856         ep = get_ep_from_handle(pcd, ep_handle);
++00857         dwc_ep = &ep->dwc_ep;
++00858 
++00859         return dwc_ep->pkt_cnt;
++00860 }
++00861 
++00862 void dwc_otg_pcd_get_iso_packet_params(dwc_otg_pcd_t * pcd, void *ep_handle,
++00863                                        void *iso_req_handle, int packet,
++00864                                        int *status, int *actual, int *offset)
++00865 {
++00866         dwc_otg_pcd_ep_t *ep;
++00867         dwc_ep_t *dwc_ep;
++00868 
++00869         ep = get_ep_from_handle(pcd, ep_handle);
++00870         dwc_ep = &ep->dwc_ep;
++00871 
++00872         *status = dwc_ep->pkt_info[packet].status;
++00873         *actual = dwc_ep->pkt_info[packet].length;
++00874         *offset = dwc_ep->pkt_info[packet].offset;
++00875 }
++00876 
++00877 #endif                          /* DWC_EN_ISOC */
++00878 
++00879 static void dwc_otg_pcd_init_ep(dwc_otg_pcd_t * pcd, dwc_otg_pcd_ep_t * pcd_ep,
++00880                                 uint32_t is_in, uint32_t ep_num)
++00881 {
++00882         /* Init EP structure */
++00883         pcd_ep->desc = 0;
++00884         pcd_ep->pcd = pcd;
++00885         pcd_ep->stopped = 1;
++00886         pcd_ep->queue_sof = 0;
++00887 
++00888         /* Init DWC ep structure */
++00889         pcd_ep->dwc_ep.is_in = is_in;
++00890         pcd_ep->dwc_ep.num = ep_num;
++00891         pcd_ep->dwc_ep.active = 0;
++00892         pcd_ep->dwc_ep.tx_fifo_num = 0;
++00893         /* Control until ep is actvated */
++00894         pcd_ep->dwc_ep.type = DWC_OTG_EP_TYPE_CONTROL;
++00895         pcd_ep->dwc_ep.maxpacket = MAX_PACKET_SIZE;
++00896         pcd_ep->dwc_ep.dma_addr = 0;
++00897         pcd_ep->dwc_ep.start_xfer_buff = 0;
++00898         pcd_ep->dwc_ep.xfer_buff = 0;
++00899         pcd_ep->dwc_ep.xfer_len = 0;
++00900         pcd_ep->dwc_ep.xfer_count = 0;
++00901         pcd_ep->dwc_ep.sent_zlp = 0;
++00902         pcd_ep->dwc_ep.total_len = 0;
++00903         pcd_ep->dwc_ep.desc_addr = 0;
++00904         pcd_ep->dwc_ep.dma_desc_addr = 0;
++00905         DWC_CIRCLEQ_INIT(&pcd_ep->queue);
++00906 }
++00907 
++00911 static void dwc_otg_pcd_reinit(dwc_otg_pcd_t * pcd)
++00912 {
++00913         int i;
++00914         uint32_t hwcfg1;
++00915         dwc_otg_pcd_ep_t *ep;
++00916         int in_ep_cntr, out_ep_cntr;
++00917         uint32_t num_in_eps = (GET_CORE_IF(pcd))->dev_if->num_in_eps;
++00918         uint32_t num_out_eps = (GET_CORE_IF(pcd))->dev_if->num_out_eps;
++00919 
++00923         ep = &pcd->ep0;
++00924         dwc_otg_pcd_init_ep(pcd, ep, 0, 0);
++00925 
++00926         in_ep_cntr = 0;
++00927         hwcfg1 = (GET_CORE_IF(pcd))->hwcfg1.d32 >> 3;
++00928         for (i = 1; in_ep_cntr < num_in_eps; i++) {
++00929                 if ((hwcfg1 & 0x1) == 0) {
++00930                         dwc_otg_pcd_ep_t *ep = &pcd->in_ep[in_ep_cntr];
++00931                         in_ep_cntr++;
++00937                         dwc_otg_pcd_init_ep(pcd, ep, 1 /* IN */ , i);
++00938 
++00939                         DWC_CIRCLEQ_INIT(&ep->queue);
++00940                 }
++00941                 hwcfg1 >>= 2;
++00942         }
++00943 
++00944         out_ep_cntr = 0;
++00945         hwcfg1 = (GET_CORE_IF(pcd))->hwcfg1.d32 >> 2;
++00946         for (i = 1; out_ep_cntr < num_out_eps; i++) {
++00947                 if ((hwcfg1 & 0x1) == 0) {
++00948                         dwc_otg_pcd_ep_t *ep = &pcd->out_ep[out_ep_cntr];
++00949                         out_ep_cntr++;
++00955                         dwc_otg_pcd_init_ep(pcd, ep, 0 /* OUT */ , i);
++00956                         DWC_CIRCLEQ_INIT(&ep->queue);
++00957                 }
++00958                 hwcfg1 >>= 2;
++00959         }
++00960 
++00961         pcd->ep0state = EP0_DISCONNECT;
++00962         pcd->ep0.dwc_ep.maxpacket = MAX_EP0_SIZE;
++00963         pcd->ep0.dwc_ep.type = DWC_OTG_EP_TYPE_CONTROL;
++00964 }
++00965 
++00970 static void srp_timeout(void *ptr)
++00971 {
++00972         gotgctl_data_t gotgctl;
++00973         dwc_otg_core_if_t *core_if = (dwc_otg_core_if_t *) ptr;
++00974         volatile uint32_t *addr = &core_if->core_global_regs->gotgctl;
++00975 
++00976         gotgctl.d32 = dwc_read_reg32(addr);
++00977 
++00978         core_if->srp_timer_started = 0;
++00979 
++00980         if ((core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS) &&
++00981             (core_if->core_params->i2c_enable)) {
++00982                 DWC_PRINTF("SRP Timeout\n");
++00983 
++00984                 if ((core_if->srp_success) && (gotgctl.b.bsesvld)) {
++00985                         if (core_if->pcd_cb && core_if->pcd_cb->resume_wakeup) {
++00986                                 core_if->pcd_cb->resume_wakeup(core_if->pcd_cb->
++00987                                                                p);
++00988                         }
++00989 
++00990                         /* Clear Session Request */
++00991                         gotgctl.d32 = 0;
++00992                         gotgctl.b.sesreq = 1;
++00993                         dwc_modify_reg32(&core_if->core_global_regs->gotgctl,
++00994                                          gotgctl.d32, 0);
++00995 
++00996                         core_if->srp_success = 0;
++00997                 } else {
++00998                         __DWC_ERROR("Device not connected/responding\n");
++00999                         gotgctl.b.sesreq = 0;
++01000                         dwc_write_reg32(addr, gotgctl.d32);
++01001                 }
++01002         } else if (gotgctl.b.sesreq) {
++01003                 DWC_PRINTF("SRP Timeout\n");
++01004 
++01005                 __DWC_ERROR("Device not connected/responding\n");
++01006                 gotgctl.b.sesreq = 0;
++01007                 dwc_write_reg32(addr, gotgctl.d32);
++01008         } else {
++01009                 DWC_PRINTF(" SRP GOTGCTL=%0x\n", gotgctl.d32);
++01010         }
++01011 }
++01012 
++01017 extern void start_next_request(dwc_otg_pcd_ep_t * ep);
++01018 
++01019 static void start_xfer_tasklet_func(void *data)
++01020 {
++01021         dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *) data;
++01022         dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
++01023 
++01024         int i;
++01025         depctl_data_t diepctl;
++01026 
++01027         DWC_DEBUGPL(DBG_PCDV, "Start xfer tasklet\n");
++01028 
++01029         diepctl.d32 = dwc_read_reg32(&core_if->dev_if->in_ep_regs[0]->diepctl);
++01030 
++01031         if (pcd->ep0.queue_sof) {
++01032                 pcd->ep0.queue_sof = 0;
++01033                 start_next_request(&pcd->ep0);
++01034                 // break;
++01035         }
++01036 
++01037         for (i = 0; i < core_if->dev_if->num_in_eps; i++) {
++01038                 depctl_data_t diepctl;
++01039                 diepctl.d32 =
++01040                     dwc_read_reg32(&core_if->dev_if->in_ep_regs[i]->diepctl);
++01041 
++01042                 if (pcd->in_ep[i].queue_sof) {
++01043                         pcd->in_ep[i].queue_sof = 0;
++01044                         start_next_request(&pcd->in_ep[i]);
++01045                         // break;
++01046                 }
++01047         }
++01048 
++01049         return;
++01050 }
++01051 
++01056 dwc_otg_pcd_t *dwc_otg_pcd_init(dwc_otg_core_if_t * core_if)
++01057 {
++01058         dwc_otg_pcd_t *pcd = 0;
++01059         dwc_otg_dev_if_t *dev_if;
++01060 
++01061         /*
++01062          * Allocate PCD structure
++01063          */
++01064         pcd = dwc_alloc(sizeof(dwc_otg_pcd_t));
++01065 
++01066         if (pcd == 0) {
++01067                 return NULL;
++01068         }
++01069 
++01070         pcd->lock = DWC_SPINLOCK_ALLOC();
++01071         pcd->core_if = core_if;
++01072         if (!pcd->lock) {
++01073                 DWC_ERROR("Could not allocate lock for pcd");
++01074                 dwc_free(pcd);
++01075                 return NULL;
++01076         }
++01077         dev_if = core_if->dev_if;
++01078 
++01079         if (core_if->hwcfg4.b.ded_fifo_en) {
++01080                 DWC_PRINTF("Dedicated Tx FIFOs mode\n");
++01081         } else {
++01082                 DWC_PRINTF("Shared Tx FIFO mode\n");
++01083         }
++01084 
++01085         /*
++01086          * Initialized the Core for Device mode.
++01087          */
++01088         if (dwc_otg_is_device_mode(core_if)) {
++01089                 dwc_otg_core_dev_init(core_if);
++01090         }
++01091 
++01092         /*
++01093          * Register the PCD Callbacks.
++01094          */
++01095         dwc_otg_cil_register_pcd_callbacks(core_if, &pcd_callbacks, pcd);
++01096 
++01097         /*
++01098          * Initialize the DMA buffer for SETUP packets
++01099          */
++01100         if (GET_CORE_IF(pcd)->dma_enable) {
++01101                 pcd->setup_pkt =
++01102                     dwc_dma_alloc(sizeof(*pcd->setup_pkt) * 5,
++01103                                   &pcd->setup_pkt_dma_handle);
++01104                 if (pcd->setup_pkt == 0) {
++01105                         dwc_free(pcd);
++01106                         return NULL;
++01107                 }
++01108 
++01109                 pcd->status_buf =
++01110                     dwc_dma_alloc(sizeof(uint16_t),
++01111                                   &pcd->status_buf_dma_handle);
++01112                 if (pcd->status_buf == 0) {
++01113                         dwc_dma_free(sizeof(*pcd->setup_pkt) * 5,
++01114                                      pcd->setup_pkt, pcd->setup_pkt_dma_handle);
++01115                         dwc_free(pcd);
++01116                         return NULL;
++01117                 }
++01118 
++01119                 if (GET_CORE_IF(pcd)->dma_desc_enable) {
++01120                         dev_if->setup_desc_addr[0] =
++01121                             dwc_otg_ep_alloc_desc_chain(&dev_if->
++01122                                                         dma_setup_desc_addr[0],
++01123                                                         1);
++01124                         dev_if->setup_desc_addr[1] =
++01125                             dwc_otg_ep_alloc_desc_chain(&dev_if->
++01126                                                         dma_setup_desc_addr[1],
++01127                                                         1);
++01128                         dev_if->in_desc_addr =
++01129                             dwc_otg_ep_alloc_desc_chain(&dev_if->
++01130                                                         dma_in_desc_addr, 1);
++01131                         dev_if->out_desc_addr =
++01132                             dwc_otg_ep_alloc_desc_chain(&dev_if->
++01133                                                         dma_out_desc_addr, 1);
++01134 
++01135                         if (dev_if->setup_desc_addr[0] == 0
++01136                             || dev_if->setup_desc_addr[1] == 0
++01137                             || dev_if->in_desc_addr == 0
++01138                             || dev_if->out_desc_addr == 0) {
++01139 
++01140                                 if (dev_if->out_desc_addr)
++01141                                         dwc_otg_ep_free_desc_chain(dev_if->
++01142                                                                    out_desc_addr,
++01143                                                                    dev_if->
++01144                                                                    dma_out_desc_addr,
++01145                                                                    1);
++01146                                 if (dev_if->in_desc_addr)
++01147                                         dwc_otg_ep_free_desc_chain(dev_if->
++01148                                                                    in_desc_addr,
++01149                                                                    dev_if->
++01150                                                                    dma_in_desc_addr,
++01151                                                                    1);
++01152                                 if (dev_if->setup_desc_addr[1])
++01153                                         dwc_otg_ep_free_desc_chain(dev_if->
++01154                                                                    setup_desc_addr
++01155                                                                    [1],
++01156                                                                    dev_if->
++01157                                                                    dma_setup_desc_addr
++01158                                                                    [1], 1);
++01159                                 if (dev_if->setup_desc_addr[0])
++01160                                         dwc_otg_ep_free_desc_chain(dev_if->
++01161                                                                    setup_desc_addr
++01162                                                                    [0],
++01163                                                                    dev_if->
++01164                                                                    dma_setup_desc_addr
++01165                                                                    [0], 1);
++01166 
++01167                                 dwc_dma_free(sizeof(*pcd->setup_pkt) * 5,
++01168                                              pcd->setup_pkt,
++01169                                              pcd->setup_pkt_dma_handle);
++01170                                 dwc_dma_free(sizeof(*pcd->status_buf),
++01171                                              pcd->status_buf,
++01172                                              pcd->status_buf_dma_handle);
++01173 
++01174                                 dwc_free(pcd);
++01175 
++01176                                 return NULL;
++01177                         }
++01178                 }
++01179         } else {
++01180                 pcd->setup_pkt = dwc_alloc(sizeof(*pcd->setup_pkt) * 5);
++01181                 if (pcd->setup_pkt == 0) {
++01182                         dwc_free(pcd);
++01183                         return NULL;
++01184                 }
++01185 
++01186                 pcd->status_buf = dwc_alloc(sizeof(uint16_t));
++01187                 if (pcd->status_buf == 0) {
++01188                         dwc_free(pcd->setup_pkt);
++01189                         dwc_free(pcd);
++01190                         return NULL;
++01191                 }
++01192         }
++01193 
++01194         dwc_otg_pcd_reinit(pcd);
++01195 
++01196         /* Allocate the cfi object for the PCD */
++01197 #ifdef DWC_UTE_CFI
++01198         pcd->cfi = dwc_alloc(sizeof(cfiobject_t));
++01199         if (NULL == pcd->cfi)
++01200                 return NULL;
++01201         if (init_cfi(pcd->cfi)) {
++01202                 CFI_INFO("%s: Failed to init the CFI object\n", __func__);
++01203                 return NULL;
++01204         }
++01205 #endif
++01206 
++01207         /* Initialize tasklets */
++01208         pcd->start_xfer_tasklet = DWC_TASK_ALLOC(start_xfer_tasklet_func, pcd);
++01209         pcd->test_mode_tasklet = DWC_TASK_ALLOC(do_test_mode, pcd);
++01210         /* Initialize timer */
++01211         pcd->srp_timer = DWC_TIMER_ALLOC("SRP TIMER", srp_timeout, core_if);
++01212         return pcd;
++01213 }
++01214 
++01215 void dwc_otg_pcd_remove(dwc_otg_pcd_t * pcd)
++01216 {
++01217         dwc_otg_dev_if_t *dev_if = GET_CORE_IF(pcd)->dev_if;
++01218 
++01219         if (GET_CORE_IF(pcd)->dma_enable) {
++01220                 dwc_dma_free(sizeof(*pcd->setup_pkt) * 5, pcd->setup_pkt,
++01221                              pcd->setup_pkt_dma_handle);
++01222                 dwc_dma_free(sizeof(uint16_t), pcd->status_buf,
++01223                              pcd->status_buf_dma_handle);
++01224                 if (GET_CORE_IF(pcd)->dma_desc_enable) {
++01225                         dwc_otg_ep_free_desc_chain(dev_if->setup_desc_addr[0],
++01226                                                    dev_if->
++01227                                                    dma_setup_desc_addr[0], 1);
++01228                         dwc_otg_ep_free_desc_chain(dev_if->setup_desc_addr[1],
++01229                                                    dev_if->
++01230                                                    dma_setup_desc_addr[1], 1);
++01231                         dwc_otg_ep_free_desc_chain(dev_if->in_desc_addr,
++01232                                                    dev_if->dma_in_desc_addr, 1);
++01233                         dwc_otg_ep_free_desc_chain(dev_if->out_desc_addr,
++01234                                                    dev_if->dma_out_desc_addr,
++01235                                                    1);
++01236                 }
++01237         } else {
++01238                 dwc_free(pcd->setup_pkt);
++01239                 dwc_free(pcd->status_buf);
++01240         }
++01241         DWC_SPINLOCK_FREE(pcd->lock);
++01242         DWC_TASK_FREE(pcd->start_xfer_tasklet);
++01243         DWC_TASK_FREE(pcd->test_mode_tasklet);
++01244         DWC_TIMER_FREE(pcd->srp_timer);
++01245 
++01246 /* Release the CFI object's dynamic memory */
++01247 #ifdef DWC_UTE_CFI
++01248         if (pcd->cfi->ops.release) {
++01249                 pcd->cfi->ops.release(pcd->cfi);
++01250         }
++01251 #endif
++01252 
++01253         dwc_free(pcd);
++01254 }
++01255 
++01256 uint32_t dwc_otg_pcd_is_dualspeed(dwc_otg_pcd_t * pcd)
++01257 {
++01258         dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
++01259 
++01260         if ((core_if->core_params->speed == DWC_SPEED_PARAM_FULL) ||
++01261             ((core_if->hwcfg2.b.hs_phy_type == 2) &&
++01262              (core_if->hwcfg2.b.fs_phy_type == 1) &&
++01263              (core_if->core_params->ulpi_fs_ls))) {
++01264                 return 0;
++01265         }
++01266 
++01267         return 1;
++01268 }
++01269 
++01270 uint32_t dwc_otg_pcd_is_otg(dwc_otg_pcd_t * pcd)
++01271 {
++01272         dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
++01273         gusbcfg_data_t usbcfg = {.d32 = 0 };
++01274 
++01275         usbcfg.d32 = dwc_read_reg32(&core_if->core_global_regs->gusbcfg);
++01276         if (!usbcfg.b.srpcap || !usbcfg.b.hnpcap) {
++01277                 return 0;
++01278         }
++01279 
++01280         return 1;
++01281 }
++01282 
++01287 static uint32_t assign_tx_fifo(dwc_otg_core_if_t * core_if)
++01288 {
++01289         uint32_t TxMsk = 1;
++01290         int i;
++01291 
++01292         for (i = 0; i < core_if->hwcfg4.b.num_in_eps; ++i) {
++01293                 if ((TxMsk & core_if->tx_msk) == 0) {
++01294                         core_if->tx_msk |= TxMsk;
++01295                         return i + 1;
++01296                 }
++01297                 TxMsk <<= 1;
++01298         }
++01299         return 0;
++01300 }
++01301 
++01306 static uint32_t assign_perio_tx_fifo(dwc_otg_core_if_t * core_if)
++01307 {
++01308         uint32_t PerTxMsk = 1;
++01309         int i;
++01310         for (i = 0; i < core_if->hwcfg4.b.num_dev_perio_in_ep; ++i) {
++01311                 if ((PerTxMsk & core_if->p_tx_msk) == 0) {
++01312                         core_if->p_tx_msk |= PerTxMsk;
++01313                         return i + 1;
++01314                 }
++01315                 PerTxMsk <<= 1;
++01316         }
++01317         return 0;
++01318 }
++01319 
++01324 static void release_perio_tx_fifo(dwc_otg_core_if_t * core_if,
++01325                                   uint32_t fifo_num)
++01326 {
++01327         core_if->p_tx_msk =
++01328             (core_if->p_tx_msk & (1 << (fifo_num - 1))) ^ core_if->p_tx_msk;
++01329 }
++01330 
++01335 static void release_tx_fifo(dwc_otg_core_if_t * core_if, uint32_t fifo_num)
++01336 {
++01337         core_if->tx_msk =
++01338             (core_if->tx_msk & (1 << (fifo_num - 1))) ^ core_if->tx_msk;
++01339 }
++01340 
++01341 int dwc_otg_pcd_ep_enable(dwc_otg_pcd_t * pcd,
++01342                           const uint8_t * ep_desc, void *usb_ep)
++01343 {
++01344         int num, dir;
++01345         dwc_otg_pcd_ep_t *ep = 0;
++01346         const usb_endpoint_descriptor_t *desc;
++01347         uint64_t flags;
++01348         int retval = 0;
++01349 
++01350         desc = (const usb_endpoint_descriptor_t *)ep_desc;
++01351 
++01352         if (!desc) {
++01353                 pcd->ep0.priv = usb_ep;
++01354                 ep = &pcd->ep0;
++01355                 retval = -DWC_E_INVALID;
++01356                 goto out;
++01357         }
++01358 
++01359         num = UE_GET_ADDR(desc->bEndpointAddress);
++01360         dir = UE_GET_DIR(desc->bEndpointAddress);
++01361 
++01362         if (!desc->wMaxPacketSize) {
++01363                 DWC_WARN("bad maxpacketsize\n");
++01364                 retval = -DWC_E_INVALID;
++01365                 goto out;
++01366         }
++01367 
++01368         if (dir == UE_DIR_IN) {
++01369                 ep = &pcd->in_ep[num - 1];
++01370         } else {
++01371                 ep = &pcd->out_ep[num - 1];
++01372         }
++01373 
++01374         DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
++01375 
++01376         ep->desc = desc;
++01377         ep->priv = usb_ep;
++01378 
++01379         /*
++01380          * Activate the EP
++01381          */
++01382         ep->stopped = 0;
++01383 
++01384         ep->dwc_ep.is_in = (dir == UE_DIR_IN);
++01385         ep->dwc_ep.maxpacket = UGETW(desc->wMaxPacketSize);
++01386 
++01387         ep->dwc_ep.type = desc->bmAttributes & UE_XFERTYPE;
++01388 
++01389         if (ep->dwc_ep.is_in) {
++01390                 if (!GET_CORE_IF(pcd)->en_multiple_tx_fifo) {
++01391                         ep->dwc_ep.tx_fifo_num = 0;
++01392 
++01393                         if (ep->dwc_ep.type == UE_ISOCHRONOUS) {
++01394                                 /*
++01395                                  * if ISOC EP then assign a Periodic Tx FIFO.
++01396                                  */
++01397                                 ep->dwc_ep.tx_fifo_num =
++01398                                     assign_perio_tx_fifo(GET_CORE_IF(pcd));
++01399                         }
++01400                 } else {
++01401                         /*
++01402                          * if Dedicated FIFOs mode is on then assign a Tx FIFO.
++01403                          */
++01404                         ep->dwc_ep.tx_fifo_num =
++01405                             assign_tx_fifo(GET_CORE_IF(pcd));
++01406 
++01407                 }
++01408         }
++01409         /* Set initial data PID. */
++01410         if (ep->dwc_ep.type == UE_BULK) {
++01411                 ep->dwc_ep.data_pid_start = 0;
++01412         }
++01413 
++01414         /* Alloc DMA Descriptors */
++01415         if (GET_CORE_IF(pcd)->dma_desc_enable) {
++01416                 if (ep->dwc_ep.type != UE_ISOCHRONOUS) {
++01417                         ep->dwc_ep.desc_addr =
++01418                             dwc_otg_ep_alloc_desc_chain(&ep->dwc_ep.
++01419                                                         dma_desc_addr,
++01420                                                         MAX_DMA_DESC_CNT);
++01421                         if (!ep->dwc_ep.desc_addr) {
++01422                                 DWC_WARN("%s, can't allocate DMA descriptor\n",
++01423                                          __func__);
++01424                                 retval = -DWC_E_SHUTDOWN;
++01425                                 DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
++01426                                 goto out;
++01427                         }
++01428                 }
++01429         }
++01430 
++01431         DWC_DEBUGPL(DBG_PCD, "Activate %s: type=%d, mps=%d desc=%p\n",
++01432                     (ep->dwc_ep.is_in ? "IN" : "OUT"),
++01433                     ep->dwc_ep.type, ep->dwc_ep.maxpacket, ep->desc);
++01434 
++01435         dwc_otg_ep_activate(GET_CORE_IF(pcd), &ep->dwc_ep);
++01436 
++01437 #ifdef DWC_UTE_CFI
++01438         if (pcd->cfi->ops.ep_enable) {
++01439                 pcd->cfi->ops.ep_enable(pcd->cfi, pcd, ep);
++01440         }
++01441 #endif
++01442 
++01443         DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
++01444 
++01445       out:
++01446         return retval;
++01447 }
++01448 
++01449 int dwc_otg_pcd_ep_disable(dwc_otg_pcd_t * pcd, void *ep_handle)
++01450 {
++01451         dwc_otg_pcd_ep_t *ep;
++01452         uint64_t flags;
++01453         dwc_otg_dev_dma_desc_t *desc_addr;
++01454         dwc_dma_t dma_desc_addr;
++01455 
++01456         ep = get_ep_from_handle(pcd, ep_handle);
++01457 
++01458         if (!ep || !ep->desc) {
++01459                 DWC_DEBUGPL(DBG_PCD, "%s, %d %s not enabled\n", __func__,
++01460                             ep->dwc_ep.num, ep->dwc_ep.is_in ? "IN" : "OUT");
++01461                 return -DWC_E_INVALID;
++01462         }
++01463 
++01464         DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
++01465 
++01466         dwc_otg_request_nuke(ep);
++01467 
++01468         dwc_otg_ep_deactivate(GET_CORE_IF(pcd), &ep->dwc_ep);
++01469         ep->desc = 0;
++01470         ep->stopped = 1;
++01471 
++01472         if (ep->dwc_ep.is_in) {
++01473                 dwc_otg_flush_tx_fifo(GET_CORE_IF(pcd), ep->dwc_ep.tx_fifo_num);
++01474                 release_perio_tx_fifo(GET_CORE_IF(pcd), ep->dwc_ep.tx_fifo_num);
++01475                 release_tx_fifo(GET_CORE_IF(pcd), ep->dwc_ep.tx_fifo_num);
++01476         }
++01477 
++01478         /* Free DMA Descriptors */
++01479         if (GET_CORE_IF(pcd)->dma_desc_enable) {
++01480                 if (ep->dwc_ep.type != UE_ISOCHRONOUS) {
++01481                         desc_addr = ep->dwc_ep.desc_addr;
++01482                         dma_desc_addr = ep->dwc_ep.dma_desc_addr;
++01483 
++01484                         /* Cannot call dma_free_coherent() with IRQs disabled */
++01485                         DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
++01486                         dwc_otg_ep_free_desc_chain(desc_addr, dma_desc_addr,
++01487                                                    MAX_DMA_DESC_CNT);
++01488 
++01489                         goto out_unlocked;
++01490                 }
++01491         }
++01492 
++01493         DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
++01494 
++01495       out_unlocked:
++01496         DWC_DEBUGPL(DBG_PCD, "%d %s disabled\n", ep->dwc_ep.num,
++01497                     ep->dwc_ep.is_in ? "IN" : "OUT");
++01498         return 0;
++01499 
++01500 }
++01501 
++01502 int dwc_otg_pcd_ep_queue(dwc_otg_pcd_t * pcd, void *ep_handle,
++01503                          uint8_t * buf, dwc_dma_t dma_buf, uint32_t buflen,
++01504                          int zero, void *req_handle, int atomic_alloc)
++01505 {
++01506         int prevented = 0;
++01507         uint64_t flags;
++01508         dwc_otg_pcd_request_t *req;
++01509         dwc_otg_pcd_ep_t *ep;
++01510         uint32_t max_transfer;
++01511 
++01512         ep = get_ep_from_handle(pcd, ep_handle);
++01513         if ((!ep->desc && ep->dwc_ep.num != 0)) {
++01514                 DWC_WARN("bad ep\n");
++01515                 return -DWC_E_INVALID;
++01516         }
++01517 
++01518         if (atomic_alloc) {
++01519                 req = dwc_alloc_atomic(sizeof(*req));
++01520         } else {
++01521                 req = dwc_alloc(sizeof(*req));
++01522         }
++01523 
++01524         if (!req) {
++01525                 return -DWC_E_NO_MEMORY;
++01526         }
++01527         DWC_CIRCLEQ_INIT_ENTRY(req, queue_entry);
++01528         if (!GET_CORE_IF(pcd)->core_params->opt) {
++01529                 if (ep->dwc_ep.num != 0) {
++01530                         DWC_ERROR("queue req %p, len %d buf %p\n",
++01531                                   req_handle, buflen, buf);
++01532                 }
++01533         }
++01534 
++01535         req->buf = buf;
++01536         req->dma = dma_buf;
++01537         req->length = buflen;
++01538         req->sent_zlp = zero;
++01539         req->priv = req_handle;
++01540 
++01541         DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
++01542 
++01543         /*
++01544          * For EP0 IN without premature status, zlp is required?
++01545          */
++01546         if (ep->dwc_ep.num == 0 && ep->dwc_ep.is_in) {
++01547                 DWC_DEBUGPL(DBG_PCDV, "%d-OUT ZLP\n", ep->dwc_ep.num);
++01548                 //_req->zero = 1;
++01549         }
++01550 
++01551         /* Start the transfer */
++01552         if (DWC_CIRCLEQ_EMPTY(&ep->queue) && !ep->stopped) {
++01553                 /* EP0 Transfer? */
++01554                 if (ep->dwc_ep.num == 0) {
++01555                         switch (pcd->ep0state) {
++01556                         case EP0_IN_DATA_PHASE:
++01557                                 DWC_DEBUGPL(DBG_PCD,
++01558                                             "%s ep0: EP0_IN_DATA_PHASE\n",
++01559                                             __func__);
++01560                                 break;
++01561 
++01562                         case EP0_OUT_DATA_PHASE:
++01563                                 DWC_DEBUGPL(DBG_PCD,
++01564                                             "%s ep0: EP0_OUT_DATA_PHASE\n",
++01565                                             __func__);
++01566                                 if (pcd->request_config) {
++01567                                         /* Complete STATUS PHASE */
++01568                                         ep->dwc_ep.is_in = 1;
++01569                                         pcd->ep0state = EP0_IN_STATUS_PHASE;
++01570                                 }
++01571                                 break;
++01572 
++01573                         case EP0_IN_STATUS_PHASE:
++01574                                 DWC_DEBUGPL(DBG_PCD,
++01575                                             "%s ep0: EP0_IN_STATUS_PHASE\n",
++01576                                             __func__);
++01577                                 break;
++01578 
++01579                         default:
++01580                                 DWC_DEBUGPL(DBG_ANY, "ep0: odd state %d\n",
++01581                                             pcd->ep0state);
++01582                                 DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
++01583                                 return -DWC_E_SHUTDOWN;
++01584                         }
++01585 
++01586                         ep->dwc_ep.dma_addr = dma_buf;
++01587                         ep->dwc_ep.start_xfer_buff = buf;
++01588                         ep->dwc_ep.xfer_buff = buf;
++01589                         ep->dwc_ep.xfer_len = buflen;
++01590                         ep->dwc_ep.xfer_count = 0;
++01591                         ep->dwc_ep.sent_zlp = 0;
++01592                         ep->dwc_ep.total_len = ep->dwc_ep.xfer_len;
++01593 
++01594                         if (zero) {
++01595                                 if ((ep->dwc_ep.xfer_len %
++01596                                      ep->dwc_ep.maxpacket == 0)
++01597                                     && (ep->dwc_ep.xfer_len != 0)) {
++01598                                         ep->dwc_ep.sent_zlp = 1;
++01599                                 }
++01600 
++01601                         }
++01602 
++01603                         dwc_otg_ep0_start_transfer(GET_CORE_IF(pcd),
++01604                                                    &ep->dwc_ep);
++01605                 }               // non-ep0 endpoints
++01606                 else {
++01607 #ifdef DWC_UTE_CFI
++01608                         if (ep->dwc_ep.buff_mode != BM_STANDARD) {
++01609                                 /* store the request length */
++01610                                 ep->dwc_ep.cfi_req_len = buflen;
++01611                                 pcd->cfi->ops.build_descriptors(pcd->cfi, pcd,
++01612                                                                 ep, req);
++01613                 } else {
++01614 #endif
++01615                                 max_transfer =
++01616                                     GET_CORE_IF(ep->pcd)->core_params->
++01617                                     max_transfer_size;
++01618 
++01619                         /* Setup and start the Transfer */
++01620                         ep->dwc_ep.dma_addr = dma_buf;
++01621                         ep->dwc_ep.start_xfer_buff = buf;
++01622                         ep->dwc_ep.xfer_buff = buf;
++01623                         ep->dwc_ep.xfer_len = 0;
++01624                         ep->dwc_ep.xfer_count = 0;
++01625                         ep->dwc_ep.sent_zlp = 0;
++01626                         ep->dwc_ep.total_len = buflen;
++01627 
++01628                         ep->dwc_ep.maxxfer = max_transfer;
++01629                         if (GET_CORE_IF(pcd)->dma_desc_enable) {
++01630                                         uint32_t out_max_xfer =
++01631                                             DDMA_MAX_TRANSFER_SIZE -
++01632                                             (DDMA_MAX_TRANSFER_SIZE % 4);
++01633                                 if (ep->dwc_ep.is_in) {
++01634                                         if (ep->dwc_ep.maxxfer >
++01635                                             DDMA_MAX_TRANSFER_SIZE) {
++01636                                                 ep->dwc_ep.maxxfer =
++01637                                                     DDMA_MAX_TRANSFER_SIZE;
++01638                                         }
++01639                                 } else {
++01640                                                 if (ep->dwc_ep.maxxfer >
++01641                                                     out_max_xfer) {
++01642                                                 ep->dwc_ep.maxxfer =
++01643                                                     out_max_xfer;
++01644                                         }
++01645                                 }
++01646                         }
++01647                         if (ep->dwc_ep.maxxfer < ep->dwc_ep.total_len) {
++01648                                 ep->dwc_ep.maxxfer -=
++01649                                             (ep->dwc_ep.maxxfer %
++01650                                              ep->dwc_ep.maxpacket);
++01651                         }
++01652 
++01653                         if (zero) {
++01654                                 if ((ep->dwc_ep.total_len %
++01655                                              ep->dwc_ep.maxpacket == 0)
++01656                                             && (ep->dwc_ep.total_len != 0)) {
++01657                                         ep->dwc_ep.sent_zlp = 1;
++01658                                 }
++01659                         }
++01660 #ifdef DWC_UTE_CFI
++01661                         }
++01662 #endif
++01663                         dwc_otg_ep_start_transfer(GET_CORE_IF(pcd),
++01664                                                   &ep->dwc_ep);
++01665                 }
++01666         }
++01667 
++01668         if ((req != 0) || prevented) {
++01669                 ++pcd->request_pending;
++01670                 DWC_CIRCLEQ_INSERT_TAIL(&ep->queue, req, queue_entry);
++01671                 if (ep->dwc_ep.is_in && ep->stopped
++01672                     && !(GET_CORE_IF(pcd)->dma_enable)) {
++01674                         diepmsk_data_t diepmsk = {.d32 = 0 };
++01675                         diepmsk.b.intktxfemp = 1;
++01676                         if (GET_CORE_IF(pcd)->multiproc_int_enable) {
++01677                                 dwc_modify_reg32(&GET_CORE_IF(pcd)->dev_if->
++01678                                                  dev_global_regs->
++01679                                                  diepeachintmsk[ep->dwc_ep.num],
++01680                                                  0, diepmsk.d32);
++01681                         } else {
++01682                                 dwc_modify_reg32(&GET_CORE_IF(pcd)->dev_if->
++01683                                                  dev_global_regs->diepmsk, 0,
++01684                                                  diepmsk.d32);
++01685                         }
++01686 
++01687                 }
++01688         }
++01689 
++01690         DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
++01691 
++01692         return 0;
++01693 }
++01694 int dwc_otg_pcd_ep_dequeue(dwc_otg_pcd_t * pcd, void *ep_handle,
++01695                            void *req_handle)
++01696 {
++01697         uint64_t flags;
++01698         dwc_otg_pcd_request_t *req;
++01699         dwc_otg_pcd_ep_t *ep;
++01700 
++01701         ep = get_ep_from_handle(pcd, ep_handle);
++01702         if (!ep->desc && ep->dwc_ep.num != 0) {
++01703                 DWC_WARN("bad argument\n");
++01704                 return -DWC_E_INVALID;
++01705         }
++01706 
++01707         DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
++01708 
++01709         /* make sure it's actually queued on this endpoint */
++01710         DWC_CIRCLEQ_FOREACH(req, &ep->queue, queue_entry) {
++01711                 if (req->priv == (void *)req_handle) {
++01712                         break;
++01713                 }
++01714         }
++01715 
++01716         if (req->priv != (void *)req_handle) {
++01717                 DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
++01718                 return -DWC_E_INVALID;
++01719         }
++01720 
++01721         if (!DWC_CIRCLEQ_EMPTY_ENTRY(req, queue_entry)) {
++01722                 dwc_otg_request_done(ep, req, -DWC_E_RESTART);
++01723         } else {
++01724                 req = 0;
++01725         }
++01726 
++01727         DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
++01728 
++01729         return req ? 0 : -DWC_E_SHUTDOWN;
++01730 
++01731 }
++01732 
++01733 int dwc_otg_pcd_ep_halt(dwc_otg_pcd_t * pcd, void *ep_handle, int value)
++01734 {
++01735         dwc_otg_pcd_ep_t *ep;
++01736         uint64_t flags;
++01737         int retval = 0;
++01738 
++01739         ep = get_ep_from_handle(pcd, ep_handle);
++01740 
++01741         if ((!ep->desc && ep != &pcd->ep0) ||
++01742             (ep->desc && (ep->desc->bmAttributes == UE_ISOCHRONOUS))) {
++01743                 DWC_WARN("%s, bad ep\n", __func__);
++01744                 return -DWC_E_INVALID;
++01745         }
++01746 
++01747         DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
++01748         if (!DWC_CIRCLEQ_EMPTY(&ep->queue)) {
++01749                 DWC_WARN("%d %s XFer In process\n", ep->dwc_ep.num,
++01750                          ep->dwc_ep.is_in ? "IN" : "OUT");
++01751                 retval = -DWC_E_AGAIN;
++01752         } else if (value == 0) {
++01753                 dwc_otg_ep_clear_stall(GET_CORE_IF(pcd), &ep->dwc_ep);
++01754         } else if (value == 1) {
++01755                 if (ep->dwc_ep.is_in == 1 && GET_CORE_IF(pcd)->dma_desc_enable) {
++01756                         dtxfsts_data_t txstatus;
++01757                         fifosize_data_t txfifosize;
++01758 
++01759                         txfifosize.d32 =
++01760                             dwc_read_reg32(&GET_CORE_IF(pcd)->core_global_regs->
++01761                                            dptxfsiz_dieptxf[ep->dwc_ep.
++01762                                                             tx_fifo_num]);
++01763                         txstatus.d32 =
++01764                             dwc_read_reg32(&GET_CORE_IF(pcd)->dev_if->
++01765                                            in_ep_regs[ep->dwc_ep.num]->dtxfsts);
++01766 
++01767                         if (txstatus.b.txfspcavail < txfifosize.b.depth) {
++01768                                 DWC_WARN("%s() Data In Tx Fifo\n", __func__);
++01769                                 retval = -DWC_E_AGAIN;
++01770                         } else {
++01771                                 if (ep->dwc_ep.num == 0) {
++01772                                         pcd->ep0state = EP0_STALL;
++01773                                 }
++01774 
++01775                                 ep->stopped = 1;
++01776                                 dwc_otg_ep_set_stall(GET_CORE_IF(pcd),
++01777                                                      &ep->dwc_ep);
++01778                         }
++01779                 } else {
++01780                         if (ep->dwc_ep.num == 0) {
++01781                                 pcd->ep0state = EP0_STALL;
++01782                         }
++01783 
++01784                         ep->stopped = 1;
++01785                         dwc_otg_ep_set_stall(GET_CORE_IF(pcd), &ep->dwc_ep);
++01786                 }
++01787         } else if (value == 2) {
++01788                 ep->dwc_ep.stall_clear_flag = 0;
++01789         } else if (value == 3) {
++01790                 ep->dwc_ep.stall_clear_flag = 1;
++01791         }
++01792 
++01793         DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
++01794 
++01795         return retval;
++01796 }
++01797 
++01801 void dwc_otg_pcd_rem_wkup_from_suspend(dwc_otg_pcd_t * pcd, int set)
++01802 {
++01803         dctl_data_t dctl = { 0 };
++01804         dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
++01805         dsts_data_t dsts;
++01806 
++01807         dsts.d32 = dwc_read_reg32(&core_if->dev_if->dev_global_regs->dsts);
++01808         if (!dsts.b.suspsts) {
++01809                 DWC_WARN("Remote wakeup while is not in suspend state\n");
++01810         }
++01811         /* Check if DEVICE_REMOTE_WAKEUP feature enabled */
++01812         if (pcd->remote_wakeup_enable) {
++01813                 if (set) {
++01814                         dctl.b.rmtwkupsig = 1;
++01815                         dwc_modify_reg32(&core_if->dev_if->dev_global_regs->
++01816                                          dctl, 0, dctl.d32);
++01817                         DWC_DEBUGPL(DBG_PCD, "Set Remote Wakeup\n");
++01818                         dwc_mdelay(2);
++01819                         dwc_modify_reg32(&core_if->dev_if->dev_global_regs->
++01820                                          dctl, dctl.d32, 0);
++01821                         DWC_DEBUGPL(DBG_PCD, "Clear Remote Wakeup\n");
++01822                 }
++01823         } else {
++01824                 DWC_DEBUGPL(DBG_PCD, "Remote Wakeup is disabled\n");
++01825         }
++01826 }
++01827 
++01828 #ifdef CONFIG_USB_DWC_OTG_LPM
++01829 
++01832 void dwc_otg_pcd_rem_wkup_from_sleep(dwc_otg_pcd_t * pcd, int set)
++01833 {
++01834         glpmcfg_data_t lpmcfg;
++01835         dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
++01836 
++01837         lpmcfg.d32 = dwc_read_reg32(&core_if->core_global_regs->glpmcfg);
++01838 
++01839         /* Check if we are in L1 state */
++01840         if (!lpmcfg.b.prt_sleep_sts) {
++01841                 DWC_DEBUGPL(DBG_PCD, "Device is not in sleep state\n");
++01842                 return;
++01843         }
++01844 
++01845         /* Check if host allows remote wakeup */
++01846         if (!lpmcfg.b.rem_wkup_en) {
++01847                 DWC_DEBUGPL(DBG_PCD, "Host does not allow remote wakeup\n");
++01848                 return;
++01849         }
++01850 
++01851         /* Check if Resume OK */
++01852         if (!lpmcfg.b.sleep_state_resumeok) {
++01853                 DWC_DEBUGPL(DBG_PCD, "Sleep state resume is not OK\n");
++01854                 return;
++01855         }
++01856 
++01857         lpmcfg.d32 = dwc_read_reg32(&core_if->core_global_regs->glpmcfg);
++01858         lpmcfg.b.en_utmi_sleep = 0;
++01859         lpmcfg.b.hird_thres &= (~(1 << 4));
++01860         dwc_write_reg32(&core_if->core_global_regs->glpmcfg, lpmcfg.d32);
++01861 
++01862         if (set) {
++01863                 dctl_data_t dctl = {.d32 = 0 };
++01864                 dctl.b.rmtwkupsig = 1;
++01865                 /* Set RmtWkUpSig bit to start remote wakup signaling.
++01866                  * Hardware will automatically clear this bit.
++01867                  */
++01868                 dwc_modify_reg32(&core_if->dev_if->dev_global_regs->dctl,
++01869                                  0, dctl.d32);
++01870                 DWC_DEBUGPL(DBG_PCD, "Set Remote Wakeup\n");
++01871         }
++01872 
++01873 }
++01874 #endif
++01875 
++01879 void dwc_otg_pcd_remote_wakeup(dwc_otg_pcd_t * pcd, int set)
++01880 {
++01881         dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
++01882         if (dwc_otg_is_device_mode(core_if)) {
++01883 #ifdef CONFIG_USB_DWC_OTG_LPM
++01884                 if (core_if->lx_state == DWC_OTG_L1) {
++01885                         dwc_otg_pcd_rem_wkup_from_sleep(pcd, set);
++01886                 } else {
++01887 #endif
++01888                         dwc_otg_pcd_rem_wkup_from_suspend(pcd, set);
++01889 #ifdef CONFIG_USB_DWC_OTG_LPM
++01890                 }
++01891 #endif
++01892         }
++01893         return;
++01894 }
++01895 
++01896 int dwc_otg_pcd_wakeup(dwc_otg_pcd_t * pcd)
++01897 {
++01898         dsts_data_t dsts;
++01899         gotgctl_data_t gotgctl;
++01900         uint64_t flags;
++01901 
++01902         DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
++01903 
++01904         /*
++01905          * This function starts the Protocol if no session is in progress. If
++01906          * a session is already in progress, but the device is suspended,
++01907          * remote wakeup signaling is started.
++01908          */
++01909 
++01910         /* Check if valid session */
++01911         gotgctl.d32 =
++01912             dwc_read_reg32(&(GET_CORE_IF(pcd)->core_global_regs->gotgctl));
++01913         if (gotgctl.b.bsesvld) {
++01914                 /* Check if suspend state */
++01915                 dsts.d32 =
++01916                     dwc_read_reg32(&
++01917                                    (GET_CORE_IF(pcd)->dev_if->dev_global_regs->
++01918                                     dsts));
++01919                 if (dsts.b.suspsts) {
++01920                         dwc_otg_pcd_remote_wakeup(pcd, 1);
++01921                 }
++01922         } else {
++01923                 dwc_otg_pcd_initiate_srp(pcd);
++01924         }
++01925 
++01926         DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
++01927         return 0;
++01928 
++01929 }
++01930 
++01937 void dwc_otg_pcd_start_srp_timer(dwc_otg_pcd_t * pcd)
++01938 {
++01939         GET_CORE_IF(pcd)->srp_timer_started = 1;
++01940         DWC_TIMER_SCHEDULE(pcd->srp_timer, 6000 /* 6 secs */ );
++01941 }
++01942 
++01943 void dwc_otg_pcd_initiate_srp(dwc_otg_pcd_t * pcd)
++01944 {
++01945         uint32_t *addr =
++01946             (uint32_t *) & (GET_CORE_IF(pcd)->core_global_regs->gotgctl);
++01947         gotgctl_data_t mem;
++01948         gotgctl_data_t val;
++01949 
++01950         val.d32 = dwc_read_reg32(addr);
++01951         if (val.b.sesreq) {
++01952                 DWC_ERROR("Session Request Already active!\n");
++01953                 return;
++01954         }
++01955 
++01956         DWC_INFO("Session Request Initated\n"); //NOTICE
++01957         mem.d32 = dwc_read_reg32(addr);
++01958         mem.b.sesreq = 1;
++01959         dwc_write_reg32(addr, mem.d32);
++01960 
++01961         /* Start the SRP timer */
++01962         dwc_otg_pcd_start_srp_timer(pcd);
++01963         return;
++01964 }
++01965 
++01966 int dwc_otg_pcd_get_frame_number(dwc_otg_pcd_t * pcd)
++01967 {
++01968         return dwc_otg_get_frame_number(GET_CORE_IF(pcd));
++01969 }
++01970 
++01971 int dwc_otg_pcd_is_lpm_enabled(dwc_otg_pcd_t * pcd)
++01972 {
++01973         return GET_CORE_IF(pcd)->core_params->lpm_enable;
++01974 }
++01975 
++01976 uint32_t get_b_hnp_enable(dwc_otg_pcd_t * pcd)
++01977 {
++01978         return pcd->b_hnp_enable;
++01979 }
++01980 
++01981 uint32_t get_a_hnp_support(dwc_otg_pcd_t * pcd)
++01982 {
++01983         return pcd->a_hnp_support;
++01984 }
++01985 
++01986 uint32_t get_a_alt_hnp_support(dwc_otg_pcd_t * pcd)
++01987 {
++01988         return pcd->a_alt_hnp_support;
++01989 }
++01990 
++01991 int dwc_otg_pcd_get_rmwkup_enable(dwc_otg_pcd_t * pcd)
++01992 {
++01993         return pcd->remote_wakeup_enable;
++01994 }
++01995 
++01996 #endif                          /* DWC_HOST_ONLY */
++
Generated on Tue May 5 02:22:48 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__pcd_8c.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__pcd_8c.html 2013-07-26 19:31:21.000000000 +0000 +@@ -0,0 +1,1343 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_pcd.c File Reference ++ ++ ++ ++ ++
++
++
++
++

dwc_otg_pcd.c File Reference

This file implements PCD Core. More... ++

++#include "dwc_otg_pcd.h"
++ ++

++Go to the source code of this file. ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++

Functions

++static dwc_otg_pcd_ep_t * get_ep_from_handle (dwc_otg_pcd_t *pcd, void *handle)
void dwc_otg_request_done (dwc_otg_pcd_ep_t *ep, dwc_otg_pcd_request_t *req, int32_t status)
 This function completes a request.
++void dwc_otg_request_nuke (dwc_otg_pcd_ep_t *ep)
 This function terminates all the requsts in the EP request queue.
void dwc_otg_pcd_start (dwc_otg_pcd_t *pcd, const struct dwc_otg_pcd_function_ops *fops)
 Call this to bind the function driver to the PCD Core.
static int32_t dwc_otg_pcd_start_cb (void *p)
 PCD Callback function for initializing the PCD when switching to device mode.
++uint8_t * cfiw_ep_alloc_buffer (dwc_otg_pcd_t *pcd, void *pep, dwc_dma_t *addr, size_t buflen, int flags)
 CFI-specific buffer allocation function for EP.
static int32_t dwc_otg_pcd_resume_cb (void *p)
 PCD Callback function for notifying the PCD when resuming from suspend.
static int32_t dwc_otg_pcd_suspend_cb (void *p)
 PCD Callback function for notifying the PCD device is suspended.
static int32_t dwc_otg_pcd_stop_cb (void *p)
 PCD Callback function for stopping the PCD when switching to Host mode.
++dwc_otg_dev_dma_desc_t * dwc_otg_ep_alloc_desc_chain (uint32_t *dma_desc_addr, uint32_t count)
 This function allocates a DMA Descriptor chain for the Endpoint buffer to be used for a transfer to/from the specified endpoint.
++void dwc_otg_ep_free_desc_chain (dwc_otg_dev_dma_desc_t *desc_addr, uint32_t dma_desc_addr, uint32_t count)
 This function frees a DMA Descriptor chain that was allocated by ep_alloc_desc.
void dwc_otg_iso_ep_start_ddma_transfer (dwc_otg_core_if_t *core_if, dwc_ep_t *dwc_ep)
 This function initializes a descriptor chain for Isochronous transfer.
void dwc_otg_iso_ep_start_buf_transfer (dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
 This function initializes a descriptor chain for Isochronous transfer.
static void dwc_otg_iso_ep_start_transfer (dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
 This function does the setup for a data transfer for an EP and starts the transfer.
void dwc_otg_iso_ep_stop_transfer (dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
 This function does the setup for a data transfer for an EP and starts the transfer.
int dwc_otg_pcd_iso_ep_start (dwc_otg_pcd_t *pcd, void *ep_handle, uint8_t *buf0, uint8_t *buf1, dwc_dma_t dma0, dwc_dma_t dma1, int sync_frame, int dp_frame, int data_per_frame, int start_frame, int buf_proc_intrvl, void *req_handle, int atomic_alloc)
 Start isochronous transfers on the endpoint referenced by ep_handle.
int dwc_otg_pcd_iso_ep_stop (dwc_otg_pcd_t *pcd, void *ep_handle, void *req_handle)
 Stop ISOC transfers on endpoint referenced by ep_handle.
void dwc_otg_iso_buffer_done (dwc_otg_pcd_t *pcd, dwc_otg_pcd_ep_t *ep, void *req_handle)
 This function is used for perodical data exchnage between PCD and gadget drivers.
int dwc_otg_pcd_get_iso_packet_count (dwc_otg_pcd_t *pcd, void *ep_handle, void *iso_req_handle)
 Get ISOC packet count.
void dwc_otg_pcd_get_iso_packet_params (dwc_otg_pcd_t *pcd, void *ep_handle, void *iso_req_handle, int packet, int *status, int *actual, int *offset)
 Get ISOC packet status.
++static void dwc_otg_pcd_init_ep (dwc_otg_pcd_t *pcd, dwc_otg_pcd_ep_t *pcd_ep, uint32_t is_in, uint32_t ep_num)
static void dwc_otg_pcd_reinit (dwc_otg_pcd_t *pcd)
 Initialise ep's.
static void srp_timeout (void *ptr)
 This function is called when the SRP timer expires.
++void start_next_request (dwc_otg_pcd_ep_t *ep)
 Tasklet.
++static void start_xfer_tasklet_func (void *data)
dwc_otg_pcd_t * dwc_otg_pcd_init (dwc_otg_core_if_t *core_if)
 Call this function to get pointer on dwc_otg_pcd_t, this pointer will be used for all PCD API functions.
void dwc_otg_pcd_remove (dwc_otg_pcd_t *pcd)
 Frees PCD allocated by dwc_otg_pcd_init.
++uint32_t dwc_otg_pcd_is_dualspeed (dwc_otg_pcd_t *pcd)
 This function returns whether device is dualspeed.
++uint32_t dwc_otg_pcd_is_otg (dwc_otg_pcd_t *pcd)
 This function returns whether device is otg.
++static uint32_t assign_tx_fifo (dwc_otg_core_if_t *core_if)
 This function assigns periodic Tx FIFO to an periodic EP in shared Tx FIFO mode.
++static uint32_t assign_perio_tx_fifo (dwc_otg_core_if_t *core_if)
 This function assigns periodic Tx FIFO to an periodic EP in shared Tx FIFO mode.
++static void release_perio_tx_fifo (dwc_otg_core_if_t *core_if, uint32_t fifo_num)
 This function releases periodic Tx FIFO in shared Tx FIFO mode.
++static void release_tx_fifo (dwc_otg_core_if_t *core_if, uint32_t fifo_num)
 This function releases periodic Tx FIFO in shared Tx FIFO mode.
int dwc_otg_pcd_ep_enable (dwc_otg_pcd_t *pcd, const uint8_t *ep_desc, void *usb_ep)
 Enables an endpoint for use.
int dwc_otg_pcd_ep_disable (dwc_otg_pcd_t *pcd, void *ep_handle)
 Disable the endpoint referenced by ep_handle.
int dwc_otg_pcd_ep_queue (dwc_otg_pcd_t *pcd, void *ep_handle, uint8_t *buf, dwc_dma_t dma_buf, uint32_t buflen, int zero, void *req_handle, int atomic_alloc)
 Queue a data transfer request on the endpoint referenced by ep_handle.
int dwc_otg_pcd_ep_dequeue (dwc_otg_pcd_t *pcd, void *ep_handle, void *req_handle)
 De-queue the specified data transfer that has not yet completed.
int dwc_otg_pcd_ep_halt (dwc_otg_pcd_t *pcd, void *ep_handle, int value)
 Halt (STALL) an endpoint or clear it.
++void dwc_otg_pcd_rem_wkup_from_suspend (dwc_otg_pcd_t *pcd, int set)
 This function initiates remote wakeup of the host from suspend state.
++void dwc_otg_pcd_remote_wakeup (dwc_otg_pcd_t *pcd, int set)
 Starts remote wakeup signaling.
int dwc_otg_pcd_wakeup (dwc_otg_pcd_t *pcd)
 This function starts the SRP Protocol if no session is in progress.
void dwc_otg_pcd_start_srp_timer (dwc_otg_pcd_t *pcd)
 Start the SRP timer to detect when the SRP does not complete within 6 seconds.
++void dwc_otg_pcd_initiate_srp (dwc_otg_pcd_t *pcd)
 Initiate SRP.
++int dwc_otg_pcd_get_frame_number (dwc_otg_pcd_t *pcd)
 This function returns current frame number.
++int dwc_otg_pcd_is_lpm_enabled (dwc_otg_pcd_t *pcd)
 This function returns 1 if LPM support is enabled, and 0 otherwise.
++uint32_t get_b_hnp_enable (dwc_otg_pcd_t *pcd)
 These functions allow to get hnp parameters.
++uint32_t get_a_hnp_support (dwc_otg_pcd_t *pcd)
++uint32_t get_a_alt_hnp_support (dwc_otg_pcd_t *pcd)
++int dwc_otg_pcd_get_rmwkup_enable (dwc_otg_pcd_t *pcd)
 This function returns 1 if remote wakeup is allowed and 0, otherwise.

Variables

static dwc_otg_cil_callbacks_t pcd_callbacks
 PCD Callback structure for handling mode switching.
++

Detailed Description

++This file implements PCD Core. ++

++All code in this file is portable and don't use any OS specific functions. PCD Core provides Interface, defined in <dwc_otg_pcd_if.h> header file, which can be used to implement OS specific PCD interface.

++An important function of the PCD is managing interrupts generated by the DWC_otg controller. The implementation of the DWC_otg device mode interrupt service routines is in dwc_otg_pcd_intr.c.

++

Todo:
Add Device Mode test modes (Test J mode, Test K mode, etc).

++Does it work when the request size is greater than DEPTSIZ transfer size

++ ++

++Definition in file dwc_otg_pcd.c.

Function Documentation

++ ++
++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_otg_request_done (dwc_otg_pcd_ep_t *  ep,
dwc_otg_pcd_request_t *  req,
int32_t  status 
)
++
++
++ ++

++This function completes a request. ++

++It call's the request call back. ++

++Definition at line 78 of file dwc_otg_pcd.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_otg_pcd_start (dwc_otg_pcd_t *  pcd,
const struct dwc_otg_pcd_function_ops *  fops 
)
++
++
++ ++

++Call this to bind the function driver to the PCD Core. ++

++

Parameters:
++ ++ ++ ++
pcd Pointer on dwc_otg_pcd_t returned by dwc_otg_pcd_init function.
fops The Function Driver Ops data structure containing pointers to all callbacks.
++
++ ++

++Definition at line 117 of file dwc_otg_pcd.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
static int32_t dwc_otg_pcd_start_cb (void *  p  )  [static]
++
++
++ ++

++PCD Callback function for initializing the PCD when switching to device mode. ++

++

Parameters:
++ ++ ++
p void pointer to the dwc_otg_pcd_t
++
++ ++

++Definition at line 129 of file dwc_otg_pcd.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
static int32_t dwc_otg_pcd_resume_cb (void *  p  )  [static]
++
++
++ ++

++PCD Callback function for notifying the PCD when resuming from suspend. ++

++

Parameters:
++ ++ ++
p void pointer to the dwc_otg_pcd_t
++
++ ++

++Definition at line 163 of file dwc_otg_pcd.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
static int32_t dwc_otg_pcd_suspend_cb (void *  p  )  [static]
++
++
++ ++

++PCD Callback function for notifying the PCD device is suspended. ++

++

Parameters:
++ ++ ++
p void pointer to the dwc_otg_pcd_t
++
++ ++

++Definition at line 187 of file dwc_otg_pcd.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
static int32_t dwc_otg_pcd_stop_cb (void *  p  )  [static]
++
++
++ ++

++PCD Callback function for stopping the PCD when switching to Host mode. ++

++

Parameters:
++ ++ ++
p void pointer to the dwc_otg_pcd_t
++
++ ++

++Definition at line 204 of file dwc_otg_pcd.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_otg_iso_ep_start_ddma_transfer (dwc_otg_core_if_t *  core_if,
dwc_ep_t *  dwc_ep 
)
++
++
++ ++

++This function initializes a descriptor chain for Isochronous transfer. ++

++

Parameters:
++ ++ ++ ++
core_if Programming view of DWC_otg controller.
dwc_ep The EP to start the transfer on.
++
++ ++

++Allocate descriptors for double buffering

++ISO OUT EP

++Buffer 0 descriptors setup

++Buffer 1 descriptors setup

++Write dma_ad into DOEPDMA register

++ISO IN EP

++Buffer 0 descriptors setup

++Buffer 1 descriptors setup

++Write dma_ad into diepdma register

++Enable endpoint, clear nak ++

++Definition at line 254 of file dwc_otg_pcd.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_otg_iso_ep_start_buf_transfer (dwc_otg_core_if_t *  core_if,
dwc_ep_t *  ep 
)
++
++
++ ++

++This function initializes a descriptor chain for Isochronous transfer. ++

++

Parameters:
++ ++ ++ ++
core_if Programming view of DWC_otg controller.
ep The EP to start the transfer on.
++
++ ++

++Enable endpoint, clear nak ++

++Definition at line 517 of file dwc_otg_pcd.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
static void dwc_otg_iso_ep_start_transfer (dwc_otg_core_if_t *  core_if,
dwc_ep_t *  ep 
) [static]
++
++
++ ++

++This function does the setup for a data transfer for an EP and starts the transfer. ++

++For an IN transfer, the packets will be loaded into the appropriate Tx FIFO in the ISR. For OUT transfers, the packets are unloaded from the Rx FIFO in the ISR. the ISR.

++

Parameters:
++ ++ ++ ++
core_if Programming view of DWC_otg controller.
ep The EP to start the transfer on.
++
++ ++

++Definition at line 598 of file dwc_otg_pcd.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_otg_iso_ep_stop_transfer (dwc_otg_core_if_t *  core_if,
dwc_ep_t *  ep 
)
++
++
++ ++

++This function does the setup for a data transfer for an EP and starts the transfer. ++

++For an IN transfer, the packets will be loaded into the appropriate Tx FIFO in the ISR. For OUT transfers, the packets are unloaded from the Rx FIFO in the ISR. the ISR.

++

Parameters:
++ ++ ++ ++
core_if Programming view of DWC_otg controller.
ep The EP to start the transfer on.
++
++ ++

++Definition at line 641 of file dwc_otg_pcd.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int dwc_otg_pcd_iso_ep_start (dwc_otg_pcd_t *  pcd,
void *  ep_handle,
uint8_t *  buf0,
uint8_t *  buf1,
dwc_dma_t  dma0,
dwc_dma_t  dma1,
int  sync_frame,
int  dp_frame,
int  data_per_frame,
int  start_frame,
int  buf_proc_intrvl,
void *  req_handle,
int  atomic_alloc 
)
++
++
++ ++

++Start isochronous transfers on the endpoint referenced by ep_handle. ++

++For isochronous transfers duble buffering is used. After processing each of buffers comlete callback will be called with status for each transaction.

++

Parameters:
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
pcd The PCD
ep_handle The handle of the endpoint
buf0 The virtual address of first data buffer
buf1 The virtual address of second data buffer
dma0 The DMA address of first data buffer
dma1 The DMA address of second data buffer
sync_frame Data pattern frame number
dp_frame Data size for pattern frame
data_per_frame Data size for regular frame
start_frame Frame number to start transfers, if -1 then start transfers ASAP.
buf_proc_intrvl Interval of ISOC Buffer processing
req_handle Handle of ISOC request
atomic_alloc Specefies whether to perform atomic allocation for internal data structures.
++
++Returns -DWC_E_NO_MEMORY if there is no enough memory. Returns -DWC_E_INVALID if incorrect arguments are passed to the function. Returns -DW_E_SHUTDOWN for any other error. Returns 0 on success ++

++

Todo:
    ++
  • pattern data support is to be implemented in the future
++
++ ++

++Definition at line 685 of file dwc_otg_pcd.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int dwc_otg_pcd_iso_ep_stop (dwc_otg_pcd_t *  pcd,
void *  ep_handle,
void *  req_handle 
)
++
++
++ ++

++Stop ISOC transfers on endpoint referenced by ep_handle. ++

++

Parameters:
++ ++ ++ ++ ++
pcd The PCD
ep_handle The handle of the endpoint
req_handle Handle of ISOC request
++
++Returns -DWC_E_INVALID if incorrect arguments are passed to the function Returns 0 on success ++

++Definition at line 794 of file dwc_otg_pcd.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_otg_iso_buffer_done (dwc_otg_pcd_t *  pcd,
dwc_otg_pcd_ep_t *  ep,
void *  req_handle 
)
++
++
++ ++

++This function is used for perodical data exchnage between PCD and gadget drivers. ++

++for Isochronous EPs

++

    ++
  • Every time a sync period completes this function is called to perform data exchange between PCD and gadget
++ ++

++Definition at line 830 of file dwc_otg_pcd.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int dwc_otg_pcd_get_iso_packet_count (dwc_otg_pcd_t *  pcd,
void *  ep_handle,
void *  iso_req_handle 
)
++
++
++ ++

++Get ISOC packet count. ++

++

Parameters:
++ ++ ++ ++ ++
pcd The PCD
ep_handle The handle of the endpoint
iso_req_handle 
++
++ ++

++Definition at line 850 of file dwc_otg_pcd.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_otg_pcd_get_iso_packet_params (dwc_otg_pcd_t *  pcd,
void *  ep_handle,
void *  iso_req_handle,
int  packet,
int *  status,
int *  actual,
int *  offset 
)
++
++
++ ++

++Get ISOC packet status. ++

++

Parameters:
++ ++ ++ ++ ++ ++ ++ ++ ++
pcd The PCD
ep_handle The handle of the endpoint
iso_req_handle Isochronoush request handle
packet Number of packet
status Out parameter for returning status
actual Out parameter for returning actual length
offset Out parameter for returning offset
++
++ ++

++Definition at line 862 of file dwc_otg_pcd.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
static void dwc_otg_pcd_reinit (dwc_otg_pcd_t *  pcd  )  [static]
++
++
++ ++

++Initialise ep's. ++

++ ++

++Initialize the EP0 structure.

++

Todo:
NGS: Add direction to EP, based on contents of HWCFG1. Need a copy of HWCFG1 in pcd structure? sprintf(";r
++

++

Todo:
NGS: Add direction to EP, based on contents of HWCFG1. Need a copy of HWCFG1 in pcd structure? sprintf(";r
++ ++

++Definition at line 911 of file dwc_otg_pcd.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
static void srp_timeout (void *  ptr  )  [static]
++
++
++ ++

++This function is called when the SRP timer expires. ++

++The SRP should complete within 6 seconds. ++

++Definition at line 970 of file dwc_otg_pcd.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
dwc_otg_pcd_t* dwc_otg_pcd_init (dwc_otg_core_if_t *  core_if  ) 
++
++
++ ++

++Call this function to get pointer on dwc_otg_pcd_t, this pointer will be used for all PCD API functions. ++

++

Parameters:
++ ++ ++
core_if The DWC_OTG Core
++
++ ++

++Definition at line 1056 of file dwc_otg_pcd.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_otg_pcd_remove (dwc_otg_pcd_t *  pcd  ) 
++
++
++ ++

++Frees PCD allocated by dwc_otg_pcd_init. ++

++

Parameters:
++ ++ ++
pcd The PCD
++
++ ++

++Definition at line 1215 of file dwc_otg_pcd.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int dwc_otg_pcd_ep_enable (dwc_otg_pcd_t *  pcd,
const uint8_t *  ep_desc,
void *  ep_handle 
)
++
++
++ ++

++Enables an endpoint for use. ++

++This function enables an endpoint in the PCD. The endpoint is described by the ep_desc which has the same format as a USB ep descriptor. The ep_handle parameter is used to refer to the endpoint from other API functions and in callbacks. Normally this should be called after a SET_CONFIGURATION/SET_INTERFACE to configure the core for that interface.

++Returns -DWC_E_INVALID if invalid parameters were passed. Returns -DWC_E_SHUTDOWN if any other error ocurred. Returns 0 on success.

++

Parameters:
++ ++ ++ ++ ++
pcd The PCD
ep_desc Endpoint descriptor
ep_handle Handle on endpoint, that will be used to identify endpoint.
++
++ ++

++Definition at line 1341 of file dwc_otg_pcd.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int dwc_otg_pcd_ep_disable (dwc_otg_pcd_t *  pcd,
void *  ep_handle 
)
++
++
++ ++

++Disable the endpoint referenced by ep_handle. ++

++Returns -DWC_E_INVALID if invalid parameters were passed. Returns -DWC_E_SHUTDOWN if any other error ocurred. Returns 0 on success. ++

++Definition at line 1449 of file dwc_otg_pcd.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int dwc_otg_pcd_ep_queue (dwc_otg_pcd_t *  pcd,
void *  ep_handle,
uint8_t *  buf,
dwc_dma_t  dma_buf,
uint32_t  buflen,
int  zero,
void *  req_handle,
int  atomic_alloc 
)
++
++
++ ++

++Queue a data transfer request on the endpoint referenced by ep_handle. ++

++After the transfer is completes, the complete callback will be called with the request status.

++

Parameters:
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
pcd The PCD
ep_handle The handle of the endpoint
buf The buffer for the data
dma_buf The DMA buffer for the data
buflen The length of the data transfer
zero Specifies whether to send zero length last packet.
req_handle Set this handle to any value to use to reference this request in the ep_dequeue function or from the complete callback
atomic_alloc If driver need to perform atomic allocations for internal data structures.
++
++Returns -DWC_E_INVALID if invalid parameters were passed. Returns -DWC_E_SHUTDOWN if any other error ocurred. Returns 0 on success. ++

++

Todo:
NGS Create a function for this.
++ ++

++Definition at line 1502 of file dwc_otg_pcd.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int dwc_otg_pcd_ep_dequeue (dwc_otg_pcd_t *  pcd,
void *  ep_handle,
void *  req_handle 
)
++
++
++ ++

++De-queue the specified data transfer that has not yet completed. ++

++Returns -DWC_E_INVALID if invalid parameters were passed. Returns -DWC_E_SHUTDOWN if any other error ocurred. Returns 0 on success. ++

++Definition at line 1694 of file dwc_otg_pcd.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int dwc_otg_pcd_ep_halt (dwc_otg_pcd_t *  pcd,
void *  ep_handle,
int  value 
)
++
++
++ ++

++Halt (STALL) an endpoint or clear it. ++

++Returns -DWC_E_INVALID if invalid parameters were passed. Returns -DWC_E_SHUTDOWN if any other error ocurred. Returns -DWC_E_AGAIN if the STALL cannot be sent and must be tried again later Returns 0 on success. ++

++Definition at line 1733 of file dwc_otg_pcd.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int dwc_otg_pcd_wakeup (dwc_otg_pcd_t *  pcd  ) 
++
++
++ ++

++This function starts the SRP Protocol if no session is in progress. ++

++If a session is already in progress, but the device is suspended, remote wakeup signaling is started. ++

++Definition at line 1896 of file dwc_otg_pcd.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_otg_pcd_start_srp_timer (dwc_otg_pcd_t *  pcd  ) 
++
++
++ ++

++Start the SRP timer to detect when the SRP does not complete within 6 seconds. ++

++

Parameters:
++ ++ ++
pcd the pcd structure.
++
++ ++

++Definition at line 1937 of file dwc_otg_pcd.c. ++

++

++

Variable Documentation

++ ++
++
++ ++ ++ ++ ++
dwc_otg_cil_callbacks_t pcd_callbacks [static]
++
++
++ ++

++Initial value:

 {
++        .start = dwc_otg_pcd_start_cb,
++        .stop = dwc_otg_pcd_stop_cb,
++        .suspend = dwc_otg_pcd_suspend_cb,
++        .resume_wakeup = dwc_otg_pcd_resume_cb,
++        .p = 0,                 
++}
++
PCD Callback structure for handling mode switching. ++

++ ++

++Definition at line 216 of file dwc_otg_pcd.c. ++

++

++

Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__pcd_8h-source.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__pcd_8h-source.html 2013-07-26 19:31:21.000000000 +0000 +@@ -0,0 +1,171 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_pcd.h Source File ++ ++ ++ ++ ++
++
++
++
++

dwc_otg_pcd.h

Go to the documentation of this file.
00001 /* ==========================================================================
++00002  * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_pcd.h $
++00003  * $Revision: #39 $
++00004  * $Date: 2008/12/16 $
++00005  * $Change: 1153731 $
++00006  *
++00007  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
++00008  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
++00009  * otherwise expressly agreed to in writing between Synopsys and you.
++00010  *
++00011  * The Software IS NOT an item of Licensed Software or Licensed Product under
++00012  * any End User Software License Agreement or Agreement for Licensed Product
++00013  * with Synopsys or any supplement thereto. You are permitted to use and
++00014  * redistribute this Software in source and binary forms, with or without
++00015  * modification, provided that redistributions of source code must retain this
++00016  * notice. You may not view, use, disclose, copy or distribute this file or
++00017  * any information contained herein except pursuant to this license grant from
++00018  * Synopsys. If you do not agree with this notice, including the disclaimer
++00019  * below, then you are not authorized to use the Software.
++00020  *
++00021  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
++00022  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++00023  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++00024  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
++00025  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++00026  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
++00027  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
++00028  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
++00029  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
++00030  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
++00031  * DAMAGE.
++00032  * ========================================================================== */
++00033 #ifndef DWC_HOST_ONLY
++00034 #if !defined(__DWC_PCD_H__)
++00035 #define __DWC_PCD_H__
++00036 
++00037 #include "usb.h"
++00038 #include "dwc_otg_cil.h"
++00039 #include "dwc_otg_pcd_if.h"
++00040 struct cfiobject;
++00041 
++00058 #define DDMA_MAX_TRANSFER_SIZE 65535
++00059 
++00061 #define MAX_DMA_DESC_CNT 64
++00062 
++00066 #define GET_CORE_IF( _pcd ) (_pcd->core_if)
++00067 
++00071 typedef enum ep0_state {
++00072         EP0_DISCONNECT,         /* no host */
++00073         EP0_IDLE,
++00074         EP0_IN_DATA_PHASE,
++00075         EP0_OUT_DATA_PHASE,
++00076         EP0_IN_STATUS_PHASE,
++00077         EP0_OUT_STATUS_PHASE,
++00078         EP0_STALL,
++00079 } ep0state_e;
++00080 
++00082 struct dwc_otg_pcd;
++00083 
++00087 typedef struct usb_iso_request dwc_otg_pcd_iso_request_t;
++00088 
++00092 typedef struct dwc_otg_pcd_request {
++00093         void *priv;
++00094         void *buf;
++00095         dwc_dma_t dma;
++00096         uint32_t length;
++00097         uint32_t actual;
++00098         unsigned sent_zlp:1;
++00099 
++00100          DWC_CIRCLEQ_ENTRY(dwc_otg_pcd_request) queue_entry;
++00101 } dwc_otg_pcd_request_t;
++00102 
++00103 DWC_CIRCLEQ_HEAD(req_list, dwc_otg_pcd_request);
++00104 
++00109 typedef struct dwc_otg_pcd_ep {
++00111         const usb_endpoint_descriptor_t *desc;
++00112 
++00114         struct req_list queue;
++00115         unsigned stopped:1;
++00116         unsigned disabling:1;
++00117         unsigned dma:1;
++00118         unsigned queue_sof:1;
++00119 
++00120 #ifdef DWC_EN_ISOC
++00121 
++00122         void *iso_req_handle;
++00123 #endif                          //_EN_ISOC_
++00124 
++00126         dwc_ep_t dwc_ep;
++00127 
++00129         struct dwc_otg_pcd *pcd;
++00130 
++00131         void *priv;
++00132 } dwc_otg_pcd_ep_t;
++00133 
++00137 struct dwc_otg_pcd {
++00138         const struct dwc_otg_pcd_function_ops *fops;
++00140         dwc_otg_core_if_t *core_if;
++00142         ep0state_e ep0state;
++00144         unsigned ep0_pending:1;
++00146         unsigned request_config:1;
++00148         unsigned remote_wakeup_enable:1;
++00150         unsigned b_hnp_enable:1;
++00152         unsigned a_hnp_support:1;
++00154         unsigned a_alt_hnp_support:1;
++00156         unsigned request_pending;
++00157 
++00162         union {
++00163                 usb_device_request_t req;
++00164                 uint32_t d32[2];
++00165         } *setup_pkt;
++00166 
++00167         dwc_dma_t setup_pkt_dma_handle;
++00168 
++00170         uint16_t *status_buf;
++00171         dwc_dma_t status_buf_dma_handle;
++00172 
++00174         dwc_otg_pcd_ep_t ep0;
++00175 
++00177         dwc_otg_pcd_ep_t in_ep[MAX_EPS_CHANNELS - 1];
++00179         dwc_otg_pcd_ep_t out_ep[MAX_EPS_CHANNELS - 1];
++00181 //        unsigned      num_eps : 4;
++00182         dwc_spinlock_t *lock;
++00185         dwc_timer_t *srp_timer;
++00186 
++00190         dwc_tasklet_t *test_mode_tasklet;
++00191 
++00193         dwc_tasklet_t *start_xfer_tasklet;
++00194 
++00196         unsigned test_mode;
++00200 #ifdef DWC_UTE_CFI
++00201         struct cfiobject *cfi;
++00202 #endif
++00203 
++00204 };
++00205 
++00206 //FIXME this functions should be static, and this prototypes should be removed
++00207 extern void dwc_otg_request_nuke(dwc_otg_pcd_ep_t * ep);
++00208 extern void dwc_otg_request_done(dwc_otg_pcd_ep_t * ep,
++00209                                  dwc_otg_pcd_request_t * req, int32_t status);
++00210 
++00211 void dwc_otg_iso_buffer_done(dwc_otg_pcd_t * pcd, dwc_otg_pcd_ep_t * ep,
++00212                              void *req_handle);
++00213 
++00214 extern void do_test_mode(void *data);
++00215 #endif
++00216 #endif                          /* DWC_HOST_ONLY */
++
Generated on Tue May 5 02:22:48 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__pcd_8h.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__pcd_8h.html 2013-07-26 19:31:21.000000000 +0000 +@@ -0,0 +1,254 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_pcd.h File Reference ++ ++ ++ ++ ++
++
++
++
++

dwc_otg_pcd.h File Reference

This file contains the structures, constants, and interfaces for the Perpherial Contoller Driver (PCD). More... ++

++#include "usb.h"
++#include "dwc_otg_cil.h"
++#include "dwc_otg_pcd_if.h"
++ ++

++Go to the source code of this file. ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++

Data Structures

struct  dwc_otg_pcd_request
 DWC_otg request structure. More...
struct  dwc_otg_pcd_ep
 PCD EP structure. More...
struct  dwc_otg_pcd
 DWC_otg PCD Structure. More...

Defines

++#define __DWC_PCD_H__
++#define DDMA_MAX_TRANSFER_SIZE   65535
 Max Transfer size for any EP.
++#define MAX_DMA_DESC_CNT   64
 Max DMA Descriptor count for any EP.
++#define GET_CORE_IF(_pcd)   (_pcd->core_if)
 Get the pointer to the core_if from the pcd pointer.

Typedefs

++typedef enum ep0_state ep0state_e
 States of EP0.
++typedef usb_iso_request dwc_otg_pcd_iso_request_t
 DWC_otg iso request structure.
typedef dwc_otg_pcd_request dwc_otg_pcd_request_t
 DWC_otg request structure.
typedef dwc_otg_pcd_ep dwc_otg_pcd_ep_t
 PCD EP structure.

Enumerations

enum  ep0_state {
++  EP0_DISCONNECT, ++EP0_IDLE, ++EP0_IN_DATA_PHASE, ++EP0_OUT_DATA_PHASE, ++
++  EP0_IN_STATUS_PHASE, ++EP0_OUT_STATUS_PHASE, ++EP0_STALL ++
++ }
 States of EP0.

Functions

++ DWC_CIRCLEQ_HEAD (req_list, dwc_otg_pcd_request)
++void dwc_otg_request_nuke (dwc_otg_pcd_ep_t *ep)
 This function terminates all the requsts in the EP request queue.
void dwc_otg_request_done (dwc_otg_pcd_ep_t *ep, dwc_otg_pcd_request_t *req, int32_t status)
 This function completes a request.
void dwc_otg_iso_buffer_done (dwc_otg_pcd_t *pcd, dwc_otg_pcd_ep_t *ep, void *req_handle)
 This function is used for perodical data exchnage between PCD and gadget drivers.
void do_test_mode (void *data)
 This function is called when the SET_FEATURE TEST_MODE Setup packet is sent from the host.
++

Detailed Description

++This file contains the structures, constants, and interfaces for the Perpherial Contoller Driver (PCD). ++

++The Peripheral Controller Driver (PCD) for Linux will implement the Gadget API, so that the existing Gadget drivers can be used. For the Mass Storage Function driver the File-backed USB Storage Gadget (FBS) driver will be used. The FBS driver supports the Control-Bulk (CB), Control-Bulk-Interrupt (CBI), and Bulk-Only transports. ++

++Definition in file dwc_otg_pcd.h.

Typedef Documentation

++ ++
++
++ ++ ++ ++ ++
typedef struct dwc_otg_pcd_request dwc_otg_pcd_request_t
++
++
++ ++

++DWC_otg request structure. ++

++This structure is a list of requests. ++

++

++ ++

++
++ ++ ++ ++ ++
typedef struct dwc_otg_pcd_ep dwc_otg_pcd_ep_t
++
++
++ ++

++PCD EP structure. ++

++This structure describes an EP, there is an array of EPs in the PCD structure. ++

++

++

Function Documentation

++ ++
++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_otg_request_done (dwc_otg_pcd_ep_t *  ep,
dwc_otg_pcd_request_t *  req,
int32_t  status 
)
++
++
++ ++

++This function completes a request. ++

++It call's the request call back. ++

++Definition at line 78 of file dwc_otg_pcd.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_otg_iso_buffer_done (dwc_otg_pcd_t *  pcd,
dwc_otg_pcd_ep_t *  ep,
void *  req_handle 
)
++
++
++ ++

++This function is used for perodical data exchnage between PCD and gadget drivers. ++

++for Isochronous EPs

++

    ++
  • Every time a sync period completes this function is called to perform data exchange between PCD and gadget
++ ++

++Definition at line 830 of file dwc_otg_pcd.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void do_test_mode (void *  data  ) 
++
++
++ ++

++This function is called when the SET_FEATURE TEST_MODE Setup packet is sent from the host. ++

++The Device Control register is written with the Test Mode bits set to the specified Test Mode. This is done as a tasklet so that the "Status" phase of the control transfer completes before transmitting the TEST packets.

++

Todo:
This has not been tested since the tasklet struct was put into the PCD struct!
++ ++

++Definition at line 1284 of file dwc_otg_pcd_intr.c. ++

++

++

Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__pcd__if_8h-source.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__pcd__if_8h-source.html 2013-07-26 19:31:21.000000000 +0000 +@@ -0,0 +1,174 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_pcd_if.h Source File ++ ++ ++ ++ ++
++
++
++
++

dwc_otg_pcd_if.h

Go to the documentation of this file.
00001 /* ==========================================================================
++00002  * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_pcd_if.h $
++00003  * $Revision: #6 $
++00004  * $Date: 2009/04/03 $
++00005  * $Change: 1225059 $
++00006  *
++00007  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
++00008  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
++00009  * otherwise expressly agreed to in writing between Synopsys and you.
++00010  *
++00011  * The Software IS NOT an item of Licensed Software or Licensed Product under
++00012  * any End User Software License Agreement or Agreement for Licensed Product
++00013  * with Synopsys or any supplement thereto. You are permitted to use and
++00014  * redistribute this Software in source and binary forms, with or without
++00015  * modification, provided that redistributions of source code must retain this
++00016  * notice. You may not view, use, disclose, copy or distribute this file or
++00017  * any information contained herein except pursuant to this license grant from
++00018  * Synopsys. If you do not agree with this notice, including the disclaimer
++00019  * below, then you are not authorized to use the Software.
++00020  *
++00021  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
++00022  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++00023  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++00024  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
++00025  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++00026  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
++00027  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
++00028  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
++00029  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
++00030  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
++00031  * DAMAGE.
++00032  * ========================================================================== */
++00033 #ifndef DWC_HOST_ONLY
++00034 
++00035 #if !defined(__DWC_PCD_IF_H__)
++00036 #define __DWC_PCD_IF_H__
++00037 
++00038 #include "dwc_os.h"
++00039 #include "dwc_otg_core_if.h"
++00040 
++00045 struct dwc_otg_pcd;
++00046 typedef struct dwc_otg_pcd dwc_otg_pcd_t;
++00047 
++00049 #define MAX_EP0_SIZE    64
++00050 
++00051 #define MAX_PACKET_SIZE 1024
++00052 
++00061 typedef int (*dwc_completion_cb_t) (dwc_otg_pcd_t * pcd, void *ep_handle,
++00062                                     void *req_handle, int32_t status,
++00063                                     uint32_t actual);
++00071 typedef int (*dwc_isoc_completion_cb_t) (dwc_otg_pcd_t * pcd, void *ep_handle,
++00072                                          void *req_handle, int proc_buf_num);
++00081 typedef int (*dwc_setup_cb_t) (dwc_otg_pcd_t * pcd, uint8_t * bytes);
++00086 typedef int (*dwc_disconnect_cb_t) (dwc_otg_pcd_t * pcd);
++00088 typedef int (*dwc_connect_cb_t) (dwc_otg_pcd_t * pcd, int speed);
++00090 typedef int (*dwc_suspend_cb_t) (dwc_otg_pcd_t * pcd);
++00093 typedef int (*dwc_sleep_cb_t) (dwc_otg_pcd_t * pcd);
++00096 typedef int (*dwc_resume_cb_t) (dwc_otg_pcd_t * pcd);
++00100 typedef int (*dwc_hnp_params_changed_cb_t) (dwc_otg_pcd_t * pcd);
++00102 typedef int (*dwc_reset_cb_t) (dwc_otg_pcd_t * pcd);
++00103 
++00104 typedef int (*cfi_setup_cb_t) (dwc_otg_pcd_t * pcd, void *ctrl_req_bytes);
++00105 
++00107 struct dwc_otg_pcd_function_ops {
++00108         dwc_connect_cb_t connect;
++00109         dwc_disconnect_cb_t disconnect;
++00110         dwc_setup_cb_t setup;
++00111         dwc_completion_cb_t complete;
++00112         dwc_isoc_completion_cb_t isoc_complete;
++00113         dwc_suspend_cb_t suspend;
++00114         dwc_sleep_cb_t sleep;
++00115         dwc_resume_cb_t resume;
++00116         dwc_reset_cb_t reset;
++00117         dwc_hnp_params_changed_cb_t hnp_changed;
++00118         cfi_setup_cb_t cfi_setup;
++00119 };
++00130 extern dwc_otg_pcd_t *dwc_otg_pcd_init(dwc_otg_core_if_t * core_if);
++00131 
++00136 extern void dwc_otg_pcd_remove(dwc_otg_pcd_t * pcd);
++00137 
++00143 extern void dwc_otg_pcd_start(dwc_otg_pcd_t * pcd,
++00144                               const struct dwc_otg_pcd_function_ops *fops);
++00145 
++00161 extern int dwc_otg_pcd_ep_enable(dwc_otg_pcd_t * pcd,
++00162                                  const uint8_t * ep_desc, void *ep_handle);
++00163 
++00169 extern int dwc_otg_pcd_ep_disable(dwc_otg_pcd_t * pcd, void *ep_handle);
++00170 
++00189 extern int dwc_otg_pcd_ep_queue(dwc_otg_pcd_t * pcd, void *ep_handle,
++00190                                 uint8_t * buf, dwc_dma_t dma_buf,
++00191                                 uint32_t buflen, int zero, void *req_handle,
++00192                                 int atomic_alloc);
++00193 
++00199 extern int dwc_otg_pcd_ep_dequeue(dwc_otg_pcd_t * pcd, void *ep_handle,
++00200                                   void *req_handle);
++00201 
++00208 extern int dwc_otg_pcd_ep_halt(dwc_otg_pcd_t * pcd, void *ep_handle, int value);
++00209 
++00211 extern int32_t dwc_otg_pcd_handle_intr(dwc_otg_pcd_t * pcd);
++00212 
++00214 extern int dwc_otg_pcd_get_frame_number(dwc_otg_pcd_t * pcd);
++00215 
++00242 extern int dwc_otg_pcd_iso_ep_start(dwc_otg_pcd_t * pcd, void *ep_handle,
++00243                                     uint8_t * buf0, uint8_t * buf1,
++00244                                     dwc_dma_t dma0, dwc_dma_t dma1,
++00245                                     int sync_frame, int dp_frame,
++00246                                     int data_per_frame, int start_frame,
++00247                                     int buf_proc_intrvl, void *req_handle,
++00248                                     int atomic_alloc);
++00249 
++00259 int dwc_otg_pcd_iso_ep_stop(dwc_otg_pcd_t * pcd, void *ep_handle,
++00260                             void *req_handle);
++00261 
++00273 extern void dwc_otg_pcd_get_iso_packet_params(dwc_otg_pcd_t * pcd,
++00274                                               void *ep_handle,
++00275                                               void *iso_req_handle, int packet,
++00276                                               int *status, int *actual,
++00277                                               int *offset);
++00278 
++00285 extern int dwc_otg_pcd_get_iso_packet_count(dwc_otg_pcd_t * pcd,
++00286                                             void *ep_handle,
++00287                                             void *iso_req_handle);
++00288 
++00293 extern int dwc_otg_pcd_wakeup(dwc_otg_pcd_t * pcd);
++00294 
++00296 extern int dwc_otg_pcd_is_lpm_enabled(dwc_otg_pcd_t * pcd);
++00297 
++00299 extern int dwc_otg_pcd_get_rmwkup_enable(dwc_otg_pcd_t * pcd);
++00300 
++00302 extern void dwc_otg_pcd_initiate_srp(dwc_otg_pcd_t * pcd);
++00303 
++00305 extern void dwc_otg_pcd_remote_wakeup(dwc_otg_pcd_t * pcd, int set);
++00306 
++00308 extern uint32_t dwc_otg_pcd_is_dualspeed(dwc_otg_pcd_t * pcd);
++00309 
++00311 extern uint32_t dwc_otg_pcd_is_otg(dwc_otg_pcd_t * pcd);
++00312 
++00314 extern uint32_t get_b_hnp_enable(dwc_otg_pcd_t * pcd);
++00315 extern uint32_t get_a_hnp_support(dwc_otg_pcd_t * pcd);
++00316 extern uint32_t get_a_alt_hnp_support(dwc_otg_pcd_t * pcd);
++00317 
++00320 extern uint8_t *cfiw_ep_alloc_buffer(dwc_otg_pcd_t * pcd, void *pep,
++00321                                      dwc_dma_t * addr, size_t buflen,
++00322                                      int flags);
++00323 
++00324 /******************************************************************************/
++00325 
++00328 #endif                          /* __DWC_PCD_IF_H__ */
++00329 
++00330 #endif                          /* DWC_HOST_ONLY */
++
Generated on Tue May 5 02:22:48 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__pcd__if_8h.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__pcd__if_8h.html 2013-07-26 19:31:21.000000000 +0000 +@@ -0,0 +1,976 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_pcd_if.h File Reference ++ ++ ++ ++ ++
++
++
++
++

dwc_otg_pcd_if.h File Reference

This file defines DWC_OTG PCD Core API. More... ++

++#include "dwc_os.h"
++#include "dwc_otg_core_if.h"
++ ++

++Go to the source code of this file. ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++

Data Structures

struct  dwc_otg_pcd_function_ops
 Function Driver Ops Data Structure. More...

Function Driver Callbacks

typedef int(*) dwc_completion_cb_t (dwc_otg_pcd_t *pcd, void *ep_handle, void *req_handle, int32_t status, uint32_t actual)
 This function will be called whenever a previously queued request has completed.
typedef int(*) dwc_isoc_completion_cb_t (dwc_otg_pcd_t *pcd, void *ep_handle, void *req_handle, int proc_buf_num)
 This function will be called whenever a previousle queued ISOC request has completed.
typedef int(*) dwc_setup_cb_t (dwc_otg_pcd_t *pcd, uint8_t *bytes)
 This function should handle any SETUP request that cannot be handled by the PCD Core.
typedef int(*) dwc_disconnect_cb_t (dwc_otg_pcd_t *pcd)
 This is called whenever the device has been disconnected.
++typedef int(*) dwc_connect_cb_t (dwc_otg_pcd_t *pcd, int speed)
 This function is called when device has been connected.
++typedef int(*) dwc_suspend_cb_t (dwc_otg_pcd_t *pcd)
 This function is called when device has been suspended.
typedef int(*) dwc_sleep_cb_t (dwc_otg_pcd_t *pcd)
 This function is called when device has received LPM tokens, i.e.
++typedef int(*) dwc_resume_cb_t (dwc_otg_pcd_t *pcd)
 This function is called when device has been resumed from suspend(L2) or L1 sleep state.
typedef int(*) dwc_hnp_params_changed_cb_t (dwc_otg_pcd_t *pcd)
 This function is called whenever hnp params has been changed.
++typedef int(*) dwc_reset_cb_t (dwc_otg_pcd_t *pcd)
 This function is called whenever USB RESET is detected.
++typedef int(*) cfi_setup_cb_t (dwc_otg_pcd_t *pcd, void *ctrl_req_bytes)

Function Driver Functions

dwc_otg_pcd_t * dwc_otg_pcd_init (dwc_otg_core_if_t *core_if)
 Call this function to get pointer on dwc_otg_pcd_t, this pointer will be used for all PCD API functions.
void dwc_otg_pcd_remove (dwc_otg_pcd_t *pcd)
 Frees PCD allocated by dwc_otg_pcd_init.
void dwc_otg_pcd_start (dwc_otg_pcd_t *pcd, const struct dwc_otg_pcd_function_ops *fops)
 Call this to bind the function driver to the PCD Core.
int dwc_otg_pcd_ep_enable (dwc_otg_pcd_t *pcd, const uint8_t *ep_desc, void *ep_handle)
 Enables an endpoint for use.
int dwc_otg_pcd_ep_disable (dwc_otg_pcd_t *pcd, void *ep_handle)
 Disable the endpoint referenced by ep_handle.
int dwc_otg_pcd_ep_queue (dwc_otg_pcd_t *pcd, void *ep_handle, uint8_t *buf, dwc_dma_t dma_buf, uint32_t buflen, int zero, void *req_handle, int atomic_alloc)
 Queue a data transfer request on the endpoint referenced by ep_handle.
int dwc_otg_pcd_ep_dequeue (dwc_otg_pcd_t *pcd, void *ep_handle, void *req_handle)
 De-queue the specified data transfer that has not yet completed.
int dwc_otg_pcd_ep_halt (dwc_otg_pcd_t *pcd, void *ep_handle, int value)
 Halt (STALL) an endpoint or clear it.
int32_t dwc_otg_pcd_handle_intr (dwc_otg_pcd_t *pcd)
 This function should be called on every hardware interrupt.
++int dwc_otg_pcd_get_frame_number (dwc_otg_pcd_t *pcd)
 This function returns current frame number.
int dwc_otg_pcd_iso_ep_start (dwc_otg_pcd_t *pcd, void *ep_handle, uint8_t *buf0, uint8_t *buf1, dwc_dma_t dma0, dwc_dma_t dma1, int sync_frame, int dp_frame, int data_per_frame, int start_frame, int buf_proc_intrvl, void *req_handle, int atomic_alloc)
 Start isochronous transfers on the endpoint referenced by ep_handle.
int dwc_otg_pcd_iso_ep_stop (dwc_otg_pcd_t *pcd, void *ep_handle, void *req_handle)
 Stop ISOC transfers on endpoint referenced by ep_handle.
void dwc_otg_pcd_get_iso_packet_params (dwc_otg_pcd_t *pcd, void *ep_handle, void *iso_req_handle, int packet, int *status, int *actual, int *offset)
 Get ISOC packet status.
int dwc_otg_pcd_get_iso_packet_count (dwc_otg_pcd_t *pcd, void *ep_handle, void *iso_req_handle)
 Get ISOC packet count.
int dwc_otg_pcd_wakeup (dwc_otg_pcd_t *pcd)
 This function starts the SRP Protocol if no session is in progress.
++int dwc_otg_pcd_is_lpm_enabled (dwc_otg_pcd_t *pcd)
 This function returns 1 if LPM support is enabled, and 0 otherwise.
++int dwc_otg_pcd_get_rmwkup_enable (dwc_otg_pcd_t *pcd)
 This function returns 1 if remote wakeup is allowed and 0, otherwise.
++void dwc_otg_pcd_initiate_srp (dwc_otg_pcd_t *pcd)
 Initiate SRP.
++void dwc_otg_pcd_remote_wakeup (dwc_otg_pcd_t *pcd, int set)
 Starts remote wakeup signaling.
++uint32_t dwc_otg_pcd_is_dualspeed (dwc_otg_pcd_t *pcd)
 This function returns whether device is dualspeed.
++uint32_t dwc_otg_pcd_is_otg (dwc_otg_pcd_t *pcd)
 This function returns whether device is otg.
++uint32_t get_b_hnp_enable (dwc_otg_pcd_t *pcd)
 These functions allow to get hnp parameters.
++uint32_t get_a_hnp_support (dwc_otg_pcd_t *pcd)
++uint32_t get_a_alt_hnp_support (dwc_otg_pcd_t *pcd)
++uint8_t * cfiw_ep_alloc_buffer (dwc_otg_pcd_t *pcd, void *pep, dwc_dma_t *addr, size_t buflen, int flags)
 Allocate a cfi buffer.

Defines

++#define __DWC_PCD_IF_H__
++#define MAX_EP0_SIZE   64
 Maxpacket size for EP0.
++#define MAX_PACKET_SIZE   1024
 Maxpacket size for any EP.

Typedefs

++typedef dwc_otg_pcd dwc_otg_pcd_t
++

Detailed Description

++This file defines DWC_OTG PCD Core API. ++

++ ++

++Definition in file dwc_otg_pcd_if.h.

Typedef Documentation

++ ++
++
++ ++ ++ ++ ++
typedef int(*) dwc_completion_cb_t(dwc_otg_pcd_t *pcd, void *ep_handle, void *req_handle, int32_t status, uint32_t actual)
++
++
++ ++

++This function will be called whenever a previously queued request has completed. ++

++The status value will be set to -DWC_E_SHUTDOWN to indicated a failed or aborted transfer, or -DWC_E_RESTART to indicate the device was reset, or -DWC_E_TIMEOUT to indicate it timed out, or -DWC_E_INVALID to indicate invalid parameters. ++

++Definition at line 61 of file dwc_otg_pcd_if.h. ++

++

++ ++

++
++ ++ ++ ++ ++
typedef int(*) dwc_isoc_completion_cb_t(dwc_otg_pcd_t *pcd, void *ep_handle, void *req_handle, int proc_buf_num)
++
++
++ ++

++This function will be called whenever a previousle queued ISOC request has completed. ++

++Count of ISOC packets could be read using dwc_otg_pcd_get_iso_packet_count function. The status of each ISOC packet could be read using dwc_otg_pcd_get_iso_packet_* functions. ++

++Definition at line 71 of file dwc_otg_pcd_if.h. ++

++

++ ++

++
++ ++ ++ ++ ++
typedef int(*) dwc_setup_cb_t(dwc_otg_pcd_t *pcd, uint8_t *bytes)
++
++
++ ++

++This function should handle any SETUP request that cannot be handled by the PCD Core. ++

++This includes most GET_DESCRIPTORs, SET_CONFIGS, Any class-specific requests, etc. The function must non-blocking.

++Returns 0 on success. Returns -DWC_E_NOT_SUPPORTED if the request is not supported. Returns -DWC_E_INVALID if the setup request had invalid parameters or bytes. Returns -DWC_E_SHUTDOWN on any other error. ++

++Definition at line 81 of file dwc_otg_pcd_if.h. ++

++

++ ++

++
++ ++ ++ ++ ++
typedef int(*) dwc_disconnect_cb_t(dwc_otg_pcd_t *pcd)
++
++
++ ++

++This is called whenever the device has been disconnected. ++

++The function driver should take appropriate action to clean up all pending requests in the PCD Core, remove all endpoints (except ep0), and initialize back to reset state. ++

++Definition at line 86 of file dwc_otg_pcd_if.h. ++

++

++ ++

++
++ ++ ++ ++ ++
typedef int(*) dwc_sleep_cb_t(dwc_otg_pcd_t *pcd)
++
++
++ ++

++This function is called when device has received LPM tokens, i.e. ++

++device has been sent to sleep state. ++

++Definition at line 93 of file dwc_otg_pcd_if.h. ++

++

++ ++

++
++ ++ ++ ++ ++
typedef int(*) dwc_hnp_params_changed_cb_t(dwc_otg_pcd_t *pcd)
++
++
++ ++

++This function is called whenever hnp params has been changed. ++

++User can call get_b_hnp_enable, get_a_hnp_support, get_a_alt_hnp_support functions to get hnp parameters. ++

++Definition at line 100 of file dwc_otg_pcd_if.h. ++

++

++

Function Documentation

++ ++
++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
dwc_otg_pcd_t* dwc_otg_pcd_init (dwc_otg_core_if_t *  core_if  ) 
++
++
++ ++

++Call this function to get pointer on dwc_otg_pcd_t, this pointer will be used for all PCD API functions. ++

++

Parameters:
++ ++ ++
core_if The DWC_OTG Core
++
++ ++

++Definition at line 1056 of file dwc_otg_pcd.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_otg_pcd_remove (dwc_otg_pcd_t *  pcd  ) 
++
++
++ ++

++Frees PCD allocated by dwc_otg_pcd_init. ++

++

Parameters:
++ ++ ++
pcd The PCD
++
++ ++

++Definition at line 1215 of file dwc_otg_pcd.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_otg_pcd_start (dwc_otg_pcd_t *  pcd,
const struct dwc_otg_pcd_function_ops *  fops 
)
++
++
++ ++

++Call this to bind the function driver to the PCD Core. ++

++

Parameters:
++ ++ ++ ++
pcd Pointer on dwc_otg_pcd_t returned by dwc_otg_pcd_init function.
fops The Function Driver Ops data structure containing pointers to all callbacks.
++
++ ++

++Definition at line 117 of file dwc_otg_pcd.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int dwc_otg_pcd_ep_enable (dwc_otg_pcd_t *  pcd,
const uint8_t *  ep_desc,
void *  ep_handle 
)
++
++
++ ++

++Enables an endpoint for use. ++

++This function enables an endpoint in the PCD. The endpoint is described by the ep_desc which has the same format as a USB ep descriptor. The ep_handle parameter is used to refer to the endpoint from other API functions and in callbacks. Normally this should be called after a SET_CONFIGURATION/SET_INTERFACE to configure the core for that interface.

++Returns -DWC_E_INVALID if invalid parameters were passed. Returns -DWC_E_SHUTDOWN if any other error ocurred. Returns 0 on success.

++

Parameters:
++ ++ ++ ++ ++
pcd The PCD
ep_desc Endpoint descriptor
ep_handle Handle on endpoint, that will be used to identify endpoint.
++
++ ++

++Definition at line 1341 of file dwc_otg_pcd.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int dwc_otg_pcd_ep_disable (dwc_otg_pcd_t *  pcd,
void *  ep_handle 
)
++
++
++ ++

++Disable the endpoint referenced by ep_handle. ++

++Returns -DWC_E_INVALID if invalid parameters were passed. Returns -DWC_E_SHUTDOWN if any other error ocurred. Returns 0 on success. ++

++Definition at line 1449 of file dwc_otg_pcd.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int dwc_otg_pcd_ep_queue (dwc_otg_pcd_t *  pcd,
void *  ep_handle,
uint8_t *  buf,
dwc_dma_t  dma_buf,
uint32_t  buflen,
int  zero,
void *  req_handle,
int  atomic_alloc 
)
++
++
++ ++

++Queue a data transfer request on the endpoint referenced by ep_handle. ++

++After the transfer is completes, the complete callback will be called with the request status.

++

Parameters:
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
pcd The PCD
ep_handle The handle of the endpoint
buf The buffer for the data
dma_buf The DMA buffer for the data
buflen The length of the data transfer
zero Specifies whether to send zero length last packet.
req_handle Set this handle to any value to use to reference this request in the ep_dequeue function or from the complete callback
atomic_alloc If driver need to perform atomic allocations for internal data structures.
++
++Returns -DWC_E_INVALID if invalid parameters were passed. Returns -DWC_E_SHUTDOWN if any other error ocurred. Returns 0 on success. ++

++

Todo:
NGS Create a function for this.
++ ++

++Definition at line 1502 of file dwc_otg_pcd.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int dwc_otg_pcd_ep_dequeue (dwc_otg_pcd_t *  pcd,
void *  ep_handle,
void *  req_handle 
)
++
++
++ ++

++De-queue the specified data transfer that has not yet completed. ++

++Returns -DWC_E_INVALID if invalid parameters were passed. Returns -DWC_E_SHUTDOWN if any other error ocurred. Returns 0 on success. ++

++Definition at line 1694 of file dwc_otg_pcd.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int dwc_otg_pcd_ep_halt (dwc_otg_pcd_t *  pcd,
void *  ep_handle,
int  value 
)
++
++
++ ++

++Halt (STALL) an endpoint or clear it. ++

++Returns -DWC_E_INVALID if invalid parameters were passed. Returns -DWC_E_SHUTDOWN if any other error ocurred. Returns -DWC_E_AGAIN if the STALL cannot be sent and must be tried again later Returns 0 on success. ++

++Definition at line 1733 of file dwc_otg_pcd.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int32_t dwc_otg_pcd_handle_intr (dwc_otg_pcd_t *  pcd  ) 
++
++
++ ++

++This function should be called on every hardware interrupt. ++

++The PCD handles the device interrupts. Many conditions can cause a device interrupt. When an interrupt occurs, the device interrupt service routine determines the cause of the interrupt and dispatches handling to the appropriate function. These interrupt handling functions are described below.

++All interrupt registers are processed from LSB to MSB. ++

++Definition at line 3971 of file dwc_otg_pcd_intr.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int dwc_otg_pcd_iso_ep_start (dwc_otg_pcd_t *  pcd,
void *  ep_handle,
uint8_t *  buf0,
uint8_t *  buf1,
dwc_dma_t  dma0,
dwc_dma_t  dma1,
int  sync_frame,
int  dp_frame,
int  data_per_frame,
int  start_frame,
int  buf_proc_intrvl,
void *  req_handle,
int  atomic_alloc 
)
++
++
++ ++

++Start isochronous transfers on the endpoint referenced by ep_handle. ++

++For isochronous transfers duble buffering is used. After processing each of buffers comlete callback will be called with status for each transaction.

++

Parameters:
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
pcd The PCD
ep_handle The handle of the endpoint
buf0 The virtual address of first data buffer
buf1 The virtual address of second data buffer
dma0 The DMA address of first data buffer
dma1 The DMA address of second data buffer
sync_frame Data pattern frame number
dp_frame Data size for pattern frame
data_per_frame Data size for regular frame
start_frame Frame number to start transfers, if -1 then start transfers ASAP.
buf_proc_intrvl Interval of ISOC Buffer processing
req_handle Handle of ISOC request
atomic_alloc Specefies whether to perform atomic allocation for internal data structures.
++
++Returns -DWC_E_NO_MEMORY if there is no enough memory. Returns -DWC_E_INVALID if incorrect arguments are passed to the function. Returns -DW_E_SHUTDOWN for any other error. Returns 0 on success ++

++

Todo:
    ++
  • pattern data support is to be implemented in the future
++
++ ++

++Definition at line 685 of file dwc_otg_pcd.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int dwc_otg_pcd_iso_ep_stop (dwc_otg_pcd_t *  pcd,
void *  ep_handle,
void *  req_handle 
)
++
++
++ ++

++Stop ISOC transfers on endpoint referenced by ep_handle. ++

++

Parameters:
++ ++ ++ ++ ++
pcd The PCD
ep_handle The handle of the endpoint
req_handle Handle of ISOC request
++
++Returns -DWC_E_INVALID if incorrect arguments are passed to the function Returns 0 on success ++

++Definition at line 794 of file dwc_otg_pcd.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_otg_pcd_get_iso_packet_params (dwc_otg_pcd_t *  pcd,
void *  ep_handle,
void *  iso_req_handle,
int  packet,
int *  status,
int *  actual,
int *  offset 
)
++
++
++ ++

++Get ISOC packet status. ++

++

Parameters:
++ ++ ++ ++ ++ ++ ++ ++ ++
pcd The PCD
ep_handle The handle of the endpoint
iso_req_handle Isochronoush request handle
packet Number of packet
status Out parameter for returning status
actual Out parameter for returning actual length
offset Out parameter for returning offset
++
++ ++

++Definition at line 862 of file dwc_otg_pcd.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int dwc_otg_pcd_get_iso_packet_count (dwc_otg_pcd_t *  pcd,
void *  ep_handle,
void *  iso_req_handle 
)
++
++
++ ++

++Get ISOC packet count. ++

++

Parameters:
++ ++ ++ ++ ++
pcd The PCD
ep_handle The handle of the endpoint
iso_req_handle 
++
++ ++

++Definition at line 850 of file dwc_otg_pcd.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int dwc_otg_pcd_wakeup (dwc_otg_pcd_t *  pcd  ) 
++
++
++ ++

++This function starts the SRP Protocol if no session is in progress. ++

++If a session is already in progress, but the device is suspended, remote wakeup signaling is started. ++

++Definition at line 1896 of file dwc_otg_pcd.c. ++

++

++

Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__pcd__intr_8c-source.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__pcd__intr_8c-source.html 2013-07-26 19:31:21.000000000 +0000 +@@ -0,0 +1,3629 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_pcd_intr.c Source File ++ ++ ++ ++ ++
++
++
++
++

dwc_otg_pcd_intr.c

Go to the documentation of this file.
00001 /* ==========================================================================
++00002  * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_pcd_intr.c $
++00003  * $Revision: #93 $
++00004  * $Date: 2009/04/02 $
++00005  * $Change: 1224216 $
++00006  *
++00007  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
++00008  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
++00009  * otherwise expressly agreed to in writing between Synopsys and you.
++00010  *
++00011  * The Software IS NOT an item of Licensed Software or Licensed Product under
++00012  * any End User Software License Agreement or Agreement for Licensed Product
++00013  * with Synopsys or any supplement thereto. You are permitted to use and
++00014  * redistribute this Software in source and binary forms, with or without
++00015  * modification, provided that redistributions of source code must retain this
++00016  * notice. You may not view, use, disclose, copy or distribute this file or
++00017  * any information contained herein except pursuant to this license grant from
++00018  * Synopsys. If you do not agree with this notice, including the disclaimer
++00019  * below, then you are not authorized to use the Software.
++00020  *
++00021  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
++00022  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++00023  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++00024  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
++00025  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++00026  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
++00027  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
++00028  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
++00029  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
++00030  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
++00031  * DAMAGE.
++00032  * ========================================================================== */
++00033 #ifndef DWC_HOST_ONLY
++00034 
++00035 #include "dwc_otg_pcd.h"
++00036 
++00037 #ifdef DWC_UTE_CFI
++00038 #include "dwc_otg_cfi.h"
++00039 #endif
++00040 
++00041 //#define PRINT_CFI_DMA_DESCS
++00042 
++00043 #define DEBUG_EP0
++00044 
++00048 static void dwc_otg_pcd_update_otg(dwc_otg_pcd_t * pcd, const unsigned reset)
++00049 {
++00050 
++00051         if (reset) {
++00052                 pcd->b_hnp_enable = 0;
++00053                 pcd->a_hnp_support = 0;
++00054                 pcd->a_alt_hnp_support = 0;
++00055         }
++00056 
++00057         if (pcd->fops->hnp_changed) {
++00058                 pcd->fops->hnp_changed(pcd);
++00059         }
++00060 }
++00061 
++00076 static inline void print_ep0_state(dwc_otg_pcd_t * pcd)
++00077 {
++00078 #ifdef DEBUG
++00079         char str[40];
++00080 
++00081         switch (pcd->ep0state) {
++00082         case EP0_DISCONNECT:
++00083                 dwc_strcpy(str, "EP0_DISCONNECT");
++00084                 break;
++00085         case EP0_IDLE:
++00086                 dwc_strcpy(str, "EP0_IDLE");
++00087                 break;
++00088         case EP0_IN_DATA_PHASE:
++00089                 dwc_strcpy(str, "EP0_IN_DATA_PHASE");
++00090                 break;
++00091         case EP0_OUT_DATA_PHASE:
++00092                 dwc_strcpy(str, "EP0_OUT_DATA_PHASE");
++00093                 break;
++00094         case EP0_IN_STATUS_PHASE:
++00095                 dwc_strcpy(str, "EP0_IN_STATUS_PHASE");
++00096                 break;
++00097         case EP0_OUT_STATUS_PHASE:
++00098                 dwc_strcpy(str, "EP0_OUT_STATUS_PHASE");
++00099                 break;
++00100         case EP0_STALL:
++00101                 dwc_strcpy(str, "EP0_STALL");
++00102                 break;
++00103         default:
++00104                 dwc_strcpy(str, "EP0_INVALID");
++00105         }
++00106 
++00107         DWC_DEBUGPL(DBG_ANY, "%s(%d)\n", str, pcd->ep0state);
++00108 #endif
++00109 }
++00110 
++00111 #ifdef DWC_UTE_CFI
++00112 static inline void print_desc(struct dwc_otg_dma_desc *ddesc,
++00113                               const uint8_t * epname, int descnum)
++00114 {
++00115         CFI_INFO
++00116             ("%s DMA_DESC(%d) buf=0x%08x bytes=0x%04x; sp=0x%x; l=0x%x; sts=0x%02x; bs=0x%02x\n",
++00117              epname, descnum, ddesc->buf, ddesc->status.b.bytes,
++00118              ddesc->status.b.sp, ddesc->status.b.l, ddesc->status.b.sts,
++00119              ddesc->status.b.bs);
++00120 }
++00121 #endif
++00122 
++00126 static inline dwc_otg_pcd_ep_t *get_in_ep(dwc_otg_pcd_t * pcd, uint32_t ep_num)
++00127 {
++00128         int i;
++00129         int num_in_eps = GET_CORE_IF(pcd)->dev_if->num_in_eps;
++00130         if (ep_num == 0) {
++00131                 return &pcd->ep0;
++00132         } else {
++00133                 for (i = 0; i < num_in_eps; ++i) {
++00134                         if (pcd->in_ep[i].dwc_ep.num == ep_num)
++00135                                 return &pcd->in_ep[i];
++00136                 }
++00137                 return 0;
++00138         }
++00139 }
++00140 
++00144 static inline dwc_otg_pcd_ep_t *get_out_ep(dwc_otg_pcd_t * pcd, uint32_t ep_num)
++00145 {
++00146         int i;
++00147         int num_out_eps = GET_CORE_IF(pcd)->dev_if->num_out_eps;
++00148         if (ep_num == 0) {
++00149                 return &pcd->ep0;
++00150         } else {
++00151                 for (i = 0; i < num_out_eps; ++i) {
++00152                         if (pcd->out_ep[i].dwc_ep.num == ep_num)
++00153                                 return &pcd->out_ep[i];
++00154                 }
++00155                 return 0;
++00156         }
++00157 }
++00158 
++00163 dwc_otg_pcd_ep_t *get_ep_by_addr(dwc_otg_pcd_t * pcd, u16 wIndex)
++00164 {
++00165         dwc_otg_pcd_ep_t *ep;
++00166         uint32_t ep_num = UE_GET_ADDR(wIndex);
++00167 
++00168         if (ep_num == 0) {
++00169                 ep = &pcd->ep0;
++00170         } else if (UE_GET_DIR(wIndex) == UE_DIR_IN) {   /* in ep */
++00171                 ep = &pcd->in_ep[ep_num - 1];
++00172         } else {
++00173                 ep = &pcd->out_ep[ep_num - 1];
++00174         }
++00175 
++00176         return ep;
++00177 }
++00178 
++00183 void start_next_request(dwc_otg_pcd_ep_t * ep)
++00184 {
++00185         dwc_otg_pcd_request_t *req = 0;
++00186         uint32_t max_transfer =
++00187             GET_CORE_IF(ep->pcd)->core_params->max_transfer_size;
++00188 
++00189 #ifdef DWC_UTE_CFI
++00190         struct dwc_otg_pcd *pcd;
++00191         pcd = ep->pcd;
++00192 #endif
++00193 
++00194         if (!DWC_CIRCLEQ_EMPTY(&ep->queue)) {
++00195                 req = DWC_CIRCLEQ_FIRST(&ep->queue);
++00196 
++00197 #ifdef DWC_UTE_CFI
++00198                 if (ep->dwc_ep.buff_mode != BM_STANDARD) {
++00199                         ep->dwc_ep.cfi_req_len = req->length;
++00200                         pcd->cfi->ops.build_descriptors(pcd->cfi, pcd, ep, req);
++00201                 } else {
++00202 #endif
++00203                 /* Setup and start the Transfer */
++00204                 ep->dwc_ep.dma_addr = req->dma;
++00205                 ep->dwc_ep.start_xfer_buff = req->buf;
++00206                 ep->dwc_ep.xfer_buff = req->buf;
++00207                 ep->dwc_ep.sent_zlp = 0;
++00208                 ep->dwc_ep.total_len = req->length;
++00209                 ep->dwc_ep.xfer_len = 0;
++00210                 ep->dwc_ep.xfer_count = 0;
++00211 
++00212                 ep->dwc_ep.maxxfer = max_transfer;
++00213                 if (GET_CORE_IF(ep->pcd)->dma_desc_enable) {
++00214                         uint32_t out_max_xfer = DDMA_MAX_TRANSFER_SIZE
++00215                             - (DDMA_MAX_TRANSFER_SIZE % 4);
++00216                         if (ep->dwc_ep.is_in) {
++00217                                         if (ep->dwc_ep.maxxfer >
++00218                                             DDMA_MAX_TRANSFER_SIZE) {
++00219                                         ep->dwc_ep.maxxfer =
++00220                                             DDMA_MAX_TRANSFER_SIZE;
++00221                                 }
++00222                         } else {
++00223                                 if (ep->dwc_ep.maxxfer > out_max_xfer) {
++00224                                                 ep->dwc_ep.maxxfer =
++00225                                                     out_max_xfer;
++00226                                 }
++00227                         }
++00228                 }
++00229                 if (ep->dwc_ep.maxxfer < ep->dwc_ep.total_len) {
++00230                         ep->dwc_ep.maxxfer -=
++00231                             (ep->dwc_ep.maxxfer % ep->dwc_ep.maxpacket);
++00232                 }
++00233                 if (req->sent_zlp) {
++00234                                 if ((ep->dwc_ep.total_len %
++00235                                      ep->dwc_ep.maxpacket == 0)
++00236                                     && (ep->dwc_ep.total_len != 0)) {
++00237                                 ep->dwc_ep.sent_zlp = 1;
++00238                         }
++00239 
++00240                 }
++00241 #ifdef DWC_UTE_CFI
++00242                 }
++00243 #endif
++00244                 dwc_otg_ep_start_transfer(GET_CORE_IF(ep->pcd), &ep->dwc_ep);
++00245         }
++00246 }
++00247 
++00252 int32_t dwc_otg_pcd_handle_sof_intr(dwc_otg_pcd_t * pcd)
++00253 {
++00254         dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
++00255 
++00256         gintsts_data_t gintsts;
++00257 
++00258         DWC_DEBUGPL(DBG_PCD, "SOF\n");
++00259 
++00260         /* Clear interrupt */
++00261         gintsts.d32 = 0;
++00262         gintsts.b.sofintr = 1;
++00263         dwc_write_reg32(&core_if->core_global_regs->gintsts, gintsts.d32);
++00264 
++00265         return 1;
++00266 }
++00267 
++00285 int32_t dwc_otg_pcd_handle_rx_status_q_level_intr(dwc_otg_pcd_t * pcd)
++00286 {
++00287         dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
++00288         dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
++00289         gintmsk_data_t gintmask = {.d32 = 0 };
++00290         device_grxsts_data_t status;
++00291         dwc_otg_pcd_ep_t *ep;
++00292         gintsts_data_t gintsts;
++00293 #ifdef DEBUG
++00294         static char *dpid_str[] = { "D0", "D2", "D1", "MDATA" };
++00295 #endif
++00296 
++00297         //DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, _pcd);
++00298         /* Disable the Rx Status Queue Level interrupt */
++00299         gintmask.b.rxstsqlvl = 1;
++00300         dwc_modify_reg32(&global_regs->gintmsk, gintmask.d32, 0);
++00301 
++00302         /* Get the Status from the top of the FIFO */
++00303         status.d32 = dwc_read_reg32(&global_regs->grxstsp);
++00304 
++00305         DWC_DEBUGPL(DBG_PCD, "EP:%d BCnt:%d DPID:%s "
++00306                     "pktsts:%x Frame:%d(0x%0x)\n",
++00307                     status.b.epnum, status.b.bcnt,
++00308                     dpid_str[status.b.dpid],
++00309                     status.b.pktsts, status.b.fn, status.b.fn);
++00310         /* Get pointer to EP structure */
++00311         ep = get_out_ep(pcd, status.b.epnum);
++00312 
++00313         switch (status.b.pktsts) {
++00314         case DWC_DSTS_GOUT_NAK:
++00315                 DWC_DEBUGPL(DBG_PCDV, "Global OUT NAK\n");
++00316                 break;
++00317         case DWC_STS_DATA_UPDT:
++00318                 DWC_DEBUGPL(DBG_PCDV, "OUT Data Packet\n");
++00319                 if (status.b.bcnt && ep->dwc_ep.xfer_buff) {
++00321                         dwc_otg_read_packet(core_if,
++00322                                             ep->dwc_ep.xfer_buff,
++00323                                             status.b.bcnt);
++00324                         ep->dwc_ep.xfer_count += status.b.bcnt;
++00325                         ep->dwc_ep.xfer_buff += status.b.bcnt;
++00326                 }
++00327                 break;
++00328         case DWC_STS_XFER_COMP:
++00329                 DWC_DEBUGPL(DBG_PCDV, "OUT Complete\n");
++00330                 break;
++00331         case DWC_DSTS_SETUP_COMP:
++00332 #ifdef DEBUG_EP0
++00333                 DWC_DEBUGPL(DBG_PCDV, "Setup Complete\n");
++00334 #endif
++00335                 break;
++00336         case DWC_DSTS_SETUP_UPDT:
++00337                 dwc_otg_read_setup_packet(core_if, pcd->setup_pkt->d32);
++00338 #ifdef DEBUG_EP0
++00339                 DWC_DEBUGPL(DBG_PCD,
++00340                             "SETUP PKT: %02x.%02x v%04x i%04x l%04x\n",
++00341                             pcd->setup_pkt->req.bmRequestType,
++00342                             pcd->setup_pkt->req.bRequest,
++00343                             UGETW(pcd->setup_pkt->req.wValue),
++00344                             UGETW(pcd->setup_pkt->req.wIndex),
++00345                             UGETW(pcd->setup_pkt->req.wLength));
++00346 #endif
++00347                 ep->dwc_ep.xfer_count += status.b.bcnt;
++00348                 break;
++00349         default:
++00350                 DWC_DEBUGPL(DBG_PCDV, "Invalid Packet Status (0x%0x)\n",
++00351                             status.b.pktsts);
++00352                 break;
++00353         }
++00354 
++00355         /* Enable the Rx Status Queue Level interrupt */
++00356         dwc_modify_reg32(&global_regs->gintmsk, 0, gintmask.d32);
++00357         /* Clear interrupt */
++00358         gintsts.d32 = 0;
++00359         gintsts.b.rxstsqlvl = 1;
++00360         dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
++00361 
++00362         //DWC_DEBUGPL(DBG_PCDV, "EXIT: %s\n", __func__);
++00363         return 1;
++00364 }
++00365 
++00378 static inline int get_ep_of_last_in_token(dwc_otg_core_if_t * core_if)
++00379 {
++00380         dwc_otg_device_global_regs_t *dev_global_regs =
++00381             core_if->dev_if->dev_global_regs;
++00382         const uint32_t TOKEN_Q_DEPTH = core_if->hwcfg2.b.dev_token_q_depth;
++00383         /* Number of Token Queue Registers */
++00384         const int DTKNQ_REG_CNT = (TOKEN_Q_DEPTH + 7) / 8;
++00385         dtknq1_data_t dtknqr1;
++00386         uint32_t in_tkn_epnums[4];
++00387         int ndx = 0;
++00388         int i = 0;
++00389         volatile uint32_t *addr = &dev_global_regs->dtknqr1;
++00390         int epnum = 0;
++00391 
++00392         //DWC_DEBUGPL(DBG_PCD,"dev_token_q_depth=%d\n",TOKEN_Q_DEPTH);
++00393 
++00394         /* Read the DTKNQ Registers */
++00395         for (i = 0; i < DTKNQ_REG_CNT; i++) {
++00396                 in_tkn_epnums[i] = dwc_read_reg32(addr);
++00397                 DWC_DEBUGPL(DBG_PCDV, "DTKNQR%d=0x%08x\n", i + 1,
++00398                             in_tkn_epnums[i]);
++00399                 if (addr == &dev_global_regs->dvbusdis) {
++00400                         addr = &dev_global_regs->dtknqr3_dthrctl;
++00401                 } else {
++00402                         ++addr;
++00403                 }
++00404 
++00405         }
++00406 
++00407         /* Copy the DTKNQR1 data to the bit field. */
++00408         dtknqr1.d32 = in_tkn_epnums[0];
++00409         /* Get the EP numbers */
++00410         in_tkn_epnums[0] = dtknqr1.b.epnums0_5;
++00411         ndx = dtknqr1.b.intknwptr - 1;
++00412 
++00413         //DWC_DEBUGPL(DBG_PCDV,"ndx=%d\n",ndx);
++00414         if (ndx == -1) {
++00417                 int cnt = TOKEN_Q_DEPTH;
++00418                 if (TOKEN_Q_DEPTH <= 6) {
++00419                         cnt = TOKEN_Q_DEPTH - 1;
++00420                 } else if (TOKEN_Q_DEPTH <= 14) {
++00421                         cnt = TOKEN_Q_DEPTH - 7;
++00422                 } else if (TOKEN_Q_DEPTH <= 22) {
++00423                         cnt = TOKEN_Q_DEPTH - 15;
++00424                 } else {
++00425                         cnt = TOKEN_Q_DEPTH - 23;
++00426                 }
++00427                 epnum = (in_tkn_epnums[DTKNQ_REG_CNT - 1] >> (cnt * 4)) & 0xF;
++00428         } else {
++00429                 if (ndx <= 5) {
++00430                         epnum = (in_tkn_epnums[0] >> (ndx * 4)) & 0xF;
++00431                 } else if (ndx <= 13) {
++00432                         ndx -= 6;
++00433                         epnum = (in_tkn_epnums[1] >> (ndx * 4)) & 0xF;
++00434                 } else if (ndx <= 21) {
++00435                         ndx -= 14;
++00436                         epnum = (in_tkn_epnums[2] >> (ndx * 4)) & 0xF;
++00437                 } else if (ndx <= 29) {
++00438                         ndx -= 22;
++00439                         epnum = (in_tkn_epnums[3] >> (ndx * 4)) & 0xF;
++00440                 }
++00441         }
++00442         //DWC_DEBUGPL(DBG_PCD,"epnum=%d\n",epnum);
++00443         return epnum;
++00444 }
++00445 
++00451 int32_t dwc_otg_pcd_handle_np_tx_fifo_empty_intr(dwc_otg_pcd_t * pcd)
++00452 {
++00453         dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
++00454         dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
++00455         dwc_otg_dev_in_ep_regs_t *ep_regs;
++00456         gnptxsts_data_t txstatus = {.d32 = 0 };
++00457         gintsts_data_t gintsts;
++00458 
++00459         int epnum = 0;
++00460         dwc_otg_pcd_ep_t *ep = 0;
++00461         uint32_t len = 0;
++00462         int dwords;
++00463 
++00464         /* Get the epnum from the IN Token Learning Queue. */
++00465         epnum = get_ep_of_last_in_token(core_if);
++00466         ep = get_in_ep(pcd, epnum);
++00467 
++00468         DWC_DEBUGPL(DBG_PCD, "NP TxFifo Empty: %d \n", epnum);
++00469 
++00470         ep_regs = core_if->dev_if->in_ep_regs[epnum];
++00471 
++00472         len = ep->dwc_ep.xfer_len - ep->dwc_ep.xfer_count;
++00473         if (len > ep->dwc_ep.maxpacket) {
++00474                 len = ep->dwc_ep.maxpacket;
++00475         }
++00476         dwords = (len + 3) / 4;
++00477 
++00478         /* While there is space in the queue and space in the FIFO and
++00479          * More data to tranfer, Write packets to the Tx FIFO */
++00480         txstatus.d32 = dwc_read_reg32(&global_regs->gnptxsts);
++00481         DWC_DEBUGPL(DBG_PCDV, "b4 GNPTXSTS=0x%08x\n", txstatus.d32);
++00482 
++00483         while (txstatus.b.nptxqspcavail > 0 &&
++00484                txstatus.b.nptxfspcavail > dwords &&
++00485                ep->dwc_ep.xfer_count < ep->dwc_ep.xfer_len) {
++00486                 /* Write the FIFO */
++00487                 dwc_otg_ep_write_packet(core_if, &ep->dwc_ep, 0);
++00488                 len = ep->dwc_ep.xfer_len - ep->dwc_ep.xfer_count;
++00489 
++00490                 if (len > ep->dwc_ep.maxpacket) {
++00491                         len = ep->dwc_ep.maxpacket;
++00492                 }
++00493 
++00494                 dwords = (len + 3) / 4;
++00495                 txstatus.d32 = dwc_read_reg32(&global_regs->gnptxsts);
++00496                 DWC_DEBUGPL(DBG_PCDV, "GNPTXSTS=0x%08x\n", txstatus.d32);
++00497         }
++00498 
++00499         DWC_DEBUGPL(DBG_PCDV, "GNPTXSTS=0x%08x\n",
++00500                     dwc_read_reg32(&global_regs->gnptxsts));
++00501 
++00502         /* Clear interrupt */
++00503         gintsts.d32 = 0;
++00504         gintsts.b.nptxfempty = 1;
++00505         dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
++00506 
++00507         return 1;
++00508 }
++00509 
++00515 static int32_t write_empty_tx_fifo(dwc_otg_pcd_t * pcd, uint32_t epnum)
++00516 {
++00517         dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
++00518         dwc_otg_dev_if_t *dev_if = core_if->dev_if;
++00519         dwc_otg_dev_in_ep_regs_t *ep_regs;
++00520         dtxfsts_data_t txstatus = {.d32 = 0 };
++00521         dwc_otg_pcd_ep_t *ep = 0;
++00522         uint32_t len = 0;
++00523         int dwords;
++00524 
++00525         ep = get_in_ep(pcd, epnum);
++00526 
++00527         DWC_DEBUGPL(DBG_PCD, "Dedicated TxFifo Empty: %d \n", epnum);
++00528 
++00529         ep_regs = core_if->dev_if->in_ep_regs[epnum];
++00530 
++00531         len = ep->dwc_ep.xfer_len - ep->dwc_ep.xfer_count;
++00532 
++00533         if (len > ep->dwc_ep.maxpacket) {
++00534                 len = ep->dwc_ep.maxpacket;
++00535         }
++00536 
++00537         dwords = (len + 3) / 4;
++00538 
++00539         /* While there is space in the queue and space in the FIFO and
++00540          * More data to tranfer, Write packets to the Tx FIFO */
++00541         txstatus.d32 = dwc_read_reg32(&dev_if->in_ep_regs[epnum]->dtxfsts);
++00542         DWC_DEBUGPL(DBG_PCDV, "b4 dtxfsts[%d]=0x%08x\n", epnum, txstatus.d32);
++00543 
++00544         while (txstatus.b.txfspcavail > dwords &&
++00545                ep->dwc_ep.xfer_count < ep->dwc_ep.xfer_len &&
++00546                ep->dwc_ep.xfer_len != 0) {
++00547                 /* Write the FIFO */
++00548                 dwc_otg_ep_write_packet(core_if, &ep->dwc_ep, 0);
++00549 
++00550                 len = ep->dwc_ep.xfer_len - ep->dwc_ep.xfer_count;
++00551                 if (len > ep->dwc_ep.maxpacket) {
++00552                         len = ep->dwc_ep.maxpacket;
++00553                 }
++00554 
++00555                 dwords = (len + 3) / 4;
++00556                 txstatus.d32 =
++00557                     dwc_read_reg32(&dev_if->in_ep_regs[epnum]->dtxfsts);
++00558                 DWC_DEBUGPL(DBG_PCDV, "dtxfsts[%d]=0x%08x\n", epnum,
++00559                             txstatus.d32);
++00560         }
++00561 
++00562         DWC_DEBUGPL(DBG_PCDV, "b4 dtxfsts[%d]=0x%08x\n", epnum,
++00563                     dwc_read_reg32(&dev_if->in_ep_regs[epnum]->dtxfsts));
++00564 
++00565         return 1;
++00566 }
++00567 
++00573 void dwc_otg_pcd_stop(dwc_otg_pcd_t * pcd)
++00574 {
++00575         int i, num_in_eps, num_out_eps;
++00576         dwc_otg_pcd_ep_t *ep;
++00577 
++00578         gintmsk_data_t intr_mask = {.d32 = 0 };
++00579 
++00580         DWC_SPINLOCK(pcd->lock);
++00581 
++00582         num_in_eps = GET_CORE_IF(pcd)->dev_if->num_in_eps;
++00583         num_out_eps = GET_CORE_IF(pcd)->dev_if->num_out_eps;
++00584 
++00585         DWC_DEBUGPL(DBG_PCDV, "%s() \n", __func__);
++00586         /* don't disconnect drivers more than once */
++00587         if (pcd->ep0state == EP0_DISCONNECT) {
++00588                 DWC_DEBUGPL(DBG_ANY, "%s() Already Disconnected\n", __func__);
++00589                 return;
++00590         }
++00591         pcd->ep0state = EP0_DISCONNECT;
++00592 
++00593         /* Reset the OTG state. */
++00594         dwc_otg_pcd_update_otg(pcd, 1);
++00595 
++00596         /* Disable the NP Tx Fifo Empty Interrupt. */
++00597         intr_mask.b.nptxfempty = 1;
++00598         dwc_modify_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk,
++00599                          intr_mask.d32, 0);
++00600 
++00601         /* Flush the FIFOs */
++00603         dwc_otg_flush_tx_fifo(GET_CORE_IF(pcd), 0x10);
++00604         dwc_otg_flush_rx_fifo(GET_CORE_IF(pcd));
++00605 
++00606         /* prevent new request submissions, kill any outstanding requests  */
++00607         ep = &pcd->ep0;
++00608         dwc_otg_request_nuke(ep);
++00609         /* prevent new request submissions, kill any outstanding requests  */
++00610         for (i = 0; i < num_in_eps; i++) {
++00611                 dwc_otg_pcd_ep_t *ep = &pcd->in_ep[i];
++00612                 dwc_otg_request_nuke(ep);
++00613         }
++00614         /* prevent new request submissions, kill any outstanding requests  */
++00615         for (i = 0; i < num_out_eps; i++) {
++00616                 dwc_otg_pcd_ep_t *ep = &pcd->out_ep[i];
++00617                 dwc_otg_request_nuke(ep);
++00618         }
++00619 
++00620         /* report disconnect; the driver is already quiesced */
++00621         if (pcd->fops->disconnect) {
++00622                 DWC_SPINUNLOCK(pcd->lock);
++00623                 pcd->fops->disconnect(pcd);
++00624                 DWC_SPINLOCK(pcd->lock);
++00625         }
++00626         DWC_SPINUNLOCK(pcd->lock);
++00627 }
++00628 
++00632 int32_t dwc_otg_pcd_handle_i2c_intr(dwc_otg_pcd_t * pcd)
++00633 {
++00634         gintmsk_data_t intr_mask = {.d32 = 0 };
++00635         gintsts_data_t gintsts;
++00636 
++00637         DWC_PRINTF("INTERRUPT Handler not implemented for %s\n", "i2cintr");
++00638         intr_mask.b.i2cintr = 1;
++00639         dwc_modify_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk,
++00640                          intr_mask.d32, 0);
++00641 
++00642         /* Clear interrupt */
++00643         gintsts.d32 = 0;
++00644         gintsts.b.i2cintr = 1;
++00645         dwc_write_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
++00646                         gintsts.d32);
++00647         return 1;
++00648 }
++00649 
++00653 int32_t dwc_otg_pcd_handle_early_suspend_intr(dwc_otg_pcd_t * pcd)
++00654 {
++00655         gintsts_data_t gintsts;
++00656 #if defined(VERBOSE)
++00657         DWC_PRINTF("Early Suspend Detected\n");
++00658 #endif
++00659         /* Clear interrupt */
++00660         gintsts.d32 = 0;
++00661         gintsts.b.erlysuspend = 1;
++00662         dwc_write_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
++00663                         gintsts.d32);
++00664         return 1;
++00665 }
++00666 
++00684 static inline void ep0_out_start(dwc_otg_core_if_t * core_if,
++00685                                  dwc_otg_pcd_t * pcd)
++00686 {
++00687         dwc_otg_dev_if_t *dev_if = core_if->dev_if;
++00688         deptsiz0_data_t doeptsize0 = {.d32 = 0 };
++00689         dwc_otg_dev_dma_desc_t *dma_desc;
++00690         depctl_data_t doepctl = {.d32 = 0 };
++00691 
++00692 #ifdef VERBOSE
++00693         DWC_DEBUGPL(DBG_PCDV, "%s() doepctl0=%0x\n", __func__,
++00694                     dwc_read_reg32(&dev_if->out_ep_regs[0]->doepctl));
++00695 #endif
++00696 
++00697         doeptsize0.b.supcnt = 3;
++00698         doeptsize0.b.pktcnt = 1;
++00699         doeptsize0.b.xfersize = 8 * 3;
++00700 
++00701         if (core_if->dma_enable) {
++00702                 if (!core_if->dma_desc_enable) {
++00704                         dwc_write_reg32(&dev_if->out_ep_regs[0]->doeptsiz,
++00705                                         doeptsize0.d32);
++00706 
++00708                         dwc_write_reg32(&dev_if->out_ep_regs[0]->doepdma,
++00709                                         pcd->setup_pkt_dma_handle);
++00710                 } else {
++00711                         dev_if->setup_desc_index =
++00712                             (dev_if->setup_desc_index + 1) & 1;
++00713                         dma_desc =
++00714                             dev_if->setup_desc_addr[dev_if->setup_desc_index];
++00715 
++00717                         dma_desc->status.b.bs = BS_HOST_BUSY;
++00718                         dma_desc->status.b.l = 1;
++00719                         dma_desc->status.b.ioc = 1;
++00720                         dma_desc->status.b.bytes = pcd->ep0.dwc_ep.maxpacket;
++00721                         dma_desc->buf = pcd->setup_pkt_dma_handle;
++00722                         dma_desc->status.b.bs = BS_HOST_READY;
++00723 
++00725                         dwc_write_reg32(&dev_if->out_ep_regs[0]->doepdma,
++00726                                         dev_if->dma_setup_desc_addr[dev_if->
++00727                                                                     setup_desc_index]);
++00728                 }
++00729 
++00730         } else {
++00732                 dwc_write_reg32(&dev_if->out_ep_regs[0]->doeptsiz,
++00733                                 doeptsize0.d32);
++00734         }
++00735 
++00737         doepctl.b.epena = 1;
++00738         doepctl.b.cnak = 1;
++00739         dwc_write_reg32(&dev_if->out_ep_regs[0]->doepctl, doepctl.d32);
++00740 
++00741 #ifdef VERBOSE
++00742         DWC_DEBUGPL(DBG_PCDV, "doepctl0=%0x\n",
++00743                     dwc_read_reg32(&dev_if->out_ep_regs[0]->doepctl));
++00744         DWC_DEBUGPL(DBG_PCDV, "diepctl0=%0x\n",
++00745                     dwc_read_reg32(&dev_if->in_ep_regs[0]->diepctl));
++00746 #endif
++00747 }
++00748 
++00772 int32_t dwc_otg_pcd_handle_usb_reset_intr(dwc_otg_pcd_t * pcd)
++00773 {
++00774         dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
++00775         dwc_otg_dev_if_t *dev_if = core_if->dev_if;
++00776         depctl_data_t doepctl = {.d32 = 0 };
++00777         daint_data_t daintmsk = {.d32 = 0 };
++00778         doepmsk_data_t doepmsk = {.d32 = 0 };
++00779         diepmsk_data_t diepmsk = {.d32 = 0 };
++00780         dcfg_data_t dcfg = {.d32 = 0 };
++00781         grstctl_t resetctl = {.d32 = 0 };
++00782         dctl_data_t dctl = {.d32 = 0 };
++00783         int i = 0;
++00784         gintsts_data_t gintsts;
++00785         pcgcctl_data_t power = {.d32 = 0 };
++00786 
++00787         power.d32 = dwc_read_reg32(core_if->pcgcctl);
++00788         if (power.b.stoppclk) {
++00789                 power.d32 = 0;
++00790                 power.b.stoppclk = 1;
++00791                 dwc_modify_reg32(core_if->pcgcctl, power.d32, 0);
++00792 
++00793                 power.b.pwrclmp = 1;
++00794                 dwc_modify_reg32(core_if->pcgcctl, power.d32, 0);
++00795 
++00796                 power.b.rstpdwnmodule = 1;
++00797                 dwc_modify_reg32(core_if->pcgcctl, power.d32, 0);
++00798         }
++00799 
++00800         core_if->lx_state = DWC_OTG_L0;
++00801 
++00802         DWC_PRINTF("USB RESET\n");
++00803 #ifdef DWC_EN_ISOC
++00804         for (i = 1; i < 16; ++i) {
++00805                 dwc_otg_pcd_ep_t *ep;
++00806                 dwc_ep_t *dwc_ep;
++00807                 ep = get_in_ep(pcd, i);
++00808                 if (ep != 0) {
++00809                         dwc_ep = &ep->dwc_ep;
++00810                         dwc_ep->next_frame = 0xffffffff;
++00811                 }
++00812         }
++00813 #endif                          /* DWC_EN_ISOC */
++00814 
++00815         /* reset the HNP settings */
++00816         dwc_otg_pcd_update_otg(pcd, 1);
++00817 
++00818         /* Clear the Remote Wakeup Signalling */
++00819         dctl.b.rmtwkupsig = 1;
++00820         dwc_modify_reg32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32, 0);
++00821 
++00822         /* Set NAK for all OUT EPs */
++00823         doepctl.b.snak = 1;
++00824         for (i = 0; i <= dev_if->num_out_eps; i++) {
++00825                 dwc_write_reg32(&dev_if->out_ep_regs[i]->doepctl, doepctl.d32);
++00826         }
++00827 
++00828         /* Flush the NP Tx FIFO */
++00829         dwc_otg_flush_tx_fifo(core_if, 0x10);
++00830         /* Flush the Learning Queue */
++00831         resetctl.b.intknqflsh = 1;
++00832         dwc_write_reg32(&core_if->core_global_regs->grstctl, resetctl.d32);
++00833 
++00834         if (core_if->multiproc_int_enable) {
++00835                 daintmsk.b.inep0 = 1;
++00836                 daintmsk.b.outep0 = 1;
++00837                 dwc_write_reg32(&dev_if->dev_global_regs->deachintmsk,
++00838                                 daintmsk.d32);
++00839 
++00840                 doepmsk.b.setup = 1;
++00841                 doepmsk.b.xfercompl = 1;
++00842                 doepmsk.b.ahberr = 1;
++00843                 doepmsk.b.epdisabled = 1;
++00844 
++00845                 if (core_if->dma_desc_enable) {
++00846                         doepmsk.b.stsphsercvd = 1;
++00847                         doepmsk.b.bna = 1;
++00848                 }
++00849 /*              
++00850                 doepmsk.b.babble = 1;
++00851                 doepmsk.b.nyet = 1;
++00852                 
++00853                 if(core_if->dma_enable) {
++00854                         doepmsk.b.nak = 1;
++00855                 }
++00856 */
++00857                 dwc_write_reg32(&dev_if->dev_global_regs->doepeachintmsk[0],
++00858                                 doepmsk.d32);
++00859 
++00860                 diepmsk.b.xfercompl = 1;
++00861                 diepmsk.b.timeout = 1;
++00862                 diepmsk.b.epdisabled = 1;
++00863                 diepmsk.b.ahberr = 1;
++00864                 diepmsk.b.intknepmis = 1;
++00865 
++00866                 if (core_if->dma_desc_enable) {
++00867                         diepmsk.b.bna = 1;
++00868                 }
++00869 /*              
++00870                 if(core_if->dma_enable) {
++00871                         diepmsk.b.nak = 1;
++00872                 }
++00873 */
++00874                 dwc_write_reg32(&dev_if->dev_global_regs->diepeachintmsk[0],
++00875                                 diepmsk.d32);
++00876         } else {
++00877                 daintmsk.b.inep0 = 1;
++00878                 daintmsk.b.outep0 = 1;
++00879                 dwc_write_reg32(&dev_if->dev_global_regs->daintmsk,
++00880                                 daintmsk.d32);
++00881 
++00882                 doepmsk.b.setup = 1;
++00883                 doepmsk.b.xfercompl = 1;
++00884                 doepmsk.b.ahberr = 1;
++00885                 doepmsk.b.epdisabled = 1;
++00886 
++00887                 if (core_if->dma_desc_enable) {
++00888                         doepmsk.b.stsphsercvd = 1;
++00889                         doepmsk.b.bna = 1;
++00890                 }
++00891                 dwc_write_reg32(&dev_if->dev_global_regs->doepmsk, doepmsk.d32);
++00892 
++00893                 diepmsk.b.xfercompl = 1;
++00894                 diepmsk.b.timeout = 1;
++00895                 diepmsk.b.epdisabled = 1;
++00896                 diepmsk.b.ahberr = 1;
++00897                 diepmsk.b.intknepmis = 1;
++00898 
++00899                 if (core_if->dma_desc_enable) {
++00900                         diepmsk.b.bna = 1;
++00901                 }
++00902 
++00903                 dwc_write_reg32(&dev_if->dev_global_regs->diepmsk, diepmsk.d32);
++00904         }
++00905 
++00906         /* Reset Device Address */
++00907         dcfg.d32 = dwc_read_reg32(&dev_if->dev_global_regs->dcfg);
++00908         dcfg.b.devaddr = 0;
++00909         dwc_write_reg32(&dev_if->dev_global_regs->dcfg, dcfg.d32);
++00910 
++00911         /* setup EP0 to receive SETUP packets */
++00912         ep0_out_start(core_if, pcd);
++00913 
++00914         /* Clear interrupt */
++00915         gintsts.d32 = 0;
++00916         gintsts.b.usbreset = 1;
++00917         dwc_write_reg32(&core_if->core_global_regs->gintsts, gintsts.d32);
++00918 
++00919         return 1;
++00920 }
++00921 
++00928 static int get_device_speed(dwc_otg_core_if_t * core_if)
++00929 {
++00930         dsts_data_t dsts;
++00931         int speed = 0;
++00932         dsts.d32 = dwc_read_reg32(&core_if->dev_if->dev_global_regs->dsts);
++00933 
++00934         switch (dsts.b.enumspd) {
++00935         case DWC_DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ:
++00936                 speed = USB_SPEED_HIGH;
++00937                 break;
++00938         case DWC_DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ:
++00939         case DWC_DSTS_ENUMSPD_FS_PHY_48MHZ:
++00940                 speed = USB_SPEED_FULL;
++00941                 break;
++00942 
++00943         case DWC_DSTS_ENUMSPD_LS_PHY_6MHZ:
++00944                 speed = USB_SPEED_LOW;
++00945                 break;
++00946         }
++00947 
++00948         return speed;
++00949 }
++00950 
++00956 int32_t dwc_otg_pcd_handle_enum_done_intr(dwc_otg_pcd_t * pcd)
++00957 {
++00958         dwc_otg_pcd_ep_t *ep0 = &pcd->ep0;
++00959         gintsts_data_t gintsts;
++00960         gusbcfg_data_t gusbcfg;
++00961         dwc_otg_core_global_regs_t *global_regs =
++00962             GET_CORE_IF(pcd)->core_global_regs;
++00963         uint8_t utmi16b, utmi8b;
++00964         int speed;
++00965         DWC_DEBUGPL(DBG_PCD, "SPEED ENUM\n");
++00966 
++00967         if (GET_CORE_IF(pcd)->snpsid >= OTG_CORE_REV_2_60a) {
++00968                 utmi16b = 6;
++00969                 utmi8b = 9;
++00970         } else {
++00971                 utmi16b = 4;
++00972                 utmi8b = 8;
++00973         }
++00974         dwc_otg_ep0_activate(GET_CORE_IF(pcd), &ep0->dwc_ep);
++00975 
++00976 #ifdef DEBUG_EP0
++00977         print_ep0_state(pcd);
++00978 #endif
++00979 
++00980         if (pcd->ep0state == EP0_DISCONNECT) {
++00981                 pcd->ep0state = EP0_IDLE;
++00982         } else if (pcd->ep0state == EP0_STALL) {
++00983                 pcd->ep0state = EP0_IDLE;
++00984         }
++00985 
++00986         pcd->ep0state = EP0_IDLE;
++00987 
++00988         ep0->stopped = 0;
++00989 
++00990         speed = get_device_speed(GET_CORE_IF(pcd));
++00991         pcd->fops->connect(pcd, speed);
++00992 
++00993         /* Set USB turnaround time based on device speed and PHY interface. */
++00994         gusbcfg.d32 = dwc_read_reg32(&global_regs->gusbcfg);
++00995         if (speed == USB_SPEED_HIGH) {
++00996                 if (GET_CORE_IF(pcd)->hwcfg2.b.hs_phy_type ==
++00997                     DWC_HWCFG2_HS_PHY_TYPE_ULPI) {
++00998                         /* ULPI interface */
++00999                         gusbcfg.b.usbtrdtim = 9;
++01000                 }
++01001                 if (GET_CORE_IF(pcd)->hwcfg2.b.hs_phy_type ==
++01002                     DWC_HWCFG2_HS_PHY_TYPE_UTMI) {
++01003                         /* UTMI+ interface */
++01004                         if (GET_CORE_IF(pcd)->hwcfg4.b.utmi_phy_data_width == 0) {
++01005                                 gusbcfg.b.usbtrdtim = utmi8b;
++01006                         } else if (GET_CORE_IF(pcd)->hwcfg4.b.
++01007                                    utmi_phy_data_width == 1) {
++01008                                 gusbcfg.b.usbtrdtim = utmi16b;
++01009                         } else if (GET_CORE_IF(pcd)->core_params->
++01010                                    phy_utmi_width == 8) {
++01011                                 gusbcfg.b.usbtrdtim = utmi8b;
++01012                         } else {
++01013                                 gusbcfg.b.usbtrdtim = utmi16b;
++01014                         }
++01015                 }
++01016                 if (GET_CORE_IF(pcd)->hwcfg2.b.hs_phy_type ==
++01017                     DWC_HWCFG2_HS_PHY_TYPE_UTMI_ULPI) {
++01018                         /* UTMI+  OR  ULPI interface */
++01019                         if (gusbcfg.b.ulpi_utmi_sel == 1) {
++01020                                 /* ULPI interface */
++01021                                 gusbcfg.b.usbtrdtim = 9;
++01022                         } else {
++01023                                 /* UTMI+ interface */
++01024                                 if (GET_CORE_IF(pcd)->core_params->
++01025                                     phy_utmi_width == 16) {
++01026                                         gusbcfg.b.usbtrdtim = utmi16b;
++01027                                 } else {
++01028                                         gusbcfg.b.usbtrdtim = utmi8b;
++01029                                 }
++01030                         }
++01031                 }
++01032         } else {
++01033                 /* Full or low speed */
++01034                 gusbcfg.b.usbtrdtim = 9;
++01035         }
++01036         dwc_write_reg32(&global_regs->gusbcfg, gusbcfg.d32);
++01037 
++01038         /* Clear interrupt */
++01039         gintsts.d32 = 0;
++01040         gintsts.b.enumdone = 1;
++01041         dwc_write_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
++01042                         gintsts.d32);
++01043         return 1;
++01044 }
++01045 
++01051 int32_t dwc_otg_pcd_handle_isoc_out_packet_dropped_intr(dwc_otg_pcd_t * pcd)
++01052 {
++01053         gintmsk_data_t intr_mask = {.d32 = 0 };
++01054         gintsts_data_t gintsts;
++01055 
++01056         DWC_PRINTF("INTERRUPT Handler not implemented for %s\n",
++01057                    "ISOC Out Dropped");
++01058 
++01059         intr_mask.b.isooutdrop = 1;
++01060         dwc_modify_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk,
++01061                          intr_mask.d32, 0);
++01062 
++01063         /* Clear interrupt */
++01064         gintsts.d32 = 0;
++01065         gintsts.b.isooutdrop = 1;
++01066         dwc_write_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
++01067                         gintsts.d32);
++01068 
++01069         return 1;
++01070 }
++01071 
++01077 int32_t dwc_otg_pcd_handle_end_periodic_frame_intr(dwc_otg_pcd_t * pcd)
++01078 {
++01079         gintmsk_data_t intr_mask = {.d32 = 0 };
++01080         gintsts_data_t gintsts;
++01081         DWC_PRINTF("INTERRUPT Handler not implemented for %s\n", "EOP");
++01082 
++01083         intr_mask.b.eopframe = 1;
++01084         dwc_modify_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk,
++01085                          intr_mask.d32, 0);
++01086 
++01087         /* Clear interrupt */
++01088         gintsts.d32 = 0;
++01089         gintsts.b.eopframe = 1;
++01090         dwc_write_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
++01091                         gintsts.d32);
++01092 
++01093         return 1;
++01094 }
++01095 
++01105 int32_t dwc_otg_pcd_handle_ep_mismatch_intr(dwc_otg_core_if_t * core_if)
++01106 {
++01107         gintsts_data_t gintsts;
++01108         DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, core_if);
++01109 
++01110         /* Clear interrupt */
++01111         gintsts.d32 = 0;
++01112         gintsts.b.epmismatch = 1;
++01113         dwc_write_reg32(&core_if->core_global_regs->gintsts, gintsts.d32);
++01114 
++01115         return 1;
++01116 }
++01117 
++01121 static inline void ep0_do_stall(dwc_otg_pcd_t * pcd, const int err_val)
++01122 {
++01123         dwc_otg_pcd_ep_t *ep0 = &pcd->ep0;
++01124         usb_device_request_t *ctrl = &pcd->setup_pkt->req;
++01125         DWC_WARN("req %02x.%02x protocol STALL; err %d\n",
++01126                  ctrl->bmRequestType, ctrl->bRequest, err_val);
++01127 
++01128         ep0->dwc_ep.is_in = 1;
++01129         dwc_otg_ep_set_stall(GET_CORE_IF(pcd), &ep0->dwc_ep);
++01130         pcd->ep0.stopped = 1;
++01131         pcd->ep0state = EP0_IDLE;
++01132         ep0_out_start(GET_CORE_IF(pcd), pcd);
++01133 }
++01134 
++01138 static inline void do_gadget_setup(dwc_otg_pcd_t * pcd,
++01139                                    usb_device_request_t * ctrl)
++01140 {
++01141         int ret = 0;
++01142         DWC_SPINUNLOCK(pcd->lock);
++01143         ret = pcd->fops->setup(pcd, (uint8_t *) ctrl);
++01144         DWC_SPINLOCK(pcd->lock);
++01145         if (ret < 0) {
++01146                 ep0_do_stall(pcd, ret);
++01147         }
++01148 
++01161         if (ret == 256 + 999) {
++01162                 pcd->request_config = 1;
++01163         }
++01164 }
++01165 
++01166 #ifdef DWC_UTE_CFI
++01167 
++01171 static inline int cfi_gadget_setup(dwc_otg_pcd_t * pcd,
++01172                                    struct cfi_usb_ctrlrequest *ctrl_req)
++01173 {
++01174         int ret = 0;
++01175 
++01176         if (pcd->fops && pcd->fops->cfi_setup) {
++01177                 DWC_SPINUNLOCK(pcd->lock);
++01178                 ret = pcd->fops->cfi_setup(pcd, ctrl_req);
++01179                 DWC_SPINLOCK(pcd->lock);
++01180                 if (ret < 0) {
++01181                         ep0_do_stall(pcd, ret);
++01182                         return ret;
++01183                 }
++01184         }
++01185 
++01186         return ret;
++01187 }
++01188 #endif
++01189 
++01194 static inline void do_setup_in_status_phase(dwc_otg_pcd_t * pcd)
++01195 {
++01196         dwc_otg_pcd_ep_t *ep0 = &pcd->ep0;
++01197         if (pcd->ep0state == EP0_STALL) {
++01198                 return;
++01199         }
++01200 
++01201         pcd->ep0state = EP0_IN_STATUS_PHASE;
++01202 
++01203         /* Prepare for more SETUP Packets */
++01204         DWC_DEBUGPL(DBG_PCD, "EP0 IN ZLP\n");
++01205         ep0->dwc_ep.xfer_len = 0;
++01206         ep0->dwc_ep.xfer_count = 0;
++01207         ep0->dwc_ep.is_in = 1;
++01208         ep0->dwc_ep.dma_addr = pcd->setup_pkt_dma_handle;
++01209         dwc_otg_ep0_start_transfer(GET_CORE_IF(pcd), &ep0->dwc_ep);
++01210 
++01211         /* Prepare for more SETUP Packets */
++01212         //ep0_out_start(GET_CORE_IF(pcd), pcd);
++01213 }
++01214 
++01219 static inline void do_setup_out_status_phase(dwc_otg_pcd_t * pcd)
++01220 {
++01221         dwc_otg_pcd_ep_t *ep0 = &pcd->ep0;
++01222         if (pcd->ep0state == EP0_STALL) {
++01223                 DWC_DEBUGPL(DBG_PCD, "EP0 STALLED\n");
++01224                 return;
++01225         }
++01226         pcd->ep0state = EP0_OUT_STATUS_PHASE;
++01227 
++01228         DWC_DEBUGPL(DBG_PCD, "EP0 OUT ZLP\n");
++01229         ep0->dwc_ep.xfer_len = 0;
++01230         ep0->dwc_ep.xfer_count = 0;
++01231         ep0->dwc_ep.is_in = 0;
++01232         ep0->dwc_ep.dma_addr = pcd->setup_pkt_dma_handle;
++01233         dwc_otg_ep0_start_transfer(GET_CORE_IF(pcd), &ep0->dwc_ep);
++01234 
++01235         /* Prepare for more SETUP Packets */
++01236         if (GET_CORE_IF(pcd)->dma_enable == 0) {
++01237                 ep0_out_start(GET_CORE_IF(pcd), pcd);
++01238         }
++01239 }
++01240 
++01245 static inline void pcd_clear_halt(dwc_otg_pcd_t * pcd, dwc_otg_pcd_ep_t * ep)
++01246 {
++01247         if (ep->dwc_ep.stall_clear_flag == 0)
++01248                 dwc_otg_ep_clear_stall(GET_CORE_IF(pcd), &ep->dwc_ep);
++01249 
++01250         /* Reactive the EP */
++01251         dwc_otg_ep_activate(GET_CORE_IF(pcd), &ep->dwc_ep);
++01252         if (ep->stopped) {
++01253                 ep->stopped = 0;
++01254                 /* If there is a request in the EP queue start it */
++01255 
++01259                 /*
++01260                  * Above fixme is solved by implmenting a tasklet to call the
++01261                  * start_next_request(), outside of interrupt context at some
++01262                  * time after the current time, after a clear-halt setup packet.
++01263                  * Still need to implement ep mismatch in the future if a gadget
++01264                  * ever uses more than one endpoint at once
++01265                  */
++01266                 ep->queue_sof = 1;
++01267                 DWC_TASK_SCHEDULE(pcd->start_xfer_tasklet);
++01268         }
++01269         /* Start Control Status Phase */
++01270         do_setup_in_status_phase(pcd);
++01271 }
++01272 
++01284 void do_test_mode(void *data)
++01285 {
++01286         dctl_data_t dctl;
++01287         dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *) data;
++01288         dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
++01289         int test_mode = pcd->test_mode;
++01290 
++01291 //        DWC_WARN("%s() has not been tested since being rewritten!\n", __func__);
++01292 
++01293         dctl.d32 = dwc_read_reg32(&core_if->dev_if->dev_global_regs->dctl);
++01294         switch (test_mode) {
++01295         case 1:         // TEST_J
++01296                 dctl.b.tstctl = 1;
++01297                 break;
++01298 
++01299         case 2:         // TEST_K
++01300                 dctl.b.tstctl = 2;
++01301                 break;
++01302 
++01303         case 3:         // TEST_SE0_NAK
++01304                 dctl.b.tstctl = 3;
++01305                 break;
++01306 
++01307         case 4:         // TEST_PACKET
++01308                 dctl.b.tstctl = 4;
++01309                 break;
++01310 
++01311         case 5:         // TEST_FORCE_ENABLE
++01312                 dctl.b.tstctl = 5;
++01313                 break;
++01314         }
++01315         dwc_write_reg32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32);
++01316 }
++01317 
++01321 static inline void do_get_status(dwc_otg_pcd_t * pcd)
++01322 {
++01323         usb_device_request_t ctrl = pcd->setup_pkt->req;
++01324         dwc_otg_pcd_ep_t *ep;
++01325         dwc_otg_pcd_ep_t *ep0 = &pcd->ep0;
++01326         uint16_t *status = pcd->status_buf;
++01327 
++01328 #ifdef DEBUG_EP0
++01329         DWC_DEBUGPL(DBG_PCD,
++01330                     "GET_STATUS %02x.%02x v%04x i%04x l%04x\n",
++01331                     ctrl.bmRequestType, ctrl.bRequest,
++01332                     UGETW(ctrl.wValue), UGETW(ctrl.wIndex),
++01333                     UGETW(ctrl.wLength));
++01334 #endif
++01335 
++01336         switch (UT_GET_RECIPIENT(ctrl.bmRequestType)) {
++01337         case UT_DEVICE:
++01338                 *status = 0x1;  /* Self powered */
++01339                 *status |= pcd->remote_wakeup_enable << 1;
++01340                 break;
++01341 
++01342         case UT_INTERFACE:
++01343                 *status = 0;
++01344                 break;
++01345 
++01346         case UT_ENDPOINT:
++01347                 ep = get_ep_by_addr(pcd, UGETW(ctrl.wIndex));
++01348                 if (ep == 0 || UGETW(ctrl.wLength) > 2) {
++01349                         ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED);
++01350                         return;
++01351                 }
++01353                 *status = ep->stopped;
++01354                 break;
++01355         }
++01356         pcd->ep0_pending = 1;
++01357         ep0->dwc_ep.start_xfer_buff = (uint8_t *) status;
++01358         ep0->dwc_ep.xfer_buff = (uint8_t *) status;
++01359         ep0->dwc_ep.dma_addr = pcd->status_buf_dma_handle;
++01360         ep0->dwc_ep.xfer_len = 2;
++01361         ep0->dwc_ep.xfer_count = 0;
++01362         ep0->dwc_ep.total_len = ep0->dwc_ep.xfer_len;
++01363         dwc_otg_ep0_start_transfer(GET_CORE_IF(pcd), &ep0->dwc_ep);
++01364 }
++01365 
++01369 static inline void do_set_feature(dwc_otg_pcd_t * pcd)
++01370 {
++01371         dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
++01372         dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
++01373         usb_device_request_t ctrl = pcd->setup_pkt->req;
++01374         dwc_otg_pcd_ep_t *ep = 0;
++01375         int32_t otg_cap_param = core_if->core_params->otg_cap;
++01376         gotgctl_data_t gotgctl = {.d32 = 0 };
++01377 
++01378         DWC_DEBUGPL(DBG_PCD, "SET_FEATURE:%02x.%02x v%04x i%04x l%04x\n",
++01379                     ctrl.bmRequestType, ctrl.bRequest,
++01380                     UGETW(ctrl.wValue), UGETW(ctrl.wIndex),
++01381                     UGETW(ctrl.wLength));
++01382         DWC_DEBUGPL(DBG_PCD, "otg_cap=%d\n", otg_cap_param);
++01383 
++01384         switch (UT_GET_RECIPIENT(ctrl.bmRequestType)) {
++01385         case UT_DEVICE:
++01386                 switch (UGETW(ctrl.wValue)) {
++01387                 case UF_DEVICE_REMOTE_WAKEUP:
++01388                         pcd->remote_wakeup_enable = 1;
++01389                         break;
++01390 
++01391                 case UF_TEST_MODE:
++01392                         /* Setup the Test Mode tasklet to do the Test
++01393                          * Packet generation after the SETUP Status
++01394                          * phase has completed. */
++01395 
++01399                         pcd->test_mode = UGETW(ctrl.wIndex) >> 8;
++01400                         DWC_TASK_SCHEDULE(pcd->test_mode_tasklet);
++01401                         break;
++01402 
++01403                 case UF_DEVICE_B_HNP_ENABLE:
++01404                         DWC_DEBUGPL(DBG_PCDV,
++01405                                     "SET_FEATURE: USB_DEVICE_B_HNP_ENABLE\n");
++01406 
++01407                         /* dev may initiate HNP */
++01408                         if (otg_cap_param == DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE) {
++01409                                 pcd->b_hnp_enable = 1;
++01410                                 dwc_otg_pcd_update_otg(pcd, 0);
++01411                                 DWC_DEBUGPL(DBG_PCD, "Request B HNP\n");
++01414                                 gotgctl.b.devhnpen = 1;
++01415                                 gotgctl.b.hnpreq = 1;
++01416                                 dwc_write_reg32(&global_regs->gotgctl,
++01417                                                 gotgctl.d32);
++01418                         } else {
++01419                                 ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED);
++01420                         }
++01421                         break;
++01422 
++01423                 case UF_DEVICE_A_HNP_SUPPORT:
++01424                         /* RH port supports HNP */
++01425                         DWC_DEBUGPL(DBG_PCDV,
++01426                                     "SET_FEATURE: USB_DEVICE_A_HNP_SUPPORT\n");
++01427                         if (otg_cap_param == DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE) {
++01428                                 pcd->a_hnp_support = 1;
++01429                                 dwc_otg_pcd_update_otg(pcd, 0);
++01430                         } else {
++01431                                 ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED);
++01432                         }
++01433                         break;
++01434 
++01435                 case UF_DEVICE_A_ALT_HNP_SUPPORT:
++01436                         /* other RH port does */
++01437                         DWC_DEBUGPL(DBG_PCDV,
++01438                                     "SET_FEATURE: USB_DEVICE_A_ALT_HNP_SUPPORT\n");
++01439                         if (otg_cap_param == DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE) {
++01440                                 pcd->a_alt_hnp_support = 1;
++01441                                 dwc_otg_pcd_update_otg(pcd, 0);
++01442                         } else {
++01443                                 ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED);
++01444                         }
++01445                         break;
++01446                 }
++01447                 do_setup_in_status_phase(pcd);
++01448                 break;
++01449 
++01450         case UT_INTERFACE:
++01451                 do_gadget_setup(pcd, &ctrl);
++01452                 break;
++01453 
++01454         case UT_ENDPOINT:
++01455                 if (UGETW(ctrl.wValue) == UF_ENDPOINT_HALT) {
++01456                         ep = get_ep_by_addr(pcd, UGETW(ctrl.wIndex));
++01457                         if (ep == 0) {
++01458                                 ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED);
++01459                                 return;
++01460                         }
++01461                         ep->stopped = 1;
++01462                         dwc_otg_ep_set_stall(core_if, &ep->dwc_ep);
++01463                 }
++01464                 do_setup_in_status_phase(pcd);
++01465                 break;
++01466         }
++01467 }
++01468 
++01472 static inline void do_clear_feature(dwc_otg_pcd_t * pcd)
++01473 {
++01474         usb_device_request_t ctrl = pcd->setup_pkt->req;
++01475         dwc_otg_pcd_ep_t *ep = 0;
++01476 
++01477         DWC_DEBUGPL(DBG_PCD,
++01478                     "CLEAR_FEATURE:%02x.%02x v%04x i%04x l%04x\n",
++01479                     ctrl.bmRequestType, ctrl.bRequest,
++01480                     UGETW(ctrl.wValue), UGETW(ctrl.wIndex),
++01481                     UGETW(ctrl.wLength));
++01482 
++01483         switch (UT_GET_RECIPIENT(ctrl.bmRequestType)) {
++01484         case UT_DEVICE:
++01485                 switch (UGETW(ctrl.wValue)) {
++01486                 case UF_DEVICE_REMOTE_WAKEUP:
++01487                         pcd->remote_wakeup_enable = 0;
++01488                         break;
++01489 
++01490                 case UF_TEST_MODE:
++01492                         break;
++01493                 }
++01494                 do_setup_in_status_phase(pcd);
++01495                 break;
++01496 
++01497         case UT_ENDPOINT:
++01498                 ep = get_ep_by_addr(pcd, UGETW(ctrl.wIndex));
++01499                 if (ep == 0) {
++01500                         ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED);
++01501                         return;
++01502                 }
++01503 
++01504                 pcd_clear_halt(pcd, ep);
++01505 
++01506                 break;
++01507         }
++01508 }
++01509 
++01513 static inline void do_set_address(dwc_otg_pcd_t * pcd)
++01514 {
++01515         dwc_otg_dev_if_t *dev_if = GET_CORE_IF(pcd)->dev_if;
++01516         usb_device_request_t ctrl = pcd->setup_pkt->req;
++01517 
++01518         if (ctrl.bmRequestType == UT_DEVICE) {
++01519                 dcfg_data_t dcfg = {.d32 = 0 };
++01520 
++01521 #ifdef DEBUG_EP0
++01522 //                      DWC_DEBUGPL(DBG_PCDV, "SET_ADDRESS:%d\n", ctrl.wValue);
++01523 #endif
++01524                 dcfg.b.devaddr = UGETW(ctrl.wValue);
++01525                 dwc_modify_reg32(&dev_if->dev_global_regs->dcfg, 0, dcfg.d32);
++01526                 do_setup_in_status_phase(pcd);
++01527         }
++01528 }
++01529 
++01580 static inline void pcd_setup(dwc_otg_pcd_t * pcd)
++01581 {
++01582         dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
++01583         dwc_otg_dev_if_t *dev_if = core_if->dev_if;
++01584         usb_device_request_t ctrl = pcd->setup_pkt->req;
++01585         dwc_otg_pcd_ep_t *ep0 = &pcd->ep0;
++01586 
++01587         deptsiz0_data_t doeptsize0 = {.d32 = 0 };
++01588 
++01589 #ifdef DWC_UTE_CFI
++01590         int retval = 0;
++01591         struct cfi_usb_ctrlrequest cfi_req;
++01592 #endif
++01593 
++01594 #ifdef DEBUG_EP0
++01595         DWC_DEBUGPL(DBG_PCD, "SETUP %02x.%02x v%04x i%04x l%04x\n",
++01596                     ctrl.bmRequestType, ctrl.bRequest,
++01597                     UGETW(ctrl.wValue), UGETW(ctrl.wIndex),
++01598                     UGETW(ctrl.wLength));
++01599 #endif
++01600 
++01601         doeptsize0.d32 = dwc_read_reg32(&dev_if->out_ep_regs[0]->doeptsiz);
++01602 
++01605         if (core_if->dma_enable && core_if->dma_desc_enable == 0
++01606             && (doeptsize0.b.supcnt < 2)) {
++01607                 DWC_ERROR
++01608                     ("\n\n-----------    CANNOT handle > 1 setup packet in DMA mode\n\n");
++01609         }
++01610 
++01611         /* Clean up the request queue */
++01612         dwc_otg_request_nuke(ep0);
++01613         ep0->stopped = 0;
++01614 
++01615         if (ctrl.bmRequestType & UE_DIR_IN) {
++01616                 ep0->dwc_ep.is_in = 1;
++01617                 pcd->ep0state = EP0_IN_DATA_PHASE;
++01618         } else {
++01619                 ep0->dwc_ep.is_in = 0;
++01620                 pcd->ep0state = EP0_OUT_DATA_PHASE;
++01621         }
++01622 
++01623         if (UGETW(ctrl.wLength) == 0) {
++01624                 ep0->dwc_ep.is_in = 1;
++01625                 pcd->ep0state = EP0_IN_STATUS_PHASE;
++01626         }
++01627 
++01628         if (UT_GET_TYPE(ctrl.bmRequestType) != UT_STANDARD) {
++01629 
++01630 #ifdef DWC_UTE_CFI
++01631                 DWC_MEMCPY(&cfi_req, &ctrl, sizeof(usb_device_request_t));
++01632 
++01633                 //printk(KERN_ALERT "CFI: req_type=0x%02x; req=0x%02x\n", ctrl.bRequestType, ctrl.bRequest);
++01634                 if (UT_GET_TYPE(cfi_req.bRequestType) == UT_VENDOR) {
++01635                         if (cfi_req.bRequest > 0xB0 && cfi_req.bRequest < 0xBF) {
++01636                                 retval = cfi_setup(pcd, &cfi_req);
++01637                                 if (retval < 0) {
++01638                                         ep0_do_stall(pcd, retval);
++01639                                         pcd->ep0_pending = 0;
++01640                                         return;
++01641                                 }
++01642 
++01643                                 /* if need gadget setup then call it and check the retval */
++01644                                 if (pcd->cfi->need_gadget_att) {
++01645                                         retval =
++01646                                             cfi_gadget_setup(pcd,
++01647                                                              &pcd->cfi->
++01648                                                              ctrl_req);
++01649                                         if (retval < 0) {
++01650                                                 pcd->ep0_pending = 0;
++01651                                                 return;
++01652                                         }
++01653                                 }
++01654 
++01655                                 if (pcd->cfi->need_status_in_complete) {
++01656                                         do_setup_in_status_phase(pcd);
++01657                                 }
++01658                                 return;
++01659                         }
++01660                 }
++01661 #endif
++01662 
++01663                 /* handle non-standard (class/vendor) requests in the gadget driver */
++01664                 do_gadget_setup(pcd, &ctrl);
++01665                 return;
++01666         }
++01667 
++01670 
++01671 
++01672 
++01673         switch (ctrl.bRequest) {
++01674         case UR_GET_STATUS:
++01675                 do_get_status(pcd);
++01676                 break;
++01677 
++01678         case UR_CLEAR_FEATURE:
++01679                 do_clear_feature(pcd);
++01680                 break;
++01681 
++01682         case UR_SET_FEATURE:
++01683                 do_set_feature(pcd);
++01684                 break;
++01685 
++01686         case UR_SET_ADDRESS:
++01687                 do_set_address(pcd);
++01688                 break;
++01689 
++01690         case UR_SET_INTERFACE:
++01691         case UR_SET_CONFIG:
++01692 //              _pcd->request_config = 1;       /* Configuration changed */
++01693                 do_gadget_setup(pcd, &ctrl);
++01694                 break;
++01695 
++01696         case UR_SYNCH_FRAME:
++01697                 do_gadget_setup(pcd, &ctrl);
++01698                 break;
++01699 
++01700         default:
++01701                 /* Call the Gadget Driver's setup functions */
++01702                 do_gadget_setup(pcd, &ctrl);
++01703                 break;
++01704         }
++01705 }
++01706 
++01710 static int32_t ep0_complete_request(dwc_otg_pcd_ep_t * ep)
++01711 {
++01712         dwc_otg_core_if_t *core_if = GET_CORE_IF(ep->pcd);
++01713         dwc_otg_dev_if_t *dev_if = core_if->dev_if;
++01714         dwc_otg_dev_in_ep_regs_t *in_ep_regs =
++01715             dev_if->in_ep_regs[ep->dwc_ep.num];
++01716 #ifdef DEBUG_EP0
++01717         dwc_otg_dev_out_ep_regs_t *out_ep_regs =
++01718             dev_if->out_ep_regs[ep->dwc_ep.num];
++01719 #endif
++01720         deptsiz0_data_t deptsiz;
++01721         dev_dma_desc_sts_t desc_sts;
++01722         dwc_otg_pcd_request_t *req;
++01723         int is_last = 0;
++01724         dwc_otg_pcd_t *pcd = ep->pcd;
++01725 
++01726 #ifdef DWC_UTE_CFI
++01727         struct cfi_usb_ctrlrequest *ctrlreq;
++01728         int retval = -DWC_E_NOT_SUPPORTED;
++01729 #endif
++01730 
++01731         if (pcd->ep0_pending && DWC_CIRCLEQ_EMPTY(&ep->queue)) {
++01732                 if (ep->dwc_ep.is_in) {
++01733 #ifdef DEBUG_EP0
++01734                         DWC_DEBUGPL(DBG_PCDV, "Do setup OUT status phase\n");
++01735 #endif
++01736                         do_setup_out_status_phase(pcd);
++01737                 } else {
++01738 #ifdef DEBUG_EP0
++01739                         DWC_DEBUGPL(DBG_PCDV, "Do setup IN status phase\n");
++01740 #endif
++01741 
++01742 #ifdef DWC_UTE_CFI
++01743                         ctrlreq = &pcd->cfi->ctrl_req;
++01744 
++01745                         if (UT_GET_TYPE(ctrlreq->bRequestType) == UT_VENDOR) {
++01746                                 if (ctrlreq->bRequest > 0xB0
++01747                                     && ctrlreq->bRequest < 0xBF) {
++01748 
++01749                                         /* Return if the PCD failed to handle the request */
++01750                                         if ((retval =
++01751                                              pcd->cfi->ops.
++01752                                              ctrl_write_complete(pcd->cfi,
++01753                                                                  pcd)) < 0) {
++01754                                                 CFI_INFO
++01755                                                     ("ERROR setting a new value in the PCD(%d)\n",
++01756                                                      retval);
++01757                                                 ep0_do_stall(pcd, retval);
++01758                                                 pcd->ep0_pending = 0;
++01759                                                 return 0;
++01760                                         }
++01761 
++01762                                         /* If the gadget needs to be notified on the request */
++01763                                         if (pcd->cfi->need_gadget_att == 1) {
++01764                                                 //retval = do_gadget_setup(pcd, &pcd->cfi->ctrl_req);
++01765                                                 retval =
++01766                                                     cfi_gadget_setup(pcd,
++01767                                                                      &pcd->cfi->
++01768                                                                      ctrl_req);
++01769 
++01770                                                 /* Return from the function if the gadget failed to process
++01771                                                  * the request properly - this should never happen !!!
++01772                                                  */
++01773                                                 if (retval < 0) {
++01774                                                         CFI_INFO
++01775                                                             ("ERROR setting a new value in the gadget(%d)\n",
++01776                                                              retval);
++01777                                                         pcd->ep0_pending = 0;
++01778                                                         return 0;
++01779                                                 }
++01780                                         }
++01781 
++01782                                         CFI_INFO("%s: RETVAL=%d\n", __func__,
++01783                                                  retval);
++01784                                         /* If we hit here then the PCD and the gadget has properly
++01785                                          * handled the request - so send the ZLP IN to the host.
++01786                                          */
++01787                                         /* @todo: MAS - decide whether we need to start the setup
++01788                                          * stage based on the need_setup value of the cfi object
++01789                                          */
++01790                                         do_setup_in_status_phase(pcd);
++01791                                         pcd->ep0_pending = 0;
++01792                                         return 1;
++01793                                 }
++01794                         }
++01795 #endif
++01796 
++01797                         do_setup_in_status_phase(pcd);
++01798                 }
++01799                 pcd->ep0_pending = 0;
++01800                 return 1;
++01801         }
++01802 
++01803         if (DWC_CIRCLEQ_EMPTY(&ep->queue)) {
++01804                 return 0;
++01805         }
++01806         req = DWC_CIRCLEQ_FIRST(&ep->queue);
++01807 
++01808         if (pcd->ep0state == EP0_OUT_STATUS_PHASE
++01809             || pcd->ep0state == EP0_IN_STATUS_PHASE) {
++01810                 is_last = 1;
++01811         } else if (ep->dwc_ep.is_in) {
++01812                 deptsiz.d32 = dwc_read_reg32(&in_ep_regs->dieptsiz);
++01813                 if (core_if->dma_desc_enable != 0)
++01814                         desc_sts = dev_if->in_desc_addr->status;
++01815 #ifdef DEBUG_EP0
++01816                 DWC_DEBUGPL(DBG_PCDV, "%d len=%d  xfersize=%d pktcnt=%d\n",
++01817                             ep->dwc_ep.num, ep->dwc_ep.xfer_len,
++01818                             deptsiz.b.xfersize, deptsiz.b.pktcnt);
++01819 #endif
++01820 
++01821                 if (((core_if->dma_desc_enable == 0)
++01822                      && (deptsiz.b.xfersize == 0))
++01823                     || ((core_if->dma_desc_enable != 0)
++01824                         && (desc_sts.b.bytes == 0))) {
++01825                         req->actual = ep->dwc_ep.xfer_count;
++01826                         /* Is a Zero Len Packet needed? */
++01827                         if (req->sent_zlp) {
++01828 #ifdef DEBUG_EP0
++01829                                 DWC_DEBUGPL(DBG_PCD, "Setup Rx ZLP\n");
++01830 #endif
++01831                                 req->sent_zlp = 0;
++01832                         }
++01833                         do_setup_out_status_phase(pcd);
++01834                 }
++01835         } else {
++01836                 /* ep0-OUT */
++01837 #ifdef DEBUG_EP0
++01838                 deptsiz.d32 = dwc_read_reg32(&out_ep_regs->doeptsiz);
++01839                 DWC_DEBUGPL(DBG_PCDV, "%d len=%d xsize=%d pktcnt=%d\n",
++01840                             ep->dwc_ep.num, ep->dwc_ep.xfer_len,
++01841                             deptsiz.b.xfersize, deptsiz.b.pktcnt);
++01842 #endif
++01843                 req->actual = ep->dwc_ep.xfer_count;
++01844 
++01845                 /* Is a Zero Len Packet needed? */
++01846                 if (req->sent_zlp) {
++01847 #ifdef DEBUG_EP0
++01848                         DWC_DEBUGPL(DBG_PCDV, "Setup Tx ZLP\n");
++01849 #endif
++01850                         req->sent_zlp = 0;
++01851                 }
++01852                 if (core_if->dma_desc_enable == 0)
++01853                         do_setup_in_status_phase(pcd);
++01854         }
++01855 
++01856         /* Complete the request */
++01857         if (is_last) {
++01858                 dwc_otg_request_done(ep, req, 0);
++01859                 ep->dwc_ep.start_xfer_buff = 0;
++01860                 ep->dwc_ep.xfer_buff = 0;
++01861                 ep->dwc_ep.xfer_len = 0;
++01862                 return 1;
++01863         }
++01864         return 0;
++01865 }
++01866 
++01867 #ifdef DWC_UTE_CFI
++01868 
++01874 static inline int cfi_calc_desc_residue(dwc_otg_pcd_ep_t * ep)
++01875 {
++01876         int32_t ret = 0;
++01877         int i;
++01878         struct dwc_otg_dma_desc *ddesc = NULL;
++01879         struct cfi_ep *cfiep;
++01880 
++01881         /* See if the pcd_ep has its respective cfi_ep mapped */
++01882         cfiep = get_cfi_ep_by_pcd_ep(ep->pcd->cfi, ep);
++01883         if (!cfiep) {
++01884                 CFI_INFO("%s: Failed to find ep\n", __func__);
++01885                 return -1;
++01886         }
++01887 
++01888         ddesc = ep->dwc_ep.descs;
++01889 
++01890         for (i = 0; (i < cfiep->desc_count) && (i < MAX_DMA_DESCS_PER_EP); i++) {
++01891 
++01892 #if defined(PRINT_CFI_DMA_DESCS)
++01893                 print_desc(ddesc, ep->ep.name, i);
++01894 #endif
++01895                 ret += ddesc->status.b.bytes;
++01896                 ddesc++;
++01897         }
++01898 
++01899         if (ret)
++01900                 CFI_INFO("!!!!!!!!!! WARNING (%s) - residue=%d\n", __func__,
++01901                          ret);
++01902 
++01903         return ret;
++01904 }
++01905 #endif
++01906 
++01911 static void complete_ep(dwc_otg_pcd_ep_t * ep)
++01912 {
++01913         dwc_otg_core_if_t *core_if = GET_CORE_IF(ep->pcd);
++01914         dwc_otg_dev_if_t *dev_if = core_if->dev_if;
++01915         dwc_otg_dev_in_ep_regs_t *in_ep_regs =
++01916             dev_if->in_ep_regs[ep->dwc_ep.num];
++01917         deptsiz_data_t deptsiz;
++01918         dev_dma_desc_sts_t desc_sts;
++01919         dwc_otg_pcd_request_t *req = 0;
++01920         dwc_otg_dev_dma_desc_t *dma_desc;
++01921         uint32_t byte_count = 0;
++01922         int is_last = 0;
++01923         int i;
++01924 
++01925         DWC_DEBUGPL(DBG_PCDV, "%s() %d-%s\n", __func__, ep->dwc_ep.num,
++01926                     (ep->dwc_ep.is_in ? "IN" : "OUT"));
++01927 
++01928         /* Get any pending requests */
++01929         if (!DWC_CIRCLEQ_EMPTY(&ep->queue)) {
++01930                 req = DWC_CIRCLEQ_FIRST(&ep->queue);
++01931                 if (!req) {
++01932                         DWC_PRINTF("complete_ep 0x%p, req = NULL!\n", ep);
++01933                         return;
++01934                 }
++01935         } else {
++01936                 DWC_PRINTF("complete_ep 0x%p, ep->queue empty!\n", ep);
++01937                 return;
++01938         }
++01939 
++01940         DWC_DEBUGPL(DBG_PCD, "Requests %d\n", ep->pcd->request_pending);
++01941 
++01942         if (ep->dwc_ep.is_in) {
++01943                 deptsiz.d32 = dwc_read_reg32(&in_ep_regs->dieptsiz);
++01944 
++01945                 if (core_if->dma_enable) {
++01946                         if (core_if->dma_desc_enable == 0) {
++01947                                 if (deptsiz.b.xfersize == 0
++01948                                     && deptsiz.b.pktcnt == 0) {
++01949                                         byte_count =
++01950                                             ep->dwc_ep.xfer_len -
++01951                                             ep->dwc_ep.xfer_count;
++01952 
++01953                                         ep->dwc_ep.xfer_buff += byte_count;
++01954                                         ep->dwc_ep.dma_addr += byte_count;
++01955                                         ep->dwc_ep.xfer_count += byte_count;
++01956 
++01957                                         DWC_DEBUGPL(DBG_PCDV,
++01958                                                     "%d-%s len=%d  xfersize=%d pktcnt=%d\n",
++01959                                                     ep->dwc_ep.num,
++01960                                                     (ep->dwc_ep.
++01961                                                      is_in ? "IN" : "OUT"),
++01962                                                     ep->dwc_ep.xfer_len,
++01963                                                     deptsiz.b.xfersize,
++01964                                                     deptsiz.b.pktcnt);
++01965 
++01966                                         if (ep->dwc_ep.xfer_len <
++01967                                             ep->dwc_ep.total_len) {
++01968                                                 dwc_otg_ep_start_transfer
++01969                                                     (core_if, &ep->dwc_ep);
++01970                                         } else if (ep->dwc_ep.sent_zlp) {
++01971                                                 /*      
++01972                                                  * This fragment of code should initiate 0 
++01973                                                  * length trasfer in case if it is queued
++01974                                                  * a trasfer with size divisible to EPs max 
++01975                                                  * packet size and with usb_request zero field 
++01976                                                  * is set, which means that after data is transfered, 
++01977                                                  * it is also should be transfered 
++01978                                                  * a 0 length packet at the end. For Slave and 
++01979                                                  * Buffer DMA modes in this case SW has 
++01980                                                  * to initiate 2 transfers one with transfer size, 
++01981                                                  * and the second with 0 size. For Desriptor 
++01982                                                  * DMA mode SW is able to initiate a transfer, 
++01983                                                  * which will handle all the packets including 
++01984                                                  * the last  0 legth.
++01985                                                  */
++01986                                                 ep->dwc_ep.sent_zlp = 0;
++01987                                                 dwc_otg_ep_start_zl_transfer
++01988                                                     (core_if, &ep->dwc_ep);
++01989                                         } else {
++01990                                                 is_last = 1;
++01991                                         }
++01992                                 } else {
++01993                                         DWC_WARN
++01994                                             ("Incomplete transfer (%d - %s [siz=%d pkt=%d])\n",
++01995                                              ep->dwc_ep.num,
++01996                                              (ep->dwc_ep.is_in ? "IN" : "OUT"),
++01997                                              deptsiz.b.xfersize,
++01998                                              deptsiz.b.pktcnt);
++01999                                 }
++02000                         } else {
++02001                                 dma_desc = ep->dwc_ep.desc_addr;
++02002                                 byte_count = 0;
++02003                                 ep->dwc_ep.sent_zlp = 0;
++02004 
++02005 #ifdef DWC_UTE_CFI
++02006                                 CFI_INFO("%s: BUFFER_MODE=%d\n", __func__,
++02007                                          ep->dwc_ep.buff_mode);
++02008                                 if (ep->dwc_ep.buff_mode != BM_STANDARD) {
++02009                                         int residue;
++02010 
++02011                                         residue = cfi_calc_desc_residue(ep);
++02012                                         if (residue < 0)
++02013                                                 return;
++02014 
++02015                                         byte_count = residue;
++02016                                 } else {
++02017 #endif
++02018                                         for (i = 0; i < ep->dwc_ep.desc_cnt;
++02019                                              ++i) {
++02020                                         desc_sts = dma_desc->status;
++02021                                         byte_count += desc_sts.b.bytes;
++02022                                         dma_desc++;
++02023                                 }
++02024 #ifdef DWC_UTE_CFI
++02025                                 }
++02026 #endif
++02027                                 if (byte_count == 0) {
++02028                                         ep->dwc_ep.xfer_count =
++02029                                             ep->dwc_ep.total_len;
++02030                                         is_last = 1;
++02031                                 } else {
++02032                                         DWC_WARN("Incomplete transfer\n");
++02033                                 }
++02034                         }
++02035                 } else {
++02036                         if (deptsiz.b.xfersize == 0 && deptsiz.b.pktcnt == 0) {
++02037                                 DWC_DEBUGPL(DBG_PCDV,
++02038                                             "%d-%s len=%d  xfersize=%d pktcnt=%d\n",
++02039                                             ep->dwc_ep.num,
++02040                                             ep->dwc_ep.is_in ? "IN" : "OUT",
++02041                                             ep->dwc_ep.xfer_len,
++02042                                             deptsiz.b.xfersize,
++02043                                             deptsiz.b.pktcnt);
++02044 
++02045                                 /*      Check if the whole transfer was completed,  
++02046                                  *      if no, setup transfer for next portion of data
++02047                                  */
++02048                                 if (ep->dwc_ep.xfer_len < ep->dwc_ep.total_len) {
++02049                                         dwc_otg_ep_start_transfer(core_if,
++02050                                                                   &ep->dwc_ep);
++02051                                 } else if (ep->dwc_ep.sent_zlp) {
++02052                                         /*      
++02053                                          * This fragment of code should initiate 0 
++02054                                          * length trasfer in case if it is queued
++02055                                          * a trasfer with size divisible to EPs max 
++02056                                          * packet size and with usb_request zero field 
++02057                                          * is set, which means that after data is transfered, 
++02058                                          * it is also should be transfered 
++02059                                          * a 0 length packet at the end. For Slave and 
++02060                                          * Buffer DMA modes in this case SW has 
++02061                                          * to initiate 2 transfers one with transfer size, 
++02062                                          * and the second with 0 size. For Desriptor 
++02063                                          * DMA mode SW is able to initiate a transfer, 
++02064                                          * which will handle all the packets including 
++02065                                          * the last  0 legth.
++02066                                          */
++02067                                         ep->dwc_ep.sent_zlp = 0;
++02068                                         dwc_otg_ep_start_zl_transfer(core_if,
++02069                                                                      &ep->
++02070                                                                      dwc_ep);
++02071                                 } else {
++02072                                         is_last = 1;
++02073                                 }
++02074                         } else {
++02075                                 DWC_WARN
++02076                                     ("Incomplete transfer (%d-%s [siz=%d pkt=%d])\n",
++02077                                      ep->dwc_ep.num,
++02078                                      (ep->dwc_ep.is_in ? "IN" : "OUT"),
++02079                                      deptsiz.b.xfersize, deptsiz.b.pktcnt);
++02080                         }
++02081                 }
++02082         } else {
++02083                 dwc_otg_dev_out_ep_regs_t *out_ep_regs =
++02084                     dev_if->out_ep_regs[ep->dwc_ep.num];
++02085                 desc_sts.d32 = 0;
++02086                 if (core_if->dma_enable) {
++02087                         if (core_if->dma_desc_enable) {
++02088                                 dma_desc = ep->dwc_ep.desc_addr;
++02089                                 byte_count = 0;
++02090                                 ep->dwc_ep.sent_zlp = 0;
++02091 
++02092 #ifdef DWC_UTE_CFI
++02093                                 CFI_INFO("%s: BUFFER_MODE=%d\n", __func__,
++02094                                          ep->dwc_ep.buff_mode);
++02095                                 if (ep->dwc_ep.buff_mode != BM_STANDARD) {
++02096                                         int residue;
++02097                                         residue = cfi_calc_desc_residue(ep);
++02098                                         if (residue < 0)
++02099                                                 return;
++02100                                         byte_count = residue;
++02101                                 } else {
++02102 #endif
++02103 
++02104                                         for (i = 0; i < ep->dwc_ep.desc_cnt;
++02105                                              ++i) {
++02106                                         desc_sts = dma_desc->status;
++02107                                         byte_count += desc_sts.b.bytes;
++02108                                         dma_desc++;
++02109                                 }
++02110 
++02111 #ifdef DWC_UTE_CFI
++02112                                 }
++02113 #endif
++02114                                 ep->dwc_ep.xfer_count = ep->dwc_ep.total_len
++02115                                     - byte_count +
++02116                                     ((4 - (ep->dwc_ep.total_len & 0x3)) & 0x3);
++02117                                 is_last = 1;
++02118                         } else {
++02119                                 deptsiz.d32 = 0;
++02120                                 deptsiz.d32 =
++02121                                     dwc_read_reg32(&out_ep_regs->doeptsiz);
++02122 
++02123                                 byte_count = (ep->dwc_ep.xfer_len -
++02124                                               ep->dwc_ep.xfer_count -
++02125                                               deptsiz.b.xfersize);
++02126                                 ep->dwc_ep.xfer_buff += byte_count;
++02127                                 ep->dwc_ep.dma_addr += byte_count;
++02128                                 ep->dwc_ep.xfer_count += byte_count;
++02129 
++02130                                 /*      Check if the whole transfer was completed,  
++02131                                  *      if no, setup transfer for next portion of data
++02132                                  */
++02133                                 if (ep->dwc_ep.xfer_len < ep->dwc_ep.total_len) {
++02134                                         dwc_otg_ep_start_transfer(core_if,
++02135                                                                   &ep->dwc_ep);
++02136                                 } else if (ep->dwc_ep.sent_zlp) {
++02137                                         /*      
++02138                                          * This fragment of code should initiate 0 
++02139                                          * length trasfer in case if it is queued
++02140                                          * a trasfer with size divisible to EPs max 
++02141                                          * packet size and with usb_request zero field 
++02142                                          * is set, which means that after data is transfered, 
++02143                                          * it is also should be transfered 
++02144                                          * a 0 length packet at the end. For Slave and 
++02145                                          * Buffer DMA modes in this case SW has 
++02146                                          * to initiate 2 transfers one with transfer size, 
++02147                                          * and the second with 0 size. For Desriptor 
++02148                                          * DMA mode SW is able to initiate a transfer, 
++02149                                          * which will handle all the packets including 
++02150                                          * the last  0 legth.
++02151                                          */
++02152                                         ep->dwc_ep.sent_zlp = 0;
++02153                                         dwc_otg_ep_start_zl_transfer(core_if,
++02154                                                                      &ep->
++02155                                                                      dwc_ep);
++02156                                 } else {
++02157                                         is_last = 1;
++02158                                 }
++02159                         }
++02160                 } else {
++02161                         /*      Check if the whole transfer was completed,  
++02162                          *      if no, setup transfer for next portion of data
++02163                          */
++02164                         if (ep->dwc_ep.xfer_len < ep->dwc_ep.total_len) {
++02165                                 dwc_otg_ep_start_transfer(core_if, &ep->dwc_ep);
++02166                         } else if (ep->dwc_ep.sent_zlp) {
++02167                                 /*      
++02168                                  * This fragment of code should initiate 0 
++02169                                  * length trasfer in case if it is queued
++02170                                  * a trasfer with size divisible to EPs max 
++02171                                  * packet size and with usb_request zero field 
++02172                                  * is set, which means that after data is transfered, 
++02173                                  * it is also should be transfered 
++02174                                  * a 0 length packet at the end. For Slave and 
++02175                                  * Buffer DMA modes in this case SW has 
++02176                                  * to initiate 2 transfers one with transfer size, 
++02177                                  * and the second with 0 size. For Desriptor 
++02178                                  * DMA mode SW is able to initiate a transfer, 
++02179                                  * which will handle all the packets including 
++02180                                  * the last  0 legth.
++02181                                  */
++02182                                 ep->dwc_ep.sent_zlp = 0;
++02183                                 dwc_otg_ep_start_zl_transfer(core_if,
++02184                                                              &ep->dwc_ep);
++02185                         } else {
++02186                                 is_last = 1;
++02187                         }
++02188                 }
++02189 
++02190                 DWC_DEBUGPL(DBG_PCDV,
++02191                             "addr %p,    %d-%s len=%d cnt=%d xsize=%d pktcnt=%d\n",
++02192                             &out_ep_regs->doeptsiz, ep->dwc_ep.num,
++02193                             ep->dwc_ep.is_in ? "IN" : "OUT",
++02194                             ep->dwc_ep.xfer_len, ep->dwc_ep.xfer_count,
++02195                             deptsiz.b.xfersize, deptsiz.b.pktcnt);
++02196         }
++02197 
++02198         /* Complete the request */
++02199         if (is_last) {
++02200 #ifdef DWC_UTE_CFI
++02201                 if (ep->dwc_ep.buff_mode != BM_STANDARD) {
++02202                         req->actual = ep->dwc_ep.cfi_req_len - byte_count;
++02203                 } else {
++02204 #endif
++02205                 req->actual = ep->dwc_ep.xfer_count;
++02206 #ifdef DWC_UTE_CFI
++02207                 }
++02208 #endif
++02209 
++02210                 dwc_otg_request_done(ep, req, 0);
++02211 
++02212                 ep->dwc_ep.start_xfer_buff = 0;
++02213                 ep->dwc_ep.xfer_buff = 0;
++02214                 ep->dwc_ep.xfer_len = 0;
++02215 
++02216                 /* If there is a request in the queue start it. */
++02217                 start_next_request(ep);
++02218         }
++02219 }
++02220 
++02221 #ifdef DWC_EN_ISOC
++02222 
++02227 static void dwc_otg_pcd_handle_iso_bna(dwc_otg_pcd_ep_t * ep)
++02228 {
++02229         dwc_ep_t *dwc_ep = &ep->dwc_ep;
++02230         volatile uint32_t *addr;
++02231         depctl_data_t depctl = {.d32 = 0 };
++02232         dwc_otg_pcd_t *pcd = ep->pcd;
++02233         dwc_otg_dev_dma_desc_t *dma_desc;
++02234         int i;
++02235 
++02236         dma_desc =
++02237             dwc_ep->iso_desc_addr + dwc_ep->desc_cnt * (dwc_ep->proc_buf_num);
++02238 
++02239         if (dwc_ep->is_in) {
++02240                 dev_dma_desc_sts_t sts = {.d32 = 0 };
++02241                 for (i = 0; i < dwc_ep->desc_cnt; ++i, ++dma_desc) {
++02242                         sts.d32 = dma_desc->status.d32;
++02243                         sts.b_iso_in.bs = BS_HOST_READY;
++02244                         dma_desc->status.d32 = sts.d32;
++02245                 }
++02246         } else {
++02247                 dev_dma_desc_sts_t sts = {.d32 = 0 };
++02248                 for (i = 0; i < dwc_ep->desc_cnt; ++i, ++dma_desc) {
++02249                         sts.d32 = dma_desc->status.d32;
++02250                         sts.b_iso_out.bs = BS_HOST_READY;
++02251                         dma_desc->status.d32 = sts.d32;
++02252                 }
++02253         }
++02254 
++02255         if (dwc_ep->is_in == 0) {
++02256                 addr =
++02257                     &GET_CORE_IF(pcd)->dev_if->out_ep_regs[dwc_ep->num]->
++02258                     doepctl;
++02259         } else {
++02260                 addr =
++02261                     &GET_CORE_IF(pcd)->dev_if->in_ep_regs[dwc_ep->num]->diepctl;
++02262         }
++02263         depctl.b.epena = 1;
++02264         dwc_modify_reg32(addr, depctl.d32, depctl.d32);
++02265 }
++02266 
++02274 void set_current_pkt_info(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
++02275 {
++02276         deptsiz_data_t deptsiz = {.d32 = 0 };
++02277         dma_addr_t dma_addr;
++02278         uint32_t offset;
++02279 
++02280         if (ep->proc_buf_num)
++02281                 dma_addr = ep->dma_addr1;
++02282         else
++02283                 dma_addr = ep->dma_addr0;
++02284 
++02285         if (ep->is_in) {
++02286                 deptsiz.d32 =
++02287                     dwc_read_reg32(&core_if->dev_if->in_ep_regs[ep->num]->
++02288                                    dieptsiz);
++02289                 offset = ep->data_per_frame;
++02290         } else {
++02291                 deptsiz.d32 =
++02292                     dwc_read_reg32(&core_if->dev_if->out_ep_regs[ep->num]->
++02293                                    doeptsiz);
++02294                 offset =
++02295                     ep->data_per_frame +
++02296                     (0x4 & (0x4 - (ep->data_per_frame & 0x3)));
++02297         }
++02298 
++02299         if (!deptsiz.b.xfersize) {
++02300                 ep->pkt_info[ep->cur_pkt].length = ep->data_per_frame;
++02301                 ep->pkt_info[ep->cur_pkt].offset =
++02302                     ep->cur_pkt_dma_addr - dma_addr;
++02303                 ep->pkt_info[ep->cur_pkt].status = 0;
++02304         } else {
++02305                 ep->pkt_info[ep->cur_pkt].length = ep->data_per_frame;
++02306                 ep->pkt_info[ep->cur_pkt].offset =
++02307                     ep->cur_pkt_dma_addr - dma_addr;
++02308                 ep->pkt_info[ep->cur_pkt].status = -DWC_E_NO_DATA;
++02309         }
++02310         ep->cur_pkt_addr += offset;
++02311         ep->cur_pkt_dma_addr += offset;
++02312         ep->cur_pkt++;
++02313 }
++02314 
++02322 static void set_ddma_iso_pkts_info(dwc_otg_core_if_t * core_if,
++02323                                    dwc_ep_t * dwc_ep)
++02324 {
++02325         dwc_otg_dev_dma_desc_t *dma_desc;
++02326         dev_dma_desc_sts_t sts = {.d32 = 0 };
++02327         iso_pkt_info_t *iso_packet;
++02328         uint32_t data_per_desc;
++02329         uint32_t offset;
++02330         int i, j;
++02331 
++02332         iso_packet = dwc_ep->pkt_info;
++02333 
++02336         if (dwc_ep->is_in == 0) {
++02337                 dma_desc =
++02338                     dwc_ep->iso_desc_addr +
++02339                     dwc_ep->desc_cnt * dwc_ep->proc_buf_num;
++02340                 offset = 0;
++02341 
++02342                 for (i = 0; i < dwc_ep->desc_cnt - dwc_ep->pkt_per_frm;
++02343                      i += dwc_ep->pkt_per_frm) {
++02344                         for (j = 0; j < dwc_ep->pkt_per_frm; ++j) {
++02345                                 data_per_desc =
++02346                                     ((j + 1) * dwc_ep->maxpacket >
++02347                                      dwc_ep->data_per_frame) ? dwc_ep->
++02348                                     data_per_frame -
++02349                                     j * dwc_ep->maxpacket : dwc_ep->maxpacket;
++02350                                 data_per_desc +=
++02351                                     (data_per_desc % 4) ? (4 -
++02352                                                            data_per_desc %
++02353                                                            4) : 0;
++02354 
++02355                                 sts.d32 = dma_desc->status.d32;
++02356 
++02357                                 /* Write status in iso_packet_decsriptor  */
++02358                                 iso_packet->status =
++02359                                     sts.b_iso_out.rxsts +
++02360                                     (sts.b_iso_out.bs ^ BS_DMA_DONE);
++02361                                 if (iso_packet->status) {
++02362                                         iso_packet->status = -DWC_E_NO_DATA;
++02363                                 }
++02364 
++02365                                 /* Received data length */
++02366                                 if (!sts.b_iso_out.rxbytes) {
++02367                                         iso_packet->length =
++02368                                             data_per_desc -
++02369                                             sts.b_iso_out.rxbytes;
++02370                                 } else {
++02371                                         iso_packet->length =
++02372                                             data_per_desc -
++02373                                             sts.b_iso_out.rxbytes + (4 -
++02374                                                                      dwc_ep->
++02375                                                                      data_per_frame
++02376                                                                      % 4);
++02377                                 }
++02378 
++02379                                 iso_packet->offset = offset;
++02380 
++02381                                 offset += data_per_desc;
++02382                                 dma_desc++;
++02383                                 iso_packet++;
++02384                         }
++02385                 }
++02386 
++02387                 for (j = 0; j < dwc_ep->pkt_per_frm - 1; ++j) {
++02388                         data_per_desc =
++02389                             ((j + 1) * dwc_ep->maxpacket >
++02390                              dwc_ep->data_per_frame) ? dwc_ep->data_per_frame -
++02391                             j * dwc_ep->maxpacket : dwc_ep->maxpacket;
++02392                         data_per_desc +=
++02393                             (data_per_desc % 4) ? (4 - data_per_desc % 4) : 0;
++02394 
++02395                         sts.d32 = dma_desc->status.d32;
++02396 
++02397                         /* Write status in iso_packet_decsriptor  */
++02398                         iso_packet->status =
++02399                             sts.b_iso_out.rxsts +
++02400                             (sts.b_iso_out.bs ^ BS_DMA_DONE);
++02401                         if (iso_packet->status) {
++02402                                 iso_packet->status = -DWC_E_NO_DATA;
++02403                         }
++02404 
++02405                         /* Received data length */
++02406                         iso_packet->length =
++02407                             dwc_ep->data_per_frame - sts.b_iso_out.rxbytes;
++02408 
++02409                         iso_packet->offset = offset;
++02410 
++02411                         offset += data_per_desc;
++02412                         iso_packet++;
++02413                         dma_desc++;
++02414                 }
++02415 
++02416                 sts.d32 = dma_desc->status.d32;
++02417 
++02418                 /* Write status in iso_packet_decsriptor  */
++02419                 iso_packet->status =
++02420                     sts.b_iso_out.rxsts + (sts.b_iso_out.bs ^ BS_DMA_DONE);
++02421                 if (iso_packet->status) {
++02422                         iso_packet->status = -DWC_E_NO_DATA;
++02423                 }
++02424                 /* Received data length */
++02425                 if (!sts.b_iso_out.rxbytes) {
++02426                         iso_packet->length =
++02427                             dwc_ep->data_per_frame - sts.b_iso_out.rxbytes;
++02428                 } else {
++02429                         iso_packet->length =
++02430                             dwc_ep->data_per_frame - sts.b_iso_out.rxbytes +
++02431                             (4 - dwc_ep->data_per_frame % 4);
++02432                 }
++02433 
++02434                 iso_packet->offset = offset;
++02435         } else {
++02438                 dma_desc =
++02439                     dwc_ep->iso_desc_addr +
++02440                     dwc_ep->desc_cnt * dwc_ep->proc_buf_num;
++02441 
++02442                 for (i = 0; i < dwc_ep->desc_cnt - 1; i++) {
++02443                         sts.d32 = dma_desc->status.d32;
++02444 
++02445                         /* Write status in iso packet descriptor */
++02446                         iso_packet->status =
++02447                             sts.b_iso_in.txsts +
++02448                             (sts.b_iso_in.bs ^ BS_DMA_DONE);
++02449                         if (iso_packet->status != 0) {
++02450                                 iso_packet->status = -DWC_E_NO_DATA;
++02451 
++02452                         }
++02453                         /* Bytes has been transfered */
++02454                         iso_packet->length =
++02455                             dwc_ep->data_per_frame - sts.b_iso_in.txbytes;
++02456 
++02457                         dma_desc++;
++02458                         iso_packet++;
++02459                 }
++02460 
++02461                 sts.d32 = dma_desc->status.d32;
++02462                 while (sts.b_iso_in.bs == BS_DMA_BUSY) {
++02463                         sts.d32 = dma_desc->status.d32;
++02464                 }
++02465 
++02466                 /* Write status in iso packet descriptor ??? do be done with ERROR codes */
++02467                 iso_packet->status =
++02468                     sts.b_iso_in.txsts + (sts.b_iso_in.bs ^ BS_DMA_DONE);
++02469                 if (iso_packet->status != 0) {
++02470                         iso_packet->status = -DWC_E_NO_DATA;
++02471                 }
++02472 
++02473                 /* Bytes has been transfered */
++02474                 iso_packet->length =
++02475                     dwc_ep->data_per_frame - sts.b_iso_in.txbytes;
++02476         }
++02477 }
++02478 
++02486 static void reinit_ddma_iso_xfer(dwc_otg_core_if_t * core_if, dwc_ep_t * dwc_ep)
++02487 {
++02488         int i, j;
++02489         dwc_otg_dev_dma_desc_t *dma_desc;
++02490         dma_addr_t dma_ad;
++02491         volatile uint32_t *addr;
++02492         dev_dma_desc_sts_t sts = {.d32 = 0 };
++02493         uint32_t data_per_desc;
++02494 
++02495         if (dwc_ep->is_in == 0) {
++02496                 addr = &core_if->dev_if->out_ep_regs[dwc_ep->num]->doepctl;
++02497         } else {
++02498                 addr = &core_if->dev_if->in_ep_regs[dwc_ep->num]->diepctl;
++02499         }
++02500 
++02501         if (dwc_ep->proc_buf_num == 0) {
++02503                 dma_ad = dwc_ep->dma_addr0;
++02504         } else {
++02506                 dma_ad = dwc_ep->dma_addr1;
++02507         }
++02508 
++02511         if (dwc_ep->is_in == 0) {
++02512                 dma_desc =
++02513                     dwc_ep->iso_desc_addr +
++02514                     dwc_ep->desc_cnt * dwc_ep->proc_buf_num;
++02515 
++02516                 sts.b_iso_out.bs = BS_HOST_READY;
++02517                 sts.b_iso_out.rxsts = 0;
++02518                 sts.b_iso_out.l = 0;
++02519                 sts.b_iso_out.sp = 0;
++02520                 sts.b_iso_out.ioc = 0;
++02521                 sts.b_iso_out.pid = 0;
++02522                 sts.b_iso_out.framenum = 0;
++02523 
++02524                 for (i = 0; i < dwc_ep->desc_cnt - dwc_ep->pkt_per_frm;
++02525                      i += dwc_ep->pkt_per_frm) {
++02526                         for (j = 0; j < dwc_ep->pkt_per_frm; ++j) {
++02527                                 data_per_desc =
++02528                                     ((j + 1) * dwc_ep->maxpacket >
++02529                                      dwc_ep->data_per_frame) ? dwc_ep->
++02530                                     data_per_frame -
++02531                                     j * dwc_ep->maxpacket : dwc_ep->maxpacket;
++02532                                 data_per_desc +=
++02533                                     (data_per_desc % 4) ? (4 -
++02534                                                            data_per_desc %
++02535                                                            4) : 0;
++02536                                 sts.b_iso_out.rxbytes = data_per_desc;
++02537                                 dma_desc->buf = dma_ad;
++02538                                 dma_desc->status.d32 = sts.d32;
++02539 
++02540                                 dma_ad += data_per_desc;
++02541                                 dma_desc++;
++02542                         }
++02543                 }
++02544 
++02545                 for (j = 0; j < dwc_ep->pkt_per_frm - 1; ++j) {
++02546 
++02547                         data_per_desc =
++02548                             ((j + 1) * dwc_ep->maxpacket >
++02549                              dwc_ep->data_per_frame) ? dwc_ep->data_per_frame -
++02550                             j * dwc_ep->maxpacket : dwc_ep->maxpacket;
++02551                         data_per_desc +=
++02552                             (data_per_desc % 4) ? (4 - data_per_desc % 4) : 0;
++02553                         sts.b_iso_out.rxbytes = data_per_desc;
++02554 
++02555                         dma_desc->buf = dma_ad;
++02556                         dma_desc->status.d32 = sts.d32;
++02557 
++02558                         dma_desc++;
++02559                         dma_ad += data_per_desc;
++02560                 }
++02561 
++02562                 sts.b_iso_out.ioc = 1;
++02563                 sts.b_iso_out.l = dwc_ep->proc_buf_num;
++02564 
++02565                 data_per_desc =
++02566                     ((j + 1) * dwc_ep->maxpacket >
++02567                      dwc_ep->data_per_frame) ? dwc_ep->data_per_frame -
++02568                     j * dwc_ep->maxpacket : dwc_ep->maxpacket;
++02569                 data_per_desc +=
++02570                     (data_per_desc % 4) ? (4 - data_per_desc % 4) : 0;
++02571                 sts.b_iso_out.rxbytes = data_per_desc;
++02572 
++02573                 dma_desc->buf = dma_ad;
++02574                 dma_desc->status.d32 = sts.d32;
++02575         } else {
++02578                 dma_desc =
++02579                     dwc_ep->iso_desc_addr +
++02580                     dwc_ep->desc_cnt * dwc_ep->proc_buf_num;
++02581 
++02582                 sts.b_iso_in.bs = BS_HOST_READY;
++02583                 sts.b_iso_in.txsts = 0;
++02584                 sts.b_iso_in.sp = 0;
++02585                 sts.b_iso_in.ioc = 0;
++02586                 sts.b_iso_in.pid = dwc_ep->pkt_per_frm;
++02587                 sts.b_iso_in.framenum = dwc_ep->next_frame;
++02588                 sts.b_iso_in.txbytes = dwc_ep->data_per_frame;
++02589                 sts.b_iso_in.l = 0;
++02590 
++02591                 for (i = 0; i < dwc_ep->desc_cnt - 1; i++) {
++02592                         dma_desc->buf = dma_ad;
++02593                         dma_desc->status.d32 = sts.d32;
++02594 
++02595                         sts.b_iso_in.framenum += dwc_ep->bInterval;
++02596                         dma_ad += dwc_ep->data_per_frame;
++02597                         dma_desc++;
++02598                 }
++02599 
++02600                 sts.b_iso_in.ioc = 1;
++02601                 sts.b_iso_in.l = dwc_ep->proc_buf_num;
++02602 
++02603                 dma_desc->buf = dma_ad;
++02604                 dma_desc->status.d32 = sts.d32;
++02605 
++02606                 dwc_ep->next_frame =
++02607                     sts.b_iso_in.framenum + dwc_ep->bInterval * 1;
++02608         }
++02609         dwc_ep->proc_buf_num = (dwc_ep->proc_buf_num ^ 1) & 0x1;
++02610 }
++02611 
++02620 static uint32_t handle_iso_out_pkt_dropped(dwc_otg_core_if_t * core_if,
++02621                                            dwc_ep_t * dwc_ep)
++02622 {
++02623         uint32_t dma_addr;
++02624         uint32_t drp_pkt;
++02625         uint32_t drp_pkt_cnt;
++02626         deptsiz_data_t deptsiz = {.d32 = 0 };
++02627         depctl_data_t depctl = {.d32 = 0 };
++02628         int i;
++02629 
++02630         deptsiz.d32 =
++02631             dwc_read_reg32(&core_if->dev_if->out_ep_regs[dwc_ep->num]->
++02632                            doeptsiz);
++02633 
++02634         drp_pkt = dwc_ep->pkt_cnt - deptsiz.b.pktcnt;
++02635         drp_pkt_cnt = dwc_ep->pkt_per_frm - (drp_pkt % dwc_ep->pkt_per_frm);
++02636 
++02637         /* Setting dropped packets status */
++02638         for (i = 0; i < drp_pkt_cnt; ++i) {
++02639                 dwc_ep->pkt_info[drp_pkt].status = -DWC_E_NO_DATA;
++02640                 drp_pkt++;
++02641                 deptsiz.b.pktcnt--;
++02642         }
++02643 
++02644         if (deptsiz.b.pktcnt > 0) {
++02645                 deptsiz.b.xfersize =
++02646                     dwc_ep->xfer_len - (dwc_ep->pkt_cnt -
++02647                                         deptsiz.b.pktcnt) * dwc_ep->maxpacket;
++02648         } else {
++02649                 deptsiz.b.xfersize = 0;
++02650                 deptsiz.b.pktcnt = 0;
++02651         }
++02652 
++02653         dwc_write_reg32(&core_if->dev_if->out_ep_regs[dwc_ep->num]->doeptsiz,
++02654                         deptsiz.d32);
++02655 
++02656         if (deptsiz.b.pktcnt > 0) {
++02657                 if (dwc_ep->proc_buf_num) {
++02658                         dma_addr =
++02659                             dwc_ep->dma_addr1 + dwc_ep->xfer_len -
++02660                             deptsiz.b.xfersize;
++02661                 } else {
++02662                         dma_addr =
++02663                             dwc_ep->dma_addr0 + dwc_ep->xfer_len -
++02664                             deptsiz.b.xfersize;;
++02665                 }
++02666 
++02667                 dwc_write_reg32(&core_if->dev_if->out_ep_regs[dwc_ep->num]->
++02668                                 doepdma, dma_addr);
++02669 
++02671                 depctl.d32 = 0;
++02672                 depctl.b.epena = 1;
++02673                 depctl.b.cnak = 1;
++02674 
++02675                 dwc_modify_reg32(&core_if->dev_if->out_ep_regs[dwc_ep->num]->
++02676                                  doepctl, depctl.d32, depctl.d32);
++02677                 return 0;
++02678         } else {
++02679                 return 1;
++02680         }
++02681 }
++02682 
++02690 static uint32_t set_iso_pkts_info(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
++02691 {
++02692         int i, j;
++02693         dma_addr_t dma_ad;
++02694         iso_pkt_info_t *packet_info = ep->pkt_info;
++02695         uint32_t offset;
++02696         uint32_t frame_data;
++02697         deptsiz_data_t deptsiz;
++02698 
++02699         if (ep->proc_buf_num == 0) {
++02701                 dma_ad = ep->dma_addr0;
++02702         } else {
++02704                 dma_ad = ep->dma_addr1;
++02705         }
++02706 
++02707         if (ep->is_in) {
++02708                 deptsiz.d32 =
++02709                     dwc_read_reg32(&core_if->dev_if->in_ep_regs[ep->num]->
++02710                                    dieptsiz);
++02711         } else {
++02712                 deptsiz.d32 =
++02713                     dwc_read_reg32(&core_if->dev_if->out_ep_regs[ep->num]->
++02714                                    doeptsiz);
++02715         }
++02716 
++02717         if (!deptsiz.b.xfersize) {
++02718                 offset = 0;
++02719                 for (i = 0; i < ep->pkt_cnt; i += ep->pkt_per_frm) {
++02720                         frame_data = ep->data_per_frame;
++02721                         for (j = 0; j < ep->pkt_per_frm; ++j) {
++02722 
++02723                                 /* Packet status - is not set as initially 
++02724                                  * it is set to 0 and if packet was sent 
++02725                                  successfully, status field will remain 0*/
++02726 
++02727                                 /* Bytes has been transfered */
++02728                                 packet_info->length =
++02729                                     (ep->maxpacket <
++02730                                      frame_data) ? ep->maxpacket : frame_data;
++02731 
++02732                                 /* Received packet offset */
++02733                                 packet_info->offset = offset;
++02734                                 offset += packet_info->length;
++02735                                 frame_data -= packet_info->length;
++02736 
++02737                                 packet_info++;
++02738                         }
++02739                 }
++02740                 return 1;
++02741         } else {
++02742                 /* This is a workaround for in case of Transfer Complete with 
++02743                  * PktDrpSts interrupts merging - in this case Transfer complete 
++02744                  * interrupt for Isoc Out Endpoint is asserted without PktDrpSts 
++02745                  * set and with DOEPTSIZ register non zero. Investigations showed,
++02746                  * that this happens when Out packet is dropped, but because of 
++02747                  * interrupts merging during first interrupt handling PktDrpSts
++02748                  * bit is cleared and for next merged interrupts it is not reset.
++02749                  * In this case SW hadles the interrupt as if PktDrpSts bit is set.
++02750                  */
++02751                 if (ep->is_in) {
++02752                         return 1;
++02753                 } else {
++02754                         return handle_iso_out_pkt_dropped(core_if, ep);
++02755                 }
++02756         }
++02757 }
++02758 
++02766 static void complete_iso_ep(dwc_otg_pcd_t * pcd, dwc_otg_pcd_ep_t * ep)
++02767 {
++02768         dwc_otg_core_if_t *core_if = GET_CORE_IF(ep->pcd);
++02769         dwc_ep_t *dwc_ep = &ep->dwc_ep;
++02770         uint8_t is_last = 0;
++02771 
++02772         if(ep->dwc_ep.next_frame == 0xffffffff) {
++02773                 DWC_WARN("Next frame is not set!\n");
++02774                 return;
++02775         }
++02776 
++02777         if (core_if->dma_enable) {
++02778                 if (core_if->dma_desc_enable) {
++02779                         set_ddma_iso_pkts_info(core_if, dwc_ep);
++02780                         reinit_ddma_iso_xfer(core_if, dwc_ep);
++02781                         is_last = 1;
++02782                 } else {
++02783                         if (core_if->pti_enh_enable) {
++02784                                 if (set_iso_pkts_info(core_if, dwc_ep)) {
++02785                                         dwc_ep->proc_buf_num =
++02786                                             (dwc_ep->proc_buf_num ^ 1) & 0x1;
++02787                                         dwc_otg_iso_ep_start_buf_transfer
++02788                                             (core_if, dwc_ep);
++02789                                         is_last = 1;
++02790                                 }
++02791                         } else {
++02792                                 set_current_pkt_info(core_if, dwc_ep);
++02793                                 if (dwc_ep->cur_pkt >= dwc_ep->pkt_cnt) {
++02794                                         is_last = 1;
++02795                                         dwc_ep->cur_pkt = 0;
++02796                                         dwc_ep->proc_buf_num =
++02797                                             (dwc_ep->proc_buf_num ^ 1) & 0x1;
++02798                                         if (dwc_ep->proc_buf_num) {
++02799                                                 dwc_ep->cur_pkt_addr =
++02800                                                     dwc_ep->xfer_buff1;
++02801                                                 dwc_ep->cur_pkt_dma_addr =
++02802                                                     dwc_ep->dma_addr1;
++02803                                         } else {
++02804                                                 dwc_ep->cur_pkt_addr =
++02805                                                     dwc_ep->xfer_buff0;
++02806                                                 dwc_ep->cur_pkt_dma_addr =
++02807                                                     dwc_ep->dma_addr0;
++02808                                         }
++02809 
++02810                                 }
++02811                                 dwc_otg_iso_ep_start_frm_transfer(core_if,
++02812                                                                   dwc_ep);
++02813                         }
++02814                 }
++02815         } else {
++02816                 set_current_pkt_info(core_if, dwc_ep);
++02817                 if (dwc_ep->cur_pkt >= dwc_ep->pkt_cnt) {
++02818                         is_last = 1;
++02819                         dwc_ep->cur_pkt = 0;
++02820                         dwc_ep->proc_buf_num = (dwc_ep->proc_buf_num ^ 1) & 0x1;
++02821                         if (dwc_ep->proc_buf_num) {
++02822                                 dwc_ep->cur_pkt_addr = dwc_ep->xfer_buff1;
++02823                                 dwc_ep->cur_pkt_dma_addr = dwc_ep->dma_addr1;
++02824                         } else {
++02825                                 dwc_ep->cur_pkt_addr = dwc_ep->xfer_buff0;
++02826                                 dwc_ep->cur_pkt_dma_addr = dwc_ep->dma_addr0;
++02827                         }
++02828 
++02829                 }
++02830                 dwc_otg_iso_ep_start_frm_transfer(core_if, dwc_ep);
++02831         }
++02832         if (is_last)
++02833                 dwc_otg_iso_buffer_done(pcd, ep, ep->iso_req_handle);
++02834 }
++02835 #endif                          /* DWC_EN_ISOC */
++02836 
++02843 static void handle_ep0(dwc_otg_pcd_t * pcd)
++02844 {
++02845         dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
++02846         dwc_otg_pcd_ep_t *ep0 = &pcd->ep0;
++02847         dev_dma_desc_sts_t desc_sts;
++02848         deptsiz0_data_t deptsiz;
++02849         uint32_t byte_count;
++02850 
++02851 #ifdef DEBUG_EP0
++02852         DWC_DEBUGPL(DBG_PCDV, "%s()\n", __func__);
++02853         print_ep0_state(pcd);
++02854 #endif
++02855 
++02856 //      DWC_PRINTF("HANDLE EP0\n");
++02857 
++02858         switch (pcd->ep0state) {
++02859         case EP0_DISCONNECT:
++02860                 break;
++02861 
++02862         case EP0_IDLE:
++02863                 pcd->request_config = 0;
++02864 
++02865                 pcd_setup(pcd);
++02866                 break;
++02867 
++02868         case EP0_IN_DATA_PHASE:
++02869 #ifdef DEBUG_EP0
++02870                 DWC_DEBUGPL(DBG_PCD, "DATA_IN EP%d-%s: type=%d, mps=%d\n",
++02871                             ep0->dwc_ep.num, (ep0->dwc_ep.is_in ? "IN" : "OUT"),
++02872                             ep0->dwc_ep.type, ep0->dwc_ep.maxpacket);
++02873 #endif
++02874 
++02875                 if (core_if->dma_enable != 0) {
++02876                         /*
++02877                          * For EP0 we can only program 1 packet at a time so we
++02878                          * need to do the make calculations after each complete.
++02879                          * Call write_packet to make the calculations, as in
++02880                          * slave mode, and use those values to determine if we
++02881                          * can complete.
++02882                          */
++02883                         if (core_if->dma_desc_enable == 0) {
++02884                                 deptsiz.d32 =
++02885                                     dwc_read_reg32(&core_if->dev_if->
++02886                                                    in_ep_regs[0]->dieptsiz);
++02887                                 byte_count =
++02888                                     ep0->dwc_ep.xfer_len - deptsiz.b.xfersize;
++02889                         } else {
++02890                                 desc_sts =
++02891                                     core_if->dev_if->in_desc_addr->status;
++02892                                 byte_count =
++02893                                     ep0->dwc_ep.xfer_len - desc_sts.b.bytes;
++02894                         }
++02895                         ep0->dwc_ep.xfer_count += byte_count;
++02896                         ep0->dwc_ep.xfer_buff += byte_count;
++02897                         ep0->dwc_ep.dma_addr += byte_count;
++02898                 }
++02899                 if (ep0->dwc_ep.xfer_count < ep0->dwc_ep.total_len) {
++02900                         dwc_otg_ep0_continue_transfer(GET_CORE_IF(pcd),
++02901                                                       &ep0->dwc_ep);
++02902                         DWC_DEBUGPL(DBG_PCD, "CONTINUE TRANSFER\n");
++02903                 } else if (ep0->dwc_ep.sent_zlp) {
++02904                         dwc_otg_ep0_continue_transfer(GET_CORE_IF(pcd),
++02905                                                       &ep0->dwc_ep);
++02906                         ep0->dwc_ep.sent_zlp = 0;
++02907                         DWC_DEBUGPL(DBG_PCD, "CONTINUE TRANSFER\n");
++02908                 } else {
++02909                         ep0_complete_request(ep0);
++02910                         DWC_DEBUGPL(DBG_PCD, "COMPLETE TRANSFER\n");
++02911                 }
++02912                 break;
++02913         case EP0_OUT_DATA_PHASE:
++02914 #ifdef DEBUG_EP0
++02915                 DWC_DEBUGPL(DBG_PCD, "DATA_OUT EP%d-%s: type=%d, mps=%d\n",
++02916                             ep0->dwc_ep.num, (ep0->dwc_ep.is_in ? "IN" : "OUT"),
++02917                             ep0->dwc_ep.type, ep0->dwc_ep.maxpacket);
++02918 #endif
++02919                 if (core_if->dma_enable != 0) {
++02920                         if (core_if->dma_desc_enable == 0) {
++02921                                 deptsiz.d32 =
++02922                                     dwc_read_reg32(&core_if->dev_if->
++02923                                                    out_ep_regs[0]->doeptsiz);
++02924                                 byte_count =
++02925                                     ep0->dwc_ep.maxpacket - deptsiz.b.xfersize;
++02926                         } else {
++02927                                 desc_sts =
++02928                                     core_if->dev_if->out_desc_addr->status;
++02929                                 byte_count =
++02930                                     ep0->dwc_ep.maxpacket - desc_sts.b.bytes;
++02931                         }
++02932                         ep0->dwc_ep.xfer_count += byte_count;
++02933                         ep0->dwc_ep.xfer_buff += byte_count;
++02934                         ep0->dwc_ep.dma_addr += byte_count;
++02935                 }
++02936                 if (ep0->dwc_ep.xfer_count < ep0->dwc_ep.total_len) {
++02937                         dwc_otg_ep0_continue_transfer(GET_CORE_IF(pcd),
++02938                                                       &ep0->dwc_ep);
++02939                         DWC_DEBUGPL(DBG_PCD, "CONTINUE TRANSFER\n");
++02940                 } else if (ep0->dwc_ep.sent_zlp) {
++02941                         dwc_otg_ep0_continue_transfer(GET_CORE_IF(pcd),
++02942                                                       &ep0->dwc_ep);
++02943                         ep0->dwc_ep.sent_zlp = 0;
++02944                         DWC_DEBUGPL(DBG_PCD, "CONTINUE TRANSFER\n");
++02945                 } else {
++02946                         ep0_complete_request(ep0);
++02947                         DWC_DEBUGPL(DBG_PCD, "COMPLETE TRANSFER\n");
++02948                 }
++02949                 break;
++02950 
++02951         case EP0_IN_STATUS_PHASE:
++02952         case EP0_OUT_STATUS_PHASE:
++02953                 DWC_DEBUGPL(DBG_PCD, "CASE: EP0_STATUS\n");
++02954                 ep0_complete_request(ep0);
++02955                 pcd->ep0state = EP0_IDLE;
++02956                 ep0->stopped = 1;
++02957                 ep0->dwc_ep.is_in = 0;  /* OUT for next SETUP */
++02958 
++02959                 /* Prepare for more SETUP Packets */
++02960                 if (core_if->dma_enable) {
++02961                         ep0_out_start(core_if, pcd);
++02962                 }
++02963                 break;
++02964 
++02965         case EP0_STALL:
++02966                 DWC_ERROR("EP0 STALLed, should not get here pcd_setup()\n");
++02967                 break;
++02968         }
++02969 #ifdef DEBUG_EP0
++02970         print_ep0_state(pcd);
++02971 #endif
++02972 }
++02973 
++02977 static void restart_transfer(dwc_otg_pcd_t * pcd, const uint32_t epnum)
++02978 {
++02979         dwc_otg_core_if_t *core_if;
++02980         dwc_otg_dev_if_t *dev_if;
++02981         deptsiz_data_t dieptsiz = {.d32 = 0 };
++02982         dwc_otg_pcd_ep_t *ep;
++02983 
++02984         ep = get_in_ep(pcd, epnum);
++02985 
++02986 #ifdef DWC_EN_ISOC
++02987         if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) {
++02988                 return;
++02989         }
++02990 #endif                          /* DWC_EN_ISOC  */
++02991 
++02992         core_if = GET_CORE_IF(pcd);
++02993         dev_if = core_if->dev_if;
++02994 
++02995         dieptsiz.d32 = dwc_read_reg32(&dev_if->in_ep_regs[epnum]->dieptsiz);
++02996 
++02997         DWC_DEBUGPL(DBG_PCD, "xfer_buff=%p xfer_count=%0x xfer_len=%0x"
++02998                     " stopped=%d\n", ep->dwc_ep.xfer_buff,
++02999                     ep->dwc_ep.xfer_count, ep->dwc_ep.xfer_len, ep->stopped);
++03000         /*
++03001          * If xfersize is 0 and pktcnt in not 0, resend the last packet.
++03002          */
++03003         if (dieptsiz.b.pktcnt && dieptsiz.b.xfersize == 0 &&
++03004             ep->dwc_ep.start_xfer_buff != 0) {
++03005                 if (ep->dwc_ep.total_len <= ep->dwc_ep.maxpacket) {
++03006                         ep->dwc_ep.xfer_count = 0;
++03007                         ep->dwc_ep.xfer_buff = ep->dwc_ep.start_xfer_buff;
++03008                         ep->dwc_ep.xfer_len = ep->dwc_ep.xfer_count;
++03009                 } else {
++03010                         ep->dwc_ep.xfer_count -= ep->dwc_ep.maxpacket;
++03011                         /* convert packet size to dwords. */
++03012                         ep->dwc_ep.xfer_buff -= ep->dwc_ep.maxpacket;
++03013                         ep->dwc_ep.xfer_len = ep->dwc_ep.xfer_count;
++03014                 }
++03015                 ep->stopped = 0;
++03016                 DWC_DEBUGPL(DBG_PCD, "xfer_buff=%p xfer_count=%0x "
++03017                             "xfer_len=%0x stopped=%d\n",
++03018                             ep->dwc_ep.xfer_buff,
++03019                             ep->dwc_ep.xfer_count, ep->dwc_ep.xfer_len,
++03020                             ep->stopped);
++03021                 if (epnum == 0) {
++03022                         dwc_otg_ep0_start_transfer(core_if, &ep->dwc_ep);
++03023                 } else {
++03024                         dwc_otg_ep_start_transfer(core_if, &ep->dwc_ep);
++03025                 }
++03026         }
++03027 }
++03028 
++03032 static inline void handle_in_ep_disable_intr(dwc_otg_pcd_t * pcd,
++03033                                              const uint32_t epnum)
++03034 {
++03035         dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
++03036         dwc_otg_dev_if_t *dev_if = core_if->dev_if;
++03037         deptsiz_data_t dieptsiz = {.d32 = 0 };
++03038         dctl_data_t dctl = {.d32 = 0 };
++03039         dwc_otg_pcd_ep_t *ep;
++03040         dwc_ep_t *dwc_ep;
++03041 
++03042         ep = get_in_ep(pcd, epnum);
++03043         dwc_ep = &ep->dwc_ep;
++03044 
++03045         if (dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) {
++03046                 dwc_otg_flush_tx_fifo(core_if, dwc_ep->tx_fifo_num);
++03047                 return;
++03048         }
++03049 
++03050         DWC_DEBUGPL(DBG_PCD, "diepctl%d=%0x\n", epnum,
++03051                     dwc_read_reg32(&dev_if->in_ep_regs[epnum]->diepctl));
++03052         dieptsiz.d32 = dwc_read_reg32(&dev_if->in_ep_regs[epnum]->dieptsiz);
++03053 
++03054         DWC_DEBUGPL(DBG_ANY, "pktcnt=%d size=%d\n",
++03055                     dieptsiz.b.pktcnt, dieptsiz.b.xfersize);
++03056 
++03057         if (ep->stopped) {
++03058                 /* Flush the Tx FIFO */
++03059                 dwc_otg_flush_tx_fifo(core_if, dwc_ep->tx_fifo_num);
++03060                 /* Clear the Global IN NP NAK */
++03061                 dctl.d32 = 0;
++03062                 dctl.b.cgnpinnak = 1;
++03063                 dwc_modify_reg32(&dev_if->dev_global_regs->dctl, dctl.d32, 0);
++03064                 /* Restart the transaction */
++03065                 if (dieptsiz.b.pktcnt != 0 || dieptsiz.b.xfersize != 0) {
++03066                         restart_transfer(pcd, epnum);
++03067                 }
++03068         } else {
++03069                 /* Restart the transaction */
++03070                 if (dieptsiz.b.pktcnt != 0 || dieptsiz.b.xfersize != 0) {
++03071                         restart_transfer(pcd, epnum);
++03072                 }
++03073                 DWC_DEBUGPL(DBG_ANY, "STOPPED!!!\n");
++03074         }
++03075 }
++03076 
++03080 static inline void handle_in_ep_timeout_intr(dwc_otg_pcd_t * pcd,
++03081                                              const uint32_t epnum)
++03082 {
++03083         dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
++03084         dwc_otg_dev_if_t *dev_if = core_if->dev_if;
++03085 
++03086 #ifdef DEBUG
++03087         deptsiz_data_t dieptsiz = {.d32 = 0 };
++03088         uint32_t num = 0;
++03089 #endif
++03090         dctl_data_t dctl = {.d32 = 0 };
++03091         dwc_otg_pcd_ep_t *ep;
++03092 
++03093         gintmsk_data_t intr_mask = {.d32 = 0 };
++03094 
++03095         ep = get_in_ep(pcd, epnum);
++03096 
++03097         /* Disable the NP Tx Fifo Empty Interrrupt */
++03098         if (!core_if->dma_enable) {
++03099                 intr_mask.b.nptxfempty = 1;
++03100                 dwc_modify_reg32(&core_if->core_global_regs->gintmsk,
++03101                                  intr_mask.d32, 0);
++03102         }
++03105         /*
++03106          * Non-periodic EP
++03107          */
++03108         /* Enable the Global IN NAK Effective Interrupt */
++03109         intr_mask.b.ginnakeff = 1;
++03110         dwc_modify_reg32(&core_if->core_global_regs->gintmsk, 0, intr_mask.d32);
++03111 
++03112         /* Set Global IN NAK */
++03113         dctl.b.sgnpinnak = 1;
++03114         dwc_modify_reg32(&dev_if->dev_global_regs->dctl, dctl.d32, dctl.d32);
++03115 
++03116         ep->stopped = 1;
++03117 
++03118 #ifdef DEBUG
++03119         dieptsiz.d32 = dwc_read_reg32(&dev_if->in_ep_regs[num]->dieptsiz);
++03120         DWC_DEBUGPL(DBG_ANY, "pktcnt=%d size=%d\n",
++03121                     dieptsiz.b.pktcnt, dieptsiz.b.xfersize);
++03122 #endif
++03123 
++03124 #ifdef DISABLE_PERIODIC_EP
++03125         /*
++03126          * Set the NAK bit for this EP to
++03127          * start the disable process.
++03128          */
++03129         diepctl.d32 = 0;
++03130         diepctl.b.snak = 1;
++03131         dwc_modify_reg32(&dev_if->in_ep_regs[num]->diepctl, diepctl.d32,
++03132                          diepctl.d32);
++03133         ep->disabling = 1;
++03134         ep->stopped = 1;
++03135 #endif
++03136 }
++03137 
++03141 static inline int32_t handle_in_ep_nak_intr(dwc_otg_pcd_t * pcd,
++03142                                             const uint32_t epnum)
++03143 {
++03145         dwc_otg_core_if_t *core_if;
++03146         diepmsk_data_t intr_mask = {.d32 = 0 };
++03147 
++03148         DWC_PRINTF("INTERRUPT Handler not implemented for %s\n", "IN EP NAK");
++03149         core_if = GET_CORE_IF(pcd);
++03150         intr_mask.b.nak = 1;
++03151 
++03152         if (core_if->multiproc_int_enable) {
++03153                 dwc_modify_reg32(&core_if->dev_if->dev_global_regs->
++03154                                  diepeachintmsk[epnum], intr_mask.d32, 0);
++03155         } else {
++03156                 dwc_modify_reg32(&core_if->dev_if->dev_global_regs->diepmsk,
++03157                                  intr_mask.d32, 0);
++03158         }
++03159 
++03160         return 1;
++03161 }
++03162 
++03166 static inline int32_t handle_out_ep_babble_intr(dwc_otg_pcd_t * pcd,
++03167                                                 const uint32_t epnum)
++03168 {
++03170         dwc_otg_core_if_t *core_if;
++03171         doepmsk_data_t intr_mask = {.d32 = 0 };
++03172 
++03173         DWC_PRINTF("INTERRUPT Handler not implemented for %s\n",
++03174                    "OUT EP Babble");
++03175         core_if = GET_CORE_IF(pcd);
++03176         intr_mask.b.babble = 1;
++03177 
++03178         if (core_if->multiproc_int_enable) {
++03179                 dwc_modify_reg32(&core_if->dev_if->dev_global_regs->
++03180                                  doepeachintmsk[epnum], intr_mask.d32, 0);
++03181         } else {
++03182                 dwc_modify_reg32(&core_if->dev_if->dev_global_regs->doepmsk,
++03183                                  intr_mask.d32, 0);
++03184         }
++03185 
++03186         return 1;
++03187 }
++03188 
++03192 static inline int32_t handle_out_ep_nak_intr(dwc_otg_pcd_t * pcd,
++03193                                              const uint32_t epnum)
++03194 {
++03196         dwc_otg_core_if_t *core_if;
++03197         doepmsk_data_t intr_mask = {.d32 = 0 };
++03198 
++03199         DWC_PRINTF("INTERRUPT Handler not implemented for %s\n", "OUT EP NAK");
++03200         core_if = GET_CORE_IF(pcd);
++03201         intr_mask.b.nak = 1;
++03202 
++03203         if (core_if->multiproc_int_enable) {
++03204                 dwc_modify_reg32(&core_if->dev_if->dev_global_regs->
++03205                                  doepeachintmsk[epnum], intr_mask.d32, 0);
++03206         } else {
++03207                 dwc_modify_reg32(&core_if->dev_if->dev_global_regs->doepmsk,
++03208                                  intr_mask.d32, 0);
++03209         }
++03210 
++03211         return 1;
++03212 }
++03213 
++03217 static inline int32_t handle_out_ep_nyet_intr(dwc_otg_pcd_t * pcd,
++03218                                               const uint32_t epnum)
++03219 {
++03221         dwc_otg_core_if_t *core_if;
++03222         doepmsk_data_t intr_mask = {.d32 = 0 };
++03223 
++03224         DWC_PRINTF("INTERRUPT Handler not implemented for %s\n", "OUT EP NYET");
++03225         core_if = GET_CORE_IF(pcd);
++03226         intr_mask.b.nyet = 1;
++03227 
++03228         if (core_if->multiproc_int_enable) {
++03229                 dwc_modify_reg32(&core_if->dev_if->dev_global_regs->
++03230                                  doepeachintmsk[epnum], intr_mask.d32, 0);
++03231         } else {
++03232                 dwc_modify_reg32(&core_if->dev_if->dev_global_regs->doepmsk,
++03233                                  intr_mask.d32, 0);
++03234         }
++03235 
++03236         return 1;
++03237 }
++03238 
++03255 static int32_t dwc_otg_pcd_handle_in_ep_intr(dwc_otg_pcd_t * pcd)
++03256 {
++03257 #define CLEAR_IN_EP_INTR(__core_if,__epnum,__intr) \
++03258 do { \
++03259                 diepint_data_t diepint = {.d32=0}; \
++03260                 diepint.b.__intr = 1; \
++03261                 dwc_write_reg32(&__core_if->dev_if->in_ep_regs[__epnum]->diepint, \
++03262                 diepint.d32); \
++03263 } while (0)
++03264 
++03265         dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
++03266         dwc_otg_dev_if_t *dev_if = core_if->dev_if;
++03267         diepint_data_t diepint = {.d32 = 0 };
++03268         dctl_data_t dctl = {.d32 = 0 };
++03269         depctl_data_t depctl = {.d32 = 0 };
++03270         uint32_t ep_intr;
++03271         uint32_t epnum = 0;
++03272         dwc_otg_pcd_ep_t *ep;
++03273         dwc_ep_t *dwc_ep;
++03274         gintmsk_data_t intr_mask = {.d32 = 0 };
++03275 
++03276         DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, pcd);
++03277 
++03278         /* Read in the device interrupt bits */
++03279         ep_intr = dwc_otg_read_dev_all_in_ep_intr(core_if);
++03280 
++03281         /* Service the Device IN interrupts for each endpoint */
++03282         while (ep_intr) {
++03283                 if (ep_intr & 0x1) {
++03284                         uint32_t empty_msk;
++03285                         /* Get EP pointer */
++03286                         ep = get_in_ep(pcd, epnum);
++03287                         dwc_ep = &ep->dwc_ep;
++03288 
++03289                         depctl.d32 =
++03290                             dwc_read_reg32(&dev_if->in_ep_regs[epnum]->diepctl);
++03291                         empty_msk =
++03292                             dwc_read_reg32(&dev_if->dev_global_regs->
++03293                                            dtknqr4_fifoemptymsk);
++03294 
++03295                         DWC_DEBUGPL(DBG_PCDV,
++03296                                     "IN EP INTERRUPT - %d\nepmty_msk - %8x  diepctl - %8x\n",
++03297                                     epnum, empty_msk, depctl.d32);
++03298 
++03299                         DWC_DEBUGPL(DBG_PCD,
++03300                                     "EP%d-%s: type=%d, mps=%d\n",
++03301                                     dwc_ep->num, (dwc_ep->is_in ? "IN" : "OUT"),
++03302                                     dwc_ep->type, dwc_ep->maxpacket);
++03303 
++03304                         diepint.d32 =
++03305                             dwc_otg_read_dev_in_ep_intr(core_if, dwc_ep);
++03306 
++03307                         DWC_DEBUGPL(DBG_PCDV,
++03308                                     "EP %d Interrupt Register - 0x%x\n", epnum,
++03309                                     diepint.d32);
++03310                         /* Transfer complete */
++03311                         if (diepint.b.xfercompl) {
++03312                                 /* Disable the NP Tx FIFO Empty
++03313                                  * Interrrupt */
++03314                                 if (core_if->en_multiple_tx_fifo == 0) {
++03315                                         intr_mask.b.nptxfempty = 1;
++03316                                         dwc_modify_reg32(&core_if->
++03317                                                          core_global_regs->
++03318                                                          gintmsk, intr_mask.d32,
++03319                                                          0);
++03320                                 } else {
++03321                                         /* Disable the Tx FIFO Empty Interrupt for this EP */
++03322                                         uint32_t fifoemptymsk =
++03323                                             0x1 << dwc_ep->num;
++03324                                         dwc_modify_reg32(&core_if->dev_if->
++03325                                                          dev_global_regs->
++03326                                                          dtknqr4_fifoemptymsk,
++03327                                                          fifoemptymsk, 0);
++03328                                 }
++03329                                 /* Clear the bit in DIEPINTn for this interrupt */
++03330                                 CLEAR_IN_EP_INTR(core_if, epnum, xfercompl);
++03331 
++03332                                 /* Complete the transfer */
++03333                                 if (epnum == 0) {
++03334                                         handle_ep0(pcd);
++03335                                 }
++03336 #ifdef DWC_EN_ISOC
++03337                                 else if (dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) {
++03338                                         if (!ep->stopped)
++03339                                                 complete_iso_ep(pcd, ep);
++03340                                 }
++03341 #endif                          /* DWC_EN_ISOC */
++03342                                 else {
++03343 
++03344                                         complete_ep(ep);
++03345                                 }
++03346                         }
++03347                         /* Endpoint disable      */
++03348                         if (diepint.b.epdisabled) {
++03349                                 DWC_DEBUGPL(DBG_ANY, "EP%d IN disabled\n",
++03350                                             epnum);
++03351                                 handle_in_ep_disable_intr(pcd, epnum);
++03352 
++03353                                 /* Clear the bit in DIEPINTn for this interrupt */
++03354                                 CLEAR_IN_EP_INTR(core_if, epnum, epdisabled);
++03355                         }
++03356                         /* AHB Error */
++03357                         if (diepint.b.ahberr) {
++03358                                 DWC_DEBUGPL(DBG_ANY, "EP%d IN AHB Error\n",
++03359                                             epnum);
++03360                                 /* Clear the bit in DIEPINTn for this interrupt */
++03361                                 CLEAR_IN_EP_INTR(core_if, epnum, ahberr);
++03362                         }
++03363                         /* TimeOUT Handshake (non-ISOC IN EPs) */
++03364                         if (diepint.b.timeout) {
++03365                                 DWC_DEBUGPL(DBG_ANY, "EP%d IN Time-out\n",
++03366                                             epnum);
++03367                                 handle_in_ep_timeout_intr(pcd, epnum);
++03368 
++03369                                 CLEAR_IN_EP_INTR(core_if, epnum, timeout);
++03370                         }
++03372                         if (diepint.b.intktxfemp) {
++03373                                 DWC_DEBUGPL(DBG_ANY,
++03374                                             "EP%d IN TKN TxFifo Empty\n",
++03375                                             epnum);
++03376                                 if (!ep->stopped && epnum != 0) {
++03377 
++03378                                         diepmsk_data_t diepmsk = {.d32 = 0 };
++03379                                         diepmsk.b.intktxfemp = 1;
++03380 
++03381                                         if (core_if->multiproc_int_enable) {
++03382                                                 dwc_modify_reg32(&dev_if->
++03383                                                                  dev_global_regs->
++03384                                                                  diepeachintmsk
++03385                                                                  [epnum],
++03386                                                                  diepmsk.d32,
++03387                                                                  0);
++03388                                         } else {
++03389                                                 dwc_modify_reg32(&dev_if->
++03390                                                                  dev_global_regs->
++03391                                                                  diepmsk,
++03392                                                                  diepmsk.d32,
++03393                                                                  0);
++03394                                         }
++03395                                 } else if (core_if->dma_desc_enable
++03396                                            && epnum == 0
++03397                                            && pcd->ep0state ==
++03398                                            EP0_OUT_STATUS_PHASE) {
++03399                                         // EP0 IN set STALL
++03400                                         depctl.d32 =
++03401                                             dwc_read_reg32(&dev_if->
++03402                                                            in_ep_regs[epnum]->
++03403                                                            diepctl);
++03404 
++03405                                         /* set the disable and stall bits */
++03406                                         if (depctl.b.epena) {
++03407                                                 depctl.b.epdis = 1;
++03408                                         }
++03409                                         depctl.b.stall = 1;
++03410                                         dwc_write_reg32(&dev_if->
++03411                                                         in_ep_regs[epnum]->
++03412                                                         diepctl, depctl.d32);
++03413                                 }
++03414                                 CLEAR_IN_EP_INTR(core_if, epnum, intktxfemp);
++03415                         }
++03417                         if (diepint.b.intknepmis) {
++03418                                 DWC_DEBUGPL(DBG_ANY,
++03419                                             "EP%d IN TKN EP Mismatch\n", epnum);
++03420                                 CLEAR_IN_EP_INTR(core_if, epnum, intknepmis);
++03421                         }
++03423                         if (diepint.b.inepnakeff) {
++03424                                 DWC_DEBUGPL(DBG_ANY,
++03425                                             "EP%d IN EP NAK Effective\n",
++03426                                             epnum);
++03427                                 /* Periodic EP */
++03428                                 if (ep->disabling) {
++03429                                         depctl.d32 = 0;
++03430                                         depctl.b.snak = 1;
++03431                                         depctl.b.epdis = 1;
++03432                                         dwc_modify_reg32(&dev_if->
++03433                                                          in_ep_regs[epnum]->
++03434                                                          diepctl, depctl.d32,
++03435                                                          depctl.d32);
++03436                                 }
++03437                                 CLEAR_IN_EP_INTR(core_if, epnum, inepnakeff);
++03438 
++03439                         }
++03440 
++03442                         if (diepint.b.emptyintr) {
++03443                                 DWC_DEBUGPL(DBG_ANY,
++03444                                             "EP%d Tx FIFO Empty Intr \n",
++03445                                             epnum);
++03446                                 write_empty_tx_fifo(pcd, epnum);
++03447 
++03448                                 CLEAR_IN_EP_INTR(core_if, epnum, emptyintr);
++03449 
++03450                         }
++03451 
++03453                         if (diepint.b.bna) {
++03454                                 CLEAR_IN_EP_INTR(core_if, epnum, bna);
++03455                                 if (core_if->dma_desc_enable) {
++03456 #ifdef DWC_EN_ISOC
++03457                                         if (dwc_ep->type ==
++03458                                             DWC_OTG_EP_TYPE_ISOC) {
++03459                                                 /*
++03460                                                  * This checking is performed to prevent first "false" BNA 
++03461                                                  * handling occuring right after reconnect 
++03462                                                  */
++03463                                                 if (dwc_ep->next_frame !=
++03464                                                     0xffffffff)
++03465                                                         dwc_otg_pcd_handle_iso_bna
++03466                                                             (ep);
++03467                                         } else
++03468 #endif                          /* DWC_EN_ISOC */
++03469                                         {
++03470                                                 dctl.d32 =
++03471                                                     dwc_read_reg32(&dev_if->
++03472                                                                    dev_global_regs->
++03473                                                                    dctl);
++03474 
++03475                                                 /* If Global Continue on BNA is disabled - disable EP */
++03476                                                 if (!dctl.b.gcontbna) {
++03477                                                         depctl.d32 = 0;
++03478                                                         depctl.b.snak = 1;
++03479                                                         depctl.b.epdis = 1;
++03480                                                         dwc_modify_reg32
++03481                                                             (&dev_if->
++03482                                                              in_ep_regs[epnum]->
++03483                                                              diepctl,
++03484                                                              depctl.d32,
++03485                                                              depctl.d32);
++03486                                                 } else {
++03487                                                         start_next_request(ep);
++03488                                                 }
++03489                                         }
++03490                                 }
++03491                         }
++03492                         /* NAK Interrutp */
++03493                         if (diepint.b.nak) {
++03494                                 DWC_DEBUGPL(DBG_ANY, "EP%d IN NAK Interrupt\n",
++03495                                             epnum);
++03496                                 handle_in_ep_nak_intr(pcd, epnum);
++03497 
++03498                                 CLEAR_IN_EP_INTR(core_if, epnum, nak);
++03499                         }
++03500                 }
++03501                 epnum++;
++03502                 ep_intr >>= 1;
++03503         }
++03504 
++03505         return 1;
++03506 #undef CLEAR_IN_EP_INTR
++03507 }
++03508 
++03522 static int32_t dwc_otg_pcd_handle_out_ep_intr(dwc_otg_pcd_t * pcd)
++03523 {
++03524 #define CLEAR_OUT_EP_INTR(__core_if,__epnum,__intr) \
++03525 do { \
++03526                 doepint_data_t doepint = {.d32=0}; \
++03527                 doepint.b.__intr = 1; \
++03528                 dwc_write_reg32(&__core_if->dev_if->out_ep_regs[__epnum]->doepint, \
++03529                 doepint.d32); \
++03530 } while (0)
++03531 
++03532         dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
++03533         dwc_otg_dev_if_t *dev_if = core_if->dev_if;
++03534         uint32_t ep_intr;
++03535         doepint_data_t doepint = {.d32 = 0 };
++03536         dctl_data_t dctl = {.d32 = 0 };
++03537         depctl_data_t doepctl = {.d32 = 0 };
++03538         uint32_t epnum = 0;
++03539         dwc_otg_pcd_ep_t *ep;
++03540         dwc_ep_t *dwc_ep;
++03541 
++03542         DWC_DEBUGPL(DBG_PCDV, "%s()\n", __func__);
++03543 
++03544         /* Read in the device interrupt bits */
++03545         ep_intr = dwc_otg_read_dev_all_out_ep_intr(core_if);
++03546 
++03547         while (ep_intr) {
++03548                 if (ep_intr & 0x1) {
++03549                         /* Get EP pointer */
++03550                         ep = get_out_ep(pcd, epnum);
++03551                         dwc_ep = &ep->dwc_ep;
++03552 
++03553 #ifdef VERBOSE
++03554                         DWC_DEBUGPL(DBG_PCDV,
++03555                                     "EP%d-%s: type=%d, mps=%d\n",
++03556                                     dwc_ep->num, (dwc_ep->is_in ? "IN" : "OUT"),
++03557                                     dwc_ep->type, dwc_ep->maxpacket);
++03558 #endif
++03559                         doepint.d32 =
++03560                             dwc_otg_read_dev_out_ep_intr(core_if, dwc_ep);
++03561 
++03562                         /* Transfer complete */
++03563                         if (doepint.b.xfercompl) {
++03564 
++03565                                 if (epnum == 0) {
++03566                                         /* Clear the bit in DOEPINTn for this interrupt */
++03567                                         CLEAR_OUT_EP_INTR(core_if, epnum,
++03568                                                           xfercompl);
++03569                                         if (core_if->dma_desc_enable == 0
++03570                                             || pcd->ep0state != EP0_IDLE)
++03571                                                 handle_ep0(pcd);
++03572 #ifdef DWC_EN_ISOC
++03573                                 } else if (dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) {
++03574                                         if (doepint.b.pktdrpsts == 0) {
++03575                                                 /* Clear the bit in DOEPINTn for this interrupt */
++03576                                                 CLEAR_OUT_EP_INTR(core_if,
++03577                                                                   epnum,
++03578                                                                   xfercompl);
++03579                                                 complete_iso_ep(pcd, ep);
++03580                                         } else {
++03581 
++03582                                                 doepint_data_t doepint = {.d32 =
++03583                                                             0 };
++03584                                                 doepint.b.xfercompl = 1;
++03585                                                 doepint.b.pktdrpsts = 1;
++03586                                                 dwc_write_reg32(&core_if->
++03587                                                                 dev_if->
++03588                                                                 out_ep_regs
++03589                                                                 [epnum]->
++03590                                                                 doepint,
++03591                                                                 doepint.d32);
++03592                                                 if (handle_iso_out_pkt_dropped
++03593                                                     (core_if, dwc_ep)) {
++03594                                                         complete_iso_ep(pcd,
++03595                                                                         ep);
++03596                                                 }
++03597                                         }
++03598 #endif                          /* DWC_EN_ISOC */
++03599                                 } else {
++03600                                         /* Clear the bit in DOEPINTn for this interrupt */
++03601                                         CLEAR_OUT_EP_INTR(core_if, epnum,
++03602                                                           xfercompl);
++03603                                         complete_ep(ep);
++03604                                 }
++03605 
++03606                         }
++03607 
++03608                         /* Endpoint disable      */
++03609                         if (doepint.b.epdisabled) {
++03610 
++03611                                 /* Clear the bit in DOEPINTn for this interrupt */
++03612                                 CLEAR_OUT_EP_INTR(core_if, epnum, epdisabled);
++03613                         }
++03614                         /* AHB Error */
++03615                         if (doepint.b.ahberr) {
++03616                                 DWC_DEBUGPL(DBG_PCD, "EP%d OUT AHB Error\n",
++03617                                             epnum);
++03618                                 DWC_DEBUGPL(DBG_PCD, "EP DMA REG         %d \n",
++03619                                             core_if->dev_if->
++03620                                             out_ep_regs[epnum]->doepdma);
++03621                                 CLEAR_OUT_EP_INTR(core_if, epnum, ahberr);
++03622                         }
++03623                         /* Setup Phase Done (contorl EPs) */
++03624                         if (doepint.b.setup) {
++03625 #ifdef DEBUG_EP0
++03626                                 DWC_DEBUGPL(DBG_PCD, "EP%d SETUP Done\n",
++03627                                             epnum);
++03628 #endif
++03629                                 CLEAR_OUT_EP_INTR(core_if, epnum, setup);
++03630 
++03631                                 handle_ep0(pcd);
++03632                         }
++03633 
++03635                         if (doepint.b.bna) {
++03636                                 CLEAR_OUT_EP_INTR(core_if, epnum, bna);
++03637                                 if (core_if->dma_desc_enable) {
++03638 #ifdef DWC_EN_ISOC
++03639                                         if (dwc_ep->type ==
++03640                                             DWC_OTG_EP_TYPE_ISOC) {
++03641                                                 /*
++03642                                                  * This checking is performed to prevent first "false" BNA 
++03643                                                  * handling occuring right after reconnect 
++03644                                                  */
++03645                                                 if (dwc_ep->next_frame !=
++03646                                                     0xffffffff)
++03647                                                         dwc_otg_pcd_handle_iso_bna
++03648                                                             (ep);
++03649                                         } else
++03650 #endif                          /* DWC_EN_ISOC */
++03651                                         {
++03652                                                 dctl.d32 =
++03653                                                     dwc_read_reg32(&dev_if->
++03654                                                                    dev_global_regs->
++03655                                                                    dctl);
++03656 
++03657                                                 /* If Global Continue on BNA is disabled - disable EP */
++03658                                                 if (!dctl.b.gcontbna) {
++03659                                                         doepctl.d32 = 0;
++03660                                                         doepctl.b.snak = 1;
++03661                                                         doepctl.b.epdis = 1;
++03662                                                         dwc_modify_reg32
++03663                                                             (&dev_if->
++03664                                                              out_ep_regs
++03665                                                              [epnum]->doepctl,
++03666                                                              doepctl.d32,
++03667                                                              doepctl.d32);
++03668                                                 } else {
++03669                                                         start_next_request(ep);
++03670                                                 }
++03671                                         }
++03672                                 }
++03673                         }
++03674                         if (doepint.b.stsphsercvd) {
++03675                                 CLEAR_OUT_EP_INTR(core_if, epnum, stsphsercvd);
++03676                                 if (core_if->dma_desc_enable) {
++03677                                         do_setup_in_status_phase(pcd);
++03678                                 }
++03679                         }
++03680                         /* Babble Interrutp */
++03681                         if (doepint.b.babble) {
++03682                                 DWC_DEBUGPL(DBG_ANY, "EP%d OUT Babble\n",
++03683                                             epnum);
++03684                                 handle_out_ep_babble_intr(pcd, epnum);
++03685 
++03686                                 CLEAR_OUT_EP_INTR(core_if, epnum, babble);
++03687                         }
++03688                         /* NAK Interrutp */
++03689                         if (doepint.b.nak) {
++03690                                 DWC_DEBUGPL(DBG_ANY, "EP%d OUT NAK\n", epnum);
++03691                                 handle_out_ep_nak_intr(pcd, epnum);
++03692 
++03693                                 CLEAR_OUT_EP_INTR(core_if, epnum, nak);
++03694                         }
++03695                         /* NYET Interrutp */
++03696                         if (doepint.b.nyet) {
++03697                                 DWC_DEBUGPL(DBG_ANY, "EP%d OUT NYET\n", epnum);
++03698                                 handle_out_ep_nyet_intr(pcd, epnum);
++03699 
++03700                                 CLEAR_OUT_EP_INTR(core_if, epnum, nyet);
++03701                         }
++03702                 }
++03703 
++03704                 epnum++;
++03705                 ep_intr >>= 1;
++03706         }
++03707 
++03708         return 1;
++03709 
++03710 #undef CLEAR_OUT_EP_INTR
++03711 }
++03712 
++03725 int32_t dwc_otg_pcd_handle_incomplete_isoc_in_intr(dwc_otg_pcd_t * pcd)
++03726 {
++03727         gintsts_data_t gintsts;
++03728 
++03729 #ifdef DWC_EN_ISOC
++03730         dwc_otg_dev_if_t *dev_if;
++03731         deptsiz_data_t deptsiz = {.d32 = 0 };
++03732         depctl_data_t depctl = {.d32 = 0 };
++03733         dsts_data_t dsts = {.d32 = 0 };
++03734         dwc_ep_t *dwc_ep;
++03735         int i;
++03736 
++03737         dev_if = GET_CORE_IF(pcd)->dev_if;
++03738 
++03739         for (i = 1; i <= dev_if->num_in_eps; ++i) {
++03740                 dwc_ep = &pcd->in_ep[i].dwc_ep;
++03741                 if (dwc_ep->active && dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) {
++03742                         deptsiz.d32 =
++03743                             dwc_read_reg32(&dev_if->in_ep_regs[i]->dieptsiz);
++03744                         depctl.d32 =
++03745                             dwc_read_reg32(&dev_if->in_ep_regs[i]->diepctl);
++03746 
++03747                         if (depctl.b.epdis && deptsiz.d32) {
++03748                                 set_current_pkt_info(GET_CORE_IF(pcd), dwc_ep);
++03749                                 if (dwc_ep->cur_pkt >= dwc_ep->pkt_cnt) {
++03750                                         dwc_ep->cur_pkt = 0;
++03751                                         dwc_ep->proc_buf_num =
++03752                                             (dwc_ep->proc_buf_num ^ 1) & 0x1;
++03753 
++03754                                         if (dwc_ep->proc_buf_num) {
++03755                                                 dwc_ep->cur_pkt_addr =
++03756                                                     dwc_ep->xfer_buff1;
++03757                                                 dwc_ep->cur_pkt_dma_addr =
++03758                                                     dwc_ep->dma_addr1;
++03759                                         } else {
++03760                                                 dwc_ep->cur_pkt_addr =
++03761                                                     dwc_ep->xfer_buff0;
++03762                                                 dwc_ep->cur_pkt_dma_addr =
++03763                                                     dwc_ep->dma_addr0;
++03764                                         }
++03765 
++03766                                 }
++03767 
++03768                                 dsts.d32 =
++03769                                     dwc_read_reg32(&GET_CORE_IF(pcd)->dev_if->
++03770                                                    dev_global_regs->dsts);
++03771                                 dwc_ep->next_frame = dsts.b.soffn;
++03772 
++03773                                 dwc_otg_iso_ep_start_frm_transfer(GET_CORE_IF
++03774                                                                   (pcd),
++03775                                                                   dwc_ep);
++03776                         }
++03777                 }
++03778         }
++03779 
++03780 #else
++03781         gintmsk_data_t intr_mask = {.d32 = 0 };
++03782         DWC_PRINTF("INTERRUPT Handler not implemented for %s\n",
++03783                    "IN ISOC Incomplete");
++03784 
++03785         intr_mask.b.incomplisoin = 1;
++03786         dwc_modify_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk,
++03787                          intr_mask.d32, 0);
++03788 #endif                          //DWC_EN_ISOC
++03789 
++03790         /* Clear interrupt */
++03791         gintsts.d32 = 0;
++03792         gintsts.b.incomplisoin = 1;
++03793         dwc_write_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
++03794                         gintsts.d32);
++03795 
++03796         return 1;
++03797 }
++03798 
++03814 int32_t dwc_otg_pcd_handle_incomplete_isoc_out_intr(dwc_otg_pcd_t * pcd)
++03815 {
++03816 
++03817         gintsts_data_t gintsts;
++03818 
++03819 #ifdef DWC_EN_ISOC
++03820         dwc_otg_dev_if_t *dev_if;
++03821         deptsiz_data_t deptsiz = {.d32 = 0 };
++03822         depctl_data_t depctl = {.d32 = 0 };
++03823         dsts_data_t dsts = {.d32 = 0 };
++03824         dwc_ep_t *dwc_ep;
++03825         int i;
++03826 
++03827         dev_if = GET_CORE_IF(pcd)->dev_if;
++03828 
++03829         for (i = 1; i <= dev_if->num_out_eps; ++i) {
++03830                 dwc_ep = &pcd->in_ep[i].dwc_ep;
++03831                 if (pcd->out_ep[i].dwc_ep.active &&
++03832                     pcd->out_ep[i].dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) {
++03833                         deptsiz.d32 =
++03834                             dwc_read_reg32(&dev_if->out_ep_regs[i]->doeptsiz);
++03835                         depctl.d32 =
++03836                             dwc_read_reg32(&dev_if->out_ep_regs[i]->doepctl);
++03837 
++03838                         if (depctl.b.epdis && deptsiz.d32) {
++03839                                 set_current_pkt_info(GET_CORE_IF(pcd),
++03840                                                      &pcd->out_ep[i].dwc_ep);
++03841                                 if (dwc_ep->cur_pkt >= dwc_ep->pkt_cnt) {
++03842                                         dwc_ep->cur_pkt = 0;
++03843                                         dwc_ep->proc_buf_num =
++03844                                             (dwc_ep->proc_buf_num ^ 1) & 0x1;
++03845 
++03846                                         if (dwc_ep->proc_buf_num) {
++03847                                                 dwc_ep->cur_pkt_addr =
++03848                                                     dwc_ep->xfer_buff1;
++03849                                                 dwc_ep->cur_pkt_dma_addr =
++03850                                                     dwc_ep->dma_addr1;
++03851                                         } else {
++03852                                                 dwc_ep->cur_pkt_addr =
++03853                                                     dwc_ep->xfer_buff0;
++03854                                                 dwc_ep->cur_pkt_dma_addr =
++03855                                                     dwc_ep->dma_addr0;
++03856                                         }
++03857 
++03858                                 }
++03859 
++03860                                 dsts.d32 =
++03861                                     dwc_read_reg32(&GET_CORE_IF(pcd)->dev_if->
++03862                                                    dev_global_regs->dsts);
++03863                                 dwc_ep->next_frame = dsts.b.soffn;
++03864 
++03865                                 dwc_otg_iso_ep_start_frm_transfer(GET_CORE_IF
++03866                                                                   (pcd),
++03867                                                                   dwc_ep);
++03868                         }
++03869                 }
++03870         }
++03871 #else
++03872 
++03873         gintmsk_data_t intr_mask = {.d32 = 0 };
++03874 
++03875         DWC_PRINTF("INTERRUPT Handler not implemented for %s\n",
++03876                    "OUT ISOC Incomplete");
++03877 
++03878         intr_mask.b.incomplisoout = 1;
++03879         dwc_modify_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk,
++03880                          intr_mask.d32, 0);
++03881 
++03882 #endif                          /* DWC_EN_ISOC */
++03883 
++03884         /* Clear interrupt */
++03885         gintsts.d32 = 0;
++03886         gintsts.b.incomplisoout = 1;
++03887         dwc_write_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
++03888                         gintsts.d32);
++03889 
++03890         return 1;
++03891 }
++03892 
++03897 int32_t dwc_otg_pcd_handle_in_nak_effective(dwc_otg_pcd_t * pcd)
++03898 {
++03899         dwc_otg_dev_if_t *dev_if = GET_CORE_IF(pcd)->dev_if;
++03900         depctl_data_t diepctl = {.d32 = 0 };
++03901         depctl_data_t diepctl_rd = {.d32 = 0 };
++03902         gintmsk_data_t intr_mask = {.d32 = 0 };
++03903         gintsts_data_t gintsts;
++03904         int i;
++03905 
++03906         DWC_DEBUGPL(DBG_PCD, "Global IN NAK Effective\n");
++03907 
++03908         /* Disable all active IN EPs */
++03909         diepctl.b.epdis = 1;
++03910         diepctl.b.snak = 1;
++03911 
++03912         for (i = 0; i <= dev_if->num_in_eps; i++) {
++03913                 diepctl_rd.d32 =
++03914                     dwc_read_reg32(&dev_if->in_ep_regs[i]->diepctl);
++03915                 if (diepctl_rd.b.epena) {
++03916                         dwc_write_reg32(&dev_if->in_ep_regs[i]->diepctl,
++03917                                         diepctl.d32);
++03918                 }
++03919         }
++03920         /* Disable the Global IN NAK Effective Interrupt */
++03921         intr_mask.b.ginnakeff = 1;
++03922         dwc_modify_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk,
++03923                          intr_mask.d32, 0);
++03924 
++03925         /* Clear interrupt */
++03926         gintsts.d32 = 0;
++03927         gintsts.b.ginnakeff = 1;
++03928         dwc_write_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
++03929                         gintsts.d32);
++03930 
++03931         return 1;
++03932 }
++03933 
++03938 int32_t dwc_otg_pcd_handle_out_nak_effective(dwc_otg_pcd_t * pcd)
++03939 {
++03940         gintmsk_data_t intr_mask = {.d32 = 0 };
++03941         gintsts_data_t gintsts;
++03942 
++03943         DWC_PRINTF("INTERRUPT Handler not implemented for %s\n",
++03944                    "Global IN NAK Effective\n");
++03945         /* Disable the Global IN NAK Effective Interrupt */
++03946         intr_mask.b.goutnakeff = 1;
++03947         dwc_modify_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk,
++03948                          intr_mask.d32, 0);
++03949 
++03950         /* Clear interrupt */
++03951         gintsts.d32 = 0;
++03952         gintsts.b.goutnakeff = 1;
++03953         dwc_write_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
++03954                         gintsts.d32);
++03955 
++03956         return 1;
++03957 }
++03958 
++03971 int32_t dwc_otg_pcd_handle_intr(dwc_otg_pcd_t * pcd)
++03972 {
++03973         dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
++03974 #ifdef VERBOSE
++03975         dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
++03976 #endif
++03977         gintsts_data_t gintr_status;
++03978         int32_t retval = 0;
++03979 
++03980 #ifdef VERBOSE
++03981         DWC_DEBUGPL(DBG_ANY, "%s() gintsts=%08x  gintmsk=%08x\n",
++03982                     __func__,
++03983                     dwc_read_reg32(&global_regs->gintsts),
++03984                     dwc_read_reg32(&global_regs->gintmsk));
++03985 #endif
++03986 
++03987         if (dwc_otg_is_device_mode(core_if)) {
++03988                 DWC_SPINLOCK(pcd->lock);
++03989 #ifdef VERBOSE
++03990                 DWC_DEBUGPL(DBG_PCDV, "%s() gintsts=%08x  gintmsk=%08x\n",
++03991                             __func__,
++03992                             dwc_read_reg32(&global_regs->gintsts),
++03993                             dwc_read_reg32(&global_regs->gintmsk));
++03994 #endif
++03995 
++03996                 gintr_status.d32 = dwc_otg_read_core_intr(core_if);
++03997 
++03998                 DWC_DEBUGPL(DBG_PCDV, "%s: gintsts&gintmsk=%08x\n",
++03999                             __func__, gintr_status.d32);
++04000 
++04001                 if (gintr_status.b.sofintr) {
++04002                         retval |= dwc_otg_pcd_handle_sof_intr(pcd);
++04003                 }
++04004                 if (gintr_status.b.rxstsqlvl) {
++04005                         retval |=
++04006                             dwc_otg_pcd_handle_rx_status_q_level_intr(pcd);
++04007                 }
++04008                 if (gintr_status.b.nptxfempty) {
++04009                         retval |= dwc_otg_pcd_handle_np_tx_fifo_empty_intr(pcd);
++04010                 }
++04011                 if (gintr_status.b.ginnakeff) {
++04012                         retval |= dwc_otg_pcd_handle_in_nak_effective(pcd);
++04013                 }
++04014                 if (gintr_status.b.goutnakeff) {
++04015                         retval |= dwc_otg_pcd_handle_out_nak_effective(pcd);
++04016                 }
++04017                 if (gintr_status.b.i2cintr) {
++04018                         retval |= dwc_otg_pcd_handle_i2c_intr(pcd);
++04019                 }
++04020                 if (gintr_status.b.erlysuspend) {
++04021                         retval |= dwc_otg_pcd_handle_early_suspend_intr(pcd);
++04022                 }
++04023                 if (gintr_status.b.usbreset) {
++04024                         retval |= dwc_otg_pcd_handle_usb_reset_intr(pcd);
++04025                 }
++04026                 if (gintr_status.b.enumdone) {
++04027                         retval |= dwc_otg_pcd_handle_enum_done_intr(pcd);
++04028                 }
++04029                 if (gintr_status.b.isooutdrop) {
++04030                         retval |=
++04031                             dwc_otg_pcd_handle_isoc_out_packet_dropped_intr
++04032                             (pcd);
++04033                 }
++04034                 if (gintr_status.b.eopframe) {
++04035                         retval |=
++04036                             dwc_otg_pcd_handle_end_periodic_frame_intr(pcd);
++04037                 }
++04038                 if (gintr_status.b.epmismatch) {
++04039                         retval |= dwc_otg_pcd_handle_ep_mismatch_intr(core_if);
++04040                 }
++04041                 if (gintr_status.b.inepint) {
++04042                         if (!core_if->multiproc_int_enable) {
++04043                                 retval |= dwc_otg_pcd_handle_in_ep_intr(pcd);
++04044                         }
++04045                 }
++04046                 if (gintr_status.b.outepintr) {
++04047                         if (!core_if->multiproc_int_enable) {
++04048                                 retval |= dwc_otg_pcd_handle_out_ep_intr(pcd);
++04049                         }
++04050                 }
++04051                 if (gintr_status.b.incomplisoin) {
++04052                         retval |=
++04053                             dwc_otg_pcd_handle_incomplete_isoc_in_intr(pcd);
++04054                 }
++04055                 if (gintr_status.b.incomplisoout) {
++04056                         retval |=
++04057                             dwc_otg_pcd_handle_incomplete_isoc_out_intr(pcd);
++04058                 }
++04059 
++04060                 /* In MPI mode De vice Endpoints intterrupts are asserted 
++04061                  * without setting outepintr and inepint bits set, so these
++04062                  * Interrupt handlers are called without checking these bit-fields
++04063                  */
++04064                 if (core_if->multiproc_int_enable) {
++04065                         retval |= dwc_otg_pcd_handle_in_ep_intr(pcd);
++04066                         retval |= dwc_otg_pcd_handle_out_ep_intr(pcd);
++04067                 }
++04068 #ifdef VERBOSE
++04069                 DWC_DEBUGPL(DBG_PCDV, "%s() gintsts=%0x\n", __func__,
++04070                             dwc_read_reg32(&global_regs->gintsts));
++04071 #endif
++04072                 DWC_SPINUNLOCK(pcd->lock);
++04073         }
++04074         return retval;
++04075 }
++04076 
++04077 #endif                          /* DWC_HOST_ONLY */
++
Generated on Tue May 5 02:22:48 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__pcd__intr_8c.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__pcd__intr_8c.html 2013-07-26 19:31:21.000000000 +0000 +@@ -0,0 +1,1599 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_pcd_intr.c File Reference ++ ++ ++ ++ ++
++
++
++
++

dwc_otg_pcd_intr.c File Reference

This file contains the implementation of the PCD Interrupt handlers. More... ++

++#include "dwc_otg_pcd.h"
++ ++

++Go to the source code of this file. ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++

Defines

++#define DEBUG_EP0
#define CLEAR_IN_EP_INTR(__core_if, __epnum, __intr)
#define CLEAR_OUT_EP_INTR(__core_if, __epnum, __intr)

Functions

++static void dwc_otg_pcd_update_otg (dwc_otg_pcd_t *pcd, const unsigned reset)
 This function updates OTG.
++static void print_ep0_state (dwc_otg_pcd_t *pcd)
 This function prints the ep0 state for debug purposes.
++static dwc_otg_pcd_ep_t * get_in_ep (dwc_otg_pcd_t *pcd, uint32_t ep_num)
 This function returns pointer to in ep struct with number ep_num.
++static dwc_otg_pcd_ep_t * get_out_ep (dwc_otg_pcd_t *pcd, uint32_t ep_num)
 This function returns pointer to out ep struct with number ep_num.
++dwc_otg_pcd_ep_t * get_ep_by_addr (dwc_otg_pcd_t *pcd, u16 wIndex)
 This functions gets a pointer to an EP from the wIndex address value of the control request.
++void start_next_request (dwc_otg_pcd_ep_t *ep)
 Tasklet.
int32_t dwc_otg_pcd_handle_sof_intr (dwc_otg_pcd_t *pcd)
 This function handles the SOF Interrupts.
int32_t dwc_otg_pcd_handle_rx_status_q_level_intr (dwc_otg_pcd_t *pcd)
 This function handles the Rx Status Queue Level Interrupt, which indicates that there is a least one packet in the Rx FIFO.
static int get_ep_of_last_in_token (dwc_otg_core_if_t *core_if)
 This function examines the Device IN Token Learning Queue to determine the EP number of the last IN token received.
int32_t dwc_otg_pcd_handle_np_tx_fifo_empty_intr (dwc_otg_pcd_t *pcd)
 This interrupt occurs when the non-periodic Tx FIFO is half-empty.
static int32_t write_empty_tx_fifo (dwc_otg_pcd_t *pcd, uint32_t epnum)
 This function is called when dedicated Tx FIFO Empty interrupt occurs.
void dwc_otg_pcd_stop (dwc_otg_pcd_t *pcd)
 This function is called when the Device is disconnected.
int32_t dwc_otg_pcd_handle_i2c_intr (dwc_otg_pcd_t *pcd)
 This interrupt indicates that .
int32_t dwc_otg_pcd_handle_early_suspend_intr (dwc_otg_pcd_t *pcd)
 This interrupt indicates that .
static void ep0_out_start (dwc_otg_core_if_t *core_if, dwc_otg_pcd_t *pcd)
 This function configures EPO to receive SETUP packets.
int32_t dwc_otg_pcd_handle_usb_reset_intr (dwc_otg_pcd_t *pcd)
 This interrupt occurs when a USB Reset is detected.
static int get_device_speed (dwc_otg_core_if_t *core_if)
 Get the device speed from the device status register and convert it to USB speed constant.
int32_t dwc_otg_pcd_handle_enum_done_intr (dwc_otg_pcd_t *pcd)
 Read the device status register and set the device speed in the data structure.
int32_t dwc_otg_pcd_handle_isoc_out_packet_dropped_intr (dwc_otg_pcd_t *pcd)
 This interrupt indicates that the ISO OUT Packet was dropped due to Rx FIFO full or Rx Status Queue Full.
int32_t dwc_otg_pcd_handle_end_periodic_frame_intr (dwc_otg_pcd_t *pcd)
 This interrupt indicates the end of the portion of the micro-frame for periodic transactions.
int32_t dwc_otg_pcd_handle_ep_mismatch_intr (dwc_otg_core_if_t *core_if)
 This interrupt indicates that EP of the packet on the top of the non-periodic Tx FIFO does not match EP of the IN Token received.
++static void ep0_do_stall (dwc_otg_pcd_t *pcd, const int err_val)
 This funcion stalls EP0.
static void do_gadget_setup (dwc_otg_pcd_t *pcd, usb_device_request_t *ctrl)
 This functions delegates the setup command to the gadget driver.
++static void do_setup_in_status_phase (dwc_otg_pcd_t *pcd)
 This function starts the Zero-Length Packet for the IN status phase of a 2 stage control transfer.
++static void do_setup_out_status_phase (dwc_otg_pcd_t *pcd)
 This function starts the Zero-Length Packet for the OUT status phase of a 2 stage control transfer.
static void pcd_clear_halt (dwc_otg_pcd_t *pcd, dwc_otg_pcd_ep_t *ep)
 Clear the EP halt (STALL) and if pending requests start the transfer.
void do_test_mode (void *data)
 This function is called when the SET_FEATURE TEST_MODE Setup packet is sent from the host.
static void do_get_status (dwc_otg_pcd_t *pcd)
 This function process the GET_STATUS Setup Commands.
static void do_set_feature (dwc_otg_pcd_t *pcd)
 This function process the SET_FEATURE Setup Commands.
static void do_clear_feature (dwc_otg_pcd_t *pcd)
 This function process the CLEAR_FEATURE Setup Commands.
++static void do_set_address (dwc_otg_pcd_t *pcd)
 This function process the SET_ADDRESS Setup Commands.
static void pcd_setup (dwc_otg_pcd_t *pcd)
 This function processes SETUP commands.
++static int32_t ep0_complete_request (dwc_otg_pcd_ep_t *ep)
 This function completes the ep0 control transfer.
static void complete_ep (dwc_otg_pcd_ep_t *ep)
 This function completes the request for the EP.
++static void dwc_otg_pcd_handle_iso_bna (dwc_otg_pcd_ep_t *ep)
 This function BNA interrupt for Isochronous EPs.
void set_current_pkt_info (dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
 This function sets latest iso packet information(non-PTI mode).
static void set_ddma_iso_pkts_info (dwc_otg_core_if_t *core_if, dwc_ep_t *dwc_ep)
 This function sets latest iso packet information(DDMA mode).
static void reinit_ddma_iso_xfer (dwc_otg_core_if_t *core_if, dwc_ep_t *dwc_ep)
 This function reinitialize DMA Descriptors for Isochronous transfer.
static uint32_t handle_iso_out_pkt_dropped (dwc_otg_core_if_t *core_if, dwc_ep_t *dwc_ep)
 This function is to handle Iso EP transfer complete interrupt in case Iso out packet was dropped.
static uint32_t set_iso_pkts_info (dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
 This function sets iso packets information(PTI mode).
static void complete_iso_ep (dwc_otg_pcd_t *pcd, dwc_otg_pcd_ep_t *ep)
 This function is to handle Iso EP transfer complete interrupt.
static void handle_ep0 (dwc_otg_pcd_t *pcd)
 This function handles EP0 Control transfers.
++static void restart_transfer (dwc_otg_pcd_t *pcd, const uint32_t epnum)
 Restart transfer.
++static void handle_in_ep_disable_intr (dwc_otg_pcd_t *pcd, const uint32_t epnum)
 handle the IN EP disable interrupt.
static void handle_in_ep_timeout_intr (dwc_otg_pcd_t *pcd, const uint32_t epnum)
 Handler for the IN EP timeout handshake interrupt.
static int32_t handle_in_ep_nak_intr (dwc_otg_pcd_t *pcd, const uint32_t epnum)
 Handler for the IN EP NAK interrupt.
static int32_t handle_out_ep_babble_intr (dwc_otg_pcd_t *pcd, const uint32_t epnum)
 Handler for the OUT EP Babble interrupt.
static int32_t handle_out_ep_nak_intr (dwc_otg_pcd_t *pcd, const uint32_t epnum)
 Handler for the OUT EP NAK interrupt.
static int32_t handle_out_ep_nyet_intr (dwc_otg_pcd_t *pcd, const uint32_t epnum)
 Handler for the OUT EP NYET interrupt.
static int32_t dwc_otg_pcd_handle_in_ep_intr (dwc_otg_pcd_t *pcd)
 This interrupt indicates that an IN EP has a pending Interrupt.
static int32_t dwc_otg_pcd_handle_out_ep_intr (dwc_otg_pcd_t *pcd)
 This interrupt indicates that an OUT EP has a pending Interrupt.
int32_t dwc_otg_pcd_handle_incomplete_isoc_in_intr (dwc_otg_pcd_t *pcd)
 Incomplete ISO IN Transfer Interrupt.
int32_t dwc_otg_pcd_handle_incomplete_isoc_out_intr (dwc_otg_pcd_t *pcd)
 Incomplete ISO OUT Transfer Interrupt.
++int32_t dwc_otg_pcd_handle_in_nak_effective (dwc_otg_pcd_t *pcd)
 This function handles the Global IN NAK Effective interrupt.
++int32_t dwc_otg_pcd_handle_out_nak_effective (dwc_otg_pcd_t *pcd)
 OUT NAK Effective.
int32_t dwc_otg_pcd_handle_intr (dwc_otg_pcd_t *pcd)
 This function should be called on every hardware interrupt.
++

Detailed Description

++This file contains the implementation of the PCD Interrupt handlers. ++

++The PCD handles the device interrupts. Many conditions can cause a device interrupt. When an interrupt occurs, the device interrupt service routine determines the cause of the interrupt and dispatches handling to the appropriate function. These interrupt handling functions are described below. All interrupt registers are processed from LSB to MSB. ++

++Definition in file dwc_otg_pcd_intr.c.

Define Documentation

++ ++
++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
#define CLEAR_IN_EP_INTR (__core_if,
__epnum,
__intr   ) 
++
++
++ ++

++Value:

do { \
++                diepint_data_t diepint = {.d32=0}; \
++                diepint.b.__intr = 1; \
++                dwc_write_reg32(&__core_if->dev_if->in_ep_regs[__epnum]->diepint, \
++                diepint.d32); \
++} while (0)
++
++
++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
#define CLEAR_OUT_EP_INTR (__core_if,
__epnum,
__intr   ) 
++
++
++ ++

++Value:

do { \
++                doepint_data_t doepint = {.d32=0}; \
++                doepint.b.__intr = 1; \
++                dwc_write_reg32(&__core_if->dev_if->out_ep_regs[__epnum]->doepint, \
++                doepint.d32); \
++} while (0)
++
++
++

++

Function Documentation

++ ++
++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int32_t dwc_otg_pcd_handle_sof_intr (dwc_otg_pcd_t *  pcd  ) 
++
++
++ ++

++This function handles the SOF Interrupts. ++

++At this time the SOF Interrupt is disabled. ++

++Definition at line 252 of file dwc_otg_pcd_intr.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int32_t dwc_otg_pcd_handle_rx_status_q_level_intr (dwc_otg_pcd_t *  pcd  ) 
++
++
++ ++

++This function handles the Rx Status Queue Level Interrupt, which indicates that there is a least one packet in the Rx FIFO. ++

++The packets are moved from the FIFO to memory, where they will be processed when the Endpoint Interrupt Register indicates Transfer Complete or SETUP Phase Done.

++Repeat the following until the Rx Status Queue is empty:

    ++
  1. Read the Receive Status Pop Register (GRXSTSP) to get Packet info
  2. If Receive FIFO is empty then skip to step Clear the interrupt and exit
  3. If SETUP Packet call dwc_otg_read_setup_packet to copy the SETUP data to the buffer
  4. If OUT Data Packet call dwc_otg_read_packet to copy the data to the destination buffer
++ ++

++

Todo:
NGS Check for buffer overflow?
++ ++

++Definition at line 285 of file dwc_otg_pcd_intr.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
static int get_ep_of_last_in_token (dwc_otg_core_if_t *  core_if  )  [inline, static]
++
++
++ ++

++This function examines the Device IN Token Learning Queue to determine the EP number of the last IN token received. ++

++This implementation is for the Mass Storage device where there are only 2 IN EPs (Control-IN and BULK-IN).

++The EP numbers for the first six IN Tokens are in DTKNQR1 and there are 8 EP Numbers in each of the other possible DTKNQ Registers.

++

Parameters:
++ ++ ++
core_if Programming view of DWC_otg controller.
++
++ ++

++

Todo:
Find a simpler way to calculate the max queue position.
++ ++

++Definition at line 378 of file dwc_otg_pcd_intr.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int32_t dwc_otg_pcd_handle_np_tx_fifo_empty_intr (dwc_otg_pcd_t *  pcd  ) 
++
++
++ ++

++This interrupt occurs when the non-periodic Tx FIFO is half-empty. ++

++The active request is checked for the next packet to be loaded into the non-periodic Tx FIFO. ++

++Definition at line 451 of file dwc_otg_pcd_intr.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
static int32_t write_empty_tx_fifo (dwc_otg_pcd_t *  pcd,
uint32_t  epnum 
) [static]
++
++
++ ++

++This function is called when dedicated Tx FIFO Empty interrupt occurs. ++

++The active request is checked for the next packet to be loaded into apropriate Tx FIFO. ++

++Definition at line 515 of file dwc_otg_pcd_intr.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_otg_pcd_stop (dwc_otg_pcd_t *  pcd  ) 
++
++
++ ++

++This function is called when the Device is disconnected. ++

++It stops any active requests and informs the Gadget driver of the disconnect. ++

++

Todo:
NGS Flush Periodic FIFOs
++ ++

++Definition at line 573 of file dwc_otg_pcd_intr.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int32_t dwc_otg_pcd_handle_i2c_intr (dwc_otg_pcd_t *  pcd  ) 
++
++
++ ++

++This interrupt indicates that . ++

++.. ++

++Definition at line 632 of file dwc_otg_pcd_intr.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int32_t dwc_otg_pcd_handle_early_suspend_intr (dwc_otg_pcd_t *  pcd  ) 
++
++
++ ++

++This interrupt indicates that . ++

++.. ++

++Definition at line 653 of file dwc_otg_pcd_intr.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
static void ep0_out_start (dwc_otg_core_if_t *  core_if,
dwc_otg_pcd_t *  pcd 
) [inline, static]
++
++
++ ++

++This function configures EPO to receive SETUP packets. ++

++

Todo:
NGS: Update the comments from the HW FS.
++
    ++
  1. Program the following fields in the endpoint specific registers for Control OUT EP 0, in order to receive a setup packet
++
    ++
  • DOEPTSIZ0.Packet Count = 3 (To receive up to 3 back to back setup packets)
  • DOEPTSIZE0.Transfer Size = 24 Bytes (To receive up to 3 back to back setup packets)
      ++
    • In DMA mode, DOEPDMA0 Register with a memory address to store any setup packets received
    ++
++

++

Parameters:
++ ++ ++ ++
core_if Programming view of DWC_otg controller.
pcd Programming view of the PCD.
++
++ ++

++put here as for Hermes mode deptisz register should not be written

++

Todo:
dma needs to handle multiple setup packets (up to 3)
++

++DMA Descriptor Setup

++DOEPDMA0 Register write

++put here as for Hermes mode deptisz register should not be written

++DOEPCTL0 Register write ++

++Definition at line 684 of file dwc_otg_pcd_intr.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int32_t dwc_otg_pcd_handle_usb_reset_intr (dwc_otg_pcd_t *  pcd  ) 
++
++
++ ++

++This interrupt occurs when a USB Reset is detected. ++

++When the USB Reset Interrupt occurs the device state is set to DEFAULT and the EP0 state is set to IDLE.

    ++
  1. Set the NAK bit for all OUT endpoints (DOEPCTLn.SNAK = 1)
  2. Unmask the following interrupt bits
      ++
    • DAINTMSK.INEP0 = 1 (Control 0 IN endpoint)
    ++
++
    ++
  • DAINTMSK.OUTEP0 = 1 (Control 0 OUT endpoint)
  • DOEPMSK.SETUP = 1
  • DOEPMSK.XferCompl = 1
  • DIEPMSK.XferCompl = 1
  • DIEPMSK.TimeOut = 1
++
    ++
  1. Program the following fields in the endpoint specific registers for Control OUT EP 0, in order to receive a setup packet
++
    ++
  • DOEPTSIZ0.Packet Count = 3 (To receive up to 3 back to back setup packets)
  • DOEPTSIZE0.Transfer Size = 24 Bytes (To receive up to 3 back to back setup packets)
      ++
    • In DMA mode, DOEPDMA0 Register with a memory address to store any setup packets received At this point, all the required initialization, except for enabling the control 0 OUT endpoint is done, for receiving SETUP packets.
    ++
++ ++

++Definition at line 772 of file dwc_otg_pcd_intr.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
static int get_device_speed (dwc_otg_core_if_t *  core_if  )  [static]
++
++
++ ++

++Get the device speed from the device status register and convert it to USB speed constant. ++

++

Parameters:
++ ++ ++
core_if Programming view of DWC_otg controller.
++
++ ++

++Definition at line 928 of file dwc_otg_pcd_intr.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int32_t dwc_otg_pcd_handle_enum_done_intr (dwc_otg_pcd_t *  pcd  ) 
++
++
++ ++

++Read the device status register and set the device speed in the data structure. ++

++Set up EP0 to receive SETUP packets by calling dwc_ep0_activate. ++

++Definition at line 956 of file dwc_otg_pcd_intr.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int32_t dwc_otg_pcd_handle_isoc_out_packet_dropped_intr (dwc_otg_pcd_t *  pcd  ) 
++
++
++ ++

++This interrupt indicates that the ISO OUT Packet was dropped due to Rx FIFO full or Rx Status Queue Full. ++

++If this interrupt occurs read all the data from the Rx FIFO. ++

++Definition at line 1051 of file dwc_otg_pcd_intr.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int32_t dwc_otg_pcd_handle_end_periodic_frame_intr (dwc_otg_pcd_t *  pcd  ) 
++
++
++ ++

++This interrupt indicates the end of the portion of the micro-frame for periodic transactions. ++

++If there is a periodic transaction for the next frame, load the packets into the EP periodic Tx FIFO. ++

++Definition at line 1077 of file dwc_otg_pcd_intr.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int32_t dwc_otg_pcd_handle_ep_mismatch_intr (dwc_otg_core_if_t *  core_if  ) 
++
++
++ ++

++This interrupt indicates that EP of the packet on the top of the non-periodic Tx FIFO does not match EP of the IN Token received. ++

++The "Device IN Token Queue" Registers are read to determine the order the IN Tokens have been received. The non-periodic Tx FIFO is flushed, so it can be reloaded in the order seen in the IN Token Queue. ++

++Definition at line 1105 of file dwc_otg_pcd_intr.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
static void do_gadget_setup (dwc_otg_pcd_t *  pcd,
usb_device_request_t *  ctrl 
) [inline, static]
++
++
++ ++

++This functions delegates the setup command to the gadget driver. ++

++ ++

++

Todo:
This is a g_file_storage gadget driver specific workaround: a DELAYED_STATUS result from the fsg_setup routine will result in the gadget queueing a EP0 IN status phase for a two-stage control transfer. Exactly the same as a SET_CONFIGURATION/SET_INTERFACE except that this is a class specific request. Need a generic way to know when the gadget driver will queue the status phase. Can we assume when we call the gadget driver setup() function that it will always queue and require the following flag? Need to look into this.
++ ++

++Definition at line 1138 of file dwc_otg_pcd_intr.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
static void pcd_clear_halt (dwc_otg_pcd_t *  pcd,
dwc_otg_pcd_ep_t *  ep 
) [inline, static]
++
++
++ ++

++Clear the EP halt (STALL) and if pending requests start the transfer. ++

++ ++

++

Todo:
FIXME: this causes an EP mismatch in DMA mode. epmismatch not yet implemented.
++ ++

++Definition at line 1245 of file dwc_otg_pcd_intr.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void do_test_mode (void *  data  ) 
++
++
++ ++

++This function is called when the SET_FEATURE TEST_MODE Setup packet is sent from the host. ++

++The Device Control register is written with the Test Mode bits set to the specified Test Mode. This is done as a tasklet so that the "Status" phase of the control transfer completes before transmitting the TEST packets.

++

Todo:
This has not been tested since the tasklet struct was put into the PCD struct!
++ ++

++Definition at line 1284 of file dwc_otg_pcd_intr.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
static void do_get_status (dwc_otg_pcd_t *  pcd  )  [inline, static]
++
++
++ ++

++This function process the GET_STATUS Setup Commands. ++

++ ++

++

Todo:
check for EP stall
++ ++

++Definition at line 1321 of file dwc_otg_pcd_intr.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
static void do_set_feature (dwc_otg_pcd_t *  pcd  )  [inline, static]
++
++
++ ++

++This function process the SET_FEATURE Setup Commands. ++

++ ++

++

Todo:
This has not been tested since the tasklet struct was put into the PCD struct!
++

++

Todo:
Is the gotgctl.devhnpen cleared by a USB Reset?
++ ++

++Definition at line 1369 of file dwc_otg_pcd_intr.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
static void do_clear_feature (dwc_otg_pcd_t *  pcd  )  [inline, static]
++
++
++ ++

++This function process the CLEAR_FEATURE Setup Commands. ++

++ ++

++

Todo:
Add CLEAR_FEATURE for TEST modes.
++ ++

++Definition at line 1472 of file dwc_otg_pcd_intr.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
static void pcd_setup (dwc_otg_pcd_t *  pcd  )  [inline, static]
++
++
++ ++

++This function processes SETUP commands. ++

++In Linux, the USB Command processing is done in two places - the first being the PCD and the second in the Gadget Driver (for example, the File-Backed Storage Gadget Driver).

++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
Command Driver Description

++

GET_STATUS PCD Command is processed as defined in chapter 9 of the USB 2.0 Specification chapter 9

++

CLEAR_FEATURE PCD The Device and Endpoint requests are the ENDPOINT_HALT feature is procesed, all others the interface requests are ignored.

++

SET_FEATURE PCD The Device and Endpoint requests are processed by the PCD. Interface requests are passed to the Gadget Driver.

++

SET_ADDRESS PCD Program the DCFG reg, with device address received

++

GET_DESCRIPTOR Gadget Driver Return the requested descriptor

++

SET_DESCRIPTOR Gadget Driver Optional - not implemented by any of the existing Gadget Drivers.

++

SET_CONFIGURATION Gadget Driver Disable all EPs and enable EPs for new configuration.

++

GET_CONFIGURATION Gadget Driver Return the current configuration

++

SET_INTERFACE Gadget Driver Disable all EPs and enable EPs for new configuration.

++

GET_INTERFACE Gadget Driver Return the current interface.

++

SYNC_FRAME PCD Display debug message.
++

++When the SETUP Phase Done interrupt occurs, the PCD SETUP commands are processed by pcd_setup. Calling the Function Driver's setup function from pcd_setup processes the gadget SETUP commands. ++

++

Todo:
handle > 1 setup packet , assert error for now
++

++

Todo:
NGS: Handle bad setup packet?
++ ++

++Definition at line 1580 of file dwc_otg_pcd_intr.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
static void complete_ep (dwc_otg_pcd_ep_t *  ep  )  [static]
++
++
++ ++

++This function completes the request for the EP. ++

++If there are additional requests for the EP in the queue they will be started. ++

++Definition at line 1911 of file dwc_otg_pcd_intr.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void set_current_pkt_info (dwc_otg_core_if_t *  core_if,
dwc_ep_t *  ep 
)
++
++
++ ++

++This function sets latest iso packet information(non-PTI mode). ++

++

Parameters:
++ ++ ++ ++
core_if Programming view of DWC_otg controller.
ep The EP to start the transfer on.
++
++ ++

++Definition at line 2274 of file dwc_otg_pcd_intr.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
static void set_ddma_iso_pkts_info (dwc_otg_core_if_t *  core_if,
dwc_ep_t *  dwc_ep 
) [static]
++
++
++ ++

++This function sets latest iso packet information(DDMA mode). ++

++

Parameters:
++ ++ ++ ++
core_if Programming view of DWC_otg controller.
dwc_ep The EP to start the transfer on.
++
++ ++

++Reinit closed DMA Descriptors

++ISO OUT EP

++ISO IN EP ++

++Definition at line 2322 of file dwc_otg_pcd_intr.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
static void reinit_ddma_iso_xfer (dwc_otg_core_if_t *  core_if,
dwc_ep_t *  dwc_ep 
) [static]
++
++
++ ++

++This function reinitialize DMA Descriptors for Isochronous transfer. ++

++

Parameters:
++ ++ ++ ++
core_if Programming view of DWC_otg controller.
dwc_ep The EP to start the transfer on.
++
++ ++

++Buffer 0 descriptors setup

++Buffer 1 descriptors setup

++Reinit closed DMA Descriptors

++ISO OUT EP

++ISO IN EP ++

++Definition at line 2486 of file dwc_otg_pcd_intr.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
static uint32_t handle_iso_out_pkt_dropped (dwc_otg_core_if_t *  core_if,
dwc_ep_t *  dwc_ep 
) [static]
++
++
++ ++

++This function is to handle Iso EP transfer complete interrupt in case Iso out packet was dropped. ++

++

Parameters:
++ ++ ++ ++
core_if Programming view of DWC_otg controller.
dwc_ep The EP for wihich transfer complete was asserted
++
++ ++

++Re-enable endpoint, clear nak ++

++Definition at line 2620 of file dwc_otg_pcd_intr.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
static uint32_t set_iso_pkts_info (dwc_otg_core_if_t *  core_if,
dwc_ep_t *  ep 
) [static]
++
++
++ ++

++This function sets iso packets information(PTI mode). ++

++

Parameters:
++ ++ ++ ++
core_if Programming view of DWC_otg controller.
ep The EP to start the transfer on.
++
++ ++

++Buffer 0 descriptors setup

++Buffer 1 descriptors setup ++

++Definition at line 2690 of file dwc_otg_pcd_intr.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
static void complete_iso_ep (dwc_otg_pcd_t *  pcd,
dwc_otg_pcd_ep_t *  ep 
) [static]
++
++
++ ++

++This function is to handle Iso EP transfer complete interrupt. ++

++

Parameters:
++ ++ ++ ++
pcd The PCD
ep The EP for which transfer complete was asserted
++
++ ++

++Definition at line 2766 of file dwc_otg_pcd_intr.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
static void handle_ep0 (dwc_otg_pcd_t *  pcd  )  [static]
++
++
++ ++

++This function handles EP0 Control transfers. ++

++The state of the control tranfers are tracked in ep0state. ++

++Definition at line 2843 of file dwc_otg_pcd_intr.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
static void handle_in_ep_timeout_intr (dwc_otg_pcd_t *  pcd,
const uint32_t  epnum 
) [inline, static]
++
++
++ ++

++Handler for the IN EP timeout handshake interrupt. ++

++ ++

++

Todo:
NGS Check EP type. Implement for Periodic EPs
++ ++

++Definition at line 3080 of file dwc_otg_pcd_intr.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
static int32_t handle_in_ep_nak_intr (dwc_otg_pcd_t *  pcd,
const uint32_t  epnum 
) [inline, static]
++
++
++ ++

++Handler for the IN EP NAK interrupt. ++

++ ++

++

Todo:
implement ISR
++ ++

++Definition at line 3141 of file dwc_otg_pcd_intr.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
static int32_t handle_out_ep_babble_intr (dwc_otg_pcd_t *  pcd,
const uint32_t  epnum 
) [inline, static]
++
++
++ ++

++Handler for the OUT EP Babble interrupt. ++

++ ++

++

Todo:
implement ISR
++ ++

++Definition at line 3166 of file dwc_otg_pcd_intr.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
static int32_t handle_out_ep_nak_intr (dwc_otg_pcd_t *  pcd,
const uint32_t  epnum 
) [inline, static]
++
++
++ ++

++Handler for the OUT EP NAK interrupt. ++

++ ++

++

Todo:
implement ISR
++ ++

++Definition at line 3192 of file dwc_otg_pcd_intr.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
static int32_t handle_out_ep_nyet_intr (dwc_otg_pcd_t *  pcd,
const uint32_t  epnum 
) [inline, static]
++
++
++ ++

++Handler for the OUT EP NYET interrupt. ++

++ ++

++

Todo:
implement ISR
++ ++

++Definition at line 3217 of file dwc_otg_pcd_intr.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
static int32_t dwc_otg_pcd_handle_in_ep_intr (dwc_otg_pcd_t *  pcd  )  [static]
++
++
++ ++

++This interrupt indicates that an IN EP has a pending Interrupt. ++

++The sequence for handling the IN EP interrupt is shown below:

    ++
  1. Read the Device All Endpoint Interrupt register
  2. Repeat the following for each IN EP interrupt bit set (from LSB to MSB).
  3. Read the Device Endpoint Interrupt (DIEPINTn) register
  4. If "Transfer Complete" call the request complete function
  5. If "Endpoint Disabled" complete the EP disable procedure.
  6. If "AHB Error Interrupt" log error
  7. If "Time-out Handshake" log error
  8. If "IN Token Received when TxFIFO Empty" write packet to Tx FIFO.
  9. If "IN Token EP Mismatch" (disable, this is handled by EP Mismatch Interrupt)
++ ++

++IN Token received with TxF Empty

++IN Token Received with EP mismatch

++IN Endpoint NAK Effective

++IN EP Tx FIFO Empty Intr

++IN EP BNA Intr ++

++Definition at line 3255 of file dwc_otg_pcd_intr.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
static int32_t dwc_otg_pcd_handle_out_ep_intr (dwc_otg_pcd_t *  pcd  )  [static]
++
++
++ ++

++This interrupt indicates that an OUT EP has a pending Interrupt. ++

++The sequence for handling the OUT EP interrupt is shown below:

    ++
  1. Read the Device All Endpoint Interrupt register
  2. Repeat the following for each OUT EP interrupt bit set (from LSB to MSB).
  3. Read the Device Endpoint Interrupt (DOEPINTn) register
  4. If "Transfer Complete" call the request complete function
  5. If "Endpoint Disabled" complete the EP disable procedure.
  6. If "AHB Error Interrupt" log error
  7. If "Setup Phase Done" process Setup Packet (See Standard USB Command Processing)
++ ++

++OUT EP BNA Intr ++

++Definition at line 3522 of file dwc_otg_pcd_intr.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int32_t dwc_otg_pcd_handle_incomplete_isoc_in_intr (dwc_otg_pcd_t *  pcd  ) 
++
++
++ ++

++Incomplete ISO IN Transfer Interrupt. ++

++This interrupt indicates one of the following conditions occurred while transmitting an ISOC transaction.

    ++
  • Corrupted IN Token for ISOC EP.
  • Packet not complete in FIFO. The follow actions will be taken:
      ++
    1. Determine the EP
    2. Set incomplete flag in dwc_ep structure
    3. Disable EP; when "Endpoint Disabled" interrupt is received Flush FIFO
    ++
++ ++

++Definition at line 3725 of file dwc_otg_pcd_intr.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int32_t dwc_otg_pcd_handle_incomplete_isoc_out_intr (dwc_otg_pcd_t *  pcd  ) 
++
++
++ ++

++Incomplete ISO OUT Transfer Interrupt. ++

++This interrupt indicates that the core has dropped an ISO OUT packet. The following conditions can be the cause:

    ++
  • FIFO Full, the entire packet would not fit in the FIFO.
  • CRC Error
  • Corrupted Token The follow actions will be taken:
      ++
    1. Determine the EP
    2. Set incomplete flag in dwc_ep structure
    3. Read any data from the FIFO
    4. Disable EP. when "Endpoint Disabled" interrupt is received re-enable EP.
    ++
++ ++

++Definition at line 3814 of file dwc_otg_pcd_intr.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int32_t dwc_otg_pcd_handle_intr (dwc_otg_pcd_t *  pcd  ) 
++
++
++ ++

++This function should be called on every hardware interrupt. ++

++The PCD handles the device interrupts. Many conditions can cause a device interrupt. When an interrupt occurs, the device interrupt service routine determines the cause of the interrupt and dispatches handling to the appropriate function. These interrupt handling functions are described below.

++All interrupt registers are processed from LSB to MSB. ++

++Definition at line 3971 of file dwc_otg_pcd_intr.c. ++

++

++

Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__pcd__linux_8c-source.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__pcd__linux_8c-source.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,997 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_pcd_linux.c Source File ++ ++ ++ ++ ++
++
++
++
++

dwc_otg_pcd_linux.c

Go to the documentation of this file.
00001  /* ==========================================================================
++00002   * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_pcd_linux.c $
++00003   * $Revision: #7 $
++00004   * $Date: 2009/04/03 $
++00005   * $Change: 1225160 $
++00006   *
++00007   * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
++00008   * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
++00009   * otherwise expressly agreed to in writing between Synopsys and you.
++00010   *
++00011   * The Software IS NOT an item of Licensed Software or Licensed Product under
++00012   * any End User Software License Agreement or Agreement for Licensed Product
++00013   * with Synopsys or any supplement thereto. You are permitted to use and
++00014   * redistribute this Software in source and binary forms, with or without
++00015   * modification, provided that redistributions of source code must retain this
++00016   * notice. You may not view, use, disclose, copy or distribute this file or
++00017   * any information contained herein except pursuant to this license grant from
++00018   * Synopsys. If you do not agree with this notice, including the disclaimer
++00019   * below, then you are not authorized to use the Software.
++00020   *
++00021   * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
++00022   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++00023   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++00024   * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
++00025   * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++00026   * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
++00027   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
++00028   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
++00029   * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
++00030   * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
++00031   * DAMAGE.
++00032   * ========================================================================== */
++00033 #ifndef DWC_HOST_ONLY
++00034 
++00056 #include <linux/kernel.h>
++00057 #include <linux/module.h>
++00058 #include <linux/moduleparam.h>
++00059 #include <linux/init.h>
++00060 #include <linux/device.h>
++00061 #include <linux/errno.h>
++00062 #include <linux/list.h>
++00063 #include <linux/interrupt.h>
++00064 #include <linux/string.h>
++00065 #include <linux/dma-mapping.h>
++00066 #include <linux/version.h>
++00067 
++00068 #ifdef LM_INTERFACE
++00069 # include <asm/arch/regs-irq.h>
++00070 # include <asm/arch/lm.h>
++00071 # include <asm/arch/irqs.h>
++00072 #endif
++00073 
++00074 #include <asm/io.h>
++00075 # include <linux/usb_ch9.h>
++00076 #include <linux/usb_gadget.h>
++00077 
++00078 #include "dwc_otg_pcd_if.h"
++00079 #include "dwc_otg_driver.h"
++00080 #include "dwc_otg_dbg.h"
++00081 
++00082 static struct gadget_wrapper {
++00083         dwc_otg_pcd_t *pcd;
++00084 
++00085         struct usb_gadget gadget;
++00086         struct usb_gadget_driver *driver;
++00087 
++00088         struct usb_ep ep0;
++00089         struct usb_ep in_ep[16];
++00090         struct usb_ep out_ep[16];
++00091 
++00092 } *gadget_wrapper;
++00093 
++00094 /* Display the contents of the buffer */
++00095 extern void dump_msg(const u8 * buf, unsigned int length);
++00096 
++00097 /* USB Endpoint Operations */
++00098 /*
++00099  * The following sections briefly describe the behavior of the Gadget
++00100  * API endpoint operations implemented in the DWC_otg driver
++00101  * software. Detailed descriptions of the generic behavior of each of
++00102  * these functions can be found in the Linux header file
++00103  * include/linux/usb_gadget.h.
++00104  *
++00105  * The Gadget API provides wrapper functions for each of the function
++00106  * pointers defined in usb_ep_ops. The Gadget Driver calls the wrapper
++00107  * function, which then calls the underlying PCD function. The
++00108  * following sections are named according to the wrapper
++00109  * functions. Within each section, the corresponding DWC_otg PCD
++00110  * function name is specified.
++00111  *
++00112  */
++00113 
++00121 static int ep_enable(struct usb_ep *usb_ep,
++00122                      const struct usb_endpoint_descriptor *ep_desc)
++00123 {
++00124         int retval;
++00125 
++00126         DWC_DEBUGPL(DBG_PCDV, "%s(%p,%p)\n", __func__, usb_ep, ep_desc);
++00127 
++00128         if (!usb_ep || !ep_desc || ep_desc->bDescriptorType != USB_DT_ENDPOINT) {
++00129                 DWC_WARN("%s, bad ep or descriptor\n", __func__);
++00130                 return -EINVAL;
++00131         }
++00132         if (usb_ep == &gadget_wrapper->ep0) {
++00133                 DWC_WARN("%s, bad ep(0)\n", __func__);
++00134                 return -EINVAL;
++00135         }
++00136 
++00137         /* Check FIFO size? */
++00138         if (!ep_desc->wMaxPacketSize) {
++00139                 DWC_WARN("%s, bad %s maxpacket\n", __func__, usb_ep->name);
++00140                 return -ERANGE;
++00141         }
++00142 
++00143         if (!gadget_wrapper->driver ||
++00144             gadget_wrapper->gadget.speed == USB_SPEED_UNKNOWN) {
++00145                 DWC_WARN("%s, bogus device state\n", __func__);
++00146                 return -ESHUTDOWN;
++00147         }
++00148 
++00149         retval = dwc_otg_pcd_ep_enable(gadget_wrapper->pcd,
++00150                                        (const uint8_t *)ep_desc,
++00151                                        (void *)usb_ep);
++00152         if (retval) {
++00153                 DWC_WARN("dwc_otg_pcd_ep_enable failed\n");
++00154                 return -EINVAL;
++00155         }
++00156 
++00157         usb_ep->maxpacket = le16_to_cpu(ep_desc->wMaxPacketSize);
++00158 
++00159         return 0;
++00160 }
++00161 
++00170 static int ep_disable(struct usb_ep *usb_ep)
++00171 {
++00172         int retval;
++00173 
++00174         DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, usb_ep);
++00175         if (!usb_ep) {
++00176                 DWC_DEBUGPL(DBG_PCD, "%s, %s not enabled\n", __func__,
++00177                             usb_ep ? usb_ep->name : NULL);
++00178                 return -EINVAL;
++00179         }
++00180 
++00181         retval = dwc_otg_pcd_ep_disable(gadget_wrapper->pcd, usb_ep);
++00182         if (retval) {
++00183                 retval = -EINVAL;
++00184         }
++00185 
++00186         return retval;
++00187 }
++00188 
++00196 static struct usb_request *dwc_otg_pcd_alloc_request(struct usb_ep *ep,
++00197                                                      gfp_t gfp_flags)
++00198 {
++00199         struct usb_request *usb_req;
++00200 
++00201         DWC_DEBUGPL(DBG_PCDV, "%s(%p,%d)\n", __func__, ep, gfp_flags);
++00202         if (0 == ep) {
++00203                 DWC_WARN("%s() %s\n", __func__, "Invalid EP!\n");
++00204                 return 0;
++00205         }
++00206         usb_req = kmalloc(sizeof(*usb_req), gfp_flags);
++00207         if (0 == usb_req) {
++00208                 DWC_WARN("%s() %s\n", __func__, "request allocation failed!\n");
++00209                 return 0;
++00210         }
++00211         memset(usb_req, 0, sizeof(*usb_req));
++00212         usb_req->dma = DWC_INVALID_DMA_ADDR;
++00213 
++00214         return usb_req;
++00215 }
++00216 
++00223 static void dwc_otg_pcd_free_request(struct usb_ep *ep, struct usb_request *req)
++00224 {
++00225         DWC_DEBUGPL(DBG_PCDV, "%s(%p,%p)\n", __func__, ep, req);
++00226 
++00227         if (0 == ep || 0 == req) {
++00228                 DWC_WARN("%s() %s\n", __func__,
++00229                          "Invalid ep or req argument!\n");
++00230                 return;
++00231         }
++00232 
++00233         kfree(req);
++00234 }
++00235 
++00246 static void *dwc_otg_pcd_alloc_buffer(struct usb_ep *usb_ep, unsigned bytes,
++00247                                       dma_addr_t * dma, gfp_t gfp_flags)
++00248 {
++00249         void *buf;
++00250         dwc_otg_pcd_t *pcd = 0;
++00251 
++00252         pcd = gadget_wrapper->pcd;
++00253 
++00254         DWC_DEBUGPL(DBG_PCDV, "%s(%p,%d,%p,%0x)\n", __func__, usb_ep, bytes,
++00255                     dma, gfp_flags);
++00256 
++00257         /* Check dword alignment */
++00258         if ((bytes & 0x3UL) != 0) {
++00259                 DWC_WARN("%s() Buffer size is not a multiple of"
++00260                          "DWORD size (%d)", __func__, bytes);
++00261         }
++00262 
++00263         buf = dma_alloc_coherent(NULL, bytes, dma, gfp_flags);
++00264 
++00265         /* Check dword alignment */
++00266         if (((int)buf & 0x3UL) != 0) {
++00267                 DWC_WARN("%s() Buffer is not DWORD aligned (%p)",
++00268                          __func__, buf);
++00269         }
++00270 
++00271         return buf;
++00272 }
++00273 
++00282 static void dwc_otg_pcd_free_buffer(struct usb_ep *usb_ep, void *buf,
++00283                                     dma_addr_t dma, unsigned bytes)
++00284 {
++00285         dwc_otg_pcd_t *pcd = 0;
++00286 
++00287         pcd = gadget_wrapper->pcd;
++00288 
++00289         DWC_DEBUGPL(DBG_PCDV, "%s(%p,%0x,%d)\n", __func__, buf, dma, bytes);
++00290 
++00291         dma_free_coherent(NULL, bytes, buf, dma);
++00292 }
++00293 
++00308 static int ep_queue(struct usb_ep *usb_ep, struct usb_request *usb_req,
++00309                     gfp_t gfp_flags)
++00310 {
++00311         dwc_otg_pcd_t *pcd;
++00312         int retval;
++00313 
++00314         DWC_DEBUGPL(DBG_PCDV, "%s(%p,%p,%d)\n",
++00315                     __func__, usb_ep, usb_req, gfp_flags);
++00316 
++00317         if (!usb_req || !usb_req->complete || !usb_req->buf) {
++00318                 DWC_WARN("bad params\n");
++00319                 return -EINVAL;
++00320         }
++00321 
++00322         if (!usb_ep) {
++00323                 DWC_WARN("bad ep\n");
++00324                 return -EINVAL;
++00325         }
++00326 
++00327         pcd = gadget_wrapper->pcd;
++00328         if (!gadget_wrapper->driver ||
++00329             gadget_wrapper->gadget.speed == USB_SPEED_UNKNOWN) {
++00330                 DWC_DEBUGPL(DBG_PCDV, "gadget.speed=%d\n",
++00331                             gadget_wrapper->gadget.speed);
++00332                 DWC_WARN("bogus device state\n");
++00333                 return -ESHUTDOWN;
++00334         }
++00335 
++00336         DWC_DEBUGPL(DBG_PCD, "%s queue req %p, len %d buf %p\n",
++00337                     usb_ep->name, usb_req, usb_req->length, usb_req->buf);
++00338 
++00339         usb_req->status = -EINPROGRESS;
++00340         usb_req->actual = 0;
++00341 
++00342         retval = dwc_otg_pcd_ep_queue(pcd, usb_ep, usb_req->buf, usb_req->dma,
++00343                                       usb_req->length, usb_req->zero, usb_req,
++00344                                       gfp_flags == GFP_ATOMIC ? 1 : 0);
++00345         if (retval) {
++00346                 return -EINVAL;
++00347         }
++00348 
++00349         return 0;
++00350 }
++00351 
++00355 static int ep_dequeue(struct usb_ep *usb_ep, struct usb_request *usb_req)
++00356 {
++00357         DWC_DEBUGPL(DBG_PCDV, "%s(%p,%p)\n", __func__, usb_ep, usb_req);
++00358 
++00359         if (!usb_ep || !usb_req) {
++00360                 DWC_WARN("bad argument\n");
++00361                 return -EINVAL;
++00362         }
++00363         if (!gadget_wrapper->driver ||
++00364             gadget_wrapper->gadget.speed == USB_SPEED_UNKNOWN) {
++00365                 DWC_WARN("bogus device state\n");
++00366                 return -ESHUTDOWN;
++00367         }
++00368         if (dwc_otg_pcd_ep_dequeue(gadget_wrapper->pcd, usb_ep, usb_req)) {
++00369                 return -EINVAL;
++00370         }
++00371 
++00372         return 0;
++00373 }
++00374 
++00391 static int ep_halt(struct usb_ep *usb_ep, int value)
++00392 {
++00393         int retval = 0;
++00394 
++00395         DWC_DEBUGPL(DBG_PCD, "HALT %s %d\n", usb_ep->name, value);
++00396 
++00397         if (!usb_ep) {
++00398                 DWC_WARN("bad ep\n");
++00399                 return -EINVAL;
++00400         }
++00401 
++00402         retval = dwc_otg_pcd_ep_halt(gadget_wrapper->pcd, usb_ep, value);
++00403         if (retval == -DWC_E_AGAIN) {
++00404                 return -EAGAIN;
++00405         } else if (retval) {
++00406                 retval = -EINVAL;
++00407         }
++00408 
++00409         return retval;
++00410 }
++00411 
++00412 #ifdef DWC_EN_ISOC
++00413 
++00422 static int iso_ep_start(struct usb_ep *usb_ep, struct usb_iso_request *req,
++00423                         gfp_t gfp_flags)
++00424 {
++00425         int retval = 0;
++00426 
++00427         if (!req || !req->process_buffer || !req->buf0 || !req->buf1) {
++00428                 DWC_WARN("bad params\n");
++00429                 return -EINVAL;
++00430         }
++00431 
++00432         if (!usb_ep) {
++00433                 DWC_PRINTF("bad params\n");
++00434                 return -EINVAL;
++00435         }
++00436 
++00437         req->status = -EINPROGRESS;
++00438 
++00439         retval =
++00440             dwc_otg_pcd_iso_ep_start(gadget_wrapper->pcd, usb_ep, req->buf0,
++00441                                      req->buf1, req->dma0, req->dma1,
++00442                                      req->sync_frame, req->data_pattern_frame,
++00443                                      req->data_per_frame,
++00444                                      req->flags & USB_REQ_ISO_ASAP ? -1 : req->
++00445                                      start_frame, req->buf_proc_intrvl, req,
++00446                                      gfp_flags == GFP_ATOMIC ? 1 : 0);
++00447 
++00448         if (retval) {
++00449                 return -EINVAL;
++00450         }
++00451 
++00452         return retval;
++00453 }
++00454 
++00458 static int iso_ep_stop(struct usb_ep *usb_ep, struct usb_iso_request *req)
++00459 {
++00460         int retval = 0;
++00461         if (!usb_ep) {
++00462                 DWC_WARN("bad ep\n");
++00463         }
++00464 
++00465         if (!gadget_wrapper->driver ||
++00466             gadget_wrapper->gadget.speed == USB_SPEED_UNKNOWN) {
++00467                 DWC_DEBUGPL(DBG_PCDV, "gadget.speed=%d\n",
++00468                             gadget_wrapper->gadget.speed);
++00469                 DWC_WARN("bogus device state\n");
++00470         }
++00471 
++00472         dwc_otg_pcd_iso_ep_stop(gadget_wrapper->pcd, usb_ep, req);
++00473         if (retval) {
++00474                 retval = -EINVAL;
++00475         }
++00476 
++00477         return retval;
++00478 }
++00479 
++00480 static struct usb_iso_request *alloc_iso_request(struct usb_ep *ep,
++00481                                                  int packets, gfp_t gfp_flags)
++00482 {
++00483         struct usb_iso_request *pReq = NULL;
++00484         uint32_t req_size;
++00485 
++00486         req_size = sizeof(struct usb_iso_request);
++00487         req_size +=
++00488             (2 * packets * (sizeof(struct usb_gadget_iso_packet_descriptor)));
++00489 
++00490         pReq = kmalloc(req_size, gfp_flags);
++00491         if (!pReq) {
++00492                 DWC_WARN("Can't allocate Iso Request\n");
++00493                 return 0;
++00494         }
++00495         pReq->iso_packet_desc0 = (void *)(pReq + 1);
++00496 
++00497         pReq->iso_packet_desc1 = pReq->iso_packet_desc0 + packets;
++00498 
++00499         return pReq;
++00500 }
++00501 
++00502 static void free_iso_request(struct usb_ep *ep, struct usb_iso_request *req)
++00503 {
++00504         kfree(req);
++00505 }
++00506 
++00507 static struct usb_isoc_ep_ops dwc_otg_pcd_ep_ops = {
++00508         .ep_ops = {
++00509                    .enable = ep_enable,
++00510                    .disable = ep_disable,
++00511 
++00512                    .alloc_request = dwc_otg_pcd_alloc_request,
++00513                    .free_request = dwc_otg_pcd_free_request,
++00514 
++00515                    .alloc_buffer = dwc_otg_pcd_alloc_buffer,
++00516                    .free_buffer = dwc_otg_pcd_free_buffer,
++00517 
++00518                    .queue = ep_queue,
++00519                    .dequeue = ep_dequeue,
++00520 
++00521                    .set_halt = ep_halt,
++00522                    .fifo_status = 0,
++00523                    .fifo_flush = 0,
++00524                    },
++00525         .iso_ep_start = iso_ep_start,
++00526         .iso_ep_stop = iso_ep_stop,
++00527         .alloc_iso_request = alloc_iso_request,
++00528         .free_iso_request = free_iso_request,
++00529 };
++00530 
++00531 #else
++00532 
++00533 static struct usb_ep_ops dwc_otg_pcd_ep_ops = {
++00534         .enable = ep_enable,
++00535         .disable = ep_disable,
++00536 
++00537         .alloc_request = dwc_otg_pcd_alloc_request,
++00538         .free_request = dwc_otg_pcd_free_request,
++00539 
++00540         .alloc_buffer = dwc_otg_pcd_alloc_buffer,
++00541         .free_buffer = dwc_otg_pcd_free_buffer,
++00542 
++00543         .queue = ep_queue,
++00544         .dequeue = ep_dequeue,
++00545 
++00546         .set_halt = ep_halt,
++00547         .fifo_status = 0,
++00548         .fifo_flush = 0,
++00549 
++00550 };
++00551 
++00552 #endif                          /* _EN_ISOC_ */
++00553 /*      Gadget Operations */
++00572 static int get_frame_number(struct usb_gadget *gadget)
++00573 {
++00574         struct gadget_wrapper *d;
++00575 
++00576         DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, gadget);
++00577 
++00578         if (gadget == 0) {
++00579                 return -ENODEV;
++00580         }
++00581 
++00582         d = container_of(gadget, struct gadget_wrapper, gadget);
++00583         return dwc_otg_pcd_get_frame_number(d->pcd);
++00584 }
++00585 
++00586 #ifdef CONFIG_USB_DWC_OTG_LPM
++00587 static int test_lpm_enabled(struct usb_gadget *gadget)
++00588 {
++00589         struct gadget_wrapper *d;
++00590 
++00591         d = container_of(gadget, struct gadget_wrapper, gadget);
++00592 
++00593         return dwc_otg_pcd_is_lpm_enabled(d->pcd);
++00594 }
++00595 #endif
++00596 
++00603 static int wakeup(struct usb_gadget *gadget)
++00604 {
++00605         struct gadget_wrapper *d;
++00606 
++00607         DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, gadget);
++00608 
++00609         if (gadget == 0) {
++00610                 return -ENODEV;
++00611         } else {
++00612                 d = container_of(gadget, struct gadget_wrapper, gadget);
++00613         }
++00614         dwc_otg_pcd_wakeup(d->pcd);
++00615         return 0;
++00616 }
++00617 
++00618 static const struct usb_gadget_ops dwc_otg_pcd_ops = {
++00619         .get_frame = get_frame_number,
++00620         .wakeup = wakeup,
++00621 #ifdef CONFIG_USB_DWC_OTG_LPM
++00622         .lpm_support = test_lpm_enabled,
++00623 #endif
++00624         // current versions must always be self-powered
++00625 };
++00626 
++00627 static int _setup(dwc_otg_pcd_t * pcd, uint8_t * bytes)
++00628 {
++00629         int retval = -DWC_E_NOT_SUPPORTED;
++00630         if (gadget_wrapper->driver && gadget_wrapper->driver->setup) {
++00631                 retval = gadget_wrapper->driver->setup(&gadget_wrapper->gadget,
++00632                                                        (struct usb_ctrlrequest
++00633                                                         *)bytes);
++00634         }
++00635 
++00636         if (retval == -ENOTSUPP) {
++00637                 retval = -DWC_E_NOT_SUPPORTED;
++00638         } else if (retval < 0) {
++00639                 retval = -DWC_E_INVALID;
++00640         }
++00641 
++00642         return retval;
++00643 }
++00644 
++00645 #ifdef DWC_EN_ISOC
++00646 static int _isoc_complete(dwc_otg_pcd_t * pcd, void *ep_handle,
++00647                           void *req_handle, int proc_buf_num)
++00648 {
++00649         int i, packet_count;
++00650         struct usb_gadget_iso_packet_descriptor *iso_packet = 0;
++00651         struct usb_iso_request *iso_req = req_handle;
++00652 
++00653         if (proc_buf_num) {
++00654                 iso_packet = iso_req->iso_packet_desc1;
++00655         } else {
++00656                 iso_packet = iso_req->iso_packet_desc0;
++00657         }
++00658         packet_count =
++00659             dwc_otg_pcd_get_iso_packet_count(pcd, ep_handle, req_handle);
++00660         for (i = 0; i < packet_count; ++i) {
++00661                 int status;
++00662                 int actual;
++00663                 int offset;
++00664                 dwc_otg_pcd_get_iso_packet_params(pcd, ep_handle, req_handle,
++00665                                                   i, &status, &actual, &offset);
++00666                 switch (status) {
++00667                 case -DWC_E_NO_DATA:
++00668                         status = -ENODATA;
++00669                         break;
++00670                 default:
++00671                         if (status) {
++00672                                 DWC_PRINTF("unknown status in isoc packet\n");
++00673                         }
++00674 
++00675                 }
++00676                 iso_packet[i].status = status;
++00677                 iso_packet[i].offset = offset;
++00678                 iso_packet[i].actual_length = actual;
++00679         }
++00680 
++00681         iso_req->status = 0;
++00682         iso_req->process_buffer(ep_handle, iso_req);
++00683 
++00684         return 0;
++00685 }
++00686 #endif                          /* DWC_EN_ISOC */
++00687 
++00688 static int _complete(dwc_otg_pcd_t * pcd, void *ep_handle,
++00689                      void *req_handle, int32_t status, uint32_t actual)
++00690 {
++00691         struct usb_request *req = (struct usb_request *)req_handle;
++00692 
++00693         if (req && req->complete) {
++00694                 switch (status) {
++00695                 case -DWC_E_SHUTDOWN:
++00696                         req->status = -ESHUTDOWN;
++00697                         break;
++00698                 case -DWC_E_RESTART:
++00699                         req->status = -ECONNRESET;
++00700                         break;
++00701                 case -DWC_E_INVALID:
++00702                         req->status = -EINVAL;
++00703                         break;
++00704                 case -DWC_E_TIMEOUT:
++00705                         req->status = -ETIMEDOUT;
++00706                         break;
++00707                 default:
++00708                         req->status = status;
++00709 
++00710                 }
++00711                 req->actual = actual;
++00712                 req->complete(ep_handle, req);
++00713         }
++00714 
++00715         return 0;
++00716 }
++00717 
++00718 static int _connect(dwc_otg_pcd_t * pcd, int speed)
++00719 {
++00720         gadget_wrapper->gadget.speed = speed;
++00721         return 0;
++00722 }
++00723 
++00724 static int _disconnect(dwc_otg_pcd_t * pcd)
++00725 {
++00726         if (gadget_wrapper->driver && gadget_wrapper->driver->disconnect) {
++00727                 gadget_wrapper->driver->disconnect(&gadget_wrapper->gadget);
++00728         }
++00729         return 0;
++00730 }
++00731 
++00732 static int _resume(dwc_otg_pcd_t * pcd)
++00733 {
++00734         if (gadget_wrapper->driver && gadget_wrapper->driver->resume) {
++00735                 gadget_wrapper->driver->resume(&gadget_wrapper->gadget);
++00736         }
++00737 
++00738         return 0;
++00739 }
++00740 
++00741 static int _suspend(dwc_otg_pcd_t * pcd)
++00742 {
++00743         if (gadget_wrapper->driver && gadget_wrapper->driver->suspend) {
++00744                 gadget_wrapper->driver->suspend(&gadget_wrapper->gadget);
++00745         }
++00746         return 0;
++00747 }
++00748 
++00752 static int _hnp_changed(dwc_otg_pcd_t * pcd)
++00753 {
++00754 
++00755         if (!gadget_wrapper->gadget.is_otg)
++00756                 return 0;
++00757 
++00758         gadget_wrapper->gadget.b_hnp_enable = get_b_hnp_enable(pcd);
++00759         gadget_wrapper->gadget.a_hnp_support = get_a_hnp_support(pcd);
++00760         gadget_wrapper->gadget.a_alt_hnp_support = get_a_alt_hnp_support(pcd);
++00761         return 0;
++00762 }
++00763 
++00764 static int _reset(dwc_otg_pcd_t * pcd)
++00765 {
++00766         return 0;
++00767 }
++00768 
++00769 #ifdef DWC_UTE_CFI
++00770 static int _cfi_setup(dwc_otg_pcd_t * pcd, void *cfi_req)
++00771 {
++00772         int retval = -DWC_E_INVALID;
++00773         if (gadget_wrapper->driver->cfi_feature_setup) {
++00774                 retval =
++00775                     gadget_wrapper->driver->cfi_feature_setup(&gadget_wrapper->
++00776                                                               gadget,
++00777                                                               (struct
++00778                                                                cfi_usb_ctrlrequest
++00779                                                                *)cfi_req);
++00780         }
++00781 
++00782         return retval;
++00783 }
++00784 #endif
++00785 
++00786 static const struct dwc_otg_pcd_function_ops fops = {
++00787         .complete = _complete,
++00788 #ifdef DWC_EN_ISOC
++00789         .isoc_complete = _isoc_complete,
++00790 #endif
++00791         .setup = _setup,
++00792         .disconnect = _disconnect,
++00793         .connect = _connect,
++00794         .resume = _resume,
++00795         .suspend = _suspend,
++00796         .hnp_changed = _hnp_changed,
++00797         .reset = _reset,
++00798 #ifdef DWC_UTE_CFI
++00799         .cfi_setup = _cfi_setup,
++00800 #endif
++00801 };
++00802 
++00806 static irqreturn_t dwc_otg_pcd_irq(int irq, void *dev)
++00807 {
++00808         dwc_otg_pcd_t *pcd = dev;
++00809         int32_t retval = IRQ_NONE;
++00810 
++00811         retval = dwc_otg_pcd_handle_intr(pcd);
++00812         if (retval != 0) {
++00813                 S3C2410X_CLEAR_EINTPEND();
++00814         }
++00815         return IRQ_RETVAL(retval);
++00816 }
++00817 
++00824 void gadget_add_eps(struct gadget_wrapper *d)
++00825 {
++00826         static const char *names[] = {
++00827 
++00828                 "ep0",
++00829                 "ep1in",
++00830                 "ep2in",
++00831                 "ep3in",
++00832                 "ep4in",
++00833                 "ep5in",
++00834                 "ep6in",
++00835                 "ep7in",
++00836                 "ep8in",
++00837                 "ep9in",
++00838                 "ep10in",
++00839                 "ep11in",
++00840                 "ep12in",
++00841                 "ep13in",
++00842                 "ep14in",
++00843                 "ep15in",
++00844                 "ep1out",
++00845                 "ep2out",
++00846                 "ep3out",
++00847                 "ep4out",
++00848                 "ep5out",
++00849                 "ep6out",
++00850                 "ep7out",
++00851                 "ep8out",
++00852                 "ep9out",
++00853                 "ep10out",
++00854                 "ep11out",
++00855                 "ep12out",
++00856                 "ep13out",
++00857                 "ep14out",
++00858                 "ep15out"
++00859         };
++00860 
++00861         int i;
++00862         struct usb_ep *ep;
++00863 
++00864         DWC_DEBUGPL(DBG_PCDV, "%s\n", __func__);
++00865 
++00866         INIT_LIST_HEAD(&d->gadget.ep_list);
++00867         d->gadget.ep0 = &d->ep0;
++00868         d->gadget.speed = USB_SPEED_UNKNOWN;
++00869 
++00870         INIT_LIST_HEAD(&d->gadget.ep0->ep_list);
++00871 
++00875         ep = &d->ep0;
++00876 
++00877         /* Init the usb_ep structure. */
++00878         ep->name = names[0];
++00879         ep->ops = (struct usb_ep_ops *)&dwc_otg_pcd_ep_ops;
++00880 
++00885         ep->maxpacket = MAX_PACKET_SIZE;
++00886         dwc_otg_pcd_ep_enable(d->pcd, NULL, ep);
++00887 
++00888         list_add_tail(&ep->ep_list, &d->gadget.ep_list);
++00889 
++00894         for (i = 0; i < 15; i++) {
++00895                 ep = &d->in_ep[i];
++00896 
++00897                 /* Init the usb_ep structure. */
++00898                 ep->name = names[i + 1];
++00899                 ep->ops = (struct usb_ep_ops *)&dwc_otg_pcd_ep_ops;
++00900 
++00905                 ep->maxpacket = MAX_PACKET_SIZE;
++00906                 list_add_tail(&ep->ep_list, &d->gadget.ep_list);
++00907         }
++00908 
++00909         for (i = 0; i < 15; i++) {
++00910                 ep = &d->out_ep[i];
++00911 
++00912                 /* Init the usb_ep structure. */
++00913                 ep->name = names[15 + i + 1];
++00914                 ep->ops = (struct usb_ep_ops *)&dwc_otg_pcd_ep_ops;
++00915 
++00920                 ep->maxpacket = MAX_PACKET_SIZE;
++00921 
++00922                 list_add_tail(&ep->ep_list, &d->gadget.ep_list);
++00923         }
++00924 
++00925         /* remove ep0 from the list.  There is a ep0 pointer. */
++00926         list_del_init(&d->ep0.ep_list);
++00927 
++00928         d->ep0.maxpacket = MAX_EP0_SIZE;
++00929 }
++00930 
++00937 static void dwc_otg_pcd_gadget_release(struct device *dev)
++00938 {
++00939         DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, dev);
++00940 }
++00941 
++00942 static struct gadget_wrapper *alloc_wrapper(
++00943 #ifdef LM_INTERFACE
++00944         struct lm_device *_dev
++00945 #elif  PCI_INTERFACE
++00946         struct pci_dev *_dev
++00947 #endif
++00948         )
++00949 {
++00950         static char pcd_name[] = "dwc_otg_pcd";
++00951 #ifdef LM_INTERFACE
++00952         dwc_otg_device_t *otg_dev = lm_get_drvdata(_dev);
++00953 #elif PCI_INTERFACE
++00954         dwc_otg_device_t *otg_dev = pci_get_drvdata(_dev);
++00955 #endif
++00956 
++00957         struct gadget_wrapper *d;
++00958         int retval;
++00959 
++00960         d = dwc_alloc(sizeof(*d));
++00961         if (d == NULL) {
++00962                 return NULL;
++00963         }
++00964 
++00965         memset(d, 0, sizeof(*d));
++00966 
++00967         d->gadget.name = pcd_name;
++00968         d->pcd = otg_dev->pcd;
++00969         strcpy(d->gadget.dev.bus_id, "gadget");
++00970 
++00971         d->gadget.dev.parent = &_dev->dev;
++00972         d->gadget.dev.release = dwc_otg_pcd_gadget_release;
++00973         d->gadget.ops = &dwc_otg_pcd_ops;
++00974         d->gadget.is_dualspeed = dwc_otg_pcd_is_dualspeed(otg_dev->pcd);
++00975         d->gadget.is_otg = dwc_otg_pcd_is_otg(otg_dev->pcd);
++00976 
++00977         d->driver = 0;
++00978         /* Register the gadget device */
++00979         retval = device_register(&d->gadget.dev);
++00980         if (retval != 0) {
++00981                 DWC_ERROR("device_register failed\n");
++00982                 dwc_free(d);
++00983                 return NULL;
++00984         }
++00985 
++00986         return d;
++00987 }
++00988 
++00989 static void free_wrapper(struct gadget_wrapper *d)
++00990 {
++00991         if (d->driver) {
++00992                 /* should have been done already by driver model core */
++00993                 DWC_WARN("driver '%s' is still registered\n",
++00994                          d->driver->driver.name);
++00995                 usb_gadget_unregister_driver(d->driver);
++00996         }
++00997 
++00998         device_unregister(&d->gadget.dev);
++00999         dwc_free(d);
++01000 }
++01001 
++01006 int pcd_init(
++01007 #ifdef LM_INTERFACE
++01008         struct lm_device *_dev
++01009 #elif  PCI_INTERFACE
++01010         struct pci_dev *_dev
++01011 #endif
++01012         )
++01013 
++01014 {
++01015 #ifdef LM_INTERFACE
++01016         dwc_otg_device_t *otg_dev = lm_get_drvdata(_dev);
++01017 #elif  PCI_INTERFACE
++01018         dwc_otg_device_t *otg_dev = pci_get_drvdata(_dev);
++01019 #endif
++01020 
++01021         int retval = 0;
++01022 
++01023         DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, _dev);
++01024 
++01025         otg_dev->pcd = dwc_otg_pcd_init(otg_dev->core_if);
++01026 
++01027         if (!otg_dev->pcd) {
++01028                 DWC_ERROR("dwc_otg_pcd_init failed\n");
++01029                 return -ENOMEM;
++01030         }
++01031 
++01032         gadget_wrapper = alloc_wrapper(_dev);
++01033 
++01034         /*
++01035          * Initialize EP structures
++01036          */
++01037         gadget_add_eps(gadget_wrapper);
++01038 
++01039         /*
++01040          * Setup interupt handler
++01041          */
++01042         DWC_DEBUGPL(DBG_ANY, "registering handler for irq%d\n", _dev->irq);
++01043         retval = request_irq(_dev->irq, dwc_otg_pcd_irq,
++01044                              SA_SHIRQ, gadget_wrapper->gadget.name,
++01045                              otg_dev->pcd);
++01046         if (retval != 0) {
++01047                 DWC_ERROR("request of irq%d failed\n", _dev->irq);
++01048                 free_wrapper(gadget_wrapper);
++01049                 return -EBUSY;
++01050         }
++01051 
++01052         dwc_otg_pcd_start(gadget_wrapper->pcd, &fops);
++01053 
++01054         return retval;
++01055 }
++01056 
++01060 void pcd_remove(
++01061 #ifdef LM_INTERFACE
++01062         struct lm_device *_dev
++01063 #elif  PCI_INTERFACE
++01064         struct pci_dev *_dev
++01065 #endif
++01066         )
++01067 {
++01068 #ifdef LM_INTERFACE
++01069         dwc_otg_device_t *otg_dev = lm_get_drvdata(_dev);
++01070 #elif  PCI_INTERFACE
++01071         dwc_otg_device_t *otg_dev = pci_get_drvdata(_dev);
++01072 #endif
++01073         dwc_otg_pcd_t *pcd = otg_dev->pcd;
++01074 
++01075         DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, _dev);
++01076 
++01077         /*
++01078          * Free the IRQ
++01079          */
++01080         free_irq(_dev->irq, pcd);
++01081         dwc_otg_pcd_remove(otg_dev->pcd);
++01082         free_wrapper(gadget_wrapper);
++01083         otg_dev->pcd = 0;
++01084 }
++01085 
++01096 int usb_gadget_register_driver(struct usb_gadget_driver *driver)
++01097 {
++01098         int retval;
++01099 
++01100         DWC_DEBUGPL(DBG_PCD, "registering gadget driver '%s'\n",
++01101                     driver->driver.name);
++01102 
++01103         if (!driver || driver->speed == USB_SPEED_UNKNOWN ||
++01104             !driver->bind ||
++01105             !driver->unbind || !driver->disconnect || !driver->setup) {
++01106                 DWC_DEBUGPL(DBG_PCDV, "EINVAL\n");
++01107                 return -EINVAL;
++01108         }
++01109         if (gadget_wrapper == 0) {
++01110                 DWC_DEBUGPL(DBG_PCDV, "ENODEV\n");
++01111                 return -ENODEV;
++01112         }
++01113         if (gadget_wrapper->driver != 0) {
++01114                 DWC_DEBUGPL(DBG_PCDV, "EBUSY (%p)\n", gadget_wrapper->driver);
++01115                 return -EBUSY;
++01116         }
++01117 
++01118         /* hook up the driver */
++01119         gadget_wrapper->driver = driver;
++01120         gadget_wrapper->gadget.dev.driver = &driver->driver;
++01121 
++01122         DWC_DEBUGPL(DBG_PCD, "bind to driver %s\n", driver->driver.name);
++01123         retval = driver->bind(&gadget_wrapper->gadget);
++01124         if (retval) {
++01125                 DWC_ERROR("bind to driver %s --> error %d\n",
++01126                           driver->driver.name, retval);
++01127                 gadget_wrapper->driver = 0;
++01128                 gadget_wrapper->gadget.dev.driver = 0;
++01129                 return retval;
++01130         }
++01131         DWC_DEBUGPL(DBG_ANY, "registered gadget driver '%s'\n",
++01132                     driver->driver.name);
++01133         return 0;
++01134 }
++01135 
++01136 EXPORT_SYMBOL(usb_gadget_register_driver);
++01137 
++01143 int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
++01144 {
++01145         //DWC_DEBUGPL(DBG_PCDV,"%s(%p)\n", __func__, _driver);
++01146 
++01147         if (gadget_wrapper == 0) {
++01148                 DWC_DEBUGPL(DBG_ANY, "%s Return(%d): s_pcd==0\n", __func__,
++01149                             -ENODEV);
++01150                 return -ENODEV;
++01151         }
++01152         if (driver == 0 || driver != gadget_wrapper->driver) {
++01153                 DWC_DEBUGPL(DBG_ANY, "%s Return(%d): driver?\n", __func__,
++01154                             -EINVAL);
++01155                 return -EINVAL;
++01156         }
++01157 
++01158         driver->unbind(&gadget_wrapper->gadget);
++01159         gadget_wrapper->driver = 0;
++01160 
++01161         DWC_DEBUGPL(DBG_ANY, "unregistered driver '%s'\n", driver->driver.name);
++01162         return 0;
++01163 }
++01164 
++01165 EXPORT_SYMBOL(usb_gadget_unregister_driver);
++01166 
++01167 #endif                          /* DWC_HOST_ONLY */
++
Generated on Tue May 5 02:22:48 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__pcd__linux_8c.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__pcd__linux_8c.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,796 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_pcd_linux.c File Reference ++ ++ ++ ++ ++
++
++
++
++

dwc_otg_pcd_linux.c File Reference

This file implements the Peripheral Controller Driver. More... ++

++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/moduleparam.h>
++#include <linux/init.h>
++#include <linux/device.h>
++#include <linux/errno.h>
++#include <linux/list.h>
++#include <linux/interrupt.h>
++#include <linux/string.h>
++#include <linux/dma-mapping.h>
++#include <linux/version.h>
++#include <asm/io.h>
++#include <linux/usb_ch9.h>
++#include <linux/usb_gadget.h>
++#include "dwc_otg_pcd_if.h"
++#include "dwc_otg_driver.h"
++#include "dwc_otg_dbg.h"
++ ++

++Go to the source code of this file. ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++

Data Structures

struct  gadget_wrapper

Functions

++void dump_msg (const u8 *buf, unsigned int length)
static int ep_enable (struct usb_ep *usb_ep, const struct usb_endpoint_descriptor *ep_desc)
 This function is called by the Gadget Driver for each EP to be configured for the current configuration (SET_CONFIGURATION).
static int ep_disable (struct usb_ep *usb_ep)
 This function is called when an EP is disabled due to disconnect or change in configuration.
static struct usb_request * dwc_otg_pcd_alloc_request (struct usb_ep *ep, gfp_t gfp_flags)
 This function allocates a request object to use with the specified endpoint.
static void dwc_otg_pcd_free_request (struct usb_ep *ep, struct usb_request *req)
 This function frees a request object.
static void * dwc_otg_pcd_alloc_buffer (struct usb_ep *usb_ep, unsigned bytes, dma_addr_t *dma, gfp_t gfp_flags)
 This function allocates an I/O buffer to be used for a transfer to/from the specified endpoint.
static void dwc_otg_pcd_free_buffer (struct usb_ep *usb_ep, void *buf, dma_addr_t dma, unsigned bytes)
 This function frees an I/O buffer that was allocated by alloc_buffer.
static int ep_queue (struct usb_ep *usb_ep, struct usb_request *usb_req, gfp_t gfp_flags)
 This function is used to submit an I/O Request to an EP.
++static int ep_dequeue (struct usb_ep *usb_ep, struct usb_request *usb_req)
 This function cancels an I/O request from an EP.
static int ep_halt (struct usb_ep *usb_ep, int value)
 usb_ep_set_halt stalls an endpoint.
static int iso_ep_start (struct usb_ep *usb_ep, struct usb_iso_request *req, gfp_t gfp_flags)
 This function is used to submit an ISOC Transfer Request to an EP.
++static int iso_ep_stop (struct usb_ep *usb_ep, struct usb_iso_request *req)
 This function stops ISO EP Periodic Data Transfer.
++static struct usb_iso_request * alloc_iso_request (struct usb_ep *ep, int packets, gfp_t gfp_flags)
++static void free_iso_request (struct usb_ep *ep, struct usb_iso_request *req)
++static int get_frame_number (struct usb_gadget *gadget)
 Gets the USB Frame number of the last SOF.
static int wakeup (struct usb_gadget *gadget)
 Initiates Session Request Protocol (SRP) to wakeup the host if no session is in progress.
++static int _setup (dwc_otg_pcd_t *pcd, uint8_t *bytes)
++static int _isoc_complete (dwc_otg_pcd_t *pcd, void *ep_handle, void *req_handle, int proc_buf_num)
++static int _complete (dwc_otg_pcd_t *pcd, void *ep_handle, void *req_handle, int32_t status, uint32_t actual)
++static int _connect (dwc_otg_pcd_t *pcd, int speed)
++static int _disconnect (dwc_otg_pcd_t *pcd)
++static int _resume (dwc_otg_pcd_t *pcd)
++static int _suspend (dwc_otg_pcd_t *pcd)
++static int _hnp_changed (dwc_otg_pcd_t *pcd)
 This function updates the otg values in the gadget structure.
++static int _reset (dwc_otg_pcd_t *pcd)
++static irqreturn_t dwc_otg_pcd_irq (int irq, void *dev)
 This function is the top level PCD interrupt handler.
void gadget_add_eps (struct gadget_wrapper *d)
 This function initialized the usb_ep structures to there default state.
static void dwc_otg_pcd_gadget_release (struct device *dev)
 This function releases the Gadget device.
++static struct gadget_wrapper * alloc_wrapper ()
++static void free_wrapper (struct gadget_wrapper *d)
++int pcd_init ()
 This function initialized the PCD portion of the driver.
++void pcd_remove ()
 Cleanup the PCD.
int usb_gadget_register_driver (struct usb_gadget_driver *driver)
 This function registers a gadget driver with the PCD.
++ EXPORT_SYMBOL (usb_gadget_register_driver)
int usb_gadget_unregister_driver (struct usb_gadget_driver *driver)
 This function unregisters a gadget driver.
++ EXPORT_SYMBOL (usb_gadget_unregister_driver)

Variables

static struct usb_isoc_ep_ops dwc_otg_pcd_ep_ops
static struct usb_gadget_ops dwc_otg_pcd_ops
static struct dwc_otg_pcd_function_ops fops
++

Detailed Description

++This file implements the Peripheral Controller Driver. ++

++The Peripheral Controller Driver (PCD) is responsible for translating requests from the Function Driver into the appropriate actions on the DWC_otg controller. It isolates the Function Driver from the specifics of the controller by providing an API to the Function Driver.

++The Peripheral Controller Driver for Linux will implement the Gadget API, so that the existing Gadget drivers can be used. (Gadget Driver is the Linux terminology for a Function Driver.)

++The Linux Gadget API is defined in the header file <linux/usb_gadget.h>. The USB EP operations API is defined in the structure usb_ep_ops and the USB Controller API is defined in the structure usb_gadget_ops. ++

++Definition in file dwc_otg_pcd_linux.c.

Function Documentation

++ ++
++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
static int ep_enable (struct usb_ep *  usb_ep,
const struct usb_endpoint_descriptor *  ep_desc 
) [static]
++
++
++ ++

++This function is called by the Gadget Driver for each EP to be configured for the current configuration (SET_CONFIGURATION). ++

++This function initializes the dwc_otg_ep_t data structure, and then calls dwc_otg_ep_activate. ++

++Definition at line 121 of file dwc_otg_pcd_linux.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
static int ep_disable (struct usb_ep *  usb_ep  )  [static]
++
++
++ ++

++This function is called when an EP is disabled due to disconnect or change in configuration. ++

++Any pending requests will terminate with a status of -ESHUTDOWN.

++This function modifies the dwc_otg_ep_t data structure for this EP, and then calls dwc_otg_ep_deactivate. ++

++Definition at line 170 of file dwc_otg_pcd_linux.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
static struct usb_request* dwc_otg_pcd_alloc_request (struct usb_ep *  ep,
gfp_t  gfp_flags 
) [static]
++
++
++ ++

++This function allocates a request object to use with the specified endpoint. ++

++

Parameters:
++ ++ ++ ++
ep The endpoint to be used with with the request
gfp_flags the GFP_* flags to use.
++
++ ++

++Definition at line 196 of file dwc_otg_pcd_linux.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
static void dwc_otg_pcd_free_request (struct usb_ep *  ep,
struct usb_request *  req 
) [static]
++
++
++ ++

++This function frees a request object. ++

++

Parameters:
++ ++ ++ ++
ep The endpoint associated with the request
req The request being freed
++
++ ++

++Definition at line 223 of file dwc_otg_pcd_linux.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
static void* dwc_otg_pcd_alloc_buffer (struct usb_ep *  usb_ep,
unsigned  bytes,
dma_addr_t *  dma,
gfp_t  gfp_flags 
) [static]
++
++
++ ++

++This function allocates an I/O buffer to be used for a transfer to/from the specified endpoint. ++

++

Parameters:
++ ++ ++ ++ ++ ++
usb_ep The endpoint to be used with with the request
bytes The desired number of bytes for the buffer
dma Pointer to the buffer's DMA address; must be valid
gfp_flags the GFP_* flags to use.
++
++
Returns:
address of a new buffer or null is buffer could not be allocated.
++ ++

++Definition at line 246 of file dwc_otg_pcd_linux.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
static void dwc_otg_pcd_free_buffer (struct usb_ep *  usb_ep,
void *  buf,
dma_addr_t  dma,
unsigned  bytes 
) [static]
++
++
++ ++

++This function frees an I/O buffer that was allocated by alloc_buffer. ++

++

Parameters:
++ ++ ++ ++ ++ ++
usb_ep the endpoint associated with the buffer
buf address of the buffer
dma The buffer's DMA address
bytes The number of bytes of the buffer
++
++ ++

++Definition at line 282 of file dwc_otg_pcd_linux.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
static int ep_queue (struct usb_ep *  usb_ep,
struct usb_request *  usb_req,
gfp_t  gfp_flags 
) [static]
++
++
++ ++

++This function is used to submit an I/O Request to an EP. ++

++

    ++
  • When the request completes the request's completion callback is called to return the request to the driver.
  • An EP, except control EPs, may have multiple requests pending.
  • Once submitted the request cannot be examined or modified.
  • Each request is turned into one or more packets.
  • A BULK EP can queue any amount of data; the transfer is packetized.
  • Zero length Packets are specified with the request 'zero' flag.
++ ++

++Definition at line 308 of file dwc_otg_pcd_linux.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
static int ep_halt (struct usb_ep *  usb_ep,
int  value 
) [static]
++
++
++ ++

++usb_ep_set_halt stalls an endpoint. ++

++usb_ep_clear_halt clears an endpoint halt and resets its data toggle.

++Both of these functions are implemented with the same underlying function. The behavior depends on the value argument.

++

Parameters:
++ ++ ++ ++
[in] usb_ep the Endpoint to halt or clear halt.
[in] value 
    ++
  • 0 means clear_halt.
  • 1 means set_halt,
  • 2 means clear stall lock flag.
  • 3 means set stall lock flag.
++
++
++ ++

++Definition at line 391 of file dwc_otg_pcd_linux.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
static int iso_ep_start (struct usb_ep *  usb_ep,
struct usb_iso_request *  req,
gfp_t  gfp_flags 
) [static]
++
++
++ ++

++This function is used to submit an ISOC Transfer Request to an EP. ++

++

    ++
  • Every time a sync period completes the request's completion callback is called to provide data to the gadget driver.
  • Once submitted the request cannot be modified.
  • Each request is turned into periodic data packets untill ISO Transfer is stopped..
++ ++

++Definition at line 422 of file dwc_otg_pcd_linux.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
static int wakeup (struct usb_gadget *  gadget  )  [static]
++
++
++ ++

++Initiates Session Request Protocol (SRP) to wakeup the host if no session is in progress. ++

++If a session is already in progress, but the device is suspended, remote wakeup signaling is started. ++

++Definition at line 603 of file dwc_otg_pcd_linux.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void gadget_add_eps (struct gadget_wrapper *  d  ) 
++
++
++ ++

++This function initialized the usb_ep structures to there default state. ++

++

Parameters:
++ ++ ++
d Pointer on gadget_wrapper.
++
++ ++

++Initialize the EP0 structure.

++

Todo:
NGS: What should the max packet size be set to here? Before EP type is set?
++

++Initialize the EP structures.

++

Todo:
NGS: What should the max packet size be set to here? Before EP type is set?
++

++

Todo:
NGS: What should the max packet size be set to here? Before EP type is set?
++ ++

++Definition at line 824 of file dwc_otg_pcd_linux.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
static void dwc_otg_pcd_gadget_release (struct device *  dev  )  [static]
++
++
++ ++

++This function releases the Gadget device. ++

++required by device_unregister().

++

Todo:
Should this do something? Should it free the PCD?
++ ++

++Definition at line 937 of file dwc_otg_pcd_linux.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int usb_gadget_register_driver (struct usb_gadget_driver *  driver  ) 
++
++
++ ++

++This function registers a gadget driver with the PCD. ++

++When a driver is successfully registered, it will receive control requests including set_configuration(), which enables non-control requests. then usb traffic follows until a disconnect is reported. then a host may connect again, or the driver might get unbound.

++

Parameters:
++ ++ ++
driver The driver being registered
++
++ ++

++Definition at line 1096 of file dwc_otg_pcd_linux.c. ++

++

++ ++

++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int usb_gadget_unregister_driver (struct usb_gadget_driver *  driver  ) 
++
++
++ ++

++This function unregisters a gadget driver. ++

++

Parameters:
++ ++ ++
driver The driver being unregistered
++
++ ++

++Definition at line 1143 of file dwc_otg_pcd_linux.c. ++

++

++

Variable Documentation

++ ++
++
++ ++ ++ ++ ++
struct usb_isoc_ep_ops dwc_otg_pcd_ep_ops [static]
++
++
++ ++

++Initial value:

 {
++        .ep_ops = {
++                   .enable = ep_enable,
++                   .disable = ep_disable,
++
++                   .alloc_request = dwc_otg_pcd_alloc_request,
++                   .free_request = dwc_otg_pcd_free_request,
++
++                   .alloc_buffer = dwc_otg_pcd_alloc_buffer,
++                   .free_buffer = dwc_otg_pcd_free_buffer,
++
++                   .queue = ep_queue,
++                   .dequeue = ep_dequeue,
++
++                   .set_halt = ep_halt,
++                   .fifo_status = 0,
++                   .fifo_flush = 0,
++                   },
++        .iso_ep_start = iso_ep_start,
++        .iso_ep_stop = iso_ep_stop,
++        .alloc_iso_request = alloc_iso_request,
++        .free_iso_request = free_iso_request,
++}
++
++

++Definition at line 507 of file dwc_otg_pcd_linux.c. ++

++

++ ++

++
++ ++ ++ ++ ++
struct usb_gadget_ops dwc_otg_pcd_ops [static]
++
++
++ ++

++Initial value:

 {
++        .get_frame = get_frame_number,
++        .wakeup = wakeup,
++
++
++
++        
++}
++
++

++Definition at line 618 of file dwc_otg_pcd_linux.c. ++

++

++ ++

++
++ ++ ++ ++ ++
struct dwc_otg_pcd_function_ops fops [static]
++
++
++ ++

++Initial value:

 {
++        .complete = _complete,
++
++        .isoc_complete = _isoc_complete,
++
++        .setup = _setup,
++        .disconnect = _disconnect,
++        .connect = _connect,
++        .resume = _resume,
++        .suspend = _suspend,
++        .hnp_changed = _hnp_changed,
++        .reset = _reset,
++
++
++
++}
++
++

++Definition at line 786 of file dwc_otg_pcd_linux.c. ++

++

++

Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__regs_8h-source.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__regs_8h-source.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,1260 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_regs.h Source File ++ ++ ++ ++ ++
++
++
++
++

dwc_otg_regs.h

Go to the documentation of this file.
00001 /* ==========================================================================
++00002  * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_regs.h $
++00003  * $Revision: #76 $
++00004  * $Date: 2009/04/02 $
++00005  * $Change: 1224216 $
++00006  *
++00007  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
++00008  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
++00009  * otherwise expressly agreed to in writing between Synopsys and you.
++00010  * 
++00011  * The Software IS NOT an item of Licensed Software or Licensed Product under
++00012  * any End User Software License Agreement or Agreement for Licensed Product
++00013  * with Synopsys or any supplement thereto. You are permitted to use and
++00014  * redistribute this Software in source and binary forms, with or without
++00015  * modification, provided that redistributions of source code must retain this
++00016  * notice. You may not view, use, disclose, copy or distribute this file or
++00017  * any information contained herein except pursuant to this license grant from
++00018  * Synopsys. If you do not agree with this notice, including the disclaimer
++00019  * below, then you are not authorized to use the Software.
++00020  * 
++00021  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
++00022  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++00023  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++00024  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
++00025  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++00026  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
++00027  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
++00028  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
++00029  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
++00030  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
++00031  * DAMAGE.
++00032  * ========================================================================== */
++00033 
++00034 #ifndef __DWC_OTG_REGS_H__
++00035 #define __DWC_OTG_REGS_H__
++00036 
++00037 #include "dwc_otg_core_if.h"
++00038 
++00066 /****************************************************************************/
++00071 typedef struct dwc_otg_core_global_regs {
++00073         volatile uint32_t gotgctl;
++00075         volatile uint32_t gotgint;
++00077         volatile uint32_t gahbcfg;
++00078 
++00079 #define DWC_GLBINTRMASK         0x0001
++00080 #define DWC_DMAENABLE           0x0020
++00081 #define DWC_NPTXEMPTYLVL_EMPTY  0x0080
++00082 #define DWC_NPTXEMPTYLVL_HALFEMPTY      0x0000
++00083 #define DWC_PTXEMPTYLVL_EMPTY   0x0100
++00084 #define DWC_PTXEMPTYLVL_HALFEMPTY       0x0000
++00085 
++00087         volatile uint32_t gusbcfg;
++00089         volatile uint32_t grstctl;
++00091         volatile uint32_t gintsts;
++00093         volatile uint32_t gintmsk;
++00095         volatile uint32_t grxstsr;
++00097         volatile uint32_t grxstsp;
++00099         volatile uint32_t grxfsiz;
++00101         volatile uint32_t gnptxfsiz;
++00104         volatile uint32_t gnptxsts;
++00106         volatile uint32_t gi2cctl;
++00108         volatile uint32_t gpvndctl;
++00110         volatile uint32_t ggpio;
++00112         volatile uint32_t guid;
++00114         volatile uint32_t gsnpsid;
++00116         volatile uint32_t ghwcfg1;
++00118         volatile uint32_t ghwcfg2;
++00119 #define DWC_SLAVE_ONLY_ARCH 0
++00120 #define DWC_EXT_DMA_ARCH 1
++00121 #define DWC_INT_DMA_ARCH 2
++00122 
++00123 #define DWC_MODE_HNP_SRP_CAPABLE        0
++00124 #define DWC_MODE_SRP_ONLY_CAPABLE       1
++00125 #define DWC_MODE_NO_HNP_SRP_CAPABLE             2
++00126 #define DWC_MODE_SRP_CAPABLE_DEVICE             3
++00127 #define DWC_MODE_NO_SRP_CAPABLE_DEVICE  4
++00128 #define DWC_MODE_SRP_CAPABLE_HOST       5
++00129 #define DWC_MODE_NO_SRP_CAPABLE_HOST    6
++00130 
++00132         volatile uint32_t ghwcfg3;
++00134         volatile uint32_t ghwcfg4;
++00136         volatile uint32_t glpmcfg;
++00138         volatile uint32_t reserved[42];
++00140         volatile uint32_t hptxfsiz;
++00144         volatile uint32_t dptxfsiz_dieptxf[15];
++00145 } dwc_otg_core_global_regs_t;
++00146 
++00152 typedef union gotgctl_data {
++00154         uint32_t d32;
++00156         struct {
++00157                 unsigned sesreqscs:1;
++00158                 unsigned sesreq:1;
++00159                 unsigned reserved2_7:6;
++00160                 unsigned hstnegscs:1;
++00161                 unsigned hnpreq:1;
++00162                 unsigned hstsethnpen:1;
++00163                 unsigned devhnpen:1;
++00164                 unsigned reserved12_15:4;
++00165                 unsigned conidsts:1;
++00166                 unsigned reserved17:1;
++00167                 unsigned asesvld:1;
++00168                 unsigned bsesvld:1;
++00169                 unsigned currmod:1;
++00170                 unsigned reserved21_31:11;
++00171         } b;
++00172 } gotgctl_data_t;
++00173 
++00179 typedef union gotgint_data {
++00181         uint32_t d32;
++00183         struct {
++00185                 unsigned reserved0_1:2;
++00186 
++00188                 unsigned sesenddet:1;
++00189 
++00190                 unsigned reserved3_7:5;
++00191 
++00193                 unsigned sesreqsucstschng:1;
++00195                 unsigned hstnegsucstschng:1;
++00196 
++00197                 unsigned reserver10_16:7;
++00198 
++00200                 unsigned hstnegdet:1;
++00202                 unsigned adevtoutchng:1;
++00204                 unsigned debdone:1;
++00205 
++00206                 unsigned reserved31_20:12;
++00207 
++00208         } b;
++00209 } gotgint_data_t;
++00210 
++00216 typedef union gahbcfg_data {
++00218         uint32_t d32;
++00220         struct {
++00221                 unsigned glblintrmsk:1;
++00222 #define DWC_GAHBCFG_GLBINT_ENABLE               1
++00223 
++00224                 unsigned hburstlen:4;
++00225 #define DWC_GAHBCFG_INT_DMA_BURST_SINGLE        0
++00226 #define DWC_GAHBCFG_INT_DMA_BURST_INCR          1
++00227 #define DWC_GAHBCFG_INT_DMA_BURST_INCR4         3
++00228 #define DWC_GAHBCFG_INT_DMA_BURST_INCR8         5
++00229 #define DWC_GAHBCFG_INT_DMA_BURST_INCR16        7
++00230 
++00231                 unsigned dmaenable:1;
++00232 #define DWC_GAHBCFG_DMAENABLE                   1
++00233                 unsigned reserved:1;
++00234                 unsigned nptxfemplvl_txfemplvl:1;
++00235                 unsigned ptxfemplvl:1;
++00236 #define DWC_GAHBCFG_TXFEMPTYLVL_EMPTY           1
++00237 #define DWC_GAHBCFG_TXFEMPTYLVL_HALFEMPTY       0
++00238                 unsigned reserved9_31:23;
++00239         } b;
++00240 } gahbcfg_data_t;
++00241 
++00247 typedef union gusbcfg_data {
++00249         uint32_t d32;
++00251         struct {
++00252                 unsigned toutcal:3;
++00253                 unsigned phyif:1;
++00254                 unsigned ulpi_utmi_sel:1;
++00255                 unsigned fsintf:1;
++00256                 unsigned physel:1;
++00257                 unsigned ddrsel:1;
++00258                 unsigned srpcap:1;
++00259                 unsigned hnpcap:1;
++00260                 unsigned usbtrdtim:4;
++00261                 unsigned nptxfrwnden:1;
++00262                 unsigned phylpwrclksel:1;
++00263                 unsigned otgutmifssel:1;
++00264                 unsigned ulpi_fsls:1;
++00265                 unsigned ulpi_auto_res:1;
++00266                 unsigned ulpi_clk_sus_m:1;
++00267                 unsigned ulpi_ext_vbus_drv:1;
++00268                 unsigned ulpi_int_vbus_indicator:1;
++00269                 unsigned term_sel_dl_pulse:1;
++00270                 unsigned reserved23_25:3;
++00271                 unsigned ic_usb_cap:1;
++00272                 unsigned ic_traffic_pull_remove:1;
++00273                 unsigned tx_end_delay:1;
++00274                 unsigned reserved29_31:3;
++00275         } b;
++00276 } gusbcfg_data_t;
++00277 
++00283 typedef union glpmctl_data {
++00285         uint32_t d32;
++00287         struct {
++00292                 unsigned lpm_cap_en:1;
++00297                 unsigned appl_resp:1;
++00306                 unsigned hird:4;
++00315                 unsigned rem_wkup_en:1;
++00320                 unsigned en_utmi_sleep:1;
++00323                 unsigned hird_thres:5;
++00334                 unsigned lpm_resp:2;
++00339                 unsigned prt_sleep_sts:1;
++00344                 unsigned sleep_state_resumeok:1;
++00350                 unsigned lpm_chan_index:4;
++00355                 unsigned retry_count:3;
++00361                 unsigned send_lpm:1;
++00366                 unsigned retry_count_sts:3;
++00367                 unsigned reserved28_29:2;
++00375                 unsigned hsic_connect:1;
++00379                 unsigned inv_sel_hsic:1;
++00380         } b;
++00381 } glpmcfg_data_t;
++00382 
++00388 typedef union grstctl_data {
++00390         uint32_t d32;
++00392         struct {
++00428                 unsigned csftrst:1;
++00435                 unsigned hsftrst:1;
++00444                 unsigned hstfrm:1;
++00448                 unsigned intknqflsh:1;
++00463                 unsigned rxfflsh:1;
++00478                 unsigned txfflsh:1;
++00479 
++00495                 unsigned txfnum:5;
++00497                 unsigned reserved11_29:19;
++00500                 unsigned dmareq:1;
++00503                 unsigned ahbidle:1;
++00504         } b;
++00505 } grstctl_t;
++00506 
++00512 typedef union gintmsk_data {
++00514         uint32_t d32;
++00516         struct {
++00517                 unsigned reserved0:1;
++00518                 unsigned modemismatch:1;
++00519                 unsigned otgintr:1;
++00520                 unsigned sofintr:1;
++00521                 unsigned rxstsqlvl:1;
++00522                 unsigned nptxfempty:1;
++00523                 unsigned ginnakeff:1;
++00524                 unsigned goutnakeff:1;
++00525                 unsigned reserved8:1;
++00526                 unsigned i2cintr:1;
++00527                 unsigned erlysuspend:1;
++00528                 unsigned usbsuspend:1;
++00529                 unsigned usbreset:1;
++00530                 unsigned enumdone:1;
++00531                 unsigned isooutdrop:1;
++00532                 unsigned eopframe:1;
++00533                 unsigned reserved16:1;
++00534                 unsigned epmismatch:1;
++00535                 unsigned inepintr:1;
++00536                 unsigned outepintr:1;
++00537                 unsigned incomplisoin:1;
++00538                 unsigned incomplisoout:1;
++00539                 unsigned reserved22_23:2;
++00540                 unsigned portintr:1;
++00541                 unsigned hcintr:1;
++00542                 unsigned ptxfempty:1;
++00543                 unsigned lpmtranrcvd:1;
++00544                 unsigned conidstschng:1;
++00545                 unsigned disconnect:1;
++00546                 unsigned sessreqintr:1;
++00547                 unsigned wkupintr:1;
++00548         } b;
++00549 } gintmsk_data_t;
++00555 typedef union gintsts_data {
++00557         uint32_t d32;
++00558 #define DWC_SOF_INTR_MASK 0x0008
++00559 
++00560         struct {
++00561 #define DWC_HOST_MODE 1
++00562                 unsigned curmode:1;
++00563                 unsigned modemismatch:1;
++00564                 unsigned otgintr:1;
++00565                 unsigned sofintr:1;
++00566                 unsigned rxstsqlvl:1;
++00567                 unsigned nptxfempty:1;
++00568                 unsigned ginnakeff:1;
++00569                 unsigned goutnakeff:1;
++00570                 unsigned reserved8:1;
++00571                 unsigned i2cintr:1;
++00572                 unsigned erlysuspend:1;
++00573                 unsigned usbsuspend:1;
++00574                 unsigned usbreset:1;
++00575                 unsigned enumdone:1;
++00576                 unsigned isooutdrop:1;
++00577                 unsigned eopframe:1;
++00578                 unsigned intokenrx:1;
++00579                 unsigned epmismatch:1;
++00580                 unsigned inepint:1;
++00581                 unsigned outepintr:1;
++00582                 unsigned incomplisoin:1;
++00583                 unsigned incomplisoout:1;
++00584                 unsigned reserved22_23:2;
++00585                 unsigned portintr:1;
++00586                 unsigned hcintr:1;
++00587                 unsigned ptxfempty:1;
++00588                 unsigned lpmtranrcvd:1;
++00589                 unsigned conidstschng:1;
++00590                 unsigned disconnect:1;
++00591                 unsigned sessreqintr:1;
++00592                 unsigned wkupintr:1;
++00593         } b;
++00594 } gintsts_data_t;
++00595 
++00601 typedef union device_grxsts_data {
++00603         uint32_t d32;
++00605         struct {
++00606                 unsigned epnum:4;
++00607                 unsigned bcnt:11;
++00608                 unsigned dpid:2;
++00609 
++00610 #define DWC_STS_DATA_UPDT               0x2     // OUT Data Packet
++00611 #define DWC_STS_XFER_COMP               0x3     // OUT Data Transfer Complete
++00612 
++00613 #define DWC_DSTS_GOUT_NAK               0x1     // Global OUT NAK
++00614 #define DWC_DSTS_SETUP_COMP             0x4     // Setup Phase Complete
++00615 #define DWC_DSTS_SETUP_UPDT 0x6 // SETUP Packet
++00616                 unsigned pktsts:4;
++00617                 unsigned fn:4;
++00618                 unsigned reserved:7;
++00619         } b;
++00620 } device_grxsts_data_t;
++00621 
++00627 typedef union host_grxsts_data {
++00629         uint32_t d32;
++00631         struct {
++00632                 unsigned chnum:4;
++00633                 unsigned bcnt:11;
++00634                 unsigned dpid:2;
++00635 
++00636                 unsigned pktsts:4;
++00637 #define DWC_GRXSTS_PKTSTS_IN                      0x2
++00638 #define DWC_GRXSTS_PKTSTS_IN_XFER_COMP    0x3
++00639 #define DWC_GRXSTS_PKTSTS_DATA_TOGGLE_ERR 0x5
++00640 #define DWC_GRXSTS_PKTSTS_CH_HALTED               0x7
++00641 
++00642                 unsigned reserved:11;
++00643         } b;
++00644 } host_grxsts_data_t;
++00645 
++00651 typedef union fifosize_data {
++00653         uint32_t d32;
++00655         struct {
++00656                 unsigned startaddr:16;
++00657                 unsigned depth:16;
++00658         } b;
++00659 } fifosize_data_t;
++00660 
++00667 typedef union gnptxsts_data {
++00669         uint32_t d32;
++00671         struct {
++00672                 unsigned nptxfspcavail:16;
++00673                 unsigned nptxqspcavail:8;
++00684                 unsigned nptxqtop_terminate:1;
++00685                 unsigned nptxqtop_token:2;
++00686                 unsigned nptxqtop_chnep:4;
++00687                 unsigned reserved:1;
++00688         } b;
++00689 } gnptxsts_data_t;
++00690 
++00697 typedef union dtxfsts_data {
++00699         uint32_t d32;
++00701         struct {
++00702                 unsigned txfspcavail:16;
++00703                 unsigned reserved:16;
++00704         } b;
++00705 } dtxfsts_data_t;
++00706 
++00712 typedef union gi2cctl_data {
++00714         uint32_t d32;
++00716         struct {
++00717                 unsigned rwdata:8;
++00718                 unsigned regaddr:8;
++00719                 unsigned addr:7;
++00720                 unsigned i2cen:1;
++00721                 unsigned ack:1;
++00722                 unsigned i2csuspctl:1;
++00723                 unsigned i2cdevaddr:2;
++00724                 unsigned reserved:2;
++00725                 unsigned rw:1;
++00726                 unsigned bsydne:1;
++00727         } b;
++00728 } gi2cctl_data_t;
++00729 
++00735 typedef union hwcfg1_data {
++00737         uint32_t d32;
++00739         struct {
++00740                 unsigned ep_dir0:2;
++00741                 unsigned ep_dir1:2;
++00742                 unsigned ep_dir2:2;
++00743                 unsigned ep_dir3:2;
++00744                 unsigned ep_dir4:2;
++00745                 unsigned ep_dir5:2;
++00746                 unsigned ep_dir6:2;
++00747                 unsigned ep_dir7:2;
++00748                 unsigned ep_dir8:2;
++00749                 unsigned ep_dir9:2;
++00750                 unsigned ep_dir10:2;
++00751                 unsigned ep_dir11:2;
++00752                 unsigned ep_dir12:2;
++00753                 unsigned ep_dir13:2;
++00754                 unsigned ep_dir14:2;
++00755                 unsigned ep_dir15:2;
++00756         } b;
++00757 } hwcfg1_data_t;
++00758 
++00764 typedef union hwcfg2_data {
++00766         uint32_t d32;
++00768         struct {
++00769                 /* GHWCFG2 */
++00770                 unsigned op_mode:3;
++00771 #define DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG 0
++00772 #define DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG 1
++00773 #define DWC_HWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE_OTG 2
++00774 #define DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE 3
++00775 #define DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE 4
++00776 #define DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST 5
++00777 #define DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST 6
++00778 
++00779                 unsigned architecture:2;
++00780                 unsigned point2point:1;
++00781                 unsigned hs_phy_type:2;
++00782 #define DWC_HWCFG2_HS_PHY_TYPE_NOT_SUPPORTED 0
++00783 #define DWC_HWCFG2_HS_PHY_TYPE_UTMI 1
++00784 #define DWC_HWCFG2_HS_PHY_TYPE_ULPI 2
++00785 #define DWC_HWCFG2_HS_PHY_TYPE_UTMI_ULPI 3
++00786 
++00787                 unsigned fs_phy_type:2;
++00788                 unsigned num_dev_ep:4;
++00789                 unsigned num_host_chan:4;
++00790                 unsigned perio_ep_supported:1;
++00791                 unsigned dynamic_fifo:1;
++00792                 unsigned multi_proc_int:1;
++00793                 unsigned reserved21:1;
++00794                 unsigned nonperio_tx_q_depth:2;
++00795                 unsigned host_perio_tx_q_depth:2;
++00796                 unsigned dev_token_q_depth:5;
++00797                 unsigned reserved31:1;
++00798         } b;
++00799 } hwcfg2_data_t;
++00800 
++00806 typedef union hwcfg3_data {
++00808         uint32_t d32;
++00810         struct {
++00811                 /* GHWCFG3 */
++00812                 unsigned xfer_size_cntr_width:4;
++00813                 unsigned packet_size_cntr_width:3;
++00814                 unsigned otg_func:1;
++00815                 unsigned i2c:1;
++00816                 unsigned vendor_ctrl_if:1;
++00817                 unsigned optional_features:1;
++00818                 unsigned synch_reset_type:1;
++00819                 unsigned otg_enable_ic_usb:1;
++00820                 unsigned otg_enable_hsic:1;
++00821                 unsigned reserved14:1;
++00822                 unsigned otg_lpm_en:1;
++00823                 unsigned dfifo_depth:16;
++00824         } b;
++00825 } hwcfg3_data_t;
++00826 
++00832 typedef union hwcfg4_data {
++00834         uint32_t d32;
++00836         struct {
++00837                 unsigned num_dev_perio_in_ep:4;
++00838                 unsigned power_optimiz:1;
++00839                 unsigned min_ahb_freq:9;
++00840                 unsigned utmi_phy_data_width:2;
++00841                 unsigned num_dev_mode_ctrl_ep:4;
++00842                 unsigned iddig_filt_en:1;
++00843                 unsigned vbus_valid_filt_en:1;
++00844                 unsigned a_valid_filt_en:1;
++00845                 unsigned b_valid_filt_en:1;
++00846                 unsigned session_end_filt_en:1;
++00847                 unsigned ded_fifo_en:1;
++00848                 unsigned num_in_eps:4;
++00849                 unsigned desc_dma:1;
++00850                 unsigned desc_dma_dyn:1;
++00851         } b;
++00852 } hwcfg4_data_t;
++00853 
++00855 // Device Registers
++00865 typedef struct dwc_otg_dev_global_regs {
++00867         volatile uint32_t dcfg;
++00869         volatile uint32_t dctl;
++00871         volatile uint32_t dsts;
++00873         uint32_t unused;
++00876         volatile uint32_t diepmsk;
++00879         volatile uint32_t doepmsk;
++00881         volatile uint32_t daint;
++00884         volatile uint32_t daintmsk;
++00887         volatile uint32_t dtknqr1;
++00890         volatile uint32_t dtknqr2;
++00892         volatile uint32_t dvbusdis;
++00894         volatile uint32_t dvbuspulse;
++00898         volatile uint32_t dtknqr3_dthrctl;
++00902         volatile uint32_t dtknqr4_fifoemptymsk;
++00905         volatile uint32_t deachint;
++00908         volatile uint32_t deachintmsk;
++00911         volatile uint32_t diepeachintmsk[MAX_EPS_CHANNELS];
++00914         volatile uint32_t doepeachintmsk[MAX_EPS_CHANNELS];
++00915 } dwc_otg_device_global_regs_t;
++00916 
++00923 typedef union dcfg_data {
++00925         uint32_t d32;
++00927         struct {
++00929                 unsigned devspd:2;
++00931                 unsigned nzstsouthshk:1;
++00932 #define DWC_DCFG_SEND_STALL 1
++00933 
++00934                 unsigned reserved3:1;
++00936                 unsigned devaddr:7;
++00938                 unsigned perfrint:2;
++00939 #define DWC_DCFG_FRAME_INTERVAL_80 0
++00940 #define DWC_DCFG_FRAME_INTERVAL_85 1
++00941 #define DWC_DCFG_FRAME_INTERVAL_90 2
++00942 #define DWC_DCFG_FRAME_INTERVAL_95 3
++00943 
++00944                 unsigned reserved13_17:5;
++00946                 unsigned epmscnt:5;
++00948                 unsigned descdma:1;
++00949         } b;
++00950 } dcfg_data_t;
++00951 
++00957 typedef union dctl_data {
++00959         uint32_t d32;
++00961         struct {
++00963                 unsigned rmtwkupsig:1;
++00965                 unsigned sftdiscon:1;
++00967                 unsigned gnpinnaksts:1;
++00969                 unsigned goutnaksts:1;
++00971                 unsigned tstctl:3;
++00973                 unsigned sgnpinnak:1;
++00975                 unsigned cgnpinnak:1;
++00977                 unsigned sgoutnak:1;
++00979                 unsigned cgoutnak:1;
++00980 
++00982                 unsigned pwronprgdone:1;
++00984                 unsigned gcontbna:1;
++00986                 unsigned gmc:2;
++00988                 unsigned ifrmnum:1;
++00990                 unsigned nakonbble:1;
++00991 
++00992                 unsigned reserved17_31:15;
++00993         } b;
++00994 } dctl_data_t;
++00995 
++01001 typedef union dsts_data {
++01003         uint32_t d32;
++01005         struct {
++01007                 unsigned suspsts:1;
++01009                 unsigned enumspd:2;
++01010 #define DWC_DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ 0
++01011 #define DWC_DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ 1
++01012 #define DWC_DSTS_ENUMSPD_LS_PHY_6MHZ               2
++01013 #define DWC_DSTS_ENUMSPD_FS_PHY_48MHZ              3
++01014 
++01015                 unsigned errticerr:1;
++01016                 unsigned reserved4_7:4;
++01018                 unsigned soffn:14;
++01019                 unsigned reserved22_31:10;
++01020         } b;
++01021 } dsts_data_t;
++01022 
++01030 typedef union diepint_data {
++01032         uint32_t d32;
++01034         struct {
++01036                 unsigned xfercompl:1;
++01038                 unsigned epdisabled:1;
++01040                 unsigned ahberr:1;
++01042                 unsigned timeout:1;
++01044                 unsigned intktxfemp:1;
++01046                 unsigned intknepmis:1;
++01048                 unsigned inepnakeff:1;
++01050                 unsigned emptyintr:1;
++01051 
++01052                 unsigned txfifoundrn:1;
++01053 
++01055                 unsigned bna:1;
++01056 
++01057                 unsigned reserved10_12:3;
++01059                 unsigned nak:1;
++01060 
++01061                 unsigned reserved14_31:18;
++01062         } b;
++01063 } diepint_data_t;
++01064 
++01069 typedef union diepint_data diepmsk_data_t;
++01070 
++01078 typedef union doepint_data {
++01080         uint32_t d32;
++01082         struct {
++01084                 unsigned xfercompl:1;
++01086                 unsigned epdisabled:1;
++01088                 unsigned ahberr:1;
++01090                 unsigned setup:1;
++01092                 unsigned outtknepdis:1;
++01093 
++01094                 unsigned stsphsercvd:1;
++01096                 unsigned back2backsetup:1;
++01097 
++01098                 unsigned reserved7:1;
++01100                 unsigned outpkterr:1;
++01102                 unsigned bna:1;
++01103 
++01104                 unsigned reserved10:1;
++01106                 unsigned pktdrpsts:1;
++01108                 unsigned babble:1;
++01110                 unsigned nak:1;
++01112                 unsigned nyet:1;
++01113 
++01114                 unsigned reserved15_31:17;
++01115         } b;
++01116 } doepint_data_t;
++01117 
++01122 typedef union doepint_data doepmsk_data_t;
++01123 
++01130 typedef union daint_data {
++01132         uint32_t d32;
++01134         struct {
++01136                 unsigned in:16;
++01138                 unsigned out:16;
++01139         } ep;
++01140         struct {
++01142                 unsigned inep0:1;
++01143                 unsigned inep1:1;
++01144                 unsigned inep2:1;
++01145                 unsigned inep3:1;
++01146                 unsigned inep4:1;
++01147                 unsigned inep5:1;
++01148                 unsigned inep6:1;
++01149                 unsigned inep7:1;
++01150                 unsigned inep8:1;
++01151                 unsigned inep9:1;
++01152                 unsigned inep10:1;
++01153                 unsigned inep11:1;
++01154                 unsigned inep12:1;
++01155                 unsigned inep13:1;
++01156                 unsigned inep14:1;
++01157                 unsigned inep15:1;
++01159                 unsigned outep0:1;
++01160                 unsigned outep1:1;
++01161                 unsigned outep2:1;
++01162                 unsigned outep3:1;
++01163                 unsigned outep4:1;
++01164                 unsigned outep5:1;
++01165                 unsigned outep6:1;
++01166                 unsigned outep7:1;
++01167                 unsigned outep8:1;
++01168                 unsigned outep9:1;
++01169                 unsigned outep10:1;
++01170                 unsigned outep11:1;
++01171                 unsigned outep12:1;
++01172                 unsigned outep13:1;
++01173                 unsigned outep14:1;
++01174                 unsigned outep15:1;
++01175         } b;
++01176 } daint_data_t;
++01177 
++01184 typedef union dtknq1_data {
++01186         uint32_t d32;
++01188         struct {
++01190                 unsigned intknwptr:5;
++01192                 unsigned reserved05_06:2;
++01194                 unsigned wrap_bit:1;
++01196                 unsigned epnums0_5:24;
++01197         } b;
++01198 } dtknq1_data_t;
++01199 
++01205 typedef union dthrctl_data {
++01207         uint32_t d32;
++01209         struct {
++01211                 unsigned non_iso_thr_en:1;
++01213                 unsigned iso_thr_en:1;
++01215                 unsigned tx_thr_len:9;
++01217                 unsigned ahb_thr_ratio:2;
++01219                 unsigned reserved13_15:3;
++01221                 unsigned rx_thr_en:1;
++01223                 unsigned rx_thr_len:9;
++01225                 unsigned reserved26_31:6;
++01226         } b;
++01227 } dthrctl_data_t;
++01228 
++01239 typedef struct dwc_otg_dev_in_ep_regs {
++01242         volatile uint32_t diepctl;
++01244         uint32_t reserved04;
++01247         volatile uint32_t diepint;
++01249         uint32_t reserved0C;
++01252         volatile uint32_t dieptsiz;
++01255         volatile uint32_t diepdma;
++01258         volatile uint32_t dtxfsts;
++01261         volatile uint32_t diepdmab;
++01262 } dwc_otg_dev_in_ep_regs_t;
++01263 
++01274 typedef struct dwc_otg_dev_out_ep_regs {
++01277         volatile uint32_t doepctl;
++01280         volatile uint32_t doepfn;
++01283         volatile uint32_t doepint;
++01285         uint32_t reserved0C;
++01288         volatile uint32_t doeptsiz;
++01291         volatile uint32_t doepdma;
++01293         uint32_t unused;
++01296         uint32_t doepdmab;
++01297 } dwc_otg_dev_out_ep_regs_t;
++01298 
++01304 typedef union depctl_data {
++01306         uint32_t d32;
++01308         struct {
++01316                 unsigned mps:11;
++01317 #define DWC_DEP0CTL_MPS_64       0
++01318 #define DWC_DEP0CTL_MPS_32       1
++01319 #define DWC_DEP0CTL_MPS_16       2
++01320 #define DWC_DEP0CTL_MPS_8        3
++01321 
++01325                 unsigned nextep:4;
++01326 
++01328                 unsigned usbactep:1;
++01329 
++01344                 unsigned dpid:1;
++01345 
++01347                 unsigned naksts:1;
++01348 
++01354                 unsigned eptype:2;
++01355 
++01359                 unsigned snp:1;
++01360 
++01362                 unsigned stall:1;
++01363 
++01367                 unsigned txfnum:4;
++01368 
++01370                 unsigned cnak:1;
++01372                 unsigned snak:1;
++01381                 unsigned setd0pid:1;
++01389                 unsigned setd1pid:1;
++01390 
++01392                 unsigned epdis:1;
++01394                 unsigned epena:1;
++01395         } b;
++01396 } depctl_data_t;
++01397 
++01403 typedef union deptsiz_data {
++01405         uint32_t d32;
++01407         struct {
++01409                 unsigned xfersize:19;
++01411                 unsigned pktcnt:10;
++01413                 unsigned mc:2;
++01414                 unsigned reserved:1;
++01415         } b;
++01416 } deptsiz_data_t;
++01417 
++01423 typedef union deptsiz0_data {
++01425         uint32_t d32;
++01427         struct {
++01429                 unsigned xfersize:7;
++01431                 unsigned reserved7_18:12;
++01433                 unsigned pktcnt:1;
++01435                 unsigned reserved20_28:9;
++01437                 unsigned supcnt:2;
++01438                 unsigned reserved31;
++01439         } b;
++01440 } deptsiz0_data_t;
++01441 
++01443 // DMA Descriptor Specific Structures
++01444 //
++01445 
++01448 #define BS_HOST_READY   0x0
++01449 #define BS_DMA_BUSY             0x1
++01450 #define BS_DMA_DONE             0x2
++01451 #define BS_HOST_BUSY    0x3
++01452 
++01455 #define RTS_SUCCESS             0x0
++01456 #define RTS_BUFFLUSH    0x1
++01457 #define RTS_RESERVED    0x2
++01458 #define RTS_BUFERR              0x3
++01459 
++01466 typedef union dev_dma_desc_sts {
++01468         uint32_t d32;
++01470         struct {
++01472                 unsigned bytes:16;
++01473 
++01474                 unsigned reserved16_22:7;
++01476                 unsigned mtrf:1;
++01478                 unsigned sr:1;
++01480                 unsigned ioc:1;
++01482                 unsigned sp:1;
++01484                 unsigned l:1;
++01486                 unsigned sts:2;
++01488                 unsigned bs:2;
++01489         } b;
++01490 
++01491 #ifdef DWC_EN_ISOC
++01492 
++01493         struct {
++01495                 unsigned rxbytes:11;
++01496 
++01497                 unsigned reserved11:1;
++01499                 unsigned framenum:11;
++01501                 unsigned pid:2;
++01503                 unsigned ioc:1;
++01505                 unsigned sp:1;
++01507                 unsigned l:1;
++01509                 unsigned rxsts:2;
++01511                 unsigned bs:2;
++01512         } b_iso_out;
++01513 
++01515         struct {
++01517                 unsigned txbytes:12;
++01519                 unsigned framenum:11;
++01521                 unsigned pid:2;
++01523                 unsigned ioc:1;
++01525                 unsigned sp:1;
++01527                 unsigned l:1;
++01529                 unsigned txsts:2;
++01531                 unsigned bs:2;
++01532         } b_iso_in;
++01533 #endif                          /* DWC_EN_ISOC */
++01534 } dev_dma_desc_sts_t;
++01535 
++01542 typedef struct dwc_otg_dev_dma_desc {
++01544         dev_dma_desc_sts_t status;
++01546         uint32_t buf;
++01547 } dwc_otg_dev_dma_desc_t;
++01548 
++01554 typedef struct dwc_otg_dev_if {
++01558         dwc_otg_device_global_regs_t *dev_global_regs;
++01559 #define DWC_DEV_GLOBAL_REG_OFFSET 0x800
++01560 
++01564         dwc_otg_dev_in_ep_regs_t *in_ep_regs[MAX_EPS_CHANNELS];
++01565 #define DWC_DEV_IN_EP_REG_OFFSET 0x900
++01566 #define DWC_EP_REG_OFFSET 0x20
++01567 
++01569         dwc_otg_dev_out_ep_regs_t *out_ep_regs[MAX_EPS_CHANNELS];
++01570 #define DWC_DEV_OUT_EP_REG_OFFSET 0xB00
++01571 
++01572         /* Device configuration information */
++01573         uint8_t speed;                           
++01574         uint8_t num_in_eps;              
++01575         uint8_t num_out_eps;             
++01578         uint16_t perio_tx_fifo_size[MAX_PERIO_FIFOS];
++01579 
++01581         uint16_t tx_fifo_size[MAX_TX_FIFOS];
++01582 
++01584         uint16_t rx_thr_en;
++01585         uint16_t iso_tx_thr_en;
++01586         uint16_t non_iso_tx_thr_en;
++01587 
++01588         uint16_t rx_thr_length;
++01589         uint16_t tx_thr_length;
++01590 
++01597         dwc_dma_t dma_setup_desc_addr[2];
++01598         dwc_otg_dev_dma_desc_t *setup_desc_addr[2];
++01599 
++01601         dwc_otg_dev_dma_desc_t *psetup;
++01602 
++01604         uint32_t setup_desc_index;
++01605 
++01607         dwc_dma_t dma_in_desc_addr;
++01608         dwc_otg_dev_dma_desc_t *in_desc_addr;
++01609 
++01611         dwc_dma_t dma_out_desc_addr;
++01612         dwc_otg_dev_dma_desc_t *out_desc_addr;
++01613 
++01615         uint32_t spd;
++01616 
++01617 } dwc_otg_dev_if_t;
++01618 
++01620 // Host Mode Register Structures
++01621 //
++01627 typedef struct dwc_otg_host_global_regs {
++01629         volatile uint32_t hcfg;
++01631         volatile uint32_t hfir;
++01633         volatile uint32_t hfnum;
++01635         uint32_t reserved40C;
++01637         volatile uint32_t hptxsts;
++01639         volatile uint32_t haint;
++01641         volatile uint32_t haintmsk;
++01643         volatile uint32_t hflbaddr;
++01644 } dwc_otg_host_global_regs_t;
++01645 
++01646 
++01652 typedef union hcfg_data
++01653 {
++01655         uint32_t d32;
++01656 
++01658         struct 
++01659         {
++01661                 unsigned fslspclksel:2;
++01662 #define DWC_HCFG_30_60_MHZ 0
++01663 #define DWC_HCFG_48_MHZ    1
++01664 #define DWC_HCFG_6_MHZ     2
++01665 
++01667                 unsigned fslssupp:1;
++01668                 unsigned reserved3_22 : 20;
++01670                 unsigned descdma : 1;
++01672                 unsigned frlisten: 2;
++01674                 unsigned perschedena: 1;
++01676                 unsigned perschedstat: 1;
++01677         } b;
++01678 } hcfg_data_t;
++01679 
++01684 typedef union hfir_data {
++01686         uint32_t d32;
++01687 
++01689         struct {
++01690                 unsigned frint:16;
++01691                 unsigned reserved:16;
++01692         } b;
++01693 } hfir_data_t;
++01694 
++01699 typedef union hfnum_data {
++01701         uint32_t d32;
++01702 
++01704         struct {
++01705                 unsigned frnum:16;
++01706 #define DWC_HFNUM_MAX_FRNUM 0x3FFF
++01707                 unsigned frrem:16;
++01708         } b;
++01709 } hfnum_data_t;
++01710 
++01711 typedef union hptxsts_data {
++01713         uint32_t d32;
++01714 
++01716         struct {
++01717                 unsigned ptxfspcavail:16;
++01718                 unsigned ptxqspcavail:8;
++01728                 unsigned ptxqtop_terminate:1;
++01729                 unsigned ptxqtop_token:2;
++01730                 unsigned ptxqtop_chnum:4;
++01731                 unsigned ptxqtop_odd:1;
++01732         } b;
++01733 } hptxsts_data_t;
++01734 
++01741 typedef union hprt0_data {
++01743         uint32_t d32;
++01745         struct {
++01746                 unsigned prtconnsts:1;
++01747                 unsigned prtconndet:1;
++01748                 unsigned prtena:1;
++01749                 unsigned prtenchng:1;
++01750                 unsigned prtovrcurract:1;
++01751                 unsigned prtovrcurrchng:1;
++01752                 unsigned prtres:1;
++01753                 unsigned prtsusp:1;
++01754                 unsigned prtrst:1;
++01755                 unsigned reserved9:1;
++01756                 unsigned prtlnsts:2;
++01757                 unsigned prtpwr:1;
++01758                 unsigned prttstctl:4;
++01759                 unsigned prtspd:2;
++01760 #define DWC_HPRT0_PRTSPD_HIGH_SPEED 0
++01761 #define DWC_HPRT0_PRTSPD_FULL_SPEED 1
++01762 #define DWC_HPRT0_PRTSPD_LOW_SPEED      2
++01763                 unsigned reserved19_31:13;
++01764         } b;
++01765 } hprt0_data_t;
++01766 
++01771 typedef union haint_data {
++01773         uint32_t d32;
++01775         struct {
++01776                 unsigned ch0:1;
++01777                 unsigned ch1:1;
++01778                 unsigned ch2:1;
++01779                 unsigned ch3:1;
++01780                 unsigned ch4:1;
++01781                 unsigned ch5:1;
++01782                 unsigned ch6:1;
++01783                 unsigned ch7:1;
++01784                 unsigned ch8:1;
++01785                 unsigned ch9:1;
++01786                 unsigned ch10:1;
++01787                 unsigned ch11:1;
++01788                 unsigned ch12:1;
++01789                 unsigned ch13:1;
++01790                 unsigned ch14:1;
++01791                 unsigned ch15:1;
++01792                 unsigned reserved:16;
++01793         } b;
++01794 
++01795         struct {
++01796                 unsigned chint:16;
++01797                 unsigned reserved:16;
++01798         } b2;
++01799 } haint_data_t;
++01800 
++01805 typedef union haintmsk_data {
++01807         uint32_t d32;
++01809         struct {
++01810                 unsigned ch0:1;
++01811                 unsigned ch1:1;
++01812                 unsigned ch2:1;
++01813                 unsigned ch3:1;
++01814                 unsigned ch4:1;
++01815                 unsigned ch5:1;
++01816                 unsigned ch6:1;
++01817                 unsigned ch7:1;
++01818                 unsigned ch8:1;
++01819                 unsigned ch9:1;
++01820                 unsigned ch10:1;
++01821                 unsigned ch11:1;
++01822                 unsigned ch12:1;
++01823                 unsigned ch13:1;
++01824                 unsigned ch14:1;
++01825                 unsigned ch15:1;
++01826                 unsigned reserved:16;
++01827         } b;
++01828 
++01829         struct {
++01830                 unsigned chint:16;
++01831                 unsigned reserved:16;
++01832         } b2;
++01833 } haintmsk_data_t;
++01834 
++01838 typedef struct dwc_otg_hc_regs 
++01839 {
++01841         volatile uint32_t hcchar;
++01843         volatile uint32_t hcsplt;
++01845         volatile uint32_t hcint;
++01847         volatile uint32_t hcintmsk;
++01849         volatile uint32_t hctsiz;
++01851         volatile uint32_t hcdma;
++01852         volatile uint32_t reserved;
++01854         volatile uint32_t hcdmab;
++01855 } dwc_otg_hc_regs_t;
++01856 
++01863 typedef union hcchar_data {
++01865         uint32_t d32;
++01866 
++01868         struct {
++01870                 unsigned mps:11;
++01871 
++01873                 unsigned epnum:4;
++01874 
++01876                 unsigned epdir:1;
++01877 
++01878                 unsigned reserved:1;
++01879 
++01881                 unsigned lspddev:1;
++01882 
++01884                 unsigned eptype:2;
++01885 
++01887                 unsigned multicnt:2;
++01888 
++01890                 unsigned devaddr:7;
++01891 
++01896                 unsigned oddfrm:1;
++01897 
++01899                 unsigned chdis:1;
++01900 
++01902                 unsigned chen:1;
++01903         } b;
++01904 } hcchar_data_t;
++01905 
++01906 typedef union hcsplt_data {
++01908         uint32_t d32;
++01909 
++01911         struct {
++01913                 unsigned prtaddr:7;
++01914 
++01916                 unsigned hubaddr:7;
++01917 
++01919                 unsigned xactpos:2;
++01920 #define DWC_HCSPLIT_XACTPOS_MID 0
++01921 #define DWC_HCSPLIT_XACTPOS_END 1
++01922 #define DWC_HCSPLIT_XACTPOS_BEGIN 2
++01923 #define DWC_HCSPLIT_XACTPOS_ALL 3
++01924 
++01926                 unsigned compsplt:1;
++01927 
++01929                 unsigned reserved:14;
++01930 
++01932                 unsigned spltena:1;
++01933         } b;
++01934 } hcsplt_data_t;
++01935 
++01940 typedef union hcint_data
++01941 {
++01943         uint32_t d32;
++01945         struct 
++01946         {
++01948                 unsigned xfercomp:1;
++01950                 unsigned chhltd:1;
++01952                 unsigned ahberr:1;
++01954                 unsigned stall:1;
++01956                 unsigned nak:1;
++01958                 unsigned ack:1;
++01960                 unsigned nyet:1;
++01962                 unsigned xacterr:1;
++01964                 unsigned bblerr:1;
++01966                 unsigned frmovrun:1;
++01968                 unsigned datatglerr:1;
++01970                 unsigned bna : 1;
++01972                 unsigned xcs_xact : 1;
++01974                 unsigned frm_list_roll : 1;
++01976                 unsigned reserved14_31 : 18;
++01977         } b;
++01978 } hcint_data_t;
++01979 
++01986 typedef union hcintmsk_data
++01987 {
++01989         uint32_t d32;
++01990 
++01992         struct 
++01993         {
++01994                 unsigned xfercompl : 1;
++01995                 unsigned chhltd : 1;
++01996                 unsigned ahberr : 1;
++01997                 unsigned stall : 1;
++01998                 unsigned nak : 1;
++01999                 unsigned ack : 1;
++02000                 unsigned nyet : 1;
++02001                 unsigned xacterr : 1;
++02002                 unsigned bblerr : 1;
++02003                 unsigned frmovrun : 1;
++02004                 unsigned datatglerr : 1;
++02005                 unsigned bna : 1;
++02006                 unsigned xcs_xact : 1;
++02007                 unsigned frm_list_roll : 1;
++02008                 unsigned reserved14_31 : 18;
++02009         } b;
++02010 } hcintmsk_data_t;
++02011 
++02019 typedef union hctsiz_data
++02020 {
++02022         uint32_t d32;
++02023 
++02025         struct 
++02026         {
++02028                 unsigned xfersize:19;
++02029 
++02031                 unsigned pktcnt:10;
++02032 
++02040                 unsigned pid:2;
++02041 #define DWC_HCTSIZ_DATA0 0
++02042 #define DWC_HCTSIZ_DATA1 2
++02043 #define DWC_HCTSIZ_DATA2 1
++02044 #define DWC_HCTSIZ_MDATA 3
++02045 #define DWC_HCTSIZ_SETUP 3
++02046 
++02048                 unsigned dopng:1;
++02049         } b;
++02050         
++02052         struct 
++02053         {
++02055                 unsigned schinfo : 8;
++02056                 
++02062                 unsigned ntd : 8;
++02063 
++02065                 unsigned reserved16_28 : 13;
++02066 
++02074                 unsigned pid : 2;
++02075 
++02077                 unsigned dopng : 1;
++02078         } b_ddma;
++02079 } hctsiz_data_t;
++02080 
++02081 
++02086 typedef union hcdma_data
++02087 {
++02089         uint32_t d32;
++02091         struct 
++02092         {
++02093                 unsigned reserved0_2 : 3;
++02095                 unsigned ctd : 8;
++02097                 unsigned dma_addr : 21;
++02098         } b;
++02099 } hcdma_data_t;
++02100 
++02106 typedef union host_dma_desc_sts
++02107 {
++02109         uint32_t d32;
++02112         /* for non-isochronous  */
++02113         struct {
++02115                 unsigned n_bytes : 17;
++02117                 unsigned qtd_offset : 6;
++02122                 unsigned a_qtd : 1;
++02127                 unsigned sup : 1;
++02129                 unsigned ioc : 1;
++02131                 unsigned eol : 1;
++02132                 unsigned reserved27 : 1;
++02134                 unsigned sts : 2;
++02135         #define DMA_DESC_STS_PKTERR     1
++02136                 unsigned reserved30 : 1;
++02138                 unsigned a : 1;
++02139         } b;
++02140         /* for isochronous */
++02141         struct {
++02143                 unsigned n_bytes : 12;
++02144                 unsigned reserved12_24 : 13;
++02146                 unsigned ioc : 1;
++02147                 unsigned reserved26_27 : 2;
++02149                 unsigned sts : 2;
++02150                 unsigned reserved30 : 1;
++02152                 unsigned a : 1;
++02153         } b_isoc;
++02154 } host_dma_desc_sts_t;
++02155 
++02156 #define MAX_DMA_DESC_SIZE               131071
++02157 #define MAX_DMA_DESC_NUM_GENERIC        64
++02158 #define MAX_DMA_DESC_NUM_HS_ISOC        256
++02159 #define MAX_FRLIST_EN_NUM               64
++02160 
++02166 typedef struct dwc_otg_host_dma_desc
++02167 {
++02169         host_dma_desc_sts_t     status;
++02171         uint32_t        buf;
++02172 } dwc_otg_host_dma_desc_t;
++02173 
++02181 typedef struct dwc_otg_host_if {
++02183         dwc_otg_host_global_regs_t *host_global_regs;
++02184 #define DWC_OTG_HOST_GLOBAL_REG_OFFSET 0x400
++02185 
++02187         volatile uint32_t *hprt0;
++02188 #define DWC_OTG_HOST_PORT_REGS_OFFSET 0x440
++02189 
++02191         dwc_otg_hc_regs_t *hc_regs[MAX_EPS_CHANNELS];
++02192 #define DWC_OTG_HOST_CHAN_REGS_OFFSET 0x500
++02193 #define DWC_OTG_CHAN_REGS_OFFSET 0x20
++02194 
++02195         /* Host configuration information */
++02197         uint8_t num_host_channels;
++02199         uint8_t perio_eps_supported;
++02201         uint16_t perio_tx_fifo_size;
++02202 
++02203 } dwc_otg_host_if_t;
++02204 
++02210 typedef union pcgcctl_data {
++02212         uint32_t d32;
++02213 
++02215         struct {
++02217                 unsigned stoppclk:1;
++02219                 unsigned gatehclk:1;
++02221                 unsigned pwrclmp:1;
++02223                 unsigned rstpdwnmodule:1;
++02225                 unsigned physuspended:1;
++02227                 unsigned enbl_sleep_gating:1;
++02229                 unsigned phy_in_sleep:1;
++02231                 unsigned deep_sleep:1;
++02232 
++02233                 unsigned reserved31_8:24;
++02234         } b;
++02235 } pcgcctl_data_t;
++02236 
++02237 #endif
++
Generated on Tue May 5 02:22:48 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__regs_8h.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__regs_8h.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,1468 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_regs.h File Reference ++ ++ ++ ++ ++
++
++
++
++

dwc_otg_regs.h File Reference

This file contains the data structures for accessing the DWC_otg core registers. More... ++

++#include "dwc_otg_core_if.h"
++ ++

++Go to the source code of this file. ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++

Data Structures

struct  dwc_otg_core_global_regs
 DWC_otg Core registers . More...
union  gotgctl_data
 This union represents the bit fields of the Core OTG Control and Status Register (GOTGCTL). More...
union  gotgint_data
 This union represents the bit fields of the Core OTG Interrupt Register (GOTGINT). More...
union  gahbcfg_data
 This union represents the bit fields of the Core AHB Configuration Register (GAHBCFG). More...
union  gusbcfg_data
 This union represents the bit fields of the Core USB Configuration Register (GUSBCFG). More...
union  glpmctl_data
 This union represents the bit fields of the Core LPM Configuration Register (GLPMCFG). More...
union  grstctl_data
 This union represents the bit fields of the Core Reset Register (GRSTCTL). More...
union  gintmsk_data
 This union represents the bit fields of the Core Interrupt Mask Register (GINTMSK). More...
union  gintsts_data
 This union represents the bit fields of the Core Interrupt Register (GINTSTS). More...
union  device_grxsts_data
 This union represents the bit fields in the Device Receive Status Read and Pop Registers (GRXSTSR, GRXSTSP) Read the register into the d32 element then read out the bits using the bit elements. More...
union  host_grxsts_data
 This union represents the bit fields in the Host Receive Status Read and Pop Registers (GRXSTSR, GRXSTSP) Read the register into the d32 element then read out the bits using the bit elements. More...
union  fifosize_data
 This union represents the bit fields in the FIFO Size Registers (HPTXFSIZ, GNPTXFSIZ, DPTXFSIZn, DIEPTXFn). More...
union  gnptxsts_data
 This union represents the bit fields in the Non-Periodic Transmit FIFO/Queue Status Register (GNPTXSTS). More...
union  dtxfsts_data
 This union represents the bit fields in the Transmit FIFO Status Register (DTXFSTS). More...
union  gi2cctl_data
 This union represents the bit fields in the I2C Control Register (I2CCTL). More...
union  hwcfg1_data
 This union represents the bit fields in the User HW Config1 Register. More...
union  hwcfg2_data
 This union represents the bit fields in the User HW Config2 Register. More...
union  hwcfg3_data
 This union represents the bit fields in the User HW Config3 Register. More...
union  hwcfg4_data
 This union represents the bit fields in the User HW Config4 Register. More...
struct  dwc_otg_dev_global_regs
 Device Global Registers. More...
union  dcfg_data
 This union represents the bit fields in the Device Configuration Register. More...
union  dctl_data
 This union represents the bit fields in the Device Control Register. More...
union  dsts_data
 This union represents the bit fields in the Device Status Register. More...
union  diepint_data
 This union represents the bit fields in the Device IN EP Interrupt Register and the Device IN EP Common Mask Register. More...
union  doepint_data
 This union represents the bit fields in the Device OUT EP Interrupt Registerand Device OUT EP Common Interrupt Mask Register. More...
union  daint_data
 This union represents the bit fields in the Device All EP Interrupt and Mask Registers. More...
union  dtknq1_data
 This union represents the bit fields in the Device IN Token Queue Read Registers. More...
union  dthrctl_data
 This union represents Threshold control Register
    ++
  • Read and write the register into the d32 member.
++ More...
struct  dwc_otg_dev_in_ep_regs
 Device Logical IN Endpoint-Specific Registers. More...
struct  dwc_otg_dev_out_ep_regs
 Device Logical OUT Endpoint-Specific Registers. More...
union  depctl_data
 This union represents the bit fields in the Device EP Control Register. More...
union  deptsiz_data
 This union represents the bit fields in the Device EP Transfer Size Register. More...
union  deptsiz0_data
 This union represents the bit fields in the Device EP 0 Transfer Size Register. More...
union  dev_dma_desc_sts
 This union represents the bit fields in the DMA Descriptor status quadlet. More...
struct  dwc_otg_dev_dma_desc
 DMA Descriptor structure. More...
struct  dwc_otg_dev_if
 The dwc_otg_dev_if structure contains information needed to manage the DWC_otg controller acting in device mode. More...
struct  dwc_otg_host_global_regs
 The Host Global Registers structure defines the size and relative field offsets for the Host Mode Global Registers. More...
union  hcfg_data
 This union represents the bit fields in the Host Configuration Register. More...
union  hfir_data
 This union represents the bit fields in the Host Frame Remaing/Number Register. More...
union  hfnum_data
 This union represents the bit fields in the Host Frame Remaing/Number Register. More...
union  hptxsts_data
union  hprt0_data
 This union represents the bit fields in the Host Port Control and Status Register. More...
union  haint_data
 This union represents the bit fields in the Host All Interrupt Register. More...
union  haintmsk_data
 This union represents the bit fields in the Host All Interrupt Register. More...
struct  dwc_otg_hc_regs
 Host Channel Specific Registers. More...
union  hcchar_data
 This union represents the bit fields in the Host Channel Characteristics Register. More...
union  hcsplt_data
union  hcint_data
 This union represents the bit fields in the Host All Interrupt Register. More...
union  hcintmsk_data
 This union represents the bit fields in the Host Channel Interrupt Mask Register. More...
union  hctsiz_data
 This union represents the bit fields in the Host Channel Transfer Size Register. More...
union  hcdma_data
 This union represents the bit fields in the Host DMA Address Register used in Descriptor DMA mode. More...
union  host_dma_desc_sts
 This union represents the bit fields in the DMA Descriptor status quadlet for host mode. More...
struct  dwc_otg_host_dma_desc
 Host-mode DMA Descriptor structure. More...
struct  dwc_otg_host_if
 OTG Host Interface Structure. More...
union  pcgcctl_data
 This union represents the bit fields in the Power and Clock Gating Control Register. More...

Defines

++#define DWC_GLBINTRMASK   0x0001
++#define DWC_DMAENABLE   0x0020
++#define DWC_NPTXEMPTYLVL_EMPTY   0x0080
++#define DWC_NPTXEMPTYLVL_HALFEMPTY   0x0000
++#define DWC_PTXEMPTYLVL_EMPTY   0x0100
++#define DWC_PTXEMPTYLVL_HALFEMPTY   0x0000
++#define DWC_SLAVE_ONLY_ARCH   0
++#define DWC_EXT_DMA_ARCH   1
++#define DWC_INT_DMA_ARCH   2
++#define DWC_MODE_HNP_SRP_CAPABLE   0
++#define DWC_MODE_SRP_ONLY_CAPABLE   1
++#define DWC_MODE_NO_HNP_SRP_CAPABLE   2
++#define DWC_MODE_SRP_CAPABLE_DEVICE   3
++#define DWC_MODE_NO_SRP_CAPABLE_DEVICE   4
++#define DWC_MODE_SRP_CAPABLE_HOST   5
++#define DWC_MODE_NO_SRP_CAPABLE_HOST   6
++#define DWC_GAHBCFG_GLBINT_ENABLE   1
++#define DWC_GAHBCFG_INT_DMA_BURST_SINGLE   0
++#define DWC_GAHBCFG_INT_DMA_BURST_INCR   1
++#define DWC_GAHBCFG_INT_DMA_BURST_INCR4   3
++#define DWC_GAHBCFG_INT_DMA_BURST_INCR8   5
++#define DWC_GAHBCFG_INT_DMA_BURST_INCR16   7
++#define DWC_GAHBCFG_DMAENABLE   1
++#define DWC_GAHBCFG_TXFEMPTYLVL_EMPTY   1
++#define DWC_GAHBCFG_TXFEMPTYLVL_HALFEMPTY   0
++#define DWC_SOF_INTR_MASK   0x0008
++#define DWC_HOST_MODE   1
++#define DWC_STS_DATA_UPDT   0x2
++#define DWC_STS_XFER_COMP   0x3
++#define DWC_DSTS_GOUT_NAK   0x1
++#define DWC_DSTS_SETUP_COMP   0x4
++#define DWC_DSTS_SETUP_UPDT   0x6
++#define DWC_GRXSTS_PKTSTS_IN   0x2
++#define DWC_GRXSTS_PKTSTS_IN_XFER_COMP   0x3
++#define DWC_GRXSTS_PKTSTS_DATA_TOGGLE_ERR   0x5
++#define DWC_GRXSTS_PKTSTS_CH_HALTED   0x7
++#define DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG   0
++#define DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG   1
++#define DWC_HWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE_OTG   2
++#define DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE   3
++#define DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE   4
++#define DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST   5
++#define DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST   6
++#define DWC_HWCFG2_HS_PHY_TYPE_NOT_SUPPORTED   0
++#define DWC_HWCFG2_HS_PHY_TYPE_UTMI   1
++#define DWC_HWCFG2_HS_PHY_TYPE_ULPI   2
++#define DWC_HWCFG2_HS_PHY_TYPE_UTMI_ULPI   3
++#define DWC_DCFG_SEND_STALL   1
++#define DWC_DCFG_FRAME_INTERVAL_80   0
++#define DWC_DCFG_FRAME_INTERVAL_85   1
++#define DWC_DCFG_FRAME_INTERVAL_90   2
++#define DWC_DCFG_FRAME_INTERVAL_95   3
++#define DWC_DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ   0
++#define DWC_DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ   1
++#define DWC_DSTS_ENUMSPD_LS_PHY_6MHZ   2
++#define DWC_DSTS_ENUMSPD_FS_PHY_48MHZ   3
++#define DWC_DEP0CTL_MPS_64   0
++#define DWC_DEP0CTL_MPS_32   1
++#define DWC_DEP0CTL_MPS_16   2
++#define DWC_DEP0CTL_MPS_8   3
++#define BS_HOST_READY   0x0
 Buffer status definitions.
++#define BS_DMA_BUSY   0x1
++#define BS_DMA_DONE   0x2
++#define BS_HOST_BUSY   0x3
++#define RTS_SUCCESS   0x0
 Receive/Transmit status definitions.
++#define RTS_BUFFLUSH   0x1
++#define RTS_RESERVED   0x2
++#define RTS_BUFERR   0x3
++#define DWC_DEV_GLOBAL_REG_OFFSET   0x800
++#define DWC_DEV_IN_EP_REG_OFFSET   0x900
++#define DWC_EP_REG_OFFSET   0x20
++#define DWC_DEV_OUT_EP_REG_OFFSET   0xB00
++#define DWC_HCFG_30_60_MHZ   0
++#define DWC_HCFG_48_MHZ   1
++#define DWC_HCFG_6_MHZ   2
++#define DWC_HFNUM_MAX_FRNUM   0x3FFF
++#define DWC_HPRT0_PRTSPD_HIGH_SPEED   0
++#define DWC_HPRT0_PRTSPD_FULL_SPEED   1
++#define DWC_HPRT0_PRTSPD_LOW_SPEED   2
++#define DWC_HCSPLIT_XACTPOS_MID   0
++#define DWC_HCSPLIT_XACTPOS_END   1
++#define DWC_HCSPLIT_XACTPOS_BEGIN   2
++#define DWC_HCSPLIT_XACTPOS_ALL   3
++#define DWC_HCTSIZ_DATA0   0
++#define DWC_HCTSIZ_DATA1   2
++#define DWC_HCTSIZ_DATA2   1
++#define DWC_HCTSIZ_MDATA   3
++#define DWC_HCTSIZ_SETUP   3
++#define DMA_DESC_STS_PKTERR   1
++#define MAX_DMA_DESC_SIZE   131071
++#define MAX_DMA_DESC_NUM_GENERIC   64
++#define MAX_DMA_DESC_NUM_HS_ISOC   256
++#define MAX_FRLIST_EN_NUM   64
++#define DWC_OTG_HOST_GLOBAL_REG_OFFSET   0x400
++#define DWC_OTG_HOST_PORT_REGS_OFFSET   0x440
++#define DWC_OTG_HOST_CHAN_REGS_OFFSET   0x500
++#define DWC_OTG_CHAN_REGS_OFFSET   0x20

Typedefs

typedef dwc_otg_core_global_regs dwc_otg_core_global_regs_t
 DWC_otg Core registers .
typedef gotgctl_data gotgctl_data_t
 This union represents the bit fields of the Core OTG Control and Status Register (GOTGCTL).
typedef gotgint_data gotgint_data_t
 This union represents the bit fields of the Core OTG Interrupt Register (GOTGINT).
typedef gahbcfg_data gahbcfg_data_t
 This union represents the bit fields of the Core AHB Configuration Register (GAHBCFG).
typedef gusbcfg_data gusbcfg_data_t
 This union represents the bit fields of the Core USB Configuration Register (GUSBCFG).
typedef glpmctl_data glpmcfg_data_t
 This union represents the bit fields of the Core LPM Configuration Register (GLPMCFG).
typedef grstctl_data grstctl_t
 This union represents the bit fields of the Core Reset Register (GRSTCTL).
typedef gintmsk_data gintmsk_data_t
 This union represents the bit fields of the Core Interrupt Mask Register (GINTMSK).
typedef gintsts_data gintsts_data_t
 This union represents the bit fields of the Core Interrupt Register (GINTSTS).
++typedef device_grxsts_data device_grxsts_data_t
 This union represents the bit fields in the Device Receive Status Read and Pop Registers (GRXSTSR, GRXSTSP) Read the register into the d32 element then read out the bits using the bit elements.
++typedef host_grxsts_data host_grxsts_data_t
 This union represents the bit fields in the Host Receive Status Read and Pop Registers (GRXSTSR, GRXSTSP) Read the register into the d32 element then read out the bits using the bit elements.
typedef fifosize_data fifosize_data_t
 This union represents the bit fields in the FIFO Size Registers (HPTXFSIZ, GNPTXFSIZ, DPTXFSIZn, DIEPTXFn).
typedef gnptxsts_data gnptxsts_data_t
 This union represents the bit fields in the Non-Periodic Transmit FIFO/Queue Status Register (GNPTXSTS).
typedef dtxfsts_data dtxfsts_data_t
 This union represents the bit fields in the Transmit FIFO Status Register (DTXFSTS).
typedef gi2cctl_data gi2cctl_data_t
 This union represents the bit fields in the I2C Control Register (I2CCTL).
typedef hwcfg1_data hwcfg1_data_t
 This union represents the bit fields in the User HW Config1 Register.
typedef hwcfg2_data hwcfg2_data_t
 This union represents the bit fields in the User HW Config2 Register.
typedef hwcfg3_data hwcfg3_data_t
 This union represents the bit fields in the User HW Config3 Register.
typedef hwcfg4_data hwcfg4_data_t
 This union represents the bit fields in the User HW Config4 Register.
typedef dwc_otg_dev_global_regs dwc_otg_device_global_regs_t
 Device Global Registers.
typedef dcfg_data dcfg_data_t
 This union represents the bit fields in the Device Configuration Register.
typedef dctl_data dctl_data_t
 This union represents the bit fields in the Device Control Register.
typedef dsts_data dsts_data_t
 This union represents the bit fields in the Device Status Register.
typedef diepint_data diepint_data_t
 This union represents the bit fields in the Device IN EP Interrupt Register and the Device IN EP Common Mask Register.
++typedef diepint_data diepmsk_data_t
 This union represents the bit fields in the Device IN EP Common/Dedicated Interrupt Mask Register.
typedef doepint_data doepint_data_t
 This union represents the bit fields in the Device OUT EP Interrupt Registerand Device OUT EP Common Interrupt Mask Register.
++typedef doepint_data doepmsk_data_t
 This union represents the bit fields in the Device OUT EP Common/Dedicated Interrupt Mask Register.
typedef daint_data daint_data_t
 This union represents the bit fields in the Device All EP Interrupt and Mask Registers.
typedef dtknq1_data dtknq1_data_t
 This union represents the bit fields in the Device IN Token Queue Read Registers.
typedef dthrctl_data dthrctl_data_t
 This union represents Threshold control Register
    ++
  • Read and write the register into the d32 member.
++
typedef dwc_otg_dev_in_ep_regs dwc_otg_dev_in_ep_regs_t
 Device Logical IN Endpoint-Specific Registers.
typedef dwc_otg_dev_out_ep_regs dwc_otg_dev_out_ep_regs_t
 Device Logical OUT Endpoint-Specific Registers.
typedef depctl_data depctl_data_t
 This union represents the bit fields in the Device EP Control Register.
typedef deptsiz_data deptsiz_data_t
 This union represents the bit fields in the Device EP Transfer Size Register.
typedef deptsiz0_data deptsiz0_data_t
 This union represents the bit fields in the Device EP 0 Transfer Size Register.
typedef dev_dma_desc_sts dev_dma_desc_sts_t
 This union represents the bit fields in the DMA Descriptor status quadlet.
typedef dwc_otg_dev_dma_desc dwc_otg_dev_dma_desc_t
 DMA Descriptor structure.
typedef dwc_otg_dev_if dwc_otg_dev_if_t
 The dwc_otg_dev_if structure contains information needed to manage the DWC_otg controller acting in device mode.
typedef dwc_otg_host_global_regs dwc_otg_host_global_regs_t
 The Host Global Registers structure defines the size and relative field offsets for the Host Mode Global Registers.
typedef hcfg_data hcfg_data_t
 This union represents the bit fields in the Host Configuration Register.
++typedef hfir_data hfir_data_t
 This union represents the bit fields in the Host Frame Remaing/Number Register.
++typedef hfnum_data hfnum_data_t
 This union represents the bit fields in the Host Frame Remaing/Number Register.
++typedef hptxsts_data hptxsts_data_t
typedef hprt0_data hprt0_data_t
 This union represents the bit fields in the Host Port Control and Status Register.
++typedef haint_data haint_data_t
 This union represents the bit fields in the Host All Interrupt Register.
++typedef haintmsk_data haintmsk_data_t
 This union represents the bit fields in the Host All Interrupt Register.
typedef dwc_otg_hc_regs dwc_otg_hc_regs_t
 Host Channel Specific Registers.
typedef hcchar_data hcchar_data_t
 This union represents the bit fields in the Host Channel Characteristics Register.
++typedef hcsplt_data hcsplt_data_t
++typedef hcint_data hcint_data_t
 This union represents the bit fields in the Host All Interrupt Register.
typedef hcintmsk_data hcintmsk_data_t
 This union represents the bit fields in the Host Channel Interrupt Mask Register.
typedef hctsiz_data hctsiz_data_t
 This union represents the bit fields in the Host Channel Transfer Size Register.
++typedef hcdma_data hcdma_data_t
 This union represents the bit fields in the Host DMA Address Register used in Descriptor DMA mode.
typedef host_dma_desc_sts host_dma_desc_sts_t
 This union represents the bit fields in the DMA Descriptor status quadlet for host mode.
typedef dwc_otg_host_dma_desc dwc_otg_host_dma_desc_t
 Host-mode DMA Descriptor structure.
typedef dwc_otg_host_if dwc_otg_host_if_t
 OTG Host Interface Structure.
typedef pcgcctl_data pcgcctl_data_t
 This union represents the bit fields in the Power and Clock Gating Control Register.
++

Detailed Description

++This file contains the data structures for accessing the DWC_otg core registers. ++

++The application interfaces with the HS OTG core by reading from and writing to the Control and Status Register (CSR) space through the AHB Slave interface. These registers are 32 bits wide, and the addresses are 32-bit-block aligned. CSRs are classified as follows:

    ++
  • Core Global Registers
  • Device Mode Registers
  • Device Global Registers
  • Device Endpoint Specific Registers
  • Host Mode Registers
  • Host Global Registers
  • Host Port CSRs
  • Host Channel Specific Registers
++

++Only the Core Global registers can be accessed in both Device and Host modes. When the HS OTG core is operating in one mode, either Device or Host, the application must not access registers from the other mode. When the core switches from one mode to another, the registers in the new mode of operation must be reprogrammed as they would be after a power-on reset. ++

++Definition in file dwc_otg_regs.h.

Typedef Documentation

++ ++
++
++ ++ ++ ++ ++
typedef struct dwc_otg_core_global_regs dwc_otg_core_global_regs_t
++
++
++ ++

++DWC_otg Core registers . ++

++The dwc_otg_core_global_regs structure defines the size and relative field offsets for the Core Global registers. ++

++

++ ++

++
++ ++ ++ ++ ++
typedef union gotgctl_data gotgctl_data_t
++
++
++ ++

++This union represents the bit fields of the Core OTG Control and Status Register (GOTGCTL). ++

++Set the bits using the bit fields then write the d32 value to the register. ++

++

++ ++

++
++ ++ ++ ++ ++
typedef union gotgint_data gotgint_data_t
++
++
++ ++

++This union represents the bit fields of the Core OTG Interrupt Register (GOTGINT). ++

++Set/clear the bits using the bit fields then write the d32 value to the register. ++

++

++ ++

++
++ ++ ++ ++ ++
typedef union gahbcfg_data gahbcfg_data_t
++
++
++ ++

++This union represents the bit fields of the Core AHB Configuration Register (GAHBCFG). ++

++Set/clear the bits using the bit fields then write the d32 value to the register. ++

++

++ ++

++
++ ++ ++ ++ ++
typedef union gusbcfg_data gusbcfg_data_t
++
++
++ ++

++This union represents the bit fields of the Core USB Configuration Register (GUSBCFG). ++

++Set the bits using the bit fields then write the d32 value to the register. ++

++

++ ++

++
++ ++ ++ ++ ++
typedef union glpmctl_data glpmcfg_data_t
++
++
++ ++

++This union represents the bit fields of the Core LPM Configuration Register (GLPMCFG). ++

++Set the bits using bit fields then write the d32 value to the register. ++

++

++ ++

++
++ ++ ++ ++ ++
typedef union grstctl_data grstctl_t
++
++
++ ++

++This union represents the bit fields of the Core Reset Register (GRSTCTL). ++

++Set/clear the bits using the bit fields then write the d32 value to the register. ++

++

++ ++

++
++ ++ ++ ++ ++
typedef union gintmsk_data gintmsk_data_t
++
++
++ ++

++This union represents the bit fields of the Core Interrupt Mask Register (GINTMSK). ++

++Set/clear the bits using the bit fields then write the d32 value to the register. ++

++

++ ++

++
++ ++ ++ ++ ++
typedef union gintsts_data gintsts_data_t
++
++
++ ++

++This union represents the bit fields of the Core Interrupt Register (GINTSTS). ++

++Set/clear the bits using the bit fields then write the d32 value to the register. ++

++

++ ++

++
++ ++ ++ ++ ++
typedef union fifosize_data fifosize_data_t
++
++
++ ++

++This union represents the bit fields in the FIFO Size Registers (HPTXFSIZ, GNPTXFSIZ, DPTXFSIZn, DIEPTXFn). ++

++Read the register into the d32 element then read out the bits using the bit elements. ++

++

++ ++

++
++ ++ ++ ++ ++
typedef union gnptxsts_data gnptxsts_data_t
++
++
++ ++

++This union represents the bit fields in the Non-Periodic Transmit FIFO/Queue Status Register (GNPTXSTS). ++

++Read the register into the d32 element then read out the bits using the bit elements. ++

++

++ ++

++
++ ++ ++ ++ ++
typedef union dtxfsts_data dtxfsts_data_t
++
++
++ ++

++This union represents the bit fields in the Transmit FIFO Status Register (DTXFSTS). ++

++Read the register into the d32 element then read out the bits using the bit elements. ++

++

++ ++

++
++ ++ ++ ++ ++
typedef union gi2cctl_data gi2cctl_data_t
++
++
++ ++

++This union represents the bit fields in the I2C Control Register (I2CCTL). ++

++Read the register into the d32 element then read out the bits using the bit elements. ++

++

++ ++

++
++ ++ ++ ++ ++
typedef union hwcfg1_data hwcfg1_data_t
++
++
++ ++

++This union represents the bit fields in the User HW Config1 Register. ++

++Read the register into the d32 element then read out the bits using the bit elements. ++

++

++ ++

++
++ ++ ++ ++ ++
typedef union hwcfg2_data hwcfg2_data_t
++
++
++ ++

++This union represents the bit fields in the User HW Config2 Register. ++

++Read the register into the d32 element then read out the bits using the bit elements. ++

++

++ ++

++
++ ++ ++ ++ ++
typedef union hwcfg3_data hwcfg3_data_t
++
++
++ ++

++This union represents the bit fields in the User HW Config3 Register. ++

++Read the register into the d32 element then read out the bits using the bit elements. ++

++

++ ++

++
++ ++ ++ ++ ++
typedef union hwcfg4_data hwcfg4_data_t
++
++
++ ++

++This union represents the bit fields in the User HW Config4 Register. ++

++Read the register into the d32 element then read out the bits using the bit elements. ++

++

++ ++

++
++ ++ ++ ++ ++
typedef struct dwc_otg_dev_global_regs dwc_otg_device_global_regs_t
++
++
++ ++

++Device Global Registers. ++

++Offsets 800h-BFFh

++The following structures define the size and relative field offsets for the Device Mode Registers.

++These registers are visible only in Device mode and must not be accessed in Host mode, as the results are unknown. ++

++

++ ++

++
++ ++ ++ ++ ++
typedef union dcfg_data dcfg_data_t
++
++
++ ++

++This union represents the bit fields in the Device Configuration Register. ++

++Read the register into the d32 member then set/clear the bits using the bit elements. Write the d32 member to the dcfg register. ++

++

++ ++

++
++ ++ ++ ++ ++
typedef union dctl_data dctl_data_t
++
++
++ ++

++This union represents the bit fields in the Device Control Register. ++

++Read the register into the d32 member then set/clear the bits using the bit elements. ++

++

++ ++

++
++ ++ ++ ++ ++
typedef union dsts_data dsts_data_t
++
++
++ ++

++This union represents the bit fields in the Device Status Register. ++

++Read the register into the d32 member then set/clear the bits using the bit elements. ++

++

++ ++

++
++ ++ ++ ++ ++
typedef union diepint_data diepint_data_t
++
++
++ ++

++This union represents the bit fields in the Device IN EP Interrupt Register and the Device IN EP Common Mask Register. ++

++

    ++
  • Read the register into the d32 member then set/clear the bits using the bit elements.
++ ++
++

++ ++

++
++ ++ ++ ++ ++
typedef union doepint_data doepint_data_t
++
++
++ ++

++This union represents the bit fields in the Device OUT EP Interrupt Registerand Device OUT EP Common Interrupt Mask Register. ++

++

    ++
  • Read the register into the d32 member then set/clear the bits using the bit elements.
++ ++
++

++ ++

++
++ ++ ++ ++ ++
typedef union daint_data daint_data_t
++
++
++ ++

++This union represents the bit fields in the Device All EP Interrupt and Mask Registers. ++

++

    ++
  • Read the register into the d32 member then set/clear the bits using the bit elements.
++ ++
++

++ ++

++
++ ++ ++ ++ ++
typedef union dtknq1_data dtknq1_data_t
++
++
++ ++

++This union represents the bit fields in the Device IN Token Queue Read Registers. ++

++

    ++
  • Read the register into the d32 member.
  • READ-ONLY Register
++ ++
++

++ ++

++
++ ++ ++ ++ ++
typedef union dthrctl_data dthrctl_data_t
++
++
++ ++

++This union represents Threshold control Register

    ++
  • Read and write the register into the d32 member.
++ ++

++

    ++
  • READ-WRITABLE Register
++ ++
++

++ ++

++
++ ++ ++ ++ ++
typedef struct dwc_otg_dev_in_ep_regs dwc_otg_dev_in_ep_regs_t
++
++
++ ++

++Device Logical IN Endpoint-Specific Registers. ++

++Offsets 900h-AFCh

++There will be one set of endpoint registers per logical endpoint implemented.

++These registers are visible only in Device mode and must not be accessed in Host mode, as the results are unknown. ++

++

++ ++

++
++ ++ ++ ++ ++
typedef struct dwc_otg_dev_out_ep_regs dwc_otg_dev_out_ep_regs_t
++
++
++ ++

++Device Logical OUT Endpoint-Specific Registers. ++

++Offsets: B00h-CFCh

++There will be one set of endpoint registers per logical endpoint implemented.

++These registers are visible only in Device mode and must not be accessed in Host mode, as the results are unknown. ++

++

++ ++

++
++ ++ ++ ++ ++
typedef union depctl_data depctl_data_t
++
++
++ ++

++This union represents the bit fields in the Device EP Control Register. ++

++Read the register into the d32 member then set/clear the bits using the bit elements. ++

++

++ ++

++
++ ++ ++ ++ ++
typedef union deptsiz_data deptsiz_data_t
++
++
++ ++

++This union represents the bit fields in the Device EP Transfer Size Register. ++

++Read the register into the d32 member then set/clear the bits using the bit elements. ++

++

++ ++

++
++ ++ ++ ++ ++
typedef union deptsiz0_data deptsiz0_data_t
++
++
++ ++

++This union represents the bit fields in the Device EP 0 Transfer Size Register. ++

++Read the register into the d32 member then set/clear the bits using the bit elements. ++

++

++ ++

++
++ ++ ++ ++ ++
typedef union dev_dma_desc_sts dev_dma_desc_sts_t
++
++
++ ++

++This union represents the bit fields in the DMA Descriptor status quadlet. ++

++Read the quadlet into the d32 member then set/clear the bits using the bit, b_iso_out and b_iso_in elements. ++

++

++ ++

++
++ ++ ++ ++ ++
typedef struct dwc_otg_dev_dma_desc dwc_otg_dev_dma_desc_t
++
++
++ ++

++DMA Descriptor structure. ++

++DMA Descriptor structure contains two quadlets: Status quadlet and Data buffer pointer. ++

++

++ ++

++
++ ++ ++ ++ ++
typedef struct dwc_otg_dev_if dwc_otg_dev_if_t
++
++
++ ++

++The dwc_otg_dev_if structure contains information needed to manage the DWC_otg controller acting in device mode. ++

++It represents the programming view of the device-specific aspects of the controller. ++

++

++ ++

++
++ ++ ++ ++ ++
typedef struct dwc_otg_host_global_regs dwc_otg_host_global_regs_t
++
++
++ ++

++The Host Global Registers structure defines the size and relative field offsets for the Host Mode Global Registers. ++

++Host Global Registers offsets 400h-7FFh. ++

++

++ ++

++
++ ++ ++ ++ ++
typedef union hcfg_data hcfg_data_t
++
++
++ ++

++This union represents the bit fields in the Host Configuration Register. ++

++Read the register into the d32 member then set/clear the bits using the bit elements. Write the d32 member to the hcfg register. ++

++

++ ++

++
++ ++ ++ ++ ++
typedef union hprt0_data hprt0_data_t
++
++
++ ++

++This union represents the bit fields in the Host Port Control and Status Register. ++

++Read the register into the d32 member then set/clear the bits using the bit elements. Write the d32 member to the hprt0 register. ++

++

++ ++

++
++ ++ ++ ++ ++
typedef struct dwc_otg_hc_regs dwc_otg_hc_regs_t
++
++
++ ++

++Host Channel Specific Registers. ++

++500h-5FCh ++

++

++ ++

++
++ ++ ++ ++ ++
typedef union hcchar_data hcchar_data_t
++
++
++ ++

++This union represents the bit fields in the Host Channel Characteristics Register. ++

++Read the register into the d32 member then set/clear the bits using the bit elements. Write the d32 member to the hcchar register. ++

++

++ ++

++
++ ++ ++ ++ ++
typedef union hcintmsk_data hcintmsk_data_t
++
++
++ ++

++This union represents the bit fields in the Host Channel Interrupt Mask Register. ++

++Read the register into the d32 member then set/clear the bits using the bit elements. Write the d32 member to the hcintmsk register. ++

++

++ ++

++
++ ++ ++ ++ ++
typedef union hctsiz_data hctsiz_data_t
++
++
++ ++

++This union represents the bit fields in the Host Channel Transfer Size Register. ++

++Read the register into the d32 member then set/clear the bits using the bit elements. Write the d32 member to the hcchar register. ++

++

++ ++

++
++ ++ ++ ++ ++
typedef union host_dma_desc_sts host_dma_desc_sts_t
++
++
++ ++

++This union represents the bit fields in the DMA Descriptor status quadlet for host mode. ++

++Read the quadlet into the d32 member then set/clear the bits using the bit elements. ++

++

++ ++

++
++ ++ ++ ++ ++
typedef struct dwc_otg_host_dma_desc dwc_otg_host_dma_desc_t
++
++
++ ++

++Host-mode DMA Descriptor structure. ++

++DMA Descriptor structure contains two quadlets: Status quadlet and Data buffer pointer. ++

++

++ ++

++
++ ++ ++ ++ ++
typedef struct dwc_otg_host_if dwc_otg_host_if_t
++
++
++ ++

++OTG Host Interface Structure. ++

++The OTG Host Interface Structure structure contains information needed to manage the DWC_otg controller acting in host mode. It represents the programming view of the host-specific aspects of the controller. ++

++

++ ++

++
++ ++ ++ ++ ++
typedef union pcgcctl_data pcgcctl_data_t
++
++
++ ++

++This union represents the bit fields in the Power and Clock Gating Control Register. ++

++Read the register into the d32 member then set/clear the bits using the bit elements. ++

++

++

Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/files.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/files.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,52 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: File Index ++ ++ ++ ++ ++
++
++
++
++

DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver File List

Here is a list of all documented files with brief descriptions: ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
dummy_audio.c [code]
dwc_cfi_common.h [code]This file contains the CFI specific common constants, interfaces (functions and macros) and structures for Linux
dwc_otg_attr.c [code]The diagnostic interface will provide access to the controller for bringing up the hardware and testing
dwc_otg_attr.h [code]This file contains the interface to the Linux device attributes
dwc_otg_cfi.c [code]This file contains the most of the CFI implementation for the OTG
dwc_otg_cfi.h [code]This file contains the CFI related OTG PCD specific common constants, interfaces (functions and macros) and data structures
dwc_otg_cil.c [code]The Core Interface Layer provides basic services for accessing and managing the DWC_otg hardware
dwc_otg_cil.h [code]This file contains the interface to the Core Interface Layer
dwc_otg_cil_intr.c [code]The Core Interface Layer provides basic services for accessing and managing the DWC_otg hardware
dwc_otg_core_if.h [code]This file defines DWC_OTG Core API
dwc_otg_dbg.h [code]This file defines debug levels
dwc_otg_driver.c [code]The dwc_otg_driver module provides the initialization and cleanup entry points for the DWC_otg driver
dwc_otg_driver.h [code]This file contains the interface to the Linux driver
dwc_otg_hcd.c [code]This file implements HCD Core
dwc_otg_hcd.h [code]This file contains the structures, constants, and interfaces for the Host Contoller Driver (HCD)
dwc_otg_hcd_ddma.c [code]This file contains Descriptor DMA support implementation for host mode
dwc_otg_hcd_if.h [code]This file defines DWC_OTG HCD Core API
dwc_otg_hcd_intr.c [code]This file contains the implementation of the HCD Interrupt handlers
dwc_otg_hcd_linux.c [code]This file contains the implementation of the HCD
dwc_otg_hcd_queue.c [code]This file contains the functions to manage Queue Heads and Queue Transfer Descriptors
dwc_otg_pcd.c [code]This file implements PCD Core
dwc_otg_pcd.h [code]This file contains the structures, constants, and interfaces for the Perpherial Contoller Driver (PCD)
dwc_otg_pcd_if.h [code]This file defines DWC_OTG PCD Core API
dwc_otg_pcd_intr.c [code]This file contains the implementation of the PCD Interrupt handlers
dwc_otg_pcd_linux.c [code]This file implements the Peripheral Controller Driver
dwc_otg_regs.h [code]This file contains the data structures for accessing the DWC_otg core registers
++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/functions.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/functions.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,82 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields ++ ++ ++ ++ ++
++
++
++
++
++ ++
++
++
    ++
  • a
    • ++
  • b
    • ++
  • c
    • ++
  • d
    • ++
  • e
    • ++
  • f
    • ++
  • g
    • ++
  • h
    • ++
  • i
    • ++
  • l
    • ++
  • m
    • ++
  • n
    • ++
  • o
    • ++
  • p
    • ++
  • q
    • ++
  • r
    • ++
  • s
    • ++
  • t
    • ++
  • u
    • ++
  • v
    • ++
  • w
    • ++
  • x
    • ++
++
++ ++

++Here is a list of all documented struct and union fields with links to the struct/union documentation for each field: ++

++

- a -

++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/functions_0x62.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/functions_0x62.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,99 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields ++ ++ ++ ++ ++
++
++
++
++
++ ++
++
++
    ++
  • a
    • ++
  • b
    • ++
  • c
    • ++
  • d
    • ++
  • e
    • ++
  • f
    • ++
  • g
    • ++
  • h
    • ++
  • i
    • ++
  • l
    • ++
  • m
    • ++
  • n
    • ++
  • o
    • ++
  • p
    • ++
  • q
    • ++
  • r
    • ++
  • s
    • ++
  • t
    • ++
  • u
    • ++
  • v
    • ++
  • w
    • ++
  • x
    • ++
++
++ ++

++Here is a list of all documented struct and union fields with links to the struct/union documentation for each field: ++

++

- b -

++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/functions_0x63.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/functions_0x63.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,110 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields ++ ++ ++ ++ ++
++
++
++
++
++ ++
++
++
    ++
  • a
    • ++
  • b
    • ++
  • c
    • ++
  • d
    • ++
  • e
    • ++
  • f
    • ++
  • g
    • ++
  • h
    • ++
  • i
    • ++
  • l
    • ++
  • m
    • ++
  • n
    • ++
  • o
    • ++
  • p
    • ++
  • q
    • ++
  • r
    • ++
  • s
    • ++
  • t
    • ++
  • u
    • ++
  • v
    • ++
  • w
    • ++
  • x
    • ++
++
++ ++

++Here is a list of all documented struct and union fields with links to the struct/union documentation for each field: ++

++

- c -

++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/functions_0x64.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/functions_0x64.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,158 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields ++ ++ ++ ++ ++
++
++
++
++
++ ++
++
++
    ++
  • a
    • ++
  • b
    • ++
  • c
    • ++
  • d
    • ++
  • e
    • ++
  • f
    • ++
  • g
    • ++
  • h
    • ++
  • i
    • ++
  • l
    • ++
  • m
    • ++
  • n
    • ++
  • o
    • ++
  • p
    • ++
  • q
    • ++
  • r
    • ++
  • s
    • ++
  • t
    • ++
  • u
    • ++
  • v
    • ++
  • w
    • ++
  • x
    • ++
++
++ ++

++Here is a list of all documented struct and union fields with links to the struct/union documentation for each field: ++

++

- d -

++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/functions_0x65.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/functions_0x65.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,109 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields ++ ++ ++ ++ ++
++
++
++
++
++ ++
++
++
    ++
  • a
    • ++
  • b
    • ++
  • c
    • ++
  • d
    • ++
  • e
    • ++
  • f
    • ++
  • g
    • ++
  • h
    • ++
  • i
    • ++
  • l
    • ++
  • m
    • ++
  • n
    • ++
  • o
    • ++
  • p
    • ++
  • q
    • ++
  • r
    • ++
  • s
    • ++
  • t
    • ++
  • u
    • ++
  • v
    • ++
  • w
    • ++
  • x
    • ++
++
++ ++

++Here is a list of all documented struct and union fields with links to the struct/union documentation for each field: ++

++

- e -

++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/functions_0x66.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/functions_0x66.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,81 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields ++ ++ ++ ++ ++
++
++
++
++
++ ++
++
++
    ++
  • a
    • ++
  • b
    • ++
  • c
    • ++
  • d
    • ++
  • e
    • ++
  • f
    • ++
  • g
    • ++
  • h
    • ++
  • i
    • ++
  • l
    • ++
  • m
    • ++
  • n
    • ++
  • o
    • ++
  • p
    • ++
  • q
    • ++
  • r
    • ++
  • s
    • ++
  • t
    • ++
  • u
    • ++
  • v
    • ++
  • w
    • ++
  • x
    • ++
++
++ ++

++Here is a list of all documented struct and union fields with links to the struct/union documentation for each field: ++

++

- f -

++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/functions_0x67.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/functions_0x67.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,95 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields ++ ++ ++ ++ ++
++
++
++
++
++ ++
++
++
    ++
  • a
    • ++
  • b
    • ++
  • c
    • ++
  • d
    • ++
  • e
    • ++
  • f
    • ++
  • g
    • ++
  • h
    • ++
  • i
    • ++
  • l
    • ++
  • m
    • ++
  • n
    • ++
  • o
    • ++
  • p
    • ++
  • q
    • ++
  • r
    • ++
  • s
    • ++
  • t
    • ++
  • u
    • ++
  • v
    • ++
  • w
    • ++
  • x
    • ++
++
++ ++

++Here is a list of all documented struct and union fields with links to the struct/union documentation for each field: ++

++

- g -

++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/functions_0x68.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/functions_0x68.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,119 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields ++ ++ ++ ++ ++
++
++
++
++
++ ++
++
++
    ++
  • a
    • ++
  • b
    • ++
  • c
    • ++
  • d
    • ++
  • e
    • ++
  • f
    • ++
  • g
    • ++
  • h
    • ++
  • i
    • ++
  • l
    • ++
  • m
    • ++
  • n
    • ++
  • o
    • ++
  • p
    • ++
  • q
    • ++
  • r
    • ++
  • s
    • ++
  • t
    • ++
  • u
    • ++
  • v
    • ++
  • w
    • ++
  • x
    • ++
++
++ ++

++Here is a list of all documented struct and union fields with links to the struct/union documentation for each field: ++

++

- h -

++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/functions_0x69.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/functions_0x69.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,121 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields ++ ++ ++ ++ ++
++
++
++
++
++ ++
++
++
    ++
  • a
    • ++
  • b
    • ++
  • c
    • ++
  • d
    • ++
  • e
    • ++
  • f
    • ++
  • g
    • ++
  • h
    • ++
  • i
    • ++
  • l
    • ++
  • m
    • ++
  • n
    • ++
  • o
    • ++
  • p
    • ++
  • q
    • ++
  • r
    • ++
  • s
    • ++
  • t
    • ++
  • u
    • ++
  • v
    • ++
  • w
    • ++
  • x
    • ++
++
++ ++

++Here is a list of all documented struct and union fields with links to the struct/union documentation for each field: ++

++

- i -

++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/functions_0x6c.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/functions_0x6c.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,74 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields ++ ++ ++ ++ ++
++
++
++
++
++ ++
++
++
    ++
  • a
    • ++
  • b
    • ++
  • c
    • ++
  • d
    • ++
  • e
    • ++
  • f
    • ++
  • g
    • ++
  • h
    • ++
  • i
    • ++
  • l
    • ++
  • m
    • ++
  • n
    • ++
  • o
    • ++
  • p
    • ++
  • q
    • ++
  • r
    • ++
  • s
    • ++
  • t
    • ++
  • u
    • ++
  • v
    • ++
  • w
    • ++
  • x
    • ++
++
++ ++

++Here is a list of all documented struct and union fields with links to the struct/union documentation for each field: ++

++

- l -

++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/functions_0x6d.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/functions_0x6d.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,79 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields ++ ++ ++ ++ ++
++
++
++
++
++ ++
++
++
    ++
  • a
    • ++
  • b
    • ++
  • c
    • ++
  • d
    • ++
  • e
    • ++
  • f
    • ++
  • g
    • ++
  • h
    • ++
  • i
    • ++
  • l
    • ++
  • m
    • ++
  • n
    • ++
  • o
    • ++
  • p
    • ++
  • q
    • ++
  • r
    • ++
  • s
    • ++
  • t
    • ++
  • u
    • ++
  • v
    • ++
  • w
    • ++
  • x
    • ++
++
++ ++

++Here is a list of all documented struct and union fields with links to the struct/union documentation for each field: ++

++

- m -

++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/functions_0x6e.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/functions_0x6e.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,99 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields ++ ++ ++ ++ ++
++
++
++
++
++ ++
++
++
    ++
  • a
    • ++
  • b
    • ++
  • c
    • ++
  • d
    • ++
  • e
    • ++
  • f
    • ++
  • g
    • ++
  • h
    • ++
  • i
    • ++
  • l
    • ++
  • m
    • ++
  • n
    • ++
  • o
    • ++
  • p
    • ++
  • q
    • ++
  • r
    • ++
  • s
    • ++
  • t
    • ++
  • u
    • ++
  • v
    • ++
  • w
    • ++
  • x
    • ++
++
++ ++

++Here is a list of all documented struct and union fields with links to the struct/union documentation for each field: ++

++

- n -

++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/functions_0x6f.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/functions_0x6f.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,101 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields ++ ++ ++ ++ ++
++
++
++
++
++ ++
++
++
    ++
  • a
    • ++
  • b
    • ++
  • c
    • ++
  • d
    • ++
  • e
    • ++
  • f
    • ++
  • g
    • ++
  • h
    • ++
  • i
    • ++
  • l
    • ++
  • m
    • ++
  • n
    • ++
  • o
    • ++
  • p
    • ++
  • q
    • ++
  • r
    • ++
  • s
    • ++
  • t
    • ++
  • u
    • ++
  • v
    • ++
  • w
    • ++
  • x
    • ++
++
++ ++

++Here is a list of all documented struct and union fields with links to the struct/union documentation for each field: ++

++

- o -

++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/functions_0x70.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/functions_0x70.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,144 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields ++ ++ ++ ++ ++
++
++
++
++
++ ++
++
++
    ++
  • a
    • ++
  • b
    • ++
  • c
    • ++
  • d
    • ++
  • e
    • ++
  • f
    • ++
  • g
    • ++
  • h
    • ++
  • i
    • ++
  • l
    • ++
  • m
    • ++
  • n
    • ++
  • o
    • ++
  • p
    • ++
  • q
    • ++
  • r
    • ++
  • s
    • ++
  • t
    • ++
  • u
    • ++
  • v
    • ++
  • w
    • ++
  • x
    • ++
++
++ ++

++Here is a list of all documented struct and union fields with links to the struct/union documentation for each field: ++

++

- p -

++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/functions_0x71.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/functions_0x71.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,71 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields ++ ++ ++ ++ ++
++
++
++
++
++ ++
++
++
    ++
  • a
    • ++
  • b
    • ++
  • c
    • ++
  • d
    • ++
  • e
    • ++
  • f
    • ++
  • g
    • ++
  • h
    • ++
  • i
    • ++
  • l
    • ++
  • m
    • ++
  • n
    • ++
  • o
    • ++
  • p
    • ++
  • q
    • ++
  • r
    • ++
  • s
    • ++
  • t
    • ++
  • u
    • ++
  • v
    • ++
  • w
    • ++
  • x
    • ++
++
++ ++

++Here is a list of all documented struct and union fields with links to the struct/union documentation for each field: ++

++

- q -

++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/functions_0x72.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/functions_0x72.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,141 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields ++ ++ ++ ++ ++
++
++
++
++
++ ++
++
++
    ++
  • a
    • ++
  • b
    • ++
  • c
    • ++
  • d
    • ++
  • e
    • ++
  • f
    • ++
  • g
    • ++
  • h
    • ++
  • i
    • ++
  • l
    • ++
  • m
    • ++
  • n
    • ++
  • o
    • ++
  • p
    • ++
  • q
    • ++
  • r
    • ++
  • s
    • ++
  • t
    • ++
  • u
    • ++
  • v
    • ++
  • w
    • ++
  • x
    • ++
++
++ ++

++Here is a list of all documented struct and union fields with links to the struct/union documentation for each field: ++

++

- r -

++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/functions_0x73.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/functions_0x73.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,128 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields ++ ++ ++ ++ ++
++
++
++
++
++ ++
++
++
    ++
  • a
    • ++
  • b
    • ++
  • c
    • ++
  • d
    • ++
  • e
    • ++
  • f
    • ++
  • g
    • ++
  • h
    • ++
  • i
    • ++
  • l
    • ++
  • m
    • ++
  • n
    • ++
  • o
    • ++
  • p
    • ++
  • q
    • ++
  • r
    • ++
  • s
    • ++
  • t
    • ++
  • u
    • ++
  • v
    • ++
  • w
    • ++
  • x
    • ++
++
++ ++

++Here is a list of all documented struct and union fields with links to the struct/union documentation for each field: ++

++

- s -

++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/functions_0x74.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/functions_0x74.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,88 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields ++ ++ ++ ++ ++
++
++
++
++
++ ++
++
++
    ++
  • a
    • ++
  • b
    • ++
  • c
    • ++
  • d
    • ++
  • e
    • ++
  • f
    • ++
  • g
    • ++
  • h
    • ++
  • i
    • ++
  • l
    • ++
  • m
    • ++
  • n
    • ++
  • o
    • ++
  • p
    • ++
  • q
    • ++
  • r
    • ++
  • s
    • ++
  • t
    • ++
  • u
    • ++
  • v
    • ++
  • w
    • ++
  • x
    • ++
++
++ ++

++Here is a list of all documented struct and union fields with links to the struct/union documentation for each field: ++

++

- t -

++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/functions_0x75.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/functions_0x75.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,78 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields ++ ++ ++ ++ ++
++
++
++
++
++ ++
++
++
    ++
  • a
    • ++
  • b
    • ++
  • c
    • ++
  • d
    • ++
  • e
    • ++
  • f
    • ++
  • g
    • ++
  • h
    • ++
  • i
    • ++
  • l
    • ++
  • m
    • ++
  • n
    • ++
  • o
    • ++
  • p
    • ++
  • q
    • ++
  • r
    • ++
  • s
    • ++
  • t
    • ++
  • u
    • ++
  • v
    • ++
  • w
    • ++
  • x
    • ++
++
++ ++

++Here is a list of all documented struct and union fields with links to the struct/union documentation for each field: ++

++

- u -

++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/functions_0x76.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/functions_0x76.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,65 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields ++ ++ ++ ++ ++
++
++
++
++
++ ++
++
++
    ++
  • a
    • ++
  • b
    • ++
  • c
    • ++
  • d
    • ++
  • e
    • ++
  • f
    • ++
  • g
    • ++
  • h
    • ++
  • i
    • ++
  • l
    • ++
  • m
    • ++
  • n
    • ++
  • o
    • ++
  • p
    • ++
  • q
    • ++
  • r
    • ++
  • s
    • ++
  • t
    • ++
  • u
    • ++
  • v
    • ++
  • w
    • ++
  • x
    • ++
++
++ ++

++Here is a list of all documented struct and union fields with links to the struct/union documentation for each field: ++

++

- v -

++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/functions_0x77.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/functions_0x77.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,79 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields ++ ++ ++ ++ ++
++
++
++
++
++ ++
++
++
    ++
  • a
    • ++
  • b
    • ++
  • c
    • ++
  • d
    • ++
  • e
    • ++
  • f
    • ++
  • g
    • ++
  • h
    • ++
  • i
    • ++
  • l
    • ++
  • m
    • ++
  • n
    • ++
  • o
    • ++
  • p
    • ++
  • q
    • ++
  • r
    • ++
  • s
    • ++
  • t
    • ++
  • u
    • ++
  • v
    • ++
  • w
    • ++
  • x
    • ++
++
++ ++

++Here is a list of all documented struct and union fields with links to the struct/union documentation for each field: ++

++

- w -

++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/functions_0x78.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/functions_0x78.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,77 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields ++ ++ ++ ++ ++
++
++
++
++
++ ++
++
++
    ++
  • a
    • ++
  • b
    • ++
  • c
    • ++
  • d
    • ++
  • e
    • ++
  • f
    • ++
  • g
    • ++
  • h
    • ++
  • i
    • ++
  • l
    • ++
  • m
    • ++
  • n
    • ++
  • o
    • ++
  • p
    • ++
  • q
    • ++
  • r
    • ++
  • s
    • ++
  • t
    • ++
  • u
    • ++
  • v
    • ++
  • w
    • ++
  • x
    • ++
++
++ ++

++Here is a list of all documented struct and union fields with links to the struct/union documentation for each field: ++

++

- x -

++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/functions_func.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/functions_func.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,36 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields - Functions ++ ++ ++ ++ ++
++
++
++
++
++ ++
++  ++

++

++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/functions_vars.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/functions_vars.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,82 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields - Variables ++ ++ ++ ++ ++
++
++
++
++
++ ++
++
++
    ++
  • a
    • ++
  • b
    • ++
  • c
    • ++
  • d
    • ++
  • e
    • ++
  • f
    • ++
  • g
    • ++
  • h
    • ++
  • i
    • ++
  • l
    • ++
  • m
    • ++
  • n
    • ++
  • o
    • ++
  • p
    • ++
  • q
    • ++
  • r
    • ++
  • s
    • ++
  • t
    • ++
  • u
    • ++
  • v
    • ++
  • w
    • ++
  • x
    • ++
++
++ ++

++  ++

++

- a -

++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x62.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x62.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,99 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields - Variables ++ ++ ++ ++ ++
++
++
++
++
++ ++
++
++
    ++
  • a
    • ++
  • b
    • ++
  • c
    • ++
  • d
    • ++
  • e
    • ++
  • f
    • ++
  • g
    • ++
  • h
    • ++
  • i
    • ++
  • l
    • ++
  • m
    • ++
  • n
    • ++
  • o
    • ++
  • p
    • ++
  • q
    • ++
  • r
    • ++
  • s
    • ++
  • t
    • ++
  • u
    • ++
  • v
    • ++
  • w
    • ++
  • x
    • ++
++
++ ++

++  ++

++

- b -

++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x63.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x63.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,110 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields - Variables ++ ++ ++ ++ ++
++
++
++
++
++ ++
++
++
    ++
  • a
    • ++
  • b
    • ++
  • c
    • ++
  • d
    • ++
  • e
    • ++
  • f
    • ++
  • g
    • ++
  • h
    • ++
  • i
    • ++
  • l
    • ++
  • m
    • ++
  • n
    • ++
  • o
    • ++
  • p
    • ++
  • q
    • ++
  • r
    • ++
  • s
    • ++
  • t
    • ++
  • u
    • ++
  • v
    • ++
  • w
    • ++
  • x
    • ++
++
++ ++

++  ++

++

- c -

++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x64.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x64.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,157 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields - Variables ++ ++ ++ ++ ++
++
++
++
++
++ ++
++
++
    ++
  • a
    • ++
  • b
    • ++
  • c
    • ++
  • d
    • ++
  • e
    • ++
  • f
    • ++
  • g
    • ++
  • h
    • ++
  • i
    • ++
  • l
    • ++
  • m
    • ++
  • n
    • ++
  • o
    • ++
  • p
    • ++
  • q
    • ++
  • r
    • ++
  • s
    • ++
  • t
    • ++
  • u
    • ++
  • v
    • ++
  • w
    • ++
  • x
    • ++
++
++ ++

++  ++

++

- d -

++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x65.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x65.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,109 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields - Variables ++ ++ ++ ++ ++
++
++
++
++
++ ++
++
++
    ++
  • a
    • ++
  • b
    • ++
  • c
    • ++
  • d
    • ++
  • e
    • ++
  • f
    • ++
  • g
    • ++
  • h
    • ++
  • i
    • ++
  • l
    • ++
  • m
    • ++
  • n
    • ++
  • o
    • ++
  • p
    • ++
  • q
    • ++
  • r
    • ++
  • s
    • ++
  • t
    • ++
  • u
    • ++
  • v
    • ++
  • w
    • ++
  • x
    • ++
++
++ ++

++  ++

++

- e -

++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x66.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x66.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,81 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields - Variables ++ ++ ++ ++ ++
++
++
++
++
++ ++
++
++
    ++
  • a
    • ++
  • b
    • ++
  • c
    • ++
  • d
    • ++
  • e
    • ++
  • f
    • ++
  • g
    • ++
  • h
    • ++
  • i
    • ++
  • l
    • ++
  • m
    • ++
  • n
    • ++
  • o
    • ++
  • p
    • ++
  • q
    • ++
  • r
    • ++
  • s
    • ++
  • t
    • ++
  • u
    • ++
  • v
    • ++
  • w
    • ++
  • x
    • ++
++
++ ++

++  ++

++

- f -

++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x67.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x67.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,95 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields - Variables ++ ++ ++ ++ ++
++
++
++
++
++ ++
++
++
    ++
  • a
    • ++
  • b
    • ++
  • c
    • ++
  • d
    • ++
  • e
    • ++
  • f
    • ++
  • g
    • ++
  • h
    • ++
  • i
    • ++
  • l
    • ++
  • m
    • ++
  • n
    • ++
  • o
    • ++
  • p
    • ++
  • q
    • ++
  • r
    • ++
  • s
    • ++
  • t
    • ++
  • u
    • ++
  • v
    • ++
  • w
    • ++
  • x
    • ++
++
++ ++

++  ++

++

- g -

++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x68.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x68.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,119 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields - Variables ++ ++ ++ ++ ++
++
++
++
++
++ ++
++
++
    ++
  • a
    • ++
  • b
    • ++
  • c
    • ++
  • d
    • ++
  • e
    • ++
  • f
    • ++
  • g
    • ++
  • h
    • ++
  • i
    • ++
  • l
    • ++
  • m
    • ++
  • n
    • ++
  • o
    • ++
  • p
    • ++
  • q
    • ++
  • r
    • ++
  • s
    • ++
  • t
    • ++
  • u
    • ++
  • v
    • ++
  • w
    • ++
  • x
    • ++
++
++ ++

++  ++

++

- h -

++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x69.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x69.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,121 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields - Variables ++ ++ ++ ++ ++
++
++
++
++
++ ++
++
++
    ++
  • a
    • ++
  • b
    • ++
  • c
    • ++
  • d
    • ++
  • e
    • ++
  • f
    • ++
  • g
    • ++
  • h
    • ++
  • i
    • ++
  • l
    • ++
  • m
    • ++
  • n
    • ++
  • o
    • ++
  • p
    • ++
  • q
    • ++
  • r
    • ++
  • s
    • ++
  • t
    • ++
  • u
    • ++
  • v
    • ++
  • w
    • ++
  • x
    • ++
++
++ ++

++  ++

++

- i -

++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x6c.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x6c.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,74 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields - Variables ++ ++ ++ ++ ++
++
++
++
++
++ ++
++
++
    ++
  • a
    • ++
  • b
    • ++
  • c
    • ++
  • d
    • ++
  • e
    • ++
  • f
    • ++
  • g
    • ++
  • h
    • ++
  • i
    • ++
  • l
    • ++
  • m
    • ++
  • n
    • ++
  • o
    • ++
  • p
    • ++
  • q
    • ++
  • r
    • ++
  • s
    • ++
  • t
    • ++
  • u
    • ++
  • v
    • ++
  • w
    • ++
  • x
    • ++
++
++ ++

++  ++

++

- l -

++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x6d.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x6d.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,79 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields - Variables ++ ++ ++ ++ ++
++
++
++
++
++ ++
++
++
    ++
  • a
    • ++
  • b
    • ++
  • c
    • ++
  • d
    • ++
  • e
    • ++
  • f
    • ++
  • g
    • ++
  • h
    • ++
  • i
    • ++
  • l
    • ++
  • m
    • ++
  • n
    • ++
  • o
    • ++
  • p
    • ++
  • q
    • ++
  • r
    • ++
  • s
    • ++
  • t
    • ++
  • u
    • ++
  • v
    • ++
  • w
    • ++
  • x
    • ++
++
++ ++

++  ++

++

- m -

++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x6e.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x6e.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,99 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields - Variables ++ ++ ++ ++ ++
++
++
++
++
++ ++
++
++
    ++
  • a
    • ++
  • b
    • ++
  • c
    • ++
  • d
    • ++
  • e
    • ++
  • f
    • ++
  • g
    • ++
  • h
    • ++
  • i
    • ++
  • l
    • ++
  • m
    • ++
  • n
    • ++
  • o
    • ++
  • p
    • ++
  • q
    • ++
  • r
    • ++
  • s
    • ++
  • t
    • ++
  • u
    • ++
  • v
    • ++
  • w
    • ++
  • x
    • ++
++
++ ++

++  ++

++

- n -

++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x6f.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x6f.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,101 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields - Variables ++ ++ ++ ++ ++
++
++
++
++
++ ++
++
++
    ++
  • a
    • ++
  • b
    • ++
  • c
    • ++
  • d
    • ++
  • e
    • ++
  • f
    • ++
  • g
    • ++
  • h
    • ++
  • i
    • ++
  • l
    • ++
  • m
    • ++
  • n
    • ++
  • o
    • ++
  • p
    • ++
  • q
    • ++
  • r
    • ++
  • s
    • ++
  • t
    • ++
  • u
    • ++
  • v
    • ++
  • w
    • ++
  • x
    • ++
++
++ ++

++  ++

++

- o -

++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x70.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x70.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,144 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields - Variables ++ ++ ++ ++ ++
++
++
++
++
++ ++
++
++
    ++
  • a
    • ++
  • b
    • ++
  • c
    • ++
  • d
    • ++
  • e
    • ++
  • f
    • ++
  • g
    • ++
  • h
    • ++
  • i
    • ++
  • l
    • ++
  • m
    • ++
  • n
    • ++
  • o
    • ++
  • p
    • ++
  • q
    • ++
  • r
    • ++
  • s
    • ++
  • t
    • ++
  • u
    • ++
  • v
    • ++
  • w
    • ++
  • x
    • ++
++
++ ++

++  ++

++

- p -

++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x71.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x71.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,71 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields - Variables ++ ++ ++ ++ ++
++
++
++
++
++ ++
++
++
    ++
  • a
    • ++
  • b
    • ++
  • c
    • ++
  • d
    • ++
  • e
    • ++
  • f
    • ++
  • g
    • ++
  • h
    • ++
  • i
    • ++
  • l
    • ++
  • m
    • ++
  • n
    • ++
  • o
    • ++
  • p
    • ++
  • q
    • ++
  • r
    • ++
  • s
    • ++
  • t
    • ++
  • u
    • ++
  • v
    • ++
  • w
    • ++
  • x
    • ++
++
++ ++

++  ++

++

- q -

++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x72.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x72.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,141 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields - Variables ++ ++ ++ ++ ++
++
++
++
++
++ ++
++
++
    ++
  • a
    • ++
  • b
    • ++
  • c
    • ++
  • d
    • ++
  • e
    • ++
  • f
    • ++
  • g
    • ++
  • h
    • ++
  • i
    • ++
  • l
    • ++
  • m
    • ++
  • n
    • ++
  • o
    • ++
  • p
    • ++
  • q
    • ++
  • r
    • ++
  • s
    • ++
  • t
    • ++
  • u
    • ++
  • v
    • ++
  • w
    • ++
  • x
    • ++
++
++ ++

++  ++

++

- r -

++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x73.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x73.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,128 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields - Variables ++ ++ ++ ++ ++
++
++
++
++
++ ++
++
++
    ++
  • a
    • ++
  • b
    • ++
  • c
    • ++
  • d
    • ++
  • e
    • ++
  • f
    • ++
  • g
    • ++
  • h
    • ++
  • i
    • ++
  • l
    • ++
  • m
    • ++
  • n
    • ++
  • o
    • ++
  • p
    • ++
  • q
    • ++
  • r
    • ++
  • s
    • ++
  • t
    • ++
  • u
    • ++
  • v
    • ++
  • w
    • ++
  • x
    • ++
++
++ ++

++  ++

++

- s -

++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x74.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x74.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,88 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields - Variables ++ ++ ++ ++ ++
++
++
++
++
++ ++
++
++
    ++
  • a
    • ++
  • b
    • ++
  • c
    • ++
  • d
    • ++
  • e
    • ++
  • f
    • ++
  • g
    • ++
  • h
    • ++
  • i
    • ++
  • l
    • ++
  • m
    • ++
  • n
    • ++
  • o
    • ++
  • p
    • ++
  • q
    • ++
  • r
    • ++
  • s
    • ++
  • t
    • ++
  • u
    • ++
  • v
    • ++
  • w
    • ++
  • x
    • ++
++
++ ++

++  ++

++

- t -

++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x75.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x75.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,78 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields - Variables ++ ++ ++ ++ ++
++
++
++
++
++ ++
++
++
    ++
  • a
    • ++
  • b
    • ++
  • c
    • ++
  • d
    • ++
  • e
    • ++
  • f
    • ++
  • g
    • ++
  • h
    • ++
  • i
    • ++
  • l
    • ++
  • m
    • ++
  • n
    • ++
  • o
    • ++
  • p
    • ++
  • q
    • ++
  • r
    • ++
  • s
    • ++
  • t
    • ++
  • u
    • ++
  • v
    • ++
  • w
    • ++
  • x
    • ++
++
++ ++

++  ++

++

- u -

++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x76.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x76.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,65 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields - Variables ++ ++ ++ ++ ++
++
++
++
++
++ ++
++
++
    ++
  • a
    • ++
  • b
    • ++
  • c
    • ++
  • d
    • ++
  • e
    • ++
  • f
    • ++
  • g
    • ++
  • h
    • ++
  • i
    • ++
  • l
    • ++
  • m
    • ++
  • n
    • ++
  • o
    • ++
  • p
    • ++
  • q
    • ++
  • r
    • ++
  • s
    • ++
  • t
    • ++
  • u
    • ++
  • v
    • ++
  • w
    • ++
  • x
    • ++
++
++ ++

++  ++

++

- v -

++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x77.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x77.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,79 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields - Variables ++ ++ ++ ++ ++
++
++
++
++
++ ++
++
++
    ++
  • a
    • ++
  • b
    • ++
  • c
    • ++
  • d
    • ++
  • e
    • ++
  • f
    • ++
  • g
    • ++
  • h
    • ++
  • i
    • ++
  • l
    • ++
  • m
    • ++
  • n
    • ++
  • o
    • ++
  • p
    • ++
  • q
    • ++
  • r
    • ++
  • s
    • ++
  • t
    • ++
  • u
    • ++
  • v
    • ++
  • w
    • ++
  • x
    • ++
++
++ ++

++  ++

++

- w -

++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x78.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x78.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,77 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields - Variables ++ ++ ++ ++ ++
++
++
++
++
++ ++
++
++
    ++
  • a
    • ++
  • b
    • ++
  • c
    • ++
  • d
    • ++
  • e
    • ++
  • f
    • ++
  • g
    • ++
  • h
    • ++
  • i
    • ++
  • l
    • ++
  • m
    • ++
  • n
    • ++
  • o
    • ++
  • p
    • ++
  • q
    • ++
  • r
    • ++
  • s
    • ++
  • t
    • ++
  • u
    • ++
  • v
    • ++
  • w
    • ++
  • x
    • ++
++
++ ++

++  ++

++

- x -

++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,87 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields ++ ++ ++ ++ ++
++
++
++
++
++ ++
++
++
    ++
  • _
    • ++
  • a
    • ++
  • b
    • ++
  • c
    • ++
  • d
    • ++
  • e
    • ++
  • f
    • ++
  • g
    • ++
  • h
    • ++
  • i
    • ++
  • k
    • ++
  • m
    • ++
  • n
    • ++
  • o
    • ++
  • p
    • ++
  • q
    • ++
  • r
    • ++
  • s
    • ++
  • t
    • ++
  • u
    • ++
  • v
    • ++
  • w
    • ++
++
++ ++

++Here is a list of all documented functions, variables, defines, enums, and typedefs with links to the documentation: ++

++

- _ -

++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_0x61.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_0x61.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,76 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields ++ ++ ++ ++ ++
++
++
++
++
++ ++
++
++
    ++
  • _
    • ++
  • a
    • ++
  • b
    • ++
  • c
    • ++
  • d
    • ++
  • e
    • ++
  • f
    • ++
  • g
    • ++
  • h
    • ++
  • i
    • ++
  • k
    • ++
  • m
    • ++
  • n
    • ++
  • o
    • ++
  • p
    • ++
  • q
    • ++
  • r
    • ++
  • s
    • ++
  • t
    • ++
  • u
    • ++
  • v
    • ++
  • w
    • ++
++
++ ++

++Here is a list of all documented functions, variables, defines, enums, and typedefs with links to the documentation: ++

++

- a -

++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_0x62.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_0x62.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,83 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields ++ ++ ++ ++ ++
++
++
++
++
++ ++
++
++
    ++
  • _
    • ++
  • a
    • ++
  • b
    • ++
  • c
    • ++
  • d
    • ++
  • e
    • ++
  • f
    • ++
  • g
    • ++
  • h
    • ++
  • i
    • ++
  • k
    • ++
  • m
    • ++
  • n
    • ++
  • o
    • ++
  • p
    • ++
  • q
    • ++
  • r
    • ++
  • s
    • ++
  • t
    • ++
  • u
    • ++
  • v
    • ++
  • w
    • ++
++
++ ++

++Here is a list of all documented functions, variables, defines, enums, and typedefs with links to the documentation: ++

++

- b -

++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_0x63.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_0x63.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,100 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields ++ ++ ++ ++ ++
++
++
++
++
++ ++
++
++
    ++
  • _
    • ++
  • a
    • ++
  • b
    • ++
  • c
    • ++
  • d
    • ++
  • e
    • ++
  • f
    • ++
  • g
    • ++
  • h
    • ++
  • i
    • ++
  • k
    • ++
  • m
    • ++
  • n
    • ++
  • o
    • ++
  • p
    • ++
  • q
    • ++
  • r
    • ++
  • s
    • ++
  • t
    • ++
  • u
    • ++
  • v
    • ++
  • w
    • ++
++
++ ++

++Here is a list of all documented functions, variables, defines, enums, and typedefs with links to the documentation: ++

++

- c -

++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_0x64.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_0x64.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,686 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields ++ ++ ++ ++ ++
++
++
++
++
++ ++
++
++
    ++
  • _
    • ++
  • a
    • ++
  • b
    • ++
  • c
    • ++
  • d
    • ++
  • e
    • ++
  • f
    • ++
  • g
    • ++
  • h
    • ++
  • i
    • ++
  • k
    • ++
  • m
    • ++
  • n
    • ++
  • o
    • ++
  • p
    • ++
  • q
    • ++
  • r
    • ++
  • s
    • ++
  • t
    • ++
  • u
    • ++
  • v
    • ++
  • w
    • ++
++
++ ++

++Here is a list of all documented functions, variables, defines, enums, and typedefs with links to the documentation: ++

++

- d -

++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_0x65.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_0x65.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,78 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields ++ ++ ++ ++ ++
++
++
++
++
++ ++
++
++
    ++
  • _
    • ++
  • a
    • ++
  • b
    • ++
  • c
    • ++
  • d
    • ++
  • e
    • ++
  • f
    • ++
  • g
    • ++
  • h
    • ++
  • i
    • ++
  • k
    • ++
  • m
    • ++
  • n
    • ++
  • o
    • ++
  • p
    • ++
  • q
    • ++
  • r
    • ++
  • s
    • ++
  • t
    • ++
  • u
    • ++
  • v
    • ++
  • w
    • ++
++
++ ++

++Here is a list of all documented functions, variables, defines, enums, and typedefs with links to the documentation: ++

++

- e -

++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_0x66.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_0x66.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,87 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields ++ ++ ++ ++ ++
++
++
++
++
++ ++
++
++
    ++
  • _
    • ++
  • a
    • ++
  • b
    • ++
  • c
    • ++
  • d
    • ++
  • e
    • ++
  • f
    • ++
  • g
    • ++
  • h
    • ++
  • i
    • ++
  • k
    • ++
  • m
    • ++
  • n
    • ++
  • o
    • ++
  • p
    • ++
  • q
    • ++
  • r
    • ++
  • s
    • ++
  • t
    • ++
  • u
    • ++
  • v
    • ++
  • w
    • ++
++
++ ++

++Here is a list of all documented functions, variables, defines, enums, and typedefs with links to the documentation: ++

++

- f -

++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_0x67.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_0x67.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,93 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields ++ ++ ++ ++ ++
++
++
++
++
++ ++
++
++
    ++
  • _
    • ++
  • a
    • ++
  • b
    • ++
  • c
    • ++
  • d
    • ++
  • e
    • ++
  • f
    • ++
  • g
    • ++
  • h
    • ++
  • i
    • ++
  • k
    • ++
  • m
    • ++
  • n
    • ++
  • o
    • ++
  • p
    • ++
  • q
    • ++
  • r
    • ++
  • s
    • ++
  • t
    • ++
  • u
    • ++
  • v
    • ++
  • w
    • ++
++
++ ++

++Here is a list of all documented functions, variables, defines, enums, and typedefs with links to the documentation: ++

++

- g -

++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_0x68.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_0x68.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,129 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields ++ ++ ++ ++ ++
++
++
++
++
++ ++
++
++
    ++
  • _
    • ++
  • a
    • ++
  • b
    • ++
  • c
    • ++
  • d
    • ++
  • e
    • ++
  • f
    • ++
  • g
    • ++
  • h
    • ++
  • i
    • ++
  • k
    • ++
  • m
    • ++
  • n
    • ++
  • o
    • ++
  • p
    • ++
  • q
    • ++
  • r
    • ++
  • s
    • ++
  • t
    • ++
  • u
    • ++
  • v
    • ++
  • w
    • ++
++
++ ++

++Here is a list of all documented functions, variables, defines, enums, and typedefs with links to the documentation: ++

++

- h -

++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_0x69.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_0x69.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,76 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields ++ ++ ++ ++ ++
++
++
++
++
++ ++
++
++
    ++
  • _
    • ++
  • a
    • ++
  • b
    • ++
  • c
    • ++
  • d
    • ++
  • e
    • ++
  • f
    • ++
  • g
    • ++
  • h
    • ++
  • i
    • ++
  • k
    • ++
  • m
    • ++
  • n
    • ++
  • o
    • ++
  • p
    • ++
  • q
    • ++
  • r
    • ++
  • s
    • ++
  • t
    • ++
  • u
    • ++
  • v
    • ++
  • w
    • ++
++
++ ++

++Here is a list of all documented functions, variables, defines, enums, and typedefs with links to the documentation: ++

++

- i -

++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_0x6b.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_0x6b.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,69 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields ++ ++ ++ ++ ++
++
++
++
++
++ ++
++
++
    ++
  • _
    • ++
  • a
    • ++
  • b
    • ++
  • c
    • ++
  • d
    • ++
  • e
    • ++
  • f
    • ++
  • g
    • ++
  • h
    • ++
  • i
    • ++
  • k
    • ++
  • m
    • ++
  • n
    • ++
  • o
    • ++
  • p
    • ++
  • q
    • ++
  • r
    • ++
  • s
    • ++
  • t
    • ++
  • u
    • ++
  • v
    • ++
  • w
    • ++
++
++ ++

++Here is a list of all documented functions, variables, defines, enums, and typedefs with links to the documentation: ++

++

- k -

++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_0x6d.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_0x6d.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,84 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields ++ ++ ++ ++ ++
++
++
++
++
++ ++
++
++
    ++
  • _
    • ++
  • a
    • ++
  • b
    • ++
  • c
    • ++
  • d
    • ++
  • e
    • ++
  • f
    • ++
  • g
    • ++
  • h
    • ++
  • i
    • ++
  • k
    • ++
  • m
    • ++
  • n
    • ++
  • o
    • ++
  • p
    • ++
  • q
    • ++
  • r
    • ++
  • s
    • ++
  • t
    • ++
  • u
    • ++
  • v
    • ++
  • w
    • ++
++
++ ++

++Here is a list of all documented functions, variables, defines, enums, and typedefs with links to the documentation: ++

++

- m -

++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_0x6e.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_0x6e.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,68 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields ++ ++ ++ ++ ++
++
++
++
++
++ ++
++
++
    ++
  • _
    • ++
  • a
    • ++
  • b
    • ++
  • c
    • ++
  • d
    • ++
  • e
    • ++
  • f
    • ++
  • g
    • ++
  • h
    • ++
  • i
    • ++
  • k
    • ++
  • m
    • ++
  • n
    • ++
  • o
    • ++
  • p
    • ++
  • q
    • ++
  • r
    • ++
  • s
    • ++
  • t
    • ++
  • u
    • ++
  • v
    • ++
  • w
    • ++
++
++ ++

++Here is a list of all documented functions, variables, defines, enums, and typedefs with links to the documentation: ++

++

- n -

++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_0x6f.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_0x6f.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,73 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields ++ ++ ++ ++ ++
++
++
++
++
++ ++
++
++
    ++
  • _
    • ++
  • a
    • ++
  • b
    • ++
  • c
    • ++
  • d
    • ++
  • e
    • ++
  • f
    • ++
  • g
    • ++
  • h
    • ++
  • i
    • ++
  • k
    • ++
  • m
    • ++
  • n
    • ++
  • o
    • ++
  • p
    • ++
  • q
    • ++
  • r
    • ++
  • s
    • ++
  • t
    • ++
  • u
    • ++
  • v
    • ++
  • w
    • ++
++
++ ++

++Here is a list of all documented functions, variables, defines, enums, and typedefs with links to the documentation: ++

++

- o -

++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_0x70.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_0x70.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,84 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields ++ ++ ++ ++ ++
++
++
++
++
++ ++
++
++
    ++
  • _
    • ++
  • a
    • ++
  • b
    • ++
  • c
    • ++
  • d
    • ++
  • e
    • ++
  • f
    • ++
  • g
    • ++
  • h
    • ++
  • i
    • ++
  • k
    • ++
  • m
    • ++
  • n
    • ++
  • o
    • ++
  • p
    • ++
  • q
    • ++
  • r
    • ++
  • s
    • ++
  • t
    • ++
  • u
    • ++
  • v
    • ++
  • w
    • ++
++
++ ++

++Here is a list of all documented functions, variables, defines, enums, and typedefs with links to the documentation: ++

++

- p -

++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_0x71.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_0x71.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,70 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields ++ ++ ++ ++ ++
++
++
++
++
++ ++
++
++
    ++
  • _
    • ++
  • a
    • ++
  • b
    • ++
  • c
    • ++
  • d
    • ++
  • e
    • ++
  • f
    • ++
  • g
    • ++
  • h
    • ++
  • i
    • ++
  • k
    • ++
  • m
    • ++
  • n
    • ++
  • o
    • ++
  • p
    • ++
  • q
    • ++
  • r
    • ++
  • s
    • ++
  • t
    • ++
  • u
    • ++
  • v
    • ++
  • w
    • ++
++
++ ++

++Here is a list of all documented functions, variables, defines, enums, and typedefs with links to the documentation: ++

++

- q -

++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_0x72.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_0x72.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,94 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields ++ ++ ++ ++ ++
++
++
++
++
++ ++
++
++
    ++
  • _
    • ++
  • a
    • ++
  • b
    • ++
  • c
    • ++
  • d
    • ++
  • e
    • ++
  • f
    • ++
  • g
    • ++
  • h
    • ++
  • i
    • ++
  • k
    • ++
  • m
    • ++
  • n
    • ++
  • o
    • ++
  • p
    • ++
  • q
    • ++
  • r
    • ++
  • s
    • ++
  • t
    • ++
  • u
    • ++
  • v
    • ++
  • w
    • ++
++
++ ++

++Here is a list of all documented functions, variables, defines, enums, and typedefs with links to the documentation: ++

++

- r -

++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_0x73.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_0x73.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,85 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields ++ ++ ++ ++ ++
++
++
++
++
++ ++
++
++
    ++
  • _
    • ++
  • a
    • ++
  • b
    • ++
  • c
    • ++
  • d
    • ++
  • e
    • ++
  • f
    • ++
  • g
    • ++
  • h
    • ++
  • i
    • ++
  • k
    • ++
  • m
    • ++
  • n
    • ++
  • o
    • ++
  • p
    • ++
  • q
    • ++
  • r
    • ++
  • s
    • ++
  • t
    • ++
  • u
    • ++
  • v
    • ++
  • w
    • ++
++
++ ++

++Here is a list of all documented functions, variables, defines, enums, and typedefs with links to the documentation: ++

++

- s -

++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_0x74.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_0x74.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,68 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields ++ ++ ++ ++ ++
++
++
++
++
++ ++
++
++
    ++
  • _
    • ++
  • a
    • ++
  • b
    • ++
  • c
    • ++
  • d
    • ++
  • e
    • ++
  • f
    • ++
  • g
    • ++
  • h
    • ++
  • i
    • ++
  • k
    • ++
  • m
    • ++
  • n
    • ++
  • o
    • ++
  • p
    • ++
  • q
    • ++
  • r
    • ++
  • s
    • ++
  • t
    • ++
  • u
    • ++
  • v
    • ++
  • w
    • ++
++
++ ++

++Here is a list of all documented functions, variables, defines, enums, and typedefs with links to the documentation: ++

++

- t -

++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_0x75.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_0x75.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,80 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields ++ ++ ++ ++ ++
++
++
++
++
++ ++
++
++
    ++
  • _
    • ++
  • a
    • ++
  • b
    • ++
  • c
    • ++
  • d
    • ++
  • e
    • ++
  • f
    • ++
  • g
    • ++
  • h
    • ++
  • i
    • ++
  • k
    • ++
  • m
    • ++
  • n
    • ++
  • o
    • ++
  • p
    • ++
  • q
    • ++
  • r
    • ++
  • s
    • ++
  • t
    • ++
  • u
    • ++
  • v
    • ++
  • w
    • ++
++
++ ++

++Here is a list of all documented functions, variables, defines, enums, and typedefs with links to the documentation: ++

++

- u -

++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_0x76.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_0x76.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,75 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields ++ ++ ++ ++ ++
++
++
++
++
++ ++
++
++
    ++
  • _
    • ++
  • a
    • ++
  • b
    • ++
  • c
    • ++
  • d
    • ++
  • e
    • ++
  • f
    • ++
  • g
    • ++
  • h
    • ++
  • i
    • ++
  • k
    • ++
  • m
    • ++
  • n
    • ++
  • o
    • ++
  • p
    • ++
  • q
    • ++
  • r
    • ++
  • s
    • ++
  • t
    • ++
  • u
    • ++
  • v
    • ++
  • w
    • ++
++
++ ++

++Here is a list of all documented functions, variables, defines, enums, and typedefs with links to the documentation: ++

++

- v -

++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_0x77.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_0x77.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,74 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields ++ ++ ++ ++ ++
++
++
++
++
++ ++
++
++
    ++
  • _
    • ++
  • a
    • ++
  • b
    • ++
  • c
    • ++
  • d
    • ++
  • e
    • ++
  • f
    • ++
  • g
    • ++
  • h
    • ++
  • i
    • ++
  • k
    • ++
  • m
    • ++
  • n
    • ++
  • o
    • ++
  • p
    • ++
  • q
    • ++
  • r
    • ++
  • s
    • ++
  • t
    • ++
  • u
    • ++
  • v
    • ++
  • w
    • ++
++
++ ++

++Here is a list of all documented functions, variables, defines, enums, and typedefs with links to the documentation: ++

++

- w -

++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_defs.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_defs.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,68 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields ++ ++ ++ ++ ++
++
++
++
++
++ ++
++
++
    ++
  • _
    • ++
  • a
    • ++
  • b
    • ++
  • c
    • ++
  • d
    • ++
  • f
    • ++
  • g
    • ++
  • h
    • ++
  • i
    • ++
  • m
    • ++
  • n
    • ++
  • o
    • ++
  • r
    • ++
  • s
    • ++
  • u
    • ++
  • v
    • ++
++
++ ++

++  ++

++

- _ -

++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_defs_0x61.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_defs_0x61.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,64 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields ++ ++ ++ ++ ++
++
++
++
++
++ ++
++
++
    ++
  • _
    • ++
  • a
    • ++
  • b
    • ++
  • c
    • ++
  • d
    • ++
  • f
    • ++
  • g
    • ++
  • h
    • ++
  • i
    • ++
  • m
    • ++
  • n
    • ++
  • o
    • ++
  • r
    • ++
  • s
    • ++
  • u
    • ++
  • v
    • ++
++
++ ++

++  ++

++

- a -

++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_defs_0x62.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_defs_0x62.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,71 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields ++ ++ ++ ++ ++
++
++
++
++
++ ++
++
++
    ++
  • _
    • ++
  • a
    • ++
  • b
    • ++
  • c
    • ++
  • d
    • ++
  • f
    • ++
  • g
    • ++
  • h
    • ++
  • i
    • ++
  • m
    • ++
  • n
    • ++
  • o
    • ++
  • r
    • ++
  • s
    • ++
  • u
    • ++
  • v
    • ++
++
++ ++

++  ++

++

- b -

++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_defs_0x63.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_defs_0x63.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,74 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields ++ ++ ++ ++ ++
++
++
++
++
++ ++
++
++
    ++
  • _
    • ++
  • a
    • ++
  • b
    • ++
  • c
    • ++
  • d
    • ++
  • f
    • ++
  • g
    • ++
  • h
    • ++
  • i
    • ++
  • m
    • ++
  • n
    • ++
  • o
    • ++
  • r
    • ++
  • s
    • ++
  • u
    • ++
  • v
    • ++
++
++ ++

++  ++

++

- c -

++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_defs_0x64.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_defs_0x64.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,241 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields ++ ++ ++ ++ ++
++
++
++
++
++ ++
++
++
    ++
  • _
    • ++
  • a
    • ++
  • b
    • ++
  • c
    • ++
  • d
    • ++
  • f
    • ++
  • g
    • ++
  • h
    • ++
  • i
    • ++
  • m
    • ++
  • n
    • ++
  • o
    • ++
  • r
    • ++
  • s
    • ++
  • u
    • ++
  • v
    • ++
++
++ ++

++  ++

++

- d -

++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_defs_0x66.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_defs_0x66.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,71 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields ++ ++ ++ ++ ++
++
++
++
++
++ ++
++
++
    ++
  • _
    • ++
  • a
    • ++
  • b
    • ++
  • c
    • ++
  • d
    • ++
  • f
    • ++
  • g
    • ++
  • h
    • ++
  • i
    • ++
  • m
    • ++
  • n
    • ++
  • o
    • ++
  • r
    • ++
  • s
    • ++
  • u
    • ++
  • v
    • ++
++
++ ++

++  ++

++

- f -

++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_defs_0x67.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_defs_0x67.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,62 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields ++ ++ ++ ++ ++
++
++
++
++
++ ++
++
++
    ++
  • _
    • ++
  • a
    • ++
  • b
    • ++
  • c
    • ++
  • d
    • ++
  • f
    • ++
  • g
    • ++
  • h
    • ++
  • i
    • ++
  • m
    • ++
  • n
    • ++
  • o
    • ++
  • r
    • ++
  • s
    • ++
  • u
    • ++
  • v
    • ++
++
++ ++

++  ++

++

- g -

++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_defs_0x68.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_defs_0x68.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,63 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields ++ ++ ++ ++ ++
++
++
++
++
++ ++
++
++
    ++
  • _
    • ++
  • a
    • ++
  • b
    • ++
  • c
    • ++
  • d
    • ++
  • f
    • ++
  • g
    • ++
  • h
    • ++
  • i
    • ++
  • m
    • ++
  • n
    • ++
  • o
    • ++
  • r
    • ++
  • s
    • ++
  • u
    • ++
  • v
    • ++
++
++ ++

++  ++

++

- h -

++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_defs_0x69.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_defs_0x69.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,62 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields ++ ++ ++ ++ ++
++
++
++
++
++ ++
++
++
    ++
  • _
    • ++
  • a
    • ++
  • b
    • ++
  • c
    • ++
  • d
    • ++
  • f
    • ++
  • g
    • ++
  • h
    • ++
  • i
    • ++
  • m
    • ++
  • n
    • ++
  • o
    • ++
  • r
    • ++
  • s
    • ++
  • u
    • ++
  • v
    • ++
++
++ ++

++  ++

++

- i -

++
Generated on Tue May 5 02:22:50 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_defs_0x6d.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_defs_0x6d.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,76 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields ++ ++ ++ ++ ++
++
++
++
++
++ ++
++
++
    ++
  • _
    • ++
  • a
    • ++
  • b
    • ++
  • c
    • ++
  • d
    • ++
  • f
    • ++
  • g
    • ++
  • h
    • ++
  • i
    • ++
  • m
    • ++
  • n
    • ++
  • o
    • ++
  • r
    • ++
  • s
    • ++
  • u
    • ++
  • v
    • ++
++
++ ++

++  ++

++

- m -

++
Generated on Tue May 5 02:22:50 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_defs_0x6e.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_defs_0x6e.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,62 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields ++ ++ ++ ++ ++
++
++
++
++
++ ++
++
++
    ++
  • _
    • ++
  • a
    • ++
  • b
    • ++
  • c
    • ++
  • d
    • ++
  • f
    • ++
  • g
    • ++
  • h
    • ++
  • i
    • ++
  • m
    • ++
  • n
    • ++
  • o
    • ++
  • r
    • ++
  • s
    • ++
  • u
    • ++
  • v
    • ++
++
++ ++

++  ++

++

- n -

++
Generated on Tue May 5 02:22:50 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_defs_0x6f.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_defs_0x6f.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,67 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields ++ ++ ++ ++ ++
++
++
++
++
++ ++
++
++
    ++
  • _
    • ++
  • a
    • ++
  • b
    • ++
  • c
    • ++
  • d
    • ++
  • f
    • ++
  • g
    • ++
  • h
    • ++
  • i
    • ++
  • m
    • ++
  • n
    • ++
  • o
    • ++
  • r
    • ++
  • s
    • ++
  • u
    • ++
  • v
    • ++
++
++ ++

++  ++

++

- o -

++
Generated on Tue May 5 02:22:50 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_defs_0x72.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_defs_0x72.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,66 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields ++ ++ ++ ++ ++
++
++
++
++
++ ++
++
++
    ++
  • _
    • ++
  • a
    • ++
  • b
    • ++
  • c
    • ++
  • d
    • ++
  • f
    • ++
  • g
    • ++
  • h
    • ++
  • i
    • ++
  • m
    • ++
  • n
    • ++
  • o
    • ++
  • r
    • ++
  • s
    • ++
  • u
    • ++
  • v
    • ++
++
++ ++

++  ++

++

- r -

++
Generated on Tue May 5 02:22:50 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_defs_0x73.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_defs_0x73.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,63 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields ++ ++ ++ ++ ++
++
++
++
++
++ ++
++
++
    ++
  • _
    • ++
  • a
    • ++
  • b
    • ++
  • c
    • ++
  • d
    • ++
  • f
    • ++
  • g
    • ++
  • h
    • ++
  • i
    • ++
  • m
    • ++
  • n
    • ++
  • o
    • ++
  • r
    • ++
  • s
    • ++
  • u
    • ++
  • v
    • ++
++
++ ++

++  ++

++

- s -

++
Generated on Tue May 5 02:22:50 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_defs_0x75.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_defs_0x75.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,64 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields ++ ++ ++ ++ ++
++
++
++
++
++ ++
++
++
    ++
  • _
    • ++
  • a
    • ++
  • b
    • ++
  • c
    • ++
  • d
    • ++
  • f
    • ++
  • g
    • ++
  • h
    • ++
  • i
    • ++
  • m
    • ++
  • n
    • ++
  • o
    • ++
  • r
    • ++
  • s
    • ++
  • u
    • ++
  • v
    • ++
++
++ ++

++  ++

++

- u -

++
Generated on Tue May 5 02:22:50 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_defs_0x76.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_defs_0x76.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,68 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields ++ ++ ++ ++ ++
++
++
++
++
++ ++
++
++
    ++
  • _
    • ++
  • a
    • ++
  • b
    • ++
  • c
    • ++
  • d
    • ++
  • f
    • ++
  • g
    • ++
  • h
    • ++
  • i
    • ++
  • m
    • ++
  • n
    • ++
  • o
    • ++
  • r
    • ++
  • s
    • ++
  • u
    • ++
  • v
    • ++
++
++ ++

++  ++

++

- v -

++
Generated on Tue May 5 02:22:50 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_enum.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_enum.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,44 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields ++ ++ ++ ++ ++
++
++
++
++
++ ++
++  ++

++

++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_eval.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_eval.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,43 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields ++ ++ ++ ++ ++
++
++
++
++
++ ++
++  ++

++

++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_func.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_func.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,77 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields ++ ++ ++ ++ ++
++
++
++
++
++ ++
++
++
    ++
  • _
    • ++
  • a
    • ++
  • b
    • ++
  • c
    • ++
  • d
    • ++
  • e
    • ++
  • f
    • ++
  • g
    • ++
  • h
    • ++
  • i
    • ++
  • k
    • ++
  • m
    • ++
  • p
    • ++
  • q
    • ++
  • r
    • ++
  • s
    • ++
  • u
    • ++
  • v
    • ++
  • w
    • ++
++
++ ++

++  ++

++

- _ -

++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_func_0x61.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_func_0x61.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,70 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields ++ ++ ++ ++ ++
++
++
++
++
++ ++
++
++
    ++
  • _
    • ++
  • a
    • ++
  • b
    • ++
  • c
    • ++
  • d
    • ++
  • e
    • ++
  • f
    • ++
  • g
    • ++
  • h
    • ++
  • i
    • ++
  • k
    • ++
  • m
    • ++
  • p
    • ++
  • q
    • ++
  • r
    • ++
  • s
    • ++
  • u
    • ++
  • v
    • ++
  • w
    • ++
++
++ ++

++  ++

++

- a -

++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_func_0x62.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_func_0x62.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,68 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields ++ ++ ++ ++ ++
++
++
++
++
++ ++
++
++
    ++
  • _
    • ++
  • a
    • ++
  • b
    • ++
  • c
    • ++
  • d
    • ++
  • e
    • ++
  • f
    • ++
  • g
    • ++
  • h
    • ++
  • i
    • ++
  • k
    • ++
  • m
    • ++
  • p
    • ++
  • q
    • ++
  • r
    • ++
  • s
    • ++
  • u
    • ++
  • v
    • ++
  • w
    • ++
++
++ ++

++  ++

++

- b -

++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_func_0x63.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_func_0x63.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,77 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields ++ ++ ++ ++ ++
++
++
++
++
++ ++
++
++
    ++
  • _
    • ++
  • a
    • ++
  • b
    • ++
  • c
    • ++
  • d
    • ++
  • e
    • ++
  • f
    • ++
  • g
    • ++
  • h
    • ++
  • i
    • ++
  • k
    • ++
  • m
    • ++
  • p
    • ++
  • q
    • ++
  • r
    • ++
  • s
    • ++
  • u
    • ++
  • v
    • ++
  • w
    • ++
++
++ ++

++  ++

++

- c -

++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_func_0x64.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_func_0x64.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,427 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields ++ ++ ++ ++ ++
++
++
++
++
++ ++
++
++
    ++
  • _
    • ++
  • a
    • ++
  • b
    • ++
  • c
    • ++
  • d
    • ++
  • e
    • ++
  • f
    • ++
  • g
    • ++
  • h
    • ++
  • i
    • ++
  • k
    • ++
  • m
    • ++
  • p
    • ++
  • q
    • ++
  • r
    • ++
  • s
    • ++
  • u
    • ++
  • v
    • ++
  • w
    • ++
++
++ ++

++  ++

++

- d -

++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_func_0x65.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_func_0x65.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,73 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields ++ ++ ++ ++ ++
++
++
++
++
++ ++
++
++
    ++
  • _
    • ++
  • a
    • ++
  • b
    • ++
  • c
    • ++
  • d
    • ++
  • e
    • ++
  • f
    • ++
  • g
    • ++
  • h
    • ++
  • i
    • ++
  • k
    • ++
  • m
    • ++
  • p
    • ++
  • q
    • ++
  • r
    • ++
  • s
    • ++
  • u
    • ++
  • v
    • ++
  • w
    • ++
++
++ ++

++  ++

++

- e -

++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_func_0x66.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_func_0x66.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,72 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields ++ ++ ++ ++ ++
++
++
++
++
++ ++
++
++
    ++
  • _
    • ++
  • a
    • ++
  • b
    • ++
  • c
    • ++
  • d
    • ++
  • e
    • ++
  • f
    • ++
  • g
    • ++
  • h
    • ++
  • i
    • ++
  • k
    • ++
  • m
    • ++
  • p
    • ++
  • q
    • ++
  • r
    • ++
  • s
    • ++
  • u
    • ++
  • v
    • ++
  • w
    • ++
++
++ ++

++  ++

++

- f -

++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_func_0x67.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_func_0x67.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,78 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields ++ ++ ++ ++ ++
++
++
++
++
++ ++
++
++
    ++
  • _
    • ++
  • a
    • ++
  • b
    • ++
  • c
    • ++
  • d
    • ++
  • e
    • ++
  • f
    • ++
  • g
    • ++
  • h
    • ++
  • i
    • ++
  • k
    • ++
  • m
    • ++
  • p
    • ++
  • q
    • ++
  • r
    • ++
  • s
    • ++
  • u
    • ++
  • v
    • ++
  • w
    • ++
++
++ ++

++  ++

++

- g -

++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_func_0x68.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_func_0x68.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,101 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields ++ ++ ++ ++ ++
++
++
++
++
++ ++
++
++
    ++
  • _
    • ++
  • a
    • ++
  • b
    • ++
  • c
    • ++
  • d
    • ++
  • e
    • ++
  • f
    • ++
  • g
    • ++
  • h
    • ++
  • i
    • ++
  • k
    • ++
  • m
    • ++
  • p
    • ++
  • q
    • ++
  • r
    • ++
  • s
    • ++
  • u
    • ++
  • v
    • ++
  • w
    • ++
++
++ ++

++  ++

++

- h -

++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_func_0x69.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_func_0x69.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,71 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields ++ ++ ++ ++ ++
++
++
++
++
++ ++
++
++
    ++
  • _
    • ++
  • a
    • ++
  • b
    • ++
  • c
    • ++
  • d
    • ++
  • e
    • ++
  • f
    • ++
  • g
    • ++
  • h
    • ++
  • i
    • ++
  • k
    • ++
  • m
    • ++
  • p
    • ++
  • q
    • ++
  • r
    • ++
  • s
    • ++
  • u
    • ++
  • v
    • ++
  • w
    • ++
++
++ ++

++  ++

++

- i -

++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_func_0x6b.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_func_0x6b.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,66 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields ++ ++ ++ ++ ++
++
++
++
++
++ ++
++
++
    ++
  • _
    • ++
  • a
    • ++
  • b
    • ++
  • c
    • ++
  • d
    • ++
  • e
    • ++
  • f
    • ++
  • g
    • ++
  • h
    • ++
  • i
    • ++
  • k
    • ++
  • m
    • ++
  • p
    • ++
  • q
    • ++
  • r
    • ++
  • s
    • ++
  • u
    • ++
  • v
    • ++
  • w
    • ++
++
++ ++

++  ++

++

- k -

++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_func_0x6d.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_func_0x6d.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,66 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields ++ ++ ++ ++ ++
++
++
++
++
++ ++
++
++
    ++
  • _
    • ++
  • a
    • ++
  • b
    • ++
  • c
    • ++
  • d
    • ++
  • e
    • ++
  • f
    • ++
  • g
    • ++
  • h
    • ++
  • i
    • ++
  • k
    • ++
  • m
    • ++
  • p
    • ++
  • q
    • ++
  • r
    • ++
  • s
    • ++
  • u
    • ++
  • v
    • ++
  • w
    • ++
++
++ ++

++  ++

++

- m -

++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_func_0x70.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_func_0x70.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,78 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields ++ ++ ++ ++ ++
++
++
++
++
++ ++
++
++
    ++
  • _
    • ++
  • a
    • ++
  • b
    • ++
  • c
    • ++
  • d
    • ++
  • e
    • ++
  • f
    • ++
  • g
    • ++
  • h
    • ++
  • i
    • ++
  • k
    • ++
  • m
    • ++
  • p
    • ++
  • q
    • ++
  • r
    • ++
  • s
    • ++
  • u
    • ++
  • v
    • ++
  • w
    • ++
++
++ ++

++  ++

++

- p -

++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_func_0x71.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_func_0x71.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,67 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields ++ ++ ++ ++ ++
++
++
++
++
++ ++
++
++
    ++
  • _
    • ++
  • a
    • ++
  • b
    • ++
  • c
    • ++
  • d
    • ++
  • e
    • ++
  • f
    • ++
  • g
    • ++
  • h
    • ++
  • i
    • ++
  • k
    • ++
  • m
    • ++
  • p
    • ++
  • q
    • ++
  • r
    • ++
  • s
    • ++
  • u
    • ++
  • v
    • ++
  • w
    • ++
++
++ ++

++  ++

++

- q -

++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_func_0x72.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_func_0x72.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,80 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields ++ ++ ++ ++ ++
++
++
++
++
++ ++
++
++
    ++
  • _
    • ++
  • a
    • ++
  • b
    • ++
  • c
    • ++
  • d
    • ++
  • e
    • ++
  • f
    • ++
  • g
    • ++
  • h
    • ++
  • i
    • ++
  • k
    • ++
  • m
    • ++
  • p
    • ++
  • q
    • ++
  • r
    • ++
  • s
    • ++
  • u
    • ++
  • v
    • ++
  • w
    • ++
++
++ ++

++  ++

++

- r -

++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_func_0x73.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_func_0x73.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,77 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields ++ ++ ++ ++ ++
++
++
++
++
++ ++
++
++
    ++
  • _
    • ++
  • a
    • ++
  • b
    • ++
  • c
    • ++
  • d
    • ++
  • e
    • ++
  • f
    • ++
  • g
    • ++
  • h
    • ++
  • i
    • ++
  • k
    • ++
  • m
    • ++
  • p
    • ++
  • q
    • ++
  • r
    • ++
  • s
    • ++
  • u
    • ++
  • v
    • ++
  • w
    • ++
++
++ ++

++  ++

++

- s -

++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_func_0x75.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_func_0x75.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,73 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields ++ ++ ++ ++ ++
++
++
++
++
++ ++
++
++
    ++
  • _
    • ++
  • a
    • ++
  • b
    • ++
  • c
    • ++
  • d
    • ++
  • e
    • ++
  • f
    • ++
  • g
    • ++
  • h
    • ++
  • i
    • ++
  • k
    • ++
  • m
    • ++
  • p
    • ++
  • q
    • ++
  • r
    • ++
  • s
    • ++
  • u
    • ++
  • v
    • ++
  • w
    • ++
++
++ ++

++  ++

++

- u -

++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_func_0x76.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_func_0x76.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,65 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields ++ ++ ++ ++ ++
++
++
++
++
++ ++
++
++
    ++
  • _
    • ++
  • a
    • ++
  • b
    • ++
  • c
    • ++
  • d
    • ++
  • e
    • ++
  • f
    • ++
  • g
    • ++
  • h
    • ++
  • i
    • ++
  • k
    • ++
  • m
    • ++
  • p
    • ++
  • q
    • ++
  • r
    • ++
  • s
    • ++
  • u
    • ++
  • v
    • ++
  • w
    • ++
++
++ ++

++  ++

++

- v -

++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_func_0x77.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_func_0x77.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,70 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields ++ ++ ++ ++ ++
++
++
++
++
++ ++
++
++
    ++
  • _
    • ++
  • a
    • ++
  • b
    • ++
  • c
    • ++
  • d
    • ++
  • e
    • ++
  • f
    • ++
  • g
    • ++
  • h
    • ++
  • i
    • ++
  • k
    • ++
  • m
    • ++
  • p
    • ++
  • q
    • ++
  • r
    • ++
  • s
    • ++
  • u
    • ++
  • v
    • ++
  • w
    • ++
++
++ ++

++  ++

++

- w -

++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_type.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_type.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,175 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields ++ ++ ++ ++ ++
++
++
++
++
++ ++
++
++
    ++
  • c
    • ++
  • d
    • ++
  • e
    • ++
  • f
    • ++
  • g
    • ++
  • h
    • ++
  • i
    • ++
  • p
    • ++
  • r
    • ++
  • t
    • ++
++
++ ++

++  ++

++

- c -

++

- d -

++

- e -

++

- f -

++

- g -

++

- h -

++

- i -

++

- p -

++

- r -

++

- t -

++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_vars.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_vars.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,120 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields ++ ++ ++ ++ ++
++
++
++
++
++ ++
++
++
    ++
  • b
    • ++
  • d
    • ++
  • f
    • ++
  • g
    • ++
  • h
    • ++
  • p
    • ++
  • r
    • ++
  • s
    • ++
  • u
    • ++
  • w
    • ++
++
++ ++

++  ++

++

- b -

++

- d -

++

- f -

++

- g -

++

- h -

++

- p -

++

- r -

++

- s -

++

- u -

++

- w -

++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/index.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/index.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,8 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver ++ ++ ++ ++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/linux module attributes.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/linux module attributes.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,130 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: ++ ++ ++ ++ ++
++
++The Linux module attributes feature is used to provide the Linux Diagnostic Interface.

++These attributes are accessed through sysfs. The diagnostic interface will provide access to the controller for bringing up the hardware and testing.

++The following table shows the attributes. ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
Name Description Access

++

mode Returns the current mode: 0 for device mode, 1 for host mode Read

++

hnpcapable Gets or sets the "HNP-capable" bit in the Core USB Configuraton Register. Read returns the current value. Read/Write

++

srpcapable Gets or sets the "SRP-capable" bit in the Core USB Configuraton Register. Read returns the current value. Read/Write

++

hsic_connect Gets or sets the "HSIC-Connect" bit in the GLPMCFG Register. Read returns the current value. Read/Write

++

inv_sel_hsic Gets or sets the "Invert Select HSIC" bit in the GLPMFG Register. Read returns the current value. Read/Write

++

hnp Initiates the Host Negotiation Protocol. Read returns the status. Read/Write

++

srp Initiates the Session Request Protocol. Read returns the status. Read/Write

++

buspower Gets or sets the Power State of the bus (0 - Off or 1 - On) Read/Write

++

bussuspend Suspends the USB bus. Read/Write

++

busconnected Gets the connection status of the bus Read

++

gotgctl Gets or sets the Core Control Status Register. Read/Write

++

gusbcfg Gets or sets the Core USB Configuration Register Read/Write

++

grxfsiz Gets or sets the Receive FIFO Size Register Read/Write

++

gnptxfsiz Gets or sets the non-periodic Transmit Size Register Read/Write

++

gpvndctl Gets or sets the PHY Vendor Control Register Read/Write

++

ggpio Gets the value in the lower 16-bits of the General Purpose IO Register or sets the upper 16 bits. Read/Write

++

guid Gets or sets the value of the User ID Register Read/Write

++

gsnpsid Gets the value of the Synopsys ID Regester Read

++

devspeed Gets or sets the device speed setting in the DCFG register Read/Write

++

enumspeed Gets the device enumeration Speed. Read

++

hptxfsiz Gets the value of the Host Periodic Transmit FIFO Read

++

hprt0 Gets or sets the value in the Host Port Control and Status Register Read/Write

++

regoffset Sets the register offset for the next Register Access Read/Write

++

regvalue Gets or sets the value of the register at the offset in the regoffset attribute. Read/Write

++

remote_wakeup On read, shows the status of Remote Wakeup. On write, initiates a remote wakeup of the host. When bit 0 is 1 and Remote Wakeup is enabled, the Remote Wakeup signalling bit in the Device Control Register is set for 1 milli-second. Read/Write

++

regdump Dumps the contents of core registers. Read

++

spramdump Dumps the contents of core registers. Read

++

hcddump Dumps the current HCD state. Read

++

hcd_frrem Shows the average value of the Frame Remaining field in the Host Frame Number/Frame Remaining register when an SOF interrupt occurs. This can be used to determine the average interrupt latency. Also shows the average Frame Remaining value for start_transfer and the "a" and "b" sample points. The "a" and "b" sample points may be used during debugging bto determine how long it takes to execute a section of the HCD code. Read

++

rd_reg_test Displays the time required to read the GNPTXFSIZ register many times (the output shows the number of times the register is read). Read

++

wr_reg_test Displays the time required to write the GNPTXFSIZ register many times (the output shows the number of times the register is written). Read

++

lpm_response Gets or sets lpm_response mode. Applicable only in device mode. Write

++

sleep_local_dev Generetates sleep signaling. Applicable only in host mode. Write

++

sleep_status Shows sleep status of device. Read

++

++

++Example usage: To get the current mode: cat /sys/devices/lm0/mode

++To power down the USB: echo 0 > /sys/devices/lm0/buspower

Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/main.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/main.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,21 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Main Page ++ ++ ++ ++ ++
++
++

DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver Documentation

++

++

v2.90a

Generated on Tue May 5 02:22:48 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/module parameters.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/module parameters.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,189 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: ++ ++ ++ ++ ++
++
++The following parameters may be specified when starting the module.

++These parameters define how the DWC_otg controller should be configured. Parameter values are passed to the CIL initialization function dwc_otg_cil_init

++Example: modprobe dwc_otg speed=1 otg_cap=1

++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
Parameter NameMeaning

++

otg_cap Specifies the OTG capabilities. The driver will automatically detect the value for this parameter if none is specified.
    ++
  • 0: HNP and SRP capable (default, if available)
  • 1: SRP Only capable
  • 2: No HNP/SRP capable
++

++

dma_enable Specifies whether to use slave or DMA mode for accessing the data FIFOs. The driver will automatically detect the value for this parameter if none is specified.
    ++
  • 0: Slave
  • 1: DMA (default, if available)
++

++

dma_burst_size The DMA Burst size (applicable only for External DMA Mode).
    ++
  • Values: 1, 4, 8 16, 32, 64, 128, 256 (default 32)
++

++

speed Specifies the maximum speed of operation in host and device mode. The actual speed depends on the speed of the attached device and the value of phy_type.
    ++
  • 0: High Speed (default)
  • 1: Full Speed
++

++

host_support_fs_ls_low_power Specifies whether low power mode is supported when attached to a Full Speed or Low Speed device in host mode.
    ++
  • 0: Don't support low power mode (default)
  • 1: Support low power mode
++

++

host_ls_low_power_phy_clk Specifies the PHY clock rate in low power mode when connected to a Low Speed device in host mode. This parameter is applicable only if HOST_SUPPORT_FS_LS_LOW_POWER is enabled.
    ++
  • 0: 48 MHz (default)
  • 1: 6 MHz
++

++

enable_dynamic_fifo Specifies whether FIFOs may be resized by the driver software.
    ++
  • 0: Use cC FIFO size parameters
  • 1: Allow dynamic FIFO sizing (default)
++

++

data_fifo_size Total number of 4-byte words in the data FIFO memory. This memory includes the Rx FIFO, non-periodic Tx FIFO, and periodic Tx FIFOs.
    ++
  • Values: 32 to 32768 (default 8192)
++

++Note: The total FIFO memory depth in the FPGA configuration is 8192.

++

dev_rx_fifo_size Number of 4-byte words in the Rx FIFO in device mode when dynamic FIFO sizing is enabled.
    ++
  • Values: 16 to 32768 (default 1064)
++

++

dev_nperio_tx_fifo_size Number of 4-byte words in the non-periodic Tx FIFO in device mode when dynamic FIFO sizing is enabled.
    ++
  • Values: 16 to 32768 (default 1024)
++

++

dev_perio_tx_fifo_size_n (n = 1 to 15) Number of 4-byte words in each of the periodic Tx FIFOs in device mode when dynamic FIFO sizing is enabled.
    ++
  • Values: 4 to 768 (default 256)
++

++

host_rx_fifo_size Number of 4-byte words in the Rx FIFO in host mode when dynamic FIFO sizing is enabled.
    ++
  • Values: 16 to 32768 (default 1024)
++

++

host_nperio_tx_fifo_size Number of 4-byte words in the non-periodic Tx FIFO in host mode when dynamic FIFO sizing is enabled in the core.
    ++
  • Values: 16 to 32768 (default 1024)
++

++

host_perio_tx_fifo_size Number of 4-byte words in the host periodic Tx FIFO when dynamic FIFO sizing is enabled.
    ++
  • Values: 16 to 32768 (default 1024)
++

++

max_transfer_size The maximum transfer size supported in bytes.
    ++
  • Values: 2047 to 65,535 (default 65,535)
++

++

max_packet_count The maximum number of packets in a transfer.
    ++
  • Values: 15 to 511 (default 511)
++

++

host_channels The number of host channel registers to use.
    ++
  • Values: 1 to 16 (default 12)
++

++Note: The FPGA configuration supports a maximum of 12 host channels.

++

dev_endpoints The number of endpoints in addition to EP0 available for device mode operations.
    ++
  • Values: 1 to 15 (default 6 IN and OUT)
++

++Note: The FPGA configuration supports a maximum of 6 IN and OUT endpoints in addition to EP0.

++

phy_type Specifies the type of PHY interface to use. By default, the driver will automatically detect the phy_type.
    ++
  • 0: Full Speed
  • 1: UTMI+ (default, if available)
  • 2: ULPI
++

++

phy_utmi_width Specifies the UTMI+ Data Width. This parameter is applicable for a phy_type of UTMI+. Also, this parameter is applicable only if the OTG_HSPHY_WIDTH cC parameter was set to "8 and 16 bits", meaning that the core has been configured to work at either data path width.
    ++
  • Values: 8 or 16 bits (default 16)
++

++

phy_ulpi_ddr Specifies whether the ULPI operates at double or single data rate. This parameter is only applicable if phy_type is ULPI.
    ++
  • 0: single data rate ULPI interface with 8 bit wide data bus (default)
  • 1: double data rate ULPI interface with 4 bit wide data bus
++

++

i2c_enable Specifies whether to use the I2C interface for full speed PHY. This parameter is only applicable if PHY_TYPE is FS.
    ++
  • 0: Disabled (default)
  • 1: Enabled
++

++

otg_en_multiple_tx_fifo Specifies whether dedicatedto tx fifos are enabled for non periodic IN EPs. The driver will automatically detect the value for this parameter if none is specified.
    ++
  • 0: Disabled
  • 1: Enabled (default, if available)
++

++

dev_tx_fifo_size_n (n = 1 to 15) Number of 4-byte words in each of the Tx FIFOs in device mode when dynamic FIFO sizing is enabled.
    ++
  • Values: 4 to 768 (default 256)
++

++

tx_thr_length Transmit Threshold length in 32 bit double words
    ++
  • Values: 8 to 128 (default 64)
++

++

rx_thr_length Receive Threshold length in 32 bit double words
    ++
  • Values: 8 to 128 (default 64)
++

++

thr_ctl Specifies whether to enable Thresholding for Device mode. Bits 0, 1, 2 of this parmater specifies if thresholding is enabled for non-Iso Tx, Iso Tx and Rx transfers accordingly. The driver will automatically detect the value for this parameter if none is specified.
    ++
  • Values: 0 to 7 (default 0) Bit values indicate:
  • 0: Thresholding disabled
  • 1: Thresholding enabled
++

++

dma_desc_enable Specifies whether to enable Descriptor DMA mode. The driver will automatically detect the value for this parameter if none is specified.
    ++
  • 0: Descriptor DMA disabled
  • 1: Descriptor DMA (default, if available)
++

++

mpi_enable Specifies whether to enable MPI enhancement mode. The driver will automatically detect the value for this parameter if none is specified.
    ++
  • 0: MPI disabled (default)
  • 1: MPI enable
++

++

pti_enable Specifies whether to enable PTI enhancement support. The driver will automatically detect the value for this parameter if none is specified.
    ++
  • 0: PTI disabled (default)
  • 1: PTI enable
++

++

lpm_enable Specifies whether to enable LPM support. The driver will automatically detect the value for this parameter if none is specified.
    ++
  • 0: LPM disabled
  • 1: LPM enable (default, if available)
++

++

ahb_thr_ratio Specifies AHB Threshold ratio.
    ++
  • Values: 0 to 3 (default 0)
++
++

Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/pages.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/pages.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,27 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Page Index ++ ++ ++ ++ ++
++
++

DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver Related Pages

Here is a list of all related documentation pages: ++
Generated on Tue May 5 02:22:50 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/struct__ddma__align__buffer__setup.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/struct__ddma__align__buffer__setup.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,46 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: _ddma_align_buffer_setup Struct Reference ++ ++ ++ ++ ++
++
++
++
++

_ddma_align_buffer_setup Struct Reference

Descriptor DMA Alignment Buffer setup structure. ++More... ++

++#include <dwc_otg_cfi.h> ++

++ ++ ++ ++ ++ ++ ++ ++

Data Fields

++uint8_t bEndpointAddress
++uint8_t bAlign
++

Detailed Description

++Descriptor DMA Alignment Buffer setup structure. ++

++ ++

++Definition at line 115 of file dwc_otg_cfi.h.

The documentation for this struct was generated from the following file: ++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/struct__ddma__concat__buffer__setup.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/struct__ddma__concat__buffer__setup.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,46 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: _ddma_concat_buffer_setup Struct Reference ++ ++ ++ ++ ++
++
++
++
++

_ddma_concat_buffer_setup Struct Reference

Descriptor DMA Concatenation Buffer setup structure. ++More... ++

++#include <dwc_otg_cfi.h> ++

++ ++ ++ ++ ++ ++ ++ ++

Data Fields

++ddma_concat_buffer_setup_hdr_t hdr
++uint16_t * wTxBytes
++

Detailed Description

++Descriptor DMA Concatenation Buffer setup structure. ++

++ ++

++Definition at line 105 of file dwc_otg_cfi.h.

The documentation for this struct was generated from the following file: ++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/struct__ddma__concat__buffer__setup__hdr.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/struct__ddma__concat__buffer__setup__hdr.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,49 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: _ddma_concat_buffer_setup_hdr Struct Reference ++ ++ ++ ++ ++
++
++
++
++

_ddma_concat_buffer_setup_hdr Struct Reference

Descriptor DMA Concatenation Buffer setup structure. ++More... ++

++#include <dwc_otg_cfi.h> ++

++ ++ ++ ++ ++ ++ ++ ++ ++ ++

Data Fields

++uint8_t bEndpointAddress
++uint8_t bDescCount
++uint16_t wSize
++

Detailed Description

++Descriptor DMA Concatenation Buffer setup structure. ++

++ ++

++Definition at line 93 of file dwc_otg_cfi.h.

The documentation for this struct was generated from the following file: ++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/struct__ddma__sg__buffer__setup.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/struct__ddma__sg__buffer__setup.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,57 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: _ddma_sg_buffer_setup Struct Reference ++ ++ ++ ++ ++
++
++
++
++

_ddma_sg_buffer_setup Struct Reference

Descriptor DMA SG Buffer setup structure (SG buffer). ++More... ++

++#include <dwc_otg_cfi.h> ++

++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++

Data Fields

++uint8_t bOutEndpointAddress
++uint8_t bInEndpointAddress
++uint8_t bOffset
++uint8_t bCount
++uint16_t wSize
++

Detailed Description

++Descriptor DMA SG Buffer setup structure (SG buffer). ++

++This structure is also used for setting up a buffer for Circular DDMA. ++

++ ++

++Definition at line 77 of file dwc_otg_cfi.h.

The documentation for this struct was generated from the following file: ++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/struct__rx__fifo__size__setup.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/struct__rx__fifo__size__setup.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,43 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: _rx_fifo_size_setup Struct Reference ++ ++ ++ ++ ++
++
++
++
++

_rx_fifo_size_setup Struct Reference

Transmit FIFO Size setup structure. ++More... ++

++#include <dwc_otg_cfi.h> ++

++ ++ ++ ++ ++ ++

Data Fields

++uint16_t wDepth
++

Detailed Description

++Transmit FIFO Size setup structure. ++

++ ++

++Definition at line 130 of file dwc_otg_cfi.h.

The documentation for this struct was generated from the following file: ++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/struct__tx__fifo__size__setup.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/struct__tx__fifo__size__setup.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,46 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: _tx_fifo_size_setup Struct Reference ++ ++ ++ ++ ++
++
++
++
++

_tx_fifo_size_setup Struct Reference

Transmit FIFO Size setup structure. ++More... ++

++#include <dwc_otg_cfi.h> ++

++ ++ ++ ++ ++ ++ ++ ++

Data Fields

++uint8_t bEndpointAddress
++uint16_t wDepth
++

Detailed Description

++Transmit FIFO Size setup structure. ++

++ ++

++Definition at line 123 of file dwc_otg_cfi.h.

The documentation for this struct was generated from the following file: ++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structcfi__all__features__header.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structcfi__all__features__header.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,75 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: cfi_all_features_header Struct Reference ++ ++ ++ ++ ++
++
++
++
++

cfi_all_features_header Struct Reference

This structure is the header of the Core Features dataset returned to the Host. ++More... ++

++#include <dwc_cfi_common.h> ++

++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++

Data Fields

++uint16_t wTotalLen
 The total length of the features dataset returned to the Host.
uint16_t wVersion
 CFI version number inBinary-Coded Decimal (i.e., 1.00 is 100H).
++uint16_t wCoreID
 The ID of the Core.
++uint16_t wNumFeatures
 Number of features returned by VEN_CORE_GET_FEATURES request.
++

Detailed Description

++This structure is the header of the Core Features dataset returned to the Host. ++

++ ++

++Definition at line 69 of file dwc_cfi_common.h.

Field Documentation

++ ++
++
++ ++ ++ ++ ++
uint16_t cfi_all_features_header::wVersion
++
++
++ ++

++CFI version number inBinary-Coded Decimal (i.e., 1.00 is 100H). ++

++This field identifies the version of the CFI Specification with which the device is compliant. ++

++Definition at line 82 of file dwc_cfi_common.h. ++

++

++

The documentation for this struct was generated from the following file: ++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structcfi__dma__buff.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structcfi__dma__buff.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,41 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: cfi_dma_buff Struct Reference ++ ++ ++ ++ ++
++
++
++
++

cfi_dma_buff Struct Reference

++ ++ ++ ++ ++ ++ ++

Data Fields

++dma_addr_t addr
++uint8_t * buf
++

Detailed Description

++ ++

++ ++

++Definition at line 182 of file dwc_otg_cfi.h.

The documentation for this struct was generated from the following file: ++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structcfi__ep.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structcfi__ep.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,69 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: cfi_ep Struct Reference ++ ++ ++ ++ ++
++
++
++
++

cfi_ep Struct Reference

The CFI wrapper of the enabled and activated dwc_otg_pcd_ep structures. ++More... ++

++#include <dwc_otg_cfi.h> ++

++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++

Data Fields

++dwc_list_link_t lh
++dwc_otg_pcd_ep * ep
++dwc_otg_dma_desc * dma_desc_last
++ddma_sg_buffer_setup_t * bm_sg
++ddma_sg_buffer_setup_t * bm_circ
++ddma_concat_buffer_setup_t * bm_concat
++ddma_align_buffer_setup_t * bm_align
++uint32_t xfer_len
++uint32_t desc_count
++

Detailed Description

++The CFI wrapper of the enabled and activated dwc_otg_pcd_ep structures. ++

++This structure is used to store the buffer setup data for any enabled endpoint in the PCD. ++

++ ++

++Definition at line 156 of file dwc_otg_cfi.h.

The documentation for this struct was generated from the following file: ++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structcfi__feature__desc__header.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structcfi__feature__desc__header.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,60 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: cfi_feature_desc_header Struct Reference ++ ++ ++ ++ ++
++
++
++
++

cfi_feature_desc_header Struct Reference

This structure is a header of the Core Feature descriptor dataset returned to the Host after the VEN_CORE_GET_FEATURES request. ++More... ++

++#include <dwc_cfi_common.h> ++

++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++

Data Fields

++uint16_t wFeatureID
 The feature ID.
++uint16_t wLength
 Length of this feature descriptor in bytes - including the length of the feature name string.
++uint16_t wDataLength
 The data length of this feature in bytes.
++uint8_t bmAttributes
 Attributes of this features D0: Access rights 0 - Read/Write 1 - Read only.
++uint8_t bNameLen
 Length of the feature name in bytes.
++

Detailed Description

++This structure is a header of the Core Feature descriptor dataset returned to the Host after the VEN_CORE_GET_FEATURES request. ++

++ ++

++Definition at line 99 of file dwc_cfi_common.h.

The documentation for this struct was generated from the following file: ++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structcfi__ops.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structcfi__ops.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,64 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: cfi_ops Struct Reference ++ ++ ++ ++ ++
++
++
++
++

cfi_ops Struct Reference

This is the interface for the CFI operations. ++More... ++

++#include <dwc_otg_cfi.h> ++

++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++

Data Fields

++int(* ep_enable )(struct cfiobject *cfi, struct dwc_otg_pcd *pcd, struct dwc_otg_pcd_ep *ep)
++void *(* ep_alloc_buf )(struct cfiobject *cfi, struct dwc_otg_pcd *pcd, struct dwc_otg_pcd_ep *ep, dma_addr_t *dma, unsigned size, gfp_t flags)
++void(* release )(struct cfiobject *cfi)
++int(* ctrl_write_complete )(struct cfiobject *cfi, struct dwc_otg_pcd *pcd)
++void(* build_descriptors )(struct cfiobject *cfi, struct dwc_otg_pcd *pcd, struct dwc_otg_pcd_ep *ep, dwc_otg_pcd_request_t *req)
++

Detailed Description

++This is the interface for the CFI operations. ++

++

Parameters:
++ ++ ++ ++ ++
ep_enable Called when any endpoint is enabled and activated.
release Called when the CFI object is released and it needs to correctly deallocate the dynamic memory
ctrl_write_complete Called when the data stage of the request is complete
++
++ ++

++ ++

++Definition at line 199 of file dwc_otg_cfi.h.

The documentation for this struct was generated from the following file: ++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structcfi__string.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structcfi__string.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,48 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: cfi_string Struct Reference ++ ++ ++ ++ ++
++
++
++
++

cfi_string Struct Reference

This structure describes a NULL terminated string referenced by its id field. ++More... ++

++#include <dwc_cfi_common.h> ++

++ ++ ++ ++ ++ ++ ++ ++

Data Fields

++uint16_t id
++const uint8_t * s
++

Detailed Description

++This structure describes a NULL terminated string referenced by its id field. ++

++It is very similar to usb_string structure but has the id field type set to 16-bit. ++

++ ++

++Definition at line 136 of file dwc_cfi_common.h.

The documentation for this struct was generated from the following file: ++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structcfi__usb__ctrlrequest.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structcfi__usb__ctrlrequest.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,58 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: cfi_usb_ctrlrequest Struct Reference ++ ++ ++ ++ ++
++
++
++
++

cfi_usb_ctrlrequest Struct Reference

struct cfi_usb_ctrlrequest - the CFI implementation of the struct usb_ctrlrequest This structure encapsulates the standard usb_ctrlrequest and adds a pointer to the data returned in the data stage of a 3-stage Control Write requests. ++More... ++

++#include <dwc_otg_cfi.h> ++

++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++

Data Fields

++uint8_t bRequestType
++uint8_t bRequest
++uint16_t wValue
++uint16_t wIndex
++uint16_t wLength
++uint8_t * data
++

Detailed Description

++struct cfi_usb_ctrlrequest - the CFI implementation of the struct usb_ctrlrequest This structure encapsulates the standard usb_ctrlrequest and adds a pointer to the data returned in the data stage of a 3-stage Control Write requests. ++

++ ++

++Definition at line 140 of file dwc_otg_cfi.h.

The documentation for this struct was generated from the following file: ++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structcfiobject.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structcfiobject.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,62 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: cfiobject Struct Reference ++ ++ ++ ++ ++
++
++
++
++

cfiobject Struct Reference

++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++

Data Fields

++cfi_ops_t ops
++dwc_otg_pcd * pcd
++usb_gadget * gadget
++cfi_dma_buff_t buf_in
++cfi_dma_buff_t buf_out
++cfi_usb_ctrlrequest ctrl_req
++dwc_list_link_t active_eps
++uint8_t need_gadget_att
++uint8_t need_status_in_complete
++

Detailed Description

++ ++

++ ++

++Definition at line 214 of file dwc_otg_cfi.h.

The documentation for this struct was generated from the following file: ++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structdwc__ep.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structdwc__ep.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,192 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_ep Struct Reference ++ ++ ++ ++ ++
++
++
++
++

dwc_ep Struct Reference

The dwc_ep structure represents the state of a single endpoint when acting in device mode. ++More... ++

++#include <dwc_otg_cil.h> ++

++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++

Data Fields

++uint8_t num
 EP number used for register address lookup.
++unsigned is_in:1
 EP direction 0 = OUT.
++unsigned active:1
 EP active.
++unsigned tx_fifo_num:4
 Periodic Tx FIFO # for IN EPs For INTR EP set to 0 to use non-periodic Tx FIFO If dedicated Tx FIFOs are enabled for all IN Eps - Tx FIFO # FOR IN EPs.
++unsigned type:2
 EP type: 0 - Control, 1 - ISOC, 2 - BULK, 3 - INTR.
++unsigned data_pid_start:1
 DATA start PID for INTR and BULK EP.
++unsigned even_odd_frame:1
 Frame (even/odd) for ISOC EP.
++unsigned maxpacket:11
 Max Packet bytes.
++uint32_t maxxfer
 Max Transfer size.
Transfer state
++dwc_dma_t dma_addr
 Pointer to the beginning of the transfer buffer -- do not modify during transfer.
++dwc_dma_t dma_desc_addr
++dwc_otg_dev_dma_desc_t * desc_addr
++uint8_t * start_xfer_buff
++uint8_t * xfer_buff
 pointer to the transfer buffer
++unsigned xfer_len:19
 Number of bytes to transfer.
++unsigned xfer_count:19
 Number of bytes transferred.
++unsigned sent_zlp:1
 Sent ZLP.
++unsigned total_len:19
 Total len for control transfer.
++unsigned stall_clear_flag:1
 stall clear flag
++uint32_t desc_cnt
 Allocated DMA Desc count.
++dwc_dma_t dma_addr0
 DMA addresses of ISOC buffers.
++dwc_dma_t dma_addr1
++dwc_dma_t iso_dma_desc_addr
++dwc_otg_dev_dma_desc_t * iso_desc_addr
++uint8_t * xfer_buff0
 pointer to the transfer buffers
++uint8_t * xfer_buff1
++uint32_t proc_buf_num
 number of ISOC Buffer is processing
++uint32_t buf_proc_intrvl
 Interval of ISOC Buffer processing.
++uint32_t data_per_frame
 Data size for regular frame.
++uint32_t data_pattern_frame
 Data size for pattern frame.
++uint32_t sync_frame
 Frame number of pattern data.
++uint32_t bInterval
 bInterval
++uint32_t pkt_per_frm
 ISO Packet number per frame.
++uint32_t next_frame
 Next frame num for which will be setup DMA Desc.
++uint32_t pkt_cnt
 Number of packets per buffer processing.
++iso_pkt_info_t * pkt_info
 Info for all isoc packets.
++uint32_t cur_pkt
 current pkt number
++uint8_t * cur_pkt_addr
 current pkt number
++uint32_t cur_pkt_dma_addr
 current pkt number
++

Detailed Description

++The dwc_ep structure represents the state of a single endpoint when acting in device mode. ++

++It contains the data items needed for an endpoint to be activated and transfer packets. ++

++ ++

++Definition at line 88 of file dwc_otg_cil.h.

The documentation for this struct was generated from the following file: ++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structdwc__hc.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structdwc__hc.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,345 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_hc Struct Reference ++ ++ ++ ++ ++
++
++
++
++

dwc_hc Struct Reference

Host channel descriptor. ++More... ++

++#include <dwc_otg_cil.h> ++

++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++

Public Member Functions

++ DWC_CIRCLEQ_ENTRY (dwc_hc) hc_list_entry
 Entry in list of host channels.

Data Fields

++uint8_t hc_num
 Host channel number used for register address lookup.
++unsigned dev_addr:7
 Device to access.
++unsigned ep_num:4
 EP to access.
unsigned ep_is_in:1
 EP direction.
unsigned speed:2
 EP speed.
unsigned ep_type:2
 Endpoint type.
++unsigned max_packet:11
 Max packet size in bytes.
unsigned data_pid_start:2
 PID for initial transaction.
++unsigned multi_count:2
 Number of periodic transactions per (micro)frame.
Transfer State
++uint8_t * xfer_buff
 Pointer to the current transfer buffer position.
++dwc_dma_t align_buff
 In Buffer DMA mode this buffer will be used if xfer_buff is not DWORD aligned.
++uint32_t xfer_len
 Total number of bytes to transfer.
++uint32_t xfer_count
 Number of bytes transferred so far.
++uint16_t start_pkt_count
 Packet count at start of transfer.
uint8_t xfer_started
 Flag to indicate whether the transfer has been started.
uint8_t do_ping
 Set to 1 to indicate that a PING request should be issued on this channel.
uint8_t error_state
 Set to 1 to indicate that the error count for this transaction is non-zero.
uint8_t halt_on_queue
 Set to 1 to indicate that this channel should be halted the next time a request is queued for the channel.
uint8_t halt_pending
 Set to 1 if the host channel has been halted, but the core is not finished flushing queued requests.
++dwc_otg_halt_status_e halt_status
 Reason for halting the host channel.
++uint8_t do_split
 Enable split for the channel.
++uint8_t complete_split
 Enable complete split.
++uint8_t hub_addr
 Address of high speed hub.
++uint8_t port_addr
 Port of the low/full speed device.
++uint8_t xact_pos
 Split transaction position One of the following values:
    ++
  • DWC_HCSPLIT_XACTPOS_MID
  • DWC_HCSPLIT_XACTPOS_BEGIN
  • DWC_HCSPLIT_XACTPOS_END
  • DWC_HCSPLIT_XACTPOS_ALL.
++
++uint8_t short_read
 Set when the host channel does a short read.
++uint8_t requests
 Number of requests issued for this channel since it was assigned to the current transfer (not counting PINGs).
++dwc_otg_qh * qh
 Queue Head for the transfer being processed by this channel.
Descriptor DMA support
++uint16_t ntd
 Number of Transfer Descriptors.
++dwc_dma_t desc_list_addr
 Descriptor List DMA address.
++uint8_t schinfo
 Scheduling micro-frame bitmap.
++

Detailed Description

++Host channel descriptor. ++

++This structure represents the state of a single host channel when acting in host mode. It contains the data items needed to transfer packets to an endpoint via a host channel. ++

++ ++

++Definition at line 237 of file dwc_otg_cil.h.

Field Documentation

++ ++
++
++ ++ ++ ++ ++
unsigned dwc_hc::ep_is_in
++
++
++ ++

++EP direction. ++

++0: OUT, 1: IN ++

++Definition at line 248 of file dwc_otg_cil.h. ++

++

++ ++

++
++ ++ ++ ++ ++
unsigned dwc_hc::speed
++
++
++ ++

++EP speed. ++

++One of the following values:

    ++
  • DWC_OTG_EP_SPEED_LOW
  • DWC_OTG_EP_SPEED_FULL
  • DWC_OTG_EP_SPEED_HIGH
++ ++

++Definition at line 257 of file dwc_otg_cil.h. ++

++

++ ++

++
++ ++ ++ ++ ++
unsigned dwc_hc::ep_type
++
++
++ ++

++Endpoint type. ++

++One of the following values:

    ++
  • DWC_OTG_EP_TYPE_CONTROL: 0
  • DWC_OTG_EP_TYPE_ISOC: 1
  • DWC_OTG_EP_TYPE_BULK: 2
  • DWC_OTG_EP_TYPE_INTR: 3
++ ++

++Definition at line 270 of file dwc_otg_cil.h. ++

++

++ ++

++
++ ++ ++ ++ ++
unsigned dwc_hc::data_pid_start
++
++
++ ++

++PID for initial transaction. ++

++0: DATA0,
++ 1: DATA2,
++ 2: DATA1,
++ 3: MDATA (non-Control EP), SETUP (Control EP) ++

++Definition at line 283 of file dwc_otg_cil.h. ++

++

++ ++

++
++ ++ ++ ++ ++
uint8_t dwc_hc::xfer_started
++
++
++ ++

++Flag to indicate whether the transfer has been started. ++

++Set to 1 if it has been started, 0 otherwise. ++

++Definition at line 314 of file dwc_otg_cil.h. ++

++

++ ++

++
++ ++ ++ ++ ++
uint8_t dwc_hc::do_ping
++
++
++ ++

++Set to 1 to indicate that a PING request should be issued on this channel. ++

++If 0, process normally. ++

++Definition at line 320 of file dwc_otg_cil.h. ++

++

++ ++

++
++ ++ ++ ++ ++
uint8_t dwc_hc::error_state
++
++
++ ++

++Set to 1 to indicate that the error count for this transaction is non-zero. ++

++Set to 0 if the error count is 0. ++

++Definition at line 326 of file dwc_otg_cil.h. ++

++

++ ++

++
++ ++ ++ ++ ++
uint8_t dwc_hc::halt_on_queue
++
++
++ ++

++Set to 1 to indicate that this channel should be halted the next time a request is queued for the channel. ++

++This is necessary in slave mode if no request queue space is available when an attempt is made to halt the channel. ++

++Definition at line 334 of file dwc_otg_cil.h. ++

++

++ ++

++
++ ++ ++ ++ ++
uint8_t dwc_hc::halt_pending
++
++
++ ++

++Set to 1 if the host channel has been halted, but the core is not finished flushing queued requests. ++

++Otherwise 0. ++

++Definition at line 340 of file dwc_otg_cil.h. ++

++

++

The documentation for this struct was generated from the following file: ++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__cil__callbacks.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__cil__callbacks.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,70 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_cil_callbacks Struct Reference ++ ++ ++ ++ ++
++
++
++
++

dwc_otg_cil_callbacks Struct Reference

DWC_otg CIL callback structure. ++More... ++

++#include <dwc_otg_cil.h> ++

++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++

Data Fields

++int(* start )(void *_p)
 Start function for role change.
++int(* stop )(void *_p)
 Stop Function for role change.
++int(* disconnect )(void *_p)
 Disconnect Function for role change.
++int(* resume_wakeup )(void *_p)
 Resume/Remote wakeup Function.
++int(* suspend )(void *_p)
 Suspend function.
++int(* session_start )(void *_p)
 Session Start (SRP).
++void * p
 Pointer passed to start() and stop().
++

Detailed Description

++DWC_otg CIL callback structure. ++

++This structure allows the HCD and PCD to register functions used for starting and stopping the PCD and HCD for role change on for a DRD. ++

++ ++

++Definition at line 1109 of file dwc_otg_cil.h.

The documentation for this struct was generated from the following file: ++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__core__global__regs.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__core__global__regs.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,557 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_core_global_regs Struct Reference ++ ++ ++ ++ ++
++
++
++
++

dwc_otg_core_global_regs Struct Reference

DWC_otg Core registers . ++More... ++

++#include <dwc_otg_regs.h> ++

++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++

Data Fields

volatile uint32_t gotgctl
 OTG Control and Status Register.
volatile uint32_t gotgint
 OTG Interrupt Register.
volatile uint32_t gahbcfg
 Core AHB Configuration Register.
volatile uint32_t gusbcfg
 Core USB Configuration Register.
volatile uint32_t grstctl
 Core Reset Register.
volatile uint32_t gintsts
 Core Interrupt Register.
volatile uint32_t gintmsk
 Core Interrupt Mask Register.
volatile uint32_t grxstsr
 Receive Status Queue Read Register (Read Only).
volatile uint32_t grxstsp
 Receive Status Queue Read & POP Register (Read Only).
volatile uint32_t grxfsiz
 Receive FIFO Size Register.
volatile uint32_t gnptxfsiz
 Non Periodic Transmit FIFO Size Register.
volatile uint32_t gnptxsts
 Non Periodic Transmit FIFO/Queue Status Register (Read Only).
volatile uint32_t gi2cctl
 I2C Access Register.
volatile uint32_t gpvndctl
 PHY Vendor Control Register.
volatile uint32_t ggpio
 General Purpose Input/Output Register.
volatile uint32_t guid
 User ID Register.
volatile uint32_t gsnpsid
 Synopsys ID Register (Read Only).
volatile uint32_t ghwcfg1
 User HW Config1 Register (Read Only).
volatile uint32_t ghwcfg2
 User HW Config2 Register (Read Only).
volatile uint32_t ghwcfg3
 User HW Config3 Register (Read Only).
volatile uint32_t ghwcfg4
 User HW Config4 Register (Read Only).
++volatile uint32_t glpmcfg
 Core LPM Configuration register.
++volatile uint32_t reserved [42]
 Reserved Offset: 058h-0FFh.
volatile uint32_t hptxfsiz
 Host Periodic Transmit FIFO Size Register.
volatile uint32_t dptxfsiz_dieptxf [15]
 Device Periodic Transmit FIFO::n Register if dedicated fifos are disabled, otherwise Device Transmit FIFO::n Register.
++

Detailed Description

++DWC_otg Core registers . ++

++The dwc_otg_core_global_regs structure defines the size and relative field offsets for the Core Global registers. ++

++ ++

++Definition at line 71 of file dwc_otg_regs.h.

Field Documentation

++ ++
++
++ ++ ++ ++ ++
volatile uint32_t dwc_otg_core_global_regs::gotgctl
++
++
++ ++

++OTG Control and Status Register. ++

++Offset: 000h ++

++Definition at line 73 of file dwc_otg_regs.h. ++

++

++ ++

++
++ ++ ++ ++ ++
volatile uint32_t dwc_otg_core_global_regs::gotgint
++
++
++ ++

++OTG Interrupt Register. ++

++Offset: 004h ++

++Definition at line 75 of file dwc_otg_regs.h. ++

++

++ ++

++
++ ++ ++ ++ ++
volatile uint32_t dwc_otg_core_global_regs::gahbcfg
++
++
++ ++

++Core AHB Configuration Register. ++

++Offset: 008h ++

++Definition at line 77 of file dwc_otg_regs.h. ++

++

++ ++

++
++ ++ ++ ++ ++
volatile uint32_t dwc_otg_core_global_regs::gusbcfg
++
++
++ ++

++Core USB Configuration Register. ++

++Offset: 00Ch ++

++Definition at line 87 of file dwc_otg_regs.h. ++

++

++ ++

++
++ ++ ++ ++ ++
volatile uint32_t dwc_otg_core_global_regs::grstctl
++
++
++ ++

++Core Reset Register. ++

++Offset: 010h ++

++Definition at line 89 of file dwc_otg_regs.h. ++

++

++ ++

++
++ ++ ++ ++ ++
volatile uint32_t dwc_otg_core_global_regs::gintsts
++
++
++ ++

++Core Interrupt Register. ++

++Offset: 014h ++

++Definition at line 91 of file dwc_otg_regs.h. ++

++

++ ++

++
++ ++ ++ ++ ++
volatile uint32_t dwc_otg_core_global_regs::gintmsk
++
++
++ ++

++Core Interrupt Mask Register. ++

++Offset: 018h ++

++Definition at line 93 of file dwc_otg_regs.h. ++

++

++ ++

++
++ ++ ++ ++ ++
volatile uint32_t dwc_otg_core_global_regs::grxstsr
++
++
++ ++

++Receive Status Queue Read Register (Read Only). ++

++Offset: 01Ch ++

++Definition at line 95 of file dwc_otg_regs.h. ++

++

++ ++

++
++ ++ ++ ++ ++
volatile uint32_t dwc_otg_core_global_regs::grxstsp
++
++
++ ++

++Receive Status Queue Read & POP Register (Read Only). ++

++Offset: 020h ++

++Definition at line 97 of file dwc_otg_regs.h. ++

++

++ ++

++
++ ++ ++ ++ ++
volatile uint32_t dwc_otg_core_global_regs::grxfsiz
++
++
++ ++

++Receive FIFO Size Register. ++

++Offset: 024h ++

++Definition at line 99 of file dwc_otg_regs.h. ++

++

++ ++

++
++ ++ ++ ++ ++
volatile uint32_t dwc_otg_core_global_regs::gnptxfsiz
++
++
++ ++

++Non Periodic Transmit FIFO Size Register. ++

++Offset: 028h ++

++Definition at line 101 of file dwc_otg_regs.h. ++

++

++ ++

++
++ ++ ++ ++ ++
volatile uint32_t dwc_otg_core_global_regs::gnptxsts
++
++
++ ++

++Non Periodic Transmit FIFO/Queue Status Register (Read Only). ++

++Offset: 02Ch ++

++Definition at line 104 of file dwc_otg_regs.h. ++

++

++ ++

++
++ ++ ++ ++ ++
volatile uint32_t dwc_otg_core_global_regs::gi2cctl
++
++
++ ++

++I2C Access Register. ++

++Offset: 030h ++

++Definition at line 106 of file dwc_otg_regs.h. ++

++

++ ++

++
++ ++ ++ ++ ++
volatile uint32_t dwc_otg_core_global_regs::gpvndctl
++
++
++ ++

++PHY Vendor Control Register. ++

++Offset: 034h ++

++Definition at line 108 of file dwc_otg_regs.h. ++

++

++ ++

++
++ ++ ++ ++ ++
volatile uint32_t dwc_otg_core_global_regs::ggpio
++
++
++ ++

++General Purpose Input/Output Register. ++

++Offset: 038h ++

++Definition at line 110 of file dwc_otg_regs.h. ++

++

++ ++

++
++ ++ ++ ++ ++
volatile uint32_t dwc_otg_core_global_regs::guid
++
++
++ ++

++User ID Register. ++

++Offset: 03Ch ++

++Definition at line 112 of file dwc_otg_regs.h. ++

++

++ ++

++
++ ++ ++ ++ ++
volatile uint32_t dwc_otg_core_global_regs::gsnpsid
++
++
++ ++

++Synopsys ID Register (Read Only). ++

++Offset: 040h ++

++Definition at line 114 of file dwc_otg_regs.h. ++

++

++ ++

++
++ ++ ++ ++ ++
volatile uint32_t dwc_otg_core_global_regs::ghwcfg1
++
++
++ ++

++User HW Config1 Register (Read Only). ++

++Offset: 044h ++

++Definition at line 116 of file dwc_otg_regs.h. ++

++

++ ++

++
++ ++ ++ ++ ++
volatile uint32_t dwc_otg_core_global_regs::ghwcfg2
++
++
++ ++

++User HW Config2 Register (Read Only). ++

++Offset: 048h ++

++Definition at line 118 of file dwc_otg_regs.h. ++

++

++ ++

++
++ ++ ++ ++ ++
volatile uint32_t dwc_otg_core_global_regs::ghwcfg3
++
++
++ ++

++User HW Config3 Register (Read Only). ++

++Offset: 04Ch ++

++Definition at line 132 of file dwc_otg_regs.h. ++

++

++ ++

++
++ ++ ++ ++ ++
volatile uint32_t dwc_otg_core_global_regs::ghwcfg4
++
++
++ ++

++User HW Config4 Register (Read Only). ++

++Offset: 050h ++

++Definition at line 134 of file dwc_otg_regs.h. ++

++

++ ++

++
++ ++ ++ ++ ++
volatile uint32_t dwc_otg_core_global_regs::hptxfsiz
++
++
++ ++

++Host Periodic Transmit FIFO Size Register. ++

++Offset: 100h ++

++Definition at line 140 of file dwc_otg_regs.h. ++

++

++ ++

++
++ ++ ++ ++ ++
volatile uint32_t dwc_otg_core_global_regs::dptxfsiz_dieptxf[15]
++
++
++ ++

++Device Periodic Transmit FIFO::n Register if dedicated fifos are disabled, otherwise Device Transmit FIFO::n Register. ++

++Offset: 104h + (FIFO_Number-1)*04h, 1 <= FIFO Number <= 15 (1<=n<=15). ++

++Definition at line 144 of file dwc_otg_regs.h. ++

++

++

The documentation for this struct was generated from the following file: ++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__core__if.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__core__if.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,190 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_core_if Struct Reference ++ ++ ++ ++ ++
++
++
++
++

dwc_otg_core_if Struct Reference

The dwc_otg_core_if structure contains information needed to manage the DWC_otg controller acting in either host or device mode. ++More... ++

++#include <dwc_otg_cil.h> ++

++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++

Data Fields

++dwc_otg_core_params_t * core_params
 Parameters that define how the core should be configured.
++dwc_otg_core_global_regs_t * core_global_regs
 Core Global registers starting at offset 000h.
++dwc_otg_dev_if_t * dev_if
 Device-specific information.
++dwc_otg_host_if_t * host_if
 Host-specific information.
++uint32_t snpsid
 Value from SNPSID register.
++uint8_t phy_init_done
++uint8_t srp_success
++uint8_t srp_timer_started
++volatile uint32_t * pcgcctl
 Power and Clock Gating Control Register.
++uint32_t * data_fifo [MAX_EPS_CHANNELS]
 Push/pop addresses for endpoints or host channels.
++uint16_t total_fifo_size
 Total RAM for FIFOs (Bytes).
++uint16_t rx_fifo_size
 Size of Rx FIFO (Bytes).
++uint16_t nperio_tx_fifo_size
 Size of Non-periodic Tx FIFO (Bytes).
++uint8_t dma_enable
 1 if DMA is enabled, 0 otherwise.
++uint8_t dma_desc_enable
 1 if DMA descriptor is enabled, 0 otherwise.
++uint8_t pti_enh_enable
 1 if PTI Enhancement mode is enabled, 0 otherwise.
++uint8_t multiproc_int_enable
 1 if MPI Enhancement mode is enabled, 0 otherwise.
++uint8_t en_multiple_tx_fifo
 1 if dedicated Tx FIFOs are enabled, 0 otherwise.
++uint8_t queuing_high_bandwidth
 Set to 1 if multiple packets of a high-bandwidth transfer is in process of being queued.
++hwcfg1_data_t hwcfg1
 Hardware Configuration -- stored here for convenience.
++hwcfg2_data_t hwcfg2
++hwcfg3_data_t hwcfg3
++hwcfg4_data_t hwcfg4
++hcfg_data_t hcfg
 Host and Device Configuration -- stored here for convenience.
++dcfg_data_t dcfg
++uint8_t op_state
 The operational State, during transations (a_host>>a_peripherial and b_device=>b_host) this may not match the core but allows the software to determine transitions.
uint8_t restart_hcd_on_session_req
 Set to 1 if the HCD needs to be restarted on a session request interrupt.
++dwc_otg_cil_callbacks * hcd_cb
 HCD callbacks.
++dwc_otg_cil_callbacks * pcd_cb
 PCD callbacks.
++uint32_t p_tx_msk
 Device mode Periodic Tx FIFO Mask.
++uint32_t tx_msk
 Device mode Periodic Tx FIFO Mask.
++dwc_workq_t * wq_otg
 Workqueue object used for handling several interrupts.
++dwc_timer_t * wkp_timer
 Timer object used for handling "Wakeup Detected" Interrupt.
++dwc_otg_lx_state_e lx_state
 Lx state of device.
++

Detailed Description

++The dwc_otg_core_if structure contains information needed to manage the DWC_otg controller acting in either host or device mode. ++

++It represents the programming view of the controller as a whole. ++

++ ++

++Definition at line 680 of file dwc_otg_cil.h.

Field Documentation

++ ++
++
++ ++ ++ ++ ++
uint8_t dwc_otg_core_if::restart_hcd_on_session_req
++
++
++ ++

++Set to 1 if the HCD needs to be restarted on a session request interrupt. ++

++This is required if no connector ID status change has occurred since the HCD was last disconnected. ++

++Definition at line 765 of file dwc_otg_cil.h. ++

++

++

The documentation for this struct was generated from the following file: ++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__core__params.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__core__params.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,606 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_core_params Struct Reference ++ ++ ++ ++ ++
++
++
++
++

dwc_otg_core_params Struct Reference

The following parameters may be specified when starting the module. ++More... ++

++#include <dwc_otg_cil.h> ++

++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++

Data Fields

++int32_t opt
int32_t otg_cap
 Specifies the OTG capabilities.
int32_t dma_enable
 Specifies whether to use slave or DMA mode for accessing the data FIFOs.
int32_t dma_desc_enable
 When DMA mode is enabled specifies whether to use address DMA or DMA Descritor mode for accessing the data FIFOs in device mode.
int32_t dma_burst_size
 The DMA Burst size (applicable only for External DMA Mode).
int32_t speed
 Specifies the maximum speed of operation in host and device mode.
int32_t host_support_fs_ls_low_power
 Specifies whether low power mode is supported when attached to a Full Speed or Low Speed device in host mode.
int32_t host_ls_low_power_phy_clk
 Specifies the PHY clock rate in low power mode when connected to a Low Speed device in host mode.
++int32_t enable_dynamic_fifo
 0 - Use cC FIFO size parameters 1 - Allow dynamic FIFO sizing (default)
int32_t data_fifo_size
 Total number of 4-byte words in the data FIFO memory.
int32_t dev_rx_fifo_size
 Number of 4-byte words in the Rx FIFO in device mode when dynamic FIFO sizing is enabled.
int32_t dev_nperio_tx_fifo_size
 Number of 4-byte words in the non-periodic Tx FIFO in device mode when dynamic FIFO sizing is enabled.
uint32_t dev_perio_tx_fifo_size [MAX_PERIO_FIFOS]
 Number of 4-byte words in each of the periodic Tx FIFOs in device mode when dynamic FIFO sizing is enabled.
int32_t host_rx_fifo_size
 Number of 4-byte words in the Rx FIFO in host mode when dynamic FIFO sizing is enabled.
int32_t host_nperio_tx_fifo_size
 Number of 4-byte words in the non-periodic Tx FIFO in host mode when Dynamic FIFO sizing is enabled in the core.
int32_t host_perio_tx_fifo_size
 Number of 4-byte words in the host periodic Tx FIFO when dynamic FIFO sizing is enabled.
int32_t max_transfer_size
 The maximum transfer size supported in bytes.
int32_t max_packet_count
 The maximum number of packets in a transfer.
int32_t host_channels
 The number of host channel registers to use.
int32_t dev_endpoints
 The number of endpoints in addition to EP0 available for device mode operations.
int32_t phy_type
 Specifies the type of PHY interface to use.
int32_t phy_utmi_width
 Specifies the UTMI+ Data Width.
int32_t phy_ulpi_ddr
 Specifies whether the ULPI operates at double or single data rate.
++int32_t phy_ulpi_ext_vbus
 Specifies whether to use the internal or external supply to drive the vbus with a ULPI phy.
int32_t i2c_enable
 Specifies whether to use the I2Cinterface for full speed PHY.
++int32_t ulpi_fs_ls
++int32_t ts_dline
++int32_t en_multiple_tx_fifo
 Specifies whether dedicated transmit FIFOs are enabled for non periodic IN endpoints in device mode 0 - No 1 - Yes.
uint32_t dev_tx_fifo_size [MAX_TX_FIFOS]
 Number of 4-byte words in each of the Tx FIFOs in device mode when dynamic FIFO sizing is enabled.
++uint32_t thr_ctl
 Thresholding enable flag- bit 0 - enable non-ISO Tx thresholding bit 1 - enable ISO Tx thresholding bit 2 - enable Rx thresholding.
++uint32_t tx_thr_length
 Thresholding length for Tx FIFOs in 32 bit DWORDs.
++uint32_t rx_thr_length
 Thresholding length for Rx FIFOs in 32 bit DWORDs.
++int32_t lpm_enable
 Specifies whether LPM (Link Power Management) support is enabled.
++int32_t pti_enable
 Per Transfer Interrupt mode enable flag 1 - Enabled 0 - Disabled.
++int32_t mpi_enable
 Multi Processor Interrupt mode enable flag 1 - Enabled 0 - Disabled.
++int32_t ic_usb_cap
 IS_USB Capability 1 - Enabled 0 - Disabled.
++int32_t ahb_thr_ratio
 AHB Threshold Ratio 2'b00 AHB Threshold = MAC Threshold 2'b01 AHB Threshold = 1/2 MAC Threshold 2'b10 AHB Threshold = 1/4 MAC Threshold 2'b11 AHB Threshold = 1/8 MAC Threshold.
++

Detailed Description

++The following parameters may be specified when starting the module. ++

++These parameters define how the DWC_otg controller should be configured. ++

++ ++

++Definition at line 401 of file dwc_otg_cil.h.

Field Documentation

++ ++
++
++ ++ ++ ++ ++
int32_t dwc_otg_core_params::otg_cap
++
++
++ ++

++Specifies the OTG capabilities. ++

++The driver will automatically detect the value for this parameter if none is specified. 0 - HNP and SRP capable (default) 1 - SRP Only capable 2 - No HNP/SRP capable ++

++Definition at line 411 of file dwc_otg_cil.h. ++

++

++ ++

++
++ ++ ++ ++ ++
int32_t dwc_otg_core_params::dma_enable
++
++
++ ++

++Specifies whether to use slave or DMA mode for accessing the data FIFOs. ++

++The driver will automatically detect the value for this parameter if none is specified. 0 - Slave 1 - DMA (default, if available) ++

++Definition at line 420 of file dwc_otg_cil.h. ++

++

++ ++

++
++ ++ ++ ++ ++
int32_t dwc_otg_core_params::dma_desc_enable
++
++
++ ++

++When DMA mode is enabled specifies whether to use address DMA or DMA Descritor mode for accessing the data FIFOs in device mode. ++

++The driver will automatically detect the value for this parameter if none is specified. 0 - address DMA 1 - DMA Descriptor(default, if available) ++

++Definition at line 429 of file dwc_otg_cil.h. ++

++

++ ++

++
++ ++ ++ ++ ++
int32_t dwc_otg_core_params::dma_burst_size
++
++
++ ++

++The DMA Burst size (applicable only for External DMA Mode). ++

++1, 4, 8 16, 32, 64, 128, 256 (default 32) ++

++Definition at line 433 of file dwc_otg_cil.h. ++

++

++ ++

++
++ ++ ++ ++ ++
int32_t dwc_otg_core_params::speed
++
++
++ ++

++Specifies the maximum speed of operation in host and device mode. ++

++The actual speed depends on the speed of the attached device and the value of phy_type. The actual speed depends on the speed of the attached device. 0 - High Speed (default) 1 - Full Speed ++

++Definition at line 443 of file dwc_otg_cil.h. ++

++

++ ++

++
++ ++ ++ ++ ++
int32_t dwc_otg_core_params::host_support_fs_ls_low_power
++
++
++ ++

++Specifies whether low power mode is supported when attached to a Full Speed or Low Speed device in host mode. ++

++0 - Don't support low power mode (default) 1 - Support low power mode ++

++Definition at line 449 of file dwc_otg_cil.h. ++

++

++ ++

++
++ ++ ++ ++ ++
int32_t dwc_otg_core_params::host_ls_low_power_phy_clk
++
++
++ ++

++Specifies the PHY clock rate in low power mode when connected to a Low Speed device in host mode. ++

++This parameter is applicable only if HOST_SUPPORT_FS_LS_LOW_POWER is enabled. If PHY_TYPE is set to FS then defaults to 6 MHZ otherwise 48 MHZ.

++0 - 48 MHz 1 - 6 MHz ++

++Definition at line 459 of file dwc_otg_cil.h. ++

++

++ ++

++
++ ++ ++ ++ ++
int32_t dwc_otg_core_params::data_fifo_size
++
++
++ ++

++Total number of 4-byte words in the data FIFO memory. ++

++This memory includes the Rx FIFO, non-periodic Tx FIFO, and periodic Tx FIFOs. 32 to 32768 (default 8192) Note: The total FIFO memory depth in the FPGA configuration is 8192. ++

++Definition at line 473 of file dwc_otg_cil.h. ++

++

++ ++

++
++ ++ ++ ++ ++
int32_t dwc_otg_core_params::dev_rx_fifo_size
++
++
++ ++

++Number of 4-byte words in the Rx FIFO in device mode when dynamic FIFO sizing is enabled. ++

++16 to 32768 (default 1064) ++

++Definition at line 479 of file dwc_otg_cil.h. ++

++

++ ++

++
++ ++ ++ ++ ++
int32_t dwc_otg_core_params::dev_nperio_tx_fifo_size
++
++
++ ++

++Number of 4-byte words in the non-periodic Tx FIFO in device mode when dynamic FIFO sizing is enabled. ++

++16 to 32768 (default 1024) ++

++Definition at line 485 of file dwc_otg_cil.h. ++

++

++ ++

++
++ ++ ++ ++ ++
uint32_t dwc_otg_core_params::dev_perio_tx_fifo_size[MAX_PERIO_FIFOS]
++
++
++ ++

++Number of 4-byte words in each of the periodic Tx FIFOs in device mode when dynamic FIFO sizing is enabled. ++

++4 to 768 (default 256) ++

++Definition at line 491 of file dwc_otg_cil.h. ++

++

++ ++

++
++ ++ ++ ++ ++
int32_t dwc_otg_core_params::host_rx_fifo_size
++
++
++ ++

++Number of 4-byte words in the Rx FIFO in host mode when dynamic FIFO sizing is enabled. ++

++16 to 32768 (default 1024) ++

++Definition at line 497 of file dwc_otg_cil.h. ++

++

++ ++

++
++ ++ ++ ++ ++
int32_t dwc_otg_core_params::host_nperio_tx_fifo_size
++
++
++ ++

++Number of 4-byte words in the non-periodic Tx FIFO in host mode when Dynamic FIFO sizing is enabled in the core. ++

++16 to 32768 (default 1024) ++

++Definition at line 503 of file dwc_otg_cil.h. ++

++

++ ++

++
++ ++ ++ ++ ++
int32_t dwc_otg_core_params::host_perio_tx_fifo_size
++
++
++ ++

++Number of 4-byte words in the host periodic Tx FIFO when dynamic FIFO sizing is enabled. ++

++16 to 32768 (default 1024) ++

++Definition at line 509 of file dwc_otg_cil.h. ++

++

++ ++

++
++ ++ ++ ++ ++
int32_t dwc_otg_core_params::max_transfer_size
++
++
++ ++

++The maximum transfer size supported in bytes. ++

++2047 to 65,535 (default 65,535) ++

++Definition at line 514 of file dwc_otg_cil.h. ++

++

++ ++

++
++ ++ ++ ++ ++
int32_t dwc_otg_core_params::max_packet_count
++
++
++ ++

++The maximum number of packets in a transfer. ++

++15 to 511 (default 511) ++

++Definition at line 519 of file dwc_otg_cil.h. ++

++

++ ++

++
++ ++ ++ ++ ++
int32_t dwc_otg_core_params::host_channels
++
++
++ ++

++The number of host channel registers to use. ++

++1 to 16 (default 12) Note: The FPGA configuration supports a maximum of 12 host channels. ++

++Definition at line 525 of file dwc_otg_cil.h. ++

++

++ ++

++
++ ++ ++ ++ ++
int32_t dwc_otg_core_params::dev_endpoints
++
++
++ ++

++The number of endpoints in addition to EP0 available for device mode operations. ++

++1 to 15 (default 6 IN and OUT) Note: The FPGA configuration supports a maximum of 6 IN and OUT endpoints in addition to EP0. ++

++Definition at line 533 of file dwc_otg_cil.h. ++

++

++ ++

++
++ ++ ++ ++ ++
int32_t dwc_otg_core_params::phy_type
++
++
++ ++

++Specifies the type of PHY interface to use. ++

++By default, the driver will automatically detect the phy_type.

++0 - Full Speed PHY 1 - UTMI+ (default) 2 - ULPI ++

++Definition at line 543 of file dwc_otg_cil.h. ++

++

++ ++

++
++ ++ ++ ++ ++
int32_t dwc_otg_core_params::phy_utmi_width
++
++
++ ++

++Specifies the UTMI+ Data Width. ++

++This parameter is applicable for a PHY_TYPE of UTMI+ or ULPI. (For a ULPI PHY_TYPE, this parameter indicates the data width between the MAC and the ULPI Wrapper.) Also, this parameter is applicable only if the OTG_HSPHY_WIDTH cC parameter was set to "8 and 16 bits", meaning that the core has been configured to work at either data path width.

++8 or 16 bits (default 16) ++

++Definition at line 556 of file dwc_otg_cil.h. ++

++

++ ++

++
++ ++ ++ ++ ++
int32_t dwc_otg_core_params::phy_ulpi_ddr
++
++
++ ++

++Specifies whether the ULPI operates at double or single data rate. ++

++This parameter is only applicable if PHY_TYPE is ULPI.

++0 - single data rate ULPI interface with 8 bit wide data bus (default) 1 - double data rate ULPI interface with 4 bit wide data bus ++

++Definition at line 568 of file dwc_otg_cil.h. ++

++

++ ++

++
++ ++ ++ ++ ++
int32_t dwc_otg_core_params::i2c_enable
++
++
++ ++

++Specifies whether to use the I2Cinterface for full speed PHY. ++

++This parameter is only applicable if PHY_TYPE is FS. 0 - No (default) 1 - Yes ++

++Definition at line 582 of file dwc_otg_cil.h. ++

++

++ ++

++
++ ++ ++ ++ ++
uint32_t dwc_otg_core_params::dev_tx_fifo_size[MAX_TX_FIFOS]
++
++
++ ++

++Number of 4-byte words in each of the Tx FIFOs in device mode when dynamic FIFO sizing is enabled. ++

++4 to 768 (default 256) ++

++Definition at line 600 of file dwc_otg_cil.h. ++

++

++

The documentation for this struct was generated from the following file: ++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__dev__dma__desc.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__dev__dma__desc.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,50 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_dev_dma_desc Struct Reference ++ ++ ++ ++ ++
++
++
++
++

dwc_otg_dev_dma_desc Struct Reference

DMA Descriptor structure. ++More... ++

++#include <dwc_otg_regs.h> ++

++ ++ ++ ++ ++ ++ ++ ++ ++ ++

Data Fields

++dev_dma_desc_sts_t status
 DMA Descriptor status quadlet.
++uint32_t buf
 DMA Descriptor data buffer pointer.
++

Detailed Description

++DMA Descriptor structure. ++

++DMA Descriptor structure contains two quadlets: Status quadlet and Data buffer pointer. ++

++ ++

++Definition at line 1542 of file dwc_otg_regs.h.

The documentation for this struct was generated from the following file: ++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__dev__global__regs.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__dev__global__regs.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,441 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_dev_global_regs Struct Reference ++ ++ ++ ++ ++
++
++
++
++

dwc_otg_dev_global_regs Struct Reference

Device Global Registers. ++More... ++

++#include <dwc_otg_regs.h> ++

++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++

Data Fields

volatile uint32_t dcfg
 Device Configuration Register.
volatile uint32_t dctl
 Device Control Register.
volatile uint32_t dsts
 Device Status Register (Read Only).
uint32_t unused
 Reserved.
volatile uint32_t diepmsk
 Device IN Endpoint Common Interrupt Mask Register.
volatile uint32_t doepmsk
 Device OUT Endpoint Common Interrupt Mask Register.
volatile uint32_t daint
 Device All Endpoints Interrupt Register.
volatile uint32_t daintmsk
 Device All Endpoints Interrupt Mask Register.
volatile uint32_t dtknqr1
 Device IN Token Queue Read Register-1 (Read Only).
volatile uint32_t dtknqr2
 Device IN Token Queue Read Register-2 (Read Only).
volatile uint32_t dvbusdis
 Device VBUS discharge Register.
volatile uint32_t dvbuspulse
 Device VBUS Pulse Register.
volatile uint32_t dtknqr3_dthrctl
 Device IN Token Queue Read Register-3 (Read Only).
volatile uint32_t dtknqr4_fifoemptymsk
 Device IN Token Queue Read Register-4 (Read Only).
volatile uint32_t deachint
 Device Each Endpoint Interrupt Register (Read Only).
volatile uint32_t deachintmsk
 Device Each Endpoint Interrupt mask Register (Read/Write).
volatile uint32_t diepeachintmsk [MAX_EPS_CHANNELS]
 Device Each In Endpoint Interrupt mask Register (Read/Write).
volatile uint32_t doepeachintmsk [MAX_EPS_CHANNELS]
 Device Each Out Endpoint Interrupt mask Register (Read/Write).
++

Detailed Description

++Device Global Registers. ++

++Offsets 800h-BFFh

++The following structures define the size and relative field offsets for the Device Mode Registers.

++These registers are visible only in Device mode and must not be accessed in Host mode, as the results are unknown. ++

++ ++

++Definition at line 865 of file dwc_otg_regs.h.

Field Documentation

++ ++
++
++ ++ ++ ++ ++
volatile uint32_t dwc_otg_dev_global_regs::dcfg
++
++
++ ++

++Device Configuration Register. ++

++Offset 800h ++

++Definition at line 867 of file dwc_otg_regs.h. ++

++

++ ++

++
++ ++ ++ ++ ++
volatile uint32_t dwc_otg_dev_global_regs::dctl
++
++
++ ++

++Device Control Register. ++

++Offset: 804h ++

++Definition at line 869 of file dwc_otg_regs.h. ++

++

++ ++

++
++ ++ ++ ++ ++
volatile uint32_t dwc_otg_dev_global_regs::dsts
++
++
++ ++

++Device Status Register (Read Only). ++

++Offset: 808h ++

++Definition at line 871 of file dwc_otg_regs.h. ++

++

++ ++

++
++ ++ ++ ++ ++
uint32_t dwc_otg_dev_global_regs::unused
++
++
++ ++

++Reserved. ++

++Offset: 80Ch ++

++Definition at line 873 of file dwc_otg_regs.h. ++

++

++ ++

++
++ ++ ++ ++ ++
volatile uint32_t dwc_otg_dev_global_regs::diepmsk
++
++
++ ++

++Device IN Endpoint Common Interrupt Mask Register. ++

++Offset: 810h ++

++Definition at line 876 of file dwc_otg_regs.h. ++

++

++ ++

++
++ ++ ++ ++ ++
volatile uint32_t dwc_otg_dev_global_regs::doepmsk
++
++
++ ++

++Device OUT Endpoint Common Interrupt Mask Register. ++

++Offset: 814h ++

++Definition at line 879 of file dwc_otg_regs.h. ++

++

++ ++

++
++ ++ ++ ++ ++
volatile uint32_t dwc_otg_dev_global_regs::daint
++
++
++ ++

++Device All Endpoints Interrupt Register. ++

++Offset: 818h ++

++Definition at line 881 of file dwc_otg_regs.h. ++

++

++ ++

++
++ ++ ++ ++ ++
volatile uint32_t dwc_otg_dev_global_regs::daintmsk
++
++
++ ++

++Device All Endpoints Interrupt Mask Register. ++

++Offset: 81Ch ++

++Definition at line 884 of file dwc_otg_regs.h. ++

++

++ ++

++
++ ++ ++ ++ ++
volatile uint32_t dwc_otg_dev_global_regs::dtknqr1
++
++
++ ++

++Device IN Token Queue Read Register-1 (Read Only). ++

++Offset: 820h ++

++Definition at line 887 of file dwc_otg_regs.h. ++

++

++ ++

++
++ ++ ++ ++ ++
volatile uint32_t dwc_otg_dev_global_regs::dtknqr2
++
++
++ ++

++Device IN Token Queue Read Register-2 (Read Only). ++

++Offset: 824h ++

++Definition at line 890 of file dwc_otg_regs.h. ++

++

++ ++

++
++ ++ ++ ++ ++
volatile uint32_t dwc_otg_dev_global_regs::dvbusdis
++
++
++ ++

++Device VBUS discharge Register. ++

++Offset: 828h ++

++Definition at line 892 of file dwc_otg_regs.h. ++

++

++ ++

++
++ ++ ++ ++ ++
volatile uint32_t dwc_otg_dev_global_regs::dvbuspulse
++
++
++ ++

++Device VBUS Pulse Register. ++

++Offset: 82Ch ++

++Definition at line 894 of file dwc_otg_regs.h. ++

++

++ ++

++
++ ++ ++ ++ ++
volatile uint32_t dwc_otg_dev_global_regs::dtknqr3_dthrctl
++
++
++ ++

++Device IN Token Queue Read Register-3 (Read Only). ++

++/ Device Thresholding control register (Read/Write) Offset: 830h ++

++Definition at line 898 of file dwc_otg_regs.h. ++

++

++ ++

++
++ ++ ++ ++ ++
volatile uint32_t dwc_otg_dev_global_regs::dtknqr4_fifoemptymsk
++
++
++ ++

++Device IN Token Queue Read Register-4 (Read Only). ++

++/ Device IN EPs empty Inr. Mask Register (Read/Write) Offset: 834h ++

++Definition at line 902 of file dwc_otg_regs.h. ++

++

++ ++

++
++ ++ ++ ++ ++
volatile uint32_t dwc_otg_dev_global_regs::deachint
++
++
++ ++

++Device Each Endpoint Interrupt Register (Read Only). ++

++/ Offset: 838h ++

++Definition at line 905 of file dwc_otg_regs.h. ++

++

++ ++

++
++ ++ ++ ++ ++
volatile uint32_t dwc_otg_dev_global_regs::deachintmsk
++
++
++ ++

++Device Each Endpoint Interrupt mask Register (Read/Write). ++

++/ Offset: 83Ch ++

++Definition at line 908 of file dwc_otg_regs.h. ++

++

++ ++

++
++ ++ ++ ++ ++
volatile uint32_t dwc_otg_dev_global_regs::diepeachintmsk[MAX_EPS_CHANNELS]
++
++
++ ++

++Device Each In Endpoint Interrupt mask Register (Read/Write). ++

++/ Offset: 840h ++

++Definition at line 911 of file dwc_otg_regs.h. ++

++

++ ++

++
++ ++ ++ ++ ++
volatile uint32_t dwc_otg_dev_global_regs::doepeachintmsk[MAX_EPS_CHANNELS]
++
++
++ ++

++Device Each Out Endpoint Interrupt mask Register (Read/Write). ++

++/ Offset: 880h ++

++Definition at line 914 of file dwc_otg_regs.h. ++

++

++

The documentation for this struct was generated from the following file: ++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__dev__if.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__dev__if.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,142 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_dev_if Struct Reference ++ ++ ++ ++ ++
++
++
++
++

dwc_otg_dev_if Struct Reference

The dwc_otg_dev_if structure contains information needed to manage the DWC_otg controller acting in device mode. ++More... ++

++#include <dwc_otg_regs.h> ++

++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++

Data Fields

dwc_otg_device_global_regs_t * dev_global_regs
 Pointer to device Global registers.
++dwc_otg_dev_in_ep_regs_t * in_ep_regs [MAX_EPS_CHANNELS]
 Device Logical IN Endpoint-Specific Registers 900h-AFCh.
++dwc_otg_dev_out_ep_regs_t * out_ep_regs [MAX_EPS_CHANNELS]
 Device Logical OUT Endpoint-Specific Registers B00h-CFCh.
++uint8_t speed
 Device Speed 0: Unknown, 1: LS, 2:FS, 3: HS.
++uint8_t num_in_eps
 Number # of Tx EP range: 0-15 exept ep0.
++uint8_t num_out_eps
 Number # of Rx EP range: 0-15 exept ep 0.
++uint16_t perio_tx_fifo_size [MAX_PERIO_FIFOS]
 Size of periodic FIFOs (Bytes).
++uint16_t tx_fifo_size [MAX_TX_FIFOS]
 Size of Tx FIFOs (Bytes).
++uint16_t rx_thr_en
 Thresholding enable flags and length varaiables.
++uint16_t iso_tx_thr_en
++uint16_t non_iso_tx_thr_en
++uint16_t rx_thr_length
++uint16_t tx_thr_length
++dwc_dma_t dma_setup_desc_addr [2]
 2 descriptors for SETUP packets
++dwc_otg_dev_dma_desc_t * setup_desc_addr [2]
++dwc_otg_dev_dma_desc_t * psetup
 Pointer to Descriptor with latest SETUP packet.
++uint32_t setup_desc_index
 Index of current SETUP handler descriptor.
++dwc_dma_t dma_in_desc_addr
 Descriptor for Data In or Status In phases.
++dwc_otg_dev_dma_desc_t * in_desc_addr
++dwc_dma_t dma_out_desc_addr
 Descriptor for Data Out or Status Out phases.
++dwc_otg_dev_dma_desc_t * out_desc_addr
++uint32_t spd
 Setup Packet Detected - if set clear NAK when queueing.
++

Detailed Description

++The dwc_otg_dev_if structure contains information needed to manage the DWC_otg controller acting in device mode. ++

++It represents the programming view of the device-specific aspects of the controller. ++

++ ++

++Definition at line 1554 of file dwc_otg_regs.h.

Field Documentation

++ ++
++
++ ++ ++ ++ ++
dwc_otg_device_global_regs_t* dwc_otg_dev_if::dev_global_regs
++
++
++ ++

++Pointer to device Global registers. ++

++Device Global Registers starting at offset 800h ++

++Definition at line 1558 of file dwc_otg_regs.h. ++

++

++

The documentation for this struct was generated from the following file: ++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__dev__in__ep__regs.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__dev__in__ep__regs.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,221 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_dev_in_ep_regs Struct Reference ++ ++ ++ ++ ++
++
++
++
++

dwc_otg_dev_in_ep_regs Struct Reference

Device Logical IN Endpoint-Specific Registers. ++More... ++

++#include <dwc_otg_regs.h> ++

++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++

Data Fields

volatile uint32_t diepctl
 Device IN Endpoint Control Register.
uint32_t reserved04
 Reserved.
volatile uint32_t diepint
 Device IN Endpoint Interrupt Register.
uint32_t reserved0C
 Reserved.
volatile uint32_t dieptsiz
 Device IN Endpoint Transfer Size Register.
volatile uint32_t diepdma
 Device IN Endpoint DMA Address Register.
volatile uint32_t dtxfsts
 Device IN Endpoint Transmit FIFO Status Register.
volatile uint32_t diepdmab
 Device IN Endpoint DMA Buffer Register.
++

Detailed Description

++Device Logical IN Endpoint-Specific Registers. ++

++Offsets 900h-AFCh

++There will be one set of endpoint registers per logical endpoint implemented.

++These registers are visible only in Device mode and must not be accessed in Host mode, as the results are unknown. ++

++ ++

++Definition at line 1239 of file dwc_otg_regs.h.

Field Documentation

++ ++
++
++ ++ ++ ++ ++
volatile uint32_t dwc_otg_dev_in_ep_regs::diepctl
++
++
++ ++

++Device IN Endpoint Control Register. ++

++Offset:900h + (ep_num * 20h) + 00h ++

++Definition at line 1242 of file dwc_otg_regs.h. ++

++

++ ++

++
++ ++ ++ ++ ++
uint32_t dwc_otg_dev_in_ep_regs::reserved04
++
++
++ ++

++Reserved. ++

++Offset:900h + (ep_num * 20h) + 04h ++

++Definition at line 1244 of file dwc_otg_regs.h. ++

++

++ ++

++
++ ++ ++ ++ ++
volatile uint32_t dwc_otg_dev_in_ep_regs::diepint
++
++
++ ++

++Device IN Endpoint Interrupt Register. ++

++Offset:900h + (ep_num * 20h) + 08h ++

++Definition at line 1247 of file dwc_otg_regs.h. ++

++

++ ++

++
++ ++ ++ ++ ++
uint32_t dwc_otg_dev_in_ep_regs::reserved0C
++
++
++ ++

++Reserved. ++

++Offset:900h + (ep_num * 20h) + 0Ch ++

++Definition at line 1249 of file dwc_otg_regs.h. ++

++

++ ++

++
++ ++ ++ ++ ++
volatile uint32_t dwc_otg_dev_in_ep_regs::dieptsiz
++
++
++ ++

++Device IN Endpoint Transfer Size Register. ++

++Offset:900h + (ep_num * 20h) + 10h ++

++Definition at line 1252 of file dwc_otg_regs.h. ++

++

++ ++

++
++ ++ ++ ++ ++
volatile uint32_t dwc_otg_dev_in_ep_regs::diepdma
++
++
++ ++

++Device IN Endpoint DMA Address Register. ++

++Offset:900h + (ep_num * 20h) + 14h ++

++Definition at line 1255 of file dwc_otg_regs.h. ++

++

++ ++

++
++ ++ ++ ++ ++
volatile uint32_t dwc_otg_dev_in_ep_regs::dtxfsts
++
++
++ ++

++Device IN Endpoint Transmit FIFO Status Register. ++

++Offset:900h + (ep_num * 20h) + 18h ++

++Definition at line 1258 of file dwc_otg_regs.h. ++

++

++ ++

++
++ ++ ++ ++ ++
volatile uint32_t dwc_otg_dev_in_ep_regs::diepdmab
++
++
++ ++

++Device IN Endpoint DMA Buffer Register. ++

++Offset:900h + (ep_num * 20h) + 1Ch ++

++Definition at line 1261 of file dwc_otg_regs.h. ++

++

++

The documentation for this struct was generated from the following file: ++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__dev__out__ep__regs.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__dev__out__ep__regs.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,221 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_dev_out_ep_regs Struct Reference ++ ++ ++ ++ ++
++
++
++
++

dwc_otg_dev_out_ep_regs Struct Reference

Device Logical OUT Endpoint-Specific Registers. ++More... ++

++#include <dwc_otg_regs.h> ++

++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++

Data Fields

volatile uint32_t doepctl
 Device OUT Endpoint Control Register.
volatile uint32_t doepfn
 Device OUT Endpoint Frame number Register.
volatile uint32_t doepint
 Device OUT Endpoint Interrupt Register.
uint32_t reserved0C
 Reserved.
volatile uint32_t doeptsiz
 Device OUT Endpoint Transfer Size Register.
volatile uint32_t doepdma
 Device OUT Endpoint DMA Address Register.
uint32_t unused
 Reserved.
uint32_t doepdmab
 Device OUT Endpoint DMA Buffer Register.
++

Detailed Description

++Device Logical OUT Endpoint-Specific Registers. ++

++Offsets: B00h-CFCh

++There will be one set of endpoint registers per logical endpoint implemented.

++These registers are visible only in Device mode and must not be accessed in Host mode, as the results are unknown. ++

++ ++

++Definition at line 1274 of file dwc_otg_regs.h.

Field Documentation

++ ++
++
++ ++ ++ ++ ++
volatile uint32_t dwc_otg_dev_out_ep_regs::doepctl
++
++
++ ++

++Device OUT Endpoint Control Register. ++

++Offset:B00h + (ep_num * 20h) + 00h ++

++Definition at line 1277 of file dwc_otg_regs.h. ++

++

++ ++

++
++ ++ ++ ++ ++
volatile uint32_t dwc_otg_dev_out_ep_regs::doepfn
++
++
++ ++

++Device OUT Endpoint Frame number Register. ++

++Offset: B00h + (ep_num * 20h) + 04h ++

++Definition at line 1280 of file dwc_otg_regs.h. ++

++

++ ++

++
++ ++ ++ ++ ++
volatile uint32_t dwc_otg_dev_out_ep_regs::doepint
++
++
++ ++

++Device OUT Endpoint Interrupt Register. ++

++Offset:B00h + (ep_num * 20h) + 08h ++

++Definition at line 1283 of file dwc_otg_regs.h. ++

++

++ ++

++
++ ++ ++ ++ ++
uint32_t dwc_otg_dev_out_ep_regs::reserved0C
++
++
++ ++

++Reserved. ++

++Offset:B00h + (ep_num * 20h) + 0Ch ++

++Definition at line 1285 of file dwc_otg_regs.h. ++

++

++ ++

++
++ ++ ++ ++ ++
volatile uint32_t dwc_otg_dev_out_ep_regs::doeptsiz
++
++
++ ++

++Device OUT Endpoint Transfer Size Register. ++

++Offset: B00h + (ep_num * 20h) + 10h ++

++Definition at line 1288 of file dwc_otg_regs.h. ++

++

++ ++

++
++ ++ ++ ++ ++
volatile uint32_t dwc_otg_dev_out_ep_regs::doepdma
++
++
++ ++

++Device OUT Endpoint DMA Address Register. ++

++Offset:B00h + (ep_num * 20h) + 14h ++

++Definition at line 1291 of file dwc_otg_regs.h. ++

++

++ ++

++
++ ++ ++ ++ ++
uint32_t dwc_otg_dev_out_ep_regs::unused
++
++
++ ++

++Reserved. ++

++Offset:B00h + * (ep_num * 20h) + 18h ++

++Definition at line 1293 of file dwc_otg_regs.h. ++

++

++ ++

++
++ ++ ++ ++ ++
uint32_t dwc_otg_dev_out_ep_regs::doepdmab
++
++
++ ++

++Device OUT Endpoint DMA Buffer Register. ++

++Offset:B00h + (ep_num * 20h) + 1Ch ++

++Definition at line 1296 of file dwc_otg_regs.h. ++

++

++

The documentation for this struct was generated from the following file: ++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__device.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__device.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,64 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_device Struct Reference ++ ++ ++ ++ ++
++
++
++
++

dwc_otg_device Struct Reference

This structure is a wrapper that encapsulates the driver components used to manage a single DWC_otg controller. ++More... ++

++#include <dwc_otg_driver.h> ++

++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++

Data Fields

++void * base
 Base address returned from ioremap().
++dwc_otg_core_if_t * core_if
 Pointer to the core interface structure.
++uint32_t reg_offset
 Register offset for Diagnostic API.
++dwc_otg_pcd * pcd
 Pointer to the PCD structure.
++dwc_otg_hcd * hcd
 Pointer to the HCD structure.
++uint8_t common_irq_installed
 Flag to indicate whether the common IRQ handler is installed.
++

Detailed Description

++This structure is a wrapper that encapsulates the driver components used to manage a single DWC_otg controller. ++

++ ++

++Definition at line 56 of file dwc_otg_driver.h.

The documentation for this struct was generated from the following file: ++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__driver__module__params.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__driver__module__params.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,146 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_driver_module_params Struct Reference ++ ++ ++ ++ ++
++
++
++
++

dwc_otg_driver_module_params Struct Reference

++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++

Data Fields

++int32_t opt
++int32_t otg_cap
++int32_t dma_enable
++int32_t dma_desc_enable
++int32_t dma_burst_size
++int32_t speed
++int32_t host_support_fs_ls_low_power
++int32_t host_ls_low_power_phy_clk
++int32_t enable_dynamic_fifo
++int32_t data_fifo_size
++int32_t dev_rx_fifo_size
++int32_t dev_nperio_tx_fifo_size
++uint32_t dev_perio_tx_fifo_size [MAX_PERIO_FIFOS]
++int32_t host_rx_fifo_size
++int32_t host_nperio_tx_fifo_size
++int32_t host_perio_tx_fifo_size
++int32_t max_transfer_size
++int32_t max_packet_count
++int32_t host_channels
++int32_t dev_endpoints
++int32_t phy_type
++int32_t phy_utmi_width
++int32_t phy_ulpi_ddr
++int32_t phy_ulpi_ext_vbus
++int32_t i2c_enable
++int32_t ulpi_fs_ls
++int32_t ts_dline
++int32_t en_multiple_tx_fifo
++uint32_t dev_tx_fifo_size [MAX_TX_FIFOS]
++uint32_t thr_ctl
++uint32_t tx_thr_length
++uint32_t rx_thr_length
++int32_t pti_enable
++int32_t mpi_enable
++int32_t lpm_enable
++int32_t ic_usb_cap
++int32_t ahb_thr_ratio
++

Detailed Description

++ ++

++ ++

++Definition at line 120 of file dwc_otg_driver.c.

The documentation for this struct was generated from the following file: ++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__hc__regs.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__hc__regs.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,200 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_hc_regs Struct Reference ++ ++ ++ ++ ++
++
++
++
++

dwc_otg_hc_regs Struct Reference

Host Channel Specific Registers. ++More... ++

++#include <dwc_otg_regs.h> ++

++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++

Data Fields

volatile uint32_t hcchar
 Host Channel 0 Characteristic Register.
volatile uint32_t hcsplt
 Host Channel 0 Split Control Register.
volatile uint32_t hcint
 Host Channel 0 Interrupt Register.
volatile uint32_t hcintmsk
 Host Channel 0 Interrupt Mask Register.
volatile uint32_t hctsiz
 Host Channel 0 Transfer Size Register.
volatile uint32_t hcdma
 Host Channel 0 DMA Address Register.
++volatile uint32_t reserved
volatile uint32_t hcdmab
 Host Channel 0 DMA Buffer Address Register.
++

Detailed Description

++Host Channel Specific Registers. ++

++500h-5FCh ++

++ ++

++Definition at line 1838 of file dwc_otg_regs.h.

Field Documentation

++ ++
++
++ ++ ++ ++ ++
volatile uint32_t dwc_otg_hc_regs::hcchar
++
++
++ ++

++Host Channel 0 Characteristic Register. ++

++Offset: 500h + (chan_num * 20h) + 00h ++

++Definition at line 1841 of file dwc_otg_regs.h. ++

++

++ ++

++
++ ++ ++ ++ ++
volatile uint32_t dwc_otg_hc_regs::hcsplt
++
++
++ ++

++Host Channel 0 Split Control Register. ++

++Offset: 500h + (chan_num * 20h) + 04h ++

++Definition at line 1843 of file dwc_otg_regs.h. ++

++

++ ++

++
++ ++ ++ ++ ++
volatile uint32_t dwc_otg_hc_regs::hcint
++
++
++ ++

++Host Channel 0 Interrupt Register. ++

++Offset: 500h + (chan_num * 20h) + 08h ++

++Definition at line 1845 of file dwc_otg_regs.h. ++

++

++ ++

++
++ ++ ++ ++ ++
volatile uint32_t dwc_otg_hc_regs::hcintmsk
++
++
++ ++

++Host Channel 0 Interrupt Mask Register. ++

++Offset: 500h + (chan_num * 20h) + 0Ch ++

++Definition at line 1847 of file dwc_otg_regs.h. ++

++

++ ++

++
++ ++ ++ ++ ++
volatile uint32_t dwc_otg_hc_regs::hctsiz
++
++
++ ++

++Host Channel 0 Transfer Size Register. ++

++Offset: 500h + (chan_num * 20h) + 10h ++

++Definition at line 1849 of file dwc_otg_regs.h. ++

++

++ ++

++
++ ++ ++ ++ ++
volatile uint32_t dwc_otg_hc_regs::hcdma
++
++
++ ++

++Host Channel 0 DMA Address Register. ++

++Offset: 500h + (chan_num * 20h) + 14h ++

++Definition at line 1851 of file dwc_otg_regs.h. ++

++

++ ++

++
++ ++ ++ ++ ++
volatile uint32_t dwc_otg_hc_regs::hcdmab
++
++
++ ++

++Host Channel 0 DMA Buffer Address Register. ++

++Offset: 500h + (chan_num * 20h) + 1Ch ++

++Definition at line 1854 of file dwc_otg_regs.h. ++

++

++

The documentation for this struct was generated from the following file: ++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__hcd.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__hcd.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,377 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_hcd Struct Reference ++ ++ ++ ++ ++
++
++
++
++

dwc_otg_hcd Struct Reference

This structure holds the state of the HCD, including the non-periodic and periodic schedules. ++More... ++

++#include <dwc_otg_hcd.h> ++

++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++

Data Fields

++dwc_otg_core_if_t * core_if
 DWC OTG Core Interface Layer.
++dwc_otg_hcd_function_ops * fops
 Function HCD driver callbacks.
++dwc_otg_hcd::dwc_otg_hcd_internal_flags flags
 Internal DWC HCD Flags.
dwc_list_link_t non_periodic_sched_inactive
 Inactive items in the non-periodic schedule.
dwc_list_link_t non_periodic_sched_active
 Active items in the non-periodic schedule.
++dwc_list_link_t * non_periodic_qh_ptr
 Pointer to the next Queue Head to process in the active non-periodic schedule.
dwc_list_link_t periodic_sched_inactive
 Inactive items in the periodic schedule.
dwc_list_link_t periodic_sched_ready
 List of periodic QHs that are ready for execution in the next frame, but have not yet been assigned to host channels.
dwc_list_link_t periodic_sched_assigned
 List of periodic QHs to be executed in the next frame that are assigned to host channels.
dwc_list_link_t periodic_sched_queued
 List of periodic QHs that have been queued for execution.
uint16_t periodic_usecs
 Total bandwidth claimed so far for periodic transfers.
uint16_t frame_number
 Frame number read from the core at SOF.
hc_list free_hc_list
 Free host channels in the controller.
int periodic_channels
 Number of host channels assigned to periodic transfers.
++int non_periodic_channels
 Number of host channels assigned to non-periodic transfers.
dwc_hc * hc_ptr_array [MAX_EPS_CHANNELS]
 Array of pointers to the host channel descriptors.
uint8_t * status_buf
 Buffer to use for any data received during the status phase of a control transfer.
++dma_addr_t status_buf_dma
 DMA address for status_buf.
dwc_timer_t * conn_timer
 Connection timer.
++dwc_tasklet_t * reset_tasklet
++dwc_spinlock_t * lock
++void * priv
 Private data that could be used by OS wrapper.
++uint8_t otg_port
++uint32_t * frame_list
 Frame List.
++dma_addr_t frame_list_dma
 Frame List DMA address.

Data Structures

union  dwc_otg_hcd_internal_flags
 Internal DWC HCD Flags. More...
++

Detailed Description

++This structure holds the state of the HCD, including the non-periodic and periodic schedules. ++

++ ++

++Definition at line 372 of file dwc_otg_hcd.h.

Field Documentation

++ ++
++
++ ++ ++ ++ ++
dwc_list_link_t dwc_otg_hcd::non_periodic_sched_inactive
++
++
++ ++

++Inactive items in the non-periodic schedule. ++

++This is a list of Queue Heads. Transfers associated with these Queue Heads are not currently assigned to a host channel. ++

++Definition at line 399 of file dwc_otg_hcd.h. ++

++

++ ++

++
++ ++ ++ ++ ++
dwc_list_link_t dwc_otg_hcd::non_periodic_sched_active
++
++
++ ++

++Active items in the non-periodic schedule. ++

++This is a list of Queue Heads. Transfers associated with these Queue Heads are currently assigned to a host channel. ++

++Definition at line 406 of file dwc_otg_hcd.h. ++

++

++ ++

++
++ ++ ++ ++ ++
dwc_list_link_t dwc_otg_hcd::periodic_sched_inactive
++
++
++ ++

++Inactive items in the periodic schedule. ++

++This is a list of QHs for periodic transfers that are _not_ scheduled for the next frame. Each QH in the list has an interval counter that determines when it needs to be scheduled for execution. This scheduling mechanism allows only a simple calculation for periodic bandwidth used (i.e. must assume that all periodic transfers may need to execute in the same frame). However, it greatly simplifies scheduling and should be sufficient for the vast majority of OTG hosts, which need to connect to a small number of peripherals at one time.

++Items move from this list to periodic_sched_ready when the QH interval counter is 0 at SOF. ++

++Definition at line 428 of file dwc_otg_hcd.h. ++

++

++ ++

++
++ ++ ++ ++ ++
dwc_list_link_t dwc_otg_hcd::periodic_sched_ready
++
++
++ ++

++List of periodic QHs that are ready for execution in the next frame, but have not yet been assigned to host channels. ++

++Items move from this list to periodic_sched_assigned as host channels become available during the current frame. ++

++Definition at line 437 of file dwc_otg_hcd.h. ++

++

++ ++

++
++ ++ ++ ++ ++
dwc_list_link_t dwc_otg_hcd::periodic_sched_assigned
++
++
++ ++

++List of periodic QHs to be executed in the next frame that are assigned to host channels. ++

++Items move from this list to periodic_sched_queued as the transactions for the QH are queued to the DWC_otg controller. ++

++Definition at line 446 of file dwc_otg_hcd.h. ++

++

++ ++

++
++ ++ ++ ++ ++
dwc_list_link_t dwc_otg_hcd::periodic_sched_queued
++
++
++ ++

++List of periodic QHs that have been queued for execution. ++

++Items move from this list to either periodic_sched_inactive or periodic_sched_ready when the channel associated with the transfer is released. If the interval for the QH is 1, the item moves to periodic_sched_ready because it must be rescheduled for the next frame. Otherwise, the item moves to periodic_sched_inactive. ++

++Definition at line 457 of file dwc_otg_hcd.h. ++

++

++ ++

++
++ ++ ++ ++ ++
uint16_t dwc_otg_hcd::periodic_usecs
++
++
++ ++

++Total bandwidth claimed so far for periodic transfers. ++

++This value is in microseconds per (micro)frame. The assumption is that all periodic transfers may occur in the same (micro)frame. ++

++Definition at line 464 of file dwc_otg_hcd.h. ++

++

++ ++

++
++ ++ ++ ++ ++
uint16_t dwc_otg_hcd::frame_number
++
++
++ ++

++Frame number read from the core at SOF. ++

++The value ranges from 0 to DWC_HFNUM_MAX_FRNUM. ++

++Definition at line 470 of file dwc_otg_hcd.h. ++

++

++ ++

++
++ ++ ++ ++ ++
struct hc_list dwc_otg_hcd::free_hc_list
++
++
++ ++

++Free host channels in the controller. ++

++This is a list of dwc_hc_t items. ++

++Definition at line 476 of file dwc_otg_hcd.h. ++

++

++ ++

++
++ ++ ++ ++ ++
int dwc_otg_hcd::periodic_channels
++
++
++ ++

++Number of host channels assigned to periodic transfers. ++

++Currently assuming that there is a dedicated host channel for each periodic transaction and at least one host channel available for non-periodic transactions. ++

++Definition at line 483 of file dwc_otg_hcd.h. ++

++

++ ++

++
++ ++ ++ ++ ++
struct dwc_hc* dwc_otg_hcd::hc_ptr_array[MAX_EPS_CHANNELS]
++
++
++ ++

++Array of pointers to the host channel descriptors. ++

++Allows accessing a host channel descriptor given the host channel number. This is useful in interrupt handlers. ++

++Definition at line 495 of file dwc_otg_hcd.h. ++

++

++ ++

++
++ ++ ++ ++ ++
uint8_t* dwc_otg_hcd::status_buf
++
++
++ ++

++Buffer to use for any data received during the status phase of a control transfer. ++

++Normally no data is transferred during the status phase. This buffer is used as a bit bucket. ++

++Definition at line 502 of file dwc_otg_hcd.h. ++

++

++ ++

++
++ ++ ++ ++ ++
dwc_timer_t* dwc_otg_hcd::conn_timer
++
++
++ ++

++Connection timer. ++

++An OTG host must display a message if the device does not connect. Started when the VBus power is turned on via sysfs attribute "buspower". ++

++Definition at line 515 of file dwc_otg_hcd.h. ++

++

++

The documentation for this struct was generated from the following file: ++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__hcd__function__ops.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__hcd__function__ops.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,53 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_hcd_function_ops Struct Reference ++ ++ ++ ++ ++
++
++
++
++

dwc_otg_hcd_function_ops Struct Reference

++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++

Data Fields

++dwc_otg_hcd_start_cb_t start
++dwc_otg_hcd_disconnect_cb_t disconnect
++dwc_otg_hcd_hub_info_from_urb_cb_t hub_info
++dwc_otg_hcd_speed_from_urb_cb_t speed
++dwc_otg_hcd_complete_urb_cb_t complete
++dwc_otg_hcd_get_b_hnp_enable get_b_hnp_enable
++

Detailed Description

++ ++

++ ++

++Definition at line 76 of file dwc_otg_hcd_if.h.

The documentation for this struct was generated from the following file: ++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__hcd__iso__packet__desc.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__hcd__iso__packet__desc.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,47 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_hcd_iso_packet_desc Struct Reference ++ ++ ++ ++ ++
++
++
++
++

dwc_otg_hcd_iso_packet_desc Struct Reference

++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++

Data Fields

++uint32_t offset
++uint32_t length
++uint32_t actual_length
++uint32_t status
++

Detailed Description

++ ++

++ ++

++Definition at line 63 of file dwc_otg_hcd.h.

The documentation for this struct was generated from the following file: ++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__hcd__pipe__info.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__hcd__pipe__info.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,50 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_hcd_pipe_info Struct Reference ++ ++ ++ ++ ++
++
++
++
++

dwc_otg_hcd_pipe_info Struct Reference

++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++

Data Fields

++uint8_t dev_addr
++uint8_t ep_num
++uint8_t pipe_type
++uint8_t pipe_dir
++uint16_t mps
++

Detailed Description

++ ++

++ ++

++Definition at line 55 of file dwc_otg_hcd.h.

The documentation for this struct was generated from the following file: ++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__hcd__urb.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__hcd__urb.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,80 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_hcd_urb Struct Reference ++ ++ ++ ++ ++
++
++
++
++

dwc_otg_hcd_urb Struct Reference

++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++

Data Fields

++void * priv
++dwc_otg_qtd * qtd
++void * buf
++dwc_dma_t dma
++void * setup_packet
++dwc_dma_t setup_dma
++uint32_t length
++uint32_t actual_length
++uint32_t status
++uint32_t error_count
++uint32_t packet_count
++uint32_t flags
++uint16_t interval
++dwc_otg_hcd_pipe_info pipe_info
++dwc_otg_hcd_iso_packet_desc iso_descs [0]
++

Detailed Description

++ ++

++ ++

++Definition at line 72 of file dwc_otg_hcd.h.

The documentation for this struct was generated from the following file: ++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__host__dma__desc.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__host__dma__desc.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,50 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_host_dma_desc Struct Reference ++ ++ ++ ++ ++
++
++
++
++

dwc_otg_host_dma_desc Struct Reference

Host-mode DMA Descriptor structure. ++More... ++

++#include <dwc_otg_regs.h> ++

++ ++ ++ ++ ++ ++ ++ ++ ++ ++

Data Fields

++host_dma_desc_sts_t status
 DMA Descriptor status quadlet.
++uint32_t buf
 DMA Descriptor data buffer pointer.
++

Detailed Description

++Host-mode DMA Descriptor structure. ++

++DMA Descriptor structure contains two quadlets: Status quadlet and Data buffer pointer. ++

++ ++

++Definition at line 2166 of file dwc_otg_regs.h.

The documentation for this struct was generated from the following file: ++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__host__global__regs.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__host__global__regs.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,219 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_host_global_regs Struct Reference ++ ++ ++ ++ ++
++
++
++
++

dwc_otg_host_global_regs Struct Reference

The Host Global Registers structure defines the size and relative field offsets for the Host Mode Global Registers. ++More... ++

++#include <dwc_otg_regs.h> ++

++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++

Data Fields

volatile uint32_t hcfg
 Host Configuration Register.
volatile uint32_t hfir
 Host Frame Interval Register.
volatile uint32_t hfnum
 Host Frame Number / Frame Remaining Register.
uint32_t reserved40C
 Reserved.
volatile uint32_t hptxsts
 Host Periodic Transmit FIFO/ Queue Status Register.
volatile uint32_t haint
 Host All Channels Interrupt Register.
volatile uint32_t haintmsk
 Host All Channels Interrupt Mask Register.
volatile uint32_t hflbaddr
 Host Frame List Base Address Register .
++

Detailed Description

++The Host Global Registers structure defines the size and relative field offsets for the Host Mode Global Registers. ++

++Host Global Registers offsets 400h-7FFh. ++

++ ++

++Definition at line 1627 of file dwc_otg_regs.h.

Field Documentation

++ ++
++
++ ++ ++ ++ ++
volatile uint32_t dwc_otg_host_global_regs::hcfg
++
++
++ ++

++Host Configuration Register. ++

++Offset: 400h ++

++Definition at line 1629 of file dwc_otg_regs.h. ++

++

++ ++

++
++ ++ ++ ++ ++
volatile uint32_t dwc_otg_host_global_regs::hfir
++
++
++ ++

++Host Frame Interval Register. ++

++Offset: 404h ++

++Definition at line 1631 of file dwc_otg_regs.h. ++

++

++ ++

++
++ ++ ++ ++ ++
volatile uint32_t dwc_otg_host_global_regs::hfnum
++
++
++ ++

++Host Frame Number / Frame Remaining Register. ++

++Offset: 408h ++

++Definition at line 1633 of file dwc_otg_regs.h. ++

++

++ ++

++
++ ++ ++ ++ ++
uint32_t dwc_otg_host_global_regs::reserved40C
++
++
++ ++

++Reserved. ++

++Offset: 40Ch ++

++Definition at line 1635 of file dwc_otg_regs.h. ++

++

++ ++

++
++ ++ ++ ++ ++
volatile uint32_t dwc_otg_host_global_regs::hptxsts
++
++
++ ++

++Host Periodic Transmit FIFO/ Queue Status Register. ++

++Offset: 410h ++

++Definition at line 1637 of file dwc_otg_regs.h. ++

++

++ ++

++
++ ++ ++ ++ ++
volatile uint32_t dwc_otg_host_global_regs::haint
++
++
++ ++

++Host All Channels Interrupt Register. ++

++Offset: 414h ++

++Definition at line 1639 of file dwc_otg_regs.h. ++

++

++ ++

++
++ ++ ++ ++ ++
volatile uint32_t dwc_otg_host_global_regs::haintmsk
++
++
++ ++

++Host All Channels Interrupt Mask Register. ++

++Offset: 418h ++

++Definition at line 1641 of file dwc_otg_regs.h. ++

++

++ ++

++
++ ++ ++ ++ ++
volatile uint32_t dwc_otg_host_global_regs::hflbaddr
++
++
++ ++

++Host Frame List Base Address Register . ++

++Offset: 41Ch ++

++Definition at line 1643 of file dwc_otg_regs.h. ++

++

++

The documentation for this struct was generated from the following file: ++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__host__if.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__host__if.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,66 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_host_if Struct Reference ++ ++ ++ ++ ++
++
++
++
++

dwc_otg_host_if Struct Reference

OTG Host Interface Structure. ++More... ++

++#include <dwc_otg_regs.h> ++

++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++

Data Fields

++dwc_otg_host_global_regs_t * host_global_regs
 Host Global Registers starting at offset 400h.
++volatile uint32_t * hprt0
 Host Port 0 Control and Status Register.
++dwc_otg_hc_regs_t * hc_regs [MAX_EPS_CHANNELS]
 Host Channel Specific Registers at offsets 500h-5FCh.
++uint8_t num_host_channels
 Number of Host Channels (range: 1-16).
++uint8_t perio_eps_supported
 Periodic EPs supported (0: no, 1: yes).
++uint16_t perio_tx_fifo_size
 Periodic Tx FIFO Size (Only 1 host periodic Tx FIFO).
++

Detailed Description

++OTG Host Interface Structure. ++

++The OTG Host Interface Structure structure contains information needed to manage the DWC_otg controller acting in host mode. It represents the programming view of the host-specific aspects of the controller. ++

++ ++

++Definition at line 2181 of file dwc_otg_regs.h.

The documentation for this struct was generated from the following file: ++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__pcd.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__pcd.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,152 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_pcd Struct Reference ++ ++ ++ ++ ++
++
++
++
++

dwc_otg_pcd Struct Reference

DWC_otg PCD Structure. ++More... ++

++#include <dwc_otg_pcd.h> ++

++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++

Data Fields

++dwc_otg_pcd_function_ops * fops
++dwc_otg_core_if_t * core_if
 Core Interface.
++ep0state_e ep0state
 State of EP0.
++unsigned ep0_pending:1
 EP0 Request is pending.
++unsigned request_config:1
 Indicates when SET CONFIGURATION Request is in process.
++unsigned remote_wakeup_enable:1
 The state of the Remote Wakeup Enable.
++unsigned b_hnp_enable:1
 The state of the B-Device HNP Enable.
++unsigned a_hnp_support:1
 The state of A-Device HNP Support.
++unsigned a_alt_hnp_support:1
 The state of the A-Device Alt HNP support.
++unsigned request_pending
 Count of pending Requests.
++union {
   usb_device_request_t   req
   uint32_t   d32 [2]
} setup_pkt
 SETUP packet for EP0 This structure is allocated as a DMA buffer on PCD initialization with enough space for up to 3 setup packets.
++dwc_dma_t setup_pkt_dma_handle
++uint16_t * status_buf
 2-byte dma buffer used to return status from GET_STATUS
++dwc_dma_t status_buf_dma_handle
++dwc_otg_pcd_ep_t ep0
 EP0.
++dwc_otg_pcd_ep_t in_ep [MAX_EPS_CHANNELS-1]
 Array of IN EPs.
++dwc_otg_pcd_ep_t out_ep [MAX_EPS_CHANNELS-1]
 Array of OUT EPs.
++dwc_spinlock_t * lock
 number of valid EPs in the above array.
dwc_timer_t * srp_timer
 Timer for SRP.
++dwc_tasklet_t * test_mode_tasklet
 Tasklet to defer starting of TEST mode transmissions until Status Phase has been completed.
++dwc_tasklet_t * start_xfer_tasklet
 Tasklet to delay starting of xfer in DMA mode.
++unsigned test_mode
 The test mode to enter when the tasklet is executed.
++

Detailed Description

++DWC_otg PCD Structure. ++

++This structure encapsulates the data for the dwc_otg PCD. ++

++ ++

++Definition at line 137 of file dwc_otg_pcd.h.

Field Documentation

++ ++
++
++ ++ ++ ++ ++
dwc_timer_t* dwc_otg_pcd::srp_timer
++
++
++ ++

++Timer for SRP. ++

++If it expires before SRP is successful clear the SRP. ++

++Definition at line 185 of file dwc_otg_pcd.h. ++

++

++

The documentation for this struct was generated from the following file: ++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__pcd__ep.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__pcd__ep.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,77 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_pcd_ep Struct Reference ++ ++ ++ ++ ++
++
++
++
++

dwc_otg_pcd_ep Struct Reference

PCD EP structure. ++More... ++

++#include <dwc_otg_pcd.h> ++

++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++

Data Fields

++const usb_endpoint_descriptor_t * desc
 USB EP Descriptor.
++req_list queue
 queue of dwc_otg_pcd_requests.
++unsigned stopped:1
++unsigned disabling:1
++unsigned dma:1
++unsigned queue_sof:1
++void * iso_req_handle
 ISOC req handle passed.
++dwc_ep_t dwc_ep
 DWC_otg ep data.
++dwc_otg_pcd * pcd
 Pointer to PCD.
++void * priv
++

Detailed Description

++PCD EP structure. ++

++This structure describes an EP, there is an array of EPs in the PCD structure. ++

++ ++

++Definition at line 109 of file dwc_otg_pcd.h.

The documentation for this struct was generated from the following file: ++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__pcd__function__ops.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__pcd__function__ops.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,73 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_pcd_function_ops Struct Reference ++ ++ ++ ++ ++
++
++
++
++

dwc_otg_pcd_function_ops Struct Reference

Function Driver Ops Data Structure. ++More... ++

++#include <dwc_otg_pcd_if.h> ++

++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++

Data Fields

++dwc_connect_cb_t connect
++dwc_disconnect_cb_t disconnect
++dwc_setup_cb_t setup
++dwc_completion_cb_t complete
++dwc_isoc_completion_cb_t isoc_complete
++dwc_suspend_cb_t suspend
++dwc_sleep_cb_t sleep
++dwc_resume_cb_t resume
++dwc_reset_cb_t reset
++dwc_hnp_params_changed_cb_t hnp_changed
++cfi_setup_cb_t cfi_setup
++

Detailed Description

++Function Driver Ops Data Structure. ++

++ ++

++Definition at line 107 of file dwc_otg_pcd_if.h.

The documentation for this struct was generated from the following file: ++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__pcd__request.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__pcd__request.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,64 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_pcd_request Struct Reference ++ ++ ++ ++ ++
++
++
++
++

dwc_otg_pcd_request Struct Reference

DWC_otg request structure. ++More... ++

++#include <dwc_otg_pcd.h> ++

++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++

Public Member Functions

++ DWC_CIRCLEQ_ENTRY (dwc_otg_pcd_request) queue_entry

Data Fields

++void * priv
++void * buf
++dwc_dma_t dma
++uint32_t length
++uint32_t actual
++unsigned sent_zlp:1
++

Detailed Description

++DWC_otg request structure. ++

++This structure is a list of requests. ++

++ ++

++Definition at line 92 of file dwc_otg_pcd.h.

The documentation for this struct was generated from the following file: ++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__qh.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__qh.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,228 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_qh Struct Reference ++ ++ ++ ++ ++
++
++
++
++

dwc_otg_qh Struct Reference

A Queue Head (QH) holds the static characteristics of an endpoint and maintains a list of transfers (QTDs) for that endpoint. ++More... ++

++#include <dwc_otg_hcd.h> ++

++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++

Data Fields

uint8_t ep_type
 Endpoint type.
++uint8_t ep_is_in
++uint16_t maxp
 wMaxPacketSize Field of Endpoint Descriptor.
uint8_t dev_speed
 Device speed.
uint8_t data_toggle
 Determines the PID of the next data packet for non-control transfers.
++uint8_t ping_state
 Ping state if 1.
++dwc_otg_qtd_list qtd_list
 List of QTDs for this QH.
++dwc_hc * channel
 Host channel currently processing transfers for this QH.
++uint8_t do_split
 Full/low speed endpoint on high-speed hub requires split.
++uint8_t * dw_align_buf
 Used instead of original buffer if it(physical address) is not dword-aligned.
++dwc_dma_t dw_align_buf_dma
++dwc_list_link_t qh_list_entry
 Entry for QH in either the periodic or non-periodic schedule.
Periodic schedule information
++uint16_t usecs
 Bandwidth in microseconds per (micro)frame.
++uint16_t interval
 Interval between transfers in (micro)frames.
uint16_t sched_frame
 (micro)frame to initialize a periodic transfer.
++uint16_t start_split_frame
 (micro)frame at which last start split was initialized.
Descriptor DMA support
++dwc_otg_host_dma_desc_t * desc_list
 Descriptor List.
++dwc_dma_t desc_list_dma
 Descriptor List physical address.
uint32_t * n_bytes
 Xfer Bytes array.
++uint16_t ntd
 Actual number of transfer descriptors in a list.
++uint8_t td_first
 First activated isochronous transfer descriptor index.
++uint8_t td_last
 Last activated isochronous transfer descriptor index.
++

Detailed Description

++A Queue Head (QH) holds the static characteristics of an endpoint and maintains a list of transfers (QTDs) for that endpoint. ++

++A QH structure may be entered in either the non-periodic or periodic schedule. ++

++ ++

++Definition at line 261 of file dwc_otg_hcd.h.

Field Documentation

++ ++
++
++ ++ ++ ++ ++
uint8_t dwc_otg_qh::ep_type
++
++
++ ++

++Endpoint type. ++

++One of the following values:

    ++
  • UE_CONTROL
  • UE_BULK
  • UE_INTERRUPT
  • UE_ISOCHRONOUS
++ ++

++Definition at line 270 of file dwc_otg_hcd.h. ++

++

++ ++

++
++ ++ ++ ++ ++
uint8_t dwc_otg_qh::dev_speed
++
++
++ ++

++Device speed. ++

++One of the following values:

    ++
  • DWC_OTG_EP_SPEED_LOW
  • DWC_OTG_EP_SPEED_FULL
  • DWC_OTG_EP_SPEED_HIGH
++ ++

++Definition at line 283 of file dwc_otg_hcd.h. ++

++

++ ++

++
++ ++ ++ ++ ++
uint8_t dwc_otg_qh::data_toggle
++
++
++ ++

++Determines the PID of the next data packet for non-control transfers. ++

++Ignored for control transfers.
++ One of the following values:

    ++
  • DWC_OTG_HC_PID_DATA0
  • DWC_OTG_HC_PID_DATA1
++ ++

++Definition at line 292 of file dwc_otg_hcd.h. ++

++

++ ++

++
++ ++ ++ ++ ++
uint16_t dwc_otg_qh::sched_frame
++
++
++ ++

++(micro)frame to initialize a periodic transfer. ++

++The transfer executes in the following (micro)frame. ++

++Definition at line 321 of file dwc_otg_hcd.h. ++

++

++ ++

++
++ ++ ++ ++ ++
uint32_t* dwc_otg_qh::n_bytes
++
++
++ ++

++Xfer Bytes array. ++

++Each element corresponds to a descriptor and indicates original XferSize size value for the descriptor. ++

++Definition at line 352 of file dwc_otg_hcd.h. ++

++

++

The documentation for this struct was generated from the following file: ++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__qtd.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__qtd.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,157 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_qtd Struct Reference ++ ++ ++ ++ ++
++
++
++
++

dwc_otg_qtd Struct Reference

A Queue Transfer Descriptor (QTD) holds the state of a bulk, control, interrupt, or isochronous transfer. ++More... ++

++#include <dwc_otg_hcd.h> ++

++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++

Public Member Functions

++ DWC_CIRCLEQ_ENTRY (dwc_otg_qtd) qtd_list_entry
 This list of QTDs.

Data Fields

uint8_t data_toggle
 Determines the PID of the next data packet for the data phase of control transfers.
++dwc_otg_control_phase_e control_phase
 Current phase for control transfers (Setup, Data, or Status).
++uint8_t complete_split
 Keep track of the current split type for FS/LS endpoints on a HS Hub.
++uint32_t ssplit_out_xfer_count
 How many bytes transferred during SSPLIT OUT.
++uint8_t error_count
 Holds the number of bus errors that have occurred for a transaction within this transfer.
uint16_t isoc_frame_index
 Index of the next frame descriptor for an isochronous transfer.
++uint8_t isoc_split_pos
 Position of the ISOC split on full/low speed.
++uint16_t isoc_split_offset
 Position of the ISOC split in the buffer for the current frame.
++dwc_otg_hcd_urb * urb
 URB for this transfer.
++dwc_otg_qh * qh
++uint8_t in_process
 Indicates if this QTD is currently processed by HW.
++uint8_t n_desc
 Number of DMA descriptors for this QTD.
uint16_t isoc_frame_index_last
 Last activated frame(packet) index.
++

Detailed Description

++A Queue Transfer Descriptor (QTD) holds the state of a bulk, control, interrupt, or isochronous transfer. ++

++A single QTD is created for each URB (of one of these types) submitted to the HCD. The transfer associated with a QTD may require one or multiple transactions.

++A QTD is linked to a Queue Head, which is entered in either the non-periodic or periodic schedule for execution. When a QTD is chosen for execution, some or all of its transactions may be executed. After execution, the state of the QTD is updated. The QTD may be retired if all its transactions are complete or if an error occurred. Otherwise, it remains in the schedule so more transactions can be executed later. ++

++ ++

++Definition at line 191 of file dwc_otg_hcd.h.

Field Documentation

++ ++
++
++ ++ ++ ++ ++
uint8_t dwc_otg_qtd::data_toggle
++
++
++ ++

++Determines the PID of the next data packet for the data phase of control transfers. ++

++Ignored for other transfer types.
++ One of the following values:

    ++
  • DWC_OTG_HC_PID_DATA0
  • DWC_OTG_HC_PID_DATA1
++ ++

++Definition at line 199 of file dwc_otg_hcd.h. ++

++

++ ++

++
++ ++ ++ ++ ++
uint16_t dwc_otg_qtd::isoc_frame_index
++
++
++ ++

++Index of the next frame descriptor for an isochronous transfer. ++

++A frame descriptor describes the buffer position and length of the data to be transferred in the next scheduled (micro)frame of an isochronous transfer. It also holds status for that transaction. The frame index starts at 0. ++

++Definition at line 224 of file dwc_otg_hcd.h. ++

++

++ ++

++
++ ++ ++ ++ ++
uint16_t dwc_otg_qtd::isoc_frame_index_last
++
++
++ ++

++Last activated frame(packet) index. ++

++Used in Descriptor DMA mode only. ++

++Definition at line 250 of file dwc_otg_hcd.h. ++

++

++

The documentation for this struct was generated from the following file: ++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structgadget__wrapper.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structgadget__wrapper.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,53 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: gadget_wrapper Struct Reference ++ ++ ++ ++ ++
++
++
++
++

gadget_wrapper Struct Reference

++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++

Data Fields

++dwc_otg_pcd_t * pcd
++usb_gadget gadget
++usb_gadget_driver * driver
++usb_ep ep0
++usb_ep in_ep [16]
++usb_ep out_ep [16]
++

Detailed Description

++ ++

++ ++

++Definition at line 82 of file dwc_otg_pcd_linux.c.

The documentation for this struct was generated from the following file: ++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structiso__pkt__info.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structiso__pkt__info.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,49 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: iso_pkt_info Struct Reference ++ ++ ++ ++ ++
++
++
++
++

iso_pkt_info Struct Reference

Information for each ISOC packet. ++More... ++

++#include <dwc_otg_cil.h> ++

++ ++ ++ ++ ++ ++ ++ ++ ++ ++

Data Fields

++uint32_t offset
++uint32_t length
++int32_t status
++

Detailed Description

++Information for each ISOC packet. ++

++ ++

++Definition at line 77 of file dwc_otg_cil.h.

The documentation for this struct was generated from the following file: ++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structwrapper__priv__data.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structwrapper__priv__data.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,38 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: wrapper_priv_data Struct Reference ++ ++ ++ ++ ++
++
++
++
++

wrapper_priv_data Struct Reference

++ ++ ++ ++ ++

Data Fields

++dwc_otg_hcd_t * dwc_otg_hcd
++

Detailed Description

++ ++

++ ++

++Definition at line 95 of file dwc_otg_hcd_linux.c.

The documentation for this struct was generated from the following file: ++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structzero__dev.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structzero__dev.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,56 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: zero_dev Struct Reference ++ ++ ++ ++ ++
++
++
++
++

zero_dev Struct Reference

++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++

Data Fields

++spinlock_t lock
++usb_gadget * gadget
++usb_request * req
++u8 config
++usb_ep * in_ep
++usb_ep * out_ep
++timer_list resume
++

Detailed Description

++ ++

++ ++

++Definition at line 342 of file dummy_audio.c.

The documentation for this struct was generated from the following file: ++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/tabs.css +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/tabs.css 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,102 @@ ++/* tabs styles, based on http://www.alistapart.com/articles/slidingdoors */ ++ ++DIV.tabs ++{ ++ float : left; ++ width : 100%; ++ background : url("tab_b.gif") repeat-x bottom; ++ margin-bottom : 4px; ++} ++ ++DIV.tabs UL ++{ ++ margin : 0px; ++ padding-left : 10px; ++ list-style : none; ++} ++ ++DIV.tabs LI, DIV.tabs FORM ++{ ++ display : inline; ++ margin : 0px; ++ padding : 0px; ++} ++ ++DIV.tabs FORM ++{ ++ float : right; ++} ++ ++DIV.tabs A ++{ ++ float : left; ++ background : url("tab_r.gif") no-repeat right top; ++ border-bottom : 1px solid #84B0C7; ++ font-size : x-small; ++ font-weight : bold; ++ text-decoration : none; ++} ++ ++DIV.tabs A:hover ++{ ++ background-position: 100% -150px; ++} ++ ++DIV.tabs A:link, DIV.tabs A:visited, ++DIV.tabs A:active, DIV.tabs A:hover ++{ ++ color: #1A419D; ++} ++ ++DIV.tabs SPAN ++{ ++ float : left; ++ display : block; ++ background : url("tab_l.gif") no-repeat left top; ++ padding : 5px 9px; ++ white-space : nowrap; ++} ++ ++DIV.tabs INPUT ++{ ++ float : right; ++ display : inline; ++ font-size : 1em; ++} ++ ++DIV.tabs TD ++{ ++ font-size : x-small; ++ font-weight : bold; ++ text-decoration : none; ++} ++ ++ ++ ++/* Commented Backslash Hack hides rule from IE5-Mac \*/ ++DIV.tabs SPAN {float : none;} ++/* End IE5-Mac hack */ ++ ++DIV.tabs A:hover SPAN ++{ ++ background-position: 0% -150px; ++} ++ ++DIV.tabs LI#current A ++{ ++ background-position: 100% -150px; ++ border-width : 0px; ++} ++ ++DIV.tabs LI#current SPAN ++{ ++ background-position: 0% -150px; ++ padding-bottom : 6px; ++} ++ ++DIV.nav ++{ ++ background : none; ++ border : none; ++ border-bottom : 1px solid #84B0C7; ++} +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/todo.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/todo.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,262 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Todo List ++ ++ ++ ++ ++
++
++

Todo List

++
Global DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW
++
Add code to initiate the HNP.
++
++

++

++
Global srp_show
++
Add code to initiate the SRP.
++
++

++

++
Global buspower_show
++
Need to do more for power on/off?
++
++

++

++
Global bussuspend_show
++
Need to do more for suspend?
++
++

++

++
Global dwc_otg_enable_device_interrupts
++
NGS: Should this be a module parameter?
++
++

++

++
Global dwc_otg_core_dev_init
++
NGS: Fix Periodic FIFO Sizing!
++
++

++

++
Global dwc_otg_core_dev_init
++
Finish debug of this
++
++

++

++
Global dwc_otg_core_dev_init
++
- if the condition needed to be checked or in any case all pending interrutps should be cleared?
++
++

++

++
Global dwc_otg_ep0_continue_transfer
++
Should there be check for room in the Tx Status Queue. If not remove the code above this comment.
++
++

++

++
Global dwc_otg_ep_write_packet
++
NGS Where are the Periodic Tx FIFO addresses intialized? What should this be?
++
++

++

++
Global dwc_otg_read_packet
++
Account for the case where _dest is not dword aligned. This requires reading data from the FIFO into a uint32_t temp buffer, then moving it into the data buffer.
++
++

++

++
Global dwc_otg_handle_disconnect_intr
++
Consolidate this if statement.
++
++

++

++
Global dwc_otg_read_common_intr
++
: The port interrupt occurs while in device mode. Added code to CIL to clear the interrupt for now!
++
++

++

++
Global MODULE_PARM_DESC
++
Set the max to 512K, modify checks
++
++

++

++
Global dwc_otg_hcd_handle_intr
++
Implement i2cintr handler.
++
++

++

++
Global dwc_otg_hcd_qh_create
++
add memflags argument
++
++

++

++
Global dwc_otg_hcd_complete_xfer_ddma
++
Consider the case when period exceeds FrameList size. Frame Rollover interrupt should be used.
++
++

++

++
Global handle_hc_nyet_intr
++
add support for isoc release
++
++

++

++
Global handle_hc_chhltd_intr_dma
++
This is here because of a possible hardware bug. Spec says that on SPLIT-ISOC OUT transfers in DMA mode that a HALT interrupt w/ACK bit set should occur, but I only see the XFERCOMP bit, even with it masked out. This is a workaround for that behavior. Should fix this when hardware is fixed.
++
++

++

++
Global qh_init
++
Account for split transfers in the bus time.
++
++

++

++
File dwc_otg_pcd.c
++
Add Device Mode test modes (Test J mode, Test K mode, etc).

++Does it work when the request size is greater than DEPTSIZ transfer size

++

++
++

++

++
Global dwc_otg_pcd_iso_ep_start
++
- pattern data support is to be implemented in the future
++
++

++

++
Global dwc_otg_pcd_reinit
++
NGS: Add direction to EP, based on contents of HWCFG1. Need a copy of HWCFG1 in pcd structure? sprintf(";r
++
++

++

++
Global dwc_otg_pcd_reinit
++
NGS: Add direction to EP, based on contents of HWCFG1. Need a copy of HWCFG1 in pcd structure? sprintf(";r
++
++

++

++
Global dwc_otg_pcd_ep_queue
++
NGS Create a function for this.
++
++

++

++
Global do_test_mode
++
This has not been tested since the tasklet struct was put into the PCD struct!

++

++
++

++

++
Global dwc_otg_pcd_handle_rx_status_q_level_intr
++
NGS Check for buffer overflow?
++
++

++

++
Global get_ep_of_last_in_token
++
Find a simpler way to calculate the max queue position.
++
++

++

++
Global dwc_otg_pcd_stop
++
NGS Flush Periodic FIFOs
++
++

++

++
Global ep0_out_start
++
NGS: Update the comments from the HW FS.

++

++
++

++

++
Global ep0_out_start
++
dma needs to handle multiple setup packets (up to 3)
++
++

++

++
Global do_gadget_setup
++
This is a g_file_storage gadget driver specific workaround: a DELAYED_STATUS result from the fsg_setup routine will result in the gadget queueing a EP0 IN status phase for a two-stage control transfer. Exactly the same as a SET_CONFIGURATION/SET_INTERFACE except that this is a class specific request. Need a generic way to know when the gadget driver will queue the status phase. Can we assume when we call the gadget driver setup() function that it will always queue and require the following flag? Need to look into this.
++
++

++

++
Global pcd_clear_halt
++
FIXME: this causes an EP mismatch in DMA mode. epmismatch not yet implemented.
++
++

++

++
Global do_get_status
++
check for EP stall
++
++

++

++
Global do_set_feature
++
This has not been tested since the tasklet struct was put into the PCD struct!
++
++

++

++
Global do_set_feature
++
Is the gotgctl.devhnpen cleared by a USB Reset?
++
++

++

++
Global do_clear_feature
++
Add CLEAR_FEATURE for TEST modes.
++
++

++

++
Global pcd_setup
++
handle > 1 setup packet , assert error for now
++
++

++

++
Global pcd_setup
++
NGS: Handle bad setup packet?
++
++

++

++
Global handle_in_ep_timeout_intr
++
NGS Check EP type. Implement for Periodic EPs
++
++

++

++
Global handle_in_ep_nak_intr
++
implement ISR
++
++

++

++
Global handle_out_ep_babble_intr
++
implement ISR
++
++

++

++
Global handle_out_ep_nak_intr
++
implement ISR
++
++

++

++
Global handle_out_ep_nyet_intr
++
implement ISR
++
++

++

++
Global gadget_add_eps
++
NGS: What should the max packet size be set to here? Before EP type is set?
++
++

++

++
Global gadget_add_eps
++
NGS: What should the max packet size be set to here? Before EP type is set?
++
++

++

++
Global gadget_add_eps
++
NGS: What should the max packet size be set to here? Before EP type is set?
++
++

++

++
Global dwc_otg_pcd_gadget_release
++
Should this do something? Should it free the PCD?
++
++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/tree.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/tree.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,201 @@ ++ ++ ++ ++ ++ ++ ++ TreeView ++ ++ ++ ++ ++
++

DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver

++
++

o+Data Structures

++
++

|o*_ddma_align_buffer_setup

++

|o*_ddma_concat_buffer_setup

++

|o*_ddma_concat_buffer_setup_hdr

++

|o*_ddma_sg_buffer_setup

++

|o*_rx_fifo_size_setup

++

|o*_tx_fifo_size_setup

++

|o*cfi_all_features_header

++

|o*cfi_dma_buff

++

|o*cfi_ep

++

|o*cfi_feature_desc_header

++

|o*cfi_ops

++

|o*cfi_string

++

|o*cfi_usb_ctrlrequest

++

|o*cfiobject

++

|o*daint_data

++

|o*dcfg_data

++

|o*dctl_data

++

|o*depctl_data

++

|o*deptsiz0_data

++

|o*deptsiz_data

++

|o*dev_dma_desc_sts

++

|o*device_grxsts_data

++

|o*diepint_data

++

|o*doepint_data

++

|o*dsts_data

++

|o*dthrctl_data

++

|o*dtknq1_data

++

|o*dtxfsts_data

++

|o*dwc_ep

++

|o*dwc_hc

++

|o*dwc_otg_cil_callbacks

++

|o*dwc_otg_core_global_regs

++

|o*dwc_otg_core_if

++

|o*dwc_otg_core_params

++

|o*dwc_otg_dev_dma_desc

++

|o*dwc_otg_dev_global_regs

++

|o*dwc_otg_dev_if

++

|o*dwc_otg_dev_in_ep_regs

++

|o*dwc_otg_dev_out_ep_regs

++

|o*dwc_otg_device

++

|o*dwc_otg_driver_module_params

++

|o*dwc_otg_hc_regs

++

|o*dwc_otg_hcd

++

|o*dwc_otg_hcd::dwc_otg_hcd_internal_flags

++

|o*dwc_otg_hcd_function_ops

++

|o*dwc_otg_hcd_iso_packet_desc

++

|o*dwc_otg_hcd_pipe_info

++

|o*dwc_otg_hcd_urb

++

|o*dwc_otg_host_dma_desc

++

|o*dwc_otg_host_global_regs

++

|o*dwc_otg_host_if

++

|o*dwc_otg_pcd

++

|o*dwc_otg_pcd_ep

++

|o*dwc_otg_pcd_function_ops

++

|o*dwc_otg_pcd_request

++

|o*dwc_otg_qh

++

|o*dwc_otg_qtd

++

|o*fifosize_data

++

|o*gadget_wrapper

++

|o*gahbcfg_data

++

|o*gi2cctl_data

++

|o*gintmsk_data

++

|o*gintsts_data

++

|o*glpmctl_data

++

|o*gnptxsts_data

++

|o*gotgctl_data

++

|o*gotgint_data

++

|o*grstctl_data

++

|o*gusbcfg_data

++

|o*haint_data

++

|o*haintmsk_data

++

|o*hcchar_data

++

|o*hcdma_data

++

|o*hcfg_data

++

|o*hcint_data

++

|o*hcintmsk_data

++

|o*hcsplt_data

++

|o*hctsiz_data

++

|o*hfir_data

++

|o*hfnum_data

++

|o*host_dma_desc_sts

++

|o*host_grxsts_data

++

|o*hprt0_data

++

|o*hptxsts_data

++

|o*hwcfg1_data

++

|o*hwcfg2_data

++

|o*hwcfg3_data

++

|o*hwcfg4_data

++

|o*iso_pkt_info

++

|o*pcgcctl_data

++

|o*wrapper_priv_data

++

|\*zero_dev

++
++

o*Data Fields

++

o+File List

++ ++

o*Globals

++

\+Related Pages

++ ++
++
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/uniondaint__data.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/uniondaint__data.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,131 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: daint_data Union Reference ++ ++ ++ ++ ++
++
++
++
++

daint_data Union Reference

This union represents the bit fields in the Device All EP Interrupt and Mask Registers. ++More... ++

++#include <dwc_otg_regs.h> ++

++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++

Data Fields

++uint32_t d32
 raw register data
++struct {
   unsigned   in:16
 IN Endpoint bits.
   unsigned   out:16
 OUT Endpoint bits.
} ep
 register bits
++struct {
   unsigned   inep0:1
 IN Endpoint bits.
   unsigned   inep1:1
   unsigned   inep2:1
   unsigned   inep3:1
   unsigned   inep4:1
   unsigned   inep5:1
   unsigned   inep6:1
   unsigned   inep7:1
   unsigned   inep8:1
   unsigned   inep9:1
   unsigned   inep10:1
   unsigned   inep11:1
   unsigned   inep12:1
   unsigned   inep13:1
   unsigned   inep14:1
   unsigned   inep15:1
   unsigned   outep0:1
 OUT Endpoint bits.
   unsigned   outep1:1
   unsigned   outep2:1
   unsigned   outep3:1
   unsigned   outep4:1
   unsigned   outep5:1
   unsigned   outep6:1
   unsigned   outep7:1
   unsigned   outep8:1
   unsigned   outep9:1
   unsigned   outep10:1
   unsigned   outep11:1
   unsigned   outep12:1
   unsigned   outep13:1
   unsigned   outep14:1
   unsigned   outep15:1
} b
++

Detailed Description

++This union represents the bit fields in the Device All EP Interrupt and Mask Registers. ++

++

    ++
  • Read the register into the d32 member then set/clear the bits using the bit elements.
++ ++

++ ++

++Definition at line 1130 of file dwc_otg_regs.h.

The documentation for this union was generated from the following file: ++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/uniondcfg__data.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/uniondcfg__data.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,74 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dcfg_data Union Reference ++ ++ ++ ++ ++
++
++
++
++

dcfg_data Union Reference

This union represents the bit fields in the Device Configuration Register. ++More... ++

++#include <dwc_otg_regs.h> ++

++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++

Data Fields

++uint32_t d32
 raw register data
++struct {
   unsigned   devspd:2
 Device Speed.
   unsigned   nzstsouthshk:1
 Non Zero Length Status OUT Handshake.
   unsigned   reserved3:1
   unsigned   devaddr:7
 Device Addresses.
   unsigned   perfrint:2
 Periodic Frame Interval.
   unsigned   reserved13_17:5
   unsigned   epmscnt:5
 In Endpoint Mis-match count.
   unsigned   descdma:1
 Enable Descriptor DMA in Device mode.
} b
 register bits
++

Detailed Description

++This union represents the bit fields in the Device Configuration Register. ++

++Read the register into the d32 member then set/clear the bits using the bit elements. Write the d32 member to the dcfg register. ++

++ ++

++Definition at line 923 of file dwc_otg_regs.h.

The documentation for this union was generated from the following file: ++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/uniondctl__data.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/uniondctl__data.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,96 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dctl_data Union Reference ++ ++ ++ ++ ++
++
++
++
++

dctl_data Union Reference

This union represents the bit fields in the Device Control Register. ++More... ++

++#include <dwc_otg_regs.h> ++

++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++

Data Fields

++uint32_t d32
 raw register data
++struct {
   unsigned   rmtwkupsig:1
 Remote Wakeup.
   unsigned   sftdiscon:1
 Soft Disconnect.
   unsigned   gnpinnaksts:1
 Global Non-Periodic IN NAK Status.
   unsigned   goutnaksts:1
 Global OUT NAK Status.
   unsigned   tstctl:3
 Test Control.
   unsigned   sgnpinnak:1
 Set Global Non-Periodic IN NAK.
   unsigned   cgnpinnak:1
 Clear Global Non-Periodic IN NAK.
   unsigned   sgoutnak:1
 Set Global OUT NAK.
   unsigned   cgoutnak:1
 Clear Global OUT NAK.
   unsigned   pwronprgdone:1
 Power-On Programming Done.
   unsigned   gcontbna:1
 Global Continue on BNA.
   unsigned   gmc:2
 Global Multi Count.
   unsigned   ifrmnum:1
 Ignore Frame Number for ISOC EPs.
   unsigned   nakonbble:1
 NAK on Babble.
   unsigned   reserved17_31:15
} b
 register bits
++

Detailed Description

++This union represents the bit fields in the Device Control Register. ++

++Read the register into the d32 member then set/clear the bits using the bit elements. ++

++ ++

++Definition at line 957 of file dwc_otg_regs.h.

The documentation for this union was generated from the following file: ++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/uniondepctl__data.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/uniondepctl__data.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,139 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: depctl_data Union Reference ++ ++ ++ ++ ++
++
++
++
++

depctl_data Union Reference

This union represents the bit fields in the Device EP Control Register. ++More... ++

++#include <dwc_otg_regs.h> ++

++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++

Data Fields

++uint32_t d32
 raw register data
++struct {
   unsigned   mps:11
 Maximum Packet Size IN/OUT EPn IN/OUT EP0 - 2 bits 2'b00: 64 Bytes 2'b01: 32 2'b10: 16 2'b11: 8.
   unsigned   nextep:4
 Next Endpoint IN EPn/IN EP0 OUT EPn/OUT EP0 - reserved.
   unsigned   usbactep:1
 USB Active Endpoint.
   unsigned   dpid:1
 Endpoint DPID (INTR/Bulk IN and OUT endpoints) This field contains the PID of the packet going to be received or transmitted on this endpoint.
   unsigned   naksts:1
 NAK Status.
   unsigned   eptype:2
 Endpoint Type 2'b00: Control 2'b01: Isochronous 2'b10: Bulk 2'b11: Interrupt.
   unsigned   snp:1
 Snoop Mode OUT EPn/OUT EP0 IN EPn/IN EP0 - reserved.
   unsigned   stall:1
 Stall Handshake.
   unsigned   txfnum:4
 Tx Fifo Number IN EPn/IN EP0 OUT EPn/OUT EP0 - reserved.
   unsigned   cnak:1
 Clear NAK.
   unsigned   snak:1
 Set NAK.
   unsigned   setd0pid:1
 Set DATA0 PID (INTR/Bulk IN and OUT endpoints) Writing to this field sets the Endpoint DPID (DPID) field in this register to DATA0.
   unsigned   setd1pid:1
 Set DATA1 PID (INTR/Bulk IN and OUT endpoints) Writing to this field sets the Endpoint DPID (DPID) field in this register to DATA1 Set Odd (micro)frame (SetOddFr) (ISO IN and OUT Endpoints) Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to odd (micro) frame.
   unsigned   epdis:1
 Endpoint Disable.
   unsigned   epena:1
 Endpoint Enable.
} b
 register bits
++

Detailed Description

++This union represents the bit fields in the Device EP Control Register. ++

++Read the register into the d32 member then set/clear the bits using the bit elements. ++

++ ++

++Definition at line 1304 of file dwc_otg_regs.h.

Field Documentation

++ ++
++
++ ++ ++ ++ ++
unsigned depctl_data::dpid
++
++
++ ++

++Endpoint DPID (INTR/Bulk IN and OUT endpoints) This field contains the PID of the packet going to be received or transmitted on this endpoint. ++

++The application should program the PID of the first packet going to be received or transmitted on this endpoint , after the endpoint is activated. Application use the SetD1PID and SetD0PID fields of this register to program either D0 or D1 PID.

++The encoding for this field is

    ++
  • 0: D0
  • 1: D1
++ ++

++Definition at line 1344 of file dwc_otg_regs.h. ++

++

++ ++

++
++ ++ ++ ++ ++
unsigned depctl_data::setd0pid
++
++
++ ++

++Set DATA0 PID (INTR/Bulk IN and OUT endpoints) Writing to this field sets the Endpoint DPID (DPID) field in this register to DATA0. ++

++Set Even (micro)frame (SetEvenFr) (ISO IN and OUT Endpoints) Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to even (micro) frame. ++

++Definition at line 1381 of file dwc_otg_regs.h. ++

++

++

The documentation for this union was generated from the following file: ++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/uniondeptsiz0__data.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/uniondeptsiz0__data.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,69 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: deptsiz0_data Union Reference ++ ++ ++ ++ ++
++
++
++
++

deptsiz0_data Union Reference

This union represents the bit fields in the Device EP 0 Transfer Size Register. ++More... ++

++#include <dwc_otg_regs.h> ++

++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++

Data Fields

++uint32_t d32
 raw register data
++struct {
   unsigned   xfersize:7
 Transfer size.
   unsigned   reserved7_18:12
 Reserved.
   unsigned   pktcnt:1
 Packet Count.
   unsigned   reserved20_28:9
 Reserved.
   unsigned   supcnt:2
 Setup Packet Count (DOEPTSIZ0 Only).
   unsigned   reserved31
} b
 register bits
++

Detailed Description

++This union represents the bit fields in the Device EP 0 Transfer Size Register. ++

++Read the register into the d32 member then set/clear the bits using the bit elements. ++

++ ++

++Definition at line 1423 of file dwc_otg_regs.h.

The documentation for this union was generated from the following file: ++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/uniondeptsiz__data.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/uniondeptsiz__data.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,63 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: deptsiz_data Union Reference ++ ++ ++ ++ ++
++
++
++
++

deptsiz_data Union Reference

This union represents the bit fields in the Device EP Transfer Size Register. ++More... ++

++#include <dwc_otg_regs.h> ++

++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++

Data Fields

++uint32_t d32
 raw register data
++struct {
   unsigned   xfersize:19
 Transfer size.
   unsigned   pktcnt:10
 Packet Count.
   unsigned   mc:2
 Multi Count - Periodic IN endpoints.
   unsigned   reserved:1
} b
 register bits
++

Detailed Description

++This union represents the bit fields in the Device EP Transfer Size Register. ++

++Read the register into the d32 member then set/clear the bits using the bit elements. ++

++ ++

++Definition at line 1403 of file dwc_otg_regs.h.

The documentation for this union was generated from the following file: ++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/uniondev__dma__desc__sts.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/uniondev__dma__desc__sts.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,140 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dev_dma_desc_sts Union Reference ++ ++ ++ ++ ++
++
++
++
++

dev_dma_desc_sts Union Reference

This union represents the bit fields in the DMA Descriptor status quadlet. ++More... ++

++#include <dwc_otg_regs.h> ++

++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++

Data Fields

++uint32_t d32
 raw register data
++struct {
   unsigned   bytes:16
 Received number of bytes.
   unsigned   reserved16_22:7
   unsigned   mtrf:1
 Multiple Transfer - only for OUT EPs.
   unsigned   sr:1
 Setup Packet received - only for OUT EPs.
   unsigned   ioc:1
 Interrupt On Complete.
   unsigned   sp:1
 Short Packet.
   unsigned   l:1
 Last.
   unsigned   sts:2
 Receive Status.
   unsigned   bs:2
 Buffer Status.
} b
 quadlet bits
++struct {
   unsigned   rxbytes:11
 Received number of bytes.
   unsigned   reserved11:1
   unsigned   framenum:11
 Frame Number.
   unsigned   pid:2
 Received ISO Data PID.
   unsigned   ioc:1
 Interrupt On Complete.
   unsigned   sp:1
 Short Packet.
   unsigned   l:1
 Last.
   unsigned   rxsts:2
 Receive Status.
   unsigned   bs:2
 Buffer Status.
} b_iso_out
 iso out quadlet bits
++struct {
   unsigned   txbytes:12
 Transmited number of bytes.
   unsigned   framenum:11
 Frame Number.
   unsigned   pid:2
 Transmited ISO Data PID.
   unsigned   ioc:1
 Interrupt On Complete.
   unsigned   sp:1
 Short Packet.
   unsigned   l:1
 Last.
   unsigned   txsts:2
 Transmit Status.
   unsigned   bs:2
 Buffer Status.
} b_iso_in
 iso in quadlet bits
++

Detailed Description

++This union represents the bit fields in the DMA Descriptor status quadlet. ++

++Read the quadlet into the d32 member then set/clear the bits using the bit, b_iso_out and b_iso_in elements. ++

++ ++

++Definition at line 1466 of file dwc_otg_regs.h.

The documentation for this union was generated from the following file: ++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/uniondevice__grxsts__data.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/uniondevice__grxsts__data.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,62 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: device_grxsts_data Union Reference ++ ++ ++ ++ ++
++
++
++
++

device_grxsts_data Union Reference

This union represents the bit fields in the Device Receive Status Read and Pop Registers (GRXSTSR, GRXSTSP) Read the register into the d32 element then read out the bits using the bit elements. ++More... ++

++#include <dwc_otg_regs.h> ++

++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++

Data Fields

++uint32_t d32
 raw register data
++struct {
   unsigned   epnum:4
   unsigned   bcnt:11
   unsigned   dpid:2
   unsigned   pktsts:4
   unsigned   fn:4
   unsigned   reserved:7
} b
 register bits
++

Detailed Description

++This union represents the bit fields in the Device Receive Status Read and Pop Registers (GRXSTSR, GRXSTSP) Read the register into the d32 element then read out the bits using the bit elements. ++

++ ++

++Definition at line 601 of file dwc_otg_regs.h.

The documentation for this union was generated from the following file: ++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/uniondiepint__data.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/uniondiepint__data.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,90 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: diepint_data Union Reference ++ ++ ++ ++ ++
++
++
++
++

diepint_data Union Reference

This union represents the bit fields in the Device IN EP Interrupt Register and the Device IN EP Common Mask Register. ++More... ++

++#include <dwc_otg_regs.h> ++

++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++

Data Fields

++uint32_t d32
 raw register data
++struct {
   unsigned   xfercompl:1
 Transfer complete mask.
   unsigned   epdisabled:1
 Endpoint disable mask.
   unsigned   ahberr:1
 AHB Error mask.
   unsigned   timeout:1
 TimeOUT Handshake mask (non-ISOC EPs).
   unsigned   intktxfemp:1
 IN Token received with TxF Empty mask.
   unsigned   intknepmis:1
 IN Token Received with EP mismatch mask.
   unsigned   inepnakeff:1
 IN Endpoint HAK Effective mask.
   unsigned   emptyintr:1
 IN Endpoint HAK Effective mask.
   unsigned   txfifoundrn:1
   unsigned   bna:1
 BNA Interrupt mask.
   unsigned   reserved10_12:3
   unsigned   nak:1
 BNA Interrupt mask.
   unsigned   reserved14_31:18
} b
 register bits
++

Detailed Description

++This union represents the bit fields in the Device IN EP Interrupt Register and the Device IN EP Common Mask Register. ++

++

    ++
  • Read the register into the d32 member then set/clear the bits using the bit elements.
++ ++

++ ++

++Definition at line 1030 of file dwc_otg_regs.h.

The documentation for this union was generated from the following file: ++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/uniondoepint__data.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/uniondoepint__data.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,98 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: doepint_data Union Reference ++ ++ ++ ++ ++
++
++
++
++

doepint_data Union Reference

This union represents the bit fields in the Device OUT EP Interrupt Registerand Device OUT EP Common Interrupt Mask Register. ++More... ++

++#include <dwc_otg_regs.h> ++

++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++

Data Fields

++uint32_t d32
 raw register data
++struct {
   unsigned   xfercompl:1
 Transfer complete.
   unsigned   epdisabled:1
 Endpoint disable.
   unsigned   ahberr:1
 AHB Error.
   unsigned   setup:1
 Setup Phase Done (contorl EPs).
   unsigned   outtknepdis:1
 OUT Token Received when Endpoint Disabled.
   unsigned   stsphsercvd:1
   unsigned   back2backsetup:1
 Back-to-Back SETUP Packets Received.
   unsigned   reserved7:1
   unsigned   outpkterr:1
 OUT packet Error.
   unsigned   bna:1
 BNA Interrupt.
   unsigned   reserved10:1
   unsigned   pktdrpsts:1
 Packet Drop Status.
   unsigned   babble:1
 Babble Interrupt.
   unsigned   nak:1
 NAK Interrupt.
   unsigned   nyet:1
 NYET Interrupt.
   unsigned   reserved15_31:17
} b
 register bits
++

Detailed Description

++This union represents the bit fields in the Device OUT EP Interrupt Registerand Device OUT EP Common Interrupt Mask Register. ++

++

    ++
  • Read the register into the d32 member then set/clear the bits using the bit elements.
++ ++

++ ++

++Definition at line 1078 of file dwc_otg_regs.h.

The documentation for this union was generated from the following file: ++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/uniondsts__data.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/uniondsts__data.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,68 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dsts_data Union Reference ++ ++ ++ ++ ++
++
++
++
++

dsts_data Union Reference

This union represents the bit fields in the Device Status Register. ++More... ++

++#include <dwc_otg_regs.h> ++

++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++

Data Fields

++uint32_t d32
 raw register data
++struct {
   unsigned   suspsts:1
 Suspend Status.
   unsigned   enumspd:2
 Enumerated Speed.
   unsigned   errticerr:1
 Erratic Error.
   unsigned   reserved4_7:4
   unsigned   soffn:14
 Frame or Microframe Number of the received SOF.
   unsigned   reserved22_31:10
} b
 register bits
++

Detailed Description

++This union represents the bit fields in the Device Status Register. ++

++Read the register into the d32 member then set/clear the bits using the bit elements. ++

++ ++

++Definition at line 1001 of file dwc_otg_regs.h.

The documentation for this union was generated from the following file: ++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/uniondthrctl__data.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/uniondthrctl__data.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,178 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dthrctl_data Union Reference ++ ++ ++ ++ ++
++
++
++
++

dthrctl_data Union Reference

This union represents Threshold control Register
    ++
  • Read and write the register into the d32 member.
++ ++More... ++

++#include <dwc_otg_regs.h> ++

++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++

Data Fields

++uint32_t d32
 raw register data
++struct {
   unsigned   non_iso_thr_en:1
 non ISO Tx Thr.
   unsigned   iso_thr_en:1
 ISO Tx Thr.
   unsigned   tx_thr_len:9
 Tx Thr.
   unsigned   ahb_thr_ratio:2
 AHB Threshold ratio.
   unsigned   reserved13_15:3
 Reserved.
   unsigned   rx_thr_en:1
 Rx Thr.
   unsigned   rx_thr_len:9
 Rx Thr.
   unsigned   reserved26_31:6
 Reserved.
} b
 register bits
++

Detailed Description

++This union represents Threshold control Register
    ++
  • Read and write the register into the d32 member.
++ ++

++

    ++
  • READ-WRITABLE Register
++ ++

++ ++

++Definition at line 1205 of file dwc_otg_regs.h.

Field Documentation

++ ++
++
++ ++ ++ ++ ++
unsigned dthrctl_data::non_iso_thr_en
++
++
++ ++

++non ISO Tx Thr. ++

++Enable ++

++Definition at line 1211 of file dwc_otg_regs.h. ++

++

++ ++

++
++ ++ ++ ++ ++
unsigned dthrctl_data::iso_thr_en
++
++
++ ++

++ISO Tx Thr. ++

++Enable ++

++Definition at line 1213 of file dwc_otg_regs.h. ++

++

++ ++

++
++ ++ ++ ++ ++
unsigned dthrctl_data::tx_thr_len
++
++
++ ++

++Tx Thr. ++

++Length ++

++Definition at line 1215 of file dwc_otg_regs.h. ++

++

++ ++

++
++ ++ ++ ++ ++
unsigned dthrctl_data::rx_thr_en
++
++
++ ++

++Rx Thr. ++

++Enable ++

++Definition at line 1221 of file dwc_otg_regs.h. ++

++

++ ++

++
++ ++ ++ ++ ++
unsigned dthrctl_data::rx_thr_len
++
++
++ ++

++Rx Thr. ++

++Length ++

++Definition at line 1223 of file dwc_otg_regs.h. ++

++

++

The documentation for this union was generated from the following file: ++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/uniondtknq1__data.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/uniondtknq1__data.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,86 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dtknq1_data Union Reference ++ ++ ++ ++ ++
++
++
++
++

dtknq1_data Union Reference

This union represents the bit fields in the Device IN Token Queue Read Registers. ++More... ++

++#include <dwc_otg_regs.h> ++

++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++

Data Fields

++uint32_t d32
 raw register data
++struct {
   unsigned   intknwptr:5
 In Token Queue Write Pointer.
   unsigned   reserved05_06:2
 Reserved.
   unsigned   wrap_bit:1
 write pointer has wrapped.
   unsigned   epnums0_5:24
 EP Numbers of IN Tokens 0 .
} b
 register bits
++

Detailed Description

++This union represents the bit fields in the Device IN Token Queue Read Registers. ++

++

    ++
  • Read the register into the d32 member.
  • READ-ONLY Register
++ ++

++ ++

++Definition at line 1184 of file dwc_otg_regs.h.

Field Documentation

++ ++
++
++ ++ ++ ++ ++
unsigned dtknq1_data::epnums0_5
++
++
++ ++

++EP Numbers of IN Tokens 0 . ++

++.. 4 ++

++Definition at line 1196 of file dwc_otg_regs.h. ++

++

++

The documentation for this union was generated from the following file: ++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/uniondtxfsts__data.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/uniondtxfsts__data.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,56 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dtxfsts_data Union Reference ++ ++ ++ ++ ++
++
++
++
++

dtxfsts_data Union Reference

This union represents the bit fields in the Transmit FIFO Status Register (DTXFSTS). ++More... ++

++#include <dwc_otg_regs.h> ++

++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++

Data Fields

++uint32_t d32
 raw register data
++struct {
   unsigned   txfspcavail:16
   unsigned   reserved:16
} b
 register bits
++

Detailed Description

++This union represents the bit fields in the Transmit FIFO Status Register (DTXFSTS). ++

++Read the register into the d32 element then read out the bits using the bit elements. ++

++ ++

++Definition at line 697 of file dwc_otg_regs.h.

The documentation for this union was generated from the following file: ++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/uniondwc__otg__hcd_1_1dwc__otg__hcd__internal__flags.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/uniondwc__otg__hcd_1_1dwc__otg__hcd__internal__flags.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,66 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_hcd::dwc_otg_hcd_internal_flags Union Reference ++ ++ ++ ++ ++
++
++
++
++
++dwc_otg_hcd::dwc_otg_hcd_internal_flags
++

dwc_otg_hcd::dwc_otg_hcd_internal_flags Union Reference

Internal DWC HCD Flags. ++More... ++

++#include <dwc_otg_hcd.h> ++

++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++

Data Fields

++uint32_t d32
++struct {
   unsigned   port_connect_status_change:1
   unsigned   port_connect_status:1
   unsigned   port_reset_change:1
   unsigned   port_enable_change:1
   unsigned   port_suspend_change:1
   unsigned   port_over_current_change:1
   unsigned   port_l1_change:1
   unsigned   reserved:26
} b
++

Detailed Description

++Internal DWC HCD Flags. ++

++ ++

++Definition at line 380 of file dwc_otg_hcd.h.

The documentation for this union was generated from the following file: ++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/unionfifosize__data.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/unionfifosize__data.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,56 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: fifosize_data Union Reference ++ ++ ++ ++ ++
++
++
++
++

fifosize_data Union Reference

This union represents the bit fields in the FIFO Size Registers (HPTXFSIZ, GNPTXFSIZ, DPTXFSIZn, DIEPTXFn). ++More... ++

++#include <dwc_otg_regs.h> ++

++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++

Data Fields

++uint32_t d32
 raw register data
++struct {
   unsigned   startaddr:16
   unsigned   depth:16
} b
 register bits
++

Detailed Description

++This union represents the bit fields in the FIFO Size Registers (HPTXFSIZ, GNPTXFSIZ, DPTXFSIZn, DIEPTXFn). ++

++Read the register into the d32 element then read out the bits using the bit elements. ++

++ ++

++Definition at line 651 of file dwc_otg_regs.h.

The documentation for this union was generated from the following file: ++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/uniongahbcfg__data.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/uniongahbcfg__data.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,66 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: gahbcfg_data Union Reference ++ ++ ++ ++ ++
++
++
++
++

gahbcfg_data Union Reference

This union represents the bit fields of the Core AHB Configuration Register (GAHBCFG). ++More... ++

++#include <dwc_otg_regs.h> ++

++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++

Data Fields

++uint32_t d32
 raw register data
++struct {
   unsigned   glblintrmsk:1
   unsigned   hburstlen:4
   unsigned   dmaenable:1
   unsigned   reserved:1
   unsigned   nptxfemplvl_txfemplvl:1
   unsigned   ptxfemplvl:1
   unsigned   reserved9_31:23
} b
 register bits
++

Detailed Description

++This union represents the bit fields of the Core AHB Configuration Register (GAHBCFG). ++

++Set/clear the bits using the bit fields then write the d32 value to the register. ++

++ ++

++Definition at line 216 of file dwc_otg_regs.h.

The documentation for this union was generated from the following file: ++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/uniongi2cctl__data.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/uniongi2cctl__data.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,72 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: gi2cctl_data Union Reference ++ ++ ++ ++ ++
++
++
++
++

gi2cctl_data Union Reference

This union represents the bit fields in the I2C Control Register (I2CCTL). ++More... ++

++#include <dwc_otg_regs.h> ++

++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++

Data Fields

++uint32_t d32
 raw register data
++struct {
   unsigned   rwdata:8
   unsigned   regaddr:8
   unsigned   addr:7
   unsigned   i2cen:1
   unsigned   ack:1
   unsigned   i2csuspctl:1
   unsigned   i2cdevaddr:2
   unsigned   reserved:2
   unsigned   rw:1
   unsigned   bsydne:1
} b
 register bits
++

Detailed Description

++This union represents the bit fields in the I2C Control Register (I2CCTL). ++

++Read the register into the d32 element then read out the bits using the bit elements. ++

++ ++

++Definition at line 712 of file dwc_otg_regs.h.

The documentation for this union was generated from the following file: ++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/uniongintmsk__data.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/uniongintmsk__data.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,114 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: gintmsk_data Union Reference ++ ++ ++ ++ ++
++
++
++
++

gintmsk_data Union Reference

This union represents the bit fields of the Core Interrupt Mask Register (GINTMSK). ++More... ++

++#include <dwc_otg_regs.h> ++

++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++

Data Fields

++uint32_t d32
 raw register data
++struct {
   unsigned   reserved0:1
   unsigned   modemismatch:1
   unsigned   otgintr:1
   unsigned   sofintr:1
   unsigned   rxstsqlvl:1
   unsigned   nptxfempty:1
   unsigned   ginnakeff:1
   unsigned   goutnakeff:1
   unsigned   reserved8:1
   unsigned   i2cintr:1
   unsigned   erlysuspend:1
   unsigned   usbsuspend:1
   unsigned   usbreset:1
   unsigned   enumdone:1
   unsigned   isooutdrop:1
   unsigned   eopframe:1
   unsigned   reserved16:1
   unsigned   epmismatch:1
   unsigned   inepintr:1
   unsigned   outepintr:1
   unsigned   incomplisoin:1
   unsigned   incomplisoout:1
   unsigned   reserved22_23:2
   unsigned   portintr:1
   unsigned   hcintr:1
   unsigned   ptxfempty:1
   unsigned   lpmtranrcvd:1
   unsigned   conidstschng:1
   unsigned   disconnect:1
   unsigned   sessreqintr:1
   unsigned   wkupintr:1
} b
 register bits
++

Detailed Description

++This union represents the bit fields of the Core Interrupt Mask Register (GINTMSK). ++

++Set/clear the bits using the bit fields then write the d32 value to the register. ++

++ ++

++Definition at line 512 of file dwc_otg_regs.h.

The documentation for this union was generated from the following file: ++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/uniongintsts__data.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/uniongintsts__data.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,114 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: gintsts_data Union Reference ++ ++ ++ ++ ++
++
++
++
++

gintsts_data Union Reference

This union represents the bit fields of the Core Interrupt Register (GINTSTS). ++More... ++

++#include <dwc_otg_regs.h> ++

++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++

Data Fields

++uint32_t d32
 raw register data
++struct {
   unsigned   curmode:1
   unsigned   modemismatch:1
   unsigned   otgintr:1
   unsigned   sofintr:1
   unsigned   rxstsqlvl:1
   unsigned   nptxfempty:1
   unsigned   ginnakeff:1
   unsigned   goutnakeff:1
   unsigned   reserved8:1
   unsigned   i2cintr:1
   unsigned   erlysuspend:1
   unsigned   usbsuspend:1
   unsigned   usbreset:1
   unsigned   enumdone:1
   unsigned   isooutdrop:1
   unsigned   eopframe:1
   unsigned   intokenrx:1
   unsigned   epmismatch:1
   unsigned   inepint:1
   unsigned   outepintr:1
   unsigned   incomplisoin:1
   unsigned   incomplisoout:1
   unsigned   reserved22_23:2
   unsigned   portintr:1
   unsigned   hcintr:1
   unsigned   ptxfempty:1
   unsigned   lpmtranrcvd:1
   unsigned   conidstschng:1
   unsigned   disconnect:1
   unsigned   sessreqintr:1
   unsigned   wkupintr:1
} b
 register bits
++

Detailed Description

++This union represents the bit fields of the Core Interrupt Register (GINTSTS). ++

++Set/clear the bits using the bit fields then write the d32 value to the register. ++

++ ++

++Definition at line 555 of file dwc_otg_regs.h.

The documentation for this union was generated from the following file: ++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/unionglpmctl__data.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/unionglpmctl__data.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,178 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: glpmctl_data Union Reference ++ ++ ++ ++ ++
++
++
++
++

glpmctl_data Union Reference

This union represents the bit fields of the Core LPM Configuration Register (GLPMCFG). ++More... ++

++#include <dwc_otg_regs.h> ++

++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++

Data Fields

++uint32_t d32
 raw register data
++struct {
   unsigned   lpm_cap_en:1
 LPM-Capable (LPMCap) (Device and Host) The application uses this bit to control the DWC_otg core LPM capabilities.
   unsigned   appl_resp:1
 LPM response programmed by application (AppL1Res) (Device) Handshake response to LPM token pre-programmed by device application software.
   unsigned   hird:4
 Host Initiated Resume Duration (HIRD) (Device and Host) In Host mode this field indicates the value of HIRD to be sent in an LPM transaction.
   unsigned   rem_wkup_en:1
 RemoteWakeEnable (bRemoteWake) (Device and Host) In Host mode this bit indicates the value of remote wake up to be sent in wIndex field of LPM transaction.
   unsigned   en_utmi_sleep:1
 Enable utmi_sleep_n (EnblSlpM) (Device and Host) The application uses this bit to control the utmi_sleep_n assertion to the PHY when in L1 state.
   unsigned   hird_thres:5
 HIRD Threshold (HIRD_Thres) (Device and Host).
   unsigned   lpm_resp:2
 LPM Response (CoreL1Res) (Device and Host) In Host mode this bit contains handsake response to LPM transaction.
   unsigned   prt_sleep_sts:1
 Port Sleep Status (SlpSts) (Device and Host) This bit is set as long as a Sleep condition is present on the USB bus.
   unsigned   sleep_state_resumeok:1
 Sleep State Resume OK (L1ResumeOK) (Device and Host) Indicates that the application or host can start resume from Sleep state.
   unsigned   lpm_chan_index:4
 LPM channel Index (LPM_Chnl_Indx) (Host) The channel number on which the LPM transaction has to be applied while sending an LPM transaction to the local device.
   unsigned   retry_count:3
 LPM Retry Count (LPM_Retry_Cnt) (Host) Number host retries that would be performed if the device response was not valid response.
   unsigned   send_lpm:1
 Send LPM Transaction (SndLPM) (Host) When set by application software, an LPM transaction containing two tokens is sent.
   unsigned   retry_count_sts:3
 LPM Retry status (LPM_RetryCnt_Sts) (Host) Number of LPM Host Retries still remaining to be transmitted for the current LPM sequence.
   unsigned   reserved28_29:2
   unsigned   hsic_connect:1
 In host mode once this bit is set, the host configures to drive the HSIC Idle state on the bus.
   unsigned   inv_sel_hsic:1
 This bit overrides and functionally inverts the if_select_hsic input port signal.
} b
 register bits
++

Detailed Description

++This union represents the bit fields of the Core LPM Configuration Register (GLPMCFG). ++

++Set the bits using bit fields then write the d32 value to the register. ++

++ ++

++Definition at line 283 of file dwc_otg_regs.h.

Field Documentation

++ ++
++
++ ++ ++ ++ ++
unsigned glpmctl_data::hird
++
++
++ ++

++Host Initiated Resume Duration (HIRD) (Device and Host) In Host mode this field indicates the value of HIRD to be sent in an LPM transaction. ++

++In Device mode this field is updated with the Received LPM Token HIRD bmAttribute when an ACK/NYET/STALL response is sent to an LPM transaction. ++

++Definition at line 306 of file dwc_otg_regs.h. ++

++

++ ++

++
++ ++ ++ ++ ++
unsigned glpmctl_data::rem_wkup_en
++
++
++ ++

++RemoteWakeEnable (bRemoteWake) (Device and Host) In Host mode this bit indicates the value of remote wake up to be sent in wIndex field of LPM transaction. ++

++In Device mode this field is updated with the Received LPM Token bRemoteWake bmAttribute when an ACK/NYET/STALL response is sent to an LPM transaction. ++

++Definition at line 315 of file dwc_otg_regs.h. ++

++

++ ++

++
++ ++ ++ ++ ++
unsigned glpmctl_data::lpm_resp
++
++
++ ++

++LPM Response (CoreL1Res) (Device and Host) In Host mode this bit contains handsake response to LPM transaction. ++

++In Device mode the response of the core to LPM transaction received is reflected in these two bits.

    ++
  • 0x0 : ERROR (No handshake response)
  • 0x1 : STALL
  • 0x2 : NYET
  • 0x3 : ACK
++ ++

++Definition at line 334 of file dwc_otg_regs.h. ++

++

++ ++

++
++ ++ ++ ++ ++
unsigned glpmctl_data::hsic_connect
++
++
++ ++

++In host mode once this bit is set, the host configures to drive the HSIC Idle state on the bus. ++

++It then waits for the device to initiate the Connect sequence. In device mode once this bit is set, the device waits for the HSIC Idle line state on the bus. Upon receving the Idle line state, it initiates the HSIC Connect sequence. ++

++Definition at line 375 of file dwc_otg_regs.h. ++

++

++

The documentation for this union was generated from the following file: ++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/uniongnptxsts__data.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/uniongnptxsts__data.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,69 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: gnptxsts_data Union Reference ++ ++ ++ ++ ++
++
++
++
++

gnptxsts_data Union Reference

This union represents the bit fields in the Non-Periodic Transmit FIFO/Queue Status Register (GNPTXSTS). ++More... ++

++#include <dwc_otg_regs.h> ++

++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++

Data Fields

++uint32_t d32
 raw register data
++struct {
   unsigned   nptxfspcavail:16
   unsigned   nptxqspcavail:8
   unsigned   nptxqtop_terminate:1
 Top of the Non-Periodic Transmit Request Queue
    ++
  • bit 24 - Terminate (Last entry for the selected channel/EP)
  • bits 26:25 - Token Type
      ++
    • 2'b00 - IN/OUT
    • 2'b01 - Zero Length OUT
    • 2'b10 - PING/Complete Split
    • 2'b11 - Channel Halt
    ++
  • bits 30:27 - Channel/EP Number.
++
   unsigned   nptxqtop_token:2
   unsigned   nptxqtop_chnep:4
   unsigned   reserved:1
} b
 register bits
++

Detailed Description

++This union represents the bit fields in the Non-Periodic Transmit FIFO/Queue Status Register (GNPTXSTS). ++

++Read the register into the d32 element then read out the bits using the bit elements. ++

++ ++

++Definition at line 667 of file dwc_otg_regs.h.

The documentation for this union was generated from the following file: ++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/uniongotgctl__data.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/uniongotgctl__data.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,80 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: gotgctl_data Union Reference ++ ++ ++ ++ ++
++
++
++
++

gotgctl_data Union Reference

This union represents the bit fields of the Core OTG Control and Status Register (GOTGCTL). ++More... ++

++#include <dwc_otg_regs.h> ++

++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++

Data Fields

++uint32_t d32
 raw register data
++struct {
   unsigned   sesreqscs:1
   unsigned   sesreq:1
   unsigned   reserved2_7:6
   unsigned   hstnegscs:1
   unsigned   hnpreq:1
   unsigned   hstsethnpen:1
   unsigned   devhnpen:1
   unsigned   reserved12_15:4
   unsigned   conidsts:1
   unsigned   reserved17:1
   unsigned   asesvld:1
   unsigned   bsesvld:1
   unsigned   currmod:1
   unsigned   reserved21_31:11
} b
 register bits
++

Detailed Description

++This union represents the bit fields of the Core OTG Control and Status Register (GOTGCTL). ++

++Set the bits using the bit fields then write the d32 value to the register. ++

++ ++

++Definition at line 152 of file dwc_otg_regs.h.

The documentation for this union was generated from the following file: ++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/uniongotgint__data.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/uniongotgint__data.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,79 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: gotgint_data Union Reference ++ ++ ++ ++ ++
++
++
++
++

gotgint_data Union Reference

This union represents the bit fields of the Core OTG Interrupt Register (GOTGINT). ++More... ++

++#include <dwc_otg_regs.h> ++

++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++

Data Fields

++uint32_t d32
 raw register data
++struct {
   unsigned   reserved0_1:2
 Current Mode.
   unsigned   sesenddet:1
 Session End Detected.
   unsigned   reserved3_7:5
   unsigned   sesreqsucstschng:1
 Session Request Success Status Change.
   unsigned   hstnegsucstschng:1
 Host Negotiation Success Status Change.
   unsigned   reserver10_16:7
   unsigned   hstnegdet:1
 Host Negotiation Detected.
   unsigned   adevtoutchng:1
 A-Device Timeout Change.
   unsigned   debdone:1
 Debounce Done.
   unsigned   reserved31_20:12
} b
 register bits
++

Detailed Description

++This union represents the bit fields of the Core OTG Interrupt Register (GOTGINT). ++

++Set/clear the bits using the bit fields then write the d32 value to the register. ++

++ ++

++Definition at line 179 of file dwc_otg_regs.h.

The documentation for this union was generated from the following file: ++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/uniongrstctl__data.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/uniongrstctl__data.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,249 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: grstctl_data Union Reference ++ ++ ++ ++ ++
++
++
++
++

grstctl_data Union Reference

This union represents the bit fields of the Core Reset Register (GRSTCTL). ++More... ++

++#include <dwc_otg_regs.h> ++

++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++

Data Fields

++uint32_t d32
 raw register data
++struct {
   unsigned   csftrst:1
 Core Soft Reset (CSftRst) (Device and Host).
   unsigned   hsftrst:1
 Hclk Soft Reset.
   unsigned   hstfrm:1
 Host Frame Counter Reset (Host Only)
++.
   unsigned   intknqflsh:1
 In Token Sequence Learning Queue Flush (INTknQFlsh) (Device Only).
   unsigned   rxfflsh:1
 RxFIFO Flush (RxFFlsh) (Device and Host).
   unsigned   txfflsh:1
 TxFIFO Flush (TxFFlsh) (Device and Host).
   unsigned   txfnum:5
 TxFIFO Number (TxFNum) (Device and Host).
   unsigned   reserved11_29:19
 Reserved.
   unsigned   dmareq:1
 DMA Request Signal.
   unsigned   ahbidle:1
 AHB Master Idle.
} b
 register bits
++

Detailed Description

++This union represents the bit fields of the Core Reset Register (GRSTCTL). ++

++Set/clear the bits using the bit fields then write the d32 value to the register. ++

++ ++

++Definition at line 388 of file dwc_otg_regs.h.

Field Documentation

++ ++
++
++ ++ ++ ++ ++
unsigned grstctl_data::csftrst
++
++
++ ++

++Core Soft Reset (CSftRst) (Device and Host). ++

++The application can flush the control logic in the entire core using this bit. This bit resets the pipelines in the AHB Clock domain as well as the PHY Clock domain.

++The state machines are reset to an IDLE state, the control bits in the CSRs are cleared, all the transmit FIFOs and the receive FIFO are flushed.

++The status mask bits that control the generation of the interrupt, are cleared, to clear the interrupt. The interrupt status bits are not cleared, so the application can get the status of any events that occurred in the core after it has set this bit.

++Any transactions on the AHB are terminated as soon as possible following the protocol. Any transactions on the USB are terminated immediately.

++The configuration settings in the CSRs are unchanged, so the software doesn't have to reprogram these registers (Device Configuration/Host Configuration/Core System Configuration/Core PHY Configuration).

++The application can write to this bit, any time it wants to reset the core. This is a self clearing bit and the core clears this bit after all the necessary logic is reset in the core, which may take several clocks, depending on the current state of the core. ++

++Definition at line 428 of file dwc_otg_regs.h. ++

++

++ ++

++
++ ++ ++ ++ ++
unsigned grstctl_data::hsftrst
++
++
++ ++

++Hclk Soft Reset. ++

++The application uses this bit to reset the control logic in the AHB clock domain. Only AHB clock domain pipelines are reset. ++

++Definition at line 435 of file dwc_otg_regs.h. ++

++

++ ++

++
++ ++ ++ ++ ++
unsigned grstctl_data::hstfrm
++
++
++ ++

++Host Frame Counter Reset (Host Only)
++. ++

++The application can reset the (micro)frame number counter inside the core, using this bit. When the (micro)frame counter is reset, the subsequent SOF sent out by the core, will have a (micro)frame number of 0. ++

++Definition at line 444 of file dwc_otg_regs.h. ++

++

++ ++

++
++ ++ ++ ++ ++
unsigned grstctl_data::rxfflsh
++
++
++ ++

++RxFIFO Flush (RxFFlsh) (Device and Host). ++

++The application can flush the entire Receive FIFO using this bit.

++The application must first ensure that the core is not in the middle of a transaction.

++The application should write into this bit, only after making sure that neither the DMA engine is reading from the RxFIFO nor the MAC is writing the data in to the FIFO.

++The application should wait until the bit is cleared before performing any other operations. This bit will takes 8 clocks (slowest of PHY or AHB clock) to clear. ++

++Definition at line 463 of file dwc_otg_regs.h. ++

++

++ ++

++
++ ++ ++ ++ ++
unsigned grstctl_data::txfflsh
++
++
++ ++

++TxFIFO Flush (TxFFlsh) (Device and Host). ++

++This bit is used to selectively flush a single or all transmit FIFOs. The application must first ensure that the core is not in the middle of a transaction.

++The application should write into this bit, only after making sure that neither the DMA engine is writing into the TxFIFO nor the MAC is reading the data out of the FIFO.

++The application should wait until the core clears this bit, before performing any operations. This bit will takes 8 clocks (slowest of PHY or AHB clock) to clear. ++

++Definition at line 478 of file dwc_otg_regs.h. ++

++

++ ++

++
++ ++ ++ ++ ++
unsigned grstctl_data::txfnum
++
++
++ ++

++TxFIFO Number (TxFNum) (Device and Host). ++

++This is the FIFO number which needs to be flushed, using the TxFIFO Flush bit. This field should not be changed until the TxFIFO Flush bit is cleared by the core.

    ++
  • 0x0 : Non Periodic TxFIFO Flush
  • 0x1 : Periodic TxFIFO #1 Flush in device mode or Periodic TxFIFO in host mode
  • 0x2 : Periodic TxFIFO #2 Flush in device mode.
  • ...
  • 0xF : Periodic TxFIFO #15 Flush in device mode
  • 0x10: Flush all the Transmit NonPeriodic and Transmit Periodic FIFOs in the core
++ ++

++Definition at line 495 of file dwc_otg_regs.h. ++

++

++ ++

++
++ ++ ++ ++ ++
unsigned grstctl_data::dmareq
++
++
++ ++

++DMA Request Signal. ++

++Indicated DMA request is in probress. Used for debug purpose. ++

++Definition at line 500 of file dwc_otg_regs.h. ++

++

++ ++

++
++ ++ ++ ++ ++
unsigned grstctl_data::ahbidle
++
++
++ ++

++AHB Master Idle. ++

++Indicates the AHB Master State Machine is in IDLE condition. ++

++Definition at line 503 of file dwc_otg_regs.h. ++

++

++

The documentation for this union was generated from the following file: ++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/uniongusbcfg__data.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/uniongusbcfg__data.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,98 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: gusbcfg_data Union Reference ++ ++ ++ ++ ++
++
++
++
++

gusbcfg_data Union Reference

This union represents the bit fields of the Core USB Configuration Register (GUSBCFG). ++More... ++

++#include <dwc_otg_regs.h> ++

++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++

Data Fields

++uint32_t d32
 raw register data
++struct {
   unsigned   toutcal:3
   unsigned   phyif:1
   unsigned   ulpi_utmi_sel:1
   unsigned   fsintf:1
   unsigned   physel:1
   unsigned   ddrsel:1
   unsigned   srpcap:1
   unsigned   hnpcap:1
   unsigned   usbtrdtim:4
   unsigned   nptxfrwnden:1
   unsigned   phylpwrclksel:1
   unsigned   otgutmifssel:1
   unsigned   ulpi_fsls:1
   unsigned   ulpi_auto_res:1
   unsigned   ulpi_clk_sus_m:1
   unsigned   ulpi_ext_vbus_drv:1
   unsigned   ulpi_int_vbus_indicator:1
   unsigned   term_sel_dl_pulse:1
   unsigned   reserved23_25:3
   unsigned   ic_usb_cap:1
   unsigned   ic_traffic_pull_remove:1
   unsigned   tx_end_delay:1
   unsigned   reserved29_31:3
} b
 register bits
++

Detailed Description

++This union represents the bit fields of the Core USB Configuration Register (GUSBCFG). ++

++Set the bits using the bit fields then write the d32 value to the register. ++

++ ++

++Definition at line 247 of file dwc_otg_regs.h.

The documentation for this union was generated from the following file: ++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/unionhaint__data.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/unionhaint__data.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,93 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: haint_data Union Reference ++ ++ ++ ++ ++
++
++
++
++

haint_data Union Reference

This union represents the bit fields in the Host All Interrupt Register. ++More... ++

++#include <dwc_otg_regs.h> ++

++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++

Data Fields

++uint32_t d32
 raw register data
++struct {
   unsigned   ch0:1
   unsigned   ch1:1
   unsigned   ch2:1
   unsigned   ch3:1
   unsigned   ch4:1
   unsigned   ch5:1
   unsigned   ch6:1
   unsigned   ch7:1
   unsigned   ch8:1
   unsigned   ch9:1
   unsigned   ch10:1
   unsigned   ch11:1
   unsigned   ch12:1
   unsigned   ch13:1
   unsigned   ch14:1
   unsigned   ch15:1
   unsigned   reserved:16
} b
 register bits
++struct {
   unsigned   chint:16
   unsigned   reserved:16
} b2
++

Detailed Description

++This union represents the bit fields in the Host All Interrupt Register. ++

++ ++

++Definition at line 1771 of file dwc_otg_regs.h.

The documentation for this union was generated from the following file: ++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/unionhaintmsk__data.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/unionhaintmsk__data.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,93 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: haintmsk_data Union Reference ++ ++ ++ ++ ++
++
++
++
++

haintmsk_data Union Reference

This union represents the bit fields in the Host All Interrupt Register. ++More... ++

++#include <dwc_otg_regs.h> ++

++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++

Data Fields

++uint32_t d32
 raw register data
++struct {
   unsigned   ch0:1
   unsigned   ch1:1
   unsigned   ch2:1
   unsigned   ch3:1
   unsigned   ch4:1
   unsigned   ch5:1
   unsigned   ch6:1
   unsigned   ch7:1
   unsigned   ch8:1
   unsigned   ch9:1
   unsigned   ch10:1
   unsigned   ch11:1
   unsigned   ch12:1
   unsigned   ch13:1
   unsigned   ch14:1
   unsigned   ch15:1
   unsigned   reserved:16
} b
 register bits
++struct {
   unsigned   chint:16
   unsigned   reserved:16
} b2
++

Detailed Description

++This union represents the bit fields in the Host All Interrupt Register. ++

++ ++

++Definition at line 1805 of file dwc_otg_regs.h.

The documentation for this union was generated from the following file: ++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/unionhcchar__data.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/unionhcchar__data.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,123 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: hcchar_data Union Reference ++ ++ ++ ++ ++
++
++
++
++

hcchar_data Union Reference

This union represents the bit fields in the Host Channel Characteristics Register. ++More... ++

++#include <dwc_otg_regs.h> ++

++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++

Data Fields

++uint32_t d32
 raw register data
++struct {
   unsigned   mps:11
 Maximum packet size in bytes.
   unsigned   epnum:4
 Endpoint number.
   unsigned   epdir:1
 0: OUT, 1: IN
   unsigned   reserved:1
   unsigned   lspddev:1
 0: Full/high speed device, 1: Low speed device
   unsigned   eptype:2
 0: Control, 1: Isoc, 2: Bulk, 3: Intr
   unsigned   multicnt:2
 Packets per frame for periodic transfers.
   unsigned   devaddr:7
 Device address.
   unsigned   oddfrm:1
 Frame to transmit periodic transaction.
   unsigned   chdis:1
 Channel disable.
   unsigned   chen:1
 Channel enable.
} b
 register bits
++

Detailed Description

++This union represents the bit fields in the Host Channel Characteristics Register. ++

++Read the register into the d32 member then set/clear the bits using the bit elements. Write the d32 member to the hcchar register. ++

++ ++

++Definition at line 1863 of file dwc_otg_regs.h.

Field Documentation

++ ++
++
++ ++ ++ ++ ++
unsigned hcchar_data::multicnt
++
++
++ ++

++Packets per frame for periodic transfers. ++

++0 is reserved. ++

++Definition at line 1887 of file dwc_otg_regs.h. ++

++

++ ++

++
++ ++ ++ ++ ++
unsigned hcchar_data::oddfrm
++
++
++ ++

++Frame to transmit periodic transaction. ++

++0: even, 1: odd ++

++Definition at line 1896 of file dwc_otg_regs.h. ++

++

++

The documentation for this union was generated from the following file: ++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/unionhcdma__data.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/unionhcdma__data.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,78 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: hcdma_data Union Reference ++ ++ ++ ++ ++
++
++
++
++

hcdma_data Union Reference

This union represents the bit fields in the Host DMA Address Register used in Descriptor DMA mode. ++More... ++

++#include <dwc_otg_regs.h> ++

++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++

Data Fields

++uint32_t d32
 raw register data
++struct {
   unsigned   reserved0_2: 3
   unsigned   ctd: 8
 Current Transfer Descriptor.
   unsigned   dma_addr: 21
 Start Address of Descriptor List.
} b
 register bits
++

Detailed Description

++This union represents the bit fields in the Host DMA Address Register used in Descriptor DMA mode. ++

++ ++

++Definition at line 2086 of file dwc_otg_regs.h.

Field Documentation

++ ++
++
++ ++ ++ ++ ++
unsigned hcdma_data::ctd
++
++
++ ++

++Current Transfer Descriptor. ++

++Not used for ISOC ++

++Definition at line 2095 of file dwc_otg_regs.h. ++

++

++

The documentation for this union was generated from the following file: ++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/unionhcfg__data.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/unionhcfg__data.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,72 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: hcfg_data Union Reference ++ ++ ++ ++ ++
++
++
++
++

hcfg_data Union Reference

This union represents the bit fields in the Host Configuration Register. ++More... ++

++#include <dwc_otg_regs.h> ++

++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++

Data Fields

++uint32_t d32
 raw register data
++struct {
   unsigned   fslspclksel:2
 FS/LS Phy Clock Select.
   unsigned   fslssupp:1
 FS/LS Only Support.
   unsigned   reserved3_22: 20
   unsigned   descdma: 1
 Enable Scatter/gather DMA in Host mode.
   unsigned   frlisten: 2
 Frame List Entries.
   unsigned   perschedena: 1
 Enable Periodic Scheduling.
   unsigned   perschedstat: 1
 Periodic Scheduling Enabled Status.
} b
 register bits
++

Detailed Description

++This union represents the bit fields in the Host Configuration Register. ++

++Read the register into the d32 member then set/clear the bits using the bit elements. Write the d32 member to the hcfg register. ++

++ ++

++Definition at line 1652 of file dwc_otg_regs.h.

The documentation for this union was generated from the following file: ++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/unionhcint__data.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/unionhcint__data.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,95 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: hcint_data Union Reference ++ ++ ++ ++ ++
++
++
++
++

hcint_data Union Reference

This union represents the bit fields in the Host All Interrupt Register. ++More... ++

++#include <dwc_otg_regs.h> ++

++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++

Data Fields

++uint32_t d32
 raw register data
++struct {
   unsigned   xfercomp:1
 Transfer Complete.
   unsigned   chhltd:1
 Channel Halted.
   unsigned   ahberr:1
 AHB Error.
   unsigned   stall:1
 STALL Response Received.
   unsigned   nak:1
 NAK Response Received.
   unsigned   ack:1
 ACK Response Received.
   unsigned   nyet:1
 NYET Response Received.
   unsigned   xacterr:1
 Transaction Err.
   unsigned   bblerr:1
 Babble Error.
   unsigned   frmovrun:1
 Frame Overrun.
   unsigned   datatglerr:1
 Data Toggle Error.
   unsigned   bna: 1
 Buffer Not Available (only for DDMA mode).
   unsigned   xcs_xact: 1
 Exessive transaction error (only for DDMA mode).
   unsigned   frm_list_roll: 1
 Frame List Rollover interrupt.
   unsigned   reserved14_31: 18
 Reserved.
} b
 register bits
++

Detailed Description

++This union represents the bit fields in the Host All Interrupt Register. ++

++ ++

++Definition at line 1940 of file dwc_otg_regs.h.

The documentation for this union was generated from the following file: ++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/unionhcintmsk__data.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/unionhcintmsk__data.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,82 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: hcintmsk_data Union Reference ++ ++ ++ ++ ++
++
++
++
++

hcintmsk_data Union Reference

This union represents the bit fields in the Host Channel Interrupt Mask Register. ++More... ++

++#include <dwc_otg_regs.h> ++

++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++

Data Fields

++uint32_t d32
 raw register data
++struct {
   unsigned   xfercompl: 1
   unsigned   chhltd: 1
   unsigned   ahberr: 1
   unsigned   stall: 1
   unsigned   nak: 1
   unsigned   ack: 1
   unsigned   nyet: 1
   unsigned   xacterr: 1
   unsigned   bblerr: 1
   unsigned   frmovrun: 1
   unsigned   datatglerr: 1
   unsigned   bna: 1
   unsigned   xcs_xact: 1
   unsigned   frm_list_roll: 1
   unsigned   reserved14_31: 18
} b
 register bits
++

Detailed Description

++This union represents the bit fields in the Host Channel Interrupt Mask Register. ++

++Read the register into the d32 member then set/clear the bits using the bit elements. Write the d32 member to the hcintmsk register. ++

++ ++

++Definition at line 1986 of file dwc_otg_regs.h.

The documentation for this union was generated from the following file: ++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/unionhcsplt__data.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/unionhcsplt__data.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,63 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: hcsplt_data Union Reference ++ ++ ++ ++ ++
++
++
++
++

hcsplt_data Union Reference

++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++

Data Fields

++uint32_t d32
 raw register data
++struct {
   unsigned   prtaddr:7
 Port Address.
   unsigned   hubaddr:7
 Hub Address.
   unsigned   xactpos:2
 Transaction Position.
   unsigned   compsplt:1
 Do Complete Split.
   unsigned   reserved:14
 Reserved.
   unsigned   spltena:1
 Split Enble.
} b
 register bits
++

Detailed Description

++ ++

++ ++

++Definition at line 1906 of file dwc_otg_regs.h.

The documentation for this union was generated from the following file: ++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/unionhctsiz__data.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/unionhctsiz__data.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,105 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: hctsiz_data Union Reference ++ ++ ++ ++ ++
++
++
++
++

hctsiz_data Union Reference

This union represents the bit fields in the Host Channel Transfer Size Register. ++More... ++

++#include <dwc_otg_regs.h> ++

++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++

Data Fields

++uint32_t d32
 raw register data
++struct {
   unsigned   xfersize:19
 Total transfer size in bytes.
   unsigned   pktcnt:10
 Data packets to transfer.
   unsigned   pid:2
 Packet ID for next data packet 0: DATA0 1: DATA2 2: DATA1 3: MDATA (non-Control), SETUP (Control).
   unsigned   dopng:1
 Do PING protocol when 1.
} b
 register bits
++struct {
   unsigned   schinfo: 8
 Scheduling information.
   unsigned   ntd: 8
 Number of transfer descriptors.
   unsigned   reserved16_28: 13
 Data packets to transfer.
   unsigned   pid: 2
 Packet ID for next data packet 0: DATA0 1: DATA2 2: DATA1 3: MDATA (non-Control).
   unsigned   dopng: 1
 Do PING protocol when 1.
} b_ddma
 register bits
++

Detailed Description

++This union represents the bit fields in the Host Channel Transfer Size Register. ++

++Read the register into the d32 member then set/clear the bits using the bit elements. Write the d32 member to the hcchar register. ++

++ ++

++Definition at line 2019 of file dwc_otg_regs.h.

Field Documentation

++ ++
++
++ ++ ++ ++ ++
unsigned hctsiz_data::ntd
++
++
++ ++

++Number of transfer descriptors. ++

++Max value: 64 in general, 256 only for HS isochronous endpoint. ++

++Definition at line 2062 of file dwc_otg_regs.h. ++

++

++

The documentation for this union was generated from the following file: ++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/unionhfir__data.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/unionhfir__data.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,54 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: hfir_data Union Reference ++ ++ ++ ++ ++
++
++
++
++

hfir_data Union Reference

This union represents the bit fields in the Host Frame Remaing/Number Register. ++More... ++

++#include <dwc_otg_regs.h> ++

++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++

Data Fields

++uint32_t d32
 raw register data
++struct {
   unsigned   frint:16
   unsigned   reserved:16
} b
 register bits
++

Detailed Description

++This union represents the bit fields in the Host Frame Remaing/Number Register. ++

++ ++

++Definition at line 1684 of file dwc_otg_regs.h.

The documentation for this union was generated from the following file: ++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/unionhfnum__data.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/unionhfnum__data.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,54 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: hfnum_data Union Reference ++ ++ ++ ++ ++
++
++
++
++

hfnum_data Union Reference

This union represents the bit fields in the Host Frame Remaing/Number Register. ++More... ++

++#include <dwc_otg_regs.h> ++

++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++

Data Fields

++uint32_t d32
 raw register data
++struct {
   unsigned   frnum:16
   unsigned   frrem:16
} b
 register bits
++

Detailed Description

++This union represents the bit fields in the Host Frame Remaing/Number Register. ++

++ ++

++Definition at line 1699 of file dwc_otg_regs.h.

The documentation for this union was generated from the following file: ++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/unionhost__dma__desc__sts.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/unionhost__dma__desc__sts.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,123 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: host_dma_desc_sts Union Reference ++ ++ ++ ++ ++
++
++
++
++

host_dma_desc_sts Union Reference

This union represents the bit fields in the DMA Descriptor status quadlet for host mode. ++More... ++

++#include <dwc_otg_regs.h> ++

++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++

Data Fields

++uint32_t d32
 raw register data
++struct {
   unsigned   n_bytes: 17
 Number of bytes.
   unsigned   qtd_offset: 6
 QTD offset to jump when Short Packet received - only for IN EPs.
   unsigned   a_qtd: 1
 Set to request the core to jump to alternate QTD if Short Packet received - only for IN EPs.
   unsigned   sup: 1
 Setup Packet bit.
   unsigned   ioc: 1
 Interrupt On Complete.
   unsigned   eol: 1
 End of List.
   unsigned   reserved27: 1
   unsigned   sts: 2
 Rx/Tx Status.
   unsigned   reserved30: 1
   unsigned   a: 1
 Active Bit.
} b
 quadlet bits
++struct {
   unsigned   n_bytes: 12
 Number of bytes.
   unsigned   reserved12_24: 13
   unsigned   ioc: 1
 Interrupt On Complete.
   unsigned   reserved26_27: 2
   unsigned   sts: 2
 Rx/Tx Status.
   unsigned   reserved30: 1
   unsigned   a: 1
 Active Bit.
} b_isoc
++

Detailed Description

++This union represents the bit fields in the DMA Descriptor status quadlet for host mode. ++

++Read the quadlet into the d32 member then set/clear the bits using the bit elements. ++

++ ++

++Definition at line 2106 of file dwc_otg_regs.h.

Field Documentation

++ ++
++
++ ++ ++ ++ ++
unsigned host_dma_desc_sts::sup
++
++
++ ++

++Setup Packet bit. ++

++When set indicates that buffer contains setup packet. ++

++Definition at line 2127 of file dwc_otg_regs.h. ++

++

++

The documentation for this union was generated from the following file: ++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/unionhost__grxsts__data.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/unionhost__grxsts__data.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,60 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: host_grxsts_data Union Reference ++ ++ ++ ++ ++
++
++
++
++

host_grxsts_data Union Reference

This union represents the bit fields in the Host Receive Status Read and Pop Registers (GRXSTSR, GRXSTSP) Read the register into the d32 element then read out the bits using the bit elements. ++More... ++

++#include <dwc_otg_regs.h> ++

++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++

Data Fields

++uint32_t d32
 raw register data
++struct {
   unsigned   chnum:4
   unsigned   bcnt:11
   unsigned   dpid:2
   unsigned   pktsts:4
   unsigned   reserved:11
} b
 register bits
++

Detailed Description

++This union represents the bit fields in the Host Receive Status Read and Pop Registers (GRXSTSR, GRXSTSP) Read the register into the d32 element then read out the bits using the bit elements. ++

++ ++

++Definition at line 627 of file dwc_otg_regs.h.

The documentation for this union was generated from the following file: ++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/unionhprt0__data.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/unionhprt0__data.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,82 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: hprt0_data Union Reference ++ ++ ++ ++ ++
++
++
++
++

hprt0_data Union Reference

This union represents the bit fields in the Host Port Control and Status Register. ++More... ++

++#include <dwc_otg_regs.h> ++

++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++

Data Fields

++uint32_t d32
 raw register data
++struct {
   unsigned   prtconnsts:1
   unsigned   prtconndet:1
   unsigned   prtena:1
   unsigned   prtenchng:1
   unsigned   prtovrcurract:1
   unsigned   prtovrcurrchng:1
   unsigned   prtres:1
   unsigned   prtsusp:1
   unsigned   prtrst:1
   unsigned   reserved9:1
   unsigned   prtlnsts:2
   unsigned   prtpwr:1
   unsigned   prttstctl:4
   unsigned   prtspd:2
   unsigned   reserved19_31:13
} b
 register bits
++

Detailed Description

++This union represents the bit fields in the Host Port Control and Status Register. ++

++Read the register into the d32 member then set/clear the bits using the bit elements. Write the d32 member to the hprt0 register. ++

++ ++

++Definition at line 1741 of file dwc_otg_regs.h.

The documentation for this union was generated from the following file: ++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/unionhptxsts__data.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/unionhptxsts__data.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,62 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: hptxsts_data Union Reference ++ ++ ++ ++ ++
++
++
++
++

hptxsts_data Union Reference

++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++

Data Fields

++uint32_t d32
 raw register data
++struct {
   unsigned   ptxfspcavail:16
   unsigned   ptxqspcavail:8
   unsigned   ptxqtop_terminate:1
 Top of the Periodic Transmit Request Queue
    ++
  • bit 24 - Terminate (last entry for the selected channel)
  • bits 26:25 - Token Type
      ++
    • 2'b00 - Zero length
    • 2'b01 - Ping
    • 2'b10 - Disable
    ++
  • bits 30:27 - Channel Number
  • bit 31 - Odd/even microframe.
++
   unsigned   ptxqtop_token:2
   unsigned   ptxqtop_chnum:4
   unsigned   ptxqtop_odd:1
} b
 register bits
++

Detailed Description

++ ++

++ ++

++Definition at line 1711 of file dwc_otg_regs.h.

The documentation for this union was generated from the following file: ++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/unionhwcfg1__data.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/unionhwcfg1__data.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,84 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: hwcfg1_data Union Reference ++ ++ ++ ++ ++
++
++
++
++

hwcfg1_data Union Reference

This union represents the bit fields in the User HW Config1 Register. ++More... ++

++#include <dwc_otg_regs.h> ++

++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++

Data Fields

++uint32_t d32
 raw register data
++struct {
   unsigned   ep_dir0:2
   unsigned   ep_dir1:2
   unsigned   ep_dir2:2
   unsigned   ep_dir3:2
   unsigned   ep_dir4:2
   unsigned   ep_dir5:2
   unsigned   ep_dir6:2
   unsigned   ep_dir7:2
   unsigned   ep_dir8:2
   unsigned   ep_dir9:2
   unsigned   ep_dir10:2
   unsigned   ep_dir11:2
   unsigned   ep_dir12:2
   unsigned   ep_dir13:2
   unsigned   ep_dir14:2
   unsigned   ep_dir15:2
} b
 register bits
++

Detailed Description

++This union represents the bit fields in the User HW Config1 Register. ++

++Read the register into the d32 element then read out the bits using the bit elements. ++

++ ++

++Definition at line 735 of file dwc_otg_regs.h.

The documentation for this union was generated from the following file: ++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/unionhwcfg2__data.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/unionhwcfg2__data.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,82 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: hwcfg2_data Union Reference ++ ++ ++ ++ ++
++
++
++
++

hwcfg2_data Union Reference

This union represents the bit fields in the User HW Config2 Register. ++More... ++

++#include <dwc_otg_regs.h> ++

++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++

Data Fields

++uint32_t d32
 raw register data
++struct {
   unsigned   op_mode:3
   unsigned   architecture:2
   unsigned   point2point:1
   unsigned   hs_phy_type:2
   unsigned   fs_phy_type:2
   unsigned   num_dev_ep:4
   unsigned   num_host_chan:4
   unsigned   perio_ep_supported:1
   unsigned   dynamic_fifo:1
   unsigned   multi_proc_int:1
   unsigned   reserved21:1
   unsigned   nonperio_tx_q_depth:2
   unsigned   host_perio_tx_q_depth:2
   unsigned   dev_token_q_depth:5
   unsigned   reserved31:1
} b
 register bits
++

Detailed Description

++This union represents the bit fields in the User HW Config2 Register. ++

++Read the register into the d32 element then read out the bits using the bit elements. ++

++ ++

++Definition at line 764 of file dwc_otg_regs.h.

The documentation for this union was generated from the following file: ++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/unionhwcfg3__data.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/unionhwcfg3__data.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,76 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: hwcfg3_data Union Reference ++ ++ ++ ++ ++
++
++
++
++

hwcfg3_data Union Reference

This union represents the bit fields in the User HW Config3 Register. ++More... ++

++#include <dwc_otg_regs.h> ++

++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++

Data Fields

++uint32_t d32
 raw register data
++struct {
   unsigned   xfer_size_cntr_width:4
   unsigned   packet_size_cntr_width:3
   unsigned   otg_func:1
   unsigned   i2c:1
   unsigned   vendor_ctrl_if:1
   unsigned   optional_features:1
   unsigned   synch_reset_type:1
   unsigned   otg_enable_ic_usb:1
   unsigned   otg_enable_hsic:1
   unsigned   reserved14:1
   unsigned   otg_lpm_en:1
   unsigned   dfifo_depth:16
} b
 register bits
++

Detailed Description

++This union represents the bit fields in the User HW Config3 Register. ++

++Read the register into the d32 element then read out the bits using the bit elements. ++

++ ++

++Definition at line 806 of file dwc_otg_regs.h.

The documentation for this union was generated from the following file: ++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/unionhwcfg4__data.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/unionhwcfg4__data.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,80 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: hwcfg4_data Union Reference ++ ++ ++ ++ ++
++
++
++
++

hwcfg4_data Union Reference

This union represents the bit fields in the User HW Config4 Register. ++More... ++

++#include <dwc_otg_regs.h> ++

++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++

Data Fields

++uint32_t d32
 raw register data
++struct {
   unsigned   num_dev_perio_in_ep:4
   unsigned   power_optimiz:1
   unsigned   min_ahb_freq:9
   unsigned   utmi_phy_data_width:2
   unsigned   num_dev_mode_ctrl_ep:4
   unsigned   iddig_filt_en:1
   unsigned   vbus_valid_filt_en:1
   unsigned   a_valid_filt_en:1
   unsigned   b_valid_filt_en:1
   unsigned   session_end_filt_en:1
   unsigned   ded_fifo_en:1
   unsigned   num_in_eps:4
   unsigned   desc_dma:1
   unsigned   desc_dma_dyn:1
} b
 register bits
++

Detailed Description

++This union represents the bit fields in the User HW Config4 Register. ++

++Read the register into the d32 element then read out the bits using the bit elements. ++

++ ++

++Definition at line 832 of file dwc_otg_regs.h.

The documentation for this union was generated from the following file: ++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/unionpcgcctl__data.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/unionpcgcctl__data.html 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,78 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: pcgcctl_data Union Reference ++ ++ ++ ++ ++
++
++
++
++

pcgcctl_data Union Reference

This union represents the bit fields in the Power and Clock Gating Control Register. ++More... ++

++#include <dwc_otg_regs.h> ++

++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++

Data Fields

++uint32_t d32
 raw register data
++struct {
   unsigned   stoppclk:1
 Stop Pclk.
   unsigned   gatehclk:1
 Gate Hclk.
   unsigned   pwrclmp:1
 Power Clamp.
   unsigned   rstpdwnmodule:1
 Reset Power Down Modules.
   unsigned   physuspended:1
 PHY Suspended.
   unsigned   enbl_sleep_gating:1
 Enable Sleep Clock Gating (Enbl_L1Gating).
   unsigned   phy_in_sleep:1
 PHY In Sleep (PhySleep).
   unsigned   deep_sleep:1
 Deep Sleep.
   unsigned   reserved31_8:24
} b
 register bits
++

Detailed Description

++This union represents the bit fields in the Power and Clock Gating Control Register. ++

++Read the register into the d32 member then set/clear the bits using the bit elements. ++

++ ++

++Definition at line 2210 of file dwc_otg_regs.h.

The documentation for this union was generated from the following file: ++
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.4.7
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/dummy_audio.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/dummy_audio.c 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,1575 @@ ++/* ++ * zero.c -- Gadget Zero, for USB development ++ * ++ * Copyright (C) 2003-2004 David Brownell ++ * All rights reserved. ++ * ++ * Redistribution and use in source and binary forms, with or without ++ * modification, are permitted provided that the following conditions ++ * are met: ++ * 1. Redistributions of source code must retain the above copyright ++ * notice, this list of conditions, and the following disclaimer, ++ * without modification. ++ * 2. Redistributions in binary form must reproduce the above copyright ++ * notice, this list of conditions and the following disclaimer in the ++ * documentation and/or other materials provided with the distribution. ++ * 3. The names of the above-listed copyright holders may not be used ++ * to endorse or promote products derived from this software without ++ * specific prior written permission. ++ * ++ * ALTERNATIVELY, this software may be distributed under the terms of the ++ * GNU General Public License ("GPL") as published by the Free Software ++ * Foundation, either version 2 of that License or (at your option) any ++ * later version. ++ * ++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS ++ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, ++ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR ++ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR ++ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, ++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, ++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR ++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ++ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING ++ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ++ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ++ */ ++ ++ ++/* ++ * Gadget Zero only needs two bulk endpoints, and is an example of how you ++ * can write a hardware-agnostic gadget driver running inside a USB device. ++ * ++ * Hardware details are visible (see CONFIG_USB_ZERO_* below) but don't ++ * affect most of the driver. ++ * ++ * Use it with the Linux host/master side "usbtest" driver to get a basic ++ * functional test of your device-side usb stack, or with "usb-skeleton". ++ * ++ * It supports two similar configurations. One sinks whatever the usb host ++ * writes, and in return sources zeroes. The other loops whatever the host ++ * writes back, so the host can read it. Module options include: ++ * ++ * buflen=N default N=4096, buffer size used ++ * qlen=N default N=32, how many buffers in the loopback queue ++ * loopdefault default false, list loopback config first ++ * ++ * Many drivers will only have one configuration, letting them be much ++ * simpler if they also don't support high speed operation (like this ++ * driver does). ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,21) ++# include ++#else ++# include ++#endif ++ ++#include ++ ++ ++/*-------------------------------------------------------------------------*/ ++/*-------------------------------------------------------------------------*/ ++ ++ ++static int utf8_to_utf16le(const char *s, u16 *cp, unsigned len) ++{ ++ int count = 0; ++ u8 c; ++ u16 uchar; ++ ++ /* this insists on correct encodings, though not minimal ones. ++ * BUT it currently rejects legit 4-byte UTF-8 code points, ++ * which need surrogate pairs. (Unicode 3.1 can use them.) ++ */ ++ while (len != 0 && (c = (u8) *s++) != 0) { ++ if (unlikely(c & 0x80)) { ++ // 2-byte sequence: ++ // 00000yyyyyxxxxxx = 110yyyyy 10xxxxxx ++ if ((c & 0xe0) == 0xc0) { ++ uchar = (c & 0x1f) << 6; ++ ++ c = (u8) *s++; ++ if ((c & 0xc0) != 0xc0) ++ goto fail; ++ c &= 0x3f; ++ uchar |= c; ++ ++ // 3-byte sequence (most CJKV characters): ++ // zzzzyyyyyyxxxxxx = 1110zzzz 10yyyyyy 10xxxxxx ++ } else if ((c & 0xf0) == 0xe0) { ++ uchar = (c & 0x0f) << 12; ++ ++ c = (u8) *s++; ++ if ((c & 0xc0) != 0xc0) ++ goto fail; ++ c &= 0x3f; ++ uchar |= c << 6; ++ ++ c = (u8) *s++; ++ if ((c & 0xc0) != 0xc0) ++ goto fail; ++ c &= 0x3f; ++ uchar |= c; ++ ++ /* no bogus surrogates */ ++ if (0xd800 <= uchar && uchar <= 0xdfff) ++ goto fail; ++ ++ // 4-byte sequence (surrogate pairs, currently rare): ++ // 11101110wwwwzzzzyy + 110111yyyyxxxxxx ++ // = 11110uuu 10uuzzzz 10yyyyyy 10xxxxxx ++ // (uuuuu = wwww + 1) ++ // FIXME accept the surrogate code points (only) ++ ++ } else ++ goto fail; ++ } else ++ uchar = c; ++ put_unaligned (cpu_to_le16 (uchar), cp++); ++ count++; ++ len--; ++ } ++ return count; ++fail: ++ return -1; ++} ++ ++ ++/** ++ * usb_gadget_get_string - fill out a string descriptor ++ * @table: of c strings encoded using UTF-8 ++ * @id: string id, from low byte of wValue in get string descriptor ++ * @buf: at least 256 bytes ++ * ++ * Finds the UTF-8 string matching the ID, and converts it into a ++ * string descriptor in utf16-le. ++ * Returns length of descriptor (always even) or negative errno ++ * ++ * If your driver needs stings in multiple languages, you'll probably ++ * "switch (wIndex) { ... }" in your ep0 string descriptor logic, ++ * using this routine after choosing which set of UTF-8 strings to use. ++ * Note that US-ASCII is a strict subset of UTF-8; any string bytes with ++ * the eighth bit set will be multibyte UTF-8 characters, not ISO-8859/1 ++ * characters (which are also widely used in C strings). ++ */ ++int ++usb_gadget_get_string (struct usb_gadget_strings *table, int id, u8 *buf) ++{ ++ struct usb_string *s; ++ int len; ++ ++ /* descriptor 0 has the language id */ ++ if (id == 0) { ++ buf [0] = 4; ++ buf [1] = USB_DT_STRING; ++ buf [2] = (u8) table->language; ++ buf [3] = (u8) (table->language >> 8); ++ return 4; ++ } ++ for (s = table->strings; s && s->s; s++) ++ if (s->id == id) ++ break; ++ ++ /* unrecognized: stall. */ ++ if (!s || !s->s) ++ return -EINVAL; ++ ++ /* string descriptors have length, tag, then UTF16-LE text */ ++ len = min ((size_t) 126, strlen (s->s)); ++ memset (buf + 2, 0, 2 * len); /* zero all the bytes */ ++ len = utf8_to_utf16le(s->s, (u16 *)&buf[2], len); ++ if (len < 0) ++ return -EINVAL; ++ buf [0] = (len + 1) * 2; ++ buf [1] = USB_DT_STRING; ++ return buf [0]; ++} ++ ++ ++/*-------------------------------------------------------------------------*/ ++/*-------------------------------------------------------------------------*/ ++ ++ ++/** ++ * usb_descriptor_fillbuf - fill buffer with descriptors ++ * @buf: Buffer to be filled ++ * @buflen: Size of buf ++ * @src: Array of descriptor pointers, terminated by null pointer. ++ * ++ * Copies descriptors into the buffer, returning the length or a ++ * negative error code if they can't all be copied. Useful when ++ * assembling descriptors for an associated set of interfaces used ++ * as part of configuring a composite device; or in other cases where ++ * sets of descriptors need to be marshaled. ++ */ ++int ++usb_descriptor_fillbuf(void *buf, unsigned buflen, ++ const struct usb_descriptor_header **src) ++{ ++ u8 *dest = buf; ++ ++ if (!src) ++ return -EINVAL; ++ ++ /* fill buffer from src[] until null descriptor ptr */ ++ for (; 0 != *src; src++) { ++ unsigned len = (*src)->bLength; ++ ++ if (len > buflen) ++ return -EINVAL; ++ memcpy(dest, *src, len); ++ buflen -= len; ++ dest += len; ++ } ++ return dest - (u8 *)buf; ++} ++ ++ ++/** ++ * usb_gadget_config_buf - builts a complete configuration descriptor ++ * @config: Header for the descriptor, including characteristics such ++ * as power requirements and number of interfaces. ++ * @desc: Null-terminated vector of pointers to the descriptors (interface, ++ * endpoint, etc) defining all functions in this device configuration. ++ * @buf: Buffer for the resulting configuration descriptor. ++ * @length: Length of buffer. If this is not big enough to hold the ++ * entire configuration descriptor, an error code will be returned. ++ * ++ * This copies descriptors into the response buffer, building a descriptor ++ * for that configuration. It returns the buffer length or a negative ++ * status code. The config.wTotalLength field is set to match the length ++ * of the result, but other descriptor fields (including power usage and ++ * interface count) must be set by the caller. ++ * ++ * Gadget drivers could use this when constructing a config descriptor ++ * in response to USB_REQ_GET_DESCRIPTOR. They will need to patch the ++ * resulting bDescriptorType value if USB_DT_OTHER_SPEED_CONFIG is needed. ++ */ ++int usb_gadget_config_buf( ++ const struct usb_config_descriptor *config, ++ void *buf, ++ unsigned length, ++ const struct usb_descriptor_header **desc ++) ++{ ++ struct usb_config_descriptor *cp = buf; ++ int len; ++ ++ /* config descriptor first */ ++ if (length < USB_DT_CONFIG_SIZE || !desc) ++ return -EINVAL; ++ *cp = *config; ++ ++ /* then interface/endpoint/class/vendor/... */ ++ len = usb_descriptor_fillbuf(USB_DT_CONFIG_SIZE + (u8*)buf, ++ length - USB_DT_CONFIG_SIZE, desc); ++ if (len < 0) ++ return len; ++ len += USB_DT_CONFIG_SIZE; ++ if (len > 0xffff) ++ return -EINVAL; ++ ++ /* patch up the config descriptor */ ++ cp->bLength = USB_DT_CONFIG_SIZE; ++ cp->bDescriptorType = USB_DT_CONFIG; ++ cp->wTotalLength = cpu_to_le16(len); ++ cp->bmAttributes |= USB_CONFIG_ATT_ONE; ++ return len; ++} ++ ++/*-------------------------------------------------------------------------*/ ++/*-------------------------------------------------------------------------*/ ++ ++ ++#define RBUF_LEN (1024*1024) ++static int rbuf_start; ++static int rbuf_len; ++static __u8 rbuf[RBUF_LEN]; ++ ++/*-------------------------------------------------------------------------*/ ++ ++#define DRIVER_VERSION "St Patrick's Day 2004" ++ ++static const char shortname [] = "zero"; ++static const char longname [] = "YAMAHA YST-MS35D USB Speaker "; ++ ++static const char source_sink [] = "source and sink data"; ++static const char loopback [] = "loop input to output"; ++ ++/*-------------------------------------------------------------------------*/ ++ ++/* ++ * driver assumes self-powered hardware, and ++ * has no way for users to trigger remote wakeup. ++ * ++ * this version autoconfigures as much as possible, ++ * which is reasonable for most "bulk-only" drivers. ++ */ ++static const char *EP_IN_NAME; /* source */ ++static const char *EP_OUT_NAME; /* sink */ ++ ++/*-------------------------------------------------------------------------*/ ++ ++/* big enough to hold our biggest descriptor */ ++#define USB_BUFSIZ 512 ++ ++struct zero_dev { ++ spinlock_t lock; ++ struct usb_gadget *gadget; ++ struct usb_request *req; /* for control responses */ ++ ++ /* when configured, we have one of two configs: ++ * - source data (in to host) and sink it (out from host) ++ * - or loop it back (out from host back in to host) ++ */ ++ u8 config; ++ struct usb_ep *in_ep, *out_ep; ++ ++ /* autoresume timer */ ++ struct timer_list resume; ++}; ++ ++#define xprintk(d,level,fmt,args...) \ ++ dev_printk(level , &(d)->gadget->dev , fmt , ## args) ++ ++#ifdef DEBUG ++#define DBG(dev,fmt,args...) \ ++ xprintk(dev , KERN_DEBUG , fmt , ## args) ++#else ++#define DBG(dev,fmt,args...) \ ++ do { } while (0) ++#endif /* DEBUG */ ++ ++#ifdef VERBOSE ++#define VDBG DBG ++#else ++#define VDBG(dev,fmt,args...) \ ++ do { } while (0) ++#endif /* VERBOSE */ ++ ++#define ERROR(dev,fmt,args...) \ ++ xprintk(dev , KERN_ERR , fmt , ## args) ++#define WARN(dev,fmt,args...) \ ++ xprintk(dev , KERN_WARNING , fmt , ## args) ++#define INFO(dev,fmt,args...) \ ++ xprintk(dev , KERN_INFO , fmt , ## args) ++ ++/*-------------------------------------------------------------------------*/ ++ ++static unsigned buflen = 4096; ++static unsigned qlen = 32; ++static unsigned pattern = 0; ++ ++module_param (buflen, uint, S_IRUGO|S_IWUSR); ++module_param (qlen, uint, S_IRUGO|S_IWUSR); ++module_param (pattern, uint, S_IRUGO|S_IWUSR); ++ ++/* ++ * if it's nonzero, autoresume says how many seconds to wait ++ * before trying to wake up the host after suspend. ++ */ ++static unsigned autoresume = 0; ++module_param (autoresume, uint, 0); ++ ++/* ++ * Normally the "loopback" configuration is second (index 1) so ++ * it's not the default. Here's where to change that order, to ++ * work better with hosts where config changes are problematic. ++ * Or controllers (like superh) that only support one config. ++ */ ++static int loopdefault = 0; ++ ++module_param (loopdefault, bool, S_IRUGO|S_IWUSR); ++ ++/*-------------------------------------------------------------------------*/ ++ ++/* Thanks to NetChip Technologies for donating this product ID. ++ * ++ * DO NOT REUSE THESE IDs with a protocol-incompatible driver!! Ever!! ++ * Instead: allocate your own, using normal USB-IF procedures. ++ */ ++#ifndef CONFIG_USB_ZERO_HNPTEST ++#define DRIVER_VENDOR_NUM 0x0525 /* NetChip */ ++#define DRIVER_PRODUCT_NUM 0xa4a0 /* Linux-USB "Gadget Zero" */ ++#else ++#define DRIVER_VENDOR_NUM 0x1a0a /* OTG test device IDs */ ++#define DRIVER_PRODUCT_NUM 0xbadd ++#endif ++ ++/*-------------------------------------------------------------------------*/ ++ ++/* ++ * DESCRIPTORS ... most are static, but strings and (full) ++ * configuration descriptors are built on demand. ++ */ ++ ++/* ++#define STRING_MANUFACTURER 25 ++#define STRING_PRODUCT 42 ++#define STRING_SERIAL 101 ++*/ ++#define STRING_MANUFACTURER 1 ++#define STRING_PRODUCT 2 ++#define STRING_SERIAL 3 ++ ++#define STRING_SOURCE_SINK 250 ++#define STRING_LOOPBACK 251 ++ ++/* ++ * This device advertises two configurations; these numbers work ++ * on a pxa250 as well as more flexible hardware. ++ */ ++#define CONFIG_SOURCE_SINK 3 ++#define CONFIG_LOOPBACK 2 ++ ++/* ++static struct usb_device_descriptor ++device_desc = { ++ .bLength = sizeof device_desc, ++ .bDescriptorType = USB_DT_DEVICE, ++ ++ .bcdUSB = __constant_cpu_to_le16 (0x0200), ++ .bDeviceClass = USB_CLASS_VENDOR_SPEC, ++ ++ .idVendor = __constant_cpu_to_le16 (DRIVER_VENDOR_NUM), ++ .idProduct = __constant_cpu_to_le16 (DRIVER_PRODUCT_NUM), ++ .iManufacturer = STRING_MANUFACTURER, ++ .iProduct = STRING_PRODUCT, ++ .iSerialNumber = STRING_SERIAL, ++ .bNumConfigurations = 2, ++}; ++*/ ++static struct usb_device_descriptor ++device_desc = { ++ .bLength = sizeof device_desc, ++ .bDescriptorType = USB_DT_DEVICE, ++ .bcdUSB = __constant_cpu_to_le16 (0x0100), ++ .bDeviceClass = USB_CLASS_PER_INTERFACE, ++ .bDeviceSubClass = 0, ++ .bDeviceProtocol = 0, ++ .bMaxPacketSize0 = 64, ++ .bcdDevice = __constant_cpu_to_le16 (0x0100), ++ .idVendor = __constant_cpu_to_le16 (0x0499), ++ .idProduct = __constant_cpu_to_le16 (0x3002), ++ .iManufacturer = STRING_MANUFACTURER, ++ .iProduct = STRING_PRODUCT, ++ .iSerialNumber = STRING_SERIAL, ++ .bNumConfigurations = 1, ++}; ++ ++static struct usb_config_descriptor ++z_config = { ++ .bLength = sizeof z_config, ++ .bDescriptorType = USB_DT_CONFIG, ++ ++ /* compute wTotalLength on the fly */ ++ .bNumInterfaces = 2, ++ .bConfigurationValue = 1, ++ .iConfiguration = 0, ++ .bmAttributes = 0x40, ++ .bMaxPower = 0, /* self-powered */ ++}; ++ ++ ++static struct usb_otg_descriptor ++otg_descriptor = { ++ .bLength = sizeof otg_descriptor, ++ .bDescriptorType = USB_DT_OTG, ++ ++ .bmAttributes = USB_OTG_SRP, ++}; ++ ++/* one interface in each configuration */ ++#ifdef CONFIG_USB_GADGET_DUALSPEED ++ ++/* ++ * usb 2.0 devices need to expose both high speed and full speed ++ * descriptors, unless they only run at full speed. ++ * ++ * that means alternate endpoint descriptors (bigger packets) ++ * and a "device qualifier" ... plus more construction options ++ * for the config descriptor. ++ */ ++ ++static struct usb_qualifier_descriptor ++dev_qualifier = { ++ .bLength = sizeof dev_qualifier, ++ .bDescriptorType = USB_DT_DEVICE_QUALIFIER, ++ ++ .bcdUSB = __constant_cpu_to_le16 (0x0200), ++ .bDeviceClass = USB_CLASS_VENDOR_SPEC, ++ ++ .bNumConfigurations = 2, ++}; ++ ++ ++struct usb_cs_as_general_descriptor { ++ __u8 bLength; ++ __u8 bDescriptorType; ++ ++ __u8 bDescriptorSubType; ++ __u8 bTerminalLink; ++ __u8 bDelay; ++ __u16 wFormatTag; ++} __attribute__ ((packed)); ++ ++struct usb_cs_as_format_descriptor { ++ __u8 bLength; ++ __u8 bDescriptorType; ++ ++ __u8 bDescriptorSubType; ++ __u8 bFormatType; ++ __u8 bNrChannels; ++ __u8 bSubframeSize; ++ __u8 bBitResolution; ++ __u8 bSamfreqType; ++ __u8 tLowerSamFreq[3]; ++ __u8 tUpperSamFreq[3]; ++} __attribute__ ((packed)); ++ ++static const struct usb_interface_descriptor ++z_audio_control_if_desc = { ++ .bLength = sizeof z_audio_control_if_desc, ++ .bDescriptorType = USB_DT_INTERFACE, ++ .bInterfaceNumber = 0, ++ .bAlternateSetting = 0, ++ .bNumEndpoints = 0, ++ .bInterfaceClass = USB_CLASS_AUDIO, ++ .bInterfaceSubClass = 0x1, ++ .bInterfaceProtocol = 0, ++ .iInterface = 0, ++}; ++ ++static const struct usb_interface_descriptor ++z_audio_if_desc = { ++ .bLength = sizeof z_audio_if_desc, ++ .bDescriptorType = USB_DT_INTERFACE, ++ .bInterfaceNumber = 1, ++ .bAlternateSetting = 0, ++ .bNumEndpoints = 0, ++ .bInterfaceClass = USB_CLASS_AUDIO, ++ .bInterfaceSubClass = 0x2, ++ .bInterfaceProtocol = 0, ++ .iInterface = 0, ++}; ++ ++static const struct usb_interface_descriptor ++z_audio_if_desc2 = { ++ .bLength = sizeof z_audio_if_desc, ++ .bDescriptorType = USB_DT_INTERFACE, ++ .bInterfaceNumber = 1, ++ .bAlternateSetting = 1, ++ .bNumEndpoints = 1, ++ .bInterfaceClass = USB_CLASS_AUDIO, ++ .bInterfaceSubClass = 0x2, ++ .bInterfaceProtocol = 0, ++ .iInterface = 0, ++}; ++ ++static const struct usb_cs_as_general_descriptor ++z_audio_cs_as_if_desc = { ++ .bLength = 7, ++ .bDescriptorType = 0x24, ++ ++ .bDescriptorSubType = 0x01, ++ .bTerminalLink = 0x01, ++ .bDelay = 0x0, ++ .wFormatTag = __constant_cpu_to_le16 (0x0001) ++}; ++ ++ ++static const struct usb_cs_as_format_descriptor ++z_audio_cs_as_format_desc = { ++ .bLength = 0xe, ++ .bDescriptorType = 0x24, ++ ++ .bDescriptorSubType = 2, ++ .bFormatType = 1, ++ .bNrChannels = 1, ++ .bSubframeSize = 1, ++ .bBitResolution = 8, ++ .bSamfreqType = 0, ++ .tLowerSamFreq = {0x7e, 0x13, 0x00}, ++ .tUpperSamFreq = {0xe2, 0xd6, 0x00}, ++}; ++ ++static const struct usb_endpoint_descriptor ++z_iso_ep = { ++ .bLength = 0x09, ++ .bDescriptorType = 0x05, ++ .bEndpointAddress = 0x04, ++ .bmAttributes = 0x09, ++ .wMaxPacketSize = 0x0038, ++ .bInterval = 0x01, ++ .bRefresh = 0x00, ++ .bSynchAddress = 0x00, ++}; ++ ++static char z_iso_ep2[] = {0x07, 0x25, 0x01, 0x00, 0x02, 0x00, 0x02}; ++ ++// 9 bytes ++static char z_ac_interface_header_desc[] = ++{ 0x09, 0x24, 0x01, 0x00, 0x01, 0x2b, 0x00, 0x01, 0x01 }; ++ ++// 12 bytes ++static char z_0[] = {0x0c, 0x24, 0x02, 0x01, 0x01, 0x01, 0x00, 0x02, ++ 0x03, 0x00, 0x00, 0x00}; ++// 13 bytes ++static char z_1[] = {0x0d, 0x24, 0x06, 0x02, 0x01, 0x02, 0x15, 0x00, ++ 0x02, 0x00, 0x02, 0x00, 0x00}; ++// 9 bytes ++static char z_2[] = {0x09, 0x24, 0x03, 0x03, 0x01, 0x03, 0x00, 0x02, ++ 0x00}; ++ ++static char za_0[] = {0x09, 0x04, 0x01, 0x02, 0x01, 0x01, 0x02, 0x00, ++ 0x00}; ++ ++static char za_1[] = {0x07, 0x24, 0x01, 0x01, 0x00, 0x01, 0x00}; ++ ++static char za_2[] = {0x0e, 0x24, 0x02, 0x01, 0x02, 0x01, 0x08, 0x00, ++ 0x7e, 0x13, 0x00, 0xe2, 0xd6, 0x00}; ++ ++static char za_3[] = {0x09, 0x05, 0x04, 0x09, 0x70, 0x00, 0x01, 0x00, ++ 0x00}; ++ ++static char za_4[] = {0x07, 0x25, 0x01, 0x00, 0x02, 0x00, 0x02}; ++ ++static char za_5[] = {0x09, 0x04, 0x01, 0x03, 0x01, 0x01, 0x02, 0x00, ++ 0x00}; ++ ++static char za_6[] = {0x07, 0x24, 0x01, 0x01, 0x00, 0x01, 0x00}; ++ ++static char za_7[] = {0x0e, 0x24, 0x02, 0x01, 0x01, 0x02, 0x10, 0x00, ++ 0x7e, 0x13, 0x00, 0xe2, 0xd6, 0x00}; ++ ++static char za_8[] = {0x09, 0x05, 0x04, 0x09, 0x70, 0x00, 0x01, 0x00, ++ 0x00}; ++ ++static char za_9[] = {0x07, 0x25, 0x01, 0x00, 0x02, 0x00, 0x02}; ++ ++static char za_10[] = {0x09, 0x04, 0x01, 0x04, 0x01, 0x01, 0x02, 0x00, ++ 0x00}; ++ ++static char za_11[] = {0x07, 0x24, 0x01, 0x01, 0x00, 0x01, 0x00}; ++ ++static char za_12[] = {0x0e, 0x24, 0x02, 0x01, 0x02, 0x02, 0x10, 0x00, ++ 0x73, 0x13, 0x00, 0xe2, 0xd6, 0x00}; ++ ++static char za_13[] = {0x09, 0x05, 0x04, 0x09, 0xe0, 0x00, 0x01, 0x00, ++ 0x00}; ++ ++static char za_14[] = {0x07, 0x25, 0x01, 0x00, 0x02, 0x00, 0x02}; ++ ++static char za_15[] = {0x09, 0x04, 0x01, 0x05, 0x01, 0x01, 0x02, 0x00, ++ 0x00}; ++ ++static char za_16[] = {0x07, 0x24, 0x01, 0x01, 0x00, 0x01, 0x00}; ++ ++static char za_17[] = {0x0e, 0x24, 0x02, 0x01, 0x01, 0x03, 0x14, 0x00, ++ 0x7e, 0x13, 0x00, 0xe2, 0xd6, 0x00}; ++ ++static char za_18[] = {0x09, 0x05, 0x04, 0x09, 0xa8, 0x00, 0x01, 0x00, ++ 0x00}; ++ ++static char za_19[] = {0x07, 0x25, 0x01, 0x00, 0x02, 0x00, 0x02}; ++ ++static char za_20[] = {0x09, 0x04, 0x01, 0x06, 0x01, 0x01, 0x02, 0x00, ++ 0x00}; ++ ++static char za_21[] = {0x07, 0x24, 0x01, 0x01, 0x00, 0x01, 0x00}; ++ ++static char za_22[] = {0x0e, 0x24, 0x02, 0x01, 0x02, 0x03, 0x14, 0x00, ++ 0x7e, 0x13, 0x00, 0xe2, 0xd6, 0x00}; ++ ++static char za_23[] = {0x09, 0x05, 0x04, 0x09, 0x50, 0x01, 0x01, 0x00, ++ 0x00}; ++ ++static char za_24[] = {0x07, 0x25, 0x01, 0x00, 0x02, 0x00, 0x02}; ++ ++ ++ ++static const struct usb_descriptor_header *z_function [] = { ++ (struct usb_descriptor_header *) &z_audio_control_if_desc, ++ (struct usb_descriptor_header *) &z_ac_interface_header_desc, ++ (struct usb_descriptor_header *) &z_0, ++ (struct usb_descriptor_header *) &z_1, ++ (struct usb_descriptor_header *) &z_2, ++ (struct usb_descriptor_header *) &z_audio_if_desc, ++ (struct usb_descriptor_header *) &z_audio_if_desc2, ++ (struct usb_descriptor_header *) &z_audio_cs_as_if_desc, ++ (struct usb_descriptor_header *) &z_audio_cs_as_format_desc, ++ (struct usb_descriptor_header *) &z_iso_ep, ++ (struct usb_descriptor_header *) &z_iso_ep2, ++ (struct usb_descriptor_header *) &za_0, ++ (struct usb_descriptor_header *) &za_1, ++ (struct usb_descriptor_header *) &za_2, ++ (struct usb_descriptor_header *) &za_3, ++ (struct usb_descriptor_header *) &za_4, ++ (struct usb_descriptor_header *) &za_5, ++ (struct usb_descriptor_header *) &za_6, ++ (struct usb_descriptor_header *) &za_7, ++ (struct usb_descriptor_header *) &za_8, ++ (struct usb_descriptor_header *) &za_9, ++ (struct usb_descriptor_header *) &za_10, ++ (struct usb_descriptor_header *) &za_11, ++ (struct usb_descriptor_header *) &za_12, ++ (struct usb_descriptor_header *) &za_13, ++ (struct usb_descriptor_header *) &za_14, ++ (struct usb_descriptor_header *) &za_15, ++ (struct usb_descriptor_header *) &za_16, ++ (struct usb_descriptor_header *) &za_17, ++ (struct usb_descriptor_header *) &za_18, ++ (struct usb_descriptor_header *) &za_19, ++ (struct usb_descriptor_header *) &za_20, ++ (struct usb_descriptor_header *) &za_21, ++ (struct usb_descriptor_header *) &za_22, ++ (struct usb_descriptor_header *) &za_23, ++ (struct usb_descriptor_header *) &za_24, ++ NULL, ++}; ++ ++/* maxpacket and other transfer characteristics vary by speed. */ ++#define ep_desc(g,hs,fs) (((g)->speed==USB_SPEED_HIGH)?(hs):(fs)) ++ ++#else ++ ++/* if there's no high speed support, maxpacket doesn't change. */ ++#define ep_desc(g,hs,fs) fs ++ ++#endif /* !CONFIG_USB_GADGET_DUALSPEED */ ++ ++static char manufacturer [40]; ++//static char serial [40]; ++static char serial [] = "Ser 00 em"; ++ ++/* static strings, in UTF-8 */ ++static struct usb_string strings [] = { ++ { STRING_MANUFACTURER, manufacturer, }, ++ { STRING_PRODUCT, longname, }, ++ { STRING_SERIAL, serial, }, ++ { STRING_LOOPBACK, loopback, }, ++ { STRING_SOURCE_SINK, source_sink, }, ++ { } /* end of list */ ++}; ++ ++static struct usb_gadget_strings stringtab = { ++ .language = 0x0409, /* en-us */ ++ .strings = strings, ++}; ++ ++/* ++ * config descriptors are also handcrafted. these must agree with code ++ * that sets configurations, and with code managing interfaces and their ++ * altsettings. other complexity may come from: ++ * ++ * - high speed support, including "other speed config" rules ++ * - multiple configurations ++ * - interfaces with alternate settings ++ * - embedded class or vendor-specific descriptors ++ * ++ * this handles high speed, and has a second config that could as easily ++ * have been an alternate interface setting (on most hardware). ++ * ++ * NOTE: to demonstrate (and test) more USB capabilities, this driver ++ * should include an altsetting to test interrupt transfers, including ++ * high bandwidth modes at high speed. (Maybe work like Intel's test ++ * device?) ++ */ ++static int ++config_buf (struct usb_gadget *gadget, u8 *buf, u8 type, unsigned index) ++{ ++ int len; ++ const struct usb_descriptor_header **function; ++ ++ function = z_function; ++ len = usb_gadget_config_buf (&z_config, buf, USB_BUFSIZ, function); ++ if (len < 0) ++ return len; ++ ((struct usb_config_descriptor *) buf)->bDescriptorType = type; ++ return len; ++} ++ ++/*-------------------------------------------------------------------------*/ ++ ++static struct usb_request * ++alloc_ep_req (struct usb_ep *ep, unsigned length) ++{ ++ struct usb_request *req; ++ ++ req = usb_ep_alloc_request (ep, GFP_ATOMIC); ++ if (req) { ++ req->length = length; ++ req->buf = usb_ep_alloc_buffer (ep, length, ++ &req->dma, GFP_ATOMIC); ++ if (!req->buf) { ++ usb_ep_free_request (ep, req); ++ req = NULL; ++ } ++ } ++ return req; ++} ++ ++static void free_ep_req (struct usb_ep *ep, struct usb_request *req) ++{ ++ if (req->buf) ++ usb_ep_free_buffer (ep, req->buf, req->dma, req->length); ++ usb_ep_free_request (ep, req); ++} ++ ++/*-------------------------------------------------------------------------*/ ++ ++/* optionally require specific source/sink data patterns */ ++ ++static int ++check_read_data ( ++ struct zero_dev *dev, ++ struct usb_ep *ep, ++ struct usb_request *req ++) ++{ ++ unsigned i; ++ u8 *buf = req->buf; ++ ++ for (i = 0; i < req->actual; i++, buf++) { ++ switch (pattern) { ++ /* all-zeroes has no synchronization issues */ ++ case 0: ++ if (*buf == 0) ++ continue; ++ break; ++ /* mod63 stays in sync with short-terminated transfers, ++ * or otherwise when host and gadget agree on how large ++ * each usb transfer request should be. resync is done ++ * with set_interface or set_config. ++ */ ++ case 1: ++ if (*buf == (u8)(i % 63)) ++ continue; ++ break; ++ } ++ ERROR (dev, "bad OUT byte, buf [%d] = %d\n", i, *buf); ++ usb_ep_set_halt (ep); ++ return -EINVAL; ++ } ++ return 0; ++} ++ ++/*-------------------------------------------------------------------------*/ ++ ++static void zero_reset_config (struct zero_dev *dev) ++{ ++ if (dev->config == 0) ++ return; ++ ++ DBG (dev, "reset config\n"); ++ ++ /* just disable endpoints, forcing completion of pending i/o. ++ * all our completion handlers free their requests in this case. ++ */ ++ if (dev->in_ep) { ++ usb_ep_disable (dev->in_ep); ++ dev->in_ep = NULL; ++ } ++ if (dev->out_ep) { ++ usb_ep_disable (dev->out_ep); ++ dev->out_ep = NULL; ++ } ++ dev->config = 0; ++ del_timer (&dev->resume); ++} ++ ++#define _write(f, buf, sz) (f->f_op->write(f, buf, sz, &f->f_pos)) ++ ++static void ++zero_isoc_complete (struct usb_ep *ep, struct usb_request *req) ++{ ++ struct zero_dev *dev = ep->driver_data; ++ int status = req->status; ++ int i, j; ++ ++ switch (status) { ++ ++ case 0: /* normal completion? */ ++ //printk ("\nzero ---------------> isoc normal completion %d bytes\n", req->actual); ++ for (i=0, j=rbuf_start; iactual; i++) { ++ //printk ("%02x ", ((__u8*)req->buf)[i]); ++ rbuf[j] = ((__u8*)req->buf)[i]; ++ j++; ++ if (j >= RBUF_LEN) j=0; ++ } ++ rbuf_start = j; ++ //printk ("\n\n"); ++ ++ if (rbuf_len < RBUF_LEN) { ++ rbuf_len += req->actual; ++ if (rbuf_len > RBUF_LEN) { ++ rbuf_len = RBUF_LEN; ++ } ++ } ++ ++ break; ++ ++ /* this endpoint is normally active while we're configured */ ++ case -ECONNABORTED: /* hardware forced ep reset */ ++ case -ECONNRESET: /* request dequeued */ ++ case -ESHUTDOWN: /* disconnect from host */ ++ VDBG (dev, "%s gone (%d), %d/%d\n", ep->name, status, ++ req->actual, req->length); ++ if (ep == dev->out_ep) ++ check_read_data (dev, ep, req); ++ free_ep_req (ep, req); ++ return; ++ ++ case -EOVERFLOW: /* buffer overrun on read means that ++ * we didn't provide a big enough ++ * buffer. ++ */ ++ default: ++#if 1 ++ DBG (dev, "%s complete --> %d, %d/%d\n", ep->name, ++ status, req->actual, req->length); ++#endif ++ case -EREMOTEIO: /* short read */ ++ break; ++ } ++ ++ status = usb_ep_queue (ep, req, GFP_ATOMIC); ++ if (status) { ++ ERROR (dev, "kill %s: resubmit %d bytes --> %d\n", ++ ep->name, req->length, status); ++ usb_ep_set_halt (ep); ++ /* FIXME recover later ... somehow */ ++ } ++} ++ ++static struct usb_request * ++zero_start_isoc_ep (struct usb_ep *ep, int gfp_flags) ++{ ++ struct usb_request *req; ++ int status; ++ ++ req = alloc_ep_req (ep, 512); ++ if (!req) ++ return NULL; ++ ++ req->complete = zero_isoc_complete; ++ ++ status = usb_ep_queue (ep, req, gfp_flags); ++ if (status) { ++ struct zero_dev *dev = ep->driver_data; ++ ++ ERROR (dev, "start %s --> %d\n", ep->name, status); ++ free_ep_req (ep, req); ++ req = NULL; ++ } ++ ++ return req; ++} ++ ++/* change our operational config. this code must agree with the code ++ * that returns config descriptors, and altsetting code. ++ * ++ * it's also responsible for power management interactions. some ++ * configurations might not work with our current power sources. ++ * ++ * note that some device controller hardware will constrain what this ++ * code can do, perhaps by disallowing more than one configuration or ++ * by limiting configuration choices (like the pxa2xx). ++ */ ++static int ++zero_set_config (struct zero_dev *dev, unsigned number, int gfp_flags) ++{ ++ int result = 0; ++ struct usb_gadget *gadget = dev->gadget; ++ const struct usb_endpoint_descriptor *d; ++ struct usb_ep *ep; ++ ++ if (number == dev->config) ++ return 0; ++ ++ zero_reset_config (dev); ++ ++ gadget_for_each_ep (ep, gadget) { ++ ++ if (strcmp (ep->name, "ep4") == 0) { ++ ++ d = (struct usb_endpoint_descripter *)&za_23; // isoc ep desc for audio i/f alt setting 6 ++ result = usb_ep_enable (ep, d); ++ ++ if (result == 0) { ++ ep->driver_data = dev; ++ dev->in_ep = ep; ++ ++ if (zero_start_isoc_ep (ep, gfp_flags) != 0) { ++ ++ dev->in_ep = ep; ++ continue; ++ } ++ ++ usb_ep_disable (ep); ++ result = -EIO; ++ } ++ } ++ ++ } ++ ++ dev->config = number; ++ return result; ++} ++ ++/*-------------------------------------------------------------------------*/ ++ ++static void zero_setup_complete (struct usb_ep *ep, struct usb_request *req) ++{ ++ if (req->status || req->actual != req->length) ++ DBG ((struct zero_dev *) ep->driver_data, ++ "setup complete --> %d, %d/%d\n", ++ req->status, req->actual, req->length); ++} ++ ++/* ++ * The setup() callback implements all the ep0 functionality that's ++ * not handled lower down, in hardware or the hardware driver (like ++ * device and endpoint feature flags, and their status). It's all ++ * housekeeping for the gadget function we're implementing. Most of ++ * the work is in config-specific setup. ++ */ ++static int ++zero_setup (struct usb_gadget *gadget, const struct usb_ctrlrequest *ctrl) ++{ ++ struct zero_dev *dev = get_gadget_data (gadget); ++ struct usb_request *req = dev->req; ++ int value = -EOPNOTSUPP; ++ ++ /* usually this stores reply data in the pre-allocated ep0 buffer, ++ * but config change events will reconfigure hardware. ++ */ ++ req->zero = 0; ++ switch (ctrl->bRequest) { ++ ++ case USB_REQ_GET_DESCRIPTOR: ++ ++ switch (ctrl->wValue >> 8) { ++ ++ case USB_DT_DEVICE: ++ value = min (ctrl->wLength, (u16) sizeof device_desc); ++ memcpy (req->buf, &device_desc, value); ++ break; ++#ifdef CONFIG_USB_GADGET_DUALSPEED ++ case USB_DT_DEVICE_QUALIFIER: ++ if (!gadget->is_dualspeed) ++ break; ++ value = min (ctrl->wLength, (u16) sizeof dev_qualifier); ++ memcpy (req->buf, &dev_qualifier, value); ++ break; ++ ++ case USB_DT_OTHER_SPEED_CONFIG: ++ if (!gadget->is_dualspeed) ++ break; ++ // FALLTHROUGH ++#endif /* CONFIG_USB_GADGET_DUALSPEED */ ++ case USB_DT_CONFIG: ++ value = config_buf (gadget, req->buf, ++ ctrl->wValue >> 8, ++ ctrl->wValue & 0xff); ++ if (value >= 0) ++ value = min (ctrl->wLength, (u16) value); ++ break; ++ ++ case USB_DT_STRING: ++ /* wIndex == language code. ++ * this driver only handles one language, you can ++ * add string tables for other languages, using ++ * any UTF-8 characters ++ */ ++ value = usb_gadget_get_string (&stringtab, ++ ctrl->wValue & 0xff, req->buf); ++ if (value >= 0) { ++ value = min (ctrl->wLength, (u16) value); ++ } ++ break; ++ } ++ break; ++ ++ /* currently two configs, two speeds */ ++ case USB_REQ_SET_CONFIGURATION: ++ if (ctrl->bRequestType != 0) ++ goto unknown; ++ ++ spin_lock (&dev->lock); ++ value = zero_set_config (dev, ctrl->wValue, GFP_ATOMIC); ++ spin_unlock (&dev->lock); ++ break; ++ case USB_REQ_GET_CONFIGURATION: ++ if (ctrl->bRequestType != USB_DIR_IN) ++ goto unknown; ++ *(u8 *)req->buf = dev->config; ++ value = min (ctrl->wLength, (u16) 1); ++ break; ++ ++ /* until we add altsetting support, or other interfaces, ++ * only 0/0 are possible. pxa2xx only supports 0/0 (poorly) ++ * and already killed pending endpoint I/O. ++ */ ++ case USB_REQ_SET_INTERFACE: ++ ++ if (ctrl->bRequestType != USB_RECIP_INTERFACE) ++ goto unknown; ++ spin_lock (&dev->lock); ++ if (dev->config) { ++ u8 config = dev->config; ++ ++ /* resets interface configuration, forgets about ++ * previous transaction state (queued bufs, etc) ++ * and re-inits endpoint state (toggle etc) ++ * no response queued, just zero status == success. ++ * if we had more than one interface we couldn't ++ * use this "reset the config" shortcut. ++ */ ++ zero_reset_config (dev); ++ zero_set_config (dev, config, GFP_ATOMIC); ++ value = 0; ++ } ++ spin_unlock (&dev->lock); ++ break; ++ case USB_REQ_GET_INTERFACE: ++ if ((ctrl->bRequestType == 0x21) && (ctrl->wIndex == 0x02)) { ++ value = ctrl->wLength; ++ break; ++ } ++ else { ++ if (ctrl->bRequestType != (USB_DIR_IN|USB_RECIP_INTERFACE)) ++ goto unknown; ++ if (!dev->config) ++ break; ++ if (ctrl->wIndex != 0) { ++ value = -EDOM; ++ break; ++ } ++ *(u8 *)req->buf = 0; ++ value = min (ctrl->wLength, (u16) 1); ++ } ++ break; ++ ++ /* ++ * These are the same vendor-specific requests supported by ++ * Intel's USB 2.0 compliance test devices. We exceed that ++ * device spec by allowing multiple-packet requests. ++ */ ++ case 0x5b: /* control WRITE test -- fill the buffer */ ++ if (ctrl->bRequestType != (USB_DIR_OUT|USB_TYPE_VENDOR)) ++ goto unknown; ++ if (ctrl->wValue || ctrl->wIndex) ++ break; ++ /* just read that many bytes into the buffer */ ++ if (ctrl->wLength > USB_BUFSIZ) ++ break; ++ value = ctrl->wLength; ++ break; ++ case 0x5c: /* control READ test -- return the buffer */ ++ if (ctrl->bRequestType != (USB_DIR_IN|USB_TYPE_VENDOR)) ++ goto unknown; ++ if (ctrl->wValue || ctrl->wIndex) ++ break; ++ /* expect those bytes are still in the buffer; send back */ ++ if (ctrl->wLength > USB_BUFSIZ ++ || ctrl->wLength != req->length) ++ break; ++ value = ctrl->wLength; ++ break; ++ ++ case 0x01: // SET_CUR ++ case 0x02: ++ case 0x03: ++ case 0x04: ++ case 0x05: ++ value = ctrl->wLength; ++ break; ++ case 0x81: ++ switch (ctrl->wValue) { ++ case 0x0201: ++ case 0x0202: ++ ((u8*)req->buf)[0] = 0x00; ++ ((u8*)req->buf)[1] = 0xe3; ++ break; ++ case 0x0300: ++ case 0x0500: ++ ((u8*)req->buf)[0] = 0x00; ++ break; ++ } ++ //((u8*)req->buf)[0] = 0x81; ++ //((u8*)req->buf)[1] = 0x81; ++ value = ctrl->wLength; ++ break; ++ case 0x82: ++ switch (ctrl->wValue) { ++ case 0x0201: ++ case 0x0202: ++ ((u8*)req->buf)[0] = 0x00; ++ ((u8*)req->buf)[1] = 0xc3; ++ break; ++ case 0x0300: ++ case 0x0500: ++ ((u8*)req->buf)[0] = 0x00; ++ break; ++ } ++ //((u8*)req->buf)[0] = 0x82; ++ //((u8*)req->buf)[1] = 0x82; ++ value = ctrl->wLength; ++ break; ++ case 0x83: ++ switch (ctrl->wValue) { ++ case 0x0201: ++ case 0x0202: ++ ((u8*)req->buf)[0] = 0x00; ++ ((u8*)req->buf)[1] = 0x00; ++ break; ++ case 0x0300: ++ ((u8*)req->buf)[0] = 0x60; ++ break; ++ case 0x0500: ++ ((u8*)req->buf)[0] = 0x18; ++ break; ++ } ++ //((u8*)req->buf)[0] = 0x83; ++ //((u8*)req->buf)[1] = 0x83; ++ value = ctrl->wLength; ++ break; ++ case 0x84: ++ switch (ctrl->wValue) { ++ case 0x0201: ++ case 0x0202: ++ ((u8*)req->buf)[0] = 0x00; ++ ((u8*)req->buf)[1] = 0x01; ++ break; ++ case 0x0300: ++ case 0x0500: ++ ((u8*)req->buf)[0] = 0x08; ++ break; ++ } ++ //((u8*)req->buf)[0] = 0x84; ++ //((u8*)req->buf)[1] = 0x84; ++ value = ctrl->wLength; ++ break; ++ case 0x85: ++ ((u8*)req->buf)[0] = 0x85; ++ ((u8*)req->buf)[1] = 0x85; ++ value = ctrl->wLength; ++ break; ++ ++ ++ default: ++unknown: ++ printk("unknown control req%02x.%02x v%04x i%04x l%d\n", ++ ctrl->bRequestType, ctrl->bRequest, ++ ctrl->wValue, ctrl->wIndex, ctrl->wLength); ++ } ++ ++ /* respond with data transfer before status phase? */ ++ if (value >= 0) { ++ req->length = value; ++ req->zero = value < ctrl->wLength ++ && (value % gadget->ep0->maxpacket) == 0; ++ value = usb_ep_queue (gadget->ep0, req, GFP_ATOMIC); ++ if (value < 0) { ++ DBG (dev, "ep_queue < 0 --> %d\n", value); ++ req->status = 0; ++ zero_setup_complete (gadget->ep0, req); ++ } ++ } ++ ++ /* device either stalls (value < 0) or reports success */ ++ return value; ++} ++ ++static void ++zero_disconnect (struct usb_gadget *gadget) ++{ ++ struct zero_dev *dev = get_gadget_data (gadget); ++ unsigned long flags; ++ ++ spin_lock_irqsave (&dev->lock, flags); ++ zero_reset_config (dev); ++ ++ /* a more significant application might have some non-usb ++ * activities to quiesce here, saving resources like power ++ * or pushing the notification up a network stack. ++ */ ++ spin_unlock_irqrestore (&dev->lock, flags); ++ ++ /* next we may get setup() calls to enumerate new connections; ++ * or an unbind() during shutdown (including removing module). ++ */ ++} ++ ++static void ++zero_autoresume (unsigned long _dev) ++{ ++ struct zero_dev *dev = (struct zero_dev *) _dev; ++ int status; ++ ++ /* normally the host would be woken up for something ++ * more significant than just a timer firing... ++ */ ++ if (dev->gadget->speed != USB_SPEED_UNKNOWN) { ++ status = usb_gadget_wakeup (dev->gadget); ++ DBG (dev, "wakeup --> %d\n", status); ++ } ++} ++ ++/*-------------------------------------------------------------------------*/ ++ ++static void ++zero_unbind (struct usb_gadget *gadget) ++{ ++ struct zero_dev *dev = get_gadget_data (gadget); ++ ++ DBG (dev, "unbind\n"); ++ ++ /* we've already been disconnected ... no i/o is active */ ++ if (dev->req) ++ free_ep_req (gadget->ep0, dev->req); ++ del_timer_sync (&dev->resume); ++ kfree (dev); ++ set_gadget_data (gadget, NULL); ++} ++ ++static int ++zero_bind (struct usb_gadget *gadget) ++{ ++ struct zero_dev *dev; ++ //struct usb_ep *ep; ++ ++ printk("binding\n"); ++ /* ++ * DRIVER POLICY CHOICE: you may want to do this differently. ++ * One thing to avoid is reusing a bcdDevice revision code ++ * with different host-visible configurations or behavior ++ * restrictions -- using ep1in/ep2out vs ep1out/ep3in, etc ++ */ ++ //device_desc.bcdDevice = __constant_cpu_to_le16 (0x0201); ++ ++ ++ /* ok, we made sense of the hardware ... */ ++ dev = kmalloc (sizeof *dev, SLAB_KERNEL); ++ if (!dev) ++ return -ENOMEM; ++ memset (dev, 0, sizeof *dev); ++ spin_lock_init (&dev->lock); ++ dev->gadget = gadget; ++ set_gadget_data (gadget, dev); ++ ++ /* preallocate control response and buffer */ ++ dev->req = usb_ep_alloc_request (gadget->ep0, GFP_KERNEL); ++ if (!dev->req) ++ goto enomem; ++ dev->req->buf = usb_ep_alloc_buffer (gadget->ep0, USB_BUFSIZ, ++ &dev->req->dma, GFP_KERNEL); ++ if (!dev->req->buf) ++ goto enomem; ++ ++ dev->req->complete = zero_setup_complete; ++ ++ device_desc.bMaxPacketSize0 = gadget->ep0->maxpacket; ++ ++#ifdef CONFIG_USB_GADGET_DUALSPEED ++ /* assume ep0 uses the same value for both speeds ... */ ++ dev_qualifier.bMaxPacketSize0 = device_desc.bMaxPacketSize0; ++ ++ /* and that all endpoints are dual-speed */ ++ //hs_source_desc.bEndpointAddress = fs_source_desc.bEndpointAddress; ++ //hs_sink_desc.bEndpointAddress = fs_sink_desc.bEndpointAddress; ++#endif ++ ++ usb_gadget_set_selfpowered (gadget); ++ ++ init_timer (&dev->resume); ++ dev->resume.function = zero_autoresume; ++ dev->resume.data = (unsigned long) dev; ++ ++ gadget->ep0->driver_data = dev; ++ ++ INFO (dev, "%s, version: " DRIVER_VERSION "\n", longname); ++ INFO (dev, "using %s, OUT %s IN %s\n", gadget->name, ++ EP_OUT_NAME, EP_IN_NAME); ++ ++ snprintf (manufacturer, sizeof manufacturer, ++ UTS_SYSNAME " " UTS_RELEASE " with %s", ++ gadget->name); ++ ++ return 0; ++ ++enomem: ++ zero_unbind (gadget); ++ return -ENOMEM; ++} ++ ++/*-------------------------------------------------------------------------*/ ++ ++static void ++zero_suspend (struct usb_gadget *gadget) ++{ ++ struct zero_dev *dev = get_gadget_data (gadget); ++ ++ if (gadget->speed == USB_SPEED_UNKNOWN) ++ return; ++ ++ if (autoresume) { ++ mod_timer (&dev->resume, jiffies + (HZ * autoresume)); ++ DBG (dev, "suspend, wakeup in %d seconds\n", autoresume); ++ } else ++ DBG (dev, "suspend\n"); ++} ++ ++static void ++zero_resume (struct usb_gadget *gadget) ++{ ++ struct zero_dev *dev = get_gadget_data (gadget); ++ ++ DBG (dev, "resume\n"); ++ del_timer (&dev->resume); ++} ++ ++ ++/*-------------------------------------------------------------------------*/ ++ ++static struct usb_gadget_driver zero_driver = { ++#ifdef CONFIG_USB_GADGET_DUALSPEED ++ .speed = USB_SPEED_HIGH, ++#else ++ .speed = USB_SPEED_FULL, ++#endif ++ .function = (char *) longname, ++ .bind = zero_bind, ++ .unbind = zero_unbind, ++ ++ .setup = zero_setup, ++ .disconnect = zero_disconnect, ++ ++ .suspend = zero_suspend, ++ .resume = zero_resume, ++ ++ .driver = { ++ .name = (char *) shortname, ++ // .shutdown = ... ++ // .suspend = ... ++ // .resume = ... ++ }, ++}; ++ ++MODULE_AUTHOR ("David Brownell"); ++MODULE_LICENSE ("Dual BSD/GPL"); ++ ++static struct proc_dir_entry *pdir, *pfile; ++ ++static int isoc_read_data (char *page, char **start, ++ off_t off, int count, ++ int *eof, void *data) ++{ ++ int i; ++ static int c = 0; ++ static int done = 0; ++ static int s = 0; ++ ++/* ++ printk ("\ncount: %d\n", count); ++ printk ("rbuf_start: %d\n", rbuf_start); ++ printk ("rbuf_len: %d\n", rbuf_len); ++ printk ("off: %d\n", off); ++ printk ("start: %p\n\n", *start); ++*/ ++ if (done) { ++ c = 0; ++ done = 0; ++ *eof = 1; ++ return 0; ++ } ++ ++ if (c == 0) { ++ if (rbuf_len == RBUF_LEN) ++ s = rbuf_start; ++ else s = 0; ++ } ++ ++ for (i=0; i= rbuf_len) { ++ *eof = 1; ++ done = 1; ++ } ++ ++ ++ return i; ++} ++ ++static int __init init (void) ++{ ++ ++ int retval = 0; ++ ++ pdir = proc_mkdir("isoc_test", NULL); ++ if(pdir == NULL) { ++ retval = -ENOMEM; ++ printk("Error creating dir\n"); ++ goto done; ++ } ++ pdir->owner = THIS_MODULE; ++ ++ pfile = create_proc_read_entry("isoc_data", ++ 0444, pdir, ++ isoc_read_data, ++ NULL); ++ if (pfile == NULL) { ++ retval = -ENOMEM; ++ printk("Error creating file\n"); ++ goto no_file; ++ } ++ pfile->owner = THIS_MODULE; ++ ++ return usb_gadget_register_driver (&zero_driver); ++ ++ no_file: ++ remove_proc_entry("isoc_data", NULL); ++ done: ++ return retval; ++} ++module_init (init); ++ ++static void __exit cleanup (void) ++{ ++ ++ usb_gadget_unregister_driver (&zero_driver); ++ ++ remove_proc_entry("isoc_data", pdir); ++ remove_proc_entry("isoc_test", NULL); ++} ++module_exit (cleanup); +Index: linux-3.2.46/drivers/usb/host/dwc_otg/dwc_cfi_common.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/dwc_cfi_common.h 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,142 @@ ++/* ========================================================================== ++ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, ++ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless ++ * otherwise expressly agreed to in writing between Synopsys and you. ++ * ++ * The Software IS NOT an item of Licensed Software or Licensed Product under ++ * any End User Software License Agreement or Agreement for Licensed Product ++ * with Synopsys or any supplement thereto. You are permitted to use and ++ * redistribute this Software in source and binary forms, with or without ++ * modification, provided that redistributions of source code must retain this ++ * notice. You may not view, use, disclose, copy or distribute this file or ++ * any information contained herein except pursuant to this license grant from ++ * Synopsys. If you do not agree with this notice, including the disclaimer ++ * below, then you are not authorized to use the Software. ++ * ++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, ++ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR ++ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER ++ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY ++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH ++ * DAMAGE. ++ * ========================================================================== */ ++ ++#if !defined(__DWC_CFI_COMMON_H__) ++#define __DWC_CFI_COMMON_H__ ++ ++//#include ++ ++/** ++ * @file ++ * ++ * This file contains the CFI specific common constants, interfaces ++ * (functions and macros) and structures for Linux. No PCD specific ++ * data structure or definition is to be included in this file. ++ * ++ */ ++ ++/** This is a request for all Core Features */ ++#define VEN_CORE_GET_FEATURES 0xB1 ++ ++/** This is a request to get the value of a specific Core Feature */ ++#define VEN_CORE_GET_FEATURE 0xB2 ++ ++/** This command allows the host to set the value of a specific Core Feature */ ++#define VEN_CORE_SET_FEATURE 0xB3 ++ ++/** This command allows the host to set the default values of ++ * either all or any specific Core Feature ++ */ ++#define VEN_CORE_RESET_FEATURES 0xB4 ++ ++/** This command forces the PCD to write the deferred values of a Core Features */ ++#define VEN_CORE_ACTIVATE_FEATURES 0xB5 ++ ++/** This request reads a DWORD value from a register at the specified offset */ ++#define VEN_CORE_READ_REGISTER 0xB6 ++ ++/** This request writes a DWORD value into a register at the specified offset */ ++#define VEN_CORE_WRITE_REGISTER 0xB7 ++ ++/** This structure is the header of the Core Features dataset returned to ++ * the Host ++ */ ++struct cfi_all_features_header { ++/** The features header structure length is */ ++#define CFI_ALL_FEATURES_HDR_LEN 8 ++ /** ++ * The total length of the features dataset returned to the Host ++ */ ++ uint16_t wTotalLen; ++ ++ /** ++ * CFI version number inBinary-Coded Decimal (i.e., 1.00 is 100H). ++ * This field identifies the version of the CFI Specification with which ++ * the device is compliant. ++ */ ++ uint16_t wVersion; ++ ++ /** The ID of the Core */ ++ uint16_t wCoreID; ++#define CFI_CORE_ID_UDC 1 ++#define CFI_CORE_ID_OTG 2 ++#define CFI_CORE_ID_WUDEV 3 ++ ++ /** Number of features returned by VEN_CORE_GET_FEATURES request */ ++ uint16_t wNumFeatures; ++} UPACKED; ++ ++typedef struct cfi_all_features_header cfi_all_features_header_t; ++ ++/** This structure is a header of the Core Feature descriptor dataset returned to ++ * the Host after the VEN_CORE_GET_FEATURES request ++ */ ++struct cfi_feature_desc_header { ++#define CFI_FEATURE_DESC_HDR_LEN 8 ++ ++ /** The feature ID */ ++ uint16_t wFeatureID; ++ ++ /** Length of this feature descriptor in bytes - including the ++ * length of the feature name string ++ */ ++ uint16_t wLength; ++ ++ /** The data length of this feature in bytes */ ++ uint16_t wDataLength; ++ ++ /** ++ * Attributes of this features ++ * D0: Access rights ++ * 0 - Read/Write ++ * 1 - Read only ++ */ ++ uint8_t bmAttributes; ++#define CFI_FEATURE_ATTR_RO 1 ++#define CFI_FEATURE_ATTR_RW 0 ++ ++ /** Length of the feature name in bytes */ ++ uint8_t bNameLen; ++ ++ /** The feature name buffer */ ++ //uint8_t *name; ++} UPACKED; ++ ++typedef struct cfi_feature_desc_header cfi_feature_desc_header_t; ++ ++/** ++ * This structure describes a NULL terminated string referenced by its id field. ++ * It is very similar to usb_string structure but has the id field type set to 16-bit. ++ */ ++struct cfi_string { ++ uint16_t id; ++ const uint8_t *s; ++}; ++typedef struct cfi_string cfi_string_t; ++ ++#endif +Index: linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_attr.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_attr.c 2013-07-26 19:31:22.000000000 +0000 +@@ -0,0 +1,1316 @@ ++/* ========================================================================== ++ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_attr.c $ ++ * $Revision: #35 $ ++ * $Date: 2009/04/03 $ ++ * $Change: 1225160 $ ++ * ++ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, ++ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless ++ * otherwise expressly agreed to in writing between Synopsys and you. ++ * ++ * The Software IS NOT an item of Licensed Software or Licensed Product under ++ * any End User Software License Agreement or Agreement for Licensed Product ++ * with Synopsys or any supplement thereto. You are permitted to use and ++ * redistribute this Software in source and binary forms, with or without ++ * modification, provided that redistributions of source code must retain this ++ * notice. You may not view, use, disclose, copy or distribute this file or ++ * any information contained herein except pursuant to this license grant from ++ * Synopsys. If you do not agree with this notice, including the disclaimer ++ * below, then you are not authorized to use the Software. ++ * ++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, ++ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR ++ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER ++ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY ++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH ++ * DAMAGE. ++ * ========================================================================== */ ++ ++/** @file ++ * ++ * The diagnostic interface will provide access to the controller for ++ * bringing up the hardware and testing. The Linux driver attributes ++ * feature will be used to provide the Linux Diagnostic ++ * Interface. These attributes are accessed through sysfs. ++ */ ++ ++/** @page "Linux Module Attributes" ++ * ++ * The Linux module attributes feature is used to provide the Linux ++ * Diagnostic Interface. These attributes are accessed through sysfs. ++ * The diagnostic interface will provide access to the controller for ++ * bringing up the hardware and testing. ++ ++ The following table shows the attributes. ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
Name Description Access
mode Returns the current mode: 0 for device mode, 1 for host mode Read
hnpcapable Gets or sets the "HNP-capable" bit in the Core USB Configuraton Register. ++ Read returns the current value. Read/Write
srpcapable Gets or sets the "SRP-capable" bit in the Core USB Configuraton Register. ++ Read returns the current value. Read/Write
hsic_connect Gets or sets the "HSIC-Connect" bit in the GLPMCFG Register. ++ Read returns the current value. Read/Write
inv_sel_hsic Gets or sets the "Invert Select HSIC" bit in the GLPMFG Register. ++ Read returns the current value. Read/Write
hnp Initiates the Host Negotiation Protocol. Read returns the status. Read/Write
srp Initiates the Session Request Protocol. Read returns the status. Read/Write
buspower Gets or sets the Power State of the bus (0 - Off or 1 - On) Read/Write
bussuspend Suspends the USB bus. Read/Write
busconnected Gets the connection status of the bus Read
gotgctl Gets or sets the Core Control Status Register. Read/Write
gusbcfg Gets or sets the Core USB Configuration Register Read/Write
grxfsiz Gets or sets the Receive FIFO Size Register Read/Write
gnptxfsiz Gets or sets the non-periodic Transmit Size Register Read/Write
gpvndctl Gets or sets the PHY Vendor Control Register Read/Write
ggpio Gets the value in the lower 16-bits of the General Purpose IO Register ++ or sets the upper 16 bits. Read/Write
guid Gets or sets the value of the User ID Register Read/Write
gsnpsid Gets the value of the Synopsys ID Regester Read
devspeed Gets or sets the device speed setting in the DCFG register Read/Write
enumspeed Gets the device enumeration Speed. Read
hptxfsiz Gets the value of the Host Periodic Transmit FIFO Read
hprt0 Gets or sets the value in the Host Port Control and Status Register Read/Write
regoffset Sets the register offset for the next Register Access Read/Write
regvalue Gets or sets the value of the register at the offset in the regoffset attribute. Read/Write
remote_wakeup On read, shows the status of Remote Wakeup. On write, initiates a remote ++ wakeup of the host. When bit 0 is 1 and Remote Wakeup is enabled, the Remote ++ Wakeup signalling bit in the Device Control Register is set for 1 ++ milli-second. Read/Write
regdump Dumps the contents of core registers. Read
spramdump Dumps the contents of core registers. Read
hcddump Dumps the current HCD state. Read
hcd_frrem Shows the average value of the Frame Remaining ++ field in the Host Frame Number/Frame Remaining register when an SOF interrupt ++ occurs. This can be used to determine the average interrupt latency. Also ++ shows the average Frame Remaining value for start_transfer and the "a" and ++ "b" sample points. The "a" and "b" sample points may be used during debugging ++ bto determine how long it takes to execute a section of the HCD code. Read
rd_reg_test Displays the time required to read the GNPTXFSIZ register many times ++ (the output shows the number of times the register is read). ++ Read
wr_reg_test Displays the time required to write the GNPTXFSIZ register many times ++ (the output shows the number of times the register is written). ++ Read
lpm_response Gets or sets lpm_response mode. Applicable only in device mode. ++ Write
sleep_local_dev Generetates sleep signaling. Applicable only in host mode. ++ Write
sleep_status Shows sleep status of device. ++ Read
++ ++ Example usage: ++ To get the current mode: ++ cat /sys/devices/lm0/mode ++ ++ To power down the USB: ++ echo 0 > /sys/devices/lm0/buspower ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include /* permission constants */ ++#include ++#include ++#include ++#include ++ ++ ++#ifdef LM_INTERFACE ++#include ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30)) ++#include ++#else ++/* in 2.6.31, at least, we seem to have lost the generic LM infrastructure - ++ here we use definitions stolen from arm-integrator headers ++*/ ++#include ++#endif ++#elif defined(PLATFORM_INTERFACE) ++#include ++#endif ++ ++#include ++ ++#include "dwc_os.h" ++#include "dwc_otg_driver.h" ++#include "dwc_otg_attr.h" ++#include "dwc_otg_core_if.h" ++#include "dwc_otg_pcd_if.h" ++#include "dwc_otg_hcd_if.h" ++ ++/* ++ * MACROs for defining sysfs attribute ++ */ ++#ifdef LM_INTERFACE ++ ++#define DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_string_) \ ++static ssize_t _otg_attr_name_##_show (struct device *_dev, struct device_attribute *attr, char *buf) \ ++{ \ ++ struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev); \ ++ dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev); \ ++ uint32_t val; \ ++ val = dwc_otg_get_##_otg_attr_name_ (otg_dev->core_if); \ ++ return sprintf (buf, "%s = 0x%x\n", _string_, val); \ ++} ++#define DWC_OTG_DEVICE_ATTR_BITFIELD_STORE(_otg_attr_name_,_string_) \ ++static ssize_t _otg_attr_name_##_store (struct device *_dev, struct device_attribute *attr, \ ++ const char *buf, size_t count) \ ++{ \ ++ struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev); \ ++ dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev); \ ++ uint32_t set = simple_strtoul(buf, NULL, 16); \ ++ dwc_otg_set_##_otg_attr_name_(otg_dev->core_if, set);\ ++ return count; \ ++} ++ ++#elif defined(PCI_INTERFACE) ++ ++#define DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_string_) \ ++static ssize_t _otg_attr_name_##_show (struct device *_dev, struct device_attribute *attr, char *buf) \ ++{ \ ++ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); \ ++ uint32_t val; \ ++ val = dwc_otg_get_##_otg_attr_name_ (otg_dev->core_if); \ ++ return sprintf (buf, "%s = 0x%x\n", _string_, val); \ ++} ++#define DWC_OTG_DEVICE_ATTR_BITFIELD_STORE(_otg_attr_name_,_string_) \ ++static ssize_t _otg_attr_name_##_store (struct device *_dev, struct device_attribute *attr, \ ++ const char *buf, size_t count) \ ++{ \ ++ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); \ ++ uint32_t set = simple_strtoul(buf, NULL, 16); \ ++ dwc_otg_set_##_otg_attr_name_(otg_dev->core_if, set);\ ++ return count; \ ++} ++ ++#elif defined(PLATFORM_INTERFACE) ++ ++#define DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_string_) \ ++static ssize_t _otg_attr_name_##_show (struct device *_dev, struct device_attribute *attr, char *buf) \ ++{ \ ++ struct platform_device *platform_dev = \ ++ container_of(_dev, struct platform_device, dev); \ ++ dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev); \ ++ uint32_t val; \ ++ DWC_PRINTF("%s(%p) -> platform_dev %p, otg_dev %p\n", \ ++ __func__, _dev, platform_dev, otg_dev); \ ++ val = dwc_otg_get_##_otg_attr_name_ (otg_dev->core_if); \ ++ return sprintf (buf, "%s = 0x%x\n", _string_, val); \ ++} ++#define DWC_OTG_DEVICE_ATTR_BITFIELD_STORE(_otg_attr_name_,_string_) \ ++static ssize_t _otg_attr_name_##_store (struct device *_dev, struct device_attribute *attr, \ ++ const char *buf, size_t count) \ ++{ \ ++ struct platform_device *platform_dev = container_of(_dev, struct platform_device, dev); \ ++ dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev); \ ++ uint32_t set = simple_strtoul(buf, NULL, 16); \ ++ dwc_otg_set_##_otg_attr_name_(otg_dev->core_if, set);\ ++ return count; \ ++} ++#endif ++ ++/* ++ * MACROs for defining sysfs attribute for 32-bit registers ++ */ ++#ifdef LM_INTERFACE ++#define DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_string_) \ ++static ssize_t _otg_attr_name_##_show (struct device *_dev, struct device_attribute *attr, char *buf) \ ++{ \ ++ struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev); \ ++ dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev); \ ++ uint32_t val; \ ++ val = dwc_otg_get_##_otg_attr_name_ (otg_dev->core_if); \ ++ return sprintf (buf, "%s = 0x%08x\n", _string_, val); \ ++} ++#define DWC_OTG_DEVICE_ATTR_REG_STORE(_otg_attr_name_,_string_) \ ++static ssize_t _otg_attr_name_##_store (struct device *_dev, struct device_attribute *attr, \ ++ const char *buf, size_t count) \ ++{ \ ++ struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev); \ ++ dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev); \ ++ uint32_t val = simple_strtoul(buf, NULL, 16); \ ++ dwc_otg_set_##_otg_attr_name_ (otg_dev->core_if, val); \ ++ return count; \ ++} ++#elif defined(PCI_INTERFACE) ++#define DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_string_) \ ++static ssize_t _otg_attr_name_##_show (struct device *_dev, struct device_attribute *attr, char *buf) \ ++{ \ ++ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); \ ++ uint32_t val; \ ++ val = dwc_otg_get_##_otg_attr_name_ (otg_dev->core_if); \ ++ return sprintf (buf, "%s = 0x%08x\n", _string_, val); \ ++} ++#define DWC_OTG_DEVICE_ATTR_REG_STORE(_otg_attr_name_,_string_) \ ++static ssize_t _otg_attr_name_##_store (struct device *_dev, struct device_attribute *attr, \ ++ const char *buf, size_t count) \ ++{ \ ++ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); \ ++ uint32_t val = simple_strtoul(buf, NULL, 16); \ ++ dwc_otg_set_##_otg_attr_name_ (otg_dev->core_if, val); \ ++ return count; \ ++} ++ ++#elif defined(PLATFORM_INTERFACE) ++#include "dwc_otg_dbg.h" ++#define DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_string_) \ ++static ssize_t _otg_attr_name_##_show (struct device *_dev, struct device_attribute *attr, char *buf) \ ++{ \ ++ struct platform_device *platform_dev = container_of(_dev, struct platform_device, dev); \ ++ dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev); \ ++ uint32_t val; \ ++ DWC_PRINTF("%s(%p) -> platform_dev %p, otg_dev %p\n", \ ++ __func__, _dev, platform_dev, otg_dev); \ ++ val = dwc_otg_get_##_otg_attr_name_ (otg_dev->core_if); \ ++ return sprintf (buf, "%s = 0x%08x\n", _string_, val); \ ++} ++#define DWC_OTG_DEVICE_ATTR_REG_STORE(_otg_attr_name_,_string_) \ ++static ssize_t _otg_attr_name_##_store (struct device *_dev, struct device_attribute *attr, \ ++ const char *buf, size_t count) \ ++{ \ ++ struct platform_device *platform_dev = container_of(_dev, struct platform_device, dev); \ ++ dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev); \ ++ uint32_t val = simple_strtoul(buf, NULL, 16); \ ++ dwc_otg_set_##_otg_attr_name_ (otg_dev->core_if, val); \ ++ return count; \ ++} ++ ++#endif ++ ++#define DWC_OTG_DEVICE_ATTR_BITFIELD_RW(_otg_attr_name_,_string_) \ ++DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_string_) \ ++DWC_OTG_DEVICE_ATTR_BITFIELD_STORE(_otg_attr_name_,_string_) \ ++DEVICE_ATTR(_otg_attr_name_,0644,_otg_attr_name_##_show,_otg_attr_name_##_store); ++ ++#define DWC_OTG_DEVICE_ATTR_BITFIELD_RO(_otg_attr_name_,_string_) \ ++DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_string_) \ ++DEVICE_ATTR(_otg_attr_name_,0444,_otg_attr_name_##_show,NULL); ++ ++#define DWC_OTG_DEVICE_ATTR_REG32_RW(_otg_attr_name_,_addr_,_string_) \ ++DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_string_) \ ++DWC_OTG_DEVICE_ATTR_REG_STORE(_otg_attr_name_,_string_) \ ++DEVICE_ATTR(_otg_attr_name_,0644,_otg_attr_name_##_show,_otg_attr_name_##_store); ++ ++#define DWC_OTG_DEVICE_ATTR_REG32_RO(_otg_attr_name_,_addr_,_string_) \ ++DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_string_) \ ++DEVICE_ATTR(_otg_attr_name_,0444,_otg_attr_name_##_show,NULL); ++ ++/** @name Functions for Show/Store of Attributes */ ++/**@{*/ ++ ++/** ++ * Show the register offset of the Register Access. ++ */ ++static ssize_t regoffset_show(struct device *_dev, ++ struct device_attribute *attr, char *buf) ++{ ++#ifdef LM_INTERFACE ++ struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev); ++ dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev); ++#elif defined(PCI_INTERFACE) ++ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); ++#elif defined(PLATFORM_INTERFACE) ++ struct platform_device *platform_dev = container_of(_dev, ++ struct platform_device, dev); ++ dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev); ++#endif ++ ++ return snprintf(buf, sizeof("0xFFFFFFFF\n") + 1, "0x%08x\n", ++ otg_dev->reg_offset); ++} ++ ++/** ++ * Set the register offset for the next Register Access Read/Write ++ */ ++static ssize_t regoffset_store(struct device *_dev, ++ struct device_attribute *attr, ++ const char *buf, size_t count) ++{ ++#ifdef LM_INTERFACE ++ struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev); ++ dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev); ++#elif defined(PCI_INTERFACE) ++ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); ++#elif defined(PLATFORM_INTERFACE) ++ struct platform_device *platform_dev = container_of(_dev, ++ struct platform_device, dev); ++ dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev); ++#endif ++ ++ uint32_t offset = simple_strtoul(buf, NULL, 16); ++ if (offset < SZ_256K) { ++ otg_dev->reg_offset = offset; ++ } else { ++ dev_err(_dev, "invalid offset\n"); ++ } ++ ++ return count; ++} ++ ++DEVICE_ATTR(regoffset, S_IRUGO | S_IWUSR, regoffset_show, regoffset_store); ++ ++/** ++ * Show the value of the register at the offset in the reg_offset ++ * attribute. ++ */ ++static ssize_t regvalue_show(struct device *_dev, ++ struct device_attribute *attr, char *buf) ++{ ++#ifdef LM_INTERFACE ++ struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev); ++ dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev); ++#elif defined(PCI_INTERFACE) ++ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); ++#elif defined(PLATFORM_INTERFACE) ++ struct platform_device *platform_dev = ++ container_of(_dev, struct platform_device, dev); ++ dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev); ++#endif ++ ++ uint32_t val; ++ volatile uint32_t *addr; ++ ++ if (otg_dev->reg_offset != 0xFFFFFFFF && 0 != otg_dev->base) { ++ /* Calculate the address */ ++ addr = (uint32_t *) (otg_dev->reg_offset + ++ (uint8_t *) otg_dev->base); ++ val = dwc_read_reg32(addr); ++ return snprintf(buf, ++ sizeof("Reg@0xFFFFFFFF = 0xFFFFFFFF\n") + 1, ++ "Reg@0x%06x = 0x%08x\n", otg_dev->reg_offset, ++ val); ++ } else { ++ dev_err(_dev, "Invalid offset (0x%0x)\n", otg_dev->reg_offset); ++ return sprintf(buf, "invalid offset\n"); ++ } ++} ++ ++/** ++ * Store the value in the register at the offset in the reg_offset ++ * attribute. ++ * ++ */ ++static ssize_t regvalue_store(struct device *_dev, ++ struct device_attribute *attr, ++ const char *buf, size_t count) ++{ ++#ifdef LM_INTERFACE ++ struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev); ++ dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev); ++#elif defined(PCI_INTERFACE) ++ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); ++#elif defined(PLATFORM_INTERFACE) ++ struct platform_device *platform_dev = ++ container_of(_dev, struct platform_device, dev); ++ dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev); ++#endif ++ ++ volatile uint32_t *addr; ++ uint32_t val = simple_strtoul(buf, NULL, 16); ++ //dev_dbg(_dev, "Offset=0x%08x Val=0x%08x\n", otg_dev->reg_offset, val); ++ if (otg_dev->reg_offset != 0xFFFFFFFF && 0 != otg_dev->base) { ++ /* Calculate the address */ ++ addr = (uint32_t *) (otg_dev->reg_offset + ++ (uint8_t *) otg_dev->base); ++ dwc_write_reg32(addr, val); ++ } else { ++ dev_err(_dev, "Invalid Register Offset (0x%08x)\n", ++ otg_dev->reg_offset); ++ } ++ return count; ++} ++ ++DEVICE_ATTR(regvalue, S_IRUGO | S_IWUSR, regvalue_show, regvalue_store); ++ ++/* ++ * Attributes ++ */ ++DWC_OTG_DEVICE_ATTR_BITFIELD_RO(mode, "Mode"); ++DWC_OTG_DEVICE_ATTR_BITFIELD_RW(hnpcapable, "HNPCapable"); ++DWC_OTG_DEVICE_ATTR_BITFIELD_RW(srpcapable, "Mode"); ++DWC_OTG_DEVICE_ATTR_BITFIELD_RW(hsic_connect, "HSIC Connect"); ++DWC_OTG_DEVICE_ATTR_BITFIELD_RW(inv_sel_hsic, "Invert Select HSIC"); ++ ++//DWC_OTG_DEVICE_ATTR_BITFIELD_RW(buspower,&(otg_dev->core_if->core_global_regs->gotgctl),(1<<8),8,"Mode"); ++//DWC_OTG_DEVICE_ATTR_BITFIELD_RW(bussuspend,&(otg_dev->core_if->core_global_regs->gotgctl),(1<<8),8,"Mode"); ++DWC_OTG_DEVICE_ATTR_BITFIELD_RO(busconnected, "Bus Connected"); ++ ++DWC_OTG_DEVICE_ATTR_REG32_RW(gotgctl, 0, "GOTGCTL"); ++DWC_OTG_DEVICE_ATTR_REG32_RW(gusbcfg, ++ &(otg_dev->core_if->core_global_regs->gusbcfg), ++ "GUSBCFG"); ++DWC_OTG_DEVICE_ATTR_REG32_RW(grxfsiz, ++ &(otg_dev->core_if->core_global_regs->grxfsiz), ++ "GRXFSIZ"); ++DWC_OTG_DEVICE_ATTR_REG32_RW(gnptxfsiz, ++ &(otg_dev->core_if->core_global_regs->gnptxfsiz), ++ "GNPTXFSIZ"); ++DWC_OTG_DEVICE_ATTR_REG32_RW(gpvndctl, ++ &(otg_dev->core_if->core_global_regs->gpvndctl), ++ "GPVNDCTL"); ++DWC_OTG_DEVICE_ATTR_REG32_RW(ggpio, ++ &(otg_dev->core_if->core_global_regs->ggpio), ++ "GGPIO"); ++DWC_OTG_DEVICE_ATTR_REG32_RW(guid, &(otg_dev->core_if->core_global_regs->guid), ++ "GUID"); ++DWC_OTG_DEVICE_ATTR_REG32_RO(gsnpsid, ++ &(otg_dev->core_if->core_global_regs->gsnpsid), ++ "GSNPSID"); ++DWC_OTG_DEVICE_ATTR_BITFIELD_RW(devspeed, "Device Speed"); ++DWC_OTG_DEVICE_ATTR_BITFIELD_RO(enumspeed, "Device Enumeration Speed"); ++ ++DWC_OTG_DEVICE_ATTR_REG32_RO(hptxfsiz, ++ &(otg_dev->core_if->core_global_regs->hptxfsiz), ++ "HPTXFSIZ"); ++DWC_OTG_DEVICE_ATTR_REG32_RW(hprt0, otg_dev->core_if->host_if->hprt0, "HPRT0"); ++ ++/** ++ * @todo Add code to initiate the HNP. ++ */ ++/** ++ * Show the HNP status bit ++ */ ++static ssize_t hnp_show(struct device *_dev, ++ struct device_attribute *attr, char *buf) ++{ ++#ifdef LM_INTERFACE ++ struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev); ++ dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev); ++#elif defined(PCI_INTERFACE) ++ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); ++#elif defined(PLATFORM_INTERFACE) ++ struct platform_device *platform_dev = ++ container_of(_dev, struct platform_device, dev); ++ dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev); ++#endif ++ return sprintf(buf, "HstNegScs = 0x%x\n", ++ dwc_otg_get_hnpstatus(otg_dev->core_if)); ++} ++ ++/** ++ * Set the HNP Request bit ++ */ ++static ssize_t hnp_store(struct device *_dev, ++ struct device_attribute *attr, ++ const char *buf, size_t count) ++{ ++#ifdef LM_INTERFACE ++ struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev); ++ dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev); ++#elif defined(PCI_INTERFACE) ++ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); ++#elif defined(PLATFORM_INTERFACE) ++ struct platform_device *platform_dev = ++ container_of(_dev, struct platform_device, dev); ++ dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev); ++#endif ++ uint32_t in = simple_strtoul(buf, NULL, 16); ++ dwc_otg_set_hnpreq(otg_dev->core_if, in); ++ return count; ++} ++ ++DEVICE_ATTR(hnp, 0644, hnp_show, hnp_store); ++ ++/** ++ * @todo Add code to initiate the SRP. ++ */ ++/** ++ * Show the SRP status bit ++ */ ++static ssize_t srp_show(struct device *_dev, ++ struct device_attribute *attr, char *buf) ++{ ++#ifndef DWC_HOST_ONLY ++#ifdef LM_INTERFACE ++ struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev); ++ dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev); ++#elif defined(PCI_INTERFACE) ++ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); ++#elif defined(PLATFORM_INTERFACE) ++ struct platform_device *platform_dev = ++ container_of(_dev, struct platform_device, dev); ++ dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev); ++#endif ++ return sprintf(buf, "SesReqScs = 0x%x\n", ++ dwc_otg_get_srpstatus(otg_dev->core_if)); ++#else ++ return sprintf(buf, "Host Only Mode!\n"); ++#endif ++} ++ ++/** ++ * Set the SRP Request bit ++ */ ++static ssize_t srp_store(struct device *_dev, ++ struct device_attribute *attr, ++ const char *buf, size_t count) ++{ ++#ifndef DWC_HOST_ONLY ++#ifdef LM_INTERFACE ++ struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev); ++ dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev); ++#elif defined(PCI_INTERFACE) ++ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); ++#elif defined(PLATFORM_INTERFACE) ++ struct platform_device *platform_dev = ++ container_of(_dev, struct platform_device, dev); ++ dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev); ++#endif ++ dwc_otg_pcd_initiate_srp(otg_dev->pcd); ++#endif ++ return count; ++} ++ ++DEVICE_ATTR(srp, 0644, srp_show, srp_store); ++ ++/** ++ * @todo Need to do more for power on/off? ++ */ ++/** ++ * Show the Bus Power status ++ */ ++static ssize_t buspower_show(struct device *_dev, ++ struct device_attribute *attr, char *buf) ++{ ++#ifdef LM_INTERFACE ++ struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev); ++ dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev); ++#elif defined(PCI_INTERFACE) ++ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); ++#elif defined(PLATFORM_INTERFACE) ++ struct platform_device *platform_dev = ++ container_of(_dev, struct platform_device, dev); ++ dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev); ++#endif ++ return sprintf(buf, "Bus Power = 0x%x\n", ++ dwc_otg_get_prtpower(otg_dev->core_if)); ++} ++ ++/** ++ * Set the Bus Power status ++ */ ++static ssize_t buspower_store(struct device *_dev, ++ struct device_attribute *attr, ++ const char *buf, size_t count) ++{ ++#ifdef LM_INTERFACE ++ struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev); ++ dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev); ++#elif defined(PCI_INTERFACE) ++ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); ++#elif defined(PLATFORM_INTERFACE) ++ struct platform_device *platform_dev = ++ container_of(_dev, struct platform_device, dev); ++ dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev); ++#endif ++ uint32_t on = simple_strtoul(buf, NULL, 16); ++ dwc_otg_set_prtpower(otg_dev->core_if, on); ++ return count; ++} ++ ++DEVICE_ATTR(buspower, 0644, buspower_show, buspower_store); ++ ++/** ++ * @todo Need to do more for suspend? ++ */ ++/** ++ * Show the Bus Suspend status ++ */ ++static ssize_t bussuspend_show(struct device *_dev, ++ struct device_attribute *attr, char *buf) ++{ ++#ifdef LM_INTERFACE ++ struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev); ++ dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev); ++#elif defined(PCI_INTERFACE) ++ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); ++#elif defined(PLATFORM_INTERFACE) ++ struct platform_device *platform_dev = ++ container_of(_dev, struct platform_device, dev); ++ dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev); ++#endif ++ ++ return sprintf(buf, "Bus Suspend = 0x%x\n", ++ dwc_otg_get_prtsuspend(otg_dev->core_if)); ++} ++ ++/** ++ * Set the Bus Suspend status ++ */ ++static ssize_t bussuspend_store(struct device *_dev, ++ struct device_attribute *attr, ++ const char *buf, size_t count) ++{ ++#ifdef LM_INTERFACE ++ struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev); ++ dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev); ++#elif defined(PCI_INTERFACE) ++ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); ++#elif defined(PLATFORM_INTERFACE) ++ struct platform_device *platform_dev = ++ container_of(_dev, struct platform_device, dev); ++ dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev); ++#endif ++ ++ uint32_t in = simple_strtoul(buf, NULL, 16); ++ dwc_otg_set_prtsuspend(otg_dev->core_if, in); ++ return count; ++} ++ ++DEVICE_ATTR(bussuspend, 0644, bussuspend_show, bussuspend_store); ++ ++/** ++ * Show the status of Remote Wakeup. ++ */ ++static ssize_t remote_wakeup_show(struct device *_dev, ++ struct device_attribute *attr, char *buf) ++{ ++#ifndef DWC_HOST_ONLY ++#ifdef LM_INTERFACE ++ struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev); ++ dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev); ++#elif defined(PCI_INTERFACE) ++ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); ++#elif defined(PLATFORM_INTERFACE) ++ struct platform_device *platform_dev = ++ container_of(_dev, struct platform_device, dev); ++ dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev); ++#endif ++ ++ return sprintf(buf, ++ "Remote Wakeup Sig = %d Enabled = %d LPM Remote Wakeup = %d\n", ++ dwc_otg_get_remotewakesig(otg_dev->core_if), ++ dwc_otg_pcd_get_rmwkup_enable(otg_dev->pcd), ++ dwc_otg_get_lpm_remotewakeenabled(otg_dev->core_if)); ++#else ++ return sprintf(buf, "Host Only Mode!\n"); ++#endif /* DWC_HOST_ONLY */ ++} ++ ++/** ++ * Initiate a remote wakeup of the host. The Device control register ++ * Remote Wakeup Signal bit is written if the PCD Remote wakeup enable ++ * flag is set. ++ * ++ */ ++static ssize_t remote_wakeup_store(struct device *_dev, ++ struct device_attribute *attr, ++ const char *buf, size_t count) ++{ ++#ifndef DWC_HOST_ONLY ++#ifdef LM_INTERFACE ++ struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev); ++ dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev); ++#elif defined(PCI_INTERFACE) ++ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); ++#elif defined(PLATFORM_INTERFACE) ++ struct platform_device *platform_dev = ++ container_of(_dev, struct platform_device, dev); ++ dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev); ++#endif ++ ++ uint32_t val = simple_strtoul(buf, NULL, 16); ++ ++ if (val & 1) { ++ dwc_otg_pcd_remote_wakeup(otg_dev->pcd, 1); ++ } else { ++ dwc_otg_pcd_remote_wakeup(otg_dev->pcd, 0); ++ } ++#endif /* DWC_HOST_ONLY */ ++ return count; ++} ++ ++DEVICE_ATTR(remote_wakeup, S_IRUGO | S_IWUSR, remote_wakeup_show, ++ remote_wakeup_store); ++ ++/** ++ * Dump global registers and either host or device registers (depending on the ++ * current mode of the core). ++ */ ++static ssize_t regdump_show(struct device *_dev, ++ struct device_attribute *attr, char *buf) ++{ ++#ifdef LM_INTERFACE ++ struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev); ++ dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev); ++#elif defined(PCI_INTERFACE) ++ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); ++#elif defined(PLATFORM_INTERFACE) ++ struct platform_device *platform_dev = ++ container_of(_dev, struct platform_device, dev); ++ dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev); ++#endif ++ ++ dwc_otg_dump_global_registers(otg_dev->core_if); ++ if (dwc_otg_is_host_mode(otg_dev->core_if)) { ++ dwc_otg_dump_host_registers(otg_dev->core_if); ++ } else { ++ dwc_otg_dump_dev_registers(otg_dev->core_if); ++ ++ } ++ return sprintf(buf, "Register Dump\n"); ++} ++ ++DEVICE_ATTR(regdump, S_IRUGO | S_IWUSR, regdump_show, 0); ++ ++/** ++ * Dump global registers and either host or device registers (depending on the ++ * current mode of the core). ++ */ ++static ssize_t spramdump_show(struct device *_dev, ++ struct device_attribute *attr, char *buf) ++{ ++#ifdef LM_INTERFACE ++ struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev); ++ dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev); ++#elif defined(PCI_INTERFACE) ++ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); ++#elif defined(PLATFORM_INTERFACE) ++ struct platform_device *platform_dev = ++ container_of(_dev, struct platform_device, dev); ++ dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev); ++#endif ++ ++ dwc_otg_dump_spram(otg_dev->core_if); ++ ++ return sprintf(buf, "SPRAM Dump\n"); ++} ++ ++DEVICE_ATTR(spramdump, S_IRUGO | S_IWUSR, spramdump_show, 0); ++ ++/** ++ * Dump the current hcd state. ++ */ ++static ssize_t hcddump_show(struct device *_dev, ++ struct device_attribute *attr, char *buf) ++{ ++#ifndef DWC_DEVICE_ONLY ++#ifdef LM_INTERFACE ++ struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev); ++ dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev); ++#elif defined(PCI_INTERFACE) ++ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); ++#elif defined(PLATFORM_INTERFACE) ++ struct platform_device *platform_dev = ++ container_of(_dev, struct platform_device, dev); ++ dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev); ++#endif ++ ++ dwc_otg_hcd_dump_state(otg_dev->hcd); ++#endif /* DWC_DEVICE_ONLY */ ++ return sprintf(buf, "HCD Dump\n"); ++} ++ ++DEVICE_ATTR(hcddump, S_IRUGO | S_IWUSR, hcddump_show, 0); ++ ++/** ++ * Dump the average frame remaining at SOF. This can be used to ++ * determine average interrupt latency. Frame remaining is also shown for ++ * start transfer and two additional sample points. ++ */ ++static ssize_t hcd_frrem_show(struct device *_dev, ++ struct device_attribute *attr, char *buf) ++{ ++#ifndef DWC_DEVICE_ONLY ++#ifdef LM_INTERFACE ++ struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev); ++ dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev); ++#elif defined(PCI_INTERFACE) ++ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); ++#elif defined(PLATFORM_INTERFACE) ++ struct platform_device *platform_dev = ++ container_of(_dev, struct platform_device, dev); ++ dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev); ++#endif ++ ++ dwc_otg_hcd_dump_frrem(otg_dev->hcd); ++#endif /* DWC_DEVICE_ONLY */ ++ return sprintf(buf, "HCD Dump Frame Remaining\n"); ++} ++ ++DEVICE_ATTR(hcd_frrem, S_IRUGO | S_IWUSR, hcd_frrem_show, 0); ++ ++/** ++ * Displays the time required to read the GNPTXFSIZ register many times (the ++ * output shows the number of times the register is read). ++ */ ++#define RW_REG_COUNT 10000000 ++#define MSEC_PER_JIFFIE 1000/HZ ++static ssize_t rd_reg_test_show(struct device *_dev, ++ struct device_attribute *attr, char *buf) ++{ ++#ifdef LM_INTERFACE ++ struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev); ++ dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev); ++#elif defined(PCI_INTERFACE) ++ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); ++#elif defined(PLATFORM_INTERFACE) ++ struct platform_device *platform_dev = ++ container_of(_dev, struct platform_device, dev); ++ dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev); ++#endif ++ ++ int i; ++ int time; ++ int start_jiffies; ++ ++ printk("HZ %d, MSEC_PER_JIFFIE %d, loops_per_jiffy %lu\n", ++ HZ, MSEC_PER_JIFFIE, loops_per_jiffy); ++ start_jiffies = jiffies; ++ for (i = 0; i < RW_REG_COUNT; i++) { ++ dwc_otg_get_gnptxfsiz(otg_dev->core_if); ++ } ++ time = jiffies - start_jiffies; ++ return sprintf(buf, ++ "Time to read GNPTXFSIZ reg %d times: %d msecs (%d jiffies)\n", ++ RW_REG_COUNT, time * MSEC_PER_JIFFIE, time); ++} ++ ++DEVICE_ATTR(rd_reg_test, S_IRUGO | S_IWUSR, rd_reg_test_show, 0); ++ ++/** ++ * Displays the time required to write the GNPTXFSIZ register many times (the ++ * output shows the number of times the register is written). ++ */ ++static ssize_t wr_reg_test_show(struct device *_dev, ++ struct device_attribute *attr, char *buf) ++{ ++#ifdef LM_INTERFACE ++ struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev); ++ dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev); ++#elif defined(PCI_INTERFACE) ++ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); ++#elif defined(PLATFORM_INTERFACE) ++ struct platform_device *platform_dev = ++ container_of(_dev, struct platform_device, dev); ++ dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev); ++#endif ++ ++ uint32_t reg_val; ++ int i; ++ int time; ++ int start_jiffies; ++ ++ printk("HZ %d, MSEC_PER_JIFFIE %d, loops_per_jiffy %lu\n", ++ HZ, MSEC_PER_JIFFIE, loops_per_jiffy); ++ reg_val = dwc_otg_get_gnptxfsiz(otg_dev->core_if); ++ start_jiffies = jiffies; ++ for (i = 0; i < RW_REG_COUNT; i++) { ++ dwc_otg_set_gnptxfsiz(otg_dev->core_if, reg_val); ++ } ++ time = jiffies - start_jiffies; ++ return sprintf(buf, ++ "Time to write GNPTXFSIZ reg %d times: %d msecs (%d jiffies)\n", ++ RW_REG_COUNT, time * MSEC_PER_JIFFIE, time); ++} ++ ++DEVICE_ATTR(wr_reg_test, S_IRUGO | S_IWUSR, wr_reg_test_show, 0); ++ ++#ifdef CONFIG_USB_DWC_OTG_LPM ++ ++/** ++* Show the lpm_response attribute. ++*/ ++static ssize_t lpmresp_show(struct device *_dev, ++ struct device_attribute *attr, char *buf) ++{ ++#ifdef LM_INTERFACE ++ struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev); ++ dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev); ++#elif defined(PCI_INTERFACE) ++ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); ++#elif defined(PLATFORM_INTERFACE) ++ struct platform_device *platform_dev = ++ container_of(_dev, struct platform_device, dev); ++ dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev); ++#endif ++ ++ if (!dwc_otg_get_param_lpm_enable(otg_dev->core_if)) ++ return sprintf(buf, "** LPM is DISABLED **\n"); ++ ++ if (!dwc_otg_is_device_mode(otg_dev->core_if)) { ++ return sprintf(buf, "** Current mode is not device mode\n"); ++ } ++ return sprintf(buf, "lpm_response = %d\n", ++ dwc_otg_get_lpmresponse(otg_dev->core_if)); ++} ++ ++/** ++* Store the lpm_response attribute. ++*/ ++static ssize_t lpmresp_store(struct device *_dev, ++ struct device_attribute *attr, ++ const char *buf, size_t count) ++{ ++#ifdef LM_INTERFACE ++ struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev); ++ dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev); ++#elif defined(PCI_INTERFACE) ++ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); ++#elif defined(PLATFORM_INTERFACE) ++ struct platform_device *platform_dev = ++ container_of(_dev, struct platform_device, dev); ++ dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev); ++#endif ++ ++ uint32_t val = simple_strtoul(buf, NULL, 16); ++ ++ if (!dwc_otg_get_param_lpm_enable(otg_dev->core_if)) { ++ return 0; ++ } ++ ++ if (!dwc_otg_is_device_mode(otg_dev->core_if)) { ++ return 0; ++ } ++ ++ dwc_otg_set_lpmresponse(otg_dev->core_if, val); ++ return count; ++} ++ ++DEVICE_ATTR(lpm_response, S_IRUGO | S_IWUSR, lpmresp_show, lpmresp_store); ++ ++/** ++* Show the sleep_status attribute. ++*/ ++static ssize_t sleepstatus_show(struct device *_dev, ++ struct device_attribute *attr, char *buf) ++{ ++#ifdef LM_INTERFACE ++ struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev); ++ dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev); ++#elif defined(PCI_INTERFACE) ++ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); ++#elif defined(PLATFORM_INTERFACE) ++ struct platform_device *platform_dev = ++ container_of(_dev, struct platform_device, dev); ++ dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev); ++#endif ++ ++ ++ return sprintf(buf, "Sleep Status = %d\n", ++ dwc_otg_get_lpm_portsleepstatus(otg_dev->core_if)); ++} ++ ++/** ++ * Store the sleep_status attribure. ++ */ ++static ssize_t sleepstatus_store(struct device *_dev, ++ struct device_attribute *attr, ++ const char *buf, size_t count) ++{ ++#ifdef LM_INTERFACE ++ struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev); ++ dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev); ++#elif defined(PCI_INTERFACE) ++ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); ++#elif defined(PLATFORM_INTERFACE) ++ struct platform_device *platform_dev = ++ container_of(_dev, struct platform_device, dev); ++ dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev); ++#endif ++ ++ dwc_otg_core_if_t *core_if = otg_dev->core_if; ++ ++ if (dwc_otg_get_lpm_portsleepstatus(otg_dev->core_if)) { ++ if (dwc_otg_is_host_mode(core_if)) { ++ ++ DWC_PRINTF("Host initiated resume\n"); ++ dwc_otg_set_prtresume(otg_dev->core_if, 1); ++ } ++ } ++ ++ return count; ++} ++ ++DEVICE_ATTR(sleep_status, S_IRUGO | S_IWUSR, sleepstatus_show, ++ sleepstatus_store); ++ ++#endif /* CONFIG_USB_DWC_OTG_LPM_ENABLE */ ++ ++/**@}*/ ++ ++/** ++ * Create the device files ++ */ ++void dwc_otg_attr_create ( ++#ifdef LM_INTERFACE ++ struct lm_device *dev ++#elif defined(PCI_INTERFACE) ++ struct pci_dev *dev ++#elif defined(PLATFORM_INTERFACE) ++ struct platform_device *dev ++#endif ++ ) ++ ++{ ++ int error; ++ ++ error = device_create_file(&dev->dev, &dev_attr_regoffset); ++ error = device_create_file(&dev->dev, &dev_attr_regvalue); ++ error = device_create_file(&dev->dev, &dev_attr_mode); ++ error = device_create_file(&dev->dev, &dev_attr_hnpcapable); ++ error = device_create_file(&dev->dev, &dev_attr_srpcapable); ++ error = device_create_file(&dev->dev, &dev_attr_hsic_connect); ++ error = device_create_file(&dev->dev, &dev_attr_inv_sel_hsic); ++ error = device_create_file(&dev->dev, &dev_attr_hnp); ++ error = device_create_file(&dev->dev, &dev_attr_srp); ++ error = device_create_file(&dev->dev, &dev_attr_buspower); ++ error = device_create_file(&dev->dev, &dev_attr_bussuspend); ++ error = device_create_file(&dev->dev, &dev_attr_busconnected); ++ error = device_create_file(&dev->dev, &dev_attr_gotgctl); ++ error = device_create_file(&dev->dev, &dev_attr_gusbcfg); ++ error = device_create_file(&dev->dev, &dev_attr_grxfsiz); ++ error = device_create_file(&dev->dev, &dev_attr_gnptxfsiz); ++ error = device_create_file(&dev->dev, &dev_attr_gpvndctl); ++ error = device_create_file(&dev->dev, &dev_attr_ggpio); ++ error = device_create_file(&dev->dev, &dev_attr_guid); ++ error = device_create_file(&dev->dev, &dev_attr_gsnpsid); ++ error = device_create_file(&dev->dev, &dev_attr_devspeed); ++ error = device_create_file(&dev->dev, &dev_attr_enumspeed); ++ error = device_create_file(&dev->dev, &dev_attr_hptxfsiz); ++ error = device_create_file(&dev->dev, &dev_attr_hprt0); ++ error = device_create_file(&dev->dev, &dev_attr_remote_wakeup); ++ error = device_create_file(&dev->dev, &dev_attr_regdump); ++ error = device_create_file(&dev->dev, &dev_attr_spramdump); ++ error = device_create_file(&dev->dev, &dev_attr_hcddump); ++ error = device_create_file(&dev->dev, &dev_attr_hcd_frrem); ++ error = device_create_file(&dev->dev, &dev_attr_rd_reg_test); ++ error = device_create_file(&dev->dev, &dev_attr_wr_reg_test); ++#ifdef CONFIG_USB_DWC_OTG_LPM ++ error = device_create_file(&dev->dev, &dev_attr_lpm_response); ++ error = device_create_file(&dev->dev, &dev_attr_sleep_status); ++#endif ++} ++ ++/** ++ * Remove the device files ++ */ ++void dwc_otg_attr_remove ( ++#ifdef LM_INTERFACE ++ struct lm_device *dev ++#elif defined(PCI_INTERFACE) ++ struct pci_dev *dev ++#elif defined(PLATFORM_INTERFACE) ++ struct platform_device *dev ++#endif ++ ) ++ ++{ ++ device_remove_file(&dev->dev, &dev_attr_regoffset); ++ device_remove_file(&dev->dev, &dev_attr_regvalue); ++ device_remove_file(&dev->dev, &dev_attr_mode); ++ device_remove_file(&dev->dev, &dev_attr_hnpcapable); ++ device_remove_file(&dev->dev, &dev_attr_srpcapable); ++ device_remove_file(&dev->dev, &dev_attr_hsic_connect); ++ device_remove_file(&dev->dev, &dev_attr_inv_sel_hsic); ++ device_remove_file(&dev->dev, &dev_attr_hnp); ++ device_remove_file(&dev->dev, &dev_attr_srp); ++ device_remove_file(&dev->dev, &dev_attr_buspower); ++ device_remove_file(&dev->dev, &dev_attr_bussuspend); ++ device_remove_file(&dev->dev, &dev_attr_busconnected); ++ device_remove_file(&dev->dev, &dev_attr_gotgctl); ++ device_remove_file(&dev->dev, &dev_attr_gusbcfg); ++ device_remove_file(&dev->dev, &dev_attr_grxfsiz); ++ device_remove_file(&dev->dev, &dev_attr_gnptxfsiz); ++ device_remove_file(&dev->dev, &dev_attr_gpvndctl); ++ device_remove_file(&dev->dev, &dev_attr_ggpio); ++ device_remove_file(&dev->dev, &dev_attr_guid); ++ device_remove_file(&dev->dev, &dev_attr_gsnpsid); ++ device_remove_file(&dev->dev, &dev_attr_devspeed); ++ device_remove_file(&dev->dev, &dev_attr_enumspeed); ++ device_remove_file(&dev->dev, &dev_attr_hptxfsiz); ++ device_remove_file(&dev->dev, &dev_attr_hprt0); ++ device_remove_file(&dev->dev, &dev_attr_remote_wakeup); ++ device_remove_file(&dev->dev, &dev_attr_regdump); ++ device_remove_file(&dev->dev, &dev_attr_spramdump); ++ device_remove_file(&dev->dev, &dev_attr_hcddump); ++ device_remove_file(&dev->dev, &dev_attr_hcd_frrem); ++ device_remove_file(&dev->dev, &dev_attr_rd_reg_test); ++ device_remove_file(&dev->dev, &dev_attr_wr_reg_test); ++#ifdef CONFIG_USB_DWC_OTG_LPM ++ device_remove_file(&dev->dev, &dev_attr_lpm_response); ++ device_remove_file(&dev->dev, &dev_attr_sleep_status); ++#endif ++} +Index: linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_attr.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_attr.h 2013-07-26 19:31:23.000000000 +0000 +@@ -0,0 +1,88 @@ ++/* ========================================================================== ++ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_attr.h $ ++ * $Revision: #11 $ ++ * $Date: 2009/04/03 $ ++ * $Change: 1225160 $ ++ * ++ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, ++ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless ++ * otherwise expressly agreed to in writing between Synopsys and you. ++ * ++ * The Software IS NOT an item of Licensed Software or Licensed Product under ++ * any End User Software License Agreement or Agreement for Licensed Product ++ * with Synopsys or any supplement thereto. You are permitted to use and ++ * redistribute this Software in source and binary forms, with or without ++ * modification, provided that redistributions of source code must retain this ++ * notice. You may not view, use, disclose, copy or distribute this file or ++ * any information contained herein except pursuant to this license grant from ++ * Synopsys. If you do not agree with this notice, including the disclaimer ++ * below, then you are not authorized to use the Software. ++ * ++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, ++ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR ++ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER ++ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY ++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH ++ * DAMAGE. ++ * ========================================================================== */ ++ ++#if !defined(__DWC_OTG_ATTR_H__) ++#define __DWC_OTG_ATTR_H__ ++ ++/** @file ++ * This file contains the interface to the Linux device attributes. ++ */ ++extern struct device_attribute dev_attr_regoffset; ++extern struct device_attribute dev_attr_regvalue; ++ ++extern struct device_attribute dev_attr_mode; ++extern struct device_attribute dev_attr_hnpcapable; ++extern struct device_attribute dev_attr_srpcapable; ++extern struct device_attribute dev_attr_hnp; ++extern struct device_attribute dev_attr_srp; ++extern struct device_attribute dev_attr_buspower; ++extern struct device_attribute dev_attr_bussuspend; ++extern struct device_attribute dev_attr_busconnected; ++extern struct device_attribute dev_attr_gotgctl; ++extern struct device_attribute dev_attr_gusbcfg; ++extern struct device_attribute dev_attr_grxfsiz; ++extern struct device_attribute dev_attr_gnptxfsiz; ++extern struct device_attribute dev_attr_gpvndctl; ++extern struct device_attribute dev_attr_ggpio; ++extern struct device_attribute dev_attr_guid; ++extern struct device_attribute dev_attr_gsnpsid; ++extern struct device_attribute dev_attr_devspeed; ++extern struct device_attribute dev_attr_enumspeed; ++extern struct device_attribute dev_attr_hptxfsiz; ++extern struct device_attribute dev_attr_hprt0; ++#ifdef CONFIG_USB_DWC_OTG_LPM ++extern struct device_attribute dev_attr_lpm_response; ++extern struct device_attribute dev_attr_sleep_local_dev; ++extern struct device_attribute devi_attr_sleep_status; ++#endif ++ ++void dwc_otg_attr_create ( ++#ifdef LM_INTERFACE ++ struct lm_device *dev ++#elif defined(PCI_INTERFACE) ++ struct pci_dev *dev ++#elif defined(PLATFORM_INTERFACE) ++ struct platform_device *dev ++#endif ++ ); ++ ++void dwc_otg_attr_remove ( ++#ifdef LM_INTERFACE ++ struct lm_device *dev ++#elif defined(PCI_INTERFACE) ++ struct pci_dev *dev ++#elif defined(PLATFORM_INTERFACE) ++ struct platform_device *dev ++#endif ++ ); ++#endif +Index: linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_cfi.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_cfi.c 2013-07-26 19:31:23.000000000 +0000 +@@ -0,0 +1,1876 @@ ++/* ========================================================================== ++ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, ++ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless ++ * otherwise expressly agreed to in writing between Synopsys and you. ++ * ++ * The Software IS NOT an item of Licensed Software or Licensed Product under ++ * any End User Software License Agreement or Agreement for Licensed Product ++ * with Synopsys or any supplement thereto. You are permitted to use and ++ * redistribute this Software in source and binary forms, with or without ++ * modification, provided that redistributions of source code must retain this ++ * notice. You may not view, use, disclose, copy or distribute this file or ++ * any information contained herein except pursuant to this license grant from ++ * Synopsys. If you do not agree with this notice, including the disclaimer ++ * below, then you are not authorized to use the Software. ++ * ++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, ++ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR ++ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER ++ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY ++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH ++ * DAMAGE. ++ * ========================================================================== */ ++ ++/** @file ++ * ++ * This file contains the most of the CFI implementation for the OTG. ++ */ ++ ++#ifdef DWC_UTE_CFI ++ ++#include "dwc_otg_pcd.h" ++#include "dwc_otg_cfi.h" ++ ++/** This definition should actually migrate to the Portability Library */ ++#define DWC_CONSTANT_CPU_TO_LE16(x) (x) ++ ++extern dwc_otg_pcd_ep_t *get_ep_by_addr(dwc_otg_pcd_t * pcd, u16 wIndex); ++ ++static int cfi_core_features_buf(uint8_t * buf, uint16_t buflen); ++static int cfi_get_feature_value(uint8_t * buf, uint16_t buflen, ++ struct dwc_otg_pcd *pcd, ++ struct cfi_usb_ctrlrequest *ctrl_req); ++static int cfi_set_feature_value(struct dwc_otg_pcd *pcd); ++static int cfi_ep_get_sg_val(uint8_t * buf, struct dwc_otg_pcd *pcd, ++ struct cfi_usb_ctrlrequest *req); ++static int cfi_ep_get_concat_val(uint8_t * buf, struct dwc_otg_pcd *pcd, ++ struct cfi_usb_ctrlrequest *req); ++static int cfi_ep_get_align_val(uint8_t * buf, struct dwc_otg_pcd *pcd, ++ struct cfi_usb_ctrlrequest *req); ++static int cfi_preproc_reset(struct dwc_otg_pcd *pcd, ++ struct cfi_usb_ctrlrequest *req); ++static void cfi_free_ep_bs_dyn_data(cfi_ep_t * cfiep); ++ ++static uint16_t get_dfifo_size(dwc_otg_core_if_t * core_if); ++static int32_t get_rxfifo_size(dwc_otg_core_if_t * core_if, uint16_t wValue); ++static int32_t get_txfifo_size(struct dwc_otg_pcd *pcd, uint16_t wValue); ++ ++static uint8_t resize_fifos(dwc_otg_core_if_t * core_if); ++ ++/** This is the header of the all features descriptor */ ++static cfi_all_features_header_t all_props_desc_header = { ++ .wVersion = DWC_CONSTANT_CPU_TO_LE16(0x100), ++ .wCoreID = DWC_CONSTANT_CPU_TO_LE16(CFI_CORE_ID_OTG), ++ .wNumFeatures = DWC_CONSTANT_CPU_TO_LE16(9), ++}; ++ ++/** This is an array of statically allocated feature descriptors */ ++static cfi_feature_desc_header_t prop_descs[] = { ++ ++ /* FT_ID_DMA_MODE */ ++ { ++ .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_DMA_MODE), ++ .bmAttributes = CFI_FEATURE_ATTR_RW, ++ .wDataLength = DWC_CONSTANT_CPU_TO_LE16(1), ++ }, ++ ++ /* FT_ID_DMA_BUFFER_SETUP */ ++ { ++ .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_DMA_BUFFER_SETUP), ++ .bmAttributes = CFI_FEATURE_ATTR_RW, ++ .wDataLength = DWC_CONSTANT_CPU_TO_LE16(6), ++ }, ++ ++ /* FT_ID_DMA_BUFF_ALIGN */ ++ { ++ .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_DMA_BUFF_ALIGN), ++ .bmAttributes = CFI_FEATURE_ATTR_RW, ++ .wDataLength = DWC_CONSTANT_CPU_TO_LE16(2), ++ }, ++ ++ /* FT_ID_DMA_CONCAT_SETUP */ ++ { ++ .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_DMA_CONCAT_SETUP), ++ .bmAttributes = CFI_FEATURE_ATTR_RW, ++ //.wDataLength = DWC_CONSTANT_CPU_TO_LE16(6), ++ }, ++ ++ /* FT_ID_DMA_CIRCULAR */ ++ { ++ .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_DMA_CIRCULAR), ++ .bmAttributes = CFI_FEATURE_ATTR_RW, ++ .wDataLength = DWC_CONSTANT_CPU_TO_LE16(6), ++ }, ++ ++ /* FT_ID_THRESHOLD_SETUP */ ++ { ++ .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_THRESHOLD_SETUP), ++ .bmAttributes = CFI_FEATURE_ATTR_RW, ++ .wDataLength = DWC_CONSTANT_CPU_TO_LE16(6), ++ }, ++ ++ /* FT_ID_DFIFO_DEPTH */ ++ { ++ .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_DFIFO_DEPTH), ++ .bmAttributes = CFI_FEATURE_ATTR_RO, ++ .wDataLength = DWC_CONSTANT_CPU_TO_LE16(2), ++ }, ++ ++ /* FT_ID_TX_FIFO_DEPTH */ ++ { ++ .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_TX_FIFO_DEPTH), ++ .bmAttributes = CFI_FEATURE_ATTR_RW, ++ .wDataLength = DWC_CONSTANT_CPU_TO_LE16(2), ++ }, ++ ++ /* FT_ID_RX_FIFO_DEPTH */ ++ { ++ .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_RX_FIFO_DEPTH), ++ .bmAttributes = CFI_FEATURE_ATTR_RW, ++ .wDataLength = DWC_CONSTANT_CPU_TO_LE16(2), ++ } ++}; ++ ++/** The table of feature names */ ++cfi_string_t prop_name_table[] = { ++ {FT_ID_DMA_MODE, "dma_mode"}, ++ {FT_ID_DMA_BUFFER_SETUP, "buffer_setup"}, ++ {FT_ID_DMA_BUFF_ALIGN, "buffer_align"}, ++ {FT_ID_DMA_CONCAT_SETUP, "concat_setup"}, ++ {FT_ID_DMA_CIRCULAR, "buffer_circular"}, ++ {FT_ID_THRESHOLD_SETUP, "threshold_setup"}, ++ {FT_ID_DFIFO_DEPTH, "dfifo_depth"}, ++ {FT_ID_TX_FIFO_DEPTH, "txfifo_depth"}, ++ {FT_ID_RX_FIFO_DEPTH, "rxfifo_depth"}, ++ {} ++}; ++ ++/************************************************************************/ ++ ++/** ++ * Returns the name of the feature by its ID ++ * or NULL if no featute ID matches. ++ * ++ */ ++const uint8_t *get_prop_name(uint16_t prop_id, int *len) ++{ ++ cfi_string_t *pstr; ++ *len = 0; ++ ++ for (pstr = prop_name_table; pstr && pstr->s; pstr++) { ++ if (pstr->id == prop_id) { ++ *len = DWC_STRLEN(pstr->s); ++ return pstr->s; ++ } ++ } ++ return NULL; ++} ++ ++/** ++ * This function handles all CFI specific control requests. ++ * ++ * Return a negative value to stall the DCE. ++ */ ++int cfi_setup(struct dwc_otg_pcd *pcd, struct cfi_usb_ctrlrequest *ctrl) ++{ ++ int retval = 0; ++ dwc_otg_pcd_ep_t *ep = NULL; ++ cfiobject_t *cfi = pcd->cfi; ++ struct dwc_otg_core_if *coreif = GET_CORE_IF(pcd); ++ uint16_t wLen = DWC_LE16_TO_CPU(&ctrl->wLength); ++ uint16_t wValue = DWC_LE16_TO_CPU(&ctrl->wValue); ++ uint16_t wIndex = DWC_LE16_TO_CPU(&ctrl->wIndex); ++ uint32_t regaddr = 0; ++ uint32_t regval = 0; ++ ++ /* Save this Control Request in the CFI object. ++ * The data field will be assigned in the data stage completion CB function. ++ */ ++ cfi->ctrl_req = *ctrl; ++ cfi->ctrl_req.data = NULL; ++ ++ cfi->need_gadget_att = 0; ++ cfi->need_status_in_complete = 0; ++ ++ switch (ctrl->bRequest) { ++ case VEN_CORE_GET_FEATURES: ++ retval = cfi_core_features_buf(cfi->buf_in.buf, CFI_IN_BUF_LEN); ++ if (retval >= 0) { ++ //dump_msg(cfi->buf_in.buf, retval); ++ ep = &pcd->ep0; ++ ++ retval = min((uint16_t) retval, wLen); ++ /* Transfer this buffer to the host through the EP0-IN EP */ ++ ep->dwc_ep.dma_addr = cfi->buf_in.addr; ++ ep->dwc_ep.start_xfer_buff = cfi->buf_in.buf; ++ ep->dwc_ep.xfer_buff = cfi->buf_in.buf; ++ ep->dwc_ep.xfer_len = retval; ++ ep->dwc_ep.xfer_count = 0; ++ ep->dwc_ep.sent_zlp = 0; ++ ep->dwc_ep.total_len = ep->dwc_ep.xfer_len; ++ ++ pcd->ep0_pending = 1; ++ dwc_otg_ep0_start_transfer(coreif, &ep->dwc_ep); ++ } ++ retval = 0; ++ break; ++ ++ case VEN_CORE_GET_FEATURE: ++ CFI_INFO("VEN_CORE_GET_FEATURE\n"); ++ retval = cfi_get_feature_value(cfi->buf_in.buf, CFI_IN_BUF_LEN, ++ pcd, ctrl); ++ if (retval >= 0) { ++ ep = &pcd->ep0; ++ ++ retval = min((uint16_t) retval, wLen); ++ /* Transfer this buffer to the host through the EP0-IN EP */ ++ ep->dwc_ep.dma_addr = cfi->buf_in.addr; ++ ep->dwc_ep.start_xfer_buff = cfi->buf_in.buf; ++ ep->dwc_ep.xfer_buff = cfi->buf_in.buf; ++ ep->dwc_ep.xfer_len = retval; ++ ep->dwc_ep.xfer_count = 0; ++ ep->dwc_ep.sent_zlp = 0; ++ ep->dwc_ep.total_len = ep->dwc_ep.xfer_len; ++ ++ pcd->ep0_pending = 1; ++ dwc_otg_ep0_start_transfer(coreif, &ep->dwc_ep); ++ } ++ CFI_INFO("VEN_CORE_GET_FEATURE=%d\n", retval); ++ dump_msg(cfi->buf_in.buf, retval); ++ break; ++ ++ case VEN_CORE_SET_FEATURE: ++ CFI_INFO("VEN_CORE_SET_FEATURE\n"); ++ /* Set up an XFER to get the data stage of the control request, ++ * which is the new value of the feature to be modified. ++ */ ++ ep = &pcd->ep0; ++ ep->dwc_ep.is_in = 0; ++ ep->dwc_ep.dma_addr = cfi->buf_out.addr; ++ ep->dwc_ep.start_xfer_buff = cfi->buf_out.buf; ++ ep->dwc_ep.xfer_buff = cfi->buf_out.buf; ++ ep->dwc_ep.xfer_len = wLen; ++ ep->dwc_ep.xfer_count = 0; ++ ep->dwc_ep.sent_zlp = 0; ++ ep->dwc_ep.total_len = ep->dwc_ep.xfer_len; ++ ++ pcd->ep0_pending = 1; ++ /* Read the control write's data stage */ ++ dwc_otg_ep0_start_transfer(coreif, &ep->dwc_ep); ++ retval = 0; ++ break; ++ ++ case VEN_CORE_RESET_FEATURES: ++ CFI_INFO("VEN_CORE_RESET_FEATURES\n"); ++ cfi->need_gadget_att = 1; ++ cfi->need_status_in_complete = 1; ++ retval = cfi_preproc_reset(pcd, ctrl); ++ CFI_INFO("VEN_CORE_RESET_FEATURES = (%d)\n", retval); ++ break; ++ ++ case VEN_CORE_ACTIVATE_FEATURES: ++ CFI_INFO("VEN_CORE_ACTIVATE_FEATURES\n"); ++ break; ++ ++ case VEN_CORE_READ_REGISTER: ++ CFI_INFO("VEN_CORE_READ_REGISTER\n"); ++ /* wValue optionally contains the HI WORD of the register offset and ++ * wIndex contains the LOW WORD of the register offset ++ */ ++ if (wValue == 0) { ++ /* @TODO - MAS - fix the access to the base field */ ++ regaddr = 0; ++ //regaddr = (uint32_t) pcd->otg_dev->base; ++ //GET_CORE_IF(pcd)->co ++ regaddr |= wIndex; ++ } else { ++ regaddr = (wValue << 16) | wIndex; ++ } ++ ++ /* Read a 32-bit value of the memory at the regaddr */ ++ regval = dwc_read_reg32((uint32_t *) regaddr); ++ ++ ep = &pcd->ep0; ++ dwc_memcpy(cfi->buf_in.buf, ®val, sizeof(uint32_t)); ++ ep->dwc_ep.is_in = 1; ++ ep->dwc_ep.dma_addr = cfi->buf_in.addr; ++ ep->dwc_ep.start_xfer_buff = cfi->buf_in.buf; ++ ep->dwc_ep.xfer_buff = cfi->buf_in.buf; ++ ep->dwc_ep.xfer_len = wLen; ++ ep->dwc_ep.xfer_count = 0; ++ ep->dwc_ep.sent_zlp = 0; ++ ep->dwc_ep.total_len = ep->dwc_ep.xfer_len; ++ ++ pcd->ep0_pending = 1; ++ dwc_otg_ep0_start_transfer(coreif, &ep->dwc_ep); ++ cfi->need_gadget_att = 0; ++ retval = 0; ++ break; ++ ++ case VEN_CORE_WRITE_REGISTER: ++ CFI_INFO("VEN_CORE_WRITE_REGISTER\n"); ++ /* Set up an XFER to get the data stage of the control request, ++ * which is the new value of the register to be modified. ++ */ ++ ep = &pcd->ep0; ++ ep->dwc_ep.is_in = 0; ++ ep->dwc_ep.dma_addr = cfi->buf_out.addr; ++ ep->dwc_ep.start_xfer_buff = cfi->buf_out.buf; ++ ep->dwc_ep.xfer_buff = cfi->buf_out.buf; ++ ep->dwc_ep.xfer_len = wLen; ++ ep->dwc_ep.xfer_count = 0; ++ ep->dwc_ep.sent_zlp = 0; ++ ep->dwc_ep.total_len = ep->dwc_ep.xfer_len; ++ ++ pcd->ep0_pending = 1; ++ /* Read the control write's data stage */ ++ dwc_otg_ep0_start_transfer(coreif, &ep->dwc_ep); ++ retval = 0; ++ break; ++ ++ default: ++ retval = -DWC_E_NOT_SUPPORTED; ++ break; ++ } ++ ++ return retval; ++} ++ ++/** ++ * This function prepares the core features descriptors and copies its ++ * raw representation into the buffer . ++ * ++ * The buffer structure is as follows: ++ * all_features_header (8 bytes) ++ * features_#1 (8 bytes + feature name string length) ++ * features_#2 (8 bytes + feature name string length) ++ * ..... ++ * features_#n - where n=the total count of feature descriptors ++ */ ++static int cfi_core_features_buf(uint8_t * buf, uint16_t buflen) ++{ ++ cfi_feature_desc_header_t *prop_hdr = prop_descs; ++ cfi_feature_desc_header_t *prop; ++ cfi_all_features_header_t *all_props_hdr = &all_props_desc_header; ++ cfi_all_features_header_t *tmp; ++ uint8_t *tmpbuf = buf; ++ const uint8_t *pname = NULL; ++ int i, j, namelen = 0, totlen; ++ ++ /* Prepare and copy the core features into the buffer */ ++ CFI_INFO("%s:\n", __func__); ++ ++ tmp = (cfi_all_features_header_t *) tmpbuf; ++ *tmp = *all_props_hdr; ++ tmpbuf += CFI_ALL_FEATURES_HDR_LEN; ++ ++ j = sizeof(prop_descs) / sizeof(cfi_all_features_header_t); ++ for (i = 0; i < j; i++, prop_hdr++) { ++ pname = get_prop_name(prop_hdr->wFeatureID, &namelen); ++ prop = (cfi_feature_desc_header_t *) tmpbuf; ++ *prop = *prop_hdr; ++ ++ prop->bNameLen = namelen; ++ prop->wLength = ++ DWC_CONSTANT_CPU_TO_LE16(CFI_FEATURE_DESC_HDR_LEN + ++ namelen); ++ ++ tmpbuf += CFI_FEATURE_DESC_HDR_LEN; ++ dwc_memcpy(tmpbuf, pname, namelen); ++ tmpbuf += namelen; ++ } ++ ++ totlen = tmpbuf - buf; ++ ++ if (totlen > 0) { ++ tmp = (cfi_all_features_header_t *) buf; ++ tmp->wTotalLen = DWC_CONSTANT_CPU_TO_LE16(totlen); ++ } ++ ++ return totlen; ++} ++ ++/** ++ * This function releases all the dynamic memory in the CFI object. ++ */ ++static void cfi_release(cfiobject_t * cfiobj) ++{ ++ cfi_ep_t *cfiep; ++ dwc_list_link_t *tmp; ++ ++ CFI_INFO("%s\n", __func__); ++ ++ if (cfiobj->buf_in.buf) { ++ dwc_dma_free(CFI_IN_BUF_LEN, cfiobj->buf_in.buf, ++ cfiobj->buf_in.addr); ++ cfiobj->buf_in.buf = NULL; ++ } ++ ++ if (cfiobj->buf_out.buf) { ++ dwc_dma_free(CFI_OUT_BUF_LEN, cfiobj->buf_out.buf, ++ cfiobj->buf_out.addr); ++ cfiobj->buf_out.buf = NULL; ++ } ++ ++ /* Free the Buffer Setup values for each EP */ ++ //list_for_each_entry(cfiep, &cfiobj->active_eps, lh) { ++ DWC_LIST_FOREACH(tmp, &cfiobj->active_eps) { ++ cfiep = DWC_LIST_ENTRY(tmp, struct cfi_ep, lh); ++ cfi_free_ep_bs_dyn_data(cfiep); ++ } ++} ++ ++/** ++ * This function frees the dynamically allocated EP buffer setup data. ++ */ ++static void cfi_free_ep_bs_dyn_data(cfi_ep_t * cfiep) ++{ ++ if (cfiep->bm_sg) { ++ dwc_free(cfiep->bm_sg); ++ cfiep->bm_sg = NULL; ++ } ++ ++ if (cfiep->bm_align) { ++ dwc_free(cfiep->bm_align); ++ cfiep->bm_align = NULL; ++ } ++ ++ if (cfiep->bm_concat) { ++ if (NULL != cfiep->bm_concat->wTxBytes) { ++ dwc_free(cfiep->bm_concat->wTxBytes); ++ cfiep->bm_concat->wTxBytes = NULL; ++ } ++ dwc_free(cfiep->bm_concat); ++ cfiep->bm_concat = NULL; ++ } ++} ++ ++/** ++ * This function initializes the default values of the features ++ * for a specific endpoint and should be called only once when ++ * the EP is enabled first time. ++ */ ++static int cfi_ep_init_defaults(struct dwc_otg_pcd *pcd, cfi_ep_t * cfiep) ++{ ++ int retval = 0; ++ ++ cfiep->bm_sg = dwc_alloc(sizeof(ddma_sg_buffer_setup_t)); ++ if (NULL == cfiep->bm_sg) { ++ CFI_INFO("Failed to allocate memory for SG feature value\n"); ++ return -DWC_E_NO_MEMORY; ++ } ++ dwc_memset(cfiep->bm_sg, 0, sizeof(ddma_sg_buffer_setup_t)); ++ ++ /* For the Concatenation feature's default value we do not allocate ++ * memory for the wTxBytes field - it will be done in the set_feature_value ++ * request handler. ++ */ ++ cfiep->bm_concat = dwc_alloc(sizeof(ddma_concat_buffer_setup_t)); ++ if (NULL == cfiep->bm_concat) { ++ CFI_INFO ++ ("Failed to allocate memory for CONCATENATION feature value\n"); ++ dwc_free(cfiep->bm_sg); ++ return -DWC_E_NO_MEMORY; ++ } ++ dwc_memset(cfiep->bm_concat, 0, sizeof(ddma_concat_buffer_setup_t)); ++ ++ cfiep->bm_align = dwc_alloc(sizeof(ddma_align_buffer_setup_t)); ++ if (NULL == cfiep->bm_align) { ++ CFI_INFO ++ ("Failed to allocate memory for Alignment feature value\n"); ++ dwc_free(cfiep->bm_sg); ++ dwc_free(cfiep->bm_concat); ++ return -DWC_E_NO_MEMORY; ++ } ++ dwc_memset(cfiep->bm_align, 0, sizeof(ddma_align_buffer_setup_t)); ++ ++ return retval; ++} ++ ++/** ++ * The callback function that notifies the CFI on the activation of ++ * an endpoint in the PCD. The following steps are done in this function: ++ * ++ * Create a dynamically allocated cfi_ep_t object (a CFI wrapper to the PCD's ++ * active endpoint) ++ * Create MAX_DMA_DESCS_PER_EP count DMA Descriptors for the EP ++ * Set the Buffer Mode to standard ++ * Initialize the default values for all EP modes (SG, Circular, Concat, Align) ++ * Add the cfi_ep_t object to the list of active endpoints in the CFI object ++ */ ++static int cfi_ep_enable(struct cfiobject *cfi, struct dwc_otg_pcd *pcd, ++ struct dwc_otg_pcd_ep *ep) ++{ ++ cfi_ep_t *cfiep; ++ int retval = -DWC_E_NOT_SUPPORTED; ++ ++ CFI_INFO("%s: epname=%s; epnum=0x%02x\n", __func__, ++ "EP_" /*ep->ep.name */ , ep->desc->bEndpointAddress); ++ /* MAS - Check whether this endpoint already is in the list */ ++ cfiep = get_cfi_ep_by_pcd_ep(cfi, ep); ++ ++ if (NULL == cfiep) { ++ /* Allocate a cfi_ep_t object */ ++ cfiep = dwc_alloc(sizeof(cfi_ep_t)); ++ if (NULL == cfiep) { ++ CFI_INFO ++ ("Unable to allocate memory for in function %s\n", ++ __func__); ++ return -DWC_E_NO_MEMORY; ++ } ++ dwc_memset(cfiep, 0, sizeof(cfi_ep_t)); ++ ++ /* Save the dwc_otg_pcd_ep pointer in the cfiep object */ ++ cfiep->ep = ep; ++ ++ /* Allocate the DMA Descriptors chain of MAX_DMA_DESCS_PER_EP count */ ++ ep->dwc_ep.descs = ++ dwc_dma_alloc(MAX_DMA_DESCS_PER_EP * ++ sizeof(dwc_otg_dma_desc_t), ++ &ep->dwc_ep.descs_dma_addr); ++ ++ if (NULL == ep->dwc_ep.descs) { ++ dwc_free(cfiep); ++ return -DWC_E_NO_MEMORY; ++ } ++ ++ DWC_LIST_INIT(&cfiep->lh); ++ ++ /* Set the buffer mode to BM_STANDARD. It will be modified ++ * when building descriptors for a specific buffer mode */ ++ ep->dwc_ep.buff_mode = BM_STANDARD; ++ ++ /* Create and initialize the default values for this EP's Buffer modes */ ++ if ((retval = cfi_ep_init_defaults(pcd, cfiep)) < 0) ++ return retval; ++ ++ /* Add the cfi_ep_t object to the CFI object's list of active endpoints */ ++ DWC_LIST_INSERT_TAIL(&cfi->active_eps, &cfiep->lh); ++ retval = 0; ++ } else { /* The sought EP already is in the list */ ++ CFI_INFO("%s: The sought EP already is in the list\n", ++ __func__); ++ } ++ ++ return retval; ++} ++ ++/** ++ * This function is called when the data stage of a 3-stage Control Write request ++ * is complete. ++ * ++ */ ++static int cfi_ctrl_write_complete(struct cfiobject *cfi, ++ struct dwc_otg_pcd *pcd) ++{ ++ uint32_t addr, reg_value; ++ uint16_t wIndex, wValue; ++ uint8_t bRequest; ++ uint8_t *buf = cfi->buf_out.buf; ++ //struct usb_ctrlrequest *ctrl_req = &cfi->ctrl_req_saved; ++ struct cfi_usb_ctrlrequest *ctrl_req = &cfi->ctrl_req; ++ int retval = -DWC_E_NOT_SUPPORTED; ++ ++ CFI_INFO("%s\n", __func__); ++ ++ bRequest = ctrl_req->bRequest; ++ wIndex = DWC_CONSTANT_CPU_TO_LE16(ctrl_req->wIndex); ++ wValue = DWC_CONSTANT_CPU_TO_LE16(ctrl_req->wValue); ++ ++ /* ++ * Save the pointer to the data stage in the ctrl_req's field. ++ * The request should be already saved in the command stage by now. ++ */ ++ ctrl_req->data = cfi->buf_out.buf; ++ cfi->need_status_in_complete = 0; ++ cfi->need_gadget_att = 0; ++ ++ switch (bRequest) { ++ case VEN_CORE_WRITE_REGISTER: ++ /* The buffer contains raw data of the new value for the register */ ++ reg_value = *((uint32_t *) buf); ++ if (wValue == 0) { ++ addr = 0; ++ //addr = (uint32_t) pcd->otg_dev->base; ++ addr += wIndex; ++ } else { ++ addr = (wValue << 16) | wIndex; ++ } ++ ++ //writel(reg_value, addr); ++ ++ retval = 0; ++ cfi->need_status_in_complete = 1; ++ break; ++ ++ case VEN_CORE_SET_FEATURE: ++ /* The buffer contains raw data of the new value of the feature */ ++ retval = cfi_set_feature_value(pcd); ++ if (retval < 0) ++ return retval; ++ ++ cfi->need_status_in_complete = 1; ++ break; ++ ++ default: ++ break; ++ } ++ ++ return retval; ++} ++ ++/** ++ * This function builds the DMA descriptors for the SG buffer mode. ++ */ ++static void cfi_build_sg_descs(struct cfiobject *cfi, cfi_ep_t * cfiep, ++ dwc_otg_pcd_request_t * req) ++{ ++ struct dwc_otg_pcd_ep *ep = cfiep->ep; ++ ddma_sg_buffer_setup_t *sgval = cfiep->bm_sg; ++ struct dwc_otg_dma_desc *desc = cfiep->ep->dwc_ep.descs; ++ struct dwc_otg_dma_desc *desc_last = cfiep->ep->dwc_ep.descs; ++ dma_addr_t buff_addr = req->dma; ++ int i; ++ uint32_t txsize, off; ++ ++ txsize = sgval->wSize; ++ off = sgval->bOffset; ++ ++// CFI_INFO("%s: %s TXSIZE=0x%08x; OFFSET=0x%08x\n", ++// __func__, cfiep->ep->ep.name, txsize, off); ++ ++ for (i = 0; i < sgval->bCount; i++) { ++ desc->status.b.bs = BS_HOST_BUSY; ++ desc->buf = buff_addr; ++ desc->status.b.l = 0; ++ desc->status.b.ioc = 0; ++ desc->status.b.sp = 0; ++ desc->status.b.bytes = txsize; ++ desc->status.b.bs = BS_HOST_READY; ++ ++ /* Set the next address of the buffer */ ++ buff_addr += txsize + off; ++ desc_last = desc; ++ desc++; ++ } ++ ++ /* Set the last, ioc and sp bits on the Last DMA Descriptor */ ++ desc_last->status.b.l = 1; ++ desc_last->status.b.ioc = 1; ++ desc_last->status.b.sp = ep->dwc_ep.sent_zlp; ++ /* Save the last DMA descriptor pointer */ ++ cfiep->dma_desc_last = desc_last; ++ cfiep->desc_count = sgval->bCount; ++} ++ ++/** ++ * This function builds the DMA descriptors for the Concatenation buffer mode. ++ */ ++static void cfi_build_concat_descs(struct cfiobject *cfi, cfi_ep_t * cfiep, ++ dwc_otg_pcd_request_t * req) ++{ ++ struct dwc_otg_pcd_ep *ep = cfiep->ep; ++ ddma_concat_buffer_setup_t *concatval = cfiep->bm_concat; ++ struct dwc_otg_dma_desc *desc = cfiep->ep->dwc_ep.descs; ++ struct dwc_otg_dma_desc *desc_last = cfiep->ep->dwc_ep.descs; ++ dma_addr_t buff_addr = req->dma; ++ int i; ++ uint16_t *txsize; ++ ++ txsize = concatval->wTxBytes; ++ ++ for (i = 0; i < concatval->hdr.bDescCount; i++) { ++ desc->buf = buff_addr; ++ desc->status.b.bs = BS_HOST_BUSY; ++ desc->status.b.l = 0; ++ desc->status.b.ioc = 0; ++ desc->status.b.sp = 0; ++ desc->status.b.bytes = *txsize; ++ desc->status.b.bs = BS_HOST_READY; ++ ++ txsize++; ++ /* Set the next address of the buffer */ ++ buff_addr += UGETW(ep->desc->wMaxPacketSize); ++ desc_last = desc; ++ desc++; ++ } ++ ++ /* Set the last, ioc and sp bits on the Last DMA Descriptor */ ++ desc_last->status.b.l = 1; ++ desc_last->status.b.ioc = 1; ++ desc_last->status.b.sp = ep->dwc_ep.sent_zlp; ++ cfiep->dma_desc_last = desc_last; ++ cfiep->desc_count = concatval->hdr.bDescCount; ++} ++ ++/** ++ * This function builds the DMA descriptors for the Circular buffer mode ++ */ ++static void cfi_build_circ_descs(struct cfiobject *cfi, cfi_ep_t * cfiep, ++ dwc_otg_pcd_request_t * req) ++{ ++ /* @todo: MAS - add implementation when this feature needs to be tested */ ++} ++ ++/** ++ * This function builds the DMA descriptors for the Alignment buffer mode ++ */ ++static void cfi_build_align_descs(struct cfiobject *cfi, cfi_ep_t * cfiep, ++ dwc_otg_pcd_request_t * req) ++{ ++ struct dwc_otg_pcd_ep *ep = cfiep->ep; ++ ddma_align_buffer_setup_t *alignval = cfiep->bm_align; ++ struct dwc_otg_dma_desc *desc = cfiep->ep->dwc_ep.descs; ++ dma_addr_t buff_addr = req->dma; ++ ++ desc->status.b.bs = BS_HOST_BUSY; ++ desc->status.b.l = 1; ++ desc->status.b.ioc = 1; ++ desc->status.b.sp = ep->dwc_ep.sent_zlp; ++ desc->status.b.bytes = req->length; ++ /* Adjust the buffer alignment */ ++ desc->buf = (buff_addr + alignval->bAlign); ++ desc->status.b.bs = BS_HOST_READY; ++ cfiep->dma_desc_last = desc; ++ cfiep->desc_count = 1; ++} ++ ++/** ++ * This function builds the DMA descriptors chain for different modes of the ++ * buffer setup of an endpoint. ++ */ ++static void cfi_build_descriptors(struct cfiobject *cfi, ++ struct dwc_otg_pcd *pcd, ++ struct dwc_otg_pcd_ep *ep, ++ dwc_otg_pcd_request_t * req) ++{ ++ cfi_ep_t *cfiep; ++ ++ /* Get the cfiep by the dwc_otg_pcd_ep */ ++ cfiep = get_cfi_ep_by_pcd_ep(cfi, ep); ++ if (NULL == cfiep) { ++ CFI_INFO("%s: Unable to find a matching active endpoint\n", ++ __func__); ++ return; ++ } ++ ++ cfiep->xfer_len = req->length; ++ ++ /* Iterate through all the DMA descriptors */ ++ switch (cfiep->ep->dwc_ep.buff_mode) { ++ case BM_SG: ++ cfi_build_sg_descs(cfi, cfiep, req); ++ break; ++ ++ case BM_CONCAT: ++ cfi_build_concat_descs(cfi, cfiep, req); ++ break; ++ ++ case BM_CIRCULAR: ++ cfi_build_circ_descs(cfi, cfiep, req); ++ break; ++ ++ case BM_ALIGN: ++ cfi_build_align_descs(cfi, cfiep, req); ++ break; ++ ++ default: ++ break; ++ } ++} ++ ++/** ++ * Allocate DMA buffer for different Buffer modes. ++ */ ++static void *cfi_ep_alloc_buf(struct cfiobject *cfi, struct dwc_otg_pcd *pcd, ++ struct dwc_otg_pcd_ep *ep, dma_addr_t * dma, ++ unsigned size, gfp_t flags) ++{ ++ return dwc_dma_alloc(size, dma); ++} ++ ++/** ++ * This function initializes the CFI object. ++ */ ++int init_cfi(cfiobject_t * cfiobj) ++{ ++ CFI_INFO("%s\n", __func__); ++ ++ /* Allocate a buffer for IN XFERs */ ++ cfiobj->buf_in.buf = ++ dwc_dma_alloc(CFI_IN_BUF_LEN, &cfiobj->buf_in.addr); ++ if (NULL == cfiobj->buf_in.buf) { ++ CFI_INFO("Unable to allocate buffer for INs\n"); ++ return -DWC_E_NO_MEMORY; ++ } ++ ++ /* Allocate a buffer for OUT XFERs */ ++ cfiobj->buf_out.buf = ++ dwc_dma_alloc(CFI_OUT_BUF_LEN, &cfiobj->buf_out.addr); ++ if (NULL == cfiobj->buf_out.buf) { ++ CFI_INFO("Unable to allocate buffer for OUT\n"); ++ return -DWC_E_NO_MEMORY; ++ } ++ ++ /* Initialize the callback function pointers */ ++ cfiobj->ops.release = cfi_release; ++ cfiobj->ops.ep_enable = cfi_ep_enable; ++ cfiobj->ops.ctrl_write_complete = cfi_ctrl_write_complete; ++ cfiobj->ops.build_descriptors = cfi_build_descriptors; ++ cfiobj->ops.ep_alloc_buf = cfi_ep_alloc_buf; ++ ++ /* Initialize the list of active endpoints in the CFI object */ ++ DWC_LIST_INIT(&cfiobj->active_eps); ++ ++ return 0; ++} ++ ++/** ++ * This function reads the required feature's current value into the buffer ++ * ++ * @retval: Returns negative as error, or the data length of the feature ++ */ ++static int cfi_get_feature_value(uint8_t * buf, uint16_t buflen, ++ struct dwc_otg_pcd *pcd, ++ struct cfi_usb_ctrlrequest *ctrl_req) ++{ ++ int retval = -DWC_E_NOT_SUPPORTED; ++ struct dwc_otg_core_if *coreif = GET_CORE_IF(pcd); ++ uint16_t dfifo, rxfifo, txfifo; ++ ++ switch (ctrl_req->wIndex) { ++ /* Whether the DDMA is enabled or not */ ++ case FT_ID_DMA_MODE: ++ *buf = (coreif->dma_enable && coreif->dma_desc_enable) ? 1 : 0; ++ retval = 1; ++ break; ++ ++ case FT_ID_DMA_BUFFER_SETUP: ++ retval = cfi_ep_get_sg_val(buf, pcd, ctrl_req); ++ break; ++ ++ case FT_ID_DMA_BUFF_ALIGN: ++ retval = cfi_ep_get_align_val(buf, pcd, ctrl_req); ++ break; ++ ++ case FT_ID_DMA_CONCAT_SETUP: ++ retval = cfi_ep_get_concat_val(buf, pcd, ctrl_req); ++ break; ++ ++ case FT_ID_DMA_CIRCULAR: ++ CFI_INFO("GetFeature value (FT_ID_DMA_CIRCULAR)\n"); ++ break; ++ ++ case FT_ID_THRESHOLD_SETUP: ++ CFI_INFO("GetFeature value (FT_ID_THRESHOLD_SETUP)\n"); ++ break; ++ ++ case FT_ID_DFIFO_DEPTH: ++ dfifo = get_dfifo_size(coreif); ++ *((uint16_t *) buf) = dfifo; ++ retval = sizeof(uint16_t); ++ break; ++ ++ case FT_ID_TX_FIFO_DEPTH: ++ retval = get_txfifo_size(pcd, ctrl_req->wValue); ++ if (retval >= 0) { ++ txfifo = retval; ++ *((uint16_t *) buf) = txfifo; ++ retval = sizeof(uint16_t); ++ } ++ break; ++ ++ case FT_ID_RX_FIFO_DEPTH: ++ retval = get_rxfifo_size(coreif, ctrl_req->wValue); ++ if (retval >= 0) { ++ rxfifo = retval; ++ *((uint16_t *) buf) = rxfifo; ++ retval = sizeof(uint16_t); ++ } ++ break; ++ } ++ ++ return retval; ++} ++ ++/** ++ * This function resets the SG for the specified EP to its default value ++ */ ++static int cfi_reset_sg_val(cfi_ep_t * cfiep) ++{ ++ dwc_memset(cfiep->bm_sg, 0, sizeof(ddma_sg_buffer_setup_t)); ++ return 0; ++} ++ ++/** ++ * This function resets the Alignment for the specified EP to its default value ++ */ ++static int cfi_reset_align_val(cfi_ep_t * cfiep) ++{ ++ dwc_memset(cfiep->bm_sg, 0, sizeof(ddma_sg_buffer_setup_t)); ++ return 0; ++} ++ ++/** ++ * This function resets the Concatenation for the specified EP to its default value ++ * This function will also set the value of the wTxBytes field to NULL after ++ * freeing the memory previously allocated for this field. ++ */ ++static int cfi_reset_concat_val(cfi_ep_t * cfiep) ++{ ++ /* First we need to free the wTxBytes field */ ++ if (cfiep->bm_concat->wTxBytes) { ++ dwc_free(cfiep->bm_concat->wTxBytes); ++ cfiep->bm_concat->wTxBytes = NULL; ++ } ++ ++ dwc_memset(cfiep->bm_concat, 0, sizeof(ddma_concat_buffer_setup_t)); ++ return 0; ++} ++ ++/** ++ * This function resets all the buffer setups of the specified endpoint ++ */ ++static int cfi_ep_reset_all_setup_vals(cfi_ep_t * cfiep) ++{ ++ cfi_reset_sg_val(cfiep); ++ cfi_reset_align_val(cfiep); ++ cfi_reset_concat_val(cfiep); ++ return 0; ++} ++ ++static int cfi_handle_reset_fifo_val(struct dwc_otg_pcd *pcd, uint8_t ep_addr, ++ uint8_t rx_rst, uint8_t tx_rst) ++{ ++ int retval = -DWC_E_INVALID; ++ uint16_t tx_siz[15]; ++ uint16_t rx_siz = 0; ++ dwc_otg_pcd_ep_t *ep = NULL; ++ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); ++ dwc_otg_core_params_t *params = GET_CORE_IF(pcd)->core_params; ++ ++ if (rx_rst) { ++ rx_siz = params->dev_rx_fifo_size; ++ params->dev_rx_fifo_size = GET_CORE_IF(pcd)->init_rxfsiz; ++ } ++ ++ if (tx_rst) { ++ if (ep_addr == 0) { ++ int i; ++ ++ for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) { ++ tx_siz[i] = ++ core_if->core_params->dev_tx_fifo_size[i]; ++ core_if->core_params->dev_tx_fifo_size[i] = ++ core_if->init_txfsiz[i]; ++ } ++ } else { ++ ++ ep = get_ep_by_addr(pcd, ep_addr); ++ ++ if (NULL == ep) { ++ CFI_INFO ++ ("%s: Unable to get the endpoint addr=0x%02x\n", ++ __func__, ep_addr); ++ return -DWC_E_INVALID; ++ } ++ ++ tx_siz[0] = ++ params->dev_tx_fifo_size[ep->dwc_ep.tx_fifo_num - ++ 1]; ++ params->dev_tx_fifo_size[ep->dwc_ep.tx_fifo_num - 1] = ++ GET_CORE_IF(pcd)->init_txfsiz[ep->dwc_ep. ++ tx_fifo_num - 1]; ++ } ++ } ++ ++ if (resize_fifos(GET_CORE_IF(pcd))) { ++ retval = 0; ++ } else { ++ CFI_INFO ++ ("%s: Error resetting the feature Reset All(FIFO size)\n", ++ __func__); ++ if (rx_rst) { ++ params->dev_rx_fifo_size = rx_siz; ++ } ++ ++ if (tx_rst) { ++ if (ep_addr == 0) { ++ int i; ++ for (i = 0; i < core_if->hwcfg4.b.num_in_eps; ++ i++) { ++ core_if->core_params-> ++ dev_tx_fifo_size[i] = tx_siz[i]; ++ } ++ } else { ++ params->dev_tx_fifo_size[ep->dwc_ep. ++ tx_fifo_num - 1] = ++ tx_siz[0]; ++ } ++ } ++ retval = -DWC_E_INVALID; ++ } ++ return retval; ++} ++ ++static int cfi_handle_reset_all(struct dwc_otg_pcd *pcd, uint8_t addr) ++{ ++ int retval = 0; ++ cfi_ep_t *cfiep; ++ cfiobject_t *cfi = pcd->cfi; ++ dwc_list_link_t *tmp; ++ ++ retval = cfi_handle_reset_fifo_val(pcd, addr, 1, 1); ++ if (retval < 0) { ++ return retval; ++ } ++ ++ /* If the EP address is known then reset the features for only that EP */ ++ if (addr) { ++ cfiep = get_cfi_ep_by_addr(pcd->cfi, addr); ++ if (NULL == cfiep) { ++ CFI_INFO("%s: Error getting the EP address 0x%02x\n", ++ __func__, addr); ++ return -DWC_E_INVALID; ++ } ++ retval = cfi_ep_reset_all_setup_vals(cfiep); ++ cfiep->ep->dwc_ep.buff_mode = BM_STANDARD; ++ } ++ /* Otherwise (wValue == 0), reset all features of all EP's */ ++ else { ++ /* Traverse all the active EP's and reset the feature(s) value(s) */ ++ //list_for_each_entry(cfiep, &cfi->active_eps, lh) { ++ DWC_LIST_FOREACH(tmp, &cfi->active_eps) { ++ cfiep = DWC_LIST_ENTRY(tmp, struct cfi_ep, lh); ++ retval = cfi_ep_reset_all_setup_vals(cfiep); ++ cfiep->ep->dwc_ep.buff_mode = BM_STANDARD; ++ if (retval < 0) { ++ CFI_INFO ++ ("%s: Error resetting the feature Reset All\n", ++ __func__); ++ return retval; ++ } ++ } ++ } ++ return retval; ++} ++ ++static int cfi_handle_reset_dma_buff_setup(struct dwc_otg_pcd *pcd, ++ uint8_t addr) ++{ ++ int retval = 0; ++ cfi_ep_t *cfiep; ++ cfiobject_t *cfi = pcd->cfi; ++ dwc_list_link_t *tmp; ++ ++ /* If the EP address is known then reset the features for only that EP */ ++ if (addr) { ++ cfiep = get_cfi_ep_by_addr(pcd->cfi, addr); ++ if (NULL == cfiep) { ++ CFI_INFO("%s: Error getting the EP address 0x%02x\n", ++ __func__, addr); ++ return -DWC_E_INVALID; ++ } ++ retval = cfi_reset_sg_val(cfiep); ++ } ++ /* Otherwise (wValue == 0), reset all features of all EP's */ ++ else { ++ /* Traverse all the active EP's and reset the feature(s) value(s) */ ++ //list_for_each_entry(cfiep, &cfi->active_eps, lh) { ++ DWC_LIST_FOREACH(tmp, &cfi->active_eps) { ++ cfiep = DWC_LIST_ENTRY(tmp, struct cfi_ep, lh); ++ retval = cfi_reset_sg_val(cfiep); ++ if (retval < 0) { ++ CFI_INFO ++ ("%s: Error resetting the feature Buffer Setup\n", ++ __func__); ++ return retval; ++ } ++ } ++ } ++ return retval; ++} ++ ++static int cfi_handle_reset_concat_val(struct dwc_otg_pcd *pcd, uint8_t addr) ++{ ++ int retval = 0; ++ cfi_ep_t *cfiep; ++ cfiobject_t *cfi = pcd->cfi; ++ dwc_list_link_t *tmp; ++ ++ /* If the EP address is known then reset the features for only that EP */ ++ if (addr) { ++ cfiep = get_cfi_ep_by_addr(pcd->cfi, addr); ++ if (NULL == cfiep) { ++ CFI_INFO("%s: Error getting the EP address 0x%02x\n", ++ __func__, addr); ++ return -DWC_E_INVALID; ++ } ++ retval = cfi_reset_concat_val(cfiep); ++ } ++ /* Otherwise (wValue == 0), reset all features of all EP's */ ++ else { ++ /* Traverse all the active EP's and reset the feature(s) value(s) */ ++ //list_for_each_entry(cfiep, &cfi->active_eps, lh) { ++ DWC_LIST_FOREACH(tmp, &cfi->active_eps) { ++ cfiep = DWC_LIST_ENTRY(tmp, struct cfi_ep, lh); ++ retval = cfi_reset_concat_val(cfiep); ++ if (retval < 0) { ++ CFI_INFO ++ ("%s: Error resetting the feature Concatenation Value\n", ++ __func__); ++ return retval; ++ } ++ } ++ } ++ return retval; ++} ++ ++static int cfi_handle_reset_align_val(struct dwc_otg_pcd *pcd, uint8_t addr) ++{ ++ int retval = 0; ++ cfi_ep_t *cfiep; ++ cfiobject_t *cfi = pcd->cfi; ++ dwc_list_link_t *tmp; ++ ++ /* If the EP address is known then reset the features for only that EP */ ++ if (addr) { ++ cfiep = get_cfi_ep_by_addr(pcd->cfi, addr); ++ if (NULL == cfiep) { ++ CFI_INFO("%s: Error getting the EP address 0x%02x\n", ++ __func__, addr); ++ return -DWC_E_INVALID; ++ } ++ retval = cfi_reset_align_val(cfiep); ++ } ++ /* Otherwise (wValue == 0), reset all features of all EP's */ ++ else { ++ /* Traverse all the active EP's and reset the feature(s) value(s) */ ++ //list_for_each_entry(cfiep, &cfi->active_eps, lh) { ++ DWC_LIST_FOREACH(tmp, &cfi->active_eps) { ++ cfiep = DWC_LIST_ENTRY(tmp, struct cfi_ep, lh); ++ retval = cfi_reset_align_val(cfiep); ++ if (retval < 0) { ++ CFI_INFO ++ ("%s: Error resetting the feature Aliignment Value\n", ++ __func__); ++ return retval; ++ } ++ } ++ } ++ return retval; ++ ++} ++ ++static int cfi_preproc_reset(struct dwc_otg_pcd *pcd, ++ struct cfi_usb_ctrlrequest *req) ++{ ++ int retval = 0; ++ ++ switch (req->wIndex) { ++ case 0: ++ /* Reset all features */ ++ retval = cfi_handle_reset_all(pcd, req->wValue & 0xff); ++ break; ++ ++ case FT_ID_DMA_BUFFER_SETUP: ++ /* Reset the SG buffer setup */ ++ retval = ++ cfi_handle_reset_dma_buff_setup(pcd, req->wValue & 0xff); ++ break; ++ ++ case FT_ID_DMA_CONCAT_SETUP: ++ /* Reset the Concatenation buffer setup */ ++ retval = cfi_handle_reset_concat_val(pcd, req->wValue & 0xff); ++ break; ++ ++ case FT_ID_DMA_BUFF_ALIGN: ++ /* Reset the Alignment buffer setup */ ++ retval = cfi_handle_reset_align_val(pcd, req->wValue & 0xff); ++ break; ++ ++ case FT_ID_TX_FIFO_DEPTH: ++ retval = ++ cfi_handle_reset_fifo_val(pcd, req->wValue & 0xff, 0, 1); ++ pcd->cfi->need_gadget_att = 0; ++ break; ++ ++ case FT_ID_RX_FIFO_DEPTH: ++ retval = cfi_handle_reset_fifo_val(pcd, 0, 1, 0); ++ pcd->cfi->need_gadget_att = 0; ++ break; ++ default: ++ break; ++ } ++ return retval; ++} ++ ++/** ++ * This function sets a new value for the SG buffer setup. ++ */ ++static int cfi_ep_set_sg_val(uint8_t * buf, struct dwc_otg_pcd *pcd) ++{ ++ uint8_t inaddr, outaddr; ++ cfi_ep_t *epin, *epout; ++ ddma_sg_buffer_setup_t *psgval; ++ uint32_t desccount, size; ++ ++ CFI_INFO("%s\n", __func__); ++ ++ psgval = (ddma_sg_buffer_setup_t *) buf; ++ desccount = (uint32_t) psgval->bCount; ++ size = (uint32_t) psgval->wSize; ++ ++ /* Check the DMA descriptor count */ ++ if ((desccount > MAX_DMA_DESCS_PER_EP) || (desccount == 0)) { ++ CFI_INFO ++ ("%s: The count of DMA Descriptors should be between 1 and %d\n", ++ __func__, MAX_DMA_DESCS_PER_EP); ++ return -DWC_E_INVALID; ++ } ++ ++ /* Check the DMA descriptor count */ ++ ++ if (size == 0) { ++ ++ CFI_INFO("%s: The transfer size should be at least 1 byte\n", ++ __func__); ++ ++ return -DWC_E_INVALID; ++ ++ } ++ ++ inaddr = psgval->bInEndpointAddress; ++ outaddr = psgval->bOutEndpointAddress; ++ ++ epin = get_cfi_ep_by_addr(pcd->cfi, inaddr); ++ epout = get_cfi_ep_by_addr(pcd->cfi, outaddr); ++ ++ if (NULL == epin || NULL == epout) { ++ CFI_INFO ++ ("%s: Unable to get the endpoints inaddr=0x%02x outaddr=0x%02x\n", ++ __func__, inaddr, outaddr); ++ return -DWC_E_INVALID; ++ } ++ ++ epin->ep->dwc_ep.buff_mode = BM_SG; ++ dwc_memcpy(epin->bm_sg, psgval, sizeof(ddma_sg_buffer_setup_t)); ++ ++ epout->ep->dwc_ep.buff_mode = BM_SG; ++ dwc_memcpy(epout->bm_sg, psgval, sizeof(ddma_sg_buffer_setup_t)); ++ ++ return 0; ++} ++ ++/** ++ * This function sets a new value for the buffer Alignment setup. ++ */ ++static int cfi_ep_set_alignment_val(uint8_t * buf, struct dwc_otg_pcd *pcd) ++{ ++ cfi_ep_t *ep; ++ uint8_t addr; ++ ddma_align_buffer_setup_t *palignval; ++ ++ palignval = (ddma_align_buffer_setup_t *) buf; ++ addr = palignval->bEndpointAddress; ++ ++ ep = get_cfi_ep_by_addr(pcd->cfi, addr); ++ ++ if (NULL == ep) { ++ CFI_INFO("%s: Unable to get the endpoint addr=0x%02x\n", ++ __func__, addr); ++ return -DWC_E_INVALID; ++ } ++ ++ ep->ep->dwc_ep.buff_mode = BM_ALIGN; ++ dwc_memcpy(ep->bm_align, palignval, sizeof(ddma_align_buffer_setup_t)); ++ ++ return 0; ++} ++ ++/** ++ * This function sets a new value for the Concatenation buffer setup. ++ */ ++static int cfi_ep_set_concat_val(uint8_t * buf, struct dwc_otg_pcd *pcd) ++{ ++ uint8_t addr; ++ cfi_ep_t *ep; ++ struct _ddma_concat_buffer_setup_hdr *pConcatValHdr; ++ uint16_t *pVals; ++ uint32_t desccount; ++ int i; ++ uint16_t mps; ++ ++ pConcatValHdr = (struct _ddma_concat_buffer_setup_hdr *)buf; ++ desccount = (uint32_t) pConcatValHdr->bDescCount; ++ pVals = (uint16_t *) (buf + BS_CONCAT_VAL_HDR_LEN); ++ ++ /* Check the DMA descriptor count */ ++ if (desccount > MAX_DMA_DESCS_PER_EP) { ++ CFI_INFO("%s: Maximum DMA Descriptor count should be %d\n", ++ __func__, MAX_DMA_DESCS_PER_EP); ++ return -DWC_E_INVALID; ++ } ++ ++ addr = pConcatValHdr->bEndpointAddress; ++ ep = get_cfi_ep_by_addr(pcd->cfi, addr); ++ if (NULL == ep) { ++ CFI_INFO("%s: Unable to get the endpoint addr=0x%02x\n", ++ __func__, addr); ++ return -DWC_E_INVALID; ++ } ++ ++ mps = UGETW(ep->ep->desc->wMaxPacketSize); ++ ++#if 0 ++ for (i = 0; i < desccount; i++) { ++ CFI_INFO("%s: wTxSize[%d]=0x%04x\n", __func__, i, pVals[i]); ++ } ++ CFI_INFO("%s: epname=%s; mps=%d\n", __func__, ep->ep->ep.name, mps); ++#endif ++ ++ /* Check the wTxSizes to be less than or equal to the mps */ ++ for (i = 0; i < desccount; i++) { ++ if (pVals[i] > mps) { ++ CFI_INFO ++ ("%s: ERROR - the wTxSize[%d] should be <= MPS (wTxSize=%d)\n", ++ __func__, i, pVals[i]); ++ return -DWC_E_INVALID; ++ } ++ } ++ ++ ep->ep->dwc_ep.buff_mode = BM_CONCAT; ++ dwc_memcpy(ep->bm_concat, pConcatValHdr, BS_CONCAT_VAL_HDR_LEN); ++ ++ /* Free the previously allocated storage for the wTxBytes */ ++ if (ep->bm_concat->wTxBytes) { ++ dwc_free(ep->bm_concat->wTxBytes); ++ } ++ ++ /* Allocate a new storage for the wTxBytes field */ ++ ep->bm_concat->wTxBytes = ++ dwc_alloc(sizeof(uint16_t) * pConcatValHdr->bDescCount); ++ if (NULL == ep->bm_concat->wTxBytes) { ++ CFI_INFO("%s: Unable to allocate memory\n", __func__); ++ return -DWC_E_NO_MEMORY; ++ } ++ ++ /* Copy the new values into the wTxBytes filed */ ++ dwc_memcpy(ep->bm_concat->wTxBytes, buf + BS_CONCAT_VAL_HDR_LEN, ++ sizeof(uint16_t) * pConcatValHdr->bDescCount); ++ ++ return 0; ++} ++ ++/** ++ * This function calculates the total of all FIFO sizes ++ * ++ * @param core_if Programming view of DWC_otg controller ++ * ++ * @return The total of data FIFO sizes. ++ * ++ */ ++static uint16_t get_dfifo_size(dwc_otg_core_if_t * core_if) ++{ ++ dwc_otg_core_params_t *params = core_if->core_params; ++ uint16_t dfifo_total = 0; ++ int i; ++ ++ /* The shared RxFIFO size */ ++ dfifo_total = ++ params->dev_rx_fifo_size + params->dev_nperio_tx_fifo_size; ++ ++ /* Add up each TxFIFO size to the total */ ++ for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) { ++ dfifo_total += params->dev_tx_fifo_size[i]; ++ } ++ ++ return dfifo_total; ++} ++ ++/** ++ * This function returns Rx FIFO size ++ * ++ * @param core_if Programming view of DWC_otg controller ++ * ++ * @return The total of data FIFO sizes. ++ * ++ */ ++static int32_t get_rxfifo_size(dwc_otg_core_if_t * core_if, uint16_t wValue) ++{ ++ switch (wValue >> 8) { ++ case 0: ++ return (core_if->pwron_rxfsiz < ++ 32768) ? core_if->pwron_rxfsiz : 32768; ++ break; ++ case 1: ++ return core_if->core_params->dev_rx_fifo_size; ++ break; ++ default: ++ return -DWC_E_INVALID; ++ break; ++ } ++} ++ ++/** ++ * This function returns Tx FIFO size for IN EP ++ * ++ * @param core_if Programming view of DWC_otg controller ++ * ++ * @return The total of data FIFO sizes. ++ * ++ */ ++static int32_t get_txfifo_size(struct dwc_otg_pcd *pcd, uint16_t wValue) ++{ ++ dwc_otg_pcd_ep_t *ep; ++ ++ ep = get_ep_by_addr(pcd, wValue & 0xff); ++ ++ if (NULL == ep) { ++ CFI_INFO("%s: Unable to get the endpoint addr=0x%02x\n", ++ __func__, wValue & 0xff); ++ return -DWC_E_INVALID; ++ } ++ ++ if (!ep->dwc_ep.is_in) { ++ CFI_INFO ++ ("%s: No Tx FIFO assingned to the Out endpoint addr=0x%02x\n", ++ __func__, wValue & 0xff); ++ return -DWC_E_INVALID; ++ } ++ ++ switch (wValue >> 8) { ++ case 0: ++ return (GET_CORE_IF(pcd)-> ++ pwron_txfsiz[ep->dwc_ep.tx_fifo_num - 1] < ++ 768) ? GET_CORE_IF(pcd)->pwron_txfsiz[ep->dwc_ep. ++ tx_fifo_num - ++ 1] : 32768; ++ break; ++ case 1: ++ return GET_CORE_IF(pcd)->core_params->dev_tx_fifo_size[ep-> ++ dwc_ep. ++ num - 1]; ++ break; ++ default: ++ return -DWC_E_INVALID; ++ break; ++ } ++} ++ ++/** ++ * This function checks if the submitted combination of ++ * device mode FIFO sizes is possible or not. ++ * ++ * @param core_if Programming view of DWC_otg controller ++ * ++ * @return 1 if possible, 0 otherwise. ++ * ++ */ ++static uint8_t check_fifo_sizes(dwc_otg_core_if_t * core_if) ++{ ++ uint16_t dfifo_actual = 0; ++ dwc_otg_core_params_t *params = core_if->core_params; ++ uint16_t start_addr = 0; ++ int i; ++ ++ dfifo_actual = ++ params->dev_rx_fifo_size + params->dev_nperio_tx_fifo_size; ++ ++ for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) { ++ dfifo_actual += params->dev_tx_fifo_size[i]; ++ } ++ ++ if (dfifo_actual > core_if->total_fifo_size) { ++ return 0; ++ } ++ ++ if (params->dev_rx_fifo_size > 32768 || params->dev_rx_fifo_size < 16) ++ return 0; ++ ++ if (params->dev_nperio_tx_fifo_size > 32768 ++ || params->dev_nperio_tx_fifo_size < 16) ++ return 0; ++ ++ for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) { ++ ++ if (params->dev_tx_fifo_size[i] > 768 ++ || params->dev_tx_fifo_size[i] < 4) ++ return 0; ++ } ++ ++ if (params->dev_rx_fifo_size > core_if->pwron_rxfsiz) ++ return 0; ++ start_addr = params->dev_rx_fifo_size; ++ ++ if (params->dev_nperio_tx_fifo_size > core_if->pwron_gnptxfsiz) ++ return 0; ++ start_addr += params->dev_nperio_tx_fifo_size; ++ ++ for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) { ++ ++ if (params->dev_tx_fifo_size[i] > core_if->pwron_txfsiz[i]) ++ return 0; ++ start_addr += params->dev_tx_fifo_size[i]; ++ } ++ ++ return 1; ++} ++ ++/** ++ * This function resizes Device mode FIFOs ++ * ++ * @param core_if Programming view of DWC_otg controller ++ * ++ * @return 1 if successful, 0 otherwise ++ * ++ */ ++static uint8_t resize_fifos(dwc_otg_core_if_t * core_if) ++{ ++ int i = 0; ++ dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs; ++ dwc_otg_core_params_t *params = core_if->core_params; ++ uint32_t rx_fifo_size; ++ fifosize_data_t nptxfifosize; ++ fifosize_data_t txfifosize[15]; ++ ++ uint32_t rx_fsz_bak; ++ uint32_t nptxfsz_bak; ++ uint32_t txfsz_bak[15]; ++ ++ uint16_t start_address; ++ uint8_t retval = 1; ++ ++ if (!check_fifo_sizes(core_if)) { ++ return 0; ++ } ++ ++ /* Configure data FIFO sizes */ ++ if (core_if->hwcfg2.b.dynamic_fifo && params->enable_dynamic_fifo) { ++ rx_fsz_bak = dwc_read_reg32(&global_regs->grxfsiz); ++ rx_fifo_size = params->dev_rx_fifo_size; ++ dwc_write_reg32(&global_regs->grxfsiz, rx_fifo_size); ++ ++ /* ++ * Tx FIFOs These FIFOs are numbered from 1 to 15. ++ * Indexes of the FIFO size module parameters in the ++ * dev_tx_fifo_size array and the FIFO size registers in ++ * the dptxfsiz_dieptxf array run from 0 to 14. ++ */ ++ ++ /* Non-periodic Tx FIFO */ ++ nptxfsz_bak = dwc_read_reg32(&global_regs->gnptxfsiz); ++ nptxfifosize.b.depth = params->dev_nperio_tx_fifo_size; ++ start_address = params->dev_rx_fifo_size; ++ nptxfifosize.b.startaddr = start_address; ++ ++ dwc_write_reg32(&global_regs->gnptxfsiz, nptxfifosize.d32); ++ ++ start_address += nptxfifosize.b.depth; ++ ++ for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) { ++ txfsz_bak[i] = ++ dwc_read_reg32(&global_regs->dptxfsiz_dieptxf[i]); ++ ++ txfifosize[i].b.depth = params->dev_tx_fifo_size[i]; ++ txfifosize[i].b.startaddr = start_address; ++ dwc_write_reg32(&global_regs->dptxfsiz_dieptxf[i], ++ txfifosize[i].d32); ++ ++ start_address += txfifosize[i].b.depth; ++ } ++ ++ /** Check if register values are set correctly */ ++ if (rx_fifo_size != dwc_read_reg32(&global_regs->grxfsiz)) { ++ retval = 0; ++ } ++ ++ if (nptxfifosize.d32 != dwc_read_reg32(&global_regs->gnptxfsiz)) { ++ retval = 0; ++ } ++ ++ for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) { ++ if (txfifosize[i].d32 != ++ dwc_read_reg32(&global_regs->dptxfsiz_dieptxf[i])) { ++ retval = 0; ++ } ++ } ++ ++ /** If register values are not set correctly, reset old values */ ++ if (retval == 0) { ++ dwc_write_reg32(&global_regs->grxfsiz, rx_fsz_bak); ++ ++ /* Non-periodic Tx FIFO */ ++ dwc_write_reg32(&global_regs->gnptxfsiz, nptxfsz_bak); ++ ++ for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) { ++ dwc_write_reg32(&global_regs-> ++ dptxfsiz_dieptxf[i], ++ txfsz_bak[i]); ++ } ++ } ++ } else { ++ return 0; ++ } ++ ++ /* Flush the FIFOs */ ++ dwc_otg_flush_tx_fifo(core_if, 0x10); /* all Tx FIFOs */ ++ dwc_otg_flush_rx_fifo(core_if); ++ ++ return retval; ++} ++ ++/** ++ * This function sets a new value for the buffer Alignment setup. ++ */ ++static int cfi_ep_set_tx_fifo_val(uint8_t * buf, dwc_otg_pcd_t * pcd) ++{ ++ int retval; ++ uint32_t fsiz; ++ uint16_t size; ++ uint16_t ep_addr; ++ dwc_otg_pcd_ep_t *ep; ++ dwc_otg_core_params_t *params = GET_CORE_IF(pcd)->core_params; ++ tx_fifo_size_setup_t *ptxfifoval; ++ ++ ptxfifoval = (tx_fifo_size_setup_t *) buf; ++ ep_addr = ptxfifoval->bEndpointAddress; ++ size = ptxfifoval->wDepth; ++ ++ ep = get_ep_by_addr(pcd, ep_addr); ++ ++ CFI_INFO ++ ("%s: Set Tx FIFO size: endpoint addr=0x%02x, depth=%d, FIFO Num=%d\n", ++ __func__, ep_addr, size, ep->dwc_ep.tx_fifo_num); ++ ++ if (NULL == ep) { ++ CFI_INFO("%s: Unable to get the endpoint addr=0x%02x\n", ++ __func__, ep_addr); ++ return -DWC_E_INVALID; ++ } ++ ++ fsiz = params->dev_tx_fifo_size[ep->dwc_ep.tx_fifo_num - 1]; ++ params->dev_tx_fifo_size[ep->dwc_ep.tx_fifo_num - 1] = size; ++ ++ if (resize_fifos(GET_CORE_IF(pcd))) { ++ retval = 0; ++ } else { ++ CFI_INFO ++ ("%s: Error setting the feature Tx FIFO Size for EP%d\n", ++ __func__, ep_addr); ++ params->dev_tx_fifo_size[ep->dwc_ep.tx_fifo_num - 1] = fsiz; ++ retval = -DWC_E_INVALID; ++ } ++ ++ return retval; ++} ++ ++/** ++ * This function sets a new value for the buffer Alignment setup. ++ */ ++static int cfi_set_rx_fifo_val(uint8_t * buf, dwc_otg_pcd_t * pcd) ++{ ++ int retval; ++ uint32_t fsiz; ++ uint16_t size; ++ dwc_otg_core_params_t *params = GET_CORE_IF(pcd)->core_params; ++ rx_fifo_size_setup_t *prxfifoval; ++ ++ prxfifoval = (rx_fifo_size_setup_t *) buf; ++ size = prxfifoval->wDepth; ++ ++ fsiz = params->dev_rx_fifo_size; ++ params->dev_rx_fifo_size = size; ++ ++ if (resize_fifos(GET_CORE_IF(pcd))) { ++ retval = 0; ++ } else { ++ CFI_INFO("%s: Error setting the feature Rx FIFO Size\n", ++ __func__); ++ params->dev_rx_fifo_size = fsiz; ++ retval = -DWC_E_INVALID; ++ } ++ ++ return retval; ++} ++ ++/** ++ * This function reads the SG of an EP's buffer setup into the buffer buf ++ */ ++static int cfi_ep_get_sg_val(uint8_t * buf, struct dwc_otg_pcd *pcd, ++ struct cfi_usb_ctrlrequest *req) ++{ ++ int retval = -DWC_E_INVALID; ++ uint8_t addr; ++ cfi_ep_t *ep; ++ ++ /* The Low Byte of the wValue contains a non-zero address of the endpoint */ ++ addr = req->wValue & 0xFF; ++ if (addr == 0) /* The address should be non-zero */ ++ return retval; ++ ++ ep = get_cfi_ep_by_addr(pcd->cfi, addr); ++ if (NULL == ep) { ++ CFI_INFO("%s: Unable to get the endpoint address(0x%02x)\n", ++ __func__, addr); ++ return retval; ++ } ++ ++ dwc_memcpy(buf, ep->bm_sg, BS_SG_VAL_DESC_LEN); ++ retval = BS_SG_VAL_DESC_LEN; ++ return retval; ++} ++ ++/** ++ * This function reads the Concatenation value of an EP's buffer mode into ++ * the buffer buf ++ */ ++static int cfi_ep_get_concat_val(uint8_t * buf, struct dwc_otg_pcd *pcd, ++ struct cfi_usb_ctrlrequest *req) ++{ ++ int retval = -DWC_E_INVALID; ++ uint8_t addr; ++ cfi_ep_t *ep; ++ uint8_t desc_count; ++ ++ /* The Low Byte of the wValue contains a non-zero address of the endpoint */ ++ addr = req->wValue & 0xFF; ++ if (addr == 0) /* The address should be non-zero */ ++ return retval; ++ ++ ep = get_cfi_ep_by_addr(pcd->cfi, addr); ++ if (NULL == ep) { ++ CFI_INFO("%s: Unable to get the endpoint address(0x%02x)\n", ++ __func__, addr); ++ return retval; ++ } ++ ++ /* Copy the header to the buffer */ ++ dwc_memcpy(buf, ep->bm_concat, BS_CONCAT_VAL_HDR_LEN); ++ /* Advance the buffer pointer by the header size */ ++ buf += BS_CONCAT_VAL_HDR_LEN; ++ ++ desc_count = ep->bm_concat->hdr.bDescCount; ++ /* Copy alll the wTxBytes to the buffer */ ++ dwc_memcpy(buf, ep->bm_concat->wTxBytes, sizeof(uid16_t) * desc_count); ++ ++ retval = BS_CONCAT_VAL_HDR_LEN + sizeof(uid16_t) * desc_count; ++ return retval; ++} ++ ++/** ++ * This function reads the buffer Alignment value of an EP's buffer mode into ++ * the buffer buf ++ * ++ * @return The total number of bytes copied to the buffer or negative error code. ++ */ ++static int cfi_ep_get_align_val(uint8_t * buf, struct dwc_otg_pcd *pcd, ++ struct cfi_usb_ctrlrequest *req) ++{ ++ int retval = -DWC_E_INVALID; ++ uint8_t addr; ++ cfi_ep_t *ep; ++ ++ /* The Low Byte of the wValue contains a non-zero address of the endpoint */ ++ addr = req->wValue & 0xFF; ++ if (addr == 0) /* The address should be non-zero */ ++ return retval; ++ ++ ep = get_cfi_ep_by_addr(pcd->cfi, addr); ++ if (NULL == ep) { ++ CFI_INFO("%s: Unable to get the endpoint address(0x%02x)\n", ++ __func__, addr); ++ return retval; ++ } ++ ++ dwc_memcpy(buf, ep->bm_align, BS_ALIGN_VAL_HDR_LEN); ++ retval = BS_ALIGN_VAL_HDR_LEN; ++ ++ return retval; ++} ++ ++/** ++ * This function sets a new value for the specified feature ++ * ++ * @param pcd A pointer to the PCD object ++ * ++ * @return 0 if successful, negative error code otherwise to stall the DCE. ++ */ ++static int cfi_set_feature_value(struct dwc_otg_pcd *pcd) ++{ ++ int retval = -DWC_E_NOT_SUPPORTED; ++ uint16_t wIndex, wValue; ++ uint8_t bRequest; ++ struct dwc_otg_core_if *coreif; ++ cfiobject_t *cfi = pcd->cfi; ++ struct cfi_usb_ctrlrequest *ctrl_req; ++ uint8_t *buf; ++ ctrl_req = &cfi->ctrl_req; ++ ++ buf = pcd->cfi->ctrl_req.data; ++ ++ coreif = GET_CORE_IF(pcd); ++ bRequest = ctrl_req->bRequest; ++ wIndex = DWC_CONSTANT_CPU_TO_LE16(ctrl_req->wIndex); ++ wValue = DWC_CONSTANT_CPU_TO_LE16(ctrl_req->wValue); ++ ++ /* See which feature is to be modified */ ++ switch (wIndex) { ++ case FT_ID_DMA_BUFFER_SETUP: ++ /* Modify the feature */ ++ if ((retval = cfi_ep_set_sg_val(buf, pcd)) < 0) ++ return retval; ++ ++ /* And send this request to the gadget */ ++ cfi->need_gadget_att = 1; ++ break; ++ ++ case FT_ID_DMA_BUFF_ALIGN: ++ if ((retval = cfi_ep_set_alignment_val(buf, pcd)) < 0) ++ return retval; ++ cfi->need_gadget_att = 1; ++ break; ++ ++ case FT_ID_DMA_CONCAT_SETUP: ++ /* Modify the feature */ ++ if ((retval = cfi_ep_set_concat_val(buf, pcd)) < 0) ++ return retval; ++ cfi->need_gadget_att = 1; ++ break; ++ ++ case FT_ID_DMA_CIRCULAR: ++ CFI_INFO("FT_ID_DMA_CIRCULAR\n"); ++ break; ++ ++ case FT_ID_THRESHOLD_SETUP: ++ CFI_INFO("FT_ID_THRESHOLD_SETUP\n"); ++ break; ++ ++ case FT_ID_DFIFO_DEPTH: ++ CFI_INFO("FT_ID_DFIFO_DEPTH\n"); ++ break; ++ ++ case FT_ID_TX_FIFO_DEPTH: ++ CFI_INFO("FT_ID_TX_FIFO_DEPTH\n"); ++ if ((retval = cfi_ep_set_tx_fifo_val(buf, pcd)) < 0) ++ return retval; ++ cfi->need_gadget_att = 0; ++ break; ++ ++ case FT_ID_RX_FIFO_DEPTH: ++ CFI_INFO("FT_ID_RX_FIFO_DEPTH\n"); ++ if ((retval = cfi_set_rx_fifo_val(buf, pcd)) < 0) ++ return retval; ++ cfi->need_gadget_att = 0; ++ break; ++ } ++ ++ return retval; ++} ++ ++#endif //DWC_UTE_CFI +Index: linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_cfi.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_cfi.h 2013-07-26 19:31:23.000000000 +0000 +@@ -0,0 +1,319 @@ ++/* ========================================================================== ++ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, ++ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless ++ * otherwise expressly agreed to in writing between Synopsys and you. ++ * ++ * The Software IS NOT an item of Licensed Software or Licensed Product under ++ * any End User Software License Agreement or Agreement for Licensed Product ++ * with Synopsys or any supplement thereto. You are permitted to use and ++ * redistribute this Software in source and binary forms, with or without ++ * modification, provided that redistributions of source code must retain this ++ * notice. You may not view, use, disclose, copy or distribute this file or ++ * any information contained herein except pursuant to this license grant from ++ * Synopsys. If you do not agree with this notice, including the disclaimer ++ * below, then you are not authorized to use the Software. ++ * ++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, ++ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR ++ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER ++ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY ++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH ++ * DAMAGE. ++ * ========================================================================== */ ++ ++#if !defined(__DWC_OTG_CFI_H__) ++#define __DWC_OTG_CFI_H__ ++ ++#include "dwc_otg_pcd.h" ++#include "dwc_cfi_common.h" ++ ++/** ++ * @file ++ * ++ * This file contains the CFI related OTG PCD specific common constants, interfaces ++ * (functions and macros) and data structures. ++ * ++ */ ++ ++struct dwc_otg_pcd; ++struct dwc_otg_pcd_ep; ++ ++/** OTG CFI Features (properties) ID constants */ ++/** This is a request for all Core Features */ ++#define FT_ID_DMA_MODE 0x0001 ++#define FT_ID_DMA_BUFFER_SETUP 0x0002 ++#define FT_ID_DMA_BUFF_ALIGN 0x0003 ++#define FT_ID_DMA_CONCAT_SETUP 0x0004 ++#define FT_ID_DMA_CIRCULAR 0x0005 ++#define FT_ID_THRESHOLD_SETUP 0x0006 ++#define FT_ID_DFIFO_DEPTH 0x0007 ++#define FT_ID_TX_FIFO_DEPTH 0x0008 ++#define FT_ID_RX_FIFO_DEPTH 0x0009 ++ ++/**********************************************************/ ++#define CFI_INFO_DEF ++ ++#ifdef CFI_INFO_DEF ++#define CFI_INFO(fmt...) DWC_PRINTF("CFI: " fmt); ++#else ++#define CFI_INFO(fmt...) ++#endif ++ ++#define min(x,y) ({ \ ++ x < y ? x : y; }) ++ ++#define max(x,y) ({ \ ++ x > y ? x : y; }) ++ ++/** ++ * Descriptor DMA SG Buffer setup structure (SG buffer). This structure is ++ * also used for setting up a buffer for Circular DDMA. ++ */ ++struct _ddma_sg_buffer_setup { ++#define BS_SG_VAL_DESC_LEN 6 ++ /* The OUT EP address */ ++ uint8_t bOutEndpointAddress; ++ /* The IN EP address */ ++ uint8_t bInEndpointAddress; ++ /* Number of bytes to put between transfer segments (must be DWORD boundaries) */ ++ uint8_t bOffset; ++ /* The number of transfer segments (a DMA descriptors per each segment) */ ++ uint8_t bCount; ++ /* Size (in byte) of each transfer segment */ ++ uint16_t wSize; ++} __attribute__ ((packed)); ++typedef struct _ddma_sg_buffer_setup ddma_sg_buffer_setup_t; ++ ++/** Descriptor DMA Concatenation Buffer setup structure */ ++struct _ddma_concat_buffer_setup_hdr { ++#define BS_CONCAT_VAL_HDR_LEN 4 ++ /* The endpoint for which the buffer is to be set up */ ++ uint8_t bEndpointAddress; ++ /* The count of descriptors to be used */ ++ uint8_t bDescCount; ++ /* The total size of the transfer */ ++ uint16_t wSize; ++} __attribute__ ((packed)); ++typedef struct _ddma_concat_buffer_setup_hdr ddma_concat_buffer_setup_hdr_t; ++ ++/** Descriptor DMA Concatenation Buffer setup structure */ ++struct _ddma_concat_buffer_setup { ++ /* The SG header */ ++ ddma_concat_buffer_setup_hdr_t hdr; ++ ++ /* The XFER sizes pointer (allocated dynamically) */ ++ uint16_t *wTxBytes; ++} __attribute__ ((packed)); ++typedef struct _ddma_concat_buffer_setup ddma_concat_buffer_setup_t; ++ ++/** Descriptor DMA Alignment Buffer setup structure */ ++struct _ddma_align_buffer_setup { ++#define BS_ALIGN_VAL_HDR_LEN 2 ++ uint8_t bEndpointAddress; ++ uint8_t bAlign; ++} __attribute__ ((packed)); ++typedef struct _ddma_align_buffer_setup ddma_align_buffer_setup_t; ++ ++/** Transmit FIFO Size setup structure */ ++struct _tx_fifo_size_setup { ++ uint8_t bEndpointAddress; ++ uint16_t wDepth; ++} __attribute__ ((packed)); ++typedef struct _tx_fifo_size_setup tx_fifo_size_setup_t; ++ ++/** Transmit FIFO Size setup structure */ ++struct _rx_fifo_size_setup { ++ uint16_t wDepth; ++} __attribute__ ((packed)); ++typedef struct _rx_fifo_size_setup rx_fifo_size_setup_t; ++ ++/** ++ * struct cfi_usb_ctrlrequest - the CFI implementation of the struct usb_ctrlrequest ++ * This structure encapsulates the standard usb_ctrlrequest and adds a pointer ++ * to the data returned in the data stage of a 3-stage Control Write requests. ++ */ ++struct cfi_usb_ctrlrequest { ++ uint8_t bRequestType; ++ uint8_t bRequest; ++ uint16_t wValue; ++ uint16_t wIndex; ++ uint16_t wLength; ++ uint8_t *data; ++} UPACKED; ++ ++/*---------------------------------------------------------------------------*/ ++ ++/** ++ * The CFI wrapper of the enabled and activated dwc_otg_pcd_ep structures. ++ * This structure is used to store the buffer setup data for any ++ * enabled endpoint in the PCD. ++ */ ++struct cfi_ep { ++ /* Entry for the list container */ ++ dwc_list_link_t lh; ++ /* Pointer to the active PCD endpoint structure */ ++ struct dwc_otg_pcd_ep *ep; ++ /* The last descriptor in the chain of DMA descriptors of the endpoint */ ++ struct dwc_otg_dma_desc *dma_desc_last; ++ /* The SG feature value */ ++ ddma_sg_buffer_setup_t *bm_sg; ++ /* The Circular feature value */ ++ ddma_sg_buffer_setup_t *bm_circ; ++ /* The Concatenation feature value */ ++ ddma_concat_buffer_setup_t *bm_concat; ++ /* The Alignment feature value */ ++ ddma_align_buffer_setup_t *bm_align; ++ /* XFER length */ ++ uint32_t xfer_len; ++ /* ++ * Count of DMA descriptors currently used. ++ * The total should not exceed the MAX_DMA_DESCS_PER_EP value ++ * defined in the dwc_otg_cil.h ++ */ ++ uint32_t desc_count; ++}; ++typedef struct cfi_ep cfi_ep_t; ++ ++typedef struct cfi_dma_buff { ++#define CFI_IN_BUF_LEN 1024 ++#define CFI_OUT_BUF_LEN 1024 ++ dma_addr_t addr; ++ uint8_t *buf; ++} cfi_dma_buff_t; ++ ++struct cfiobject; ++ ++/** ++ * This is the interface for the CFI operations. ++ * ++ * @param ep_enable Called when any endpoint is enabled and activated. ++ * @param release Called when the CFI object is released and it needs to correctly ++ * deallocate the dynamic memory ++ * @param ctrl_write_complete Called when the data stage of the request is complete ++ */ ++typedef struct cfi_ops { ++ int (*ep_enable) (struct cfiobject * cfi, struct dwc_otg_pcd * pcd, ++ struct dwc_otg_pcd_ep * ep); ++ void *(*ep_alloc_buf) (struct cfiobject * cfi, struct dwc_otg_pcd * pcd, ++ struct dwc_otg_pcd_ep * ep, dma_addr_t * dma, ++ unsigned size, gfp_t flags); ++ void (*release) (struct cfiobject * cfi); ++ int (*ctrl_write_complete) (struct cfiobject * cfi, ++ struct dwc_otg_pcd * pcd); ++ void (*build_descriptors) (struct cfiobject * cfi, ++ struct dwc_otg_pcd * pcd, ++ struct dwc_otg_pcd_ep * ep, ++ dwc_otg_pcd_request_t * req); ++} cfi_ops_t; ++ ++struct cfiobject { ++ cfi_ops_t ops; ++ struct dwc_otg_pcd *pcd; ++ struct usb_gadget *gadget; ++ ++ /* Buffers used to send/receive CFI-related request data */ ++ cfi_dma_buff_t buf_in; ++ cfi_dma_buff_t buf_out; ++ ++ /* CFI specific Control request wrapper */ ++ struct cfi_usb_ctrlrequest ctrl_req; ++ ++ /* The list of active EP's in the PCD of type cfi_ep_t */ ++ dwc_list_link_t active_eps; ++ ++ /* This flag shall control the propagation of a specific request ++ * to the gadget's processing routines. ++ * 0 - no gadget handling ++ * 1 - the gadget needs to know about this request (w/o completing a status ++ * phase - just return a 0 to the _setup callback) ++ */ ++ uint8_t need_gadget_att; ++ ++ /* Flag indicating whether the status IN phase needs to be ++ * completed by the PCD ++ */ ++ uint8_t need_status_in_complete; ++}; ++typedef struct cfiobject cfiobject_t; ++ ++#define DUMP_MSG ++ ++#if defined(DUMP_MSG) ++static inline void dump_msg(const u8 * buf, unsigned int length) ++{ ++ unsigned int start, num, i; ++ char line[52], *p; ++ ++ if (length >= 512) ++ return; ++ ++ start = 0; ++ while (length > 0) { ++ num = min(length, 16u); ++ p = line; ++ for (i = 0; i < num; ++i) { ++ if (i == 8) ++ *p++ = ' '; ++ DWC_SPRINTF(p, " %02x", buf[i]); ++ p += 3; ++ } ++ *p = 0; ++ DWC_DEBUG("%6x: %s\n", start, line); ++ buf += num; ++ start += num; ++ length -= num; ++ } ++} ++#else ++static inline void dump_msg(const u8 * buf, unsigned int length) ++{ ++} ++#endif ++ ++/** ++ * This function returns a pointer to cfi_ep_t object with the addr address. ++ */ ++static inline struct cfi_ep *get_cfi_ep_by_addr(struct cfiobject *cfi, ++ uint8_t addr) ++{ ++ struct cfi_ep *pcfiep; ++ dwc_list_link_t *tmp; ++ ++ DWC_LIST_FOREACH(tmp, &cfi->active_eps) { ++ pcfiep = DWC_LIST_ENTRY(tmp, struct cfi_ep, lh); ++ ++ if (pcfiep->ep->desc->bEndpointAddress == addr) { ++ return pcfiep; ++ } ++ } ++ ++ return NULL; ++} ++ ++/** ++ * This function returns a pointer to cfi_ep_t object that matches ++ * the dwc_otg_pcd_ep object. ++ */ ++static inline struct cfi_ep *get_cfi_ep_by_pcd_ep(struct cfiobject *cfi, ++ struct dwc_otg_pcd_ep *ep) ++{ ++ struct cfi_ep *pcfiep = NULL; ++ dwc_list_link_t *tmp; ++ ++ DWC_LIST_FOREACH(tmp, &cfi->active_eps) { ++ pcfiep = DWC_LIST_ENTRY(tmp, struct cfi_ep, lh); ++ if (pcfiep->ep == ep) { ++ return pcfiep; ++ } ++ } ++ return NULL; ++} ++ ++int cfi_setup(struct dwc_otg_pcd *pcd, struct cfi_usb_ctrlrequest *ctrl); ++ ++#endif /* (__DWC_OTG_CFI_H__) */ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_cil.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_cil.c 2013-07-26 19:31:23.000000000 +0000 +@@ -0,0 +1,5410 @@ ++/* ========================================================================== ++ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_cil.c $ ++ * $Revision: #159 $ ++ * $Date: 2009/04/21 $ ++ * $Change: 1237465 $ ++ * ++ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, ++ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless ++ * otherwise expressly agreed to in writing between Synopsys and you. ++ * ++ * The Software IS NOT an item of Licensed Software or Licensed Product under ++ * any End User Software License Agreement or Agreement for Licensed Product ++ * with Synopsys or any supplement thereto. You are permitted to use and ++ * redistribute this Software in source and binary forms, with or without ++ * modification, provided that redistributions of source code must retain this ++ * notice. You may not view, use, disclose, copy or distribute this file or ++ * any information contained herein except pursuant to this license grant from ++ * Synopsys. If you do not agree with this notice, including the disclaimer ++ * below, then you are not authorized to use the Software. ++ * ++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, ++ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR ++ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER ++ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY ++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH ++ * DAMAGE. ++ * ========================================================================== */ ++ ++/** @file ++ * ++ * The Core Interface Layer provides basic services for accessing and ++ * managing the DWC_otg hardware. These services are used by both the ++ * Host Controller Driver and the Peripheral Controller Driver. ++ * ++ * The CIL manages the memory map for the core so that the HCD and PCD ++ * don't have to do this separately. It also handles basic tasks like ++ * reading/writing the registers and data FIFOs in the controller. ++ * Some of the data access functions provide encapsulation of several ++ * operations required to perform a task, such as writing multiple ++ * registers to start a transfer. Finally, the CIL performs basic ++ * services that are not specific to either the host or device modes ++ * of operation. These services include management of the OTG Host ++ * Negotiation Protocol (HNP) and Session Request Protocol (SRP). A ++ * Diagnostic API is also provided to allow testing of the controller ++ * hardware. ++ * ++ * The Core Interface Layer has the following requirements: ++ * - Provides basic controller operations. ++ * - Minimal use of OS services. ++ * - The OS services used will be abstracted by using inline functions ++ * or macros. ++ * ++ */ ++ ++#include "dwc_os.h" ++#include "dwc_otg_regs.h" ++#include "dwc_otg_cil.h" ++ ++static int dwc_otg_setup_params(dwc_otg_core_if_t * core_if); ++ ++/** ++ * This function is called to initialize the DWC_otg CSR data ++ * structures. The register addresses in the device and host ++ * structures are initialized from the base address supplied by the ++ * caller. The calling function must make the OS calls to get the ++ * base address of the DWC_otg controller registers. The core_params ++ * argument holds the parameters that specify how the core should be ++ * configured. ++ * ++ * @param reg_base_addr Base address of DWC_otg core registers ++ * ++ */ ++dwc_otg_core_if_t *dwc_otg_cil_init(const uint32_t * reg_base_addr) ++{ ++ dwc_otg_core_if_t *core_if = 0; ++ dwc_otg_dev_if_t *dev_if = 0; ++ dwc_otg_host_if_t *host_if = 0; ++ uint8_t *reg_base = (uint8_t *) reg_base_addr; ++ int i = 0; ++ ++ DWC_DEBUGPL(DBG_CILV, "%s(%p)\n", __func__, reg_base_addr); ++ ++ core_if = dwc_alloc(sizeof(dwc_otg_core_if_t)); ++ ++ if (core_if == 0) { ++ DWC_DEBUGPL(DBG_CIL, ++ "Allocation of dwc_otg_core_if_t failed\n"); ++ return 0; ++ } ++ core_if->core_global_regs = (dwc_otg_core_global_regs_t *) reg_base; ++ ++ /* ++ * Allocate the Device Mode structures. ++ */ ++ dev_if = dwc_alloc(sizeof(dwc_otg_dev_if_t)); ++ ++ if (dev_if == 0) { ++ DWC_DEBUGPL(DBG_CIL, "Allocation of dwc_otg_dev_if_t failed\n"); ++ dwc_free(core_if); ++ return 0; ++ } ++ ++ dev_if->dev_global_regs = ++ (dwc_otg_device_global_regs_t *) (reg_base + ++ DWC_DEV_GLOBAL_REG_OFFSET); ++ ++ for (i = 0; i < MAX_EPS_CHANNELS; i++) { ++ dev_if->in_ep_regs[i] = (dwc_otg_dev_in_ep_regs_t *) ++ (reg_base + DWC_DEV_IN_EP_REG_OFFSET + ++ (i * DWC_EP_REG_OFFSET)); ++ ++ dev_if->out_ep_regs[i] = (dwc_otg_dev_out_ep_regs_t *) ++ (reg_base + DWC_DEV_OUT_EP_REG_OFFSET + ++ (i * DWC_EP_REG_OFFSET)); ++ DWC_DEBUGPL(DBG_CILV, "in_ep_regs[%d]->diepctl=%p\n", ++ i, &dev_if->in_ep_regs[i]->diepctl); ++ DWC_DEBUGPL(DBG_CILV, "out_ep_regs[%d]->doepctl=%p\n", ++ i, &dev_if->out_ep_regs[i]->doepctl); ++ } ++ ++ dev_if->speed = 0; // unknown ++ ++ core_if->dev_if = dev_if; ++ ++ /* ++ * Allocate the Host Mode structures. ++ */ ++ host_if = dwc_alloc(sizeof(dwc_otg_host_if_t)); ++ ++ if (host_if == 0) { ++ DWC_DEBUGPL(DBG_CIL, ++ "Allocation of dwc_otg_host_if_t failed\n"); ++ dwc_free(dev_if); ++ dwc_free(core_if); ++ return 0; ++ } ++ ++ host_if->host_global_regs = (dwc_otg_host_global_regs_t *) ++ (reg_base + DWC_OTG_HOST_GLOBAL_REG_OFFSET); ++ ++ host_if->hprt0 = ++ (uint32_t *) (reg_base + DWC_OTG_HOST_PORT_REGS_OFFSET); ++ ++ for (i = 0; i < MAX_EPS_CHANNELS; i++) { ++ host_if->hc_regs[i] = (dwc_otg_hc_regs_t *) ++ (reg_base + DWC_OTG_HOST_CHAN_REGS_OFFSET + ++ (i * DWC_OTG_CHAN_REGS_OFFSET)); ++ DWC_DEBUGPL(DBG_CILV, "hc_reg[%d]->hcchar=%p\n", ++ i, &host_if->hc_regs[i]->hcchar); ++ } ++ ++ host_if->num_host_channels = MAX_EPS_CHANNELS; ++ core_if->host_if = host_if; ++ ++ for (i = 0; i < MAX_EPS_CHANNELS; i++) { ++ core_if->data_fifo[i] = ++ (uint32_t *) (reg_base + DWC_OTG_DATA_FIFO_OFFSET + ++ (i * DWC_OTG_DATA_FIFO_SIZE)); ++ DWC_DEBUGPL(DBG_CILV, "data_fifo[%d]=0x%08x\n", ++ i, (unsigned)core_if->data_fifo[i]); ++ } ++ ++ core_if->pcgcctl = (uint32_t *) (reg_base + DWC_OTG_PCGCCTL_OFFSET); ++ ++ /* Initiate lx_state to L3 disconnected state */ ++ core_if->lx_state = DWC_OTG_L3; ++ /* ++ * Store the contents of the hardware configuration registers here for ++ * easy access later. ++ */ ++ core_if->hwcfg1.d32 = ++ dwc_read_reg32(&core_if->core_global_regs->ghwcfg1); ++ core_if->hwcfg2.d32 = ++ dwc_read_reg32(&core_if->core_global_regs->ghwcfg2); ++ core_if->hwcfg3.d32 = ++ dwc_read_reg32(&core_if->core_global_regs->ghwcfg3); ++ core_if->hwcfg4.d32 = ++ dwc_read_reg32(&core_if->core_global_regs->ghwcfg4); ++ ++ DWC_DEBUGPL(DBG_CILV, "hwcfg1=%08x\n", core_if->hwcfg1.d32); ++ DWC_DEBUGPL(DBG_CILV, "hwcfg2=%08x\n", core_if->hwcfg2.d32); ++ DWC_DEBUGPL(DBG_CILV, "hwcfg3=%08x\n", core_if->hwcfg3.d32); ++ DWC_DEBUGPL(DBG_CILV, "hwcfg4=%08x\n", core_if->hwcfg4.d32); ++ ++ core_if->hcfg.d32 = ++ dwc_read_reg32(&core_if->host_if->host_global_regs->hcfg); ++ core_if->dcfg.d32 = ++ dwc_read_reg32(&core_if->dev_if->dev_global_regs->dcfg); ++ ++ DWC_DEBUGPL(DBG_CILV, "hcfg=%08x\n", core_if->hcfg.d32); ++ DWC_DEBUGPL(DBG_CILV, "dcfg=%08x\n", core_if->dcfg.d32); ++ ++ DWC_DEBUGPL(DBG_CILV, "op_mode=%0x\n", core_if->hwcfg2.b.op_mode); ++ DWC_DEBUGPL(DBG_CILV, "arch=%0x\n", core_if->hwcfg2.b.architecture); ++ DWC_DEBUGPL(DBG_CILV, "num_dev_ep=%d\n", core_if->hwcfg2.b.num_dev_ep); ++ DWC_DEBUGPL(DBG_CILV, "num_host_chan=%d\n", ++ core_if->hwcfg2.b.num_host_chan); ++ DWC_DEBUGPL(DBG_CILV, "nonperio_tx_q_depth=0x%0x\n", ++ core_if->hwcfg2.b.nonperio_tx_q_depth); ++ DWC_DEBUGPL(DBG_CILV, "host_perio_tx_q_depth=0x%0x\n", ++ core_if->hwcfg2.b.host_perio_tx_q_depth); ++ DWC_DEBUGPL(DBG_CILV, "dev_token_q_depth=0x%0x\n", ++ core_if->hwcfg2.b.dev_token_q_depth); ++ ++ DWC_DEBUGPL(DBG_CILV, "Total FIFO SZ=%d\n", ++ core_if->hwcfg3.b.dfifo_depth); ++ DWC_DEBUGPL(DBG_CILV, "xfer_size_cntr_width=%0x\n", ++ core_if->hwcfg3.b.xfer_size_cntr_width); ++ ++ /* ++ * Set the SRP sucess bit for FS-I2c ++ */ ++ core_if->srp_success = 0; ++ core_if->srp_timer_started = 0; ++ ++ /* ++ * Create new workqueue and init works ++ */ ++ core_if->wq_otg = DWC_WORKQ_ALLOC("dwc_otg"); ++ if (core_if->wq_otg == 0) { ++ DWC_WARN("DWC_WORKQ_ALLOC failed\n"); ++ dwc_free(host_if); ++ dwc_free(dev_if); ++ dwc_free(core_if); ++ return 0; ++ } ++ ++ core_if->snpsid = dwc_read_reg32(&core_if->core_global_regs->gsnpsid); ++ ++ DWC_PRINTF("Core Release: %x.%x%x%x\n", ++ (core_if->snpsid >> 12 & 0xF), ++ (core_if->snpsid >> 8 & 0xF), ++ (core_if->snpsid >> 4 & 0xF), (core_if->snpsid & 0xF)); ++ ++ core_if->wkp_timer = DWC_TIMER_ALLOC("Wake Up Timer", ++ w_wakeup_detected, core_if); ++ if (core_if->wkp_timer == 0) { ++ DWC_WARN("DWC_TIMER_ALLOC failed\n"); ++ dwc_free(host_if); ++ dwc_free(dev_if); ++ DWC_WORKQ_FREE(core_if->wq_otg); ++ dwc_free(core_if); ++ return 0; ++ } ++ ++ if (dwc_otg_setup_params(core_if)) { ++ DWC_WARN("Error while setting core params\n"); ++ } ++ ++ return core_if; ++} ++ ++/** ++ * This function frees the structures allocated by dwc_otg_cil_init(). ++ * ++ * @param core_if The core interface pointer returned from ++ * dwc_otg_cil_init(). ++ * ++ */ ++void dwc_otg_cil_remove(dwc_otg_core_if_t * core_if) ++{ ++ DWC_DEBUGPL(DBG_CILV, "%s(%p)\n", __func__, core_if); ++ ++ /* Disable all interrupts */ ++ dwc_modify_reg32(&core_if->core_global_regs->gahbcfg, 1, 0); ++ dwc_write_reg32(&core_if->core_global_regs->gintmsk, 0); ++ ++ if (core_if->wq_otg) { ++ DWC_WORKQ_WAIT_WORK_DONE(core_if->wq_otg, 500); ++ DWC_WORKQ_FREE(core_if->wq_otg); ++ } ++ if (core_if->dev_if) { ++ dwc_free(core_if->dev_if); ++ } ++ if (core_if->host_if) { ++ dwc_free(core_if->host_if); ++ } ++ dwc_free(core_if); ++ DWC_TIMER_FREE(core_if->wkp_timer); ++ DWC_FREE(core_if->core_params); ++} ++ ++/** ++ * This function enables the controller's Global Interrupt in the AHB Config ++ * register. ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ */ ++void dwc_otg_enable_global_interrupts(dwc_otg_core_if_t * core_if) ++{ ++ gahbcfg_data_t ahbcfg = {.d32 = 0 }; ++ ahbcfg.b.glblintrmsk = 1; /* Enable interrupts */ ++ dwc_modify_reg32(&core_if->core_global_regs->gahbcfg, 0, ahbcfg.d32); ++} ++ ++/** ++ * This function disables the controller's Global Interrupt in the AHB Config ++ * register. ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ */ ++void dwc_otg_disable_global_interrupts(dwc_otg_core_if_t * core_if) ++{ ++ gahbcfg_data_t ahbcfg = {.d32 = 0 }; ++ ahbcfg.b.glblintrmsk = 1; /* Enable interrupts */ ++ DWC_PRINTF("%x -> %x\n", (unsigned int)&core_if->core_global_regs->gahbcfg, ahbcfg.d32); ++ dwc_modify_reg32(&core_if->core_global_regs->gahbcfg, ahbcfg.d32, 0); ++} ++ ++/** ++ * This function initializes the commmon interrupts, used in both ++ * device and host modes. ++ * ++ * @param core_if Programming view of the DWC_otg controller ++ * ++ */ ++static void dwc_otg_enable_common_interrupts(dwc_otg_core_if_t * core_if) ++{ ++ dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs; ++ gintmsk_data_t intr_mask = {.d32 = 0 }; ++ ++ /* Clear any pending OTG Interrupts */ ++ dwc_write_reg32(&global_regs->gotgint, 0xFFFFFFFF); ++ ++ /* Clear any pending interrupts */ ++ dwc_write_reg32(&global_regs->gintsts, 0xFFFFFFFF); ++ ++ /* ++ * Enable the interrupts in the GINTMSK. ++ */ ++ intr_mask.b.modemismatch = 1; ++ intr_mask.b.otgintr = 1; ++ ++ if (!core_if->dma_enable) { ++ intr_mask.b.rxstsqlvl = 1; ++ } ++ ++ intr_mask.b.conidstschng = 1; ++ intr_mask.b.wkupintr = 1; ++ intr_mask.b.disconnect = 1; ++ intr_mask.b.usbsuspend = 1; ++ intr_mask.b.sessreqintr = 1; ++#ifdef CONFIG_USB_DWC_OTG_LPM ++ if (core_if->core_params->lpm_enable) { ++ intr_mask.b.lpmtranrcvd = 1; ++ } ++#endif ++ dwc_write_reg32(&global_regs->gintmsk, intr_mask.d32); ++} ++ ++/** ++ * Initializes the FSLSPClkSel field of the HCFG register depending on the PHY ++ * type. ++ */ ++static void init_fslspclksel(dwc_otg_core_if_t * core_if) ++{ ++ uint32_t val; ++ hcfg_data_t hcfg; ++ ++ if (((core_if->hwcfg2.b.hs_phy_type == 2) && ++ (core_if->hwcfg2.b.fs_phy_type == 1) && ++ (core_if->core_params->ulpi_fs_ls)) || ++ (core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS)) { ++ /* Full speed PHY */ ++ val = DWC_HCFG_48_MHZ; ++ } else { ++ /* High speed PHY running at full speed or high speed */ ++ val = DWC_HCFG_30_60_MHZ; ++ } ++ ++ DWC_DEBUGPL(DBG_CIL, "Initializing HCFG.FSLSPClkSel to 0x%1x\n", val); ++ hcfg.d32 = dwc_read_reg32(&core_if->host_if->host_global_regs->hcfg); ++ hcfg.b.fslspclksel = val; ++ dwc_write_reg32(&core_if->host_if->host_global_regs->hcfg, hcfg.d32); ++} ++ ++/** ++ * Initializes the DevSpd field of the DCFG register depending on the PHY type ++ * and the enumeration speed of the device. ++ */ ++static void init_devspd(dwc_otg_core_if_t * core_if) ++{ ++ uint32_t val; ++ dcfg_data_t dcfg; ++ ++ if (((core_if->hwcfg2.b.hs_phy_type == 2) && ++ (core_if->hwcfg2.b.fs_phy_type == 1) && ++ (core_if->core_params->ulpi_fs_ls)) || ++ (core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS)) { ++ /* Full speed PHY */ ++ val = 0x3; ++ } else if (core_if->core_params->speed == DWC_SPEED_PARAM_FULL) { ++ /* High speed PHY running at full speed */ ++ val = 0x1; ++ } else { ++ /* High speed PHY running at high speed */ ++ val = 0x0; ++ } ++ ++ DWC_DEBUGPL(DBG_CIL, "Initializing DCFG.DevSpd to 0x%1x\n", val); ++ ++ dcfg.d32 = dwc_read_reg32(&core_if->dev_if->dev_global_regs->dcfg); ++ dcfg.b.devspd = val; ++ dwc_write_reg32(&core_if->dev_if->dev_global_regs->dcfg, dcfg.d32); ++} ++ ++/** ++ * This function calculates the number of IN EPS ++ * using GHWCFG1 and GHWCFG2 registers values ++ * ++ * @param core_if Programming view of the DWC_otg controller ++ */ ++static uint32_t calc_num_in_eps(dwc_otg_core_if_t * core_if) ++{ ++ uint32_t num_in_eps = 0; ++ uint32_t num_eps = core_if->hwcfg2.b.num_dev_ep; ++ uint32_t hwcfg1 = core_if->hwcfg1.d32 >> 3; ++ uint32_t num_tx_fifos = core_if->hwcfg4.b.num_in_eps; ++ int i; ++ ++ for (i = 0; i < num_eps; ++i) { ++ if (!(hwcfg1 & 0x1)) ++ num_in_eps++; ++ ++ hwcfg1 >>= 2; ++ } ++ ++ if (core_if->hwcfg4.b.ded_fifo_en) { ++ num_in_eps = ++ (num_in_eps > num_tx_fifos) ? num_tx_fifos : num_in_eps; ++ } ++ ++ return num_in_eps; ++} ++ ++/** ++ * This function calculates the number of OUT EPS ++ * using GHWCFG1 and GHWCFG2 registers values ++ * ++ * @param core_if Programming view of the DWC_otg controller ++ */ ++static uint32_t calc_num_out_eps(dwc_otg_core_if_t * core_if) ++{ ++ uint32_t num_out_eps = 0; ++ uint32_t num_eps = core_if->hwcfg2.b.num_dev_ep; ++ uint32_t hwcfg1 = core_if->hwcfg1.d32 >> 2; ++ int i; ++ ++ for (i = 0; i < num_eps; ++i) { ++ if (!(hwcfg1 & 0x1)) ++ num_out_eps++; ++ ++ hwcfg1 >>= 2; ++ } ++ return num_out_eps; ++} ++ ++/** ++ * This function initializes the DWC_otg controller registers and ++ * prepares the core for device mode or host mode operation. ++ * ++ * @param core_if Programming view of the DWC_otg controller ++ * ++ */ ++void dwc_otg_core_init(dwc_otg_core_if_t * core_if) ++{ ++ int i = 0; ++ dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs; ++ dwc_otg_dev_if_t *dev_if = core_if->dev_if; ++ gahbcfg_data_t ahbcfg = {.d32 = 0 }; ++ gusbcfg_data_t usbcfg = {.d32 = 0 }; ++ gi2cctl_data_t i2cctl = {.d32 = 0 }; ++ ++ DWC_DEBUGPL(DBG_CILV, "dwc_otg_core_init(%p) regs at %p\n", ++ core_if, global_regs); ++ ++ /* Common Initialization */ ++ ++ usbcfg.d32 = dwc_read_reg32(&global_regs->gusbcfg); ++ ++ /* Program the ULPI External VBUS bit if needed */ ++ usbcfg.b.ulpi_ext_vbus_drv = ++ (core_if->core_params->phy_ulpi_ext_vbus == ++ DWC_PHY_ULPI_EXTERNAL_VBUS) ? 1 : 0; ++ ++ /* Set external TS Dline pulsing */ ++ usbcfg.b.term_sel_dl_pulse = ++ (core_if->core_params->ts_dline == 1) ? 1 : 0; ++ dwc_write_reg32(&global_regs->gusbcfg, usbcfg.d32); ++ ++ /* Reset the Controller */ ++ dwc_otg_core_reset(core_if); ++ ++ /* Initialize parameters from Hardware configuration registers. */ ++ dev_if->num_in_eps = calc_num_in_eps(core_if); ++ dev_if->num_out_eps = calc_num_out_eps(core_if); ++ ++ DWC_DEBUGPL(DBG_CIL, "num_dev_perio_in_ep=%d\n", ++ core_if->hwcfg4.b.num_dev_perio_in_ep); ++ ++ for (i = 0; i < core_if->hwcfg4.b.num_dev_perio_in_ep; i++) { ++ dev_if->perio_tx_fifo_size[i] = ++ dwc_read_reg32(&global_regs->dptxfsiz_dieptxf[i]) >> 16; ++ DWC_DEBUGPL(DBG_CIL, "Periodic Tx FIFO SZ #%d=0x%0x\n", ++ i, dev_if->perio_tx_fifo_size[i]); ++ } ++ ++ for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) { ++ dev_if->tx_fifo_size[i] = ++ dwc_read_reg32(&global_regs->dptxfsiz_dieptxf[i]) >> 16; ++ DWC_DEBUGPL(DBG_CIL, "Tx FIFO SZ #%d=0x%0x\n", ++ i, dev_if->perio_tx_fifo_size[i]); ++ } ++ ++ core_if->total_fifo_size = core_if->hwcfg3.b.dfifo_depth; ++ core_if->rx_fifo_size = dwc_read_reg32(&global_regs->grxfsiz); ++ core_if->nperio_tx_fifo_size = ++ dwc_read_reg32(&global_regs->gnptxfsiz) >> 16; ++ ++ DWC_DEBUGPL(DBG_CIL, "Total FIFO SZ=%d\n", core_if->total_fifo_size); ++ DWC_DEBUGPL(DBG_CIL, "Rx FIFO SZ=%d\n", core_if->rx_fifo_size); ++ DWC_DEBUGPL(DBG_CIL, "NP Tx FIFO SZ=%d\n", ++ core_if->nperio_tx_fifo_size); ++ ++ /* This programming sequence needs to happen in FS mode before any other ++ * programming occurs */ ++ if ((core_if->core_params->speed == DWC_SPEED_PARAM_FULL) && ++ (core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS)) { ++ /* If FS mode with FS PHY */ ++ ++ /* core_init() is now called on every switch so only call the ++ * following for the first time through. */ ++ if (!core_if->phy_init_done) { ++ core_if->phy_init_done = 1; ++ DWC_DEBUGPL(DBG_CIL, "FS_PHY detected\n"); ++ usbcfg.d32 = dwc_read_reg32(&global_regs->gusbcfg); ++ usbcfg.b.physel = 1; ++ dwc_write_reg32(&global_regs->gusbcfg, usbcfg.d32); ++ ++ /* Reset after a PHY select */ ++ dwc_otg_core_reset(core_if); ++ } ++ ++ /* Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS. Also ++ * do this on HNP Dev/Host mode switches (done in dev_init and ++ * host_init). */ ++ if (dwc_otg_is_host_mode(core_if)) { ++ init_fslspclksel(core_if); ++ } else { ++ init_devspd(core_if); ++ } ++ ++ if (core_if->core_params->i2c_enable) { ++ DWC_DEBUGPL(DBG_CIL, "FS_PHY Enabling I2c\n"); ++ /* Program GUSBCFG.OtgUtmifsSel to I2C */ ++ usbcfg.d32 = dwc_read_reg32(&global_regs->gusbcfg); ++ usbcfg.b.otgutmifssel = 1; ++ dwc_write_reg32(&global_regs->gusbcfg, usbcfg.d32); ++ ++ /* Program GI2CCTL.I2CEn */ ++ i2cctl.d32 = dwc_read_reg32(&global_regs->gi2cctl); ++ i2cctl.b.i2cdevaddr = 1; ++ i2cctl.b.i2cen = 0; ++ dwc_write_reg32(&global_regs->gi2cctl, i2cctl.d32); ++ i2cctl.b.i2cen = 1; ++ dwc_write_reg32(&global_regs->gi2cctl, i2cctl.d32); ++ } ++ ++ } /* endif speed == DWC_SPEED_PARAM_FULL */ ++ else { ++ /* High speed PHY. */ ++ if (!core_if->phy_init_done) { ++ core_if->phy_init_done = 1; ++ /* HS PHY parameters. These parameters are preserved ++ * during soft reset so only program the first time. Do ++ * a soft reset immediately after setting phyif. */ ++ usbcfg.b.ulpi_utmi_sel = core_if->core_params->phy_type; ++ if (usbcfg.b.ulpi_utmi_sel == 1) { ++ /* ULPI interface */ ++ usbcfg.b.phyif = 0; ++ usbcfg.b.ddrsel = ++ core_if->core_params->phy_ulpi_ddr; ++ } else { ++ /* UTMI+ interface */ ++ if (core_if->core_params->phy_utmi_width == 16) { ++ usbcfg.b.phyif = 1; ++ ++ } else { ++ usbcfg.b.phyif = 0; ++ } ++ ++ } ++ ++ dwc_write_reg32(&global_regs->gusbcfg, usbcfg.d32); ++ /* Reset after setting the PHY parameters */ ++ dwc_otg_core_reset(core_if); ++ } ++ } ++ ++ if ((core_if->hwcfg2.b.hs_phy_type == 2) && ++ (core_if->hwcfg2.b.fs_phy_type == 1) && ++ (core_if->core_params->ulpi_fs_ls)) { ++ DWC_DEBUGPL(DBG_CIL, "Setting ULPI FSLS\n"); ++ usbcfg.d32 = dwc_read_reg32(&global_regs->gusbcfg); ++ usbcfg.b.ulpi_fsls = 1; ++ usbcfg.b.ulpi_clk_sus_m = 1; ++ dwc_write_reg32(&global_regs->gusbcfg, usbcfg.d32); ++ } else { ++ usbcfg.d32 = dwc_read_reg32(&global_regs->gusbcfg); ++ usbcfg.b.ulpi_fsls = 0; ++ usbcfg.b.ulpi_clk_sus_m = 0; ++ dwc_write_reg32(&global_regs->gusbcfg, usbcfg.d32); ++ } ++ ++ /* Program the GAHBCFG Register. */ ++ switch (core_if->hwcfg2.b.architecture) { ++ ++ case DWC_SLAVE_ONLY_ARCH: ++ DWC_DEBUGPL(DBG_CIL, "Slave Only Mode\n"); ++ ahbcfg.b.nptxfemplvl_txfemplvl = ++ DWC_GAHBCFG_TXFEMPTYLVL_HALFEMPTY; ++ ahbcfg.b.ptxfemplvl = DWC_GAHBCFG_TXFEMPTYLVL_HALFEMPTY; ++ core_if->dma_enable = 0; ++ core_if->dma_desc_enable = 0; ++ break; ++ ++ case DWC_EXT_DMA_ARCH: ++ DWC_DEBUGPL(DBG_CIL, "External DMA Mode\n"); ++ { ++ uint8_t brst_sz = core_if->core_params->dma_burst_size; ++ ahbcfg.b.hburstlen = 0; ++ while (brst_sz > 1) { ++ ahbcfg.b.hburstlen++; ++ brst_sz >>= 1; ++ } ++ } ++ core_if->dma_enable = (core_if->core_params->dma_enable != 0); ++ core_if->dma_desc_enable = ++ (core_if->core_params->dma_desc_enable != 0); ++ break; ++ ++ case DWC_INT_DMA_ARCH: ++ DWC_DEBUGPL(DBG_CIL, "Internal DMA Mode\n"); ++ /*ahbcfg.b.hburstlen = DWC_GAHBCFG_INT_DMA_BURST_INCR; */ ++ ahbcfg.b.hburstlen = (1<<3)|(0<<0); /* WRESP=1, max 4 beats */ ++ core_if->dma_enable = (core_if->core_params->dma_enable != 0); ++ core_if->dma_desc_enable = ++ (core_if->core_params->dma_desc_enable != 0); ++ break; ++ ++ } ++ if (core_if->dma_enable) { ++ if (core_if->dma_desc_enable) { ++ DWC_PRINTF("Using Descriptor DMA mode\n"); ++ } else { ++ DWC_PRINTF("Using Buffer DMA mode\n"); ++ ++ } ++ } else { ++ DWC_PRINTF("Using Slave mode\n"); ++ core_if->dma_desc_enable = 0; ++ } ++ ++ ahbcfg.b.dmaenable = core_if->dma_enable; ++ dwc_write_reg32(&global_regs->gahbcfg, ahbcfg.d32); ++ ++ core_if->en_multiple_tx_fifo = core_if->hwcfg4.b.ded_fifo_en; ++ ++ core_if->pti_enh_enable = core_if->core_params->pti_enable != 0; ++ core_if->multiproc_int_enable = core_if->core_params->mpi_enable; ++ DWC_PRINTF("Periodic Transfer Interrupt Enhancement - %s\n", ++ ((core_if->pti_enh_enable) ? "enabled" : "disabled")); ++ DWC_PRINTF("Multiprocessor Interrupt Enhancement - %s\n", ++ ((core_if->multiproc_int_enable) ? "enabled" : "disabled")); ++ ++ /* ++ * Program the GUSBCFG register. ++ */ ++ usbcfg.d32 = dwc_read_reg32(&global_regs->gusbcfg); ++ ++ switch (core_if->hwcfg2.b.op_mode) { ++ case DWC_MODE_HNP_SRP_CAPABLE: ++ usbcfg.b.hnpcap = (core_if->core_params->otg_cap == ++ DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE); ++ usbcfg.b.srpcap = (core_if->core_params->otg_cap != ++ DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE); ++ break; ++ ++ case DWC_MODE_SRP_ONLY_CAPABLE: ++ usbcfg.b.hnpcap = 0; ++ usbcfg.b.srpcap = (core_if->core_params->otg_cap != ++ DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE); ++ break; ++ ++ case DWC_MODE_NO_HNP_SRP_CAPABLE: ++ usbcfg.b.hnpcap = 0; ++ usbcfg.b.srpcap = 0; ++ break; ++ ++ case DWC_MODE_SRP_CAPABLE_DEVICE: ++ usbcfg.b.hnpcap = 0; ++ usbcfg.b.srpcap = (core_if->core_params->otg_cap != ++ DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE); ++ break; ++ ++ case DWC_MODE_NO_SRP_CAPABLE_DEVICE: ++ usbcfg.b.hnpcap = 0; ++ usbcfg.b.srpcap = 0; ++ break; ++ ++ case DWC_MODE_SRP_CAPABLE_HOST: ++ usbcfg.b.hnpcap = 0; ++ usbcfg.b.srpcap = (core_if->core_params->otg_cap != ++ DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE); ++ break; ++ ++ case DWC_MODE_NO_SRP_CAPABLE_HOST: ++ usbcfg.b.hnpcap = 0; ++ usbcfg.b.srpcap = 0; ++ break; ++ } ++ ++ dwc_write_reg32(&global_regs->gusbcfg, usbcfg.d32); ++ ++#ifdef CONFIG_USB_DWC_OTG_LPM ++ if (core_if->core_params->lpm_enable) { ++ glpmcfg_data_t lpmcfg = {.d32 = 0 }; ++ ++ /* To enable LPM support set lpm_cap_en bit */ ++ lpmcfg.b.lpm_cap_en = 1; ++ ++ /* Make AppL1Res ACK */ ++ lpmcfg.b.appl_resp = 1; ++ ++ /* Retry 3 times */ ++ lpmcfg.b.retry_count = 3; ++ ++ dwc_modify_reg32(&core_if->core_global_regs->glpmcfg, ++ 0, lpmcfg.d32); ++ ++ } ++#endif ++ if (core_if->core_params->ic_usb_cap) { ++ gusbcfg_data_t gusbcfg = {.d32 = 0 }; ++ gusbcfg.b.ic_usb_cap = 1; ++ dwc_modify_reg32(&core_if->core_global_regs->gusbcfg, ++ 0, gusbcfg.d32); ++ } ++ ++ /* Enable common interrupts */ ++ dwc_otg_enable_common_interrupts(core_if); ++ ++ /* Do device or host intialization based on mode during PCD ++ * and HCD initialization */ ++ if (dwc_otg_is_host_mode(core_if)) { ++ DWC_DEBUGPL(DBG_ANY, "Host Mode\n"); ++ core_if->op_state = A_HOST; ++ } else { ++ DWC_DEBUGPL(DBG_ANY, "Device Mode\n"); ++ core_if->op_state = B_PERIPHERAL; ++#ifdef DWC_DEVICE_ONLY ++ dwc_otg_core_dev_init(core_if); ++#endif ++ } ++} ++ ++/** ++ * This function enables the Device mode interrupts. ++ * ++ * @param core_if Programming view of DWC_otg controller ++ */ ++void dwc_otg_enable_device_interrupts(dwc_otg_core_if_t * core_if) ++{ ++ gintmsk_data_t intr_mask = {.d32 = 0 }; ++ dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs; ++ ++ DWC_DEBUGPL(DBG_CIL, "%s()\n", __func__); ++ ++ /* Disable all interrupts. */ ++ dwc_write_reg32(&global_regs->gintmsk, 0); ++ ++ /* Clear any pending interrupts */ ++ dwc_write_reg32(&global_regs->gintsts, 0xFFFFFFFF); ++ ++ /* Enable the common interrupts */ ++ dwc_otg_enable_common_interrupts(core_if); ++ ++ /* Enable interrupts */ ++ intr_mask.b.usbreset = 1; ++ intr_mask.b.enumdone = 1; ++ ++ if (!core_if->multiproc_int_enable) { ++ intr_mask.b.inepintr = 1; ++ intr_mask.b.outepintr = 1; ++ } ++ ++ intr_mask.b.erlysuspend = 1; ++ ++ if (core_if->en_multiple_tx_fifo == 0) { ++ intr_mask.b.epmismatch = 1; ++ } ++#ifdef DWC_EN_ISOC ++ if (core_if->dma_enable) { ++ if (core_if->dma_desc_enable == 0) { ++ if (core_if->pti_enh_enable) { ++ dctl_data_t dctl = {.d32 = 0 }; ++ dctl.b.ifrmnum = 1; ++ dwc_modify_reg32(&core_if->dev_if-> ++ dev_global_regs->dctl, 0, ++ dctl.d32); ++ } else { ++ intr_mask.b.incomplisoin = 1; ++ intr_mask.b.incomplisoout = 1; ++ } ++ } ++ } else { ++ intr_mask.b.incomplisoin = 1; ++ intr_mask.b.incomplisoout = 1; ++ } ++#endif /* DWC_EN_ISOC */ ++ ++ /** @todo NGS: Should this be a module parameter? */ ++#ifdef USE_PERIODIC_EP ++ intr_mask.b.isooutdrop = 1; ++ intr_mask.b.eopframe = 1; ++ intr_mask.b.incomplisoin = 1; ++ intr_mask.b.incomplisoout = 1; ++#endif ++ ++ dwc_modify_reg32(&global_regs->gintmsk, intr_mask.d32, intr_mask.d32); ++ ++ DWC_DEBUGPL(DBG_CIL, "%s() gintmsk=%0x\n", __func__, ++ dwc_read_reg32(&global_regs->gintmsk)); ++} ++ ++/** ++ * This function initializes the DWC_otg controller registers for ++ * device mode. ++ * ++ * @param core_if Programming view of DWC_otg controller ++ * ++ */ ++void dwc_otg_core_dev_init(dwc_otg_core_if_t * core_if) ++{ ++ int i; ++ dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs; ++ dwc_otg_dev_if_t *dev_if = core_if->dev_if; ++ dwc_otg_core_params_t *params = core_if->core_params; ++ dcfg_data_t dcfg = {.d32 = 0 }; ++ grstctl_t resetctl = {.d32 = 0 }; ++ uint32_t rx_fifo_size; ++ fifosize_data_t nptxfifosize; ++ fifosize_data_t txfifosize; ++ dthrctl_data_t dthrctl; ++ fifosize_data_t ptxfifosize; ++ ++ /* Restart the Phy Clock */ ++ dwc_write_reg32(core_if->pcgcctl, 0); ++ ++ /* Device configuration register */ ++ init_devspd(core_if); ++ dcfg.d32 = dwc_read_reg32(&dev_if->dev_global_regs->dcfg); ++ dcfg.b.descdma = (core_if->dma_desc_enable) ? 1 : 0; ++ dcfg.b.perfrint = DWC_DCFG_FRAME_INTERVAL_80; ++ ++ dwc_write_reg32(&dev_if->dev_global_regs->dcfg, dcfg.d32); ++ ++ /* Configure data FIFO sizes */ ++ if (core_if->hwcfg2.b.dynamic_fifo && params->enable_dynamic_fifo) { ++ DWC_DEBUGPL(DBG_CIL, "Total FIFO Size=%d\n", ++ core_if->total_fifo_size); ++ DWC_DEBUGPL(DBG_CIL, "Rx FIFO Size=%d\n", ++ params->dev_rx_fifo_size); ++ DWC_DEBUGPL(DBG_CIL, "NP Tx FIFO Size=%d\n", ++ params->dev_nperio_tx_fifo_size); ++ ++ /* Rx FIFO */ ++ DWC_DEBUGPL(DBG_CIL, "initial grxfsiz=%08x\n", ++ dwc_read_reg32(&global_regs->grxfsiz)); ++ ++#ifdef DWC_UTE_CFI ++ core_if->pwron_rxfsiz = dwc_read_reg32(&global_regs->grxfsiz); ++ core_if->init_rxfsiz = params->dev_rx_fifo_size; ++#endif ++ rx_fifo_size = params->dev_rx_fifo_size; ++ dwc_write_reg32(&global_regs->grxfsiz, rx_fifo_size); ++ ++ DWC_DEBUGPL(DBG_CIL, "new grxfsiz=%08x\n", ++ dwc_read_reg32(&global_regs->grxfsiz)); ++ ++ /** Set Periodic Tx FIFO Mask all bits 0 */ ++ core_if->p_tx_msk = 0; ++ ++ /** Set Tx FIFO Mask all bits 0 */ ++ core_if->tx_msk = 0; ++ ++ if (core_if->en_multiple_tx_fifo == 0) { ++ /* Non-periodic Tx FIFO */ ++ DWC_DEBUGPL(DBG_CIL, "initial gnptxfsiz=%08x\n", ++ dwc_read_reg32(&global_regs->gnptxfsiz)); ++ ++ nptxfifosize.b.depth = params->dev_nperio_tx_fifo_size; ++ nptxfifosize.b.startaddr = params->dev_rx_fifo_size; ++ ++ dwc_write_reg32(&global_regs->gnptxfsiz, ++ nptxfifosize.d32); ++ ++ DWC_DEBUGPL(DBG_CIL, "new gnptxfsiz=%08x\n", ++ dwc_read_reg32(&global_regs->gnptxfsiz)); ++ ++ /**@todo NGS: Fix Periodic FIFO Sizing! */ ++ /* ++ * Periodic Tx FIFOs These FIFOs are numbered from 1 to 15. ++ * Indexes of the FIFO size module parameters in the ++ * dev_perio_tx_fifo_size array and the FIFO size registers in ++ * the dptxfsiz array run from 0 to 14. ++ */ ++ /** @todo Finish debug of this */ ++ ptxfifosize.b.startaddr = ++ nptxfifosize.b.startaddr + nptxfifosize.b.depth; ++ for (i = 0; i < core_if->hwcfg4.b.num_dev_perio_in_ep; ++ i++) { ++ ptxfifosize.b.depth = ++ params->dev_perio_tx_fifo_size[i]; ++ DWC_DEBUGPL(DBG_CIL, ++ "initial dptxfsiz_dieptxf[%d]=%08x\n", ++ i, ++ dwc_read_reg32(&global_regs-> ++ dptxfsiz_dieptxf ++ [i])); ++ dwc_write_reg32(&global_regs-> ++ dptxfsiz_dieptxf[i], ++ ptxfifosize.d32); ++ DWC_DEBUGPL(DBG_CIL, ++ "new dptxfsiz_dieptxf[%d]=%08x\n", ++ i, ++ dwc_read_reg32(&global_regs-> ++ dptxfsiz_dieptxf ++ [i])); ++ ptxfifosize.b.startaddr += ptxfifosize.b.depth; ++ } ++ } else { ++ /* ++ * Tx FIFOs These FIFOs are numbered from 1 to 15. ++ * Indexes of the FIFO size module parameters in the ++ * dev_tx_fifo_size array and the FIFO size registers in ++ * the dptxfsiz_dieptxf array run from 0 to 14. ++ */ ++ ++ /* Non-periodic Tx FIFO */ ++ DWC_DEBUGPL(DBG_CIL, "initial gnptxfsiz=%08x\n", ++ dwc_read_reg32(&global_regs->gnptxfsiz)); ++ ++#ifdef DWC_UTE_CFI ++ core_if->pwron_gnptxfsiz = ++ (dwc_read_reg32(&global_regs->gnptxfsiz) >> 16); ++ core_if->init_gnptxfsiz = ++ params->dev_nperio_tx_fifo_size; ++#endif ++ nptxfifosize.b.depth = params->dev_nperio_tx_fifo_size; ++ nptxfifosize.b.startaddr = params->dev_rx_fifo_size; ++ ++ dwc_write_reg32(&global_regs->gnptxfsiz, ++ nptxfifosize.d32); ++ ++ DWC_DEBUGPL(DBG_CIL, "new gnptxfsiz=%08x\n", ++ dwc_read_reg32(&global_regs->gnptxfsiz)); ++ ++ txfifosize.b.startaddr = ++ nptxfifosize.b.startaddr + nptxfifosize.b.depth; ++ ++ for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) { ++ ++ txfifosize.b.depth = ++ params->dev_tx_fifo_size[i]; ++ ++ DWC_DEBUGPL(DBG_CIL, ++ "initial dptxfsiz_dieptxf[%d]=%08x\n", ++ i, ++ dwc_read_reg32(&global_regs-> ++ dptxfsiz_dieptxf ++ [i])); ++ ++#ifdef DWC_UTE_CFI ++ core_if->pwron_txfsiz[i] = ++ (dwc_read_reg32 ++ (&global_regs->dptxfsiz_dieptxf[i]) >> 16); ++ core_if->init_txfsiz[i] = ++ params->dev_tx_fifo_size[i]; ++#endif ++ dwc_write_reg32(&global_regs-> ++ dptxfsiz_dieptxf[i], ++ txfifosize.d32); ++ ++ DWC_DEBUGPL(DBG_CIL, ++ "new dptxfsiz_dieptxf[%d]=%08x\n", ++ i, ++ dwc_read_reg32(&global_regs-> ++ dptxfsiz_dieptxf ++ [i])); ++ ++ txfifosize.b.startaddr += txfifosize.b.depth; ++ } ++ } ++ } ++ /* Flush the FIFOs */ ++ dwc_otg_flush_tx_fifo(core_if, 0x10); /* all Tx FIFOs */ ++ dwc_otg_flush_rx_fifo(core_if); ++ ++ /* Flush the Learning Queue. */ ++ resetctl.b.intknqflsh = 1; ++ dwc_write_reg32(&core_if->core_global_regs->grstctl, resetctl.d32); ++ ++ /* Clear all pending Device Interrupts */ ++ /** @todo - if the condition needed to be checked ++ * or in any case all pending interrutps should be cleared? ++ */ ++ if (core_if->multiproc_int_enable) { ++ for (i = 0; i < core_if->dev_if->num_in_eps; ++i) { ++ dwc_write_reg32(&dev_if->dev_global_regs-> ++ diepeachintmsk[i], 0); ++ } ++ ++ for (i = 0; i < core_if->dev_if->num_out_eps; ++i) { ++ dwc_write_reg32(&dev_if->dev_global_regs-> ++ doepeachintmsk[i], 0); ++ } ++ ++ dwc_write_reg32(&dev_if->dev_global_regs->deachint, 0xFFFFFFFF); ++ dwc_write_reg32(&dev_if->dev_global_regs->deachintmsk, 0); ++ } else { ++ dwc_write_reg32(&dev_if->dev_global_regs->diepmsk, 0); ++ dwc_write_reg32(&dev_if->dev_global_regs->doepmsk, 0); ++ dwc_write_reg32(&dev_if->dev_global_regs->daint, 0xFFFFFFFF); ++ dwc_write_reg32(&dev_if->dev_global_regs->daintmsk, 0); ++ } ++ ++ for (i = 0; i <= dev_if->num_in_eps; i++) { ++ depctl_data_t depctl; ++ depctl.d32 = dwc_read_reg32(&dev_if->in_ep_regs[i]->diepctl); ++ if (depctl.b.epena) { ++ depctl.d32 = 0; ++ depctl.b.epdis = 1; ++ depctl.b.snak = 1; ++ } else { ++ depctl.d32 = 0; ++ } ++ ++ dwc_write_reg32(&dev_if->in_ep_regs[i]->diepctl, depctl.d32); ++ ++ dwc_write_reg32(&dev_if->in_ep_regs[i]->dieptsiz, 0); ++ dwc_write_reg32(&dev_if->in_ep_regs[i]->diepdma, 0); ++ dwc_write_reg32(&dev_if->in_ep_regs[i]->diepint, 0xFF); ++ } ++ ++ for (i = 0; i <= dev_if->num_out_eps; i++) { ++ depctl_data_t depctl; ++ depctl.d32 = dwc_read_reg32(&dev_if->out_ep_regs[i]->doepctl); ++ if (depctl.b.epena) { ++ depctl.d32 = 0; ++ depctl.b.epdis = 1; ++ depctl.b.snak = 1; ++ } else { ++ depctl.d32 = 0; ++ } ++ ++ dwc_write_reg32(&dev_if->out_ep_regs[i]->doepctl, depctl.d32); ++ ++ dwc_write_reg32(&dev_if->out_ep_regs[i]->doeptsiz, 0); ++ dwc_write_reg32(&dev_if->out_ep_regs[i]->doepdma, 0); ++ dwc_write_reg32(&dev_if->out_ep_regs[i]->doepint, 0xFF); ++ } ++ ++ if (core_if->en_multiple_tx_fifo && core_if->dma_enable) { ++ dev_if->non_iso_tx_thr_en = params->thr_ctl & 0x1; ++ dev_if->iso_tx_thr_en = (params->thr_ctl >> 1) & 0x1; ++ dev_if->rx_thr_en = (params->thr_ctl >> 2) & 0x1; ++ ++ dev_if->rx_thr_length = params->rx_thr_length; ++ dev_if->tx_thr_length = params->tx_thr_length; ++ ++ dev_if->setup_desc_index = 0; ++ ++ dthrctl.d32 = 0; ++ dthrctl.b.non_iso_thr_en = dev_if->non_iso_tx_thr_en; ++ dthrctl.b.iso_thr_en = dev_if->iso_tx_thr_en; ++ dthrctl.b.tx_thr_len = dev_if->tx_thr_length; ++ dthrctl.b.rx_thr_en = dev_if->rx_thr_en; ++ dthrctl.b.rx_thr_len = dev_if->rx_thr_length; ++ dthrctl.b.ahb_thr_ratio = params->ahb_thr_ratio; ++ ++ dwc_write_reg32(&dev_if->dev_global_regs->dtknqr3_dthrctl, ++ dthrctl.d32); ++ ++ DWC_DEBUGPL(DBG_CIL, ++ "Non ISO Tx Thr - %d\nISO Tx Thr - %d\nRx Thr - %d\nTx Thr Len - %d\nRx Thr Len - %d\n", ++ dthrctl.b.non_iso_thr_en, dthrctl.b.iso_thr_en, ++ dthrctl.b.rx_thr_en, dthrctl.b.tx_thr_len, ++ dthrctl.b.rx_thr_len); ++ ++ } ++ ++ dwc_otg_enable_device_interrupts(core_if); ++ ++ { ++ diepmsk_data_t msk = {.d32 = 0 }; ++ msk.b.txfifoundrn = 1; ++ if (core_if->multiproc_int_enable) { ++ dwc_modify_reg32(&dev_if->dev_global_regs-> ++ diepeachintmsk[0], msk.d32, msk.d32); ++ } else { ++ dwc_modify_reg32(&dev_if->dev_global_regs->diepmsk, ++ msk.d32, msk.d32); ++ } ++ } ++ ++ if (core_if->multiproc_int_enable) { ++ /* Set NAK on Babble */ ++ dctl_data_t dctl = {.d32 = 0 }; ++ dctl.b.nakonbble = 1; ++ dwc_modify_reg32(&dev_if->dev_global_regs->dctl, 0, dctl.d32); ++ } ++} ++ ++/** ++ * This function enables the Host mode interrupts. ++ * ++ * @param core_if Programming view of DWC_otg controller ++ */ ++void dwc_otg_enable_host_interrupts(dwc_otg_core_if_t * core_if) ++{ ++ dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs; ++ gintmsk_data_t intr_mask = {.d32 = 0 }; ++ ++ DWC_DEBUGPL(DBG_CIL, "%s(%p)\n", __func__, core_if); ++ ++ /* Disable all interrupts. */ ++ dwc_write_reg32(&global_regs->gintmsk, 0); ++ ++ /* Clear any pending interrupts. */ ++ dwc_write_reg32(&global_regs->gintsts, 0xFFFFFFFF); ++ ++ /* Enable the common interrupts */ ++ dwc_otg_enable_common_interrupts(core_if); ++ ++ /* ++ * Enable host mode interrupts without disturbing common ++ * interrupts. ++ */ ++ ++ /* Do not need sof interrupt for Descriptor DMA*/ ++ if (!core_if->dma_desc_enable) ++ intr_mask.b.sofintr = 1; ++ intr_mask.b.portintr = 1; ++ intr_mask.b.hcintr = 1; ++ ++ dwc_modify_reg32(&global_regs->gintmsk, intr_mask.d32, intr_mask.d32); ++} ++ ++/** ++ * This function disables the Host Mode interrupts. ++ * ++ * @param core_if Programming view of DWC_otg controller ++ */ ++void dwc_otg_disable_host_interrupts(dwc_otg_core_if_t * core_if) ++{ ++ dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs; ++ gintmsk_data_t intr_mask = {.d32 = 0 }; ++ ++ DWC_DEBUGPL(DBG_CILV, "%s()\n", __func__); ++ ++ /* ++ * Disable host mode interrupts without disturbing common ++ * interrupts. ++ */ ++ intr_mask.b.sofintr = 1; ++ intr_mask.b.portintr = 1; ++ intr_mask.b.hcintr = 1; ++ intr_mask.b.ptxfempty = 1; ++ intr_mask.b.nptxfempty = 1; ++ ++ dwc_modify_reg32(&global_regs->gintmsk, intr_mask.d32, 0); ++} ++ ++/** ++ * This function initializes the DWC_otg controller registers for ++ * host mode. ++ * ++ * This function flushes the Tx and Rx FIFOs and it flushes any entries in the ++ * request queues. Host channels are reset to ensure that they are ready for ++ * performing transfers. ++ * ++ * @param core_if Programming view of DWC_otg controller ++ * ++ */ ++void dwc_otg_core_host_init(dwc_otg_core_if_t * core_if) ++{ ++ dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs; ++ dwc_otg_host_if_t *host_if = core_if->host_if; ++ dwc_otg_core_params_t *params = core_if->core_params; ++ hprt0_data_t hprt0 = {.d32 = 0 }; ++ fifosize_data_t nptxfifosize; ++ fifosize_data_t ptxfifosize; ++ int i; ++ hcchar_data_t hcchar; ++ hcfg_data_t hcfg; ++ dwc_otg_hc_regs_t *hc_regs; ++ int num_channels; ++ gotgctl_data_t gotgctl = {.d32 = 0 }; ++ ++ DWC_DEBUGPL(DBG_CILV, "%s(%p)\n", __func__, core_if); ++ ++ /* Restart the Phy Clock */ ++ dwc_write_reg32(core_if->pcgcctl, 0); ++ ++ /* Initialize Host Configuration Register */ ++ init_fslspclksel(core_if); ++ if (core_if->core_params->speed == DWC_SPEED_PARAM_FULL) { ++ hcfg.d32 = dwc_read_reg32(&host_if->host_global_regs->hcfg); ++ hcfg.b.fslssupp = 1; ++ dwc_write_reg32(&host_if->host_global_regs->hcfg, hcfg.d32); ++ ++ } ++ ++ if (core_if->core_params->dma_desc_enable) { ++ uint8_t op_mode = core_if->hwcfg2.b.op_mode; ++ if (!(core_if->hwcfg4.b.desc_dma && (core_if->snpsid >= OTG_CORE_REV_2_90a) && ++ ((op_mode == DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG) || ++ (op_mode == DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG) || ++ (op_mode == DWC_HWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE_OTG) || ++ (op_mode == DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST) || ++ (op_mode == DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST)))) { ++ ++ DWC_ERROR("Host can't operate in Descriptor DMA mode.\n" ++ "Either core version is below 2.90a or " ++ "GHWCFG2, GHWCFG4 registers' values do not allow Descriptor DMA in host mode.\n" ++ "To run the driver in Buffer DMA host mode set dma_desc_enable " ++ "module parameter to 0.\n"); ++ return; ++ } ++ hcfg.d32 = dwc_read_reg32(&host_if->host_global_regs->hcfg); ++ hcfg.b.descdma = 1; ++ dwc_write_reg32(&host_if->host_global_regs->hcfg, hcfg.d32); ++ } ++ ++ /* Configure data FIFO sizes */ ++ if (core_if->hwcfg2.b.dynamic_fifo && params->enable_dynamic_fifo) { ++ DWC_DEBUGPL(DBG_CIL, "Total FIFO Size=%d\n", ++ core_if->total_fifo_size); ++ DWC_DEBUGPL(DBG_CIL, "Rx FIFO Size=%d\n", ++ params->host_rx_fifo_size); ++ DWC_DEBUGPL(DBG_CIL, "NP Tx FIFO Size=%d\n", ++ params->host_nperio_tx_fifo_size); ++ DWC_DEBUGPL(DBG_CIL, "P Tx FIFO Size=%d\n", ++ params->host_perio_tx_fifo_size); ++ ++ /* Rx FIFO */ ++ DWC_DEBUGPL(DBG_CIL, "initial grxfsiz=%08x\n", ++ dwc_read_reg32(&global_regs->grxfsiz)); ++ dwc_write_reg32(&global_regs->grxfsiz, ++ params->host_rx_fifo_size); ++ DWC_DEBUGPL(DBG_CIL, "new grxfsiz=%08x\n", ++ dwc_read_reg32(&global_regs->grxfsiz)); ++ ++ /* Non-periodic Tx FIFO */ ++ DWC_DEBUGPL(DBG_CIL, "initial gnptxfsiz=%08x\n", ++ dwc_read_reg32(&global_regs->gnptxfsiz)); ++ nptxfifosize.b.depth = params->host_nperio_tx_fifo_size; ++ nptxfifosize.b.startaddr = params->host_rx_fifo_size; ++ dwc_write_reg32(&global_regs->gnptxfsiz, nptxfifosize.d32); ++ DWC_DEBUGPL(DBG_CIL, "new gnptxfsiz=%08x\n", ++ dwc_read_reg32(&global_regs->gnptxfsiz)); ++ ++ /* Periodic Tx FIFO */ ++ DWC_DEBUGPL(DBG_CIL, "initial hptxfsiz=%08x\n", ++ dwc_read_reg32(&global_regs->hptxfsiz)); ++ ptxfifosize.b.depth = params->host_perio_tx_fifo_size; ++ ptxfifosize.b.startaddr = ++ nptxfifosize.b.startaddr + nptxfifosize.b.depth; ++ dwc_write_reg32(&global_regs->hptxfsiz, ptxfifosize.d32); ++ DWC_DEBUGPL(DBG_CIL, "new hptxfsiz=%08x\n", ++ dwc_read_reg32(&global_regs->hptxfsiz)); ++ } ++ ++ /* Clear Host Set HNP Enable in the OTG Control Register */ ++ gotgctl.b.hstsethnpen = 1; ++ dwc_modify_reg32(&global_regs->gotgctl, gotgctl.d32, 0); ++ ++ /* Make sure the FIFOs are flushed. */ ++ dwc_otg_flush_tx_fifo(core_if, 0x10 /* all Tx FIFOs */ ); ++ dwc_otg_flush_rx_fifo(core_if); ++ ++ if(!core_if->core_params->dma_desc_enable) { ++ /* Flush out any leftover queued requests. */ ++ num_channels = core_if->core_params->host_channels; ++ ++ for (i = 0; i < num_channels; i++) { ++ hc_regs = core_if->host_if->hc_regs[i]; ++ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); ++ hcchar.b.chen = 0; ++ hcchar.b.chdis = 1; ++ hcchar.b.epdir = 0; ++ dwc_write_reg32(&hc_regs->hcchar, hcchar.d32); ++ } ++ ++ /* Halt all channels to put them into a known state. */ ++ for (i = 0; i < num_channels; i++) { ++ int count = 0; ++ hc_regs = core_if->host_if->hc_regs[i]; ++ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); ++ hcchar.b.chen = 1; ++ hcchar.b.chdis = 1; ++ hcchar.b.epdir = 0; ++ dwc_write_reg32(&hc_regs->hcchar, hcchar.d32); ++ DWC_DEBUGPL(DBG_HCDV, "%s: Halt channel %d regs %p\n", __func__, i, hc_regs); ++ do { ++ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); ++ if (++count > 1000) { ++ DWC_ERROR ++ ("%s: Unable to clear halt on channel %d (timeout HCCHAR 0x%X @%p)\n", ++ __func__, i, hcchar.d32, &hc_regs->hcchar); ++ break; ++ } ++ dwc_udelay(1); ++ } while (hcchar.b.chen); ++ } ++ } ++ ++ /* Turn on the vbus power. */ ++ DWC_PRINTF("Init: Port Power? op_state=%d\n", core_if->op_state); ++ if (core_if->op_state == A_HOST) { ++ hprt0.d32 = dwc_otg_read_hprt0(core_if); ++ DWC_PRINTF("Init: Power Port (%d)\n", hprt0.b.prtpwr); ++ if (hprt0.b.prtpwr == 0) { ++ hprt0.b.prtpwr = 1; ++ dwc_write_reg32(host_if->hprt0, hprt0.d32); ++ } ++ } ++ ++ dwc_otg_enable_host_interrupts(core_if); ++} ++ ++/** ++ * Prepares a host channel for transferring packets to/from a specific ++ * endpoint. The HCCHARn register is set up with the characteristics specified ++ * in _hc. Host channel interrupts that may need to be serviced while this ++ * transfer is in progress are enabled. ++ * ++ * @param core_if Programming view of DWC_otg controller ++ * @param hc Information needed to initialize the host channel ++ */ ++void dwc_otg_hc_init(dwc_otg_core_if_t * core_if, dwc_hc_t * hc) ++{ ++ uint32_t intr_enable; ++ hcintmsk_data_t hc_intr_mask; ++ gintmsk_data_t gintmsk = {.d32 = 0 }; ++ hcchar_data_t hcchar; ++ hcsplt_data_t hcsplt; ++ ++ uint8_t hc_num = hc->hc_num; ++ dwc_otg_host_if_t *host_if = core_if->host_if; ++ dwc_otg_hc_regs_t *hc_regs = host_if->hc_regs[hc_num]; ++ ++ /* Clear old interrupt conditions for this host channel. */ ++ hc_intr_mask.d32 = 0xFFFFFFFF; ++ hc_intr_mask.b.reserved14_31 = 0; ++ dwc_write_reg32(&hc_regs->hcint, hc_intr_mask.d32); ++ ++ /* Enable channel interrupts required for this transfer. */ ++ hc_intr_mask.d32 = 0; ++ hc_intr_mask.b.chhltd = 1; ++ if (core_if->dma_enable) { ++ /* For Descriptor DMA mode core halts the channel on AHB error. Interrupt is not required */ ++ if (!core_if->dma_desc_enable) ++ hc_intr_mask.b.ahberr = 1; ++ else { ++ if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC) ++ hc_intr_mask.b.xfercompl = 1; ++ } ++ ++ if (hc->error_state && !hc->do_split && ++ hc->ep_type != DWC_OTG_EP_TYPE_ISOC) { ++ hc_intr_mask.b.ack = 1; ++ if (hc->ep_is_in) { ++ hc_intr_mask.b.datatglerr = 1; ++ if (hc->ep_type != DWC_OTG_EP_TYPE_INTR) { ++ hc_intr_mask.b.nak = 1; ++ } ++ } ++ } ++ } else { ++ switch (hc->ep_type) { ++ case DWC_OTG_EP_TYPE_CONTROL: ++ case DWC_OTG_EP_TYPE_BULK: ++ hc_intr_mask.b.xfercompl = 1; ++ hc_intr_mask.b.stall = 1; ++ hc_intr_mask.b.xacterr = 1; ++ hc_intr_mask.b.datatglerr = 1; ++ if (hc->ep_is_in) { ++ hc_intr_mask.b.bblerr = 1; ++ } else { ++ hc_intr_mask.b.nak = 1; ++ hc_intr_mask.b.nyet = 1; ++ if (hc->do_ping) { ++ hc_intr_mask.b.ack = 1; ++ } ++ } ++ ++ if (hc->do_split) { ++ hc_intr_mask.b.nak = 1; ++ if (hc->complete_split) { ++ hc_intr_mask.b.nyet = 1; ++ } else { ++ hc_intr_mask.b.ack = 1; ++ } ++ } ++ ++ if (hc->error_state) { ++ hc_intr_mask.b.ack = 1; ++ } ++ break; ++ case DWC_OTG_EP_TYPE_INTR: ++ hc_intr_mask.b.xfercompl = 1; ++ hc_intr_mask.b.nak = 1; ++ hc_intr_mask.b.stall = 1; ++ hc_intr_mask.b.xacterr = 1; ++ hc_intr_mask.b.datatglerr = 1; ++ hc_intr_mask.b.frmovrun = 1; ++ ++ if (hc->ep_is_in) { ++ hc_intr_mask.b.bblerr = 1; ++ } ++ if (hc->error_state) { ++ hc_intr_mask.b.ack = 1; ++ } ++ if (hc->do_split) { ++ if (hc->complete_split) { ++ hc_intr_mask.b.nyet = 1; ++ } else { ++ hc_intr_mask.b.ack = 1; ++ } ++ } ++ break; ++ case DWC_OTG_EP_TYPE_ISOC: ++ hc_intr_mask.b.xfercompl = 1; ++ hc_intr_mask.b.frmovrun = 1; ++ hc_intr_mask.b.ack = 1; ++ ++ if (hc->ep_is_in) { ++ hc_intr_mask.b.xacterr = 1; ++ hc_intr_mask.b.bblerr = 1; ++ } ++ break; ++ } ++ } ++ dwc_write_reg32(&hc_regs->hcintmsk, hc_intr_mask.d32); ++ ++ /* Enable the top level host channel interrupt. */ ++ intr_enable = (1 << hc_num); ++ dwc_modify_reg32(&host_if->host_global_regs->haintmsk, 0, intr_enable); ++ ++ /* Make sure host channel interrupts are enabled. */ ++ gintmsk.b.hcintr = 1; ++ dwc_modify_reg32(&core_if->core_global_regs->gintmsk, 0, gintmsk.d32); ++ ++ /* ++ * Program the HCCHARn register with the endpoint characteristics for ++ * the current transfer. ++ */ ++ hcchar.d32 = 0; ++ hcchar.b.devaddr = hc->dev_addr; ++ hcchar.b.epnum = hc->ep_num; ++ hcchar.b.epdir = hc->ep_is_in; ++ hcchar.b.lspddev = (hc->speed == DWC_OTG_EP_SPEED_LOW); ++ hcchar.b.eptype = hc->ep_type; ++ hcchar.b.mps = hc->max_packet; ++ ++ dwc_write_reg32(&host_if->hc_regs[hc_num]->hcchar, hcchar.d32); ++ ++ DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num); ++ DWC_DEBUGPL(DBG_HCDV, " Dev Addr: %d\n", hcchar.b.devaddr); ++ DWC_DEBUGPL(DBG_HCDV, " Ep Num: %d\n", hcchar.b.epnum); ++ DWC_DEBUGPL(DBG_HCDV, " Is In: %d\n", hcchar.b.epdir); ++ DWC_DEBUGPL(DBG_HCDV, " Is Low Speed: %d\n", hcchar.b.lspddev); ++ DWC_DEBUGPL(DBG_HCDV, " Ep Type: %d\n", hcchar.b.eptype); ++ DWC_DEBUGPL(DBG_HCDV, " Max Pkt: %d\n", hcchar.b.mps); ++ DWC_DEBUGPL(DBG_HCDV, " Multi Cnt: %d\n", hcchar.b.multicnt); ++ ++ /* ++ * Program the HCSPLIT register for SPLITs ++ */ ++ hcsplt.d32 = 0; ++ if (hc->do_split) { ++ DWC_DEBUGPL(DBG_HCDV, "Programming HC %d with split --> %s\n", ++ hc->hc_num, ++ hc->complete_split ? "CSPLIT" : "SSPLIT"); ++ hcsplt.b.compsplt = hc->complete_split; ++ hcsplt.b.xactpos = hc->xact_pos; ++ hcsplt.b.hubaddr = hc->hub_addr; ++ hcsplt.b.prtaddr = hc->port_addr; ++ DWC_DEBUGPL(DBG_HCDV, " comp split %d\n", hc->complete_split); ++ DWC_DEBUGPL(DBG_HCDV, " xact pos %d\n", hc->xact_pos); ++ DWC_DEBUGPL(DBG_HCDV, " hub addr %d\n", hc->hub_addr); ++ DWC_DEBUGPL(DBG_HCDV, " port addr %d\n", hc->port_addr); ++ DWC_DEBUGPL(DBG_HCDV, " is_in %d\n", hc->ep_is_in); ++ DWC_DEBUGPL(DBG_HCDV, " Max Pkt: %d\n", hcchar.b.mps); ++ DWC_DEBUGPL(DBG_HCDV, " xferlen: %d\n", hc->xfer_len); ++ } ++ dwc_write_reg32(&host_if->hc_regs[hc_num]->hcsplt, hcsplt.d32); ++ ++} ++ ++/** ++ * Attempts to halt a host channel. This function should only be called in ++ * Slave mode or to abort a transfer in either Slave mode or DMA mode. Under ++ * normal circumstances in DMA mode, the controller halts the channel when the ++ * transfer is complete or a condition occurs that requires application ++ * intervention. ++ * ++ * In slave mode, checks for a free request queue entry, then sets the Channel ++ * Enable and Channel Disable bits of the Host Channel Characteristics ++ * register of the specified channel to intiate the halt. If there is no free ++ * request queue entry, sets only the Channel Disable bit of the HCCHARn ++ * register to flush requests for this channel. In the latter case, sets a ++ * flag to indicate that the host channel needs to be halted when a request ++ * queue slot is open. ++ * ++ * In DMA mode, always sets the Channel Enable and Channel Disable bits of the ++ * HCCHARn register. The controller ensures there is space in the request ++ * queue before submitting the halt request. ++ * ++ * Some time may elapse before the core flushes any posted requests for this ++ * host channel and halts. The Channel Halted interrupt handler completes the ++ * deactivation of the host channel. ++ * ++ * @param core_if Controller register interface. ++ * @param hc Host channel to halt. ++ * @param halt_status Reason for halting the channel. ++ */ ++void dwc_otg_hc_halt(dwc_otg_core_if_t * core_if, ++ dwc_hc_t * hc, dwc_otg_halt_status_e halt_status) ++{ ++ gnptxsts_data_t nptxsts; ++ hptxsts_data_t hptxsts; ++ hcchar_data_t hcchar; ++ dwc_otg_hc_regs_t *hc_regs; ++ dwc_otg_core_global_regs_t *global_regs; ++ dwc_otg_host_global_regs_t *host_global_regs; ++ ++ DWC_DEBUGPL(DBG_HW2937, " dwc_otg_hc_halt(%d)\n", hc->hc_num); ++ hc_regs = core_if->host_if->hc_regs[hc->hc_num]; ++ global_regs = core_if->core_global_regs; ++ host_global_regs = core_if->host_if->host_global_regs; ++ ++ DWC_ASSERT(!(halt_status == DWC_OTG_HC_XFER_NO_HALT_STATUS), ++ "halt_status = %d\n", halt_status); ++ ++ if (halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE || ++ halt_status == DWC_OTG_HC_XFER_AHB_ERR) { ++ /* ++ * Disable all channel interrupts except Ch Halted. The QTD ++ * and QH state associated with this transfer has been cleared ++ * (in the case of URB_DEQUEUE), so the channel needs to be ++ * shut down carefully to prevent crashes. ++ */ ++ hcintmsk_data_t hcintmsk; ++ hcintmsk.d32 = 0; ++ hcintmsk.b.chhltd = 1; ++ dwc_write_reg32(&hc_regs->hcintmsk, hcintmsk.d32); ++ ++ /* ++ * Make sure no other interrupts besides halt are currently ++ * pending. Handling another interrupt could cause a crash due ++ * to the QTD and QH state. ++ */ ++ dwc_write_reg32(&hc_regs->hcint, ~hcintmsk.d32); ++ ++ /* ++ * Make sure the halt status is set to URB_DEQUEUE or AHB_ERR ++ * even if the channel was already halted for some other ++ * reason. ++ */ ++ hc->halt_status = halt_status; ++ ++ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); ++ if (hcchar.b.chen == 0) { ++ /* ++ * The channel is either already halted or it hasn't ++ * started yet. In DMA mode, the transfer may halt if ++ * it finishes normally or a condition occurs that ++ * requires driver intervention. Don't want to halt ++ * the channel again. In either Slave or DMA mode, ++ * it's possible that the transfer has been assigned ++ * to a channel, but not started yet when an URB is ++ * dequeued. Don't want to halt a channel that hasn't ++ * started yet. ++ */ ++ return; ++ } ++ } ++ if (hc->halt_pending) { ++ /* ++ * A halt has already been issued for this channel. This might ++ * happen when a transfer is aborted by a higher level in ++ * the stack. ++ */ ++#ifdef DEBUG ++ DWC_PRINTF ++ ("*** %s: Channel %d, _hc->halt_pending already set ***\n", ++ __func__, hc->hc_num); ++ ++#endif ++ return; ++ } ++ ++ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); ++ ++ /* No need to set the bit in DDMA for disabling the channel */ ++ //TODO check it everywhere channel is disabled ++ if(!core_if->core_params->dma_desc_enable) ++ hcchar.b.chen = 1; ++ hcchar.b.chdis = 1; ++ ++ if (!core_if->dma_enable) { ++ /* Check for space in the request queue to issue the halt. */ ++ if (hc->ep_type == DWC_OTG_EP_TYPE_CONTROL || ++ hc->ep_type == DWC_OTG_EP_TYPE_BULK) { ++ nptxsts.d32 = dwc_read_reg32(&global_regs->gnptxsts); ++ if (nptxsts.b.nptxqspcavail == 0) { ++ hcchar.b.chen = 0; ++ } ++ } else { ++ hptxsts.d32 = ++ dwc_read_reg32(&host_global_regs->hptxsts); ++ if ((hptxsts.b.ptxqspcavail == 0) ++ || (core_if->queuing_high_bandwidth)) { ++ hcchar.b.chen = 0; ++ } ++ } ++ } ++ dwc_write_reg32(&hc_regs->hcchar, hcchar.d32); ++ ++ hc->halt_status = halt_status; ++ ++ if (hcchar.b.chen) { ++ hc->halt_pending = 1; ++ hc->halt_on_queue = 0; ++ } else { ++ hc->halt_on_queue = 1; ++ } ++ ++ DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num); ++ DWC_DEBUGPL(DBG_HCDV, " hcchar: 0x%08x\n", hcchar.d32); ++ DWC_DEBUGPL(DBG_HCDV, " halt_pending: %d\n", hc->halt_pending); ++ DWC_DEBUGPL(DBG_HCDV, " halt_on_queue: %d\n", hc->halt_on_queue); ++ DWC_DEBUGPL(DBG_HCDV, " halt_status: %d\n", hc->halt_status); ++ ++ return; ++} ++ ++/** ++ * Clears the transfer state for a host channel. This function is normally ++ * called after a transfer is done and the host channel is being released. ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ * @param hc Identifies the host channel to clean up. ++ */ ++void dwc_otg_hc_cleanup(dwc_otg_core_if_t * core_if, dwc_hc_t * hc) ++{ ++ dwc_otg_hc_regs_t *hc_regs; ++ ++ hc->xfer_started = 0; ++ ++ /* ++ * Clear channel interrupt enables and any unhandled channel interrupt ++ * conditions. ++ */ ++ hc_regs = core_if->host_if->hc_regs[hc->hc_num]; ++ dwc_write_reg32(&hc_regs->hcintmsk, 0); ++ dwc_write_reg32(&hc_regs->hcint, 0xFFFFFFFF); ++#ifdef DEBUG ++ DWC_TIMER_CANCEL(core_if->hc_xfer_timer[hc->hc_num]); ++#endif ++} ++ ++/** ++ * Sets the channel property that indicates in which frame a periodic transfer ++ * should occur. This is always set to the _next_ frame. This function has no ++ * effect on non-periodic transfers. ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ * @param hc Identifies the host channel to set up and its properties. ++ * @param hcchar Current value of the HCCHAR register for the specified host ++ * channel. ++ */ ++static inline void hc_set_even_odd_frame(dwc_otg_core_if_t * core_if, ++ dwc_hc_t * hc, hcchar_data_t * hcchar) ++{ ++ if (hc->ep_type == DWC_OTG_EP_TYPE_INTR || ++ hc->ep_type == DWC_OTG_EP_TYPE_ISOC) { ++ hfnum_data_t hfnum; ++ hfnum.d32 = ++ dwc_read_reg32(&core_if->host_if->host_global_regs->hfnum); ++ ++ /* 1 if _next_ frame is odd, 0 if it's even */ ++ hcchar->b.oddfrm = (hfnum.b.frnum & 0x1) ? 0 : 1; ++#ifdef DEBUG ++ if (hc->ep_type == DWC_OTG_EP_TYPE_INTR && hc->do_split ++ && !hc->complete_split) { ++ switch (hfnum.b.frnum & 0x7) { ++ case 7: ++ core_if->hfnum_7_samples++; ++ core_if->hfnum_7_frrem_accum += hfnum.b.frrem; ++ break; ++ case 0: ++ core_if->hfnum_0_samples++; ++ core_if->hfnum_0_frrem_accum += hfnum.b.frrem; ++ break; ++ default: ++ core_if->hfnum_other_samples++; ++ core_if->hfnum_other_frrem_accum += ++ hfnum.b.frrem; ++ break; ++ } ++ } ++#endif ++ } ++} ++ ++#ifdef DEBUG ++void hc_xfer_timeout(void *ptr) ++{ ++ hc_xfer_info_t *xfer_info = (hc_xfer_info_t *) ptr; ++ int hc_num = xfer_info->hc->hc_num; ++ DWC_WARN("%s: timeout on channel %d\n", __func__, hc_num); ++ DWC_WARN(" start_hcchar_val 0x%08x\n", ++ xfer_info->core_if->start_hcchar_val[hc_num]); ++} ++#endif ++ ++void set_pid_isoc(dwc_hc_t * hc) ++{ ++ /* Set up the initial PID for the transfer. */ ++ if (hc->speed == DWC_OTG_EP_SPEED_HIGH) { ++ if (hc->ep_is_in) { ++ if (hc->multi_count == 1) { ++ hc->data_pid_start = ++ DWC_OTG_HC_PID_DATA0; ++ } else if (hc->multi_count == 2) { ++ hc->data_pid_start = ++ DWC_OTG_HC_PID_DATA1; ++ } else { ++ hc->data_pid_start = ++ DWC_OTG_HC_PID_DATA2; ++ } ++ } else { ++ if (hc->multi_count == 1) { ++ hc->data_pid_start = ++ DWC_OTG_HC_PID_DATA0; ++ } else { ++ hc->data_pid_start = ++ DWC_OTG_HC_PID_MDATA; ++ } ++ } ++ } else { ++ hc->data_pid_start = DWC_OTG_HC_PID_DATA0; ++ } ++} ++ ++/** ++ * This function does the setup for a data transfer for a host channel and ++ * starts the transfer. May be called in either Slave mode or DMA mode. In ++ * Slave mode, the caller must ensure that there is sufficient space in the ++ * request queue and Tx Data FIFO. ++ * ++ * For an OUT transfer in Slave mode, it loads a data packet into the ++ * appropriate FIFO. If necessary, additional data packets will be loaded in ++ * the Host ISR. ++ * ++ * For an IN transfer in Slave mode, a data packet is requested. The data ++ * packets are unloaded from the Rx FIFO in the Host ISR. If necessary, ++ * additional data packets are requested in the Host ISR. ++ * ++ * For a PING transfer in Slave mode, the Do Ping bit is set in the HCTSIZ ++ * register along with a packet count of 1 and the channel is enabled. This ++ * causes a single PING transaction to occur. Other fields in HCTSIZ are ++ * simply set to 0 since no data transfer occurs in this case. ++ * ++ * For a PING transfer in DMA mode, the HCTSIZ register is initialized with ++ * all the information required to perform the subsequent data transfer. In ++ * addition, the Do Ping bit is set in the HCTSIZ register. In this case, the ++ * controller performs the entire PING protocol, then starts the data ++ * transfer. ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ * @param hc Information needed to initialize the host channel. The xfer_len ++ * value may be reduced to accommodate the max widths of the XferSize and ++ * PktCnt fields in the HCTSIZn register. The multi_count value may be changed ++ * to reflect the final xfer_len value. ++ */ ++void dwc_otg_hc_start_transfer(dwc_otg_core_if_t * core_if, dwc_hc_t * hc) ++{ ++ hcchar_data_t hcchar; ++ hctsiz_data_t hctsiz; ++ uint16_t num_packets; ++ uint32_t max_hc_xfer_size = core_if->core_params->max_transfer_size; ++ uint16_t max_hc_pkt_count = core_if->core_params->max_packet_count; ++ dwc_otg_hc_regs_t *hc_regs = core_if->host_if->hc_regs[hc->hc_num]; ++ ++ hctsiz.d32 = 0; ++ ++ if (hc->do_ping) { ++ if (!core_if->dma_enable) { ++ dwc_otg_hc_do_ping(core_if, hc); ++ hc->xfer_started = 1; ++ return; ++ } else { ++ hctsiz.b.dopng = 1; ++ } ++ } ++ ++ if (hc->do_split) { ++ num_packets = 1; ++ ++ if (hc->complete_split && !hc->ep_is_in) { ++ /* For CSPLIT OUT Transfer, set the size to 0 so the ++ * core doesn't expect any data written to the FIFO */ ++ hc->xfer_len = 0; ++ } else if (hc->ep_is_in || (hc->xfer_len > hc->max_packet)) { ++ hc->xfer_len = hc->max_packet; ++ } else if (!hc->ep_is_in && (hc->xfer_len > 188)) { ++ hc->xfer_len = 188; ++ } ++ ++ hctsiz.b.xfersize = hc->xfer_len; ++ } else { ++ /* ++ * Ensure that the transfer length and packet count will fit ++ * in the widths allocated for them in the HCTSIZn register. ++ */ ++ if (hc->ep_type == DWC_OTG_EP_TYPE_INTR || ++ hc->ep_type == DWC_OTG_EP_TYPE_ISOC) { ++ /* ++ * Make sure the transfer size is no larger than one ++ * (micro)frame's worth of data. (A check was done ++ * when the periodic transfer was accepted to ensure ++ * that a (micro)frame's worth of data can be ++ * programmed into a channel.) ++ */ ++ uint32_t max_periodic_len = ++ hc->multi_count * hc->max_packet; ++ if (hc->xfer_len > max_periodic_len) { ++ hc->xfer_len = max_periodic_len; ++ } else { ++ } ++ } else if (hc->xfer_len > max_hc_xfer_size) { ++ /* Make sure that xfer_len is a multiple of max packet size. */ ++ hc->xfer_len = max_hc_xfer_size - hc->max_packet + 1; ++ } ++ ++ if (hc->xfer_len > 0) { ++ num_packets = ++ (hc->xfer_len + hc->max_packet - ++ 1) / hc->max_packet; ++ if (num_packets > max_hc_pkt_count) { ++ num_packets = max_hc_pkt_count; ++ hc->xfer_len = num_packets * hc->max_packet; ++ } ++ } else { ++ /* Need 1 packet for transfer length of 0. */ ++ num_packets = 1; ++ } ++ ++ if (hc->ep_is_in) { ++ /* Always program an integral # of max packets for IN transfers. */ ++ hc->xfer_len = num_packets * hc->max_packet; ++ } ++ ++ if (hc->ep_type == DWC_OTG_EP_TYPE_INTR || ++ hc->ep_type == DWC_OTG_EP_TYPE_ISOC) { ++ /* ++ * Make sure that the multi_count field matches the ++ * actual transfer length. ++ */ ++ hc->multi_count = num_packets; ++ } ++ ++ if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC) ++ set_pid_isoc(hc); ++ ++ hctsiz.b.xfersize = hc->xfer_len; ++ } ++ ++ hc->start_pkt_count = num_packets; ++ hctsiz.b.pktcnt = num_packets; ++ hctsiz.b.pid = hc->data_pid_start; ++ dwc_write_reg32(&hc_regs->hctsiz, hctsiz.d32); ++ ++ DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num); ++ DWC_DEBUGPL(DBG_HCDV, " Xfer Size: %d\n", hctsiz.b.xfersize); ++ DWC_DEBUGPL(DBG_HCDV, " Num Pkts: %d\n", hctsiz.b.pktcnt); ++ DWC_DEBUGPL(DBG_HCDV, " Start PID: %d\n", hctsiz.b.pid); ++ ++ if (core_if->dma_enable) { ++ dwc_dma_t dma_addr; ++ if (hc->align_buff) { ++ dma_addr = hc->align_buff; ++ } else { ++ dma_addr = (uint32_t)hc->xfer_buff; ++ } ++ dwc_write_reg32(&hc_regs->hcdma, dma_addr); ++ } ++ ++ /* Start the split */ ++ if (hc->do_split) { ++ hcsplt_data_t hcsplt; ++ hcsplt.d32 = dwc_read_reg32(&hc_regs->hcsplt); ++ hcsplt.b.spltena = 1; ++ dwc_write_reg32(&hc_regs->hcsplt, hcsplt.d32); ++ } ++ ++ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); ++ hcchar.b.multicnt = hc->multi_count; ++ hc_set_even_odd_frame(core_if, hc, &hcchar); ++#ifdef DEBUG ++ core_if->start_hcchar_val[hc->hc_num] = hcchar.d32; ++ if (hcchar.b.chdis) { ++ DWC_WARN("%s: chdis set, channel %d, hcchar 0x%08x\n", ++ __func__, hc->hc_num, hcchar.d32); ++ } ++#endif ++ ++ /* Set host channel enable after all other setup is complete. */ ++ hcchar.b.chen = 1; ++ hcchar.b.chdis = 0; ++ dwc_write_reg32(&hc_regs->hcchar, hcchar.d32); ++ ++ hc->xfer_started = 1; ++ hc->requests++; ++ ++ if (!core_if->dma_enable && !hc->ep_is_in && hc->xfer_len > 0) { ++ /* Load OUT packet into the appropriate Tx FIFO. */ ++ dwc_otg_hc_write_packet(core_if, hc); ++ } ++#ifdef DEBUG ++ if (hc->ep_type != DWC_OTG_EP_TYPE_INTR) { ++ DWC_DEBUGPL(DBG_HCDV, "transfer %d from core_if %p\n", ++ hc->hc_num, core_if);//GRAYG ++ core_if->hc_xfer_info[hc->hc_num].core_if = core_if; ++ core_if->hc_xfer_info[hc->hc_num].hc = hc; ++ /* Start a timer for this transfer. */ ++ DWC_TIMER_SCHEDULE(core_if->hc_xfer_timer[hc->hc_num], 10000); ++ } ++#endif ++} ++ ++/** ++ * This function does the setup for a data transfer for a host channel ++ * and starts the transfer in Descriptor DMA mode. ++ * ++ * Initializes HCTSIZ register. For a PING transfer the Do Ping bit is set. ++ * Sets PID and NTD values. For periodic transfers ++ * initializes SCHED_INFO field with micro-frame bitmap. ++ * ++ * Initializes HCDMA register with descriptor list address and CTD value ++ * then starts the transfer via enabling the channel. ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ * @param hc Information needed to initialize the host channel. ++ */ ++void dwc_otg_hc_start_transfer_ddma(dwc_otg_core_if_t * core_if, dwc_hc_t * hc) ++{ ++ dwc_otg_hc_regs_t *hc_regs = core_if->host_if->hc_regs[hc->hc_num]; ++ hcchar_data_t hcchar; ++ hctsiz_data_t hctsiz; ++ hcdma_data_t hcdma; ++ ++ hctsiz.d32 = 0; ++ ++ if (hc->do_ping && !hc->ep_is_in) ++ hctsiz.b_ddma.dopng = 1; ++ ++ if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC) ++ set_pid_isoc(hc); ++ ++ /* Packet Count and Xfer Size are not used in Descriptor DMA mode */ ++ hctsiz.b_ddma.pid = hc->data_pid_start; ++ hctsiz.b_ddma.ntd = hc->ntd - 1; /* 0 - 1 descriptor, 1 - 2 descriptors, etc. */ ++ hctsiz.b_ddma.schinfo = hc->schinfo; /* Non-zero only for high-speed interrupt endpoints */ ++ ++ DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num); ++ DWC_DEBUGPL(DBG_HCDV, " Start PID: %d\n", hctsiz.b.pid); ++ DWC_DEBUGPL(DBG_HCDV, " NTD: %d\n", hctsiz.b_ddma.ntd); ++ ++ dwc_write_reg32(&hc_regs->hctsiz, hctsiz.d32); ++ ++ hcdma.d32 = 0; ++ hcdma.b.dma_addr = ((uint32_t)hc->desc_list_addr) >> 11; ++ ++ /* Always start from first descriptor. */ ++ hcdma.b.ctd = 0; ++ dwc_write_reg32(&hc_regs->hcdma, hcdma.d32); ++ ++ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); ++ hcchar.b.multicnt = hc->multi_count; ++ ++#ifdef DEBUG ++ core_if->start_hcchar_val[hc->hc_num] = hcchar.d32; ++ if (hcchar.b.chdis) { ++ DWC_WARN("%s: chdis set, channel %d, hcchar 0x%08x\n", ++ __func__, hc->hc_num, hcchar.d32); ++ } ++#endif ++ ++ /* Set host channel enable after all other setup is complete. */ ++ hcchar.b.chen = 1; ++ hcchar.b.chdis = 0; ++ ++ dwc_write_reg32(&hc_regs->hcchar, hcchar.d32); ++ ++ hc->xfer_started = 1; ++ hc->requests++; ++ ++#ifdef DEBUG ++ if ((hc->ep_type != DWC_OTG_EP_TYPE_INTR) && (hc->ep_type != DWC_OTG_EP_TYPE_ISOC)) { ++ DWC_DEBUGPL(DBG_HCDV, "DMA transfer %d from core_if %p\n", ++ hc->hc_num, core_if);//GRAYG ++ core_if->hc_xfer_info[hc->hc_num].core_if = core_if; ++ core_if->hc_xfer_info[hc->hc_num].hc = hc; ++ /* Start a timer for this transfer. */ ++ DWC_TIMER_SCHEDULE(core_if->hc_xfer_timer[hc->hc_num], 10000); ++ } ++ ++#endif ++ ++} ++ ++/** ++ * This function continues a data transfer that was started by previous call ++ * to dwc_otg_hc_start_transfer. The caller must ensure there is ++ * sufficient space in the request queue and Tx Data FIFO. This function ++ * should only be called in Slave mode. In DMA mode, the controller acts ++ * autonomously to complete transfers programmed to a host channel. ++ * ++ * For an OUT transfer, a new data packet is loaded into the appropriate FIFO ++ * if there is any data remaining to be queued. For an IN transfer, another ++ * data packet is always requested. For the SETUP phase of a control transfer, ++ * this function does nothing. ++ * ++ * @return 1 if a new request is queued, 0 if no more requests are required ++ * for this transfer. ++ */ ++int dwc_otg_hc_continue_transfer(dwc_otg_core_if_t * core_if, dwc_hc_t * hc) ++{ ++ DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num); ++ ++ if (hc->do_split) { ++ /* SPLITs always queue just once per channel */ ++ return 0; ++ } else if (hc->data_pid_start == DWC_OTG_HC_PID_SETUP) { ++ /* SETUPs are queued only once since they can't be NAKed. */ ++ return 0; ++ } else if (hc->ep_is_in) { ++ /* ++ * Always queue another request for other IN transfers. If ++ * back-to-back INs are issued and NAKs are received for both, ++ * the driver may still be processing the first NAK when the ++ * second NAK is received. When the interrupt handler clears ++ * the NAK interrupt for the first NAK, the second NAK will ++ * not be seen. So we can't depend on the NAK interrupt ++ * handler to requeue a NAKed request. Instead, IN requests ++ * are issued each time this function is called. When the ++ * transfer completes, the extra requests for the channel will ++ * be flushed. ++ */ ++ hcchar_data_t hcchar; ++ dwc_otg_hc_regs_t *hc_regs = ++ core_if->host_if->hc_regs[hc->hc_num]; ++ ++ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); ++ hc_set_even_odd_frame(core_if, hc, &hcchar); ++ hcchar.b.chen = 1; ++ hcchar.b.chdis = 0; ++ DWC_DEBUGPL(DBG_HCDV, " IN xfer: hcchar = 0x%08x\n", ++ hcchar.d32); ++ dwc_write_reg32(&hc_regs->hcchar, hcchar.d32); ++ hc->requests++; ++ return 1; ++ } else { ++ /* OUT transfers. */ ++ if (hc->xfer_count < hc->xfer_len) { ++ if (hc->ep_type == DWC_OTG_EP_TYPE_INTR || ++ hc->ep_type == DWC_OTG_EP_TYPE_ISOC) { ++ hcchar_data_t hcchar; ++ dwc_otg_hc_regs_t *hc_regs; ++ hc_regs = core_if->host_if->hc_regs[hc->hc_num]; ++ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); ++ hc_set_even_odd_frame(core_if, hc, &hcchar); ++ } ++ ++ /* Load OUT packet into the appropriate Tx FIFO. */ ++ dwc_otg_hc_write_packet(core_if, hc); ++ hc->requests++; ++ return 1; ++ } else { ++ return 0; ++ } ++ } ++} ++ ++/** ++ * Starts a PING transfer. This function should only be called in Slave mode. ++ * The Do Ping bit is set in the HCTSIZ register, then the channel is enabled. ++ */ ++void dwc_otg_hc_do_ping(dwc_otg_core_if_t * core_if, dwc_hc_t * hc) ++{ ++ hcchar_data_t hcchar; ++ hctsiz_data_t hctsiz; ++ dwc_otg_hc_regs_t *hc_regs = core_if->host_if->hc_regs[hc->hc_num]; ++ ++ DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num); ++ ++ hctsiz.d32 = 0; ++ hctsiz.b.dopng = 1; ++ hctsiz.b.pktcnt = 1; ++ dwc_write_reg32(&hc_regs->hctsiz, hctsiz.d32); ++ ++ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); ++ hcchar.b.chen = 1; ++ hcchar.b.chdis = 0; ++ dwc_write_reg32(&hc_regs->hcchar, hcchar.d32); ++} ++ ++/* ++ * This function writes a packet into the Tx FIFO associated with the Host ++ * Channel. For a channel associated with a non-periodic EP, the non-periodic ++ * Tx FIFO is written. For a channel associated with a periodic EP, the ++ * periodic Tx FIFO is written. This function should only be called in Slave ++ * mode. ++ * ++ * Upon return the xfer_buff and xfer_count fields in _hc are incremented by ++ * then number of bytes written to the Tx FIFO. ++ */ ++void dwc_otg_hc_write_packet(dwc_otg_core_if_t * core_if, dwc_hc_t * hc) ++{ ++ uint32_t i; ++ uint32_t remaining_count; ++ uint32_t byte_count; ++ uint32_t dword_count; ++ ++ uint32_t *data_buff = (uint32_t *) (hc->xfer_buff); ++ uint32_t *data_fifo = core_if->data_fifo[hc->hc_num]; ++ ++ remaining_count = hc->xfer_len - hc->xfer_count; ++ if (remaining_count > hc->max_packet) { ++ byte_count = hc->max_packet; ++ } else { ++ byte_count = remaining_count; ++ } ++ ++ dword_count = (byte_count + 3) / 4; ++ ++ if ((((unsigned long)data_buff) & 0x3) == 0) { ++ /* xfer_buff is DWORD aligned. */ ++ for (i = 0; i < dword_count; i++, data_buff++) { ++ dwc_write_reg32(data_fifo, *data_buff); ++ } ++ } else { ++ /* xfer_buff is not DWORD aligned. */ ++ for (i = 0; i < dword_count; i++, data_buff++) { ++ uint32_t data; ++ data = ++ (data_buff[0] | data_buff[1] << 8 | data_buff[2] << ++ 16 | data_buff[3] << 24); ++ dwc_write_reg32(data_fifo, data); ++ } ++ } ++ ++ hc->xfer_count += byte_count; ++ hc->xfer_buff += byte_count; ++} ++ ++/** ++ * Gets the current USB frame number. This is the frame number from the last ++ * SOF packet. ++ */ ++uint32_t dwc_otg_get_frame_number(dwc_otg_core_if_t * core_if) ++{ ++ dsts_data_t dsts; ++ dsts.d32 = dwc_read_reg32(&core_if->dev_if->dev_global_regs->dsts); ++ ++ /* read current frame/microframe number from DSTS register */ ++ return dsts.b.soffn; ++} ++ ++/** ++ * This function reads a setup packet from the Rx FIFO into the destination ++ * buffer. This function is called from the Rx Status Queue Level (RxStsQLvl) ++ * Interrupt routine when a SETUP packet has been received in Slave mode. ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ * @param dest Destination buffer for packet data. ++ */ ++void dwc_otg_read_setup_packet(dwc_otg_core_if_t * core_if, uint32_t * dest) ++{ ++ /* Get the 8 bytes of a setup transaction data */ ++ ++ /* Pop 2 DWORDS off the receive data FIFO into memory */ ++ dest[0] = dwc_read_reg32(core_if->data_fifo[0]); ++ dest[1] = dwc_read_reg32(core_if->data_fifo[0]); ++} ++ ++/** ++ * This function enables EP0 OUT to receive SETUP packets and configures EP0 ++ * IN for transmitting packets. It is normally called when the ++ * "Enumeration Done" interrupt occurs. ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ * @param ep The EP0 data. ++ */ ++void dwc_otg_ep0_activate(dwc_otg_core_if_t * core_if, dwc_ep_t * ep) ++{ ++ dwc_otg_dev_if_t *dev_if = core_if->dev_if; ++ dsts_data_t dsts; ++ depctl_data_t diepctl; ++ depctl_data_t doepctl; ++ dctl_data_t dctl = {.d32 = 0 }; ++ ++ /* Read the Device Status and Endpoint 0 Control registers */ ++ dsts.d32 = dwc_read_reg32(&dev_if->dev_global_regs->dsts); ++ diepctl.d32 = dwc_read_reg32(&dev_if->in_ep_regs[0]->diepctl); ++ doepctl.d32 = dwc_read_reg32(&dev_if->out_ep_regs[0]->doepctl); ++ ++ /* Set the MPS of the IN EP based on the enumeration speed */ ++ switch (dsts.b.enumspd) { ++ case DWC_DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ: ++ case DWC_DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ: ++ case DWC_DSTS_ENUMSPD_FS_PHY_48MHZ: ++ diepctl.b.mps = DWC_DEP0CTL_MPS_64; ++ break; ++ case DWC_DSTS_ENUMSPD_LS_PHY_6MHZ: ++ diepctl.b.mps = DWC_DEP0CTL_MPS_8; ++ break; ++ } ++ ++ dwc_write_reg32(&dev_if->in_ep_regs[0]->diepctl, diepctl.d32); ++ ++ /* Enable OUT EP for receive */ ++ doepctl.b.epena = 1; ++ dwc_write_reg32(&dev_if->out_ep_regs[0]->doepctl, doepctl.d32); ++ ++#ifdef VERBOSE ++ DWC_DEBUGPL(DBG_PCDV, "doepctl0=%0x\n", ++ dwc_read_reg32(&dev_if->out_ep_regs[0]->doepctl)); ++ DWC_DEBUGPL(DBG_PCDV, "diepctl0=%0x\n", ++ dwc_read_reg32(&dev_if->in_ep_regs[0]->diepctl)); ++#endif ++ dctl.b.cgnpinnak = 1; ++ ++ dwc_modify_reg32(&dev_if->dev_global_regs->dctl, dctl.d32, dctl.d32); ++ DWC_DEBUGPL(DBG_PCDV, "dctl=%0x\n", ++ dwc_read_reg32(&dev_if->dev_global_regs->dctl)); ++} ++ ++/** ++ * This function activates an EP. The Device EP control register for ++ * the EP is configured as defined in the ep structure. Note: This ++ * function is not used for EP0. ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ * @param ep The EP to activate. ++ */ ++void dwc_otg_ep_activate(dwc_otg_core_if_t * core_if, dwc_ep_t * ep) ++{ ++ dwc_otg_dev_if_t *dev_if = core_if->dev_if; ++ depctl_data_t depctl; ++ volatile uint32_t *addr; ++ daint_data_t daintmsk = {.d32 = 0 }; ++ ++ DWC_DEBUGPL(DBG_PCDV, "%s() EP%d-%s\n", __func__, ep->num, ++ (ep->is_in ? "IN" : "OUT")); ++ ++ /* Read DEPCTLn register */ ++ if (ep->is_in == 1) { ++ addr = &dev_if->in_ep_regs[ep->num]->diepctl; ++ daintmsk.ep.in = 1 << ep->num; ++ } else { ++ addr = &dev_if->out_ep_regs[ep->num]->doepctl; ++ daintmsk.ep.out = 1 << ep->num; ++ } ++ ++ /* If the EP is already active don't change the EP Control ++ * register. */ ++ depctl.d32 = dwc_read_reg32(addr); ++ if (!depctl.b.usbactep) { ++ depctl.b.mps = ep->maxpacket; ++ depctl.b.eptype = ep->type; ++ depctl.b.txfnum = ep->tx_fifo_num; ++ ++ if (ep->type == DWC_OTG_EP_TYPE_ISOC) { ++ depctl.b.setd0pid = 1; // ??? ++ } else { ++ depctl.b.setd0pid = 1; ++ } ++ depctl.b.usbactep = 1; ++ ++ dwc_write_reg32(addr, depctl.d32); ++ DWC_DEBUGPL(DBG_PCDV, "DEPCTL=%08x\n", dwc_read_reg32(addr)); ++ } ++ ++ /* Enable the Interrupt for this EP */ ++ if (core_if->multiproc_int_enable) { ++ if (ep->is_in == 1) { ++ diepmsk_data_t diepmsk = {.d32 = 0 }; ++ diepmsk.b.xfercompl = 1; ++ diepmsk.b.timeout = 1; ++ diepmsk.b.epdisabled = 1; ++ diepmsk.b.ahberr = 1; ++ diepmsk.b.intknepmis = 1; ++ diepmsk.b.txfifoundrn = 1; //????? ++ ++ if (core_if->dma_desc_enable) { ++ diepmsk.b.bna = 1; ++ } ++/* ++ if(core_if->dma_enable) { ++ doepmsk.b.nak = 1; ++ } ++*/ ++ dwc_write_reg32(&dev_if->dev_global_regs-> ++ diepeachintmsk[ep->num], diepmsk.d32); ++ ++ } else { ++ doepmsk_data_t doepmsk = {.d32 = 0 }; ++ doepmsk.b.xfercompl = 1; ++ doepmsk.b.ahberr = 1; ++ doepmsk.b.epdisabled = 1; ++ ++ if (core_if->dma_desc_enable) { ++ doepmsk.b.bna = 1; ++ } ++/* ++ doepmsk.b.babble = 1; ++ doepmsk.b.nyet = 1; ++ doepmsk.b.nak = 1; ++*/ ++ dwc_write_reg32(&dev_if->dev_global_regs-> ++ doepeachintmsk[ep->num], doepmsk.d32); ++ } ++ dwc_modify_reg32(&dev_if->dev_global_regs->deachintmsk, ++ 0, daintmsk.d32); ++ } else { ++ dwc_modify_reg32(&dev_if->dev_global_regs->daintmsk, ++ 0, daintmsk.d32); ++ } ++ ++ DWC_DEBUGPL(DBG_PCDV, "DAINTMSK=%0x\n", ++ dwc_read_reg32(&dev_if->dev_global_regs->daintmsk)); ++ ++ ep->stall_clear_flag = 0; ++ return; ++} ++ ++/** ++ * This function deactivates an EP. This is done by clearing the USB Active ++ * EP bit in the Device EP control register. Note: This function is not used ++ * for EP0. EP0 cannot be deactivated. ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ * @param ep The EP to deactivate. ++ */ ++void dwc_otg_ep_deactivate(dwc_otg_core_if_t * core_if, dwc_ep_t * ep) ++{ ++ depctl_data_t depctl = {.d32 = 0 }; ++ volatile uint32_t *addr; ++ daint_data_t daintmsk = {.d32 = 0 }; ++ ++ /* Read DEPCTLn register */ ++ if (ep->is_in == 1) { ++ addr = &core_if->dev_if->in_ep_regs[ep->num]->diepctl; ++ daintmsk.ep.in = 1 << ep->num; ++ } else { ++ addr = &core_if->dev_if->out_ep_regs[ep->num]->doepctl; ++ daintmsk.ep.out = 1 << ep->num; ++ } ++ ++ depctl.d32 = dwc_read_reg32(addr); ++ ++ depctl.b.usbactep = 0; ++ ++ if (core_if->dma_desc_enable) ++ depctl.b.epdis = 1; ++ ++ dwc_write_reg32(addr, depctl.d32); ++ ++ /* Disable the Interrupt for this EP */ ++ if (core_if->multiproc_int_enable) { ++ dwc_modify_reg32(&core_if->dev_if->dev_global_regs->deachintmsk, ++ daintmsk.d32, 0); ++ ++ if (ep->is_in == 1) { ++ dwc_write_reg32(&core_if->dev_if->dev_global_regs-> ++ diepeachintmsk[ep->num], 0); ++ } else { ++ dwc_write_reg32(&core_if->dev_if->dev_global_regs-> ++ doepeachintmsk[ep->num], 0); ++ } ++ } else { ++ dwc_modify_reg32(&core_if->dev_if->dev_global_regs->daintmsk, ++ daintmsk.d32, 0); ++ } ++} ++ ++/** ++ * This function initializes dma descriptor chain. ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ * @param ep The EP to start the transfer on. ++ */ ++static void init_dma_desc_chain(dwc_otg_core_if_t * core_if, dwc_ep_t * ep) ++{ ++ dwc_otg_dev_dma_desc_t *dma_desc; ++ uint32_t offset; ++ uint32_t xfer_est; ++ int i; ++ ++ ep->desc_cnt = (ep->total_len / ep->maxxfer) + ++ ((ep->total_len % ep->maxxfer) ? 1 : 0); ++ if (!ep->desc_cnt) ++ ep->desc_cnt = 1; ++ ++ dma_desc = ep->desc_addr; ++ xfer_est = ep->total_len; ++ offset = 0; ++ for (i = 0; i < ep->desc_cnt; ++i) { ++ /** DMA Descriptor Setup */ ++ if (xfer_est > ep->maxxfer) { ++ dma_desc->status.b.bs = BS_HOST_BUSY; ++ dma_desc->status.b.l = 0; ++ dma_desc->status.b.ioc = 0; ++ dma_desc->status.b.sp = 0; ++ dma_desc->status.b.bytes = ep->maxxfer; ++ dma_desc->buf = ep->dma_addr + offset; ++ dma_desc->status.b.bs = BS_HOST_READY; ++ ++ xfer_est -= ep->maxxfer; ++ offset += ep->maxxfer; ++ } else { ++ dma_desc->status.b.bs = BS_HOST_BUSY; ++ dma_desc->status.b.l = 1; ++ dma_desc->status.b.ioc = 1; ++ if (ep->is_in) { ++ dma_desc->status.b.sp = ++ (xfer_est % ++ ep->maxpacket) ? 1 : ((ep-> ++ sent_zlp) ? 1 : 0); ++ dma_desc->status.b.bytes = xfer_est; ++ } else { ++ dma_desc->status.b.bytes = ++ xfer_est + ((4 - (xfer_est & 0x3)) & 0x3); ++ } ++ ++ dma_desc->buf = ep->dma_addr + offset; ++ dma_desc->status.b.bs = BS_HOST_READY; ++ } ++ dma_desc++; ++ } ++} ++ ++/** ++ * This function does the setup for a data transfer for an EP and ++ * starts the transfer. For an IN transfer, the packets will be ++ * loaded into the appropriate Tx FIFO in the ISR. For OUT transfers, ++ * the packets are unloaded from the Rx FIFO in the ISR. the ISR. ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ * @param ep The EP to start the transfer on. ++ */ ++ ++void dwc_otg_ep_start_transfer(dwc_otg_core_if_t * core_if, dwc_ep_t * ep) ++{ ++ depctl_data_t depctl; ++ deptsiz_data_t deptsiz; ++ gintmsk_data_t intr_mask = {.d32 = 0 }; ++ ++ DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "%s()\n", __func__); ++ DWC_DEBUGPL(DBG_PCD, "ep%d-%s xfer_len=%d xfer_cnt=%d " ++ "xfer_buff=%p start_xfer_buff=%p, total_len = %d\n", ++ ep->num, (ep->is_in ? "IN" : "OUT"), ep->xfer_len, ++ ep->xfer_count, ep->xfer_buff, ep->start_xfer_buff, ++ ep->total_len); ++ /* IN endpoint */ ++ if (ep->is_in == 1) { ++ dwc_otg_dev_in_ep_regs_t *in_regs = ++ core_if->dev_if->in_ep_regs[ep->num]; ++ ++ gnptxsts_data_t gtxstatus; ++ ++ gtxstatus.d32 = ++ dwc_read_reg32(&core_if->core_global_regs->gnptxsts); ++ ++ if (core_if->en_multiple_tx_fifo == 0 ++ && gtxstatus.b.nptxqspcavail == 0) { ++#ifdef DEBUG ++ DWC_PRINTF("TX Queue Full (0x%0x)\n", gtxstatus.d32); ++#endif ++ return; ++ } ++ ++ depctl.d32 = dwc_read_reg32(&(in_regs->diepctl)); ++ deptsiz.d32 = dwc_read_reg32(&(in_regs->dieptsiz)); ++ ++ ep->xfer_len += (ep->maxxfer < (ep->total_len - ep->xfer_len)) ? ++ ep->maxxfer : (ep->total_len - ep->xfer_len); ++ ++ /* Zero Length Packet? */ ++ if ((ep->xfer_len - ep->xfer_count) == 0) { ++ deptsiz.b.xfersize = 0; ++ deptsiz.b.pktcnt = 1; ++ } else { ++ /* Program the transfer size and packet count ++ * as follows: xfersize = N * maxpacket + ++ * short_packet pktcnt = N + (short_packet ++ * exist ? 1 : 0) ++ */ ++ deptsiz.b.xfersize = ep->xfer_len - ep->xfer_count; ++ deptsiz.b.pktcnt = ++ (ep->xfer_len - ep->xfer_count - 1 + ++ ep->maxpacket) / ep->maxpacket; ++ } ++ ++ /* Write the DMA register */ ++ if (core_if->dma_enable) { ++ if (core_if->dma_desc_enable == 0) { ++ dwc_write_reg32(&in_regs->dieptsiz, ++ deptsiz.d32); ++ dwc_write_reg32(&(in_regs->diepdma), ++ (uint32_t) ep->dma_addr); ++ } else { ++#ifdef DWC_UTE_CFI ++ /* The descriptor chain should be already initialized by now */ ++ if (ep->buff_mode != BM_STANDARD) { ++ dwc_write_reg32(&in_regs->diepdma, ++ ep->descs_dma_addr); ++ } else { ++#endif ++ init_dma_desc_chain(core_if, ep); ++ /** DIEPDMAn Register write */ ++ dwc_write_reg32(&in_regs->diepdma, ++ ep->dma_desc_addr); ++#ifdef DWC_UTE_CFI ++ } ++#endif ++ } ++ } else { ++ dwc_write_reg32(&in_regs->dieptsiz, deptsiz.d32); ++ if (ep->type != DWC_OTG_EP_TYPE_ISOC) { ++ /** ++ * Enable the Non-Periodic Tx FIFO empty interrupt, ++ * or the Tx FIFO epmty interrupt in dedicated Tx FIFO mode, ++ * the data will be written into the fifo by the ISR. ++ */ ++ if (core_if->en_multiple_tx_fifo == 0) { ++ intr_mask.b.nptxfempty = 1; ++ dwc_modify_reg32(&core_if-> ++ core_global_regs-> ++ gintmsk, intr_mask.d32, ++ intr_mask.d32); ++ } else { ++ /* Enable the Tx FIFO Empty Interrupt for this EP */ ++ if (ep->xfer_len > 0) { ++ uint32_t fifoemptymsk = 0; ++ fifoemptymsk = 1 << ep->num; ++ dwc_modify_reg32(&core_if-> ++ dev_if-> ++ dev_global_regs-> ++ dtknqr4_fifoemptymsk, ++ 0, ++ fifoemptymsk); ++ ++ } ++ } ++ } ++ } ++ ++ /* EP enable, IN data in FIFO */ ++ depctl.b.cnak = 1; ++ depctl.b.epena = 1; ++ dwc_write_reg32(&in_regs->diepctl, depctl.d32); ++ ++ depctl.d32 = ++ dwc_read_reg32(&core_if->dev_if->in_ep_regs[0]->diepctl); ++ depctl.b.nextep = ep->num; ++ dwc_write_reg32(&core_if->dev_if->in_ep_regs[0]->diepctl, ++ depctl.d32); ++ ++ } else { ++ /* OUT endpoint */ ++ dwc_otg_dev_out_ep_regs_t *out_regs = ++ core_if->dev_if->out_ep_regs[ep->num]; ++ ++ depctl.d32 = dwc_read_reg32(&(out_regs->doepctl)); ++ deptsiz.d32 = dwc_read_reg32(&(out_regs->doeptsiz)); ++ ++ ep->xfer_len += (ep->maxxfer < (ep->total_len - ep->xfer_len)) ? ++ ep->maxxfer : (ep->total_len - ep->xfer_len); ++ ++ /* Program the transfer size and packet count as follows: ++ * ++ * pktcnt = N ++ * xfersize = N * maxpacket ++ */ ++ if ((ep->xfer_len - ep->xfer_count) == 0) { ++ /* Zero Length Packet */ ++ deptsiz.b.xfersize = ep->maxpacket; ++ deptsiz.b.pktcnt = 1; ++ } else { ++ deptsiz.b.pktcnt = ++ (ep->xfer_len - ep->xfer_count + ++ (ep->maxpacket - 1)) / ep->maxpacket; ++ ep->xfer_len = ++ deptsiz.b.pktcnt * ep->maxpacket + ep->xfer_count; ++ deptsiz.b.xfersize = ep->xfer_len - ep->xfer_count; ++ } ++ ++ DWC_DEBUGPL(DBG_PCDV, "ep%d xfersize=%d pktcnt=%d\n", ++ ep->num, deptsiz.b.xfersize, deptsiz.b.pktcnt); ++ ++ if (core_if->dma_enable) { ++ if (!core_if->dma_desc_enable) { ++ dwc_write_reg32(&out_regs->doeptsiz, ++ deptsiz.d32); ++ ++ dwc_write_reg32(&(out_regs->doepdma), ++ (uint32_t) ep->dma_addr); ++ } else { ++#ifdef DWC_UTE_CFI ++ /* The descriptor chain should be already initialized by now */ ++ if (ep->buff_mode != BM_STANDARD) { ++ dwc_write_reg32(&out_regs->doepdma, ++ ep->descs_dma_addr); ++ } else { ++#endif ++ ++ init_dma_desc_chain(core_if, ep); ++ ++ /** DOEPDMAn Register write */ ++ dwc_write_reg32(&out_regs->doepdma, ++ ep->dma_desc_addr); ++#ifdef DWC_UTE_CFI ++ } ++#endif ++ } ++ } else { ++ dwc_write_reg32(&out_regs->doeptsiz, deptsiz.d32); ++ } ++ ++ /* EP enable */ ++ depctl.b.cnak = 1; ++ depctl.b.epena = 1; ++ ++ dwc_write_reg32(&out_regs->doepctl, depctl.d32); ++ ++ DWC_DEBUGPL(DBG_PCD, "DOEPCTL=%08x DOEPTSIZ=%08x\n", ++ dwc_read_reg32(&out_regs->doepctl), ++ dwc_read_reg32(&out_regs->doeptsiz)); ++ DWC_DEBUGPL(DBG_PCD, "DAINTMSK=%08x GINTMSK=%08x\n", ++ dwc_read_reg32(&core_if->dev_if->dev_global_regs-> ++ daintmsk), ++ dwc_read_reg32(&core_if->core_global_regs-> ++ gintmsk)); ++ } ++} ++ ++/** ++ * This function setup a zero length transfer in Buffer DMA and ++ * Slave modes for usb requests with zero field set ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ * @param ep The EP to start the transfer on. ++ * ++ */ ++void dwc_otg_ep_start_zl_transfer(dwc_otg_core_if_t * core_if, dwc_ep_t * ep) ++{ ++ ++ depctl_data_t depctl; ++ deptsiz_data_t deptsiz; ++ gintmsk_data_t intr_mask = {.d32 = 0 }; ++ ++ DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "%s()\n", __func__); ++ DWC_PRINTF("zero length transfer is called\n"); ++ ++ /* IN endpoint */ ++ if (ep->is_in == 1) { ++ dwc_otg_dev_in_ep_regs_t *in_regs = ++ core_if->dev_if->in_ep_regs[ep->num]; ++ ++ depctl.d32 = dwc_read_reg32(&(in_regs->diepctl)); ++ deptsiz.d32 = dwc_read_reg32(&(in_regs->dieptsiz)); ++ ++ deptsiz.b.xfersize = 0; ++ deptsiz.b.pktcnt = 1; ++ ++ /* Write the DMA register */ ++ if (core_if->dma_enable) { ++ if (core_if->dma_desc_enable == 0) { ++ dwc_write_reg32(&in_regs->dieptsiz, ++ deptsiz.d32); ++ dwc_write_reg32(&(in_regs->diepdma), ++ (uint32_t) ep->dma_addr); ++ } ++ } else { ++ dwc_write_reg32(&in_regs->dieptsiz, deptsiz.d32); ++ /** ++ * Enable the Non-Periodic Tx FIFO empty interrupt, ++ * or the Tx FIFO epmty interrupt in dedicated Tx FIFO mode, ++ * the data will be written into the fifo by the ISR. ++ */ ++ if (core_if->en_multiple_tx_fifo == 0) { ++ intr_mask.b.nptxfempty = 1; ++ dwc_modify_reg32(&core_if->core_global_regs-> ++ gintmsk, intr_mask.d32, ++ intr_mask.d32); ++ } else { ++ /* Enable the Tx FIFO Empty Interrupt for this EP */ ++ if (ep->xfer_len > 0) { ++ uint32_t fifoemptymsk = 0; ++ fifoemptymsk = 1 << ep->num; ++ dwc_modify_reg32(&core_if->dev_if-> ++ dev_global_regs-> ++ dtknqr4_fifoemptymsk, ++ 0, fifoemptymsk); ++ } ++ } ++ } ++ ++ /* EP enable, IN data in FIFO */ ++ depctl.b.cnak = 1; ++ depctl.b.epena = 1; ++ dwc_write_reg32(&in_regs->diepctl, depctl.d32); ++ ++ depctl.d32 = ++ dwc_read_reg32(&core_if->dev_if->in_ep_regs[0]->diepctl); ++ depctl.b.nextep = ep->num; ++ dwc_write_reg32(&core_if->dev_if->in_ep_regs[0]->diepctl, ++ depctl.d32); ++ ++ } else { ++ /* OUT endpoint */ ++ dwc_otg_dev_out_ep_regs_t *out_regs = ++ core_if->dev_if->out_ep_regs[ep->num]; ++ ++ depctl.d32 = dwc_read_reg32(&(out_regs->doepctl)); ++ deptsiz.d32 = dwc_read_reg32(&(out_regs->doeptsiz)); ++ ++ /* Zero Length Packet */ ++ deptsiz.b.xfersize = ep->maxpacket; ++ deptsiz.b.pktcnt = 1; ++ ++ if (core_if->dma_enable) { ++ if (!core_if->dma_desc_enable) { ++ dwc_write_reg32(&out_regs->doeptsiz, ++ deptsiz.d32); ++ ++ dwc_write_reg32(&(out_regs->doepdma), ++ (uint32_t) ep->dma_addr); ++ } ++ } else { ++ dwc_write_reg32(&out_regs->doeptsiz, deptsiz.d32); ++ } ++ ++ /* EP enable */ ++ depctl.b.cnak = 1; ++ depctl.b.epena = 1; ++ ++ dwc_write_reg32(&out_regs->doepctl, depctl.d32); ++ ++ } ++} ++ ++/** ++ * This function does the setup for a data transfer for EP0 and starts ++ * the transfer. For an IN transfer, the packets will be loaded into ++ * the appropriate Tx FIFO in the ISR. For OUT transfers, the packets are ++ * unloaded from the Rx FIFO in the ISR. ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ * @param ep The EP0 data. ++ */ ++void dwc_otg_ep0_start_transfer(dwc_otg_core_if_t * core_if, dwc_ep_t * ep) ++{ ++ depctl_data_t depctl; ++ deptsiz0_data_t deptsiz; ++ gintmsk_data_t intr_mask = {.d32 = 0 }; ++ dwc_otg_dev_dma_desc_t *dma_desc; ++ ++ DWC_DEBUGPL(DBG_PCD, "ep%d-%s xfer_len=%d xfer_cnt=%d " ++ "xfer_buff=%p start_xfer_buff=%p \n", ++ ep->num, (ep->is_in ? "IN" : "OUT"), ep->xfer_len, ++ ep->xfer_count, ep->xfer_buff, ep->start_xfer_buff); ++ ++ ep->total_len = ep->xfer_len; ++ ++ /* IN endpoint */ ++ if (ep->is_in == 1) { ++ dwc_otg_dev_in_ep_regs_t *in_regs = ++ core_if->dev_if->in_ep_regs[0]; ++ ++ gnptxsts_data_t gtxstatus; ++ ++ gtxstatus.d32 = ++ dwc_read_reg32(&core_if->core_global_regs->gnptxsts); ++ ++ if (core_if->en_multiple_tx_fifo == 0 ++ && gtxstatus.b.nptxqspcavail == 0) { ++#ifdef DEBUG ++ deptsiz.d32 = dwc_read_reg32(&in_regs->dieptsiz); ++ DWC_DEBUGPL(DBG_PCD, "DIEPCTL0=%0x\n", ++ dwc_read_reg32(&in_regs->diepctl)); ++ DWC_DEBUGPL(DBG_PCD, "DIEPTSIZ0=%0x (sz=%d, pcnt=%d)\n", ++ deptsiz.d32, ++ deptsiz.b.xfersize, deptsiz.b.pktcnt); ++ DWC_PRINTF("TX Queue or FIFO Full (0x%0x)\n", ++ gtxstatus.d32); ++#endif ++ return; ++ } ++ ++ depctl.d32 = dwc_read_reg32(&in_regs->diepctl); ++ deptsiz.d32 = dwc_read_reg32(&in_regs->dieptsiz); ++ ++ /* Zero Length Packet? */ ++ if (ep->xfer_len == 0) { ++ deptsiz.b.xfersize = 0; ++ deptsiz.b.pktcnt = 1; ++ } else { ++ /* Program the transfer size and packet count ++ * as follows: xfersize = N * maxpacket + ++ * short_packet pktcnt = N + (short_packet ++ * exist ? 1 : 0) ++ */ ++ if (ep->xfer_len > ep->maxpacket) { ++ ep->xfer_len = ep->maxpacket; ++ deptsiz.b.xfersize = ep->maxpacket; ++ } else { ++ deptsiz.b.xfersize = ep->xfer_len; ++ } ++ deptsiz.b.pktcnt = 1; ++ ++ } ++ DWC_DEBUGPL(DBG_PCDV, ++ "IN len=%d xfersize=%d pktcnt=%d [%08x]\n", ++ ep->xfer_len, deptsiz.b.xfersize, deptsiz.b.pktcnt, ++ deptsiz.d32); ++ ++ /* Write the DMA register */ ++ if (core_if->dma_enable) { ++ if (core_if->dma_desc_enable == 0) { ++ dwc_write_reg32(&in_regs->dieptsiz, ++ deptsiz.d32); ++ ++ dwc_write_reg32(&(in_regs->diepdma), ++ (uint32_t) ep->dma_addr); ++ } else { ++ dma_desc = core_if->dev_if->in_desc_addr; ++ ++ /** DMA Descriptor Setup */ ++ dma_desc->status.b.bs = BS_HOST_BUSY; ++ dma_desc->status.b.l = 1; ++ dma_desc->status.b.ioc = 1; ++ dma_desc->status.b.sp = ++ (ep->xfer_len == ep->maxpacket) ? 0 : 1; ++ dma_desc->status.b.bytes = ep->xfer_len; ++ dma_desc->buf = ep->dma_addr; ++ dma_desc->status.b.bs = BS_HOST_READY; ++ ++ /** DIEPDMA0 Register write */ ++ dwc_write_reg32(&in_regs->diepdma, ++ core_if->dev_if-> ++ dma_in_desc_addr); ++ } ++ } else { ++ dwc_write_reg32(&in_regs->dieptsiz, deptsiz.d32); ++ } ++ ++ /* EP enable, IN data in FIFO */ ++ depctl.b.cnak = 1; ++ depctl.b.epena = 1; ++ dwc_write_reg32(&in_regs->diepctl, depctl.d32); ++ ++ /** ++ * Enable the Non-Periodic Tx FIFO empty interrupt, the ++ * data will be written into the fifo by the ISR. ++ */ ++ if (!core_if->dma_enable) { ++ if (core_if->en_multiple_tx_fifo == 0) { ++ intr_mask.b.nptxfempty = 1; ++ dwc_modify_reg32(&core_if->core_global_regs-> ++ gintmsk, intr_mask.d32, ++ intr_mask.d32); ++ } else { ++ /* Enable the Tx FIFO Empty Interrupt for this EP */ ++ if (ep->xfer_len > 0) { ++ uint32_t fifoemptymsk = 0; ++ fifoemptymsk |= 1 << ep->num; ++ dwc_modify_reg32(&core_if->dev_if-> ++ dev_global_regs-> ++ dtknqr4_fifoemptymsk, ++ 0, fifoemptymsk); ++ } ++ } ++ } ++ } else { ++ /* OUT endpoint */ ++ dwc_otg_dev_out_ep_regs_t *out_regs = ++ core_if->dev_if->out_ep_regs[0]; ++ ++ depctl.d32 = dwc_read_reg32(&out_regs->doepctl); ++ deptsiz.d32 = dwc_read_reg32(&out_regs->doeptsiz); ++ ++ /* Program the transfer size and packet count as follows: ++ * xfersize = N * (maxpacket + 4 - (maxpacket % 4)) ++ * pktcnt = N */ ++ /* Zero Length Packet */ ++ deptsiz.b.xfersize = ep->maxpacket; ++ deptsiz.b.pktcnt = 1; ++ ++ DWC_DEBUGPL(DBG_PCDV, "len=%d xfersize=%d pktcnt=%d\n", ++ ep->xfer_len, deptsiz.b.xfersize, deptsiz.b.pktcnt); ++ ++ if (core_if->dma_enable) { ++ if (!core_if->dma_desc_enable) { ++ dwc_write_reg32(&out_regs->doeptsiz, ++ deptsiz.d32); ++ ++ dwc_write_reg32(&(out_regs->doepdma), ++ (uint32_t) ep->dma_addr); ++ } else { ++ dma_desc = core_if->dev_if->out_desc_addr; ++ ++ /** DMA Descriptor Setup */ ++ dma_desc->status.b.bs = BS_HOST_BUSY; ++ dma_desc->status.b.l = 1; ++ dma_desc->status.b.ioc = 1; ++ dma_desc->status.b.bytes = ep->maxpacket; ++ dma_desc->buf = ep->dma_addr; ++ dma_desc->status.b.bs = BS_HOST_READY; ++ ++ /** DOEPDMA0 Register write */ ++ dwc_write_reg32(&out_regs->doepdma, ++ core_if->dev_if-> ++ dma_out_desc_addr); ++ } ++ } else { ++ dwc_write_reg32(&out_regs->doeptsiz, deptsiz.d32); ++ } ++ ++ /* EP enable */ ++ depctl.b.cnak = 1; ++ depctl.b.epena = 1; ++ dwc_write_reg32(&(out_regs->doepctl), depctl.d32); ++ } ++} ++ ++/** ++ * This function continues control IN transfers started by ++ * dwc_otg_ep0_start_transfer, when the transfer does not fit in a ++ * single packet. NOTE: The DIEPCTL0/DOEPCTL0 registers only have one ++ * bit for the packet count. ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ * @param ep The EP0 data. ++ */ ++void dwc_otg_ep0_continue_transfer(dwc_otg_core_if_t * core_if, dwc_ep_t * ep) ++{ ++ depctl_data_t depctl; ++ deptsiz0_data_t deptsiz; ++ gintmsk_data_t intr_mask = {.d32 = 0 }; ++ dwc_otg_dev_dma_desc_t *dma_desc; ++ ++ if (ep->is_in == 1) { ++ dwc_otg_dev_in_ep_regs_t *in_regs = ++ core_if->dev_if->in_ep_regs[0]; ++ gnptxsts_data_t tx_status = {.d32 = 0 }; ++ ++ tx_status.d32 = ++ dwc_read_reg32(&core_if->core_global_regs->gnptxsts); ++ /** @todo Should there be check for room in the Tx ++ * Status Queue. If not remove the code above this comment. */ ++ ++ depctl.d32 = dwc_read_reg32(&in_regs->diepctl); ++ deptsiz.d32 = dwc_read_reg32(&in_regs->dieptsiz); ++ ++ /* Program the transfer size and packet count ++ * as follows: xfersize = N * maxpacket + ++ * short_packet pktcnt = N + (short_packet ++ * exist ? 1 : 0) ++ */ ++ ++ if (core_if->dma_desc_enable == 0) { ++ deptsiz.b.xfersize = ++ (ep->total_len - ep->xfer_count) > ++ ep->maxpacket ? ep->maxpacket : (ep->total_len - ++ ep->xfer_count); ++ deptsiz.b.pktcnt = 1; ++ if (core_if->dma_enable == 0) { ++ ep->xfer_len += deptsiz.b.xfersize; ++ } else { ++ ep->xfer_len = deptsiz.b.xfersize; ++ } ++ dwc_write_reg32(&in_regs->dieptsiz, deptsiz.d32); ++ } else { ++ ep->xfer_len = ++ (ep->total_len - ep->xfer_count) > ++ ep->maxpacket ? ep->maxpacket : (ep->total_len - ++ ep->xfer_count); ++ ++ dma_desc = core_if->dev_if->in_desc_addr; ++ ++ /** DMA Descriptor Setup */ ++ dma_desc->status.b.bs = BS_HOST_BUSY; ++ dma_desc->status.b.l = 1; ++ dma_desc->status.b.ioc = 1; ++ dma_desc->status.b.sp = ++ (ep->xfer_len == ep->maxpacket) ? 0 : 1; ++ dma_desc->status.b.bytes = ep->xfer_len; ++ dma_desc->buf = ep->dma_addr; ++ dma_desc->status.b.bs = BS_HOST_READY; ++ ++ /** DIEPDMA0 Register write */ ++ dwc_write_reg32(&in_regs->diepdma, ++ core_if->dev_if->dma_in_desc_addr); ++ } ++ ++ DWC_DEBUGPL(DBG_PCDV, ++ "IN len=%d xfersize=%d pktcnt=%d [%08x]\n", ++ ep->xfer_len, deptsiz.b.xfersize, deptsiz.b.pktcnt, ++ deptsiz.d32); ++ ++ /* Write the DMA register */ ++ if (core_if->hwcfg2.b.architecture == DWC_INT_DMA_ARCH) { ++ if (core_if->dma_desc_enable == 0) ++ dwc_write_reg32(&(in_regs->diepdma), ++ (uint32_t) ep->dma_addr); ++ } ++ ++ /* EP enable, IN data in FIFO */ ++ depctl.b.cnak = 1; ++ depctl.b.epena = 1; ++ dwc_write_reg32(&in_regs->diepctl, depctl.d32); ++ ++ /** ++ * Enable the Non-Periodic Tx FIFO empty interrupt, the ++ * data will be written into the fifo by the ISR. ++ */ ++ if (!core_if->dma_enable) { ++ if (core_if->en_multiple_tx_fifo == 0) { ++ /* First clear it from GINTSTS */ ++ intr_mask.b.nptxfempty = 1; ++ dwc_modify_reg32(&core_if->core_global_regs-> ++ gintmsk, intr_mask.d32, ++ intr_mask.d32); ++ ++ } else { ++ /* Enable the Tx FIFO Empty Interrupt for this EP */ ++ if (ep->xfer_len > 0) { ++ uint32_t fifoemptymsk = 0; ++ fifoemptymsk |= 1 << ep->num; ++ dwc_modify_reg32(&core_if->dev_if-> ++ dev_global_regs-> ++ dtknqr4_fifoemptymsk, ++ 0, fifoemptymsk); ++ } ++ } ++ } ++ } else { ++ dwc_otg_dev_out_ep_regs_t *out_regs = ++ core_if->dev_if->out_ep_regs[0]; ++ ++ depctl.d32 = dwc_read_reg32(&out_regs->doepctl); ++ deptsiz.d32 = dwc_read_reg32(&out_regs->doeptsiz); ++ ++ /* Program the transfer size and packet count ++ * as follows: xfersize = N * maxpacket + ++ * short_packet pktcnt = N + (short_packet ++ * exist ? 1 : 0) ++ */ ++ deptsiz.b.xfersize = ep->maxpacket; ++ deptsiz.b.pktcnt = 1; ++ ++ if (core_if->dma_desc_enable == 0) { ++ dwc_write_reg32(&out_regs->doeptsiz, deptsiz.d32); ++ } else { ++ dma_desc = core_if->dev_if->out_desc_addr; ++ ++ /** DMA Descriptor Setup */ ++ dma_desc->status.b.bs = BS_HOST_BUSY; ++ dma_desc->status.b.l = 1; ++ dma_desc->status.b.ioc = 1; ++ dma_desc->status.b.bytes = ep->maxpacket; ++ dma_desc->buf = ep->dma_addr; ++ dma_desc->status.b.bs = BS_HOST_READY; ++ ++ /** DOEPDMA0 Register write */ ++ dwc_write_reg32(&out_regs->doepdma, ++ core_if->dev_if->dma_out_desc_addr); ++ } ++ ++ DWC_DEBUGPL(DBG_PCDV, ++ "IN len=%d xfersize=%d pktcnt=%d [%08x]\n", ++ ep->xfer_len, deptsiz.b.xfersize, deptsiz.b.pktcnt, ++ deptsiz.d32); ++ ++ /* Write the DMA register */ ++ if (core_if->hwcfg2.b.architecture == DWC_INT_DMA_ARCH) { ++ if (core_if->dma_desc_enable == 0) ++ dwc_write_reg32(&(out_regs->doepdma), ++ (uint32_t) ep->dma_addr); ++ } ++ ++ /* EP enable, IN data in FIFO */ ++ depctl.b.cnak = 1; ++ depctl.b.epena = 1; ++ dwc_write_reg32(&out_regs->doepctl, depctl.d32); ++ ++ } ++} ++ ++#ifdef DEBUG ++void dump_msg(const u8 * buf, unsigned int length) ++{ ++ unsigned int start, num, i; ++ char line[52], *p; ++ ++ if (length >= 512) ++ return; ++ start = 0; ++ while (length > 0) { ++ num = length < 16u ? length : 16u; ++ p = line; ++ for (i = 0; i < num; ++i) { ++ if (i == 8) ++ *p++ = ' '; ++ DWC_SPRINTF(p, " %02x", buf[i]); ++ p += 3; ++ } ++ *p = 0; ++ DWC_PRINTF("%6x: %s\n", start, line); ++ buf += num; ++ start += num; ++ length -= num; ++ } ++} ++#else ++static inline void dump_msg(const u8 * buf, unsigned int length) ++{ ++} ++#endif ++ ++/** ++ * This function writes a packet into the Tx FIFO associated with the ++ * EP. For non-periodic EPs the non-periodic Tx FIFO is written. For ++ * periodic EPs the periodic Tx FIFO associated with the EP is written ++ * with all packets for the next micro-frame. ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ * @param ep The EP to write packet for. ++ * @param dma Indicates if DMA is being used. ++ */ ++void dwc_otg_ep_write_packet(dwc_otg_core_if_t * core_if, dwc_ep_t * ep, ++ int dma) ++{ ++ /** ++ * The buffer is padded to DWORD on a per packet basis in ++ * slave/dma mode if the MPS is not DWORD aligned. The last ++ * packet, if short, is also padded to a multiple of DWORD. ++ * ++ * ep->xfer_buff always starts DWORD aligned in memory and is a ++ * multiple of DWORD in length ++ * ++ * ep->xfer_len can be any number of bytes ++ * ++ * ep->xfer_count is a multiple of ep->maxpacket until the last ++ * packet ++ * ++ * FIFO access is DWORD */ ++ ++ uint32_t i; ++ uint32_t byte_count; ++ uint32_t dword_count; ++ uint32_t *fifo; ++ uint32_t *data_buff = (uint32_t *) ep->xfer_buff; ++ ++ DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "%s(%p,%p)\n", __func__, core_if, ++ ep); ++ if (ep->xfer_count >= ep->xfer_len) { ++ DWC_WARN("%s() No data for EP%d!!!\n", __func__, ep->num); ++ return; ++ } ++ ++ /* Find the byte length of the packet either short packet or MPS */ ++ if ((ep->xfer_len - ep->xfer_count) < ep->maxpacket) { ++ byte_count = ep->xfer_len - ep->xfer_count; ++ } else { ++ byte_count = ep->maxpacket; ++ } ++ ++ /* Find the DWORD length, padded by extra bytes as neccessary if MPS ++ * is not a multiple of DWORD */ ++ dword_count = (byte_count + 3) / 4; ++ ++#ifdef VERBOSE ++ dump_msg(ep->xfer_buff, byte_count); ++#endif ++ ++ /**@todo NGS Where are the Periodic Tx FIFO addresses ++ * intialized? What should this be? */ ++ ++ fifo = core_if->data_fifo[ep->num]; ++ ++ DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "fifo=%p buff=%p *p=%08x bc=%d\n", ++ fifo, data_buff, *data_buff, byte_count); ++ ++ if (!dma) { ++ for (i = 0; i < dword_count; i++, data_buff++) { ++ dwc_write_reg32(fifo, *data_buff); ++ } ++ } ++ ++ ep->xfer_count += byte_count; ++ ep->xfer_buff += byte_count; ++ ep->dma_addr += byte_count; ++} ++ ++/** ++ * Set the EP STALL. ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ * @param ep The EP to set the stall on. ++ */ ++void dwc_otg_ep_set_stall(dwc_otg_core_if_t * core_if, dwc_ep_t * ep) ++{ ++ depctl_data_t depctl; ++ volatile uint32_t *depctl_addr; ++ ++ DWC_DEBUGPL(DBG_PCD, "%s ep%d-%s\n", __func__, ep->num, ++ (ep->is_in ? "IN" : "OUT")); ++ ++ if (ep->is_in == 1) { ++ depctl_addr = &(core_if->dev_if->in_ep_regs[ep->num]->diepctl); ++ depctl.d32 = dwc_read_reg32(depctl_addr); ++ ++ /* set the disable and stall bits */ ++ if (depctl.b.epena) { ++ depctl.b.epdis = 1; ++ } ++ depctl.b.stall = 1; ++ dwc_write_reg32(depctl_addr, depctl.d32); ++ } else { ++ depctl_addr = &(core_if->dev_if->out_ep_regs[ep->num]->doepctl); ++ depctl.d32 = dwc_read_reg32(depctl_addr); ++ ++ /* set the stall bit */ ++ depctl.b.stall = 1; ++ dwc_write_reg32(depctl_addr, depctl.d32); ++ } ++ ++ DWC_DEBUGPL(DBG_PCD, "DEPCTL=%0x\n", dwc_read_reg32(depctl_addr)); ++ ++ return; ++} ++ ++/** ++ * Clear the EP STALL. ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ * @param ep The EP to clear stall from. ++ */ ++void dwc_otg_ep_clear_stall(dwc_otg_core_if_t * core_if, dwc_ep_t * ep) ++{ ++ depctl_data_t depctl; ++ volatile uint32_t *depctl_addr; ++ ++ DWC_DEBUGPL(DBG_PCD, "%s ep%d-%s\n", __func__, ep->num, ++ (ep->is_in ? "IN" : "OUT")); ++ ++ if (ep->is_in == 1) { ++ depctl_addr = &(core_if->dev_if->in_ep_regs[ep->num]->diepctl); ++ } else { ++ depctl_addr = &(core_if->dev_if->out_ep_regs[ep->num]->doepctl); ++ } ++ ++ depctl.d32 = dwc_read_reg32(depctl_addr); ++ ++ /* clear the stall bits */ ++ depctl.b.stall = 0; ++ ++ /* ++ * USB Spec 9.4.5: For endpoints using data toggle, regardless ++ * of whether an endpoint has the Halt feature set, a ++ * ClearFeature(ENDPOINT_HALT) request always results in the ++ * data toggle being reinitialized to DATA0. ++ */ ++ if (ep->type == DWC_OTG_EP_TYPE_INTR || ++ ep->type == DWC_OTG_EP_TYPE_BULK) { ++ depctl.b.setd0pid = 1; /* DATA0 */ ++ } ++ ++ dwc_write_reg32(depctl_addr, depctl.d32); ++ DWC_DEBUGPL(DBG_PCD, "DEPCTL=%0x\n", dwc_read_reg32(depctl_addr)); ++ return; ++} ++ ++/** ++ * This function reads a packet from the Rx FIFO into the destination ++ * buffer. To read SETUP data use dwc_otg_read_setup_packet. ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ * @param dest Destination buffer for the packet. ++ * @param bytes Number of bytes to copy to the destination. ++ */ ++void dwc_otg_read_packet(dwc_otg_core_if_t * core_if, ++ uint8_t * dest, uint16_t bytes) ++{ ++ int i; ++ int word_count = (bytes + 3) / 4; ++ ++ volatile uint32_t *fifo = core_if->data_fifo[0]; ++ uint32_t *data_buff = (uint32_t *) dest; ++ ++ /** ++ * @todo Account for the case where _dest is not dword aligned. This ++ * requires reading data from the FIFO into a uint32_t temp buffer, ++ * then moving it into the data buffer. ++ */ ++ ++ DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "%s(%p,%p,%d)\n", __func__, ++ core_if, dest, bytes); ++ ++ for (i = 0; i < word_count; i++, data_buff++) { ++ *data_buff = dwc_read_reg32(fifo); ++ } ++ ++ return; ++} ++ ++/** ++ * This functions reads the device registers and prints them ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ */ ++void dwc_otg_dump_dev_registers(dwc_otg_core_if_t * core_if) ++{ ++ int i; ++ volatile uint32_t *addr; ++ ++ DWC_PRINTF("Device Global Registers\n"); ++ addr = &core_if->dev_if->dev_global_regs->dcfg; ++ DWC_PRINTF("DCFG @0x%08X : 0x%08X\n", (uint32_t) addr, ++ dwc_read_reg32(addr)); ++ addr = &core_if->dev_if->dev_global_regs->dctl; ++ DWC_PRINTF("DCTL @0x%08X : 0x%08X\n", (uint32_t) addr, ++ dwc_read_reg32(addr)); ++ addr = &core_if->dev_if->dev_global_regs->dsts; ++ DWC_PRINTF("DSTS @0x%08X : 0x%08X\n", (uint32_t) addr, ++ dwc_read_reg32(addr)); ++ addr = &core_if->dev_if->dev_global_regs->diepmsk; ++ DWC_PRINTF("DIEPMSK @0x%08X : 0x%08X\n", (uint32_t) addr, ++ dwc_read_reg32(addr)); ++ addr = &core_if->dev_if->dev_global_regs->doepmsk; ++ DWC_PRINTF("DOEPMSK @0x%08X : 0x%08X\n", (uint32_t) addr, ++ dwc_read_reg32(addr)); ++ addr = &core_if->dev_if->dev_global_regs->daint; ++ DWC_PRINTF("DAINT @0x%08X : 0x%08X\n", (uint32_t) addr, ++ dwc_read_reg32(addr)); ++ addr = &core_if->dev_if->dev_global_regs->daintmsk; ++ DWC_PRINTF("DAINTMSK @0x%08X : 0x%08X\n", (uint32_t) addr, ++ dwc_read_reg32(addr)); ++ addr = &core_if->dev_if->dev_global_regs->dtknqr1; ++ DWC_PRINTF("DTKNQR1 @0x%08X : 0x%08X\n", (uint32_t) addr, ++ dwc_read_reg32(addr)); ++ if (core_if->hwcfg2.b.dev_token_q_depth > 6) { ++ addr = &core_if->dev_if->dev_global_regs->dtknqr2; ++ DWC_PRINTF("DTKNQR2 @0x%08X : 0x%08X\n", ++ (uint32_t) addr, dwc_read_reg32(addr)); ++ } ++ ++ addr = &core_if->dev_if->dev_global_regs->dvbusdis; ++ DWC_PRINTF("DVBUSID @0x%08X : 0x%08X\n", (uint32_t) addr, ++ dwc_read_reg32(addr)); ++ ++ addr = &core_if->dev_if->dev_global_regs->dvbuspulse; ++ DWC_PRINTF("DVBUSPULSE @0x%08X : 0x%08X\n", ++ (uint32_t) addr, dwc_read_reg32(addr)); ++ ++ addr = &core_if->dev_if->dev_global_regs->dtknqr3_dthrctl; ++ DWC_PRINTF("DTKNQR3_DTHRCTL @0x%08X : 0x%08X\n", ++ (uint32_t) addr, dwc_read_reg32(addr)); ++ ++ if (core_if->hwcfg2.b.dev_token_q_depth > 22) { ++ addr = &core_if->dev_if->dev_global_regs->dtknqr4_fifoemptymsk; ++ DWC_PRINTF("DTKNQR4 @0x%08X : 0x%08X\n", ++ (uint32_t) addr, dwc_read_reg32(addr)); ++ } ++ ++ addr = &core_if->dev_if->dev_global_regs->dtknqr4_fifoemptymsk; ++ DWC_PRINTF("FIFOEMPMSK @0x%08X : 0x%08X\n", (uint32_t) addr, ++ dwc_read_reg32(addr)); ++ ++ addr = &core_if->dev_if->dev_global_regs->deachint; ++ DWC_PRINTF("DEACHINT @0x%08X : 0x%08X\n", (uint32_t) addr, ++ dwc_read_reg32(addr)); ++ addr = &core_if->dev_if->dev_global_regs->deachintmsk; ++ DWC_PRINTF("DEACHINTMSK @0x%08X : 0x%08X\n", (uint32_t) addr, ++ dwc_read_reg32(addr)); ++ ++ for (i = 0; i <= core_if->dev_if->num_in_eps; i++) { ++ addr = &core_if->dev_if->dev_global_regs->diepeachintmsk[i]; ++ DWC_PRINTF("DIEPEACHINTMSK[%d] @0x%08X : 0x%08X\n", i, ++ (uint32_t) addr, dwc_read_reg32(addr)); ++ } ++ ++ for (i = 0; i <= core_if->dev_if->num_out_eps; i++) { ++ addr = &core_if->dev_if->dev_global_regs->doepeachintmsk[i]; ++ DWC_PRINTF("DOEPEACHINTMSK[%d] @0x%08X : 0x%08X\n", i, ++ (uint32_t) addr, dwc_read_reg32(addr)); ++ } ++ ++ for (i = 0; i <= core_if->dev_if->num_in_eps; i++) { ++ DWC_PRINTF("Device IN EP %d Registers\n", i); ++ addr = &core_if->dev_if->in_ep_regs[i]->diepctl; ++ DWC_PRINTF("DIEPCTL @0x%08X : 0x%08X\n", (uint32_t) addr, ++ dwc_read_reg32(addr)); ++ addr = &core_if->dev_if->in_ep_regs[i]->diepint; ++ DWC_PRINTF("DIEPINT @0x%08X : 0x%08X\n", (uint32_t) addr, ++ dwc_read_reg32(addr)); ++ addr = &core_if->dev_if->in_ep_regs[i]->dieptsiz; ++ DWC_PRINTF("DIETSIZ @0x%08X : 0x%08X\n", (uint32_t) addr, ++ dwc_read_reg32(addr)); ++ addr = &core_if->dev_if->in_ep_regs[i]->diepdma; ++ DWC_PRINTF("DIEPDMA @0x%08X : 0x%08X\n", (uint32_t) addr, ++ dwc_read_reg32(addr)); ++ addr = &core_if->dev_if->in_ep_regs[i]->dtxfsts; ++ DWC_PRINTF("DTXFSTS @0x%08X : 0x%08X\n", (uint32_t) addr, ++ dwc_read_reg32(addr)); ++ addr = &core_if->dev_if->in_ep_regs[i]->diepdmab; ++ DWC_PRINTF("DIEPDMAB @0x%08X : 0x%08X\n", (uint32_t) addr, ++ 0 /*dwc_read_reg32(addr) */ ); ++ } ++ ++ for (i = 0; i <= core_if->dev_if->num_out_eps; i++) { ++ DWC_PRINTF("Device OUT EP %d Registers\n", i); ++ addr = &core_if->dev_if->out_ep_regs[i]->doepctl; ++ DWC_PRINTF("DOEPCTL @0x%08X : 0x%08X\n", (uint32_t) addr, ++ dwc_read_reg32(addr)); ++ addr = &core_if->dev_if->out_ep_regs[i]->doepfn; ++ DWC_PRINTF("DOEPFN @0x%08X : 0x%08X\n", (uint32_t) addr, ++ dwc_read_reg32(addr)); ++ addr = &core_if->dev_if->out_ep_regs[i]->doepint; ++ DWC_PRINTF("DOEPINT @0x%08X : 0x%08X\n", (uint32_t) addr, ++ dwc_read_reg32(addr)); ++ addr = &core_if->dev_if->out_ep_regs[i]->doeptsiz; ++ DWC_PRINTF("DOETSIZ @0x%08X : 0x%08X\n", (uint32_t) addr, ++ dwc_read_reg32(addr)); ++ addr = &core_if->dev_if->out_ep_regs[i]->doepdma; ++ DWC_PRINTF("DOEPDMA @0x%08X : 0x%08X\n", (uint32_t) addr, ++ dwc_read_reg32(addr)); ++ if (core_if->dma_enable) { /* Don't access this register in SLAVE mode */ ++ addr = &core_if->dev_if->out_ep_regs[i]->doepdmab; ++ DWC_PRINTF("DOEPDMAB @0x%08X : 0x%08X\n", ++ (uint32_t) addr, dwc_read_reg32(addr)); ++ } ++ ++ } ++} ++ ++/** ++ * This functions reads the SPRAM and prints its content ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ */ ++void dwc_otg_dump_spram(dwc_otg_core_if_t * core_if) ++{ ++ volatile uint8_t *addr, *start_addr, *end_addr; ++ ++ DWC_PRINTF("SPRAM Data:\n"); ++ start_addr = (void *)core_if->core_global_regs; ++ DWC_PRINTF("Base Address: 0x%8X\n", (uint32_t) start_addr); ++ start_addr += 0x00028000; ++ end_addr = (void *)core_if->core_global_regs; ++ end_addr += 0x000280e0; ++ ++ for (addr = start_addr; addr < end_addr; addr += 16) { ++ DWC_PRINTF ++ ("0x%8X:\t%2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X\n", ++ (uint32_t) addr, addr[0], addr[1], addr[2], addr[3], ++ addr[4], addr[5], addr[6], addr[7], addr[8], addr[9], ++ addr[10], addr[11], addr[12], addr[13], addr[14], addr[15] ++ ); ++ } ++ ++ return; ++} ++ ++/** ++ * This function reads the host registers and prints them ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ */ ++void dwc_otg_dump_host_registers(dwc_otg_core_if_t * core_if) ++{ ++ int i; ++ volatile uint32_t *addr; ++ ++ DWC_PRINTF("Host Global Registers\n"); ++ addr = &core_if->host_if->host_global_regs->hcfg; ++ DWC_PRINTF("HCFG @0x%08X : 0x%08X\n", (uint32_t) addr, ++ dwc_read_reg32(addr)); ++ addr = &core_if->host_if->host_global_regs->hfir; ++ DWC_PRINTF("HFIR @0x%08X : 0x%08X\n", (uint32_t) addr, ++ dwc_read_reg32(addr)); ++ addr = &core_if->host_if->host_global_regs->hfnum; ++ DWC_PRINTF("HFNUM @0x%08X : 0x%08X\n", (uint32_t) addr, ++ dwc_read_reg32(addr)); ++ addr = &core_if->host_if->host_global_regs->hptxsts; ++ DWC_PRINTF("HPTXSTS @0x%08X : 0x%08X\n", (uint32_t) addr, ++ dwc_read_reg32(addr)); ++ addr = &core_if->host_if->host_global_regs->haint; ++ DWC_PRINTF("HAINT @0x%08X : 0x%08X\n", (uint32_t) addr, ++ dwc_read_reg32(addr)); ++ addr = &core_if->host_if->host_global_regs->haintmsk; ++ DWC_PRINTF("HAINTMSK @0x%08X : 0x%08X\n", (uint32_t) addr, ++ dwc_read_reg32(addr)); ++ if (core_if->dma_desc_enable) { ++ addr = &core_if->host_if->host_global_regs->hflbaddr; ++ DWC_PRINTF("HFLBADDR @0x%08X : 0x%08X\n",(uint32_t) addr, ++ dwc_read_reg32(addr)); ++ } ++ ++ addr = core_if->host_if->hprt0; ++ DWC_PRINTF("HPRT0 @0x%08X : 0x%08X\n", (uint32_t) addr, ++ dwc_read_reg32(addr)); ++ ++ for (i = 0; i < core_if->core_params->host_channels; i++) { ++ DWC_PRINTF("Host Channel %d Specific Registers\n", i); ++ addr = &core_if->host_if->hc_regs[i]->hcchar; ++ DWC_PRINTF("HCCHAR @0x%08X : 0x%08X\n", (uint32_t) addr, ++ dwc_read_reg32(addr)); ++ addr = &core_if->host_if->hc_regs[i]->hcsplt; ++ DWC_PRINTF("HCSPLT @0x%08X : 0x%08X\n", (uint32_t) addr, ++ dwc_read_reg32(addr)); ++ addr = &core_if->host_if->hc_regs[i]->hcint; ++ DWC_PRINTF("HCINT @0x%08X : 0x%08X\n", (uint32_t) addr, ++ dwc_read_reg32(addr)); ++ addr = &core_if->host_if->hc_regs[i]->hcintmsk; ++ DWC_PRINTF("HCINTMSK @0x%08X : 0x%08X\n", (uint32_t) addr, ++ dwc_read_reg32(addr)); ++ addr = &core_if->host_if->hc_regs[i]->hctsiz; ++ DWC_PRINTF("HCTSIZ @0x%08X : 0x%08X\n", (uint32_t) addr, ++ dwc_read_reg32(addr)); ++ addr = &core_if->host_if->hc_regs[i]->hcdma; ++ DWC_PRINTF("HCDMA @0x%08X : 0x%08X\n", (uint32_t) addr, ++ dwc_read_reg32(addr)); ++ if (core_if->dma_desc_enable) { ++ addr=&core_if->host_if->hc_regs[i]->hcdmab; ++ DWC_PRINTF("HCDMAB @0x%08X : 0x%08X\n",(uint32_t) addr, dwc_read_reg32(addr)); ++ } ++ ++ } ++ return; ++} ++ ++/** ++ * This function reads the core global registers and prints them ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ */ ++void dwc_otg_dump_global_registers(dwc_otg_core_if_t * core_if) ++{ ++ int i; ++ volatile uint32_t *addr; ++ ++ DWC_PRINTF("Core Global Registers\n"); ++ addr = &core_if->core_global_regs->gotgctl; ++ DWC_PRINTF("GOTGCTL @0x%08X : 0x%08X\n", (uint32_t) addr, ++ dwc_read_reg32(addr)); ++ addr = &core_if->core_global_regs->gotgint; ++ DWC_PRINTF("GOTGINT @0x%08X : 0x%08X\n", (uint32_t) addr, ++ dwc_read_reg32(addr)); ++ addr = &core_if->core_global_regs->gahbcfg; ++ DWC_PRINTF("GAHBCFG @0x%08X : 0x%08X\n", (uint32_t) addr, ++ dwc_read_reg32(addr)); ++ addr = &core_if->core_global_regs->gusbcfg; ++ DWC_PRINTF("GUSBCFG @0x%08X : 0x%08X\n", (uint32_t) addr, ++ dwc_read_reg32(addr)); ++ addr = &core_if->core_global_regs->grstctl; ++ DWC_PRINTF("GRSTCTL @0x%08X : 0x%08X\n", (uint32_t) addr, ++ dwc_read_reg32(addr)); ++ addr = &core_if->core_global_regs->gintsts; ++ DWC_PRINTF("GINTSTS @0x%08X : 0x%08X\n", (uint32_t) addr, ++ dwc_read_reg32(addr)); ++ addr = &core_if->core_global_regs->gintmsk; ++ DWC_PRINTF("GINTMSK @0x%08X : 0x%08X\n", (uint32_t) addr, ++ dwc_read_reg32(addr)); ++ addr = &core_if->core_global_regs->grxstsr; ++ DWC_PRINTF("GRXSTSR @0x%08X : 0x%08X\n", (uint32_t) addr, ++ dwc_read_reg32(addr)); ++ addr = &core_if->core_global_regs->grxfsiz; ++ DWC_PRINTF("GRXFSIZ @0x%08X : 0x%08X\n", (uint32_t) addr, ++ dwc_read_reg32(addr)); ++ addr = &core_if->core_global_regs->gnptxfsiz; ++ DWC_PRINTF("GNPTXFSIZ @0x%08X : 0x%08X\n", (uint32_t) addr, ++ dwc_read_reg32(addr)); ++ addr = &core_if->core_global_regs->gnptxsts; ++ DWC_PRINTF("GNPTXSTS @0x%08X : 0x%08X\n", (uint32_t) addr, ++ dwc_read_reg32(addr)); ++ addr = &core_if->core_global_regs->gi2cctl; ++ DWC_PRINTF("GI2CCTL @0x%08X : 0x%08X\n", (uint32_t) addr, ++ dwc_read_reg32(addr)); ++ addr = &core_if->core_global_regs->gpvndctl; ++ DWC_PRINTF("GPVNDCTL @0x%08X : 0x%08X\n", (uint32_t) addr, ++ dwc_read_reg32(addr)); ++ addr = &core_if->core_global_regs->ggpio; ++ DWC_PRINTF("GGPIO @0x%08X : 0x%08X\n", (uint32_t) addr, ++ dwc_read_reg32(addr)); ++ addr = &core_if->core_global_regs->guid; ++ DWC_PRINTF("GUID @0x%08X : 0x%08X\n", (uint32_t) addr, ++ dwc_read_reg32(addr)); ++ addr = &core_if->core_global_regs->gsnpsid; ++ DWC_PRINTF("GSNPSID @0x%08X : 0x%08X\n", (uint32_t) addr, ++ dwc_read_reg32(addr)); ++ addr = &core_if->core_global_regs->ghwcfg1; ++ DWC_PRINTF("GHWCFG1 @0x%08X : 0x%08X\n", (uint32_t) addr, ++ dwc_read_reg32(addr)); ++ addr = &core_if->core_global_regs->ghwcfg2; ++ DWC_PRINTF("GHWCFG2 @0x%08X : 0x%08X\n", (uint32_t) addr, ++ dwc_read_reg32(addr)); ++ addr = &core_if->core_global_regs->ghwcfg3; ++ DWC_PRINTF("GHWCFG3 @0x%08X : 0x%08X\n", (uint32_t) addr, ++ dwc_read_reg32(addr)); ++ addr = &core_if->core_global_regs->ghwcfg4; ++ DWC_PRINTF("GHWCFG4 @0x%08X : 0x%08X\n", (uint32_t) addr, ++ dwc_read_reg32(addr)); ++ addr = &core_if->core_global_regs->glpmcfg; ++ DWC_PRINTF("GLPMCFG @0x%08X : 0x%08X\n", (uint32_t) addr, ++ dwc_read_reg32(addr)); ++ addr = &core_if->core_global_regs->hptxfsiz; ++ DWC_PRINTF("HPTXFSIZ @0x%08X : 0x%08X\n", (uint32_t) addr, ++ dwc_read_reg32(addr)); ++ ++ for (i = 0; i < core_if->hwcfg4.b.num_dev_perio_in_ep; i++) { ++ addr = &core_if->core_global_regs->dptxfsiz_dieptxf[i]; ++ DWC_PRINTF("DPTXFSIZ[%d] @0x%08X : 0x%08X\n", i, ++ (uint32_t) addr, dwc_read_reg32(addr)); ++ } ++ addr = core_if->pcgcctl; ++ DWC_PRINTF("PCGCCTL @0x%08X : 0x%08X\n", (uint32_t) addr, ++ dwc_read_reg32(addr)); ++} ++ ++/** ++ * Flush a Tx FIFO. ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ * @param num Tx FIFO to flush. ++ */ ++void dwc_otg_flush_tx_fifo(dwc_otg_core_if_t * core_if, const int num) ++{ ++ dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs; ++ volatile grstctl_t greset = {.d32 = 0 }; ++ int count = 0; ++ ++ DWC_DEBUGPL((DBG_CIL | DBG_PCDV), "Flush Tx FIFO %d\n", num); ++ ++ greset.b.txfflsh = 1; ++ greset.b.txfnum = num; ++ dwc_write_reg32(&global_regs->grstctl, greset.d32); ++ ++ do { ++ greset.d32 = dwc_read_reg32(&global_regs->grstctl); ++ if (++count > 10000) { ++ DWC_WARN("%s() HANG! GRSTCTL=%0x GNPTXSTS=0x%08x\n", ++ __func__, greset.d32, ++ dwc_read_reg32(&global_regs->gnptxsts)); ++ break; ++ } ++ dwc_udelay(1); ++ } while (greset.b.txfflsh == 1); ++ ++ /* Wait for 3 PHY Clocks */ ++ dwc_udelay(1); ++} ++ ++/** ++ * Flush Rx FIFO. ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ */ ++void dwc_otg_flush_rx_fifo(dwc_otg_core_if_t * core_if) ++{ ++ dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs; ++ volatile grstctl_t greset = {.d32 = 0 }; ++ int count = 0; ++ ++ DWC_DEBUGPL((DBG_CIL | DBG_PCDV), "%s\n", __func__); ++ /* ++ * ++ */ ++ greset.b.rxfflsh = 1; ++ dwc_write_reg32(&global_regs->grstctl, greset.d32); ++ ++ do { ++ greset.d32 = dwc_read_reg32(&global_regs->grstctl); ++ if (++count > 10000) { ++ DWC_WARN("%s() HANG! GRSTCTL=%0x\n", __func__, ++ greset.d32); ++ break; ++ } ++ dwc_udelay(1); ++ } while (greset.b.rxfflsh == 1); ++ ++ /* Wait for 3 PHY Clocks */ ++ dwc_udelay(1); ++} ++ ++/** ++ * Do core a soft reset of the core. Be careful with this because it ++ * resets all the internal state machines of the core. ++ */ ++void dwc_otg_core_reset(dwc_otg_core_if_t * core_if) ++{ ++ dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs; ++ volatile grstctl_t greset = {.d32 = 0 }; ++ int count = 0; ++ ++ DWC_DEBUGPL(DBG_CILV, "%s\n", __func__); ++ /* Wait for AHB master IDLE state. */ ++ do { ++ dwc_udelay(10); ++ greset.d32 = dwc_read_reg32(&global_regs->grstctl); ++ if (++count > 100000) { ++ DWC_WARN("%s() HANG! AHB Idle GRSTCTL=%0x\n", __func__, ++ greset.d32); ++ return; ++ } ++ } ++ while (greset.b.ahbidle == 0); ++ ++ /* Core Soft Reset */ ++ count = 0; ++ greset.b.csftrst = 1; ++ dwc_write_reg32(&global_regs->grstctl, greset.d32); ++ do { ++ greset.d32 = dwc_read_reg32(&global_regs->grstctl); ++ if (++count > 10000) { ++ DWC_WARN("%s() HANG! Soft Reset GRSTCTL=%0x\n", ++ __func__, greset.d32); ++ break; ++ } ++ dwc_udelay(1); ++ } ++ while (greset.b.csftrst == 1); ++ ++ /* Wait for 3 PHY Clocks */ ++ dwc_mdelay(100); ++} ++ ++uint8_t dwc_otg_is_device_mode(dwc_otg_core_if_t * _core_if) ++{ ++ return (dwc_otg_mode(_core_if) != DWC_HOST_MODE); ++} ++ ++uint8_t dwc_otg_is_host_mode(dwc_otg_core_if_t * _core_if) ++{ ++ return (dwc_otg_mode(_core_if) == DWC_HOST_MODE); ++} ++ ++/** ++ * Register HCD callbacks. The callbacks are used to start and stop ++ * the HCD for interrupt processing. ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ * @param cb the HCD callback structure. ++ * @param p pointer to be passed to callback function (usb_hcd*). ++ */ ++void dwc_otg_cil_register_hcd_callbacks(dwc_otg_core_if_t * core_if, ++ dwc_otg_cil_callbacks_t * cb, void *p) ++{ ++ core_if->hcd_cb = cb; ++ cb->p = p; ++} ++ ++/** ++ * Register PCD callbacks. The callbacks are used to start and stop ++ * the PCD for interrupt processing. ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ * @param cb the PCD callback structure. ++ * @param p pointer to be passed to callback function (pcd*). ++ */ ++void dwc_otg_cil_register_pcd_callbacks(dwc_otg_core_if_t * core_if, ++ dwc_otg_cil_callbacks_t * cb, void *p) ++{ ++ core_if->pcd_cb = cb; ++ cb->p = p; ++} ++ ++#ifdef DWC_EN_ISOC ++ ++/** ++ * This function writes isoc data per 1 (micro)frame into tx fifo ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ * @param ep The EP to start the transfer on. ++ * ++ */ ++void write_isoc_frame_data(dwc_otg_core_if_t * core_if, dwc_ep_t * ep) ++{ ++ dwc_otg_dev_in_ep_regs_t *ep_regs; ++ dtxfsts_data_t txstatus = {.d32 = 0 }; ++ uint32_t len = 0; ++ uint32_t dwords; ++ ++ ep->xfer_len = ep->data_per_frame; ++ ep->xfer_count = 0; ++ ++ ep_regs = core_if->dev_if->in_ep_regs[ep->num]; ++ ++ len = ep->xfer_len - ep->xfer_count; ++ ++ if (len > ep->maxpacket) { ++ len = ep->maxpacket; ++ } ++ ++ dwords = (len + 3) / 4; ++ ++ /* While there is space in the queue and space in the FIFO and ++ * More data to tranfer, Write packets to the Tx FIFO */ ++ txstatus.d32 = ++ dwc_read_reg32(&core_if->dev_if->in_ep_regs[ep->num]->dtxfsts); ++ DWC_DEBUGPL(DBG_PCDV, "b4 dtxfsts[%d]=0x%08x\n", ep->num, txstatus.d32); ++ ++ while (txstatus.b.txfspcavail > dwords && ++ ep->xfer_count < ep->xfer_len && ep->xfer_len != 0) { ++ /* Write the FIFO */ ++ dwc_otg_ep_write_packet(core_if, ep, 0); ++ ++ len = ep->xfer_len - ep->xfer_count; ++ if (len > ep->maxpacket) { ++ len = ep->maxpacket; ++ } ++ ++ dwords = (len + 3) / 4; ++ txstatus.d32 = ++ dwc_read_reg32(&core_if->dev_if->in_ep_regs[ep->num]-> ++ dtxfsts); ++ DWC_DEBUGPL(DBG_PCDV, "dtxfsts[%d]=0x%08x\n", ep->num, ++ txstatus.d32); ++ } ++} ++ ++/** ++ * This function initializes a descriptor chain for Isochronous transfer ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ * @param ep The EP to start the transfer on. ++ * ++ */ ++void dwc_otg_iso_ep_start_frm_transfer(dwc_otg_core_if_t * core_if, ++ dwc_ep_t * ep) ++{ ++ deptsiz_data_t deptsiz = {.d32 = 0 }; ++ depctl_data_t depctl = {.d32 = 0 }; ++ dsts_data_t dsts = {.d32 = 0 }; ++ volatile uint32_t *addr; ++ ++ if (ep->is_in) { ++ addr = &core_if->dev_if->in_ep_regs[ep->num]->diepctl; ++ } else { ++ addr = &core_if->dev_if->out_ep_regs[ep->num]->doepctl; ++ } ++ ++ ep->xfer_len = ep->data_per_frame; ++ ep->xfer_count = 0; ++ ep->xfer_buff = ep->cur_pkt_addr; ++ ep->dma_addr = ep->cur_pkt_dma_addr; ++ ++ if (ep->is_in) { ++ /* Program the transfer size and packet count ++ * as follows: xfersize = N * maxpacket + ++ * short_packet pktcnt = N + (short_packet ++ * exist ? 1 : 0) ++ */ ++ deptsiz.b.xfersize = ep->xfer_len; ++ deptsiz.b.pktcnt = ++ (ep->xfer_len - 1 + ep->maxpacket) / ep->maxpacket; ++ deptsiz.b.mc = deptsiz.b.pktcnt; ++ dwc_write_reg32(&core_if->dev_if->in_ep_regs[ep->num]->dieptsiz, ++ deptsiz.d32); ++ ++ /* Write the DMA register */ ++ if (core_if->dma_enable) { ++ dwc_write_reg32(& ++ (core_if->dev_if->in_ep_regs[ep->num]-> ++ diepdma), (uint32_t) ep->dma_addr); ++ } ++ } else { ++ deptsiz.b.pktcnt = ++ (ep->xfer_len + (ep->maxpacket - 1)) / ep->maxpacket; ++ deptsiz.b.xfersize = deptsiz.b.pktcnt * ep->maxpacket; ++ ++ dwc_write_reg32(&core_if->dev_if->out_ep_regs[ep->num]-> ++ doeptsiz, deptsiz.d32); ++ ++ if (core_if->dma_enable) { ++ dwc_write_reg32(& ++ (core_if->dev_if->out_ep_regs[ep->num]-> ++ doepdma), (uint32_t) ep->dma_addr); ++ } ++ } ++ ++ /** Enable endpoint, clear nak */ ++ ++ depctl.d32 = 0; ++ if (ep->bInterval == 1) { ++ dsts.d32 = ++ dwc_read_reg32(&core_if->dev_if->dev_global_regs->dsts); ++ ep->next_frame = dsts.b.soffn + ep->bInterval; ++ ++ if (ep->next_frame & 0x1) { ++ depctl.b.setd1pid = 1; ++ } else { ++ depctl.b.setd0pid = 1; ++ } ++ } else { ++ ep->next_frame += ep->bInterval; ++ ++ if (ep->next_frame & 0x1) { ++ depctl.b.setd1pid = 1; ++ } else { ++ depctl.b.setd0pid = 1; ++ } ++ } ++ depctl.b.epena = 1; ++ depctl.b.cnak = 1; ++ ++ dwc_modify_reg32(addr, 0, depctl.d32); ++ depctl.d32 = dwc_read_reg32(addr); ++ ++ if (ep->is_in && core_if->dma_enable == 0) { ++ write_isoc_frame_data(core_if, ep); ++ } ++ ++} ++#endif /* DWC_EN_ISOC */ ++ ++static void dwc_otg_set_uninitialized(int32_t * p, int size) ++{ ++ int i; ++ for (i = 0; i < size; i++) { ++ p[i] = -1; ++ } ++} ++ ++static int dwc_otg_param_initialized(int32_t val) ++{ ++ return val != -1; ++} ++ ++static int dwc_otg_setup_params(dwc_otg_core_if_t * core_if) ++{ ++ int i; ++ core_if->core_params = DWC_ALLOC(sizeof(*core_if->core_params)); ++ if (!core_if->core_params) { ++ return -DWC_E_NO_MEMORY; ++ } ++ dwc_otg_set_uninitialized((int32_t *) core_if->core_params, ++ sizeof(*core_if->core_params) / ++ sizeof(int32_t)); ++ DWC_PRINTF("Setting default values for core params\n"); ++ dwc_otg_set_param_otg_cap(core_if, dwc_param_otg_cap_default); ++ dwc_otg_set_param_dma_enable(core_if, dwc_param_dma_enable_default); ++ dwc_otg_set_param_dma_desc_enable(core_if, ++ dwc_param_dma_desc_enable_default); ++ dwc_otg_set_param_opt(core_if, dwc_param_opt_default); ++ dwc_otg_set_param_dma_burst_size(core_if, ++ dwc_param_dma_burst_size_default); ++ dwc_otg_set_param_host_support_fs_ls_low_power(core_if, ++ dwc_param_host_support_fs_ls_low_power_default); ++ dwc_otg_set_param_enable_dynamic_fifo(core_if, ++ dwc_param_enable_dynamic_fifo_default); ++ dwc_otg_set_param_data_fifo_size(core_if, ++ dwc_param_data_fifo_size_default); ++ dwc_otg_set_param_dev_rx_fifo_size(core_if, ++ dwc_param_dev_rx_fifo_size_default); ++ dwc_otg_set_param_dev_nperio_tx_fifo_size(core_if, ++ dwc_param_dev_nperio_tx_fifo_size_default); ++ dwc_otg_set_param_host_rx_fifo_size(core_if, ++ dwc_param_host_rx_fifo_size_default); ++ dwc_otg_set_param_host_nperio_tx_fifo_size(core_if, ++ dwc_param_host_nperio_tx_fifo_size_default); ++ dwc_otg_set_param_host_perio_tx_fifo_size(core_if, ++ dwc_param_host_perio_tx_fifo_size_default); ++ dwc_otg_set_param_max_transfer_size(core_if, ++ dwc_param_max_transfer_size_default); ++ dwc_otg_set_param_max_packet_count(core_if, ++ dwc_param_max_packet_count_default); ++ dwc_otg_set_param_host_channels(core_if, ++ dwc_param_host_channels_default); ++ dwc_otg_set_param_dev_endpoints(core_if, ++ dwc_param_dev_endpoints_default); ++ dwc_otg_set_param_phy_type(core_if, dwc_param_phy_type_default); ++ dwc_otg_set_param_speed(core_if, dwc_param_speed_default); ++ dwc_otg_set_param_host_ls_low_power_phy_clk(core_if, ++ dwc_param_host_ls_low_power_phy_clk_default); ++ dwc_otg_set_param_phy_ulpi_ddr(core_if, dwc_param_phy_ulpi_ddr_default); ++ dwc_otg_set_param_phy_ulpi_ext_vbus(core_if, ++ dwc_param_phy_ulpi_ext_vbus_default); ++ dwc_otg_set_param_phy_utmi_width(core_if, ++ dwc_param_phy_utmi_width_default); ++ dwc_otg_set_param_ts_dline(core_if, dwc_param_ts_dline_default); ++ dwc_otg_set_param_i2c_enable(core_if, dwc_param_i2c_enable_default); ++ dwc_otg_set_param_ulpi_fs_ls(core_if, dwc_param_ulpi_fs_ls_default); ++ dwc_otg_set_param_en_multiple_tx_fifo(core_if, ++ dwc_param_en_multiple_tx_fifo_default); ++ for (i = 0; i < 15; i++) { ++ dwc_otg_set_param_dev_perio_tx_fifo_size(core_if, ++ dwc_param_dev_perio_tx_fifo_size_default, ++ i); ++ } ++ ++ for (i = 0; i < 15; i++) { ++ dwc_otg_set_param_dev_tx_fifo_size(core_if, ++ dwc_param_dev_tx_fifo_size_default, ++ i); ++ } ++ dwc_otg_set_param_thr_ctl(core_if, dwc_param_thr_ctl_default); ++ dwc_otg_set_param_mpi_enable(core_if, dwc_param_mpi_enable_default); ++ dwc_otg_set_param_pti_enable(core_if, dwc_param_pti_enable_default); ++ dwc_otg_set_param_lpm_enable(core_if, dwc_param_lpm_enable_default); ++ dwc_otg_set_param_ic_usb_cap(core_if, dwc_param_ic_usb_cap_default); ++ dwc_otg_set_param_tx_thr_length(core_if, ++ dwc_param_tx_thr_length_default); ++ dwc_otg_set_param_rx_thr_length(core_if, ++ dwc_param_rx_thr_length_default); ++ dwc_otg_set_param_ahb_thr_ratio(core_if, dwc_param_ahb_thr_ratio_default); ++ DWC_PRINTF("Finished setting default values for core params\n"); ++ return 0; ++} ++ ++uint8_t dwc_otg_is_dma_enable(dwc_otg_core_if_t * core_if) ++{ ++ return core_if->dma_enable; ++} ++ ++/* Checks if the parameter is outside of its valid range of values */ ++#define DWC_OTG_PARAM_TEST(_param_, _low_, _high_) \ ++ (((_param_) < (_low_)) || \ ++ ((_param_) > (_high_))) ++ ++/* Parameter access functions */ ++int dwc_otg_set_param_otg_cap(dwc_otg_core_if_t * core_if, int32_t val) ++{ ++ int valid; ++ int retval = 0; ++ if (DWC_OTG_PARAM_TEST(val, 0, 2)) { ++ DWC_WARN("Wrong value for otg_cap parameter\n"); ++ DWC_WARN("otg_cap parameter must be 0,1 or 2\n"); ++ retval = -DWC_E_INVALID; ++ goto out; ++ } ++ ++ valid = 1; ++ switch (val) { ++ case DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE: ++ if (core_if->hwcfg2.b.op_mode != ++ DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG) ++ valid = 0; ++ break; ++ case DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE: ++ if ((core_if->hwcfg2.b.op_mode != ++ DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG) ++ && (core_if->hwcfg2.b.op_mode != ++ DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG) ++ && (core_if->hwcfg2.b.op_mode != ++ DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE) ++ && (core_if->hwcfg2.b.op_mode != ++ DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST)) { ++ valid = 0; ++ } ++ break; ++ case DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE: ++ /* always valid */ ++ break; ++ } ++ if (!valid) { ++ if (dwc_otg_param_initialized(core_if->core_params->otg_cap)) { ++ DWC_ERROR ++ ("%d invalid for otg_cap paremter. Check HW configuration.\n", ++ val); ++ } ++ val = ++ (((core_if->hwcfg2.b.op_mode == ++ DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG) ++ || (core_if->hwcfg2.b.op_mode == ++ DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG) ++ || (core_if->hwcfg2.b.op_mode == ++ DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE) ++ || (core_if->hwcfg2.b.op_mode == ++ DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST)) ? ++ DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE : ++ DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE); ++ retval = -DWC_E_INVALID; ++ } ++ ++ core_if->core_params->otg_cap = val; ++ out: ++ return retval; ++} ++ ++int32_t dwc_otg_get_param_otg_cap(dwc_otg_core_if_t * core_if) ++{ ++ return core_if->core_params->otg_cap; ++} ++ ++int dwc_otg_set_param_opt(dwc_otg_core_if_t * core_if, int32_t val) ++{ ++ if (DWC_OTG_PARAM_TEST(val, 0, 1)) { ++ DWC_WARN("Wrong value for opt parameter\n"); ++ return -DWC_E_INVALID; ++ } ++ core_if->core_params->opt = val; ++ return 0; ++} ++ ++int32_t dwc_otg_get_param_opt(dwc_otg_core_if_t * core_if) ++{ ++ return core_if->core_params->opt; ++} ++ ++int dwc_otg_set_param_dma_enable(dwc_otg_core_if_t * core_if, int32_t val) ++{ ++ int retval = 0; ++ if (DWC_OTG_PARAM_TEST(val, 0, 1)) { ++ DWC_WARN("Wrong value for dma enable\n"); ++ return -DWC_E_INVALID; ++ } ++ ++ if ((val == 1) && (core_if->hwcfg2.b.architecture == 0)) { ++ if (dwc_otg_param_initialized(core_if->core_params->dma_enable)) { ++ DWC_ERROR ++ ("%d invalid for dma_enable paremter. Check HW configuration.\n", ++ val); ++ } ++ val = 0; ++ retval = -DWC_E_INVALID; ++ } ++ ++ core_if->core_params->dma_enable = val; ++ if (val == 0) { ++ dwc_otg_set_param_dma_desc_enable(core_if, 0); ++ } ++ return retval; ++} ++ ++int32_t dwc_otg_get_param_dma_enable(dwc_otg_core_if_t * core_if) ++{ ++ return core_if->core_params->dma_enable; ++} ++ ++int dwc_otg_set_param_dma_desc_enable(dwc_otg_core_if_t * core_if, int32_t val) ++{ ++ int retval = 0; ++ if (DWC_OTG_PARAM_TEST(val, 0, 1)) { ++ DWC_WARN("Wrong value for dma_enable\n"); ++ DWC_WARN("dma_desc_enable must be 0 or 1\n"); ++ return -DWC_E_INVALID; ++ } ++ ++ if ((val == 1) ++ && ((dwc_otg_get_param_dma_enable(core_if) == 0) ++ || (core_if->hwcfg4.b.desc_dma == 0))) { ++ if (dwc_otg_param_initialized ++ (core_if->core_params->dma_desc_enable)) { ++ DWC_ERROR ++ ("%d invalid for dma_desc_enable paremter. Check HW configuration.\n", ++ val); ++ } ++ val = 0; ++ retval = -DWC_E_INVALID; ++ } ++ core_if->core_params->dma_desc_enable = val; ++ return retval; ++} ++ ++int32_t dwc_otg_get_param_dma_desc_enable(dwc_otg_core_if_t * core_if) ++{ ++ return core_if->core_params->dma_desc_enable; ++} ++ ++int dwc_otg_set_param_host_support_fs_ls_low_power(dwc_otg_core_if_t * core_if, ++ int32_t val) ++{ ++ if (DWC_OTG_PARAM_TEST(val, 0, 1)) { ++ DWC_WARN("Wrong value for host_support_fs_low_power\n"); ++ DWC_WARN("host_support_fs_low_power must be 0 or 1\n"); ++ return -DWC_E_INVALID; ++ } ++ core_if->core_params->host_support_fs_ls_low_power = val; ++ return 0; ++} ++ ++int32_t dwc_otg_get_param_host_support_fs_ls_low_power(dwc_otg_core_if_t * ++ core_if) ++{ ++ return core_if->core_params->host_support_fs_ls_low_power; ++} ++ ++int dwc_otg_set_param_enable_dynamic_fifo(dwc_otg_core_if_t * core_if, ++ int32_t val) ++{ ++ int retval = 0; ++ if (DWC_OTG_PARAM_TEST(val, 0, 1)) { ++ DWC_WARN("Wrong value for enable_dynamic_fifo\n"); ++ DWC_WARN("enable_dynamic_fifo must be 0 or 1\n"); ++ return -DWC_E_INVALID; ++ } ++ ++ if ((val == 1) && (core_if->hwcfg2.b.dynamic_fifo == 0)) { ++ if (dwc_otg_param_initialized ++ (core_if->core_params->enable_dynamic_fifo)) { ++ DWC_ERROR ++ ("%d invalid for enable_dynamic_fifo paremter. Check HW configuration.\n", ++ val); ++ } ++ val = 0; ++ retval = -DWC_E_INVALID; ++ } ++ core_if->core_params->enable_dynamic_fifo = val; ++ return retval; ++} ++ ++int32_t dwc_otg_get_param_enable_dynamic_fifo(dwc_otg_core_if_t * core_if) ++{ ++ return core_if->core_params->enable_dynamic_fifo; ++} ++ ++int dwc_otg_set_param_data_fifo_size(dwc_otg_core_if_t * core_if, int32_t val) ++{ ++ int retval = 0; ++ if (DWC_OTG_PARAM_TEST(val, 32, 32768)) { ++ DWC_WARN("Wrong value for data_fifo_size\n"); ++ DWC_WARN("data_fifo_size must be 32-32768\n"); ++ return -DWC_E_INVALID; ++ } ++ ++ if (val > core_if->hwcfg3.b.dfifo_depth) { ++ if (dwc_otg_param_initialized ++ (core_if->core_params->data_fifo_size)) { ++ DWC_ERROR ++ ("%d invalid for data_fifo_size parameter. Check HW configuration.\n", ++ val); ++ } ++ val = core_if->hwcfg3.b.dfifo_depth; ++ retval = -DWC_E_INVALID; ++ } ++ ++ core_if->core_params->data_fifo_size = val; ++ return retval; ++} ++ ++int32_t dwc_otg_get_param_data_fifo_size(dwc_otg_core_if_t * core_if) ++{ ++ return core_if->core_params->data_fifo_size; ++} ++ ++int dwc_otg_set_param_dev_rx_fifo_size(dwc_otg_core_if_t * core_if, int32_t val) ++{ ++ int retval = 0; ++ if (DWC_OTG_PARAM_TEST(val, 16, 32768)) { ++ DWC_WARN("Wrong value for dev_rx_fifo_size\n"); ++ DWC_WARN("dev_rx_fifo_size must be 16-32768\n"); ++ return -DWC_E_INVALID; ++ } ++ ++ if (val > dwc_read_reg32(&core_if->core_global_regs->grxfsiz)) { ++ if(dwc_otg_param_initialized(core_if->core_params->dev_rx_fifo_size)) { ++ DWC_WARN("%d invalid for dev_rx_fifo_size parameter\n", val); ++ } ++ val = dwc_read_reg32(&core_if->core_global_regs->grxfsiz); ++ retval = -DWC_E_INVALID; ++ } ++ ++ core_if->core_params->dev_rx_fifo_size = val; ++ return retval; ++} ++ ++int32_t dwc_otg_get_param_dev_rx_fifo_size(dwc_otg_core_if_t * core_if) ++{ ++ return core_if->core_params->dev_rx_fifo_size; ++} ++ ++int dwc_otg_set_param_dev_nperio_tx_fifo_size(dwc_otg_core_if_t * core_if, ++ int32_t val) ++{ ++ int retval = 0; ++ ++ if (DWC_OTG_PARAM_TEST(val, 16, 32768)) { ++ DWC_WARN("Wrong value for dev_nperio_tx_fifo\n"); ++ DWC_WARN("dev_nperio_tx_fifo must be 16-32768\n"); ++ return -DWC_E_INVALID; ++ } ++ ++ if (val > (dwc_read_reg32(&core_if->core_global_regs->gnptxfsiz) >> 16)) { ++ if (dwc_otg_param_initialized ++ (core_if->core_params->dev_nperio_tx_fifo_size)) { ++ DWC_ERROR ++ ("%d invalid for dev_nperio_tx_fifo_size. Check HW configuration.\n", ++ val); ++ } ++ val = ++ (dwc_read_reg32(&core_if->core_global_regs->gnptxfsiz) >> ++ 16); ++ retval = -DWC_E_INVALID; ++ } ++ ++ core_if->core_params->dev_nperio_tx_fifo_size = val; ++ return retval; ++} ++ ++int32_t dwc_otg_get_param_dev_nperio_tx_fifo_size(dwc_otg_core_if_t * core_if) ++{ ++ return core_if->core_params->dev_nperio_tx_fifo_size; ++} ++ ++int dwc_otg_set_param_host_rx_fifo_size(dwc_otg_core_if_t * core_if, ++ int32_t val) ++{ ++ int retval = 0; ++ ++ if (DWC_OTG_PARAM_TEST(val, 16, 32768)) { ++ DWC_WARN("Wrong value for host_rx_fifo_size\n"); ++ DWC_WARN("host_rx_fifo_size must be 16-32768\n"); ++ return -DWC_E_INVALID; ++ } ++ ++ if (val > dwc_read_reg32(&core_if->core_global_regs->grxfsiz)) { ++ if (dwc_otg_param_initialized ++ (core_if->core_params->host_rx_fifo_size)) { ++ DWC_ERROR ++ ("%d invalid for host_rx_fifo_size. Check HW configuration.\n", ++ val); ++ } ++ val = dwc_read_reg32(&core_if->core_global_regs->grxfsiz); ++ retval = -DWC_E_INVALID; ++ } ++ ++ core_if->core_params->host_rx_fifo_size = val; ++ return retval; ++ ++} ++ ++int32_t dwc_otg_get_param_host_rx_fifo_size(dwc_otg_core_if_t * core_if) ++{ ++ return core_if->core_params->host_rx_fifo_size; ++} ++ ++int dwc_otg_set_param_host_nperio_tx_fifo_size(dwc_otg_core_if_t * core_if, ++ int32_t val) ++{ ++ int retval = 0; ++ ++ if (DWC_OTG_PARAM_TEST(val, 16, 32768)) { ++ DWC_WARN("Wrong value for host_nperio_tx_fifo_size\n"); ++ DWC_WARN("host_nperio_tx_fifo_size must be 16-32768\n"); ++ return -DWC_E_INVALID; ++ } ++ ++ if (val > (dwc_read_reg32(&core_if->core_global_regs->gnptxfsiz) >> 16)) { ++ if (dwc_otg_param_initialized ++ (core_if->core_params->host_nperio_tx_fifo_size)) { ++ DWC_ERROR ++ ("%d invalid for host_nperio_tx_fifo_size. Check HW configuration.\n", ++ val); ++ } ++ val = ++ (dwc_read_reg32(&core_if->core_global_regs->gnptxfsiz) >> ++ 16); ++ retval = -DWC_E_INVALID; ++ } ++ ++ core_if->core_params->host_nperio_tx_fifo_size = val; ++ return retval; ++} ++ ++int32_t dwc_otg_get_param_host_nperio_tx_fifo_size(dwc_otg_core_if_t * core_if) ++{ ++ return core_if->core_params->host_nperio_tx_fifo_size; ++} ++ ++int dwc_otg_set_param_host_perio_tx_fifo_size(dwc_otg_core_if_t * core_if, ++ int32_t val) ++{ ++ int retval = 0; ++ if (DWC_OTG_PARAM_TEST(val, 16, 32768)) { ++ DWC_WARN("Wrong value for host_perio_tx_fifo_size\n"); ++ DWC_WARN("host_perio_tx_fifo_size must be 16-32768\n"); ++ return -DWC_E_INVALID; ++ } ++ ++ if (val > ++ ((dwc_read_reg32(&core_if->core_global_regs->hptxfsiz) >> 16))) { ++ if (dwc_otg_param_initialized ++ (core_if->core_params->host_perio_tx_fifo_size)) { ++ DWC_ERROR ++ ("%d invalid for host_perio_tx_fifo_size. Check HW configuration.\n", ++ val); ++ } ++ val = ++ (dwc_read_reg32(&core_if->core_global_regs->hptxfsiz) >> ++ 16); ++ retval = -DWC_E_INVALID; ++ } ++ ++ core_if->core_params->host_perio_tx_fifo_size = val; ++ return retval; ++} ++ ++int32_t dwc_otg_get_param_host_perio_tx_fifo_size(dwc_otg_core_if_t * core_if) ++{ ++ return core_if->core_params->host_perio_tx_fifo_size; ++} ++ ++int dwc_otg_set_param_max_transfer_size(dwc_otg_core_if_t * core_if, ++ int32_t val) ++{ ++ int retval = 0; ++ ++ if (DWC_OTG_PARAM_TEST(val, 2047, 524288)) { ++ DWC_WARN("Wrong value for max_transfer_size\n"); ++ DWC_WARN("max_transfer_size must be 2047-524288\n"); ++ return -DWC_E_INVALID; ++ } ++ ++ if (val >= (1 << (core_if->hwcfg3.b.xfer_size_cntr_width + 11))) { ++ if (dwc_otg_param_initialized ++ (core_if->core_params->max_transfer_size)) { ++ DWC_ERROR ++ ("%d invalid for max_transfer_size. Check HW configuration.\n", ++ val); ++ } ++ val = ++ ((1 << (core_if->hwcfg3.b.packet_size_cntr_width + 11)) - ++ 1); ++ retval = -DWC_E_INVALID; ++ } ++ ++ core_if->core_params->max_transfer_size = val; ++ return retval; ++} ++ ++int32_t dwc_otg_get_param_max_transfer_size(dwc_otg_core_if_t * core_if) ++{ ++ return core_if->core_params->max_transfer_size; ++} ++ ++int dwc_otg_set_param_max_packet_count(dwc_otg_core_if_t * core_if, int32_t val) ++{ ++ int retval = 0; ++ ++ if (DWC_OTG_PARAM_TEST(val, 15, 511)) { ++ DWC_WARN("Wrong value for max_packet_count\n"); ++ DWC_WARN("max_packet_count must be 15-511\n"); ++ return -DWC_E_INVALID; ++ } ++ ++ if (val > (1 << (core_if->hwcfg3.b.packet_size_cntr_width + 4))) { ++ if (dwc_otg_param_initialized ++ (core_if->core_params->max_packet_count)) { ++ DWC_ERROR ++ ("%d invalid for max_packet_count. Check HW configuration.\n", ++ val); ++ } ++ val = ++ ((1 << (core_if->hwcfg3.b.packet_size_cntr_width + 4)) - 1); ++ retval = -DWC_E_INVALID; ++ } ++ ++ core_if->core_params->max_packet_count = val; ++ return retval; ++} ++ ++int32_t dwc_otg_get_param_max_packet_count(dwc_otg_core_if_t * core_if) ++{ ++ return core_if->core_params->max_packet_count; ++} ++ ++int dwc_otg_set_param_host_channels(dwc_otg_core_if_t * core_if, int32_t val) ++{ ++ int retval = 0; ++ ++ if (DWC_OTG_PARAM_TEST(val, 1, 16)) { ++ DWC_WARN("Wrong value for host_channels\n"); ++ DWC_WARN("host_channels must be 1-16\n"); ++ return -DWC_E_INVALID; ++ } ++ ++ if (val > (core_if->hwcfg2.b.num_host_chan + 1)) { ++ if (dwc_otg_param_initialized ++ (core_if->core_params->host_channels)) { ++ DWC_ERROR ++ ("%d invalid for host_channels. Check HW configurations.\n", ++ val); ++ } ++ val = (core_if->hwcfg2.b.num_host_chan + 1); ++ retval = -DWC_E_INVALID; ++ } ++ ++ core_if->core_params->host_channels = val; ++ return retval; ++} ++ ++int32_t dwc_otg_get_param_host_channels(dwc_otg_core_if_t * core_if) ++{ ++ return core_if->core_params->host_channels; ++} ++ ++int dwc_otg_set_param_dev_endpoints(dwc_otg_core_if_t * core_if, int32_t val) ++{ ++ int retval = 0; ++ ++ if (DWC_OTG_PARAM_TEST(val, 1, 15)) { ++ DWC_WARN("Wrong value for dev_endpoints\n"); ++ DWC_WARN("dev_endpoints must be 1-15\n"); ++ return -DWC_E_INVALID; ++ } ++ ++ if (val > (core_if->hwcfg2.b.num_dev_ep)) { ++ if (dwc_otg_param_initialized ++ (core_if->core_params->dev_endpoints)) { ++ DWC_ERROR ++ ("%d invalid for dev_endpoints. Check HW configurations.\n", ++ val); ++ } ++ val = core_if->hwcfg2.b.num_dev_ep; ++ retval = -DWC_E_INVALID; ++ } ++ ++ core_if->core_params->dev_endpoints = val; ++ return retval; ++} ++ ++int32_t dwc_otg_get_param_dev_endpoints(dwc_otg_core_if_t * core_if) ++{ ++ return core_if->core_params->dev_endpoints; ++} ++ ++int dwc_otg_set_param_phy_type(dwc_otg_core_if_t * core_if, int32_t val) ++{ ++ int retval = 0; ++ int valid = 0; ++ ++ if (DWC_OTG_PARAM_TEST(val, 0, 2)) { ++ DWC_WARN("Wrong value for phy_type\n"); ++ DWC_WARN("phy_type must be 0,1 or 2\n"); ++ return -DWC_E_INVALID; ++ } ++#ifndef NO_FS_PHY_HW_CHECKS ++ if ((val == DWC_PHY_TYPE_PARAM_UTMI) && ++ ((core_if->hwcfg2.b.hs_phy_type == 1) || ++ (core_if->hwcfg2.b.hs_phy_type == 3))) { ++ valid = 1; ++ } else if ((val == DWC_PHY_TYPE_PARAM_ULPI) && ++ ((core_if->hwcfg2.b.hs_phy_type == 2) || ++ (core_if->hwcfg2.b.hs_phy_type == 3))) { ++ valid = 1; ++ } else if ((val == DWC_PHY_TYPE_PARAM_FS) && ++ (core_if->hwcfg2.b.fs_phy_type == 1)) { ++ valid = 1; ++ } ++ if (!valid) { ++ if (dwc_otg_param_initialized(core_if->core_params->phy_type)) { ++ DWC_ERROR ++ ("%d invalid for phy_type. Check HW configurations.\n", ++ val); ++ } ++ if (core_if->hwcfg2.b.hs_phy_type) { ++ if ((core_if->hwcfg2.b.hs_phy_type == 3) || ++ (core_if->hwcfg2.b.hs_phy_type == 1)) { ++ val = DWC_PHY_TYPE_PARAM_UTMI; ++ } else { ++ val = DWC_PHY_TYPE_PARAM_ULPI; ++ } ++ } ++ retval = -DWC_E_INVALID; ++ } ++#endif ++ core_if->core_params->phy_type = val; ++ return retval; ++} ++ ++int32_t dwc_otg_get_param_phy_type(dwc_otg_core_if_t * core_if) ++{ ++ return core_if->core_params->phy_type; ++} ++ ++int dwc_otg_set_param_speed(dwc_otg_core_if_t * core_if, int32_t val) ++{ ++ int retval = 0; ++ if (DWC_OTG_PARAM_TEST(val, 0, 1)) { ++ DWC_WARN("Wrong value for speed parameter\n"); ++ DWC_WARN("max_speed parameter must be 0 or 1\n"); ++ return -DWC_E_INVALID; ++ } ++ if ((val == 0) ++ && dwc_otg_get_param_phy_type(core_if) == DWC_PHY_TYPE_PARAM_FS) { ++ if (dwc_otg_param_initialized(core_if->core_params->speed)) { ++ DWC_ERROR ++ ("%d invalid for speed paremter. Check HW configuration.\n", ++ val); ++ } ++ val = ++ (dwc_otg_get_param_phy_type(core_if) == ++ DWC_PHY_TYPE_PARAM_FS ? 1 : 0); ++ retval = -DWC_E_INVALID; ++ } ++ core_if->core_params->speed = val; ++ return retval; ++} ++ ++int32_t dwc_otg_get_param_speed(dwc_otg_core_if_t * core_if) ++{ ++ return core_if->core_params->speed; ++} ++ ++int dwc_otg_set_param_host_ls_low_power_phy_clk(dwc_otg_core_if_t * core_if, ++ int32_t val) ++{ ++ int retval = 0; ++ ++ if (DWC_OTG_PARAM_TEST(val, 0, 1)) { ++ DWC_WARN ++ ("Wrong value for host_ls_low_power_phy_clk parameter\n"); ++ DWC_WARN("host_ls_low_power_phy_clk must be 0 or 1\n"); ++ return -DWC_E_INVALID; ++ } ++ ++ if ((val == DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ) ++ && (dwc_otg_get_param_phy_type(core_if) == DWC_PHY_TYPE_PARAM_FS)) { ++ if(dwc_otg_param_initialized(core_if->core_params->host_ls_low_power_phy_clk)) { ++ DWC_ERROR("%d invalid for host_ls_low_power_phy_clk. Check HW configuration.\n", ++ val); ++ } ++ val = ++ (dwc_otg_get_param_phy_type(core_if) == ++ DWC_PHY_TYPE_PARAM_FS) ? ++ DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ : ++ DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ; ++ retval = -DWC_E_INVALID; ++ } ++ ++ core_if->core_params->host_ls_low_power_phy_clk = val; ++ return retval; ++} ++ ++int32_t dwc_otg_get_param_host_ls_low_power_phy_clk(dwc_otg_core_if_t * core_if) ++{ ++ return core_if->core_params->host_ls_low_power_phy_clk; ++} ++ ++int dwc_otg_set_param_phy_ulpi_ddr(dwc_otg_core_if_t * core_if, int32_t val) ++{ ++ if (DWC_OTG_PARAM_TEST(val, 0, 1)) { ++ DWC_WARN("Wrong value for phy_ulpi_ddr\n"); ++ DWC_WARN("phy_upli_ddr must be 0 or 1\n"); ++ return -DWC_E_INVALID; ++ } ++ ++ core_if->core_params->phy_ulpi_ddr = val; ++ return 0; ++} ++ ++int32_t dwc_otg_get_param_phy_ulpi_ddr(dwc_otg_core_if_t * core_if) ++{ ++ return core_if->core_params->phy_ulpi_ddr; ++} ++ ++int dwc_otg_set_param_phy_ulpi_ext_vbus(dwc_otg_core_if_t * core_if, ++ int32_t val) ++{ ++ if (DWC_OTG_PARAM_TEST(val, 0, 1)) { ++ DWC_WARN("Wrong valaue for phy_ulpi_ext_vbus\n"); ++ DWC_WARN("phy_ulpi_ext_vbus must be 0 or 1\n"); ++ return -DWC_E_INVALID; ++ } ++ ++ core_if->core_params->phy_ulpi_ext_vbus = val; ++ return 0; ++} ++ ++int32_t dwc_otg_get_param_phy_ulpi_ext_vbus(dwc_otg_core_if_t * core_if) ++{ ++ return core_if->core_params->phy_ulpi_ext_vbus; ++} ++ ++int dwc_otg_set_param_phy_utmi_width(dwc_otg_core_if_t * core_if, int32_t val) ++{ ++ if (DWC_OTG_PARAM_TEST(val, 8, 8) && DWC_OTG_PARAM_TEST(val, 16, 16)) { ++ DWC_WARN("Wrong valaue for phy_utmi_width\n"); ++ DWC_WARN("phy_utmi_width must be 8 or 16\n"); ++ return -DWC_E_INVALID; ++ } ++ ++ core_if->core_params->phy_utmi_width = val; ++ return 0; ++} ++ ++int32_t dwc_otg_get_param_phy_utmi_width(dwc_otg_core_if_t * core_if) ++{ ++ return core_if->core_params->phy_utmi_width; ++} ++ ++int dwc_otg_set_param_ulpi_fs_ls(dwc_otg_core_if_t * core_if, int32_t val) ++{ ++ if (DWC_OTG_PARAM_TEST(val, 0, 1)) { ++ DWC_WARN("Wrong valaue for ulpi_fs_ls\n"); ++ DWC_WARN("ulpi_fs_ls must be 0 or 1\n"); ++ return -DWC_E_INVALID; ++ } ++ ++ core_if->core_params->ulpi_fs_ls = val; ++ return 0; ++} ++ ++int32_t dwc_otg_get_param_ulpi_fs_ls(dwc_otg_core_if_t * core_if) ++{ ++ return core_if->core_params->ulpi_fs_ls; ++} ++ ++int dwc_otg_set_param_ts_dline(dwc_otg_core_if_t * core_if, int32_t val) ++{ ++ if (DWC_OTG_PARAM_TEST(val, 0, 1)) { ++ DWC_WARN("Wrong valaue for ts_dline\n"); ++ DWC_WARN("ts_dline must be 0 or 1\n"); ++ return -DWC_E_INVALID; ++ } ++ ++ core_if->core_params->ts_dline = val; ++ return 0; ++} ++ ++int32_t dwc_otg_get_param_ts_dline(dwc_otg_core_if_t * core_if) ++{ ++ return core_if->core_params->ts_dline; ++} ++ ++int dwc_otg_set_param_i2c_enable(dwc_otg_core_if_t * core_if, int32_t val) ++{ ++ int retval = 0; ++ if (DWC_OTG_PARAM_TEST(val, 0, 1)) { ++ DWC_WARN("Wrong valaue for i2c_enable\n"); ++ DWC_WARN("i2c_enable must be 0 or 1\n"); ++ return -DWC_E_INVALID; ++ } ++#ifndef NO_FS_PHY_HW_CHECK ++ if (val == 1 && core_if->hwcfg3.b.i2c == 0) { ++ if(dwc_otg_param_initialized(core_if->core_params->i2c_enable)) { ++ DWC_ERROR("%d invalid for i2c_enable. Check HW configuration.\n", ++ val); ++ } ++ val = 0; ++ retval = -DWC_E_INVALID; ++ } ++#endif ++ ++ core_if->core_params->i2c_enable = val; ++ return retval; ++} ++ ++int32_t dwc_otg_get_param_i2c_enable(dwc_otg_core_if_t * core_if) ++{ ++ return core_if->core_params->i2c_enable; ++} ++ ++int dwc_otg_set_param_dev_perio_tx_fifo_size(dwc_otg_core_if_t * core_if, ++ int32_t val, int fifo_num) ++{ ++ int retval = 0; ++ ++ if (DWC_OTG_PARAM_TEST(val, 4, 768)) { ++ DWC_WARN("Wrong value for dev_perio_tx_fifo_size\n"); ++ DWC_WARN("dev_perio_tx_fifo_size must be 4-768\n"); ++ return -DWC_E_INVALID; ++ } ++ ++ if (val > (dwc_read_reg32(&core_if->core_global_regs->dptxfsiz_dieptxf[fifo_num]))) { ++ if(dwc_otg_param_initialized(core_if->core_params->dev_perio_tx_fifo_size[fifo_num])) { ++ DWC_ERROR("`%d' invalid for parameter `dev_perio_fifo_size_%d'. Check HW configuration.\n", ++ val, fifo_num); ++ } ++ val = (dwc_read_reg32(&core_if->core_global_regs->dptxfsiz_dieptxf[fifo_num])); ++ retval = -DWC_E_INVALID; ++ } ++ ++ core_if->core_params->dev_perio_tx_fifo_size[fifo_num] = val; ++ return retval; ++} ++ ++int32_t dwc_otg_get_param_dev_perio_tx_fifo_size(dwc_otg_core_if_t * core_if, ++ int fifo_num) ++{ ++ return core_if->core_params->dev_perio_tx_fifo_size[fifo_num]; ++} ++ ++int dwc_otg_set_param_en_multiple_tx_fifo(dwc_otg_core_if_t * core_if, ++ int32_t val) ++{ ++ int retval = 0; ++ if (DWC_OTG_PARAM_TEST(val, 0, 1)) { ++ DWC_WARN("Wrong valaue for en_multiple_tx_fifo,\n"); ++ DWC_WARN("en_multiple_tx_fifo must be 0 or 1\n"); ++ return -DWC_E_INVALID; ++ } ++ ++ if (val == 1 && core_if->hwcfg4.b.ded_fifo_en == 0) { ++ if(dwc_otg_param_initialized(core_if->core_params->en_multiple_tx_fifo)) { ++ DWC_ERROR("%d invalid for parameter en_multiple_tx_fifo. Check HW configuration.\n", ++ val); ++ } ++ val = 0; ++ retval = -DWC_E_INVALID; ++ } ++ ++ core_if->core_params->en_multiple_tx_fifo = val; ++ return retval; ++} ++ ++int32_t dwc_otg_get_param_en_multiple_tx_fifo(dwc_otg_core_if_t * core_if) ++{ ++ return core_if->core_params->en_multiple_tx_fifo; ++} ++ ++int dwc_otg_set_param_dev_tx_fifo_size(dwc_otg_core_if_t * core_if, int32_t val, ++ int fifo_num) ++{ ++ int retval = 0; ++ ++ if (DWC_OTG_PARAM_TEST(val, 4, 768)) { ++ DWC_WARN("Wrong value for dev_tx_fifo_size\n"); ++ DWC_WARN("dev_tx_fifo_size must be 4-768\n"); ++ return -DWC_E_INVALID; ++ } ++ ++ if (val > (dwc_read_reg32(&core_if->core_global_regs->dptxfsiz_dieptxf[fifo_num]))) { ++ if(dwc_otg_param_initialized(core_if->core_params->dev_tx_fifo_size[fifo_num])) { ++ DWC_ERROR("`%d' invalid for parameter `dev_tx_fifo_size_%d'. Check HW configuration.\n", ++ val, fifo_num); ++ } ++ val = (dwc_read_reg32(&core_if->core_global_regs->dptxfsiz_dieptxf[fifo_num])); ++ retval = -DWC_E_INVALID; ++ } ++ ++ core_if->core_params->dev_tx_fifo_size[fifo_num] = val; ++ return retval; ++} ++ ++int32_t dwc_otg_get_param_dev_tx_fifo_size(dwc_otg_core_if_t * core_if, ++ int fifo_num) ++{ ++ return core_if->core_params->dev_tx_fifo_size[fifo_num]; ++} ++ ++int dwc_otg_set_param_thr_ctl(dwc_otg_core_if_t * core_if, int32_t val) ++{ ++ int retval = 0; ++ ++ if (DWC_OTG_PARAM_TEST(val, 0, 7)) { ++ DWC_WARN("Wrong value for thr_ctl\n"); ++ DWC_WARN("thr_ctl must be 0-7\n"); ++ return -DWC_E_INVALID; ++ } ++ ++ if ((val != 0) && ++ (!dwc_otg_get_param_dma_enable(core_if) || ++ !core_if->hwcfg4.b.ded_fifo_en)) { ++ if(dwc_otg_param_initialized(core_if->core_params->thr_ctl)) { ++ DWC_ERROR("%d invalid for parameter thr_ctl. Check HW configuration.\n", ++ val); ++ } ++ val = 0; ++ retval = -DWC_E_INVALID; ++ } ++ ++ core_if->core_params->thr_ctl = val; ++ return retval; ++} ++ ++int32_t dwc_otg_get_param_thr_ctl(dwc_otg_core_if_t * core_if) ++{ ++ return core_if->core_params->thr_ctl; ++} ++ ++int dwc_otg_set_param_lpm_enable(dwc_otg_core_if_t * core_if, int32_t val) ++{ ++ int retval = 0; ++ ++ if (DWC_OTG_PARAM_TEST(val, 0, 1)) { ++ DWC_WARN("Wrong value for lpm_enable\n"); ++ DWC_WARN("lpm_enable must be 0 or 1\n"); ++ return -DWC_E_INVALID; ++ } ++ ++ if (val && !core_if->hwcfg3.b.otg_lpm_en) { ++ if(dwc_otg_param_initialized(core_if->core_params->lpm_enable)) { ++ DWC_ERROR("%d invalid for parameter lpm_enable. Check HW configuration.\n", ++ val); ++ } ++ val = 0; ++ retval = -DWC_E_INVALID; ++ } ++ ++ core_if->core_params->lpm_enable = val; ++ return retval; ++} ++ ++int32_t dwc_otg_get_param_lpm_enable(dwc_otg_core_if_t * core_if) ++{ ++ return core_if->core_params->lpm_enable; ++} ++ ++int dwc_otg_set_param_tx_thr_length(dwc_otg_core_if_t * core_if, int32_t val) ++{ ++ if (DWC_OTG_PARAM_TEST(val, 8, 128)) { ++ DWC_WARN("Wrong valaue for tx_thr_length\n"); ++ DWC_WARN("tx_thr_length must be 8 - 128\n"); ++ return -DWC_E_INVALID; ++ } ++ ++ core_if->core_params->tx_thr_length = val; ++ return 0; ++} ++ ++int32_t dwc_otg_get_param_tx_thr_length(dwc_otg_core_if_t * core_if) ++{ ++ return core_if->core_params->tx_thr_length; ++} ++ ++int dwc_otg_set_param_rx_thr_length(dwc_otg_core_if_t * core_if, int32_t val) ++{ ++ if (DWC_OTG_PARAM_TEST(val, 8, 128)) { ++ DWC_WARN("Wrong valaue for rx_thr_length\n"); ++ DWC_WARN("rx_thr_length must be 8 - 128\n"); ++ return -DWC_E_INVALID; ++ } ++ ++ core_if->core_params->rx_thr_length = val; ++ return 0; ++} ++ ++int32_t dwc_otg_get_param_rx_thr_length(dwc_otg_core_if_t * core_if) ++{ ++ return core_if->core_params->rx_thr_length; ++} ++ ++int dwc_otg_set_param_dma_burst_size(dwc_otg_core_if_t * core_if, int32_t val) ++{ ++ if (DWC_OTG_PARAM_TEST(val, 1, 1) && ++ DWC_OTG_PARAM_TEST(val, 4, 4) && ++ DWC_OTG_PARAM_TEST(val, 8, 8) && ++ DWC_OTG_PARAM_TEST(val, 16, 16) && ++ DWC_OTG_PARAM_TEST(val, 32, 32) && ++ DWC_OTG_PARAM_TEST(val, 64, 64) && ++ DWC_OTG_PARAM_TEST(val, 128, 128) && ++ DWC_OTG_PARAM_TEST(val, 256, 256)) { ++ DWC_WARN("`%d' invalid for parameter `dma_burst_size'\n", val); ++ return -DWC_E_INVALID; ++ } ++ core_if->core_params->dma_burst_size = val; ++ return 0; ++} ++ ++int32_t dwc_otg_get_param_dma_burst_size(dwc_otg_core_if_t * core_if) ++{ ++ return core_if->core_params->dma_burst_size; ++} ++ ++int dwc_otg_set_param_pti_enable(dwc_otg_core_if_t * core_if, int32_t val) ++{ ++ int retval = 0; ++ if (DWC_OTG_PARAM_TEST(val, 0, 1)) { ++ DWC_WARN("`%d' invalid for parameter `pti_enable'\n", val); ++ return -DWC_E_INVALID; ++ } ++ if (val && (core_if->snpsid < OTG_CORE_REV_2_72a)) { ++ if (dwc_otg_param_initialized(core_if->core_params->pti_enable)) { ++ DWC_ERROR("%d invalid for parameter pti_enable. Check HW configuration.\n", ++ val); ++ } ++ retval = -DWC_E_INVALID; ++ val = 0; ++ } ++ core_if->core_params->pti_enable = val; ++ return retval; ++} ++ ++int32_t dwc_otg_get_param_pti_enable(dwc_otg_core_if_t * core_if) ++{ ++ return core_if->core_params->pti_enable; ++} ++ ++int dwc_otg_set_param_mpi_enable(dwc_otg_core_if_t * core_if, int32_t val) ++{ ++ int retval = 0; ++ if (DWC_OTG_PARAM_TEST(val, 0, 1)) { ++ DWC_WARN("`%d' invalid for parameter `mpi_enable'\n", val); ++ return -DWC_E_INVALID; ++ } ++ if (val && (core_if->hwcfg2.b.multi_proc_int == 0)) { ++ if (dwc_otg_param_initialized(core_if->core_params->mpi_enable)) { ++ DWC_ERROR("%d invalid for parameter mpi_enable. Check HW configuration.\n", ++ val); ++ } ++ retval = -DWC_E_INVALID; ++ val = 0; ++ } ++ core_if->core_params->mpi_enable = val; ++ return retval; ++} ++ ++int32_t dwc_otg_get_param_mpi_enable(dwc_otg_core_if_t * core_if) ++{ ++ return core_if->core_params->mpi_enable; ++} ++ ++int dwc_otg_set_param_ic_usb_cap(dwc_otg_core_if_t * core_if, ++ int32_t val) ++{ ++ int retval = 0; ++ if (DWC_OTG_PARAM_TEST(val, 0, 1)) { ++ DWC_WARN("`%d' invalid for parameter `ic_usb_cap'\n", val); ++ DWC_WARN("ic_usb_cap must be 0 or 1\n"); ++ return -DWC_E_INVALID; ++ } ++ ++ if (val && (core_if->hwcfg3.b.otg_enable_ic_usb == 0)) { ++ if (dwc_otg_param_initialized(core_if->core_params->ic_usb_cap)) { ++ DWC_ERROR("%d invalid for parameter ic_usb_cap. Check HW configuration.\n", ++ val); ++ } ++ retval = -DWC_E_INVALID; ++ val = 0; ++ } ++ core_if->core_params->ic_usb_cap = val; ++ return retval; ++} ++int32_t dwc_otg_get_param_ic_usb_cap(dwc_otg_core_if_t * core_if) ++{ ++ return core_if->core_params->ic_usb_cap; ++} ++ ++int dwc_otg_set_param_ahb_thr_ratio(dwc_otg_core_if_t * core_if, int32_t val) ++{ ++ int retval = 0; ++ int valid = 1; ++ ++ if(DWC_OTG_PARAM_TEST(val, 0, 3)) { ++ DWC_WARN("`%d' invalid for parameter `ahb_thr_ratio'\n", val); ++ DWC_WARN("ahb_thr_ratio must be 0 - 3\n"); ++ return -DWC_E_INVALID; ++ } ++ ++ if(val && (core_if->snpsid < OTG_CORE_REV_2_81a || !dwc_otg_get_param_thr_ctl(core_if))) { ++ valid = 0; ++ } else if(val && ((dwc_otg_get_param_tx_thr_length(core_if) / (1 << val)) < 4)) { ++ valid = 0; ++ } ++ if(valid == 0) { ++ if(dwc_otg_param_initialized(core_if->core_params->ahb_thr_ratio)) { ++ DWC_ERROR("%d invalid for parameter ahb_thr_ratio. Chack HW configuration.\n", val); ++ } ++ retval = -DWC_E_INVALID; ++ val = 0; ++ } ++ ++ core_if->core_params->ahb_thr_ratio = val; ++ return retval; ++} ++int32_t dwc_otg_get_param_ahb_thr_ratio(dwc_otg_core_if_t * core_if) ++{ ++ return core_if->core_params->ahb_thr_ratio; ++} ++ ++ ++uint32_t dwc_otg_get_hnpstatus(dwc_otg_core_if_t * core_if) ++{ ++ gotgctl_data_t otgctl; ++ otgctl.d32 = dwc_read_reg32(&core_if->core_global_regs->gotgctl); ++ return otgctl.b.hstnegscs; ++} ++ ++uint32_t dwc_otg_get_srpstatus(dwc_otg_core_if_t * core_if) ++{ ++ gotgctl_data_t otgctl; ++ otgctl.d32 = dwc_read_reg32(&core_if->core_global_regs->gotgctl); ++ return otgctl.b.sesreqscs; ++} ++ ++void dwc_otg_set_hnpreq(dwc_otg_core_if_t * core_if, uint32_t val) ++{ ++ gotgctl_data_t otgctl; ++ otgctl.d32 = dwc_read_reg32(&core_if->core_global_regs->gotgctl); ++ otgctl.b.hnpreq = val; ++ dwc_write_reg32(&core_if->core_global_regs->gotgctl, otgctl.d32); ++} ++ ++uint32_t dwc_otg_get_gsnpsid(dwc_otg_core_if_t * core_if) ++{ ++ return core_if->snpsid; ++} ++ ++uint32_t dwc_otg_get_mode(dwc_otg_core_if_t * core_if) ++{ ++ gotgctl_data_t otgctl; ++ otgctl.d32 = dwc_read_reg32(&core_if->core_global_regs->gotgctl); ++ return otgctl.b.currmod; ++} ++ ++uint32_t dwc_otg_get_hnpcapable(dwc_otg_core_if_t * core_if) ++{ ++ gusbcfg_data_t usbcfg; ++ usbcfg.d32 = dwc_read_reg32(&core_if->core_global_regs->gusbcfg); ++ return usbcfg.b.hnpcap; ++} ++ ++void dwc_otg_set_hnpcapable(dwc_otg_core_if_t * core_if, uint32_t val) ++{ ++ gusbcfg_data_t usbcfg; ++ usbcfg.d32 = dwc_read_reg32(&core_if->core_global_regs->gusbcfg); ++ usbcfg.b.hnpcap = val; ++ dwc_write_reg32(&core_if->core_global_regs->gusbcfg, usbcfg.d32); ++} ++ ++uint32_t dwc_otg_get_srpcapable(dwc_otg_core_if_t * core_if) ++{ ++ gusbcfg_data_t usbcfg; ++ usbcfg.d32 = dwc_read_reg32(&core_if->core_global_regs->gusbcfg); ++ return usbcfg.b.srpcap; ++} ++ ++void dwc_otg_set_srpcapable(dwc_otg_core_if_t * core_if, uint32_t val) ++{ ++ gusbcfg_data_t usbcfg; ++ usbcfg.d32 = dwc_read_reg32(&core_if->core_global_regs->gusbcfg); ++ usbcfg.b.srpcap = val; ++ dwc_write_reg32(&core_if->core_global_regs->gusbcfg, usbcfg.d32); ++} ++ ++uint32_t dwc_otg_get_devspeed(dwc_otg_core_if_t * core_if) ++{ ++ dcfg_data_t dcfg; ++ dcfg.d32 = -1; //GRAYG ++ DWC_DEBUGPL(DBG_CILV, "%s - core_if(%p)\n", __func__, core_if); ++ if (NULL == core_if) ++ DWC_ERROR("reg request with NULL core_if\n"); ++ DWC_DEBUGPL(DBG_CILV, "%s - core_if(%p)->dev_if(%p)\n", __func__, ++ core_if, core_if->dev_if); ++ if (NULL == core_if->dev_if) ++ DWC_ERROR("reg request with NULL dev_if\n"); ++ DWC_DEBUGPL(DBG_CILV, "%s - core_if(%p)->dev_if(%p)->" ++ "dev_global_regs(%p)\n", __func__, ++ core_if, core_if->dev_if, ++ core_if->dev_if->dev_global_regs); ++ if (NULL == core_if->dev_if->dev_global_regs) ++ DWC_ERROR("reg request with NULL dev_global_regs\n"); ++ else { ++ DWC_DEBUGPL(DBG_CILV, "%s - &core_if(%p)->dev_if(%p)->" ++ "dev_global_regs(%p)->dcfg = %p\n", __func__, ++ core_if, core_if->dev_if, ++ core_if->dev_if->dev_global_regs, ++ &core_if->dev_if->dev_global_regs->dcfg); ++ dcfg.d32 = dwc_read_reg32(&core_if->dev_if->dev_global_regs->dcfg); ++ } ++ return dcfg.b.devspd; ++} ++ ++void dwc_otg_set_devspeed(dwc_otg_core_if_t * core_if, uint32_t val) ++{ ++ dcfg_data_t dcfg; ++ dcfg.d32 = dwc_read_reg32(&core_if->dev_if->dev_global_regs->dcfg); ++ dcfg.b.devspd = val; ++ dwc_write_reg32(&core_if->dev_if->dev_global_regs->dcfg, dcfg.d32); ++} ++ ++uint32_t dwc_otg_get_busconnected(dwc_otg_core_if_t * core_if) ++{ ++ hprt0_data_t hprt0; ++ hprt0.d32 = dwc_read_reg32(core_if->host_if->hprt0); ++ return hprt0.b.prtconnsts; ++} ++ ++uint32_t dwc_otg_get_enumspeed(dwc_otg_core_if_t * core_if) ++{ ++ dsts_data_t dsts; ++ dsts.d32 = dwc_read_reg32(&core_if->dev_if->dev_global_regs->dsts); ++ return dsts.b.enumspd; ++} ++ ++uint32_t dwc_otg_get_prtpower(dwc_otg_core_if_t * core_if) ++{ ++ hprt0_data_t hprt0; ++ hprt0.d32 = dwc_read_reg32(core_if->host_if->hprt0); ++ return hprt0.b.prtpwr; ++ ++} ++ ++void dwc_otg_set_prtpower(dwc_otg_core_if_t * core_if, uint32_t val) ++{ ++ hprt0_data_t hprt0; ++ hprt0.d32 = dwc_read_reg32(core_if->host_if->hprt0); ++ hprt0.b.prtpwr = val; ++ dwc_write_reg32(core_if->host_if->hprt0, val); ++} ++ ++uint32_t dwc_otg_get_prtsuspend(dwc_otg_core_if_t * core_if) ++{ ++ hprt0_data_t hprt0; ++ hprt0.d32 = dwc_read_reg32(core_if->host_if->hprt0); ++ return hprt0.b.prtsusp; ++ ++} ++ ++void dwc_otg_set_prtsuspend(dwc_otg_core_if_t * core_if, uint32_t val) ++{ ++ hprt0_data_t hprt0; ++ hprt0.d32 = dwc_read_reg32(core_if->host_if->hprt0); ++ hprt0.b.prtsusp = val; ++ dwc_write_reg32(core_if->host_if->hprt0, val); ++} ++ ++void dwc_otg_set_prtresume(dwc_otg_core_if_t * core_if, uint32_t val) ++{ ++ hprt0_data_t hprt0; ++ hprt0.d32 = dwc_read_reg32(core_if->host_if->hprt0); ++ hprt0.b.prtres = val; ++ dwc_write_reg32(core_if->host_if->hprt0, val); ++} ++ ++uint32_t dwc_otg_get_remotewakesig(dwc_otg_core_if_t * core_if) ++{ ++ dctl_data_t dctl; ++ dctl.d32 = dwc_read_reg32(&core_if->dev_if->dev_global_regs->dctl); ++ return dctl.b.rmtwkupsig; ++} ++ ++uint32_t dwc_otg_get_lpm_portsleepstatus(dwc_otg_core_if_t * core_if) ++{ ++ glpmcfg_data_t lpmcfg; ++ lpmcfg.d32 = dwc_read_reg32(&core_if->core_global_regs->glpmcfg); ++ ++ DWC_ASSERT(! ++ ((core_if->lx_state == DWC_OTG_L1) ^ lpmcfg.b.prt_sleep_sts), ++ "lx_state = %d, lmpcfg.prt_sleep_sts = %d\n", ++ core_if->lx_state, lpmcfg.b.prt_sleep_sts); ++ ++ return lpmcfg.b.prt_sleep_sts; ++} ++ ++uint32_t dwc_otg_get_lpm_remotewakeenabled(dwc_otg_core_if_t * core_if) ++{ ++ glpmcfg_data_t lpmcfg; ++ lpmcfg.d32 = dwc_read_reg32(&core_if->core_global_regs->glpmcfg); ++ return lpmcfg.b.rem_wkup_en; ++} ++ ++uint32_t dwc_otg_get_lpmresponse(dwc_otg_core_if_t * core_if) ++{ ++ glpmcfg_data_t lpmcfg; ++ lpmcfg.d32 = dwc_read_reg32(&core_if->core_global_regs->glpmcfg); ++ return lpmcfg.b.appl_resp; ++} ++ ++void dwc_otg_set_lpmresponse(dwc_otg_core_if_t * core_if, uint32_t val) ++{ ++ glpmcfg_data_t lpmcfg; ++ lpmcfg.d32 = dwc_read_reg32(&core_if->core_global_regs->glpmcfg); ++ lpmcfg.b.appl_resp = val; ++ dwc_write_reg32(&core_if->core_global_regs->glpmcfg, lpmcfg.d32); ++} ++ ++uint32_t dwc_otg_get_hsic_connect(dwc_otg_core_if_t * core_if) ++{ ++ glpmcfg_data_t lpmcfg; ++ lpmcfg.d32 = dwc_read_reg32(&core_if->core_global_regs->glpmcfg); ++ return lpmcfg.b.hsic_connect; ++} ++ ++void dwc_otg_set_hsic_connect(dwc_otg_core_if_t * core_if, uint32_t val) ++{ ++ glpmcfg_data_t lpmcfg; ++ lpmcfg.d32 = dwc_read_reg32(&core_if->core_global_regs->glpmcfg); ++ lpmcfg.b.hsic_connect = val; ++ dwc_write_reg32(&core_if->core_global_regs->glpmcfg, lpmcfg.d32); ++} ++ ++uint32_t dwc_otg_get_inv_sel_hsic(dwc_otg_core_if_t * core_if) ++{ ++ glpmcfg_data_t lpmcfg; ++ lpmcfg.d32 = dwc_read_reg32(&core_if->core_global_regs->glpmcfg); ++ return lpmcfg.b.inv_sel_hsic; ++ ++} ++ ++void dwc_otg_set_inv_sel_hsic(dwc_otg_core_if_t * core_if, uint32_t val) ++{ ++ glpmcfg_data_t lpmcfg; ++ lpmcfg.d32 = dwc_read_reg32(&core_if->core_global_regs->glpmcfg); ++ lpmcfg.b.inv_sel_hsic = val; ++ dwc_write_reg32(&core_if->core_global_regs->glpmcfg, lpmcfg.d32); ++} ++ ++uint32_t dwc_otg_get_gotgctl(dwc_otg_core_if_t * core_if) ++{ ++ return dwc_read_reg32(&core_if->core_global_regs->gotgctl); ++} ++ ++void dwc_otg_set_gotgctl(dwc_otg_core_if_t * core_if, uint32_t val) ++{ ++ dwc_write_reg32(&core_if->core_global_regs->gotgctl, val); ++} ++ ++uint32_t dwc_otg_get_gusbcfg(dwc_otg_core_if_t * core_if) ++{ ++ return dwc_read_reg32(&core_if->core_global_regs->gusbcfg); ++} ++ ++void dwc_otg_set_gusbcfg(dwc_otg_core_if_t * core_if, uint32_t val) ++{ ++ dwc_write_reg32(&core_if->core_global_regs->gusbcfg, val); ++} ++ ++uint32_t dwc_otg_get_grxfsiz(dwc_otg_core_if_t * core_if) ++{ ++ return dwc_read_reg32(&core_if->core_global_regs->grxfsiz); ++} ++ ++void dwc_otg_set_grxfsiz(dwc_otg_core_if_t * core_if, uint32_t val) ++{ ++ dwc_write_reg32(&core_if->core_global_regs->grxfsiz, val); ++} ++ ++uint32_t dwc_otg_get_gnptxfsiz(dwc_otg_core_if_t * core_if) ++{ ++ return dwc_read_reg32(&core_if->core_global_regs->gnptxfsiz); ++} ++ ++void dwc_otg_set_gnptxfsiz(dwc_otg_core_if_t * core_if, uint32_t val) ++{ ++ dwc_write_reg32(&core_if->core_global_regs->gnptxfsiz, val); ++} ++ ++uint32_t dwc_otg_get_gpvndctl(dwc_otg_core_if_t * core_if) ++{ ++ return dwc_read_reg32(&core_if->core_global_regs->gpvndctl); ++} ++ ++void dwc_otg_set_gpvndctl(dwc_otg_core_if_t * core_if, uint32_t val) ++{ ++ dwc_write_reg32(&core_if->core_global_regs->gpvndctl, val); ++} ++ ++uint32_t dwc_otg_get_ggpio(dwc_otg_core_if_t * core_if) ++{ ++ return dwc_read_reg32(&core_if->core_global_regs->ggpio); ++} ++ ++void dwc_otg_set_ggpio(dwc_otg_core_if_t * core_if, uint32_t val) ++{ ++ dwc_write_reg32(&core_if->core_global_regs->ggpio, val); ++} ++ ++uint32_t dwc_otg_get_hprt0(dwc_otg_core_if_t * core_if) ++{ ++ return dwc_read_reg32(core_if->host_if->hprt0); ++ ++} ++ ++void dwc_otg_set_hprt0(dwc_otg_core_if_t * core_if, uint32_t val) ++{ ++ dwc_write_reg32(core_if->host_if->hprt0, val); ++} ++ ++uint32_t dwc_otg_get_guid(dwc_otg_core_if_t * core_if) ++{ ++ return dwc_read_reg32(&core_if->core_global_regs->guid); ++} ++ ++void dwc_otg_set_guid(dwc_otg_core_if_t * core_if, uint32_t val) ++{ ++ dwc_write_reg32(&core_if->core_global_regs->guid, val); ++} ++ ++uint32_t dwc_otg_get_hptxfsiz(dwc_otg_core_if_t * core_if) ++{ ++ return dwc_read_reg32(&core_if->core_global_regs->hptxfsiz); ++} +Index: linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_cil.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_cil.h 2013-07-26 19:31:23.000000000 +0000 +@@ -0,0 +1,1143 @@ ++/* ========================================================================== ++ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_cil.h $ ++ * $Revision: #99 $ ++ * $Date: 2009/04/21 $ ++ * $Change: 1237466 $ ++ * ++ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, ++ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless ++ * otherwise expressly agreed to in writing between Synopsys and you. ++ * ++ * The Software IS NOT an item of Licensed Software or Licensed Product under ++ * any End User Software License Agreement or Agreement for Licensed Product ++ * with Synopsys or any supplement thereto. You are permitted to use and ++ * redistribute this Software in source and binary forms, with or without ++ * modification, provided that redistributions of source code must retain this ++ * notice. You may not view, use, disclose, copy or distribute this file or ++ * any information contained herein except pursuant to this license grant from ++ * Synopsys. If you do not agree with this notice, including the disclaimer ++ * below, then you are not authorized to use the Software. ++ * ++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, ++ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR ++ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER ++ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY ++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH ++ * DAMAGE. ++ * ========================================================================== */ ++ ++#if !defined(__DWC_CIL_H__) ++#define __DWC_CIL_H__ ++ ++//#define HW2937_WORKAROUND ++#define DBG_HW2937 0x400 ++ ++#include "dwc_os.h" ++#include "dwc_list.h" ++#include "dwc_otg_dbg.h" ++#include "dwc_otg_regs.h" ++ ++#include "dwc_otg_core_if.h" ++ ++/** ++ * @file ++ * This file contains the interface to the Core Interface Layer. ++ */ ++ ++#ifdef DWC_UTE_CFI ++ ++#define MAX_DMA_DESCS_PER_EP 256 ++ ++/** ++ * Enumeration for the data buffer mode ++ */ ++typedef enum _data_buffer_mode { ++ BM_STANDARD = 0, /* data buffer is in normal mode */ ++ BM_SG = 1, /* data buffer uses the scatter/gather mode */ ++ BM_CONCAT = 2, /* data buffer uses the concatenation mode */ ++ BM_CIRCULAR = 3, /* data buffer uses the circular DMA mode */ ++ BM_ALIGN = 4 /* data buffer is in buffer alignment mode */ ++} data_buffer_mode_e; ++#endif //DWC_UTE_CFI ++ ++/** Macros defined for DWC OTG HW Release verison */ ++ ++#define OTG_CORE_REV_2_60a 0x4F54260A ++#define OTG_CORE_REV_2_71a 0x4F54271A ++#define OTG_CORE_REV_2_72a 0x4F54272A ++#define OTG_CORE_REV_2_80a 0x4F54280A ++#define OTG_CORE_REV_2_81a 0x4F54281A ++#define OTG_CORE_REV_2_90a 0x4F54290A ++ ++/** ++ * Information for each ISOC packet. ++ */ ++typedef struct iso_pkt_info { ++ uint32_t offset; ++ uint32_t length; ++ int32_t status; ++} iso_pkt_info_t; ++ ++/** ++ * The dwc_ep structure represents the state of a single ++ * endpoint when acting in device mode. It contains the data items ++ * needed for an endpoint to be activated and transfer packets. ++ */ ++typedef struct dwc_ep { ++ /** EP number used for register address lookup */ ++ uint8_t num; ++ /** EP direction 0 = OUT */ ++ unsigned is_in:1; ++ /** EP active. */ ++ unsigned active:1; ++ ++ /** Periodic Tx FIFO # for IN EPs For INTR EP set to 0 to use non-periodic Tx FIFO ++ If dedicated Tx FIFOs are enabled for all IN Eps - Tx FIFO # FOR IN EPs*/ ++ unsigned tx_fifo_num:4; ++ /** EP type: 0 - Control, 1 - ISOC, 2 - BULK, 3 - INTR */ ++ unsigned type:2; ++#define DWC_OTG_EP_TYPE_CONTROL 0 ++#define DWC_OTG_EP_TYPE_ISOC 1 ++#define DWC_OTG_EP_TYPE_BULK 2 ++#define DWC_OTG_EP_TYPE_INTR 3 ++ ++ /** DATA start PID for INTR and BULK EP */ ++ unsigned data_pid_start:1; ++ /** Frame (even/odd) for ISOC EP */ ++ unsigned even_odd_frame:1; ++ /** Max Packet bytes */ ++ unsigned maxpacket:11; ++ ++ /** Max Transfer size */ ++ uint32_t maxxfer; ++ ++ /** @name Transfer state */ ++ /** @{ */ ++ ++ /** ++ * Pointer to the beginning of the transfer buffer -- do not modify ++ * during transfer. ++ */ ++ ++ dwc_dma_t dma_addr; ++ ++ dwc_dma_t dma_desc_addr; ++ dwc_otg_dev_dma_desc_t *desc_addr; ++ ++ uint8_t *start_xfer_buff; ++ /** pointer to the transfer buffer */ ++ uint8_t *xfer_buff; ++ /** Number of bytes to transfer */ ++ unsigned xfer_len:19; ++ /** Number of bytes transferred. */ ++ unsigned xfer_count:19; ++ /** Sent ZLP */ ++ unsigned sent_zlp:1; ++ /** Total len for control transfer */ ++ unsigned total_len:19; ++ ++ /** stall clear flag */ ++ unsigned stall_clear_flag:1; ++ ++#ifdef DWC_UTE_CFI ++ /* The buffer mode */ ++ data_buffer_mode_e buff_mode; ++ ++ /* The chain of DMA descriptors. ++ * MAX_DMA_DESCS_PER_EP will be allocated for each active EP. ++ */ ++ dwc_otg_dma_desc_t *descs; ++ ++ /* The DMA address of the descriptors chain start */ ++ dma_addr_t descs_dma_addr; ++ /** This variable stores the length of the last enqueued request */ ++ uint32_t cfi_req_len; ++#endif //DWC_UTE_CFI ++ ++ /** Allocated DMA Desc count */ ++ uint32_t desc_cnt; ++ ++#ifdef DWC_EN_ISOC ++ /** ++ * Variables specific for ISOC EPs ++ * ++ */ ++ /** DMA addresses of ISOC buffers */ ++ dwc_dma_t dma_addr0; ++ dwc_dma_t dma_addr1; ++ ++ dwc_dma_t iso_dma_desc_addr; ++ dwc_otg_dev_dma_desc_t *iso_desc_addr; ++ ++ /** pointer to the transfer buffers */ ++ uint8_t *xfer_buff0; ++ uint8_t *xfer_buff1; ++ ++ /** number of ISOC Buffer is processing */ ++ uint32_t proc_buf_num; ++ /** Interval of ISOC Buffer processing */ ++ uint32_t buf_proc_intrvl; ++ /** Data size for regular frame */ ++ uint32_t data_per_frame; ++ ++ /* todo - pattern data support is to be implemented in the future */ ++ /** Data size for pattern frame */ ++ uint32_t data_pattern_frame; ++ /** Frame number of pattern data */ ++ uint32_t sync_frame; ++ ++ /** bInterval */ ++ uint32_t bInterval; ++ /** ISO Packet number per frame */ ++ uint32_t pkt_per_frm; ++ /** Next frame num for which will be setup DMA Desc */ ++ uint32_t next_frame; ++ /** Number of packets per buffer processing */ ++ uint32_t pkt_cnt; ++ /** Info for all isoc packets */ ++ iso_pkt_info_t *pkt_info; ++ /** current pkt number */ ++ uint32_t cur_pkt; ++ /** current pkt number */ ++ uint8_t *cur_pkt_addr; ++ /** current pkt number */ ++ uint32_t cur_pkt_dma_addr; ++#endif /* DWC_EN_ISOC */ ++ ++/** @} */ ++} dwc_ep_t; ++ ++/* ++ * Reasons for halting a host channel. ++ */ ++typedef enum dwc_otg_halt_status { ++ DWC_OTG_HC_XFER_NO_HALT_STATUS, ++ DWC_OTG_HC_XFER_COMPLETE, ++ DWC_OTG_HC_XFER_URB_COMPLETE, ++ DWC_OTG_HC_XFER_ACK, ++ DWC_OTG_HC_XFER_NAK, ++ DWC_OTG_HC_XFER_NYET, ++ DWC_OTG_HC_XFER_STALL, ++ DWC_OTG_HC_XFER_XACT_ERR, ++ DWC_OTG_HC_XFER_FRAME_OVERRUN, ++ DWC_OTG_HC_XFER_BABBLE_ERR, ++ DWC_OTG_HC_XFER_DATA_TOGGLE_ERR, ++ DWC_OTG_HC_XFER_AHB_ERR, ++ DWC_OTG_HC_XFER_PERIODIC_INCOMPLETE, ++ DWC_OTG_HC_XFER_URB_DEQUEUE ++#ifdef HW2937_WORKAROUND ++ , DWC_OTG_HC_XFER_PAUSE_IN ++#endif ++} dwc_otg_halt_status_e; ++ ++/** ++ * Host channel descriptor. This structure represents the state of a single ++ * host channel when acting in host mode. It contains the data items needed to ++ * transfer packets to an endpoint via a host channel. ++ */ ++typedef struct dwc_hc { ++ /** Host channel number used for register address lookup */ ++ uint8_t hc_num; ++ ++ /** Device to access */ ++ unsigned dev_addr:7; ++ ++ /** EP to access */ ++ unsigned ep_num:4; ++ ++ /** EP direction. 0: OUT, 1: IN */ ++ unsigned ep_is_in:1; ++ ++ /** ++ * EP speed. ++ * One of the following values: ++ * - DWC_OTG_EP_SPEED_LOW ++ * - DWC_OTG_EP_SPEED_FULL ++ * - DWC_OTG_EP_SPEED_HIGH ++ */ ++ unsigned speed:2; ++#define DWC_OTG_EP_SPEED_LOW 0 ++#define DWC_OTG_EP_SPEED_FULL 1 ++#define DWC_OTG_EP_SPEED_HIGH 2 ++ ++ /** ++ * Endpoint type. ++ * One of the following values: ++ * - DWC_OTG_EP_TYPE_CONTROL: 0 ++ * - DWC_OTG_EP_TYPE_ISOC: 1 ++ * - DWC_OTG_EP_TYPE_BULK: 2 ++ * - DWC_OTG_EP_TYPE_INTR: 3 ++ */ ++ unsigned ep_type:2; ++ ++ /** Max packet size in bytes */ ++ unsigned max_packet:11; ++ ++ /** ++ * PID for initial transaction. ++ * 0: DATA0,
++ * 1: DATA2,
++ * 2: DATA1,
++ * 3: MDATA (non-Control EP), ++ * SETUP (Control EP) ++ */ ++ unsigned data_pid_start:2; ++#define DWC_OTG_HC_PID_DATA0 0 ++#define DWC_OTG_HC_PID_DATA2 1 ++#define DWC_OTG_HC_PID_DATA1 2 ++#define DWC_OTG_HC_PID_MDATA 3 ++#define DWC_OTG_HC_PID_SETUP 3 ++ ++ /** Number of periodic transactions per (micro)frame */ ++ unsigned multi_count:2; ++ ++ /** @name Transfer State */ ++ /** @{ */ ++ ++ /** Pointer to the current transfer buffer position. */ ++ uint8_t *xfer_buff; ++ /** ++ * In Buffer DMA mode this buffer will be used ++ * if xfer_buff is not DWORD aligned. ++ */ ++ dwc_dma_t align_buff; ++ /** Total number of bytes to transfer. */ ++ uint32_t xfer_len; ++ /** Number of bytes transferred so far. */ ++ uint32_t xfer_count; ++ /** Packet count at start of transfer.*/ ++ uint16_t start_pkt_count; ++ ++ /** ++ * Flag to indicate whether the transfer has been started. Set to 1 if ++ * it has been started, 0 otherwise. ++ */ ++ uint8_t xfer_started; ++ ++ /** ++ * Set to 1 to indicate that a PING request should be issued on this ++ * channel. If 0, process normally. ++ */ ++ uint8_t do_ping; ++ ++ /** ++ * Set to 1 to indicate that the error count for this transaction is ++ * non-zero. Set to 0 if the error count is 0. ++ */ ++ uint8_t error_state; ++ ++ /** ++ * Set to 1 to indicate that this channel should be halted the next ++ * time a request is queued for the channel. This is necessary in ++ * slave mode if no request queue space is available when an attempt ++ * is made to halt the channel. ++ */ ++ uint8_t halt_on_queue; ++ ++ /** ++ * Set to 1 if the host channel has been halted, but the core is not ++ * finished flushing queued requests. Otherwise 0. ++ */ ++ uint8_t halt_pending; ++ ++ /** ++ * Reason for halting the host channel. ++ */ ++ dwc_otg_halt_status_e halt_status; ++ ++ /* ++ * Split settings for the host channel ++ */ ++ uint8_t do_split; /**< Enable split for the channel */ ++ uint8_t complete_split; /**< Enable complete split */ ++ uint8_t hub_addr; /**< Address of high speed hub */ ++ ++ uint8_t port_addr; /**< Port of the low/full speed device */ ++ /** Split transaction position ++ * One of the following values: ++ * - DWC_HCSPLIT_XACTPOS_MID ++ * - DWC_HCSPLIT_XACTPOS_BEGIN ++ * - DWC_HCSPLIT_XACTPOS_END ++ * - DWC_HCSPLIT_XACTPOS_ALL */ ++ uint8_t xact_pos; ++ ++ /** Set when the host channel does a short read. */ ++ uint8_t short_read; ++ ++ /** ++ * Number of requests issued for this channel since it was assigned to ++ * the current transfer (not counting PINGs). ++ */ ++ uint8_t requests; ++ ++ /** ++ * Queue Head for the transfer being processed by this channel. ++ */ ++ struct dwc_otg_qh *qh; ++ ++ /** @} */ ++ ++ /** Entry in list of host channels. */ ++ DWC_CIRCLEQ_ENTRY(dwc_hc) hc_list_entry; ++ ++ /** @name Descriptor DMA support */ ++ /** @{ */ ++ ++ /** Number of Transfer Descriptors */ ++ uint16_t ntd; ++ ++ /** Descriptor List DMA address */ ++ dwc_dma_t desc_list_addr; ++ ++ /** Scheduling micro-frame bitmap. */ ++ uint8_t schinfo; ++ ++ /** @} */ ++} dwc_hc_t; ++ ++/** ++ * The following parameters may be specified when starting the module. These ++ * parameters define how the DWC_otg controller should be configured. ++ */ ++typedef struct dwc_otg_core_params { ++ int32_t opt; ++ ++ /** ++ * Specifies the OTG capabilities. The driver will automatically ++ * detect the value for this parameter if none is specified. ++ * 0 - HNP and SRP capable (default) ++ * 1 - SRP Only capable ++ * 2 - No HNP/SRP capable ++ */ ++ int32_t otg_cap; ++ ++ /** ++ * Specifies whether to use slave or DMA mode for accessing the data ++ * FIFOs. The driver will automatically detect the value for this ++ * parameter if none is specified. ++ * 0 - Slave ++ * 1 - DMA (default, if available) ++ */ ++ int32_t dma_enable; ++ ++ /** ++ * When DMA mode is enabled specifies whether to use address DMA or DMA Descritor mode for accessing the data ++ * FIFOs in device mode. The driver will automatically detect the value for this ++ * parameter if none is specified. ++ * 0 - address DMA ++ * 1 - DMA Descriptor(default, if available) ++ */ ++ int32_t dma_desc_enable; ++ /** The DMA Burst size (applicable only for External DMA ++ * Mode). 1, 4, 8 16, 32, 64, 128, 256 (default 32) ++ */ ++ int32_t dma_burst_size; /* Translate this to GAHBCFG values */ ++ ++ /** ++ * Specifies the maximum speed of operation in host and device mode. ++ * The actual speed depends on the speed of the attached device and ++ * the value of phy_type. The actual speed depends on the speed of the ++ * attached device. ++ * 0 - High Speed (default) ++ * 1 - Full Speed ++ */ ++ int32_t speed; ++ /** Specifies whether low power mode is supported when attached ++ * to a Full Speed or Low Speed device in host mode. ++ * 0 - Don't support low power mode (default) ++ * 1 - Support low power mode ++ */ ++ int32_t host_support_fs_ls_low_power; ++ ++ /** Specifies the PHY clock rate in low power mode when connected to a ++ * Low Speed device in host mode. This parameter is applicable only if ++ * HOST_SUPPORT_FS_LS_LOW_POWER is enabled. If PHY_TYPE is set to FS ++ * then defaults to 6 MHZ otherwise 48 MHZ. ++ * ++ * 0 - 48 MHz ++ * 1 - 6 MHz ++ */ ++ int32_t host_ls_low_power_phy_clk; ++ ++ /** ++ * 0 - Use cC FIFO size parameters ++ * 1 - Allow dynamic FIFO sizing (default) ++ */ ++ int32_t enable_dynamic_fifo; ++ ++ /** Total number of 4-byte words in the data FIFO memory. This ++ * memory includes the Rx FIFO, non-periodic Tx FIFO, and periodic ++ * Tx FIFOs. ++ * 32 to 32768 (default 8192) ++ * Note: The total FIFO memory depth in the FPGA configuration is 8192. ++ */ ++ int32_t data_fifo_size; ++ ++ /** Number of 4-byte words in the Rx FIFO in device mode when dynamic ++ * FIFO sizing is enabled. ++ * 16 to 32768 (default 1064) ++ */ ++ int32_t dev_rx_fifo_size; ++ ++ /** Number of 4-byte words in the non-periodic Tx FIFO in device mode ++ * when dynamic FIFO sizing is enabled. ++ * 16 to 32768 (default 1024) ++ */ ++ int32_t dev_nperio_tx_fifo_size; ++ ++ /** Number of 4-byte words in each of the periodic Tx FIFOs in device ++ * mode when dynamic FIFO sizing is enabled. ++ * 4 to 768 (default 256) ++ */ ++ uint32_t dev_perio_tx_fifo_size[MAX_PERIO_FIFOS]; ++ ++ /** Number of 4-byte words in the Rx FIFO in host mode when dynamic ++ * FIFO sizing is enabled. ++ * 16 to 32768 (default 1024) ++ */ ++ int32_t host_rx_fifo_size; ++ ++ /** Number of 4-byte words in the non-periodic Tx FIFO in host mode ++ * when Dynamic FIFO sizing is enabled in the core. ++ * 16 to 32768 (default 1024) ++ */ ++ int32_t host_nperio_tx_fifo_size; ++ ++ /** Number of 4-byte words in the host periodic Tx FIFO when dynamic ++ * FIFO sizing is enabled. ++ * 16 to 32768 (default 1024) ++ */ ++ int32_t host_perio_tx_fifo_size; ++ ++ /** The maximum transfer size supported in bytes. ++ * 2047 to 65,535 (default 65,535) ++ */ ++ int32_t max_transfer_size; ++ ++ /** The maximum number of packets in a transfer. ++ * 15 to 511 (default 511) ++ */ ++ int32_t max_packet_count; ++ ++ /** The number of host channel registers to use. ++ * 1 to 16 (default 12) ++ * Note: The FPGA configuration supports a maximum of 12 host channels. ++ */ ++ int32_t host_channels; ++ ++ /** The number of endpoints in addition to EP0 available for device ++ * mode operations. ++ * 1 to 15 (default 6 IN and OUT) ++ * Note: The FPGA configuration supports a maximum of 6 IN and OUT ++ * endpoints in addition to EP0. ++ */ ++ int32_t dev_endpoints; ++ ++ /** ++ * Specifies the type of PHY interface to use. By default, the driver ++ * will automatically detect the phy_type. ++ * ++ * 0 - Full Speed PHY ++ * 1 - UTMI+ (default) ++ * 2 - ULPI ++ */ ++ int32_t phy_type; ++ ++ /** ++ * Specifies the UTMI+ Data Width. This parameter is ++ * applicable for a PHY_TYPE of UTMI+ or ULPI. (For a ULPI ++ * PHY_TYPE, this parameter indicates the data width between ++ * the MAC and the ULPI Wrapper.) Also, this parameter is ++ * applicable only if the OTG_HSPHY_WIDTH cC parameter was set ++ * to "8 and 16 bits", meaning that the core has been ++ * configured to work at either data path width. ++ * ++ * 8 or 16 bits (default 16) ++ */ ++ int32_t phy_utmi_width; ++ ++ /** ++ * Specifies whether the ULPI operates at double or single ++ * data rate. This parameter is only applicable if PHY_TYPE is ++ * ULPI. ++ * ++ * 0 - single data rate ULPI interface with 8 bit wide data ++ * bus (default) ++ * 1 - double data rate ULPI interface with 4 bit wide data ++ * bus ++ */ ++ int32_t phy_ulpi_ddr; ++ ++ /** ++ * Specifies whether to use the internal or external supply to ++ * drive the vbus with a ULPI phy. ++ */ ++ int32_t phy_ulpi_ext_vbus; ++ ++ /** ++ * Specifies whether to use the I2Cinterface for full speed PHY. This ++ * parameter is only applicable if PHY_TYPE is FS. ++ * 0 - No (default) ++ * 1 - Yes ++ */ ++ int32_t i2c_enable; ++ ++ int32_t ulpi_fs_ls; ++ ++ int32_t ts_dline; ++ ++ /** ++ * Specifies whether dedicated transmit FIFOs are ++ * enabled for non periodic IN endpoints in device mode ++ * 0 - No ++ * 1 - Yes ++ */ ++ int32_t en_multiple_tx_fifo; ++ ++ /** Number of 4-byte words in each of the Tx FIFOs in device ++ * mode when dynamic FIFO sizing is enabled. ++ * 4 to 768 (default 256) ++ */ ++ uint32_t dev_tx_fifo_size[MAX_TX_FIFOS]; ++ ++ /** Thresholding enable flag- ++ * bit 0 - enable non-ISO Tx thresholding ++ * bit 1 - enable ISO Tx thresholding ++ * bit 2 - enable Rx thresholding ++ */ ++ uint32_t thr_ctl; ++ ++ /** Thresholding length for Tx ++ * FIFOs in 32 bit DWORDs ++ */ ++ uint32_t tx_thr_length; ++ ++ /** Thresholding length for Rx ++ * FIFOs in 32 bit DWORDs ++ */ ++ uint32_t rx_thr_length; ++ ++ /** ++ * Specifies whether LPM (Link Power Management) support is enabled ++ */ ++ int32_t lpm_enable; ++ ++ /** Per Transfer Interrupt ++ * mode enable flag ++ * 1 - Enabled ++ * 0 - Disabled ++ */ ++ int32_t pti_enable; ++ ++ /** Multi Processor Interrupt ++ * mode enable flag ++ * 1 - Enabled ++ * 0 - Disabled ++ */ ++ int32_t mpi_enable; ++ ++ /** IS_USB Capability ++ * 1 - Enabled ++ * 0 - Disabled ++ */ ++ int32_t ic_usb_cap; ++ ++ /** AHB Threshold Ratio ++ * 2'b00 AHB Threshold = MAC Threshold ++ * 2'b01 AHB Threshold = 1/2 MAC Threshold ++ * 2'b10 AHB Threshold = 1/4 MAC Threshold ++ * 2'b11 AHB Threshold = 1/8 MAC Threshold ++ */ ++ int32_t ahb_thr_ratio; ++ ++} dwc_otg_core_params_t; ++ ++#ifdef DEBUG ++struct dwc_otg_core_if; ++typedef struct hc_xfer_info { ++ struct dwc_otg_core_if *core_if; ++ dwc_hc_t *hc; ++} hc_xfer_info_t; ++#endif ++/* ++ * Device States ++ */ ++typedef enum dwc_otg_lx_state { ++ /** On state */ ++ DWC_OTG_L0, ++ /** LPM sleep state*/ ++ DWC_OTG_L1, ++ /** USB suspend state*/ ++ DWC_OTG_L2, ++ /** Off state*/ ++ DWC_OTG_L3 ++} dwc_otg_lx_state_e; ++ ++/** ++ * The dwc_otg_core_if structure contains information needed to manage ++ * the DWC_otg controller acting in either host or device mode. It ++ * represents the programming view of the controller as a whole. ++ */ ++struct dwc_otg_core_if { ++ /** Parameters that define how the core should be configured.*/ ++ dwc_otg_core_params_t *core_params; ++ ++ /** Core Global registers starting at offset 000h. */ ++ dwc_otg_core_global_regs_t *core_global_regs; ++ ++ /** Device-specific information */ ++ dwc_otg_dev_if_t *dev_if; ++ /** Host-specific information */ ++ dwc_otg_host_if_t *host_if; ++ ++ /** Value from SNPSID register */ ++ uint32_t snpsid; ++ ++ /* ++ * Set to 1 if the core PHY interface bits in USBCFG have been ++ * initialized. ++ */ ++ uint8_t phy_init_done; ++ ++ /* ++ * SRP Success flag, set by srp success interrupt in FS I2C mode ++ */ ++ uint8_t srp_success; ++ uint8_t srp_timer_started; ++ ++ /* Common configuration information */ ++ /** Power and Clock Gating Control Register */ ++ volatile uint32_t *pcgcctl; ++#define DWC_OTG_PCGCCTL_OFFSET 0xE00 ++ ++ /** Push/pop addresses for endpoints or host channels.*/ ++ uint32_t *data_fifo[MAX_EPS_CHANNELS]; ++#define DWC_OTG_DATA_FIFO_OFFSET 0x1000 ++#define DWC_OTG_DATA_FIFO_SIZE 0x1000 ++ ++ /** Total RAM for FIFOs (Bytes) */ ++ uint16_t total_fifo_size; ++ /** Size of Rx FIFO (Bytes) */ ++ uint16_t rx_fifo_size; ++ /** Size of Non-periodic Tx FIFO (Bytes) */ ++ uint16_t nperio_tx_fifo_size; ++ ++ /** 1 if DMA is enabled, 0 otherwise. */ ++ uint8_t dma_enable; ++ ++ /** 1 if DMA descriptor is enabled, 0 otherwise. */ ++ uint8_t dma_desc_enable; ++ ++ /** 1 if PTI Enhancement mode is enabled, 0 otherwise. */ ++ uint8_t pti_enh_enable; ++ ++ /** 1 if MPI Enhancement mode is enabled, 0 otherwise. */ ++ uint8_t multiproc_int_enable; ++ ++ /** 1 if dedicated Tx FIFOs are enabled, 0 otherwise. */ ++ uint8_t en_multiple_tx_fifo; ++ ++ /** Set to 1 if multiple packets of a high-bandwidth transfer is in ++ * process of being queued */ ++ uint8_t queuing_high_bandwidth; ++ ++ /** Hardware Configuration -- stored here for convenience.*/ ++ hwcfg1_data_t hwcfg1; ++ hwcfg2_data_t hwcfg2; ++ hwcfg3_data_t hwcfg3; ++ hwcfg4_data_t hwcfg4; ++ ++ /** Host and Device Configuration -- stored here for convenience.*/ ++ hcfg_data_t hcfg; ++ dcfg_data_t dcfg; ++ ++ /** The operational State, during transations ++ * (a_host>>a_peripherial and b_device=>b_host) this may not ++ * match the core but allows the software to determine ++ * transitions. ++ */ ++ uint8_t op_state; ++ ++ /** ++ * Set to 1 if the HCD needs to be restarted on a session request ++ * interrupt. This is required if no connector ID status change has ++ * occurred since the HCD was last disconnected. ++ */ ++ uint8_t restart_hcd_on_session_req; ++ ++ /** HCD callbacks */ ++ /** A-Device is a_host */ ++#define A_HOST (1) ++ /** A-Device is a_suspend */ ++#define A_SUSPEND (2) ++ /** A-Device is a_peripherial */ ++#define A_PERIPHERAL (3) ++ /** B-Device is operating as a Peripheral. */ ++#define B_PERIPHERAL (4) ++ /** B-Device is operating as a Host. */ ++#define B_HOST (5) ++ ++ /** HCD callbacks */ ++ struct dwc_otg_cil_callbacks *hcd_cb; ++ /** PCD callbacks */ ++ struct dwc_otg_cil_callbacks *pcd_cb; ++ ++ /** Device mode Periodic Tx FIFO Mask */ ++ uint32_t p_tx_msk; ++ /** Device mode Periodic Tx FIFO Mask */ ++ uint32_t tx_msk; ++ ++ /** Workqueue object used for handling several interrupts */ ++ dwc_workq_t *wq_otg; ++ ++ /** Timer object used for handling "Wakeup Detected" Interrupt */ ++ dwc_timer_t *wkp_timer; ++ ++#ifdef DEBUG ++ uint32_t start_hcchar_val[MAX_EPS_CHANNELS]; ++ ++ hc_xfer_info_t hc_xfer_info[MAX_EPS_CHANNELS]; ++ dwc_timer_t *hc_xfer_timer[MAX_EPS_CHANNELS]; ++ ++ uint32_t hfnum_7_samples; ++ uint64_t hfnum_7_frrem_accum; ++ uint32_t hfnum_0_samples; ++ uint64_t hfnum_0_frrem_accum; ++ uint32_t hfnum_other_samples; ++ uint64_t hfnum_other_frrem_accum; ++#endif ++ ++#ifdef DWC_UTE_CFI ++ uint16_t pwron_rxfsiz; ++ uint16_t pwron_gnptxfsiz; ++ uint16_t pwron_txfsiz[15]; ++ ++ uint16_t init_rxfsiz; ++ uint16_t init_gnptxfsiz; ++ uint16_t init_txfsiz[15]; ++#endif ++ ++ /** Lx state of device */ ++ dwc_otg_lx_state_e lx_state; ++ ++}; ++ ++#ifdef DEBUG ++/* ++ * This function is called when transfer is timed out. ++ */ ++extern void hc_xfer_timeout(void *ptr); ++#endif ++ ++/* ++ * The following functions are functions for works ++ * using during handling some interrupts ++ */ ++extern void w_conn_id_status_change(void *p); ++ ++extern void w_wakeup_detected(void *p); ++ ++/* ++ * The following functions support initialization of the CIL driver component ++ * and the DWC_otg controller. ++ */ ++extern void dwc_otg_core_host_init(dwc_otg_core_if_t * _core_if); ++extern void dwc_otg_core_dev_init(dwc_otg_core_if_t * _core_if); ++ ++/** @name Device CIL Functions ++ * The following functions support managing the DWC_otg controller in device ++ * mode. ++ */ ++/**@{*/ ++extern void dwc_otg_wakeup(dwc_otg_core_if_t * _core_if); ++extern void dwc_otg_read_setup_packet(dwc_otg_core_if_t * _core_if, ++ uint32_t * _dest); ++extern uint32_t dwc_otg_get_frame_number(dwc_otg_core_if_t * _core_if); ++extern void dwc_otg_ep0_activate(dwc_otg_core_if_t * _core_if, dwc_ep_t * _ep); ++extern void dwc_otg_ep_activate(dwc_otg_core_if_t * _core_if, dwc_ep_t * _ep); ++extern void dwc_otg_ep_deactivate(dwc_otg_core_if_t * _core_if, dwc_ep_t * _ep); ++extern void dwc_otg_ep_start_transfer(dwc_otg_core_if_t * _core_if, ++ dwc_ep_t * _ep); ++extern void dwc_otg_ep_start_zl_transfer(dwc_otg_core_if_t * _core_if, ++ dwc_ep_t * _ep); ++extern void dwc_otg_ep0_start_transfer(dwc_otg_core_if_t * _core_if, ++ dwc_ep_t * _ep); ++extern void dwc_otg_ep0_continue_transfer(dwc_otg_core_if_t * _core_if, ++ dwc_ep_t * _ep); ++extern void dwc_otg_ep_write_packet(dwc_otg_core_if_t * _core_if, ++ dwc_ep_t * _ep, int _dma); ++extern void dwc_otg_ep_set_stall(dwc_otg_core_if_t * _core_if, dwc_ep_t * _ep); ++extern void dwc_otg_ep_clear_stall(dwc_otg_core_if_t * _core_if, ++ dwc_ep_t * _ep); ++extern void dwc_otg_enable_device_interrupts(dwc_otg_core_if_t * _core_if); ++ ++#ifdef DWC_EN_ISOC ++extern void dwc_otg_iso_ep_start_frm_transfer(dwc_otg_core_if_t * core_if, ++ dwc_ep_t * ep); ++extern void dwc_otg_iso_ep_start_buf_transfer(dwc_otg_core_if_t * core_if, ++ dwc_ep_t * ep); ++#endif /* DWC_EN_ISOC */ ++/**@}*/ ++ ++/** @name Host CIL Functions ++ * The following functions support managing the DWC_otg controller in host ++ * mode. ++ */ ++/**@{*/ ++extern void dwc_otg_hc_init(dwc_otg_core_if_t * _core_if, dwc_hc_t * _hc); ++extern void dwc_otg_hc_halt(dwc_otg_core_if_t * _core_if, ++ dwc_hc_t * _hc, dwc_otg_halt_status_e _halt_status); ++extern void dwc_otg_hc_cleanup(dwc_otg_core_if_t * _core_if, dwc_hc_t * _hc); ++extern void dwc_otg_hc_start_transfer(dwc_otg_core_if_t * _core_if, ++ dwc_hc_t * _hc); ++extern int dwc_otg_hc_continue_transfer(dwc_otg_core_if_t * _core_if, ++ dwc_hc_t * _hc); ++extern void dwc_otg_hc_do_ping(dwc_otg_core_if_t * _core_if, dwc_hc_t * _hc); ++extern void dwc_otg_hc_write_packet(dwc_otg_core_if_t * _core_if, ++ dwc_hc_t * _hc); ++extern void dwc_otg_enable_host_interrupts(dwc_otg_core_if_t * _core_if); ++extern void dwc_otg_disable_host_interrupts(dwc_otg_core_if_t * _core_if); ++ ++extern void dwc_otg_hc_start_transfer_ddma(dwc_otg_core_if_t * core_if, dwc_hc_t * hc); ++ ++/* Macro used to clear one channel interrupt */ ++#define clear_hc_int(_hc_regs_, _intr_) \ ++do { \ ++ hcint_data_t hcint_clear = {.d32 = 0}; \ ++ hcint_clear.b._intr_ = 1; \ ++ dwc_write_reg32(&(_hc_regs_)->hcint, hcint_clear.d32); \ ++} while (0) ++ ++/* ++ * Macro used to disable one channel interrupt. Channel interrupts are ++ * disabled when the channel is halted or released by the interrupt handler. ++ * There is no need to handle further interrupts of that type until the ++ * channel is re-assigned. In fact, subsequent handling may cause crashes ++ * because the channel structures are cleaned up when the channel is released. ++ */ ++#define disable_hc_int(_hc_regs_, _intr_) \ ++do { \ ++ hcintmsk_data_t hcintmsk = {.d32 = 0}; \ ++ hcintmsk.b._intr_ = 1; \ ++ dwc_modify_reg32(&(_hc_regs_)->hcintmsk, hcintmsk.d32, 0); \ ++} while (0) ++ ++/** ++ * This function Reads HPRT0 in preparation to modify. It keeps the ++ * WC bits 0 so that if they are read as 1, they won't clear when you ++ * write it back ++ */ ++static inline uint32_t dwc_otg_read_hprt0(dwc_otg_core_if_t * _core_if) ++{ ++ hprt0_data_t hprt0; ++ hprt0.d32 = dwc_read_reg32(_core_if->host_if->hprt0); ++ hprt0.b.prtena = 0; ++ hprt0.b.prtconndet = 0; ++ hprt0.b.prtenchng = 0; ++ hprt0.b.prtovrcurrchng = 0; ++ return hprt0.d32; ++} ++ ++/**@}*/ ++ ++/** @name Common CIL Functions ++ * The following functions support managing the DWC_otg controller in either ++ * device or host mode. ++ */ ++/**@{*/ ++ ++extern void dwc_otg_read_packet(dwc_otg_core_if_t * core_if, ++ uint8_t * dest, uint16_t bytes); ++ ++extern void dwc_otg_flush_tx_fifo(dwc_otg_core_if_t * _core_if, const int _num); ++extern void dwc_otg_flush_rx_fifo(dwc_otg_core_if_t * _core_if); ++extern void dwc_otg_core_reset(dwc_otg_core_if_t * _core_if); ++ ++/** ++ * This function returns the Core Interrupt register. ++ */ ++static inline uint32_t dwc_otg_read_core_intr(dwc_otg_core_if_t * core_if) ++{ ++ return (dwc_read_reg32(&core_if->core_global_regs->gintsts) & ++ dwc_read_reg32(&core_if->core_global_regs->gintmsk)); ++} ++ ++/** ++ * This function returns the OTG Interrupt register. ++ */ ++static inline uint32_t dwc_otg_read_otg_intr(dwc_otg_core_if_t * core_if) ++{ ++ return (dwc_read_reg32(&core_if->core_global_regs->gotgint)); ++} ++ ++/** ++ * This function reads the Device All Endpoints Interrupt register and ++ * returns the IN endpoint interrupt bits. ++ */ ++static inline uint32_t dwc_otg_read_dev_all_in_ep_intr(dwc_otg_core_if_t * ++ core_if) ++{ ++ ++ uint32_t v; ++ ++ if (core_if->multiproc_int_enable) { ++ v = dwc_read_reg32(&core_if->dev_if->dev_global_regs-> ++ deachint) & dwc_read_reg32(&core_if->dev_if-> ++ dev_global_regs-> ++ deachintmsk); ++ } else { ++ v = dwc_read_reg32(&core_if->dev_if->dev_global_regs->daint) & ++ dwc_read_reg32(&core_if->dev_if->dev_global_regs->daintmsk); ++ } ++ return (v & 0xffff); ++} ++ ++/** ++ * This function reads the Device All Endpoints Interrupt register and ++ * returns the OUT endpoint interrupt bits. ++ */ ++static inline uint32_t dwc_otg_read_dev_all_out_ep_intr(dwc_otg_core_if_t * ++ core_if) ++{ ++ uint32_t v; ++ ++ if (core_if->multiproc_int_enable) { ++ v = dwc_read_reg32(&core_if->dev_if->dev_global_regs-> ++ deachint) & dwc_read_reg32(&core_if->dev_if-> ++ dev_global_regs-> ++ deachintmsk); ++ } else { ++ v = dwc_read_reg32(&core_if->dev_if->dev_global_regs->daint) & ++ dwc_read_reg32(&core_if->dev_if->dev_global_regs->daintmsk); ++ } ++ ++ return ((v & 0xffff0000) >> 16); ++} ++ ++/** ++ * This function returns the Device IN EP Interrupt register ++ */ ++static inline uint32_t dwc_otg_read_dev_in_ep_intr(dwc_otg_core_if_t * core_if, ++ dwc_ep_t * ep) ++{ ++ dwc_otg_dev_if_t *dev_if = core_if->dev_if; ++ uint32_t v, msk, emp; ++ ++ if (core_if->multiproc_int_enable) { ++ msk = ++ dwc_read_reg32(&dev_if->dev_global_regs-> ++ diepeachintmsk[ep->num]); ++ emp = ++ dwc_read_reg32(&dev_if->dev_global_regs-> ++ dtknqr4_fifoemptymsk); ++ msk |= ((emp >> ep->num) & 0x1) << 7; ++ v = dwc_read_reg32(&dev_if->in_ep_regs[ep->num]->diepint) & msk; ++ } else { ++ msk = dwc_read_reg32(&dev_if->dev_global_regs->diepmsk); ++ emp = ++ dwc_read_reg32(&dev_if->dev_global_regs-> ++ dtknqr4_fifoemptymsk); ++ msk |= ((emp >> ep->num) & 0x1) << 7; ++ v = dwc_read_reg32(&dev_if->in_ep_regs[ep->num]->diepint) & msk; ++ } ++ ++ return v; ++} ++ ++/** ++ * This function returns the Device OUT EP Interrupt register ++ */ ++static inline uint32_t dwc_otg_read_dev_out_ep_intr(dwc_otg_core_if_t * ++ _core_if, dwc_ep_t * _ep) ++{ ++ dwc_otg_dev_if_t *dev_if = _core_if->dev_if; ++ uint32_t v; ++ doepmsk_data_t msk = {.d32 = 0 }; ++ ++ if (_core_if->multiproc_int_enable) { ++ msk.d32 = ++ dwc_read_reg32(&dev_if->dev_global_regs-> ++ doepeachintmsk[_ep->num]); ++ if (_core_if->pti_enh_enable) { ++ msk.b.pktdrpsts = 1; ++ } ++ v = dwc_read_reg32(&dev_if->out_ep_regs[_ep->num]-> ++ doepint) & msk.d32; ++ } else { ++ msk.d32 = dwc_read_reg32(&dev_if->dev_global_regs->doepmsk); ++ if (_core_if->pti_enh_enable) { ++ msk.b.pktdrpsts = 1; ++ } ++ v = dwc_read_reg32(&dev_if->out_ep_regs[_ep->num]-> ++ doepint) & msk.d32; ++ } ++ return v; ++} ++ ++/** ++ * This function returns the Host All Channel Interrupt register ++ */ ++static inline uint32_t dwc_otg_read_host_all_channels_intr(dwc_otg_core_if_t * ++ _core_if) ++{ ++ return (dwc_read_reg32(&_core_if->host_if->host_global_regs->haint)); ++} ++ ++static inline uint32_t dwc_otg_read_host_channel_intr(dwc_otg_core_if_t * ++ _core_if, dwc_hc_t * _hc) ++{ ++ return (dwc_read_reg32 ++ (&_core_if->host_if->hc_regs[_hc->hc_num]->hcint)); ++} ++ ++/** ++ * This function returns the mode of the operation, host or device. ++ * ++ * @return 0 - Device Mode, 1 - Host Mode ++ */ ++static inline uint32_t dwc_otg_mode(dwc_otg_core_if_t * _core_if) ++{ ++ return (dwc_read_reg32(&_core_if->core_global_regs->gintsts) & 0x1); ++} ++ ++/**@}*/ ++ ++/** ++ * DWC_otg CIL callback structure. This structure allows the HCD and ++ * PCD to register functions used for starting and stopping the PCD ++ * and HCD for role change on for a DRD. ++ */ ++typedef struct dwc_otg_cil_callbacks { ++ /** Start function for role change */ ++ int (*start) (void *_p); ++ /** Stop Function for role change */ ++ int (*stop) (void *_p); ++ /** Disconnect Function for role change */ ++ int (*disconnect) (void *_p); ++ /** Resume/Remote wakeup Function */ ++ int (*resume_wakeup) (void *_p); ++ /** Suspend function */ ++ int (*suspend) (void *_p); ++ /** Session Start (SRP) */ ++ int (*session_start) (void *_p); ++#ifdef CONFIG_USB_DWC_OTG_LPM ++ /** Sleep (switch to L0 state) */ ++ int (*sleep) (void *_p); ++#endif ++ /** Pointer passed to start() and stop() */ ++ void *p; ++} dwc_otg_cil_callbacks_t; ++ ++extern void dwc_otg_cil_register_pcd_callbacks(dwc_otg_core_if_t * _core_if, ++ dwc_otg_cil_callbacks_t * _cb, ++ void *_p); ++extern void dwc_otg_cil_register_hcd_callbacks(dwc_otg_core_if_t * _core_if, ++ dwc_otg_cil_callbacks_t * _cb, ++ void *_p); ++ ++#endif +Index: linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_cil_intr.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_cil_intr.c 2013-07-26 19:31:23.000000000 +0000 +@@ -0,0 +1,846 @@ ++/* ========================================================================== ++ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_cil_intr.c $ ++ * $Revision: #15 $ ++ * $Date: 2009/04/15 $ ++ * $Change: 1234129 $ ++ * ++ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, ++ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless ++ * otherwise expressly agreed to in writing between Synopsys and you. ++ * ++ * The Software IS NOT an item of Licensed Software or Licensed Product under ++ * any End User Software License Agreement or Agreement for Licensed Product ++ * with Synopsys or any supplement thereto. You are permitted to use and ++ * redistribute this Software in source and binary forms, with or without ++ * modification, provided that redistributions of source code must retain this ++ * notice. You may not view, use, disclose, copy or distribute this file or ++ * any information contained herein except pursuant to this license grant from ++ * Synopsys. If you do not agree with this notice, including the disclaimer ++ * below, then you are not authorized to use the Software. ++ * ++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, ++ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR ++ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER ++ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY ++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH ++ * DAMAGE. ++ * ========================================================================== */ ++ ++/** @file ++ * ++ * The Core Interface Layer provides basic services for accessing and ++ * managing the DWC_otg hardware. These services are used by both the ++ * Host Controller Driver and the Peripheral Controller Driver. ++ * ++ * This file contains the Common Interrupt handlers. ++ */ ++#include "dwc_os.h" ++#include "dwc_otg_regs.h" ++#include "dwc_otg_cil.h" ++ ++#ifdef DEBUG ++inline const char *op_state_str(dwc_otg_core_if_t * core_if) ++{ ++ return (core_if->op_state == A_HOST ? "a_host" : ++ (core_if->op_state == A_SUSPEND ? "a_suspend" : ++ (core_if->op_state == A_PERIPHERAL ? "a_peripheral" : ++ (core_if->op_state == B_PERIPHERAL ? "b_peripheral" : ++ (core_if->op_state == B_HOST ? "b_host" : "unknown"))))); ++} ++#endif ++ ++/** This function will log a debug message ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ */ ++int32_t dwc_otg_handle_mode_mismatch_intr(dwc_otg_core_if_t * core_if) ++{ ++ gintsts_data_t gintsts; ++ DWC_WARN("Mode Mismatch Interrupt: currently in %s mode\n", ++ dwc_otg_mode(core_if) ? "Host" : "Device"); ++ ++ /* Clear interrupt */ ++ gintsts.d32 = 0; ++ gintsts.b.modemismatch = 1; ++ dwc_write_reg32(&core_if->core_global_regs->gintsts, gintsts.d32); ++ return 1; ++} ++ ++/** Start the HCD. Helper function for using the HCD callbacks. ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ */ ++static inline void hcd_start(dwc_otg_core_if_t * core_if) ++{ ++ if (core_if->hcd_cb && core_if->hcd_cb->start) { ++ core_if->hcd_cb->start(core_if->hcd_cb->p); ++ } ++} ++ ++/** Stop the HCD. Helper function for using the HCD callbacks. ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ */ ++static inline void hcd_stop(dwc_otg_core_if_t * core_if) ++{ ++ if (core_if->hcd_cb && core_if->hcd_cb->stop) { ++ core_if->hcd_cb->stop(core_if->hcd_cb->p); ++ } ++} ++ ++/** Disconnect the HCD. Helper function for using the HCD callbacks. ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ */ ++static inline void hcd_disconnect(dwc_otg_core_if_t * core_if) ++{ ++ if (core_if->hcd_cb && core_if->hcd_cb->disconnect) { ++ core_if->hcd_cb->disconnect(core_if->hcd_cb->p); ++ } ++} ++ ++/** Inform the HCD the a New Session has begun. Helper function for ++ * using the HCD callbacks. ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ */ ++static inline void hcd_session_start(dwc_otg_core_if_t * core_if) ++{ ++ if (core_if->hcd_cb && core_if->hcd_cb->session_start) { ++ core_if->hcd_cb->session_start(core_if->hcd_cb->p); ++ } ++} ++ ++#ifdef CONFIG_USB_DWC_OTG_LPM ++/** ++ * Inform the HCD about LPM sleep. ++ * Helper function for using the HCD callbacks. ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ */ ++static inline void hcd_sleep(dwc_otg_core_if_t * core_if) ++{ ++ if (core_if->hcd_cb && core_if->hcd_cb->sleep) { ++ core_if->hcd_cb->sleep(core_if->hcd_cb->p); ++ } ++} ++#endif ++ ++/** Resume the HCD. Helper function for using the HCD callbacks. ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ */ ++static inline void hcd_resume(dwc_otg_core_if_t * core_if) ++{ ++ if (core_if->hcd_cb && core_if->hcd_cb->resume_wakeup) { ++ core_if->hcd_cb->resume_wakeup(core_if->hcd_cb->p); ++ } ++} ++ ++/** Start the PCD. Helper function for using the PCD callbacks. ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ */ ++static inline void pcd_start(dwc_otg_core_if_t * core_if) ++{ ++ if (core_if->pcd_cb && core_if->pcd_cb->start) { ++ core_if->pcd_cb->start(core_if->pcd_cb->p); ++ } ++} ++ ++/** Stop the PCD. Helper function for using the PCD callbacks. ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ */ ++static inline void pcd_stop(dwc_otg_core_if_t * core_if) ++{ ++ if (core_if->pcd_cb && core_if->pcd_cb->stop) { ++ core_if->pcd_cb->stop(core_if->pcd_cb->p); ++ } ++} ++ ++/** Suspend the PCD. Helper function for using the PCD callbacks. ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ */ ++static inline void pcd_suspend(dwc_otg_core_if_t * core_if) ++{ ++ if (core_if->pcd_cb && core_if->pcd_cb->suspend) { ++ core_if->pcd_cb->suspend(core_if->pcd_cb->p); ++ } ++} ++ ++/** Resume the PCD. Helper function for using the PCD callbacks. ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ */ ++static inline void pcd_resume(dwc_otg_core_if_t * core_if) ++{ ++ if (core_if->pcd_cb && core_if->pcd_cb->resume_wakeup) { ++ core_if->pcd_cb->resume_wakeup(core_if->pcd_cb->p); ++ } ++} ++ ++/** ++ * This function handles the OTG Interrupts. It reads the OTG ++ * Interrupt Register (GOTGINT) to determine what interrupt has ++ * occurred. ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ */ ++int32_t dwc_otg_handle_otg_intr(dwc_otg_core_if_t * core_if) ++{ ++ dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs; ++ gotgint_data_t gotgint; ++ gotgctl_data_t gotgctl; ++ gintmsk_data_t gintmsk; ++ ++ gotgint.d32 = dwc_read_reg32(&global_regs->gotgint); ++ gotgctl.d32 = dwc_read_reg32(&global_regs->gotgctl); ++ DWC_DEBUGPL(DBG_CIL, "++OTG Interrupt gotgint=%0x [%s]\n", gotgint.d32, ++ op_state_str(core_if)); ++ ++ if (gotgint.b.sesenddet) { ++ DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: " ++ "Session End Detected++ (%s)\n", ++ op_state_str(core_if)); ++ gotgctl.d32 = dwc_read_reg32(&global_regs->gotgctl); ++ ++ if (core_if->op_state == B_HOST) { ++ pcd_start(core_if); ++ core_if->op_state = B_PERIPHERAL; ++ } else { ++ /* If not B_HOST and Device HNP still set. HNP ++ * Did not succeed!*/ ++ if (gotgctl.b.devhnpen) { ++ DWC_DEBUGPL(DBG_ANY, "Session End Detected\n"); ++ __DWC_ERROR("Device Not Connected/Responding!\n"); ++ } ++ ++ /* If Session End Detected the B-Cable has ++ * been disconnected. */ ++ /* Reset PCD and Gadget driver to a ++ * clean state. */ ++ core_if->lx_state = DWC_OTG_L0; ++ pcd_stop(core_if); ++ } ++ gotgctl.d32 = 0; ++ gotgctl.b.devhnpen = 1; ++ dwc_modify_reg32(&global_regs->gotgctl, gotgctl.d32, 0); ++ } ++ if (gotgint.b.sesreqsucstschng) { ++ DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: " ++ "Session Reqeust Success Status Change++\n"); ++ gotgctl.d32 = dwc_read_reg32(&global_regs->gotgctl); ++ if (gotgctl.b.sesreqscs) { ++ if ((core_if->core_params->phy_type == ++ DWC_PHY_TYPE_PARAM_FS) && (core_if->core_params->i2c_enable)) { ++ core_if->srp_success = 1; ++ } else { ++ pcd_resume(core_if); ++ /* Clear Session Request */ ++ gotgctl.d32 = 0; ++ gotgctl.b.sesreq = 1; ++ dwc_modify_reg32(&global_regs->gotgctl, ++ gotgctl.d32, 0); ++ } ++ } ++ } ++ if (gotgint.b.hstnegsucstschng) { ++ /* Print statements during the HNP interrupt handling ++ * can cause it to fail.*/ ++ gotgctl.d32 = dwc_read_reg32(&global_regs->gotgctl); ++ if (gotgctl.b.hstnegscs) { ++ if (dwc_otg_is_host_mode(core_if)) { ++ core_if->op_state = B_HOST; ++ /* ++ * Need to disable SOF interrupt immediately. ++ * When switching from device to host, the PCD ++ * interrupt handler won't handle the ++ * interrupt if host mode is already set. The ++ * HCD interrupt handler won't get called if ++ * the HCD state is HALT. This means that the ++ * interrupt does not get handled and Linux ++ * complains loudly. ++ */ ++ gintmsk.d32 = 0; ++ gintmsk.b.sofintr = 1; ++ dwc_modify_reg32(&global_regs->gintmsk, ++ gintmsk.d32, 0); ++ pcd_stop(core_if); ++ /* ++ * Initialize the Core for Host mode. ++ */ ++ hcd_start(core_if); ++ core_if->op_state = B_HOST; ++ } ++ } else { ++ gotgctl.d32 = 0; ++ gotgctl.b.hnpreq = 1; ++ gotgctl.b.devhnpen = 1; ++ dwc_modify_reg32(&global_regs->gotgctl, gotgctl.d32, 0); ++ DWC_DEBUGPL(DBG_ANY, "HNP Failed\n"); ++ __DWC_ERROR("Device Not Connected/Responding\n"); ++ } ++ } ++ if (gotgint.b.hstnegdet) { ++ /* The disconnect interrupt is set at the same time as ++ * Host Negotiation Detected. During the mode ++ * switch all interrupts are cleared so the disconnect ++ * interrupt handler will not get executed. ++ */ ++ DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: " ++ "Host Negotiation Detected++ (%s)\n", ++ (dwc_otg_is_host_mode(core_if) ? "Host" : ++ "Device")); ++ if (dwc_otg_is_device_mode(core_if)) { ++ DWC_DEBUGPL(DBG_ANY, "a_suspend->a_peripheral (%d)\n", ++ core_if->op_state); ++ hcd_disconnect(core_if); ++ pcd_start(core_if); ++ core_if->op_state = A_PERIPHERAL; ++ } else { ++ /* ++ * Need to disable SOF interrupt immediately. When ++ * switching from device to host, the PCD interrupt ++ * handler won't handle the interrupt if host mode is ++ * already set. The HCD interrupt handler won't get ++ * called if the HCD state is HALT. This means that ++ * the interrupt does not get handled and Linux ++ * complains loudly. ++ */ ++ gintmsk.d32 = 0; ++ gintmsk.b.sofintr = 1; ++ dwc_modify_reg32(&global_regs->gintmsk, gintmsk.d32, 0); ++ pcd_stop(core_if); ++ hcd_start(core_if); ++ core_if->op_state = A_HOST; ++ } ++ } ++ if (gotgint.b.adevtoutchng) { ++ DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: " ++ "A-Device Timeout Change++\n"); ++ } ++ if (gotgint.b.debdone) { ++ DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: " "Debounce Done++\n"); ++ } ++ ++ /* Clear GOTGINT */ ++ dwc_write_reg32(&core_if->core_global_regs->gotgint, gotgint.d32); ++ ++ return 1; ++} ++ ++void w_conn_id_status_change(void *p) ++{ ++ dwc_otg_core_if_t *core_if = p; ++ uint32_t count = 0; ++ gotgctl_data_t gotgctl = {.d32 = 0 }; ++ ++ gotgctl.d32 = dwc_read_reg32(&core_if->core_global_regs->gotgctl); ++ DWC_DEBUGPL(DBG_CIL, "gotgctl=%0x\n", gotgctl.d32); ++ DWC_DEBUGPL(DBG_CIL, "gotgctl.b.conidsts=%d\n", gotgctl.b.conidsts); ++ ++ /* B-Device connector (Device Mode) */ ++ if (gotgctl.b.conidsts) { ++ /* Wait for switch to device mode. */ ++ while (!dwc_otg_is_device_mode(core_if)) { ++ DWC_PRINTF("Waiting for Peripheral Mode, Mode=%s\n", ++ (dwc_otg_is_host_mode(core_if) ? "Host" : ++ "Peripheral")); ++ dwc_mdelay(100); ++ if (++count > 10000) ++ break; ++ } ++ DWC_ASSERT(++count < 10000, ++ "Connection id status change timed out"); ++ core_if->op_state = B_PERIPHERAL; ++ dwc_otg_core_init(core_if); ++ dwc_otg_enable_global_interrupts(core_if); ++ pcd_start(core_if); ++ } else { ++ /* A-Device connector (Host Mode) */ ++ while (!dwc_otg_is_host_mode(core_if)) { ++ DWC_PRINTF("Waiting for Host Mode, Mode=%s\n", ++ (dwc_otg_is_host_mode(core_if) ? "Host" : ++ "Peripheral")); ++ dwc_mdelay(100); ++ if (++count > 10000) ++ break; ++ } ++ DWC_ASSERT(++count < 10000, ++ "Connection id status change timed out"); ++ core_if->op_state = A_HOST; ++ /* ++ * Initialize the Core for Host mode. ++ */ ++ dwc_otg_core_init(core_if); ++ dwc_otg_enable_global_interrupts(core_if); ++ hcd_start(core_if); ++ } ++} ++ ++/** ++ * This function handles the Connector ID Status Change Interrupt. It ++ * reads the OTG Interrupt Register (GOTCTL) to determine whether this ++ * is a Device to Host Mode transition or a Host Mode to Device ++ * Transition. ++ * ++ * This only occurs when the cable is connected/removed from the PHY ++ * connector. ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ */ ++int32_t dwc_otg_handle_conn_id_status_change_intr(dwc_otg_core_if_t * core_if) ++{ ++ ++ /* ++ * Need to disable SOF interrupt immediately. If switching from device ++ * to host, the PCD interrupt handler won't handle the interrupt if ++ * host mode is already set. The HCD interrupt handler won't get ++ * called if the HCD state is HALT. This means that the interrupt does ++ * not get handled and Linux complains loudly. ++ */ ++ gintmsk_data_t gintmsk = {.d32 = 0 }; ++ gintsts_data_t gintsts = {.d32 = 0 }; ++ ++ gintmsk.b.sofintr = 1; ++ dwc_modify_reg32(&core_if->core_global_regs->gintmsk, gintmsk.d32, 0); ++ ++ DWC_DEBUGPL(DBG_CIL, ++ " ++Connector ID Status Change Interrupt++ (%s)\n", ++ (dwc_otg_is_host_mode(core_if) ? "Host" : "Device")); ++ ++ /* ++ * Need to schedule a work, as there are possible DELAY function calls ++ */ ++ DWC_WORKQ_SCHEDULE(core_if->wq_otg, w_conn_id_status_change, ++ core_if, "connection id status change"); ++ ++ /* Set flag and clear interrupt */ ++ gintsts.b.conidstschng = 1; ++ dwc_write_reg32(&core_if->core_global_regs->gintsts, gintsts.d32); ++ ++ return 1; ++} ++ ++/** ++ * This interrupt indicates that a device is initiating the Session ++ * Request Protocol to request the host to turn on bus power so a new ++ * session can begin. The handler responds by turning on bus power. If ++ * the DWC_otg controller is in low power mode, the handler brings the ++ * controller out of low power mode before turning on bus power. ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ */ ++int32_t dwc_otg_handle_session_req_intr(dwc_otg_core_if_t * core_if) ++{ ++ hprt0_data_t hprt0; ++ gintsts_data_t gintsts; ++ ++#ifndef DWC_HOST_ONLY ++ DWC_DEBUGPL(DBG_ANY, "++Session Request Interrupt++\n"); ++ ++ if (dwc_otg_is_device_mode(core_if)) { ++ DWC_PRINTF("SRP: Device mode\n"); ++ } else { ++ DWC_PRINTF("SRP: Host mode\n"); ++ ++ /* Turn on the port power bit. */ ++ hprt0.d32 = dwc_otg_read_hprt0(core_if); ++ hprt0.b.prtpwr = 1; ++ dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32); ++ ++ /* Start the Connection timer. So a message can be displayed ++ * if connect does not occur within 10 seconds. */ ++ hcd_session_start(core_if); ++ } ++#endif ++ ++ /* Clear interrupt */ ++ gintsts.d32 = 0; ++ gintsts.b.sessreqintr = 1; ++ dwc_write_reg32(&core_if->core_global_regs->gintsts, gintsts.d32); ++ ++ return 1; ++} ++ ++void w_wakeup_detected(void *p) ++{ ++ dwc_otg_core_if_t *core_if = (dwc_otg_core_if_t *) p; ++ /* ++ * Clear the Resume after 70ms. (Need 20 ms minimum. Use 70 ms ++ * so that OPT tests pass with all PHYs). ++ */ ++ hprt0_data_t hprt0 = {.d32 = 0 }; ++#if 0 ++ pcgcctl_data_t pcgcctl = {.d32 = 0 }; ++ /* Restart the Phy Clock */ ++ pcgcctl.b.stoppclk = 1; ++ dwc_modify_reg32(core_if->pcgcctl, pcgcctl.d32, 0); ++ dwc_udelay(10); ++#endif //0 ++ hprt0.d32 = dwc_otg_read_hprt0(core_if); ++ DWC_DEBUGPL(DBG_ANY, "Resume: HPRT0=%0x\n", hprt0.d32); ++// dwc_mdelay(70); ++ hprt0.b.prtres = 0; /* Resume */ ++ dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32); ++ DWC_DEBUGPL(DBG_ANY, "Clear Resume: HPRT0=%0x\n", ++ dwc_read_reg32(core_if->host_if->hprt0)); ++ ++ hcd_resume(core_if); ++ ++ /** Change to L0 state*/ ++ core_if->lx_state = DWC_OTG_L0; ++ ++} ++ ++/** ++ * This interrupt indicates that the DWC_otg controller has detected a ++ * resume or remote wakeup sequence. If the DWC_otg controller is in ++ * low power mode, the handler must brings the controller out of low ++ * power mode. The controller automatically begins resume ++ * signaling. The handler schedules a time to stop resume signaling. ++ */ ++int32_t dwc_otg_handle_wakeup_detected_intr(dwc_otg_core_if_t * core_if) ++{ ++ gintsts_data_t gintsts; ++ ++ DWC_DEBUGPL(DBG_ANY, ++ "++Resume and Remote Wakeup Detected Interrupt++\n"); ++ ++ DWC_PRINTF("%s lxstate = %d\n", __func__, core_if->lx_state); ++ ++ if (dwc_otg_is_device_mode(core_if)) { ++ dctl_data_t dctl = {.d32 = 0 }; ++ DWC_DEBUGPL(DBG_PCD, "DSTS=0x%0x\n", ++ dwc_read_reg32(&core_if->dev_if->dev_global_regs-> ++ dsts)); ++ if (core_if->lx_state == DWC_OTG_L2) { ++#ifdef PARTIAL_POWER_DOWN ++ if (core_if->hwcfg4.b.power_optimiz) { ++ pcgcctl_data_t power = {.d32 = 0 }; ++ ++ power.d32 = dwc_read_reg32(core_if->pcgcctl); ++ DWC_DEBUGPL(DBG_CIL, "PCGCCTL=%0x\n", ++ power.d32); ++ ++ power.b.stoppclk = 0; ++ dwc_write_reg32(core_if->pcgcctl, power.d32); ++ ++ power.b.pwrclmp = 0; ++ dwc_write_reg32(core_if->pcgcctl, power.d32); ++ ++ power.b.rstpdwnmodule = 0; ++ dwc_write_reg32(core_if->pcgcctl, power.d32); ++ } ++#endif ++ /* Clear the Remote Wakeup Signalling */ ++ dctl.b.rmtwkupsig = 1; ++ dwc_modify_reg32(&core_if->dev_if->dev_global_regs-> ++ dctl, dctl.d32, 0); ++ ++ if (core_if->pcd_cb && core_if->pcd_cb->resume_wakeup) { ++ core_if->pcd_cb->resume_wakeup(core_if->pcd_cb-> ++ p); ++ } ++ } else { ++ glpmcfg_data_t lpmcfg; ++ lpmcfg.d32 = ++ dwc_read_reg32(&core_if->core_global_regs->glpmcfg); ++ lpmcfg.b.hird_thres &= (~(1 << 4)); ++ dwc_write_reg32(&core_if->core_global_regs->glpmcfg, ++ lpmcfg.d32); ++ } ++ /** Change to L0 state*/ ++ core_if->lx_state = DWC_OTG_L0; ++ } else { ++ if (core_if->lx_state != DWC_OTG_L1) { ++ pcgcctl_data_t pcgcctl = {.d32 = 0 }; ++ ++ /* Restart the Phy Clock */ ++ pcgcctl.b.stoppclk = 1; ++ dwc_modify_reg32(core_if->pcgcctl, pcgcctl.d32, 0); ++ ++ DWC_TIMER_SCHEDULE(core_if->wkp_timer, 71); ++ } else { ++ /** Change to L0 state*/ ++ core_if->lx_state = DWC_OTG_L0; ++ } ++ } ++ ++ /* Clear interrupt */ ++ gintsts.d32 = 0; ++ gintsts.b.wkupintr = 1; ++ dwc_write_reg32(&core_if->core_global_regs->gintsts, gintsts.d32); ++ ++ return 1; ++} ++ ++/** ++ * This interrupt indicates that a device has been disconnected from ++ * the root port. ++ */ ++int32_t dwc_otg_handle_disconnect_intr(dwc_otg_core_if_t * core_if) ++{ ++ gintsts_data_t gintsts; ++ ++ DWC_DEBUGPL(DBG_ANY, "++Disconnect Detected Interrupt++ (%s) %s\n", ++ (dwc_otg_is_host_mode(core_if) ? "Host" : "Device"), ++ op_state_str(core_if)); ++ ++/** @todo Consolidate this if statement. */ ++#ifndef DWC_HOST_ONLY ++ if (core_if->op_state == B_HOST) { ++ /* If in device mode Disconnect and stop the HCD, then ++ * start the PCD. */ ++ hcd_disconnect(core_if); ++ pcd_start(core_if); ++ core_if->op_state = B_PERIPHERAL; ++ } else if (dwc_otg_is_device_mode(core_if)) { ++ gotgctl_data_t gotgctl = {.d32 = 0 }; ++ gotgctl.d32 = ++ dwc_read_reg32(&core_if->core_global_regs->gotgctl); ++ if (gotgctl.b.hstsethnpen == 1) { ++ /* Do nothing, if HNP in process the OTG ++ * interrupt "Host Negotiation Detected" ++ * interrupt will do the mode switch. ++ */ ++ } else if (gotgctl.b.devhnpen == 0) { ++ /* If in device mode Disconnect and stop the HCD, then ++ * start the PCD. */ ++ hcd_disconnect(core_if); ++ pcd_start(core_if); ++ core_if->op_state = B_PERIPHERAL; ++ } else { ++ DWC_DEBUGPL(DBG_ANY, "!a_peripheral && !devhnpen\n"); ++ } ++ } else { ++ if (core_if->op_state == A_HOST) { ++ /* A-Cable still connected but device disconnected. */ ++ hcd_disconnect(core_if); ++ } ++ } ++#endif ++ /* Change to L3(OFF) state */ ++ core_if->lx_state = DWC_OTG_L3; ++ ++ gintsts.d32 = 0; ++ gintsts.b.disconnect = 1; ++ dwc_write_reg32(&core_if->core_global_regs->gintsts, gintsts.d32); ++ return 1; ++} ++ ++/** ++ * This interrupt indicates that SUSPEND state has been detected on ++ * the USB. ++ * ++ * For HNP the USB Suspend interrupt signals the change from ++ * "a_peripheral" to "a_host". ++ * ++ * When power management is enabled the core will be put in low power ++ * mode. ++ */ ++int32_t dwc_otg_handle_usb_suspend_intr(dwc_otg_core_if_t * core_if) ++{ ++ dsts_data_t dsts; ++ gintsts_data_t gintsts; ++ ++ DWC_DEBUGPL(DBG_ANY, "USB SUSPEND\n"); ++ ++ if (dwc_otg_is_device_mode(core_if)) { ++ /* Check the Device status register to determine if the Suspend ++ * state is active. */ ++ dsts.d32 = ++ dwc_read_reg32(&core_if->dev_if->dev_global_regs->dsts); ++ DWC_DEBUGPL(DBG_PCD, "DSTS=0x%0x\n", dsts.d32); ++ DWC_DEBUGPL(DBG_PCD, "DSTS.Suspend Status=%d " ++ "HWCFG4.power Optimize=%d\n", ++ dsts.b.suspsts, core_if->hwcfg4.b.power_optimiz); ++ ++#ifdef PARTIAL_POWER_DOWN ++/** @todo Add a module parameter for power management. */ ++ ++ if (dsts.b.suspsts && core_if->hwcfg4.b.power_optimiz) { ++ pcgcctl_data_t power = {.d32 = 0 }; ++ DWC_DEBUGPL(DBG_CIL, "suspend\n"); ++ ++ power.b.pwrclmp = 1; ++ dwc_write_reg32(core_if->pcgcctl, power.d32); ++ ++ power.b.rstpdwnmodule = 1; ++ dwc_modify_reg32(core_if->pcgcctl, 0, power.d32); ++ ++ power.b.stoppclk = 1; ++ dwc_modify_reg32(core_if->pcgcctl, 0, power.d32); ++ ++ } else { ++ DWC_DEBUGPL(DBG_ANY, "disconnect?\n"); ++ } ++#endif ++ /* PCD callback for suspend. */ ++ pcd_suspend(core_if); ++ } else { ++ if (core_if->op_state == A_PERIPHERAL) { ++ DWC_DEBUGPL(DBG_ANY, "a_peripheral->a_host\n"); ++ /* Clear the a_peripheral flag, back to a_host. */ ++ pcd_stop(core_if); ++ hcd_start(core_if); ++ core_if->op_state = A_HOST; ++ } ++ } ++ ++ /* Change to L2(suspend) state */ ++ core_if->lx_state = DWC_OTG_L2; ++ ++ /* Clear interrupt */ ++ gintsts.d32 = 0; ++ gintsts.b.usbsuspend = 1; ++ dwc_write_reg32(&core_if->core_global_regs->gintsts, gintsts.d32); ++ ++ return 1; ++} ++ ++#ifdef CONFIG_USB_DWC_OTG_LPM ++/** ++ * This function hadles LPM transaction received interrupt. ++ */ ++static int32_t dwc_otg_handle_lpm_intr(dwc_otg_core_if_t * core_if) ++{ ++ glpmcfg_data_t lpmcfg; ++ gintsts_data_t gintsts; ++ ++ if (!core_if->core_params->lpm_enable) { ++ DWC_PRINTF("Unexpected LPM interrupt\n"); ++ } ++ ++ lpmcfg.d32 = dwc_read_reg32(&core_if->core_global_regs->glpmcfg); ++ DWC_PRINTF("LPM config register = 0x%08x\n", lpmcfg.d32); ++ ++ if (dwc_otg_is_host_mode(core_if)) { ++ hcd_sleep(core_if); ++ } else { ++ lpmcfg.b.hird_thres |= (1 << 4); ++ dwc_write_reg32(&core_if->core_global_regs->glpmcfg, ++ lpmcfg.d32); ++ } ++ ++ /* Examine prt_sleep_sts after TL1TokenTetry period max (10 us) */ ++ dwc_udelay(10); ++ lpmcfg.d32 = dwc_read_reg32(&core_if->core_global_regs->glpmcfg); ++ if (lpmcfg.b.prt_sleep_sts) { ++ /* Save the current state */ ++ core_if->lx_state = DWC_OTG_L1; ++ } ++ ++ /* Clear interrupt */ ++ gintsts.d32 = 0; ++ gintsts.b.lpmtranrcvd = 1; ++ dwc_write_reg32(&core_if->core_global_regs->gintsts, gintsts.d32); ++ return 1; ++} ++#endif /* CONFIG_USB_DWC_OTG_LPM */ ++ ++/** ++ * This function returns the Core Interrupt register. ++ */ ++static inline uint32_t dwc_otg_read_common_intr(dwc_otg_core_if_t * core_if) ++{ ++ gintsts_data_t gintsts; ++ gintmsk_data_t gintmsk; ++ gintmsk_data_t gintmsk_common = {.d32 = 0 }; ++ gintmsk_common.b.wkupintr = 1; ++ gintmsk_common.b.sessreqintr = 1; ++ gintmsk_common.b.conidstschng = 1; ++ gintmsk_common.b.otgintr = 1; ++ gintmsk_common.b.modemismatch = 1; ++ gintmsk_common.b.disconnect = 1; ++ gintmsk_common.b.usbsuspend = 1; ++#ifdef CONFIG_USB_DWC_OTG_LPM ++ gintmsk_common.b.lpmtranrcvd = 1; ++#endif ++ /** @todo: The port interrupt occurs while in device ++ * mode. Added code to CIL to clear the interrupt for now! ++ */ ++ gintmsk_common.b.portintr = 1; ++ ++ gintsts.d32 = dwc_read_reg32(&core_if->core_global_regs->gintsts); ++ gintmsk.d32 = dwc_read_reg32(&core_if->core_global_regs->gintmsk); ++#ifdef DEBUG ++ /* if any common interrupts set */ ++ if (gintsts.d32 & gintmsk_common.d32) { ++ DWC_DEBUGPL(DBG_ANY, "gintsts=%08x gintmsk=%08x\n", ++ gintsts.d32, gintmsk.d32); ++ } ++#endif ++ ++ return ((gintsts.d32 & gintmsk.d32) & gintmsk_common.d32); ++ ++} ++ ++/** ++ * Common interrupt handler. ++ * ++ * The common interrupts are those that occur in both Host and Device mode. ++ * This handler handles the following interrupts: ++ * - Mode Mismatch Interrupt ++ * - Disconnect Interrupt ++ * - OTG Interrupt ++ * - Connector ID Status Change Interrupt ++ * - Session Request Interrupt. ++ * - Resume / Remote Wakeup Detected Interrupt. ++ * - LPM Transaction Received Interrutp ++ * ++ */ ++int32_t dwc_otg_handle_common_intr(dwc_otg_core_if_t * core_if) ++{ ++ int retval = 0; ++ gintsts_data_t gintsts; ++ ++ gintsts.d32 = dwc_otg_read_common_intr(core_if); ++ ++ if (gintsts.b.modemismatch) { ++ retval |= dwc_otg_handle_mode_mismatch_intr(core_if); ++ } ++ if (gintsts.b.otgintr) { ++ retval |= dwc_otg_handle_otg_intr(core_if); ++ } ++ if (gintsts.b.conidstschng) { ++ retval |= dwc_otg_handle_conn_id_status_change_intr(core_if); ++ } ++ if (gintsts.b.disconnect) { ++ retval |= dwc_otg_handle_disconnect_intr(core_if); ++ } ++ if (gintsts.b.sessreqintr) { ++ retval |= dwc_otg_handle_session_req_intr(core_if); ++ } ++ if (gintsts.b.wkupintr) { ++ retval |= dwc_otg_handle_wakeup_detected_intr(core_if); ++ } ++ if (gintsts.b.usbsuspend) { ++ retval |= dwc_otg_handle_usb_suspend_intr(core_if); ++ } ++#ifdef CONFIG_USB_DWC_OTG_LPM ++ if (gintsts.b.lpmtranrcvd) { ++ retval |= dwc_otg_handle_lpm_intr(core_if); ++ } ++#endif ++ ++ if (gintsts.b.portintr && dwc_otg_is_device_mode(core_if)) { ++ /* The port interrupt occurs while in device mode with HPRT0 ++ * Port Enable/Disable. ++ */ ++ gintsts.d32 = 0; ++ gintsts.b.portintr = 1; ++ dwc_write_reg32(&core_if->core_global_regs->gintsts, ++ gintsts.d32); ++ retval |= 1; ++ ++ } ++ return retval; ++} +Index: linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_core_if.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_core_if.h 2013-07-26 19:31:23.000000000 +0000 +@@ -0,0 +1,641 @@ ++/* ========================================================================== ++ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_core_if.h $ ++ * $Revision: #4 $ ++ * $Date: 2008/12/18 $ ++ * $Change: 1155299 $ ++ * ++ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, ++ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless ++ * otherwise expressly agreed to in writing between Synopsys and you. ++ * ++ * The Software IS NOT an item of Licensed Software or Licensed Product under ++ * any End User Software License Agreement or Agreement for Licensed Product ++ * with Synopsys or any supplement thereto. You are permitted to use and ++ * redistribute this Software in source and binary forms, with or without ++ * modification, provided that redistributions of source code must retain this ++ * notice. You may not view, use, disclose, copy or distribute this file or ++ * any information contained herein except pursuant to this license grant from ++ * Synopsys. If you do not agree with this notice, including the disclaimer ++ * below, then you are not authorized to use the Software. ++ * ++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, ++ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR ++ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER ++ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY ++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH ++ * DAMAGE. ++ * ========================================================================== */ ++#if !defined(__DWC_CORE_IF_H__) ++#define __DWC_CORE_IF_H__ ++ ++#include "dwc_os.h" ++ ++/** @file ++ * This file defines DWC_OTG Core API ++ */ ++ ++struct dwc_otg_core_if; ++typedef struct dwc_otg_core_if dwc_otg_core_if_t; ++ ++/** Maximum number of Periodic FIFOs */ ++#define MAX_PERIO_FIFOS 15 ++/** Maximum number of Periodic FIFOs */ ++#define MAX_TX_FIFOS 15 ++ ++/** Maximum number of Endpoints/HostChannels */ ++#define MAX_EPS_CHANNELS 16 ++ ++extern dwc_otg_core_if_t *dwc_otg_cil_init(const uint32_t * _reg_base_addr); ++extern void dwc_otg_core_init(dwc_otg_core_if_t * _core_if); ++extern void dwc_otg_cil_remove(dwc_otg_core_if_t * _core_if); ++ ++extern void dwc_otg_enable_global_interrupts(dwc_otg_core_if_t * _core_if); ++extern void dwc_otg_disable_global_interrupts(dwc_otg_core_if_t * _core_if); ++ ++extern uint8_t dwc_otg_is_device_mode(dwc_otg_core_if_t * _core_if); ++extern uint8_t dwc_otg_is_host_mode(dwc_otg_core_if_t * _core_if); ++ ++extern uint8_t dwc_otg_is_dma_enable(dwc_otg_core_if_t * core_if); ++ ++/** This function should be called on every hardware interrupt. */ ++extern int32_t dwc_otg_handle_common_intr(dwc_otg_core_if_t * _core_if); ++ ++/** @name OTG Core Parameters */ ++/** @{ */ ++ ++/** ++ * Specifies the OTG capabilities. The driver will automatically ++ * detect the value for this parameter if none is specified. ++ * 0 - HNP and SRP capable (default) ++ * 1 - SRP Only capable ++ * 2 - No HNP/SRP capable ++ */ ++extern int dwc_otg_set_param_otg_cap(dwc_otg_core_if_t * core_if, int32_t val); ++extern int32_t dwc_otg_get_param_otg_cap(dwc_otg_core_if_t * core_if); ++#define DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE 0 ++#define DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE 1 ++#define DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE 2 ++#define dwc_param_otg_cap_default DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE ++ ++extern int dwc_otg_set_param_opt(dwc_otg_core_if_t * core_if, int32_t val); ++extern int32_t dwc_otg_get_param_opt(dwc_otg_core_if_t * core_if); ++#define dwc_param_opt_default 1 ++ ++/** ++ * Specifies whether to use slave or DMA mode for accessing the data ++ * FIFOs. The driver will automatically detect the value for this ++ * parameter if none is specified. ++ * 0 - Slave ++ * 1 - DMA (default, if available) ++ */ ++extern int dwc_otg_set_param_dma_enable(dwc_otg_core_if_t * core_if, ++ int32_t val); ++extern int32_t dwc_otg_get_param_dma_enable(dwc_otg_core_if_t * core_if); ++#define dwc_param_dma_enable_default 1 ++ ++/** ++ * When DMA mode is enabled specifies whether to use ++ * address DMA or DMA Descritor mode for accessing the data ++ * FIFOs in device mode. The driver will automatically detect ++ * the value for this parameter if none is specified. ++ * 0 - address DMA ++ * 1 - DMA Descriptor(default, if available) ++ */ ++extern int dwc_otg_set_param_dma_desc_enable(dwc_otg_core_if_t * core_if, ++ int32_t val); ++extern int32_t dwc_otg_get_param_dma_desc_enable(dwc_otg_core_if_t * core_if); ++//#define dwc_param_dma_desc_enable_default 1 ++#define dwc_param_dma_desc_enable_default 0 // Broadcom BCM2708 ++ ++/** The DMA Burst size (applicable only for External DMA ++ * Mode). 1, 4, 8 16, 32, 64, 128, 256 (default 32) ++ */ ++extern int dwc_otg_set_param_dma_burst_size(dwc_otg_core_if_t * core_if, ++ int32_t val); ++extern int32_t dwc_otg_get_param_dma_burst_size(dwc_otg_core_if_t * core_if); ++#define dwc_param_dma_burst_size_default 32 ++ ++/** ++ * Specifies the maximum speed of operation in host and device mode. ++ * The actual speed depends on the speed of the attached device and ++ * the value of phy_type. The actual speed depends on the speed of the ++ * attached device. ++ * 0 - High Speed (default) ++ * 1 - Full Speed ++ */ ++extern int dwc_otg_set_param_speed(dwc_otg_core_if_t * core_if, int32_t val); ++extern int32_t dwc_otg_get_param_speed(dwc_otg_core_if_t * core_if); ++#define dwc_param_speed_default 0 ++#define DWC_SPEED_PARAM_HIGH 0 ++#define DWC_SPEED_PARAM_FULL 1 ++ ++/** Specifies whether low power mode is supported when attached ++ * to a Full Speed or Low Speed device in host mode. ++ * 0 - Don't support low power mode (default) ++ * 1 - Support low power mode ++ */ ++extern int dwc_otg_set_param_host_support_fs_ls_low_power(dwc_otg_core_if_t * ++ core_if, int32_t val); ++extern int32_t dwc_otg_get_param_host_support_fs_ls_low_power(dwc_otg_core_if_t ++ * core_if); ++#define dwc_param_host_support_fs_ls_low_power_default 0 ++ ++/** Specifies the PHY clock rate in low power mode when connected to a ++ * Low Speed device in host mode. This parameter is applicable only if ++ * HOST_SUPPORT_FS_LS_LOW_POWER is enabled. If PHY_TYPE is set to FS ++ * then defaults to 6 MHZ otherwise 48 MHZ. ++ * ++ * 0 - 48 MHz ++ * 1 - 6 MHz ++ */ ++extern int dwc_otg_set_param_host_ls_low_power_phy_clk(dwc_otg_core_if_t * ++ core_if, int32_t val); ++extern int32_t dwc_otg_get_param_host_ls_low_power_phy_clk(dwc_otg_core_if_t * ++ core_if); ++#define dwc_param_host_ls_low_power_phy_clk_default 0 ++#define DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ 0 ++#define DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ 1 ++ ++/** ++ * 0 - Use cC FIFO size parameters ++ * 1 - Allow dynamic FIFO sizing (default) ++ */ ++extern int dwc_otg_set_param_enable_dynamic_fifo(dwc_otg_core_if_t * core_if, ++ int32_t val); ++extern int32_t dwc_otg_get_param_enable_dynamic_fifo(dwc_otg_core_if_t * ++ core_if); ++#define dwc_param_enable_dynamic_fifo_default 1 ++ ++/** Total number of 4-byte words in the data FIFO memory. This ++ * memory includes the Rx FIFO, non-periodic Tx FIFO, and periodic ++ * Tx FIFOs. ++ * 32 to 32768 (default 8192) ++ * Note: The total FIFO memory depth in the FPGA configuration is 8192. ++ */ ++extern int dwc_otg_set_param_data_fifo_size(dwc_otg_core_if_t * core_if, ++ int32_t val); ++extern int32_t dwc_otg_get_param_data_fifo_size(dwc_otg_core_if_t * core_if); ++//#define dwc_param_data_fifo_size_default 8192 ++#define dwc_param_data_fifo_size_default 0xFF0 // Broadcom BCM2708 ++ ++/** Number of 4-byte words in the Rx FIFO in device mode when dynamic ++ * FIFO sizing is enabled. ++ * 16 to 32768 (default 1064) ++ */ ++extern int dwc_otg_set_param_dev_rx_fifo_size(dwc_otg_core_if_t * core_if, ++ int32_t val); ++extern int32_t dwc_otg_get_param_dev_rx_fifo_size(dwc_otg_core_if_t * core_if); ++#define dwc_param_dev_rx_fifo_size_default 1064 ++ ++/** Number of 4-byte words in the non-periodic Tx FIFO in device mode ++ * when dynamic FIFO sizing is enabled. ++ * 16 to 32768 (default 1024) ++ */ ++extern int dwc_otg_set_param_dev_nperio_tx_fifo_size(dwc_otg_core_if_t * ++ core_if, int32_t val); ++extern int32_t dwc_otg_get_param_dev_nperio_tx_fifo_size(dwc_otg_core_if_t * ++ core_if); ++#define dwc_param_dev_nperio_tx_fifo_size_default 1024 ++ ++/** Number of 4-byte words in each of the periodic Tx FIFOs in device ++ * mode when dynamic FIFO sizing is enabled. ++ * 4 to 768 (default 256) ++ */ ++extern int dwc_otg_set_param_dev_perio_tx_fifo_size(dwc_otg_core_if_t * core_if, ++ int32_t val, int fifo_num); ++extern int32_t dwc_otg_get_param_dev_perio_tx_fifo_size(dwc_otg_core_if_t * ++ core_if, int fifo_num); ++#define dwc_param_dev_perio_tx_fifo_size_default 256 ++ ++/** Number of 4-byte words in the Rx FIFO in host mode when dynamic ++ * FIFO sizing is enabled. ++ * 16 to 32768 (default 1024) ++ */ ++extern int dwc_otg_set_param_host_rx_fifo_size(dwc_otg_core_if_t * core_if, ++ int32_t val); ++extern int32_t dwc_otg_get_param_host_rx_fifo_size(dwc_otg_core_if_t * core_if); ++//#define dwc_param_host_rx_fifo_size_default 1024 ++#define dwc_param_host_rx_fifo_size_default 774 // Broadcom BCM2708 ++ ++/** Number of 4-byte words in the non-periodic Tx FIFO in host mode ++ * when Dynamic FIFO sizing is enabled in the core. ++ * 16 to 32768 (default 1024) ++ */ ++extern int dwc_otg_set_param_host_nperio_tx_fifo_size(dwc_otg_core_if_t * ++ core_if, int32_t val); ++extern int32_t dwc_otg_get_param_host_nperio_tx_fifo_size(dwc_otg_core_if_t * ++ core_if); ++//#define dwc_param_host_nperio_tx_fifo_size_default 1024 ++#define dwc_param_host_nperio_tx_fifo_size_default 0x100 // Broadcom BCM2708 ++ ++/** Number of 4-byte words in the host periodic Tx FIFO when dynamic ++ * FIFO sizing is enabled. ++ * 16 to 32768 (default 1024) ++ */ ++extern int dwc_otg_set_param_host_perio_tx_fifo_size(dwc_otg_core_if_t * ++ core_if, int32_t val); ++extern int32_t dwc_otg_get_param_host_perio_tx_fifo_size(dwc_otg_core_if_t * ++ core_if); ++//#define dwc_param_host_perio_tx_fifo_size_default 1024 ++#define dwc_param_host_perio_tx_fifo_size_default 0x200 // Broadcom BCM2708 ++ ++/** The maximum transfer size supported in bytes. ++ * 2047 to 65,535 (default 65,535) ++ */ ++extern int dwc_otg_set_param_max_transfer_size(dwc_otg_core_if_t * core_if, ++ int32_t val); ++extern int32_t dwc_otg_get_param_max_transfer_size(dwc_otg_core_if_t * core_if); ++#define dwc_param_max_transfer_size_default 65535 ++ ++/** The maximum number of packets in a transfer. ++ * 15 to 511 (default 511) ++ */ ++extern int dwc_otg_set_param_max_packet_count(dwc_otg_core_if_t * core_if, ++ int32_t val); ++extern int32_t dwc_otg_get_param_max_packet_count(dwc_otg_core_if_t * core_if); ++#define dwc_param_max_packet_count_default 511 ++ ++/** The number of host channel registers to use. ++ * 1 to 16 (default 12) ++ * Note: The FPGA configuration supports a maximum of 12 host channels. ++ */ ++extern int dwc_otg_set_param_host_channels(dwc_otg_core_if_t * core_if, ++ int32_t val); ++extern int32_t dwc_otg_get_param_host_channels(dwc_otg_core_if_t * core_if); ++#define dwc_param_host_channels_default 12 ++ ++/** The number of endpoints in addition to EP0 available for device ++ * mode operations. ++ * 1 to 15 (default 6 IN and OUT) ++ * Note: The FPGA configuration supports a maximum of 6 IN and OUT ++ * endpoints in addition to EP0. ++ */ ++extern int dwc_otg_set_param_dev_endpoints(dwc_otg_core_if_t * core_if, ++ int32_t val); ++extern int32_t dwc_otg_get_param_dev_endpoints(dwc_otg_core_if_t * core_if); ++#define dwc_param_dev_endpoints_default 6 ++ ++/** ++ * Specifies the type of PHY interface to use. By default, the driver ++ * will automatically detect the phy_type. ++ * ++ * 0 - Full Speed PHY ++ * 1 - UTMI+ (default) ++ * 2 - ULPI ++ */ ++extern int dwc_otg_set_param_phy_type(dwc_otg_core_if_t * core_if, int32_t val); ++extern int32_t dwc_otg_get_param_phy_type(dwc_otg_core_if_t * core_if); ++#define DWC_PHY_TYPE_PARAM_FS 0 ++#define DWC_PHY_TYPE_PARAM_UTMI 1 ++#define DWC_PHY_TYPE_PARAM_ULPI 2 ++#define dwc_param_phy_type_default DWC_PHY_TYPE_PARAM_UTMI ++ ++/** ++ * Specifies the UTMI+ Data Width. This parameter is ++ * applicable for a PHY_TYPE of UTMI+ or ULPI. (For a ULPI ++ * PHY_TYPE, this parameter indicates the data width between ++ * the MAC and the ULPI Wrapper.) Also, this parameter is ++ * applicable only if the OTG_HSPHY_WIDTH cC parameter was set ++ * to "8 and 16 bits", meaning that the core has been ++ * configured to work at either data path width. ++ * ++ * 8 or 16 bits (default 16) ++ */ ++extern int dwc_otg_set_param_phy_utmi_width(dwc_otg_core_if_t * core_if, ++ int32_t val); ++extern int32_t dwc_otg_get_param_phy_utmi_width(dwc_otg_core_if_t * core_if); ++//#define dwc_param_phy_utmi_width_default 16 ++#define dwc_param_phy_utmi_width_default 8 // Broadcom BCM2708 ++ ++/** ++ * Specifies whether the ULPI operates at double or single ++ * data rate. This parameter is only applicable if PHY_TYPE is ++ * ULPI. ++ * ++ * 0 - single data rate ULPI interface with 8 bit wide data ++ * bus (default) ++ * 1 - double data rate ULPI interface with 4 bit wide data ++ * bus ++ */ ++extern int dwc_otg_set_param_phy_ulpi_ddr(dwc_otg_core_if_t * core_if, ++ int32_t val); ++extern int32_t dwc_otg_get_param_phy_ulpi_ddr(dwc_otg_core_if_t * core_if); ++#define dwc_param_phy_ulpi_ddr_default 0 ++ ++/** ++ * Specifies whether to use the internal or external supply to ++ * drive the vbus with a ULPI phy. ++ */ ++extern int dwc_otg_set_param_phy_ulpi_ext_vbus(dwc_otg_core_if_t * core_if, ++ int32_t val); ++extern int32_t dwc_otg_get_param_phy_ulpi_ext_vbus(dwc_otg_core_if_t * core_if); ++#define DWC_PHY_ULPI_INTERNAL_VBUS 0 ++#define DWC_PHY_ULPI_EXTERNAL_VBUS 1 ++#define dwc_param_phy_ulpi_ext_vbus_default DWC_PHY_ULPI_INTERNAL_VBUS ++ ++/** ++ * Specifies whether to use the I2Cinterface for full speed PHY. This ++ * parameter is only applicable if PHY_TYPE is FS. ++ * 0 - No (default) ++ * 1 - Yes ++ */ ++extern int dwc_otg_set_param_i2c_enable(dwc_otg_core_if_t * core_if, ++ int32_t val); ++extern int32_t dwc_otg_get_param_i2c_enable(dwc_otg_core_if_t * core_if); ++#define dwc_param_i2c_enable_default 0 ++ ++extern int dwc_otg_set_param_ulpi_fs_ls(dwc_otg_core_if_t * core_if, ++ int32_t val); ++extern int32_t dwc_otg_get_param_ulpi_fs_ls(dwc_otg_core_if_t * core_if); ++#define dwc_param_ulpi_fs_ls_default 0 ++ ++extern int dwc_otg_set_param_ts_dline(dwc_otg_core_if_t * core_if, int32_t val); ++extern int32_t dwc_otg_get_param_ts_dline(dwc_otg_core_if_t * core_if); ++#define dwc_param_ts_dline_default 0 ++ ++/** ++ * Specifies whether dedicated transmit FIFOs are ++ * enabled for non periodic IN endpoints in device mode ++ * 0 - No ++ * 1 - Yes ++ */ ++extern int dwc_otg_set_param_en_multiple_tx_fifo(dwc_otg_core_if_t * core_if, ++ int32_t val); ++extern int32_t dwc_otg_get_param_en_multiple_tx_fifo(dwc_otg_core_if_t * ++ core_if); ++#define dwc_param_en_multiple_tx_fifo_default 1 ++ ++/** Number of 4-byte words in each of the Tx FIFOs in device ++ * mode when dynamic FIFO sizing is enabled. ++ * 4 to 768 (default 256) ++ */ ++extern int dwc_otg_set_param_dev_tx_fifo_size(dwc_otg_core_if_t * core_if, ++ int fifo_num, int32_t val); ++extern int32_t dwc_otg_get_param_dev_tx_fifo_size(dwc_otg_core_if_t * core_if, ++ int fifo_num); ++#define dwc_param_dev_tx_fifo_size_default 256 ++ ++/** Thresholding enable flag- ++ * bit 0 - enable non-ISO Tx thresholding ++ * bit 1 - enable ISO Tx thresholding ++ * bit 2 - enable Rx thresholding ++ */ ++extern int dwc_otg_set_param_thr_ctl(dwc_otg_core_if_t * core_if, int32_t val); ++extern int32_t dwc_otg_get_thr_ctl(dwc_otg_core_if_t * core_if, int fifo_num); ++#define dwc_param_thr_ctl_default 0 ++ ++/** Thresholding length for Tx ++ * FIFOs in 32 bit DWORDs ++ */ ++extern int dwc_otg_set_param_tx_thr_length(dwc_otg_core_if_t * core_if, ++ int32_t val); ++extern int32_t dwc_otg_get_tx_thr_length(dwc_otg_core_if_t * core_if); ++#define dwc_param_tx_thr_length_default 64 ++ ++/** Thresholding length for Rx ++ * FIFOs in 32 bit DWORDs ++ */ ++extern int dwc_otg_set_param_rx_thr_length(dwc_otg_core_if_t * core_if, ++ int32_t val); ++extern int32_t dwc_otg_get_rx_thr_length(dwc_otg_core_if_t * core_if); ++#define dwc_param_rx_thr_length_default 64 ++ ++/** ++ * Specifies whether LPM (Link Power Management) support is enabled ++ */ ++extern int dwc_otg_set_param_lpm_enable(dwc_otg_core_if_t * core_if, ++ int32_t val); ++extern int32_t dwc_otg_get_param_lpm_enable(dwc_otg_core_if_t * core_if); ++#define dwc_param_lpm_enable_default 1 ++ ++/** ++ * Specifies whether PTI enhancement is enabled ++ */ ++extern int dwc_otg_set_param_pti_enable(dwc_otg_core_if_t * core_if, ++ int32_t val); ++extern int32_t dwc_otg_get_param_pti_enable(dwc_otg_core_if_t * core_if); ++#define dwc_param_pti_enable_default 0 ++ ++/** ++ * Specifies whether MPI enhancement is enabled ++ */ ++extern int dwc_otg_set_param_mpi_enable(dwc_otg_core_if_t * core_if, ++ int32_t val); ++extern int32_t dwc_otg_get_param_mpi_enable(dwc_otg_core_if_t * core_if); ++#define dwc_param_mpi_enable_default 0 ++ ++/** ++ * Specifies whether IC_USB capability is enabled ++ */ ++extern int dwc_otg_set_param_ic_usb_cap(dwc_otg_core_if_t * core_if, ++ int32_t val); ++extern int32_t dwc_otg_get_param_ic_usb_cap(dwc_otg_core_if_t * core_if); ++#define dwc_param_ic_usb_cap_default 0 ++ ++extern int dwc_otg_set_param_ahb_thr_ratio(dwc_otg_core_if_t * core_if, int32_t val); ++extern int32_t dwc_otg_get_param_ahb_thr_ratio(dwc_otg_core_if_t * core_if); ++#define dwc_param_ahb_thr_ratio_default 0 ++ ++/** @} */ ++ ++/** @name Access to registers and bit-fields */ ++ ++/** ++ * Dump core registers and SPRAM ++ */ ++extern void dwc_otg_dump_dev_registers(dwc_otg_core_if_t * _core_if); ++extern void dwc_otg_dump_spram(dwc_otg_core_if_t * _core_if); ++extern void dwc_otg_dump_host_registers(dwc_otg_core_if_t * _core_if); ++extern void dwc_otg_dump_global_registers(dwc_otg_core_if_t * _core_if); ++ ++/** ++ * Get host negotiation status. ++ */ ++extern uint32_t dwc_otg_get_hnpstatus(dwc_otg_core_if_t * core_if); ++ ++/** ++ * Get srp status ++ */ ++extern uint32_t dwc_otg_get_srpstatus(dwc_otg_core_if_t * core_if); ++ ++/** ++ * Set hnpreq bit in the GOTGCTL register. ++ */ ++extern void dwc_otg_set_hnpreq(dwc_otg_core_if_t * core_if, uint32_t val); ++ ++/** ++ * Get Content of SNPSID register. ++ */ ++extern uint32_t dwc_otg_get_gsnpsid(dwc_otg_core_if_t * core_if); ++ ++/** ++ * Get current mode. ++ * Returns 0 if in device mode, and 1 if in host mode. ++ */ ++extern uint32_t dwc_otg_get_mode(dwc_otg_core_if_t * core_if); ++ ++/** ++ * Get value of hnpcapable field in the GUSBCFG register ++ */ ++extern uint32_t dwc_otg_get_hnpcapable(dwc_otg_core_if_t * core_if); ++/** ++ * Set value of hnpcapable field in the GUSBCFG register ++ */ ++extern void dwc_otg_set_hnpcapable(dwc_otg_core_if_t * core_if, uint32_t val); ++ ++/** ++ * Get value of srpcapable field in the GUSBCFG register ++ */ ++extern uint32_t dwc_otg_get_srpcapable(dwc_otg_core_if_t * core_if); ++/** ++ * Set value of srpcapable field in the GUSBCFG register ++ */ ++extern void dwc_otg_set_srpcapable(dwc_otg_core_if_t * core_if, uint32_t val); ++ ++/** ++ * Get value of devspeed field in the DCFG register ++ */ ++extern uint32_t dwc_otg_get_devspeed(dwc_otg_core_if_t * core_if); ++/** ++ * Set value of devspeed field in the DCFG register ++ */ ++extern void dwc_otg_set_devspeed(dwc_otg_core_if_t * core_if, uint32_t val); ++ ++/** ++ * Get the value of busconnected field from the HPRT0 register ++ */ ++extern uint32_t dwc_otg_get_busconnected(dwc_otg_core_if_t * core_if); ++ ++/** ++ * Gets the device enumeration Speed. ++ */ ++extern uint32_t dwc_otg_get_enumspeed(dwc_otg_core_if_t * core_if); ++ ++/** ++ * Get value of prtpwr field from the HPRT0 register ++ */ ++extern uint32_t dwc_otg_get_prtpower(dwc_otg_core_if_t * core_if); ++/** ++ * Set value of prtpwr field from the HPRT0 register ++ */ ++extern void dwc_otg_set_prtpower(dwc_otg_core_if_t * core_if, uint32_t val); ++ ++/** ++ * Get value of prtsusp field from the HPRT0 regsiter ++ */ ++extern uint32_t dwc_otg_get_prtsuspend(dwc_otg_core_if_t * core_if); ++/** ++ * Set value of prtpwr field from the HPRT0 register ++ */ ++extern void dwc_otg_set_prtsuspend(dwc_otg_core_if_t * core_if, uint32_t val); ++ ++/** ++ * Set value of prtres field from the HPRT0 register ++ *FIXME Remove? ++ */ ++extern void dwc_otg_set_prtresume(dwc_otg_core_if_t * core_if, uint32_t val); ++ ++/** ++ * Get value of rmtwkupsig bit in DCTL register ++ */ ++extern uint32_t dwc_otg_get_remotewakesig(dwc_otg_core_if_t * core_if); ++ ++/** ++ * Get value of prt_sleep_sts field from the GLPMCFG register ++ */ ++extern uint32_t dwc_otg_get_lpm_portsleepstatus(dwc_otg_core_if_t * core_if); ++ ++/** ++ * Get value of rem_wkup_en field from the GLPMCFG register ++ */ ++extern uint32_t dwc_otg_get_lpm_remotewakeenabled(dwc_otg_core_if_t * core_if); ++ ++/** ++ * Get value of appl_resp field from the GLPMCFG register ++ */ ++extern uint32_t dwc_otg_get_lpmresponse(dwc_otg_core_if_t * core_if); ++/** ++ * Set value of appl_resp field from the GLPMCFG register ++ */ ++extern void dwc_otg_set_lpmresponse(dwc_otg_core_if_t * core_if, uint32_t val); ++ ++/** ++ * Get value of hsic_connect field from the GLPMCFG register ++ */ ++extern uint32_t dwc_otg_get_hsic_connect(dwc_otg_core_if_t * core_if); ++/** ++ * Set value of hsic_connect field from the GLPMCFG register ++ */ ++extern void dwc_otg_set_hsic_connect(dwc_otg_core_if_t * core_if, uint32_t val); ++ ++/** ++ * Get value of inv_sel_hsic field from the GLPMCFG register. ++ */ ++extern uint32_t dwc_otg_get_inv_sel_hsic(dwc_otg_core_if_t * core_if); ++/** ++ * Set value of inv_sel_hsic field from the GLPMFG register. ++ */ ++extern void dwc_otg_set_inv_sel_hsic(dwc_otg_core_if_t * core_if, uint32_t val); ++ ++/* ++ * Some functions for accessing registers ++ */ ++ ++/** ++ * GOTGCTL register ++ */ ++extern uint32_t dwc_otg_get_gotgctl(dwc_otg_core_if_t * core_if); ++extern void dwc_otg_set_gotgctl(dwc_otg_core_if_t * core_if, uint32_t val); ++ ++/** ++ * GUSBCFG register ++ */ ++extern uint32_t dwc_otg_get_gusbcfg(dwc_otg_core_if_t * core_if); ++extern void dwc_otg_set_gusbcfg(dwc_otg_core_if_t * core_if, uint32_t val); ++ ++/** ++ * GRXFSIZ register ++ */ ++extern uint32_t dwc_otg_get_grxfsiz(dwc_otg_core_if_t * core_if); ++extern void dwc_otg_set_grxfsiz(dwc_otg_core_if_t * core_if, uint32_t val); ++ ++/** ++ * GNPTXFSIZ register ++ */ ++extern uint32_t dwc_otg_get_gnptxfsiz(dwc_otg_core_if_t * core_if); ++extern void dwc_otg_set_gnptxfsiz(dwc_otg_core_if_t * core_if, uint32_t val); ++ ++extern uint32_t dwc_otg_get_gpvndctl(dwc_otg_core_if_t * core_if); ++extern void dwc_otg_set_gpvndctl(dwc_otg_core_if_t * core_if, uint32_t val); ++ ++/** ++ * GGPIO register ++ */ ++extern uint32_t dwc_otg_get_ggpio(dwc_otg_core_if_t * core_if); ++extern void dwc_otg_set_ggpio(dwc_otg_core_if_t * core_if, uint32_t val); ++ ++/** ++ * GUID register ++ */ ++extern uint32_t dwc_otg_get_guid(dwc_otg_core_if_t * core_if); ++extern void dwc_otg_set_guid(dwc_otg_core_if_t * core_if, uint32_t val); ++ ++/** ++ * HPRT0 register ++ */ ++extern uint32_t dwc_otg_get_hprt0(dwc_otg_core_if_t * core_if); ++extern void dwc_otg_set_hprt0(dwc_otg_core_if_t * core_if, uint32_t val); ++ ++/** ++ * GHPTXFSIZE ++ */ ++extern uint32_t dwc_otg_get_hptxfsiz(dwc_otg_core_if_t * core_if); ++ ++/** @} */ ++ ++#endif /* __DWC_CORE_IF_H__ */ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_dbg.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_dbg.h 2013-07-26 19:31:23.000000000 +0000 +@@ -0,0 +1,113 @@ ++/* ========================================================================== ++ * ++ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, ++ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless ++ * otherwise expressly agreed to in writing between Synopsys and you. ++ * ++ * The Software IS NOT an item of Licensed Software or Licensed Product under ++ * any End User Software License Agreement or Agreement for Licensed Product ++ * with Synopsys or any supplement thereto. You are permitted to use and ++ * redistribute this Software in source and binary forms, with or without ++ * modification, provided that redistributions of source code must retain this ++ * notice. You may not view, use, disclose, copy or distribute this file or ++ * any information contained herein except pursuant to this license grant from ++ * Synopsys. If you do not agree with this notice, including the disclaimer ++ * below, then you are not authorized to use the Software. ++ * ++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, ++ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR ++ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER ++ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY ++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH ++ * DAMAGE. ++ * ========================================================================== */ ++ ++#ifndef __DWC_OTG_DBG_H__ ++#define __DWC_OTG_DBG_H__ ++ ++/** @file ++ * This file defines debug levels. ++ * Debugging support vanishes in non-debug builds. ++ */ ++ ++/** ++ * The Debug Level bit-mask variable. ++ */ ++extern uint32_t g_dbg_lvl; ++/** ++ * Set the Debug Level variable. ++ */ ++static inline uint32_t SET_DEBUG_LEVEL(const uint32_t new) ++{ ++ uint32_t old = g_dbg_lvl; ++ g_dbg_lvl = new; ++ return old; ++} ++ ++/** When debug level has the DBG_CIL bit set, display CIL Debug messages. */ ++#define DBG_CIL (0x2) ++/** When debug level has the DBG_CILV bit set, display CIL Verbose debug ++ * messages */ ++#define DBG_CILV (0x20) ++/** When debug level has the DBG_PCD bit set, display PCD (Device) debug ++ * messages */ ++#define DBG_PCD (0x4) ++/** When debug level has the DBG_PCDV set, display PCD (Device) Verbose debug ++ * messages */ ++#define DBG_PCDV (0x40) ++/** When debug level has the DBG_HCD bit set, display Host debug messages */ ++#define DBG_HCD (0x8) ++/** When debug level has the DBG_HCDV bit set, display Verbose Host debug ++ * messages */ ++#define DBG_HCDV (0x80) ++/** When debug level has the DBG_HCD_URB bit set, display enqueued URBs in host ++ * mode. */ ++#define DBG_HCD_URB (0x800) ++ ++/** When debug level has any bit set, display debug messages */ ++#define DBG_ANY (0xFF) ++ ++/** All debug messages off */ ++#define DBG_OFF 0 ++ ++/** Prefix string for DWC_DEBUG print macros. */ ++#define USB_DWC "DWC_otg: " ++ ++/** ++ * Print a debug message when the Global debug level variable contains ++ * the bit defined in lvl. ++ * ++ * @param[in] lvl - Debug level, use one of the DBG_ constants above. ++ * @param[in] x - like printf ++ * ++ * Example:

++ * ++ * DWC_DEBUGPL( DBG_ANY, "%s(%p)\n", __func__, _reg_base_addr); ++ * ++ *
++ * results in:
++ * ++ * usb-DWC_otg: dwc_otg_cil_init(ca867000) ++ * ++ */ ++#ifdef DEBUG ++ ++# define DWC_DEBUGPL(lvl, x...) do{ if ((lvl)&g_dbg_lvl)__DWC_DEBUG(USB_DWC x ); }while(0) ++# define DWC_DEBUGP(x...) DWC_DEBUGPL(DBG_ANY, x ) ++ ++# define CHK_DEBUG_LEVEL(level) ((level) & g_dbg_lvl) ++ ++#else ++ ++# define DWC_DEBUGPL(lvl, x...) do{}while(0) ++# define DWC_DEBUGP(x...) ++ ++# define CHK_DEBUG_LEVEL(level) (0) ++ ++#endif /*DEBUG*/ ++#endif +Index: linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_driver.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_driver.c 2013-07-26 19:31:23.000000000 +0000 +@@ -0,0 +1,1577 @@ ++/* ========================================================================== ++ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_driver.c $ ++ * $Revision: #76 $ ++ * $Date: 2009/05/03 $ ++ * $Change: 1245589 $ ++ * ++ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, ++ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless ++ * otherwise expressly agreed to in writing between Synopsys and you. ++ * ++ * The Software IS NOT an item of Licensed Software or Licensed Product under ++ * any End User Software License Agreement or Agreement for Licensed Product ++ * with Synopsys or any supplement thereto. You are permitted to use and ++ * redistribute this Software in source and binary forms, with or without ++ * modification, provided that redistributions of source code must retain this ++ * notice. You may not view, use, disclose, copy or distribute this file or ++ * any information contained herein except pursuant to this license grant from ++ * Synopsys. If you do not agree with this notice, including the disclaimer ++ * below, then you are not authorized to use the Software. ++ * ++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, ++ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR ++ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER ++ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY ++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH ++ * DAMAGE. ++ * ========================================================================== */ ++ ++/** @file ++ * The dwc_otg_driver module provides the initialization and cleanup entry ++ * points for the DWC_otg driver. This module will be dynamically installed ++ * after Linux is booted using the insmod command. When the module is ++ * installed, the dwc_otg_driver_init function is called. When the module is ++ * removed (using rmmod), the dwc_otg_driver_cleanup function is called. ++ * ++ * This module also defines a data structure for the dwc_otg_driver, which is ++ * used in conjunction with the standard ARM lm_device structure. These ++ * structures allow the OTG driver to comply with the standard Linux driver ++ * model in which devices and drivers are registered with a bus driver. This ++ * has the benefit that Linux can expose attributes of the driver and device ++ * in its special sysfs file system. Users can then read or write files in ++ * this file system to perform diagnostics on the driver components or the ++ * device. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include /* permission constants */ ++#include ++#include ++ ++#ifdef LM_INTERFACE ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30)) ++#include ++#include ++#else ++/* in 2.6.31, at least, we seem to have lost the generic LM infrastructure - ++ here we use definitions stolen from arm-integrator headers ++*/ ++#include ++#include ++#endif ++#include ++#include ++ ++#elif defined(PLATFORM_INTERFACE) ++ ++#include ++#include ++ ++#endif ++ ++# include ++ ++#include ++ ++ ++#include "dwc_os.h" ++#include "dwc_otg_dbg.h" ++#include "dwc_otg_driver.h" ++#include "dwc_otg_attr.h" ++#include "dwc_otg_core_if.h" ++#include "dwc_otg_pcd_if.h" ++#include "dwc_otg_hcd_if.h" ++ ++#define DWC_DRIVER_VERSION "2.90b 6-MAY-2010" ++#define DWC_DRIVER_DESC "HS OTG USB Controller driver" ++ ++static const char dwc_driver_name[] = "dwc_otg"; ++ ++extern int pcd_init( ++#ifdef LM_INTERFACE ++ struct lm_device *_dev ++#elif defined(PCI_INTERFACE) ++ struct pci_dev *_dev ++#elif defined(PLATFORM_INTERFACE) ++ struct platform_device *dev ++#endif ++ ); ++extern int hcd_init( ++#ifdef LM_INTERFACE ++ struct lm_device *_dev ++#elif defined(PCI_INTERFACE) ++ struct pci_dev *_dev ++#elif defined(PLATFORM_INTERFACE) ++ struct platform_device *dev ++#endif ++ ); ++ ++extern int pcd_remove( ++#ifdef LM_INTERFACE ++ struct lm_device *_dev ++#elif defined(PCI_INTERFACE) ++ struct pci_dev *_dev ++#elif defined(PLATFORM_INTERFACE) ++ struct platform_device *_dev ++#endif ++ ); ++ ++extern void hcd_remove( ++#ifdef LM_INTERFACE ++ struct lm_device *_dev ++#elif defined(PCI_INTERFACE) ++ struct pci_dev *_dev ++#elif defined(PLATFORM_INTERFACE) ++ struct platform_device *_dev ++#endif ++ ); ++ ++/*-------------------------------------------------------------------------*/ ++/* Encapsulate the module parameter settings */ ++ ++struct dwc_otg_driver_module_params { ++ int32_t opt; ++ int32_t otg_cap; ++ int32_t dma_enable; ++ int32_t dma_desc_enable; ++ int32_t dma_burst_size; ++ int32_t speed; ++ int32_t host_support_fs_ls_low_power; ++ int32_t host_ls_low_power_phy_clk; ++ int32_t enable_dynamic_fifo; ++ int32_t data_fifo_size; ++ int32_t dev_rx_fifo_size; ++ int32_t dev_nperio_tx_fifo_size; ++ uint32_t dev_perio_tx_fifo_size[MAX_PERIO_FIFOS]; ++ int32_t host_rx_fifo_size; ++ int32_t host_nperio_tx_fifo_size; ++ int32_t host_perio_tx_fifo_size; ++ int32_t max_transfer_size; ++ int32_t max_packet_count; ++ int32_t host_channels; ++ int32_t dev_endpoints; ++ int32_t phy_type; ++ int32_t phy_utmi_width; ++ int32_t phy_ulpi_ddr; ++ int32_t phy_ulpi_ext_vbus; ++ int32_t i2c_enable; ++ int32_t ulpi_fs_ls; ++ int32_t ts_dline; ++ int32_t en_multiple_tx_fifo; ++ uint32_t dev_tx_fifo_size[MAX_TX_FIFOS]; ++ uint32_t thr_ctl; ++ uint32_t tx_thr_length; ++ uint32_t rx_thr_length; ++ int32_t pti_enable; ++ int32_t mpi_enable; ++ int32_t lpm_enable; ++ int32_t ic_usb_cap; ++ int32_t ahb_thr_ratio; ++}; ++ ++static struct dwc_otg_driver_module_params dwc_otg_module_params = { ++ .opt = -1, ++ .otg_cap = -1, ++ .dma_enable = -1, ++ .dma_desc_enable = -1, ++ .dma_burst_size = -1, ++ .speed = -1, ++ .host_support_fs_ls_low_power = -1, ++ .host_ls_low_power_phy_clk = -1, ++ .enable_dynamic_fifo = -1, ++ .data_fifo_size = -1, ++ .dev_rx_fifo_size = -1, ++ .dev_nperio_tx_fifo_size = -1, ++ .dev_perio_tx_fifo_size = { ++ /* dev_perio_tx_fifo_size_1 */ ++ -1, ++ -1, ++ -1, ++ -1, ++ -1, ++ -1, ++ -1, ++ -1, ++ -1, ++ -1, ++ -1, ++ -1, ++ -1, ++ -1, ++ -1 ++ /* 15 */ ++ }, ++ .host_rx_fifo_size = -1, ++ .host_nperio_tx_fifo_size = -1, ++ .host_perio_tx_fifo_size = -1, ++ .max_transfer_size = -1, ++ .max_packet_count = -1, ++ .host_channels = -1, ++ .dev_endpoints = -1, ++ .phy_type = -1, ++ .phy_utmi_width = -1, ++ .phy_ulpi_ddr = -1, ++ .phy_ulpi_ext_vbus = -1, ++ .i2c_enable = -1, ++ .ulpi_fs_ls = -1, ++ .ts_dline = -1, ++ .en_multiple_tx_fifo = -1, ++ .dev_tx_fifo_size = { ++ /* dev_tx_fifo_size */ ++ -1, ++ -1, ++ -1, ++ -1, ++ -1, ++ -1, ++ -1, ++ -1, ++ -1, ++ -1, ++ -1, ++ -1, ++ -1, ++ -1, ++ -1 ++ /* 15 */ ++ }, ++ .thr_ctl = -1, ++ .tx_thr_length = -1, ++ .rx_thr_length = -1, ++ .pti_enable = -1, ++ .mpi_enable = -1, ++ .lpm_enable = -1, ++ .ic_usb_cap = -1, ++ .ahb_thr_ratio = -1, ++}; ++ ++/** ++ * This function shows the Driver Version. ++ */ ++static ssize_t version_show(struct device_driver *dev, char *buf) ++{ ++ return snprintf(buf, sizeof(DWC_DRIVER_VERSION) + 2, "%s\n", ++ DWC_DRIVER_VERSION); ++} ++ ++static DRIVER_ATTR(version, S_IRUGO, version_show, NULL); ++ ++/** ++ * Global Debug Level Mask. ++ */ ++uint32_t g_dbg_lvl = 0; /* OFF */ ++ ++/** ++ * This function shows the driver Debug Level. ++ */ ++static ssize_t dbg_level_show(struct device_driver *drv, char *buf) ++{ ++ return sprintf(buf, "0x%0x\n", g_dbg_lvl); ++} ++ ++/** ++ * This function stores the driver Debug Level. ++ */ ++static ssize_t dbg_level_store(struct device_driver *drv, const char *buf, ++ size_t count) ++{ ++ g_dbg_lvl = simple_strtoul(buf, NULL, 16); ++ return count; ++} ++ ++static DRIVER_ATTR(debuglevel, S_IRUGO | S_IWUSR, dbg_level_show, ++ dbg_level_store); ++ ++/** ++ * This function is called during module intialization ++ * to pass module parameters to the DWC_OTG CORE. ++ */ ++static int set_parameters(dwc_otg_core_if_t * core_if) ++{ ++ int retval = 0; ++ int i; ++ ++ if (dwc_otg_module_params.otg_cap != -1) { ++ retval += ++ dwc_otg_set_param_otg_cap(core_if, ++ dwc_otg_module_params.otg_cap); ++ } ++ if (dwc_otg_module_params.dma_enable != -1) { ++ retval += ++ dwc_otg_set_param_dma_enable(core_if, ++ dwc_otg_module_params. ++ dma_enable); ++ } ++ if (dwc_otg_module_params.dma_desc_enable != -1) { ++ retval += ++ dwc_otg_set_param_dma_desc_enable(core_if, ++ dwc_otg_module_params. ++ dma_desc_enable); ++ } ++ if (dwc_otg_module_params.opt != -1) { ++ retval += ++ dwc_otg_set_param_opt(core_if, dwc_otg_module_params.opt); ++ } ++ if (dwc_otg_module_params.dma_burst_size != -1) { ++ retval += ++ dwc_otg_set_param_dma_burst_size(core_if, ++ dwc_otg_module_params. ++ dma_burst_size); ++ } ++ if (dwc_otg_module_params.host_support_fs_ls_low_power != -1) { ++ retval += ++ dwc_otg_set_param_host_support_fs_ls_low_power(core_if, ++ dwc_otg_module_params. ++ host_support_fs_ls_low_power); ++ } ++ if (dwc_otg_module_params.enable_dynamic_fifo != -1) { ++ retval += ++ dwc_otg_set_param_enable_dynamic_fifo(core_if, ++ dwc_otg_module_params. ++ enable_dynamic_fifo); ++ } ++ if (dwc_otg_module_params.data_fifo_size != -1) { ++ retval += ++ dwc_otg_set_param_data_fifo_size(core_if, ++ dwc_otg_module_params. ++ data_fifo_size); ++ } ++ if (dwc_otg_module_params.dev_rx_fifo_size != -1) { ++ retval += ++ dwc_otg_set_param_dev_rx_fifo_size(core_if, ++ dwc_otg_module_params. ++ dev_rx_fifo_size); ++ } ++ if (dwc_otg_module_params.dev_nperio_tx_fifo_size != -1) { ++ retval += ++ dwc_otg_set_param_dev_nperio_tx_fifo_size(core_if, ++ dwc_otg_module_params. ++ dev_nperio_tx_fifo_size); ++ } ++ if (dwc_otg_module_params.host_rx_fifo_size != -1) { ++ retval += ++ dwc_otg_set_param_host_rx_fifo_size(core_if, ++ dwc_otg_module_params.host_rx_fifo_size); ++ } ++ if (dwc_otg_module_params.host_nperio_tx_fifo_size != -1) { ++ retval += ++ dwc_otg_set_param_host_nperio_tx_fifo_size(core_if, ++ dwc_otg_module_params. ++ host_nperio_tx_fifo_size); ++ } ++ if (dwc_otg_module_params.host_perio_tx_fifo_size != -1) { ++ retval += ++ dwc_otg_set_param_host_perio_tx_fifo_size(core_if, ++ dwc_otg_module_params. ++ host_perio_tx_fifo_size); ++ } ++ if (dwc_otg_module_params.max_transfer_size != -1) { ++ retval += ++ dwc_otg_set_param_max_transfer_size(core_if, ++ dwc_otg_module_params. ++ max_transfer_size); ++ } ++ if (dwc_otg_module_params.max_packet_count != -1) { ++ retval += ++ dwc_otg_set_param_max_packet_count(core_if, ++ dwc_otg_module_params. ++ max_packet_count); ++ } ++ if (dwc_otg_module_params.host_channels != -1) { ++ retval += ++ dwc_otg_set_param_host_channels(core_if, ++ dwc_otg_module_params. ++ host_channels); ++ } ++ if (dwc_otg_module_params.dev_endpoints != -1) { ++ retval += ++ dwc_otg_set_param_dev_endpoints(core_if, ++ dwc_otg_module_params. ++ dev_endpoints); ++ } ++ if (dwc_otg_module_params.phy_type != -1) { ++ retval += ++ dwc_otg_set_param_phy_type(core_if, ++ dwc_otg_module_params.phy_type); ++ } ++ if (dwc_otg_module_params.speed != -1) { ++ retval += ++ dwc_otg_set_param_speed(core_if, ++ dwc_otg_module_params.speed); ++ } ++ if (dwc_otg_module_params.host_ls_low_power_phy_clk != -1) { ++ retval += ++ dwc_otg_set_param_host_ls_low_power_phy_clk(core_if, ++ dwc_otg_module_params. ++ host_ls_low_power_phy_clk); ++ } ++ if (dwc_otg_module_params.phy_ulpi_ddr != -1) { ++ retval += ++ dwc_otg_set_param_phy_ulpi_ddr(core_if, ++ dwc_otg_module_params. ++ phy_ulpi_ddr); ++ } ++ if (dwc_otg_module_params.phy_ulpi_ext_vbus != -1) { ++ retval += ++ dwc_otg_set_param_phy_ulpi_ext_vbus(core_if, ++ dwc_otg_module_params. ++ phy_ulpi_ext_vbus); ++ } ++ if (dwc_otg_module_params.phy_utmi_width != -1) { ++ retval += ++ dwc_otg_set_param_phy_utmi_width(core_if, ++ dwc_otg_module_params. ++ phy_utmi_width); ++ } ++ if (dwc_otg_module_params.ulpi_fs_ls != -1) { ++ retval += ++ dwc_otg_set_param_ulpi_fs_ls(core_if, dwc_otg_module_params.ulpi_fs_ls); ++ } ++ if (dwc_otg_module_params.ts_dline != -1) { ++ retval += ++ dwc_otg_set_param_ts_dline(core_if, ++ dwc_otg_module_params.ts_dline); ++ } ++ if (dwc_otg_module_params.i2c_enable != -1) { ++ retval += ++ dwc_otg_set_param_i2c_enable(core_if, ++ dwc_otg_module_params. ++ i2c_enable); ++ } ++ if (dwc_otg_module_params.en_multiple_tx_fifo != -1) { ++ retval += ++ dwc_otg_set_param_en_multiple_tx_fifo(core_if, ++ dwc_otg_module_params. ++ en_multiple_tx_fifo); ++ } ++ for (i = 0; i < 15; i++) { ++ if (dwc_otg_module_params.dev_perio_tx_fifo_size[i] != -1) { ++ retval += ++ dwc_otg_set_param_dev_perio_tx_fifo_size(core_if, ++ dwc_otg_module_params. ++ dev_perio_tx_fifo_size ++ [i], i); ++ } ++ } ++ ++ for (i = 0; i < 15; i++) { ++ if (dwc_otg_module_params.dev_tx_fifo_size[i] != -1) { ++ retval += dwc_otg_set_param_dev_tx_fifo_size(core_if, ++ dwc_otg_module_params. ++ dev_tx_fifo_size ++ [i], i); ++ } ++ } ++ if (dwc_otg_module_params.thr_ctl != -1) { ++ retval += ++ dwc_otg_set_param_thr_ctl(core_if, ++ dwc_otg_module_params.thr_ctl); ++ } ++ if (dwc_otg_module_params.mpi_enable != -1) { ++ retval += ++ dwc_otg_set_param_mpi_enable(core_if, ++ dwc_otg_module_params. ++ mpi_enable); ++ } ++ if (dwc_otg_module_params.pti_enable != -1) { ++ retval += ++ dwc_otg_set_param_pti_enable(core_if, ++ dwc_otg_module_params. ++ pti_enable); ++ } ++ if (dwc_otg_module_params.lpm_enable != -1) { ++ retval += ++ dwc_otg_set_param_lpm_enable(core_if, ++ dwc_otg_module_params. ++ lpm_enable); ++ } ++ if (dwc_otg_module_params.ic_usb_cap != -1) { ++ retval += ++ dwc_otg_set_param_ic_usb_cap(core_if, ++ dwc_otg_module_params. ++ ic_usb_cap); ++ } ++ if (dwc_otg_module_params.tx_thr_length != -1) { ++ retval += ++ dwc_otg_set_param_tx_thr_length(core_if, ++ dwc_otg_module_params.tx_thr_length); ++ } ++ if (dwc_otg_module_params.rx_thr_length != -1) { ++ retval += ++ dwc_otg_set_param_rx_thr_length(core_if, ++ dwc_otg_module_params. ++ rx_thr_length); ++ } ++ if(dwc_otg_module_params.ahb_thr_ratio != -1) { ++ retval += ++ dwc_otg_set_param_ahb_thr_ratio(core_if, dwc_otg_module_params.ahb_thr_ratio); ++ } ++ return retval; ++} ++ ++/** ++ * This function is the top level interrupt handler for the Common ++ * (Device and host modes) interrupts. ++ */ ++static irqreturn_t dwc_otg_common_irq(int irq, void *dev) ++{ ++ dwc_otg_device_t *otg_dev = dev; ++ int32_t retval = IRQ_NONE; ++ ++ retval = dwc_otg_handle_common_intr(otg_dev->core_if); ++ if (retval != 0) { ++ S3C2410X_CLEAR_EINTPEND(); ++ } ++ return IRQ_RETVAL(retval); ++} ++ ++/** ++ * This function is called when a lm_device is unregistered with the ++ * dwc_otg_driver. This happens, for example, when the rmmod command is ++ * executed. The device may or may not be electrically present. If it is ++ * present, the driver stops device processing. Any resources used on behalf ++ * of this device are freed. ++ * ++ * @param _dev ++ */ ++#ifdef LM_INTERFACE ++static void dwc_otg_driver_remove( ++ struct lm_device *_dev ++#elif defined(PCI_INTERFACE) ++static void dwc_otg_driver_remove( ++ struct pci_dev *_dev ++#elif defined(PLATFORM_INTERFACE) ++static int dwc_otg_driver_remove( ++ struct platform_device *_dev ++#endif ++) ++ ++{ ++#ifdef LM_INTERFACE ++ dwc_otg_device_t *otg_dev = lm_get_drvdata(_dev); ++#elif defined(PCI_INTERFACE) ++ dwc_otg_device_t *otg_dev = pci_get_drvdata(_dev); ++#elif defined(PLATFORM_INTERFACE) ++ dwc_otg_device_t *otg_dev = platform_get_drvdata(_dev); ++#endif ++ ++ ++ DWC_DEBUGPL(DBG_ANY, "%s(%p) otg_dev %p\n", __func__, _dev, otg_dev); ++ ++ if (!otg_dev) { ++ /* Memory allocation for the dwc_otg_device failed. */ ++ DWC_DEBUGPL(DBG_ANY, "%s: otg_dev NULL!\n", __func__); ++#ifdef PLATFORM_INTERFACE ++ return -ENOMEM; ++#else ++ return; ++#endif ++ } ++#ifndef DWC_DEVICE_ONLY ++ if (otg_dev->hcd) { ++ hcd_remove(_dev); ++ } else { ++ DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->hcd NULL!\n", __func__); ++#ifdef PLATFORM_INTERFACE ++ return -EINVAL; ++#else ++ return; ++#endif ++ } ++#endif ++ ++#ifndef DWC_HOST_ONLY ++ if (otg_dev->pcd) { ++ pcd_remove(_dev); ++ } ++#endif ++ /* ++ * Free the IRQ ++ */ ++ if (otg_dev->common_irq_installed) { ++#ifdef PLATFORM_INTERFACE ++ free_irq(platform_get_irq(_dev, 0), otg_dev); ++#else ++ free_irq(_dev->irq, otg_dev); ++#endif ++ } ++ ++ if (otg_dev->core_if) { ++ dwc_otg_cil_remove(otg_dev->core_if); ++ } ++ ++ /* ++ * Remove the device attributes ++ */ ++ dwc_otg_attr_remove(_dev); ++ ++ /* ++ * Return the memory. ++ */ ++ if (otg_dev->base) { ++ iounmap(otg_dev->base); ++ } ++ dwc_free(otg_dev); ++ ++ /* ++ * Clear the drvdata pointer. ++ */ ++#ifdef LM_INTERFACE ++ lm_set_drvdata(_dev, 0); ++#elif defined(PCI_INTERFACE) ++ release_mem_region(otg_dev->rsrc_start, otg_dev->rsrc_len); ++ pci_set_drvdata(_dev, 0); ++#elif defined(PLATFORM_INTERFACE) ++ platform_set_drvdata(_dev, 0); ++ return 0; ++#endif ++} ++ ++/** ++ * This function is called when an lm_device is bound to a ++ * dwc_otg_driver. It creates the driver components required to ++ * control the device (CIL, HCD, and PCD) and it initializes the ++ * device. The driver components are stored in a dwc_otg_device ++ * structure. A reference to the dwc_otg_device is saved in the ++ * lm_device. This allows the driver to access the dwc_otg_device ++ * structure on subsequent calls to driver methods for this device. ++ * ++ * @param _dev Bus device ++ */ ++static int dwc_otg_driver_probe( ++#ifdef LM_INTERFACE ++struct lm_device *_dev ++#elif defined(PCI_INTERFACE) ++struct pci_dev *_dev, const struct pci_device_id *id ++#elif defined(PLATFORM_INTERFACE) ++struct platform_device *_dev ++#endif ++) ++{ ++ int retval = 0; ++ dwc_otg_device_t *dwc_otg_device; ++ int devirq; ++ ++ dev_dbg(&_dev->dev, "dwc_otg_driver_probe(%p)\n", _dev); ++#ifdef LM_INTERFACE ++ dev_dbg(&_dev->dev, "start=0x%08x\n", (unsigned)_dev->resource.start); ++#elif defined(PCI_INTERFACE) ++ if (!id) { ++ DWC_ERROR("Invalid pci_device_id %p", id); ++ return -EINVAL; ++ } ++ ++ if (!_dev || (pci_enable_device(_dev) < 0)) { ++ DWC_ERROR("Invalid pci_device %p", _dev); ++ return -ENODEV; ++ } ++ dev_dbg(&_dev->dev, "start=0x%08x\n", (unsigned)pci_resource_start(_dev,0)); ++ /* other stuff needed as well? */ ++ ++#elif defined(PLATFORM_INTERFACE) ++ dev_dbg(&_dev->dev, "start=0x%08x (len 0x%x)\n", ++ (unsigned)_dev->resource->start, ++ (unsigned)(_dev->resource->end - _dev->resource->start)); ++#endif ++ ++ ++ dwc_otg_device = dwc_alloc(sizeof(dwc_otg_device_t)); ++ ++ if (!dwc_otg_device) { ++ dev_err(&_dev->dev, "kmalloc of dwc_otg_device failed\n"); ++ retval = -ENOMEM; ++ goto fail; ++ } ++ ++ memset(dwc_otg_device, 0, sizeof(*dwc_otg_device)); ++ dwc_otg_device->reg_offset = 0xFFFFFFFF; ++ ++ /* ++ * Map the DWC_otg Core memory into virtual address space. ++ */ ++#ifdef LM_INTERFACE ++#if 1 ++ dwc_otg_device->base = ioremap(_dev->resource.start, SZ_256K); ++#else ++ struct map_desc desc = { ++ .virtual = IO_ADDRESS((unsigned)_dev->resource.start), ++ .pfn = __phys_to_pfn((unsigned)_dev->resource.start), ++ .length = SZ_128K, ++ .type = MT_DEVICE ++ }; ++ iotable_init(&desc, 1); ++ dwc_otg_device->base = (void *)desc.virtual; ++#endif ++ ++ if (!dwc_otg_device->base) { ++ dev_err(&_dev->dev, "ioremap() failed\n"); ++ retval = -ENOMEM; ++ goto fail; ++ } ++ dev_dbg(&_dev->dev, "base=0x%08x\n", (unsigned)dwc_otg_device->base); ++#elif defined(PCI_INTERFACE) ++ _dev->current_state = PCI_D0; ++ _dev->dev.power.power_state = PMSG_ON; ++ ++ if (!_dev->irq) { ++ DWC_ERROR("Found HC with no IRQ. Check BIOS/PCI %s setup!", pci_name(_dev)); ++ retval = -ENODEV; ++ goto fail; ++ } ++ ++ dwc_otg_device->rsrc_start = pci_resource_start(_dev,0); ++ dwc_otg_device->rsrc_len = pci_resource_len(_dev,0); ++ DWC_DEBUGPL(DBG_ANY,"PCI resource: start=%08x, len=%08x\n", ++ dwc_otg_device->rsrc_start, ++ dwc_otg_device->rsrc_len); ++ if (!request_mem_region(dwc_otg_device->rsrc_start, dwc_otg_device->rsrc_len, "dwc_otg")) { ++ dev_dbg(&_dev->dev, "error mapping memory\n"); ++ retval = -EFAULT; ++ goto fail; ++ } ++ ++ dwc_otg_device->base = ioremap_nocache(dwc_otg_device->rsrc_start, dwc_otg_device->rsrc_len); ++ if (dwc_otg_device->base == NULL) { ++ dev_dbg(&_dev->dev, "error mapping memory\n"); ++ retval = -EFAULT; ++ goto fail; ++ } ++ dev_dbg(&_dev->dev, "base=0x%p (before adjust) \n", dwc_otg_device->base); ++ dwc_otg_device->base = (char *)dwc_otg_device->base; ++ dev_dbg(&_dev->dev, "base=0x%p (after adjust) \n", dwc_otg_device->base); ++ dev_dbg(&_dev->dev, "%s: mapped PA 0x%x to VA 0x%p\n", __func__, ++ (unsigned)dwc_otg_device->rsrc_start, dwc_otg_device->base); ++ // ++ pci_set_drvdata(_dev, dwc_otg_device); ++ pci_set_master(_dev); ++#elif defined(PLATFORM_INTERFACE) ++ DWC_DEBUGPL(DBG_ANY,"Platform resource: start=%08x, len=%08x\n", ++ _dev->resource->start, ++ _dev->resource->end - _dev->resource->start + 1); ++#if 1 ++ if (!request_mem_region(_dev->resource->start, ++ _dev->resource->end - _dev->resource->start + 1, ++ "dwc_otg")) { ++ dev_dbg(&_dev->dev, "error reserving mapped memory\n"); ++ retval = -EFAULT; ++ goto fail; ++ } ++ ++ dwc_otg_device->base = ioremap_nocache(_dev->resource->start, ++ _dev->resource->end - ++ _dev->resource->start + 1); ++#else ++ { ++ struct map_desc desc = { ++ .virtual = IO_ADDRESS((unsigned)_dev->resource->start), ++ .pfn = __phys_to_pfn((unsigned)_dev->resource->start), ++ .length = SZ_128K, ++ .type = MT_DEVICE ++ }; ++ iotable_init(&desc, 1); ++ dwc_otg_device->base = (void *)desc.virtual; ++ } ++#endif ++ if (!dwc_otg_device->base) { ++ dev_err(&_dev->dev, "ioremap() failed\n"); ++ retval = -ENOMEM; ++ goto fail; ++ } ++ dev_dbg(&_dev->dev, "base=0x%08x\n", (unsigned)dwc_otg_device->base); ++#endif ++ ++ /* ++ * Initialize driver data to point to the global DWC_otg ++ * Device structure. ++ */ ++#ifdef LM_INTERFACE ++ lm_set_drvdata(_dev, dwc_otg_device); ++#elif defined(PLATFORM_INTERFACE) ++ platform_set_drvdata(_dev, dwc_otg_device); ++#endif ++ dev_dbg(&_dev->dev, "dwc_otg_device=0x%p\n", dwc_otg_device); ++ ++ dwc_otg_device->core_if = dwc_otg_cil_init(dwc_otg_device->base); ++ DWC_DEBUGPL(DBG_HCDV, "probe of device %p given core_if %p\n", ++ dwc_otg_device, dwc_otg_device->core_if);//GRAYG ++ ++ if (!dwc_otg_device->core_if) { ++ dev_err(&_dev->dev, "CIL initialization failed!\n"); ++ retval = -ENOMEM; ++ goto fail; ++ } ++ ++ dev_dbg(&_dev->dev, "Calling get_gsnpsid\n"); ++ /* ++ * Attempt to ensure this device is really a DWC_otg Controller. ++ * Read and verify the SNPSID register contents. The value should be ++ * 0x45F42XXX, which corresponds to "OT2", as in "OTG version 2.XX". ++ */ ++ ++ if ((dwc_otg_get_gsnpsid(dwc_otg_device->core_if) & 0xFFFFF000) != ++ 0x4F542000) { ++ dev_err(&_dev->dev, "Bad value for SNPSID: 0x%08x\n", ++ dwc_otg_get_gsnpsid(dwc_otg_device->core_if)); ++ dwc_otg_cil_remove(dwc_otg_device->core_if); ++ dwc_free(dwc_otg_device); ++ retval = -EINVAL; ++ goto fail; ++ } ++ ++ /* ++ * Validate parameter values. ++ */ ++ dev_dbg(&_dev->dev, "Calling set_parameters\n"); ++ if (set_parameters(dwc_otg_device->core_if)) { ++ dwc_otg_cil_remove(dwc_otg_device->core_if); ++ retval = -EINVAL; ++ goto fail; ++ } ++ ++ /* ++ * Create Device Attributes in sysfs ++ */ ++ dev_dbg(&_dev->dev, "Calling attr_create\n"); ++ dwc_otg_attr_create(_dev); ++ ++ /* ++ * Disable the global interrupt until all the interrupt ++ * handlers are installed. ++ */ ++ dev_dbg(&_dev->dev, "Calling disable_global_interrupts\n"); ++ dwc_otg_disable_global_interrupts(dwc_otg_device->core_if); ++ ++ /* ++ * Install the interrupt handler for the common interrupts before ++ * enabling common interrupts in core_init below. ++ */ ++#if defined(PLATFORM_INTERFACE) ++ devirq = platform_get_irq(_dev, 0); ++#else ++ devirq = _dev->irq; ++#endif ++ DWC_DEBUGPL(DBG_CIL, "registering (common) handler for irq%d\n", ++ devirq); ++ dev_dbg(&_dev->dev, "Calling request_irq(%d)\n", devirq); ++ retval = request_irq(devirq, dwc_otg_common_irq, ++ IRQF_SHARED, ++ "dwc_otg", dwc_otg_device); ++ if (retval) { ++ DWC_ERROR("request of irq%d failed\n", devirq); ++ retval = -EBUSY; ++ goto fail; ++ } else { ++ dwc_otg_device->common_irq_installed = 1; ++ } ++ ++#ifndef IRQF_TRIGGER_LOW ++#if defined(LM_INTERFACE) || defined(PLATFORM_INTERFACE) ++ dev_dbg(&_dev->dev, "Calling set_irq_type\n"); ++ set_irq_type(devirq, ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30)) ++ IRQT_LOW ++#else ++ IRQ_TYPE_LEVEL_LOW ++#endif ++ ); ++#endif ++#endif /*IRQF_TRIGGER_LOW*/ ++ ++ /* ++ * Initialize the DWC_otg core. ++ */ ++ dev_dbg(&_dev->dev, "Calling dwc_otg_core_init\n"); ++ dwc_otg_core_init(dwc_otg_device->core_if); ++ ++#ifndef DWC_HOST_ONLY ++ /* ++ * Initialize the PCD ++ */ ++ dev_dbg(&_dev->dev, "Calling pcd_init\n"); ++ retval = pcd_init(_dev); ++ if (retval != 0) { ++ DWC_ERROR("pcd_init failed\n"); ++ dwc_otg_device->pcd = NULL; ++ goto fail; ++ } ++#endif ++#ifndef DWC_DEVICE_ONLY ++ /* ++ * Initialize the HCD ++ */ ++ dev_dbg(&_dev->dev, "Calling hcd_init\n"); ++ retval = hcd_init(_dev); ++ if (retval != 0) { ++ DWC_ERROR("hcd_init failed\n"); ++ dwc_otg_device->hcd = NULL; ++ goto fail; ++ } ++#endif ++ /* Recover from drvdata having been overwritten by hcd_init() */ ++#ifdef LM_INTERFACE ++ lm_set_drvdata(_dev, dwc_otg_device); ++#elif defined(PLATFORM_INTERFACE) ++ platform_set_drvdata(_dev, dwc_otg_device); ++#elif defined(PCI_INTERFACE) ++ pci_set_drvdata(_dev, dwc_otg_device); ++#endif ++ ++ /* ++ * Enable the global interrupt after all the interrupt ++ * handlers are installed. ++ */ ++ dev_dbg(&_dev->dev, "Calling enable_global_interrupts\n"); ++ dwc_otg_enable_global_interrupts(dwc_otg_device->core_if); ++ dev_dbg(&_dev->dev, "Done\n"); ++ ++ return 0; ++ ++ fail: ++ dwc_otg_driver_remove(_dev); ++ return retval; ++} ++ ++/** ++ * This structure defines the methods to be called by a bus driver ++ * during the lifecycle of a device on that bus. Both drivers and ++ * devices are registered with a bus driver. The bus driver matches ++ * devices to drivers based on information in the device and driver ++ * structures. ++ * ++ * The probe function is called when the bus driver matches a device ++ * to this driver. The remove function is called when a device is ++ * unregistered with the bus driver. ++ */ ++#ifdef LM_INTERFACE ++static struct lm_driver dwc_otg_driver = { ++ .drv = { ++ .name = (char *)dwc_driver_name, ++ }, ++ .probe = dwc_otg_driver_probe, ++ .remove = dwc_otg_driver_remove, ++ // 'suspend' and 'resume' absent ++}; ++#elif defined(PCI_INTERFACE) ++static const struct pci_device_id pci_ids[] = { { ++ PCI_DEVICE(0x16c3, 0xabcd), ++ .driver_data = (unsigned long) 0xdeadbeef, ++ }, { /* end: all zeroes */ } ++}; ++MODULE_DEVICE_TABLE(pci, pci_ids); ++ ++/* pci driver glue; this is a "new style" PCI driver module */ ++static struct pci_driver dwc_otg_driver = { ++ .name = "dwc_otg", ++ .id_table = pci_ids, ++ ++ .probe = dwc_otg_driver_probe, ++ .remove = dwc_otg_driver_remove, ++ ++ .driver = { ++ .name = (char*)dwc_driver_name, ++ }, ++}; ++#elif defined(PLATFORM_INTERFACE) ++static struct platform_device_id platform_ids[] = { ++ { ++ .name = "bcm2708_usb", ++ .driver_data = (kernel_ulong_t) 0xdeadbeef, ++ }, ++ { /* end: all zeroes */ } ++}; ++MODULE_DEVICE_TABLE(platform, platform_ids); ++ ++static struct platform_driver dwc_otg_driver = { ++ .driver = { ++ .name = (char *)dwc_driver_name, ++ }, ++ .id_table = platform_ids, ++ ++ .probe = dwc_otg_driver_probe, ++ .remove = dwc_otg_driver_remove, ++ // no 'shutdown', 'suspend', 'resume', 'suspend_late' or 'resume_early' ++}; ++#endif ++ ++ ++/** ++ * This function is called when the dwc_otg_driver is installed with the ++ * insmod command. It registers the dwc_otg_driver structure with the ++ * appropriate bus driver. This will cause the dwc_otg_driver_probe function ++ * to be called. In addition, the bus driver will automatically expose ++ * attributes defined for the device and driver in the special sysfs file ++ * system. ++ * ++ * @return ++ */ ++static int __init dwc_otg_driver_init(void) ++{ ++ int retval = 0; ++ int error; ++ printk(KERN_INFO "%s: version %s (%s bus)\n", dwc_driver_name, ++ DWC_DRIVER_VERSION, ++#ifdef LM_INTERFACE ++ "logicmodule"); ++ retval = lm_driver_register(&dwc_otg_driver); ++#elif defined(PCI_INTERFACE) ++ "pci"); ++ retval = pci_register_driver(&dwc_otg_driver); ++#elif defined(PLATFORM_INTERFACE) ++ "platform"); ++ retval = platform_driver_register(&dwc_otg_driver); ++#endif ++ if (retval < 0) { ++ printk(KERN_ERR "%s retval=%d\n", __func__, retval); ++ return retval; ++ } ++#ifdef LM_INTERFACE ++ error = driver_create_file(&dwc_otg_driver.drv, &driver_attr_version); ++ error = driver_create_file(&dwc_otg_driver.drv, &driver_attr_debuglevel); ++#elif defined(PCI_INTERFACE) ++ error = driver_create_file(&dwc_otg_driver.driver, ++ &driver_attr_version); ++ error = driver_create_file(&dwc_otg_driver.driver, ++ &driver_attr_debuglevel); ++#elif defined(PLATFORM_INTERFACE) ++ error = driver_create_file(&dwc_otg_driver.driver, ++ &driver_attr_version); ++ error = driver_create_file(&dwc_otg_driver.driver, ++ &driver_attr_debuglevel); ++#endif ++ return retval; ++} ++ ++module_init(dwc_otg_driver_init); ++ ++/** ++ * This function is called when the driver is removed from the kernel ++ * with the rmmod command. The driver unregisters itself with its bus ++ * driver. ++ * ++ */ ++static void __exit dwc_otg_driver_cleanup(void) ++{ ++ printk(KERN_DEBUG "dwc_otg_driver_cleanup()\n"); ++ ++#ifdef LM_INTERFACE ++ driver_remove_file(&dwc_otg_driver.drv, &driver_attr_debuglevel); ++ driver_remove_file(&dwc_otg_driver.drv, &driver_attr_version); ++ lm_driver_unregister(&dwc_otg_driver); ++#elif defined(PCI_INTERFACE) ++ driver_remove_file(&dwc_otg_driver.driver, &driver_attr_debuglevel); ++ driver_remove_file(&dwc_otg_driver.driver, &driver_attr_version); ++ pci_unregister_driver(&dwc_otg_driver); ++#elif defined(PLATFORM_INTERFACE) ++ driver_remove_file(&dwc_otg_driver.driver, &driver_attr_debuglevel); ++ driver_remove_file(&dwc_otg_driver.driver, &driver_attr_version); ++ platform_driver_unregister(&dwc_otg_driver); ++#endif ++ ++ printk(KERN_INFO "%s module removed\n", dwc_driver_name); ++} ++module_exit(dwc_otg_driver_cleanup); ++ ++MODULE_DESCRIPTION(DWC_DRIVER_DESC); ++MODULE_AUTHOR("Synopsys Inc."); ++MODULE_LICENSE("GPL"); ++ ++module_param_named(otg_cap, dwc_otg_module_params.otg_cap, int, 0444); ++MODULE_PARM_DESC(otg_cap, "OTG Capabilities 0=HNP&SRP 1=SRP Only 2=None"); ++module_param_named(opt, dwc_otg_module_params.opt, int, 0444); ++MODULE_PARM_DESC(opt, "OPT Mode"); ++module_param_named(dma_enable, dwc_otg_module_params.dma_enable, int, 0444); ++MODULE_PARM_DESC(dma_enable, "DMA Mode 0=Slave 1=DMA enabled"); ++ ++module_param_named(dma_desc_enable, dwc_otg_module_params.dma_desc_enable, int, ++ 0444); ++MODULE_PARM_DESC(dma_desc_enable, ++ "DMA Desc Mode 0=Address DMA 1=DMA Descriptor enabled"); ++ ++module_param_named(dma_burst_size, dwc_otg_module_params.dma_burst_size, int, ++ 0444); ++MODULE_PARM_DESC(dma_burst_size, ++ "DMA Burst Size 1, 4, 8, 16, 32, 64, 128, 256"); ++module_param_named(speed, dwc_otg_module_params.speed, int, 0444); ++MODULE_PARM_DESC(speed, "Speed 0=High Speed 1=Full Speed"); ++module_param_named(host_support_fs_ls_low_power, ++ dwc_otg_module_params.host_support_fs_ls_low_power, int, ++ 0444); ++MODULE_PARM_DESC(host_support_fs_ls_low_power, ++ "Support Low Power w/FS or LS 0=Support 1=Don't Support"); ++module_param_named(host_ls_low_power_phy_clk, ++ dwc_otg_module_params.host_ls_low_power_phy_clk, int, 0444); ++MODULE_PARM_DESC(host_ls_low_power_phy_clk, ++ "Low Speed Low Power Clock 0=48Mhz 1=6Mhz"); ++module_param_named(enable_dynamic_fifo, ++ dwc_otg_module_params.enable_dynamic_fifo, int, 0444); ++MODULE_PARM_DESC(enable_dynamic_fifo, "0=cC Setting 1=Allow Dynamic Sizing"); ++module_param_named(data_fifo_size, dwc_otg_module_params.data_fifo_size, int, ++ 0444); ++MODULE_PARM_DESC(data_fifo_size, ++ "Total number of words in the data FIFO memory 32-32768"); ++module_param_named(dev_rx_fifo_size, dwc_otg_module_params.dev_rx_fifo_size, ++ int, 0444); ++MODULE_PARM_DESC(dev_rx_fifo_size, "Number of words in the Rx FIFO 16-32768"); ++module_param_named(dev_nperio_tx_fifo_size, ++ dwc_otg_module_params.dev_nperio_tx_fifo_size, int, 0444); ++MODULE_PARM_DESC(dev_nperio_tx_fifo_size, ++ "Number of words in the non-periodic Tx FIFO 16-32768"); ++module_param_named(dev_perio_tx_fifo_size_1, ++ dwc_otg_module_params.dev_perio_tx_fifo_size[0], int, 0444); ++MODULE_PARM_DESC(dev_perio_tx_fifo_size_1, ++ "Number of words in the periodic Tx FIFO 4-768"); ++module_param_named(dev_perio_tx_fifo_size_2, ++ dwc_otg_module_params.dev_perio_tx_fifo_size[1], int, 0444); ++MODULE_PARM_DESC(dev_perio_tx_fifo_size_2, ++ "Number of words in the periodic Tx FIFO 4-768"); ++module_param_named(dev_perio_tx_fifo_size_3, ++ dwc_otg_module_params.dev_perio_tx_fifo_size[2], int, 0444); ++MODULE_PARM_DESC(dev_perio_tx_fifo_size_3, ++ "Number of words in the periodic Tx FIFO 4-768"); ++module_param_named(dev_perio_tx_fifo_size_4, ++ dwc_otg_module_params.dev_perio_tx_fifo_size[3], int, 0444); ++MODULE_PARM_DESC(dev_perio_tx_fifo_size_4, ++ "Number of words in the periodic Tx FIFO 4-768"); ++module_param_named(dev_perio_tx_fifo_size_5, ++ dwc_otg_module_params.dev_perio_tx_fifo_size[4], int, 0444); ++MODULE_PARM_DESC(dev_perio_tx_fifo_size_5, ++ "Number of words in the periodic Tx FIFO 4-768"); ++module_param_named(dev_perio_tx_fifo_size_6, ++ dwc_otg_module_params.dev_perio_tx_fifo_size[5], int, 0444); ++MODULE_PARM_DESC(dev_perio_tx_fifo_size_6, ++ "Number of words in the periodic Tx FIFO 4-768"); ++module_param_named(dev_perio_tx_fifo_size_7, ++ dwc_otg_module_params.dev_perio_tx_fifo_size[6], int, 0444); ++MODULE_PARM_DESC(dev_perio_tx_fifo_size_7, ++ "Number of words in the periodic Tx FIFO 4-768"); ++module_param_named(dev_perio_tx_fifo_size_8, ++ dwc_otg_module_params.dev_perio_tx_fifo_size[7], int, 0444); ++MODULE_PARM_DESC(dev_perio_tx_fifo_size_8, ++ "Number of words in the periodic Tx FIFO 4-768"); ++module_param_named(dev_perio_tx_fifo_size_9, ++ dwc_otg_module_params.dev_perio_tx_fifo_size[8], int, 0444); ++MODULE_PARM_DESC(dev_perio_tx_fifo_size_9, ++ "Number of words in the periodic Tx FIFO 4-768"); ++module_param_named(dev_perio_tx_fifo_size_10, ++ dwc_otg_module_params.dev_perio_tx_fifo_size[9], int, 0444); ++MODULE_PARM_DESC(dev_perio_tx_fifo_size_10, ++ "Number of words in the periodic Tx FIFO 4-768"); ++module_param_named(dev_perio_tx_fifo_size_11, ++ dwc_otg_module_params.dev_perio_tx_fifo_size[10], int, 0444); ++MODULE_PARM_DESC(dev_perio_tx_fifo_size_11, ++ "Number of words in the periodic Tx FIFO 4-768"); ++module_param_named(dev_perio_tx_fifo_size_12, ++ dwc_otg_module_params.dev_perio_tx_fifo_size[11], int, 0444); ++MODULE_PARM_DESC(dev_perio_tx_fifo_size_12, ++ "Number of words in the periodic Tx FIFO 4-768"); ++module_param_named(dev_perio_tx_fifo_size_13, ++ dwc_otg_module_params.dev_perio_tx_fifo_size[12], int, 0444); ++MODULE_PARM_DESC(dev_perio_tx_fifo_size_13, ++ "Number of words in the periodic Tx FIFO 4-768"); ++module_param_named(dev_perio_tx_fifo_size_14, ++ dwc_otg_module_params.dev_perio_tx_fifo_size[13], int, 0444); ++MODULE_PARM_DESC(dev_perio_tx_fifo_size_14, ++ "Number of words in the periodic Tx FIFO 4-768"); ++module_param_named(dev_perio_tx_fifo_size_15, ++ dwc_otg_module_params.dev_perio_tx_fifo_size[14], int, 0444); ++MODULE_PARM_DESC(dev_perio_tx_fifo_size_15, ++ "Number of words in the periodic Tx FIFO 4-768"); ++module_param_named(host_rx_fifo_size, dwc_otg_module_params.host_rx_fifo_size, ++ int, 0444); ++MODULE_PARM_DESC(host_rx_fifo_size, "Number of words in the Rx FIFO 16-32768"); ++module_param_named(host_nperio_tx_fifo_size, ++ dwc_otg_module_params.host_nperio_tx_fifo_size, int, 0444); ++MODULE_PARM_DESC(host_nperio_tx_fifo_size, ++ "Number of words in the non-periodic Tx FIFO 16-32768"); ++module_param_named(host_perio_tx_fifo_size, ++ dwc_otg_module_params.host_perio_tx_fifo_size, int, 0444); ++MODULE_PARM_DESC(host_perio_tx_fifo_size, ++ "Number of words in the host periodic Tx FIFO 16-32768"); ++module_param_named(max_transfer_size, dwc_otg_module_params.max_transfer_size, ++ int, 0444); ++/** @todo Set the max to 512K, modify checks */ ++MODULE_PARM_DESC(max_transfer_size, ++ "The maximum transfer size supported in bytes 2047-65535"); ++module_param_named(max_packet_count, dwc_otg_module_params.max_packet_count, ++ int, 0444); ++MODULE_PARM_DESC(max_packet_count, ++ "The maximum number of packets in a transfer 15-511"); ++module_param_named(host_channels, dwc_otg_module_params.host_channels, int, ++ 0444); ++MODULE_PARM_DESC(host_channels, ++ "The number of host channel registers to use 1-16"); ++module_param_named(dev_endpoints, dwc_otg_module_params.dev_endpoints, int, ++ 0444); ++MODULE_PARM_DESC(dev_endpoints, ++ "The number of endpoints in addition to EP0 available for device mode 1-15"); ++module_param_named(phy_type, dwc_otg_module_params.phy_type, int, 0444); ++MODULE_PARM_DESC(phy_type, "0=Reserved 1=UTMI+ 2=ULPI"); ++module_param_named(phy_utmi_width, dwc_otg_module_params.phy_utmi_width, int, ++ 0444); ++MODULE_PARM_DESC(phy_utmi_width, "Specifies the UTMI+ Data Width 8 or 16 bits"); ++module_param_named(phy_ulpi_ddr, dwc_otg_module_params.phy_ulpi_ddr, int, 0444); ++MODULE_PARM_DESC(phy_ulpi_ddr, ++ "ULPI at double or single data rate 0=Single 1=Double"); ++module_param_named(phy_ulpi_ext_vbus, dwc_otg_module_params.phy_ulpi_ext_vbus, ++ int, 0444); ++MODULE_PARM_DESC(phy_ulpi_ext_vbus, ++ "ULPI PHY using internal or external vbus 0=Internal"); ++module_param_named(i2c_enable, dwc_otg_module_params.i2c_enable, int, 0444); ++MODULE_PARM_DESC(i2c_enable, "FS PHY Interface"); ++module_param_named(ulpi_fs_ls, dwc_otg_module_params.ulpi_fs_ls, int, 0444); ++MODULE_PARM_DESC(ulpi_fs_ls, "ULPI PHY FS/LS mode only"); ++module_param_named(ts_dline, dwc_otg_module_params.ts_dline, int, 0444); ++MODULE_PARM_DESC(ts_dline, "Term select Dline pulsing for all PHYs"); ++module_param_named(debug, g_dbg_lvl, int, 0444); ++MODULE_PARM_DESC(debug, ""); ++ ++module_param_named(en_multiple_tx_fifo, ++ dwc_otg_module_params.en_multiple_tx_fifo, int, 0444); ++MODULE_PARM_DESC(en_multiple_tx_fifo, ++ "Dedicated Non Periodic Tx FIFOs 0=disabled 1=enabled"); ++module_param_named(dev_tx_fifo_size_1, ++ dwc_otg_module_params.dev_tx_fifo_size[0], int, 0444); ++MODULE_PARM_DESC(dev_tx_fifo_size_1, "Number of words in the Tx FIFO 4-768"); ++module_param_named(dev_tx_fifo_size_2, ++ dwc_otg_module_params.dev_tx_fifo_size[1], int, 0444); ++MODULE_PARM_DESC(dev_tx_fifo_size_2, "Number of words in the Tx FIFO 4-768"); ++module_param_named(dev_tx_fifo_size_3, ++ dwc_otg_module_params.dev_tx_fifo_size[2], int, 0444); ++MODULE_PARM_DESC(dev_tx_fifo_size_3, "Number of words in the Tx FIFO 4-768"); ++module_param_named(dev_tx_fifo_size_4, ++ dwc_otg_module_params.dev_tx_fifo_size[3], int, 0444); ++MODULE_PARM_DESC(dev_tx_fifo_size_4, "Number of words in the Tx FIFO 4-768"); ++module_param_named(dev_tx_fifo_size_5, ++ dwc_otg_module_params.dev_tx_fifo_size[4], int, 0444); ++MODULE_PARM_DESC(dev_tx_fifo_size_5, "Number of words in the Tx FIFO 4-768"); ++module_param_named(dev_tx_fifo_size_6, ++ dwc_otg_module_params.dev_tx_fifo_size[5], int, 0444); ++MODULE_PARM_DESC(dev_tx_fifo_size_6, "Number of words in the Tx FIFO 4-768"); ++module_param_named(dev_tx_fifo_size_7, ++ dwc_otg_module_params.dev_tx_fifo_size[6], int, 0444); ++MODULE_PARM_DESC(dev_tx_fifo_size_7, "Number of words in the Tx FIFO 4-768"); ++module_param_named(dev_tx_fifo_size_8, ++ dwc_otg_module_params.dev_tx_fifo_size[7], int, 0444); ++MODULE_PARM_DESC(dev_tx_fifo_size_8, "Number of words in the Tx FIFO 4-768"); ++module_param_named(dev_tx_fifo_size_9, ++ dwc_otg_module_params.dev_tx_fifo_size[8], int, 0444); ++MODULE_PARM_DESC(dev_tx_fifo_size_9, "Number of words in the Tx FIFO 4-768"); ++module_param_named(dev_tx_fifo_size_10, ++ dwc_otg_module_params.dev_tx_fifo_size[9], int, 0444); ++MODULE_PARM_DESC(dev_tx_fifo_size_10, "Number of words in the Tx FIFO 4-768"); ++module_param_named(dev_tx_fifo_size_11, ++ dwc_otg_module_params.dev_tx_fifo_size[10], int, 0444); ++MODULE_PARM_DESC(dev_tx_fifo_size_11, "Number of words in the Tx FIFO 4-768"); ++module_param_named(dev_tx_fifo_size_12, ++ dwc_otg_module_params.dev_tx_fifo_size[11], int, 0444); ++MODULE_PARM_DESC(dev_tx_fifo_size_12, "Number of words in the Tx FIFO 4-768"); ++module_param_named(dev_tx_fifo_size_13, ++ dwc_otg_module_params.dev_tx_fifo_size[12], int, 0444); ++MODULE_PARM_DESC(dev_tx_fifo_size_13, "Number of words in the Tx FIFO 4-768"); ++module_param_named(dev_tx_fifo_size_14, ++ dwc_otg_module_params.dev_tx_fifo_size[13], int, 0444); ++MODULE_PARM_DESC(dev_tx_fifo_size_14, "Number of words in the Tx FIFO 4-768"); ++module_param_named(dev_tx_fifo_size_15, ++ dwc_otg_module_params.dev_tx_fifo_size[14], int, 0444); ++MODULE_PARM_DESC(dev_tx_fifo_size_15, "Number of words in the Tx FIFO 4-768"); ++ ++module_param_named(thr_ctl, dwc_otg_module_params.thr_ctl, int, 0444); ++MODULE_PARM_DESC(thr_ctl, ++ "Thresholding enable flag bit 0 - non ISO Tx thr., 1 - ISO Tx thr., 2 - Rx thr.- bit 0=disabled 1=enabled"); ++module_param_named(tx_thr_length, dwc_otg_module_params.tx_thr_length, int, ++ 0444); ++MODULE_PARM_DESC(tx_thr_length, "Tx Threshold length in 32 bit DWORDs"); ++module_param_named(rx_thr_length, dwc_otg_module_params.rx_thr_length, int, ++ 0444); ++MODULE_PARM_DESC(rx_thr_length, "Rx Threshold length in 32 bit DWORDs"); ++ ++module_param_named(pti_enable, dwc_otg_module_params.pti_enable, int, 0444); ++module_param_named(mpi_enable, dwc_otg_module_params.mpi_enable, int, 0444); ++module_param_named(lpm_enable, dwc_otg_module_params.lpm_enable, int, 0444); ++MODULE_PARM_DESC(lpm_enable, "LPM Enable 0=LPM Disabled 1=LPM Enabled"); ++module_param_named(ic_usb_cap, dwc_otg_module_params.ic_usb_cap, int, 0444); ++MODULE_PARM_DESC(ic_usb_cap, ++ "IC_USB Capability 0=IC_USB Disabled 1=IC_USB Enabled"); ++module_param_named(ahb_thr_ratio, dwc_otg_module_params.ahb_thr_ratio, int, 0444); ++MODULE_PARM_DESC(ahb_thr_ratio, "AHB Threshold Ratio"); ++ ++/** @page "Module Parameters" ++ * ++ * The following parameters may be specified when starting the module. ++ * These parameters define how the DWC_otg controller should be ++ * configured. Parameter values are passed to the CIL initialization ++ * function dwc_otg_cil_init ++ * ++ * Example: modprobe dwc_otg speed=1 otg_cap=1 ++ * ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++*/ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_driver.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_driver.h 2013-07-26 19:31:23.000000000 +0000 +@@ -0,0 +1,101 @@ ++/* ========================================================================== ++ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_driver.h $ ++ * $Revision: #16 $ ++ * $Date: 2009/04/03 $ ++ * $Change: 1225160 $ ++ * ++ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, ++ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless ++ * otherwise expressly agreed to in writing between Synopsys and you. ++ * ++ * The Software IS NOT an item of Licensed Software or Licensed Product under ++ * any End User Software License Agreement or Agreement for Licensed Product ++ * with Synopsys or any supplement thereto. You are permitted to use and ++ * redistribute this Software in source and binary forms, with or without ++ * modification, provided that redistributions of source code must retain this ++ * notice. You may not view, use, disclose, copy or distribute this file or ++ * any information contained herein except pursuant to this license grant from ++ * Synopsys. If you do not agree with this notice, including the disclaimer ++ * below, then you are not authorized to use the Software. ++ * ++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, ++ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR ++ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER ++ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY ++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH ++ * DAMAGE. ++ * ========================================================================== */ ++ ++#ifndef __DWC_OTG_DRIVER_H__ ++#define __DWC_OTG_DRIVER_H__ ++ ++/** @file ++ * This file contains the interface to the Linux driver. ++ */ ++#include "dwc_otg_core_if.h" ++ ++/* Type declarations */ ++struct dwc_otg_pcd; ++struct dwc_otg_hcd; ++ ++#ifdef PCI_INTERFACE ++#include ++#endif ++ ++ ++ ++/** ++ * This structure is a wrapper that encapsulates the driver components used to ++ * manage a single DWC_otg controller. ++ */ ++typedef struct dwc_otg_device { ++ /** Base address returned from ioremap() */ ++ void *base; ++ ++#ifdef LM_INTERFACE ++ struct lm_device *lmdev; ++#elif defined(PCI_INTERFACE) ++ int rsrc_start; ++ int rsrc_len; ++#elif defined(PLATFORM_INTERFACE) ++ struct platform_device *platformdev; ++#endif ++ ++ /** Pointer to the core interface structure. */ ++ dwc_otg_core_if_t *core_if; ++ ++ /** Register offset for Diagnostic API. */ ++ uint32_t reg_offset; ++ ++ /** Pointer to the PCD structure. */ ++ struct dwc_otg_pcd *pcd; ++ ++ /** Pointer to the HCD structure. */ ++ struct dwc_otg_hcd *hcd; ++ ++ /** Flag to indicate whether the common IRQ handler is installed. */ ++ uint8_t common_irq_installed; ++ ++} dwc_otg_device_t; ++ ++/*We must clear S3C24XX_EINTPEND external interrupt register ++ * because after clearing in this register trigerred IRQ from ++ * H/W core in kernel interrupt can be occured again before OTG ++ * handlers clear all IRQ sources of Core registers because of ++ * timing latencies and Low Level IRQ Type. ++ */ ++#ifdef CONFIG_MACH_IPMATE ++#define S3C2410X_CLEAR_EINTPEND() \ ++do { \ ++ __raw_writel(1UL << 11,S3C24XX_EINTPEND); \ ++} while (0) ++#else ++#define S3C2410X_CLEAR_EINTPEND() do { } while (0) ++#endif ++ ++#endif +Index: linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_hcd.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_hcd.c 2013-07-26 19:31:23.000000000 +0000 +@@ -0,0 +1,3330 @@ ++ ++/* ========================================================================== ++ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd.c $ ++ * $Revision: #87 $ ++ * $Date: 2009/04/23 $ ++ * $Change: 1239143 $ ++ * ++ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, ++ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless ++ * otherwise expressly agreed to in writing between Synopsys and you. ++ * ++ * The Software IS NOT an item of Licensed Software or Licensed Product under ++ * any End User Software License Agreement or Agreement for Licensed Product ++ * with Synopsys or any supplement thereto. You are permitted to use and ++ * redistribute this Software in source and binary forms, with or without ++ * modification, provided that redistributions of source code must retain this ++ * notice. You may not view, use, disclose, copy or distribute this file or ++ * any information contained herein except pursuant to this license grant from ++ * Synopsys. If you do not agree with this notice, including the disclaimer ++ * below, then you are not authorized to use the Software. ++ * ++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, ++ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR ++ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER ++ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY ++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH ++ * DAMAGE. ++ * ========================================================================== */ ++#ifndef DWC_DEVICE_ONLY ++ ++/** @file ++ * This file implements HCD Core. All code in this file is portable and don't ++ * use any OS specific functions. ++ * Interface provided by HCD Core is defined in ++ * header file. ++ */ ++ ++#include "dwc_otg_hcd.h" ++#include "dwc_otg_regs.h" ++ ++#ifdef HW2937_WORKAROUND ++//#include ++#include ++#endif ++ ++dwc_otg_hcd_t *dwc_otg_hcd_alloc_hcd(void) ++{ ++ return dwc_alloc(sizeof(dwc_otg_hcd_t)); ++} ++ ++/** ++ * Connection timeout function. An OTG host is required to display a ++ * message if the device does not connect within 10 seconds. ++ */ ++void dwc_otg_hcd_connect_timeout(void *ptr) ++{ ++ DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, ptr); ++ DWC_PRINTF("Connect Timeout\n"); ++ __DWC_ERROR("Device Not Connected/Responding\n"); ++} ++ ++#ifdef DEBUG ++static void dump_channel_info(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh) ++{ ++ if (qh->channel != NULL) { ++ dwc_hc_t *hc = qh->channel; ++ dwc_list_link_t *item; ++ dwc_otg_qh_t *qh_item; ++ int num_channels = hcd->core_if->core_params->host_channels; ++ int i; ++ ++ dwc_otg_hc_regs_t *hc_regs; ++ hcchar_data_t hcchar; ++ hcsplt_data_t hcsplt; ++ hctsiz_data_t hctsiz; ++ uint32_t hcdma; ++ ++ hc_regs = hcd->core_if->host_if->hc_regs[hc->hc_num]; ++ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); ++ hcsplt.d32 = dwc_read_reg32(&hc_regs->hcsplt); ++ hctsiz.d32 = dwc_read_reg32(&hc_regs->hctsiz); ++ hcdma = dwc_read_reg32(&hc_regs->hcdma); ++ ++ DWC_PRINTF(" Assigned to channel %p:\n", hc); ++ DWC_PRINTF(" hcchar 0x%08x, hcsplt 0x%08x\n", hcchar.d32, ++ hcsplt.d32); ++ DWC_PRINTF(" hctsiz 0x%08x, hcdma 0x%08x\n", hctsiz.d32, ++ hcdma); ++ DWC_PRINTF(" dev_addr: %d, ep_num: %d, ep_is_in: %d\n", ++ hc->dev_addr, hc->ep_num, hc->ep_is_in); ++ DWC_PRINTF(" ep_type: %d\n", hc->ep_type); ++ DWC_PRINTF(" max_packet: %d\n", hc->max_packet); ++ DWC_PRINTF(" data_pid_start: %d\n", hc->data_pid_start); ++ DWC_PRINTF(" xfer_started: %d\n", hc->xfer_started); ++ DWC_PRINTF(" halt_status: %d\n", hc->halt_status); ++ DWC_PRINTF(" xfer_buff: %p\n", hc->xfer_buff); ++ DWC_PRINTF(" xfer_len: %d\n", hc->xfer_len); ++ DWC_PRINTF(" qh: %p\n", hc->qh); ++ DWC_PRINTF(" NP inactive sched:\n"); ++ DWC_LIST_FOREACH(item, &hcd->non_periodic_sched_inactive) { ++ qh_item = ++ DWC_LIST_ENTRY(item, dwc_otg_qh_t, qh_list_entry); ++ DWC_PRINTF(" %p\n", qh_item); ++ } ++ DWC_PRINTF(" NP active sched:\n"); ++ DWC_LIST_FOREACH(item, &hcd->non_periodic_sched_active) { ++ qh_item = ++ DWC_LIST_ENTRY(item, dwc_otg_qh_t, qh_list_entry); ++ DWC_PRINTF(" %p\n", qh_item); ++ } ++ DWC_PRINTF(" Channels: \n"); ++ for (i = 0; i < num_channels; i++) { ++ dwc_hc_t *hc = hcd->hc_ptr_array[i]; ++ DWC_PRINTF(" %2d: %p\n", i, hc); ++ } ++ } ++} ++#endif /* DEBUG */ ++ ++/** ++ * Work queue function for starting the HCD when A-Cable is connected. ++ * The hcd_start() must be called in a process context. ++ */ ++static void hcd_start_func(void *_vp) ++{ ++ dwc_otg_hcd_t *hcd = (dwc_otg_hcd_t *) _vp; ++ ++ DWC_DEBUGPL(DBG_HCDV, "%s() %p\n", __func__, hcd); ++ if (hcd) { ++ hcd->fops->start(hcd); ++ } ++} ++ ++static void del_xfer_timers(dwc_otg_hcd_t * hcd) ++{ ++#ifdef DEBUG ++ int i; ++ int num_channels = hcd->core_if->core_params->host_channels; ++ for (i = 0; i < num_channels; i++) { ++ DWC_TIMER_CANCEL(hcd->core_if->hc_xfer_timer[i]); ++ } ++#endif ++} ++ ++static void del_timers(dwc_otg_hcd_t * hcd) ++{ ++ del_xfer_timers(hcd); ++ DWC_TIMER_CANCEL(hcd->conn_timer); ++} ++ ++/** ++ * Processes all the URBs in a single list of QHs. Completes them with ++ * -ETIMEDOUT and frees the QTD. ++ */ ++static void kill_urbs_in_qh_list(dwc_otg_hcd_t * hcd, dwc_list_link_t * qh_list) ++{ ++ dwc_list_link_t *qh_item; ++ dwc_otg_qh_t *qh; ++ dwc_otg_qtd_t *qtd, *qtd_tmp; ++ ++ DWC_LIST_FOREACH(qh_item, qh_list) { ++ qh = DWC_LIST_ENTRY(qh_item, dwc_otg_qh_t, qh_list_entry); ++ DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp, ++ &qh->qtd_list, qtd_list_entry) { ++ qtd = DWC_CIRCLEQ_FIRST(&qh->qtd_list); ++ if (qtd->urb != NULL) { ++ hcd->fops->complete(hcd, qtd->urb->priv, ++ qtd->urb, ++ -DWC_E_TIMEOUT); ++ dwc_otg_hcd_qtd_remove_and_free(hcd, qtd, qh); ++ } ++ ++ } ++ } ++} ++ ++/** ++ * Responds with an error status of ETIMEDOUT to all URBs in the non-periodic ++ * and periodic schedules. The QTD associated with each URB is removed from ++ * the schedule and freed. This function may be called when a disconnect is ++ * detected or when the HCD is being stopped. ++ */ ++static void kill_all_urbs(dwc_otg_hcd_t * hcd) ++{ ++ kill_urbs_in_qh_list(hcd, &hcd->non_periodic_sched_inactive); ++ kill_urbs_in_qh_list(hcd, &hcd->non_periodic_sched_active); ++ kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_inactive); ++ kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_ready); ++ kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_assigned); ++ kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_queued); ++} ++ ++/** ++ * Start the connection timer. An OTG host is required to display a ++ * message if the device does not connect within 10 seconds. The ++ * timer is deleted if a port connect interrupt occurs before the ++ * timer expires. ++ */ ++static void dwc_otg_hcd_start_connect_timer(dwc_otg_hcd_t * hcd) ++{ ++ DWC_TIMER_SCHEDULE(hcd->conn_timer, 10000 /* 10 secs */ ); ++} ++ ++/** ++ * HCD Callback function for disconnect of the HCD. ++ * ++ * @param p void pointer to the struct usb_hcd ++ */ ++static int32_t dwc_otg_hcd_session_start_cb(void *p) ++{ ++ dwc_otg_hcd_t *dwc_otg_hcd; ++ DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, p); ++ dwc_otg_hcd = p; ++ dwc_otg_hcd_start_connect_timer(dwc_otg_hcd); ++ return 1; ++} ++ ++/** ++ * HCD Callback function for starting the HCD when A-Cable is ++ * connected. ++ * ++ * @param p void pointer to the struct usb_hcd ++ */ ++static int32_t dwc_otg_hcd_start_cb(void *p) ++{ ++ dwc_otg_hcd_t *dwc_otg_hcd = p; ++ dwc_otg_core_if_t *core_if; ++ hprt0_data_t hprt0; ++ ++ core_if = dwc_otg_hcd->core_if; ++ ++ if (core_if->op_state == B_HOST) { ++ /* ++ * Reset the port. During a HNP mode switch the reset ++ * needs to occur within 1ms and have a duration of at ++ * least 50ms. ++ */ ++ hprt0.d32 = dwc_otg_read_hprt0(core_if); ++ hprt0.b.prtrst = 1; ++ dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32); ++ } ++ DWC_WORKQ_SCHEDULE_DELAYED(core_if->wq_otg, ++ hcd_start_func, dwc_otg_hcd, 50, ++ "start hcd"); ++ ++ return 1; ++} ++ ++/** ++ * HCD Callback function for disconnect of the HCD. ++ * ++ * @param p void pointer to the struct usb_hcd ++ */ ++static int32_t dwc_otg_hcd_disconnect_cb(void *p) ++{ ++ gintsts_data_t intr; ++ dwc_otg_hcd_t *dwc_otg_hcd = p; ++ ++ /* ++ * Set status flags for the hub driver. ++ */ ++ dwc_otg_hcd->flags.b.port_connect_status_change = 1; ++ dwc_otg_hcd->flags.b.port_connect_status = 0; ++ ++ /* ++ * Shutdown any transfers in process by clearing the Tx FIFO Empty ++ * interrupt mask and status bits and disabling subsequent host ++ * channel interrupts. ++ */ ++ intr.d32 = 0; ++ intr.b.nptxfempty = 1; ++ intr.b.ptxfempty = 1; ++ intr.b.hcintr = 1; ++ dwc_modify_reg32(&dwc_otg_hcd->core_if->core_global_regs->gintmsk, ++ intr.d32, 0); ++ dwc_modify_reg32(&dwc_otg_hcd->core_if->core_global_regs->gintsts, ++ intr.d32, 0); ++ ++ del_timers(dwc_otg_hcd); ++ ++ /* ++ * Turn off the vbus power only if the core has transitioned to device ++ * mode. If still in host mode, need to keep power on to detect a ++ * reconnection. ++ */ ++ if (dwc_otg_is_device_mode(dwc_otg_hcd->core_if)) { ++ if (dwc_otg_hcd->core_if->op_state != A_SUSPEND) { ++ hprt0_data_t hprt0 = {.d32 = 0 }; ++ DWC_PRINTF("Disconnect: PortPower off\n"); ++ hprt0.b.prtpwr = 0; ++ dwc_write_reg32(dwc_otg_hcd->core_if->host_if->hprt0, ++ hprt0.d32); ++ } ++ ++ dwc_otg_disable_host_interrupts(dwc_otg_hcd->core_if); ++ } ++ ++ /* Respond with an error status to all URBs in the schedule. */ ++ kill_all_urbs(dwc_otg_hcd); ++ ++ if (dwc_otg_is_host_mode(dwc_otg_hcd->core_if)) { ++ /* Clean up any host channels that were in use. */ ++ int num_channels; ++ int i; ++ dwc_hc_t *channel; ++ dwc_otg_hc_regs_t *hc_regs; ++ hcchar_data_t hcchar; ++ ++ num_channels = dwc_otg_hcd->core_if->core_params->host_channels; ++ ++ if (!dwc_otg_hcd->core_if->dma_enable) { ++ /* Flush out any channel requests in slave mode. */ ++ for (i = 0; i < num_channels; i++) { ++ channel = dwc_otg_hcd->hc_ptr_array[i]; ++ if (DWC_CIRCLEQ_EMPTY_ENTRY ++ (channel, hc_list_entry)) { ++ hc_regs = ++ dwc_otg_hcd->core_if->host_if-> ++ hc_regs[i]; ++ hcchar.d32 = ++ dwc_read_reg32(&hc_regs->hcchar); ++ if (hcchar.b.chen) { ++ hcchar.b.chen = 0; ++ hcchar.b.chdis = 1; ++ hcchar.b.epdir = 0; ++ dwc_write_reg32(&hc_regs-> ++ hcchar, ++ hcchar.d32); ++ } ++ } ++ } ++ } ++ ++ for (i = 0; i < num_channels; i++) { ++ channel = dwc_otg_hcd->hc_ptr_array[i]; ++ if (DWC_CIRCLEQ_EMPTY_ENTRY(channel, hc_list_entry)) { ++ hc_regs = ++ dwc_otg_hcd->core_if->host_if->hc_regs[i]; ++ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); ++ if (hcchar.b.chen) { ++ /* Halt the channel. */ ++ hcchar.b.chdis = 1; ++ dwc_write_reg32(&hc_regs->hcchar, ++ hcchar.d32); ++ } ++ ++ dwc_otg_hc_cleanup(dwc_otg_hcd->core_if, ++ channel); ++ DWC_CIRCLEQ_INSERT_TAIL(&dwc_otg_hcd-> ++ free_hc_list, channel, ++ hc_list_entry); ++ /* ++ * Added for Descriptor DMA to prevent channel double cleanup ++ * in release_channel_ddma(). Which called from ep_disable ++ * when device disconnect. ++ */ ++ channel->qh = NULL; ++ } ++ } ++ } ++ ++ if (dwc_otg_hcd->fops->disconnect) { ++ dwc_otg_hcd->fops->disconnect(dwc_otg_hcd); ++ } ++ ++ return 1; ++} ++ ++/** ++ * HCD Callback function for stopping the HCD. ++ * ++ * @param p void pointer to the struct usb_hcd ++ */ ++static int32_t dwc_otg_hcd_stop_cb(void *p) ++{ ++ dwc_otg_hcd_t *dwc_otg_hcd = p; ++ ++ DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, p); ++ dwc_otg_hcd_stop(dwc_otg_hcd); ++ return 1; ++} ++ ++#ifdef CONFIG_USB_DWC_OTG_LPM ++/** ++ * HCD Callback function for sleep of HCD. ++ * ++ * @param p void pointer to the struct usb_hcd ++ */ ++static int dwc_otg_hcd_sleep_cb(void *p) ++{ ++ dwc_otg_hcd_t *hcd = p; ++ ++ dwc_otg_hcd_free_hc_from_lpm(hcd); ++ ++ return 0; ++} ++#endif ++ ++/** ++ * HCD Callback function for Remote Wakeup. ++ * ++ * @param p void pointer to the struct usb_hcd ++ */ ++static int dwc_otg_hcd_rem_wakeup_cb(void *p) ++{ ++ dwc_otg_hcd_t *hcd = p; ++ ++ if (hcd->core_if->lx_state == DWC_OTG_L2) { ++ hcd->flags.b.port_suspend_change = 1; ++ } ++#ifdef CONFIG_USB_DWC_OTG_LPM ++ else { ++ hcd->flags.b.port_l1_change = 1; ++ } ++#endif ++ return 0; ++} ++ ++/** ++ * Halts the DWC_otg host mode operations in a clean manner. USB transfers are ++ * stopped. ++ */ ++void dwc_otg_hcd_stop(dwc_otg_hcd_t * hcd) ++{ ++ hprt0_data_t hprt0 = {.d32 = 0 }; ++ ++ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD STOP\n"); ++ ++ /* ++ * The root hub should be disconnected before this function is called. ++ * The disconnect will clear the QTD lists (via ..._hcd_urb_dequeue) ++ * and the QH lists (via ..._hcd_endpoint_disable). ++ */ ++ ++ /* Turn off all host-specific interrupts. */ ++ dwc_otg_disable_host_interrupts(hcd->core_if); ++ ++ /* Turn off the vbus power */ ++ DWC_PRINTF("PortPower off\n"); ++ hprt0.b.prtpwr = 0; ++ dwc_write_reg32(hcd->core_if->host_if->hprt0, hprt0.d32); ++ dwc_mdelay(1); ++} ++ ++int dwc_otg_hcd_urb_enqueue(dwc_otg_hcd_t * hcd, ++ dwc_otg_hcd_urb_t * dwc_otg_urb, void **ep_handle) ++{ ++ uint64_t flags; ++ int retval = 0; ++ dwc_otg_qtd_t *qtd; ++ ++ if (NULL == hcd->core_if) { //GRAYG ++ DWC_ERROR("**** DWC OTG HCD URB Enqueue - HCD has NULL core_if\n"); ++ /* No longer connected. */ ++ return -DWC_E_INVALID; ++ } ++ ++ if (!hcd->flags.b.port_connect_status) { ++ /* No longer connected. */ ++ return -DWC_E_NO_DEVICE; ++ } ++ ++ qtd = dwc_otg_hcd_qtd_create(dwc_otg_urb); ++ if (qtd == NULL) { ++ DWC_ERROR("DWC OTG HCD URB Enqueue failed creating QTD\n"); ++ return -DWC_E_NO_MEMORY; ++ } ++ if (qtd->urb == NULL) { //GRAYG ++ DWC_ERROR("**** DWC OTG HCD URB Enqueue created QTD with no URBs\n"); ++ return -DWC_E_NO_MEMORY; ++ } ++ if (qtd->urb->priv == NULL) { //GRAYG ++ DWC_ERROR("**** DWC OTG HCD URB Enqueue created QTD URB with no URB handle\n"); ++ return -DWC_E_NO_MEMORY; ++ } ++ ++ retval = ++ dwc_otg_hcd_qtd_add(qtd, hcd, (dwc_otg_qh_t **) ep_handle); ++ // creates a new queue in ep_handle if it doesn't exist already ++ if (retval < 0) { ++ DWC_ERROR("DWC OTG HCD URB Enqueue failed adding QTD. " ++ "Error status %d\n", retval); ++ dwc_otg_hcd_qtd_free(qtd); ++ } else { ++ qtd->qh = *ep_handle; ++ } ++ ++ if (hcd->core_if->dma_desc_enable && retval == 0) { ++ dwc_otg_transaction_type_e tr_type; ++ if ((qtd->qh->ep_type == UE_BULK) && !(qtd->urb->flags & URB_GIVEBACK_ASAP)) { ++ /* Do not schedule SG transcations until qtd has URB_GIVEBACK_ASAP set */ ++ return 0; ++ } ++ DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags); ++ tr_type = dwc_otg_hcd_select_transactions(hcd); ++ if (tr_type != DWC_OTG_TRANSACTION_NONE) { ++ dwc_otg_hcd_queue_transactions(hcd, tr_type); ++ } ++ DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags); ++ } ++ ++ return retval; ++} ++ ++int dwc_otg_hcd_urb_dequeue(dwc_otg_hcd_t * hcd, ++ dwc_otg_hcd_urb_t * dwc_otg_urb) ++{ ++ uint64_t flags; ++ ++ dwc_otg_qh_t *qh; ++ dwc_otg_qtd_t *urb_qtd; ++ ++ DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags); ++ ++ if (hcd == NULL) { //GRAYG ++ DWC_ERROR("**** DWC OTG HCD URB Dequeue has NULL HCD\n"); ++ return -DWC_E_INVALID; ++ } ++ if (dwc_otg_urb == NULL) { //GRAYG ++ DWC_ERROR("**** DWC OTG HCD URB Dequeue has NULL URB\n"); ++ return -DWC_E_INVALID; ++ } ++ if (dwc_otg_urb->qtd == NULL) { //GRAYG ++ DWC_ERROR("**** DWC OTG HCD URB Dequeue with NULL QTD\n"); ++ return -DWC_E_INVALID; ++ } ++ urb_qtd = dwc_otg_urb->qtd; ++ if (urb_qtd->qh == NULL) { //GRAYG ++ DWC_ERROR("**** DWC OTG HCD URB Dequeue with QTD with NULL Q handler\n"); ++ return -DWC_E_INVALID; ++ } ++ qh = urb_qtd->qh; ++#ifdef DEBUG ++ if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) { ++ if (urb_qtd->in_process) { ++ dump_channel_info(hcd, qh); ++ } ++ } ++#endif ++ if (hcd->core_if == NULL) { //GRAYG ++ DWC_ERROR("**** DWC OTG HCD URB Dequeue HCD has NULL core_if\n"); ++ return -DWC_E_INVALID; ++ } ++ if (urb_qtd->in_process && qh->channel) { ++ /* The QTD is in process (it has been assigned to a channel). */ ++ if (hcd->flags.b.port_connect_status) { ++ /* ++ * If still connected (i.e. in host mode), halt the ++ * channel so it can be used for other transfers. If ++ * no longer connected, the host registers can't be ++ * written to halt the channel since the core is in ++ * device mode. ++ */ ++ dwc_otg_hc_halt(hcd->core_if, qh->channel, ++ DWC_OTG_HC_XFER_URB_DEQUEUE); ++ } ++ } ++ ++ /* ++ * Free the QTD and clean up the associated QH. Leave the QH in the ++ * schedule if it has any remaining QTDs. ++ */ ++ ++ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD URB Dequeue - " ++ "delete %sQueue handler\n", ++ hcd->core_if->dma_desc_enable?"DMA ":""); //GRAYG ++ if (!hcd->core_if->dma_desc_enable) { ++ uint8_t b = urb_qtd->in_process; ++ dwc_otg_hcd_qtd_remove_and_free(hcd, urb_qtd, qh); ++ if (b) { ++ dwc_otg_hcd_qh_deactivate(hcd, qh, 0); ++ qh->channel = NULL; ++ } else if (DWC_CIRCLEQ_EMPTY(&qh->qtd_list)) { ++ dwc_otg_hcd_qh_remove(hcd, qh); ++ } ++ } ++ else { ++ dwc_otg_hcd_qtd_remove_and_free(hcd, urb_qtd, qh); ++ } ++ ++ DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags); ++ ++ return 0; ++} ++ ++int dwc_otg_hcd_endpoint_disable(dwc_otg_hcd_t * hcd, void *ep_handle, ++ int retry) ++{ ++ dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle; ++ int retval = 0; ++ uint64_t flags; ++ ++ if (retry < 0) { ++ retval = -DWC_E_INVALID; ++ goto done; ++ } ++ ++ if (!qh) { ++ goto done; ++ } ++ ++ DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags); ++ ++ while (!DWC_CIRCLEQ_EMPTY(&qh->qtd_list) && retry) { ++ DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags); ++ retry--; ++ dwc_msleep(5); ++ DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags); ++ } ++ ++ dwc_otg_hcd_qh_remove(hcd, qh); ++ ++ DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags); ++ /* ++ * Split dwc_otg_hcd_qh_remove_and_free() into qh_remove ++ * and qh_free to prevent stack dump on dwc_dma_free() with ++ * irq_disabled (spinlock_irqsave) in dwc_otg_hcd_desc_list_free() ++ * and dwc_otg_hcd_frame_list_alloc(). ++ */ ++ dwc_otg_hcd_qh_free(hcd, qh); ++ ++ done: ++ return retval; ++} ++ ++/** ++ * HCD Callback structure for handling mode switching. ++ */ ++static dwc_otg_cil_callbacks_t hcd_cil_callbacks = { ++ .start = dwc_otg_hcd_start_cb, ++ .stop = dwc_otg_hcd_stop_cb, ++ .disconnect = dwc_otg_hcd_disconnect_cb, ++ .session_start = dwc_otg_hcd_session_start_cb, ++ .resume_wakeup = dwc_otg_hcd_rem_wakeup_cb, ++#ifdef CONFIG_USB_DWC_OTG_LPM ++ .sleep = dwc_otg_hcd_sleep_cb, ++#endif ++ .p = 0, ++}; ++ ++/** ++ * Reset tasklet function ++ */ ++static void reset_tasklet_func(void *data) ++{ ++ dwc_otg_hcd_t *dwc_otg_hcd = (dwc_otg_hcd_t *) data; ++ dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if; ++ hprt0_data_t hprt0; ++ ++ DWC_DEBUGPL(DBG_HCDV, "USB RESET tasklet called\n"); ++ ++ hprt0.d32 = dwc_otg_read_hprt0(core_if); ++ hprt0.b.prtrst = 1; ++ dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32); ++ dwc_mdelay(60); ++ ++ hprt0.b.prtrst = 0; ++ dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32); ++ dwc_otg_hcd->flags.b.port_reset_change = 1; ++} ++ ++static void qh_list_free(dwc_otg_hcd_t * hcd, dwc_list_link_t * qh_list) ++{ ++ dwc_list_link_t *item; ++ dwc_otg_qh_t *qh; ++ ++ if (!qh_list->next) { ++ /* The list hasn't been initialized yet. */ ++ return; ++ } ++ ++ /* Ensure there are no QTDs or URBs left. */ ++ kill_urbs_in_qh_list(hcd, qh_list); ++ ++ DWC_LIST_FOREACH(item, qh_list) { ++ qh = DWC_LIST_ENTRY(item, dwc_otg_qh_t, qh_list_entry); ++ dwc_otg_hcd_qh_remove_and_free(hcd, qh); ++ } ++} ++ ++/** ++ * Frees secondary storage associated with the dwc_otg_hcd structure contained ++ * in the struct usb_hcd field. ++ */ ++static void dwc_otg_hcd_free(dwc_otg_hcd_t * dwc_otg_hcd) ++{ ++ int i; ++ ++ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD FREE\n"); ++ ++ del_timers(dwc_otg_hcd); ++ ++ /* Free memory for QH/QTD lists */ ++ qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->non_periodic_sched_inactive); ++ qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->non_periodic_sched_active); ++ qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_inactive); ++ qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_ready); ++ qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_assigned); ++ qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_queued); ++ ++ /* Free memory for the host channels. */ ++ for (i = 0; i < MAX_EPS_CHANNELS; i++) { ++ dwc_hc_t *hc = dwc_otg_hcd->hc_ptr_array[i]; ++ ++#ifdef DEBUG ++ if (dwc_otg_hcd->core_if->hc_xfer_timer[i]) { ++ DWC_TIMER_FREE(dwc_otg_hcd->core_if->hc_xfer_timer[i]); ++ } ++#endif ++ if (hc != NULL) { ++ DWC_DEBUGPL(DBG_HCDV, "HCD Free channel #%i, hc=%p\n", ++ i, hc); ++ dwc_free(hc); ++ } ++ } ++ ++ if (dwc_otg_hcd->core_if->dma_enable) { ++ if (dwc_otg_hcd->status_buf_dma) { ++ dwc_dma_free(DWC_OTG_HCD_STATUS_BUF_SIZE, ++ dwc_otg_hcd->status_buf, ++ dwc_otg_hcd->status_buf_dma); ++ } ++ } else if (dwc_otg_hcd->status_buf != NULL) { ++ dwc_free(dwc_otg_hcd->status_buf); ++ } ++ DWC_SPINLOCK_FREE(dwc_otg_hcd->lock); ++ DWC_TIMER_FREE(dwc_otg_hcd->conn_timer); ++ DWC_TASK_FREE(dwc_otg_hcd->reset_tasklet); ++ dwc_free(dwc_otg_hcd); ++} ++ ++int dwc_otg_hcd_init(dwc_otg_hcd_t * hcd, dwc_otg_core_if_t * core_if) ++{ ++ int retval = 0; ++ int num_channels; ++ int i; ++ dwc_hc_t *channel; ++ ++ hcd->lock = DWC_SPINLOCK_ALLOC(); ++ ++ DWC_DEBUGPL(DBG_HCDV, "init of HCD %p given core_if %p\n", ++ hcd, core_if);//GRAYG ++ ++ hcd->core_if = core_if; ++ /* Register the HCD CIL Callbacks */ ++ dwc_otg_cil_register_hcd_callbacks(hcd->core_if, ++ &hcd_cil_callbacks, hcd); ++ ++ /* Initialize the non-periodic schedule. */ ++ DWC_LIST_INIT(&hcd->non_periodic_sched_inactive); ++ DWC_LIST_INIT(&hcd->non_periodic_sched_active); ++ ++ /* Initialize the periodic schedule. */ ++ DWC_LIST_INIT(&hcd->periodic_sched_inactive); ++ DWC_LIST_INIT(&hcd->periodic_sched_ready); ++ DWC_LIST_INIT(&hcd->periodic_sched_assigned); ++ DWC_LIST_INIT(&hcd->periodic_sched_queued); ++ ++ /* ++ * Create a host channel descriptor for each host channel implemented ++ * in the controller. Initialize the channel descriptor array. ++ */ ++ DWC_CIRCLEQ_INIT(&hcd->free_hc_list); ++ num_channels = hcd->core_if->core_params->host_channels; ++ DWC_MEMSET(hcd->hc_ptr_array, 0, sizeof(hcd->hc_ptr_array)); ++ for (i = 0; i < num_channels; i++) { ++ channel = dwc_alloc(sizeof(dwc_hc_t)); ++ if (channel == NULL) { ++ retval = -DWC_E_NO_MEMORY; ++ DWC_ERROR("%s: host channel allocation failed\n", ++ __func__); ++ dwc_otg_hcd_free(hcd); ++ goto out; ++ } ++ channel->hc_num = i; ++ hcd->hc_ptr_array[i] = channel; ++#ifdef DEBUG ++ hcd->core_if->hc_xfer_timer[i] = ++ DWC_TIMER_ALLOC("hc timer", hc_xfer_timeout, ++ &hcd->core_if->hc_xfer_info[i]); ++#endif ++ DWC_DEBUGPL(DBG_HCDV, "HCD Added channel #%d, hc=%p\n", i, ++ channel); ++ } ++ ++ /* Initialize the Connection timeout timer. */ ++ hcd->conn_timer = DWC_TIMER_ALLOC("Connection timer", ++ dwc_otg_hcd_connect_timeout, 0); ++ ++ /* Initialize reset tasklet. */ ++ hcd->reset_tasklet = DWC_TASK_ALLOC(reset_tasklet_func, hcd); ++ ++ /* ++ * Allocate space for storing data on status transactions. Normally no ++ * data is sent, but this space acts as a bit bucket. This must be ++ * done after usb_add_hcd since that function allocates the DMA buffer ++ * pool. ++ */ ++ if (hcd->core_if->dma_enable) { ++ hcd->status_buf = ++ dwc_dma_alloc(DWC_OTG_HCD_STATUS_BUF_SIZE, ++ &hcd->status_buf_dma); ++ } else { ++ hcd->status_buf = dwc_alloc(DWC_OTG_HCD_STATUS_BUF_SIZE); ++ } ++ if (!hcd->status_buf) { ++ retval = -DWC_E_NO_MEMORY; ++ DWC_ERROR("%s: status_buf allocation failed\n", __func__); ++ dwc_otg_hcd_free(hcd); ++ goto out; ++ } ++ ++ hcd->otg_port = 1; ++ hcd->frame_list = NULL; ++ hcd->frame_list_dma = 0; ++ ++#ifdef HW2937_WORKAROUND ++ hcd->hw2937_xfer_mode = HW2937_XFER_MODE_IDLE; ++ hcd->hw2937_assigned_channels = 0; ++#endif ++ ++out: ++ return retval; ++} ++ ++void dwc_otg_hcd_remove(dwc_otg_hcd_t * hcd) ++{ ++ /* Turn off all host-specific interrupts. */ ++ dwc_otg_disable_host_interrupts(hcd->core_if); ++ ++ dwc_otg_hcd_free(hcd); ++} ++ ++/** ++ * Initializes dynamic portions of the DWC_otg HCD state. ++ */ ++static void dwc_otg_hcd_reinit(dwc_otg_hcd_t * hcd) ++{ ++ int num_channels; ++ int i; ++ dwc_hc_t *channel; ++ dwc_hc_t *channel_tmp; ++ ++ hcd->flags.d32 = 0; ++ ++ hcd->non_periodic_qh_ptr = &hcd->non_periodic_sched_active; ++ hcd->non_periodic_channels = 0; ++ hcd->periodic_channels = 0; ++ ++ /* ++ * Put all channels in the free channel list and clean up channel ++ * states. ++ */ ++ DWC_CIRCLEQ_FOREACH_SAFE(channel, channel_tmp, ++ &hcd->free_hc_list, hc_list_entry) { ++ DWC_CIRCLEQ_REMOVE(&hcd->free_hc_list, channel, hc_list_entry); ++ } ++ ++ num_channels = hcd->core_if->core_params->host_channels; ++ for (i = 0; i < num_channels; i++) { ++ channel = hcd->hc_ptr_array[i]; ++ DWC_CIRCLEQ_INSERT_TAIL(&hcd->free_hc_list, channel, ++ hc_list_entry); ++ dwc_otg_hc_cleanup(hcd->core_if, channel); ++ } ++ ++ /* Initialize the DWC core for host mode operation. */ ++ dwc_otg_core_host_init(hcd->core_if); ++} ++ ++/** ++ * Assigns transactions from a QTD to a free host channel and initializes the ++ * host channel to perform the transactions. The host channel is removed from ++ * the free list. ++ * ++ * @param hcd The HCD state structure. ++ * @param qh Transactions from the first QTD for this QH are selected and ++ * assigned to a free host channel. ++ */ ++#ifdef HW2937_WORKAROUND ++static int assign_and_init_hc(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh) ++#else ++static void assign_and_init_hc(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh) ++#endif ++{ ++ dwc_hc_t *hc; ++ dwc_otg_qtd_t *qtd; ++ dwc_otg_hcd_urb_t *urb; ++ void* ptr = NULL; ++#ifdef HW2937_WORKAROUND ++ int ep_is_in; ++#endif ++ ++ qtd = DWC_CIRCLEQ_FIRST(&qh->qtd_list); ++ ++ urb = qtd->urb; ++ ++ DWC_DEBUGPL(DBG_HCDV, "%s(%p,%p) - urb %x, actual_length %d\n", __func__, hcd, qh, (unsigned int)urb, urb->actual_length); ++ ++#ifdef HW2937_WORKAROUND ++ ep_is_in = (dwc_otg_hcd_is_pipe_in(&urb->pipe_info) != 0); ++ if (ep_is_in && ((hcd->hw2937_xfer_mode == HW2937_XFER_MODE_OUT) || ++ (hcd->hw2937_xfer_mode == HW2937_XFER_MODE_PAUSEIN))) ++ return 0; ++#endif ++ ++ hc = DWC_CIRCLEQ_FIRST(&hcd->free_hc_list); ++ ++ /* Remove the host channel from the free list. */ ++ DWC_CIRCLEQ_REMOVE_INIT(&hcd->free_hc_list, hc, hc_list_entry); ++ qh->channel = hc; ++ ++ qtd->in_process = 1; ++ ++ /* ++ * Use usb_pipedevice to determine device address. This address is ++ * 0 before the SET_ADDRESS command and the correct address afterward. ++ */ ++ hc->dev_addr = dwc_otg_hcd_get_dev_addr(&urb->pipe_info); ++ hc->ep_num = dwc_otg_hcd_get_ep_num(&urb->pipe_info); ++ hc->speed = qh->dev_speed; ++ hc->max_packet = dwc_max_packet(qh->maxp); ++ ++ hc->xfer_started = 0; ++ hc->halt_status = DWC_OTG_HC_XFER_NO_HALT_STATUS; ++ hc->error_state = (qtd->error_count > 0); ++ hc->halt_on_queue = 0; ++ hc->halt_pending = 0; ++ hc->requests = 0; ++ ++ /* ++ * The following values may be modified in the transfer type section ++ * below. The xfer_len value may be reduced when the transfer is ++ * started to accommodate the max widths of the XferSize and PktCnt ++ * fields in the HCTSIZn register. ++ */ ++ hc->do_ping = qh->ping_state; ++#ifdef HW2937_WORKAROUND ++ hc->ep_is_in = ep_is_in; ++#else ++ hc->ep_is_in = (dwc_otg_hcd_is_pipe_in(&urb->pipe_info) != 0); ++#endif ++ hc->data_pid_start = qh->data_toggle; ++ hc->multi_count = 1; ++ ++ if (hcd->core_if->dma_enable) { ++ hc->xfer_buff = (uint8_t *) urb->dma + urb->actual_length; ++ ++ /* For non-dword aligned case */ ++ if (((uint32_t)hc->xfer_buff & 0x3) && !hcd->core_if->dma_desc_enable) { ++ ptr = (uint8_t *) urb->buf + urb->actual_length; ++ } ++ } else { ++ hc->xfer_buff = (uint8_t *) urb->buf + urb->actual_length; ++ } ++ hc->xfer_len = urb->length - urb->actual_length; ++ hc->xfer_count = 0; ++ ++ /* ++ * Set the split attributes ++ */ ++ hc->do_split = 0; ++ if (qh->do_split) { ++ uint32_t hub_addr, port_addr; ++ hc->do_split = 1; ++ hc->xact_pos = qtd->isoc_split_pos; ++ hc->complete_split = qtd->complete_split; ++ hcd->fops->hub_info(hcd, urb->priv, &hub_addr, &port_addr); ++ hc->hub_addr = (uint8_t) hub_addr; ++ hc->port_addr = (uint8_t) port_addr; ++ } ++ ++ switch (dwc_otg_hcd_get_pipe_type(&urb->pipe_info)) { ++ case UE_CONTROL: ++ hc->ep_type = DWC_OTG_EP_TYPE_CONTROL; ++ switch (qtd->control_phase) { ++ case DWC_OTG_CONTROL_SETUP: ++ DWC_DEBUGPL(DBG_HCDV, " Control setup transaction\n"); ++ hc->do_ping = 0; ++ hc->ep_is_in = 0; ++ hc->data_pid_start = DWC_OTG_HC_PID_SETUP; ++ if (hcd->core_if->dma_enable) { ++ hc->xfer_buff = (uint8_t *) urb->setup_dma; ++ } else { ++ hc->xfer_buff = (uint8_t *) urb->setup_packet; ++ } ++ hc->xfer_len = 8; ++ ptr = NULL; ++ break; ++ case DWC_OTG_CONTROL_DATA: ++ DWC_DEBUGPL(DBG_HCDV, " Control data transaction\n"); ++ hc->data_pid_start = qtd->data_toggle; ++ break; ++ case DWC_OTG_CONTROL_STATUS: ++ /* ++ * Direction is opposite of data direction or IN if no ++ * data. ++ */ ++ DWC_DEBUGPL(DBG_HCDV, " Control status transaction\n"); ++ if (urb->length == 0) { ++ hc->ep_is_in = 1; ++ } else { ++ hc->ep_is_in = ++ dwc_otg_hcd_is_pipe_out(&urb->pipe_info); ++ } ++ if (hc->ep_is_in) { ++ hc->do_ping = 0; ++ } ++ ++ hc->data_pid_start = DWC_OTG_HC_PID_DATA1; ++ ++ hc->xfer_len = 0; ++ if (hcd->core_if->dma_enable) { ++ hc->xfer_buff = (uint8_t *) hcd->status_buf_dma; ++ } else { ++ hc->xfer_buff = (uint8_t *) hcd->status_buf; ++ } ++ ptr = NULL; ++ break; ++ } ++ break; ++ case UE_BULK: ++ hc->ep_type = DWC_OTG_EP_TYPE_BULK; ++ break; ++ case UE_INTERRUPT: ++ hc->ep_type = DWC_OTG_EP_TYPE_INTR; ++ break; ++ case UE_ISOCHRONOUS: ++ { ++ struct dwc_otg_hcd_iso_packet_desc *frame_desc; ++ ++ hc->ep_type = DWC_OTG_EP_TYPE_ISOC; ++ ++ if (hcd->core_if->dma_desc_enable) ++ break; ++ ++ frame_desc = &urb->iso_descs[qtd->isoc_frame_index]; ++ ++ frame_desc->status = 0; ++ ++ if (hcd->core_if->dma_enable) { ++ hc->xfer_buff = (uint8_t *) urb->dma; ++ } else { ++ hc->xfer_buff = (uint8_t *) urb->buf; ++ } ++ hc->xfer_buff += ++ frame_desc->offset + qtd->isoc_split_offset; ++ hc->xfer_len = ++ frame_desc->length - qtd->isoc_split_offset; ++ ++ /* For non-dword aligned buffers */ ++ if (((uint32_t)hc->xfer_buff & 0x3) && hcd->core_if->dma_enable) { ++ ptr = (uint8_t *) urb->buf + frame_desc->offset + qtd->isoc_split_offset; ++ } ++ else ++ ptr = NULL; ++ ++ if (hc->xact_pos == DWC_HCSPLIT_XACTPOS_ALL) { ++ if (hc->xfer_len <= 188) { ++ hc->xact_pos = DWC_HCSPLIT_XACTPOS_ALL; ++ } else { ++ hc->xact_pos = ++ DWC_HCSPLIT_XACTPOS_BEGIN; ++ } ++ } ++ } ++ break; ++ } ++ /* non DWORD-aligned buffer case */ ++ if (ptr) { ++ uint32_t buf_size; ++ if (hc->ep_type != DWC_OTG_EP_TYPE_ISOC) { ++ buf_size = hcd->core_if->core_params->max_transfer_size; ++ } else { ++ buf_size = 4096; ++ } ++ if (!qh->dw_align_buf) { ++ qh->dw_align_buf = ++ dwc_dma_alloc_atomic(buf_size, ++ &qh->dw_align_buf_dma); ++ if (!qh->dw_align_buf) { ++ DWC_ERROR("%s: Failed to allocate memory to handle " ++ "non-dword aligned buffer case\n", __func__); ++#ifdef HW2937_WORKAROUND ++ return 0; ++#else ++ return; ++#endif ++ } ++ } ++ if (!hc->ep_is_in) { ++ dwc_memcpy(qh->dw_align_buf, ptr, hc->xfer_len); ++ } ++ hc->align_buff = qh->dw_align_buf_dma; ++ } ++ else { ++ hc->align_buff = 0; ++ } ++ ++ if (hc->ep_type == DWC_OTG_EP_TYPE_INTR || ++ hc->ep_type == DWC_OTG_EP_TYPE_ISOC) { ++ /* ++ * This value may be modified when the transfer is started to ++ * reflect the actual transfer length. ++ */ ++ hc->multi_count = dwc_hb_mult(qh->maxp); ++ } ++ ++ if (hcd->core_if->dma_desc_enable) ++ hc->desc_list_addr = qh->desc_list_dma; ++ ++ dwc_otg_hc_init(hcd->core_if, hc); ++ hc->qh = qh; ++#ifdef HW2937_WORKAROUND ++ hcd->hw2937_assigned_channels |= (1 << hc->hc_num); ++ DWC_DEBUGPL(DBG_HW2937, " assign %d -> hw2937_ac %x\n", hc->hc_num, hcd->hw2937_assigned_channels); ++ return 1; ++#endif ++} ++ ++#ifdef HW2937_WORKAROUND ++ ++void debug_halt(void) ++{ ++ spinlock_t mr_lock = SPIN_LOCK_UNLOCKED; ++ unsigned long flags; ++ extern void v6_flush_kern_cache_all(void); ++ ++ spin_lock_irqsave(&mr_lock, flags); ++#ifdef CONFIG_MACH_BCM2708 ++ v6_flush_kern_cache_all(); ++#endif ++ while (1) continue; ++} ++ ++static ++void dwc_otg_hcd_disable_in_channels(dwc_otg_hcd_t * hcd) ++{ ++ int num_channels = hcd->core_if->core_params->host_channels; ++ static int stall_count = 0; ++ static int max_stall_count = 1; ++ static int last_stalled = 0; ++ int stalled = 0; ++ int i; ++ ++ DWC_DEBUGPL(DBG_HW2937, " Disable In Channels(%x)\n", hcd->hw2937_assigned_channels); ++ ++ for (i = 0; i < num_channels; i++) { ++ if (hcd->hw2937_assigned_channels & (1 << i)) { ++ dwc_hc_t *hc = hcd->hc_ptr_array[i]; ++ if (!hc->halt_pending) { ++ dwc_otg_hc_regs_t *hc_regs = hcd->core_if->host_if->hc_regs[hc->hc_num]; ++ hctsiz_data_t hctsiz; ++ hctsiz.d32 = dwc_read_reg32(&hc_regs->hctsiz); ++ DWC_DEBUGPL(DBG_HW2937, "pktcnt %d, xfersize %x, xfer_len %x\n", hctsiz.b.pktcnt, hctsiz.b.xfersize, hc->xfer_len); ++ if (hctsiz.b.pktcnt == hc->start_pkt_count) ++ { ++ dwc_otg_hc_halt(hcd->core_if, hc, DWC_OTG_HC_XFER_PAUSE_IN); ++ } ++ else ++ { ++ /* Unless a receive is in progress */ ++ stalled |= (1< max_stall_count) ++ { ++ max_stall_count = stall_count; ++ DWC_PRINTF( "stall (%x) count -> %d\n", stalled, stall_count); ++ if (stall_count == 10) ++ { ++ debug_halt(); ++ } ++ } ++ } ++ else ++ { ++ stall_count = 0; ++ last_stalled = stalled; ++ } ++} ++ ++static ++int dwc_otg_hcd_update_transaction_mode(dwc_otg_hcd_t * hcd) ++{ ++ dwc_list_link_t *qh_ptr; ++ dwc_otg_qh_t *qh; ++ dwc_otg_qtd_t *qtd; ++ dwc_otg_hcd_urb_t *urb; ++ int found_in = 0; ++ ++ /* If there are any existing out transactions, stay in OUT mode */ ++ if (hcd->hw2937_xfer_mode == HW2937_XFER_MODE_OUT) ++ { ++ return 1; ++ } ++ ++ /* Scan entries in the periodic ready list. */ ++ qh_ptr = DWC_LIST_FIRST(&hcd->periodic_sched_ready); ++ ++ while (qh_ptr != &hcd->periodic_sched_ready) { ++ qh = DWC_LIST_ENTRY(qh_ptr, dwc_otg_qh_t, qh_list_entry); ++ qtd = DWC_CIRCLEQ_FIRST(&qh->qtd_list); ++ urb = qtd->urb; ++ if (!dwc_otg_hcd_is_pipe_in(&urb->pipe_info)) { ++ /* Switch to OUT mode */ ++ switch (hcd->hw2937_xfer_mode) ++ { ++ case HW2937_XFER_MODE_IDLE: ++ DWC_DEBUGPL(DBG_HW2937, "utm -> OUT\n"); ++ hcd->hw2937_xfer_mode = HW2937_XFER_MODE_OUT; ++ /* Drop through... */ ++ case HW2937_XFER_MODE_OUT: ++ return 1; ++ case HW2937_XFER_MODE_IN: ++ DWC_DEBUGPL(DBG_HW2937, "utm - halting %x INs\n", hcd->hw2937_assigned_channels); ++ /* Disable the channels with outstanding INs */ ++ dwc_otg_hcd_disable_in_channels(hcd); ++ ++ DWC_DEBUGPL(DBG_HW2937, "utm -> PAUSEIN\n"); ++ hcd->hw2937_xfer_mode = HW2937_XFER_MODE_PAUSEIN; ++ /* Drop through... */ ++ case HW2937_XFER_MODE_PAUSEIN: ++ /* Delay until the halt completes */ ++ return 0; ++ } ++ } ++ found_in = 1; ++ qh_ptr = DWC_LIST_NEXT(qh_ptr); ++ } ++ ++ /* ++ * Scan entries in the inactive portion of the non-periodic ++ * schedule. ++ */ ++ qh_ptr = hcd->non_periodic_sched_inactive.next; ++ while (qh_ptr != &hcd->non_periodic_sched_inactive) { ++ qh = DWC_LIST_ENTRY(qh_ptr, dwc_otg_qh_t, qh_list_entry); ++ qtd = DWC_CIRCLEQ_FIRST(&qh->qtd_list); ++ urb = qtd->urb; ++ if (!dwc_otg_hcd_is_pipe_in(&urb->pipe_info)) { ++ /* Switch to OUT mode */ ++ switch (hcd->hw2937_xfer_mode) ++ { ++ case HW2937_XFER_MODE_IDLE: ++ DWC_DEBUGPL(DBG_HW2937, "utm -> OUT\n"); ++ hcd->hw2937_xfer_mode = HW2937_XFER_MODE_OUT; ++ /* Drop through... */ ++ case HW2937_XFER_MODE_OUT: ++ return 1; ++ case HW2937_XFER_MODE_IN: ++ DWC_DEBUGPL(DBG_HW2937, "utm - halting %x INs\n", hcd->hw2937_assigned_channels); ++ /* Disable the channels with outstanding INs */ ++ dwc_otg_hcd_disable_in_channels(hcd); ++ ++ DWC_DEBUGPL(DBG_HW2937, "utm -> PAUSEIN\n"); ++ hcd->hw2937_xfer_mode = HW2937_XFER_MODE_PAUSEIN; ++ /* Drop through... */ ++ case HW2937_XFER_MODE_PAUSEIN: ++ /* Delay until the halt completes */ ++ return 0; ++ } ++ } ++ found_in = 1; ++ qh_ptr = DWC_LIST_NEXT(qh_ptr); ++ } ++ ++ if (found_in && (hcd->hw2937_xfer_mode == HW2937_XFER_MODE_IDLE)) ++ { ++ DWC_DEBUGPL(DBG_HW2937, "utm -> IN\n"); ++ hcd->hw2937_xfer_mode = HW2937_XFER_MODE_IN; ++ } ++ return 1; ++} ++ ++#endif /* HW2937_WORKAROUND */ ++ ++/** ++ * This function selects transactions from the HCD transfer schedule and ++ * assigns them to available host channels. It is called from HCD interrupt ++ * handler functions. ++ * ++ * @param hcd The HCD state structure. ++ * ++ * @return The types of new transactions that were assigned to host channels. ++ */ ++dwc_otg_transaction_type_e dwc_otg_hcd_select_transactions(dwc_otg_hcd_t * hcd) ++{ ++ dwc_list_link_t *qh_ptr; ++ dwc_otg_qh_t *qh; ++ int num_channels; ++ dwc_otg_transaction_type_e ret_val = DWC_OTG_TRANSACTION_NONE; ++ ++#ifdef DEBUG_SOF ++ DWC_DEBUGPL(DBG_HCD, " Select Transactions\n"); ++#endif ++ ++#ifdef HW2937_WORKAROUND ++ if (!dwc_otg_hcd_update_transaction_mode(hcd)) ++ { ++ return ret_val; ++ } ++#endif ++ ++ /* Process entries in the periodic ready list. */ ++ qh_ptr = DWC_LIST_FIRST(&hcd->periodic_sched_ready); ++ ++ while (qh_ptr != &hcd->periodic_sched_ready && ++ !DWC_CIRCLEQ_EMPTY(&hcd->free_hc_list)) { ++ qh = DWC_LIST_ENTRY(qh_ptr, dwc_otg_qh_t, qh_list_entry); ++#ifdef HW2937_WORKAROUND ++ if (assign_and_init_hc(hcd, qh)) { ++#else ++ assign_and_init_hc(hcd, qh); ++#endif ++ ++ /* ++ * Move the QH from the periodic ready schedule to the ++ * periodic assigned schedule. ++ */ ++ qh_ptr = DWC_LIST_NEXT(qh_ptr); ++ DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_assigned, ++ &qh->qh_list_entry); ++ ++ ret_val = DWC_OTG_TRANSACTION_PERIODIC; ++#ifdef HW2937_WORKAROUND ++ } else { ++ qh_ptr = DWC_LIST_NEXT(qh_ptr); ++ } ++#endif ++ } ++ ++ /* ++ * Process entries in the inactive portion of the non-periodic ++ * schedule. Some free host channels may not be used if they are ++ * reserved for periodic transfers. ++ */ ++ qh_ptr = hcd->non_periodic_sched_inactive.next; ++ num_channels = hcd->core_if->core_params->host_channels; ++ while (qh_ptr != &hcd->non_periodic_sched_inactive && ++ (hcd->non_periodic_channels < ++ num_channels - hcd->periodic_channels) && ++ !DWC_CIRCLEQ_EMPTY(&hcd->free_hc_list)) { ++ ++ qh = DWC_LIST_ENTRY(qh_ptr, dwc_otg_qh_t, qh_list_entry); ++ ++#ifdef HW2937_WORKAROUND ++ if (assign_and_init_hc(hcd, qh)) { ++#else ++ assign_and_init_hc(hcd, qh); ++#endif ++ ++ /* ++ * Move the QH from the non-periodic inactive schedule to the ++ * non-periodic active schedule. ++ */ ++ qh_ptr = DWC_LIST_NEXT(qh_ptr); ++ DWC_LIST_MOVE_HEAD(&hcd->non_periodic_sched_active, ++ &qh->qh_list_entry); ++ ++ if (ret_val == DWC_OTG_TRANSACTION_NONE) { ++ ret_val = DWC_OTG_TRANSACTION_NON_PERIODIC; ++ } else { ++ ret_val = DWC_OTG_TRANSACTION_ALL; ++ } ++ ++ hcd->non_periodic_channels++; ++#ifdef HW2937_WORKAROUND ++ } else { ++ qh_ptr = DWC_LIST_NEXT(qh_ptr); ++ } ++#endif ++ } ++ ++ return ret_val; ++} ++/** ++ * Attempts to queue a single transaction request for a host channel ++ * associated with either a periodic or non-periodic transfer. This function ++ * assumes that there is space available in the appropriate request queue. For ++ * an OUT transfer or SETUP transaction in Slave mode, it checks whether space ++ * is available in the appropriate Tx FIFO. ++ * ++ * @param hcd The HCD state structure. ++ * @param hc Host channel descriptor associated with either a periodic or ++ * non-periodic transfer. ++ * @param fifo_dwords_avail Number of DWORDs available in the periodic Tx ++ * FIFO for periodic transfers or the non-periodic Tx FIFO for non-periodic ++ * transfers. ++ * ++ * @return 1 if a request is queued and more requests may be needed to ++ * complete the transfer, 0 if no more requests are required for this ++ * transfer, -1 if there is insufficient space in the Tx FIFO. ++ */ ++static int queue_transaction(dwc_otg_hcd_t * hcd, ++ dwc_hc_t * hc, uint16_t fifo_dwords_avail) ++{ ++ int retval; ++ ++ if (hcd->core_if->dma_enable) { ++ if (hcd->core_if->dma_desc_enable) { ++ if (!hc->xfer_started || (hc->ep_type == DWC_OTG_EP_TYPE_ISOC)) { ++ dwc_otg_hcd_start_xfer_ddma(hcd, hc->qh); ++ hc->qh->ping_state = 0; ++ } ++ } ++ else if (!hc->xfer_started) { ++ dwc_otg_hc_start_transfer(hcd->core_if, hc); ++ hc->qh->ping_state = 0; ++ } ++ retval = 0; ++ } else if (hc->halt_pending) { ++ /* Don't queue a request if the channel has been halted. */ ++ retval = 0; ++ } else if (hc->halt_on_queue) { ++ dwc_otg_hc_halt(hcd->core_if, hc, hc->halt_status); ++ retval = 0; ++ } else if (hc->do_ping) { ++ if (!hc->xfer_started) { ++ dwc_otg_hc_start_transfer(hcd->core_if, hc); ++ } ++ retval = 0; ++ } else if (!hc->ep_is_in || hc->data_pid_start == DWC_OTG_HC_PID_SETUP) { ++ if ((fifo_dwords_avail * 4) >= hc->max_packet) { ++ if (!hc->xfer_started) { ++ dwc_otg_hc_start_transfer(hcd->core_if, hc); ++ retval = 1; ++ } else { ++ retval = ++ dwc_otg_hc_continue_transfer(hcd->core_if, ++ hc); ++ } ++ } else { ++ retval = -1; ++ } ++ } else { ++ if (!hc->xfer_started) { ++ dwc_otg_hc_start_transfer(hcd->core_if, hc); ++ retval = 1; ++ } else { ++ retval = dwc_otg_hc_continue_transfer(hcd->core_if, hc); ++ } ++ } ++ ++ return retval; ++} ++ ++/** ++ * Processes periodic channels for the next frame and queues transactions for ++ * these channels to the DWC_otg controller. After queueing transactions, the ++ * Periodic Tx FIFO Empty interrupt is enabled if there are more transactions ++ * to queue as Periodic Tx FIFO or request queue space becomes available. ++ * Otherwise, the Periodic Tx FIFO Empty interrupt is disabled. ++ */ ++static void process_periodic_channels(dwc_otg_hcd_t * hcd) ++{ ++ hptxsts_data_t tx_status; ++ dwc_list_link_t *qh_ptr; ++ dwc_otg_qh_t *qh; ++ int status; ++ int no_queue_space = 0; ++ int no_fifo_space = 0; ++ ++ dwc_otg_host_global_regs_t *host_regs; ++ host_regs = hcd->core_if->host_if->host_global_regs; ++ ++ DWC_DEBUGPL(DBG_HCDV, "Queue periodic transactions\n"); ++#ifdef DEBUG ++ tx_status.d32 = dwc_read_reg32(&host_regs->hptxsts); ++ DWC_DEBUGPL(DBG_HCDV, ++ " P Tx Req Queue Space Avail (before queue): %d\n", ++ tx_status.b.ptxqspcavail); ++ DWC_DEBUGPL(DBG_HCDV, " P Tx FIFO Space Avail (before queue): %d\n", ++ tx_status.b.ptxfspcavail); ++#endif ++ ++ qh_ptr = hcd->periodic_sched_assigned.next; ++ while (qh_ptr != &hcd->periodic_sched_assigned) { ++ tx_status.d32 = dwc_read_reg32(&host_regs->hptxsts); ++ if (tx_status.b.ptxqspcavail == 0) { ++ no_queue_space = 1; ++ break; ++ } ++ ++ qh = DWC_LIST_ENTRY(qh_ptr, dwc_otg_qh_t, qh_list_entry); ++ ++ /* ++ * Set a flag if we're queuing high-bandwidth in slave mode. ++ * The flag prevents any halts to get into the request queue in ++ * the middle of multiple high-bandwidth packets getting queued. ++ */ ++ if (!hcd->core_if->dma_enable && qh->channel->multi_count > 1) { ++ hcd->core_if->queuing_high_bandwidth = 1; ++ } ++ status = ++ queue_transaction(hcd, qh->channel, ++ tx_status.b.ptxfspcavail); ++ if (status < 0) { ++ no_fifo_space = 1; ++ break; ++ } ++ ++ /* ++ * In Slave mode, stay on the current transfer until there is ++ * nothing more to do or the high-bandwidth request count is ++ * reached. In DMA mode, only need to queue one request. The ++ * controller automatically handles multiple packets for ++ * high-bandwidth transfers. ++ */ ++ if (hcd->core_if->dma_enable || status == 0 || ++ qh->channel->requests == qh->channel->multi_count) { ++ qh_ptr = qh_ptr->next; ++ /* ++ * Move the QH from the periodic assigned schedule to ++ * the periodic queued schedule. ++ */ ++ DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_queued, ++ &qh->qh_list_entry); ++ ++ /* done queuing high bandwidth */ ++ hcd->core_if->queuing_high_bandwidth = 0; ++ } ++ } ++ ++ if (!hcd->core_if->dma_enable) { ++ dwc_otg_core_global_regs_t *global_regs; ++ gintmsk_data_t intr_mask = {.d32 = 0 }; ++ ++ global_regs = hcd->core_if->core_global_regs; ++ intr_mask.b.ptxfempty = 1; ++#ifdef DEBUG ++ tx_status.d32 = dwc_read_reg32(&host_regs->hptxsts); ++ DWC_DEBUGPL(DBG_HCDV, ++ " P Tx Req Queue Space Avail (after queue): %d\n", ++ tx_status.b.ptxqspcavail); ++ DWC_DEBUGPL(DBG_HCDV, ++ " P Tx FIFO Space Avail (after queue): %d\n", ++ tx_status.b.ptxfspcavail); ++#endif ++ if (!DWC_LIST_EMPTY(&hcd->periodic_sched_assigned) || ++ no_queue_space || no_fifo_space) { ++ /* ++ * May need to queue more transactions as the request ++ * queue or Tx FIFO empties. Enable the periodic Tx ++ * FIFO empty interrupt. (Always use the half-empty ++ * level to ensure that new requests are loaded as ++ * soon as possible.) ++ */ ++ dwc_modify_reg32(&global_regs->gintmsk, 0, ++ intr_mask.d32); ++ } else { ++ /* ++ * Disable the Tx FIFO empty interrupt since there are ++ * no more transactions that need to be queued right ++ * now. This function is called from interrupt ++ * handlers to queue more transactions as transfer ++ * states change. ++ */ ++ dwc_modify_reg32(&global_regs->gintmsk, intr_mask.d32, ++ 0); ++ } ++ } ++} ++ ++/** ++ * Processes active non-periodic channels and queues transactions for these ++ * channels to the DWC_otg controller. After queueing transactions, the NP Tx ++ * FIFO Empty interrupt is enabled if there are more transactions to queue as ++ * NP Tx FIFO or request queue space becomes available. Otherwise, the NP Tx ++ * FIFO Empty interrupt is disabled. ++ */ ++static void process_non_periodic_channels(dwc_otg_hcd_t * hcd) ++{ ++ gnptxsts_data_t tx_status; ++ dwc_list_link_t *orig_qh_ptr; ++ dwc_otg_qh_t *qh; ++ int status; ++ int no_queue_space = 0; ++ int no_fifo_space = 0; ++ int more_to_do = 0; ++ ++ dwc_otg_core_global_regs_t *global_regs = ++ hcd->core_if->core_global_regs; ++ ++ DWC_DEBUGPL(DBG_HCDV, "Queue non-periodic transactions\n"); ++#ifdef DEBUG ++ tx_status.d32 = dwc_read_reg32(&global_regs->gnptxsts); ++ DWC_DEBUGPL(DBG_HCDV, ++ " NP Tx Req Queue Space Avail (before queue): %d\n", ++ tx_status.b.nptxqspcavail); ++ DWC_DEBUGPL(DBG_HCDV, " NP Tx FIFO Space Avail (before queue): %d\n", ++ tx_status.b.nptxfspcavail); ++#endif ++ /* ++ * Keep track of the starting point. Skip over the start-of-list ++ * entry. ++ */ ++ if (hcd->non_periodic_qh_ptr == &hcd->non_periodic_sched_active) { ++ hcd->non_periodic_qh_ptr = hcd->non_periodic_qh_ptr->next; ++ } ++ orig_qh_ptr = hcd->non_periodic_qh_ptr; ++ ++ /* ++ * Process once through the active list or until no more space is ++ * available in the request queue or the Tx FIFO. ++ */ ++ do { ++ tx_status.d32 = dwc_read_reg32(&global_regs->gnptxsts); ++ if (!hcd->core_if->dma_enable && tx_status.b.nptxqspcavail == 0) { ++ no_queue_space = 1; ++ break; ++ } ++ ++ qh = DWC_LIST_ENTRY(hcd->non_periodic_qh_ptr, dwc_otg_qh_t, ++ qh_list_entry); ++ status = ++ queue_transaction(hcd, qh->channel, ++ tx_status.b.nptxfspcavail); ++ ++ if (status > 0) { ++ more_to_do = 1; ++ } else if (status < 0) { ++ no_fifo_space = 1; ++ break; ++ } ++ ++ /* Advance to next QH, skipping start-of-list entry. */ ++ hcd->non_periodic_qh_ptr = hcd->non_periodic_qh_ptr->next; ++ if (hcd->non_periodic_qh_ptr == &hcd->non_periodic_sched_active) { ++ hcd->non_periodic_qh_ptr = ++ hcd->non_periodic_qh_ptr->next; ++ } ++ ++ } while (hcd->non_periodic_qh_ptr != orig_qh_ptr); ++ ++ if (!hcd->core_if->dma_enable) { ++ gintmsk_data_t intr_mask = {.d32 = 0 }; ++ intr_mask.b.nptxfempty = 1; ++ ++#ifdef DEBUG ++ tx_status.d32 = dwc_read_reg32(&global_regs->gnptxsts); ++ DWC_DEBUGPL(DBG_HCDV, ++ " NP Tx Req Queue Space Avail (after queue): %d\n", ++ tx_status.b.nptxqspcavail); ++ DWC_DEBUGPL(DBG_HCDV, ++ " NP Tx FIFO Space Avail (after queue): %d\n", ++ tx_status.b.nptxfspcavail); ++#endif ++ if (more_to_do || no_queue_space || no_fifo_space) { ++ /* ++ * May need to queue more transactions as the request ++ * queue or Tx FIFO empties. Enable the non-periodic ++ * Tx FIFO empty interrupt. (Always use the half-empty ++ * level to ensure that new requests are loaded as ++ * soon as possible.) ++ */ ++ dwc_modify_reg32(&global_regs->gintmsk, 0, ++ intr_mask.d32); ++ } else { ++ /* ++ * Disable the Tx FIFO empty interrupt since there are ++ * no more transactions that need to be queued right ++ * now. This function is called from interrupt ++ * handlers to queue more transactions as transfer ++ * states change. ++ */ ++ dwc_modify_reg32(&global_regs->gintmsk, intr_mask.d32, ++ 0); ++ } ++ } ++} ++ ++/** ++ * This function processes the currently active host channels and queues ++ * transactions for these channels to the DWC_otg controller. It is called ++ * from HCD interrupt handler functions. ++ * ++ * @param hcd The HCD state structure. ++ * @param tr_type The type(s) of transactions to queue (non-periodic, ++ * periodic, or both). ++ */ ++void dwc_otg_hcd_queue_transactions(dwc_otg_hcd_t * hcd, ++ dwc_otg_transaction_type_e tr_type) ++{ ++#ifdef DEBUG_SOF ++ DWC_DEBUGPL(DBG_HCD, "Queue Transactions\n"); ++#endif ++ /* Process host channels associated with periodic transfers. */ ++ if ((tr_type == DWC_OTG_TRANSACTION_PERIODIC || ++ tr_type == DWC_OTG_TRANSACTION_ALL) && ++ !DWC_LIST_EMPTY(&hcd->periodic_sched_assigned)) { ++ ++ process_periodic_channels(hcd); ++ } ++ ++ /* Process host channels associated with non-periodic transfers. */ ++ if (tr_type == DWC_OTG_TRANSACTION_NON_PERIODIC || ++ tr_type == DWC_OTG_TRANSACTION_ALL) { ++ if (!DWC_LIST_EMPTY(&hcd->non_periodic_sched_active)) { ++ process_non_periodic_channels(hcd); ++ } else { ++ /* ++ * Ensure NP Tx FIFO empty interrupt is disabled when ++ * there are no non-periodic transfers to process. ++ */ ++ gintmsk_data_t gintmsk = {.d32 = 0 }; ++ gintmsk.b.nptxfempty = 1; ++ dwc_modify_reg32(&hcd->core_if->core_global_regs-> ++ gintmsk, gintmsk.d32, 0); ++ } ++ } ++} ++ ++#ifdef DWC_HS_ELECT_TST ++/* ++ * Quick and dirty hack to implement the HS Electrical Test ++ * SINGLE_STEP_GET_DEVICE_DESCRIPTOR feature. ++ * ++ * This code was copied from our userspace app "hset". It sends a ++ * Get Device Descriptor control sequence in two parts, first the ++ * Setup packet by itself, followed some time later by the In and ++ * Ack packets. Rather than trying to figure out how to add this ++ * functionality to the normal driver code, we just hijack the ++ * hardware, using these two function to drive the hardware ++ * directly. ++ */ ++ ++static dwc_otg_core_global_regs_t *global_regs; ++static dwc_otg_host_global_regs_t *hc_global_regs; ++static dwc_otg_hc_regs_t *hc_regs; ++static uint32_t *data_fifo; ++ ++static void do_setup(void) ++{ ++ gintsts_data_t gintsts; ++ hctsiz_data_t hctsiz; ++ hcchar_data_t hcchar; ++ haint_data_t haint; ++ hcint_data_t hcint; ++ ++ /* Enable HAINTs */ ++ dwc_write_reg32(&hc_global_regs->haintmsk, 0x0001); ++ ++ /* Enable HCINTs */ ++ dwc_write_reg32(&hc_regs->hcintmsk, 0x04a3); ++ ++ /* Read GINTSTS */ ++ gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); ++ ++ /* Read HAINT */ ++ haint.d32 = dwc_read_reg32(&hc_global_regs->haint); ++ ++ /* Read HCINT */ ++ hcint.d32 = dwc_read_reg32(&hc_regs->hcint); ++ ++ /* Read HCCHAR */ ++ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); ++ ++ /* Clear HCINT */ ++ dwc_write_reg32(&hc_regs->hcint, hcint.d32); ++ ++ /* Clear HAINT */ ++ dwc_write_reg32(&hc_global_regs->haint, haint.d32); ++ ++ /* Clear GINTSTS */ ++ dwc_write_reg32(&global_regs->gintsts, gintsts.d32); ++ ++ /* Read GINTSTS */ ++ gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); ++ ++ /* ++ * Send Setup packet (Get Device Descriptor) ++ */ ++ ++ /* Make sure channel is disabled */ ++ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); ++ if (hcchar.b.chen) { ++ hcchar.b.chdis = 1; ++// hcchar.b.chen = 1; ++ dwc_write_reg32(&hc_regs->hcchar, hcchar.d32); ++ //sleep(1); ++ dwc_mdelay(1000); ++ ++ /* Read GINTSTS */ ++ gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); ++ ++ /* Read HAINT */ ++ haint.d32 = dwc_read_reg32(&hc_global_regs->haint); ++ ++ /* Read HCINT */ ++ hcint.d32 = dwc_read_reg32(&hc_regs->hcint); ++ ++ /* Read HCCHAR */ ++ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); ++ ++ /* Clear HCINT */ ++ dwc_write_reg32(&hc_regs->hcint, hcint.d32); ++ ++ /* Clear HAINT */ ++ dwc_write_reg32(&hc_global_regs->haint, haint.d32); ++ ++ /* Clear GINTSTS */ ++ dwc_write_reg32(&global_regs->gintsts, gintsts.d32); ++ ++ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); ++ } ++ ++ /* Set HCTSIZ */ ++ hctsiz.d32 = 0; ++ hctsiz.b.xfersize = 8; ++ hctsiz.b.pktcnt = 1; ++ hctsiz.b.pid = DWC_OTG_HC_PID_SETUP; ++ dwc_write_reg32(&hc_regs->hctsiz, hctsiz.d32); ++ ++ /* Set HCCHAR */ ++ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); ++ hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL; ++ hcchar.b.epdir = 0; ++ hcchar.b.epnum = 0; ++ hcchar.b.mps = 8; ++ hcchar.b.chen = 1; ++ dwc_write_reg32(&hc_regs->hcchar, hcchar.d32); ++ ++ /* Fill FIFO with Setup data for Get Device Descriptor */ ++ data_fifo = (uint32_t *) ((char *)global_regs + 0x1000); ++ dwc_write_reg32(data_fifo++, 0x01000680); ++ dwc_write_reg32(data_fifo++, 0x00080000); ++ ++ gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); ++ ++ /* Wait for host channel interrupt */ ++ do { ++ gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); ++ } while (gintsts.b.hcintr == 0); ++ ++ ++ /* Disable HCINTs */ ++ dwc_write_reg32(&hc_regs->hcintmsk, 0x0000); ++ ++ /* Disable HAINTs */ ++ dwc_write_reg32(&hc_global_regs->haintmsk, 0x0000); ++ ++ /* Read HAINT */ ++ haint.d32 = dwc_read_reg32(&hc_global_regs->haint); ++ ++ /* Read HCINT */ ++ hcint.d32 = dwc_read_reg32(&hc_regs->hcint); ++ ++ /* Read HCCHAR */ ++ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); ++ ++ /* Clear HCINT */ ++ dwc_write_reg32(&hc_regs->hcint, hcint.d32); ++ ++ /* Clear HAINT */ ++ dwc_write_reg32(&hc_global_regs->haint, haint.d32); ++ ++ /* Clear GINTSTS */ ++ dwc_write_reg32(&global_regs->gintsts, gintsts.d32); ++ ++ /* Read GINTSTS */ ++ gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); ++} ++ ++static void do_in_ack(void) ++{ ++ gintsts_data_t gintsts; ++ hctsiz_data_t hctsiz; ++ hcchar_data_t hcchar; ++ haint_data_t haint; ++ hcint_data_t hcint; ++ host_grxsts_data_t grxsts; ++ ++ /* Enable HAINTs */ ++ dwc_write_reg32(&hc_global_regs->haintmsk, 0x0001); ++ ++ /* Enable HCINTs */ ++ dwc_write_reg32(&hc_regs->hcintmsk, 0x04a3); ++ ++ /* Read GINTSTS */ ++ gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); ++ ++ /* Read HAINT */ ++ haint.d32 = dwc_read_reg32(&hc_global_regs->haint); ++ ++ /* Read HCINT */ ++ hcint.d32 = dwc_read_reg32(&hc_regs->hcint); ++ ++ /* Read HCCHAR */ ++ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); ++ ++ /* Clear HCINT */ ++ dwc_write_reg32(&hc_regs->hcint, hcint.d32); ++ ++ /* Clear HAINT */ ++ dwc_write_reg32(&hc_global_regs->haint, haint.d32); ++ ++ /* Clear GINTSTS */ ++ dwc_write_reg32(&global_regs->gintsts, gintsts.d32); ++ ++ /* Read GINTSTS */ ++ gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); ++ ++ /* ++ * Receive Control In packet ++ */ ++ ++ /* Make sure channel is disabled */ ++ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); ++ if (hcchar.b.chen) { ++ hcchar.b.chdis = 1; ++ hcchar.b.chen = 1; ++ dwc_write_reg32(&hc_regs->hcchar, hcchar.d32); ++ //sleep(1); ++ dwc_mdelay(1000); ++ ++ /* Read GINTSTS */ ++ gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); ++ ++ /* Read HAINT */ ++ haint.d32 = dwc_read_reg32(&hc_global_regs->haint); ++ ++ /* Read HCINT */ ++ hcint.d32 = dwc_read_reg32(&hc_regs->hcint); ++ ++ /* Read HCCHAR */ ++ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); ++ ++ /* Clear HCINT */ ++ dwc_write_reg32(&hc_regs->hcint, hcint.d32); ++ ++ /* Clear HAINT */ ++ dwc_write_reg32(&hc_global_regs->haint, haint.d32); ++ ++ /* Clear GINTSTS */ ++ dwc_write_reg32(&global_regs->gintsts, gintsts.d32); ++ ++ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); ++ } ++ ++ /* Set HCTSIZ */ ++ hctsiz.d32 = 0; ++ hctsiz.b.xfersize = 8; ++ hctsiz.b.pktcnt = 1; ++ hctsiz.b.pid = DWC_OTG_HC_PID_DATA1; ++ dwc_write_reg32(&hc_regs->hctsiz, hctsiz.d32); ++ ++ /* Set HCCHAR */ ++ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); ++ hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL; ++ hcchar.b.epdir = 1; ++ hcchar.b.epnum = 0; ++ hcchar.b.mps = 8; ++ hcchar.b.chen = 1; ++ dwc_write_reg32(&hc_regs->hcchar, hcchar.d32); ++ ++ gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); ++ ++ /* Wait for receive status queue interrupt */ ++ do { ++ gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); ++ } while (gintsts.b.rxstsqlvl == 0); ++ ++ ++ /* Read RXSTS */ ++ grxsts.d32 = dwc_read_reg32(&global_regs->grxstsp); ++ ++ /* Clear RXSTSQLVL in GINTSTS */ ++ gintsts.d32 = 0; ++ gintsts.b.rxstsqlvl = 1; ++ dwc_write_reg32(&global_regs->gintsts, gintsts.d32); ++ ++ switch (grxsts.b.pktsts) { ++ case DWC_GRXSTS_PKTSTS_IN: ++ /* Read the data into the host buffer */ ++ if (grxsts.b.bcnt > 0) { ++ int i; ++ int word_count = (grxsts.b.bcnt + 3) / 4; ++ ++ data_fifo = (uint32_t *) ((char *)global_regs + 0x1000); ++ ++ for (i = 0; i < word_count; i++) { ++ (void)dwc_read_reg32(data_fifo++); ++ } ++ } ++ break; ++ ++ default: ++ break; ++ } ++ ++ gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); ++ ++ /* Wait for receive status queue interrupt */ ++ do { ++ gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); ++ } while (gintsts.b.rxstsqlvl == 0); ++ ++ ++ /* Read RXSTS */ ++ grxsts.d32 = dwc_read_reg32(&global_regs->grxstsp); ++ ++ /* Clear RXSTSQLVL in GINTSTS */ ++ gintsts.d32 = 0; ++ gintsts.b.rxstsqlvl = 1; ++ dwc_write_reg32(&global_regs->gintsts, gintsts.d32); ++ ++ switch (grxsts.b.pktsts) { ++ case DWC_GRXSTS_PKTSTS_IN_XFER_COMP: ++ break; ++ ++ default: ++ break; ++ } ++ ++ gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); ++ ++ /* Wait for host channel interrupt */ ++ do { ++ gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); ++ } while (gintsts.b.hcintr == 0); ++ ++ ++ /* Read HAINT */ ++ haint.d32 = dwc_read_reg32(&hc_global_regs->haint); ++ ++ /* Read HCINT */ ++ hcint.d32 = dwc_read_reg32(&hc_regs->hcint); ++ ++ /* Read HCCHAR */ ++ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); ++ ++ /* Clear HCINT */ ++ dwc_write_reg32(&hc_regs->hcint, hcint.d32); ++ ++ /* Clear HAINT */ ++ dwc_write_reg32(&hc_global_regs->haint, haint.d32); ++ ++ /* Clear GINTSTS */ ++ dwc_write_reg32(&global_regs->gintsts, gintsts.d32); ++ ++ /* Read GINTSTS */ ++ gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); ++ ++// usleep(100000); ++// mdelay(100); ++ dwc_mdelay(1); ++ ++ /* ++ * Send handshake packet ++ */ ++ ++ /* Read HAINT */ ++ haint.d32 = dwc_read_reg32(&hc_global_regs->haint); ++ ++ /* Read HCINT */ ++ hcint.d32 = dwc_read_reg32(&hc_regs->hcint); ++ ++ /* Read HCCHAR */ ++ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); ++ ++ /* Clear HCINT */ ++ dwc_write_reg32(&hc_regs->hcint, hcint.d32); ++ ++ /* Clear HAINT */ ++ dwc_write_reg32(&hc_global_regs->haint, haint.d32); ++ ++ /* Clear GINTSTS */ ++ dwc_write_reg32(&global_regs->gintsts, gintsts.d32); ++ ++ /* Read GINTSTS */ ++ gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); ++ ++ /* Make sure channel is disabled */ ++ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); ++ if (hcchar.b.chen) { ++ hcchar.b.chdis = 1; ++ hcchar.b.chen = 1; ++ dwc_write_reg32(&hc_regs->hcchar, hcchar.d32); ++ //sleep(1); ++ dwc_mdelay(1000); ++ ++ /* Read GINTSTS */ ++ gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); ++ ++ /* Read HAINT */ ++ haint.d32 = dwc_read_reg32(&hc_global_regs->haint); ++ ++ /* Read HCINT */ ++ hcint.d32 = dwc_read_reg32(&hc_regs->hcint); ++ ++ /* Read HCCHAR */ ++ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); ++ ++ /* Clear HCINT */ ++ dwc_write_reg32(&hc_regs->hcint, hcint.d32); ++ ++ /* Clear HAINT */ ++ dwc_write_reg32(&hc_global_regs->haint, haint.d32); ++ ++ /* Clear GINTSTS */ ++ dwc_write_reg32(&global_regs->gintsts, gintsts.d32); ++ ++ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); ++ } ++ ++ /* Set HCTSIZ */ ++ hctsiz.d32 = 0; ++ hctsiz.b.xfersize = 0; ++ hctsiz.b.pktcnt = 1; ++ hctsiz.b.pid = DWC_OTG_HC_PID_DATA1; ++ dwc_write_reg32(&hc_regs->hctsiz, hctsiz.d32); ++ ++ /* Set HCCHAR */ ++ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); ++ hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL; ++ hcchar.b.epdir = 0; ++ hcchar.b.epnum = 0; ++ hcchar.b.mps = 8; ++ hcchar.b.chen = 1; ++ dwc_write_reg32(&hc_regs->hcchar, hcchar.d32); ++ ++ gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); ++ ++ /* Wait for host channel interrupt */ ++ do { ++ gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); ++ } while (gintsts.b.hcintr == 0); ++ ++ ++ /* Disable HCINTs */ ++ dwc_write_reg32(&hc_regs->hcintmsk, 0x0000); ++ ++ /* Disable HAINTs */ ++ dwc_write_reg32(&hc_global_regs->haintmsk, 0x0000); ++ ++ /* Read HAINT */ ++ haint.d32 = dwc_read_reg32(&hc_global_regs->haint); ++ ++ /* Read HCINT */ ++ hcint.d32 = dwc_read_reg32(&hc_regs->hcint); ++ ++ /* Read HCCHAR */ ++ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); ++ ++ /* Clear HCINT */ ++ dwc_write_reg32(&hc_regs->hcint, hcint.d32); ++ ++ /* Clear HAINT */ ++ dwc_write_reg32(&hc_global_regs->haint, haint.d32); ++ ++ /* Clear GINTSTS */ ++ dwc_write_reg32(&global_regs->gintsts, gintsts.d32); ++ ++ /* Read GINTSTS */ ++ gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); ++} ++#endif ++ ++/** Handles hub class-specific requests. */ ++int dwc_otg_hcd_hub_control(dwc_otg_hcd_t * dwc_otg_hcd, ++ uint16_t typeReq, ++ uint16_t wValue, ++ uint16_t wIndex, uint8_t * buf, uint16_t wLength) ++{ ++ int retval = 0; ++ ++ dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if; ++ usb_hub_descriptor_t *hub_desc; ++ hprt0_data_t hprt0 = {.d32 = 0 }; ++ ++ uint32_t port_status; ++ ++ switch (typeReq) { ++ case UCR_CLEAR_HUB_FEATURE: ++ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - " ++ "ClearHubFeature 0x%x\n", wValue); ++ switch (wValue) { ++ case UHF_C_HUB_LOCAL_POWER: ++ case UHF_C_HUB_OVER_CURRENT: ++ /* Nothing required here */ ++ break; ++ default: ++ retval = -DWC_E_INVALID; ++ DWC_ERROR("DWC OTG HCD - " ++ "ClearHubFeature request %xh unknown\n", ++ wValue); ++ } ++ break; ++ case UCR_CLEAR_PORT_FEATURE: ++#ifdef CONFIG_USB_DWC_OTG_LPM ++ if (wValue != UHF_PORT_L1) ++#endif ++ if (!wIndex || wIndex > 1) ++ goto error; ++ ++ switch (wValue) { ++ case UHF_PORT_ENABLE: ++ DWC_DEBUGPL(DBG_ANY, "DWC OTG HCD HUB CONTROL - " ++ "ClearPortFeature USB_PORT_FEAT_ENABLE\n"); ++ hprt0.d32 = dwc_otg_read_hprt0(core_if); ++ hprt0.b.prtena = 1; ++ dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32); ++ break; ++ case UHF_PORT_SUSPEND: ++ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - " ++ "ClearPortFeature USB_PORT_FEAT_SUSPEND\n"); ++ ++ dwc_write_reg32(core_if->pcgcctl, 0); ++ dwc_mdelay(5); ++ ++ hprt0.d32 = dwc_otg_read_hprt0(core_if); ++ hprt0.b.prtres = 1; ++ dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32); ++ hprt0.b.prtsusp = 0; ++ /* Clear Resume bit */ ++ dwc_mdelay(100); ++ hprt0.b.prtres = 0; ++ dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32); ++ break; ++#ifdef CONFIG_USB_DWC_OTG_LPM ++ case UHF_PORT_L1: ++ { ++ pcgcctl_data_t pcgcctl = {.d32 = 0 }; ++ glpmcfg_data_t lpmcfg = {.d32 = 0 }; ++ ++ lpmcfg.d32 = ++ dwc_read_reg32(&core_if->core_global_regs-> ++ glpmcfg); ++ lpmcfg.b.en_utmi_sleep = 0; ++ lpmcfg.b.hird_thres &= (~(1 << 4)); ++ lpmcfg.b.prt_sleep_sts = 1; ++ dwc_write_reg32(&core_if->core_global_regs-> ++ glpmcfg, lpmcfg.d32); ++ ++ /* Clear Enbl_L1Gating bit. */ ++ pcgcctl.b.enbl_sleep_gating = 1; ++ dwc_modify_reg32(core_if->pcgcctl, pcgcctl.d32, ++ 0); ++ ++ dwc_mdelay(5); ++ ++ hprt0.d32 = dwc_otg_read_hprt0(core_if); ++ hprt0.b.prtres = 1; ++ dwc_write_reg32(core_if->host_if->hprt0, ++ hprt0.d32); ++ /* This bit will be cleared in wakeup interrupt handle */ ++ break; ++ } ++#endif ++ case UHF_PORT_POWER: ++ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - " ++ "ClearPortFeature USB_PORT_FEAT_POWER\n"); ++ hprt0.d32 = dwc_otg_read_hprt0(core_if); ++ hprt0.b.prtpwr = 0; ++ dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32); ++ break; ++ case UHF_PORT_INDICATOR: ++ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - " ++ "ClearPortFeature USB_PORT_FEAT_INDICATOR\n"); ++ /* Port inidicator not supported */ ++ break; ++ case UHF_C_PORT_CONNECTION: ++ /* Clears drivers internal connect status change ++ * flag */ ++ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - " ++ "ClearPortFeature USB_PORT_FEAT_C_CONNECTION\n"); ++ dwc_otg_hcd->flags.b.port_connect_status_change = 0; ++ break; ++ case UHF_C_PORT_RESET: ++ /* Clears the driver's internal Port Reset Change ++ * flag */ ++ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - " ++ "ClearPortFeature USB_PORT_FEAT_C_RESET\n"); ++ dwc_otg_hcd->flags.b.port_reset_change = 0; ++ break; ++ case UHF_C_PORT_ENABLE: ++ /* Clears the driver's internal Port ++ * Enable/Disable Change flag */ ++ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - " ++ "ClearPortFeature USB_PORT_FEAT_C_ENABLE\n"); ++ dwc_otg_hcd->flags.b.port_enable_change = 0; ++ break; ++ case UHF_C_PORT_SUSPEND: ++ /* Clears the driver's internal Port Suspend ++ * Change flag, which is set when resume signaling on ++ * the host port is complete */ ++ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - " ++ "ClearPortFeature USB_PORT_FEAT_C_SUSPEND\n"); ++ dwc_otg_hcd->flags.b.port_suspend_change = 0; ++ break; ++#ifdef CONFIG_USB_DWC_OTG_LPM ++ case UHF_C_PORT_L1: ++ dwc_otg_hcd->flags.b.port_l1_change = 0; ++ break; ++#endif ++ case UHF_C_PORT_OVER_CURRENT: ++ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - " ++ "ClearPortFeature USB_PORT_FEAT_C_OVER_CURRENT\n"); ++ dwc_otg_hcd->flags.b.port_over_current_change = 0; ++ break; ++ default: ++ retval = -DWC_E_INVALID; ++ DWC_ERROR("DWC OTG HCD - " ++ "ClearPortFeature request %xh " ++ "unknown or unsupported\n", wValue); ++ } ++ break; ++ case UCR_GET_HUB_DESCRIPTOR: ++ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - " ++ "GetHubDescriptor\n"); ++ hub_desc = (usb_hub_descriptor_t *) buf; ++ hub_desc->bDescLength = 9; ++ hub_desc->bDescriptorType = 0x29; ++ hub_desc->bNbrPorts = 1; ++ USETW(hub_desc->wHubCharacteristics, 0x08); ++ hub_desc->bPwrOn2PwrGood = 1; ++ hub_desc->bHubContrCurrent = 0; ++ hub_desc->DeviceRemovable[0] = 0; ++ hub_desc->DeviceRemovable[1] = 0xff; ++ break; ++ case UCR_GET_HUB_STATUS: ++ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - " ++ "GetHubStatus\n"); ++ DWC_MEMSET(buf, 0, 4); ++ break; ++ case UCR_GET_PORT_STATUS: ++ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - " ++ "GetPortStatus\n"); ++ if (!wIndex || wIndex > 1) ++ goto error; ++ ++ port_status = 0; ++ ++ if (dwc_otg_hcd->flags.b.port_connect_status_change) ++ port_status |= (1 << UHF_C_PORT_CONNECTION); ++ ++ if (dwc_otg_hcd->flags.b.port_enable_change) ++ port_status |= (1 << UHF_C_PORT_ENABLE); ++ ++ if (dwc_otg_hcd->flags.b.port_suspend_change) ++ port_status |= (1 << UHF_C_PORT_SUSPEND); ++ ++ if (dwc_otg_hcd->flags.b.port_l1_change) ++ port_status |= (1 << UHF_C_PORT_L1); ++ ++ if (dwc_otg_hcd->flags.b.port_reset_change) { ++ port_status |= (1 << UHF_C_PORT_RESET); ++ } ++ ++ if (dwc_otg_hcd->flags.b.port_over_current_change) { ++ DWC_ERROR("Device Not Supported\n"); ++ port_status |= (1 << UHF_C_PORT_OVER_CURRENT); ++ } ++ ++ if (!dwc_otg_hcd->flags.b.port_connect_status) { ++ /* ++ * The port is disconnected, which means the core is ++ * either in device mode or it soon will be. Just ++ * return 0's for the remainder of the port status ++ * since the port register can't be read if the core ++ * is in device mode. ++ */ ++ *((__le32 *) buf) = dwc_cpu_to_le32(&port_status); ++ break; ++ } ++ ++ hprt0.d32 = dwc_read_reg32(core_if->host_if->hprt0); ++ DWC_DEBUGPL(DBG_HCDV, " HPRT0: 0x%08x\n", hprt0.d32); ++ ++ if (hprt0.b.prtconnsts) ++ port_status |= (1 << UHF_PORT_CONNECTION); ++ ++ if (hprt0.b.prtena) ++ port_status |= (1 << UHF_PORT_ENABLE); ++ ++ if (hprt0.b.prtsusp) ++ port_status |= (1 << UHF_PORT_SUSPEND); ++ ++ if (hprt0.b.prtovrcurract) ++ port_status |= (1 << UHF_PORT_OVER_CURRENT); ++ ++ if (hprt0.b.prtrst) ++ port_status |= (1 << UHF_PORT_RESET); ++ ++ if (hprt0.b.prtpwr) ++ port_status |= (1 << UHF_PORT_POWER); ++ ++ if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_HIGH_SPEED) ++ port_status |= (1 << UHF_PORT_HIGH_SPEED); ++ else if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_LOW_SPEED) ++ port_status |= (1 << UHF_PORT_LOW_SPEED); ++ ++ if (hprt0.b.prttstctl) ++ port_status |= (1 << UHF_PORT_TEST); ++ if (dwc_otg_get_lpm_portsleepstatus(dwc_otg_hcd->core_if)) { ++ port_status |= (1 << UHF_PORT_L1); ++ } ++ ++ /* USB_PORT_FEAT_INDICATOR unsupported always 0 */ ++ ++ *((__le32 *) buf) = dwc_cpu_to_le32(&port_status); ++ ++ break; ++ case UCR_SET_HUB_FEATURE: ++ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - " ++ "SetHubFeature\n"); ++ /* No HUB features supported */ ++ break; ++ case UCR_SET_PORT_FEATURE: ++ if (wValue != UHF_PORT_TEST && (!wIndex || wIndex > 1)) ++ goto error; ++ ++ if (!dwc_otg_hcd->flags.b.port_connect_status) { ++ /* ++ * The port is disconnected, which means the core is ++ * either in device mode or it soon will be. Just ++ * return without doing anything since the port ++ * register can't be written if the core is in device ++ * mode. ++ */ ++ break; ++ } ++ ++ switch (wValue) { ++ case UHF_PORT_SUSPEND: ++ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - " ++ "SetPortFeature - USB_PORT_FEAT_SUSPEND\n"); ++ if (dwc_otg_hcd_otg_port(dwc_otg_hcd) == wIndex && ++ dwc_otg_hcd->fops->get_b_hnp_enable(dwc_otg_hcd)) { ++ gotgctl_data_t gotgctl = {.d32 = 0 }; ++ gotgctl.b.hstsethnpen = 1; ++ dwc_modify_reg32(&core_if->core_global_regs-> ++ gotgctl, 0, gotgctl.d32); ++ core_if->op_state = A_SUSPEND; ++ } ++ hprt0.d32 = dwc_otg_read_hprt0(core_if); ++ hprt0.b.prtsusp = 1; ++ dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32); ++ { ++ uint64_t flags; ++ /* Update lx_state */ ++ DWC_SPINLOCK_IRQSAVE(dwc_otg_hcd->lock, &flags); ++ core_if->lx_state = DWC_OTG_L2; ++ DWC_SPINUNLOCK_IRQRESTORE(dwc_otg_hcd->lock, flags); ++ } ++ /* Suspend the Phy Clock */ ++ { ++ pcgcctl_data_t pcgcctl = {.d32 = 0 }; ++ pcgcctl.b.stoppclk = 1; ++ dwc_modify_reg32(core_if->pcgcctl, 0, ++ pcgcctl.d32); ++ } ++ ++ /* For HNP the bus must be suspended for at least 200ms. */ ++ if (dwc_otg_hcd->fops->get_b_hnp_enable(dwc_otg_hcd)) { ++ dwc_mdelay(200); ++ } ++ break; ++ case UHF_PORT_POWER: ++ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - " ++ "SetPortFeature - USB_PORT_FEAT_POWER\n"); ++ hprt0.d32 = dwc_otg_read_hprt0(core_if); ++ hprt0.b.prtpwr = 1; ++ dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32); ++ break; ++ case UHF_PORT_RESET: ++ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - " ++ "SetPortFeature - USB_PORT_FEAT_RESET\n"); ++ { ++ pcgcctl_data_t pcgcctl = {.d32 = 0 }; ++ pcgcctl.b.enbl_sleep_gating = 1; ++ pcgcctl.b.stoppclk = 1; ++ dwc_modify_reg32(core_if->pcgcctl, pcgcctl.d32, ++ 0); ++ dwc_write_reg32(core_if->pcgcctl, 0); ++ } ++#ifdef CONFIG_USB_DWC_OTG_LPM ++ { ++ glpmcfg_data_t lpmcfg; ++ lpmcfg.d32 = ++ dwc_read_reg32(&core_if->core_global_regs-> ++ glpmcfg); ++ if (lpmcfg.b.prt_sleep_sts) { ++ lpmcfg.b.en_utmi_sleep = 0; ++ lpmcfg.b.hird_thres &= (~(1 << 4)); ++ dwc_write_reg32(&core_if-> ++ core_global_regs-> ++ glpmcfg, lpmcfg.d32); ++ dwc_mdelay(1); ++ } ++ } ++#endif ++ hprt0.d32 = dwc_otg_read_hprt0(core_if); ++ /* When B-Host the Port reset bit is set in ++ * the Start HCD Callback function, so that ++ * the reset is started within 1ms of the HNP ++ * success interrupt. */ ++ if (!dwc_otg_hcd_is_b_host(dwc_otg_hcd)) { ++ hprt0.b.prtrst = 1; ++ dwc_write_reg32(core_if->host_if->hprt0, ++ hprt0.d32); ++ } ++ /* Clear reset bit in 10ms (FS/LS) or 50ms (HS) */ ++ dwc_mdelay(60); ++ hprt0.b.prtrst = 0; ++ dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32); ++ core_if->lx_state = DWC_OTG_L0; /* Now back to the on state */ ++ break; ++#ifdef DWC_HS_ELECT_TST ++ case UHF_PORT_TEST: ++ { ++ uint32_t t; ++ gintmsk_data_t gintmsk; ++ ++ t = (wIndex >> 8); /* MSB wIndex USB */ ++ DWC_DEBUGPL(DBG_HCD, ++ "DWC OTG HCD HUB CONTROL - " ++ "SetPortFeature - USB_PORT_FEAT_TEST %d\n", ++ t); ++ DWC_WARN("USB_PORT_FEAT_TEST %d\n", t); ++ if (t < 6) { ++ hprt0.d32 = dwc_otg_read_hprt0(core_if); ++ hprt0.b.prttstctl = t; ++ dwc_write_reg32(core_if->host_if->hprt0, ++ hprt0.d32); ++ } else { ++ /* Setup global vars with reg addresses (quick and ++ * dirty hack, should be cleaned up) ++ */ ++ global_regs = core_if->core_global_regs; ++ hc_global_regs = ++ core_if->host_if->host_global_regs; ++ hc_regs = ++ (dwc_otg_hc_regs_t *) ((char *) ++ global_regs + ++ 0x500); ++ data_fifo = ++ (uint32_t *) ((char *)global_regs + ++ 0x1000); ++ ++ if (t == 6) { /* HS_HOST_PORT_SUSPEND_RESUME */ ++ /* Save current interrupt mask */ ++ gintmsk.d32 = ++ dwc_read_reg32 ++ (&global_regs->gintmsk); ++ ++ /* Disable all interrupts while we muck with ++ * the hardware directly ++ */ ++ dwc_write_reg32(&global_regs-> ++ gintmsk, 0); ++ ++ /* 15 second delay per the test spec */ ++ dwc_mdelay(15000); ++ ++ /* Drive suspend on the root port */ ++ hprt0.d32 = ++ dwc_otg_read_hprt0(core_if); ++ hprt0.b.prtsusp = 1; ++ hprt0.b.prtres = 0; ++ dwc_write_reg32(core_if-> ++ host_if->hprt0, ++ hprt0.d32); ++ ++ /* 15 second delay per the test spec */ ++ dwc_mdelay(15000); ++ ++ /* Drive resume on the root port */ ++ hprt0.d32 = ++ dwc_otg_read_hprt0(core_if); ++ hprt0.b.prtsusp = 0; ++ hprt0.b.prtres = 1; ++ dwc_write_reg32(core_if-> ++ host_if->hprt0, ++ hprt0.d32); ++ dwc_mdelay(100); ++ ++ /* Clear the resume bit */ ++ hprt0.b.prtres = 0; ++ dwc_write_reg32(core_if-> ++ host_if->hprt0, ++ hprt0.d32); ++ ++ /* Restore interrupts */ ++ dwc_write_reg32(&global_regs-> ++ gintmsk, ++ gintmsk.d32); ++ } else if (t == 7) { /* SINGLE_STEP_GET_DEVICE_DESCRIPTOR setup */ ++ /* Save current interrupt mask */ ++ gintmsk.d32 = ++ dwc_read_reg32 ++ (&global_regs->gintmsk); ++ ++ /* Disable all interrupts while we muck with ++ * the hardware directly ++ */ ++ dwc_write_reg32(&global_regs-> ++ gintmsk, 0); ++ ++ /* 15 second delay per the test spec */ ++ dwc_mdelay(15000); ++ ++ /* Send the Setup packet */ ++ do_setup(); ++ ++ /* 15 second delay so nothing else happens for awhile */ ++ dwc_mdelay(15000); ++ ++ /* Restore interrupts */ ++ dwc_write_reg32(&global_regs-> ++ gintmsk, ++ gintmsk.d32); ++ } else if (t == 8) { /* SINGLE_STEP_GET_DEVICE_DESCRIPTOR execute */ ++ /* Save current interrupt mask */ ++ gintmsk.d32 = ++ dwc_read_reg32 ++ (&global_regs->gintmsk); ++ ++ /* Disable all interrupts while we muck with ++ * the hardware directly ++ */ ++ dwc_write_reg32(&global_regs-> ++ gintmsk, 0); ++ ++ /* Send the Setup packet */ ++ do_setup(); ++ ++ /* 15 second delay so nothing else happens for awhile */ ++ dwc_mdelay(15000); ++ ++ /* Send the In and Ack packets */ ++ do_in_ack(); ++ ++ /* 15 second delay so nothing else happens for awhile */ ++ dwc_mdelay(15000); ++ ++ /* Restore interrupts */ ++ dwc_write_reg32(&global_regs-> ++ gintmsk, ++ gintmsk.d32); ++ } ++ } ++ break; ++ } ++#endif /* DWC_HS_ELECT_TST */ ++ ++ case UHF_PORT_INDICATOR: ++ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - " ++ "SetPortFeature - USB_PORT_FEAT_INDICATOR\n"); ++ /* Not supported */ ++ break; ++ default: ++ retval = -DWC_E_INVALID; ++ DWC_ERROR("DWC OTG HCD - " ++ "SetPortFeature request %xh " ++ "unknown or unsupported\n", wValue); ++ break; ++ } ++ break; ++#ifdef CONFIG_USB_DWC_OTG_LPM ++ case UCR_SET_AND_TEST_PORT_FEATURE: ++ if (wValue != UHF_PORT_L1) { ++ goto error; ++ } ++ { ++ int portnum, hird, devaddr, remwake; ++ glpmcfg_data_t lpmcfg; ++ uint32_t time_usecs; ++ gintsts_data_t gintsts; ++ gintmsk_data_t gintmsk; ++ ++ if (!dwc_otg_get_param_lpm_enable(core_if)) { ++ goto error; ++ } ++ if (wValue != UHF_PORT_L1 || wLength != 1) { ++ goto error; ++ } ++ /* Check if the port currently is in SLEEP state */ ++ lpmcfg.d32 = ++ dwc_read_reg32(&core_if->core_global_regs->glpmcfg); ++ if (lpmcfg.b.prt_sleep_sts) { ++ DWC_INFO("Port is already in sleep mode\n"); ++ buf[0] = 0; /* Return success */ ++ break; ++ } ++ ++ portnum = wIndex & 0xf; ++ hird = (wIndex >> 4) & 0xf; ++ devaddr = (wIndex >> 8) & 0x7f; ++ remwake = (wIndex >> 15); ++ ++ if (portnum != 1) { ++ retval = -DWC_E_INVALID; ++ DWC_WARN ++ ("Wrong port number(%d) in SetandTestPortFeature request\n", ++ portnum); ++ break; ++ } ++ ++ DWC_PRINTF ++ ("SetandTestPortFeature request: portnum = %d, hird = %d, devaddr = %d, rewake = %d\n", ++ portnum, hird, devaddr, remwake); ++ /* Disable LPM interrupt */ ++ gintmsk.d32 = 0; ++ gintmsk.b.lpmtranrcvd = 1; ++ dwc_modify_reg32(&core_if->core_global_regs->gintmsk, ++ gintmsk.d32, 0); ++ ++ if (dwc_otg_hcd_send_lpm ++ (dwc_otg_hcd, devaddr, hird, remwake)) { ++ retval = -DWC_E_INVALID; ++ break; ++ } ++ ++ time_usecs = 10 * (lpmcfg.b.retry_count + 1); ++ /* We will consider timeout if time_usecs microseconds pass, ++ * and we don't receive LPM transaction status. ++ * After receiving non-error responce(ACK/NYET/STALL) from device, ++ * core will set lpmtranrcvd bit. ++ */ ++ do { ++ gintsts.d32 = ++ dwc_read_reg32(&core_if->core_global_regs-> ++ gintsts); ++ if (gintsts.b.lpmtranrcvd) { ++ break; ++ } ++ dwc_udelay(1); ++ } while (--time_usecs); ++ /* lpm_int bit will be cleared in LPM interrupt handler */ ++ ++ /* Now fill status ++ * 0x00 - Success ++ * 0x10 - NYET ++ * 0x11 - Timeout ++ */ ++ if (!gintsts.b.lpmtranrcvd) { ++ buf[0] = 0x3; /* Completion code is Timeout */ ++ dwc_otg_hcd_free_hc_from_lpm(dwc_otg_hcd); ++ } else { ++ lpmcfg.d32 = ++ dwc_read_reg32(&core_if->core_global_regs-> ++ glpmcfg); ++ if (lpmcfg.b.lpm_resp == 0x3) { ++ /* ACK responce from the device */ ++ buf[0] = 0x00; /* Success */ ++ } else if (lpmcfg.b.lpm_resp == 0x2) { ++ /* NYET responce from the device */ ++ buf[0] = 0x2; ++ } else { ++ /* Otherwise responce with Timeout */ ++ buf[0] = 0x3; ++ } ++ } ++ DWC_PRINTF("Device responce to LPM trans is %x\n", ++ lpmcfg.b.lpm_resp); ++ dwc_modify_reg32(&core_if->core_global_regs->gintmsk, 0, ++ gintmsk.d32); ++ ++ break; ++ } ++#endif /* CONFIG_USB_DWC_OTG_LPM */ ++ default: ++ error: ++ retval = -DWC_E_INVALID; ++ DWC_WARN("DWC OTG HCD - " ++ "Unknown hub control request type or invalid typeReq: %xh wIndex: %xh wValue: %xh\n", ++ typeReq, wIndex, wValue); ++ break; ++ } ++ ++ return retval; ++} ++ ++#ifdef CONFIG_USB_DWC_OTG_LPM ++/** Returns index of host channel to perform LPM transaction. */ ++int dwc_otg_hcd_get_hc_for_lpm_tran(dwc_otg_hcd_t * hcd, uint8_t devaddr) ++{ ++ dwc_otg_core_if_t *core_if = hcd->core_if; ++ dwc_hc_t *hc; ++ hcchar_data_t hcchar; ++ gintmsk_data_t gintmsk = {.d32 = 0 }; ++ ++ if (DWC_CIRCLEQ_EMPTY(&hcd->free_hc_list)) { ++ DWC_PRINTF("No free channel to select for LPM transaction\n"); ++ return -1; ++ } ++ ++ hc = DWC_CIRCLEQ_FIRST(&hcd->free_hc_list); ++ ++ /* Mask host channel interrupts. */ ++ gintmsk.b.hcintr = 1; ++ dwc_modify_reg32(&core_if->core_global_regs->gintmsk, gintmsk.d32, 0); ++ ++ /* Fill fields that core needs for LPM transaction */ ++ hcchar.b.devaddr = devaddr; ++ hcchar.b.epnum = 0; ++ hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL; ++ hcchar.b.mps = 64; ++ hcchar.b.lspddev = (hc->speed == DWC_OTG_EP_SPEED_LOW); ++ hcchar.b.epdir = 0; /* OUT */ ++ dwc_write_reg32(&core_if->host_if->hc_regs[hc->hc_num]->hcchar, ++ hcchar.d32); ++ ++ /* Remove the host channel from the free list. */ ++ DWC_CIRCLEQ_REMOVE_INIT(&hcd->free_hc_list, hc, hc_list_entry); ++ ++ DWC_PRINTF("hcnum = %d devaddr = %d\n", hc->hc_num, devaddr); ++ ++ return hc->hc_num; ++} ++ ++/** Release hc after performing LPM transaction */ ++void dwc_otg_hcd_free_hc_from_lpm(dwc_otg_hcd_t * hcd) ++{ ++ dwc_hc_t *hc; ++ glpmcfg_data_t lpmcfg; ++ uint8_t hc_num; ++ ++ lpmcfg.d32 = dwc_read_reg32(&hcd->core_if->core_global_regs->glpmcfg); ++ hc_num = lpmcfg.b.lpm_chan_index; ++ ++ hc = hcd->hc_ptr_array[hc_num]; ++ ++ DWC_PRINTF("Freeing channel %d after LPM\n", hc_num); ++ /* Return host channel to free list */ ++ DWC_CIRCLEQ_INSERT_TAIL(&hcd->free_hc_list, hc, hc_list_entry); ++} ++ ++int dwc_otg_hcd_send_lpm(dwc_otg_hcd_t * hcd, uint8_t devaddr, uint8_t hird, ++ uint8_t bRemoteWake) ++{ ++ glpmcfg_data_t lpmcfg; ++ pcgcctl_data_t pcgcctl = {.d32 = 0 }; ++ int channel; ++ ++ channel = dwc_otg_hcd_get_hc_for_lpm_tran(hcd, devaddr); ++ if (channel < 0) { ++ return channel; ++ } ++ ++ pcgcctl.b.enbl_sleep_gating = 1; ++ dwc_modify_reg32(hcd->core_if->pcgcctl, 0, pcgcctl.d32); ++ ++ /* Read LPM config register */ ++ lpmcfg.d32 = dwc_read_reg32(&hcd->core_if->core_global_regs->glpmcfg); ++ ++ /* Program LPM transaction fields */ ++ lpmcfg.b.rem_wkup_en = bRemoteWake; ++ lpmcfg.b.hird = hird; ++ lpmcfg.b.hird_thres = 0x1c; ++ lpmcfg.b.lpm_chan_index = channel; ++ lpmcfg.b.en_utmi_sleep = 1; ++ /* Program LPM config register */ ++ dwc_write_reg32(&hcd->core_if->core_global_regs->glpmcfg, lpmcfg.d32); ++ ++ /* Send LPM transaction */ ++ lpmcfg.b.send_lpm = 1; ++ dwc_write_reg32(&hcd->core_if->core_global_regs->glpmcfg, lpmcfg.d32); ++ ++ return 0; ++} ++ ++#endif /* CONFIG_USB_DWC_OTG_LPM */ ++ ++int dwc_otg_hcd_is_status_changed(dwc_otg_hcd_t * hcd, int port) ++{ ++ int retval; ++ ++ if (port != 1) { ++ return -DWC_E_INVALID; ++ } ++ ++ retval = (hcd->flags.b.port_connect_status_change || ++ hcd->flags.b.port_reset_change || ++ hcd->flags.b.port_enable_change || ++ hcd->flags.b.port_suspend_change || ++ hcd->flags.b.port_over_current_change); ++#ifdef DEBUG ++ if (retval) { ++ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB STATUS DATA:" ++ " Root port status changed\n"); ++ DWC_DEBUGPL(DBG_HCDV, " port_connect_status_change: %d\n", ++ hcd->flags.b.port_connect_status_change); ++ DWC_DEBUGPL(DBG_HCDV, " port_reset_change: %d\n", ++ hcd->flags.b.port_reset_change); ++ DWC_DEBUGPL(DBG_HCDV, " port_enable_change: %d\n", ++ hcd->flags.b.port_enable_change); ++ DWC_DEBUGPL(DBG_HCDV, " port_suspend_change: %d\n", ++ hcd->flags.b.port_suspend_change); ++ DWC_DEBUGPL(DBG_HCDV, " port_over_current_change: %d\n", ++ hcd->flags.b.port_over_current_change); ++ } ++#endif ++ return retval; ++} ++ ++int dwc_otg_hcd_get_frame_number(dwc_otg_hcd_t * dwc_otg_hcd) ++{ ++ hfnum_data_t hfnum; ++ hfnum.d32 = dwc_read_reg32(&dwc_otg_hcd->core_if-> ++ host_if->host_global_regs->hfnum); ++ ++#ifdef DEBUG_SOF ++ DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD GET FRAME NUMBER %d\n", ++ hfnum.b.frnum); ++#endif ++ return hfnum.b.frnum; ++} ++ ++int dwc_otg_hcd_start(dwc_otg_hcd_t * hcd, ++ struct dwc_otg_hcd_function_ops *fops) ++{ ++ int retval = 0; ++ ++ hcd->fops = fops; ++ if (!dwc_otg_is_device_mode(hcd->core_if)) { ++ dwc_otg_hcd_reinit(hcd); ++ } else { ++ retval = -DWC_E_NO_DEVICE; ++ } ++ ++ return retval; ++} ++ ++void *dwc_otg_hcd_get_priv_data(dwc_otg_hcd_t * hcd) ++{ ++ return hcd->priv; ++} ++ ++void dwc_otg_hcd_set_priv_data(dwc_otg_hcd_t * hcd, void *priv_data) ++{ ++ hcd->priv = priv_data; ++} ++ ++uint32_t dwc_otg_hcd_otg_port(dwc_otg_hcd_t * hcd) ++{ ++ return hcd->otg_port; ++} ++ ++uint32_t dwc_otg_hcd_is_b_host(dwc_otg_hcd_t * hcd) ++{ ++ uint32_t is_b_host; ++ if (hcd->core_if->op_state == B_HOST) { ++ is_b_host = 1; ++ } else { ++ is_b_host = 0; ++ } ++ ++ return is_b_host; ++} ++ ++dwc_otg_hcd_urb_t *dwc_otg_hcd_urb_alloc(dwc_otg_hcd_t * hcd, ++ int iso_desc_count, int atomic_alloc) ++{ ++ dwc_otg_hcd_urb_t *dwc_otg_urb; ++ uint32_t size; ++ ++ size = ++ sizeof(*dwc_otg_urb) + ++ iso_desc_count * sizeof(struct dwc_otg_hcd_iso_packet_desc); ++ if (atomic_alloc) { ++ dwc_otg_urb = dwc_alloc_atomic(size); ++ } else { ++ dwc_otg_urb = dwc_alloc(size); ++ } ++ dwc_otg_urb->packet_count = iso_desc_count; ++ ++ return dwc_otg_urb; ++} ++ ++void dwc_otg_hcd_urb_set_pipeinfo(dwc_otg_hcd_urb_t * dwc_otg_urb, ++ uint8_t dev_addr, uint8_t ep_num, ++ uint8_t ep_type, uint8_t ep_dir, uint16_t mps) ++{ ++ dwc_otg_hcd_fill_pipe(&dwc_otg_urb->pipe_info, dev_addr, ep_num, ++ ep_type, ep_dir, mps); ++#if 0 ++ DWC_PRINTF ++ ("addr = %d, ep_num = %d, ep_dir = 0x%x, ep_type = 0x%x, mps = %d\n", ++ dev_addr, ep_num, ep_dir, ep_type, mps); ++#endif ++} ++ ++void dwc_otg_hcd_urb_set_params(dwc_otg_hcd_urb_t * dwc_otg_urb, ++ void *urb_handle, void *buf, dwc_dma_t dma, ++ uint32_t buflen, void *setup_packet, ++ dwc_dma_t setup_dma, uint32_t flags, ++ uint16_t interval) ++{ ++ dwc_otg_urb->priv = urb_handle; ++ dwc_otg_urb->buf = buf; ++ dwc_otg_urb->dma = dma; ++ dwc_otg_urb->length = buflen; ++ dwc_otg_urb->setup_packet = setup_packet; ++ dwc_otg_urb->setup_dma = setup_dma; ++ dwc_otg_urb->flags = flags; ++ dwc_otg_urb->interval = interval; ++ dwc_otg_urb->status = -DWC_E_IN_PROGRESS; ++} ++ ++uint32_t dwc_otg_hcd_urb_get_status(dwc_otg_hcd_urb_t * dwc_otg_urb) ++{ ++ return dwc_otg_urb->status; ++} ++ ++uint32_t dwc_otg_hcd_urb_get_actual_length(dwc_otg_hcd_urb_t * dwc_otg_urb) ++{ ++ return dwc_otg_urb->actual_length; ++} ++ ++uint32_t dwc_otg_hcd_urb_get_error_count(dwc_otg_hcd_urb_t * dwc_otg_urb) ++{ ++ return dwc_otg_urb->error_count; ++} ++ ++void dwc_otg_hcd_urb_set_iso_desc_params(dwc_otg_hcd_urb_t * dwc_otg_urb, ++ int desc_num, uint32_t offset, ++ uint32_t length) ++{ ++ dwc_otg_urb->iso_descs[desc_num].offset = offset; ++ dwc_otg_urb->iso_descs[desc_num].length = length; ++} ++ ++uint32_t dwc_otg_hcd_urb_get_iso_desc_status(dwc_otg_hcd_urb_t * dwc_otg_urb, ++ int desc_num) ++{ ++ return dwc_otg_urb->iso_descs[desc_num].status; ++} ++ ++uint32_t dwc_otg_hcd_urb_get_iso_desc_actual_length(dwc_otg_hcd_urb_t * ++ dwc_otg_urb, int desc_num) ++{ ++ return dwc_otg_urb->iso_descs[desc_num].actual_length; ++} ++ ++int dwc_otg_hcd_is_bandwidth_allocated(dwc_otg_hcd_t * hcd, void *ep_handle) ++{ ++ int allocated = 0; ++ dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle; ++ ++ if (qh) { ++ if (!DWC_LIST_EMPTY(&qh->qh_list_entry)) { ++ allocated = 1; ++ } ++ } ++ return allocated; ++} ++ ++int dwc_otg_hcd_is_bandwidth_freed(dwc_otg_hcd_t * hcd, void *ep_handle) ++{ ++ dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle; ++ int freed = 0; ++ DWC_ASSERT(qh, "qh is not allocated\n"); ++ ++ if (DWC_LIST_EMPTY(&qh->qh_list_entry)) { ++ freed = 1; ++ } ++ ++ return freed; ++} ++ ++uint8_t dwc_otg_hcd_get_ep_bandwidth(dwc_otg_hcd_t * hcd, void *ep_handle) ++{ ++ dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle; ++ DWC_ASSERT(qh, "qh is not allocated\n"); ++ return qh->usecs; ++} ++ ++void dwc_otg_hcd_dump_state(dwc_otg_hcd_t * hcd) ++{ ++#ifdef DEBUG ++ int num_channels; ++ int i; ++ gnptxsts_data_t np_tx_status; ++ hptxsts_data_t p_tx_status; ++ ++ num_channels = hcd->core_if->core_params->host_channels; ++ DWC_PRINTF("\n"); ++ DWC_PRINTF ++ ("************************************************************\n"); ++ DWC_PRINTF("HCD State:\n"); ++ DWC_PRINTF(" Num channels: %d\n", num_channels); ++ for (i = 0; i < num_channels; i++) { ++ dwc_hc_t *hc = hcd->hc_ptr_array[i]; ++ DWC_PRINTF(" Channel %d:\n", i); ++ DWC_PRINTF(" dev_addr: %d, ep_num: %d, ep_is_in: %d\n", ++ hc->dev_addr, hc->ep_num, hc->ep_is_in); ++ DWC_PRINTF(" speed: %d\n", hc->speed); ++ DWC_PRINTF(" ep_type: %d\n", hc->ep_type); ++ DWC_PRINTF(" max_packet: %d\n", hc->max_packet); ++ DWC_PRINTF(" data_pid_start: %d\n", hc->data_pid_start); ++ DWC_PRINTF(" multi_count: %d\n", hc->multi_count); ++ DWC_PRINTF(" xfer_started: %d\n", hc->xfer_started); ++ DWC_PRINTF(" xfer_buff: %p\n", hc->xfer_buff); ++ DWC_PRINTF(" xfer_len: %d\n", hc->xfer_len); ++ DWC_PRINTF(" xfer_count: %d\n", hc->xfer_count); ++ DWC_PRINTF(" halt_on_queue: %d\n", hc->halt_on_queue); ++ DWC_PRINTF(" halt_pending: %d\n", hc->halt_pending); ++ DWC_PRINTF(" halt_status: %d\n", hc->halt_status); ++ DWC_PRINTF(" do_split: %d\n", hc->do_split); ++ DWC_PRINTF(" complete_split: %d\n", hc->complete_split); ++ DWC_PRINTF(" hub_addr: %d\n", hc->hub_addr); ++ DWC_PRINTF(" port_addr: %d\n", hc->port_addr); ++ DWC_PRINTF(" xact_pos: %d\n", hc->xact_pos); ++ DWC_PRINTF(" requests: %d\n", hc->requests); ++ DWC_PRINTF(" qh: %p\n", hc->qh); ++ if (hc->xfer_started) { ++ hfnum_data_t hfnum; ++ hcchar_data_t hcchar; ++ hctsiz_data_t hctsiz; ++ hcint_data_t hcint; ++ hcintmsk_data_t hcintmsk; ++ hfnum.d32 = ++ dwc_read_reg32(&hcd->core_if->host_if-> ++ host_global_regs->hfnum); ++ hcchar.d32 = ++ dwc_read_reg32(&hcd->core_if->host_if->hc_regs[i]-> ++ hcchar); ++ hctsiz.d32 = ++ dwc_read_reg32(&hcd->core_if->host_if->hc_regs[i]-> ++ hctsiz); ++ hcint.d32 = ++ dwc_read_reg32(&hcd->core_if->host_if->hc_regs[i]-> ++ hcint); ++ hcintmsk.d32 = ++ dwc_read_reg32(&hcd->core_if->host_if->hc_regs[i]-> ++ hcintmsk); ++ DWC_PRINTF(" hfnum: 0x%08x\n", hfnum.d32); ++ DWC_PRINTF(" hcchar: 0x%08x\n", hcchar.d32); ++ DWC_PRINTF(" hctsiz: 0x%08x\n", hctsiz.d32); ++ DWC_PRINTF(" hcint: 0x%08x\n", hcint.d32); ++ DWC_PRINTF(" hcintmsk: 0x%08x\n", hcintmsk.d32); ++ } ++ if (hc->xfer_started && hc->qh) { ++ dwc_otg_qtd_t *qtd; ++ dwc_otg_hcd_urb_t *urb; ++ ++ DWC_CIRCLEQ_FOREACH(qtd, &hc->qh->qtd_list, qtd_list_entry) { ++ if(!qtd->in_process) ++ break; ++ ++ urb = qtd->urb; ++ DWC_PRINTF(" URB Info:\n"); ++ DWC_PRINTF(" qtd: %p, urb: %p\n", qtd, urb); ++ if (urb) { ++ DWC_PRINTF(" Dev: %d, EP: %d %s\n", ++ dwc_otg_hcd_get_dev_addr(&urb-> ++ pipe_info), ++ dwc_otg_hcd_get_ep_num(&urb-> ++ pipe_info), ++ dwc_otg_hcd_is_pipe_in(&urb-> ++ pipe_info) ? ++ "IN" : "OUT"); ++ DWC_PRINTF(" Max packet size: %d\n", ++ dwc_otg_hcd_get_mps(&urb-> ++ pipe_info)); ++ DWC_PRINTF(" transfer_buffer: %p\n", ++ urb->buf); ++ DWC_PRINTF(" transfer_dma: %p\n", ++ (void *)urb->dma); ++ DWC_PRINTF(" transfer_buffer_length: %d\n", ++ urb->length); ++ DWC_PRINTF(" actual_length: %d\n", ++ urb->actual_length); ++ } ++ } ++ } ++ } ++ DWC_PRINTF(" non_periodic_channels: %d\n", hcd->non_periodic_channels); ++ DWC_PRINTF(" periodic_channels: %d\n", hcd->periodic_channels); ++ DWC_PRINTF(" periodic_usecs: %d\n", hcd->periodic_usecs); ++ np_tx_status.d32 = ++ dwc_read_reg32(&hcd->core_if->core_global_regs->gnptxsts); ++ DWC_PRINTF(" NP Tx Req Queue Space Avail: %d\n", ++ np_tx_status.b.nptxqspcavail); ++ DWC_PRINTF(" NP Tx FIFO Space Avail: %d\n", ++ np_tx_status.b.nptxfspcavail); ++ p_tx_status.d32 = ++ dwc_read_reg32(&hcd->core_if->host_if->host_global_regs->hptxsts); ++ DWC_PRINTF(" P Tx Req Queue Space Avail: %d\n", ++ p_tx_status.b.ptxqspcavail); ++ DWC_PRINTF(" P Tx FIFO Space Avail: %d\n", p_tx_status.b.ptxfspcavail); ++ dwc_otg_hcd_dump_frrem(hcd); ++ dwc_otg_dump_global_registers(hcd->core_if); ++ dwc_otg_dump_host_registers(hcd->core_if); ++ DWC_PRINTF ++ ("************************************************************\n"); ++ DWC_PRINTF("\n"); ++#endif ++} ++ ++#ifdef DEBUG ++void dwc_print_setup_data(uint8_t * setup) ++{ ++ int i; ++ if (CHK_DEBUG_LEVEL(DBG_HCD)) { ++ DWC_PRINTF("Setup Data = MSB "); ++ for (i = 7; i >= 0; i--) ++ DWC_PRINTF("%02x ", setup[i]); ++ DWC_PRINTF("\n"); ++ DWC_PRINTF(" bmRequestType Tranfer = %s\n", ++ (setup[0] & 0x80) ? "Device-to-Host" : ++ "Host-to-Device"); ++ DWC_PRINTF(" bmRequestType Type = "); ++ switch ((setup[0] & 0x60) >> 5) { ++ case 0: ++ DWC_PRINTF("Standard\n"); ++ break; ++ case 1: ++ DWC_PRINTF("Class\n"); ++ break; ++ case 2: ++ DWC_PRINTF("Vendor\n"); ++ break; ++ case 3: ++ DWC_PRINTF("Reserved\n"); ++ break; ++ } ++ DWC_PRINTF(" bmRequestType Recipient = "); ++ switch (setup[0] & 0x1f) { ++ case 0: ++ DWC_PRINTF("Device\n"); ++ break; ++ case 1: ++ DWC_PRINTF("Interface\n"); ++ break; ++ case 2: ++ DWC_PRINTF("Endpoint\n"); ++ break; ++ case 3: ++ DWC_PRINTF("Other\n"); ++ break; ++ default: ++ DWC_PRINTF("Reserved\n"); ++ break; ++ } ++ DWC_PRINTF(" bRequest = 0x%0x\n", setup[1]); ++ DWC_PRINTF(" wValue = 0x%0x\n", *((uint16_t *) & setup[2])); ++ DWC_PRINTF(" wIndex = 0x%0x\n", *((uint16_t *) & setup[4])); ++ DWC_PRINTF(" wLength = 0x%0x\n\n", *((uint16_t *) & setup[6])); ++ } ++} ++#endif ++ ++void dwc_otg_hcd_dump_frrem(dwc_otg_hcd_t * hcd) ++{ ++#if 0 ++ DWC_PRINTF("Frame remaining at SOF:\n"); ++ DWC_PRINTF(" samples %u, accum %llu, avg %llu\n", ++ hcd->frrem_samples, hcd->frrem_accum, ++ (hcd->frrem_samples > 0) ? ++ hcd->frrem_accum / hcd->frrem_samples : 0); ++ ++ DWC_PRINTF("\n"); ++ DWC_PRINTF("Frame remaining at start_transfer (uframe 7):\n"); ++ DWC_PRINTF(" samples %u, accum %llu, avg %llu\n", ++ hcd->core_if->hfnum_7_samples, ++ hcd->core_if->hfnum_7_frrem_accum, ++ (hcd->core_if->hfnum_7_samples > ++ 0) ? hcd->core_if->hfnum_7_frrem_accum / ++ hcd->core_if->hfnum_7_samples : 0); ++ DWC_PRINTF("Frame remaining at start_transfer (uframe 0):\n"); ++ DWC_PRINTF(" samples %u, accum %llu, avg %llu\n", ++ hcd->core_if->hfnum_0_samples, ++ hcd->core_if->hfnum_0_frrem_accum, ++ (hcd->core_if->hfnum_0_samples > ++ 0) ? hcd->core_if->hfnum_0_frrem_accum / ++ hcd->core_if->hfnum_0_samples : 0); ++ DWC_PRINTF("Frame remaining at start_transfer (uframe 1-6):\n"); ++ DWC_PRINTF(" samples %u, accum %llu, avg %llu\n", ++ hcd->core_if->hfnum_other_samples, ++ hcd->core_if->hfnum_other_frrem_accum, ++ (hcd->core_if->hfnum_other_samples > ++ 0) ? hcd->core_if->hfnum_other_frrem_accum / ++ hcd->core_if->hfnum_other_samples : 0); ++ ++ DWC_PRINTF("\n"); ++ DWC_PRINTF("Frame remaining at sample point A (uframe 7):\n"); ++ DWC_PRINTF(" samples %u, accum %llu, avg %llu\n", ++ hcd->hfnum_7_samples_a, hcd->hfnum_7_frrem_accum_a, ++ (hcd->hfnum_7_samples_a > 0) ? ++ hcd->hfnum_7_frrem_accum_a / hcd->hfnum_7_samples_a : 0); ++ DWC_PRINTF("Frame remaining at sample point A (uframe 0):\n"); ++ DWC_PRINTF(" samples %u, accum %llu, avg %llu\n", ++ hcd->hfnum_0_samples_a, hcd->hfnum_0_frrem_accum_a, ++ (hcd->hfnum_0_samples_a > 0) ? ++ hcd->hfnum_0_frrem_accum_a / hcd->hfnum_0_samples_a : 0); ++ DWC_PRINTF("Frame remaining at sample point A (uframe 1-6):\n"); ++ DWC_PRINTF(" samples %u, accum %llu, avg %llu\n", ++ hcd->hfnum_other_samples_a, hcd->hfnum_other_frrem_accum_a, ++ (hcd->hfnum_other_samples_a > 0) ? ++ hcd->hfnum_other_frrem_accum_a / ++ hcd->hfnum_other_samples_a : 0); ++ ++ DWC_PRINTF("\n"); ++ DWC_PRINTF("Frame remaining at sample point B (uframe 7):\n"); ++ DWC_PRINTF(" samples %u, accum %llu, avg %llu\n", ++ hcd->hfnum_7_samples_b, hcd->hfnum_7_frrem_accum_b, ++ (hcd->hfnum_7_samples_b > 0) ? ++ hcd->hfnum_7_frrem_accum_b / hcd->hfnum_7_samples_b : 0); ++ DWC_PRINTF("Frame remaining at sample point B (uframe 0):\n"); ++ DWC_PRINTF(" samples %u, accum %llu, avg %llu\n", ++ hcd->hfnum_0_samples_b, hcd->hfnum_0_frrem_accum_b, ++ (hcd->hfnum_0_samples_b > 0) ? ++ hcd->hfnum_0_frrem_accum_b / hcd->hfnum_0_samples_b : 0); ++ DWC_PRINTF("Frame remaining at sample point B (uframe 1-6):\n"); ++ DWC_PRINTF(" samples %u, accum %llu, avg %llu\n", ++ hcd->hfnum_other_samples_b, hcd->hfnum_other_frrem_accum_b, ++ (hcd->hfnum_other_samples_b > 0) ? ++ hcd->hfnum_other_frrem_accum_b / ++ hcd->hfnum_other_samples_b : 0); ++#endif ++} ++ ++#endif /* DWC_DEVICE_ONLY */ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_hcd.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_hcd.h 2013-07-26 19:31:23.000000000 +0000 +@@ -0,0 +1,804 @@ ++/* ========================================================================== ++ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd.h $ ++ * $Revision: #52 $ ++ * $Date: 2009/04/21 $ ++ * $Change: 1237472 $ ++ * ++ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, ++ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless ++ * otherwise expressly agreed to in writing between Synopsys and you. ++ * ++ * The Software IS NOT an item of Licensed Software or Licensed Product under ++ * any End User Software License Agreement or Agreement for Licensed Product ++ * with Synopsys or any supplement thereto. You are permitted to use and ++ * redistribute this Software in source and binary forms, with or without ++ * modification, provided that redistributions of source code must retain this ++ * notice. You may not view, use, disclose, copy or distribute this file or ++ * any information contained herein except pursuant to this license grant from ++ * Synopsys. If you do not agree with this notice, including the disclaimer ++ * below, then you are not authorized to use the Software. ++ * ++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, ++ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR ++ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER ++ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY ++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH ++ * DAMAGE. ++ * ========================================================================== */ ++#ifndef DWC_DEVICE_ONLY ++#ifndef __DWC_HCD_H__ ++#define __DWC_HCD_H__ ++ ++#include ++#include "dwc_otg_hcd_if.h" ++#include "dwc_otg_core_if.h" ++#include "dwc_list.h" ++#include "dwc_otg_cil.h" ++ ++/** ++ * @file ++ * ++ * This file contains the structures, constants, and interfaces for ++ * the Host Contoller Driver (HCD). ++ * ++ * The Host Controller Driver (HCD) is responsible for translating requests ++ * from the USB Driver into the appropriate actions on the DWC_otg controller. ++ * It isolates the USBD from the specifics of the controller by providing an ++ * API to the USBD. ++ */ ++ ++struct dwc_otg_hcd_pipe_info { ++ uint8_t dev_addr; ++ uint8_t ep_num; ++ uint8_t pipe_type; ++ uint8_t pipe_dir; ++ uint16_t mps; ++}; ++ ++struct dwc_otg_hcd_iso_packet_desc { ++ uint32_t offset; ++ uint32_t length; ++ uint32_t actual_length; ++ uint32_t status; ++}; ++ ++struct dwc_otg_qtd; ++ ++struct dwc_otg_hcd_urb { ++ void *priv; ++ struct dwc_otg_qtd *qtd; ++ void *buf; ++ dwc_dma_t dma; ++ void *setup_packet; ++ dwc_dma_t setup_dma; ++ uint32_t length; ++ uint32_t actual_length; ++ uint32_t status; ++ uint32_t error_count; ++ uint32_t packet_count; ++ uint32_t flags; ++ uint16_t interval; ++ struct dwc_otg_hcd_pipe_info pipe_info; ++ struct dwc_otg_hcd_iso_packet_desc iso_descs[0]; ++}; ++ ++static inline uint8_t dwc_otg_hcd_get_ep_num(struct dwc_otg_hcd_pipe_info *pipe) ++{ ++ return pipe->ep_num; ++} ++ ++static inline uint8_t dwc_otg_hcd_get_pipe_type(struct dwc_otg_hcd_pipe_info ++ *pipe) ++{ ++ return pipe->pipe_type; ++} ++ ++static inline uint16_t dwc_otg_hcd_get_mps(struct dwc_otg_hcd_pipe_info *pipe) ++{ ++ return pipe->mps; ++} ++ ++static inline uint8_t dwc_otg_hcd_get_dev_addr(struct dwc_otg_hcd_pipe_info ++ *pipe) ++{ ++ return pipe->dev_addr; ++} ++ ++static inline uint8_t dwc_otg_hcd_is_pipe_isoc(struct dwc_otg_hcd_pipe_info ++ *pipe) ++{ ++ return (pipe->pipe_type == UE_ISOCHRONOUS); ++} ++ ++static inline uint8_t dwc_otg_hcd_is_pipe_int(struct dwc_otg_hcd_pipe_info ++ *pipe) ++{ ++ return (pipe->pipe_type == UE_INTERRUPT); ++} ++ ++static inline uint8_t dwc_otg_hcd_is_pipe_bulk(struct dwc_otg_hcd_pipe_info ++ *pipe) ++{ ++ return (pipe->pipe_type == UE_BULK); ++} ++ ++static inline uint8_t dwc_otg_hcd_is_pipe_control(struct dwc_otg_hcd_pipe_info ++ *pipe) ++{ ++ return (pipe->pipe_type == UE_CONTROL); ++} ++ ++static inline uint8_t dwc_otg_hcd_is_pipe_in(struct dwc_otg_hcd_pipe_info *pipe) ++{ ++ return (pipe->pipe_dir == UE_DIR_IN); ++} ++ ++static inline uint8_t dwc_otg_hcd_is_pipe_out(struct dwc_otg_hcd_pipe_info ++ *pipe) ++{ ++ return (!dwc_otg_hcd_is_pipe_in(pipe)); ++} ++ ++static inline void dwc_otg_hcd_fill_pipe(struct dwc_otg_hcd_pipe_info *pipe, ++ uint8_t devaddr, uint8_t ep_num, ++ uint8_t pipe_type, uint8_t pipe_dir, ++ uint16_t mps) ++{ ++ pipe->dev_addr = devaddr; ++ pipe->ep_num = ep_num; ++ pipe->pipe_type = pipe_type; ++ pipe->pipe_dir = pipe_dir; ++ pipe->mps = mps; ++} ++ ++/** ++ * Phases for control transfers. ++ */ ++typedef enum dwc_otg_control_phase { ++ DWC_OTG_CONTROL_SETUP, ++ DWC_OTG_CONTROL_DATA, ++ DWC_OTG_CONTROL_STATUS ++} dwc_otg_control_phase_e; ++ ++/** Transaction types. */ ++typedef enum dwc_otg_transaction_type { ++ DWC_OTG_TRANSACTION_NONE, ++ DWC_OTG_TRANSACTION_PERIODIC, ++ DWC_OTG_TRANSACTION_NON_PERIODIC, ++ DWC_OTG_TRANSACTION_ALL ++} dwc_otg_transaction_type_e; ++ ++struct dwc_otg_qh; ++ ++/** ++ * A Queue Transfer Descriptor (QTD) holds the state of a bulk, control, ++ * interrupt, or isochronous transfer. A single QTD is created for each URB ++ * (of one of these types) submitted to the HCD. The transfer associated with ++ * a QTD may require one or multiple transactions. ++ * ++ * A QTD is linked to a Queue Head, which is entered in either the ++ * non-periodic or periodic schedule for execution. When a QTD is chosen for ++ * execution, some or all of its transactions may be executed. After ++ * execution, the state of the QTD is updated. The QTD may be retired if all ++ * its transactions are complete or if an error occurred. Otherwise, it ++ * remains in the schedule so more transactions can be executed later. ++ */ ++typedef struct dwc_otg_qtd { ++ /** ++ * Determines the PID of the next data packet for the data phase of ++ * control transfers. Ignored for other transfer types.
++ * One of the following values: ++ * - DWC_OTG_HC_PID_DATA0 ++ * - DWC_OTG_HC_PID_DATA1 ++ */ ++ uint8_t data_toggle; ++ ++ /** Current phase for control transfers (Setup, Data, or Status). */ ++ dwc_otg_control_phase_e control_phase; ++ ++ /** Keep track of the current split type ++ * for FS/LS endpoints on a HS Hub */ ++ uint8_t complete_split; ++ ++ /** How many bytes transferred during SSPLIT OUT */ ++ uint32_t ssplit_out_xfer_count; ++ ++ /** ++ * Holds the number of bus errors that have occurred for a transaction ++ * within this transfer. ++ */ ++ uint8_t error_count; ++ ++ /** ++ * Index of the next frame descriptor for an isochronous transfer. A ++ * frame descriptor describes the buffer position and length of the ++ * data to be transferred in the next scheduled (micro)frame of an ++ * isochronous transfer. It also holds status for that transaction. ++ * The frame index starts at 0. ++ */ ++ uint16_t isoc_frame_index; ++ ++ /** Position of the ISOC split on full/low speed */ ++ uint8_t isoc_split_pos; ++ ++ /** Position of the ISOC split in the buffer for the current frame */ ++ uint16_t isoc_split_offset; ++ ++ /** URB for this transfer */ ++ struct dwc_otg_hcd_urb *urb; ++ ++ struct dwc_otg_qh *qh; ++ ++ /** This list of QTDs */ ++ DWC_CIRCLEQ_ENTRY(dwc_otg_qtd) qtd_list_entry; ++ ++ /** Indicates if this QTD is currently processed by HW. */ ++ uint8_t in_process; ++ ++ /** Number of DMA descriptors for this QTD */ ++ uint8_t n_desc; ++ ++ /** ++ * Last activated frame(packet) index. ++ * Used in Descriptor DMA mode only. ++ */ ++ uint16_t isoc_frame_index_last; ++ ++} dwc_otg_qtd_t; ++ ++DWC_CIRCLEQ_HEAD(dwc_otg_qtd_list, dwc_otg_qtd); ++ ++/** ++ * A Queue Head (QH) holds the static characteristics of an endpoint and ++ * maintains a list of transfers (QTDs) for that endpoint. A QH structure may ++ * be entered in either the non-periodic or periodic schedule. ++ */ ++typedef struct dwc_otg_qh { ++ /** ++ * Endpoint type. ++ * One of the following values: ++ * - UE_CONTROL ++ * - UE_BULK ++ * - UE_INTERRUPT ++ * - UE_ISOCHRONOUS ++ */ ++ uint8_t ep_type; ++ uint8_t ep_is_in; ++ ++ /** wMaxPacketSize Field of Endpoint Descriptor. */ ++ uint16_t maxp; ++ ++ /** ++ * Device speed. ++ * One of the following values: ++ * - DWC_OTG_EP_SPEED_LOW ++ * - DWC_OTG_EP_SPEED_FULL ++ * - DWC_OTG_EP_SPEED_HIGH ++ */ ++ uint8_t dev_speed; ++ ++ /** ++ * Determines the PID of the next data packet for non-control ++ * transfers. Ignored for control transfers.
++ * One of the following values: ++ * - DWC_OTG_HC_PID_DATA0 ++ * - DWC_OTG_HC_PID_DATA1 ++ */ ++ uint8_t data_toggle; ++ ++ /** Ping state if 1. */ ++ uint8_t ping_state; ++ ++ /** ++ * List of QTDs for this QH. ++ */ ++ struct dwc_otg_qtd_list qtd_list; ++ ++ /** Host channel currently processing transfers for this QH. */ ++ struct dwc_hc *channel; ++ ++ /** Full/low speed endpoint on high-speed hub requires split. */ ++ uint8_t do_split; ++ ++ /** @name Periodic schedule information */ ++ /** @{ */ ++ ++ /** Bandwidth in microseconds per (micro)frame. */ ++ uint16_t usecs; ++ ++ /** Interval between transfers in (micro)frames. */ ++ uint16_t interval; ++ ++ /** ++ * (micro)frame to initialize a periodic transfer. The transfer ++ * executes in the following (micro)frame. ++ */ ++ uint16_t sched_frame; ++ ++ /** (micro)frame at which last start split was initialized. */ ++ uint16_t start_split_frame; ++ ++ /** @} */ ++ ++ /** ++ * Used instead of original buffer if ++ * it(physical address) is not dword-aligned. ++ */ ++ uint8_t *dw_align_buf; ++ dwc_dma_t dw_align_buf_dma; ++ ++ /** Entry for QH in either the periodic or non-periodic schedule. */ ++ dwc_list_link_t qh_list_entry; ++ ++ /** @name Descriptor DMA support */ ++ /** @{ */ ++ ++ /** Descriptor List. */ ++ dwc_otg_host_dma_desc_t *desc_list; ++ ++ /** Descriptor List physical address. */ ++ dwc_dma_t desc_list_dma; ++ ++ /** ++ * Xfer Bytes array. ++ * Each element corresponds to a descriptor and indicates ++ * original XferSize size value for the descriptor. ++ */ ++ uint32_t *n_bytes; ++ ++ /** Actual number of transfer descriptors in a list. */ ++ uint16_t ntd; ++ ++ /** First activated isochronous transfer descriptor index. */ ++ uint8_t td_first; ++ /** Last activated isochronous transfer descriptor index. */ ++ uint8_t td_last; ++ ++ /** @} */ ++ ++} dwc_otg_qh_t; ++ ++DWC_CIRCLEQ_HEAD(hc_list, dwc_hc); ++ ++#ifdef HW2937_WORKAROUND ++ ++typedef enum { ++ HW2937_XFER_MODE_IDLE, ++ HW2937_XFER_MODE_IN, ++ HW2937_XFER_MODE_OUT, ++ HW2937_XFER_MODE_PAUSEIN /* Transitioning from IN to IDLE */ ++} hw2937_xfer_mode_t; ++#endif ++ ++/** ++ * This structure holds the state of the HCD, including the non-periodic and ++ * periodic schedules. ++ */ ++struct dwc_otg_hcd { ++ /** DWC OTG Core Interface Layer */ ++ dwc_otg_core_if_t *core_if; ++ ++ /** Function HCD driver callbacks */ ++ struct dwc_otg_hcd_function_ops *fops; ++ ++ /** Internal DWC HCD Flags */ ++ volatile union dwc_otg_hcd_internal_flags { ++ uint32_t d32; ++ struct { ++ unsigned port_connect_status_change:1; ++ unsigned port_connect_status:1; ++ unsigned port_reset_change:1; ++ unsigned port_enable_change:1; ++ unsigned port_suspend_change:1; ++ unsigned port_over_current_change:1; ++ unsigned port_l1_change:1; ++ unsigned reserved:26; ++ } b; ++ } flags; ++ ++ /** ++ * Inactive items in the non-periodic schedule. This is a list of ++ * Queue Heads. Transfers associated with these Queue Heads are not ++ * currently assigned to a host channel. ++ */ ++ dwc_list_link_t non_periodic_sched_inactive; ++ ++ /** ++ * Active items in the non-periodic schedule. This is a list of ++ * Queue Heads. Transfers associated with these Queue Heads are ++ * currently assigned to a host channel. ++ */ ++ dwc_list_link_t non_periodic_sched_active; ++ ++ /** ++ * Pointer to the next Queue Head to process in the active ++ * non-periodic schedule. ++ */ ++ dwc_list_link_t *non_periodic_qh_ptr; ++ ++ /** ++ * Inactive items in the periodic schedule. This is a list of QHs for ++ * periodic transfers that are _not_ scheduled for the next frame. ++ * Each QH in the list has an interval counter that determines when it ++ * needs to be scheduled for execution. This scheduling mechanism ++ * allows only a simple calculation for periodic bandwidth used (i.e. ++ * must assume that all periodic transfers may need to execute in the ++ * same frame). However, it greatly simplifies scheduling and should ++ * be sufficient for the vast majority of OTG hosts, which need to ++ * connect to a small number of peripherals at one time. ++ * ++ * Items move from this list to periodic_sched_ready when the QH ++ * interval counter is 0 at SOF. ++ */ ++ dwc_list_link_t periodic_sched_inactive; ++ ++ /** ++ * List of periodic QHs that are ready for execution in the next ++ * frame, but have not yet been assigned to host channels. ++ * ++ * Items move from this list to periodic_sched_assigned as host ++ * channels become available during the current frame. ++ */ ++ dwc_list_link_t periodic_sched_ready; ++ ++ /** ++ * List of periodic QHs to be executed in the next frame that are ++ * assigned to host channels. ++ * ++ * Items move from this list to periodic_sched_queued as the ++ * transactions for the QH are queued to the DWC_otg controller. ++ */ ++ dwc_list_link_t periodic_sched_assigned; ++ ++ /** ++ * List of periodic QHs that have been queued for execution. ++ * ++ * Items move from this list to either periodic_sched_inactive or ++ * periodic_sched_ready when the channel associated with the transfer ++ * is released. If the interval for the QH is 1, the item moves to ++ * periodic_sched_ready because it must be rescheduled for the next ++ * frame. Otherwise, the item moves to periodic_sched_inactive. ++ */ ++ dwc_list_link_t periodic_sched_queued; ++ ++ /** ++ * Total bandwidth claimed so far for periodic transfers. This value ++ * is in microseconds per (micro)frame. The assumption is that all ++ * periodic transfers may occur in the same (micro)frame. ++ */ ++ uint16_t periodic_usecs; ++ ++ /** ++ * Frame number read from the core at SOF. The value ranges from 0 to ++ * DWC_HFNUM_MAX_FRNUM. ++ */ ++ uint16_t frame_number; ++ ++ /** ++ * Free host channels in the controller. This is a list of ++ * dwc_hc_t items. ++ */ ++ struct hc_list free_hc_list; ++ /** ++ * Number of host channels assigned to periodic transfers. Currently ++ * assuming that there is a dedicated host channel for each periodic ++ * transaction and at least one host channel available for ++ * non-periodic transactions. ++ */ ++ int periodic_channels; ++ ++ /** ++ * Number of host channels assigned to non-periodic transfers. ++ */ ++ int non_periodic_channels; ++ ++ /** ++ * Array of pointers to the host channel descriptors. Allows accessing ++ * a host channel descriptor given the host channel number. This is ++ * useful in interrupt handlers. ++ */ ++ struct dwc_hc *hc_ptr_array[MAX_EPS_CHANNELS]; ++ ++ /** ++ * Buffer to use for any data received during the status phase of a ++ * control transfer. Normally no data is transferred during the status ++ * phase. This buffer is used as a bit bucket. ++ */ ++ uint8_t *status_buf; ++ ++ /** ++ * DMA address for status_buf. ++ */ ++ dma_addr_t status_buf_dma; ++#define DWC_OTG_HCD_STATUS_BUF_SIZE 64 ++ ++ /** ++ * Connection timer. An OTG host must display a message if the device ++ * does not connect. Started when the VBus power is turned on via ++ * sysfs attribute "buspower". ++ */ ++ dwc_timer_t *conn_timer; ++ ++ /* Tasket to do a reset */ ++ dwc_tasklet_t *reset_tasklet; ++ ++ /* */ ++ dwc_spinlock_t *lock; ++ ++ /** ++ * Private data that could be used by OS wrapper. ++ */ ++ void *priv; ++ ++ uint8_t otg_port; ++ ++ /** Frame List */ ++ uint32_t *frame_list; ++ ++ /** Frame List DMA address */ ++ dma_addr_t frame_list_dma; ++ ++#ifdef HW2937_WORKAROUND ++ /** Current transfer mode (IN, OUT, or IDLE) */ ++ hw2937_xfer_mode_t hw2937_xfer_mode; ++ ++ /** Mask of channels assigned to the current mode */ ++ uint32_t hw2937_assigned_channels; ++#endif ++ ++#ifdef DEBUG ++ uint32_t frrem_samples; ++ uint64_t frrem_accum; ++ ++ uint32_t hfnum_7_samples_a; ++ uint64_t hfnum_7_frrem_accum_a; ++ uint32_t hfnum_0_samples_a; ++ uint64_t hfnum_0_frrem_accum_a; ++ uint32_t hfnum_other_samples_a; ++ uint64_t hfnum_other_frrem_accum_a; ++ ++ uint32_t hfnum_7_samples_b; ++ uint64_t hfnum_7_frrem_accum_b; ++ uint32_t hfnum_0_samples_b; ++ uint64_t hfnum_0_frrem_accum_b; ++ uint32_t hfnum_other_samples_b; ++ uint64_t hfnum_other_frrem_accum_b; ++#endif ++}; ++ ++/** @name Transaction Execution Functions */ ++/** @{ */ ++extern dwc_otg_transaction_type_e dwc_otg_hcd_select_transactions(dwc_otg_hcd_t ++ * hcd); ++extern void dwc_otg_hcd_queue_transactions(dwc_otg_hcd_t * hcd, ++ dwc_otg_transaction_type_e tr_type); ++ ++/** @} */ ++ ++/** @name Interrupt Handler Functions */ ++/** @{ */ ++extern int32_t dwc_otg_hcd_handle_intr(dwc_otg_hcd_t * dwc_otg_hcd); ++extern int32_t dwc_otg_hcd_handle_sof_intr(dwc_otg_hcd_t * dwc_otg_hcd); ++extern int32_t dwc_otg_hcd_handle_rx_status_q_level_intr(dwc_otg_hcd_t * ++ dwc_otg_hcd); ++extern int32_t dwc_otg_hcd_handle_np_tx_fifo_empty_intr(dwc_otg_hcd_t * ++ dwc_otg_hcd); ++extern int32_t dwc_otg_hcd_handle_perio_tx_fifo_empty_intr(dwc_otg_hcd_t * ++ dwc_otg_hcd); ++extern int32_t dwc_otg_hcd_handle_incomplete_periodic_intr(dwc_otg_hcd_t * ++ dwc_otg_hcd); ++extern int32_t dwc_otg_hcd_handle_port_intr(dwc_otg_hcd_t * dwc_otg_hcd); ++extern int32_t dwc_otg_hcd_handle_conn_id_status_change_intr(dwc_otg_hcd_t * ++ dwc_otg_hcd); ++extern int32_t dwc_otg_hcd_handle_disconnect_intr(dwc_otg_hcd_t * dwc_otg_hcd); ++extern int32_t dwc_otg_hcd_handle_hc_intr(dwc_otg_hcd_t * dwc_otg_hcd); ++extern int32_t dwc_otg_hcd_handle_hc_n_intr(dwc_otg_hcd_t * dwc_otg_hcd, ++ uint32_t num); ++extern int32_t dwc_otg_hcd_handle_session_req_intr(dwc_otg_hcd_t * dwc_otg_hcd); ++extern int32_t dwc_otg_hcd_handle_wakeup_detected_intr(dwc_otg_hcd_t * ++ dwc_otg_hcd); ++/** @} */ ++ ++/** @name Schedule Queue Functions */ ++/** @{ */ ++ ++/* Implemented in dwc_otg_hcd_queue.c */ ++extern dwc_otg_qh_t *dwc_otg_hcd_qh_create(dwc_otg_hcd_t * hcd, ++ dwc_otg_hcd_urb_t * urb); ++extern void dwc_otg_hcd_qh_free(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh); ++extern int dwc_otg_hcd_qh_add(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh); ++extern void dwc_otg_hcd_qh_remove(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh); ++extern void dwc_otg_hcd_qh_deactivate(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh, ++ int sched_csplit); ++ ++/** Remove and free a QH */ ++static inline void dwc_otg_hcd_qh_remove_and_free(dwc_otg_hcd_t * hcd, ++ dwc_otg_qh_t * qh) ++{ ++ dwc_otg_hcd_qh_remove(hcd, qh); ++ dwc_otg_hcd_qh_free(hcd, qh); ++} ++ ++/** Allocates memory for a QH structure. ++ * @return Returns the memory allocate or NULL on error. */ ++static inline dwc_otg_qh_t *dwc_otg_hcd_qh_alloc(void) ++{ ++ return (dwc_otg_qh_t *) dwc_alloc(sizeof(dwc_otg_qh_t)); ++} ++ ++extern dwc_otg_qtd_t *dwc_otg_hcd_qtd_create(dwc_otg_hcd_urb_t * urb); ++extern void dwc_otg_hcd_qtd_init(dwc_otg_qtd_t * qtd, dwc_otg_hcd_urb_t * urb); ++extern int dwc_otg_hcd_qtd_add(dwc_otg_qtd_t * qtd, dwc_otg_hcd_t * dwc_otg_hcd, ++ dwc_otg_qh_t ** qh); ++ ++/** Allocates memory for a QTD structure. ++ * @return Returns the memory allocate or NULL on error. */ ++static inline dwc_otg_qtd_t *dwc_otg_hcd_qtd_alloc(void) ++{ ++ return (dwc_otg_qtd_t *) dwc_alloc(sizeof(dwc_otg_qtd_t)); ++} ++ ++/** Frees the memory for a QTD structure. QTD should already be removed from ++ * list. ++ * @param qtd QTD to free.*/ ++static inline void dwc_otg_hcd_qtd_free(dwc_otg_qtd_t * qtd) ++{ ++ dwc_free(qtd); ++} ++ ++/** Removes a QTD from list. ++ * @param hcd HCD instance. ++ * @param qtd QTD to remove from list. ++ * @param qh QTD belongs to. ++ */ ++static inline void dwc_otg_hcd_qtd_remove(dwc_otg_hcd_t * hcd, ++ dwc_otg_qtd_t * qtd, ++ dwc_otg_qh_t * qh) ++{ ++ uint64_t flags; ++ DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags); ++ DWC_CIRCLEQ_REMOVE(&qh->qtd_list, qtd, qtd_list_entry); ++ DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags); ++} ++ ++/** Remove and free a QTD */ ++static inline void dwc_otg_hcd_qtd_remove_and_free(dwc_otg_hcd_t * hcd, ++ dwc_otg_qtd_t * qtd, ++ dwc_otg_qh_t * qh) ++{ ++ dwc_otg_hcd_qtd_remove(hcd, qtd, qh); ++ dwc_otg_hcd_qtd_free(qtd); ++} ++ ++/** @} */ ++ ++/** @name Descriptor DMA Supporting Functions */ ++/** @{ */ ++ ++extern void dwc_otg_hcd_start_xfer_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh); ++extern void dwc_otg_hcd_complete_xfer_ddma(dwc_otg_hcd_t * hcd, ++ dwc_hc_t * hc, ++ dwc_otg_hc_regs_t * hc_regs, ++ dwc_otg_halt_status_e halt_status); ++ ++extern int dwc_otg_hcd_qh_init_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh); ++extern void dwc_otg_hcd_qh_free_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh); ++ ++/** @} */ ++ ++/** @name Internal Functions */ ++/** @{ */ ++dwc_otg_qh_t *dwc_urb_to_qh(dwc_otg_hcd_urb_t * urb); ++/** @} */ ++ ++#ifdef CONFIG_USB_DWC_OTG_LPM ++extern int dwc_otg_hcd_get_hc_for_lpm_tran(dwc_otg_hcd_t * hcd, ++ uint8_t devaddr); ++extern void dwc_otg_hcd_free_hc_from_lpm(dwc_otg_hcd_t * hcd); ++#endif ++ ++/** Gets the QH that contains the list_head */ ++#define dwc_list_to_qh(_list_head_ptr_) container_of(_list_head_ptr_, dwc_otg_qh_t, qh_list_entry) ++ ++/** Gets the QTD that contains the list_head */ ++#define dwc_list_to_qtd(_list_head_ptr_) container_of(_list_head_ptr_, dwc_otg_qtd_t, qtd_list_entry) ++ ++/** Check if QH is non-periodic */ ++#define dwc_qh_is_non_per(_qh_ptr_) ((_qh_ptr_->ep_type == UE_BULK) || \ ++ (_qh_ptr_->ep_type == UE_CONTROL)) ++ ++/** High bandwidth multiplier as encoded in highspeed endpoint descriptors */ ++#define dwc_hb_mult(wMaxPacketSize) (1 + (((wMaxPacketSize) >> 11) & 0x03)) ++ ++/** Packet size for any kind of endpoint descriptor */ ++#define dwc_max_packet(wMaxPacketSize) ((wMaxPacketSize) & 0x07ff) ++ ++/** ++ * Returns true if _frame1 is less than or equal to _frame2. The comparison is ++ * done modulo DWC_HFNUM_MAX_FRNUM. This accounts for the rollover of the ++ * frame number when the max frame number is reached. ++ */ ++static inline int dwc_frame_num_le(uint16_t frame1, uint16_t frame2) ++{ ++ return ((frame2 - frame1) & DWC_HFNUM_MAX_FRNUM) <= ++ (DWC_HFNUM_MAX_FRNUM >> 1); ++} ++ ++/** ++ * Returns true if _frame1 is greater than _frame2. The comparison is done ++ * modulo DWC_HFNUM_MAX_FRNUM. This accounts for the rollover of the frame ++ * number when the max frame number is reached. ++ */ ++static inline int dwc_frame_num_gt(uint16_t frame1, uint16_t frame2) ++{ ++ return (frame1 != frame2) && ++ (((frame1 - frame2) & DWC_HFNUM_MAX_FRNUM) < ++ (DWC_HFNUM_MAX_FRNUM >> 1)); ++} ++ ++/** ++ * Increments _frame by the amount specified by _inc. The addition is done ++ * modulo DWC_HFNUM_MAX_FRNUM. Returns the incremented value. ++ */ ++static inline uint16_t dwc_frame_num_inc(uint16_t frame, uint16_t inc) ++{ ++ return (frame + inc) & DWC_HFNUM_MAX_FRNUM; ++} ++ ++static inline uint16_t dwc_full_frame_num(uint16_t frame) ++{ ++ return (frame & DWC_HFNUM_MAX_FRNUM) >> 3; ++} ++ ++static inline uint16_t dwc_micro_frame_num(uint16_t frame) ++{ ++ return frame & 0x7; ++} ++ ++void dwc_otg_hcd_save_data_toggle(dwc_hc_t * hc, ++ dwc_otg_hc_regs_t * hc_regs, ++ dwc_otg_qtd_t * qtd); ++ ++#ifdef DEBUG ++/** ++ * Macro to sample the remaining PHY clocks left in the current frame. This ++ * may be used during debugging to determine the average time it takes to ++ * execute sections of code. There are two possible sample points, "a" and ++ * "b", so the _letter argument must be one of these values. ++ * ++ * To dump the average sample times, read the "hcd_frrem" sysfs attribute. For ++ * example, "cat /sys/devices/lm0/hcd_frrem". ++ */ ++#define dwc_sample_frrem(_hcd, _qh, _letter) \ ++{ \ ++ hfnum_data_t hfnum; \ ++ dwc_otg_qtd_t *qtd; \ ++ qtd = list_entry(_qh->qtd_list.next, dwc_otg_qtd_t, qtd_list_entry); \ ++ if (usb_pipeint(qtd->urb->pipe) && _qh->start_split_frame != 0 && !qtd->complete_split) { \ ++ hfnum.d32 = dwc_read_reg32(&_hcd->core_if->host_if->host_global_regs->hfnum); \ ++ switch (hfnum.b.frnum & 0x7) { \ ++ case 7: \ ++ _hcd->hfnum_7_samples_##_letter++; \ ++ _hcd->hfnum_7_frrem_accum_##_letter += hfnum.b.frrem; \ ++ break; \ ++ case 0: \ ++ _hcd->hfnum_0_samples_##_letter++; \ ++ _hcd->hfnum_0_frrem_accum_##_letter += hfnum.b.frrem; \ ++ break; \ ++ default: \ ++ _hcd->hfnum_other_samples_##_letter++; \ ++ _hcd->hfnum_other_frrem_accum_##_letter += hfnum.b.frrem; \ ++ break; \ ++ } \ ++ } \ ++} ++#else ++#define dwc_sample_frrem(_hcd, _qh, _letter) ++#endif ++#endif ++#endif /* DWC_DEVICE_ONLY */ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_hcd_ddma.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_hcd_ddma.c 2013-07-26 19:31:23.000000000 +0000 +@@ -0,0 +1,1106 @@ ++/*========================================================================== ++ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd_ddma.c $ ++ * $Revision: #2 $ ++ * $Date: 2009/04/21 $ ++ * $Change: 1237473 $ ++ * ++ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, ++ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless ++ * otherwise expressly agreed to in writing between Synopsys and you. ++ * ++ * The Software IS NOT an item of Licensed Software or Licensed Product under ++ * any End User Software License Agreement or Agreement for Licensed Product ++ * with Synopsys or any supplement thereto. You are permitted to use and ++ * redistribute this Software in source and binary forms, with or without ++ * modification, provided that redistributions of source code must retain this ++ * notice. You may not view, use, disclose, copy or distribute this file or ++ * any information contained herein except pursuant to this license grant from ++ * Synopsys. If you do not agree with this notice, including the disclaimer ++ * below, then you are not authorized to use the Software. ++ * ++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, ++ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR ++ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER ++ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY ++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH ++ * DAMAGE. ++ * ========================================================================== */ ++#ifndef DWC_DEVICE_ONLY ++ ++/** @file ++ * This file contains Descriptor DMA support implementation for host mode. ++ */ ++ ++#include "dwc_otg_hcd.h" ++#include "dwc_otg_regs.h" ++ ++ ++static inline uint8_t frame_list_idx(uint16_t frame) ++{ ++ return (frame & (MAX_FRLIST_EN_NUM - 1)); ++} ++ ++static inline uint16_t desclist_idx_inc(uint16_t idx, uint16_t inc, uint8_t speed) ++{ ++ return (idx + inc) & ++ (((speed == DWC_OTG_EP_SPEED_HIGH) ? MAX_DMA_DESC_NUM_HS_ISOC : MAX_DMA_DESC_NUM_GENERIC) - 1); ++} ++ ++static inline uint16_t desclist_idx_dec(uint16_t idx, uint16_t inc, uint8_t speed) ++{ ++ return (idx - inc) & ++ (((speed == DWC_OTG_EP_SPEED_HIGH) ? MAX_DMA_DESC_NUM_HS_ISOC : MAX_DMA_DESC_NUM_GENERIC) - 1); ++} ++ ++static inline uint16_t max_desc_num(dwc_otg_qh_t * qh) ++{ ++ return (((qh->ep_type == UE_ISOCHRONOUS) && (qh->dev_speed == DWC_OTG_EP_SPEED_HIGH)) ++ ? ++ MAX_DMA_DESC_NUM_HS_ISOC ++ : ++ MAX_DMA_DESC_NUM_GENERIC); ++} ++static inline uint16_t frame_incr_val(dwc_otg_qh_t * qh) ++{ ++ return ((qh->dev_speed == DWC_OTG_EP_SPEED_HIGH) ++ ? ((qh->interval + 8 - 1) / 8) ++ : ++ qh->interval); ++} ++ ++static int desc_list_alloc(dwc_otg_qh_t * qh) ++{ ++ int retval = 0; ++ ++ qh->desc_list = (dwc_otg_host_dma_desc_t *) ++ dwc_dma_alloc(sizeof(dwc_otg_host_dma_desc_t) * max_desc_num(qh), ++ &qh->desc_list_dma ++ ); ++ ++ if (!qh->desc_list) { ++ retval = -DWC_E_NO_MEMORY; ++ DWC_ERROR("%s: DMA descriptor list allocation failed\n", __func__); ++ ++ } ++ ++ dwc_memset(qh->desc_list, 0x00, sizeof(dwc_otg_host_dma_desc_t) * max_desc_num(qh)); ++ ++ ++ qh->n_bytes = (uint32_t *) dwc_alloc(sizeof(uint32_t) * max_desc_num(qh)); ++ ++ if (!qh->n_bytes) { ++ retval = -DWC_E_NO_MEMORY; ++ DWC_ERROR("%s: Failed to allocate array for descriptors' size actual values\n", ++ __func__); ++ ++ } ++ return retval; ++ ++} ++ ++static void desc_list_free(dwc_otg_qh_t * qh) ++{ ++ if(qh->desc_list) { ++ dwc_dma_free(max_desc_num(qh), qh->desc_list, qh->desc_list_dma); ++ qh->desc_list = NULL; ++ } ++ ++ if (qh->n_bytes) { ++ dwc_free(qh->n_bytes); ++ qh->n_bytes = NULL; ++ } ++} ++ ++static int frame_list_alloc(dwc_otg_hcd_t * hcd) ++{ ++ int retval = 0; ++ if (hcd->frame_list) ++ return 0; ++ ++ hcd->frame_list = dwc_dma_alloc(4 * MAX_FRLIST_EN_NUM, ++ &hcd->frame_list_dma ++ ); ++ if (!hcd->frame_list) { ++ retval = -DWC_E_NO_MEMORY; ++ DWC_ERROR("%s: Frame List allocation failed\n", __func__); ++ } ++ ++ dwc_memset(hcd->frame_list, 0x00, 4 * MAX_FRLIST_EN_NUM); ++ ++ return retval; ++} ++ ++static void frame_list_free(dwc_otg_hcd_t * hcd) ++{ ++ if (!hcd->frame_list) ++ return; ++ ++ dwc_dma_free(4 * MAX_FRLIST_EN_NUM, hcd->frame_list, hcd->frame_list_dma); ++ hcd->frame_list = NULL; ++} ++ ++static void per_sched_enable(dwc_otg_hcd_t * hcd, uint16_t fr_list_en) ++{ ++ ++ hcfg_data_t hcfg; ++ ++ hcfg.d32 = dwc_read_reg32(&hcd->core_if->host_if->host_global_regs->hcfg); ++ ++ if (hcfg.b.perschedstat) { ++ /* already enabled*/ ++ return; ++ } ++ ++ dwc_write_reg32(&hcd->core_if->host_if->host_global_regs->hflbaddr, hcd->frame_list_dma); ++ ++ switch(fr_list_en) { ++ case 64: ++ hcfg.b.frlisten = 3; ++ break; ++ case 32: ++ hcfg.b.frlisten = 2; ++ break; ++ case 16: ++ hcfg.b.frlisten = 1; ++ case 8: ++ hcfg.b.frlisten = 0; ++ default: ++ break; ++ } ++ ++ hcfg.b.perschedena = 1; ++ ++ DWC_DEBUGPL(DBG_HCD, "Enabling Periodic schedule\n"); ++ dwc_write_reg32(&hcd->core_if->host_if->host_global_regs->hcfg, hcfg.d32); ++ ++} ++ ++static void per_sched_disable(dwc_otg_hcd_t * hcd) ++{ ++ hcfg_data_t hcfg; ++ ++ hcfg.d32 = dwc_read_reg32(&hcd->core_if->host_if->host_global_regs->hcfg); ++ ++ if (!hcfg.b.perschedstat) { ++ /* already disabled */ ++ return; ++ } ++ hcfg.b.perschedena = 0; ++ ++ DWC_DEBUGPL(DBG_HCD, "Disabling Periodic schedule\n"); ++ dwc_write_reg32(&hcd->core_if->host_if->host_global_regs->hcfg, hcfg.d32); ++} ++ ++/* ++ * Activates/Deactivates FrameList entries for the channel ++ * based on endpoint servicing period. ++ */ ++void update_frame_list(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh, uint8_t enable) ++{ ++ uint16_t i, j, inc; ++ dwc_hc_t *hc = qh->channel; ++ ++ inc = frame_incr_val(qh); ++ ++ if (qh->ep_type == UE_ISOCHRONOUS) ++ i = frame_list_idx(qh->sched_frame); ++ else ++ i = 0; ++ ++ j = i; ++ do { ++ if (enable) ++ hcd->frame_list[j] |= (1 << hc->hc_num); ++ else ++ hcd->frame_list[j] &= ~(1 << hc->hc_num); ++ j = (j + inc) & (MAX_FRLIST_EN_NUM - 1); ++ } ++ while (j != i); ++ ++ if (!enable) ++ return; ++ ++ hc->schinfo = 0; ++ if (qh->channel->speed == DWC_OTG_EP_SPEED_HIGH) { ++ j = 1; ++ for (i = 0 ; i < 8 / qh->interval; i++) { ++ hc->schinfo |= j; ++ j = j << qh->interval; ++ } ++ } ++ else { ++ hc->schinfo = 0xff; ++ } ++} ++#if 1 ++void dump_frame_list(dwc_otg_hcd_t * hcd) ++{ ++ int i = 0; ++ DWC_PRINTF("--FRAME LIST (hex) --\n"); ++ for (i = 0; i < MAX_FRLIST_EN_NUM; i++) { ++ DWC_PRINTF("%x\t",hcd->frame_list[i]); ++ if (!(i % 8) && i) ++ DWC_PRINTF("\n"); ++ } ++ DWC_PRINTF("\n----\n"); ++ ++} ++#endif ++ ++static void release_channel_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh) ++{ ++ dwc_hc_t *hc = qh->channel; ++ if (dwc_qh_is_non_per(qh)) { ++ hcd->non_periodic_channels--; ++ } ++ else { ++ update_frame_list(hcd, qh, 0); ++ } ++ /* ++ * The condition is added to prevent double cleanup try in case of device ++ * disconnect. See channel cleanup in dwc_otg_hcd_disconnect_cb(). ++ */ ++ if (hc->qh) { ++ dwc_otg_hc_cleanup(hcd->core_if, hc); ++ DWC_CIRCLEQ_INSERT_TAIL(&hcd->free_hc_list, hc, hc_list_entry); ++ hc->qh = NULL; ++ } ++ ++ qh->channel = NULL; ++ qh->ntd = 0; ++ ++ if (qh->desc_list) { ++ dwc_memset(qh->desc_list, 0x00, ++ sizeof(dwc_otg_host_dma_desc_t) * max_desc_num(qh)); ++ } ++} ++ ++/** ++ * Initializes a QH structure's Descriptor DMA related members. ++ * Allocates memory for descriptor list. ++ * On first periodic QH, allocates memory for FrameList ++ * and enables periodic scheduling. ++ * ++ * @param hcd The HCD state structure for the DWC OTG controller. ++ * @param qh The QH to init. ++ * ++ * @return 0 if successful, negative error code otherwise. ++ */ ++int dwc_otg_hcd_qh_init_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh) ++{ ++ int retval = 0; ++ ++ if (qh->do_split) { ++ DWC_ERROR("SPLIT Transfers are not supported in Descriptor DMA.\n"); ++ return -1; ++ } ++ ++ retval = desc_list_alloc(qh); ++ ++ if ((retval == 0) && (qh->ep_type == UE_ISOCHRONOUS || qh->ep_type == UE_INTERRUPT)) { ++ if(!hcd->frame_list) { ++ retval = frame_list_alloc(hcd); ++ /* Enable periodic schedule on first periodic QH */ ++ if (retval == 0) ++ per_sched_enable(hcd, MAX_FRLIST_EN_NUM); ++ } ++ } ++ ++ qh->ntd = 0; ++ ++ return retval; ++} ++ ++/** ++ * Frees descriptor list memory associated with the QH. ++ * If QH is periodic and the last, frees FrameList memory ++ * and disables periodic scheduling. ++ * ++ * @param hcd The HCD state structure for the DWC OTG controller. ++ * @param qh The QH to init. ++ */ ++void dwc_otg_hcd_qh_free_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh) ++{ ++ desc_list_free(qh); ++ ++ /* ++ * Channel still assigned due to some reasons. ++ * Seen on Isoc URB dequeue. Channel halted but no subsequent ++ * ChHalted interrupt to release the channel. Afterwards ++ * when it comes here from endpoint disable routine ++ * channel remains assigned. ++ */ ++ if (qh->channel) ++ release_channel_ddma(hcd, qh); ++ ++ if ((qh->ep_type == UE_ISOCHRONOUS || qh->ep_type == UE_INTERRUPT) ++ && !hcd->periodic_channels && hcd->frame_list) { ++ ++ per_sched_disable(hcd); ++ frame_list_free(hcd); ++ } ++} ++ ++static uint8_t frame_to_desc_idx(dwc_otg_qh_t * qh, uint16_t frame_idx) ++{ ++ if (qh->dev_speed == DWC_OTG_EP_SPEED_HIGH) { ++ /* ++ * Descriptor set(8 descriptors) index ++ * which is 8-aligned. ++ */ ++ return (frame_idx & ((MAX_DMA_DESC_NUM_HS_ISOC / 8) - 1)) * 8; ++ } ++ else { ++ return (frame_idx & (MAX_DMA_DESC_NUM_GENERIC - 1)); ++ } ++} ++ ++/* ++ * Determine starting frame for Isochronous transfer. ++ * Few frames skipped to prevent race condition with HC. ++ */ ++static uint8_t calc_starting_frame(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh, uint8_t* skip_frames) ++{ ++ uint16_t frame = 0; ++ hcd->frame_number = dwc_otg_hcd_get_frame_number(hcd); ++ ++ /* sched_frame is always frame number(not uFrame) both in FS and HS !! */ ++ ++ /* ++ * skip_frames is used to limit activated descriptors number ++ * to avoid the situation when HC services the last activated ++ * descriptor firstly. ++ * Example for FS: ++ * Current frame is 1, scheduled frame is 3. Since HC always fetches the descriptor ++ * corresponding to curr_frame+1, the descriptor corresponding to frame 2 ++ * will be fetched. If the number of descriptors is max=64 (or greather) the list will ++ * be fully programmed with Active descriptors and it is possible case(rare) that the latest ++ * descriptor(considering rollback) corresponding to frame 2 will be serviced first. ++ * HS case is more probable because, in fact, up to 11 uframes(16 in the code) ++ * may be skipped. ++ */ ++ if (qh->dev_speed == DWC_OTG_EP_SPEED_HIGH) { ++ /* ++ * Consider uframe counter also, to start xfer asap. ++ * If half of the frame elapsed skip 2 frames otherwise ++ * just 1 frame. ++ * Starting descriptor index must be 8-aligned, so ++ * if the current frame is near to complete the next one ++ * is skipped as well. ++ */ ++ ++ if (dwc_micro_frame_num(hcd->frame_number) >= 5) { ++ *skip_frames = 2 * 8; ++ frame = dwc_frame_num_inc(hcd->frame_number, *skip_frames); ++ } ++ else { ++ *skip_frames = 1 * 8; ++ frame = dwc_frame_num_inc(hcd->frame_number, *skip_frames); ++ } ++ ++ frame = dwc_full_frame_num(frame); ++ } else { ++ /* ++ * Two frames are skipped for FS - the current and the next. ++ * But for descriptor programming, 1 frame(descriptor) is enough, ++ * see example above. ++ */ ++ *skip_frames = 1; ++ frame = dwc_frame_num_inc(hcd->frame_number, 2); ++ } ++ ++ return frame; ++} ++/* ++ * Calculate initial descriptor index for isochronous transfer ++ * based on scheduled frame. ++ */ ++static uint8_t recalc_initial_desc_idx(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh) ++{ ++ uint16_t frame = 0, fr_idx, fr_idx_tmp; ++ uint8_t skip_frames = 0 ; ++ /* ++ * With current ISOC processing algorithm the channel is being ++ * released when no more QTDs in the list(qh->ntd == 0). ++ * Thus this function is called only when qh->ntd == 0 and qh->channel == 0. ++ * ++ * So qh->channel != NULL branch is not used and just not removed from the ++ * source file. It is required for another possible approach which is, ++ * do not disable and release the channel when ISOC session completed, ++ * just move QH to inactive schedule until new QTD arrives. ++ * On new QTD, the QH moved back to 'ready' schedule, ++ * starting frame and therefore starting desc_index are recalculated. ++ * In this case channel is released only on ep_disable. ++ */ ++ ++ /* Calculate starting descriptor index. For INTERRUPT endpoint it is always 0. */ ++ if (qh->channel) { ++ frame = calc_starting_frame(hcd, qh, &skip_frames); ++ /* ++ * Calculate initial descriptor index based on FrameList current bitmap ++ * and servicing period. ++ */ ++ fr_idx_tmp = frame_list_idx(frame); ++ fr_idx = (MAX_FRLIST_EN_NUM + frame_list_idx(qh->sched_frame) - fr_idx_tmp) ++ % frame_incr_val(qh); ++ fr_idx = (fr_idx + fr_idx_tmp) % MAX_FRLIST_EN_NUM; ++ } ++ else { ++ qh->sched_frame = calc_starting_frame(hcd, qh, &skip_frames); ++ fr_idx = frame_list_idx(qh->sched_frame); ++ } ++ ++ qh->td_first = qh->td_last = frame_to_desc_idx(qh, fr_idx); ++ ++ return skip_frames; ++} ++ ++#define ISOC_URB_GIVEBACK_ASAP ++ ++#define MAX_ISOC_XFER_SIZE_FS 1023 ++#define MAX_ISOC_XFER_SIZE_HS 3072 ++#define DESCNUM_THRESHOLD 4 ++ ++static void init_isoc_dma_desc(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh, uint8_t skip_frames) ++{ ++ struct dwc_otg_hcd_iso_packet_desc *frame_desc; ++ dwc_otg_qtd_t *qtd; ++ dwc_otg_host_dma_desc_t *dma_desc; ++ uint16_t idx, inc, n_desc, ntd_max, max_xfer_size; ++ ++ idx = qh->td_last; ++ inc = qh->interval; ++ n_desc = 0; ++ ++ ntd_max = (max_desc_num(qh) + qh->interval - 1) / qh->interval; ++ if (skip_frames && !qh->channel) ++ ntd_max = ntd_max - skip_frames / qh->interval; ++ ++ max_xfer_size = (qh->dev_speed == DWC_OTG_EP_SPEED_HIGH) ? MAX_ISOC_XFER_SIZE_HS ++ : MAX_ISOC_XFER_SIZE_FS; ++ ++ DWC_CIRCLEQ_FOREACH(qtd, &qh->qtd_list, qtd_list_entry) { ++ while ((qh->ntd < ntd_max) && (qtd->isoc_frame_index_last < qtd->urb->packet_count)) { ++ ++ dma_desc = &qh->desc_list[idx]; ++ dwc_memset(dma_desc, 0x00, sizeof(dwc_otg_host_dma_desc_t)); ++ ++ frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index_last]; ++ ++ if (frame_desc->length > max_xfer_size) ++ qh->n_bytes[idx] = max_xfer_size; ++ else ++ qh->n_bytes[idx] = frame_desc->length; ++ dma_desc->status.b_isoc.n_bytes = qh->n_bytes[idx]; ++ dma_desc->status.b_isoc.a = 1; ++ ++ dma_desc->buf = qtd->urb->dma + frame_desc->offset; ++ ++ qh->ntd++; ++ ++ qtd->isoc_frame_index_last++; ++ ++ #ifdef ISOC_URB_GIVEBACK_ASAP ++ /* ++ * Set IOC for each descriptor corresponding to the ++ * last frame of the URB. ++ */ ++ if (qtd->isoc_frame_index_last == qtd->urb->packet_count) ++ dma_desc->status.b_isoc.ioc = 1; ++ ++ #endif ++ idx = desclist_idx_inc(idx, inc, qh->dev_speed); ++ n_desc++; ++ ++ } ++ qtd->in_process = 1; ++ } ++ ++ qh->td_last = idx; ++ ++#ifdef ISOC_URB_GIVEBACK_ASAP ++ /* Set IOC for the last descriptor if descriptor list is full */ ++ if (qh->ntd == ntd_max) { ++ idx = desclist_idx_dec(qh->td_last, inc, qh->dev_speed); ++ qh->desc_list[idx].status.b_isoc.ioc = 1; ++ } ++#else ++ /* ++ * Set IOC bit only for one descriptor. ++ * Always try to be ahead of HW processing, ++ * i.e. on IOC generation driver activates next descriptors but ++ * core continues to process descriptors followed the one with IOC set. ++ */ ++ ++ if (n_desc > DESCNUM_THRESHOLD) { ++ /* ++ * Move IOC "up". Required even if there is only one QTD ++ * in the list, cause QTDs migth continue to be queued, ++ * but during the activation it was only one queued. ++ * Actually more than one QTD might be in the list if this function called ++ * from XferCompletion - QTDs was queued during HW processing of the previous ++ * descriptor chunk. ++ */ ++ idx = dwc_desclist_idx_dec(idx, inc * ((qh->ntd + 1) / 2), qh->dev_speed); ++ } ++ else { ++ /* ++ * Set the IOC for the latest descriptor ++ * if either number of descriptor is not greather than threshold ++ * or no more new descriptors activated. ++ */ ++ idx = dwc_desclist_idx_dec(qh->td_last, inc, qh->dev_speed); ++ } ++ ++ qh->desc_list[idx].status.b_isoc.ioc = 1; ++#endif ++} ++ ++ ++static void init_non_isoc_dma_desc(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh) ++{ ++ ++ dwc_hc_t *hc; ++ dwc_otg_host_dma_desc_t *dma_desc; ++ dwc_otg_qtd_t *qtd; ++ int num_packets, len, n_desc = 0; ++ ++ hc = qh->channel; ++ ++ /* ++ * Start with hc->xfer_buff initialized in ++ * assign_and_init_hc(), then if SG transfer consists of multiple URBs, ++ * this pointer re-assigned to the buffer of the currently processed QTD. ++ * For non-SG request there is always one QTD active. ++ */ ++ ++ DWC_CIRCLEQ_FOREACH(qtd, &qh->qtd_list, qtd_list_entry) { ++ ++ if (n_desc) { ++ /* SG request - more than 1 QTDs */ ++ hc->xfer_buff = (uint8_t *)qtd->urb->dma + qtd->urb->actual_length; ++ hc->xfer_len = qtd->urb->length - qtd->urb->actual_length; ++ } ++ ++ qtd->n_desc = 0; ++ ++ do { ++ dma_desc = &qh->desc_list[n_desc]; ++ len = hc->xfer_len; ++ ++ ++ if (len > MAX_DMA_DESC_SIZE) ++ len = MAX_DMA_DESC_SIZE - hc->max_packet + 1; ++ ++ if (hc->ep_is_in) { ++ if (len > 0) { ++ num_packets = (len + hc->max_packet - 1) / hc->max_packet; ++ } ++ else { ++ /* Need 1 packet for transfer length of 0. */ ++ num_packets = 1; ++ } ++ /* Always program an integral # of max packets for IN transfers. */ ++ len = num_packets * hc->max_packet; ++ } ++ ++ dma_desc->status.b.n_bytes = len; ++ ++ qh->n_bytes[n_desc] = len; ++ ++ ++ if ((qh->ep_type == UE_CONTROL) && (qtd->control_phase == DWC_OTG_CONTROL_SETUP)) ++ dma_desc->status.b.sup = 1; /* Setup Packet */ ++ ++ dma_desc->status.b.a = 1; /* Active descriptor */ ++ ++ dma_desc->buf = (uint32_t) hc->xfer_buff; ++ ++ /* ++ * Last descriptor(or single) of IN transfer ++ * with actual size less than MaxPacket. ++ */ ++ if (len > hc->xfer_len) { ++ hc->xfer_len = 0; ++ } ++ else { ++ hc->xfer_buff += len; ++ hc->xfer_len -= len; ++ } ++ ++ qtd->n_desc++; ++ n_desc++; ++ } ++ while ((hc->xfer_len > 0) && (n_desc != MAX_DMA_DESC_NUM_GENERIC)); ++ ++ ++ qtd->in_process = 1; ++ ++ if (n_desc == MAX_DMA_DESC_NUM_GENERIC) ++ break; ++ } ++ ++ if (n_desc) { ++ /* Request Transfer Complete interrupt for the last descriptor */ ++ qh->desc_list[n_desc-1].status.b.ioc = 1; ++ /* End of List indicator */ ++ qh->desc_list[n_desc-1].status.b.eol = 1; ++ ++ hc->ntd = n_desc; ++ } ++} ++ ++/** ++ * For Control and Bulk endpoints initializes descriptor list ++ * and starts the transfer. ++ * ++ * For Interrupt and Isochronous endpoints initializes descriptor list ++ * then updates FrameList, marking appropriate entries as active. ++ * In case of Isochronous, the starting descriptor index is calculated based ++ * on the scheduled frame, but only on the first transfer descriptor within a session. ++ * Then starts the transfer via enabling the channel. ++ * For Isochronous endpoint the channel is not halted on XferComplete ++ * interrupt so remains assigned to the endpoint(QH) until session is done. ++ * ++ * @param hcd The HCD state structure for the DWC OTG controller. ++ * @param qh The QH to init. ++ * ++ * @return 0 if successful, negative error code otherwise. ++ */ ++void dwc_otg_hcd_start_xfer_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh) ++{ ++ /* Channel is already assigned */ ++ dwc_hc_t *hc = qh->channel; ++ uint8_t skip_frames = 0; ++ ++ switch (hc->ep_type) { ++ case DWC_OTG_EP_TYPE_CONTROL: ++ case DWC_OTG_EP_TYPE_BULK: ++ init_non_isoc_dma_desc(hcd, qh); ++ ++ dwc_otg_hc_start_transfer_ddma(hcd->core_if, hc); ++ break; ++ case DWC_OTG_EP_TYPE_INTR: ++ init_non_isoc_dma_desc(hcd, qh); ++ ++ update_frame_list(hcd, qh, 1); ++ ++ dwc_otg_hc_start_transfer_ddma(hcd->core_if, hc); ++ break; ++ case DWC_OTG_EP_TYPE_ISOC: ++ ++ if(!qh->ntd) ++ skip_frames = recalc_initial_desc_idx(hcd, qh); ++ ++ init_isoc_dma_desc(hcd, qh, skip_frames); ++ ++ if (!hc->xfer_started) { ++ ++ update_frame_list(hcd, qh, 1); ++ ++ /* ++ * Always set to max, instead of actual size. ++ * Otherwise ntd will be changed with ++ * channel being enabled. Not recommended. ++ * ++ */ ++ hc->ntd = max_desc_num(qh); ++ /* Enable channel only once for ISOC */ ++ dwc_otg_hc_start_transfer_ddma(hcd->core_if, hc); ++ } ++ ++ break; ++ default: ++ ++ break; ++ } ++} ++ ++static void complete_isoc_xfer_ddma(dwc_otg_hcd_t *hcd, ++ dwc_hc_t *hc, ++ dwc_otg_hc_regs_t *hc_regs, ++ dwc_otg_halt_status_e halt_status) ++{ ++ struct dwc_otg_hcd_iso_packet_desc *frame_desc; ++ dwc_otg_qtd_t *qtd, *qtd_tmp; ++ dwc_otg_qh_t *qh; ++ dwc_otg_host_dma_desc_t *dma_desc; ++ uint16_t idx, remain; ++ uint8_t urb_compl; ++ ++ qh = hc->qh; ++ idx = qh->td_first; ++ ++ ++ if (hc->halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE) { ++ DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp, &hc->qh->qtd_list, qtd_list_entry) ++ qtd->in_process = 0; ++ return; ++ } ++ else if ((halt_status == DWC_OTG_HC_XFER_AHB_ERR) || ++ (halt_status == DWC_OTG_HC_XFER_BABBLE_ERR)) { ++ /* ++ * Channel is halted in these error cases. ++ * Considered as serious issues. ++ * Complete all URBs marking all frames as failed, ++ * irrespective whether some of the descriptors(frames) succeeded or no. ++ * Pass error code to completion routine as well, to ++ * update urb->status, some of class drivers might use it to stop ++ * queing transfer requests. ++ */ ++ int err = (halt_status == DWC_OTG_HC_XFER_AHB_ERR) ++ ? (-DWC_E_IO) ++ : (-DWC_E_OVERFLOW); ++ ++ DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp, &hc->qh->qtd_list, qtd_list_entry) { ++ for(idx = 0; idx < qtd->urb->packet_count; idx++) { ++ frame_desc = &qtd->urb->iso_descs[idx]; ++ frame_desc->status = err; ++ } ++ hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, err); ++ dwc_otg_hcd_qtd_remove_and_free(hcd, qtd, qh); ++ } ++ return; ++ } ++ ++ ++ DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp, &hc->qh->qtd_list, qtd_list_entry) { ++ ++ if (!qtd->in_process) ++ break; ++ ++ urb_compl = 0; ++ ++ do { ++ ++ dma_desc = &qh->desc_list[idx]; ++ ++ frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index]; ++ remain = hc->ep_is_in ? dma_desc->status.b_isoc.n_bytes : 0; ++ ++ if (dma_desc->status.b_isoc.sts == DMA_DESC_STS_PKTERR) { ++ /* ++ * XactError or, unable to complete all the transactions ++ * in the scheduled micro-frame/frame, ++ * both indicated by DMA_DESC_STS_PKTERR. ++ */ ++ qtd->urb->error_count++; ++ frame_desc->actual_length = qh->n_bytes[idx] - remain; ++ frame_desc->status = -DWC_E_PROTOCOL; ++ } ++ else { ++ /* Success */ ++ ++ frame_desc->actual_length = qh->n_bytes[idx] - remain; ++ frame_desc->status = 0; ++ } ++ ++ if (++qtd->isoc_frame_index == qtd->urb->packet_count) { ++ /* ++ * urb->status is not used for isoc transfers here. ++ * The individual frame_desc status are used instead. ++ */ ++ ++ hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, 0); ++ dwc_otg_hcd_qtd_remove_and_free(hcd, qtd, qh); ++ ++ /* ++ * This check is necessary because urb_dequeue can be called ++ * from urb complete callback(sound driver example). ++ * All pending URBs are dequeued there, so no need for ++ * further processing. ++ */ ++ if (hc->halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE) { ++ return; ++ } ++ ++ urb_compl = 1; ++ ++ } ++ ++ qh->ntd--; ++ ++ /* Stop if IOC requested descriptor reached */ ++ if (dma_desc->status.b_isoc.ioc) { ++ idx = desclist_idx_inc(idx, qh->interval, hc->speed); ++ goto stop_scan; ++ } ++ ++ idx = desclist_idx_inc(idx, qh->interval, hc->speed); ++ ++ if (urb_compl) ++ break; ++ } ++ while(idx != qh->td_first); ++ } ++stop_scan: ++ qh->td_first = idx; ++} ++ ++uint8_t update_non_isoc_urb_state_ddma(dwc_otg_hcd_t * hcd, ++ dwc_hc_t * hc, ++ dwc_otg_qtd_t * qtd, ++ dwc_otg_host_dma_desc_t * dma_desc, ++ dwc_otg_halt_status_e halt_status, ++ uint32_t n_bytes, ++ uint8_t *xfer_done) ++{ ++ ++ uint16_t remain = hc->ep_is_in ? dma_desc->status.b.n_bytes : 0; ++ dwc_otg_hcd_urb_t *urb = qtd->urb; ++ ++ ++ if (halt_status == DWC_OTG_HC_XFER_AHB_ERR) { ++ urb->status = -DWC_E_IO; ++ return 1; ++ } ++ if (dma_desc->status.b.sts == DMA_DESC_STS_PKTERR) { ++ switch (halt_status) { ++ case DWC_OTG_HC_XFER_STALL: ++ urb->status = -DWC_E_PIPE; ++ break; ++ case DWC_OTG_HC_XFER_BABBLE_ERR: ++ urb->status = -DWC_E_OVERFLOW; ++ break; ++ case DWC_OTG_HC_XFER_XACT_ERR: ++ urb->status = -DWC_E_PROTOCOL; ++ break; ++ default: ++ DWC_ERROR("%s: Unhandled descriptor error status (%d)\n", __func__, ++ halt_status); ++ break; ++ } ++ return 1; ++ } ++ ++ if (dma_desc->status.b.a == 1) { ++ DWC_DEBUGPL(DBG_HCDV, "Active descriptor encountered on channel %d\n", hc->hc_num); ++ return 0; ++ } ++ ++ if (hc->ep_type == DWC_OTG_EP_TYPE_CONTROL) { ++ if (qtd->control_phase == DWC_OTG_CONTROL_DATA) { ++ urb->actual_length += n_bytes - remain; ++ if (remain || urb->actual_length == urb->length) { ++ /* ++ * For Control Data stage do not set urb->status=0 to prevent ++ * URB callback. Set it when Status phase done. See below. ++ */ ++ *xfer_done = 1; ++ } ++ ++ } ++ else if (qtd->control_phase == DWC_OTG_CONTROL_STATUS) { ++ urb->status = 0; ++ *xfer_done = 1; ++ } ++ /* No handling for SETUP stage */ ++ ++ } ++ else { ++ /* BULK and INTR */ ++ urb->actual_length += n_bytes - remain; ++ if (remain || urb->actual_length == urb->length) { ++ urb->status = 0; ++ *xfer_done = 1; ++ } ++ } ++ ++ return 0; ++} ++ ++static void complete_non_isoc_xfer_ddma(dwc_otg_hcd_t * hcd, ++ dwc_hc_t * hc, ++ dwc_otg_hc_regs_t * hc_regs, ++ dwc_otg_halt_status_e halt_status) ++{ ++ dwc_otg_hcd_urb_t *urb = NULL; ++ dwc_otg_qtd_t *qtd, *qtd_tmp; ++ dwc_otg_qh_t *qh; ++ dwc_otg_host_dma_desc_t *dma_desc; ++ uint32_t n_bytes, n_desc, i; ++ uint8_t failed = 0, xfer_done; ++ ++ n_desc = 0; ++ ++ qh = hc->qh; ++ ++ ++ if (hc->halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE) { ++ DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp, &hc->qh->qtd_list, qtd_list_entry) { ++ qtd->in_process = 0; ++ } ++ return; ++ } ++ ++ DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp, &qh->qtd_list, qtd_list_entry) { ++ ++ urb = qtd->urb; ++ ++ n_bytes = 0; ++ xfer_done = 0; ++ ++ for (i = 0; i < qtd->n_desc; i++) { ++ dma_desc = &qh->desc_list[n_desc]; ++ ++ n_bytes = qh->n_bytes[n_desc]; ++ ++ ++ failed = update_non_isoc_urb_state_ddma(hcd, hc, qtd, dma_desc, ++ halt_status, n_bytes, &xfer_done); ++ ++ if (failed || (xfer_done && (urb->status != -DWC_E_IN_PROGRESS))) { ++ ++ hcd->fops->complete(hcd, urb->priv, urb, urb->status); ++ dwc_otg_hcd_qtd_remove_and_free(hcd, qtd, qh); ++ ++ if (failed) ++ goto stop_scan; ++ } ++ else if (qh->ep_type == UE_CONTROL) { ++ if (qtd->control_phase == DWC_OTG_CONTROL_SETUP) { ++ if (urb->length > 0) { ++ qtd->control_phase = DWC_OTG_CONTROL_DATA; ++ } else { ++ qtd->control_phase = DWC_OTG_CONTROL_STATUS; ++ } ++ DWC_DEBUGPL(DBG_HCDV, " Control setup transaction done\n"); ++ } ++ else if(qtd->control_phase == DWC_OTG_CONTROL_DATA) { ++ if (xfer_done) { ++ qtd->control_phase = DWC_OTG_CONTROL_STATUS; ++ DWC_DEBUGPL(DBG_HCDV, " Control data transfer done\n"); ++ } else if (i+1 == qtd->n_desc){ ++ /* ++ * Last descriptor for Control data stage which is ++ * not completed yet. ++ */ ++ dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd); ++ } ++ } ++ } ++ ++ n_desc++; ++ } ++ ++ } ++ ++stop_scan: ++ ++ if (qh->ep_type != UE_CONTROL) { ++ /* ++ * Resetting the data toggle for bulk ++ * and interrupt endpoints in case of stall. See handle_hc_stall_intr() ++ */ ++ if (halt_status == DWC_OTG_HC_XFER_STALL) { ++ qh->data_toggle = DWC_OTG_HC_PID_DATA0; ++ } ++ else { ++ dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd); ++ } ++ } ++ ++ if (halt_status == DWC_OTG_HC_XFER_COMPLETE) { ++ hcint_data_t hcint; ++ hcint.d32 = dwc_read_reg32(&hc_regs->hcint); ++ if (hcint.b.nyet) { ++ /* ++ * Got a NYET on the last transaction of the transfer. It ++ * means that the endpoint should be in the PING state at the ++ * beginning of the next transfer. ++ */ ++ qh->ping_state = 1; ++ clear_hc_int(hc_regs, nyet); ++ } ++ ++ } ++ ++} ++ ++/** ++ * This function is called from interrupt handlers. ++ * Scans the descriptor list, updates URB's status and ++ * calls completion routine for the URB if it's done. ++ * Releases the channel to be used by other transfers. ++ * In case of Isochronous endpoint the channel is not halted until ++ * the end of the session, i.e. QTD list is empty. ++ * If periodic channel released the FrameList is updated accordingly. ++ * ++ * Calls transaction selection routines to activate pending transfers. ++ * ++ * @param hcd The HCD state structure for the DWC OTG controller. ++ * @param hc Host channel, the transfer is completed on. ++ * @param hc_regs Host channel registers. ++ * @param halt_status Reason the channel is being halted, ++ * or just XferComplete for isochronous transfer ++ */ ++void dwc_otg_hcd_complete_xfer_ddma(dwc_otg_hcd_t *hcd, ++ dwc_hc_t *hc, ++ dwc_otg_hc_regs_t *hc_regs, ++ dwc_otg_halt_status_e halt_status) ++{ ++ uint8_t continue_isoc_xfer = 0; ++ dwc_otg_transaction_type_e tr_type; ++ dwc_otg_qh_t *qh = hc->qh; ++ ++ if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC) { ++ ++ complete_isoc_xfer_ddma(hcd, hc, hc_regs, halt_status); ++ ++ /* Release the channel if halted or session completed */ ++ if (halt_status != DWC_OTG_HC_XFER_COMPLETE || ++ DWC_CIRCLEQ_EMPTY(&qh->qtd_list)) { ++ ++ /* Halt the channel if session completed */ ++ if (halt_status == DWC_OTG_HC_XFER_COMPLETE) { ++ dwc_otg_hc_halt(hcd->core_if, hc, halt_status); ++ } ++ ++ release_channel_ddma(hcd, qh); ++ dwc_otg_hcd_qh_remove(hcd, qh); ++ } ++ else { ++ /* Keep in assigned schedule to continue transfer */ ++ DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_assigned, ++ &qh->qh_list_entry); ++ continue_isoc_xfer = 1; ++ ++ } ++ /** @todo Consider the case when period exceeds FrameList size. ++ * Frame Rollover interrupt should be used. ++ */ ++ } ++ else { ++ /* Scan descriptor list to complete the URB(s), then release the channel */ ++ complete_non_isoc_xfer_ddma(hcd, hc, hc_regs, halt_status); ++ ++ release_channel_ddma(hcd, qh); ++ ++ dwc_otg_hcd_qh_remove(hcd, qh); ++ ++ if (!DWC_CIRCLEQ_EMPTY(&qh->qtd_list)) { ++ /* Add back to inactive non-periodic schedule on normal completion */ ++ dwc_otg_hcd_qh_add(hcd, qh); ++ } ++ ++ ++ } ++ tr_type = dwc_otg_hcd_select_transactions(hcd); ++ if (tr_type != DWC_OTG_TRANSACTION_NONE || continue_isoc_xfer) { ++ if (continue_isoc_xfer) { ++ if (tr_type == DWC_OTG_TRANSACTION_NONE) { ++ tr_type = DWC_OTG_TRANSACTION_PERIODIC; ++ } else if (tr_type == DWC_OTG_TRANSACTION_NON_PERIODIC) { ++ tr_type = DWC_OTG_TRANSACTION_ALL; ++ } ++ } ++ dwc_otg_hcd_queue_transactions(hcd, tr_type); ++ } ++} ++ ++#endif /* DWC_DEVICE_ONLY */ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_hcd_if.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_hcd_if.h 2013-07-26 19:31:23.000000000 +0000 +@@ -0,0 +1,393 @@ ++/* ========================================================================== ++ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd_if.h $ ++ * $Revision: #6 $ ++ * $Date: 2009/04/21 $ ++ * $Change: 1237474 $ ++ * ++ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, ++ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless ++ * otherwise expressly agreed to in writing between Synopsys and you. ++ * ++ * The Software IS NOT an item of Licensed Software or Licensed Product under ++ * any End User Software License Agreement or Agreement for Licensed Product ++ * with Synopsys or any supplement thereto. You are permitted to use and ++ * redistribute this Software in source and binary forms, with or without ++ * modification, provided that redistributions of source code must retain this ++ * notice. You may not view, use, disclose, copy or distribute this file or ++ * any information contained herein except pursuant to this license grant from ++ * Synopsys. If you do not agree with this notice, including the disclaimer ++ * below, then you are not authorized to use the Software. ++ * ++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, ++ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR ++ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER ++ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY ++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH ++ * DAMAGE. ++ * ========================================================================== */ ++#ifndef DWC_DEVICE_ONLY ++#ifndef __DWC_HCD_IF_H__ ++#define __DWC_HCD_IF_H__ ++ ++#include "dwc_otg_core_if.h" ++ ++/** @file ++ * This file defines DWC_OTG HCD Core API. ++ */ ++ ++struct dwc_otg_hcd; ++typedef struct dwc_otg_hcd dwc_otg_hcd_t; ++ ++struct dwc_otg_hcd_urb; ++typedef struct dwc_otg_hcd_urb dwc_otg_hcd_urb_t; ++ ++/** @name HCD Function Driver Callbacks */ ++/** @{ */ ++ ++/** This function is called whenever core switches to host mode. */ ++typedef int (*dwc_otg_hcd_start_cb_t) (dwc_otg_hcd_t * hcd); ++ ++/** This function is called when device has been disconnected */ ++typedef int (*dwc_otg_hcd_disconnect_cb_t) (dwc_otg_hcd_t * hcd); ++ ++/** Wrapper provides this function to HCD to core, so it can get hub information to which device is connected */ ++typedef int (*dwc_otg_hcd_hub_info_from_urb_cb_t) (dwc_otg_hcd_t * hcd, ++ void *urb_handle, ++ uint32_t * hub_addr, ++ uint32_t * port_addr); ++/** Via this function HCD core gets device speed */ ++typedef int (*dwc_otg_hcd_speed_from_urb_cb_t) (dwc_otg_hcd_t * hcd, ++ void *urb_handle); ++ ++/** This function is called when urb is completed */ ++typedef int (*dwc_otg_hcd_complete_urb_cb_t) (dwc_otg_hcd_t * hcd, ++ void *urb_handle, ++ dwc_otg_hcd_urb_t * dwc_otg_urb, ++ int32_t status); ++ ++/** Via this function HCD core gets b_hnp_enable parameter */ ++typedef int (*dwc_otg_hcd_get_b_hnp_enable) (dwc_otg_hcd_t * hcd); ++ ++struct dwc_otg_hcd_function_ops { ++ dwc_otg_hcd_start_cb_t start; ++ dwc_otg_hcd_disconnect_cb_t disconnect; ++ dwc_otg_hcd_hub_info_from_urb_cb_t hub_info; ++ dwc_otg_hcd_speed_from_urb_cb_t speed; ++ dwc_otg_hcd_complete_urb_cb_t complete; ++ dwc_otg_hcd_get_b_hnp_enable get_b_hnp_enable; ++}; ++/** @} */ ++ ++/** @name HCD Core API */ ++/** @{ */ ++/** This function allocates dwc_otg_hcd structure and returns pointer on it. */ ++extern dwc_otg_hcd_t *dwc_otg_hcd_alloc_hcd(void); ++ ++/** This function should be called to initiate HCD Core. ++ * ++ * @param hcd The HCD ++ * @param core_if The DWC_OTG Core ++ * ++ * Returns -DWC_E_NO_MEMORY if no enough memory. ++ * Returns 0 on success ++ */ ++extern int dwc_otg_hcd_init(dwc_otg_hcd_t * hcd, dwc_otg_core_if_t * core_if); ++ ++/** Frees HCD ++ * ++ * @param hcd The HCD ++ */ ++extern void dwc_otg_hcd_remove(dwc_otg_hcd_t * hcd); ++ ++/** This function should be called on every hardware interrupt. ++ * ++ * @param dwc_otg_hcd The HCD ++ * ++ * Returns non zero if interrupt is handled ++ * Return 0 if interrupt is not handled ++ */ ++extern int32_t dwc_otg_hcd_handle_intr(dwc_otg_hcd_t * dwc_otg_hcd); ++ ++/** ++ * Returns private data set by ++ * dwc_otg_hcd_set_priv_data function. ++ * ++ * @param hcd The HCD ++ */ ++extern void *dwc_otg_hcd_get_priv_data(dwc_otg_hcd_t * hcd); ++ ++/** ++ * Set private data. ++ * ++ * @param hcd The HCD ++ * @param priv_data pointer to be stored in private data ++ */ ++extern void dwc_otg_hcd_set_priv_data(dwc_otg_hcd_t * hcd, void *priv_data); ++ ++/** ++ * This function initializes the HCD Core. ++ * ++ * @param hcd The HCD ++ * @param fops The Function Driver Operations data structure containing pointers to all callbacks. ++ * ++ * Returns -DWC_E_NO_DEVICE if Core is currently is in device mode. ++ * Returns 0 on success ++ */ ++extern int dwc_otg_hcd_start(dwc_otg_hcd_t * hcd, ++ struct dwc_otg_hcd_function_ops *fops); ++ ++/** ++ * Halts the DWC_otg host mode operations in a clean manner. USB transfers are ++ * stopped. ++ * ++ * @param hcd The HCD ++ */ ++extern void dwc_otg_hcd_stop(dwc_otg_hcd_t * hcd); ++ ++/** ++ * Handles hub class-specific requests. ++ * ++ * @param dwc_otg_hcd The HCD ++ * @param typeReq Request Type ++ * @param wValue wValue from control request ++ * @param wIndex wIndex from control request ++ * @param buf data buffer ++ * @param wLength data buffer length ++ * ++ * Returns -DWC_E_INVALID if invalid argument is passed ++ * Returns 0 on success ++ */ ++extern int dwc_otg_hcd_hub_control(dwc_otg_hcd_t * dwc_otg_hcd, ++ uint16_t typeReq, uint16_t wValue, ++ uint16_t wIndex, uint8_t * buf, ++ uint16_t wLength); ++ ++/** ++ * Returns otg port number. ++ * ++ * @param hcd The HCD ++ */ ++extern uint32_t dwc_otg_hcd_otg_port(dwc_otg_hcd_t * hcd); ++ ++/** ++ * Returns 1 if currently core is acting as B host, and 0 otherwise. ++ * ++ * @param hcd The HCD ++ */ ++extern uint32_t dwc_otg_hcd_is_b_host(dwc_otg_hcd_t * hcd); ++ ++/** ++ * Returns current frame number. ++ * ++ * @param hcd The HCD ++ */ ++extern int dwc_otg_hcd_get_frame_number(dwc_otg_hcd_t * hcd); ++ ++/** ++ * Dumps hcd state. ++ * ++ * @param hcd The HCD ++ */ ++extern void dwc_otg_hcd_dump_state(dwc_otg_hcd_t * hcd); ++ ++/** ++ * Dump the average frame remaining at SOF. This can be used to ++ * determine average interrupt latency. Frame remaining is also shown for ++ * start transfer and two additional sample points. ++ * Currently this function is not implemented. ++ * ++ * @param hcd The HCD ++ */ ++extern void dwc_otg_hcd_dump_frrem(dwc_otg_hcd_t * hcd); ++ ++/** ++ * Sends LPM transaction to the local device. ++ * ++ * @param hcd The HCD ++ * @param devaddr Device Address ++ * @param hird Host initiated resume duration ++ * @param bRemoteWake Value of bRemoteWake field in LPM transaction ++ * ++ * Returns negative value if sending LPM transaction was not succeeded. ++ * Returns 0 on success. ++ */ ++extern int dwc_otg_hcd_send_lpm(dwc_otg_hcd_t * hcd, uint8_t devaddr, ++ uint8_t hird, uint8_t bRemoteWake); ++ ++/* URB interface */ ++ ++/** ++ * Allocates memory for dwc_otg_hcd_urb structure. ++ * Allocated memory should be freed by call dwc_free function. ++ * ++ * @param hcd The HCD ++ * @param iso_desc_count Count of ISOC descriptors ++ * @param atomic_alloc Specefies whether to perform atomic allocation. ++ */ ++extern dwc_otg_hcd_urb_t *dwc_otg_hcd_urb_alloc(dwc_otg_hcd_t * hcd, ++ int iso_desc_count, ++ int atomic_alloc); ++ ++/** ++ * Set pipe information in URB. ++ * ++ * @param hcd_urb DWC_OTG URB ++ * @param devaddr Device Address ++ * @param ep_num Endpoint Number ++ * @param ep_type Endpoint Type ++ * @param ep_dir Endpoint Direction ++ * @param mps Max Packet Size ++ */ ++extern void dwc_otg_hcd_urb_set_pipeinfo(dwc_otg_hcd_urb_t * hcd_urb, ++ uint8_t devaddr, uint8_t ep_num, ++ uint8_t ep_type, uint8_t ep_dir, ++ uint16_t mps); ++ ++/* Transfer flags */ ++#define URB_GIVEBACK_ASAP 0x1 ++#define URB_SEND_ZERO_PACKET 0x2 ++ ++/** ++ * Sets dwc_otg_hcd_urb parameters. ++ * ++ * @param urb DWC_OTG URB allocated by dwc_otg_hcd_urb_alloc function. ++ * @param urb_handle Unique handle for request, this will be passed back ++ * to function driver in completion callback. ++ * @param buf The buffer for the data ++ * @param dma The DMA buffer for the data ++ * @param buflen Transfer length ++ * @param sp Buffer for setup data ++ * @param sp_dma DMA address of setup data buffer ++ * @param flags Transfer flags ++ * @param interval Polling interval for interrupt or isochronous transfers. ++ */ ++extern void dwc_otg_hcd_urb_set_params(dwc_otg_hcd_urb_t * urb, ++ void *urb_handle, void *buf, ++ dwc_dma_t dma, uint32_t buflen, void *sp, ++ dwc_dma_t sp_dma, uint32_t flags, ++ uint16_t interval); ++ ++/** Gets status from dwc_otg_hcd_urb ++ * ++ * @param dwc_otg_urb DWC_OTG URB ++ */ ++extern uint32_t dwc_otg_hcd_urb_get_status(dwc_otg_hcd_urb_t * dwc_otg_urb); ++ ++/** Gets actual length from dwc_otg_hcd_urb ++ * ++ * @param dwc_otg_urb DWC_OTG URB ++ */ ++extern uint32_t dwc_otg_hcd_urb_get_actual_length(dwc_otg_hcd_urb_t * ++ dwc_otg_urb); ++ ++/** Gets error count from dwc_otg_hcd_urb. Only for ISOC URBs ++ * ++ * @param dwc_otg_urb DWC_OTG URB ++ */ ++extern uint32_t dwc_otg_hcd_urb_get_error_count(dwc_otg_hcd_urb_t * ++ dwc_otg_urb); ++ ++/** Set ISOC descriptor offset and length ++ * ++ * @param dwc_otg_urb DWC_OTG URB ++ * @param desc_num ISOC descriptor number ++ * @param offset Offset from beginig of buffer. ++ * @param length Transaction length ++ */ ++extern void dwc_otg_hcd_urb_set_iso_desc_params(dwc_otg_hcd_urb_t * dwc_otg_urb, ++ int desc_num, uint32_t offset, ++ uint32_t length); ++ ++/** Get status of ISOC descriptor, specified by desc_num ++ * ++ * @param dwc_otg_urb DWC_OTG URB ++ * @param desc_num ISOC descriptor number ++ */ ++extern uint32_t dwc_otg_hcd_urb_get_iso_desc_status(dwc_otg_hcd_urb_t * ++ dwc_otg_urb, int desc_num); ++ ++/** Get actual length of ISOC descriptor, specified by desc_num ++ * ++ * @param dwc_otg_urb DWC_OTG URB ++ * @param desc_num ISOC descriptor number ++ */ ++extern uint32_t dwc_otg_hcd_urb_get_iso_desc_actual_length(dwc_otg_hcd_urb_t * ++ dwc_otg_urb, ++ int desc_num); ++ ++/** Queue URB. After transfer is completes, the complete callback will be called with the URB status ++ * ++ * @param dwc_otg_hcd The HCD ++ * @param dwc_otg_urb DWC_OTG URB ++ * @param ep_handle Out parameter for returning endpoint handle ++ * ++ * Returns -DWC_E_NO_DEVICE if no device is connected. ++ * Returns -DWC_E_NO_MEMORY if there is no enough memory. ++ * Returns 0 on success. ++ */ ++extern int dwc_otg_hcd_urb_enqueue(dwc_otg_hcd_t * dwc_otg_hcd, ++ dwc_otg_hcd_urb_t * dwc_otg_urb, ++ void **ep_handle); ++ ++/** De-queue the specified URB ++ * ++ * @param dwc_otg_hcd The HCD ++ * @param dwc_otg_urb DWC_OTG URB ++ */ ++extern int dwc_otg_hcd_urb_dequeue(dwc_otg_hcd_t * dwc_otg_hcd, ++ dwc_otg_hcd_urb_t * dwc_otg_urb); ++ ++/** Frees resources in the DWC_otg controller related to a given endpoint. ++ * Any URBs for the endpoint must already be dequeued. ++ * ++ * @param hcd The HCD ++ * @param ep_handle Endpoint handle, returned by dwc_otg_hcd_urb_enqueue function ++ * @param retry Number of retries if there are queued transfers. ++ * ++ * Returns -DWC_E_INVALID if invalid arguments are passed. ++ * Returns 0 on success ++ */ ++extern int dwc_otg_hcd_endpoint_disable(dwc_otg_hcd_t * hcd, void *ep_handle, ++ int retry); ++ ++/** Returns 1 if status of specified port is changed and 0 otherwise. ++ * ++ * @param hcd The HCD ++ * @param port Port number ++ */ ++extern int dwc_otg_hcd_is_status_changed(dwc_otg_hcd_t * hcd, int port); ++ ++/** Call this function to check if bandwidth was allocated for specified endpoint. ++ * Only for ISOC and INTERRUPT endpoints. ++ * ++ * @param hcd The HCD ++ * @param ep_handle Endpoint handle ++ */ ++extern int dwc_otg_hcd_is_bandwidth_allocated(dwc_otg_hcd_t * hcd, ++ void *ep_handle); ++ ++/** Call this function to check if bandwidth was freed for specified endpoint. ++ * ++ * @param hcd The HCD ++ * @param ep_handle Endpoint handle ++ */ ++extern int dwc_otg_hcd_is_bandwidth_freed(dwc_otg_hcd_t * hcd, void *ep_handle); ++ ++/** Returns bandwidth allocated for specified endpoint in microseconds. ++ * Only for ISOC and INTERRUPT endpoints. ++ * ++ * @param hcd The HCD ++ * @param ep_handle Endpoint handle ++ */ ++extern uint8_t dwc_otg_hcd_get_ep_bandwidth(dwc_otg_hcd_t * hcd, ++ void *ep_handle); ++ ++/** @} */ ++ ++#endif /* __DWC_HCD_IF_H__ */ ++#endif /* DWC_DEVICE_ONLY */ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c 2013-07-26 19:31:23.000000000 +0000 +@@ -0,0 +1,2065 @@ ++/* ========================================================================== ++ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd_intr.c $ ++ * $Revision: #77 $ ++ * $Date: 2009/04/21 $ ++ * $Change: 1237475 $ ++ * ++ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, ++ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless ++ * otherwise expressly agreed to in writing between Synopsys and you. ++ * ++ * The Software IS NOT an item of Licensed Software or Licensed Product under ++ * any End User Software License Agreement or Agreement for Licensed Product ++ * with Synopsys or any supplement thereto. You are permitted to use and ++ * redistribute this Software in source and binary forms, with or without ++ * modification, provided that redistributions of source code must retain this ++ * notice. You may not view, use, disclose, copy or distribute this file or ++ * any information contained herein except pursuant to this license grant from ++ * Synopsys. If you do not agree with this notice, including the disclaimer ++ * below, then you are not authorized to use the Software. ++ * ++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, ++ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR ++ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER ++ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY ++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH ++ * DAMAGE. ++ * ========================================================================== */ ++#ifndef DWC_DEVICE_ONLY ++ ++#include "dwc_otg_hcd.h" ++#include "dwc_otg_regs.h" ++ ++/** @file ++ * This file contains the implementation of the HCD Interrupt handlers. ++ */ ++ ++/** This function handles interrupts for the HCD. */ ++int32_t dwc_otg_hcd_handle_intr(dwc_otg_hcd_t * dwc_otg_hcd) ++{ ++ int retval = 0; ++ ++ dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if; ++ gintsts_data_t gintsts; ++#ifdef DEBUG ++ dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs; ++ ++ //GRAYG: debugging ++ if (NULL == global_regs) { ++ DWC_DEBUGPL(DBG_HCD, "**** NULL regs: dwc_otg_hcd=%p " ++ "core_if=%p\n", ++ dwc_otg_hcd, global_regs); ++ return retval; ++ } ++#endif ++ ++ /* Check if HOST Mode */ ++ if (dwc_otg_is_host_mode(core_if)) { ++ gintsts.d32 = dwc_otg_read_core_intr(core_if); ++ if (!gintsts.d32) { ++ return 0; ++ } ++#ifdef DEBUG ++ /* Don't print debug message in the interrupt handler on SOF */ ++#ifndef DEBUG_SOF ++ if (gintsts.d32 != DWC_SOF_INTR_MASK) ++#endif ++ DWC_DEBUGPL(DBG_HCD, "\n"); ++#endif ++ ++#ifdef DEBUG ++#ifndef DEBUG_SOF ++ if (gintsts.d32 != DWC_SOF_INTR_MASK) ++#endif ++ DWC_DEBUGPL(DBG_HCD, ++ "DWC OTG HCD Interrupt Detected gintsts&gintmsk=0x%08x core_if=%p\n", ++ gintsts.d32, core_if); ++#endif ++ ++ if (gintsts.b.sofintr) { ++ retval |= dwc_otg_hcd_handle_sof_intr(dwc_otg_hcd); ++ } ++ if (gintsts.b.rxstsqlvl) { ++ retval |= ++ dwc_otg_hcd_handle_rx_status_q_level_intr ++ (dwc_otg_hcd); ++ } ++ if (gintsts.b.nptxfempty) { ++ retval |= ++ dwc_otg_hcd_handle_np_tx_fifo_empty_intr ++ (dwc_otg_hcd); ++ } ++ if (gintsts.b.i2cintr) { ++ /** @todo Implement i2cintr handler. */ ++ } ++ if (gintsts.b.portintr) { ++ retval |= dwc_otg_hcd_handle_port_intr(dwc_otg_hcd); ++ } ++ if (gintsts.b.hcintr) { ++ retval |= dwc_otg_hcd_handle_hc_intr(dwc_otg_hcd); ++ } ++ if (gintsts.b.ptxfempty) { ++ retval |= ++ dwc_otg_hcd_handle_perio_tx_fifo_empty_intr ++ (dwc_otg_hcd); ++ } ++#ifdef DEBUG ++#ifndef DEBUG_SOF ++ if (gintsts.d32 != DWC_SOF_INTR_MASK) ++#endif ++ { ++ DWC_DEBUGPL(DBG_HCD, ++ "DWC OTG HCD Finished Servicing Interrupts\n"); ++ DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD gintsts=0x%08x\n", ++ dwc_read_reg32(&global_regs->gintsts)); ++ DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD gintmsk=0x%08x\n", ++ dwc_read_reg32(&global_regs->gintmsk)); ++ } ++#endif ++ ++#ifdef DEBUG ++#ifndef DEBUG_SOF ++ if (gintsts.d32 != DWC_SOF_INTR_MASK) ++#endif ++ DWC_DEBUGPL(DBG_HCD, "\n"); ++#endif ++ ++ } ++ ++ return retval; ++} ++ ++#ifdef DWC_TRACK_MISSED_SOFS ++#warning Compiling code to track missed SOFs ++#define FRAME_NUM_ARRAY_SIZE 1000 ++/** ++ * This function is for debug only. ++ */ ++static inline void track_missed_sofs(uint16_t curr_frame_number) ++{ ++ static uint16_t frame_num_array[FRAME_NUM_ARRAY_SIZE]; ++ static uint16_t last_frame_num_array[FRAME_NUM_ARRAY_SIZE]; ++ static int frame_num_idx = 0; ++ static uint16_t last_frame_num = DWC_HFNUM_MAX_FRNUM; ++ static int dumped_frame_num_array = 0; ++ ++ if (frame_num_idx < FRAME_NUM_ARRAY_SIZE) { ++ if (((last_frame_num + 1) & DWC_HFNUM_MAX_FRNUM) != ++ curr_frame_number) { ++ frame_num_array[frame_num_idx] = curr_frame_number; ++ last_frame_num_array[frame_num_idx++] = last_frame_num; ++ } ++ } else if (!dumped_frame_num_array) { ++ int i; ++ DWC_PRINTF("Frame Last Frame\n"); ++ DWC_PRINTF("----- ----------\n"); ++ for (i = 0; i < FRAME_NUM_ARRAY_SIZE; i++) { ++ DWC_PRINTF("0x%04x 0x%04x\n", ++ frame_num_array[i], last_frame_num_array[i]); ++ } ++ dumped_frame_num_array = 1; ++ } ++ last_frame_num = curr_frame_number; ++} ++#endif ++ ++/** ++ * Handles the start-of-frame interrupt in host mode. Non-periodic ++ * transactions may be queued to the DWC_otg controller for the current ++ * (micro)frame. Periodic transactions may be queued to the controller for the ++ * next (micro)frame. ++ */ ++int32_t dwc_otg_hcd_handle_sof_intr(dwc_otg_hcd_t * hcd) ++{ ++ hfnum_data_t hfnum; ++ dwc_list_link_t *qh_entry; ++ dwc_otg_qh_t *qh; ++ dwc_otg_transaction_type_e tr_type; ++ gintsts_data_t gintsts = {.d32 = 0 }; ++ ++ hfnum.d32 = ++ dwc_read_reg32(&hcd->core_if->host_if->host_global_regs->hfnum); ++ ++#ifdef DEBUG_SOF ++ DWC_DEBUGPL(DBG_HCD, "--Start of Frame Interrupt--\n"); ++#endif ++ hcd->frame_number = hfnum.b.frnum; ++ ++#ifdef DEBUG ++ hcd->frrem_accum += hfnum.b.frrem; ++ hcd->frrem_samples++; ++#endif ++ ++#ifdef DWC_TRACK_MISSED_SOFS ++ track_missed_sofs(hcd->frame_number); ++#endif ++ /* Determine whether any periodic QHs should be executed. */ ++ qh_entry = DWC_LIST_FIRST(&hcd->periodic_sched_inactive); ++ while (qh_entry != &hcd->periodic_sched_inactive) { ++ qh = DWC_LIST_ENTRY(qh_entry, dwc_otg_qh_t, qh_list_entry); ++ qh_entry = qh_entry->next; ++ if (dwc_frame_num_le(qh->sched_frame, hcd->frame_number)) { ++ /* ++ * Move QH to the ready list to be executed next ++ * (micro)frame. ++ */ ++ DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_ready, ++ &qh->qh_list_entry); ++ } ++ } ++ tr_type = dwc_otg_hcd_select_transactions(hcd); ++ if (tr_type != DWC_OTG_TRANSACTION_NONE) { ++ dwc_otg_hcd_queue_transactions(hcd, tr_type); ++ } ++ ++ /* Clear interrupt */ ++ gintsts.b.sofintr = 1; ++ dwc_write_reg32(&hcd->core_if->core_global_regs->gintsts, gintsts.d32); ++ ++ return 1; ++} ++ ++/** Handles the Rx Status Queue Level Interrupt, which indicates that there is at ++ * least one packet in the Rx FIFO. The packets are moved from the FIFO to ++ * memory if the DWC_otg controller is operating in Slave mode. */ ++int32_t dwc_otg_hcd_handle_rx_status_q_level_intr(dwc_otg_hcd_t * dwc_otg_hcd) ++{ ++ host_grxsts_data_t grxsts; ++ dwc_hc_t *hc = NULL; ++ ++ DWC_DEBUGPL(DBG_HCD, "--RxStsQ Level Interrupt--\n"); ++ ++ grxsts.d32 = ++ dwc_read_reg32(&dwc_otg_hcd->core_if->core_global_regs->grxstsp); ++ ++ hc = dwc_otg_hcd->hc_ptr_array[grxsts.b.chnum]; ++ ++ /* Packet Status */ ++ DWC_DEBUGPL(DBG_HCDV, " Ch num = %d\n", grxsts.b.chnum); ++ DWC_DEBUGPL(DBG_HCDV, " Count = %d\n", grxsts.b.bcnt); ++ DWC_DEBUGPL(DBG_HCDV, " DPID = %d, hc.dpid = %d\n", grxsts.b.dpid, ++ hc->data_pid_start); ++ DWC_DEBUGPL(DBG_HCDV, " PStatus = %d\n", grxsts.b.pktsts); ++ ++ switch (grxsts.b.pktsts) { ++ case DWC_GRXSTS_PKTSTS_IN: ++ /* Read the data into the host buffer. */ ++ if (grxsts.b.bcnt > 0) { ++ dwc_otg_read_packet(dwc_otg_hcd->core_if, ++ hc->xfer_buff, grxsts.b.bcnt); ++ ++ /* Update the HC fields for the next packet received. */ ++ hc->xfer_count += grxsts.b.bcnt; ++ hc->xfer_buff += grxsts.b.bcnt; ++ } ++ ++ case DWC_GRXSTS_PKTSTS_IN_XFER_COMP: ++ case DWC_GRXSTS_PKTSTS_DATA_TOGGLE_ERR: ++ case DWC_GRXSTS_PKTSTS_CH_HALTED: ++ /* Handled in interrupt, just ignore data */ ++ break; ++ default: ++ DWC_ERROR("RX_STS_Q Interrupt: Unknown status %d\n", ++ grxsts.b.pktsts); ++ break; ++ } ++ ++ return 1; ++} ++ ++/** This interrupt occurs when the non-periodic Tx FIFO is half-empty. More ++ * data packets may be written to the FIFO for OUT transfers. More requests ++ * may be written to the non-periodic request queue for IN transfers. This ++ * interrupt is enabled only in Slave mode. */ ++int32_t dwc_otg_hcd_handle_np_tx_fifo_empty_intr(dwc_otg_hcd_t * dwc_otg_hcd) ++{ ++ DWC_DEBUGPL(DBG_HCD, "--Non-Periodic TxFIFO Empty Interrupt--\n"); ++ dwc_otg_hcd_queue_transactions(dwc_otg_hcd, ++ DWC_OTG_TRANSACTION_NON_PERIODIC); ++ return 1; ++} ++ ++/** This interrupt occurs when the periodic Tx FIFO is half-empty. More data ++ * packets may be written to the FIFO for OUT transfers. More requests may be ++ * written to the periodic request queue for IN transfers. This interrupt is ++ * enabled only in Slave mode. */ ++int32_t dwc_otg_hcd_handle_perio_tx_fifo_empty_intr(dwc_otg_hcd_t * dwc_otg_hcd) ++{ ++ DWC_DEBUGPL(DBG_HCD, "--Periodic TxFIFO Empty Interrupt--\n"); ++ dwc_otg_hcd_queue_transactions(dwc_otg_hcd, ++ DWC_OTG_TRANSACTION_PERIODIC); ++ return 1; ++} ++ ++/** There are multiple conditions that can cause a port interrupt. This function ++ * determines which interrupt conditions have occurred and handles them ++ * appropriately. */ ++int32_t dwc_otg_hcd_handle_port_intr(dwc_otg_hcd_t * dwc_otg_hcd) ++{ ++ int retval = 0; ++ hprt0_data_t hprt0; ++ hprt0_data_t hprt0_modify; ++ ++ hprt0.d32 = dwc_read_reg32(dwc_otg_hcd->core_if->host_if->hprt0); ++ hprt0_modify.d32 = dwc_read_reg32(dwc_otg_hcd->core_if->host_if->hprt0); ++ ++ /* Clear appropriate bits in HPRT0 to clear the interrupt bit in ++ * GINTSTS */ ++ ++ hprt0_modify.b.prtena = 0; ++ hprt0_modify.b.prtconndet = 0; ++ hprt0_modify.b.prtenchng = 0; ++ hprt0_modify.b.prtovrcurrchng = 0; ++ ++ /* Port Connect Detected ++ * Set flag and clear if detected */ ++ if (hprt0.b.prtconndet) { ++ DWC_DEBUGPL(DBG_HCD, "--Port Interrupt HPRT0=0x%08x " ++ "Port Connect Detected--\n", hprt0.d32); ++ dwc_otg_hcd->flags.b.port_connect_status_change = 1; ++ dwc_otg_hcd->flags.b.port_connect_status = 1; ++ hprt0_modify.b.prtconndet = 1; ++ ++ /* B-Device has connected, Delete the connection timer. */ ++ DWC_TIMER_CANCEL(dwc_otg_hcd->conn_timer); ++ ++ /* The Hub driver asserts a reset when it sees port connect ++ * status change flag */ ++ retval |= 1; ++ } ++ ++ /* Port Enable Changed ++ * Clear if detected - Set internal flag if disabled */ ++ if (hprt0.b.prtenchng) { ++ DWC_DEBUGPL(DBG_HCD, " --Port Interrupt HPRT0=0x%08x " ++ "Port Enable Changed--\n", hprt0.d32); ++ hprt0_modify.b.prtenchng = 1; ++ if (hprt0.b.prtena == 1) { ++ int do_reset = 0; ++ dwc_otg_core_params_t *params = ++ dwc_otg_hcd->core_if->core_params; ++ dwc_otg_core_global_regs_t *global_regs = ++ dwc_otg_hcd->core_if->core_global_regs; ++ dwc_otg_host_if_t *host_if = ++ dwc_otg_hcd->core_if->host_if; ++ ++ /* Check if we need to adjust the PHY clock speed for ++ * low power and adjust it */ ++ if (params->host_support_fs_ls_low_power) { ++ gusbcfg_data_t usbcfg; ++ ++ usbcfg.d32 = ++ dwc_read_reg32(&global_regs->gusbcfg); ++ ++ if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_LOW_SPEED ++ || hprt0.b.prtspd == ++ DWC_HPRT0_PRTSPD_FULL_SPEED) { ++ /* ++ * Low power ++ */ ++ hcfg_data_t hcfg; ++ if (usbcfg.b.phylpwrclksel == 0) { ++ /* Set PHY low power clock select for FS/LS devices */ ++ usbcfg.b.phylpwrclksel = 1; ++ dwc_write_reg32(&global_regs-> ++ gusbcfg, ++ usbcfg.d32); ++ do_reset = 1; ++ } ++ ++ hcfg.d32 = ++ dwc_read_reg32(&host_if-> ++ host_global_regs->hcfg); ++ ++ if (hprt0.b.prtspd == ++ DWC_HPRT0_PRTSPD_LOW_SPEED ++ && params-> ++ host_ls_low_power_phy_clk == ++ DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ) ++ { ++ /* 6 MHZ */ ++ DWC_DEBUGPL(DBG_CIL, ++ "FS_PHY programming HCFG to 6 MHz (Low Power)\n"); ++ if (hcfg.b.fslspclksel != ++ DWC_HCFG_6_MHZ) { ++ hcfg.b.fslspclksel = ++ DWC_HCFG_6_MHZ; ++ dwc_write_reg32 ++ (&host_if-> ++ host_global_regs-> ++ hcfg, hcfg.d32); ++ do_reset = 1; ++ } ++ } else { ++ /* 48 MHZ */ ++ DWC_DEBUGPL(DBG_CIL, ++ "FS_PHY programming HCFG to 48 MHz ()\n"); ++ if (hcfg.b.fslspclksel != ++ DWC_HCFG_48_MHZ) { ++ hcfg.b.fslspclksel = ++ DWC_HCFG_48_MHZ; ++ dwc_write_reg32 ++ (&host_if-> ++ host_global_regs-> ++ hcfg, hcfg.d32); ++ do_reset = 1; ++ } ++ } ++ } else { ++ /* ++ * Not low power ++ */ ++ if (usbcfg.b.phylpwrclksel == 1) { ++ usbcfg.b.phylpwrclksel = 0; ++ dwc_write_reg32(&global_regs-> ++ gusbcfg, ++ usbcfg.d32); ++ do_reset = 1; ++ } ++ } ++ ++ if (do_reset) { ++ DWC_TASK_SCHEDULE(dwc_otg_hcd-> ++ reset_tasklet); ++ } ++ } ++ ++ if (!do_reset) { ++ /* Port has been enabled set the reset change flag */ ++ dwc_otg_hcd->flags.b.port_reset_change = 1; ++ } ++ } else { ++ dwc_otg_hcd->flags.b.port_enable_change = 1; ++ } ++ retval |= 1; ++ } ++ ++ /** Overcurrent Change Interrupt */ ++ if (hprt0.b.prtovrcurrchng) { ++ DWC_DEBUGPL(DBG_HCD, " --Port Interrupt HPRT0=0x%08x " ++ "Port Overcurrent Changed--\n", hprt0.d32); ++ dwc_otg_hcd->flags.b.port_over_current_change = 1; ++ hprt0_modify.b.prtovrcurrchng = 1; ++ retval |= 1; ++ } ++ ++ /* Clear Port Interrupts */ ++ dwc_write_reg32(dwc_otg_hcd->core_if->host_if->hprt0, hprt0_modify.d32); ++ ++ return retval; ++} ++ ++/** This interrupt indicates that one or more host channels has a pending ++ * interrupt. There are multiple conditions that can cause each host channel ++ * interrupt. This function determines which conditions have occurred for each ++ * host channel interrupt and handles them appropriately. */ ++int32_t dwc_otg_hcd_handle_hc_intr(dwc_otg_hcd_t * dwc_otg_hcd) ++{ ++ int i; ++ int retval = 0; ++ haint_data_t haint; ++ ++ /* Clear appropriate bits in HCINTn to clear the interrupt bit in ++ * GINTSTS */ ++ ++ haint.d32 = dwc_otg_read_host_all_channels_intr(dwc_otg_hcd->core_if); ++ ++ for (i = 0; i < dwc_otg_hcd->core_if->core_params->host_channels; i++) { ++ if (haint.b2.chint & (1 << i)) { ++ retval |= dwc_otg_hcd_handle_hc_n_intr(dwc_otg_hcd, i); ++ } ++ } ++ ++ return retval; ++} ++ ++ ++ ++/** ++ * Gets the actual length of a transfer after the transfer halts. _halt_status ++ * holds the reason for the halt. ++ * ++ * For IN transfers where halt_status is DWC_OTG_HC_XFER_COMPLETE, ++ * *short_read is set to 1 upon return if less than the requested ++ * number of bytes were transferred. Otherwise, *short_read is set to 0 upon ++ * return. short_read may also be NULL on entry, in which case it remains ++ * unchanged. ++ */ ++static uint32_t get_actual_xfer_length(dwc_hc_t * hc, ++ dwc_otg_hc_regs_t * hc_regs, ++ dwc_otg_qtd_t * qtd, ++ dwc_otg_halt_status_e halt_status, ++ int *short_read) ++{ ++ hctsiz_data_t hctsiz; ++ uint32_t length; ++ ++ if (short_read != NULL) { ++ *short_read = 0; ++ } ++ hctsiz.d32 = dwc_read_reg32(&hc_regs->hctsiz); ++ ++ if (halt_status == DWC_OTG_HC_XFER_COMPLETE) { ++ if (hc->ep_is_in) { ++ length = hc->xfer_len - hctsiz.b.xfersize; ++ if (short_read != NULL) { ++ *short_read = (hctsiz.b.xfersize != 0); ++ } ++ } else if (hc->qh->do_split) { ++ length = qtd->ssplit_out_xfer_count; ++ } else { ++ length = hc->xfer_len; ++ } ++ } else { ++ /* ++ * Must use the hctsiz.pktcnt field to determine how much data ++ * has been transferred. This field reflects the number of ++ * packets that have been transferred via the USB. This is ++ * always an integral number of packets if the transfer was ++ * halted before its normal completion. (Can't use the ++ * hctsiz.xfersize field because that reflects the number of ++ * bytes transferred via the AHB, not the USB). ++ */ ++ length = ++ (hc->start_pkt_count - hctsiz.b.pktcnt) * hc->max_packet; ++ } ++ ++ return length; ++} ++ ++/** ++ * Updates the state of the URB after a Transfer Complete interrupt on the ++ * host channel. Updates the actual_length field of the URB based on the ++ * number of bytes transferred via the host channel. Sets the URB status ++ * if the data transfer is finished. ++ * ++ * @return 1 if the data transfer specified by the URB is completely finished, ++ * 0 otherwise. ++ */ ++static int update_urb_state_xfer_comp(dwc_hc_t * hc, ++ dwc_otg_hc_regs_t * hc_regs, ++ dwc_otg_hcd_urb_t * urb, ++ dwc_otg_qtd_t * qtd) ++{ ++ int xfer_done = 0; ++ int short_read = 0; ++ ++ int xfer_length; ++ ++ xfer_length = get_actual_xfer_length(hc, hc_regs, qtd, ++ DWC_OTG_HC_XFER_COMPLETE, ++ &short_read); ++ ++ ++ /* non DWORD-aligned buffer case handling. */ ++ if (hc->align_buff && xfer_length && hc->ep_is_in) { ++ dwc_memcpy(urb->buf + urb->actual_length, hc->qh->dw_align_buf, xfer_length); ++ } ++ ++ urb->actual_length += xfer_length; ++ ++ if(xfer_length && (hc->ep_type == DWC_OTG_EP_TYPE_BULK) && ++ (urb->flags & URB_SEND_ZERO_PACKET) && (urb->actual_length == urb->length) && ++ !(urb->length % hc->max_packet)) { ++ xfer_done = 0; ++ } else if (short_read || urb->actual_length == urb->length) { ++ xfer_done = 1; ++ urb->status = 0; ++ } ++ ++#ifdef DEBUG ++ { ++ hctsiz_data_t hctsiz; ++ hctsiz.d32 = dwc_read_reg32(&hc_regs->hctsiz); ++ DWC_DEBUGPL(DBG_HCDV, "DWC_otg: %s: %s, channel %d\n", ++ __func__, (hc->ep_is_in ? "IN" : "OUT"), ++ hc->hc_num); ++ DWC_DEBUGPL(DBG_HCDV, " hc->xfer_len %d\n", hc->xfer_len); ++ DWC_DEBUGPL(DBG_HCDV, " hctsiz.xfersize %d\n", ++ hctsiz.b.xfersize); ++ DWC_DEBUGPL(DBG_HCDV, " urb->transfer_buffer_length %d\n", ++ urb->length); ++ DWC_DEBUGPL(DBG_HCDV, " urb->actual_length %d\n", ++ urb->actual_length); ++ DWC_DEBUGPL(DBG_HCDV, " short_read %d, xfer_done %d\n", ++ short_read, xfer_done); ++ } ++#endif ++ ++ return xfer_done; ++} ++ ++/* ++ * Save the starting data toggle for the next transfer. The data toggle is ++ * saved in the QH for non-control transfers and it's saved in the QTD for ++ * control transfers. ++ */ ++void dwc_otg_hcd_save_data_toggle(dwc_hc_t * hc, ++ dwc_otg_hc_regs_t * hc_regs, dwc_otg_qtd_t * qtd) ++{ ++ hctsiz_data_t hctsiz; ++ hctsiz.d32 = dwc_read_reg32(&hc_regs->hctsiz); ++ ++ if (hc->ep_type != DWC_OTG_EP_TYPE_CONTROL) { ++ dwc_otg_qh_t *qh = hc->qh; ++ if (hctsiz.b.pid == DWC_HCTSIZ_DATA0) { ++ qh->data_toggle = DWC_OTG_HC_PID_DATA0; ++ } else { ++ qh->data_toggle = DWC_OTG_HC_PID_DATA1; ++ } ++ } else { ++ if (hctsiz.b.pid == DWC_HCTSIZ_DATA0) { ++ qtd->data_toggle = DWC_OTG_HC_PID_DATA0; ++ } else { ++ qtd->data_toggle = DWC_OTG_HC_PID_DATA1; ++ } ++ } ++} ++ ++/** ++ * Updates the state of an Isochronous URB when the transfer is stopped for ++ * any reason. The fields of the current entry in the frame descriptor array ++ * are set based on the transfer state and the input _halt_status. Completes ++ * the Isochronous URB if all the URB frames have been completed. ++ * ++ * @return DWC_OTG_HC_XFER_COMPLETE if there are more frames remaining to be ++ * transferred in the URB. Otherwise return DWC_OTG_HC_XFER_URB_COMPLETE. ++ */ ++static dwc_otg_halt_status_e ++update_isoc_urb_state(dwc_otg_hcd_t * hcd, ++ dwc_hc_t * hc, ++ dwc_otg_hc_regs_t * hc_regs, ++ dwc_otg_qtd_t * qtd, dwc_otg_halt_status_e halt_status) ++{ ++ dwc_otg_hcd_urb_t *urb = qtd->urb; ++ dwc_otg_halt_status_e ret_val = halt_status; ++ struct dwc_otg_hcd_iso_packet_desc *frame_desc; ++ ++ frame_desc = &urb->iso_descs[qtd->isoc_frame_index]; ++ switch (halt_status) { ++ case DWC_OTG_HC_XFER_COMPLETE: ++ frame_desc->status = 0; ++ frame_desc->actual_length = ++ get_actual_xfer_length(hc, hc_regs, qtd, halt_status, NULL); ++ ++ /* non DWORD-aligned buffer case handling. */ ++ if (hc->align_buff && frame_desc->actual_length && hc->ep_is_in) { ++ dwc_memcpy(urb->buf + frame_desc->offset + qtd->isoc_split_offset, ++ hc->qh->dw_align_buf, frame_desc->actual_length); ++ } ++ ++ break; ++ case DWC_OTG_HC_XFER_FRAME_OVERRUN: ++ urb->error_count++; ++ if (hc->ep_is_in) { ++ frame_desc->status = -DWC_E_NO_STREAM_RES; ++ } else { ++ frame_desc->status = -DWC_E_COMMUNICATION; ++ } ++ frame_desc->actual_length = 0; ++ break; ++ case DWC_OTG_HC_XFER_BABBLE_ERR: ++ urb->error_count++; ++ frame_desc->status = -DWC_E_OVERFLOW; ++ /* Don't need to update actual_length in this case. */ ++ break; ++ case DWC_OTG_HC_XFER_XACT_ERR: ++ urb->error_count++; ++ frame_desc->status = -DWC_E_PROTOCOL; ++ frame_desc->actual_length = ++ get_actual_xfer_length(hc, hc_regs, qtd, halt_status, NULL); ++ ++ /* non DWORD-aligned buffer case handling. */ ++ if (hc->align_buff && frame_desc->actual_length && hc->ep_is_in) { ++ dwc_memcpy(urb->buf + frame_desc->offset + qtd->isoc_split_offset, ++ hc->qh->dw_align_buf, frame_desc->actual_length); ++ } ++ /* Skip whole frame */ ++ if (hc->qh->do_split && (hc->ep_type == DWC_OTG_EP_TYPE_ISOC) && ++ hc->ep_is_in && hcd->core_if->dma_enable) { ++ qtd->complete_split = 0; ++ qtd->isoc_split_offset = 0; ++ } ++ ++ break; ++ default: ++ DWC_ASSERT(1, "Unhandled _halt_status (%d)\n", halt_status); ++ break; ++ } ++ if (++qtd->isoc_frame_index == urb->packet_count) { ++ /* ++ * urb->status is not used for isoc transfers. ++ * The individual frame_desc statuses are used instead. ++ */ ++ hcd->fops->complete(hcd, urb->priv, urb, 0); ++ ret_val = DWC_OTG_HC_XFER_URB_COMPLETE; ++ } else { ++ ret_val = DWC_OTG_HC_XFER_COMPLETE; ++ } ++ return ret_val; ++} ++ ++/** ++ * Frees the first QTD in the QH's list if free_qtd is 1. For non-periodic ++ * QHs, removes the QH from the active non-periodic schedule. If any QTDs are ++ * still linked to the QH, the QH is added to the end of the inactive ++ * non-periodic schedule. For periodic QHs, removes the QH from the periodic ++ * schedule if no more QTDs are linked to the QH. ++ */ ++static void deactivate_qh(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh, int free_qtd) ++{ ++ int continue_split = 0; ++ dwc_otg_qtd_t *qtd; ++ ++ DWC_DEBUGPL(DBG_HCDV, " %s(%p,%p,%d)\n", __func__, hcd, qh, free_qtd); ++ ++ qtd = DWC_CIRCLEQ_FIRST(&qh->qtd_list); ++ ++ if (qtd->complete_split) { ++ continue_split = 1; ++ } else if (qtd->isoc_split_pos == DWC_HCSPLIT_XACTPOS_MID || ++ qtd->isoc_split_pos == DWC_HCSPLIT_XACTPOS_END) { ++ continue_split = 1; ++ } ++ ++ if (free_qtd) { ++ dwc_otg_hcd_qtd_remove_and_free(hcd, qtd, qh); ++ continue_split = 0; ++ } ++ ++ qh->channel = NULL; ++ dwc_otg_hcd_qh_deactivate(hcd, qh, continue_split); ++} ++ ++/** ++ * Releases a host channel for use by other transfers. Attempts to select and ++ * queue more transactions since at least one host channel is available. ++ * ++ * @param hcd The HCD state structure. ++ * @param hc The host channel to release. ++ * @param qtd The QTD associated with the host channel. This QTD may be freed ++ * if the transfer is complete or an error has occurred. ++ * @param halt_status Reason the channel is being released. This status ++ * determines the actions taken by this function. ++ */ ++static void release_channel(dwc_otg_hcd_t * hcd, ++ dwc_hc_t * hc, ++ dwc_otg_qtd_t * qtd, ++ dwc_otg_halt_status_e halt_status) ++{ ++ dwc_otg_transaction_type_e tr_type; ++ int free_qtd; ++ ++ DWC_DEBUGPL(DBG_HCDV, " %s: channel %d, halt_status %d, xfer_len %d\n", ++ __func__, hc->hc_num, halt_status, hc->xfer_len); ++ ++#ifdef HW2937_WORKAROUND ++ if (hcd->hw2937_assigned_channels & (1<hc_num)) ++ { ++ if ((hcd->hw2937_assigned_channels &= ~(1<hc_num)) == 0) ++ hcd->hw2937_xfer_mode = HW2937_XFER_MODE_IDLE; ++ DWC_DEBUGPL(DBG_HW2937, " release %d, hw2937_ac -> %x\n", hc->hc_num, hcd->hw2937_assigned_channels); ++ } ++ else ++ { ++ DWC_DEBUGPL(DBG_ANY, " Unexpected release %d (hw2937_ac = %x)\n", hc->hc_num, hcd->hw2937_assigned_channels); ++ } ++#endif ++ ++ switch (halt_status) { ++ case DWC_OTG_HC_XFER_URB_COMPLETE: ++ free_qtd = 1; ++ break; ++ case DWC_OTG_HC_XFER_AHB_ERR: ++ case DWC_OTG_HC_XFER_STALL: ++ case DWC_OTG_HC_XFER_BABBLE_ERR: ++ free_qtd = 1; ++ break; ++ case DWC_OTG_HC_XFER_XACT_ERR: ++ if (qtd->error_count >= 3) { ++ DWC_DEBUGPL(DBG_HCDV, ++ " Complete URB with transaction error\n"); ++ free_qtd = 1; ++ qtd->urb->status = -DWC_E_PROTOCOL; ++ hcd->fops->complete(hcd, qtd->urb->priv, ++ qtd->urb, -DWC_E_PROTOCOL); ++ } else { ++ free_qtd = 0; ++ } ++ break; ++ case DWC_OTG_HC_XFER_URB_DEQUEUE: ++ /* ++ * The QTD has already been removed and the QH has been ++ * deactivated. Don't want to do anything except release the ++ * host channel and try to queue more transfers. ++ */ ++ goto cleanup; ++ case DWC_OTG_HC_XFER_NO_HALT_STATUS: ++ free_qtd = 0; ++ break; ++ default: ++ free_qtd = 0; ++ break; ++ } ++ ++ deactivate_qh(hcd, hc->qh, free_qtd); ++ ++ cleanup: ++ /* ++ * Release the host channel for use by other transfers. The cleanup ++ * function clears the channel interrupt enables and conditions, so ++ * there's no need to clear the Channel Halted interrupt separately. ++ */ ++ dwc_otg_hc_cleanup(hcd->core_if, hc); ++ DWC_CIRCLEQ_INSERT_TAIL(&hcd->free_hc_list, hc, hc_list_entry); ++ ++ switch (hc->ep_type) { ++ case DWC_OTG_EP_TYPE_CONTROL: ++ case DWC_OTG_EP_TYPE_BULK: ++ hcd->non_periodic_channels--; ++ break; ++ ++ default: ++ /* ++ * Don't release reservations for periodic channels here. ++ * That's done when a periodic transfer is descheduled (i.e. ++ * when the QH is removed from the periodic schedule). ++ */ ++ break; ++ } ++ ++ /* Try to queue more transfers now that there's a free channel. */ ++ tr_type = dwc_otg_hcd_select_transactions(hcd); ++ if (tr_type != DWC_OTG_TRANSACTION_NONE) { ++ dwc_otg_hcd_queue_transactions(hcd, tr_type); ++ } ++} ++ ++ ++/** ++ * Halts a host channel. If the channel cannot be halted immediately because ++ * the request queue is full, this function ensures that the FIFO empty ++ * interrupt for the appropriate queue is enabled so that the halt request can ++ * be queued when there is space in the request queue. ++ * ++ * This function may also be called in DMA mode. In that case, the channel is ++ * simply released since the core always halts the channel automatically in ++ * DMA mode. ++ */ ++static void halt_channel(dwc_otg_hcd_t * hcd, ++ dwc_hc_t * hc, ++ dwc_otg_qtd_t * qtd, dwc_otg_halt_status_e halt_status) ++{ ++ if (hcd->core_if->dma_enable) { ++ release_channel(hcd, hc, qtd, halt_status); ++ return; ++ } ++ ++ /* Slave mode processing... */ ++ dwc_otg_hc_halt(hcd->core_if, hc, halt_status); ++ ++ if (hc->halt_on_queue) { ++ gintmsk_data_t gintmsk = {.d32 = 0 }; ++ dwc_otg_core_global_regs_t *global_regs; ++ global_regs = hcd->core_if->core_global_regs; ++ ++ if (hc->ep_type == DWC_OTG_EP_TYPE_CONTROL || ++ hc->ep_type == DWC_OTG_EP_TYPE_BULK) { ++ /* ++ * Make sure the Non-periodic Tx FIFO empty interrupt ++ * is enabled so that the non-periodic schedule will ++ * be processed. ++ */ ++ gintmsk.b.nptxfempty = 1; ++ dwc_modify_reg32(&global_regs->gintmsk, 0, gintmsk.d32); ++ } else { ++ /* ++ * Move the QH from the periodic queued schedule to ++ * the periodic assigned schedule. This allows the ++ * halt to be queued when the periodic schedule is ++ * processed. ++ */ ++ DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_assigned, ++ &hc->qh->qh_list_entry); ++ ++ /* ++ * Make sure the Periodic Tx FIFO Empty interrupt is ++ * enabled so that the periodic schedule will be ++ * processed. ++ */ ++ gintmsk.b.ptxfempty = 1; ++ dwc_modify_reg32(&global_regs->gintmsk, 0, gintmsk.d32); ++ } ++ } ++} ++ ++/** ++ * Performs common cleanup for non-periodic transfers after a Transfer ++ * Complete interrupt. This function should be called after any endpoint type ++ * specific handling is finished to release the host channel. ++ */ ++static void complete_non_periodic_xfer(dwc_otg_hcd_t * hcd, ++ dwc_hc_t * hc, ++ dwc_otg_hc_regs_t * hc_regs, ++ dwc_otg_qtd_t * qtd, ++ dwc_otg_halt_status_e halt_status) ++{ ++ hcint_data_t hcint; ++ ++ qtd->error_count = 0; ++ ++ hcint.d32 = dwc_read_reg32(&hc_regs->hcint); ++ if (hcint.b.nyet) { ++ /* ++ * Got a NYET on the last transaction of the transfer. This ++ * means that the endpoint should be in the PING state at the ++ * beginning of the next transfer. ++ */ ++ hc->qh->ping_state = 1; ++ clear_hc_int(hc_regs, nyet); ++ } ++ ++ /* ++ * Always halt and release the host channel to make it available for ++ * more transfers. There may still be more phases for a control ++ * transfer or more data packets for a bulk transfer at this point, ++ * but the host channel is still halted. A channel will be reassigned ++ * to the transfer when the non-periodic schedule is processed after ++ * the channel is released. This allows transactions to be queued ++ * properly via dwc_otg_hcd_queue_transactions, which also enables the ++ * Tx FIFO Empty interrupt if necessary. ++ */ ++ if (hc->ep_is_in) { ++ /* ++ * IN transfers in Slave mode require an explicit disable to ++ * halt the channel. (In DMA mode, this call simply releases ++ * the channel.) ++ */ ++ halt_channel(hcd, hc, qtd, halt_status); ++ } else { ++ /* ++ * The channel is automatically disabled by the core for OUT ++ * transfers in Slave mode. ++ */ ++ release_channel(hcd, hc, qtd, halt_status); ++ } ++} ++ ++/** ++ * Performs common cleanup for periodic transfers after a Transfer Complete ++ * interrupt. This function should be called after any endpoint type specific ++ * handling is finished to release the host channel. ++ */ ++static void complete_periodic_xfer(dwc_otg_hcd_t * hcd, ++ dwc_hc_t * hc, ++ dwc_otg_hc_regs_t * hc_regs, ++ dwc_otg_qtd_t * qtd, ++ dwc_otg_halt_status_e halt_status) ++{ ++ hctsiz_data_t hctsiz; ++ qtd->error_count = 0; ++ ++ hctsiz.d32 = dwc_read_reg32(&hc_regs->hctsiz); ++ if (!hc->ep_is_in || hctsiz.b.pktcnt == 0) { ++ /* Core halts channel in these cases. */ ++ release_channel(hcd, hc, qtd, halt_status); ++ } else { ++ /* Flush any outstanding requests from the Tx queue. */ ++ halt_channel(hcd, hc, qtd, halt_status); ++ } ++} ++ ++static int32_t handle_xfercomp_isoc_split_in(dwc_otg_hcd_t * hcd, ++ dwc_hc_t * hc, ++ dwc_otg_hc_regs_t * hc_regs, ++ dwc_otg_qtd_t * qtd) ++{ ++ uint32_t len; ++ struct dwc_otg_hcd_iso_packet_desc *frame_desc; ++ frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index]; ++ ++ len = get_actual_xfer_length(hc, hc_regs, qtd, ++ DWC_OTG_HC_XFER_COMPLETE, ++ NULL); ++ ++ if (!len) { ++ qtd->complete_split = 0; ++ qtd->isoc_split_offset = 0; ++ return 0; ++ } ++ frame_desc->actual_length += len; ++ ++ if (hc->align_buff && len) ++ dwc_memcpy(qtd->urb->buf + frame_desc->offset + qtd->isoc_split_offset, ++ hc->qh->dw_align_buf, ++ len); ++ qtd->isoc_split_offset += len; ++ ++ if (frame_desc->length == frame_desc->actual_length) { ++ frame_desc->status = 0; ++ qtd->isoc_frame_index++; ++ qtd->complete_split = 0; ++ qtd->isoc_split_offset = 0; ++ } ++ ++ if (qtd->isoc_frame_index == qtd->urb->packet_count) { ++ hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, 0); ++ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE); ++ } else { ++ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NO_HALT_STATUS); ++ } ++ ++ return 1; /* Indicates that channel released */ ++} ++/** ++ * Handles a host channel Transfer Complete interrupt. This handler may be ++ * called in either DMA mode or Slave mode. ++ */ ++static int32_t handle_hc_xfercomp_intr(dwc_otg_hcd_t * hcd, ++ dwc_hc_t * hc, ++ dwc_otg_hc_regs_t * hc_regs, ++ dwc_otg_qtd_t * qtd) ++{ ++ int urb_xfer_done; ++ dwc_otg_halt_status_e halt_status = DWC_OTG_HC_XFER_COMPLETE; ++ dwc_otg_hcd_urb_t *urb = qtd->urb; ++ int pipe_type = dwc_otg_hcd_get_pipe_type(&urb->pipe_info); ++ ++ DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: " ++ "Transfer Complete--\n", hc->hc_num); ++ ++ if (hcd->core_if->dma_desc_enable) { ++ dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs, halt_status); ++ if (pipe_type == UE_ISOCHRONOUS) { ++ /* Do not disable the interrupt, just clear it */ ++ clear_hc_int(hc_regs, xfercomp); ++ return 1; ++ } ++ goto handle_xfercomp_done; ++ } ++ ++ /* ++ * Handle xfer complete on CSPLIT. ++ */ ++ ++ if (hc->qh->do_split) { ++ if ((hc->ep_type == DWC_OTG_EP_TYPE_ISOC) && hc->ep_is_in && hcd->core_if->dma_enable) { ++ if (qtd->complete_split && handle_xfercomp_isoc_split_in(hcd, hc, hc_regs, qtd)) ++ goto handle_xfercomp_done; ++ } ++ else { ++ qtd->complete_split = 0; ++ } ++ } ++ ++ /* Update the QTD and URB states. */ ++ switch (pipe_type) { ++ case UE_CONTROL: ++ switch (qtd->control_phase) { ++ case DWC_OTG_CONTROL_SETUP: ++ if (urb->length > 0) { ++ qtd->control_phase = DWC_OTG_CONTROL_DATA; ++ } else { ++ qtd->control_phase = DWC_OTG_CONTROL_STATUS; ++ } ++ DWC_DEBUGPL(DBG_HCDV, ++ " Control setup transaction done\n"); ++ halt_status = DWC_OTG_HC_XFER_COMPLETE; ++ break; ++ case DWC_OTG_CONTROL_DATA:{ ++ urb_xfer_done = ++ update_urb_state_xfer_comp(hc, hc_regs, urb, ++ qtd); ++ if (urb_xfer_done) { ++ qtd->control_phase = ++ DWC_OTG_CONTROL_STATUS; ++ DWC_DEBUGPL(DBG_HCDV, ++ " Control data transfer done\n"); ++ } else { ++ dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd); ++ } ++ halt_status = DWC_OTG_HC_XFER_COMPLETE; ++ break; ++ } ++ case DWC_OTG_CONTROL_STATUS: ++ DWC_DEBUGPL(DBG_HCDV, " Control transfer complete\n"); ++ if (urb->status == -DWC_E_IN_PROGRESS) { ++ urb->status = 0; ++ } ++ hcd->fops->complete(hcd, urb->priv, urb, urb->status); ++ halt_status = DWC_OTG_HC_XFER_URB_COMPLETE; ++ break; ++ } ++ ++ complete_non_periodic_xfer(hcd, hc, hc_regs, qtd, halt_status); ++ break; ++ case UE_BULK: ++ DWC_DEBUGPL(DBG_HCDV, " Bulk transfer complete\n"); ++ urb_xfer_done = ++ update_urb_state_xfer_comp(hc, hc_regs, urb, qtd); ++ if (urb_xfer_done) { ++ hcd->fops->complete(hcd, urb->priv, urb, urb->status); ++ halt_status = DWC_OTG_HC_XFER_URB_COMPLETE; ++ } else { ++ halt_status = DWC_OTG_HC_XFER_COMPLETE; ++ } ++ ++ dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd); ++ complete_non_periodic_xfer(hcd, hc, hc_regs, qtd, halt_status); ++ break; ++ case UE_INTERRUPT: ++ DWC_DEBUGPL(DBG_HCDV, " Interrupt transfer complete\n"); ++ update_urb_state_xfer_comp(hc, hc_regs, urb, qtd); ++ ++ /* ++ * Interrupt URB is done on the first transfer complete ++ * interrupt. ++ */ ++ hcd->fops->complete(hcd, urb->priv, urb, urb->status); ++ dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd); ++ complete_periodic_xfer(hcd, hc, hc_regs, qtd, ++ DWC_OTG_HC_XFER_URB_COMPLETE); ++ break; ++ case UE_ISOCHRONOUS: ++ DWC_DEBUGPL(DBG_HCDV, " Isochronous transfer complete\n"); ++ if (qtd->isoc_split_pos == DWC_HCSPLIT_XACTPOS_ALL) { ++ halt_status = ++ update_isoc_urb_state(hcd, hc, hc_regs, qtd, ++ DWC_OTG_HC_XFER_COMPLETE); ++ } ++ complete_periodic_xfer(hcd, hc, hc_regs, qtd, halt_status); ++ break; ++ } ++ ++handle_xfercomp_done: ++ disable_hc_int(hc_regs, xfercompl); ++ ++ return 1; ++} ++ ++/** ++ * Handles a host channel STALL interrupt. This handler may be called in ++ * either DMA mode or Slave mode. ++ */ ++static int32_t handle_hc_stall_intr(dwc_otg_hcd_t * hcd, ++ dwc_hc_t * hc, ++ dwc_otg_hc_regs_t * hc_regs, ++ dwc_otg_qtd_t * qtd) ++{ ++ dwc_otg_hcd_urb_t *urb = qtd->urb; ++ int pipe_type = dwc_otg_hcd_get_pipe_type(&urb->pipe_info); ++ ++ DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: " ++ "STALL Received--\n", hc->hc_num); ++ ++ if (hcd->core_if->dma_desc_enable) { ++ dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs, DWC_OTG_HC_XFER_STALL); ++ goto handle_stall_done; ++ } ++ ++ if (pipe_type == UE_CONTROL) { ++ hcd->fops->complete(hcd, urb->priv, urb, -DWC_E_PIPE); ++ } ++ ++ if (pipe_type == UE_BULK || pipe_type == UE_INTERRUPT) { ++ hcd->fops->complete(hcd, urb->priv, urb, -DWC_E_PIPE); ++ /* ++ * USB protocol requires resetting the data toggle for bulk ++ * and interrupt endpoints when a CLEAR_FEATURE(ENDPOINT_HALT) ++ * setup command is issued to the endpoint. Anticipate the ++ * CLEAR_FEATURE command since a STALL has occurred and reset ++ * the data toggle now. ++ */ ++ hc->qh->data_toggle = 0; ++ } ++ ++ halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_STALL); ++ ++handle_stall_done: ++ disable_hc_int(hc_regs, stall); ++ ++ return 1; ++} ++ ++/* ++ * Updates the state of the URB when a transfer has been stopped due to an ++ * abnormal condition before the transfer completes. Modifies the ++ * actual_length field of the URB to reflect the number of bytes that have ++ * actually been transferred via the host channel. ++ */ ++static void update_urb_state_xfer_intr(dwc_hc_t * hc, ++ dwc_otg_hc_regs_t * hc_regs, ++ dwc_otg_hcd_urb_t * urb, ++ dwc_otg_qtd_t * qtd, ++ dwc_otg_halt_status_e halt_status) ++{ ++ uint32_t bytes_transferred = get_actual_xfer_length(hc, hc_regs, qtd, ++ halt_status, NULL); ++ /* non DWORD-aligned buffer case handling. */ ++ if (hc->align_buff && bytes_transferred && hc->ep_is_in) { ++ dwc_memcpy(urb->buf + urb->actual_length, hc->qh->dw_align_buf, bytes_transferred); ++ } ++ ++ urb->actual_length += bytes_transferred; ++ ++#ifdef DEBUG ++ { ++ hctsiz_data_t hctsiz; ++ hctsiz.d32 = dwc_read_reg32(&hc_regs->hctsiz); ++ DWC_DEBUGPL(DBG_HCDV, "DWC_otg: %s: %s, channel %d\n", ++ __func__, (hc->ep_is_in ? "IN" : "OUT"), ++ hc->hc_num); ++ DWC_DEBUGPL(DBG_HCDV, " hc->start_pkt_count %d\n", ++ hc->start_pkt_count); ++ DWC_DEBUGPL(DBG_HCDV, " hctsiz.pktcnt %d\n", hctsiz.b.pktcnt); ++ DWC_DEBUGPL(DBG_HCDV, " hc->max_packet %d\n", hc->max_packet); ++ DWC_DEBUGPL(DBG_HCDV, " bytes_transferred %d\n", ++ bytes_transferred); ++ DWC_DEBUGPL(DBG_HCDV, " urb->actual_length %d\n", ++ urb->actual_length); ++ DWC_DEBUGPL(DBG_HCDV, " urb->transfer_buffer_length %d\n", ++ urb->length); ++ } ++#endif ++} ++ ++/** ++ * Handles a host channel NAK interrupt. This handler may be called in either ++ * DMA mode or Slave mode. ++ */ ++static int32_t handle_hc_nak_intr(dwc_otg_hcd_t * hcd, ++ dwc_hc_t * hc, ++ dwc_otg_hc_regs_t * hc_regs, ++ dwc_otg_qtd_t * qtd) ++{ ++ DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: " ++ "NAK Received--\n", hc->hc_num); ++ ++ /* ++ * Handle NAK for IN/OUT SSPLIT/CSPLIT transfers, bulk, control, and ++ * interrupt. Re-start the SSPLIT transfer. ++ */ ++ if (hc->do_split) { ++ if (hc->complete_split) { ++ qtd->error_count = 0; ++ } ++ qtd->complete_split = 0; ++ halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NAK); ++ goto handle_nak_done; ++ } ++ ++ switch (dwc_otg_hcd_get_pipe_type(&qtd->urb->pipe_info)) { ++ case UE_CONTROL: ++ case UE_BULK: ++ if (hcd->core_if->dma_enable && hc->ep_is_in) { ++#ifdef HW2937_WORKAROUND ++ if (hc->halt_status == DWC_OTG_HC_XFER_PAUSE_IN) { ++ halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NAK); ++ } ++#endif ++ /* ++ * NAK interrupts are enabled on bulk/control IN ++ * transfers in DMA mode for the sole purpose of ++ * resetting the error count after a transaction error ++ * occurs. The core will continue transferring data. ++ */ ++ qtd->error_count = 0; ++ goto handle_nak_done; ++ } ++ ++ /* ++ * NAK interrupts normally occur during OUT transfers in DMA ++ * or Slave mode. For IN transfers, more requests will be ++ * queued as request queue space is available. ++ */ ++ qtd->error_count = 0; ++ ++ if (!hc->qh->ping_state) { ++ update_urb_state_xfer_intr(hc, hc_regs, ++ qtd->urb, qtd, ++ DWC_OTG_HC_XFER_NAK); ++ dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd); ++ ++ if (hc->speed == DWC_OTG_EP_SPEED_HIGH) ++ hc->qh->ping_state = 1; ++ } ++ ++ /* ++ * Halt the channel so the transfer can be re-started from ++ * the appropriate point or the PING protocol will ++ * start/continue. ++ */ ++ halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NAK); ++ break; ++ case UE_INTERRUPT: ++ qtd->error_count = 0; ++ halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NAK); ++ break; ++ case UE_ISOCHRONOUS: ++#ifdef HW2937_WORKAROUND ++ if (hc->halt_status == DWC_OTG_HC_XFER_PAUSE_IN) { ++ halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NAK); ++ break; ++ } ++#endif ++ /* Should never get called for isochronous transfers. */ ++ DWC_ASSERT(1, "NACK interrupt for ISOC transfer\n"); ++ break; ++ } ++ ++ handle_nak_done: ++ disable_hc_int(hc_regs, nak); ++ ++ return 1; ++} ++ ++/** ++ * Handles a host channel ACK interrupt. This interrupt is enabled when ++ * performing the PING protocol in Slave mode, when errors occur during ++ * either Slave mode or DMA mode, and during Start Split transactions. ++ */ ++static int32_t handle_hc_ack_intr(dwc_otg_hcd_t * hcd, ++ dwc_hc_t * hc, ++ dwc_otg_hc_regs_t * hc_regs, ++ dwc_otg_qtd_t * qtd) ++{ ++ DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: " ++ "ACK Received--\n", hc->hc_num); ++ ++ if (hc->do_split) { ++ /* ++ * Handle ACK on SSPLIT. ++ * ACK should not occur in CSPLIT. ++ */ ++ if (!hc->ep_is_in && hc->data_pid_start != DWC_OTG_HC_PID_SETUP) { ++ qtd->ssplit_out_xfer_count = hc->xfer_len; ++ } ++ if (!(hc->ep_type == DWC_OTG_EP_TYPE_ISOC && !hc->ep_is_in)) { ++ /* Don't need complete for isochronous out transfers. */ ++ qtd->complete_split = 1; ++ } ++ ++ /* ISOC OUT */ ++ if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC && !hc->ep_is_in) { ++ switch (hc->xact_pos) { ++ case DWC_HCSPLIT_XACTPOS_ALL: ++ break; ++ case DWC_HCSPLIT_XACTPOS_END: ++ qtd->isoc_split_pos = DWC_HCSPLIT_XACTPOS_ALL; ++ qtd->isoc_split_offset = 0; ++ break; ++ case DWC_HCSPLIT_XACTPOS_BEGIN: ++ case DWC_HCSPLIT_XACTPOS_MID: ++ /* ++ * For BEGIN or MID, calculate the length for ++ * the next microframe to determine the correct ++ * SSPLIT token, either MID or END. ++ */ ++ { ++ struct dwc_otg_hcd_iso_packet_desc ++ *frame_desc; ++ ++ frame_desc = ++ &qtd->urb->iso_descs[qtd-> ++ isoc_frame_index]; ++ qtd->isoc_split_offset += 188; ++ ++ if ((frame_desc->length - ++ qtd->isoc_split_offset) <= 188) { ++ qtd->isoc_split_pos = ++ DWC_HCSPLIT_XACTPOS_END; ++ } else { ++ qtd->isoc_split_pos = ++ DWC_HCSPLIT_XACTPOS_MID; ++ } ++ ++ } ++ break; ++ } ++ } else { ++ halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_ACK); ++ } ++ } else { ++ qtd->error_count = 0; ++ ++ if (hc->qh->ping_state) { ++ hc->qh->ping_state = 0; ++ /* ++ * Halt the channel so the transfer can be re-started ++ * from the appropriate point. This only happens in ++ * Slave mode. In DMA mode, the ping_state is cleared ++ * when the transfer is started because the core ++ * automatically executes the PING, then the transfer. ++ */ ++ halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_ACK); ++ } ++#ifdef HW2937_WORKAROUND ++ else if (hc->halt_status == DWC_OTG_HC_XFER_PAUSE_IN) { ++ dwc_otg_hc_regs_t *hc_regs = hcd->core_if->host_if->hc_regs[hc->hc_num]; ++ update_urb_state_xfer_intr(hc, hc_regs, qtd->urb, qtd, DWC_OTG_HC_XFER_PAUSE_IN); ++ dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd); ++ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_PAUSE_IN); ++ } ++#endif ++ } ++ ++ /* ++ * If the ACK occurred when _not_ in the PING state, let the channel ++ * continue transferring data after clearing the error count. ++ */ ++ ++ disable_hc_int(hc_regs, ack); ++ ++ return 1; ++} ++ ++/** ++ * Handles a host channel NYET interrupt. This interrupt should only occur on ++ * Bulk and Control OUT endpoints and for complete split transactions. If a ++ * NYET occurs at the same time as a Transfer Complete interrupt, it is ++ * handled in the xfercomp interrupt handler, not here. This handler may be ++ * called in either DMA mode or Slave mode. ++ */ ++static int32_t handle_hc_nyet_intr(dwc_otg_hcd_t * hcd, ++ dwc_hc_t * hc, ++ dwc_otg_hc_regs_t * hc_regs, ++ dwc_otg_qtd_t * qtd) ++{ ++ DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: " ++ "NYET Received--\n", hc->hc_num); ++ ++ /* ++ * NYET on CSPLIT ++ * re-do the CSPLIT immediately on non-periodic ++ */ ++ if (hc->do_split && hc->complete_split) { ++ if (hc->ep_is_in && (hc->ep_type == DWC_OTG_EP_TYPE_ISOC) && hcd->core_if->dma_enable) { ++ qtd->complete_split = 0; ++ qtd->isoc_split_offset = 0; ++ if (++qtd->isoc_frame_index == qtd->urb->packet_count) { ++ hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, 0); ++ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE); ++ } ++ else ++ release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NO_HALT_STATUS); ++ goto handle_nyet_done; ++ } ++ ++ if (hc->ep_type == DWC_OTG_EP_TYPE_INTR || ++ hc->ep_type == DWC_OTG_EP_TYPE_ISOC) { ++ int frnum = dwc_otg_hcd_get_frame_number(hcd); ++ ++ if (dwc_full_frame_num(frnum) != ++ dwc_full_frame_num(hc->qh->sched_frame)) { ++ /* ++ * No longer in the same full speed frame. ++ * Treat this as a transaction error. ++ */ ++#if 0 ++ /** @todo Fix system performance so this can ++ * be treated as an error. Right now complete ++ * splits cannot be scheduled precisely enough ++ * due to other system activity, so this error ++ * occurs regularly in Slave mode. ++ */ ++ qtd->error_count++; ++#endif ++ qtd->complete_split = 0; ++ halt_channel(hcd, hc, qtd, ++ DWC_OTG_HC_XFER_XACT_ERR); ++ /** @todo add support for isoc release */ ++ goto handle_nyet_done; ++ } ++ } ++ ++ halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NYET); ++ goto handle_nyet_done; ++ } ++ ++ hc->qh->ping_state = 1; ++ qtd->error_count = 0; ++ ++ update_urb_state_xfer_intr(hc, hc_regs, qtd->urb, qtd, ++ DWC_OTG_HC_XFER_NYET); ++ dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd); ++ ++ /* ++ * Halt the channel and re-start the transfer so the PING ++ * protocol will start. ++ */ ++ halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NYET); ++ ++ handle_nyet_done: ++ disable_hc_int(hc_regs, nyet); ++ return 1; ++} ++ ++/** ++ * Handles a host channel babble interrupt. This handler may be called in ++ * either DMA mode or Slave mode. ++ */ ++static int32_t handle_hc_babble_intr(dwc_otg_hcd_t * hcd, ++ dwc_hc_t * hc, ++ dwc_otg_hc_regs_t * hc_regs, ++ dwc_otg_qtd_t * qtd) ++{ ++ DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: " ++ "Babble Error--\n", hc->hc_num); ++ ++ if (hcd->core_if->dma_desc_enable) { ++ dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs, DWC_OTG_HC_XFER_BABBLE_ERR); ++ goto handle_babble_done; ++ } ++ ++ if (hc->ep_type != DWC_OTG_EP_TYPE_ISOC) { ++ hcd->fops->complete(hcd, qtd->urb->priv, ++ qtd->urb, -DWC_E_OVERFLOW); ++ halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_BABBLE_ERR); ++ } else { ++ dwc_otg_halt_status_e halt_status; ++ halt_status = update_isoc_urb_state(hcd, hc, hc_regs, qtd, ++ DWC_OTG_HC_XFER_BABBLE_ERR); ++ halt_channel(hcd, hc, qtd, halt_status); ++ } ++ ++handle_babble_done: ++ disable_hc_int(hc_regs, bblerr); ++ return 1; ++} ++ ++/** ++ * Handles a host channel AHB error interrupt. This handler is only called in ++ * DMA mode. ++ */ ++static int32_t handle_hc_ahberr_intr(dwc_otg_hcd_t * hcd, ++ dwc_hc_t * hc, ++ dwc_otg_hc_regs_t * hc_regs, ++ dwc_otg_qtd_t * qtd) ++{ ++ hcchar_data_t hcchar; ++ hcsplt_data_t hcsplt; ++ hctsiz_data_t hctsiz; ++ uint32_t hcdma; ++ char *pipetype, *speed; ++ ++ dwc_otg_hcd_urb_t *urb = qtd->urb; ++ ++ DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: " ++ "AHB Error--\n", hc->hc_num); ++ ++ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); ++ hcsplt.d32 = dwc_read_reg32(&hc_regs->hcsplt); ++ hctsiz.d32 = dwc_read_reg32(&hc_regs->hctsiz); ++ hcdma = dwc_read_reg32(&hc_regs->hcdma); ++ ++ DWC_ERROR("AHB ERROR, Channel %d\n", hc->hc_num); ++ DWC_ERROR(" hcchar 0x%08x, hcsplt 0x%08x\n", hcchar.d32, hcsplt.d32); ++ DWC_ERROR(" hctsiz 0x%08x, hcdma 0x%08x\n", hctsiz.d32, hcdma); ++ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD URB Enqueue\n"); ++ DWC_ERROR(" Device address: %d\n", ++ dwc_otg_hcd_get_dev_addr(&urb->pipe_info)); ++ DWC_ERROR(" Endpoint: %d, %s\n", ++ dwc_otg_hcd_get_ep_num(&urb->pipe_info), ++ (dwc_otg_hcd_is_pipe_in(&urb->pipe_info) ? "IN" : "OUT")); ++ ++ ++ switch (dwc_otg_hcd_get_pipe_type(&urb->pipe_info)) { ++case UE_CONTROL: ++ pipetype = "CONTROL"; ++ break; ++ case UE_BULK: ++ pipetype = "BULK"; ++ break; ++ case UE_INTERRUPT: ++ pipetype = "INTERRUPT"; ++ break; ++ case UE_ISOCHRONOUS: ++ pipetype = "ISOCHRONOUS"; ++ break; ++ default: ++ pipetype = "UNKNOWN"; ++ break; ++ } ++ ++ DWC_ERROR(" Endpoint type: %s\n", pipetype); ++ ++ switch (hc->speed) { ++ case DWC_OTG_EP_SPEED_HIGH: ++ speed = "HIGH"; ++ break; ++ case DWC_OTG_EP_SPEED_FULL: ++ speed = "FULL"; ++ break; ++ case DWC_OTG_EP_SPEED_LOW: ++ speed = "LOW"; ++ break; ++ default: ++ speed = "UNKNOWN"; ++ break; ++ }; ++ ++ DWC_ERROR(" Speed: %s\n", speed); ++ ++ DWC_ERROR(" Max packet size: %d\n", ++ dwc_otg_hcd_get_mps(&urb->pipe_info)); ++ DWC_ERROR(" Data buffer length: %d\n", urb->length); ++ DWC_ERROR(" Transfer buffer: %p, Transfer DMA: %p\n", ++ urb->buf, (void *)urb->dma); ++ DWC_ERROR(" Setup buffer: %p, Setup DMA: %p\n", ++ urb->setup_packet, (void *)urb->setup_dma); ++ DWC_ERROR(" Interval: %d\n", urb->interval); ++ ++ /* Core haltes the channel for Descriptor DMA mode */ ++ if (hcd->core_if->dma_desc_enable) { ++ dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs, DWC_OTG_HC_XFER_AHB_ERR); ++ goto handle_ahberr_done; ++ } ++ ++ hcd->fops->complete(hcd, urb->priv, urb, -DWC_E_IO); ++ ++ /* ++ * Force a channel halt. Don't call halt_channel because that won't ++ * write to the HCCHARn register in DMA mode to force the halt. ++ */ ++ dwc_otg_hc_halt(hcd->core_if, hc, DWC_OTG_HC_XFER_AHB_ERR); ++handle_ahberr_done: ++ disable_hc_int(hc_regs, ahberr); ++ return 1; ++} ++ ++/** ++ * Handles a host channel transaction error interrupt. This handler may be ++ * called in either DMA mode or Slave mode. ++ */ ++static int32_t handle_hc_xacterr_intr(dwc_otg_hcd_t * hcd, ++ dwc_hc_t * hc, ++ dwc_otg_hc_regs_t * hc_regs, ++ dwc_otg_qtd_t * qtd) ++{ ++ DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: " ++ "Transaction Error--\n", hc->hc_num); ++ ++ if (hcd->core_if->dma_desc_enable) { ++ dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs, DWC_OTG_HC_XFER_XACT_ERR); ++ goto handle_xacterr_done; ++ } ++ ++ switch (dwc_otg_hcd_get_pipe_type(&qtd->urb->pipe_info)) { ++ case UE_CONTROL: ++ case UE_BULK: ++ qtd->error_count++; ++ if (!hc->qh->ping_state) { ++ ++ update_urb_state_xfer_intr(hc, hc_regs, ++ qtd->urb, qtd, ++ DWC_OTG_HC_XFER_XACT_ERR); ++ dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd); ++ if (!hc->ep_is_in && hc->speed == DWC_OTG_EP_SPEED_HIGH) { ++ hc->qh->ping_state = 1; ++ } ++ } ++ ++ /* ++ * Halt the channel so the transfer can be re-started from ++ * the appropriate point or the PING protocol will start. ++ */ ++ halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_XACT_ERR); ++ break; ++ case UE_INTERRUPT: ++ qtd->error_count++; ++ if (hc->do_split && hc->complete_split) { ++ qtd->complete_split = 0; ++ } ++ halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_XACT_ERR); ++ break; ++ case UE_ISOCHRONOUS: ++ { ++ dwc_otg_halt_status_e halt_status; ++ halt_status = ++ update_isoc_urb_state(hcd, hc, hc_regs, qtd, ++ DWC_OTG_HC_XFER_XACT_ERR); ++ ++ halt_channel(hcd, hc, qtd, halt_status); ++ } ++ break; ++ } ++handle_xacterr_done: ++ disable_hc_int(hc_regs, xacterr); ++ ++ return 1; ++} ++ ++/** ++ * Handles a host channel frame overrun interrupt. This handler may be called ++ * in either DMA mode or Slave mode. ++ */ ++static int32_t handle_hc_frmovrun_intr(dwc_otg_hcd_t * hcd, ++ dwc_hc_t * hc, ++ dwc_otg_hc_regs_t * hc_regs, ++ dwc_otg_qtd_t * qtd) ++{ ++ DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: " ++ "Frame Overrun--\n", hc->hc_num); ++ ++ switch (dwc_otg_hcd_get_pipe_type(&qtd->urb->pipe_info)) { ++ case UE_CONTROL: ++ case UE_BULK: ++ break; ++ case UE_INTERRUPT: ++ halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_FRAME_OVERRUN); ++ break; ++ case UE_ISOCHRONOUS: ++ { ++ dwc_otg_halt_status_e halt_status; ++ halt_status = ++ update_isoc_urb_state(hcd, hc, hc_regs, qtd, ++ DWC_OTG_HC_XFER_FRAME_OVERRUN); ++ ++ halt_channel(hcd, hc, qtd, halt_status); ++ } ++ break; ++ } ++ ++ disable_hc_int(hc_regs, frmovrun); ++ ++ return 1; ++} ++ ++/** ++ * Handles a host channel data toggle error interrupt. This handler may be ++ * called in either DMA mode or Slave mode. ++ */ ++static int32_t handle_hc_datatglerr_intr(dwc_otg_hcd_t * hcd, ++ dwc_hc_t * hc, ++ dwc_otg_hc_regs_t * hc_regs, ++ dwc_otg_qtd_t * qtd) ++{ ++ DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: " ++ "Data Toggle Error--\n", hc->hc_num); ++ ++ if (hc->ep_is_in) { ++ qtd->error_count = 0; ++ } else { ++ DWC_ERROR("Data Toggle Error on OUT transfer," ++ "channel %d\n", hc->hc_num); ++ } ++ ++ disable_hc_int(hc_regs, datatglerr); ++ ++ return 1; ++} ++ ++#ifdef DEBUG ++/** ++ * This function is for debug only. It checks that a valid halt status is set ++ * and that HCCHARn.chdis is clear. If there's a problem, corrective action is ++ * taken and a warning is issued. ++ * @return 1 if halt status is ok, 0 otherwise. ++ */ ++static inline int halt_status_ok(dwc_otg_hcd_t * hcd, ++ dwc_hc_t * hc, ++ dwc_otg_hc_regs_t * hc_regs, ++ dwc_otg_qtd_t * qtd) ++{ ++ hcchar_data_t hcchar; ++ hctsiz_data_t hctsiz; ++ hcint_data_t hcint; ++ hcintmsk_data_t hcintmsk; ++ hcsplt_data_t hcsplt; ++ ++ if (hc->halt_status == DWC_OTG_HC_XFER_NO_HALT_STATUS) { ++ /* ++ * This code is here only as a check. This condition should ++ * never happen. Ignore the halt if it does occur. ++ */ ++ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); ++ hctsiz.d32 = dwc_read_reg32(&hc_regs->hctsiz); ++ hcint.d32 = dwc_read_reg32(&hc_regs->hcint); ++ hcintmsk.d32 = dwc_read_reg32(&hc_regs->hcintmsk); ++ hcsplt.d32 = dwc_read_reg32(&hc_regs->hcsplt); ++ DWC_WARN ++ ("%s: hc->halt_status == DWC_OTG_HC_XFER_NO_HALT_STATUS, " ++ "channel %d, hcchar 0x%08x, hctsiz 0x%08x, " ++ "hcint 0x%08x, hcintmsk 0x%08x, " ++ "hcsplt 0x%08x, qtd->complete_split %d\n", __func__, ++ hc->hc_num, hcchar.d32, hctsiz.d32, hcint.d32, ++ hcintmsk.d32, hcsplt.d32, qtd->complete_split); ++ ++ DWC_WARN("%s: no halt status, channel %d, ignoring interrupt\n", ++ __func__, hc->hc_num); ++ DWC_WARN("\n"); ++ clear_hc_int(hc_regs, chhltd); ++ return 0; ++ } ++ ++ /* ++ * This code is here only as a check. hcchar.chdis should ++ * never be set when the halt interrupt occurs. Halt the ++ * channel again if it does occur. ++ */ ++ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); ++ if (hcchar.b.chdis) { ++ DWC_WARN("%s: hcchar.chdis set unexpectedly, " ++ "hcchar 0x%08x, trying to halt again\n", ++ __func__, hcchar.d32); ++ clear_hc_int(hc_regs, chhltd); ++ hc->halt_pending = 0; ++ halt_channel(hcd, hc, qtd, hc->halt_status); ++ return 0; ++ } ++ ++ return 1; ++} ++#endif ++ ++/** ++ * Handles a host Channel Halted interrupt in DMA mode. This handler ++ * determines the reason the channel halted and proceeds accordingly. ++ */ ++static void handle_hc_chhltd_intr_dma(dwc_otg_hcd_t * hcd, ++ dwc_hc_t * hc, ++ dwc_otg_hc_regs_t * hc_regs, ++ dwc_otg_qtd_t * qtd) ++{ ++ hcint_data_t hcint; ++ hcintmsk_data_t hcintmsk; ++ int out_nak_enh = 0; ++ ++ /* For core with OUT NAK enhancement, the flow for high- ++ * speed CONTROL/BULK OUT is handled a little differently. ++ */ ++ if (hcd->core_if->snpsid >= OTG_CORE_REV_2_71a) { ++ if (hc->speed == DWC_OTG_EP_SPEED_HIGH && !hc->ep_is_in && ++ (hc->ep_type == DWC_OTG_EP_TYPE_CONTROL || ++ hc->ep_type == DWC_OTG_EP_TYPE_BULK)) { ++ out_nak_enh = 1; ++ } ++ } ++ ++ if (hc->halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE || ++ (hc->halt_status == DWC_OTG_HC_XFER_AHB_ERR && !hcd->core_if->dma_desc_enable)) { ++ /* ++ * Just release the channel. A dequeue can happen on a ++ * transfer timeout. In the case of an AHB Error, the channel ++ * was forced to halt because there's no way to gracefully ++ * recover. ++ */ ++ if (hcd->core_if->dma_desc_enable) ++ dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs, hc->halt_status); ++ else ++ release_channel(hcd, hc, qtd, hc->halt_status); ++ return; ++ } ++ ++ /* Read the HCINTn register to determine the cause for the halt. */ ++ hcint.d32 = dwc_read_reg32(&hc_regs->hcint); ++ hcintmsk.d32 = dwc_read_reg32(&hc_regs->hcintmsk); ++ ++ if (hcint.b.xfercomp) { ++ /** @todo This is here because of a possible hardware bug. Spec ++ * says that on SPLIT-ISOC OUT transfers in DMA mode that a HALT ++ * interrupt w/ACK bit set should occur, but I only see the ++ * XFERCOMP bit, even with it masked out. This is a workaround ++ * for that behavior. Should fix this when hardware is fixed. ++ */ ++ if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC && !hc->ep_is_in) { ++ handle_hc_ack_intr(hcd, hc, hc_regs, qtd); ++ } ++ handle_hc_xfercomp_intr(hcd, hc, hc_regs, qtd); ++ } else if (hcint.b.stall) { ++ handle_hc_stall_intr(hcd, hc, hc_regs, qtd); ++ } else if (hcint.b.xacterr && !hcd->core_if->dma_desc_enable) { ++ if (out_nak_enh) { ++ if (hcint.b.nyet || hcint.b.nak || hcint.b.ack) { ++ DWC_DEBUG("XactErr with NYET/NAK/ACK\n"); ++ qtd->error_count = 0; ++ } else { ++ DWC_DEBUG("XactErr without NYET/NAK/ACK\n"); ++ } ++ } ++ ++ /* ++ * Must handle xacterr before nak or ack. Could get a xacterr ++ * at the same time as either of these on a BULK/CONTROL OUT ++ * that started with a PING. The xacterr takes precedence. ++ */ ++ handle_hc_xacterr_intr(hcd, hc, hc_regs, qtd); ++ } else if (hcint.b.xcs_xact && hcd->core_if->dma_desc_enable) { ++ handle_hc_xacterr_intr(hcd, hc, hc_regs, qtd); ++ } else if (hcint.b.ahberr && hcd->core_if->dma_desc_enable) { ++ handle_hc_ahberr_intr(hcd, hc, hc_regs, qtd); ++ } else if (hcint.b.bblerr) { ++ handle_hc_babble_intr(hcd, hc, hc_regs, qtd); ++ } else if (hcint.b.frmovrun) { ++ handle_hc_frmovrun_intr(hcd, hc, hc_regs, qtd); ++ } else if (!out_nak_enh) { ++ if (hcint.b.nyet) { ++ /* ++ * Must handle nyet before nak or ack. Could get a nyet at the ++ * same time as either of those on a BULK/CONTROL OUT that ++ * started with a PING. The nyet takes precedence. ++ */ ++ handle_hc_nyet_intr(hcd, hc, hc_regs, qtd); ++ } else if (hcint.b.nak && !hcintmsk.b.nak) { ++ /* ++ * If nak is not masked, it's because a non-split IN transfer ++ * is in an error state. In that case, the nak is handled by ++ * the nak interrupt handler, not here. Handle nak here for ++ * BULK/CONTROL OUT transfers, which halt on a NAK to allow ++ * rewinding the buffer pointer. ++ */ ++ handle_hc_nak_intr(hcd, hc, hc_regs, qtd); ++ } else if (hcint.b.ack && !hcintmsk.b.ack) { ++ /* ++ * If ack is not masked, it's because a non-split IN transfer ++ * is in an error state. In that case, the ack is handled by ++ * the ack interrupt handler, not here. Handle ack here for ++ * split transfers. Start splits halt on ACK. ++ */ ++ handle_hc_ack_intr(hcd, hc, hc_regs, qtd); ++ } else { ++ if (hc->ep_type == DWC_OTG_EP_TYPE_INTR || ++ hc->ep_type == DWC_OTG_EP_TYPE_ISOC) { ++ /* ++ * A periodic transfer halted with no other channel ++ * interrupts set. Assume it was halted by the core ++ * because it could not be completed in its scheduled ++ * (micro)frame. ++ */ ++#ifdef DEBUG ++ DWC_PRINTF ++ ("%s: Halt channel %d (assume incomplete periodic transfer)\n", ++ __func__, hc->hc_num); ++#endif ++ halt_channel(hcd, hc, qtd, ++ DWC_OTG_HC_XFER_PERIODIC_INCOMPLETE); ++ } else { ++ DWC_ERROR ++ ("%s: Channel %d, DMA Mode -- ChHltd set, but reason " ++ "for halting is unknown, hcint 0x%08x, intsts 0x%08x\n", ++ __func__, hc->hc_num, hcint.d32, ++ dwc_read_reg32(&hcd->core_if-> ++ core_global_regs->gintsts)); ++ } ++ ++ } ++ } else { ++ DWC_PRINTF("NYET/NAK/ACK/other in non-error case, 0x%08x\n", ++ hcint.d32); ++ } ++} ++ ++/** ++ * Handles a host channel Channel Halted interrupt. ++ * ++ * In slave mode, this handler is called only when the driver specifically ++ * requests a halt. This occurs during handling other host channel interrupts ++ * (e.g. nak, xacterr, stall, nyet, etc.). ++ * ++ * In DMA mode, this is the interrupt that occurs when the core has finished ++ * processing a transfer on a channel. Other host channel interrupts (except ++ * ahberr) are disabled in DMA mode. ++ */ ++static int32_t handle_hc_chhltd_intr(dwc_otg_hcd_t * hcd, ++ dwc_hc_t * hc, ++ dwc_otg_hc_regs_t * hc_regs, ++ dwc_otg_qtd_t * qtd) ++{ ++ DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: " ++ "Channel Halted--\n", hc->hc_num); ++ ++ if (hcd->core_if->dma_enable) { ++ handle_hc_chhltd_intr_dma(hcd, hc, hc_regs, qtd); ++ } else { ++#ifdef DEBUG ++ if (!halt_status_ok(hcd, hc, hc_regs, qtd)) { ++ return 1; ++ } ++#endif ++ release_channel(hcd, hc, qtd, hc->halt_status); ++ } ++ ++ return 1; ++} ++ ++/** Handles interrupt for a specific Host Channel */ ++int32_t dwc_otg_hcd_handle_hc_n_intr(dwc_otg_hcd_t * dwc_otg_hcd, uint32_t num) ++{ ++ int retval = 0; ++ hcint_data_t hcint; ++ hcintmsk_data_t hcintmsk; ++ dwc_hc_t *hc; ++ dwc_otg_hc_regs_t *hc_regs; ++ dwc_otg_qtd_t *qtd; ++ ++ DWC_DEBUGPL(DBG_HCDV, "--Host Channel Interrupt--, Channel %d\n", num); ++ ++ hc = dwc_otg_hcd->hc_ptr_array[num]; ++ hc_regs = dwc_otg_hcd->core_if->host_if->hc_regs[num]; ++ qtd = DWC_CIRCLEQ_FIRST(&hc->qh->qtd_list); ++ ++ hcint.d32 = dwc_read_reg32(&hc_regs->hcint); ++ hcintmsk.d32 = dwc_read_reg32(&hc_regs->hcintmsk); ++ DWC_DEBUGPL(DBG_HCDV, ++ " hcint 0x%08x, hcintmsk 0x%08x, hcint&hcintmsk 0x%08x\n", ++ hcint.d32, hcintmsk.d32, (hcint.d32 & hcintmsk.d32)); ++ hcint.d32 = hcint.d32 & hcintmsk.d32; ++ ++ if (!dwc_otg_hcd->core_if->dma_enable) { ++ if (hcint.b.chhltd && hcint.d32 != 0x2) { ++ hcint.b.chhltd = 0; ++ } ++ } ++ ++ if (hcint.b.xfercomp) { ++ retval |= ++ handle_hc_xfercomp_intr(dwc_otg_hcd, hc, hc_regs, qtd); ++ /* ++ * If NYET occurred at same time as Xfer Complete, the NYET is ++ * handled by the Xfer Complete interrupt handler. Don't want ++ * to call the NYET interrupt handler in this case. ++ */ ++ hcint.b.nyet = 0; ++ } ++ if (hcint.b.chhltd) { ++ retval |= handle_hc_chhltd_intr(dwc_otg_hcd, hc, hc_regs, qtd); ++ } ++ if (hcint.b.ahberr) { ++ retval |= handle_hc_ahberr_intr(dwc_otg_hcd, hc, hc_regs, qtd); ++ } ++ if (hcint.b.stall) { ++ retval |= handle_hc_stall_intr(dwc_otg_hcd, hc, hc_regs, qtd); ++ } ++ if (hcint.b.nak) { ++ retval |= handle_hc_nak_intr(dwc_otg_hcd, hc, hc_regs, qtd); ++ } ++ if (hcint.b.ack) { ++ retval |= handle_hc_ack_intr(dwc_otg_hcd, hc, hc_regs, qtd); ++ } ++ if (hcint.b.nyet) { ++ retval |= handle_hc_nyet_intr(dwc_otg_hcd, hc, hc_regs, qtd); ++ } ++ if (hcint.b.xacterr) { ++ retval |= handle_hc_xacterr_intr(dwc_otg_hcd, hc, hc_regs, qtd); ++ } ++ if (hcint.b.bblerr) { ++ retval |= handle_hc_babble_intr(dwc_otg_hcd, hc, hc_regs, qtd); ++ } ++ if (hcint.b.frmovrun) { ++ retval |= ++ handle_hc_frmovrun_intr(dwc_otg_hcd, hc, hc_regs, qtd); ++ } ++ if (hcint.b.datatglerr) { ++ retval |= ++ handle_hc_datatglerr_intr(dwc_otg_hcd, hc, hc_regs, qtd); ++ } ++ ++ return retval; ++} ++ ++#endif /* DWC_DEVICE_ONLY */ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c 2013-07-26 19:31:23.000000000 +0000 +@@ -0,0 +1,840 @@ ++/* ========================================================================== ++ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd_linux.c $ ++ * $Revision: #11 $ ++ * $Date: 2009/04/21 $ ++ * $Change: 1237476 $ ++ * ++ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, ++ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless ++ * otherwise expressly agreed to in writing between Synopsys and you. ++ * ++ * The Software IS NOT an item of Licensed Software or Licensed Product under ++ * any End User Software License Agreement or Agreement for Licensed Product ++ * with Synopsys or any supplement thereto. You are permitted to use and ++ * redistribute this Software in source and binary forms, with or without ++ * modification, provided that redistributions of source code must retain this ++ * notice. You may not view, use, disclose, copy or distribute this file or ++ * any information contained herein except pursuant to this license grant from ++ * Synopsys. If you do not agree with this notice, including the disclaimer ++ * below, then you are not authorized to use the Software. ++ * ++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, ++ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR ++ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER ++ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY ++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH ++ * DAMAGE. ++ * ========================================================================== */ ++#ifndef DWC_DEVICE_ONLY ++ ++/** ++ * @file ++ * ++ * This file contains the implementation of the HCD. In Linux, the HCD ++ * implements the hc_driver API. ++ */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#ifdef LM_INTERFACE ++//#include ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30)) ++#include ++#include ++#else ++#include ++#include ++#endif ++#elif defined(PLATFORM_INTERFACE) ++#include ++#endif ++ ++#include ++#include ++ ++#include "dwc_otg_hcd_if.h" ++#include "dwc_otg_dbg.h" ++#include "dwc_otg_driver.h" ++ ++/** ++ * Gets the endpoint number from a _bEndpointAddress argument. The endpoint is ++ * qualified with its direction (possible 32 endpoints per device). ++ */ ++#define dwc_ep_addr_to_endpoint(_bEndpointAddress_) ((_bEndpointAddress_ & USB_ENDPOINT_NUMBER_MASK) | \ ++ ((_bEndpointAddress_ & USB_DIR_IN) != 0) << 4) ++ ++static const char dwc_otg_hcd_name[] = "dwc_otg_hcd"; ++ ++/** @name Linux HC Driver API Functions */ ++/** @{ */ ++/* manage i/o requests, device state */ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30)) ++static int urb_enqueue(struct usb_hcd *hcd, ++ struct usb_host_endpoint *ep, ++ struct urb *urb, gfp_t mem_flags); ++ ++static int urb_dequeue(struct usb_hcd *hcd, struct urb *urb); ++#else ++static int urb_enqueue(struct usb_hcd *hcd, ++ struct urb *urb, gfp_t mem_flags); ++ ++static int urb_dequeue(struct usb_hcd *hcd, ++ struct urb *urb, int status); ++#endif ++ ++static void endpoint_disable(struct usb_hcd *hcd, struct usb_host_endpoint *ep); ++ ++static irqreturn_t dwc_otg_hcd_irq(struct usb_hcd *hcd); ++extern int hcd_start(struct usb_hcd *hcd); ++extern void hcd_stop(struct usb_hcd *hcd); ++static int get_frame_number(struct usb_hcd *hcd); ++extern int hub_status_data(struct usb_hcd *hcd, char *buf); ++extern int hub_control(struct usb_hcd *hcd, ++ u16 typeReq, ++ u16 wValue, u16 wIndex, char *buf, u16 wLength); ++ ++struct wrapper_priv_data { ++ dwc_otg_hcd_t *dwc_otg_hcd; ++}; ++ ++/** @} */ ++ ++static struct hc_driver dwc_otg_hc_driver = { ++ ++ .description = dwc_otg_hcd_name, ++ .product_desc = "DWC OTG Controller", ++ .hcd_priv_size = sizeof(struct wrapper_priv_data), ++ ++ .irq = dwc_otg_hcd_irq, ++ ++ .flags = HCD_MEMORY | HCD_USB2, ++ ++ //.reset = ++ .start = hcd_start, ++ //.suspend = ++ //.resume = ++ .stop = hcd_stop, ++ ++ .urb_enqueue = urb_enqueue, ++ .urb_dequeue = urb_dequeue, ++ .endpoint_disable = endpoint_disable, ++ ++ .get_frame_number = get_frame_number, ++ ++ .hub_status_data = hub_status_data, ++ .hub_control = hub_control, ++ //.bus_suspend = ++ //.bus_resume = ++}; ++ ++/** Gets the dwc_otg_hcd from a struct usb_hcd */ ++static inline dwc_otg_hcd_t *hcd_to_dwc_otg_hcd(struct usb_hcd *hcd) ++{ ++ struct wrapper_priv_data *p; ++ p = (struct wrapper_priv_data *)(hcd->hcd_priv); ++ return p->dwc_otg_hcd; ++} ++ ++/** Gets the struct usb_hcd that contains a dwc_otg_hcd_t. */ ++static inline struct usb_hcd *dwc_otg_hcd_to_hcd(dwc_otg_hcd_t * dwc_otg_hcd) ++{ ++ return dwc_otg_hcd_get_priv_data(dwc_otg_hcd); ++} ++ ++/** Gets the usb_host_endpoint associated with an URB. */ ++inline struct usb_host_endpoint *dwc_urb_to_endpoint(struct urb *urb) ++{ ++ struct usb_device *dev = urb->dev; ++ int ep_num = usb_pipeendpoint(urb->pipe); ++ ++ if (usb_pipein(urb->pipe)) ++ return dev->ep_in[ep_num]; ++ else ++ return dev->ep_out[ep_num]; ++} ++ ++static int _disconnect(dwc_otg_hcd_t * hcd) ++{ ++ struct usb_hcd *usb_hcd = dwc_otg_hcd_to_hcd(hcd); ++ ++ usb_hcd->self.is_b_host = 0; ++ return 0; ++} ++ ++static int _start(dwc_otg_hcd_t * hcd) ++{ ++ struct usb_hcd *usb_hcd = dwc_otg_hcd_to_hcd(hcd); ++ ++ usb_hcd->self.is_b_host = dwc_otg_hcd_is_b_host(hcd); ++ hcd_start(usb_hcd); ++ ++ return 0; ++} ++ ++static int _hub_info(dwc_otg_hcd_t * hcd, void *urb_handle, uint32_t * hub_addr, ++ uint32_t * port_addr) ++{ ++ struct urb *urb = (struct urb *)urb_handle; ++#if 1 //GRAYG - temporary ++ if (NULL == urb_handle) ++ DWC_ERROR("**** %s - NULL URB handle\n", __func__);//GRAYG ++ if (NULL == urb->dev) ++ DWC_ERROR("**** %s - URB has no device\n", __func__);//GRAYG ++ if (NULL == port_addr) ++ DWC_ERROR("**** %s - NULL port_address\n", __func__);//GRAYG ++#endif ++ if (urb->dev->tt) { ++ if (NULL == urb->dev->tt->hub) { ++ DWC_ERROR("**** %s - (URB's transactor has no TT - giving no hub)\n", ++ __func__); //GRAYG ++ //*hub_addr = (u8)usb_pipedevice(urb->pipe); //GRAYG ++ *hub_addr = 0; //GRAYG ++ // we probably shouldn't have a transaction translator if ++ // there's no associated hub? ++ } else ++ *hub_addr = urb->dev->tt->hub->devnum; ++ } else { ++ *hub_addr = 0; ++ } ++ *port_addr = urb->dev->ttport; ++ return 0; ++} ++ ++static int _speed(dwc_otg_hcd_t * hcd, void *urb_handle) ++{ ++ struct urb *urb = (struct urb *)urb_handle; ++ return urb->dev->speed; ++} ++ ++static int _get_b_hnp_enable(dwc_otg_hcd_t * hcd) ++{ ++ struct usb_hcd *usb_hcd = dwc_otg_hcd_to_hcd(hcd); ++ return usb_hcd->self.b_hnp_enable; ++} ++ ++static void allocate_bus_bandwidth(struct usb_hcd *hcd, uint32_t bw, ++ struct urb *urb) ++{ ++ hcd_to_bus(hcd)->bandwidth_allocated += bw / urb->interval; ++ if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) { ++ hcd_to_bus(hcd)->bandwidth_isoc_reqs++; ++ } else { ++ hcd_to_bus(hcd)->bandwidth_int_reqs++; ++ } ++} ++ ++static void free_bus_bandwidth(struct usb_hcd *hcd, uint32_t bw, ++ struct urb *urb) ++{ ++ hcd_to_bus(hcd)->bandwidth_allocated -= bw / urb->interval; ++ if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) { ++ hcd_to_bus(hcd)->bandwidth_isoc_reqs--; ++ } else { ++ hcd_to_bus(hcd)->bandwidth_int_reqs--; ++ } ++} ++ ++/** ++ * Sets the final status of an URB and returns it to the device driver. Any ++ * required cleanup of the URB is performed. ++ */ ++static int _complete(dwc_otg_hcd_t * hcd, void *urb_handle, ++ dwc_otg_hcd_urb_t * dwc_otg_urb, int32_t status) ++{ ++ struct urb *urb = (struct urb *)urb_handle; ++#ifdef DEBUG ++ if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) { ++ DWC_PRINTF("%s: urb %p, device %d, ep %d %s, status=%d\n", ++ __func__, urb, usb_pipedevice(urb->pipe), ++ usb_pipeendpoint(urb->pipe), ++ usb_pipein(urb->pipe) ? "IN" : "OUT", status); ++ if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) { ++ int i; ++ for (i = 0; i < urb->number_of_packets; i++) { ++ DWC_PRINTF(" ISO Desc %d status: %d\n", ++ i, urb->iso_frame_desc[i].status); ++ } ++ } ++ } ++#endif ++ ++ urb->actual_length = dwc_otg_hcd_urb_get_actual_length(dwc_otg_urb); ++ /* Convert status value. */ ++ switch (status) { ++ case -DWC_E_PROTOCOL: ++ status = -EPROTO; ++ break; ++ case -DWC_E_IN_PROGRESS: ++ status = -EINPROGRESS; ++ break; ++ case -DWC_E_PIPE: ++ status = -EPIPE; ++ break; ++ case -DWC_E_IO: ++ status = -EIO; ++ break; ++ case -DWC_E_TIMEOUT: ++ status = -ETIMEDOUT; ++ break; ++ case -DWC_E_OVERFLOW: ++ status = -EOVERFLOW; ++ break; ++ default: ++ if (status) { ++ DWC_PRINTF("Uknown urb status %d\n", status); ++ ++ } ++ } ++ ++ if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) { ++ int i; ++ ++ urb->error_count = dwc_otg_hcd_urb_get_error_count(dwc_otg_urb); ++ for (i = 0; i < urb->number_of_packets; ++i) { ++ urb->iso_frame_desc[i].actual_length = ++ dwc_otg_hcd_urb_get_iso_desc_actual_length ++ (dwc_otg_urb, i); ++ urb->iso_frame_desc[i].status = ++ dwc_otg_hcd_urb_get_iso_desc_status ++ (dwc_otg_urb, i); ++ } ++ } ++ ++ urb->status = status; ++ urb->hcpriv = NULL; ++ if (!status) { ++ if ((urb->transfer_flags & URB_SHORT_NOT_OK) && ++ (urb->actual_length < urb->transfer_buffer_length)) { ++ urb->status = -EREMOTEIO; ++ } ++ } ++ ++ if ((usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) || ++ (usb_pipetype(urb->pipe) == PIPE_INTERRUPT)) { ++ struct usb_host_endpoint *ep = dwc_urb_to_endpoint(urb); ++ if (ep) { ++ free_bus_bandwidth(dwc_otg_hcd_to_hcd(hcd), ++ dwc_otg_hcd_get_ep_bandwidth(hcd, ++ ep-> ++ hcpriv), ++ urb); ++ } ++ } ++ ++ dwc_free(dwc_otg_urb); ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30)) ++ usb_hcd_giveback_urb(dwc_otg_hcd_to_hcd(hcd), urb); ++#else ++ usb_hcd_unlink_urb_from_ep(dwc_otg_hcd_to_hcd(hcd), urb); ++ usb_hcd_giveback_urb(dwc_otg_hcd_to_hcd(hcd), urb, status); ++#endif ++ return 0; ++} ++ ++static struct dwc_otg_hcd_function_ops hcd_fops = { ++ .start = _start, ++ .disconnect = _disconnect, ++ .hub_info = _hub_info, ++ .speed = _speed, ++ .complete = _complete, ++ .get_b_hnp_enable = _get_b_hnp_enable, ++}; ++ ++/** ++ * Initializes the HCD. This function allocates memory for and initializes the ++ * static parts of the usb_hcd and dwc_otg_hcd structures. It also registers the ++ * USB bus with the core and calls the hc_driver->start() function. It returns ++ * a negative error on failure. ++ */ ++int hcd_init( ++#ifdef LM_INTERFACE ++ struct lm_device *_dev ++#elif defined(PCI_INTERFACE) ++ struct pci_dev *_dev ++#elif defined(PLATFORM_INTERFACE) ++ struct platform_device *_dev ++#endif ++ ) ++{ ++ struct usb_hcd *hcd = NULL; ++ dwc_otg_hcd_t *dwc_otg_hcd = NULL; ++#ifdef LM_INTERFACE ++ dwc_otg_device_t *otg_dev = lm_get_drvdata(_dev); ++#elif defined(PCI_INTERFACE) ++ dwc_otg_device_t *otg_dev = pci_get_drvdata(_dev); ++#elif defined(PLATFORM_INTERFACE) ++ dwc_otg_device_t *otg_dev = platform_get_drvdata(_dev); ++#endif ++ ++ int retval = 0; ++ u64 dmamask; ++ ++ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD INIT otg_dev=%p\n", otg_dev); ++ ++ /* Set device flags indicating whether the HCD supports DMA. */ ++ if (dwc_otg_is_dma_enable(otg_dev->core_if)) ++ dmamask = DMA_BIT_MASK(32); ++ else ++ dmamask = 0; ++ ++#if defined(LM_INTERFACE) || defined(PLATFORM_INTERFACE) ++ dma_set_mask(&_dev->dev, dmamask); ++ dma_set_coherent_mask(&_dev->dev, dmamask); ++#elif defined(PCI_INTERFACE) ++ pci_set_dma_mask(_dev, dmamask); ++ pci_set_consistent_dma_mask(_dev, dmamask); ++#endif ++ ++ /* ++ * Allocate memory for the base HCD plus the DWC OTG HCD. ++ * Initialize the base HCD. ++ */ ++ hcd = usb_create_hcd(&dwc_otg_hc_driver, &_dev->dev, ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30)) ++ _dev->dev.bus_id); ++#else ++ dev_name(&_dev->dev)); ++#endif ++ if (!hcd) { ++ retval = -ENOMEM; ++ goto error1; ++ } ++ ++ hcd->regs = otg_dev->base; ++ ++ /* Initialize the DWC OTG HCD. */ ++ dwc_otg_hcd = dwc_otg_hcd_alloc_hcd(); ++ if (!dwc_otg_hcd) { ++ goto error2; ++ } ++ ((struct wrapper_priv_data *)(hcd->hcd_priv))->dwc_otg_hcd = ++ dwc_otg_hcd; ++ otg_dev->hcd = dwc_otg_hcd; ++ ++ if (dwc_otg_hcd_init(dwc_otg_hcd, otg_dev->core_if)) { ++ goto error2; ++ } ++ ++ hcd->self.otg_port = dwc_otg_hcd_otg_port(dwc_otg_hcd); ++ ++ /* ++ * Finish generic HCD initialization and start the HCD. This function ++ * allocates the DMA buffer pool, registers the USB bus, requests the ++ * IRQ line, and calls hcd_start method. ++ */ ++#ifdef PLATFORM_INTERFACE ++ retval = usb_add_hcd(hcd, platform_get_irq(_dev, 0), IRQF_SHARED); ++#else ++ retval = usb_add_hcd(hcd, _dev->irq, IRQF_SHARED); ++#endif ++ if (retval < 0) { ++ goto error2; ++ } ++ ++ dwc_otg_hcd_set_priv_data(dwc_otg_hcd, hcd); ++ return 0; ++ ++ error2: ++ usb_put_hcd(hcd); ++ error1: ++ return retval; ++} ++ ++/** ++ * Removes the HCD. ++ * Frees memory and resources associated with the HCD and deregisters the bus. ++ */ ++void hcd_remove( ++#ifdef LM_INTERFACE ++ struct lm_device *_dev ++#elif defined(PCI_INTERFACE) ++ struct pci_dev *_dev ++#elif defined(PLATFORM_INTERFACE) ++ struct platform_device *_dev ++#endif ++ ) ++{ ++#ifdef LM_INTERFACE ++ dwc_otg_device_t *otg_dev = lm_get_drvdata(_dev); ++#elif defined(PCI_INTERFACE) ++ dwc_otg_device_t *otg_dev = pci_get_drvdata(_dev); ++#elif defined(PLATFORM_INTERFACE) ++ dwc_otg_device_t *otg_dev = platform_get_drvdata(_dev); ++#endif ++ ++ dwc_otg_hcd_t *dwc_otg_hcd; ++ struct usb_hcd *hcd; ++ ++ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD REMOVE otg_dev=%p\n", otg_dev); ++ ++ if (!otg_dev) { ++ DWC_DEBUGPL(DBG_ANY, "%s: otg_dev NULL!\n", __func__); ++ return; ++ } ++ ++ dwc_otg_hcd = otg_dev->hcd; ++ ++ if (!dwc_otg_hcd) { ++ DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->hcd NULL!\n", __func__); ++ return; ++ } ++ ++ hcd = dwc_otg_hcd_to_hcd(dwc_otg_hcd); ++ ++ if (!hcd) { ++ DWC_DEBUGPL(DBG_ANY, ++ "%s: dwc_otg_hcd_to_hcd(dwc_otg_hcd) NULL!\n", ++ __func__); ++ return; ++ } ++ usb_remove_hcd(hcd); ++ dwc_otg_hcd_set_priv_data(dwc_otg_hcd, NULL); ++ dwc_otg_hcd_remove(dwc_otg_hcd); ++ usb_put_hcd(hcd); ++} ++ ++/* ========================================================================= ++ * Linux HC Driver Functions ++ * ========================================================================= */ ++ ++/** Initializes the DWC_otg controller and its root hub and prepares it for host ++ * mode operation. Activates the root port. Returns 0 on success and a negative ++ * error code on failure. */ ++int hcd_start(struct usb_hcd *hcd) ++{ ++ dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd); ++ struct usb_bus *bus; ++ ++ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD START\n"); ++ bus = hcd_to_bus(hcd); ++ ++ hcd->state = HC_STATE_RUNNING; ++ if (dwc_otg_hcd_start(dwc_otg_hcd, &hcd_fops)) { ++ return 0; ++ } ++ ++ /* Initialize and connect root hub if one is not already attached */ ++ if (bus->root_hub) { ++ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Has Root Hub\n"); ++ /* Inform the HUB driver to resume. */ ++ usb_hcd_resume_root_hub(hcd); ++ } ++ ++ return 0; ++} ++ ++/** ++ * Halts the DWC_otg host mode operations in a clean manner. USB transfers are ++ * stopped. ++ */ ++void hcd_stop(struct usb_hcd *hcd) ++{ ++ dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd); ++ ++ dwc_otg_hcd_stop(dwc_otg_hcd); ++} ++ ++/** Returns the current frame number. */ ++static int get_frame_number(struct usb_hcd *hcd) ++{ ++ dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd); ++ ++ return dwc_otg_hcd_get_frame_number(dwc_otg_hcd); ++} ++ ++#ifdef DEBUG ++static void dump_urb_info(struct urb *urb, char *fn_name) ++{ ++ DWC_PRINTF("%s, urb %p\n", fn_name, urb); ++ DWC_PRINTF(" Device address: %d\n", usb_pipedevice(urb->pipe)); ++ DWC_PRINTF(" Endpoint: %d, %s\n", usb_pipeendpoint(urb->pipe), ++ (usb_pipein(urb->pipe) ? "IN" : "OUT")); ++ DWC_PRINTF(" Endpoint type: %s\n", ( { ++ char *pipetype; ++ switch (usb_pipetype(urb->pipe)) { ++case PIPE_CONTROL: ++pipetype = "CONTROL"; break; case PIPE_BULK: ++pipetype = "BULK"; break; case PIPE_INTERRUPT: ++pipetype = "INTERRUPT"; break; case PIPE_ISOCHRONOUS: ++pipetype = "ISOCHRONOUS"; break; default: ++ pipetype = "UNKNOWN"; break;}; ++ pipetype;} ++ )) ; ++ DWC_PRINTF(" Speed: %s\n", ( { ++ char *speed; switch (urb->dev->speed) { ++case USB_SPEED_HIGH: ++speed = "HIGH"; break; case USB_SPEED_FULL: ++speed = "FULL"; break; case USB_SPEED_LOW: ++speed = "LOW"; break; default: ++ speed = "UNKNOWN"; break;}; ++ speed;} ++ )) ; ++ DWC_PRINTF(" Max packet size: %d\n", ++ usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe))); ++ DWC_PRINTF(" Data buffer length: %d\n", urb->transfer_buffer_length); ++ DWC_PRINTF(" Transfer buffer: %p, Transfer DMA: %p\n", ++ urb->transfer_buffer, (void *)urb->transfer_dma); ++ DWC_PRINTF(" Setup buffer: %p, Setup DMA: %p\n", ++ urb->setup_packet, (void *)urb->setup_dma); ++ DWC_PRINTF(" Interval: %d\n", urb->interval); ++ if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) { ++ int i; ++ for (i = 0; i < urb->number_of_packets; i++) { ++ DWC_PRINTF(" ISO Desc %d:\n", i); ++ DWC_PRINTF(" offset: %d, length %d\n", ++ urb->iso_frame_desc[i].offset, ++ urb->iso_frame_desc[i].length); ++ } ++ } ++} ++ ++#endif ++ ++/** Starts processing a USB transfer request specified by a USB Request Block ++ * (URB). mem_flags indicates the type of memory allocation to use while ++ * processing this URB. */ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30)) ++static int urb_enqueue(struct usb_hcd *hcd, ++ struct usb_host_endpoint *ep, ++ struct urb *urb, gfp_t mem_flags) ++{ ++#else ++static int urb_enqueue(struct usb_hcd *hcd, ++ struct urb *urb, ++ gfp_t mem_flags) ++{ ++ struct usb_host_endpoint *ep = urb->ep; ++#endif ++ void **ref_ep_hcpriv = &ep->hcpriv; ++ int retval = 0; ++ dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd); ++ dwc_otg_hcd_urb_t *dwc_otg_urb; ++ int i; ++ int alloc_bandwidth = 0; ++ uint8_t ep_type = 0; ++ uint32_t flags = 0; ++ void *buf; ++ ++#ifdef DEBUG ++ if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) { ++ dump_urb_info(urb, "urb_enqueue"); ++ } ++#endif ++ ++ if (!urb->transfer_buffer && urb->transfer_buffer_length) ++ return -EINVAL; ++ ++ if ((usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) ++ || (usb_pipetype(urb->pipe) == PIPE_INTERRUPT)) { ++ if (!dwc_otg_hcd_is_bandwidth_allocated ++ (dwc_otg_hcd, ref_ep_hcpriv)) { ++ alloc_bandwidth = 1; ++ } ++ } ++ ++ switch (usb_pipetype(urb->pipe)) { ++ case PIPE_CONTROL: ++ ep_type = USB_ENDPOINT_XFER_CONTROL; ++ break; ++ case PIPE_ISOCHRONOUS: ++ ep_type = USB_ENDPOINT_XFER_ISOC; ++ break; ++ case PIPE_BULK: ++ ep_type = USB_ENDPOINT_XFER_BULK; ++ break; ++ case PIPE_INTERRUPT: ++ ep_type = USB_ENDPOINT_XFER_INT; ++ break; ++ default: ++ DWC_WARN("Wrong ep type\n"); ++ } ++ ++ dwc_otg_urb = dwc_otg_hcd_urb_alloc(dwc_otg_hcd, ++ urb->number_of_packets, ++ mem_flags == GFP_ATOMIC ? 1 : 0); ++ ++ urb->hcpriv = dwc_otg_urb; ++ ++ dwc_otg_hcd_urb_set_pipeinfo(dwc_otg_urb, usb_pipedevice(urb->pipe), ++ usb_pipeendpoint(urb->pipe), ep_type, ++ usb_pipein(urb->pipe), ++ usb_maxpacket(urb->dev, urb->pipe, ++ !(usb_pipein(urb->pipe)))); ++ ++ buf = urb->transfer_buffer; ++ if (hcd->self.uses_dma) { ++ /* ++ * Calculate virtual address from physical address, ++ * because some class driver may not fill transfer_buffer. ++ * In Buffer DMA mode virual address is used, ++ * when handling non DWORD aligned buffers. ++ */ ++ //buf = phys_to_virt(urb->transfer_dma); ++ // DMA addresses are bus addresses not physical addresses! ++ buf = dma_to_virt(&urb->dev->dev, urb->transfer_dma); ++ } ++ ++ if (!(urb->transfer_flags & URB_NO_INTERRUPT)) ++ flags |= URB_GIVEBACK_ASAP; ++ if (urb->transfer_flags & URB_ZERO_PACKET) ++ flags |= URB_SEND_ZERO_PACKET; ++ ++ dwc_otg_hcd_urb_set_params(dwc_otg_urb, urb, buf, ++ urb->transfer_dma, ++ urb->transfer_buffer_length, ++ urb->setup_packet, ++ urb->setup_dma, ++ flags, ++ urb->interval); ++ ++ for (i = 0; i < urb->number_of_packets; ++i) { ++ dwc_otg_hcd_urb_set_iso_desc_params(dwc_otg_urb, i, ++ urb->iso_frame_desc[i]. ++ offset, ++ urb->iso_frame_desc[i]. ++ length); ++ } ++ ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,30)) ++ retval = usb_hcd_link_urb_to_ep(hcd, urb); ++ if (0 == retval) ++#endif ++ { ++ retval = dwc_otg_hcd_urb_enqueue(dwc_otg_hcd, dwc_otg_urb, ++ /*(dwc_otg_qh_t **)*/ ++ ref_ep_hcpriv); ++ if (0 == retval) { ++ if (alloc_bandwidth) { ++ allocate_bus_bandwidth(hcd, ++ dwc_otg_hcd_get_ep_bandwidth( ++ dwc_otg_hcd, *ref_ep_hcpriv), ++ urb); ++ } ++ } else { ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,30)) ++ usb_hcd_unlink_urb_from_ep(hcd, urb); ++#endif ++ if (retval == -DWC_E_NO_DEVICE) { ++ retval = -ENODEV; ++ } ++ } ++ } ++ return retval; ++} ++ ++/** Aborts/cancels a USB transfer request. Always returns 0 to indicate ++ * success. */ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30)) ++static int urb_dequeue(struct usb_hcd *hcd, struct urb *urb) ++#else ++static int urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status) ++#endif ++{ ++ dwc_otg_hcd_t *dwc_otg_hcd; ++ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD URB Dequeue\n"); ++ ++ dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd); ++ ++#ifdef DEBUG ++ if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) { ++ dump_urb_info(urb, "urb_dequeue"); ++ } ++#endif ++ dwc_otg_hcd_urb_dequeue(dwc_otg_hcd, (dwc_otg_hcd_urb_t *)urb->hcpriv); ++ ++ dwc_free(urb->hcpriv); ++ urb->hcpriv = NULL; ++ ++ /* Higher layer software sets URB status. */ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30)) ++ usb_hcd_giveback_urb(hcd, urb); ++#else ++ usb_hcd_unlink_urb_from_ep(hcd, urb); ++ usb_hcd_giveback_urb(hcd, urb, status); ++#endif ++ if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) { ++ DWC_PRINTF("Called usb_hcd_giveback_urb()\n"); ++ DWC_PRINTF(" urb->status = %d\n", urb->status); ++ } ++ ++ return 0; ++} ++ ++/* Frees resources in the DWC_otg controller related to a given endpoint. Also ++ * clears state in the HCD related to the endpoint. Any URBs for the endpoint ++ * must already be dequeued. */ ++static void endpoint_disable(struct usb_hcd *hcd, struct usb_host_endpoint *ep) ++{ ++ dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd); ++ ++ DWC_DEBUGPL(DBG_HCD, ++ "DWC OTG HCD EP DISABLE: _bEndpointAddress=0x%02x, " ++ "endpoint=%d\n", ep->desc.bEndpointAddress, ++ dwc_ep_addr_to_endpoint(ep->desc.bEndpointAddress)); ++ dwc_otg_hcd_endpoint_disable(dwc_otg_hcd, ep->hcpriv, 250); ++ ep->hcpriv = NULL; ++} ++ ++/** Handles host mode interrupts for the DWC_otg controller. Returns IRQ_NONE if ++ * there was no interrupt to handle. Returns IRQ_HANDLED if there was a valid ++ * interrupt. ++ * ++ * This function is called by the USB core when an interrupt occurs */ ++static irqreturn_t dwc_otg_hcd_irq(struct usb_hcd *hcd) ++{ ++ dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd); ++ int32_t retval = dwc_otg_hcd_handle_intr(dwc_otg_hcd); ++ if (retval != 0) { ++ S3C2410X_CLEAR_EINTPEND(); ++ } ++ return IRQ_RETVAL(retval); ++} ++ ++/** Creates Status Change bitmap for the root hub and root port. The bitmap is ++ * returned in buf. Bit 0 is the status change indicator for the root hub. Bit 1 ++ * is the status change indicator for the single root port. Returns 1 if either ++ * change indicator is 1, otherwise returns 0. */ ++int hub_status_data(struct usb_hcd *hcd, char *buf) ++{ ++ dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd); ++ ++ buf[0] = 0; ++ buf[0] |= (dwc_otg_hcd_is_status_changed(dwc_otg_hcd, 1)) << 1; ++ ++ return (buf[0] != 0); ++} ++ ++/** Handles hub class-specific requests. */ ++int hub_control(struct usb_hcd *hcd, ++ u16 typeReq, u16 wValue, u16 wIndex, char *buf, u16 wLength) ++{ ++ int retval; ++ ++ retval = dwc_otg_hcd_hub_control(hcd_to_dwc_otg_hcd(hcd), ++ typeReq, wValue, wIndex, buf, wLength); ++ ++ switch (retval) { ++ case -DWC_E_INVALID: ++ retval = -EINVAL; ++ break; ++ } ++ ++ return retval; ++} ++ ++#endif /* DWC_DEVICE_ONLY */ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_hcd_queue.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_hcd_queue.c 2013-07-26 19:31:23.000000000 +0000 +@@ -0,0 +1,732 @@ ++/* ========================================================================== ++ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd_queue.c $ ++ * $Revision: #39 $ ++ * $Date: 2009/04/21 $ ++ * $Change: 1237477 $ ++ * ++ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, ++ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless ++ * otherwise expressly agreed to in writing between Synopsys and you. ++ * ++ * The Software IS NOT an item of Licensed Software or Licensed Product under ++ * any End User Software License Agreement or Agreement for Licensed Product ++ * with Synopsys or any supplement thereto. You are permitted to use and ++ * redistribute this Software in source and binary forms, with or without ++ * modification, provided that redistributions of source code must retain this ++ * notice. You may not view, use, disclose, copy or distribute this file or ++ * any information contained herein except pursuant to this license grant from ++ * Synopsys. If you do not agree with this notice, including the disclaimer ++ * below, then you are not authorized to use the Software. ++ * ++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, ++ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR ++ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER ++ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY ++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH ++ * DAMAGE. ++ * ========================================================================== */ ++#ifndef DWC_DEVICE_ONLY ++ ++/** ++ * @file ++ * ++ * This file contains the functions to manage Queue Heads and Queue ++ * Transfer Descriptors. ++ */ ++ ++#include "dwc_otg_hcd.h" ++#include "dwc_otg_regs.h" ++ ++/** ++ * Free each QTD in the QH's QTD-list then free the QH. QH should already be ++ * removed from a list. QTD list should already be empty if called from URB ++ * Dequeue. ++ * ++ * @param hcd HCD instance. ++ * @param qh The QH to free. ++ */ ++void dwc_otg_hcd_qh_free(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh) ++{ ++ dwc_otg_qtd_t *qtd, *qtd_tmp; ++ uint64_t flags; ++ ++ /* Free each QTD in the QTD list */ ++ DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags); ++ DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp, &qh->qtd_list, qtd_list_entry) { ++ DWC_CIRCLEQ_REMOVE(&qh->qtd_list, qtd, qtd_list_entry); ++ dwc_otg_hcd_qtd_free(qtd); ++ } ++ DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags); ++ ++ if (hcd->core_if->dma_desc_enable) { ++ dwc_otg_hcd_qh_free_ddma(hcd, qh); ++ } ++ else if (qh->dw_align_buf) { ++ uint32_t buf_size; ++ if(qh->ep_type == UE_ISOCHRONOUS) { ++ buf_size = 4096; ++ } else { ++ buf_size = hcd->core_if->core_params->max_transfer_size; ++ } ++ dwc_dma_free(buf_size, qh->dw_align_buf, qh->dw_align_buf_dma); ++ } ++ ++ ++ ++ dwc_free(qh); ++ return; ++} ++ ++#define BitStuffTime(bytecount) ((8 * 7* bytecount) / 6) ++#define HS_HOST_DELAY 5 /* nanoseconds */ ++#define FS_LS_HOST_DELAY 1000 /* nanoseconds */ ++#define HUB_LS_SETUP 333 /* nanoseconds */ ++#define NS_TO_US(ns) ((ns + 500) / 1000) ++ /* convert & round nanoseconds to microseconds */ ++ ++static uint32_t calc_bus_time(int speed, int is_in, int is_isoc, ++ int bytecount) ++{ ++ unsigned long retval; ++ ++ switch (speed) { ++ case USB_SPEED_HIGH: ++ if (is_isoc) { ++ retval = ++ ((38 * 8 * 2083) + ++ (2083 * (3 + BitStuffTime(bytecount)))) / 1000 + ++ HS_HOST_DELAY; ++ } else { ++ retval = ++ ((55 * 8 * 2083) + ++ (2083 * (3 + BitStuffTime(bytecount)))) / 1000 + ++ HS_HOST_DELAY; ++ } ++ break; ++ case USB_SPEED_FULL: ++ if (is_isoc) { ++ retval = ++ (8354 * (31 + 10 * BitStuffTime(bytecount))) / 1000; ++ if (is_in) { ++ retval = 7268 + FS_LS_HOST_DELAY + retval; ++ } else { ++ retval = 6265 + FS_LS_HOST_DELAY + retval; ++ } ++ } else { ++ retval = ++ (8354 * (31 + 10 * BitStuffTime(bytecount))) / 1000; ++ retval = 9107 + FS_LS_HOST_DELAY + retval; ++ } ++ break; ++ case USB_SPEED_LOW: ++ if (is_in) { ++ retval = ++ (67667 * (31 + 10 * BitStuffTime(bytecount))) / ++ 1000; ++ retval = ++ 64060 + (2 * HUB_LS_SETUP) + FS_LS_HOST_DELAY + ++ retval; ++ } else { ++ retval = ++ (66700 * (31 + 10 * BitStuffTime(bytecount))) / ++ 1000; ++ retval = ++ 64107 + (2 * HUB_LS_SETUP) + FS_LS_HOST_DELAY + ++ retval; ++ } ++ break; ++ default: ++ DWC_WARN("Unknown device speed\n"); ++ retval = -1; ++ } ++ ++ return NS_TO_US(retval); ++} ++ ++/** ++ * Initializes a QH structure. ++ * ++ * @param hcd The HCD state structure for the DWC OTG controller. ++ * @param qh The QH to init. ++ * @param urb Holds the information about the device/endpoint that we need ++ * to initialize the QH. ++ */ ++#define SCHEDULE_SLOP 10 ++void qh_init(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh, ++ dwc_otg_hcd_urb_t * urb) ++{ ++ char *speed, *type; ++ int dev_speed; ++ uint32_t hub_addr, hub_port; ++ ++ dwc_memset(qh, 0, sizeof(dwc_otg_qh_t)); ++ ++ /* Initialize QH */ ++ qh->ep_type = dwc_otg_hcd_get_pipe_type(&urb->pipe_info); ++ ++ qh->ep_is_in = dwc_otg_hcd_is_pipe_in(&urb->pipe_info) ? 1 : 0; ++ ++ qh->data_toggle = DWC_OTG_HC_PID_DATA0; ++ qh->maxp = dwc_otg_hcd_get_mps(&urb->pipe_info); ++ DWC_CIRCLEQ_INIT(&qh->qtd_list); ++ DWC_LIST_INIT(&qh->qh_list_entry); ++ qh->channel = NULL; ++ ++ /* FS/LS Enpoint on HS Hub ++ * NOT virtual root hub */ ++ dev_speed = hcd->fops->speed(hcd, urb->priv); ++ hcd->fops->hub_info(hcd, urb->priv, &hub_addr, &hub_port); ++ qh->do_split = 0; ++ if (((dev_speed == USB_SPEED_LOW) || ++ (dev_speed == USB_SPEED_FULL)) && ++ (hub_addr != 0 && hub_addr != 1)) { ++ ++ DWC_DEBUGPL(DBG_HCD, ++ "QH init: EP %d: TT found at hub addr %d, for port %d\n", ++ dwc_otg_hcd_get_ep_num(&urb->pipe_info), hub_addr, ++ hub_port); ++ ++ qh->do_split = 1; ++ } ++ ++ if (qh->ep_type == UE_INTERRUPT || qh->ep_type == UE_ISOCHRONOUS) { ++ /* Compute scheduling parameters once and save them. */ ++ hprt0_data_t hprt; ++ ++ /** @todo Account for split transfers in the bus time. */ ++ int bytecount = ++ dwc_hb_mult(qh->maxp) * dwc_max_packet(qh->maxp); ++ ++ qh->usecs = calc_bus_time((qh->do_split ? USB_SPEED_HIGH : dev_speed), ++ qh->ep_is_in, ++ (qh->ep_type == UE_ISOCHRONOUS), ++ bytecount); ++ /* Start in a slightly future (micro)frame. */ ++ qh->sched_frame = dwc_frame_num_inc(hcd->frame_number, ++ SCHEDULE_SLOP); ++ qh->interval = urb->interval; ++ ++#if 0 ++ /* Increase interrupt polling rate for debugging. */ ++ if (qh->ep_type == UE_INTERRUPT) { ++ qh->interval = 8; ++ } ++#endif ++ hprt.d32 = dwc_read_reg32(hcd->core_if->host_if->hprt0); ++ if ((hprt.b.prtspd == DWC_HPRT0_PRTSPD_HIGH_SPEED) && ++ ((dev_speed == USB_SPEED_LOW) || ++ (dev_speed == USB_SPEED_FULL))) { ++ qh->interval *= 8; ++ qh->sched_frame |= 0x7; ++ qh->start_split_frame = qh->sched_frame; ++ } ++ ++ } ++ ++ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD QH Initialized\n"); ++ DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - qh = %p\n", qh); ++ DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - Device Address = %d\n", ++ dwc_otg_hcd_get_dev_addr(&urb->pipe_info)); ++ DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - Endpoint %d, %s\n", ++ dwc_otg_hcd_get_ep_num(&urb->pipe_info), ++ dwc_otg_hcd_is_pipe_in(&urb->pipe_info) ? "IN" : "OUT"); ++ switch (dev_speed) { ++ case USB_SPEED_LOW: ++ qh->dev_speed = DWC_OTG_EP_SPEED_LOW; ++ speed = "low"; ++ break; ++ case USB_SPEED_FULL: ++ qh->dev_speed = DWC_OTG_EP_SPEED_FULL; ++ speed = "full"; ++ break; ++ case USB_SPEED_HIGH: ++ qh->dev_speed = DWC_OTG_EP_SPEED_HIGH; ++ speed = "high"; ++ break; ++ default: ++ speed = "?"; ++ break; ++ } ++ DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - Speed = %s\n", speed); ++ ++ switch (qh->ep_type) { ++ case UE_ISOCHRONOUS: ++ type = "isochronous"; ++ break; ++ case UE_INTERRUPT: ++ type = "interrupt"; ++ break; ++ case UE_CONTROL: ++ type = "control"; ++ break; ++ case UE_BULK: ++ type = "bulk"; ++ break; ++ default: ++ type = "?"; ++ break; ++ } ++ ++ DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - Type = %s\n", type); ++ ++#ifdef DEBUG ++ if (qh->ep_type == UE_INTERRUPT) { ++ DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - usecs = %d\n", ++ qh->usecs); ++ DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - interval = %d\n", ++ qh->interval); ++ } ++#endif ++ ++} ++ ++/** ++ * This function allocates and initializes a QH. ++ * ++ * @param hcd The HCD state structure for the DWC OTG controller. ++ * @param urb Holds the information about the device/endpoint that we need ++ * to initialize the QH. ++ * ++ * @return Returns pointer to the newly allocated QH, or NULL on error. */ ++dwc_otg_qh_t *dwc_otg_hcd_qh_create(dwc_otg_hcd_t * hcd, ++ dwc_otg_hcd_urb_t * urb) ++{ ++ dwc_otg_qh_t *qh; ++ ++ /* Allocate memory */ ++ /** @todo add memflags argument */ ++ qh = dwc_otg_hcd_qh_alloc(); ++ if (qh == NULL) { ++ return NULL; ++ } ++ ++ qh_init(hcd, qh, urb); ++ ++ if (hcd->core_if->dma_desc_enable && (dwc_otg_hcd_qh_init_ddma(hcd, qh) < 0)) { ++ dwc_otg_hcd_qh_free(hcd, qh); ++ return NULL; ++ } ++ ++ return qh; ++} ++ ++/** ++ * Checks that a channel is available for a periodic transfer. ++ * ++ * @return 0 if successful, negative error code otherise. ++ */ ++static int periodic_channel_available(dwc_otg_hcd_t * hcd) ++{ ++ /* ++ * Currently assuming that there is a dedicated host channnel for each ++ * periodic transaction plus at least one host channel for ++ * non-periodic transactions. ++ */ ++ int status; ++ int num_channels; ++ ++ num_channels = hcd->core_if->core_params->host_channels; ++ if ((hcd->periodic_channels + hcd->non_periodic_channels < num_channels) && ++ (hcd->periodic_channels < num_channels - 1)) { ++ status = 0; ++ } else { ++ DWC_INFO("%s: Total channels: %d, Periodic: %d, Non-periodic: %d\n", ++ __func__, num_channels, hcd->periodic_channels, hcd->non_periodic_channels); //NOTICE ++ status = -DWC_E_NO_SPACE; ++ } ++ ++ return status; ++} ++ ++/** ++ * Checks that there is sufficient bandwidth for the specified QH in the ++ * periodic schedule. For simplicity, this calculation assumes that all the ++ * transfers in the periodic schedule may occur in the same (micro)frame. ++ * ++ * @param hcd The HCD state structure for the DWC OTG controller. ++ * @param qh QH containing periodic bandwidth required. ++ * ++ * @return 0 if successful, negative error code otherwise. ++ */ ++static int check_periodic_bandwidth(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh) ++{ ++ int status; ++ int16_t max_claimed_usecs; ++ ++ status = 0; ++ ++ if ((qh->dev_speed == DWC_OTG_EP_SPEED_HIGH) || qh->do_split) { ++ /* ++ * High speed mode. ++ * Max periodic usecs is 80% x 125 usec = 100 usec. ++ */ ++ ++ max_claimed_usecs = 100 - qh->usecs; ++ } else { ++ /* ++ * Full speed mode. ++ * Max periodic usecs is 90% x 1000 usec = 900 usec. ++ */ ++ max_claimed_usecs = 900 - qh->usecs; ++ } ++ ++ if (hcd->periodic_usecs > max_claimed_usecs) { ++ DWC_INFO("%s: already claimed usecs %d, required usecs %d\n", __func__, hcd->periodic_usecs, qh->usecs); //NOTICE ++ status = -DWC_E_NO_SPACE; ++ } ++ ++ return status; ++} ++ ++/** ++ * Checks that the max transfer size allowed in a host channel is large enough ++ * to handle the maximum data transfer in a single (micro)frame for a periodic ++ * transfer. ++ * ++ * @param hcd The HCD state structure for the DWC OTG controller. ++ * @param qh QH for a periodic endpoint. ++ * ++ * @return 0 if successful, negative error code otherwise. ++ */ ++static int check_max_xfer_size(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh) ++{ ++ int status; ++ uint32_t max_xfer_size; ++ uint32_t max_channel_xfer_size; ++ ++ status = 0; ++ ++ max_xfer_size = dwc_max_packet(qh->maxp) * dwc_hb_mult(qh->maxp); ++ max_channel_xfer_size = hcd->core_if->core_params->max_transfer_size; ++ ++ if (max_xfer_size > max_channel_xfer_size) { ++ DWC_INFO("%s: Periodic xfer length %d > " "max xfer length for channel %d\n", ++ __func__, max_xfer_size, max_channel_xfer_size); //NOTICE ++ status = -DWC_E_NO_SPACE; ++ } ++ ++ return status; ++} ++ ++/** ++ * Schedules an interrupt or isochronous transfer in the periodic schedule. ++ * ++ * @param hcd The HCD state structure for the DWC OTG controller. ++ * @param qh QH for the periodic transfer. The QH should already contain the ++ * scheduling information. ++ * ++ * @return 0 if successful, negative error code otherwise. ++ */ ++static int schedule_periodic(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh) ++{ ++ int status = 0; ++ ++ status = periodic_channel_available(hcd); ++ if (status) { ++ DWC_INFO("%s: No host channel available for periodic " "transfer.\n", __func__); //NOTICE ++ return status; ++ } ++ ++ status = check_periodic_bandwidth(hcd, qh); ++ if (status) { ++ DWC_INFO("%s: Insufficient periodic bandwidth for " "periodic transfer.\n", __func__); //NOTICE ++ return status; ++ } ++ ++ status = check_max_xfer_size(hcd, qh); ++ if (status) { ++ DWC_INFO("%s: Channel max transfer size too small " "for periodic transfer.\n", __func__); //NOTICE ++ return status; ++ } ++ ++ if (hcd->core_if->dma_desc_enable) { ++ /* Don't rely on SOF and start in ready schedule */ ++ DWC_LIST_INSERT_TAIL(&hcd->periodic_sched_ready, &qh->qh_list_entry); ++ } ++ else { ++ /* Always start in the inactive schedule. */ ++ DWC_LIST_INSERT_TAIL(&hcd->periodic_sched_inactive, &qh->qh_list_entry); ++ } ++ ++ /* Reserve the periodic channel. */ ++ hcd->periodic_channels++; ++ ++ /* Update claimed usecs per (micro)frame. */ ++ hcd->periodic_usecs += qh->usecs; ++ ++ return status; ++} ++ ++/** ++ * This function adds a QH to either the non periodic or periodic schedule if ++ * it is not already in the schedule. If the QH is already in the schedule, no ++ * action is taken. ++ * ++ * @return 0 if successful, negative error code otherwise. ++ */ ++int dwc_otg_hcd_qh_add(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh) ++{ ++ int status = 0; ++ uint64_t flags; ++ ++ DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags); ++ ++ if (!DWC_LIST_EMPTY(&qh->qh_list_entry)) { ++ /* QH already in a schedule. */ ++ goto done; ++ } ++ ++ /* Add the new QH to the appropriate schedule */ ++ if (dwc_qh_is_non_per(qh)) { ++ /* Always start in the inactive schedule. */ ++ DWC_LIST_INSERT_TAIL(&hcd->non_periodic_sched_inactive, ++ &qh->qh_list_entry); ++ } else { ++ status = schedule_periodic(hcd, qh); ++ } ++ ++ done: ++ DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags); ++ ++ return status; ++} ++ ++/** ++ * Removes an interrupt or isochronous transfer from the periodic schedule. ++ * ++ * @param hcd The HCD state structure for the DWC OTG controller. ++ * @param qh QH for the periodic transfer. ++ */ ++static void deschedule_periodic(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh) ++{ ++ DWC_LIST_REMOVE_INIT(&qh->qh_list_entry); ++ ++ /* Release the periodic channel reservation. */ ++ hcd->periodic_channels--; ++ ++ /* Update claimed usecs per (micro)frame. */ ++ hcd->periodic_usecs -= qh->usecs; ++} ++ ++/** ++ * Removes a QH from either the non-periodic or periodic schedule. Memory is ++ * not freed. ++ * ++ * @param hcd The HCD state structure. ++ * @param qh QH to remove from schedule. */ ++void dwc_otg_hcd_qh_remove(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh) ++{ ++ uint64_t flags; ++ DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags); ++ ++ if (DWC_LIST_EMPTY(&qh->qh_list_entry)) { ++ /* QH is not in a schedule. */ ++ goto done; ++ } ++ ++ if (dwc_qh_is_non_per(qh)) { ++ if (hcd->non_periodic_qh_ptr == &qh->qh_list_entry) { ++ hcd->non_periodic_qh_ptr = ++ hcd->non_periodic_qh_ptr->next; ++ } ++ DWC_LIST_REMOVE_INIT(&qh->qh_list_entry); ++ } else { ++ deschedule_periodic(hcd, qh); ++ } ++ ++ done: ++ DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags); ++} ++ ++/** ++ * Deactivates a QH. For non-periodic QHs, removes the QH from the active ++ * non-periodic schedule. The QH is added to the inactive non-periodic ++ * schedule if any QTDs are still attached to the QH. ++ * ++ * For periodic QHs, the QH is removed from the periodic queued schedule. If ++ * there are any QTDs still attached to the QH, the QH is added to either the ++ * periodic inactive schedule or the periodic ready schedule and its next ++ * scheduled frame is calculated. The QH is placed in the ready schedule if ++ * the scheduled frame has been reached already. Otherwise it's placed in the ++ * inactive schedule. If there are no QTDs attached to the QH, the QH is ++ * completely removed from the periodic schedule. ++ */ ++void dwc_otg_hcd_qh_deactivate(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh, ++ int sched_next_periodic_split) ++{ ++ uint64_t flags; ++ DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags); ++ ++ if (dwc_qh_is_non_per(qh)) { ++ dwc_otg_hcd_qh_remove(hcd, qh); ++ if (!DWC_CIRCLEQ_EMPTY(&qh->qtd_list)) { ++ /* Add back to inactive non-periodic schedule. */ ++ dwc_otg_hcd_qh_add(hcd, qh); ++ } ++ } else { ++ uint16_t frame_number = dwc_otg_hcd_get_frame_number(hcd); ++ ++ if (qh->do_split) { ++ /* Schedule the next continuing periodic split transfer */ ++ if (sched_next_periodic_split) { ++ ++ qh->sched_frame = frame_number; ++ if (dwc_frame_num_le(frame_number, ++ dwc_frame_num_inc(qh-> ++ start_split_frame, ++ 1))) { ++ /* ++ * Allow one frame to elapse after start ++ * split microframe before scheduling ++ * complete split, but DONT if we are ++ * doing the next start split in the ++ * same frame for an ISOC out. ++ */ ++ if ((qh->ep_type != UE_ISOCHRONOUS) || ++ (qh->ep_is_in != 0)) { ++ qh->sched_frame = ++ dwc_frame_num_inc(qh->sched_frame, 1); ++ } ++ } ++ } else { ++ qh->sched_frame = ++ dwc_frame_num_inc(qh->start_split_frame, ++ qh->interval); ++ if (dwc_frame_num_le ++ (qh->sched_frame, frame_number)) { ++ qh->sched_frame = frame_number; ++ } ++ qh->sched_frame |= 0x7; ++ qh->start_split_frame = qh->sched_frame; ++ } ++ } else { ++ qh->sched_frame = ++ dwc_frame_num_inc(qh->sched_frame, qh->interval); ++ if (dwc_frame_num_le(qh->sched_frame, frame_number)) { ++ qh->sched_frame = frame_number; ++ } ++ } ++ ++ if (DWC_CIRCLEQ_EMPTY(&qh->qtd_list)) { ++ dwc_otg_hcd_qh_remove(hcd, qh); ++ } else { ++ /* ++ * Remove from periodic_sched_queued and move to ++ * appropriate queue. ++ */ ++ if (qh->sched_frame == frame_number) { ++ DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_ready, ++ &qh->qh_list_entry); ++ } else { ++ DWC_LIST_MOVE_HEAD(&hcd-> ++ periodic_sched_inactive, ++ &qh->qh_list_entry); ++ } ++ } ++ } ++ ++ DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags); ++} ++ ++/** ++ * This function allocates and initializes a QTD. ++ * ++ * @param urb The URB to create a QTD from. Each URB-QTD pair will end up ++ * pointing to each other so each pair should have a unique correlation. ++ * ++ * @return Returns pointer to the newly allocated QTD, or NULL on error. */ ++dwc_otg_qtd_t *dwc_otg_hcd_qtd_create(dwc_otg_hcd_urb_t * urb) ++{ ++ dwc_otg_qtd_t *qtd; ++ ++ qtd = dwc_otg_hcd_qtd_alloc(); ++ if (qtd == NULL) { ++ return NULL; ++ } ++ ++ dwc_otg_hcd_qtd_init(qtd, urb); ++ return qtd; ++} ++ ++/** ++ * Initializes a QTD structure. ++ * ++ * @param qtd The QTD to initialize. ++ * @param urb The URB to use for initialization. */ ++void dwc_otg_hcd_qtd_init(dwc_otg_qtd_t * qtd, dwc_otg_hcd_urb_t * urb) ++{ ++ dwc_memset(qtd, 0, sizeof(dwc_otg_qtd_t)); ++ qtd->urb = urb; ++ if (dwc_otg_hcd_get_pipe_type(&urb->pipe_info) == UE_CONTROL) { ++ /* ++ * The only time the QTD data toggle is used is on the data ++ * phase of control transfers. This phase always starts with ++ * DATA1. ++ */ ++ qtd->data_toggle = DWC_OTG_HC_PID_DATA1; ++ qtd->control_phase = DWC_OTG_CONTROL_SETUP; ++ } ++ ++ /* start split */ ++ qtd->complete_split = 0; ++ qtd->isoc_split_pos = DWC_HCSPLIT_XACTPOS_ALL; ++ qtd->isoc_split_offset = 0; ++ qtd->in_process = 0; ++ ++ /* Store the qtd ptr in the urb to reference what QTD. */ ++ urb->qtd = qtd; ++ return; ++} ++ ++/** ++ * This function adds a QTD to the QTD-list of a QH. It will find the correct ++ * QH to place the QTD into. If it does not find a QH, then it will create a ++ * new QH. If the QH to which the QTD is added is not currently scheduled, it ++ * is placed into the proper schedule based on its EP type. ++ * ++ * @param[in] qtd The QTD to add ++ * @param[in] hcd The DWC HCD structure ++ * @param[out] qh out parameter to return queue head ++ * ++ * @return 0 if successful, negative error code otherwise. ++ */ ++int dwc_otg_hcd_qtd_add(dwc_otg_qtd_t * qtd, ++ dwc_otg_hcd_t * hcd, dwc_otg_qh_t ** qh) ++{ ++ int retval = 0; ++ uint64_t flags; ++ ++ dwc_otg_hcd_urb_t *urb = qtd->urb; ++ ++ DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags); ++ ++ /* ++ * Get the QH which holds the QTD-list to insert to. Create QH if it ++ * doesn't exist. ++ */ ++ if (*qh == NULL) { ++ *qh = dwc_otg_hcd_qh_create(hcd, urb); ++ if (*qh == NULL) { ++ retval = -1; ++ goto done; ++ } ++ } ++ ++ retval = dwc_otg_hcd_qh_add(hcd, *qh); ++ if (retval == 0) { ++ DWC_CIRCLEQ_INSERT_TAIL(&((*qh)->qtd_list), qtd, ++ qtd_list_entry); ++ } ++ ++ done: ++ DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags); ++ ++ return retval; ++} ++ ++#endif /* DWC_DEVICE_ONLY */ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_pcd.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_pcd.c 2013-07-26 19:31:23.000000000 +0000 +@@ -0,0 +1,2067 @@ ++/* ========================================================================== ++ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_pcd.c $ ++ * $Revision: #79 $ ++ * $Date: 2009/04/10 $ ++ * $Change: 1230501 $ ++ * ++ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, ++ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless ++ * otherwise expressly agreed to in writing between Synopsys and you. ++ * ++ * The Software IS NOT an item of Licensed Software or Licensed Product under ++ * any End User Software License Agreement or Agreement for Licensed Product ++ * with Synopsys or any supplement thereto. You are permitted to use and ++ * redistribute this Software in source and binary forms, with or without ++ * modification, provided that redistributions of source code must retain this ++ * notice. You may not view, use, disclose, copy or distribute this file or ++ * any information contained herein except pursuant to this license grant from ++ * Synopsys. If you do not agree with this notice, including the disclaimer ++ * below, then you are not authorized to use the Software. ++ * ++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, ++ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR ++ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER ++ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY ++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH ++ * DAMAGE. ++ * ========================================================================== */ ++#ifndef DWC_HOST_ONLY ++ ++/** @file ++ * This file implements PCD Core. All code in this file is portable and don't ++ * use any OS specific functions. ++ * PCD Core provides Interface, defined in ++ * header file, which can be used to implement OS specific PCD interface. ++ * ++ * An important function of the PCD is managing interrupts generated ++ * by the DWC_otg controller. The implementation of the DWC_otg device ++ * mode interrupt service routines is in dwc_otg_pcd_intr.c. ++ * ++ * @todo Add Device Mode test modes (Test J mode, Test K mode, etc). ++ * @todo Does it work when the request size is greater than DEPTSIZ ++ * transfer size ++ * ++ */ ++ ++#include "dwc_otg_pcd.h" ++ ++#ifdef DWC_UTE_CFI ++#include "dwc_otg_cfi.h" ++ ++extern int init_cfi(cfiobject_t * cfiobj); ++#endif ++ ++static dwc_otg_pcd_ep_t *get_ep_from_handle(dwc_otg_pcd_t * pcd, void *handle) ++{ ++ int i; ++ if (pcd->ep0.priv == handle) { ++ return &pcd->ep0; ++ } ++ for (i = 0; i < MAX_EPS_CHANNELS - 1; i++) { ++ if (pcd->in_ep[i].priv == handle) ++ return &pcd->in_ep[i]; ++ if (pcd->out_ep[i].priv == handle) ++ return &pcd->out_ep[i]; ++ } ++ ++ return NULL; ++} ++ ++/** ++ * This function completes a request. It call's the request call back. ++ */ ++void dwc_otg_request_done(dwc_otg_pcd_ep_t * ep, dwc_otg_pcd_request_t * req, ++ int32_t status) ++{ ++ unsigned stopped = ep->stopped; ++ ++ DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, ep); ++ DWC_CIRCLEQ_REMOVE_INIT(&ep->queue, req, queue_entry); ++ ++ /* don't modify queue heads during completion callback */ ++ ep->stopped = 1; ++ DWC_SPINUNLOCK(ep->pcd->lock); ++ ep->pcd->fops->complete(ep->pcd, ep->priv, req->priv, status, ++ req->actual); ++ DWC_SPINLOCK(ep->pcd->lock); ++ ++ if (ep->pcd->request_pending > 0) { ++ --ep->pcd->request_pending; ++ } ++ ++ ep->stopped = stopped; ++ dwc_free(req); ++} ++ ++/** ++ * This function terminates all the requsts in the EP request queue. ++ */ ++void dwc_otg_request_nuke(dwc_otg_pcd_ep_t * ep) ++{ ++ dwc_otg_pcd_request_t *req; ++ ++ ep->stopped = 1; ++ ++ /* called with irqs blocked?? */ ++ while (!DWC_CIRCLEQ_EMPTY(&ep->queue)) { ++ req = DWC_CIRCLEQ_FIRST(&ep->queue); ++ dwc_otg_request_done(ep, req, -DWC_E_SHUTDOWN); ++ } ++} ++ ++void dwc_otg_pcd_start(dwc_otg_pcd_t * pcd, ++ const struct dwc_otg_pcd_function_ops *fops) ++{ ++ pcd->fops = fops; ++} ++ ++/** ++ * PCD Callback function for initializing the PCD when switching to ++ * device mode. ++ * ++ * @param p void pointer to the dwc_otg_pcd_t ++ */ ++static int32_t dwc_otg_pcd_start_cb(void *p) ++{ ++ dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *) p; ++ ++ /* ++ * Initialized the Core for Device mode. ++ */ ++ if (dwc_otg_is_device_mode(GET_CORE_IF(pcd))) { ++ dwc_otg_core_dev_init(GET_CORE_IF(pcd)); ++ } ++ return 1; ++} ++ ++/** CFI-specific buffer allocation function for EP */ ++#ifdef DWC_UTE_CFI ++uint8_t *cfiw_ep_alloc_buffer(dwc_otg_pcd_t * pcd, void *pep, dwc_dma_t * addr, ++ size_t buflen, int flags) ++{ ++ dwc_otg_pcd_ep_t *ep; ++ ep = get_ep_from_handle(pcd, pep); ++ return pcd->cfi->ops.ep_alloc_buf(pcd->cfi, pcd, ep, addr, buflen, ++ flags); ++} ++#else ++uint8_t *cfiw_ep_alloc_buffer(dwc_otg_pcd_t * pcd, void *pep, dwc_dma_t * addr, ++ size_t buflen, int flags); ++#endif ++ ++/** ++ * PCD Callback function for notifying the PCD when resuming from ++ * suspend. ++ * ++ * @param p void pointer to the dwc_otg_pcd_t ++ */ ++static int32_t dwc_otg_pcd_resume_cb(void *p) ++{ ++ dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *) p; ++ ++ if (pcd->fops->resume) { ++ pcd->fops->resume(pcd); ++ } ++ ++ /* Stop the SRP timeout timer. */ ++ if ((GET_CORE_IF(pcd)->core_params->phy_type != DWC_PHY_TYPE_PARAM_FS) ++ || (!GET_CORE_IF(pcd)->core_params->i2c_enable)) { ++ if (GET_CORE_IF(pcd)->srp_timer_started) { ++ GET_CORE_IF(pcd)->srp_timer_started = 0; ++ DWC_TIMER_CANCEL(pcd->srp_timer); ++ } ++ } ++ return 1; ++} ++ ++/** ++ * PCD Callback function for notifying the PCD device is suspended. ++ * ++ * @param p void pointer to the dwc_otg_pcd_t ++ */ ++static int32_t dwc_otg_pcd_suspend_cb(void *p) ++{ ++ dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *) p; ++ ++ if (pcd->fops->suspend) { ++ pcd->fops->suspend(pcd); ++ } ++ ++ return 1; ++} ++ ++/** ++ * PCD Callback function for stopping the PCD when switching to Host ++ * mode. ++ * ++ * @param p void pointer to the dwc_otg_pcd_t ++ */ ++static int32_t dwc_otg_pcd_stop_cb(void *p) ++{ ++ dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *) p; ++ extern void dwc_otg_pcd_stop(dwc_otg_pcd_t * _pcd); ++ ++ dwc_otg_pcd_stop(pcd); ++ return 1; ++} ++ ++/** ++ * PCD Callback structure for handling mode switching. ++ */ ++static dwc_otg_cil_callbacks_t pcd_callbacks = { ++ .start = dwc_otg_pcd_start_cb, ++ .stop = dwc_otg_pcd_stop_cb, ++ .suspend = dwc_otg_pcd_suspend_cb, ++ .resume_wakeup = dwc_otg_pcd_resume_cb, ++ .p = 0, /* Set at registration */ ++}; ++ ++/** ++ * This function allocates a DMA Descriptor chain for the Endpoint ++ * buffer to be used for a transfer to/from the specified endpoint. ++ */ ++dwc_otg_dev_dma_desc_t *dwc_otg_ep_alloc_desc_chain(uint32_t * dma_desc_addr, ++ uint32_t count) ++{ ++ ++ return dwc_dma_alloc(count * sizeof(dwc_otg_dev_dma_desc_t), dma_desc_addr); ++} ++ ++/** ++ * This function frees a DMA Descriptor chain that was allocated by ep_alloc_desc. ++ */ ++void dwc_otg_ep_free_desc_chain(dwc_otg_dev_dma_desc_t * desc_addr, ++ uint32_t dma_desc_addr, uint32_t count) ++{ ++ dwc_dma_free(count * sizeof(dwc_otg_dev_dma_desc_t), desc_addr, ++ dma_desc_addr); ++} ++ ++#ifdef DWC_EN_ISOC ++ ++/** ++ * This function initializes a descriptor chain for Isochronous transfer ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ * @param dwc_ep The EP to start the transfer on. ++ * ++ */ ++void dwc_otg_iso_ep_start_ddma_transfer(dwc_otg_core_if_t * core_if, ++ dwc_ep_t * dwc_ep) ++{ ++ ++ dsts_data_t dsts = {.d32 = 0 }; ++ depctl_data_t depctl = {.d32 = 0 }; ++ volatile uint32_t *addr; ++ int i, j; ++ ++ if (dwc_ep->is_in) ++ dwc_ep->desc_cnt = dwc_ep->buf_proc_intrvl / dwc_ep->bInterval; ++ else ++ dwc_ep->desc_cnt = ++ dwc_ep->buf_proc_intrvl * dwc_ep->pkt_per_frm / ++ dwc_ep->bInterval; ++ ++ /** Allocate descriptors for double buffering */ ++ dwc_ep->iso_desc_addr = ++ dwc_otg_ep_alloc_desc_chain(&dwc_ep->iso_dma_desc_addr, ++ dwc_ep->desc_cnt * 2); ++ if (dwc_ep->desc_addr) { ++ DWC_WARN("%s, can't allocate DMA descriptor chain\n", __func__); ++ return; ++ } ++ ++ dsts.d32 = dwc_read_reg32(&core_if->dev_if->dev_global_regs->dsts); ++ ++ /** ISO OUT EP */ ++ if (dwc_ep->is_in == 0) { ++ dev_dma_desc_sts_t sts = {.d32 = 0 }; ++ dwc_otg_dev_dma_desc_t *dma_desc = dwc_ep->iso_desc_addr; ++ dma_addr_t dma_ad; ++ uint32_t data_per_desc; ++ dwc_otg_dev_out_ep_regs_t *out_regs = ++ core_if->dev_if->out_ep_regs[dwc_ep->num]; ++ int offset; ++ ++ addr = &core_if->dev_if->out_ep_regs[dwc_ep->num]->doepctl; ++ dma_ad = (dma_addr_t) dwc_read_reg32(&(out_regs->doepdma)); ++ ++ /** Buffer 0 descriptors setup */ ++ dma_ad = dwc_ep->dma_addr0; ++ ++ sts.b_iso_out.bs = BS_HOST_READY; ++ sts.b_iso_out.rxsts = 0; ++ sts.b_iso_out.l = 0; ++ sts.b_iso_out.sp = 0; ++ sts.b_iso_out.ioc = 0; ++ sts.b_iso_out.pid = 0; ++ sts.b_iso_out.framenum = 0; ++ ++ offset = 0; ++ for (i = 0; i < dwc_ep->desc_cnt - dwc_ep->pkt_per_frm; ++ i += dwc_ep->pkt_per_frm) { ++ ++ for (j = 0; j < dwc_ep->pkt_per_frm; ++j) { ++ data_per_desc = ++ ((j + 1) * dwc_ep->maxpacket > ++ dwc_ep->data_per_frame) ? dwc_ep-> ++ data_per_frame - ++ j * dwc_ep->maxpacket : dwc_ep->maxpacket; ++ ++ data_per_desc += ++ (data_per_desc % 4) ? (4 - ++ data_per_desc % ++ 4) : 0; ++ sts.b_iso_out.rxbytes = data_per_desc; ++ dma_desc->buf = dma_ad; ++ dma_desc->status.d32 = sts.d32; ++ ++ offset += data_per_desc; ++ dma_desc++; ++ dma_ad += data_per_desc; ++ } ++ } ++ ++ for (j = 0; j < dwc_ep->pkt_per_frm - 1; ++j) { ++ data_per_desc = ++ ((j + 1) * dwc_ep->maxpacket > ++ dwc_ep->data_per_frame) ? dwc_ep->data_per_frame - ++ j * dwc_ep->maxpacket : dwc_ep->maxpacket; ++ data_per_desc += ++ (data_per_desc % 4) ? (4 - data_per_desc % 4) : 0; ++ sts.b_iso_out.rxbytes = data_per_desc; ++ dma_desc->buf = dma_ad; ++ dma_desc->status.d32 = sts.d32; ++ ++ offset += data_per_desc; ++ dma_desc++; ++ dma_ad += data_per_desc; ++ } ++ ++ sts.b_iso_out.ioc = 1; ++ data_per_desc = ++ ((j + 1) * dwc_ep->maxpacket > ++ dwc_ep->data_per_frame) ? dwc_ep->data_per_frame - ++ j * dwc_ep->maxpacket : dwc_ep->maxpacket; ++ data_per_desc += ++ (data_per_desc % 4) ? (4 - data_per_desc % 4) : 0; ++ sts.b_iso_out.rxbytes = data_per_desc; ++ ++ dma_desc->buf = dma_ad; ++ dma_desc->status.d32 = sts.d32; ++ dma_desc++; ++ ++ /** Buffer 1 descriptors setup */ ++ sts.b_iso_out.ioc = 0; ++ dma_ad = dwc_ep->dma_addr1; ++ ++ offset = 0; ++ for (i = 0; i < dwc_ep->desc_cnt - dwc_ep->pkt_per_frm; ++ i += dwc_ep->pkt_per_frm) { ++ for (j = 0; j < dwc_ep->pkt_per_frm; ++j) { ++ data_per_desc = ++ ((j + 1) * dwc_ep->maxpacket > ++ dwc_ep->data_per_frame) ? dwc_ep-> ++ data_per_frame - ++ j * dwc_ep->maxpacket : dwc_ep->maxpacket; ++ data_per_desc += ++ (data_per_desc % 4) ? (4 - ++ data_per_desc % ++ 4) : 0; ++ sts.b_iso_out.rxbytes = data_per_desc; ++ dma_desc->buf = dma_ad; ++ dma_desc->status.d32 = sts.d32; ++ ++ offset += data_per_desc; ++ dma_desc++; ++ dma_ad += data_per_desc; ++ } ++ } ++ for (j = 0; j < dwc_ep->pkt_per_frm - 1; ++j) { ++ data_per_desc = ++ ((j + 1) * dwc_ep->maxpacket > ++ dwc_ep->data_per_frame) ? dwc_ep->data_per_frame - ++ j * dwc_ep->maxpacket : dwc_ep->maxpacket; ++ data_per_desc += ++ (data_per_desc % 4) ? (4 - data_per_desc % 4) : 0; ++ sts.b_iso_out.rxbytes = data_per_desc; ++ dma_desc->buf = dma_ad; ++ dma_desc->status.d32 = sts.d32; ++ ++ offset += data_per_desc; ++ dma_desc++; ++ dma_ad += data_per_desc; ++ } ++ ++ sts.b_iso_out.ioc = 1; ++ sts.b_iso_out.l = 1; ++ data_per_desc = ++ ((j + 1) * dwc_ep->maxpacket > ++ dwc_ep->data_per_frame) ? dwc_ep->data_per_frame - ++ j * dwc_ep->maxpacket : dwc_ep->maxpacket; ++ data_per_desc += ++ (data_per_desc % 4) ? (4 - data_per_desc % 4) : 0; ++ sts.b_iso_out.rxbytes = data_per_desc; ++ ++ dma_desc->buf = dma_ad; ++ dma_desc->status.d32 = sts.d32; ++ ++ dwc_ep->next_frame = 0; ++ ++ /** Write dma_ad into DOEPDMA register */ ++ dwc_write_reg32(&(out_regs->doepdma), ++ (uint32_t) dwc_ep->iso_dma_desc_addr); ++ ++ } ++ /** ISO IN EP */ ++ else { ++ dev_dma_desc_sts_t sts = {.d32 = 0 }; ++ dwc_otg_dev_dma_desc_t *dma_desc = dwc_ep->iso_desc_addr; ++ dma_addr_t dma_ad; ++ dwc_otg_dev_in_ep_regs_t *in_regs = ++ core_if->dev_if->in_ep_regs[dwc_ep->num]; ++ unsigned int frmnumber; ++ fifosize_data_t txfifosize, rxfifosize; ++ ++ txfifosize.d32 = ++ dwc_read_reg32(&core_if->dev_if->in_ep_regs[dwc_ep->num]-> ++ dtxfsts); ++ rxfifosize.d32 = ++ dwc_read_reg32(&core_if->core_global_regs->grxfsiz); ++ ++ addr = &core_if->dev_if->in_ep_regs[dwc_ep->num]->diepctl; ++ ++ dma_ad = dwc_ep->dma_addr0; ++ ++ dsts.d32 = ++ dwc_read_reg32(&core_if->dev_if->dev_global_regs->dsts); ++ ++ sts.b_iso_in.bs = BS_HOST_READY; ++ sts.b_iso_in.txsts = 0; ++ sts.b_iso_in.sp = ++ (dwc_ep->data_per_frame % dwc_ep->maxpacket) ? 1 : 0; ++ sts.b_iso_in.ioc = 0; ++ sts.b_iso_in.pid = dwc_ep->pkt_per_frm; ++ ++ frmnumber = dwc_ep->next_frame; ++ ++ sts.b_iso_in.framenum = frmnumber; ++ sts.b_iso_in.txbytes = dwc_ep->data_per_frame; ++ sts.b_iso_in.l = 0; ++ ++ /** Buffer 0 descriptors setup */ ++ for (i = 0; i < dwc_ep->desc_cnt - 1; i++) { ++ dma_desc->buf = dma_ad; ++ dma_desc->status.d32 = sts.d32; ++ dma_desc++; ++ ++ dma_ad += dwc_ep->data_per_frame; ++ sts.b_iso_in.framenum += dwc_ep->bInterval; ++ } ++ ++ sts.b_iso_in.ioc = 1; ++ dma_desc->buf = dma_ad; ++ dma_desc->status.d32 = sts.d32; ++ ++dma_desc; ++ ++ /** Buffer 1 descriptors setup */ ++ sts.b_iso_in.ioc = 0; ++ dma_ad = dwc_ep->dma_addr1; ++ ++ for (i = 0; i < dwc_ep->desc_cnt - dwc_ep->pkt_per_frm; ++ i += dwc_ep->pkt_per_frm) { ++ dma_desc->buf = dma_ad; ++ dma_desc->status.d32 = sts.d32; ++ dma_desc++; ++ ++ dma_ad += dwc_ep->data_per_frame; ++ sts.b_iso_in.framenum += dwc_ep->bInterval; ++ ++ sts.b_iso_in.ioc = 0; ++ } ++ sts.b_iso_in.ioc = 1; ++ sts.b_iso_in.l = 1; ++ ++ dma_desc->buf = dma_ad; ++ dma_desc->status.d32 = sts.d32; ++ ++ dwc_ep->next_frame = sts.b_iso_in.framenum + dwc_ep->bInterval; ++ ++ /** Write dma_ad into diepdma register */ ++ dwc_write_reg32(&(in_regs->diepdma), ++ (uint32_t) dwc_ep->iso_dma_desc_addr); ++ } ++ /** Enable endpoint, clear nak */ ++ depctl.d32 = 0; ++ depctl.b.epena = 1; ++ depctl.b.usbactep = 1; ++ depctl.b.cnak = 1; ++ ++ dwc_modify_reg32(addr, depctl.d32, depctl.d32); ++ depctl.d32 = dwc_read_reg32(addr); ++} ++ ++/** ++ * This function initializes a descriptor chain for Isochronous transfer ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ * @param ep The EP to start the transfer on. ++ * ++ */ ++ ++void dwc_otg_iso_ep_start_buf_transfer(dwc_otg_core_if_t * core_if, ++ dwc_ep_t * ep) ++{ ++ depctl_data_t depctl = {.d32 = 0 }; ++ volatile uint32_t *addr; ++ ++ if (ep->is_in) { ++ addr = &core_if->dev_if->in_ep_regs[ep->num]->diepctl; ++ } else { ++ addr = &core_if->dev_if->out_ep_regs[ep->num]->doepctl; ++ } ++ ++ if (core_if->dma_enable == 0 || core_if->dma_desc_enable != 0) { ++ return; ++ } else { ++ deptsiz_data_t deptsiz = {.d32 = 0 }; ++ ++ ep->xfer_len = ++ ep->data_per_frame * ep->buf_proc_intrvl / ep->bInterval; ++ ep->pkt_cnt = ++ (ep->xfer_len - 1 + ep->maxpacket) / ep->maxpacket; ++ ep->xfer_count = 0; ++ ep->xfer_buff = ++ (ep->proc_buf_num) ? ep->xfer_buff1 : ep->xfer_buff0; ++ ep->dma_addr = ++ (ep->proc_buf_num) ? ep->dma_addr1 : ep->dma_addr0; ++ ++ if (ep->is_in) { ++ /* Program the transfer size and packet count ++ * as follows: xfersize = N * maxpacket + ++ * short_packet pktcnt = N + (short_packet ++ * exist ? 1 : 0) ++ */ ++ deptsiz.b.mc = ep->pkt_per_frm; ++ deptsiz.b.xfersize = ep->xfer_len; ++ deptsiz.b.pktcnt = ++ (ep->xfer_len - 1 + ep->maxpacket) / ep->maxpacket; ++ dwc_write_reg32(&core_if->dev_if->in_ep_regs[ep->num]-> ++ dieptsiz, deptsiz.d32); ++ ++ /* Write the DMA register */ ++ dwc_write_reg32(& ++ (core_if->dev_if->in_ep_regs[ep->num]-> ++ diepdma), (uint32_t) ep->dma_addr); ++ ++ } else { ++ deptsiz.b.pktcnt = ++ (ep->xfer_len + (ep->maxpacket - 1)) / ++ ep->maxpacket; ++ deptsiz.b.xfersize = deptsiz.b.pktcnt * ep->maxpacket; ++ ++ dwc_write_reg32(&core_if->dev_if->out_ep_regs[ep->num]-> ++ doeptsiz, deptsiz.d32); ++ ++ /* Write the DMA register */ ++ dwc_write_reg32(& ++ (core_if->dev_if->out_ep_regs[ep->num]-> ++ doepdma), (uint32_t) ep->dma_addr); ++ ++ } ++ /** Enable endpoint, clear nak */ ++ depctl.d32 = 0; ++ dwc_modify_reg32(addr, depctl.d32, depctl.d32); ++ ++ depctl.b.epena = 1; ++ depctl.b.cnak = 1; ++ ++ dwc_modify_reg32(addr, depctl.d32, depctl.d32); ++ } ++} ++ ++/** ++ * This function does the setup for a data transfer for an EP and ++ * starts the transfer. For an IN transfer, the packets will be ++ * loaded into the appropriate Tx FIFO in the ISR. For OUT transfers, ++ * the packets are unloaded from the Rx FIFO in the ISR. the ISR. ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ * @param ep The EP to start the transfer on. ++ */ ++ ++static void dwc_otg_iso_ep_start_transfer(dwc_otg_core_if_t * core_if, ++ dwc_ep_t * ep) ++{ ++ if (core_if->dma_enable) { ++ if (core_if->dma_desc_enable) { ++ if (ep->is_in) { ++ ep->desc_cnt = ep->pkt_cnt / ep->pkt_per_frm; ++ } else { ++ ep->desc_cnt = ep->pkt_cnt; ++ } ++ dwc_otg_iso_ep_start_ddma_transfer(core_if, ep); ++ } else { ++ if (core_if->pti_enh_enable) { ++ dwc_otg_iso_ep_start_buf_transfer(core_if, ep); ++ } else { ++ ep->cur_pkt_addr = ++ (ep->proc_buf_num) ? ep->xfer_buff1 : ep-> ++ xfer_buff0; ++ ep->cur_pkt_dma_addr = ++ (ep->proc_buf_num) ? ep->dma_addr1 : ep-> ++ dma_addr0; ++ dwc_otg_iso_ep_start_frm_transfer(core_if, ep); ++ } ++ } ++ } else { ++ ep->cur_pkt_addr = ++ (ep->proc_buf_num) ? ep->xfer_buff1 : ep->xfer_buff0; ++ ep->cur_pkt_dma_addr = ++ (ep->proc_buf_num) ? ep->dma_addr1 : ep->dma_addr0; ++ dwc_otg_iso_ep_start_frm_transfer(core_if, ep); ++ } ++} ++ ++/** ++ * This function does the setup for a data transfer for an EP and ++ * starts the transfer. For an IN transfer, the packets will be ++ * loaded into the appropriate Tx FIFO in the ISR. For OUT transfers, ++ * the packets are unloaded from the Rx FIFO in the ISR. the ISR. ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ * @param ep The EP to start the transfer on. ++ */ ++ ++void dwc_otg_iso_ep_stop_transfer(dwc_otg_core_if_t * core_if, dwc_ep_t * ep) ++{ ++ depctl_data_t depctl = {.d32 = 0 }; ++ volatile uint32_t *addr; ++ ++ if (ep->is_in == 1) { ++ addr = &core_if->dev_if->in_ep_regs[ep->num]->diepctl; ++ } else { ++ addr = &core_if->dev_if->out_ep_regs[ep->num]->doepctl; ++ } ++ ++ /* disable the ep */ ++ depctl.d32 = dwc_read_reg32(addr); ++ ++ depctl.b.epdis = 1; ++ depctl.b.snak = 1; ++ ++ dwc_write_reg32(addr, depctl.d32); ++ ++ if (core_if->dma_desc_enable && ++ ep->iso_desc_addr && ep->iso_dma_desc_addr) { ++ dwc_otg_ep_free_desc_chain(ep->iso_desc_addr, ++ ep->iso_dma_desc_addr, ++ ep->desc_cnt * 2); ++ } ++ ++ /* reset varibales */ ++ ep->dma_addr0 = 0; ++ ep->dma_addr1 = 0; ++ ep->xfer_buff0 = 0; ++ ep->xfer_buff1 = 0; ++ ep->data_per_frame = 0; ++ ep->data_pattern_frame = 0; ++ ep->sync_frame = 0; ++ ep->buf_proc_intrvl = 0; ++ ep->bInterval = 0; ++ ep->proc_buf_num = 0; ++ ep->pkt_per_frm = 0; ++ ep->pkt_per_frm = 0; ++ ep->desc_cnt = 0; ++ ep->iso_desc_addr = 0; ++ ep->iso_dma_desc_addr = 0; ++} ++ ++int dwc_otg_pcd_iso_ep_start(dwc_otg_pcd_t * pcd, void *ep_handle, ++ uint8_t * buf0, uint8_t * buf1, dwc_dma_t dma0, ++ dwc_dma_t dma1, int sync_frame, int dp_frame, ++ int data_per_frame, int start_frame, ++ int buf_proc_intrvl, void *req_handle, ++ int atomic_alloc) ++{ ++ dwc_otg_pcd_ep_t *ep; ++ uint64_t flags = 0; ++ dwc_ep_t *dwc_ep; ++ int32_t frm_data; ++ dsts_data_t dsts; ++ dwc_otg_core_if_t *core_if; ++ ++ ep = get_ep_from_handle(pcd, ep_handle); ++ ++ if (!ep->desc || ep->dwc_ep.num == 0) { ++ DWC_WARN("bad ep\n"); ++ return -DWC_E_INVALID; ++ } ++ ++ DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags); ++ core_if = GET_CORE_IF(pcd); ++ dwc_ep = &ep->dwc_ep; ++ ++ if (ep->iso_req_handle) { ++ DWC_WARN("ISO request in progress\n"); ++ } ++ ++ dwc_ep->dma_addr0 = dma0; ++ dwc_ep->dma_addr1 = dma1; ++ ++ dwc_ep->xfer_buff0 = buf0; ++ dwc_ep->xfer_buff1 = buf1; ++ ++ dwc_ep->data_per_frame = data_per_frame; ++ ++ /** @todo - pattern data support is to be implemented in the future */ ++ dwc_ep->data_pattern_frame = dp_frame; ++ dwc_ep->sync_frame = sync_frame; ++ ++ dwc_ep->buf_proc_intrvl = buf_proc_intrvl; ++ ++ dwc_ep->bInterval = 1 << (ep->desc->bInterval - 1); ++ ++ dwc_ep->proc_buf_num = 0; ++ ++ dwc_ep->pkt_per_frm = 0; ++ frm_data = ep->dwc_ep.data_per_frame; ++ while (frm_data > 0) { ++ dwc_ep->pkt_per_frm++; ++ frm_data -= ep->dwc_ep.maxpacket; ++ } ++ ++ dsts.d32 = dwc_read_reg32(&core_if->dev_if->dev_global_regs->dsts); ++ ++ if (start_frame == -1) { ++ dwc_ep->next_frame = dsts.b.soffn + 1; ++ if (dwc_ep->bInterval != 1) { ++ dwc_ep->next_frame = ++ dwc_ep->next_frame + (dwc_ep->bInterval - 1 - ++ dwc_ep->next_frame % ++ dwc_ep->bInterval); ++ } ++ } else { ++ dwc_ep->next_frame = start_frame; ++ } ++ ++ if (!core_if->pti_enh_enable) { ++ dwc_ep->pkt_cnt = ++ dwc_ep->buf_proc_intrvl * dwc_ep->pkt_per_frm / ++ dwc_ep->bInterval; ++ } else { ++ dwc_ep->pkt_cnt = ++ (dwc_ep->data_per_frame * ++ (dwc_ep->buf_proc_intrvl / dwc_ep->bInterval) ++ - 1 + dwc_ep->maxpacket) / dwc_ep->maxpacket; ++ } ++ ++ if (core_if->dma_desc_enable) { ++ dwc_ep->desc_cnt = ++ dwc_ep->buf_proc_intrvl * dwc_ep->pkt_per_frm / ++ dwc_ep->bInterval; ++ } ++ ++ if (atomic_alloc) { ++ dwc_ep->pkt_info = ++ dwc_alloc_atomic(sizeof(iso_pkt_info_t) * dwc_ep->pkt_cnt); ++ } else { ++ dwc_ep->pkt_info = ++ dwc_alloc(sizeof(iso_pkt_info_t) * dwc_ep->pkt_cnt); ++ } ++ if (!dwc_ep->pkt_info) { ++ DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags); ++ return -DWC_E_NO_MEMORY; ++ } ++ if (core_if->pti_enh_enable) { ++ dwc_memset(dwc_ep->pkt_info, 0, ++ sizeof(iso_pkt_info_t) * dwc_ep->pkt_cnt); ++ } ++ ++ dwc_ep->cur_pkt = 0; ++ ep->iso_req_handle = req_handle; ++ ++ DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags); ++ dwc_otg_iso_ep_start_transfer(core_if, dwc_ep); ++ return 0; ++} ++ ++int dwc_otg_pcd_iso_ep_stop(dwc_otg_pcd_t * pcd, void *ep_handle, ++ void *req_handle) ++{ ++ uint64_t flags = 0; ++ dwc_otg_pcd_ep_t *ep; ++ dwc_ep_t *dwc_ep; ++ ++ ep = get_ep_from_handle(pcd, ep_handle); ++ if (!ep || !ep->desc || ep->dwc_ep.num == 0) { ++ DWC_WARN("bad ep\n"); ++ return -DWC_E_INVALID; ++ } ++ dwc_ep = &ep->dwc_ep; ++ ++ dwc_otg_iso_ep_stop_transfer(GET_CORE_IF(pcd), dwc_ep); ++ ++ dwc_free(dwc_ep->pkt_info); ++ DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags); ++ if (ep->iso_req_handle != req_handle) { ++ DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags); ++ return -DWC_E_INVALID; ++ } ++ ++ DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags); ++ ++ ep->iso_req_handle = 0; ++ return 0; ++} ++ ++/** ++ * This function is used for perodical data exchnage between PCD and gadget drivers. ++ * for Isochronous EPs ++ * ++ * - Every time a sync period completes this function is called to ++ * perform data exchange between PCD and gadget ++ */ ++void dwc_otg_iso_buffer_done(dwc_otg_pcd_t * pcd, dwc_otg_pcd_ep_t * ep, ++ void *req_handle) ++{ ++ int i; ++ dwc_ep_t *dwc_ep; ++ ++ dwc_ep = &ep->dwc_ep; ++ ++ DWC_SPINUNLOCK(ep->pcd->lock); ++ pcd->fops->isoc_complete(pcd, ep->priv, ep->iso_req_handle, ++ dwc_ep->proc_buf_num ^ 0x1); ++ DWC_SPINLOCK(ep->pcd->lock); ++ ++ for (i = 0; i < dwc_ep->pkt_cnt; ++i) { ++ dwc_ep->pkt_info[i].status = 0; ++ dwc_ep->pkt_info[i].offset = 0; ++ dwc_ep->pkt_info[i].length = 0; ++ } ++} ++ ++int dwc_otg_pcd_get_iso_packet_count(dwc_otg_pcd_t * pcd, void *ep_handle, ++ void *iso_req_handle) ++{ ++ dwc_otg_pcd_ep_t *ep; ++ dwc_ep_t *dwc_ep; ++ ++ ep = get_ep_from_handle(pcd, ep_handle); ++ dwc_ep = &ep->dwc_ep; ++ ++ return dwc_ep->pkt_cnt; ++} ++ ++void dwc_otg_pcd_get_iso_packet_params(dwc_otg_pcd_t * pcd, void *ep_handle, ++ void *iso_req_handle, int packet, ++ int *status, int *actual, int *offset) ++{ ++ dwc_otg_pcd_ep_t *ep; ++ dwc_ep_t *dwc_ep; ++ ++ ep = get_ep_from_handle(pcd, ep_handle); ++ dwc_ep = &ep->dwc_ep; ++ ++ *status = dwc_ep->pkt_info[packet].status; ++ *actual = dwc_ep->pkt_info[packet].length; ++ *offset = dwc_ep->pkt_info[packet].offset; ++} ++ ++#endif /* DWC_EN_ISOC */ ++ ++static void dwc_otg_pcd_init_ep(dwc_otg_pcd_t * pcd, dwc_otg_pcd_ep_t * pcd_ep, ++ uint32_t is_in, uint32_t ep_num) ++{ ++ /* Init EP structure */ ++ pcd_ep->desc = 0; ++ pcd_ep->pcd = pcd; ++ pcd_ep->stopped = 1; ++ pcd_ep->queue_sof = 0; ++ ++ /* Init DWC ep structure */ ++ pcd_ep->dwc_ep.is_in = is_in; ++ pcd_ep->dwc_ep.num = ep_num; ++ pcd_ep->dwc_ep.active = 0; ++ pcd_ep->dwc_ep.tx_fifo_num = 0; ++ /* Control until ep is actvated */ ++ pcd_ep->dwc_ep.type = DWC_OTG_EP_TYPE_CONTROL; ++ pcd_ep->dwc_ep.maxpacket = MAX_PACKET_SIZE; ++ pcd_ep->dwc_ep.dma_addr = 0; ++ pcd_ep->dwc_ep.start_xfer_buff = 0; ++ pcd_ep->dwc_ep.xfer_buff = 0; ++ pcd_ep->dwc_ep.xfer_len = 0; ++ pcd_ep->dwc_ep.xfer_count = 0; ++ pcd_ep->dwc_ep.sent_zlp = 0; ++ pcd_ep->dwc_ep.total_len = 0; ++ pcd_ep->dwc_ep.desc_addr = 0; ++ pcd_ep->dwc_ep.dma_desc_addr = 0; ++ DWC_CIRCLEQ_INIT(&pcd_ep->queue); ++} ++ ++/** ++ * Initialise ep's ++ */ ++static void dwc_otg_pcd_reinit(dwc_otg_pcd_t * pcd) ++{ ++ int i; ++ uint32_t hwcfg1; ++ dwc_otg_pcd_ep_t *ep; ++ int in_ep_cntr, out_ep_cntr; ++ uint32_t num_in_eps = (GET_CORE_IF(pcd))->dev_if->num_in_eps; ++ uint32_t num_out_eps = (GET_CORE_IF(pcd))->dev_if->num_out_eps; ++ ++ /** ++ * Initialize the EP0 structure. ++ */ ++ ep = &pcd->ep0; ++ dwc_otg_pcd_init_ep(pcd, ep, 0, 0); ++ ++ in_ep_cntr = 0; ++ hwcfg1 = (GET_CORE_IF(pcd))->hwcfg1.d32 >> 3; ++ for (i = 1; in_ep_cntr < num_in_eps; i++) { ++ if ((hwcfg1 & 0x1) == 0) { ++ dwc_otg_pcd_ep_t *ep = &pcd->in_ep[in_ep_cntr]; ++ in_ep_cntr++; ++ /** ++ * @todo NGS: Add direction to EP, based on contents ++ * of HWCFG1. Need a copy of HWCFG1 in pcd structure? ++ * sprintf(";r ++ */ ++ dwc_otg_pcd_init_ep(pcd, ep, 1 /* IN */ , i); ++ ++ DWC_CIRCLEQ_INIT(&ep->queue); ++ } ++ hwcfg1 >>= 2; ++ } ++ ++ out_ep_cntr = 0; ++ hwcfg1 = (GET_CORE_IF(pcd))->hwcfg1.d32 >> 2; ++ for (i = 1; out_ep_cntr < num_out_eps; i++) { ++ if ((hwcfg1 & 0x1) == 0) { ++ dwc_otg_pcd_ep_t *ep = &pcd->out_ep[out_ep_cntr]; ++ out_ep_cntr++; ++ /** ++ * @todo NGS: Add direction to EP, based on contents ++ * of HWCFG1. Need a copy of HWCFG1 in pcd structure? ++ * sprintf(";r ++ */ ++ dwc_otg_pcd_init_ep(pcd, ep, 0 /* OUT */ , i); ++ DWC_CIRCLEQ_INIT(&ep->queue); ++ } ++ hwcfg1 >>= 2; ++ } ++ ++ pcd->ep0state = EP0_DISCONNECT; ++ pcd->ep0.dwc_ep.maxpacket = MAX_EP0_SIZE; ++ pcd->ep0.dwc_ep.type = DWC_OTG_EP_TYPE_CONTROL; ++} ++ ++/** ++ * This function is called when the SRP timer expires. The SRP should ++ * complete within 6 seconds. ++ */ ++static void srp_timeout(void *ptr) ++{ ++ gotgctl_data_t gotgctl; ++ dwc_otg_core_if_t *core_if = (dwc_otg_core_if_t *) ptr; ++ volatile uint32_t *addr = &core_if->core_global_regs->gotgctl; ++ ++ gotgctl.d32 = dwc_read_reg32(addr); ++ ++ core_if->srp_timer_started = 0; ++ ++ if ((core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS) && ++ (core_if->core_params->i2c_enable)) { ++ DWC_PRINTF("SRP Timeout\n"); ++ ++ if ((core_if->srp_success) && (gotgctl.b.bsesvld)) { ++ if (core_if->pcd_cb && core_if->pcd_cb->resume_wakeup) { ++ core_if->pcd_cb->resume_wakeup(core_if->pcd_cb-> ++ p); ++ } ++ ++ /* Clear Session Request */ ++ gotgctl.d32 = 0; ++ gotgctl.b.sesreq = 1; ++ dwc_modify_reg32(&core_if->core_global_regs->gotgctl, ++ gotgctl.d32, 0); ++ ++ core_if->srp_success = 0; ++ } else { ++ __DWC_ERROR("Device not connected/responding\n"); ++ gotgctl.b.sesreq = 0; ++ dwc_write_reg32(addr, gotgctl.d32); ++ } ++ } else if (gotgctl.b.sesreq) { ++ DWC_PRINTF("SRP Timeout\n"); ++ ++ __DWC_ERROR("Device not connected/responding\n"); ++ gotgctl.b.sesreq = 0; ++ dwc_write_reg32(addr, gotgctl.d32); ++ } else { ++ DWC_PRINTF(" SRP GOTGCTL=%0x\n", gotgctl.d32); ++ } ++} ++ ++/** ++ * Tasklet ++ * ++ */ ++extern void start_next_request(dwc_otg_pcd_ep_t * ep); ++ ++static void start_xfer_tasklet_func(void *data) ++{ ++ dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *) data; ++ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); ++ ++ int i; ++ depctl_data_t diepctl; ++ ++ DWC_DEBUGPL(DBG_PCDV, "Start xfer tasklet\n"); ++ ++ diepctl.d32 = dwc_read_reg32(&core_if->dev_if->in_ep_regs[0]->diepctl); ++ ++ if (pcd->ep0.queue_sof) { ++ pcd->ep0.queue_sof = 0; ++ start_next_request(&pcd->ep0); ++ // break; ++ } ++ ++ for (i = 0; i < core_if->dev_if->num_in_eps; i++) { ++ depctl_data_t diepctl; ++ diepctl.d32 = ++ dwc_read_reg32(&core_if->dev_if->in_ep_regs[i]->diepctl); ++ ++ if (pcd->in_ep[i].queue_sof) { ++ pcd->in_ep[i].queue_sof = 0; ++ start_next_request(&pcd->in_ep[i]); ++ // break; ++ } ++ } ++ ++ return; ++} ++ ++/** ++ * This function initialized the PCD portion of the driver. ++ * ++ */ ++dwc_otg_pcd_t *dwc_otg_pcd_init(dwc_otg_core_if_t * core_if) ++{ ++ dwc_otg_pcd_t *pcd = 0; ++ dwc_otg_dev_if_t *dev_if; ++ ++ /* ++ * Allocate PCD structure ++ */ ++ pcd = dwc_alloc(sizeof(dwc_otg_pcd_t)); ++ ++ if (pcd == 0) { ++ return NULL; ++ } ++ ++ pcd->lock = DWC_SPINLOCK_ALLOC(); ++ DWC_DEBUGPL(DBG_HCDV, "Init of PCD %p given core_if %p\n", ++ pcd, core_if);//GRAYG ++ pcd->core_if = core_if; ++ if (!pcd->lock) { ++ DWC_ERROR("Could not allocate lock for pcd"); ++ dwc_free(pcd); ++ return NULL; ++ } ++ dev_if = core_if->dev_if; ++ ++ if (core_if->hwcfg4.b.ded_fifo_en) { ++ DWC_PRINTF("Dedicated Tx FIFOs mode\n"); ++ } else { ++ DWC_PRINTF("Shared Tx FIFO mode\n"); ++ } ++ ++ /* ++ * Initialized the Core for Device mode. ++ */ ++ if (dwc_otg_is_device_mode(core_if)) { ++ dwc_otg_core_dev_init(core_if); ++ } ++ ++ /* ++ * Register the PCD Callbacks. ++ */ ++ dwc_otg_cil_register_pcd_callbacks(core_if, &pcd_callbacks, pcd); ++ ++ /* ++ * Initialize the DMA buffer for SETUP packets ++ */ ++ if (GET_CORE_IF(pcd)->dma_enable) { ++ pcd->setup_pkt = ++ dwc_dma_alloc(sizeof(*pcd->setup_pkt) * 5, ++ &pcd->setup_pkt_dma_handle); ++ if (pcd->setup_pkt == 0) { ++ dwc_free(pcd); ++ return NULL; ++ } ++ ++ pcd->status_buf = ++ dwc_dma_alloc(sizeof(uint16_t), ++ &pcd->status_buf_dma_handle); ++ if (pcd->status_buf == 0) { ++ dwc_dma_free(sizeof(*pcd->setup_pkt) * 5, ++ pcd->setup_pkt, pcd->setup_pkt_dma_handle); ++ dwc_free(pcd); ++ return NULL; ++ } ++ ++ if (GET_CORE_IF(pcd)->dma_desc_enable) { ++ dev_if->setup_desc_addr[0] = ++ dwc_otg_ep_alloc_desc_chain(&dev_if-> ++ dma_setup_desc_addr[0], ++ 1); ++ dev_if->setup_desc_addr[1] = ++ dwc_otg_ep_alloc_desc_chain(&dev_if-> ++ dma_setup_desc_addr[1], ++ 1); ++ dev_if->in_desc_addr = ++ dwc_otg_ep_alloc_desc_chain(&dev_if-> ++ dma_in_desc_addr, 1); ++ dev_if->out_desc_addr = ++ dwc_otg_ep_alloc_desc_chain(&dev_if-> ++ dma_out_desc_addr, 1); ++ ++ if (dev_if->setup_desc_addr[0] == 0 ++ || dev_if->setup_desc_addr[1] == 0 ++ || dev_if->in_desc_addr == 0 ++ || dev_if->out_desc_addr == 0) { ++ ++ if (dev_if->out_desc_addr) ++ dwc_otg_ep_free_desc_chain(dev_if-> ++ out_desc_addr, ++ dev_if-> ++ dma_out_desc_addr, ++ 1); ++ if (dev_if->in_desc_addr) ++ dwc_otg_ep_free_desc_chain(dev_if-> ++ in_desc_addr, ++ dev_if-> ++ dma_in_desc_addr, ++ 1); ++ if (dev_if->setup_desc_addr[1]) ++ dwc_otg_ep_free_desc_chain(dev_if-> ++ setup_desc_addr ++ [1], ++ dev_if-> ++ dma_setup_desc_addr ++ [1], 1); ++ if (dev_if->setup_desc_addr[0]) ++ dwc_otg_ep_free_desc_chain(dev_if-> ++ setup_desc_addr ++ [0], ++ dev_if-> ++ dma_setup_desc_addr ++ [0], 1); ++ ++ dwc_dma_free(sizeof(*pcd->setup_pkt) * 5, ++ pcd->setup_pkt, ++ pcd->setup_pkt_dma_handle); ++ dwc_dma_free(sizeof(*pcd->status_buf), ++ pcd->status_buf, ++ pcd->status_buf_dma_handle); ++ ++ dwc_free(pcd); ++ ++ return NULL; ++ } ++ } ++ } else { ++ pcd->setup_pkt = dwc_alloc(sizeof(*pcd->setup_pkt) * 5); ++ if (pcd->setup_pkt == 0) { ++ dwc_free(pcd); ++ return NULL; ++ } ++ ++ pcd->status_buf = dwc_alloc(sizeof(uint16_t)); ++ if (pcd->status_buf == 0) { ++ dwc_free(pcd->setup_pkt); ++ dwc_free(pcd); ++ return NULL; ++ } ++ } ++ ++ dwc_otg_pcd_reinit(pcd); ++ ++ /* Allocate the cfi object for the PCD */ ++#ifdef DWC_UTE_CFI ++ pcd->cfi = dwc_alloc(sizeof(cfiobject_t)); ++ if (NULL == pcd->cfi) ++ return NULL; ++ if (init_cfi(pcd->cfi)) { ++ CFI_INFO("%s: Failed to init the CFI object\n", __func__); ++ return NULL; ++ } ++#endif ++ ++ /* Initialize tasklets */ ++ pcd->start_xfer_tasklet = DWC_TASK_ALLOC(start_xfer_tasklet_func, pcd); ++ pcd->test_mode_tasklet = DWC_TASK_ALLOC(do_test_mode, pcd); ++ /* Initialize timer */ ++ pcd->srp_timer = DWC_TIMER_ALLOC("SRP TIMER", srp_timeout, core_if); ++ return pcd; ++} ++ ++void dwc_otg_pcd_remove(dwc_otg_pcd_t * pcd) ++{ ++ dwc_otg_dev_if_t *dev_if = GET_CORE_IF(pcd)->dev_if; ++ ++ if (GET_CORE_IF(pcd)->dma_enable) { ++ dwc_dma_free(sizeof(*pcd->setup_pkt) * 5, pcd->setup_pkt, ++ pcd->setup_pkt_dma_handle); ++ dwc_dma_free(sizeof(uint16_t), pcd->status_buf, ++ pcd->status_buf_dma_handle); ++ if (GET_CORE_IF(pcd)->dma_desc_enable) { ++ dwc_otg_ep_free_desc_chain(dev_if->setup_desc_addr[0], ++ dev_if-> ++ dma_setup_desc_addr[0], 1); ++ dwc_otg_ep_free_desc_chain(dev_if->setup_desc_addr[1], ++ dev_if-> ++ dma_setup_desc_addr[1], 1); ++ dwc_otg_ep_free_desc_chain(dev_if->in_desc_addr, ++ dev_if->dma_in_desc_addr, 1); ++ dwc_otg_ep_free_desc_chain(dev_if->out_desc_addr, ++ dev_if->dma_out_desc_addr, ++ 1); ++ } ++ } else { ++ dwc_free(pcd->setup_pkt); ++ dwc_free(pcd->status_buf); ++ } ++ DWC_SPINLOCK_FREE(pcd->lock); ++ DWC_TASK_FREE(pcd->start_xfer_tasklet); ++ DWC_TASK_FREE(pcd->test_mode_tasklet); ++ DWC_TIMER_FREE(pcd->srp_timer); ++ ++/* Release the CFI object's dynamic memory */ ++#ifdef DWC_UTE_CFI ++ if (pcd->cfi->ops.release) { ++ pcd->cfi->ops.release(pcd->cfi); ++ } ++#endif ++ ++ dwc_free(pcd); ++} ++ ++uint32_t dwc_otg_pcd_is_dualspeed(dwc_otg_pcd_t * pcd) ++{ ++ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); ++ ++ if ((core_if->core_params->speed == DWC_SPEED_PARAM_FULL) || ++ ((core_if->hwcfg2.b.hs_phy_type == 2) && ++ (core_if->hwcfg2.b.fs_phy_type == 1) && ++ (core_if->core_params->ulpi_fs_ls))) { ++ return 0; ++ } ++ ++ return 1; ++} ++ ++uint32_t dwc_otg_pcd_is_otg(dwc_otg_pcd_t * pcd) ++{ ++ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); ++ gusbcfg_data_t usbcfg = {.d32 = 0 }; ++ ++ usbcfg.d32 = dwc_read_reg32(&core_if->core_global_regs->gusbcfg); ++ if (!usbcfg.b.srpcap || !usbcfg.b.hnpcap) { ++ return 0; ++ } ++ ++ return 1; ++} ++ ++/** ++ * This function assigns periodic Tx FIFO to an periodic EP ++ * in shared Tx FIFO mode ++ */ ++static uint32_t assign_tx_fifo(dwc_otg_core_if_t * core_if) ++{ ++ uint32_t TxMsk = 1; ++ int i; ++ ++ for (i = 0; i < core_if->hwcfg4.b.num_in_eps; ++i) { ++ if ((TxMsk & core_if->tx_msk) == 0) { ++ core_if->tx_msk |= TxMsk; ++ return i + 1; ++ } ++ TxMsk <<= 1; ++ } ++ return 0; ++} ++ ++/** ++ * This function assigns periodic Tx FIFO to an periodic EP ++ * in shared Tx FIFO mode ++ */ ++static uint32_t assign_perio_tx_fifo(dwc_otg_core_if_t * core_if) ++{ ++ uint32_t PerTxMsk = 1; ++ int i; ++ for (i = 0; i < core_if->hwcfg4.b.num_dev_perio_in_ep; ++i) { ++ if ((PerTxMsk & core_if->p_tx_msk) == 0) { ++ core_if->p_tx_msk |= PerTxMsk; ++ return i + 1; ++ } ++ PerTxMsk <<= 1; ++ } ++ return 0; ++} ++ ++/** ++ * This function releases periodic Tx FIFO ++ * in shared Tx FIFO mode ++ */ ++static void release_perio_tx_fifo(dwc_otg_core_if_t * core_if, ++ uint32_t fifo_num) ++{ ++ core_if->p_tx_msk = ++ (core_if->p_tx_msk & (1 << (fifo_num - 1))) ^ core_if->p_tx_msk; ++} ++ ++/** ++ * This function releases periodic Tx FIFO ++ * in shared Tx FIFO mode ++ */ ++static void release_tx_fifo(dwc_otg_core_if_t * core_if, uint32_t fifo_num) ++{ ++ core_if->tx_msk = ++ (core_if->tx_msk & (1 << (fifo_num - 1))) ^ core_if->tx_msk; ++} ++ ++int dwc_otg_pcd_ep_enable(dwc_otg_pcd_t * pcd, ++ const uint8_t * ep_desc, void *usb_ep) ++{ ++ int num, dir; ++ dwc_otg_pcd_ep_t *ep = 0; ++ const usb_endpoint_descriptor_t *desc; ++ uint64_t flags; ++ int retval = 0; ++ ++ desc = (const usb_endpoint_descriptor_t *)ep_desc; ++ ++ if (!desc) { ++ pcd->ep0.priv = usb_ep; ++ ep = &pcd->ep0; ++ retval = -DWC_E_INVALID; ++ goto out; ++ } ++ ++ num = UE_GET_ADDR(desc->bEndpointAddress); ++ dir = UE_GET_DIR(desc->bEndpointAddress); ++ ++ if (!desc->wMaxPacketSize) { ++ DWC_WARN("bad maxpacketsize\n"); ++ retval = -DWC_E_INVALID; ++ goto out; ++ } ++ ++ if (dir == UE_DIR_IN) { ++ ep = &pcd->in_ep[num - 1]; ++ } else { ++ ep = &pcd->out_ep[num - 1]; ++ } ++ ++ DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags); ++ ++ ep->desc = desc; ++ ep->priv = usb_ep; ++ ++ /* ++ * Activate the EP ++ */ ++ ep->stopped = 0; ++ ++ ep->dwc_ep.is_in = (dir == UE_DIR_IN); ++ ep->dwc_ep.maxpacket = UGETW(desc->wMaxPacketSize); ++ ++ ep->dwc_ep.type = desc->bmAttributes & UE_XFERTYPE; ++ ++ if (ep->dwc_ep.is_in) { ++ if (!GET_CORE_IF(pcd)->en_multiple_tx_fifo) { ++ ep->dwc_ep.tx_fifo_num = 0; ++ ++ if (ep->dwc_ep.type == UE_ISOCHRONOUS) { ++ /* ++ * if ISOC EP then assign a Periodic Tx FIFO. ++ */ ++ ep->dwc_ep.tx_fifo_num = ++ assign_perio_tx_fifo(GET_CORE_IF(pcd)); ++ } ++ } else { ++ /* ++ * if Dedicated FIFOs mode is on then assign a Tx FIFO. ++ */ ++ ep->dwc_ep.tx_fifo_num = ++ assign_tx_fifo(GET_CORE_IF(pcd)); ++ ++ } ++ } ++ /* Set initial data PID. */ ++ if (ep->dwc_ep.type == UE_BULK) { ++ ep->dwc_ep.data_pid_start = 0; ++ } ++ ++ /* Alloc DMA Descriptors */ ++ if (GET_CORE_IF(pcd)->dma_desc_enable) { ++ if (ep->dwc_ep.type != UE_ISOCHRONOUS) { ++ ep->dwc_ep.desc_addr = ++ dwc_otg_ep_alloc_desc_chain(&ep->dwc_ep. ++ dma_desc_addr, ++ MAX_DMA_DESC_CNT); ++ if (!ep->dwc_ep.desc_addr) { ++ DWC_WARN("%s, can't allocate DMA descriptor\n", ++ __func__); ++ retval = -DWC_E_SHUTDOWN; ++ DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags); ++ goto out; ++ } ++ } ++ } ++ ++ DWC_DEBUGPL(DBG_PCD, "Activate %s: type=%d, mps=%d desc=%p\n", ++ (ep->dwc_ep.is_in ? "IN" : "OUT"), ++ ep->dwc_ep.type, ep->dwc_ep.maxpacket, ep->desc); ++ ++ dwc_otg_ep_activate(GET_CORE_IF(pcd), &ep->dwc_ep); ++ ++#ifdef DWC_UTE_CFI ++ if (pcd->cfi->ops.ep_enable) { ++ pcd->cfi->ops.ep_enable(pcd->cfi, pcd, ep); ++ } ++#endif ++ ++ DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags); ++ ++ out: ++ return retval; ++} ++ ++int dwc_otg_pcd_ep_disable(dwc_otg_pcd_t * pcd, void *ep_handle) ++{ ++ dwc_otg_pcd_ep_t *ep; ++ uint64_t flags; ++ dwc_otg_dev_dma_desc_t *desc_addr; ++ dwc_dma_t dma_desc_addr; ++ ++ ep = get_ep_from_handle(pcd, ep_handle); ++ ++ if (!ep || !ep->desc) { ++ DWC_DEBUGPL(DBG_PCD, "%s, %d %s not enabled\n", __func__, ++ ep->dwc_ep.num, ep->dwc_ep.is_in ? "IN" : "OUT"); ++ return -DWC_E_INVALID; ++ } ++ ++ DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags); ++ ++ dwc_otg_request_nuke(ep); ++ ++ dwc_otg_ep_deactivate(GET_CORE_IF(pcd), &ep->dwc_ep); ++ ep->desc = 0; ++ ep->stopped = 1; ++ ++ if (ep->dwc_ep.is_in) { ++ dwc_otg_flush_tx_fifo(GET_CORE_IF(pcd), ep->dwc_ep.tx_fifo_num); ++ release_perio_tx_fifo(GET_CORE_IF(pcd), ep->dwc_ep.tx_fifo_num); ++ release_tx_fifo(GET_CORE_IF(pcd), ep->dwc_ep.tx_fifo_num); ++ } ++ ++ /* Free DMA Descriptors */ ++ if (GET_CORE_IF(pcd)->dma_desc_enable) { ++ if (ep->dwc_ep.type != UE_ISOCHRONOUS) { ++ desc_addr = ep->dwc_ep.desc_addr; ++ dma_desc_addr = ep->dwc_ep.dma_desc_addr; ++ ++ /* Cannot call dma_free_coherent() with IRQs disabled */ ++ DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags); ++ dwc_otg_ep_free_desc_chain(desc_addr, dma_desc_addr, ++ MAX_DMA_DESC_CNT); ++ ++ goto out_unlocked; ++ } ++ } ++ ++ DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags); ++ ++ out_unlocked: ++ DWC_DEBUGPL(DBG_PCD, "%d %s disabled\n", ep->dwc_ep.num, ++ ep->dwc_ep.is_in ? "IN" : "OUT"); ++ return 0; ++ ++} ++ ++int dwc_otg_pcd_ep_queue(dwc_otg_pcd_t * pcd, void *ep_handle, ++ uint8_t * buf, dwc_dma_t dma_buf, uint32_t buflen, ++ int zero, void *req_handle, int atomic_alloc) ++{ ++ int prevented = 0; ++ uint64_t flags; ++ dwc_otg_pcd_request_t *req; ++ dwc_otg_pcd_ep_t *ep; ++ uint32_t max_transfer; ++ ++ ep = get_ep_from_handle(pcd, ep_handle); ++ if ((!ep->desc && ep->dwc_ep.num != 0)) { ++ DWC_WARN("bad ep\n"); ++ return -DWC_E_INVALID; ++ } ++ ++ if (atomic_alloc) { ++ req = dwc_alloc_atomic(sizeof(*req)); ++ } else { ++ req = dwc_alloc(sizeof(*req)); ++ } ++ ++ if (!req) { ++ return -DWC_E_NO_MEMORY; ++ } ++ DWC_CIRCLEQ_INIT_ENTRY(req, queue_entry); ++ if (!GET_CORE_IF(pcd)->core_params->opt) { ++ if (ep->dwc_ep.num != 0) { ++ DWC_ERROR("queue req %p, len %d buf %p\n", ++ req_handle, buflen, buf); ++ } ++ } ++ ++ req->buf = buf; ++ req->dma = dma_buf; ++ req->length = buflen; ++ req->sent_zlp = zero; ++ req->priv = req_handle; ++ ++ DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags); ++ ++ /* ++ * For EP0 IN without premature status, zlp is required? ++ */ ++ if (ep->dwc_ep.num == 0 && ep->dwc_ep.is_in) { ++ DWC_DEBUGPL(DBG_PCDV, "%d-OUT ZLP\n", ep->dwc_ep.num); ++ //_req->zero = 1; ++ } ++ ++ /* Start the transfer */ ++ if (DWC_CIRCLEQ_EMPTY(&ep->queue) && !ep->stopped) { ++ /* EP0 Transfer? */ ++ if (ep->dwc_ep.num == 0) { ++ switch (pcd->ep0state) { ++ case EP0_IN_DATA_PHASE: ++ DWC_DEBUGPL(DBG_PCD, ++ "%s ep0: EP0_IN_DATA_PHASE\n", ++ __func__); ++ break; ++ ++ case EP0_OUT_DATA_PHASE: ++ DWC_DEBUGPL(DBG_PCD, ++ "%s ep0: EP0_OUT_DATA_PHASE\n", ++ __func__); ++ if (pcd->request_config) { ++ /* Complete STATUS PHASE */ ++ ep->dwc_ep.is_in = 1; ++ pcd->ep0state = EP0_IN_STATUS_PHASE; ++ } ++ break; ++ ++ case EP0_IN_STATUS_PHASE: ++ DWC_DEBUGPL(DBG_PCD, ++ "%s ep0: EP0_IN_STATUS_PHASE\n", ++ __func__); ++ break; ++ ++ default: ++ DWC_DEBUGPL(DBG_ANY, "ep0: odd state %d\n", ++ pcd->ep0state); ++ DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags); ++ return -DWC_E_SHUTDOWN; ++ } ++ ++ ep->dwc_ep.dma_addr = dma_buf; ++ ep->dwc_ep.start_xfer_buff = buf; ++ ep->dwc_ep.xfer_buff = buf; ++ ep->dwc_ep.xfer_len = buflen; ++ ep->dwc_ep.xfer_count = 0; ++ ep->dwc_ep.sent_zlp = 0; ++ ep->dwc_ep.total_len = ep->dwc_ep.xfer_len; ++ ++ if (zero) { ++ if ((ep->dwc_ep.xfer_len % ++ ep->dwc_ep.maxpacket == 0) ++ && (ep->dwc_ep.xfer_len != 0)) { ++ ep->dwc_ep.sent_zlp = 1; ++ } ++ ++ } ++ ++ dwc_otg_ep0_start_transfer(GET_CORE_IF(pcd), ++ &ep->dwc_ep); ++ } // non-ep0 endpoints ++ else { ++#ifdef DWC_UTE_CFI ++ if (ep->dwc_ep.buff_mode != BM_STANDARD) { ++ /* store the request length */ ++ ep->dwc_ep.cfi_req_len = buflen; ++ pcd->cfi->ops.build_descriptors(pcd->cfi, pcd, ++ ep, req); ++ } else { ++#endif ++ max_transfer = ++ GET_CORE_IF(ep->pcd)->core_params-> ++ max_transfer_size; ++ ++ /* Setup and start the Transfer */ ++ ep->dwc_ep.dma_addr = dma_buf; ++ ep->dwc_ep.start_xfer_buff = buf; ++ ep->dwc_ep.xfer_buff = buf; ++ ep->dwc_ep.xfer_len = 0; ++ ep->dwc_ep.xfer_count = 0; ++ ep->dwc_ep.sent_zlp = 0; ++ ep->dwc_ep.total_len = buflen; ++ ++ ep->dwc_ep.maxxfer = max_transfer; ++ if (GET_CORE_IF(pcd)->dma_desc_enable) { ++ uint32_t out_max_xfer = ++ DDMA_MAX_TRANSFER_SIZE - ++ (DDMA_MAX_TRANSFER_SIZE % 4); ++ if (ep->dwc_ep.is_in) { ++ if (ep->dwc_ep.maxxfer > ++ DDMA_MAX_TRANSFER_SIZE) { ++ ep->dwc_ep.maxxfer = ++ DDMA_MAX_TRANSFER_SIZE; ++ } ++ } else { ++ if (ep->dwc_ep.maxxfer > ++ out_max_xfer) { ++ ep->dwc_ep.maxxfer = ++ out_max_xfer; ++ } ++ } ++ } ++ if (ep->dwc_ep.maxxfer < ep->dwc_ep.total_len) { ++ ep->dwc_ep.maxxfer -= ++ (ep->dwc_ep.maxxfer % ++ ep->dwc_ep.maxpacket); ++ } ++ ++ if (zero) { ++ if ((ep->dwc_ep.total_len % ++ ep->dwc_ep.maxpacket == 0) ++ && (ep->dwc_ep.total_len != 0)) { ++ ep->dwc_ep.sent_zlp = 1; ++ } ++ } ++#ifdef DWC_UTE_CFI ++ } ++#endif ++ dwc_otg_ep_start_transfer(GET_CORE_IF(pcd), ++ &ep->dwc_ep); ++ } ++ } ++ ++ if ((req != 0) || prevented) { ++ ++pcd->request_pending; ++ DWC_CIRCLEQ_INSERT_TAIL(&ep->queue, req, queue_entry); ++ if (ep->dwc_ep.is_in && ep->stopped ++ && !(GET_CORE_IF(pcd)->dma_enable)) { ++ /** @todo NGS Create a function for this. */ ++ diepmsk_data_t diepmsk = {.d32 = 0 }; ++ diepmsk.b.intktxfemp = 1; ++ if (GET_CORE_IF(pcd)->multiproc_int_enable) { ++ dwc_modify_reg32(&GET_CORE_IF(pcd)->dev_if-> ++ dev_global_regs-> ++ diepeachintmsk[ep->dwc_ep.num], ++ 0, diepmsk.d32); ++ } else { ++ dwc_modify_reg32(&GET_CORE_IF(pcd)->dev_if-> ++ dev_global_regs->diepmsk, 0, ++ diepmsk.d32); ++ } ++ ++ } ++ } ++ ++ DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags); ++ ++ return 0; ++} ++int dwc_otg_pcd_ep_dequeue(dwc_otg_pcd_t * pcd, void *ep_handle, ++ void *req_handle) ++{ ++ uint64_t flags; ++ dwc_otg_pcd_request_t *req; ++ dwc_otg_pcd_ep_t *ep; ++ ++ ep = get_ep_from_handle(pcd, ep_handle); ++ if (!ep->desc && ep->dwc_ep.num != 0) { ++ DWC_WARN("bad argument\n"); ++ return -DWC_E_INVALID; ++ } ++ ++ DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags); ++ ++ /* make sure it's actually queued on this endpoint */ ++ DWC_CIRCLEQ_FOREACH(req, &ep->queue, queue_entry) { ++ if (req->priv == (void *)req_handle) { ++ break; ++ } ++ } ++ ++ if (req->priv != (void *)req_handle) { ++ DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags); ++ return -DWC_E_INVALID; ++ } ++ ++ if (!DWC_CIRCLEQ_EMPTY_ENTRY(req, queue_entry)) { ++ dwc_otg_request_done(ep, req, -DWC_E_RESTART); ++ } else { ++ req = 0; ++ } ++ ++ DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags); ++ ++ return req ? 0 : -DWC_E_SHUTDOWN; ++ ++} ++ ++/** ++ * dwc_otg_pcd_ep_wedge - sets the halt feature and ignores clear requests ++ * ++ * Use this to stall an endpoint and ignore CLEAR_FEATURE(HALT_ENDPOINT) ++ * requests. If the gadget driver clears the halt status, it will ++ * automatically unwedge the endpoint. ++ * ++ * Returns zero on success, else negative DWC error code. ++ */ ++int dwc_otg_pcd_ep_wedge(dwc_otg_pcd_t * pcd, void *ep_handle) ++{ ++ dwc_otg_pcd_ep_t *ep; ++ uint64_t flags; ++ int retval = 0; ++ ++ ep = get_ep_from_handle(pcd, ep_handle); ++ ++ if ((!ep->desc && ep != &pcd->ep0) || ++ (ep->desc && (ep->desc->bmAttributes == UE_ISOCHRONOUS))) { ++ DWC_WARN("%s, bad ep\n", __func__); ++ return -DWC_E_INVALID; ++ } ++ ++ DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags); ++ if (!DWC_CIRCLEQ_EMPTY(&ep->queue)) { ++ DWC_WARN("%d %s XFer In process\n", ep->dwc_ep.num, ++ ep->dwc_ep.is_in ? "IN" : "OUT"); ++ retval = -DWC_E_AGAIN; ++ } else { ++ /* This code needs to be reviewed */ ++ if (ep->dwc_ep.is_in == 1 && GET_CORE_IF(pcd)->dma_desc_enable) { ++ dtxfsts_data_t txstatus; ++ fifosize_data_t txfifosize; ++ ++ txfifosize.d32 = ++ dwc_read_reg32(&GET_CORE_IF(pcd)->core_global_regs-> ++ dptxfsiz_dieptxf[ep->dwc_ep. ++ tx_fifo_num]); ++ txstatus.d32 = ++ dwc_read_reg32(&GET_CORE_IF(pcd)->dev_if-> ++ in_ep_regs[ep->dwc_ep.num]->dtxfsts); ++ ++ if (txstatus.b.txfspcavail < txfifosize.b.depth) { ++ DWC_WARN("%s() Data In Tx Fifo\n", __func__); ++ retval = -DWC_E_AGAIN; ++ } else { ++ if (ep->dwc_ep.num == 0) { ++ pcd->ep0state = EP0_STALL; ++ } ++ ++ ep->stopped = 1; ++ dwc_otg_ep_set_stall(GET_CORE_IF(pcd), ++ &ep->dwc_ep); ++ } ++ } else { ++ if (ep->dwc_ep.num == 0) { ++ pcd->ep0state = EP0_STALL; ++ } ++ ++ ep->stopped = 1; ++ dwc_otg_ep_set_stall(GET_CORE_IF(pcd), &ep->dwc_ep); ++ } ++ } ++ ++ DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags); ++ ++ return retval; ++} ++ ++int dwc_otg_pcd_ep_halt(dwc_otg_pcd_t * pcd, void *ep_handle, int value) ++{ ++ dwc_otg_pcd_ep_t *ep; ++ uint64_t flags; ++ int retval = 0; ++ ++ ep = get_ep_from_handle(pcd, ep_handle); ++ ++ if ((!ep->desc && ep != &pcd->ep0) || ++ (ep->desc && (ep->desc->bmAttributes == UE_ISOCHRONOUS))) { ++ DWC_WARN("%s, bad ep\n", __func__); ++ return -DWC_E_INVALID; ++ } ++ ++ DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags); ++ if (!DWC_CIRCLEQ_EMPTY(&ep->queue)) { ++ DWC_WARN("%d %s XFer In process\n", ep->dwc_ep.num, ++ ep->dwc_ep.is_in ? "IN" : "OUT"); ++ retval = -DWC_E_AGAIN; ++ } else if (value == 0) { ++ dwc_otg_ep_clear_stall(GET_CORE_IF(pcd), &ep->dwc_ep); ++ } else if (value == 1) { ++ if (ep->dwc_ep.is_in == 1 && GET_CORE_IF(pcd)->dma_desc_enable) { ++ dtxfsts_data_t txstatus; ++ fifosize_data_t txfifosize; ++ ++ txfifosize.d32 = ++ dwc_read_reg32(&GET_CORE_IF(pcd)->core_global_regs-> ++ dptxfsiz_dieptxf[ep->dwc_ep. ++ tx_fifo_num]); ++ txstatus.d32 = ++ dwc_read_reg32(&GET_CORE_IF(pcd)->dev_if-> ++ in_ep_regs[ep->dwc_ep.num]->dtxfsts); ++ ++ if (txstatus.b.txfspcavail < txfifosize.b.depth) { ++ DWC_WARN("%s() Data In Tx Fifo\n", __func__); ++ retval = -DWC_E_AGAIN; ++ } else { ++ if (ep->dwc_ep.num == 0) { ++ pcd->ep0state = EP0_STALL; ++ } ++ ++ ep->stopped = 1; ++ dwc_otg_ep_set_stall(GET_CORE_IF(pcd), ++ &ep->dwc_ep); ++ } ++ } else { ++ if (ep->dwc_ep.num == 0) { ++ pcd->ep0state = EP0_STALL; ++ } ++ ++ ep->stopped = 1; ++ dwc_otg_ep_set_stall(GET_CORE_IF(pcd), &ep->dwc_ep); ++ } ++ } else if (value == 2) { ++ ep->dwc_ep.stall_clear_flag = 0; ++ } else if (value == 3) { ++ ep->dwc_ep.stall_clear_flag = 1; ++ } ++ ++ DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags); ++ ++ return retval; ++} ++ ++/** ++ * This function initiates remote wakeup of the host from suspend state. ++ */ ++void dwc_otg_pcd_rem_wkup_from_suspend(dwc_otg_pcd_t * pcd, int set) ++{ ++ dctl_data_t dctl = { 0 }; ++ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); ++ dsts_data_t dsts; ++ ++ dsts.d32 = dwc_read_reg32(&core_if->dev_if->dev_global_regs->dsts); ++ if (!dsts.b.suspsts) { ++ DWC_WARN("Remote wakeup while is not in suspend state\n"); ++ } ++ /* Check if DEVICE_REMOTE_WAKEUP feature enabled */ ++ if (pcd->remote_wakeup_enable) { ++ if (set) { ++ dctl.b.rmtwkupsig = 1; ++ dwc_modify_reg32(&core_if->dev_if->dev_global_regs-> ++ dctl, 0, dctl.d32); ++ DWC_DEBUGPL(DBG_PCD, "Set Remote Wakeup\n"); ++ dwc_mdelay(2); ++ dwc_modify_reg32(&core_if->dev_if->dev_global_regs-> ++ dctl, dctl.d32, 0); ++ DWC_DEBUGPL(DBG_PCD, "Clear Remote Wakeup\n"); ++ } ++ } else { ++ DWC_DEBUGPL(DBG_PCD, "Remote Wakeup is disabled\n"); ++ } ++} ++ ++#ifdef CONFIG_USB_DWC_OTG_LPM ++/** ++ * This function initiates remote wakeup of the host from L1 sleep state. ++ */ ++void dwc_otg_pcd_rem_wkup_from_sleep(dwc_otg_pcd_t * pcd, int set) ++{ ++ glpmcfg_data_t lpmcfg; ++ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); ++ ++ lpmcfg.d32 = dwc_read_reg32(&core_if->core_global_regs->glpmcfg); ++ ++ /* Check if we are in L1 state */ ++ if (!lpmcfg.b.prt_sleep_sts) { ++ DWC_DEBUGPL(DBG_PCD, "Device is not in sleep state\n"); ++ return; ++ } ++ ++ /* Check if host allows remote wakeup */ ++ if (!lpmcfg.b.rem_wkup_en) { ++ DWC_DEBUGPL(DBG_PCD, "Host does not allow remote wakeup\n"); ++ return; ++ } ++ ++ /* Check if Resume OK */ ++ if (!lpmcfg.b.sleep_state_resumeok) { ++ DWC_DEBUGPL(DBG_PCD, "Sleep state resume is not OK\n"); ++ return; ++ } ++ ++ lpmcfg.d32 = dwc_read_reg32(&core_if->core_global_regs->glpmcfg); ++ lpmcfg.b.en_utmi_sleep = 0; ++ lpmcfg.b.hird_thres &= (~(1 << 4)); ++ dwc_write_reg32(&core_if->core_global_regs->glpmcfg, lpmcfg.d32); ++ ++ if (set) { ++ dctl_data_t dctl = {.d32 = 0 }; ++ dctl.b.rmtwkupsig = 1; ++ /* Set RmtWkUpSig bit to start remote wakup signaling. ++ * Hardware will automatically clear this bit. ++ */ ++ dwc_modify_reg32(&core_if->dev_if->dev_global_regs->dctl, ++ 0, dctl.d32); ++ DWC_DEBUGPL(DBG_PCD, "Set Remote Wakeup\n"); ++ } ++ ++} ++#endif ++ ++/** ++ * Performs remote wakeup. ++ */ ++void dwc_otg_pcd_remote_wakeup(dwc_otg_pcd_t * pcd, int set) ++{ ++ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); ++ if (dwc_otg_is_device_mode(core_if)) { ++#ifdef CONFIG_USB_DWC_OTG_LPM ++ if (core_if->lx_state == DWC_OTG_L1) { ++ dwc_otg_pcd_rem_wkup_from_sleep(pcd, set); ++ } else { ++#endif ++ dwc_otg_pcd_rem_wkup_from_suspend(pcd, set); ++#ifdef CONFIG_USB_DWC_OTG_LPM ++ } ++#endif ++ } ++ return; ++} ++ ++int dwc_otg_pcd_wakeup(dwc_otg_pcd_t * pcd) ++{ ++ dsts_data_t dsts; ++ gotgctl_data_t gotgctl; ++ uint64_t flags; ++ ++ DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags); ++ ++ /* ++ * This function starts the Protocol if no session is in progress. If ++ * a session is already in progress, but the device is suspended, ++ * remote wakeup signaling is started. ++ */ ++ ++ /* Check if valid session */ ++ gotgctl.d32 = ++ dwc_read_reg32(&(GET_CORE_IF(pcd)->core_global_regs->gotgctl)); ++ if (gotgctl.b.bsesvld) { ++ /* Check if suspend state */ ++ dsts.d32 = ++ dwc_read_reg32(& ++ (GET_CORE_IF(pcd)->dev_if->dev_global_regs-> ++ dsts)); ++ if (dsts.b.suspsts) { ++ dwc_otg_pcd_remote_wakeup(pcd, 1); ++ } ++ } else { ++ dwc_otg_pcd_initiate_srp(pcd); ++ } ++ ++ DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags); ++ return 0; ++ ++} ++ ++/** ++ * Start the SRP timer to detect when the SRP does not complete within ++ * 6 seconds. ++ * ++ * @param pcd the pcd structure. ++ */ ++void dwc_otg_pcd_start_srp_timer(dwc_otg_pcd_t * pcd) ++{ ++ GET_CORE_IF(pcd)->srp_timer_started = 1; ++ DWC_TIMER_SCHEDULE(pcd->srp_timer, 6000 /* 6 secs */ ); ++} ++ ++void dwc_otg_pcd_initiate_srp(dwc_otg_pcd_t * pcd) ++{ ++ uint32_t *addr = ++ (uint32_t *) & (GET_CORE_IF(pcd)->core_global_regs->gotgctl); ++ gotgctl_data_t mem; ++ gotgctl_data_t val; ++ ++ val.d32 = dwc_read_reg32(addr); ++ if (val.b.sesreq) { ++ DWC_ERROR("Session Request Already active!\n"); ++ return; ++ } ++ ++ DWC_INFO("Session Request Initated\n"); //NOTICE ++ mem.d32 = dwc_read_reg32(addr); ++ mem.b.sesreq = 1; ++ dwc_write_reg32(addr, mem.d32); ++ ++ /* Start the SRP timer */ ++ dwc_otg_pcd_start_srp_timer(pcd); ++ return; ++} ++ ++int dwc_otg_pcd_get_frame_number(dwc_otg_pcd_t * pcd) ++{ ++ return dwc_otg_get_frame_number(GET_CORE_IF(pcd)); ++} ++ ++int dwc_otg_pcd_is_lpm_enabled(dwc_otg_pcd_t * pcd) ++{ ++ return GET_CORE_IF(pcd)->core_params->lpm_enable; ++} ++ ++uint32_t get_b_hnp_enable(dwc_otg_pcd_t * pcd) ++{ ++ return pcd->b_hnp_enable; ++} ++ ++uint32_t get_a_hnp_support(dwc_otg_pcd_t * pcd) ++{ ++ return pcd->a_hnp_support; ++} ++ ++uint32_t get_a_alt_hnp_support(dwc_otg_pcd_t * pcd) ++{ ++ return pcd->a_alt_hnp_support; ++} ++ ++int dwc_otg_pcd_get_rmwkup_enable(dwc_otg_pcd_t * pcd) ++{ ++ return pcd->remote_wakeup_enable; ++} ++ ++#endif /* DWC_HOST_ONLY */ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_pcd.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_pcd.h 2013-07-26 19:31:23.000000000 +0000 +@@ -0,0 +1,216 @@ ++/* ========================================================================== ++ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_pcd.h $ ++ * $Revision: #39 $ ++ * $Date: 2008/12/16 $ ++ * $Change: 1153731 $ ++ * ++ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, ++ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless ++ * otherwise expressly agreed to in writing between Synopsys and you. ++ * ++ * The Software IS NOT an item of Licensed Software or Licensed Product under ++ * any End User Software License Agreement or Agreement for Licensed Product ++ * with Synopsys or any supplement thereto. You are permitted to use and ++ * redistribute this Software in source and binary forms, with or without ++ * modification, provided that redistributions of source code must retain this ++ * notice. You may not view, use, disclose, copy or distribute this file or ++ * any information contained herein except pursuant to this license grant from ++ * Synopsys. If you do not agree with this notice, including the disclaimer ++ * below, then you are not authorized to use the Software. ++ * ++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, ++ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR ++ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER ++ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY ++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH ++ * DAMAGE. ++ * ========================================================================== */ ++#ifndef DWC_HOST_ONLY ++#if !defined(__DWC_PCD_H__) ++#define __DWC_PCD_H__ ++ ++#include "usb.h" ++#include "dwc_otg_cil.h" ++#include "dwc_otg_pcd_if.h" ++struct cfiobject; ++ ++/** ++ * @file ++ * ++ * This file contains the structures, constants, and interfaces for ++ * the Perpherial Contoller Driver (PCD). ++ * ++ * The Peripheral Controller Driver (PCD) for Linux will implement the ++ * Gadget API, so that the existing Gadget drivers can be used. For ++ * the Mass Storage Function driver the File-backed USB Storage Gadget ++ * (FBS) driver will be used. The FBS driver supports the ++ * Control-Bulk (CB), Control-Bulk-Interrupt (CBI), and Bulk-Only ++ * transports. ++ * ++ */ ++ ++/** Max Transfer size for any EP */ ++#define DDMA_MAX_TRANSFER_SIZE 65535 ++ ++/** Max DMA Descriptor count for any EP */ ++#define MAX_DMA_DESC_CNT 64 ++ ++/** ++ * Get the pointer to the core_if from the pcd pointer. ++ */ ++#define GET_CORE_IF( _pcd ) (_pcd->core_if) ++ ++/** ++ * States of EP0. ++ */ ++typedef enum ep0_state { ++ EP0_DISCONNECT, /* no host */ ++ EP0_IDLE, ++ EP0_IN_DATA_PHASE, ++ EP0_OUT_DATA_PHASE, ++ EP0_IN_STATUS_PHASE, ++ EP0_OUT_STATUS_PHASE, ++ EP0_STALL, ++} ep0state_e; ++ ++/** Fordward declaration.*/ ++struct dwc_otg_pcd; ++ ++/** DWC_otg iso request structure. ++ * ++ */ ++typedef struct usb_iso_request dwc_otg_pcd_iso_request_t; ++ ++/** DWC_otg request structure. ++ * This structure is a list of requests. ++ */ ++typedef struct dwc_otg_pcd_request { ++ void *priv; ++ void *buf; ++ dwc_dma_t dma; ++ uint32_t length; ++ uint32_t actual; ++ unsigned sent_zlp:1; ++ ++ DWC_CIRCLEQ_ENTRY(dwc_otg_pcd_request) queue_entry; ++} dwc_otg_pcd_request_t; ++ ++DWC_CIRCLEQ_HEAD(req_list, dwc_otg_pcd_request); ++ ++/** PCD EP structure. ++ * This structure describes an EP, there is an array of EPs in the PCD ++ * structure. ++ */ ++typedef struct dwc_otg_pcd_ep { ++ /** USB EP Descriptor */ ++ const usb_endpoint_descriptor_t *desc; ++ ++ /** queue of dwc_otg_pcd_requests. */ ++ struct req_list queue; ++ unsigned stopped:1; ++ unsigned disabling:1; ++ unsigned dma:1; ++ unsigned queue_sof:1; ++ ++#ifdef DWC_EN_ISOC ++ /** ISOC req handle passed */ ++ void *iso_req_handle; ++#endif //_EN_ISOC_ ++ ++ /** DWC_otg ep data. */ ++ dwc_ep_t dwc_ep; ++ ++ /** Pointer to PCD */ ++ struct dwc_otg_pcd *pcd; ++ ++ void *priv; ++} dwc_otg_pcd_ep_t; ++ ++/** DWC_otg PCD Structure. ++ * This structure encapsulates the data for the dwc_otg PCD. ++ */ ++struct dwc_otg_pcd { ++ const struct dwc_otg_pcd_function_ops *fops; ++ /** Core Interface */ ++ dwc_otg_core_if_t *core_if; ++ /** State of EP0 */ ++ ep0state_e ep0state; ++ /** EP0 Request is pending */ ++ unsigned ep0_pending:1; ++ /** Indicates when SET CONFIGURATION Request is in process */ ++ unsigned request_config:1; ++ /** The state of the Remote Wakeup Enable. */ ++ unsigned remote_wakeup_enable:1; ++ /** The state of the B-Device HNP Enable. */ ++ unsigned b_hnp_enable:1; ++ /** The state of A-Device HNP Support. */ ++ unsigned a_hnp_support:1; ++ /** The state of the A-Device Alt HNP support. */ ++ unsigned a_alt_hnp_support:1; ++ /** Count of pending Requests */ ++ unsigned request_pending; ++ ++ /** SETUP packet for EP0 ++ * This structure is allocated as a DMA buffer on PCD initialization ++ * with enough space for up to 3 setup packets. ++ */ ++ union { ++ usb_device_request_t req; ++ uint32_t d32[2]; ++ } *setup_pkt; ++ ++ dwc_dma_t setup_pkt_dma_handle; ++ ++ /** 2-byte dma buffer used to return status from GET_STATUS */ ++ uint16_t *status_buf; ++ dwc_dma_t status_buf_dma_handle; ++ ++ /** EP0 */ ++ dwc_otg_pcd_ep_t ep0; ++ ++ /** Array of IN EPs. */ ++ dwc_otg_pcd_ep_t in_ep[MAX_EPS_CHANNELS - 1]; ++ /** Array of OUT EPs. */ ++ dwc_otg_pcd_ep_t out_ep[MAX_EPS_CHANNELS - 1]; ++ /** number of valid EPs in the above array. */ ++// unsigned num_eps : 4; ++ dwc_spinlock_t *lock; ++ /** Timer for SRP. If it expires before SRP is successful ++ * clear the SRP. */ ++ dwc_timer_t *srp_timer; ++ ++ /** Tasklet to defer starting of TEST mode transmissions until ++ * Status Phase has been completed. ++ */ ++ dwc_tasklet_t *test_mode_tasklet; ++ ++ /** Tasklet to delay starting of xfer in DMA mode */ ++ dwc_tasklet_t *start_xfer_tasklet; ++ ++ /** The test mode to enter when the tasklet is executed. */ ++ unsigned test_mode; ++ /** The cfi_api structure that implements most of the CFI API ++ * and OTG specific core configuration functionality ++ */ ++#ifdef DWC_UTE_CFI ++ struct cfiobject *cfi; ++#endif ++ ++}; ++ ++//FIXME this functions should be static, and this prototypes should be removed ++extern void dwc_otg_request_nuke(dwc_otg_pcd_ep_t * ep); ++extern void dwc_otg_request_done(dwc_otg_pcd_ep_t * ep, ++ dwc_otg_pcd_request_t * req, int32_t status); ++ ++void dwc_otg_iso_buffer_done(dwc_otg_pcd_t * pcd, dwc_otg_pcd_ep_t * ep, ++ void *req_handle); ++ ++extern void do_test_mode(void *data); ++#endif ++#endif /* DWC_HOST_ONLY */ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_pcd_if.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_pcd_if.h 2013-07-26 19:31:23.000000000 +0000 +@@ -0,0 +1,333 @@ ++/* ========================================================================== ++ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_pcd_if.h $ ++ * $Revision: #6 $ ++ * $Date: 2009/04/03 $ ++ * $Change: 1225059 $ ++ * ++ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, ++ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless ++ * otherwise expressly agreed to in writing between Synopsys and you. ++ * ++ * The Software IS NOT an item of Licensed Software or Licensed Product under ++ * any End User Software License Agreement or Agreement for Licensed Product ++ * with Synopsys or any supplement thereto. You are permitted to use and ++ * redistribute this Software in source and binary forms, with or without ++ * modification, provided that redistributions of source code must retain this ++ * notice. You may not view, use, disclose, copy or distribute this file or ++ * any information contained herein except pursuant to this license grant from ++ * Synopsys. If you do not agree with this notice, including the disclaimer ++ * below, then you are not authorized to use the Software. ++ * ++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, ++ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR ++ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER ++ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY ++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH ++ * DAMAGE. ++ * ========================================================================== */ ++#ifndef DWC_HOST_ONLY ++ ++#if !defined(__DWC_PCD_IF_H__) ++#define __DWC_PCD_IF_H__ ++ ++#include "dwc_os.h" ++#include "dwc_otg_core_if.h" ++ ++/** @file ++ * This file defines DWC_OTG PCD Core API. ++ */ ++ ++struct dwc_otg_pcd; ++typedef struct dwc_otg_pcd dwc_otg_pcd_t; ++ ++/** Maxpacket size for EP0 */ ++#define MAX_EP0_SIZE 64 ++/** Maxpacket size for any EP */ ++#define MAX_PACKET_SIZE 1024 ++ ++/** @name Function Driver Callbacks */ ++/** @{ */ ++ ++/** This function will be called whenever a previously queued request has ++ * completed. The status value will be set to -DWC_E_SHUTDOWN to indicated a ++ * failed or aborted transfer, or -DWC_E_RESTART to indicate the device was reset, ++ * or -DWC_E_TIMEOUT to indicate it timed out, or -DWC_E_INVALID to indicate invalid ++ * parameters. */ ++typedef int (*dwc_completion_cb_t) (dwc_otg_pcd_t * pcd, void *ep_handle, ++ void *req_handle, int32_t status, ++ uint32_t actual); ++/** ++ * This function will be called whenever a previousle queued ISOC request has ++ * completed. Count of ISOC packets could be read using dwc_otg_pcd_get_iso_packet_count ++ * function. ++ * The status of each ISOC packet could be read using dwc_otg_pcd_get_iso_packet_* ++ * functions. ++ */ ++typedef int (*dwc_isoc_completion_cb_t) (dwc_otg_pcd_t * pcd, void *ep_handle, ++ void *req_handle, int proc_buf_num); ++/** This function should handle any SETUP request that cannot be handled by the ++ * PCD Core. This includes most GET_DESCRIPTORs, SET_CONFIGS, Any ++ * class-specific requests, etc. The function must non-blocking. ++ * ++ * Returns 0 on success. ++ * Returns -DWC_E_NOT_SUPPORTED if the request is not supported. ++ * Returns -DWC_E_INVALID if the setup request had invalid parameters or bytes. ++ * Returns -DWC_E_SHUTDOWN on any other error. */ ++typedef int (*dwc_setup_cb_t) (dwc_otg_pcd_t * pcd, uint8_t * bytes); ++/** This is called whenever the device has been disconnected. The function ++ * driver should take appropriate action to clean up all pending requests in the ++ * PCD Core, remove all endpoints (except ep0), and initialize back to reset ++ * state. */ ++typedef int (*dwc_disconnect_cb_t) (dwc_otg_pcd_t * pcd); ++/** This function is called when device has been connected. */ ++typedef int (*dwc_connect_cb_t) (dwc_otg_pcd_t * pcd, int speed); ++/** This function is called when device has been suspended */ ++typedef int (*dwc_suspend_cb_t) (dwc_otg_pcd_t * pcd); ++/** This function is called when device has received LPM tokens, i.e. ++ * device has been sent to sleep state. */ ++typedef int (*dwc_sleep_cb_t) (dwc_otg_pcd_t * pcd); ++/** This function is called when device has been resumed ++ * from suspend(L2) or L1 sleep state. */ ++typedef int (*dwc_resume_cb_t) (dwc_otg_pcd_t * pcd); ++/** This function is called whenever hnp params has been changed. ++ * User can call get_b_hnp_enable, get_a_hnp_support, get_a_alt_hnp_support functions ++ * to get hnp parameters. */ ++typedef int (*dwc_hnp_params_changed_cb_t) (dwc_otg_pcd_t * pcd); ++/** This function is called whenever USB RESET is detected. */ ++typedef int (*dwc_reset_cb_t) (dwc_otg_pcd_t * pcd); ++ ++typedef int (*cfi_setup_cb_t) (dwc_otg_pcd_t * pcd, void *ctrl_req_bytes); ++ ++/** Function Driver Ops Data Structure */ ++struct dwc_otg_pcd_function_ops { ++ dwc_connect_cb_t connect; ++ dwc_disconnect_cb_t disconnect; ++ dwc_setup_cb_t setup; ++ dwc_completion_cb_t complete; ++ dwc_isoc_completion_cb_t isoc_complete; ++ dwc_suspend_cb_t suspend; ++ dwc_sleep_cb_t sleep; ++ dwc_resume_cb_t resume; ++ dwc_reset_cb_t reset; ++ dwc_hnp_params_changed_cb_t hnp_changed; ++ cfi_setup_cb_t cfi_setup; ++}; ++/** @} */ ++ ++/** @name Function Driver Functions */ ++/** @{ */ ++ ++/** Call this function to get pointer on dwc_otg_pcd_t, ++ * this pointer will be used for all PCD API functions. ++ * ++ * @param core_if The DWC_OTG Core ++ */ ++extern dwc_otg_pcd_t *dwc_otg_pcd_init(dwc_otg_core_if_t * core_if); ++ ++/** Frees PCD allocated by dwc_otg_pcd_init ++ * ++ * @param pcd The PCD ++ */ ++extern void dwc_otg_pcd_remove(dwc_otg_pcd_t * pcd); ++ ++/** Call this to bind the function driver to the PCD Core. ++ * ++ * @param pcd Pointer on dwc_otg_pcd_t returned by dwc_otg_pcd_init function. ++ * @param fops The Function Driver Ops data structure containing pointers to all callbacks. ++ */ ++extern void dwc_otg_pcd_start(dwc_otg_pcd_t * pcd, ++ const struct dwc_otg_pcd_function_ops *fops); ++ ++/** Enables an endpoint for use. This function enables an endpoint in ++ * the PCD. The endpoint is described by the ep_desc which has the ++ * same format as a USB ep descriptor. The ep_handle parameter is used to refer ++ * to the endpoint from other API functions and in callbacks. Normally this ++ * should be called after a SET_CONFIGURATION/SET_INTERFACE to configure the ++ * core for that interface. ++ * ++ * Returns -DWC_E_INVALID if invalid parameters were passed. ++ * Returns -DWC_E_SHUTDOWN if any other error ocurred. ++ * Returns 0 on success. ++ * ++ * @param pcd The PCD ++ * @param ep_desc Endpoint descriptor ++ * @param ep_handle Handle on endpoint, that will be used to identify endpoint. ++ */ ++extern int dwc_otg_pcd_ep_enable(dwc_otg_pcd_t * pcd, ++ const uint8_t * ep_desc, void *ep_handle); ++ ++/** Disable the endpoint referenced by ep_handle. ++ * ++ * Returns -DWC_E_INVALID if invalid parameters were passed. ++ * Returns -DWC_E_SHUTDOWN if any other error ocurred. ++ * Returns 0 on success. */ ++extern int dwc_otg_pcd_ep_disable(dwc_otg_pcd_t * pcd, void *ep_handle); ++ ++/** Queue a data transfer request on the endpoint referenced by ep_handle. ++ * After the transfer is completes, the complete callback will be called with ++ * the request status. ++ * ++ * @param pcd The PCD ++ * @param ep_handle The handle of the endpoint ++ * @param buf The buffer for the data ++ * @param dma_buf The DMA buffer for the data ++ * @param buflen The length of the data transfer ++ * @param zero Specifies whether to send zero length last packet. ++ * @param req_handle Set this handle to any value to use to reference this ++ * request in the ep_dequeue function or from the complete callback ++ * @param atomic_alloc If driver need to perform atomic allocations ++ * for internal data structures. ++ * ++ * Returns -DWC_E_INVALID if invalid parameters were passed. ++ * Returns -DWC_E_SHUTDOWN if any other error ocurred. ++ * Returns 0 on success. */ ++extern int dwc_otg_pcd_ep_queue(dwc_otg_pcd_t * pcd, void *ep_handle, ++ uint8_t * buf, dwc_dma_t dma_buf, ++ uint32_t buflen, int zero, void *req_handle, ++ int atomic_alloc); ++ ++/** De-queue the specified data transfer that has not yet completed. ++ * ++ * Returns -DWC_E_INVALID if invalid parameters were passed. ++ * Returns -DWC_E_SHUTDOWN if any other error ocurred. ++ * Returns 0 on success. */ ++extern int dwc_otg_pcd_ep_dequeue(dwc_otg_pcd_t * pcd, void *ep_handle, ++ void *req_handle); ++ ++/** Halt (STALL) an endpoint or clear it. ++ * ++ * Returns -DWC_E_INVALID if invalid parameters were passed. ++ * Returns -DWC_E_SHUTDOWN if any other error ocurred. ++ * Returns -DWC_E_AGAIN if the STALL cannot be sent and must be tried again later ++ * Returns 0 on success. */ ++extern int dwc_otg_pcd_ep_halt(dwc_otg_pcd_t * pcd, void *ep_handle, int value); ++ ++/** This function */ ++extern int dwc_otg_pcd_ep_wedge(dwc_otg_pcd_t * pcd, void *ep_handle); ++ ++/** This function should be called on every hardware interrupt */ ++extern int32_t dwc_otg_pcd_handle_intr(dwc_otg_pcd_t * pcd); ++ ++/** This function returns current frame number */ ++extern int dwc_otg_pcd_get_frame_number(dwc_otg_pcd_t * pcd); ++ ++/** ++ * Start isochronous transfers on the endpoint referenced by ep_handle. ++ * For isochronous transfers duble buffering is used. ++ * After processing each of buffers comlete callback will be called with ++ * status for each transaction. ++ * ++ * @param pcd The PCD ++ * @param ep_handle The handle of the endpoint ++ * @param buf0 The virtual address of first data buffer ++ * @param buf1 The virtual address of second data buffer ++ * @param dma0 The DMA address of first data buffer ++ * @param dma1 The DMA address of second data buffer ++ * @param sync_frame Data pattern frame number ++ * @param dp_frame Data size for pattern frame ++ * @param data_per_frame Data size for regular frame ++ * @param start_frame Frame number to start transfers, if -1 then start transfers ASAP. ++ * @param buf_proc_intrvl Interval of ISOC Buffer processing ++ * @param req_handle Handle of ISOC request ++ * @param atomic_alloc Specefies whether to perform atomic allocation for ++ * internal data structures. ++ * ++ * Returns -DWC_E_NO_MEMORY if there is no enough memory. ++ * Returns -DWC_E_INVALID if incorrect arguments are passed to the function. ++ * Returns -DW_E_SHUTDOWN for any other error. ++ * Returns 0 on success ++ */ ++extern int dwc_otg_pcd_iso_ep_start(dwc_otg_pcd_t * pcd, void *ep_handle, ++ uint8_t * buf0, uint8_t * buf1, ++ dwc_dma_t dma0, dwc_dma_t dma1, ++ int sync_frame, int dp_frame, ++ int data_per_frame, int start_frame, ++ int buf_proc_intrvl, void *req_handle, ++ int atomic_alloc); ++ ++/** Stop ISOC transfers on endpoint referenced by ep_handle. ++ * ++ * @param pcd The PCD ++ * @param ep_handle The handle of the endpoint ++ * @param req_handle Handle of ISOC request ++ * ++ * Returns -DWC_E_INVALID if incorrect arguments are passed to the function ++ * Returns 0 on success ++ */ ++int dwc_otg_pcd_iso_ep_stop(dwc_otg_pcd_t * pcd, void *ep_handle, ++ void *req_handle); ++ ++/** Get ISOC packet status. ++ * ++ * @param pcd The PCD ++ * @param ep_handle The handle of the endpoint ++ * @param iso_req_handle Isochronoush request handle ++ * @param packet Number of packet ++ * @param status Out parameter for returning status ++ * @param actual Out parameter for returning actual length ++ * @param offset Out parameter for returning offset ++ * ++ */ ++extern void dwc_otg_pcd_get_iso_packet_params(dwc_otg_pcd_t * pcd, ++ void *ep_handle, ++ void *iso_req_handle, int packet, ++ int *status, int *actual, ++ int *offset); ++ ++/** Get ISOC packet count. ++ * ++ * @param pcd The PCD ++ * @param ep_handle The handle of the endpoint ++ * @param iso_req_handle ++ */ ++extern int dwc_otg_pcd_get_iso_packet_count(dwc_otg_pcd_t * pcd, ++ void *ep_handle, ++ void *iso_req_handle); ++ ++/** This function starts the SRP Protocol if no session is in progress. If ++ * a session is already in progress, but the device is suspended, ++ * remote wakeup signaling is started. ++ */ ++extern int dwc_otg_pcd_wakeup(dwc_otg_pcd_t * pcd); ++ ++/** This function returns 1 if LPM support is enabled, and 0 otherwise. */ ++extern int dwc_otg_pcd_is_lpm_enabled(dwc_otg_pcd_t * pcd); ++ ++/** This function returns 1 if remote wakeup is allowed and 0, otherwise. */ ++extern int dwc_otg_pcd_get_rmwkup_enable(dwc_otg_pcd_t * pcd); ++ ++/** Initiate SRP */ ++extern void dwc_otg_pcd_initiate_srp(dwc_otg_pcd_t * pcd); ++ ++/** Starts remote wakeup signaling. */ ++extern void dwc_otg_pcd_remote_wakeup(dwc_otg_pcd_t * pcd, int set); ++ ++/** This function returns whether device is dualspeed.*/ ++extern uint32_t dwc_otg_pcd_is_dualspeed(dwc_otg_pcd_t * pcd); ++ ++/** This function returns whether device is otg. */ ++extern uint32_t dwc_otg_pcd_is_otg(dwc_otg_pcd_t * pcd); ++ ++/** These functions allow to get hnp parameters */ ++extern uint32_t get_b_hnp_enable(dwc_otg_pcd_t * pcd); ++extern uint32_t get_a_hnp_support(dwc_otg_pcd_t * pcd); ++extern uint32_t get_a_alt_hnp_support(dwc_otg_pcd_t * pcd); ++ ++/** CFI specific Interface functions */ ++/** Allocate a cfi buffer */ ++extern uint8_t *cfiw_ep_alloc_buffer(dwc_otg_pcd_t * pcd, void *pep, ++ dwc_dma_t * addr, size_t buflen, ++ int flags); ++ ++/******************************************************************************/ ++ ++/** @} */ ++ ++#endif /* __DWC_PCD_IF_H__ */ ++ ++#endif /* DWC_HOST_ONLY */ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_pcd_intr.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_pcd_intr.c 2013-07-26 19:31:23.000000000 +0000 +@@ -0,0 +1,4077 @@ ++/* ========================================================================== ++ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_pcd_intr.c $ ++ * $Revision: #93 $ ++ * $Date: 2009/04/02 $ ++ * $Change: 1224216 $ ++ * ++ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, ++ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless ++ * otherwise expressly agreed to in writing between Synopsys and you. ++ * ++ * The Software IS NOT an item of Licensed Software or Licensed Product under ++ * any End User Software License Agreement or Agreement for Licensed Product ++ * with Synopsys or any supplement thereto. You are permitted to use and ++ * redistribute this Software in source and binary forms, with or without ++ * modification, provided that redistributions of source code must retain this ++ * notice. You may not view, use, disclose, copy or distribute this file or ++ * any information contained herein except pursuant to this license grant from ++ * Synopsys. If you do not agree with this notice, including the disclaimer ++ * below, then you are not authorized to use the Software. ++ * ++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, ++ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR ++ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER ++ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY ++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH ++ * DAMAGE. ++ * ========================================================================== */ ++#ifndef DWC_HOST_ONLY ++ ++#include "dwc_otg_pcd.h" ++ ++#ifdef DWC_UTE_CFI ++#include "dwc_otg_cfi.h" ++#endif ++ ++//#define PRINT_CFI_DMA_DESCS ++ ++#define DEBUG_EP0 ++ ++/** ++ * This function updates OTG. ++ */ ++static void dwc_otg_pcd_update_otg(dwc_otg_pcd_t * pcd, const unsigned reset) ++{ ++ ++ if (reset) { ++ pcd->b_hnp_enable = 0; ++ pcd->a_hnp_support = 0; ++ pcd->a_alt_hnp_support = 0; ++ } ++ ++ if (pcd->fops->hnp_changed) { ++ pcd->fops->hnp_changed(pcd); ++ } ++} ++ ++/** @file ++ * This file contains the implementation of the PCD Interrupt handlers. ++ * ++ * The PCD handles the device interrupts. Many conditions can cause a ++ * device interrupt. When an interrupt occurs, the device interrupt ++ * service routine determines the cause of the interrupt and ++ * dispatches handling to the appropriate function. These interrupt ++ * handling functions are described below. ++ * All interrupt registers are processed from LSB to MSB. ++ */ ++ ++/** ++ * This function prints the ep0 state for debug purposes. ++ */ ++static inline void print_ep0_state(dwc_otg_pcd_t * pcd) ++{ ++#ifdef DEBUG ++ char str[40]; ++ ++ switch (pcd->ep0state) { ++ case EP0_DISCONNECT: ++ dwc_strcpy(str, "EP0_DISCONNECT"); ++ break; ++ case EP0_IDLE: ++ dwc_strcpy(str, "EP0_IDLE"); ++ break; ++ case EP0_IN_DATA_PHASE: ++ dwc_strcpy(str, "EP0_IN_DATA_PHASE"); ++ break; ++ case EP0_OUT_DATA_PHASE: ++ dwc_strcpy(str, "EP0_OUT_DATA_PHASE"); ++ break; ++ case EP0_IN_STATUS_PHASE: ++ dwc_strcpy(str, "EP0_IN_STATUS_PHASE"); ++ break; ++ case EP0_OUT_STATUS_PHASE: ++ dwc_strcpy(str, "EP0_OUT_STATUS_PHASE"); ++ break; ++ case EP0_STALL: ++ dwc_strcpy(str, "EP0_STALL"); ++ break; ++ default: ++ dwc_strcpy(str, "EP0_INVALID"); ++ } ++ ++ DWC_DEBUGPL(DBG_ANY, "%s(%d)\n", str, pcd->ep0state); ++#endif ++} ++ ++#ifdef DWC_UTE_CFI ++static inline void print_desc(struct dwc_otg_dma_desc *ddesc, ++ const uint8_t * epname, int descnum) ++{ ++ CFI_INFO ++ ("%s DMA_DESC(%d) buf=0x%08x bytes=0x%04x; sp=0x%x; l=0x%x; sts=0x%02x; bs=0x%02x\n", ++ epname, descnum, ddesc->buf, ddesc->status.b.bytes, ++ ddesc->status.b.sp, ddesc->status.b.l, ddesc->status.b.sts, ++ ddesc->status.b.bs); ++} ++#endif ++ ++/** ++ * This function returns pointer to in ep struct with number ep_num ++ */ ++static inline dwc_otg_pcd_ep_t *get_in_ep(dwc_otg_pcd_t * pcd, uint32_t ep_num) ++{ ++ int i; ++ int num_in_eps = GET_CORE_IF(pcd)->dev_if->num_in_eps; ++ if (ep_num == 0) { ++ return &pcd->ep0; ++ } else { ++ for (i = 0; i < num_in_eps; ++i) { ++ if (pcd->in_ep[i].dwc_ep.num == ep_num) ++ return &pcd->in_ep[i]; ++ } ++ return 0; ++ } ++} ++ ++/** ++ * This function returns pointer to out ep struct with number ep_num ++ */ ++static inline dwc_otg_pcd_ep_t *get_out_ep(dwc_otg_pcd_t * pcd, uint32_t ep_num) ++{ ++ int i; ++ int num_out_eps = GET_CORE_IF(pcd)->dev_if->num_out_eps; ++ if (ep_num == 0) { ++ return &pcd->ep0; ++ } else { ++ for (i = 0; i < num_out_eps; ++i) { ++ if (pcd->out_ep[i].dwc_ep.num == ep_num) ++ return &pcd->out_ep[i]; ++ } ++ return 0; ++ } ++} ++ ++/** ++ * This functions gets a pointer to an EP from the wIndex address ++ * value of the control request. ++ */ ++dwc_otg_pcd_ep_t *get_ep_by_addr(dwc_otg_pcd_t * pcd, u16 wIndex) ++{ ++ dwc_otg_pcd_ep_t *ep; ++ uint32_t ep_num = UE_GET_ADDR(wIndex); ++ ++ if (ep_num == 0) { ++ ep = &pcd->ep0; ++ } else if (UE_GET_DIR(wIndex) == UE_DIR_IN) { /* in ep */ ++ ep = &pcd->in_ep[ep_num - 1]; ++ } else { ++ ep = &pcd->out_ep[ep_num - 1]; ++ } ++ ++ return ep; ++} ++ ++/** ++ * This function checks the EP request queue, if the queue is not ++ * empty the next request is started. ++ */ ++void start_next_request(dwc_otg_pcd_ep_t * ep) ++{ ++ dwc_otg_pcd_request_t *req = 0; ++ uint32_t max_transfer = ++ GET_CORE_IF(ep->pcd)->core_params->max_transfer_size; ++ ++#ifdef DWC_UTE_CFI ++ struct dwc_otg_pcd *pcd; ++ pcd = ep->pcd; ++#endif ++ ++ if (!DWC_CIRCLEQ_EMPTY(&ep->queue)) { ++ req = DWC_CIRCLEQ_FIRST(&ep->queue); ++ ++#ifdef DWC_UTE_CFI ++ if (ep->dwc_ep.buff_mode != BM_STANDARD) { ++ ep->dwc_ep.cfi_req_len = req->length; ++ pcd->cfi->ops.build_descriptors(pcd->cfi, pcd, ep, req); ++ } else { ++#endif ++ /* Setup and start the Transfer */ ++ ep->dwc_ep.dma_addr = req->dma; ++ ep->dwc_ep.start_xfer_buff = req->buf; ++ ep->dwc_ep.xfer_buff = req->buf; ++ ep->dwc_ep.sent_zlp = 0; ++ ep->dwc_ep.total_len = req->length; ++ ep->dwc_ep.xfer_len = 0; ++ ep->dwc_ep.xfer_count = 0; ++ ++ ep->dwc_ep.maxxfer = max_transfer; ++ if (GET_CORE_IF(ep->pcd)->dma_desc_enable) { ++ uint32_t out_max_xfer = DDMA_MAX_TRANSFER_SIZE ++ - (DDMA_MAX_TRANSFER_SIZE % 4); ++ if (ep->dwc_ep.is_in) { ++ if (ep->dwc_ep.maxxfer > ++ DDMA_MAX_TRANSFER_SIZE) { ++ ep->dwc_ep.maxxfer = ++ DDMA_MAX_TRANSFER_SIZE; ++ } ++ } else { ++ if (ep->dwc_ep.maxxfer > out_max_xfer) { ++ ep->dwc_ep.maxxfer = ++ out_max_xfer; ++ } ++ } ++ } ++ if (ep->dwc_ep.maxxfer < ep->dwc_ep.total_len) { ++ ep->dwc_ep.maxxfer -= ++ (ep->dwc_ep.maxxfer % ep->dwc_ep.maxpacket); ++ } ++ if (req->sent_zlp) { ++ if ((ep->dwc_ep.total_len % ++ ep->dwc_ep.maxpacket == 0) ++ && (ep->dwc_ep.total_len != 0)) { ++ ep->dwc_ep.sent_zlp = 1; ++ } ++ ++ } ++#ifdef DWC_UTE_CFI ++ } ++#endif ++ dwc_otg_ep_start_transfer(GET_CORE_IF(ep->pcd), &ep->dwc_ep); ++ } ++} ++ ++/** ++ * This function handles the SOF Interrupts. At this time the SOF ++ * Interrupt is disabled. ++ */ ++int32_t dwc_otg_pcd_handle_sof_intr(dwc_otg_pcd_t * pcd) ++{ ++ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); ++ ++ gintsts_data_t gintsts; ++ ++ DWC_DEBUGPL(DBG_PCD, "SOF\n"); ++ ++ /* Clear interrupt */ ++ gintsts.d32 = 0; ++ gintsts.b.sofintr = 1; ++ dwc_write_reg32(&core_if->core_global_regs->gintsts, gintsts.d32); ++ ++ return 1; ++} ++ ++/** ++ * This function handles the Rx Status Queue Level Interrupt, which ++ * indicates that there is a least one packet in the Rx FIFO. The ++ * packets are moved from the FIFO to memory, where they will be ++ * processed when the Endpoint Interrupt Register indicates Transfer ++ * Complete or SETUP Phase Done. ++ * ++ * Repeat the following until the Rx Status Queue is empty: ++ * -# Read the Receive Status Pop Register (GRXSTSP) to get Packet ++ * info ++ * -# If Receive FIFO is empty then skip to step Clear the interrupt ++ * and exit ++ * -# If SETUP Packet call dwc_otg_read_setup_packet to copy the ++ * SETUP data to the buffer ++ * -# If OUT Data Packet call dwc_otg_read_packet to copy the data ++ * to the destination buffer ++ */ ++int32_t dwc_otg_pcd_handle_rx_status_q_level_intr(dwc_otg_pcd_t * pcd) ++{ ++ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); ++ dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs; ++ gintmsk_data_t gintmask = {.d32 = 0 }; ++ device_grxsts_data_t status; ++ dwc_otg_pcd_ep_t *ep; ++ gintsts_data_t gintsts; ++#ifdef DEBUG ++ static char *dpid_str[] = { "D0", "D2", "D1", "MDATA" }; ++#endif ++ ++ //DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, _pcd); ++ /* Disable the Rx Status Queue Level interrupt */ ++ gintmask.b.rxstsqlvl = 1; ++ dwc_modify_reg32(&global_regs->gintmsk, gintmask.d32, 0); ++ ++ /* Get the Status from the top of the FIFO */ ++ status.d32 = dwc_read_reg32(&global_regs->grxstsp); ++ ++ DWC_DEBUGPL(DBG_PCD, "EP:%d BCnt:%d DPID:%s " ++ "pktsts:%x Frame:%d(0x%0x)\n", ++ status.b.epnum, status.b.bcnt, ++ dpid_str[status.b.dpid], ++ status.b.pktsts, status.b.fn, status.b.fn); ++ /* Get pointer to EP structure */ ++ ep = get_out_ep(pcd, status.b.epnum); ++ ++ switch (status.b.pktsts) { ++ case DWC_DSTS_GOUT_NAK: ++ DWC_DEBUGPL(DBG_PCDV, "Global OUT NAK\n"); ++ break; ++ case DWC_STS_DATA_UPDT: ++ DWC_DEBUGPL(DBG_PCDV, "OUT Data Packet\n"); ++ if (status.b.bcnt && ep->dwc_ep.xfer_buff) { ++ /** @todo NGS Check for buffer overflow? */ ++ dwc_otg_read_packet(core_if, ++ ep->dwc_ep.xfer_buff, ++ status.b.bcnt); ++ ep->dwc_ep.xfer_count += status.b.bcnt; ++ ep->dwc_ep.xfer_buff += status.b.bcnt; ++ } ++ break; ++ case DWC_STS_XFER_COMP: ++ DWC_DEBUGPL(DBG_PCDV, "OUT Complete\n"); ++ break; ++ case DWC_DSTS_SETUP_COMP: ++#ifdef DEBUG_EP0 ++ DWC_DEBUGPL(DBG_PCDV, "Setup Complete\n"); ++#endif ++ break; ++ case DWC_DSTS_SETUP_UPDT: ++ dwc_otg_read_setup_packet(core_if, pcd->setup_pkt->d32); ++#ifdef DEBUG_EP0 ++ DWC_DEBUGPL(DBG_PCD, ++ "SETUP PKT: %02x.%02x v%04x i%04x l%04x\n", ++ pcd->setup_pkt->req.bmRequestType, ++ pcd->setup_pkt->req.bRequest, ++ UGETW(pcd->setup_pkt->req.wValue), ++ UGETW(pcd->setup_pkt->req.wIndex), ++ UGETW(pcd->setup_pkt->req.wLength)); ++#endif ++ ep->dwc_ep.xfer_count += status.b.bcnt; ++ break; ++ default: ++ DWC_DEBUGPL(DBG_PCDV, "Invalid Packet Status (0x%0x)\n", ++ status.b.pktsts); ++ break; ++ } ++ ++ /* Enable the Rx Status Queue Level interrupt */ ++ dwc_modify_reg32(&global_regs->gintmsk, 0, gintmask.d32); ++ /* Clear interrupt */ ++ gintsts.d32 = 0; ++ gintsts.b.rxstsqlvl = 1; ++ dwc_write_reg32(&global_regs->gintsts, gintsts.d32); ++ ++ //DWC_DEBUGPL(DBG_PCDV, "EXIT: %s\n", __func__); ++ return 1; ++} ++ ++/** ++ * This function examines the Device IN Token Learning Queue to ++ * determine the EP number of the last IN token received. This ++ * implementation is for the Mass Storage device where there are only ++ * 2 IN EPs (Control-IN and BULK-IN). ++ * ++ * The EP numbers for the first six IN Tokens are in DTKNQR1 and there ++ * are 8 EP Numbers in each of the other possible DTKNQ Registers. ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ * ++ */ ++static inline int get_ep_of_last_in_token(dwc_otg_core_if_t * core_if) ++{ ++ dwc_otg_device_global_regs_t *dev_global_regs = ++ core_if->dev_if->dev_global_regs; ++ const uint32_t TOKEN_Q_DEPTH = core_if->hwcfg2.b.dev_token_q_depth; ++ /* Number of Token Queue Registers */ ++ const int DTKNQ_REG_CNT = (TOKEN_Q_DEPTH + 7) / 8; ++ dtknq1_data_t dtknqr1; ++ uint32_t in_tkn_epnums[4]; ++ int ndx = 0; ++ int i = 0; ++ volatile uint32_t *addr = &dev_global_regs->dtknqr1; ++ int epnum = 0; ++ ++ //DWC_DEBUGPL(DBG_PCD,"dev_token_q_depth=%d\n",TOKEN_Q_DEPTH); ++ ++ /* Read the DTKNQ Registers */ ++ for (i = 0; i < DTKNQ_REG_CNT; i++) { ++ in_tkn_epnums[i] = dwc_read_reg32(addr); ++ DWC_DEBUGPL(DBG_PCDV, "DTKNQR%d=0x%08x\n", i + 1, ++ in_tkn_epnums[i]); ++ if (addr == &dev_global_regs->dvbusdis) { ++ addr = &dev_global_regs->dtknqr3_dthrctl; ++ } else { ++ ++addr; ++ } ++ ++ } ++ ++ /* Copy the DTKNQR1 data to the bit field. */ ++ dtknqr1.d32 = in_tkn_epnums[0]; ++ /* Get the EP numbers */ ++ in_tkn_epnums[0] = dtknqr1.b.epnums0_5; ++ ndx = dtknqr1.b.intknwptr - 1; ++ ++ //DWC_DEBUGPL(DBG_PCDV,"ndx=%d\n",ndx); ++ if (ndx == -1) { ++ /** @todo Find a simpler way to calculate the max ++ * queue position.*/ ++ int cnt = TOKEN_Q_DEPTH; ++ if (TOKEN_Q_DEPTH <= 6) { ++ cnt = TOKEN_Q_DEPTH - 1; ++ } else if (TOKEN_Q_DEPTH <= 14) { ++ cnt = TOKEN_Q_DEPTH - 7; ++ } else if (TOKEN_Q_DEPTH <= 22) { ++ cnt = TOKEN_Q_DEPTH - 15; ++ } else { ++ cnt = TOKEN_Q_DEPTH - 23; ++ } ++ epnum = (in_tkn_epnums[DTKNQ_REG_CNT - 1] >> (cnt * 4)) & 0xF; ++ } else { ++ if (ndx <= 5) { ++ epnum = (in_tkn_epnums[0] >> (ndx * 4)) & 0xF; ++ } else if (ndx <= 13) { ++ ndx -= 6; ++ epnum = (in_tkn_epnums[1] >> (ndx * 4)) & 0xF; ++ } else if (ndx <= 21) { ++ ndx -= 14; ++ epnum = (in_tkn_epnums[2] >> (ndx * 4)) & 0xF; ++ } else if (ndx <= 29) { ++ ndx -= 22; ++ epnum = (in_tkn_epnums[3] >> (ndx * 4)) & 0xF; ++ } ++ } ++ //DWC_DEBUGPL(DBG_PCD,"epnum=%d\n",epnum); ++ return epnum; ++} ++ ++/** ++ * This interrupt occurs when the non-periodic Tx FIFO is half-empty. ++ * The active request is checked for the next packet to be loaded into ++ * the non-periodic Tx FIFO. ++ */ ++int32_t dwc_otg_pcd_handle_np_tx_fifo_empty_intr(dwc_otg_pcd_t * pcd) ++{ ++ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); ++ dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs; ++ dwc_otg_dev_in_ep_regs_t *ep_regs; ++ gnptxsts_data_t txstatus = {.d32 = 0 }; ++ gintsts_data_t gintsts; ++ ++ int epnum = 0; ++ dwc_otg_pcd_ep_t *ep = 0; ++ uint32_t len = 0; ++ int dwords; ++ ++ /* Get the epnum from the IN Token Learning Queue. */ ++ epnum = get_ep_of_last_in_token(core_if); ++ ep = get_in_ep(pcd, epnum); ++ ++ DWC_DEBUGPL(DBG_PCD, "NP TxFifo Empty: %d \n", epnum); ++ ++ ep_regs = core_if->dev_if->in_ep_regs[epnum]; ++ ++ len = ep->dwc_ep.xfer_len - ep->dwc_ep.xfer_count; ++ if (len > ep->dwc_ep.maxpacket) { ++ len = ep->dwc_ep.maxpacket; ++ } ++ dwords = (len + 3) / 4; ++ ++ /* While there is space in the queue and space in the FIFO and ++ * More data to tranfer, Write packets to the Tx FIFO */ ++ txstatus.d32 = dwc_read_reg32(&global_regs->gnptxsts); ++ DWC_DEBUGPL(DBG_PCDV, "b4 GNPTXSTS=0x%08x\n", txstatus.d32); ++ ++ while (txstatus.b.nptxqspcavail > 0 && ++ txstatus.b.nptxfspcavail > dwords && ++ ep->dwc_ep.xfer_count < ep->dwc_ep.xfer_len) { ++ /* Write the FIFO */ ++ dwc_otg_ep_write_packet(core_if, &ep->dwc_ep, 0); ++ len = ep->dwc_ep.xfer_len - ep->dwc_ep.xfer_count; ++ ++ if (len > ep->dwc_ep.maxpacket) { ++ len = ep->dwc_ep.maxpacket; ++ } ++ ++ dwords = (len + 3) / 4; ++ txstatus.d32 = dwc_read_reg32(&global_regs->gnptxsts); ++ DWC_DEBUGPL(DBG_PCDV, "GNPTXSTS=0x%08x\n", txstatus.d32); ++ } ++ ++ DWC_DEBUGPL(DBG_PCDV, "GNPTXSTS=0x%08x\n", ++ dwc_read_reg32(&global_regs->gnptxsts)); ++ ++ /* Clear interrupt */ ++ gintsts.d32 = 0; ++ gintsts.b.nptxfempty = 1; ++ dwc_write_reg32(&global_regs->gintsts, gintsts.d32); ++ ++ return 1; ++} ++ ++/** ++ * This function is called when dedicated Tx FIFO Empty interrupt occurs. ++ * The active request is checked for the next packet to be loaded into ++ * apropriate Tx FIFO. ++ */ ++static int32_t write_empty_tx_fifo(dwc_otg_pcd_t * pcd, uint32_t epnum) ++{ ++ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); ++ dwc_otg_dev_if_t *dev_if = core_if->dev_if; ++ dwc_otg_dev_in_ep_regs_t *ep_regs; ++ dtxfsts_data_t txstatus = {.d32 = 0 }; ++ dwc_otg_pcd_ep_t *ep = 0; ++ uint32_t len = 0; ++ int dwords; ++ ++ ep = get_in_ep(pcd, epnum); ++ ++ DWC_DEBUGPL(DBG_PCD, "Dedicated TxFifo Empty: %d \n", epnum); ++ ++ ep_regs = core_if->dev_if->in_ep_regs[epnum]; ++ ++ len = ep->dwc_ep.xfer_len - ep->dwc_ep.xfer_count; ++ ++ if (len > ep->dwc_ep.maxpacket) { ++ len = ep->dwc_ep.maxpacket; ++ } ++ ++ dwords = (len + 3) / 4; ++ ++ /* While there is space in the queue and space in the FIFO and ++ * More data to tranfer, Write packets to the Tx FIFO */ ++ txstatus.d32 = dwc_read_reg32(&dev_if->in_ep_regs[epnum]->dtxfsts); ++ DWC_DEBUGPL(DBG_PCDV, "b4 dtxfsts[%d]=0x%08x\n", epnum, txstatus.d32); ++ ++ while (txstatus.b.txfspcavail > dwords && ++ ep->dwc_ep.xfer_count < ep->dwc_ep.xfer_len && ++ ep->dwc_ep.xfer_len != 0) { ++ /* Write the FIFO */ ++ dwc_otg_ep_write_packet(core_if, &ep->dwc_ep, 0); ++ ++ len = ep->dwc_ep.xfer_len - ep->dwc_ep.xfer_count; ++ if (len > ep->dwc_ep.maxpacket) { ++ len = ep->dwc_ep.maxpacket; ++ } ++ ++ dwords = (len + 3) / 4; ++ txstatus.d32 = ++ dwc_read_reg32(&dev_if->in_ep_regs[epnum]->dtxfsts); ++ DWC_DEBUGPL(DBG_PCDV, "dtxfsts[%d]=0x%08x\n", epnum, ++ txstatus.d32); ++ } ++ ++ DWC_DEBUGPL(DBG_PCDV, "b4 dtxfsts[%d]=0x%08x\n", epnum, ++ dwc_read_reg32(&dev_if->in_ep_regs[epnum]->dtxfsts)); ++ ++ return 1; ++} ++ ++/** ++ * This function is called when the Device is disconnected. It stops ++ * any active requests and informs the Gadget driver of the ++ * disconnect. ++ */ ++void dwc_otg_pcd_stop(dwc_otg_pcd_t * pcd) ++{ ++ int i, num_in_eps, num_out_eps; ++ dwc_otg_pcd_ep_t *ep; ++ ++ gintmsk_data_t intr_mask = {.d32 = 0 }; ++ ++ DWC_SPINLOCK(pcd->lock); ++ ++ num_in_eps = GET_CORE_IF(pcd)->dev_if->num_in_eps; ++ num_out_eps = GET_CORE_IF(pcd)->dev_if->num_out_eps; ++ ++ DWC_DEBUGPL(DBG_PCDV, "%s() \n", __func__); ++ /* don't disconnect drivers more than once */ ++ if (pcd->ep0state == EP0_DISCONNECT) { ++ DWC_DEBUGPL(DBG_ANY, "%s() Already Disconnected\n", __func__); ++ return; ++ } ++ pcd->ep0state = EP0_DISCONNECT; ++ ++ /* Reset the OTG state. */ ++ dwc_otg_pcd_update_otg(pcd, 1); ++ ++ /* Disable the NP Tx Fifo Empty Interrupt. */ ++ intr_mask.b.nptxfempty = 1; ++ dwc_modify_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk, ++ intr_mask.d32, 0); ++ ++ /* Flush the FIFOs */ ++ /**@todo NGS Flush Periodic FIFOs */ ++ dwc_otg_flush_tx_fifo(GET_CORE_IF(pcd), 0x10); ++ dwc_otg_flush_rx_fifo(GET_CORE_IF(pcd)); ++ ++ /* prevent new request submissions, kill any outstanding requests */ ++ ep = &pcd->ep0; ++ dwc_otg_request_nuke(ep); ++ /* prevent new request submissions, kill any outstanding requests */ ++ for (i = 0; i < num_in_eps; i++) { ++ dwc_otg_pcd_ep_t *ep = &pcd->in_ep[i]; ++ dwc_otg_request_nuke(ep); ++ } ++ /* prevent new request submissions, kill any outstanding requests */ ++ for (i = 0; i < num_out_eps; i++) { ++ dwc_otg_pcd_ep_t *ep = &pcd->out_ep[i]; ++ dwc_otg_request_nuke(ep); ++ } ++ ++ /* report disconnect; the driver is already quiesced */ ++ if (pcd->fops->disconnect) { ++ DWC_SPINUNLOCK(pcd->lock); ++ pcd->fops->disconnect(pcd); ++ DWC_SPINLOCK(pcd->lock); ++ } ++ DWC_SPINUNLOCK(pcd->lock); ++} ++ ++/** ++ * This interrupt indicates that ... ++ */ ++int32_t dwc_otg_pcd_handle_i2c_intr(dwc_otg_pcd_t * pcd) ++{ ++ gintmsk_data_t intr_mask = {.d32 = 0 }; ++ gintsts_data_t gintsts; ++ ++ DWC_PRINTF("INTERRUPT Handler not implemented for %s\n", "i2cintr"); ++ intr_mask.b.i2cintr = 1; ++ dwc_modify_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk, ++ intr_mask.d32, 0); ++ ++ /* Clear interrupt */ ++ gintsts.d32 = 0; ++ gintsts.b.i2cintr = 1; ++ dwc_write_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintsts, ++ gintsts.d32); ++ return 1; ++} ++ ++/** ++ * This interrupt indicates that ... ++ */ ++int32_t dwc_otg_pcd_handle_early_suspend_intr(dwc_otg_pcd_t * pcd) ++{ ++ gintsts_data_t gintsts; ++#if defined(VERBOSE) ++ DWC_PRINTF("Early Suspend Detected\n"); ++#endif ++ /* Clear interrupt */ ++ gintsts.d32 = 0; ++ gintsts.b.erlysuspend = 1; ++ dwc_write_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintsts, ++ gintsts.d32); ++ return 1; ++} ++ ++/** ++ * This function configures EPO to receive SETUP packets. ++ * ++ * @todo NGS: Update the comments from the HW FS. ++ * ++ * -# Program the following fields in the endpoint specific registers ++ * for Control OUT EP 0, in order to receive a setup packet ++ * - DOEPTSIZ0.Packet Count = 3 (To receive up to 3 back to back ++ * setup packets) ++ * - DOEPTSIZE0.Transfer Size = 24 Bytes (To receive up to 3 back ++ * to back setup packets) ++ * - In DMA mode, DOEPDMA0 Register with a memory address to ++ * store any setup packets received ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ * @param pcd Programming view of the PCD. ++ */ ++static inline void ep0_out_start(dwc_otg_core_if_t * core_if, ++ dwc_otg_pcd_t * pcd) ++{ ++ dwc_otg_dev_if_t *dev_if = core_if->dev_if; ++ deptsiz0_data_t doeptsize0 = {.d32 = 0 }; ++ dwc_otg_dev_dma_desc_t *dma_desc; ++ depctl_data_t doepctl = {.d32 = 0 }; ++ ++#ifdef VERBOSE ++ DWC_DEBUGPL(DBG_PCDV, "%s() doepctl0=%0x\n", __func__, ++ dwc_read_reg32(&dev_if->out_ep_regs[0]->doepctl)); ++#endif ++ ++ doeptsize0.b.supcnt = 3; ++ doeptsize0.b.pktcnt = 1; ++ doeptsize0.b.xfersize = 8 * 3; ++ ++ if (core_if->dma_enable) { ++ if (!core_if->dma_desc_enable) { ++ /** put here as for Hermes mode deptisz register should not be written */ ++ dwc_write_reg32(&dev_if->out_ep_regs[0]->doeptsiz, ++ doeptsize0.d32); ++ ++ /** @todo dma needs to handle multiple setup packets (up to 3) */ ++ dwc_write_reg32(&dev_if->out_ep_regs[0]->doepdma, ++ pcd->setup_pkt_dma_handle); ++ } else { ++ dev_if->setup_desc_index = ++ (dev_if->setup_desc_index + 1) & 1; ++ dma_desc = ++ dev_if->setup_desc_addr[dev_if->setup_desc_index]; ++ ++ /** DMA Descriptor Setup */ ++ dma_desc->status.b.bs = BS_HOST_BUSY; ++ dma_desc->status.b.l = 1; ++ dma_desc->status.b.ioc = 1; ++ dma_desc->status.b.bytes = pcd->ep0.dwc_ep.maxpacket; ++ dma_desc->buf = pcd->setup_pkt_dma_handle; ++ dma_desc->status.b.bs = BS_HOST_READY; ++ ++ /** DOEPDMA0 Register write */ ++ dwc_write_reg32(&dev_if->out_ep_regs[0]->doepdma, ++ dev_if->dma_setup_desc_addr[dev_if-> ++ setup_desc_index]); ++ } ++ ++ } else { ++ /** put here as for Hermes mode deptisz register should not be written */ ++ dwc_write_reg32(&dev_if->out_ep_regs[0]->doeptsiz, ++ doeptsize0.d32); ++ } ++ ++ /** DOEPCTL0 Register write */ ++ doepctl.b.epena = 1; ++ doepctl.b.cnak = 1; ++ dwc_write_reg32(&dev_if->out_ep_regs[0]->doepctl, doepctl.d32); ++ ++#ifdef VERBOSE ++ DWC_DEBUGPL(DBG_PCDV, "doepctl0=%0x\n", ++ dwc_read_reg32(&dev_if->out_ep_regs[0]->doepctl)); ++ DWC_DEBUGPL(DBG_PCDV, "diepctl0=%0x\n", ++ dwc_read_reg32(&dev_if->in_ep_regs[0]->diepctl)); ++#endif ++} ++ ++/** ++ * This interrupt occurs when a USB Reset is detected. When the USB ++ * Reset Interrupt occurs the device state is set to DEFAULT and the ++ * EP0 state is set to IDLE. ++ * -# Set the NAK bit for all OUT endpoints (DOEPCTLn.SNAK = 1) ++ * -# Unmask the following interrupt bits ++ * - DAINTMSK.INEP0 = 1 (Control 0 IN endpoint) ++ * - DAINTMSK.OUTEP0 = 1 (Control 0 OUT endpoint) ++ * - DOEPMSK.SETUP = 1 ++ * - DOEPMSK.XferCompl = 1 ++ * - DIEPMSK.XferCompl = 1 ++ * - DIEPMSK.TimeOut = 1 ++ * -# Program the following fields in the endpoint specific registers ++ * for Control OUT EP 0, in order to receive a setup packet ++ * - DOEPTSIZ0.Packet Count = 3 (To receive up to 3 back to back ++ * setup packets) ++ * - DOEPTSIZE0.Transfer Size = 24 Bytes (To receive up to 3 back ++ * to back setup packets) ++ * - In DMA mode, DOEPDMA0 Register with a memory address to ++ * store any setup packets received ++ * At this point, all the required initialization, except for enabling ++ * the control 0 OUT endpoint is done, for receiving SETUP packets. ++ */ ++int32_t dwc_otg_pcd_handle_usb_reset_intr(dwc_otg_pcd_t * pcd) ++{ ++ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); ++ dwc_otg_dev_if_t *dev_if = core_if->dev_if; ++ depctl_data_t doepctl = {.d32 = 0 }; ++ daint_data_t daintmsk = {.d32 = 0 }; ++ doepmsk_data_t doepmsk = {.d32 = 0 }; ++ diepmsk_data_t diepmsk = {.d32 = 0 }; ++ dcfg_data_t dcfg = {.d32 = 0 }; ++ grstctl_t resetctl = {.d32 = 0 }; ++ dctl_data_t dctl = {.d32 = 0 }; ++ int i = 0; ++ gintsts_data_t gintsts; ++ pcgcctl_data_t power = {.d32 = 0 }; ++ ++ power.d32 = dwc_read_reg32(core_if->pcgcctl); ++ if (power.b.stoppclk) { ++ power.d32 = 0; ++ power.b.stoppclk = 1; ++ dwc_modify_reg32(core_if->pcgcctl, power.d32, 0); ++ ++ power.b.pwrclmp = 1; ++ dwc_modify_reg32(core_if->pcgcctl, power.d32, 0); ++ ++ power.b.rstpdwnmodule = 1; ++ dwc_modify_reg32(core_if->pcgcctl, power.d32, 0); ++ } ++ ++ core_if->lx_state = DWC_OTG_L0; ++ ++ DWC_PRINTF("USB RESET\n"); ++#ifdef DWC_EN_ISOC ++ for (i = 1; i < 16; ++i) { ++ dwc_otg_pcd_ep_t *ep; ++ dwc_ep_t *dwc_ep; ++ ep = get_in_ep(pcd, i); ++ if (ep != 0) { ++ dwc_ep = &ep->dwc_ep; ++ dwc_ep->next_frame = 0xffffffff; ++ } ++ } ++#endif /* DWC_EN_ISOC */ ++ ++ /* reset the HNP settings */ ++ dwc_otg_pcd_update_otg(pcd, 1); ++ ++ /* Clear the Remote Wakeup Signalling */ ++ dctl.b.rmtwkupsig = 1; ++ dwc_modify_reg32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32, 0); ++ ++ /* Set NAK for all OUT EPs */ ++ doepctl.b.snak = 1; ++ for (i = 0; i <= dev_if->num_out_eps; i++) { ++ dwc_write_reg32(&dev_if->out_ep_regs[i]->doepctl, doepctl.d32); ++ } ++ ++ /* Flush the NP Tx FIFO */ ++ dwc_otg_flush_tx_fifo(core_if, 0x10); ++ /* Flush the Learning Queue */ ++ resetctl.b.intknqflsh = 1; ++ dwc_write_reg32(&core_if->core_global_regs->grstctl, resetctl.d32); ++ ++ if (core_if->multiproc_int_enable) { ++ daintmsk.b.inep0 = 1; ++ daintmsk.b.outep0 = 1; ++ dwc_write_reg32(&dev_if->dev_global_regs->deachintmsk, ++ daintmsk.d32); ++ ++ doepmsk.b.setup = 1; ++ doepmsk.b.xfercompl = 1; ++ doepmsk.b.ahberr = 1; ++ doepmsk.b.epdisabled = 1; ++ ++ if (core_if->dma_desc_enable) { ++ doepmsk.b.stsphsercvd = 1; ++ doepmsk.b.bna = 1; ++ } ++/* ++ doepmsk.b.babble = 1; ++ doepmsk.b.nyet = 1; ++ ++ if(core_if->dma_enable) { ++ doepmsk.b.nak = 1; ++ } ++*/ ++ dwc_write_reg32(&dev_if->dev_global_regs->doepeachintmsk[0], ++ doepmsk.d32); ++ ++ diepmsk.b.xfercompl = 1; ++ diepmsk.b.timeout = 1; ++ diepmsk.b.epdisabled = 1; ++ diepmsk.b.ahberr = 1; ++ diepmsk.b.intknepmis = 1; ++ ++ if (core_if->dma_desc_enable) { ++ diepmsk.b.bna = 1; ++ } ++/* ++ if(core_if->dma_enable) { ++ diepmsk.b.nak = 1; ++ } ++*/ ++ dwc_write_reg32(&dev_if->dev_global_regs->diepeachintmsk[0], ++ diepmsk.d32); ++ } else { ++ daintmsk.b.inep0 = 1; ++ daintmsk.b.outep0 = 1; ++ dwc_write_reg32(&dev_if->dev_global_regs->daintmsk, ++ daintmsk.d32); ++ ++ doepmsk.b.setup = 1; ++ doepmsk.b.xfercompl = 1; ++ doepmsk.b.ahberr = 1; ++ doepmsk.b.epdisabled = 1; ++ ++ if (core_if->dma_desc_enable) { ++ doepmsk.b.stsphsercvd = 1; ++ doepmsk.b.bna = 1; ++ } ++ dwc_write_reg32(&dev_if->dev_global_regs->doepmsk, doepmsk.d32); ++ ++ diepmsk.b.xfercompl = 1; ++ diepmsk.b.timeout = 1; ++ diepmsk.b.epdisabled = 1; ++ diepmsk.b.ahberr = 1; ++ diepmsk.b.intknepmis = 1; ++ ++ if (core_if->dma_desc_enable) { ++ diepmsk.b.bna = 1; ++ } ++ ++ dwc_write_reg32(&dev_if->dev_global_regs->diepmsk, diepmsk.d32); ++ } ++ ++ /* Reset Device Address */ ++ dcfg.d32 = dwc_read_reg32(&dev_if->dev_global_regs->dcfg); ++ dcfg.b.devaddr = 0; ++ dwc_write_reg32(&dev_if->dev_global_regs->dcfg, dcfg.d32); ++ ++ /* setup EP0 to receive SETUP packets */ ++ ep0_out_start(core_if, pcd); ++ ++ /* Clear interrupt */ ++ gintsts.d32 = 0; ++ gintsts.b.usbreset = 1; ++ dwc_write_reg32(&core_if->core_global_regs->gintsts, gintsts.d32); ++ ++ return 1; ++} ++ ++/** ++ * Get the device speed from the device status register and convert it ++ * to USB speed constant. ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ */ ++static int get_device_speed(dwc_otg_core_if_t * core_if) ++{ ++ dsts_data_t dsts; ++ int speed = 0; ++ dsts.d32 = dwc_read_reg32(&core_if->dev_if->dev_global_regs->dsts); ++ ++ switch (dsts.b.enumspd) { ++ case DWC_DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ: ++ speed = USB_SPEED_HIGH; ++ break; ++ case DWC_DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ: ++ case DWC_DSTS_ENUMSPD_FS_PHY_48MHZ: ++ speed = USB_SPEED_FULL; ++ break; ++ ++ case DWC_DSTS_ENUMSPD_LS_PHY_6MHZ: ++ speed = USB_SPEED_LOW; ++ break; ++ } ++ ++ return speed; ++} ++ ++/** ++ * Read the device status register and set the device speed in the ++ * data structure. ++ * Set up EP0 to receive SETUP packets by calling dwc_ep0_activate. ++ */ ++int32_t dwc_otg_pcd_handle_enum_done_intr(dwc_otg_pcd_t * pcd) ++{ ++ dwc_otg_pcd_ep_t *ep0 = &pcd->ep0; ++ gintsts_data_t gintsts; ++ gusbcfg_data_t gusbcfg; ++ dwc_otg_core_global_regs_t *global_regs = ++ GET_CORE_IF(pcd)->core_global_regs; ++ uint8_t utmi16b, utmi8b; ++ int speed; ++ DWC_DEBUGPL(DBG_PCD, "SPEED ENUM\n"); ++ ++ if (GET_CORE_IF(pcd)->snpsid >= OTG_CORE_REV_2_60a) { ++ utmi16b = 6; ++ utmi8b = 9; ++ } else { ++ utmi16b = 4; ++ utmi8b = 8; ++ } ++ dwc_otg_ep0_activate(GET_CORE_IF(pcd), &ep0->dwc_ep); ++ ++#ifdef DEBUG_EP0 ++ print_ep0_state(pcd); ++#endif ++ ++ if (pcd->ep0state == EP0_DISCONNECT) { ++ pcd->ep0state = EP0_IDLE; ++ } else if (pcd->ep0state == EP0_STALL) { ++ pcd->ep0state = EP0_IDLE; ++ } ++ ++ pcd->ep0state = EP0_IDLE; ++ ++ ep0->stopped = 0; ++ ++ speed = get_device_speed(GET_CORE_IF(pcd)); ++ pcd->fops->connect(pcd, speed); ++ ++ /* Set USB turnaround time based on device speed and PHY interface. */ ++ gusbcfg.d32 = dwc_read_reg32(&global_regs->gusbcfg); ++ if (speed == USB_SPEED_HIGH) { ++ if (GET_CORE_IF(pcd)->hwcfg2.b.hs_phy_type == ++ DWC_HWCFG2_HS_PHY_TYPE_ULPI) { ++ /* ULPI interface */ ++ gusbcfg.b.usbtrdtim = 9; ++ } ++ if (GET_CORE_IF(pcd)->hwcfg2.b.hs_phy_type == ++ DWC_HWCFG2_HS_PHY_TYPE_UTMI) { ++ /* UTMI+ interface */ ++ if (GET_CORE_IF(pcd)->hwcfg4.b.utmi_phy_data_width == 0) { ++ gusbcfg.b.usbtrdtim = utmi8b; ++ } else if (GET_CORE_IF(pcd)->hwcfg4.b. ++ utmi_phy_data_width == 1) { ++ gusbcfg.b.usbtrdtim = utmi16b; ++ } else if (GET_CORE_IF(pcd)->core_params-> ++ phy_utmi_width == 8) { ++ gusbcfg.b.usbtrdtim = utmi8b; ++ } else { ++ gusbcfg.b.usbtrdtim = utmi16b; ++ } ++ } ++ if (GET_CORE_IF(pcd)->hwcfg2.b.hs_phy_type == ++ DWC_HWCFG2_HS_PHY_TYPE_UTMI_ULPI) { ++ /* UTMI+ OR ULPI interface */ ++ if (gusbcfg.b.ulpi_utmi_sel == 1) { ++ /* ULPI interface */ ++ gusbcfg.b.usbtrdtim = 9; ++ } else { ++ /* UTMI+ interface */ ++ if (GET_CORE_IF(pcd)->core_params-> ++ phy_utmi_width == 16) { ++ gusbcfg.b.usbtrdtim = utmi16b; ++ } else { ++ gusbcfg.b.usbtrdtim = utmi8b; ++ } ++ } ++ } ++ } else { ++ /* Full or low speed */ ++ gusbcfg.b.usbtrdtim = 9; ++ } ++ dwc_write_reg32(&global_regs->gusbcfg, gusbcfg.d32); ++ ++ /* Clear interrupt */ ++ gintsts.d32 = 0; ++ gintsts.b.enumdone = 1; ++ dwc_write_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintsts, ++ gintsts.d32); ++ return 1; ++} ++ ++/** ++ * This interrupt indicates that the ISO OUT Packet was dropped due to ++ * Rx FIFO full or Rx Status Queue Full. If this interrupt occurs ++ * read all the data from the Rx FIFO. ++ */ ++int32_t dwc_otg_pcd_handle_isoc_out_packet_dropped_intr(dwc_otg_pcd_t * pcd) ++{ ++ gintmsk_data_t intr_mask = {.d32 = 0 }; ++ gintsts_data_t gintsts; ++ ++ DWC_PRINTF("INTERRUPT Handler not implemented for %s\n", ++ "ISOC Out Dropped"); ++ ++ intr_mask.b.isooutdrop = 1; ++ dwc_modify_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk, ++ intr_mask.d32, 0); ++ ++ /* Clear interrupt */ ++ gintsts.d32 = 0; ++ gintsts.b.isooutdrop = 1; ++ dwc_write_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintsts, ++ gintsts.d32); ++ ++ return 1; ++} ++ ++/** ++ * This interrupt indicates the end of the portion of the micro-frame ++ * for periodic transactions. If there is a periodic transaction for ++ * the next frame, load the packets into the EP periodic Tx FIFO. ++ */ ++int32_t dwc_otg_pcd_handle_end_periodic_frame_intr(dwc_otg_pcd_t * pcd) ++{ ++ gintmsk_data_t intr_mask = {.d32 = 0 }; ++ gintsts_data_t gintsts; ++ DWC_PRINTF("INTERRUPT Handler not implemented for %s\n", "EOP"); ++ ++ intr_mask.b.eopframe = 1; ++ dwc_modify_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk, ++ intr_mask.d32, 0); ++ ++ /* Clear interrupt */ ++ gintsts.d32 = 0; ++ gintsts.b.eopframe = 1; ++ dwc_write_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintsts, ++ gintsts.d32); ++ ++ return 1; ++} ++ ++/** ++ * This interrupt indicates that EP of the packet on the top of the ++ * non-periodic Tx FIFO does not match EP of the IN Token received. ++ * ++ * The "Device IN Token Queue" Registers are read to determine the ++ * order the IN Tokens have been received. The non-periodic Tx FIFO ++ * is flushed, so it can be reloaded in the order seen in the IN Token ++ * Queue. ++ */ ++int32_t dwc_otg_pcd_handle_ep_mismatch_intr(dwc_otg_core_if_t * core_if) ++{ ++ gintsts_data_t gintsts; ++ DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, core_if); ++ ++ /* Clear interrupt */ ++ gintsts.d32 = 0; ++ gintsts.b.epmismatch = 1; ++ dwc_write_reg32(&core_if->core_global_regs->gintsts, gintsts.d32); ++ ++ return 1; ++} ++ ++/** ++ * This funcion stalls EP0. ++ */ ++static inline void ep0_do_stall(dwc_otg_pcd_t * pcd, const int err_val) ++{ ++ dwc_otg_pcd_ep_t *ep0 = &pcd->ep0; ++ usb_device_request_t *ctrl = &pcd->setup_pkt->req; ++ DWC_WARN("req %02x.%02x protocol STALL; err %d\n", ++ ctrl->bmRequestType, ctrl->bRequest, err_val); ++ ++ ep0->dwc_ep.is_in = 1; ++ dwc_otg_ep_set_stall(GET_CORE_IF(pcd), &ep0->dwc_ep); ++ pcd->ep0.stopped = 1; ++ pcd->ep0state = EP0_IDLE; ++ ep0_out_start(GET_CORE_IF(pcd), pcd); ++} ++ ++/** ++ * This functions delegates the setup command to the gadget driver. ++ */ ++static inline void do_gadget_setup(dwc_otg_pcd_t * pcd, ++ usb_device_request_t * ctrl) ++{ ++ int ret = 0; ++ DWC_SPINUNLOCK(pcd->lock); ++ ret = pcd->fops->setup(pcd, (uint8_t *) ctrl); ++ DWC_SPINLOCK(pcd->lock); ++ if (ret < 0) { ++ ep0_do_stall(pcd, ret); ++ } ++ ++ /** @todo This is a g_file_storage gadget driver specific ++ * workaround: a DELAYED_STATUS result from the fsg_setup ++ * routine will result in the gadget queueing a EP0 IN status ++ * phase for a two-stage control transfer. Exactly the same as ++ * a SET_CONFIGURATION/SET_INTERFACE except that this is a class ++ * specific request. Need a generic way to know when the gadget ++ * driver will queue the status phase. Can we assume when we ++ * call the gadget driver setup() function that it will always ++ * queue and require the following flag? Need to look into ++ * this. ++ */ ++ ++ if (ret == 256 + 999) { ++ pcd->request_config = 1; ++ } ++} ++ ++#ifdef DWC_UTE_CFI ++/** ++ * This functions delegates the CFI setup commands to the gadget driver. ++ * This function will return a negative value to indicate a failure. ++ */ ++static inline int cfi_gadget_setup(dwc_otg_pcd_t * pcd, ++ struct cfi_usb_ctrlrequest *ctrl_req) ++{ ++ int ret = 0; ++ ++ if (pcd->fops && pcd->fops->cfi_setup) { ++ DWC_SPINUNLOCK(pcd->lock); ++ ret = pcd->fops->cfi_setup(pcd, ctrl_req); ++ DWC_SPINLOCK(pcd->lock); ++ if (ret < 0) { ++ ep0_do_stall(pcd, ret); ++ return ret; ++ } ++ } ++ ++ return ret; ++} ++#endif ++ ++/** ++ * This function starts the Zero-Length Packet for the IN status phase ++ * of a 2 stage control transfer. ++ */ ++static inline void do_setup_in_status_phase(dwc_otg_pcd_t * pcd) ++{ ++ dwc_otg_pcd_ep_t *ep0 = &pcd->ep0; ++ if (pcd->ep0state == EP0_STALL) { ++ return; ++ } ++ ++ pcd->ep0state = EP0_IN_STATUS_PHASE; ++ ++ /* Prepare for more SETUP Packets */ ++ DWC_DEBUGPL(DBG_PCD, "EP0 IN ZLP\n"); ++ ep0->dwc_ep.xfer_len = 0; ++ ep0->dwc_ep.xfer_count = 0; ++ ep0->dwc_ep.is_in = 1; ++ ep0->dwc_ep.dma_addr = pcd->setup_pkt_dma_handle; ++ dwc_otg_ep0_start_transfer(GET_CORE_IF(pcd), &ep0->dwc_ep); ++ ++ /* Prepare for more SETUP Packets */ ++ //ep0_out_start(GET_CORE_IF(pcd), pcd); ++} ++ ++/** ++ * This function starts the Zero-Length Packet for the OUT status phase ++ * of a 2 stage control transfer. ++ */ ++static inline void do_setup_out_status_phase(dwc_otg_pcd_t * pcd) ++{ ++ dwc_otg_pcd_ep_t *ep0 = &pcd->ep0; ++ if (pcd->ep0state == EP0_STALL) { ++ DWC_DEBUGPL(DBG_PCD, "EP0 STALLED\n"); ++ return; ++ } ++ pcd->ep0state = EP0_OUT_STATUS_PHASE; ++ ++ DWC_DEBUGPL(DBG_PCD, "EP0 OUT ZLP\n"); ++ ep0->dwc_ep.xfer_len = 0; ++ ep0->dwc_ep.xfer_count = 0; ++ ep0->dwc_ep.is_in = 0; ++ ep0->dwc_ep.dma_addr = pcd->setup_pkt_dma_handle; ++ dwc_otg_ep0_start_transfer(GET_CORE_IF(pcd), &ep0->dwc_ep); ++ ++ /* Prepare for more SETUP Packets */ ++ if (GET_CORE_IF(pcd)->dma_enable == 0) { ++ ep0_out_start(GET_CORE_IF(pcd), pcd); ++ } ++} ++ ++/** ++ * Clear the EP halt (STALL) and if pending requests start the ++ * transfer. ++ */ ++static inline void pcd_clear_halt(dwc_otg_pcd_t * pcd, dwc_otg_pcd_ep_t * ep) ++{ ++ if (ep->dwc_ep.stall_clear_flag == 0) ++ dwc_otg_ep_clear_stall(GET_CORE_IF(pcd), &ep->dwc_ep); ++ ++ /* Reactive the EP */ ++ dwc_otg_ep_activate(GET_CORE_IF(pcd), &ep->dwc_ep); ++ if (ep->stopped) { ++ ep->stopped = 0; ++ /* If there is a request in the EP queue start it */ ++ ++ /** @todo FIXME: this causes an EP mismatch in DMA mode. ++ * epmismatch not yet implemented. */ ++ ++ /* ++ * Above fixme is solved by implmenting a tasklet to call the ++ * start_next_request(), outside of interrupt context at some ++ * time after the current time, after a clear-halt setup packet. ++ * Still need to implement ep mismatch in the future if a gadget ++ * ever uses more than one endpoint at once ++ */ ++ ep->queue_sof = 1; ++ DWC_TASK_SCHEDULE(pcd->start_xfer_tasklet); ++ } ++ /* Start Control Status Phase */ ++ do_setup_in_status_phase(pcd); ++} ++ ++/** ++ * This function is called when the SET_FEATURE TEST_MODE Setup packet ++ * is sent from the host. The Device Control register is written with ++ * the Test Mode bits set to the specified Test Mode. This is done as ++ * a tasklet so that the "Status" phase of the control transfer ++ * completes before transmitting the TEST packets. ++ * ++ * @todo This has not been tested since the tasklet struct was put ++ * into the PCD struct! ++ * ++ */ ++void do_test_mode(void *data) ++{ ++ dctl_data_t dctl; ++ dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *) data; ++ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); ++ int test_mode = pcd->test_mode; ++ ++// DWC_WARN("%s() has not been tested since being rewritten!\n", __func__); ++ ++ dctl.d32 = dwc_read_reg32(&core_if->dev_if->dev_global_regs->dctl); ++ switch (test_mode) { ++ case 1: // TEST_J ++ dctl.b.tstctl = 1; ++ break; ++ ++ case 2: // TEST_K ++ dctl.b.tstctl = 2; ++ break; ++ ++ case 3: // TEST_SE0_NAK ++ dctl.b.tstctl = 3; ++ break; ++ ++ case 4: // TEST_PACKET ++ dctl.b.tstctl = 4; ++ break; ++ ++ case 5: // TEST_FORCE_ENABLE ++ dctl.b.tstctl = 5; ++ break; ++ } ++ dwc_write_reg32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32); ++} ++ ++/** ++ * This function process the GET_STATUS Setup Commands. ++ */ ++static inline void do_get_status(dwc_otg_pcd_t * pcd) ++{ ++ usb_device_request_t ctrl = pcd->setup_pkt->req; ++ dwc_otg_pcd_ep_t *ep; ++ dwc_otg_pcd_ep_t *ep0 = &pcd->ep0; ++ uint16_t *status = pcd->status_buf; ++ ++#ifdef DEBUG_EP0 ++ DWC_DEBUGPL(DBG_PCD, ++ "GET_STATUS %02x.%02x v%04x i%04x l%04x\n", ++ ctrl.bmRequestType, ctrl.bRequest, ++ UGETW(ctrl.wValue), UGETW(ctrl.wIndex), ++ UGETW(ctrl.wLength)); ++#endif ++ ++ switch (UT_GET_RECIPIENT(ctrl.bmRequestType)) { ++ case UT_DEVICE: ++ *status = 0x1; /* Self powered */ ++ *status |= pcd->remote_wakeup_enable << 1; ++ break; ++ ++ case UT_INTERFACE: ++ *status = 0; ++ break; ++ ++ case UT_ENDPOINT: ++ ep = get_ep_by_addr(pcd, UGETW(ctrl.wIndex)); ++ if (ep == 0 || UGETW(ctrl.wLength) > 2) { ++ ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED); ++ return; ++ } ++ /** @todo check for EP stall */ ++ *status = ep->stopped; ++ break; ++ } ++ pcd->ep0_pending = 1; ++ ep0->dwc_ep.start_xfer_buff = (uint8_t *) status; ++ ep0->dwc_ep.xfer_buff = (uint8_t *) status; ++ ep0->dwc_ep.dma_addr = pcd->status_buf_dma_handle; ++ ep0->dwc_ep.xfer_len = 2; ++ ep0->dwc_ep.xfer_count = 0; ++ ep0->dwc_ep.total_len = ep0->dwc_ep.xfer_len; ++ dwc_otg_ep0_start_transfer(GET_CORE_IF(pcd), &ep0->dwc_ep); ++} ++ ++/** ++ * This function process the SET_FEATURE Setup Commands. ++ */ ++static inline void do_set_feature(dwc_otg_pcd_t * pcd) ++{ ++ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); ++ dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs; ++ usb_device_request_t ctrl = pcd->setup_pkt->req; ++ dwc_otg_pcd_ep_t *ep = 0; ++ int32_t otg_cap_param = core_if->core_params->otg_cap; ++ gotgctl_data_t gotgctl = {.d32 = 0 }; ++ ++ DWC_DEBUGPL(DBG_PCD, "SET_FEATURE:%02x.%02x v%04x i%04x l%04x\n", ++ ctrl.bmRequestType, ctrl.bRequest, ++ UGETW(ctrl.wValue), UGETW(ctrl.wIndex), ++ UGETW(ctrl.wLength)); ++ DWC_DEBUGPL(DBG_PCD, "otg_cap=%d\n", otg_cap_param); ++ ++ switch (UT_GET_RECIPIENT(ctrl.bmRequestType)) { ++ case UT_DEVICE: ++ switch (UGETW(ctrl.wValue)) { ++ case UF_DEVICE_REMOTE_WAKEUP: ++ pcd->remote_wakeup_enable = 1; ++ break; ++ ++ case UF_TEST_MODE: ++ /* Setup the Test Mode tasklet to do the Test ++ * Packet generation after the SETUP Status ++ * phase has completed. */ ++ ++ /** @todo This has not been tested since the ++ * tasklet struct was put into the PCD ++ * struct! */ ++ pcd->test_mode = UGETW(ctrl.wIndex) >> 8; ++ DWC_TASK_SCHEDULE(pcd->test_mode_tasklet); ++ break; ++ ++ case UF_DEVICE_B_HNP_ENABLE: ++ DWC_DEBUGPL(DBG_PCDV, ++ "SET_FEATURE: USB_DEVICE_B_HNP_ENABLE\n"); ++ ++ /* dev may initiate HNP */ ++ if (otg_cap_param == DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE) { ++ pcd->b_hnp_enable = 1; ++ dwc_otg_pcd_update_otg(pcd, 0); ++ DWC_DEBUGPL(DBG_PCD, "Request B HNP\n"); ++ /**@todo Is the gotgctl.devhnpen cleared ++ * by a USB Reset? */ ++ gotgctl.b.devhnpen = 1; ++ gotgctl.b.hnpreq = 1; ++ dwc_write_reg32(&global_regs->gotgctl, ++ gotgctl.d32); ++ } else { ++ ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED); ++ } ++ break; ++ ++ case UF_DEVICE_A_HNP_SUPPORT: ++ /* RH port supports HNP */ ++ DWC_DEBUGPL(DBG_PCDV, ++ "SET_FEATURE: USB_DEVICE_A_HNP_SUPPORT\n"); ++ if (otg_cap_param == DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE) { ++ pcd->a_hnp_support = 1; ++ dwc_otg_pcd_update_otg(pcd, 0); ++ } else { ++ ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED); ++ } ++ break; ++ ++ case UF_DEVICE_A_ALT_HNP_SUPPORT: ++ /* other RH port does */ ++ DWC_DEBUGPL(DBG_PCDV, ++ "SET_FEATURE: USB_DEVICE_A_ALT_HNP_SUPPORT\n"); ++ if (otg_cap_param == DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE) { ++ pcd->a_alt_hnp_support = 1; ++ dwc_otg_pcd_update_otg(pcd, 0); ++ } else { ++ ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED); ++ } ++ break; ++ } ++ do_setup_in_status_phase(pcd); ++ break; ++ ++ case UT_INTERFACE: ++ do_gadget_setup(pcd, &ctrl); ++ break; ++ ++ case UT_ENDPOINT: ++ if (UGETW(ctrl.wValue) == UF_ENDPOINT_HALT) { ++ ep = get_ep_by_addr(pcd, UGETW(ctrl.wIndex)); ++ if (ep == 0) { ++ ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED); ++ return; ++ } ++ ep->stopped = 1; ++ dwc_otg_ep_set_stall(core_if, &ep->dwc_ep); ++ } ++ do_setup_in_status_phase(pcd); ++ break; ++ } ++} ++ ++/** ++ * This function process the CLEAR_FEATURE Setup Commands. ++ */ ++static inline void do_clear_feature(dwc_otg_pcd_t * pcd) ++{ ++ usb_device_request_t ctrl = pcd->setup_pkt->req; ++ dwc_otg_pcd_ep_t *ep = 0; ++ ++ DWC_DEBUGPL(DBG_PCD, ++ "CLEAR_FEATURE:%02x.%02x v%04x i%04x l%04x\n", ++ ctrl.bmRequestType, ctrl.bRequest, ++ UGETW(ctrl.wValue), UGETW(ctrl.wIndex), ++ UGETW(ctrl.wLength)); ++ ++ switch (UT_GET_RECIPIENT(ctrl.bmRequestType)) { ++ case UT_DEVICE: ++ switch (UGETW(ctrl.wValue)) { ++ case UF_DEVICE_REMOTE_WAKEUP: ++ pcd->remote_wakeup_enable = 0; ++ break; ++ ++ case UF_TEST_MODE: ++ /** @todo Add CLEAR_FEATURE for TEST modes. */ ++ break; ++ } ++ do_setup_in_status_phase(pcd); ++ break; ++ ++ case UT_ENDPOINT: ++ ep = get_ep_by_addr(pcd, UGETW(ctrl.wIndex)); ++ if (ep == 0) { ++ ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED); ++ return; ++ } ++ ++ pcd_clear_halt(pcd, ep); ++ ++ break; ++ } ++} ++ ++/** ++ * This function process the SET_ADDRESS Setup Commands. ++ */ ++static inline void do_set_address(dwc_otg_pcd_t * pcd) ++{ ++ dwc_otg_dev_if_t *dev_if = GET_CORE_IF(pcd)->dev_if; ++ usb_device_request_t ctrl = pcd->setup_pkt->req; ++ ++ if (ctrl.bmRequestType == UT_DEVICE) { ++ dcfg_data_t dcfg = {.d32 = 0 }; ++ ++#ifdef DEBUG_EP0 ++// DWC_DEBUGPL(DBG_PCDV, "SET_ADDRESS:%d\n", ctrl.wValue); ++#endif ++ dcfg.b.devaddr = UGETW(ctrl.wValue); ++ dwc_modify_reg32(&dev_if->dev_global_regs->dcfg, 0, dcfg.d32); ++ do_setup_in_status_phase(pcd); ++ } ++} ++ ++/** ++ * This function processes SETUP commands. In Linux, the USB Command ++ * processing is done in two places - the first being the PCD and the ++ * second in the Gadget Driver (for example, the File-Backed Storage ++ * Gadget Driver). ++ * ++ *
Parameter NameMeaning
otg_capSpecifies the OTG capabilities. The driver will automatically detect the ++ value for this parameter if none is specified. ++ - 0: HNP and SRP capable (default, if available) ++ - 1: SRP Only capable ++ - 2: No HNP/SRP capable ++
dma_enableSpecifies whether to use slave or DMA mode for accessing the data FIFOs. ++ The driver will automatically detect the value for this parameter if none is ++ specified. ++ - 0: Slave ++ - 1: DMA (default, if available) ++
dma_burst_sizeThe DMA Burst size (applicable only for External DMA Mode). ++ - Values: 1, 4, 8 16, 32, 64, 128, 256 (default 32) ++
speedSpecifies the maximum speed of operation in host and device mode. The ++ actual speed depends on the speed of the attached device and the value of ++ phy_type. ++ - 0: High Speed (default) ++ - 1: Full Speed ++
host_support_fs_ls_low_powerSpecifies whether low power mode is supported when attached to a Full ++ Speed or Low Speed device in host mode. ++ - 0: Don't support low power mode (default) ++ - 1: Support low power mode ++
host_ls_low_power_phy_clkSpecifies the PHY clock rate in low power mode when connected to a Low ++ Speed device in host mode. This parameter is applicable only if ++ HOST_SUPPORT_FS_LS_LOW_POWER is enabled. ++ - 0: 48 MHz (default) ++ - 1: 6 MHz ++
enable_dynamic_fifo Specifies whether FIFOs may be resized by the driver software. ++ - 0: Use cC FIFO size parameters ++ - 1: Allow dynamic FIFO sizing (default) ++
data_fifo_sizeTotal number of 4-byte words in the data FIFO memory. This memory ++ includes the Rx FIFO, non-periodic Tx FIFO, and periodic Tx FIFOs. ++ - Values: 32 to 32768 (default 8192) ++ ++ Note: The total FIFO memory depth in the FPGA configuration is 8192. ++
dev_rx_fifo_sizeNumber of 4-byte words in the Rx FIFO in device mode when dynamic ++ FIFO sizing is enabled. ++ - Values: 16 to 32768 (default 1064) ++
dev_nperio_tx_fifo_sizeNumber of 4-byte words in the non-periodic Tx FIFO in device mode when ++ dynamic FIFO sizing is enabled. ++ - Values: 16 to 32768 (default 1024) ++
dev_perio_tx_fifo_size_n (n = 1 to 15)Number of 4-byte words in each of the periodic Tx FIFOs in device mode ++ when dynamic FIFO sizing is enabled. ++ - Values: 4 to 768 (default 256) ++
host_rx_fifo_sizeNumber of 4-byte words in the Rx FIFO in host mode when dynamic FIFO ++ sizing is enabled. ++ - Values: 16 to 32768 (default 1024) ++
host_nperio_tx_fifo_sizeNumber of 4-byte words in the non-periodic Tx FIFO in host mode when ++ dynamic FIFO sizing is enabled in the core. ++ - Values: 16 to 32768 (default 1024) ++
host_perio_tx_fifo_sizeNumber of 4-byte words in the host periodic Tx FIFO when dynamic FIFO ++ sizing is enabled. ++ - Values: 16 to 32768 (default 1024) ++
max_transfer_sizeThe maximum transfer size supported in bytes. ++ - Values: 2047 to 65,535 (default 65,535) ++
max_packet_countThe maximum number of packets in a transfer. ++ - Values: 15 to 511 (default 511) ++
host_channelsThe number of host channel registers to use. ++ - Values: 1 to 16 (default 12) ++ ++ Note: The FPGA configuration supports a maximum of 12 host channels. ++
dev_endpointsThe number of endpoints in addition to EP0 available for device mode ++ operations. ++ - Values: 1 to 15 (default 6 IN and OUT) ++ ++ Note: The FPGA configuration supports a maximum of 6 IN and OUT endpoints in ++ addition to EP0. ++
phy_typeSpecifies the type of PHY interface to use. By default, the driver will ++ automatically detect the phy_type. ++ - 0: Full Speed ++ - 1: UTMI+ (default, if available) ++ - 2: ULPI ++
phy_utmi_widthSpecifies the UTMI+ Data Width. This parameter is applicable for a ++ phy_type of UTMI+. Also, this parameter is applicable only if the ++ OTG_HSPHY_WIDTH cC parameter was set to "8 and 16 bits", meaning that the ++ core has been configured to work at either data path width. ++ - Values: 8 or 16 bits (default 16) ++
phy_ulpi_ddrSpecifies whether the ULPI operates at double or single data rate. This ++ parameter is only applicable if phy_type is ULPI. ++ - 0: single data rate ULPI interface with 8 bit wide data bus (default) ++ - 1: double data rate ULPI interface with 4 bit wide data bus ++
i2c_enableSpecifies whether to use the I2C interface for full speed PHY. This ++ parameter is only applicable if PHY_TYPE is FS. ++ - 0: Disabled (default) ++ - 1: Enabled ++
otg_en_multiple_tx_fifoSpecifies whether dedicatedto tx fifos are enabled for non periodic IN EPs. ++ The driver will automatically detect the value for this parameter if none is ++ specified. ++ - 0: Disabled ++ - 1: Enabled (default, if available) ++
dev_tx_fifo_size_n (n = 1 to 15)Number of 4-byte words in each of the Tx FIFOs in device mode ++ when dynamic FIFO sizing is enabled. ++ - Values: 4 to 768 (default 256) ++
tx_thr_lengthTransmit Threshold length in 32 bit double words ++ - Values: 8 to 128 (default 64) ++
rx_thr_lengthReceive Threshold length in 32 bit double words ++ - Values: 8 to 128 (default 64) ++
thr_ctlSpecifies whether to enable Thresholding for Device mode. Bits 0, 1, 2 of this ++ parmater specifies if thresholding is enabled for non-Iso Tx, Iso Tx and Rx ++ transfers accordingly. ++ The driver will automatically detect the value for this parameter if none is ++ specified. ++ - Values: 0 to 7 (default 0) ++ Bit values indicate: ++ - 0: Thresholding disabled ++ - 1: Thresholding enabled ++
dma_desc_enableSpecifies whether to enable Descriptor DMA mode. ++ The driver will automatically detect the value for this parameter if none is ++ specified. ++ - 0: Descriptor DMA disabled ++ - 1: Descriptor DMA (default, if available) ++
mpi_enableSpecifies whether to enable MPI enhancement mode. ++ The driver will automatically detect the value for this parameter if none is ++ specified. ++ - 0: MPI disabled (default) ++ - 1: MPI enable ++
pti_enableSpecifies whether to enable PTI enhancement support. ++ The driver will automatically detect the value for this parameter if none is ++ specified. ++ - 0: PTI disabled (default) ++ - 1: PTI enable ++
lpm_enableSpecifies whether to enable LPM support. ++ The driver will automatically detect the value for this parameter if none is ++ specified. ++ - 0: LPM disabled ++ - 1: LPM enable (default, if available) ++
ahb_thr_ratioSpecifies AHB Threshold ratio. ++ - Values: 0 to 3 (default 0) ++
++ * ++ * ++ * ++ * ++ * ++ * ++ * ++ * ++ * ++ * ++ * ++ * ++ * ++ * ++ * ++ * ++ * ++ * ++ * ++ * ++ * ++ * ++ * ++ *
Command Driver Description
GET_STATUS PCD Command is processed as ++ * defined in chapter 9 of the USB 2.0 Specification chapter 9 ++ *
CLEAR_FEATURE PCD The Device and Endpoint ++ * requests are the ENDPOINT_HALT feature is procesed, all others the ++ * interface requests are ignored.
SET_FEATURE PCD The Device and Endpoint ++ * requests are processed by the PCD. Interface requests are passed ++ * to the Gadget Driver.
SET_ADDRESS PCD Program the DCFG reg, ++ * with device address received
GET_DESCRIPTOR Gadget Driver Return the ++ * requested descriptor
SET_DESCRIPTOR Gadget Driver Optional - ++ * not implemented by any of the existing Gadget Drivers.
SET_CONFIGURATION Gadget Driver Disable ++ * all EPs and enable EPs for new configuration.
GET_CONFIGURATION Gadget Driver Return ++ * the current configuration
SET_INTERFACE Gadget Driver Disable all ++ * EPs and enable EPs for new configuration.
GET_INTERFACE Gadget Driver Return the ++ * current interface.
SYNC_FRAME PCD Display debug ++ * message.
++ * ++ * When the SETUP Phase Done interrupt occurs, the PCD SETUP commands are ++ * processed by pcd_setup. Calling the Function Driver's setup function from ++ * pcd_setup processes the gadget SETUP commands. ++ */ ++static inline void pcd_setup(dwc_otg_pcd_t * pcd) ++{ ++ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); ++ dwc_otg_dev_if_t *dev_if = core_if->dev_if; ++ usb_device_request_t ctrl = pcd->setup_pkt->req; ++ dwc_otg_pcd_ep_t *ep0 = &pcd->ep0; ++ ++ deptsiz0_data_t doeptsize0 = {.d32 = 0 }; ++ ++#ifdef DWC_UTE_CFI ++ int retval = 0; ++ struct cfi_usb_ctrlrequest cfi_req; ++#endif ++ ++#ifdef DEBUG_EP0 ++ DWC_DEBUGPL(DBG_PCD, "SETUP %02x.%02x v%04x i%04x l%04x\n", ++ ctrl.bmRequestType, ctrl.bRequest, ++ UGETW(ctrl.wValue), UGETW(ctrl.wIndex), ++ UGETW(ctrl.wLength)); ++#endif ++ ++ doeptsize0.d32 = dwc_read_reg32(&dev_if->out_ep_regs[0]->doeptsiz); ++ ++ /** @todo handle > 1 setup packet , assert error for now */ ++ ++ if (core_if->dma_enable && core_if->dma_desc_enable == 0 ++ && (doeptsize0.b.supcnt < 2)) { ++ DWC_ERROR ++ ("\n\n----------- CANNOT handle > 1 setup packet in DMA mode\n\n"); ++ } ++ ++ /* Clean up the request queue */ ++ dwc_otg_request_nuke(ep0); ++ ep0->stopped = 0; ++ ++ if (ctrl.bmRequestType & UE_DIR_IN) { ++ ep0->dwc_ep.is_in = 1; ++ pcd->ep0state = EP0_IN_DATA_PHASE; ++ } else { ++ ep0->dwc_ep.is_in = 0; ++ pcd->ep0state = EP0_OUT_DATA_PHASE; ++ } ++ ++ if (UGETW(ctrl.wLength) == 0) { ++ ep0->dwc_ep.is_in = 1; ++ pcd->ep0state = EP0_IN_STATUS_PHASE; ++ } ++ ++ if (UT_GET_TYPE(ctrl.bmRequestType) != UT_STANDARD) { ++ ++#ifdef DWC_UTE_CFI ++ DWC_MEMCPY(&cfi_req, &ctrl, sizeof(usb_device_request_t)); ++ ++ //printk(KERN_ALERT "CFI: req_type=0x%02x; req=0x%02x\n", ctrl.bRequestType, ctrl.bRequest); ++ if (UT_GET_TYPE(cfi_req.bRequestType) == UT_VENDOR) { ++ if (cfi_req.bRequest > 0xB0 && cfi_req.bRequest < 0xBF) { ++ retval = cfi_setup(pcd, &cfi_req); ++ if (retval < 0) { ++ ep0_do_stall(pcd, retval); ++ pcd->ep0_pending = 0; ++ return; ++ } ++ ++ /* if need gadget setup then call it and check the retval */ ++ if (pcd->cfi->need_gadget_att) { ++ retval = ++ cfi_gadget_setup(pcd, ++ &pcd->cfi-> ++ ctrl_req); ++ if (retval < 0) { ++ pcd->ep0_pending = 0; ++ return; ++ } ++ } ++ ++ if (pcd->cfi->need_status_in_complete) { ++ do_setup_in_status_phase(pcd); ++ } ++ return; ++ } ++ } ++#endif ++ ++ /* handle non-standard (class/vendor) requests in the gadget driver */ ++ do_gadget_setup(pcd, &ctrl); ++ return; ++ } ++ ++ /** @todo NGS: Handle bad setup packet? */ ++ ++/////////////////////////////////////////// ++//// --- Standard Request handling --- //// ++ ++ switch (ctrl.bRequest) { ++ case UR_GET_STATUS: ++ do_get_status(pcd); ++ break; ++ ++ case UR_CLEAR_FEATURE: ++ do_clear_feature(pcd); ++ break; ++ ++ case UR_SET_FEATURE: ++ do_set_feature(pcd); ++ break; ++ ++ case UR_SET_ADDRESS: ++ do_set_address(pcd); ++ break; ++ ++ case UR_SET_INTERFACE: ++ case UR_SET_CONFIG: ++// _pcd->request_config = 1; /* Configuration changed */ ++ do_gadget_setup(pcd, &ctrl); ++ break; ++ ++ case UR_SYNCH_FRAME: ++ do_gadget_setup(pcd, &ctrl); ++ break; ++ ++ default: ++ /* Call the Gadget Driver's setup functions */ ++ do_gadget_setup(pcd, &ctrl); ++ break; ++ } ++} ++ ++/** ++ * This function completes the ep0 control transfer. ++ */ ++static int32_t ep0_complete_request(dwc_otg_pcd_ep_t * ep) ++{ ++ dwc_otg_core_if_t *core_if = GET_CORE_IF(ep->pcd); ++ dwc_otg_dev_if_t *dev_if = core_if->dev_if; ++ dwc_otg_dev_in_ep_regs_t *in_ep_regs = ++ dev_if->in_ep_regs[ep->dwc_ep.num]; ++#ifdef DEBUG_EP0 ++ dwc_otg_dev_out_ep_regs_t *out_ep_regs = ++ dev_if->out_ep_regs[ep->dwc_ep.num]; ++#endif ++ deptsiz0_data_t deptsiz; ++ dev_dma_desc_sts_t desc_sts; ++ dwc_otg_pcd_request_t *req; ++ int is_last = 0; ++ dwc_otg_pcd_t *pcd = ep->pcd; ++ ++#ifdef DWC_UTE_CFI ++ struct cfi_usb_ctrlrequest *ctrlreq; ++ int retval = -DWC_E_NOT_SUPPORTED; ++#endif ++ ++ if (pcd->ep0_pending && DWC_CIRCLEQ_EMPTY(&ep->queue)) { ++ if (ep->dwc_ep.is_in) { ++#ifdef DEBUG_EP0 ++ DWC_DEBUGPL(DBG_PCDV, "Do setup OUT status phase\n"); ++#endif ++ do_setup_out_status_phase(pcd); ++ } else { ++#ifdef DEBUG_EP0 ++ DWC_DEBUGPL(DBG_PCDV, "Do setup IN status phase\n"); ++#endif ++ ++#ifdef DWC_UTE_CFI ++ ctrlreq = &pcd->cfi->ctrl_req; ++ ++ if (UT_GET_TYPE(ctrlreq->bRequestType) == UT_VENDOR) { ++ if (ctrlreq->bRequest > 0xB0 ++ && ctrlreq->bRequest < 0xBF) { ++ ++ /* Return if the PCD failed to handle the request */ ++ if ((retval = ++ pcd->cfi->ops. ++ ctrl_write_complete(pcd->cfi, ++ pcd)) < 0) { ++ CFI_INFO ++ ("ERROR setting a new value in the PCD(%d)\n", ++ retval); ++ ep0_do_stall(pcd, retval); ++ pcd->ep0_pending = 0; ++ return 0; ++ } ++ ++ /* If the gadget needs to be notified on the request */ ++ if (pcd->cfi->need_gadget_att == 1) { ++ //retval = do_gadget_setup(pcd, &pcd->cfi->ctrl_req); ++ retval = ++ cfi_gadget_setup(pcd, ++ &pcd->cfi-> ++ ctrl_req); ++ ++ /* Return from the function if the gadget failed to process ++ * the request properly - this should never happen !!! ++ */ ++ if (retval < 0) { ++ CFI_INFO ++ ("ERROR setting a new value in the gadget(%d)\n", ++ retval); ++ pcd->ep0_pending = 0; ++ return 0; ++ } ++ } ++ ++ CFI_INFO("%s: RETVAL=%d\n", __func__, ++ retval); ++ /* If we hit here then the PCD and the gadget has properly ++ * handled the request - so send the ZLP IN to the host. ++ */ ++ /* @todo: MAS - decide whether we need to start the setup ++ * stage based on the need_setup value of the cfi object ++ */ ++ do_setup_in_status_phase(pcd); ++ pcd->ep0_pending = 0; ++ return 1; ++ } ++ } ++#endif ++ ++ do_setup_in_status_phase(pcd); ++ } ++ pcd->ep0_pending = 0; ++ return 1; ++ } ++ ++ if (DWC_CIRCLEQ_EMPTY(&ep->queue)) { ++ return 0; ++ } ++ req = DWC_CIRCLEQ_FIRST(&ep->queue); ++ ++ if (pcd->ep0state == EP0_OUT_STATUS_PHASE ++ || pcd->ep0state == EP0_IN_STATUS_PHASE) { ++ is_last = 1; ++ } else if (ep->dwc_ep.is_in) { ++ deptsiz.d32 = dwc_read_reg32(&in_ep_regs->dieptsiz); ++ if (core_if->dma_desc_enable != 0) ++ desc_sts = dev_if->in_desc_addr->status; ++#ifdef DEBUG_EP0 ++ DWC_DEBUGPL(DBG_PCDV, "%d len=%d xfersize=%d pktcnt=%d\n", ++ ep->dwc_ep.num, ep->dwc_ep.xfer_len, ++ deptsiz.b.xfersize, deptsiz.b.pktcnt); ++#endif ++ ++ if (((core_if->dma_desc_enable == 0) ++ && (deptsiz.b.xfersize == 0)) ++ || ((core_if->dma_desc_enable != 0) ++ && (desc_sts.b.bytes == 0))) { ++ req->actual = ep->dwc_ep.xfer_count; ++ /* Is a Zero Len Packet needed? */ ++ if (req->sent_zlp) { ++#ifdef DEBUG_EP0 ++ DWC_DEBUGPL(DBG_PCD, "Setup Rx ZLP\n"); ++#endif ++ req->sent_zlp = 0; ++ } ++ do_setup_out_status_phase(pcd); ++ } ++ } else { ++ /* ep0-OUT */ ++#ifdef DEBUG_EP0 ++ deptsiz.d32 = dwc_read_reg32(&out_ep_regs->doeptsiz); ++ DWC_DEBUGPL(DBG_PCDV, "%d len=%d xsize=%d pktcnt=%d\n", ++ ep->dwc_ep.num, ep->dwc_ep.xfer_len, ++ deptsiz.b.xfersize, deptsiz.b.pktcnt); ++#endif ++ req->actual = ep->dwc_ep.xfer_count; ++ ++ /* Is a Zero Len Packet needed? */ ++ if (req->sent_zlp) { ++#ifdef DEBUG_EP0 ++ DWC_DEBUGPL(DBG_PCDV, "Setup Tx ZLP\n"); ++#endif ++ req->sent_zlp = 0; ++ } ++ if (core_if->dma_desc_enable == 0) ++ do_setup_in_status_phase(pcd); ++ } ++ ++ /* Complete the request */ ++ if (is_last) { ++ dwc_otg_request_done(ep, req, 0); ++ ep->dwc_ep.start_xfer_buff = 0; ++ ep->dwc_ep.xfer_buff = 0; ++ ep->dwc_ep.xfer_len = 0; ++ return 1; ++ } ++ return 0; ++} ++ ++#ifdef DWC_UTE_CFI ++/** ++ * This function calculates traverses all the CFI DMA descriptors and ++ * and accumulates the bytes that are left to be transfered. ++ * ++ * @return The total bytes left to transfered, or a negative value as failure ++ */ ++static inline int cfi_calc_desc_residue(dwc_otg_pcd_ep_t * ep) ++{ ++ int32_t ret = 0; ++ int i; ++ struct dwc_otg_dma_desc *ddesc = NULL; ++ struct cfi_ep *cfiep; ++ ++ /* See if the pcd_ep has its respective cfi_ep mapped */ ++ cfiep = get_cfi_ep_by_pcd_ep(ep->pcd->cfi, ep); ++ if (!cfiep) { ++ CFI_INFO("%s: Failed to find ep\n", __func__); ++ return -1; ++ } ++ ++ ddesc = ep->dwc_ep.descs; ++ ++ for (i = 0; (i < cfiep->desc_count) && (i < MAX_DMA_DESCS_PER_EP); i++) { ++ ++#if defined(PRINT_CFI_DMA_DESCS) ++ print_desc(ddesc, ep->ep.name, i); ++#endif ++ ret += ddesc->status.b.bytes; ++ ddesc++; ++ } ++ ++ if (ret) ++ CFI_INFO("!!!!!!!!!! WARNING (%s) - residue=%d\n", __func__, ++ ret); ++ ++ return ret; ++} ++#endif ++ ++/** ++ * This function completes the request for the EP. If there are ++ * additional requests for the EP in the queue they will be started. ++ */ ++static void complete_ep(dwc_otg_pcd_ep_t * ep) ++{ ++ dwc_otg_core_if_t *core_if = GET_CORE_IF(ep->pcd); ++ dwc_otg_dev_if_t *dev_if = core_if->dev_if; ++ dwc_otg_dev_in_ep_regs_t *in_ep_regs = ++ dev_if->in_ep_regs[ep->dwc_ep.num]; ++ deptsiz_data_t deptsiz; ++ dev_dma_desc_sts_t desc_sts; ++ dwc_otg_pcd_request_t *req = 0; ++ dwc_otg_dev_dma_desc_t *dma_desc; ++ uint32_t byte_count = 0; ++ int is_last = 0; ++ int i; ++ ++ DWC_DEBUGPL(DBG_PCDV, "%s() %d-%s\n", __func__, ep->dwc_ep.num, ++ (ep->dwc_ep.is_in ? "IN" : "OUT")); ++ ++ /* Get any pending requests */ ++ if (!DWC_CIRCLEQ_EMPTY(&ep->queue)) { ++ req = DWC_CIRCLEQ_FIRST(&ep->queue); ++ if (!req) { ++ DWC_PRINTF("complete_ep 0x%p, req = NULL!\n", ep); ++ return; ++ } ++ } else { ++ DWC_PRINTF("complete_ep 0x%p, ep->queue empty!\n", ep); ++ return; ++ } ++ ++ DWC_DEBUGPL(DBG_PCD, "Requests %d\n", ep->pcd->request_pending); ++ ++ if (ep->dwc_ep.is_in) { ++ deptsiz.d32 = dwc_read_reg32(&in_ep_regs->dieptsiz); ++ ++ if (core_if->dma_enable) { ++ if (core_if->dma_desc_enable == 0) { ++ if (deptsiz.b.xfersize == 0 ++ && deptsiz.b.pktcnt == 0) { ++ byte_count = ++ ep->dwc_ep.xfer_len - ++ ep->dwc_ep.xfer_count; ++ ++ ep->dwc_ep.xfer_buff += byte_count; ++ ep->dwc_ep.dma_addr += byte_count; ++ ep->dwc_ep.xfer_count += byte_count; ++ ++ DWC_DEBUGPL(DBG_PCDV, ++ "%d-%s len=%d xfersize=%d pktcnt=%d\n", ++ ep->dwc_ep.num, ++ (ep->dwc_ep. ++ is_in ? "IN" : "OUT"), ++ ep->dwc_ep.xfer_len, ++ deptsiz.b.xfersize, ++ deptsiz.b.pktcnt); ++ ++ if (ep->dwc_ep.xfer_len < ++ ep->dwc_ep.total_len) { ++ dwc_otg_ep_start_transfer ++ (core_if, &ep->dwc_ep); ++ } else if (ep->dwc_ep.sent_zlp) { ++ /* ++ * This fragment of code should initiate 0 ++ * length trasfer in case if it is queued ++ * a trasfer with size divisible to EPs max ++ * packet size and with usb_request zero field ++ * is set, which means that after data is transfered, ++ * it is also should be transfered ++ * a 0 length packet at the end. For Slave and ++ * Buffer DMA modes in this case SW has ++ * to initiate 2 transfers one with transfer size, ++ * and the second with 0 size. For Desriptor ++ * DMA mode SW is able to initiate a transfer, ++ * which will handle all the packets including ++ * the last 0 legth. ++ */ ++ ep->dwc_ep.sent_zlp = 0; ++ dwc_otg_ep_start_zl_transfer ++ (core_if, &ep->dwc_ep); ++ } else { ++ is_last = 1; ++ } ++ } else { ++ DWC_WARN ++ ("Incomplete transfer (%d - %s [siz=%d pkt=%d])\n", ++ ep->dwc_ep.num, ++ (ep->dwc_ep.is_in ? "IN" : "OUT"), ++ deptsiz.b.xfersize, ++ deptsiz.b.pktcnt); ++ } ++ } else { ++ dma_desc = ep->dwc_ep.desc_addr; ++ byte_count = 0; ++ ep->dwc_ep.sent_zlp = 0; ++ ++#ifdef DWC_UTE_CFI ++ CFI_INFO("%s: BUFFER_MODE=%d\n", __func__, ++ ep->dwc_ep.buff_mode); ++ if (ep->dwc_ep.buff_mode != BM_STANDARD) { ++ int residue; ++ ++ residue = cfi_calc_desc_residue(ep); ++ if (residue < 0) ++ return; ++ ++ byte_count = residue; ++ } else { ++#endif ++ for (i = 0; i < ep->dwc_ep.desc_cnt; ++ ++i) { ++ desc_sts = dma_desc->status; ++ byte_count += desc_sts.b.bytes; ++ dma_desc++; ++ } ++#ifdef DWC_UTE_CFI ++ } ++#endif ++ if (byte_count == 0) { ++ ep->dwc_ep.xfer_count = ++ ep->dwc_ep.total_len; ++ is_last = 1; ++ } else { ++ DWC_WARN("Incomplete transfer\n"); ++ } ++ } ++ } else { ++ if (deptsiz.b.xfersize == 0 && deptsiz.b.pktcnt == 0) { ++ DWC_DEBUGPL(DBG_PCDV, ++ "%d-%s len=%d xfersize=%d pktcnt=%d\n", ++ ep->dwc_ep.num, ++ ep->dwc_ep.is_in ? "IN" : "OUT", ++ ep->dwc_ep.xfer_len, ++ deptsiz.b.xfersize, ++ deptsiz.b.pktcnt); ++ ++ /* Check if the whole transfer was completed, ++ * if no, setup transfer for next portion of data ++ */ ++ if (ep->dwc_ep.xfer_len < ep->dwc_ep.total_len) { ++ dwc_otg_ep_start_transfer(core_if, ++ &ep->dwc_ep); ++ } else if (ep->dwc_ep.sent_zlp) { ++ /* ++ * This fragment of code should initiate 0 ++ * length trasfer in case if it is queued ++ * a trasfer with size divisible to EPs max ++ * packet size and with usb_request zero field ++ * is set, which means that after data is transfered, ++ * it is also should be transfered ++ * a 0 length packet at the end. For Slave and ++ * Buffer DMA modes in this case SW has ++ * to initiate 2 transfers one with transfer size, ++ * and the second with 0 size. For Desriptor ++ * DMA mode SW is able to initiate a transfer, ++ * which will handle all the packets including ++ * the last 0 legth. ++ */ ++ ep->dwc_ep.sent_zlp = 0; ++ dwc_otg_ep_start_zl_transfer(core_if, ++ &ep-> ++ dwc_ep); ++ } else { ++ is_last = 1; ++ } ++ } else { ++ DWC_WARN ++ ("Incomplete transfer (%d-%s [siz=%d pkt=%d])\n", ++ ep->dwc_ep.num, ++ (ep->dwc_ep.is_in ? "IN" : "OUT"), ++ deptsiz.b.xfersize, deptsiz.b.pktcnt); ++ } ++ } ++ } else { ++ dwc_otg_dev_out_ep_regs_t *out_ep_regs = ++ dev_if->out_ep_regs[ep->dwc_ep.num]; ++ desc_sts.d32 = 0; ++ if (core_if->dma_enable) { ++ if (core_if->dma_desc_enable) { ++ dma_desc = ep->dwc_ep.desc_addr; ++ byte_count = 0; ++ ep->dwc_ep.sent_zlp = 0; ++ ++#ifdef DWC_UTE_CFI ++ CFI_INFO("%s: BUFFER_MODE=%d\n", __func__, ++ ep->dwc_ep.buff_mode); ++ if (ep->dwc_ep.buff_mode != BM_STANDARD) { ++ int residue; ++ residue = cfi_calc_desc_residue(ep); ++ if (residue < 0) ++ return; ++ byte_count = residue; ++ } else { ++#endif ++ ++ for (i = 0; i < ep->dwc_ep.desc_cnt; ++ ++i) { ++ desc_sts = dma_desc->status; ++ byte_count += desc_sts.b.bytes; ++ dma_desc++; ++ } ++ ++#ifdef DWC_UTE_CFI ++ } ++#endif ++ ep->dwc_ep.xfer_count = ep->dwc_ep.total_len ++ - byte_count + ++ ((4 - (ep->dwc_ep.total_len & 0x3)) & 0x3); ++ is_last = 1; ++ } else { ++ deptsiz.d32 = 0; ++ deptsiz.d32 = ++ dwc_read_reg32(&out_ep_regs->doeptsiz); ++ ++ byte_count = (ep->dwc_ep.xfer_len - ++ ep->dwc_ep.xfer_count - ++ deptsiz.b.xfersize); ++ ep->dwc_ep.xfer_buff += byte_count; ++ ep->dwc_ep.dma_addr += byte_count; ++ ep->dwc_ep.xfer_count += byte_count; ++ ++ /* Check if the whole transfer was completed, ++ * if no, setup transfer for next portion of data ++ */ ++ if (ep->dwc_ep.xfer_len < ep->dwc_ep.total_len) { ++ dwc_otg_ep_start_transfer(core_if, ++ &ep->dwc_ep); ++ } else if (ep->dwc_ep.sent_zlp) { ++ /* ++ * This fragment of code should initiate 0 ++ * length trasfer in case if it is queued ++ * a trasfer with size divisible to EPs max ++ * packet size and with usb_request zero field ++ * is set, which means that after data is transfered, ++ * it is also should be transfered ++ * a 0 length packet at the end. For Slave and ++ * Buffer DMA modes in this case SW has ++ * to initiate 2 transfers one with transfer size, ++ * and the second with 0 size. For Desriptor ++ * DMA mode SW is able to initiate a transfer, ++ * which will handle all the packets including ++ * the last 0 legth. ++ */ ++ ep->dwc_ep.sent_zlp = 0; ++ dwc_otg_ep_start_zl_transfer(core_if, ++ &ep-> ++ dwc_ep); ++ } else { ++ is_last = 1; ++ } ++ } ++ } else { ++ /* Check if the whole transfer was completed, ++ * if no, setup transfer for next portion of data ++ */ ++ if (ep->dwc_ep.xfer_len < ep->dwc_ep.total_len) { ++ dwc_otg_ep_start_transfer(core_if, &ep->dwc_ep); ++ } else if (ep->dwc_ep.sent_zlp) { ++ /* ++ * This fragment of code should initiate 0 ++ * length trasfer in case if it is queued ++ * a trasfer with size divisible to EPs max ++ * packet size and with usb_request zero field ++ * is set, which means that after data is transfered, ++ * it is also should be transfered ++ * a 0 length packet at the end. For Slave and ++ * Buffer DMA modes in this case SW has ++ * to initiate 2 transfers one with transfer size, ++ * and the second with 0 size. For Desriptor ++ * DMA mode SW is able to initiate a transfer, ++ * which will handle all the packets including ++ * the last 0 legth. ++ */ ++ ep->dwc_ep.sent_zlp = 0; ++ dwc_otg_ep_start_zl_transfer(core_if, ++ &ep->dwc_ep); ++ } else { ++ is_last = 1; ++ } ++ } ++ ++ DWC_DEBUGPL(DBG_PCDV, ++ "addr %p, %d-%s len=%d cnt=%d xsize=%d pktcnt=%d\n", ++ &out_ep_regs->doeptsiz, ep->dwc_ep.num, ++ ep->dwc_ep.is_in ? "IN" : "OUT", ++ ep->dwc_ep.xfer_len, ep->dwc_ep.xfer_count, ++ deptsiz.b.xfersize, deptsiz.b.pktcnt); ++ } ++ ++ /* Complete the request */ ++ if (is_last) { ++#ifdef DWC_UTE_CFI ++ if (ep->dwc_ep.buff_mode != BM_STANDARD) { ++ req->actual = ep->dwc_ep.cfi_req_len - byte_count; ++ } else { ++#endif ++ req->actual = ep->dwc_ep.xfer_count; ++#ifdef DWC_UTE_CFI ++ } ++#endif ++ ++ dwc_otg_request_done(ep, req, 0); ++ ++ ep->dwc_ep.start_xfer_buff = 0; ++ ep->dwc_ep.xfer_buff = 0; ++ ep->dwc_ep.xfer_len = 0; ++ ++ /* If there is a request in the queue start it. */ ++ start_next_request(ep); ++ } ++} ++ ++#ifdef DWC_EN_ISOC ++ ++/** ++ * This function BNA interrupt for Isochronous EPs ++ * ++ */ ++static void dwc_otg_pcd_handle_iso_bna(dwc_otg_pcd_ep_t * ep) ++{ ++ dwc_ep_t *dwc_ep = &ep->dwc_ep; ++ volatile uint32_t *addr; ++ depctl_data_t depctl = {.d32 = 0 }; ++ dwc_otg_pcd_t *pcd = ep->pcd; ++ dwc_otg_dev_dma_desc_t *dma_desc; ++ int i; ++ ++ dma_desc = ++ dwc_ep->iso_desc_addr + dwc_ep->desc_cnt * (dwc_ep->proc_buf_num); ++ ++ if (dwc_ep->is_in) { ++ dev_dma_desc_sts_t sts = {.d32 = 0 }; ++ for (i = 0; i < dwc_ep->desc_cnt; ++i, ++dma_desc) { ++ sts.d32 = dma_desc->status.d32; ++ sts.b_iso_in.bs = BS_HOST_READY; ++ dma_desc->status.d32 = sts.d32; ++ } ++ } else { ++ dev_dma_desc_sts_t sts = {.d32 = 0 }; ++ for (i = 0; i < dwc_ep->desc_cnt; ++i, ++dma_desc) { ++ sts.d32 = dma_desc->status.d32; ++ sts.b_iso_out.bs = BS_HOST_READY; ++ dma_desc->status.d32 = sts.d32; ++ } ++ } ++ ++ if (dwc_ep->is_in == 0) { ++ addr = ++ &GET_CORE_IF(pcd)->dev_if->out_ep_regs[dwc_ep->num]-> ++ doepctl; ++ } else { ++ addr = ++ &GET_CORE_IF(pcd)->dev_if->in_ep_regs[dwc_ep->num]->diepctl; ++ } ++ depctl.b.epena = 1; ++ dwc_modify_reg32(addr, depctl.d32, depctl.d32); ++} ++ ++/** ++ * This function sets latest iso packet information(non-PTI mode) ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ * @param ep The EP to start the transfer on. ++ * ++ */ ++void set_current_pkt_info(dwc_otg_core_if_t * core_if, dwc_ep_t * ep) ++{ ++ deptsiz_data_t deptsiz = {.d32 = 0 }; ++ dma_addr_t dma_addr; ++ uint32_t offset; ++ ++ if (ep->proc_buf_num) ++ dma_addr = ep->dma_addr1; ++ else ++ dma_addr = ep->dma_addr0; ++ ++ if (ep->is_in) { ++ deptsiz.d32 = ++ dwc_read_reg32(&core_if->dev_if->in_ep_regs[ep->num]-> ++ dieptsiz); ++ offset = ep->data_per_frame; ++ } else { ++ deptsiz.d32 = ++ dwc_read_reg32(&core_if->dev_if->out_ep_regs[ep->num]-> ++ doeptsiz); ++ offset = ++ ep->data_per_frame + ++ (0x4 & (0x4 - (ep->data_per_frame & 0x3))); ++ } ++ ++ if (!deptsiz.b.xfersize) { ++ ep->pkt_info[ep->cur_pkt].length = ep->data_per_frame; ++ ep->pkt_info[ep->cur_pkt].offset = ++ ep->cur_pkt_dma_addr - dma_addr; ++ ep->pkt_info[ep->cur_pkt].status = 0; ++ } else { ++ ep->pkt_info[ep->cur_pkt].length = ep->data_per_frame; ++ ep->pkt_info[ep->cur_pkt].offset = ++ ep->cur_pkt_dma_addr - dma_addr; ++ ep->pkt_info[ep->cur_pkt].status = -DWC_E_NO_DATA; ++ } ++ ep->cur_pkt_addr += offset; ++ ep->cur_pkt_dma_addr += offset; ++ ep->cur_pkt++; ++} ++ ++/** ++ * This function sets latest iso packet information(DDMA mode) ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ * @param dwc_ep The EP to start the transfer on. ++ * ++ */ ++static void set_ddma_iso_pkts_info(dwc_otg_core_if_t * core_if, ++ dwc_ep_t * dwc_ep) ++{ ++ dwc_otg_dev_dma_desc_t *dma_desc; ++ dev_dma_desc_sts_t sts = {.d32 = 0 }; ++ iso_pkt_info_t *iso_packet; ++ uint32_t data_per_desc; ++ uint32_t offset; ++ int i, j; ++ ++ iso_packet = dwc_ep->pkt_info; ++ ++ /** Reinit closed DMA Descriptors*/ ++ /** ISO OUT EP */ ++ if (dwc_ep->is_in == 0) { ++ dma_desc = ++ dwc_ep->iso_desc_addr + ++ dwc_ep->desc_cnt * dwc_ep->proc_buf_num; ++ offset = 0; ++ ++ for (i = 0; i < dwc_ep->desc_cnt - dwc_ep->pkt_per_frm; ++ i += dwc_ep->pkt_per_frm) { ++ for (j = 0; j < dwc_ep->pkt_per_frm; ++j) { ++ data_per_desc = ++ ((j + 1) * dwc_ep->maxpacket > ++ dwc_ep->data_per_frame) ? dwc_ep-> ++ data_per_frame - ++ j * dwc_ep->maxpacket : dwc_ep->maxpacket; ++ data_per_desc += ++ (data_per_desc % 4) ? (4 - ++ data_per_desc % ++ 4) : 0; ++ ++ sts.d32 = dma_desc->status.d32; ++ ++ /* Write status in iso_packet_decsriptor */ ++ iso_packet->status = ++ sts.b_iso_out.rxsts + ++ (sts.b_iso_out.bs ^ BS_DMA_DONE); ++ if (iso_packet->status) { ++ iso_packet->status = -DWC_E_NO_DATA; ++ } ++ ++ /* Received data length */ ++ if (!sts.b_iso_out.rxbytes) { ++ iso_packet->length = ++ data_per_desc - ++ sts.b_iso_out.rxbytes; ++ } else { ++ iso_packet->length = ++ data_per_desc - ++ sts.b_iso_out.rxbytes + (4 - ++ dwc_ep-> ++ data_per_frame ++ % 4); ++ } ++ ++ iso_packet->offset = offset; ++ ++ offset += data_per_desc; ++ dma_desc++; ++ iso_packet++; ++ } ++ } ++ ++ for (j = 0; j < dwc_ep->pkt_per_frm - 1; ++j) { ++ data_per_desc = ++ ((j + 1) * dwc_ep->maxpacket > ++ dwc_ep->data_per_frame) ? dwc_ep->data_per_frame - ++ j * dwc_ep->maxpacket : dwc_ep->maxpacket; ++ data_per_desc += ++ (data_per_desc % 4) ? (4 - data_per_desc % 4) : 0; ++ ++ sts.d32 = dma_desc->status.d32; ++ ++ /* Write status in iso_packet_decsriptor */ ++ iso_packet->status = ++ sts.b_iso_out.rxsts + ++ (sts.b_iso_out.bs ^ BS_DMA_DONE); ++ if (iso_packet->status) { ++ iso_packet->status = -DWC_E_NO_DATA; ++ } ++ ++ /* Received data length */ ++ iso_packet->length = ++ dwc_ep->data_per_frame - sts.b_iso_out.rxbytes; ++ ++ iso_packet->offset = offset; ++ ++ offset += data_per_desc; ++ iso_packet++; ++ dma_desc++; ++ } ++ ++ sts.d32 = dma_desc->status.d32; ++ ++ /* Write status in iso_packet_decsriptor */ ++ iso_packet->status = ++ sts.b_iso_out.rxsts + (sts.b_iso_out.bs ^ BS_DMA_DONE); ++ if (iso_packet->status) { ++ iso_packet->status = -DWC_E_NO_DATA; ++ } ++ /* Received data length */ ++ if (!sts.b_iso_out.rxbytes) { ++ iso_packet->length = ++ dwc_ep->data_per_frame - sts.b_iso_out.rxbytes; ++ } else { ++ iso_packet->length = ++ dwc_ep->data_per_frame - sts.b_iso_out.rxbytes + ++ (4 - dwc_ep->data_per_frame % 4); ++ } ++ ++ iso_packet->offset = offset; ++ } else { ++/** ISO IN EP */ ++ ++ dma_desc = ++ dwc_ep->iso_desc_addr + ++ dwc_ep->desc_cnt * dwc_ep->proc_buf_num; ++ ++ for (i = 0; i < dwc_ep->desc_cnt - 1; i++) { ++ sts.d32 = dma_desc->status.d32; ++ ++ /* Write status in iso packet descriptor */ ++ iso_packet->status = ++ sts.b_iso_in.txsts + ++ (sts.b_iso_in.bs ^ BS_DMA_DONE); ++ if (iso_packet->status != 0) { ++ iso_packet->status = -DWC_E_NO_DATA; ++ ++ } ++ /* Bytes has been transfered */ ++ iso_packet->length = ++ dwc_ep->data_per_frame - sts.b_iso_in.txbytes; ++ ++ dma_desc++; ++ iso_packet++; ++ } ++ ++ sts.d32 = dma_desc->status.d32; ++ while (sts.b_iso_in.bs == BS_DMA_BUSY) { ++ sts.d32 = dma_desc->status.d32; ++ } ++ ++ /* Write status in iso packet descriptor ??? do be done with ERROR codes */ ++ iso_packet->status = ++ sts.b_iso_in.txsts + (sts.b_iso_in.bs ^ BS_DMA_DONE); ++ if (iso_packet->status != 0) { ++ iso_packet->status = -DWC_E_NO_DATA; ++ } ++ ++ /* Bytes has been transfered */ ++ iso_packet->length = ++ dwc_ep->data_per_frame - sts.b_iso_in.txbytes; ++ } ++} ++ ++/** ++ * This function reinitialize DMA Descriptors for Isochronous transfer ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ * @param dwc_ep The EP to start the transfer on. ++ * ++ */ ++static void reinit_ddma_iso_xfer(dwc_otg_core_if_t * core_if, dwc_ep_t * dwc_ep) ++{ ++ int i, j; ++ dwc_otg_dev_dma_desc_t *dma_desc; ++ dma_addr_t dma_ad; ++ volatile uint32_t *addr; ++ dev_dma_desc_sts_t sts = {.d32 = 0 }; ++ uint32_t data_per_desc; ++ ++ if (dwc_ep->is_in == 0) { ++ addr = &core_if->dev_if->out_ep_regs[dwc_ep->num]->doepctl; ++ } else { ++ addr = &core_if->dev_if->in_ep_regs[dwc_ep->num]->diepctl; ++ } ++ ++ if (dwc_ep->proc_buf_num == 0) { ++ /** Buffer 0 descriptors setup */ ++ dma_ad = dwc_ep->dma_addr0; ++ } else { ++ /** Buffer 1 descriptors setup */ ++ dma_ad = dwc_ep->dma_addr1; ++ } ++ ++ /** Reinit closed DMA Descriptors*/ ++ /** ISO OUT EP */ ++ if (dwc_ep->is_in == 0) { ++ dma_desc = ++ dwc_ep->iso_desc_addr + ++ dwc_ep->desc_cnt * dwc_ep->proc_buf_num; ++ ++ sts.b_iso_out.bs = BS_HOST_READY; ++ sts.b_iso_out.rxsts = 0; ++ sts.b_iso_out.l = 0; ++ sts.b_iso_out.sp = 0; ++ sts.b_iso_out.ioc = 0; ++ sts.b_iso_out.pid = 0; ++ sts.b_iso_out.framenum = 0; ++ ++ for (i = 0; i < dwc_ep->desc_cnt - dwc_ep->pkt_per_frm; ++ i += dwc_ep->pkt_per_frm) { ++ for (j = 0; j < dwc_ep->pkt_per_frm; ++j) { ++ data_per_desc = ++ ((j + 1) * dwc_ep->maxpacket > ++ dwc_ep->data_per_frame) ? dwc_ep-> ++ data_per_frame - ++ j * dwc_ep->maxpacket : dwc_ep->maxpacket; ++ data_per_desc += ++ (data_per_desc % 4) ? (4 - ++ data_per_desc % ++ 4) : 0; ++ sts.b_iso_out.rxbytes = data_per_desc; ++ dma_desc->buf = dma_ad; ++ dma_desc->status.d32 = sts.d32; ++ ++ dma_ad += data_per_desc; ++ dma_desc++; ++ } ++ } ++ ++ for (j = 0; j < dwc_ep->pkt_per_frm - 1; ++j) { ++ ++ data_per_desc = ++ ((j + 1) * dwc_ep->maxpacket > ++ dwc_ep->data_per_frame) ? dwc_ep->data_per_frame - ++ j * dwc_ep->maxpacket : dwc_ep->maxpacket; ++ data_per_desc += ++ (data_per_desc % 4) ? (4 - data_per_desc % 4) : 0; ++ sts.b_iso_out.rxbytes = data_per_desc; ++ ++ dma_desc->buf = dma_ad; ++ dma_desc->status.d32 = sts.d32; ++ ++ dma_desc++; ++ dma_ad += data_per_desc; ++ } ++ ++ sts.b_iso_out.ioc = 1; ++ sts.b_iso_out.l = dwc_ep->proc_buf_num; ++ ++ data_per_desc = ++ ((j + 1) * dwc_ep->maxpacket > ++ dwc_ep->data_per_frame) ? dwc_ep->data_per_frame - ++ j * dwc_ep->maxpacket : dwc_ep->maxpacket; ++ data_per_desc += ++ (data_per_desc % 4) ? (4 - data_per_desc % 4) : 0; ++ sts.b_iso_out.rxbytes = data_per_desc; ++ ++ dma_desc->buf = dma_ad; ++ dma_desc->status.d32 = sts.d32; ++ } else { ++/** ISO IN EP */ ++ ++ dma_desc = ++ dwc_ep->iso_desc_addr + ++ dwc_ep->desc_cnt * dwc_ep->proc_buf_num; ++ ++ sts.b_iso_in.bs = BS_HOST_READY; ++ sts.b_iso_in.txsts = 0; ++ sts.b_iso_in.sp = 0; ++ sts.b_iso_in.ioc = 0; ++ sts.b_iso_in.pid = dwc_ep->pkt_per_frm; ++ sts.b_iso_in.framenum = dwc_ep->next_frame; ++ sts.b_iso_in.txbytes = dwc_ep->data_per_frame; ++ sts.b_iso_in.l = 0; ++ ++ for (i = 0; i < dwc_ep->desc_cnt - 1; i++) { ++ dma_desc->buf = dma_ad; ++ dma_desc->status.d32 = sts.d32; ++ ++ sts.b_iso_in.framenum += dwc_ep->bInterval; ++ dma_ad += dwc_ep->data_per_frame; ++ dma_desc++; ++ } ++ ++ sts.b_iso_in.ioc = 1; ++ sts.b_iso_in.l = dwc_ep->proc_buf_num; ++ ++ dma_desc->buf = dma_ad; ++ dma_desc->status.d32 = sts.d32; ++ ++ dwc_ep->next_frame = ++ sts.b_iso_in.framenum + dwc_ep->bInterval * 1; ++ } ++ dwc_ep->proc_buf_num = (dwc_ep->proc_buf_num ^ 1) & 0x1; ++} ++ ++/** ++ * This function is to handle Iso EP transfer complete interrupt ++ * in case Iso out packet was dropped ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ * @param dwc_ep The EP for wihich transfer complete was asserted ++ * ++ */ ++static uint32_t handle_iso_out_pkt_dropped(dwc_otg_core_if_t * core_if, ++ dwc_ep_t * dwc_ep) ++{ ++ uint32_t dma_addr; ++ uint32_t drp_pkt; ++ uint32_t drp_pkt_cnt; ++ deptsiz_data_t deptsiz = {.d32 = 0 }; ++ depctl_data_t depctl = {.d32 = 0 }; ++ int i; ++ ++ deptsiz.d32 = ++ dwc_read_reg32(&core_if->dev_if->out_ep_regs[dwc_ep->num]-> ++ doeptsiz); ++ ++ drp_pkt = dwc_ep->pkt_cnt - deptsiz.b.pktcnt; ++ drp_pkt_cnt = dwc_ep->pkt_per_frm - (drp_pkt % dwc_ep->pkt_per_frm); ++ ++ /* Setting dropped packets status */ ++ for (i = 0; i < drp_pkt_cnt; ++i) { ++ dwc_ep->pkt_info[drp_pkt].status = -DWC_E_NO_DATA; ++ drp_pkt++; ++ deptsiz.b.pktcnt--; ++ } ++ ++ if (deptsiz.b.pktcnt > 0) { ++ deptsiz.b.xfersize = ++ dwc_ep->xfer_len - (dwc_ep->pkt_cnt - ++ deptsiz.b.pktcnt) * dwc_ep->maxpacket; ++ } else { ++ deptsiz.b.xfersize = 0; ++ deptsiz.b.pktcnt = 0; ++ } ++ ++ dwc_write_reg32(&core_if->dev_if->out_ep_regs[dwc_ep->num]->doeptsiz, ++ deptsiz.d32); ++ ++ if (deptsiz.b.pktcnt > 0) { ++ if (dwc_ep->proc_buf_num) { ++ dma_addr = ++ dwc_ep->dma_addr1 + dwc_ep->xfer_len - ++ deptsiz.b.xfersize; ++ } else { ++ dma_addr = ++ dwc_ep->dma_addr0 + dwc_ep->xfer_len - ++ deptsiz.b.xfersize;; ++ } ++ ++ dwc_write_reg32(&core_if->dev_if->out_ep_regs[dwc_ep->num]-> ++ doepdma, dma_addr); ++ ++ /** Re-enable endpoint, clear nak */ ++ depctl.d32 = 0; ++ depctl.b.epena = 1; ++ depctl.b.cnak = 1; ++ ++ dwc_modify_reg32(&core_if->dev_if->out_ep_regs[dwc_ep->num]-> ++ doepctl, depctl.d32, depctl.d32); ++ return 0; ++ } else { ++ return 1; ++ } ++} ++ ++/** ++ * This function sets iso packets information(PTI mode) ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ * @param ep The EP to start the transfer on. ++ * ++ */ ++static uint32_t set_iso_pkts_info(dwc_otg_core_if_t * core_if, dwc_ep_t * ep) ++{ ++ int i, j; ++ dma_addr_t dma_ad; ++ iso_pkt_info_t *packet_info = ep->pkt_info; ++ uint32_t offset; ++ uint32_t frame_data; ++ deptsiz_data_t deptsiz; ++ ++ if (ep->proc_buf_num == 0) { ++ /** Buffer 0 descriptors setup */ ++ dma_ad = ep->dma_addr0; ++ } else { ++ /** Buffer 1 descriptors setup */ ++ dma_ad = ep->dma_addr1; ++ } ++ ++ if (ep->is_in) { ++ deptsiz.d32 = ++ dwc_read_reg32(&core_if->dev_if->in_ep_regs[ep->num]-> ++ dieptsiz); ++ } else { ++ deptsiz.d32 = ++ dwc_read_reg32(&core_if->dev_if->out_ep_regs[ep->num]-> ++ doeptsiz); ++ } ++ ++ if (!deptsiz.b.xfersize) { ++ offset = 0; ++ for (i = 0; i < ep->pkt_cnt; i += ep->pkt_per_frm) { ++ frame_data = ep->data_per_frame; ++ for (j = 0; j < ep->pkt_per_frm; ++j) { ++ ++ /* Packet status - is not set as initially ++ * it is set to 0 and if packet was sent ++ successfully, status field will remain 0*/ ++ ++ /* Bytes has been transfered */ ++ packet_info->length = ++ (ep->maxpacket < ++ frame_data) ? ep->maxpacket : frame_data; ++ ++ /* Received packet offset */ ++ packet_info->offset = offset; ++ offset += packet_info->length; ++ frame_data -= packet_info->length; ++ ++ packet_info++; ++ } ++ } ++ return 1; ++ } else { ++ /* This is a workaround for in case of Transfer Complete with ++ * PktDrpSts interrupts merging - in this case Transfer complete ++ * interrupt for Isoc Out Endpoint is asserted without PktDrpSts ++ * set and with DOEPTSIZ register non zero. Investigations showed, ++ * that this happens when Out packet is dropped, but because of ++ * interrupts merging during first interrupt handling PktDrpSts ++ * bit is cleared and for next merged interrupts it is not reset. ++ * In this case SW hadles the interrupt as if PktDrpSts bit is set. ++ */ ++ if (ep->is_in) { ++ return 1; ++ } else { ++ return handle_iso_out_pkt_dropped(core_if, ep); ++ } ++ } ++} ++ ++/** ++ * This function is to handle Iso EP transfer complete interrupt ++ * ++ * @param pcd The PCD ++ * @param ep The EP for which transfer complete was asserted ++ * ++ */ ++static void complete_iso_ep(dwc_otg_pcd_t * pcd, dwc_otg_pcd_ep_t * ep) ++{ ++ dwc_otg_core_if_t *core_if = GET_CORE_IF(ep->pcd); ++ dwc_ep_t *dwc_ep = &ep->dwc_ep; ++ uint8_t is_last = 0; ++ ++ if(ep->dwc_ep.next_frame == 0xffffffff) { ++ DWC_WARN("Next frame is not set!\n"); ++ return; ++ } ++ ++ if (core_if->dma_enable) { ++ if (core_if->dma_desc_enable) { ++ set_ddma_iso_pkts_info(core_if, dwc_ep); ++ reinit_ddma_iso_xfer(core_if, dwc_ep); ++ is_last = 1; ++ } else { ++ if (core_if->pti_enh_enable) { ++ if (set_iso_pkts_info(core_if, dwc_ep)) { ++ dwc_ep->proc_buf_num = ++ (dwc_ep->proc_buf_num ^ 1) & 0x1; ++ dwc_otg_iso_ep_start_buf_transfer ++ (core_if, dwc_ep); ++ is_last = 1; ++ } ++ } else { ++ set_current_pkt_info(core_if, dwc_ep); ++ if (dwc_ep->cur_pkt >= dwc_ep->pkt_cnt) { ++ is_last = 1; ++ dwc_ep->cur_pkt = 0; ++ dwc_ep->proc_buf_num = ++ (dwc_ep->proc_buf_num ^ 1) & 0x1; ++ if (dwc_ep->proc_buf_num) { ++ dwc_ep->cur_pkt_addr = ++ dwc_ep->xfer_buff1; ++ dwc_ep->cur_pkt_dma_addr = ++ dwc_ep->dma_addr1; ++ } else { ++ dwc_ep->cur_pkt_addr = ++ dwc_ep->xfer_buff0; ++ dwc_ep->cur_pkt_dma_addr = ++ dwc_ep->dma_addr0; ++ } ++ ++ } ++ dwc_otg_iso_ep_start_frm_transfer(core_if, ++ dwc_ep); ++ } ++ } ++ } else { ++ set_current_pkt_info(core_if, dwc_ep); ++ if (dwc_ep->cur_pkt >= dwc_ep->pkt_cnt) { ++ is_last = 1; ++ dwc_ep->cur_pkt = 0; ++ dwc_ep->proc_buf_num = (dwc_ep->proc_buf_num ^ 1) & 0x1; ++ if (dwc_ep->proc_buf_num) { ++ dwc_ep->cur_pkt_addr = dwc_ep->xfer_buff1; ++ dwc_ep->cur_pkt_dma_addr = dwc_ep->dma_addr1; ++ } else { ++ dwc_ep->cur_pkt_addr = dwc_ep->xfer_buff0; ++ dwc_ep->cur_pkt_dma_addr = dwc_ep->dma_addr0; ++ } ++ ++ } ++ dwc_otg_iso_ep_start_frm_transfer(core_if, dwc_ep); ++ } ++ if (is_last) ++ dwc_otg_iso_buffer_done(pcd, ep, ep->iso_req_handle); ++} ++#endif /* DWC_EN_ISOC */ ++ ++/** ++ * This function handles EP0 Control transfers. ++ * ++ * The state of the control tranfers are tracked in ++ * ep0state. ++ */ ++static void handle_ep0(dwc_otg_pcd_t * pcd) ++{ ++ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); ++ dwc_otg_pcd_ep_t *ep0 = &pcd->ep0; ++ dev_dma_desc_sts_t desc_sts; ++ deptsiz0_data_t deptsiz; ++ uint32_t byte_count; ++ ++#ifdef DEBUG_EP0 ++ DWC_DEBUGPL(DBG_PCDV, "%s()\n", __func__); ++ print_ep0_state(pcd); ++#endif ++ ++// DWC_PRINTF("HANDLE EP0\n"); ++ ++ switch (pcd->ep0state) { ++ case EP0_DISCONNECT: ++ break; ++ ++ case EP0_IDLE: ++ pcd->request_config = 0; ++ ++ pcd_setup(pcd); ++ break; ++ ++ case EP0_IN_DATA_PHASE: ++#ifdef DEBUG_EP0 ++ DWC_DEBUGPL(DBG_PCD, "DATA_IN EP%d-%s: type=%d, mps=%d\n", ++ ep0->dwc_ep.num, (ep0->dwc_ep.is_in ? "IN" : "OUT"), ++ ep0->dwc_ep.type, ep0->dwc_ep.maxpacket); ++#endif ++ ++ if (core_if->dma_enable != 0) { ++ /* ++ * For EP0 we can only program 1 packet at a time so we ++ * need to do the make calculations after each complete. ++ * Call write_packet to make the calculations, as in ++ * slave mode, and use those values to determine if we ++ * can complete. ++ */ ++ if (core_if->dma_desc_enable == 0) { ++ deptsiz.d32 = ++ dwc_read_reg32(&core_if->dev_if-> ++ in_ep_regs[0]->dieptsiz); ++ byte_count = ++ ep0->dwc_ep.xfer_len - deptsiz.b.xfersize; ++ } else { ++ desc_sts = ++ core_if->dev_if->in_desc_addr->status; ++ byte_count = ++ ep0->dwc_ep.xfer_len - desc_sts.b.bytes; ++ } ++ ep0->dwc_ep.xfer_count += byte_count; ++ ep0->dwc_ep.xfer_buff += byte_count; ++ ep0->dwc_ep.dma_addr += byte_count; ++ } ++ if (ep0->dwc_ep.xfer_count < ep0->dwc_ep.total_len) { ++ dwc_otg_ep0_continue_transfer(GET_CORE_IF(pcd), ++ &ep0->dwc_ep); ++ DWC_DEBUGPL(DBG_PCD, "CONTINUE TRANSFER\n"); ++ } else if (ep0->dwc_ep.sent_zlp) { ++ dwc_otg_ep0_continue_transfer(GET_CORE_IF(pcd), ++ &ep0->dwc_ep); ++ ep0->dwc_ep.sent_zlp = 0; ++ DWC_DEBUGPL(DBG_PCD, "CONTINUE TRANSFER\n"); ++ } else { ++ ep0_complete_request(ep0); ++ DWC_DEBUGPL(DBG_PCD, "COMPLETE TRANSFER\n"); ++ } ++ break; ++ case EP0_OUT_DATA_PHASE: ++#ifdef DEBUG_EP0 ++ DWC_DEBUGPL(DBG_PCD, "DATA_OUT EP%d-%s: type=%d, mps=%d\n", ++ ep0->dwc_ep.num, (ep0->dwc_ep.is_in ? "IN" : "OUT"), ++ ep0->dwc_ep.type, ep0->dwc_ep.maxpacket); ++#endif ++ if (core_if->dma_enable != 0) { ++ if (core_if->dma_desc_enable == 0) { ++ deptsiz.d32 = ++ dwc_read_reg32(&core_if->dev_if-> ++ out_ep_regs[0]->doeptsiz); ++ byte_count = ++ ep0->dwc_ep.maxpacket - deptsiz.b.xfersize; ++ } else { ++ desc_sts = ++ core_if->dev_if->out_desc_addr->status; ++ byte_count = ++ ep0->dwc_ep.maxpacket - desc_sts.b.bytes; ++ } ++ ep0->dwc_ep.xfer_count += byte_count; ++ ep0->dwc_ep.xfer_buff += byte_count; ++ ep0->dwc_ep.dma_addr += byte_count; ++ } ++ if (ep0->dwc_ep.xfer_count < ep0->dwc_ep.total_len) { ++ dwc_otg_ep0_continue_transfer(GET_CORE_IF(pcd), ++ &ep0->dwc_ep); ++ DWC_DEBUGPL(DBG_PCD, "CONTINUE TRANSFER\n"); ++ } else if (ep0->dwc_ep.sent_zlp) { ++ dwc_otg_ep0_continue_transfer(GET_CORE_IF(pcd), ++ &ep0->dwc_ep); ++ ep0->dwc_ep.sent_zlp = 0; ++ DWC_DEBUGPL(DBG_PCD, "CONTINUE TRANSFER\n"); ++ } else { ++ ep0_complete_request(ep0); ++ DWC_DEBUGPL(DBG_PCD, "COMPLETE TRANSFER\n"); ++ } ++ break; ++ ++ case EP0_IN_STATUS_PHASE: ++ case EP0_OUT_STATUS_PHASE: ++ DWC_DEBUGPL(DBG_PCD, "CASE: EP0_STATUS\n"); ++ ep0_complete_request(ep0); ++ pcd->ep0state = EP0_IDLE; ++ ep0->stopped = 1; ++ ep0->dwc_ep.is_in = 0; /* OUT for next SETUP */ ++ ++ /* Prepare for more SETUP Packets */ ++ if (core_if->dma_enable) { ++ ep0_out_start(core_if, pcd); ++ } ++ break; ++ ++ case EP0_STALL: ++ DWC_ERROR("EP0 STALLed, should not get here pcd_setup()\n"); ++ break; ++ } ++#ifdef DEBUG_EP0 ++ print_ep0_state(pcd); ++#endif ++} ++ ++/** ++ * Restart transfer ++ */ ++static void restart_transfer(dwc_otg_pcd_t * pcd, const uint32_t epnum) ++{ ++ dwc_otg_core_if_t *core_if; ++ dwc_otg_dev_if_t *dev_if; ++ deptsiz_data_t dieptsiz = {.d32 = 0 }; ++ dwc_otg_pcd_ep_t *ep; ++ ++ ep = get_in_ep(pcd, epnum); ++ ++#ifdef DWC_EN_ISOC ++ if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) { ++ return; ++ } ++#endif /* DWC_EN_ISOC */ ++ ++ core_if = GET_CORE_IF(pcd); ++ dev_if = core_if->dev_if; ++ ++ dieptsiz.d32 = dwc_read_reg32(&dev_if->in_ep_regs[epnum]->dieptsiz); ++ ++ DWC_DEBUGPL(DBG_PCD, "xfer_buff=%p xfer_count=%0x xfer_len=%0x" ++ " stopped=%d\n", ep->dwc_ep.xfer_buff, ++ ep->dwc_ep.xfer_count, ep->dwc_ep.xfer_len, ep->stopped); ++ /* ++ * If xfersize is 0 and pktcnt in not 0, resend the last packet. ++ */ ++ if (dieptsiz.b.pktcnt && dieptsiz.b.xfersize == 0 && ++ ep->dwc_ep.start_xfer_buff != 0) { ++ if (ep->dwc_ep.total_len <= ep->dwc_ep.maxpacket) { ++ ep->dwc_ep.xfer_count = 0; ++ ep->dwc_ep.xfer_buff = ep->dwc_ep.start_xfer_buff; ++ ep->dwc_ep.xfer_len = ep->dwc_ep.xfer_count; ++ } else { ++ ep->dwc_ep.xfer_count -= ep->dwc_ep.maxpacket; ++ /* convert packet size to dwords. */ ++ ep->dwc_ep.xfer_buff -= ep->dwc_ep.maxpacket; ++ ep->dwc_ep.xfer_len = ep->dwc_ep.xfer_count; ++ } ++ ep->stopped = 0; ++ DWC_DEBUGPL(DBG_PCD, "xfer_buff=%p xfer_count=%0x " ++ "xfer_len=%0x stopped=%d\n", ++ ep->dwc_ep.xfer_buff, ++ ep->dwc_ep.xfer_count, ep->dwc_ep.xfer_len, ++ ep->stopped); ++ if (epnum == 0) { ++ dwc_otg_ep0_start_transfer(core_if, &ep->dwc_ep); ++ } else { ++ dwc_otg_ep_start_transfer(core_if, &ep->dwc_ep); ++ } ++ } ++} ++ ++/** ++ * handle the IN EP disable interrupt. ++ */ ++static inline void handle_in_ep_disable_intr(dwc_otg_pcd_t * pcd, ++ const uint32_t epnum) ++{ ++ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); ++ dwc_otg_dev_if_t *dev_if = core_if->dev_if; ++ deptsiz_data_t dieptsiz = {.d32 = 0 }; ++ dctl_data_t dctl = {.d32 = 0 }; ++ dwc_otg_pcd_ep_t *ep; ++ dwc_ep_t *dwc_ep; ++ ++ ep = get_in_ep(pcd, epnum); ++ dwc_ep = &ep->dwc_ep; ++ ++ if (dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) { ++ dwc_otg_flush_tx_fifo(core_if, dwc_ep->tx_fifo_num); ++ return; ++ } ++ ++ DWC_DEBUGPL(DBG_PCD, "diepctl%d=%0x\n", epnum, ++ dwc_read_reg32(&dev_if->in_ep_regs[epnum]->diepctl)); ++ dieptsiz.d32 = dwc_read_reg32(&dev_if->in_ep_regs[epnum]->dieptsiz); ++ ++ DWC_DEBUGPL(DBG_ANY, "pktcnt=%d size=%d\n", ++ dieptsiz.b.pktcnt, dieptsiz.b.xfersize); ++ ++ if (ep->stopped) { ++ /* Flush the Tx FIFO */ ++ dwc_otg_flush_tx_fifo(core_if, dwc_ep->tx_fifo_num); ++ /* Clear the Global IN NP NAK */ ++ dctl.d32 = 0; ++ dctl.b.cgnpinnak = 1; ++ dwc_modify_reg32(&dev_if->dev_global_regs->dctl, dctl.d32, 0); ++ /* Restart the transaction */ ++ if (dieptsiz.b.pktcnt != 0 || dieptsiz.b.xfersize != 0) { ++ restart_transfer(pcd, epnum); ++ } ++ } else { ++ /* Restart the transaction */ ++ if (dieptsiz.b.pktcnt != 0 || dieptsiz.b.xfersize != 0) { ++ restart_transfer(pcd, epnum); ++ } ++ DWC_DEBUGPL(DBG_ANY, "STOPPED!!!\n"); ++ } ++} ++ ++/** ++ * Handler for the IN EP timeout handshake interrupt. ++ */ ++static inline void handle_in_ep_timeout_intr(dwc_otg_pcd_t * pcd, ++ const uint32_t epnum) ++{ ++ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); ++ dwc_otg_dev_if_t *dev_if = core_if->dev_if; ++ ++#ifdef DEBUG ++ deptsiz_data_t dieptsiz = {.d32 = 0 }; ++ uint32_t num = 0; ++#endif ++ dctl_data_t dctl = {.d32 = 0 }; ++ dwc_otg_pcd_ep_t *ep; ++ ++ gintmsk_data_t intr_mask = {.d32 = 0 }; ++ ++ ep = get_in_ep(pcd, epnum); ++ ++ /* Disable the NP Tx Fifo Empty Interrrupt */ ++ if (!core_if->dma_enable) { ++ intr_mask.b.nptxfempty = 1; ++ dwc_modify_reg32(&core_if->core_global_regs->gintmsk, ++ intr_mask.d32, 0); ++ } ++ /** @todo NGS Check EP type. ++ * Implement for Periodic EPs */ ++ /* ++ * Non-periodic EP ++ */ ++ /* Enable the Global IN NAK Effective Interrupt */ ++ intr_mask.b.ginnakeff = 1; ++ dwc_modify_reg32(&core_if->core_global_regs->gintmsk, 0, intr_mask.d32); ++ ++ /* Set Global IN NAK */ ++ dctl.b.sgnpinnak = 1; ++ dwc_modify_reg32(&dev_if->dev_global_regs->dctl, dctl.d32, dctl.d32); ++ ++ ep->stopped = 1; ++ ++#ifdef DEBUG ++ dieptsiz.d32 = dwc_read_reg32(&dev_if->in_ep_regs[num]->dieptsiz); ++ DWC_DEBUGPL(DBG_ANY, "pktcnt=%d size=%d\n", ++ dieptsiz.b.pktcnt, dieptsiz.b.xfersize); ++#endif ++ ++#ifdef DISABLE_PERIODIC_EP ++ /* ++ * Set the NAK bit for this EP to ++ * start the disable process. ++ */ ++ diepctl.d32 = 0; ++ diepctl.b.snak = 1; ++ dwc_modify_reg32(&dev_if->in_ep_regs[num]->diepctl, diepctl.d32, ++ diepctl.d32); ++ ep->disabling = 1; ++ ep->stopped = 1; ++#endif ++} ++ ++/** ++ * Handler for the IN EP NAK interrupt. ++ */ ++static inline int32_t handle_in_ep_nak_intr(dwc_otg_pcd_t * pcd, ++ const uint32_t epnum) ++{ ++ /** @todo implement ISR */ ++ dwc_otg_core_if_t *core_if; ++ diepmsk_data_t intr_mask = {.d32 = 0 }; ++ ++ DWC_PRINTF("INTERRUPT Handler not implemented for %s\n", "IN EP NAK"); ++ core_if = GET_CORE_IF(pcd); ++ intr_mask.b.nak = 1; ++ ++ if (core_if->multiproc_int_enable) { ++ dwc_modify_reg32(&core_if->dev_if->dev_global_regs-> ++ diepeachintmsk[epnum], intr_mask.d32, 0); ++ } else { ++ dwc_modify_reg32(&core_if->dev_if->dev_global_regs->diepmsk, ++ intr_mask.d32, 0); ++ } ++ ++ return 1; ++} ++ ++/** ++ * Handler for the OUT EP Babble interrupt. ++ */ ++static inline int32_t handle_out_ep_babble_intr(dwc_otg_pcd_t * pcd, ++ const uint32_t epnum) ++{ ++ /** @todo implement ISR */ ++ dwc_otg_core_if_t *core_if; ++ doepmsk_data_t intr_mask = {.d32 = 0 }; ++ ++ DWC_PRINTF("INTERRUPT Handler not implemented for %s\n", ++ "OUT EP Babble"); ++ core_if = GET_CORE_IF(pcd); ++ intr_mask.b.babble = 1; ++ ++ if (core_if->multiproc_int_enable) { ++ dwc_modify_reg32(&core_if->dev_if->dev_global_regs-> ++ doepeachintmsk[epnum], intr_mask.d32, 0); ++ } else { ++ dwc_modify_reg32(&core_if->dev_if->dev_global_regs->doepmsk, ++ intr_mask.d32, 0); ++ } ++ ++ return 1; ++} ++ ++/** ++ * Handler for the OUT EP NAK interrupt. ++ */ ++static inline int32_t handle_out_ep_nak_intr(dwc_otg_pcd_t * pcd, ++ const uint32_t epnum) ++{ ++ /** @todo implement ISR */ ++ dwc_otg_core_if_t *core_if; ++ doepmsk_data_t intr_mask = {.d32 = 0 }; ++ ++ DWC_PRINTF("INTERRUPT Handler not implemented for %s\n", "OUT EP NAK"); ++ core_if = GET_CORE_IF(pcd); ++ intr_mask.b.nak = 1; ++ ++ if (core_if->multiproc_int_enable) { ++ dwc_modify_reg32(&core_if->dev_if->dev_global_regs-> ++ doepeachintmsk[epnum], intr_mask.d32, 0); ++ } else { ++ dwc_modify_reg32(&core_if->dev_if->dev_global_regs->doepmsk, ++ intr_mask.d32, 0); ++ } ++ ++ return 1; ++} ++ ++/** ++ * Handler for the OUT EP NYET interrupt. ++ */ ++static inline int32_t handle_out_ep_nyet_intr(dwc_otg_pcd_t * pcd, ++ const uint32_t epnum) ++{ ++ /** @todo implement ISR */ ++ dwc_otg_core_if_t *core_if; ++ doepmsk_data_t intr_mask = {.d32 = 0 }; ++ ++ DWC_PRINTF("INTERRUPT Handler not implemented for %s\n", "OUT EP NYET"); ++ core_if = GET_CORE_IF(pcd); ++ intr_mask.b.nyet = 1; ++ ++ if (core_if->multiproc_int_enable) { ++ dwc_modify_reg32(&core_if->dev_if->dev_global_regs-> ++ doepeachintmsk[epnum], intr_mask.d32, 0); ++ } else { ++ dwc_modify_reg32(&core_if->dev_if->dev_global_regs->doepmsk, ++ intr_mask.d32, 0); ++ } ++ ++ return 1; ++} ++ ++/** ++ * This interrupt indicates that an IN EP has a pending Interrupt. ++ * The sequence for handling the IN EP interrupt is shown below: ++ * -# Read the Device All Endpoint Interrupt register ++ * -# Repeat the following for each IN EP interrupt bit set (from ++ * LSB to MSB). ++ * -# Read the Device Endpoint Interrupt (DIEPINTn) register ++ * -# If "Transfer Complete" call the request complete function ++ * -# If "Endpoint Disabled" complete the EP disable procedure. ++ * -# If "AHB Error Interrupt" log error ++ * -# If "Time-out Handshake" log error ++ * -# If "IN Token Received when TxFIFO Empty" write packet to Tx ++ * FIFO. ++ * -# If "IN Token EP Mismatch" (disable, this is handled by EP ++ * Mismatch Interrupt) ++ */ ++static int32_t dwc_otg_pcd_handle_in_ep_intr(dwc_otg_pcd_t * pcd) ++{ ++#define CLEAR_IN_EP_INTR(__core_if,__epnum,__intr) \ ++do { \ ++ diepint_data_t diepint = {.d32=0}; \ ++ diepint.b.__intr = 1; \ ++ dwc_write_reg32(&__core_if->dev_if->in_ep_regs[__epnum]->diepint, \ ++ diepint.d32); \ ++} while (0) ++ ++ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); ++ dwc_otg_dev_if_t *dev_if = core_if->dev_if; ++ diepint_data_t diepint = {.d32 = 0 }; ++ dctl_data_t dctl = {.d32 = 0 }; ++ depctl_data_t depctl = {.d32 = 0 }; ++ uint32_t ep_intr; ++ uint32_t epnum = 0; ++ dwc_otg_pcd_ep_t *ep; ++ dwc_ep_t *dwc_ep; ++ gintmsk_data_t intr_mask = {.d32 = 0 }; ++ ++ DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, pcd); ++ ++ /* Read in the device interrupt bits */ ++ ep_intr = dwc_otg_read_dev_all_in_ep_intr(core_if); ++ ++ /* Service the Device IN interrupts for each endpoint */ ++ while (ep_intr) { ++ if (ep_intr & 0x1) { ++ uint32_t empty_msk; ++ /* Get EP pointer */ ++ ep = get_in_ep(pcd, epnum); ++ dwc_ep = &ep->dwc_ep; ++ ++ depctl.d32 = ++ dwc_read_reg32(&dev_if->in_ep_regs[epnum]->diepctl); ++ empty_msk = ++ dwc_read_reg32(&dev_if->dev_global_regs-> ++ dtknqr4_fifoemptymsk); ++ ++ DWC_DEBUGPL(DBG_PCDV, ++ "IN EP INTERRUPT - %d\nepmty_msk - %8x diepctl - %8x\n", ++ epnum, empty_msk, depctl.d32); ++ ++ DWC_DEBUGPL(DBG_PCD, ++ "EP%d-%s: type=%d, mps=%d\n", ++ dwc_ep->num, (dwc_ep->is_in ? "IN" : "OUT"), ++ dwc_ep->type, dwc_ep->maxpacket); ++ ++ diepint.d32 = ++ dwc_otg_read_dev_in_ep_intr(core_if, dwc_ep); ++ ++ DWC_DEBUGPL(DBG_PCDV, ++ "EP %d Interrupt Register - 0x%x\n", epnum, ++ diepint.d32); ++ /* Transfer complete */ ++ if (diepint.b.xfercompl) { ++ /* Disable the NP Tx FIFO Empty ++ * Interrrupt */ ++ if (core_if->en_multiple_tx_fifo == 0) { ++ intr_mask.b.nptxfempty = 1; ++ dwc_modify_reg32(&core_if-> ++ core_global_regs-> ++ gintmsk, intr_mask.d32, ++ 0); ++ } else { ++ /* Disable the Tx FIFO Empty Interrupt for this EP */ ++ uint32_t fifoemptymsk = ++ 0x1 << dwc_ep->num; ++ dwc_modify_reg32(&core_if->dev_if-> ++ dev_global_regs-> ++ dtknqr4_fifoemptymsk, ++ fifoemptymsk, 0); ++ } ++ /* Clear the bit in DIEPINTn for this interrupt */ ++ CLEAR_IN_EP_INTR(core_if, epnum, xfercompl); ++ ++ /* Complete the transfer */ ++ if (epnum == 0) { ++ handle_ep0(pcd); ++ } ++#ifdef DWC_EN_ISOC ++ else if (dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) { ++ if (!ep->stopped) ++ complete_iso_ep(pcd, ep); ++ } ++#endif /* DWC_EN_ISOC */ ++ else { ++ ++ complete_ep(ep); ++ } ++ } ++ /* Endpoint disable */ ++ if (diepint.b.epdisabled) { ++ DWC_DEBUGPL(DBG_ANY, "EP%d IN disabled\n", ++ epnum); ++ handle_in_ep_disable_intr(pcd, epnum); ++ ++ /* Clear the bit in DIEPINTn for this interrupt */ ++ CLEAR_IN_EP_INTR(core_if, epnum, epdisabled); ++ } ++ /* AHB Error */ ++ if (diepint.b.ahberr) { ++ DWC_DEBUGPL(DBG_ANY, "EP%d IN AHB Error\n", ++ epnum); ++ /* Clear the bit in DIEPINTn for this interrupt */ ++ CLEAR_IN_EP_INTR(core_if, epnum, ahberr); ++ } ++ /* TimeOUT Handshake (non-ISOC IN EPs) */ ++ if (diepint.b.timeout) { ++ DWC_DEBUGPL(DBG_ANY, "EP%d IN Time-out\n", ++ epnum); ++ handle_in_ep_timeout_intr(pcd, epnum); ++ ++ CLEAR_IN_EP_INTR(core_if, epnum, timeout); ++ } ++ /** IN Token received with TxF Empty */ ++ if (diepint.b.intktxfemp) { ++ DWC_DEBUGPL(DBG_ANY, ++ "EP%d IN TKN TxFifo Empty\n", ++ epnum); ++ if (!ep->stopped && epnum != 0) { ++ ++ diepmsk_data_t diepmsk = {.d32 = 0 }; ++ diepmsk.b.intktxfemp = 1; ++ ++ if (core_if->multiproc_int_enable) { ++ dwc_modify_reg32(&dev_if-> ++ dev_global_regs-> ++ diepeachintmsk ++ [epnum], ++ diepmsk.d32, ++ 0); ++ } else { ++ dwc_modify_reg32(&dev_if-> ++ dev_global_regs-> ++ diepmsk, ++ diepmsk.d32, ++ 0); ++ } ++ } else if (core_if->dma_desc_enable ++ && epnum == 0 ++ && pcd->ep0state == ++ EP0_OUT_STATUS_PHASE) { ++ // EP0 IN set STALL ++ depctl.d32 = ++ dwc_read_reg32(&dev_if-> ++ in_ep_regs[epnum]-> ++ diepctl); ++ ++ /* set the disable and stall bits */ ++ if (depctl.b.epena) { ++ depctl.b.epdis = 1; ++ } ++ depctl.b.stall = 1; ++ dwc_write_reg32(&dev_if-> ++ in_ep_regs[epnum]-> ++ diepctl, depctl.d32); ++ } ++ CLEAR_IN_EP_INTR(core_if, epnum, intktxfemp); ++ } ++ /** IN Token Received with EP mismatch */ ++ if (diepint.b.intknepmis) { ++ DWC_DEBUGPL(DBG_ANY, ++ "EP%d IN TKN EP Mismatch\n", epnum); ++ CLEAR_IN_EP_INTR(core_if, epnum, intknepmis); ++ } ++ /** IN Endpoint NAK Effective */ ++ if (diepint.b.inepnakeff) { ++ DWC_DEBUGPL(DBG_ANY, ++ "EP%d IN EP NAK Effective\n", ++ epnum); ++ /* Periodic EP */ ++ if (ep->disabling) { ++ depctl.d32 = 0; ++ depctl.b.snak = 1; ++ depctl.b.epdis = 1; ++ dwc_modify_reg32(&dev_if-> ++ in_ep_regs[epnum]-> ++ diepctl, depctl.d32, ++ depctl.d32); ++ } ++ CLEAR_IN_EP_INTR(core_if, epnum, inepnakeff); ++ ++ } ++ ++ /** IN EP Tx FIFO Empty Intr */ ++ if (diepint.b.emptyintr) { ++ DWC_DEBUGPL(DBG_ANY, ++ "EP%d Tx FIFO Empty Intr \n", ++ epnum); ++ write_empty_tx_fifo(pcd, epnum); ++ ++ CLEAR_IN_EP_INTR(core_if, epnum, emptyintr); ++ ++ } ++ ++ /** IN EP BNA Intr */ ++ if (diepint.b.bna) { ++ CLEAR_IN_EP_INTR(core_if, epnum, bna); ++ if (core_if->dma_desc_enable) { ++#ifdef DWC_EN_ISOC ++ if (dwc_ep->type == ++ DWC_OTG_EP_TYPE_ISOC) { ++ /* ++ * This checking is performed to prevent first "false" BNA ++ * handling occuring right after reconnect ++ */ ++ if (dwc_ep->next_frame != ++ 0xffffffff) ++ dwc_otg_pcd_handle_iso_bna ++ (ep); ++ } else ++#endif /* DWC_EN_ISOC */ ++ { ++ dctl.d32 = ++ dwc_read_reg32(&dev_if-> ++ dev_global_regs-> ++ dctl); ++ ++ /* If Global Continue on BNA is disabled - disable EP */ ++ if (!dctl.b.gcontbna) { ++ depctl.d32 = 0; ++ depctl.b.snak = 1; ++ depctl.b.epdis = 1; ++ dwc_modify_reg32 ++ (&dev_if-> ++ in_ep_regs[epnum]-> ++ diepctl, ++ depctl.d32, ++ depctl.d32); ++ } else { ++ start_next_request(ep); ++ } ++ } ++ } ++ } ++ /* NAK Interrutp */ ++ if (diepint.b.nak) { ++ DWC_DEBUGPL(DBG_ANY, "EP%d IN NAK Interrupt\n", ++ epnum); ++ handle_in_ep_nak_intr(pcd, epnum); ++ ++ CLEAR_IN_EP_INTR(core_if, epnum, nak); ++ } ++ } ++ epnum++; ++ ep_intr >>= 1; ++ } ++ ++ return 1; ++#undef CLEAR_IN_EP_INTR ++} ++ ++/** ++ * This interrupt indicates that an OUT EP has a pending Interrupt. ++ * The sequence for handling the OUT EP interrupt is shown below: ++ * -# Read the Device All Endpoint Interrupt register ++ * -# Repeat the following for each OUT EP interrupt bit set (from ++ * LSB to MSB). ++ * -# Read the Device Endpoint Interrupt (DOEPINTn) register ++ * -# If "Transfer Complete" call the request complete function ++ * -# If "Endpoint Disabled" complete the EP disable procedure. ++ * -# If "AHB Error Interrupt" log error ++ * -# If "Setup Phase Done" process Setup Packet (See Standard USB ++ * Command Processing) ++ */ ++static int32_t dwc_otg_pcd_handle_out_ep_intr(dwc_otg_pcd_t * pcd) ++{ ++#define CLEAR_OUT_EP_INTR(__core_if,__epnum,__intr) \ ++do { \ ++ doepint_data_t doepint = {.d32=0}; \ ++ doepint.b.__intr = 1; \ ++ dwc_write_reg32(&__core_if->dev_if->out_ep_regs[__epnum]->doepint, \ ++ doepint.d32); \ ++} while (0) ++ ++ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); ++ dwc_otg_dev_if_t *dev_if = core_if->dev_if; ++ uint32_t ep_intr; ++ doepint_data_t doepint = {.d32 = 0 }; ++ dctl_data_t dctl = {.d32 = 0 }; ++ depctl_data_t doepctl = {.d32 = 0 }; ++ uint32_t epnum = 0; ++ dwc_otg_pcd_ep_t *ep; ++ dwc_ep_t *dwc_ep; ++ ++ DWC_DEBUGPL(DBG_PCDV, "%s()\n", __func__); ++ ++ /* Read in the device interrupt bits */ ++ ep_intr = dwc_otg_read_dev_all_out_ep_intr(core_if); ++ ++ while (ep_intr) { ++ if (ep_intr & 0x1) { ++ /* Get EP pointer */ ++ ep = get_out_ep(pcd, epnum); ++ dwc_ep = &ep->dwc_ep; ++ ++#ifdef VERBOSE ++ DWC_DEBUGPL(DBG_PCDV, ++ "EP%d-%s: type=%d, mps=%d\n", ++ dwc_ep->num, (dwc_ep->is_in ? "IN" : "OUT"), ++ dwc_ep->type, dwc_ep->maxpacket); ++#endif ++ doepint.d32 = ++ dwc_otg_read_dev_out_ep_intr(core_if, dwc_ep); ++ ++ /* Transfer complete */ ++ if (doepint.b.xfercompl) { ++ ++ if (epnum == 0) { ++ /* Clear the bit in DOEPINTn for this interrupt */ ++ CLEAR_OUT_EP_INTR(core_if, epnum, ++ xfercompl); ++ if (core_if->dma_desc_enable == 0 ++ || pcd->ep0state != EP0_IDLE) ++ handle_ep0(pcd); ++#ifdef DWC_EN_ISOC ++ } else if (dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) { ++ if (doepint.b.pktdrpsts == 0) { ++ /* Clear the bit in DOEPINTn for this interrupt */ ++ CLEAR_OUT_EP_INTR(core_if, ++ epnum, ++ xfercompl); ++ complete_iso_ep(pcd, ep); ++ } else { ++ ++ doepint_data_t doepint = {.d32 = ++ 0 }; ++ doepint.b.xfercompl = 1; ++ doepint.b.pktdrpsts = 1; ++ dwc_write_reg32(&core_if-> ++ dev_if-> ++ out_ep_regs ++ [epnum]-> ++ doepint, ++ doepint.d32); ++ if (handle_iso_out_pkt_dropped ++ (core_if, dwc_ep)) { ++ complete_iso_ep(pcd, ++ ep); ++ } ++ } ++#endif /* DWC_EN_ISOC */ ++ } else { ++ /* Clear the bit in DOEPINTn for this interrupt */ ++ CLEAR_OUT_EP_INTR(core_if, epnum, ++ xfercompl); ++ complete_ep(ep); ++ } ++ ++ } ++ ++ /* Endpoint disable */ ++ if (doepint.b.epdisabled) { ++ ++ /* Clear the bit in DOEPINTn for this interrupt */ ++ CLEAR_OUT_EP_INTR(core_if, epnum, epdisabled); ++ } ++ /* AHB Error */ ++ if (doepint.b.ahberr) { ++ DWC_DEBUGPL(DBG_PCD, "EP%d OUT AHB Error\n", ++ epnum); ++ DWC_DEBUGPL(DBG_PCD, "EP DMA REG %d \n", ++ core_if->dev_if-> ++ out_ep_regs[epnum]->doepdma); ++ CLEAR_OUT_EP_INTR(core_if, epnum, ahberr); ++ } ++ /* Setup Phase Done (contorl EPs) */ ++ if (doepint.b.setup) { ++#ifdef DEBUG_EP0 ++ DWC_DEBUGPL(DBG_PCD, "EP%d SETUP Done\n", ++ epnum); ++#endif ++ CLEAR_OUT_EP_INTR(core_if, epnum, setup); ++ ++ handle_ep0(pcd); ++ } ++ ++ /** OUT EP BNA Intr */ ++ if (doepint.b.bna) { ++ CLEAR_OUT_EP_INTR(core_if, epnum, bna); ++ if (core_if->dma_desc_enable) { ++#ifdef DWC_EN_ISOC ++ if (dwc_ep->type == ++ DWC_OTG_EP_TYPE_ISOC) { ++ /* ++ * This checking is performed to prevent first "false" BNA ++ * handling occuring right after reconnect ++ */ ++ if (dwc_ep->next_frame != ++ 0xffffffff) ++ dwc_otg_pcd_handle_iso_bna ++ (ep); ++ } else ++#endif /* DWC_EN_ISOC */ ++ { ++ dctl.d32 = ++ dwc_read_reg32(&dev_if-> ++ dev_global_regs-> ++ dctl); ++ ++ /* If Global Continue on BNA is disabled - disable EP */ ++ if (!dctl.b.gcontbna) { ++ doepctl.d32 = 0; ++ doepctl.b.snak = 1; ++ doepctl.b.epdis = 1; ++ dwc_modify_reg32 ++ (&dev_if-> ++ out_ep_regs ++ [epnum]->doepctl, ++ doepctl.d32, ++ doepctl.d32); ++ } else { ++ start_next_request(ep); ++ } ++ } ++ } ++ } ++ if (doepint.b.stsphsercvd) { ++ CLEAR_OUT_EP_INTR(core_if, epnum, stsphsercvd); ++ if (core_if->dma_desc_enable) { ++ do_setup_in_status_phase(pcd); ++ } ++ } ++ /* Babble Interrutp */ ++ if (doepint.b.babble) { ++ DWC_DEBUGPL(DBG_ANY, "EP%d OUT Babble\n", ++ epnum); ++ handle_out_ep_babble_intr(pcd, epnum); ++ ++ CLEAR_OUT_EP_INTR(core_if, epnum, babble); ++ } ++ /* NAK Interrutp */ ++ if (doepint.b.nak) { ++ DWC_DEBUGPL(DBG_ANY, "EP%d OUT NAK\n", epnum); ++ handle_out_ep_nak_intr(pcd, epnum); ++ ++ CLEAR_OUT_EP_INTR(core_if, epnum, nak); ++ } ++ /* NYET Interrutp */ ++ if (doepint.b.nyet) { ++ DWC_DEBUGPL(DBG_ANY, "EP%d OUT NYET\n", epnum); ++ handle_out_ep_nyet_intr(pcd, epnum); ++ ++ CLEAR_OUT_EP_INTR(core_if, epnum, nyet); ++ } ++ } ++ ++ epnum++; ++ ep_intr >>= 1; ++ } ++ ++ return 1; ++ ++#undef CLEAR_OUT_EP_INTR ++} ++ ++/** ++ * Incomplete ISO IN Transfer Interrupt. ++ * This interrupt indicates one of the following conditions occurred ++ * while transmitting an ISOC transaction. ++ * - Corrupted IN Token for ISOC EP. ++ * - Packet not complete in FIFO. ++ * The follow actions will be taken: ++ * -# Determine the EP ++ * -# Set incomplete flag in dwc_ep structure ++ * -# Disable EP; when "Endpoint Disabled" interrupt is received ++ * Flush FIFO ++ */ ++int32_t dwc_otg_pcd_handle_incomplete_isoc_in_intr(dwc_otg_pcd_t * pcd) ++{ ++ gintsts_data_t gintsts; ++ ++#ifdef DWC_EN_ISOC ++ dwc_otg_dev_if_t *dev_if; ++ deptsiz_data_t deptsiz = {.d32 = 0 }; ++ depctl_data_t depctl = {.d32 = 0 }; ++ dsts_data_t dsts = {.d32 = 0 }; ++ dwc_ep_t *dwc_ep; ++ int i; ++ ++ dev_if = GET_CORE_IF(pcd)->dev_if; ++ ++ for (i = 1; i <= dev_if->num_in_eps; ++i) { ++ dwc_ep = &pcd->in_ep[i].dwc_ep; ++ if (dwc_ep->active && dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) { ++ deptsiz.d32 = ++ dwc_read_reg32(&dev_if->in_ep_regs[i]->dieptsiz); ++ depctl.d32 = ++ dwc_read_reg32(&dev_if->in_ep_regs[i]->diepctl); ++ ++ if (depctl.b.epdis && deptsiz.d32) { ++ set_current_pkt_info(GET_CORE_IF(pcd), dwc_ep); ++ if (dwc_ep->cur_pkt >= dwc_ep->pkt_cnt) { ++ dwc_ep->cur_pkt = 0; ++ dwc_ep->proc_buf_num = ++ (dwc_ep->proc_buf_num ^ 1) & 0x1; ++ ++ if (dwc_ep->proc_buf_num) { ++ dwc_ep->cur_pkt_addr = ++ dwc_ep->xfer_buff1; ++ dwc_ep->cur_pkt_dma_addr = ++ dwc_ep->dma_addr1; ++ } else { ++ dwc_ep->cur_pkt_addr = ++ dwc_ep->xfer_buff0; ++ dwc_ep->cur_pkt_dma_addr = ++ dwc_ep->dma_addr0; ++ } ++ ++ } ++ ++ dsts.d32 = ++ dwc_read_reg32(&GET_CORE_IF(pcd)->dev_if-> ++ dev_global_regs->dsts); ++ dwc_ep->next_frame = dsts.b.soffn; ++ ++ dwc_otg_iso_ep_start_frm_transfer(GET_CORE_IF ++ (pcd), ++ dwc_ep); ++ } ++ } ++ } ++ ++#else ++ gintmsk_data_t intr_mask = {.d32 = 0 }; ++ DWC_PRINTF("INTERRUPT Handler not implemented for %s\n", ++ "IN ISOC Incomplete"); ++ ++ intr_mask.b.incomplisoin = 1; ++ dwc_modify_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk, ++ intr_mask.d32, 0); ++#endif //DWC_EN_ISOC ++ ++ /* Clear interrupt */ ++ gintsts.d32 = 0; ++ gintsts.b.incomplisoin = 1; ++ dwc_write_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintsts, ++ gintsts.d32); ++ ++ return 1; ++} ++ ++/** ++ * Incomplete ISO OUT Transfer Interrupt. ++ * ++ * This interrupt indicates that the core has dropped an ISO OUT ++ * packet. The following conditions can be the cause: ++ * - FIFO Full, the entire packet would not fit in the FIFO. ++ * - CRC Error ++ * - Corrupted Token ++ * The follow actions will be taken: ++ * -# Determine the EP ++ * -# Set incomplete flag in dwc_ep structure ++ * -# Read any data from the FIFO ++ * -# Disable EP. when "Endpoint Disabled" interrupt is received ++ * re-enable EP. ++ */ ++int32_t dwc_otg_pcd_handle_incomplete_isoc_out_intr(dwc_otg_pcd_t * pcd) ++{ ++ ++ gintsts_data_t gintsts; ++ ++#ifdef DWC_EN_ISOC ++ dwc_otg_dev_if_t *dev_if; ++ deptsiz_data_t deptsiz = {.d32 = 0 }; ++ depctl_data_t depctl = {.d32 = 0 }; ++ dsts_data_t dsts = {.d32 = 0 }; ++ dwc_ep_t *dwc_ep; ++ int i; ++ ++ dev_if = GET_CORE_IF(pcd)->dev_if; ++ ++ for (i = 1; i <= dev_if->num_out_eps; ++i) { ++ dwc_ep = &pcd->in_ep[i].dwc_ep; ++ if (pcd->out_ep[i].dwc_ep.active && ++ pcd->out_ep[i].dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) { ++ deptsiz.d32 = ++ dwc_read_reg32(&dev_if->out_ep_regs[i]->doeptsiz); ++ depctl.d32 = ++ dwc_read_reg32(&dev_if->out_ep_regs[i]->doepctl); ++ ++ if (depctl.b.epdis && deptsiz.d32) { ++ set_current_pkt_info(GET_CORE_IF(pcd), ++ &pcd->out_ep[i].dwc_ep); ++ if (dwc_ep->cur_pkt >= dwc_ep->pkt_cnt) { ++ dwc_ep->cur_pkt = 0; ++ dwc_ep->proc_buf_num = ++ (dwc_ep->proc_buf_num ^ 1) & 0x1; ++ ++ if (dwc_ep->proc_buf_num) { ++ dwc_ep->cur_pkt_addr = ++ dwc_ep->xfer_buff1; ++ dwc_ep->cur_pkt_dma_addr = ++ dwc_ep->dma_addr1; ++ } else { ++ dwc_ep->cur_pkt_addr = ++ dwc_ep->xfer_buff0; ++ dwc_ep->cur_pkt_dma_addr = ++ dwc_ep->dma_addr0; ++ } ++ ++ } ++ ++ dsts.d32 = ++ dwc_read_reg32(&GET_CORE_IF(pcd)->dev_if-> ++ dev_global_regs->dsts); ++ dwc_ep->next_frame = dsts.b.soffn; ++ ++ dwc_otg_iso_ep_start_frm_transfer(GET_CORE_IF ++ (pcd), ++ dwc_ep); ++ } ++ } ++ } ++#else ++ /** @todo implement ISR */ ++ gintmsk_data_t intr_mask = {.d32 = 0 }; ++ ++ DWC_PRINTF("INTERRUPT Handler not implemented for %s\n", ++ "OUT ISOC Incomplete"); ++ ++ intr_mask.b.incomplisoout = 1; ++ dwc_modify_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk, ++ intr_mask.d32, 0); ++ ++#endif /* DWC_EN_ISOC */ ++ ++ /* Clear interrupt */ ++ gintsts.d32 = 0; ++ gintsts.b.incomplisoout = 1; ++ dwc_write_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintsts, ++ gintsts.d32); ++ ++ return 1; ++} ++ ++/** ++ * This function handles the Global IN NAK Effective interrupt. ++ * ++ */ ++int32_t dwc_otg_pcd_handle_in_nak_effective(dwc_otg_pcd_t * pcd) ++{ ++ dwc_otg_dev_if_t *dev_if = GET_CORE_IF(pcd)->dev_if; ++ depctl_data_t diepctl = {.d32 = 0 }; ++ depctl_data_t diepctl_rd = {.d32 = 0 }; ++ gintmsk_data_t intr_mask = {.d32 = 0 }; ++ gintsts_data_t gintsts; ++ int i; ++ ++ DWC_DEBUGPL(DBG_PCD, "Global IN NAK Effective\n"); ++ ++ /* Disable all active IN EPs */ ++ diepctl.b.epdis = 1; ++ diepctl.b.snak = 1; ++ ++ for (i = 0; i <= dev_if->num_in_eps; i++) { ++ diepctl_rd.d32 = ++ dwc_read_reg32(&dev_if->in_ep_regs[i]->diepctl); ++ if (diepctl_rd.b.epena) { ++ dwc_write_reg32(&dev_if->in_ep_regs[i]->diepctl, ++ diepctl.d32); ++ } ++ } ++ /* Disable the Global IN NAK Effective Interrupt */ ++ intr_mask.b.ginnakeff = 1; ++ dwc_modify_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk, ++ intr_mask.d32, 0); ++ ++ /* Clear interrupt */ ++ gintsts.d32 = 0; ++ gintsts.b.ginnakeff = 1; ++ dwc_write_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintsts, ++ gintsts.d32); ++ ++ return 1; ++} ++ ++/** ++ * OUT NAK Effective. ++ * ++ */ ++int32_t dwc_otg_pcd_handle_out_nak_effective(dwc_otg_pcd_t * pcd) ++{ ++ gintmsk_data_t intr_mask = {.d32 = 0 }; ++ gintsts_data_t gintsts; ++ ++ DWC_PRINTF("INTERRUPT Handler not implemented for %s\n", ++ "Global IN NAK Effective\n"); ++ /* Disable the Global IN NAK Effective Interrupt */ ++ intr_mask.b.goutnakeff = 1; ++ dwc_modify_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk, ++ intr_mask.d32, 0); ++ ++ /* Clear interrupt */ ++ gintsts.d32 = 0; ++ gintsts.b.goutnakeff = 1; ++ dwc_write_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintsts, ++ gintsts.d32); ++ ++ return 1; ++} ++ ++/** ++ * PCD interrupt handler. ++ * ++ * The PCD handles the device interrupts. Many conditions can cause a ++ * device interrupt. When an interrupt occurs, the device interrupt ++ * service routine determines the cause of the interrupt and ++ * dispatches handling to the appropriate function. These interrupt ++ * handling functions are described below. ++ * ++ * All interrupt registers are processed from LSB to MSB. ++ * ++ */ ++int32_t dwc_otg_pcd_handle_intr(dwc_otg_pcd_t * pcd) ++{ ++ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); ++#ifdef VERBOSE ++ dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs; ++#endif ++ gintsts_data_t gintr_status; ++ int32_t retval = 0; ++ ++#ifdef VERBOSE ++ DWC_DEBUGPL(DBG_ANY, "%s() gintsts=%08x gintmsk=%08x\n", ++ __func__, ++ dwc_read_reg32(&global_regs->gintsts), ++ dwc_read_reg32(&global_regs->gintmsk)); ++#endif ++ ++ if (dwc_otg_is_device_mode(core_if)) { ++ DWC_SPINLOCK(pcd->lock); ++#ifdef VERBOSE ++ DWC_DEBUGPL(DBG_PCDV, "%s() gintsts=%08x gintmsk=%08x\n", ++ __func__, ++ dwc_read_reg32(&global_regs->gintsts), ++ dwc_read_reg32(&global_regs->gintmsk)); ++#endif ++ ++ gintr_status.d32 = dwc_otg_read_core_intr(core_if); ++ ++ DWC_DEBUGPL(DBG_PCDV, "%s: gintsts&gintmsk=%08x\n", ++ __func__, gintr_status.d32); ++ ++ if (gintr_status.b.sofintr) { ++ retval |= dwc_otg_pcd_handle_sof_intr(pcd); ++ } ++ if (gintr_status.b.rxstsqlvl) { ++ retval |= ++ dwc_otg_pcd_handle_rx_status_q_level_intr(pcd); ++ } ++ if (gintr_status.b.nptxfempty) { ++ retval |= dwc_otg_pcd_handle_np_tx_fifo_empty_intr(pcd); ++ } ++ if (gintr_status.b.ginnakeff) { ++ retval |= dwc_otg_pcd_handle_in_nak_effective(pcd); ++ } ++ if (gintr_status.b.goutnakeff) { ++ retval |= dwc_otg_pcd_handle_out_nak_effective(pcd); ++ } ++ if (gintr_status.b.i2cintr) { ++ retval |= dwc_otg_pcd_handle_i2c_intr(pcd); ++ } ++ if (gintr_status.b.erlysuspend) { ++ retval |= dwc_otg_pcd_handle_early_suspend_intr(pcd); ++ } ++ if (gintr_status.b.usbreset) { ++ retval |= dwc_otg_pcd_handle_usb_reset_intr(pcd); ++ } ++ if (gintr_status.b.enumdone) { ++ retval |= dwc_otg_pcd_handle_enum_done_intr(pcd); ++ } ++ if (gintr_status.b.isooutdrop) { ++ retval |= ++ dwc_otg_pcd_handle_isoc_out_packet_dropped_intr ++ (pcd); ++ } ++ if (gintr_status.b.eopframe) { ++ retval |= ++ dwc_otg_pcd_handle_end_periodic_frame_intr(pcd); ++ } ++ if (gintr_status.b.epmismatch) { ++ retval |= dwc_otg_pcd_handle_ep_mismatch_intr(core_if); ++ } ++ if (gintr_status.b.inepint) { ++ if (!core_if->multiproc_int_enable) { ++ retval |= dwc_otg_pcd_handle_in_ep_intr(pcd); ++ } ++ } ++ if (gintr_status.b.outepintr) { ++ if (!core_if->multiproc_int_enable) { ++ retval |= dwc_otg_pcd_handle_out_ep_intr(pcd); ++ } ++ } ++ if (gintr_status.b.incomplisoin) { ++ retval |= ++ dwc_otg_pcd_handle_incomplete_isoc_in_intr(pcd); ++ } ++ if (gintr_status.b.incomplisoout) { ++ retval |= ++ dwc_otg_pcd_handle_incomplete_isoc_out_intr(pcd); ++ } ++ ++ /* In MPI mode De vice Endpoints intterrupts are asserted ++ * without setting outepintr and inepint bits set, so these ++ * Interrupt handlers are called without checking these bit-fields ++ */ ++ if (core_if->multiproc_int_enable) { ++ retval |= dwc_otg_pcd_handle_in_ep_intr(pcd); ++ retval |= dwc_otg_pcd_handle_out_ep_intr(pcd); ++ } ++#ifdef VERBOSE ++ DWC_DEBUGPL(DBG_PCDV, "%s() gintsts=%0x\n", __func__, ++ dwc_read_reg32(&global_regs->gintsts)); ++#endif ++ DWC_SPINUNLOCK(pcd->lock); ++ } ++ return retval; ++} ++ ++#endif /* DWC_HOST_ONLY */ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_pcd_linux.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_pcd_linux.c 2013-07-26 19:31:23.000000000 +0000 +@@ -0,0 +1,1288 @@ ++ /* ========================================================================== ++ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_pcd_linux.c $ ++ * $Revision: #7 $ ++ * $Date: 2009/04/03 $ ++ * $Change: 1225160 $ ++ * ++ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, ++ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless ++ * otherwise expressly agreed to in writing between Synopsys and you. ++ * ++ * The Software IS NOT an item of Licensed Software or Licensed Product under ++ * any End User Software License Agreement or Agreement for Licensed Product ++ * with Synopsys or any supplement thereto. You are permitted to use and ++ * redistribute this Software in source and binary forms, with or without ++ * modification, provided that redistributions of source code must retain this ++ * notice. You may not view, use, disclose, copy or distribute this file or ++ * any information contained herein except pursuant to this license grant from ++ * Synopsys. If you do not agree with this notice, including the disclaimer ++ * below, then you are not authorized to use the Software. ++ * ++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, ++ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR ++ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER ++ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY ++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH ++ * DAMAGE. ++ * ========================================================================== */ ++#ifndef DWC_HOST_ONLY ++ ++/** @file ++ * This file implements the Peripheral Controller Driver. ++ * ++ * The Peripheral Controller Driver (PCD) is responsible for ++ * translating requests from the Function Driver into the appropriate ++ * actions on the DWC_otg controller. It isolates the Function Driver ++ * from the specifics of the controller by providing an API to the ++ * Function Driver. ++ * ++ * The Peripheral Controller Driver for Linux will implement the ++ * Gadget API, so that the existing Gadget drivers can be used. ++ * (Gadget Driver is the Linux terminology for a Function Driver.) ++ * ++ * The Linux Gadget API is defined in the header file ++ * . The USB EP operations API is ++ * defined in the structure usb_ep_ops and the USB ++ * Controller API is defined in the structure ++ * usb_gadget_ops. ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#if defined(LM_INTERFACE) ++//# include ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30)) ++#include ++#else ++/* by 2.6.31, at least, the location of some headers has changed ++*/ ++#include ++#endif ++ ++#elif defined(PLATFORM_INTERFACE) ++#include ++#endif ++ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30)) ++#include ++#include ++#include ++#else ++/* by 2.6.31, at least, the location of some headers has changed ++*/ ++#include ++#include ++#include ++#endif ++ ++#include ++ ++#include "dwc_otg_pcd_if.h" ++#include "dwc_otg_driver.h" ++#include "dwc_otg_dbg.h" ++ ++static struct gadget_wrapper { ++ dwc_otg_pcd_t *pcd; ++ ++ struct usb_gadget gadget; ++ struct usb_gadget_driver *driver; ++ ++ struct usb_ep ep0; ++ struct usb_ep in_ep[16]; ++ struct usb_ep out_ep[16]; ++ ++} *gadget_wrapper; ++ ++/* Display the contents of the buffer */ ++extern void dump_msg(const u8 * buf, unsigned int length); ++ ++/* USB Endpoint Operations */ ++/* ++ * The following sections briefly describe the behavior of the Gadget ++ * API endpoint operations implemented in the DWC_otg driver ++ * software. Detailed descriptions of the generic behavior of each of ++ * these functions can be found in the Linux header file ++ * include/linux/usb_gadget.h. ++ * ++ * The Gadget API provides wrapper functions for each of the function ++ * pointers defined in usb_ep_ops. The Gadget Driver calls the wrapper ++ * function, which then calls the underlying PCD function. The ++ * following sections are named according to the wrapper ++ * functions. Within each section, the corresponding DWC_otg PCD ++ * function name is specified. ++ * ++ */ ++ ++/** ++ * This function is called by the Gadget Driver for each EP to be ++ * configured for the current configuration (SET_CONFIGURATION). ++ * ++ * This function initializes the dwc_otg_ep_t data structure, and then ++ * calls dwc_otg_ep_activate. ++ */ ++static int ep_enable(struct usb_ep *usb_ep, ++ const struct usb_endpoint_descriptor *ep_desc) ++{ ++ int retval; ++ ++ DWC_DEBUGPL(DBG_PCDV, "%s(%p,%p)\n", __func__, usb_ep, ep_desc); ++ ++ if (!usb_ep || !ep_desc || ep_desc->bDescriptorType != USB_DT_ENDPOINT) { ++ DWC_WARN("%s, bad ep or descriptor\n", __func__); ++ return -EINVAL; ++ } ++ if (usb_ep == &gadget_wrapper->ep0) { ++ DWC_WARN("%s, bad ep(0)\n", __func__); ++ return -EINVAL; ++ } ++ ++ /* Check FIFO size? */ ++ if (!ep_desc->wMaxPacketSize) { ++ DWC_WARN("%s, bad %s maxpacket\n", __func__, usb_ep->name); ++ return -ERANGE; ++ } ++ ++ if (!gadget_wrapper->driver || ++ gadget_wrapper->gadget.speed == USB_SPEED_UNKNOWN) { ++ DWC_WARN("%s, bogus device state\n", __func__); ++ return -ESHUTDOWN; ++ } ++ ++ retval = dwc_otg_pcd_ep_enable(gadget_wrapper->pcd, ++ (const uint8_t *)ep_desc, ++ (void *)usb_ep); ++ if (retval) { ++ DWC_WARN("dwc_otg_pcd_ep_enable failed\n"); ++ return -EINVAL; ++ } ++ ++ usb_ep->maxpacket = le16_to_cpu(ep_desc->wMaxPacketSize); ++ ++ return 0; ++} ++ ++/** ++ * This function is called when an EP is disabled due to disconnect or ++ * change in configuration. Any pending requests will terminate with a ++ * status of -ESHUTDOWN. ++ * ++ * This function modifies the dwc_otg_ep_t data structure for this EP, ++ * and then calls dwc_otg_ep_deactivate. ++ */ ++static int ep_disable(struct usb_ep *usb_ep) ++{ ++ int retval; ++ ++ DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, usb_ep); ++ if (!usb_ep) { ++ DWC_DEBUGPL(DBG_PCD, "%s, %s not enabled\n", __func__, ++ usb_ep ? usb_ep->name : NULL); ++ return -EINVAL; ++ } ++ ++ retval = dwc_otg_pcd_ep_disable(gadget_wrapper->pcd, usb_ep); ++ if (retval) { ++ retval = -EINVAL; ++ } ++ ++ return retval; ++} ++ ++/** ++ * This function allocates a request object to use with the specified ++ * endpoint. ++ * ++ * @param ep The endpoint to be used with with the request ++ * @param gfp_flags the GFP_* flags to use. ++ */ ++static struct usb_request *dwc_otg_pcd_alloc_request(struct usb_ep *ep, ++ gfp_t gfp_flags) ++{ ++ struct usb_request *usb_req; ++ ++ DWC_DEBUGPL(DBG_PCDV, "%s(%p,%d)\n", __func__, ep, gfp_flags); ++ if (0 == ep) { ++ DWC_WARN("%s() %s\n", __func__, "Invalid EP!\n"); ++ return 0; ++ } ++ usb_req = kmalloc(sizeof(*usb_req), gfp_flags); ++ if (0 == usb_req) { ++ DWC_WARN("%s() %s\n", __func__, "request allocation failed!\n"); ++ return 0; ++ } ++ memset(usb_req, 0, sizeof(*usb_req)); ++ usb_req->dma = DWC_INVALID_DMA_ADDR; ++ ++ return usb_req; ++} ++ ++/** ++ * This function frees a request object. ++ * ++ * @param ep The endpoint associated with the request ++ * @param req The request being freed ++ */ ++static void dwc_otg_pcd_free_request(struct usb_ep *ep, struct usb_request *req) ++{ ++ DWC_DEBUGPL(DBG_PCDV, "%s(%p,%p)\n", __func__, ep, req); ++ ++ if (0 == ep || 0 == req) { ++ DWC_WARN("%s() %s\n", __func__, ++ "Invalid ep or req argument!\n"); ++ return; ++ } ++ ++ kfree(req); ++} ++ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30)) ++/** ++ * This function allocates an I/O buffer to be used for a transfer ++ * to/from the specified endpoint. ++ * ++ * @param usb_ep The endpoint to be used with with the request ++ * @param bytes The desired number of bytes for the buffer ++ * @param dma Pointer to the buffer's DMA address; must be valid ++ * @param gfp_flags the GFP_* flags to use. ++ * @return address of a new buffer or null is buffer could not be allocated. ++ */ ++static void *dwc_otg_pcd_alloc_buffer(struct usb_ep *usb_ep, unsigned bytes, ++ dma_addr_t * dma, gfp_t gfp_flags) ++{ ++ void *buf; ++ dwc_otg_pcd_t *pcd = 0; ++ ++ pcd = gadget_wrapper->pcd; ++ ++ DWC_DEBUGPL(DBG_PCDV, "%s(%p,%d,%p,%0x)\n", __func__, usb_ep, bytes, ++ dma, gfp_flags); ++ ++ /* Check dword alignment */ ++ if ((bytes & 0x3UL) != 0) { ++ DWC_WARN("%s() Buffer size is not a multiple of" ++ "DWORD size (%d)", __func__, bytes); ++ } ++ ++ buf = dma_alloc_coherent(NULL, bytes, dma, gfp_flags); ++ ++ /* Check dword alignment */ ++ if (((int)buf & 0x3UL) != 0) { ++ DWC_WARN("%s() Buffer is not DWORD aligned (%p)", ++ __func__, buf); ++ } ++ ++ return buf; ++} ++ ++/** ++ * This function frees an I/O buffer that was allocated by alloc_buffer. ++ * ++ * @param usb_ep the endpoint associated with the buffer ++ * @param buf address of the buffer ++ * @param dma The buffer's DMA address ++ * @param bytes The number of bytes of the buffer ++ */ ++static void dwc_otg_pcd_free_buffer(struct usb_ep *usb_ep, void *buf, ++ dma_addr_t dma, unsigned bytes) ++{ ++ dwc_otg_pcd_t *pcd = 0; ++ ++ pcd = gadget_wrapper->pcd; ++ ++ DWC_DEBUGPL(DBG_PCDV, "%s(%p,%0x,%d)\n", __func__, buf, dma, bytes); ++ ++ dma_free_coherent(NULL, bytes, buf, dma); ++} ++#endif ++ ++/** ++ * This function is used to submit an I/O Request to an EP. ++ * ++ * - When the request completes the request's completion callback ++ * is called to return the request to the driver. ++ * - An EP, except control EPs, may have multiple requests ++ * pending. ++ * - Once submitted the request cannot be examined or modified. ++ * - Each request is turned into one or more packets. ++ * - A BULK EP can queue any amount of data; the transfer is ++ * packetized. ++ * - Zero length Packets are specified with the request 'zero' ++ * flag. ++ */ ++static int ep_queue(struct usb_ep *usb_ep, struct usb_request *usb_req, ++ gfp_t gfp_flags) ++{ ++ dwc_otg_pcd_t *pcd; ++ int retval; ++ ++ DWC_DEBUGPL(DBG_PCDV, "%s(%p,%p,%d)\n", ++ __func__, usb_ep, usb_req, gfp_flags); ++ ++ if (!usb_req || !usb_req->complete || !usb_req->buf) { ++ DWC_WARN("bad params\n"); ++ return -EINVAL; ++ } ++ ++ if (!usb_ep) { ++ DWC_WARN("bad ep\n"); ++ return -EINVAL; ++ } ++ ++ pcd = gadget_wrapper->pcd; ++ if (!gadget_wrapper->driver || ++ gadget_wrapper->gadget.speed == USB_SPEED_UNKNOWN) { ++ DWC_DEBUGPL(DBG_PCDV, "gadget.speed=%d\n", ++ gadget_wrapper->gadget.speed); ++ DWC_WARN("bogus device state\n"); ++ return -ESHUTDOWN; ++ } ++ ++ DWC_DEBUGPL(DBG_PCD, "%s queue req %p, len %d buf %p\n", ++ usb_ep->name, usb_req, usb_req->length, usb_req->buf); ++ ++ usb_req->status = -EINPROGRESS; ++ usb_req->actual = 0; ++ ++ retval = dwc_otg_pcd_ep_queue(pcd, usb_ep, usb_req->buf, usb_req->dma, ++ usb_req->length, usb_req->zero, usb_req, ++ gfp_flags == GFP_ATOMIC ? 1 : 0); ++ if (retval) { ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++/** ++ * This function cancels an I/O request from an EP. ++ */ ++static int ep_dequeue(struct usb_ep *usb_ep, struct usb_request *usb_req) ++{ ++ DWC_DEBUGPL(DBG_PCDV, "%s(%p,%p)\n", __func__, usb_ep, usb_req); ++ ++ if (!usb_ep || !usb_req) { ++ DWC_WARN("bad argument\n"); ++ return -EINVAL; ++ } ++ if (!gadget_wrapper->driver || ++ gadget_wrapper->gadget.speed == USB_SPEED_UNKNOWN) { ++ DWC_WARN("bogus device state\n"); ++ return -ESHUTDOWN; ++ } ++ if (dwc_otg_pcd_ep_dequeue(gadget_wrapper->pcd, usb_ep, usb_req)) { ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++/** ++ * usb_ep_set_halt stalls an endpoint. ++ * ++ * usb_ep_clear_halt clears an endpoint halt and resets its data ++ * toggle. ++ * ++ * Both of these functions are implemented with the same underlying ++ * function. The behavior depends on the value argument. ++ * ++ * @param[in] usb_ep the Endpoint to halt or clear halt. ++ * @param[in] value ++ * - 0 means clear_halt. ++ * - 1 means set_halt, ++ * - 2 means clear stall lock flag. ++ * - 3 means set stall lock flag. ++ */ ++static int ep_halt(struct usb_ep *usb_ep, int value) ++{ ++ int retval = 0; ++ ++ DWC_DEBUGPL(DBG_PCD, "HALT %s %d\n", usb_ep->name, value); ++ ++ if (!usb_ep) { ++ DWC_WARN("bad ep\n"); ++ return -EINVAL; ++ } ++ ++ retval = dwc_otg_pcd_ep_halt(gadget_wrapper->pcd, usb_ep, value); ++ if (retval == -DWC_E_AGAIN) { ++ return -EAGAIN; ++ } else if (retval) { ++ retval = -EINVAL; ++ } ++ ++ return retval; ++} ++ ++//#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,30)) ++#if 0 ++/** ++ * ep_wedge: sets the halt feature and ignores clear requests ++ * ++ * @usb_ep: the endpoint being wedged ++ * ++ * Use this to stall an endpoint and ignore CLEAR_FEATURE(HALT_ENDPOINT) ++ * requests. If the gadget driver clears the halt status, it will ++ * automatically unwedge the endpoint. ++ * ++ * Returns zero on success, else negative errno. * ++ * Check usb_ep_set_wedge() at "usb_gadget.h" for details ++ */ ++static int ep_wedge(struct usb_ep *usb_ep) ++{ ++ int retval = 0; ++ ++ DWC_DEBUGPL(DBG_PCD, "WEDGE %s\n", usb_ep->name); ++ ++ if (!usb_ep) { ++ DWC_WARN("bad ep\n"); ++ return -EINVAL; ++ } ++ ++ retval = dwc_otg_pcd_ep_wedge(gadget_wrapper->pcd, usb_ep); ++ if (retval == -DWC_E_AGAIN) { ++ retval = -EAGAIN; ++ } else if (retval) { ++ retval = -EINVAL; ++ } ++ ++ return retval; ++} ++#endif ++ ++#ifdef DWC_EN_ISOC ++/** ++ * This function is used to submit an ISOC Transfer Request to an EP. ++ * ++ * - Every time a sync period completes the request's completion callback ++ * is called to provide data to the gadget driver. ++ * - Once submitted the request cannot be modified. ++ * - Each request is turned into periodic data packets untill ISO ++ * Transfer is stopped.. ++ */ ++static int iso_ep_start(struct usb_ep *usb_ep, struct usb_iso_request *req, ++ gfp_t gfp_flags) ++{ ++ int retval = 0; ++ ++ if (!req || !req->process_buffer || !req->buf0 || !req->buf1) { ++ DWC_WARN("bad params\n"); ++ return -EINVAL; ++ } ++ ++ if (!usb_ep) { ++ DWC_PRINTF("bad params\n"); ++ return -EINVAL; ++ } ++ ++ req->status = -EINPROGRESS; ++ ++ retval = ++ dwc_otg_pcd_iso_ep_start(gadget_wrapper->pcd, usb_ep, req->buf0, ++ req->buf1, req->dma0, req->dma1, ++ req->sync_frame, req->data_pattern_frame, ++ req->data_per_frame, ++ req->flags & USB_REQ_ISO_ASAP ? -1 : req-> ++ start_frame, req->buf_proc_intrvl, req, ++ gfp_flags == GFP_ATOMIC ? 1 : 0); ++ ++ if (retval) { ++ return -EINVAL; ++ } ++ ++ return retval; ++} ++ ++/** ++ * This function stops ISO EP Periodic Data Transfer. ++ */ ++static int iso_ep_stop(struct usb_ep *usb_ep, struct usb_iso_request *req) ++{ ++ int retval = 0; ++ if (!usb_ep) { ++ DWC_WARN("bad ep\n"); ++ } ++ ++ if (!gadget_wrapper->driver || ++ gadget_wrapper->gadget.speed == USB_SPEED_UNKNOWN) { ++ DWC_DEBUGPL(DBG_PCDV, "gadget.speed=%d\n", ++ gadget_wrapper->gadget.speed); ++ DWC_WARN("bogus device state\n"); ++ } ++ ++ dwc_otg_pcd_iso_ep_stop(gadget_wrapper->pcd, usb_ep, req); ++ if (retval) { ++ retval = -EINVAL; ++ } ++ ++ return retval; ++} ++ ++static struct usb_iso_request *alloc_iso_request(struct usb_ep *ep, ++ int packets, gfp_t gfp_flags) ++{ ++ struct usb_iso_request *pReq = NULL; ++ uint32_t req_size; ++ ++ req_size = sizeof(struct usb_iso_request); ++ req_size += ++ (2 * packets * (sizeof(struct usb_gadget_iso_packet_descriptor))); ++ ++ pReq = kmalloc(req_size, gfp_flags); ++ if (!pReq) { ++ DWC_WARN("Can't allocate Iso Request\n"); ++ return 0; ++ } ++ pReq->iso_packet_desc0 = (void *)(pReq + 1); ++ ++ pReq->iso_packet_desc1 = pReq->iso_packet_desc0 + packets; ++ ++ return pReq; ++} ++ ++static void free_iso_request(struct usb_ep *ep, struct usb_iso_request *req) ++{ ++ kfree(req); ++} ++ ++static struct usb_isoc_ep_ops dwc_otg_pcd_ep_ops = { ++ .ep_ops = { ++ .enable = ep_enable, ++ .disable = ep_disable, ++ ++ .alloc_request = dwc_otg_pcd_alloc_request, ++ .free_request = dwc_otg_pcd_free_request, ++ ++ .alloc_buffer = dwc_otg_pcd_alloc_buffer, ++ .free_buffer = dwc_otg_pcd_free_buffer, ++ ++ .queue = ep_queue, ++ .dequeue = ep_dequeue, ++ ++ .set_halt = ep_halt, ++ .fifo_status = 0, ++ .fifo_flush = 0, ++ }, ++ .iso_ep_start = iso_ep_start, ++ .iso_ep_stop = iso_ep_stop, ++ .alloc_iso_request = alloc_iso_request, ++ .free_iso_request = free_iso_request, ++}; ++ ++#else ++ ++ int (*enable) (struct usb_ep *ep, ++ const struct usb_endpoint_descriptor *desc); ++ int (*disable) (struct usb_ep *ep); ++ ++ struct usb_request *(*alloc_request) (struct usb_ep *ep, ++ gfp_t gfp_flags); ++ void (*free_request) (struct usb_ep *ep, struct usb_request *req); ++ ++ int (*queue) (struct usb_ep *ep, struct usb_request *req, ++ gfp_t gfp_flags); ++ int (*dequeue) (struct usb_ep *ep, struct usb_request *req); ++ ++ int (*set_halt) (struct usb_ep *ep, int value); ++ int (*set_wedge) (struct usb_ep *ep); ++ ++ int (*fifo_status) (struct usb_ep *ep); ++ void (*fifo_flush) (struct usb_ep *ep); ++static struct usb_ep_ops dwc_otg_pcd_ep_ops = { ++ .enable = ep_enable, ++ .disable = ep_disable, ++ ++ .alloc_request = dwc_otg_pcd_alloc_request, ++ .free_request = dwc_otg_pcd_free_request, ++ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30)) ++ .alloc_buffer = dwc_otg_pcd_alloc_buffer, ++ .free_buffer = dwc_otg_pcd_free_buffer, ++#else ++ /* .set_wedge = ep_wedge, */ ++ .set_wedge = NULL, /* uses set_halt instead */ ++#endif ++ ++ .queue = ep_queue, ++ .dequeue = ep_dequeue, ++ ++ .set_halt = ep_halt, ++ .fifo_status = 0, ++ .fifo_flush = 0, ++ ++}; ++ ++#endif /* _EN_ISOC_ */ ++/* Gadget Operations */ ++/** ++ * The following gadget operations will be implemented in the DWC_otg ++ * PCD. Functions in the API that are not described below are not ++ * implemented. ++ * ++ * The Gadget API provides wrapper functions for each of the function ++ * pointers defined in usb_gadget_ops. The Gadget Driver calls the ++ * wrapper function, which then calls the underlying PCD function. The ++ * following sections are named according to the wrapper functions ++ * (except for ioctl, which doesn't have a wrapper function). Within ++ * each section, the corresponding DWC_otg PCD function name is ++ * specified. ++ * ++ */ ++ ++/** ++ *Gets the USB Frame number of the last SOF. ++ */ ++static int get_frame_number(struct usb_gadget *gadget) ++{ ++ struct gadget_wrapper *d; ++ ++ DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, gadget); ++ ++ if (gadget == 0) { ++ return -ENODEV; ++ } ++ ++ d = container_of(gadget, struct gadget_wrapper, gadget); ++ return dwc_otg_pcd_get_frame_number(d->pcd); ++} ++ ++#ifdef CONFIG_USB_DWC_OTG_LPM ++static int test_lpm_enabled(struct usb_gadget *gadget) ++{ ++ struct gadget_wrapper *d; ++ ++ d = container_of(gadget, struct gadget_wrapper, gadget); ++ ++ return dwc_otg_pcd_is_lpm_enabled(d->pcd); ++} ++#endif ++ ++/** ++ * Initiates Session Request Protocol (SRP) to wakeup the host if no ++ * session is in progress. If a session is already in progress, but ++ * the device is suspended, remote wakeup signaling is started. ++ * ++ */ ++static int wakeup(struct usb_gadget *gadget) ++{ ++ struct gadget_wrapper *d; ++ ++ DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, gadget); ++ ++ if (gadget == 0) { ++ return -ENODEV; ++ } else { ++ d = container_of(gadget, struct gadget_wrapper, gadget); ++ } ++ dwc_otg_pcd_wakeup(d->pcd); ++ return 0; ++} ++ ++static const struct usb_gadget_ops dwc_otg_pcd_ops = { ++ .get_frame = get_frame_number, ++ .wakeup = wakeup, ++#ifdef CONFIG_USB_DWC_OTG_LPM ++ .lpm_support = test_lpm_enabled, ++#endif ++ // current versions must always be self-powered ++}; ++ ++static int _setup(dwc_otg_pcd_t * pcd, uint8_t * bytes) ++{ ++ int retval = -DWC_E_NOT_SUPPORTED; ++ if (gadget_wrapper->driver && gadget_wrapper->driver->setup) { ++ retval = gadget_wrapper->driver->setup(&gadget_wrapper->gadget, ++ (struct usb_ctrlrequest ++ *)bytes); ++ } ++ ++ if (retval == -ENOTSUPP) { ++ retval = -DWC_E_NOT_SUPPORTED; ++ } else if (retval < 0) { ++ retval = -DWC_E_INVALID; ++ } ++ ++ return retval; ++} ++ ++#ifdef DWC_EN_ISOC ++static int _isoc_complete(dwc_otg_pcd_t * pcd, void *ep_handle, ++ void *req_handle, int proc_buf_num) ++{ ++ int i, packet_count; ++ struct usb_gadget_iso_packet_descriptor *iso_packet = 0; ++ struct usb_iso_request *iso_req = req_handle; ++ ++ if (proc_buf_num) { ++ iso_packet = iso_req->iso_packet_desc1; ++ } else { ++ iso_packet = iso_req->iso_packet_desc0; ++ } ++ packet_count = ++ dwc_otg_pcd_get_iso_packet_count(pcd, ep_handle, req_handle); ++ for (i = 0; i < packet_count; ++i) { ++ int status; ++ int actual; ++ int offset; ++ dwc_otg_pcd_get_iso_packet_params(pcd, ep_handle, req_handle, ++ i, &status, &actual, &offset); ++ switch (status) { ++ case -DWC_E_NO_DATA: ++ status = -ENODATA; ++ break; ++ default: ++ if (status) { ++ DWC_PRINTF("unknown status in isoc packet\n"); ++ } ++ ++ } ++ iso_packet[i].status = status; ++ iso_packet[i].offset = offset; ++ iso_packet[i].actual_length = actual; ++ } ++ ++ iso_req->status = 0; ++ iso_req->process_buffer(ep_handle, iso_req); ++ ++ return 0; ++} ++#endif /* DWC_EN_ISOC */ ++ ++static int _complete(dwc_otg_pcd_t * pcd, void *ep_handle, ++ void *req_handle, int32_t status, uint32_t actual) ++{ ++ struct usb_request *req = (struct usb_request *)req_handle; ++ ++ if (req && req->complete) { ++ switch (status) { ++ case -DWC_E_SHUTDOWN: ++ req->status = -ESHUTDOWN; ++ break; ++ case -DWC_E_RESTART: ++ req->status = -ECONNRESET; ++ break; ++ case -DWC_E_INVALID: ++ req->status = -EINVAL; ++ break; ++ case -DWC_E_TIMEOUT: ++ req->status = -ETIMEDOUT; ++ break; ++ default: ++ req->status = status; ++ ++ } ++ req->actual = actual; ++ req->complete(ep_handle, req); ++ } ++ ++ return 0; ++} ++ ++static int _connect(dwc_otg_pcd_t * pcd, int speed) ++{ ++ gadget_wrapper->gadget.speed = speed; ++ return 0; ++} ++ ++static int _disconnect(dwc_otg_pcd_t * pcd) ++{ ++ if (gadget_wrapper->driver && gadget_wrapper->driver->disconnect) { ++ gadget_wrapper->driver->disconnect(&gadget_wrapper->gadget); ++ } ++ return 0; ++} ++ ++static int _resume(dwc_otg_pcd_t * pcd) ++{ ++ if (gadget_wrapper->driver && gadget_wrapper->driver->resume) { ++ gadget_wrapper->driver->resume(&gadget_wrapper->gadget); ++ } ++ ++ return 0; ++} ++ ++static int _suspend(dwc_otg_pcd_t * pcd) ++{ ++ if (gadget_wrapper->driver && gadget_wrapper->driver->suspend) { ++ gadget_wrapper->driver->suspend(&gadget_wrapper->gadget); ++ } ++ return 0; ++} ++ ++/** ++ * This function updates the otg values in the gadget structure. ++ */ ++static int _hnp_changed(dwc_otg_pcd_t * pcd) ++{ ++ ++ if (!gadget_wrapper->gadget.is_otg) ++ return 0; ++ ++ gadget_wrapper->gadget.b_hnp_enable = get_b_hnp_enable(pcd); ++ gadget_wrapper->gadget.a_hnp_support = get_a_hnp_support(pcd); ++ gadget_wrapper->gadget.a_alt_hnp_support = get_a_alt_hnp_support(pcd); ++ return 0; ++} ++ ++static int _reset(dwc_otg_pcd_t * pcd) ++{ ++ return 0; ++} ++ ++#ifdef DWC_UTE_CFI ++static int _cfi_setup(dwc_otg_pcd_t * pcd, void *cfi_req) ++{ ++ int retval = -DWC_E_INVALID; ++ if (gadget_wrapper->driver->cfi_feature_setup) { ++ retval = ++ gadget_wrapper->driver->cfi_feature_setup(&gadget_wrapper-> ++ gadget, ++ (struct ++ cfi_usb_ctrlrequest ++ *)cfi_req); ++ } ++ ++ return retval; ++} ++#endif ++ ++static const struct dwc_otg_pcd_function_ops fops = { ++ .complete = _complete, ++#ifdef DWC_EN_ISOC ++ .isoc_complete = _isoc_complete, ++#endif ++ .setup = _setup, ++ .disconnect = _disconnect, ++ .connect = _connect, ++ .resume = _resume, ++ .suspend = _suspend, ++ .hnp_changed = _hnp_changed, ++ .reset = _reset, ++#ifdef DWC_UTE_CFI ++ .cfi_setup = _cfi_setup, ++#endif ++}; ++ ++/** ++ * This function is the top level PCD interrupt handler. ++ */ ++static irqreturn_t dwc_otg_pcd_irq(int irq, void *dev) ++{ ++ dwc_otg_pcd_t *pcd = dev; ++ int32_t retval = IRQ_NONE; ++ ++ retval = dwc_otg_pcd_handle_intr(pcd); ++ if (retval != 0) { ++ S3C2410X_CLEAR_EINTPEND(); ++ } ++ return IRQ_RETVAL(retval); ++} ++ ++/** ++ * This function initialized the usb_ep structures to there default ++ * state. ++ * ++ * @param d Pointer on gadget_wrapper. ++ */ ++void gadget_add_eps(struct gadget_wrapper *d) ++{ ++ static const char *names[] = { ++ ++ "ep0", ++ "ep1in", ++ "ep2in", ++ "ep3in", ++ "ep4in", ++ "ep5in", ++ "ep6in", ++ "ep7in", ++ "ep8in", ++ "ep9in", ++ "ep10in", ++ "ep11in", ++ "ep12in", ++ "ep13in", ++ "ep14in", ++ "ep15in", ++ "ep1out", ++ "ep2out", ++ "ep3out", ++ "ep4out", ++ "ep5out", ++ "ep6out", ++ "ep7out", ++ "ep8out", ++ "ep9out", ++ "ep10out", ++ "ep11out", ++ "ep12out", ++ "ep13out", ++ "ep14out", ++ "ep15out" ++ }; ++ ++ int i; ++ struct usb_ep *ep; ++ ++ DWC_DEBUGPL(DBG_PCDV, "%s\n", __func__); ++ ++ INIT_LIST_HEAD(&d->gadget.ep_list); ++ d->gadget.ep0 = &d->ep0; ++ d->gadget.speed = USB_SPEED_UNKNOWN; ++ ++ INIT_LIST_HEAD(&d->gadget.ep0->ep_list); ++ ++ /** ++ * Initialize the EP0 structure. ++ */ ++ ep = &d->ep0; ++ ++ /* Init the usb_ep structure. */ ++ ep->name = names[0]; ++ ep->ops = (struct usb_ep_ops *)&dwc_otg_pcd_ep_ops; ++ ++ /** ++ * @todo NGS: What should the max packet size be set to ++ * here? Before EP type is set? ++ */ ++ ep->maxpacket = MAX_PACKET_SIZE; ++ dwc_otg_pcd_ep_enable(d->pcd, NULL, ep); ++ ++ list_add_tail(&ep->ep_list, &d->gadget.ep_list); ++ ++ /** ++ * Initialize the EP structures. ++ */ ++ ++ for (i = 0; i < 15; i++) { ++ ep = &d->in_ep[i]; ++ ++ /* Init the usb_ep structure. */ ++ ep->name = names[i + 1]; ++ ep->ops = (struct usb_ep_ops *)&dwc_otg_pcd_ep_ops; ++ ++ /** ++ * @todo NGS: What should the max packet size be set to ++ * here? Before EP type is set? ++ */ ++ ep->maxpacket = MAX_PACKET_SIZE; ++ list_add_tail(&ep->ep_list, &d->gadget.ep_list); ++ } ++ ++ for (i = 0; i < 15; i++) { ++ ep = &d->out_ep[i]; ++ ++ /* Init the usb_ep structure. */ ++ ep->name = names[15 + i + 1]; ++ ep->ops = (struct usb_ep_ops *)&dwc_otg_pcd_ep_ops; ++ ++ /** ++ * @todo NGS: What should the max packet size be set to ++ * here? Before EP type is set? ++ */ ++ ep->maxpacket = MAX_PACKET_SIZE; ++ ++ list_add_tail(&ep->ep_list, &d->gadget.ep_list); ++ } ++ ++ /* remove ep0 from the list. There is a ep0 pointer. */ ++ list_del_init(&d->ep0.ep_list); ++ ++ d->ep0.maxpacket = MAX_EP0_SIZE; ++} ++ ++/** ++ * This function releases the Gadget device. ++ * required by device_unregister(). ++ * ++ * @todo Should this do something? Should it free the PCD? ++ */ ++static void dwc_otg_pcd_gadget_release(struct device *dev) ++{ ++ DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, dev); ++} ++ ++static struct gadget_wrapper *alloc_wrapper( ++#ifdef LM_INTERFACE ++ struct lm_device *_dev ++#elif defined(PCI_INTERFACE) ++ struct pci_dev *_dev ++#elif defined(PLATFORM_INTERFACE) ++ struct platform_device *_dev ++#endif ++ ) ++{ ++#ifdef LM_INTERFACE ++ dwc_otg_device_t *otg_dev = lm_get_drvdata(_dev); ++#elif defined(PCI_INTERFACE) ++ dwc_otg_device_t *otg_dev = pci_get_drvdata(_dev); ++#elif defined(PLATFORM_INTERFACE) ++ dwc_otg_device_t *otg_dev = platform_get_drvdata(_dev); ++#endif ++ static char pcd_name[] = "dwc_otg_pcd"; ++ ++ struct gadget_wrapper *d; ++ int retval; ++ ++ d = dwc_alloc(sizeof(*d)); ++ if (d == NULL) { ++ return NULL; ++ } ++ ++ memset(d, 0, sizeof(*d)); ++ ++ d->gadget.name = pcd_name; ++ d->pcd = otg_dev->pcd; ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30)) ++ strcpy(d->gadget.dev.bus_id, "gadget"); ++#else ++ /*d->gadget.dev.bus = NULL;*/ ++ d->gadget.dev.init_name = "gadget"; ++#endif ++ d->gadget.dev.parent = &_dev->dev; ++ d->gadget.dev.release = dwc_otg_pcd_gadget_release; ++ d->gadget.ops = &dwc_otg_pcd_ops; ++ d->gadget.is_dualspeed = dwc_otg_pcd_is_dualspeed(otg_dev->pcd); ++ d->gadget.is_otg = dwc_otg_pcd_is_otg(otg_dev->pcd); ++ ++ d->driver = 0; ++ /* Register the gadget device */ ++ retval = device_register(&d->gadget.dev); ++ if (retval != 0) { ++ DWC_ERROR("device_register failed\n"); ++ dwc_free(d); ++ return NULL; ++ } ++ ++ return d; ++} ++ ++static void free_wrapper(struct gadget_wrapper *d) ++{ ++ if (d->driver) { ++ /* should have been done already by driver model core */ ++ DWC_WARN("driver '%s' is still registered\n", ++ d->driver->driver.name); ++ usb_gadget_unregister_driver(d->driver); ++ } ++ ++ device_unregister(&d->gadget.dev); ++ dwc_free(d); ++} ++ ++/** ++ * This function initialized the PCD portion of the driver. ++ * ++ */ ++int pcd_init( ++#ifdef LM_INTERFACE ++ struct lm_device *_dev ++#elif defined(PCI_INTERFACE) ++ struct pci_dev *_dev ++#elif defined(PLATFORM_INTERFACE) ++ struct platform_device *_dev ++#endif ++ ) ++ ++{ ++#ifdef LM_INTERFACE ++ dwc_otg_device_t *otg_dev = lm_get_drvdata(_dev); ++#elif defined(PCI_INTERFACE) ++ dwc_otg_device_t *otg_dev = pci_get_drvdata(_dev); ++#elif defined(PLATFORM_INTERFACE) ++ dwc_otg_device_t *otg_dev = platform_get_drvdata(_dev); ++#endif ++ int devirq; ++ ++ int retval = 0; ++ ++ DWC_DEBUGPL(DBG_PCDV, "%s(%p) otg_dev=%p\n", __func__, _dev, otg_dev); ++ ++ otg_dev->pcd = dwc_otg_pcd_init(otg_dev->core_if); ++ ++ if (!otg_dev->pcd) { ++ DWC_ERROR("dwc_otg_pcd_init failed\n"); ++ return -ENOMEM; ++ } ++ ++ gadget_wrapper = alloc_wrapper(_dev); ++ ++ /* ++ * Initialize EP structures ++ */ ++ gadget_add_eps(gadget_wrapper); ++ ++ /* ++ * Setup interupt handler ++ */ ++#ifdef PLATFORM_INTERFACE ++ devirq = platform_get_irq(_dev, 0); ++#else ++ devirq = _dev->irq; ++#endif ++ DWC_DEBUGPL(DBG_ANY, "registering handler for irq%d\n", devirq); ++ retval = request_irq(devirq, dwc_otg_pcd_irq, ++ IRQF_SHARED, gadget_wrapper->gadget.name, ++ otg_dev->pcd); ++ if (retval != 0) { ++ DWC_ERROR("request of irq%d failed\n", devirq); ++ free_wrapper(gadget_wrapper); ++ return -EBUSY; ++ } ++ ++ dwc_otg_pcd_start(gadget_wrapper->pcd, &fops); ++ ++ return retval; ++} ++ ++/** ++ * Cleanup the PCD. ++ */ ++void pcd_remove( ++#ifdef LM_INTERFACE ++ struct lm_device *_dev ++#elif defined(PCI_INTERFACE) ++ struct pci_dev *_dev ++#elif defined(PLATFORM_INTERFACE) ++ struct platform_device *_dev ++#endif ++ ) ++{ ++#ifdef LM_INTERFACE ++ dwc_otg_device_t *otg_dev = lm_get_drvdata(_dev); ++#elif defined(PCI_INTERFACE) ++ dwc_otg_device_t *otg_dev = pci_get_drvdata(_dev); ++#elif defined(PLATFORM_INTERFACE) ++ dwc_otg_device_t *otg_dev = platform_get_drvdata(_dev); ++#endif ++ dwc_otg_pcd_t *pcd = otg_dev->pcd; ++ ++ DWC_DEBUGPL(DBG_PCDV, "%s(%p) otg_dev %p\n", __func__, _dev, otg_dev); ++ ++ /* ++ * Free the IRQ ++ */ ++#ifdef PLATFORM_INTERFACE ++ free_irq(platform_get_irq(_dev, 0), pcd); ++#else ++ free_irq(_dev->irq, pcd); ++#endif ++ dwc_otg_pcd_remove(otg_dev->pcd); ++ free_wrapper(gadget_wrapper); ++ otg_dev->pcd = 0; ++} ++ ++/** ++ * This function registers a gadget driver with the PCD. ++ * ++ * When a driver is successfully registered, it will receive control ++ * requests including set_configuration(), which enables non-control ++ * requests. then usb traffic follows until a disconnect is reported. ++ * then a host may connect again, or the driver might get unbound. ++ * ++ * @param driver The driver being registered ++ */ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,37) ++int usb_gadget_register_driver(struct usb_gadget_driver *driver) ++#else ++int usb_gadget_probe_driver(struct usb_gadget_driver *driver, ++ int (*bind)(struct usb_gadget *)) ++#endif ++{ ++ int retval; ++ ++ DWC_DEBUGPL(DBG_PCD, "registering gadget driver '%s'\n", ++ driver->driver.name); ++ ++ if (!driver || driver->speed == USB_SPEED_UNKNOWN || ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,37) ++ !driver->bind || ++#else ++ !bind || ++#endif ++ !driver->unbind || !driver->disconnect || !driver->setup) { ++ DWC_DEBUGPL(DBG_PCDV, "EINVAL\n"); ++ return -EINVAL; ++ } ++ if (gadget_wrapper == 0) { ++ DWC_DEBUGPL(DBG_PCDV, "ENODEV\n"); ++ return -ENODEV; ++ } ++ if (gadget_wrapper->driver != 0) { ++ DWC_DEBUGPL(DBG_PCDV, "EBUSY (%p)\n", gadget_wrapper->driver); ++ return -EBUSY; ++ } ++ ++ /* hook up the driver */ ++ gadget_wrapper->driver = driver; ++ gadget_wrapper->gadget.dev.driver = &driver->driver; ++ ++ DWC_DEBUGPL(DBG_PCD, "bind to driver %s\n", driver->driver.name); ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,37) ++ retval = driver->bind(&gadget_wrapper->gadget); ++#else ++ retval = bind(&gadget_wrapper->gadget); ++#endif ++ if (retval) { ++ DWC_ERROR("bind to driver %s --> error %d\n", ++ driver->driver.name, retval); ++ gadget_wrapper->driver = 0; ++ gadget_wrapper->gadget.dev.driver = 0; ++ return retval; ++ } ++ DWC_DEBUGPL(DBG_ANY, "registered gadget driver '%s'\n", ++ driver->driver.name); ++ return 0; ++} ++ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,37) ++EXPORT_SYMBOL(usb_gadget_register_driver); ++#else ++EXPORT_SYMBOL(usb_gadget_probe_driver); ++#endif ++ ++/** ++ * This function unregisters a gadget driver ++ * ++ * @param driver The driver being unregistered ++ */ ++int usb_gadget_unregister_driver(struct usb_gadget_driver *driver) ++{ ++ //DWC_DEBUGPL(DBG_PCDV,"%s(%p)\n", __func__, _driver); ++ ++ if (gadget_wrapper == 0) { ++ DWC_DEBUGPL(DBG_ANY, "%s Return(%d): s_pcd==0\n", __func__, ++ -ENODEV); ++ return -ENODEV; ++ } ++ if (driver == 0 || driver != gadget_wrapper->driver) { ++ DWC_DEBUGPL(DBG_ANY, "%s Return(%d): driver?\n", __func__, ++ -EINVAL); ++ return -EINVAL; ++ } ++ ++ driver->unbind(&gadget_wrapper->gadget); ++ gadget_wrapper->driver = 0; ++ ++ DWC_DEBUGPL(DBG_ANY, "unregistered driver '%s'\n", driver->driver.name); ++ return 0; ++} ++ ++EXPORT_SYMBOL(usb_gadget_unregister_driver); ++ ++#endif /* DWC_HOST_ONLY */ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_regs.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_regs.h 2013-07-26 19:31:23.000000000 +0000 +@@ -0,0 +1,2237 @@ ++/* ========================================================================== ++ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_regs.h $ ++ * $Revision: #76 $ ++ * $Date: 2009/04/02 $ ++ * $Change: 1224216 $ ++ * ++ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, ++ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless ++ * otherwise expressly agreed to in writing between Synopsys and you. ++ * ++ * The Software IS NOT an item of Licensed Software or Licensed Product under ++ * any End User Software License Agreement or Agreement for Licensed Product ++ * with Synopsys or any supplement thereto. You are permitted to use and ++ * redistribute this Software in source and binary forms, with or without ++ * modification, provided that redistributions of source code must retain this ++ * notice. You may not view, use, disclose, copy or distribute this file or ++ * any information contained herein except pursuant to this license grant from ++ * Synopsys. If you do not agree with this notice, including the disclaimer ++ * below, then you are not authorized to use the Software. ++ * ++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, ++ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR ++ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER ++ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY ++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH ++ * DAMAGE. ++ * ========================================================================== */ ++ ++#ifndef __DWC_OTG_REGS_H__ ++#define __DWC_OTG_REGS_H__ ++ ++#include "dwc_otg_core_if.h" ++ ++/** ++ * @file ++ * ++ * This file contains the data structures for accessing the DWC_otg core registers. ++ * ++ * The application interfaces with the HS OTG core by reading from and ++ * writing to the Control and Status Register (CSR) space through the ++ * AHB Slave interface. These registers are 32 bits wide, and the ++ * addresses are 32-bit-block aligned. ++ * CSRs are classified as follows: ++ * - Core Global Registers ++ * - Device Mode Registers ++ * - Device Global Registers ++ * - Device Endpoint Specific Registers ++ * - Host Mode Registers ++ * - Host Global Registers ++ * - Host Port CSRs ++ * - Host Channel Specific Registers ++ * ++ * Only the Core Global registers can be accessed in both Device and ++ * Host modes. When the HS OTG core is operating in one mode, either ++ * Device or Host, the application must not access registers from the ++ * other mode. When the core switches from one mode to another, the ++ * registers in the new mode of operation must be reprogrammed as they ++ * would be after a power-on reset. ++ */ ++ ++/****************************************************************************/ ++/** DWC_otg Core registers . ++ * The dwc_otg_core_global_regs structure defines the size ++ * and relative field offsets for the Core Global registers. ++ */ ++typedef struct dwc_otg_core_global_regs { ++ /** OTG Control and Status Register. Offset: 000h */ ++ volatile uint32_t gotgctl; ++ /** OTG Interrupt Register. Offset: 004h */ ++ volatile uint32_t gotgint; ++ /**Core AHB Configuration Register. Offset: 008h */ ++ volatile uint32_t gahbcfg; ++ ++#define DWC_GLBINTRMASK 0x0001 ++#define DWC_DMAENABLE 0x0020 ++#define DWC_NPTXEMPTYLVL_EMPTY 0x0080 ++#define DWC_NPTXEMPTYLVL_HALFEMPTY 0x0000 ++#define DWC_PTXEMPTYLVL_EMPTY 0x0100 ++#define DWC_PTXEMPTYLVL_HALFEMPTY 0x0000 ++ ++ /**Core USB Configuration Register. Offset: 00Ch */ ++ volatile uint32_t gusbcfg; ++ /**Core Reset Register. Offset: 010h */ ++ volatile uint32_t grstctl; ++ /**Core Interrupt Register. Offset: 014h */ ++ volatile uint32_t gintsts; ++ /**Core Interrupt Mask Register. Offset: 018h */ ++ volatile uint32_t gintmsk; ++ /**Receive Status Queue Read Register (Read Only). Offset: 01Ch */ ++ volatile uint32_t grxstsr; ++ /**Receive Status Queue Read & POP Register (Read Only). Offset: 020h*/ ++ volatile uint32_t grxstsp; ++ /**Receive FIFO Size Register. Offset: 024h */ ++ volatile uint32_t grxfsiz; ++ /**Non Periodic Transmit FIFO Size Register. Offset: 028h */ ++ volatile uint32_t gnptxfsiz; ++ /**Non Periodic Transmit FIFO/Queue Status Register (Read ++ * Only). Offset: 02Ch */ ++ volatile uint32_t gnptxsts; ++ /**I2C Access Register. Offset: 030h */ ++ volatile uint32_t gi2cctl; ++ /**PHY Vendor Control Register. Offset: 034h */ ++ volatile uint32_t gpvndctl; ++ /**General Purpose Input/Output Register. Offset: 038h */ ++ volatile uint32_t ggpio; ++ /**User ID Register. Offset: 03Ch */ ++ volatile uint32_t guid; ++ /**Synopsys ID Register (Read Only). Offset: 040h */ ++ volatile uint32_t gsnpsid; ++ /**User HW Config1 Register (Read Only). Offset: 044h */ ++ volatile uint32_t ghwcfg1; ++ /**User HW Config2 Register (Read Only). Offset: 048h */ ++ volatile uint32_t ghwcfg2; ++#define DWC_SLAVE_ONLY_ARCH 0 ++#define DWC_EXT_DMA_ARCH 1 ++#define DWC_INT_DMA_ARCH 2 ++ ++#define DWC_MODE_HNP_SRP_CAPABLE 0 ++#define DWC_MODE_SRP_ONLY_CAPABLE 1 ++#define DWC_MODE_NO_HNP_SRP_CAPABLE 2 ++#define DWC_MODE_SRP_CAPABLE_DEVICE 3 ++#define DWC_MODE_NO_SRP_CAPABLE_DEVICE 4 ++#define DWC_MODE_SRP_CAPABLE_HOST 5 ++#define DWC_MODE_NO_SRP_CAPABLE_HOST 6 ++ ++ /**User HW Config3 Register (Read Only). Offset: 04Ch */ ++ volatile uint32_t ghwcfg3; ++ /**User HW Config4 Register (Read Only). Offset: 050h*/ ++ volatile uint32_t ghwcfg4; ++ /** Core LPM Configuration register */ ++ volatile uint32_t glpmcfg; ++ /** Reserved Offset: 058h-0FFh */ ++ volatile uint32_t reserved[42]; ++ /** Host Periodic Transmit FIFO Size Register. Offset: 100h */ ++ volatile uint32_t hptxfsiz; ++ /** Device Periodic Transmit FIFO#n Register if dedicated fifos are disabled, ++ otherwise Device Transmit FIFO#n Register. ++ * Offset: 104h + (FIFO_Number-1)*04h, 1 <= FIFO Number <= 15 (1<=n<=15). */ ++ volatile uint32_t dptxfsiz_dieptxf[15]; ++} dwc_otg_core_global_regs_t; ++ ++/** ++ * This union represents the bit fields of the Core OTG Control ++ * and Status Register (GOTGCTL). Set the bits using the bit ++ * fields then write the d32 value to the register. ++ */ ++typedef union gotgctl_data { ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct { ++ unsigned sesreqscs:1; ++ unsigned sesreq:1; ++ unsigned reserved2_7:6; ++ unsigned hstnegscs:1; ++ unsigned hnpreq:1; ++ unsigned hstsethnpen:1; ++ unsigned devhnpen:1; ++ unsigned reserved12_15:4; ++ unsigned conidsts:1; ++ unsigned reserved17:1; ++ unsigned asesvld:1; ++ unsigned bsesvld:1; ++ unsigned currmod:1; ++ unsigned reserved21_31:11; ++ } b; ++} gotgctl_data_t; ++ ++/** ++ * This union represents the bit fields of the Core OTG Interrupt Register ++ * (GOTGINT). Set/clear the bits using the bit fields then write the d32 ++ * value to the register. ++ */ ++typedef union gotgint_data { ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct { ++ /** Current Mode */ ++ unsigned reserved0_1:2; ++ ++ /** Session End Detected */ ++ unsigned sesenddet:1; ++ ++ unsigned reserved3_7:5; ++ ++ /** Session Request Success Status Change */ ++ unsigned sesreqsucstschng:1; ++ /** Host Negotiation Success Status Change */ ++ unsigned hstnegsucstschng:1; ++ ++ unsigned reserver10_16:7; ++ ++ /** Host Negotiation Detected */ ++ unsigned hstnegdet:1; ++ /** A-Device Timeout Change */ ++ unsigned adevtoutchng:1; ++ /** Debounce Done */ ++ unsigned debdone:1; ++ ++ unsigned reserved31_20:12; ++ ++ } b; ++} gotgint_data_t; ++ ++/** ++ * This union represents the bit fields of the Core AHB Configuration ++ * Register (GAHBCFG). Set/clear the bits using the bit fields then ++ * write the d32 value to the register. ++ */ ++typedef union gahbcfg_data { ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct { ++ unsigned glblintrmsk:1; ++#define DWC_GAHBCFG_GLBINT_ENABLE 1 ++ ++ unsigned hburstlen:4; ++#define DWC_GAHBCFG_INT_DMA_BURST_SINGLE 0 ++#define DWC_GAHBCFG_INT_DMA_BURST_INCR 1 ++#define DWC_GAHBCFG_INT_DMA_BURST_INCR4 3 ++#define DWC_GAHBCFG_INT_DMA_BURST_INCR8 5 ++#define DWC_GAHBCFG_INT_DMA_BURST_INCR16 7 ++ ++ unsigned dmaenable:1; ++#define DWC_GAHBCFG_DMAENABLE 1 ++ unsigned reserved:1; ++ unsigned nptxfemplvl_txfemplvl:1; ++ unsigned ptxfemplvl:1; ++#define DWC_GAHBCFG_TXFEMPTYLVL_EMPTY 1 ++#define DWC_GAHBCFG_TXFEMPTYLVL_HALFEMPTY 0 ++ unsigned reserved9_31:23; ++ } b; ++} gahbcfg_data_t; ++ ++/** ++ * This union represents the bit fields of the Core USB Configuration ++ * Register (GUSBCFG). Set the bits using the bit fields then write ++ * the d32 value to the register. ++ */ ++typedef union gusbcfg_data { ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct { ++ unsigned toutcal:3; ++ unsigned phyif:1; ++ unsigned ulpi_utmi_sel:1; ++ unsigned fsintf:1; ++ unsigned physel:1; ++ unsigned ddrsel:1; ++ unsigned srpcap:1; ++ unsigned hnpcap:1; ++ unsigned usbtrdtim:4; ++ unsigned nptxfrwnden:1; ++ unsigned phylpwrclksel:1; ++ unsigned otgutmifssel:1; ++ unsigned ulpi_fsls:1; ++ unsigned ulpi_auto_res:1; ++ unsigned ulpi_clk_sus_m:1; ++ unsigned ulpi_ext_vbus_drv:1; ++ unsigned ulpi_int_vbus_indicator:1; ++ unsigned term_sel_dl_pulse:1; ++ unsigned reserved23_25:3; ++ unsigned ic_usb_cap:1; ++ unsigned ic_traffic_pull_remove:1; ++ unsigned tx_end_delay:1; ++ unsigned reserved29_31:3; ++ } b; ++} gusbcfg_data_t; ++ ++/** ++ * This union represents the bit fields of the Core LPM Configuration ++ * Register (GLPMCFG). Set the bits using bit fields then write ++ * the d32 value to the register. ++ */ ++typedef union glpmctl_data { ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct { ++ /** LPM-Capable (LPMCap) (Device and Host) ++ * The application uses this bit to control ++ * the DWC_otg core LPM capabilities. ++ */ ++ unsigned lpm_cap_en:1; ++ /** LPM response programmed by application (AppL1Res) (Device) ++ * Handshake response to LPM token pre-programmed ++ * by device application software. ++ */ ++ unsigned appl_resp:1; ++ /** Host Initiated Resume Duration (HIRD) (Device and Host) ++ * In Host mode this field indicates the value of HIRD ++ * to be sent in an LPM transaction. ++ * In Device mode this field is updated with the ++ * Received LPM Token HIRD bmAttribute ++ * when an ACK/NYET/STALL response is sent ++ * to an LPM transaction. ++ */ ++ unsigned hird:4; ++ /** RemoteWakeEnable (bRemoteWake) (Device and Host) ++ * In Host mode this bit indicates the value of remote ++ * wake up to be sent in wIndex field of LPM transaction. ++ * In Device mode this field is updated with the ++ * Received LPM Token bRemoteWake bmAttribute ++ * when an ACK/NYET/STALL response is sent ++ * to an LPM transaction. ++ */ ++ unsigned rem_wkup_en:1; ++ /** Enable utmi_sleep_n (EnblSlpM) (Device and Host) ++ * The application uses this bit to control ++ * the utmi_sleep_n assertion to the PHY when in L1 state. ++ */ ++ unsigned en_utmi_sleep:1; ++ /** HIRD Threshold (HIRD_Thres) (Device and Host) ++ */ ++ unsigned hird_thres:5; ++ /** LPM Response (CoreL1Res) (Device and Host) ++ * In Host mode this bit contains handsake response to ++ * LPM transaction. ++ * In Device mode the response of the core to ++ * LPM transaction received is reflected in these two bits. ++ - 0x0 : ERROR (No handshake response) ++ - 0x1 : STALL ++ - 0x2 : NYET ++ - 0x3 : ACK ++ */ ++ unsigned lpm_resp:2; ++ /** Port Sleep Status (SlpSts) (Device and Host) ++ * This bit is set as long as a Sleep condition ++ * is present on the USB bus. ++ */ ++ unsigned prt_sleep_sts:1; ++ /** Sleep State Resume OK (L1ResumeOK) (Device and Host) ++ * Indicates that the application or host ++ * can start resume from Sleep state. ++ */ ++ unsigned sleep_state_resumeok:1; ++ /** LPM channel Index (LPM_Chnl_Indx) (Host) ++ * The channel number on which the LPM transaction ++ * has to be applied while sending ++ * an LPM transaction to the local device. ++ */ ++ unsigned lpm_chan_index:4; ++ /** LPM Retry Count (LPM_Retry_Cnt) (Host) ++ * Number host retries that would be performed ++ * if the device response was not valid response. ++ */ ++ unsigned retry_count:3; ++ /** Send LPM Transaction (SndLPM) (Host) ++ * When set by application software, ++ * an LPM transaction containing two tokens ++ * is sent. ++ */ ++ unsigned send_lpm:1; ++ /** LPM Retry status (LPM_RetryCnt_Sts) (Host) ++ * Number of LPM Host Retries still remaining ++ * to be transmitted for the current LPM sequence ++ */ ++ unsigned retry_count_sts:3; ++ unsigned reserved28_29:2; ++ /** In host mode once this bit is set, the host ++ * configures to drive the HSIC Idle state on the bus. ++ * It then waits for the device to initiate the Connect sequence. ++ * In device mode once this bit is set, the device waits for ++ * the HSIC Idle line state on the bus. Upon receving the Idle ++ * line state, it initiates the HSIC Connect sequence. ++ */ ++ unsigned hsic_connect:1; ++ /** This bit overrides and functionally inverts ++ * the if_select_hsic input port signal. ++ */ ++ unsigned inv_sel_hsic:1; ++ } b; ++} glpmcfg_data_t; ++ ++/** ++ * This union represents the bit fields of the Core Reset Register ++ * (GRSTCTL). Set/clear the bits using the bit fields then write the ++ * d32 value to the register. ++ */ ++typedef union grstctl_data { ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct { ++ /** Core Soft Reset (CSftRst) (Device and Host) ++ * ++ * The application can flush the control logic in the ++ * entire core using this bit. This bit resets the ++ * pipelines in the AHB Clock domain as well as the ++ * PHY Clock domain. ++ * ++ * The state machines are reset to an IDLE state, the ++ * control bits in the CSRs are cleared, all the ++ * transmit FIFOs and the receive FIFO are flushed. ++ * ++ * The status mask bits that control the generation of ++ * the interrupt, are cleared, to clear the ++ * interrupt. The interrupt status bits are not ++ * cleared, so the application can get the status of ++ * any events that occurred in the core after it has ++ * set this bit. ++ * ++ * Any transactions on the AHB are terminated as soon ++ * as possible following the protocol. Any ++ * transactions on the USB are terminated immediately. ++ * ++ * The configuration settings in the CSRs are ++ * unchanged, so the software doesn't have to ++ * reprogram these registers (Device ++ * Configuration/Host Configuration/Core System ++ * Configuration/Core PHY Configuration). ++ * ++ * The application can write to this bit, any time it ++ * wants to reset the core. This is a self clearing ++ * bit and the core clears this bit after all the ++ * necessary logic is reset in the core, which may ++ * take several clocks, depending on the current state ++ * of the core. ++ */ ++ unsigned csftrst:1; ++ /** Hclk Soft Reset ++ * ++ * The application uses this bit to reset the control logic in ++ * the AHB clock domain. Only AHB clock domain pipelines are ++ * reset. ++ */ ++ unsigned hsftrst:1; ++ /** Host Frame Counter Reset (Host Only)
++ * ++ * The application can reset the (micro)frame number ++ * counter inside the core, using this bit. When the ++ * (micro)frame counter is reset, the subsequent SOF ++ * sent out by the core, will have a (micro)frame ++ * number of 0. ++ */ ++ unsigned hstfrm:1; ++ /** In Token Sequence Learning Queue Flush ++ * (INTknQFlsh) (Device Only) ++ */ ++ unsigned intknqflsh:1; ++ /** RxFIFO Flush (RxFFlsh) (Device and Host) ++ * ++ * The application can flush the entire Receive FIFO ++ * using this bit.

The application must first ++ * ensure that the core is not in the middle of a ++ * transaction.

The application should write into ++ * this bit, only after making sure that neither the ++ * DMA engine is reading from the RxFIFO nor the MAC ++ * is writing the data in to the FIFO.

The ++ * application should wait until the bit is cleared ++ * before performing any other operations. This bit ++ * will takes 8 clocks (slowest of PHY or AHB clock) ++ * to clear. ++ */ ++ unsigned rxfflsh:1; ++ /** TxFIFO Flush (TxFFlsh) (Device and Host). ++ * ++ * This bit is used to selectively flush a single or ++ * all transmit FIFOs. The application must first ++ * ensure that the core is not in the middle of a ++ * transaction.

The application should write into ++ * this bit, only after making sure that neither the ++ * DMA engine is writing into the TxFIFO nor the MAC ++ * is reading the data out of the FIFO.

The ++ * application should wait until the core clears this ++ * bit, before performing any operations. This bit ++ * will takes 8 clocks (slowest of PHY or AHB clock) ++ * to clear. ++ */ ++ unsigned txfflsh:1; ++ ++ /** TxFIFO Number (TxFNum) (Device and Host). ++ * ++ * This is the FIFO number which needs to be flushed, ++ * using the TxFIFO Flush bit. This field should not ++ * be changed until the TxFIFO Flush bit is cleared by ++ * the core. ++ * - 0x0 : Non Periodic TxFIFO Flush ++ * - 0x1 : Periodic TxFIFO #1 Flush in device mode ++ * or Periodic TxFIFO in host mode ++ * - 0x2 : Periodic TxFIFO #2 Flush in device mode. ++ * - ... ++ * - 0xF : Periodic TxFIFO #15 Flush in device mode ++ * - 0x10: Flush all the Transmit NonPeriodic and ++ * Transmit Periodic FIFOs in the core ++ */ ++ unsigned txfnum:5; ++ /** Reserved */ ++ unsigned reserved11_29:19; ++ /** DMA Request Signal. Indicated DMA request is in ++ * probress. Used for debug purpose. */ ++ unsigned dmareq:1; ++ /** AHB Master Idle. Indicates the AHB Master State ++ * Machine is in IDLE condition. */ ++ unsigned ahbidle:1; ++ } b; ++} grstctl_t; ++ ++/** ++ * This union represents the bit fields of the Core Interrupt Mask ++ * Register (GINTMSK). Set/clear the bits using the bit fields then ++ * write the d32 value to the register. ++ */ ++typedef union gintmsk_data { ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct { ++ unsigned reserved0:1; ++ unsigned modemismatch:1; ++ unsigned otgintr:1; ++ unsigned sofintr:1; ++ unsigned rxstsqlvl:1; ++ unsigned nptxfempty:1; ++ unsigned ginnakeff:1; ++ unsigned goutnakeff:1; ++ unsigned reserved8:1; ++ unsigned i2cintr:1; ++ unsigned erlysuspend:1; ++ unsigned usbsuspend:1; ++ unsigned usbreset:1; ++ unsigned enumdone:1; ++ unsigned isooutdrop:1; ++ unsigned eopframe:1; ++ unsigned reserved16:1; ++ unsigned epmismatch:1; ++ unsigned inepintr:1; ++ unsigned outepintr:1; ++ unsigned incomplisoin:1; ++ unsigned incomplisoout:1; ++ unsigned reserved22_23:2; ++ unsigned portintr:1; ++ unsigned hcintr:1; ++ unsigned ptxfempty:1; ++ unsigned lpmtranrcvd:1; ++ unsigned conidstschng:1; ++ unsigned disconnect:1; ++ unsigned sessreqintr:1; ++ unsigned wkupintr:1; ++ } b; ++} gintmsk_data_t; ++/** ++ * This union represents the bit fields of the Core Interrupt Register ++ * (GINTSTS). Set/clear the bits using the bit fields then write the ++ * d32 value to the register. ++ */ ++typedef union gintsts_data { ++ /** raw register data */ ++ uint32_t d32; ++#define DWC_SOF_INTR_MASK 0x0008 ++ /** register bits */ ++ struct { ++#define DWC_HOST_MODE 1 ++ unsigned curmode:1; ++ unsigned modemismatch:1; ++ unsigned otgintr:1; ++ unsigned sofintr:1; ++ unsigned rxstsqlvl:1; ++ unsigned nptxfempty:1; ++ unsigned ginnakeff:1; ++ unsigned goutnakeff:1; ++ unsigned reserved8:1; ++ unsigned i2cintr:1; ++ unsigned erlysuspend:1; ++ unsigned usbsuspend:1; ++ unsigned usbreset:1; ++ unsigned enumdone:1; ++ unsigned isooutdrop:1; ++ unsigned eopframe:1; ++ unsigned intokenrx:1; ++ unsigned epmismatch:1; ++ unsigned inepint:1; ++ unsigned outepintr:1; ++ unsigned incomplisoin:1; ++ unsigned incomplisoout:1; ++ unsigned reserved22_23:2; ++ unsigned portintr:1; ++ unsigned hcintr:1; ++ unsigned ptxfempty:1; ++ unsigned lpmtranrcvd:1; ++ unsigned conidstschng:1; ++ unsigned disconnect:1; ++ unsigned sessreqintr:1; ++ unsigned wkupintr:1; ++ } b; ++} gintsts_data_t; ++ ++/** ++ * This union represents the bit fields in the Device Receive Status Read and ++ * Pop Registers (GRXSTSR, GRXSTSP) Read the register into the d32 ++ * element then read out the bits using the bit elements. ++ */ ++typedef union device_grxsts_data { ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct { ++ unsigned epnum:4; ++ unsigned bcnt:11; ++ unsigned dpid:2; ++ ++#define DWC_STS_DATA_UPDT 0x2 // OUT Data Packet ++#define DWC_STS_XFER_COMP 0x3 // OUT Data Transfer Complete ++ ++#define DWC_DSTS_GOUT_NAK 0x1 // Global OUT NAK ++#define DWC_DSTS_SETUP_COMP 0x4 // Setup Phase Complete ++#define DWC_DSTS_SETUP_UPDT 0x6 // SETUP Packet ++ unsigned pktsts:4; ++ unsigned fn:4; ++ unsigned reserved:7; ++ } b; ++} device_grxsts_data_t; ++ ++/** ++ * This union represents the bit fields in the Host Receive Status Read and ++ * Pop Registers (GRXSTSR, GRXSTSP) Read the register into the d32 ++ * element then read out the bits using the bit elements. ++ */ ++typedef union host_grxsts_data { ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct { ++ unsigned chnum:4; ++ unsigned bcnt:11; ++ unsigned dpid:2; ++ ++ unsigned pktsts:4; ++#define DWC_GRXSTS_PKTSTS_IN 0x2 ++#define DWC_GRXSTS_PKTSTS_IN_XFER_COMP 0x3 ++#define DWC_GRXSTS_PKTSTS_DATA_TOGGLE_ERR 0x5 ++#define DWC_GRXSTS_PKTSTS_CH_HALTED 0x7 ++ ++ unsigned reserved:11; ++ } b; ++} host_grxsts_data_t; ++ ++/** ++ * This union represents the bit fields in the FIFO Size Registers (HPTXFSIZ, ++ * GNPTXFSIZ, DPTXFSIZn, DIEPTXFn). Read the register into the d32 element then ++ * read out the bits using the bit elements. ++ */ ++typedef union fifosize_data { ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct { ++ unsigned startaddr:16; ++ unsigned depth:16; ++ } b; ++} fifosize_data_t; ++ ++/** ++ * This union represents the bit fields in the Non-Periodic Transmit ++ * FIFO/Queue Status Register (GNPTXSTS). Read the register into the ++ * d32 element then read out the bits using the bit ++ * elements. ++ */ ++typedef union gnptxsts_data { ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct { ++ unsigned nptxfspcavail:16; ++ unsigned nptxqspcavail:8; ++ /** Top of the Non-Periodic Transmit Request Queue ++ * - bit 24 - Terminate (Last entry for the selected ++ * channel/EP) ++ * - bits 26:25 - Token Type ++ * - 2'b00 - IN/OUT ++ * - 2'b01 - Zero Length OUT ++ * - 2'b10 - PING/Complete Split ++ * - 2'b11 - Channel Halt ++ * - bits 30:27 - Channel/EP Number ++ */ ++ unsigned nptxqtop_terminate:1; ++ unsigned nptxqtop_token:2; ++ unsigned nptxqtop_chnep:4; ++ unsigned reserved:1; ++ } b; ++} gnptxsts_data_t; ++ ++/** ++ * This union represents the bit fields in the Transmit ++ * FIFO Status Register (DTXFSTS). Read the register into the ++ * d32 element then read out the bits using the bit ++ * elements. ++ */ ++typedef union dtxfsts_data { ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct { ++ unsigned txfspcavail:16; ++ unsigned reserved:16; ++ } b; ++} dtxfsts_data_t; ++ ++/** ++ * This union represents the bit fields in the I2C Control Register ++ * (I2CCTL). Read the register into the d32 element then read out the ++ * bits using the bit elements. ++ */ ++typedef union gi2cctl_data { ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct { ++ unsigned rwdata:8; ++ unsigned regaddr:8; ++ unsigned addr:7; ++ unsigned i2cen:1; ++ unsigned ack:1; ++ unsigned i2csuspctl:1; ++ unsigned i2cdevaddr:2; ++ unsigned reserved:2; ++ unsigned rw:1; ++ unsigned bsydne:1; ++ } b; ++} gi2cctl_data_t; ++ ++/** ++ * This union represents the bit fields in the User HW Config1 ++ * Register. Read the register into the d32 element then read ++ * out the bits using the bit elements. ++ */ ++typedef union hwcfg1_data { ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct { ++ unsigned ep_dir0:2; ++ unsigned ep_dir1:2; ++ unsigned ep_dir2:2; ++ unsigned ep_dir3:2; ++ unsigned ep_dir4:2; ++ unsigned ep_dir5:2; ++ unsigned ep_dir6:2; ++ unsigned ep_dir7:2; ++ unsigned ep_dir8:2; ++ unsigned ep_dir9:2; ++ unsigned ep_dir10:2; ++ unsigned ep_dir11:2; ++ unsigned ep_dir12:2; ++ unsigned ep_dir13:2; ++ unsigned ep_dir14:2; ++ unsigned ep_dir15:2; ++ } b; ++} hwcfg1_data_t; ++ ++/** ++ * This union represents the bit fields in the User HW Config2 ++ * Register. Read the register into the d32 element then read ++ * out the bits using the bit elements. ++ */ ++typedef union hwcfg2_data { ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct { ++ /* GHWCFG2 */ ++ unsigned op_mode:3; ++#define DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG 0 ++#define DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG 1 ++#define DWC_HWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE_OTG 2 ++#define DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE 3 ++#define DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE 4 ++#define DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST 5 ++#define DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST 6 ++ ++ unsigned architecture:2; ++ unsigned point2point:1; ++ unsigned hs_phy_type:2; ++#define DWC_HWCFG2_HS_PHY_TYPE_NOT_SUPPORTED 0 ++#define DWC_HWCFG2_HS_PHY_TYPE_UTMI 1 ++#define DWC_HWCFG2_HS_PHY_TYPE_ULPI 2 ++#define DWC_HWCFG2_HS_PHY_TYPE_UTMI_ULPI 3 ++ ++ unsigned fs_phy_type:2; ++ unsigned num_dev_ep:4; ++ unsigned num_host_chan:4; ++ unsigned perio_ep_supported:1; ++ unsigned dynamic_fifo:1; ++ unsigned multi_proc_int:1; ++ unsigned reserved21:1; ++ unsigned nonperio_tx_q_depth:2; ++ unsigned host_perio_tx_q_depth:2; ++ unsigned dev_token_q_depth:5; ++ unsigned reserved31:1; ++ } b; ++} hwcfg2_data_t; ++ ++/** ++ * This union represents the bit fields in the User HW Config3 ++ * Register. Read the register into the d32 element then read ++ * out the bits using the bit elements. ++ */ ++typedef union hwcfg3_data { ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct { ++ /* GHWCFG3 */ ++ unsigned xfer_size_cntr_width:4; ++ unsigned packet_size_cntr_width:3; ++ unsigned otg_func:1; ++ unsigned i2c:1; ++ unsigned vendor_ctrl_if:1; ++ unsigned optional_features:1; ++ unsigned synch_reset_type:1; ++ unsigned otg_enable_ic_usb:1; ++ unsigned otg_enable_hsic:1; ++ unsigned reserved14:1; ++ unsigned otg_lpm_en:1; ++ unsigned dfifo_depth:16; ++ } b; ++} hwcfg3_data_t; ++ ++/** ++ * This union represents the bit fields in the User HW Config4 ++ * Register. Read the register into the d32 element then read ++ * out the bits using the bit elements. ++ */ ++typedef union hwcfg4_data { ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct { ++ unsigned num_dev_perio_in_ep:4; ++ unsigned power_optimiz:1; ++ unsigned min_ahb_freq:9; ++ unsigned utmi_phy_data_width:2; ++ unsigned num_dev_mode_ctrl_ep:4; ++ unsigned iddig_filt_en:1; ++ unsigned vbus_valid_filt_en:1; ++ unsigned a_valid_filt_en:1; ++ unsigned b_valid_filt_en:1; ++ unsigned session_end_filt_en:1; ++ unsigned ded_fifo_en:1; ++ unsigned num_in_eps:4; ++ unsigned desc_dma:1; ++ unsigned desc_dma_dyn:1; ++ } b; ++} hwcfg4_data_t; ++ ++//////////////////////////////////////////// ++// Device Registers ++/** ++ * Device Global Registers. Offsets 800h-BFFh ++ * ++ * The following structures define the size and relative field offsets ++ * for the Device Mode Registers. ++ * ++ * These registers are visible only in Device mode and must not be ++ * accessed in Host mode, as the results are unknown. ++ */ ++typedef struct dwc_otg_dev_global_regs { ++ /** Device Configuration Register. Offset 800h */ ++ volatile uint32_t dcfg; ++ /** Device Control Register. Offset: 804h */ ++ volatile uint32_t dctl; ++ /** Device Status Register (Read Only). Offset: 808h */ ++ volatile uint32_t dsts; ++ /** Reserved. Offset: 80Ch */ ++ uint32_t unused; ++ /** Device IN Endpoint Common Interrupt Mask ++ * Register. Offset: 810h */ ++ volatile uint32_t diepmsk; ++ /** Device OUT Endpoint Common Interrupt Mask ++ * Register. Offset: 814h */ ++ volatile uint32_t doepmsk; ++ /** Device All Endpoints Interrupt Register. Offset: 818h */ ++ volatile uint32_t daint; ++ /** Device All Endpoints Interrupt Mask Register. Offset: ++ * 81Ch */ ++ volatile uint32_t daintmsk; ++ /** Device IN Token Queue Read Register-1 (Read Only). ++ * Offset: 820h */ ++ volatile uint32_t dtknqr1; ++ /** Device IN Token Queue Read Register-2 (Read Only). ++ * Offset: 824h */ ++ volatile uint32_t dtknqr2; ++ /** Device VBUS discharge Register. Offset: 828h */ ++ volatile uint32_t dvbusdis; ++ /** Device VBUS Pulse Register. Offset: 82Ch */ ++ volatile uint32_t dvbuspulse; ++ /** Device IN Token Queue Read Register-3 (Read Only). / ++ * Device Thresholding control register (Read/Write) ++ * Offset: 830h */ ++ volatile uint32_t dtknqr3_dthrctl; ++ /** Device IN Token Queue Read Register-4 (Read Only). / ++ * Device IN EPs empty Inr. Mask Register (Read/Write) ++ * Offset: 834h */ ++ volatile uint32_t dtknqr4_fifoemptymsk; ++ /** Device Each Endpoint Interrupt Register (Read Only). / ++ * Offset: 838h */ ++ volatile uint32_t deachint; ++ /** Device Each Endpoint Interrupt mask Register (Read/Write). / ++ * Offset: 83Ch */ ++ volatile uint32_t deachintmsk; ++ /** Device Each In Endpoint Interrupt mask Register (Read/Write). / ++ * Offset: 840h */ ++ volatile uint32_t diepeachintmsk[MAX_EPS_CHANNELS]; ++ /** Device Each Out Endpoint Interrupt mask Register (Read/Write). / ++ * Offset: 880h */ ++ volatile uint32_t doepeachintmsk[MAX_EPS_CHANNELS]; ++} dwc_otg_device_global_regs_t; ++ ++/** ++ * This union represents the bit fields in the Device Configuration ++ * Register. Read the register into the d32 member then ++ * set/clear the bits using the bit elements. Write the ++ * d32 member to the dcfg register. ++ */ ++typedef union dcfg_data { ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct { ++ /** Device Speed */ ++ unsigned devspd:2; ++ /** Non Zero Length Status OUT Handshake */ ++ unsigned nzstsouthshk:1; ++#define DWC_DCFG_SEND_STALL 1 ++ ++ unsigned reserved3:1; ++ /** Device Addresses */ ++ unsigned devaddr:7; ++ /** Periodic Frame Interval */ ++ unsigned perfrint:2; ++#define DWC_DCFG_FRAME_INTERVAL_80 0 ++#define DWC_DCFG_FRAME_INTERVAL_85 1 ++#define DWC_DCFG_FRAME_INTERVAL_90 2 ++#define DWC_DCFG_FRAME_INTERVAL_95 3 ++ ++ unsigned reserved13_17:5; ++ /** In Endpoint Mis-match count */ ++ unsigned epmscnt:5; ++ /** Enable Descriptor DMA in Device mode */ ++ unsigned descdma:1; ++ } b; ++} dcfg_data_t; ++ ++/** ++ * This union represents the bit fields in the Device Control ++ * Register. Read the register into the d32 member then ++ * set/clear the bits using the bit elements. ++ */ ++typedef union dctl_data { ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct { ++ /** Remote Wakeup */ ++ unsigned rmtwkupsig:1; ++ /** Soft Disconnect */ ++ unsigned sftdiscon:1; ++ /** Global Non-Periodic IN NAK Status */ ++ unsigned gnpinnaksts:1; ++ /** Global OUT NAK Status */ ++ unsigned goutnaksts:1; ++ /** Test Control */ ++ unsigned tstctl:3; ++ /** Set Global Non-Periodic IN NAK */ ++ unsigned sgnpinnak:1; ++ /** Clear Global Non-Periodic IN NAK */ ++ unsigned cgnpinnak:1; ++ /** Set Global OUT NAK */ ++ unsigned sgoutnak:1; ++ /** Clear Global OUT NAK */ ++ unsigned cgoutnak:1; ++ ++ /** Power-On Programming Done */ ++ unsigned pwronprgdone:1; ++ /** Global Continue on BNA */ ++ unsigned gcontbna:1; ++ /** Global Multi Count */ ++ unsigned gmc:2; ++ /** Ignore Frame Number for ISOC EPs */ ++ unsigned ifrmnum:1; ++ /** NAK on Babble */ ++ unsigned nakonbble:1; ++ ++ unsigned reserved17_31:15; ++ } b; ++} dctl_data_t; ++ ++/** ++ * This union represents the bit fields in the Device Status ++ * Register. Read the register into the d32 member then ++ * set/clear the bits using the bit elements. ++ */ ++typedef union dsts_data { ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct { ++ /** Suspend Status */ ++ unsigned suspsts:1; ++ /** Enumerated Speed */ ++ unsigned enumspd:2; ++#define DWC_DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ 0 ++#define DWC_DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ 1 ++#define DWC_DSTS_ENUMSPD_LS_PHY_6MHZ 2 ++#define DWC_DSTS_ENUMSPD_FS_PHY_48MHZ 3 ++ /** Erratic Error */ ++ unsigned errticerr:1; ++ unsigned reserved4_7:4; ++ /** Frame or Microframe Number of the received SOF */ ++ unsigned soffn:14; ++ unsigned reserved22_31:10; ++ } b; ++} dsts_data_t; ++ ++/** ++ * This union represents the bit fields in the Device IN EP Interrupt ++ * Register and the Device IN EP Common Mask Register. ++ * ++ * - Read the register into the d32 member then set/clear the ++ * bits using the bit elements. ++ */ ++typedef union diepint_data { ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct { ++ /** Transfer complete mask */ ++ unsigned xfercompl:1; ++ /** Endpoint disable mask */ ++ unsigned epdisabled:1; ++ /** AHB Error mask */ ++ unsigned ahberr:1; ++ /** TimeOUT Handshake mask (non-ISOC EPs) */ ++ unsigned timeout:1; ++ /** IN Token received with TxF Empty mask */ ++ unsigned intktxfemp:1; ++ /** IN Token Received with EP mismatch mask */ ++ unsigned intknepmis:1; ++ /** IN Endpoint HAK Effective mask */ ++ unsigned inepnakeff:1; ++ /** IN Endpoint HAK Effective mask */ ++ unsigned emptyintr:1; ++ ++ unsigned txfifoundrn:1; ++ ++ /** BNA Interrupt mask */ ++ unsigned bna:1; ++ ++ unsigned reserved10_12:3; ++ /** BNA Interrupt mask */ ++ unsigned nak:1; ++ ++ unsigned reserved14_31:18; ++ } b; ++} diepint_data_t; ++ ++/** ++ * This union represents the bit fields in the Device IN EP ++ * Common/Dedicated Interrupt Mask Register. ++ */ ++typedef union diepint_data diepmsk_data_t; ++ ++/** ++ * This union represents the bit fields in the Device OUT EP Interrupt ++ * Registerand Device OUT EP Common Interrupt Mask Register. ++ * ++ * - Read the register into the d32 member then set/clear the ++ * bits using the bit elements. ++ */ ++typedef union doepint_data { ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct { ++ /** Transfer complete */ ++ unsigned xfercompl:1; ++ /** Endpoint disable */ ++ unsigned epdisabled:1; ++ /** AHB Error */ ++ unsigned ahberr:1; ++ /** Setup Phase Done (contorl EPs) */ ++ unsigned setup:1; ++ /** OUT Token Received when Endpoint Disabled */ ++ unsigned outtknepdis:1; ++ ++ unsigned stsphsercvd:1; ++ /** Back-to-Back SETUP Packets Received */ ++ unsigned back2backsetup:1; ++ ++ unsigned reserved7:1; ++ /** OUT packet Error */ ++ unsigned outpkterr:1; ++ /** BNA Interrupt */ ++ unsigned bna:1; ++ ++ unsigned reserved10:1; ++ /** Packet Drop Status */ ++ unsigned pktdrpsts:1; ++ /** Babble Interrupt */ ++ unsigned babble:1; ++ /** NAK Interrupt */ ++ unsigned nak:1; ++ /** NYET Interrupt */ ++ unsigned nyet:1; ++ ++ unsigned reserved15_31:17; ++ } b; ++} doepint_data_t; ++ ++/** ++ * This union represents the bit fields in the Device OUT EP ++ * Common/Dedicated Interrupt Mask Register. ++ */ ++typedef union doepint_data doepmsk_data_t; ++ ++/** ++ * This union represents the bit fields in the Device All EP Interrupt ++ * and Mask Registers. ++ * - Read the register into the d32 member then set/clear the ++ * bits using the bit elements. ++ */ ++typedef union daint_data { ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct { ++ /** IN Endpoint bits */ ++ unsigned in:16; ++ /** OUT Endpoint bits */ ++ unsigned out:16; ++ } ep; ++ struct { ++ /** IN Endpoint bits */ ++ unsigned inep0:1; ++ unsigned inep1:1; ++ unsigned inep2:1; ++ unsigned inep3:1; ++ unsigned inep4:1; ++ unsigned inep5:1; ++ unsigned inep6:1; ++ unsigned inep7:1; ++ unsigned inep8:1; ++ unsigned inep9:1; ++ unsigned inep10:1; ++ unsigned inep11:1; ++ unsigned inep12:1; ++ unsigned inep13:1; ++ unsigned inep14:1; ++ unsigned inep15:1; ++ /** OUT Endpoint bits */ ++ unsigned outep0:1; ++ unsigned outep1:1; ++ unsigned outep2:1; ++ unsigned outep3:1; ++ unsigned outep4:1; ++ unsigned outep5:1; ++ unsigned outep6:1; ++ unsigned outep7:1; ++ unsigned outep8:1; ++ unsigned outep9:1; ++ unsigned outep10:1; ++ unsigned outep11:1; ++ unsigned outep12:1; ++ unsigned outep13:1; ++ unsigned outep14:1; ++ unsigned outep15:1; ++ } b; ++} daint_data_t; ++ ++/** ++ * This union represents the bit fields in the Device IN Token Queue ++ * Read Registers. ++ * - Read the register into the d32 member. ++ * - READ-ONLY Register ++ */ ++typedef union dtknq1_data { ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct { ++ /** In Token Queue Write Pointer */ ++ unsigned intknwptr:5; ++ /** Reserved */ ++ unsigned reserved05_06:2; ++ /** write pointer has wrapped. */ ++ unsigned wrap_bit:1; ++ /** EP Numbers of IN Tokens 0 ... 4 */ ++ unsigned epnums0_5:24; ++ } b; ++} dtknq1_data_t; ++ ++/** ++ * This union represents Threshold control Register ++ * - Read and write the register into the d32 member. ++ * - READ-WRITABLE Register ++ */ ++typedef union dthrctl_data { ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct { ++ /** non ISO Tx Thr. Enable */ ++ unsigned non_iso_thr_en:1; ++ /** ISO Tx Thr. Enable */ ++ unsigned iso_thr_en:1; ++ /** Tx Thr. Length */ ++ unsigned tx_thr_len:9; ++ /** AHB Threshold ratio */ ++ unsigned ahb_thr_ratio:2; ++ /** Reserved */ ++ unsigned reserved13_15:3; ++ /** Rx Thr. Enable */ ++ unsigned rx_thr_en:1; ++ /** Rx Thr. Length */ ++ unsigned rx_thr_len:9; ++ /** Reserved */ ++ unsigned reserved26_31:6; ++ } b; ++} dthrctl_data_t; ++ ++/** ++ * Device Logical IN Endpoint-Specific Registers. Offsets ++ * 900h-AFCh ++ * ++ * There will be one set of endpoint registers per logical endpoint ++ * implemented. ++ * ++ * These registers are visible only in Device mode and must not be ++ * accessed in Host mode, as the results are unknown. ++ */ ++typedef struct dwc_otg_dev_in_ep_regs { ++ /** Device IN Endpoint Control Register. Offset:900h + ++ * (ep_num * 20h) + 00h */ ++ volatile uint32_t diepctl; ++ /** Reserved. Offset:900h + (ep_num * 20h) + 04h */ ++ uint32_t reserved04; ++ /** Device IN Endpoint Interrupt Register. Offset:900h + ++ * (ep_num * 20h) + 08h */ ++ volatile uint32_t diepint; ++ /** Reserved. Offset:900h + (ep_num * 20h) + 0Ch */ ++ uint32_t reserved0C; ++ /** Device IN Endpoint Transfer Size ++ * Register. Offset:900h + (ep_num * 20h) + 10h */ ++ volatile uint32_t dieptsiz; ++ /** Device IN Endpoint DMA Address Register. Offset:900h + ++ * (ep_num * 20h) + 14h */ ++ volatile uint32_t diepdma; ++ /** Device IN Endpoint Transmit FIFO Status Register. Offset:900h + ++ * (ep_num * 20h) + 18h */ ++ volatile uint32_t dtxfsts; ++ /** Device IN Endpoint DMA Buffer Register. Offset:900h + ++ * (ep_num * 20h) + 1Ch */ ++ volatile uint32_t diepdmab; ++} dwc_otg_dev_in_ep_regs_t; ++ ++/** ++ * Device Logical OUT Endpoint-Specific Registers. Offsets: ++ * B00h-CFCh ++ * ++ * There will be one set of endpoint registers per logical endpoint ++ * implemented. ++ * ++ * These registers are visible only in Device mode and must not be ++ * accessed in Host mode, as the results are unknown. ++ */ ++typedef struct dwc_otg_dev_out_ep_regs { ++ /** Device OUT Endpoint Control Register. Offset:B00h + ++ * (ep_num * 20h) + 00h */ ++ volatile uint32_t doepctl; ++ /** Device OUT Endpoint Frame number Register. Offset: ++ * B00h + (ep_num * 20h) + 04h */ ++ volatile uint32_t doepfn; ++ /** Device OUT Endpoint Interrupt Register. Offset:B00h + ++ * (ep_num * 20h) + 08h */ ++ volatile uint32_t doepint; ++ /** Reserved. Offset:B00h + (ep_num * 20h) + 0Ch */ ++ uint32_t reserved0C; ++ /** Device OUT Endpoint Transfer Size Register. Offset: ++ * B00h + (ep_num * 20h) + 10h */ ++ volatile uint32_t doeptsiz; ++ /** Device OUT Endpoint DMA Address Register. Offset:B00h ++ * + (ep_num * 20h) + 14h */ ++ volatile uint32_t doepdma; ++ /** Reserved. Offset:B00h + * (ep_num * 20h) + 18h */ ++ uint32_t unused; ++ /** Device OUT Endpoint DMA Buffer Register. Offset:B00h ++ * + (ep_num * 20h) + 1Ch */ ++ uint32_t doepdmab; ++} dwc_otg_dev_out_ep_regs_t; ++ ++/** ++ * This union represents the bit fields in the Device EP Control ++ * Register. Read the register into the d32 member then ++ * set/clear the bits using the bit elements. ++ */ ++typedef union depctl_data { ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct { ++ /** Maximum Packet Size ++ * IN/OUT EPn ++ * IN/OUT EP0 - 2 bits ++ * 2'b00: 64 Bytes ++ * 2'b01: 32 ++ * 2'b10: 16 ++ * 2'b11: 8 */ ++ unsigned mps:11; ++#define DWC_DEP0CTL_MPS_64 0 ++#define DWC_DEP0CTL_MPS_32 1 ++#define DWC_DEP0CTL_MPS_16 2 ++#define DWC_DEP0CTL_MPS_8 3 ++ ++ /** Next Endpoint ++ * IN EPn/IN EP0 ++ * OUT EPn/OUT EP0 - reserved */ ++ unsigned nextep:4; ++ ++ /** USB Active Endpoint */ ++ unsigned usbactep:1; ++ ++ /** Endpoint DPID (INTR/Bulk IN and OUT endpoints) ++ * This field contains the PID of the packet going to ++ * be received or transmitted on this endpoint. The ++ * application should program the PID of the first ++ * packet going to be received or transmitted on this ++ * endpoint , after the endpoint is ++ * activated. Application use the SetD1PID and ++ * SetD0PID fields of this register to program either ++ * D0 or D1 PID. ++ * ++ * The encoding for this field is ++ * - 0: D0 ++ * - 1: D1 ++ */ ++ unsigned dpid:1; ++ ++ /** NAK Status */ ++ unsigned naksts:1; ++ ++ /** Endpoint Type ++ * 2'b00: Control ++ * 2'b01: Isochronous ++ * 2'b10: Bulk ++ * 2'b11: Interrupt */ ++ unsigned eptype:2; ++ ++ /** Snoop Mode ++ * OUT EPn/OUT EP0 ++ * IN EPn/IN EP0 - reserved */ ++ unsigned snp:1; ++ ++ /** Stall Handshake */ ++ unsigned stall:1; ++ ++ /** Tx Fifo Number ++ * IN EPn/IN EP0 ++ * OUT EPn/OUT EP0 - reserved */ ++ unsigned txfnum:4; ++ ++ /** Clear NAK */ ++ unsigned cnak:1; ++ /** Set NAK */ ++ unsigned snak:1; ++ /** Set DATA0 PID (INTR/Bulk IN and OUT endpoints) ++ * Writing to this field sets the Endpoint DPID (DPID) ++ * field in this register to DATA0. Set Even ++ * (micro)frame (SetEvenFr) (ISO IN and OUT Endpoints) ++ * Writing to this field sets the Even/Odd ++ * (micro)frame (EO_FrNum) field to even (micro) ++ * frame. ++ */ ++ unsigned setd0pid:1; ++ /** Set DATA1 PID (INTR/Bulk IN and OUT endpoints) ++ * Writing to this field sets the Endpoint DPID (DPID) ++ * field in this register to DATA1 Set Odd ++ * (micro)frame (SetOddFr) (ISO IN and OUT Endpoints) ++ * Writing to this field sets the Even/Odd ++ * (micro)frame (EO_FrNum) field to odd (micro) frame. ++ */ ++ unsigned setd1pid:1; ++ ++ /** Endpoint Disable */ ++ unsigned epdis:1; ++ /** Endpoint Enable */ ++ unsigned epena:1; ++ } b; ++} depctl_data_t; ++ ++/** ++ * This union represents the bit fields in the Device EP Transfer ++ * Size Register. Read the register into the d32 member then ++ * set/clear the bits using the bit elements. ++ */ ++typedef union deptsiz_data { ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct { ++ /** Transfer size */ ++ unsigned xfersize:19; ++ /** Packet Count */ ++ unsigned pktcnt:10; ++ /** Multi Count - Periodic IN endpoints */ ++ unsigned mc:2; ++ unsigned reserved:1; ++ } b; ++} deptsiz_data_t; ++ ++/** ++ * This union represents the bit fields in the Device EP 0 Transfer ++ * Size Register. Read the register into the d32 member then ++ * set/clear the bits using the bit elements. ++ */ ++typedef union deptsiz0_data { ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct { ++ /** Transfer size */ ++ unsigned xfersize:7; ++ /** Reserved */ ++ unsigned reserved7_18:12; ++ /** Packet Count */ ++ unsigned pktcnt:1; ++ /** Reserved */ ++ unsigned reserved20_28:9; ++ /**Setup Packet Count (DOEPTSIZ0 Only) */ ++ unsigned supcnt:2; ++ unsigned reserved31; ++ } b; ++} deptsiz0_data_t; ++ ++///////////////////////////////////////////////// ++// DMA Descriptor Specific Structures ++// ++ ++/** Buffer status definitions */ ++ ++#define BS_HOST_READY 0x0 ++#define BS_DMA_BUSY 0x1 ++#define BS_DMA_DONE 0x2 ++#define BS_HOST_BUSY 0x3 ++ ++/** Receive/Transmit status definitions */ ++ ++#define RTS_SUCCESS 0x0 ++#define RTS_BUFFLUSH 0x1 ++#define RTS_RESERVED 0x2 ++#define RTS_BUFERR 0x3 ++ ++/** ++ * This union represents the bit fields in the DMA Descriptor ++ * status quadlet. Read the quadlet into the d32 member then ++ * set/clear the bits using the bit, b_iso_out and ++ * b_iso_in elements. ++ */ ++typedef union dev_dma_desc_sts { ++ /** raw register data */ ++ uint32_t d32; ++ /** quadlet bits */ ++ struct { ++ /** Received number of bytes */ ++ unsigned bytes:16; ++ ++ unsigned reserved16_22:7; ++ /** Multiple Transfer - only for OUT EPs */ ++ unsigned mtrf:1; ++ /** Setup Packet received - only for OUT EPs */ ++ unsigned sr:1; ++ /** Interrupt On Complete */ ++ unsigned ioc:1; ++ /** Short Packet */ ++ unsigned sp:1; ++ /** Last */ ++ unsigned l:1; ++ /** Receive Status */ ++ unsigned sts:2; ++ /** Buffer Status */ ++ unsigned bs:2; ++ } b; ++ ++#ifdef DWC_EN_ISOC ++ /** iso out quadlet bits */ ++ struct { ++ /** Received number of bytes */ ++ unsigned rxbytes:11; ++ ++ unsigned reserved11:1; ++ /** Frame Number */ ++ unsigned framenum:11; ++ /** Received ISO Data PID */ ++ unsigned pid:2; ++ /** Interrupt On Complete */ ++ unsigned ioc:1; ++ /** Short Packet */ ++ unsigned sp:1; ++ /** Last */ ++ unsigned l:1; ++ /** Receive Status */ ++ unsigned rxsts:2; ++ /** Buffer Status */ ++ unsigned bs:2; ++ } b_iso_out; ++ ++ /** iso in quadlet bits */ ++ struct { ++ /** Transmited number of bytes */ ++ unsigned txbytes:12; ++ /** Frame Number */ ++ unsigned framenum:11; ++ /** Transmited ISO Data PID */ ++ unsigned pid:2; ++ /** Interrupt On Complete */ ++ unsigned ioc:1; ++ /** Short Packet */ ++ unsigned sp:1; ++ /** Last */ ++ unsigned l:1; ++ /** Transmit Status */ ++ unsigned txsts:2; ++ /** Buffer Status */ ++ unsigned bs:2; ++ } b_iso_in; ++#endif /* DWC_EN_ISOC */ ++} dev_dma_desc_sts_t; ++ ++/** ++ * DMA Descriptor structure ++ * ++ * DMA Descriptor structure contains two quadlets: ++ * Status quadlet and Data buffer pointer. ++ */ ++typedef struct dwc_otg_dev_dma_desc { ++ /** DMA Descriptor status quadlet */ ++ dev_dma_desc_sts_t status; ++ /** DMA Descriptor data buffer pointer */ ++ uint32_t buf; ++} dwc_otg_dev_dma_desc_t; ++ ++/** ++ * The dwc_otg_dev_if structure contains information needed to manage ++ * the DWC_otg controller acting in device mode. It represents the ++ * programming view of the device-specific aspects of the controller. ++ */ ++typedef struct dwc_otg_dev_if { ++ /** Pointer to device Global registers. ++ * Device Global Registers starting at offset 800h ++ */ ++ dwc_otg_device_global_regs_t *dev_global_regs; ++#define DWC_DEV_GLOBAL_REG_OFFSET 0x800 ++ ++ /** ++ * Device Logical IN Endpoint-Specific Registers 900h-AFCh ++ */ ++ dwc_otg_dev_in_ep_regs_t *in_ep_regs[MAX_EPS_CHANNELS]; ++#define DWC_DEV_IN_EP_REG_OFFSET 0x900 ++#define DWC_EP_REG_OFFSET 0x20 ++ ++ /** Device Logical OUT Endpoint-Specific Registers B00h-CFCh */ ++ dwc_otg_dev_out_ep_regs_t *out_ep_regs[MAX_EPS_CHANNELS]; ++#define DWC_DEV_OUT_EP_REG_OFFSET 0xB00 ++ ++ /* Device configuration information */ ++ uint8_t speed; /**< Device Speed 0: Unknown, 1: LS, 2:FS, 3: HS */ ++ uint8_t num_in_eps; /**< Number # of Tx EP range: 0-15 exept ep0 */ ++ uint8_t num_out_eps; /**< Number # of Rx EP range: 0-15 exept ep 0*/ ++ ++ /** Size of periodic FIFOs (Bytes) */ ++ uint16_t perio_tx_fifo_size[MAX_PERIO_FIFOS]; ++ ++ /** Size of Tx FIFOs (Bytes) */ ++ uint16_t tx_fifo_size[MAX_TX_FIFOS]; ++ ++ /** Thresholding enable flags and length varaiables **/ ++ uint16_t rx_thr_en; ++ uint16_t iso_tx_thr_en; ++ uint16_t non_iso_tx_thr_en; ++ ++ uint16_t rx_thr_length; ++ uint16_t tx_thr_length; ++ ++ /** ++ * Pointers to the DMA Descriptors for EP0 Control ++ * transfers (virtual and physical) ++ */ ++ ++ /** 2 descriptors for SETUP packets */ ++ dwc_dma_t dma_setup_desc_addr[2]; ++ dwc_otg_dev_dma_desc_t *setup_desc_addr[2]; ++ ++ /** Pointer to Descriptor with latest SETUP packet */ ++ dwc_otg_dev_dma_desc_t *psetup; ++ ++ /** Index of current SETUP handler descriptor */ ++ uint32_t setup_desc_index; ++ ++ /** Descriptor for Data In or Status In phases */ ++ dwc_dma_t dma_in_desc_addr; ++ dwc_otg_dev_dma_desc_t *in_desc_addr; ++ ++ /** Descriptor for Data Out or Status Out phases */ ++ dwc_dma_t dma_out_desc_addr; ++ dwc_otg_dev_dma_desc_t *out_desc_addr; ++ ++ /** Setup Packet Detected - if set clear NAK when queueing */ ++ uint32_t spd; ++ ++} dwc_otg_dev_if_t; ++ ++///////////////////////////////////////////////// ++// Host Mode Register Structures ++// ++/** ++ * The Host Global Registers structure defines the size and relative ++ * field offsets for the Host Mode Global Registers. Host Global ++ * Registers offsets 400h-7FFh. ++*/ ++typedef struct dwc_otg_host_global_regs { ++ /** Host Configuration Register. Offset: 400h */ ++ volatile uint32_t hcfg; ++ /** Host Frame Interval Register. Offset: 404h */ ++ volatile uint32_t hfir; ++ /** Host Frame Number / Frame Remaining Register. Offset: 408h */ ++ volatile uint32_t hfnum; ++ /** Reserved. Offset: 40Ch */ ++ uint32_t reserved40C; ++ /** Host Periodic Transmit FIFO/ Queue Status Register. Offset: 410h */ ++ volatile uint32_t hptxsts; ++ /** Host All Channels Interrupt Register. Offset: 414h */ ++ volatile uint32_t haint; ++ /** Host All Channels Interrupt Mask Register. Offset: 418h */ ++ volatile uint32_t haintmsk; ++ /** Host Frame List Base Address Register . Offset: 41Ch */ ++ volatile uint32_t hflbaddr; ++} dwc_otg_host_global_regs_t; ++ ++ ++/** ++ * This union represents the bit fields in the Host Configuration Register. ++ * Read the register into the d32 member then set/clear the bits using ++ * the bit elements. Write the d32 member to the hcfg register. ++ */ ++typedef union hcfg_data ++{ ++ /** raw register data */ ++ uint32_t d32; ++ ++ /** register bits */ ++ struct ++ { ++ /** FS/LS Phy Clock Select */ ++ unsigned fslspclksel:2; ++#define DWC_HCFG_30_60_MHZ 0 ++#define DWC_HCFG_48_MHZ 1 ++#define DWC_HCFG_6_MHZ 2 ++ ++ /** FS/LS Only Support */ ++ unsigned fslssupp:1; ++ unsigned reserved3_22 : 20; ++ /** Enable Scatter/gather DMA in Host mode */ ++ unsigned descdma : 1; ++ /** Frame List Entries */ ++ unsigned frlisten: 2; ++ /** Enable Periodic Scheduling */ ++ unsigned perschedena: 1; ++ /** Periodic Scheduling Enabled Status */ ++ unsigned perschedstat: 1; ++ } b; ++} hcfg_data_t; ++ ++/** ++ * This union represents the bit fields in the Host Frame Remaing/Number ++ * Register. ++ */ ++typedef union hfir_data { ++ /** raw register data */ ++ uint32_t d32; ++ ++ /** register bits */ ++ struct { ++ unsigned frint:16; ++ unsigned reserved:16; ++ } b; ++} hfir_data_t; ++ ++/** ++ * This union represents the bit fields in the Host Frame Remaing/Number ++ * Register. ++ */ ++typedef union hfnum_data { ++ /** raw register data */ ++ uint32_t d32; ++ ++ /** register bits */ ++ struct { ++ unsigned frnum:16; ++#define DWC_HFNUM_MAX_FRNUM 0x3FFF ++ unsigned frrem:16; ++ } b; ++} hfnum_data_t; ++ ++typedef union hptxsts_data { ++ /** raw register data */ ++ uint32_t d32; ++ ++ /** register bits */ ++ struct { ++ unsigned ptxfspcavail:16; ++ unsigned ptxqspcavail:8; ++ /** Top of the Periodic Transmit Request Queue ++ * - bit 24 - Terminate (last entry for the selected channel) ++ * - bits 26:25 - Token Type ++ * - 2'b00 - Zero length ++ * - 2'b01 - Ping ++ * - 2'b10 - Disable ++ * - bits 30:27 - Channel Number ++ * - bit 31 - Odd/even microframe ++ */ ++ unsigned ptxqtop_terminate:1; ++ unsigned ptxqtop_token:2; ++ unsigned ptxqtop_chnum:4; ++ unsigned ptxqtop_odd:1; ++ } b; ++} hptxsts_data_t; ++ ++/** ++ * This union represents the bit fields in the Host Port Control and Status ++ * Register. Read the register into the d32 member then set/clear the ++ * bits using the bit elements. Write the d32 member to the ++ * hprt0 register. ++ */ ++typedef union hprt0_data { ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct { ++ unsigned prtconnsts:1; ++ unsigned prtconndet:1; ++ unsigned prtena:1; ++ unsigned prtenchng:1; ++ unsigned prtovrcurract:1; ++ unsigned prtovrcurrchng:1; ++ unsigned prtres:1; ++ unsigned prtsusp:1; ++ unsigned prtrst:1; ++ unsigned reserved9:1; ++ unsigned prtlnsts:2; ++ unsigned prtpwr:1; ++ unsigned prttstctl:4; ++ unsigned prtspd:2; ++#define DWC_HPRT0_PRTSPD_HIGH_SPEED 0 ++#define DWC_HPRT0_PRTSPD_FULL_SPEED 1 ++#define DWC_HPRT0_PRTSPD_LOW_SPEED 2 ++ unsigned reserved19_31:13; ++ } b; ++} hprt0_data_t; ++ ++/** ++ * This union represents the bit fields in the Host All Interrupt ++ * Register. ++ */ ++typedef union haint_data { ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct { ++ unsigned ch0:1; ++ unsigned ch1:1; ++ unsigned ch2:1; ++ unsigned ch3:1; ++ unsigned ch4:1; ++ unsigned ch5:1; ++ unsigned ch6:1; ++ unsigned ch7:1; ++ unsigned ch8:1; ++ unsigned ch9:1; ++ unsigned ch10:1; ++ unsigned ch11:1; ++ unsigned ch12:1; ++ unsigned ch13:1; ++ unsigned ch14:1; ++ unsigned ch15:1; ++ unsigned reserved:16; ++ } b; ++ ++ struct { ++ unsigned chint:16; ++ unsigned reserved:16; ++ } b2; ++} haint_data_t; ++ ++/** ++ * This union represents the bit fields in the Host All Interrupt ++ * Register. ++ */ ++typedef union haintmsk_data { ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct { ++ unsigned ch0:1; ++ unsigned ch1:1; ++ unsigned ch2:1; ++ unsigned ch3:1; ++ unsigned ch4:1; ++ unsigned ch5:1; ++ unsigned ch6:1; ++ unsigned ch7:1; ++ unsigned ch8:1; ++ unsigned ch9:1; ++ unsigned ch10:1; ++ unsigned ch11:1; ++ unsigned ch12:1; ++ unsigned ch13:1; ++ unsigned ch14:1; ++ unsigned ch15:1; ++ unsigned reserved:16; ++ } b; ++ ++ struct { ++ unsigned chint:16; ++ unsigned reserved:16; ++ } b2; ++} haintmsk_data_t; ++ ++/** ++ * Host Channel Specific Registers. 500h-5FCh ++ */ ++typedef struct dwc_otg_hc_regs ++{ ++ /** Host Channel 0 Characteristic Register. Offset: 500h + (chan_num * 20h) + 00h */ ++ volatile uint32_t hcchar; ++ /** Host Channel 0 Split Control Register. Offset: 500h + (chan_num * 20h) + 04h */ ++ volatile uint32_t hcsplt; ++ /** Host Channel 0 Interrupt Register. Offset: 500h + (chan_num * 20h) + 08h */ ++ volatile uint32_t hcint; ++ /** Host Channel 0 Interrupt Mask Register. Offset: 500h + (chan_num * 20h) + 0Ch */ ++ volatile uint32_t hcintmsk; ++ /** Host Channel 0 Transfer Size Register. Offset: 500h + (chan_num * 20h) + 10h */ ++ volatile uint32_t hctsiz; ++ /** Host Channel 0 DMA Address Register. Offset: 500h + (chan_num * 20h) + 14h */ ++ volatile uint32_t hcdma; ++ volatile uint32_t reserved; ++ /** Host Channel 0 DMA Buffer Address Register. Offset: 500h + (chan_num * 20h) + 1Ch */ ++ volatile uint32_t hcdmab; ++} dwc_otg_hc_regs_t; ++ ++/** ++ * This union represents the bit fields in the Host Channel Characteristics ++ * Register. Read the register into the d32 member then set/clear the ++ * bits using the bit elements. Write the d32 member to the ++ * hcchar register. ++ */ ++typedef union hcchar_data { ++ /** raw register data */ ++ uint32_t d32; ++ ++ /** register bits */ ++ struct { ++ /** Maximum packet size in bytes */ ++ unsigned mps:11; ++ ++ /** Endpoint number */ ++ unsigned epnum:4; ++ ++ /** 0: OUT, 1: IN */ ++ unsigned epdir:1; ++ ++ unsigned reserved:1; ++ ++ /** 0: Full/high speed device, 1: Low speed device */ ++ unsigned lspddev:1; ++ ++ /** 0: Control, 1: Isoc, 2: Bulk, 3: Intr */ ++ unsigned eptype:2; ++ ++ /** Packets per frame for periodic transfers. 0 is reserved. */ ++ unsigned multicnt:2; ++ ++ /** Device address */ ++ unsigned devaddr:7; ++ ++ /** ++ * Frame to transmit periodic transaction. ++ * 0: even, 1: odd ++ */ ++ unsigned oddfrm:1; ++ ++ /** Channel disable */ ++ unsigned chdis:1; ++ ++ /** Channel enable */ ++ unsigned chen:1; ++ } b; ++} hcchar_data_t; ++ ++typedef union hcsplt_data { ++ /** raw register data */ ++ uint32_t d32; ++ ++ /** register bits */ ++ struct { ++ /** Port Address */ ++ unsigned prtaddr:7; ++ ++ /** Hub Address */ ++ unsigned hubaddr:7; ++ ++ /** Transaction Position */ ++ unsigned xactpos:2; ++#define DWC_HCSPLIT_XACTPOS_MID 0 ++#define DWC_HCSPLIT_XACTPOS_END 1 ++#define DWC_HCSPLIT_XACTPOS_BEGIN 2 ++#define DWC_HCSPLIT_XACTPOS_ALL 3 ++ ++ /** Do Complete Split */ ++ unsigned compsplt:1; ++ ++ /** Reserved */ ++ unsigned reserved:14; ++ ++ /** Split Enble */ ++ unsigned spltena:1; ++ } b; ++} hcsplt_data_t; ++ ++/** ++ * This union represents the bit fields in the Host All Interrupt ++ * Register. ++ */ ++typedef union hcint_data ++{ ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct ++ { ++ /** Transfer Complete */ ++ unsigned xfercomp:1; ++ /** Channel Halted */ ++ unsigned chhltd:1; ++ /** AHB Error */ ++ unsigned ahberr:1; ++ /** STALL Response Received */ ++ unsigned stall:1; ++ /** NAK Response Received */ ++ unsigned nak:1; ++ /** ACK Response Received */ ++ unsigned ack:1; ++ /** NYET Response Received */ ++ unsigned nyet:1; ++ /** Transaction Err */ ++ unsigned xacterr:1; ++ /** Babble Error */ ++ unsigned bblerr:1; ++ /** Frame Overrun */ ++ unsigned frmovrun:1; ++ /** Data Toggle Error */ ++ unsigned datatglerr:1; ++ /** Buffer Not Available (only for DDMA mode) */ ++ unsigned bna : 1; ++ /** Exessive transaction error (only for DDMA mode) */ ++ unsigned xcs_xact : 1; ++ /** Frame List Rollover interrupt */ ++ unsigned frm_list_roll : 1; ++ /** Reserved */ ++ unsigned reserved14_31 : 18; ++ } b; ++} hcint_data_t; ++ ++/** ++ * This union represents the bit fields in the Host Channel Interrupt Mask ++ * Register. Read the register into the d32 member then set/clear the ++ * bits using the bit elements. Write the d32 member to the ++ * hcintmsk register. ++ */ ++typedef union hcintmsk_data ++{ ++ /** raw register data */ ++ uint32_t d32; ++ ++ /** register bits */ ++ struct ++ { ++ unsigned xfercompl : 1; ++ unsigned chhltd : 1; ++ unsigned ahberr : 1; ++ unsigned stall : 1; ++ unsigned nak : 1; ++ unsigned ack : 1; ++ unsigned nyet : 1; ++ unsigned xacterr : 1; ++ unsigned bblerr : 1; ++ unsigned frmovrun : 1; ++ unsigned datatglerr : 1; ++ unsigned bna : 1; ++ unsigned xcs_xact : 1; ++ unsigned frm_list_roll : 1; ++ unsigned reserved14_31 : 18; ++ } b; ++} hcintmsk_data_t; ++ ++/** ++ * This union represents the bit fields in the Host Channel Transfer Size ++ * Register. Read the register into the d32 member then set/clear the ++ * bits using the bit elements. Write the d32 member to the ++ * hcchar register. ++ */ ++ ++typedef union hctsiz_data ++{ ++ /** raw register data */ ++ uint32_t d32; ++ ++ /** register bits */ ++ struct ++ { ++ /** Total transfer size in bytes */ ++ unsigned xfersize:19; ++ ++ /** Data packets to transfer */ ++ unsigned pktcnt:10; ++ ++ /** ++ * Packet ID for next data packet ++ * 0: DATA0 ++ * 1: DATA2 ++ * 2: DATA1 ++ * 3: MDATA (non-Control), SETUP (Control) ++ */ ++ unsigned pid:2; ++#define DWC_HCTSIZ_DATA0 0 ++#define DWC_HCTSIZ_DATA1 2 ++#define DWC_HCTSIZ_DATA2 1 ++#define DWC_HCTSIZ_MDATA 3 ++#define DWC_HCTSIZ_SETUP 3 ++ ++ /** Do PING protocol when 1 */ ++ unsigned dopng:1; ++ } b; ++ ++ /** register bits */ ++ struct ++ { ++ /** Scheduling information */ ++ unsigned schinfo : 8; ++ ++ /** Number of transfer descriptors. ++ * Max value: ++ * 64 in general, ++ * 256 only for HS isochronous endpoint. ++ */ ++ unsigned ntd : 8; ++ ++ /** Data packets to transfer */ ++ unsigned reserved16_28 : 13; ++ ++ /** ++ * Packet ID for next data packet ++ * 0: DATA0 ++ * 1: DATA2 ++ * 2: DATA1 ++ * 3: MDATA (non-Control) ++ */ ++ unsigned pid : 2; ++ ++ /** Do PING protocol when 1 */ ++ unsigned dopng : 1; ++ } b_ddma; ++} hctsiz_data_t; ++ ++ ++/** ++ * This union represents the bit fields in the Host DMA Address ++ * Register used in Descriptor DMA mode. ++ */ ++typedef union hcdma_data ++{ ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct ++ { ++ unsigned reserved0_2 : 3; ++ /** Current Transfer Descriptor. Not used for ISOC */ ++ unsigned ctd : 8; ++ /** Start Address of Descriptor List */ ++ unsigned dma_addr : 21; ++ } b; ++} hcdma_data_t; ++ ++/** ++ * This union represents the bit fields in the DMA Descriptor ++ * status quadlet for host mode. Read the quadlet into the d32 member then ++ * set/clear the bits using the bit elements. ++ */ ++typedef union host_dma_desc_sts ++{ ++ /** raw register data */ ++ uint32_t d32; ++ /** quadlet bits */ ++ ++ /* for non-isochronous */ ++ struct { ++ /** Number of bytes */ ++ unsigned n_bytes : 17; ++ /** QTD offset to jump when Short Packet received - only for IN EPs */ ++ unsigned qtd_offset : 6; ++ /** ++ * Set to request the core to jump to alternate QTD if ++ * Short Packet received - only for IN EPs ++ */ ++ unsigned a_qtd : 1; ++ /** ++ * Setup Packet bit. When set indicates that buffer contains ++ * setup packet. ++ */ ++ unsigned sup : 1; ++ /** Interrupt On Complete */ ++ unsigned ioc : 1; ++ /** End of List */ ++ unsigned eol : 1; ++ unsigned reserved27 : 1; ++ /** Rx/Tx Status */ ++ unsigned sts : 2; ++ #define DMA_DESC_STS_PKTERR 1 ++ unsigned reserved30 : 1; ++ /** Active Bit */ ++ unsigned a : 1; ++ } b; ++ /* for isochronous */ ++ struct { ++ /** Number of bytes */ ++ unsigned n_bytes : 12; ++ unsigned reserved12_24 : 13; ++ /** Interrupt On Complete */ ++ unsigned ioc : 1; ++ unsigned reserved26_27 : 2; ++ /** Rx/Tx Status */ ++ unsigned sts : 2; ++ unsigned reserved30 : 1; ++ /** Active Bit */ ++ unsigned a : 1; ++ } b_isoc; ++} host_dma_desc_sts_t; ++ ++#define MAX_DMA_DESC_SIZE 131071 ++#define MAX_DMA_DESC_NUM_GENERIC 64 ++#define MAX_DMA_DESC_NUM_HS_ISOC 256 ++#define MAX_FRLIST_EN_NUM 64 ++/** ++ * Host-mode DMA Descriptor structure ++ * ++ * DMA Descriptor structure contains two quadlets: ++ * Status quadlet and Data buffer pointer. ++ */ ++typedef struct dwc_otg_host_dma_desc ++{ ++ /** DMA Descriptor status quadlet */ ++ host_dma_desc_sts_t status; ++ /** DMA Descriptor data buffer pointer */ ++ uint32_t buf; ++} dwc_otg_host_dma_desc_t; ++ ++/** OTG Host Interface Structure. ++ * ++ * The OTG Host Interface Structure structure contains information ++ * needed to manage the DWC_otg controller acting in host mode. It ++ * represents the programming view of the host-specific aspects of the ++ * controller. ++ */ ++typedef struct dwc_otg_host_if { ++ /** Host Global Registers starting at offset 400h.*/ ++ dwc_otg_host_global_regs_t *host_global_regs; ++#define DWC_OTG_HOST_GLOBAL_REG_OFFSET 0x400 ++ ++ /** Host Port 0 Control and Status Register */ ++ volatile uint32_t *hprt0; ++#define DWC_OTG_HOST_PORT_REGS_OFFSET 0x440 ++ ++ /** Host Channel Specific Registers at offsets 500h-5FCh. */ ++ dwc_otg_hc_regs_t *hc_regs[MAX_EPS_CHANNELS]; ++#define DWC_OTG_HOST_CHAN_REGS_OFFSET 0x500 ++#define DWC_OTG_CHAN_REGS_OFFSET 0x20 ++ ++ /* Host configuration information */ ++ /** Number of Host Channels (range: 1-16) */ ++ uint8_t num_host_channels; ++ /** Periodic EPs supported (0: no, 1: yes) */ ++ uint8_t perio_eps_supported; ++ /** Periodic Tx FIFO Size (Only 1 host periodic Tx FIFO) */ ++ uint16_t perio_tx_fifo_size; ++ ++} dwc_otg_host_if_t; ++ ++/** ++ * This union represents the bit fields in the Power and Clock Gating Control ++ * Register. Read the register into the d32 member then set/clear the ++ * bits using the bit elements. ++ */ ++typedef union pcgcctl_data { ++ /** raw register data */ ++ uint32_t d32; ++ ++ /** register bits */ ++ struct { ++ /** Stop Pclk */ ++ unsigned stoppclk:1; ++ /** Gate Hclk */ ++ unsigned gatehclk:1; ++ /** Power Clamp */ ++ unsigned pwrclmp:1; ++ /** Reset Power Down Modules */ ++ unsigned rstpdwnmodule:1; ++ /** PHY Suspended */ ++ unsigned physuspended:1; ++ /** Enable Sleep Clock Gating (Enbl_L1Gating) */ ++ unsigned enbl_sleep_gating:1; ++ /** PHY In Sleep (PhySleep) */ ++ unsigned phy_in_sleep:1; ++ /** Deep Sleep*/ ++ unsigned deep_sleep:1; ++ ++ unsigned reserved31_8:24; ++ } b; ++} pcgcctl_data_t; ++ ++#endif +Index: linux-3.2.46/drivers/usb/host/dwc_otg/test/Makefile +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/test/Makefile 2013-07-26 19:31:23.000000000 +0000 +@@ -0,0 +1,16 @@ ++ ++PERL=/usr/bin/perl ++PL_TESTS=test_sysfs.pl test_mod_param.pl ++ ++.PHONY : test ++test : perl_tests ++ ++perl_tests : ++ @echo ++ @echo Running perl tests ++ @for test in $(PL_TESTS); do \ ++ if $(PERL) ./$$test ; then \ ++ echo "=======> $$test, PASSED" ; \ ++ else echo "=======> $$test, FAILED" ; \ ++ fi \ ++ done +Index: linux-3.2.46/drivers/usb/host/dwc_otg/test/dwc_otg_test.pm +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/test/dwc_otg_test.pm 2013-07-26 19:31:23.000000000 +0000 +@@ -0,0 +1,337 @@ ++package dwc_otg_test; ++ ++use strict; ++use Exporter (); ++ ++use vars qw(@ISA @EXPORT ++$sysfsdir $paramdir $errors $params ++); ++ ++@ISA = qw(Exporter); ++ ++# ++# Globals ++# ++$sysfsdir = "/sys/devices/lm0"; ++$paramdir = "/sys/module/dwc_otg"; ++$errors = 0; ++ ++$params = [ ++ { ++ NAME => "otg_cap", ++ DEFAULT => 0, ++ ENUM => [], ++ LOW => 0, ++ HIGH => 2 ++ }, ++ { ++ NAME => "dma_enable", ++ DEFAULT => 0, ++ ENUM => [], ++ LOW => 0, ++ HIGH => 1 ++ }, ++ { ++ NAME => "dma_burst_size", ++ DEFAULT => 32, ++ ENUM => [1, 4, 8, 16, 32, 64, 128, 256], ++ LOW => 1, ++ HIGH => 256 ++ }, ++ { ++ NAME => "host_speed", ++ DEFAULT => 0, ++ ENUM => [], ++ LOW => 0, ++ HIGH => 1 ++ }, ++ { ++ NAME => "host_support_fs_ls_low_power", ++ DEFAULT => 0, ++ ENUM => [], ++ LOW => 0, ++ HIGH => 1 ++ }, ++ { ++ NAME => "host_ls_low_power_phy_clk", ++ DEFAULT => 0, ++ ENUM => [], ++ LOW => 0, ++ HIGH => 1 ++ }, ++ { ++ NAME => "dev_speed", ++ DEFAULT => 0, ++ ENUM => [], ++ LOW => 0, ++ HIGH => 1 ++ }, ++ { ++ NAME => "enable_dynamic_fifo", ++ DEFAULT => 1, ++ ENUM => [], ++ LOW => 0, ++ HIGH => 1 ++ }, ++ { ++ NAME => "data_fifo_size", ++ DEFAULT => 8192, ++ ENUM => [], ++ LOW => 32, ++ HIGH => 32768 ++ }, ++ { ++ NAME => "dev_rx_fifo_size", ++ DEFAULT => 1064, ++ ENUM => [], ++ LOW => 16, ++ HIGH => 32768 ++ }, ++ { ++ NAME => "dev_nperio_tx_fifo_size", ++ DEFAULT => 1024, ++ ENUM => [], ++ LOW => 16, ++ HIGH => 32768 ++ }, ++ { ++ NAME => "dev_perio_tx_fifo_size_1", ++ DEFAULT => 256, ++ ENUM => [], ++ LOW => 4, ++ HIGH => 768 ++ }, ++ { ++ NAME => "dev_perio_tx_fifo_size_2", ++ DEFAULT => 256, ++ ENUM => [], ++ LOW => 4, ++ HIGH => 768 ++ }, ++ { ++ NAME => "dev_perio_tx_fifo_size_3", ++ DEFAULT => 256, ++ ENUM => [], ++ LOW => 4, ++ HIGH => 768 ++ }, ++ { ++ NAME => "dev_perio_tx_fifo_size_4", ++ DEFAULT => 256, ++ ENUM => [], ++ LOW => 4, ++ HIGH => 768 ++ }, ++ { ++ NAME => "dev_perio_tx_fifo_size_5", ++ DEFAULT => 256, ++ ENUM => [], ++ LOW => 4, ++ HIGH => 768 ++ }, ++ { ++ NAME => "dev_perio_tx_fifo_size_6", ++ DEFAULT => 256, ++ ENUM => [], ++ LOW => 4, ++ HIGH => 768 ++ }, ++ { ++ NAME => "dev_perio_tx_fifo_size_7", ++ DEFAULT => 256, ++ ENUM => [], ++ LOW => 4, ++ HIGH => 768 ++ }, ++ { ++ NAME => "dev_perio_tx_fifo_size_8", ++ DEFAULT => 256, ++ ENUM => [], ++ LOW => 4, ++ HIGH => 768 ++ }, ++ { ++ NAME => "dev_perio_tx_fifo_size_9", ++ DEFAULT => 256, ++ ENUM => [], ++ LOW => 4, ++ HIGH => 768 ++ }, ++ { ++ NAME => "dev_perio_tx_fifo_size_10", ++ DEFAULT => 256, ++ ENUM => [], ++ LOW => 4, ++ HIGH => 768 ++ }, ++ { ++ NAME => "dev_perio_tx_fifo_size_11", ++ DEFAULT => 256, ++ ENUM => [], ++ LOW => 4, ++ HIGH => 768 ++ }, ++ { ++ NAME => "dev_perio_tx_fifo_size_12", ++ DEFAULT => 256, ++ ENUM => [], ++ LOW => 4, ++ HIGH => 768 ++ }, ++ { ++ NAME => "dev_perio_tx_fifo_size_13", ++ DEFAULT => 256, ++ ENUM => [], ++ LOW => 4, ++ HIGH => 768 ++ }, ++ { ++ NAME => "dev_perio_tx_fifo_size_14", ++ DEFAULT => 256, ++ ENUM => [], ++ LOW => 4, ++ HIGH => 768 ++ }, ++ { ++ NAME => "dev_perio_tx_fifo_size_15", ++ DEFAULT => 256, ++ ENUM => [], ++ LOW => 4, ++ HIGH => 768 ++ }, ++ { ++ NAME => "host_rx_fifo_size", ++ DEFAULT => 1024, ++ ENUM => [], ++ LOW => 16, ++ HIGH => 32768 ++ }, ++ { ++ NAME => "host_nperio_tx_fifo_size", ++ DEFAULT => 1024, ++ ENUM => [], ++ LOW => 16, ++ HIGH => 32768 ++ }, ++ { ++ NAME => "host_perio_tx_fifo_size", ++ DEFAULT => 1024, ++ ENUM => [], ++ LOW => 16, ++ HIGH => 32768 ++ }, ++ { ++ NAME => "max_transfer_size", ++ DEFAULT => 65535, ++ ENUM => [], ++ LOW => 2047, ++ HIGH => 65535 ++ }, ++ { ++ NAME => "max_packet_count", ++ DEFAULT => 511, ++ ENUM => [], ++ LOW => 15, ++ HIGH => 511 ++ }, ++ { ++ NAME => "host_channels", ++ DEFAULT => 12, ++ ENUM => [], ++ LOW => 1, ++ HIGH => 16 ++ }, ++ { ++ NAME => "dev_endpoints", ++ DEFAULT => 6, ++ ENUM => [], ++ LOW => 1, ++ HIGH => 15 ++ }, ++ { ++ NAME => "phy_type", ++ DEFAULT => 1, ++ ENUM => [], ++ LOW => 0, ++ HIGH => 2 ++ }, ++ { ++ NAME => "phy_utmi_width", ++ DEFAULT => 16, ++ ENUM => [8, 16], ++ LOW => 8, ++ HIGH => 16 ++ }, ++ { ++ NAME => "phy_ulpi_ddr", ++ DEFAULT => 0, ++ ENUM => [], ++ LOW => 0, ++ HIGH => 1 ++ }, ++ ]; ++ ++ ++# ++# ++sub check_arch { ++ $_ = `uname -m`; ++ chomp; ++ unless (m/armv4tl/) { ++ warn "# \n# Can't execute on $_. Run on integrator platform.\n# \n"; ++ return 0; ++ } ++ return 1; ++} ++ ++# ++# ++sub load_module { ++ my $params = shift; ++ print "\nRemoving Module\n"; ++ system "rmmod dwc_otg"; ++ print "Loading Module\n"; ++ if ($params ne "") { ++ print "Module Parameters: $params\n"; ++ } ++ if (system("modprobe dwc_otg $params")) { ++ warn "Unable to load module\n"; ++ return 0; ++ } ++ return 1; ++} ++ ++# ++# ++sub test_status { ++ my $arg = shift; ++ ++ print "\n"; ++ ++ if (defined $arg) { ++ warn "WARNING: $arg\n"; ++ } ++ ++ if ($errors > 0) { ++ warn "TEST FAILED with $errors errors\n"; ++ return 0; ++ } else { ++ print "TEST PASSED\n"; ++ return 0 if (defined $arg); ++ } ++ return 1; ++} ++ ++# ++# ++@EXPORT = qw( ++$sysfsdir ++$paramdir ++$params ++$errors ++check_arch ++load_module ++test_status ++); ++ ++1; +Index: linux-3.2.46/drivers/usb/host/dwc_otg/test/test_mod_param.pl +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/test/test_mod_param.pl 2013-07-26 19:31:23.000000000 +0000 +@@ -0,0 +1,133 @@ ++#!/usr/bin/perl -w ++# ++# Run this program on the integrator. ++# ++# - Tests module parameter default values. ++# - Tests setting of valid module parameter values via modprobe. ++# - Tests invalid module parameter values. ++# ----------------------------------------------------------------------------- ++use strict; ++use dwc_otg_test; ++ ++check_arch() or die; ++ ++# ++# ++sub test { ++ my ($param,$expected) = @_; ++ my $value = get($param); ++ ++ if ($value == $expected) { ++ print "$param = $value, okay\n"; ++ } ++ ++ else { ++ warn "ERROR: value of $param != $expected, $value\n"; ++ $errors ++; ++ } ++} ++ ++# ++# ++sub get { ++ my $param = shift; ++ my $tmp = `cat $paramdir/$param`; ++ chomp $tmp; ++ return $tmp; ++} ++ ++# ++# ++sub test_main { ++ ++ print "\nTesting Module Parameters\n"; ++ ++ load_module("") or die; ++ ++ # Test initial values ++ print "\nTesting Default Values\n"; ++ foreach (@{$params}) { ++ test ($_->{NAME}, $_->{DEFAULT}); ++ } ++ ++ # Test low value ++ print "\nTesting Low Value\n"; ++ my $cmd_params = ""; ++ foreach (@{$params}) { ++ $cmd_params = $cmd_params . "$_->{NAME}=$_->{LOW} "; ++ } ++ load_module($cmd_params) or die; ++ ++ foreach (@{$params}) { ++ test ($_->{NAME}, $_->{LOW}); ++ } ++ ++ # Test high value ++ print "\nTesting High Value\n"; ++ $cmd_params = ""; ++ foreach (@{$params}) { ++ $cmd_params = $cmd_params . "$_->{NAME}=$_->{HIGH} "; ++ } ++ load_module($cmd_params) or die; ++ ++ foreach (@{$params}) { ++ test ($_->{NAME}, $_->{HIGH}); ++ } ++ ++ # Test Enum ++ print "\nTesting Enumerated\n"; ++ foreach (@{$params}) { ++ if (defined $_->{ENUM}) { ++ my $value; ++ foreach $value (@{$_->{ENUM}}) { ++ $cmd_params = "$_->{NAME}=$value"; ++ load_module($cmd_params) or die; ++ test ($_->{NAME}, $value); ++ } ++ } ++ } ++ ++ # Test Invalid Values ++ print "\nTesting Invalid Values\n"; ++ $cmd_params = ""; ++ foreach (@{$params}) { ++ $cmd_params = $cmd_params . sprintf "$_->{NAME}=%d ", $_->{LOW}-1; ++ } ++ load_module($cmd_params) or die; ++ ++ foreach (@{$params}) { ++ test ($_->{NAME}, $_->{DEFAULT}); ++ } ++ ++ $cmd_params = ""; ++ foreach (@{$params}) { ++ $cmd_params = $cmd_params . sprintf "$_->{NAME}=%d ", $_->{HIGH}+1; ++ } ++ load_module($cmd_params) or die; ++ ++ foreach (@{$params}) { ++ test ($_->{NAME}, $_->{DEFAULT}); ++ } ++ ++ print "\nTesting Enumerated\n"; ++ foreach (@{$params}) { ++ if (defined $_->{ENUM}) { ++ my $value; ++ foreach $value (@{$_->{ENUM}}) { ++ $value = $value + 1; ++ $cmd_params = "$_->{NAME}=$value"; ++ load_module($cmd_params) or die; ++ test ($_->{NAME}, $_->{DEFAULT}); ++ $value = $value - 2; ++ $cmd_params = "$_->{NAME}=$value"; ++ load_module($cmd_params) or die; ++ test ($_->{NAME}, $_->{DEFAULT}); ++ } ++ } ++ } ++ ++ test_status() or die; ++} ++ ++test_main(); ++0; +Index: linux-3.2.46/drivers/usb/host/dwc_otg/test/test_sysfs.pl +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/test/test_sysfs.pl 2013-07-26 19:31:23.000000000 +0000 +@@ -0,0 +1,193 @@ ++#!/usr/bin/perl -w ++# ++# Run this program on the integrator ++# - Tests select sysfs attributes. ++# - Todo ... test more attributes, hnp/srp, buspower/bussuspend, etc. ++# ----------------------------------------------------------------------------- ++use strict; ++use dwc_otg_test; ++ ++check_arch() or die; ++ ++# ++# ++sub test { ++ my ($attr,$expected) = @_; ++ my $string = get($attr); ++ ++ if ($string eq $expected) { ++ printf("$attr = $string, okay\n"); ++ } ++ else { ++ warn "ERROR: value of $attr != $expected, $string\n"; ++ $errors ++; ++ } ++} ++ ++# ++# ++sub set { ++ my ($reg, $value) = @_; ++ system "echo $value > $sysfsdir/$reg"; ++} ++ ++# ++# ++sub get { ++ my $attr = shift; ++ my $string = `cat $sysfsdir/$attr`; ++ chomp $string; ++ if ($string =~ m/\s\=\s/) { ++ my $tmp; ++ ($tmp, $string) = split /\s=\s/, $string; ++ } ++ return $string; ++} ++ ++# ++# ++sub test_main { ++ print("\nTesting Sysfs Attributes\n"); ++ ++ load_module("") or die; ++ ++ # Test initial values of regoffset/regvalue/guid/gsnpsid ++ print("\nTesting Default Values\n"); ++ ++ test("regoffset", "0xffffffff"); ++ test("regvalue", "invalid offset"); ++ test("guid", "0x12345678"); # this will fail if it has been changed ++ test("gsnpsid", "0x4f54200a"); ++ ++ # Test operation of regoffset/regvalue ++ print("\nTesting regoffset\n"); ++ set('regoffset', '5a5a5a5a'); ++ test("regoffset", "0xffffffff"); ++ ++ set('regoffset', '0'); ++ test("regoffset", "0x00000000"); ++ ++ set('regoffset', '40000'); ++ test("regoffset", "0x00000000"); ++ ++ set('regoffset', '3ffff'); ++ test("regoffset", "0x0003ffff"); ++ ++ set('regoffset', '1'); ++ test("regoffset", "0x00000001"); ++ ++ print("\nTesting regvalue\n"); ++ set('regoffset', '3c'); ++ test("regvalue", "0x12345678"); ++ set('regvalue', '5a5a5a5a'); ++ test("regvalue", "0x5a5a5a5a"); ++ set('regvalue','a5a5a5a5'); ++ test("regvalue", "0xa5a5a5a5"); ++ set('guid','12345678'); ++ ++ # Test HNP Capable ++ print("\nTesting HNP Capable bit\n"); ++ set('hnpcapable', '1'); ++ test("hnpcapable", "0x1"); ++ set('hnpcapable','0'); ++ test("hnpcapable", "0x0"); ++ ++ set('regoffset','0c'); ++ ++ my $old = get('gusbcfg'); ++ print("setting hnpcapable\n"); ++ set('hnpcapable', '1'); ++ test("hnpcapable", "0x1"); ++ test('gusbcfg', sprintf "0x%08x", (oct ($old) | (1<<9))); ++ test('regvalue', sprintf "0x%08x", (oct ($old) | (1<<9))); ++ ++ $old = get('gusbcfg'); ++ print("clearing hnpcapable\n"); ++ set('hnpcapable', '0'); ++ test("hnpcapable", "0x0"); ++ test ('gusbcfg', sprintf "0x%08x", oct ($old) & (~(1<<9))); ++ test ('regvalue', sprintf "0x%08x", oct ($old) & (~(1<<9))); ++ ++ # Test SRP Capable ++ print("\nTesting SRP Capable bit\n"); ++ set('srpcapable', '1'); ++ test("srpcapable", "0x1"); ++ set('srpcapable','0'); ++ test("srpcapable", "0x0"); ++ ++ set('regoffset','0c'); ++ ++ $old = get('gusbcfg'); ++ print("setting srpcapable\n"); ++ set('srpcapable', '1'); ++ test("srpcapable", "0x1"); ++ test('gusbcfg', sprintf "0x%08x", (oct ($old) | (1<<8))); ++ test('regvalue', sprintf "0x%08x", (oct ($old) | (1<<8))); ++ ++ $old = get('gusbcfg'); ++ print("clearing srpcapable\n"); ++ set('srpcapable', '0'); ++ test("srpcapable", "0x0"); ++ test('gusbcfg', sprintf "0x%08x", oct ($old) & (~(1<<8))); ++ test('regvalue', sprintf "0x%08x", oct ($old) & (~(1<<8))); ++ ++ # Test GGPIO ++ print("\nTesting GGPIO\n"); ++ set('ggpio','5a5a5a5a'); ++ test('ggpio','0x5a5a0000'); ++ set('ggpio','a5a5a5a5'); ++ test('ggpio','0xa5a50000'); ++ set('ggpio','11110000'); ++ test('ggpio','0x11110000'); ++ set('ggpio','00001111'); ++ test('ggpio','0x00000000'); ++ ++ # Test DEVSPEED ++ print("\nTesting DEVSPEED\n"); ++ set('regoffset','800'); ++ $old = get('regvalue'); ++ set('devspeed','0'); ++ test('devspeed','0x0'); ++ test('regvalue',sprintf("0x%08x", oct($old) & ~(0x3))); ++ set('devspeed','1'); ++ test('devspeed','0x1'); ++ test('regvalue',sprintf("0x%08x", oct($old) & ~(0x3) | 1)); ++ set('devspeed','2'); ++ test('devspeed','0x2'); ++ test('regvalue',sprintf("0x%08x", oct($old) & ~(0x3) | 2)); ++ set('devspeed','3'); ++ test('devspeed','0x3'); ++ test('regvalue',sprintf("0x%08x", oct($old) & ~(0x3) | 3)); ++ set('devspeed','4'); ++ test('devspeed','0x0'); ++ test('regvalue',sprintf("0x%08x", oct($old) & ~(0x3))); ++ set('devspeed','5'); ++ test('devspeed','0x1'); ++ test('regvalue',sprintf("0x%08x", oct($old) & ~(0x3) | 1)); ++ ++ ++ # mode Returns the current mode:0 for device mode1 for host mode Read ++ # hnp Initiate the Host Negotiation Protocol. Read returns the status. Read/Write ++ # srp Initiate the Session Request Protocol. Read returns the status. Read/Write ++ # buspower Get or Set the Power State of the bus (0 - Off or 1 - On) Read/Write ++ # bussuspend Suspend the USB bus. Read/Write ++ # busconnected Get the connection status of the bus Read ++ ++ # gotgctl Get or set the Core Control Status Register. Read/Write ++ ## gusbcfg Get or set the Core USB Configuration Register Read/Write ++ # grxfsiz Get or set the Receive FIFO Size Register Read/Write ++ # gnptxfsiz Get or set the non-periodic Transmit Size Register Read/Write ++ # gpvndctl Get or set the PHY Vendor Control Register Read/Write ++ ## ggpio Get the value in the lower 16-bits of the General Purpose IO Register or Set the upper 16 bits. Read/Write ++ ## guid Get or set the value of the User ID Register Read/Write ++ ## gsnpsid Get the value of the Synopsys ID Regester Read ++ ## devspeed Get or set the device speed setting in the DCFG register Read/Write ++ # enumspeed Gets the device enumeration Speed. Read ++ # hptxfsiz Get the value of the Host Periodic Transmit FIFO Read ++ # hprt0 Get or Set the value in the Host Port Control and Status Register Read/Write ++ ++ test_status("TEST NYI") or die; ++} ++ ++test_main(); ++0; diff -Nru linux-3.2.46/debian/patches/rpi/rpi_101_031ee3ef3d0db7aa9b704650300e20f274b2047b.patch linux-3.2.46/debian/patches/rpi/rpi_101_031ee3ef3d0db7aa9b704650300e20f274b2047b.patch --- linux-3.2.46/debian/patches/rpi/rpi_101_031ee3ef3d0db7aa9b704650300e20f274b2047b.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_101_031ee3ef3d0db7aa9b704650300e20f274b2047b.patch 2013-07-26 19:31:56.000000000 +0000 @@ -0,0 +1,10973 @@ +commit 031ee3ef3d0db7aa9b704650300e20f274b2047b +Author: popcornmix +Date: Tue Jan 17 19:20:11 2012 +0000 + + Main bcm2708 linux port + + Signed-off-by: popcornmix + +Index: linux-3.2.46/arch/arm/Kconfig +=================================================================== +--- linux-3.2.46.orig/arch/arm/Kconfig 2013-07-26 19:24:04.000000000 +0000 ++++ linux-3.2.46/arch/arm/Kconfig 2013-07-26 19:31:51.000000000 +0000 +@@ -957,6 +957,19 @@ + help + Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx). + ++config ARCH_BCM2708 ++ bool "Broadcom BCM2708 family" ++ select CPU_V6 ++ select ARM_AMBA ++ select HAVE_CLK ++ select CLKDEV_LOOKUP ++ select GENERIC_CLOCKEVENTS ++ select ARM_ERRATA_411920 ++ select MACH_BCM2708 ++ select VC4 ++ help ++ This enables support for Broadcom BCM2708 boards. ++ + config ARCH_VT8500 + bool "VIA/WonderMedia 85xx" + select CPU_ARM926T +@@ -1100,6 +1113,7 @@ + source "arch/arm/mach-vt8500/Kconfig" + + source "arch/arm/mach-w90x900/Kconfig" ++source "arch/arm/mach-bcm2708/Kconfig" + + # Definitions to make life easier + config ARCH_ACORN +Index: linux-3.2.46/arch/arm/Makefile +=================================================================== +--- linux-3.2.46.orig/arch/arm/Makefile 2013-07-26 19:24:01.000000000 +0000 ++++ linux-3.2.46/arch/arm/Makefile 2013-07-26 19:31:51.000000000 +0000 +@@ -198,6 +198,7 @@ + machine-$(CONFIG_MACH_SPEAR320) := spear3xx + machine-$(CONFIG_MACH_SPEAR600) := spear6xx + machine-$(CONFIG_ARCH_ZYNQ) := zynq ++machine-$(CONFIG_ARCH_BCM2708) := bcm2708 + + # Platform directory name. This list is sorted alphanumerically + # by CONFIG_* macro name. +Index: linux-3.2.46/arch/arm/boot/compressed/Makefile +=================================================================== +--- linux-3.2.46.orig/arch/arm/boot/compressed/Makefile 2013-05-30 13:35:16.000000000 +0000 ++++ linux-3.2.46/arch/arm/boot/compressed/Makefile 2013-07-26 19:31:51.000000000 +0000 +@@ -145,11 +145,17 @@ + LDFLAGS_vmlinux += -T + + # For __aeabi_uidivmod +-lib1funcs = $(obj)/lib1funcs.o ++lib1funcs = $(obj)/lib1funcs.o $(obj)/divdi3.o + + $(obj)/lib1funcs.S: $(srctree)/arch/$(SRCARCH)/lib/lib1funcs.S + $(call cmd,shipped) + ++$(obj)/longlong.h: $(srctree)/arch/$(SRCARCH)/lib/longlong.h FORCE ++ $(call cmd,shipped) ++ ++$(obj)/divdi3.c: $(srctree)/arch/$(SRCARCH)/lib/divdi3.c $(obj)/longlong.h FORCE ++ $(call cmd,shipped) ++ + # We need to prevent any GOTOFF relocs being used with references + # to symbols in the .bss section since we cannot relocate them + # independently from the rest at run time. This can be achieved by +Index: linux-3.2.46/arch/arm/boot/compressed/divdi3.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/arch/arm/boot/compressed/divdi3.c 2013-07-26 19:31:51.000000000 +0000 +@@ -0,0 +1,338 @@ ++/* 64-bit multiplication and division ++ Copyright (C) 1989, 1992-1999, 2000, 2001, 2002, 2003 ++ Free Software Foundation, Inc. ++ This file is part of the GNU C Library. ++ ++ The GNU C Library is free software; you can redistribute it and/or ++ modify it under the terms of the GNU Lesser General Public ++ License as published by the Free Software Foundation; either ++ version 2.1 of the License, or (at your option) any later version. ++ ++ The GNU C Library is distributed in the hope that it will be useful, ++ but WITHOUT ANY WARRANTY; without even the implied warranty of ++ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++ Lesser General Public License for more details. ++ ++ You should have received a copy of the GNU Lesser General Public ++ License along with the GNU C Library; if not, write to the Free ++ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA ++ 02111-1307 USA. */ ++ ++#include "longlong.h" ++ ++#define W_TYPE_SIZE (sizeof(long)) ++ ++#ifdef __ARMEB__ ++struct DWstruct { long high, low;}; ++#else ++struct DWstruct { long low, high;}; ++#endif ++ ++typedef union { struct DWstruct s; long long ll; } DWunion; ++ ++/* Prototypes of exported functions. */ ++long long __divdi3 (long long u, long long v); ++long long __moddi3 (long long u, long long v); ++unsigned long long __udivdi3 (unsigned long long u, unsigned long long v); ++unsigned long long __umoddi3 (unsigned long long u, unsigned long long v); ++ ++static unsigned long long ++__udivmoddi4 (unsigned long long n, unsigned long long d, unsigned long long *rp) ++{ ++ DWunion ww; ++ DWunion nn, dd; ++ DWunion rr; ++ unsigned long d0, d1, n0, n1, n2; ++ unsigned long q0, q1; ++ unsigned long b, bm; ++ ++ nn.ll = n; ++ dd.ll = d; ++ ++ d0 = dd.s.low; ++ d1 = dd.s.high; ++ n0 = nn.s.low; ++ n1 = nn.s.high; ++ ++#if !UDIV_NEEDS_NORMALIZATION ++ if (d1 == 0) ++ { ++ if (d0 > n1) ++ { ++ /* 0q = nn / 0D */ ++ ++ udiv_qrnnd (q0, n0, n1, n0, d0); ++ q1 = 0; ++ ++ /* Remainder in n0. */ ++ } ++ else ++ { ++ /* qq = NN / 0d */ ++ ++ if (d0 == 0) ++ d0 = 1 / d0; /* Divide intentionally by zero. */ ++ ++ udiv_qrnnd (q1, n1, 0, n1, d0); ++ udiv_qrnnd (q0, n0, n1, n0, d0); ++ ++ /* Remainder in n0. */ ++ } ++ ++ if (rp != 0) ++ { ++ rr.s.low = n0; ++ rr.s.high = 0; ++ *rp = rr.ll; ++ } ++ } ++ ++#else /* UDIV_NEEDS_NORMALIZATION */ ++ ++ if (d1 == 0) ++ { ++ if (d0 > n1) ++ { ++ /* 0q = nn / 0D */ ++ ++ count_leading_zeros (bm, d0); ++ ++ if (bm != 0) ++ { ++ /* Normalize, i.e. make the most significant bit of the ++ denominator set. */ ++ ++ d0 = d0 << bm; ++ n1 = (n1 << bm) | (n0 >> (W_TYPE_SIZE - bm)); ++ n0 = n0 << bm; ++ } ++ ++ udiv_qrnnd (q0, n0, n1, n0, d0); ++ q1 = 0; ++ ++ /* Remainder in n0 >> bm. */ ++ } ++ else ++ { ++ /* qq = NN / 0d */ ++ ++ if (d0 == 0) ++ d0 = 1 / d0; /* Divide intentionally by zero. */ ++ ++ count_leading_zeros (bm, d0); ++ ++ if (bm == 0) ++ { ++ /* From (n1 >= d0) /\ (the most significant bit of d0 is set), ++ conclude (the most significant bit of n1 is set) /\ (the ++ leading quotient digit q1 = 1). ++ ++ This special case is necessary, not an optimization. ++ (Shifts counts of W_TYPE_SIZE are undefined.) */ ++ ++ n1 -= d0; ++ q1 = 1; ++ } ++ else ++ { ++ /* Normalize. */ ++ ++ b = W_TYPE_SIZE - bm; ++ ++ d0 = d0 << bm; ++ n2 = n1 >> b; ++ n1 = (n1 << bm) | (n0 >> b); ++ n0 = n0 << bm; ++ ++ udiv_qrnnd (q1, n1, n2, n1, d0); ++ } ++ ++ /* n1 != d0... */ ++ ++ udiv_qrnnd (q0, n0, n1, n0, d0); ++ ++ /* Remainder in n0 >> bm. */ ++ } ++ ++ if (rp != 0) ++ { ++ rr.s.low = n0 >> bm; ++ rr.s.high = 0; ++ *rp = rr.ll; ++ } ++ } ++#endif /* UDIV_NEEDS_NORMALIZATION */ ++ ++ else ++ { ++ if (d1 > n1) ++ { ++ /* 00 = nn / DD */ ++ ++ q0 = 0; ++ q1 = 0; ++ ++ /* Remainder in n1n0. */ ++ if (rp != 0) ++ { ++ rr.s.low = n0; ++ rr.s.high = n1; ++ *rp = rr.ll; ++ } ++ } ++ else ++ { ++ /* 0q = NN / dd */ ++ ++ count_leading_zeros (bm, d1); ++ if (bm == 0) ++ { ++ /* From (n1 >= d1) /\ (the most significant bit of d1 is set), ++ conclude (the most significant bit of n1 is set) /\ (the ++ quotient digit q0 = 0 or 1). ++ ++ This special case is necessary, not an optimization. */ ++ ++ /* The condition on the next line takes advantage of that ++ n1 >= d1 (true due to program flow). */ ++ if (n1 > d1 || n0 >= d0) ++ { ++ q0 = 1; ++ sub_ddmmss (n1, n0, n1, n0, d1, d0); ++ } ++ else ++ q0 = 0; ++ ++ q1 = 0; ++ ++ if (rp != 0) ++ { ++ rr.s.low = n0; ++ rr.s.high = n1; ++ *rp = rr.ll; ++ } ++ } ++ else ++ { ++ unsigned long m1, m0; ++ /* Normalize. */ ++ ++ b = W_TYPE_SIZE - bm; ++ ++ d1 = (d1 << bm) | (d0 >> b); ++ d0 = d0 << bm; ++ n2 = n1 >> b; ++ n1 = (n1 << bm) | (n0 >> b); ++ n0 = n0 << bm; ++ ++ udiv_qrnnd (q0, n1, n2, n1, d1); ++ umul_ppmm (m1, m0, q0, d0); ++ ++ if (m1 > n1 || (m1 == n1 && m0 > n0)) ++ { ++ q0--; ++ sub_ddmmss (m1, m0, m1, m0, d1, d0); ++ } ++ ++ q1 = 0; ++ ++ /* Remainder in (n1n0 - m1m0) >> bm. */ ++ if (rp != 0) ++ { ++ sub_ddmmss (n1, n0, n1, n0, m1, m0); ++ rr.s.low = (n1 << b) | (n0 >> bm); ++ rr.s.high = n1 >> bm; ++ *rp = rr.ll; ++ } ++ } ++ } ++ } ++ ++ ww.s.low = q0; ++ ww.s.high = q1; ++ return ww.ll; ++} ++ ++long long ++__divdi3 (long long u, long long v) ++{ ++ long c = 0; ++ long long w; ++ ++ if (u < 0) ++ { ++ c = ~c; ++ u = -u; ++ } ++ if (v < 0) ++ { ++ c = ~c; ++ v = -v; ++ } ++ w = __udivmoddi4 (u, v, 0); ++ if (c) ++ w = -w; ++ return w; ++} ++ ++long long ++__moddi3 (long long u, long long v) ++{ ++ long c = 0; ++ long long w; ++ ++ if (u < 0) ++ { ++ c = ~c; ++ u = -u; ++ } ++ if (v < 0) ++ v = -v; ++ __udivmoddi4 (u, v, &w); ++ if (c) ++ w = -w; ++ return w; ++} ++ ++unsigned long long ++__udivdi3 (unsigned long long u, unsigned long long v) ++{ ++ return __udivmoddi4 (u, v, 0); ++} ++ ++unsigned long long ++__umoddi3 (unsigned long long u, unsigned long long v) ++{ ++ unsigned long long w; ++ ++ __udivmoddi4 (u, v, &w); ++ return w; ++} ++ ++long long ++__gnu_ldivmod_helper (long long a, ++ ++ long long b, ++ long long *remainder) ++{ ++ long long quotient; ++ ++ quotient = __divdi3 (a, b); ++ *remainder = a - b * quotient; ++ ++ return quotient; ++} ++ ++unsigned long long ++ ++__gnu_uldivmod_helper (unsigned long long a, ++ ++ unsigned long long b, ++ unsigned long long *remainder) ++{ ++ unsigned long long quotient; ++ ++ quotient = __udivdi3 (a, b); ++ *remainder = a - b * quotient; ++ return quotient; ++} +Index: linux-3.2.46/arch/arm/boot/compressed/longlong.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/arch/arm/boot/compressed/longlong.h 2013-07-26 19:31:51.000000000 +0000 +@@ -0,0 +1,151 @@ ++/* longlong.h -- based on code from gcc-2.95.3 ++ ++ definitions for mixed size 32/64 bit arithmetic. ++ Copyright (C) 1991, 92, 94, 95, 96, 1997, 1998 Free Software Foundation, Inc. ++ ++ This definition file is free software; you can redistribute it ++ and/or modify it under the terms of the GNU General Public ++ License as published by the Free Software Foundation; either ++ version 2, or (at your option) any later version. ++ ++ This definition file is distributed in the hope that it will be ++ useful, but WITHOUT ANY WARRANTY; without even the implied ++ warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. ++ See the GNU General Public License for more details. ++ ++ You should have received a copy of the GNU General Public License ++ along with this program; if not, write to the Free Software ++ Foundation, Inc., 59 Temple Place - Suite 330, ++ Boston, MA 02111-1307, USA. */ ++ ++/* Borrowed from GCC 2.95.3, I Molton 29/07/01 */ ++ ++#define USItype unsigned long ++#define SI_TYPE_SIZE sizeof(USItype) ++ ++#define __BITS4 (SI_TYPE_SIZE / 4) ++#define __ll_B (1L << (SI_TYPE_SIZE / 2)) ++#define __ll_lowpart(t) ((USItype) (t) % __ll_B) ++#define __ll_highpart(t) ((USItype) (t) / __ll_B) ++ ++/* Define auxiliary asm macros. ++ ++ 1) umul_ppmm(high_prod, low_prod, multipler, multiplicand) ++ multiplies two USItype integers MULTIPLER and MULTIPLICAND, ++ and generates a two-part USItype product in HIGH_PROD and ++ LOW_PROD. ++ ++ 2) __umulsidi3(a,b) multiplies two USItype integers A and B, ++ and returns a UDItype product. This is just a variant of umul_ppmm. ++ ++ 3) udiv_qrnnd(quotient, remainder, high_numerator, low_numerator, ++ denominator) divides a two-word unsigned integer, composed by the ++ integers HIGH_NUMERATOR and LOW_NUMERATOR, by DENOMINATOR and ++ places the quotient in QUOTIENT and the remainder in REMAINDER. ++ HIGH_NUMERATOR must be less than DENOMINATOR for correct operation. ++ If, in addition, the most significant bit of DENOMINATOR must be 1, ++ then the pre-processor symbol UDIV_NEEDS_NORMALIZATION is defined to 1. ++ ++ 4) sdiv_qrnnd(quotient, remainder, high_numerator, low_numerator, ++ denominator). Like udiv_qrnnd but the numbers are signed. The ++ quotient is rounded towards 0. ++ ++ 5) count_leading_zeros(count, x) counts the number of zero-bits from ++ the msb to the first non-zero bit. This is the number of steps X ++ needs to be shifted left to set the msb. Undefined for X == 0. ++ ++ 6) add_ssaaaa(high_sum, low_sum, high_addend_1, low_addend_1, ++ high_addend_2, low_addend_2) adds two two-word unsigned integers, ++ composed by HIGH_ADDEND_1 and LOW_ADDEND_1, and HIGH_ADDEND_2 and ++ LOW_ADDEND_2 respectively. The result is placed in HIGH_SUM and ++ LOW_SUM. Overflow (i.e. carry out) is not stored anywhere, and is ++ lost. ++ ++ 7) sub_ddmmss(high_difference, low_difference, high_minuend, ++ low_minuend, high_subtrahend, low_subtrahend) subtracts two ++ two-word unsigned integers, composed by HIGH_MINUEND_1 and ++ LOW_MINUEND_1, and HIGH_SUBTRAHEND_2 and LOW_SUBTRAHEND_2 ++ respectively. The result is placed in HIGH_DIFFERENCE and ++ LOW_DIFFERENCE. Overflow (i.e. carry out) is not stored anywhere, ++ and is lost. ++ ++ If any of these macros are left undefined for a particular CPU, ++ C macros are used. */ ++ ++#if defined (__arm__) ++#define add_ssaaaa(sh, sl, ah, al, bh, bl) \ ++ __asm__ ("adds %1, %4, %5 \n\ ++ adc %0, %2, %3" \ ++ : "=r" ((USItype) (sh)), \ ++ "=&r" ((USItype) (sl)) \ ++ : "%r" ((USItype) (ah)), \ ++ "rI" ((USItype) (bh)), \ ++ "%r" ((USItype) (al)), \ ++ "rI" ((USItype) (bl))) ++#define sub_ddmmss(sh, sl, ah, al, bh, bl) \ ++ __asm__ ("subs %1, %4, %5 \n\ ++ sbc %0, %2, %3" \ ++ : "=r" ((USItype) (sh)), \ ++ "=&r" ((USItype) (sl)) \ ++ : "r" ((USItype) (ah)), \ ++ "rI" ((USItype) (bh)), \ ++ "r" ((USItype) (al)), \ ++ "rI" ((USItype) (bl))) ++#define umul_ppmm(xh, xl, a, b) \ ++ __asm__ ("%@ Inlined umul_ppmm\n" \ ++ "umull %r1, %r0, %r2, %r3" \ ++ : "=&r" ((USItype)(xh)), \ ++ "=r" ((USItype)(xl)) \ ++ : "r" ((USItype)(a)), \ ++ "r" ((USItype)(b)) \ ++ : "r0", "r1") ++#define count_leading_zeros(count, x) \ ++ __asm__ ("clz %0, %1" : "=r"(count) : "r"(x)) ++#define UMUL_TIME 20 ++#define UDIV_TIME 100 ++#endif /* __arm__ */ ++ ++#define __umulsidi3(u, v) \ ++ ({DIunion __w; \ ++ umul_ppmm (__w.s.high, __w.s.low, u, v); \ ++ __w.ll; }) ++ ++#define __udiv_qrnnd_c(q, r, n1, n0, d) \ ++ do { \ ++ USItype __d1, __d0, __q1, __q0; \ ++ USItype __r1, __r0, __m; \ ++ __d1 = __ll_highpart (d); \ ++ __d0 = __ll_lowpart (d); \ ++ \ ++ __r1 = (n1) % __d1; \ ++ __q1 = (n1) / __d1; \ ++ __m = (USItype) __q1 * __d0; \ ++ __r1 = __r1 * __ll_B | __ll_highpart (n0); \ ++ if (__r1 < __m) \ ++ { \ ++ __q1--, __r1 += (d); \ ++ if (__r1 >= (d)) /* i.e. we didn't get carry when adding to __r1 */\ ++ if (__r1 < __m) \ ++ __q1--, __r1 += (d); \ ++ } \ ++ __r1 -= __m; \ ++ \ ++ __r0 = __r1 % __d1; \ ++ __q0 = __r1 / __d1; \ ++ __m = (USItype) __q0 * __d0; \ ++ __r0 = __r0 * __ll_B | __ll_lowpart (n0); \ ++ if (__r0 < __m) \ ++ { \ ++ __q0--, __r0 += (d); \ ++ if (__r0 >= (d)) \ ++ if (__r0 < __m) \ ++ __q0--, __r0 += (d); \ ++ } \ ++ __r0 -= __m; \ ++ \ ++ (q) = (USItype) __q1 * __ll_B | __q0; \ ++ (r) = __r0; \ ++ } while (0) ++ ++#define UDIV_NEEDS_NORMALIZATION 1 ++#define udiv_qrnnd __udiv_qrnnd_c +Index: linux-3.2.46/arch/arm/configs/bcmrpi_cutdown_defconfig +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/arch/arm/configs/bcmrpi_cutdown_defconfig 2013-07-26 19:31:51.000000000 +0000 +@@ -0,0 +1,1558 @@ ++# ++# Automatically generated file; DO NOT EDIT. ++# Linux/arm 3.1.9 Kernel Configuration ++# ++CONFIG_ARM=y ++CONFIG_SYS_SUPPORTS_APM_EMULATION=y ++CONFIG_GENERIC_GPIO=y ++# CONFIG_ARCH_USES_GETTIMEOFFSET is not set ++CONFIG_GENERIC_CLOCKEVENTS=y ++CONFIG_KTIME_SCALAR=y ++CONFIG_HAVE_PROC_CPU=y ++CONFIG_STACKTRACE_SUPPORT=y ++CONFIG_HAVE_LATENCYTOP_SUPPORT=y ++CONFIG_LOCKDEP_SUPPORT=y ++CONFIG_TRACE_IRQFLAGS_SUPPORT=y ++CONFIG_HARDIRQS_SW_RESEND=y ++CONFIG_GENERIC_IRQ_PROBE=y ++CONFIG_RWSEM_GENERIC_SPINLOCK=y ++CONFIG_ARCH_HAS_CPU_IDLE_WAIT=y ++CONFIG_GENERIC_HWEIGHT=y ++CONFIG_GENERIC_CALIBRATE_DELAY=y ++CONFIG_NEED_DMA_MAP_STATE=y ++CONFIG_VECTORS_BASE=0xffff0000 ++# CONFIG_ARM_PATCH_PHYS_VIRT is not set ++CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" ++CONFIG_HAVE_IRQ_WORK=y ++ ++# ++# General setup ++# ++CONFIG_EXPERIMENTAL=y ++CONFIG_BROKEN_ON_SMP=y ++CONFIG_INIT_ENV_ARG_LIMIT=32 ++CONFIG_CROSS_COMPILE="" ++CONFIG_LOCALVERSION="" ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_HAVE_KERNEL_GZIP=y ++CONFIG_HAVE_KERNEL_LZMA=y ++CONFIG_HAVE_KERNEL_LZO=y ++CONFIG_KERNEL_GZIP=y ++# CONFIG_KERNEL_LZMA is not set ++# CONFIG_KERNEL_LZO is not set ++CONFIG_DEFAULT_HOSTNAME="(none)" ++CONFIG_SWAP=y ++CONFIG_SYSVIPC=y ++CONFIG_SYSVIPC_SYSCTL=y ++CONFIG_POSIX_MQUEUE=y ++CONFIG_POSIX_MQUEUE_SYSCTL=y ++# CONFIG_BSD_PROCESS_ACCT is not set ++# CONFIG_FHANDLE is not set ++# CONFIG_TASKSTATS is not set ++# CONFIG_AUDIT is not set ++CONFIG_HAVE_GENERIC_HARDIRQS=y ++ ++# ++# IRQ subsystem ++# ++CONFIG_GENERIC_HARDIRQS=y ++CONFIG_HAVE_SPARSE_IRQ=y ++CONFIG_GENERIC_IRQ_SHOW=y ++# CONFIG_SPARSE_IRQ is not set ++ ++# ++# RCU Subsystem ++# ++CONFIG_TINY_RCU=y ++# CONFIG_PREEMPT_RCU is not set ++# CONFIG_RCU_TRACE is not set ++# CONFIG_TREE_RCU_TRACE is not set ++CONFIG_IKCONFIG=y ++CONFIG_IKCONFIG_PROC=y ++CONFIG_LOG_BUF_SHIFT=17 ++# CONFIG_CGROUPS is not set ++# CONFIG_NAMESPACES is not set ++# CONFIG_SCHED_AUTOGROUP is not set ++# CONFIG_SYSFS_DEPRECATED is not set ++# CONFIG_RELAY is not set ++# CONFIG_BLK_DEV_INITRD is not set ++# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set ++CONFIG_SYSCTL=y ++CONFIG_ANON_INODES=y ++CONFIG_EXPERT=y ++# CONFIG_UID16 is not set ++CONFIG_SYSCTL_SYSCALL=y ++# CONFIG_KALLSYMS is not set ++CONFIG_HOTPLUG=y ++CONFIG_PRINTK=y ++CONFIG_BUG=y ++# CONFIG_ELF_CORE is not set ++CONFIG_BASE_FULL=y ++CONFIG_FUTEX=y ++CONFIG_EPOLL=y ++CONFIG_SIGNALFD=y ++CONFIG_TIMERFD=y ++CONFIG_EVENTFD=y ++CONFIG_SHMEM=y ++CONFIG_AIO=y ++CONFIG_EMBEDDED=y ++CONFIG_HAVE_PERF_EVENTS=y ++CONFIG_PERF_USE_VMALLOC=y ++ ++# ++# Kernel Performance Events And Counters ++# ++# CONFIG_PERF_EVENTS is not set ++# CONFIG_PERF_COUNTERS is not set ++# CONFIG_VM_EVENT_COUNTERS is not set ++# CONFIG_COMPAT_BRK is not set ++CONFIG_SLAB=y ++# CONFIG_SLUB is not set ++# CONFIG_SLOB is not set ++# CONFIG_PROFILING is not set ++CONFIG_HAVE_OPROFILE=y ++# CONFIG_KPROBES is not set ++CONFIG_HAVE_KPROBES=y ++CONFIG_HAVE_KRETPROBES=y ++CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y ++CONFIG_HAVE_CLK=y ++CONFIG_HAVE_DMA_API_DEBUG=y ++ ++# ++# GCOV-based kernel profiling ++# ++CONFIG_HAVE_GENERIC_DMA_COHERENT=y ++CONFIG_SLABINFO=y ++CONFIG_RT_MUTEXES=y ++CONFIG_BASE_SMALL=0 ++CONFIG_MODULES=y ++# CONFIG_MODULE_FORCE_LOAD is not set ++CONFIG_MODULE_UNLOAD=y ++# CONFIG_MODULE_FORCE_UNLOAD is not set ++CONFIG_MODVERSIONS=y ++CONFIG_MODULE_SRCVERSION_ALL=y ++CONFIG_BLOCK=y ++CONFIG_LBDAF=y ++# CONFIG_BLK_DEV_BSG is not set ++# CONFIG_BLK_DEV_BSGLIB is not set ++# CONFIG_BLK_DEV_INTEGRITY is not set ++ ++# ++# IO Schedulers ++# ++CONFIG_IOSCHED_NOOP=y ++CONFIG_IOSCHED_DEADLINE=y ++CONFIG_IOSCHED_CFQ=y ++# CONFIG_DEFAULT_DEADLINE is not set ++CONFIG_DEFAULT_CFQ=y ++# CONFIG_DEFAULT_NOOP is not set ++CONFIG_DEFAULT_IOSCHED="cfq" ++# CONFIG_INLINE_SPIN_TRYLOCK is not set ++# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set ++# CONFIG_INLINE_SPIN_LOCK is not set ++# CONFIG_INLINE_SPIN_LOCK_BH is not set ++# CONFIG_INLINE_SPIN_LOCK_IRQ is not set ++# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set ++CONFIG_INLINE_SPIN_UNLOCK=y ++# CONFIG_INLINE_SPIN_UNLOCK_BH is not set ++CONFIG_INLINE_SPIN_UNLOCK_IRQ=y ++# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set ++# CONFIG_INLINE_READ_TRYLOCK is not set ++# CONFIG_INLINE_READ_LOCK is not set ++# CONFIG_INLINE_READ_LOCK_BH is not set ++# CONFIG_INLINE_READ_LOCK_IRQ is not set ++# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set ++CONFIG_INLINE_READ_UNLOCK=y ++# CONFIG_INLINE_READ_UNLOCK_BH is not set ++CONFIG_INLINE_READ_UNLOCK_IRQ=y ++# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set ++# CONFIG_INLINE_WRITE_TRYLOCK is not set ++# CONFIG_INLINE_WRITE_LOCK is not set ++# CONFIG_INLINE_WRITE_LOCK_BH is not set ++# CONFIG_INLINE_WRITE_LOCK_IRQ is not set ++# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set ++CONFIG_INLINE_WRITE_UNLOCK=y ++# CONFIG_INLINE_WRITE_UNLOCK_BH is not set ++CONFIG_INLINE_WRITE_UNLOCK_IRQ=y ++# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set ++# CONFIG_MUTEX_SPIN_ON_OWNER is not set ++CONFIG_FREEZER=y ++ ++# ++# System Type ++# ++CONFIG_MMU=y ++# CONFIG_ARCH_INTEGRATOR is not set ++# CONFIG_ARCH_REALVIEW is not set ++# CONFIG_ARCH_VERSATILE is not set ++# CONFIG_ARCH_VEXPRESS is not set ++# CONFIG_ARCH_AT91 is not set ++# CONFIG_ARCH_BCMRING is not set ++# CONFIG_ARCH_CLPS711X is not set ++# CONFIG_ARCH_CNS3XXX is not set ++# CONFIG_ARCH_GEMINI is not set ++# CONFIG_ARCH_PRIMA2 is not set ++# CONFIG_ARCH_EBSA110 is not set ++# CONFIG_ARCH_EP93XX is not set ++# CONFIG_ARCH_FOOTBRIDGE is not set ++# CONFIG_ARCH_MXC is not set ++# CONFIG_ARCH_MXS is not set ++# CONFIG_ARCH_NETX is not set ++# CONFIG_ARCH_H720X is not set ++# CONFIG_ARCH_IOP13XX is not set ++# CONFIG_ARCH_IOP32X is not set ++# CONFIG_ARCH_IOP33X is not set ++# CONFIG_ARCH_IXP23XX is not set ++# CONFIG_ARCH_IXP2000 is not set ++# CONFIG_ARCH_IXP4XX is not set ++# CONFIG_ARCH_DOVE is not set ++# CONFIG_ARCH_KIRKWOOD is not set ++# CONFIG_ARCH_LPC32XX is not set ++# CONFIG_ARCH_MV78XX0 is not set ++# CONFIG_ARCH_ORION5X is not set ++# CONFIG_ARCH_MMP is not set ++# CONFIG_ARCH_KS8695 is not set ++# CONFIG_ARCH_W90X900 is not set ++# CONFIG_ARCH_NUC93X is not set ++# CONFIG_ARCH_TEGRA is not set ++# CONFIG_ARCH_PNX4008 is not set ++# CONFIG_ARCH_PXA is not set ++# CONFIG_ARCH_MSM is not set ++# CONFIG_ARCH_SHMOBILE is not set ++# CONFIG_ARCH_RPC is not set ++# CONFIG_ARCH_SA1100 is not set ++# CONFIG_ARCH_S3C2410 is not set ++# CONFIG_ARCH_S3C64XX is not set ++# CONFIG_ARCH_S5P64X0 is not set ++# CONFIG_ARCH_S5PC100 is not set ++# CONFIG_ARCH_S5PV210 is not set ++# CONFIG_ARCH_EXYNOS4 is not set ++# CONFIG_ARCH_SHARK is not set ++# CONFIG_ARCH_TCC_926 is not set ++# CONFIG_ARCH_U300 is not set ++# CONFIG_ARCH_U8500 is not set ++# CONFIG_ARCH_NOMADIK is not set ++# CONFIG_ARCH_DAVINCI is not set ++# CONFIG_ARCH_OMAP is not set ++# CONFIG_PLAT_SPEAR is not set ++CONFIG_ARCH_BCM2708=y ++# CONFIG_ARCH_VT8500 is not set ++# CONFIG_ARCH_ZYNQ is not set ++ ++# ++# System MMU ++# ++ ++# ++# Broadcom BCM2708 Implementations ++# ++CONFIG_MACH_BCM2708=y ++CONFIG_BCM2708_GPIO=y ++CONFIG_BCM2708_VCMEM=y ++ ++# ++# Processor Type ++# ++CONFIG_CPU_V6=y ++CONFIG_CPU_32v6=y ++CONFIG_CPU_ABRT_EV6=y ++CONFIG_CPU_PABRT_V6=y ++CONFIG_CPU_CACHE_V6=y ++CONFIG_CPU_CACHE_VIPT=y ++CONFIG_CPU_COPY_V6=y ++CONFIG_CPU_TLB_V6=y ++CONFIG_CPU_HAS_ASID=y ++CONFIG_CPU_CP15=y ++CONFIG_CPU_CP15_MMU=y ++CONFIG_CPU_USE_DOMAINS=y ++ ++# ++# Processor Features ++# ++CONFIG_ARM_THUMB=y ++# CONFIG_CPU_ICACHE_DISABLE is not set ++# CONFIG_CPU_DCACHE_DISABLE is not set ++# CONFIG_CPU_BPREDICT_DISABLE is not set ++CONFIG_ARM_L1_CACHE_SHIFT=5 ++CONFIG_ARM_DMA_MEM_BUFFERABLE=y ++CONFIG_CPU_HAS_PMU=y ++CONFIG_ARM_ERRATA_411920=y ++# CONFIG_ARM_ERRATA_364296 is not set ++ ++# ++# Bus support ++# ++CONFIG_ARM_AMBA=y ++# CONFIG_PCI_SYSCALL is not set ++# CONFIG_ARCH_SUPPORTS_MSI is not set ++# CONFIG_PCCARD is not set ++ ++# ++# Kernel Features ++# ++CONFIG_TICK_ONESHOT=y ++CONFIG_NO_HZ=y ++# CONFIG_HIGH_RES_TIMERS is not set ++CONFIG_GENERIC_CLOCKEVENTS_BUILD=y ++CONFIG_VMSPLIT_3G=y ++# CONFIG_VMSPLIT_2G is not set ++# CONFIG_VMSPLIT_1G is not set ++CONFIG_PAGE_OFFSET=0xC0000000 ++CONFIG_PREEMPT_NONE=y ++# CONFIG_PREEMPT_VOLUNTARY is not set ++# CONFIG_PREEMPT is not set ++CONFIG_HZ=100 ++CONFIG_AEABI=y ++CONFIG_OABI_COMPAT=y ++# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set ++# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set ++CONFIG_HAVE_ARCH_PFN_VALID=y ++# CONFIG_HIGHMEM is not set ++CONFIG_SELECT_MEMORY_MODEL=y ++CONFIG_FLATMEM_MANUAL=y ++CONFIG_FLATMEM=y ++CONFIG_FLAT_NODE_MEM_MAP=y ++CONFIG_HAVE_MEMBLOCK=y ++CONFIG_PAGEFLAGS_EXTENDED=y ++CONFIG_SPLIT_PTLOCK_CPUS=4 ++# CONFIG_COMPACTION is not set ++# CONFIG_PHYS_ADDR_T_64BIT is not set ++CONFIG_ZONE_DMA_FLAG=0 ++CONFIG_VIRT_TO_BUS=y ++# CONFIG_KSM is not set ++CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 ++CONFIG_NEED_PER_CPU_KM=y ++# CONFIG_CLEANCACHE is not set ++CONFIG_FORCE_MAX_ZONEORDER=11 ++CONFIG_ALIGNMENT_TRAP=y ++# CONFIG_UACCESS_WITH_MEMCPY is not set ++# CONFIG_SECCOMP is not set ++# CONFIG_CC_STACKPROTECTOR is not set ++# CONFIG_DEPRECATED_PARAM_STRUCT is not set ++ ++# ++# Boot options ++# ++# CONFIG_USE_OF is not set ++CONFIG_ZBOOT_ROM_TEXT=0x0 ++CONFIG_ZBOOT_ROM_BSS=0x0 ++CONFIG_CMDLINE="dwc_otg.lpm_enable=0 console=ttyAMA0,115200 kgdboc=ttyAMA0,115200 root=/dev/mmcblk0p2 rootfstype=ext3 rootwait" ++CONFIG_CMDLINE_FROM_BOOTLOADER=y ++# CONFIG_CMDLINE_EXTEND is not set ++# CONFIG_CMDLINE_FORCE is not set ++# CONFIG_XIP_KERNEL is not set ++# CONFIG_KEXEC is not set ++# CONFIG_CRASH_DUMP is not set ++# CONFIG_AUTO_ZRELADDR is not set ++ ++# ++# CPU Power Management ++# ++CONFIG_CPU_IDLE=y ++CONFIG_CPU_IDLE_GOV_LADDER=y ++CONFIG_CPU_IDLE_GOV_MENU=y ++ ++# ++# Floating point emulation ++# ++ ++# ++# At least one emulation must be selected ++# ++# CONFIG_FPE_NWFPE is not set ++# CONFIG_FPE_FASTFPE is not set ++CONFIG_VFP=y ++ ++# ++# Userspace binary formats ++# ++CONFIG_BINFMT_ELF=y ++CONFIG_HAVE_AOUT=y ++# CONFIG_BINFMT_AOUT is not set ++# CONFIG_BINFMT_MISC is not set ++ ++# ++# Power management options ++# ++CONFIG_SUSPEND=y ++CONFIG_SUSPEND_FREEZER=y ++CONFIG_PM_SLEEP=y ++# CONFIG_PM_RUNTIME is not set ++CONFIG_PM=y ++# CONFIG_PM_DEBUG is not set ++# CONFIG_APM_EMULATION is not set ++CONFIG_PM_CLK=y ++CONFIG_ARCH_SUSPEND_POSSIBLE=y ++CONFIG_NET=y ++ ++# ++# Networking options ++# ++CONFIG_PACKET=y ++CONFIG_UNIX=y ++CONFIG_XFRM=y ++CONFIG_XFRM_USER=y ++# CONFIG_XFRM_SUB_POLICY is not set ++# CONFIG_XFRM_MIGRATE is not set ++# CONFIG_XFRM_STATISTICS is not set ++CONFIG_NET_KEY=m ++# CONFIG_NET_KEY_MIGRATE is not set ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++# CONFIG_IP_ADVANCED_ROUTER is not set ++CONFIG_IP_PNP=y ++CONFIG_IP_PNP_DHCP=y ++# CONFIG_IP_PNP_BOOTP is not set ++CONFIG_IP_PNP_RARP=y ++# CONFIG_NET_IPIP is not set ++# CONFIG_NET_IPGRE_DEMUX is not set ++# CONFIG_IP_MROUTE is not set ++# CONFIG_ARPD is not set ++CONFIG_SYN_COOKIES=y ++# CONFIG_INET_AH is not set ++# CONFIG_INET_ESP is not set ++# CONFIG_INET_IPCOMP is not set ++# CONFIG_INET_XFRM_TUNNEL is not set ++# CONFIG_INET_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_LRO is not set ++# CONFIG_INET_DIAG is not set ++# CONFIG_TCP_CONG_ADVANCED is not set ++CONFIG_TCP_CONG_CUBIC=y ++CONFIG_DEFAULT_TCP_CONG="cubic" ++# CONFIG_TCP_MD5SIG is not set ++# CONFIG_IPV6 is not set ++# CONFIG_NETWORK_SECMARK is not set ++# CONFIG_NETWORK_PHY_TIMESTAMPING is not set ++# CONFIG_NETFILTER is not set ++# CONFIG_IP_DCCP is not set ++# CONFIG_IP_SCTP is not set ++# CONFIG_RDS is not set ++# CONFIG_TIPC is not set ++# CONFIG_ATM is not set ++# CONFIG_L2TP is not set ++# CONFIG_BRIDGE is not set ++# CONFIG_NET_DSA is not set ++# CONFIG_VLAN_8021Q is not set ++# CONFIG_DECNET is not set ++# CONFIG_LLC2 is not set ++# CONFIG_IPX is not set ++# CONFIG_ATALK is not set ++# CONFIG_X25 is not set ++# CONFIG_LAPB is not set ++# CONFIG_ECONET is not set ++# CONFIG_WAN_ROUTER is not set ++# CONFIG_PHONET is not set ++# CONFIG_IEEE802154 is not set ++# CONFIG_NET_SCHED is not set ++# CONFIG_DCB is not set ++CONFIG_DNS_RESOLVER=y ++# CONFIG_BATMAN_ADV is not set ++ ++# ++# Network testing ++# ++CONFIG_NET_PKTGEN=m ++# CONFIG_HAMRADIO is not set ++# CONFIG_CAN is not set ++# CONFIG_IRDA is not set ++# CONFIG_BT is not set ++# CONFIG_AF_RXRPC is not set ++CONFIG_WIRELESS=y ++CONFIG_WEXT_CORE=y ++CONFIG_WEXT_PROC=y ++CONFIG_CFG80211=y ++# CONFIG_NL80211_TESTMODE is not set ++# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set ++# CONFIG_CFG80211_REG_DEBUG is not set ++CONFIG_CFG80211_DEFAULT_PS=y ++# CONFIG_CFG80211_INTERNAL_REGDB is not set ++CONFIG_CFG80211_WEXT=y ++CONFIG_WIRELESS_EXT_SYSFS=y ++# CONFIG_LIB80211 is not set ++# CONFIG_MAC80211 is not set ++# CONFIG_WIMAX is not set ++# CONFIG_RFKILL is not set ++# CONFIG_NET_9P is not set ++# CONFIG_CAIF is not set ++# CONFIG_CEPH_LIB is not set ++# CONFIG_NFC is not set ++ ++# ++# Device Drivers ++# ++ ++# ++# Generic Driver Options ++# ++CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" ++# CONFIG_DEVTMPFS is not set ++CONFIG_STANDALONE=y ++CONFIG_PREVENT_FIRMWARE_BUILD=y ++CONFIG_FW_LOADER=y ++CONFIG_FIRMWARE_IN_KERNEL=y ++CONFIG_EXTRA_FIRMWARE="" ++# CONFIG_DEBUG_DRIVER is not set ++# CONFIG_DEBUG_DEVRES is not set ++# CONFIG_SYS_HYPERVISOR is not set ++# CONFIG_CONNECTOR is not set ++# CONFIG_MTD is not set ++# CONFIG_PARPORT is not set ++CONFIG_BLK_DEV=y ++# CONFIG_BLK_DEV_COW_COMMON is not set ++CONFIG_BLK_DEV_LOOP=y ++CONFIG_BLK_DEV_LOOP_MIN_COUNT=8 ++# CONFIG_BLK_DEV_CRYPTOLOOP is not set ++ ++# ++# DRBD disabled because PROC_FS, INET or CONNECTOR not selected ++# ++# CONFIG_BLK_DEV_NBD is not set ++# CONFIG_BLK_DEV_UB is not set ++CONFIG_BLK_DEV_RAM=y ++CONFIG_BLK_DEV_RAM_COUNT=16 ++CONFIG_BLK_DEV_RAM_SIZE=4096 ++# CONFIG_BLK_DEV_XIP is not set ++# CONFIG_CDROM_PKTCDVD is not set ++# CONFIG_ATA_OVER_ETH is not set ++# CONFIG_MG_DISK is not set ++# CONFIG_BLK_DEV_RBD is not set ++# CONFIG_SENSORS_LIS3LV02D is not set ++CONFIG_MISC_DEVICES=y ++# CONFIG_ENCLOSURE_SERVICES is not set ++# CONFIG_C2PORT is not set ++ ++# ++# EEPROM support ++# ++# CONFIG_EEPROM_93CX6 is not set ++# CONFIG_IWMC3200TOP is not set ++ ++# ++# Texas Instruments shared transport line discipline ++# ++# CONFIG_TI_ST is not set ++CONFIG_BCM2708_VCHIQ=y ++CONFIG_HAVE_IDE=y ++# CONFIG_IDE is not set ++ ++# ++# SCSI device support ++# ++CONFIG_SCSI_MOD=y ++# CONFIG_RAID_ATTRS is not set ++CONFIG_SCSI=y ++CONFIG_SCSI_DMA=y ++# CONFIG_SCSI_TGT is not set ++# CONFIG_SCSI_NETLINK is not set ++# CONFIG_SCSI_PROC_FS is not set ++ ++# ++# SCSI support type (disk, tape, CD-ROM) ++# ++CONFIG_BLK_DEV_SD=m ++# CONFIG_CHR_DEV_ST is not set ++# CONFIG_CHR_DEV_OSST is not set ++CONFIG_BLK_DEV_SR=m ++# CONFIG_BLK_DEV_SR_VENDOR is not set ++# CONFIG_CHR_DEV_SG is not set ++# CONFIG_CHR_DEV_SCH is not set ++CONFIG_SCSI_MULTI_LUN=y ++# CONFIG_SCSI_CONSTANTS is not set ++# CONFIG_SCSI_LOGGING is not set ++# CONFIG_SCSI_SCAN_ASYNC is not set ++CONFIG_SCSI_WAIT_SCAN=m ++ ++# ++# SCSI Transports ++# ++# CONFIG_SCSI_SPI_ATTRS is not set ++# CONFIG_SCSI_FC_ATTRS is not set ++# CONFIG_SCSI_ISCSI_ATTRS is not set ++# CONFIG_SCSI_SAS_ATTRS is not set ++# CONFIG_SCSI_SAS_LIBSAS is not set ++# CONFIG_SCSI_SRP_ATTRS is not set ++# CONFIG_SCSI_LOWLEVEL is not set ++# CONFIG_SCSI_DH is not set ++# CONFIG_SCSI_OSD_INITIATOR is not set ++# CONFIG_ATA is not set ++# CONFIG_MD is not set ++# CONFIG_TARGET_CORE is not set ++CONFIG_NETDEVICES=y ++# CONFIG_DUMMY is not set ++# CONFIG_BONDING is not set ++# CONFIG_MACVLAN is not set ++# CONFIG_EQUALIZER is not set ++CONFIG_TUN=m ++# CONFIG_VETH is not set ++CONFIG_MII=y ++CONFIG_PHYLIB=m ++ ++# ++# MII PHY device drivers ++# ++# CONFIG_MARVELL_PHY is not set ++# CONFIG_DAVICOM_PHY is not set ++# CONFIG_QSEMI_PHY is not set ++# CONFIG_LXT_PHY is not set ++# CONFIG_CICADA_PHY is not set ++# CONFIG_VITESSE_PHY is not set ++# CONFIG_SMSC_PHY is not set ++# CONFIG_BROADCOM_PHY is not set ++# CONFIG_ICPLUS_PHY is not set ++# CONFIG_REALTEK_PHY is not set ++# CONFIG_NATIONAL_PHY is not set ++# CONFIG_STE10XP is not set ++# CONFIG_LSI_ET1011C_PHY is not set ++# CONFIG_MICREL_PHY is not set ++CONFIG_MDIO_BITBANG=m ++# CONFIG_MDIO_GPIO is not set ++CONFIG_NET_ETHERNET=y ++CONFIG_AX88796=m ++# CONFIG_AX88796_93CX6 is not set ++# CONFIG_SMC91X is not set ++# CONFIG_DM9000 is not set ++# CONFIG_ETHOC is not set ++# CONFIG_SMC911X is not set ++# CONFIG_SMSC911X is not set ++# CONFIG_DNET is not set ++# CONFIG_IBM_NEW_EMAC_ZMII is not set ++# CONFIG_IBM_NEW_EMAC_RGMII is not set ++# CONFIG_IBM_NEW_EMAC_TAH is not set ++# CONFIG_IBM_NEW_EMAC_EMAC4 is not set ++# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set ++# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set ++# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set ++# CONFIG_B44 is not set ++# CONFIG_KS8851_MLL is not set ++# CONFIG_FTMAC100 is not set ++# CONFIG_NETDEV_1000 is not set ++# CONFIG_NETDEV_10000 is not set ++# CONFIG_WLAN is not set ++ ++# ++# Enable WiMAX (Networking options) to see the WiMAX drivers ++# ++ ++# ++# USB Network Adapters ++# ++# CONFIG_USB_CATC is not set ++# CONFIG_USB_KAWETH is not set ++# CONFIG_USB_PEGASUS is not set ++# CONFIG_USB_RTL8150 is not set ++CONFIG_USB_USBNET=y ++CONFIG_USB_NET_AX8817X=m ++# CONFIG_USB_NET_CDCETHER is not set ++# CONFIG_USB_NET_CDC_EEM is not set ++CONFIG_USB_NET_CDC_NCM=y ++# CONFIG_USB_NET_DM9601 is not set ++# CONFIG_USB_NET_SMSC75XX is not set ++CONFIG_USB_NET_SMSC95XX=y ++# CONFIG_USB_NET_GL620A is not set ++# CONFIG_USB_NET_NET1080 is not set ++# CONFIG_USB_NET_PLUSB is not set ++# CONFIG_USB_NET_MCS7830 is not set ++# CONFIG_USB_NET_RNDIS_HOST is not set ++# CONFIG_USB_NET_CDC_SUBSET is not set ++# CONFIG_USB_NET_ZAURUS is not set ++# CONFIG_USB_NET_CX82310_ETH is not set ++# CONFIG_USB_NET_KALMIA is not set ++# CONFIG_USB_NET_INT51X1 is not set ++# CONFIG_USB_IPHETH is not set ++# CONFIG_USB_SIERRA_NET is not set ++# CONFIG_WAN is not set ++ ++# ++# CAIF transport drivers ++# ++# CONFIG_PPP is not set ++# CONFIG_SLIP is not set ++# CONFIG_NETCONSOLE is not set ++# CONFIG_NETPOLL is not set ++# CONFIG_NET_POLL_CONTROLLER is not set ++# CONFIG_ISDN is not set ++# CONFIG_PHONE is not set ++ ++# ++# Input device support ++# ++CONFIG_INPUT=y ++# CONFIG_INPUT_FF_MEMLESS is not set ++# CONFIG_INPUT_POLLDEV is not set ++# CONFIG_INPUT_SPARSEKMAP is not set ++ ++# ++# Userland interfaces ++# ++CONFIG_INPUT_MOUSEDEV=y ++# CONFIG_INPUT_MOUSEDEV_PSAUX is not set ++CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 ++CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 ++# CONFIG_INPUT_JOYDEV is not set ++CONFIG_INPUT_EVDEV=m ++# CONFIG_INPUT_EVBUG is not set ++ ++# ++# Input Device Drivers ++# ++# CONFIG_INPUT_KEYBOARD is not set ++# CONFIG_INPUT_MOUSE is not set ++# CONFIG_INPUT_JOYSTICK is not set ++# CONFIG_INPUT_TABLET is not set ++# CONFIG_INPUT_TOUCHSCREEN is not set ++CONFIG_INPUT_MISC=y ++# CONFIG_INPUT_AD714X is not set ++# CONFIG_INPUT_ATI_REMOTE is not set ++# CONFIG_INPUT_ATI_REMOTE2 is not set ++# CONFIG_INPUT_KEYSPAN_REMOTE is not set ++# CONFIG_INPUT_POWERMATE is not set ++# CONFIG_INPUT_YEALINK is not set ++# CONFIG_INPUT_CM109 is not set ++CONFIG_INPUT_UINPUT=m ++# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set ++# CONFIG_INPUT_ADXL34X is not set ++# CONFIG_INPUT_CMA3000 is not set ++ ++# ++# Hardware I/O ports ++# ++CONFIG_SERIO=m ++CONFIG_SERIO_SERPORT=m ++# CONFIG_SERIO_AMBAKMI is not set ++# CONFIG_SERIO_LIBPS2 is not set ++CONFIG_SERIO_RAW=m ++# CONFIG_SERIO_ALTERA_PS2 is not set ++# CONFIG_SERIO_PS2MULT is not set ++CONFIG_GAMEPORT=m ++CONFIG_GAMEPORT_NS558=m ++CONFIG_GAMEPORT_L4=m ++ ++# ++# Character devices ++# ++CONFIG_VT=y ++CONFIG_CONSOLE_TRANSLATIONS=y ++CONFIG_VT_CONSOLE=y ++CONFIG_HW_CONSOLE=y ++CONFIG_VT_HW_CONSOLE_BINDING=y ++CONFIG_UNIX98_PTYS=y ++# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_SERIAL_NONSTANDARD is not set ++# CONFIG_N_GSM is not set ++# CONFIG_TRACE_SINK is not set ++# CONFIG_DEVKMEM is not set ++ ++# ++# Serial drivers ++# ++# CONFIG_SERIAL_8250 is not set ++ ++# ++# Non-8250 serial port support ++# ++# CONFIG_SERIAL_AMBA_PL010 is not set ++CONFIG_SERIAL_AMBA_PL011=y ++CONFIG_SERIAL_AMBA_PL011_CONSOLE=y ++CONFIG_SERIAL_CORE=y ++CONFIG_SERIAL_CORE_CONSOLE=y ++# CONFIG_SERIAL_TIMBERDALE is not set ++# CONFIG_SERIAL_ALTERA_JTAGUART is not set ++# CONFIG_SERIAL_ALTERA_UART is not set ++# CONFIG_SERIAL_XILINX_PS_UART is not set ++# CONFIG_TTY_PRINTK is not set ++# CONFIG_HVC_DCC is not set ++# CONFIG_IPMI_HANDLER is not set ++# CONFIG_HW_RANDOM is not set ++# CONFIG_R3964 is not set ++CONFIG_RAW_DRIVER=y ++CONFIG_MAX_RAW_DEVS=256 ++# CONFIG_TCG_TPM is not set ++# CONFIG_RAMOOPS is not set ++# CONFIG_I2C is not set ++# CONFIG_SPI is not set ++ ++# ++# PPS support ++# ++# CONFIG_PPS is not set ++ ++# ++# PPS generators support ++# ++ ++# ++# PTP clock support ++# ++ ++# ++# Enable Device Drivers -> PPS to see the PTP clock options. ++# ++CONFIG_ARCH_REQUIRE_GPIOLIB=y ++CONFIG_GPIOLIB=y ++# CONFIG_DEBUG_GPIO is not set ++CONFIG_GPIO_SYSFS=y ++ ++# ++# Memory mapped GPIO drivers: ++# ++# CONFIG_GPIO_GENERIC_PLATFORM is not set ++# CONFIG_GPIO_IT8761E is not set ++# CONFIG_GPIO_PL061 is not set ++ ++# ++# I2C GPIO expanders: ++# ++ ++# ++# PCI GPIO expanders: ++# ++ ++# ++# SPI GPIO expanders: ++# ++ ++# ++# AC97 GPIO expanders: ++# ++ ++# ++# MODULbus GPIO expanders: ++# ++# CONFIG_W1 is not set ++# CONFIG_POWER_SUPPLY is not set ++# CONFIG_HWMON is not set ++# CONFIG_THERMAL is not set ++# CONFIG_WATCHDOG is not set ++CONFIG_SSB_POSSIBLE=y ++ ++# ++# Sonics Silicon Backplane ++# ++# CONFIG_SSB is not set ++CONFIG_BCMA_POSSIBLE=y ++ ++# ++# Broadcom specific AMBA ++# ++# CONFIG_BCMA is not set ++# CONFIG_MFD_SUPPORT is not set ++# CONFIG_REGULATOR is not set ++# CONFIG_MEDIA_SUPPORT is not set ++ ++# ++# Graphics support ++# ++# CONFIG_DRM is not set ++# CONFIG_VGASTATE is not set ++# CONFIG_VIDEO_OUTPUT_CONTROL is not set ++CONFIG_FB=y ++# CONFIG_FIRMWARE_EDID is not set ++# CONFIG_FB_DDC is not set ++# CONFIG_FB_BOOT_VESA_SUPPORT is not set ++CONFIG_FB_CFB_FILLRECT=y ++CONFIG_FB_CFB_COPYAREA=y ++CONFIG_FB_CFB_IMAGEBLIT=y ++# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set ++# CONFIG_FB_SYS_FILLRECT is not set ++# CONFIG_FB_SYS_COPYAREA is not set ++# CONFIG_FB_SYS_IMAGEBLIT is not set ++# CONFIG_FB_FOREIGN_ENDIAN is not set ++# CONFIG_FB_SYS_FOPS is not set ++# CONFIG_FB_WMT_GE_ROPS is not set ++# CONFIG_FB_SVGALIB is not set ++# CONFIG_FB_MACMODES is not set ++# CONFIG_FB_BACKLIGHT is not set ++# CONFIG_FB_MODE_HELPERS is not set ++# CONFIG_FB_TILEBLITTING is not set ++ ++# ++# Frame buffer hardware drivers ++# ++CONFIG_FB_BCM2708=y ++# CONFIG_FB_ARMCLCD is not set ++# CONFIG_FB_S1D13XXX is not set ++# CONFIG_FB_UDL is not set ++# CONFIG_FB_VIRTUAL is not set ++# CONFIG_FB_METRONOME is not set ++# CONFIG_FB_BROADSHEET is not set ++# CONFIG_BACKLIGHT_LCD_SUPPORT is not set ++ ++# ++# Display device support ++# ++# CONFIG_DISPLAY_SUPPORT is not set ++ ++# ++# Console display driver support ++# ++CONFIG_DUMMY_CONSOLE=y ++CONFIG_FRAMEBUFFER_CONSOLE=y ++# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set ++# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set ++# CONFIG_FONTS is not set ++CONFIG_FONT_8x8=y ++CONFIG_FONT_8x16=y ++CONFIG_LOGO=y ++# CONFIG_LOGO_LINUX_MONO is not set ++# CONFIG_LOGO_LINUX_VGA16 is not set ++CONFIG_LOGO_LINUX_CLUT224=y ++# CONFIG_SOUND is not set ++CONFIG_HID_SUPPORT=y ++CONFIG_HID=y ++# CONFIG_HIDRAW is not set ++ ++# ++# USB Input Devices ++# ++CONFIG_USB_HID=y ++CONFIG_HID_PID=y ++CONFIG_USB_HIDDEV=y ++ ++# ++# Special HID drivers ++# ++CONFIG_HID_A4TECH=m ++# CONFIG_HID_ACRUX is not set ++CONFIG_HID_APPLE=m ++CONFIG_HID_BELKIN=m ++CONFIG_HID_CHERRY=m ++CONFIG_HID_CHICONY=m ++CONFIG_HID_CYPRESS=m ++CONFIG_HID_DRAGONRISE=m ++# CONFIG_DRAGONRISE_FF is not set ++# CONFIG_HID_EMS_FF is not set ++CONFIG_HID_EZKEY=m ++# CONFIG_HID_HOLTEK is not set ++# CONFIG_HID_KEYTOUCH is not set ++CONFIG_HID_KYE=m ++# CONFIG_HID_UCLOGIC is not set ++# CONFIG_HID_WALTOP is not set ++CONFIG_HID_GYRATION=m ++CONFIG_HID_TWINHAN=m ++CONFIG_HID_KENSINGTON=m ++# CONFIG_HID_LCPOWER is not set ++CONFIG_HID_LOGITECH=m ++# CONFIG_LOGITECH_FF is not set ++# CONFIG_LOGIRUMBLEPAD2_FF is not set ++# CONFIG_LOGIG940_FF is not set ++# CONFIG_LOGIWII_FF is not set ++CONFIG_HID_MICROSOFT=m ++CONFIG_HID_MONTEREY=m ++# CONFIG_HID_MULTITOUCH is not set ++# CONFIG_HID_NTRIG is not set ++CONFIG_HID_ORTEK=m ++CONFIG_HID_PANTHERLORD=m ++# CONFIG_PANTHERLORD_FF is not set ++CONFIG_HID_PETALYNX=m ++# CONFIG_HID_PICOLCD is not set ++# CONFIG_HID_QUANTA is not set ++# CONFIG_HID_ROCCAT is not set ++CONFIG_HID_SAMSUNG=m ++CONFIG_HID_SONY=m ++# CONFIG_HID_SPEEDLINK is not set ++CONFIG_HID_SUNPLUS=m ++CONFIG_HID_GREENASIA=m ++# CONFIG_GREENASIA_FF is not set ++CONFIG_HID_SMARTJOYPLUS=m ++# CONFIG_SMARTJOYPLUS_FF is not set ++CONFIG_HID_TOPSEED=m ++CONFIG_HID_THRUSTMASTER=m ++# CONFIG_THRUSTMASTER_FF is not set ++CONFIG_HID_ZEROPLUS=m ++# CONFIG_ZEROPLUS_FF is not set ++# CONFIG_HID_ZYDACRON is not set ++CONFIG_USB_SUPPORT=y ++CONFIG_USB_ARCH_HAS_HCD=y ++# CONFIG_USB_ARCH_HAS_OHCI is not set ++# CONFIG_USB_ARCH_HAS_EHCI is not set ++CONFIG_USB=y ++# CONFIG_USB_DEBUG is not set ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++ ++# ++# Miscellaneous USB options ++# ++# CONFIG_USB_DEVICEFS is not set ++CONFIG_USB_DEVICE_CLASS=y ++# CONFIG_USB_DYNAMIC_MINORS is not set ++# CONFIG_USB_OTG_WHITELIST is not set ++# CONFIG_USB_OTG_BLACKLIST_HUB is not set ++CONFIG_USB_MON=m ++# CONFIG_USB_WUSB is not set ++# CONFIG_USB_WUSB_CBAF is not set ++ ++# ++# USB Host Controller Drivers ++# ++# CONFIG_USB_C67X00_HCD is not set ++# CONFIG_USB_OXU210HP_HCD is not set ++# CONFIG_USB_ISP116X_HCD is not set ++# CONFIG_USB_ISP1760_HCD is not set ++# CONFIG_USB_ISP1362_HCD is not set ++# CONFIG_USB_SL811_HCD is not set ++# CONFIG_USB_R8A66597_HCD is not set ++# CONFIG_USB_HWA_HCD is not set ++CONFIG_USB_DWCOTG=y ++ ++# ++# USB Device Class drivers ++# ++# CONFIG_USB_ACM is not set ++# CONFIG_USB_PRINTER is not set ++# CONFIG_USB_WDM is not set ++# CONFIG_USB_TMC is not set ++ ++# ++# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may ++# ++ ++# ++# also be needed; see USB_STORAGE Help for more info ++# ++CONFIG_USB_STORAGE=y ++# CONFIG_USB_STORAGE_DEBUG is not set ++# CONFIG_USB_STORAGE_REALTEK is not set ++# CONFIG_USB_STORAGE_DATAFAB is not set ++# CONFIG_USB_STORAGE_FREECOM is not set ++# CONFIG_USB_STORAGE_ISD200 is not set ++# CONFIG_USB_STORAGE_USBAT is not set ++# CONFIG_USB_STORAGE_SDDR09 is not set ++# CONFIG_USB_STORAGE_SDDR55 is not set ++# CONFIG_USB_STORAGE_JUMPSHOT is not set ++# CONFIG_USB_STORAGE_ALAUDA is not set ++# CONFIG_USB_STORAGE_ONETOUCH is not set ++# CONFIG_USB_STORAGE_KARMA is not set ++# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set ++# CONFIG_USB_STORAGE_ENE_UB6250 is not set ++# CONFIG_USB_UAS is not set ++CONFIG_USB_LIBUSUAL=y ++ ++# ++# USB Imaging devices ++# ++# CONFIG_USB_MDC800 is not set ++# CONFIG_USB_MICROTEK is not set ++ ++# ++# USB port drivers ++# ++# CONFIG_USB_SERIAL is not set ++ ++# ++# USB Miscellaneous drivers ++# ++# CONFIG_USB_EMI62 is not set ++# CONFIG_USB_EMI26 is not set ++# CONFIG_USB_ADUTUX is not set ++# CONFIG_USB_SEVSEG is not set ++# CONFIG_USB_RIO500 is not set ++# CONFIG_USB_LEGOTOWER is not set ++# CONFIG_USB_LCD is not set ++# CONFIG_USB_LED is not set ++# CONFIG_USB_CYPRESS_CY7C63 is not set ++# CONFIG_USB_CYTHERM is not set ++# CONFIG_USB_IDMOUSE is not set ++# CONFIG_USB_FTDI_ELAN is not set ++# CONFIG_USB_APPLEDISPLAY is not set ++# CONFIG_USB_LD is not set ++# CONFIG_USB_TRANCEVIBRATOR is not set ++# CONFIG_USB_IOWARRIOR is not set ++# CONFIG_USB_TEST is not set ++# CONFIG_USB_ISIGHTFW is not set ++# CONFIG_USB_YUREX is not set ++# CONFIG_USB_GADGET is not set ++ ++# ++# OTG and related infrastructure ++# ++# CONFIG_USB_GPIO_VBUS is not set ++# CONFIG_USB_ULPI is not set ++# CONFIG_NOP_USB_XCEIV is not set ++CONFIG_MMC=y ++# CONFIG_MMC_DEBUG is not set ++# CONFIG_MMC_UNSAFE_RESUME is not set ++# CONFIG_MMC_CLKGATE is not set ++ ++# ++# MMC/SD/SDIO Card Drivers ++# ++CONFIG_MMC_BLOCK=y ++CONFIG_MMC_BLOCK_MINORS=8 ++CONFIG_MMC_BLOCK_BOUNCE=y ++# CONFIG_SDIO_UART is not set ++# CONFIG_MMC_TEST is not set ++ ++# ++# MMC/SD/SDIO Host Controller Drivers ++# ++# CONFIG_MMC_ARMMMCI is not set ++CONFIG_MMC_SDHCI=y ++CONFIG_MMC_SDHCI_IO_ACCESSORS=y ++CONFIG_MMC_SDHCI_PLTFM=y ++# CONFIG_MMC_SDHCI_PXAV3 is not set ++# CONFIG_MMC_SDHCI_PXAV2 is not set ++CONFIG_MMC_SDHCI_BCM2708=y ++CONFIG_MMC_SDHCI_BCM2708_DMA=y ++# CONFIG_MMC_BCM2708 is not set ++# CONFIG_MMC_DW is not set ++# CONFIG_MMC_VUB300 is not set ++# CONFIG_MMC_USHC is not set ++# CONFIG_MEMSTICK is not set ++CONFIG_NEW_LEDS=y ++CONFIG_LEDS_CLASS=y ++ ++# ++# LED drivers ++# ++CONFIG_LEDS_GPIO=y ++# CONFIG_LEDS_LT3593 is not set ++CONFIG_LEDS_TRIGGERS=y ++ ++# ++# LED Triggers ++# ++CONFIG_LEDS_TRIGGER_TIMER=m ++CONFIG_LEDS_TRIGGER_HEARTBEAT=m ++# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set ++# CONFIG_LEDS_TRIGGER_GPIO is not set ++CONFIG_LEDS_TRIGGER_DEFAULT_ON=m ++ ++# ++# iptables trigger is under Netfilter config (LED target) ++# ++# CONFIG_ACCESSIBILITY is not set ++CONFIG_RTC_LIB=y ++# CONFIG_RTC_CLASS is not set ++# CONFIG_DMADEVICES is not set ++# CONFIG_AUXDISPLAY is not set ++# CONFIG_UIO is not set ++ ++# ++# Virtio drivers ++# ++# CONFIG_VIRTIO_BALLOON is not set ++# CONFIG_STAGING is not set ++CONFIG_CLKDEV_LOOKUP=y ++# CONFIG_IOMMU_SUPPORT is not set ++# CONFIG_VIRT_DRIVERS is not set ++ ++# ++# File systems ++# ++CONFIG_EXT2_FS=m ++CONFIG_EXT2_FS_XATTR=y ++CONFIG_EXT2_FS_POSIX_ACL=y ++CONFIG_EXT2_FS_SECURITY=y ++CONFIG_EXT2_FS_XIP=y ++CONFIG_EXT3_FS=y ++# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set ++CONFIG_EXT3_FS_XATTR=y ++CONFIG_EXT3_FS_POSIX_ACL=y ++CONFIG_EXT3_FS_SECURITY=y ++CONFIG_EXT4_FS=m ++CONFIG_EXT4_FS_XATTR=y ++CONFIG_EXT4_FS_POSIX_ACL=y ++CONFIG_EXT4_FS_SECURITY=y ++# CONFIG_EXT4_DEBUG is not set ++CONFIG_FS_XIP=y ++CONFIG_JBD=y ++CONFIG_JBD2=m ++CONFIG_FS_MBCACHE=y ++# CONFIG_REISERFS_FS is not set ++# CONFIG_JFS_FS is not set ++# CONFIG_XFS_FS is not set ++# CONFIG_GFS2_FS is not set ++# CONFIG_OCFS2_FS is not set ++# CONFIG_BTRFS_FS is not set ++# CONFIG_NILFS2_FS is not set ++CONFIG_FS_POSIX_ACL=y ++CONFIG_FILE_LOCKING=y ++CONFIG_FSNOTIFY=y ++CONFIG_DNOTIFY=y ++CONFIG_INOTIFY_USER=y ++# CONFIG_FANOTIFY is not set ++# CONFIG_QUOTA is not set ++# CONFIG_QUOTACTL is not set ++CONFIG_AUTOFS4_FS=y ++CONFIG_FUSE_FS=m ++CONFIG_CUSE=m ++ ++# ++# Caches ++# ++CONFIG_FSCACHE=y ++# CONFIG_FSCACHE_STATS is not set ++# CONFIG_FSCACHE_HISTOGRAM is not set ++# CONFIG_FSCACHE_DEBUG is not set ++# CONFIG_FSCACHE_OBJECT_LIST is not set ++CONFIG_CACHEFILES=y ++# CONFIG_CACHEFILES_DEBUG is not set ++# CONFIG_CACHEFILES_HISTOGRAM is not set ++ ++# ++# CD-ROM/DVD Filesystems ++# ++CONFIG_ISO9660_FS=m ++CONFIG_JOLIET=y ++CONFIG_ZISOFS=y ++CONFIG_UDF_FS=m ++CONFIG_UDF_NLS=y ++ ++# ++# DOS/FAT/NT Filesystems ++# ++CONFIG_FAT_FS=y ++CONFIG_MSDOS_FS=y ++CONFIG_VFAT_FS=y ++CONFIG_FAT_DEFAULT_CODEPAGE=437 ++CONFIG_FAT_DEFAULT_IOCHARSET="ascii" ++CONFIG_NTFS_FS=m ++# CONFIG_NTFS_DEBUG is not set ++# CONFIG_NTFS_RW is not set ++ ++# ++# Pseudo filesystems ++# ++CONFIG_PROC_FS=y ++CONFIG_PROC_SYSCTL=y ++CONFIG_PROC_PAGE_MONITOR=y ++CONFIG_SYSFS=y ++CONFIG_TMPFS=y ++# CONFIG_TMPFS_POSIX_ACL is not set ++# CONFIG_TMPFS_XATTR is not set ++# CONFIG_HUGETLB_PAGE is not set ++CONFIG_CONFIGFS_FS=y ++CONFIG_MISC_FILESYSTEMS=y ++# CONFIG_ADFS_FS is not set ++# CONFIG_AFFS_FS is not set ++# CONFIG_ECRYPT_FS is not set ++# CONFIG_HFS_FS is not set ++# CONFIG_HFSPLUS_FS is not set ++# CONFIG_BEFS_FS is not set ++# CONFIG_BFS_FS is not set ++# CONFIG_EFS_FS is not set ++# CONFIG_LOGFS is not set ++# CONFIG_CRAMFS is not set ++# CONFIG_SQUASHFS is not set ++# CONFIG_VXFS_FS is not set ++# CONFIG_MINIX_FS is not set ++# CONFIG_OMFS_FS is not set ++# CONFIG_HPFS_FS is not set ++# CONFIG_QNX4FS_FS is not set ++# CONFIG_ROMFS_FS is not set ++# CONFIG_PSTORE is not set ++# CONFIG_SYSV_FS is not set ++# CONFIG_UFS_FS is not set ++CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_NFS_FS=y ++CONFIG_NFS_V3=y ++CONFIG_NFS_V3_ACL=y ++CONFIG_NFS_V4=y ++# CONFIG_NFS_V4_1 is not set ++CONFIG_ROOT_NFS=y ++CONFIG_NFS_FSCACHE=y ++# CONFIG_NFS_USE_LEGACY_DNS is not set ++CONFIG_NFS_USE_KERNEL_DNS=y ++# CONFIG_NFS_USE_NEW_IDMAPPER is not set ++# CONFIG_NFSD is not set ++CONFIG_LOCKD=y ++CONFIG_LOCKD_V4=y ++CONFIG_NFS_ACL_SUPPORT=y ++CONFIG_NFS_COMMON=y ++CONFIG_SUNRPC=y ++CONFIG_SUNRPC_GSS=y ++# CONFIG_CEPH_FS is not set ++CONFIG_CIFS=m ++# CONFIG_CIFS_STATS is not set ++CONFIG_CIFS_WEAK_PW_HASH=y ++# CONFIG_CIFS_UPCALL is not set ++CONFIG_CIFS_XATTR=y ++CONFIG_CIFS_POSIX=y ++# CONFIG_CIFS_DEBUG2 is not set ++# CONFIG_CIFS_DFS_UPCALL is not set ++# CONFIG_CIFS_FSCACHE is not set ++# CONFIG_CIFS_ACL is not set ++# CONFIG_NCP_FS is not set ++# CONFIG_CODA_FS is not set ++# CONFIG_AFS_FS is not set ++ ++# ++# Partition Types ++# ++CONFIG_PARTITION_ADVANCED=y ++# CONFIG_ACORN_PARTITION is not set ++# CONFIG_OSF_PARTITION is not set ++# CONFIG_AMIGA_PARTITION is not set ++# CONFIG_ATARI_PARTITION is not set ++CONFIG_MAC_PARTITION=y ++CONFIG_MSDOS_PARTITION=y ++# CONFIG_BSD_DISKLABEL is not set ++# CONFIG_MINIX_SUBPARTITION is not set ++# CONFIG_SOLARIS_X86_PARTITION is not set ++# CONFIG_UNIXWARE_DISKLABEL is not set ++# CONFIG_LDM_PARTITION is not set ++# CONFIG_SGI_PARTITION is not set ++# CONFIG_ULTRIX_PARTITION is not set ++# CONFIG_SUN_PARTITION is not set ++# CONFIG_KARMA_PARTITION is not set ++CONFIG_EFI_PARTITION=y ++# CONFIG_SYSV68_PARTITION is not set ++CONFIG_NLS=y ++CONFIG_NLS_DEFAULT="utf8" ++CONFIG_NLS_CODEPAGE_437=y ++CONFIG_NLS_CODEPAGE_737=m ++CONFIG_NLS_CODEPAGE_775=m ++CONFIG_NLS_CODEPAGE_850=m ++CONFIG_NLS_CODEPAGE_852=m ++CONFIG_NLS_CODEPAGE_855=m ++CONFIG_NLS_CODEPAGE_857=m ++CONFIG_NLS_CODEPAGE_860=m ++CONFIG_NLS_CODEPAGE_861=m ++CONFIG_NLS_CODEPAGE_862=m ++CONFIG_NLS_CODEPAGE_863=m ++CONFIG_NLS_CODEPAGE_864=m ++CONFIG_NLS_CODEPAGE_865=m ++CONFIG_NLS_CODEPAGE_866=m ++CONFIG_NLS_CODEPAGE_869=m ++CONFIG_NLS_CODEPAGE_936=m ++CONFIG_NLS_CODEPAGE_950=m ++CONFIG_NLS_CODEPAGE_932=m ++CONFIG_NLS_CODEPAGE_949=m ++CONFIG_NLS_CODEPAGE_874=m ++CONFIG_NLS_ISO8859_8=m ++CONFIG_NLS_CODEPAGE_1250=m ++CONFIG_NLS_CODEPAGE_1251=m ++CONFIG_NLS_ASCII=y ++CONFIG_NLS_ISO8859_1=m ++CONFIG_NLS_ISO8859_2=m ++CONFIG_NLS_ISO8859_3=m ++CONFIG_NLS_ISO8859_4=m ++CONFIG_NLS_ISO8859_5=m ++CONFIG_NLS_ISO8859_6=m ++CONFIG_NLS_ISO8859_7=m ++CONFIG_NLS_ISO8859_9=m ++CONFIG_NLS_ISO8859_13=m ++CONFIG_NLS_ISO8859_14=m ++CONFIG_NLS_ISO8859_15=m ++CONFIG_NLS_KOI8_R=m ++CONFIG_NLS_KOI8_U=m ++CONFIG_NLS_UTF8=m ++# CONFIG_DLM is not set ++ ++# ++# Kernel hacking ++# ++# CONFIG_PRINTK_TIME is not set ++CONFIG_DEFAULT_MESSAGE_LOGLEVEL=4 ++CONFIG_ENABLE_WARN_DEPRECATED=y ++CONFIG_ENABLE_MUST_CHECK=y ++CONFIG_FRAME_WARN=1024 ++# CONFIG_MAGIC_SYSRQ is not set ++# CONFIG_STRIP_ASM_SYMS is not set ++# CONFIG_UNUSED_SYMBOLS is not set ++# CONFIG_DEBUG_FS is not set ++# CONFIG_HEADERS_CHECK is not set ++# CONFIG_DEBUG_SECTION_MISMATCH is not set ++CONFIG_DEBUG_KERNEL=y ++# CONFIG_DEBUG_SHIRQ is not set ++# CONFIG_LOCKUP_DETECTOR is not set ++# CONFIG_HARDLOCKUP_DETECTOR is not set ++# CONFIG_DETECT_HUNG_TASK is not set ++# CONFIG_SCHED_DEBUG is not set ++# CONFIG_SCHEDSTATS is not set ++# CONFIG_TIMER_STATS is not set ++# CONFIG_DEBUG_OBJECTS is not set ++# CONFIG_DEBUG_SLAB is not set ++# CONFIG_DEBUG_KMEMLEAK is not set ++# CONFIG_DEBUG_RT_MUTEXES is not set ++# CONFIG_RT_MUTEX_TESTER is not set ++# CONFIG_DEBUG_SPINLOCK is not set ++# CONFIG_DEBUG_MUTEXES is not set ++# CONFIG_DEBUG_LOCK_ALLOC is not set ++# CONFIG_PROVE_LOCKING is not set ++# CONFIG_SPARSE_RCU_POINTER is not set ++# CONFIG_LOCK_STAT is not set ++# CONFIG_DEBUG_ATOMIC_SLEEP is not set ++# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set ++# CONFIG_DEBUG_STACK_USAGE is not set ++# CONFIG_DEBUG_KOBJECT is not set ++# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_DEBUG_INFO is not set ++# CONFIG_DEBUG_VM is not set ++# CONFIG_DEBUG_WRITECOUNT is not set ++# CONFIG_DEBUG_MEMORY_INIT is not set ++# CONFIG_DEBUG_LIST is not set ++# CONFIG_TEST_LIST_SORT is not set ++# CONFIG_DEBUG_SG is not set ++# CONFIG_DEBUG_NOTIFIERS is not set ++# CONFIG_DEBUG_CREDENTIALS is not set ++CONFIG_FRAME_POINTER=y ++# CONFIG_BOOT_PRINTK_DELAY is not set ++# CONFIG_RCU_TORTURE_TEST is not set ++# CONFIG_BACKTRACE_SELF_TEST is not set ++# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set ++# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set ++# CONFIG_FAULT_INJECTION is not set ++# CONFIG_LATENCYTOP is not set ++# CONFIG_SYSCTL_SYSCALL_CHECK is not set ++# CONFIG_DEBUG_PAGEALLOC is not set ++CONFIG_HAVE_FUNCTION_TRACER=y ++CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y ++CONFIG_HAVE_DYNAMIC_FTRACE=y ++CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y ++CONFIG_HAVE_C_RECORDMCOUNT=y ++CONFIG_TRACING_SUPPORT=y ++# CONFIG_FTRACE is not set ++# CONFIG_DMA_API_DEBUG is not set ++# CONFIG_ATOMIC64_SELFTEST is not set ++# CONFIG_SAMPLES is not set ++CONFIG_HAVE_ARCH_KGDB=y ++# CONFIG_KGDB is not set ++# CONFIG_TEST_KSTRTOX is not set ++# CONFIG_STRICT_DEVMEM is not set ++# CONFIG_ARM_UNWIND is not set ++# CONFIG_DEBUG_USER is not set ++# CONFIG_DEBUG_LL is not set ++# CONFIG_OC_ETM is not set ++ ++# ++# Security options ++# ++CONFIG_KEYS=y ++# CONFIG_KEYS_DEBUG_PROC_KEYS is not set ++# CONFIG_SECURITY_DMESG_RESTRICT is not set ++# CONFIG_SECURITY is not set ++# CONFIG_SECURITYFS is not set ++CONFIG_DEFAULT_SECURITY_DAC=y ++CONFIG_DEFAULT_SECURITY="" ++CONFIG_CRYPTO=y ++ ++# ++# Crypto core or helper ++# ++CONFIG_CRYPTO_ALGAPI=y ++CONFIG_CRYPTO_ALGAPI2=y ++CONFIG_CRYPTO_AEAD=m ++CONFIG_CRYPTO_AEAD2=y ++CONFIG_CRYPTO_BLKCIPHER=y ++CONFIG_CRYPTO_BLKCIPHER2=y ++CONFIG_CRYPTO_HASH=y ++CONFIG_CRYPTO_HASH2=y ++CONFIG_CRYPTO_RNG=m ++CONFIG_CRYPTO_RNG2=y ++CONFIG_CRYPTO_PCOMP2=y ++CONFIG_CRYPTO_MANAGER=y ++CONFIG_CRYPTO_MANAGER2=y ++CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y ++# CONFIG_CRYPTO_GF128MUL is not set ++# CONFIG_CRYPTO_NULL is not set ++CONFIG_CRYPTO_WORKQUEUE=y ++# CONFIG_CRYPTO_CRYPTD is not set ++CONFIG_CRYPTO_AUTHENC=m ++# CONFIG_CRYPTO_TEST is not set ++ ++# ++# Authenticated Encryption with Associated Data ++# ++# CONFIG_CRYPTO_CCM is not set ++# CONFIG_CRYPTO_GCM is not set ++CONFIG_CRYPTO_SEQIV=m ++ ++# ++# Block modes ++# ++CONFIG_CRYPTO_CBC=y ++# CONFIG_CRYPTO_CTR is not set ++# CONFIG_CRYPTO_CTS is not set ++CONFIG_CRYPTO_ECB=m ++# CONFIG_CRYPTO_LRW is not set ++# CONFIG_CRYPTO_PCBC is not set ++# CONFIG_CRYPTO_XTS is not set ++ ++# ++# Hash modes ++# ++CONFIG_CRYPTO_HMAC=y ++CONFIG_CRYPTO_XCBC=m ++# CONFIG_CRYPTO_VMAC is not set ++ ++# ++# Digest ++# ++CONFIG_CRYPTO_CRC32C=y ++# CONFIG_CRYPTO_GHASH is not set ++CONFIG_CRYPTO_MD4=m ++CONFIG_CRYPTO_MD5=y ++CONFIG_CRYPTO_MICHAEL_MIC=m ++# CONFIG_CRYPTO_RMD128 is not set ++# CONFIG_CRYPTO_RMD160 is not set ++# CONFIG_CRYPTO_RMD256 is not set ++# CONFIG_CRYPTO_RMD320 is not set ++CONFIG_CRYPTO_SHA1=y ++CONFIG_CRYPTO_SHA256=m ++CONFIG_CRYPTO_SHA512=m ++CONFIG_CRYPTO_TGR192=m ++CONFIG_CRYPTO_WP512=m ++ ++# ++# Ciphers ++# ++# CONFIG_CRYPTO_AES is not set ++# CONFIG_CRYPTO_ANUBIS is not set ++CONFIG_CRYPTO_ARC4=m ++# CONFIG_CRYPTO_BLOWFISH is not set ++# CONFIG_CRYPTO_CAMELLIA is not set ++CONFIG_CRYPTO_CAST5=m ++# CONFIG_CRYPTO_CAST6 is not set ++CONFIG_CRYPTO_DES=y ++# CONFIG_CRYPTO_FCRYPT is not set ++# CONFIG_CRYPTO_KHAZAD is not set ++# CONFIG_CRYPTO_SALSA20 is not set ++# CONFIG_CRYPTO_SEED is not set ++# CONFIG_CRYPTO_SERPENT is not set ++# CONFIG_CRYPTO_TEA is not set ++# CONFIG_CRYPTO_TWOFISH is not set ++ ++# ++# Compression ++# ++CONFIG_CRYPTO_DEFLATE=m ++# CONFIG_CRYPTO_ZLIB is not set ++# CONFIG_CRYPTO_LZO is not set ++ ++# ++# Random Number Generation ++# ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++# CONFIG_CRYPTO_USER_API_HASH is not set ++# CONFIG_CRYPTO_USER_API_SKCIPHER is not set ++# CONFIG_CRYPTO_HW is not set ++# CONFIG_BINARY_PRINTF is not set ++ ++# ++# Library routines ++# ++CONFIG_BITREVERSE=y ++CONFIG_CRC_CCITT=m ++CONFIG_CRC16=y ++# CONFIG_CRC_T10DIF is not set ++CONFIG_CRC_ITU_T=y ++CONFIG_CRC32=y ++# CONFIG_CRC7 is not set ++CONFIG_LIBCRC32C=y ++# CONFIG_CRC8 is not set ++CONFIG_ZLIB_INFLATE=m ++CONFIG_ZLIB_DEFLATE=m ++# CONFIG_XZ_DEC is not set ++# CONFIG_XZ_DEC_BCJ is not set ++CONFIG_HAS_IOMEM=y ++CONFIG_HAS_IOPORT=y ++CONFIG_HAS_DMA=y ++CONFIG_NLATTR=y ++CONFIG_GENERIC_ATOMIC64=y ++# CONFIG_AVERAGE is not set ++# CONFIG_CORDIC is not set +Index: linux-3.2.46/arch/arm/kernel/armksyms.c +=================================================================== +--- linux-3.2.46.orig/arch/arm/kernel/armksyms.c 2013-05-30 13:35:16.000000000 +0000 ++++ linux-3.2.46/arch/arm/kernel/armksyms.c 2013-07-26 19:31:51.000000000 +0000 +@@ -46,6 +46,8 @@ + extern void __aeabi_uidiv(void); + extern void __aeabi_uidivmod(void); + extern void __aeabi_ulcmp(void); ++extern void __aeabi_ldivmod(void); ++extern void __aeabi_uldivmod(void); + + extern void fpundefinstr(void); + +@@ -131,6 +133,8 @@ + EXPORT_SYMBOL(__aeabi_uidiv); + EXPORT_SYMBOL(__aeabi_uidivmod); + EXPORT_SYMBOL(__aeabi_ulcmp); ++EXPORT_SYMBOL(__aeabi_ldivmod); ++EXPORT_SYMBOL(__aeabi_uldivmod); + #endif + + /* bitops */ +Index: linux-3.2.46/arch/arm/lib/Makefile +=================================================================== +--- linux-3.2.46.orig/arch/arm/lib/Makefile 2013-05-30 13:35:16.000000000 +0000 ++++ linux-3.2.46/arch/arm/lib/Makefile 2013-07-26 19:31:51.000000000 +0000 +@@ -13,7 +13,8 @@ + testchangebit.o testclearbit.o testsetbit.o \ + ashldi3.o ashrdi3.o lshrdi3.o muldi3.o \ + ucmpdi2.o lib1funcs.o div64.o \ +- io-readsb.o io-writesb.o io-readsl.o io-writesl.o ++ io-readsb.o io-writesb.o io-readsl.o io-writesl.o \ ++ divdi3.o + + mmu-y := clear_user.o copy_page.o getuser.o putuser.o + +Index: linux-3.2.46/arch/arm/lib/divdi3.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/arch/arm/lib/divdi3.c 2013-07-26 19:31:51.000000000 +0000 +@@ -0,0 +1,338 @@ ++/* 64-bit multiplication and division ++ Copyright (C) 1989, 1992-1999, 2000, 2001, 2002, 2003 ++ Free Software Foundation, Inc. ++ This file is part of the GNU C Library. ++ ++ The GNU C Library is free software; you can redistribute it and/or ++ modify it under the terms of the GNU Lesser General Public ++ License as published by the Free Software Foundation; either ++ version 2.1 of the License, or (at your option) any later version. ++ ++ The GNU C Library is distributed in the hope that it will be useful, ++ but WITHOUT ANY WARRANTY; without even the implied warranty of ++ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU ++ Lesser General Public License for more details. ++ ++ You should have received a copy of the GNU Lesser General Public ++ License along with the GNU C Library; if not, write to the Free ++ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA ++ 02111-1307 USA. */ ++ ++#include "longlong.h" ++ ++#define W_TYPE_SIZE (sizeof(long)) ++ ++#ifdef __ARMEB__ ++struct DWstruct { long high, low;}; ++#else ++struct DWstruct { long low, high;}; ++#endif ++ ++typedef union { struct DWstruct s; long long ll; } DWunion; ++ ++/* Prototypes of exported functions. */ ++long long __divdi3 (long long u, long long v); ++long long __moddi3 (long long u, long long v); ++unsigned long long __udivdi3 (unsigned long long u, unsigned long long v); ++unsigned long long __umoddi3 (unsigned long long u, unsigned long long v); ++ ++static unsigned long long ++__udivmoddi4 (unsigned long long n, unsigned long long d, unsigned long long *rp) ++{ ++ DWunion ww; ++ DWunion nn, dd; ++ DWunion rr; ++ unsigned long d0, d1, n0, n1, n2; ++ unsigned long q0, q1; ++ unsigned long b, bm; ++ ++ nn.ll = n; ++ dd.ll = d; ++ ++ d0 = dd.s.low; ++ d1 = dd.s.high; ++ n0 = nn.s.low; ++ n1 = nn.s.high; ++ ++#if !UDIV_NEEDS_NORMALIZATION ++ if (d1 == 0) ++ { ++ if (d0 > n1) ++ { ++ /* 0q = nn / 0D */ ++ ++ udiv_qrnnd (q0, n0, n1, n0, d0); ++ q1 = 0; ++ ++ /* Remainder in n0. */ ++ } ++ else ++ { ++ /* qq = NN / 0d */ ++ ++ if (d0 == 0) ++ d0 = 1 / d0; /* Divide intentionally by zero. */ ++ ++ udiv_qrnnd (q1, n1, 0, n1, d0); ++ udiv_qrnnd (q0, n0, n1, n0, d0); ++ ++ /* Remainder in n0. */ ++ } ++ ++ if (rp != 0) ++ { ++ rr.s.low = n0; ++ rr.s.high = 0; ++ *rp = rr.ll; ++ } ++ } ++ ++#else /* UDIV_NEEDS_NORMALIZATION */ ++ ++ if (d1 == 0) ++ { ++ if (d0 > n1) ++ { ++ /* 0q = nn / 0D */ ++ ++ count_leading_zeros (bm, d0); ++ ++ if (bm != 0) ++ { ++ /* Normalize, i.e. make the most significant bit of the ++ denominator set. */ ++ ++ d0 = d0 << bm; ++ n1 = (n1 << bm) | (n0 >> (W_TYPE_SIZE - bm)); ++ n0 = n0 << bm; ++ } ++ ++ udiv_qrnnd (q0, n0, n1, n0, d0); ++ q1 = 0; ++ ++ /* Remainder in n0 >> bm. */ ++ } ++ else ++ { ++ /* qq = NN / 0d */ ++ ++ if (d0 == 0) ++ d0 = 1 / d0; /* Divide intentionally by zero. */ ++ ++ count_leading_zeros (bm, d0); ++ ++ if (bm == 0) ++ { ++ /* From (n1 >= d0) /\ (the most significant bit of d0 is set), ++ conclude (the most significant bit of n1 is set) /\ (the ++ leading quotient digit q1 = 1). ++ ++ This special case is necessary, not an optimization. ++ (Shifts counts of W_TYPE_SIZE are undefined.) */ ++ ++ n1 -= d0; ++ q1 = 1; ++ } ++ else ++ { ++ /* Normalize. */ ++ ++ b = W_TYPE_SIZE - bm; ++ ++ d0 = d0 << bm; ++ n2 = n1 >> b; ++ n1 = (n1 << bm) | (n0 >> b); ++ n0 = n0 << bm; ++ ++ udiv_qrnnd (q1, n1, n2, n1, d0); ++ } ++ ++ /* n1 != d0... */ ++ ++ udiv_qrnnd (q0, n0, n1, n0, d0); ++ ++ /* Remainder in n0 >> bm. */ ++ } ++ ++ if (rp != 0) ++ { ++ rr.s.low = n0 >> bm; ++ rr.s.high = 0; ++ *rp = rr.ll; ++ } ++ } ++#endif /* UDIV_NEEDS_NORMALIZATION */ ++ ++ else ++ { ++ if (d1 > n1) ++ { ++ /* 00 = nn / DD */ ++ ++ q0 = 0; ++ q1 = 0; ++ ++ /* Remainder in n1n0. */ ++ if (rp != 0) ++ { ++ rr.s.low = n0; ++ rr.s.high = n1; ++ *rp = rr.ll; ++ } ++ } ++ else ++ { ++ /* 0q = NN / dd */ ++ ++ count_leading_zeros (bm, d1); ++ if (bm == 0) ++ { ++ /* From (n1 >= d1) /\ (the most significant bit of d1 is set), ++ conclude (the most significant bit of n1 is set) /\ (the ++ quotient digit q0 = 0 or 1). ++ ++ This special case is necessary, not an optimization. */ ++ ++ /* The condition on the next line takes advantage of that ++ n1 >= d1 (true due to program flow). */ ++ if (n1 > d1 || n0 >= d0) ++ { ++ q0 = 1; ++ sub_ddmmss (n1, n0, n1, n0, d1, d0); ++ } ++ else ++ q0 = 0; ++ ++ q1 = 0; ++ ++ if (rp != 0) ++ { ++ rr.s.low = n0; ++ rr.s.high = n1; ++ *rp = rr.ll; ++ } ++ } ++ else ++ { ++ unsigned long m1, m0; ++ /* Normalize. */ ++ ++ b = W_TYPE_SIZE - bm; ++ ++ d1 = (d1 << bm) | (d0 >> b); ++ d0 = d0 << bm; ++ n2 = n1 >> b; ++ n1 = (n1 << bm) | (n0 >> b); ++ n0 = n0 << bm; ++ ++ udiv_qrnnd (q0, n1, n2, n1, d1); ++ umul_ppmm (m1, m0, q0, d0); ++ ++ if (m1 > n1 || (m1 == n1 && m0 > n0)) ++ { ++ q0--; ++ sub_ddmmss (m1, m0, m1, m0, d1, d0); ++ } ++ ++ q1 = 0; ++ ++ /* Remainder in (n1n0 - m1m0) >> bm. */ ++ if (rp != 0) ++ { ++ sub_ddmmss (n1, n0, n1, n0, m1, m0); ++ rr.s.low = (n1 << b) | (n0 >> bm); ++ rr.s.high = n1 >> bm; ++ *rp = rr.ll; ++ } ++ } ++ } ++ } ++ ++ ww.s.low = q0; ++ ww.s.high = q1; ++ return ww.ll; ++} ++ ++long long ++__divdi3 (long long u, long long v) ++{ ++ long c = 0; ++ long long w; ++ ++ if (u < 0) ++ { ++ c = ~c; ++ u = -u; ++ } ++ if (v < 0) ++ { ++ c = ~c; ++ v = -v; ++ } ++ w = __udivmoddi4 (u, v, 0); ++ if (c) ++ w = -w; ++ return w; ++} ++ ++long long ++__moddi3 (long long u, long long v) ++{ ++ long c = 0; ++ long long w; ++ ++ if (u < 0) ++ { ++ c = ~c; ++ u = -u; ++ } ++ if (v < 0) ++ v = -v; ++ __udivmoddi4 (u, v, &w); ++ if (c) ++ w = -w; ++ return w; ++} ++ ++unsigned long long ++__udivdi3 (unsigned long long u, unsigned long long v) ++{ ++ return __udivmoddi4 (u, v, 0); ++} ++ ++unsigned long long ++__umoddi3 (unsigned long long u, unsigned long long v) ++{ ++ unsigned long long w; ++ ++ __udivmoddi4 (u, v, &w); ++ return w; ++} ++ ++long long ++__gnu_ldivmod_helper (long long a, ++ ++ long long b, ++ long long *remainder) ++{ ++ long long quotient; ++ ++ quotient = __divdi3 (a, b); ++ *remainder = a - b * quotient; ++ ++ return quotient; ++} ++ ++unsigned long long ++ ++__gnu_uldivmod_helper (unsigned long long a, ++ ++ unsigned long long b, ++ unsigned long long *remainder) ++{ ++ unsigned long long quotient; ++ ++ quotient = __udivdi3 (a, b); ++ *remainder = a - b * quotient; ++ return quotient; ++} +Index: linux-3.2.46/arch/arm/lib/lib1funcs.S +=================================================================== +--- linux-3.2.46.orig/arch/arm/lib/lib1funcs.S 2013-05-30 13:35:16.000000000 +0000 ++++ linux-3.2.46/arch/arm/lib/lib1funcs.S 2013-07-26 19:31:51.000000000 +0000 +@@ -349,6 +349,33 @@ + UNWIND(.fnend) + ENDPROC(__aeabi_idivmod) + ++/* Added 64x64 bit division for use with OTG USB driver - multi-precision ++ * arithmetic for RSA encyrption. ++ */ ++ENTRY(__aeabi_ldivmod) ++ ++ sub sp, sp, #8 ++ stmfd sp!, {sp, lr} ++ bl __gnu_ldivmod_helper ++ ldr lr, [sp, #4] ++ add sp, sp, #8 ++ ldmfd sp!, {r2, r3} ++ mov pc, lr ++ ++ENDPROC(__aeabi_ldivmod) ++ ++ENTRY(__aeabi_uldivmod) ++ ++ sub sp, sp, #8 ++ stmfd sp!, {sp, lr} ++ bl __gnu_uldivmod_helper ++ ldr lr, [sp, #4] ++ add sp, sp, #8 ++ ldmfd sp!, {r2, r3} ++ mov pc, lr ++ ++ENDPROC(__aeabi_uldivmod) ++ + #endif + + Ldiv0: +Index: linux-3.2.46/arch/arm/lib/longlong.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/arch/arm/lib/longlong.h 2013-07-26 19:31:51.000000000 +0000 +@@ -0,0 +1,151 @@ ++/* longlong.h -- based on code from gcc-2.95.3 ++ ++ definitions for mixed size 32/64 bit arithmetic. ++ Copyright (C) 1991, 92, 94, 95, 96, 1997, 1998 Free Software Foundation, Inc. ++ ++ This definition file is free software; you can redistribute it ++ and/or modify it under the terms of the GNU General Public ++ License as published by the Free Software Foundation; either ++ version 2, or (at your option) any later version. ++ ++ This definition file is distributed in the hope that it will be ++ useful, but WITHOUT ANY WARRANTY; without even the implied ++ warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. ++ See the GNU General Public License for more details. ++ ++ You should have received a copy of the GNU General Public License ++ along with this program; if not, write to the Free Software ++ Foundation, Inc., 59 Temple Place - Suite 330, ++ Boston, MA 02111-1307, USA. */ ++ ++/* Borrowed from GCC 2.95.3, I Molton 29/07/01 */ ++ ++#define USItype unsigned long ++#define SI_TYPE_SIZE sizeof(USItype) ++ ++#define __BITS4 (SI_TYPE_SIZE / 4) ++#define __ll_B (1L << (SI_TYPE_SIZE / 2)) ++#define __ll_lowpart(t) ((USItype) (t) % __ll_B) ++#define __ll_highpart(t) ((USItype) (t) / __ll_B) ++ ++/* Define auxiliary asm macros. ++ ++ 1) umul_ppmm(high_prod, low_prod, multipler, multiplicand) ++ multiplies two USItype integers MULTIPLER and MULTIPLICAND, ++ and generates a two-part USItype product in HIGH_PROD and ++ LOW_PROD. ++ ++ 2) __umulsidi3(a,b) multiplies two USItype integers A and B, ++ and returns a UDItype product. This is just a variant of umul_ppmm. ++ ++ 3) udiv_qrnnd(quotient, remainder, high_numerator, low_numerator, ++ denominator) divides a two-word unsigned integer, composed by the ++ integers HIGH_NUMERATOR and LOW_NUMERATOR, by DENOMINATOR and ++ places the quotient in QUOTIENT and the remainder in REMAINDER. ++ HIGH_NUMERATOR must be less than DENOMINATOR for correct operation. ++ If, in addition, the most significant bit of DENOMINATOR must be 1, ++ then the pre-processor symbol UDIV_NEEDS_NORMALIZATION is defined to 1. ++ ++ 4) sdiv_qrnnd(quotient, remainder, high_numerator, low_numerator, ++ denominator). Like udiv_qrnnd but the numbers are signed. The ++ quotient is rounded towards 0. ++ ++ 5) count_leading_zeros(count, x) counts the number of zero-bits from ++ the msb to the first non-zero bit. This is the number of steps X ++ needs to be shifted left to set the msb. Undefined for X == 0. ++ ++ 6) add_ssaaaa(high_sum, low_sum, high_addend_1, low_addend_1, ++ high_addend_2, low_addend_2) adds two two-word unsigned integers, ++ composed by HIGH_ADDEND_1 and LOW_ADDEND_1, and HIGH_ADDEND_2 and ++ LOW_ADDEND_2 respectively. The result is placed in HIGH_SUM and ++ LOW_SUM. Overflow (i.e. carry out) is not stored anywhere, and is ++ lost. ++ ++ 7) sub_ddmmss(high_difference, low_difference, high_minuend, ++ low_minuend, high_subtrahend, low_subtrahend) subtracts two ++ two-word unsigned integers, composed by HIGH_MINUEND_1 and ++ LOW_MINUEND_1, and HIGH_SUBTRAHEND_2 and LOW_SUBTRAHEND_2 ++ respectively. The result is placed in HIGH_DIFFERENCE and ++ LOW_DIFFERENCE. Overflow (i.e. carry out) is not stored anywhere, ++ and is lost. ++ ++ If any of these macros are left undefined for a particular CPU, ++ C macros are used. */ ++ ++#if defined (__arm__) ++#define add_ssaaaa(sh, sl, ah, al, bh, bl) \ ++ __asm__ ("adds %1, %4, %5 \n\ ++ adc %0, %2, %3" \ ++ : "=r" ((USItype) (sh)), \ ++ "=&r" ((USItype) (sl)) \ ++ : "%r" ((USItype) (ah)), \ ++ "rI" ((USItype) (bh)), \ ++ "%r" ((USItype) (al)), \ ++ "rI" ((USItype) (bl))) ++#define sub_ddmmss(sh, sl, ah, al, bh, bl) \ ++ __asm__ ("subs %1, %4, %5 \n\ ++ sbc %0, %2, %3" \ ++ : "=r" ((USItype) (sh)), \ ++ "=&r" ((USItype) (sl)) \ ++ : "r" ((USItype) (ah)), \ ++ "rI" ((USItype) (bh)), \ ++ "r" ((USItype) (al)), \ ++ "rI" ((USItype) (bl))) ++#define umul_ppmm(xh, xl, a, b) \ ++ __asm__ ("%@ Inlined umul_ppmm\n" \ ++ "umull %r1, %r0, %r2, %r3" \ ++ : "=&r" ((USItype)(xh)), \ ++ "=r" ((USItype)(xl)) \ ++ : "r" ((USItype)(a)), \ ++ "r" ((USItype)(b)) \ ++ : "r0", "r1") ++#define count_leading_zeros(count, x) \ ++ __asm__ ("clz %0, %1" : "=r"(count) : "r"(x)) ++#define UMUL_TIME 20 ++#define UDIV_TIME 100 ++#endif /* __arm__ */ ++ ++#define __umulsidi3(u, v) \ ++ ({DIunion __w; \ ++ umul_ppmm (__w.s.high, __w.s.low, u, v); \ ++ __w.ll; }) ++ ++#define __udiv_qrnnd_c(q, r, n1, n0, d) \ ++ do { \ ++ USItype __d1, __d0, __q1, __q0; \ ++ USItype __r1, __r0, __m; \ ++ __d1 = __ll_highpart (d); \ ++ __d0 = __ll_lowpart (d); \ ++ \ ++ __r1 = (n1) % __d1; \ ++ __q1 = (n1) / __d1; \ ++ __m = (USItype) __q1 * __d0; \ ++ __r1 = __r1 * __ll_B | __ll_highpart (n0); \ ++ if (__r1 < __m) \ ++ { \ ++ __q1--, __r1 += (d); \ ++ if (__r1 >= (d)) /* i.e. we didn't get carry when adding to __r1 */\ ++ if (__r1 < __m) \ ++ __q1--, __r1 += (d); \ ++ } \ ++ __r1 -= __m; \ ++ \ ++ __r0 = __r1 % __d1; \ ++ __q0 = __r1 / __d1; \ ++ __m = (USItype) __q0 * __d0; \ ++ __r0 = __r0 * __ll_B | __ll_lowpart (n0); \ ++ if (__r0 < __m) \ ++ { \ ++ __q0--, __r0 += (d); \ ++ if (__r0 >= (d)) \ ++ if (__r0 < __m) \ ++ __q0--, __r0 += (d); \ ++ } \ ++ __r0 -= __m; \ ++ \ ++ (q) = (USItype) __q1 * __ll_B | __q0; \ ++ (r) = __r0; \ ++ } while (0) ++ ++#define UDIV_NEEDS_NORMALIZATION 1 ++#define udiv_qrnnd __udiv_qrnnd_c +Index: linux-3.2.46/arch/arm/mach-bcm2708/Kconfig +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/arch/arm/mach-bcm2708/Kconfig 2013-07-26 19:31:51.000000000 +0000 +@@ -0,0 +1,25 @@ ++menu "Broadcom BCM2708 Implementations" ++ depends on ARCH_BCM2708 ++ ++config MACH_BCM2708 ++ bool "Broadcom BCM2708 Development Platform" ++ select CPU_V6 ++ help ++ Include support for the Broadcom(R) BCM2708 platform. ++ ++config BCM2708_GPIO ++ bool "BCM2708 gpio support" ++ depends on MACH_BCM2708 ++ select ARCH_REQUIRE_GPIOLIB ++ default y ++ help ++ Include support for the Broadcom(R) BCM2708 gpio. ++ ++config BCM2708_VCMEM ++ bool "Videocore Memory" ++ depends on MACH_BCM2708 ++ default y ++ help ++ Helper for videocore memory access and total size allocation. ++ ++endmenu +Index: linux-3.2.46/arch/arm/mach-bcm2708/Makefile +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/arch/arm/mach-bcm2708/Makefile 2013-07-26 19:31:51.000000000 +0000 +@@ -0,0 +1,8 @@ ++# ++# Makefile for the linux kernel. ++# ++ ++obj-$(CONFIG_MACH_BCM2708) += clock.o bcm2708.o armctrl.o vcio.o power.o dma.o ++obj-$(CONFIG_BCM2708_GPIO) += bcm2708_gpio.o ++obj-$(CONFIG_BCM2708_VCMEM) += vc_mem.o ++ +Index: linux-3.2.46/arch/arm/mach-bcm2708/Makefile.boot +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/arch/arm/mach-bcm2708/Makefile.boot 2013-07-26 19:31:51.000000000 +0000 +@@ -0,0 +1,3 @@ ++ zreladdr-y := 0x00008000 ++params_phys-y := 0x00000100 ++initrd_phys-y := 0x00800000 +Index: linux-3.2.46/arch/arm/mach-bcm2708/armctrl.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/arch/arm/mach-bcm2708/armctrl.c 2013-07-26 19:31:51.000000000 +0000 +@@ -0,0 +1,399 @@ ++/* ++ * linux/arch/arm/mach-bcm2708/armctrl.c ++ * ++ * Copyright (C) 2010 Broadcom ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++#include ++#include ++#include ++#include ++#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,39) ++#include ++#else ++#include ++#endif ++#include ++ ++#include ++#include ++#include "armctrl.h" ++ ++/* For support of kernels >= 3.0 assume only one VIC for now*/ ++static unsigned int remap_irqs[(INTERRUPT_ARASANSDIO + 1) - INTERRUPT_JPEG] = { ++ INTERRUPT_VC_JPEG, ++ INTERRUPT_VC_USB, ++ INTERRUPT_VC_3D, ++ INTERRUPT_VC_DMA2, ++ INTERRUPT_VC_DMA3, ++ INTERRUPT_VC_I2C, ++ INTERRUPT_VC_SPI, ++ INTERRUPT_VC_I2SPCM, ++ INTERRUPT_VC_SDIO, ++ INTERRUPT_VC_UART, ++ INTERRUPT_VC_ARASANSDIO ++}; ++ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,38) ++static void armctrl_mask_irq(struct irq_data *d) ++#else ++static void armctrl_mask_irq(unsigned int irq) ++#endif ++{ ++ static const unsigned int disables[4] = { ++ IO_ADDRESS(ARM_IRQ_DIBL1), ++ IO_ADDRESS(ARM_IRQ_DIBL2), ++ IO_ADDRESS(ARM_IRQ_DIBL3), ++ 0 ++ }; ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,38) ++ unsigned int data = (unsigned int)irq_get_chip_data(d->irq); ++#else ++ unsigned int data = (unsigned int)get_irq_chip_data(irq); ++#endif ++ writel(1 << (data & 0x1f), __io(disables[(data >> 5) & 0x3])); ++} ++ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,38) ++static void armctrl_unmask_irq(struct irq_data *d) ++#else ++static void armctrl_unmask_irq(unsigned int irq) ++#endif ++{ ++ static const unsigned int enables[4] = { ++ IO_ADDRESS(ARM_IRQ_ENBL1), ++ IO_ADDRESS(ARM_IRQ_ENBL2), ++ IO_ADDRESS(ARM_IRQ_ENBL3), ++ 0 ++ }; ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,38) ++ unsigned int data = (unsigned int)irq_get_chip_data(d->irq); ++#else ++ unsigned int data = (unsigned int)get_irq_chip_data(irq); ++#endif ++ writel(1 << (data & 0x1f), __io(enables[(data >> 5) & 0x3])); ++} ++ ++#if defined(CONFIG_PM) ++ ++/* for kernels 3.xx use the new syscore_ops apis but for older kernels use the sys dev class */ ++ ++/* Static defines ++ * struct armctrl_device - VIC PM device (< 3.xx) ++ * @sysdev: The system device which is registered. (< 3.xx) ++ * @irq: The IRQ number for the base of the VIC. ++ * @base: The register base for the VIC. ++ * @resume_sources: A bitmask of interrupts for resume. ++ * @resume_irqs: The IRQs enabled for resume. ++ * @int_select: Save for VIC_INT_SELECT. ++ * @int_enable: Save for VIC_INT_ENABLE. ++ * @soft_int: Save for VIC_INT_SOFT. ++ * @protect: Save for VIC_PROTECT. ++ */ ++#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,39) ++struct armctrl_device { ++ struct sys_device sysdev; ++#else ++ struct armctrl_info { ++#endif ++ void __iomem *base; ++ int irq; ++ u32 resume_sources; ++ u32 resume_irqs; ++ u32 int_select; ++ u32 int_enable; ++ u32 soft_int; ++ u32 protect; ++#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,39) ++}; ++#else ++ } armctrl; ++#endif ++ ++#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,39) ++ ++static struct armctrl_device armctrl_devices[1]; ++ ++static inline struct armctrl_device *to_vic(struct sys_device *sys) ++{ ++ return container_of(sys, struct armctrl_device, sysdev); ++} ++ ++static int armctrl_id; ++ ++static int armctrl_class_resume(struct sys_device *dev) ++{ ++#if 0 // FIXME ++ struct armctrl_device *armctrl = to_vic(dev); ++ void __iomem *base = armctrl->base; ++ ++ printk(KERN_DEBUG "%s: resuming armctrl at %p\n", __func__, base); ++ ++ writel(armctrl->int_select, base + VIC_INT_SELECT); ++ writel(armctrl->protect, base + VIC_PROTECT); ++ ++ /* set the enabled ints and then clear the non-enabled */ ++ writel(armctrl->int_enable, base + VIC_INT_ENABLE); ++ writel(~armctrl->int_enable, base + VIC_INT_ENABLE_CLEAR); ++ ++ /* and the same for the soft-int register */ ++ ++ writel(armctrl->soft_int, base + VIC_INT_SOFT); ++ writel(~armctrl->soft_int, base + VIC_INT_SOFT_CLEAR); ++#endif ++ return 0; ++} ++ ++static int armctrl_class_suspend(struct sys_device *dev, pm_message_t state) ++{ ++#if 0 // FIXME ++ struct armctrl_device *armctrl = to_vic(dev); ++ void __iomem *base = armctrl->base; ++ ++ printk(KERN_DEBUG "%s: suspending armctrl at %p\n", __func__, base); ++ ++ armctrl->int_select = readl(base + VIC_INT_SELECT); ++ armctrl->int_enable = readl(base + VIC_INT_ENABLE); ++ armctrl->soft_int = readl(base + VIC_INT_SOFT); ++ armctrl->protect = readl(base + VIC_PROTECT); ++ ++ /* set the interrupts (if any) that are used for ++ * resuming the system */ ++ ++ writel(armctrl->resume_irqs, base + VIC_INT_ENABLE); ++ writel(~armctrl->resume_irqs, base + VIC_INT_ENABLE_CLEAR); ++#endif ++ return 0; ++} ++ ++struct sysdev_class armctrl_class = { ++ .name = "armctrl", ++ .suspend = armctrl_class_suspend, ++ .resume = armctrl_class_resume, ++}; ++ ++#endif // < 2.6.39 ++ ++static int armctrl_suspend(void) ++{ ++ return 0; ++} ++ ++static void armctrl_resume(void) ++{ ++ return; ++} ++ ++ ++/** ++ * armctrl_pm_register - Register a VIC for later power management control ++ * @base: The base address of the VIC. ++ * @irq: The base IRQ for the VIC. ++ * @resume_sources: bitmask of interrupts allowed for resume sources. ++ * ++ * For older kernels (< 3.xx) do - ++ * Register the VIC with the system device tree so that it can be notified ++ * of suspend and resume requests and ensure that the correct actions are ++ * taken to re-instate the settings on resume. ++ */ ++static void __init armctrl_pm_register(void __iomem * base, unsigned int irq, ++ u32 resume_sources) ++{ ++#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,39) ++ struct armctrl_device *v; ++ ++ if (armctrl_id >= ARRAY_SIZE(armctrl_devices)) ++ printk(KERN_ERR ++ "%s: too few VICs, increase CONFIG_ARM_VIC_NR\n", ++ __func__); ++ else { ++ v = &armctrl_devices[armctrl_id]; ++ v->base = base; ++ v->resume_sources = resume_sources; ++ v->irq = irq; ++ armctrl_id++; ++ } ++#else ++ armctrl.base = base; ++ armctrl.resume_sources = resume_sources; ++ armctrl.irq = irq; ++#endif ++} ++ ++#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,39) ++ ++/** ++ * armctrl_pm_init - initicall to register VIC pm ++ * ++ * This is called via late_initcall() to register ++ * the resources for the VICs due to the early ++ * nature of the VIC's registration. ++*/ ++static int __init armctrl_pm_init(void) ++{ ++ struct armctrl_device *dev = armctrl_devices; ++ int err; ++ int id; ++ ++ if (armctrl_id == 0) ++ return 0; ++ ++ err = sysdev_class_register(&armctrl_class); ++ if (err) { ++ printk(KERN_ERR "%s: cannot register class\n", __func__); ++ return err; ++ } ++ ++ for (id = 0; id < armctrl_id; id++, dev++) { ++ dev->sysdev.id = id; ++ dev->sysdev.cls = &armctrl_class; ++ ++ err = sysdev_register(&dev->sysdev); ++ if (err) { ++ printk(KERN_ERR "%s: failed to register device\n", ++ __func__); ++ return err; ++ } ++ } ++ ++ return 0; ++} ++ ++late_initcall(armctrl_pm_init); ++ ++#endif // VERSION check ++ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,38) ++static int armctrl_set_wake(struct irq_data *d, unsigned int on) ++#else ++static int armctrl_set_wake(unsigned int irq, unsigned int on) ++#endif ++{ ++#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,39) ++ struct armctrl_device *armctrl = &armctrl_devices[0]; ++#endif ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,38) ++ unsigned int off = d->irq & 31; ++#else ++ unsigned int off = irq & 31; ++#endif ++ u32 bit = 1 << off; ++ ++#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,39) ++ if (!armctrl) ++ return -EINVAL; ++ ++ if (!(bit & armctrl->resume_sources)) ++ return -EINVAL; ++ ++ if (on) ++ armctrl->resume_irqs |= bit; ++ else ++ armctrl->resume_irqs &= ~bit; ++#else ++ if (!(bit & armctrl.resume_sources)) ++ return -EINVAL; ++ ++ if (on) ++ armctrl.resume_irqs |= bit; ++ else ++ armctrl.resume_irqs &= ~bit; ++#endif ++ ++ return 0; ++} ++ ++#else ++static inline void armctrl_pm_register(void __iomem *base, unsigned int irq, ++ u32 arg1) ++{ ++} ++#define armctrl_suspend NULL ++#define armctrl_resume NULL ++#define armctrl_set_wake NULL ++#endif /* CONFIG_PM */ ++ ++#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,39) ++ ++static struct syscore_ops armctrl_syscore_ops = { ++ .suspend = armctrl_suspend, ++ .resume = armctrl_resume, ++}; ++ ++/** ++ * armctrl_syscore_init - initicall to register VIC pm functions ++ * ++ * This is called via late_initcall() to register ++ * the resources for the VICs due to the early ++ * nature of the VIC's registration. ++*/ ++static int __init armctrl_syscore_init(void) ++{ ++ register_syscore_ops(&armctrl_syscore_ops); ++ return 0; ++} ++ ++late_initcall(armctrl_syscore_init); ++ ++#endif ++ ++static struct irq_chip armctrl_chip = { ++ .name = "ARMCTRL", ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,38) ++ .irq_ack = armctrl_mask_irq, ++ .irq_mask = armctrl_mask_irq, ++ .irq_unmask = armctrl_unmask_irq, ++ .irq_set_wake = armctrl_set_wake, ++#else ++ .ack = armctrl_mask_irq, ++ .mask = armctrl_mask_irq, ++ .unmask = armctrl_unmask_irq, ++ .set_wake = armctrl_set_wake, ++#endif ++}; ++ ++/** ++ * armctrl_init - initialise a vectored interrupt controller ++ * @base: iomem base address ++ * @irq_start: starting interrupt number, must be muliple of 32 ++ * @armctrl_sources: bitmask of interrupt sources to allow ++ * @resume_sources: bitmask of interrupt sources to allow for resume ++ */ ++int __init armctrl_init(void __iomem * base, unsigned int irq_start, ++ u32 armctrl_sources, u32 resume_sources) ++{ ++ unsigned int irq; ++ ++ for (irq = 0; irq < NR_IRQS; irq++) { ++ unsigned int data = irq; ++ if (irq >= INTERRUPT_JPEG) ++ data = remap_irqs[irq - INTERRUPT_JPEG]; ++ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,38) ++ irq_set_chip(irq, &armctrl_chip); ++ irq_set_chip_data(irq, (void *)data); ++ irq_set_handler(irq, handle_level_irq); ++#else ++ set_irq_chip(irq, &armctrl_chip); ++ set_irq_chip_data(irq, (void *)data); ++ set_irq_handler(irq, handle_level_irq); ++#endif ++ set_irq_flags(irq, IRQF_VALID | IRQF_PROBE | IRQF_DISABLED); ++ } ++ ++ armctrl_pm_register(base, irq_start, resume_sources); ++ return 0; ++} +Index: linux-3.2.46/arch/arm/mach-bcm2708/armctrl.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/arch/arm/mach-bcm2708/armctrl.h 2013-07-26 19:31:51.000000000 +0000 +@@ -0,0 +1,27 @@ ++/* ++ * linux/arch/arm/mach-bcm2708/armctrl.h ++ * ++ * Copyright (C) 2010 Broadcom ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++#ifndef __BCM2708_ARMCTRL_H ++#define __BCM2708_ARMCTRL_H ++ ++extern int __init armctrl_init(void __iomem * base, unsigned int irq_start, ++ u32 armctrl_sources, u32 resume_sources); ++ ++#endif +Index: linux-3.2.46/arch/arm/mach-bcm2708/bcm2708.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/arch/arm/mach-bcm2708/bcm2708.c 2013-07-26 19:31:51.000000000 +0000 +@@ -0,0 +1,658 @@ ++/* ++ * linux/arch/arm/mach-bcm2708/bcm2708.c ++ * ++ * Copyright (C) 2010 Broadcom ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,38) ++#include ++#else ++#include ++#endif ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++ ++#include "bcm2708.h" ++#include "armctrl.h" ++#include "clock.h" ++ ++/* Effectively we have an IOMMU (ARM<->VideoCore map) that is set up to ++ * give us IO access only to 64Mbytes of physical memory (26 bits). We could ++ * represent this window by setting our dmamasks to 26 bits but, in fact ++ * we're not going to use addresses outside this range (they're not in real ++ * memory) so we don't bother. ++ * ++ * In the future we might include code to use this IOMMU to remap other ++ * physical addresses onto VideoCore memory then the use of 32-bits would be ++ * more legitimate. ++ */ ++#define DMA_MASK_BITS_COMMON 32 ++ ++static void __init bcm2708_init_led(void); ++ ++void __init bcm2708_init_irq(void) ++{ ++ armctrl_init(__io_address(ARMCTRL_IC_BASE), 0, 0, 0); ++} ++ ++static struct map_desc bcm2708_io_desc[] __initdata = { ++ { ++ .virtual = IO_ADDRESS(ARMCTRL_BASE), ++ .pfn = __phys_to_pfn(ARMCTRL_BASE), ++ .length = SZ_4K, ++ .type = MT_DEVICE ++ }, { ++ .virtual = IO_ADDRESS(UART0_BASE), ++ .pfn = __phys_to_pfn(UART0_BASE), ++ .length = SZ_4K, ++ .type = MT_DEVICE ++ }, { ++ .virtual = IO_ADDRESS(UART1_BASE), ++ .pfn = __phys_to_pfn(UART1_BASE), ++ .length = SZ_4K, ++ .type = MT_DEVICE ++ }, { ++#ifdef CONFIG_MMC_BCM2708 /* broadcom legacy SD */ ++ .virtual = IO_ADDRESS(MMCI0_BASE), ++ .pfn = __phys_to_pfn(MMCI0_BASE), ++ .length = SZ_4K, ++ .type = MT_DEVICE ++ }, { ++#endif ++ .virtual = IO_ADDRESS(DMA_BASE), ++ .pfn = __phys_to_pfn(DMA_BASE), ++ .length = SZ_4K, ++ .type = MT_DEVICE ++ }, { ++ .virtual = IO_ADDRESS(MCORE_BASE), ++ .pfn = __phys_to_pfn(MCORE_BASE), ++ .length = SZ_4K, ++ .type = MT_DEVICE ++ }, { ++ .virtual = IO_ADDRESS(ST_BASE), ++ .pfn = __phys_to_pfn(ST_BASE), ++ .length = SZ_4K, ++ .type = MT_DEVICE ++ }, { ++ .virtual = IO_ADDRESS(USB_BASE), ++ .pfn = __phys_to_pfn(USB_BASE), ++ .length = SZ_128K, ++ .type = MT_DEVICE ++ }, { ++ .virtual = IO_ADDRESS(PM_BASE), ++ .pfn = __phys_to_pfn(PM_BASE), ++ .length = SZ_4K, ++ .type = MT_DEVICE ++ }, { ++ .virtual = IO_ADDRESS(GPIO_BASE), ++ .pfn = __phys_to_pfn(GPIO_BASE), ++ .length = SZ_4K, ++ .type = MT_DEVICE ++ } ++}; ++ ++void __init bcm2708_map_io(void) ++{ ++ iotable_init(bcm2708_io_desc, ARRAY_SIZE(bcm2708_io_desc)); ++} ++ ++unsigned long frc_clock_ticks32(void) ++{ ++ /* STC: a free running counter that increments at the rate of 1MHz */ ++ return readl(__io_address(ST_BASE+0x04)); ++} ++ ++unsigned long long frc_clock_ticks63(void) ++{ ++ unsigned long t = frc_clock_ticks32(); ++ /* For cnt32_to_63 to work correctly we MUST call this routine ++ * at least once every half-32-bit-wraparound period - that's once ++ * every 35minutes or so - using it in sched_clock() should ensure this ++ */ ++ return cnt32_to_63(t); ++} ++ ++unsigned long long sched_clock(void) ++{ ++ return 1000ull * frc_clock_ticks63(); ++} ++ ++/* ++ * These are fixed clocks. ++ */ ++static struct clk ref24_clk = { ++ .rate = 3000000, /* The UART is clocked at 3MHz via APB_CLK */ ++}; ++static struct clk osc_clk = { ++#ifdef CONFIG_ARCH_BCM2708_CHIPIT ++ .rate = 27000000, ++#else ++ .rate = 500000000, /* ARM clock is set from the VideoCore booter */ ++#endif ++}; ++/* warning - the USB needs a clock > 34MHz */ ++ ++#ifdef CONFIG_MMC_BCM2708 ++static struct clk sdhost_clk = { ++#ifdef CONFIG_ARCH_BCM2708_CHIPIT ++ .rate = 4000000, /* 4MHz */ ++#else ++ .rate = 250000000, /* 250MHz */ ++#endif ++}; ++#endif ++ ++static struct clk_lookup lookups[] = { ++ { /* UART0 */ ++ .dev_id = "dev:f1", ++ .clk = &ref24_clk, ++ }, ++ { /* USB */ ++ .dev_id = "bcm2708_usb", ++ .clk = &osc_clk, ++#ifdef CONFIG_MMC_BCM2708 ++ }, ++ { /* MCI */ ++ .dev_id = "bcm2708_mci.0", ++ .clk = &sdhost_clk, ++#endif ++ } ++}; ++ ++ ++#define UART0_IRQ { IRQ_UART, NO_IRQ } ++#define UART0_DMA { 15, 14 } ++ ++AMBA_DEVICE(uart0, "dev:f1", UART0, NULL); ++ ++static struct amba_device *amba_devs[] __initdata = { ++ &uart0_device, ++}; ++ ++static struct resource bcm2708_dmaman_resources[] = { ++ { ++ .start = DMA_BASE, ++ .end = DMA_BASE + SZ_4K - 1, ++ .flags = IORESOURCE_MEM, ++ } ++}; ++ ++static struct platform_device bcm2708_dmaman_device = { ++ .name = BCM_DMAMAN_DRIVER_NAME, ++ .id = 0, /* first bcm2708_dma */ ++ .resource = bcm2708_dmaman_resources, ++ .num_resources = ARRAY_SIZE(bcm2708_dmaman_resources), ++}; ++ ++#ifdef CONFIG_MMC_BCM2708 ++static struct resource bcm2708_mci_resources[] = { ++ { ++ .start = MMCI0_BASE, ++ .end = MMCI0_BASE + SZ_4K - 1, ++ .flags = IORESOURCE_MEM, ++ }, { ++ .start = IRQ_SDIO, ++ .end = IRQ_SDIO, ++ .flags = IORESOURCE_IRQ, ++ } ++}; ++ ++ ++static struct platform_device bcm2708_mci_device = { ++ .name = "bcm2708_mci", ++ .id = 0, /* first bcm2708_mci */ ++ .resource = bcm2708_mci_resources, ++ .num_resources = ARRAY_SIZE(bcm2708_mci_resources), ++ .dev = { ++ .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON), ++ }, ++}; ++#endif /* CONFIG_MMC_BCM2708 */ ++ ++ ++static u64 fb_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON); ++ ++static struct platform_device bcm2708_fb_device = { ++ .name = "bcm2708_fb", ++ .id = -1, /* only one bcm2708_fb */ ++ .resource = NULL, ++ .num_resources = 0, ++ .dev = { ++ .dma_mask = &fb_dmamask, ++ .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON), ++ }, ++}; ++ ++static struct plat_serial8250_port bcm2708_uart1_platform_data[] = { ++ { ++ .mapbase = UART1_BASE + 0x40, ++ .irq = IRQ_AUX, ++ .uartclk = 125000000, ++ .regshift = 2, ++ .iotype = UPIO_MEM, ++ .flags = UPF_FIXED_TYPE | UPF_IOREMAP | UPF_SKIP_TEST, ++ .type = PORT_8250, ++ }, ++ { }, ++}; ++ ++static struct platform_device bcm2708_uart1_device = { ++ .name = "serial8250", ++ .id = PLAT8250_DEV_PLATFORM, ++ .dev = { ++ .platform_data = bcm2708_uart1_platform_data, ++ }, ++}; ++ ++static struct resource bcm2708_usb_resources[] = { ++ [0] = { ++ .start = USB_BASE, ++ .end = USB_BASE + SZ_128K - 1, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = IRQ_USB, ++ .end = IRQ_USB, ++ .flags = IORESOURCE_IRQ, ++ }, ++}; ++ ++static u64 usb_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON); ++ ++static struct platform_device bcm2708_usb_device = { ++ .name = "bcm2708_usb", ++ .id = -1, /* only one bcm2708_usb */ ++ .resource = bcm2708_usb_resources, ++ .num_resources = ARRAY_SIZE(bcm2708_usb_resources), ++ .dev = { ++ .dma_mask = &usb_dmamask, ++ .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON), ++ }, ++}; ++ ++static struct resource bcm2708_vcio_resources[] = { ++ [0] = { /* mailbox/semaphore/doorbell access */ ++ .start = MCORE_BASE, ++ .end = MCORE_BASE + SZ_4K - 1, ++ .flags = IORESOURCE_MEM, ++ }, ++}; ++ ++static u64 vcio_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON); ++ ++static struct platform_device bcm2708_vcio_device = { ++ .name = BCM_VCIO_DRIVER_NAME, ++ .id = -1, /* only one VideoCore I/O area */ ++ .resource = bcm2708_vcio_resources, ++ .num_resources = ARRAY_SIZE(bcm2708_vcio_resources), ++ .dev = { ++ .dma_mask = &vcio_dmamask, ++ .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON), ++ }, ++}; ++ ++#ifdef CONFIG_BCM2708_GPIO ++#define BCM_GPIO_DRIVER_NAME "bcm2708_gpio" ++ ++static struct resource bcm2708_gpio_resources[] = { ++ [0] = { /* general purpose I/O */ ++ .start = GPIO_BASE, ++ .end = GPIO_BASE + SZ_4K - 1, ++ .flags = IORESOURCE_MEM, ++ }, ++}; ++ ++static u64 gpio_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON); ++ ++static struct platform_device bcm2708_gpio_device = { ++ .name = BCM_GPIO_DRIVER_NAME, ++ .id = -1, /* only one VideoCore I/O area */ ++ .resource = bcm2708_gpio_resources, ++ .num_resources = ARRAY_SIZE(bcm2708_gpio_resources), ++ .dev = { ++ .dma_mask = &gpio_dmamask, ++ .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON), ++ }, ++}; ++#endif ++ ++#ifdef CONFIG_BCM2708_BUTTONS ++static struct resource bcm2708_vcbuttons_resources[] = { ++}; ++ ++static u64 vcbuttons_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON); ++ ++static struct platform_device bcm2708_vcbuttons_device = { ++ .name = "bcm2708_vcbuttons", ++ .id = -1, /* only one VideoCore I/O area */ ++ .resource = bcm2708_vcbuttons_resources, ++ .num_resources = ARRAY_SIZE(bcm2708_vcbuttons_resources), ++ .dev = { ++ .dma_mask = &vcbuttons_dmamask, ++ .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON), ++ }, ++}; ++#endif ++ ++#ifdef CONFIG_BCM2708_TOUCHSCREEN ++static struct resource bcm2708_vctouch_resources[] = { ++}; ++ ++static u64 vctouch_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON); ++ ++static struct platform_device bcm2708_vctouch_device = { ++ .name = "bcm2708_vctouch", ++ .id = -1, /* only one VideoCore I/O area */ ++ .resource = bcm2708_vctouch_resources, ++ .num_resources = ARRAY_SIZE(bcm2708_vctouch_resources), ++ .dev = { ++ .dma_mask = &vctouch_dmamask, ++ .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON), ++ }, ++}; ++#endif ++ ++static struct resource bcm2708_systemtimer_resources[] = { ++ [0] = { /* system timer access */ ++ .start = ST_BASE, ++ .end = ST_BASE + SZ_4K - 1, ++ .flags = IORESOURCE_MEM, ++ }, { ++ .start = IRQ_TIMER3, ++ .end = IRQ_TIMER3, ++ .flags = IORESOURCE_IRQ, ++ } ++ ++ ++}; ++ ++static u64 systemtimer_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON); ++ ++static struct platform_device bcm2708_systemtimer_device = { ++ .name = "bcm2708_systemtimer", ++ .id = -1, /* only one VideoCore I/O area */ ++ .resource = bcm2708_systemtimer_resources, ++ .num_resources = ARRAY_SIZE(bcm2708_systemtimer_resources), ++ .dev = { ++ .dma_mask = &systemtimer_dmamask, ++ .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON), ++ }, ++}; ++ ++#ifdef CONFIG_MMC_SDHCI_BCM2708 /* Arasan emmc SD */ ++static struct resource bcm2708_emmc_resources[] = { ++ [0] = { ++ .start = EMMC_BASE, ++ .end = EMMC_BASE + SZ_256 - 1, /* we only need this area */ ++ /* the memory map actually makes SZ_4K available */ ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = IRQ_ARASANSDIO, ++ .end = IRQ_ARASANSDIO, ++ .flags = IORESOURCE_IRQ, ++ }, ++}; ++ ++static u64 bcm2708_emmc_dmamask = 0xffffffffUL; ++ ++struct platform_device bcm2708_emmc_device = { ++ .name = "bcm2708_sdhci", ++ .id = 0, ++ .num_resources = ARRAY_SIZE(bcm2708_emmc_resources), ++ .resource = bcm2708_emmc_resources, ++ .dev = { ++ .dma_mask = &bcm2708_emmc_dmamask, ++ .coherent_dma_mask = 0xffffffffUL ++ }, ++}; ++#endif /* CONFIG_MMC_SDHCI_BCM2708 */ ++ ++static struct resource bcm2708_powerman_resources[] = { ++ [0] = { ++ .start = PM_BASE, ++ .end = PM_BASE + SZ_256 - 1, ++ .flags = IORESOURCE_MEM, ++ }, ++}; ++ ++static u64 powerman_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON); ++ ++struct platform_device bcm2708_powerman_device = { ++ .name = "bcm2708_powerman", ++ .id = 0, ++ .num_resources = ARRAY_SIZE(bcm2708_powerman_resources), ++ .resource = bcm2708_powerman_resources, ++ .dev = { ++ .dma_mask = &powerman_dmamask, ++ .coherent_dma_mask = 0xffffffffUL ++ }, ++}; ++ ++int __init bcm_register_device(struct platform_device *pdev) ++{ ++ int ret; ++ ++ ret = platform_device_register(pdev); ++ if (ret) ++ pr_debug("Unable to register platform device '%s': %d\n", ++ pdev->name, ret); ++ ++ return ret; ++} ++ ++void __init bcm2708_init(void) ++{ ++ int i; ++ ++ for (i = 0; i < ARRAY_SIZE(lookups); i++) ++ clkdev_add(&lookups[i]); ++ ++ bcm_register_device(&bcm2708_dmaman_device); ++ bcm_register_device(&bcm2708_vcio_device); ++#ifdef CONFIG_BCM2708_GPIO ++ bcm_register_device(&bcm2708_gpio_device); ++#endif ++ bcm_register_device(&bcm2708_systemtimer_device); ++#ifdef CONFIG_MMC_BCM2708 ++ bcm_register_device(&bcm2708_mci_device); ++#endif ++ bcm_register_device(&bcm2708_fb_device); ++ bcm_register_device(&bcm2708_usb_device); ++ bcm_register_device(&bcm2708_uart1_device); ++#ifdef CONFIG_BCM2708_BUTTONS ++ bcm_register_device(&bcm2708_vcbuttons_device); ++#endif ++#ifdef CONFIG_BCM2708_TOUCHSCREEN ++ bcm_register_device(&bcm2708_vctouch_device); ++#endif ++ bcm_register_device(&bcm2708_powerman_device); ++#ifdef CONFIG_MMC_SDHCI_BCM2708 ++ bcm_register_device(&bcm2708_emmc_device); ++#endif ++ bcm2708_init_led(); ++#ifdef CONFIG_BCM2708_VCMEM ++{ ++ extern void vc_mem_connected_init(void); ++ vc_mem_connected_init(); ++} ++#endif ++ for (i = 0; i < ARRAY_SIZE(amba_devs); i++) { ++ struct amba_device *d = amba_devs[i]; ++ amba_device_register(d, &iomem_resource); ++ } ++} ++ ++#define TIMER_PERIOD 10000 /* HZ in microsecs */ ++ ++static void timer_set_mode(enum clock_event_mode mode, ++ struct clock_event_device *clk) ++{ ++ unsigned long stc; ++ ++ switch (mode) { ++ case CLOCK_EVT_MODE_PERIODIC: ++ stc = readl(__io_address(ST_BASE+0x04)); ++ writel(stc + TIMER_PERIOD, ++ __io_address(ST_BASE+0x18));/* stc3 */ ++ break; ++ case CLOCK_EVT_MODE_ONESHOT: ++ case CLOCK_EVT_MODE_UNUSED: ++ case CLOCK_EVT_MODE_SHUTDOWN: ++ default: ++ printk(KERN_ERR "timer_set_mode: unhandled mode:%d\n", ++ (int)mode); ++ break; ++ } ++ ++} ++ ++static int timer_set_next_event(unsigned long evt, ++ struct clock_event_device *unused) ++{ ++ unsigned long stc; ++ ++ stc = readl(__io_address(ST_BASE + 0x04)); ++ writel(stc + TIMER_PERIOD, __io_address(ST_BASE+0x18)); /* stc3 */ ++ return 0; ++} ++ ++static struct clock_event_device timer0_clockevent = { ++ .name = "timer0", ++ .shift = 32, ++ .features = CLOCK_EVT_FEAT_ONESHOT, ++ .set_mode = timer_set_mode, ++ .set_next_event = timer_set_next_event, ++}; ++ ++/* ++ * IRQ handler for the timer ++ */ ++static irqreturn_t bcm2708_timer_interrupt(int irq, void *dev_id) ++{ ++ struct clock_event_device *evt = &timer0_clockevent; ++ ++ writel(1<<3, __io_address(ST_BASE+0x00)); /* stcs clear timer int */ ++ ++ evt->event_handler(evt); ++ ++ return IRQ_HANDLED; ++} ++ ++static struct irqaction bcm2708_timer_irq = { ++ .name = "BCM2708 Timer Tick", ++ .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, ++ .handler = bcm2708_timer_interrupt, ++}; ++ ++/* ++ * Set up timer interrupt, and return the current time in seconds. ++ */ ++static void __init bcm2708_timer_init(void) ++{ ++ /* ++ * Initialise to a known state (all timers off) ++ */ ++ writel(0, __io_address(ARM_T_CONTROL)); ++ /* ++ * Make irqs happen for the system timer ++ */ ++ setup_irq(IRQ_TIMER3, &bcm2708_timer_irq); ++ ++ timer0_clockevent.mult = ++ div_sc(1000000, NSEC_PER_SEC, timer0_clockevent.shift); ++ timer0_clockevent.max_delta_ns = ++ clockevent_delta2ns(0xffffffff, &timer0_clockevent); ++ timer0_clockevent.min_delta_ns = ++ clockevent_delta2ns(0xf, &timer0_clockevent); ++ ++ timer0_clockevent.cpumask = cpumask_of(0); ++ clockevents_register_device(&timer0_clockevent); ++} ++ ++struct sys_timer bcm2708_timer = { ++ .init = bcm2708_timer_init, ++}; ++ ++#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE) ++#include ++ ++static struct gpio_led bcm2708_leds[] = { ++ [0] = { ++ .gpio = 16, ++ .name = "led0", ++ .default_trigger = "mmc0", ++ .active_low = 0, ++ }, ++}; ++ ++static struct gpio_led_platform_data bcm2708_led_pdata = { ++ .num_leds = ARRAY_SIZE(bcm2708_leds), ++ .leds = bcm2708_leds, ++}; ++ ++static struct platform_device bcm2708_led_device = { ++ .name = "leds-gpio", ++ .id = -1, ++ .dev = { ++ .platform_data = &bcm2708_led_pdata, ++ }, ++}; ++ ++static void __init bcm2708_init_led(void) ++{ ++ platform_device_register(&bcm2708_led_device); ++} ++#else ++static inline void bcm2708_init_led(void) {} ++#endif ++ ++ ++MACHINE_START(BCM2708, "BCM2708") ++ /* Maintainer: Broadcom Europe Ltd. */ ++ .map_io = bcm2708_map_io, ++ .init_irq = bcm2708_init_irq, ++ .timer = &bcm2708_timer, ++ .init_machine = bcm2708_init, ++MACHINE_END +Index: linux-3.2.46/arch/arm/mach-bcm2708/bcm2708.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/arch/arm/mach-bcm2708/bcm2708.h 2013-07-26 19:31:51.000000000 +0000 +@@ -0,0 +1,51 @@ ++/* ++ * linux/arch/arm/mach-bcm2708/bcm2708.h ++ * ++ * BCM2708 machine support header ++ * ++ * Copyright (C) 2010 Broadcom ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++#ifndef __BCM2708_BCM2708_H ++#define __BCM2708_BCM2708_H ++ ++#include ++ ++extern void __init bcm2708_init(void); ++extern void __init bcm2708_init_irq(void); ++extern void __init bcm2708_map_io(void); ++extern struct sys_timer bcm2708_timer; ++extern unsigned int mmc_status(struct device *dev); ++ ++#define AMBA_DEVICE(name, busid, base, plat) \ ++static struct amba_device name##_device = { \ ++ .dev = { \ ++ .coherent_dma_mask = ~0, \ ++ .init_name = busid, \ ++ .platform_data = plat, \ ++ }, \ ++ .res = { \ ++ .start = base##_BASE, \ ++ .end = (base##_BASE) + SZ_4K - 1,\ ++ .flags = IORESOURCE_MEM, \ ++ }, \ ++ .dma_mask = ~0, \ ++ .irq = base##_IRQ, \ ++ /* .dma = base##_DMA,*/ \ ++} ++ ++#endif +Index: linux-3.2.46/arch/arm/mach-bcm2708/bcm2708_gpio.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/arch/arm/mach-bcm2708/bcm2708_gpio.c 2013-07-26 19:31:51.000000000 +0000 +@@ -0,0 +1,323 @@ ++/* ++ * linux/arch/arm/mach-bcm2708/bcm2708_gpio.c ++ * ++ * Copyright (C) 2010 Broadcom ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define BCM_GPIO_DRIVER_NAME "bcm2708_gpio" ++#define DRIVER_NAME BCM_GPIO_DRIVER_NAME ++#define BCM_GPIO_USE_IRQ 0 ++ ++#define GPIOFSEL(x) (0x00+(x)*4) ++#define GPIOSET(x) (0x1c+(x)*4) ++#define GPIOCLR(x) (0x28+(x)*4) ++#define GPIOLEV(x) (0x34+(x)*4) ++#define GPIOEDS(x) (0x40+(x)*4) ++#define GPIOREN(x) (0x4c+(x)*4) ++#define GPIOFEN(x) (0x58+(x)*4) ++#define GPIOHEN(x) (0x64+(x)*4) ++#define GPIOLEN(x) (0x70+(x)*4) ++#define GPIOAREN(x) (0x7c+(x)*4) ++#define GPIOAFEN(x) (0x88+(x)*4) ++#define GPIOUD(x) (0x94+(x)*4) ++#define GPIOUDCLK(x) (0x98+(x)*4) ++ ++enum { GPIO_FSEL_INPUT, GPIO_FSEL_OUTPUT, ++ GPIO_FSEL_ALT5, GPIO_FSEL_ALT_4, ++ GPIO_FSEL_ALT0, GPIO_FSEL_ALT1, ++ GPIO_FSEL_ALT2, GPIO_FSEL_ALT3, }; ++ ++ /* Each of the two spinlocks protects a different set of hardware ++ * regiters and data structurs. This decouples the code of the IRQ from ++ * the GPIO code. This also makes the case of a GPIO routine call from ++ * the IRQ code simpler. ++ */ ++static DEFINE_SPINLOCK(lock); /* GPIO registers */ ++static DEFINE_SPINLOCK(irq_lock); /* IRQ registers */ ++ ++ ++struct bcm2708_gpio { ++ /* We use a list of bcm2708_gpio structs for each trigger IRQ in the main ++ * interrupts controller of the system. We need this to support systems ++ * in which more that one bcm2708s are connected to the same IRQ. The ISR ++ * interates through this list to find the source of the interrupt. ++ */ ++ struct list_head list; ++ ++ void __iomem *base; ++ unsigned irq_base; ++ struct gpio_chip gc; ++}; ++ ++static int bcm2708_set_function(struct gpio_chip *gc, unsigned offset, int function) ++{ ++ struct bcm2708_gpio *gpio = container_of(gc, struct bcm2708_gpio, gc); ++ unsigned long flags; ++ unsigned gpiodir; ++ unsigned gpio_bank = offset/10; ++ unsigned gpio_field_offset = (offset - 10*gpio_bank) * 3; ++ ++//printk(KERN_ERR DRIVER_NAME ": bcm2708_gpio_set_function %p (%d,%d)\n", gc, offset, function); ++ if (offset >= ARCH_NR_GPIOS) ++ return -EINVAL; ++ ++ spin_lock_irqsave(&lock, flags); ++ ++ gpiodir = readl(gpio->base + GPIOFSEL(gpio_bank)); ++ gpiodir &= ~(7 << gpio_field_offset); ++ gpiodir |= function << gpio_field_offset; ++ writel(gpiodir, gpio->base + GPIOFSEL(gpio_bank)); ++ spin_unlock_irqrestore(&lock, flags); ++ gpiodir = readl(gpio->base + GPIOFSEL(gpio_bank)); ++ ++ return 0; ++} ++ ++ ++static int bcm2708_gpio_dir_in(struct gpio_chip *gc, unsigned offset) ++{ ++ return bcm2708_set_function(gc, offset, GPIO_FSEL_INPUT); ++} ++ ++static void bcm2708_gpio_set(struct gpio_chip *gc, unsigned offset, int value); ++static int bcm2708_gpio_dir_out(struct gpio_chip *gc, unsigned offset, int value) ++{ ++ int ret; ++ ret = bcm2708_set_function(gc, offset, GPIO_FSEL_OUTPUT); ++ if (ret >= 0) ++ bcm2708_gpio_set(gc, offset, value); ++ return ret; ++} ++ ++static int bcm2708_gpio_get(struct gpio_chip *gc, unsigned offset) ++{ ++ struct bcm2708_gpio *gpio = container_of(gc, struct bcm2708_gpio, gc); ++ unsigned gpio_bank = offset/32; ++ unsigned gpio_field_offset = (offset - 32*gpio_bank); ++ unsigned lev; ++ ++ if (offset >= ARCH_NR_GPIOS) ++ return 0; ++ lev = readl(gpio->base + GPIOLEV(gpio_bank)); ++//printk(KERN_ERR DRIVER_NAME ": bcm2708_gpio_get %p (%d)=%d\n", gc, offset, 0x1 & (lev>>gpio_field_offset)); ++ return 0x1 & (lev>>gpio_field_offset); ++} ++ ++static void bcm2708_gpio_set(struct gpio_chip *gc, unsigned offset, int value) ++{ ++ struct bcm2708_gpio *gpio = container_of(gc, struct bcm2708_gpio, gc); ++ unsigned gpio_bank = offset/32; ++ unsigned gpio_field_offset = (offset - 32*gpio_bank); ++//printk(KERN_ERR DRIVER_NAME ": bcm2708_gpio_set %p (%d=%d)\n", gc, offset, value); ++ if (offset >= ARCH_NR_GPIOS) ++ return; ++ if (value) ++ writel(1<base + GPIOSET(gpio_bank)); ++ else ++ writel(1<base + GPIOCLR(gpio_bank)); ++} ++ ++/* ++ * bcm2708 GPIO IRQ ++ */ ++ ++#if BCM_GPIO_USE_IRQ ++static void bcm2708_irq_disable(unsigned irq) ++{ ++ struct bcm2708_gpio *chip = get_irq_chip_data(irq); ++ //int offset = irq - gpio->irq_base; ++ unsigned long flags; ++ ++ spin_lock_irqsave(&chip->irq_lock, flags); ++ // disable gpio interrupts here ++ spin_unlock_irqrestore(&chip->irq_lock, flags); ++} ++ ++static void bcm2708_irq_enable(unsigned irq) ++{ ++ struct bcm2708_gpio *chip = get_irq_chip_data(irq); ++ //int offset = irq - chip->irq_base; ++ unsigned long flags; ++ ++ spin_lock_irqsave(&chip->irq_lock, flags); ++ // enable gpio interrupts here ++ spin_unlock_irqrestore(&chip->irq_lock, flags); ++} ++ ++static int bcm2708_irq_type(unsigned irq, unsigned trigger) ++{ ++ struct bcm2708_gpio *chip = get_irq_chip_data(irq); ++ int offset = irq - chip->irq_base; ++ unsigned long flags; ++ unsigned gpio_bank = offset/32; ++ unsigned gpio_field_offset = (offset - 32*gpio_bank); ++ unsigned gpioren, gpiofen, gpiohen, gpiolen; ++ ++ if (offset < 0 || offset >= ARCH_NR_GPIOS) ++ return -EINVAL; ++ ++ spin_lock_irqsave(&chip->irq_lock, flags); ++ ++ gpioren = readl(chip->base + GPIOREN(gpio_bank)); ++ gpiofen = readl(chip->base + GPIOFEN(gpio_bank)); ++ gpiohen = readl(chip->base + GPIOHEN(gpio_bank)); ++ gpiolen = readl(chip->base + GPIOLEN(gpio_bank)); ++ ++ if (trigger & (IRQ_TYPE_EDGE_RISING)) ++ gpioren |= (1<base + GPIOREN(gpio_bank)); ++ writel(gpiofen, chip->base + GPIOFEN(gpio_bank)); ++ writel(gpiohen, chip->base + GPIOHEN(gpio_bank)); ++ writel(gpiolen, chip->base + GPIOLEN(gpio_bank)); ++ ++ spin_unlock_irqrestore(&chip->irq_lock, flags); ++ ++ return 0; ++} ++ ++static struct irq_chip bcm2708_irqchip = { ++ .name = "GPIO", ++ .enable = bcm2708_irq_enable, ++ .disable = bcm2708_irq_disable, ++ .set_type = bcm2708_irq_type, ++}; ++ ++static void bcm2708_irq_handler(unsigned irq, struct irq_desc *desc) ++{ ++ struct list_head *chip_list = get_irq_data(irq); ++ struct list_head *ptr; ++ struct bcm2708_gpio *chip; ++ unsigned gpio_bank; ++ ++ desc->chip->ack(irq); ++ list_for_each(ptr, chip_list) { ++ unsigned long pending; ++ int offset; ++ ++ chip = list_entry(ptr, struct bcm2708_gpio, list); ++ for (gpio_bank = 0; gpio_bank < ARCH_NR_GPIOS/32; gpio_bank++) { ++ pending = readl(chip->base + GPIOEDS(gpio_bank)); ++ writel(pending, chip->base + GPIOEDS(gpio_bank)); ++ ++ if (pending == 0) ++ continue; ++ ++ for_each_set_bit(offset, &pending, ARCH_NR_GPIOS) ++ generic_handle_irq(gpio_to_irq(offset+32*gpio_bank)); ++ } ++ } ++ desc->chip->unmask(irq); ++} ++#endif /* #if BCM_GPIO_USE_IRQ */ ++ ++static int bcm2708_gpio_probe(struct platform_device *dev) ++{ ++ struct bcm2708_gpio *ucb; ++ struct resource *res; ++ int err = 0; ++ ++ printk(KERN_ERR DRIVER_NAME ": bcm2708_gpio_probe %p\n", dev); ++ ++ ucb = kzalloc(sizeof(*ucb), GFP_KERNEL); ++ if (NULL == ucb) { ++ printk(KERN_ERR DRIVER_NAME ": failed to allocate " ++ "mailbox memory\n"); ++ err = -ENOMEM; ++ goto err; ++ } ++ ++ res = platform_get_resource(dev, IORESOURCE_MEM, 0); ++ ++ platform_set_drvdata(dev, ucb); ++ ucb->base = __io_address(GPIO_BASE); ++ ++ ucb->gc.label = "bcm2708_gpio"; ++ ucb->gc.base = 0; ++ ucb->gc.ngpio = ARCH_NR_GPIOS; ++ ucb->gc.owner = THIS_MODULE; ++ ++ ucb->gc.direction_input = bcm2708_gpio_dir_in; ++ ucb->gc.direction_output = bcm2708_gpio_dir_out; ++ ucb->gc.get = bcm2708_gpio_get; ++ ucb->gc.set = bcm2708_gpio_set; ++ ucb->gc.can_sleep = 0; ++ ++ err = gpiochip_add(&ucb->gc); ++ if (err) ++ goto err; ++ ++err: ++ return err; ++ ++} ++ ++static int bcm2708_gpio_remove(struct platform_device *dev) ++{ ++ int err = 0; ++ struct bcm2708_gpio *ucb = platform_get_drvdata(dev); ++ ++ printk(KERN_ERR DRIVER_NAME ": bcm2708_gpio_remove %p\n", dev); ++ ++ err = gpiochip_remove(&ucb->gc); ++ ++ platform_set_drvdata(dev, NULL); ++ kfree(ucb); ++ ++ return err; ++} ++ ++static struct platform_driver bcm2708_gpio_driver = { ++ .probe = bcm2708_gpio_probe, ++ .remove = bcm2708_gpio_remove, ++ .driver = { ++ .name = "bcm2708_gpio" ++ }, ++}; ++ ++static int __init bcm2708_gpio_init(void) ++{ ++ return platform_driver_register(&bcm2708_gpio_driver); ++} ++ ++static void __exit bcm2708_gpio_exit(void) ++{ ++ platform_driver_unregister(&bcm2708_gpio_driver); ++} ++ ++module_init(bcm2708_gpio_init); ++module_exit(bcm2708_gpio_exit); ++ ++MODULE_DESCRIPTION("Broadcom BCM2708 GPIO driver"); ++MODULE_LICENSE("GPL"); ++ +Index: linux-3.2.46/arch/arm/mach-bcm2708/clock.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/arch/arm/mach-bcm2708/clock.c 2013-07-26 19:31:51.000000000 +0000 +@@ -0,0 +1,61 @@ ++/* ++ * linux/arch/arm/mach-bcm2708/clock.c ++ * ++ * Copyright (C) 2010 Broadcom ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#include "clock.h" ++ ++int clk_enable(struct clk *clk) ++{ ++ return 0; ++} ++EXPORT_SYMBOL(clk_enable); ++ ++void clk_disable(struct clk *clk) ++{ ++} ++EXPORT_SYMBOL(clk_disable); ++ ++unsigned long clk_get_rate(struct clk *clk) ++{ ++ return clk->rate; ++} ++EXPORT_SYMBOL(clk_get_rate); ++ ++long clk_round_rate(struct clk *clk, unsigned long rate) ++{ ++ return clk->rate; ++} ++EXPORT_SYMBOL(clk_round_rate); ++ ++int clk_set_rate(struct clk *clk, unsigned long rate) ++{ ++ return -EIO; ++} ++EXPORT_SYMBOL(clk_set_rate); +Index: linux-3.2.46/arch/arm/mach-bcm2708/clock.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/arch/arm/mach-bcm2708/clock.h 2013-07-26 19:31:51.000000000 +0000 +@@ -0,0 +1,24 @@ ++/* ++ * linux/arch/arm/mach-bcm2708/clock.h ++ * ++ * Copyright (C) 2010 Broadcom ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++struct module; ++ ++struct clk { ++ unsigned long rate; ++}; +Index: linux-3.2.46/arch/arm/mach-bcm2708/dma.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/arch/arm/mach-bcm2708/dma.c 2013-07-26 19:31:51.000000000 +0000 +@@ -0,0 +1,397 @@ ++/* ++ * linux/arch/arm/mach-bcm2708/dma.c ++ * ++ * Copyright (C) 2010 Broadcom ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++/*****************************************************************************\ ++ * * ++ * Configuration * ++ * * ++\*****************************************************************************/ ++ ++#define CACHE_LINE_MASK 31 ++#define DRIVER_NAME BCM_DMAMAN_DRIVER_NAME ++#define DEFAULT_DMACHAN_BITMAP 0x10 /* channel 4 only */ ++ ++/* valid only for channels 0 - 14, 15 has its own base address */ ++#define BCM2708_DMA_CHAN(n) ((n)<<8) /* base address */ ++#define BCM2708_DMA_CHANIO(dma_base, n) \ ++ ((void __iomem *)((char *)(dma_base)+BCM2708_DMA_CHAN(n))) ++ ++ ++/*****************************************************************************\ ++ * * ++ * DMA Auxilliary Functions * ++ * * ++\*****************************************************************************/ ++ ++/* A DMA buffer on an arbitrary boundary may separate a cache line into a ++ section inside the DMA buffer and another section outside it. ++ Even if we flush DMA buffers from the cache there is always the chance that ++ during a DMA someone will access the part of a cache line that is outside ++ the DMA buffer - which will then bring in unwelcome data. ++ Without being able to dictate our own buffer pools we must insist that ++ DMA buffers consist of a whole number of cache lines. ++*/ ++ ++extern int ++bcm_sg_suitable_for_dma(struct scatterlist *sg_ptr, int sg_len) ++{ ++ int i; ++ ++ for (i = 0; i < sg_len; i++) { ++ if (sg_ptr[i].offset & CACHE_LINE_MASK || ++ sg_ptr[i].length & CACHE_LINE_MASK) ++ return 0; ++ } ++ ++ return 1; ++} ++EXPORT_SYMBOL_GPL(bcm_sg_suitable_for_dma); ++ ++extern void ++bcm_dma_start(void __iomem *dma_chan_base, dma_addr_t control_block) ++{ ++ dsb(); /* ARM data synchronization (push) operation */ ++ ++ writel(control_block, dma_chan_base + BCM2708_DMA_ADDR); ++ writel(BCM2708_DMA_ACTIVE, dma_chan_base + BCM2708_DMA_CS); ++} ++ ++extern void bcm_dma_wait_idle(void __iomem *dma_chan_base) ++{ ++ dsb(); ++ ++ /* ugly busy wait only option for now */ ++ while (readl(dma_chan_base + BCM2708_DMA_CS) & BCM2708_DMA_ACTIVE); ++} ++ ++EXPORT_SYMBOL_GPL(bcm_dma_start); ++ ++/* Complete an ongoing DMA (assuming its results are to be ignored) ++ Does nothing if there is no DMA in progress. ++ This routine waits for the current AXI transfer to complete before ++ terminating the current DMA. If the current transfer is hung on a DREQ used ++ by an uncooperative peripheral the AXI transfer may never complete. In this ++ case the routine times out and return a non-zero error code. ++ Use of this routine doesn't guarantee that the ongoing or aborted DMA ++ does not produce an interrupt. ++*/ ++extern int ++bcm_dma_abort(void __iomem *dma_chan_base) ++{ ++ unsigned long int cs; ++ int rc = 0; ++ ++ cs = readl(dma_chan_base + BCM2708_DMA_CS); ++ ++ if (BCM2708_DMA_ACTIVE & cs) { ++ long int timeout = 10000; ++ ++ /* write 0 to the active bit - pause the DMA */ ++ writel(0, dma_chan_base + BCM2708_DMA_CS); ++ ++ /* wait for any current AXI transfer to complete */ ++ while (0 != (cs & BCM2708_DMA_ISPAUSED) && --timeout >= 0) ++ cs = readl(dma_chan_base + BCM2708_DMA_CS); ++ ++ if (0 != (cs & BCM2708_DMA_ISPAUSED)) { ++ /* we'll un-pause when we set of our next DMA */ ++ rc = -ETIMEDOUT; ++ ++ } else if (BCM2708_DMA_ACTIVE & cs) { ++ /* terminate the control block chain */ ++ writel(0, dma_chan_base + BCM2708_DMA_NEXTCB); ++ ++ /* abort the whole DMA */ ++ writel(BCM2708_DMA_ABORT | BCM2708_DMA_ACTIVE, ++ dma_chan_base + BCM2708_DMA_CS); ++ } ++ } ++ ++ return rc; ++} ++EXPORT_SYMBOL_GPL(bcm_dma_abort); ++ ++ ++/***************************************************************************** \ ++ * * ++ * DMA Manager Device Methods * ++ * * ++\*****************************************************************************/ ++ ++struct vc_dmaman { ++ void __iomem *dma_base; ++ u32 chan_available; /* bitmap of available channels */ ++ u32 has_feature[BCM_DMA_FEATURE_COUNT]; /* bitmap of feature presence */ ++}; ++ ++static void vc_dmaman_init(struct vc_dmaman *dmaman, void __iomem *dma_base, ++ u32 chans_available) ++{ ++ dmaman->dma_base = dma_base; ++ dmaman->chan_available = chans_available; ++ dmaman->has_feature[BCM_DMA_FEATURE_FAST_ORD] = 0x0c; /* chans 2 & 3 */ ++} ++ ++static int vc_dmaman_chan_alloc(struct vc_dmaman *dmaman, ++ unsigned preferred_feature_set) ++{ ++ u32 chans; ++ int feature; ++ ++ chans = dmaman->chan_available; ++ for (feature = 0; feature < BCM_DMA_FEATURE_COUNT; feature++) ++ /* select the subset of available channels with the desired ++ feature so long as some of the candidate channels have that ++ feature */ ++ if ((preferred_feature_set & (1 << feature)) && ++ (chans & dmaman->has_feature[feature])) ++ chans &= dmaman->has_feature[feature]; ++ ++ if (chans) { ++ int chan = 0; ++ /* return the ordinal of the first channel in the bitmap */ ++ while (chans != 0 && (chans & 1) == 0) { ++ chans >>= 1; ++ chan++; ++ } ++ /* claim the channel */ ++ dmaman->chan_available &= ~(1 << chan); ++ return chan; ++ } else ++ return -ENOMEM; ++} ++ ++static int vc_dmaman_chan_free(struct vc_dmaman *dmaman, int chan) ++{ ++ if (chan < 0) ++ return -EINVAL; ++ else if ((1 << chan) & dmaman->chan_available) ++ return -EIDRM; ++ else { ++ dmaman->chan_available |= (1 << chan); ++ return 0; ++ } ++} ++ ++/*****************************************************************************\ ++ * * ++ * DMA IRQs * ++ * * ++\*****************************************************************************/ ++ ++static unsigned char bcm_dma_irqs[] = { ++ IRQ_DMA0, ++ IRQ_DMA1, ++ IRQ_DMA2, ++ IRQ_DMA3, ++ IRQ_DMA4, ++ IRQ_DMA5, ++ IRQ_DMA6, ++ IRQ_DMA7, ++ IRQ_DMA8, ++ IRQ_DMA9, ++ IRQ_DMA10, ++ IRQ_DMA11, ++ IRQ_DMA12 ++}; ++ ++ ++/***************************************************************************** \ ++ * * ++ * DMA Manager Monitor * ++ * * ++\*****************************************************************************/ ++ ++static struct device *dmaman_dev; /* we assume there's only one! */ ++ ++extern int bcm_dma_chan_alloc(unsigned preferred_feature_set, ++ void __iomem **out_dma_base, int *out_dma_irq) ++{ ++ if (!dmaman_dev) ++ return -ENODEV; ++ else { ++ struct vc_dmaman *dmaman = dev_get_drvdata(dmaman_dev); ++ int rc; ++ ++ device_lock(dmaman_dev); ++ rc = vc_dmaman_chan_alloc(dmaman, preferred_feature_set); ++ if (rc >= 0) { ++ *out_dma_base = BCM2708_DMA_CHANIO(dmaman->dma_base, ++ rc); ++ *out_dma_irq = bcm_dma_irqs[rc]; ++ } ++ device_unlock(dmaman_dev); ++ ++ return rc; ++ } ++} ++EXPORT_SYMBOL_GPL(bcm_dma_chan_alloc); ++ ++extern int bcm_dma_chan_free(int channel) ++{ ++ if (dmaman_dev) { ++ struct vc_dmaman *dmaman = dev_get_drvdata(dmaman_dev); ++ int rc; ++ ++ device_lock(dmaman_dev); ++ rc = vc_dmaman_chan_free(dmaman, channel); ++ device_unlock(dmaman_dev); ++ ++ return rc; ++ } else ++ return -ENODEV; ++} ++EXPORT_SYMBOL_GPL(bcm_dma_chan_free); ++ ++static int dev_dmaman_register(const char *dev_name, struct device *dev) ++{ ++ int rc = dmaman_dev ? -EINVAL : 0; ++ dmaman_dev = dev; ++ return rc; ++} ++ ++static void dev_dmaman_deregister(const char *dev_name, struct device *dev) ++{ ++ dmaman_dev = NULL; ++} ++ ++/*****************************************************************************\ ++ * * ++ * DMA Device * ++ * * ++\*****************************************************************************/ ++ ++static int dmachans = -1; /* module parameter */ ++ ++static int bcm_dmaman_probe(struct platform_device *pdev) ++{ ++ int ret = 0; ++ struct vc_dmaman *dmaman; ++ struct resource *dma_res = NULL; ++ void __iomem *dma_base = NULL; ++ int have_dma_region = 0; ++ ++ dmaman = kzalloc(sizeof(*dmaman), GFP_KERNEL); ++ if (NULL == dmaman) { ++ printk(KERN_ERR DRIVER_NAME ": failed to allocate " ++ "DMA management memory\n"); ++ ret = -ENOMEM; ++ } else { ++ ++ dma_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ if (dma_res == NULL) { ++ printk(KERN_ERR DRIVER_NAME ": failed to obtain memory " ++ "resource\n"); ++ ret = -ENODEV; ++ } else if (!request_mem_region(dma_res->start, ++ resource_size(dma_res), ++ DRIVER_NAME)) { ++ dev_err(&pdev->dev, "cannot obtain DMA region\n"); ++ ret = -EBUSY; ++ } else { ++ have_dma_region = 1; ++ dma_base = ioremap(dma_res->start, ++ resource_size(dma_res)); ++ if (!dma_base) { ++ dev_err(&pdev->dev, "cannot map DMA region\n"); ++ ret = -ENOMEM; ++ } else { ++ /* use module parameter if one was provided */ ++ if (dmachans > 0) ++ vc_dmaman_init(dmaman, dma_base, ++ dmachans); ++ else ++ vc_dmaman_init(dmaman, dma_base, ++ DEFAULT_DMACHAN_BITMAP); ++ ++ platform_set_drvdata(pdev, dmaman); ++ dev_dmaman_register(DRIVER_NAME, &pdev->dev); ++ ++ printk(KERN_INFO DRIVER_NAME ": DMA manager " ++ "at %p\n", dma_base); ++ } ++ } ++ } ++ if (ret != 0) { ++ if (dma_base) ++ iounmap(dma_base); ++ if (dma_res && have_dma_region) ++ release_mem_region(dma_res->start, ++ resource_size(dma_res)); ++ if (dmaman) ++ kfree(dmaman); ++ } ++ return ret; ++} ++ ++static int bcm_dmaman_remove(struct platform_device *pdev) ++{ ++ struct vc_dmaman *dmaman = platform_get_drvdata(pdev); ++ ++ platform_set_drvdata(pdev, NULL); ++ dev_dmaman_deregister(DRIVER_NAME, &pdev->dev); ++ kfree(dmaman); ++ ++ return 0; ++} ++ ++static struct platform_driver bcm_dmaman_driver = { ++ .probe = bcm_dmaman_probe, ++ .remove = bcm_dmaman_remove, ++ ++ .driver = { ++ .name = DRIVER_NAME, ++ .owner = THIS_MODULE, ++ }, ++}; ++ ++/*****************************************************************************\ ++ * * ++ * Driver init/exit * ++ * * ++\*****************************************************************************/ ++ ++static int __init bcm_dmaman_drv_init(void) ++{ ++ int ret; ++ ++ ret = platform_driver_register(&bcm_dmaman_driver); ++ if (ret != 0) { ++ printk(KERN_ERR DRIVER_NAME ": failed to register " ++ "on platform\n"); ++ } ++ ++ return ret; ++} ++ ++static void __exit bcm_dmaman_drv_exit(void) ++{ ++ platform_driver_unregister(&bcm_dmaman_driver); ++} ++ ++module_init(bcm_dmaman_drv_init); ++module_exit(bcm_dmaman_drv_exit); ++ ++module_param(dmachans, int, 0644); ++ ++MODULE_AUTHOR("Gray Girling "); ++MODULE_DESCRIPTION("DMA channel manager driver"); ++MODULE_LICENSE("GPL"); ++ ++MODULE_PARM_DESC(dmachans, "Bitmap of DMA channels available to the ARM"); +Index: linux-3.2.46/arch/arm/mach-bcm2708/include/mach/arm_control.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/arch/arm/mach-bcm2708/include/mach/arm_control.h 2013-07-26 19:31:51.000000000 +0000 +@@ -0,0 +1,419 @@ ++/* ++ * linux/arch/arm/mach-bcm2708/arm_control.h ++ * ++ * Copyright (C) 2010 Broadcom ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++#ifndef __BCM2708_ARM_CONTROL_H ++#define __BCM2708_ARM_CONTROL_H ++ ++/* ++ * Definitions and addresses for the ARM CONTROL logic ++ * This file is manually generated. ++ */ ++ ++#define ARM_BASE 0x7E00B000 ++ ++/* Basic configuration */ ++#define ARM_CONTROL0 HW_REGISTER_RW(ARM_BASE+0x000) ++#define ARM_C0_SIZ128M 0x00000000 ++#define ARM_C0_SIZ256M 0x00000001 ++#define ARM_C0_SIZ512M 0x00000002 ++#define ARM_C0_SIZ1G 0x00000003 ++#define ARM_C0_BRESP0 0x00000000 ++#define ARM_C0_BRESP1 0x00000004 ++#define ARM_C0_BRESP2 0x00000008 ++#define ARM_C0_BOOTHI 0x00000010 ++#define ARM_C0_UNUSED05 0x00000020 /* free */ ++#define ARM_C0_FULLPERI 0x00000040 ++#define ARM_C0_UNUSED78 0x00000180 /* free */ ++#define ARM_C0_JTAGMASK 0x00000E00 ++#define ARM_C0_JTAGOFF 0x00000000 ++#define ARM_C0_JTAGBASH 0x00000800 /* Debug on GPIO off */ ++#define ARM_C0_JTAGGPIO 0x00000C00 /* Debug on GPIO on */ ++#define ARM_C0_APROTMSK 0x0000F000 ++#define ARM_C0_DBG0SYNC 0x00010000 /* VPU0 halt sync */ ++#define ARM_C0_DBG1SYNC 0x00020000 /* VPU1 halt sync */ ++#define ARM_C0_SWDBGREQ 0x00040000 /* HW debug request */ ++#define ARM_C0_PASSHALT 0x00080000 /* ARM halt passed to debugger */ ++#define ARM_C0_PRIO_PER 0x00F00000 /* per priority mask */ ++#define ARM_C0_PRIO_L2 0x0F000000 ++#define ARM_C0_PRIO_UC 0xF0000000 ++ ++#define ARM_C0_APROTPASS 0x0000A000 /* Translate 1:1 */ ++#define ARM_C0_APROTUSER 0x00000000 /* Only user mode */ ++#define ARM_C0_APROTSYST 0x0000F000 /* Only system mode */ ++ ++ ++#define ARM_CONTROL1 HW_REGISTER_RW(ARM_BASE+0x440) ++#define ARM_C1_TIMER 0x00000001 /* re-route timer IRQ to VC */ ++#define ARM_C1_MAIL 0x00000002 /* re-route Mail IRQ to VC */ ++#define ARM_C1_BELL0 0x00000004 /* re-route Doorbell 0 to VC */ ++#define ARM_C1_BELL1 0x00000008 /* re-route Doorbell 1 to VC */ ++#define ARM_C1_PERSON 0x00000100 /* peripherals on */ ++#define ARM_C1_REQSTOP 0x00000200 /* ASYNC bridge request stop */ ++ ++#define ARM_STATUS HW_REGISTER_RW(ARM_BASE+0x444) ++#define ARM_S_ACKSTOP 0x80000000 /* Bridge stopped */ ++#define ARM_S_READPEND 0x000003FF /* pending reads counter */ ++#define ARM_S_WRITPEND 0x000FFC00 /* pending writes counter */ ++ ++#define ARM_ERRHALT HW_REGISTER_RW(ARM_BASE+0x448) ++#define ARM_EH_PERIBURST 0x00000001 /* Burst write seen on peri bus */ ++#define ARM_EH_ILLADDRS1 0x00000002 /* Address bits 25-27 error */ ++#define ARM_EH_ILLADDRS2 0x00000004 /* Address bits 31-28 error */ ++#define ARM_EH_VPU0HALT 0x00000008 /* VPU0 halted & in debug mode */ ++#define ARM_EH_VPU1HALT 0x00000010 /* VPU1 halted & in debug mode */ ++#define ARM_EH_ARMHALT 0x00000020 /* ARM in halted debug mode */ ++ ++#define ARM_ID_SECURE HW_REGISTER_RW(ARM_BASE+0x00C) ++#define ARM_ID HW_REGISTER_RW(ARM_BASE+0x44C) ++#define ARM_IDVAL 0x364D5241 ++ ++/* Translation memory */ ++#define ARM_TRANSLATE HW_REGISTER_RW(ARM_BASE+0x100) ++/* 32 locations: 0x100.. 0x17F */ ++/* 32 spare means we CAN go to 64 pages.... */ ++ ++ ++/* Interrupts */ ++#define ARM_IRQ_PEND0 HW_REGISTER_RW(ARM_BASE+0x200) /* Top IRQ bits */ ++#define ARM_I0_TIMER 0x00000001 /* timer IRQ */ ++#define ARM_I0_MAIL 0x00000002 /* Mail IRQ */ ++#define ARM_I0_BELL0 0x00000004 /* Doorbell 0 */ ++#define ARM_I0_BELL1 0x00000008 /* Doorbell 1 */ ++#define ARM_I0_BANK1 0x00000100 /* Bank1 IRQ */ ++#define ARM_I0_BANK2 0x00000200 /* Bank2 IRQ */ ++ ++#define ARM_IRQ_PEND1 HW_REGISTER_RW(ARM_BASE+0x204) /* All bank1 IRQ bits */ ++/* todo: all I1_interrupt sources */ ++#define ARM_IRQ_PEND2 HW_REGISTER_RW(ARM_BASE+0x208) /* All bank2 IRQ bits */ ++/* todo: all I2_interrupt sources */ ++ ++#define ARM_IRQ_FAST HW_REGISTER_RW(ARM_BASE+0x20C) /* FIQ control */ ++#define ARM_IF_INDEX 0x0000007F /* FIQ select */ ++#define ARM_IF_ENABLE 0x00000080 /* FIQ enable */ ++#define ARM_IF_VCMASK 0x0000003F /* FIQ = (index from VC source) */ ++#define ARM_IF_TIMER 0x00000040 /* FIQ = ARM timer */ ++#define ARM_IF_MAIL 0x00000041 /* FIQ = ARM Mail */ ++#define ARM_IF_BELL0 0x00000042 /* FIQ = ARM Doorbell 0 */ ++#define ARM_IF_BELL1 0x00000043 /* FIQ = ARM Doorbell 1 */ ++#define ARM_IF_VP0HALT 0x00000044 /* FIQ = VPU0 Halt seen */ ++#define ARM_IF_VP1HALT 0x00000045 /* FIQ = VPU1 Halt seen */ ++#define ARM_IF_ILLEGAL 0x00000046 /* FIQ = Illegal access seen */ ++ ++#define ARM_IRQ_ENBL1 HW_REGISTER_RW(ARM_BASE+0x210) /* Bank1 enable bits */ ++#define ARM_IRQ_ENBL2 HW_REGISTER_RW(ARM_BASE+0x214) /* Bank2 enable bits */ ++#define ARM_IRQ_ENBL3 HW_REGISTER_RW(ARM_BASE+0x218) /* ARM irqs enable bits */ ++#define ARM_IRQ_DIBL1 HW_REGISTER_RW(ARM_BASE+0x21C) /* Bank1 disable bits */ ++#define ARM_IRQ_DIBL2 HW_REGISTER_RW(ARM_BASE+0x220) /* Bank2 disable bits */ ++#define ARM_IRQ_DIBL3 HW_REGISTER_RW(ARM_BASE+0x224) /* ARM irqs disable bits */ ++#define ARM_IE_TIMER 0x00000001 /* Timer IRQ */ ++#define ARM_IE_MAIL 0x00000002 /* Mail IRQ */ ++#define ARM_IE_BELL0 0x00000004 /* Doorbell 0 */ ++#define ARM_IE_BELL1 0x00000008 /* Doorbell 1 */ ++#define ARM_IE_VP0HALT 0x00000010 /* VPU0 Halt */ ++#define ARM_IE_VP1HALT 0x00000020 /* VPU1 Halt */ ++#define ARM_IE_ILLEGAL 0x00000040 /* Illegal access seen */ ++ ++/* Timer */ ++/* For reg. fields see sp804 spec. */ ++#define ARM_T_LOAD HW_REGISTER_RW(ARM_BASE+0x400) ++#define ARM_T_VALUE HW_REGISTER_RW(ARM_BASE+0x404) ++#define ARM_T_CONTROL HW_REGISTER_RW(ARM_BASE+0x408) ++#define ARM_T_IRQCNTL HW_REGISTER_RW(ARM_BASE+0x40C) ++#define ARM_T_RAWIRQ HW_REGISTER_RW(ARM_BASE+0x410) ++#define ARM_T_MSKIRQ HW_REGISTER_RW(ARM_BASE+0x414) ++#define ARM_T_RELOAD HW_REGISTER_RW(ARM_BASE+0x418) ++#define ARM_T_PREDIV HW_REGISTER_RW(ARM_BASE+0x41c) ++#define ARM_T_FREECNT HW_REGISTER_RW(ARM_BASE+0x420) ++ ++#define TIMER_CTRL_ONESHOT (1 << 0) ++#define TIMER_CTRL_32BIT (1 << 1) ++#define TIMER_CTRL_DIV1 (0 << 2) ++#define TIMER_CTRL_DIV16 (1 << 2) ++#define TIMER_CTRL_DIV256 (2 << 2) ++#define TIMER_CTRL_IE (1 << 5) ++#define TIMER_CTRL_PERIODIC (1 << 6) ++#define TIMER_CTRL_ENABLE (1 << 7) ++#define TIMER_CTRL_DBGHALT (1 << 8) ++#define TIMER_CTRL_ENAFREE (1 << 9) ++#define TIMER_CTRL_FREEDIV_SHIFT 16) ++#define TIMER_CTRL_FREEDIV_MASK 0xff ++ ++/* Semaphores, Doorbells, Mailboxes */ ++#define ARM_SBM_OWN0 (ARM_BASE+0x800) ++#define ARM_SBM_OWN1 (ARM_BASE+0x900) ++#define ARM_SBM_OWN2 (ARM_BASE+0xA00) ++#define ARM_SBM_OWN3 (ARM_BASE+0xB00) ++ ++/* MAILBOXES ++ * Register flags are common across all ++ * owner registers. See end of this section ++ * ++ * Semaphores, Doorbells, Mailboxes Owner 0 ++ * ++ */ ++ ++#define ARM_0_SEMS HW_REGISTER_RW(ARM_SBM_OWN0+0x00) ++#define ARM_0_SEM0 HW_REGISTER_RW(ARM_SBM_OWN0+0x00) ++#define ARM_0_SEM1 HW_REGISTER_RW(ARM_SBM_OWN0+0x04) ++#define ARM_0_SEM2 HW_REGISTER_RW(ARM_SBM_OWN0+0x08) ++#define ARM_0_SEM3 HW_REGISTER_RW(ARM_SBM_OWN0+0x0C) ++#define ARM_0_SEM4 HW_REGISTER_RW(ARM_SBM_OWN0+0x10) ++#define ARM_0_SEM5 HW_REGISTER_RW(ARM_SBM_OWN0+0x14) ++#define ARM_0_SEM6 HW_REGISTER_RW(ARM_SBM_OWN0+0x18) ++#define ARM_0_SEM7 HW_REGISTER_RW(ARM_SBM_OWN0+0x1C) ++#define ARM_0_BELL0 HW_REGISTER_RW(ARM_SBM_OWN0+0x40) ++#define ARM_0_BELL1 HW_REGISTER_RW(ARM_SBM_OWN0+0x44) ++#define ARM_0_BELL2 HW_REGISTER_RW(ARM_SBM_OWN0+0x48) ++#define ARM_0_BELL3 HW_REGISTER_RW(ARM_SBM_OWN0+0x4C) ++/* MAILBOX 0 access in Owner 0 area */ ++/* Some addresses should ONLY be used by owner 0 */ ++#define ARM_0_MAIL0_WRT HW_REGISTER_RW(ARM_SBM_OWN0+0x80) /* .. 0x8C (4 locations) */ ++#define ARM_0_MAIL0_RD HW_REGISTER_RW(ARM_SBM_OWN0+0x80) /* .. 0x8C (4 locations) Normal read */ ++#define ARM_0_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN0+0x90) /* none-pop read */ ++#define ARM_0_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN0+0x94) /* Sender read (only LS 2 bits) */ ++#define ARM_0_MAIL0_STA HW_REGISTER_RW(ARM_SBM_OWN0+0x98) /* Status read */ ++#define ARM_0_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN0+0x9C) /* Config read/write */ ++/* MAILBOX 1 access in Owner 0 area */ ++/* Owner 0 should only WRITE to this mailbox */ ++#define ARM_0_MAIL1_WRT HW_REGISTER_RW(ARM_SBM_OWN0+0xA0) /* .. 0xAC (4 locations) */ ++/*#define ARM_0_MAIL1_RD HW_REGISTER_RW(ARM_SBM_OWN0+0xA0) */ /* DO NOT USE THIS !!!!! */ ++/*#define ARM_0_MAIL1_POL HW_REGISTER_RW(ARM_SBM_OWN0+0xB0) */ /* DO NOT USE THIS !!!!! */ ++/*#define ARM_0_MAIL1_SND HW_REGISTER_RW(ARM_SBM_OWN0+0xB4) */ /* DO NOT USE THIS !!!!! */ ++#define ARM_0_MAIL1_STA HW_REGISTER_RW(ARM_SBM_OWN0+0xB8) /* Status read */ ++/*#define ARM_0_MAIL1_CNF HW_REGISTER_RW(ARM_SBM_OWN0+0xBC) */ /* DO NOT USE THIS !!!!! */ ++/* General SEM, BELL, MAIL config/status */ ++#define ARM_0_SEMCLRDBG HW_REGISTER_RW(ARM_SBM_OWN0+0xE0) /* semaphore clear/debug register */ ++#define ARM_0_BELLCLRDBG HW_REGISTER_RW(ARM_SBM_OWN0+0xE4) /* Doorbells clear/debug register */ ++#define ARM_0_ALL_IRQS HW_REGISTER_RW(ARM_SBM_OWN0+0xF8) /* ALL interrupts */ ++#define ARM_0_MY_IRQS HW_REGISTER_RW(ARM_SBM_OWN0+0xFC) /* IRQS pending for owner 0 */ ++ ++/* Semaphores, Doorbells, Mailboxes Owner 1 */ ++#define ARM_1_SEMS HW_REGISTER_RW(ARM_SBM_OWN1+0x00) ++#define ARM_1_SEM0 HW_REGISTER_RW(ARM_SBM_OWN1+0x00) ++#define ARM_1_SEM1 HW_REGISTER_RW(ARM_SBM_OWN1+0x04) ++#define ARM_1_SEM2 HW_REGISTER_RW(ARM_SBM_OWN1+0x08) ++#define ARM_1_SEM3 HW_REGISTER_RW(ARM_SBM_OWN1+0x0C) ++#define ARM_1_SEM4 HW_REGISTER_RW(ARM_SBM_OWN1+0x10) ++#define ARM_1_SEM5 HW_REGISTER_RW(ARM_SBM_OWN1+0x14) ++#define ARM_1_SEM6 HW_REGISTER_RW(ARM_SBM_OWN1+0x18) ++#define ARM_1_SEM7 HW_REGISTER_RW(ARM_SBM_OWN1+0x1C) ++#define ARM_1_BELL0 HW_REGISTER_RW(ARM_SBM_OWN1+0x40) ++#define ARM_1_BELL1 HW_REGISTER_RW(ARM_SBM_OWN1+0x44) ++#define ARM_1_BELL2 HW_REGISTER_RW(ARM_SBM_OWN1+0x48) ++#define ARM_1_BELL3 HW_REGISTER_RW(ARM_SBM_OWN1+0x4C) ++/* MAILBOX 0 access in Owner 0 area */ ++/* Owner 1 should only WRITE to this mailbox */ ++#define ARM_1_MAIL0_WRT HW_REGISTER_RW(ARM_SBM_OWN1+0x80) /* .. 0x8C (4 locations) */ ++/*#define ARM_1_MAIL0_RD HW_REGISTER_RW(ARM_SBM_OWN1+0x80) */ /* DO NOT USE THIS !!!!! */ ++/*#define ARM_1_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN1+0x90) */ /* DO NOT USE THIS !!!!! */ ++/*#define ARM_1_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN1+0x94) */ /* DO NOT USE THIS !!!!! */ ++#define ARM_1_MAIL0_STA HW_REGISTER_RW(ARM_SBM_OWN1+0x98) /* Status read */ ++/*#define ARM_1_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN1+0x9C) */ /* DO NOT USE THIS !!!!! */ ++/* MAILBOX 1 access in Owner 0 area */ ++#define ARM_1_MAIL1_WRT HW_REGISTER_RW(ARM_SBM_OWN1+0xA0) /* .. 0xAC (4 locations) */ ++#define ARM_1_MAIL1_RD HW_REGISTER_RW(ARM_SBM_OWN1+0xA0) /* .. 0xAC (4 locations) Normal read */ ++#define ARM_1_MAIL1_POL HW_REGISTER_RW(ARM_SBM_OWN1+0xB0) /* none-pop read */ ++#define ARM_1_MAIL1_SND HW_REGISTER_RW(ARM_SBM_OWN1+0xB4) /* Sender read (only LS 2 bits) */ ++#define ARM_1_MAIL1_STA HW_REGISTER_RW(ARM_SBM_OWN1+0xB8) /* Status read */ ++#define ARM_1_MAIL1_CNF HW_REGISTER_RW(ARM_SBM_OWN1+0xBC) ++/* General SEM, BELL, MAIL config/status */ ++#define ARM_1_SEMCLRDBG HW_REGISTER_RW(ARM_SBM_OWN1+0xE0) /* semaphore clear/debug register */ ++#define ARM_1_BELLCLRDBG HW_REGISTER_RW(ARM_SBM_OWN1+0xE4) /* Doorbells clear/debug register */ ++#define ARM_1_MY_IRQS HW_REGISTER_RW(ARM_SBM_OWN1+0xFC) /* IRQS pending for owner 1 */ ++#define ARM_1_ALL_IRQS HW_REGISTER_RW(ARM_SBM_OWN1+0xF8) /* ALL interrupts */ ++ ++/* Semaphores, Doorbells, Mailboxes Owner 2 */ ++#define ARM_2_SEMS HW_REGISTER_RW(ARM_SBM_OWN2+0x00) ++#define ARM_2_SEM0 HW_REGISTER_RW(ARM_SBM_OWN2+0x00) ++#define ARM_2_SEM1 HW_REGISTER_RW(ARM_SBM_OWN2+0x04) ++#define ARM_2_SEM2 HW_REGISTER_RW(ARM_SBM_OWN2+0x08) ++#define ARM_2_SEM3 HW_REGISTER_RW(ARM_SBM_OWN2+0x0C) ++#define ARM_2_SEM4 HW_REGISTER_RW(ARM_SBM_OWN2+0x10) ++#define ARM_2_SEM5 HW_REGISTER_RW(ARM_SBM_OWN2+0x14) ++#define ARM_2_SEM6 HW_REGISTER_RW(ARM_SBM_OWN2+0x18) ++#define ARM_2_SEM7 HW_REGISTER_RW(ARM_SBM_OWN2+0x1C) ++#define ARM_2_BELL0 HW_REGISTER_RW(ARM_SBM_OWN2+0x40) ++#define ARM_2_BELL1 HW_REGISTER_RW(ARM_SBM_OWN2+0x44) ++#define ARM_2_BELL2 HW_REGISTER_RW(ARM_SBM_OWN2+0x48) ++#define ARM_2_BELL3 HW_REGISTER_RW(ARM_SBM_OWN2+0x4C) ++/* MAILBOX 0 access in Owner 2 area */ ++/* Owner 2 should only WRITE to this mailbox */ ++#define ARM_2_MAIL0_WRT HW_REGISTER_RW(ARM_SBM_OWN2+0x80) /* .. 0x8C (4 locations) */ ++/*#define ARM_2_MAIL0_RD HW_REGISTER_RW(ARM_SBM_OWN2+0x80) */ /* DO NOT USE THIS !!!!! */ ++/*#define ARM_2_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN2+0x90) */ /* DO NOT USE THIS !!!!! */ ++/*#define ARM_2_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN2+0x94) */ /* DO NOT USE THIS !!!!! */ ++#define ARM_2_MAIL0_STA HW_REGISTER_RW(ARM_SBM_OWN2+0x98) /* Status read */ ++/*#define ARM_2_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN2+0x9C) */ /* DO NOT USE THIS !!!!! */ ++/* MAILBOX 1 access in Owner 2 area */ ++/* Owner 2 should only WRITE to this mailbox */ ++#define ARM_2_MAIL1_WRT HW_REGISTER_RW(ARM_SBM_OWN2+0xA0) /* .. 0xAC (4 locations) */ ++/*#define ARM_2_MAIL1_RD HW_REGISTER_RW(ARM_SBM_OWN2+0xA0) */ /* DO NOT USE THIS !!!!! */ ++/*#define ARM_2_MAIL1_POL HW_REGISTER_RW(ARM_SBM_OWN2+0xB0) */ /* DO NOT USE THIS !!!!! */ ++/*#define ARM_2_MAIL1_SND HW_REGISTER_RW(ARM_SBM_OWN2+0xB4) */ /* DO NOT USE THIS !!!!! */ ++#define ARM_2_MAIL1_STA HW_REGISTER_RW(ARM_SBM_OWN2+0xB8) /* Status read */ ++/*#define ARM_2_MAIL1_CNF HW_REGISTER_RW(ARM_SBM_OWN2+0xBC) */ /* DO NOT USE THIS !!!!! */ ++/* General SEM, BELL, MAIL config/status */ ++#define ARM_2_SEMCLRDBG HW_REGISTER_RW(ARM_SBM_OWN2+0xE0) /* semaphore clear/debug register */ ++#define ARM_2_BELLCLRDBG HW_REGISTER_RW(ARM_SBM_OWN2+0xE4) /* Doorbells clear/debug register */ ++#define ARM_2_MY_IRQS HW_REGISTER_RW(ARM_SBM_OWN2+0xFC) /* IRQS pending for owner 2 */ ++#define ARM_2_ALL_IRQS HW_REGISTER_RW(ARM_SBM_OWN2+0xF8) /* ALL interrupts */ ++ ++/* Semaphores, Doorbells, Mailboxes Owner 3 */ ++#define ARM_3_SEMS HW_REGISTER_RW(ARM_SBM_OWN3+0x00) ++#define ARM_3_SEM0 HW_REGISTER_RW(ARM_SBM_OWN3+0x00) ++#define ARM_3_SEM1 HW_REGISTER_RW(ARM_SBM_OWN3+0x04) ++#define ARM_3_SEM2 HW_REGISTER_RW(ARM_SBM_OWN3+0x08) ++#define ARM_3_SEM3 HW_REGISTER_RW(ARM_SBM_OWN3+0x0C) ++#define ARM_3_SEM4 HW_REGISTER_RW(ARM_SBM_OWN3+0x10) ++#define ARM_3_SEM5 HW_REGISTER_RW(ARM_SBM_OWN3+0x14) ++#define ARM_3_SEM6 HW_REGISTER_RW(ARM_SBM_OWN3+0x18) ++#define ARM_3_SEM7 HW_REGISTER_RW(ARM_SBM_OWN3+0x1C) ++#define ARM_3_BELL0 HW_REGISTER_RW(ARM_SBM_OWN3+0x40) ++#define ARM_3_BELL1 HW_REGISTER_RW(ARM_SBM_OWN3+0x44) ++#define ARM_3_BELL2 HW_REGISTER_RW(ARM_SBM_OWN3+0x48) ++#define ARM_3_BELL3 HW_REGISTER_RW(ARM_SBM_OWN3+0x4C) ++/* MAILBOX 0 access in Owner 3 area */ ++/* Owner 3 should only WRITE to this mailbox */ ++#define ARM_3_MAIL0_WRT HW_REGISTER_RW(ARM_SBM_OWN3+0x80) /* .. 0x8C (4 locations) */ ++/*#define ARM_3_MAIL0_RD HW_REGISTER_RW(ARM_SBM_OWN3+0x80) */ /* DO NOT USE THIS !!!!! */ ++/*#define ARM_3_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN3+0x90) */ /* DO NOT USE THIS !!!!! */ ++/*#define ARM_3_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN3+0x94) */ /* DO NOT USE THIS !!!!! */ ++#define ARM_3_MAIL0_STA HW_REGISTER_RW(ARM_SBM_OWN3+0x98) /* Status read */ ++/*#define ARM_3_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN3+0x9C) */ /* DO NOT USE THIS !!!!! */ ++/* MAILBOX 1 access in Owner 3 area */ ++/* Owner 3 should only WRITE to this mailbox */ ++#define ARM_3_MAIL1_WRT HW_REGISTER_RW(ARM_SBM_OWN3+0xA0) /* .. 0xAC (4 locations) */ ++/*#define ARM_3_MAIL1_RD HW_REGISTER_RW(ARM_SBM_OWN3+0xA0) */ /* DO NOT USE THIS !!!!! */ ++/*#define ARM_3_MAIL1_POL HW_REGISTER_RW(ARM_SBM_OWN3+0xB0) */ /* DO NOT USE THIS !!!!! */ ++/*#define ARM_3_MAIL1_SND HW_REGISTER_RW(ARM_SBM_OWN3+0xB4) */ /* DO NOT USE THIS !!!!! */ ++#define ARM_3_MAIL1_STA HW_REGISTER_RW(ARM_SBM_OWN3+0xB8) /* Status read */ ++/*#define ARM_3_MAIL1_CNF HW_REGISTER_RW(ARM_SBM_OWN3+0xBC) */ /* DO NOT USE THIS !!!!! */ ++/* General SEM, BELL, MAIL config/status */ ++#define ARM_3_SEMCLRDBG HW_REGISTER_RW(ARM_SBM_OWN3+0xE0) /* semaphore clear/debug register */ ++#define ARM_3_BELLCLRDBG HW_REGISTER_RW(ARM_SBM_OWN3+0xE4) /* Doorbells clear/debug register */ ++#define ARM_3_MY_IRQS HW_REGISTER_RW(ARM_SBM_OWN3+0xFC) /* IRQS pending for owner 3 */ ++#define ARM_3_ALL_IRQS HW_REGISTER_RW(ARM_SBM_OWN3+0xF8) /* ALL interrupts */ ++ ++ ++ ++/* Mailbox flags. Valid for all owners */ ++ ++/* Mailbox status register (...0x98) */ ++#define ARM_MS_FULL 0x80000000 ++#define ARM_MS_EMPTY 0x40000000 ++#define ARM_MS_LEVEL 0x400000FF /* Max. value depdnds on mailbox depth parameter */ ++ ++/* MAILBOX config/status register (...0x9C) */ ++/* ANY write to this register clears the error bits! */ ++#define ARM_MC_IHAVEDATAIRQEN 0x00000001 /* mailbox irq enable: has data */ ++#define ARM_MC_IHAVESPACEIRQEN 0x00000002 /* mailbox irq enable: has space */ ++#define ARM_MC_OPPISEMPTYIRQEN 0x00000004 /* mailbox irq enable: Opp. is empty */ ++#define ARM_MC_MAIL_CLEAR 0x00000008 /* mailbox clear write 1, then 0 */ ++#define ARM_MC_IHAVEDATAIRQPEND 0x00000010 /* mailbox irq pending: has space */ ++#define ARM_MC_IHAVESPACEIRQPEND 0x00000020 /* mailbox irq pending: Opp. is empty */ ++#define ARM_MC_OPPISEMPTYIRQPEND 0x00000040 /* mailbox irq pending */ ++/* Bit 7 is unused */ ++#define ARM_MC_ERRNOOWN 0x00000100 /* error : none owner read from mailbox */ ++#define ARM_MC_ERROVERFLW 0x00000200 /* error : write to fill mailbox */ ++#define ARM_MC_ERRUNDRFLW 0x00000400 /* error : read from empty mailbox */ ++ ++/* Semaphore clear/debug register (...0xE0) */ ++#define ARM_SD_OWN0 0x00000003 /* Owner of sem 0 */ ++#define ARM_SD_OWN1 0x0000000C /* Owner of sem 1 */ ++#define ARM_SD_OWN2 0x00000030 /* Owner of sem 2 */ ++#define ARM_SD_OWN3 0x000000C0 /* Owner of sem 3 */ ++#define ARM_SD_OWN4 0x00000300 /* Owner of sem 4 */ ++#define ARM_SD_OWN5 0x00000C00 /* Owner of sem 5 */ ++#define ARM_SD_OWN6 0x00003000 /* Owner of sem 6 */ ++#define ARM_SD_OWN7 0x0000C000 /* Owner of sem 7 */ ++#define ARM_SD_SEM0 0x00010000 /* Status of sem 0 */ ++#define ARM_SD_SEM1 0x00020000 /* Status of sem 1 */ ++#define ARM_SD_SEM2 0x00040000 /* Status of sem 2 */ ++#define ARM_SD_SEM3 0x00080000 /* Status of sem 3 */ ++#define ARM_SD_SEM4 0x00100000 /* Status of sem 4 */ ++#define ARM_SD_SEM5 0x00200000 /* Status of sem 5 */ ++#define ARM_SD_SEM6 0x00400000 /* Status of sem 6 */ ++#define ARM_SD_SEM7 0x00800000 /* Status of sem 7 */ ++ ++/* Doorbells clear/debug register (...0xE4) */ ++#define ARM_BD_OWN0 0x00000003 /* Owner of doorbell 0 */ ++#define ARM_BD_OWN1 0x0000000C /* Owner of doorbell 1 */ ++#define ARM_BD_OWN2 0x00000030 /* Owner of doorbell 2 */ ++#define ARM_BD_OWN3 0x000000C0 /* Owner of doorbell 3 */ ++#define ARM_BD_BELL0 0x00000100 /* Status of doorbell 0 */ ++#define ARM_BD_BELL1 0x00000200 /* Status of doorbell 1 */ ++#define ARM_BD_BELL2 0x00000400 /* Status of doorbell 2 */ ++#define ARM_BD_BELL3 0x00000800 /* Status of doorbell 3 */ ++ ++/* MY IRQS register (...0xF8) */ ++#define ARM_MYIRQ_BELL 0x00000001 /* This owner has a doorbell IRQ */ ++#define ARM_MYIRQ_MAIL 0x00000002 /* This owner has a mailbox IRQ */ ++ ++/* ALL IRQS register (...0xF8) */ ++#define ARM_AIS_BELL0 0x00000001 /* Doorbell 0 IRQ pending */ ++#define ARM_AIS_BELL1 0x00000002 /* Doorbell 1 IRQ pending */ ++#define ARM_AIS_BELL2 0x00000004 /* Doorbell 2 IRQ pending */ ++#define ARM_AIS_BELL3 0x00000008 /* Doorbell 3 IRQ pending */ ++#define ARM_AIS0_HAVEDATA 0x00000010 /* MAIL 0 has data IRQ pending */ ++#define ARM_AIS0_HAVESPAC 0x00000020 /* MAIL 0 has space IRQ pending */ ++#define ARM_AIS0_OPPEMPTY 0x00000040 /* MAIL 0 opposite is empty IRQ */ ++#define ARM_AIS1_HAVEDATA 0x00000080 /* MAIL 1 has data IRQ pending */ ++#define ARM_AIS1_HAVESPAC 0x00000100 /* MAIL 1 has space IRQ pending */ ++#define ARM_AIS1_OPPEMPTY 0x00000200 /* MAIL 1 opposite is empty IRQ */ ++/* Note that bell-0, bell-1 and MAIL0 IRQ go only to the ARM */ ++/* Whilst that bell-2, bell-3 and MAIL1 IRQ go only to the VC */ ++/* */ ++/* ARM JTAG BASH */ ++/* */ ++#define AJB_BASE 0x7e2000c0 ++ ++#define AJBCONF HW_REGISTER_RW(AJB_BASE+0x00) ++#define AJB_BITS0 0x000000 ++#define AJB_BITS4 0x000004 ++#define AJB_BITS8 0x000008 ++#define AJB_BITS12 0x00000C ++#define AJB_BITS16 0x000010 ++#define AJB_BITS20 0x000014 ++#define AJB_BITS24 0x000018 ++#define AJB_BITS28 0x00001C ++#define AJB_BITS32 0x000020 ++#define AJB_BITS34 0x000022 ++#define AJB_OUT_MS 0x000040 ++#define AJB_OUT_LS 0x000000 ++#define AJB_INV_CLK 0x000080 ++#define AJB_D0_RISE 0x000100 ++#define AJB_D0_FALL 0x000000 ++#define AJB_D1_RISE 0x000200 ++#define AJB_D1_FALL 0x000000 ++#define AJB_IN_RISE 0x000400 ++#define AJB_IN_FALL 0x000000 ++#define AJB_ENABLE 0x000800 ++#define AJB_HOLD0 0x000000 ++#define AJB_HOLD1 0x001000 ++#define AJB_HOLD2 0x002000 ++#define AJB_HOLD3 0x003000 ++#define AJB_RESETN 0x004000 ++#define AJB_CLKSHFT 16 ++#define AJB_BUSY 0x80000000 ++#define AJBTMS HW_REGISTER_RW(AJB_BASE+0x04) ++#define AJBTDI HW_REGISTER_RW(AJB_BASE+0x08) ++#define AJBTDO HW_REGISTER_RW(AJB_BASE+0x0c) ++ ++#endif +Index: linux-3.2.46/arch/arm/mach-bcm2708/include/mach/arm_power.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/arch/arm/mach-bcm2708/include/mach/arm_power.h 2013-07-26 19:31:51.000000000 +0000 +@@ -0,0 +1,60 @@ ++/* ++ * linux/arch/arm/mach-bcm2708/include/mach/arm_power.h ++ * ++ * Copyright (C) 2010 Broadcom ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++#ifndef _ARM_POWER_H ++#define _ARM_POWER_H ++ ++/* Use meaningful names on each side */ ++#ifdef __VIDEOCORE__ ++#define PREFIX(x) ARM_##x ++#else ++#define PREFIX(x) BCM_##x ++#endif ++ ++enum { ++ PREFIX(POWER_SDCARD_BIT), ++ PREFIX(POWER_UART_BIT), ++ PREFIX(POWER_MINIUART_BIT), ++ PREFIX(POWER_USB_BIT), ++ PREFIX(POWER_I2C0_BIT), ++ PREFIX(POWER_I2C1_BIT), ++ PREFIX(POWER_I2C2_BIT), ++ PREFIX(POWER_SPI_BIT), ++ PREFIX(POWER_CCP2TX_BIT), ++ ++ PREFIX(POWER_MAX) ++}; ++ ++enum { ++ PREFIX(POWER_SDCARD) = (1 << PREFIX(POWER_SDCARD_BIT)), ++ PREFIX(POWER_UART) = (1 << PREFIX(POWER_UART_BIT)), ++ PREFIX(POWER_MINIUART) = (1 << PREFIX(POWER_MINIUART_BIT)), ++ PREFIX(POWER_USB) = (1 << PREFIX(POWER_USB_BIT)), ++ PREFIX(POWER_I2C0) = (1 << PREFIX(POWER_I2C0_BIT)), ++ PREFIX(POWER_I2C1_MASK) = (1 << PREFIX(POWER_I2C1_BIT)), ++ PREFIX(POWER_I2C2_MASK) = (1 << PREFIX(POWER_I2C2_BIT)), ++ PREFIX(POWER_SPI_MASK) = (1 << PREFIX(POWER_SPI_BIT)), ++ PREFIX(POWER_CCP2TX_MASK) = (1 << PREFIX(POWER_CCP2TX_BIT)), ++ ++ PREFIX(POWER_MASK) = (1 << PREFIX(POWER_MAX)) - 1, ++ PREFIX(POWER_NONE) = 0 ++}; ++ ++#endif +Index: linux-3.2.46/arch/arm/mach-bcm2708/include/mach/clkdev.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/arch/arm/mach-bcm2708/include/mach/clkdev.h 2013-07-26 19:31:51.000000000 +0000 +@@ -0,0 +1,7 @@ ++#ifndef __ASM_MACH_CLKDEV_H ++#define __ASM_MACH_CLKDEV_H ++ ++#define __clk_get(clk) ({ 1; }) ++#define __clk_put(clk) do { } while (0) ++ ++#endif +Index: linux-3.2.46/arch/arm/mach-bcm2708/include/mach/debug-macro.S +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/arch/arm/mach-bcm2708/include/mach/debug-macro.S 2013-07-26 19:31:51.000000000 +0000 +@@ -0,0 +1,24 @@ ++/* arch/arm/mach-bcm2708/include/mach/debug-macro.S ++ * ++ * Debugging macro include header ++ * ++ * Copyright (C) 2010 Broadcom ++ * Copyright (C) 1994-1999 Russell King ++ * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++*/ ++ ++ .macro addruart, rx, tmp ++ mrc p15, 0, \rx, c1, c0 ++ tst \rx, #1 @ MMU enabled? ++ moveq \rx, #0x08000000 ++ movne \rx, #0xf8000000 @ virtual base ++ orr \rx, \rx, #0x00200000 ++ orr \rx, \rx, #0x00001000 ++ .endm ++ ++#include +Index: linux-3.2.46/arch/arm/mach-bcm2708/include/mach/dma.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/arch/arm/mach-bcm2708/include/mach/dma.h 2013-07-26 19:31:51.000000000 +0000 +@@ -0,0 +1,84 @@ ++/* ++ * linux/arch/arm/mach-bcm2708/include/mach/dma.h ++ * ++ * Copyright (C) 2010 Broadcom ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++ ++#ifndef _MACH_BCM2708_DMA_H ++#define _MACH_BCM2708_DMA_H ++ ++#define BCM_DMAMAN_DRIVER_NAME "bcm2708_dma" ++ ++/* DMA CS Control and Status bits */ ++#define BCM2708_DMA_ACTIVE (1 << 0) ++#define BCM2708_DMA_INT (1 << 2) ++#define BCM2708_DMA_ISPAUSED (1 << 4) /* Pause requested or not active */ ++#define BCM2708_DMA_ISHELD (1 << 5) /* Is held by DREQ flow control */ ++#define BCM2708_DMA_ERR (1 << 8) ++#define BCM2708_DMA_ABORT (1 << 30) /* stop current CB, go to next, WO */ ++#define BCM2708_DMA_RESET (1 << 31) /* WO, self clearing */ ++ ++/* DMA control block "info" field bits */ ++#define BCM2708_DMA_INT_EN (1 << 0) ++#define BCM2708_DMA_TDMODE (1 << 1) ++#define BCM2708_DMA_WAIT_RESP (1 << 3) ++#define BCM2708_DMA_D_INC (1 << 4) ++#define BCM2708_DMA_D_WIDTH (1 << 5) ++#define BCM2708_DMA_D_DREQ (1 << 6) ++#define BCM2708_DMA_S_INC (1 << 8) ++#define BCM2708_DMA_S_WIDTH (1 << 9) ++#define BCM2708_DMA_S_DREQ (1 << 10) ++ ++#define BCM2708_DMA_BURST(x) (((x)&0xf) << 12) ++#define BCM2708_DMA_PER_MAP(x) ((x) << 16) ++#define BCM2708_DMA_WAITS(x) (((x)&0x1f) << 21) ++ ++#define BCM2708_DMA_DREQ_EMMC 11 ++#define BCM2708_DMA_DREQ_SDHOST 13 ++ ++#define BCM2708_DMA_CS 0x00 /* Control and Status */ ++#define BCM2708_DMA_ADDR 0x04 ++/* the current control block appears in the following registers - read only */ ++#define BCM2708_DMA_INFO 0x08 ++#define BCM2708_DMA_NEXTCB 0x1C ++#define BCM2708_DMA_DEBUG 0x20 ++ ++#define BCM2708_DMA4_CS (BCM2708_DMA_CHAN(4)+BCM2708_DMA_CS) ++#define BCM2708_DMA4_ADDR (BCM2708_DMA_CHAN(4)+BCM2708_DMA_ADDR) ++ ++#define BCM2708_DMA_TDMODE_LEN(w, h) ((h) << 16 | (w)) ++ ++struct bcm2708_dma_cb { ++ unsigned long info; ++ unsigned long src; ++ unsigned long dst; ++ unsigned long length; ++ unsigned long stride; ++ unsigned long next; ++ unsigned long pad[2]; ++}; ++ ++extern int bcm_sg_suitable_for_dma(struct scatterlist *sg_ptr, int sg_len); ++extern void bcm_dma_start(void __iomem *dma_chan_base, ++ dma_addr_t control_block); ++extern void bcm_dma_wait_idle(void __iomem *dma_chan_base); ++extern int /*rc*/ bcm_dma_abort(void __iomem *dma_chan_base); ++ ++/* When listing features we can ask for when allocating DMA channels give ++ those with higher priority smaller ordinal numbers */ ++#define BCM_DMA_FEATURE_FAST_ORD 0 ++#define BCM_DMA_FEATURE_FAST (1< ++ ++ .macro disable_fiq ++ .endm ++ ++ .macro get_irqnr_preamble, base, tmp ++ ldr \base, =IO_ADDRESS(ARMCTRL_IC_BASE) ++ .endm ++ ++ .macro arch_ret_to_user, tmp1, tmp2 ++ .endm ++ ++ .macro get_irqnr_and_base, irqnr, irqstat, base, tmp ++ /* get masked status */ ++ ldr \irqstat, [\base, #(ARM_IRQ_PEND0 - ARMCTRL_IC_BASE)] ++ mov \irqnr, #(ARM_IRQ0_BASE + 31) ++ and \tmp, \irqstat, #0x300 @ save bits 8 and 9 ++ /* clear bits 8 and 9, and test */ ++ bics \irqstat, \irqstat, #0x300 ++ bne 1010f ++ ++ tst \tmp, #0x100 ++ ldrne \irqstat, [\base, #(ARM_IRQ_PEND1 - ARMCTRL_IC_BASE)] ++ movne \irqnr, #(ARM_IRQ1_BASE + 31) ++ @ Mask out the interrupts also present in PEND0 - see SW-5809 ++ bicne \irqstat, #((1<<7) | (1<<9) | (1<<10)) ++ bicne \irqstat, #((1<<18) | (1<<19)) ++ bne 1010f ++ ++ tst \tmp, #0x200 ++ ldrne \irqstat, [\base, #(ARM_IRQ_PEND2 - ARMCTRL_IC_BASE)] ++ movne \irqnr, #(ARM_IRQ2_BASE + 31) ++ @ Mask out the interrupts also present in PEND0 - see SW-5809 ++ bicne \irqstat, #((1<<21) | (1<<22) | (1<<23) | (1<<24) | (1<<25)) ++ bicne \irqstat, #((1<<30)) ++ beq 1020f ++ ++1010: ++ @ For non-zero x, LSB(x) = 31 - CLZ(x^(x-1)) ++ @ N.B. CLZ is an ARM5 instruction. ++ sub \tmp, \irqstat, #1 ++ eor \irqstat, \irqstat, \tmp ++ clz \tmp, \irqstat ++ sub \irqnr, \tmp ++ ++1020: @ EQ will be set if no irqs pending ++ ++ .endm +Index: linux-3.2.46/arch/arm/mach-bcm2708/include/mach/frc.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/arch/arm/mach-bcm2708/include/mach/frc.h 2013-07-26 19:31:51.000000000 +0000 +@@ -0,0 +1,38 @@ ++/* ++ * arch/arm/mach-bcm2708/include/mach/timex.h ++ * ++ * BCM2708 free running counter (timer) ++ * ++ * Copyright (C) 2010 Broadcom ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++#ifndef _MACH_FRC_H ++#define _MACH_FRC_H ++ ++#define FRC_TICK_RATE (1000000) ++ ++/*! Free running counter incrementing at the CLOCK_TICK_RATE ++ (slightly faster than frc_clock_ticks63() ++ */ ++extern unsigned long frc_clock_ticks32(void); ++ ++/*! Free running counter incrementing at the CLOCK_TICK_RATE ++ * Note - top bit should be ignored (see cnt32_to_63) ++ */ ++extern unsigned long long frc_clock_ticks63(void); ++ ++#endif +Index: linux-3.2.46/arch/arm/mach-bcm2708/include/mach/gpio.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/arch/arm/mach-bcm2708/include/mach/gpio.h 2013-07-26 19:31:51.000000000 +0000 +@@ -0,0 +1,48 @@ ++/* ++ * arch/arm/mach-bcm2708/include/mach/gpio.h ++ * ++ * This file is licensed under the terms of the GNU General Public ++ * License version 2. This program is licensed "as is" without any ++ * warranty of any kind, whether express or implied. ++ */ ++ ++#ifndef __ASM_ARCH_GPIO_H ++#define __ASM_ARCH_GPIO_H ++ ++#define ARCH_NR_GPIOS 54 // number of gpio lines ++ ++#include ++ ++ ++#ifdef CONFIG_GPIOLIB ++ ++static inline int gpio_get_value(unsigned gpio) ++{ ++ return __gpio_get_value(gpio); ++} ++ ++static inline void gpio_set_value(unsigned gpio, int value) ++{ ++ __gpio_set_value(gpio, value); ++} ++ ++static inline int gpio_cansleep(unsigned gpio) ++{ ++ return __gpio_cansleep(gpio); ++} ++ ++static inline int gpio_to_irq(unsigned gpio) ++{ ++ WARN_ON(1); ++ return -ENOSYS; ++} ++ ++static inline int irq_to_gpio(unsigned int irq) ++{ ++ WARN_ON(1); ++ return -EINVAL; ++} ++ ++#endif /* CONFIG_GPIOLIB */ ++ ++#endif +Index: linux-3.2.46/arch/arm/mach-bcm2708/include/mach/hardware.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/arch/arm/mach-bcm2708/include/mach/hardware.h 2013-07-26 19:31:51.000000000 +0000 +@@ -0,0 +1,28 @@ ++/* ++ * arch/arm/mach-bcm2708/include/mach/hardware.h ++ * ++ * This file contains the hardware definitions of the BCM2708 devices. ++ * ++ * Copyright (C) 2010 Broadcom ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++#ifndef __ASM_ARCH_HARDWARE_H ++#define __ASM_ARCH_HARDWARE_H ++ ++#include ++#include ++ ++#endif +Index: linux-3.2.46/arch/arm/mach-bcm2708/include/mach/io.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/arch/arm/mach-bcm2708/include/mach/io.h 2013-07-26 19:31:51.000000000 +0000 +@@ -0,0 +1,28 @@ ++/* ++ * arch/arm/mach-bcm2708/include/mach/io.h ++ * ++ * Copyright (C) 2003 ARM Limited ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++#ifndef __ASM_ARM_ARCH_IO_H ++#define __ASM_ARM_ARCH_IO_H ++ ++#define IO_SPACE_LIMIT 0xffffffff ++ ++#define __io(a) __typesafe_io(a) ++#define __mem_pci(a) (a) ++ ++#endif +Index: linux-3.2.46/arch/arm/mach-bcm2708/include/mach/irqs.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/arch/arm/mach-bcm2708/include/mach/irqs.h 2013-07-26 19:31:51.000000000 +0000 +@@ -0,0 +1,190 @@ ++/* ++ * arch/arm/mach-bcm2708/include/mach/irqs.h ++ * ++ * Copyright (C) 2010 Broadcom ++ * Copyright (C) 2003 ARM Limited ++ * Copyright (C) 2000 Deep Blue Solutions Ltd. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++#ifndef _BCM2708_IRQS_H_ ++#define _BCM2708_IRQS_H_ ++ ++#include ++ ++/* ++ * IRQ interrupts definitions are the same as the INT definitions ++ * held within platform.h ++ */ ++#define IRQ_ARMCTRL_START 0 ++#define IRQ_TIMER0 (IRQ_ARMCTRL_START + INTERRUPT_TIMER0) ++#define IRQ_TIMER1 (IRQ_ARMCTRL_START + INTERRUPT_TIMER1) ++#define IRQ_TIMER2 (IRQ_ARMCTRL_START + INTERRUPT_TIMER2) ++#define IRQ_TIMER3 (IRQ_ARMCTRL_START + INTERRUPT_TIMER3) ++#define IRQ_CODEC0 (IRQ_ARMCTRL_START + INTERRUPT_CODEC0) ++#define IRQ_CODEC1 (IRQ_ARMCTRL_START + INTERRUPT_CODEC1) ++#define IRQ_CODEC2 (IRQ_ARMCTRL_START + INTERRUPT_CODEC2) ++#define IRQ_JPEG (IRQ_ARMCTRL_START + INTERRUPT_JPEG) ++#define IRQ_ISP (IRQ_ARMCTRL_START + INTERRUPT_ISP) ++#define IRQ_USB (IRQ_ARMCTRL_START + INTERRUPT_USB) ++#define IRQ_3D (IRQ_ARMCTRL_START + INTERRUPT_3D) ++#define IRQ_TRANSPOSER (IRQ_ARMCTRL_START + INTERRUPT_TRANSPOSER) ++#define IRQ_MULTICORESYNC0 (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC0) ++#define IRQ_MULTICORESYNC1 (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC1) ++#define IRQ_MULTICORESYNC2 (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC2) ++#define IRQ_MULTICORESYNC3 (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC3) ++#define IRQ_DMA0 (IRQ_ARMCTRL_START + INTERRUPT_DMA0) ++#define IRQ_DMA1 (IRQ_ARMCTRL_START + INTERRUPT_DMA1) ++#define IRQ_DMA2 (IRQ_ARMCTRL_START + INTERRUPT_DMA2) ++#define IRQ_DMA3 (IRQ_ARMCTRL_START + INTERRUPT_DMA3) ++#define IRQ_DMA4 (IRQ_ARMCTRL_START + INTERRUPT_DMA4) ++#define IRQ_DMA5 (IRQ_ARMCTRL_START + INTERRUPT_DMA5) ++#define IRQ_DMA6 (IRQ_ARMCTRL_START + INTERRUPT_DMA6) ++#define IRQ_DMA7 (IRQ_ARMCTRL_START + INTERRUPT_DMA7) ++#define IRQ_DMA8 (IRQ_ARMCTRL_START + INTERRUPT_DMA8) ++#define IRQ_DMA9 (IRQ_ARMCTRL_START + INTERRUPT_DMA9) ++#define IRQ_DMA10 (IRQ_ARMCTRL_START + INTERRUPT_DMA10) ++#define IRQ_DMA11 (IRQ_ARMCTRL_START + INTERRUPT_DMA11) ++#define IRQ_DMA12 (IRQ_ARMCTRL_START + INTERRUPT_DMA12) ++#define IRQ_AUX (IRQ_ARMCTRL_START + INTERRUPT_AUX) ++#define IRQ_ARM (IRQ_ARMCTRL_START + INTERRUPT_ARM) ++#define IRQ_VPUDMA (IRQ_ARMCTRL_START + INTERRUPT_VPUDMA) ++#define IRQ_HOSTPORT (IRQ_ARMCTRL_START + INTERRUPT_HOSTPORT) ++#define IRQ_VIDEOSCALER (IRQ_ARMCTRL_START + INTERRUPT_VIDEOSCALER) ++#define IRQ_CCP2TX (IRQ_ARMCTRL_START + INTERRUPT_CCP2TX) ++#define IRQ_SDC (IRQ_ARMCTRL_START + INTERRUPT_SDC) ++#define IRQ_DSI0 (IRQ_ARMCTRL_START + INTERRUPT_DSI0) ++#define IRQ_AVE (IRQ_ARMCTRL_START + INTERRUPT_AVE) ++#define IRQ_CAM0 (IRQ_ARMCTRL_START + INTERRUPT_CAM0) ++#define IRQ_CAM1 (IRQ_ARMCTRL_START + INTERRUPT_CAM1) ++#define IRQ_HDMI0 (IRQ_ARMCTRL_START + INTERRUPT_HDMI0) ++#define IRQ_HDMI1 (IRQ_ARMCTRL_START + INTERRUPT_HDMI1) ++#define IRQ_PIXELVALVE1 (IRQ_ARMCTRL_START + INTERRUPT_PIXELVALVE1) ++#define IRQ_I2CSPISLV (IRQ_ARMCTRL_START + INTERRUPT_I2CSPISLV) ++#define IRQ_DSI1 (IRQ_ARMCTRL_START + INTERRUPT_DSI1) ++#define IRQ_PWA0 (IRQ_ARMCTRL_START + INTERRUPT_PWA0) ++#define IRQ_PWA1 (IRQ_ARMCTRL_START + INTERRUPT_PWA1) ++#define IRQ_CPR (IRQ_ARMCTRL_START + INTERRUPT_CPR) ++#define IRQ_SMI (IRQ_ARMCTRL_START + INTERRUPT_SMI) ++#define IRQ_GPIO0 (IRQ_ARMCTRL_START + INTERRUPT_GPIO0) ++#define IRQ_GPIO1 (IRQ_ARMCTRL_START + INTERRUPT_GPIO1) ++#define IRQ_GPIO2 (IRQ_ARMCTRL_START + INTERRUPT_GPIO2) ++#define IRQ_GPIO3 (IRQ_ARMCTRL_START + INTERRUPT_GPIO3) ++#define IRQ_I2C (IRQ_ARMCTRL_START + INTERRUPT_I2C) ++#define IRQ_SPI (IRQ_ARMCTRL_START + INTERRUPT_SPI) ++#define IRQ_I2SPCM (IRQ_ARMCTRL_START + INTERRUPT_I2SPCM) ++#define IRQ_SDIO (IRQ_ARMCTRL_START + INTERRUPT_SDIO) ++#define IRQ_UART (IRQ_ARMCTRL_START + INTERRUPT_UART) ++#define IRQ_SLIMBUS (IRQ_ARMCTRL_START + INTERRUPT_SLIMBUS) ++#define IRQ_VEC (IRQ_ARMCTRL_START + INTERRUPT_VEC) ++#define IRQ_CPG (IRQ_ARMCTRL_START + INTERRUPT_CPG) ++#define IRQ_RNG (IRQ_ARMCTRL_START + INTERRUPT_RNG) ++#define IRQ_ARASANSDIO (IRQ_ARMCTRL_START + INTERRUPT_ARASANSDIO) ++#define IRQ_AVSPMON (IRQ_ARMCTRL_START + INTERRUPT_AVSPMON) ++ ++#define IRQ_ARM_TIMER (IRQ_ARMCTRL_START + INTERRUPT_ARM_TIMER) ++#define IRQ_ARM_MAILBOX (IRQ_ARMCTRL_START + INTERRUPT_ARM_MAILBOX) ++#define IRQ_ARM_DOORBELL_0 (IRQ_ARMCTRL_START + INTERRUPT_ARM_DOORBELL_0) ++#define IRQ_ARM_DOORBELL_1 (IRQ_ARMCTRL_START + INTERRUPT_ARM_DOORBELL_1) ++#define IRQ_VPU0_HALTED (IRQ_ARMCTRL_START + INTERRUPT_VPU0_HALTED) ++#define IRQ_VPU1_HALTED (IRQ_ARMCTRL_START + INTERRUPT_VPU1_HALTED) ++#define IRQ_ILLEGAL_TYPE0 (IRQ_ARMCTRL_START + INTERRUPT_ILLEGAL_TYPE0) ++#define IRQ_ILLEGAL_TYPE1 (IRQ_ARMCTRL_START + INTERRUPT_ILLEGAL_TYPE1) ++#define IRQ_PENDING1 (IRQ_ARMCTRL_START + INTERRUPT_PENDING1) ++#define IRQ_PENDING2 (IRQ_ARMCTRL_START + INTERRUPT_PENDING2) ++ ++/* ++ * FIQ interrupts definitions are the same as the INT definitions. ++ */ ++#define FIQ_TIMER0 INT_TIMER0 ++#define FIQ_TIMER1 INT_TIMER1 ++#define FIQ_TIMER2 INT_TIMER2 ++#define FIQ_TIMER3 INT_TIMER3 ++#define FIQ_CODEC0 INT_CODEC0 ++#define FIQ_CODEC1 INT_CODEC1 ++#define FIQ_CODEC2 INT_CODEC2 ++#define FIQ_JPEG INT_JPEG ++#define FIQ_ISP INT_ISP ++#define FIQ_USB INT_USB ++#define FIQ_3D INT_3D ++#define FIQ_TRANSPOSER INT_TRANSPOSER ++#define FIQ_MULTICORESYNC0 INT_MULTICORESYNC0 ++#define FIQ_MULTICORESYNC1 INT_MULTICORESYNC1 ++#define FIQ_MULTICORESYNC2 INT_MULTICORESYNC2 ++#define FIQ_MULTICORESYNC3 INT_MULTICORESYNC3 ++#define FIQ_DMA0 INT_DMA0 ++#define FIQ_DMA1 INT_DMA1 ++#define FIQ_DMA2 INT_DMA2 ++#define FIQ_DMA3 INT_DMA3 ++#define FIQ_DMA4 INT_DMA4 ++#define FIQ_DMA5 INT_DMA5 ++#define FIQ_DMA6 INT_DMA6 ++#define FIQ_DMA7 INT_DMA7 ++#define FIQ_DMA8 INT_DMA8 ++#define FIQ_DMA9 INT_DMA9 ++#define FIQ_DMA10 INT_DMA10 ++#define FIQ_DMA11 INT_DMA11 ++#define FIQ_DMA12 INT_DMA12 ++#define FIQ_AUX INT_AUX ++#define FIQ_ARM INT_ARM ++#define FIQ_VPUDMA INT_VPUDMA ++#define FIQ_HOSTPORT INT_HOSTPORT ++#define FIQ_VIDEOSCALER INT_VIDEOSCALER ++#define FIQ_CCP2TX INT_CCP2TX ++#define FIQ_SDC INT_SDC ++#define FIQ_DSI0 INT_DSI0 ++#define FIQ_AVE INT_AVE ++#define FIQ_CAM0 INT_CAM0 ++#define FIQ_CAM1 INT_CAM1 ++#define FIQ_HDMI0 INT_HDMI0 ++#define FIQ_HDMI1 INT_HDMI1 ++#define FIQ_PIXELVALVE1 INT_PIXELVALVE1 ++#define FIQ_I2CSPISLV INT_I2CSPISLV ++#define FIQ_DSI1 INT_DSI1 ++#define FIQ_PWA0 INT_PWA0 ++#define FIQ_PWA1 INT_PWA1 ++#define FIQ_CPR INT_CPR ++#define FIQ_SMI INT_SMI ++#define FIQ_GPIO0 INT_GPIO0 ++#define FIQ_GPIO1 INT_GPIO1 ++#define FIQ_GPIO2 INT_GPIO2 ++#define FIQ_GPIO3 INT_GPIO3 ++#define FIQ_I2C INT_I2C ++#define FIQ_SPI INT_SPI ++#define FIQ_I2SPCM INT_I2SPCM ++#define FIQ_SDIO INT_SDIO ++#define FIQ_UART INT_UART ++#define FIQ_SLIMBUS INT_SLIMBUS ++#define FIQ_VEC INT_VEC ++#define FIQ_CPG INT_CPG ++#define FIQ_RNG INT_RNG ++#define FIQ_ARASANSDIO INT_ARASANSDIO ++#define FIQ_AVSPMON INT_AVSPMON ++ ++#define FIQ_ARM_TIMER INT_ARM_TIMER ++#define FIQ_ARM_MAILBOX INT_ARM_MAILBOX ++#define FIQ_ARM_DOORBELL_0 INT_ARM_DOORBELL_0 ++#define FIQ_ARM_DOORBELL_1 INT_ARM_DOORBELL_1 ++#define FIQ_VPU0_HALTED INT_VPU0_HALTED ++#define FIQ_VPU1_HALTED INT_VPU1_HALTED ++#define FIQ_ILLEGAL_TYPE0 INT_ILLEGAL_TYPE0 ++#define FIQ_ILLEGAL_TYPE1 INT_ILLEGAL_TYPE1 ++#define FIQ_PENDING1 INT_PENDING1 ++#define FIQ_PENDING2 INT_PENDING2 ++ ++#define NR_IRQS (64 + 21) ++ ++#endif /* _BCM2708_IRQS_H_ */ +Index: linux-3.2.46/arch/arm/mach-bcm2708/include/mach/irqs.h.orig +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/arch/arm/mach-bcm2708/include/mach/irqs.h.orig 2013-07-26 19:31:51.000000000 +0000 +@@ -0,0 +1,185 @@ ++/* ++ * arch/arm/mach-bcm2708/include/mach/irqs.h ++ * ++ * Copyright (C) 2010 Broadcom ++ * Copyright (C) 2003 ARM Limited ++ * Copyright (C) 2000 Deep Blue Solutions Ltd. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++#include ++ ++/* ++ * IRQ interrupts definitions are the same as the INT definitions ++ * held within platform.h ++ */ ++#define IRQ_ARMCTRL_START 0 ++#define IRQ_TIMER0 (IRQ_ARMCTRL_START + INTERRUPT_TIMER0) ++#define IRQ_TIMER1 (IRQ_ARMCTRL_START + INTERRUPT_TIMER1) ++#define IRQ_TIMER2 (IRQ_ARMCTRL_START + INTERRUPT_TIMER2) ++#define IRQ_TIMER3 (IRQ_ARMCTRL_START + INTERRUPT_TIMER3) ++#define IRQ_CODEC0 (IRQ_ARMCTRL_START + INTERRUPT_CODEC0) ++#define IRQ_CODEC1 (IRQ_ARMCTRL_START + INTERRUPT_CODEC1) ++#define IRQ_CODEC2 (IRQ_ARMCTRL_START + INTERRUPT_CODEC2) ++#define IRQ_JPEG (IRQ_ARMCTRL_START + INTERRUPT_JPEG) ++#define IRQ_ISP (IRQ_ARMCTRL_START + INTERRUPT_ISP) ++#define IRQ_USB (IRQ_ARMCTRL_START + INTERRUPT_USB) ++#define IRQ_3D (IRQ_ARMCTRL_START + INTERRUPT_3D) ++#define IRQ_TRANSPOSER (IRQ_ARMCTRL_START + INTERRUPT_TRANSPOSER) ++#define IRQ_MULTICORESYNC0 (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC0) ++#define IRQ_MULTICORESYNC1 (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC1) ++#define IRQ_MULTICORESYNC2 (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC2) ++#define IRQ_MULTICORESYNC3 (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC3) ++#define IRQ_DMA0 (IRQ_ARMCTRL_START + INTERRUPT_DMA0) ++#define IRQ_DMA1 (IRQ_ARMCTRL_START + INTERRUPT_DMA1) ++#define IRQ_DMA2 (IRQ_ARMCTRL_START + INTERRUPT_DMA2) ++#define IRQ_DMA3 (IRQ_ARMCTRL_START + INTERRUPT_DMA3) ++#define IRQ_DMA4 (IRQ_ARMCTRL_START + INTERRUPT_DMA4) ++#define IRQ_DMA5 (IRQ_ARMCTRL_START + INTERRUPT_DMA5) ++#define IRQ_DMA6 (IRQ_ARMCTRL_START + INTERRUPT_DMA6) ++#define IRQ_DMA7 (IRQ_ARMCTRL_START + INTERRUPT_DMA7) ++#define IRQ_DMA8 (IRQ_ARMCTRL_START + INTERRUPT_DMA8) ++#define IRQ_DMA9 (IRQ_ARMCTRL_START + INTERRUPT_DMA9) ++#define IRQ_DMA10 (IRQ_ARMCTRL_START + INTERRUPT_DMA10) ++#define IRQ_DMA11 (IRQ_ARMCTRL_START + INTERRUPT_DMA11) ++#define IRQ_DMA12 (IRQ_ARMCTRL_START + INTERRUPT_DMA12) ++#define IRQ_AUX (IRQ_ARMCTRL_START + INTERRUPT_AUX) ++#define IRQ_ARM (IRQ_ARMCTRL_START + INTERRUPT_ARM) ++#define IRQ_VPUDMA (IRQ_ARMCTRL_START + INTERRUPT_VPUDMA) ++#define IRQ_HOSTPORT (IRQ_ARMCTRL_START + INTERRUPT_HOSTPORT) ++#define IRQ_VIDEOSCALER (IRQ_ARMCTRL_START + INTERRUPT_VIDEOSCALER) ++#define IRQ_CCP2TX (IRQ_ARMCTRL_START + INTERRUPT_CCP2TX) ++#define IRQ_SDC (IRQ_ARMCTRL_START + INTERRUPT_SDC) ++#define IRQ_DSI0 (IRQ_ARMCTRL_START + INTERRUPT_DSI0) ++#define IRQ_AVE (IRQ_ARMCTRL_START + INTERRUPT_AVE) ++#define IRQ_CAM0 (IRQ_ARMCTRL_START + INTERRUPT_CAM0) ++#define IRQ_CAM1 (IRQ_ARMCTRL_START + INTERRUPT_CAM1) ++#define IRQ_HDMI0 (IRQ_ARMCTRL_START + INTERRUPT_HDMI0) ++#define IRQ_HDMI1 (IRQ_ARMCTRL_START + INTERRUPT_HDMI1) ++#define IRQ_PIXELVALVE1 (IRQ_ARMCTRL_START + INTERRUPT_PIXELVALVE1) ++#define IRQ_I2CSPISLV (IRQ_ARMCTRL_START + INTERRUPT_I2CSPISLV) ++#define IRQ_DSI1 (IRQ_ARMCTRL_START + INTERRUPT_DSI1) ++#define IRQ_PWA0 (IRQ_ARMCTRL_START + INTERRUPT_PWA0) ++#define IRQ_PWA1 (IRQ_ARMCTRL_START + INTERRUPT_PWA1) ++#define IRQ_CPR (IRQ_ARMCTRL_START + INTERRUPT_CPR) ++#define IRQ_SMI (IRQ_ARMCTRL_START + INTERRUPT_SMI) ++#define IRQ_GPIO0 (IRQ_ARMCTRL_START + INTERRUPT_GPIO0) ++#define IRQ_GPIO1 (IRQ_ARMCTRL_START + INTERRUPT_GPIO1) ++#define IRQ_GPIO2 (IRQ_ARMCTRL_START + INTERRUPT_GPIO2) ++#define IRQ_GPIO3 (IRQ_ARMCTRL_START + INTERRUPT_GPIO3) ++#define IRQ_I2C (IRQ_ARMCTRL_START + INTERRUPT_I2C) ++#define IRQ_SPI (IRQ_ARMCTRL_START + INTERRUPT_SPI) ++#define IRQ_I2SPCM (IRQ_ARMCTRL_START + INTERRUPT_I2SPCM) ++#define IRQ_SDIO (IRQ_ARMCTRL_START + INTERRUPT_SDIO) ++#define IRQ_UART (IRQ_ARMCTRL_START + INTERRUPT_UART) ++#define IRQ_SLIMBUS (IRQ_ARMCTRL_START + INTERRUPT_SLIMBUS) ++#define IRQ_VEC (IRQ_ARMCTRL_START + INTERRUPT_VEC) ++#define IRQ_CPG (IRQ_ARMCTRL_START + INTERRUPT_CPG) ++#define IRQ_RNG (IRQ_ARMCTRL_START + INTERRUPT_RNG) ++#define IRQ_ARASANSDIO (IRQ_ARMCTRL_START + INTERRUPT_ARASANSDIO) ++#define IRQ_AVSPMON (IRQ_ARMCTRL_START + INTERRUPT_AVSPMON) ++ ++#define IRQ_ARM_TIMER (IRQ_ARMCTRL_START + INTERRUPT_ARM_TIMER) ++#define IRQ_ARM_MAILBOX (IRQ_ARMCTRL_START + INTERRUPT_ARM_MAILBOX) ++#define IRQ_ARM_DOORBELL_0 (IRQ_ARMCTRL_START + INTERRUPT_ARM_DOORBELL_0) ++#define IRQ_ARM_DOORBELL_1 (IRQ_ARMCTRL_START + INTERRUPT_ARM_DOORBELL_1) ++#define IRQ_VPU0_HALTED (IRQ_ARMCTRL_START + INTERRUPT_VPU0_HALTED) ++#define IRQ_VPU1_HALTED (IRQ_ARMCTRL_START + INTERRUPT_VPU1_HALTED) ++#define IRQ_ILLEGAL_TYPE0 (IRQ_ARMCTRL_START + INTERRUPT_ILLEGAL_TYPE0) ++#define IRQ_ILLEGAL_TYPE1 (IRQ_ARMCTRL_START + INTERRUPT_ILLEGAL_TYPE1) ++#define IRQ_PENDING1 (IRQ_ARMCTRL_START + INTERRUPT_PENDING1) ++#define IRQ_PENDING2 (IRQ_ARMCTRL_START + INTERRUPT_PENDING2) ++ ++/* ++ * FIQ interrupts definitions are the same as the INT definitions. ++ */ ++#define FIQ_TIMER0 INT_TIMER0 ++#define FIQ_TIMER1 INT_TIMER1 ++#define FIQ_TIMER2 INT_TIMER2 ++#define FIQ_TIMER3 INT_TIMER3 ++#define FIQ_CODEC0 INT_CODEC0 ++#define FIQ_CODEC1 INT_CODEC1 ++#define FIQ_CODEC2 INT_CODEC2 ++#define FIQ_JPEG INT_JPEG ++#define FIQ_ISP INT_ISP ++#define FIQ_USB INT_USB ++#define FIQ_3D INT_3D ++#define FIQ_TRANSPOSER INT_TRANSPOSER ++#define FIQ_MULTICORESYNC0 INT_MULTICORESYNC0 ++#define FIQ_MULTICORESYNC1 INT_MULTICORESYNC1 ++#define FIQ_MULTICORESYNC2 INT_MULTICORESYNC2 ++#define FIQ_MULTICORESYNC3 INT_MULTICORESYNC3 ++#define FIQ_DMA0 INT_DMA0 ++#define FIQ_DMA1 INT_DMA1 ++#define FIQ_DMA2 INT_DMA2 ++#define FIQ_DMA3 INT_DMA3 ++#define FIQ_DMA4 INT_DMA4 ++#define FIQ_DMA5 INT_DMA5 ++#define FIQ_DMA6 INT_DMA6 ++#define FIQ_DMA7 INT_DMA7 ++#define FIQ_DMA8 INT_DMA8 ++#define FIQ_DMA9 INT_DMA9 ++#define FIQ_DMA10 INT_DMA10 ++#define FIQ_DMA11 INT_DMA11 ++#define FIQ_DMA12 INT_DMA12 ++#define FIQ_AUX INT_AUX ++#define FIQ_ARM INT_ARM ++#define FIQ_VPUDMA INT_VPUDMA ++#define FIQ_HOSTPORT INT_HOSTPORT ++#define FIQ_VIDEOSCALER INT_VIDEOSCALER ++#define FIQ_CCP2TX INT_CCP2TX ++#define FIQ_SDC INT_SDC ++#define FIQ_DSI0 INT_DSI0 ++#define FIQ_AVE INT_AVE ++#define FIQ_CAM0 INT_CAM0 ++#define FIQ_CAM1 INT_CAM1 ++#define FIQ_HDMI0 INT_HDMI0 ++#define FIQ_HDMI1 INT_HDMI1 ++#define FIQ_PIXELVALVE1 INT_PIXELVALVE1 ++#define FIQ_I2CSPISLV INT_I2CSPISLV ++#define FIQ_DSI1 INT_DSI1 ++#define FIQ_PWA0 INT_PWA0 ++#define FIQ_PWA1 INT_PWA1 ++#define FIQ_CPR INT_CPR ++#define FIQ_SMI INT_SMI ++#define FIQ_GPIO0 INT_GPIO0 ++#define FIQ_GPIO1 INT_GPIO1 ++#define FIQ_GPIO2 INT_GPIO2 ++#define FIQ_GPIO3 INT_GPIO3 ++#define FIQ_I2C INT_I2C ++#define FIQ_SPI INT_SPI ++#define FIQ_I2SPCM INT_I2SPCM ++#define FIQ_SDIO INT_SDIO ++#define FIQ_UART INT_UART ++#define FIQ_SLIMBUS INT_SLIMBUS ++#define FIQ_VEC INT_VEC ++#define FIQ_CPG INT_CPG ++#define FIQ_RNG INT_RNG ++#define FIQ_ARASANSDIO INT_ARASANSDIO ++#define FIQ_AVSPMON INT_AVSPMON ++ ++#define FIQ_ARM_TIMER INT_ARM_TIMER ++#define FIQ_ARM_MAILBOX INT_ARM_MAILBOX ++#define FIQ_ARM_DOORBELL_0 INT_ARM_DOORBELL_0 ++#define FIQ_ARM_DOORBELL_1 INT_ARM_DOORBELL_1 ++#define FIQ_VPU0_HALTED INT_VPU0_HALTED ++#define FIQ_VPU1_HALTED INT_VPU1_HALTED ++#define FIQ_ILLEGAL_TYPE0 INT_ILLEGAL_TYPE0 ++#define FIQ_ILLEGAL_TYPE1 INT_ILLEGAL_TYPE1 ++#define FIQ_PENDING1 INT_PENDING1 ++#define FIQ_PENDING2 INT_PENDING2 ++ ++#define NR_IRQS (64 + 21) +Index: linux-3.2.46/arch/arm/mach-bcm2708/include/mach/memory.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/arch/arm/mach-bcm2708/include/mach/memory.h 2013-07-26 19:31:51.000000000 +0000 +@@ -0,0 +1,59 @@ ++/* ++ * arch/arm/mach-bcm2708/include/mach/memory.h ++ * ++ * Copyright (C) 2010 Broadcom ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++#ifndef __ASM_ARCH_MEMORY_H ++#define __ASM_ARCH_MEMORY_H ++ ++/* Memory overview: ++ ++ [ARMcore] <--virtual addr--> ++ [ARMmmu] <--physical addr--> ++ [GERTmap] <--bus add--> ++ [VCperiph] ++ ++*/ ++ ++/* ++ * Physical DRAM offset. ++ */ ++#define PHYS_OFFSET UL(0x00000000) ++#define ARMMEM_OFFSET UL(0x00000000) /* offset in VC of ARM memory */ ++#define _REAL_BUS_OFFSET UL(0xC0000000) /* don't use L1 or L2 caches */ ++ ++/* We're using the memory at 64M in the VideoCore for Linux - this adjustment ++ * will provide the offset into this area as well as setting the bits that ++ * stop the L1 and L2 cache from being used ++ * ++ * WARNING: this only works because the ARM is given memory at a fixed location ++ * (ARMMEM_OFFSET) ++ */ ++#define BUS_OFFSET (ARMMEM_OFFSET + _REAL_BUS_OFFSET) ++#define __virt_to_bus(x) ((x) + (BUS_OFFSET - PAGE_OFFSET)) ++#define __bus_to_virt(x) ((x) - (BUS_OFFSET - PAGE_OFFSET)) ++#define __pfn_to_bus(x) (__pfn_to_phys(x) + (BUS_OFFSET - PHYS_OFFSET)) ++#define __bus_to_pfn(x) __phys_to_pfn((x) - (BUS_OFFSET - PHYS_OFFSET)) ++ ++/* ++ * Consistent DMA area set to 2M. Framebuffer now allocated on host ++ */ ++ ++ ++#define CONSISTENT_DMA_SIZE 0x00200000 ++ ++#endif +Index: linux-3.2.46/arch/arm/mach-bcm2708/include/mach/platform.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/arch/arm/mach-bcm2708/include/mach/platform.h 2013-07-26 19:31:51.000000000 +0000 +@@ -0,0 +1,210 @@ ++/* ++ * arch/arm/mach-bcm2708/include/mach/platform.h ++ * ++ * Copyright (C) 2010 Broadcom ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++#ifndef _BCM2708_PLATFORM_H ++#define _BCM2708_PLATFORM_H ++ ++ ++/* macros to get at IO space when running virtually */ ++#define IO_ADDRESS(x) (((x) & 0x0fffffff) + (((x) >> 4) & 0x0f000000) + 0xf0000000) ++ ++#define __io_address(a) __io(IO_ADDRESS(a)) ++ ++ ++/* ++ * SDRAM ++ */ ++#define BCM2708_SDRAM_BASE 0x00000000 ++ ++/* ++ * Logic expansion modules ++ * ++ */ ++ ++ ++/* ------------------------------------------------------------------------ ++ * BCM2708 ARMCTRL Registers ++ * ------------------------------------------------------------------------ ++ */ ++ ++#define HW_REGISTER_RW(addr) (addr) ++#define HW_REGISTER_RO(addr) (addr) ++ ++#include "arm_control.h" ++#undef ARM_BASE ++ ++/* ++ * Definitions and addresses for the ARM CONTROL logic ++ * This file is manually generated. ++ */ ++ ++#define BCM2708_PERI_BASE 0x20000000 ++#define ST_BASE (BCM2708_PERI_BASE + 0x3000) /* System Timer */ ++#define DMA_BASE (BCM2708_PERI_BASE + 0x7000) /* DMA controller */ ++#define ARM_BASE (BCM2708_PERI_BASE + 0xB000) /* BCM2708 ARM control block */ ++#define PM_BASE (BCM2708_PERI_BASE + 0x100000) /* Power Management, Reset controller and Watchdog registers */ ++#define GPIO_BASE (BCM2708_PERI_BASE + 0x200000) /* GPIO */ ++#define UART0_BASE (BCM2708_PERI_BASE + 0x201000) /* Uart 0 */ ++#define MMCI0_BASE (BCM2708_PERI_BASE + 0x202000) /* MMC interface */ ++#define UART1_BASE (BCM2708_PERI_BASE + 0x215000) /* Uart 1 */ ++#define EMMC_BASE (BCM2708_PERI_BASE + 0x300000) /* eMMC interface */ ++#define SMI_BASE (BCM2708_PERI_BASE + 0x600000) /* SMI */ ++#define USB_BASE (BCM2708_PERI_BASE + 0x980000) /* DTC_OTG USB controller */ ++#define MCORE_BASE (BCM2708_PERI_BASE + 0x0000) /* Fake frame buffer device (actually the multicore sync block*/ ++ ++#define ARMCTRL_BASE (ARM_BASE + 0x000) ++#define ARMCTRL_IC_BASE (ARM_BASE + 0x200) /* ARM interrupt controller */ ++#define ARMCTRL_TIMER0_1_BASE (ARM_BASE + 0x400) /* Timer 0 and 1 */ ++#define ARMCTRL_0_SBM_BASE (ARM_BASE + 0x800) /* User 0 (ARM)'s Semaphores Doorbells and Mailboxes */ ++ ++ ++/* ++ * Interrupt assignments ++ */ ++ ++#define ARM_IRQ1_BASE 0 ++#define INTERRUPT_TIMER0 (ARM_IRQ1_BASE + 0) ++#define INTERRUPT_TIMER1 (ARM_IRQ1_BASE + 1) ++#define INTERRUPT_TIMER2 (ARM_IRQ1_BASE + 2) ++#define INTERRUPT_TIMER3 (ARM_IRQ1_BASE + 3) ++#define INTERRUPT_CODEC0 (ARM_IRQ1_BASE + 4) ++#define INTERRUPT_CODEC1 (ARM_IRQ1_BASE + 5) ++#define INTERRUPT_CODEC2 (ARM_IRQ1_BASE + 6) ++#define INTERRUPT_VC_JPEG (ARM_IRQ1_BASE + 7) ++#define INTERRUPT_ISP (ARM_IRQ1_BASE + 8) ++#define INTERRUPT_VC_USB (ARM_IRQ1_BASE + 9) ++#define INTERRUPT_VC_3D (ARM_IRQ1_BASE + 10) ++#define INTERRUPT_TRANSPOSER (ARM_IRQ1_BASE + 11) ++#define INTERRUPT_MULTICORESYNC0 (ARM_IRQ1_BASE + 12) ++#define INTERRUPT_MULTICORESYNC1 (ARM_IRQ1_BASE + 13) ++#define INTERRUPT_MULTICORESYNC2 (ARM_IRQ1_BASE + 14) ++#define INTERRUPT_MULTICORESYNC3 (ARM_IRQ1_BASE + 15) ++#define INTERRUPT_DMA0 (ARM_IRQ1_BASE + 16) ++#define INTERRUPT_DMA1 (ARM_IRQ1_BASE + 17) ++#define INTERRUPT_VC_DMA2 (ARM_IRQ1_BASE + 18) ++#define INTERRUPT_VC_DMA3 (ARM_IRQ1_BASE + 19) ++#define INTERRUPT_DMA4 (ARM_IRQ1_BASE + 20) ++#define INTERRUPT_DMA5 (ARM_IRQ1_BASE + 21) ++#define INTERRUPT_DMA6 (ARM_IRQ1_BASE + 22) ++#define INTERRUPT_DMA7 (ARM_IRQ1_BASE + 23) ++#define INTERRUPT_DMA8 (ARM_IRQ1_BASE + 24) ++#define INTERRUPT_DMA9 (ARM_IRQ1_BASE + 25) ++#define INTERRUPT_DMA10 (ARM_IRQ1_BASE + 26) ++#define INTERRUPT_DMA11 (ARM_IRQ1_BASE + 27) ++#define INTERRUPT_DMA12 (ARM_IRQ1_BASE + 28) ++#define INTERRUPT_AUX (ARM_IRQ1_BASE + 29) ++#define INTERRUPT_ARM (ARM_IRQ1_BASE + 30) ++#define INTERRUPT_VPUDMA (ARM_IRQ1_BASE + 31) ++ ++#define ARM_IRQ2_BASE 32 ++#define INTERRUPT_HOSTPORT (ARM_IRQ2_BASE + 0) ++#define INTERRUPT_VIDEOSCALER (ARM_IRQ2_BASE + 1) ++#define INTERRUPT_CCP2TX (ARM_IRQ2_BASE + 2) ++#define INTERRUPT_SDC (ARM_IRQ2_BASE + 3) ++#define INTERRUPT_DSI0 (ARM_IRQ2_BASE + 4) ++#define INTERRUPT_AVE (ARM_IRQ2_BASE + 5) ++#define INTERRUPT_CAM0 (ARM_IRQ2_BASE + 6) ++#define INTERRUPT_CAM1 (ARM_IRQ2_BASE + 7) ++#define INTERRUPT_HDMI0 (ARM_IRQ2_BASE + 8) ++#define INTERRUPT_HDMI1 (ARM_IRQ2_BASE + 9) ++#define INTERRUPT_PIXELVALVE1 (ARM_IRQ2_BASE + 10) ++#define INTERRUPT_I2CSPISLV (ARM_IRQ2_BASE + 11) ++#define INTERRUPT_DSI1 (ARM_IRQ2_BASE + 12) ++#define INTERRUPT_PWA0 (ARM_IRQ2_BASE + 13) ++#define INTERRUPT_PWA1 (ARM_IRQ2_BASE + 14) ++#define INTERRUPT_CPR (ARM_IRQ2_BASE + 15) ++#define INTERRUPT_SMI (ARM_IRQ2_BASE + 16) ++#define INTERRUPT_GPIO0 (ARM_IRQ2_BASE + 17) ++#define INTERRUPT_GPIO1 (ARM_IRQ2_BASE + 18) ++#define INTERRUPT_GPIO2 (ARM_IRQ2_BASE + 19) ++#define INTERRUPT_GPIO3 (ARM_IRQ2_BASE + 20) ++#define INTERRUPT_VC_I2C (ARM_IRQ2_BASE + 21) ++#define INTERRUPT_VC_SPI (ARM_IRQ2_BASE + 22) ++#define INTERRUPT_VC_I2SPCM (ARM_IRQ2_BASE + 23) ++#define INTERRUPT_VC_SDIO (ARM_IRQ2_BASE + 24) ++#define INTERRUPT_VC_UART (ARM_IRQ2_BASE + 25) ++#define INTERRUPT_SLIMBUS (ARM_IRQ2_BASE + 26) ++#define INTERRUPT_VEC (ARM_IRQ2_BASE + 27) ++#define INTERRUPT_CPG (ARM_IRQ2_BASE + 28) ++#define INTERRUPT_RNG (ARM_IRQ2_BASE + 29) ++#define INTERRUPT_VC_ARASANSDIO (ARM_IRQ2_BASE + 30) ++#define INTERRUPT_AVSPMON (ARM_IRQ2_BASE + 31) ++ ++#define ARM_IRQ0_BASE 64 ++#define INTERRUPT_ARM_TIMER (ARM_IRQ0_BASE + 0) ++#define INTERRUPT_ARM_MAILBOX (ARM_IRQ0_BASE + 1) ++#define INTERRUPT_ARM_DOORBELL_0 (ARM_IRQ0_BASE + 2) ++#define INTERRUPT_ARM_DOORBELL_1 (ARM_IRQ0_BASE + 3) ++#define INTERRUPT_VPU0_HALTED (ARM_IRQ0_BASE + 4) ++#define INTERRUPT_VPU1_HALTED (ARM_IRQ0_BASE + 5) ++#define INTERRUPT_ILLEGAL_TYPE0 (ARM_IRQ0_BASE + 6) ++#define INTERRUPT_ILLEGAL_TYPE1 (ARM_IRQ0_BASE + 7) ++#define INTERRUPT_PENDING1 (ARM_IRQ0_BASE + 8) ++#define INTERRUPT_PENDING2 (ARM_IRQ0_BASE + 9) ++#define INTERRUPT_JPEG (ARM_IRQ0_BASE + 10) ++#define INTERRUPT_USB (ARM_IRQ0_BASE + 11) ++#define INTERRUPT_3D (ARM_IRQ0_BASE + 12) ++#define INTERRUPT_DMA2 (ARM_IRQ0_BASE + 13) ++#define INTERRUPT_DMA3 (ARM_IRQ0_BASE + 14) ++#define INTERRUPT_I2C (ARM_IRQ0_BASE + 15) ++#define INTERRUPT_SPI (ARM_IRQ0_BASE + 16) ++#define INTERRUPT_I2SPCM (ARM_IRQ0_BASE + 17) ++#define INTERRUPT_SDIO (ARM_IRQ0_BASE + 18) ++#define INTERRUPT_UART (ARM_IRQ0_BASE + 19) ++#define INTERRUPT_ARASANSDIO (ARM_IRQ0_BASE + 20) ++ ++#define MAXIRQNUM (32 + 32 + 20) ++#define MAXFIQNUM (32 + 32 + 20) ++ ++#define MAX_TIMER 2 ++#define MAX_PERIOD 699050 ++#define TICKS_PER_uSEC 1 ++ ++/* ++ * These are useconds NOT ticks. ++ * ++ */ ++#define mSEC_1 1000 ++#define mSEC_5 (mSEC_1 * 5) ++#define mSEC_10 (mSEC_1 * 10) ++#define mSEC_25 (mSEC_1 * 25) ++#define SEC_1 (mSEC_1 * 1000) ++ ++/* ++ * Watchdog ++ */ ++#define PM_RSTC (PM_BASE+0x1c) ++#define PM_WDOG (PM_BASE+0x24) ++ ++#define PM_WDOG_RESET 0000000000 ++#define PM_PASSWORD 0x5a000000 ++#define PM_WDOG_TIME_SET 0x000fffff ++#define PM_RSTC_WRCFG_CLR 0xffffffcf ++#define PM_RSTC_WRCFG_SET 0x00000030 ++#define PM_RSTC_WRCFG_FULL_RESET 0x00000020 ++#define PM_RSTC_RESET 0x00000102 ++ ++ ++ ++ ++ ++#endif ++ ++/* END */ +Index: linux-3.2.46/arch/arm/mach-bcm2708/include/mach/platform.h.orig +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/arch/arm/mach-bcm2708/include/mach/platform.h.orig 2013-07-26 19:31:51.000000000 +0000 +@@ -0,0 +1,210 @@ ++/* ++ * arch/arm/mach-bcm2708/include/mach/platform.h ++ * ++ * Copyright (C) 2010 Broadcom ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++#ifndef _BCM2708_PLATFORM_H ++#define _BCM2708_PLATFORM_H ++ ++ ++/* macros to get at IO space when running virtually */ ++#define IO_ADDRESS(x) (((x) & 0x0fffffff) + (((x) >> 4) & 0x0f000000) + 0xf0000000) ++ ++#define __io_address(a) __io(IO_ADDRESS(a)) ++ ++ ++/* ++ * SDRAM ++ */ ++#define BCM2708_SDRAM_BASE 0x00000000 ++ ++/* ++ * Logic expansion modules ++ * ++ */ ++ ++ ++/* ------------------------------------------------------------------------ ++ * BCM2708 ARMCTRL Registers ++ * ------------------------------------------------------------------------ ++ */ ++ ++#define HW_REGISTER_RW(addr) (addr) ++#define HW_REGISTER_RO(addr) (addr) ++ ++#include "arm_control.h" ++#undef ARM_BASE ++ ++/* ++ * Definitions and addresses for the ARM CONTROL logic ++ * This file is manually generated. ++ */ ++ ++#define BCM2708_PERI_BASE 0x20000000 ++#define ST_BASE (BCM2708_PERI_BASE + 0x3000) /* System Timer */ ++#define DMA_BASE (BCM2708_PERI_BASE + 0x7000) /* DMA controller */ ++#define ARM_BASE (BCM2708_PERI_BASE + 0xB000) /* BCM2708 ARM control block */ ++#define PM_BASE (BCM2708_PERI_BASE + 0x100000) /* Power Management, Reset controller and Watchdog registers */ ++#define GPIO_BASE (BCM2708_PERI_BASE + 0x200000) /* GPIO */ ++#define UART0_BASE (BCM2708_PERI_BASE + 0x201000) /* Uart 0 */ ++#define MMCI0_BASE (BCM2708_PERI_BASE + 0x202000) /* MMC interface */ ++#define UART1_BASE (BCM2708_PERI_BASE + 0x215000) /* Uart 1 */ ++#define EMMC_BASE (BCM2708_PERI_BASE + 0x300000) /* eMMC interface */ ++#define SMI_BASE (BCM2708_PERI_BASE + 0x600000) /* SMI */ ++#define USB_BASE (BCM2708_PERI_BASE + 0x980000) /* DTC_OTG USB controller */ ++ ++ ++#define ARMCTRL_BASE (ARM_BASE + 0x000) ++#define ARMCTRL_IC_BASE (ARM_BASE + 0x200) /* ARM interrupt controller */ ++#define ARMCTRL_TIMER0_1_BASE (ARM_BASE + 0x400) /* Timer 0 and 1 */ ++#define ARMCTRL_0_SBM_BASE (ARM_BASE + 0x800) /* User 0 (ARM)'s Semaphores Doorbells and Mailboxes */ ++ ++ ++/* ++ * Interrupt assignments ++ */ ++ ++#define ARM_IRQ1_BASE 0 ++#define INTERRUPT_TIMER0 (ARM_IRQ1_BASE + 0) ++#define INTERRUPT_TIMER1 (ARM_IRQ1_BASE + 1) ++#define INTERRUPT_TIMER2 (ARM_IRQ1_BASE + 2) ++#define INTERRUPT_TIMER3 (ARM_IRQ1_BASE + 3) ++#define INTERRUPT_CODEC0 (ARM_IRQ1_BASE + 4) ++#define INTERRUPT_CODEC1 (ARM_IRQ1_BASE + 5) ++#define INTERRUPT_CODEC2 (ARM_IRQ1_BASE + 6) ++#define INTERRUPT_VC_JPEG (ARM_IRQ1_BASE + 7) ++#define INTERRUPT_ISP (ARM_IRQ1_BASE + 8) ++#define INTERRUPT_VC_USB (ARM_IRQ1_BASE + 9) ++#define INTERRUPT_VC_3D (ARM_IRQ1_BASE + 10) ++#define INTERRUPT_TRANSPOSER (ARM_IRQ1_BASE + 11) ++#define INTERRUPT_MULTICORESYNC0 (ARM_IRQ1_BASE + 12) ++#define INTERRUPT_MULTICORESYNC1 (ARM_IRQ1_BASE + 13) ++#define INTERRUPT_MULTICORESYNC2 (ARM_IRQ1_BASE + 14) ++#define INTERRUPT_MULTICORESYNC3 (ARM_IRQ1_BASE + 15) ++#define INTERRUPT_DMA0 (ARM_IRQ1_BASE + 16) ++#define INTERRUPT_DMA1 (ARM_IRQ1_BASE + 17) ++#define INTERRUPT_VC_DMA2 (ARM_IRQ1_BASE + 18) ++#define INTERRUPT_VC_DMA3 (ARM_IRQ1_BASE + 19) ++#define INTERRUPT_DMA4 (ARM_IRQ1_BASE + 20) ++#define INTERRUPT_DMA5 (ARM_IRQ1_BASE + 21) ++#define INTERRUPT_DMA6 (ARM_IRQ1_BASE + 22) ++#define INTERRUPT_DMA7 (ARM_IRQ1_BASE + 23) ++#define INTERRUPT_DMA8 (ARM_IRQ1_BASE + 24) ++#define INTERRUPT_DMA9 (ARM_IRQ1_BASE + 25) ++#define INTERRUPT_DMA10 (ARM_IRQ1_BASE + 26) ++#define INTERRUPT_DMA11 (ARM_IRQ1_BASE + 27) ++#define INTERRUPT_DMA12 (ARM_IRQ1_BASE + 28) ++#define INTERRUPT_AUX (ARM_IRQ1_BASE + 29) ++#define INTERRUPT_ARM (ARM_IRQ1_BASE + 30) ++#define INTERRUPT_VPUDMA (ARM_IRQ1_BASE + 31) ++ ++#define ARM_IRQ2_BASE 32 ++#define INTERRUPT_HOSTPORT (ARM_IRQ2_BASE + 0) ++#define INTERRUPT_VIDEOSCALER (ARM_IRQ2_BASE + 1) ++#define INTERRUPT_CCP2TX (ARM_IRQ2_BASE + 2) ++#define INTERRUPT_SDC (ARM_IRQ2_BASE + 3) ++#define INTERRUPT_DSI0 (ARM_IRQ2_BASE + 4) ++#define INTERRUPT_AVE (ARM_IRQ2_BASE + 5) ++#define INTERRUPT_CAM0 (ARM_IRQ2_BASE + 6) ++#define INTERRUPT_CAM1 (ARM_IRQ2_BASE + 7) ++#define INTERRUPT_HDMI0 (ARM_IRQ2_BASE + 8) ++#define INTERRUPT_HDMI1 (ARM_IRQ2_BASE + 9) ++#define INTERRUPT_PIXELVALVE1 (ARM_IRQ2_BASE + 10) ++#define INTERRUPT_I2CSPISLV (ARM_IRQ2_BASE + 11) ++#define INTERRUPT_DSI1 (ARM_IRQ2_BASE + 12) ++#define INTERRUPT_PWA0 (ARM_IRQ2_BASE + 13) ++#define INTERRUPT_PWA1 (ARM_IRQ2_BASE + 14) ++#define INTERRUPT_CPR (ARM_IRQ2_BASE + 15) ++#define INTERRUPT_SMI (ARM_IRQ2_BASE + 16) ++#define INTERRUPT_GPIO0 (ARM_IRQ2_BASE + 17) ++#define INTERRUPT_GPIO1 (ARM_IRQ2_BASE + 18) ++#define INTERRUPT_GPIO2 (ARM_IRQ2_BASE + 19) ++#define INTERRUPT_GPIO3 (ARM_IRQ2_BASE + 20) ++#define INTERRUPT_VC_I2C (ARM_IRQ2_BASE + 21) ++#define INTERRUPT_VC_SPI (ARM_IRQ2_BASE + 22) ++#define INTERRUPT_VC_I2SPCM (ARM_IRQ2_BASE + 23) ++#define INTERRUPT_VC_SDIO (ARM_IRQ2_BASE + 24) ++#define INTERRUPT_VC_UART (ARM_IRQ2_BASE + 25) ++#define INTERRUPT_SLIMBUS (ARM_IRQ2_BASE + 26) ++#define INTERRUPT_VEC (ARM_IRQ2_BASE + 27) ++#define INTERRUPT_CPG (ARM_IRQ2_BASE + 28) ++#define INTERRUPT_RNG (ARM_IRQ2_BASE + 29) ++#define INTERRUPT_VC_ARASANSDIO (ARM_IRQ2_BASE + 30) ++#define INTERRUPT_AVSPMON (ARM_IRQ2_BASE + 31) ++ ++#define ARM_IRQ0_BASE 64 ++#define INTERRUPT_ARM_TIMER (ARM_IRQ0_BASE + 0) ++#define INTERRUPT_ARM_MAILBOX (ARM_IRQ0_BASE + 1) ++#define INTERRUPT_ARM_DOORBELL_0 (ARM_IRQ0_BASE + 2) ++#define INTERRUPT_ARM_DOORBELL_1 (ARM_IRQ0_BASE + 3) ++#define INTERRUPT_VPU0_HALTED (ARM_IRQ0_BASE + 4) ++#define INTERRUPT_VPU1_HALTED (ARM_IRQ0_BASE + 5) ++#define INTERRUPT_ILLEGAL_TYPE0 (ARM_IRQ0_BASE + 6) ++#define INTERRUPT_ILLEGAL_TYPE1 (ARM_IRQ0_BASE + 7) ++#define INTERRUPT_PENDING1 (ARM_IRQ0_BASE + 8) ++#define INTERRUPT_PENDING2 (ARM_IRQ0_BASE + 9) ++#define INTERRUPT_JPEG (ARM_IRQ0_BASE + 10) ++#define INTERRUPT_USB (ARM_IRQ0_BASE + 11) ++#define INTERRUPT_3D (ARM_IRQ0_BASE + 12) ++#define INTERRUPT_DMA2 (ARM_IRQ0_BASE + 13) ++#define INTERRUPT_DMA3 (ARM_IRQ0_BASE + 14) ++#define INTERRUPT_I2C (ARM_IRQ0_BASE + 15) ++#define INTERRUPT_SPI (ARM_IRQ0_BASE + 16) ++#define INTERRUPT_I2SPCM (ARM_IRQ0_BASE + 17) ++#define INTERRUPT_SDIO (ARM_IRQ0_BASE + 18) ++#define INTERRUPT_UART (ARM_IRQ0_BASE + 19) ++#define INTERRUPT_ARASANSDIO (ARM_IRQ0_BASE + 20) ++ ++#define MAXIRQNUM (32 + 32 + 20) ++#define MAXFIQNUM (32 + 32 + 20) ++ ++#define MAX_TIMER 2 ++#define MAX_PERIOD 699050 ++#define TICKS_PER_uSEC 1 ++ ++/* ++ * These are useconds NOT ticks. ++ * ++ */ ++#define mSEC_1 1000 ++#define mSEC_5 (mSEC_1 * 5) ++#define mSEC_10 (mSEC_1 * 10) ++#define mSEC_25 (mSEC_1 * 25) ++#define SEC_1 (mSEC_1 * 1000) ++ ++/* ++ * Watchdog ++ */ ++#define PM_RSTC (PM_BASE+0x1c) ++#define PM_WDOG (PM_BASE+0x24) ++ ++#define PM_WDOG_RESET 0000000000 ++#define PM_PASSWORD 0x5a000000 ++#define PM_WDOG_TIME_SET 0x000fffff ++#define PM_RSTC_WRCFG_CLR 0xffffffcf ++#define PM_RSTC_WRCFG_SET 0x00000030 ++#define PM_RSTC_WRCFG_FULL_RESET 0x00000020 ++#define PM_RSTC_RESET 0x00000102 ++ ++ ++ ++ ++ ++#endif ++ ++/* END */ +Index: linux-3.2.46/arch/arm/mach-bcm2708/include/mach/power.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/arch/arm/mach-bcm2708/include/mach/power.h 2013-07-26 19:31:51.000000000 +0000 +@@ -0,0 +1,26 @@ ++/* ++ * linux/arch/arm/mach-bcm2708/power.h ++ * ++ * Copyright (C) 2010 Broadcom ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * This device provides a shared mechanism for controlling the power to ++ * VideoCore subsystems. ++ */ ++ ++#ifndef _MACH_BCM2708_POWER_H ++#define _MACH_BCM2708_POWER_H ++ ++#include ++#include ++ ++typedef unsigned int BCM_POWER_HANDLE_T; ++ ++extern int bcm_power_open(BCM_POWER_HANDLE_T *handle); ++extern int bcm_power_request(BCM_POWER_HANDLE_T handle, uint32_t request); ++extern int bcm_power_close(BCM_POWER_HANDLE_T handle); ++ ++#endif +Index: linux-3.2.46/arch/arm/mach-bcm2708/include/mach/system.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/arch/arm/mach-bcm2708/include/mach/system.h 2013-07-26 19:31:51.000000000 +0000 +@@ -0,0 +1,53 @@ ++/* ++ * arch/arm/mach-bcm2708/include/mach/system.h ++ * ++ * Copyright (C) 2010 Broadcom ++ * Copyright (C) 2003 ARM Limited ++ * Copyright (C) 2000 Deep Blue Solutions Ltd ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++#ifndef __ASM_ARCH_SYSTEM_H ++#define __ASM_ARCH_SYSTEM_H ++ ++#include ++#include ++#include ++ ++static inline void arch_idle(void) ++{ ++ /* ++ * This should do all the clock switching ++ * and wait for interrupt tricks ++ */ ++ cpu_do_idle(); ++} ++ ++static inline void arch_reset(char mode, const char *cmd) ++{ ++ uint32_t pm_rstc, pm_wdog; ++ uint32_t timeout = 10; ++ ++ /* Setup watchdog for reset */ ++ pm_rstc = readl(IO_ADDRESS(PM_RSTC)); ++ ++ pm_wdog = PM_PASSWORD | (timeout & PM_WDOG_TIME_SET); // watchdog timer = timer clock / 16; need password (31:16) + value (11:0) ++ pm_rstc = PM_PASSWORD | (pm_rstc & PM_RSTC_WRCFG_CLR) | PM_RSTC_WRCFG_FULL_RESET; ++ ++ writel(pm_wdog, IO_ADDRESS(PM_WDOG)); ++ writel(pm_rstc, IO_ADDRESS(PM_RSTC)); ++} ++ ++#endif +Index: linux-3.2.46/arch/arm/mach-bcm2708/include/mach/timex.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/arch/arm/mach-bcm2708/include/mach/timex.h 2013-07-26 19:31:51.000000000 +0000 +@@ -0,0 +1,23 @@ ++/* ++ * arch/arm/mach-bcm2708/include/mach/timex.h ++ * ++ * BCM2708 sysem clock frequency ++ * ++ * Copyright (C) 2010 Broadcom ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++#define CLOCK_TICK_RATE (1000000) +Index: linux-3.2.46/arch/arm/mach-bcm2708/include/mach/uncompress.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/arch/arm/mach-bcm2708/include/mach/uncompress.h 2013-07-26 19:31:51.000000000 +0000 +@@ -0,0 +1,49 @@ ++/* ++ * arch/arm/mach-bcn2708/include/mach/uncompress.h ++ * ++ * Copyright (C) 2010 Broadcom ++ * Copyright (C) 2003 ARM Limited ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++#include ++#include ++ ++#define BCM2708_UART_DR __io_address(UART0_BASE + 0x00) ++#define BCM2708_UART_FR __io_address(UART0_BASE + 0x18) ++ ++/* ++ * This does not append a newline ++ */ ++static inline void putc(int c) ++{ ++ while (readl(BCM2708_UART_FR) & (1 << 5)) ++ barrier(); ++ ++ writel(c, BCM2708_UART_DR); ++} ++ ++static inline void flush(void) ++{ ++ while (readl(BCM2708_UART_FR) & (1 << 3)) ++ barrier(); ++} ++ ++/* ++ * nothing to do ++ */ ++#define arch_decomp_setup() ++#define arch_decomp_wdog() +Index: linux-3.2.46/arch/arm/mach-bcm2708/include/mach/vc_mem.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/arch/arm/mach-bcm2708/include/mach/vc_mem.h 2013-07-26 19:31:51.000000000 +0000 +@@ -0,0 +1,34 @@ ++/***************************************************************************** ++* Copyright 2010 - 2011 Broadcom Corporation. All rights reserved. ++* ++* Unless you and Broadcom execute a separate written software license ++* agreement governing use of this software, this software is licensed to you ++* under the terms of the GNU General Public License version 2, available at ++* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). ++* ++* Notwithstanding the above, under no circumstances may you combine this ++* software in any way with any other Broadcom software provided under a ++* license other than the GPL, without Broadcom's express prior written ++* consent. ++*****************************************************************************/ ++ ++#if !defined( VC_MEM_H ) ++#define VC_MEM_H ++ ++#include ++ ++#define VC_MEM_IOC_MAGIC 'v' ++ ++#define VC_MEM_IOC_MEM_PHYS_ADDR _IOR( VC_MEM_IOC_MAGIC, 0, unsigned long ) ++#define VC_MEM_IOC_MEM_SIZE _IOR( VC_MEM_IOC_MAGIC, 1, unsigned int ) ++ ++#if defined( __KERNEL__ ) ++#define VC_MEM_TO_ARM_ADDR_MASK 0x3FFFFFFF ++ ++extern unsigned long mm_vc_mem_phys_addr; ++extern unsigned int mm_vc_mem_size; ++extern int vc_mem_get_current_size( void ); ++#endif ++ ++#endif /* VC_MEM_H */ ++ +Index: linux-3.2.46/arch/arm/mach-bcm2708/include/mach/vcio.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/arch/arm/mach-bcm2708/include/mach/vcio.h 2013-07-26 19:31:51.000000000 +0000 +@@ -0,0 +1,42 @@ ++/* ++ * arch/arm/mach-bcm2708/include/mach/vcio.h ++ * ++ * Copyright (C) 2010 Broadcom ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++#ifndef _MACH_BCM2708_VCIO_H ++#define _MACH_BCM2708_VCIO_H ++ ++/* Routines to handle I/O via the VideoCore "ARM control" registers ++ * (semaphores, doorbells, mailboxes) ++ */ ++ ++#define BCM_VCIO_DRIVER_NAME "bcm2708_vcio" ++ ++/* Constants shared with the ARM identifying separate mailbox channels */ ++#define MBOX_CHAN_POWER 0 /* for use by the power management interface */ ++#define MBOX_CHAN_FB 1 /* for use by the frame buffer */ ++#define MBOX_CHAN_VUART 2 /* for use by the virtual UART */ ++#define MBOX_CHAN_VCHIQ 3 /* for use by the VCHIQ interface */ ++#define MBOX_CHAN_LEDS 4 /* for use by the leds interface */ ++#define MBOX_CHAN_BUTTONS 5 /* for use by the buttons interface */ ++#define MBOX_CHAN_TOUCH 6 /* for use by the touchscreen interface */ ++#define MBOX_CHAN_COUNT 7 ++ ++extern int /*rc*/ bcm_mailbox_read(unsigned chan, uint32_t *data28); ++extern int /*rc*/ bcm_mailbox_write(unsigned chan, uint32_t data28); ++ ++#endif +Index: linux-3.2.46/arch/arm/mach-bcm2708/include/mach/vmalloc.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/arch/arm/mach-bcm2708/include/mach/vmalloc.h 2013-07-26 19:31:51.000000000 +0000 +@@ -0,0 +1,20 @@ ++/* ++ * arch/arm/mach-bcm2708/include/mach/vmalloc.h ++ * ++ * Copyright (C) 2010 Broadcom ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++#define VMALLOC_END (0xd8000000) +Index: linux-3.2.46/arch/arm/mach-bcm2708/power.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/arch/arm/mach-bcm2708/power.c 2013-07-26 19:31:51.000000000 +0000 +@@ -0,0 +1,193 @@ ++/* ++ * linux/arch/arm/mach-bcm2708/power.c ++ * ++ * Copyright (C) 2010 Broadcom ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * This device provides a shared mechanism for controlling the power to ++ * VideoCore subsystems. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define DRIVER_NAME "bcm2708_power" ++ ++#define BCM_POWER_MAXCLIENTS 4 ++#define BCM_POWER_NOCLIENT (1<<31) ++ ++/* Some drivers expect there devices to be permanently powered */ ++#define BCM_POWER_ALWAYS_ON (BCM_POWER_USB) ++ ++#if 1 ++#define DPRINTK printk ++#else ++#define DPRINTK if (0) printk ++#endif ++ ++struct state_struct { ++ uint32_t global_request; ++ uint32_t client_request[BCM_POWER_MAXCLIENTS]; ++ struct semaphore client_mutex; ++ struct semaphore mutex; ++} g_state; ++ ++int bcm_power_open(BCM_POWER_HANDLE_T *handle) ++{ ++ BCM_POWER_HANDLE_T i; ++ int ret = -EBUSY; ++ ++ down(&g_state.client_mutex); ++ ++ for (i = 0; i < BCM_POWER_MAXCLIENTS; i++) { ++ if (g_state.client_request[i] == BCM_POWER_NOCLIENT) { ++ g_state.client_request[i] = BCM_POWER_NONE; ++ *handle = i; ++ ret = 0; ++ break; ++ } ++ } ++ ++ up(&g_state.client_mutex); ++ ++ DPRINTK("bcm_power_open() -> %d\n", *handle); ++ ++ return ret; ++} ++EXPORT_SYMBOL_GPL(bcm_power_open); ++ ++int bcm_power_request(BCM_POWER_HANDLE_T handle, uint32_t request) ++{ ++ int rc = 0; ++ ++ DPRINTK("bcm_power_request(%d, %x)\n", handle, request); ++ ++ if ((handle < BCM_POWER_MAXCLIENTS) && ++ (g_state.client_request[handle] != BCM_POWER_NOCLIENT)) { ++ if (down_interruptible(&g_state.mutex) != 0) { ++ DPRINTK("bcm_power_request -> interrupted\n"); ++ return -EINTR; ++ } ++ ++ if (request != g_state.client_request[handle]) { ++ uint32_t others_request = 0; ++ uint32_t global_request; ++ BCM_POWER_HANDLE_T i; ++ ++ for (i = 0; i < BCM_POWER_MAXCLIENTS; i++) { ++ if (i != handle) ++ others_request |= ++ g_state.client_request[i]; ++ } ++ others_request &= ~BCM_POWER_NOCLIENT; ++ ++ global_request = request | others_request; ++ if (global_request != g_state.global_request) { ++ uint32_t actual; ++ ++ /* Send a request to VideoCore */ ++ bcm_mailbox_write(MBOX_CHAN_POWER, ++ global_request << 4); ++ ++ /* Wait for a response during power-up */ ++ if (global_request & ~g_state.global_request) { ++ rc = bcm_mailbox_read(MBOX_CHAN_POWER, ++ &actual); ++ DPRINTK ++ ("bcm_mailbox_read -> %08x, %d\n", ++ actual, rc); ++ actual >>= 4; ++ } else { ++ rc = 0; ++ actual = global_request; ++ } ++ ++ if (rc == 0) { ++ if (actual != global_request) { ++ printk(KERN_ERR ++ "%s: prev global %x, new global %x, actual %x, request %x, others_request %x\n", ++ __func__, ++ g_state.global_request, ++ global_request, actual, request, others_request); ++ /* A failure */ ++ BUG_ON((others_request & actual) ++ != others_request); ++ request &= actual; ++ rc = -EIO; ++ } ++ ++ g_state.global_request = actual; ++ g_state.client_request[handle] = ++ request; ++ } ++ } ++ } ++ up(&g_state.mutex); ++ } else { ++ rc = -EINVAL; ++ } ++ DPRINTK("bcm_power_request -> %d\n", rc); ++ return rc; ++} ++EXPORT_SYMBOL_GPL(bcm_power_request); ++ ++int bcm_power_close(BCM_POWER_HANDLE_T handle) ++{ ++ int rc; ++ ++ DPRINTK("bcm_power_close(%d)\n", handle); ++ ++ rc = bcm_power_request(handle, BCM_POWER_NONE); ++ if (rc == 0) ++ g_state.client_request[handle] = BCM_POWER_NOCLIENT; ++ ++ return rc; ++} ++EXPORT_SYMBOL_GPL(bcm_power_close); ++ ++static int __init bcm_power_init(void) ++{ ++#if defined(BCM_POWER_ALWAYS_ON) ++ BCM_POWER_HANDLE_T always_on_handle; ++#endif ++ int rc = 0; ++ int i; ++ ++ printk(KERN_INFO "bcm_power: Broadcom power driver\n"); ++ ++ for (i = 0; i < BCM_POWER_MAXCLIENTS; i++) ++ g_state.client_request[i] = BCM_POWER_NOCLIENT; ++ ++ sema_init(&g_state.client_mutex, 1); ++ sema_init(&g_state.mutex, 1); ++ ++ g_state.global_request = 0; ++ ++#if defined(BCM_POWER_ALWAYS_ON) ++ if (BCM_POWER_ALWAYS_ON) { ++ bcm_power_open(&always_on_handle); ++ bcm_power_request(always_on_handle, BCM_POWER_ALWAYS_ON); ++ } ++#endif ++ ++ return rc; ++} ++ ++static void __exit bcm_power_exit(void) ++{ ++ bcm_mailbox_write(MBOX_CHAN_POWER, 0); ++} ++ ++arch_initcall(bcm_power_init); /* Initialize early */ ++module_exit(bcm_power_exit); ++ ++MODULE_AUTHOR("Phil Elwell"); ++MODULE_DESCRIPTION("Interface to BCM2708 power management"); ++MODULE_LICENSE("GPL"); +Index: linux-3.2.46/arch/arm/mach-bcm2708/vc_mem.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/arch/arm/mach-bcm2708/vc_mem.c 2013-07-26 19:31:51.000000000 +0000 +@@ -0,0 +1,467 @@ ++/***************************************************************************** ++* Copyright 2010 - 2011 Broadcom Corporation. All rights reserved. ++* ++* Unless you and Broadcom execute a separate written software license ++* agreement governing use of this software, this software is licensed to you ++* under the terms of the GNU General Public License version 2, available at ++* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). ++* ++* Notwithstanding the above, under no circumstances may you combine this ++* software in any way with any other Broadcom software provided under a ++* license other than the GPL, without Broadcom's express prior written ++* consent. ++*****************************************************************************/ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#ifdef CONFIG_ARCH_KONA ++#include ++#elif CONFIG_ARCH_BCM2708 ++#else ++#include ++#endif ++ ++#include "mach/vc_mem.h" ++//#include "interface/vchiq_arm/vchiq_connected.h" ++ ++#define DRIVER_NAME "vc-mem" ++ ++// Uncomment to enable debug logging ++//#define ENABLE_DBG ++ ++#if defined(ENABLE_DBG) ++#define LOG_DBG( fmt, ... ) printk( KERN_INFO fmt "\n", ##__VA_ARGS__ ) ++#else ++#define LOG_DBG( fmt, ... ) ++#endif ++#define LOG_ERR( fmt, ... ) printk( KERN_ERR fmt "\n", ##__VA_ARGS__ ) ++ ++// Device (/dev) related variables ++static dev_t vc_mem_devnum = 0; ++static struct class *vc_mem_class = NULL; ++static struct cdev vc_mem_cdev; ++static int vc_mem_inited = 0; ++ ++// Proc entry ++static struct proc_dir_entry *vc_mem_proc_entry; ++ ++/* ++ * Videocore memory addresses and size ++ * ++ * Drivers that wish to know the videocore memory addresses and sizes should ++ * use these variables instead of the MM_IO_BASE and MM_ADDR_IO defines in ++ * headers. This allows the other drivers to not be tied down to a a certain ++ * address/size at compile time. ++ * ++ * In the future, the goal is to have the videocore memory virtual address and ++ * size be calculated at boot time rather than at compile time. The decision of ++ * where the videocore memory resides and its size would be in the hands of the ++ * bootloader (and/or kernel). When that happens, the values of these variables ++ * would be calculated and assigned in the init function. ++ */ ++#ifdef CONFIG_ARCH_KONA ++ ++#include ++unsigned long mm_vc_mem_phys_addr = VC_EMI; ++ ++#elif CONFIG_ARCH_BCM2708 ++ ++// in the 2835 VC in mapped above ARM, but ARM has full access to VC space ++unsigned long mm_vc_mem_phys_addr = 0x00000000; ++ ++#else ++ ++#include ++unsigned long mm_vc_mem_phys_addr = MM_ADDR_IO_VC_EMI; ++ ++#endif ++ ++unsigned int mm_vc_mem_size = 0; ++ ++EXPORT_SYMBOL(mm_vc_mem_phys_addr); ++EXPORT_SYMBOL(mm_vc_mem_size); ++ ++/**************************************************************************** ++* ++* vc_mem_open ++* ++***************************************************************************/ ++ ++static int ++vc_mem_open(struct inode *inode, struct file *file) ++{ ++ (void) inode; ++ (void) file; ++ ++ LOG_DBG("%s: called file = 0x%p", __func__, file); ++ ++ return 0; ++} ++ ++/**************************************************************************** ++* ++* vc_mem_release ++* ++***************************************************************************/ ++ ++static int ++vc_mem_release(struct inode *inode, struct file *file) ++{ ++ (void) inode; ++ (void) file; ++ ++ LOG_DBG("%s: called file = 0x%p", __func__, file); ++ ++ return 0; ++} ++ ++/**************************************************************************** ++* ++* vc_mem_get_size ++* ++***************************************************************************/ ++ ++static void ++vc_mem_get_size(void) ++{ ++#ifdef CONFIG_ARCH_BCM2708 ++ mm_vc_mem_size = 256 * 1024 * 1024; // Static for now ++#else ++ CHAL_IPC_HANDLE ipc_handle; ++ uint32_t wakeup_register; ++ ++ // Get the videocore memory size from the IPC mailbox if not yet ++ // assigned. ++ if (mm_vc_mem_size == 0) { ++ ipc_handle = chal_ipc_config(NULL); ++ if (ipc_handle == NULL) { ++ LOG_ERR("%s: failed to get IPC handlle", __func__); ++ return; ++ } ++ ++ chal_ipc_query_wakeup_vc(ipc_handle, &wakeup_register); ++ if ((wakeup_register & ~1) == 0) { ++ LOG_DBG("%s: videocore not yet loaded, skipping...", ++ __func__); ++ } else { ++ if (chal_ipc_read_mailbox(ipc_handle, ++ IPC_MAILBOX_ID_0, ++ &mm_vc_mem_size) != ++ BCM_SUCCESS) { ++ LOG_ERR("%s: failed to read from IPC mailbox", ++ __func__); ++ } ++ } ++ } ++#endif ++} ++ ++/**************************************************************************** ++* ++* vc_mem_get_current_size ++* ++***************************************************************************/ ++ ++int ++vc_mem_get_current_size(void) ++{ ++ vc_mem_get_size(); ++ return mm_vc_mem_size; ++} ++ ++EXPORT_SYMBOL_GPL(vc_mem_get_current_size); ++ ++/**************************************************************************** ++* ++* vc_mem_ioctl ++* ++***************************************************************************/ ++ ++static long ++vc_mem_ioctl(struct file *file, unsigned int cmd, unsigned long arg) ++{ ++ int rc = 0; ++ ++ (void) cmd; ++ (void) arg; ++ ++ LOG_DBG("%s: called file = 0x%p", __func__, file); ++ ++ switch (cmd) { ++ case VC_MEM_IOC_MEM_PHYS_ADDR: ++ { ++ LOG_DBG("%s: VC_MEM_IOC_MEM_PHYS_ADDR=0x%p", ++ __func__, (void *) mm_vc_mem_phys_addr); ++ ++ if (copy_to_user((void *) arg, &mm_vc_mem_phys_addr, ++ sizeof (mm_vc_mem_phys_addr)) != 0) { ++ rc = -EFAULT; ++ } ++ break; ++ } ++ case VC_MEM_IOC_MEM_SIZE: ++ { ++ // Get the videocore memory size first ++ vc_mem_get_size(); ++ ++ LOG_DBG("%s: VC_MEM_IOC_MEM_SIZE=%u", __func__, ++ mm_vc_mem_size); ++ ++ if (copy_to_user((void *) arg, &mm_vc_mem_size, ++ sizeof (mm_vc_mem_size)) != 0) { ++ rc = -EFAULT; ++ } ++ break; ++ } ++ default: ++ { ++ return -ENOTTY; ++ } ++ } ++ LOG_DBG("%s: file = 0x%p returning %d", __func__, file, rc); ++ ++ return rc; ++} ++ ++/**************************************************************************** ++* ++* vc_mem_mmap ++* ++***************************************************************************/ ++ ++static int ++vc_mem_mmap(struct file *filp, struct vm_area_struct *vma) ++{ ++ int rc = 0; ++ unsigned long length = vma->vm_end - vma->vm_start; ++ unsigned long offset = vma->vm_pgoff << PAGE_SHIFT; ++ ++ LOG_DBG("%s: vm_start = 0x%08lx vm_end = 0x%08lx vm_pgoff = 0x%08lx", ++ __func__, (long) vma->vm_start, (long) vma->vm_end, ++ (long) vma->vm_pgoff); ++ ++ if (offset + length > mm_vc_mem_size) { ++ LOG_ERR("%s: length %ld is too big", __func__, length); ++ return -EINVAL; ++ } ++ // Do not cache the memory map ++ vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); ++ ++ rc = remap_pfn_range(vma, vma->vm_start, ++ (mm_vc_mem_phys_addr >> PAGE_SHIFT) + ++ vma->vm_pgoff, length, vma->vm_page_prot); ++ if (rc != 0) { ++ LOG_ERR("%s: remap_pfn_range failed (rc=%d)", __func__, rc); ++ } ++ ++ return rc; ++} ++ ++/**************************************************************************** ++* ++* File Operations for the driver. ++* ++***************************************************************************/ ++ ++static const struct file_operations vc_mem_fops = { ++ .owner = THIS_MODULE, ++ .open = vc_mem_open, ++ .release = vc_mem_release, ++ .unlocked_ioctl = vc_mem_ioctl, ++ .mmap = vc_mem_mmap, ++}; ++ ++/**************************************************************************** ++* ++* vc_mem_proc_read ++* ++***************************************************************************/ ++ ++static int ++vc_mem_proc_read(char *buf, char **start, off_t offset, int count, int *eof, ++ void *data) ++{ ++ char *p = buf; ++ ++ (void) start; ++ (void) count; ++ (void) data; ++ ++ if (offset > 0) { ++ *eof = 1; ++ return 0; ++ } ++ // Get the videocore memory size first ++ vc_mem_get_size(); ++ ++ p += sprintf(p, "Videocore memory:\n"); ++ if (mm_vc_mem_phys_addr != 0) ++ p += sprintf(p, " Physical address: 0x%p\n", ++ (void *) mm_vc_mem_phys_addr); ++ else ++ p += sprintf(p, " Physical address: 0x00000000\n"); ++ p += sprintf(p, " Length (bytes): %u\n", mm_vc_mem_size); ++ ++ *eof = 1; ++ return p - buf; ++} ++ ++/**************************************************************************** ++* ++* vc_mem_proc_write ++* ++***************************************************************************/ ++ ++static int ++vc_mem_proc_write(struct file *file, const char __user * buffer, ++ unsigned long count, void *data) ++{ ++ int rc = -EFAULT; ++ char input_str[10]; ++ ++ memset(input_str, 0, sizeof (input_str)); ++ ++ if (count > sizeof (input_str)) { ++ LOG_ERR("%s: input string length too long", __func__); ++ goto out; ++ } ++ ++ if (copy_from_user(input_str, buffer, count - 1)) { ++ LOG_ERR("%s: failed to get input string", __func__); ++ goto out; ++ } ++ ++ if (strncmp(input_str, "connect", strlen("connect")) == 0) { ++ // Get the videocore memory size from the videocore ++ vc_mem_get_size(); ++ } ++ ++ out: ++ return rc; ++} ++ ++/**************************************************************************** ++* ++* vc_mem_connected_init ++* ++* This function is called once the videocore has been connected. ++* ++***************************************************************************/ ++ ++void ++vc_mem_connected_init(void) ++{ ++ int rc = -EFAULT; ++ struct device *dev; ++ ++ LOG_DBG("%s: called", __func__); ++ ++ vc_mem_get_size(); ++ ++ printk("vc-mem: mm_vc_mem_phys_addr = 0x%08lx\n", mm_vc_mem_phys_addr); ++ printk("vc-mem: mm_vc_mem_size = 0x%08x (%u MiB)\n", ++ mm_vc_mem_size, mm_vc_mem_size / (1024 * 1024)); ++ ++ if ((rc = alloc_chrdev_region(&vc_mem_devnum, 0, 1, DRIVER_NAME)) < 0) { ++ LOG_ERR("%s: alloc_chrdev_region failed (rc=%d)", __func__, rc); ++ goto out_err; ++ } ++ ++ cdev_init(&vc_mem_cdev, &vc_mem_fops); ++ if ((rc = cdev_add(&vc_mem_cdev, vc_mem_devnum, 1)) != 0) { ++ LOG_ERR("%s: cdev_add failed (rc=%d)", __func__, rc); ++ goto out_unregister; ++ } ++ ++ vc_mem_class = class_create(THIS_MODULE, DRIVER_NAME); ++ if (IS_ERR(vc_mem_class)) { ++ rc = PTR_ERR(vc_mem_class); ++ LOG_ERR("%s: class_create failed (rc=%d)", __func__, rc); ++ goto out_cdev_del; ++ } ++ ++ dev = device_create(vc_mem_class, NULL, vc_mem_devnum, NULL, ++ DRIVER_NAME); ++ if (IS_ERR(dev)) { ++ rc = PTR_ERR(dev); ++ LOG_ERR("%s: device_create failed (rc=%d)", __func__, rc); ++ goto out_class_destroy; ++ } ++ ++ vc_mem_proc_entry = create_proc_entry(DRIVER_NAME, 0444, NULL); ++ if (vc_mem_proc_entry == NULL) { ++ rc = -EFAULT; ++ LOG_ERR("%s: create_proc_entry failed", __func__); ++ goto out_device_destroy; ++ } ++ vc_mem_proc_entry->read_proc = vc_mem_proc_read; ++ vc_mem_proc_entry->write_proc = vc_mem_proc_write; ++ ++ vc_mem_inited = 1; ++ return; ++ ++ out_device_destroy: ++ device_destroy(vc_mem_class, vc_mem_devnum); ++ ++ out_class_destroy: ++ class_destroy(vc_mem_class); ++ vc_mem_class = NULL; ++ ++ out_cdev_del: ++ cdev_del(&vc_mem_cdev); ++ ++ out_unregister: ++ unregister_chrdev_region(vc_mem_devnum, 1); ++ ++ out_err: ++ return; ++} ++ ++/**************************************************************************** ++* ++* vc_mem_init ++* ++***************************************************************************/ ++ ++static int __init ++vc_mem_init(void) ++{ ++ printk(KERN_INFO "vc-mem: Videocore memory driver\n"); ++ ++ //vchiq_add_connected_callback(vc_mem_connected_init); ++ ++ return 0; ++} ++ ++/**************************************************************************** ++* ++* vc_mem_exit ++* ++***************************************************************************/ ++ ++static void __exit ++vc_mem_exit(void) ++{ ++ LOG_DBG("%s: called", __func__); ++ ++ if (vc_mem_inited) { ++ remove_proc_entry(vc_mem_proc_entry->name, NULL); ++ device_destroy(vc_mem_class, vc_mem_devnum); ++ class_destroy(vc_mem_class); ++ cdev_del(&vc_mem_cdev); ++ unregister_chrdev_region(vc_mem_devnum, 1); ++ } ++} ++ ++module_init(vc_mem_init); ++module_exit(vc_mem_exit); ++MODULE_LICENSE("GPL"); ++MODULE_AUTHOR("Broadcom Corporation"); +Index: linux-3.2.46/arch/arm/mach-bcm2708/vcio.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/arch/arm/mach-bcm2708/vcio.c 2013-07-26 19:31:51.000000000 +0000 +@@ -0,0 +1,309 @@ ++/* ++ * linux/arch/arm/mach-bcm2708/vcio.c ++ * ++ * Copyright (C) 2010 Broadcom ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * This device provides a shared mechanism for writing to the mailboxes, ++ * semaphores, doorbells etc. that are shared between the ARM and the ++ * VideoCore processor ++ */ ++ ++#if defined(CONFIG_SERIAL_BCM_MBOX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) ++#define SUPPORT_SYSRQ ++#endif ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#include ++#include ++ ++#define DRIVER_NAME BCM_VCIO_DRIVER_NAME ++ ++/* ---------------------------------------------------------------------- ++ * Mailbox ++ * -------------------------------------------------------------------- */ ++ ++/* offsets from a mail box base address */ ++#define MAIL_WRT 0x00 /* write - and next 4 words */ ++#define MAIL_RD 0x00 /* read - and next 4 words */ ++#define MAIL_POL 0x10 /* read without popping the fifo */ ++#define MAIL_SND 0x14 /* sender ID (bottom two bits) */ ++#define MAIL_STA 0x18 /* status */ ++#define MAIL_CNF 0x1C /* configuration */ ++ ++#define MBOX_MSG(chan, data28) (((data28) & ~0xf) | ((chan) & 0xf)) ++#define MBOX_MSG_LSB(chan, data28) (((data28) << 4) | ((chan) & 0xf)) ++#define MBOX_CHAN(msg) ((msg) & 0xf) ++#define MBOX_DATA28(msg) ((msg) & ~0xf) ++#define MBOX_DATA28_LSB(msg) (((uint32_t)msg) >> 4) ++ ++#define MBOX_MAGIC 0xd0d0c0de ++ ++struct vc_mailbox { ++ struct device *dev; /* parent device */ ++ void __iomem *status; ++ void __iomem *config; ++ void __iomem *read; ++ void __iomem *write; ++ uint32_t msg[MBOX_CHAN_COUNT]; ++ struct semaphore sema[MBOX_CHAN_COUNT]; ++ uint32_t magic; ++}; ++ ++static void mbox_init(struct vc_mailbox *mbox_out, struct device *dev, ++ uint32_t addr_mbox) ++{ ++ int i; ++ ++ mbox_out->dev = dev; ++ mbox_out->status = __io_address(addr_mbox + MAIL_STA); ++ mbox_out->config = __io_address(addr_mbox + MAIL_CNF); ++ mbox_out->read = __io_address(addr_mbox + MAIL_RD); ++ /* Write to the other mailbox */ ++ mbox_out->write = ++ __io_address((addr_mbox ^ ARM_0_MAIL0_WRT ^ ARM_0_MAIL1_WRT) + ++ MAIL_WRT); ++ ++ for (i = 0; i < MBOX_CHAN_COUNT; i++) { ++ mbox_out->msg[i] = 0; ++ sema_init(&mbox_out->sema[i], 0); ++ } ++ ++ /* Enable the interrupt on data reception */ ++ writel(ARM_MC_IHAVEDATAIRQEN, mbox_out->config); ++ ++ mbox_out->magic = MBOX_MAGIC; ++} ++ ++static int mbox_write(struct vc_mailbox *mbox, unsigned chan, uint32_t data28) ++{ ++ int rc; ++ ++ if (mbox->magic != MBOX_MAGIC) ++ rc = -EINVAL; ++ else { ++ /* wait for the mailbox FIFO to have some space in it */ ++ while (0 != (readl(mbox->status) & ARM_MS_FULL)) ++ cpu_relax(); ++ ++ writel(MBOX_MSG(chan, data28), mbox->write); ++ rc = 0; ++ } ++ return rc; ++} ++ ++static int mbox_read(struct vc_mailbox *mbox, unsigned chan, uint32_t *data28) ++{ ++ int rc; ++ ++ if (mbox->magic != MBOX_MAGIC) ++ rc = -EINVAL; ++ else { ++ if (mbox->msg[chan] || ++ (down_interruptible(&mbox->sema[chan]) == 0)) { ++ *data28 = MBOX_DATA28(mbox->msg[chan]); ++ mbox->msg[chan] = 0; ++ rc = 0; ++ } else { ++ /* The wait was interrupted */ ++ rc = -EINTR; ++ } ++ } ++ return rc; ++} ++ ++static irqreturn_t mbox_irq(int irq, void *dev_id) ++{ ++ /* wait for the mailbox FIFO to have some data in it */ ++ struct vc_mailbox *mbox = (struct vc_mailbox *) dev_id; ++ int status = readl(mbox->status); ++ int ret = IRQ_NONE; ++ ++ while (!(status & ARM_MS_EMPTY)) { ++ uint32_t msg = readl(mbox->read); ++ int chan = MBOX_CHAN(msg); ++ if (chan < MBOX_CHAN_COUNT) { ++ if (mbox->msg[chan]) { ++ /* Overflow */ ++ printk(KERN_ERR DRIVER_NAME ++ ": mbox chan %d overflow - drop %08x\n", ++ chan, msg); ++ } else { ++ mbox->msg[chan] = (msg | 0xf); ++ up(&mbox->sema[chan]); ++ } ++ } else { ++ printk(KERN_ERR DRIVER_NAME ++ ": invalid channel selector (msg %08x)\n", msg); ++ } ++ ret = IRQ_HANDLED; ++ status = readl(mbox->status); ++ } ++ return ret; ++} ++ ++static struct irqaction mbox_irqaction = { ++ .name = "ARM Mailbox IRQ", ++ .flags = IRQF_DISABLED | IRQF_IRQPOLL, ++ .handler = mbox_irq, ++}; ++ ++/* ---------------------------------------------------------------------- ++ * Mailbox Methods ++ * -------------------------------------------------------------------- */ ++ ++static struct device *mbox_dev; /* we assume there's only one! */ ++ ++static int dev_mbox_write(struct device *dev, unsigned chan, uint32_t data28) ++{ ++ int rc; ++ ++ struct vc_mailbox *mailbox = dev_get_drvdata(dev); ++ device_lock(dev); ++ rc = mbox_write(mailbox, chan, data28); ++ device_unlock(dev); ++ ++ return rc; ++} ++ ++static int dev_mbox_read(struct device *dev, unsigned chan, uint32_t *data28) ++{ ++ int rc; ++ ++ struct vc_mailbox *mailbox = dev_get_drvdata(dev); ++ device_lock(dev); ++ rc = mbox_read(mailbox, chan, data28); ++ device_unlock(dev); ++ ++ return rc; ++} ++ ++extern int bcm_mailbox_write(unsigned chan, uint32_t data28) ++{ ++ if (mbox_dev) ++ return dev_mbox_write(mbox_dev, chan, data28); ++ else ++ return -ENODEV; ++} ++EXPORT_SYMBOL_GPL(bcm_mailbox_write); ++ ++extern int bcm_mailbox_read(unsigned chan, uint32_t *data28) ++{ ++ if (mbox_dev) ++ return dev_mbox_read(mbox_dev, chan, data28); ++ else ++ return -ENODEV; ++} ++EXPORT_SYMBOL_GPL(bcm_mailbox_read); ++ ++static void dev_mbox_register(const char *dev_name, struct device *dev) ++{ ++ mbox_dev = dev; ++} ++ ++/* ---------------------------------------------------------------------- ++ * Platform Device for Mailbox ++ * -------------------------------------------------------------------- */ ++ ++static int bcm_vcio_probe(struct platform_device *pdev) ++{ ++ int ret = 0; ++ struct vc_mailbox *mailbox; ++ ++ mailbox = kzalloc(sizeof(*mailbox), GFP_KERNEL); ++ if (NULL == mailbox) { ++ printk(KERN_ERR DRIVER_NAME ": failed to allocate " ++ "mailbox memory\n"); ++ ret = -ENOMEM; ++ } else { ++ struct resource *res; ++ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ if (res == NULL) { ++ printk(KERN_ERR DRIVER_NAME ": failed to obtain memory " ++ "resource\n"); ++ ret = -ENODEV; ++ kfree(mailbox); ++ } else { ++ /* should be based on the registers from res really */ ++ mbox_init(mailbox, &pdev->dev, ARM_0_MAIL0_RD); ++ ++ platform_set_drvdata(pdev, mailbox); ++ dev_mbox_register(DRIVER_NAME, &pdev->dev); ++ ++ mbox_irqaction.dev_id = mailbox; ++ setup_irq(IRQ_ARM_MAILBOX, &mbox_irqaction); ++ printk(KERN_INFO DRIVER_NAME ": mailbox at %p\n", ++ __io_address(ARM_0_MAIL0_RD)); ++ } ++ } ++ return ret; ++} ++ ++static int bcm_vcio_remove(struct platform_device *pdev) ++{ ++ struct vc_mailbox *mailbox = platform_get_drvdata(pdev); ++ ++ platform_set_drvdata(pdev, NULL); ++ kfree(mailbox); ++ ++ return 0; ++} ++ ++static struct platform_driver bcm_mbox_driver = { ++ .probe = bcm_vcio_probe, ++ .remove = bcm_vcio_remove, ++ ++ .driver = { ++ .name = DRIVER_NAME, ++ .owner = THIS_MODULE, ++ }, ++}; ++ ++static int __init bcm_mbox_init(void) ++{ ++ int ret; ++ ++ printk(KERN_INFO "mailbox: Broadcom VideoCore Mailbox driver\n"); ++ ++ ret = platform_driver_register(&bcm_mbox_driver); ++ if (ret != 0) { ++ printk(KERN_ERR DRIVER_NAME ": failed to register " ++ "on platform\n"); ++ } ++ ++ return ret; ++} ++ ++static void __exit bcm_mbox_exit(void) ++{ ++ platform_driver_unregister(&bcm_mbox_driver); ++} ++ ++arch_initcall(bcm_mbox_init); /* Initialize early */ ++module_exit(bcm_mbox_exit); ++ ++MODULE_AUTHOR("Gray Girling"); ++MODULE_DESCRIPTION("ARM I/O to VideoCore processor"); ++MODULE_LICENSE("GPL"); ++MODULE_ALIAS("platform:bcm-mbox"); +Index: linux-3.2.46/arch/arm/mm/Kconfig +=================================================================== +--- linux-3.2.46.orig/arch/arm/mm/Kconfig 2013-05-30 13:35:16.000000000 +0000 ++++ linux-3.2.46/arch/arm/mm/Kconfig 2013-07-26 19:31:51.000000000 +0000 +@@ -390,7 +390,7 @@ + + # ARMv6 + config CPU_V6 +- bool "Support ARM V6 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX ++ bool "Support ARM V6 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX || MACH_BCM2708 + select CPU_32v6 + select CPU_ABRT_EV6 + select CPU_PABRT_V6 +Index: linux-3.2.46/arch/arm/mm/alignment.c +=================================================================== +--- linux-3.2.46.orig/arch/arm/mm/alignment.c 2013-05-30 13:35:16.000000000 +0000 ++++ linux-3.2.46/arch/arm/mm/alignment.c 2013-07-26 19:31:51.000000000 +0000 +@@ -852,9 +852,11 @@ + case 0x08000000: /* ldm or stm, or thumb-2 32bit instruction */ + if (thumb2_32b) + handler = do_alignment_t32_to_handler(&instr, regs, &offset); +- else ++ else { ++ offset.un = 0; /* to keep compiler happy */ + handler = do_alignment_ldmstm; +- break; ++ } ++ break; + + default: + goto bad; +Index: linux-3.2.46/arch/arm/mm/proc-v6.S +=================================================================== +--- linux-3.2.46.orig/arch/arm/mm/proc-v6.S 2013-05-30 13:35:16.000000000 +0000 ++++ linux-3.2.46/arch/arm/mm/proc-v6.S 2013-07-26 19:31:51.000000000 +0000 +@@ -70,10 +70,19 @@ + * + * IRQs are already disabled. + */ ++ ++/* See jira SW-5991 for details of this workaround */ + ENTRY(cpu_v6_do_idle) +- mov r1, #0 +- mcr p15, 0, r1, c7, c10, 4 @ DWB - WFI may enter a low-power mode +- mcr p15, 0, r1, c7, c0, 4 @ wait for interrupt ++ .align 5 ++ mov r1, #2 ++1: subs r1, #1 ++ nop ++ mcreq p15, 0, r1, c7, c10, 4 @ DWB - WFI may enter a low-power mode ++ mcreq p15, 0, r1, c7, c0, 4 @ wait for interrupt ++ nop ++ nop ++ nop ++ bne 1b + mov pc, lr + + ENTRY(cpu_v6_dcache_clean_area) +Index: linux-3.2.46/drivers/mmc/host/Kconfig +=================================================================== +--- linux-3.2.46.orig/drivers/mmc/host/Kconfig 2013-05-30 13:35:16.000000000 +0000 ++++ linux-3.2.46/drivers/mmc/host/Kconfig 2013-07-26 19:31:51.000000000 +0000 +@@ -229,6 +229,27 @@ + + YMMV. + ++config MMC_SDHCI_BCM2708 ++ tristate "SDHCI support on BCM2708" ++ depends on MMC_SDHCI && MACH_BCM2708 ++ select MMC_SDHCI_IO_ACCESSORS ++ help ++ This selects the Secure Digital Host Controller Interface (SDHCI) ++ often referrered to as the eMMC block. ++ ++ If you have a controller with this interface, say Y or M here. ++ ++ If unsure, say N. ++ ++config MMC_SDHCI_BCM2708_DMA ++ bool "DMA support on BCM2708 Arasan controller" ++ depends on MMC_SDHCI_BCM2708 && EXPERIMENTAL ++ help ++ Enable DMA support on the Arasan SDHCI controller in Broadcom 2708 ++ based chips. ++ ++ If unsure, say N. ++ + config MMC_OMAP + tristate "TI OMAP Multimedia Card Interface support" + depends on ARCH_OMAP +@@ -296,6 +317,14 @@ + If unsure, say N. + + endchoice ++config MMC_BCM2708 ++ tristate "BCM2708 Multimedia Card Interface support" ++ help ++ This selects the BCM2708 Multimedia Card Interface driver. If ++ you have a BCM2708 platform with a Multimedia Card ++ slot, say Y or M here. ++ ++ If unsure, say N. + + config MMC_IMX + tristate "Motorola i.MX Multimedia Card Interface support" +Index: linux-3.2.46/drivers/mmc/host/Makefile +=================================================================== +--- linux-3.2.46.orig/drivers/mmc/host/Makefile 2013-05-30 13:35:16.000000000 +0000 ++++ linux-3.2.46/drivers/mmc/host/Makefile 2013-07-26 19:31:51.000000000 +0000 +@@ -13,6 +13,7 @@ + obj-$(CONFIG_MMC_SDHCI_PXAV2) += sdhci-pxav2.o + obj-$(CONFIG_MMC_SDHCI_S3C) += sdhci-s3c.o + obj-$(CONFIG_MMC_SDHCI_SPEAR) += sdhci-spear.o ++obj-$(CONFIG_MMC_SDHCI_BCM2708) += sdhci-bcm2708.o + obj-$(CONFIG_MMC_WBSD) += wbsd.o + obj-$(CONFIG_MMC_AU1X) += au1xmmc.o + obj-$(CONFIG_MMC_OMAP) += omap.o +@@ -36,6 +37,7 @@ + obj-$(CONFIG_MMC_SDHI) += sh_mobile_sdhi.o + obj-$(CONFIG_MMC_CB710) += cb710-mmc.o + obj-$(CONFIG_MMC_VIA_SDMMC) += via-sdmmc.o ++obj-$(CONFIG_MMC_BCM2708) += bcm2708_mci.o + obj-$(CONFIG_SDH_BFIN) += bfin_sdh.o + obj-$(CONFIG_MMC_DW) += dw_mmc.o + obj-$(CONFIG_MMC_SH_MMCIF) += sh_mmcif.o +Index: linux-3.2.46/drivers/mmc/host/bcm2708_mci.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/mmc/host/bcm2708_mci.c 2013-07-26 19:31:51.000000000 +0000 +@@ -0,0 +1,889 @@ ++/* ++ * linux/drivers/mmc/host/bcm2708_mci.c - Broadcom BCM2708 MCI driver ++ * ++ * Copyright (C) 2010 Broadcom, All Rights Reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++//#include ++ ++#include ++ ++#include "bcm2708_mci.h" ++ ++#define DRIVER_NAME "bcm2708_mci" ++ ++//#define PIO_DEBUG ++#ifdef PIO_DEBUG ++#define DBG(host,fmt,args...) \ ++ printk(KERN_ERR"%s: %s: " fmt, mmc_hostname(host->mmc), __func__ , args) ++#else ++#define DBG(host,fmt,args...) \ ++ pr_debug("%s: %s: " fmt, mmc_hostname(host->mmc), __func__ , args) ++#endif ++ ++#define USE_DMA ++#define USE_DMA_IRQ ++ ++#ifdef USE_DMA ++#define SDHOST_DMA_CHANNEL 5 ++#endif ++ ++#define BCM2708_DMA_ACTIVE (1 << 0) ++#define BCM2708_DMA_INT (1 << 2) ++ ++#define BCM2708_DMA_INT_EN (1 << 0) ++#define BCM2708_DMA_D_INC (1 << 4) ++#define BCM2708_DMA_D_WIDTH (1 << 5) ++#define BCM2708_DMA_D_DREQ (1 << 6) ++#define BCM2708_DMA_S_INC (1 << 8) ++#define BCM2708_DMA_S_WIDTH (1 << 9) ++#define BCM2708_DMA_S_DREQ (1 << 10) ++ ++#define BCM2708_DMA_PER_MAP(x) ((x) << 16) ++ ++#define BCM2708_DMA_DREQ_SDHOST 13 ++ ++#define BCM2708_DMA_CS 0x00 ++#define BCM2708_DMA_ADDR 0x04 ++ ++static void dump_sd_regs(void * mmc_base ); ++static int bcm2708_mci_reset(struct bcm2708_mci_host *host); ++ ++static void do_command(void __iomem *base, u32 c, u32 a) ++{ ++ u32 cmdsts = 0; ++ writel(a, base + BCM2708_MCI_ARGUMENT); ++ writel(c | BCM2708_MCI_ENABLE, base + BCM2708_MCI_COMMAND); ++ ++ /* check for error and command done */ ++ cmdsts = readl(base + BCM2708_MCI_COMMAND); ++ while ((cmdsts & BCM2708_MCI_ENABLE) && (!(cmdsts & BCM2708_MCI_FAIL_FLAG))) ++ cmdsts = readl(base + BCM2708_MCI_COMMAND); ++ if (cmdsts & BCM2708_MCI_FAIL_FLAG) { ++ printk(KERN_DEBUG"%s: Command %d failed with arg %d\n", __func__, c, a); ++ dump_sd_regs(base); ++ } ++} ++ ++//static void discard_words(void __iomem *base, int words) ++//{ ++// int i; ++// for (i = 0; i < words; i++) { ++// while (!(readl(base + BCM2708_MCI_STATUS) & BCM2708_MCI_DATAFLAG)); ++// readl(base + BCM2708_MCI_DATA); ++// } ++//} ++ ++#define CACHE_LINE_MASK 31 ++ ++static int suitable_for_dma(struct scatterlist *sg_ptr, int sg_len) ++{ ++ int i; ++ ++ for (i = 0; i < sg_len; i++) { ++ if (sg_ptr[i].offset & CACHE_LINE_MASK || sg_ptr[i].length & CACHE_LINE_MASK) ++ return 0; ++ } ++ ++ return 1; ++} ++ ++static void wait_for_complete(struct bcm2708_mci_host *host, ++ void __iomem *mmc_base) ++{ ++#ifdef USE_SDHOST_IRQ ++#error not implemented yet ++#else ++ while ((readl(mmc_base + BCM2708_MCI_STATUS) & ++ (BCM2708_MCI_HSTS_BUSY | BCM2708_MCI_HSTS_BLOCK)) == 0) ++ continue; ++ ++ writel(BCM2708_MCI_HSTS_BUSY | BCM2708_MCI_HSTS_BLOCK, ++ mmc_base + BCM2708_MCI_STATUS); ++#endif ++} ++ ++static void dump_sd_regs(void * mmc_base ) ++{ ++ printk(KERN_DEBUG"Registers:\n"); ++ printk(KERN_DEBUG"SDCMD:0x%x\n", readl(mmc_base + BCM2708_MCI_COMMAND)); ++ printk(KERN_DEBUG"SDARG:0x%x\n", readl(mmc_base + BCM2708_MCI_ARGUMENT)); ++ printk(KERN_DEBUG"SDTOUT:0x%x\n", readl(mmc_base + BCM2708_MCI_TIMEOUT)); ++ printk(KERN_DEBUG"SDCDIV:0x%x\n", readl(mmc_base + BCM2708_MCI_CLKDIV)); ++ printk(KERN_DEBUG"SDRSP0:0x%x\n", readl(mmc_base + BCM2708_MCI_RESPONSE0)); ++ printk(KERN_DEBUG"SDRSP1:0x%x\n", readl(mmc_base + BCM2708_MCI_RESPONSE1)); ++ printk(KERN_DEBUG"SDRSP2:0x%x\n", readl(mmc_base + BCM2708_MCI_RESPONSE2)); ++ printk(KERN_DEBUG"SDRSP3:0x%x\n", readl(mmc_base + BCM2708_MCI_RESPONSE3)); ++ printk(KERN_DEBUG"SDHSTS:0x%x\n", readl(mmc_base + BCM2708_MCI_STATUS)); ++ printk(KERN_DEBUG"SDPO:0x%x\n", readl(mmc_base + BCM2708_MCI_VDD)); ++ printk(KERN_DEBUG"SDEDM:0x%x\n", readl(mmc_base + BCM2708_MCI_EDM)); ++ printk(KERN_DEBUG"SDHCFG:0x%x\n", readl(mmc_base + BCM2708_MCI_HOSTCONFIG)); ++ printk(KERN_DEBUG"SDHBCT:0x%x\n", readl(mmc_base + BCM2708_MCI_HBCT)); ++ //printk(KERN_ERR"SDDATA:0x%x\n", readl(mmc_base + BCM2708_MCI_DATA)); ++ printk(KERN_DEBUG"SDHBLC:0x%x\n", readl(mmc_base + BCM2708_MCI_HBLC)); ++} ++ ++ ++static void ++bcm2708_mci_start_command(struct bcm2708_mci_host *host, struct mmc_command *cmd, struct mmc_data *data) ++{ ++ void __iomem *mmc_base = host->mmc_base; ++ void __iomem *dma_base = host->dma_base; ++ u32 status; ++ u32 c; ++ int redo = 0; ++ ++ DBG(host, "op %02x arg %08x flags %08x\n", ++ cmd->opcode, cmd->arg, cmd->flags); ++ ++back: ++ ++ /* ++ * clear the controller status register ++ */ ++ ++ writel(-1, mmc_base + BCM2708_MCI_STATUS); ++ ++ /* ++ * build the command register write, incorporating no ++ * response, long response, busy, read and write flags ++ */ ++ ++ c = cmd->opcode; ++ if (cmd->flags & MMC_RSP_PRESENT) { ++ if (cmd->flags & MMC_RSP_136) ++ c |= BCM2708_MCI_LONGRESP; ++ } else ++ c |= BCM2708_MCI_NORESP; ++ if (cmd->flags & MMC_RSP_BUSY) ++ c |= BCM2708_MCI_BUSY; ++ ++ if (data) { ++ if (data->flags & MMC_DATA_READ) ++ c |= BCM2708_MCI_READ; ++ else ++ c |= BCM2708_MCI_WRITE; ++ ++ DBG(host, "BYTECOUT %d BLOCKCOUNT %d .. ",readl(mmc_base + BCM2708_MCI_HBCT), readl(mmc_base + BCM2708_MCI_HBLC)); ++ DBG(host, "set blocksize to %d\n", data->blksz); ++ DBG(host, "set blockcnt to %d\n", data->blocks); ++ writel( data->blksz, mmc_base + BCM2708_MCI_HBCT); ++ writel(data->blocks, mmc_base + BCM2708_MCI_HBLC); ++ } ++ ++ /* ++ * run the command and wait for it to complete ++ */ ++ ++ DBG(host, "executing command=%d\n", cmd->opcode); ++ ++ do_command(mmc_base, c, cmd->arg); ++ ++ DBG(host, "done cmd=%d\n", cmd->opcode); ++ ++ if (c & BCM2708_MCI_BUSY) { ++ ++ DBG(host, "waiting for command(%d) to complete\n", cmd->opcode); ++ wait_for_complete(host, mmc_base); ++ DBG(host, "done waiting for command(%d)\n", cmd->opcode); ++ } ++ ++ /* ++ * retrieve the response and error (if any) ++ */ ++ ++ status = readl(mmc_base + BCM2708_MCI_STATUS); ++ ++ if (cmd->flags & MMC_RSP_136) { ++ cmd->resp[3] = readl(mmc_base + BCM2708_MCI_RESPONSE0); ++ cmd->resp[2] = readl(mmc_base + BCM2708_MCI_RESPONSE1); ++ cmd->resp[1] = readl(mmc_base + BCM2708_MCI_RESPONSE2); ++ cmd->resp[0] = readl(mmc_base + BCM2708_MCI_RESPONSE3); ++ } else { ++ cmd->resp[0] = readl(mmc_base + BCM2708_MCI_RESPONSE0); ++ } ++ ++ if (status & BCM2708_MCI_CMDTIMEOUT) { ++ printk(KERN_DEBUG "mmc driver saw timeout with opcode = %d, data = 0x%08x, timeout = %d", cmd->opcode, (unsigned int)data, readl(mmc_base + BCM2708_MCI_TIMEOUT)); ++ if (data) ++ printk(KERN_DEBUG " data->sg_len = %d\n", data->sg_len); ++ else ++ printk(KERN_DEBUG "\n"); ++ if (!redo) { ++ printk(KERN_DEBUG "redo\n"); ++ redo = 1; ++ goto back; ++ } else ++ cmd->error = -ETIMEDOUT; ++ } ++ ++ /* ++ * pump data if necessary ++ */ ++ ++ if (data) { ++ unsigned int sg_len = data->sg_len; ++ struct scatterlist *sg_ptr = data->sg; ++ ++ data->bytes_xfered = 0; ++ ++#ifdef USE_DMA ++ if (suitable_for_dma(sg_ptr, sg_len)) { ++ int i, count = dma_map_sg(&host->dev->dev, sg_ptr, sg_len, data->flags & MMC_DATA_READ ? DMA_FROM_DEVICE : DMA_TO_DEVICE); ++ ++ for (i = 0; i < count; i++) { ++ BCM2708_DMA_CB_T *cb = &host->cb_base[i]; ++ ++ if (data->flags & MMC_DATA_READ) { ++ cb->info = BCM2708_DMA_PER_MAP(BCM2708_DMA_DREQ_SDHOST)|BCM2708_DMA_S_DREQ|BCM2708_DMA_D_WIDTH|BCM2708_DMA_D_INC; ++ cb->src = 0x7e202040; ++ cb->dst = sg_dma_address(&sg_ptr[i]); ++ } else { ++ cb->info = BCM2708_DMA_PER_MAP(BCM2708_DMA_DREQ_SDHOST)|BCM2708_DMA_S_WIDTH|BCM2708_DMA_S_INC|BCM2708_DMA_D_DREQ; ++ cb->src = sg_dma_address(&sg_ptr[i]); ++ cb->dst = 0x7e202040; ++ } ++ ++ cb->length = sg_dma_len(&sg_ptr[i]); ++ cb->stride = 0; ++ ++ if (i == count - 1) { ++#ifdef USE_DMA_IRQ ++ cb->info |= BCM2708_DMA_INT_EN; ++#endif ++ cb->next = 0; ++ } else ++ cb->next = host->cb_handle + (i + 1) * sizeof(BCM2708_DMA_CB_T); ++ ++ cb->pad[0] = 0; ++ cb->pad[1] = 0; ++ ++ data->bytes_xfered += sg_ptr[i].length; ++ } ++ ++ dsb(); // data barrier operation ++ ++ writel(host->cb_handle, dma_base + BCM2708_DMA_ADDR); ++ writel(BCM2708_DMA_ACTIVE, dma_base + BCM2708_DMA_CS); ++ ++#ifdef USE_DMA_IRQ ++ down(&host->sem); ++#else ++ while ((readl(dma_base + BCM2708_DMA_CS) & BCM2708_DMA_ACTIVE)); ++#endif ++ dma_unmap_sg(&host->dev->dev, sg_ptr, sg_len, data->flags & MMC_DATA_READ ? DMA_FROM_DEVICE : DMA_TO_DEVICE); ++ } else ++#endif ++ while (sg_len) { ++ unsigned long flags; ++ char *buffer; ++ u32 *ptr, *lim; ++ ++ DBG(host, "sg_len=%d sg_ptr=%p len=%d\n", sg_len, sg_ptr, sg_ptr->length); ++ ++ /* ++ * map the current scatter buffer ++ */ ++ ++ buffer = bcm2708_mci_kmap_atomic(sg_ptr, &flags); ++ ++ /* ++ * pump the data ++ */ ++ ++ ptr = (u32 *)(buffer); ++ lim = (u32 *)(buffer + sg_ptr->length); ++ ++ while (ptr < lim) ++ { ++#ifdef PIO_DEBUG ++ unsigned int wait_count = 1; ++#endif ++ while (!(readl(mmc_base + BCM2708_MCI_STATUS) & BCM2708_MCI_DATAFLAG)) ++ { ++#ifdef PIO_DEBUG ++ wait_count++; ++ if ( 0 == (wait_count % 20000) ) { ++ ++ printk(KERN_ERR"Timeout waiting for data flag\n"); ++ dump_sd_regs(mmc_base); ++ } ++#endif ++ } ++ ++ if (data->flags & MMC_DATA_READ) ++ *ptr++ = readl(mmc_base + BCM2708_MCI_DATA); ++ else ++ { ++#ifdef PIO_DEBUG ++ uint32_t fifo_bytes, fifo_wait_count = 1; ++ ++ fifo_bytes = readl(mmc_base + BCM2708_MCI_EDM); ++ fifo_bytes = (fifo_bytes >> 4) & 0xf; ++ ++ while(fifo_bytes > 3) ++ { ++ fifo_wait_count++; ++ if ( 0 == (fifo_wait_count % 20000) ) { ++ printk(KERN_ERR"waiting for fifo_bytes < 3\n"); ++ dump_sd_regs(mmc_base); ++ } ++ ++ fifo_bytes = readl(mmc_base + BCM2708_MCI_EDM); ++ fifo_bytes = (fifo_bytes >> 4) & 0xf; ++ } ++ ++ BUG_ON(fifo_bytes > 3); ++#endif ++ writel(*ptr++, mmc_base + BCM2708_MCI_DATA); ++ } ++ } ++ ++ DBG(host, "done reading/writing %d bytes from mmc\n", sg_ptr->length); ++ ++ ++ /* ++ * unmap the buffer ++ */ ++ ++ bcm2708_mci_kunmap_atomic(buffer, &flags); ++ ++ /* ++ * if we were reading, and we have completed this ++ * page, ensure that the data cache is coherent ++ */ ++ ++ if (data->flags & MMC_DATA_READ) ++ flush_dcache_page(sg_page(sg_ptr)); ++ ++ data->bytes_xfered += sg_ptr->length; ++ ++ sg_ptr++; ++ sg_len--; ++ } ++ ++// if (host->is_acmd && cmd->opcode == SD_APP_SEND_SCR) ++// discard_words(mmc_base, 126); ++// if (host->is_acmd && cmd->opcode == SD_APP_SEND_NUM_WR_BLKS) ++// discard_words(mmc_base, 127); ++// if (!host->is_acmd && cmd->opcode == SD_SWITCH) ++// discard_words(mmc_base, 112); ++ ++ if (data->stop) { ++ ++ DBG(host, "sending stop command %p\n", data->stop); ++ bcm2708_mci_start_command(host, data->stop, 0); ++ ++ while ((readl(mmc_base + BCM2708_MCI_STATUS) & ++ BCM2708_MCI_DATAFLAG)) ++ { ++ DBG(host, "error data flag still set read=%d bytes\n", sg_ptr->length); ++ printk(KERN_ERR"SDDATA:0x%x\n", readl(mmc_base + BCM2708_MCI_DATA)); ++ dump_sd_regs(mmc_base); ++ } ++ } ++ } ++ /* ++ * remember if we're an application command ++ */ ++ host->is_acmd = cmd->opcode == MMC_APP_CMD; ++} ++ ++static void bcm2708_mci_request(struct mmc_host *mmc, struct mmc_request *mrq) ++{ ++ struct bcm2708_mci_host *host = mmc_priv(mmc); ++ ++ if (mrq->data && !is_power_of_2(mrq->data->blksz)) { ++ printk(KERN_ERR "%s: Unsupported block size (%d bytes)\n", ++ mmc_hostname(mmc), mrq->data->blksz); ++ mrq->cmd->error = -EINVAL; ++ mmc_request_done(mmc, mrq); ++ return; ++ } ++ ++ bcm2708_mci_start_command(host, mrq->cmd, mrq->data); ++ ++ mmc_request_done(host->mmc, mrq); ++} ++ ++static void bcm2708_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) ++{ ++ ++ struct bcm2708_mci_host *host = mmc_priv(mmc); ++ void *mmc_base = host->mmc_base; ++ ++ ++ printk(KERN_DEBUG"%s: Want to set clock: %d width: %d\n", mmc_hostname(mmc), ++ ios->clock, ios->bus_width); ++ ++ if (ios->clock == 25000000 || ios->clock == 26000000) { ++ printk(KERN_DEBUG"%s setting clock div to 10 (8+2)\n", mmc_hostname(mmc)); ++ writel(0x8, mmc_base + BCM2708_MCI_CLKDIV); ++ } else if (ios->clock == 50000000 || ios->clock == 52000000) { ++ printk(KERN_DEBUG"%s setting clock div to 5 (3+2)\n", mmc_hostname(mmc)); ++ writel(0x3, mmc_base + BCM2708_MCI_CLKDIV); ++ } else { ++ // On init or unknown clock, we set the clock really low ++ printk(KERN_DEBUG"%s Setting clock div to 0x4e0\n", mmc_hostname(mmc)); ++ writel(0x4e0, mmc_base + BCM2708_MCI_CLKDIV); ++ } ++ ++ if (ios->bus_width) { ++ uint32_t hcfg; ++ hcfg = readl(mmc_base + BCM2708_MCI_HOSTCONFIG); ++ printk(KERN_DEBUG"%s setting bus width to %d\n", mmc_hostname(mmc), ios->bus_width); ++ ++ hcfg &= BCM2708_MCI_HOSTCONFIG_WIDEEXT_CLR; ++ hcfg |= (ios->bus_width == MMC_BUS_WIDTH_4) ? BCM2708_MCI_HOSTCONFIG_WIDEEXT_4BIT : 0; ++ ++ writel(hcfg, mmc_base + BCM2708_MCI_HOSTCONFIG); ++ } ++} ++ ++static int bcm2708_mci_get_cd(struct mmc_host *mmc) ++{ ++ int present = -ENOSYS; ++ ++ struct bcm2708_mci_host *host = mmc_priv(mmc); ++ void *gpio_base = host->gpio_base; ++ ++ present = readl( (gpio_base + GP_LEV0) ); ++ ++ if ((present & (1<<29))==(1<<29)) ++ present = 0; ++ else ++ present = 1; ++ ++ printk(KERN_DEBUG"***sdcard present***=%d\n", present); ++ ++ // FIXME - For now force SD card present for 2835DK ++ present = 1; ++ return present; ++} ++ ++/* ++ * Handle completion of command and data transfers. ++ */ ++ ++//static irqreturn_t bcm2708_mci_command_irq(int irq, void *dev_id) ++//{ ++// struct bcm2708_mci_host *host = dev_id; ++// ++// writel(BCM2708_DMA_INT, host->dma_base + BCM2708_DMA_CS); ++// ++// printk(KERN_ERR "irq\n"); ++// ++// return IRQ_RETVAL(0); ++//} ++ ++static irqreturn_t bcm2708_mci_sddet_irq(int irq, void *dev_id) ++{ ++ struct bcm2708_mci_host *host = dev_id; ++ irqreturn_t handled = IRQ_NONE; ++ int present; ++ ++ present = bcm2708_mci_get_cd(host->mmc); ++ ++ if (present!=host->present) ++ { ++ host->present = present; ++ printk(KERN_DEBUG "SDDET IRQ: sdcard present: %d\n",present); ++ bcm2708_mci_reset(host); ++ mmc_detect_change(host->mmc, msecs_to_jiffies(500)); ++ } ++ ++ return IRQ_RETVAL(handled); ++} ++ ++#ifdef USE_DMA_IRQ ++static irqreturn_t bcm2708_mci_data_irq(int irq, void *dev_id) ++{ ++ struct bcm2708_mci_host *host = dev_id; ++ irqreturn_t handled = IRQ_NONE; ++ ++ if (0 != (BCM2708_DMA_INT & readl(host->dma_base + BCM2708_DMA_CS))) { ++ writel(BCM2708_DMA_INT, host->dma_base + BCM2708_DMA_CS); ++ dsb(); ++ handled = IRQ_HANDLED; ++ up(&host->sem); ++ } else { ++ printk(KERN_ERR"bcm2708_mci irq check failed !!\n"); ++ } ++ ++ return IRQ_RETVAL(handled); ++} ++#endif ++ ++static const struct mmc_host_ops bcm2708_mci_ops = { ++ .request = bcm2708_mci_request, ++ .set_ios = bcm2708_mci_set_ios, ++ .get_cd = bcm2708_mci_get_cd, ++}; ++ ++static int bcm2708_mci_reset(struct bcm2708_mci_host *host) ++{ ++ ++ void *mmc_base = host->mmc_base; ++ ++ // pin muxing/gpios is done by vcloader ++ ++ printk(KERN_DEBUG"%s:Resetting BCM2708 MCI Controller.\n", __func__ ); ++ ++ writel(0, mmc_base + BCM2708_MCI_COMMAND); ++ writel(0, mmc_base + BCM2708_MCI_ARGUMENT); ++ writel(0x00F00000, mmc_base + BCM2708_MCI_TIMEOUT); ++ writel(0, mmc_base + BCM2708_MCI_CLKDIV); ++ writel(0, mmc_base + BCM2708_MCI_STATUS); ++ writel(0, mmc_base + BCM2708_MCI_VDD); ++ writel(0, mmc_base + BCM2708_MCI_HOSTCONFIG); ++ writel(0, mmc_base + BCM2708_MCI_HBCT); ++ writel(0, mmc_base + BCM2708_MCI_HBLC); ++ ++ writel( BCM2708_MCI_HOSTCONFIG_SLOW_CARD | BCM2708_MCI_HOSTCONFIG_BUSY_IRPT_EN | ++ BCM2708_MCI_HOSTCONFIG_BLOCK_IRPT_EN | BCM2708_MCI_HOSTCONFIG_WIDE_INT_BUS, ++ mmc_base + BCM2708_MCI_HOSTCONFIG); ++ ++ // On A0 silicon it has been observed that the following must hold ++ // WRITE_THRESHOLD<=5 and READ_THRESHOLD<=WRITE_THRESHOLD+1 ++ // with the chip running at 150MHz (with the interface running @ 150/22 = 6.8 MHz) ++ // the second requirement suggests that the verilog does not properly separate the read / write FIFOs ++ // On V3XDS Read=2 & Write=6 ++ ++#define READ_THRESHOLD 3 ++#define WRITE_THRESHOLD 3 ++#if 1 // !!! This is still required, without it we get CRC16 errors in data. ++ { ++ uint32_t temp; ++ temp = readl(mmc_base + BCM2708_MCI_EDM); ++ temp &= ~((0x1F<<14) | (0x1F<<9)); ++ temp |= (WRITE_THRESHOLD << 9) | (READ_THRESHOLD << 14); ++ writel(temp, mmc_base + BCM2708_MCI_EDM); ++ } ++#endif ++ ++ // Power on delay ++ mdelay(10); ++ writel(BCM2708_MCI_VDD_ENABLE, mmc_base + BCM2708_MCI_VDD); ++ mdelay(10); ++ ++ return 0; ++} ++ ++ ++static int __devinit bcm2708_mci_probe(struct platform_device *pdev) ++{ ++ struct mmc_host *mmc; ++ struct bcm2708_mci_host *host; ++ struct resource *mmc_res; ++ struct resource *dma_res; ++ struct resource *gpio_res; ++ struct resource *dat_res; ++ struct resource *sddet_res; ++ int ret; ++ ++ mmc = mmc_alloc_host(sizeof(struct bcm2708_mci_host), &pdev->dev); ++ if (!mmc) { ++ ret = -ENOMEM; ++ dev_dbg(&pdev->dev, "couldn't allocate mmc host\n"); ++ goto fail0; ++ } ++ ++ host = mmc_priv(mmc); ++ host->mmc = mmc; ++ ++ host->dev = pdev; ++ ++ sema_init(&host->sem, 0); ++ ++#ifdef USE_DMA ++ host->cb_base = dma_alloc_writecombine(&pdev->dev, SZ_4K, &host->cb_handle, GFP_KERNEL); ++ if (!host->cb_base) { ++ ret = -ENOMEM; ++ dev_dbg(&pdev->dev, "couldn't allocate dma base\n"); ++ goto fail1; ++ } ++#endif ++ ++ mmc_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ if (!mmc_res) { ++ ret = -ENXIO; ++ dev_dbg(&pdev->dev, "couldn't allocate mmc memory resource 0\n"); ++ goto fail2; ++ } ++ ++ if (!request_mem_region(mmc_res->start, mmc_res->end - mmc_res->start + 1, DRIVER_NAME)) { ++ ret = -EBUSY; ++ goto fail2; ++ } ++ ++ dma_res = platform_get_resource(pdev, IORESOURCE_MEM, 1); ++ if (!dma_res) { ++ ret = -ENXIO; ++ dev_dbg(&pdev->dev, "couldn't allocate dma memory resource 1\n"); ++ goto fail3; ++ } ++ ++ /* ++ * Map I/O regions ++ */ ++ ++ host->mmc_base = ioremap(mmc_res->start, resource_size(mmc_res)); ++ if (!host->mmc_base) { ++ ret = -ENOMEM; ++ goto fail3; ++ } ++ ++ gpio_res = platform_get_resource(pdev, IORESOURCE_MEM, 2); ++ if (!gpio_res) { ++ ret = -ENXIO; ++ dev_dbg(&pdev->dev, "couldn't allocate gpio resource\n"); ++ goto fail4; ++ } ++ ++ /* ++ * Map I/O regions ++ */ ++ ++ host->gpio_base = ioremap(gpio_res->start, resource_size(gpio_res)); ++ if (!host->gpio_base) { ++ ret = -ENOMEM; ++ goto fail4; ++ } ++ ++#ifdef USE_DMA ++ host->dma_base = __io_address(dma_res->start); ++ ++ if (!host->dma_base) { ++ ret = -ENOMEM; ++ goto fail5; ++ } ++ ++ // USE DMA5 channel ++ host->dma_base = (void __iomem *)((char *) host->dma_base + (SDHOST_DMA_CHANNEL * 0x100)); ++ ++ dev_dbg(&pdev->dev, "%s: using dma channel %d for sdhost\n", __func__, SDHOST_DMA_CHANNEL); ++ ++ /* ++ * Grab interrupts. ++ */ ++#ifdef USE_DMA_IRQ ++ dat_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); ++ if (!dat_res) { ++ ret = -ENXIO; ++ dev_dbg(&pdev->dev, "couldn't allocate irq for dma\n"); ++ goto fail5; ++ } ++ ++ ret = request_irq(dat_res->start, bcm2708_mci_data_irq, 0, DRIVER_NAME " (dat)", host); ++ if (ret) { ++ goto fail5; ++ } ++ dev_dbg(&pdev->dev, "%s: using dma interrupt number %d for sdhost\n", __func__, dat_res->start); ++ ++#endif ++#endif ++ ++ host->present = bcm2708_mci_get_cd(host->mmc); ++ ++ sddet_res = platform_get_resource(pdev, IORESOURCE_IRQ, 1); ++ if (!sddet_res) { ++ ret = -ENXIO; ++ dev_dbg(&pdev->dev, "couldn't allocate irq for sd detect\n"); ++ goto fail6; ++ } ++ ++ ret = request_irq(sddet_res->start, bcm2708_mci_sddet_irq, 0, DRIVER_NAME " (cmd)", host); ++ if (ret) { ++ goto fail6; ++ } ++ ++ host->is_acmd = 0; ++ ++ mmc->ops = &bcm2708_mci_ops; ++ mmc->f_min = 200000; ++ mmc->f_max = 52000000; ++ mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; ++ ++ /* ++ * We can do SGIO ++ */ ++ mmc->max_segs = NR_SG; ++ ++ /* ++ * Since we only have a 16-bit data length register, we must ++ * ensure that we don't exceed 2^16-1 bytes in a single request. ++ */ ++ mmc->max_req_size = 65535; ++ ++ /* ++ * Set the maximum segment size. Since we aren't doing DMA ++ * (yet) we are only limited by the data length register. ++ */ ++ mmc->max_seg_size = mmc->max_req_size; ++ ++ /* ++ * Block size can be up to 2048 bytes, but must be a power of two. ++ */ ++ mmc->max_blk_size = 2048; ++ ++ /* ++ * No limit on the number of blocks transferred. ++ */ ++ mmc->max_blk_count = mmc->max_req_size; ++ ++ /* ++ * We support 4-bit data (at least on the DB) ++ */ ++ ++ mmc->caps |= (MMC_CAP_4_BIT_DATA | MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED) ; ++ ++ bcm2708_mci_reset(host); ++ ++ mmc_add_host(mmc); ++ ++ printk(KERN_INFO "%s: BCM2708 SD host at 0x%08llx 0x%08llx\n", ++ mmc_hostname(mmc), ++ (unsigned long long)mmc_res->start, (unsigned long long)dma_res->start); ++ ++ return 0; ++ ++fail6: ++#ifdef USE_DMA_IRQ ++ free_irq(dat_res->start, host); ++#endif ++fail5: ++ iounmap(host->gpio_base); ++fail4: ++ iounmap(host->mmc_base); ++fail3: ++ release_mem_region(mmc_res->start, mmc_res->end - mmc_res->start + 1); ++fail2: ++ dma_free_writecombine(&pdev->dev, SZ_4K, host->cb_base, host->cb_handle); ++fail1: ++ mmc_free_host(mmc); ++fail0: ++ dev_err(&pdev->dev, "probe failed, err %d\n", ret); ++ return ret; ++} ++ ++static int __devexit bcm2708_mci_remove(struct platform_device *pdev) ++{ ++ struct mmc_host *mmc = platform_get_drvdata(pdev); ++ ++ if (mmc) { ++ struct bcm2708_mci_host *host = mmc_priv(mmc); ++ struct resource *res; ++ struct resource *res2; ++ ++ mmc_remove_host(mmc); ++#ifdef USE_DMA ++#ifdef USE_DMA_IRQ ++ res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); ++ free_irq(res->start, host); ++#endif ++#endif ++ ++ res2 = platform_get_resource(pdev, IORESOURCE_IRQ, 1); ++ free_irq(res2->start, host); ++ ++ iounmap(host->mmc_base); ++ iounmap(host->gpio_base); ++ iounmap(host->dma_base); ++ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ release_mem_region(res->start, resource_size(res)); ++#ifdef USE_DMA ++ dma_free_writecombine(&pdev->dev, SZ_4K, host->cb_base, host->cb_handle); ++#endif ++ ++ mmc_free_host(mmc); ++ platform_set_drvdata(pdev, NULL); ++ ++ return 0; ++ } else ++ return -1; ++} ++ ++#ifdef CONFIG_PM ++static int bcm2708_mci_suspend(struct platform_device *dev, pm_message_t state) ++{ ++ struct mmc_host *mmc = platform_get_drvdata(dev); ++ int ret = 0; ++ ++ if (mmc) { ++ ret = mmc_suspend_host(mmc); ++ } ++ ++ return ret; ++} ++ ++static int bcm2708_mci_resume(struct platform_device *dev) ++{ ++ struct mmc_host *mmc = platform_get_drvdata(dev); ++ int ret = 0; ++ ++ if (mmc) { ++ ret = mmc_resume_host(mmc); ++ } ++ ++ return ret; ++} ++#else ++#define bcm2708_mci_suspend NULL ++#define bcm2708_mci_resume NULL ++#endif ++ ++static struct platform_driver bcm2708_mci_driver = { ++ .probe = bcm2708_mci_probe, ++ .remove = bcm2708_mci_remove, ++ .suspend = bcm2708_mci_suspend, ++ .resume = bcm2708_mci_resume, ++ .driver = { ++ .name = DRIVER_NAME, ++ .owner = THIS_MODULE, ++ }, ++}; ++ ++static int __init bcm2708_mci_init(void) ++{ ++ return platform_driver_register(&bcm2708_mci_driver); ++} ++ ++static void __exit bcm2708_mci_exit(void) ++{ ++ platform_driver_unregister(&bcm2708_mci_driver); ++} ++ ++module_init(bcm2708_mci_init); ++module_exit(bcm2708_mci_exit); ++ ++MODULE_DESCRIPTION("BCM2708 Multimedia Card Interface driver"); ++MODULE_LICENSE("GPL"); ++MODULE_ALIAS("platform:bcm2708_mci"); +Index: linux-3.2.46/drivers/mmc/host/bcm2708_mci.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/mmc/host/bcm2708_mci.h 2013-07-26 19:31:51.000000000 +0000 +@@ -0,0 +1,101 @@ ++/* ++ * linux/drivers/mmc/host/bcm2708_mci.c - Broadcom BCM2708 MCI driver ++ * ++ * Copyright (C) 2010 Broadcom, All Rights Reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++struct clk; ++ ++#define BCM2708_MCI_COMMAND 0x00 ++ ++#define BCM2708_MCI_READ (1 << 6) ++#define BCM2708_MCI_WRITE (1 << 7) ++#define BCM2708_MCI_LONGRESP (1 << 9) ++#define BCM2708_MCI_NORESP (1 << 10) ++#define BCM2708_MCI_BUSY (1 << 11) ++#define BCM2708_MCI_FAIL_FLAG (1 << 14) ++#define BCM2708_MCI_ENABLE (1 << 15) ++ ++#define BCM2708_MCI_ARGUMENT 0x04 ++ ++#define BCM2708_MCI_TIMEOUT 0x08 ++#define BCM2708_MCI_CLKDIV 0x0c ++ ++ ++#define BCM2708_MCI_RESPONSE0 0x10 ++#define BCM2708_MCI_RESPONSE1 0x14 ++#define BCM2708_MCI_RESPONSE2 0x18 ++#define BCM2708_MCI_RESPONSE3 0x1c ++ ++#define BCM2708_MCI_STATUS 0x20 ++ ++#define BCM2708_MCI_VDD 0x30 ++#define BCM2708_MCI_VDD_ENABLE (1 << 0) ++ ++#define BCM2708_MCI_EDM 0x34 ++ ++#define BCM2708_MCI_HOSTCONFIG 0x38 ++ ++#define BCM2708_MCI_HOSTCONFIG_WIDE_INT_BUS 0x2 ++#define BCM2708_MCI_HOSTCONFIG_WIDEEXT_4BIT 0x4 ++#define BCM2708_MCI_HOSTCONFIG_SLOW_CARD 0x8 ++#define BCM2708_MCI_HOSTCONFIG_BLOCK_IRPT_EN (1<<8) ++#define BCM2708_MCI_HOSTCONFIG_BUSY_IRPT_EN (1<<10) ++#define BCM2708_MCI_HOSTCONFIG_WIDEEXT_CLR 0xFFFFFFFB ++ ++ ++#define BCM2708_MCI_DATAFLAG (1 << 0) ++#define BCM2708_MCI_CMDTIMEOUT (1 << 6) ++#define BCM2708_MCI_HSTS_BLOCK (1 << 9) /**< block flag in status reg */ ++#define BCM2708_MCI_HSTS_BUSY (1 << 10) /**< Busy flag in status reg */ ++ ++#define BCM2708_MCI_HBCT 0x3c ++#define BCM2708_MCI_DATA 0x40 ++#define BCM2708_MCI_HBLC 0x50 ++ ++#define NR_SG 16 ++ ++typedef struct bulk_data_struct ++{ ++ unsigned long info; ++ unsigned long src; ++ unsigned long dst; ++ unsigned long length; ++ unsigned long stride; ++ unsigned long next; ++ unsigned long pad[2]; ++} BCM2708_DMA_CB_T; ++ ++struct bcm2708_mci_host { ++ struct platform_device *dev; ++ ++ void __iomem *mmc_base; ++ void __iomem *dma_base; ++ void __iomem *gpio_base; ++ ++ BCM2708_DMA_CB_T *cb_base; ++ dma_addr_t cb_handle; ++ ++ struct mmc_host *mmc; ++ ++ struct semaphore sem; ++ ++ int is_acmd; ++ int present; ++}; ++ ++static inline char *bcm2708_mci_kmap_atomic(struct scatterlist *sg, unsigned long *flags) ++{ ++// local_irq_save(*flags); ++ return kmap_atomic(sg_page(sg), KM_BIO_SRC_IRQ) + sg->offset; ++} ++ ++static inline void bcm2708_mci_kunmap_atomic(void *buffer, unsigned long *flags) ++{ ++ kunmap_atomic(buffer, KM_BIO_SRC_IRQ); ++// local_irq_restore(*flags); ++} +Index: linux-3.2.46/drivers/mmc/host/sdhci-bcm2708.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/mmc/host/sdhci-bcm2708.c 2013-07-26 19:31:51.000000000 +0000 +@@ -0,0 +1,1461 @@ ++/* ++ * sdhci-bcm2708.c Support for SDHCI device on BCM2708 ++ * Copyright (c) 2010 Broadcom ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. ++ */ ++ ++/* Supports: ++ * SDHCI platform device - Arasan SD controller in BCM2708 ++ * ++ * Inspired by sdhci-pci.c, by Pierre Ossman ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++ ++#include "sdhci.h" ++ ++/*****************************************************************************\ ++ * * ++ * Configuration * ++ * * ++\*****************************************************************************/ ++ ++#define DRIVER_NAME "bcm2708_sdhci" ++ ++/* for the time being insist on DMA mode - PIO seems not to work */ ++#ifndef CONFIG_MMC_SDHCI_BCM2708_DMA ++#warning Non-DMA (PIO) version of this driver currently unavailable ++#endif ++#undef CONFIG_MMC_SDHCI_BCM2708_DMA ++#define CONFIG_MMC_SDHCI_BCM2708_DMA y ++ ++#define USE_SYNC_AFTER_DMA ++#ifdef CONFIG_MMC_SDHCI_BCM2708_DMA ++/* #define CHECK_DMA_USE */ ++#endif ++//#define LOG_REGISTERS ++ ++#define USE_SCHED_TIME ++ ++#define SDHCI_BCM_DMA_CHAN 4 /* this default is normally overriden */ ++#define SDHCI_BCM_DMA_WAITS 0 /* delays slowing DMA transfers: 0-31 */ ++/* We are worried that SD card DMA use may be blocking the AXI bus for others */ ++ ++/*! TODO: obtain these from the physical address */ ++#define DMA_SDHCI_BASE 0x7e300000 /* EMMC register block on Videocore */ ++#define DMA_SDHCI_BUFFER (DMA_SDHCI_BASE + SDHCI_BUFFER) ++ ++#define BCM2708_SDHCI_SLEEP_TIMEOUT 1000 /* msecs */ ++ ++#define POWER_OFF 0 ++#define POWER_LAZY_OFF 1 ++#define POWER_ON 2 ++ ++ ++/*****************************************************************************\ ++ * * ++ * Debug * ++ * * ++\*****************************************************************************/ ++ ++ ++ ++#define DBG(f, x...) \ ++ pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x) ++// printk(KERN_INFO DRIVER_NAME " [%s()]: " f, __func__,## x)//GRAYG ++ ++ ++/*****************************************************************************\ ++ * * ++ * High Precision Time * ++ * * ++\*****************************************************************************/ ++ ++#ifdef USE_SCHED_TIME ++ ++#include ++ ++typedef unsigned long hptime_t; ++ ++#define FMT_HPT "lu" ++ ++static inline hptime_t hptime(void) ++{ ++ return frc_clock_ticks32(); ++} ++ ++#define HPTIME_CLK_NS 1000ul ++ ++#else ++ ++typedef unsigned long hptime_t; ++ ++#define FMT_HPT "lu" ++ ++static inline hptime_t hptime(void) ++{ ++ return jiffies; ++} ++ ++#define HPTIME_CLK_NS (1000000000ul/HZ) ++ ++#endif ++ ++static inline unsigned long int since_ns(hptime_t t) ++{ ++ return (unsigned long)((hptime() - t) * HPTIME_CLK_NS); ++} ++ ++#if 0 ++static void hptime_test(void) ++{ ++ hptime_t now; ++ hptime_t later; ++ ++ now = hptime(); ++ msleep(10); ++ later = hptime(); ++ ++ printk(KERN_INFO DRIVER_NAME": 10ms = %"FMT_HPT" clks " ++ "(from %"FMT_HPT" to %"FMT_HPT") = %luns\n", ++ later-now, now, later, ++ (unsigned long)(HPTIME_CLK_NS * (later - now))); ++ ++ now = hptime(); ++ msleep(1000); ++ later = hptime(); ++ ++ printk(KERN_INFO DRIVER_NAME": 1s = %"FMT_HPT" clks " ++ "(from %"FMT_HPT" to %"FMT_HPT") = %luns\n", ++ later-now, now, later, ++ (unsigned long)(HPTIME_CLK_NS * (later - now))); ++} ++#endif ++ ++/*****************************************************************************\ ++ * * ++ * SDHCI core callbacks * ++ * * ++\*****************************************************************************/ ++ ++ ++#ifdef CHECK_DMA_USE ++/*#define CHECK_DMA_REG_USE*/ ++#endif ++ ++#ifdef CHECK_DMA_REG_USE ++/* we don't expect anything to be using these registers during a ++ DMA (except the IRQ status) - so check */ ++static void check_dma_reg_use(struct sdhci_host *host, int reg); ++#else ++#define check_dma_reg_use(host, reg) ++#endif ++ ++ ++static inline u32 sdhci_bcm2708_raw_readl(struct sdhci_host *host, int reg) ++{ ++ return readl(host->ioaddr + reg); ++} ++ ++u32 sdhci_bcm2708_readl(struct sdhci_host *host, int reg) ++{ ++ u32 l = sdhci_bcm2708_raw_readl(host, reg); ++ ++#ifdef LOG_REGISTERS ++ printk(KERN_ERR "%s: readl from 0x%02x, value 0x%08x\n", ++ mmc_hostname(host->mmc), reg, l); ++#endif ++ check_dma_reg_use(host, reg); ++ ++ return l; ++} ++ ++u16 sdhci_bcm2708_readw(struct sdhci_host *host, int reg) ++{ ++ u32 l = sdhci_bcm2708_raw_readl(host, reg & ~3); ++ u32 w = l >> (reg << 3 & 0x18) & 0xffff; ++ ++#ifdef LOG_REGISTERS ++ printk(KERN_ERR "%s: readw from 0x%02x, value 0x%04x\n", ++ mmc_hostname(host->mmc), reg, w); ++#endif ++ check_dma_reg_use(host, reg); ++ ++ return (u16)w; ++} ++ ++u8 sdhci_bcm2708_readb(struct sdhci_host *host, int reg) ++{ ++ u32 l = sdhci_bcm2708_raw_readl(host, reg & ~3); ++ u32 b = l >> (reg << 3 & 0x18) & 0xff; ++ ++#ifdef LOG_REGISTERS ++ printk(KERN_ERR "%s: readb from 0x%02x, value 0x%02x\n", ++ mmc_hostname(host->mmc), reg, b); ++#endif ++ check_dma_reg_use(host, reg); ++ ++ return (u8)b; ++} ++ ++ ++static void sdhci_bcm2708_raw_writel(struct sdhci_host *host, u32 val, int reg) ++{ ++ /* The Arasan has a bugette whereby it may lose the content of ++ * successive writes to registers that are within two SD-card clock ++ * cycles of each other (a clock domain crossing problem). ++ * It seems, however, that the data register does not have this problem. ++ * (Which is just as well - otherwise we'd have to nobble the DMA engine ++ * too) ++ */ ++#if 1 ++ if (reg != SDHCI_BUFFER && host->clock != 0) { ++ /* host->clock is the clock freq in Hz */ ++ static hptime_t last_write_hpt; ++ hptime_t now = hptime(); ++ unsigned int ns_2clk = 2000000000/host->clock; ++ ++ if (now == last_write_hpt || now == last_write_hpt+1) { ++ /* we can't guarantee any significant time has ++ * passed - we'll have to wait anyway ! */ ++ udelay((ns_2clk+1000-1)/1000); ++ } else ++ { ++ /* we must have waited at least this many ns: */ ++ unsigned int ns_wait = HPTIME_CLK_NS * ++ (last_write_hpt - now - 1); ++ if (ns_wait < ns_2clk) ++ udelay((ns_2clk-ns_wait+500)/1000); ++ } ++ last_write_hpt = now; ++ } ++ writel(val, host->ioaddr + reg); ++#else ++ void __iomem * regaddr = host->ioaddr + reg; ++ ++ writel(val, regaddr); ++ ++ if (reg != SDHCI_BUFFER && reg != SDHCI_INT_STATUS && host->clock != 0) ++ { ++ int timeout = 100000; ++ while (val != readl(regaddr) && --timeout > 0) ++ continue; ++ ++ if (timeout <= 0) ++ printk(KERN_ERR "%s: writing 0x%X to reg 0x%X " ++ "always gives 0x%X\n", ++ mmc_hostname(host->mmc), ++ val, reg, readl(regaddr)); ++ BUG_ON(timeout <= 0); ++ } ++#endif ++} ++ ++ ++void sdhci_bcm2708_writel(struct sdhci_host *host, u32 val, int reg) ++{ ++#ifdef LOG_REGISTERS ++ printk(KERN_ERR "%s: writel to 0x%02x, value 0x%08x\n", ++ mmc_hostname(host->mmc), reg, val); ++#endif ++ check_dma_reg_use(host, reg); ++ ++ sdhci_bcm2708_raw_writel(host, val, reg); ++} ++ ++void sdhci_bcm2708_writew(struct sdhci_host *host, u16 val, int reg) ++{ ++ static u32 shadow = 0; ++ ++ u32 p = reg == SDHCI_COMMAND ? shadow : ++ sdhci_bcm2708_raw_readl(host, reg & ~3); ++ u32 s = reg << 3 & 0x18; ++ u32 l = val << s; ++ u32 m = 0xffff << s; ++ ++#ifdef LOG_REGISTERS ++ printk(KERN_ERR "%s: writew to 0x%02x, value 0x%04x\n", ++ mmc_hostname(host->mmc), reg, val); ++#endif ++ ++ if (reg == SDHCI_TRANSFER_MODE) ++ shadow = (p & ~m) | l; ++ else { ++ check_dma_reg_use(host, reg); ++ sdhci_bcm2708_raw_writel(host, (p & ~m) | l, reg & ~3); ++ } ++} ++ ++void sdhci_bcm2708_writeb(struct sdhci_host *host, u8 val, int reg) ++{ ++ u32 p = sdhci_bcm2708_raw_readl(host, reg & ~3); ++ u32 s = reg << 3 & 0x18; ++ u32 l = val << s; ++ u32 m = 0xff << s; ++ ++#ifdef LOG_REGISTERS ++ printk(KERN_ERR "%s: writeb to 0x%02x, value 0x%02x\n", ++ mmc_hostname(host->mmc), reg, val); ++#endif ++ ++ check_dma_reg_use(host, reg); ++ sdhci_bcm2708_raw_writel(host, (p & ~m) | l, reg & ~3); ++} ++ ++static unsigned int sdhci_bcm2708_get_max_clock(struct sdhci_host *host) ++{ ++ return 100000000; // this value is in Hz (100MHz/4) ++} ++ ++static unsigned int sdhci_bcm2708_get_timeout_clock(struct sdhci_host *host) ++{ ++ return 100000; // this value is in kHz (100MHz/4) ++} ++ ++/*****************************************************************************\ ++ * * ++ * DMA Operation * ++ * * ++\*****************************************************************************/ ++ ++struct sdhci_bcm2708_priv { ++ int dma_chan; ++ int dma_irq; ++ void __iomem *dma_chan_base; ++ struct bcm2708_dma_cb *cb_base; /* DMA control blocks */ ++ dma_addr_t cb_handle; ++ /* tracking scatter gather progress */ ++ unsigned sg_ix; /* scatter gather list index */ ++ unsigned sg_done; /* bytes in current sg_ix done */ ++ /* power management */ ++ BCM_POWER_HANDLE_T power_handle; ++ unsigned char power_state; /* enable/disable power state */ ++ unsigned char power_mode; /* last set power mode */ ++#ifdef CONFIG_MMC_SDHCI_BCM2708_DMA ++ unsigned char dma_wanted; /* DMA transfer requested */ ++ unsigned char dma_waits; /* wait states in DMAs */ ++#ifdef CHECK_DMA_USE ++ unsigned char dmas_pending; /* no of unfinished DMAs */ ++ hptime_t when_started; ++ hptime_t when_reset; ++ hptime_t when_stopped; ++#endif ++#endif ++ /* signalling the end of a transfer */ ++ void (*complete)(struct sdhci_host *); ++}; ++ ++#define SDHCI_HOST_PRIV(host) \ ++ (struct sdhci_bcm2708_priv *)((struct sdhci_host *)(host)+1) ++ ++ ++ ++#ifdef CHECK_DMA_REG_USE ++static void check_dma_reg_use(struct sdhci_host *host, int reg) ++{ ++ struct sdhci_bcm2708_priv *host_priv = SDHCI_HOST_PRIV(host); ++ if (host_priv->dma_wanted && reg != SDHCI_INT_STATUS) { ++ printk(KERN_INFO"%s: accessing register 0x%x during DMA\n", ++ mmc_hostname(host->mmc), reg); ++ } ++} ++#endif ++ ++ ++ ++#ifdef CONFIG_MMC_SDHCI_BCM2708_DMA ++ ++static void sdhci_clear_set_irqgen(struct sdhci_host *host, u32 clear, u32 set) ++{ ++ u32 ier; ++ ++ ier = sdhci_bcm2708_raw_readl(host, SDHCI_SIGNAL_ENABLE); ++ ier &= ~clear; ++ ier |= set; ++ /* change which requests generate IRQs - makes no difference to ++ the content of SDHCI_INT_STATUS, or the need to acknowledge IRQs */ ++ sdhci_bcm2708_raw_writel(host, ier, SDHCI_SIGNAL_ENABLE); ++} ++ ++static void sdhci_signal_irqs(struct sdhci_host *host, u32 irqs) ++{ ++ sdhci_clear_set_irqgen(host, 0, irqs); ++} ++ ++static void sdhci_unsignal_irqs(struct sdhci_host *host, u32 irqs) ++{ ++ sdhci_clear_set_irqgen(host, irqs, 0); ++} ++ ++ ++ ++static void schci_bcm2708_cb_read(struct sdhci_bcm2708_priv *host, ++ int ix, ++ dma_addr_t dma_addr, unsigned len, ++ int /*bool*/ is_last) ++{ ++ struct bcm2708_dma_cb *cb = &host->cb_base[ix]; ++ unsigned char dmawaits = host->dma_waits; ++ ++ cb->info = BCM2708_DMA_PER_MAP(BCM2708_DMA_DREQ_EMMC) | ++ BCM2708_DMA_WAITS(dmawaits) | ++ BCM2708_DMA_S_DREQ | ++ BCM2708_DMA_D_WIDTH | ++ BCM2708_DMA_D_INC; ++ cb->src = DMA_SDHCI_BUFFER; /* DATA register DMA address */ ++ cb->dst = dma_addr; ++ cb->length = len; ++ cb->stride = 0; ++ ++ if (is_last) { ++ cb->info |= BCM2708_DMA_INT_EN; ++ cb->next = 0; ++ } else ++ cb->next = host->cb_handle + ++ (ix+1)*sizeof(struct bcm2708_dma_cb); ++ ++ cb->pad[0] = 0; ++ cb->pad[1] = 0; ++} ++ ++static void schci_bcm2708_cb_write(struct sdhci_bcm2708_priv *host, ++ int ix, ++ dma_addr_t dma_addr, unsigned len, ++ int /*bool*/ is_last) ++{ ++ struct bcm2708_dma_cb *cb = &host->cb_base[ix]; ++ unsigned char dmawaits = host->dma_waits; ++ ++ /* We can make arbitrarily large writes as long as we specify DREQ to ++ pace the delivery of bytes to the Arasan hardware */ ++ cb->info = BCM2708_DMA_PER_MAP(BCM2708_DMA_DREQ_EMMC) | ++ BCM2708_DMA_WAITS(dmawaits) | ++ BCM2708_DMA_D_DREQ | ++ BCM2708_DMA_S_WIDTH | ++ BCM2708_DMA_S_INC; ++ cb->src = dma_addr; ++ cb->dst = DMA_SDHCI_BUFFER; /* DATA register DMA address */ ++ cb->length = len; ++ cb->stride = 0; ++ ++ if (is_last) { ++ cb->info |= BCM2708_DMA_INT_EN; ++ cb->next = 0; ++ } else ++ cb->next = host->cb_handle + ++ (ix+1)*sizeof(struct bcm2708_dma_cb); ++ ++ cb->pad[0] = 0; ++ cb->pad[1] = 0; ++} ++ ++ ++static void schci_bcm2708_dma_go(struct sdhci_host *host) ++{ ++ struct sdhci_bcm2708_priv *host_priv = SDHCI_HOST_PRIV(host); ++ void __iomem *dma_chan_base = host_priv->dma_chan_base; ++ ++ BUG_ON(host_priv->dma_wanted); ++#ifdef CHECK_DMA_USE ++ if (host_priv->dma_wanted) ++ printk(KERN_ERR "%s: DMA already in progress - " ++ "now %"FMT_HPT", last started %lu " ++ "reset %lu stopped %lu\n", ++ mmc_hostname(host->mmc), ++ hptime(), since_ns(host_priv->when_started), ++ since_ns(host_priv->when_reset), ++ since_ns(host_priv->when_stopped)); ++ else if (host_priv->dmas_pending > 0) ++ printk(KERN_INFO "%s: note - new DMA when %d reset DMAs " ++ "already in progress - " ++ "now %"FMT_HPT", started %lu reset %lu stopped %lu\n", ++ mmc_hostname(host->mmc), ++ host_priv->dmas_pending, ++ hptime(), since_ns(host_priv->when_started), ++ since_ns(host_priv->when_reset), ++ since_ns(host_priv->when_stopped)); ++ host_priv->dmas_pending += 1; ++ host_priv->when_started = hptime(); ++#endif ++ host_priv->dma_wanted = 1; ++ DBG("PDMA go - base %p handle %08X\n", dma_chan_base, ++ host_priv->cb_handle); ++ bcm_dma_start(dma_chan_base, host_priv->cb_handle); ++} ++ ++ ++static void ++sdhci_platdma_read(struct sdhci_host *host, dma_addr_t dma_addr, size_t len) ++{ ++ struct sdhci_bcm2708_priv *host_priv = SDHCI_HOST_PRIV(host); ++ ++ DBG("PDMA to read %d bytes\n", len); ++ host_priv->sg_done += len; ++ schci_bcm2708_cb_read(host_priv, 0, dma_addr, len, 1/*TRUE*/); ++ schci_bcm2708_dma_go(host); ++} ++ ++ ++static void ++sdhci_platdma_write(struct sdhci_host *host, dma_addr_t dma_addr, size_t len) ++{ ++ struct sdhci_bcm2708_priv *host_priv = SDHCI_HOST_PRIV(host); ++ ++ DBG("PDMA to write %d bytes\n", len); ++ //BUG_ON(0 != (len & 0x1ff)); ++ ++ host_priv->sg_done += len; ++ schci_bcm2708_cb_write(host_priv, 0, dma_addr, len, 1/*TRUE*/); ++ schci_bcm2708_dma_go(host); ++} ++ ++/*! space is avaiable to receive into or data is available to write ++ Platform DMA exported function ++*/ ++void ++sdhci_bcm2708_platdma_avail(struct sdhci_host *host, unsigned int *ref_intmask, ++ void(*completion_callback)(struct sdhci_host *host)) ++{ ++ struct mmc_data *data = host->data; ++ struct sdhci_bcm2708_priv *host_priv = SDHCI_HOST_PRIV(host); ++ int sg_ix; ++ size_t bytes; ++ dma_addr_t addr; ++ ++ BUG_ON(NULL == data); ++ BUG_ON(0 == data->blksz); ++ ++ host_priv->complete = completion_callback; ++ ++ sg_ix = host_priv->sg_ix; ++ BUG_ON(sg_ix >= data->sg_len); ++ ++ /* we can DMA blocks larger than blksz - it may hang the DMA ++ channel but we are its only user */ ++ bytes = sg_dma_len(&data->sg[sg_ix]) - host_priv->sg_done; ++ addr = sg_dma_address(&data->sg[sg_ix]) + host_priv->sg_done; ++ ++ if (bytes > 0) { ++ /* We're going to poll for read/write available state until ++ we finish this DMA ++ */ ++ ++ if (data->flags & MMC_DATA_READ) { ++ if (*ref_intmask & SDHCI_INT_DATA_AVAIL) { ++ sdhci_unsignal_irqs(host, SDHCI_INT_DATA_AVAIL | ++ SDHCI_INT_SPACE_AVAIL); ++ sdhci_platdma_read(host, addr, bytes); ++ } ++ } else { ++ if (*ref_intmask & SDHCI_INT_SPACE_AVAIL) { ++ sdhci_unsignal_irqs(host, SDHCI_INT_DATA_AVAIL | ++ SDHCI_INT_SPACE_AVAIL); ++ sdhci_platdma_write(host, addr, bytes); ++ } ++ } ++ } ++ /* else: ++ we have run out of bytes that need transferring (e.g. we may be in ++ the middle of the last DMA transfer), or ++ it is also possible that we've been called when another IRQ is ++ signalled, even though we've turned off signalling of our own IRQ */ ++ ++ *ref_intmask &= ~SDHCI_INT_DATA_END; ++ /* don't let the main sdhci driver act on this .. we'll deal with it ++ when we respond to the DMA - if one is currently in progress */ ++} ++ ++/* is it possible to DMA the given mmc_data structure? ++ Platform DMA exported function ++*/ ++int /*bool*/ ++sdhci_bcm2708_platdma_dmaable(struct sdhci_host *host, struct mmc_data *data) ++{ ++ struct sdhci_bcm2708_priv *host_priv = SDHCI_HOST_PRIV(host); ++ int ok = bcm_sg_suitable_for_dma(data->sg, data->sg_len); ++ ++ if (!ok) ++ DBG("Reverting to PIO - bad cache alignment\n"); ++ ++ else { ++ host_priv->sg_ix = 0; /* first SG index */ ++ host_priv->sg_done = 0; /* no bytes done */ ++ } ++ ++ return ok; ++} ++ ++#include //GRAYG ++/*! the current SD transacton has been abandonned ++ We need to tidy up if we were in the middle of a DMA ++ Platform DMA exported function ++*/ ++void ++sdhci_bcm2708_platdma_reset(struct sdhci_host *host, struct mmc_data *data) ++{ ++ struct sdhci_bcm2708_priv *host_priv = SDHCI_HOST_PRIV(host); ++ unsigned long flags; ++ ++ BUG_ON(NULL == host); ++ ++ spin_lock_irqsave(&host->lock, flags); ++ ++ if (host_priv->dma_wanted) { ++ if (NULL == data) { ++ printk(KERN_ERR "%s: ongoing DMA reset - no data!\n", ++ mmc_hostname(host->mmc)); ++ BUG_ON(NULL == data); ++ } else { ++ struct scatterlist *sg; ++ int sg_len; ++ int sg_todo; ++ int rc; ++ unsigned long cs; ++ ++ sg = data->sg; ++ sg_len = data->sg_len; ++ sg_todo = sg_dma_len(&sg[host_priv->sg_ix]); ++ ++ cs = readl(host_priv->dma_chan_base + BCM2708_DMA_CS); ++ ++ if (!(BCM2708_DMA_ACTIVE & cs)) ++ printk(KERN_INFO "%s: missed completion of " ++ "cmd %d DMA (%d/%d [%d]/[%d]) - " ++ "ignoring it\n", ++ mmc_hostname(host->mmc), ++ host->last_cmdop, ++ host_priv->sg_done, sg_todo, ++ host_priv->sg_ix+1, sg_len); ++ else ++ printk(KERN_INFO "%s: resetting ongoing cmd %d" ++ "DMA before %d/%d [%d]/[%d] complete\n", ++ mmc_hostname(host->mmc), ++ host->last_cmdop, ++ host_priv->sg_done, sg_todo, ++ host_priv->sg_ix+1, sg_len); ++#ifdef CHECK_DMA_USE ++ printk(KERN_INFO "%s: now %"FMT_HPT" started %lu " ++ "last reset %lu last stopped %lu\n", ++ mmc_hostname(host->mmc), ++ hptime(), since_ns(host_priv->when_started), ++ since_ns(host_priv->when_reset), ++ since_ns(host_priv->when_stopped)); ++ { unsigned long info, debug; ++ void __iomem *base; ++ unsigned long pend0, pend1, pend2; ++ ++ base = host_priv->dma_chan_base; ++ cs = readl(base + BCM2708_DMA_CS); ++ info = readl(base + BCM2708_DMA_INFO); ++ debug = readl(base + BCM2708_DMA_DEBUG); ++ printk(KERN_INFO "%s: DMA%d CS=%08lX TI=%08lX " ++ "DEBUG=%08lX\n", ++ mmc_hostname(host->mmc), ++ host_priv->dma_chan, ++ cs, info, debug); ++ pend0 = readl(__io_address(ARM_IRQ_PEND0)); ++ pend1 = readl(__io_address(ARM_IRQ_PEND1)); ++ pend2 = readl(__io_address(ARM_IRQ_PEND2)); ++ ++ printk(KERN_INFO "%s: PEND0=%08lX " ++ "PEND1=%08lX PEND2=%08lX\n", ++ mmc_hostname(host->mmc), ++ pend0, pend1, pend2); ++ ++ //gintsts = readl(__io_address(GINTSTS)); ++ //gintmsk = readl(__io_address(GINTMSK)); ++ //printk(KERN_INFO "%s: USB GINTSTS=%08lX" ++ // "GINTMSK=%08lX\n", ++ // mmc_hostname(host->mmc), gintsts, gintmsk); ++ } ++#endif ++ rc = bcm_dma_abort(host_priv->dma_chan_base); ++ BUG_ON(rc != 0); ++ } ++ host_priv->dma_wanted = 0; ++#ifdef CHECK_DMA_USE ++ host_priv->when_reset = hptime(); ++#endif ++ } ++ ++ spin_unlock_irqrestore(&host->lock, flags); ++} ++ ++ ++static void sdhci_bcm2708_dma_complete_irq(struct sdhci_host *host, ++ u32 dma_cs) ++{ ++ struct sdhci_bcm2708_priv *host_priv = SDHCI_HOST_PRIV(host); ++ struct mmc_data *data; ++ struct scatterlist *sg; ++ int sg_len; ++ int sg_ix; ++ int sg_todo; ++ unsigned long flags; ++ ++ BUG_ON(NULL == host); ++ ++ spin_lock_irqsave(&host->lock, flags); ++ data = host->data; ++ ++#ifdef CHECK_DMA_USE ++ if (host_priv->dmas_pending <= 0) ++ DBG("on completion no DMA in progress - " ++ "now %"FMT_HPT" started %lu reset %lu stopped %lu\n", ++ hptime(), since_ns(host_priv->when_started), ++ since_ns(host_priv->when_reset), ++ since_ns(host_priv->when_stopped)); ++ else if (host_priv->dmas_pending > 1) ++ DBG("still %d DMA in progress after completion - " ++ "now %"FMT_HPT" started %lu reset %lu stopped %lu\n", ++ host_priv->dmas_pending - 1, ++ hptime(), since_ns(host_priv->when_started), ++ since_ns(host_priv->when_reset), ++ since_ns(host_priv->when_stopped)); ++ BUG_ON(host_priv->dmas_pending <= 0); ++ host_priv->dmas_pending -= 1; ++ host_priv->when_stopped = hptime(); ++#endif ++ host_priv->dma_wanted = 0; ++ ++ if (NULL == data) { ++ DBG("PDMA unused completion - status 0x%X\n", dma_cs); ++ spin_unlock_irqrestore(&host->lock, flags); ++ return; ++ } ++ sg = data->sg; ++ sg_len = data->sg_len; ++ sg_todo = sg_dma_len(&sg[host_priv->sg_ix]); ++ ++ DBG("PDMA complete %d/%d [%d]/[%d]..\n", ++ host_priv->sg_done, sg_todo, ++ host_priv->sg_ix+1, sg_len); ++ ++ BUG_ON(host_priv->sg_done > sg_todo); ++ ++ if (host_priv->sg_done >= sg_todo) { ++ host_priv->sg_ix++; ++ host_priv->sg_done = 0; ++ } ++ ++ sg_ix = host_priv->sg_ix; ++ if (sg_ix < sg_len) { ++ u32 irq_mask; ++ /* Set off next DMA if we've got the capacity */ ++ ++ if (data->flags & MMC_DATA_READ) ++ irq_mask = SDHCI_INT_DATA_AVAIL; ++ else ++ irq_mask = SDHCI_INT_SPACE_AVAIL; ++ ++ /* We have to use the interrupt status register on the BCM2708 ++ rather than the SDHCI_PRESENT_STATE register because latency ++ in the glue logic means that the information retrieved from ++ the latter is not always up-to-date w.r.t the DMA engine - ++ it may not indicate that a read or a write is ready yet */ ++ if (sdhci_bcm2708_raw_readl(host, SDHCI_INT_STATUS) & ++ irq_mask) { ++ size_t bytes = sg_dma_len(&sg[sg_ix]) - ++ host_priv->sg_done; ++ dma_addr_t addr = sg_dma_address(&data->sg[sg_ix]) + ++ host_priv->sg_done; ++ ++ /* acknowledge interrupt */ ++ sdhci_bcm2708_raw_writel(host, irq_mask, ++ SDHCI_INT_STATUS); ++ ++ BUG_ON(0 == bytes); ++ ++ if (data->flags & MMC_DATA_READ) ++ sdhci_platdma_read(host, addr, bytes); ++ else ++ sdhci_platdma_write(host, addr, bytes); ++ } else { ++ DBG("PDMA - wait avail\n"); ++ /* may generate an IRQ if already present */ ++ sdhci_signal_irqs(host, SDHCI_INT_DATA_AVAIL | ++ SDHCI_INT_SPACE_AVAIL); ++ } ++ } else { ++#ifdef USE_SYNC_AFTER_DMA ++ /* On the Arasan controller the stop command (which will be ++ scheduled after this completes) does not seem to work ++ properly if we allow it to be issued when we are ++ transferring data to/from the SD card. ++ We get CRC and DEND errors unless we wait for ++ the SD controller to finish reading/writing to the card. */ ++ u32 state_mask; ++ int timeout=1000000; ++ hptime_t now = hptime(); ++ ++ DBG("PDMA over - sync card\n"); ++ if (data->flags & MMC_DATA_READ) ++ state_mask = SDHCI_DOING_READ; ++ else ++ state_mask = SDHCI_DOING_WRITE; ++ ++ while (0 != (sdhci_bcm2708_raw_readl(host, ++ SDHCI_PRESENT_STATE) & ++ state_mask) && --timeout > 0) ++ continue; ++ ++ if (1000000-timeout > 4000) /*ave. is about 3250*/ ++ printk(KERN_INFO "%s: note - long %s sync %luns - " ++ "%d its.\n", ++ mmc_hostname(host->mmc), ++ data->flags & MMC_DATA_READ? "read": "write", ++ since_ns(now), 1000000-timeout); ++ if (timeout <= 0) ++ printk(KERN_ERR"%s: final %s to SD card still " ++ "running\n", ++ mmc_hostname(host->mmc), ++ data->flags & MMC_DATA_READ? "read": "write"); ++#endif ++ if (host_priv->complete) { ++ (*host_priv->complete)(host); ++ DBG("PDMA %s complete\n", ++ data->flags & MMC_DATA_READ?"read":"write"); ++ sdhci_signal_irqs(host, SDHCI_INT_DATA_AVAIL | ++ SDHCI_INT_SPACE_AVAIL); ++ } ++ } ++ spin_unlock_irqrestore(&host->lock, flags); ++} ++ ++static irqreturn_t sdhci_bcm2708_dma_irq(int irq, void *dev_id) ++{ ++ irqreturn_t result = IRQ_NONE; ++ struct sdhci_host *host = dev_id; ++ struct sdhci_bcm2708_priv *host_priv = SDHCI_HOST_PRIV(host); ++ u32 dma_cs; /* control and status register */ ++ unsigned long flags; ++ ++ BUG_ON(NULL == dev_id); ++ BUG_ON(NULL == host_priv->dma_chan_base); ++ ++ spin_lock_irqsave(&host->lock, flags); ++ ++ dma_cs = readl(host_priv->dma_chan_base + BCM2708_DMA_CS); ++ ++ if (dma_cs & BCM2708_DMA_ERR) { ++ unsigned long debug; ++ debug = readl(host_priv->dma_chan_base + ++ BCM2708_DMA_DEBUG); ++ printk(KERN_ERR "%s: DMA error - CS %lX DEBUG %lX\n", ++ mmc_hostname(host->mmc), (unsigned long)dma_cs, ++ (unsigned long)debug); ++ /* reset error */ ++ writel(debug, host_priv->dma_chan_base + ++ BCM2708_DMA_DEBUG); ++ } ++ if (dma_cs & BCM2708_DMA_INT) { ++ /* acknowledge interrupt */ ++ writel(BCM2708_DMA_INT, ++ host_priv->dma_chan_base + BCM2708_DMA_CS); ++ ++ dsb(); /* ARM data synchronization (push) operation */ ++ ++ if (!host_priv->dma_wanted) { ++ /* ignore this interrupt - it was reset */ ++ printk(KERN_INFO "%s: DMA IRQ %X ignored - " ++ "results were reset\n", ++ mmc_hostname(host->mmc), dma_cs); ++#ifdef CHECK_DMA_USE ++ printk(KERN_INFO "%s: now %"FMT_HPT ++ " started %lu reset %lu stopped %lu\n", ++ mmc_hostname(host->mmc), hptime(), ++ since_ns(host_priv->when_started), ++ since_ns(host_priv->when_reset), ++ since_ns(host_priv->when_stopped)); ++ host_priv->dmas_pending--; ++#endif ++ } else ++ sdhci_bcm2708_dma_complete_irq(host, dma_cs); ++ ++ result = IRQ_HANDLED; ++ } ++ ++ spin_unlock_irqrestore(&host->lock, flags); ++ ++ return result; ++} ++#endif /* CONFIG_MMC_SDHCI_BCM2708_DMA */ ++ ++ ++/***************************************************************************** \ ++ * * ++ * Device Attributes * ++ * * ++\*****************************************************************************/ ++ ++ ++/** ++ * Show the DMA-using status ++ */ ++static ssize_t attr_dma_show(struct device *_dev, ++ struct device_attribute *attr, char *buf) ++{ ++ struct sdhci_host *host = (struct sdhci_host *)dev_get_drvdata(_dev); ++ ++ if (host) { ++ int use_dma = (host->flags & SDHCI_USE_PLATDMA? 1:0); ++ return sprintf(buf, "%d\n", use_dma); ++ } else ++ return -EINVAL; ++} ++ ++/** ++ * Set the DMA-using status ++ */ ++static ssize_t attr_dma_store(struct device *_dev, ++ struct device_attribute *attr, ++ const char *buf, size_t count) ++{ ++ struct sdhci_host *host = (struct sdhci_host *)dev_get_drvdata(_dev); ++ ++ if (host) { ++#ifdef CONFIG_MMC_SDHCI_BCM2708_DMA ++ int on = simple_strtol(buf, NULL, 0); ++ if (on) { ++ host->flags |= SDHCI_USE_PLATDMA; ++ printk(KERN_INFO "%s: DMA enabled\n", ++ mmc_hostname(host->mmc)); ++ } else { ++ host->flags &= ~(SDHCI_USE_PLATDMA | SDHCI_REQ_USE_DMA); ++ printk(KERN_INFO "%s: DMA disabled\n", ++ mmc_hostname(host->mmc)); ++ } ++#endif ++ return count; ++ } else ++ return -EINVAL; ++} ++ ++static DEVICE_ATTR(use_dma, S_IRUGO | S_IWUGO, attr_dma_show, attr_dma_store); ++ ++ ++/** ++ * Show the DMA wait states used ++ */ ++static ssize_t attr_dmawait_show(struct device *_dev, ++ struct device_attribute *attr, char *buf) ++{ ++ struct sdhci_host *host = (struct sdhci_host *)dev_get_drvdata(_dev); ++ ++ if (host) { ++ struct sdhci_bcm2708_priv *host_priv = SDHCI_HOST_PRIV(host); ++ int dmawait = host_priv->dma_waits; ++ return sprintf(buf, "%d\n", dmawait); ++ } else ++ return -EINVAL; ++} ++ ++/** ++ * Set the DMA wait state used ++ */ ++static ssize_t attr_dmawait_store(struct device *_dev, ++ struct device_attribute *attr, ++ const char *buf, size_t count) ++{ ++ struct sdhci_host *host = (struct sdhci_host *)dev_get_drvdata(_dev); ++ ++ if (host) { ++#ifdef CONFIG_MMC_SDHCI_BCM2708_DMA ++ struct sdhci_bcm2708_priv *host_priv = SDHCI_HOST_PRIV(host); ++ int dma_waits = simple_strtol(buf, NULL, 0); ++ if (dma_waits >= 0 && dma_waits < 32) ++ host_priv->dma_waits = dma_waits; ++ else ++ printk(KERN_ERR "%s: illegal dma_waits value - %d", ++ mmc_hostname(host->mmc), dma_waits); ++#endif ++ return count; ++ } else ++ return -EINVAL; ++} ++ ++static DEVICE_ATTR(dma_wait, S_IRUGO | S_IWUGO, ++ attr_dmawait_show, attr_dmawait_store); ++ ++ ++/** ++ * Show the DMA-using status ++ */ ++static ssize_t attr_status_show(struct device *_dev, ++ struct device_attribute *attr, char *buf) ++{ ++ struct sdhci_host *host = (struct sdhci_host *)dev_get_drvdata(_dev); ++ ++ if (host) { ++ struct sdhci_bcm2708_priv *host_priv = SDHCI_HOST_PRIV(host); ++ int power_state = host_priv->power_state; ++ return sprintf(buf, ++ "present: yes\n" ++ "power: %s\n" ++ "clock: %u Hz\n" ++#ifdef CONFIG_MMC_SDHCI_BCM2708_DMA ++ "dma: %s (%d waits)\n", ++#else ++ "dma: unconfigured\n", ++#endif ++ power_state == POWER_ON? "on": ++ power_state == POWER_OFF? "off": ++ power_state == POWER_LAZY_OFF? "lazy-off": ++ "", ++ host->clock ++#ifdef CONFIG_MMC_SDHCI_BCM2708_DMA ++ , (host->flags & SDHCI_USE_PLATDMA)? "on": "off" ++ , host_priv->dma_waits ++#endif ++ ); ++ } else ++ return -EINVAL; ++} ++ ++static DEVICE_ATTR(status, S_IRUGO, attr_status_show, NULL); ++ ++/***************************************************************************** \ ++ * * ++ * Power Management * ++ * * ++\*****************************************************************************/ ++ ++ ++#ifdef CONFIG_PM ++static int sdhci_bcm2708_suspend(struct platform_device *dev, pm_message_t state) ++{ ++ struct sdhci_host *host = (struct sdhci_host *) ++ platform_get_drvdata(dev); ++ int ret = 0; ++ ++ if (host->mmc) { ++ ret = mmc_suspend_host(host->mmc); ++ } ++ ++ return ret; ++} ++ ++static int sdhci_bcm2708_resume(struct platform_device *dev) ++{ ++ struct sdhci_host *host = (struct sdhci_host *) ++ platform_get_drvdata(dev); ++ int ret = 0; ++ ++ if (host->mmc) { ++ ret = mmc_resume_host(host->mmc); ++ } ++ ++ return ret; ++} ++#endif ++ ++ ++/* Click forwards one step towards fully on */ ++static int sdhci_bcm2708_enable(struct sdhci_host *host) ++{ ++ int rc; ++ struct sdhci_bcm2708_priv *host_priv = SDHCI_HOST_PRIV(host); ++ ++ if (host_priv->power_state == POWER_OFF) { ++ /* warning: may schedule - don't call in irq mode */ ++ rc = bcm_power_request(host_priv->power_handle, ++ BCM_POWER_SDCARD); ++ ++ if (rc == 0) { ++ mmc_power_restore_host(host->mmc); ++ host_priv->power_state = POWER_ON; ++ } else if (rc != -EINTR) ++ printk(KERN_ERR "%s: mmc power up request failed - " ++ "rc %d\n", ++ mmc_hostname(host->mmc), rc); ++ } else { ++ host_priv->power_state = POWER_ON; ++ rc = 0; ++ } ++ ++ return rc; ++} ++ ++/* Click backwards one step towards fully off */ ++static int sdhci_bcm2708_disable(struct sdhci_host *host, int lazy) ++{ ++ int rc; ++ struct sdhci_bcm2708_priv *host_priv = SDHCI_HOST_PRIV(host); ++ ++ if ((host_priv->power_state == POWER_ON) && lazy) { ++ host_priv->power_state = POWER_LAZY_OFF; ++ return BCM2708_SDHCI_SLEEP_TIMEOUT; ++ } ++ ++ /* warning: may schedule - don't call in irq mode */ ++ rc = bcm_power_request(host_priv->power_handle, BCM_POWER_NONE); ++ ++ if (rc == 0) ++ host_priv->power_state = POWER_OFF; ++ else if (rc != -EINTR) ++ printk(KERN_ERR "%s: mmc power down request failed - rc %d\n", ++ mmc_hostname(host->mmc), rc); ++ ++ return rc; ++} ++ ++static int sdhci_bcm2708_set_plat_power(struct sdhci_host *host, ++ int power_mode) ++{ ++ struct sdhci_bcm2708_priv *host_priv = SDHCI_HOST_PRIV(host); ++ int rc; ++ ++ do { ++ rc = mmc_host_enable(host->mmc); ++ } while (-EINTR == rc); ++ ++ if (rc == 0) do { ++ if (rc == 0 && power_mode != host_priv->power_mode) ++ { ++ switch (power_mode) ++ { ++ case MMC_POWER_OFF: ++ rc = bcm_power_request(host_priv->power_handle, ++ BCM_POWER_NONE); ++ break; ++ ++ case MMC_POWER_UP: ++ rc = bcm_power_request(host_priv->power_handle, ++ BCM_POWER_SDCARD); ++ /* ++ * We need an extra 10ms delay of 10ms before we ++ * can apply clock after applying power ++ */ ++ if (rc == 0) ++ mdelay(10); ++ break; ++ ++ case MMC_POWER_ON: ++ mdelay(10); ++ /* do_send_init_stream = 1; */ ++ break; ++ } ++ ++ if (rc == 0) ++ host_priv->power_mode = power_mode; ++ } ++ } while (-EINTR == rc); ++ ++ if (rc == 0) do { ++ if (rc == 0) { ++ if (power_mode == MMC_POWER_OFF) ++ rc = mmc_host_disable(host->mmc); ++ else ++ rc = mmc_host_lazy_disable(host->mmc); ++ } ++ ++ } while (-EINTR == rc); ++ ++ return rc; ++} ++ ++/*****************************************************************************\ ++ * * ++ * Device quirk functions. Implemented as local ops because the flags * ++ * field is out of space with newer kernels. This implementation can be * ++ * back ported to older kernels as well. * ++\****************************************************************************/ ++static unsigned int sdhci_bcm2708_quirk_extra_ints(struct sdhci_host *host) ++{ ++ return 1; ++} ++ ++static unsigned int sdhci_bcm2708_quirk_spurious_crc(struct sdhci_host *host) ++{ ++ return 1; ++} ++ ++static unsigned int sdhci_bcm2708_quirk_voltage_broken(struct sdhci_host *host) ++{ ++ return 1; ++} ++ ++static unsigned int sdhci_bcm2708_uhs_broken(struct sdhci_host *host) ++{ ++ return 1; ++} ++ ++/***************************************************************************** \ ++ * * ++ * Device ops * ++ * * ++\*****************************************************************************/ ++ ++static struct sdhci_ops sdhci_bcm2708_ops = { ++#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS ++ .read_l = sdhci_bcm2708_readl, ++ .read_w = sdhci_bcm2708_readw, ++ .read_b = sdhci_bcm2708_readb, ++ .write_l = sdhci_bcm2708_writel, ++ .write_w = sdhci_bcm2708_writew, ++ .write_b = sdhci_bcm2708_writeb, ++#else ++#error The BCM2708 SDHCI driver needs CONFIG_MMC_SDHCI_IO_ACCESSORS to be set ++#endif ++ //.enable_dma = NULL, ++ //.set_clock = NULL, ++ .get_max_clock = sdhci_bcm2708_get_max_clock, ++ //.get_min_clock = NULL, ++ .get_timeout_clock = sdhci_bcm2708_get_timeout_clock, ++ ++ .enable = sdhci_bcm2708_enable, ++ .disable = sdhci_bcm2708_disable, ++ .set_plat_power = sdhci_bcm2708_set_plat_power, ++ ++#ifdef CONFIG_MMC_SDHCI_BCM2708_DMA ++ // Platform DMA operations ++ .pdma_able = sdhci_bcm2708_platdma_dmaable, ++ .pdma_avail = sdhci_bcm2708_platdma_avail, ++ .pdma_reset = sdhci_bcm2708_platdma_reset, ++#endif ++ .extra_ints = sdhci_bcm2708_quirk_extra_ints, ++ .spurious_crc_acmd51 = sdhci_bcm2708_quirk_spurious_crc, ++ .voltage_broken = sdhci_bcm2708_quirk_voltage_broken, ++ .uhs_broken = sdhci_bcm2708_uhs_broken, ++}; ++ ++/*****************************************************************************\ ++ * * ++ * Device probing/removal * ++ * * ++\*****************************************************************************/ ++ ++static int __devinit sdhci_bcm2708_probe(struct platform_device *pdev) ++{ ++ struct sdhci_host *host; ++ struct resource *iomem; ++ struct sdhci_bcm2708_priv *host_priv; ++ int ret; ++ ++ BUG_ON(pdev == NULL); ++ ++ iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ if (!iomem) { ++ ret = -ENOMEM; ++ goto err; ++ } ++ ++ if (resource_size(iomem) != 0x100) ++ dev_err(&pdev->dev, "Invalid iomem size. You may " ++ "experience problems.\n"); ++ ++ if (pdev->dev.parent) ++ host = sdhci_alloc_host(pdev->dev.parent, ++ sizeof(struct sdhci_bcm2708_priv)); ++ else ++ host = sdhci_alloc_host(&pdev->dev, ++ sizeof(struct sdhci_bcm2708_priv)); ++ ++ if (IS_ERR(host)) { ++ ret = PTR_ERR(host); ++ goto err; ++ } ++ ++ host->hw_name = "BCM2708_Arasan"; ++ host->ops = &sdhci_bcm2708_ops; ++ host->irq = platform_get_irq(pdev, 0); ++ ++ host->quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION | ++ SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK; ++#ifdef CONFIG_MMC_SDHCI_BCM2708_DMA ++ host->flags = SDHCI_USE_PLATDMA; ++#endif ++ ++ if (!request_mem_region(iomem->start, resource_size(iomem), ++ mmc_hostname(host->mmc))) { ++ dev_err(&pdev->dev, "cannot request region\n"); ++ ret = -EBUSY; ++ goto err_request; ++ } ++ ++ host->ioaddr = ioremap(iomem->start, resource_size(iomem)); ++ if (!host->ioaddr) { ++ dev_err(&pdev->dev, "failed to remap registers\n"); ++ ret = -ENOMEM; ++ goto err_remap; ++ } ++ ++ host_priv = SDHCI_HOST_PRIV(host); ++ ++ host_priv->power_state = POWER_ON; ++ ret = bcm_power_open(&host_priv->power_handle); ++ if (ret != 0) ++ goto err_power; ++ ++#ifdef CONFIG_MMC_SDHCI_BCM2708_DMA ++ host_priv->dma_wanted = 0; ++#ifdef CHECK_DMA_USE ++ host_priv->dmas_pending = 0; ++ host_priv->when_started = 0; ++ host_priv->when_reset = 0; ++ host_priv->when_stopped = 0; ++#endif ++ host_priv->sg_ix = 0; ++ host_priv->sg_done = 0; ++ host_priv->complete = NULL; ++ host_priv->dma_waits = SDHCI_BCM_DMA_WAITS; ++ ++ host_priv->cb_base = dma_alloc_writecombine(&pdev->dev, SZ_4K, ++ &host_priv->cb_handle, ++ GFP_KERNEL); ++ if (!host_priv->cb_base) { ++ dev_err(&pdev->dev, "cannot allocate DMA CBs\n"); ++ ret = -ENOMEM; ++ goto err_alloc_cb; ++ } ++ ++ ret = bcm_dma_chan_alloc(BCM_DMA_FEATURE_FAST, ++ &host_priv->dma_chan_base, ++ &host_priv->dma_irq); ++ if (ret < 0) { ++ dev_err(&pdev->dev, "couldn't allocate a DMA channel\n"); ++ goto err_add_dma; ++ } ++ host_priv->dma_chan = ret; ++ ++ ret = request_irq(host_priv->dma_irq, sdhci_bcm2708_dma_irq, ++ IRQF_SHARED, DRIVER_NAME " (dma)", host); ++ if (ret) { ++ dev_err(&pdev->dev, "cannot set DMA IRQ\n"); ++ goto err_add_dma_irq; ++ } ++ DBG("DMA CBs %p handle %08X DMA%d %p DMA IRQ %d\n", ++ host_priv->cb_base, (unsigned)host_priv->cb_handle, ++ host_priv->dma_chan, host_priv->dma_chan_base, ++ host_priv->dma_irq); ++#endif ++ ++ ret = sdhci_add_host(host); ++ if (ret) ++ goto err_add_host; ++ ++ platform_set_drvdata(pdev, host); ++ ret = device_create_file(&pdev->dev, &dev_attr_use_dma); ++ ret = device_create_file(&pdev->dev, &dev_attr_dma_wait); ++ ret = device_create_file(&pdev->dev, &dev_attr_status); ++ ++ printk(KERN_INFO "%s: BCM2708 SDHC host at 0x%08llx DMA %d IRQ %d\n", ++ mmc_hostname(host->mmc), (unsigned long long)iomem->start, ++ host_priv->dma_chan, host_priv->dma_irq); ++ ++ return 0; ++ ++err_add_host: ++#ifdef CONFIG_MMC_SDHCI_BCM2708_DMA ++ free_irq(host_priv->dma_irq, host); ++err_add_dma_irq: ++ bcm_dma_chan_free(host_priv->dma_chan); ++err_add_dma: ++ dma_free_writecombine(&pdev->dev, SZ_4K, host_priv->cb_base, ++ host_priv->cb_handle); ++err_alloc_cb: ++#endif ++ bcm_power_close(host_priv->power_handle); ++err_power: ++ iounmap(host->ioaddr); ++err_remap: ++ release_mem_region(iomem->start, resource_size(iomem)); ++err_request: ++ sdhci_free_host(host); ++err: ++ dev_err(&pdev->dev, "probe failed, err %d\n", ret); ++ return ret; ++} ++ ++static int __devexit sdhci_bcm2708_remove(struct platform_device *pdev) ++{ ++ struct sdhci_host *host = platform_get_drvdata(pdev); ++ struct resource *iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ struct sdhci_bcm2708_priv *host_priv = SDHCI_HOST_PRIV(host); ++ int dead; ++ u32 scratch; ++ ++ dead = 0; ++ scratch = sdhci_bcm2708_readl(host, SDHCI_INT_STATUS); ++ if (scratch == (u32)-1) ++ dead = 1; ++ ++ device_remove_file(&pdev->dev, &dev_attr_status); ++ device_remove_file(&pdev->dev, &dev_attr_dma_wait); ++ device_remove_file(&pdev->dev, &dev_attr_use_dma); ++ ++#ifdef CONFIG_MMC_SDHCI_BCM2708_DMA ++ free_irq(host_priv->dma_irq, host); ++ dma_free_writecombine(&pdev->dev, SZ_4K, host_priv->cb_base, ++ host_priv->cb_handle); ++#endif ++ bcm_power_close(host_priv->power_handle); ++ sdhci_remove_host(host, dead); ++ iounmap(host->ioaddr); ++ release_mem_region(iomem->start, resource_size(iomem)); ++ sdhci_free_host(host); ++ platform_set_drvdata(pdev, NULL); ++ ++ return 0; ++} ++ ++static struct platform_driver sdhci_bcm2708_driver = { ++ .driver = { ++ .name = DRIVER_NAME, ++ .owner = THIS_MODULE, ++ }, ++ .probe = sdhci_bcm2708_probe, ++ .remove = __devexit_p(sdhci_bcm2708_remove), ++ ++#ifdef CONFIG_PM ++ .suspend = sdhci_bcm2708_suspend, ++ .resume = sdhci_bcm2708_resume, ++#endif ++ ++}; ++ ++/*****************************************************************************\ ++ * * ++ * Driver init/exit * ++ * * ++\*****************************************************************************/ ++ ++static int __init sdhci_drv_init(void) ++{ ++ return platform_driver_register(&sdhci_bcm2708_driver); ++} ++ ++static void __exit sdhci_drv_exit(void) ++{ ++ platform_driver_unregister(&sdhci_bcm2708_driver); ++} ++ ++module_init(sdhci_drv_init); ++module_exit(sdhci_drv_exit); ++ ++MODULE_DESCRIPTION("Secure Digital Host Controller Interface platform driver"); ++MODULE_AUTHOR("Broadcom "); ++MODULE_LICENSE("GPL v2"); ++MODULE_ALIAS("platform:"DRIVER_NAME); ++ +Index: linux-3.2.46/drivers/mmc/host/sdhci.c +=================================================================== +--- linux-3.2.46.orig/drivers/mmc/host/sdhci.c 2013-05-30 13:35:16.000000000 +0000 ++++ linux-3.2.46/drivers/mmc/host/sdhci.c 2013-07-26 19:31:51.000000000 +0000 +@@ -27,6 +27,7 @@ + + #include + #include ++#include + + #include "sdhci.h" + +@@ -296,7 +297,7 @@ + u32 uninitialized_var(scratch); + u8 *buf; + +- DBG("PIO reading\n"); ++ DBG("PIO reading %db\n", host->data->blksz); + + blksize = host->data->blksz; + chunk = 0; +@@ -341,7 +342,7 @@ + u32 scratch; + u8 *buf; + +- DBG("PIO writing\n"); ++ DBG("PIO writing %db\n", host->data->blksz); + + blksize = host->data->blksz; + chunk = 0; +@@ -380,19 +381,28 @@ + local_irq_restore(flags); + } + +-static void sdhci_transfer_pio(struct sdhci_host *host) ++static void sdhci_transfer_pio(struct sdhci_host *host, u32 intstate) + { + u32 mask; ++ u32 state = 0; ++ u32 intmask; ++ int available; + + BUG_ON(!host->data); + + if (host->blocks == 0) + return; + +- if (host->data->flags & MMC_DATA_READ) ++ if (host->data->flags & MMC_DATA_READ) { + mask = SDHCI_DATA_AVAILABLE; +- else ++ intmask = SDHCI_INT_DATA_AVAIL; ++ } else { + mask = SDHCI_SPACE_AVAILABLE; ++ intmask = SDHCI_INT_SPACE_AVAIL; ++ } ++ ++ /* initially we can see whether we can procede using intstate */ ++ available = (intstate & intmask); + + /* + * Some controllers (JMicron JMB38x) mess up the buffer bits +@@ -403,7 +413,7 @@ + (host->data->blocks == 1)) + mask = ~0; + +- while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) { ++ while (available) { + if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY) + udelay(100); + +@@ -415,9 +425,11 @@ + host->blocks--; + if (host->blocks == 0) + break; ++ state = sdhci_readl(host, SDHCI_PRESENT_STATE); ++ available = state & mask; + } + +- DBG("PIO transfer complete.\n"); ++ DBG("PIO transfer complete - %d blocks left.\n", host->blocks); + } + + static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags) +@@ -690,7 +702,9 @@ + u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL; + u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR; + +- if (host->flags & SDHCI_REQ_USE_DMA) ++ /* platform DMA will begin on receipt of PIO irqs */ ++ if ((host->flags & SDHCI_REQ_USE_DMA) && ++ !(host->flags & SDHCI_USE_PLATDMA)) + sdhci_clear_set_irqs(host, pio_irqs, dma_irqs); + else + sdhci_clear_set_irqs(host, dma_irqs, pio_irqs); +@@ -722,44 +736,25 @@ + host->data_early = 0; + host->data->bytes_xfered = 0; + +- if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) ++ if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA | SDHCI_USE_PLATDMA)) + host->flags |= SDHCI_REQ_USE_DMA; + + /* + * FIXME: This doesn't account for merging when mapping the + * scatterlist. + */ +- if (host->flags & SDHCI_REQ_USE_DMA) { +- int broken, i; +- struct scatterlist *sg; +- +- broken = 0; +- if (host->flags & SDHCI_USE_ADMA) { +- if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE) +- broken = 1; +- } else { +- if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE) +- broken = 1; +- } +- +- if (unlikely(broken)) { +- for_each_sg(data->sg, sg, data->sg_len, i) { +- if (sg->length & 0x3) { +- DBG("Reverting to PIO because of " +- "transfer size (%d)\n", +- sg->length); +- host->flags &= ~SDHCI_REQ_USE_DMA; +- break; +- } +- } +- } +- } + + /* + * The assumption here being that alignment is the same after + * translation to device address space. + */ +- if (host->flags & SDHCI_REQ_USE_DMA) { ++ if ((host->flags & (SDHCI_REQ_USE_DMA | SDHCI_USE_PLATDMA)) == ++ (SDHCI_REQ_USE_DMA | SDHCI_USE_PLATDMA)) { ++ ++ if (! sdhci_platdma_dmaable(host, data)) ++ host->flags &= ~SDHCI_REQ_USE_DMA; ++ ++ } else if (host->flags & SDHCI_REQ_USE_DMA) { + int broken, i; + struct scatterlist *sg; + +@@ -818,7 +813,8 @@ + */ + WARN_ON(1); + host->flags &= ~SDHCI_REQ_USE_DMA; +- } else { ++ } else ++ if (!(host->flags & SDHCI_USE_PLATDMA)) { + WARN_ON(sg_cnt != 1); + sdhci_writel(host, sg_dma_address(data->sg), + SDHCI_DMA_ADDRESS); +@@ -834,11 +830,13 @@ + if (host->version >= SDHCI_SPEC_200) { + ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); + ctrl &= ~SDHCI_CTRL_DMA_MASK; +- if ((host->flags & SDHCI_REQ_USE_DMA) && +- (host->flags & SDHCI_USE_ADMA)) +- ctrl |= SDHCI_CTRL_ADMA32; +- else +- ctrl |= SDHCI_CTRL_SDMA; ++ if (! (host->flags & SDHCI_USE_PLATDMA)) { ++ if ((host->flags & SDHCI_REQ_USE_DMA) && ++ (host->flags & SDHCI_USE_ADMA)) ++ ctrl |= SDHCI_CTRL_ADMA32; ++ else ++ ctrl |= SDHCI_CTRL_SDMA; ++ } + sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); + } + +@@ -890,7 +888,8 @@ + + if (data->flags & MMC_DATA_READ) + mode |= SDHCI_TRNS_READ; +- if (host->flags & SDHCI_REQ_USE_DMA) ++ if ((host->flags & SDHCI_REQ_USE_DMA) && ++ !(host->flags & SDHCI_USE_PLATDMA)) + mode |= SDHCI_TRNS_DMA; + + sdhci_writew(host, mode, SDHCI_TRANSFER_MODE); +@@ -906,13 +905,16 @@ + host->data = NULL; + + if (host->flags & SDHCI_REQ_USE_DMA) { +- if (host->flags & SDHCI_USE_ADMA) +- sdhci_adma_table_post(host, data); +- else { ++ /* we may have to abandon an ongoing platform DMA */ ++ if (host->flags & SDHCI_USE_PLATDMA) ++ sdhci_platdma_reset(host, data); ++ ++ if (host->flags & (SDHCI_USE_PLATDMA | SDHCI_USE_SDMA)) { + dma_unmap_sg(mmc_dev(host->mmc), data->sg, + data->sg_len, (data->flags & MMC_DATA_READ) ? + DMA_FROM_DEVICE : DMA_TO_DEVICE); +- } ++ } else if (host->flags & SDHCI_USE_ADMA) ++ sdhci_adma_table_post(host, data); + } + + /* +@@ -965,6 +967,12 @@ + if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY)) + mask |= SDHCI_DATA_INHIBIT; + ++ if(host->ops->missing_status && (cmd->opcode == MMC_SEND_STATUS)) { ++ timeout = 5000; // Really obscenely large delay to send the status, due to bug in controller ++ // which might cause the STATUS command to get stuck when a data operation is in flow ++ mask |= SDHCI_DATA_INHIBIT; ++ } ++ + /* We shouldn't wait for data inihibit for stop commands, even + though they might use busy signaling */ + if (host->mrq->data && (cmd == host->mrq->data->stop)) +@@ -982,10 +990,16 @@ + timeout--; + mdelay(1); + } ++ DBG("send cmd %d - wait 0x%X irq 0x%x\n", cmd->opcode, mask, ++ sdhci_readl(host, SDHCI_INT_STATUS)); + + mod_timer(&host->timer, jiffies + 10 * HZ); + + host->cmd = cmd; ++ if (host->last_cmdop == MMC_APP_CMD) ++ host->last_cmdop = -cmd->opcode; ++ else ++ host->last_cmdop = cmd->opcode; + + sdhci_prepare_data(host, cmd); + +@@ -1218,6 +1232,35 @@ + mdelay(10); + } + ++/* Power on or off the circuitary supporting the register set */ ++static int sdhci_set_plat_power(struct sdhci_host *host, int power_mode) ++{ ++ if (host->ops->set_plat_power) ++ return host->ops->set_plat_power(host, power_mode); ++ else ++ return 0; ++} ++ ++/* Click forwards one step towards fully on */ ++static int sdhci_enable(struct mmc_host *mmc) ++{ ++ struct sdhci_host *host; ++ ++ host = mmc_priv(mmc); ++ ++ return host->ops->enable? host->ops->enable(host): 0; ++} ++ ++/* Click backwards one step towards fully off */ ++static int sdhci_disable(struct mmc_host *mmc, int lazy) ++{ ++ struct sdhci_host *host; ++ ++ host = mmc_priv(mmc); ++ ++ return host->ops->disable? host->ops->disable(host, lazy): 0; ++} ++ + /*****************************************************************************\ + * * + * MMC callbacks * +@@ -1298,6 +1341,7 @@ + { + unsigned long flags; + u8 ctrl; ++ int rc; + + spin_lock_irqsave(&host->lock, flags); + +@@ -1356,7 +1400,7 @@ + else + ctrl &= ~SDHCI_CTRL_HISPD; + +- if (host->version >= SDHCI_SPEC_300) { ++ if (host->version >= SDHCI_SPEC_300 && !(host->ops->uhs_broken)) { + u16 clk, ctrl_2; + unsigned int clock; + +@@ -1364,7 +1408,8 @@ + if ((ios->timing == MMC_TIMING_UHS_SDR50) || + (ios->timing == MMC_TIMING_UHS_SDR104) || + (ios->timing == MMC_TIMING_UHS_DDR50) || +- (ios->timing == MMC_TIMING_UHS_SDR25)) ++ (ios->timing == MMC_TIMING_UHS_SDR25) || ++ (ios->timing == MMC_TIMING_UHS_SDR12)) + ctrl |= SDHCI_CTRL_HISPD; + + ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); +@@ -1445,6 +1490,12 @@ + out: + mmiowb(); + spin_unlock_irqrestore(&host->lock, flags); ++ ++ if (ios->power_mode == MMC_POWER_OFF) { ++ do ++ rc = sdhci_set_plat_power(host, ios->power_mode); ++ while (rc == -EINTR); ++ } + } + + static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) +@@ -1888,6 +1939,8 @@ + .start_signal_voltage_switch = sdhci_start_signal_voltage_switch, + .execute_tuning = sdhci_execute_tuning, + .enable_preset_value = sdhci_enable_preset_value, ++ .enable = sdhci_enable, ++ .disable = sdhci_disable, + }; + + /*****************************************************************************\ +@@ -2000,7 +2053,7 @@ + + if (host->mrq) { + pr_err("%s: Timeout waiting for hardware " +- "interrupt.\n", mmc_hostname(host->mmc)); ++ "interrupt - cmd%d.\n", mmc_hostname(host->mmc), host->last_cmdop); + sdhci_dumpregs(host); + + if (host->data) { +@@ -2045,10 +2098,13 @@ + BUG_ON(intmask == 0); + + if (!host->cmd) { +- pr_err("%s: Got command interrupt 0x%08x even " +- "though no command operation was in progress.\n", +- mmc_hostname(host->mmc), (unsigned)intmask); +- sdhci_dumpregs(host); ++ if (!(host->ops->extra_ints)) { ++ pr_err("%s: Got command interrupt 0x%08x even " ++ "though no command operation was in progress.\n", ++ mmc_hostname(host->mmc), (unsigned)intmask); ++ sdhci_dumpregs(host); ++ } else ++ DBG("cmd irq 0x%08x cmd complete\n", (unsigned)intmask); + return; + } + +@@ -2118,6 +2174,19 @@ + static void sdhci_show_adma_error(struct sdhci_host *host) { } + #endif + ++static void sdhci_data_end(struct sdhci_host *host) ++{ ++ if (host->cmd) { ++ /* ++ * Data managed to finish before the ++ * command completed. Make sure we do ++ * things in the proper order. ++ */ ++ host->data_early = 1; ++ } else ++ sdhci_finish_data(host); ++} ++ + static void sdhci_data_irq(struct sdhci_host *host, u32 intmask) + { + BUG_ON(intmask == 0); +@@ -2144,34 +2213,57 @@ + return; + } + } +- +- pr_err("%s: Got data interrupt 0x%08x even " +- "though no data operation was in progress.\n", +- mmc_hostname(host->mmc), (unsigned)intmask); +- sdhci_dumpregs(host); ++ ++ if (!(host->ops->extra_ints)) { ++ pr_err("%s: Got data interrupt 0x%08x even " ++ "though no data operation was in progress.\n", ++ mmc_hostname(host->mmc), (unsigned)intmask); ++ sdhci_dumpregs(host); ++ } else ++ DBG("data irq 0x%08x but no data\n", (unsigned)intmask); + + return; + } + + if (intmask & SDHCI_INT_DATA_TIMEOUT) + host->data->error = -ETIMEDOUT; +- else if (intmask & SDHCI_INT_DATA_END_BIT) +- host->data->error = -EILSEQ; +- else if ((intmask & SDHCI_INT_DATA_CRC) && ++ else if (intmask & SDHCI_INT_DATA_END_BIT) { ++ DBG("end error in cmd %d\n", host->last_cmdop); ++ if (host->ops->spurious_crc_acmd51 && ++ host->last_cmdop == -SD_APP_SEND_SCR) { ++ DBG("ignoring spurious data_end_bit error\n"); ++ intmask = SDHCI_INT_DATA_AVAIL|SDHCI_INT_DATA_END; ++ } else ++ host->data->error = -EILSEQ; ++ } else if ((intmask & SDHCI_INT_DATA_CRC) && + SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND)) +- != MMC_BUS_TEST_R) +- host->data->error = -EILSEQ; +- else if (intmask & SDHCI_INT_ADMA_ERROR) { ++ != MMC_BUS_TEST_R) { ++ DBG("crc error in cmd %d\n", host->last_cmdop); ++ if (host->ops->spurious_crc_acmd51 && ++ host->last_cmdop == -SD_APP_SEND_SCR) { ++ DBG("ignoring spurious data_crc_bit error\n"); ++ intmask = SDHCI_INT_DATA_AVAIL|SDHCI_INT_DATA_END; ++ } else { ++ host->data->error = -EILSEQ; ++ } ++ } else if (intmask & SDHCI_INT_ADMA_ERROR) { + pr_err("%s: ADMA error\n", mmc_hostname(host->mmc)); + sdhci_show_adma_error(host); + host->data->error = -EIO; + } + +- if (host->data->error) ++ if (host->data->error) { ++ DBG("finish request early on error %d\n", host->data->error); + sdhci_finish_data(host); +- else { +- if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL)) +- sdhci_transfer_pio(host); ++ } else { ++ if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL)) { ++ if (host->flags & SDHCI_REQ_USE_DMA) { ++ /* possible only in PLATDMA mode */ ++ sdhci_platdma_avail(host, &intmask, ++ &sdhci_data_end); ++ } else ++ sdhci_transfer_pio(host, intmask); ++ } + + /* + * We currently don't do anything fancy with DMA +@@ -2200,18 +2292,8 @@ + sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS); + } + +- if (intmask & SDHCI_INT_DATA_END) { +- if (host->cmd) { +- /* +- * Data managed to finish before the +- * command completed. Make sure we do +- * things in the proper order. +- */ +- host->data_early = 1; +- } else { +- sdhci_finish_data(host); +- } +- } ++ if (intmask & SDHCI_INT_DATA_END) ++ sdhci_data_end(host); + } + } + +@@ -2266,6 +2348,22 @@ + tasklet_schedule(&host->card_tasklet); + } + ++ if (intmask & SDHCI_INT_ERROR_MASK & ~SDHCI_INT_ERROR) ++ DBG("controller reports error 0x%x -" ++ "%s%s%s%s%s%s%s%s%s%s", ++ intmask, ++ intmask & SDHCI_INT_TIMEOUT? " timeout": "", ++ intmask & SDHCI_INT_CRC ? " crc": "", ++ intmask & SDHCI_INT_END_BIT? " endbit": "", ++ intmask & SDHCI_INT_INDEX? " index": "", ++ intmask & SDHCI_INT_DATA_TIMEOUT? " data_timeout": "", ++ intmask & SDHCI_INT_DATA_CRC? " data_crc": "", ++ intmask & SDHCI_INT_DATA_END_BIT? " data_endbit": "", ++ intmask & SDHCI_INT_BUS_POWER? " buspower": "", ++ intmask & SDHCI_INT_ACMD12ERR? " acmd12": "", ++ intmask & SDHCI_INT_ADMA_ERROR? " adma": "" ++ ); ++ + if (intmask & SDHCI_INT_CMD_MASK) { + sdhci_writel(host, intmask & SDHCI_INT_CMD_MASK, + SDHCI_INT_STATUS); +@@ -2280,7 +2378,13 @@ + + intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK); + +- intmask &= ~SDHCI_INT_ERROR; ++ if (intmask & SDHCI_INT_ERROR_MASK) { ++ /* collect any uncovered errors */ ++ sdhci_writel(host, intmask & SDHCI_INT_ERROR_MASK, ++ SDHCI_INT_STATUS); ++ } ++ ++ intmask &= ~SDHCI_INT_ERROR_MASK; + + if (intmask & SDHCI_INT_BUS_POWER) { + pr_err("%s: Card is consuming too much power!\n", +@@ -2363,7 +2467,8 @@ + return ret; + } + +- if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { ++ if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA | ++ SDHCI_USE_PLATDMA)) { + if (host->ops->enable_dma) + host->ops->enable_dma(host); + } +@@ -2570,14 +2675,16 @@ + host->flags &= ~SDHCI_USE_ADMA; + } + +- if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { ++ if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA | ++ SDHCI_USE_PLATDMA)) { + if (host->ops->enable_dma) { + if (host->ops->enable_dma(host)) { + pr_warning("%s: No suitable DMA " + "available. Falling back to PIO.\n", + mmc_hostname(mmc)); + host->flags &= +- ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA); ++ ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA | ++ SDHCI_USE_PLATDMA); + } + } + } +@@ -2688,7 +2795,7 @@ + /* Auto-CMD23 stuff only works in ADMA or PIO. */ + if ((host->version >= SDHCI_SPEC_300) && + ((host->flags & SDHCI_USE_ADMA) || +- !(host->flags & SDHCI_USE_SDMA))) { ++ !(host->flags & SDHCI_USE_SDMA) )) { + host->flags |= SDHCI_AUTO_CMD23; + DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc)); + } else { +@@ -2822,6 +2929,12 @@ + mmc->caps |= MMC_CAP_MAX_CURRENT_200; + } + ++ if(host->ops->voltage_broken) { ++ ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34; ++ // Cannot support UHS modes is we are stuck at 3.3V; ++ mmc->caps &= ~(MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 | MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_DDR50); ++ } ++ + mmc->ocr_avail = ocr_avail; + mmc->ocr_avail_sdio = ocr_avail; + if (host->ocr_avail_sdio) +@@ -2954,6 +3067,7 @@ + + pr_info("%s: SDHCI controller on %s [%s] using %s\n", + mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)), ++ (host->flags & SDHCI_USE_PLATDMA) ? "platform's DMA" : + (host->flags & SDHCI_USE_ADMA) ? "ADMA" : + (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO"); + +Index: linux-3.2.46/drivers/mmc/host/sdhci.h +=================================================================== +--- linux-3.2.46.orig/drivers/mmc/host/sdhci.h 2013-05-30 13:35:16.000000000 +0000 ++++ linux-3.2.46/drivers/mmc/host/sdhci.h 2013-07-26 19:31:52.000000000 +0000 +@@ -273,6 +273,25 @@ + void (*platform_reset_enter)(struct sdhci_host *host, u8 mask); + void (*platform_reset_exit)(struct sdhci_host *host, u8 mask); + int (*set_uhs_signaling)(struct sdhci_host *host, unsigned int uhs); ++ ++ int (*enable)(struct sdhci_host *mmc); ++ int (*disable)(struct sdhci_host *mmc, int lazy); ++ int (*set_plat_power)(struct sdhci_host *mmc, ++ int power_mode); ++ ++ int (*pdma_able)(struct sdhci_host *host, ++ struct mmc_data *data); ++ void (*pdma_avail)(struct sdhci_host *host, ++ unsigned int *ref_intmask, ++ void(*complete)(struct sdhci_host *)); ++ void (*pdma_reset)(struct sdhci_host *host, ++ struct mmc_data *data); ++ unsigned int (*extra_ints)(struct sdhci_host *host); ++ unsigned int (*spurious_crc_acmd51)(struct sdhci_host *host); ++ unsigned int (*voltage_broken)(struct sdhci_host *host); ++ unsigned int (*uhs_broken)(struct sdhci_host *host); ++ unsigned int (*missing_status)(struct sdhci_host *host); ++ + void (*hw_reset)(struct sdhci_host *host); + }; + +@@ -379,6 +398,29 @@ + extern void sdhci_enable_irq_wakeups(struct sdhci_host *host); + #endif + ++static inline int /*bool*/ ++sdhci_platdma_dmaable(struct sdhci_host *host, struct mmc_data *data) ++{ ++ if (host->ops->pdma_able) ++ return host->ops->pdma_able(host, data); ++ else ++ return 1; ++} ++static inline void ++sdhci_platdma_avail(struct sdhci_host *host, unsigned int *ref_intmask, ++ void(*completion_callback)(struct sdhci_host *)) ++{ ++ if (host->ops->pdma_avail) ++ host->ops->pdma_avail(host, ref_intmask, completion_callback); ++} ++ ++static inline void ++sdhci_platdma_reset(struct sdhci_host *host, struct mmc_data *data) ++{ ++ if (host->ops->pdma_reset) ++ host->ops->pdma_reset(host, data); ++} ++ + #ifdef CONFIG_PM_RUNTIME + extern int sdhci_runtime_suspend_host(struct sdhci_host *host); + extern int sdhci_runtime_resume_host(struct sdhci_host *host); +Index: linux-3.2.46/include/linux/mmc/sdhci.h +=================================================================== +--- linux-3.2.46.orig/include/linux/mmc/sdhci.h 2013-05-30 13:35:16.000000000 +0000 ++++ linux-3.2.46/include/linux/mmc/sdhci.h 2013-07-26 19:31:52.000000000 +0000 +@@ -121,6 +121,7 @@ + #define SDHCI_AUTO_CMD23 (1<<7) /* Auto CMD23 support */ + #define SDHCI_PV_ENABLED (1<<8) /* Preset value enabled */ + #define SDHCI_SDIO_IRQ_ENABLED (1<<9) /* SDIO irq enabled */ ++#define SDHCI_USE_PLATDMA (1<<10) /* Host uses 3rd party DMA */ + + unsigned int version; /* SDHCI spec. version */ + +@@ -135,6 +136,7 @@ + + struct mmc_request *mrq; /* Current request */ + struct mmc_command *cmd; /* Current command */ ++ int last_cmdop; /* Opcode of last cmd sent */ + struct mmc_data *data; /* Current data request */ + unsigned int data_early:1; /* Data finished before cmd */ + diff -Nru linux-3.2.46/debian/patches/rpi/rpi_102_7ff2699415531e8cc583921d5ee9b48f8df25b82.patch linux-3.2.46/debian/patches/rpi/rpi_102_7ff2699415531e8cc583921d5ee9b48f8df25b82.patch --- linux-3.2.46/debian/patches/rpi/rpi_102_7ff2699415531e8cc583921d5ee9b48f8df25b82.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_102_7ff2699415531e8cc583921d5ee9b48f8df25b82.patch 2013-07-26 19:31:58.000000000 +0000 @@ -0,0 +1,427 @@ +commit 7ff2699415531e8cc583921d5ee9b48f8df25b82 +Author: popcornmix +Date: Tue Jan 17 19:20:57 2012 +0000 + + bcm2708 watchdog driver + + Signed-off-by: popcornmix + +Index: linux-3.2.46/drivers/watchdog/Kconfig +=================================================================== +--- linux-3.2.46.orig/drivers/watchdog/Kconfig 2013-05-30 13:35:16.000000000 +0000 ++++ linux-3.2.46/drivers/watchdog/Kconfig 2013-07-26 19:31:57.000000000 +0000 +@@ -343,6 +343,12 @@ + To compile this driver as a module, choose M here: the + module will be called imx2_wdt. + ++config BCM2708_WDT ++ tristate "BCM2708 Watchdog" ++ depends on ARCH_BCM2708 ++ help ++ Enables BCM2708 watchdog support. ++ + # AVR32 Architecture + + config AT32AP700X_WDT +Index: linux-3.2.46/drivers/watchdog/Makefile +=================================================================== +--- linux-3.2.46.orig/drivers/watchdog/Makefile 2013-05-30 13:35:16.000000000 +0000 ++++ linux-3.2.46/drivers/watchdog/Makefile 2013-07-26 19:31:57.000000000 +0000 +@@ -53,6 +53,7 @@ + obj-$(CONFIG_NUC900_WATCHDOG) += nuc900_wdt.o + obj-$(CONFIG_TS72XX_WATCHDOG) += ts72xx_wdt.o + obj-$(CONFIG_IMX2_WDT) += imx2_wdt.o ++obj-$(CONFIG_BCM2708_WDT) += bcm2708_wdog.o + + # AVR32 Architecture + obj-$(CONFIG_AT32AP700X_WDT) += at32ap700x_wdt.o +Index: linux-3.2.46/drivers/watchdog/bcm2708_wdog.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/watchdog/bcm2708_wdog.c 2013-07-26 19:31:57.000000000 +0000 +@@ -0,0 +1,385 @@ ++/* ++ * Broadcom BCM2708 watchdog driver. ++ * ++ * (c) Copyright 2010 Broadcom Europe Ltd ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * as published by the Free Software Foundation; either version ++ * 2 of the License, or (at your option) any later version. ++ * ++ * BCM2708 watchdog driver. Loosely based on wdt driver. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#define SECS_TO_WDOG_TICKS(x) ((x) << 16) ++#define WDOG_TICKS_TO_SECS(x) ((x) >> 16) ++ ++static unsigned long wdog_is_open; ++static uint32_t wdog_ticks; /* Ticks to load into wdog timer */ ++static char expect_close; ++ ++/* ++ * Module parameters ++ */ ++ ++#define WD_TIMO 10 /* Default heartbeat = 60 seconds */ ++static int heartbeat = WD_TIMO; /* Heartbeat in seconds */ ++ ++module_param(heartbeat, int, 0); ++MODULE_PARM_DESC(heartbeat, ++ "Watchdog heartbeat in seconds. (0 < heartbeat < 65536, default=" ++ __MODULE_STRING(WD_TIMO) ")"); ++ ++static int nowayout = WATCHDOG_NOWAYOUT; ++module_param(nowayout, int, 0); ++MODULE_PARM_DESC(nowayout, ++ "Watchdog cannot be stopped once started (default=" ++ __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); ++ ++static DEFINE_SPINLOCK(wdog_lock); ++ ++/** ++ * Start the watchdog driver. ++ */ ++ ++static int wdog_start(unsigned long timeout) ++{ ++ uint32_t cur; ++ unsigned long flags; ++ spin_lock_irqsave(&wdog_lock, flags); ++ ++ /* enable the watchdog */ ++ iowrite32(PM_PASSWORD | (timeout & PM_WDOG_TIME_SET), ++ __io_address(PM_WDOG)); ++ cur = ioread32(__io_address(PM_RSTC)); ++ iowrite32(PM_PASSWORD | (cur & PM_RSTC_WRCFG_CLR) | ++ PM_RSTC_WRCFG_FULL_RESET, __io_address(PM_RSTC)); ++ ++ spin_unlock_irqrestore(&wdog_lock, flags); ++ return 0; ++} ++ ++/** ++ * Stop the watchdog driver. ++ */ ++ ++static int wdog_stop(void) ++{ ++ iowrite32(PM_PASSWORD | PM_RSTC_RESET, __io_address(PM_RSTC)); ++ printk(KERN_INFO "watchdog stopped\n"); ++ return 0; ++} ++ ++/** ++ * Reload counter one with the watchdog heartbeat. We don't bother ++ * reloading the cascade counter. ++ */ ++ ++static void wdog_ping(void) ++{ ++ wdog_start(wdog_ticks); ++} ++ ++/** ++ * @t: the new heartbeat value that needs to be set. ++ * ++ * Set a new heartbeat value for the watchdog device. If the heartbeat ++ * value is incorrect we keep the old value and return -EINVAL. If ++ * successful we return 0. ++ */ ++ ++static int wdog_set_heartbeat(int t) ++{ ++ if (t < 1 || t > WDOG_TICKS_TO_SECS(PM_WDOG_TIME_SET)) ++ return -EINVAL; ++ ++ heartbeat = t; ++ wdog_ticks = SECS_TO_WDOG_TICKS(t); ++ return 0; ++} ++ ++/** ++ * @file: file handle to the watchdog ++ * @buf: buffer to write (unused as data does not matter here ++ * @count: count of bytes ++ * @ppos: pointer to the position to write. No seeks allowed ++ * ++ * A write to a watchdog device is defined as a keepalive signal. ++ * ++ * if 'nowayout' is set then normally a close() is ignored. But ++ * if you write 'V' first then the close() will stop the timer. ++ */ ++ ++static ssize_t wdog_write(struct file *file, const char __user *buf, ++ size_t count, loff_t *ppos) ++{ ++ if (count) { ++ if (!nowayout) { ++ size_t i; ++ ++ /* In case it was set long ago */ ++ expect_close = 0; ++ ++ for (i = 0; i != count; i++) { ++ char c; ++ if (get_user(c, buf + i)) ++ return -EFAULT; ++ if (c == 'V') ++ expect_close = 42; ++ } ++ } ++ wdog_ping(); ++ } ++ return count; ++} ++ ++static int wdog_get_status(void) ++{ ++ unsigned long flags; ++ int status = 0; ++ spin_lock_irqsave(&wdog_lock, flags); ++ /* FIXME: readback reset reason */ ++ spin_unlock_irqrestore(&wdog_lock, flags); ++ return status; ++} ++ ++static uint32_t wdog_get_remaining(void) ++{ ++ uint32_t ret = ioread32(__io_address(PM_WDOG)); ++ return ret & PM_WDOG_TIME_SET; ++} ++ ++/** ++ * @file: file handle to the device ++ * @cmd: watchdog command ++ * @arg: argument pointer ++ * ++ * The watchdog API defines a common set of functions for all watchdogs ++ * according to their available features. We only actually usefully support ++ * querying capabilities and current status. ++ */ ++ ++static long wdog_ioctl(struct file *file, unsigned int cmd, unsigned long arg) ++{ ++ void __user *argp = (void __user *)arg; ++ int __user *p = argp; ++ int new_heartbeat; ++ int status; ++ int options; ++ uint32_t remaining; ++ ++ struct watchdog_info ident = { ++ .options = WDIOF_SETTIMEOUT| ++ WDIOF_MAGICCLOSE| ++ WDIOF_KEEPALIVEPING, ++ .firmware_version = 1, ++ .identity = "BCM2708", ++ }; ++ ++ switch (cmd) { ++ case WDIOC_GETSUPPORT: ++ return copy_to_user(argp, &ident, sizeof(ident)) ? -EFAULT : 0; ++ case WDIOC_GETSTATUS: ++ status = wdog_get_status(); ++ return put_user(status, p); ++ case WDIOC_GETBOOTSTATUS: ++ return put_user(0, p); ++ case WDIOC_KEEPALIVE: ++ wdog_ping(); ++ return 0; ++ case WDIOC_SETTIMEOUT: ++ if (get_user(new_heartbeat, p)) ++ return -EFAULT; ++ if (wdog_set_heartbeat(new_heartbeat)) ++ return -EINVAL; ++ wdog_ping(); ++ /* Fall */ ++ case WDIOC_GETTIMEOUT: ++ return put_user(heartbeat, p); ++ case WDIOC_GETTIMELEFT: ++ remaining = WDOG_TICKS_TO_SECS(wdog_get_remaining()); ++ return put_user(remaining, p); ++ case WDIOC_SETOPTIONS: ++ if (get_user(options, p)) ++ return -EFAULT; ++ if (options & WDIOS_DISABLECARD) ++ wdog_stop(); ++ if (options & WDIOS_ENABLECARD) ++ wdog_start(wdog_ticks); ++ return 0; ++ default: ++ return -ENOTTY; ++ } ++} ++ ++/** ++ * @inode: inode of device ++ * @file: file handle to device ++ * ++ * The watchdog device has been opened. The watchdog device is single ++ * open and on opening we load the counters. ++ */ ++ ++static int wdog_open(struct inode *inode, struct file *file) ++{ ++ if (test_and_set_bit(0, &wdog_is_open)) ++ return -EBUSY; ++ /* ++ * Activate ++ */ ++ wdog_start(wdog_ticks); ++ return nonseekable_open(inode, file); ++} ++ ++/** ++ * @inode: inode to board ++ * @file: file handle to board ++ * ++ * The watchdog has a configurable API. There is a religious dispute ++ * between people who want their watchdog to be able to shut down and ++ * those who want to be sure if the watchdog manager dies the machine ++ * reboots. In the former case we disable the counters, in the latter ++ * case you have to open it again very soon. ++ */ ++ ++static int wdog_release(struct inode *inode, struct file *file) ++{ ++ if (expect_close == 42) { ++ wdog_stop(); ++ } else { ++ printk(KERN_CRIT ++ "wdt: WDT device closed unexpectedly. WDT will not stop!\n"); ++ wdog_ping(); ++ } ++ clear_bit(0, &wdog_is_open); ++ expect_close = 0; ++ return 0; ++} ++ ++/** ++ * @this: our notifier block ++ * @code: the event being reported ++ * @unused: unused ++ * ++ * Our notifier is called on system shutdowns. Turn the watchdog ++ * off so that it does not fire during the next reboot. ++ */ ++ ++static int wdog_notify_sys(struct notifier_block *this, unsigned long code, ++ void *unused) ++{ ++ if (code == SYS_DOWN || code == SYS_HALT) ++ wdog_stop(); ++ return NOTIFY_DONE; ++} ++ ++/* ++ * Kernel Interfaces ++ */ ++ ++ ++static const struct file_operations wdog_fops = { ++ .owner = THIS_MODULE, ++ .llseek = no_llseek, ++ .write = wdog_write, ++ .unlocked_ioctl = wdog_ioctl, ++ .open = wdog_open, ++ .release = wdog_release, ++}; ++ ++static struct miscdevice wdog_miscdev = { ++ .minor = WATCHDOG_MINOR, ++ .name = "watchdog", ++ .fops = &wdog_fops, ++}; ++ ++/* ++ * The WDT card needs to learn about soft shutdowns in order to ++ * turn the timebomb registers off. ++ */ ++ ++static struct notifier_block wdog_notifier = { ++ .notifier_call = wdog_notify_sys, ++}; ++ ++/** ++ * cleanup_module: ++ * ++ * Unload the watchdog. You cannot do this with any file handles open. ++ * If your watchdog is set to continue ticking on close and you unload ++ * it, well it keeps ticking. We won't get the interrupt but the board ++ * will not touch PC memory so all is fine. You just have to load a new ++ * module in 60 seconds or reboot. ++ */ ++ ++static void __exit wdog_exit(void) ++{ ++ misc_deregister(&wdog_miscdev); ++ unregister_reboot_notifier(&wdog_notifier); ++} ++ ++static int __init wdog_init(void) ++{ ++ int ret; ++ ++ /* Check that the heartbeat value is within it's range; ++ if not reset to the default */ ++ if (wdog_set_heartbeat(heartbeat)) { ++ wdog_set_heartbeat(WD_TIMO); ++ printk(KERN_INFO "bcm2708_wdog: heartbeat value must be " ++ "0 < heartbeat < %d, using %d\n", ++ WDOG_TICKS_TO_SECS(PM_WDOG_TIME_SET), ++ WD_TIMO); ++ } ++ ++ ret = register_reboot_notifier(&wdog_notifier); ++ if (ret) { ++ printk(KERN_ERR ++ "wdt: cannot register reboot notifier (err=%d)\n", ret); ++ goto out_reboot; ++ } ++ ++ ret = misc_register(&wdog_miscdev); ++ if (ret) { ++ printk(KERN_ERR ++ "wdt: cannot register miscdev on minor=%d (err=%d)\n", ++ WATCHDOG_MINOR, ret); ++ goto out_misc; ++ } ++ ++ printk(KERN_INFO "bcm2708 watchdog, heartbeat=%d sec (nowayout=%d)\n", ++ heartbeat, nowayout); ++ return 0; ++ ++out_misc: ++ unregister_reboot_notifier(&wdog_notifier); ++out_reboot: ++ return ret; ++} ++ ++module_init(wdog_init); ++module_exit(wdog_exit); ++ ++MODULE_AUTHOR("Luke Diamand"); ++MODULE_DESCRIPTION("Driver for BCM2708 watchdog"); ++MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR); ++MODULE_ALIAS_MISCDEV(TEMP_MINOR); ++MODULE_LICENSE("GPL"); ++ diff -Nru linux-3.2.46/debian/patches/rpi/rpi_103_c6f535332605987ba9391c92e22647351bc1f592.patch linux-3.2.46/debian/patches/rpi/rpi_103_c6f535332605987ba9391c92e22647351bc1f592.patch --- linux-3.2.46/debian/patches/rpi/rpi_103_c6f535332605987ba9391c92e22647351bc1f592.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_103_c6f535332605987ba9391c92e22647351bc1f592.patch 2013-07-26 19:31:59.000000000 +0000 @@ -0,0 +1,2980 @@ +commit c6f535332605987ba9391c92e22647351bc1f592 +Author: popcornmix +Date: Tue Jan 17 19:21:26 2012 +0000 + + bcm2708 framebuffer driver + + Signed-off-by: popcornmix + +Index: linux-3.2.46/drivers/video/Kconfig +=================================================================== +--- linux-3.2.46.orig/drivers/video/Kconfig 2013-06-05 03:22:56.000000000 +0000 ++++ linux-3.2.46/drivers/video/Kconfig 2013-07-26 19:31:58.000000000 +0000 +@@ -312,6 +312,20 @@ + help + Support the Permedia2 FIFO disconnect feature. + ++config FB_BCM2708 ++ tristate "BCM2708 framebuffer support" ++ depends on FB && ARM ++ select FB_CFB_FILLRECT ++ select FB_CFB_COPYAREA ++ select FB_CFB_IMAGEBLIT ++ help ++ This framebuffer device driver is for the BCM2708 framebuffer. ++ ++ If you want to compile this as a module (=code which can be ++ inserted into and removed from the running kernel), say M ++ here and read . The module ++ will be called bcm2708_fb. ++ + config FB_ARMCLCD + tristate "ARM PrimeCell PL110 support" + depends on FB && ARM && ARM_AMBA +Index: linux-3.2.46/drivers/video/Makefile +=================================================================== +--- linux-3.2.46.orig/drivers/video/Makefile 2013-06-05 03:22:56.000000000 +0000 ++++ linux-3.2.46/drivers/video/Makefile 2013-07-26 19:31:58.000000000 +0000 +@@ -94,6 +94,7 @@ + obj-$(CONFIG_FB_PVR2) += pvr2fb.o + obj-$(CONFIG_FB_VOODOO1) += sstfb.o + obj-$(CONFIG_FB_ARMCLCD) += amba-clcd.o ++obj-$(CONFIG_FB_BCM2708) += bcm2708_fb.o + obj-$(CONFIG_FB_68328) += 68328fb.o + obj-$(CONFIG_FB_GBE) += gbefb.o + obj-$(CONFIG_FB_CIRRUS) += cirrusfb.o +Index: linux-3.2.46/drivers/video/bcm2708_fb.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/video/bcm2708_fb.c 2013-07-26 19:31:58.000000000 +0000 +@@ -0,0 +1,440 @@ ++/* ++ * linux/drivers/video/bcm2708_fb.c ++ * ++ * Copyright (C) 2010 Broadcom ++ * ++ * This file is subject to the terms and conditions of the GNU General Public ++ * License. See the file COPYING in the main directory of this archive ++ * for more details. ++ * ++ * Broadcom simple framebuffer driver ++ */ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++#include ++#include ++#include ++ ++/* This is limited to 16 characters when displayed by X startup */ ++static const char *bcm2708_name = "BCM2708 FB"; ++ ++#define DRIVER_NAME "bcm2708_fb" ++ ++/* this data structure describes each frame buffer device we find */ ++ ++struct fbinfo_s { ++ int xres, yres, xres_virtual, yres_virtual; ++ int pitch, bpp; ++ int xoffset, yoffset; ++ int base; ++ int screen_size; ++}; ++ ++struct bcm2708_fb { ++ struct fb_info fb; ++ struct platform_device *dev; ++ void __iomem *regs; ++ volatile struct fbinfo_s *info; ++ dma_addr_t dma; ++ u32 cmap[16]; ++}; ++ ++#define to_bcm2708(info) container_of(info, struct bcm2708_fb, fb) ++ ++static int ++bcm2708_fb_set_bitfields(struct fb_var_screeninfo *var) ++{ ++ int ret = 0; ++ ++ memset(&var->transp, 0, sizeof(var->transp)); ++ ++ var->red.msb_right = 0; ++ var->green.msb_right = 0; ++ var->blue.msb_right = 0; ++ ++ switch (var->bits_per_pixel) { ++ case 1: ++ case 2: ++ case 4: ++ case 8: ++ var->red.length = var->bits_per_pixel; ++ var->red.offset = 0; ++ var->green.length = var->bits_per_pixel; ++ var->green.offset = 0; ++ var->blue.length = var->bits_per_pixel; ++ var->blue.offset = 0; ++ break; ++ case 16: ++ var->red.length = 5; ++ var->blue.length = 5; ++ /* ++ * Green length can be 5 or 6 depending whether ++ * we're operating in RGB555 or RGB565 mode. ++ */ ++ if (var->green.length != 5 && var->green.length != 6) ++ var->green.length = 6; ++ break; ++ case 32: ++ var->red.length = 8; ++ var->green.length = 8; ++ var->blue.length = 8; ++ break; ++ default: ++ ret = -EINVAL; ++ break; ++ } ++ ++ /* ++ * >= 16bpp displays have separate colour component bitfields ++ * encoded in the pixel data. Calculate their position from ++ * the bitfield length defined above. ++ */ ++ if (ret == 0 && var->bits_per_pixel >= 16) { ++ var->blue.offset = 0; ++ var->green.offset = var->blue.offset + var->blue.length; ++ var->red.offset = var->green.offset + var->green.length; ++ } ++ ++ return ret; ++} ++ ++static int bcm2708_fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info) ++{ ++ ++ // info input, var output ++ int yres; ++ /* memory size in pixels */ ++ unsigned pixels = info->screen_size * 8 / var->bits_per_pixel; ++ ++ // info input, var output ++ printk(KERN_ERR "bcm2708_fb_check_var info(%p) %dx%d (%dx%d), %d, %d\n", info, info->var.xres, info->var.yres, info->var.xres_virtual, info->var.yres_virtual, (int)info->screen_size, info->var.bits_per_pixel ); ++ printk(KERN_ERR "bcm2708_fb_check_var var(%p) %dx%d (%dx%d), %d, %d\n", var, var->xres, var->yres, var->xres_virtual, var->yres_virtual, var->bits_per_pixel, pixels); ++ ++ if (!var->bits_per_pixel) var->bits_per_pixel = 16; ++ ++ if (0 && var->bits_per_pixel != 16 && var->bits_per_pixel != 32) { ++ printk(KERN_ERR "bcm2708_fb_check_var: ERROR: bits_per_pixel=%d\n", var->bits_per_pixel); ++ return -EINVAL; ++ } ++ ++ bcm2708_fb_set_bitfields(var); ++ ++ if (var->xres_virtual < var->xres) ++ var->xres_virtual = var->xres; ++ /* use highest possible virtual resolution */ ++ if (var->yres_virtual == -1) { ++ var->yres_virtual = 480; //pixels / var->xres_virtual; ++ ++ printk(KERN_ERR ++ "bcm2708_fb_check_var: virtual resolution set to maximum of %dx%d\n", ++ var->xres_virtual, var->yres_virtual); ++ } ++ if (var->yres_virtual < var->yres) ++ var->yres_virtual = var->yres; ++ ++ #if 0 ++ if (var->xres_virtual * var->yres_virtual > pixels) { ++ printk(KERN_ERR "bcm2708_fb_check_var: mode %dx%dx%d rejected... " ++ "virtual resolution too high to fit into video memory!\n", ++ var->xres_virtual, var->yres_virtual, ++ var->bits_per_pixel); ++ return -EINVAL; ++ } ++ #endif ++ if (var->xoffset < 0) ++ var->xoffset = 0; ++ if (var->yoffset < 0) ++ var->yoffset = 0; ++ ++ /* truncate xoffset and yoffset to maximum if too high */ ++ if (var->xoffset > var->xres_virtual - var->xres) ++ var->xoffset = var->xres_virtual - var->xres - 1; ++ if (var->yoffset > var->yres_virtual - var->yres) ++ var->yoffset = var->yres_virtual - var->yres - 1; ++ ++ var->red.msb_right = ++ var->green.msb_right = ++ var->blue.msb_right = ++ var->transp.offset = ++ var->transp.length = ++ var->transp.msb_right = 0; ++ ++ yres = var->yres; ++ if (var->vmode & FB_VMODE_DOUBLE) ++ yres *= 2; ++ else if (var->vmode & FB_VMODE_INTERLACED) ++ yres = (yres + 1) / 2; ++ ++ if (yres > 1200) { ++ printk(KERN_ERR "bcm2708_fb_check_var: ERROR: VerticalTotal >= 1200; " ++ "special treatment required! (TODO)\n"); ++ return -EINVAL; ++ } ++ ++ //if (cirrusfb_check_pixclock(var, info)) ++ // return -EINVAL; ++ ++ //if (!is_laguna(cinfo)) ++ // var->accel_flags = FB_ACCELF_TEXT; ++ ++ return 0; ++} ++ ++static int bcm2708_fb_set_par(struct fb_info *info) ++{ ++ unsigned val = 0; ++ struct bcm2708_fb *fb = to_bcm2708(info); ++ volatile struct fbinfo_s *fbinfo = fb->info; ++ fbinfo->xres = info->var.xres; ++ fbinfo->yres = info->var.yres; ++ fbinfo->xres_virtual = info->var.xres_virtual; ++ fbinfo->yres_virtual = info->var.yres_virtual; ++ fbinfo->bpp = info->var.bits_per_pixel; ++ fbinfo->xoffset = info->var.xoffset; ++ fbinfo->yoffset = info->var.yoffset; ++ fbinfo->base = 0; // filled in by VC ++ fbinfo->pitch = 0; // filled in by VC ++ ++ printk(KERN_ERR "bcm2708_fb_set_par info(%p) %dx%d (%dx%d), %d, %d\n", info, info->var.xres, info->var.yres, info->var.xres_virtual, info->var.yres_virtual, (int)info->screen_size, info->var.bits_per_pixel ); ++ ++ // inform vc about new framebuffer ++ bcm_mailbox_write(MBOX_CHAN_FB, fb->dma); ++ ++ // wait for response ++ bcm_mailbox_read(MBOX_CHAN_FB, &val); ++ ++ fb->fb.fix.line_length = fbinfo->pitch; ++ ++ if (info->var.bits_per_pixel <= 8) ++ fb->fb.fix.visual = FB_VISUAL_PSEUDOCOLOR; ++ else ++ fb->fb.fix.visual = FB_VISUAL_TRUECOLOR; ++ ++ fb->fb.fix.smem_start = fbinfo->base; ++ fb->fb.fix.smem_len = fbinfo->pitch * fbinfo->yres_virtual; ++ fb->fb.screen_size = fbinfo->screen_size; ++ fb->fb.screen_base = (void *)ioremap_nocache(fb->fb.fix.smem_start, fb->fb.screen_size); ++ ++ printk(KERN_ERR "BCM2708FB: start = %p,%p,%p width=%d, height=%d, bpp=%d, pitch=%d\n", ++ (void *)fb->fb.screen_base, (void *)fb->fb.fix.smem_start, (void *)val, fbinfo->xres, fbinfo->yres, fbinfo->bpp, fbinfo->pitch); ++ ++ return val; ++} ++ ++static inline u32 convert_bitfield(int val, struct fb_bitfield *bf) ++{ ++ unsigned int mask = (1 << bf->length) - 1; ++ ++ return (val >> (16 - bf->length) & mask) << bf->offset; ++} ++ ++static int bcm2708_fb_setcolreg(unsigned int regno, unsigned int red, unsigned int green, ++ unsigned int blue, unsigned int transp, struct fb_info *info) ++{ ++ struct bcm2708_fb *fb = to_bcm2708(info); ++ ++ if (regno < 16) ++ fb->cmap[regno] = convert_bitfield(transp, &fb->fb.var.transp) | ++ convert_bitfield(blue, &fb->fb.var.blue) | ++ convert_bitfield(green, &fb->fb.var.green) | ++ convert_bitfield(red, &fb->fb.var.red); ++ ++ return regno > 255; ++} ++ ++static int bcm2708_fb_blank(int blank_mode, struct fb_info *info) ++{ ++//printk(KERN_ERR "bcm2708_fb_blank\n"); ++ return -1; ++} ++ ++static void bcm2708_fb_fillrect(struct fb_info *info, const struct fb_fillrect *rect) ++{ ++// (is called) printk(KERN_ERR "bcm2708_fb_fillrect\n"); ++ cfb_fillrect(info, rect); ++} ++ ++static void bcm2708_fb_copyarea(struct fb_info *info, const struct fb_copyarea *region) ++{ ++//printk(KERN_ERR "bcm2708_fb_copyarea\n"); ++ cfb_copyarea(info, region); ++} ++ ++static void bcm2708_fb_imageblit(struct fb_info *info, const struct fb_image *image) ++{ ++// (is called) printk(KERN_ERR "bcm2708_fb_imageblit\n"); ++ cfb_imageblit(info, image); ++} ++ ++static struct fb_ops bcm2708_fb_ops = { ++ .owner = THIS_MODULE, ++ .fb_check_var = bcm2708_fb_check_var, ++ .fb_set_par = bcm2708_fb_set_par, ++ .fb_setcolreg = bcm2708_fb_setcolreg, ++ .fb_blank = bcm2708_fb_blank, ++ .fb_fillrect = bcm2708_fb_fillrect, ++ .fb_copyarea = bcm2708_fb_copyarea, ++ .fb_imageblit = bcm2708_fb_imageblit, ++}; ++ ++static int FBWIDTH =800; /* module parameter */ ++static int FBHEIGHT =480; /* module parameter */ ++ ++ ++static int bcm2708_fb_register(struct bcm2708_fb *fb) ++{ ++ int ret; ++ dma_addr_t dma; ++ void *mem; ++ ++ mem = dma_alloc_coherent(NULL, PAGE_ALIGN(sizeof(*fb->info)), &dma, GFP_KERNEL); ++ ++ if (NULL == mem) { ++ printk(KERN_ERR ": unable to allocate fbinfo buffer\n"); ++ ret = -ENOMEM; ++ } else { ++ fb->info = (struct fbinfo_s *)mem; ++ fb->dma = dma; ++ } ++ fb->fb.fbops = &bcm2708_fb_ops; ++ fb->fb.flags = FBINFO_FLAG_DEFAULT | FBINFO_HWACCEL_COPYAREA | FBINFO_HWACCEL_FILLRECT | FBINFO_HWACCEL_IMAGEBLIT; ++ fb->fb.pseudo_palette = fb->cmap; ++ ++ strncpy(fb->fb.fix.id, bcm2708_name, sizeof(fb->fb.fix.id)); ++ fb->fb.fix.type = FB_TYPE_PACKED_PIXELS; ++ fb->fb.fix.type_aux = 0; ++ fb->fb.fix.xpanstep = 0; ++ fb->fb.fix.ypanstep = 0; ++ fb->fb.fix.ywrapstep = 0; ++ fb->fb.fix.accel = FB_ACCEL_NONE; ++ ++ fb->fb.var.xres = FBWIDTH; ++ fb->fb.var.yres = FBHEIGHT; ++ fb->fb.var.xres_virtual = FBWIDTH; ++ fb->fb.var.yres_virtual = FBHEIGHT; ++ fb->fb.var.bits_per_pixel = 16; ++ fb->fb.var.vmode = FB_VMODE_NONINTERLACED; ++ fb->fb.var.activate = FB_ACTIVATE_NOW; ++ fb->fb.var.nonstd = 0; ++ fb->fb.var.height = FBWIDTH; ++ fb->fb.var.width = FBHEIGHT; ++ fb->fb.var.accel_flags = 0; ++ ++ fb->fb.monspecs.hfmin = 0; ++ fb->fb.monspecs.hfmax = 100000; ++ fb->fb.monspecs.vfmin = 0; ++ fb->fb.monspecs.vfmax = 400; ++ fb->fb.monspecs.dclkmin = 1000000; ++ fb->fb.monspecs.dclkmax = 100000000; ++ ++ bcm2708_fb_set_bitfields(&fb->fb.var); ++ ++ /* ++ * Allocate colourmap. ++ */ ++ ++ fb_set_var(&fb->fb, &fb->fb.var); ++ ++ printk(KERN_INFO "BCM2708FB: registering framebuffer (%d, %d)\n", FBWIDTH, FBHEIGHT); ++ ++ ret = register_framebuffer(&fb->fb); ++ printk(KERN_ERR "BCM2708FB: register framebuffer (%d)\n", ret); ++ if (ret == 0) ++ goto out; ++ ++ printk(KERN_ERR "BCM2708FB: cannot register framebuffer (%d)\n", ret); ++ ++ iounmap(fb->regs); ++ out: ++ return ret; ++} ++ ++static int bcm2708_fb_probe(struct platform_device *dev) ++{ ++ struct bcm2708_fb *fb; ++ int ret; ++ ++ fb = kmalloc(sizeof(struct bcm2708_fb), GFP_KERNEL); ++ if (!fb) { ++ dev_err(&dev->dev, "could not allocate new bcm2708_fb struct\n"); ++ ret = -ENOMEM; ++ goto free_region; ++ } ++ memset(fb, 0, sizeof(struct bcm2708_fb)); ++ ++ fb->dev = dev; ++ ++ ret = bcm2708_fb_register(fb); ++ if (ret == 0) { ++ platform_set_drvdata(dev, fb); ++ goto out; ++ } ++ ++ kfree(fb); ++ free_region: ++ dev_err(&dev->dev, "probe failed, err %d\n", ret); ++ out: ++ return ret; ++} ++ ++static int bcm2708_fb_remove(struct platform_device *dev) ++{ ++ struct bcm2708_fb *fb = platform_get_drvdata(dev); ++ ++ platform_set_drvdata(dev, NULL); ++ ++ unregister_framebuffer(&fb->fb); ++ iounmap(fb->regs); ++ ++ dma_free_coherent(NULL, PAGE_ALIGN(sizeof(*fb->info)), (void *)fb->info, fb->dma); ++ kfree(fb); ++ ++ return 0; ++} ++ ++static struct platform_driver bcm2708_fb_driver = { ++ .probe = bcm2708_fb_probe, ++ .remove = bcm2708_fb_remove, ++ .driver = { ++ .name = DRIVER_NAME, ++ .owner = THIS_MODULE, ++ }, ++}; ++ ++static int __init bcm2708_fb_init(void) ++{ ++ return platform_driver_register(&bcm2708_fb_driver); ++} ++ ++module_init(bcm2708_fb_init); ++ ++static void __exit bcm2708_fb_exit(void) ++{ ++ platform_driver_unregister(&bcm2708_fb_driver); ++} ++ ++module_exit(bcm2708_fb_exit); ++ ++module_param(FBWIDTH, int, 0644); ++module_param(FBHEIGHT, int, 0644); ++ ++MODULE_DESCRIPTION("BCM2708 framebuffer driver"); ++MODULE_LICENSE("GPL"); ++ ++MODULE_PARM_DESC(FBWIDTH, "Width of ARM Framebuffer"); ++MODULE_PARM_DESC(FBHEIGHT, "Height of ARM Framebuffer"); +Index: linux-3.2.46/drivers/video/logo/logo_linux_clut224.ppm +=================================================================== +--- linux-3.2.46.orig/drivers/video/logo/logo_linux_clut224.ppm 2013-05-30 13:35:16.000000000 +0000 ++++ linux-3.2.46/drivers/video/logo/logo_linux_clut224.ppm 2013-07-26 19:31:58.000000000 +0000 +@@ -1,1604 +1,883 @@ + P3 +-# Standard 224-color Linux logo +-80 80 ++63 80 + 255 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 6 6 6 6 6 6 10 10 10 10 10 10 +- 10 10 10 6 6 6 6 6 6 6 6 6 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 6 6 6 10 10 10 14 14 14 +- 22 22 22 26 26 26 30 30 30 34 34 34 +- 30 30 30 30 30 30 26 26 26 18 18 18 +- 14 14 14 10 10 10 6 6 6 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 1 0 0 1 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 6 6 6 14 14 14 26 26 26 42 42 42 +- 54 54 54 66 66 66 78 78 78 78 78 78 +- 78 78 78 74 74 74 66 66 66 54 54 54 +- 42 42 42 26 26 26 18 18 18 10 10 10 +- 6 6 6 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 1 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 10 10 10 +- 22 22 22 42 42 42 66 66 66 86 86 86 +- 66 66 66 38 38 38 38 38 38 22 22 22 +- 26 26 26 34 34 34 54 54 54 66 66 66 +- 86 86 86 70 70 70 46 46 46 26 26 26 +- 14 14 14 6 6 6 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 1 0 0 1 0 0 1 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 10 10 10 26 26 26 +- 50 50 50 82 82 82 58 58 58 6 6 6 +- 2 2 6 2 2 6 2 2 6 2 2 6 +- 2 2 6 2 2 6 2 2 6 2 2 6 +- 6 6 6 54 54 54 86 86 86 66 66 66 +- 38 38 38 18 18 18 6 6 6 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 6 6 6 22 22 22 50 50 50 +- 78 78 78 34 34 34 2 2 6 2 2 6 +- 2 2 6 2 2 6 2 2 6 2 2 6 +- 2 2 6 2 2 6 2 2 6 2 2 6 +- 2 2 6 2 2 6 6 6 6 70 70 70 +- 78 78 78 46 46 46 22 22 22 6 6 6 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 1 0 0 1 0 0 1 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 6 6 6 18 18 18 42 42 42 82 82 82 +- 26 26 26 2 2 6 2 2 6 2 2 6 +- 2 2 6 2 2 6 2 2 6 2 2 6 +- 2 2 6 2 2 6 2 2 6 14 14 14 +- 46 46 46 34 34 34 6 6 6 2 2 6 +- 42 42 42 78 78 78 42 42 42 18 18 18 +- 6 6 6 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 1 0 0 0 0 0 1 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 10 10 10 30 30 30 66 66 66 58 58 58 +- 2 2 6 2 2 6 2 2 6 2 2 6 +- 2 2 6 2 2 6 2 2 6 2 2 6 +- 2 2 6 2 2 6 2 2 6 26 26 26 +- 86 86 86 101 101 101 46 46 46 10 10 10 +- 2 2 6 58 58 58 70 70 70 34 34 34 +- 10 10 10 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 1 0 0 1 0 0 1 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 14 14 14 42 42 42 86 86 86 10 10 10 +- 2 2 6 2 2 6 2 2 6 2 2 6 +- 2 2 6 2 2 6 2 2 6 2 2 6 +- 2 2 6 2 2 6 2 2 6 30 30 30 +- 94 94 94 94 94 94 58 58 58 26 26 26 +- 2 2 6 6 6 6 78 78 78 54 54 54 +- 22 22 22 6 6 6 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 6 6 6 +- 22 22 22 62 62 62 62 62 62 2 2 6 +- 2 2 6 2 2 6 2 2 6 2 2 6 +- 2 2 6 2 2 6 2 2 6 2 2 6 +- 2 2 6 2 2 6 2 2 6 26 26 26 +- 54 54 54 38 38 38 18 18 18 10 10 10 +- 2 2 6 2 2 6 34 34 34 82 82 82 +- 38 38 38 14 14 14 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 1 0 0 1 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 6 6 6 +- 30 30 30 78 78 78 30 30 30 2 2 6 +- 2 2 6 2 2 6 2 2 6 2 2 6 +- 2 2 6 2 2 6 2 2 6 2 2 6 +- 2 2 6 2 2 6 2 2 6 10 10 10 +- 10 10 10 2 2 6 2 2 6 2 2 6 +- 2 2 6 2 2 6 2 2 6 78 78 78 +- 50 50 50 18 18 18 6 6 6 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 1 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 10 10 10 +- 38 38 38 86 86 86 14 14 14 2 2 6 +- 2 2 6 2 2 6 2 2 6 2 2 6 +- 2 2 6 2 2 6 2 2 6 2 2 6 +- 2 2 6 2 2 6 2 2 6 2 2 6 +- 2 2 6 2 2 6 2 2 6 2 2 6 +- 2 2 6 2 2 6 2 2 6 54 54 54 +- 66 66 66 26 26 26 6 6 6 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 1 0 0 1 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 14 14 14 +- 42 42 42 82 82 82 2 2 6 2 2 6 +- 2 2 6 6 6 6 10 10 10 2 2 6 +- 2 2 6 2 2 6 2 2 6 2 2 6 +- 2 2 6 2 2 6 2 2 6 6 6 6 +- 14 14 14 10 10 10 2 2 6 2 2 6 +- 2 2 6 2 2 6 2 2 6 18 18 18 +- 82 82 82 34 34 34 10 10 10 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 1 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 14 14 14 +- 46 46 46 86 86 86 2 2 6 2 2 6 +- 6 6 6 6 6 6 22 22 22 34 34 34 +- 6 6 6 2 2 6 2 2 6 2 2 6 +- 2 2 6 2 2 6 18 18 18 34 34 34 +- 10 10 10 50 50 50 22 22 22 2 2 6 +- 2 2 6 2 2 6 2 2 6 10 10 10 +- 86 86 86 42 42 42 14 14 14 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 1 0 0 1 0 0 1 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 14 14 14 +- 46 46 46 86 86 86 2 2 6 2 2 6 +- 38 38 38 116 116 116 94 94 94 22 22 22 +- 22 22 22 2 2 6 2 2 6 2 2 6 +- 14 14 14 86 86 86 138 138 138 162 162 162 +-154 154 154 38 38 38 26 26 26 6 6 6 +- 2 2 6 2 2 6 2 2 6 2 2 6 +- 86 86 86 46 46 46 14 14 14 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 14 14 14 +- 46 46 46 86 86 86 2 2 6 14 14 14 +-134 134 134 198 198 198 195 195 195 116 116 116 +- 10 10 10 2 2 6 2 2 6 6 6 6 +-101 98 89 187 187 187 210 210 210 218 218 218 +-214 214 214 134 134 134 14 14 14 6 6 6 +- 2 2 6 2 2 6 2 2 6 2 2 6 +- 86 86 86 50 50 50 18 18 18 6 6 6 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 1 0 0 0 +- 0 0 1 0 0 1 0 0 1 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 14 14 14 +- 46 46 46 86 86 86 2 2 6 54 54 54 +-218 218 218 195 195 195 226 226 226 246 246 246 +- 58 58 58 2 2 6 2 2 6 30 30 30 +-210 210 210 253 253 253 174 174 174 123 123 123 +-221 221 221 234 234 234 74 74 74 2 2 6 +- 2 2 6 2 2 6 2 2 6 2 2 6 +- 70 70 70 58 58 58 22 22 22 6 6 6 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 14 14 14 +- 46 46 46 82 82 82 2 2 6 106 106 106 +-170 170 170 26 26 26 86 86 86 226 226 226 +-123 123 123 10 10 10 14 14 14 46 46 46 +-231 231 231 190 190 190 6 6 6 70 70 70 +- 90 90 90 238 238 238 158 158 158 2 2 6 +- 2 2 6 2 2 6 2 2 6 2 2 6 +- 70 70 70 58 58 58 22 22 22 6 6 6 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 1 0 0 0 +- 0 0 1 0 0 1 0 0 1 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 14 14 14 +- 42 42 42 86 86 86 6 6 6 116 116 116 +-106 106 106 6 6 6 70 70 70 149 149 149 +-128 128 128 18 18 18 38 38 38 54 54 54 +-221 221 221 106 106 106 2 2 6 14 14 14 +- 46 46 46 190 190 190 198 198 198 2 2 6 +- 2 2 6 2 2 6 2 2 6 2 2 6 +- 74 74 74 62 62 62 22 22 22 6 6 6 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 1 0 0 0 +- 0 0 1 0 0 0 0 0 1 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 14 14 14 +- 42 42 42 94 94 94 14 14 14 101 101 101 +-128 128 128 2 2 6 18 18 18 116 116 116 +-118 98 46 121 92 8 121 92 8 98 78 10 +-162 162 162 106 106 106 2 2 6 2 2 6 +- 2 2 6 195 195 195 195 195 195 6 6 6 +- 2 2 6 2 2 6 2 2 6 2 2 6 +- 74 74 74 62 62 62 22 22 22 6 6 6 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 1 0 0 1 +- 0 0 1 0 0 0 0 0 1 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 10 10 10 +- 38 38 38 90 90 90 14 14 14 58 58 58 +-210 210 210 26 26 26 54 38 6 154 114 10 +-226 170 11 236 186 11 225 175 15 184 144 12 +-215 174 15 175 146 61 37 26 9 2 2 6 +- 70 70 70 246 246 246 138 138 138 2 2 6 +- 2 2 6 2 2 6 2 2 6 2 2 6 +- 70 70 70 66 66 66 26 26 26 6 6 6 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 10 10 10 +- 38 38 38 86 86 86 14 14 14 10 10 10 +-195 195 195 188 164 115 192 133 9 225 175 15 +-239 182 13 234 190 10 232 195 16 232 200 30 +-245 207 45 241 208 19 232 195 16 184 144 12 +-218 194 134 211 206 186 42 42 42 2 2 6 +- 2 2 6 2 2 6 2 2 6 2 2 6 +- 50 50 50 74 74 74 30 30 30 6 6 6 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 10 10 10 +- 34 34 34 86 86 86 14 14 14 2 2 6 +-121 87 25 192 133 9 219 162 10 239 182 13 +-236 186 11 232 195 16 241 208 19 244 214 54 +-246 218 60 246 218 38 246 215 20 241 208 19 +-241 208 19 226 184 13 121 87 25 2 2 6 +- 2 2 6 2 2 6 2 2 6 2 2 6 +- 50 50 50 82 82 82 34 34 34 10 10 10 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 10 10 10 +- 34 34 34 82 82 82 30 30 30 61 42 6 +-180 123 7 206 145 10 230 174 11 239 182 13 +-234 190 10 238 202 15 241 208 19 246 218 74 +-246 218 38 246 215 20 246 215 20 246 215 20 +-226 184 13 215 174 15 184 144 12 6 6 6 +- 2 2 6 2 2 6 2 2 6 2 2 6 +- 26 26 26 94 94 94 42 42 42 14 14 14 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 10 10 10 +- 30 30 30 78 78 78 50 50 50 104 69 6 +-192 133 9 216 158 10 236 178 12 236 186 11 +-232 195 16 241 208 19 244 214 54 245 215 43 +-246 215 20 246 215 20 241 208 19 198 155 10 +-200 144 11 216 158 10 156 118 10 2 2 6 +- 2 2 6 2 2 6 2 2 6 2 2 6 +- 6 6 6 90 90 90 54 54 54 18 18 18 +- 6 6 6 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 10 10 10 +- 30 30 30 78 78 78 46 46 46 22 22 22 +-137 92 6 210 162 10 239 182 13 238 190 10 +-238 202 15 241 208 19 246 215 20 246 215 20 +-241 208 19 203 166 17 185 133 11 210 150 10 +-216 158 10 210 150 10 102 78 10 2 2 6 +- 6 6 6 54 54 54 14 14 14 2 2 6 +- 2 2 6 62 62 62 74 74 74 30 30 30 +- 10 10 10 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 10 10 10 +- 34 34 34 78 78 78 50 50 50 6 6 6 +- 94 70 30 139 102 15 190 146 13 226 184 13 +-232 200 30 232 195 16 215 174 15 190 146 13 +-168 122 10 192 133 9 210 150 10 213 154 11 +-202 150 34 182 157 106 101 98 89 2 2 6 +- 2 2 6 78 78 78 116 116 116 58 58 58 +- 2 2 6 22 22 22 90 90 90 46 46 46 +- 18 18 18 6 6 6 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 10 10 10 +- 38 38 38 86 86 86 50 50 50 6 6 6 +-128 128 128 174 154 114 156 107 11 168 122 10 +-198 155 10 184 144 12 197 138 11 200 144 11 +-206 145 10 206 145 10 197 138 11 188 164 115 +-195 195 195 198 198 198 174 174 174 14 14 14 +- 2 2 6 22 22 22 116 116 116 116 116 116 +- 22 22 22 2 2 6 74 74 74 70 70 70 +- 30 30 30 10 10 10 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 6 6 6 18 18 18 +- 50 50 50 101 101 101 26 26 26 10 10 10 +-138 138 138 190 190 190 174 154 114 156 107 11 +-197 138 11 200 144 11 197 138 11 192 133 9 +-180 123 7 190 142 34 190 178 144 187 187 187 +-202 202 202 221 221 221 214 214 214 66 66 66 +- 2 2 6 2 2 6 50 50 50 62 62 62 +- 6 6 6 2 2 6 10 10 10 90 90 90 +- 50 50 50 18 18 18 6 6 6 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 10 10 10 34 34 34 +- 74 74 74 74 74 74 2 2 6 6 6 6 +-144 144 144 198 198 198 190 190 190 178 166 146 +-154 121 60 156 107 11 156 107 11 168 124 44 +-174 154 114 187 187 187 190 190 190 210 210 210 +-246 246 246 253 253 253 253 253 253 182 182 182 +- 6 6 6 2 2 6 2 2 6 2 2 6 +- 2 2 6 2 2 6 2 2 6 62 62 62 +- 74 74 74 34 34 34 14 14 14 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 10 10 10 22 22 22 54 54 54 +- 94 94 94 18 18 18 2 2 6 46 46 46 +-234 234 234 221 221 221 190 190 190 190 190 190 +-190 190 190 187 187 187 187 187 187 190 190 190 +-190 190 190 195 195 195 214 214 214 242 242 242 +-253 253 253 253 253 253 253 253 253 253 253 253 +- 82 82 82 2 2 6 2 2 6 2 2 6 +- 2 2 6 2 2 6 2 2 6 14 14 14 +- 86 86 86 54 54 54 22 22 22 6 6 6 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 6 6 6 18 18 18 46 46 46 90 90 90 +- 46 46 46 18 18 18 6 6 6 182 182 182 +-253 253 253 246 246 246 206 206 206 190 190 190 +-190 190 190 190 190 190 190 190 190 190 190 190 +-206 206 206 231 231 231 250 250 250 253 253 253 +-253 253 253 253 253 253 253 253 253 253 253 253 +-202 202 202 14 14 14 2 2 6 2 2 6 +- 2 2 6 2 2 6 2 2 6 2 2 6 +- 42 42 42 86 86 86 42 42 42 18 18 18 +- 6 6 6 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 6 6 6 +- 14 14 14 38 38 38 74 74 74 66 66 66 +- 2 2 6 6 6 6 90 90 90 250 250 250 +-253 253 253 253 253 253 238 238 238 198 198 198 +-190 190 190 190 190 190 195 195 195 221 221 221 +-246 246 246 253 253 253 253 253 253 253 253 253 +-253 253 253 253 253 253 253 253 253 253 253 253 +-253 253 253 82 82 82 2 2 6 2 2 6 +- 2 2 6 2 2 6 2 2 6 2 2 6 +- 2 2 6 78 78 78 70 70 70 34 34 34 +- 14 14 14 6 6 6 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 14 14 14 +- 34 34 34 66 66 66 78 78 78 6 6 6 +- 2 2 6 18 18 18 218 218 218 253 253 253 +-253 253 253 253 253 253 253 253 253 246 246 246 +-226 226 226 231 231 231 246 246 246 253 253 253 +-253 253 253 253 253 253 253 253 253 253 253 253 +-253 253 253 253 253 253 253 253 253 253 253 253 +-253 253 253 178 178 178 2 2 6 2 2 6 +- 2 2 6 2 2 6 2 2 6 2 2 6 +- 2 2 6 18 18 18 90 90 90 62 62 62 +- 30 30 30 10 10 10 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 10 10 10 26 26 26 +- 58 58 58 90 90 90 18 18 18 2 2 6 +- 2 2 6 110 110 110 253 253 253 253 253 253 +-253 253 253 253 253 253 253 253 253 253 253 253 +-250 250 250 253 253 253 253 253 253 253 253 253 +-253 253 253 253 253 253 253 253 253 253 253 253 +-253 253 253 253 253 253 253 253 253 253 253 253 +-253 253 253 231 231 231 18 18 18 2 2 6 +- 2 2 6 2 2 6 2 2 6 2 2 6 +- 2 2 6 2 2 6 18 18 18 94 94 94 +- 54 54 54 26 26 26 10 10 10 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 6 6 6 22 22 22 50 50 50 +- 90 90 90 26 26 26 2 2 6 2 2 6 +- 14 14 14 195 195 195 250 250 250 253 253 253 +-253 253 253 253 253 253 253 253 253 253 253 253 +-253 253 253 253 253 253 253 253 253 253 253 253 +-253 253 253 253 253 253 253 253 253 253 253 253 +-253 253 253 253 253 253 253 253 253 253 253 253 +-250 250 250 242 242 242 54 54 54 2 2 6 +- 2 2 6 2 2 6 2 2 6 2 2 6 +- 2 2 6 2 2 6 2 2 6 38 38 38 +- 86 86 86 50 50 50 22 22 22 6 6 6 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 6 6 6 14 14 14 38 38 38 82 82 82 +- 34 34 34 2 2 6 2 2 6 2 2 6 +- 42 42 42 195 195 195 246 246 246 253 253 253 +-253 253 253 253 253 253 253 253 253 250 250 250 +-242 242 242 242 242 242 250 250 250 253 253 253 +-253 253 253 253 253 253 253 253 253 253 253 253 +-253 253 253 250 250 250 246 246 246 238 238 238 +-226 226 226 231 231 231 101 101 101 6 6 6 +- 2 2 6 2 2 6 2 2 6 2 2 6 +- 2 2 6 2 2 6 2 2 6 2 2 6 +- 38 38 38 82 82 82 42 42 42 14 14 14 +- 6 6 6 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 10 10 10 26 26 26 62 62 62 66 66 66 +- 2 2 6 2 2 6 2 2 6 6 6 6 +- 70 70 70 170 170 170 206 206 206 234 234 234 +-246 246 246 250 250 250 250 250 250 238 238 238 +-226 226 226 231 231 231 238 238 238 250 250 250 +-250 250 250 250 250 250 246 246 246 231 231 231 +-214 214 214 206 206 206 202 202 202 202 202 202 +-198 198 198 202 202 202 182 182 182 18 18 18 +- 2 2 6 2 2 6 2 2 6 2 2 6 +- 2 2 6 2 2 6 2 2 6 2 2 6 +- 2 2 6 62 62 62 66 66 66 30 30 30 +- 10 10 10 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 14 14 14 42 42 42 82 82 82 18 18 18 +- 2 2 6 2 2 6 2 2 6 10 10 10 +- 94 94 94 182 182 182 218 218 218 242 242 242 +-250 250 250 253 253 253 253 253 253 250 250 250 +-234 234 234 253 253 253 253 253 253 253 253 253 +-253 253 253 253 253 253 253 253 253 246 246 246 +-238 238 238 226 226 226 210 210 210 202 202 202 +-195 195 195 195 195 195 210 210 210 158 158 158 +- 6 6 6 14 14 14 50 50 50 14 14 14 +- 2 2 6 2 2 6 2 2 6 2 2 6 +- 2 2 6 6 6 6 86 86 86 46 46 46 +- 18 18 18 6 6 6 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 6 6 6 +- 22 22 22 54 54 54 70 70 70 2 2 6 +- 2 2 6 10 10 10 2 2 6 22 22 22 +-166 166 166 231 231 231 250 250 250 253 253 253 +-253 253 253 253 253 253 253 253 253 250 250 250 +-242 242 242 253 253 253 253 253 253 253 253 253 +-253 253 253 253 253 253 253 253 253 253 253 253 +-253 253 253 253 253 253 253 253 253 246 246 246 +-231 231 231 206 206 206 198 198 198 226 226 226 +- 94 94 94 2 2 6 6 6 6 38 38 38 +- 30 30 30 2 2 6 2 2 6 2 2 6 +- 2 2 6 2 2 6 62 62 62 66 66 66 +- 26 26 26 10 10 10 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 10 10 10 +- 30 30 30 74 74 74 50 50 50 2 2 6 +- 26 26 26 26 26 26 2 2 6 106 106 106 +-238 238 238 253 253 253 253 253 253 253 253 253 +-253 253 253 253 253 253 253 253 253 253 253 253 +-253 253 253 253 253 253 253 253 253 253 253 253 +-253 253 253 253 253 253 253 253 253 253 253 253 +-253 253 253 253 253 253 253 253 253 253 253 253 +-253 253 253 246 246 246 218 218 218 202 202 202 +-210 210 210 14 14 14 2 2 6 2 2 6 +- 30 30 30 22 22 22 2 2 6 2 2 6 +- 2 2 6 2 2 6 18 18 18 86 86 86 +- 42 42 42 14 14 14 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 14 14 14 +- 42 42 42 90 90 90 22 22 22 2 2 6 +- 42 42 42 2 2 6 18 18 18 218 218 218 +-253 253 253 253 253 253 253 253 253 253 253 253 +-253 253 253 253 253 253 253 253 253 253 253 253 +-253 253 253 253 253 253 253 253 253 253 253 253 +-253 253 253 253 253 253 253 253 253 253 253 253 +-253 253 253 253 253 253 253 253 253 253 253 253 +-253 253 253 253 253 253 250 250 250 221 221 221 +-218 218 218 101 101 101 2 2 6 14 14 14 +- 18 18 18 38 38 38 10 10 10 2 2 6 +- 2 2 6 2 2 6 2 2 6 78 78 78 +- 58 58 58 22 22 22 6 6 6 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 6 6 6 18 18 18 +- 54 54 54 82 82 82 2 2 6 26 26 26 +- 22 22 22 2 2 6 123 123 123 253 253 253 +-253 253 253 253 253 253 253 253 253 253 253 253 +-253 253 253 253 253 253 253 253 253 253 253 253 +-253 253 253 253 253 253 253 253 253 253 253 253 +-253 253 253 253 253 253 253 253 253 253 253 253 +-253 253 253 253 253 253 253 253 253 253 253 253 +-253 253 253 253 253 253 253 253 253 250 250 250 +-238 238 238 198 198 198 6 6 6 38 38 38 +- 58 58 58 26 26 26 38 38 38 2 2 6 +- 2 2 6 2 2 6 2 2 6 46 46 46 +- 78 78 78 30 30 30 10 10 10 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 10 10 10 30 30 30 +- 74 74 74 58 58 58 2 2 6 42 42 42 +- 2 2 6 22 22 22 231 231 231 253 253 253 +-253 253 253 253 253 253 253 253 253 253 253 253 +-253 253 253 253 253 253 253 253 253 250 250 250 +-253 253 253 253 253 253 253 253 253 253 253 253 +-253 253 253 253 253 253 253 253 253 253 253 253 +-253 253 253 253 253 253 253 253 253 253 253 253 +-253 253 253 253 253 253 253 253 253 253 253 253 +-253 253 253 246 246 246 46 46 46 38 38 38 +- 42 42 42 14 14 14 38 38 38 14 14 14 +- 2 2 6 2 2 6 2 2 6 6 6 6 +- 86 86 86 46 46 46 14 14 14 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 6 6 6 14 14 14 42 42 42 +- 90 90 90 18 18 18 18 18 18 26 26 26 +- 2 2 6 116 116 116 253 253 253 253 253 253 +-253 253 253 253 253 253 253 253 253 253 253 253 +-253 253 253 253 253 253 250 250 250 238 238 238 +-253 253 253 253 253 253 253 253 253 253 253 253 +-253 253 253 253 253 253 253 253 253 253 253 253 +-253 253 253 253 253 253 253 253 253 253 253 253 +-253 253 253 253 253 253 253 253 253 253 253 253 +-253 253 253 253 253 253 94 94 94 6 6 6 +- 2 2 6 2 2 6 10 10 10 34 34 34 +- 2 2 6 2 2 6 2 2 6 2 2 6 +- 74 74 74 58 58 58 22 22 22 6 6 6 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 10 10 10 26 26 26 66 66 66 +- 82 82 82 2 2 6 38 38 38 6 6 6 +- 14 14 14 210 210 210 253 253 253 253 253 253 +-253 253 253 253 253 253 253 253 253 253 253 253 +-253 253 253 253 253 253 246 246 246 242 242 242 +-253 253 253 253 253 253 253 253 253 253 253 253 +-253 253 253 253 253 253 253 253 253 253 253 253 +-253 253 253 253 253 253 253 253 253 253 253 253 +-253 253 253 253 253 253 253 253 253 253 253 253 +-253 253 253 253 253 253 144 144 144 2 2 6 +- 2 2 6 2 2 6 2 2 6 46 46 46 +- 2 2 6 2 2 6 2 2 6 2 2 6 +- 42 42 42 74 74 74 30 30 30 10 10 10 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 6 6 6 14 14 14 42 42 42 90 90 90 +- 26 26 26 6 6 6 42 42 42 2 2 6 +- 74 74 74 250 250 250 253 253 253 253 253 253 +-253 253 253 253 253 253 253 253 253 253 253 253 +-253 253 253 253 253 253 242 242 242 242 242 242 +-253 253 253 253 253 253 253 253 253 253 253 253 +-253 253 253 253 253 253 253 253 253 253 253 253 +-253 253 253 253 253 253 253 253 253 253 253 253 +-253 253 253 253 253 253 253 253 253 253 253 253 +-253 253 253 253 253 253 182 182 182 2 2 6 +- 2 2 6 2 2 6 2 2 6 46 46 46 +- 2 2 6 2 2 6 2 2 6 2 2 6 +- 10 10 10 86 86 86 38 38 38 10 10 10 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 10 10 10 26 26 26 66 66 66 82 82 82 +- 2 2 6 22 22 22 18 18 18 2 2 6 +-149 149 149 253 253 253 253 253 253 253 253 253 +-253 253 253 253 253 253 253 253 253 253 253 253 +-253 253 253 253 253 253 234 234 234 242 242 242 +-253 253 253 253 253 253 253 253 253 253 253 253 +-253 253 253 253 253 253 253 253 253 253 253 253 +-253 253 253 253 253 253 253 253 253 253 253 253 +-253 253 253 253 253 253 253 253 253 253 253 253 +-253 253 253 253 253 253 206 206 206 2 2 6 +- 2 2 6 2 2 6 2 2 6 38 38 38 +- 2 2 6 2 2 6 2 2 6 2 2 6 +- 6 6 6 86 86 86 46 46 46 14 14 14 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 6 6 6 +- 18 18 18 46 46 46 86 86 86 18 18 18 +- 2 2 6 34 34 34 10 10 10 6 6 6 +-210 210 210 253 253 253 253 253 253 253 253 253 +-253 253 253 253 253 253 253 253 253 253 253 253 +-253 253 253 253 253 253 234 234 234 242 242 242 +-253 253 253 253 253 253 253 253 253 253 253 253 +-253 253 253 253 253 253 253 253 253 253 253 253 +-253 253 253 253 253 253 253 253 253 253 253 253 +-253 253 253 253 253 253 253 253 253 253 253 253 +-253 253 253 253 253 253 221 221 221 6 6 6 +- 2 2 6 2 2 6 6 6 6 30 30 30 +- 2 2 6 2 2 6 2 2 6 2 2 6 +- 2 2 6 82 82 82 54 54 54 18 18 18 +- 6 6 6 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 10 10 10 +- 26 26 26 66 66 66 62 62 62 2 2 6 +- 2 2 6 38 38 38 10 10 10 26 26 26 +-238 238 238 253 253 253 253 253 253 253 253 253 +-253 253 253 253 253 253 253 253 253 253 253 253 +-253 253 253 253 253 253 231 231 231 238 238 238 +-253 253 253 253 253 253 253 253 253 253 253 253 +-253 253 253 253 253 253 253 253 253 253 253 253 +-253 253 253 253 253 253 253 253 253 253 253 253 +-253 253 253 253 253 253 253 253 253 253 253 253 +-253 253 253 253 253 253 231 231 231 6 6 6 +- 2 2 6 2 2 6 10 10 10 30 30 30 +- 2 2 6 2 2 6 2 2 6 2 2 6 +- 2 2 6 66 66 66 58 58 58 22 22 22 +- 6 6 6 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 10 10 10 +- 38 38 38 78 78 78 6 6 6 2 2 6 +- 2 2 6 46 46 46 14 14 14 42 42 42 +-246 246 246 253 253 253 253 253 253 253 253 253 +-253 253 253 253 253 253 253 253 253 253 253 253 +-253 253 253 253 253 253 231 231 231 242 242 242 +-253 253 253 253 253 253 253 253 253 253 253 253 +-253 253 253 253 253 253 253 253 253 253 253 253 +-253 253 253 253 253 253 253 253 253 253 253 253 +-253 253 253 253 253 253 253 253 253 253 253 253 +-253 253 253 253 253 253 234 234 234 10 10 10 +- 2 2 6 2 2 6 22 22 22 14 14 14 +- 2 2 6 2 2 6 2 2 6 2 2 6 +- 2 2 6 66 66 66 62 62 62 22 22 22 +- 6 6 6 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 6 6 6 18 18 18 +- 50 50 50 74 74 74 2 2 6 2 2 6 +- 14 14 14 70 70 70 34 34 34 62 62 62 +-250 250 250 253 253 253 253 253 253 253 253 253 +-253 253 253 253 253 253 253 253 253 253 253 253 +-253 253 253 253 253 253 231 231 231 246 246 246 +-253 253 253 253 253 253 253 253 253 253 253 253 +-253 253 253 253 253 253 253 253 253 253 253 253 +-253 253 253 253 253 253 253 253 253 253 253 253 +-253 253 253 253 253 253 253 253 253 253 253 253 +-253 253 253 253 253 253 234 234 234 14 14 14 +- 2 2 6 2 2 6 30 30 30 2 2 6 +- 2 2 6 2 2 6 2 2 6 2 2 6 +- 2 2 6 66 66 66 62 62 62 22 22 22 +- 6 6 6 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 6 6 6 18 18 18 +- 54 54 54 62 62 62 2 2 6 2 2 6 +- 2 2 6 30 30 30 46 46 46 70 70 70 +-250 250 250 253 253 253 253 253 253 253 253 253 +-253 253 253 253 253 253 253 253 253 253 253 253 +-253 253 253 253 253 253 231 231 231 246 246 246 +-253 253 253 253 253 253 253 253 253 253 253 253 +-253 253 253 253 253 253 253 253 253 253 253 253 +-253 253 253 253 253 253 253 253 253 253 253 253 +-253 253 253 253 253 253 253 253 253 253 253 253 +-253 253 253 253 253 253 226 226 226 10 10 10 +- 2 2 6 6 6 6 30 30 30 2 2 6 +- 2 2 6 2 2 6 2 2 6 2 2 6 +- 2 2 6 66 66 66 58 58 58 22 22 22 +- 6 6 6 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 6 6 6 22 22 22 +- 58 58 58 62 62 62 2 2 6 2 2 6 +- 2 2 6 2 2 6 30 30 30 78 78 78 +-250 250 250 253 253 253 253 253 253 253 253 253 +-253 253 253 253 253 253 253 253 253 253 253 253 +-253 253 253 253 253 253 231 231 231 246 246 246 +-253 253 253 253 253 253 253 253 253 253 253 253 +-253 253 253 253 253 253 253 253 253 253 253 253 +-253 253 253 253 253 253 253 253 253 253 253 253 +-253 253 253 253 253 253 253 253 253 253 253 253 +-253 253 253 253 253 253 206 206 206 2 2 6 +- 22 22 22 34 34 34 18 14 6 22 22 22 +- 26 26 26 18 18 18 6 6 6 2 2 6 +- 2 2 6 82 82 82 54 54 54 18 18 18 +- 6 6 6 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 6 6 6 26 26 26 +- 62 62 62 106 106 106 74 54 14 185 133 11 +-210 162 10 121 92 8 6 6 6 62 62 62 +-238 238 238 253 253 253 253 253 253 253 253 253 +-253 253 253 253 253 253 253 253 253 253 253 253 +-253 253 253 253 253 253 231 231 231 246 246 246 +-253 253 253 253 253 253 253 253 253 253 253 253 +-253 253 253 253 253 253 253 253 253 253 253 253 +-253 253 253 253 253 253 253 253 253 253 253 253 +-253 253 253 253 253 253 253 253 253 253 253 253 +-253 253 253 253 253 253 158 158 158 18 18 18 +- 14 14 14 2 2 6 2 2 6 2 2 6 +- 6 6 6 18 18 18 66 66 66 38 38 38 +- 6 6 6 94 94 94 50 50 50 18 18 18 +- 6 6 6 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 6 6 6 +- 10 10 10 10 10 10 18 18 18 38 38 38 +- 78 78 78 142 134 106 216 158 10 242 186 14 +-246 190 14 246 190 14 156 118 10 10 10 10 +- 90 90 90 238 238 238 253 253 253 253 253 253 +-253 253 253 253 253 253 253 253 253 253 253 253 +-253 253 253 253 253 253 231 231 231 250 250 250 +-253 253 253 253 253 253 253 253 253 253 253 253 +-253 253 253 253 253 253 253 253 253 253 253 253 +-253 253 253 253 253 253 253 253 253 253 253 253 +-253 253 253 253 253 253 253 253 253 246 230 190 +-238 204 91 238 204 91 181 142 44 37 26 9 +- 2 2 6 2 2 6 2 2 6 2 2 6 +- 2 2 6 2 2 6 38 38 38 46 46 46 +- 26 26 26 106 106 106 54 54 54 18 18 18 +- 6 6 6 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 6 6 6 14 14 14 22 22 22 +- 30 30 30 38 38 38 50 50 50 70 70 70 +-106 106 106 190 142 34 226 170 11 242 186 14 +-246 190 14 246 190 14 246 190 14 154 114 10 +- 6 6 6 74 74 74 226 226 226 253 253 253 +-253 253 253 253 253 253 253 253 253 253 253 253 +-253 253 253 253 253 253 231 231 231 250 250 250 +-253 253 253 253 253 253 253 253 253 253 253 253 +-253 253 253 253 253 253 253 253 253 253 253 253 +-253 253 253 253 253 253 253 253 253 253 253 253 +-253 253 253 253 253 253 253 253 253 228 184 62 +-241 196 14 241 208 19 232 195 16 38 30 10 +- 2 2 6 2 2 6 2 2 6 2 2 6 +- 2 2 6 6 6 6 30 30 30 26 26 26 +-203 166 17 154 142 90 66 66 66 26 26 26 +- 6 6 6 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 6 6 6 18 18 18 38 38 38 58 58 58 +- 78 78 78 86 86 86 101 101 101 123 123 123 +-175 146 61 210 150 10 234 174 13 246 186 14 +-246 190 14 246 190 14 246 190 14 238 190 10 +-102 78 10 2 2 6 46 46 46 198 198 198 +-253 253 253 253 253 253 253 253 253 253 253 253 +-253 253 253 253 253 253 234 234 234 242 242 242 +-253 253 253 253 253 253 253 253 253 253 253 253 +-253 253 253 253 253 253 253 253 253 253 253 253 +-253 253 253 253 253 253 253 253 253 253 253 253 +-253 253 253 253 253 253 253 253 253 224 178 62 +-242 186 14 241 196 14 210 166 10 22 18 6 +- 2 2 6 2 2 6 2 2 6 2 2 6 +- 2 2 6 2 2 6 6 6 6 121 92 8 +-238 202 15 232 195 16 82 82 82 34 34 34 +- 10 10 10 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 14 14 14 38 38 38 70 70 70 154 122 46 +-190 142 34 200 144 11 197 138 11 197 138 11 +-213 154 11 226 170 11 242 186 14 246 190 14 +-246 190 14 246 190 14 246 190 14 246 190 14 +-225 175 15 46 32 6 2 2 6 22 22 22 +-158 158 158 250 250 250 253 253 253 253 253 253 +-253 253 253 253 253 253 253 253 253 253 253 253 +-253 253 253 253 253 253 253 253 253 253 253 253 +-253 253 253 253 253 253 253 253 253 253 253 253 +-253 253 253 253 253 253 253 253 253 253 253 253 +-253 253 253 250 250 250 242 242 242 224 178 62 +-239 182 13 236 186 11 213 154 11 46 32 6 +- 2 2 6 2 2 6 2 2 6 2 2 6 +- 2 2 6 2 2 6 61 42 6 225 175 15 +-238 190 10 236 186 11 112 100 78 42 42 42 +- 14 14 14 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 6 6 6 +- 22 22 22 54 54 54 154 122 46 213 154 11 +-226 170 11 230 174 11 226 170 11 226 170 11 +-236 178 12 242 186 14 246 190 14 246 190 14 +-246 190 14 246 190 14 246 190 14 246 190 14 +-241 196 14 184 144 12 10 10 10 2 2 6 +- 6 6 6 116 116 116 242 242 242 253 253 253 +-253 253 253 253 253 253 253 253 253 253 253 253 +-253 253 253 253 253 253 253 253 253 253 253 253 +-253 253 253 253 253 253 253 253 253 253 253 253 +-253 253 253 253 253 253 253 253 253 253 253 253 +-253 253 253 231 231 231 198 198 198 214 170 54 +-236 178 12 236 178 12 210 150 10 137 92 6 +- 18 14 6 2 2 6 2 2 6 2 2 6 +- 6 6 6 70 47 6 200 144 11 236 178 12 +-239 182 13 239 182 13 124 112 88 58 58 58 +- 22 22 22 6 6 6 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 10 10 10 +- 30 30 30 70 70 70 180 133 36 226 170 11 +-239 182 13 242 186 14 242 186 14 246 186 14 +-246 190 14 246 190 14 246 190 14 246 190 14 +-246 190 14 246 190 14 246 190 14 246 190 14 +-246 190 14 232 195 16 98 70 6 2 2 6 +- 2 2 6 2 2 6 66 66 66 221 221 221 +-253 253 253 253 253 253 253 253 253 253 253 253 +-253 253 253 253 253 253 253 253 253 253 253 253 +-253 253 253 253 253 253 253 253 253 253 253 253 +-253 253 253 253 253 253 253 253 253 253 253 253 +-253 253 253 206 206 206 198 198 198 214 166 58 +-230 174 11 230 174 11 216 158 10 192 133 9 +-163 110 8 116 81 8 102 78 10 116 81 8 +-167 114 7 197 138 11 226 170 11 239 182 13 +-242 186 14 242 186 14 162 146 94 78 78 78 +- 34 34 34 14 14 14 6 6 6 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 6 6 6 +- 30 30 30 78 78 78 190 142 34 226 170 11 +-239 182 13 246 190 14 246 190 14 246 190 14 +-246 190 14 246 190 14 246 190 14 246 190 14 +-246 190 14 246 190 14 246 190 14 246 190 14 +-246 190 14 241 196 14 203 166 17 22 18 6 +- 2 2 6 2 2 6 2 2 6 38 38 38 +-218 218 218 253 253 253 253 253 253 253 253 253 +-253 253 253 253 253 253 253 253 253 253 253 253 +-253 253 253 253 253 253 253 253 253 253 253 253 +-253 253 253 253 253 253 253 253 253 253 253 253 +-250 250 250 206 206 206 198 198 198 202 162 69 +-226 170 11 236 178 12 224 166 10 210 150 10 +-200 144 11 197 138 11 192 133 9 197 138 11 +-210 150 10 226 170 11 242 186 14 246 190 14 +-246 190 14 246 186 14 225 175 15 124 112 88 +- 62 62 62 30 30 30 14 14 14 6 6 6 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 10 10 10 +- 30 30 30 78 78 78 174 135 50 224 166 10 +-239 182 13 246 190 14 246 190 14 246 190 14 +-246 190 14 246 190 14 246 190 14 246 190 14 +-246 190 14 246 190 14 246 190 14 246 190 14 +-246 190 14 246 190 14 241 196 14 139 102 15 +- 2 2 6 2 2 6 2 2 6 2 2 6 +- 78 78 78 250 250 250 253 253 253 253 253 253 +-253 253 253 253 253 253 253 253 253 253 253 253 +-253 253 253 253 253 253 253 253 253 253 253 253 +-253 253 253 253 253 253 253 253 253 253 253 253 +-250 250 250 214 214 214 198 198 198 190 150 46 +-219 162 10 236 178 12 234 174 13 224 166 10 +-216 158 10 213 154 11 213 154 11 216 158 10 +-226 170 11 239 182 13 246 190 14 246 190 14 +-246 190 14 246 190 14 242 186 14 206 162 42 +-101 101 101 58 58 58 30 30 30 14 14 14 +- 6 6 6 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 10 10 10 +- 30 30 30 74 74 74 174 135 50 216 158 10 +-236 178 12 246 190 14 246 190 14 246 190 14 +-246 190 14 246 190 14 246 190 14 246 190 14 +-246 190 14 246 190 14 246 190 14 246 190 14 +-246 190 14 246 190 14 241 196 14 226 184 13 +- 61 42 6 2 2 6 2 2 6 2 2 6 +- 22 22 22 238 238 238 253 253 253 253 253 253 +-253 253 253 253 253 253 253 253 253 253 253 253 +-253 253 253 253 253 253 253 253 253 253 253 253 +-253 253 253 253 253 253 253 253 253 253 253 253 +-253 253 253 226 226 226 187 187 187 180 133 36 +-216 158 10 236 178 12 239 182 13 236 178 12 +-230 174 11 226 170 11 226 170 11 230 174 11 +-236 178 12 242 186 14 246 190 14 246 190 14 +-246 190 14 246 190 14 246 186 14 239 182 13 +-206 162 42 106 106 106 66 66 66 34 34 34 +- 14 14 14 6 6 6 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 6 6 6 +- 26 26 26 70 70 70 163 133 67 213 154 11 +-236 178 12 246 190 14 246 190 14 246 190 14 +-246 190 14 246 190 14 246 190 14 246 190 14 +-246 190 14 246 190 14 246 190 14 246 190 14 +-246 190 14 246 190 14 246 190 14 241 196 14 +-190 146 13 18 14 6 2 2 6 2 2 6 +- 46 46 46 246 246 246 253 253 253 253 253 253 +-253 253 253 253 253 253 253 253 253 253 253 253 +-253 253 253 253 253 253 253 253 253 253 253 253 +-253 253 253 253 253 253 253 253 253 253 253 253 +-253 253 253 221 221 221 86 86 86 156 107 11 +-216 158 10 236 178 12 242 186 14 246 186 14 +-242 186 14 239 182 13 239 182 13 242 186 14 +-242 186 14 246 186 14 246 190 14 246 190 14 +-246 190 14 246 190 14 246 190 14 246 190 14 +-242 186 14 225 175 15 142 122 72 66 66 66 +- 30 30 30 10 10 10 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 6 6 6 +- 26 26 26 70 70 70 163 133 67 210 150 10 +-236 178 12 246 190 14 246 190 14 246 190 14 +-246 190 14 246 190 14 246 190 14 246 190 14 +-246 190 14 246 190 14 246 190 14 246 190 14 +-246 190 14 246 190 14 246 190 14 246 190 14 +-232 195 16 121 92 8 34 34 34 106 106 106 +-221 221 221 253 253 253 253 253 253 253 253 253 +-253 253 253 253 253 253 253 253 253 253 253 253 +-253 253 253 253 253 253 253 253 253 253 253 253 +-253 253 253 253 253 253 253 253 253 253 253 253 +-242 242 242 82 82 82 18 14 6 163 110 8 +-216 158 10 236 178 12 242 186 14 246 190 14 +-246 190 14 246 190 14 246 190 14 246 190 14 +-246 190 14 246 190 14 246 190 14 246 190 14 +-246 190 14 246 190 14 246 190 14 246 190 14 +-246 190 14 246 190 14 242 186 14 163 133 67 +- 46 46 46 18 18 18 6 6 6 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 10 10 10 +- 30 30 30 78 78 78 163 133 67 210 150 10 +-236 178 12 246 186 14 246 190 14 246 190 14 +-246 190 14 246 190 14 246 190 14 246 190 14 +-246 190 14 246 190 14 246 190 14 246 190 14 +-246 190 14 246 190 14 246 190 14 246 190 14 +-241 196 14 215 174 15 190 178 144 253 253 253 +-253 253 253 253 253 253 253 253 253 253 253 253 +-253 253 253 253 253 253 253 253 253 253 253 253 +-253 253 253 253 253 253 253 253 253 253 253 253 +-253 253 253 253 253 253 253 253 253 218 218 218 +- 58 58 58 2 2 6 22 18 6 167 114 7 +-216 158 10 236 178 12 246 186 14 246 190 14 +-246 190 14 246 190 14 246 190 14 246 190 14 +-246 190 14 246 190 14 246 190 14 246 190 14 +-246 190 14 246 190 14 246 190 14 246 190 14 +-246 190 14 246 186 14 242 186 14 190 150 46 +- 54 54 54 22 22 22 6 6 6 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 14 14 14 +- 38 38 38 86 86 86 180 133 36 213 154 11 +-236 178 12 246 186 14 246 190 14 246 190 14 +-246 190 14 246 190 14 246 190 14 246 190 14 +-246 190 14 246 190 14 246 190 14 246 190 14 +-246 190 14 246 190 14 246 190 14 246 190 14 +-246 190 14 232 195 16 190 146 13 214 214 214 +-253 253 253 253 253 253 253 253 253 253 253 253 +-253 253 253 253 253 253 253 253 253 253 253 253 +-253 253 253 253 253 253 253 253 253 253 253 253 +-253 253 253 250 250 250 170 170 170 26 26 26 +- 2 2 6 2 2 6 37 26 9 163 110 8 +-219 162 10 239 182 13 246 186 14 246 190 14 +-246 190 14 246 190 14 246 190 14 246 190 14 +-246 190 14 246 190 14 246 190 14 246 190 14 +-246 190 14 246 190 14 246 190 14 246 190 14 +-246 186 14 236 178 12 224 166 10 142 122 72 +- 46 46 46 18 18 18 6 6 6 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 6 6 6 18 18 18 +- 50 50 50 109 106 95 192 133 9 224 166 10 +-242 186 14 246 190 14 246 190 14 246 190 14 +-246 190 14 246 190 14 246 190 14 246 190 14 +-246 190 14 246 190 14 246 190 14 246 190 14 +-246 190 14 246 190 14 246 190 14 246 190 14 +-242 186 14 226 184 13 210 162 10 142 110 46 +-226 226 226 253 253 253 253 253 253 253 253 253 +-253 253 253 253 253 253 253 253 253 253 253 253 +-253 253 253 253 253 253 253 253 253 253 253 253 +-198 198 198 66 66 66 2 2 6 2 2 6 +- 2 2 6 2 2 6 50 34 6 156 107 11 +-219 162 10 239 182 13 246 186 14 246 190 14 +-246 190 14 246 190 14 246 190 14 246 190 14 +-246 190 14 246 190 14 246 190 14 246 190 14 +-246 190 14 246 190 14 246 190 14 242 186 14 +-234 174 13 213 154 11 154 122 46 66 66 66 +- 30 30 30 10 10 10 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 6 6 6 22 22 22 +- 58 58 58 154 121 60 206 145 10 234 174 13 +-242 186 14 246 186 14 246 190 14 246 190 14 +-246 190 14 246 190 14 246 190 14 246 190 14 +-246 190 14 246 190 14 246 190 14 246 190 14 +-246 190 14 246 190 14 246 190 14 246 190 14 +-246 186 14 236 178 12 210 162 10 163 110 8 +- 61 42 6 138 138 138 218 218 218 250 250 250 +-253 253 253 253 253 253 253 253 253 250 250 250 +-242 242 242 210 210 210 144 144 144 66 66 66 +- 6 6 6 2 2 6 2 2 6 2 2 6 +- 2 2 6 2 2 6 61 42 6 163 110 8 +-216 158 10 236 178 12 246 190 14 246 190 14 +-246 190 14 246 190 14 246 190 14 246 190 14 +-246 190 14 246 190 14 246 190 14 246 190 14 +-246 190 14 239 182 13 230 174 11 216 158 10 +-190 142 34 124 112 88 70 70 70 38 38 38 +- 18 18 18 6 6 6 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 6 6 6 22 22 22 +- 62 62 62 168 124 44 206 145 10 224 166 10 +-236 178 12 239 182 13 242 186 14 242 186 14 +-246 186 14 246 190 14 246 190 14 246 190 14 +-246 190 14 246 190 14 246 190 14 246 190 14 +-246 190 14 246 190 14 246 190 14 246 190 14 +-246 190 14 236 178 12 216 158 10 175 118 6 +- 80 54 7 2 2 6 6 6 6 30 30 30 +- 54 54 54 62 62 62 50 50 50 38 38 38 +- 14 14 14 2 2 6 2 2 6 2 2 6 +- 2 2 6 2 2 6 2 2 6 2 2 6 +- 2 2 6 6 6 6 80 54 7 167 114 7 +-213 154 11 236 178 12 246 190 14 246 190 14 +-246 190 14 246 190 14 246 190 14 246 190 14 +-246 190 14 242 186 14 239 182 13 239 182 13 +-230 174 11 210 150 10 174 135 50 124 112 88 +- 82 82 82 54 54 54 34 34 34 18 18 18 +- 6 6 6 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 6 6 6 18 18 18 +- 50 50 50 158 118 36 192 133 9 200 144 11 +-216 158 10 219 162 10 224 166 10 226 170 11 +-230 174 11 236 178 12 239 182 13 239 182 13 +-242 186 14 246 186 14 246 190 14 246 190 14 +-246 190 14 246 190 14 246 190 14 246 190 14 +-246 186 14 230 174 11 210 150 10 163 110 8 +-104 69 6 10 10 10 2 2 6 2 2 6 +- 2 2 6 2 2 6 2 2 6 2 2 6 +- 2 2 6 2 2 6 2 2 6 2 2 6 +- 2 2 6 2 2 6 2 2 6 2 2 6 +- 2 2 6 6 6 6 91 60 6 167 114 7 +-206 145 10 230 174 11 242 186 14 246 190 14 +-246 190 14 246 190 14 246 186 14 242 186 14 +-239 182 13 230 174 11 224 166 10 213 154 11 +-180 133 36 124 112 88 86 86 86 58 58 58 +- 38 38 38 22 22 22 10 10 10 6 6 6 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 14 14 14 +- 34 34 34 70 70 70 138 110 50 158 118 36 +-167 114 7 180 123 7 192 133 9 197 138 11 +-200 144 11 206 145 10 213 154 11 219 162 10 +-224 166 10 230 174 11 239 182 13 242 186 14 +-246 186 14 246 186 14 246 186 14 246 186 14 +-239 182 13 216 158 10 185 133 11 152 99 6 +-104 69 6 18 14 6 2 2 6 2 2 6 +- 2 2 6 2 2 6 2 2 6 2 2 6 +- 2 2 6 2 2 6 2 2 6 2 2 6 +- 2 2 6 2 2 6 2 2 6 2 2 6 +- 2 2 6 6 6 6 80 54 7 152 99 6 +-192 133 9 219 162 10 236 178 12 239 182 13 +-246 186 14 242 186 14 239 182 13 236 178 12 +-224 166 10 206 145 10 192 133 9 154 121 60 +- 94 94 94 62 62 62 42 42 42 22 22 22 +- 14 14 14 6 6 6 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 6 6 6 +- 18 18 18 34 34 34 58 58 58 78 78 78 +-101 98 89 124 112 88 142 110 46 156 107 11 +-163 110 8 167 114 7 175 118 6 180 123 7 +-185 133 11 197 138 11 210 150 10 219 162 10 +-226 170 11 236 178 12 236 178 12 234 174 13 +-219 162 10 197 138 11 163 110 8 130 83 6 +- 91 60 6 10 10 10 2 2 6 2 2 6 +- 18 18 18 38 38 38 38 38 38 38 38 38 +- 38 38 38 38 38 38 38 38 38 38 38 38 +- 38 38 38 38 38 38 26 26 26 2 2 6 +- 2 2 6 6 6 6 70 47 6 137 92 6 +-175 118 6 200 144 11 219 162 10 230 174 11 +-234 174 13 230 174 11 219 162 10 210 150 10 +-192 133 9 163 110 8 124 112 88 82 82 82 +- 50 50 50 30 30 30 14 14 14 6 6 6 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 6 6 6 14 14 14 22 22 22 34 34 34 +- 42 42 42 58 58 58 74 74 74 86 86 86 +-101 98 89 122 102 70 130 98 46 121 87 25 +-137 92 6 152 99 6 163 110 8 180 123 7 +-185 133 11 197 138 11 206 145 10 200 144 11 +-180 123 7 156 107 11 130 83 6 104 69 6 +- 50 34 6 54 54 54 110 110 110 101 98 89 +- 86 86 86 82 82 82 78 78 78 78 78 78 +- 78 78 78 78 78 78 78 78 78 78 78 78 +- 78 78 78 82 82 82 86 86 86 94 94 94 +-106 106 106 101 101 101 86 66 34 124 80 6 +-156 107 11 180 123 7 192 133 9 200 144 11 +-206 145 10 200 144 11 192 133 9 175 118 6 +-139 102 15 109 106 95 70 70 70 42 42 42 +- 22 22 22 10 10 10 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 6 6 6 10 10 10 +- 14 14 14 22 22 22 30 30 30 38 38 38 +- 50 50 50 62 62 62 74 74 74 90 90 90 +-101 98 89 112 100 78 121 87 25 124 80 6 +-137 92 6 152 99 6 152 99 6 152 99 6 +-138 86 6 124 80 6 98 70 6 86 66 30 +-101 98 89 82 82 82 58 58 58 46 46 46 +- 38 38 38 34 34 34 34 34 34 34 34 34 +- 34 34 34 34 34 34 34 34 34 34 34 34 +- 34 34 34 34 34 34 38 38 38 42 42 42 +- 54 54 54 82 82 82 94 86 76 91 60 6 +-134 86 6 156 107 11 167 114 7 175 118 6 +-175 118 6 167 114 7 152 99 6 121 87 25 +-101 98 89 62 62 62 34 34 34 18 18 18 +- 6 6 6 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 6 6 6 6 6 6 10 10 10 +- 18 18 18 22 22 22 30 30 30 42 42 42 +- 50 50 50 66 66 66 86 86 86 101 98 89 +-106 86 58 98 70 6 104 69 6 104 69 6 +-104 69 6 91 60 6 82 62 34 90 90 90 +- 62 62 62 38 38 38 22 22 22 14 14 14 +- 10 10 10 10 10 10 10 10 10 10 10 10 +- 10 10 10 10 10 10 6 6 6 10 10 10 +- 10 10 10 10 10 10 10 10 10 14 14 14 +- 22 22 22 42 42 42 70 70 70 89 81 66 +- 80 54 7 104 69 6 124 80 6 137 92 6 +-134 86 6 116 81 8 100 82 52 86 86 86 +- 58 58 58 30 30 30 14 14 14 6 6 6 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 6 6 6 10 10 10 14 14 14 +- 18 18 18 26 26 26 38 38 38 54 54 54 +- 70 70 70 86 86 86 94 86 76 89 81 66 +- 89 81 66 86 86 86 74 74 74 50 50 50 +- 30 30 30 14 14 14 6 6 6 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 6 6 6 18 18 18 34 34 34 58 58 58 +- 82 82 82 89 81 66 89 81 66 89 81 66 +- 94 86 66 94 86 76 74 74 74 50 50 50 +- 26 26 26 14 14 14 6 6 6 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 6 6 6 6 6 6 14 14 14 18 18 18 +- 30 30 30 38 38 38 46 46 46 54 54 54 +- 50 50 50 42 42 42 30 30 30 18 18 18 +- 10 10 10 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 6 6 6 14 14 14 26 26 26 +- 38 38 38 50 50 50 58 58 58 58 58 58 +- 54 54 54 42 42 42 30 30 30 18 18 18 +- 10 10 10 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 6 6 6 +- 6 6 6 10 10 10 14 14 14 18 18 18 +- 18 18 18 14 14 14 10 10 10 6 6 6 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 6 6 6 +- 14 14 14 18 18 18 22 22 22 22 22 22 +- 18 18 18 14 14 14 10 10 10 6 6 6 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 +- 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 1 0 ++0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 ++0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 ++10 15 3 2 3 1 12 18 4 42 61 14 19 27 6 11 16 4 ++38 55 13 10 15 3 3 4 1 10 15 3 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 3 1 ++12 18 4 1 1 0 23 34 8 31 45 11 10 15 3 32 47 11 ++34 49 12 3 4 1 3 4 1 3 4 1 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 10 15 3 29 42 10 26 37 9 12 18 4 ++55 80 19 81 118 28 55 80 19 92 132 31 106 153 36 69 100 23 ++100 144 34 80 116 27 42 61 14 81 118 28 23 34 8 27 40 9 ++15 21 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 1 1 0 29 42 10 15 21 5 50 72 17 ++74 107 25 45 64 15 102 148 35 80 116 27 84 121 28 111 160 38 ++69 100 23 65 94 22 81 118 28 29 42 10 17 25 6 29 42 10 ++23 34 8 2 3 1 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 4 1 ++15 21 5 15 21 5 34 49 12 101 146 34 111 161 38 97 141 33 ++97 141 33 119 172 41 117 170 40 116 167 40 118 170 40 118 171 40 ++117 169 40 118 170 40 111 160 38 118 170 40 96 138 32 89 128 30 ++81 118 28 11 16 4 10 15 3 1 1 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++3 4 1 3 4 1 34 49 12 101 146 34 79 115 27 111 160 38 ++114 165 39 113 163 39 118 170 40 117 169 40 118 171 40 117 169 40 ++116 167 40 119 172 41 113 163 39 92 132 31 105 151 36 113 163 39 ++75 109 26 19 27 6 16 23 5 11 16 4 0 1 0 0 0 0 ++0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10 15 3 ++80 116 27 106 153 36 105 151 36 114 165 39 118 170 40 118 171 40 ++118 171 40 117 169 40 117 169 40 117 169 40 117 169 40 117 169 40 ++117 169 40 117 169 40 117 170 40 117 169 40 118 170 40 118 170 40 ++117 170 40 75 109 26 75 109 26 34 49 12 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 4 1 ++64 92 22 65 94 22 100 144 34 118 171 40 118 170 40 117 169 40 ++117 169 40 117 169 40 117 169 40 117 169 40 117 169 40 117 169 40 ++117 169 40 117 169 40 117 169 40 118 171 41 118 170 40 117 169 40 ++109 158 37 105 151 36 104 150 35 47 69 16 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++42 61 14 115 167 39 118 170 40 117 169 40 117 169 40 117 169 40 ++117 170 40 117 170 40 117 169 40 117 169 40 117 169 40 117 169 40 ++117 169 40 117 169 40 117 169 40 117 169 40 117 169 40 117 169 40 ++117 169 40 117 169 40 118 170 40 96 138 32 17 25 6 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 47 69 16 ++114 165 39 117 168 40 117 170 40 117 169 40 117 169 40 117 169 40 ++117 169 40 117 169 40 117 169 40 117 169 40 117 169 40 117 169 40 ++117 169 40 117 169 40 118 170 40 117 169 40 117 169 40 117 169 40 ++117 170 40 119 172 41 96 138 32 12 18 4 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10 15 3 ++32 47 11 105 151 36 118 170 40 117 169 40 117 169 40 116 168 40 ++109 157 37 111 160 38 117 169 40 118 171 40 117 169 40 117 169 40 ++117 169 40 117 169 40 117 169 40 117 169 40 117 169 40 117 169 40 ++117 169 40 117 169 40 117 169 40 118 171 40 69 100 23 2 3 1 ++0 0 0 0 0 0 0 0 0 0 0 0 19 27 6 101 146 34 ++118 171 40 117 169 40 117 169 40 117 169 40 117 169 40 117 169 40 ++117 169 40 117 169 40 117 169 40 117 169 40 117 169 40 117 170 40 ++118 171 40 115 166 39 107 154 36 111 161 38 117 169 40 117 169 40 ++117 169 40 118 171 40 75 109 26 19 27 6 2 3 1 0 0 0 ++0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 23 5 ++89 128 30 117 169 40 117 169 40 117 169 40 117 169 40 117 169 40 ++111 160 38 92 132 31 79 115 27 96 138 32 115 166 39 119 171 41 ++117 169 40 117 169 40 117 169 40 117 169 40 117 169 40 117 169 40 ++117 169 40 117 169 40 117 169 40 118 170 40 109 157 37 26 37 9 ++0 0 0 0 0 0 0 0 0 0 0 0 64 92 22 118 171 40 ++117 169 40 117 169 40 117 169 40 117 169 40 117 169 40 117 169 40 ++117 169 40 117 169 40 117 169 40 118 170 40 118 171 40 109 157 37 ++89 128 30 81 118 28 100 144 34 115 166 39 117 169 40 117 169 40 ++117 169 40 117 170 40 113 163 39 60 86 20 1 1 0 0 0 0 ++0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++27 40 9 96 138 32 118 170 40 117 169 40 117 169 40 117 169 40 ++117 170 40 117 169 40 101 146 34 67 96 23 55 80 19 84 121 28 ++113 163 39 119 171 41 117 169 40 117 169 40 117 169 40 117 169 40 ++117 169 40 117 169 40 117 169 40 117 169 40 119 171 41 65 94 22 ++0 0 0 0 0 0 0 0 0 15 21 5 101 146 34 118 171 40 ++117 169 40 117 169 40 117 169 40 117 169 40 117 169 40 117 169 40 ++117 169 40 118 170 40 118 171 40 104 150 35 69 100 23 53 76 18 ++81 118 28 111 160 38 118 170 40 117 169 40 117 169 40 117 169 40 ++117 169 40 114 165 39 69 100 23 10 15 3 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 ++31 45 11 77 111 26 117 169 40 117 169 40 117 169 40 117 169 40 ++117 169 40 117 169 40 118 170 40 116 168 40 92 132 31 47 69 16 ++38 55 13 81 118 28 113 163 39 119 171 41 117 169 40 117 169 40 ++117 169 40 117 169 40 117 169 40 117 169 40 118 171 41 92 132 31 ++10 15 3 0 0 0 0 0 0 36 52 12 115 166 39 117 169 40 ++117 169 40 117 169 40 117 169 40 117 169 40 117 169 40 118 170 40 ++118 171 40 102 148 35 64 92 22 34 49 12 65 94 22 106 153 36 ++118 171 40 117 170 40 117 169 40 117 169 40 117 169 40 117 169 40 ++118 170 40 107 154 36 55 80 19 15 21 5 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++29 42 10 101 146 34 118 171 40 117 169 40 117 169 40 117 169 40 ++117 169 40 117 169 40 117 169 40 117 169 40 118 171 40 113 163 39 ++75 109 26 27 40 9 36 52 12 89 128 30 116 167 40 118 171 40 ++117 169 40 117 169 40 117 169 40 117 169 40 118 170 40 104 150 35 ++16 23 5 0 0 0 0 0 0 53 76 18 118 171 40 117 169 40 ++117 169 40 117 169 40 117 169 40 117 169 40 119 171 41 109 157 37 ++67 96 23 23 34 8 42 61 14 96 138 32 118 170 40 118 170 40 ++117 169 40 117 169 40 117 169 40 117 169 40 117 169 40 117 169 40 ++117 169 40 117 169 40 74 107 25 10 15 3 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 31 45 11 101 146 34 118 170 40 117 169 40 117 169 40 ++117 169 40 117 169 40 117 169 40 117 169 40 117 169 40 117 169 40 ++119 171 41 102 148 35 47 69 16 14 20 5 50 72 17 102 148 35 ++118 171 40 117 169 40 117 169 40 117 169 40 118 170 40 102 148 35 ++15 21 5 0 0 0 0 0 0 50 72 17 118 170 40 117 169 40 ++117 169 40 117 169 40 118 170 40 116 167 40 84 121 28 27 40 9 ++19 27 6 74 107 25 114 165 39 118 171 40 117 169 40 117 169 40 ++117 169 40 117 169 40 117 169 40 117 169 40 117 169 40 117 169 40 ++117 169 40 75 109 26 10 15 4 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 38 55 13 102 148 35 118 171 40 117 169 40 117 169 40 ++117 169 40 117 169 40 117 169 40 117 169 40 117 169 40 117 169 40 ++117 169 40 118 170 40 115 167 39 77 111 26 17 25 6 19 27 6 ++77 111 26 115 166 39 118 170 40 117 169 40 119 172 41 81 118 28 ++3 4 1 0 0 0 0 0 0 27 40 9 111 160 38 118 170 40 ++117 169 40 118 171 40 105 151 36 50 72 17 10 15 3 38 55 13 ++100 144 34 118 171 40 117 169 40 117 169 40 117 169 40 117 169 40 ++117 169 40 117 169 40 117 169 40 117 169 40 117 169 40 117 169 40 ++117 169 40 79 115 27 15 21 5 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 10 15 3 64 92 22 111 160 38 117 169 40 117 169 40 ++117 169 40 117 169 40 117 169 40 117 169 40 117 169 40 117 169 40 ++117 169 40 117 169 40 117 169 40 118 171 40 96 138 32 32 47 11 ++3 4 1 50 72 17 107 154 36 120 173 41 105 151 36 31 45 11 ++0 0 0 0 0 0 0 0 0 3 4 1 65 94 22 117 169 40 ++118 170 40 89 128 30 26 37 9 3 4 1 60 86 20 111 161 38 ++118 171 40 117 169 40 117 169 40 117 169 40 117 169 40 117 169 40 ++117 169 40 117 169 40 117 169 40 117 169 40 117 169 40 117 169 40 ++97 141 33 36 52 12 1 1 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 14 20 5 75 109 26 117 168 40 117 169 40 ++117 169 40 117 169 40 117 169 40 117 169 40 117 169 40 117 169 40 ++117 169 40 117 169 40 117 169 40 117 169 40 118 171 40 107 154 36 ++45 64 15 2 3 1 31 45 11 75 109 26 32 47 11 0 1 0 ++0 0 0 0 0 0 0 0 0 0 0 0 10 15 3 55 80 19 ++65 94 22 11 16 4 11 16 4 75 109 26 116 168 40 118 170 40 ++117 169 40 117 169 40 117 169 40 117 169 40 117 169 40 117 169 40 ++117 169 40 117 169 40 117 169 40 117 169 40 118 170 40 107 154 36 ++47 69 16 3 4 1 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 12 18 4 69 100 23 111 161 38 118 171 40 ++117 169 40 117 169 40 117 169 40 117 169 40 117 169 40 117 169 40 ++117 169 40 117 169 40 117 169 40 117 169 40 117 169 40 118 170 40 ++111 160 38 50 72 17 2 3 1 2 3 1 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 ++1 1 0 12 18 4 81 118 28 118 170 40 117 169 40 117 169 40 ++117 169 40 117 169 40 117 169 40 117 169 40 117 169 40 117 169 40 ++117 169 40 117 169 40 117 169 40 117 170 40 118 171 40 101 146 34 ++42 61 14 2 3 1 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 3 4 1 36 52 12 89 128 30 ++117 169 40 117 169 40 117 169 40 117 169 40 117 169 40 117 169 40 ++117 169 40 117 169 40 117 169 40 117 169 40 117 169 40 117 169 40 ++118 171 41 101 146 34 14 20 5 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 47 69 16 118 170 40 117 169 40 117 169 40 117 169 40 ++117 169 40 117 169 40 117 169 40 117 169 40 117 169 40 117 169 40 ++117 169 40 117 169 40 117 170 40 111 160 38 69 100 23 19 27 6 ++0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 11 16 4 69 100 23 ++115 167 39 119 172 41 117 169 40 117 169 40 117 169 40 117 169 40 ++117 169 40 117 169 40 117 169 40 117 169 40 117 169 40 117 169 40 ++119 172 41 75 109 26 3 4 1 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 23 34 8 106 153 36 118 170 40 117 169 40 117 169 40 ++117 169 40 117 169 40 117 169 40 117 169 40 117 169 40 117 169 40 ++117 169 40 118 170 40 119 172 41 105 151 36 42 61 14 2 3 1 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 15 21 5 ++45 64 15 80 116 27 114 165 39 118 170 40 117 169 40 117 169 40 ++117 169 40 117 169 40 117 169 40 117 169 40 117 169 40 119 172 41 ++97 141 33 20 30 7 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 1 1 0 53 76 18 114 165 39 118 171 40 117 169 40 ++117 169 40 117 169 40 117 169 40 117 169 40 117 169 40 117 169 40 ++118 171 40 104 150 35 64 92 22 31 45 11 10 15 3 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 36 52 12 97 141 33 109 158 37 113 163 39 116 168 40 ++117 169 40 117 170 40 118 170 40 119 172 41 115 167 39 84 121 28 ++23 34 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 3 4 1 50 72 17 102 148 35 118 171 40 ++119 171 41 118 170 40 117 169 40 117 169 40 115 166 39 111 161 38 ++109 157 37 79 115 27 12 18 4 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 3 4 1 15 21 5 23 34 8 45 64 15 106 153 36 ++116 167 40 111 160 38 101 146 34 79 115 27 42 61 14 10 15 3 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 1 1 0 20 30 7 60 86 20 ++89 128 30 106 153 36 113 163 39 117 169 40 84 121 28 29 42 10 ++19 27 6 10 15 3 2 3 1 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 16 23 5 38 55 13 ++36 52 12 26 37 9 12 18 4 2 3 1 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 1 0 0 19 2 7 52 5 18 ++78 7 27 88 8 31 81 7 29 56 5 19 25 2 9 3 0 1 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++3 4 1 19 27 6 31 45 11 38 55 13 32 47 11 3 4 1 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 0 1 ++9 0 3 12 1 4 9 0 3 4 0 1 0 0 0 0 0 0 ++0 0 0 0 0 0 28 3 10 99 9 35 156 14 55 182 16 64 ++189 17 66 190 17 67 189 17 66 184 17 65 166 15 58 118 13 41 ++45 4 16 3 0 1 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 11 1 4 52 5 18 101 9 35 134 12 47 ++151 14 53 154 14 54 151 14 53 113 10 40 11 1 4 0 0 0 ++3 0 1 67 6 24 159 14 56 190 17 67 190 17 67 188 17 66 ++188 17 66 188 17 66 188 17 66 188 17 66 190 17 67 191 17 67 ++174 16 61 101 9 35 14 1 5 0 0 0 35 3 12 108 10 38 ++122 11 43 122 11 43 112 10 39 87 8 30 50 5 17 13 1 5 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++3 0 1 56 5 19 141 13 49 182 16 64 191 17 67 191 17 67 ++190 17 67 190 17 67 191 17 67 113 10 40 3 0 1 1 0 0 ++79 7 28 180 16 63 190 17 67 188 17 66 188 17 66 188 17 66 ++188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 ++189 17 66 188 17 66 122 11 43 11 1 4 41 4 14 176 16 62 ++191 17 67 191 17 67 191 17 67 190 17 67 181 16 63 146 13 51 ++75 7 26 10 1 4 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 1 2 ++90 8 32 178 16 62 191 17 67 188 17 66 188 17 66 188 17 66 ++188 17 66 190 17 67 141 13 49 22 2 8 0 0 0 41 4 14 ++173 16 61 190 17 67 188 17 66 188 17 66 188 17 66 188 17 66 ++188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 ++188 17 66 188 17 66 188 17 66 88 8 31 1 0 0 89 8 31 ++185 17 65 189 17 66 188 17 66 188 17 66 189 17 66 191 17 67 ++186 17 65 124 11 43 25 2 9 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 2 0 1 89 8 31 ++184 17 65 189 17 66 188 17 66 188 17 66 188 17 66 188 17 66 ++190 17 67 151 14 53 34 3 12 0 0 0 0 0 0 79 7 28 ++190 17 67 188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 ++188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 ++188 17 66 188 17 66 191 17 67 146 13 51 9 1 3 7 1 2 ++108 10 38 187 17 66 189 17 66 188 17 66 188 17 66 188 17 66 ++188 17 66 190 17 67 141 13 49 22 2 8 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 52 5 18 176 16 62 ++189 17 66 188 17 66 188 17 66 188 17 66 188 17 66 190 17 67 ++151 14 53 38 3 13 0 0 0 0 0 0 0 0 0 50 5 17 ++180 16 63 189 17 66 188 17 66 188 17 66 188 17 66 188 17 66 ++188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 ++188 17 66 188 17 66 191 17 67 141 13 49 7 1 3 0 0 0 ++11 1 4 112 10 39 187 17 66 189 17 66 188 17 66 188 17 66 ++188 17 66 188 17 66 190 17 67 113 10 40 5 0 2 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 7 1 3 132 12 46 191 17 67 ++188 17 66 188 17 66 188 17 66 188 17 66 190 17 67 146 13 51 ++35 3 12 0 0 0 0 0 0 0 0 0 0 0 0 5 0 2 ++101 9 35 185 17 65 190 17 67 188 17 66 188 17 66 188 17 66 ++188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 ++188 17 66 190 17 67 180 16 63 67 6 24 0 0 0 0 0 0 ++0 0 0 11 1 4 108 10 38 186 17 65 189 17 66 188 17 66 ++188 17 66 188 17 66 189 17 66 180 16 63 56 5 19 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 44 4 15 177 16 62 189 17 66 ++188 17 66 188 17 66 189 17 66 189 17 66 134 12 47 28 3 10 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++8 1 3 79 7 28 159 14 56 188 17 66 191 17 67 190 17 67 ++189 17 66 189 17 66 189 17 66 189 17 66 190 17 67 191 17 67 ++188 17 66 158 14 55 72 7 25 4 0 1 0 0 0 0 0 0 ++0 0 0 0 0 0 8 1 3 95 9 33 182 16 64 189 17 67 ++188 17 66 188 17 66 188 17 66 191 17 67 122 11 43 3 0 1 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 88 8 31 190 17 67 188 17 66 ++188 17 66 189 17 66 185 17 65 113 10 40 18 2 6 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 1 0 0 24 2 8 77 7 27 124 11 43 154 14 54 ++168 15 59 173 16 61 173 16 61 168 15 59 154 14 54 124 11 43 ++77 7 27 22 2 8 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 5 0 2 77 7 27 173 16 61 ++190 17 67 188 17 66 188 17 66 190 17 67 164 15 57 23 2 8 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 1 0 0 118 13 41 191 17 67 188 17 66 ++190 17 67 174 16 61 87 8 30 8 1 3 0 0 0 0 0 0 ++0 0 0 0 0 0 10 1 4 29 3 10 40 4 14 36 3 13 ++18 2 6 2 0 1 0 0 0 0 0 0 3 0 1 14 1 5 ++26 2 9 33 3 11 32 3 11 25 2 9 13 1 5 3 0 1 ++0 0 0 14 1 5 56 5 19 95 9 33 109 10 38 101 9 35 ++77 7 27 35 3 12 5 0 2 0 0 0 1 0 0 56 5 19 ++156 14 55 190 17 67 188 17 66 188 17 66 182 16 64 50 5 17 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 5 0 2 134 12 47 191 17 67 189 17 66 ++151 14 53 52 5 18 2 0 1 0 0 0 0 0 0 1 0 0 ++28 3 10 90 8 32 146 13 51 170 15 60 178 16 62 174 16 61 ++158 14 55 112 10 39 40 4 14 1 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 0 1 ++56 5 19 146 13 51 183 17 64 191 17 67 191 17 67 191 17 67 ++188 17 66 173 16 61 122 11 43 41 4 14 1 0 0 0 0 0 ++30 3 10 124 11 43 185 17 65 190 17 67 187 17 66 67 6 24 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 6 1 2 134 12 47 168 15 59 99 9 35 ++21 2 7 0 0 0 0 0 0 0 0 0 6 1 2 77 7 27 ++162 15 57 190 17 67 191 17 67 189 17 66 189 17 66 189 17 66 ++190 17 67 191 17 67 169 15 59 75 7 26 3 0 1 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 2 0 1 79 7 28 ++178 16 62 191 17 67 188 17 66 188 17 66 188 17 66 188 17 66 ++188 17 66 189 17 66 191 17 67 170 15 60 79 7 28 5 0 2 ++0 0 0 10 1 3 78 7 27 159 14 56 188 17 66 75 7 26 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 1 0 0 35 3 12 29 3 10 2 0 1 ++0 0 0 0 0 0 0 0 0 9 1 3 101 9 35 183 17 64 ++190 17 67 188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 ++188 17 66 188 17 66 190 17 67 178 16 63 67 6 23 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 52 5 18 174 16 61 ++190 17 67 188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 ++188 17 66 188 17 66 188 17 66 190 17 67 182 16 64 89 8 31 ++4 0 1 0 0 0 0 0 0 25 2 9 73 7 26 31 3 11 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 4 0 1 98 9 34 187 17 66 189 17 66 ++188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 ++188 17 66 188 17 66 188 17 66 190 17 67 158 14 55 25 2 9 ++0 0 0 0 0 0 0 0 0 8 1 3 134 12 47 191 17 67 ++188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 ++188 17 66 188 17 66 188 17 66 188 17 66 189 17 66 180 16 63 ++68 6 24 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 6 1 2 19 2 7 3 0 1 0 0 0 0 0 0 ++0 0 0 0 0 0 65 6 23 180 16 63 189 17 66 188 17 66 ++188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 ++188 17 66 188 17 66 188 17 66 188 17 66 189 17 66 83 8 29 ++0 0 0 0 0 0 0 0 0 41 4 14 177 16 62 189 17 66 ++188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 ++188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 190 17 67 ++159 14 56 28 3 10 0 0 0 0 0 0 0 0 0 23 2 8 ++41 4 14 5 0 2 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++23 2 8 113 10 40 159 14 56 65 6 23 0 0 0 0 0 0 ++0 0 0 16 1 6 146 13 51 191 17 67 188 17 66 188 17 66 ++188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 ++188 17 66 188 17 66 188 17 66 188 17 66 191 17 67 132 12 46 ++5 0 2 0 0 0 0 0 0 77 7 27 189 17 66 188 17 66 ++188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 ++188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 ++190 17 67 98 9 34 0 0 0 0 0 0 12 1 4 134 12 47 ++178 16 63 108 10 38 16 1 6 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 30 3 10 ++141 13 49 190 17 67 191 17 67 134 12 47 6 1 2 0 0 0 ++0 0 0 68 6 24 186 17 65 188 17 66 188 17 66 188 17 66 ++188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 ++188 17 66 188 17 66 188 17 66 188 17 66 190 17 67 156 14 55 ++14 1 5 0 0 0 0 0 0 98 9 34 191 17 67 188 17 66 ++188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 ++188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 ++190 17 67 156 14 55 19 2 7 0 0 0 47 4 16 181 16 63 ++190 17 67 189 17 66 126 14 44 17 2 6 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 16 1 6 134 12 47 ++191 17 67 188 17 66 190 17 67 162 15 57 19 2 7 0 0 0 ++3 0 1 123 11 43 191 17 67 188 17 66 188 17 66 188 17 66 ++188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 ++188 17 66 188 17 66 188 17 66 188 17 66 190 17 67 163 15 57 ++20 2 7 0 0 0 0 0 0 101 9 35 191 17 67 188 17 66 ++188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 ++188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 ++188 17 66 182 16 64 52 5 18 0 0 0 73 7 26 188 17 66 ++188 17 66 188 17 66 189 17 66 109 10 38 5 0 2 0 0 0 ++0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 95 9 33 189 17 66 ++188 17 66 188 17 66 189 17 66 171 15 60 29 3 10 0 0 0 ++16 1 6 156 14 55 190 17 67 188 17 66 188 17 66 188 17 66 ++188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 ++188 17 66 188 17 66 188 17 66 188 17 66 190 17 67 158 14 55 ++17 2 6 0 0 0 0 0 0 85 8 30 190 17 67 188 17 66 ++188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 ++188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 ++188 17 66 189 17 66 81 7 29 0 0 0 85 8 30 190 17 67 ++188 17 66 188 17 66 189 17 66 180 16 63 56 5 19 0 0 0 ++0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 25 2 9 162 15 57 190 17 67 ++188 17 66 188 17 66 189 17 66 173 16 61 31 3 11 0 0 0 ++30 3 10 171 15 60 189 17 66 188 17 66 188 17 66 188 17 66 ++188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 ++188 17 66 188 17 66 188 17 66 188 17 66 191 17 67 141 13 49 ++7 1 2 0 0 0 0 0 0 56 5 19 183 17 64 188 17 66 ++188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 ++188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 ++188 17 66 191 17 67 98 9 34 0 0 0 88 8 31 190 17 67 ++188 17 66 188 17 66 188 17 66 191 17 67 124 11 43 5 0 2 ++0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 68 6 24 187 17 66 188 17 66 ++188 17 66 188 17 66 189 17 66 170 15 60 28 3 10 0 0 0 ++34 3 12 174 16 61 189 17 66 188 17 66 188 17 66 188 17 66 ++188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 ++188 17 66 188 17 66 188 17 66 188 17 66 191 17 67 101 9 35 ++0 0 0 0 0 0 0 0 0 21 2 7 159 14 56 190 17 67 ++188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 ++188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 ++188 17 66 191 17 67 98 9 34 0 0 0 81 7 29 189 17 66 ++188 17 66 188 17 66 188 17 66 189 17 66 168 15 59 28 3 10 ++0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 109 10 38 191 17 67 188 17 66 ++188 17 66 188 17 66 190 17 67 163 15 57 21 2 7 0 0 0 ++26 2 9 168 15 59 189 17 66 188 17 66 188 17 66 188 17 66 ++188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 ++188 17 66 188 17 66 188 17 66 189 17 66 180 16 63 47 4 16 ++0 0 0 0 0 0 0 0 0 0 0 0 108 10 38 190 17 67 ++188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 ++188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 ++188 17 66 189 17 66 78 7 27 0 0 0 68 6 24 187 17 66 ++188 17 66 188 17 66 188 17 66 188 17 66 183 17 64 56 5 19 ++0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 3 0 1 131 12 46 191 17 67 188 17 66 ++188 17 66 188 17 66 190 17 67 151 14 53 12 1 4 0 0 0 ++11 1 4 146 13 51 190 17 67 188 17 66 188 17 66 188 17 66 ++188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 ++188 17 66 188 17 66 188 17 66 191 17 67 126 14 44 7 1 2 ++0 0 0 0 0 0 0 0 0 0 0 0 32 3 11 164 15 58 ++190 17 67 188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 ++188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 ++189 17 66 178 16 62 44 4 15 0 0 0 50 5 17 182 16 64 ++188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 72 7 25 ++0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 5 0 2 134 12 47 191 17 67 188 17 66 ++188 17 66 188 17 66 191 17 67 131 12 46 3 0 1 0 0 0 ++0 0 0 101 9 35 190 17 67 188 17 66 188 17 66 188 17 66 ++188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 ++188 17 66 188 17 66 190 17 67 170 15 60 44 4 15 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 77 7 27 ++183 17 64 189 17 66 188 17 66 188 17 66 188 17 66 188 17 66 ++188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 ++191 17 67 134 12 47 9 1 3 0 0 0 31 3 11 171 15 60 ++189 17 66 188 17 66 188 17 66 188 17 66 188 17 66 72 7 25 ++0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 2 0 1 124 11 43 191 17 67 188 17 66 ++188 17 66 188 17 66 191 17 67 101 9 35 0 0 0 0 0 0 ++0 0 0 35 3 12 168 15 59 190 17 67 188 17 66 188 17 66 ++188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 ++188 17 66 189 17 66 182 16 64 77 7 27 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 1 2 ++99 9 35 185 17 65 189 17 66 188 17 66 188 17 66 188 17 66 ++188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 189 17 66 ++177 16 62 56 5 19 0 0 0 0 0 0 13 1 5 151 14 53 ++190 17 67 188 17 66 188 17 66 188 17 66 185 17 65 56 5 19 ++0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 99 9 35 191 17 67 188 17 66 ++188 17 66 188 17 66 186 17 65 65 6 23 0 0 0 0 0 0 ++0 0 0 0 0 0 79 7 28 182 16 64 190 17 67 188 17 66 ++188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 ++191 17 67 177 16 62 83 8 29 4 0 1 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++8 1 3 89 8 31 175 16 62 191 17 67 189 17 66 188 17 66 ++188 17 66 188 17 66 188 17 66 188 17 66 190 17 67 181 16 63 ++85 8 30 3 0 1 0 0 0 0 0 0 1 0 0 118 13 41 ++191 17 67 188 17 66 188 17 66 189 17 66 173 16 61 34 3 12 ++0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 56 5 19 183 17 64 188 17 66 ++188 17 66 189 17 66 169 15 59 30 3 10 0 0 0 0 0 0 ++0 0 0 0 0 0 5 0 2 83 8 29 173 16 61 191 17 67 ++190 17 67 189 17 66 189 17 66 190 17 67 191 17 67 187 17 66 ++151 14 53 56 5 19 3 0 1 0 0 0 16 1 6 50 5 17 ++79 7 28 95 9 33 95 9 33 75 7 26 41 4 14 10 1 4 ++0 0 0 2 0 1 50 5 17 132 12 46 178 16 62 190 17 67 ++191 17 67 191 17 67 191 17 67 186 17 65 154 14 54 68 6 24 ++4 0 1 0 0 0 0 0 0 0 0 0 0 0 0 72 7 25 ++187 17 66 188 17 66 188 17 66 191 17 67 141 13 49 9 1 3 ++0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 14 1 5 151 14 53 190 17 67 ++188 17 66 191 17 67 131 12 46 5 0 2 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 2 0 1 44 4 15 113 10 40 ++156 14 55 173 16 61 174 16 61 164 15 58 134 12 47 77 7 27 ++18 2 6 0 0 0 16 1 6 85 8 30 151 14 53 182 16 64 ++189 17 66 191 17 67 190 17 67 188 17 66 177 16 62 141 13 49 ++68 6 24 8 1 3 0 0 0 8 1 3 44 4 15 88 8 31 ++113 10 40 122 11 43 108 10 38 67 6 24 20 2 7 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 28 3 10 ++166 15 58 190 17 67 188 17 66 187 17 66 79 7 28 0 0 0 ++0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 73 7 26 185 17 65 ++189 17 66 184 17 65 65 6 23 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 1 ++17 2 6 32 3 11 34 3 12 22 2 8 6 1 2 0 0 0 ++0 0 0 38 3 13 141 13 49 188 17 66 190 17 67 188 17 66 ++188 17 66 188 17 66 188 17 66 188 17 66 189 17 66 191 17 67 ++184 17 65 122 11 43 21 2 7 0 0 0 0 0 0 0 0 0 ++0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 ++108 10 38 191 17 67 191 17 67 141 13 49 16 1 6 0 0 0 ++0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 8 1 3 112 10 39 ++186 17 65 124 11 43 10 1 4 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++36 3 13 156 14 55 191 17 67 188 17 66 188 17 66 188 17 66 ++188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 ++189 17 66 190 17 67 134 12 47 18 2 6 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 7 1 2 41 4 14 75 7 26 66 5 23 19 2 7 ++26 2 9 144 13 50 154 14 54 40 4 14 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 13 1 5 ++56 5 19 19 2 7 0 0 0 7 1 2 29 3 10 35 3 12 ++19 2 7 2 0 1 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 13 1 5 ++134 12 47 191 17 67 188 17 66 188 17 66 188 17 66 188 17 66 ++188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 ++188 17 66 188 17 66 189 17 67 108 10 38 3 0 1 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 ++40 4 14 124 11 43 177 16 62 188 17 66 187 17 66 144 13 50 ++24 2 8 17 2 6 22 2 8 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 19 2 7 122 11 43 171 15 60 175 16 62 ++159 14 56 112 10 39 40 4 14 2 0 1 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 72 7 25 ++186 17 65 188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 ++188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 ++188 17 66 188 17 66 189 17 66 174 16 61 41 4 14 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 3 0 1 72 7 25 ++168 15 59 191 17 67 189 17 66 188 17 66 188 17 66 190 17 67 ++95 9 33 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 95 9 33 191 17 67 189 17 66 189 17 66 ++190 17 67 191 17 67 171 15 60 90 8 32 12 1 4 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 5 0 2 132 12 46 ++191 17 67 188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 ++188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 ++188 17 66 188 17 66 188 17 66 190 17 67 98 9 34 0 0 0 ++0 0 0 0 0 0 0 0 0 5 0 2 88 8 31 180 16 63 ++190 17 67 188 17 66 188 17 66 188 17 66 188 17 66 191 17 67 ++146 13 51 11 1 4 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 9 1 3 144 13 50 191 17 67 188 17 66 188 17 66 ++188 17 66 188 17 66 189 17 66 187 17 66 123 11 43 20 2 7 ++0 0 0 0 0 0 0 0 0 0 0 0 21 2 7 163 15 57 ++190 17 67 188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 ++188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 ++188 17 66 188 17 66 188 17 66 191 17 67 134 12 47 5 0 2 ++0 0 0 0 0 0 3 0 1 88 8 31 182 16 64 189 17 66 ++188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 189 17 66 ++171 15 60 31 3 11 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 20 2 7 162 15 57 190 17 67 188 17 66 188 17 66 ++188 17 66 188 17 66 188 17 66 188 17 66 190 17 67 132 12 46 ++20 2 7 0 0 0 0 0 0 0 0 0 32 3 11 173 16 61 ++189 17 66 188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 ++188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 ++188 17 66 188 17 66 188 17 66 190 17 67 151 14 53 12 1 4 ++0 0 0 0 0 0 72 7 25 180 16 63 189 17 66 188 17 66 ++188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 ++181 16 63 47 4 16 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 21 2 7 163 15 57 190 17 67 188 17 66 188 17 66 ++188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 190 17 67 ++122 11 43 9 1 3 0 0 0 0 0 0 30 3 10 171 15 60 ++189 17 66 188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 ++188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 ++188 17 66 188 17 66 188 17 66 190 17 67 146 13 51 10 1 4 ++0 0 0 38 3 13 166 15 58 190 17 67 188 17 66 188 17 66 ++188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 ++183 17 64 52 5 18 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 13 1 5 154 14 54 190 17 67 188 17 66 188 17 66 ++188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 ++186 17 65 79 7 28 0 0 0 0 0 0 14 1 5 156 14 54 ++190 17 67 188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 ++188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 ++188 17 66 188 17 66 188 17 66 191 17 67 124 11 43 2 0 1 ++5 0 2 122 11 43 191 17 67 188 17 66 188 17 66 188 17 66 ++188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 ++182 16 64 47 4 16 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 3 0 1 126 14 44 191 17 67 188 17 66 188 17 66 ++188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 ++190 17 67 158 14 55 23 2 8 0 0 0 1 0 0 113 10 40 ++191 17 67 188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 ++188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 ++188 17 66 188 17 66 188 17 66 188 17 66 78 7 27 0 0 0 ++47 4 16 177 16 62 189 17 66 188 17 66 188 17 66 188 17 66 ++188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 189 17 66 ++173 16 61 34 3 12 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 85 8 30 189 17 66 188 17 66 188 17 66 ++188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 ++188 17 66 188 17 66 79 7 28 0 0 0 0 0 0 47 4 16 ++175 16 62 189 17 66 188 17 66 188 17 66 188 17 66 188 17 66 ++188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 ++188 17 66 188 17 66 190 17 67 156 14 55 22 2 8 0 0 0 ++109 10 38 191 17 67 188 17 66 188 17 66 188 17 66 188 17 66 ++188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 190 17 67 ++151 14 53 13 1 5 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 35 3 12 173 16 61 189 17 66 188 17 66 ++188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 ++188 17 66 191 17 67 134 12 47 7 1 2 0 0 0 3 0 1 ++99 9 35 188 17 66 189 17 66 188 17 66 188 17 66 188 17 66 ++188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 ++188 17 66 189 17 66 181 16 63 68 6 24 0 0 0 18 2 6 ++156 14 55 190 17 67 188 17 66 188 17 66 188 17 66 188 17 66 ++188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 190 17 67 ++101 9 35 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 3 0 1 118 13 41 191 17 67 188 17 66 ++188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 ++188 17 66 189 17 66 168 15 59 28 3 10 0 0 0 0 0 0 ++12 1 4 113 10 40 187 17 66 189 17 67 188 17 66 188 17 66 ++188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 ++190 17 67 180 16 63 88 8 31 4 0 1 0 0 0 47 4 16 ++180 16 63 189 17 66 188 17 66 188 17 66 188 17 66 188 17 66 ++188 17 66 188 17 66 188 17 66 188 17 66 190 17 67 168 15 59 ++36 3 13 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 38 3 13 164 15 58 190 17 67 ++188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 ++188 17 66 188 17 66 182 16 64 50 5 17 0 0 0 0 0 0 ++0 0 0 11 1 4 90 8 32 169 15 59 190 17 67 190 17 67 ++189 17 66 189 17 66 189 17 66 189 17 66 191 17 67 189 17 66 ++158 14 55 68 6 24 4 0 1 0 0 0 0 0 0 73 7 26 ++188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 ++188 17 66 188 17 66 188 17 66 189 17 66 185 17 65 83 8 29 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 65 6 23 174 16 61 ++190 17 67 188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 ++188 17 66 188 17 66 185 17 65 56 5 19 0 0 0 0 0 0 ++0 0 0 0 0 0 2 0 1 35 3 12 99 9 35 146 13 51 ++170 15 60 177 16 62 177 16 62 166 15 58 141 13 49 85 8 30 ++24 2 8 0 0 0 0 0 0 0 0 0 0 0 0 85 8 30 ++190 17 67 188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 ++188 17 66 188 17 66 188 17 66 189 17 66 112 10 39 8 1 3 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 68 6 24 ++170 15 60 191 17 67 188 17 66 188 17 66 188 17 66 188 17 66 ++188 17 66 188 17 66 182 16 64 50 5 17 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 11 1 4 ++28 3 10 40 4 14 38 3 13 25 2 9 8 1 3 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 78 7 27 ++189 17 66 188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 ++188 17 66 189 17 66 187 17 66 113 10 40 14 1 5 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 ++47 4 16 141 13 49 186 17 65 191 17 67 190 17 67 189 17 66 ++189 17 66 191 17 67 156 14 55 20 2 7 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 44 4 15 ++178 16 62 190 17 67 188 17 66 188 17 66 188 17 66 190 17 67 ++191 17 67 173 16 61 90 8 32 10 1 4 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 14 1 5 68 6 24 131 12 46 162 15 57 174 16 61 ++171 15 60 146 13 51 56 5 19 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 3 0 1 14 1 5 29 3 10 ++41 4 14 47 4 16 50 5 17 45 4 16 34 3 12 18 2 6 ++5 0 2 0 0 0 0 0 0 0 0 0 0 0 0 5 0 2 ++90 8 32 169 15 59 185 17 65 187 17 66 182 16 64 163 15 57 ++113 10 40 41 4 14 2 0 1 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 5 0 2 21 2 7 34 3 12 ++29 3 10 11 1 4 0 0 0 0 0 0 0 0 0 0 0 0 ++3 0 1 32 3 11 79 7 28 124 11 43 154 14 54 171 15 60 ++180 16 63 182 16 64 182 16 64 180 16 63 174 16 61 159 14 56 ++132 12 46 88 8 31 34 3 12 3 0 1 0 0 0 0 0 0 ++3 0 1 29 3 10 56 5 19 65 6 23 50 5 17 23 2 8 ++3 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 25 2 9 ++109 10 38 169 15 59 189 17 66 191 17 67 190 17 67 189 17 66 ++189 17 66 188 17 66 188 17 66 188 17 66 189 17 66 190 17 67 ++191 17 67 190 17 67 171 15 60 98 9 34 10 1 3 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 14 1 5 141 13 49 ++191 17 67 189 17 66 188 17 66 188 17 66 188 17 66 188 17 66 ++188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 ++188 17 66 188 17 66 189 17 67 186 17 65 65 6 23 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 23 2 8 166 15 58 ++190 17 67 188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 ++188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 ++188 17 66 188 17 66 189 17 66 176 16 62 45 4 16 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 83 8 29 ++183 17 64 189 17 66 188 17 66 188 17 66 188 17 66 188 17 66 ++188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 ++188 17 66 189 17 66 185 17 65 95 9 33 3 0 1 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 0 2 ++85 8 30 176 16 62 191 17 67 188 17 66 188 17 66 188 17 66 ++188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 188 17 66 ++191 17 67 180 16 63 95 9 33 7 1 3 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++2 0 1 52 5 18 141 13 49 185 17 65 191 17 67 189 17 67 ++189 17 66 188 17 66 188 17 66 189 17 66 191 17 67 187 17 66 ++146 13 51 56 5 19 4 0 1 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 14 1 5 68 6 24 131 12 46 166 15 58 ++180 16 63 183 17 64 180 16 63 168 15 59 134 12 47 75 7 26 ++17 2 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 5 0 2 24 2 8 ++44 4 15 52 5 18 45 4 16 26 2 9 6 1 2 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ++0 0 0 0 0 0 0 0 0 diff -Nru linux-3.2.46/debian/patches/rpi/rpi_104_2669f2ed70b39a30fe5a870b4ca0b04494805d60.patch linux-3.2.46/debian/patches/rpi/rpi_104_2669f2ed70b39a30fe5a870b4ca0b04494805d60.patch --- linux-3.2.46/debian/patches/rpi/rpi_104_2669f2ed70b39a30fe5a870b4ca0b04494805d60.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_104_2669f2ed70b39a30fe5a870b4ca0b04494805d60.patch 2013-07-26 19:32:05.000000000 +0000 @@ -0,0 +1,16384 @@ +commit 2669f2ed70b39a30fe5a870b4ca0b04494805d60 +Author: popcornmix +Date: Tue Jan 17 19:22:19 2012 +0000 + + bcm2708 vchiq driver + + Signed-off-by: popcornmix + +Index: linux-3.2.46/drivers/misc/Kconfig +=================================================================== +--- linux-3.2.46.orig/drivers/misc/Kconfig 2013-05-30 13:35:16.000000000 +0000 ++++ linux-3.2.46/drivers/misc/Kconfig 2013-07-26 19:32:00.000000000 +0000 +@@ -508,5 +508,6 @@ + source "drivers/misc/lis3lv02d/Kconfig" + source "drivers/misc/carma/Kconfig" + source "drivers/misc/altera-stapl/Kconfig" ++source "drivers/misc/vc04_services/Kconfig" + + endif # MISC_DEVICES +Index: linux-3.2.46/drivers/misc/Makefile +=================================================================== +--- linux-3.2.46.orig/drivers/misc/Makefile 2013-05-30 13:35:16.000000000 +0000 ++++ linux-3.2.46/drivers/misc/Makefile 2013-07-26 19:32:00.000000000 +0000 +@@ -48,3 +48,4 @@ + obj-y += carma/ + obj-$(CONFIG_USB_SWITCH_FSA9480) += fsa9480.o + obj-$(CONFIG_ALTERA_STAPL) +=altera-stapl/ ++obj-y += vc04_services/ +Index: linux-3.2.46/drivers/misc/vc04_services/Kconfig +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/Kconfig 2013-07-26 19:32:00.000000000 +0000 +@@ -0,0 +1,7 @@ ++config BCM2708_VCHIQ ++ tristate "Videocore VCHIQ" ++ depends on MACH_BCM2708 ++ default y ++ help ++ Helper for communication for VideoCore. ++ +Index: linux-3.2.46/drivers/misc/vc04_services/Makefile +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/Makefile 2013-07-26 19:32:00.000000000 +0000 +@@ -0,0 +1,19 @@ ++obj-$(CONFIG_BCM2708_VCHIQ) += vchiq.o ++ ++vchiq-objs := \ ++ interface/vchiq_arm/vchiq_core.o \ ++ interface/vchiq_arm/vchiq_arm.o \ ++ interface/vchiq_arm/vchiq_kern_lib.o \ ++ interface/vchiq_arm/vchiq_2835_arm.o \ ++ interface/vcos/linuxkernel/vcos_linuxkernel.o \ ++ interface/vcos/linuxkernel/vcos_thread_map.o \ ++ interface/vcos/linuxkernel/vcos_linuxkernel_cfg.o \ ++ interface/vcos/generic/vcos_generic_event_flags.o \ ++ interface/vcos/generic/vcos_logcat.o \ ++ interface/vcos/generic/vcos_mem_from_malloc.o \ ++ interface/vcos/generic/vcos_cmd.o ++ ++EXTRA_CFLAGS += -DVCOS_VERIFY_BKPTS=1 -Idrivers/misc/vc04_services -Idrivers/misc/vc04_services/interface/vcos/linuxkernel ++ ++ ++ +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vchi/vchi_mh.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vchi/vchi_mh.h 2013-07-26 19:32:00.000000000 +0000 +@@ -0,0 +1,19 @@ ++/*============================================================================= ++Copyright (c) 2010 Broadcom Europe Limited. All rights reserved. ++ ++Project : vchi ++Module : vchi ++ ++FILE DESCRIPTION: ++Definitions for memory handle types. ++=============================================================================*/ ++ ++#ifndef VCHI_MH_H_ ++#define VCHI_MH_H_ ++ ++#include ++ ++typedef int32_t VCHI_MEM_HANDLE_T; ++#define VCHI_MEM_HANDLE_INVALID 0 ++ ++#endif +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq.h 2013-07-26 19:32:00.000000000 +0000 +@@ -0,0 +1,27 @@ ++/* ++ * Copyright (c) 2010-2011 Broadcom. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++#ifndef VCHIQ_VCHIQ_H ++#define VCHIQ_VCHIQ_H ++ ++#include "vchiq_if.h" ++#include "vchiq_util.h" ++#include "interface/vcos/vcos.h" ++ ++#endif ++ +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_2835.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_2835.h 2013-07-26 19:32:00.000000000 +0000 +@@ -0,0 +1,27 @@ ++/* ++ * Copyright (c) 2010-2011 Broadcom Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++#ifndef VCHIQ_2835_H ++#define VCHIQ_2835_H ++ ++#include "vchiq_pagelist.h" ++ ++#define VCHIQ_PLATFORM_FRAGMENTS_OFFSET_IDX 0 ++#define VCHIQ_PLATFORM_FRAGMENTS_COUNT_IDX 1 ++ ++#endif /* VCHIQ_2835_H */ +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_2835_arm.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_2835_arm.c 2013-07-26 19:32:00.000000000 +0000 +@@ -0,0 +1,487 @@ ++/* ++ * Copyright (c) 2010-2011 Broadcom Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#include ++#include ++ ++#define TOTAL_SLOTS (VCHIQ_SLOT_ZERO_SLOTS + 2 * 32) ++ ++#define VCHIQ_DOORBELL_IRQ IRQ_ARM_DOORBELL_0 ++#define VCHIQ_ARM_ADDRESS(x) __virt_to_bus(x) ++ ++#include "vchiq_arm.h" ++#include "vchiq_2835.h" ++ ++#define MAX_FRAGMENTS (VCHIQ_NUM_CURRENT_BULKS * 2) ++ ++#define VCOS_LOG_CATEGORY (&vchiq_arm_log_category) ++ ++static char *g_slot_mem; ++static int g_slot_mem_size; ++dma_addr_t g_slot_phys; ++static FRAGMENTS_T *g_fragments_base; ++static FRAGMENTS_T *g_free_fragments; ++struct semaphore g_free_fragments_sema; ++ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,36) ++static DEFINE_SEMAPHORE(g_free_fragments_mutex); ++#else ++static DECLARE_MUTEX(g_free_fragments_mutex); ++#endif ++ ++static irqreturn_t ++vchiq_doorbell_irq(int irq, void *dev_id); ++ ++static int ++create_pagelist(char __user *buf, size_t count, unsigned short type, ++ struct task_struct *task, PAGELIST_T ** ppagelist); ++ ++static void ++free_pagelist(PAGELIST_T *pagelist, int actual); ++ ++int __init ++vchiq_platform_vcos_init(void) ++{ ++ return (vcos_init() == VCOS_SUCCESS) ? 0 : -EINVAL; ++} ++ ++int __init ++vchiq_platform_init(VCHIQ_STATE_T *state) ++{ ++ VCHIQ_SLOT_ZERO_T *vchiq_slot_zero; ++ int frag_mem_size; ++ int err; ++ int i; ++ ++ /* Allocate space for the channels in coherent memory */ ++ g_slot_mem_size = PAGE_ALIGN(TOTAL_SLOTS * VCHIQ_SLOT_SIZE); ++ frag_mem_size = PAGE_ALIGN(sizeof(FRAGMENTS_T) * MAX_FRAGMENTS); ++ ++ g_slot_mem = dma_alloc_coherent(NULL, g_slot_mem_size + frag_mem_size, ++ &g_slot_phys, GFP_ATOMIC); ++ ++ if (!g_slot_mem) { ++ vcos_log_error("Unable to allocate channel memory"); ++ err = -ENOMEM; ++ goto failed_alloc; ++ } ++ ++ vcos_assert(((int)g_slot_mem & (PAGE_SIZE - 1)) == 0); ++ ++ vchiq_slot_zero = vchiq_init_slots(g_slot_mem, g_slot_mem_size); ++ if (!vchiq_slot_zero) ++ { ++ err = -EINVAL; ++ goto failed_init_slots; ++ } ++ ++ vchiq_slot_zero->platform_data[VCHIQ_PLATFORM_FRAGMENTS_OFFSET_IDX] = (int)g_slot_phys + g_slot_mem_size; ++ vchiq_slot_zero->platform_data[VCHIQ_PLATFORM_FRAGMENTS_COUNT_IDX] = MAX_FRAGMENTS; ++ ++ g_fragments_base = (FRAGMENTS_T *)(g_slot_mem + g_slot_mem_size); ++ g_slot_mem_size += frag_mem_size; ++ ++ g_free_fragments = g_fragments_base; ++ for (i = 0; i < (MAX_FRAGMENTS - 1); i++) { ++ *(FRAGMENTS_T **) & g_fragments_base[i] = ++ &g_fragments_base[i + 1]; ++ } ++ *(FRAGMENTS_T **) & g_fragments_base[i] = NULL; ++ sema_init(&g_free_fragments_sema, MAX_FRAGMENTS); ++ ++ if (vchiq_init_state(state, vchiq_slot_zero, 0/*slave*/) != ++ VCHIQ_SUCCESS) ++ { ++ err = -EINVAL; ++ goto failed_vchiq_init; ++ } ++ ++ err = request_irq(VCHIQ_DOORBELL_IRQ, vchiq_doorbell_irq, ++ IRQF_SAMPLE_RANDOM | IRQF_IRQPOLL, "VCHIQ doorbell", ++ state); ++ if (err < 0) ++ { ++ printk( KERN_ERR "%s: failed to register irq=%d err=%d\n", __func__, ++ VCHIQ_DOORBELL_IRQ, err ); ++ goto failed_request_irq; ++ } ++ ++ /* Send the base address of the slots to VideoCore */ ++ ++ dsb(); /* Ensure all writes have completed */ ++ ++ bcm_mailbox_write(MBOX_CHAN_VCHIQ, (unsigned int)g_slot_phys); ++ ++ vcos_log_info("vchiq_init - done (slots %x, phys %x)", ++ (unsigned int)vchiq_slot_zero, g_slot_phys); ++ ++ return 0; ++ ++failed_request_irq: ++failed_vchiq_init: ++failed_init_slots: ++ dma_free_coherent(NULL, g_slot_mem_size, g_slot_mem, g_slot_phys); ++ ++failed_alloc: ++ return err; ++} ++ ++void __exit ++vchiq_platform_exit(VCHIQ_STATE_T *state) ++{ ++ free_irq(VCHIQ_DOORBELL_IRQ, state); ++ dma_free_coherent(NULL, g_slot_mem_size, ++ g_slot_mem, g_slot_phys); ++} ++ ++void ++remote_event_signal(REMOTE_EVENT_T *event) ++{ ++ event->fired = 1; ++ ++ /* The test on the next line also ensures the write on the previous line ++ has completed */ ++ ++ if (event->armed) { ++ /* trigger vc interrupt */ ++ dsb(); /* data barrier operation */ ++ ++ writel(0, __io_address(ARM_0_BELL2)); ++ } ++} ++ ++int ++vchiq_copy_from_user(void *dst, const void *src, int size) ++{ ++ return copy_from_user(dst, src, size); ++} ++ ++VCHIQ_STATUS_T ++vchiq_prepare_bulk_data(VCHIQ_BULK_T *bulk, VCHI_MEM_HANDLE_T memhandle, ++ void *offset, int size, int dir) ++{ ++ PAGELIST_T *pagelist; ++ int ret; ++ ++ vcos_assert(memhandle == VCHI_MEM_HANDLE_INVALID); ++ ++ ret = create_pagelist((char __user *)offset, size, ++ (dir == VCHIQ_BULK_RECEIVE) ++ ? PAGELIST_READ ++ : PAGELIST_WRITE, ++ current, ++ &pagelist); ++ if (ret != 0) ++ return VCHIQ_ERROR; ++ ++ bulk->handle = memhandle; ++ bulk->data = VCHIQ_ARM_ADDRESS(pagelist); ++ ++ /* Store the pagelist address in remote_data, which isn't used by the ++ slave. */ ++ bulk->remote_data = pagelist; ++ ++ return VCHIQ_SUCCESS; ++} ++ ++void ++vchiq_complete_bulk(VCHIQ_BULK_T *bulk) ++{ ++ free_pagelist((PAGELIST_T *)bulk->remote_data, bulk->actual); ++} ++ ++void ++vchiq_transfer_bulk(VCHIQ_BULK_T *bulk) ++{ ++ /* ++ * This should only be called on the master (VideoCore) side, but ++ * provide an implementation to avoid the need for ifdefery. ++ */ ++ vcos_assert(!"This code should not be called by the ARM on BCM2835"); ++} ++ ++void ++vchiq_dump_platform_state(void *dump_context) ++{ ++ char buf[80]; ++ int len; ++ len = vcos_snprintf(buf, sizeof(buf), ++ " Platform: 2835 (VC master)"); ++ vchiq_dump(dump_context, buf, len + 1); ++} ++ ++void ++vchiq_platform_paused(VCHIQ_STATE_T *state) ++{ ++ vcos_unused(state); ++ vcos_assert_msg(0, "Suspend/resume not supported"); ++} ++ ++void ++vchiq_platform_resumed(VCHIQ_STATE_T *state) ++{ ++ vcos_unused(state); ++ vcos_assert_msg(0, "Suspend/resume not supported"); ++} ++ ++VCHIQ_STATUS_T ++vchiq_use_service(VCHIQ_SERVICE_HANDLE_T handle) ++{ ++ VCHIQ_SERVICE_T *service = (VCHIQ_SERVICE_T *)handle; ++ if (!service) ++ return VCHIQ_ERROR; ++ return VCHIQ_SUCCESS; ++} ++ ++VCHIQ_STATUS_T ++vchiq_release_service(VCHIQ_SERVICE_HANDLE_T handle) ++{ ++ VCHIQ_SERVICE_T *service = (VCHIQ_SERVICE_T *)handle; ++ if (!service) ++ return VCHIQ_ERROR; ++ return VCHIQ_SUCCESS; ++} ++ ++VCHIQ_STATUS_T ++vchiq_check_service(VCHIQ_SERVICE_HANDLE_T handle) ++{ ++ VCHIQ_SERVICE_T *service = (VCHIQ_SERVICE_T *)handle; ++ if (!service) ++ return VCHIQ_ERROR; ++ return VCHIQ_SUCCESS; ++} ++ ++/* ++ * Local functions ++ */ ++ ++static irqreturn_t ++vchiq_doorbell_irq(int irq, void *dev_id) ++{ ++ VCHIQ_STATE_T *state = dev_id; ++ irqreturn_t ret = IRQ_NONE; ++ unsigned int status; ++ ++ /* Read (and clear) the doorbell */ ++ status = readl(__io_address(ARM_0_BELL0)); ++ ++ if (status & 0x4) { /* Was the doorbell rung? */ ++ remote_event_pollall(state); ++ ret = IRQ_HANDLED; ++ } ++ ++ return ret; ++} ++ ++/* There is a potential problem with partial cache lines (pages?) ++ at the ends of the block when reading. If the CPU accessed anything in ++ the same line (page?) then it may have pulled old data into the cache, ++ obscuring the new data underneath. We can solve this by transferring the ++ partial cache lines separately, and allowing the ARM to copy into the ++ cached area. ++ ++ N.B. This implementation plays slightly fast and loose with the Linux ++ driver programming rules, e.g. its use of __virt_to_bus instead of ++ dma_map_single, but it isn't a multi-platform driver and it benefits ++ from increased speed as a result. ++ */ ++ ++static int ++create_pagelist(char __user *buf, size_t count, unsigned short type, ++ struct task_struct *task, PAGELIST_T ** ppagelist) ++{ ++ PAGELIST_T *pagelist; ++ struct page **pages; ++ struct page *page; ++ unsigned long *addrs; ++ unsigned int num_pages, offset, i; ++ char *addr, *base_addr, *next_addr; ++ int run, addridx, actual_pages; ++ ++ offset = (unsigned int)buf & (PAGE_SIZE - 1); ++ num_pages = (count + offset + PAGE_SIZE - 1) / PAGE_SIZE; ++ ++ *ppagelist = NULL; ++ ++ /* Allocate enough storage to hold the page pointers and the page list */ ++ pagelist = (PAGELIST_T *) kmalloc(sizeof(PAGELIST_T) + ++ (num_pages * sizeof(unsigned long)) + ++ (num_pages * sizeof(pages[0])), ++ GFP_KERNEL); ++ ++ vcos_log_trace("create_pagelist - %x", (unsigned int)pagelist); ++ if (!pagelist) ++ return -ENOMEM; ++ ++ addrs = pagelist->addrs; ++ pages = (struct page **)(addrs + num_pages); ++ ++ down_read(&task->mm->mmap_sem); ++ actual_pages = get_user_pages(task, task->mm, ++ (unsigned long)buf & ~(PAGE_SIZE - 1), num_pages, ++ (type == PAGELIST_READ) /*Write */ , 0 /*Force */ , ++ pages, NULL /*vmas */ ); ++ up_read(&task->mm->mmap_sem); ++ ++ if (actual_pages != num_pages) ++ { ++ for (i = 0; i < actual_pages; i++) { ++ page_cache_release(pages[i]); ++ } ++ kfree(pagelist); ++ return -EINVAL; ++ } ++ ++ pagelist->length = count; ++ pagelist->type = type; ++ pagelist->offset = offset; ++ ++ /* Group the pages into runs of contiguous pages */ ++ ++ base_addr = VCHIQ_ARM_ADDRESS(page_address(pages[0])); ++ next_addr = base_addr + PAGE_SIZE; ++ addridx = 0; ++ run = 0; ++ ++ for (i = 1; i < num_pages; i++) { ++ addr = VCHIQ_ARM_ADDRESS(page_address(pages[i])); ++ if ((addr == next_addr) && (run < (PAGE_SIZE - 1))) { ++ next_addr += PAGE_SIZE; ++ run++; ++ } else { ++ addrs[addridx] = (unsigned long)base_addr + run; ++ addridx++; ++ base_addr = addr; ++ next_addr = addr + PAGE_SIZE; ++ run = 0; ++ } ++ } ++ ++ addrs[addridx] = (unsigned long)base_addr + run; ++ addridx++; ++ ++ /* Partial cache lines (fragments) require special measures */ ++ if ((type == PAGELIST_READ) && ++ ((pagelist->offset & (CACHE_LINE_SIZE - 1)) || ++ ((pagelist->offset + pagelist->length) & (CACHE_LINE_SIZE - 1)))) { ++ FRAGMENTS_T *fragments; ++ ++ if (down_interruptible(&g_free_fragments_sema) != 0) { ++ kfree(pagelist); ++ return -EINTR; ++ } ++ ++ vcos_assert(g_free_fragments != NULL); ++ ++ down(&g_free_fragments_mutex); ++ fragments = (FRAGMENTS_T *) g_free_fragments; ++ vcos_assert(fragments != NULL); ++ g_free_fragments = *(FRAGMENTS_T **) g_free_fragments; ++ up(&g_free_fragments_mutex); ++ pagelist->type = ++ PAGELIST_READ_WITH_FRAGMENTS + (fragments - ++ g_fragments_base); ++ } ++ ++ for (page = virt_to_page(pagelist); ++ page <= virt_to_page(addrs + num_pages - 1); page++) { ++ flush_dcache_page(page); ++ } ++ ++ *ppagelist = pagelist; ++ ++ return 0; ++} ++ ++static void ++free_pagelist(PAGELIST_T *pagelist, int actual) ++{ ++ struct page **pages; ++ unsigned int num_pages, i; ++ ++ vcos_log_trace("free_pagelist - %x, %d", (unsigned int)pagelist, actual); ++ ++ num_pages = ++ (pagelist->length + pagelist->offset + PAGE_SIZE - 1) / PAGE_SIZE; ++ ++ pages = (struct page **)(pagelist->addrs + num_pages); ++ ++ /* Deal with any partial cache lines (fragments) */ ++ if (pagelist->type >= PAGELIST_READ_WITH_FRAGMENTS) { ++ FRAGMENTS_T *fragments = ++ g_fragments_base + (pagelist->type - ++ PAGELIST_READ_WITH_FRAGMENTS); ++ int head_bytes, tail_bytes; ++ ++ if (actual >= 0) ++ { ++ if ((head_bytes = (CACHE_LINE_SIZE - pagelist->offset) & (CACHE_LINE_SIZE - 1)) != 0) { ++ if (head_bytes > actual) ++ head_bytes = actual; ++ ++ memcpy((char *)page_address(pages[0]) + ++ pagelist->offset, fragments->headbuf, ++ head_bytes); ++ } ++ if ((head_bytes < actual) && ++ (tail_bytes = ++ (pagelist->offset + actual) & (CACHE_LINE_SIZE - ++ 1)) != 0) { ++ memcpy((char *)page_address(pages[num_pages - 1]) + ++ ((pagelist->offset + actual) & (PAGE_SIZE - ++ 1) & ~(CACHE_LINE_SIZE - 1)), ++ fragments->tailbuf, tail_bytes); ++ } ++ } ++ ++ down(&g_free_fragments_mutex); ++ *(FRAGMENTS_T **) fragments = g_free_fragments; ++ g_free_fragments = fragments; ++ up(&g_free_fragments_mutex); ++ up(&g_free_fragments_sema); ++ } ++ ++ for (i = 0; i < num_pages; i++) { ++ if (pagelist->type != PAGELIST_WRITE) ++ set_page_dirty(pages[i]); ++ page_cache_release(pages[i]); ++ } ++ ++ kfree(pagelist); ++} ++ ++VCHIQ_STATUS_T ++vchiq_platform_suspend(VCHIQ_STATE_T *state) ++{ ++ vcos_unused(state); ++ return VCHIQ_ERROR; ++} +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_arm.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_arm.c 2013-07-26 19:32:00.000000000 +0000 +@@ -0,0 +1,1293 @@ ++/* ++ * Copyright (c) 2010-2011 Broadcom Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "vchiq_core.h" ++#include "vchiq_ioctl.h" ++#include "vchiq_arm.h" ++ ++#define DEVICE_NAME "vchiq" ++ ++/* Override the default prefix, which would be vchiq_arm (from the filename) */ ++#undef MODULE_PARAM_PREFIX ++#define MODULE_PARAM_PREFIX DEVICE_NAME "." ++ ++#define VCHIQ_MINOR 0 ++ ++/* Some per-instance constants */ ++#define MAX_COMPLETIONS 16 ++#define MAX_SERVICES 64 ++#define MAX_ELEMENTS 8 ++#define MSG_QUEUE_SIZE 64 ++ ++#define VCOS_LOG_CATEGORY (&vchiq_arm_log_category) ++ ++typedef struct client_service_struct { ++ VCHIQ_SERVICE_T *service; ++ void *userdata; ++ VCHIQ_INSTANCE_T instance; ++ int handle; ++ int is_vchi; ++ volatile int dequeue_pending; ++ volatile int message_available_pos; ++ volatile int msg_insert; ++ volatile int msg_remove; ++ VCOS_EVENT_T insert_event; ++ VCOS_EVENT_T remove_event; ++ VCHIQ_HEADER_T *msg_queue[MSG_QUEUE_SIZE]; ++} USER_SERVICE_T; ++ ++struct vchiq_instance_struct { ++ VCHIQ_STATE_T *state; ++ VCHIQ_COMPLETION_DATA_T completions[MAX_COMPLETIONS]; ++ volatile int completion_insert; ++ volatile int completion_remove; ++ VCOS_EVENT_T insert_event; ++ VCOS_EVENT_T remove_event; ++ ++ USER_SERVICE_T services[MAX_SERVICES]; ++ ++ int connected; ++ int closing; ++ int pid; ++ int mark; ++}; ++ ++typedef struct dump_context_struct ++{ ++ char __user *buf; ++ size_t actual; ++ size_t space; ++ loff_t offset; ++} DUMP_CONTEXT_T; ++ ++VCOS_LOG_CAT_T vchiq_arm_log_category; ++ ++static struct cdev vchiq_cdev; ++static dev_t vchiq_devid; ++static VCHIQ_STATE_T g_state; ++static struct class *vchiq_class; ++static struct device *vchiq_dev; ++ ++static const char *ioctl_names[] = ++{ ++ "CONNECT", ++ "SHUTDOWN", ++ "CREATE_SERVICE", ++ "REMOVE_SERVICE", ++ "QUEUE_MESSAGE", ++ "QUEUE_BULK_TRANSMIT", ++ "QUEUE_BULK_RECEIVE", ++ "AWAIT_COMPLETION", ++ "DEQUEUE_MESSAGE", ++ "GET_CLIENT_ID", ++ "GET_CONFIG", ++ "CLOSE_SERVICE", ++ "USE_SERVICE", ++ "RELEASE_SERIVCE" ++}; ++ ++VCOS_LOG_LEVEL_T vchiq_default_arm_log_level = VCOS_LOG_WARN; ++ ++/**************************************************************************** ++* ++* find_service_by_handle ++* ++***************************************************************************/ ++ ++static inline USER_SERVICE_T *find_service_by_handle( ++ VCHIQ_INSTANCE_T instance, int handle ) ++{ ++ USER_SERVICE_T *user_service; ++ ++ if (( handle >= 0 ) ++ && ( handle < MAX_SERVICES )) ++ { ++ user_service = &instance->services[ handle ]; ++ ++ if ( user_service->service != NULL ) ++ { ++ return user_service; ++ } ++ } ++ ++ return NULL; ++} ++ ++/**************************************************************************** ++* ++* find_avail_service_handle ++* ++***************************************************************************/ ++ ++static inline USER_SERVICE_T *find_avail_service_handle( ++ VCHIQ_INSTANCE_T instance) ++{ ++ int handle; ++ ++ for ( handle = 0; handle < MAX_SERVICES; handle++ ) ++ { ++ if ( instance->services[handle].service == NULL ) ++ { ++ instance->services[handle].instance = instance; ++ instance->services[handle].handle = handle; ++ ++ return &instance->services[handle]; ++ } ++ } ++ return NULL; ++} ++ ++/**************************************************************************** ++* ++* add_completion ++* ++***************************************************************************/ ++ ++static VCHIQ_STATUS_T ++add_completion(VCHIQ_INSTANCE_T instance, VCHIQ_REASON_T reason, ++ VCHIQ_HEADER_T *header, USER_SERVICE_T *service, void *bulk_userdata) ++{ ++ VCHIQ_COMPLETION_DATA_T *completion; ++ DEBUG_INITIALISE(g_state.local) ++ ++ while (instance->completion_insert == ++ (instance->completion_remove + MAX_COMPLETIONS)) { ++ /* Out of space - wait for the client */ ++ DEBUG_TRACE(SERVICE_CALLBACK_LINE); ++ vcos_log_trace("add_completion - completion queue full"); ++ DEBUG_COUNT(COMPLETION_QUEUE_FULL_COUNT); ++ if (vcos_event_wait(&instance->remove_event) != VCOS_SUCCESS) { ++ vcos_log_info("service_callback interrupted"); ++ return VCHIQ_RETRY; ++ } else if (instance->closing) { ++ vcos_log_info("service_callback closing"); ++ return VCHIQ_ERROR; ++ } ++ DEBUG_TRACE(SERVICE_CALLBACK_LINE); ++ } ++ ++ completion = ++ &instance-> ++ completions[instance->completion_insert & (MAX_COMPLETIONS - 1)]; ++ ++ completion->header = header; ++ completion->reason = reason; ++ completion->service_userdata = service; ++ completion->bulk_userdata = bulk_userdata; ++ ++ /* A write barrier is needed here to ensure that the entire completion ++ record is written out before the insert point. */ ++ vcos_wmb(&completion->bulk_userdata); ++ ++ if (reason == VCHIQ_MESSAGE_AVAILABLE) ++ service->message_available_pos = instance->completion_insert; ++ instance->completion_insert++; ++ ++ vcos_event_signal(&instance->insert_event); ++ ++ return VCHIQ_SUCCESS; ++} ++ ++/**************************************************************************** ++* ++* service_callback ++* ++***************************************************************************/ ++ ++static VCHIQ_STATUS_T ++service_callback(VCHIQ_REASON_T reason, VCHIQ_HEADER_T *header, ++ VCHIQ_SERVICE_HANDLE_T handle, void *bulk_userdata) ++{ ++ /* How do we ensure the callback goes to the right client? ++ The service_user data points to a USER_SERVICE_T record containing the ++ original callback and the user state structure, which contains a circular ++ buffer for completion records. ++ */ ++ USER_SERVICE_T *service = ++ (USER_SERVICE_T *) VCHIQ_GET_SERVICE_USERDATA(handle); ++ VCHIQ_INSTANCE_T instance = service->instance; ++ DEBUG_INITIALISE(g_state.local) ++ ++ DEBUG_TRACE(SERVICE_CALLBACK_LINE); ++ vcos_log_trace ++ ("service_callback - service %lx(%d), reason %d, header %lx, " ++ "instance %lx, bulk_userdata %lx", ++ (unsigned long)service, ((VCHIQ_SERVICE_T *) handle)->localport, ++ reason, (unsigned long)header, ++ (unsigned long)instance, (unsigned long)bulk_userdata); ++ ++ if (!instance || instance->closing) { ++ return VCHIQ_SUCCESS; ++ } ++ ++ if (header && service->is_vchi) ++ { ++ while (service->msg_insert == (service->msg_remove + MSG_QUEUE_SIZE)) ++ { ++ DEBUG_TRACE(SERVICE_CALLBACK_LINE); ++ DEBUG_COUNT(MSG_QUEUE_FULL_COUNT); ++ vcos_log_trace("service_callback - msg queue full"); ++ /* If there is no MESSAGE_AVAILABLE in the completion queue, add one */ ++ if ((service->message_available_pos - instance->completion_remove) < 0) ++ { ++ VCHIQ_STATUS_T status; ++ vcos_log_warn("Inserting extra MESSAGE_AVAILABLE"); ++ DEBUG_TRACE(SERVICE_CALLBACK_LINE); ++ status = add_completion(instance, reason, NULL, service, bulk_userdata); ++ if (status != VCHIQ_SUCCESS) ++ { ++ DEBUG_TRACE(SERVICE_CALLBACK_LINE); ++ return status; ++ } ++ } ++ ++ DEBUG_TRACE(SERVICE_CALLBACK_LINE); ++ if (vcos_event_wait(&service->remove_event) != VCOS_SUCCESS) { ++ vcos_log_info("service_callback interrupted"); ++ DEBUG_TRACE(SERVICE_CALLBACK_LINE); ++ return VCHIQ_RETRY; ++ } else if (instance->closing) { ++ vcos_log_info("service_callback closing"); ++ DEBUG_TRACE(SERVICE_CALLBACK_LINE); ++ return VCHIQ_ERROR; ++ } ++ DEBUG_TRACE(SERVICE_CALLBACK_LINE); ++ } ++ ++ service->msg_queue[service->msg_insert & (MSG_QUEUE_SIZE - 1)] = ++ header; ++ ++ /* A write memory barrier is needed to ensure that the store of header ++ is completed before the insertion point is updated */ ++ vcos_wmb(&service->msg_queue[service->msg_insert & (MSG_QUEUE_SIZE - 1)]); ++ ++ service->msg_insert++; ++ vcos_event_signal(&service->insert_event); ++ ++ /* If there is a thread waiting in DEQUEUE_MESSAGE, or if ++ there is a MESSAGE_AVAILABLE in the completion queue then ++ bypass the completion queue. */ ++ if (((service->message_available_pos - instance->completion_remove) >= 0) || ++ service->dequeue_pending) ++ { ++ DEBUG_TRACE(SERVICE_CALLBACK_LINE); ++ service->dequeue_pending = 0; ++ return VCHIQ_SUCCESS; ++ } ++ ++ header = NULL; ++ } ++ DEBUG_TRACE(SERVICE_CALLBACK_LINE); ++ ++ return add_completion(instance, reason, header, service, bulk_userdata); ++} ++ ++/**************************************************************************** ++* ++* vchiq_ioctl ++* ++***************************************************************************/ ++ ++static long ++vchiq_ioctl(struct file *file, unsigned int cmd, unsigned long arg) ++{ ++ VCHIQ_INSTANCE_T instance = file->private_data; ++ VCHIQ_STATUS_T status = VCHIQ_SUCCESS; ++ long ret = 0; ++ int i, rc; ++ DEBUG_INITIALISE(g_state.local) ++ ++ vcos_log_trace("vchiq_ioctl - instance %x, cmd %s, arg %lx", ++ (unsigned int)instance, ++ ((_IOC_TYPE(cmd) == VCHIQ_IOC_MAGIC) && (_IOC_NR(cmd) <= VCHIQ_IOC_MAX)) ? ++ ioctl_names[_IOC_NR(cmd)] : "", arg); ++ ++ switch (cmd) { ++ case VCHIQ_IOC_SHUTDOWN: ++ if (!instance->connected) ++ break; ++ ++ /* Remove all services */ ++ for (i = 0; i < MAX_SERVICES; i++) { ++ USER_SERVICE_T *service = &instance->services[i]; ++ if (service->service != NULL) { ++ status = vchiq_remove_service(&service->service->base); ++ if (status != VCHIQ_SUCCESS) ++ break; ++ service->service = NULL; ++ } ++ } ++ ++ if (status == VCHIQ_SUCCESS) { ++ /* Wake the completion thread and ask it to exit */ ++ instance->closing = 1; ++ vcos_event_signal(&instance->insert_event); ++ } ++ ++ break; ++ ++ case VCHIQ_IOC_CONNECT: ++ if (instance->connected) { ++ ret = -EINVAL; ++ break; ++ } ++ if ((rc=vcos_mutex_lock(&instance->state->mutex)) != VCOS_SUCCESS) { ++ vcos_log_error("vchiq: connect: could not lock mutex for state %d: %d", ++ instance->state->id, rc); ++ ret = -EINTR; ++ break; ++ } ++ status = vchiq_connect_internal(instance->state, instance); ++ vcos_mutex_unlock(&instance->state->mutex); ++ ++ if (status == VCHIQ_SUCCESS) ++ instance->connected = 1; ++ else ++ vcos_log_error("vchiq: could not connect: %d", status); ++ break; ++ ++ case VCHIQ_IOC_CREATE_SERVICE: ++ { ++ VCHIQ_CREATE_SERVICE_T args; ++ VCHIQ_SERVICE_T *service = NULL; ++ USER_SERVICE_T *user_service = NULL; ++ void *userdata; ++ int srvstate; ++ ++ if (copy_from_user ++ (&args, (const void __user *)arg, ++ sizeof(args)) != 0) { ++ ret = -EFAULT; ++ break; ++ } ++ ++ for (i = 0; i < MAX_SERVICES; i++) { ++ if (instance->services[i].service == NULL) { ++ user_service = &instance->services[i]; ++ break; ++ } ++ } ++ ++ if (!user_service) { ++ ret = -EMFILE; ++ break; ++ } ++ ++ if (args.is_open) { ++ if (instance->connected) ++ srvstate = VCHIQ_SRVSTATE_OPENING; ++ else { ++ ret = -ENOTCONN; ++ break; ++ } ++ } else { ++ srvstate = ++ instance->connected ? ++ VCHIQ_SRVSTATE_LISTENING : ++ VCHIQ_SRVSTATE_HIDDEN; ++ } ++ ++ vcos_mutex_lock(&instance->state->mutex); ++ ++ userdata = args.params.userdata; ++ args.params.callback = service_callback; ++ args.params.userdata = user_service; ++ service = ++ vchiq_add_service_internal(instance->state, ++ &args.params, srvstate, ++ instance); ++ ++ vcos_mutex_unlock(&instance->state->mutex); ++ ++ if (service != NULL) { ++ user_service->service = service; ++ user_service->userdata = userdata; ++ user_service->instance = instance; ++ user_service->handle = i; ++ user_service->is_vchi = args.is_vchi; ++ user_service->dequeue_pending = 0; ++ user_service->message_available_pos = instance->completion_remove - 1; ++ user_service->msg_insert = 0; ++ user_service->msg_remove = 0; ++ vcos_event_create(&user_service->insert_event, "insert_event"); ++ vcos_event_create(&user_service->remove_event, "remove_event"); ++ ++ if (args.is_open) { ++ status = ++ vchiq_open_service_internal ++ (service, instance->pid); ++ if (status != VCHIQ_SUCCESS) { ++ vchiq_remove_service ++ (&service->base); ++ ret = ++ (status == ++ VCHIQ_RETRY) ? -EINTR : ++ -EIO; ++ user_service->service = NULL; ++ user_service->instance = NULL; ++ vcos_event_delete(&user_service->insert_event); ++ vcos_event_delete(&user_service->remove_event); ++ break; ++ } ++ } ++ ++ if (copy_to_user((void __user *) ++ &(((VCHIQ_CREATE_SERVICE_T __user ++ *) arg)->handle), ++ (const void *)&user_service-> ++ handle, ++ sizeof(user_service-> ++ handle)) != 0) ++ ret = -EFAULT; ++ } else { ++ ret = -EEXIST; ++ } ++ } ++ break; ++ ++ case VCHIQ_IOC_CLOSE_SERVICE: ++ { ++ USER_SERVICE_T *user_service; ++ int handle = (int)arg; ++ ++ user_service = find_service_by_handle(instance, handle); ++ if (user_service != NULL) ++ { ++ int is_server = (user_service->service->public_fourcc != VCHIQ_FOURCC_INVALID); ++ ++ status = ++ vchiq_close_service(&user_service->service->base); ++ if ((status == VCHIQ_SUCCESS) && !is_server) ++ { ++ vcos_event_delete(&user_service->insert_event); ++ vcos_event_delete(&user_service->remove_event); ++ user_service->service = NULL; ++ } ++ } else ++ ret = -EINVAL; ++ } ++ break; ++ ++ case VCHIQ_IOC_REMOVE_SERVICE: ++ { ++ USER_SERVICE_T *user_service; ++ int handle = (int)arg; ++ ++ user_service = find_service_by_handle(instance, handle); ++ if (user_service != NULL) ++ { ++ status = ++ vchiq_remove_service(&user_service->service->base); ++ if (status == VCHIQ_SUCCESS) ++ { ++ vcos_event_delete(&user_service->insert_event); ++ vcos_event_delete(&user_service->remove_event); ++ user_service->service = NULL; ++ } ++ } else ++ ret = -EINVAL; ++ } ++ break; ++ ++ case VCHIQ_IOC_USE_SERVICE: ++ case VCHIQ_IOC_RELEASE_SERVICE: ++ { ++ USER_SERVICE_T *user_service; ++ int handle = (int)arg; ++ ++ user_service = find_service_by_handle(instance, handle); ++ if (user_service != NULL) ++ { ++ status = (cmd == VCHIQ_IOC_USE_SERVICE) ? vchiq_use_service(&user_service->service->base) : vchiq_release_service(&user_service->service->base); ++ if (status != VCHIQ_SUCCESS) ++ { ++ ret = -EINVAL; // ??? ++ } ++ } ++ } ++ break; ++ ++ case VCHIQ_IOC_QUEUE_MESSAGE: ++ { ++ VCHIQ_QUEUE_MESSAGE_T args; ++ USER_SERVICE_T *user_service; ++ ++ if (copy_from_user ++ (&args, (const void __user *)arg, ++ sizeof(args)) != 0) { ++ ret = -EFAULT; ++ break; ++ } ++ user_service = find_service_by_handle(instance, args.handle); ++ if ((user_service != NULL) && (args.count <= MAX_ELEMENTS)) ++ { ++ /* Copy elements into kernel space */ ++ VCHIQ_ELEMENT_T elements[MAX_ELEMENTS]; ++ if (copy_from_user ++ (elements, args.elements, ++ args.count * sizeof(VCHIQ_ELEMENT_T)) == 0) ++ status = ++ vchiq_queue_message ++ (&user_service->service->base, ++ elements, args.count); ++ else ++ ret = -EFAULT; ++ } else { ++ ret = -EINVAL; ++ } ++ } ++ break; ++ ++ case VCHIQ_IOC_QUEUE_BULK_TRANSMIT: ++ case VCHIQ_IOC_QUEUE_BULK_RECEIVE: ++ { ++ VCHIQ_QUEUE_BULK_TRANSFER_T args; ++ USER_SERVICE_T *user_service; ++ VCHIQ_BULK_DIR_T dir = ++ (cmd == VCHIQ_IOC_QUEUE_BULK_TRANSMIT) ? ++ VCHIQ_BULK_TRANSMIT : VCHIQ_BULK_RECEIVE; ++ ++ if (copy_from_user ++ (&args, (const void __user *)arg, ++ sizeof(args)) != 0) { ++ ret = -EFAULT; ++ break; ++ } ++ user_service = find_service_by_handle(instance, args.handle); ++ if (user_service != NULL) ++ { ++ status = ++ vchiq_bulk_transfer ++ ((VCHIQ_SERVICE_T *)user_service->service, ++ VCHI_MEM_HANDLE_INVALID, ++ args.data, args.size, ++ args.userdata, args.mode, ++ dir); ++ } else { ++ ret = -EINVAL; ++ } ++ } ++ break; ++ ++ case VCHIQ_IOC_AWAIT_COMPLETION: ++ { ++ VCHIQ_AWAIT_COMPLETION_T args; ++ ++ DEBUG_TRACE(AWAIT_COMPLETION_LINE); ++ if (!instance->connected) { ++ ret = -ENOTCONN; ++ break; ++ } ++ ++ if (copy_from_user ++ (&args, (const void __user *)arg, ++ sizeof(args)) != 0) { ++ ret = -EFAULT; ++ break; ++ } ++ DEBUG_TRACE(AWAIT_COMPLETION_LINE); ++ while ((instance->completion_remove == ++ instance->completion_insert) ++ && !instance->closing) { ++ DEBUG_TRACE(AWAIT_COMPLETION_LINE); ++ if (vcos_event_wait(&instance->insert_event) != ++ VCOS_SUCCESS) { ++ DEBUG_TRACE(AWAIT_COMPLETION_LINE); ++ vcos_log_info ++ ("AWAIT_COMPLETION interrupted"); ++ ret = -EINTR; ++ break; ++ } ++ } ++ DEBUG_TRACE(AWAIT_COMPLETION_LINE); ++ ++ /* A read memory barrier is needed to stop prefetch of a stale ++ completion record */ ++ vcos_rmb(); ++ ++ if (ret == 0) { ++ int msgbufcount = args.msgbufcount; ++ for (ret = 0; ret < args.count; ret++) { ++ VCHIQ_COMPLETION_DATA_T *completion; ++ USER_SERVICE_T *service; ++ VCHIQ_HEADER_T *header; ++ if (instance->completion_remove == ++ instance->completion_insert) ++ break; ++ completion = ++ &instance-> ++ completions ++ [instance->completion_remove & ++ (MAX_COMPLETIONS - 1)]; ++ ++ service = (USER_SERVICE_T *)completion->service_userdata; ++ completion->service_userdata = service->userdata; ++ ++ header = completion->header; ++ if (header) ++ { ++ void __user *msgbuf; ++ int msglen; ++ ++ msglen = header->size + sizeof(VCHIQ_HEADER_T); ++ /* This must be a VCHIQ-style service */ ++ if (args.msgbufsize < msglen) ++ { ++ vcos_log_error("header %x: msgbufsize %x < msglen %x", ++ (unsigned int)header, args.msgbufsize, msglen); ++ vcos_assert(0); ++ if (ret == 0) ++ ret = -EMSGSIZE; ++ break; ++ } ++ if (msgbufcount <= 0) ++ { ++ /* Stall here for lack of a buffer for the message */ ++ break; ++ } ++ /* Get the pointer from user space */ ++ msgbufcount--; ++ if (copy_from_user(&msgbuf, ++ (const void __user *)&args.msgbufs[msgbufcount], ++ sizeof(msgbuf)) != 0) ++ { ++ if (ret == 0) ++ ret = -EFAULT; ++ break; ++ } ++ ++ /* Copy the message to user space */ ++ if (copy_to_user(msgbuf, header, msglen) != 0) ++ { ++ if (ret == 0) ++ ret = -EFAULT; ++ break; ++ } ++ ++ /* Now it has been copied, the message can be released. */ ++ vchiq_release_message(&service->service->base, header); ++ ++ /* The completion must point to the msgbuf */ ++ completion->header = msgbuf; ++ } ++ ++ if (copy_to_user ++ ((void __user *)((size_t) args.buf + ++ ret * ++ sizeof ++ (VCHIQ_COMPLETION_DATA_T)), ++ completion, ++ sizeof(VCHIQ_COMPLETION_DATA_T)) != ++ 0) { ++ if (ret == 0) ++ ret = -EFAULT; ++ break; ++ } ++ instance->completion_remove++; ++ } ++ ++ if (msgbufcount != args.msgbufcount) ++ { ++ if (copy_to_user((void __user *) ++ &((VCHIQ_AWAIT_COMPLETION_T *)arg)->msgbufcount, ++ &msgbufcount, sizeof(msgbufcount)) != 0) ++ { ++ ret = -EFAULT; ++ break; ++ } ++ } ++ } ++ ++ if (ret != 0) ++ vcos_event_signal(&instance->remove_event); ++ DEBUG_TRACE(AWAIT_COMPLETION_LINE); ++ } ++ break; ++ ++ case VCHIQ_IOC_DEQUEUE_MESSAGE: ++ { ++ VCHIQ_DEQUEUE_MESSAGE_T args; ++ USER_SERVICE_T *user_service; ++ VCHIQ_HEADER_T *header; ++ ++ DEBUG_TRACE(DEQUEUE_MESSAGE_LINE); ++ if (copy_from_user ++ (&args, (const void __user *)arg, ++ sizeof(args)) != 0) { ++ ret = -EFAULT; ++ break; ++ } ++ user_service = &instance->services[args.handle]; ++ if ((args.handle < 0) || (args.handle >= MAX_SERVICES) || ++ (user_service->service == NULL) || ++ (user_service->is_vchi == 0)) { ++ ret = -EINVAL; ++ break; ++ } ++ if (user_service->msg_remove == user_service->msg_insert) ++ { ++ if (!args.blocking) ++ { ++ DEBUG_TRACE(DEQUEUE_MESSAGE_LINE); ++ ret = -EWOULDBLOCK; ++ break; ++ } ++ user_service->dequeue_pending = 1; ++ do { ++ DEBUG_TRACE(DEQUEUE_MESSAGE_LINE); ++ if (vcos_event_wait(&user_service->insert_event) != ++ VCOS_SUCCESS) { ++ vcos_log_info("DEQUEUE_MESSAGE interrupted"); ++ ret = -EINTR; ++ break; ++ } ++ } ++ while (user_service->msg_remove == user_service->msg_insert); ++ } ++ ++ /* A read memory barrier is needed to stop prefetch of a stale ++ header value */ ++ vcos_rmb(); ++ ++ header = user_service->msg_queue[user_service->msg_remove & ++ (MSG_QUEUE_SIZE - 1)]; ++ if (header == NULL) ++ ret = -ENOTCONN; ++ else if (header->size <= args.bufsize) ++ { ++ /* Copy to user space if msgbuf is not NULL */ ++ if ((args.buf == NULL) || ++ (copy_to_user((void __user *)args.buf, header->data, ++ header->size) == 0)) ++ { ++ ret = header->size; ++ vchiq_release_message(&user_service->service->base, ++ header); ++ user_service->msg_remove++; ++ vcos_event_signal(&user_service->remove_event); ++ } ++ else ++ ret = -EFAULT; ++ } ++ else ++ { ++ vcos_log_error("header %x: bufsize %x < size %x", ++ (unsigned int)header, args.bufsize, header->size); ++ vcos_assert(0); ++ ret = -EMSGSIZE; ++ } ++ DEBUG_TRACE(DEQUEUE_MESSAGE_LINE); ++ } ++ break; ++ ++ case VCHIQ_IOC_GET_CLIENT_ID: ++ { ++ USER_SERVICE_T *user_service; ++ int handle = (int)arg; ++ ++ user_service = find_service_by_handle(instance, handle); ++ if (user_service != NULL) ++ ret = vchiq_get_client_id(&user_service->service->base); ++ else ++ ret = 0; ++ } ++ break; ++ ++ case VCHIQ_IOC_GET_CONFIG: ++ { ++ VCHIQ_GET_CONFIG_T args; ++ VCHIQ_CONFIG_T config; ++ ++ if (copy_from_user ++ (&args, (const void __user *)arg, ++ sizeof(args)) != 0) { ++ ret = -EFAULT; ++ break; ++ } ++ if (args.config_size > sizeof(config)) ++ { ++ ret = -EINVAL; ++ break; ++ } ++ status = vchiq_get_config(instance, args.config_size, &config); ++ if (status == VCHIQ_SUCCESS) ++ { ++ if (copy_to_user((void __user *)args.pconfig, ++ &config, args.config_size) != 0) ++ { ++ ret = -EFAULT; ++ break; ++ } ++ } ++ } ++ break; ++ ++ case VCHIQ_IOC_SET_SERVICE_OPTION: ++ { ++ VCHIQ_SET_SERVICE_OPTION_T args; ++ USER_SERVICE_T *user_service; ++ ++ if (copy_from_user( ++ &args, (const void __user *)arg, ++ sizeof(args)) != 0) ++ { ++ ret = -EFAULT; ++ break; ++ } ++ ++ user_service = find_service_by_handle(instance, args.handle); ++ if (user_service != NULL) ++ { ++ status = vchiq_set_service_option( ++ &user_service->service->base, ++ args.option, args.value); ++ } ++ else ++ { ++ ret = -EINVAL; ++ } ++ } ++ break; ++ ++ default: ++ ret = -ENOTTY; ++ break; ++ } ++ ++ if (ret == 0) { ++ if (status == VCHIQ_ERROR) ++ ret = -EIO; ++ else if (status == VCHIQ_RETRY) ++ ret = -EINTR; ++ } ++ ++ if ((ret < 0) && (ret != -EINTR) && (ret != -EWOULDBLOCK)) ++ vcos_log_warn(" ioctl instance %lx, cmd %s -> status %d, %ld", ++ (unsigned long)instance, ++ (_IOC_NR(cmd) <= VCHIQ_IOC_MAX) ? ioctl_names[_IOC_NR(cmd)] : ++ "", status, ret); ++ else ++ vcos_log_trace(" ioctl instance %lx, cmd %s -> status %d, %ld", ++ (unsigned long)instance, ++ (_IOC_NR(cmd) <= VCHIQ_IOC_MAX) ? ioctl_names[_IOC_NR(cmd)] : ++ "", status, ret); ++ ++ return ret; ++} ++ ++/**************************************************************************** ++* ++* vchiq_open ++* ++***************************************************************************/ ++ ++static int ++vchiq_open(struct inode *inode, struct file *file) ++{ ++ int dev = iminor(inode) & 0x0f; ++ vcos_log_info("vchiq_open"); ++ switch (dev) { ++ case VCHIQ_MINOR: ++ { ++ VCHIQ_STATE_T *state = vchiq_get_state(); ++ VCHIQ_INSTANCE_T instance; ++ ++ if (!state) ++ { ++ vcos_log_error( "vchiq has no connection to VideoCore"); ++ return -ENOTCONN; ++ } ++ ++ instance = kzalloc(sizeof(*instance), GFP_KERNEL); ++ if (!instance) ++ return -ENOMEM; ++ ++ instance->state = state; ++ instance->pid = current->tgid; ++ vcos_event_create(&instance->insert_event, DEVICE_NAME); ++ vcos_event_create(&instance->remove_event, DEVICE_NAME); ++ ++ file->private_data = instance; ++ } ++ break; ++ ++ default: ++ vcos_log_error("Unknown minor device: %d", dev); ++ return -ENXIO; ++ } ++ ++ return 0; ++} ++ ++/**************************************************************************** ++* ++* vchiq_release ++* ++***************************************************************************/ ++ ++static int ++vchiq_release(struct inode *inode, struct file *file) ++{ ++ int dev = iminor(inode) & 0x0f; ++ int ret = 0; ++ switch (dev) { ++ case VCHIQ_MINOR: ++ { ++ VCHIQ_INSTANCE_T instance = file->private_data; ++ int i; ++ ++ vcos_log_info("vchiq_release: instance=%lx", ++ (unsigned long)instance); ++ ++ instance->closing = 1; ++ ++ /* Wake the slot handler if the completion queue is full */ ++ vcos_event_signal(&instance->remove_event); ++ ++ /* Mark all services for termination... */ ++ ++ for (i = 0; i < MAX_SERVICES; i++) { ++ USER_SERVICE_T *user_service = ++ &instance->services[i]; ++ if (user_service->service != NULL) ++ { ++ /* Wake the slot handler if the msg queue is full */ ++ vcos_event_signal(&user_service->remove_event); ++ ++ if ((user_service->service->srvstate != VCHIQ_SRVSTATE_CLOSEWAIT) && ++ (user_service->service->srvstate != VCHIQ_SRVSTATE_LISTENING)) ++ { ++ vchiq_terminate_service_internal(user_service->service); ++ } ++ } ++ } ++ ++ /* ...and wait for them to die */ ++ ++ for (i = 0; i < MAX_SERVICES; i++) { ++ USER_SERVICE_T *user_service = ++ &instance->services[i]; ++ if (user_service->service != NULL) ++ { ++ /* Wait in this non-portable fashion because interruptible ++ calls will not block in this context. */ ++ while ((user_service->service->srvstate != VCHIQ_SRVSTATE_CLOSEWAIT) && ++ (user_service->service->srvstate != VCHIQ_SRVSTATE_LISTENING)) ++ { ++ down(&user_service->service->remove_event); ++ } ++ ++ vchiq_free_service_internal ++ (user_service->service); ++ } ++ } ++ ++ vcos_event_delete(&instance->insert_event); ++ vcos_event_delete(&instance->remove_event); ++ ++ kfree(instance); ++ file->private_data = NULL; ++ } ++ break; ++ ++ default: ++ vcos_log_error("Unknown minor device: %d", dev); ++ ret = -ENXIO; ++ } ++ ++ return ret; ++} ++ ++/**************************************************************************** ++* ++* vchiq_dump ++* ++***************************************************************************/ ++ ++void ++vchiq_dump(void *dump_context, const char *str, int len) ++{ ++ DUMP_CONTEXT_T *context = (DUMP_CONTEXT_T *)dump_context; ++ ++ if ((context->actual >= 0) && (context->actual < context->space)) ++ { ++ int copy_bytes; ++ if (context->offset > 0) ++ { ++ int skip_bytes = vcos_min(len, context->offset); ++ str += skip_bytes; ++ len -= skip_bytes; ++ context->offset -= skip_bytes; ++ if (context->offset > 0) ++ return; ++ } ++ copy_bytes = vcos_min(len, context->space - context->actual); ++ if (copy_bytes == 0) ++ return; ++ if (copy_to_user(context->buf + context->actual, str, copy_bytes)) ++ context->actual = -EFAULT; ++ context->actual += copy_bytes; ++ len -= copy_bytes; ++ ++ /* If tne terminating NUL is included in the length, then it marks ++ * the end of a line and should be replaced with a carriage return. ++ */ ++ if ((len == 0) && (str[copy_bytes - 1] == '\0')) ++ { ++ char cr = '\n'; ++ if (copy_to_user(context->buf + context->actual - 1, &cr, 1)) ++ { ++ context->actual = -EFAULT; ++ } ++ } ++ } ++} ++ ++/**************************************************************************** ++* ++* vchiq_dump_platform_instance_state ++* ++***************************************************************************/ ++ ++void ++vchiq_dump_platform_instances(void *dump_context) ++{ ++ VCHIQ_STATE_T *state = vchiq_get_state(); ++ char buf[80]; ++ int len; ++ int i; ++ ++ /* There is no list of instances, so instead scan all services, ++ marking those that have been dumped. */ ++ ++ for (i = 0; i < state->unused_service; i++) ++ { ++ VCHIQ_SERVICE_T *service = state->services[i]; ++ VCHIQ_INSTANCE_T instance; ++ ++ if (service ++ && ((instance = service->instance) != NULL) ++ && (service->base.callback == service_callback)) ++ instance->mark = 0; ++ } ++ ++ for (i = 0; i < state->unused_service; i++) ++ { ++ VCHIQ_SERVICE_T *service = state->services[i]; ++ VCHIQ_INSTANCE_T instance; ++ ++ if (service ++ && ((instance = service->instance) != NULL) ++ && (service->base.callback == service_callback)) ++ { ++ if (!instance->mark) ++ { ++ len = vcos_snprintf(buf, sizeof(buf), ++ "Instance %x: pid %d,%s completions %d/%d", ++ (unsigned int)instance, instance->pid, ++ instance->connected ? " connected," : "", ++ instance->completion_insert - instance->completion_remove, ++ MAX_COMPLETIONS); ++ ++ vchiq_dump(dump_context, buf, len + 1); ++ ++ instance->mark = 1; ++ } ++ } ++ } ++} ++ ++/**************************************************************************** ++* ++* vchiq_dump_platform_service_state ++* ++***************************************************************************/ ++ ++void ++vchiq_dump_platform_service_state(void *dump_context, VCHIQ_SERVICE_T *service) ++{ ++ USER_SERVICE_T *user_service = (USER_SERVICE_T *)service->base.userdata; ++ char buf[80]; ++ int len; ++ ++ len = vcos_snprintf(buf, sizeof(buf), " instance %x", ++ service->instance); ++ ++ if ((service->base.callback == service_callback) && user_service->is_vchi) ++ { ++ len += vcos_snprintf(buf + len, sizeof(buf) - len, ++ ", %d/%d messages", ++ user_service->msg_insert - user_service->msg_remove, ++ MSG_QUEUE_SIZE); ++ ++ if (user_service->dequeue_pending) ++ len += vcos_snprintf(buf + len, sizeof(buf) - len, ++ " (dequeue pending)"); ++ } ++ ++ vchiq_dump(dump_context, buf, len + 1); ++} ++ ++/**************************************************************************** ++* ++* vchiq_read ++* ++***************************************************************************/ ++ ++static ssize_t ++vchiq_read(struct file * file, char __user * buf, ++ size_t count, loff_t *ppos) ++{ ++ DUMP_CONTEXT_T context; ++ context.buf = buf; ++ context.actual = 0; ++ context.space = count; ++ context.offset = *ppos; ++ ++ vchiq_dump_state(&context, &g_state); ++ ++ if (context.actual >= 0) ++ *ppos += context.actual; ++ ++ return context.actual; ++} ++ ++VCHIQ_STATE_T * ++vchiq_get_state(void) ++{ ++ ++ if (g_state.remote == NULL) ++ { ++ printk( "%s: g_state.remote == NULL\n", __func__ ); ++ } ++ else ++ { ++ if ( g_state.remote->initialised != 1) ++ { ++ printk( "%s: g_state.remote->initialised != 1 (%d)\n", __func__, g_state.remote->initialised ); ++ } ++ } ++ ++ return ((g_state.remote != NULL) && ++ (g_state.remote->initialised == 1)) ? &g_state : NULL; ++} ++ ++static const struct file_operations ++vchiq_fops = { ++ .owner = THIS_MODULE, ++ .unlocked_ioctl = vchiq_ioctl, ++ .open = vchiq_open, ++ .release = vchiq_release, ++ .read = vchiq_read ++}; ++ ++/**************************************************************************** ++* ++* vchiq_init - called when the module is loaded. ++* ++***************************************************************************/ ++ ++static int __init ++vchiq_init(void) ++{ ++ int err; ++ void *ptr_err; ++ ++ err = vchiq_platform_vcos_init(); ++ if (err != 0) ++ goto failed_platform_vcos_init; ++ ++ vcos_log_set_level(VCOS_LOG_CATEGORY, vchiq_default_arm_log_level); ++ vcos_log_register("vchiq_arm", VCOS_LOG_CATEGORY); ++ ++ if ((err = ++ alloc_chrdev_region(&vchiq_devid, VCHIQ_MINOR, 1, ++ DEVICE_NAME)) != 0) { ++ vcos_log_error("Unable to allocate device number"); ++ goto failed_alloc_chrdev; ++ } ++ cdev_init(&vchiq_cdev, &vchiq_fops); ++ vchiq_cdev.owner = THIS_MODULE; ++ if ((err = cdev_add(&vchiq_cdev, vchiq_devid, 1)) != 0) { ++ vcos_log_error("Unable to register device"); ++ goto failed_cdev_add; ++ } ++ ++ /* create sysfs entries */ ++ vchiq_class = class_create(THIS_MODULE, DEVICE_NAME); ++ if (IS_ERR(ptr_err = vchiq_class)) ++ goto failed_class_create; ++ ++ vchiq_dev = device_create(vchiq_class, NULL, ++ vchiq_devid, NULL, "vchiq"); ++ if (IS_ERR(ptr_err = vchiq_dev)) ++ goto failed_device_create; ++ ++ err = vchiq_platform_init(&g_state); ++ if (err != 0) ++ goto failed_platform_init; ++ ++ vcos_log_error("vchiq: initialised - version %d (min %d), device %d.%d", ++ VCHIQ_VERSION, VCHIQ_VERSION_MIN, ++ MAJOR(vchiq_devid), MINOR(vchiq_devid)); ++ ++ return 0; ++ ++failed_platform_init: ++ device_destroy(vchiq_class, vchiq_devid); ++failed_device_create: ++ class_destroy(vchiq_class); ++failed_class_create: ++ cdev_del(&vchiq_cdev); ++ err = PTR_ERR(ptr_err); ++failed_cdev_add: ++ unregister_chrdev_region(vchiq_devid, 1); ++failed_alloc_chrdev: ++failed_platform_vcos_init: ++ printk(KERN_WARNING "could not load vchiq\n"); ++ return err; ++} ++/**************************************************************************** ++* ++* vchiq_exit - called when the module is unloaded. ++* ++***************************************************************************/ ++ ++static void __exit ++vchiq_exit(void) ++{ ++ vchiq_platform_exit(&g_state); ++ device_destroy(vchiq_class, vchiq_devid); ++ class_destroy(vchiq_class); ++ cdev_del(&vchiq_cdev); ++ unregister_chrdev_region(vchiq_devid, 1); ++ vcos_log_unregister(VCOS_LOG_CATEGORY); ++} ++ ++module_init(vchiq_init); ++module_exit(vchiq_exit); ++MODULE_LICENSE("GPL"); ++MODULE_AUTHOR("Broadcom Corporation"); +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_arm.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_arm.h 2013-07-26 19:32:00.000000000 +0000 +@@ -0,0 +1,38 @@ ++/* ++ * Copyright (c) 2010-2011 Broadcom Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++#ifndef VCHIQ_ARM_H ++#define VCHIQ_ARM_H ++ ++#include "vchiq_core.h" ++ ++extern VCOS_LOG_CAT_T vchiq_arm_log_category; ++ ++extern int __init ++vchiq_platform_vcos_init(void); ++ ++extern int __init ++vchiq_platform_init(VCHIQ_STATE_T *state); ++ ++extern void __exit ++vchiq_platform_exit(VCHIQ_STATE_T *state); ++ ++extern VCHIQ_STATE_T * ++vchiq_get_state(void); ++ ++#endif /* VCHIQ_ARM_H */ +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_cfg.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_cfg.h 2013-07-26 19:32:00.000000000 +0000 +@@ -0,0 +1,43 @@ ++/* ++ * Copyright (c) 2010-2011 Broadcom Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++#ifndef VCHIQ_CFG_H ++#define VCHIQ_CFG_H ++ ++#define VCHIQ_MAGIC VCHIQ_MAKE_FOURCC('V','C','H','I') ++/* The version of VCHIQ - change with any non-trivial change */ ++#define VCHIQ_VERSION 2 ++/* The minimum compatible version - update to match VCHIQ_VERSION with any incompatible change */ ++#define VCHIQ_VERSION_MIN 2 ++ ++#define VCHIQ_MAX_SERVICES 4096 ++#define VCHIQ_MAX_SLOTS 128 ++#define VCHIQ_MAX_SLOTS_PER_SIDE 64 ++ ++#define VCHIQ_NUM_CURRENT_BULKS 32 ++#define VCHIQ_NUM_SERVICE_BULKS 4 ++ ++#ifndef VCHIQ_ENABLE_DEBUG ++#define VCHIQ_ENABLE_DEBUG 1 ++#endif ++ ++#ifndef VCHIQ_ENABLE_STATS ++#define VCHIQ_ENABLE_STATS 1 ++#endif ++ ++#endif /* VCHIQ_CFG_H */ +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_connected.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_connected.c 2013-07-26 19:32:00.000000000 +0000 +@@ -0,0 +1,101 @@ ++/***************************************************************************** ++* Copyright 2001 - 2010 Broadcom Corporation. All rights reserved. ++* ++* Unless you and Broadcom execute a separate written software license ++* agreement governing use of this software, this software is licensed to you ++* under the terms of the GNU General Public License version 2, available at ++* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). ++* ++* Notwithstanding the above, under no circumstances may you combine this ++* software in any way with any other Broadcom software provided under a ++* license other than the GPL, without Broadcom's express prior written ++* consent. ++*****************************************************************************/ ++ ++#include "vcos.h" ++#include "vchiq_connected.h" ++#include ++ ++#define MAX_CALLBACKS 10 ++ ++static int g_connected = 0; ++static int g_num_deferred_callbacks; ++static VCHIQ_CONNECTED_CALLBACK_T g_deferred_callback[ MAX_CALLBACKS ]; ++static VCOS_ONCE_T g_once_init; ++static VCOS_MUTEX_T g_connected_mutex; ++ ++extern VCOS_LOG_CAT_T vchiq_core_log_category; ++#define VCOS_LOG_CATEGORY (&vchiq_core_log_category) ++ ++/**************************************************************************** ++* ++* Function to initialize our lock. ++* ++***************************************************************************/ ++ ++static void connected_init( void ) ++{ ++ vcos_mutex_create( &g_connected_mutex, "connected_mutex"); ++} ++ ++/**************************************************************************** ++* ++* This function is used to defer initialization until the vchiq stack is ++* initialized. If the stack is already initialized, then the callback will ++* be made immediately, otherwise it will be deferred until ++* vchiq_call_connected_callbacks is called. ++* ++***************************************************************************/ ++ ++void vchiq_add_connected_callback( VCHIQ_CONNECTED_CALLBACK_T callback ) ++{ ++ vcos_once( &g_once_init, connected_init ); ++ ++ vcos_mutex_lock( &g_connected_mutex ); ++ ++ if ( g_connected ) ++ { ++ // We're already connected. Call the callback immediately. ++ ++ callback(); ++ } ++ else ++ { ++ if ( g_num_deferred_callbacks >= MAX_CALLBACKS ) ++ { ++ vcos_log_error( "There already %d callback registered - please increase MAX_CALLBACKS", ++ g_num_deferred_callbacks ); ++ } ++ else ++ { ++ g_deferred_callback[ g_num_deferred_callbacks ] = callback; ++ g_num_deferred_callbacks++; ++ } ++ } ++ vcos_mutex_unlock( &g_connected_mutex ); ++} ++ ++/**************************************************************************** ++* ++* This function is called by the vchiq stack once it has been connected to ++* the videocore and clients can start to use the stack. ++* ++***************************************************************************/ ++ ++void vchiq_call_connected_callbacks( void ) ++{ ++ int i; ++ ++ vcos_once( &g_once_init, connected_init ); ++ ++ vcos_mutex_lock( &g_connected_mutex ); ++ for ( i = 0; i < g_num_deferred_callbacks; i++ )\ ++ { ++ g_deferred_callback[i](); ++ } ++ g_num_deferred_callbacks = 0; ++ g_connected = 1; ++ vcos_mutex_unlock( &g_connected_mutex ); ++} ++ ++EXPORT_SYMBOL( vchiq_add_connected_callback ); +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_connected.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_connected.h 2013-07-26 19:32:00.000000000 +0000 +@@ -0,0 +1,32 @@ ++/***************************************************************************** ++* Copyright 2001 - 2010 Broadcom Corporation. All rights reserved. ++* ++* Unless you and Broadcom execute a separate written software license ++* agreement governing use of this software, this software is licensed to you ++* under the terms of the GNU General Public License version 2, available at ++* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). ++* ++* Notwithstanding the above, under no circumstances may you combine this ++* software in any way with any other Broadcom software provided under a ++* license other than the GPL, without Broadcom's express prior written ++* consent. ++*****************************************************************************/ ++ ++#ifndef VCHIQ_CONNECTED_H ++#define VCHIQ_CONNECTED_H ++ ++/* ---- Include Files ----------------------------------------------------- */ ++ ++/* ---- Constants and Types ---------------------------------------------- */ ++ ++typedef void (*VCHIQ_CONNECTED_CALLBACK_T)( void ); ++ ++/* ---- Variable Externs ------------------------------------------------- */ ++ ++/* ---- Function Prototypes ---------------------------------------------- */ ++ ++void vchiq_add_connected_callback( VCHIQ_CONNECTED_CALLBACK_T callback ); ++void vchiq_call_connected_callbacks( void ); ++ ++#endif /* VCHIQ_CONNECTED_H */ ++ +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_core.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_core.c 2013-07-26 19:32:00.000000000 +0000 +@@ -0,0 +1,2604 @@ ++/* ++ * Copyright (c) 2010-2011 Broadcom Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++#include "vchiq_core.h" ++ ++#define VCHIQ_SLOT_HANDLER_STACK 8192 ++ ++#define SLOT_INFO_FROM_INDEX(state, index) (state->slot_info + (index)) ++#define SLOT_DATA_FROM_INDEX(state, index) (state->slot_data + (index)) ++#define SLOT_INDEX_FROM_DATA(state, data) (((unsigned int)((char *)data - (char *)state->slot_data)) / VCHIQ_SLOT_SIZE) ++#define SLOT_INDEX_FROM_INFO(state, info) ((unsigned int)(info - state->slot_info)) ++#define SLOT_QUEUE_INDEX_FROM_POS(pos) ((int)((unsigned int)(pos) / VCHIQ_SLOT_SIZE)) ++ ++#define VCOS_LOG_CATEGORY (&vchiq_core_log_category) ++ ++#define BULK_INDEX(x) (x & (VCHIQ_NUM_SERVICE_BULKS - 1)) ++ ++typedef struct bulk_waiter_struct ++{ ++ VCOS_EVENT_T event; ++ int actual; ++} BULK_WAITER_T; ++ ++typedef struct vchiq_open_payload_struct{ ++ int fourcc; ++ int client_id; ++ short version; ++ short version_min; ++} VCHIQ_OPEN_PAYLOAD_T; ++ ++vcos_static_assert(sizeof(VCHIQ_HEADER_T) == 8); /* we require this for consistency between endpoints */ ++vcos_static_assert(IS_POW2(sizeof(VCHIQ_HEADER_T))); ++vcos_static_assert(IS_POW2(VCHIQ_NUM_CURRENT_BULKS)); ++vcos_static_assert(IS_POW2(VCHIQ_NUM_SERVICE_BULKS)); ++ ++VCOS_LOG_CAT_T vchiq_core_log_category; ++VCOS_LOG_CAT_T vchiq_core_msg_log_category; ++VCOS_LOG_LEVEL_T vchiq_default_core_log_level = VCOS_LOG_WARN; ++VCOS_LOG_LEVEL_T vchiq_default_core_msg_log_level = VCOS_LOG_WARN; ++ ++static const char *const srvstate_names[] = ++{ ++ "FREE", ++ "HIDDEN", ++ "LISTENING", ++ "OPENING", ++ "OPEN", ++ "CLOSESENT", ++ "CLOSING", ++ "CLOSEWAIT" ++}; ++ ++static const char *const reason_names[] = ++{ ++ "SERVICE_OPENED", ++ "SERVICE_CLOSED", ++ "MESSAGE_AVAILABLE", ++ "BULK_TRANSMIT_DONE", ++ "BULK_RECEIVE_DONE", ++ "BULK_TRANSMIT_ABORTED", ++ "BULK_RECEIVE_ABORTED" ++}; ++ ++static const char *const conn_state_names[] = ++{ ++ "DISCONNECTED", ++ "CONNECTED", ++ "PAUSING", ++ "PAUSE_SENT", ++ "PAUSED", ++ "RESUMING" ++}; ++ ++static const char *msg_type_str( unsigned int msg_type ) ++{ ++ switch (msg_type) { ++ case VCHIQ_MSG_PADDING: return "PADDING"; ++ case VCHIQ_MSG_CONNECT: return "CONNECT"; ++ case VCHIQ_MSG_OPEN: return "OPEN"; ++ case VCHIQ_MSG_OPENACK: return "OPENACK"; ++ case VCHIQ_MSG_CLOSE: return "CLOSE"; ++ case VCHIQ_MSG_DATA: return "DATA"; ++ case VCHIQ_MSG_BULK_RX: return "BULK_RX"; ++ case VCHIQ_MSG_BULK_TX: return "BULK_TX"; ++ case VCHIQ_MSG_BULK_RX_DONE: return "BULK_RX_DONE"; ++ case VCHIQ_MSG_BULK_TX_DONE: return "BULK_TX_DONE"; ++ case VCHIQ_MSG_PAUSE: return "PAUSE"; ++ case VCHIQ_MSG_RESUME: return "RESUME"; ++ } ++ return "???"; ++} ++ ++static inline void ++vchiq_set_service_state(VCHIQ_SERVICE_T *service, int newstate) ++{ ++ vcos_log_info("%d: srv:%d %s->%s", service->state->id, service->localport, ++ srvstate_names[service->srvstate], ++ srvstate_names[newstate]); ++ service->srvstate = newstate; ++} ++ ++static inline VCHIQ_STATUS_T ++make_service_callback(VCHIQ_SERVICE_T *service, VCHIQ_REASON_T reason, ++ VCHIQ_HEADER_T *header, void *bulk_userdata) ++{ ++ vcos_log_trace("%d: callback:%d (%s, %x, %x)", service->state->id, ++ service->localport, reason_names[reason], ++ (unsigned int)header, (unsigned int)bulk_userdata); ++ return service->base.callback(reason, header, &service->base, bulk_userdata); ++} ++ ++static inline void ++vchiq_set_conn_state(VCHIQ_STATE_T *state, VCHIQ_CONNSTATE_T newstate) ++{ ++ vcos_log_info("%d: %s->%s", state->id, ++ conn_state_names[state->conn_state], ++ conn_state_names[newstate]); ++ state->conn_state = newstate; ++} ++ ++static inline void ++remote_event_create(REMOTE_EVENT_T *event) ++{ ++ event->armed = 0; ++ /* Don't clear the 'fired' flag because it may already have been set by the other side */ ++ vcos_event_create(event->event, "vchiq"); ++} ++ ++static inline void ++remote_event_destroy(REMOTE_EVENT_T *event) ++{ ++ vcos_event_delete(event->event); ++} ++ ++static inline int ++remote_event_wait(REMOTE_EVENT_T *event) ++{ ++ if (!event->fired) ++ { ++ event->armed = 1; ++ if (event->fired) /* Also ensures the write has completed */ ++ event->armed = 0; ++ else if (vcos_event_wait(event->event) != VCOS_SUCCESS) ++ return 0; ++ } ++ ++ event->fired = 0; ++ return 1; ++} ++ ++static inline void ++remote_event_signal_local(REMOTE_EVENT_T *event) ++{ ++ event->armed = 0; ++ vcos_event_signal(event->event); ++} ++ ++static inline void ++remote_event_poll(REMOTE_EVENT_T *event) ++{ ++ if (event->armed) ++ remote_event_signal_local(event); ++} ++ ++void ++remote_event_pollall(VCHIQ_STATE_T *state) ++{ ++ remote_event_poll(&state->local->trigger); ++ remote_event_poll(&state->local->recycle); ++} ++ ++/* Round up message sizes so that any space at the end of a slot is always big ++ enough for a header. This relies on header size being a power of two, which ++ has been verified earlier by a static assertion. */ ++ ++static inline unsigned int ++calc_stride(unsigned int size) ++{ ++ /* Allow room for the header */ ++ size += sizeof(VCHIQ_HEADER_T); ++ ++ /* Round up */ ++ return (size + sizeof(VCHIQ_HEADER_T) - 1) & ~(sizeof(VCHIQ_HEADER_T) - 1); ++} ++ ++static VCHIQ_SERVICE_T * ++get_listening_service(VCHIQ_STATE_T *state, int fourcc) ++{ ++ int i; ++ ++ vcos_assert(fourcc != VCHIQ_FOURCC_INVALID); ++ ++ for (i = 0; i < state->unused_service; i++) ++ { ++ VCHIQ_SERVICE_T *service = state->services[i]; ++ if (service && ++ (service->public_fourcc == fourcc) && ++ ((service->srvstate == VCHIQ_SRVSTATE_LISTENING) || ++ ((service->srvstate == VCHIQ_SRVSTATE_OPEN) && ++ (service->remoteport == VCHIQ_PORT_FREE)))) ++ return service; ++ } ++ ++ return NULL; ++} ++ ++static VCHIQ_SERVICE_T * ++get_connected_service(VCHIQ_STATE_T *state, unsigned int port) ++{ ++ int i; ++ for (i = 0; i < state->unused_service; i++) { ++ VCHIQ_SERVICE_T *service = state->services[i]; ++ if (service && (service->srvstate == VCHIQ_SRVSTATE_OPEN) ++ && (service->remoteport == port)) { ++ return service; ++ } ++ } ++ return NULL; ++} ++ ++static inline void ++request_poll(VCHIQ_STATE_T *state, VCHIQ_SERVICE_T *service, int poll_type) ++{ ++ if (service) ++ { ++ vcos_atomic_flags_or(&service->poll_flags, (1 << poll_type)); ++ vcos_atomic_flags_or(&state->poll_services[service->localport>>5], ++ (1 <<(service->localport & 0x1f))); ++ } ++ ++ state->poll_needed = 1; ++ vcos_wmb(&state->poll_needed); ++ ++ /* ... and ensure the slot handler runs. */ ++ remote_event_signal_local(&state->local->trigger); ++} ++ ++/* Called from queue_message, by the slot handler and application threads, ++ with slot_mutex held */ ++static VCHIQ_HEADER_T * ++reserve_space(VCHIQ_STATE_T *state, int space, int is_blocking) ++{ ++ VCHIQ_SHARED_STATE_T *local = state->local; ++ int tx_pos = state->local_tx_pos; ++ int slot_space = VCHIQ_SLOT_SIZE - (tx_pos & VCHIQ_SLOT_MASK); ++ ++ if (space > slot_space) { ++ VCHIQ_HEADER_T *header; ++ /* Fill the remaining space with padding */ ++ vcos_assert(state->tx_data != NULL); ++ header = (VCHIQ_HEADER_T *) (state->tx_data + (tx_pos & VCHIQ_SLOT_MASK)); ++ header->msgid = VCHIQ_MSGID_PADDING; ++ header->size = slot_space - sizeof(VCHIQ_HEADER_T); ++ ++ tx_pos += slot_space; ++ } ++ ++ /* If necessary, get the next slot. */ ++ if ((tx_pos & VCHIQ_SLOT_MASK) == 0) ++ { ++ int slot_index; ++ ++ /* If there is no free slot... */ ++ if (tx_pos == (state->slot_queue_available * VCHIQ_SLOT_SIZE)) ++ { ++ /* ...wait for one. */ ++ VCHIQ_STATS_INC(state, slot_stalls); ++ ++ /* But first, flush through the last slot. */ ++ local->tx_pos = tx_pos; ++ remote_event_signal(&state->remote->trigger); ++ ++ do { ++ if (!is_blocking || ++ (vcos_event_wait(&state->slot_available_event) != VCOS_SUCCESS)) ++ { ++ return NULL; /* No space available now */ ++ } ++ } ++ while (tx_pos == (state->slot_queue_available * VCHIQ_SLOT_SIZE)); ++ } ++ ++ slot_index = local->slot_queue[SLOT_QUEUE_INDEX_FROM_POS(tx_pos) & VCHIQ_SLOT_QUEUE_MASK]; ++ state->tx_data = (char *)SLOT_DATA_FROM_INDEX(state, slot_index); ++ } ++ ++ state->local_tx_pos = tx_pos + space; ++ ++ return (VCHIQ_HEADER_T *)(state->tx_data + (tx_pos & VCHIQ_SLOT_MASK)); ++} ++ ++/* Called with slot_mutex held */ ++static void ++process_free_queue(VCHIQ_STATE_T *state) ++{ ++ VCHIQ_SHARED_STATE_T *local = state->local; ++ BITSET_T service_found[BITSET_SIZE(VCHIQ_MAX_SERVICES)]; ++ int slot_queue_available; ++ ++ /* Use a read memory barrier to ensure that any state that may have ++ been modified by another thread is not masked by stale prefetched ++ values. */ ++ vcos_rmb(); ++ ++ /* Find slots which have been freed by the other side, and return them to ++ the available queue. */ ++ slot_queue_available = state->slot_queue_available; ++ ++ while (slot_queue_available != local->slot_queue_recycle) ++ { ++ int pos; ++ int slot_index = local->slot_queue[slot_queue_available++ & VCHIQ_SLOT_QUEUE_MASK]; ++ char *data = (char *)SLOT_DATA_FROM_INDEX(state, slot_index); ++ ++ vcos_log_trace("%d: pfq %d=%x %x %x", state->id, slot_index, ++ (unsigned int)data, local->slot_queue_recycle, ++ slot_queue_available); ++ ++ /* Initialise the bitmask for services which have used this slot */ ++ BITSET_ZERO(service_found); ++ ++ pos = 0; ++ ++ while (pos < VCHIQ_SLOT_SIZE) ++ { ++ VCHIQ_HEADER_T *header = (VCHIQ_HEADER_T *)(data + pos); ++ int msgid = header->msgid; ++ if (VCHIQ_MSG_TYPE(msgid) == VCHIQ_MSG_DATA) ++ { ++ int port = VCHIQ_MSG_SRCPORT(msgid); ++ if (!BITSET_IS_SET(service_found, port)) ++ { ++ VCHIQ_SERVICE_QUOTA_T *service_quota = ++ &state->service_quotas[port]; ++ ++ /* Set the found bit for this service */ ++ BITSET_SET(service_found, port); ++ ++ if (service_quota->slot_use_count > 0) ++ { ++ service_quota->slot_use_count--; ++ /* Signal the service in case it has dropped below its quota */ ++ vcos_event_signal(&service_quota->quota_event); ++ vcos_log_trace("%d: pfq:%d %x@%x - slot_use->%d", ++ state->id, port, ++ header->size, (unsigned int)header, ++ service_quota->slot_use_count); ++ } ++ else ++ { ++ vcos_log_error("service %d slot_use_count=%d (header %x," ++ " msgid %x, header->msgid %x, header->size %x)", ++ port, service_quota->slot_use_count, ++ (unsigned int)header, msgid, header->msgid, ++ header->size); ++ vcos_assert(0); ++ } ++ } ++ } ++ ++ pos += calc_stride(header->size); ++ if (pos > VCHIQ_SLOT_SIZE) ++ { ++ vcos_log_error("pos %x: header %x, msgid %x, header->msgid %x, header->size %x", ++ pos, (unsigned int)header, msgid, header->msgid, header->size); ++ vcos_assert(0); ++ } ++ } ++ } ++ ++ if (slot_queue_available != state->slot_queue_available) ++ { ++ state->slot_queue_available = slot_queue_available; ++ vcos_wmb(&state->slot_queue_available); ++ vcos_event_signal(&state->slot_available_event); ++ } ++} ++ ++/* Called by the slot handler and application threads */ ++static VCHIQ_STATUS_T ++queue_message(VCHIQ_STATE_T *state, VCHIQ_SERVICE_T *service, ++ int msgid, const VCHIQ_ELEMENT_T *elements, ++ int count, int size, int is_blocking) ++{ ++ VCHIQ_SHARED_STATE_T *local; ++ VCHIQ_SERVICE_QUOTA_T *service_quota = NULL; ++ VCHIQ_HEADER_T *header; ++ ++ unsigned int stride; ++ ++ local = state->local; ++ ++ stride = calc_stride(size); ++ ++ vcos_assert(stride <= VCHIQ_SLOT_SIZE); ++ ++ /* On platforms where vcos_mutex_lock cannot fail, the return will never ++ be taken and the compiler may optimise out that code. Let Coverity ++ know this is intentional. ++ */ ++ /* coverity[constant_expression_result] */ ++ if ((VCHIQ_MSG_TYPE(msgid) != VCHIQ_MSG_RESUME) && ++ (vcos_mutex_lock(&state->slot_mutex) != VCOS_SUCCESS)) ++ return VCHIQ_RETRY; ++ ++ if (service) ++ { ++ int tx_end_index = SLOT_QUEUE_INDEX_FROM_POS(state->local_tx_pos + stride - 1); ++ ++ if (service->srvstate != VCHIQ_SRVSTATE_OPEN) ++ { ++ /* The service has been closed, probably while waiting for the mutex */ ++ vcos_mutex_unlock(&state->slot_mutex); ++ return VCHIQ_ERROR; ++ } ++ ++ service_quota = &state->service_quotas[service->localport]; ++ ++ /* ...ensure it doesn't use more than its quota of slots */ ++ while ((tx_end_index != service_quota->previous_tx_index) && ++ (service_quota->slot_use_count == service_quota->slot_quota)) ++ { ++ vcos_log_trace("%d: qm:%d %s,%x - quota stall", ++ state->id, service->localport, ++ msg_type_str(VCHIQ_MSG_TYPE(msgid)), size); ++ VCHIQ_SERVICE_STATS_INC(service, quota_stalls); ++ vcos_mutex_unlock(&state->slot_mutex); ++ if (vcos_event_wait(&service_quota->quota_event) != VCOS_SUCCESS) ++ return VCHIQ_RETRY; ++ if (vcos_mutex_lock(&state->slot_mutex) != VCOS_SUCCESS) ++ return VCHIQ_RETRY; ++ vcos_assert(service_quota->slot_use_count <= service_quota->slot_quota); ++ tx_end_index = SLOT_QUEUE_INDEX_FROM_POS(state->local_tx_pos + stride - 1); ++ } ++ } ++ ++ header = reserve_space(state, stride, is_blocking); ++ ++ if (!header) { ++ if (service) ++ VCHIQ_SERVICE_STATS_INC(service, slot_stalls); ++ vcos_mutex_unlock(&state->slot_mutex); ++ return VCHIQ_RETRY; ++ } ++ ++ if (service) { ++ int i, pos; ++ int tx_end_index; ++ ++ vcos_log_info("%d: qm %s@%x,%x (%d->%d)", state->id, ++ msg_type_str(VCHIQ_MSG_TYPE(msgid)), ++ (unsigned int)header, size, ++ VCHIQ_MSG_SRCPORT(msgid), ++ VCHIQ_MSG_DSTPORT(msgid)); ++ ++ for (i = 0, pos = 0; i < (unsigned int)count; ++ pos += elements[i++].size) ++ if (elements[i].size) { ++ if (vchiq_copy_from_user ++ (header->data + pos, elements[i].data, ++ (size_t) elements[i].size) != ++ VCHIQ_SUCCESS) { ++ vcos_mutex_unlock(&state->slot_mutex); ++ VCHIQ_SERVICE_STATS_INC(service, error_count); ++ return VCHIQ_ERROR; ++ } ++ if (i == 0) { ++ vcos_log_dump_mem( &vchiq_core_msg_log_category, ++ "Sent", 0, header->data + pos, ++ vcos_min( 64, elements[0].size )); ++ } ++ } ++ ++ /* If this transmission can't fit in the last slot used by this service... */ ++ tx_end_index = SLOT_QUEUE_INDEX_FROM_POS(state->local_tx_pos - 1); ++ if (tx_end_index != service_quota->previous_tx_index) ++ { ++ service_quota->slot_use_count++; ++ vcos_log_trace("%d: qm:%d %s,%x - slot_use->%d", ++ state->id, service->localport, ++ msg_type_str(VCHIQ_MSG_TYPE(msgid)), size, ++ service_quota->slot_use_count); ++ } ++ ++ service_quota->previous_tx_index = tx_end_index; ++ VCHIQ_SERVICE_STATS_INC(service, ctrl_tx_count); ++ VCHIQ_SERVICE_STATS_ADD(service, ctrl_tx_bytes, size); ++ } else { ++ vcos_log_info("%d: qm %s@%x,%x (%d->%d)", state->id, ++ msg_type_str(VCHIQ_MSG_TYPE(msgid)), ++ (unsigned int)header, size, ++ VCHIQ_MSG_SRCPORT(msgid), ++ VCHIQ_MSG_DSTPORT(msgid)); ++ if (size != 0) ++ { ++ vcos_assert((count == 1) && (size == elements[0].size)); ++ memcpy(header->data, elements[0].data, elements[0].size); ++ } ++ VCHIQ_STATS_INC(state, ctrl_tx_count); ++ } ++ ++ header->msgid = msgid; ++ header->size = size; ++ ++ if (vcos_is_log_enabled( &vchiq_core_msg_log_category, VCOS_LOG_INFO)) ++ { ++ int svc_fourcc; ++ ++ svc_fourcc = service ++ ? service->base.fourcc ++ : VCHIQ_MAKE_FOURCC('?','?','?','?'); ++ ++ vcos_log_impl( &vchiq_core_msg_log_category, ++ VCOS_LOG_INFO, ++ "Sent Msg %s(%u) to %c%c%c%c s:%u d:%d len:%d", ++ msg_type_str(VCHIQ_MSG_TYPE(msgid)), ++ VCHIQ_MSG_TYPE(msgid), ++ VCHIQ_FOURCC_AS_4CHARS(svc_fourcc), ++ VCHIQ_MSG_SRCPORT(msgid), ++ VCHIQ_MSG_DSTPORT(msgid), ++ size ); ++ } ++ ++ /* Make the new tx_pos visible to the peer. */ ++ local->tx_pos = state->local_tx_pos; ++ vcos_wmb(&local->tx_pos); ++ ++ if (VCHIQ_MSG_TYPE(msgid) != VCHIQ_MSG_PAUSE) ++ vcos_mutex_unlock(&state->slot_mutex); ++ ++ remote_event_signal(&state->remote->trigger); ++ ++ return VCHIQ_SUCCESS; ++} ++ ++static inline void ++claim_slot(VCHIQ_SLOT_INFO_T *slot) ++{ ++ slot->use_count++; ++} ++ ++static void ++release_slot(VCHIQ_STATE_T *state, VCHIQ_SLOT_INFO_T *slot_info) ++{ ++ int release_count; ++ vcos_mutex_lock(&state->recycle_mutex); ++ ++ release_count = slot_info->release_count; ++ slot_info->release_count = ++release_count; ++ ++ if (release_count == slot_info->use_count) ++ { ++ int slot_queue_recycle; ++ /* Add to the freed queue */ ++ ++ /* A read barrier is necessary here to prevent speculative fetches of ++ remote->slot_queue_recycle from overtaking the mutex. */ ++ vcos_rmb(); ++ ++ slot_queue_recycle = state->remote->slot_queue_recycle; ++ state->remote->slot_queue[slot_queue_recycle & VCHIQ_SLOT_QUEUE_MASK] = ++ SLOT_INDEX_FROM_INFO(state, slot_info); ++ state->remote->slot_queue_recycle = slot_queue_recycle + 1; ++ vcos_log_info("%d: release_slot %d - recycle->%x", ++ state->id, SLOT_INDEX_FROM_INFO(state, slot_info), ++ state->remote->slot_queue_recycle); ++ ++ /* A write barrier is necessary, but remote_event_signal contains one. */ ++ remote_event_signal(&state->remote->recycle); ++ } ++ ++ vcos_mutex_unlock(&state->recycle_mutex); ++} ++ ++/* Called by the slot handler - don't hold the bulk mutex */ ++static VCHIQ_STATUS_T ++notify_bulks(VCHIQ_SERVICE_T *service, VCHIQ_BULK_QUEUE_T *queue) ++{ ++ VCHIQ_STATUS_T status = VCHIQ_SUCCESS; ++ ++ vcos_log_trace("%d: nb:%d %cx - p=%x rn=%x r=%x", ++ service->state->id, service->localport, ++ (queue == &service->bulk_tx) ? 't' : 'r', ++ queue->process, queue->remote_notify, queue->remove); ++ ++ if (service->state->is_master) ++ { ++ while (queue->remote_notify != queue->process) ++ { ++ VCHIQ_BULK_T *bulk = &queue->bulks[BULK_INDEX(queue->remote_notify)]; ++ int msgtype = (bulk->dir == VCHIQ_BULK_TRANSMIT) ? ++ VCHIQ_MSG_BULK_RX_DONE : VCHIQ_MSG_BULK_TX_DONE; ++ int msgid = VCHIQ_MAKE_MSG(msgtype, service->localport, service->remoteport); ++ VCHIQ_ELEMENT_T element = { &bulk->actual, 4 }; ++ /* Only reply to non-dummy bulk requests */ ++ if (bulk->remote_data) ++ { ++ status = queue_message(service->state, NULL, msgid, &element, 1, 4, 0); ++ if (status != VCHIQ_SUCCESS) ++ break; ++ } ++ queue->remote_notify++; ++ } ++ } ++ else ++ { ++ queue->remote_notify = queue->process; ++ } ++ ++ if (status == VCHIQ_SUCCESS) ++ { ++ while (queue->remove != queue->remote_notify) ++ { ++ VCHIQ_BULK_T *bulk = &queue->bulks[BULK_INDEX(queue->remove)]; ++ ++ /* Only generate callbacks for non-dummy bulk requests */ ++ if (bulk->data) ++ { ++ if (bulk->actual != VCHIQ_BULK_ACTUAL_ABORTED) ++ { ++ if (bulk->dir == VCHIQ_BULK_TRANSMIT) ++ { ++ VCHIQ_SERVICE_STATS_INC(service, bulk_tx_count); ++ VCHIQ_SERVICE_STATS_ADD(service, bulk_tx_bytes, bulk->actual); ++ } ++ else ++ { ++ VCHIQ_SERVICE_STATS_INC(service, bulk_rx_count); ++ VCHIQ_SERVICE_STATS_ADD(service, bulk_rx_bytes, bulk->actual); ++ } ++ } ++ else ++ { ++ VCHIQ_SERVICE_STATS_INC(service, bulk_aborted_count); ++ } ++ if (bulk->mode == VCHIQ_BULK_MODE_BLOCKING) ++ { ++ BULK_WAITER_T *waiter = (BULK_WAITER_T *)bulk->userdata; ++ if (waiter) ++ { ++ waiter->actual = bulk->actual; ++ vcos_event_signal(&waiter->event); ++ } ++ } ++ else if (bulk->mode == VCHIQ_BULK_MODE_CALLBACK) ++ { ++ VCHIQ_REASON_T reason = (bulk->dir == VCHIQ_BULK_TRANSMIT) ? ++ ((bulk->actual == VCHIQ_BULK_ACTUAL_ABORTED) ? ++ VCHIQ_BULK_TRANSMIT_ABORTED : VCHIQ_BULK_TRANSMIT_DONE) : ++ ((bulk->actual == VCHIQ_BULK_ACTUAL_ABORTED) ? ++ VCHIQ_BULK_RECEIVE_ABORTED : VCHIQ_BULK_RECEIVE_DONE); ++ status = make_service_callback(service, reason, ++ NULL, bulk->userdata); ++ if (status == VCHIQ_RETRY) ++ break; ++ } ++ } ++ ++ queue->remove++; ++ vcos_event_signal(&service->bulk_remove_event); ++ } ++ } ++ ++ if (status != VCHIQ_SUCCESS) ++ request_poll(service->state, service, (queue == &service->bulk_tx) ? ++ VCHIQ_POLL_TXNOTIFY : VCHIQ_POLL_RXNOTIFY); ++ ++ return status; ++} ++ ++/* Called by the slot handler thread */ ++static void ++poll_services(VCHIQ_STATE_T *state) ++{ ++ int group, i; ++ ++ for (group = 0; group < BITSET_SIZE(state->unused_service); group++) ++ { ++ uint32_t flags; ++ flags = vcos_atomic_flags_get_and_clear(&state->poll_services[group]); ++ for (i = 0; flags; i++) ++ { ++ if (flags & (1 << i)) ++ { ++ VCHIQ_SERVICE_T *service = state->services[(group<<5) + i]; ++ uint32_t service_flags = ++ vcos_atomic_flags_get_and_clear(&service->poll_flags); ++ if (service_flags & (1 << VCHIQ_POLL_TERMINATE)) ++ { ++ vcos_log_info("%d: ps - terminate %d<->%d", state->id, service->localport, service->remoteport); ++ if (vchiq_close_service_internal(service, 0/*!close_recvd*/) != VCHIQ_SUCCESS) ++ request_poll(state, service, VCHIQ_POLL_TERMINATE); ++ } ++ if (service_flags & (1 << VCHIQ_POLL_TXNOTIFY)) ++ notify_bulks(service, &service->bulk_tx); ++ if (service_flags & (1 << VCHIQ_POLL_RXNOTIFY)) ++ notify_bulks(service, &service->bulk_rx); ++ flags &= ~(1 << i); ++ } ++ } ++ } ++} ++ ++/* Called by the slot handler or application threads, holding the bulk mutex. */ ++static int ++resolve_bulks(VCHIQ_SERVICE_T *service, VCHIQ_BULK_QUEUE_T *queue) ++{ ++ VCHIQ_STATE_T *state = service->state; ++ int resolved = 0; ++ ++ while ((queue->process != queue->local_insert) && ++ (queue->process != queue->remote_insert)) ++ { ++ VCHIQ_BULK_T *bulk = &queue->bulks[BULK_INDEX(queue->process)]; ++ ++ vcos_log_trace("%d: rb:%d %cx - li=%x ri=%x p=%x", ++ state->id, service->localport, ++ (queue == &service->bulk_tx) ? 't' : 'r', ++ queue->local_insert, queue->remote_insert, ++ queue->process); ++ ++ vcos_assert((int)(queue->local_insert - queue->process) > 0); ++ vcos_assert((int)(queue->remote_insert - queue->process) > 0); ++ vchiq_transfer_bulk(bulk); ++ ++ if (vcos_is_log_enabled( &vchiq_core_msg_log_category, VCOS_LOG_INFO)) ++ { ++ const char *header = (queue == &service->bulk_tx) ? ++ "Send Bulk to" : "Recv Bulk from"; ++ if (bulk->actual != VCHIQ_BULK_ACTUAL_ABORTED) ++ vcos_log_impl( &vchiq_core_msg_log_category, ++ VCOS_LOG_INFO, ++ "%s %c%c%c%c d:%d len:%d %x<->%x", ++ header, ++ VCHIQ_FOURCC_AS_4CHARS(service->base.fourcc), ++ service->remoteport, ++ bulk->size, ++ (unsigned int)bulk->data, ++ (unsigned int)bulk->remote_data ); ++ else ++ vcos_log_impl( &vchiq_core_msg_log_category, ++ VCOS_LOG_INFO, ++ "%s %c%c%c%c d:%d ABORTED - tx len:%d, rx len:%d %x<->%x", ++ header, ++ VCHIQ_FOURCC_AS_4CHARS(service->base.fourcc), ++ service->remoteport, ++ bulk->size, ++ bulk->remote_size, ++ (unsigned int)bulk->data, ++ (unsigned int)bulk->remote_data ); ++ } ++ ++ vchiq_complete_bulk(bulk); ++ queue->process++; ++ resolved++; ++ } ++ return resolved; ++} ++ ++/* Called with the bulk_mutex held */ ++static void ++abort_outstanding_bulks(VCHIQ_SERVICE_T *service, VCHIQ_BULK_QUEUE_T *queue) ++{ ++ int is_tx = (queue == &service->bulk_tx); ++ vcos_log_trace("%d: aob:%d %cx - li=%x ri=%x p=%x", ++ service->state->id, service->localport, is_tx ? 't' : 'r', ++ queue->local_insert, queue->remote_insert, queue->process); ++ ++ vcos_assert((int)(queue->local_insert - queue->process) >= 0); ++ vcos_assert((int)(queue->remote_insert - queue->process) >= 0); ++ ++ while ((queue->process != queue->local_insert) || ++ (queue->process != queue->remote_insert)) ++ { ++ VCHIQ_BULK_T *bulk = &queue->bulks[BULK_INDEX(queue->process)]; ++ ++ if (queue->process == queue->remote_insert) ++ { ++ /* fabricate a matching dummy bulk */ ++ bulk->remote_data = NULL; ++ bulk->remote_size = 0; ++ queue->remote_insert++; ++ } ++ ++ if (queue->process != queue->local_insert) ++ { ++ vchiq_complete_bulk(bulk); ++ ++ if (vcos_is_log_enabled( &vchiq_core_msg_log_category, VCOS_LOG_INFO)) ++ { ++ vcos_log_impl( &vchiq_core_msg_log_category, ++ VCOS_LOG_INFO, ++ "%s %c%c%c%c d:%d ABORTED - tx len:%d, rx len:%d", ++ is_tx ? "Send Bulk to" : "Recv Bulk from", ++ VCHIQ_FOURCC_AS_4CHARS(service->base.fourcc), ++ service->remoteport, ++ bulk->size, ++ bulk->remote_size ); ++ } ++ } ++ else ++ { ++ /* fabricate a matching dummy bulk */ ++ bulk->data = NULL; ++ bulk->size = 0; ++ bulk->actual = VCHIQ_BULK_ACTUAL_ABORTED; ++ bulk->dir = is_tx ? VCHIQ_BULK_TRANSMIT : VCHIQ_BULK_RECEIVE; ++ queue->local_insert++; ++ } ++ ++ queue->process++; ++ } ++} ++ ++static void ++pause_bulks(VCHIQ_STATE_T *state) ++{ ++ int i; ++ ++ /* Block bulk transfers from all services */ ++ for (i = 0; i < state->unused_service; i++) ++ { ++ VCHIQ_SERVICE_T *service = state->services[i]; ++ if (!service || (service->srvstate != VCHIQ_SRVSTATE_OPEN)) ++ continue; ++ ++ vcos_log_trace("locking bulk_mutex for service %d", i); ++ vcos_mutex_lock(&service->bulk_mutex); ++ } ++} ++ ++static void ++resume_bulks(VCHIQ_STATE_T *state) ++{ ++ int i; ++ ++ /* Poll all services in case any bulk transfers have been ++ deferred */ ++ for (i = 0; i < state->unused_service; i++) ++ { ++ VCHIQ_SERVICE_T *service = state->services[i]; ++ if (!service || (service->srvstate != VCHIQ_SRVSTATE_OPEN)) ++ continue; ++ ++ if (resolve_bulks(service, &service->bulk_tx)) ++ request_poll(state, service, VCHIQ_POLL_TXNOTIFY); ++ if (resolve_bulks(service, &service->bulk_rx)) ++ request_poll(state, service, VCHIQ_POLL_RXNOTIFY); ++ vcos_log_trace("unlocking bulk_mutex for service %d", i); ++ vcos_mutex_unlock(&service->bulk_mutex); ++ } ++} ++ ++/* Called by the slot handler thread */ ++static void ++parse_rx_slots(VCHIQ_STATE_T *state) ++{ ++ VCHIQ_SHARED_STATE_T *remote = state->remote; ++ int tx_pos; ++ DEBUG_INITIALISE(state->local) ++ ++ tx_pos = remote->tx_pos; ++ ++ while (state->rx_pos != tx_pos) { ++ VCHIQ_SERVICE_T *service = NULL; ++ VCHIQ_HEADER_T *header; ++ int msgid, size; ++ int type; ++ unsigned int localport, remoteport; ++ ++ DEBUG_TRACE(PARSE_LINE); ++ if (!state->rx_data) ++ { ++ int rx_index; ++ vcos_assert((state->rx_pos & VCHIQ_SLOT_MASK) == 0); ++ rx_index = remote->slot_queue[SLOT_QUEUE_INDEX_FROM_POS(state->rx_pos) & VCHIQ_SLOT_QUEUE_MASK]; ++ state->rx_data = (char *)SLOT_DATA_FROM_INDEX(state, rx_index); ++ state->rx_info = SLOT_INFO_FROM_INDEX(state, rx_index); ++ ++ /* Initialise use_count to one, and increment release_count at the end ++ of the slot to avoid releasing the slot prematurely. */ ++ state->rx_info->use_count = 1; ++ state->rx_info->release_count = 0; ++ } ++ ++ header = (VCHIQ_HEADER_T *)(state->rx_data + (state->rx_pos & VCHIQ_SLOT_MASK)); ++ DEBUG_VALUE(PARSE_HEADER, (int)header); ++ msgid = header->msgid; ++ DEBUG_VALUE(PARSE_MSGID, msgid); ++ size = header->size; ++ type = VCHIQ_MSG_TYPE(msgid); ++ localport = VCHIQ_MSG_DSTPORT(msgid); ++ remoteport = VCHIQ_MSG_SRCPORT(msgid); ++ ++ if (type != VCHIQ_MSG_DATA) ++ { ++ VCHIQ_STATS_INC(state, ctrl_rx_count); ++ } ++ ++ switch (type) ++ { ++ case VCHIQ_MSG_OPENACK: ++ case VCHIQ_MSG_CLOSE: ++ case VCHIQ_MSG_DATA: ++ case VCHIQ_MSG_BULK_RX: ++ case VCHIQ_MSG_BULK_TX: ++ case VCHIQ_MSG_BULK_RX_DONE: ++ case VCHIQ_MSG_BULK_TX_DONE: ++ if (localport <= VCHIQ_PORT_MAX) ++ { ++ service = state->services[localport]; ++ if (service && (service->srvstate == VCHIQ_SRVSTATE_FREE)) ++ service = NULL; ++ } ++ if (!service) ++ { ++ vcos_log_error( ++ "%d: prs %s@%x (%d->%d) - invalid/closed service %d", ++ state->id, msg_type_str(type), (unsigned int)header, ++ remoteport, localport, localport); ++ goto skip_message; ++ } ++ default: ++ break; ++ } ++ ++ if ( vcos_is_log_enabled( &vchiq_core_msg_log_category, VCOS_LOG_INFO)) ++ { ++ int svc_fourcc; ++ ++ svc_fourcc = service ++ ? service->base.fourcc ++ : VCHIQ_MAKE_FOURCC('?','?','?','?'); ++ vcos_log_impl( &vchiq_core_msg_log_category, ++ VCOS_LOG_INFO, ++ "Rcvd Msg %s(%u) from %c%c%c%c s:%d d:%d len:%d", ++ msg_type_str(type), type, ++ VCHIQ_FOURCC_AS_4CHARS(svc_fourcc), ++ remoteport, localport, size ); ++ if (size > 0) { ++ vcos_log_dump_mem( &vchiq_core_msg_log_category, ++ "Rcvd", 0, header->data, ++ vcos_min( 64, size )); ++ } ++ } ++ ++ if (((unsigned int)header & VCHIQ_SLOT_MASK) + calc_stride(size) > VCHIQ_SLOT_SIZE) ++ { ++ vcos_log_error("header %x (msgid %x) - size %x too big for slot", ++ (unsigned int)header, (unsigned int)msgid, (unsigned int)size); ++ vcos_assert(0); ++ } ++ ++ switch (type) { ++ case VCHIQ_MSG_OPEN: ++ vcos_assert(VCHIQ_MSG_DSTPORT(msgid) == 0); ++ if (vcos_verify(size == sizeof(VCHIQ_OPEN_PAYLOAD_T))) { ++ const VCHIQ_OPEN_PAYLOAD_T *payload = (VCHIQ_OPEN_PAYLOAD_T *)header->data; ++ unsigned int fourcc; ++ ++ fourcc = payload->fourcc; ++ vcos_log_info("%d: prs OPEN@%x (%d->'%c%c%c%c')", ++ state->id, (unsigned int)header, ++ localport, ++ VCHIQ_FOURCC_AS_4CHARS(fourcc)); ++ ++ service = get_listening_service(state, fourcc); ++ ++ if (service) ++ { ++ /* A matching service exists */ ++ short version = payload->version; ++ short version_min = payload->version_min; ++ if ((service->version < version_min) || ++ (version < service->version_min)) ++ { ++ /* Version mismatch */ ++ vcos_log_error("%d: service %d (%c%c%c%c) version mismatch -" ++ " local (%d, min %d) vs. remote (%d, min %d)", ++ state->id, service->localport, ++ VCHIQ_FOURCC_AS_4CHARS(fourcc), ++ service->version, service->version_min, ++ version, version_min); ++ goto fail_open; ++ } ++ if (service->srvstate == VCHIQ_SRVSTATE_LISTENING) ++ { ++ /* Acknowledge the OPEN */ ++ if (queue_message(state, NULL, ++ VCHIQ_MAKE_MSG(VCHIQ_MSG_OPENACK, service->localport, remoteport), ++ NULL, 0, 0, 0) == VCHIQ_RETRY) ++ return; /* Bail out if not ready */ ++ ++ /* The service is now open */ ++ vchiq_set_service_state(service, VCHIQ_SRVSTATE_OPEN); ++ } ++ ++ service->remoteport = remoteport; ++ service->client_id = ((int *)header->data)[1]; ++ if (make_service_callback(service, VCHIQ_SERVICE_OPENED, ++ NULL, NULL) == VCHIQ_RETRY) ++ { ++ /* Bail out if not ready */ ++ service->remoteport = VCHIQ_PORT_FREE; ++ return; ++ } ++ ++ /* Break out, and skip the failure handling */ ++ break; ++ } ++ } ++ fail_open: ++ /* No available service, or an invalid request - send a CLOSE */ ++ if (queue_message(state, NULL, ++ VCHIQ_MAKE_MSG(VCHIQ_MSG_CLOSE, 0, VCHIQ_MSG_SRCPORT(msgid)), ++ NULL, 0, 0, 0) == VCHIQ_RETRY) ++ return; /* Bail out if not ready */ ++ break; ++ case VCHIQ_MSG_OPENACK: ++ { ++ vcos_log_info("%d: prs OPENACK@%x (%d->%d)", ++ state->id, (unsigned int)header, ++ remoteport, localport); ++ if (service->srvstate == VCHIQ_SRVSTATE_OPENING) { ++ service->remoteport = remoteport; ++ vchiq_set_service_state(service, ++ VCHIQ_SRVSTATE_OPEN); ++ vcos_event_signal(&service->remove_event); ++ } ++ } ++ break; ++ case VCHIQ_MSG_CLOSE: ++ { ++ vcos_assert(size == 0); /* There should be no data */ ++ ++ vcos_log_info("%d: prs CLOSE@%x (%d->%d)", ++ state->id, (unsigned int)header, ++ remoteport, localport); ++ ++ if ((service->remoteport != remoteport) && ++ VCHIQ_PORT_IS_VALID(service->remoteport)) { ++ /* This could be from a client which hadn't yet received ++ the OPENACK - look for the connected service */ ++ service = get_connected_service(state, remoteport); ++ if (!service) ++ break; ++ } ++ ++ if (vchiq_close_service_internal(service, ++ 1/*close_recvd*/) == VCHIQ_RETRY) ++ return; /* Bail out if not ready */ ++ ++ if (vcos_is_log_enabled( &vchiq_core_msg_log_category, VCOS_LOG_INFO)) ++ { ++ vcos_log_impl( &vchiq_core_msg_log_category, ++ VCOS_LOG_INFO, ++ "Close Service %c%c%c%c s:%u d:%d", ++ VCHIQ_FOURCC_AS_4CHARS(service->base.fourcc), ++ service->localport, ++ service->remoteport ); ++ } ++ } ++ break; ++ case VCHIQ_MSG_DATA: ++ { ++ vcos_log_trace("%d: prs DATA@%x,%x (%d->%d)", ++ state->id, (unsigned int)header, size, ++ remoteport, localport); ++ ++ if ((service->remoteport == remoteport) ++ && (service->srvstate == ++ VCHIQ_SRVSTATE_OPEN)) { ++ header->msgid = msgid | VCHIQ_MSGID_CLAIMED; ++ claim_slot(state->rx_info); ++ DEBUG_TRACE(PARSE_LINE); ++ if (make_service_callback(service, ++ VCHIQ_MESSAGE_AVAILABLE, header, ++ NULL) == VCHIQ_RETRY) ++ { ++ DEBUG_TRACE(PARSE_LINE); ++ return; /* Bail out if not ready */ ++ } ++ VCHIQ_SERVICE_STATS_INC(service, ctrl_rx_count); ++ VCHIQ_SERVICE_STATS_ADD(service, ctrl_rx_bytes, size); ++ } ++ else ++ { ++ VCHIQ_STATS_INC(state, error_count); ++ } ++ } ++ break; ++ case VCHIQ_MSG_CONNECT: ++ vcos_log_info("%d: prs CONNECT@%x", ++ state->id, (unsigned int)header); ++ vcos_event_signal(&state->connect); ++ break; ++ case VCHIQ_MSG_BULK_RX: ++ case VCHIQ_MSG_BULK_TX: ++ { ++ VCHIQ_BULK_QUEUE_T *queue; ++ vcos_assert(state->is_master); ++ queue = (type == VCHIQ_MSG_BULK_RX) ? ++ &service->bulk_tx : &service->bulk_rx; ++ if ((service->remoteport == remoteport) ++ && (service->srvstate == ++ VCHIQ_SRVSTATE_OPEN)) ++ { ++ VCHIQ_BULK_T *bulk; ++ int resolved; ++ ++ vcos_assert(queue->remote_insert < queue->remove + ++ VCHIQ_NUM_SERVICE_BULKS); ++ bulk = &queue->bulks[BULK_INDEX(queue->remote_insert)]; ++ bulk->remote_data = (void *)((int *)header->data)[0]; ++ bulk->remote_size = ((int *)header->data)[1]; ++ ++ vcos_log_info("%d: prs %s@%x (%d->%d) %x@%x", ++ state->id, msg_type_str(type), ++ (unsigned int)header, ++ remoteport, localport, ++ bulk->remote_size, ++ (unsigned int)bulk->remote_data); ++ ++ queue->remote_insert++; ++ ++ if (state->conn_state != VCHIQ_CONNSTATE_CONNECTED) ++ break; ++ ++ DEBUG_TRACE(PARSE_LINE); ++ if (vcos_mutex_lock(&service->bulk_mutex) != VCOS_SUCCESS) ++ { ++ DEBUG_TRACE(PARSE_LINE); ++ return; ++ } ++ DEBUG_TRACE(PARSE_LINE); ++ resolved = resolve_bulks(service, queue); ++ vcos_mutex_unlock(&service->bulk_mutex); ++ if (resolved) ++ notify_bulks(service, queue); ++ } ++ } ++ break; ++ case VCHIQ_MSG_BULK_RX_DONE: ++ case VCHIQ_MSG_BULK_TX_DONE: ++ { ++ vcos_assert(!state->is_master); ++ if ((service->remoteport == remoteport) ++ && (service->srvstate != ++ VCHIQ_SRVSTATE_FREE)) { ++ VCHIQ_BULK_QUEUE_T *queue; ++ VCHIQ_BULK_T *bulk; ++ ++ queue = (type == VCHIQ_MSG_BULK_RX_DONE) ? ++ &service->bulk_rx : &service->bulk_tx; ++ ++ bulk = &queue->bulks[BULK_INDEX(queue->process)]; ++ bulk->actual = *(int *)header->data; ++ ++ vcos_log_info("%d: prs %s@%x (%d->%d) %x@%x", ++ state->id, msg_type_str(type), ++ (unsigned int)header, ++ remoteport, localport, ++ bulk->actual, (unsigned int)bulk->data); ++ ++ vcos_log_trace("%d: prs:%d %cx li=%x ri=%x p=%x", ++ state->id, localport, ++ (type == VCHIQ_MSG_BULK_RX_DONE) ? 'r' : 't', ++ queue->local_insert, ++ queue->remote_insert, queue->process); ++ ++ DEBUG_TRACE(PARSE_LINE); ++ if (vcos_mutex_lock(&service->bulk_mutex) != VCOS_SUCCESS) ++ { ++ DEBUG_TRACE(PARSE_LINE); ++ return; ++ } ++ DEBUG_TRACE(PARSE_LINE); ++ vcos_assert(queue->process != queue->local_insert); ++ vchiq_complete_bulk(bulk); ++ queue->process++; ++ vcos_mutex_unlock(&service->bulk_mutex); ++ DEBUG_TRACE(PARSE_LINE); ++ notify_bulks(service, queue); ++ DEBUG_TRACE(PARSE_LINE); ++ } ++ } ++ break; ++ case VCHIQ_MSG_PADDING: ++ vcos_log_trace("%d: prs PADDING@%x,%x", ++ state->id, (unsigned int)header, size); ++ break; ++ case VCHIQ_MSG_PAUSE: ++ /* If initiated, signal the application thread */ ++ vcos_log_trace("%d: prs PAUSE@%x,%x", ++ state->id, (unsigned int)header, size); ++ if (state->conn_state != VCHIQ_CONNSTATE_PAUSE_SENT) ++ { ++ /* Send a PAUSE in response */ ++ if (queue_message(state, NULL, ++ VCHIQ_MAKE_MSG(VCHIQ_MSG_PAUSE, 0, 0), ++ NULL, 0, 0, 0) == VCHIQ_RETRY) ++ return; /* Bail out if not ready */ ++ if (state->is_master) ++ pause_bulks(state); ++ } ++ /* At this point slot_mutex is held */ ++ vchiq_set_conn_state(state, VCHIQ_CONNSTATE_PAUSED); ++ vchiq_platform_paused(state); ++ break; ++ case VCHIQ_MSG_RESUME: ++ vcos_log_trace("%d: prs RESUME@%x,%x", ++ state->id, (unsigned int)header, size); ++ /* Release the slot mutex */ ++ vcos_mutex_unlock(&state->slot_mutex); ++ if (state->is_master) ++ resume_bulks(state); ++ vchiq_set_conn_state(state, VCHIQ_CONNSTATE_CONNECTED); ++ vchiq_platform_resumed(state); ++ break; ++ default: ++ vcos_log_error("%d: prs invalid msgid %x@%x,%x", ++ state->id, msgid, (unsigned int)header, size); ++ vcos_assert(0); ++ break; ++ } ++ ++ skip_message: ++ state->rx_pos += calc_stride(size); ++ ++ DEBUG_TRACE(PARSE_LINE); ++ /* Perform some housekeeping when the end of the slot is reached. */ ++ if ((state->rx_pos & VCHIQ_SLOT_MASK) == 0) ++ { ++ /* Remove the extra reference count. */ ++ release_slot(state, state->rx_info); ++ state->rx_data = NULL; ++ } ++ } ++} ++ ++/* Called by the slot handler thread */ ++static void * ++slot_handler_func(void *v) ++{ ++ VCHIQ_STATE_T *state = (VCHIQ_STATE_T *) v; ++ VCHIQ_SHARED_STATE_T *local = state->local; ++ DEBUG_INITIALISE(local) ++ ++ while (1) { ++ DEBUG_COUNT(SLOT_HANDLER_COUNT); ++ DEBUG_TRACE(SLOT_HANDLER_LINE); ++ remote_event_wait(&local->trigger); ++ ++ vcos_rmb(); ++ ++ DEBUG_TRACE(SLOT_HANDLER_LINE); ++ if (state->poll_needed) ++ { ++ state->poll_needed = 0; ++ ++ /* Handle service polling and other rare conditions here out ++ of the mainline code */ ++ switch (state->conn_state) ++ { ++ case VCHIQ_CONNSTATE_CONNECTED: ++ /* Poll the services as requested */ ++ poll_services(state); ++ break; ++ ++ case VCHIQ_CONNSTATE_PAUSING: ++ if (queue_message(state, NULL, ++ VCHIQ_MAKE_MSG(VCHIQ_MSG_PAUSE, 0, 0), NULL, 0, 0, 0) ++ != VCHIQ_RETRY) ++ { ++ if (state->is_master) ++ pause_bulks(state); ++ vchiq_set_conn_state(state, VCHIQ_CONNSTATE_PAUSE_SENT); ++ } ++ else ++ { ++ state->poll_needed = 1; /* Retry later */ ++ } ++ break; ++ ++ case VCHIQ_CONNSTATE_RESUMING: ++ if (queue_message(state, NULL, ++ VCHIQ_MAKE_MSG(VCHIQ_MSG_RESUME, 0, 0), NULL, 0, 0, 0) ++ != VCHIQ_RETRY) ++ { ++ if (state->is_master) ++ resume_bulks(state); ++ vchiq_set_conn_state(state, VCHIQ_CONNSTATE_CONNECTED); ++ vchiq_platform_resumed(state); ++ } ++ else ++ { ++ /* This should really be impossible, since the PAUSE should ++ have flushed through outstanding messages. */ ++ vcos_log_error("Failed to send RESUME message"); ++ vcos_demand(0); ++ } ++ break; ++ default: ++ break; ++ } ++ } ++ ++ DEBUG_TRACE(SLOT_HANDLER_LINE); ++ parse_rx_slots(state); ++ } ++ return NULL; ++} ++ ++extern VCHIQ_STATUS_T ++vchiq_platform_suspend(VCHIQ_STATE_T *state); ++ ++/* Called by the recycle thread */ ++static void * ++recycle_func(void *v) ++{ ++ VCHIQ_STATE_T *state = (VCHIQ_STATE_T *) v; ++ VCHIQ_SHARED_STATE_T *local = state->local; ++ ++ while (1) { ++ remote_event_wait(&local->recycle); ++ ++ vcos_mutex_lock(&state->slot_mutex); ++ ++ process_free_queue(state); ++ ++ vcos_mutex_unlock(&state->slot_mutex); ++ } ++ return NULL; ++} ++ ++/* Called by the lp thread */ ++static void * ++lp_func(void *v) ++{ ++ VCHIQ_STATE_T *state = (VCHIQ_STATE_T *) v; ++ ++ while (1) { ++ vcos_event_wait(&state->lp_evt); ++ vcos_mutex_lock(&state->use_count_mutex); ++ if (state->videocore_use_count == 0) ++ { ++ vchiq_platform_suspend(state); ++ } ++ vcos_mutex_unlock(&state->use_count_mutex); ++ } ++ return NULL; ++} ++ ++static void ++init_bulk_queue(VCHIQ_BULK_QUEUE_T *queue) ++{ ++ queue->local_insert = 0; ++ queue->remote_insert = 0; ++ queue->process = 0; ++ queue->remote_notify = 0; ++ queue->remove = 0; ++} ++ ++VCHIQ_SLOT_ZERO_T * ++vchiq_init_slots(void *mem_base, int mem_size) ++{ ++ int mem_align = (VCHIQ_SLOT_SIZE - (int)mem_base) & VCHIQ_SLOT_MASK; ++ VCHIQ_SLOT_ZERO_T *slot_zero = (VCHIQ_SLOT_ZERO_T *)((char *)mem_base + mem_align); ++ int num_slots = (mem_size - mem_align)/VCHIQ_SLOT_SIZE; ++ int first_data_slot = VCHIQ_SLOT_ZERO_SLOTS; ++ ++ /* Ensure there is enough memory to run an absolutely minimum system */ ++ num_slots -= first_data_slot; ++ ++ if (num_slots < 4) ++ { ++ vcos_log_error("vchiq_init_slots - insufficient memory %x bytes", mem_size); ++ return NULL; ++ } ++ ++ memset(slot_zero, 0, sizeof(VCHIQ_SLOT_ZERO_T)); ++ ++ slot_zero->magic = VCHIQ_MAGIC; ++ slot_zero->version = VCHIQ_VERSION; ++ slot_zero->version_min = VCHIQ_VERSION_MIN; ++ slot_zero->slot_zero_size = sizeof(VCHIQ_SLOT_ZERO_T); ++ slot_zero->slot_size = VCHIQ_SLOT_SIZE; ++ slot_zero->max_slots = VCHIQ_MAX_SLOTS; ++ slot_zero->max_slots_per_side = VCHIQ_MAX_SLOTS_PER_SIDE; ++ ++ slot_zero->master.slot_first = first_data_slot; ++ slot_zero->slave.slot_first = first_data_slot + (num_slots/2); ++ slot_zero->master.slot_last = slot_zero->slave.slot_first - 1; ++ slot_zero->slave.slot_last = first_data_slot + num_slots - 1; ++ ++ return slot_zero; ++} ++ ++VCHIQ_STATUS_T ++vchiq_init_state(VCHIQ_STATE_T *state, VCHIQ_SLOT_ZERO_T *slot_zero, int is_master) ++{ ++ VCHIQ_SHARED_STATE_T *local; ++ VCHIQ_SHARED_STATE_T *remote; ++ VCOS_THREAD_ATTR_T attrs; ++ char threadname[10]; ++ static int id = 0; ++ int i; ++ ++ vcos_log_set_level(&vchiq_core_log_category, vchiq_default_core_log_level); ++ vcos_log_set_level(&vchiq_core_msg_log_category, vchiq_default_core_msg_log_level); ++ vcos_log_register("vchiq_core", &vchiq_core_log_category); ++ vcos_log_register("vchiq_core_msg", &vchiq_core_msg_log_category); ++ ++ vcos_log_warn( "%s: slot_zero = 0x%08lx, is_master = %d\n", __func__, (unsigned long)slot_zero, is_master ); ++ ++ /* Check the input configuration */ ++ ++ if (slot_zero->magic != VCHIQ_MAGIC) ++ { ++ vcos_log_error("slot_zero=%x: magic=%x (expected %x)", ++ (unsigned int)slot_zero, slot_zero->magic, VCHIQ_MAGIC); ++ return VCHIQ_ERROR; ++ } ++ ++ if (slot_zero->version < VCHIQ_VERSION_MIN) ++ { ++ vcos_log_error("slot_zero=%x: peer_version=%x (minimum %x)", ++ (unsigned int)slot_zero, slot_zero->version, VCHIQ_VERSION_MIN); ++ return VCHIQ_ERROR; ++ } ++ ++ if (VCHIQ_VERSION < slot_zero->version_min) ++ { ++ vcos_log_error("slot_zero=%x: version=%x (peer minimum %x)", ++ (unsigned int)slot_zero, VCHIQ_VERSION, slot_zero->version_min); ++ return VCHIQ_ERROR; ++ } ++ ++ if (slot_zero->slot_zero_size != sizeof(VCHIQ_SLOT_ZERO_T)) ++ { ++ vcos_log_error("slot_zero=%x: slot_zero_size=%x (expected %x)", ++ (unsigned int)slot_zero, slot_zero->slot_zero_size, sizeof(VCHIQ_SLOT_ZERO_T)); ++ return VCHIQ_ERROR; ++ } ++ ++ if (slot_zero->slot_size != VCHIQ_SLOT_SIZE) ++ { ++ vcos_log_error("slot_zero=%x: slot_size=%d (expected %d", ++ (unsigned int)slot_zero, slot_zero->slot_size, VCHIQ_SLOT_SIZE); ++ return VCHIQ_ERROR; ++ } ++ ++ if (slot_zero->max_slots != VCHIQ_MAX_SLOTS) ++ { ++ vcos_log_error("slot_zero=%x: max_slots=%d (expected %d)", ++ (unsigned int)slot_zero, slot_zero->max_slots, VCHIQ_MAX_SLOTS); ++ return VCHIQ_ERROR; ++ } ++ ++ if (slot_zero->max_slots_per_side != VCHIQ_MAX_SLOTS_PER_SIDE) ++ { ++ vcos_log_error("slot_zero=%x: max_slots_per_side=%d (expected %d)", ++ (unsigned int)slot_zero, slot_zero->max_slots_per_side, ++ VCHIQ_MAX_SLOTS_PER_SIDE); ++ return VCHIQ_ERROR; ++ } ++ ++ if (is_master) ++ { ++ local = &slot_zero->master; ++ remote = &slot_zero->slave; ++ } ++ else ++ { ++ local = &slot_zero->slave; ++ remote = &slot_zero->master; ++ } ++ ++ if (local->initialised) ++ { ++ if (remote->initialised) ++ vcos_log_error("vchiq: FATAL: local state has already been initialised"); ++ else ++ vcos_log_error("vchiq: FATAL: master/slave mismatch - two %ss", is_master ? "master" : "slave"); ++ return VCHIQ_ERROR; ++ } ++ ++ memset(state, 0, sizeof(VCHIQ_STATE_T)); ++ state->id = id++; ++ state->is_master = is_master; ++ ++ /* ++ initialize shared state pointers ++ */ ++ ++ state->local = local; ++ state->remote = remote; ++ state->slot_data = (VCHIQ_SLOT_T *)slot_zero; ++ ++ /* ++ initialize events and mutexes ++ */ ++ ++ vcos_event_create(&state->connect, "v.connect"); ++ vcos_mutex_create(&state->mutex, "v.mutex"); ++ vcos_event_create(&state->trigger_event, "v.trigger_event"); ++ vcos_event_create(&state->recycle_event, "v.recycle_event"); ++ ++ vcos_mutex_create(&state->slot_mutex, "v.slot_mutex"); ++ vcos_mutex_create(&state->recycle_mutex, "v.recycle_mutex"); ++ vcos_mutex_create(&state->use_count_mutex, "v.use_count_mutex"); ++ vcos_mutex_create(&state->suspend_resume_mutex, "v.susp_res_mutex"); ++ ++ vcos_event_create(&state->slot_available_event, "v.slot_available_event"); ++ vcos_event_create(&state->slot_remove_event, "v.slot_remove_event"); ++ ++ state->slot_queue_available = 0; ++ ++ for (i = 0; i < VCHIQ_MAX_SERVICES; i++) ++ { ++ VCHIQ_SERVICE_QUOTA_T *service_quota = &state->service_quotas[i]; ++ vcos_event_create(&service_quota->quota_event, "v.quota_event"); ++ } ++ ++ for (i = local->slot_first; i <= local->slot_last; i++) ++ { ++ local->slot_queue[state->slot_queue_available++] = i; ++ } ++ ++ state->default_slot_quota = state->slot_queue_available/2; ++ ++ local->trigger.event = &state->trigger_event; ++ remote_event_create(&local->trigger); ++ local->tx_pos = 0; ++ ++ local->recycle.event = &state->recycle_event; ++ remote_event_create(&local->recycle); ++ local->slot_queue_recycle = state->slot_queue_available; ++ ++ vcos_event_create(&state->lp_evt, "LP_EVT"); ++ ++ local->debug[DEBUG_ENTRIES] = DEBUG_MAX; ++ ++ /* ++ bring up slot handler thread ++ */ ++ ++ vcos_thread_attr_init(&attrs); ++ vcos_thread_attr_setstacksize(&attrs, VCHIQ_SLOT_HANDLER_STACK); ++ vcos_thread_attr_setpriority(&attrs, VCOS_THREAD_PRI_REALTIME); ++ vcos_snprintf(threadname, sizeof(threadname), "VCHIQ-%d", state->id); ++ if (vcos_thread_create(&state->slot_handler_thread, threadname, ++ &attrs, slot_handler_func, state) != VCOS_SUCCESS) ++ return VCHIQ_ERROR; ++ ++ vcos_thread_attr_init(&attrs); ++ vcos_thread_attr_setstacksize(&attrs, VCHIQ_SLOT_HANDLER_STACK); ++ vcos_thread_attr_setpriority(&attrs, VCOS_THREAD_PRI_REALTIME); ++ vcos_snprintf(threadname, sizeof(threadname), "VCHIQr-%d", state->id); ++ if (vcos_thread_create(&state->recycle_thread, threadname, ++ &attrs, recycle_func, state) != VCOS_SUCCESS) ++ return VCHIQ_ERROR; ++ ++ vcos_thread_attr_init(&attrs); ++ vcos_thread_attr_setstacksize(&attrs, VCHIQ_SLOT_HANDLER_STACK); ++ vcos_thread_attr_setpriority(&attrs, VCOS_THREAD_PRI_LOWEST); ++ vcos_snprintf(threadname, sizeof(threadname), "VCHIQl-%d", state->id); ++ if (vcos_thread_create(&state->lp_thread, threadname, ++ &attrs, lp_func, state) != VCOS_SUCCESS) ++ return VCHIQ_ERROR; ++ ++ /* Indicate readiness to the other side */ ++ local->initialised = 1; ++ ++ return VCHIQ_SUCCESS; ++} ++ ++/* Called from application thread when a client or server service is created. */ ++VCHIQ_SERVICE_T * ++vchiq_add_service_internal(VCHIQ_STATE_T *state, ++ const VCHIQ_SERVICE_PARAMS_T *params, int srvstate, ++ VCHIQ_INSTANCE_T instance) ++{ ++ VCHIQ_SERVICE_T **pservice = NULL; ++ VCHIQ_SERVICE_T *service = NULL; ++ int i; ++ ++ /* Prepare to use a previously unused service */ ++ if (state->unused_service < VCHIQ_MAX_SERVICES) ++ { ++ pservice = &state->services[state->unused_service]; ++ } ++ ++ if (srvstate == VCHIQ_SRVSTATE_OPENING) { ++ for (i = 0; i < state->unused_service; i++) { ++ VCHIQ_SERVICE_T *srv = state->services[i]; ++ if (!srv) ++ { ++ pservice = &state->services[i]; ++ break; ++ } ++ if (srv->srvstate == VCHIQ_SRVSTATE_FREE) { ++ service = srv; ++ break; ++ } ++ } ++ } else { ++ for (i = (state->unused_service - 1); i >= 0; i--) { ++ VCHIQ_SERVICE_T *srv = state->services[i]; ++ if (!srv) ++ pservice = &state->services[i]; ++ else if (srv->srvstate == VCHIQ_SRVSTATE_FREE) { ++ service = srv; ++ } else if ((srv->public_fourcc == params->fourcc) && ++ ((srv->instance != instance) ++ || (srv->base.callback != params->callback))) { ++ /* There is another server using this fourcc which doesn't match */ ++ pservice = NULL; ++ service = NULL; ++ } ++ } ++ } ++ ++ if (pservice && !service) ++ { ++ service = vcos_malloc(sizeof(VCHIQ_SERVICE_T), "VCHIQ service"); ++ if (service) ++ { ++ service->srvstate = VCHIQ_SRVSTATE_FREE; ++ service->localport = (pservice - state->services); ++ vcos_event_create(&service->remove_event, "v.remove_event"); ++ vcos_event_create(&service->bulk_remove_event, "v.bulk_remove_event"); ++ vcos_mutex_create(&service->bulk_mutex, "v.bulk_mutex"); ++ *pservice = service; ++ } ++ else ++ { ++ vcos_log_error("vchiq: Out of memory"); ++ } ++ } ++ ++ if (service) { ++ VCHIQ_SERVICE_QUOTA_T *service_quota = ++ &state->service_quotas[service->localport]; ++ if (vcos_is_log_enabled( &vchiq_core_msg_log_category, VCOS_LOG_INFO)) { ++ vcos_log_impl( &vchiq_core_msg_log_category, ++ VCOS_LOG_INFO, ++ "%s Service %c%c%c%c SrcPort:%d", ++ ( srvstate == VCHIQ_SRVSTATE_OPENING ) ++ ? "Open" : "Add", ++ VCHIQ_FOURCC_AS_4CHARS(params->fourcc), ++ service->localport ); ++ } ++ service->state = state; ++ service->base.fourcc = params->fourcc; ++ service->base.callback = params->callback; ++ service->base.userdata = params->userdata; ++ service->version = params->version; ++ service->version_min = params->version_min; ++ vchiq_set_service_state(service, srvstate); ++ service->public_fourcc = ++ (srvstate == ++ VCHIQ_SRVSTATE_OPENING) ? VCHIQ_FOURCC_INVALID : params->fourcc; ++ service->instance = instance; ++ service->remoteport = VCHIQ_PORT_FREE; ++ service->client_id = 0; ++ service->auto_close = 1; ++ service->service_use_count = 0; ++ init_bulk_queue(&service->bulk_tx); ++ init_bulk_queue(&service->bulk_rx); ++ service_quota->slot_quota = state->default_slot_quota; ++ if (service_quota->slot_use_count == 0) ++ service_quota->previous_tx_index = ++ SLOT_QUEUE_INDEX_FROM_POS(state->local_tx_pos) - 1; ++ memset(&service->stats, 0, sizeof(service->stats)); ++ vcos_atomic_flags_create(&service->poll_flags); ++ ++ /* Ensure the events are unsignalled */ ++ while (vcos_event_try(&service->remove_event) == VCOS_SUCCESS) ++ continue; ++ while (vcos_event_try(&service_quota->quota_event) == VCOS_SUCCESS) ++ continue; ++ ++ if (pservice == &state->services[state->unused_service]) ++ state->unused_service++; ++ } ++ ++ return service; ++} ++ ++VCHIQ_STATUS_T ++vchiq_open_service_internal(VCHIQ_SERVICE_T *service, int client_id) ++{ ++ VCHIQ_OPEN_PAYLOAD_T payload = { ++ service->base.fourcc, ++ client_id, ++ service->version, ++ service->version_min ++ }; ++ VCHIQ_ELEMENT_T body = { &payload, sizeof(payload) }; ++ VCHIQ_STATUS_T status = VCHIQ_SUCCESS; ++ ++ service->client_id = client_id; ++ vchiq_use_service(&service->base); ++ status = queue_message(service->state, NULL, ++ VCHIQ_MAKE_MSG(VCHIQ_MSG_OPEN, service->localport, 0), ++ &body, 1, sizeof(payload), 1); ++ if (status == VCHIQ_SUCCESS) { ++ if (vcos_event_wait(&service->remove_event) != VCOS_SUCCESS) { ++ status = VCHIQ_RETRY; ++ vchiq_release_service(&service->base); ++ } else if (service->srvstate != VCHIQ_SRVSTATE_OPEN) { ++ vcos_log_info("%d: osi - srvstate = %d", service->state->id, service->srvstate); ++ vcos_assert(service->srvstate == VCHIQ_SRVSTATE_CLOSEWAIT); ++ status = VCHIQ_ERROR; ++ VCHIQ_SERVICE_STATS_INC(service, error_count); ++ vchiq_release_service(&service->base); ++ } ++ } ++ return status; ++} ++ ++/* Called by the slot handler */ ++VCHIQ_STATUS_T ++vchiq_close_service_internal(VCHIQ_SERVICE_T *service, int close_recvd) ++{ ++ VCHIQ_STATE_T *state = service->state; ++ VCHIQ_STATUS_T status = VCHIQ_SUCCESS; ++ ++ vcos_log_trace("%d: csi:%d (%s)", ++ service->state->id, service->localport, ++ srvstate_names[service->srvstate]); ++ ++ switch (service->srvstate) ++ { ++ case VCHIQ_SRVSTATE_OPENING: ++ if (close_recvd) ++ { ++ /* The open was rejected - tell the user */ ++ vchiq_set_service_state(service, VCHIQ_SRVSTATE_CLOSEWAIT); ++ vcos_event_signal(&service->remove_event); ++ } ++ else ++ { ++ /* Shutdown mid-open - let the other side know */ ++ status = queue_message(state, NULL, ++ VCHIQ_MAKE_MSG ++ (VCHIQ_MSG_CLOSE, ++ service->localport, ++ VCHIQ_MSG_DSTPORT(service->remoteport)), ++ NULL, 0, 0, 0); ++ ++ if (status == VCHIQ_SUCCESS) ++ vchiq_set_service_state(service, VCHIQ_SRVSTATE_CLOSESENT); ++ } ++ break; ++ ++ case VCHIQ_SRVSTATE_OPEN: ++ if (state->is_master) ++ { ++ /* Abort any outstanding bulk transfers */ ++ vcos_mutex_lock(&service->bulk_mutex); ++ abort_outstanding_bulks(service, &service->bulk_tx); ++ abort_outstanding_bulks(service, &service->bulk_rx); ++ status = notify_bulks(service, &service->bulk_tx); ++ if (status == VCHIQ_SUCCESS) ++ status = notify_bulks(service, &service->bulk_rx); ++ vcos_mutex_unlock(&service->bulk_mutex); ++ } ++ ++ if (status == VCHIQ_SUCCESS) ++ status = queue_message(state, NULL, ++ VCHIQ_MAKE_MSG ++ (VCHIQ_MSG_CLOSE, ++ service->localport, ++ VCHIQ_MSG_DSTPORT(service->remoteport)), ++ NULL, 0, 0, 0); ++ ++ if (status == VCHIQ_SUCCESS) ++ { ++ if (close_recvd) ++ vchiq_set_service_state(service, VCHIQ_SRVSTATE_CLOSING); ++ else ++ vchiq_set_service_state(service, VCHIQ_SRVSTATE_CLOSESENT); ++ } ++ break; ++ ++ case VCHIQ_SRVSTATE_CLOSESENT: ++ vcos_assert(close_recvd); ++ ++ if (!state->is_master) ++ { ++ /* Abort any outstanding bulk transfers */ ++ vcos_mutex_lock(&service->bulk_mutex); ++ abort_outstanding_bulks(service, &service->bulk_tx); ++ abort_outstanding_bulks(service, &service->bulk_rx); ++ status = notify_bulks(service, &service->bulk_tx); ++ if (status == VCHIQ_SUCCESS) ++ status = notify_bulks(service, &service->bulk_rx); ++ vcos_mutex_unlock(&service->bulk_mutex); ++ } ++ ++ if (status == VCHIQ_SUCCESS) ++ vchiq_set_service_state(service, VCHIQ_SRVSTATE_CLOSING); ++ break; ++ ++ case VCHIQ_SRVSTATE_CLOSING: ++ /* We may come here after a retry */ ++ vcos_assert(!close_recvd); ++ break; ++ ++ default: ++ vcos_log_error("vchiq_close_service_internal(%d) called in state %s", ++ close_recvd, srvstate_names[service->srvstate]); ++ vcos_assert(0); ++ break; ++ } ++ ++ if (service->srvstate == VCHIQ_SRVSTATE_CLOSING) ++ { ++ /* Complete the close process */ ++ vchiq_release_service(&service->base); ++ ++ service->client_id = 0; ++ ++ /* Now tell the client that the services is closed */ ++ if (service->instance) ++ { ++ int oldstate = service->srvstate; ++ ++ /* Change the service state now for the benefit of the callback */ ++ vchiq_set_service_state(service, ++ ((service->public_fourcc == VCHIQ_FOURCC_INVALID) || ++ !service->auto_close) ? ++ VCHIQ_SRVSTATE_CLOSEWAIT : ++ VCHIQ_SRVSTATE_LISTENING); ++ ++ status = make_service_callback(service, VCHIQ_SERVICE_CLOSED, NULL, NULL); ++ ++ if (status == VCHIQ_RETRY) ++ { ++ /* Restore the old state, to be retried later */ ++ vchiq_set_service_state(service, oldstate); ++ } ++ else ++ { ++ if (status == VCHIQ_ERROR) { ++ /* Signal an error (fatal, since the other end will probably have closed) */ ++ vchiq_set_service_state(service, VCHIQ_SRVSTATE_OPEN); ++ } ++ } ++ } ++ ++ if (status != VCHIQ_RETRY) ++ { ++ if (service->srvstate == VCHIQ_SRVSTATE_CLOSING) ++ vchiq_set_service_state(service, VCHIQ_SRVSTATE_CLOSEWAIT); ++ vcos_event_signal(&service->remove_event); ++ } ++ } ++ ++ return status; ++} ++ ++/* Called from the application process upon process death */ ++void ++vchiq_terminate_service_internal(VCHIQ_SERVICE_T *service) ++{ ++ VCHIQ_STATE_T *state = service->state; ++ ++ vcos_log_info("%d: tsi - (%d<->%d)", state->id, service->localport, service->remoteport); ++ ++ /* Disconnect from the instance, to prevent any callbacks */ ++ service->instance = NULL; ++ ++ /* Mark the service for termination by the slot handler */ ++ request_poll(state, service, VCHIQ_POLL_TERMINATE); ++} ++ ++/* Called from the application process upon process death, and from ++ vchiq_remove_service */ ++void ++vchiq_free_service_internal(VCHIQ_SERVICE_T *service) ++{ ++ VCHIQ_STATE_T *state = service->state; ++ int slot_last = state->remote->slot_last; ++ int i; ++ ++ vcos_log_info("%d: fsi - (%d)", state->id, service->localport); ++ ++ vcos_mutex_lock(&state->mutex); ++ ++ /* Release any claimed messages */ ++ for (i = state->remote->slot_first; i <= slot_last; i++) ++ { ++ VCHIQ_SLOT_INFO_T *slot_info = SLOT_INFO_FROM_INDEX(state, i); ++ if (slot_info->release_count != slot_info->use_count) ++ { ++ char *data = (char *)SLOT_DATA_FROM_INDEX(state, i); ++ int pos, end; ++ ++ end = VCHIQ_SLOT_SIZE; ++ if (data == state->rx_data) ++ { ++ /* This buffer is still being read from - stop at the current read position */ ++ end = state->rx_pos & VCHIQ_SLOT_MASK; ++ } ++ ++ pos = 0; ++ ++ while (pos < end) ++ { ++ VCHIQ_HEADER_T *header = (VCHIQ_HEADER_T *)(data + pos); ++ int msgid = header->msgid; ++ int port = VCHIQ_MSG_DSTPORT(msgid); ++ if (port == service->localport) ++ { ++ if (msgid & VCHIQ_MSGID_CLAIMED) ++ { ++ header->msgid = msgid & ~VCHIQ_MSGID_CLAIMED; ++ vcos_log_info(" fsi - hdr %x", (unsigned int)header); ++ release_slot(state, slot_info); ++ } ++ } ++ pos += calc_stride(header->size); ++ } ++ } ++ } ++ ++ vcos_assert(state->services[service->localport] == service); ++ vchiq_set_service_state(service, VCHIQ_SRVSTATE_FREE); ++ state->services[service->localport] = NULL; ++ vcos_free(service); ++ vcos_mutex_unlock(&state->mutex); ++} ++ ++VCHIQ_STATUS_T ++vchiq_connect_internal(VCHIQ_STATE_T *state, VCHIQ_INSTANCE_T instance) ++{ ++ int i; ++ ++ /* Find all services registered to this client and enable them. */ ++ for (i = 0; i < state->unused_service; i++) ++ { ++ VCHIQ_SERVICE_T *service = state->services[i]; ++ if (service && (service->instance == instance)) { ++ if (service->srvstate == VCHIQ_SRVSTATE_HIDDEN) ++ vchiq_set_service_state(service, ++ VCHIQ_SRVSTATE_LISTENING); ++ } ++ } ++ ++ if (state->conn_state == VCHIQ_CONNSTATE_DISCONNECTED) { ++ if (queue_message(state, NULL, ++ VCHIQ_MAKE_MSG(VCHIQ_MSG_CONNECT, 0, 0), NULL, 0, ++ 0, 1) == VCHIQ_RETRY) ++ return VCHIQ_RETRY; ++ vcos_event_wait(&state->connect); ++ ++ vchiq_set_conn_state(state, VCHIQ_CONNSTATE_CONNECTED); ++ } ++ ++ return VCHIQ_SUCCESS; ++} ++ ++VCHIQ_STATUS_T ++vchiq_shutdown_internal(VCHIQ_STATE_T *state, VCHIQ_INSTANCE_T instance) ++{ ++ VCHIQ_STATUS_T status = VCHIQ_SUCCESS; ++ int i; ++ ++ /* Find all services registered to this client and close them. */ ++ for (i = 0; i < state->unused_service; i++) ++ { ++ VCHIQ_SERVICE_T *service = state->services[i]; ++ if (service && (service->instance == instance) && ++ ((service->srvstate == VCHIQ_SRVSTATE_OPEN) || ++ (service->srvstate == VCHIQ_SRVSTATE_LISTENING))) ++ { ++ status = vchiq_remove_service(&service->base); ++ if (status != VCHIQ_SUCCESS) ++ break; ++ } ++ } ++ ++ return status; ++} ++ ++VCHIQ_STATUS_T ++vchiq_pause_internal(VCHIQ_STATE_T *state) ++{ ++ VCHIQ_STATUS_T status = VCHIQ_SUCCESS; ++ ++ switch (state->conn_state) ++ { ++ case VCHIQ_CONNSTATE_CONNECTED: ++ /* Request a pause */ ++ vchiq_set_conn_state(state, VCHIQ_CONNSTATE_PAUSING); ++ request_poll(state, NULL, 0); ++ break; ++ case VCHIQ_CONNSTATE_PAUSED: ++ break; ++ default: ++ status = VCHIQ_ERROR; ++ VCHIQ_STATS_INC(state, error_count); ++ break; ++ } ++ ++ return status; ++} ++ ++VCHIQ_STATUS_T ++vchiq_resume_internal(VCHIQ_STATE_T *state) ++{ ++ VCHIQ_STATUS_T status = VCHIQ_SUCCESS; ++ ++ if (state->conn_state == VCHIQ_CONNSTATE_PAUSED) ++ { ++ vchiq_set_conn_state(state, VCHIQ_CONNSTATE_RESUMING); ++ request_poll(state, NULL, 0); ++ } ++ else ++ { ++ status = VCHIQ_ERROR; ++ VCHIQ_STATS_INC(state, error_count); ++ } ++ ++ return status; ++} ++ ++VCHIQ_STATUS_T ++vchiq_close_service(VCHIQ_SERVICE_HANDLE_T handle) ++{ ++ /* Unregister the service */ ++ VCHIQ_SERVICE_T *service = (VCHIQ_SERVICE_T *) handle; ++ VCHIQ_STATUS_T status = VCHIQ_ERROR; ++ ++ if (service == NULL) ++ return VCHIQ_ERROR; ++ ++ vcos_log_info("%d: close_service:%d", service->state->id, service->localport); ++ ++ if (service->public_fourcc != VCHIQ_FOURCC_INVALID) ++ { ++ if (service->srvstate == VCHIQ_SRVSTATE_CLOSEWAIT) ++ { ++ /* This is a non-auto-close server */ ++ vchiq_set_service_state(service, VCHIQ_SRVSTATE_LISTENING); ++ status = VCHIQ_SUCCESS; ++ } ++ } ++ else ++ { ++ /* For clients, make it an alias of vchiq_remove_service */ ++ status = vchiq_remove_service(handle); ++ } ++ ++ return status; ++} ++ ++VCHIQ_STATUS_T ++vchiq_remove_service(VCHIQ_SERVICE_HANDLE_T handle) ++{ ++ /* Unregister the service */ ++ VCHIQ_SERVICE_T *service = (VCHIQ_SERVICE_T *) handle; ++ VCHIQ_STATUS_T status = VCHIQ_SUCCESS; ++ ++ if (service == NULL) ++ return VCHIQ_ERROR; ++ ++ vcos_log_info("%d: remove_service:%d", service->state->id, service->localport); ++ ++ switch (service->srvstate) ++ { ++ case VCHIQ_SRVSTATE_OPENING: ++ case VCHIQ_SRVSTATE_OPEN: ++ /* Mark the service for termination by the slot handler */ ++ request_poll(service->state, service, VCHIQ_POLL_TERMINATE); ++ ++ /* Drop through... */ ++ case VCHIQ_SRVSTATE_CLOSESENT: ++ case VCHIQ_SRVSTATE_CLOSING: ++ while ((service->srvstate != VCHIQ_SRVSTATE_CLOSEWAIT) && ++ (service->srvstate != VCHIQ_SRVSTATE_LISTENING)) ++ { ++ if (vcos_event_wait(&service->remove_event) != VCOS_SUCCESS) { ++ status = VCHIQ_RETRY; ++ break; ++ } ++ } ++ break; ++ ++ default: ++ break; ++ } ++ ++ if (status == VCHIQ_SUCCESS) { ++ if (service->srvstate == VCHIQ_SRVSTATE_OPEN) ++ status = VCHIQ_ERROR; ++ else ++ { ++ service->instance = NULL; ++ vchiq_free_service_internal(service); ++ } ++ } ++ ++ return status; ++} ++ ++ ++VCHIQ_STATUS_T ++vchiq_bulk_transfer(VCHIQ_SERVICE_T *service, ++ VCHI_MEM_HANDLE_T memhandle, void *offset, int size, void *userdata, ++ VCHIQ_BULK_MODE_T mode, VCHIQ_BULK_DIR_T dir) ++{ ++ VCHIQ_BULK_QUEUE_T *queue = (dir == VCHIQ_BULK_TRANSMIT) ? ++ &service->bulk_tx : &service->bulk_rx; ++ VCHIQ_BULK_T *bulk; ++ VCHIQ_STATE_T *state; ++ BULK_WAITER_T bulk_waiter; ++ const char dir_char = (dir == VCHIQ_BULK_TRANSMIT) ? 't' : 'r'; ++ const int dir_msgtype = (dir == VCHIQ_BULK_TRANSMIT) ? VCHIQ_MSG_BULK_TX : VCHIQ_MSG_BULK_RX; ++ VCHIQ_STATUS_T status = VCHIQ_ERROR; ++ ++ if ((service == NULL) || ++ ((memhandle == VCHI_MEM_HANDLE_INVALID) && (offset == NULL))) ++ return VCHIQ_ERROR; ++ ++ state = service->state; ++ ++ if (service->srvstate != VCHIQ_SRVSTATE_OPEN) ++ return VCHIQ_ERROR; /* Must be connected */ ++ ++ if (vcos_mutex_lock(&service->bulk_mutex) != VCOS_SUCCESS) ++ return VCHIQ_RETRY; ++ ++ if (queue->local_insert == queue->remove + VCHIQ_NUM_SERVICE_BULKS) ++ { ++ VCHIQ_SERVICE_STATS_INC(service, bulk_stalls); ++ do { ++ vcos_mutex_unlock(&service->bulk_mutex); ++ if (vcos_event_wait(&service->bulk_remove_event) != VCOS_SUCCESS) ++ return VCHIQ_RETRY; ++ if (vcos_mutex_lock(&service->bulk_mutex) != VCOS_SUCCESS) ++ return VCHIQ_RETRY; ++ } while (queue->local_insert == queue->remove + VCHIQ_NUM_SERVICE_BULKS); ++ } ++ ++ bulk = &queue->bulks[BULK_INDEX(queue->local_insert)]; ++ ++ if (mode == VCHIQ_BULK_MODE_BLOCKING) ++ { ++ vcos_event_create(&bulk_waiter.event, "bulk_waiter"); ++ bulk_waiter.actual = 0; ++ userdata = &bulk_waiter; ++ } ++ ++ bulk->mode = mode; ++ bulk->dir = dir; ++ bulk->userdata = userdata; ++ bulk->size = size; ++ bulk->actual = VCHIQ_BULK_ACTUAL_ABORTED; ++ ++ if (vchiq_prepare_bulk_data(bulk, memhandle, offset, size, dir) != VCHIQ_SUCCESS) ++ { ++ goto error_exit; ++ } ++ ++ vcos_log_info("%d: bt (%d->%d) %cx %x@%x %x", state->id, ++ service->localport, service->remoteport, dir_char, ++ size, (unsigned int)bulk->data, (unsigned int)userdata); ++ ++ if (state->is_master) ++ { ++ queue->local_insert++; ++ if (resolve_bulks(service, queue)) ++ request_poll(state, service, (dir == VCHIQ_BULK_TRANSMIT) ? ++ VCHIQ_POLL_TXNOTIFY : VCHIQ_POLL_RXNOTIFY); ++ } ++ else ++ { ++ int payload[2] = { (int)bulk->data, bulk->size }; ++ VCHIQ_ELEMENT_T element = { payload, sizeof(payload) }; ++ ++ if (queue_message(state, NULL, ++ VCHIQ_MAKE_MSG(dir_msgtype, ++ service->localport, service->remoteport), ++ &element, 1, sizeof(payload), 1) != VCHIQ_SUCCESS) ++ { ++ vchiq_complete_bulk(bulk); ++ goto error_exit; ++ } ++ queue->local_insert++; ++ queue->remote_insert++; ++ } ++ ++ vcos_mutex_unlock(&service->bulk_mutex); ++ ++ vcos_log_trace("%d: bt:%d %cx li=%x ri=%x p=%x", state->id, ++ service->localport, dir_char, ++ queue->local_insert, queue->remote_insert, queue->process); ++ ++ status = VCHIQ_SUCCESS; ++ ++ if (mode == VCHIQ_BULK_MODE_BLOCKING) ++ { ++ if (vcos_event_wait(&bulk_waiter.event) != VCOS_SUCCESS) ++ { ++ vcos_log_info("bulk wait interrupted"); ++ /* Stop notify_bulks signalling a non-existent waiter */ ++ bulk->userdata = NULL; ++ status = VCHIQ_ERROR; ++ } ++ else if (bulk_waiter.actual == VCHIQ_BULK_ACTUAL_ABORTED) ++ status = VCHIQ_ERROR; ++ ++ vcos_event_delete(&bulk_waiter.event); ++ } ++ ++ return status; ++ ++error_exit: ++ if (mode == VCHIQ_BULK_MODE_BLOCKING) ++ vcos_event_delete(&bulk_waiter.event); ++ vcos_mutex_unlock(&service->bulk_mutex); ++ ++ return status; ++} ++ ++VCHIQ_STATUS_T ++vchiq_queue_bulk_transmit(VCHIQ_SERVICE_HANDLE_T handle, ++ const void *data, int size, void *userdata) ++{ ++ return vchiq_bulk_transfer((VCHIQ_SERVICE_T *)handle, ++ VCHI_MEM_HANDLE_INVALID, (void *)data, size, userdata, ++ VCHIQ_BULK_MODE_CALLBACK, VCHIQ_BULK_TRANSMIT); ++} ++ ++VCHIQ_STATUS_T ++vchiq_queue_bulk_receive(VCHIQ_SERVICE_HANDLE_T handle, void *data, int size, ++ void *userdata) ++{ ++ return vchiq_bulk_transfer((VCHIQ_SERVICE_T *)handle, ++ VCHI_MEM_HANDLE_INVALID, data, size, userdata, ++ VCHIQ_BULK_MODE_CALLBACK, VCHIQ_BULK_RECEIVE); ++} ++ ++VCHIQ_STATUS_T ++vchiq_queue_bulk_transmit_handle(VCHIQ_SERVICE_HANDLE_T handle, ++ VCHI_MEM_HANDLE_T memhandle, const void *offset, int size, void *userdata) ++{ ++ return vchiq_bulk_transfer((VCHIQ_SERVICE_T *)handle, ++ memhandle, (void *)offset, size, userdata, ++ VCHIQ_BULK_MODE_CALLBACK, VCHIQ_BULK_TRANSMIT); ++} ++ ++VCHIQ_STATUS_T ++vchiq_queue_bulk_receive_handle(VCHIQ_SERVICE_HANDLE_T handle, ++ VCHI_MEM_HANDLE_T memhandle, void *offset, int size, void *userdata) ++{ ++ return vchiq_bulk_transfer((VCHIQ_SERVICE_T *)handle, ++ memhandle, offset, size, userdata, ++ VCHIQ_BULK_MODE_CALLBACK, VCHIQ_BULK_RECEIVE); ++} ++ ++VCHIQ_STATUS_T ++vchiq_bulk_transmit(VCHIQ_SERVICE_HANDLE_T handle, const void *data, int size, ++ void *userdata, VCHIQ_BULK_MODE_T mode) ++{ ++ return vchiq_bulk_transfer((VCHIQ_SERVICE_T *)handle, ++ VCHI_MEM_HANDLE_INVALID, (void *)data, size, userdata, ++ mode, VCHIQ_BULK_TRANSMIT); ++} ++ ++VCHIQ_STATUS_T ++vchiq_bulk_receive(VCHIQ_SERVICE_HANDLE_T handle, void *data, int size, ++ void *userdata, VCHIQ_BULK_MODE_T mode) ++{ ++ return vchiq_bulk_transfer((VCHIQ_SERVICE_T *)handle, ++ VCHI_MEM_HANDLE_INVALID, data, size, userdata, ++ mode, VCHIQ_BULK_RECEIVE); ++} ++ ++VCHIQ_STATUS_T ++vchiq_bulk_transmit_handle(VCHIQ_SERVICE_HANDLE_T handle, ++ VCHI_MEM_HANDLE_T memhandle, const void *offset, int size, void *userdata, ++ VCHIQ_BULK_MODE_T mode) ++{ ++ return vchiq_bulk_transfer((VCHIQ_SERVICE_T *)handle, ++ memhandle, (void *)offset, size, userdata, ++ mode, VCHIQ_BULK_TRANSMIT); ++} ++ ++VCHIQ_STATUS_T ++vchiq_bulk_receive_handle(VCHIQ_SERVICE_HANDLE_T handle, ++ VCHI_MEM_HANDLE_T memhandle, void *offset, int size, void *userdata, ++ VCHIQ_BULK_MODE_T mode) ++{ ++ return vchiq_bulk_transfer((VCHIQ_SERVICE_T *)handle, ++ memhandle, offset, size, userdata, ++ mode, VCHIQ_BULK_RECEIVE); ++} ++ ++VCHIQ_STATUS_T ++vchiq_queue_message(VCHIQ_SERVICE_HANDLE_T handle, ++ const VCHIQ_ELEMENT_T *elements, int count) ++{ ++ VCHIQ_SERVICE_T *service = (VCHIQ_SERVICE_T *) handle; ++ ++ unsigned int size = 0; ++ unsigned int i; ++ ++ if ((service == NULL) || ++ (service->srvstate != VCHIQ_SRVSTATE_OPEN)) ++ return VCHIQ_ERROR; ++ ++ for (i = 0; i < (unsigned int)count; i++) ++ { ++ if (elements[i].size) ++ { ++ if (elements[i].data == NULL) ++ { ++ VCHIQ_SERVICE_STATS_INC(service, error_count); ++ return VCHIQ_ERROR; ++ } ++ size += elements[i].size; ++ } ++ } ++ ++ if (size > VCHIQ_MAX_MSG_SIZE) ++ { ++ VCHIQ_SERVICE_STATS_INC(service, error_count); ++ return VCHIQ_ERROR; ++ } ++ ++ return queue_message(service->state, service, ++ VCHIQ_MAKE_MSG(VCHIQ_MSG_DATA, service->localport, ++ service->remoteport), elements, count, size, 1); ++} ++ ++void ++vchiq_release_message(VCHIQ_SERVICE_HANDLE_T handle, VCHIQ_HEADER_T *header) ++{ ++ VCHIQ_SERVICE_T *service = (VCHIQ_SERVICE_T *)handle; ++ VCHIQ_STATE_T *state; ++ int slot_index; ++ int msgid; ++ ++ if (service == NULL) ++ return; ++ ++ state = service->state; ++ ++ slot_index = SLOT_INDEX_FROM_DATA(state, (void *)header); ++ ++ if ((slot_index >= state->remote->slot_first) && ++ (slot_index <= state->remote->slot_last) && ++ ((msgid = header->msgid) & VCHIQ_MSGID_CLAIMED)) ++ { ++ VCHIQ_SLOT_INFO_T *slot_info = SLOT_INFO_FROM_INDEX(state, slot_index); ++ ++ /* Rewrite the message header to prevent a double release */ ++ header->msgid = msgid & ~VCHIQ_MSGID_CLAIMED; ++ ++ release_slot(state, slot_info); ++ } ++} ++ ++int ++vchiq_get_client_id(VCHIQ_SERVICE_HANDLE_T handle) ++{ ++ VCHIQ_SERVICE_T *service = (VCHIQ_SERVICE_T *)handle; ++ return service ? service->client_id : 0; ++} ++ ++VCHIQ_STATUS_T ++vchiq_get_config(VCHIQ_INSTANCE_T instance, ++ int config_size, VCHIQ_CONFIG_T *pconfig) ++{ ++ VCHIQ_CONFIG_T config; ++ ++ vcos_unused(instance); ++ ++ config.max_msg_size = VCHIQ_MAX_MSG_SIZE; ++ config.bulk_threshold = VCHIQ_MAX_MSG_SIZE; ++ config.max_outstanding_bulks = VCHIQ_NUM_SERVICE_BULKS; ++ config.max_services = VCHIQ_MAX_SERVICES; ++ config.version = VCHIQ_VERSION; ++ config.version_min = VCHIQ_VERSION_MIN; ++ ++ if (config_size > sizeof(VCHIQ_CONFIG_T)) ++ return VCHIQ_ERROR; ++ ++ memcpy(pconfig, &config, vcos_min(config_size, sizeof(VCHIQ_CONFIG_T))); ++ ++ return VCHIQ_SUCCESS; ++} ++ ++VCHIQ_STATUS_T ++vchiq_set_service_option(VCHIQ_SERVICE_HANDLE_T handle, ++ VCHIQ_SERVICE_OPTION_T option, int value) ++{ ++ VCHIQ_SERVICE_T *service = (VCHIQ_SERVICE_T *)handle; ++ VCHIQ_STATUS_T status = VCHIQ_ERROR; ++ ++ if (service) ++ { ++ switch (option) ++ { ++ case VCHIQ_SERVICE_OPTION_AUTOCLOSE: ++ service->auto_close = value; ++ status = VCHIQ_SUCCESS; ++ break; ++ ++ default: ++ break; ++ } ++ } ++ ++ return status; ++} ++ ++void ++vchiq_dump_shared_state(void *dump_context, VCHIQ_STATE_T *state, ++ VCHIQ_SHARED_STATE_T *shared, const char *label) ++{ ++ static const char *const debug_names[] = ++ { ++ "", ++ "SLOT_HANDLER_COUNT", ++ "SLOT_HANDLER_LINE", ++ "PARSE_LINE", ++ "PARSE_HEADER", ++ "PARSE_MSGID", ++ "AWAIT_COMPLETION_LINE", ++ "DEQUEUE_MESSAGE_LINE", ++ "SERVICE_CALLBACK_LINE", ++ "MSG_QUEUE_FULL_COUNT", ++ "COMPLETION_QUEUE_FULL_COUNT" ++ }; ++ int i; ++ ++ char buf[80]; ++ int len; ++ len = vcos_snprintf(buf, sizeof(buf), ++ " %s: slots %d-%d tx_pos=%x recycle=%x", ++ label, shared->slot_first, shared->slot_last, ++ shared->tx_pos, shared->slot_queue_recycle); ++ vchiq_dump(dump_context, buf, len + 1); ++ ++ len = vcos_snprintf(buf, sizeof(buf), ++ " Slots claimed:"); ++ vchiq_dump(dump_context, buf, len + 1); ++ ++ for (i = shared->slot_first; i <= shared->slot_last; i++) ++ { ++ VCHIQ_SLOT_INFO_T slot_info = *SLOT_INFO_FROM_INDEX(state, i); ++ if (slot_info.use_count != slot_info.release_count) ++ { ++ len = vcos_snprintf(buf, sizeof(buf), ++ " %d: %d/%d", i, slot_info.use_count, slot_info.release_count); ++ vchiq_dump(dump_context, buf, len + 1); ++ } ++ } ++ ++ for (i = 1; i < shared->debug[DEBUG_ENTRIES]; i++) ++ { ++ len = vcos_snprintf(buf, sizeof(buf), " DEBUG: %s = %d(%x)", ++ debug_names[i], shared->debug[i], shared->debug[i]); ++ vchiq_dump(dump_context, buf, len + 1); ++ } ++} ++ ++void ++vchiq_dump_state(void *dump_context, VCHIQ_STATE_T *state) ++{ ++ char buf[80]; ++ int len; ++ int i; ++ ++ len = vcos_snprintf(buf, sizeof(buf), "State %d: %s", state->id, ++ conn_state_names[state->conn_state]); ++ vchiq_dump(dump_context, buf, len + 1); ++ ++ len = vcos_snprintf(buf, sizeof(buf), ++ " tx_pos=%x(@%x), rx_pos=%x(@%x)", ++ state->id, state->local->tx_pos, ++ (uint32_t)state->tx_data + (state->local_tx_pos & VCHIQ_SLOT_MASK), ++ state->rx_pos, ++ (uint32_t)state->rx_data + (state->rx_pos & VCHIQ_SLOT_MASK)); ++ vchiq_dump(dump_context, buf, len + 1); ++ ++ len = vcos_snprintf(buf, sizeof(buf), ++ " Version: %d (min %d)", ++ VCHIQ_VERSION, VCHIQ_VERSION_MIN); ++ vchiq_dump(dump_context, buf, len + 1); ++ ++ if (VCHIQ_ENABLE_STATS) ++ { ++ len = vcos_snprintf(buf, sizeof(buf), ++ " Stats: ctrl_tx_count=%d, ctrl_rx_count=%d, error_count=%d", ++ state->stats.ctrl_tx_count, state->stats.ctrl_rx_count, ++ state->stats.slot_stalls); ++ vchiq_dump(dump_context, buf, len + 1); ++ } ++ ++ len = vcos_snprintf(buf, sizeof(buf), ++ " Slots: %d available, %d recyclable, %d stalls", ++ state->slot_queue_available - SLOT_QUEUE_INDEX_FROM_POS(state->local_tx_pos), ++ state->local->slot_queue_recycle - state->slot_queue_available, ++ state->stats.slot_stalls); ++ vchiq_dump(dump_context, buf, len + 1); ++ ++ vchiq_dump_platform_state(dump_context); ++ ++ vchiq_dump_shared_state(dump_context, state, state->local, "Local"); ++ vchiq_dump_shared_state(dump_context, state, state->remote, "Remote"); ++ ++ vchiq_dump_platform_instances(dump_context); ++ ++ for (i = 0; i < state->unused_service; i++) { ++ VCHIQ_SERVICE_T *service = state->services[i]; ++ ++ if (service && (service->srvstate != VCHIQ_SRVSTATE_FREE)) ++ vchiq_dump_service_state(dump_context, service); ++ } ++} ++ ++void ++vchiq_dump_service_state(void *dump_context, VCHIQ_SERVICE_T *service) ++{ ++ char buf[80]; ++ int len; ++ ++ len = vcos_snprintf(buf, sizeof(buf), "Service %d: %s", ++ service->localport, srvstate_names[service->srvstate]); ++ ++ if (service->srvstate != VCHIQ_SRVSTATE_FREE) ++ { ++ char remoteport[30]; ++ VCHIQ_SERVICE_QUOTA_T *service_quota = ++ &service->state->service_quotas[service->localport]; ++ int fourcc = service->base.fourcc; ++ if (service->remoteport != VCHIQ_PORT_FREE) ++ { ++ int len2 = vcos_snprintf(remoteport, sizeof(remoteport), "%d", ++ service->remoteport); ++ if (service->public_fourcc != VCHIQ_FOURCC_INVALID) ++ vcos_snprintf(remoteport + len2, sizeof(remoteport) - len2, ++ " (client %x)", service->client_id); ++ } ++ else ++ vcos_strcpy(remoteport, "n/a"); ++ ++ len += vcos_snprintf(buf + len, sizeof(buf) - len, ++ " '%c%c%c%c' remote %s (slot use %d/%d)", ++ VCHIQ_FOURCC_AS_4CHARS(fourcc), ++ remoteport, ++ service_quota->slot_use_count, ++ service_quota->slot_quota); ++ ++ if (VCHIQ_ENABLE_STATS) ++ { ++ vchiq_dump(dump_context, buf, len + 1); ++ ++ len = vcos_snprintf(buf, sizeof(buf), ++ " Ctrl: tx_count=%d, tx_bytes=%" PRIu64 ", rx_count=%d, rx_bytes=%" PRIu64, ++ service->stats.ctrl_tx_count, service->stats.ctrl_tx_bytes, ++ service->stats.ctrl_rx_count, service->stats.ctrl_rx_bytes); ++ vchiq_dump(dump_context, buf, len + 1); ++ ++ len = vcos_snprintf(buf, sizeof(buf), ++ " Bulk: tx_count=%d, tx_bytes=%" PRIu64 ", rx_count=%d, rx_bytes=%" PRIu64, ++ service->stats.bulk_tx_count, service->stats.bulk_tx_bytes, ++ service->stats.bulk_rx_count, service->stats.bulk_rx_bytes); ++ vchiq_dump(dump_context, buf, len + 1); ++ ++ len = vcos_snprintf(buf, sizeof(buf), ++ " %d quota stalls, %d slot stalls, %d bulk stalls, %d aborted, %d errors", ++ service->stats.quota_stalls, service->stats.slot_stalls, ++ service->stats.bulk_stalls, service->stats.bulk_aborted_count, ++ service->stats.error_count); ++ } ++ } ++ ++ vchiq_dump(dump_context, buf, len + 1); ++ ++ vchiq_dump_platform_service_state(dump_context, service); ++} +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_core.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_core.h 2013-07-26 19:32:00.000000000 +0000 +@@ -0,0 +1,480 @@ ++/* ++ * Copyright (c) 2010-2011 Broadcom Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++#ifndef VCHIQ_CORE_H ++#define VCHIQ_CORE_H ++ ++#include "vchiq_cfg.h" ++ ++#include "vchiq.h" ++ ++#define IS_POW2(x) (x && ((x & (x - 1)) == 0)) ++ ++/* Ensure that the slot size and maximum number of slots are powers of 2 */ ++vcos_static_assert(IS_POW2(VCHIQ_SLOT_SIZE)); ++vcos_static_assert(IS_POW2(VCHIQ_MAX_SLOTS)); ++vcos_static_assert(IS_POW2(VCHIQ_MAX_SLOTS_PER_SIDE)); ++ ++#define VCHIQ_SLOT_MASK (VCHIQ_SLOT_SIZE - 1) ++#define VCHIQ_SLOT_QUEUE_MASK (VCHIQ_MAX_SLOTS_PER_SIDE - 1) ++#define VCHIQ_SLOT_ZERO_SLOTS ((sizeof(VCHIQ_SLOT_ZERO_T) + \ ++ VCHIQ_SLOT_SIZE - 1) / VCHIQ_SLOT_SIZE) ++ ++#define VCHIQ_MSG_PADDING 0 // - ++#define VCHIQ_MSG_CONNECT 1 // - ++#define VCHIQ_MSG_OPEN 2 // + (srcport, -), fourcc, client_id ++#define VCHIQ_MSG_OPENACK 3 // + (srcport, dstport) ++#define VCHIQ_MSG_CLOSE 4 // + (srcport, dstport) ++#define VCHIQ_MSG_DATA 5 // + (srcport, dstport) ++#define VCHIQ_MSG_BULK_RX 6 // + (srcport, dstport), data, size ++#define VCHIQ_MSG_BULK_TX 7 // + (srcport, dstport), data, size ++#define VCHIQ_MSG_BULK_RX_DONE 8 // + (srcport, dstport), actual ++#define VCHIQ_MSG_BULK_TX_DONE 9 // + (srcport, dstport), actual ++#define VCHIQ_MSG_PAUSE 10 // - ++#define VCHIQ_MSG_RESUME 11 // - ++ ++#define VCHIQ_PORT_MAX (VCHIQ_MAX_SERVICES - 1) ++#define VCHIQ_PORT_FREE 0x1000 ++#define VCHIQ_PORT_IS_VALID(port) (port < VCHIQ_PORT_FREE) ++#define VCHIQ_MAKE_MSG(type,srcport,dstport) ((type<<24) | (srcport<<12) | (dstport<<0)) ++#define VCHIQ_MSG_TYPE(msgid) ((unsigned int)msgid >> 24) ++#define VCHIQ_MSG_SRCPORT(msgid) (unsigned short)(((unsigned int)msgid >> 12) & 0xfff) ++#define VCHIQ_MSG_DSTPORT(msgid) ((unsigned short)msgid & 0xfff) ++ ++#define VCHIQ_FOURCC_AS_4CHARS(fourcc) \ ++ ((fourcc) >> 24) & 0xff, \ ++ ((fourcc) >> 16) & 0xff, \ ++ ((fourcc) >> 8) & 0xff, \ ++ ((fourcc) ) & 0xff ++ ++/* Ensure the fields are wide enough */ ++vcos_static_assert(VCHIQ_MSG_SRCPORT(VCHIQ_MAKE_MSG(0,0,VCHIQ_PORT_MAX)) == 0); ++vcos_static_assert(VCHIQ_MSG_TYPE(VCHIQ_MAKE_MSG(0,VCHIQ_PORT_MAX,0)) == 0); ++vcos_static_assert((unsigned int)VCHIQ_PORT_MAX < (unsigned int)VCHIQ_PORT_FREE); ++ ++#define VCHIQ_MSGID_PADDING VCHIQ_MAKE_MSG(VCHIQ_MSG_PADDING,0,0) ++#define VCHIQ_MSGID_CLAIMED 0x40000000 ++ ++#define VCHIQ_FOURCC_INVALID 0x00000000 ++#define VCHIQ_FOURCC_IS_LEGAL(fourcc) (fourcc != VCHIQ_FOURCC_INVALID) ++ ++#define VCHIQ_BULK_ACTUAL_ABORTED -1 ++ ++typedef uint32_t BITSET_T; ++ ++vcos_static_assert((sizeof(BITSET_T) * 8) == 32); ++ ++#define BITSET_SIZE(b) ((b + 31) >> 5) ++#define BITSET_WORD(b) (b >> 5) ++#define BITSET_BIT(b) (1 << (b & 31)) ++#define BITSET_ZERO(bs) memset(bs, 0, sizeof(bs)) ++#define BITSET_IS_SET(bs, b) (bs[BITSET_WORD(b)] & BITSET_BIT(b)) ++#define BITSET_SET(bs, b) (bs[BITSET_WORD(b)] |= BITSET_BIT(b)) ++#define BITSET_CLR(bs, b) (bs[BITSET_WORD(b)] &= ~BITSET_BIT(b)) ++ ++#if VCHIQ_ENABLE_STATS ++#define VCHIQ_STATS_INC(state, stat) (state->stats. stat ++) ++#define VCHIQ_SERVICE_STATS_INC(service, stat) (service->stats. stat ++) ++#define VCHIQ_SERVICE_STATS_ADD(service, stat, addend) (service->stats. stat += addend) ++#else ++#define VCHIQ_STATS_INC(state, stat) ((void)0) ++#define VCHIQ_SERVICE_STATS_INC(service, stat) ((void)0) ++#define VCHIQ_SERVICE_STATS_ADD(service, stat, addend) ((void)0) ++#endif ++ ++enum ++{ ++ DEBUG_ENTRIES, ++#if VCHIQ_ENABLE_DEBUG ++ DEBUG_SLOT_HANDLER_COUNT, ++ DEBUG_SLOT_HANDLER_LINE, ++ DEBUG_PARSE_LINE, ++ DEBUG_PARSE_HEADER, ++ DEBUG_PARSE_MSGID, ++ DEBUG_AWAIT_COMPLETION_LINE, ++ DEBUG_DEQUEUE_MESSAGE_LINE, ++ DEBUG_SERVICE_CALLBACK_LINE, ++ DEBUG_MSG_QUEUE_FULL_COUNT, ++ DEBUG_COMPLETION_QUEUE_FULL_COUNT, ++#endif ++ DEBUG_MAX ++}; ++ ++#if VCHIQ_ENABLE_DEBUG ++ ++#define DEBUG_INITIALISE(local) volatile int *debug_ptr = (local)->debug; ++#define DEBUG_TRACE(d) debug_ptr[DEBUG_ ## d] = __LINE__ ++#define DEBUG_VALUE(d,v) debug_ptr[DEBUG_ ## d] = (v) ++#define DEBUG_COUNT(d) debug_ptr[DEBUG_ ## d]++ ++ ++#else /* VCHIQ_ENABLE_DEBUG */ ++ ++#define DEBUG_INITIALISE(local) ++#define DEBUG_TRACE(d) ++#define DEBUG_VALUE(d,v) ++#define DEBUG_COUNT(d) ++ ++#endif /* VCHIQ_ENABLE_DEBUG */ ++ ++typedef enum ++{ ++ VCHIQ_CONNSTATE_DISCONNECTED, ++ VCHIQ_CONNSTATE_CONNECTED, ++ VCHIQ_CONNSTATE_PAUSING, ++ VCHIQ_CONNSTATE_PAUSE_SENT, ++ VCHIQ_CONNSTATE_PAUSED, ++ VCHIQ_CONNSTATE_RESUMING ++} VCHIQ_CONNSTATE_T; ++ ++enum ++{ ++ VCHIQ_SRVSTATE_FREE, ++ VCHIQ_SRVSTATE_HIDDEN, ++ VCHIQ_SRVSTATE_LISTENING, ++ VCHIQ_SRVSTATE_OPENING, ++ VCHIQ_SRVSTATE_OPEN, ++ VCHIQ_SRVSTATE_CLOSESENT, ++ VCHIQ_SRVSTATE_CLOSING, ++ VCHIQ_SRVSTATE_CLOSEWAIT ++}; ++ ++enum ++{ ++ VCHIQ_POLL_TERMINATE, ++ VCHIQ_POLL_TXNOTIFY, ++ VCHIQ_POLL_RXNOTIFY, ++ VCHIQ_POLL_COUNT ++}; ++ ++typedef enum ++{ ++ VCHIQ_BULK_TRANSMIT, ++ VCHIQ_BULK_RECEIVE ++} VCHIQ_BULK_DIR_T; ++ ++typedef struct vchiq_bulk_struct { ++ short mode; ++ short dir; ++ void *userdata; ++ VCHI_MEM_HANDLE_T handle; ++ void *data; ++ int size; ++ void *remote_data; ++ int remote_size; ++ int actual; ++} VCHIQ_BULK_T; ++ ++typedef struct vchiq_bulk_queue_struct { ++ int local_insert; /* Where to insert the next local bulk */ ++ int remote_insert; /* Where to insert the next remote bulk (master) */ ++ int process; /* Bulk to transfer next */ ++ int remote_notify; /* Bulk to notify the remote client of next (master) */ ++ int remove; /* Bulk to notify the local client of, and remove, next */ ++ VCHIQ_BULK_T bulks[VCHIQ_NUM_SERVICE_BULKS]; ++} VCHIQ_BULK_QUEUE_T; ++ ++typedef struct remote_event_struct { ++ volatile int armed; ++ volatile int fired; ++ VCOS_EVENT_T * event; ++} REMOTE_EVENT_T; ++ ++typedef struct vchiq_state_struct VCHIQ_STATE_T; ++ ++typedef struct vchiq_slot_struct { ++ char data[VCHIQ_SLOT_SIZE]; ++} VCHIQ_SLOT_T; ++ ++typedef struct vchiq_slot_info_struct { ++ /* Use two counters rather than one to avoid the need for a mutex. */ ++ volatile short use_count; ++ volatile short release_count; ++} VCHIQ_SLOT_INFO_T; ++ ++typedef struct vchiq_service_struct { ++ VCHIQ_SERVICE_BASE_T base; ++ volatile int srvstate; ++ unsigned int localport; ++ unsigned int remoteport; ++ int public_fourcc; ++ int client_id; ++ int auto_close; ++ VCOS_ATOMIC_FLAGS_T poll_flags; ++ short version; ++ short version_min; ++ ++ VCHIQ_STATE_T *state; ++ VCHIQ_INSTANCE_T instance; ++ ++ int service_use_count; ++ ++ VCHIQ_BULK_QUEUE_T bulk_tx; ++ VCHIQ_BULK_QUEUE_T bulk_rx; ++ ++ VCOS_EVENT_T remove_event; ++ VCOS_EVENT_T bulk_remove_event; ++ VCOS_MUTEX_T bulk_mutex; ++ ++ struct service_stats_struct ++ { ++ int quota_stalls; ++ int slot_stalls; ++ int bulk_stalls; ++ int error_count; ++ int ctrl_tx_count; ++ int ctrl_rx_count; ++ int bulk_tx_count; ++ int bulk_rx_count; ++ int bulk_aborted_count; ++ uint64_t ctrl_tx_bytes; ++ uint64_t ctrl_rx_bytes; ++ uint64_t bulk_tx_bytes; ++ uint64_t bulk_rx_bytes; ++ } stats; ++} VCHIQ_SERVICE_T; ++ ++/* The quota information is outside VCHIQ_SERVICE_T so that it can be ++ statically allocated, since for accounting reasons a service's slot ++ usage is carried over between users of the same port number. ++ */ ++typedef struct vchiq_service_quota_struct { ++ int slot_quota; ++ int slot_use_count; ++ VCOS_EVENT_T quota_event; ++ int previous_tx_index; ++} VCHIQ_SERVICE_QUOTA_T; ++ ++typedef struct vchiq_shared_state_struct { ++ ++ /* A non-zero value here indicates that the content is valid. */ ++ int initialised; ++ ++ /* The first and last (inclusive) slots allocated to the owner. */ ++ int slot_first; ++ int slot_last; ++ ++ /* Signalling this event indicates that owner's slot handler thread should ++ run. */ ++ REMOTE_EVENT_T trigger; ++ ++ /* Indicates the byte position within the stream where the next message ++ will be written. The least significant bits are an index into the slot. ++ The next bits are the index of the slot in slot_queue. */ ++ volatile int tx_pos; ++ ++ /* This event should be signalled when a slot is recycled. */ ++ REMOTE_EVENT_T recycle; ++ ++ /* The slot_queue index where the next recycled slot will be written. */ ++ volatile int slot_queue_recycle; ++ ++ /* A circular buffer of slot indexes. */ ++ int slot_queue[VCHIQ_MAX_SLOTS_PER_SIDE]; ++ ++ /* Debugging state */ ++ volatile int debug[DEBUG_MAX]; ++} VCHIQ_SHARED_STATE_T; ++ ++typedef struct vchiq_slot_zero_struct { ++ int magic; ++ short version; ++ short version_min; ++ int slot_zero_size; ++ int slot_size; ++ int max_slots; ++ int max_slots_per_side; ++ int platform_data[2]; ++ VCHIQ_SHARED_STATE_T master; ++ VCHIQ_SHARED_STATE_T slave; ++ VCHIQ_SLOT_INFO_T slots[VCHIQ_MAX_SLOTS]; ++} VCHIQ_SLOT_ZERO_T; ++ ++struct vchiq_state_struct { ++ int id; ++ int initialised; ++ VCHIQ_CONNSTATE_T conn_state; ++ int is_master; ++ ++ VCHIQ_SHARED_STATE_T *local; ++ VCHIQ_SHARED_STATE_T *remote; ++ VCHIQ_SLOT_T *slot_data; ++ ++ int default_slot_quota; ++ ++ VCOS_EVENT_T connect; // event indicating connect message received ++ VCOS_MUTEX_T mutex; // mutex protecting services ++ VCHIQ_INSTANCE_T *instance; ++ ++ VCOS_THREAD_T slot_handler_thread; // processes incoming messages ++ VCOS_THREAD_T recycle_thread; // processes recycled slots ++ VCOS_THREAD_T lp_thread; // processes low priority messages (eg suspend) ++ ++ /* Local implementation of the trigger remote event */ ++ VCOS_EVENT_T trigger_event; ++ ++ /* Local implementation of the recycle remote event */ ++ VCOS_EVENT_T recycle_event; ++ ++ VCOS_EVENT_T lp_evt; ++ ++ char *tx_data; ++ char *rx_data; ++ VCHIQ_SLOT_INFO_T *rx_info; ++ ++ VCOS_MUTEX_T slot_mutex; ++ ++ VCOS_MUTEX_T recycle_mutex; ++ ++ VCOS_MUTEX_T suspend_resume_mutex; ++ VCOS_MUTEX_T use_count_mutex; ++ ++ /* Global use count for videocore. ++ * This is equal to the sum of the use counts for all services. When this hits ++ * zero the videocore suspend procedure will be initiated. */ ++ int videocore_use_count; ++ ++ /* Flag to indicate whether videocore is currently suspended */ ++ int videocore_suspended; ++ ++ /* Indicates the byte position within the stream from where the next message ++ will be read. The least significant bits are an index into the slot. ++ The next bits are the index of the slot in remote->slot_queue. */ ++ int rx_pos; ++ ++ /* A cached copy of local->tx_pos. Only write to local->tx_pos, and read ++ from remote->tx_pos. */ ++ int local_tx_pos; ++ ++ /* The slot_queue index of the slot to become available next. */ ++ int slot_queue_available; ++ ++ /* A flag to indicate if any poll has been requested */ ++ int poll_needed; ++ ++ /* An array of bit sets indicating which services must be polled. */ ++ VCOS_ATOMIC_FLAGS_T poll_services[BITSET_SIZE(VCHIQ_MAX_SERVICES)]; ++ ++ /* The number of the first unused service */ ++ int unused_service; ++ ++ /* Signalled when a free slot becomes available. */ ++ VCOS_EVENT_T slot_available_event; ++ ++ VCOS_EVENT_T slot_remove_event; ++ ++ struct state_stats_struct ++ { ++ int slot_stalls; ++ int ctrl_tx_count; ++ int ctrl_rx_count; ++ int error_count; ++ } stats; ++ ++ VCHIQ_SERVICE_T *services[VCHIQ_MAX_SERVICES]; ++ VCHIQ_SERVICE_QUOTA_T service_quotas[VCHIQ_MAX_SERVICES]; ++ VCHIQ_SLOT_INFO_T slot_info[VCHIQ_MAX_SLOTS]; ++}; ++ ++extern VCHIQ_SLOT_ZERO_T * ++vchiq_init_slots(void *mem_base, int mem_size); ++ ++extern VCHIQ_STATUS_T ++vchiq_init_state(VCHIQ_STATE_T *state, VCHIQ_SLOT_ZERO_T *slot_zero, int is_master); ++ ++extern VCHIQ_STATUS_T ++vchiq_connect_internal(VCHIQ_STATE_T *state, VCHIQ_INSTANCE_T instance); ++ ++extern VCHIQ_SERVICE_T * ++vchiq_add_service_internal(VCHIQ_STATE_T *state, ++ const VCHIQ_SERVICE_PARAMS_T *params, int srvstate, ++ VCHIQ_INSTANCE_T instance); ++ ++extern VCHIQ_STATUS_T ++vchiq_open_service_internal(VCHIQ_SERVICE_T *service, int client_id); ++ ++extern VCHIQ_STATUS_T ++vchiq_close_service_internal(VCHIQ_SERVICE_T *service, int close_recvd); ++ ++extern void ++vchiq_terminate_service_internal(VCHIQ_SERVICE_T *service); ++ ++extern void ++vchiq_free_service_internal(VCHIQ_SERVICE_T *service); ++ ++extern VCHIQ_STATUS_T ++vchiq_shutdown_internal(VCHIQ_STATE_T *state, VCHIQ_INSTANCE_T instance); ++ ++extern VCHIQ_STATUS_T ++vchiq_pause_internal(VCHIQ_STATE_T *state); ++ ++extern VCHIQ_STATUS_T ++vchiq_resume_internal(VCHIQ_STATE_T *state); ++ ++extern void ++remote_event_pollall(VCHIQ_STATE_T *state); ++ ++extern VCHIQ_STATUS_T ++vchiq_bulk_transfer(VCHIQ_SERVICE_T *service, ++ VCHI_MEM_HANDLE_T memhandle, void *offset, int size, void *userdata, ++ VCHIQ_BULK_MODE_T mode, VCHIQ_BULK_DIR_T dir); ++ ++extern void ++vchiq_dump_state(void *dump_context, VCHIQ_STATE_T *state); ++ ++extern void ++vchiq_dump_service_state(void *dump_context, VCHIQ_SERVICE_T *service); ++ ++/* The following functions are called from vchiq_core, and external ++ implementations must be provided. */ ++ ++extern VCHIQ_STATUS_T ++vchiq_prepare_bulk_data(VCHIQ_BULK_T *bulk, ++ VCHI_MEM_HANDLE_T memhandle, void *offset, int size, int dir); ++ ++extern void ++vchiq_transfer_bulk(VCHIQ_BULK_T *bulk); ++ ++extern void ++vchiq_complete_bulk(VCHIQ_BULK_T *bulk); ++ ++extern VCHIQ_STATUS_T ++vchiq_copy_from_user(void *dst, const void *src, int size); ++ ++extern void ++remote_event_signal(REMOTE_EVENT_T *event); ++ ++extern void ++vchiq_platform_paused(VCHIQ_STATE_T *state); ++ ++extern void ++vchiq_platform_resumed(VCHIQ_STATE_T *state); ++ ++extern void ++vchiq_dump(void *dump_context, const char *str, int len); ++ ++extern void ++vchiq_dump_platform_state(void *dump_context); ++ ++extern void ++vchiq_dump_platform_instances(void *dump_context); ++ ++extern void ++vchiq_dump_platform_service_state(void *dump_context, ++ VCHIQ_SERVICE_T *service); ++ ++#endif +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_if.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_if.h 2013-07-26 19:32:00.000000000 +0000 +@@ -0,0 +1,148 @@ ++/* ++ * Copyright (c) 2010-2011 Broadcom Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++#ifndef VCHIQ_IF_H ++#define VCHIQ_IF_H ++ ++#include "interface/vchi/vchi_mh.h" ++ ++#define VCHIQ_SLOT_SIZE 4096 ++#define VCHIQ_MAX_MSG_SIZE (VCHIQ_SLOT_SIZE - sizeof(VCHIQ_HEADER_T)) ++#define VCHIQ_CHANNEL_SIZE VCHIQ_MAX_MSG_SIZE /* For backwards compatibility */ ++ ++#define VCHIQ_MAKE_FOURCC(x0, x1, x2, x3) (((x0) << 24) | ((x1) << 16) | ((x2) << 8) | (x3)) ++#define VCHIQ_GET_SERVICE_USERDATA(service) (service->userdata) ++#define VCHIQ_GET_SERVICE_FOURCC(service) (service->fourcc) ++ ++typedef enum { ++ VCHIQ_SERVICE_OPENED, // service, -, - ++ VCHIQ_SERVICE_CLOSED, // service, -, - ++ VCHIQ_MESSAGE_AVAILABLE, // service, header, - ++ VCHIQ_BULK_TRANSMIT_DONE, // service, -, bulk_userdata ++ VCHIQ_BULK_RECEIVE_DONE, // service, -, bulk_userdata ++ VCHIQ_BULK_TRANSMIT_ABORTED, // service, -, bulk_userdata ++ VCHIQ_BULK_RECEIVE_ABORTED // service, -, bulk_userdata ++} VCHIQ_REASON_T; ++ ++typedef enum ++{ ++ VCHIQ_ERROR = -1, ++ VCHIQ_SUCCESS = 0, ++ VCHIQ_RETRY = 1 ++} VCHIQ_STATUS_T; ++ ++typedef enum ++{ ++ VCHIQ_BULK_MODE_CALLBACK, ++ VCHIQ_BULK_MODE_BLOCKING, ++ VCHIQ_BULK_MODE_NOCALLBACK ++} VCHIQ_BULK_MODE_T; ++ ++typedef enum ++{ ++ VCHIQ_SERVICE_OPTION_AUTOCLOSE ++} VCHIQ_SERVICE_OPTION_T; ++ ++#ifdef __HIGHC__ ++/* Allow zero-sized arrays without warnings */ ++#pragma warning (push) ++#pragma warning (disable : 4200) ++#endif ++ ++typedef struct vchiq_header_struct { ++ /* The message identifier - opaque to applications. */ ++ int msgid; ++ ++ /* Size of message data. */ ++ unsigned int size; ++ ++ char data[0]; /* message */ ++} VCHIQ_HEADER_T; ++ ++#ifdef __HIGHC__ ++#pragma warning (pop) ++#endif ++ ++typedef struct { ++ const void *data; ++ int size; ++} VCHIQ_ELEMENT_T; ++ ++typedef const struct vchiq_service_base_struct *VCHIQ_SERVICE_HANDLE_T; ++ ++typedef VCHIQ_STATUS_T (*VCHIQ_CALLBACK_T)(VCHIQ_REASON_T, VCHIQ_HEADER_T *, VCHIQ_SERVICE_HANDLE_T, void *); ++ ++typedef struct vchiq_service_base_struct { ++ int fourcc; ++ VCHIQ_CALLBACK_T callback; ++ void *userdata; ++} VCHIQ_SERVICE_BASE_T; ++ ++typedef struct vchiq_service_params_struct { ++ int fourcc; ++ VCHIQ_CALLBACK_T callback; ++ void *userdata; ++ short version; /* Increment for non-trivial changes */ ++ short version_min; /* Update for incompatible changes */ ++} VCHIQ_SERVICE_PARAMS_T; ++ ++typedef struct vchiq_config_struct { ++ int max_msg_size; ++ int bulk_threshold; /* The message size aboce which it is better to use ++ a bulk transfer (<= max_msg_size) */ ++ int max_outstanding_bulks; ++ int max_services; ++ short version; /* The version of VCHIQ */ ++ short version_min; /* The minimum compatible version of VCHIQ */ ++} VCHIQ_CONFIG_T; ++ ++typedef struct vchiq_instance_struct *VCHIQ_INSTANCE_T; ++ ++extern VCHIQ_STATUS_T vchiq_initialise(VCHIQ_INSTANCE_T *pinstance); ++extern VCHIQ_STATUS_T vchiq_shutdown(VCHIQ_INSTANCE_T instance); ++extern VCHIQ_STATUS_T vchiq_connect(VCHIQ_INSTANCE_T instance); ++extern VCHIQ_STATUS_T vchiq_add_service(VCHIQ_INSTANCE_T instance, int fourcc, VCHIQ_CALLBACK_T callback, void *userdata, VCHIQ_SERVICE_HANDLE_T *pservice); ++extern VCHIQ_STATUS_T vchiq_open_service(VCHIQ_INSTANCE_T instance, int fourcc, VCHIQ_CALLBACK_T callback, void *userdata, VCHIQ_SERVICE_HANDLE_T *pservice); ++extern VCHIQ_STATUS_T vchiq_add_service_params(VCHIQ_INSTANCE_T instance, ++ const VCHIQ_SERVICE_PARAMS_T *params, ++ VCHIQ_SERVICE_HANDLE_T *pservice); ++extern VCHIQ_STATUS_T vchiq_open_service_params(VCHIQ_INSTANCE_T instance, ++ const VCHIQ_SERVICE_PARAMS_T *params, ++ VCHIQ_SERVICE_HANDLE_T *pservice); ++extern VCHIQ_STATUS_T vchiq_close_service(VCHIQ_SERVICE_HANDLE_T service); ++extern VCHIQ_STATUS_T vchiq_remove_service(VCHIQ_SERVICE_HANDLE_T service); ++extern VCHIQ_STATUS_T vchiq_use_service(VCHIQ_SERVICE_HANDLE_T service); ++extern VCHIQ_STATUS_T vchiq_release_service(VCHIQ_SERVICE_HANDLE_T service); ++ ++extern VCHIQ_STATUS_T vchiq_queue_message(VCHIQ_SERVICE_HANDLE_T service, const VCHIQ_ELEMENT_T *elements, int count); ++extern void vchiq_release_message(VCHIQ_SERVICE_HANDLE_T service, VCHIQ_HEADER_T *header); ++extern VCHIQ_STATUS_T vchiq_queue_bulk_transmit(VCHIQ_SERVICE_HANDLE_T service, const void *data, int size, void *userdata); ++extern VCHIQ_STATUS_T vchiq_queue_bulk_receive(VCHIQ_SERVICE_HANDLE_T service, void *data, int size, void *userdata); ++extern VCHIQ_STATUS_T vchiq_queue_bulk_transmit_handle(VCHIQ_SERVICE_HANDLE_T service, VCHI_MEM_HANDLE_T handle, const void *offset, int size, void *userdata); ++extern VCHIQ_STATUS_T vchiq_queue_bulk_receive_handle(VCHIQ_SERVICE_HANDLE_T service, VCHI_MEM_HANDLE_T handle, void *offset, int size, void *userdata); ++extern VCHIQ_STATUS_T vchiq_bulk_transmit(VCHIQ_SERVICE_HANDLE_T service, const void *data, int size, void *userdata, VCHIQ_BULK_MODE_T mode); ++extern VCHIQ_STATUS_T vchiq_bulk_receive(VCHIQ_SERVICE_HANDLE_T service, void *data, int size, void *userdata, VCHIQ_BULK_MODE_T mode); ++extern VCHIQ_STATUS_T vchiq_bulk_transmit_handle(VCHIQ_SERVICE_HANDLE_T service, VCHI_MEM_HANDLE_T handle, const void *offset, int size, void *userdata, VCHIQ_BULK_MODE_T mode); ++extern VCHIQ_STATUS_T vchiq_bulk_receive_handle(VCHIQ_SERVICE_HANDLE_T service, VCHI_MEM_HANDLE_T handle, void *offset, int size, void *userdata, VCHIQ_BULK_MODE_T mode); ++extern int vchiq_get_client_id(VCHIQ_SERVICE_HANDLE_T service); ++extern VCHIQ_STATUS_T vchiq_get_config(VCHIQ_INSTANCE_T instance, int config_size, VCHIQ_CONFIG_T *pconfig); ++extern VCHIQ_STATUS_T vchiq_set_service_option(VCHIQ_SERVICE_HANDLE_T service, VCHIQ_SERVICE_OPTION_T option, int value); ++ ++extern VCHIQ_STATUS_T vchiq_dump_phys_mem( VCHIQ_SERVICE_HANDLE_T service, void *ptr, size_t num_bytes ); ++ ++#endif /* VCHIQ_IF_H */ +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_ioctl.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_ioctl.h 2013-07-26 19:32:00.000000000 +0000 +@@ -0,0 +1,105 @@ ++/* ++ * Copyright (c) 2010-2011 Broadcom Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++#ifndef VCHIQ_IOCTLS_H ++#define VCHIQ_IOCTLS_H ++ ++#include ++#include "vchiq_if.h" ++ ++#define VCHIQ_IOC_MAGIC 0xc4 ++#define VCHIQ_INVALID_HANDLE -1 ++ ++typedef struct { ++ VCHIQ_SERVICE_PARAMS_T params; ++ int is_open; ++ int is_vchi; ++ int handle; /* OUT */ ++} VCHIQ_CREATE_SERVICE_T; ++ ++typedef struct { ++ int handle; ++ int count; ++ const VCHIQ_ELEMENT_T *elements; ++} VCHIQ_QUEUE_MESSAGE_T; ++ ++typedef struct { ++ int handle; ++ void *data; ++ int size; ++ void *userdata; ++ VCHIQ_BULK_MODE_T mode; ++} VCHIQ_QUEUE_BULK_TRANSFER_T; ++ ++typedef struct { ++ VCHIQ_REASON_T reason; ++ VCHIQ_HEADER_T *header; ++ void *service_userdata; ++ void *bulk_userdata; ++} VCHIQ_COMPLETION_DATA_T; ++ ++typedef struct { ++ int count; ++ VCHIQ_COMPLETION_DATA_T *buf; ++ int msgbufsize; ++ int msgbufcount; /* IN/OUT */ ++ void **msgbufs; ++} VCHIQ_AWAIT_COMPLETION_T; ++ ++typedef struct { ++ int handle; ++ int blocking; ++ int bufsize; ++ void *buf; ++} VCHIQ_DEQUEUE_MESSAGE_T; ++ ++typedef struct { ++ int config_size; ++ VCHIQ_CONFIG_T *pconfig; ++} VCHIQ_GET_CONFIG_T; ++ ++typedef struct { ++ int handle; ++ VCHIQ_SERVICE_OPTION_T option; ++ int value; ++} VCHIQ_SET_SERVICE_OPTION_T; ++ ++typedef struct { ++ void *virt_addr; ++ size_t num_bytes; ++} VCHIQ_DUMP_MEM_T; ++ ++#define VCHIQ_IOC_CONNECT _IO(VCHIQ_IOC_MAGIC, 0) ++#define VCHIQ_IOC_SHUTDOWN _IO(VCHIQ_IOC_MAGIC, 1) ++#define VCHIQ_IOC_CREATE_SERVICE _IOWR(VCHIQ_IOC_MAGIC, 2, VCHIQ_CREATE_SERVICE_T) ++#define VCHIQ_IOC_REMOVE_SERVICE _IO(VCHIQ_IOC_MAGIC, 3) ++#define VCHIQ_IOC_QUEUE_MESSAGE _IOW(VCHIQ_IOC_MAGIC, 4, VCHIQ_QUEUE_MESSAGE_T) ++#define VCHIQ_IOC_QUEUE_BULK_TRANSMIT _IOW(VCHIQ_IOC_MAGIC, 5, VCHIQ_QUEUE_BULK_TRANSFER_T) ++#define VCHIQ_IOC_QUEUE_BULK_RECEIVE _IOW(VCHIQ_IOC_MAGIC, 6, VCHIQ_QUEUE_BULK_TRANSFER_T) ++#define VCHIQ_IOC_AWAIT_COMPLETION _IOW(VCHIQ_IOC_MAGIC, 7, VCHIQ_AWAIT_COMPLETION_T) ++#define VCHIQ_IOC_DEQUEUE_MESSAGE _IOW(VCHIQ_IOC_MAGIC, 8, VCHIQ_DEQUEUE_MESSAGE_T) ++#define VCHIQ_IOC_GET_CLIENT_ID _IO(VCHIQ_IOC_MAGIC, 9) ++#define VCHIQ_IOC_GET_CONFIG _IOW(VCHIQ_IOC_MAGIC, 10, VCHIQ_GET_CONFIG_T) ++#define VCHIQ_IOC_CLOSE_SERVICE _IO(VCHIQ_IOC_MAGIC, 11) ++#define VCHIQ_IOC_USE_SERVICE _IO(VCHIQ_IOC_MAGIC, 12) ++#define VCHIQ_IOC_RELEASE_SERVICE _IO(VCHIQ_IOC_MAGIC, 13) ++#define VCHIQ_IOC_SET_SERVICE_OPTION _IOW(VCHIQ_IOC_MAGIC, 14, VCHIQ_SET_SERVICE_OPTION_T) ++#define VCHIQ_IOC_DUMP_PHYS_MEM _IOW(VCHIQ_IOC_MAGIC, 15, VCHIQ_DUMP_MEM_T) ++#define VCHIQ_IOC_MAX 15 ++ ++#endif +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_kern_lib.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_kern_lib.c 2013-07-26 19:32:00.000000000 +0000 +@@ -0,0 +1,297 @@ ++/***************************************************************************** ++* Copyright 2001 - 2011 Broadcom Corporation. All rights reserved. ++* ++* Unless you and Broadcom execute a separate written software license ++* agreement governing use of this software, this software is licensed to you ++* under the terms of the GNU General Public License version 2, available at ++* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). ++* ++* Notwithstanding the above, under no circumstances may you combine this ++* software in any way with any other Broadcom software provided under a ++* license other than the GPL, without Broadcom's express prior written ++* consent. ++*****************************************************************************/ ++ ++/* ---- Include Files ---------------------------------------------------- */ ++ ++#include ++#include ++ ++#include "vchiq_core.h" ++#include "vchiq_arm.h" ++#include "interface/vcos/vcos_logging.h" ++ ++/* ---- Public Variables ------------------------------------------------- */ ++ ++extern VCOS_LOG_CAT_T vchiq_core_log_category; ++#define VCOS_LOG_CATEGORY (&vchiq_core_log_category) ++ ++/* ---- Private Constants and Types -------------------------------------- */ ++ ++struct vchiq_instance_struct { ++ VCHIQ_STATE_T *state; ++ ++ int connected; ++}; ++ ++/**************************************************************************** ++* ++* vchiq_initialise ++* ++***************************************************************************/ ++ ++VCHIQ_STATUS_T vchiq_initialise( VCHIQ_INSTANCE_T *instanceOut ) ++{ ++ VCHIQ_STATUS_T status = VCHIQ_ERROR; ++ VCHIQ_STATE_T *state; ++ VCHIQ_INSTANCE_T instance = NULL; ++ ++ vcos_log_trace( "%s called", __func__ ); ++ ++ state = vchiq_get_state(); ++ if (!state) ++ { ++ printk( KERN_ERR "%s: videocore not initialized\n", __func__ ); ++ goto failed; ++ } ++ ++ instance = kzalloc( sizeof(*instance), GFP_KERNEL ); ++ if( !instance ) ++ { ++ printk( KERN_ERR "%s: error allocating vchiq instance\n", __func__ ); ++ goto failed; ++ } ++ ++ instance->connected = 0; ++ instance->state = state; ++ ++ *instanceOut = instance; ++ ++ status = VCHIQ_SUCCESS; ++ ++failed: ++ vcos_log_trace( "%s(%p): returning %d", __func__, instance, status ); ++ ++ return status; ++} ++ ++/**************************************************************************** ++* ++* vchiq_shutdown ++* ++***************************************************************************/ ++ ++VCHIQ_STATUS_T vchiq_shutdown( VCHIQ_INSTANCE_T instance ) ++{ ++ VCHIQ_STATUS_T status; ++ VCHIQ_STATE_T *state = instance->state; ++ ++ vcos_log_trace( "%s(%p) called", __func__, instance ); ++ ++ vcos_mutex_lock(&state->mutex); ++ ++ /* Remove all services */ ++ status = vchiq_shutdown_internal(state, instance); ++ ++ vcos_mutex_unlock(&state->mutex); ++ ++ if (status == VCHIQ_SUCCESS) ++ kfree(instance); ++ ++ vcos_log_trace( "%s(%p): returning %d", __func__, instance, status ); ++ ++ return status; ++} ++ ++/**************************************************************************** ++* ++* vchiq_is_connected ++* ++***************************************************************************/ ++ ++int vchiq_is_connected(VCHIQ_INSTANCE_T instance) ++{ ++ return instance->connected; ++} ++ ++/**************************************************************************** ++* ++* vchiq_connect ++* ++***************************************************************************/ ++ ++VCHIQ_STATUS_T vchiq_connect(VCHIQ_INSTANCE_T instance) ++{ ++ VCHIQ_STATUS_T status; ++ VCHIQ_STATE_T *state = instance->state; ++ ++ vcos_log_trace( "%s(%p) called", __func__, instance ); ++ ++ if (vcos_mutex_lock(&state->mutex) != VCOS_SUCCESS) { ++ vcos_log_trace( "%s: call to vcos_mutex_lock failed", __func__ ); ++ status = VCHIQ_RETRY; ++ goto failed; ++ } ++ status = vchiq_connect_internal(state, instance); ++ ++ if (status == VCHIQ_SUCCESS) ++ instance->connected = 1; ++ ++ vcos_mutex_unlock(&state->mutex); ++ ++failed: ++ vcos_log_trace( "%s(%p): returning %d", __func__, instance, status ); ++ ++ return status; ++} ++ ++/**************************************************************************** ++* ++* vchiq_add_service ++* ++***************************************************************************/ ++ ++VCHIQ_STATUS_T vchiq_add_service( ++ VCHIQ_INSTANCE_T instance, ++ int fourcc, ++ VCHIQ_CALLBACK_T callback, ++ void *userdata, ++ VCHIQ_SERVICE_HANDLE_T *pservice) ++{ ++ VCHIQ_SERVICE_PARAMS_T params; ++ ++ params.fourcc = fourcc; ++ params.callback = callback; ++ params.userdata = userdata; ++ params.version = 0; ++ params.version_min = 0; ++ ++ return vchiq_add_service_params(instance, ¶ms, pservice); ++} ++ ++/**************************************************************************** ++* ++* vchiq_open_service ++* ++***************************************************************************/ ++ ++VCHIQ_STATUS_T vchiq_open_service( ++ VCHIQ_INSTANCE_T instance, ++ int fourcc, ++ VCHIQ_CALLBACK_T callback, ++ void *userdata, ++ VCHIQ_SERVICE_HANDLE_T *pservice) ++{ ++ VCHIQ_SERVICE_PARAMS_T params; ++ ++ params.fourcc = fourcc; ++ params.callback = callback; ++ params.userdata = userdata; ++ params.version = 0; ++ params.version_min = 0; ++ ++ return vchiq_open_service_params(instance, ¶ms, pservice); ++} ++ ++/**************************************************************************** ++* ++* vchiq_add_service_params ++* ++***************************************************************************/ ++ ++VCHIQ_STATUS_T vchiq_add_service_params( ++ VCHIQ_INSTANCE_T instance, ++ const VCHIQ_SERVICE_PARAMS_T *params, ++ VCHIQ_SERVICE_HANDLE_T *pservice) ++{ ++ VCHIQ_STATUS_T status; ++ VCHIQ_STATE_T *state = instance->state; ++ VCHIQ_SERVICE_T *service; ++ int srvstate; ++ ++ vcos_log_trace( "%s(%p) called", __func__, instance ); ++ ++ *pservice = NULL; ++ ++ srvstate = vchiq_is_connected( instance ) ++ ? VCHIQ_SRVSTATE_LISTENING ++ : VCHIQ_SRVSTATE_HIDDEN; ++ ++ vcos_mutex_lock(&state->mutex); ++ ++ service = vchiq_add_service_internal( ++ state, ++ params, ++ srvstate, ++ instance); ++ ++ vcos_mutex_unlock(&state->mutex); ++ ++ if ( service ) ++ { ++ *pservice = &service->base; ++ status = VCHIQ_SUCCESS; ++ } ++ else ++ { ++ status = VCHIQ_ERROR; ++ } ++ ++ vcos_log_trace( "%s(%p): returning %d", __func__, instance, status ); ++ ++ return status; ++} ++ ++/**************************************************************************** ++* ++* vchiq_open_service_params ++* ++***************************************************************************/ ++ ++VCHIQ_STATUS_T vchiq_open_service_params( ++ VCHIQ_INSTANCE_T instance, ++ const VCHIQ_SERVICE_PARAMS_T *params, ++ VCHIQ_SERVICE_HANDLE_T *pservice) ++{ ++ VCHIQ_STATUS_T status = VCHIQ_ERROR; ++ VCHIQ_STATE_T *state = instance->state; ++ VCHIQ_SERVICE_T *service; ++ ++ vcos_log_trace( "%s(%p) called", __func__, instance ); ++ ++ *pservice = NULL; ++ ++ if (!vchiq_is_connected(instance)) ++ goto failed; ++ ++ vcos_mutex_lock(&state->mutex); ++ ++ service = vchiq_add_service_internal(state, ++ params, ++ VCHIQ_SRVSTATE_OPENING, ++ instance); ++ ++ vcos_mutex_unlock(&state->mutex); ++ ++ if ( service ) ++ { ++ status = vchiq_open_service_internal(service, current->pid); ++ if ( status == VCHIQ_SUCCESS ) ++ *pservice = &service->base; ++ else ++ vchiq_remove_service(&service->base); ++ } ++ ++failed: ++ vcos_log_trace( "%s(%p): returning %d", __func__, instance, status ); ++ ++ return status; ++} ++ ++EXPORT_SYMBOL(vchiq_initialise); ++EXPORT_SYMBOL(vchiq_shutdown); ++EXPORT_SYMBOL(vchiq_connect); ++EXPORT_SYMBOL(vchiq_add_service); ++EXPORT_SYMBOL(vchiq_open_service); ++EXPORT_SYMBOL(vchiq_add_service_params); ++EXPORT_SYMBOL(vchiq_open_service_params); +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_lib.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_lib.c 2013-07-26 19:32:00.000000000 +0000 +@@ -0,0 +1,1518 @@ ++/* ++ * Copyright (c) 2010-2011 Broadcom Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++#include ++#include ++#include ++#include ++ ++#include "vchiq.h" ++#include "vchiq_cfg.h" ++#include "vchiq_ioctl.h" ++#include "interface/vchi/vchi.h" ++#include "interface/vchi/common/endian.h" ++#include "interface/vcos/vcos.h" ++ ++#define VCHIQ_MAX_INSTANCE_SERVICES 32 ++#define MSGBUF_SIZE (VCHIQ_MAX_MSG_SIZE + sizeof(VCHIQ_HEADER_T)) ++ ++#define RETRY(r,x) do { r = x; } while ((r == -1) && (errno == EINTR)) ++ ++#define VCOS_LOG_CATEGORY (&vchiq_lib_log_category) ++ ++typedef struct vchiq_service_struct ++{ ++ VCHIQ_SERVICE_BASE_T base; ++ int handle; ++ int fd; ++ VCHI_CALLBACK_T vchi_callback; ++ void *peek_buf; ++ int peek_size; ++ int client_id; ++} VCHIQ_SERVICE_T; ++ ++typedef struct vchiq_service_struct VCHI_SERVICE_T; ++ ++struct vchiq_instance_struct ++{ ++ int fd; ++ int initialised; ++ int connected; ++ VCOS_THREAD_T completion_thread; ++ VCOS_MUTEX_T mutex; ++ int used_services; ++ VCHIQ_SERVICE_T services[VCHIQ_MAX_INSTANCE_SERVICES]; ++} vchiq_instance; ++ ++typedef struct vchiq_instance_struct VCHI_STATE_T; ++ ++/* Local data */ ++static VCOS_LOG_LEVEL_T vchiq_default_lib_log_level = VCOS_LOG_WARN; ++static VCOS_LOG_CAT_T vchiq_lib_log_category; ++static VCOS_MUTEX_T vchiq_lib_mutex; ++static void *free_msgbufs; ++ ++ ++/* Local utility functions */ ++static VCHIQ_INSTANCE_T ++vchiq_lib_init(void); ++ ++static void *completion_thread(void *); ++ ++static VCHIQ_STATUS_T ++create_service(VCHIQ_INSTANCE_T instance, ++ const VCHIQ_SERVICE_PARAMS_T *params, ++ VCHI_CALLBACK_T vchi_callback, ++ int is_open, ++ VCHIQ_SERVICE_HANDLE_T *pservice); ++ ++static int ++fill_peek_buf(VCHI_SERVICE_T *service, ++ VCHI_FLAGS_T flags); ++ ++static void * ++alloc_msgbuf(void); ++ ++static void ++free_msgbuf(void *buf); ++ ++static __inline int ++is_valid_instance(VCHIQ_INSTANCE_T instance) ++{ ++ return (instance == &vchiq_instance) && (instance->initialised > 0); ++} ++ ++/* ++ * VCHIQ API ++ */ ++ ++VCHIQ_STATUS_T ++vchiq_initialise(VCHIQ_INSTANCE_T *pinstance) ++{ ++ VCHIQ_INSTANCE_T instance; ++ ++ instance = vchiq_lib_init(); ++ ++ vcos_log_trace( "%s: returning instance handle %p", __func__, instance ); ++ ++ *pinstance = instance; ++ ++ return (instance != NULL) ? VCHIQ_SUCCESS : VCHIQ_ERROR; ++} ++ ++VCHIQ_STATUS_T ++vchiq_shutdown(VCHIQ_INSTANCE_T instance) ++{ ++ vcos_log_trace( "%s called", __func__ ); ++ ++ if (!is_valid_instance(instance)) ++ return VCHIQ_ERROR; ++ ++ vcos_mutex_lock(&instance->mutex); ++ ++ if (instance->initialised == 1) ++ { ++ int i; ++ ++ instance->initialised = -1; /* Enter limbo */ ++ ++ /* Remove all services */ ++ ++ for (i = 0; i < instance->used_services; i++) ++ { ++ if (instance->services[i].handle != VCHIQ_INVALID_HANDLE) ++ { ++ vchiq_remove_service(&instance->services[i].base); ++ instance->services[i].handle = VCHIQ_INVALID_HANDLE; ++ } ++ } ++ ++ if (instance->connected) ++ { ++ int ret; ++ RETRY(ret, ioctl(instance->fd, VCHIQ_IOC_SHUTDOWN, 0)); ++ vcos_assert(ret == 0); ++ vcos_thread_join(&instance->completion_thread, NULL); ++ instance->connected = 0; ++ } ++ ++ close(instance->fd); ++ instance->fd = -1; ++ } ++ else if (instance->initialised > 1) ++ { ++ instance->initialised--; ++ } ++ ++ vcos_mutex_unlock(&instance->mutex); ++ ++ vcos_global_lock(); ++ ++ if (instance->initialised == -1) ++ { ++ vcos_mutex_delete(&instance->mutex); ++ instance->initialised = 0; ++ } ++ ++ vcos_global_unlock(); ++ ++ vcos_log_trace( "%s returning", __func__ ); ++ ++ return VCHIQ_SUCCESS; ++} ++ ++VCHIQ_STATUS_T ++vchiq_connect(VCHIQ_INSTANCE_T instance) ++{ ++ VCHIQ_STATUS_T status = VCHIQ_SUCCESS; ++ ++ vcos_log_trace( "%s called", __func__ ); ++ ++ if (!is_valid_instance(instance)) ++ return VCHIQ_ERROR; ++ ++ vcos_mutex_lock(&instance->mutex); ++ ++ if (!instance->connected) ++ { ++ int ret = ioctl(instance->fd, VCHIQ_IOC_CONNECT, 0); ++ if (ret == 0) ++ { ++ VCOS_THREAD_ATTR_T attrs; ++ instance->connected = 1; ++ vcos_thread_attr_init(&attrs); ++ vcos_thread_create(&instance->completion_thread, "VCHIQ completion", ++ &attrs, completion_thread, instance); ++ } ++ else ++ { ++ status = VCHIQ_ERROR; ++ } ++ } ++ ++ vcos_mutex_unlock(&instance->mutex); ++ ++ return status; ++} ++ ++VCHIQ_STATUS_T ++vchiq_add_service(VCHIQ_INSTANCE_T instance, ++ int fourcc, ++ VCHIQ_CALLBACK_T callback, ++ void *userdata, ++ VCHIQ_SERVICE_HANDLE_T *pservice) ++{ ++ VCHIQ_SERVICE_PARAMS_T params; ++ ++ params.fourcc = fourcc; ++ params.callback = callback; ++ params.userdata = userdata; ++ params.version = 0; ++ params.version_min = 0; ++ ++ return vchiq_add_service_params(instance, ¶ms, pservice); ++} ++ ++VCHIQ_STATUS_T ++vchiq_open_service(VCHIQ_INSTANCE_T instance, ++ int fourcc, ++ VCHIQ_CALLBACK_T callback, ++ void *userdata, ++ VCHIQ_SERVICE_HANDLE_T *pservice) ++{ ++ VCHIQ_SERVICE_PARAMS_T params; ++ ++ params.fourcc = fourcc; ++ params.callback = callback; ++ params.userdata = userdata; ++ params.version = 0; ++ params.version_min = 0; ++ ++ return vchiq_open_service_params(instance, ¶ms, pservice); ++} ++ ++VCHIQ_STATUS_T ++vchiq_add_service_params(VCHIQ_INSTANCE_T instance, ++ const VCHIQ_SERVICE_PARAMS_T *params, ++ VCHIQ_SERVICE_HANDLE_T *pservice) ++{ ++ VCHIQ_STATUS_T status; ++ ++ vcos_log_trace( "%s called fourcc = 0x%08x (%c%c%c%c)", ++ __func__, ++ params->fourcc, ++ (params->fourcc >> 24) & 0xff, ++ (params->fourcc >> 16) & 0xff, ++ (params->fourcc >> 8) & 0xff, ++ (params->fourcc ) & 0xff ); ++ ++ if (!params->callback) ++ return VCHIQ_ERROR; ++ ++ if (!is_valid_instance(instance)) ++ return VCHIQ_ERROR; ++ ++ status = create_service(instance, ++ params, ++ NULL/*vchi_callback*/, ++ 0/*!open*/, ++ pservice); ++ ++ vcos_log_trace( "%s returning service handle = 0x%08x", __func__, (uint32_t)*pservice ); ++ ++ return status; ++} ++ ++VCHIQ_STATUS_T ++vchiq_open_service_params(VCHIQ_INSTANCE_T instance, ++ const VCHIQ_SERVICE_PARAMS_T *params, ++ VCHIQ_SERVICE_HANDLE_T *pservice) ++{ ++ VCHIQ_STATUS_T status; ++ ++ vcos_log_trace( "%s called fourcc = 0x%08x (%c%c%c%c)", ++ __func__, ++ params->fourcc, ++ (params->fourcc >> 24) & 0xff, ++ (params->fourcc >> 16) & 0xff, ++ (params->fourcc >> 8) & 0xff, ++ (params->fourcc ) & 0xff ); ++ ++ if (!params->callback) ++ return VCHIQ_ERROR; ++ ++ if (!is_valid_instance(instance)) ++ return VCHIQ_ERROR; ++ ++ status = create_service(instance, ++ params, ++ NULL/*vchi_callback*/, ++ 1/*open*/, ++ pservice); ++ ++ vcos_log_trace( "%s returning service handle = 0x%08x", __func__, (uint32_t)*pservice ); ++ ++ return status; ++} ++ ++VCHIQ_STATUS_T ++vchiq_close_service(VCHIQ_SERVICE_HANDLE_T handle) ++{ ++ VCHIQ_SERVICE_T *service = (VCHIQ_SERVICE_T *)handle; ++ int ret; ++ ++ vcos_log_trace( "%s called service handle = 0x%08x", __func__, (uint32_t)handle ); ++ ++ RETRY(ret,ioctl(service->fd, VCHIQ_IOC_CLOSE_SERVICE, service->handle)); ++ ++ if (ret != 0) ++ return VCHIQ_ERROR; ++ ++ service->handle = VCHIQ_INVALID_HANDLE; ++ return VCHIQ_SUCCESS; ++} ++ ++VCHIQ_STATUS_T ++vchiq_remove_service(VCHIQ_SERVICE_HANDLE_T handle) ++{ ++ VCHIQ_SERVICE_T *service = (VCHIQ_SERVICE_T *)handle; ++ int ret; ++ ++ vcos_log_trace( "%s called service handle = 0x%08x", __func__, (uint32_t)handle ); ++ ++ RETRY(ret,ioctl(service->fd, VCHIQ_IOC_REMOVE_SERVICE, service->handle)); ++ ++ if (ret != 0) ++ return VCHIQ_ERROR; ++ ++ service->handle = VCHIQ_INVALID_HANDLE; ++ return VCHIQ_SUCCESS; ++} ++ ++VCHIQ_STATUS_T ++vchiq_queue_message(VCHIQ_SERVICE_HANDLE_T handle, ++ const VCHIQ_ELEMENT_T *elements, ++ int count) ++{ ++ VCHIQ_SERVICE_T *service = (VCHIQ_SERVICE_T *)handle; ++ VCHIQ_QUEUE_MESSAGE_T args; ++ int ret; ++ ++ vcos_log_trace( "%s called service handle = 0x%08x", __func__, (uint32_t)handle ); ++ ++ args.handle = service->handle; ++ args.elements = elements; ++ args.count = count; ++ RETRY(ret, ioctl(service->fd, VCHIQ_IOC_QUEUE_MESSAGE, &args)); ++ ++ return (ret >= 0) ? VCHIQ_SUCCESS : VCHIQ_ERROR; ++} ++ ++void ++vchiq_release_message(VCHIQ_SERVICE_HANDLE_T handle, ++ VCHIQ_HEADER_T *header) ++{ ++ vcos_log_trace( "%s handle=%08x, header=%x", __func__, (uint32_t)handle, (uint32_t)header ); ++ ++ free_msgbuf(header); ++} ++ ++VCHIQ_STATUS_T ++vchiq_queue_bulk_transmit(VCHIQ_SERVICE_HANDLE_T handle, ++ const void *data, ++ int size, ++ void *userdata) ++{ ++ VCHIQ_SERVICE_T *service = (VCHIQ_SERVICE_T *)handle; ++ VCHIQ_QUEUE_BULK_TRANSFER_T args; ++ int ret; ++ ++ vcos_log_trace( "%s called service handle = 0x%08x", __func__, (uint32_t)handle ); ++ ++ args.handle = service->handle; ++ args.data = (void *)data; ++ args.size = size; ++ args.userdata = userdata; ++ args.mode = VCHIQ_BULK_MODE_CALLBACK; ++ RETRY(ret, ioctl(service->fd, VCHIQ_IOC_QUEUE_BULK_TRANSMIT, &args)); ++ ++ return (ret >= 0) ? VCHIQ_SUCCESS : VCHIQ_ERROR; ++} ++ ++VCHIQ_STATUS_T ++vchiq_queue_bulk_receive(VCHIQ_SERVICE_HANDLE_T handle, ++ void *data, ++ int size, ++ void *userdata) ++{ ++ VCHIQ_SERVICE_T *service = (VCHIQ_SERVICE_T *)handle; ++ VCHIQ_QUEUE_BULK_TRANSFER_T args; ++ int ret; ++ ++ vcos_log_trace( "%s called service handle = 0x%08x", __func__, (uint32_t)handle ); ++ ++ args.handle = service->handle; ++ args.data = data; ++ args.size = size; ++ args.userdata = userdata; ++ args.mode = VCHIQ_BULK_MODE_CALLBACK; ++ RETRY(ret, ioctl(service->fd, VCHIQ_IOC_QUEUE_BULK_RECEIVE, &args)); ++ ++ return (ret >= 0) ? VCHIQ_SUCCESS : VCHIQ_ERROR; ++} ++ ++VCHIQ_STATUS_T ++vchiq_queue_bulk_transmit_handle(VCHIQ_SERVICE_HANDLE_T handle, ++ VCHI_MEM_HANDLE_T memhandle, ++ const void *offset, ++ int size, ++ void *userdata) ++{ ++ vcos_assert(memhandle == VCHI_MEM_HANDLE_INVALID); ++ ++ vcos_log_trace( "%s called service handle = 0x%08x", __func__, (uint32_t)handle ); ++ ++ return vchiq_queue_bulk_transmit(handle, offset, size, userdata); ++} ++ ++VCHIQ_STATUS_T ++vchiq_queue_bulk_receive_handle(VCHIQ_SERVICE_HANDLE_T handle, ++ VCHI_MEM_HANDLE_T memhandle, ++ void *offset, ++ int size, ++ void *userdata) ++{ ++ vcos_assert(memhandle == VCHI_MEM_HANDLE_INVALID); ++ ++ vcos_log_trace( "%s called service handle = 0x%08x", __func__, (uint32_t)handle ); ++ ++ return vchiq_queue_bulk_receive(handle, offset, size, userdata); ++} ++ ++VCHIQ_STATUS_T ++vchiq_bulk_transmit(VCHIQ_SERVICE_HANDLE_T handle, ++ const void *data, ++ int size, ++ void *userdata, ++ VCHIQ_BULK_MODE_T mode) ++{ ++ VCHIQ_SERVICE_T *service = (VCHIQ_SERVICE_T *)handle; ++ VCHIQ_QUEUE_BULK_TRANSFER_T args; ++ int ret; ++ ++ vcos_log_trace( "%s called service handle = 0x%08x", __func__, (uint32_t)handle ); ++ ++ args.handle = service->handle; ++ args.data = (void *)data; ++ args.size = size; ++ args.userdata = userdata; ++ args.mode = mode; ++ RETRY(ret, ioctl(service->fd, VCHIQ_IOC_QUEUE_BULK_TRANSMIT, &args)); ++ ++ return (ret >= 0) ? VCHIQ_SUCCESS : VCHIQ_ERROR; ++} ++ ++VCHIQ_STATUS_T ++vchiq_bulk_receive(VCHIQ_SERVICE_HANDLE_T handle, ++ void *data, ++ int size, ++ void *userdata, ++ VCHIQ_BULK_MODE_T mode) ++{ ++ VCHIQ_SERVICE_T *service = (VCHIQ_SERVICE_T *)handle; ++ VCHIQ_QUEUE_BULK_TRANSFER_T args; ++ int ret; ++ ++ vcos_log_trace( "%s called service handle = 0x%08x", __func__, (uint32_t)handle ); ++ ++ args.handle = service->handle; ++ args.data = data; ++ args.size = size; ++ args.userdata = userdata; ++ args.mode = mode; ++ RETRY(ret, ioctl(service->fd, VCHIQ_IOC_QUEUE_BULK_RECEIVE, &args)); ++ ++ return (ret >= 0) ? VCHIQ_SUCCESS : VCHIQ_ERROR; ++} ++ ++VCHIQ_STATUS_T ++vchiq_bulk_transmit_handle(VCHIQ_SERVICE_HANDLE_T handle, ++ VCHI_MEM_HANDLE_T memhandle, ++ const void *offset, ++ int size, ++ void *userdata, ++ VCHIQ_BULK_MODE_T mode) ++{ ++ vcos_assert(memhandle == VCHI_MEM_HANDLE_INVALID); ++ ++ return vchiq_bulk_transmit(handle, offset, size, userdata, mode); ++} ++ ++VCHIQ_STATUS_T ++vchiq_bulk_receive_handle(VCHIQ_SERVICE_HANDLE_T handle, ++ VCHI_MEM_HANDLE_T memhandle, ++ void *offset, ++ int size, ++ void *userdata, ++ VCHIQ_BULK_MODE_T mode) ++{ ++ vcos_assert(memhandle == VCHI_MEM_HANDLE_INVALID); ++ ++ return vchiq_bulk_receive(handle, offset, size, userdata, mode); ++} ++ ++int ++vchiq_get_client_id(VCHIQ_SERVICE_HANDLE_T handle) ++{ ++ VCHIQ_SERVICE_T *service = (VCHIQ_SERVICE_T *)handle; ++ ++ return ioctl(service->fd, VCHIQ_IOC_GET_CLIENT_ID, service->handle); ++} ++ ++VCHIQ_STATUS_T ++vchiq_get_config(VCHIQ_INSTANCE_T instance, ++ int config_size, ++ VCHIQ_CONFIG_T *pconfig) ++{ ++ VCHIQ_GET_CONFIG_T args; ++ int ret; ++ ++ if (!is_valid_instance(instance)) ++ return VCHIQ_ERROR; ++ ++ args.config_size = config_size; ++ args.pconfig = pconfig; ++ ++ RETRY(ret, ioctl(instance->fd, VCHIQ_IOC_GET_CONFIG, &args)); ++ ++ return (ret >= 0) ? VCHIQ_SUCCESS : VCHIQ_ERROR; ++} ++ ++int32_t ++vchiq_use_service( const VCHIQ_SERVICE_HANDLE_T handle ) ++{ ++ VCHIQ_SERVICE_T *service = (VCHIQ_SERVICE_T *)handle; ++ int ret; ++ RETRY(ret,ioctl(service->fd, VCHIQ_IOC_USE_SERVICE, service->handle)); ++ return ret; ++} ++ ++int32_t ++vchiq_release_service( const VCHIQ_SERVICE_HANDLE_T handle ) ++{ ++ VCHIQ_SERVICE_T *service = (VCHIQ_SERVICE_T *)handle; ++ int ret; ++ RETRY(ret,ioctl(service->fd, VCHIQ_IOC_RELEASE_SERVICE, service->handle)); ++ return ret; ++} ++ ++VCHIQ_STATUS_T ++vchiq_set_service_option(VCHIQ_SERVICE_HANDLE_T handle, ++ VCHIQ_SERVICE_OPTION_T option, int value) ++{ ++ VCHIQ_SET_SERVICE_OPTION_T args; ++ VCHIQ_SERVICE_T *service = (VCHIQ_SERVICE_T *)handle; ++ int ret; ++ ++ args.handle = service->handle; ++ args.option = option; ++ args.value = value; ++ ++ RETRY(ret, ioctl(service->fd, VCHIQ_IOC_SET_SERVICE_OPTION, &args)); ++ ++ return (ret >= 0) ? VCHIQ_SUCCESS : VCHIQ_ERROR; ++} ++ ++/* ++ * VCHI API ++ */ ++ ++/* ---------------------------------------------------------------------- ++ * return pointer to the mphi message driver function table ++ * -------------------------------------------------------------------- */ ++const VCHI_MESSAGE_DRIVER_T * ++vchi_mphi_message_driver_func_table( void ) ++{ ++ return NULL; ++} ++ ++/* ---------------------------------------------------------------------- ++ * return a pointer to the 'single' connection driver fops ++ * -------------------------------------------------------------------- */ ++const VCHI_CONNECTION_API_T * ++single_get_func_table( void ) ++{ ++ return NULL; ++} ++ ++VCHI_CONNECTION_T * ++vchi_create_connection( const VCHI_CONNECTION_API_T * function_table, ++ const VCHI_MESSAGE_DRIVER_T * low_level ) ++{ ++ vcos_unused(function_table); ++ vcos_unused(low_level); ++ ++ return NULL; ++} ++ ++/*********************************************************** ++ * Name: vchi_msg_peek ++ * ++ * Arguments: const VCHI_SERVICE_HANDLE_T handle, ++ * void **data, ++ * uint32_t *msg_size, ++ * VCHI_FLAGS_T flags ++ * ++ * Description: Routine to return a pointer to the current message (to allow in place processing) ++ * The message can be removed using vchi_msg_remove when you're finished ++ * ++ * Returns: int32_t - success == 0 ++ * ++ ***********************************************************/ ++int32_t ++vchi_msg_peek( VCHI_SERVICE_HANDLE_T handle, ++ void **data, ++ uint32_t *msg_size, ++ VCHI_FLAGS_T flags ) ++{ ++ VCHI_SERVICE_T *service = (VCHI_SERVICE_T *)handle; ++ int ret; ++ ++ ret = fill_peek_buf(service, flags); ++ ++ if (ret == 0) ++ { ++ *data = service->peek_buf; ++ *msg_size = service->peek_size; ++ } ++ ++ return ret; ++} ++ ++/*********************************************************** ++ * Name: vchi_msg_remove ++ * ++ * Arguments: const VCHI_SERVICE_HANDLE_T handle, ++ * ++ * Description: Routine to remove a message (after it has been read with vchi_msg_peek) ++ * ++ * Returns: int32_t - success == 0 ++ * ++ ***********************************************************/ ++int32_t ++vchi_msg_remove( VCHI_SERVICE_HANDLE_T handle ) ++{ ++ VCHI_SERVICE_T *service = (VCHI_SERVICE_T *)handle; ++ ++ /* Why would you call vchi_msg_remove without calling vchi_msg_peek first? */ ++ vcos_assert(service->peek_size >= 0); ++ ++ /* Invalidate the content but reuse the buffer */ ++ service->peek_size = -1; ++ ++ return 0; ++} ++ ++/*********************************************************** ++ * Name: vchi_msg_queue ++ * ++ * Arguments: VCHI_SERVICE_HANDLE_T handle, ++ * const void *data, ++ * uint32_t data_size, ++ * VCHI_FLAGS_T flags, ++ * void *msg_handle, ++ * ++ * Description: Thin wrapper to queue a message onto a connection ++ * ++ * Returns: int32_t - success == 0 ++ * ++ ***********************************************************/ ++int32_t ++vchi_msg_queue( VCHI_SERVICE_HANDLE_T handle, ++ const void * data, ++ uint32_t data_size, ++ VCHI_FLAGS_T flags, ++ void * msg_handle ) ++{ ++ VCHI_SERVICE_T *service = (VCHI_SERVICE_T *)handle; ++ VCHIQ_QUEUE_MESSAGE_T args; ++ VCHIQ_ELEMENT_T element = {data, data_size}; ++ int ret; ++ ++ vcos_unused(msg_handle); ++ vcos_assert(flags == VCHI_FLAGS_BLOCK_UNTIL_QUEUED); ++ ++ args.handle = service->handle; ++ args.elements = &element; ++ args.count = 1; ++ RETRY(ret, ioctl(service->fd, VCHIQ_IOC_QUEUE_MESSAGE, &args)); ++ ++ return ret; ++} ++ ++/*********************************************************** ++ * Name: vchi_bulk_queue_receive ++ * ++ * Arguments: VCHI_BULK_HANDLE_T handle, ++ * void *data_dst, ++ * const uint32_t data_size, ++ * VCHI_FLAGS_T flags ++ * void *bulk_handle ++ * ++ * Description: Routine to setup a rcv buffer ++ * ++ * Returns: int32_t - success == 0 ++ * ++ ***********************************************************/ ++int32_t ++vchi_bulk_queue_receive( VCHI_SERVICE_HANDLE_T handle, ++ void * data_dst, ++ uint32_t data_size, ++ VCHI_FLAGS_T flags, ++ void * bulk_handle ) ++{ ++ VCHI_SERVICE_T *service = (VCHI_SERVICE_T *)handle; ++ VCHIQ_QUEUE_BULK_TRANSFER_T args; ++ int ret; ++ ++ switch ((int)flags) { ++ case VCHI_FLAGS_CALLBACK_WHEN_OP_COMPLETE | VCHI_FLAGS_BLOCK_UNTIL_QUEUED: ++ args.mode = VCHIQ_BULK_MODE_CALLBACK; ++ break; ++ case VCHI_FLAGS_BLOCK_UNTIL_OP_COMPLETE: ++ args.mode = VCHIQ_BULK_MODE_BLOCKING; ++ break; ++ case VCHI_FLAGS_BLOCK_UNTIL_QUEUED: ++ case VCHI_FLAGS_NONE: ++ args.mode = VCHIQ_BULK_MODE_NOCALLBACK; ++ break; ++ default: ++ vcos_assert(0); ++ break; ++ } ++ ++ args.handle = service->handle; ++ args.data = data_dst; ++ args.size = data_size; ++ args.userdata = bulk_handle; ++ RETRY(ret, ioctl(service->fd, VCHIQ_IOC_QUEUE_BULK_RECEIVE, &args)); ++ ++ return ret; ++} ++ ++/*********************************************************** ++ * Name: vchi_bulk_queue_transmit ++ * ++ * Arguments: VCHI_BULK_HANDLE_T handle, ++ * const void *data_src, ++ * uint32_t data_size, ++ * VCHI_FLAGS_T flags, ++ * void *bulk_handle ++ * ++ * Description: Routine to transmit some data ++ * ++ * Returns: int32_t - success == 0 ++ * ++ ***********************************************************/ ++int32_t ++vchi_bulk_queue_transmit( VCHI_SERVICE_HANDLE_T handle, ++ const void * data_src, ++ uint32_t data_size, ++ VCHI_FLAGS_T flags, ++ void * bulk_handle ) ++{ ++ VCHI_SERVICE_T *service = (VCHI_SERVICE_T *)handle; ++ VCHIQ_QUEUE_BULK_TRANSFER_T args; ++ int ret; ++ ++ switch ((int)flags) { ++ case VCHI_FLAGS_CALLBACK_WHEN_OP_COMPLETE | VCHI_FLAGS_BLOCK_UNTIL_QUEUED: ++ args.mode = VCHIQ_BULK_MODE_CALLBACK; ++ break; ++ case VCHI_FLAGS_BLOCK_UNTIL_DATA_READ: ++ case VCHI_FLAGS_BLOCK_UNTIL_OP_COMPLETE: ++ args.mode = VCHIQ_BULK_MODE_BLOCKING; ++ break; ++ case VCHI_FLAGS_BLOCK_UNTIL_QUEUED: ++ case VCHI_FLAGS_NONE: ++ args.mode = VCHIQ_BULK_MODE_NOCALLBACK; ++ break; ++ default: ++ vcos_assert(0); ++ break; ++ } ++ ++ args.handle = service->handle; ++ args.data = (void *)data_src; ++ args.size = data_size; ++ args.userdata = bulk_handle; ++ RETRY(ret, ioctl(service->fd, VCHIQ_IOC_QUEUE_BULK_TRANSMIT, &args)); ++ ++ return ret; ++} ++ ++/*********************************************************** ++ * Name: vchi_msg_dequeue ++ * ++ * Arguments: VCHI_SERVICE_HANDLE_T handle, ++ * void *data, ++ * uint32_t max_data_size_to_read, ++ * uint32_t *actual_msg_size ++ * VCHI_FLAGS_T flags ++ * ++ * Description: Routine to dequeue a message into the supplied buffer ++ * ++ * Returns: int32_t - success == 0 ++ * ++ ***********************************************************/ ++int32_t ++vchi_msg_dequeue( VCHI_SERVICE_HANDLE_T handle, ++ void *data, ++ uint32_t max_data_size_to_read, ++ uint32_t *actual_msg_size, ++ VCHI_FLAGS_T flags ) ++{ ++ VCHI_SERVICE_T *service = (VCHI_SERVICE_T *)handle; ++ VCHIQ_DEQUEUE_MESSAGE_T args; ++ int ret; ++ ++ vcos_assert(flags == VCHI_FLAGS_NONE || flags == VCHI_FLAGS_BLOCK_UNTIL_OP_COMPLETE); ++ ++ if (service->peek_size >= 0) ++ { ++ fprintf(stderr, "vchi_msg_dequeue -> using peek buffer\n"); ++ if ((uint32_t)service->peek_size <= max_data_size_to_read) ++ { ++ memcpy(data, service->peek_buf, service->peek_size); ++ *actual_msg_size = service->peek_size; ++ /* Invalidate the peek data, but retain the buffer */ ++ service->peek_size = -1; ++ ret = 0; ++ } ++ else ++ { ++ ret = -1; ++ } ++ } ++ else ++ { ++ args.handle = service->handle; ++ args.blocking = (flags == VCHI_FLAGS_BLOCK_UNTIL_OP_COMPLETE); ++ args.bufsize = max_data_size_to_read; ++ args.buf = data; ++ RETRY(ret, ioctl(service->fd, VCHIQ_IOC_DEQUEUE_MESSAGE, &args)); ++ if (ret >= 0) ++ { ++ *actual_msg_size = ret; ++ ret = 0; ++ } ++ } ++ ++ if ((ret < 0) && (errno != EWOULDBLOCK)) ++ fprintf(stderr, "vchi_msg_dequeue -> %d(%d)\n", ret, errno); ++ ++ return ret; ++} ++ ++/*********************************************************** ++ * Name: vchi_msg_queuev ++ * ++ * Arguments: VCHI_SERVICE_HANDLE_T handle, ++ * const void *data, ++ * uint32_t data_size, ++ * VCHI_FLAGS_T flags, ++ * void *msg_handle ++ * ++ * Description: Thin wrapper to queue a message onto a connection ++ * ++ * Returns: int32_t - success == 0 ++ * ++ ***********************************************************/ ++ ++vcos_static_assert(sizeof(VCHI_MSG_VECTOR_T) == sizeof(VCHIQ_ELEMENT_T)); ++vcos_static_assert(offsetof(VCHI_MSG_VECTOR_T, vec_base) == offsetof(VCHIQ_ELEMENT_T, data)); ++vcos_static_assert(offsetof(VCHI_MSG_VECTOR_T, vec_len) == offsetof(VCHIQ_ELEMENT_T, size)); ++ ++int32_t ++vchi_msg_queuev( VCHI_SERVICE_HANDLE_T handle, ++ VCHI_MSG_VECTOR_T * vector, ++ uint32_t count, ++ VCHI_FLAGS_T flags, ++ void *msg_handle ) ++{ ++ VCHI_SERVICE_T *service = (VCHI_SERVICE_T *)handle; ++ VCHIQ_QUEUE_MESSAGE_T args; ++ int ret; ++ ++ vcos_unused(msg_handle); ++ ++ vcos_assert(flags == VCHI_FLAGS_BLOCK_UNTIL_QUEUED); ++ ++ args.handle = service->handle; ++ args.elements = (const VCHIQ_ELEMENT_T *)vector; ++ args.count = count; ++ RETRY(ret, ioctl(service->fd, VCHIQ_IOC_QUEUE_MESSAGE, &args)); ++ ++ return ret; ++} ++ ++/*********************************************************** ++ * Name: vchi_held_msg_release ++ * ++ * Arguments: VCHI_HELD_MSG_T *message ++ * ++ * Description: Routine to release a held message (after it has been read with vchi_msg_hold) ++ * ++ * Returns: int32_t - success == 0 ++ * ++ ***********************************************************/ ++int32_t ++vchi_held_msg_release( VCHI_HELD_MSG_T *message ) ++{ ++ int ret = -1; ++ ++ if (message && message->message && !message->service) ++ { ++ free_msgbuf(message->message); ++ ret = 0; ++ } ++ ++ return ret; ++} ++ ++/*********************************************************** ++ * Name: vchi_msg_hold ++ * ++ * Arguments: VCHI_SERVICE_HANDLE_T handle, ++ * void **data, ++ * uint32_t *msg_size, ++ * VCHI_FLAGS_T flags, ++ * VCHI_HELD_MSG_T *message_handle ++ * ++ * Description: Routine to return a pointer to the current message (to allow in place processing) ++ * The message is dequeued - don't forget to release the message using ++ * vchi_held_msg_release when you're finished ++ * ++ * Returns: int32_t - success == 0 ++ * ++ ***********************************************************/ ++int32_t ++vchi_msg_hold( VCHI_SERVICE_HANDLE_T handle, ++ void **data, ++ uint32_t *msg_size, ++ VCHI_FLAGS_T flags, ++ VCHI_HELD_MSG_T *message_handle ) ++{ ++ VCHI_SERVICE_T *service = (VCHI_SERVICE_T *)handle; ++ int ret; ++ ++ ret = fill_peek_buf(service, flags); ++ ++ if (ret == 0) ++ { ++ *data = service->peek_buf; ++ *msg_size = service->peek_size; ++ ++ message_handle->message = service->peek_buf; ++ message_handle->service = NULL; ++ ++ service->peek_size = -1; ++ service->peek_buf = NULL; ++ } ++ ++ return 0; ++} ++ ++/*********************************************************** ++ * Name: vchi_initialise ++ * ++ * Arguments: VCHI_INSTANCE_T *instance_handle ++ * VCHI_CONNECTION_T **connections ++ * const uint32_t num_connections ++ * ++ * Description: Initialises the hardware but does not transmit anything ++ * When run as a Host App this will be called twice hence the need ++ * to malloc the state information ++ * ++ * Returns: 0 if successful, failure otherwise ++ * ++ ***********************************************************/ ++int32_t ++vchi_initialise( VCHI_INSTANCE_T *instance_handle ) ++{ ++ VCHIQ_INSTANCE_T instance; ++ ++ instance = vchiq_lib_init(); ++ ++ vcos_log_trace( "%s: returning instance handle %p", __func__, instance ); ++ ++ *instance_handle = (VCHI_INSTANCE_T)instance; ++ ++ return (instance != NULL) ? 0 : -1; ++} ++ ++/*********************************************************** ++ * Name: vchi_connect ++ * ++ * Arguments: VCHI_CONNECTION_T **connections ++ * const uint32_t num_connections ++ * VCHI_INSTANCE_T instance_handle ) ++ * ++ * Description: Starts the command service on each connection, ++ * causing INIT messages to be pinged back and forth ++ * ++ * Returns: 0 if successful, failure otherwise ++ * ++ ***********************************************************/ ++int32_t ++vchi_connect( VCHI_CONNECTION_T **connections, ++ const uint32_t num_connections, ++ VCHI_INSTANCE_T instance_handle ) ++{ ++ VCHIQ_STATUS_T status; ++ ++ vcos_unused(connections); ++ vcos_unused(num_connections); ++ ++ status = vchiq_connect((VCHIQ_INSTANCE_T)instance_handle); ++ ++ return (status == VCHIQ_SUCCESS) ? 0 : -1; ++} ++ ++ ++/*********************************************************** ++ * Name: vchi_disconnect ++ * ++ * Arguments: VCHI_INSTANCE_T instance_handle ++ * ++ * Description: Stops the command service on each connection, ++ * causing DE-INIT messages to be pinged back and forth ++ * ++ * Returns: 0 if successful, failure otherwise ++ * ++ ***********************************************************/ ++int32_t ++vchi_disconnect( VCHI_INSTANCE_T instance_handle ) ++{ ++ VCHIQ_STATUS_T status; ++ ++ status = vchiq_shutdown((VCHIQ_INSTANCE_T)instance_handle); ++ ++ return (status == VCHIQ_SUCCESS) ? 0 : -1; ++} ++ ++ ++/*********************************************************** ++ * Name: vchi_service_open ++ * Name: vchi_service_create ++ * ++ * Arguments: VCHI_INSTANCE_T *instance_handle ++ * SERVICE_CREATION_T *setup, ++ * VCHI_SERVICE_HANDLE_T *handle ++ * ++ * Description: Routine to open a service ++ * ++ * Returns: int32_t - success == 0 ++ * ++ ***********************************************************/ ++int32_t ++vchi_service_open( VCHI_INSTANCE_T instance_handle, ++ SERVICE_CREATION_T *setup, ++ VCHI_SERVICE_HANDLE_T *handle ) ++{ ++ VCHIQ_SERVICE_PARAMS_T params; ++ VCHIQ_STATUS_T status; ++ ++ memset(¶ms, 0, sizeof(params)); ++ params.fourcc = setup->service_id; ++ params.userdata = setup->callback_param; ++ ++ status = create_service((VCHIQ_INSTANCE_T)instance_handle, ++ ¶ms, ++ setup->callback, ++ 1/*open*/, ++ (VCHIQ_SERVICE_HANDLE_T *)handle); ++ ++ return (status == VCHIQ_SUCCESS) ? 0 : -1; ++} ++ ++int32_t ++vchi_service_create( VCHI_INSTANCE_T instance_handle, ++ SERVICE_CREATION_T *setup, VCHI_SERVICE_HANDLE_T *handle ) ++{ ++ VCHIQ_SERVICE_PARAMS_T params; ++ VCHIQ_STATUS_T status; ++ ++ memset(¶ms, 0, sizeof(params)); ++ params.fourcc = setup->service_id; ++ params.userdata = setup->callback_param; ++ ++ status = create_service((VCHIQ_INSTANCE_T)instance_handle, ++ ¶ms, ++ setup->callback, ++ 0/*!open*/, ++ (VCHIQ_SERVICE_HANDLE_T *)handle); ++ ++ return (status == VCHIQ_SUCCESS) ? 0 : -1; ++} ++ ++int32_t ++vchi_service_close( const VCHI_SERVICE_HANDLE_T handle ) ++{ ++ VCHI_SERVICE_T *service = (VCHI_SERVICE_T *)handle; ++ int ret; ++ RETRY(ret,ioctl(service->fd, VCHIQ_IOC_REMOVE_SERVICE, service->handle)); ++ ++ if (ret == 0) ++ service->handle = VCHIQ_INVALID_HANDLE; ++ ++ return ret; ++} ++ ++int32_t ++vchi_service_destroy( const VCHI_SERVICE_HANDLE_T handle ) ++{ ++ VCHI_SERVICE_T *service = (VCHI_SERVICE_T *)handle; ++ int ret; ++ RETRY(ret,ioctl(service->fd, VCHIQ_IOC_REMOVE_SERVICE, service->handle)); ++ ++ if (ret == 0) ++ service->handle = VCHIQ_INVALID_HANDLE; ++ ++ return ret; ++} ++ ++/* ---------------------------------------------------------------------- ++ * read a uint32_t from buffer. ++ * network format is defined to be little endian ++ * -------------------------------------------------------------------- */ ++uint32_t ++vchi_readbuf_uint32( const void *_ptr ) ++{ ++ const unsigned char *ptr = _ptr; ++ return ptr[0] | (ptr[1] << 8) | (ptr[2] << 16) | (ptr[3] << 24); ++} ++ ++/* ---------------------------------------------------------------------- ++ * write a uint32_t to buffer. ++ * network format is defined to be little endian ++ * -------------------------------------------------------------------- */ ++void ++vchi_writebuf_uint32( void *_ptr, uint32_t value ) ++{ ++ unsigned char *ptr = _ptr; ++ ptr[0] = (unsigned char)((value >> 0) & 0xFF); ++ ptr[1] = (unsigned char)((value >> 8) & 0xFF); ++ ptr[2] = (unsigned char)((value >> 16) & 0xFF); ++ ptr[3] = (unsigned char)((value >> 24) & 0xFF); ++} ++ ++/* ---------------------------------------------------------------------- ++ * read a uint16_t from buffer. ++ * network format is defined to be little endian ++ * -------------------------------------------------------------------- */ ++uint16_t ++vchi_readbuf_uint16( const void *_ptr ) ++{ ++ const unsigned char *ptr = _ptr; ++ return ptr[0] | (ptr[1] << 8); ++} ++ ++/* ---------------------------------------------------------------------- ++ * write a uint16_t into the buffer. ++ * network format is defined to be little endian ++ * -------------------------------------------------------------------- */ ++void ++vchi_writebuf_uint16( void *_ptr, uint16_t value ) ++{ ++ unsigned char *ptr = _ptr; ++ ptr[0] = (value >> 0) & 0xFF; ++ ptr[1] = (value >> 8) & 0xFF; ++} ++ ++/*********************************************************** ++ * Name: vchi_service_use ++ * ++ * Arguments: const VCHI_SERVICE_HANDLE_T handle ++ * ++ * Description: Routine to increment refcount on a service ++ * ++ * Returns: void ++ * ++ ***********************************************************/ ++int32_t ++vchi_service_use( const VCHI_SERVICE_HANDLE_T handle ) ++{ ++ VCHI_SERVICE_T *service = (VCHI_SERVICE_T *)handle; ++ int ret; ++ RETRY(ret,ioctl(service->fd, VCHIQ_IOC_USE_SERVICE, service->handle)); ++ return ret; ++} ++ ++/*********************************************************** ++ * Name: vchi_service_release ++ * ++ * Arguments: const VCHI_SERVICE_HANDLE_T handle ++ * ++ * Description: Routine to decrement refcount on a service ++ * ++ * Returns: void ++ * ++ ***********************************************************/ ++int32_t vchi_service_release( const VCHI_SERVICE_HANDLE_T handle ) ++{ ++ VCHI_SERVICE_T *service = (VCHI_SERVICE_T *)handle; ++ int ret; ++ RETRY(ret,ioctl(service->fd, VCHIQ_IOC_RELEASE_SERVICE, service->handle)); ++ return ret; ++} ++ ++/* ++ * Support functions ++ */ ++ ++static VCHIQ_INSTANCE_T ++vchiq_lib_init(void) ++{ ++ static int mutex_initialised = 0; ++ static VCOS_MUTEX_T vchiq_lib_mutex; ++ VCHIQ_INSTANCE_T instance = &vchiq_instance; ++ ++ vcos_global_lock(); ++ if (!mutex_initialised) ++ { ++ vcos_mutex_create(&vchiq_lib_mutex, "vchiq-init"); ++ ++ vcos_log_set_level( &vchiq_lib_log_category, vchiq_default_lib_log_level ); ++ vcos_log_register( "vchiq_lib", &vchiq_lib_log_category ); ++ ++ mutex_initialised = 1; ++ } ++ vcos_global_unlock(); ++ ++ vcos_mutex_lock(&vchiq_lib_mutex); ++ ++ if (instance->initialised == 0) ++ { ++ instance->fd = open("/dev/vchiq", O_RDWR); ++ if (instance->fd >= 0) ++ { ++ VCHIQ_GET_CONFIG_T args; ++ VCHIQ_CONFIG_T config; ++ int ret; ++ args.config_size = sizeof(config); ++ args.pconfig = &config; ++ RETRY(ret, ioctl(instance->fd, VCHIQ_IOC_GET_CONFIG, &args)); ++ if ((ret == 0) && (config.version >= VCHIQ_VERSION_MIN) && (config.version_min <= VCHIQ_VERSION)) ++ { ++ instance->used_services = 0; ++ vcos_mutex_create(&instance->mutex, "VCHIQ instance"); ++ instance->initialised = 1; ++ } ++ else ++ { ++ if (ret == 0) ++ { ++ vcos_log_error("Incompatible VCHIQ library - driver version %d (min %d), library version %d (min %d)", ++ config.version, config.version_min, VCHIQ_VERSION, VCHIQ_VERSION_MIN); ++ } ++ else ++ { ++ vcos_log_error("Very incompatible VCHIQ library - cannot retrieve driver version"); ++ } ++ close(instance->fd); ++ instance = NULL; ++ } ++ } ++ else ++ { ++ instance = NULL; ++ } ++ } ++ else if (instance->initialised > 0) ++ { ++ instance->initialised++; ++ } ++ ++ vcos_mutex_unlock(&vchiq_lib_mutex); ++ ++ return instance; ++} ++ ++static void * ++completion_thread(void *arg) ++{ ++ VCHIQ_INSTANCE_T instance = (VCHIQ_INSTANCE_T)arg; ++ VCHIQ_AWAIT_COMPLETION_T args; ++ VCHIQ_COMPLETION_DATA_T completions[8]; ++ void *msgbufs[8]; ++ ++ static const VCHI_CALLBACK_REASON_T vchiq_reason_to_vchi[] = ++ { ++ VCHI_CALLBACK_SERVICE_OPENED, // VCHIQ_SERVICE_OPENED ++ VCHI_CALLBACK_SERVICE_CLOSED, // VCHIQ_SERVICE_CLOSED ++ VCHI_CALLBACK_MSG_AVAILABLE, // VCHIQ_MESSAGE_AVAILABLE ++ VCHI_CALLBACK_BULK_SENT, // VCHIQ_BULK_TRANSMIT_DONE ++ VCHI_CALLBACK_BULK_RECEIVED, // VCHIQ_BULK_RECEIVE_DONE ++ VCHI_CALLBACK_BULK_TRANSMIT_ABORTED, // VCHIQ_BULK_TRANSMIT_ABORTED ++ VCHI_CALLBACK_BULK_RECEIVE_ABORTED, // VCHIQ_BULK_RECEIVE_ABORTED ++ }; ++ ++ args.count = vcos_countof(completions); ++ args.buf = completions; ++ args.msgbufsize = MSGBUF_SIZE; ++ args.msgbufcount = 0; ++ args.msgbufs = msgbufs; ++ ++ while (1) ++ { ++ int ret, i; ++ ++ while ((unsigned int)args.msgbufcount < vcos_countof(msgbufs)) ++ { ++ void *msgbuf = alloc_msgbuf(); ++ if (msgbuf) ++ { ++ msgbufs[args.msgbufcount++] = msgbuf; ++ } ++ else ++ { ++ fprintf(stderr, "vchiq_lib: failed to allocate a message buffer\n"); ++ vcos_demand(args.msgbufcount != 0); ++ } ++ } ++ ++ RETRY(ret, ioctl(instance->fd, VCHIQ_IOC_AWAIT_COMPLETION, &args)); ++ ++ if (ret <= 0) ++ break; ++ ++ for (i = 0; i < ret; i++) ++ { ++ VCHIQ_COMPLETION_DATA_T *completion = &completions[i]; ++ VCHIQ_SERVICE_T *service = (VCHIQ_SERVICE_T *)completion->service_userdata; ++ if (service->base.callback) ++ { ++ vcos_log_trace( "callback(%x, %x, %x, %x)", ++ completion->reason, (uint32_t)completion->header, ++ (uint32_t)&service->base, (uint32_t)completion->bulk_userdata ); ++ service->base.callback(completion->reason, completion->header, ++ &service->base, completion->bulk_userdata); ++ } ++ else if (service->vchi_callback) ++ { ++ VCHI_CALLBACK_REASON_T vchi_reason = ++ vchiq_reason_to_vchi[completion->reason]; ++ service->vchi_callback(service->base.userdata, vchi_reason, completion->bulk_userdata); ++ } ++ } ++ } ++ return NULL; ++} ++ ++static VCHIQ_STATUS_T ++create_service(VCHIQ_INSTANCE_T instance, ++ const VCHIQ_SERVICE_PARAMS_T *params, ++ VCHI_CALLBACK_T vchi_callback, ++ int is_open, ++ VCHIQ_SERVICE_HANDLE_T *pservice) ++{ ++ VCHIQ_SERVICE_T *service = NULL; ++ VCHIQ_STATUS_T status = VCHIQ_SUCCESS; ++ int i; ++ ++ if (!is_valid_instance(instance)) ++ return VCHIQ_ERROR; ++ ++ vcos_mutex_lock(&instance->mutex); ++ ++ /* Find a free service */ ++ if (is_open) ++ { ++ /* Find a free service */ ++ for (i = 0; i < instance->used_services; i++) ++ { ++ if (instance->services[i].handle == VCHIQ_INVALID_HANDLE) ++ { ++ service = &instance->services[i]; ++ break; ++ } ++ } ++ } ++ else ++ { ++ for (i = (instance->used_services - 1); i >= 0; i--) ++ { ++ VCHIQ_SERVICE_T *srv = &instance->services[i]; ++ if (srv->handle == VCHIQ_INVALID_HANDLE) ++ { ++ service = srv; ++ } ++ else if ( ++ (srv->base.fourcc == params->fourcc) && ++ ((srv->base.callback != params->callback) || ++ (srv->vchi_callback != vchi_callback))) ++ { ++ /* There is another server using this fourcc which doesn't match */ ++ service = NULL; ++ status = VCHIQ_ERROR; ++ break; ++ } ++ } ++ } ++ ++ if (!service && (status == VCHIQ_SUCCESS) && ++ (instance->used_services < VCHIQ_MAX_INSTANCE_SERVICES)) ++ service = &instance->services[instance->used_services++]; ++ ++ if (service) ++ { ++ VCHIQ_CREATE_SERVICE_T args; ++ int ret; ++ service->base.fourcc = params->fourcc; ++ service->base.callback = params->callback; ++ service->vchi_callback = vchi_callback; ++ service->base.userdata = params->userdata; ++ service->fd = instance->fd; ++ service->peek_size = -1; ++ service->peek_buf = NULL; ++ ++ args.params = *params; ++ args.params.userdata = service; ++ args.is_open = is_open; ++ args.is_vchi = (params->callback == NULL); ++ args.handle = -1; /* OUT parameter */ ++ RETRY(ret, ioctl(instance->fd, VCHIQ_IOC_CREATE_SERVICE, &args)); ++ if (ret == 0) ++ service->handle = args.handle; ++ else ++ status = VCHIQ_ERROR; ++ } ++ ++ *pservice = (status == VCHIQ_SUCCESS) ? &service->base : NULL; ++ ++ vcos_mutex_unlock(&instance->mutex); ++ ++ return status; ++} ++ ++static int ++fill_peek_buf(VCHI_SERVICE_T *service, ++ VCHI_FLAGS_T flags) ++{ ++ VCHIQ_DEQUEUE_MESSAGE_T args; ++ int ret = 0; ++ ++ vcos_assert(flags == VCHI_FLAGS_NONE || flags == VCHI_FLAGS_BLOCK_UNTIL_OP_COMPLETE); ++ ++ if (service->peek_size < 0) ++ { ++ if (!service->peek_buf) ++ service->peek_buf = alloc_msgbuf(); ++ ++ if (service->peek_buf) ++ { ++ args.handle = service->handle; ++ args.blocking = (flags == VCHI_FLAGS_BLOCK_UNTIL_OP_COMPLETE); ++ args.bufsize = MSGBUF_SIZE; ++ args.buf = service->peek_buf; ++ ++ RETRY(ret, ioctl(service->fd, VCHIQ_IOC_DEQUEUE_MESSAGE, &args)); ++ ++ if (ret >= 0) ++ { ++ service->peek_size = ret; ++ ret = 0; ++ } ++ else ++ { ++ ret = -1; ++ } ++ } ++ else ++ { ++ ret = -1; ++ } ++ } ++ ++ return ret; ++} ++ ++ ++static void * ++alloc_msgbuf(void) ++{ ++ void *msgbuf; ++ vcos_mutex_lock(&vchiq_lib_mutex); ++ msgbuf = free_msgbufs; ++ if (msgbuf) ++ free_msgbufs = *(void **)msgbuf; ++ vcos_mutex_unlock(&vchiq_lib_mutex); ++ if (!msgbuf) ++ msgbuf = malloc(MSGBUF_SIZE); ++ return msgbuf; ++} ++ ++static void ++free_msgbuf(void *buf) ++{ ++ vcos_mutex_lock(&vchiq_lib_mutex); ++ *(void **)buf = free_msgbufs; ++ free_msgbufs = buf; ++ vcos_mutex_unlock(&vchiq_lib_mutex); ++} +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_memdrv.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_memdrv.h 2013-07-26 19:32:00.000000000 +0000 +@@ -0,0 +1,45 @@ ++/***************************************************************************** ++* Copyright 2001 - 2010 Broadcom Corporation. All rights reserved. ++* ++* Unless you and Broadcom execute a separate written software license ++* agreement governing use of this software, this software is licensed to you ++* under the terms of the GNU General Public License version 2, available at ++* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). ++* ++* Notwithstanding the above, under no circumstances may you combine this ++* software in any way with any other Broadcom software provided under a ++* license other than the GPL, without Broadcom's express prior written ++* consent. ++*****************************************************************************/ ++ ++#ifndef VCHIQ_MEMDRV_H ++#define VCHIQ_MEMDRV_H ++ ++/* ---- Include Files ----------------------------------------------------- */ ++ ++#include ++#include "vchiq_if.h" ++ ++/* ---- Constants and Types ---------------------------------------------- */ ++ ++typedef struct ++{ ++ void *armSharedMemVirt; ++ dma_addr_t armSharedMemPhys; ++ size_t armSharedMemSize; ++ ++ void *vcSharedMemVirt; ++ dma_addr_t vcSharedMemPhys; ++ size_t vcSharedMemSize; ++ ++} VCHIQ_SHARED_MEM_INFO_T; ++ ++/* ---- Variable Externs ------------------------------------------------- */ ++ ++/* ---- Function Prototypes ---------------------------------------------- */ ++ ++void vchiq_get_shared_mem_info( VCHIQ_SHARED_MEM_INFO_T *info ); ++ ++VCHIQ_STATUS_T vchiq_memdrv_initialise(void); ++ ++#endif +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_pagelist.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_pagelist.h 2013-07-26 19:32:00.000000000 +0000 +@@ -0,0 +1,43 @@ ++/* ++ * Copyright (c) 2010-2011 Broadcom Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++#ifndef VCHIQ_PAGELIST_H ++#define VCHIQ_PAGELIST_H ++ ++#ifndef PAGE_SIZE ++#define PAGE_SIZE 4096 ++#endif ++#define CACHE_LINE_SIZE 32 ++#define PAGELIST_WRITE 0 ++#define PAGELIST_READ 1 ++#define PAGELIST_READ_WITH_FRAGMENTS 2 ++ ++typedef struct pagelist_struct { ++ unsigned long length; ++ unsigned short type; ++ unsigned short offset; ++ unsigned long addrs[1]; /* N.B. 12 LSBs hold the number of following ++ pages at consecutive addresses. */ ++} PAGELIST_T; ++ ++typedef struct fragments_struct { ++ char headbuf[CACHE_LINE_SIZE]; ++ char tailbuf[CACHE_LINE_SIZE]; ++} FRAGMENTS_T; ++ ++#endif /* VCHIQ_PAGELIST_H */ +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_shim.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_shim.c 2013-07-26 19:32:00.000000000 +0000 +@@ -0,0 +1,970 @@ ++/* ++ * Copyright (c) 2010-2011 Broadcom Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++#include "interface/vchi/vchi.h" ++#include "vchiq.h" ++#include "vchiq_core.h" ++ ++#include "vchiq_util.h" ++ ++#include ++ ++#if defined(__KERNEL__) ++#include ++#endif ++ ++#define vchiq_status_to_vchi(status) ((int32_t)status) ++ ++typedef struct { ++ VCHIQ_SERVICE_HANDLE_T handle; ++ ++ VCHIU_QUEUE_T queue; ++ ++ VCHI_CALLBACK_T callback; ++ void *callback_param; ++} SHIM_SERVICE_T; ++ ++/* ---------------------------------------------------------------------- ++ * return pointer to the mphi message driver function table ++ * -------------------------------------------------------------------- */ ++#ifdef WIN32 ++const VCHI_MESSAGE_DRIVER_T * ++mphi_get_func_table( void ) ++{ ++ return NULL; ++} ++#endif ++ ++/* ---------------------------------------------------------------------- ++ * return pointer to the mphi message driver function table ++ * -------------------------------------------------------------------- */ ++const VCHI_MESSAGE_DRIVER_T * ++vchi_mphi_message_driver_func_table( void ) ++{ ++ return NULL; ++} ++ ++/* ---------------------------------------------------------------------- ++ * return a pointer to the 'single' connection driver fops ++ * -------------------------------------------------------------------- */ ++const VCHI_CONNECTION_API_T * ++single_get_func_table( void ) ++{ ++ return NULL; ++} ++ ++VCHI_CONNECTION_T * vchi_create_connection( const VCHI_CONNECTION_API_T * function_table, ++ const VCHI_MESSAGE_DRIVER_T * low_level) ++{ ++ vcos_unused(function_table); ++ vcos_unused(low_level); ++ return NULL; ++} ++ ++/*********************************************************** ++ * Name: vchi_msg_peek ++ * ++ * Arguments: const VCHI_SERVICE_HANDLE_T handle, ++ * void **data, ++ * uint32_t *msg_size, ++ * VCHI_FLAGS_T flags ++ * ++ * Description: Routine to return a pointer to the current message (to allow in place processing) ++ * The message can be removed using vchi_msg_remove when you're finished ++ * ++ * Returns: int32_t - success == 0 ++ * ++ ***********************************************************/ ++int32_t vchi_msg_peek( VCHI_SERVICE_HANDLE_T handle, ++ void **data, ++ uint32_t *msg_size, ++ VCHI_FLAGS_T flags ) ++{ ++ SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle; ++ VCHIQ_HEADER_T *header; ++ ++ vcos_assert(flags == VCHI_FLAGS_NONE || flags == VCHI_FLAGS_BLOCK_UNTIL_OP_COMPLETE); ++ ++ if (flags == VCHI_FLAGS_NONE) ++ if (vchiu_queue_is_empty(&service->queue)) ++ return -1; ++ ++ header = vchiu_queue_peek(&service->queue); ++ ++ *data = header->data; ++ *msg_size = header->size; ++ ++ return 0; ++} ++ ++/*********************************************************** ++ * Name: vchi_msg_remove ++ * ++ * Arguments: const VCHI_SERVICE_HANDLE_T handle, ++ * ++ * Description: Routine to remove a message (after it has been read with vchi_msg_peek) ++ * ++ * Returns: int32_t - success == 0 ++ * ++ ***********************************************************/ ++int32_t vchi_msg_remove( VCHI_SERVICE_HANDLE_T handle ) ++{ ++ SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle; ++ VCHIQ_HEADER_T *header; ++ ++ header = vchiu_queue_pop(&service->queue); ++ ++ vchiq_release_message(service->handle, header); ++ ++ return 0; ++} ++ ++/*********************************************************** ++ * Name: vchi_msg_queue ++ * ++ * Arguments: VCHI_SERVICE_HANDLE_T handle, ++ * const void *data, ++ * uint32_t data_size, ++ * VCHI_FLAGS_T flags, ++ * void *msg_handle, ++ * ++ * Description: Thin wrapper to queue a message onto a connection ++ * ++ * Returns: int32_t - success == 0 ++ * ++ ***********************************************************/ ++int32_t vchi_msg_queue( VCHI_SERVICE_HANDLE_T handle, ++ const void * data, ++ uint32_t data_size, ++ VCHI_FLAGS_T flags, ++ void * msg_handle ) ++{ ++ SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle; ++ VCHIQ_ELEMENT_T element = {data, data_size}; ++ VCHIQ_STATUS_T status; ++ ++ vcos_unused(msg_handle); ++ ++ vcos_assert(flags == VCHI_FLAGS_BLOCK_UNTIL_QUEUED); ++ ++ status = vchiq_queue_message(service->handle, &element, 1); ++ ++ // On some platforms, like linux kernel, vchiq_queue_message() may return ++ // VCHIQ_RETRY, so we need to implment a retry mechanism since this ++ // function is supposed to block until queued ++ while ( status == VCHIQ_RETRY ) ++ { ++ vcos_sleep( 1 ); ++ status = vchiq_queue_message(service->handle, &element, 1); ++ } ++ ++ return vchiq_status_to_vchi(status); ++} ++ ++/*********************************************************** ++ * Name: vchi_bulk_queue_receive ++ * ++ * Arguments: VCHI_BULK_HANDLE_T handle, ++ * void *data_dst, ++ * const uint32_t data_size, ++ * VCHI_FLAGS_T flags ++ * void *bulk_handle ++ * ++ * Description: Routine to setup a rcv buffer ++ * ++ * Returns: int32_t - success == 0 ++ * ++ ***********************************************************/ ++int32_t vchi_bulk_queue_receive( VCHI_SERVICE_HANDLE_T handle, ++ void * data_dst, ++ uint32_t data_size, ++ VCHI_FLAGS_T flags, ++ void * bulk_handle ) ++{ ++ SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle; ++ VCHIQ_BULK_MODE_T mode; ++ VCHIQ_STATUS_T status; ++ ++ switch ((int)flags) { ++ case VCHI_FLAGS_CALLBACK_WHEN_OP_COMPLETE | VCHI_FLAGS_BLOCK_UNTIL_QUEUED: ++ vcos_assert(service->callback); ++ mode = VCHIQ_BULK_MODE_CALLBACK; ++ break; ++ case VCHI_FLAGS_BLOCK_UNTIL_OP_COMPLETE: ++ mode = VCHIQ_BULK_MODE_BLOCKING; ++ break; ++ case VCHI_FLAGS_BLOCK_UNTIL_QUEUED: ++ case VCHI_FLAGS_NONE: ++ mode = VCHIQ_BULK_MODE_NOCALLBACK; ++ break; ++ default: ++ vcos_assert(0); ++ return vchiq_status_to_vchi(VCHIQ_ERROR); ++ } ++ ++ status = vchiq_bulk_receive(service->handle, data_dst, data_size, ++ bulk_handle, mode); ++ ++ // On some platforms, like linux kernel, vchiq_bulk_receive() may return ++ // VCHIQ_RETRY, so we need to implment a retry mechanism since this ++ // function is supposed to block until queued ++ while ( status == VCHIQ_RETRY ) ++ { ++ vcos_sleep( 1 ); ++ status = vchiq_bulk_receive(service->handle, data_dst, data_size, ++ bulk_handle, mode); ++ } ++ ++ return vchiq_status_to_vchi(status); ++} ++ ++/*********************************************************** ++ * Name: vchi_bulk_queue_receive_reloc ++ * ++ * Arguments: VCHI_BULK_HANDLE_T handle, ++ * VCHI_MEM_HANDLE_T h ++ * uint32_t offset ++ * const uint32_t data_size, ++ * VCHI_FLAGS_T flags ++ * void *bulk_handle ++ * ++ * Description: Routine to setup a relocatable rcv buffer ++ * ++ * Returns: int32_t - success == 0 ++ * ++ ***********************************************************/ ++int32_t vchi_bulk_queue_receive_reloc( const VCHI_SERVICE_HANDLE_T handle, ++ VCHI_MEM_HANDLE_T h, ++ uint32_t offset, ++ uint32_t data_size, ++ const VCHI_FLAGS_T flags, ++ void * const bulk_handle ) ++{ ++ SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle; ++ VCHIQ_BULK_MODE_T mode; ++ VCHIQ_STATUS_T status; ++ ++ switch ((int)flags) { ++ case VCHI_FLAGS_CALLBACK_WHEN_OP_COMPLETE | VCHI_FLAGS_BLOCK_UNTIL_QUEUED: ++ vcos_assert(service->callback); ++ mode = VCHIQ_BULK_MODE_CALLBACK; ++ break; ++ case VCHI_FLAGS_BLOCK_UNTIL_OP_COMPLETE: ++ mode = VCHIQ_BULK_MODE_BLOCKING; ++ break; ++ case VCHI_FLAGS_BLOCK_UNTIL_QUEUED: ++ case VCHI_FLAGS_NONE: ++ mode = VCHIQ_BULK_MODE_NOCALLBACK; ++ break; ++ default: ++ vcos_assert(0); ++ return vchiq_status_to_vchi(VCHIQ_ERROR); ++ } ++ ++ status = vchiq_bulk_receive_handle(service->handle, h, (void*)offset, ++ data_size, bulk_handle, mode); ++ ++ // On some platforms, like linux kernel, vchiq_bulk_receive_handle() may ++ // return VCHIQ_RETRY, so we need to implment a retry mechanism since ++ // this function is supposed to block until queued ++ while ( status == VCHIQ_RETRY ) ++ { ++ vcos_sleep( 1 ); ++ status = vchiq_bulk_receive_handle(service->handle, h, (void*)offset, ++ data_size, bulk_handle, mode); ++ } ++ ++ return vchiq_status_to_vchi(status); ++} ++ ++/*********************************************************** ++ * Name: vchi_bulk_queue_transmit ++ * ++ * Arguments: VCHI_BULK_HANDLE_T handle, ++ * const void *data_src, ++ * uint32_t data_size, ++ * VCHI_FLAGS_T flags, ++ * void *bulk_handle ++ * ++ * Description: Routine to transmit some data ++ * ++ * Returns: int32_t - success == 0 ++ * ++ ***********************************************************/ ++int32_t vchi_bulk_queue_transmit( VCHI_SERVICE_HANDLE_T handle, ++ const void * data_src, ++ uint32_t data_size, ++ VCHI_FLAGS_T flags, ++ void * bulk_handle ) ++{ ++ SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle; ++ VCHIQ_BULK_MODE_T mode; ++ VCHIQ_STATUS_T status; ++ ++ switch ((int)flags) { ++ case VCHI_FLAGS_CALLBACK_WHEN_OP_COMPLETE | VCHI_FLAGS_BLOCK_UNTIL_QUEUED: ++ vcos_assert(service->callback); ++ mode = VCHIQ_BULK_MODE_CALLBACK; ++ break; ++ case VCHI_FLAGS_BLOCK_UNTIL_DATA_READ: ++ case VCHI_FLAGS_BLOCK_UNTIL_OP_COMPLETE: ++ mode = VCHIQ_BULK_MODE_BLOCKING; ++ break; ++ case VCHI_FLAGS_BLOCK_UNTIL_QUEUED: ++ case VCHI_FLAGS_NONE: ++ mode = VCHIQ_BULK_MODE_NOCALLBACK; ++ break; ++ default: ++ vcos_assert(0); ++ return vchiq_status_to_vchi(VCHIQ_ERROR); ++ } ++ ++ status = vchiq_bulk_transmit(service->handle, data_src, data_size, ++ bulk_handle, mode); ++ ++ // On some platforms, like linux kernel, vchiq_bulk_transmit() may return ++ // VCHIQ_RETRY, so we need to implment a retry mechanism since this ++ // function is supposed to block until queued ++ while ( status == VCHIQ_RETRY ) ++ { ++ vcos_sleep( 1 ); ++ status = vchiq_bulk_transmit(service->handle, data_src, data_size, ++ bulk_handle, mode); ++ } ++ ++ return vchiq_status_to_vchi(status); ++} ++ ++/*********************************************************** ++ * Name: vchi_bulk_queue_transmit_reloc ++ * ++ * Arguments: VCHI_BULK_HANDLE_T handle, ++ * VCHI_MEM_HANDLE_T h_src, ++ * uint32_t offset, ++ * uint32_t data_size, ++ * VCHI_FLAGS_T flags, ++ * void *bulk_handle ++ * ++ * Description: Routine to transmit some data from a relocatable buffer ++ * ++ * Returns: int32_t - success == 0 ++ * ++ ***********************************************************/ ++ ++int32_t vchi_bulk_queue_transmit_reloc( VCHI_SERVICE_HANDLE_T handle, ++ VCHI_MEM_HANDLE_T h_src, ++ uint32_t offset, ++ uint32_t data_size, ++ VCHI_FLAGS_T flags, ++ void * const bulk_handle ) ++{ ++ SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle; ++ VCHIQ_BULK_MODE_T mode; ++ VCHIQ_STATUS_T status; ++ ++ switch ((int)flags) { ++ case VCHI_FLAGS_CALLBACK_WHEN_OP_COMPLETE | VCHI_FLAGS_BLOCK_UNTIL_QUEUED: ++ vcos_assert(service->callback); ++ mode = VCHIQ_BULK_MODE_CALLBACK; ++ break; ++ case VCHI_FLAGS_BLOCK_UNTIL_DATA_READ: ++ case VCHI_FLAGS_BLOCK_UNTIL_OP_COMPLETE: ++ mode = VCHIQ_BULK_MODE_BLOCKING; ++ break; ++ case VCHI_FLAGS_BLOCK_UNTIL_QUEUED: ++ case VCHI_FLAGS_NONE: ++ mode = VCHIQ_BULK_MODE_NOCALLBACK; ++ break; ++ default: ++ vcos_assert(0); ++ return vchiq_status_to_vchi(VCHIQ_ERROR); ++ } ++ ++ status = vchiq_bulk_transmit_handle(service->handle, h_src, (void*)offset, ++ data_size, bulk_handle, mode); ++ ++ // On some platforms, like linux kernel, vchiq_bulk_transmit_handle() may ++ // return VCHIQ_RETRY, so we need to implment a retry mechanism since this ++ // function is supposed to block until queued ++ while ( status == VCHIQ_RETRY ) ++ { ++ vcos_sleep( 1 ); ++ status = vchiq_bulk_transmit_handle(service->handle, h_src, (void*)offset, ++ data_size, bulk_handle, mode); ++ } ++ ++ return vchiq_status_to_vchi(status); ++} ++ ++/*********************************************************** ++ * Name: vchi_msg_dequeue ++ * ++ * Arguments: VCHI_SERVICE_HANDLE_T handle, ++ * void *data, ++ * uint32_t max_data_size_to_read, ++ * uint32_t *actual_msg_size ++ * VCHI_FLAGS_T flags ++ * ++ * Description: Routine to dequeue a message into the supplied buffer ++ * ++ * Returns: int32_t - success == 0 ++ * ++ ***********************************************************/ ++int32_t vchi_msg_dequeue( VCHI_SERVICE_HANDLE_T handle, ++ void *data, ++ uint32_t max_data_size_to_read, ++ uint32_t *actual_msg_size, ++ VCHI_FLAGS_T flags ) ++{ ++ SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle; ++ VCHIQ_HEADER_T *header; ++ ++ vcos_assert(flags == VCHI_FLAGS_NONE || flags == VCHI_FLAGS_BLOCK_UNTIL_OP_COMPLETE); ++ ++ if (flags == VCHI_FLAGS_NONE) ++ if (vchiu_queue_is_empty(&service->queue)) ++ return -1; ++ ++ header = vchiu_queue_pop(&service->queue); ++ ++ memcpy(data, header->data, header->size < max_data_size_to_read ? header->size : max_data_size_to_read); ++ ++ *actual_msg_size = header->size; ++ ++ vchiq_release_message(service->handle, header); ++ ++ return 0; ++} ++ ++/*********************************************************** ++ * Name: vchi_msg_queuev ++ * ++ * Arguments: VCHI_SERVICE_HANDLE_T handle, ++ * const void *data, ++ * uint32_t data_size, ++ * VCHI_FLAGS_T flags, ++ * void *msg_handle ++ * ++ * Description: Thin wrapper to queue a message onto a connection ++ * ++ * Returns: int32_t - success == 0 ++ * ++ ***********************************************************/ ++ ++vcos_static_assert(sizeof(VCHI_MSG_VECTOR_T) == sizeof(VCHIQ_ELEMENT_T)); ++vcos_static_assert(offsetof(VCHI_MSG_VECTOR_T, vec_base) == offsetof(VCHIQ_ELEMENT_T, data)); ++vcos_static_assert(offsetof(VCHI_MSG_VECTOR_T, vec_len) == offsetof(VCHIQ_ELEMENT_T, size)); ++ ++int32_t vchi_msg_queuev( VCHI_SERVICE_HANDLE_T handle, ++ VCHI_MSG_VECTOR_T * vector, ++ uint32_t count, ++ VCHI_FLAGS_T flags, ++ void *msg_handle ) ++{ ++ SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle; ++ ++ vcos_unused(msg_handle); ++ ++ vcos_assert(flags == VCHI_FLAGS_BLOCK_UNTIL_QUEUED); ++ ++ return vchiq_status_to_vchi(vchiq_queue_message(service->handle, (const VCHIQ_ELEMENT_T *)vector, count)); ++} ++ ++#ifdef USE_MEMMGR ++ ++/*********************************************************** ++ * Name: vchi_msg_queuev_ex ++ * ++ * Arguments: VCHI_SERVICE_HANDLE_T handle, ++ * VCHI_MSG_VECTOR_EX_T *vector ++ * uint32_t count ++ * VCHI_FLAGS_T flags, ++ * void *msg_handle ++ * ++ * Description: Thin wrapper to queue an array of messages onto a connection ++ * Supports resolving MEM_HANDLE's at last possible moment to avoid deadlocks. ++ * ++ * Currently just a shim, so deadlocks are still possible! ++ * ++ * Returns: int32_t - success == 0 ++ * ++ ***********************************************************/ ++int32_t vchi_msg_queuev_ex( const VCHI_SERVICE_HANDLE_T handle, ++ VCHI_MSG_VECTOR_EX_T * const vector, ++ const uint32_t count, ++ const VCHI_FLAGS_T flags, ++ void * const msg_handle ) ++{ ++ int32_t success = -1; ++ // For now, we don't actually support sending anything other than ++ // a pointer, so handles have to be patched up; this is likely ++ // to cause deadlocks. This code is not designed to be either ++ // pretty, efficient, or deadlock-free. ++ ++ #define max_vecs 16 ++ VCHI_MSG_VECTOR_T copy[max_vecs]; ++ const uint8_t *orig[max_vecs]; ++ ++ int i; ++ vcos_unused(msg_handle); ++ ++ if (count > sizeof(copy)/sizeof(copy[0])) ++ { ++ vcos_assert(0); ++ return -1; ++ } ++ ++ for (i=0; iu.ptr.vec_base; ++ copy[i].vec_len = v->u.ptr.vec_len; ++ break; ++ case VCHI_VEC_HANDLE: ++ vcos_assert(v->u.handle.offset+v->u.handle.vec_len <= mem_get_size(v->u.handle.handle)); ++ copy[i].vec_base = (uint8_t*)mem_lock(v->u.handle.handle) + v->u.handle.offset; ++ orig[i] = copy[i].vec_base; ++ copy[i].vec_len = v->u.handle.vec_len; ++ break; ++ case VCHI_VEC_LIST: ++ vcos_assert(0); // FIXME: implement this ++ break; ++ default: ++ vcos_assert(0); ++ } ++ } ++ success = vchi_msg_queuev( handle, ++ copy, ++ count, ++ flags &~ VCHI_FLAGS_INTERNAL, ++ msg_handle ); ++ if (vcos_verify(success == 0)) ++ { ++ // now we need to patch up the vectors if any have been only partially consumed, and ++ // unlock memory handles. ++ ++ for (i=0; iu.ptr.vec_base = copy[i].vec_base; ++ v->u.ptr.vec_len = copy[i].vec_len; ++ } ++ break; ++ case VCHI_VEC_HANDLE: ++ mem_unlock(v->u.handle.handle); ++ if (flags & VCHI_FLAGS_ALLOW_PARTIAL) ++ { ++ const uint8_t *old = orig[i]; ++ uint32_t change = (const uint8_t*)copy[i].vec_base-old; ++ v->u.handle.offset += change; ++ v->u.handle.vec_len -= change; ++ } ++ break; ++ default: ++ vcos_assert(0); ++ } ++ } ++ } ++ ++ return vchiq_status_to_vchi(success); ++} ++ ++#endif ++ ++/*********************************************************** ++ * Name: vchi_held_msg_release ++ * ++ * Arguments: VCHI_HELD_MSG_T *message ++ * ++ * Description: Routine to release a held message (after it has been read with vchi_msg_hold) ++ * ++ * Returns: int32_t - success == 0 ++ * ++ ***********************************************************/ ++int32_t vchi_held_msg_release( VCHI_HELD_MSG_T *message ) ++{ ++ vchiq_release_message((VCHIQ_SERVICE_HANDLE_T)message->service, (VCHIQ_HEADER_T *)message->message); ++ ++ return 0; ++} ++ ++/*********************************************************** ++ * Name: vchi_msg_hold ++ * ++ * Arguments: VCHI_SERVICE_HANDLE_T handle, ++ * void **data, ++ * uint32_t *msg_size, ++ * VCHI_FLAGS_T flags, ++ * VCHI_HELD_MSG_T *message_handle ++ * ++ * Description: Routine to return a pointer to the current message (to allow in place processing) ++ * The message is dequeued - don't forget to release the message using ++ * vchi_held_msg_release when you're finished ++ * ++ * Returns: int32_t - success == 0 ++ * ++ ***********************************************************/ ++int32_t vchi_msg_hold( VCHI_SERVICE_HANDLE_T handle, ++ void **data, ++ uint32_t *msg_size, ++ VCHI_FLAGS_T flags, ++ VCHI_HELD_MSG_T *message_handle ) ++{ ++ SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle; ++ VCHIQ_HEADER_T *header; ++ ++ vcos_assert(flags == VCHI_FLAGS_NONE || flags == VCHI_FLAGS_BLOCK_UNTIL_OP_COMPLETE); ++ ++ if (flags == VCHI_FLAGS_NONE) ++ if (vchiu_queue_is_empty(&service->queue)) ++ return -1; ++ ++ header = vchiu_queue_pop(&service->queue); ++ ++ *data = header->data; ++ *msg_size = header->size; ++ ++ message_handle->service = (struct opaque_vchi_service_t *)service->handle; ++ message_handle->message = header; ++ ++ return 0; ++} ++ ++/*********************************************************** ++ * Name: vchi_initialise ++ * ++ * Arguments: VCHI_INSTANCE_T *instance_handle ++ * VCHI_CONNECTION_T **connections ++ * const uint32_t num_connections ++ * ++ * Description: Initialises the hardware but does not transmit anything ++ * When run as a Host App this will be called twice hence the need ++ * to malloc the state information ++ * ++ * Returns: 0 if successful, failure otherwise ++ * ++ ***********************************************************/ ++ ++int32_t vchi_initialise( VCHI_INSTANCE_T *instance_handle ) ++{ ++ VCHIQ_INSTANCE_T instance; ++ VCHIQ_STATUS_T status; ++ ++ status = vchiq_initialise(&instance); ++ ++ *instance_handle = (VCHI_INSTANCE_T)instance; ++ ++ return vchiq_status_to_vchi(status); ++} ++ ++/*********************************************************** ++ * Name: vchi_connect ++ * ++ * Arguments: VCHI_CONNECTION_T **connections ++ * const uint32_t num_connections ++ * VCHI_INSTANCE_T instance_handle ) ++ * ++ * Description: Starts the command service on each connection, ++ * causing INIT messages to be pinged back and forth ++ * ++ * Returns: 0 if successful, failure otherwise ++ * ++ ***********************************************************/ ++int32_t vchi_connect( VCHI_CONNECTION_T **connections, ++ const uint32_t num_connections, ++ VCHI_INSTANCE_T instance_handle ) ++{ ++ VCHIQ_INSTANCE_T instance = (VCHIQ_INSTANCE_T)instance_handle; ++ ++ vcos_unused(connections); ++ vcos_unused(num_connections); ++ ++ return vchiq_connect(instance); ++} ++ ++ ++/*********************************************************** ++ * Name: vchi_disconnect ++ * ++ * Arguments: VCHI_INSTANCE_T instance_handle ++ * ++ * Description: Stops the command service on each connection, ++ * causing DE-INIT messages to be pinged back and forth ++ * ++ * Returns: 0 if successful, failure otherwise ++ * ++ ***********************************************************/ ++int32_t vchi_disconnect( VCHI_INSTANCE_T instance_handle ) ++{ ++ VCHIQ_INSTANCE_T instance = (VCHIQ_INSTANCE_T)instance_handle; ++ return vchiq_status_to_vchi(vchiq_shutdown(instance)); ++} ++ ++ ++/*********************************************************** ++ * Name: vchi_service_open ++ * Name: vchi_service_create ++ * ++ * Arguments: VCHI_INSTANCE_T *instance_handle ++ * SERVICE_CREATION_T *setup, ++ * VCHI_SERVICE_HANDLE_T *handle ++ * ++ * Description: Routine to open a service ++ * ++ * Returns: int32_t - success == 0 ++ * ++ ***********************************************************/ ++ ++static VCHIQ_STATUS_T shim_callback(VCHIQ_REASON_T reason, VCHIQ_HEADER_T *header, VCHIQ_SERVICE_HANDLE_T handle, void *bulk_user) ++{ ++ SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)VCHIQ_GET_SERVICE_USERDATA(handle); ++ ++ switch (reason) { ++ case VCHIQ_MESSAGE_AVAILABLE: ++ vchiu_queue_push(&service->queue, header); ++ ++ if (service->callback) ++ service->callback(service->callback_param, VCHI_CALLBACK_MSG_AVAILABLE, NULL); ++ break; ++ case VCHIQ_BULK_TRANSMIT_DONE: ++ if (service->callback) ++ service->callback(service->callback_param, VCHI_CALLBACK_BULK_SENT, bulk_user); ++ break; ++ case VCHIQ_BULK_RECEIVE_DONE: ++ if (service->callback) ++ service->callback(service->callback_param, VCHI_CALLBACK_BULK_RECEIVED, bulk_user); ++ break; ++ case VCHIQ_SERVICE_CLOSED: ++ if (service->callback) ++ service->callback(service->callback_param, VCHI_CALLBACK_SERVICE_CLOSED, NULL); ++ break; ++ case VCHIQ_SERVICE_OPENED: ++ /* No equivalent VCHI reason */ ++ break; ++ case VCHIQ_BULK_TRANSMIT_ABORTED: ++ if (service->callback) ++ service->callback(service->callback_param, VCHI_CALLBACK_BULK_TRANSMIT_ABORTED, bulk_user); ++ break; ++ case VCHIQ_BULK_RECEIVE_ABORTED: ++ if (service->callback) ++ service->callback(service->callback_param, VCHI_CALLBACK_BULK_RECEIVE_ABORTED, bulk_user); ++ break; ++ default: ++ vcos_assert(0); ++ break; ++ } ++ ++ return VCHIQ_SUCCESS; ++} ++ ++static SHIM_SERVICE_T *service_alloc(VCHIQ_INSTANCE_T instance, ++ SERVICE_CREATION_T *setup) ++{ ++ SHIM_SERVICE_T *service = vcos_calloc(1, sizeof(SHIM_SERVICE_T), "vchiq_shim"); ++ ++ vcos_unused(instance); ++ ++ if (service) ++ { ++ if (vchiu_queue_init(&service->queue, 64)) ++ { ++ service->callback = setup->callback; ++ service->callback_param = setup->callback_param; ++ } ++ else ++ { ++ vcos_free(service); ++ service = NULL; ++ } ++ } ++ ++ return service; ++} ++ ++static void service_free(SHIM_SERVICE_T *service) ++{ ++ if (service) ++ { ++ vchiu_queue_delete(&service->queue); ++ vcos_free((void*)service); ++ } ++} ++ ++int32_t vchi_service_open( VCHI_INSTANCE_T instance_handle, ++ SERVICE_CREATION_T *setup, ++ VCHI_SERVICE_HANDLE_T *handle) ++{ ++ VCHIQ_INSTANCE_T instance = (VCHIQ_INSTANCE_T)instance_handle; ++ SHIM_SERVICE_T *service = service_alloc(instance, setup); ++ if (service) ++ { ++ VCHIQ_STATUS_T status = vchiq_open_service(instance, setup->service_id, shim_callback, service, &service->handle); ++ if (status != VCHIQ_SUCCESS) ++ { ++ service_free(service); ++ service = NULL; ++ } ++ } ++ ++ *handle = (VCHI_SERVICE_HANDLE_T)service; ++ ++ return (service != NULL) ? 0 : -1; ++} ++ ++int32_t vchi_service_create( VCHI_INSTANCE_T instance_handle, ++ SERVICE_CREATION_T *setup, ++ VCHI_SERVICE_HANDLE_T *handle ) ++{ ++ VCHIQ_INSTANCE_T instance = (VCHIQ_INSTANCE_T)instance_handle; ++ SHIM_SERVICE_T *service = service_alloc(instance, setup); ++ if (service) ++ { ++ VCHIQ_STATUS_T status = vchiq_add_service(instance, setup->service_id, shim_callback, service, &service->handle); ++ if (status != VCHIQ_SUCCESS) ++ { ++ service_free(service); ++ service = NULL; ++ } ++ } ++ ++ *handle = (VCHI_SERVICE_HANDLE_T)service; ++ ++ return (service != NULL) ? 0 : -1; ++} ++ ++int32_t vchi_service_close( const VCHI_SERVICE_HANDLE_T handle ) ++{ ++ vcos_unused(handle); ++ ++ // YTI?? ++ return 0; ++} ++ ++/* ---------------------------------------------------------------------- ++ * read a uint32_t from buffer. ++ * network format is defined to be little endian ++ * -------------------------------------------------------------------- */ ++uint32_t ++vchi_readbuf_uint32( const void *_ptr ) ++{ ++ const unsigned char *ptr = _ptr; ++ return ptr[0] | (ptr[1] << 8) | (ptr[2] << 16) | (ptr[3] << 24); ++} ++ ++/* ---------------------------------------------------------------------- ++ * write a uint32_t to buffer. ++ * network format is defined to be little endian ++ * -------------------------------------------------------------------- */ ++void ++vchi_writebuf_uint32( void *_ptr, uint32_t value ) ++{ ++ unsigned char *ptr = _ptr; ++ ptr[0] = (unsigned char)((value >> 0) & 0xFF); ++ ptr[1] = (unsigned char)((value >> 8) & 0xFF); ++ ptr[2] = (unsigned char)((value >> 16) & 0xFF); ++ ptr[3] = (unsigned char)((value >> 24) & 0xFF); ++} ++ ++/* ---------------------------------------------------------------------- ++ * read a uint16_t from buffer. ++ * network format is defined to be little endian ++ * -------------------------------------------------------------------- */ ++uint16_t ++vchi_readbuf_uint16( const void *_ptr ) ++{ ++ const unsigned char *ptr = _ptr; ++ return ptr[0] | (ptr[1] << 8); ++} ++ ++/* ---------------------------------------------------------------------- ++ * write a uint16_t into the buffer. ++ * network format is defined to be little endian ++ * -------------------------------------------------------------------- */ ++void ++vchi_writebuf_uint16( void *_ptr, uint16_t value ) ++{ ++ unsigned char *ptr = _ptr; ++ ptr[0] = (value >> 0) & 0xFF; ++ ptr[1] = (value >> 8) & 0xFF; ++} ++ ++/*********************************************************** ++ * Name: vchi_service_use ++ * ++ * Arguments: const VCHI_SERVICE_HANDLE_T handle ++ * ++ * Description: Routine to increment refcount on a service ++ * ++ * Returns: void ++ * ++ ***********************************************************/ ++int32_t vchi_service_use( const VCHI_SERVICE_HANDLE_T handle ) ++{ ++ int32_t ret = -1; ++ SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle; ++ if(service) ++ { ++ ret = vchiq_status_to_vchi(vchiq_use_service(service->handle)); ++ } ++ return ret; ++} ++ ++/*********************************************************** ++ * Name: vchi_service_release ++ * ++ * Arguments: const VCHI_SERVICE_HANDLE_T handle ++ * ++ * Description: Routine to decrement refcount on a service ++ * ++ * Returns: void ++ * ++ ***********************************************************/ ++int32_t vchi_service_release( const VCHI_SERVICE_HANDLE_T handle ) ++{ ++ int32_t ret = -1; ++ SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle; ++ if(service) ++ { ++ ret = vchiq_status_to_vchi(vchiq_release_service(service->handle)); ++ } ++ return ret; ++} ++ ++#if defined(__KERNEL__) ++EXPORT_SYMBOL(vchi_initialise); ++EXPORT_SYMBOL(vchi_connect); ++EXPORT_SYMBOL(vchi_bulk_queue_transmit); ++EXPORT_SYMBOL(vchi_msg_dequeue); ++EXPORT_SYMBOL(vchi_msg_queue); ++EXPORT_SYMBOL(vchi_msg_queuev); ++EXPORT_SYMBOL(vchi_service_close); ++EXPORT_SYMBOL(vchi_service_open); ++EXPORT_SYMBOL(vchi_service_create); ++EXPORT_SYMBOL(vchi_service_use); ++EXPORT_SYMBOL(vchi_service_release); ++#endif +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_util.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_util.c 2013-07-26 19:32:00.000000000 +0000 +@@ -0,0 +1,97 @@ ++/* ++ * Copyright (c) 2010-2011 Broadcom Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++#include "vchiq_util.h" ++ ++#if !defined(__KERNEL__) ++#include ++#endif ++ ++static __inline int is_pow2(int i) ++{ ++ return i && !(i & (i - 1)); ++} ++ ++int vchiu_queue_init(VCHIU_QUEUE_T *queue, int size) ++{ ++ vcos_assert(is_pow2(size)); ++ ++ queue->size = size; ++ queue->read = 0; ++ queue->write = 0; ++ ++ vcos_event_create(&queue->pop, "vchiu"); ++ vcos_event_create(&queue->push, "vchiu"); ++ ++ queue->storage = vcos_malloc(size * sizeof(VCHIQ_HEADER_T *), VCOS_FUNCTION); ++ if (queue->storage == NULL) ++ { ++ vchiu_queue_delete(queue); ++ return 0; ++ } ++ return 1; ++} ++ ++void vchiu_queue_delete(VCHIU_QUEUE_T *queue) ++{ ++ vcos_event_delete(&queue->pop); ++ vcos_event_delete(&queue->push); ++ if (queue->storage != NULL) ++ vcos_free(queue->storage); ++} ++ ++int vchiu_queue_is_empty(VCHIU_QUEUE_T *queue) ++{ ++ return queue->read == queue->write; ++} ++ ++void vchiu_queue_push(VCHIU_QUEUE_T *queue, VCHIQ_HEADER_T *header) ++{ ++ while (queue->write == queue->read + queue->size) ++ vcos_event_wait(&queue->pop); ++ ++ queue->storage[queue->write & (queue->size - 1)] = header; ++ ++ queue->write++; ++ ++ vcos_event_signal(&queue->push); ++} ++ ++VCHIQ_HEADER_T *vchiu_queue_peek(VCHIU_QUEUE_T *queue) ++{ ++ while (queue->write == queue->read) ++ vcos_event_wait(&queue->push); ++ ++ return queue->storage[queue->read & (queue->size - 1)]; ++} ++ ++VCHIQ_HEADER_T *vchiu_queue_pop(VCHIU_QUEUE_T *queue) ++{ ++ VCHIQ_HEADER_T *header; ++ ++ while (queue->write == queue->read) ++ vcos_event_wait(&queue->push); ++ ++ header = queue->storage[queue->read & (queue->size - 1)]; ++ ++ queue->read++; ++ ++ vcos_event_signal(&queue->pop); ++ ++ return header; ++} +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_util.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_util.h 2013-07-26 19:32:00.000000000 +0000 +@@ -0,0 +1,47 @@ ++/* ++ * Copyright (c) 2010-2011 Broadcom Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++#ifndef VCHIQ_UTIL_H ++#define VCHIQ_UTIL_H ++ ++#include "vchiq_if.h" ++#include "interface/vcos/vcos.h" ++ ++typedef struct { ++ int size; ++ int read; ++ int write; ++ ++ VCOS_EVENT_T pop; ++ VCOS_EVENT_T push; ++ ++ VCHIQ_HEADER_T **storage; ++} VCHIU_QUEUE_T; ++ ++extern int vchiu_queue_init(VCHIU_QUEUE_T *queue, int size); ++extern void vchiu_queue_delete(VCHIU_QUEUE_T *queue); ++ ++extern int vchiu_queue_is_empty(VCHIU_QUEUE_T *queue); ++ ++extern void vchiu_queue_push(VCHIU_QUEUE_T *queue, VCHIQ_HEADER_T *header); ++ ++extern VCHIQ_HEADER_T *vchiu_queue_peek(VCHIU_QUEUE_T *queue); ++extern VCHIQ_HEADER_T *vchiu_queue_pop(VCHIU_QUEUE_T *queue); ++ ++#endif ++ +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/generic/vcos_cmd.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/generic/vcos_cmd.c 2013-07-26 19:32:00.000000000 +0000 +@@ -0,0 +1,681 @@ ++/***************************************************************************** ++* Copyright 2009 - 2011 Broadcom Corporation. All rights reserved. ++* ++* Unless you and Broadcom execute a separate written software license ++* agreement governing use of this software, this software is licensed to you ++* under the terms of the GNU General Public License version 2, available at ++* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). ++* ++* Notwithstanding the above, under no circumstances may you combine this ++* software in any way with any other Broadcom software provided under a ++* license other than the GPL, without Broadcom's express prior written ++* consent. ++*****************************************************************************/ ++ ++/***************************************************************************** ++* ++* This file provides a generic command line interface which allows ++* vcos internals to be manipulated and/or displayed. ++* ++*****************************************************************************/ ++ ++/* ---- Include Files ---------------------------------------------------- */ ++ ++#include "interface/vcos/vcos.h" ++ ++#ifdef HAVE_VCOS_VERSION ++#include "interface/vcos/vcos_build_info.h" ++#endif ++ ++ #ifdef _VIDEOCORE ++#include vcfw/logging/logging.h ++#endif ++ ++/* ---- Public Variables ------------------------------------------------- */ ++ ++/* ---- Private Constants and Types -------------------------------------- */ ++ ++#define VCOS_LOG_CATEGORY (&vcos_cmd_log_category) ++VCOS_LOG_CAT_T vcos_cmd_log_category; ++ ++/* ---- Private Variables ------------------------------------------------ */ ++ ++static struct VCOS_CMD_GLOBALS_T ++{ ++ VCOS_MUTEX_T lock; ++ VCOS_ONCE_T initialized; ++ ++ unsigned num_cmd_entries; ++ unsigned num_cmd_alloc; ++ VCOS_CMD_T *cmd_entry; ++ ++ VCOS_LOG_CAT_T *log_category; ++} cmd_globals; ++ ++/* ---- Private Function Prototypes -------------------------------------- */ ++ ++static VCOS_STATUS_T help_cmd( VCOS_CMD_PARAM_T *param ); ++ ++/* ---- Functions ------------------------------------------------------- */ ++ ++/***************************************************************************** ++* ++* Walks through the commands looking for a particular command ++* ++*****************************************************************************/ ++ ++static VCOS_CMD_T *find_cmd( VCOS_CMD_T *cmd_entry, const char *name ) ++{ ++ VCOS_CMD_T *scan_entry = cmd_entry; ++ ++ while ( scan_entry->name != NULL ) ++ { ++ if ( vcos_strcmp( scan_entry->name, name ) == 0 ) ++ { ++ return scan_entry; ++ } ++ scan_entry++; ++ } ++ ++ return NULL; ++} ++ ++/***************************************************************************** ++* ++* Saves away ++* each line individually. ++* ++*****************************************************************************/ ++ ++void vcos_cmd_always_log_output( VCOS_LOG_CAT_T *log_category ) ++{ ++ cmd_globals.log_category = log_category; ++} ++ ++/***************************************************************************** ++* ++* Walks through a buffer containing newline separated lines, and logs ++* each line individually. ++* ++*****************************************************************************/ ++ ++static void cmd_log_results( VCOS_CMD_PARAM_T *param ) ++{ ++ char *start; ++ char *end; ++ ++ start = end = param->result_buf; ++ ++ while ( *start != '\0' ) ++ { ++ while (( *end != '\0' ) && ( *end != '\n' )) ++ end++; ++ ++ if ( *end == '\n' ) ++ { ++ *end++ = '\0'; ++ } ++ ++ if ( cmd_globals.log_category != NULL ) ++ { ++ if ( vcos_is_log_enabled( cmd_globals.log_category, VCOS_LOG_INFO )) ++ { ++ vcos_log_impl( cmd_globals.log_category, VCOS_LOG_INFO, "%s", start ); ++ } ++ } ++ else ++ { ++ vcos_log_info( "%s", start ); ++ } ++ ++ start = end; ++ } ++ ++ /* Since we logged the buffer, reset the pointer back to the beginning. */ ++ ++ param->result_ptr = param->result_buf; ++ param->result_buf[0] = '\0'; ++} ++ ++/***************************************************************************** ++* ++* Since we may have limited output space, we create a generic routine ++* which tries to use the result space, but will switch over to using ++* logging if the output is too large. ++* ++*****************************************************************************/ ++ ++void vcos_cmd_vprintf( VCOS_CMD_PARAM_T *param, const char *fmt, va_list args ) ++{ ++ int bytes_written; ++ int bytes_remaining; ++ ++ bytes_remaining = (int)(param->result_size - ( param->result_ptr - param->result_buf )); ++ ++ bytes_written = vcos_vsnprintf( param->result_ptr, bytes_remaining, fmt, args ); ++ ++ if ( cmd_globals.log_category != NULL ) ++ { ++ /* We're going to log each line as we encounter it. If the buffer ++ * doesn't end in a newline, then we'll wait for one first. ++ */ ++ ++ if ( (( bytes_written + 1 ) >= bytes_remaining ) ++ || ( param->result_ptr[ bytes_written - 1 ] == '\n' )) ++ { ++ cmd_log_results( param ); ++ } ++ else ++ { ++ param->result_ptr += bytes_written; ++ } ++ } ++ else ++ { ++ if (( bytes_written + 1 ) >= bytes_remaining ) ++ { ++ /* Output doesn't fit - switch over to logging */ ++ ++ param->use_log = 1; ++ ++ *param->result_ptr = '\0'; /* Zap the partial line that didn't fit above. */ ++ ++ cmd_log_results( param ); /* resets result_ptr */ ++ ++ bytes_written = vcos_vsnprintf( param->result_ptr, bytes_remaining, fmt, args ); ++ } ++ param->result_ptr += bytes_written; ++ } ++} ++ ++/***************************************************************************** ++* ++* Prints the output. ++* ++*****************************************************************************/ ++ ++void vcos_cmd_printf( VCOS_CMD_PARAM_T *param, const char *fmt, ... ) ++{ ++ va_list args; ++ ++ va_start( args, fmt ); ++ vcos_cmd_vprintf( param, fmt, args ); ++ va_end( args ); ++} ++ ++/***************************************************************************** ++* ++* Prints the arguments which were on the command line prior to ours. ++* ++*****************************************************************************/ ++ ++static void print_argument_prefix( VCOS_CMD_PARAM_T *param ) ++{ ++ int arg_idx; ++ ++ for ( arg_idx = 0; ¶m->argv_orig[arg_idx] != param->argv; arg_idx++ ) ++ { ++ vcos_cmd_printf( param, "%s ", param->argv_orig[arg_idx] ); ++ } ++} ++ ++/***************************************************************************** ++* ++* Prints an error message, prefixed by the command chain required to get ++* to where we're at. ++* ++*****************************************************************************/ ++ ++void vcos_cmd_error( VCOS_CMD_PARAM_T *param, const char *fmt, ... ) ++{ ++ va_list args; ++ ++ print_argument_prefix( param ); ++ ++ va_start( args, fmt ); ++ vcos_cmd_vprintf( param, fmt, args ); ++ va_end( args ); ++ vcos_cmd_printf( param, "\n" ); ++} ++ ++/**************************************************************************** ++* ++* usage - prints command usage for an array of commands. ++* ++***************************************************************************/ ++ ++static void usage( VCOS_CMD_PARAM_T *param, VCOS_CMD_T *cmd_entry ) ++{ ++ int cmd_idx; ++ int nameWidth = 0; ++ int argsWidth = 0; ++ VCOS_CMD_T *scan_entry; ++ ++ vcos_cmd_printf( param, "Usage: " ); ++ print_argument_prefix( param ); ++ vcos_cmd_printf( param, "command [args ...]\n" ); ++ vcos_cmd_printf( param, "\n" ); ++ vcos_cmd_printf( param, "Where command is one of the following:\n" ); ++ ++ for ( cmd_idx = 0; cmd_entry[cmd_idx].name != NULL; cmd_idx++ ) ++ { ++ int aw; ++ int nw; ++ ++ scan_entry = &cmd_entry[cmd_idx]; ++ ++ nw = vcos_strlen( scan_entry->name ); ++ aw = vcos_strlen( scan_entry->args ); ++ ++ if ( nw > nameWidth ) ++ { ++ nameWidth = nw; ++ } ++ if ( aw > argsWidth ) ++ { ++ argsWidth = aw; ++ } ++ } ++ ++ for ( cmd_idx = 0; cmd_entry[cmd_idx].name != NULL; cmd_idx++ ) ++ { ++ scan_entry = &cmd_entry[cmd_idx]; ++ ++ vcos_cmd_printf( param, " %-*s %-*s - %s\n", ++ nameWidth, scan_entry->name, ++ argsWidth, scan_entry->args, ++ scan_entry->descr ); ++ } ++} ++ ++/**************************************************************************** ++* ++* Prints the usage for the current command. ++* ++***************************************************************************/ ++ ++void vcos_cmd_usage( VCOS_CMD_PARAM_T *param ) ++{ ++ VCOS_CMD_T *cmd_entry; ++ ++ cmd_entry = param->cmd_entry; ++ ++ if ( cmd_entry->sub_cmd_entry != NULL ) ++ { ++ /* This command is command with sub-commands */ ++ ++ usage( param, param->cmd_entry->sub_cmd_entry ); ++ } ++ else ++ { ++ vcos_cmd_printf( param, "Usage: " ); ++ print_argument_prefix( param ); ++ vcos_cmd_printf( param, "%s - %s\n", ++ param->cmd_entry->args, ++ param->cmd_entry->descr ); ++ } ++} ++ ++/***************************************************************************** ++* ++* Command to print out the help ++* ++* This help command is only called from the main menu. ++* ++*****************************************************************************/ ++ ++static VCOS_STATUS_T help_cmd( VCOS_CMD_PARAM_T *param ) ++{ ++ VCOS_CMD_T *found_entry; ++ ++#if 0 ++ { ++ int arg_idx; ++ ++ vcos_log_trace( "%s: argc = %d", __func__, param->argc ); ++ for ( arg_idx = 0; arg_idx < param->argc; arg_idx++ ) ++ { ++ vcos_log_trace( "%s: argv[%d] = '%s'", __func__, arg_idx, param->argv[arg_idx] ); ++ } ++ } ++#endif ++ ++ /* If there is an argument after the word help, then we want to print ++ * help for that command. ++ */ ++ ++ if ( param->argc == 1 ) ++ { ++ if ( param->cmd_parent_entry == cmd_globals.cmd_entry ) ++ { ++ /* Bare help - print the command usage for the root */ ++ ++ usage( param, cmd_globals.cmd_entry ); ++ return VCOS_SUCCESS; ++ } ++ ++ /* For all other cases help requires an argument */ ++ ++ vcos_cmd_error( param, "%s requires an argument", param->argv[0] ); ++ return VCOS_EINVAL; ++ } ++ ++ /* We were given an argument. */ ++ ++ if (( found_entry = find_cmd( param->cmd_parent_entry, param->argv[1] )) != NULL ) ++ { ++ /* Make it look like the command that was specified is the one that's ++ * currently running ++ */ ++ ++ param->cmd_entry = found_entry; ++ param->argv[0] = param->argv[1]; ++ param->argv++; ++ param->argc--; ++ ++ vcos_cmd_usage( param ); ++ return VCOS_SUCCESS; ++ } ++ ++ vcos_cmd_error( param, "- unrecognized command: '%s'", param->argv[1] ); ++ return VCOS_ENOENT; ++} ++ ++/***************************************************************************** ++* ++* Command to print out the version/build information. ++* ++*****************************************************************************/ ++ ++#ifdef HAVE_VCOS_VERSION ++ ++static VCOS_STATUS_T version_cmd( VCOS_CMD_PARAM_T *param ) ++{ ++ static const char* copyright = "Copyright (c) 2011 Broadcom"; ++ ++ vcos_cmd_printf( param, "%s %s\n%s\nversion %s\n", ++ vcos_get_build_date(), ++ vcos_get_build_time(), ++ copyright, ++ vcos_get_build_version() ); ++ ++ return VCOS_SUCCESS; ++} ++ ++#endif ++ ++/***************************************************************************** ++* ++* Internal commands ++* ++*****************************************************************************/ ++ ++static VCOS_CMD_T cmd_help = { "help", "[command]", help_cmd, NULL, "Prints command help information" }; ++ ++#ifdef HAVE_VCOS_VERSION ++static VCOS_CMD_T cmd_version = { "version", "", version_cmd, NULL, "Prints build/version information" }; ++#endif ++ ++/***************************************************************************** ++* ++* Walks the command table and executes the commands ++* ++*****************************************************************************/ ++ ++static VCOS_STATUS_T execute_cmd( VCOS_CMD_PARAM_T *param, VCOS_CMD_T *cmd_entry ) ++{ ++ const char *cmdStr; ++ VCOS_CMD_T *found_entry; ++ ++#if 0 ++ { ++ int arg_idx; ++ ++ vcos_cmd_printf( param, "%s: argc = %d", __func__, param->argc ); ++ for ( arg_idx = 0; arg_idx < param->argc; arg_idx++ ) ++ { ++ vcos_cmd_printf( param, " argv[%d] = '%s'", arg_idx, param->argv[arg_idx] ); ++ } ++ vcos_cmd_printf( param, "\n" ); ++ } ++#endif ++ ++ if ( param->argc <= 1 ) ++ { ++ /* No command specified */ ++ ++ vcos_cmd_error( param, "%s - no command specified", param->argv[0] ); ++ return VCOS_EINVAL; ++ } ++ ++ /* argv[0] is the command/program that caused us to get invoked, so we strip ++ * it off. ++ */ ++ ++ param->argc--; ++ param->argv++; ++ param->cmd_parent_entry = cmd_entry; ++ ++ /* Not the help command, scan for the command and execute it. */ ++ ++ cmdStr = param->argv[0]; ++ ++ if (( found_entry = find_cmd( cmd_entry, cmdStr )) != NULL ) ++ { ++ if ( found_entry->sub_cmd_entry != NULL ) ++ { ++ return execute_cmd( param, found_entry->sub_cmd_entry ); ++ } ++ ++ param->cmd_entry = found_entry; ++ return found_entry->cmd_fn( param ); ++ } ++ ++ /* Unrecognized command - check to see if it was the help command */ ++ ++ if ( vcos_strcmp( cmdStr, cmd_help.name ) == 0 ) ++ { ++ return help_cmd( param ); ++ } ++ ++ vcos_cmd_error( param, "- unrecognized command: '%s'", cmdStr ); ++ return VCOS_ENOENT; ++} ++ ++/***************************************************************************** ++* ++* Initializes the command line parser. ++* ++*****************************************************************************/ ++ ++static void vcos_cmd_init( void ) ++{ ++ vcos_mutex_create( &cmd_globals.lock, "vcos_cmd" ); ++ ++ cmd_globals.num_cmd_entries = 0; ++ cmd_globals.num_cmd_alloc = 0; ++ cmd_globals.cmd_entry = NULL; ++} ++ ++/***************************************************************************** ++* ++* Command line processor. ++* ++*****************************************************************************/ ++ ++VCOS_STATUS_T vcos_cmd_execute( int argc, char **argv, size_t result_size, char *result_buf ) ++{ ++ VCOS_STATUS_T rc = VCOS_EINVAL; ++ VCOS_CMD_PARAM_T param; ++ ++ vcos_once( &cmd_globals.initialized, vcos_cmd_init ); ++ ++ param.argc = argc; ++ param.argv = param.argv_orig = argv; ++ ++ param.use_log = 0; ++ param.result_size = result_size; ++ param.result_ptr = result_buf; ++ param.result_buf = result_buf; ++ ++ result_buf[0] = '\0'; ++ ++ vcos_mutex_lock( &cmd_globals.lock ); ++ ++ rc = execute_cmd( ¶m, cmd_globals.cmd_entry ); ++ ++ if ( param.use_log ) ++ { ++ cmd_log_results( ¶m ); ++ vcos_snprintf( result_buf, result_size, "results logged" ); ++ } ++ else ++ if ( cmd_globals.log_category != NULL ) ++ { ++ if ( result_buf[0] != '\0' ) ++ { ++ /* There is a partial line still buffered. */ ++ ++ vcos_cmd_printf( ¶m, "\n" ); ++ } ++ } ++ ++ vcos_mutex_unlock( &cmd_globals.lock ); ++ ++ return rc; ++} ++ ++/***************************************************************************** ++* ++* Registers a command entry with the command line processor ++* ++*****************************************************************************/ ++ ++VCOS_STATUS_T vcos_cmd_register( VCOS_CMD_T *cmd_entry ) ++{ ++ VCOS_STATUS_T rc; ++ VCOS_UNSIGNED new_num_cmd_alloc; ++ VCOS_CMD_T *new_cmd_entry; ++ VCOS_CMD_T *old_cmd_entry; ++ VCOS_CMD_T *scan_entry; ++ ++ vcos_once( &cmd_globals.initialized, vcos_cmd_init ); ++ ++ vcos_assert( cmd_entry != NULL ); ++ vcos_assert( cmd_entry->name != NULL ); ++ ++ vcos_log_trace( "%s: cmd '%s'", __FUNCTION__, cmd_entry->name ); ++ ++ vcos_assert( cmd_entry->args != NULL ); ++ vcos_assert(( cmd_entry->cmd_fn != NULL ) || ( cmd_entry->sub_cmd_entry != NULL )); ++ vcos_assert( cmd_entry->descr != NULL ); ++ ++ /* We expect vcos_cmd_init to be called before vcos_logging_init, so we ++ * need to defer registering our logging category until someplace ++ * like right here. ++ */ ++ ++ if ( vcos_cmd_log_category.name == NULL ) ++ { ++ /* ++ * If you're using the command interface, you pretty much always want ++ * log messages from this file to show up. So we change the default ++ * from ERROR to be the more reasonable INFO level. ++ */ ++ ++ vcos_log_set_level(&vcos_cmd_log_category, VCOS_LOG_INFO); ++ vcos_log_register("vcos_cmd", &vcos_cmd_log_category); ++ ++ /* We register a help command so that it shows up in the usage. */ ++ ++ vcos_cmd_register( &cmd_help ); ++#ifdef HAVE_VCOS_VERSION ++ vcos_cmd_register( &cmd_version ); ++#endif ++ } ++ ++ vcos_mutex_lock( &cmd_globals.lock ); ++ ++ if ( cmd_globals.num_cmd_entries >= cmd_globals.num_cmd_alloc ) ++ { ++ if ( cmd_globals.num_cmd_alloc == 0 ) ++ { ++ /* We haven't allocated a table yet */ ++ } ++ ++ /* The number 8 is rather arbitrary. */ ++ ++ new_num_cmd_alloc = cmd_globals.num_cmd_alloc + 8; ++ ++ /* The + 1 is to ensure that we always have a NULL entry at the end. */ ++ ++ new_cmd_entry = (VCOS_CMD_T *)vcos_calloc( new_num_cmd_alloc + 1, sizeof( *cmd_entry ), "vcos_cmd_entries" ); ++ if ( new_cmd_entry == NULL ) ++ { ++ rc = VCOS_ENOMEM; ++ goto out; ++ } ++ memcpy( new_cmd_entry, cmd_globals.cmd_entry, cmd_globals.num_cmd_entries * sizeof( *cmd_entry )); ++ cmd_globals.num_cmd_alloc = new_num_cmd_alloc; ++ old_cmd_entry = cmd_globals.cmd_entry; ++ cmd_globals.cmd_entry = new_cmd_entry; ++ vcos_free( old_cmd_entry ); ++ } ++ ++ if ( cmd_globals.num_cmd_entries == 0 ) ++ { ++ /* This is the first command being registered */ ++ ++ cmd_globals.cmd_entry[0] = *cmd_entry; ++ } ++ else ++ { ++ /* Keep the list in alphabetical order. We start at the end and work backwards ++ * shuffling entries up one until we find an insertion point. ++ */ ++ ++ for ( scan_entry = &cmd_globals.cmd_entry[cmd_globals.num_cmd_entries - 1]; ++ scan_entry >= cmd_globals.cmd_entry; scan_entry-- ) ++ { ++ if ( vcos_strcmp( cmd_entry->name, scan_entry->name ) > 0 ) ++ { ++ /* We found an insertion point. */ ++ ++ break; ++ } ++ ++ scan_entry[1] = scan_entry[0]; ++ } ++ scan_entry[1] = *cmd_entry; ++ } ++ cmd_globals.num_cmd_entries++; ++ ++ rc = VCOS_SUCCESS; ++ ++out: ++ ++ vcos_mutex_unlock( &cmd_globals.lock ); ++ return rc; ++} ++ ++/***************************************************************************** ++* ++* Registers multiple commands. ++* ++*****************************************************************************/ ++ ++VCOS_STATUS_T vcos_cmd_register_multiple( VCOS_CMD_T *cmd_entry ) ++{ ++ VCOS_STATUS_T status; ++ ++ while ( cmd_entry->name != NULL ) ++ { ++ if (( status = vcos_cmd_register( cmd_entry )) != VCOS_SUCCESS ) ++ { ++ return status; ++ } ++ cmd_entry++; ++ } ++ return VCOS_SUCCESS; ++} ++ +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/generic/vcos_common.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/generic/vcos_common.h 2013-07-26 19:32:00.000000000 +0000 +@@ -0,0 +1,76 @@ ++/*============================================================================= ++Copyright (c) 2009 Broadcom Europe Limited. ++All rights reserved. ++ ++Project : vcfw ++Module : chip driver ++ ++FILE DESCRIPTION ++VideoCore OS Abstraction Layer - common postamble code ++=============================================================================*/ ++ ++/** \file ++ * ++ * Postamble code included by the platform-specific header files ++ */ ++ ++#define VCOS_THREAD_PRI_DEFAULT VCOS_THREAD_PRI_NORMAL ++ ++#if !defined(VCOS_THREAD_PRI_INCREASE) ++#error Which way to thread priorities go? ++#endif ++ ++#if VCOS_THREAD_PRI_INCREASE < 0 ++/* smaller numbers are higher priority */ ++#define VCOS_THREAD_PRI_LESS(x) ((x)VCOS_THREAD_PRI_MIN?(x)-1:VCOS_THREAD_PRI_MIN) ++#else ++/* bigger numbers are lower priority */ ++#define VCOS_THREAD_PRI_MORE(x) ((x)VCOS_THREAD_PRI_MIN?(x)-1:VCOS_THREAD_PRI_MIN) ++#endif ++ ++/* Convenience for Brits: */ ++#define VCOS_APPLICATION_INITIALISE VCOS_APPLICATION_INITIALIZE ++ ++/* ++ * Check for constant definitions ++ */ ++#ifndef VCOS_TICKS_PER_SECOND ++#error VCOS_TICKS_PER_SECOND not defined ++#endif ++ ++#if !defined(VCOS_THREAD_PRI_MIN) || !defined(VCOS_THREAD_PRI_MAX) ++#error Priority range not defined ++#endif ++ ++#if !defined(VCOS_THREAD_PRI_HIGHEST) || !defined(VCOS_THREAD_PRI_LOWEST) || !defined(VCOS_THREAD_PRI_NORMAL) ++#error Priority ordering not defined ++#endif ++ ++#if !defined(VCOS_CAN_SET_STACK_ADDR) ++#error Can stack addresses be set on this platform? Please set this macro to either 0 or 1. ++#endif ++ ++#if (_VCOS_AFFINITY_CPU0|_VCOS_AFFINITY_CPU1) & (~_VCOS_AFFINITY_MASK) ++#error _VCOS_AFFINITY_CPUxxx values are not consistent with _VCOS_AFFINITY_MASK ++#endif ++ ++/** Append to the end of a singly-linked queue, O(1). Works with ++ * any structure where list has members 'head' and 'tail' and ++ * item has a 'next' pointer. ++ */ ++#define VCOS_QUEUE_APPEND_TAIL(list, item) {\ ++ (item)->next = NULL;\ ++ if (!(list)->head) {\ ++ (list)->head = (list)->tail = (item); \ ++ } else {\ ++ (list)->tail->next = (item); \ ++ (list)->tail = (item); \ ++ } \ ++} ++ ++#ifndef VCOS_HAVE_TIMER ++VCOSPRE_ void VCOSPOST_ vcos_timer_init(void); ++#endif ++ +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/generic/vcos_generic_blockpool.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/generic/vcos_generic_blockpool.h 2013-07-26 19:32:00.000000000 +0000 +@@ -0,0 +1,260 @@ ++/*============================================================================= ++Copyright (c) 2011 Broadcom Europe Limited. ++All rights reserved. ++ ++Project : vcfw ++Module : chip driver ++ ++FILE DESCRIPTION ++VideoCore OS Abstraction Layer - event flags implemented via a semaphore ++=============================================================================*/ ++ ++#ifndef VCOS_GENERIC_BLOCKPOOL_H ++#define VCOS_GENERIC_BLOCKPOOL_H ++ ++/** ++ * \file ++ * ++ * This provides a generic, thread safe implementation of a VCOS block pool ++ * fixed size memory allocator. ++ */ ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++#include "interface/vcos/vcos_types.h" ++ ++/** Bits 0 to (VCOS_BLOCKPOOL_SUBPOOL_BITS - 1) are used to store the ++ * subpool id. */ ++#define VCOS_BLOCKPOOL_SUBPOOL_BITS 3 ++#define VCOS_BLOCKPOOL_MAX_SUBPOOLS (1 << VCOS_BLOCKPOOL_SUBPOOL_BITS) ++ ++/* Make zero an invalid handle at the cost of decreasing the maximum ++ * number of blocks (2^28) by 1. Alternatively, a spare bit could be ++ * used to indicated valid blocks but there are likely to be better ++ * uses for spare bits. e.g. allowing more subpools ++ */ ++#define INDEX_OFFSET 1 ++ ++#define VCOS_BLOCKPOOL_HANDLE_GET_INDEX(h) \ ++ (((h) >> VCOS_BLOCKPOOL_SUBPOOL_BITS) - INDEX_OFFSET) ++ ++#define VCOS_BLOCKPOOL_HANDLE_GET_SUBPOOL(h) \ ++ ((h) & ((1 << VCOS_BLOCKPOOL_SUBPOOL_BITS) - 1)) ++ ++#define VCOS_BLOCKPOOL_HANDLE_CREATE(i,s) \ ++ ((((i) + INDEX_OFFSET) << VCOS_BLOCKPOOL_SUBPOOL_BITS) | (s)) ++ ++#define VCOS_BLOCKPOOL_INVALID_HANDLE 0 ++ ++typedef struct VCOS_BLOCKPOOL_HEADER_TAG ++{ ++ /* Blocks either refer to to the pool if they are allocated ++ * or the free list if they are available. ++ */ ++ union { ++ struct VCOS_BLOCKPOOL_HEADER_TAG *next; ++ struct VCOS_BLOCKPOOL_SUBPOOL_TAG* subpool; ++ } owner; ++} VCOS_BLOCKPOOL_HEADER_T; ++ ++typedef struct VCOS_BLOCKPOOL_SUBPOOL_TAG ++{ ++ /** VCOS_BLOCKPOOL_SUBPOOL_MAGIC */ ++ uint32_t magic; ++ VCOS_BLOCKPOOL_HEADER_T* free_list; ++ /* The start of the pool memory */ ++ void *mem; ++ /* Address of the first block header */ ++ void *start; ++ /** The number of blocks in this sub-pool */ ++ VCOS_UNSIGNED num_blocks; ++ /** Current number of available blocks in this sub-pool */ ++ VCOS_UNSIGNED available_blocks; ++ /** Pointers to the pool that owns this sub-pool */ ++ struct VCOS_BLOCKPOOL_TAG* owner; ++ /** Define properties such as memory ownership */ ++ uint32_t flags; ++} VCOS_BLOCKPOOL_SUBPOOL_T; ++ ++typedef struct VCOS_BLOCKPOOL_TAG ++{ ++ /** VCOS_BLOCKPOOL_MAGIC */ ++ uint32_t magic; ++ /** Thread safety for Alloc, Free, Delete, Stats */ ++ VCOS_MUTEX_T mutex; ++ /** The size of the block data */ ++ size_t block_data_size; ++ /** Block size inc overheads */ ++ size_t block_size; ++ /** Name for debugging */ ++ const char *name; ++ /* The number of subpools that may be used */ ++ VCOS_UNSIGNED num_subpools; ++ /** Number of blocks in each dynamically allocated subpool */ ++ VCOS_UNSIGNED num_extension_blocks; ++ /** Array of subpools. Subpool zero is is not deleted until the pool is ++ * destroed. If the index of the pool is < num_subpools and ++ * subpool[index.mem] is null then the subpool entry is valid but ++ * "not currently allocated" */ ++ VCOS_BLOCKPOOL_SUBPOOL_T subpools[VCOS_BLOCKPOOL_MAX_SUBPOOLS]; ++} VCOS_BLOCKPOOL_T; ++ ++#define VCOS_BLOCKPOOL_ROUND_UP(x,s) (((x) + ((s) - 1)) & ~((s) - 1)) ++/** ++ * Calculates the size in bytes required for a block pool containing ++ * num_blocks of size block_size plus any overheads. ++ * ++ * The block pool header (VCOS_BLOCKPOOL_T) is allocated separately ++ * ++ * Overheads: ++ * block_size + header must be a multiple of sizeof(void*) ++ * The start of the first block may need to be up to wordsize - 1 bytes ++ * into the given buffer because statically allocated buffers within structures ++ * are not guaranteed to be word aligned. ++ */ ++#define VCOS_BLOCKPOOL_SIZE(num_blocks, block_size) \ ++ ((VCOS_BLOCKPOOL_ROUND_UP((block_size) + sizeof(VCOS_BLOCKPOOL_HEADER_T), \ ++ sizeof(void*)) * (num_blocks)) + sizeof(void*)) ++ ++/** ++ * Sanity check to verify whether a handle is potentially a blockpool handle ++ * when the pool pointer is not available. ++ * ++ * If the pool pointer is availabe use vcos_blockpool_elem_to_handle instead. ++ * ++ * @param handle the handle to verify ++ * @param max_blocks the expected maximum number of block in the pool ++ * that the handle belongs to. ++ */ ++#define VCOS_BLOCKPOOL_IS_VALID_HANDLE_FORMAT(handle, max_blocks) \ ++ ((handle) != VCOS_BLOCKPOOL_INVALID_HANDLE \ ++ && VCOS_BLOCKPOOL_HANDLE_GET_INDEX((handle)) < (max_blocks)) ++ ++VCOSPRE_ ++ VCOS_STATUS_T VCOSPOST_ vcos_generic_blockpool_init(VCOS_BLOCKPOOL_T *pool, ++ VCOS_UNSIGNED num_blocks, VCOS_UNSIGNED block_size, ++ void *start, VCOS_UNSIGNED pool_size, const char *name); ++ ++VCOSPRE_ ++ VCOS_STATUS_T VCOSPOST_ vcos_generic_blockpool_create_on_heap( ++ VCOS_BLOCKPOOL_T *pool, VCOS_UNSIGNED num_blocks, ++ VCOS_UNSIGNED block_size, const char *name); ++ ++VCOSPRE_ ++ VCOS_STATUS_T VCOSPOST_ vcos_generic_blockpool_extend(VCOS_BLOCKPOOL_T *pool, ++ VCOS_UNSIGNED num_extensions, VCOS_UNSIGNED num_blocks); ++ ++VCOSPRE_ void VCOSPOST_ *vcos_generic_blockpool_alloc(VCOS_BLOCKPOOL_T *pool); ++ ++VCOSPRE_ void VCOSPOST_ *vcos_generic_blockpool_calloc(VCOS_BLOCKPOOL_T *pool); ++ ++VCOSPRE_ void VCOSPOST_ vcos_generic_blockpool_free(void *block); ++ ++VCOSPRE_ ++ VCOS_UNSIGNED VCOSPOST_ vcos_generic_blockpool_available_count( ++ VCOS_BLOCKPOOL_T *pool); ++ ++VCOSPRE_ ++ VCOS_UNSIGNED VCOSPOST_ vcos_generic_blockpool_used_count( ++ VCOS_BLOCKPOOL_T *pool); ++ ++VCOSPRE_ void VCOSPOST_ vcos_generic_blockpool_delete(VCOS_BLOCKPOOL_T *pool); ++ ++VCOSPRE_ uint32_t VCOSPOST_ vcos_generic_blockpool_elem_to_handle(void *block); ++ ++VCOSPRE_ void VCOSPOST_ ++ *vcos_generic_blockpool_elem_from_handle( ++ VCOS_BLOCKPOOL_T *pool, uint32_t handle); ++ ++VCOSPRE_ uint32_t VCOSPOST_ ++ vcos_generic_blockpool_is_valid_elem( ++ VCOS_BLOCKPOOL_T *pool, const void *block); ++#if defined(VCOS_INLINE_BODIES) ++ ++VCOS_INLINE_IMPL ++VCOS_STATUS_T vcos_blockpool_init(VCOS_BLOCKPOOL_T *pool, ++ VCOS_UNSIGNED num_blocks, VCOS_UNSIGNED block_size, ++ void *start, VCOS_UNSIGNED pool_size, const char *name) ++{ ++ return vcos_generic_blockpool_init(pool, num_blocks, block_size, ++ start, pool_size, name); ++} ++ ++VCOS_INLINE_IMPL ++VCOS_STATUS_T vcos_blockpool_create_on_heap(VCOS_BLOCKPOOL_T *pool, ++ VCOS_UNSIGNED num_blocks, VCOS_UNSIGNED block_size, const char *name) ++{ ++ return vcos_generic_blockpool_create_on_heap( ++ pool, num_blocks, block_size, name); ++} ++ ++VCOS_INLINE_IMPL ++ VCOS_STATUS_T VCOSPOST_ vcos_blockpool_extend(VCOS_BLOCKPOOL_T *pool, ++ VCOS_UNSIGNED num_extensions, VCOS_UNSIGNED num_blocks) ++{ ++ return vcos_generic_blockpool_extend(pool, num_extensions, num_blocks); ++} ++ ++VCOS_INLINE_IMPL ++void *vcos_blockpool_alloc(VCOS_BLOCKPOOL_T *pool) ++{ ++ return vcos_generic_blockpool_alloc(pool); ++} ++ ++VCOS_INLINE_IMPL ++void *vcos_blockpool_calloc(VCOS_BLOCKPOOL_T *pool) ++{ ++ return vcos_generic_blockpool_calloc(pool); ++} ++ ++VCOS_INLINE_IMPL ++void vcos_blockpool_free(void *block) ++{ ++ vcos_generic_blockpool_free(block); ++} ++ ++VCOS_INLINE_IMPL ++VCOS_UNSIGNED vcos_blockpool_available_count(VCOS_BLOCKPOOL_T *pool) ++{ ++ return vcos_generic_blockpool_available_count(pool); ++} ++ ++VCOS_INLINE_IMPL ++VCOS_UNSIGNED vcos_blockpool_used_count(VCOS_BLOCKPOOL_T *pool) ++{ ++ return vcos_generic_blockpool_used_count(pool); ++} ++ ++VCOS_INLINE_IMPL ++void vcos_blockpool_delete(VCOS_BLOCKPOOL_T *pool) ++{ ++ vcos_generic_blockpool_delete(pool); ++} ++ ++VCOS_INLINE_IMPL ++uint32_t vcos_blockpool_elem_to_handle(void *block) ++{ ++ return vcos_generic_blockpool_elem_to_handle(block); ++} ++ ++VCOS_INLINE_IMPL ++void *vcos_blockpool_elem_from_handle(VCOS_BLOCKPOOL_T *pool, uint32_t handle) ++{ ++ return vcos_generic_blockpool_elem_from_handle(pool, handle); ++} ++ ++VCOS_INLINE_IMPL ++uint32_t vcos_blockpool_is_valid_elem(VCOS_BLOCKPOOL_T *pool, const void *block) ++{ ++ return vcos_generic_blockpool_is_valid_elem(pool, block); ++} ++#endif /* VCOS_INLINE_BODIES */ ++ ++ ++#ifdef __cplusplus ++} ++#endif ++#endif /* VCOS_GENERIC_BLOCKPOOL_H */ ++ +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/generic/vcos_generic_event_flags.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/generic/vcos_generic_event_flags.c 2013-07-26 19:32:00.000000000 +0000 +@@ -0,0 +1,297 @@ ++/*============================================================================= ++Copyright (c) 2009 Broadcom Europe Limited. ++All rights reserved. ++ ++FILE DESCRIPTION ++VideoCore OS Abstraction Layer - event flags implemented via mutexes ++=============================================================================*/ ++ ++#include "interface/vcos/vcos.h" ++#include "interface/vcos/generic/vcos_generic_event_flags.h" ++ ++#include ++ ++/** A structure created by a thread that waits on the event flags ++ * for a particular combination of flags to arrive. ++ */ ++typedef struct VCOS_EVENT_WAITER_T ++{ ++ VCOS_UNSIGNED requested_events; /**< The events wanted */ ++ VCOS_UNSIGNED actual_events; /**< Actual events found */ ++ VCOS_UNSIGNED op; /**< The event operation to be used */ ++ VCOS_STATUS_T return_status; /**< The return status the waiter should pass back */ ++ VCOS_EVENT_FLAGS_T *flags; /**< Pointer to the original 'flags' structure */ ++ VCOS_THREAD_T *thread; /**< Thread waiting */ ++ struct VCOS_EVENT_WAITER_T *next; ++} VCOS_EVENT_WAITER_T; ++ ++#ifndef NDEBUG ++static int waiter_list_valid(VCOS_EVENT_FLAGS_T *flags); ++#endif ++static void event_flags_timer_expired(void *cxt); ++ ++VCOS_STATUS_T vcos_generic_event_flags_create(VCOS_EVENT_FLAGS_T *flags, const char *name) ++{ ++ VCOS_STATUS_T rc; ++ if ((rc=vcos_mutex_create(&flags->lock, name)) != VCOS_SUCCESS) ++ { ++ return rc; ++ } ++ ++ flags->events = 0; ++ flags->waiters.head = flags->waiters.tail = 0; ++ return rc; ++} ++ ++void vcos_generic_event_flags_set(VCOS_EVENT_FLAGS_T *flags, ++ VCOS_UNSIGNED bitmask, ++ VCOS_OPTION op) ++{ ++ vcos_assert(flags); ++ vcos_mutex_lock(&flags->lock); ++ if (op == VCOS_OR) ++ { ++ flags->events |= bitmask; ++ } ++ else if (op == VCOS_AND) ++ { ++ flags->events &= bitmask; ++ } ++ else ++ { ++ vcos_assert(0); ++ } ++ ++ /* Now wake up any threads that have now become signalled. */ ++ if (flags->waiters.head != NULL) ++ { ++ VCOS_UNSIGNED consumed_events = 0; ++ VCOS_EVENT_WAITER_T **pcurrent_waiter = &flags->waiters.head; ++ VCOS_EVENT_WAITER_T *prev_waiter = NULL; ++ ++ /* Walk the chain of tasks suspend on this event flag group to determine ++ * if any of their requests can be satisfied. ++ */ ++ while ((*pcurrent_waiter) != NULL) ++ { ++ VCOS_EVENT_WAITER_T *curr_waiter = *pcurrent_waiter; ++ ++ /* Determine if this request has been satisfied */ ++ ++ /* First, find the event flags in common. */ ++ VCOS_UNSIGNED waiter_satisfied = flags->events & curr_waiter->requested_events; ++ ++ /* Second, determine if all the event flags must match */ ++ if (curr_waiter->op & VCOS_AND) ++ { ++ /* All requested events must be present */ ++ waiter_satisfied = (waiter_satisfied == curr_waiter->requested_events); ++ } ++ ++ /* Wake this one up? */ ++ if (waiter_satisfied) ++ { ++ ++ if (curr_waiter->op & VCOS_CONSUME) ++ { ++ consumed_events |= curr_waiter->requested_events; ++ } ++ ++ /* remove this block from the list, taking care at the end */ ++ *pcurrent_waiter = curr_waiter->next; ++ if (curr_waiter->next == NULL) ++ flags->waiters.tail = prev_waiter; ++ ++ vcos_assert(waiter_list_valid(flags)); ++ ++ curr_waiter->return_status = VCOS_SUCCESS; ++ curr_waiter->actual_events = flags->events; ++ ++ _vcos_thread_sem_post(curr_waiter->thread); ++ } ++ else ++ { ++ /* move to next element in the list */ ++ prev_waiter = *pcurrent_waiter; ++ pcurrent_waiter = &(curr_waiter->next); ++ } ++ } ++ ++ flags->events &= ~consumed_events; ++ ++ } ++ ++ vcos_mutex_unlock(&flags->lock); ++} ++ ++void vcos_generic_event_flags_delete(VCOS_EVENT_FLAGS_T *flags) ++{ ++ vcos_mutex_delete(&flags->lock); ++} ++ ++extern VCOS_STATUS_T vcos_generic_event_flags_get(VCOS_EVENT_FLAGS_T *flags, ++ VCOS_UNSIGNED bitmask, ++ VCOS_OPTION op, ++ VCOS_UNSIGNED suspend, ++ VCOS_UNSIGNED *retrieved_bits) ++{ ++ VCOS_EVENT_WAITER_T waitreq; ++ VCOS_STATUS_T rc = VCOS_EAGAIN; ++ int satisfied = 0; ++ ++ vcos_assert(flags); ++ ++ /* default retrieved bits to 0 */ ++ *retrieved_bits = 0; ++ ++ vcos_mutex_lock(&flags->lock); ++ switch (op & VCOS_EVENT_FLAG_OP_MASK) ++ { ++ case VCOS_AND: ++ if ((flags->events & bitmask) == bitmask) ++ { ++ *retrieved_bits = flags->events; ++ rc = VCOS_SUCCESS; ++ satisfied = 1; ++ if (op & VCOS_CONSUME) ++ flags->events &= ~bitmask; ++ } ++ break; ++ ++ case VCOS_OR: ++ if (flags->events & bitmask) ++ { ++ *retrieved_bits = flags->events; ++ rc = VCOS_SUCCESS; ++ satisfied = 1; ++ if (op & VCOS_CONSUME) ++ flags->events &= ~bitmask; ++ } ++ break; ++ ++ default: ++ vcos_assert(0); ++ rc = VCOS_EINVAL; ++ break; ++ } ++ ++ if (!satisfied && suspend) ++ { ++ /* Have to go to sleep. ++ * ++ * Append to tail so we get FIFO ordering. ++ */ ++ waitreq.requested_events = bitmask; ++ waitreq.op = op; ++ waitreq.return_status = VCOS_EAGAIN; ++ waitreq.flags = flags; ++ waitreq.actual_events = 0; ++ waitreq.thread = vcos_thread_current(); ++ waitreq.next = 0; ++ vcos_assert(waitreq.thread != (VCOS_THREAD_T*)-1); ++ VCOS_QUEUE_APPEND_TAIL(&flags->waiters, &waitreq); ++ ++ if (suspend != (VCOS_UNSIGNED)-1) ++ _vcos_task_timer_set(event_flags_timer_expired, &waitreq, suspend); ++ ++ vcos_mutex_unlock(&flags->lock); ++ /* go to sleep and wait to be signalled or timeout */ ++ ++ _vcos_thread_sem_wait(); ++ ++ *retrieved_bits = waitreq.actual_events; ++ rc = waitreq.return_status; ++ ++ /* cancel the timer - do not do this while holding the mutex as it ++ * might be waiting for the timeout function to complete, which will ++ * try to take the mutex. ++ */ ++ if (suspend != (VCOS_UNSIGNED)-1) ++ _vcos_task_timer_cancel(); ++ } ++ else ++ { ++ vcos_mutex_unlock(&flags->lock); ++ } ++ ++ return rc; ++} ++ ++ ++/** Called when a get call times out. Remove this thread's ++ * entry from the waiting queue, then resume the thread. ++ */ ++static void event_flags_timer_expired(void *cxt) ++{ ++ VCOS_EVENT_WAITER_T *waitreq = (VCOS_EVENT_WAITER_T *)cxt; ++ VCOS_EVENT_FLAGS_T *flags = waitreq->flags; ++ VCOS_EVENT_WAITER_T **plist; ++ VCOS_EVENT_WAITER_T *prev = NULL; ++ VCOS_THREAD_T *thread = 0; ++ ++ vcos_assert(flags); ++ ++ vcos_mutex_lock(&flags->lock); ++ ++ /* walk the list of waiting threads on this event group, and remove ++ * the one that has expired. ++ * ++ * FIXME: could use doubly-linked list if lots of threads are found ++ * to be waiting on a single event flag instance. ++ */ ++ plist = &flags->waiters.head; ++ while (*plist != NULL) ++ { ++ if (*plist == waitreq) ++ { ++ int at_end; ++ /* found it */ ++ thread = (*plist)->thread; ++ at_end = ((*plist)->next == NULL); ++ ++ /* link past */ ++ *plist = (*plist)->next; ++ if (at_end) ++ flags->waiters.tail = prev; ++ ++ break; ++ } ++ prev = *plist; ++ plist = &(*plist)->next; ++ } ++ vcos_assert(waiter_list_valid(flags)); ++ ++ vcos_mutex_unlock(&flags->lock); ++ ++ if (thread) ++ { ++ _vcos_thread_sem_post(thread); ++ } ++} ++ ++#ifndef NDEBUG ++ ++static int waiter_list_valid(VCOS_EVENT_FLAGS_T *flags) ++{ ++ int valid; ++ /* Either both head and tail are NULL, or neither are NULL */ ++ if (flags->waiters.head == NULL) ++ { ++ valid = (flags->waiters.tail == NULL); ++ } ++ else ++ { ++ valid = (flags->waiters.tail != NULL); ++ } ++ ++ /* If head and tail point at the same non-NULL element, then there ++ * is only one element in the list. ++ */ ++ if (flags->waiters.head && (flags->waiters.head == flags->waiters.tail)) ++ { ++ valid = (flags->waiters.head->next == NULL); ++ } ++ return valid; ++} ++ ++#endif +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/generic/vcos_generic_event_flags.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/generic/vcos_generic_event_flags.h 2013-07-26 19:32:00.000000000 +0000 +@@ -0,0 +1,104 @@ ++/*============================================================================= ++Copyright (c) 2009 Broadcom Europe Limited. ++All rights reserved. ++ ++FILE DESCRIPTION ++VideoCore OS Abstraction Layer - event flags implemented via a semaphore ++=============================================================================*/ ++ ++#ifndef VCOS_GENERIC_EVENT_FLAGS_H ++#define VCOS_GENERIC_EVENT_FLAGS_H ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++#include "interface/vcos/vcos_types.h" ++ ++/** ++ * \file ++ * ++ * This provides event flags (as per Nucleus Event Groups) based on a ++ * mutex, a semaphore (per waiting thread) and a timer (per waiting ++ * thread). ++ * ++ * The data structure is a 32 bit unsigned int (the current set of ++ * flags) and a linked list of clients waiting to be 'satisfied'. ++ * ++ * The mutex merely locks access to the data structure. If a client ++ * calls vcos_event_flags_get() and the requested bits are not already ++ * present, it then sleeps on its per-thread semaphore after adding ++ * this semaphore to the queue waiting. It also sets up a timer. ++ * ++ * The per-thread semaphore and timer are actually stored in the ++ * thread context (joinable thread). In future it may become necessary ++ * to support non-VCOS threads by using thread local storage to ++ * create these objects and associate them with the thread. ++ */ ++ ++struct VCOS_EVENT_WAITER_T; ++ ++typedef struct VCOS_EVENT_FLAGS_T ++{ ++ VCOS_UNSIGNED events; /**< Events currently set */ ++ VCOS_MUTEX_T lock; /**< Serialize access */ ++ struct ++ { ++ struct VCOS_EVENT_WAITER_T *head; /**< List of threads waiting */ ++ struct VCOS_EVENT_WAITER_T *tail; /**< List of threads waiting */ ++ } waiters; ++} VCOS_EVENT_FLAGS_T; ++ ++#define VCOS_OR 1 ++#define VCOS_AND 2 ++#define VCOS_CONSUME 4 ++#define VCOS_OR_CONSUME (VCOS_OR | VCOS_CONSUME) ++#define VCOS_AND_CONSUME (VCOS_AND | VCOS_CONSUME) ++#define VCOS_EVENT_FLAG_OP_MASK (VCOS_OR|VCOS_AND) ++ ++VCOSPRE_ VCOS_STATUS_T VCOSPOST_ vcos_generic_event_flags_create(VCOS_EVENT_FLAGS_T *flags, const char *name); ++VCOSPRE_ void VCOSPOST_ vcos_generic_event_flags_set(VCOS_EVENT_FLAGS_T *flags, ++ VCOS_UNSIGNED events, ++ VCOS_OPTION op); ++VCOSPRE_ void VCOSPOST_ vcos_generic_event_flags_delete(VCOS_EVENT_FLAGS_T *); ++VCOSPRE_ VCOS_STATUS_T VCOSPOST_ vcos_generic_event_flags_get(VCOS_EVENT_FLAGS_T *flags, ++ VCOS_UNSIGNED requested_events, ++ VCOS_OPTION op, ++ VCOS_UNSIGNED suspend, ++ VCOS_UNSIGNED *retrieved_events); ++ ++#ifdef VCOS_INLINE_BODIES ++ ++VCOS_INLINE_IMPL ++VCOS_STATUS_T vcos_event_flags_create(VCOS_EVENT_FLAGS_T *flags, const char *name) { ++ return vcos_generic_event_flags_create(flags, name); ++} ++ ++VCOS_INLINE_IMPL ++void vcos_event_flags_set(VCOS_EVENT_FLAGS_T *flags, ++ VCOS_UNSIGNED events, ++ VCOS_OPTION op) { ++ vcos_generic_event_flags_set(flags, events, op); ++} ++ ++VCOS_INLINE_IMPL ++void vcos_event_flags_delete(VCOS_EVENT_FLAGS_T *f) { ++ vcos_generic_event_flags_delete(f); ++} ++ ++VCOS_INLINE_IMPL ++VCOS_STATUS_T vcos_event_flags_get(VCOS_EVENT_FLAGS_T *flags, ++ VCOS_UNSIGNED requested_events, ++ VCOS_OPTION op, ++ VCOS_UNSIGNED suspend, ++ VCOS_UNSIGNED *retrieved_events) { ++ return vcos_generic_event_flags_get(flags, requested_events, op, suspend, retrieved_events); ++} ++ ++#endif /* VCOS_INLINE_BODIES */ ++ ++#ifdef __cplusplus ++} ++#endif ++#endif ++ +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/generic/vcos_generic_named_sem.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/generic/vcos_generic_named_sem.h 2013-07-26 19:32:00.000000000 +0000 +@@ -0,0 +1,81 @@ ++/*============================================================================= ++Copyright (c) 2009 Broadcom Europe Limited. ++All rights reserved. ++ ++Project : vcfw ++Module : chip driver ++ ++FILE DESCRIPTION ++VideoCore OS Abstraction Layer - named semaphores ++=============================================================================*/ ++ ++#ifndef VCOS_GENERIC_NAMED_SEM_H ++#define VCOS_GENERIC_NAMED_SEM_H ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++#include "interface/vcos/vcos_types.h" ++ ++/** ++ * \file ++ * ++ * Generic support for named semaphores, using regular ones. This is only ++ * suitable for emulating them on an embedded MMUless system, since there is ++ * no support for opening semaphores across process boundaries. ++ * ++ */ ++ ++#define VCOS_NAMED_SEMAPHORE_NAMELEN 64 ++ ++/* In theory we could use the name facility provided within Nucleus. However, this ++ * is hard to do as semaphores are constantly being created and destroyed; we ++ * would need to stop everything while allocating the memory for the semaphore ++ * list and then walking it. So keep our own list. ++ */ ++typedef struct VCOS_NAMED_SEMAPHORE_T ++{ ++ struct VCOS_NAMED_SEMAPHORE_IMPL_T *actual; /**< There are 'n' named semaphores per 1 actual semaphore */ ++ VCOS_SEMAPHORE_T *sem; /**< Pointer to actual underlying semaphore */ ++} VCOS_NAMED_SEMAPHORE_T; ++ ++VCOSPRE_ VCOS_STATUS_T VCOSPOST_ ++vcos_generic_named_semaphore_create(VCOS_NAMED_SEMAPHORE_T *sem, const char *name, VCOS_UNSIGNED count); ++ ++VCOSPRE_ void VCOSPOST_ vcos_named_semaphore_delete(VCOS_NAMED_SEMAPHORE_T *sem); ++ ++VCOSPRE_ VCOS_STATUS_T VCOSPOST_ _vcos_named_semaphore_init(void); ++VCOSPRE_ void VCOSPOST_ _vcos_named_semaphore_deinit(void); ++ ++#if defined(VCOS_INLINE_BODIES) ++ ++VCOS_INLINE_IMPL ++VCOS_STATUS_T vcos_named_semaphore_create(VCOS_NAMED_SEMAPHORE_T *sem, const char *name, VCOS_UNSIGNED count) { ++ return vcos_generic_named_semaphore_create(sem, name, count); ++} ++ ++VCOS_INLINE_IMPL ++void vcos_named_semaphore_wait(VCOS_NAMED_SEMAPHORE_T *sem) { ++ vcos_semaphore_wait(sem->sem); ++} ++ ++VCOS_INLINE_IMPL ++VCOS_STATUS_T vcos_named_semaphore_trywait(VCOS_NAMED_SEMAPHORE_T *sem) { ++ return vcos_semaphore_trywait(sem->sem); ++} ++ ++VCOS_INLINE_IMPL ++void vcos_named_semaphore_post(VCOS_NAMED_SEMAPHORE_T *sem) { ++ vcos_semaphore_post(sem->sem); ++} ++ ++ ++#endif ++ ++#ifdef __cplusplus ++} ++#endif ++#endif ++ ++ +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/generic/vcos_generic_quickslow_mutex.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/generic/vcos_generic_quickslow_mutex.h 2013-07-26 19:32:00.000000000 +0000 +@@ -0,0 +1,75 @@ ++/*============================================================================= ++Copyright (c) 2009 Broadcom Europe Limited. ++All rights reserved. ++ ++Project : vcfw ++Module : chip driver ++ ++FILE DESCRIPTION ++VideoCore OS Abstraction Layer - reentrant mutexes created from regular ones. ++=============================================================================*/ ++ ++#ifndef VCOS_GENERIC_QUICKSLOW_MUTEX_H ++#define VCOS_GENERIC_QUICKSLOW_MUTEX_H ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++#include "interface/vcos/vcos_types.h" ++ ++/** ++ * \file ++ * ++ * Quickslow Mutexes implemented as regular ones (i.e. quick and slow modes are the same). ++ * ++ */ ++ ++typedef VCOS_MUTEX_T VCOS_QUICKSLOW_MUTEX_T; ++ ++#if defined(VCOS_INLINE_BODIES) ++VCOS_INLINE_IMPL ++VCOS_STATUS_T vcos_quickslow_mutex_create(VCOS_QUICKSLOW_MUTEX_T *m, const char *name) ++{ ++ return vcos_mutex_create(m, name); ++} ++ ++VCOS_INLINE_IMPL ++void vcos_quickslow_mutex_delete(VCOS_QUICKSLOW_MUTEX_T *m) ++{ ++ vcos_mutex_delete(m); ++} ++ ++VCOS_INLINE_IMPL ++void vcos_quickslow_mutex_lock(VCOS_QUICKSLOW_MUTEX_T *m) ++{ ++ while (vcos_mutex_lock(m) == VCOS_EAGAIN); ++} ++ ++VCOS_INLINE_IMPL ++void vcos_quickslow_mutex_unlock(VCOS_QUICKSLOW_MUTEX_T *m) ++{ ++ vcos_mutex_unlock(m); ++} ++ ++VCOS_INLINE_IMPL ++void vcos_quickslow_mutex_lock_quick(VCOS_QUICKSLOW_MUTEX_T *m) ++{ ++ while (vcos_mutex_lock(m) == VCOS_EAGAIN); ++} ++ ++VCOS_INLINE_IMPL ++void vcos_quickslow_mutex_unlock_quick(VCOS_QUICKSLOW_MUTEX_T *m) ++{ ++ vcos_mutex_unlock(m); ++} ++ ++#endif ++ ++ ++#ifdef __cplusplus ++} ++#endif ++#endif ++ ++ +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/generic/vcos_generic_reentrant_mtx.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/generic/vcos_generic_reentrant_mtx.h 2013-07-26 19:32:00.000000000 +0000 +@@ -0,0 +1,75 @@ ++/*============================================================================= ++Copyright (c) 2009 Broadcom Europe Limited. ++All rights reserved. ++ ++Project : vcfw ++Module : chip driver ++ ++FILE DESCRIPTION ++VideoCore OS Abstraction Layer - reentrant mutexes created from regular ones. ++=============================================================================*/ ++ ++#ifndef VCOS_GENERIC_REENTRANT_MUTEX_H ++#define VCOS_GENERIC_REENTRANT_MUTEX_H ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++#include "interface/vcos/vcos_types.h" ++ ++/** ++ * \file ++ * ++ * Reentrant Mutexes from regular ones. ++ * ++ */ ++ ++typedef struct VCOS_REENTRANT_MUTEX_T ++{ ++ VCOS_MUTEX_T mutex; ++ VCOS_THREAD_T *owner; ++ unsigned count; ++} VCOS_REENTRANT_MUTEX_T; ++ ++/* Extern definitions of functions that do the actual work */ ++ ++VCOSPRE_ VCOS_STATUS_T VCOSPOST_ vcos_generic_reentrant_mutex_create(VCOS_REENTRANT_MUTEX_T *m, const char *name); ++ ++VCOSPRE_ void VCOSPOST_ vcos_generic_reentrant_mutex_delete(VCOS_REENTRANT_MUTEX_T *m); ++ ++VCOSPRE_ void VCOSPOST_ vcos_generic_reentrant_mutex_lock(VCOS_REENTRANT_MUTEX_T *m); ++ ++VCOSPRE_ void VCOSPOST_ vcos_generic_reentrant_mutex_unlock(VCOS_REENTRANT_MUTEX_T *m); ++ ++/* Inline forwarding functions */ ++ ++#if defined(VCOS_INLINE_BODIES) ++ ++VCOS_INLINE_IMPL ++VCOS_STATUS_T vcos_reentrant_mutex_create(VCOS_REENTRANT_MUTEX_T *m, const char *name) { ++ return vcos_generic_reentrant_mutex_create(m,name); ++} ++ ++VCOS_INLINE_IMPL ++void vcos_reentrant_mutex_delete(VCOS_REENTRANT_MUTEX_T *m) { ++ vcos_generic_reentrant_mutex_delete(m); ++} ++ ++VCOS_INLINE_IMPL ++void vcos_reentrant_mutex_lock(VCOS_REENTRANT_MUTEX_T *m) { ++ vcos_generic_reentrant_mutex_lock(m); ++} ++ ++VCOS_INLINE_IMPL ++void vcos_reentrant_mutex_unlock(VCOS_REENTRANT_MUTEX_T *m) { ++ vcos_generic_reentrant_mutex_unlock(m); ++} ++#endif ++ ++#ifdef __cplusplus ++} ++#endif ++#endif ++ ++ +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/generic/vcos_generic_tls.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/generic/vcos_generic_tls.h 2013-07-26 19:32:00.000000000 +0000 +@@ -0,0 +1,144 @@ ++/*============================================================================= ++Copyright (c) 2009 Broadcom Europe Limited. ++All rights reserved. ++ ++Project : vcfw ++Module : chip driver ++ ++FILE DESCRIPTION ++VideoCore OS Abstraction Layer - generic thread local storage ++=============================================================================*/ ++ ++#ifndef VCOS_GENERIC_TLS_H ++#define VCOS_GENERIC_TLS_H ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++#include "interface/vcos/vcos_types.h" ++ ++/** ++ * \file ++ * ++ * Do an emulation of Thread Local Storage. The platform needs to ++ * provide a way to set and get a per-thread pointer which is ++ * where the TLS data itself is stored. ++ * ++ * ++ * Each thread that wants to join in this scheme needs to call ++ * vcos_tls_thread_register(). ++ * ++ * The platform needs to support the macros/functions ++ * _vcos_tls_thread_ptr_set() and _vcos_tls_thread_ptr_get(). ++ */ ++ ++#ifndef VCOS_WANT_TLS_EMULATION ++#error Should not be included unless TLS emulation is defined ++#endif ++ ++/** Number of slots to reserve per thread. This results in an overhead ++ * of this many words per thread. ++ */ ++#define VCOS_TLS_MAX_SLOTS 4 ++ ++/** TLS key. Allocating one of these reserves the client one of the ++ * available slots. ++ */ ++typedef VCOS_UNSIGNED VCOS_TLS_KEY_T; ++ ++/** TLS per-thread structure. Each thread gets one of these ++ * if TLS emulation (rather than native TLS support) is ++ * being used. ++ */ ++typedef struct VCOS_TLS_THREAD_T ++{ ++ void *slots[VCOS_TLS_MAX_SLOTS]; ++} VCOS_TLS_THREAD_T; ++ ++/* ++ * Internal APIs ++ */ ++ ++/** Register this thread's TLS storage area. */ ++VCOSPRE_ void VCOSPOST_ vcos_tls_thread_register(VCOS_TLS_THREAD_T *); ++ ++/** Create a new TLS key */ ++VCOSPRE_ VCOS_STATUS_T VCOSPOST_ vcos_generic_tls_create(VCOS_TLS_KEY_T *key); ++ ++/** Delete a TLS key */ ++VCOSPRE_ void VCOSPOST_ vcos_generic_tls_delete(VCOS_TLS_KEY_T tls); ++ ++/** Initialise the TLS library */ ++VCOSPRE_ VCOS_STATUS_T VCOSPOST_ vcos_tls_init(void); ++ ++/** Deinitialise the TLS library */ ++VCOSPRE_ void VCOSPOST_ vcos_tls_deinit(void); ++ ++#if defined(VCOS_INLINE_BODIES) ++ ++#undef VCOS_ASSERT_LOGGING_DISABLE ++#define VCOS_ASSERT_LOGGING_DISABLE 1 ++ ++/* ++ * Implementations of public API functions ++ */ ++ ++/** Set the given value. Since everything is per-thread, there is no need ++ * for any locking. ++ */ ++VCOS_INLINE_IMPL ++VCOS_STATUS_T vcos_tls_set(VCOS_TLS_KEY_T tls, void *v) { ++ VCOS_TLS_THREAD_T *tlsdata = _vcos_tls_thread_ptr_get(); ++ vcos_assert(tlsdata); /* Fires if this thread has not been registered */ ++ if (tlsslots[tls] = v; ++ return VCOS_SUCCESS; ++ } ++ else ++ { ++ vcos_assert(0); ++ return VCOS_EINVAL; ++ } ++} ++ ++/** Get the given value. No locking required. ++ */ ++VCOS_INLINE_IMPL ++void *vcos_tls_get(VCOS_TLS_KEY_T tls) { ++ VCOS_TLS_THREAD_T *tlsdata = _vcos_tls_thread_ptr_get(); ++ vcos_assert(tlsdata); /* Fires if this thread has not been registered */ ++ if (tlsslots[tls]; ++ } ++ else ++ { ++ vcos_assert(0); ++ return NULL; ++ } ++} ++ ++VCOS_INLINE_IMPL ++VCOS_STATUS_T vcos_tls_create(VCOS_TLS_KEY_T *key) { ++ return vcos_generic_tls_create(key); ++} ++ ++VCOS_INLINE_IMPL ++void vcos_tls_delete(VCOS_TLS_KEY_T tls) { ++ vcos_generic_tls_delete(tls); ++} ++ ++#undef VCOS_ASSERT_LOGGING_DISABLE ++#define VCOS_ASSERT_LOGGING_DISABLE 0 ++ ++#endif /* VCOS_INLINE_BODIES */ ++ ++#ifdef __cplusplus ++} ++#endif ++ ++#endif ++ ++ +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/generic/vcos_joinable_thread_from_plain.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/generic/vcos_joinable_thread_from_plain.h 2013-07-26 19:32:00.000000000 +0000 +@@ -0,0 +1,202 @@ ++/*============================================================================= ++Copyright (c) 2009 Broadcom Europe Limited. ++All rights reserved. ++ ++Module : vcos ++ ++FILE DESCRIPTION ++VideoCore OS Abstraction Layer - implementation: joinable thread from plain ++=============================================================================*/ ++ ++/** \file ++ * ++ * Header file for platforms creating the joinable thread from a lowlevel ++ * thread. ++ * ++ * In addition to the actual thread, the following are also created: ++ * ++ * - a semaphore to wait on when joining the thread ++ * - a semaphore to support counted suspend/resume (used by event group) ++ * - a per-thread timer (used by event group, but could be removed) ++ */ ++ ++#ifndef VCOS_JOINABLE_THREAD_FROM_PLAIN_H ++#define VCOS_JOINABLE_THREAD_FROM_PLAIN_H ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++#include "interface/vcos/vcos_semaphore.h" ++#include "interface/vcos/vcos_lowlevel_thread.h" ++#include "interface/vcos/vcos_timer.h" ++ ++#ifdef VCOS_WANT_TLS_EMULATION ++#include "interface/vcos/generic/vcos_generic_tls.h" ++#endif ++ ++#define VCOS_THREAD_MAGIC 0x56436a74 ++ ++#define VCOS_THREAD_VALID(t) (t->magic == VCOS_THREAD_MAGIC) ++#define VCOS_HAVE_THREAD_AT_EXIT 1 ++ ++/** Thread attribute structure. Clients should not manipulate this directly, but ++ * should instead use the provided functions. ++ */ ++typedef struct VCOS_THREAD_ATTR_T ++{ ++ void *ta_stackaddr; ++ VCOS_UNSIGNED ta_stacksz; ++ VCOS_UNSIGNED ta_priority; ++ VCOS_UNSIGNED ta_affinity; ++ VCOS_UNSIGNED ta_timeslice; ++ VCOS_UNSIGNED legacy; ++ VCOS_UNSIGNED ta_autostart; ++} VCOS_THREAD_ATTR_T; ++ ++/** Each thread gets a timer, which is for internal VCOS use. ++ */ ++typedef struct _VCOS_THREAD_TIMER_T ++{ ++ VCOS_TIMER_T timer; ++ void (*pfn)(void *); ++ void *cxt; ++} _VCOS_THREAD_TIMER_T; ++ ++typedef void (*VCOS_THREAD_EXIT_HANDLER_T)(void *); ++/** Called at thread exit. ++ */ ++typedef struct VCOS_THREAD_EXIT_T ++{ ++ VCOS_THREAD_EXIT_HANDLER_T pfn; ++ void *cxt; ++} VCOS_THREAD_EXIT_T; ++#define VCOS_MAX_EXIT_HANDLERS 8 ++ ++/* The name field isn't used for anything, so we can just copy the ++ * the pointer. Nucleus makes its own copy. ++ */ ++typedef const char * VCOS_LLTHREAD_T_NAME; ++#define _VCOS_LLTHREAD_NAME(dst,src) (dst)=(src) ++ ++/* ++ * Simulated TLS support ++ */ ++ ++ ++/** Thread structure. ++ * ++ * \warning Do not access the members of this structure directly! ++ */ ++typedef struct VCOS_THREAD_T ++{ ++ VCOS_LLTHREAD_T thread; /**< The underlying thread */ ++ char name[16]; /**< The name */ ++ unsigned int magic; /**< For debug */ ++ void *exit_data; /**< Exit data passed out in vcos_joinable_thread_exit() */ ++ void *stack; /**< Stack, if not supplied by caller */ ++ VCOS_SEMAPHORE_T wait; /**< Semaphore to wait on at join */ ++ VCOS_SEMAPHORE_T suspend; /**< Semaphore to wait on for counted suspend */ ++ int16_t joined; /**< Joined yet? For debug. */ ++ VCOS_UNSIGNED legacy; /**< Use (argc,argv) for entry point arguments */ ++ void *(*entry)(void*); /**< Entry point */ ++ void *arg; /**< Argument passed to entry point */ ++ void *(*term)(void*); /**< Termination function, used by reaper */ ++ void *term_arg; /**< Argument passed to termination function */ ++ _VCOS_THREAD_TIMER_T _timer; /**< Internal timer, mainly for event groups */ ++#ifdef VCOS_WANT_TLS_EMULATION ++ VCOS_TLS_THREAD_T _tls; /**< TLS data when native TLS not available, or NULL */ ++#endif ++ /** Array of functions to call at thread exit */ ++ VCOS_THREAD_EXIT_T at_exit[VCOS_MAX_EXIT_HANDLERS]; ++ ++ struct VCOS_THREAD_T *next; /**< For linked lists of threads */ ++} VCOS_THREAD_T; ++ ++#if defined(VCOS_INLINE_BODIES) ++ ++VCOS_INLINE_IMPL ++void vcos_thread_attr_setstack(VCOS_THREAD_ATTR_T *attrs, void *addr, VCOS_UNSIGNED stacksz) { ++ attrs->ta_stackaddr = addr; ++ attrs->ta_stacksz = stacksz; ++} ++ ++VCOS_INLINE_IMPL ++void vcos_thread_attr_setstacksize(VCOS_THREAD_ATTR_T *attrs, VCOS_UNSIGNED stacksz) { ++ attrs->ta_stacksz = stacksz; ++} ++ ++VCOS_INLINE_IMPL ++void vcos_thread_attr_setpriority(VCOS_THREAD_ATTR_T *attrs, VCOS_UNSIGNED pri) { ++ attrs->ta_priority = pri; ++} ++ ++VCOS_INLINE_IMPL ++void vcos_thread_attr_setaffinity(VCOS_THREAD_ATTR_T *attrs, VCOS_UNSIGNED affinity) { ++ attrs->ta_affinity = affinity; ++} ++ ++VCOS_INLINE_IMPL ++void vcos_thread_attr_settimeslice(VCOS_THREAD_ATTR_T *attrs, VCOS_UNSIGNED ts) { ++ attrs->ta_timeslice = ts; ++} ++ ++VCOS_INLINE_IMPL ++void _vcos_thread_attr_setlegacyapi(VCOS_THREAD_ATTR_T *attrs, VCOS_UNSIGNED legacy) { ++ attrs->legacy = legacy; ++} ++ ++VCOS_INLINE_IMPL ++void vcos_thread_attr_setautostart(VCOS_THREAD_ATTR_T *attrs, VCOS_UNSIGNED autostart) { ++ attrs->ta_autostart = autostart; ++} ++ ++VCOS_INLINE_IMPL ++VCOS_THREAD_T *vcos_thread_current(void) { ++ VCOS_THREAD_T *ret = (VCOS_THREAD_T*)vcos_llthread_current(); ++ /*If we're called from a non-vcos thread, this assert will fail. ++ *XXX FIXME why is this commented out? ++ *vcos_assert(ret->magic == VCOS_THREAD_MAGIC); ++ */ ++ return ret; ++} ++ ++VCOS_INLINE_IMPL ++int vcos_thread_running(VCOS_THREAD_T *thread) { ++ return vcos_llthread_running(&thread->thread); ++} ++ ++VCOS_INLINE_IMPL ++void vcos_thread_resume(VCOS_THREAD_T *thread) { ++ vcos_llthread_resume(&thread->thread); ++} ++ ++#endif /* VCOS_INLINE_BODIES */ ++ ++/** ++ * \brief Create a VCOS_THREAD_T for the current thread. This is so we can have ++ * VCOS_THREAD_Ts even for threads not originally created by VCOS (eg the ++ * thread that calls vcos_init) ++ */ ++extern VCOS_STATUS_T _vcos_thread_create_attach(VCOS_THREAD_T *thread, ++ const char *name); ++ ++/** ++ * \brief Deletes the VCOS_THREAD_T, but does not wait for the underlying ++ * thread to exit. This will cleanup everything created by ++ * _vcos_thread_create_attach ++ */ ++extern void _vcos_thread_delete(VCOS_THREAD_T *thread); ++ ++/** Register a function to be called when the current thread exits. ++ */ ++extern VCOS_STATUS_T vcos_thread_at_exit(void (*pfn)(void*), void *cxt); ++ ++/** Deregister a previously registered at-exit function. ++ */ ++extern void vcos_thread_deregister_at_exit(void (*pfn)(void*), void *cxt); ++ ++#ifdef __cplusplus ++} ++#endif ++#endif /* VCOS_JOINABLE_THREAD_FROM_PLAIN_H */ +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/generic/vcos_latch_from_sem.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/generic/vcos_latch_from_sem.h 2013-07-26 19:32:00.000000000 +0000 +@@ -0,0 +1,48 @@ ++/*============================================================================= ++Copyright (c) 2009 Broadcom Europe Limited. ++All rights reserved. ++ ++Project : vcfw ++Module : vcos ++ ++FILE DESCRIPTION ++VideoCore OS Abstraction Layer - Construct a latch from a semaphore ++=============================================================================*/ ++ ++/** FIXME: rename to vcos_mutex_from_sem.c ++ */ ++ ++typedef struct VCOS_MUTEX_T { ++ VCOS_SEMAPHORE_T sem; ++ struct VCOS_THREAD_T *owner; ++} VCOS_MUTEX_T; ++ ++extern VCOS_STATUS_T vcos_generic_mutex_create(VCOS_MUTEX_T *latch, const char *name); ++extern void vcos_generic_mutex_delete(VCOS_MUTEX_T *latch); ++extern VCOS_STATUS_T vcos_generic_mutex_lock(VCOS_MUTEX_T *latch); ++extern void vcos_generic_mutex_unlock(VCOS_MUTEX_T *latch); ++ ++#if defined(VCOS_INLINE_BODIES) ++ ++VCOS_INLINE_IMPL ++VCOS_STATUS_T vcos_mutex_create(VCOS_MUTEX_T *latch, const char *name) { ++ return vcos_generic_mutex_create(latch,name); ++} ++ ++VCOS_INLINE_IMPL ++void vcos_mutex_delete(VCOS_MUTEX_T *latch) { ++ vcos_generic_mutex_delete(latch); ++} ++ ++VCOS_INLINE_IMPL ++VCOS_STATUS_T vcos_mutex_lock(VCOS_MUTEX_T *latch) { ++ return vcos_generic_mutex_lock(latch); ++} ++ ++VCOS_INLINE_IMPL ++void vcos_mutex_unlock(VCOS_MUTEX_T *latch) { ++ vcos_generic_mutex_unlock(latch); ++} ++ ++#endif /* VCOS_INLINE_BODIES */ ++ +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/generic/vcos_logcat.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/generic/vcos_logcat.c 2013-07-26 19:32:00.000000000 +0000 +@@ -0,0 +1,549 @@ ++/*============================================================================= ++Copyright (c) 2010 Broadcom Europe Limited. ++All rights reserved. ++ ++Project : vcfw ++Module : vcos ++ ++FILE DESCRIPTION ++Categorized logging for VCOS - a generic implementation. ++=============================================================================*/ ++ ++#include "interface/vcos/vcos.h" ++#include "interface/vcos/vcos_ctype.h" ++#include "interface/vcos/vcos_string.h" ++ ++static VCOS_MUTEX_T lock; ++static int warned_loglevel; /* only warn about invalid log level once */ ++static VCOS_VLOG_IMPL_FUNC_T vcos_vlog_impl_func = vcos_vlog_default_impl; ++ ++#define VCOS_LOG_CATEGORY (&dflt_log_category) ++static VCOS_LOG_CAT_T dflt_log_category; ++VCOS_LOG_CAT_T *vcos_logging_categories = NULL; ++static int inited; ++ ++#if VCOS_HAVE_CMD ++ ++/* ++ * For kernel or videocore purposes, we generally want the log command. For ++ * user-space apps, they might want to provide their own log command, so we ++ * don't include the built in on. ++ * ++ * So pthreads/vcos_platform.h defines VCOS_WANT_LOG_CMD to be 0. It is ++ * undefined elsewhere. ++ */ ++ ++# if !defined( VCOS_WANT_LOG_CMD ) ++# define VCOS_WANT_LOG_CMD 1 ++# endif ++#else ++# define VCOS_WANT_LOG_CMD 0 ++#endif ++ ++#if VCOS_WANT_LOG_CMD ++ ++/***************************************************************************** ++* ++* Does a vcos_assert(0), which is useful to test logging. ++* ++*****************************************************************************/ ++ ++VCOS_STATUS_T vcos_log_assert_cmd( VCOS_CMD_PARAM_T *param ) ++{ ++ (void)param; ++ ++#if defined( NDEBUG ) && !defined( VCOS_RELEASE_ASSERTS ) ++ vcos_log_error( "vcos_asserts have been compiled out" ); ++ vcos_cmd_printf( param, "vcos_asserts have been compiled out - did a vcos_log_error instead\n" ); ++#else ++ vcos_assert(0); ++ vcos_cmd_printf( param, "Executed vcos_assert(0)\n" ); ++#endif ++ ++ return VCOS_SUCCESS; ++} ++ ++/***************************************************************************** ++* ++* Sets a vcos logging level ++* ++*****************************************************************************/ ++ ++VCOS_STATUS_T vcos_log_set_cmd( VCOS_CMD_PARAM_T *param ) ++{ ++ VCOS_LOG_CAT_T *cat; ++ char *name; ++ char *levelStr; ++ VCOS_LOG_LEVEL_T level; ++ VCOS_STATUS_T status; ++ ++ if ( param->argc != 3 ) ++ { ++ vcos_cmd_usage( param ); ++ return VCOS_EINVAL; ++ } ++ ++ name = param->argv[1]; ++ levelStr = param->argv[2]; ++ ++ if ( vcos_string_to_log_level( levelStr, &level ) != VCOS_SUCCESS ) ++ { ++ vcos_cmd_printf( param, "Unrecognized logging level: '%s'\n", levelStr ); ++ return VCOS_EINVAL; ++ } ++ ++ vcos_mutex_lock(&lock); ++ ++ status = VCOS_SUCCESS; ++ for ( cat = vcos_logging_categories; cat != NULL; cat = cat->next ) ++ { ++ if ( vcos_strcmp( name, cat->name ) == 0 ) ++ { ++ cat->level = level; ++ vcos_cmd_printf( param, "Category %s level set to %s\n", name, levelStr ); ++ break; ++ } ++ } ++ if ( cat == NULL ) ++ { ++ vcos_cmd_printf( param, "Unrecognized category: '%s'\n", name ); ++ status = VCOS_ENOENT; ++ } ++ ++ vcos_mutex_unlock(&lock); ++ ++ return status; ++} ++ ++/***************************************************************************** ++* ++* Prints out the current settings for a given category (or all cvategories) ++* ++*****************************************************************************/ ++ ++VCOS_STATUS_T vcos_log_status_cmd( VCOS_CMD_PARAM_T *param ) ++{ ++ VCOS_LOG_CAT_T *cat; ++ VCOS_STATUS_T status; ++ ++ vcos_mutex_lock(&lock); ++ ++ if ( param->argc == 1) ++ { ++ int nw; ++ int nameWidth = 0; ++ ++ /* Print information about all of the categories. */ ++ ++ for ( cat = vcos_logging_categories; cat != NULL; cat = cat->next ) ++ { ++ nw = (int)strlen( cat->name ); ++ ++ if ( nw > nameWidth ) ++ { ++ nameWidth = nw; ++ } ++ } ++ ++ for ( cat = vcos_logging_categories; cat != NULL; cat = cat->next ) ++ { ++ vcos_cmd_printf( param, "%-*s - %s\n", nameWidth, cat->name, vcos_log_level_to_string( cat->level )); ++ } ++ } ++ else ++ { ++ /* Print information about a particular category */ ++ ++ for ( cat = vcos_logging_categories; cat != NULL; cat = cat->next ) ++ { ++ if ( vcos_strcmp( cat->name, param->argv[1] ) == 0 ) ++ { ++ vcos_cmd_printf( param, "%s - %s\n", cat->name, vcos_log_level_to_string( cat->level )); ++ break; ++ } ++ } ++ if ( cat == NULL ) ++ { ++ vcos_cmd_printf( param, "Unrecognized logging category: '%s'\n", param->argv[1] ); ++ status = VCOS_ENOENT; ++ goto out; ++ } ++ } ++ ++ status = VCOS_SUCCESS; ++out: ++ vcos_mutex_unlock(&lock); ++ ++ return status; ++} ++ ++/***************************************************************************** ++* ++* Prints out the current settings for a given category (or all cvategories) ++* ++*****************************************************************************/ ++ ++VCOS_STATUS_T vcos_log_test_cmd( VCOS_CMD_PARAM_T *param ) ++{ ++ if ( param->argc == 1 ) ++ { ++ static int seq_num = 100; ++ ++ /* No additional arguments - generate a message with an incrementing number */ ++ ++ vcos_log_error( "Test message %d", seq_num ); ++ ++ seq_num++; ++ vcos_cmd_printf( param, "Logged 'Test message %d'\n", seq_num ); ++ } ++ else ++ { ++ int arg_idx; ++ ++ /* Arguments supplied - log these */ ++ ++ for ( arg_idx = 0; arg_idx < param->argc; arg_idx++ ) ++ { ++ vcos_log_error( "argv[%d] = '%s'", arg_idx, param->argv[arg_idx] ); ++ } ++ vcos_cmd_printf( param, "Logged %d line(s) of test data\n", param->argc ); ++ } ++ return VCOS_SUCCESS; ++} ++ ++/***************************************************************************** ++* ++* Internal commands ++* ++*****************************************************************************/ ++ ++static VCOS_CMD_T log_cmd_entry[] = ++{ ++ { "assert", "", vcos_log_assert_cmd, NULL, "Does a vcos_assert(0) to test logging" }, ++ { "set", "category level", vcos_log_set_cmd, NULL, "Sets the vcos logging level for a category" }, ++ { "status", "[category]", vcos_log_status_cmd, NULL, "Prints the vcos log status for a (or all) categories" }, ++ { "test", "[arbitrary text]", vcos_log_test_cmd, NULL, "Does a vcos_log to test logging" }, ++ ++ { NULL, NULL, NULL, NULL, NULL } ++}; ++ ++static VCOS_CMD_T cmd_log = ++ { "log", "command [args]", NULL, log_cmd_entry, "Commands related to vcos logging" }; ++ ++#endif ++ ++void vcos_logging_init(void) ++{ ++ if (inited) ++ { ++ /* FIXME: should print a warning or something here */ ++ return; ++ } ++ vcos_mutex_create(&lock, "vcos_log"); ++ ++ vcos_log_platform_init(); ++ ++ vcos_log_register("default", &dflt_log_category); ++ ++#if VCOS_WANT_LOG_CMD ++ vcos_cmd_register( &cmd_log ); ++#endif ++ ++ vcos_assert(!inited); ++ inited = 1; ++} ++ ++/** Read an alphanumeric token, returning True if we succeeded. ++ */ ++ ++static int read_tok(char *tok, size_t toklen, const char **pstr, char sep) ++{ ++ const char *str = *pstr; ++ size_t n = 0; ++ char ch; ++ ++ /* skip past any whitespace */ ++ while (str[0] && isspace((int)(str[0]))) ++ str++; ++ ++ while ((ch = *str) != '\0' && ++ ch != sep && ++ (isalnum((int)ch) || (ch == '_')) && ++ n != toklen-1) ++ { ++ tok[n++] = ch; ++ str++; ++ } ++ ++ /* did it work out? */ ++ if (ch == '\0' || ch == sep) ++ { ++ if (ch) str++; /* move to next token if not at end */ ++ /* yes */ ++ tok[n] = '\0'; ++ *pstr = str; ++ return 1; ++ } ++ else ++ { ++ /* no */ ++ return 0; ++ } ++} ++ ++const char *vcos_log_level_to_string( VCOS_LOG_LEVEL_T level ) ++{ ++ switch (level) ++ { ++ case VCOS_LOG_UNINITIALIZED: return "uninit"; ++ case VCOS_LOG_NEVER: return "never"; ++ case VCOS_LOG_ERROR: return "error"; ++ case VCOS_LOG_WARN: return "warn"; ++ case VCOS_LOG_INFO: return "info"; ++ case VCOS_LOG_TRACE: return "trace"; ++ } ++ return "???"; ++} ++ ++VCOS_STATUS_T vcos_string_to_log_level( const char *str, VCOS_LOG_LEVEL_T *level ) ++{ ++ if (strcmp(str,"error") == 0) ++ *level = VCOS_LOG_ERROR; ++ else if (strcmp(str,"never") == 0) ++ *level = VCOS_LOG_NEVER; ++ else if (strcmp(str,"warn") == 0) ++ *level = VCOS_LOG_WARN; ++ else if (strcmp(str,"warning") == 0) ++ *level = VCOS_LOG_WARN; ++ else if (strcmp(str,"info") == 0) ++ *level = VCOS_LOG_INFO; ++ else if (strcmp(str,"trace") == 0) ++ *level = VCOS_LOG_TRACE; ++ else ++ return VCOS_EINVAL; ++ ++ return VCOS_SUCCESS; ++} ++ ++static int read_level(VCOS_LOG_LEVEL_T *level, const char **pstr, char sep) ++{ ++ char buf[16]; ++ int ret = 1; ++ if (read_tok(buf,sizeof(buf),pstr,sep)) ++ { ++ if (vcos_string_to_log_level(buf,level) != VCOS_SUCCESS) ++ { ++ vcos_log("Invalid trace level '%s'\n", buf); ++ ret = 0; ++ } ++ } ++ else ++ { ++ ret = 0; ++ } ++ return ret; ++} ++ ++void vcos_log_register(const char *name, VCOS_LOG_CAT_T *category) ++{ ++ const char *env; ++ VCOS_LOG_CAT_T *i; ++ ++ category->name = name; ++ if ( category->level == VCOS_LOG_UNINITIALIZED ) ++ { ++ category->level = VCOS_LOG_ERROR; ++ } ++ category->flags.want_prefix = (category != &dflt_log_category ); ++ ++ vcos_mutex_lock(&lock); ++ ++ /* is it already registered? */ ++ for (i = vcos_logging_categories; i ; i = i->next ) ++ { ++ if (i == category) ++ { ++ i->refcount++; ++ break; ++ } ++ } ++ ++ if (!i) ++ { ++ /* not yet registered */ ++ category->next = vcos_logging_categories; ++ vcos_logging_categories = category; ++ category->refcount++; ++ ++ vcos_log_platform_register(category); ++ } ++ ++ vcos_mutex_unlock(&lock); ++ ++ /* Check to see if this log level has been enabled. Look for ++ * (,)* ++ * ++ * VC_LOGLEVEL=ilcs:info,vchiq:warn ++ */ ++ ++ env = _VCOS_LOG_LEVEL(); ++ if (env) ++ { ++ do ++ { ++ char env_name[64]; ++ VCOS_LOG_LEVEL_T level; ++ if (read_tok(env_name, sizeof(env_name), &env, ':') && ++ read_level(&level, &env, ',')) ++ { ++ if (strcmp(env_name, name) == 0) ++ { ++ category->level = level; ++ break; ++ } ++ } ++ else ++ { ++ if (!warned_loglevel) ++ { ++ vcos_log("VC_LOGLEVEL format invalid at %s\n", env); ++ warned_loglevel = 1; ++ } ++ return; ++ } ++ } while (env[0] != '\0'); ++ } ++ ++ vcos_log_info( "Registered log category '%s' with level %s", ++ category->name, ++ vcos_log_level_to_string( category->level )); ++} ++ ++void vcos_log_unregister(VCOS_LOG_CAT_T *category) ++{ ++ VCOS_LOG_CAT_T **pcat; ++ vcos_mutex_lock(&lock); ++ category->refcount--; ++ if (category->refcount == 0) ++ { ++ pcat = &vcos_logging_categories; ++ while (*pcat != category) ++ { ++ if (!*pcat) ++ break; /* possibly deregistered twice? */ ++ if ((*pcat)->next == NULL) ++ { ++ vcos_assert(0); /* already removed! */ ++ vcos_mutex_unlock(&lock); ++ return; ++ } ++ pcat = &(*pcat)->next; ++ } ++ if (*pcat) ++ *pcat = category->next; ++ ++ vcos_log_platform_unregister(category); ++ } ++ vcos_mutex_unlock(&lock); ++} ++ ++VCOSPRE_ const VCOS_LOG_CAT_T * VCOSPOST_ vcos_log_get_default_category(void) ++{ ++ return &dflt_log_category; ++} ++ ++void vcos_set_log_options(const char *opt) ++{ ++ (void)opt; ++} ++ ++void vcos_log_dump_mem_impl( const VCOS_LOG_CAT_T *cat, ++ const char *label, ++ uint32_t addr, ++ const void *voidMem, ++ size_t numBytes ) ++{ ++ const uint8_t *mem = (const uint8_t *)voidMem; ++ size_t offset; ++ char lineBuf[ 100 ]; ++ char *s; ++ ++ while ( numBytes > 0 ) ++ { ++ s = lineBuf; ++ ++ for ( offset = 0; offset < 16; offset++ ) ++ { ++ if ( offset < numBytes ) ++ { ++ s += vcos_snprintf( s, 4, "%02x ", mem[ offset ]); ++ } ++ else ++ { ++ s += vcos_snprintf( s, 4, " " ); ++ } ++ } ++ ++ for ( offset = 0; offset < 16; offset++ ) ++ { ++ if ( offset < numBytes ) ++ { ++ uint8_t ch = mem[ offset ]; ++ ++ if (( ch < ' ' ) || ( ch > '~' )) ++ { ++ ch = '.'; ++ } ++ *s++ = (char)ch; ++ } ++ } ++ *s++ = '\0'; ++ ++ if (( label != NULL ) && ( *label != '\0' )) ++ { ++ vcos_log_impl( cat, VCOS_LOG_INFO, "%s: %08x: %s", label, addr, lineBuf ); ++ } ++ else ++ { ++ vcos_log_impl( cat, VCOS_LOG_INFO, "%08x: %s", addr, lineBuf ); ++ } ++ ++ addr += 16; ++ mem += 16; ++ if ( numBytes > 16 ) ++ { ++ numBytes -= 16; ++ } ++ else ++ { ++ numBytes = 0; ++ } ++ } ++ ++} ++ ++void vcos_log_impl(const VCOS_LOG_CAT_T *cat, VCOS_LOG_LEVEL_T _level, const char *fmt, ...) ++{ ++ va_list ap; ++ va_start(ap,fmt); ++ vcos_vlog_impl( cat, _level, fmt, ap ); ++ va_end(ap); ++} ++ ++void vcos_vlog_impl(const VCOS_LOG_CAT_T *cat, VCOS_LOG_LEVEL_T _level, const char *fmt, va_list args) ++{ ++ vcos_vlog_impl_func( cat, _level, fmt, args ); ++} ++ ++void vcos_set_vlog_impl( VCOS_VLOG_IMPL_FUNC_T vlog_impl_func ) ++{ ++ if ( vlog_impl_func == NULL ) ++ { ++ vcos_vlog_impl_func = vcos_vlog_default_impl; ++ } ++ else ++ { ++ vcos_vlog_impl_func = vlog_impl_func; ++ } ++} ++ +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/generic/vcos_mem_from_malloc.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/generic/vcos_mem_from_malloc.c 2013-07-26 19:32:00.000000000 +0000 +@@ -0,0 +1,73 @@ ++/*============================================================================= ++Copyright (c) 2009 Broadcom Europe Limited. ++All rights reserved. ++ ++Project : vcfw ++Module : vcos ++ ++FILE DESCRIPTION ++VideoCore OS Abstraction Layer - memory alloc implementation ++=============================================================================*/ ++ ++#include "interface/vcos/vcos.h" ++ ++#ifndef _vcos_platform_malloc ++#include ++#define _vcos_platform_malloc malloc ++#define _vcos_platform_free free ++#endif ++ ++typedef struct malloc_header_s { ++ uint32_t guardword; ++ uint32_t size; ++ const char *description; ++ void *ptr; ++} MALLOC_HEADER_T; ++ ++ ++#define MIN_ALIGN sizeof(MALLOC_HEADER_T) ++ ++#define GUARDWORDHEAP 0xa55a5aa5 ++ ++void *vcos_generic_mem_alloc_aligned(VCOS_UNSIGNED size, VCOS_UNSIGNED align, const char *desc) ++{ ++ int local_align = align == 0 ? 1 : align; ++ int required_size = size + local_align + sizeof(MALLOC_HEADER_T); ++ void *ptr = _vcos_platform_malloc(required_size); ++ void *ret = (void *)VCOS_ALIGN_UP(((char *)ptr)+sizeof(MALLOC_HEADER_T), local_align); ++ MALLOC_HEADER_T *h = ((MALLOC_HEADER_T *)ret)-1; ++ ++ h->size = size; ++ h->description = desc; ++ h->guardword = GUARDWORDHEAP; ++ h->ptr = ptr; ++ ++ return ret; ++} ++ ++void *vcos_generic_mem_alloc(VCOS_UNSIGNED size, const char *desc) ++{ ++ return vcos_generic_mem_alloc_aligned(size,MIN_ALIGN,desc); ++} ++ ++void *vcos_generic_mem_calloc(VCOS_UNSIGNED count, VCOS_UNSIGNED sz, const char *desc) ++{ ++ uint32_t size = count*sz; ++ void *ptr = vcos_generic_mem_alloc_aligned(size,MIN_ALIGN,desc); ++ if (ptr) ++ { ++ memset(ptr, 0, size); ++ } ++ return ptr; ++} ++ ++void vcos_generic_mem_free(void *ptr) ++{ ++ MALLOC_HEADER_T *h; ++ if (! ptr) return; ++ ++ h = ((MALLOC_HEADER_T *)ptr)-1; ++ vcos_assert(h->guardword == GUARDWORDHEAP); ++ _vcos_platform_free(h->ptr); ++} ++ +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/generic/vcos_mem_from_malloc.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/generic/vcos_mem_from_malloc.h 2013-07-26 19:32:00.000000000 +0000 +@@ -0,0 +1,54 @@ ++/*============================================================================= ++Copyright (c) 2009 Broadcom Europe Limited. ++All rights reserved. ++ ++Project : VMCS Host Apps ++Module : Framework - VMCS ++ ++FILE DESCRIPTION ++Create the vcos_malloc API from the regular system malloc/free ++=============================================================================*/ ++ ++/** ++ * \file ++ * ++ * Create the vcos malloc API from a regular system malloc/free library. ++ * ++ * The API lets callers specify an alignment. ++ * ++ * Under VideoCore this is not needed, as we can simply use the rtos_malloc routines. ++ * But on host platforms that won't be the case. ++ * ++ */ ++ ++VCOSPRE_ void * VCOSPOST_ vcos_generic_mem_alloc(VCOS_UNSIGNED sz, const char *desc); ++VCOSPRE_ void * VCOSPOST_ vcos_generic_mem_calloc(VCOS_UNSIGNED count, VCOS_UNSIGNED sz, const char *descr); ++VCOSPRE_ void VCOSPOST_ vcos_generic_mem_free(void *ptr); ++VCOSPRE_ void * VCOSPOST_ vcos_generic_mem_alloc_aligned(VCOS_UNSIGNED sz, VCOS_UNSIGNED align, const char *desc); ++ ++#ifdef VCOS_INLINE_BODIES ++ ++VCOS_INLINE_IMPL ++void *vcos_malloc(VCOS_UNSIGNED size, const char *description) { ++ return vcos_generic_mem_alloc(size, description); ++} ++ ++VCOS_INLINE_IMPL ++void *vcos_calloc(VCOS_UNSIGNED num, VCOS_UNSIGNED size, const char *description) { ++ return vcos_generic_mem_calloc(num, size, description); ++} ++ ++VCOS_INLINE_IMPL ++void vcos_free(void *ptr) { ++ vcos_generic_mem_free(ptr); ++} ++ ++VCOS_INLINE_IMPL ++void * vcos_malloc_aligned(VCOS_UNSIGNED size, VCOS_UNSIGNED align, const char *description) { ++ return vcos_generic_mem_alloc_aligned(size, align, description); ++} ++ ++ ++#endif /* VCOS_INLINE_BODIES */ ++ ++ +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/generic/vcos_mutexes_are_reentrant.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/generic/vcos_mutexes_are_reentrant.h 2013-07-26 19:32:00.000000000 +0000 +@@ -0,0 +1,68 @@ ++/*============================================================================= ++Copyright (c) 2009 Broadcom Europe Limited. ++All rights reserved. ++ ++Project : vcfw ++Module : chip driver ++ ++FILE DESCRIPTION ++VideoCore OS Abstraction Layer - reentrant mutexes mapped directly to regular ones ++=============================================================================*/ ++ ++#ifndef VCOS_GENERIC_REENTRANT_MUTEX_H ++#define VCOS_GENERIC_REENTRANT_MUTEX_H ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++#include "interface/vcos/vcos_types.h" ++#include "interface/vcos/vcos_mutex.h" ++ ++/** ++ * \file ++ * ++ * Reentrant Mutexes directly using the native re-entrant mutex. ++ * ++ */ ++ ++typedef VCOS_MUTEX_T VCOS_REENTRANT_MUTEX_T; ++ ++/* Inline forwarding functions */ ++ ++#if defined(VCOS_INLINE_BODIES) ++ ++VCOS_INLINE_IMPL ++VCOS_STATUS_T vcos_reentrant_mutex_create(VCOS_REENTRANT_MUTEX_T *m, const char *name) { ++ return vcos_mutex_create(m,name); ++} ++ ++VCOS_INLINE_IMPL ++void vcos_reentrant_mutex_delete(VCOS_REENTRANT_MUTEX_T *m) { ++ vcos_mutex_delete(m); ++} ++ ++VCOS_INLINE_IMPL ++void vcos_reentrant_mutex_lock(VCOS_REENTRANT_MUTEX_T *m) { ++ vcos_mutex_lock(m); ++} ++ ++VCOS_INLINE_IMPL ++void vcos_reentrant_mutex_unlock(VCOS_REENTRANT_MUTEX_T *m) { ++ vcos_mutex_unlock(m); ++} ++ ++VCOS_INLINE_IMPL ++int vcos_reentrant_mutex_is_locked(VCOS_REENTRANT_MUTEX_T *m) { ++ return vcos_mutex_is_locked(m); ++} ++ ++#endif ++ ++#ifdef __cplusplus ++} ++#endif ++#endif ++ ++ ++ +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/generic/vcos_thread_reaper.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/generic/vcos_thread_reaper.h 2013-07-26 19:32:00.000000000 +0000 +@@ -0,0 +1,35 @@ ++/*============================================================================= ++Copyright (c) 2010 Broadcom Europe Limited. ++All rights reserved. ++ ++Project : vcfw ++Module : vcos ++ ++FILE DESCRIPTION ++VideoCore OS Abstraction Layer - thread reaping ++=============================================================================*/ ++ ++#ifndef VCOS_THREAD_REAPER_H ++#define VCOS_THREAD_REAPER_H ++ ++#define VCOS_HAVE_THREAD_REAPER ++ ++/** Initialise the thread reaper. ++ */ ++VCOS_STATUS_T vcos_thread_reaper_init(void); ++ ++/** Reap a thread. Arranges for the thread to be automatically ++ * joined. ++ * ++ * @sa vcos_thread_join(). ++ * ++ * @param thread the thread to terminate ++ * @param on_terminated called after the thread has exited ++ * @param cxt pass back to the callback ++ * ++ */ ++void vcos_thread_reap(VCOS_THREAD_T *thread, void (*on_terminated)(void*), void *cxt); ++ ++#endif ++ ++ +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/linuxkernel/stdint.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/linuxkernel/stdint.h 2013-07-26 19:32:00.000000000 +0000 +@@ -0,0 +1,17 @@ ++/*============================================================================= ++Copyright (c) 2010 Broadcom Europe Limited. ++All rights reserved. ++ ++FILE DESCRIPTION ++VideoCore OS fAbstraction Layer - stdint.h C standard header ++=============================================================================*/ ++ ++#ifndef _VCOS_PLATFORM_LINUX_STDINT_H ++#define _VCOS_PLATFORM_LINUX_STDINT_H ++ ++/* The Linux kernel does not have a so we have to provide one of ++ our own. */ ++ ++#include /* includes integer types */ ++ ++#endif /* _VCOS_PLATFORM_LINUX_STDINT_H */ +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/linuxkernel/vcos_linuxkernel.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/linuxkernel/vcos_linuxkernel.c 2013-07-26 19:32:00.000000000 +0000 +@@ -0,0 +1,616 @@ ++/*============================================================================= ++Copyright (c) 2009 Broadcom Europe Limited. ++All rights reserved. ++ ++Project : vcfw ++Module : vcos ++ ++FILE DESCRIPTION ++VideoCore OS Abstraction Layer - pthreads types ++=============================================================================*/ ++ ++#define VCOS_INLINE_BODIES ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#if defined( CONFIG_BCM_KNLLOG_SUPPORT ) ++#include ++#endif ++#include "interface/vcos/vcos.h" ++#ifdef HAVE_VCOS_VERSION ++#include "interface/vcos/vcos_build_info.h" ++#endif ++ ++VCOS_CFG_ENTRY_T vcos_cfg_dir; ++VCOS_CFG_ENTRY_T vcos_logging_cfg_dir; ++VCOS_CFG_ENTRY_T vcos_version_cfg; ++ ++#ifndef VCOS_DEFAULT_STACK_SIZE ++#define VCOS_DEFAULT_STACK_SIZE 4096 ++#endif ++ ++static VCOS_THREAD_ATTR_T default_attrs = { ++ 0, ++ VCOS_DEFAULT_STACK_SIZE, ++}; ++ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,36) ++static DEFINE_SEMAPHORE(lock); ++#else ++static DECLARE_MUTEX(lock); ++#endif ++ ++typedef void (*LEGACY_ENTRY_FN_T)(int, void *); ++ ++/** Wrapper function around the real thread function. Posts the semaphore ++ * when completed. ++ */ ++static int vcos_thread_wrapper(void *arg) ++{ ++ void *ret; ++ VCOS_THREAD_T *thread = arg; ++ ++ vcos_assert(thread->magic == VCOS_THREAD_MAGIC); ++ ++ thread->thread.thread = current; ++ ++ vcos_add_thread(thread); ++ ++#ifdef VCOS_WANT_TLS_EMULATION ++ vcos_tls_thread_register(&thread->_tls); ++#endif ++ ++ if (thread->legacy) ++ { ++ LEGACY_ENTRY_FN_T fn = (LEGACY_ENTRY_FN_T)thread->entry; ++ fn(0,thread->arg); ++ ret = 0; ++ } ++ else ++ { ++ ret = thread->entry(thread->arg); ++ } ++ ++ thread->exit_data = ret; ++ ++ vcos_remove_thread(current); ++ ++ /* For join and cleanup */ ++ vcos_semaphore_post(&thread->wait); ++ ++ return 0; ++} ++ ++VCOS_STATUS_T vcos_thread_create(VCOS_THREAD_T *thread, ++ const char *name, ++ VCOS_THREAD_ATTR_T *attrs, ++ VCOS_THREAD_ENTRY_FN_T entry, ++ void *arg) ++{ ++ VCOS_STATUS_T st; ++ struct task_struct *kthread; ++ ++ memset(thread, 0, sizeof(*thread)); ++ thread->magic = VCOS_THREAD_MAGIC; ++ strlcpy( thread->name, name, sizeof( thread->name )); ++ thread->legacy = attrs ? attrs->legacy : 0; ++ thread->entry = entry; ++ thread->arg = arg; ++ ++ if (!name) ++ { ++ vcos_assert(0); ++ return VCOS_EINVAL; ++ } ++ ++ st = vcos_semaphore_create(&thread->wait, NULL, 0); ++ if (st != VCOS_SUCCESS) ++ { ++ return st; ++ } ++ ++ st = vcos_semaphore_create(&thread->suspend, NULL, 0); ++ if (st != VCOS_SUCCESS) ++ { ++ return st; ++ } ++ ++ /*required for event groups */ ++ vcos_timer_create(&thread->_timer.timer, thread->name, NULL, NULL); ++ ++ kthread = kthread_create((int (*)(void *))vcos_thread_wrapper, (void*)thread, name); ++ vcos_assert(kthread != NULL); ++ set_user_nice(kthread, attrs->ta_priority); ++ thread->thread.thread = kthread; ++ wake_up_process(kthread); ++ return VCOS_SUCCESS; ++} ++ ++void vcos_thread_join(VCOS_THREAD_T *thread, ++ void **pData) ++{ ++ vcos_assert(thread); ++ vcos_assert(thread->magic == VCOS_THREAD_MAGIC); ++ ++ thread->joined = 1; ++ ++ vcos_semaphore_wait(&thread->wait); ++ ++ if (pData) ++ { ++ *pData = thread->exit_data; ++ } ++ ++ /* Clean up */ ++ if (thread->stack) ++ vcos_free(thread->stack); ++ ++ vcos_semaphore_delete(&thread->wait); ++ vcos_semaphore_delete(&thread->suspend); ++ ++} ++ ++uint32_t vcos_getmicrosecs( void ) ++{ ++ struct timeval tv; ++/*XXX FIX ME! switch to ktime_get_ts to use MONOTONIC clock */ ++ do_gettimeofday(&tv); ++ return (tv.tv_sec*1000000) + tv.tv_usec; ++} ++ ++VCOS_STATUS_T vcos_timer_init(void) ++{ ++ return VCOS_SUCCESS; ++} ++ ++static const char *log_prefix[] = ++{ ++ "", /* VCOS_LOG_UNINITIALIZED */ ++ "", /* VCOS_LOG_NEVER */ ++ KERN_ERR, /* VCOS_LOG_ERROR */ ++ KERN_WARNING, /* VCOS_LOG_WARN */ ++ KERN_INFO, /* VCOS_LOG_INFO */ ++ KERN_INFO /* VCOS_LOG_TRACE */ ++}; ++ ++void vcos_vlog_default_impl(const VCOS_LOG_CAT_T *cat, VCOS_LOG_LEVEL_T _level, const char *fmt, va_list args) ++{ ++ char *newline = strchr( fmt, '\n' ); ++ const char *prefix; ++ const char *real_fmt; ++ ++ preempt_disable(); ++ { ++ if ( *fmt == '<' ) ++ { ++ prefix = fmt; ++ real_fmt= &fmt[3]; ++ } ++ else ++ { ++ prefix = log_prefix[_level]; ++ real_fmt = fmt; ++ } ++#if defined( CONFIG_BCM_KNLLOG_SUPPORT ) ++ knllog_ventry( "vcos", real_fmt, args ); ++#endif ++ printk( "%.3svcos: [%d]: ", prefix, current->pid ); ++ vprintk( real_fmt, args ); ++ ++ if ( newline == NULL ) ++ { ++ printk("\n"); ++ } ++ } ++ preempt_enable(); ++} ++ ++ ++const char * _vcos_log_level(void) ++{ ++ return NULL; ++} ++ ++/***************************************************************************** ++* ++* Displays the version information in /proc/vcos/version ++* ++*****************************************************************************/ ++ ++#ifdef HAVE_VCOS_VERSION ++ ++static void show_version( VCOS_CFG_BUF_T buf, void *data ) ++{ ++ static const char* copyright = "Copyright (c) 2011 Broadcom"; ++ ++ vcos_cfg_buf_printf( buf, "Built %s %s on %s\n%s\nversion %s\n", ++ vcos_get_build_date(), ++ vcos_get_build_time(), ++ vcos_get_build_hostname(), ++ copyright, ++ vcos_get_build_version() ); ++} ++ ++#endif ++ ++/***************************************************************************** ++* ++* Initialises vcos ++* ++*****************************************************************************/ ++ ++VCOS_STATUS_T vcos_init(void) ++{ ++ if ( vcos_cfg_mkdir( &vcos_cfg_dir, NULL, "vcos" ) != VCOS_SUCCESS ) ++ { ++ printk( KERN_ERR "%s: Unable to create vcos cfg entry\n", __func__ ); ++ } ++ vcos_logging_init(); ++ ++#ifdef HAVE_VCOS_VERSION ++ if ( vcos_cfg_create_entry( &vcos_version_cfg, &vcos_cfg_dir, "version", ++ show_version, NULL, NULL ) != VCOS_SUCCESS ) ++ { ++ printk( KERN_ERR "%s: Unable to create vcos cfg entry 'version'\n", __func__ ); ++ } ++#endif ++ ++ return VCOS_SUCCESS; ++} ++ ++/***************************************************************************** ++* ++* Deinitializes vcos ++* ++*****************************************************************************/ ++ ++void vcos_deinit(void) ++{ ++#ifdef HAVE_VCOS_VERSION ++ vcos_cfg_remove_entry( &vcos_version_cfg ); ++#endif ++ vcos_cfg_remove_entry( &vcos_cfg_dir ); ++} ++ ++void vcos_global_lock(void) ++{ ++ down(&lock); ++} ++ ++void vcos_global_unlock(void) ++{ ++ up(&lock); ++} ++ ++/* vcos_thread_exit() doesn't really stop this thread here ++ * ++ * At the moment, call to do_exit() will leak task_struct for ++ * current thread, so we let the vcos_thread_wrapper() do the ++ * cleanup and exit job, and we return w/o actually stopping the thread. ++ * ++ * ToDo: Kernel v2.6.31 onwards, it is considered safe to call do_exit() ++ * from kthread, the implementation of which is combined in 2 patches ++ * with commit-ids "63706172" and "cdd140bd" in oss Linux kernel tree ++ */ ++ ++void vcos_thread_exit(void *arg) ++{ ++ VCOS_THREAD_T *thread = vcos_thread_current(); ++ ++ vcos_assert(thread); ++ vcos_assert(thread->magic == VCOS_THREAD_MAGIC); ++ ++ thread->exit_data = arg; ++} ++ ++void vcos_thread_attr_init(VCOS_THREAD_ATTR_T *attrs) ++{ ++ *attrs = default_attrs; ++} ++ ++void _vcos_task_timer_set(void (*pfn)(void *), void *cxt, VCOS_UNSIGNED ms) ++{ ++ VCOS_THREAD_T *self = vcos_thread_current(); ++ vcos_assert(self); ++ vcos_assert(self->_timer.pfn == NULL); ++ ++ vcos_timer_create( &self->_timer.timer, "TaskTimer", pfn, cxt ); ++ vcos_timer_set(&self->_timer.timer, ms); ++} ++ ++void _vcos_task_timer_cancel(void) ++{ ++ VCOS_THREAD_T *self = vcos_thread_current(); ++ if (self->_timer.timer.linux_timer.function) ++ { ++ vcos_timer_cancel(&self->_timer.timer); ++ vcos_timer_delete(&self->_timer.timer); ++ } ++} ++ ++int vcos_vsnprintf( char *buf, size_t buflen, const char *fmt, va_list ap ) ++{ ++ return vsnprintf( buf, buflen, fmt, ap ); ++} ++ ++int vcos_snprintf(char *buf, size_t buflen, const char *fmt, ...) ++{ ++ int ret; ++ va_list ap; ++ va_start(ap,fmt); ++ ret = vsnprintf(buf, buflen, fmt, ap); ++ va_end(ap); ++ return ret; ++} ++ ++int vcos_llthread_running(VCOS_LLTHREAD_T *t) { ++ vcos_assert(0); /* this function only exists as a nasty hack for the video codecs! */ ++ return 1; ++} ++ ++static int vcos_verify_bkpts = 1; ++ ++int vcos_verify_bkpts_enabled(void) ++{ ++ return vcos_verify_bkpts; ++} ++ ++/***************************************************************************** ++* ++* _vcos_log_platform_init is called from vcos_logging_init ++* ++*****************************************************************************/ ++ ++void _vcos_log_platform_init(void) ++{ ++ if ( vcos_cfg_mkdir( &vcos_logging_cfg_dir, &vcos_cfg_dir, "logging" ) != VCOS_SUCCESS ) ++ { ++ printk( KERN_ERR "%s: Unable to create logging cfg entry\n", __func__ ); ++ } ++} ++ ++/***************************************************************************** ++* ++* Called to display the contents of a logging category. ++* ++*****************************************************************************/ ++ ++static void logging_show_category( VCOS_CFG_BUF_T buf, void *data ) ++{ ++ VCOS_LOG_CAT_T *category = data; ++ ++ vcos_cfg_buf_printf( buf, "%s\n", vcos_log_level_to_string( category->level )); ++} ++ ++/***************************************************************************** ++* ++* Called to parse content for a logging category. ++* ++*****************************************************************************/ ++ ++static void logging_parse_category( VCOS_CFG_BUF_T buf, void *data ) ++{ ++ VCOS_LOG_CAT_T *category = data; ++ const char *str = vcos_cfg_buf_get_str( buf ); ++ VCOS_LOG_LEVEL_T level; ++ ++ if ( vcos_string_to_log_level( str, &level ) == VCOS_SUCCESS ) ++ { ++ category->level = level; ++ } ++ else ++ { ++ printk( KERN_ERR "%s: Unrecognized logging level: '%s'\n", ++ __func__, str ); ++ } ++} ++ ++/***************************************************************************** ++* ++* _vcos_log_platform_register is called from vcos_log_register whenever ++* a new category is registered. ++* ++*****************************************************************************/ ++ ++void _vcos_log_platform_register(VCOS_LOG_CAT_T *category) ++{ ++ VCOS_CFG_ENTRY_T entry; ++ ++ if ( vcos_cfg_create_entry( &entry, &vcos_logging_cfg_dir, category->name, ++ logging_show_category, logging_parse_category, ++ category ) != VCOS_SUCCESS ) ++ { ++ printk( KERN_ERR "%s: Unable to create cfg entry for logging category '%s'\n", ++ __func__, category->name ); ++ category->platform_data = NULL; ++ } ++ else ++ { ++ category->platform_data = entry; ++ } ++} ++ ++/***************************************************************************** ++* ++* _vcos_log_platform_unregister is called from vcos_log_unregister whenever ++* a new category is unregistered. ++* ++*****************************************************************************/ ++ ++void _vcos_log_platform_unregister(VCOS_LOG_CAT_T *category) ++{ ++ VCOS_CFG_ENTRY_T entry; ++ ++ entry = category->platform_data; ++ if ( entry != NULL ) ++ { ++ if ( vcos_cfg_remove_entry( &entry ) != VCOS_SUCCESS ) ++ { ++ printk( KERN_ERR "%s: Unable to remove cfg entry for logging category '%s'\n", ++ __func__, category->name ); ++ } ++ } ++} ++ ++/***************************************************************************** ++* ++* Allocate memory. ++* ++*****************************************************************************/ ++ ++void *vcos_platform_malloc( VCOS_UNSIGNED required_size ) ++{ ++ if ( required_size >= ( 2 * PAGE_SIZE )) ++ { ++ /* For larger allocations, use vmalloc, whose underlying allocator ++ * returns pages ++ */ ++ ++ return vmalloc( required_size ); ++ } ++ ++ /* For smaller allocation, use kmalloc */ ++ ++ return kmalloc( required_size, GFP_KERNEL ); ++} ++ ++/***************************************************************************** ++* ++* Free previously allocated memory ++* ++*****************************************************************************/ ++ ++void vcos_platform_free( void *ptr ) ++{ ++ if (((unsigned long)ptr >= VMALLOC_START ) ++ && ((unsigned long)ptr < VMALLOC_END )) ++ { ++ vfree( ptr ); ++ } ++ else ++ { ++ kfree( ptr ); ++ } ++} ++ ++/***************************************************************************** ++* ++* Execute a routine exactly once. ++* ++*****************************************************************************/ ++ ++VCOS_STATUS_T vcos_once(VCOS_ONCE_T *once_control, ++ void (*init_routine)(void)) ++{ ++ /* In order to be thread-safe we need to re-test *once_control ++ * inside the lock. The outer test is basically an optimization ++ * so that once it is initialized we don't need to waste time ++ * trying to acquire the lock. ++ */ ++ ++ if ( *once_control == 0 ) ++ { ++ vcos_global_lock(); ++ if ( *once_control == 0 ) ++ { ++ init_routine(); ++ *once_control = 1; ++ } ++ vcos_global_unlock(); ++ } ++ ++ return VCOS_SUCCESS; ++} ++ ++/***************************************************************************** ++* ++* String duplication routine. ++* ++*****************************************************************************/ ++ ++char *vcos_strdup(const char *str) ++{ ++ return kstrdup(str, GFP_KERNEL); ++} ++ ++ ++/* Export functions for modules to use */ ++EXPORT_SYMBOL( vcos_init ); ++ ++EXPORT_SYMBOL( vcos_semaphore_trywait ); ++EXPORT_SYMBOL( vcos_semaphore_post ); ++EXPORT_SYMBOL( vcos_semaphore_create ); ++EXPORT_SYMBOL( vcos_semaphore_wait ); ++EXPORT_SYMBOL( vcos_semaphore_delete ); ++ ++EXPORT_SYMBOL( vcos_log_impl ); ++EXPORT_SYMBOL( vcos_vlog_impl ); ++EXPORT_SYMBOL( vcos_vlog_default_impl ); ++EXPORT_SYMBOL( vcos_log_get_default_category ); ++EXPORT_SYMBOL( vcos_log_register ); ++EXPORT_SYMBOL( vcos_log_unregister ); ++EXPORT_SYMBOL( vcos_logging_init ); ++EXPORT_SYMBOL( vcos_log_level_to_string ); ++EXPORT_SYMBOL( vcos_string_to_log_level ); ++EXPORT_SYMBOL( vcos_log_dump_mem_impl ); ++ ++EXPORT_SYMBOL( vcos_event_create ); ++EXPORT_SYMBOL( vcos_event_delete ); ++EXPORT_SYMBOL( vcos_event_flags_set ); ++EXPORT_SYMBOL( vcos_event_signal ); ++EXPORT_SYMBOL( vcos_event_wait ); ++EXPORT_SYMBOL( vcos_event_try ); ++ ++EXPORT_SYMBOL( vcos_getmicrosecs ); ++ ++EXPORT_SYMBOL( vcos_strcasecmp ); ++EXPORT_SYMBOL( vcos_snprintf ); ++EXPORT_SYMBOL( vcos_vsnprintf ); ++ ++EXPORT_SYMBOL( vcos_thread_current ); ++EXPORT_SYMBOL( vcos_thread_join ); ++EXPORT_SYMBOL( vcos_thread_create ); ++EXPORT_SYMBOL( vcos_thread_set_priority ); ++EXPORT_SYMBOL( vcos_thread_exit ); ++EXPORT_SYMBOL( vcos_once ); ++ ++EXPORT_SYMBOL( vcos_thread_attr_init ); ++EXPORT_SYMBOL( vcos_thread_attr_setpriority ); ++EXPORT_SYMBOL( vcos_thread_attr_settimeslice ); ++EXPORT_SYMBOL( vcos_thread_attr_setstacksize ); ++EXPORT_SYMBOL( _vcos_thread_attr_setlegacyapi ); ++ ++EXPORT_SYMBOL( vcos_event_flags_create ); ++EXPORT_SYMBOL( vcos_event_flags_delete ); ++EXPORT_SYMBOL( vcos_event_flags_get ); ++ ++EXPORT_SYMBOL( vcos_sleep ); ++ ++EXPORT_SYMBOL( vcos_calloc ); ++EXPORT_SYMBOL( vcos_malloc ); ++EXPORT_SYMBOL( vcos_malloc_aligned ); ++EXPORT_SYMBOL( vcos_free ); ++ ++EXPORT_SYMBOL( vcos_mutex_create ); ++EXPORT_SYMBOL( vcos_mutex_delete ); ++EXPORT_SYMBOL( vcos_mutex_lock ); ++EXPORT_SYMBOL( vcos_mutex_unlock ); ++EXPORT_SYMBOL( vcos_mutex_trylock ); ++ ++EXPORT_SYMBOL( vcos_timer_cancel ); ++EXPORT_SYMBOL( vcos_timer_create ); ++EXPORT_SYMBOL( vcos_timer_delete ); ++EXPORT_SYMBOL( vcos_timer_set ); ++ ++EXPORT_SYMBOL( vcos_atomic_flags_create ); ++EXPORT_SYMBOL( vcos_atomic_flags_delete ); ++EXPORT_SYMBOL( vcos_atomic_flags_or ); ++EXPORT_SYMBOL( vcos_atomic_flags_get_and_clear ); ++ ++EXPORT_SYMBOL( vcos_verify_bkpts_enabled ); ++ ++EXPORT_SYMBOL( vcos_strdup ); +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/linuxkernel/vcos_linuxkernel_cfg.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/linuxkernel/vcos_linuxkernel_cfg.c 2013-07-26 19:32:00.000000000 +0000 +@@ -0,0 +1,332 @@ ++/***************************************************************************** ++* Copyright 2009 - 2010 Broadcom Corporation. All rights reserved. ++* ++* Unless you and Broadcom execute a separate written software license ++* agreement governing use of this software, this software is licensed to you ++* under the terms of the GNU General Public License version 2, available at ++* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). ++* ++* Notwithstanding the above, under no circumstances may you combine this ++* software in any way with any other Broadcom software provided under a ++* license other than the GPL, without Broadcom's express prior written ++* consent. ++*****************************************************************************/ ++ ++#include "interface/vcos/vcos.h" ++#include ++#include ++#include ++#include ++ ++struct opaque_vcos_cfg_buf_t ++{ ++ struct seq_file *seq; ++ char *charBuf; ++}; ++ ++struct opaque_vcos_cfg_entry_t ++{ ++ struct proc_dir_entry *pde; ++ struct proc_dir_entry *parent_pde; ++ VCOS_CFG_SHOW_FPTR showFunc; ++ VCOS_CFG_PARSE_FPTR parseFunc; ++ void *data; ++ const char *name; ++}; ++ ++/***************************************************************************** ++* ++* cfg_proc_show ++* ++*****************************************************************************/ ++ ++static int cfg_proc_show( struct seq_file *s, void *v ) ++{ ++ VCOS_CFG_ENTRY_T entry; ++ struct opaque_vcos_cfg_buf_t buf; ++ ++ entry = s->private; ++ ++ if ( entry->showFunc ) ++ { ++ memset( &buf, 0, sizeof( buf )); ++ buf.seq = s; ++ ++ entry->showFunc( &buf, entry->data ); ++ } ++ ++ return 0; ++} ++ ++/***************************************************************************** ++* ++* cfg_proc_write ++* ++*****************************************************************************/ ++ ++static ssize_t cfg_proc_write( struct file *file, const char __user *buffer, size_t count, loff_t *ppos) ++{ ++ VCOS_CFG_ENTRY_T entry = PDE(file->f_path.dentry->d_inode)->data; ++ char *charBuf; ++ struct opaque_vcos_cfg_buf_t buf; ++ size_t len; ++ ++ if ( entry->parseFunc != NULL ) ++ { ++ /* The number 4000 is rather arbitrary. It just needs to be bigger than any input ++ * string we expect to use. ++ */ ++ ++ len = count; ++ if ( count > 4000 ) ++ { ++ len = 4000; ++ } ++ ++ /* Allocate a kernel buffer to contain the string being written. */ ++ ++ charBuf = kmalloc( len + 1, GFP_KERNEL ); ++ if ( copy_from_user( charBuf, buffer, len )) ++ { ++ kfree( charBuf ); ++ return -EFAULT; ++ } ++ ++ /* echo puts a trailing newline in the buffer - strip it out. */ ++ ++ if (( len > 0 ) && ( charBuf[ len - 1 ] == '\n' )) ++ { ++ len--; ++ } ++ charBuf[len] = '\0'; ++ ++ memset( &buf, 0, sizeof( buf )); ++ buf.charBuf = charBuf; ++ ++ entry->parseFunc( &buf, entry->data ); ++ kfree( charBuf ); ++ } ++ return count; ++} ++ ++/***************************************************************************** ++* ++* cfg_proc_open ++* ++*****************************************************************************/ ++ ++static int cfg_proc_open( struct inode *inode, struct file *file ) ++{ ++ return single_open( file, cfg_proc_show, PDE(inode)->data ); ++} ++ ++static const struct file_operations cfg_proc_fops = ++{ ++ .open = cfg_proc_open, ++ .read = seq_read, ++ .llseek = seq_lseek, ++ .release = single_release, ++ .write = cfg_proc_write, ++}; ++ ++/***************************************************************************** ++* ++* vcos_cfg_mkdir ++* ++*****************************************************************************/ ++ ++VCOS_STATUS_T vcos_cfg_mkdir( VCOS_CFG_ENTRY_T *entryp, ++ VCOS_CFG_ENTRY_T *parent, ++ const char *dirName ) ++{ ++ VCOS_CFG_ENTRY_T entry; ++ ++ if (( entry = kzalloc( sizeof( *entry ), GFP_KERNEL )) == NULL ) ++ { ++ return VCOS_ENOMEM; ++ } ++ ++ if ( parent == NULL ) ++ { ++ entry->pde = proc_mkdir( dirName, NULL ); ++ } ++ else ++ { ++ entry->pde = proc_mkdir( dirName, (*parent)->pde ); ++ entry->parent_pde = (*parent)->pde; ++ } ++ if ( entry->pde == NULL ) ++ { ++ kfree( entry ); ++ return VCOS_ENOMEM; ++ } ++ ++ entry->name = dirName; ++ ++ *entryp = entry; ++ return VCOS_SUCCESS; ++} ++ ++/***************************************************************************** ++* ++* vcos_cfg_create_entry ++* ++*****************************************************************************/ ++ ++VCOS_STATUS_T vcos_cfg_create_entry( VCOS_CFG_ENTRY_T *entryp, ++ VCOS_CFG_ENTRY_T *parent, ++ const char *entryName, ++ VCOS_CFG_SHOW_FPTR showFunc, ++ VCOS_CFG_PARSE_FPTR parseFunc, ++ void *data ) ++{ ++ VCOS_CFG_ENTRY_T entry; ++ mode_t mode; ++ ++ *entryp = NULL; ++ ++ if (( entry = kzalloc( sizeof( *entry ), GFP_KERNEL )) == NULL ) ++ { ++ return VCOS_ENOMEM; ++ } ++ ++ mode = 0; ++ if ( showFunc != NULL ) ++ { ++ mode |= 0444; ++ } ++ if ( parseFunc != NULL ) ++ { ++ mode |= 0200; ++ } ++ ++ if ( parent == NULL ) ++ { ++ entry->pde = create_proc_entry( entryName, mode, NULL ); ++ } ++ else ++ { ++ entry->pde = create_proc_entry( entryName, mode, (*parent)->pde ); ++ entry->parent_pde = (*parent)->pde; ++ } ++ if ( entry->pde == NULL ) ++ { ++ kfree( entry ); ++ return -ENOMEM; ++ } ++ entry->showFunc = showFunc; ++ entry->parseFunc = parseFunc; ++ entry->data = data; ++ entry->name = entryName; ++ ++ entry->pde->data = entry; ++ entry->pde->proc_fops = &cfg_proc_fops; ++ ++ *entryp = entry; ++ return VCOS_SUCCESS; ++} ++ ++/***************************************************************************** ++* ++* vcos_cfg_remove_entry ++* ++*****************************************************************************/ ++ ++VCOS_STATUS_T vcos_cfg_remove_entry( VCOS_CFG_ENTRY_T *entryp ) ++{ ++ if (( entryp != NULL ) && ( *entryp != NULL )) ++ { ++ remove_proc_entry( (*entryp)->name, (*entryp)->parent_pde ); ++ ++ kfree( *entryp ); ++ *entryp = NULL; ++ } ++ ++ return VCOS_SUCCESS; ++} ++ ++/***************************************************************************** ++* ++* vcos_cfg_is_entry_created ++* ++*****************************************************************************/ ++ ++int vcos_cfg_is_entry_created( VCOS_CFG_ENTRY_T entry ) ++{ ++ return ( entry != NULL ) && ( entry->pde != NULL ); ++} ++ ++/***************************************************************************** ++* ++* vcos_cfg_buf_printf ++* ++*****************************************************************************/ ++ ++void vcos_cfg_buf_printf( VCOS_CFG_BUF_T buf, const char *fmt, ... ) ++{ ++ struct seq_file *m = buf->seq; ++ ++ /* Bah - there is no seq_vprintf */ ++ ++ va_list args; ++ int len; ++ ++ if (m->count < m->size) { ++ va_start(args, fmt); ++ len = vsnprintf(m->buf + m->count, m->size - m->count, fmt, args); ++ va_end(args); ++ if (m->count + len < m->size) { ++ m->count += len; ++ return; ++ } ++ } ++ m->count = m->size; ++} ++ ++/***************************************************************************** ++* ++* vcos_cfg_buf_get_str ++* ++*****************************************************************************/ ++ ++char *vcos_cfg_buf_get_str( VCOS_CFG_BUF_T buf ) ++{ ++ return buf->charBuf; ++} ++ ++/***************************************************************************** ++* ++* vcos_cfg_get_proc_entry ++* ++* This function is only created for a couple of backwards compatibility ' ++* issues and shouldn't normally be used. ++* ++*****************************************************************************/ ++ ++void *vcos_cfg_get_proc_entry( VCOS_CFG_ENTRY_T entry ) ++{ ++ return entry->pde; ++} ++ ++/***************************************************************************** ++* ++* vcos_cfg_get_entry_name ++* ++*****************************************************************************/ ++ ++const char *vcos_cfg_get_entry_name( VCOS_CFG_ENTRY_T entry ) ++{ ++ return entry->pde->name; ++} ++ ++ ++EXPORT_SYMBOL( vcos_cfg_mkdir ); ++EXPORT_SYMBOL( vcos_cfg_create_entry ); ++EXPORT_SYMBOL( vcos_cfg_remove_entry ); ++EXPORT_SYMBOL( vcos_cfg_get_entry_name ); ++EXPORT_SYMBOL( vcos_cfg_is_entry_created ); ++EXPORT_SYMBOL( vcos_cfg_buf_printf ); ++EXPORT_SYMBOL( vcos_cfg_buf_get_str ); ++ ++EXPORT_SYMBOL_GPL( vcos_cfg_get_proc_entry ); ++ +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/linuxkernel/vcos_linuxkernel_misc.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/linuxkernel/vcos_linuxkernel_misc.c 2013-07-26 19:32:00.000000000 +0000 +@@ -0,0 +1,113 @@ ++// ############################################################################# ++// START ####################################################################### ++/***************************************************************************** ++* Copyright 2009 - 2010 Broadcom Corporation. All rights reserved. ++* ++* Unless you and Broadcom execute a separate written software license ++* agreement governing use of this software, this software is licensed to you ++* under the terms of the GNU General Public License version 2, available at ++* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). ++* ++* Notwithstanding the above, under no circumstances may you combine this ++* software in any way with any other Broadcom software provided under a ++* license other than the GPL, without Broadcom's express prior written ++* consent. ++*****************************************************************************/ ++ ++#include "interface/vcos/vcos.h" ++#include ++#include ++#include ++#include ++#include ++ ++/***************************************************************************** ++* ++* vcos_semaphore_wait_freezable ++* ++*****************************************************************************/ ++ ++VCOS_STATUS_T vcos_semaphore_wait_freezable(VCOS_SEMAPHORE_T *sem) ++{ ++ int rval, sig_pended = 0; ++ unsigned long flags; ++ struct task_struct *task = current; ++ ++ while (1) { ++ rval = down_interruptible((struct semaphore *)sem); ++ if (rval == 0) { /* down now */ ++ break; ++ } else { ++ if (freezing(current)) { ++ try_to_freeze(); ++ } else { ++ spin_lock_irqsave(&task->sighand->siglock, flags); ++ if (test_tsk_thread_flag(task, TIF_SIGPENDING)) { ++ clear_tsk_thread_flag(task, TIF_SIGPENDING); ++ sig_pended = 1; ++ } ++ spin_unlock_irqrestore(&task->sighand->siglock, flags); ++ } ++ } ++ } ++ ++ if (sig_pended) { ++ spin_lock_irqsave(&task->sighand->siglock, flags); ++ set_tsk_thread_flag(task, TIF_SIGPENDING); ++ spin_unlock_irqrestore(&task->sighand->siglock, flags); ++ } ++ ++ return 0; ++} ++ ++EXPORT_SYMBOL( vcos_semaphore_wait_freezable ); ++ ++/***************************************************************************** ++* ++* vcos_kmalloc ++* ++* We really need to convert malloc to do kmalloc or vmalloc based on the ++* size, but for now we'll add a separate function. ++* ++*****************************************************************************/ ++ ++void *vcos_kmalloc(VCOS_UNSIGNED size, const char *description) ++{ ++ (void)description; ++ ++ return kmalloc( size, GFP_KERNEL ); ++} ++ ++/***************************************************************************** ++* ++* vcos_kmalloc ++* ++* We really need to convert malloc to do kmalloc or vmalloc based on the ++* size, but for now we'll add a separate function. ++* ++*****************************************************************************/ ++ ++void *vcos_kcalloc(VCOS_UNSIGNED num, VCOS_UNSIGNED size, const char *description) ++{ ++ (void)description; ++ ++ return kzalloc( num * size, GFP_KERNEL ); ++} ++ ++/***************************************************************************** ++* ++* vcos_kfree ++* ++*****************************************************************************/ ++ ++void vcos_kfree(void *ptr) ++{ ++ kfree( ptr ); ++} ++ ++EXPORT_SYMBOL( vcos_kmalloc ); ++EXPORT_SYMBOL( vcos_kcalloc ); ++EXPORT_SYMBOL( vcos_kfree ); ++ ++// END ######################################################################### ++// ############################################################################# +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/linuxkernel/vcos_mod_init.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/linuxkernel/vcos_mod_init.c 2013-07-26 19:32:00.000000000 +0000 +@@ -0,0 +1,64 @@ ++/***************************************************************************** ++* Copyright 2006 - 2008 Broadcom Corporation. All rights reserved. ++* ++* Unless you and Broadcom execute a separate written software license ++* agreement governing use of this software, this software is licensed to you ++* under the terms of the GNU General Public License version 2, available at ++* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). ++* ++* Notwithstanding the above, under no circumstances may you combine this ++* software in any way with any other Broadcom software provided under a ++* license other than the GPL, without Broadcom's express prior written ++* consent. ++****************************************************************************/ ++ ++/* ---- Include Files ---------------------------------------------------- */ ++ ++#include "interface/vcos/vcos.h" ++#include ++ ++/* ---- Public Variables ------------------------------------------------- */ ++ ++/* ---- Private Constants and Types -------------------------------------- */ ++ ++/* ---- Private Variables ------------------------------------------------ */ ++ ++/* ---- Private Function Prototypes -------------------------------------- */ ++ ++/* ---- Functions -------------------------------------------------------- */ ++ ++/**************************************************************************** ++* ++* Called to perform module initialization when the module is loaded ++* ++***************************************************************************/ ++ ++static int __init vcos_mod_init( void ) ++{ ++ printk( KERN_INFO "VCOS Module\n" ); ++ ++ vcos_init(); ++ return 0; ++} ++ ++/**************************************************************************** ++* ++* Called to perform module cleanup when the module is unloaded. ++* ++***************************************************************************/ ++ ++static void __exit vcos_mod_exit( void ) ++{ ++ vcos_deinit(); ++} ++ ++/****************************************************************************/ ++ ++module_init( vcos_mod_init ); ++module_exit( vcos_mod_exit ); ++ ++MODULE_AUTHOR("Broadcom"); ++MODULE_DESCRIPTION( "VCOS Module Functions" ); ++MODULE_LICENSE( "GPL" ); ++MODULE_VERSION( "1.0" ); ++ +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/linuxkernel/vcos_platform.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/linuxkernel/vcos_platform.h 2013-07-26 19:32:00.000000000 +0000 +@@ -0,0 +1,496 @@ ++/*============================================================================= ++Copyright (c) 2009 Broadcom Europe Limited. ++All rights reserved. ++ ++Project : vcfw ++Module : vcos ++ ++FILE DESCRIPTION ++VideoCore OS Abstraction Layer - Linux kernel (partial) implementation. ++=============================================================================*/ ++ ++/* Do not include this file directly - instead include it via vcos.h */ ++ ++/** @file ++ * ++ * Linux kernel (partial) implementation of VCOS. ++ * ++ */ ++ ++#ifndef VCOS_PLATFORM_H ++#define VCOS_PLATFORM_H ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include /* for time_t */ ++#include ++#include ++ ++#define VCOS_HAVE_RTOS 1 ++#define VCOS_HAVE_SEMAPHORE 1 ++#define VCOS_HAVE_EVENT 1 ++#define VCOS_HAVE_QUEUE 0 ++#define VCOS_HAVE_LEGACY_ISR 0 ++#define VCOS_HAVE_TIMER 1 ++#define VCOS_HAVE_CANCELLATION_SAFE_TIMER 0 ++#define VCOS_HAVE_MEMPOOL 0 ++#define VCOS_HAVE_ISR 0 ++#define VCOS_HAVE_ATOMIC_FLAGS 1 ++#define VCOS_HAVE_BLOCK_POOL 0 ++#define VCOS_HAVE_ONCE 1 ++#define VCOS_HAVE_FILE 0 ++#define VCOS_HAVE_USER_BUF 0 ++#define VCOS_HAVE_CFG 1 ++#define VCOS_HAVE_SPINLOCK 0 ++#define VCOS_HAVE_CMD 1 ++#define VCOS_HAVE_EVENT_FLAGS 1 ++ ++/* Exclude many VCOS classes which don't have predicates */ ++#define VCOS_TLS_H ++#define VCOS_NAMED_MUTEX_H ++#define VCOS_REENTRANT_MUTEX_H ++#define VCOS_NAMED_SEMAPHORE_H ++#define VCOS_QUICKSLOW_MUTEX_H ++/*#define VCOS_INIT_H */ ++/*#define VCOS_MEM_H */ ++/*#define VCOS_STRING_H */ ++ ++typedef struct semaphore VCOS_SEMAPHORE_T; ++typedef struct semaphore VCOS_EVENT_T; ++typedef struct mutex VCOS_MUTEX_T; ++typedef volatile int VCOS_ONCE_T; ++ ++typedef unsigned int VCOS_UNSIGNED; ++typedef unsigned int VCOS_OPTION; ++typedef atomic_t VCOS_ATOMIC_FLAGS_T; ++ ++typedef struct ++{ ++ struct timer_list linux_timer; ++ void *context; ++ void (*expiration_routine)(void *context); ++ ++} VCOS_TIMER_T; ++ ++typedef struct VCOS_LLTHREAD_T ++{ ++ struct task_struct *thread; /**< The thread itself */ ++ VCOS_SEMAPHORE_T suspend; /**< For support event groups and similar - a per thread semaphore */ ++} VCOS_LLTHREAD_T; ++ ++typedef enum ++{ ++ VCOS_O_RDONLY = 00000000, ++ VCOS_O_WRONLY = 00000001, ++ VCOS_O_RDWR = 00000002, ++ VCOS_O_TRUNC = 00001000, ++} VCOS_FILE_FLAGS_T; ++ ++typedef struct file *VCOS_FILE_T; ++ ++#define VCOS_SUSPEND -1 ++#define VCOS_NO_SUSPEND 0 ++ ++#define VCOS_START 1 ++#define VCOS_NO_START 0 ++ ++#define VCOS_THREAD_PRI_MIN -20 ++#define VCOS_THREAD_PRI_MAX 19 ++ ++#define VCOS_THREAD_PRI_INCREASE -1 ++#define VCOS_THREAD_PRI_HIGHEST VCOS_THREAD_PRI_MIN ++#define VCOS_THREAD_PRI_LOWEST VCOS_THREAD_PRI_MAX ++#define VCOS_THREAD_PRI_NORMAL ((VCOS_THREAD_PRI_MAX+VCOS_THREAD_PRI_MIN)/2) ++#define VCOS_THREAD_PRI_ABOVE_NORMAL (VCOS_THREAD_PRI_NORMAL + VCOS_THREAD_PRI_INCREASE) ++#define VCOS_THREAD_PRI_REALTIME VCOS_THREAD_PRI_HIGHEST ++ ++#define _VCOS_AFFINITY_DEFAULT 0 ++#define _VCOS_AFFINITY_CPU0 0 ++#define _VCOS_AFFINITY_CPU1 0 ++#define _VCOS_AFFINITY_MASK 0 ++#define VCOS_CAN_SET_STACK_ADDR 0 ++ ++#define VCOS_TICKS_PER_SECOND HZ ++ ++#include "interface/vcos/generic/vcos_generic_event_flags.h" ++#include "interface/vcos/generic/vcos_mem_from_malloc.h" ++#include "interface/vcos/generic/vcos_joinable_thread_from_plain.h" ++ ++/*********************************************************** ++ * ++ * Memory allcoation ++ * ++ ***********************************************************/ ++ ++#define _vcos_platform_malloc vcos_platform_malloc ++#define _vcos_platform_free vcos_platform_free ++ ++void *vcos_platform_malloc( VCOS_UNSIGNED required_size ); ++void vcos_platform_free( void *ptr ); ++ ++#if defined(VCOS_INLINE_BODIES) ++ ++#undef VCOS_ASSERT_LOGGING_DISABLE ++#define VCOS_ASSERT_LOGGING_DISABLE 1 ++ ++/*********************************************************** ++ * ++ * Counted Semaphores ++ * ++ ***********************************************************/ ++ ++VCOS_INLINE_IMPL ++VCOS_STATUS_T vcos_semaphore_wait(VCOS_SEMAPHORE_T *sem) { ++ int ret = down_interruptible(sem); ++ if ( ret == 0 ) ++ /* Success */ ++ return VCOS_SUCCESS; ++ else if ( ret == -EINTR ) ++ /* Interrupted */ ++ return VCOS_EINTR; ++ else ++ /* Default (timeout) */ ++ return VCOS_EAGAIN; ++} ++ ++VCOS_INLINE_IMPL ++VCOS_STATUS_T vcos_semaphore_trywait(VCOS_SEMAPHORE_T *sem) { ++ if (down_trylock(sem) != 0) ++ return VCOS_EAGAIN; ++ return VCOS_SUCCESS; ++} ++ ++VCOS_INLINE_IMPL ++VCOS_STATUS_T vcos_semaphore_create(VCOS_SEMAPHORE_T *sem, ++ const char *name, ++ VCOS_UNSIGNED initial_count) { ++ sema_init(sem, initial_count); ++ return VCOS_SUCCESS; ++} ++ ++VCOS_INLINE_IMPL ++void vcos_semaphore_delete(VCOS_SEMAPHORE_T *sem) { ++} ++ ++VCOS_INLINE_IMPL ++VCOS_STATUS_T vcos_semaphore_post(VCOS_SEMAPHORE_T *sem) { ++ up(sem); ++ return VCOS_SUCCESS; ++} ++ ++/*********************************************************** ++ * ++ * Threads ++ * ++ ***********************************************************/ ++ ++#include "vcos_thread_map.h" ++ ++VCOS_INLINE_IMPL ++VCOS_LLTHREAD_T *vcos_llthread_current(void) { ++ return &vcos_kthread_current()->thread; ++} ++ ++VCOS_INLINE_IMPL ++void vcos_llthread_resume(VCOS_LLTHREAD_T *thread) { ++ vcos_assert(0); ++} ++ ++VCOS_INLINE_IMPL ++void vcos_sleep(uint32_t ms) { ++ msleep(ms); ++} ++ ++VCOS_INLINE_IMPL ++void vcos_thread_set_priority(VCOS_THREAD_T *thread, VCOS_UNSIGNED p) { ++ /* not implemented */ ++} ++VCOS_INLINE_IMPL ++VCOS_UNSIGNED vcos_thread_get_priority(VCOS_THREAD_T *thread) { ++ /* not implemented */ ++ return 0; ++} ++ ++/*********************************************************** ++ * ++ * Miscellaneous ++ * ++ ***********************************************************/ ++ ++VCOS_INLINE_IMPL ++int vcos_strcasecmp(const char *s1, const char *s2) { ++ return strcasecmp(s1,s2); ++} ++ ++ ++/*********************************************************** ++ * ++ * Mutexes ++ * ++ ***********************************************************/ ++ ++VCOS_INLINE_IMPL ++VCOS_STATUS_T vcos_mutex_create(VCOS_MUTEX_T *m, const char *name) { ++ mutex_init(m); ++ return VCOS_SUCCESS; ++} ++ ++VCOS_INLINE_IMPL ++void vcos_mutex_delete(VCOS_MUTEX_T *m) { ++} ++ ++VCOS_INLINE_IMPL ++VCOS_STATUS_T vcos_mutex_lock(VCOS_MUTEX_T *m) { ++ int ret = mutex_lock_interruptible(m); ++ if ( ret == 0 ) ++ /* Success */ ++ return VCOS_SUCCESS; ++ else if ( ret == -EINTR ) ++ /* Interrupted */ ++ return VCOS_EINTR; ++ else ++ /* Default */ ++ return VCOS_EAGAIN; ++} ++ ++VCOS_INLINE_IMPL ++void vcos_mutex_unlock(VCOS_MUTEX_T *m) { ++ mutex_unlock(m); ++} ++ ++VCOS_INLINE_IMPL ++int vcos_mutex_is_locked(VCOS_MUTEX_T *m) { ++ if (mutex_trylock(m) != 0) ++ return 1; /* it was locked */ ++ mutex_unlock(m); ++ /* it wasn't locked */ ++ return 0; ++} ++ ++VCOS_INLINE_IMPL ++VCOS_STATUS_T vcos_mutex_trylock(VCOS_MUTEX_T *m) { ++ if (mutex_trylock(m) == 0) ++ return VCOS_SUCCESS; ++ else ++ return VCOS_EAGAIN; ++} ++ ++/* For supporting event groups - per thread semaphore */ ++VCOS_INLINE_IMPL ++void _vcos_thread_sem_wait(void) { ++ VCOS_THREAD_T *t = vcos_thread_current(); ++ vcos_semaphore_wait(&t->suspend); ++} ++ ++VCOS_INLINE_IMPL ++void _vcos_thread_sem_post(VCOS_THREAD_T *target) { ++ vcos_semaphore_post(&target->suspend); ++} ++ ++/*********************************************************** ++ * ++ * Events ++ * ++ ***********************************************************/ ++ ++VCOS_INLINE_IMPL ++VCOS_STATUS_T vcos_event_create(VCOS_EVENT_T *event, const char *debug_name) ++{ ++ sema_init(event, 0); ++ return VCOS_SUCCESS; ++} ++ ++VCOS_INLINE_IMPL ++void vcos_event_signal(VCOS_EVENT_T *event) ++{ ++ up(event); ++} ++ ++VCOS_INLINE_IMPL ++VCOS_STATUS_T vcos_event_wait(VCOS_EVENT_T *event) ++{ ++ int ret = down_interruptible(event); ++ if ( ret == -EINTR ) ++ /* Interrupted */ ++ return VCOS_EINTR; ++ else if (ret != 0) ++ /* Default (timeout) */ ++ return VCOS_EAGAIN; ++ /* Emulate a maximum count of 1 by removing any extra upness */ ++ while (down_trylock(event) == 0) continue; ++ return VCOS_SUCCESS; ++} ++ ++VCOS_INLINE_DECL ++VCOS_STATUS_T vcos_event_try(VCOS_EVENT_T *event) ++{ ++ return (down_trylock(event) == 0) ? VCOS_SUCCESS : VCOS_EAGAIN; ++} ++ ++VCOS_INLINE_IMPL ++void vcos_event_delete(VCOS_EVENT_T *event) ++{ ++} ++ ++/*********************************************************** ++ * ++ * Timers ++ * ++ ***********************************************************/ ++ ++VCOS_INLINE_DECL ++void vcos_timer_linux_func(unsigned long data) ++{ ++ VCOS_TIMER_T *vcos_timer = (VCOS_TIMER_T *)data; ++ ++ vcos_timer->expiration_routine( vcos_timer->context ); ++} ++ ++VCOS_INLINE_DECL ++VCOS_STATUS_T vcos_timer_create(VCOS_TIMER_T *timer, ++ const char *name, ++ void (*expiration_routine)(void *context), ++ void *context) { ++ init_timer(&timer->linux_timer); ++ timer->linux_timer.data = (unsigned long)timer; ++ timer->linux_timer.function = vcos_timer_linux_func; ++ ++ timer->context = context; ++ timer->expiration_routine = expiration_routine; ++ ++ return VCOS_SUCCESS; ++} ++ ++VCOS_INLINE_IMPL ++void vcos_timer_set(VCOS_TIMER_T *timer, VCOS_UNSIGNED delay_ms) { ++ timer->linux_timer.expires = jiffies + msecs_to_jiffies(delay_ms); ++ add_timer(&timer->linux_timer); ++} ++ ++VCOS_INLINE_IMPL ++void vcos_timer_cancel(VCOS_TIMER_T *timer) { ++ del_timer(&timer->linux_timer); ++} ++ ++VCOS_INLINE_IMPL ++void vcos_timer_reset(VCOS_TIMER_T *timer, VCOS_UNSIGNED delay_ms) { ++ del_timer_sync(&timer->linux_timer); ++ timer->linux_timer.expires = jiffies + msecs_to_jiffies(delay_ms); ++ add_timer(&timer->linux_timer); ++} ++ ++VCOS_INLINE_IMPL ++void vcos_timer_delete(VCOS_TIMER_T *timer) { ++ timer->context = NULL; ++ timer->expiration_routine = NULL; ++ timer->linux_timer.function = NULL; ++ timer->linux_timer.data = 0; ++ return; ++} ++ ++VCOS_INLINE_IMPL ++VCOS_UNSIGNED vcos_process_id_current(void) { ++ return (VCOS_UNSIGNED)current->pid; ++} ++ ++ ++VCOS_INLINE_IMPL ++int vcos_in_interrupt(void) { ++ return in_interrupt(); ++} ++ ++/*********************************************************** ++ * ++ * Atomic flags ++ * ++ ***********************************************************/ ++ ++VCOS_INLINE_IMPL ++VCOS_STATUS_T vcos_atomic_flags_create(VCOS_ATOMIC_FLAGS_T *atomic_flags) ++{ ++ atomic_set(atomic_flags, 0); ++ return VCOS_SUCCESS; ++} ++ ++VCOS_INLINE_IMPL ++void vcos_atomic_flags_or(VCOS_ATOMIC_FLAGS_T *atomic_flags, uint32_t flags) ++{ ++ uint32_t value; ++ do { ++ value = atomic_read(atomic_flags); ++ } while (atomic_cmpxchg(atomic_flags, value, value | flags) != value); ++} ++ ++VCOS_INLINE_IMPL ++uint32_t vcos_atomic_flags_get_and_clear(VCOS_ATOMIC_FLAGS_T *atomic_flags) ++{ ++ return atomic_xchg(atomic_flags, 0); ++} ++ ++VCOS_INLINE_IMPL ++void vcos_atomic_flags_delete(VCOS_ATOMIC_FLAGS_T *atomic_flags) ++{ ++} ++ ++#undef VCOS_ASSERT_LOGGING_DISABLE ++#define VCOS_ASSERT_LOGGING_DISABLE 0 ++ ++#endif /* VCOS_INLINE_BODIES */ ++ ++VCOS_INLINE_DECL void _vcos_thread_sem_wait(void); ++VCOS_INLINE_DECL void _vcos_thread_sem_post(VCOS_THREAD_T *); ++ ++/*********************************************************** ++ * ++ * Misc ++ * ++ ***********************************************************/ ++VCOS_INLINE_DECL char *vcos_strdup(const char *str); ++ ++/*********************************************************** ++ * ++ * Logging ++ * ++ ***********************************************************/ ++ ++VCOSPRE_ const char * VCOSPOST_ _vcos_log_level(void); ++#define _VCOS_LOG_LEVEL() _vcos_log_level() ++ ++#define vcos_log_platform_init() _vcos_log_platform_init() ++#define vcos_log_platform_register(category) _vcos_log_platform_register(category) ++#define vcos_log_platform_unregister(category) _vcos_log_platform_unregister(category) ++ ++struct VCOS_LOG_CAT_T; /* Forward declaration since vcos_logging.h hasn't been included yet */ ++ ++void _vcos_log_platform_init(void); ++void _vcos_log_platform_register(struct VCOS_LOG_CAT_T *category); ++void _vcos_log_platform_unregister(struct VCOS_LOG_CAT_T *category); ++ ++/*********************************************************** ++ * ++ * Memory barriers ++ * ++ ***********************************************************/ ++ ++#define vcos_wmb(x) wmb() ++#define vcos_rmb() rmb() ++ ++#include "interface/vcos/generic/vcos_common.h" ++/*#include "interface/vcos/generic/vcos_generic_quickslow_mutex.h" */ ++ ++#endif /* VCOS_PLATFORM_H */ ++ +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/linuxkernel/vcos_platform_types.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/linuxkernel/vcos_platform_types.h 2013-07-26 19:32:00.000000000 +0000 +@@ -0,0 +1,47 @@ ++/*============================================================================= ++Copyright (c) 2009 Broadcom Europe Limited. ++All rights reserved. ++ ++Project : vcfw ++Module : osal ++ ++FILE DESCRIPTION ++VideoCore OS Abstraction Layer - platform-specific types and defines ++=============================================================================*/ ++ ++#ifndef VCOS_PLATFORM_TYPES_H ++#define VCOS_PLATFORM_TYPES_H ++ ++#include ++#include ++#include ++ ++#define VCOSPRE_ extern ++#define VCOSPOST_ ++ ++#if defined(__GNUC__) && (( __GNUC__ > 2 ) || (( __GNUC__ == 2 ) && ( __GNUC_MINOR__ >= 3 ))) ++#define VCOS_FORMAT_ATTR_(ARCHETYPE, STRING_INDEX, FIRST_TO_CHECK) __attribute__ ((format (ARCHETYPE, STRING_INDEX, FIRST_TO_CHECK))) ++#else ++#define VCOS_FORMAT_ATTR_(ARCHETYPE, STRING_INDEX, FIRST_TO_CHECK) ++#endif ++ ++#if !defined( __STDC_VERSION__ ) ++#define __STDC_VERSION__ 199901L ++#endif ++ ++#if !defined( __STDC_VERSION ) ++#define __STDC_VERSION __STDC_VERSION__ ++#endif ++ ++static inline void __vcos_bkpt( void ) { BUG(); } ++#define VCOS_BKPT __vcos_bkpt() ++ ++#define VCOS_ASSERT_MSG(...) printk( KERN_ERR "vcos_assert: " __VA_ARGS__ ) ++ ++#define PRId64 "lld" ++#define PRIi64 "lli" ++#define PRIo64 "llo" ++#define PRIu64 "llu" ++#define PRIx64 "llx" ++ ++#endif +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/linuxkernel/vcos_thread_map.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/linuxkernel/vcos_thread_map.c 2013-07-26 19:32:00.000000000 +0000 +@@ -0,0 +1,129 @@ ++/***************************************************************************** ++* Copyright 2009 - 2010 Broadcom Corporation. All rights reserved. ++* ++* Unless you and Broadcom execute a separate written software license ++* agreement governing use of this software, this software is licensed to you ++* under the terms of the GNU General Public License version 2, available at ++* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). ++* ++* Notwithstanding the above, under no circumstances may you combine this ++* software in any way with any other Broadcom software provided under a ++* license other than the GPL, without Broadcom's express prior written ++* consent. ++*****************************************************************************/ ++ ++/** Support to allow VCOS thread-related functions to be called from ++ * threads that were not created by VCOS. ++ */ ++ ++#include ++#include ++#include ++#include ++ ++#include "vcos_thread_map.h" ++#include "interface/vcos/vcos_logging.h" ++ ++/* ++ * Store the vcos_thread pointer at the end of ++ * current kthread stack, right after the thread_info ++ * structure. ++ * ++ * I belive we should be safe here to steal these 4 bytes ++ * from the stack, as long as the vcos thread does not use up ++ * all the stack available ++ * ++ * NOTE: This scheme will not work on architectures with stack growing up ++ */ ++ ++/* Shout, if we are not being compiled for ARM kernel */ ++ ++#ifndef CONFIG_ARM ++#error " **** The vcos kthread implementation may not work for non-ARM kernel ****" ++#endif ++ ++static inline void *to_current_vcos_thread(void) ++{ ++ unsigned long *vcos_data; ++ ++ vcos_data = (unsigned long *)((char *)current_thread_info() + sizeof(struct thread_info)); ++ ++ return (void *)vcos_data; ++} ++ ++ ++static inline void *to_vcos_thread(struct task_struct *tsk) ++{ ++ unsigned long *vcos_data; ++ ++ vcos_data = (unsigned long *)((char *)tsk->stack + sizeof(struct thread_info)); ++ ++ return (void *)vcos_data; ++} ++ ++/** ++ @fn uint32_t vcos_add_thread(THREAD_MAP_T *vcos_thread); ++*/ ++uint32_t vcos_add_thread(VCOS_THREAD_T *vcos_thread) ++{ ++ VCOS_THREAD_T **vcos_thread_storage = (VCOS_THREAD_T **)to_current_vcos_thread(); ++ ++ *vcos_thread_storage = vcos_thread; ++ ++ return(0); ++} ++ ++ ++/** ++ @fn uint32_t vcos_remove_thread(struct task_struct * thread_id); ++*/ ++uint32_t vcos_remove_thread(struct task_struct *thread_id) ++{ ++ /* Remove thread_id -> VCOS_THREAD_T relationship */ ++ VCOS_THREAD_T **vcos_thread_storage; ++ ++ /* ++ * We want to be able to build vcos as a loadable module, which ++ * means that we can't call get_task_struct. So we assert if we're ++ * ever called with thread_id != current. ++ */ ++ ++ BUG_ON( thread_id != current ); ++ ++ vcos_thread_storage = (VCOS_THREAD_T **)to_vcos_thread(thread_id); ++ ++ *(unsigned long *)vcos_thread_storage = 0xCAFEBABE; ++ ++ return(0); ++} ++ ++ ++VCOS_THREAD_T *vcos_kthread_current(void) ++{ ++ VCOS_THREAD_T **vcos_thread_storage = (VCOS_THREAD_T **)to_current_vcos_thread(); ++ ++ /* If we find this, either the thread is already dead or stack pages of a ++ * dead vcos thread are re-allocated to this one. ++ * ++ * Since there's no way to differentiate between these 2 cases, we just dump ++ * the current task name to the log. ++ * ++ * If the current thread is created using VCOS API, you should *never* see this ++ * print. ++ * ++ * If its a non-VCOS thread, just let it go ... ++ * ++ * To debug VCOS, uncomment printk's under the "if" condition below ++ * ++ */ ++ if (*vcos_thread_storage == (void *)0xCAFEBABE) ++ { ++ #if 0 ++ printk(KERN_DEBUG"****************************************************\n"); ++ printk(KERN_DEBUG"%s : You have a problem, if \"%s\" is a VCOS thread\n",__func__, current->comm); ++ printk(KERN_DEBUG"****************************************************\n"); ++ #endif ++ } ++ ++ return *vcos_thread_storage; ++} +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/linuxkernel/vcos_thread_map.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/linuxkernel/vcos_thread_map.h 2013-07-26 19:32:00.000000000 +0000 +@@ -0,0 +1,39 @@ ++/***************************************************************************** ++* Copyright 2009 - 2010 Broadcom Corporation. All rights reserved. ++* ++* Unless you and Broadcom execute a separate written software license ++* agreement governing use of this software, this software is licensed to you ++* under the terms of the GNU General Public License version 2, available at ++* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). ++* ++* Notwithstanding the above, under no circumstances may you combine this ++* software in any way with any other Broadcom software provided under a ++* license other than the GPL, without Broadcom's express prior written ++* consent. ++*****************************************************************************/ ++ ++ ++#ifndef VCOS_THREAD_MAP_H ++#define VCOS_THREAD_MAP_H ++ ++#include ++ ++#include "vcos_platform.h" ++ ++static inline void vcos_thread_map_init(void) ++{ ++ return; ++} ++ ++static inline void vcos_thread_map_cleanup(void) ++{ ++ return; ++} ++ ++uint32_t vcos_add_thread(VCOS_THREAD_T *vcos_thread); ++ ++uint32_t vcos_remove_thread(struct task_struct *thread_id); ++ ++VCOS_THREAD_T *vcos_kthread_current(void); ++ ++#endif /*VCOS_THREAD_MAP_H */ +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos.h 2013-07-26 19:32:00.000000000 +0000 +@@ -0,0 +1,201 @@ ++/*============================================================================= ++Copyright (c) 2009 Broadcom Europe Limited. ++All rights reserved. ++ ++Project : vcfw ++Module : chip driver ++ ++FILE DESCRIPTION ++VideoCore OS Abstraction Layer - public header file ++=============================================================================*/ ++ ++/** ++ * \mainpage OS Abstraction Layer ++ * ++ * \section intro Introduction ++ * ++ * This abstraction layer is here to allow the underlying OS to be easily changed (e.g. from ++ * Nucleus to ThreadX) and to aid in porting host applications to new targets. ++ * ++ * \subsection error Error handling ++ * ++ * Wherever possible, VCOS functions assert internally and return void. The only exceptions ++ * are creation functions (which might fail due to lack of resources) and functions that ++ * might timeout or fail due to lack of space. Errors that might be reported by the underlying ++ * OS API (e.g. invalid mutex) are treated as a programming error, and are merely asserted on. ++ * ++ * \section thread_synch Threads and synchronisation ++ * ++ * \subsection thread Threads ++ * ++ * The thread API is somewhat different to that found in Nucleus. In particular, threads ++ * cannot just be destroyed at arbitrary times and nor can they merely exit. This is so ++ * that the same API can be implemented across all interesting platforms without too much ++ * difficulty. See vcos_thread.h for details. Thread attributes are configured via ++ * the VCOS_THREAD_ATTR_T structure, found in vcos_thread_attr.h. ++ * ++ * \subsection sema Semaphores ++ * ++ * Counted semaphores (c.f. Nucleus NU_SEMAPHORE) are created with VCOS_SEMAPHORE_T. ++ * Under ThreadX on VideoCore, semaphores are implemented using VideoCore spinlocks, and ++ * so are quite a lot faster than ordinary ThreadX semaphores. See vcos_semaphore.h. ++ * ++ * \subsection mtx Mutexes ++ * ++ * Mutexes are used for locking. Attempts to take a mutex twice, or to unlock it ++ * in a different thread to the one in which it was locked should be expected to fail. ++ * Mutexes are not re-entrant (see vcos_reentrant_mutex.h for a slightly slower ++ * re-entrant mutex). ++ * ++ * \subsection evflags Event flags ++ * ++ * Event flags (the ThreadX name - also known as event groups under Nucleus) provide ++ * 32 flags which can be waited on by multiple clients, and signalled by multiple clients. ++ * A timeout can be specified. See vcos_event_flags.h. An alternative to this is the ++ * VCOS_EVENT_T (see vcos_event.h) which is akin to the Win32 auto-reset event, or a ++ * saturating counted semaphore. ++ * ++ * \subsection event Events ++ * ++ * A VCOS_EVENT_T is a bit like a saturating semaphore. No matter how many times it ++ * is signalled, the waiter will only wake up once. See vcos_event.h. You might think this ++ * is useful if you suspect that the cost of reading the semaphore count (perhaps via a ++ * system call) is expensive on your platform. ++ * ++ * \subsection tls Thread local storage ++ * ++ * Thread local storage is supported using vcos_tls.h. This is emulated on Nucleus ++ * and ThreadX. ++ * ++ * \section int Interrupts ++ * ++ * The legacy LISR/HISR scheme found in Nucleus is supported via the legacy ISR API, ++ * which is also supported on ThreadX. New code should avoid this, and old code should ++ * be migrated away from it, since it is slow. See vcos_legacy_isr.h. ++ * ++ * Registering an interrupt handler, and disabling/restoring interrupts, is handled ++ * using the functions in vcos_isr.h. ++ * ++ */ ++ ++/** ++ * \file vcos.h ++ * ++ * This is the top level header file. Clients include this. It pulls in the platform-specific ++ * header file (vcos_platform.h) together with header files defining the expected APIs, such ++ * as vcos_mutex.h, vcos_semaphore.h, etc. It is also possible to include these header files ++ * directly. ++ * ++ */ ++ ++#ifndef VCOS_H ++#define VCOS_H ++ ++#include "interface/vcos/vcos_assert.h" ++#include "vcos_types.h" ++#include "vcos_platform.h" ++ ++#ifndef VCOS_INIT_H ++#include "interface/vcos/vcos_init.h" ++#endif ++ ++#ifndef VCOS_SEMAPHORE_H ++#include "interface/vcos/vcos_semaphore.h" ++#endif ++ ++#ifndef VCOS_THREAD_H ++#include "interface/vcos/vcos_thread.h" ++#endif ++ ++#ifndef VCOS_MUTEX_H ++#include "interface/vcos/vcos_mutex.h" ++#endif ++ ++#ifndef VCOS_MEM_H ++#include "interface/vcos/vcos_mem.h" ++#endif ++ ++#ifndef VCOS_LOGGING_H ++#include "interface/vcos/vcos_logging.h" ++#endif ++ ++#ifndef VCOS_STRING_H ++#include "interface/vcos/vcos_string.h" ++#endif ++ ++#ifndef VCOS_EVENT_H ++#include "interface/vcos/vcos_event.h" ++#endif ++ ++#ifndef VCOS_THREAD_ATTR_H ++#include "interface/vcos/vcos_thread_attr.h" ++#endif ++ ++#ifndef VCOS_TLS_H ++#include "interface/vcos/vcos_tls.h" ++#endif ++ ++#ifndef VCOS_REENTRANT_MUTEX_H ++#include "interface/vcos/vcos_reentrant_mutex.h" ++#endif ++ ++#ifndef VCOS_NAMED_SEMAPHORE_H ++#include "interface/vcos/vcos_named_semaphore.h" ++#endif ++ ++#ifndef VCOS_QUICKSLOW_MUTEX_H ++#include "interface/vcos/vcos_quickslow_mutex.h" ++#endif ++ ++/* Headers with predicates */ ++ ++#if VCOS_HAVE_EVENT_FLAGS ++#include "interface/vcos/vcos_event_flags.h" ++#endif ++ ++#if VCOS_HAVE_QUEUE ++#include "interface/vcos/vcos_queue.h" ++#endif ++ ++#if VCOS_HAVE_LEGACY_ISR ++#include "interface/vcos/vcos_legacy_isr.h" ++#endif ++ ++#if VCOS_HAVE_TIMER ++#include "interface/vcos/vcos_timer.h" ++#endif ++ ++#if VCOS_HAVE_MEMPOOL ++#include "interface/vcos/vcos_mempool.h" ++#endif ++ ++#if VCOS_HAVE_ISR ++#include "interface/vcos/vcos_isr.h" ++#endif ++ ++#if VCOS_HAVE_ATOMIC_FLAGS ++#include "interface/vcos/vcos_atomic_flags.h" ++#endif ++ ++#if VCOS_HAVE_ONCE ++#include "interface/vcos/vcos_once.h" ++#endif ++ ++#if VCOS_HAVE_BLOCK_POOL ++#include "interface/vcos/vcos_blockpool.h" ++#endif ++ ++#if VCOS_HAVE_FILE ++#include "interface/vcos/vcos_file.h" ++#endif ++ ++#if VCOS_HAVE_CFG ++#include "interface/vcos/vcos_cfg.h" ++#endif ++ ++#if VCOS_HAVE_CMD ++#include "interface/vcos/vcos_cmd.h" ++#endif ++ ++#endif /* VCOS_H */ ++ +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_assert.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_assert.h 2013-07-26 19:32:00.000000000 +0000 +@@ -0,0 +1,269 @@ ++/*============================================================================= ++Copyright (c) 2009 Broadcom Europe Limited. ++All rights reserved. ++ ++Project : vcfw ++Module : osal ++ ++FILE DESCRIPTION ++VideoCore OS Abstraction Layer - Assertion and error-handling macros. ++=============================================================================*/ ++ ++ ++#ifndef VCOS_ASSERT_H ++#define VCOS_ASSERT_H ++ ++/* ++ * Macro: ++ * vcos_assert(cond) ++ * vcos_assert_msg(cond, fmt, ...) ++ * Use: ++ * Detecting programming errors by ensuring that assumptions are correct. ++ * On failure: ++ * Performs a platform-dependent "breakpoint", usually with an assert-style ++ * message. The '_msg' variant expects a printf-style format string and ++ * parameters. ++ * If a failure is detected, the code should be fixed and rebuilt. ++ * In release builds: ++ * Generates no code, i.e. does not evaluate 'cond'. ++ * Returns: ++ * Nothing. ++ * ++ * Macro: ++ * vcos_demand(cond) ++ * vcos_demand_msg(cond, fmt, ...) ++ * Use: ++ * Detecting fatal system errors that require a reboot. ++ * On failure: ++ * Performs a platform-dependent "breakpoint", usually with an assert-style ++ * message, then calls vcos_abort (see below). ++ * In release builds: ++ * Calls vcos_abort() if 'cond' is false. ++ * Returns: ++ * Nothing (never, on failure). ++ * ++ * Macro: ++ * vcos_verify(cond) ++ * vcos_verify_msg(cond, fmt, ...) ++ * Use: ++ * Detecting run-time errors and interesting conditions, normally within an ++ * 'if' statement to catch the failures, i.e. ++ * if (!vcos_verify(cond)) handle_error(); ++ * On failure: ++ * Generates a message and optionally stops at a platform-dependent ++ * "breakpoint" (usually disabled). See vcos_verify_bkpts_enable below. ++ * In release builds: ++ * Just evaluates and returns 'cond'. ++ * Returns: ++ * Non-zero if 'cond' is true, otherwise zero. ++ * ++ * Macro: ++ * vcos_static_assert(cond) ++ * Use: ++ * Detecting compile-time errors. ++ * On failure: ++ * Generates a compiler error. ++ * In release builds: ++ * Generates a compiler error. ++ * ++ * Function: ++ * void vcos_abort(void) ++ * Use: ++ * Invokes the fatal error handling mechanism, alerting the host where ++ * applicable. ++ * Returns: ++ * Never. ++ * ++ * Macro: ++ * VCOS_VERIFY_BKPTS ++ * Use: ++ * Define in a module (before including vcos.h) to specify an alternative ++ * flag to control breakpoints on vcos_verify() failures. ++ * Returns: ++ * Non-zero values enable breakpoints. ++ * ++ * Function: ++ * int vcos_verify_bkpts_enable(int enable); ++ * Use: ++ * Sets the global flag controlling breakpoints on vcos_verify failures, ++ * enabling the breakpoints iff 'enable' is non-zero. ++ * Returns: ++ * The previous state of the flag. ++ * ++ * Function: ++ * int vcos_verify_bkpts_enabled(void); ++ * Use: ++ * Queries the state of the global flag enabling breakpoints on vcos_verify ++ * failures. ++ * Returns: ++ * The current state of the flag. ++ * ++ * Examples: ++ * ++ * int my_breakpoint_enable_flag = 1; ++ * ++ * #define VCOS_VERIFY_BKPTS my_breakpoint_enable_flag ++ * ++ * #include "interface/vcos/vcos.h" ++ * ++ * vcos_static_assert((sizeof(object) % 32) == 0); ++ * ++ * // ... ++ * ++ * vcos_assert_msg(postcondition_is_true, "Coding error"); ++ * ++ * if (!vcos_verify_msg(buf, "Buffer allocation failed (%d bytes)", size)) ++ * { ++ * // Tidy up ++ * // ... ++ * return OUT_OF_MEMORY; ++ * } ++ * ++ * vcos_demand(*p++==GUARDWORDHEAP); ++ */ ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++#include "interface/vcos/vcos_types.h" ++ ++#ifdef __COVERITY__ ++#undef VCOS_ASSERT_BKPT ++#define VCOS_ASSERT_BKPT __coverity_panic__() ++#endif ++ ++#ifndef VCOS_VERIFY_BKPTS ++#define VCOS_VERIFY_BKPTS vcos_verify_bkpts_enabled() ++#endif ++ ++#ifndef VCOS_BKPT ++#if defined(__VIDEOCORE__) && !defined(VCOS_ASSERT_NO_BKPTS) ++#define VCOS_BKPT _bkpt() ++#else ++#define VCOS_BKPT (void )0 ++#endif ++#endif ++ ++#ifndef VCOS_ASSERT_BKPT ++#define VCOS_ASSERT_BKPT VCOS_BKPT ++#endif ++ ++#ifndef VCOS_VERIFY_BKPT ++#define VCOS_VERIFY_BKPT (VCOS_VERIFY_BKPTS ? VCOS_BKPT : (void)0) ++#endif ++ ++VCOSPRE_ int VCOSPOST_ vcos_verify_bkpts_enabled(void); ++VCOSPRE_ int VCOSPOST_ vcos_verify_bkpts_enable(int enable); ++VCOSPRE_ void VCOSPOST_ vcos_abort(void); ++ ++#ifndef VCOS_ASSERT_MSG ++#ifdef LOGGING ++extern void logging_assert(const char *file, const char *func, int line, const char *format, ...); ++#define VCOS_ASSERT_MSG(...) ((VCOS_ASSERT_LOGGING && !VCOS_ASSERT_LOGGING_DISABLE) ? logging_assert(__FILE__, __func__, __LINE__, __VA_ARGS__) : (void)0) ++#else ++#define VCOS_ASSERT_MSG(...) ((void)0) ++#endif ++#endif ++ ++#ifndef VCOS_VERIFY_MSG ++#define VCOS_VERIFY_MSG(...) VCOS_ASSERT_MSG(__VA_ARGS__) ++#endif ++ ++#ifndef VCOS_ASSERT_LOGGING ++#define VCOS_ASSERT_LOGGING 0 ++#endif ++ ++#ifndef VCOS_ASSERT_LOGGING_DISABLE ++#define VCOS_ASSERT_LOGGING_DISABLE 0 ++#endif ++ ++#if !defined(NDEBUG) || defined(VCOS_RELEASE_ASSERTS) ++ ++#ifndef vcos_assert ++#define vcos_assert(cond) \ ++ ( (cond) ? (void)0 : (VCOS_ASSERT_MSG("%s", #cond), VCOS_ASSERT_BKPT) ) ++#endif ++ ++#ifndef vcos_assert_msg ++#define vcos_assert_msg(cond, ...) \ ++ ( (cond) ? (void)0 : (VCOS_ASSERT_MSG(__VA_ARGS__), VCOS_ASSERT_BKPT) ) ++#endif ++ ++#else /* !defined(NDEBUG) || defined(VCOS_RELEASE_ASSERTS) */ ++ ++#ifndef vcos_assert ++#define vcos_assert(cond) (void)0 ++#endif ++ ++#ifndef vcos_assert_msg ++#define vcos_assert_msg(cond, ...) (void)0 ++#endif ++ ++#endif /* !defined(NDEBUG) || defined(VCOS_RELEASE_ASSERTS) */ ++ ++#if !defined(NDEBUG) ++ ++#ifndef vcos_demand ++#define vcos_demand(cond) \ ++ ( (cond) ? (void)0 : (VCOS_ASSERT_MSG("%s", #cond), VCOS_ASSERT_BKPT, vcos_abort()) ) ++#endif ++ ++#ifndef vcos_demand_msg ++#define vcos_demand_msg(cond, ...) \ ++ ( (cond) ? (void)0 : (VCOS_ASSERT_MSG(__VA_ARGS__), VCOS_ASSERT_BKPT, vcos_abort()) ) ++#endif ++ ++#ifndef vcos_verify ++#define vcos_verify(cond) \ ++ ( (cond) ? 1 : (VCOS_VERIFY_MSG("%s", #cond), VCOS_VERIFY_BKPT, 0) ) ++#endif ++ ++#ifndef vcos_verify_msg ++#define vcos_verify_msg(cond, ...) \ ++ ( (cond) ? 1 : (VCOS_VERIFY_MSG(__VA_ARGS__), VCOS_VERIFY_BKPT, 0) ) ++#endif ++ ++#else /* !defined(NDEBUG) */ ++ ++#ifndef vcos_demand ++#define vcos_demand(cond) \ ++ ( (cond) ? (void)0 : vcos_abort() ) ++#endif ++ ++#ifndef vcos_demand_msg ++#define vcos_demand_msg(cond, ...) \ ++ ( (cond) ? (void)0 : vcos_abort() ) ++#endif ++ ++#ifndef vcos_verify ++#define vcos_verify(cond) (cond) ++#endif ++ ++#ifndef vcos_verify_msg ++#define vcos_verify_msg(cond, ...) (cond) ++#endif ++ ++#endif /* !defined(NDEBUG) */ ++ ++#ifndef vcos_static_assert ++#if defined(__GNUC__) ++#define vcos_static_assert(cond) __attribute__((unused)) extern int vcos_static_assert[(cond)?1:-1] ++#else ++#define vcos_static_assert(cond) extern int vcos_static_assert[(cond)?1:-1] ++#endif ++#endif ++ ++#ifndef vc_assert ++#define vc_assert(cond) vcos_assert(cond) ++#endif ++ ++/** Print out a backtrace, on supported platforms. ++ */ ++extern void vcos_backtrace_self(void); ++ ++#ifdef __cplusplus ++} ++#endif ++ ++#endif /* VCOS_ASSERT_H */ +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_atomic_flags.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_atomic_flags.h 2013-07-26 19:32:00.000000000 +0000 +@@ -0,0 +1,72 @@ ++/*============================================================================= ++Copyright (c) 2009 Broadcom Europe Limited. ++All rights reserved. ++ ++Project : vcfw ++Module : chip driver (just for consistency with the rest of vcos ;) ++ ++FILE DESCRIPTION ++VideoCore OS Abstraction Layer - public header file ++=============================================================================*/ ++ ++#ifndef VCOS_ATOMIC_FLAGS_H ++#define VCOS_ATOMIC_FLAGS_H ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++#include "interface/vcos/vcos_types.h" ++#include "vcos_platform.h" ++ ++/** ++ * \file vcos_atomic_flags.h ++ * ++ * Defines atomic flags API. ++ * ++ * 32 flags. Atomic "or" and "get and clear" operations ++ */ ++ ++/** ++ * Create an atomic flags instance. ++ * ++ * @param atomic_flags Pointer to atomic flags instance, filled in on return ++ * ++ * @return VCOS_SUCCESS if succeeded. ++ */ ++VCOS_INLINE_DECL ++VCOS_STATUS_T vcos_atomic_flags_create(VCOS_ATOMIC_FLAGS_T *atomic_flags); ++ ++/** ++ * Atomically set the specified flags. ++ * ++ * @param atomic_flags Instance to set flags on ++ * @param flags Mask of flags to set ++ */ ++VCOS_INLINE_DECL ++void vcos_atomic_flags_or(VCOS_ATOMIC_FLAGS_T *atomic_flags, uint32_t flags); ++ ++/** ++ * Retrieve the current flags and then clear them. The entire operation is ++ * atomic. ++ * ++ * @param atomic_flags Instance to get/clear flags from/on ++ * ++ * @return Mask of flags which were set (and we cleared) ++ */ ++VCOS_INLINE_DECL ++uint32_t vcos_atomic_flags_get_and_clear(VCOS_ATOMIC_FLAGS_T *atomic_flags); ++ ++/** ++ * Delete an atomic flags instance. ++ * ++ * @param atomic_flags Instance to delete ++ */ ++VCOS_INLINE_DECL ++void vcos_atomic_flags_delete(VCOS_ATOMIC_FLAGS_T *atomic_flags); ++ ++#ifdef __cplusplus ++} ++#endif ++ ++#endif +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_build_info.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_build_info.h 2013-07-26 19:32:00.000000000 +0000 +@@ -0,0 +1,5 @@ ++const char *vcos_get_build_hostname( void ); ++const char *vcos_get_build_version( void ); ++const char *vcos_get_build_time( void ); ++const char *vcos_get_build_date( void ); ++ +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_cfg.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_cfg.h 2013-07-26 19:32:00.000000000 +0000 +@@ -0,0 +1,113 @@ ++/***************************************************************************** ++* Copyright 2009 - 2011 Broadcom Corporation. All rights reserved. ++* ++* Unless you and Broadcom execute a separate written software license ++* agreement governing use of this software, this software is licensed to you ++* under the terms of the GNU General Public License version 2, available at ++* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). ++* ++* Notwithstanding the above, under no circumstances may you combine this ++* software in any way with any other Broadcom software provided under a ++* license other than the GPL, without Broadcom's express prior written ++* consent. ++*****************************************************************************/ ++ ++#if !defined( VCOS_CFG_H ) ++#define VCOS_CFG_H ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++#include "interface/vcos/vcos_types.h" ++#include "vcos_platform.h" ++ ++typedef struct opaque_vcos_cfg_buf_t *VCOS_CFG_BUF_T; ++typedef struct opaque_vcos_cfg_entry_t *VCOS_CFG_ENTRY_T; ++ ++/** \file vcos_file.h ++ * ++ * API for accessing configuration/statistics information. This ++ * is loosely modelled on the linux proc entries. ++ */ ++ ++typedef void (*VCOS_CFG_SHOW_FPTR)( VCOS_CFG_BUF_T buf, void *data ); ++typedef void (*VCOS_CFG_PARSE_FPTR)( VCOS_CFG_BUF_T buf, void *data ); ++ ++/** Create a configuration directory. ++ * ++ * @param entry Place to store the created config entry. ++ * @param parent Parent entry (for directory like config ++ * options). ++ * @param entryName Name of the directory. ++ */ ++ ++VCOS_STATUS_T vcos_cfg_mkdir( VCOS_CFG_ENTRY_T *entry, ++ VCOS_CFG_ENTRY_T *parent, ++ const char *dirName ); ++ ++/** Create a configuration entry. ++ * ++ * @param entry Place to store the created config entry. ++ * @param parent Parent entry (for directory like config ++ * options). ++ * @param entryName Name of the configuration entry. ++ * @param showFunc Function pointer to show configuration ++ * data. ++ * @param parseFunc Function pointer to parse new data. ++ */ ++ ++VCOS_STATUS_T vcos_cfg_create_entry( VCOS_CFG_ENTRY_T *entry, ++ VCOS_CFG_ENTRY_T *parent, ++ const char *entryName, ++ VCOS_CFG_SHOW_FPTR showFunc, ++ VCOS_CFG_PARSE_FPTR parseFunc, ++ void *data ); ++ ++/** Determines if a configuration entry has been created or not. ++ * ++ * @param entry Configuration entry to query. ++ */ ++ ++int vcos_cfg_is_entry_created( VCOS_CFG_ENTRY_T entry ); ++ ++/** Returns the name of a configuration entry. ++ * ++ * @param entry Configuration entry to query. ++ */ ++ ++const char *vcos_cfg_get_entry_name( VCOS_CFG_ENTRY_T entry ); ++ ++/** Removes a configuration entry. ++ * ++ * @param entry Configuration entry to remove. ++ */ ++ ++VCOS_STATUS_T vcos_cfg_remove_entry( VCOS_CFG_ENTRY_T *entry ); ++ ++ ++/** Writes data into a configuration buffer. Only valid inside ++ * the show function. ++ * ++ * @param buf Buffer to write data into. ++ * @param fmt printf style format string. ++ */ ++ ++void vcos_cfg_buf_printf( VCOS_CFG_BUF_T buf, const char *fmt, ... ); ++ ++/** Retrieves a null terminated string of the data associated ++ * with the buffer. Only valid inside the parse function. ++ * ++ * @param buf Buffer to get data from. ++ * @param fmt printf style format string. ++ */ ++ ++char *vcos_cfg_buf_get_str( VCOS_CFG_BUF_T buf ); ++ ++void *vcos_cfg_get_proc_entry( VCOS_CFG_ENTRY_T entry ); ++ ++#ifdef __cplusplus ++} ++#endif ++#endif ++ +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_cmd.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_cmd.h 2013-07-26 19:32:00.000000000 +0000 +@@ -0,0 +1,98 @@ ++/***************************************************************************** ++* Copyright 2009 - 2011 Broadcom Corporation. All rights reserved. ++* ++* Unless you and Broadcom execute a separate written software license ++* agreement governing use of this software, this software is licensed to you ++* under the terms of the GNU General Public License version 2, available at ++* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). ++* ++* Notwithstanding the above, under no circumstances may you combine this ++* software in any way with any other Broadcom software provided under a ++* license other than the GPL, without Broadcom's express prior written ++* consent. ++*****************************************************************************/ ++ ++#if !defined( VCOS_CMD_H ) ++#define VCOS_CMD_H ++ ++/* ---- Include Files ----------------------------------------------------- */ ++ ++#include "interface/vcos/vcos.h" ++#include "interface/vcos/vcos_stdint.h" ++ ++ ++/* ---- Constants and Types ---------------------------------------------- */ ++ ++struct VCOS_CMD_S; ++typedef struct VCOS_CMD_S VCOS_CMD_T; ++ ++typedef struct ++{ ++ int argc; /* Number of arguments (includes the command/sub-command) */ ++ char **argv; /* Array of arguments */ ++ char **argv_orig; /* Original array of arguments */ ++ ++ VCOS_CMD_T *cmd_entry; ++ VCOS_CMD_T *cmd_parent_entry; ++ ++ int use_log; /* Output being logged? */ ++ size_t result_size; /* Size of result buffer. */ ++ char *result_ptr; /* Next place to put output. */ ++ char *result_buf; /* Start of the buffer. */ ++ ++} VCOS_CMD_PARAM_T; ++ ++typedef VCOS_STATUS_T (*VCOS_CMD_FUNC_T)( VCOS_CMD_PARAM_T *param ); ++ ++struct VCOS_CMD_S ++{ ++ const char *name; ++ const char *args; ++ VCOS_CMD_FUNC_T cmd_fn; ++ VCOS_CMD_T *sub_cmd_entry; ++ const char *descr; ++ ++}; ++ ++/* ---- Variable Externs ------------------------------------------------- */ ++ ++/* ---- Function Prototypes ---------------------------------------------- */ ++ ++/* ++ * Common printing routine for generating command output. ++ */ ++VCOSPRE_ void VCOSPOST_ vcos_cmd_error( VCOS_CMD_PARAM_T *param, const char *fmt, ... ) VCOS_FORMAT_ATTR_(printf, 2, 3); ++VCOSPRE_ void VCOSPOST_ vcos_cmd_printf( VCOS_CMD_PARAM_T *param, const char *fmt, ... ) VCOS_FORMAT_ATTR_(printf, 2, 3); ++VCOSPRE_ void VCOSPOST_ vcos_cmd_vprintf( VCOS_CMD_PARAM_T *param, const char *fmt, va_list args ) VCOS_FORMAT_ATTR_(printf, 2, 0); ++ ++/* ++ * Cause vcos_cmd_error, printf and vprintf to always log to the provided ++ * category. When this call is made, the results buffer passed into ++ * vcos_cmd_execute is used as a line buffer and does not need to be ++ * output by the caller. ++ */ ++VCOSPRE_ void VCOSPOST_ vcos_cmd_always_log_output( VCOS_LOG_CAT_T *log_category ); ++ ++/* ++ * Prints command usage for the current command. ++ */ ++VCOSPRE_ void VCOSPOST_ vcos_cmd_usage( VCOS_CMD_PARAM_T *param ); ++ ++/* ++ * Register commands to be processed ++ */ ++VCOSPRE_ VCOS_STATUS_T VCOSPOST_ vcos_cmd_register( VCOS_CMD_T *cmd_entry ); ++ ++/* ++ * Registers multiple commands to be processed. The array should ++ * be terminated by an entry with all zeros. ++ */ ++VCOSPRE_ VCOS_STATUS_T VCOSPOST_ vcos_cmd_register_multiple( VCOS_CMD_T *cmd_entry ); ++ ++/* ++ * Executes a command based on a command line. ++ */ ++VCOSPRE_ VCOS_STATUS_T VCOSPOST_ vcos_cmd_execute( int argc, char **argv, size_t result_size, char *result_buf ); ++ ++#endif /* VCOS_CMD_H */ ++ +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_ctype.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_ctype.h 2013-07-26 19:32:00.000000000 +0000 +@@ -0,0 +1,29 @@ ++/*============================================================================= ++Copyright (c) 2009 Broadcom Europe Limited. ++All rights reserved. ++ ++Project : vcfw ++Module : chip driver ++ ++FILE DESCRIPTION ++VideoCore OS Abstraction Layer - public header file ++=============================================================================*/ ++ ++#ifndef VCOS_CTYPE_H ++#define VCOS_CTYPE_H ++ ++/** ++ * \file ++ * ++ * ctype functions. ++ * ++ */ ++ ++#ifdef __KERNEL__ ++#include ++#else ++#include ++#endif ++ ++#endif ++ +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_dlfcn.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_dlfcn.h 2013-07-26 19:32:00.000000000 +0000 +@@ -0,0 +1,69 @@ ++/*============================================================================= ++Copyright (c) 2010 Broadcom Europe Limited. ++All rights reserved. ++ ++Project : vcfw ++Module : chip driver ++ ++FILE DESCRIPTION ++VCOS - abstraction over dynamic library opening ++=============================================================================*/ ++ ++#ifndef VCOS_DLFCN_H ++#define VCOS_DLFCN_H ++ ++#include "interface/vcos/vcos_types.h" ++#include "vcos_platform.h" ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++#define VCOS_DL_LAZY 1 ++#define VCOS_DL_NOW 2 ++ ++/** ++ * \file ++ * ++ * Loading dynamic libraries. See also dlfcn.h. ++ */ ++ ++/** Open a dynamic library. ++ * ++ * @param name name of the library ++ * @param mode Load lazily or immediately (VCOS_DL_LAZY, VCOS_DL_NOW). ++ * ++ * @return A handle for use in subsequent calls. ++ */ ++VCOSPRE_ void * VCOSPOST_ vcos_dlopen(const char *name, int mode); ++ ++/** Look up a symbol. ++ * ++ * @param handle Handle to open ++ * @param name Name of function ++ * ++ * @return Function pointer, or NULL. ++ */ ++VCOSPRE_ void VCOSPOST_ (*vcos_dlsym(void *handle, const char *name))(void); ++ ++/** Close a library ++ * ++ * @param handle Handle to close ++ */ ++VCOSPRE_ int VCOSPOST_ vcos_dlclose (void *handle); ++ ++/** Return error message from library. ++ * ++ * @param err On return, set to non-zero if an error has occurred ++ * @param buf Buffer to write error to ++ * @param len Size of buffer (including terminating NUL). ++ */ ++VCOSPRE_ int VCOSPOST_ vcos_dlerror(int *err, char *buf, size_t buflen); ++ ++ ++#ifdef __cplusplus ++} ++#endif ++#endif ++ ++ +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_event.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_event.h 2013-07-26 19:32:00.000000000 +0000 +@@ -0,0 +1,97 @@ ++/*============================================================================= ++Copyright (c) 2009 Broadcom Europe Limited. ++All rights reserved. ++ ++Project : vcfw ++Module : chip driver ++ ++FILE DESCRIPTION ++VideoCore OS Abstraction Layer - public header file for events ++=============================================================================*/ ++ ++#ifndef VCOS_EVENT_H ++#define VCOS_EVENT_H ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++#include "interface/vcos/vcos_types.h" ++#include "vcos_platform.h" ++ ++/** ++ * \file ++ * ++ * An event is akin to the Win32 auto-reset event. ++ * ++ * ++ * Signalling an event will wake up one waiting thread only. Once one ++ * thread has been woken the event atomically returns to the unsignalled ++ * state. ++ * ++ * If no threads are waiting on the event when it is signalled it remains ++ * signalled. ++ * ++ * This is almost, but not quite, completely unlike the "event flags" ++ * object based on Nucleus event groups and ThreadX event flags. ++ * ++ * In particular, it should be similar in speed to a semaphore, unlike ++ * the event flags. ++ */ ++ ++/** ++ * Create an event instance. ++ * ++ * @param event Filled in with constructed event. ++ * @param name Name of the event (for debugging) ++ * ++ * @return VCOS_SUCCESS on success, or error code. ++ */ ++VCOS_INLINE_DECL ++VCOS_STATUS_T vcos_event_create(VCOS_EVENT_T *event, const char *name); ++ ++#ifndef vcos_event_signal ++ ++/** ++ * Signal the event. The event will return to being unsignalled ++ * after exactly one waiting thread has been woken up. If no ++ * threads are waiting it remains signalled. ++ * ++ * @param event The event to signal ++ */ ++VCOS_INLINE_DECL ++void vcos_event_signal(VCOS_EVENT_T *event); ++ ++/** ++ * Wait for the event. ++ * ++ * @param event The event to wait for ++ * @return VCOS_SUCCESS on success, VCOS_EAGAIN if the wait was interrupted. ++ */ ++VCOS_INLINE_DECL ++VCOS_STATUS_T vcos_event_wait(VCOS_EVENT_T *event); ++ ++/** ++ * Try event, but don't block. ++ * ++ * @param event The event to try ++ * @return VCOS_SUCCESS on success, VCOS_EAGAIN if the event is not currently signalled ++ */ ++VCOS_INLINE_DECL ++VCOS_STATUS_T vcos_event_try(VCOS_EVENT_T *event); ++ ++#endif ++ ++/* ++ * Destroy an event. ++ */ ++VCOS_INLINE_DECL ++void vcos_event_delete(VCOS_EVENT_T *event); ++ ++#ifdef __cplusplus ++} ++#endif ++ ++#endif ++ ++ +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_event_flags.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_event_flags.h 2013-07-26 19:32:00.000000000 +0000 +@@ -0,0 +1,98 @@ ++/*============================================================================= ++Copyright (c) 2009 Broadcom Europe Limited. ++All rights reserved. ++ ++Project : vcfw ++Module : chip driver ++ ++FILE DESCRIPTION ++VideoCore OS Abstraction Layer - public header file ++=============================================================================*/ ++ ++#ifndef VCOS_EVENT_FLAGS_H ++#define VCOS_EVENT_FLAGS_H ++ ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++#include "interface/vcos/vcos_types.h" ++#include "vcos_platform.h" ++ ++#define VCOS_EVENT_FLAGS_SUSPEND VCOS_SUSPEND ++#define VCOS_EVENT_FLAGS_NO_SUSPEND VCOS_NO_SUSPEND ++typedef VCOS_OPTION VCOS_EVENTGROUP_OPERATION_T; ++ ++/** ++ * \file vcos_event_flags.h ++ * ++ * Defines event flags API. ++ * ++ * Similar to Nucleus event groups. ++ * ++ * These have the same semantics as Nucleus event groups and ThreadX event ++ * flags. As such, they are quite complex internally; if speed is important ++ * they might not be your best choice. ++ * ++ */ ++ ++/** ++ * Create an event flags instance. ++ * ++ * @param flags Pointer to event flags instance, filled in on return. ++ * @param name Name for the event flags, used for debug. ++ * ++ * @return VCOS_SUCCESS if succeeded. ++ */ ++ ++VCOS_INLINE_DECL ++VCOS_STATUS_T vcos_event_flags_create(VCOS_EVENT_FLAGS_T *flags, const char *name); ++ ++/** ++ * Set some events. ++ * ++ * @param flags Instance to set flags on ++ * @param events Bitmask of the flags to actually set ++ * @param op How the flags should be set. VCOS_OR will OR in the flags; VCOS_AND ++ * will AND them in, possibly clearing existing flags. ++ */ ++VCOS_INLINE_DECL ++void vcos_event_flags_set(VCOS_EVENT_FLAGS_T *flags, ++ VCOS_UNSIGNED events, ++ VCOS_OPTION op); ++ ++/** ++ * Retrieve some events. ++ * ++ * Waits until the specified events have been set. ++ * ++ * @param flags Instance to wait on ++ * @param requested_events The bitmask to wait for ++ * @param op VCOS_OR - get any; VCOS_AND - get all. ++ * @param ms_suspend How long to wait, in milliseconds ++ * @param retrieved_events the events actually retrieved. ++ * ++ * @return VCOS_SUCCESS if events were retrieved. VCOS_EAGAIN if the ++ * timeout expired. ++ */ ++VCOS_INLINE_DECL ++VCOS_STATUS_T vcos_event_flags_get(VCOS_EVENT_FLAGS_T *flags, ++ VCOS_UNSIGNED requested_events, ++ VCOS_OPTION op, ++ VCOS_UNSIGNED ms_suspend, ++ VCOS_UNSIGNED *retrieved_events); ++ ++ ++/** ++ * Delete an event flags instance. ++ */ ++VCOS_INLINE_DECL ++void vcos_event_flags_delete(VCOS_EVENT_FLAGS_T *); ++ ++#ifdef __cplusplus ++} ++#endif ++ ++#endif ++ +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_init.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_init.h 2013-07-26 19:32:00.000000000 +0000 +@@ -0,0 +1,43 @@ ++/*============================================================================= ++Copyright (c) 2009 Broadcom Europe Limited. ++All rights reserved. ++ ++Project : vcfw ++Module : chip driver ++ ++FILE DESCRIPTION ++VideoCore OS Abstraction Layer - initialization routines ++=============================================================================*/ ++ ++ ++#include "interface/vcos/vcos_types.h" ++#include "vcos_platform.h" ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/** \file ++ * ++ * Some OS support libraries need some initialization. To support this, call this ++ * function at the start of day. ++ */ ++ ++VCOSPRE_ VCOS_STATUS_T VCOSPOST_ vcos_init(void); ++VCOSPRE_ void VCOSPOST_ vcos_deinit(void); ++VCOSPRE_ void VCOSPOST_ vcos_global_lock(void); ++VCOSPRE_ void VCOSPOST_ vcos_global_unlock(void); ++ ++/** Pass in the argv/argc arguments passed to main() */ ++VCOSPRE_ void VCOSPOST_ vcos_set_args(int argc, const char **argv); ++ ++/** Return argc. */ ++VCOSPRE_ int VCOSPOST_ vcos_get_argc(void); ++ ++/** Return argv. */ ++VCOSPRE_ const char ** VCOSPOST_ vcos_get_argv(void); ++ ++#ifdef __cplusplus ++} ++#endif ++ +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_logging.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_logging.h 2013-07-26 19:32:00.000000000 +0000 +@@ -0,0 +1,279 @@ ++/*============================================================================= ++Copyright (c) 2009-2011 Broadcom Europe Limited. ++All rights reserved. ++ ++Project : vcfw ++Module : chip driver ++ ++FILE DESCRIPTION ++VideoCore OS Abstraction Layer - logging support ++=============================================================================*/ ++ ++#ifndef VCOS_LOGGING_H ++#define VCOS_LOGGING_H ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++#include ++ ++#include "interface/vcos/vcos_types.h" ++#include "vcos_platform.h" ++ ++/** ++ * \file ++ * ++ * Logging support ++ * ++ * This provides categorised logging. Clients register ++ * a category, and then get a number of logging levels for ++ * that category. ++ * ++ * The logging level flag is tested using a flag *before* the ++ * function call, which makes logging very fast when disabled - there ++ * is no function call overhead just to find out that this log ++ * message is disabled. ++ * ++ * \section VCOS_LOG_CATEGORY ++ * ++ * As a convenience, clients define VCOS_LOG_CATEGORY to point to ++ * their category; the various vcos_log_xxx() macros then expand to ++ * use this. ++ * ++ * e.g. ++ * ++ * #define VCOS_LOG_CATEGORY (&my_category) ++ * ++ * #include ++ * ++ * VCOS_LOG_CAT_T my_category; ++ * ++ * .... ++ * ++ * vcos_log_trace("Stuff happened: %d", n_stuff); ++ * ++ */ ++ ++/** Logging levels */ ++typedef enum VCOS_LOG_LEVEL_T ++{ ++ VCOS_LOG_UNINITIALIZED = 0, ++ VCOS_LOG_NEVER, ++ VCOS_LOG_ERROR, ++ VCOS_LOG_WARN, ++ VCOS_LOG_INFO, ++ VCOS_LOG_TRACE, ++} VCOS_LOG_LEVEL_T; ++ ++ ++/** Initialize a logging category without going through vcos_log_register(). ++ * ++ * This is useful for the case where there is no obvious point to do the ++ * registration (no initialization function for the module). However, it ++ * means that your logging category is not registered, so cannot be easily ++ * changed at run-time. ++ */ ++#define VCOS_LOG_INIT(n,l) { l, n, 0, {0}, 0, 0 } ++ ++/** A registered logging category. ++ */ ++typedef struct VCOS_LOG_CAT_T ++{ ++ VCOS_LOG_LEVEL_T level; /** Which levels are enabled for this category */ ++ const char *name; /** Name for this category. */ ++ struct VCOS_LOG_CAT_T *next; ++ struct { ++ unsigned int want_prefix:1; ++ } flags; ++ unsigned int refcount; ++ void *platform_data; /** platform specific data */ ++} VCOS_LOG_CAT_T; ++ ++typedef void (*VCOS_VLOG_IMPL_FUNC_T)(const VCOS_LOG_CAT_T *cat, VCOS_LOG_LEVEL_T _level, const char *fmt, va_list args); ++ ++/** Convert a VCOS_LOG_LEVEL_T into a printable string. ++ * The platform needs to implement this function. ++ */ ++VCOSPRE_ const char * VCOSPOST_ vcos_log_level_to_string( VCOS_LOG_LEVEL_T level ); ++ ++/** Convert a string into a VCOS_LOG_LEVEL_T ++ * The platform needs to implement this function. ++ */ ++VCOSPRE_ VCOS_STATUS_T VCOSPOST_ vcos_string_to_log_level( const char *str, VCOS_LOG_LEVEL_T *level ); ++ ++/** Log a message. Basic API. Normal code should not use this. ++ * The platform needs to implement this function. ++ */ ++VCOSPRE_ void VCOSPOST_ vcos_log_impl(const VCOS_LOG_CAT_T *cat, VCOS_LOG_LEVEL_T _level, const char *fmt, ...) VCOS_FORMAT_ATTR_(printf, 3, 4); ++ ++/** Log a message using a varargs parameter list. Normal code should ++ * not use this. ++ */ ++VCOSPRE_ void VCOSPOST_ vcos_vlog_impl(const VCOS_LOG_CAT_T *cat, VCOS_LOG_LEVEL_T _level, const char *fmt, va_list args) VCOS_FORMAT_ATTR_(printf, 3, 0); ++ ++/** Set the function which does the actual logging output. ++ * Passing in NULL causes the default logging function to be ++ * used. ++ */ ++VCOSPRE_ void VCOSPOST_ vcos_set_vlog_impl( VCOS_VLOG_IMPL_FUNC_T vlog_impl_func ); ++ ++/** The default logging function, which is provided by each ++ * platform. ++ */ ++ ++VCOSPRE_ void VCOSPOST_ vcos_vlog_default_impl(const VCOS_LOG_CAT_T *cat, VCOS_LOG_LEVEL_T _level, const char *fmt, va_list args) VCOS_FORMAT_ATTR_(printf, 3, 0); ++ ++/* ++ * Initialise the logging subsystem. This is called from ++ * vcos_init() so you don't normally need to call it. ++ */ ++VCOSPRE_ void VCOSPOST_ vcos_logging_init(void); ++ ++/** Register a logging category. ++ * ++ * @param name the name of this category. ++ * @param category the category to register. ++ */ ++VCOSPRE_ void VCOSPOST_ vcos_log_register(const char *name, VCOS_LOG_CAT_T *category); ++ ++/** Unregister a logging category. ++ */ ++VCOSPRE_ void VCOSPOST_ vcos_log_unregister(VCOS_LOG_CAT_T *category); ++ ++/** Return a default logging category, for people too lazy to create their own. ++ * ++ * Using the default category will be slow (there's an extra function ++ * call overhead). Don't do this in normal code. ++ */ ++VCOSPRE_ const VCOS_LOG_CAT_T * VCOSPOST_ vcos_log_get_default_category(void); ++ ++VCOSPRE_ void VCOSPOST_ vcos_set_log_options(const char *opt); ++ ++/** Set the logging level for a category at run time. Without this, the level ++ * will be that set by vcos_log_register from a platform-specific source. ++ * ++ * @param category the category to modify. ++ * @param level the new logging level for this category. ++ */ ++VCOS_STATIC_INLINE void vcos_log_set_level(VCOS_LOG_CAT_T *category, VCOS_LOG_LEVEL_T level) ++{ ++ category->level = level; ++} ++ ++#define vcos_log_dump_mem(cat,label,addr,voidMem,numBytes) do { if (vcos_is_log_enabled(cat,VCOS_LOG_TRACE)) vcos_log_dump_mem_impl(cat,label,addr,voidMem,numBytes); } while (0) ++ ++void vcos_log_dump_mem_impl( const VCOS_LOG_CAT_T *cat, ++ const char *label, ++ uint32_t addr, ++ const void *voidMem, ++ size_t numBytes ); ++ ++/* ++ * Platform specific hooks (optional). ++ */ ++#ifndef vcos_log_platform_init ++#define vcos_log_platform_init() (void)0 ++#endif ++ ++#ifndef vcos_log_platform_register ++#define vcos_log_platform_register(category) (void)0 ++#endif ++ ++#ifndef vcos_log_platform_unregister ++#define vcos_log_platform_unregister(category) (void)0 ++#endif ++ ++/* VCOS_TRACE() - deprecated macro which just outputs in a debug build and ++ * is a no-op in a release build. ++ * ++ * _VCOS_LOG_X() - internal macro which outputs if the current level for the ++ * particular category is higher than the supplied message level. ++ */ ++ ++#define VCOS_LOG_DFLT_CATEGORY vcos_log_get_default_category() ++ ++#define _VCOS_LEVEL(x) (x) ++ ++#define vcos_is_log_enabled(cat,_level) (_VCOS_LEVEL((cat)->level) >= _VCOS_LEVEL(_level)) ++ ++#if defined(_VCOS_METAWARE) || defined(__GNUC__) ++ ++# if !defined(NDEBUG) || defined(VCOS_ALWAYS_WANT_LOGGING) ++# define VCOS_LOGGING_ENABLED ++# define _VCOS_LOG_X(cat, _level, fmt...) do { if (vcos_is_log_enabled(cat,_level)) vcos_log_impl(cat,_level,fmt); } while (0) ++# define _VCOS_VLOG_X(cat, _level, fmt, ap) do { if (vcos_is_log_enabled(cat,_level)) vcos_vlog_impl(cat,_level,fmt,ap); } while (0) ++# else ++# define _VCOS_LOG_X(cat, _level, fmt...) (void)0 ++# define _VCOS_VLOG_X(cat, _level, fmt, ap) (void)0 ++# endif ++ ++ ++ ++# define vcos_log_error(...) _VCOS_LOG_X(VCOS_LOG_CATEGORY, VCOS_LOG_ERROR, __VA_ARGS__) ++# define vcos_log_warn(...) _VCOS_LOG_X(VCOS_LOG_CATEGORY, VCOS_LOG_WARN, __VA_ARGS__) ++# define vcos_log_info(...) _VCOS_LOG_X(VCOS_LOG_CATEGORY, VCOS_LOG_INFO, __VA_ARGS__) ++# define vcos_log_trace(...) _VCOS_LOG_X(VCOS_LOG_CATEGORY, VCOS_LOG_TRACE, __VA_ARGS__) ++ ++# define vcos_vlog_error(fmt,ap) _VCOS_VLOG_X(VCOS_LOG_CATEGORY, VCOS_LOG_ERROR, fmt, ap) ++# define vcos_vlog_warn(fmt,ap) _VCOS_VLOG_X(VCOS_LOG_CATEGORY, VCOS_LOG_WARN, fmt, ap) ++# define vcos_vlog_info(fmt,ap) _VCOS_VLOG_X(VCOS_LOG_CATEGORY, VCOS_LOG_INFO, fmt, ap) ++# define vcos_vlog_trace(fmt,ap) _VCOS_VLOG_X(VCOS_LOG_CATEGORY, VCOS_LOG_TRACE, fmt, ap) ++ ++# define vcos_log(...) _VCOS_LOG_X(VCOS_LOG_DFLT_CATEGORY, VCOS_LOG_INFO, __VA_ARGS__) ++# define vcos_vlog(fmt,ap) _VCOS_VLOG_X(VCOS_LOG_DFLT_CATEGORY, VCOS_LOG_INFO, fmt, ap) ++# define VCOS_ALERT(...) _VCOS_LOG_X(VCOS_LOG_DFLT_CATEGORY, VCOS_LOG_ERROR, __VA_ARGS__) ++# define VCOS_TRACE(...) _VCOS_LOG_X(VCOS_LOG_DFLT_CATEGORY, VCOS_LOG_INFO, __VA_ARGS__) ++ ++/* ++ * MS Visual Studio - pre 2005 does not grok variadic macros ++ */ ++#elif defined(_MSC_VER) ++ ++# if _MSC_VER >= 1400 ++ ++# if !defined(NDEBUG) || defined(VCOS_ALWAYS_WANT_LOGGING) ++# define VCOS_LOGGING_ENABLED ++# define _VCOS_LOG_X(cat, _level, fmt,...) do { if (vcos_is_log_enabled(cat,_level)) vcos_log_impl(cat, _level, fmt, __VA_ARGS__); } while (0) ++# else ++# define _VCOS_LOG_X(cat, _level, fmt,...) (void)0 ++# endif ++ ++# define vcos_log_error(fmt,...) _VCOS_LOG_X(VCOS_LOG_CATEGORY, VCOS_LOG_ERROR, fmt, __VA_ARGS__) ++# define vcos_log_warn(fmt,...) _VCOS_LOG_X(VCOS_LOG_CATEGORY, VCOS_LOG_WARN, fmt, __VA_ARGS__) ++# define vcos_log_info(fmt,...) _VCOS_LOG_X(VCOS_LOG_CATEGORY, VCOS_LOG_INFO, fmt, __VA_ARGS__) ++# define vcos_log_trace(fmt,...) _VCOS_LOG_X(VCOS_LOG_CATEGORY, VCOS_LOG_TRACE, fmt, __VA_ARGS__) ++ ++# define vcos_log(fmt,...) _VCOS_LOG_X(VCOS_LOG_DFLT_CATEGORY, VCOS_LOG_INFO, fmt) ++# define VCOS_ALERT(fmt,...) _VCOS_LOG_X(VCOS_LOG_DFLT_CATEGORY, VCOS_LOG_ERROR, fmt) ++# define VCOS_TRACE(fmt,...) _VCOS_LOG_X(VCOS_LOG_DFLT_CATEGORY, VCOS_LOG_INFO, fmt) ++ ++# else /* _MSC_VER >= 1400 */ ++ ++/* do not define these */ ++ ++# endif /* _MSC_VER >= 1400 */ ++ ++#endif ++ ++#if VCOS_HAVE_CMD ++ ++#include "interface/vcos/vcos_cmd.h" ++ ++/* ++ * These are the log sub-commands. They're exported here for user-mode apps which ++ * may want to call these, since the "log" command isn't registered for user-mode ++ * apps (vcdbg for example, has its own log command). ++ */ ++VCOSPRE_ VCOS_STATUS_T VCOSPOST_ vcos_log_assert_cmd( VCOS_CMD_PARAM_T *param ); ++VCOSPRE_ VCOS_STATUS_T VCOSPOST_ vcos_log_set_cmd( VCOS_CMD_PARAM_T *param ); ++VCOSPRE_ VCOS_STATUS_T VCOSPOST_ vcos_log_status_cmd( VCOS_CMD_PARAM_T *param ); ++VCOSPRE_ VCOS_STATUS_T VCOSPOST_ vcos_log_test_cmd( VCOS_CMD_PARAM_T *param ); ++#endif ++ ++#ifdef __cplusplus ++} ++#endif ++#endif /* VCOS_LOGGING_H */ ++ ++ +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_lowlevel_thread.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_lowlevel_thread.h 2013-07-26 19:32:00.000000000 +0000 +@@ -0,0 +1,107 @@ ++/*============================================================================= ++Copyright (c) 2009 Broadcom Europe Limited. ++All rights reserved. ++ ++Project : vcfw ++Module : chip driver ++ ++FILE DESCRIPTION ++VideoCore OS Abstraction Layer - low level thread support ++=============================================================================*/ ++ ++#ifndef VCOS_LOWLEVEL_THREAD_H ++#define VCOS_LOWLEVEL_THREAD_H ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++#include "interface/vcos/vcos_types.h" ++#include "vcos_platform.h" ++ ++/** ++ * \file ++ * ++ * This defines a low level thread API that is supported by *some* operating systems ++ * and can be used to construct the regular "joinable thread" API on those operating ++ * systems. ++ * ++ * Most clients will not need to use this code. ++ * ++ * \sa vcos_joinable_thread.h ++ */ ++ ++/** ++ * \brief Create a thread. ++ * ++ * This creates a thread which can be stopped either by returning from the ++ * entry point function or by calling vcos_llthread_exit from within the entry ++ * point function. The thread must be cleaned up by calling ++ * vcos_llthread_delete. vcos_llthread_delete may or may not terminate the ++ * thread. ++ * ++ * The preemptible parameter familiar from Nucleus is removed, as it is unused in ++ * VideoCore code. Affinity is added, since we do use this. ++ * ++ * @param thread Filled in with thread instance ++ * @param name An optional name for the thread. "" may be used (but ++ * a name will aid in debugging). ++ * @param entry Entry point ++ * @param arg A single argument passed to the entry point function ++ * @param stack Pointer to stack address ++ * @param stacksz Size of stack in bytes ++ * @param priority Priority of task, between VCOS_PRI_LOW and VCOS_PRI_HIGH ++ * @param affinity CPU affinity ++ * ++ * @sa vcos_llthread_terminate vcos_llthread_delete ++ */ ++VCOSPRE_ VCOS_STATUS_T VCOSPOST_ vcos_llthread_create(VCOS_LLTHREAD_T *thread, ++ const char *name, ++ VCOS_LLTHREAD_ENTRY_FN_T entry, ++ void *arg, ++ void *stack, ++ VCOS_UNSIGNED stacksz, ++ VCOS_UNSIGNED priority, ++ VCOS_UNSIGNED affinity, ++ VCOS_UNSIGNED timeslice, ++ VCOS_UNSIGNED autostart); ++ ++/** ++ * \brief Exits the current thread. ++ */ ++VCOSPRE_ void VCOSPOST_ vcos_llthread_exit(void); ++ ++/** ++ * \brief Delete a thread. This must be called to cleanup after ++ * vcos_llthread_create. This may or may not terminate the thread. ++ * It does not clean up any resources that may have been ++ * allocated by the thread. ++ */ ++VCOSPRE_ void VCOSPOST_ vcos_llthread_delete(VCOS_LLTHREAD_T *thread); ++ ++/** ++ * \brief Return current lowlevel thread pointer. ++ */ ++VCOS_INLINE_DECL ++VCOS_LLTHREAD_T *vcos_llthread_current(void); ++ ++/** ++ * Resume a thread. ++ */ ++VCOS_INLINE_DECL ++void vcos_llthread_resume(VCOS_LLTHREAD_T *thread); ++ ++VCOSPRE_ int VCOSPOST_ vcos_llthread_running(VCOS_LLTHREAD_T *thread); ++ ++/** ++ * \brief Create a VCOS_LLTHREAD_T for the current thread. This is so we can ++ * have VCOS_LLTHREAD_Ts even for threads not originally created by VCOS (eg ++ * the thread that calls vcos_init). ++ */ ++extern VCOS_STATUS_T _vcos_llthread_create_attach(VCOS_LLTHREAD_T *thread); ++ ++#ifdef __cplusplus ++} ++#endif ++#endif ++ +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_mem.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_mem.h 2013-07-26 19:32:00.000000000 +0000 +@@ -0,0 +1,81 @@ ++/*============================================================================= ++Copyright (c) 2009 Broadcom Europe Limited. ++All rights reserved. ++ ++Project : vcfw ++Module : chip driver ++ ++FILE DESCRIPTION ++VideoCore OS Abstraction Layer - memory support ++=============================================================================*/ ++ ++#ifndef VCOS_MEM_H ++#define VCOS_MEM_H ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++#include "interface/vcos/vcos_types.h" ++#include "vcos_platform.h" ++ ++/** \file ++ * ++ * Memory allocation api (malloc/free equivalents) is for benefit of host ++ * applications. VideoCore code should use rtos_XXX functions. ++ * ++ */ ++ ++ ++/** Allocate memory ++ * ++ * @param size Size of memory to allocate ++ * @param description Description, to aid in debugging. May be ignored internally on some platforms. ++ */ ++VCOS_INLINE_DECL ++void *vcos_malloc(VCOS_UNSIGNED size, const char *description); ++ ++void *vcos_kmalloc(VCOS_UNSIGNED size, const char *description); ++void *vcos_kcalloc(VCOS_UNSIGNED num, VCOS_UNSIGNED size, const char *description); ++ ++/** Allocate cleared memory ++ * ++ * @param num Number of items to allocate. ++ * @param size Size of each item in bytes. ++ * @param description Description, to aid in debugging. May be ignored internally on some platforms. ++ */ ++VCOS_INLINE_DECL ++void *vcos_calloc(VCOS_UNSIGNED num, VCOS_UNSIGNED size, const char *description); ++ ++/** Free memory ++ * ++ * Free memory that has been allocated. ++ */ ++VCOS_INLINE_DECL ++void vcos_free(void *ptr); ++ ++void vcos_kfree(void *ptr); ++ ++/** Allocate aligned memory ++ * ++ * Allocate memory aligned on the specified boundary. ++ * ++ * @param size Size of memory to allocate ++ * @param description Description, to aid in debugging. May be ignored internally on some platforms. ++ */ ++VCOS_INLINE_DECL ++void *vcos_malloc_aligned(VCOS_UNSIGNED size, VCOS_UNSIGNED align, const char *description); ++ ++/** Return the amount of free heap memory ++ * ++ */ ++VCOS_INLINE_DECL ++unsigned long vcos_get_free_mem(void); ++ ++#ifdef __cplusplus ++} ++#endif ++ ++#endif ++ ++ +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_msgqueue.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_msgqueue.h 2013-07-26 19:32:00.000000000 +0000 +@@ -0,0 +1,157 @@ ++/*============================================================================= ++Copyright (c) 2009 Broadcom Europe Limited. ++All rights reserved. ++ ++Project : vcfw ++Module : chip driver ++ ++FILE DESCRIPTION ++VCOS - packet-like messages, based loosely on those found in TRIPOS. ++=============================================================================*/ ++ ++#ifndef VCOS_MSGQUEUE_H ++#define VCOS_MSGQUEUE_H ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++#include "interface/vcos/vcos_types.h" ++#include "vcos_platform.h" ++ ++/** ++ * \file ++ * ++ * Packet-like messages, based loosely on those found in TRIPOS and ++ * derivatives thereof. ++ * ++ * A task can send a message *pointer* to another task, where it is ++ * queued on a linked list and the task woken up. The receiving task ++ * consumes all of the messages on its input queue, and optionally ++ * sends back replies using the original message memory. ++ * ++ * A caller can wait for the reply to a specific message - any other ++ * messages that arrive in the meantime are queued separately. ++ * ++ * ++ * All messages have a standard common layout, but the payload area can ++ * be used freely to extend this. ++ */ ++ ++/** Map the payload portion of a message to a structure pointer. ++ */ ++#define VCOS_MSG_DATA(_msg) (void*)((_msg)->data) ++ ++/** Standard message ids - FIXME - these need to be done properly! */ ++#define VCOS_MSG_N_QUIT 1 ++#define VCOS_MSG_N_OPEN 2 ++#define VCOS_MSG_N_CLOSE 3 ++#define VCOS_MSG_N_PRIVATE (1<<20) ++ ++#define VCOS_MSG_REPLY_BIT (1<<31) ++ ++/** Make gnuc compiler be happy about pointer punning */ ++#ifdef __GNUC__ ++#define __VCOS_MAY_ALIAS __attribute__((__may_alias__)) ++#else ++#define __VCOS_MAY_ALIAS ++#endif ++ ++/** A single message queue. ++ */ ++typedef struct VCOS_MSGQUEUE_T ++{ ++ struct VCOS_MSG_T *head; /**< head of linked list of messages waiting on this queue */ ++ struct VCOS_MSG_T *tail; /**< tail of message queue */ ++ VCOS_SEMAPHORE_T sem; /**< thread waits on this for new messages */ ++ VCOS_MUTEX_T lock; /**< locks the messages list */ ++} VCOS_MSGQUEUE_T; ++ ++/** A single message ++ */ ++typedef struct VCOS_MSG_T ++{ ++ uint32_t code; /**< message code */ ++ int error; /**< error status signalled back to caller */ ++ VCOS_MSGQUEUE_T *dst; /**< destination queue */ ++ VCOS_MSGQUEUE_T *src; /**< source; replies go back to here */ ++ struct VCOS_MSG_T *next; /**< next in queue */ ++ VCOS_THREAD_T *src_thread; /**< for debug */ ++ uint32_t data[25]; /**< payload area */ ++} VCOS_MSG_T; ++ ++/** An endpoint ++ */ ++typedef struct VCOS_MSG_ENDPOINT_T ++{ ++ VCOS_MSGQUEUE_T primary; /**< incoming messages */ ++ VCOS_MSGQUEUE_T secondary; /**< this is used for waitspecific */ ++ char name[32]; /**< name of this endpoint, for find() */ ++ struct VCOS_MSG_ENDPOINT_T *next; /**< next in global list of endpoints */ ++} VCOS_MSG_ENDPOINT_T; ++#define MSG_REPLY_BIT (1<<31) ++ ++/** Initalise the library. Normally called from vcos_init(). ++ */ ++extern VCOS_STATUS_T vcos_msgq_init(void); ++ ++/** Find a message queue by name and get a handle to it. ++ * ++ * @param name the name of the queue to find ++ * ++ * @return The message queue, or NULL if not found. ++ */ ++VCOSPRE_ VCOS_MSGQUEUE_T VCOSPOST_ *vcos_msgq_find(const char *name); ++ ++/** Wait for a message queue to come into existence. If it already exists, ++ * return immediately, otherwise block. ++ * ++ * On the whole, if you find yourself using this, it is probably a sign ++ * of poor design, since you should create all the server threads first, ++ * and then the client threads. But it is sometimes useful. ++ * ++ * @param name the name of the queue to find ++ * @return The message queue ++ */ ++VCOSPRE_ VCOS_MSGQUEUE_T VCOSPOST_ *vcos_msgq_wait(const char *name); ++ ++/** Send a message. ++ */ ++VCOSPRE_ void VCOSPOST_ vcos_msg_send(VCOS_MSGQUEUE_T *dest, uint32_t code, VCOS_MSG_T *msg); ++ ++/** Send a message and wait for a reply. ++ */ ++VCOSPRE_ void VCOSPOST_ vcos_msg_sendwait(VCOS_MSGQUEUE_T *queue, uint32_t code, VCOS_MSG_T *msg); ++ ++/** Wait for a message on this thread's endpoint. ++ */ ++VCOSPRE_ VCOS_MSG_T * VCOSPOST_ vcos_msg_wait(void); ++ ++/** Wait for a specific message. ++ */ ++VCOS_MSG_T * vcos_msg_wait_specific(VCOS_MSGQUEUE_T *queue, VCOS_MSG_T *msg); ++ ++/** Peek for a message on this thread's endpoint, if a message is not available, NULL is ++ returned. If a message is available it will be removed from the endpoint and returned. ++ */ ++VCOSPRE_ VCOS_MSG_T * VCOSPOST_ vcos_msg_peek(void); ++ ++/** Send a reply to a message ++ */ ++VCOSPRE_ void VCOSPOST_ vcos_msg_reply(VCOS_MSG_T *msg); ++ ++/** Create an endpoint. Each thread should need no more than one of these - if you ++ * find yourself needing a second one, you've done something wrong. ++ */ ++VCOSPRE_ VCOS_STATUS_T VCOSPOST_ vcos_msgq_endpoint_create(VCOS_MSG_ENDPOINT_T *ep, const char *name); ++ ++/** Destroy an endpoint. ++ */ ++VCOSPRE_ void VCOSPOST_ vcos_msgq_endpoint_delete(VCOS_MSG_ENDPOINT_T *ep); ++ ++#ifdef __cplusplus ++} ++#endif ++#endif ++ ++ +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_mutex.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_mutex.h 2013-07-26 19:32:00.000000000 +0000 +@@ -0,0 +1,92 @@ ++/*============================================================================= ++Copyright (c) 2009 Broadcom Europe Limited. ++All rights reserved. ++ ++Project : vcfw ++Module : chip driver ++ ++FILE DESCRIPTION ++VideoCore OS Abstraction Layer - mutex public header file ++=============================================================================*/ ++ ++#ifndef VCOS_MUTEX_H ++#define VCOS_MUTEX_H ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++#include "interface/vcos/vcos_types.h" ++#include "vcos_platform.h" ++ ++/** ++ * \file vcos_mutex.h ++ * ++ * Mutex API. Mutexes are not re-entrant, as supporting this adds extra code ++ * that slows down clients which have been written sensibly. ++ * ++ * \sa vcos_reentrant_mutex.h ++ * ++ */ ++ ++/** Create a mutex. ++ * ++ * @param m Filled in with mutex on return ++ * @param name A non-null name for the mutex, used for diagnostics. ++ * ++ * @return VCOS_SUCCESS if mutex was created, or error code. ++ */ ++VCOS_INLINE_DECL ++VCOS_STATUS_T vcos_mutex_create(VCOS_MUTEX_T *m, const char *name); ++ ++/** Delete the mutex. ++ */ ++VCOS_INLINE_DECL ++void vcos_mutex_delete(VCOS_MUTEX_T *m); ++ ++/** ++ * \brief Wait to claim the mutex. ++ * ++ * On most platforms this always returns VCOS_SUCCESS, and so would ideally be ++ * a void function, however some platforms allow a wait to be interrupted so ++ * it remains non-void. ++ * ++ * Try to obtain the mutex. ++ * @param m Mutex to wait on ++ * @return VCOS_SUCCESS - mutex was taken. ++ * VCOS_EAGAIN - could not take mutex. ++ */ ++#ifndef vcos_mutex_lock ++VCOS_INLINE_DECL ++VCOS_STATUS_T vcos_mutex_lock(VCOS_MUTEX_T *m); ++ ++/** Release the mutex. ++ */ ++VCOS_INLINE_DECL ++void vcos_mutex_unlock(VCOS_MUTEX_T *m); ++#endif ++ ++/** Test if the mutex is already locked. ++ * ++ * @return 1 if mutex is locked, 0 if it is unlocked. ++ */ ++VCOS_INLINE_DECL ++int vcos_mutex_is_locked(VCOS_MUTEX_T *m); ++ ++/** Obtain the mutex if possible. ++ * ++ * @param m the mutex to try to obtain ++ * ++ * @return VCOS_SUCCESS if mutex is succesfully obtained, or VCOS_EAGAIN ++ * if it is already in use by another thread. ++ */ ++#ifndef vcos_mutex_trylock ++VCOS_INLINE_DECL ++VCOS_STATUS_T vcos_mutex_trylock(VCOS_MUTEX_T *m); ++#endif ++ ++ ++#ifdef __cplusplus ++} ++#endif ++#endif +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_once.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_once.h 2013-07-26 19:32:00.000000000 +0000 +@@ -0,0 +1,42 @@ ++/*============================================================================= ++Copyright (c) 2011 Broadcom Europe Limited. ++All rights reserved. ++ ++Project : vcfw ++Module : chip driver ++ ++FILE DESCRIPTION ++VideoCore OS Abstraction Layer - 'once' ++=============================================================================*/ ++ ++#ifndef VCOS_ONCE_H ++#define VCOS_ONCE_H ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++#include "interface/vcos/vcos_types.h" ++#include "vcos_platform.h" ++ ++/** ++ * \file vcos_once.h ++ * ++ * Ensure something is called only once. ++ * ++ * Initialize once_control to VCOS_ONCE_INIT. The first ++ * time this is called, the init_routine will be called. Thereafter ++ * it won't. ++ * ++ * \sa pthread_once() ++ * ++ */ ++ ++VCOS_STATUS_T vcos_once(VCOS_ONCE_T *once_control, ++ void (*init_routine)(void)); ++ ++#ifdef __cplusplus ++} ++#endif ++#endif ++ +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_semaphore.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_semaphore.h 2013-07-26 19:32:00.000000000 +0000 +@@ -0,0 +1,115 @@ ++/*============================================================================= ++Copyright (c) 2009 Broadcom Europe Limited. ++All rights reserved. ++ ++Project : vcfw ++Module : chip driver ++ ++FILE DESCRIPTION ++VideoCore OS Abstraction Layer - public header file ++=============================================================================*/ ++ ++#ifndef VCOS_SEMAPHORE_H ++#define VCOS_SEMAPHORE_H ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++#include "interface/vcos/vcos_types.h" ++#include "vcos_platform.h" ++ ++/** ++ * \file vcos_semaphore.h ++ * ++ * \section sem Semaphores ++ * ++ * This provides counting semaphores. Semaphores are not re-entrant. On sensible ++ * operating systems a semaphore can always be posted but can only be taken in ++ * thread (not interrupt) context. Under Nucleus, a LISR cannot post a semaphore, ++ * although it would not be hard to lift this restriction. ++ * ++ * \subsection timeout Timeout ++ * ++ * On both Nucleus and ThreadX a semaphore can be taken with a timeout. This is ++ * not supported by VCOS because it makes the non-timeout code considerably more ++ * complicated (and hence slower). In the unlikely event that you need a timeout ++ * with a semaphore, and you cannot simply redesign your code to avoid it, use ++ * an event flag (vcos_event_flags.h). ++ * ++ * \subsection sem_nucleus Changes from Nucleus: ++ * ++ * Semaphores are always "FIFO" - i.e. sleeping threads are woken in FIFO order. That's ++ * because: ++ * \arg there's no support for NU_PRIORITY in threadx (though it can be emulated, slowly) ++ * \arg we don't appear to actually consciously use it - for example, Dispmanx uses ++ * it, but all threads waiting are the same priority. ++ * ++ */ ++ ++/** ++ * \brief Create a semaphore. ++ * ++ * Create a semaphore. ++ * ++ * @param sem Pointer to memory to be initialized ++ * @param name A name for this semaphore. The name may be truncated internally. ++ * @param count The initial count for the semaphore. ++ * ++ * @return VCOS_SUCCESS if the semaphore was created. ++ * ++ */ ++VCOS_INLINE_DECL ++VCOS_STATUS_T vcos_semaphore_create(VCOS_SEMAPHORE_T *sem, const char *name, VCOS_UNSIGNED count); ++ ++/** ++ * \brief Wait on a semaphore. ++ * ++ * There is no timeout option on a semaphore, as adding this will slow down ++ * implementations on some platforms. If you need that kind of behaviour, use ++ * an event group. ++ * ++ * On most platforms this always returns VCOS_SUCCESS, and so would ideally be ++ * a void function, however some platforms allow a wait to be interrupted so ++ * it remains non-void. ++ * ++ * @param sem Semaphore to wait on ++ * @return VCOS_SUCCESS - semaphore was taken. ++ * VCOS_EAGAIN - could not take semaphore ++ * ++ */ ++VCOS_INLINE_DECL ++VCOS_STATUS_T vcos_semaphore_wait(VCOS_SEMAPHORE_T *sem); ++ ++/** ++ * \brief Try to wait for a semaphore. ++ * ++ * Try to obtain the semaphore. If it is already taken, return VCOS_TIMEOUT. ++ * @param sem Semaphore to wait on ++ * @return VCOS_SUCCESS - semaphore was taken. ++ * VCOS_EAGAIN - could not take semaphore ++ */ ++VCOS_INLINE_DECL ++VCOS_STATUS_T vcos_semaphore_trywait(VCOS_SEMAPHORE_T *sem); ++ ++/** ++ * \brief Post a semaphore. ++ * ++ * @param sem Semaphore to wait on ++ */ ++VCOS_INLINE_DECL ++VCOS_STATUS_T vcos_semaphore_post(VCOS_SEMAPHORE_T *sem); ++ ++/** ++ * \brief Delete a semaphore, releasing any resources consumed by it. ++ * ++ * @param sem Semaphore to wait on ++ */ ++VCOS_INLINE_DECL ++void vcos_semaphore_delete(VCOS_SEMAPHORE_T *sem); ++ ++#ifdef __cplusplus ++} ++#endif ++#endif ++ +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_stdbool.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_stdbool.h 2013-07-26 19:32:00.000000000 +0000 +@@ -0,0 +1,17 @@ ++#ifndef VCOS_STDBOOL_H ++#define VCOS_STDBOOL_H ++ ++#ifndef __cplusplus ++ ++#if defined(__STDC__) && (__STDC_VERSION__ >= 199901L) ++#include ++#else ++typedef enum { ++ false, ++ true ++} bool; ++#endif ++ ++#endif /* __cplusplus */ ++ ++#endif +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_stdint.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_stdint.h 2013-07-26 19:32:00.000000000 +0000 +@@ -0,0 +1,193 @@ ++/*============================================================================= ++Copyright (c) 2011 Broadcom Europe Limited. ++All rights reserved. ++ ++FILE DESCRIPTION ++ ++=============================================================================*/ ++ ++#ifndef VCOS_STDINT_H ++#define VCOS_STDINT_H ++ ++/* Attempt to provide the types defined in stdint.h. ++ * ++ * Ideally this would either call out to a platform-specific ++ * header file (e.g. stdint.h) or define the types on a ++ * per-architecture/compiler basis. But for now we just ++ * use #ifdefs. ++ */ ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++#ifdef __SYMBIAN32__ ++ ++typedef signed char int8_t; ++typedef unsigned char uint8_t; ++ ++typedef signed short int16_t; ++typedef unsigned short uint16_t; ++ ++typedef int16_t int_least16_t; ++ ++typedef signed long int32_t; ++typedef unsigned long uint32_t; ++ ++typedef signed long long int64_t; ++typedef unsigned long long uint64_t; ++ ++typedef int32_t intptr_t; ++typedef uint32_t uintptr_t; ++ ++typedef int64_t intmax_t; ++typedef uint64_t uintmax_t; ++ ++#define INT8_MIN SCHAR_MIN ++#define INT8_MAX SCHAR_MAX ++#define UINT8_MAX UCHAR_MAX ++#define INT16_MIN SHRT_MIN ++#define INT16_MAX SHRT_MAX ++#define UINT16_MAX USHRT_MAX ++#define INT32_MIN LONG_MIN ++#define INT32_MAX LONG_MAX ++#define UINT32_MAX ULONG_MAX ++#define INT64_MIN LLONG_MIN ++#define INT64_MAX LLONG_MAX ++#define UINT64_MAX ULLONG_MAX ++ ++#define INTPTR_MIN INT32_MIN ++#define INTPTR_MAX INT32_MAX ++#define UINTPTR_MAX UINT32_MAX ++#define INTMAX_MIN INT64_MIN ++#define INTMAX_MAX INT64_MAX ++#define INT_LEAST16_MAX INT16_MAX ++#define INT_LEAST16_MAX INT16_MAX ++ ++/*{{{ C99 types - THIS WHOLE SECTION IS INCOMPATIBLE WITH C99. IT SHOULD RESIDE IN A STDINT.H SINCE THIS FILE GETS USED ON HOST SIDE */ ++ ++#elif defined( __STDC__ ) && __STDC_VERSION__ >= 199901L ++ ++#include ++ ++#elif defined( __GNUC__ ) ++ ++#include ++ ++#elif defined(_MSC_VER) /* Visual C define equivalent types */ ++ ++#include /* Avoids intptr_t being defined in vadefs.h */ ++ ++typedef __int8 int8_t; ++typedef unsigned __int8 uint8_t; ++ ++typedef __int16 int16_t; ++typedef unsigned __int16 uint16_t; ++ ++typedef __int32 int32_t; ++typedef unsigned __int32 uint32_t; ++ ++typedef __int64 int64_t; ++typedef unsigned __int64 uint64_t; ++typedef uint32_t uintptr_t; ++typedef int64_t intmax_t; ++typedef uint64_t uintmax_t; ++typedef int16_t int_least16_t; ++ ++#elif defined (VCMODS_LCC) ++#include ++ ++typedef signed char int8_t; ++typedef unsigned char uint8_t; ++ ++typedef signed short int16_t; ++typedef unsigned short uint16_t; ++ ++typedef signed long int32_t; ++typedef unsigned long uint32_t; ++ ++typedef signed long int64_t; /*!!!! PFCD, this means code using 64bit numbers will be broken on the VCE */ ++typedef unsigned long uint64_t; /* !!!! PFCD */ ++ ++typedef int32_t intptr_t; ++typedef uint32_t uintptr_t; ++typedef int64_t intmax_t; ++typedef uint64_t uintmax_t; ++typedef int16_t int_least16_t; ++ ++#define INT8_MIN SCHAR_MIN ++#define INT8_MAX SCHAR_MAX ++#define UINT8_MAX UCHAR_MAX ++#define INT16_MIN SHRT_MIN ++#define INT16_MAX SHRT_MAX ++#define UINT16_MAX USHRT_MAX ++#define INT32_MIN LONG_MIN ++#define INT32_MAX LONG_MAX ++#define UINT32_MAX ULONG_MAX ++#define INT64_MIN LONG_MIN /* !!!! PFCD */ ++#define INT64_MAX LONG_MAX /* !!!! PFCD */ ++#define UINT64_MAX ULONG_MAX /* !!!! PFCD */ ++ ++#define INTPTR_MIN INT32_MIN ++#define INTPTR_MAX INT32_MAX ++#define UINTPTR_MAX UINT32_MAX ++#define INTMAX_MIN INT64_MIN ++#define INTMAX_MIN INT64_MIN ++#define INT_LEAST16_MAX INT16_MAX ++#define INT_LEAST16_MAX INT16_MAX ++ ++#elif defined(__VIDEOCORE__) ++ ++typedef signed char int8_t; ++typedef unsigned char uint8_t; ++ ++typedef signed short int16_t; ++typedef unsigned short uint16_t; ++ ++typedef signed long int32_t; ++typedef unsigned long uint32_t; ++ ++typedef signed long long int64_t; ++typedef unsigned long long uint64_t; ++ ++typedef int32_t intptr_t; ++typedef uint32_t uintptr_t; ++typedef int64_t intmax_t; ++typedef uint64_t uintmax_t; ++typedef int16_t int_least16_t; ++ ++#define INT8_MIN SCHAR_MIN ++#define INT8_MAX SCHAR_MAX ++#define UINT8_MAX UCHAR_MAX ++#define INT16_MIN SHRT_MIN ++#define INT16_MAX SHRT_MAX ++#define UINT16_MAX USHRT_MAX ++#define INT32_MIN LONG_MIN ++#define INT32_MAX LONG_MAX ++#define UINT32_MAX ULONG_MAX ++#define INT64_MIN LLONG_MIN ++#define INT64_MAX LLONG_MAX ++#define UINT64_MAX ULLONG_MAX ++ ++#define INTPTR_MIN INT32_MIN ++#define INTPTR_MAX INT32_MAX ++#define UINTPTR_MAX UINT32_MAX ++#define INTMAX_MIN INT64_MIN ++#define INTMAX_MAX INT64_MAX ++#define INT_LEAST16_MAX INT16_MAX ++#define INT_LEAST16_MAX INT16_MAX ++ ++#elif defined (__HIGHC__) && defined(_I386) ++ ++#include ++ ++#else ++#error Unknown platform ++#endif ++ ++#ifdef __cplusplus ++} ++#endif ++#endif /* VCOS_STDINT_H */ ++ ++ +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_string.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_string.h 2013-07-26 19:32:00.000000000 +0000 +@@ -0,0 +1,73 @@ ++/*============================================================================= ++Copyright (c) 2009 Broadcom Europe Limited. ++All rights reserved. ++ ++Project : vcfw ++Module : chip driver ++ ++FILE DESCRIPTION ++VideoCore OS Abstraction Layer - public header file ++=============================================================================*/ ++ ++#ifndef VCOS_STRING_H ++#define VCOS_STRING_H ++ ++/** ++ * \file ++ * ++ * String functions. ++ * ++ */ ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++#include "interface/vcos/vcos_types.h" ++#include "vcos_platform.h" ++ ++#ifdef __KERNEL__ ++#include ++#else ++#include ++#endif ++ ++/** Case insensitive string comparison. ++ * ++ */ ++ ++VCOS_INLINE_DECL ++int vcos_strcasecmp(const char *s1, const char *s2); ++ ++VCOS_INLINE_DECL ++int vcos_strncasecmp(const char *s1, const char *s2, size_t n); ++ ++VCOSPRE_ int VCOSPOST_ vcos_vsnprintf( char *buf, size_t buflen, const char *fmt, va_list ap ); ++ ++VCOSPRE_ int VCOSPOST_ vcos_snprintf(char *buf, size_t buflen, const char *fmt, ...); ++ ++VCOS_STATIC_INLINE ++int vcos_strlen(const char *s) { return (int)strlen(s); } ++ ++VCOS_STATIC_INLINE ++int vcos_strcmp(const char *s1, const char *s2) { return strcmp(s1,s2); } ++ ++VCOS_STATIC_INLINE ++int vcos_strncmp(const char *cs, const char *ct, size_t count) { return strncmp(cs, ct, count); } ++ ++VCOS_STATIC_INLINE ++char *vcos_strcpy(char *dst, const char *src) { return strcpy(dst, src); } ++ ++VCOS_STATIC_INLINE ++char *vcos_strncpy(char *dst, const char *src, size_t count) { return strncpy(dst, src, count); } ++ ++VCOS_STATIC_INLINE ++void *vcos_memcpy(void *dst, const void *src, size_t n) { memcpy(dst, src, n); return dst; } ++ ++VCOS_STATIC_INLINE ++void *vcos_memset(void *p, int c, size_t n) { return memset(p, c, n); } ++ ++#ifdef __cplusplus ++} ++#endif ++#endif +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_thread.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_thread.h 2013-07-26 19:32:00.000000000 +0000 +@@ -0,0 +1,259 @@ ++/*============================================================================= ++Copyright (c) 2009 Broadcom Europe Limited. ++All rights reserved. ++ ++Project : vcfw ++Module : chip driver ++ ++FILE DESCRIPTION ++VideoCore OS Abstraction Layer - public header file ++=============================================================================*/ ++ ++#ifndef VCOS_THREAD_H ++#define VCOS_THREAD_H ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++#include "interface/vcos/vcos_types.h" ++#include "vcos_platform.h" ++ ++/** ++ * \file vcos_thread.h ++ * ++ * \section thread Threads ++ * ++ * Under Nucleus, a thread is created by NU_Create_Task, passing in the stack ++ * and various other parameters. To stop the thread, NU_Terminate_Thread() and ++ * NU_Delete_Thread() are called. ++ * ++ * Unfortunately it's not possible to emulate this API under some fairly common ++ * operating systems. Under Windows you can't pass in the stack, and you can't ++ * safely terminate a thread. ++ * ++ * Therefore, an API which is similar to the pthreads API is used instead. This ++ * API can (mostly) be emulated under all interesting operating systems. ++ * ++ * Obviously this makes the code somewhat more complicated on VideoCore than it ++ * would otherwise be - we end up with an extra mutex per thread, and some code ++ * that waits for it. The benefit is that we have a single way of creating ++ * threads that works consistently on all platforms (apart from stack supplying). ++ * ++ * \subsection stack Stack ++ * ++ * It's still not possible to pass in the stack address, but this can be made ++ * much more obvious in the API: the relevant function is missing and the ++ * CPP symbol VCOS_CAN_SET_STACK_ADDR is zero rather than one. ++ * ++ * \subsection thr_create Creating a thread ++ * ++ * The simplest way to create a thread is with vcos_thread_create() passing in a ++ * NULL thread parameter argument. To wait for the thread to exit, call ++ * vcos_thread_join(). ++ * ++ * \subsection back Backward compatibility ++ * ++ * To ease migration, a "classic" thread creation API is provided for code ++ * that used to make use of Nucleus, vcos_thread_create_classic(). The ++ * arguments are not exactly the same, as the PREEMPT parameter is dropped. ++ * ++ */ ++ ++#define VCOS_AFFINITY_CPU0 _VCOS_AFFINITY_CPU0 ++#define VCOS_AFFINITY_CPU1 _VCOS_AFFINITY_CPU1 ++#define VCOS_AFFINITY_MASK _VCOS_AFFINITY_MASK ++#define VCOS_AFFINITY_DEFAULT _VCOS_AFFINITY_DEFAULT ++#define VCOS_AFFINITY_THISCPU _VCOS_AFFINITY_THISCPU ++ ++/** Report whether or not we have an RTOS at all, and hence the ability to ++ * create threads. ++ */ ++VCOSPRE_ int VCOSPOST_ vcos_have_rtos(void); ++ ++/** Create a thread. It must be cleaned up by calling vcos_thread_join(). ++ * ++ * @param thread Filled in on return with thread ++ * @param name A name for the thread. May be the empty string. ++ * @param attrs Attributes; default attributes will be used if this is NULL. ++ * @param entry Entry point. ++ * @param arg Argument passed to the entry point. ++ */ ++VCOSPRE_ VCOS_STATUS_T VCOSPOST_ vcos_thread_create(VCOS_THREAD_T *thread, ++ const char *name, ++ VCOS_THREAD_ATTR_T *attrs, ++ VCOS_THREAD_ENTRY_FN_T entry, ++ void *arg); ++ ++/** Exit the thread from within the thread function itself. ++ * Resources must still be cleaned up via a call to thread_join(). ++ * ++ * The thread can also be terminated by simply exiting the thread function. ++ * ++ * @param data Data passed to thread_join. May be NULL. ++ */ ++VCOSPRE_ void VCOSPOST_ vcos_thread_exit(void *data); ++ ++/** Wait for a thread to terminate and then clean up its resources. ++ * ++ * @param thread Thread to wait for ++ * @param pData Updated to point at data provided in vcos_thread_exit or exit ++ * code of thread function. ++ */ ++VCOSPRE_ void VCOSPOST_ vcos_thread_join(VCOS_THREAD_T *thread, ++ void **pData); ++ ++ ++/** ++ * \brief Create a thread using an API similar to the one "traditionally" ++ * used under Nucleus. ++ * ++ * This creates a thread which must be cleaned up by calling vcos_thread_join(). ++ * The thread cannot be simply terminated (as in Nucleus and ThreadX) as thread ++ * termination is not universally supported. ++ * ++ * @param thread Filled in with thread instance ++ * @param name An optional name for the thread. NULL or "" may be used (but ++ * a name will aid in debugging). ++ * @param entry Entry point ++ * @param arg A single argument passed to the entry point function ++ * @param stack Pointer to stack address ++ * @param stacksz Size of stack in bytes ++ * @param priaff Priority of task, between VCOS_PRI_LOW and VCOS_PRI_HIGH, ORed with the CPU affinity ++ * @param autostart If non-zero the thread will start immediately. ++ * @param timeslice Timeslice (system ticks) for this thread. ++ * ++ * @sa vcos_thread_terminate vcos_thread_delete ++ */ ++VCOSPRE_ VCOS_STATUS_T VCOSPOST_ vcos_thread_create_classic(VCOS_THREAD_T *thread, ++ const char *name, ++ void *(*entry)(void *arg), ++ void *arg, ++ void *stack, ++ VCOS_UNSIGNED stacksz, ++ VCOS_UNSIGNED priaff, ++ VCOS_UNSIGNED timeslice, ++ VCOS_UNSIGNED autostart); ++ ++/** ++ * \brief Set a thread's priority ++ * ++ * Set the priority for a thread. ++ * ++ * @param thread The thread ++ * @param pri Thread priority in VCOS_PRI_MASK bits; affinity in VCOS_AFFINITY_MASK bits. ++ */ ++VCOS_INLINE_DECL ++void vcos_thread_set_priority(VCOS_THREAD_T *thread, VCOS_UNSIGNED pri); ++ ++/** ++ * \brief Return the currently executing thread. ++ * ++ */ ++VCOS_INLINE_DECL ++VCOS_THREAD_T *vcos_thread_current(void); ++ ++/** ++ * \brief Return the thread's priority. ++ */ ++VCOS_INLINE_DECL ++VCOS_UNSIGNED vcos_thread_get_priority(VCOS_THREAD_T *thread); ++ ++/** ++ * \brief Return the thread's cpu affinity. ++ */ ++VCOS_INLINE_DECL ++VCOS_UNSIGNED vcos_thread_get_affinity(VCOS_THREAD_T *thread); ++ ++/** ++ * \brief Set the thread's cpu affinity. ++ */ ++ ++VCOS_INLINE_DECL ++void vcos_thread_set_affinity(VCOS_THREAD_T *thread, VCOS_UNSIGNED affinity); ++ ++/** ++ * \brief Query whether we are in an interrupt. ++ * ++ * @return 1 if in interrupt context. ++ */ ++VCOS_INLINE_DECL ++int vcos_in_interrupt(void); ++ ++/** ++ * \brief Sleep a while. ++ * ++ * @param ms Number of milliseconds to sleep for ++ * ++ * This may actually sleep a whole number of ticks. ++ */ ++VCOS_INLINE_DECL ++void vcos_sleep(uint32_t ms); ++ ++/** ++ * \brief Return the value of the hardware microsecond counter. ++ * ++ */ ++VCOS_INLINE_DECL ++uint32_t vcos_getmicrosecs(void); ++ ++#define vcos_get_ms() (vcos_getmicrosecs()/1000) ++ ++/** ++ * \brief Return a unique identifier for the current process ++ * ++ */ ++VCOS_INLINE_DECL ++VCOS_UNSIGNED vcos_process_id_current(void); ++ ++/** Relinquish this time slice. */ ++VCOS_INLINE_DECL ++void vcos_thread_relinquish(void); ++ ++/** Return the name of the given thread. ++ */ ++VCOSPRE_ const char * VCOSPOST_ vcos_thread_get_name(const VCOS_THREAD_T *thread); ++ ++/** Change preemption. This is almost certainly not what you want, as it won't ++ * work reliably in a multicore system: although you can affect the preemption ++ * on *this* core, you won't affect what's happening on the other core(s). ++ * ++ * It's mainly here to ease migration. If you're using it in new code, you ++ * probably need to think again. ++ * ++ * @param pe New preemption, VCOS_PREEMPT or VCOS_NO_PREEMPT ++ * @return Old value of preemption. ++ */ ++VCOS_INLINE_DECL ++VCOS_UNSIGNED vcos_change_preemption(VCOS_UNSIGNED pe); ++ ++/** Is a thread still running, or has it exited? ++ * ++ * Note: this exists for some fairly scary code in the video codec tests. Don't ++ * try to use it for anything else, as it may well not do what you expect. ++ * ++ * @param thread thread to query ++ * @return non-zero if thread is running, or zero if it has exited. ++ */ ++VCOS_INLINE_DECL ++int vcos_thread_running(VCOS_THREAD_T *thread); ++ ++/** Resume a thread. ++ * ++ * @param thread thread to resume ++ */ ++VCOS_INLINE_DECL ++void vcos_thread_resume(VCOS_THREAD_T *thread); ++ ++/* ++ * Internal APIs - may not always be present and should not be used in ++ * client code. ++ */ ++ ++extern void _vcos_task_timer_set(void (*pfn)(void*), void *, VCOS_UNSIGNED ms); ++extern void _vcos_task_timer_cancel(void); ++ ++#ifdef __cplusplus ++} ++#endif ++#endif +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_thread_attr.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_thread_attr.h 2013-07-26 19:32:00.000000000 +0000 +@@ -0,0 +1,73 @@ ++/*============================================================================= ++Copyright (c) 2009 Broadcom Europe Limited. ++All rights reserved. ++ ++FILE DESCRIPTION ++VideoCore OS Abstraction Layer - thread attributes ++=============================================================================*/ ++ ++#ifndef VCOS_THREAD_ATTR_H ++#define VCOS_THREAD_ATTR_H ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/** ++ * \file ++ * ++ * Attributes for thread creation. ++ * ++ */ ++ ++/** Initialize thread attribute struct. This call does not allocate memory, ++ * and so cannot fail. ++ * ++ */ ++VCOSPRE_ void VCOSPOST_ vcos_thread_attr_init(VCOS_THREAD_ATTR_T *attrs); ++ ++/** Set the stack address and size. If not set, a stack will be allocated automatically. ++ * ++ * This can only be set on some platforms. It will always be possible to set the stack ++ * address on VideoCore, but on host platforms, support may well not be available. ++ */ ++#if VCOS_CAN_SET_STACK_ADDR ++VCOS_INLINE_DECL ++void vcos_thread_attr_setstack(VCOS_THREAD_ATTR_T *attrs, void *addr, VCOS_UNSIGNED sz); ++#endif ++ ++/** Set the stack size. If not set, a default size will be used. Attempting to call this after having ++ * set the stack location with vcos_thread_attr_setstack() will result in undefined behaviour. ++ */ ++VCOS_INLINE_DECL ++void vcos_thread_attr_setstacksize(VCOS_THREAD_ATTR_T *attrs, VCOS_UNSIGNED sz); ++ ++/** Set the task priority. If not set, a default value will be used. ++ */ ++VCOS_INLINE_DECL ++void vcos_thread_attr_setpriority(VCOS_THREAD_ATTR_T *attrs, VCOS_UNSIGNED pri); ++ ++/** Set the task cpu affinity. If not set, the default will be used. ++ */ ++VCOS_INLINE_DECL ++void vcos_thread_attr_setaffinity(VCOS_THREAD_ATTR_T *attrs, VCOS_UNSIGNED aff); ++ ++/** Set the timeslice. If not set the default will be used. ++ */ ++VCOS_INLINE_DECL ++void vcos_thread_attr_settimeslice(VCOS_THREAD_ATTR_T *attrs, VCOS_UNSIGNED ts); ++ ++/** The thread entry function takes (argc,argv), as per Nucleus, with ++ * argc being 0. This may be withdrawn in a future release and should not ++ * be used in new code. ++ */ ++VCOS_INLINE_DECL ++void _vcos_thread_attr_setlegacyapi(VCOS_THREAD_ATTR_T *attrs, VCOS_UNSIGNED legacy); ++ ++VCOS_INLINE_DECL ++void vcos_thread_attr_setautostart(VCOS_THREAD_ATTR_T *attrs, VCOS_UNSIGNED autostart); ++ ++#ifdef __cplusplus ++} ++#endif ++#endif +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_timer.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_timer.h 2013-07-26 19:32:00.000000000 +0000 +@@ -0,0 +1,95 @@ ++/*============================================================================= ++Copyright (c) 2009 Broadcom Europe Limited. ++All rights reserved. ++ ++Project : vcfw ++Module : chip driver ++ ++FILE DESCRIPTION ++VideoCore OS Abstraction Layer - timer support ++=============================================================================*/ ++ ++#ifndef VCOS_TIMER_H ++#define VCOS_TIMER_H ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++#include "interface/vcos/vcos_types.h" ++#include "vcos_platform.h" ++ ++/** \file vcos_timer.h ++ * ++ * Timers are single shot. ++ * ++ * Timer times are in milliseconds. ++ * ++ * \note that timer callback functions are called from an arbitrary thread ++ * context. The expiration function should do its work as quickly as possible; ++ * blocking should be avoided. ++ * ++ * \note On Windows, the separate function vcos_timer_init() must be called ++ * as timer initialization from DllMain is not possible. ++ */ ++ ++/** Perform timer subsystem initialization. This function is not needed ++ * on non-Windows platforms but is still present so that it can be ++ * called. On Windows it is needed because vcos_init() gets called ++ * from DLL initialization where it is not possible to create a ++ * time queue (deadlock occurs if you try). ++ * ++ * @return VCOS_SUCCESS on success. VCOS_EEXIST if this has already been called ++ * once. VCOS_ENOMEM if resource allocation failed. ++ */ ++VCOSPRE_ VCOS_STATUS_T VCOSPOST_ vcos_timer_init(void); ++ ++/** Create a timer in a disabled state. ++ * ++ * The timer is initially disabled. ++ * ++ * @param timer timer handle ++ * @param name name for timer ++ * @param expiration_routine function to call when timer expires ++ * @param context context passed to expiration routine ++ * ++ */ ++VCOS_INLINE_DECL ++VCOS_STATUS_T vcos_timer_create(VCOS_TIMER_T *timer, ++ const char *name, ++ void (*expiration_routine)(void *context), ++ void *context); ++ ++ ++ ++/** Start a timer running. ++ * ++ * Timer must be stopped. ++ * ++ * @param timer timer handle ++ * @param delay Delay to wait for, in ms ++ */ ++VCOS_INLINE_DECL ++void vcos_timer_set(VCOS_TIMER_T *timer, VCOS_UNSIGNED delay); ++ ++/** Stop an already running timer. ++ * ++ * @param timer timer handle ++ */ ++VCOS_INLINE_DECL ++void vcos_timer_cancel(VCOS_TIMER_T *timer); ++ ++/** Stop a timer and restart it. ++ * @param timer timer handle ++ * @param delay delay in ms ++ */ ++VCOS_INLINE_DECL ++void vcos_timer_reset(VCOS_TIMER_T *timer, VCOS_UNSIGNED delay); ++ ++VCOS_INLINE_DECL ++void vcos_timer_delete(VCOS_TIMER_T *timer); ++ ++#ifdef __cplusplus ++} ++#endif ++#endif +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_types.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_types.h 2013-07-26 19:32:00.000000000 +0000 +@@ -0,0 +1,197 @@ ++/*============================================================================= ++Copyright (c) 2009 Broadcom Europe Limited. ++All rights reserved. ++ ++FILE DESCRIPTION ++VideoCore OS Abstraction Layer - basic types ++=============================================================================*/ ++ ++#ifndef VCOS_TYPES_H ++#define VCOS_TYPES_H ++ ++#define VCOS_VERSION 1 ++ ++#include "vcos_platform_types.h" ++ ++#if !defined(VCOSPRE_) || !defined(VCOSPOST_) ++#error VCOSPRE_ and VCOSPOST_ not defined! ++#endif ++ ++/* Redefine these here; this means that existing header files can carry on ++ * using the VCHPOST/VCHPRE macros rather than having huge changes, which ++ * could cause nasty merge problems. ++ */ ++#ifndef VCHPOST_ ++#define VCHPOST_ VCOSPOST_ ++#endif ++#ifndef VCHPRE_ ++#define VCHPRE_ VCOSPRE_ ++#endif ++ ++/** Entry function for a lowlevel thread. ++ * ++ * Returns void for consistency with Nucleus/ThreadX. ++ */ ++typedef void (*VCOS_LLTHREAD_ENTRY_FN_T)(void *); ++ ++/** Thread entry point. Returns a void* for consistency ++ * with pthreads. ++ */ ++typedef void *(*VCOS_THREAD_ENTRY_FN_T)(void*); ++ ++ ++/* Error return codes - chosen to be similar to errno values */ ++typedef enum ++{ ++ VCOS_SUCCESS, ++ VCOS_EAGAIN, ++ VCOS_ENOENT, ++ VCOS_ENOSPC, ++ VCOS_EINVAL, ++ VCOS_EACCESS, ++ VCOS_ENOMEM, ++ VCOS_ENOSYS, ++ VCOS_EEXIST, ++ VCOS_ENXIO, ++ VCOS_EINTR ++} VCOS_STATUS_T; ++ ++/* Some compilers (MetaWare) won't inline with -g turned on, which then results ++ * in a lot of code bloat. To overcome this, inline functions are forward declared ++ * with the prefix VCOS_INLINE_DECL, and implemented with the prefix VCOS_INLINE_IMPL. ++ * ++ * That then means that in a release build, "static inline" can be used in the obvious ++ * way, but in a debug build the implementations can be skipped in all but one file, ++ * by using VCOS_INLINE_BODIES. ++ * ++ * VCOS_INLINE_DECL - put this at the start of an inline forward declaration of a VCOS ++ * function. ++ * ++ * VCOS_INLINE_IMPL - put this at the start of an inlined implementation of a VCOS ++ * function. ++ * ++ */ ++ ++/* VCOS_EXPORT - it turns out that in some circumstances we need the implementation of ++ * a function even if it is usually inlined. ++ * ++ * In particular, if we have a codec that is usually provided in object form, if it ++ * was built for a debug build it will be full of calls to vcos_XXX(). If this is used ++ * in a *release* build, then there won't be any of these calls around in the main image ++ * as they will all have been inlined. The problem also exists for vcos functions called ++ * from assembler. ++ * ++ * VCOS_EXPORT ensures that the named function will be emitted as a regular (not static-inline) ++ * function inside vcos_.c so that it can be linked against. Doing this for every ++ * VCOS function would be a bit code-bloat-tastic, so it is only done for those that need it. ++ * ++ */ ++ ++#ifdef __cplusplus ++#define _VCOS_INLINE inline ++#else ++#define _VCOS_INLINE __inline ++#endif ++ ++#if defined(NDEBUG) ++ ++#ifdef __GNUC__ ++# define VCOS_INLINE_DECL extern __inline__ ++# define VCOS_INLINE_IMPL static __inline__ ++#else ++# define VCOS_INLINE_DECL static _VCOS_INLINE /* declare a func */ ++# define VCOS_INLINE_IMPL static _VCOS_INLINE /* implement a func inline */ ++#endif ++ ++# if defined(VCOS_WANT_IMPL) ++# define VCOS_EXPORT ++# else ++# define VCOS_EXPORT VCOS_INLINE_IMPL ++# endif /* VCOS_WANT_IMPL */ ++ ++#define VCOS_INLINE_BODIES ++ ++#else /* NDEBUG */ ++ ++#if !defined(VCOS_INLINE_DECL) ++ #define VCOS_INLINE_DECL extern ++#endif ++#if !defined(VCOS_INLINE_IMPL) ++ #define VCOS_INLINE_IMPL ++#endif ++#define VCOS_EXPORT VCOS_INLINE_IMPL ++#endif ++ ++#define VCOS_STATIC_INLINE static _VCOS_INLINE ++ ++#if defined(__HIGHC__) || defined(__HIGHC_ANSI__) ++#define _VCOS_METAWARE ++#endif ++ ++/** It seems that __FUNCTION__ isn't standard! ++ */ ++#if __STDC_VERSION__ < 199901L ++# if __GNUC__ >= 2 || defined(__VIDEOCORE__) ++# define VCOS_FUNCTION __FUNCTION__ ++# else ++# define VCOS_FUNCTION "" ++# endif ++#else ++# define VCOS_FUNCTION __func__ ++#endif ++ ++#define _VCOS_MS_PER_TICK (1000/VCOS_TICKS_PER_SECOND) ++ ++/* Convert a number of milliseconds to a tick count. Internal use only - fails to ++ * convert VCOS_SUSPEND correctly. ++ */ ++#define _VCOS_MS_TO_TICKS(ms) (((ms)+_VCOS_MS_PER_TICK-1)/_VCOS_MS_PER_TICK) ++ ++#define VCOS_TICKS_TO_MS(ticks) ((ticks) * _VCOS_MS_PER_TICK) ++ ++/** VCOS version of DATESTR, from pcdisk.h. Used by the hostreq service. ++ */ ++typedef struct vcos_datestr ++{ ++ uint8_t cmsec; /**< Centesimal mili second */ ++ uint16_t date; /**< Date */ ++ uint16_t time; /**< Time */ ++ ++} VCOS_DATESTR; ++ ++/* Compile-time assert - declares invalid array length if condition ++ * not met, or array of length one if OK. ++ */ ++#define VCOS_CASSERT(e) extern char vcos_compile_time_check[1/(e)] ++ ++#define vcos_min(x,y) ((x) < (y) ? (x) : (y)) ++#define vcos_max(x,y) ((x) > (y) ? (x) : (y)) ++ ++/** Return the count of an array. FIXME: under gcc we could make ++ * this report an error for pointers using __builtin_types_compatible(). ++ */ ++#define vcos_countof(x) (sizeof((x)) / sizeof((x)[0])) ++ ++/* for backward compatibility */ ++#define countof(x) (sizeof((x)) / sizeof((x)[0])) ++ ++#define VCOS_ALIGN_DOWN(p,n) (((ptrdiff_t)(p)) & ~((n)-1)) ++#define VCOS_ALIGN_UP(p,n) VCOS_ALIGN_DOWN((ptrdiff_t)(p)+(n)-1,(n)) ++ ++/** bool_t is not a POSIX type so cannot rely on it. Define it here. ++ * It's not even defined in stdbool.h. ++ */ ++typedef int32_t vcos_bool_t; ++typedef int32_t vcos_fourcc_t; ++ ++#define VCOS_FALSE 0 ++#define VCOS_TRUE (!VCOS_FALSE) ++ ++/** Mark unused arguments to keep compilers quiet */ ++#define vcos_unused(x) (void)(x) ++ ++/** For backward compatibility */ ++typedef vcos_fourcc_t fourcc_t; ++typedef vcos_fourcc_t FOURCC_T; ++ ++#endif diff -Nru linux-3.2.46/debian/patches/rpi/rpi_105_b102abd4d519186f3ed132242c896308e853c509.patch linux-3.2.46/debian/patches/rpi/rpi_105_b102abd4d519186f3ed132242c896308e853c509.patch --- linux-3.2.46/debian/patches/rpi/rpi_105_b102abd4d519186f3ed132242c896308e853c509.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_105_b102abd4d519186f3ed132242c896308e853c509.patch 2013-07-26 19:32:07.000000000 +0000 @@ -0,0 +1,91 @@ +commit b102abd4d519186f3ed132242c896308e853c509 +Author: popcornmix +Date: Tue Jan 17 19:22:59 2012 +0000 + + Allow mac address to be set in smsc95xx + + Signed-off-by: popcornmix + +Index: linux-3.2.46/drivers/net/usb/smsc95xx.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/usb/smsc95xx.c 2013-05-30 13:35:16.000000000 +0000 ++++ linux-3.2.46/drivers/net/usb/smsc95xx.c 2013-07-26 19:32:06.000000000 +0000 +@@ -46,6 +46,7 @@ + #define SMSC95XX_INTERNAL_PHY_ID (1) + #define SMSC95XX_TX_OVERHEAD (8) + #define SMSC95XX_TX_OVERHEAD_CSUM (12) ++#define MAC_ADDR_LEN (6) + + struct smsc95xx_priv { + u32 mac_cr; +@@ -63,6 +64,10 @@ + module_param(turbo_mode, bool, 0644); + MODULE_PARM_DESC(turbo_mode, "Enable multiple frames per Rx transaction"); + ++static char *macaddr = ":"; ++module_param(macaddr, charp, 0); ++MODULE_PARM_DESC(macaddr, "MAC address"); ++ + static int smsc95xx_read_reg(struct usbnet *dev, u32 index, u32 *data) + { + u32 *buf = kmalloc(4, GFP_KERNEL); +@@ -600,8 +605,59 @@ + return generic_mii_ioctl(&dev->mii, if_mii(rq), cmd, NULL); + } + ++/* Check the macaddr module parameter for a MAC address */ ++static int smsc95xx_is_macaddr_param(struct usbnet *dev, u8 *dev_mac) ++{ ++ int i, j, got_num, num; ++ u8 mtbl[MAC_ADDR_LEN]; ++ ++ if (macaddr[0] == ':') ++ return 0; ++ ++ i = 0; ++ j = 0; ++ num = 0; ++ got_num = 0; ++ while (j < MAC_ADDR_LEN) { ++ if (macaddr[i] && macaddr[i] != ':') { ++ got_num++; ++ if ('0' <= macaddr[i] && macaddr[i] <= '9') ++ num = num * 16 + macaddr[i] - '0'; ++ else if ('A' <= macaddr[i] && macaddr[i] <= 'F') ++ num = num * 16 + 10 + macaddr[i] - 'A'; ++ else if ('a' <= macaddr[i] && macaddr[i] <= 'f') ++ num = num * 16 + 10 + macaddr[i] - 'a'; ++ else ++ break; ++ i++; ++ } else if (got_num == 2) { ++ mtbl[j++] = (u8) num; ++ num = 0; ++ got_num = 0; ++ i++; ++ } else { ++ break; ++ } ++ } ++ ++ if (j == MAC_ADDR_LEN) { ++ netif_dbg(dev, ifup, dev->net, "Overriding MAC address with: " ++ "%02x:%02x:%02x:%02x:%02x:%02x\n", mtbl[0], mtbl[1], mtbl[2], ++ mtbl[3], mtbl[4], mtbl[5]); ++ for (i = 0; i < MAC_ADDR_LEN; i++) ++ dev_mac[i] = mtbl[i]; ++ return 1; ++ } else { ++ return 0; ++ } ++} ++ + static void smsc95xx_init_mac_address(struct usbnet *dev) + { ++ /* Check module parameters */ ++ if (smsc95xx_is_macaddr_param(dev, dev->net->dev_addr)) ++ return; ++ + /* try reading mac address from EEPROM */ + if (smsc95xx_read_eeprom(dev, EEPROM_MAC_OFFSET, ETH_ALEN, + dev->net->dev_addr) == 0) { diff -Nru linux-3.2.46/debian/patches/rpi/rpi_106_2aa2155925a3989285a9cc0f804d57a2420bd28f.patch linux-3.2.46/debian/patches/rpi/rpi_106_2aa2155925a3989285a9cc0f804d57a2420bd28f.patch --- linux-3.2.46/debian/patches/rpi/rpi_106_2aa2155925a3989285a9cc0f804d57a2420bd28f.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_106_2aa2155925a3989285a9cc0f804d57a2420bd28f.patch 2013-07-26 19:32:11.000000000 +0000 @@ -0,0 +1,1445 @@ +commit 2aa2155925a3989285a9cc0f804d57a2420bd28f +Author: Dom Cobley +Date: Fri Jan 20 18:23:29 2012 +0000 + + Fix headers for vchiq/vcos to be GPLv2 + + Signed-off-by: Dom Cobley + +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vchi/vchi_mh.h +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vchi/vchi_mh.h 2013-07-26 19:32:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vchi/vchi_mh.h 2013-07-26 19:32:07.000000000 +0000 +@@ -1,12 +1,20 @@ +-/*============================================================================= +-Copyright (c) 2010 Broadcom Europe Limited. All rights reserved. +- +-Project : vchi +-Module : vchi +- +-FILE DESCRIPTION: +-Definitions for memory handle types. +-=============================================================================*/ ++/* ++ * Copyright (c) 2010-2011 Broadcom. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ + + #ifndef VCHI_MH_H_ + #define VCHI_MH_H_ +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/generic/vcos_common.h +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vcos/generic/vcos_common.h 2013-07-26 19:32:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/generic/vcos_common.h 2013-07-26 19:32:07.000000000 +0000 +@@ -1,11 +1,22 @@ +-/*============================================================================= +-Copyright (c) 2009 Broadcom Europe Limited. +-All rights reserved. +- +-Project : vcfw +-Module : chip driver ++/* ++ * Copyright (c) 2010-2011 Broadcom. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ + +-FILE DESCRIPTION ++/*============================================================================= + VideoCore OS Abstraction Layer - common postamble code + =============================================================================*/ + +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/generic/vcos_generic_blockpool.h +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vcos/generic/vcos_generic_blockpool.h 2013-07-26 19:32:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/generic/vcos_generic_blockpool.h 2013-07-26 19:32:07.000000000 +0000 +@@ -1,11 +1,22 @@ +-/*============================================================================= +-Copyright (c) 2011 Broadcom Europe Limited. +-All rights reserved. +- +-Project : vcfw +-Module : chip driver ++/* ++ * Copyright (c) 2010-2011 Broadcom. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ + +-FILE DESCRIPTION ++/*============================================================================= + VideoCore OS Abstraction Layer - event flags implemented via a semaphore + =============================================================================*/ + +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/generic/vcos_generic_event_flags.c +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vcos/generic/vcos_generic_event_flags.c 2013-07-26 19:32:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/generic/vcos_generic_event_flags.c 2013-07-26 19:32:07.000000000 +0000 +@@ -1,8 +1,22 @@ +-/*============================================================================= +-Copyright (c) 2009 Broadcom Europe Limited. +-All rights reserved. ++/* ++ * Copyright (c) 2010-2011 Broadcom. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ + +-FILE DESCRIPTION ++/*============================================================================= + VideoCore OS Abstraction Layer - event flags implemented via mutexes + =============================================================================*/ + +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/generic/vcos_generic_event_flags.h +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vcos/generic/vcos_generic_event_flags.h 2013-07-26 19:32:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/generic/vcos_generic_event_flags.h 2013-07-26 19:32:07.000000000 +0000 +@@ -1,8 +1,22 @@ +-/*============================================================================= +-Copyright (c) 2009 Broadcom Europe Limited. +-All rights reserved. ++/* ++ * Copyright (c) 2010-2011 Broadcom. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ + +-FILE DESCRIPTION ++/*============================================================================= + VideoCore OS Abstraction Layer - event flags implemented via a semaphore + =============================================================================*/ + +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/generic/vcos_generic_named_sem.h +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vcos/generic/vcos_generic_named_sem.h 2013-07-26 19:32:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/generic/vcos_generic_named_sem.h 2013-07-26 19:32:07.000000000 +0000 +@@ -1,11 +1,22 @@ +-/*============================================================================= +-Copyright (c) 2009 Broadcom Europe Limited. +-All rights reserved. +- +-Project : vcfw +-Module : chip driver ++/* ++ * Copyright (c) 2010-2011 Broadcom. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ + +-FILE DESCRIPTION ++/*============================================================================= + VideoCore OS Abstraction Layer - named semaphores + =============================================================================*/ + +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/generic/vcos_generic_quickslow_mutex.h +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vcos/generic/vcos_generic_quickslow_mutex.h 2013-07-26 19:32:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/generic/vcos_generic_quickslow_mutex.h 2013-07-26 19:32:07.000000000 +0000 +@@ -1,11 +1,22 @@ +-/*============================================================================= +-Copyright (c) 2009 Broadcom Europe Limited. +-All rights reserved. +- +-Project : vcfw +-Module : chip driver ++/* ++ * Copyright (c) 2010-2011 Broadcom. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ + +-FILE DESCRIPTION ++/*============================================================================= + VideoCore OS Abstraction Layer - reentrant mutexes created from regular ones. + =============================================================================*/ + +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/generic/vcos_generic_reentrant_mtx.h +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vcos/generic/vcos_generic_reentrant_mtx.h 2013-07-26 19:32:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/generic/vcos_generic_reentrant_mtx.h 2013-07-26 19:32:07.000000000 +0000 +@@ -1,11 +1,22 @@ +-/*============================================================================= +-Copyright (c) 2009 Broadcom Europe Limited. +-All rights reserved. +- +-Project : vcfw +-Module : chip driver ++/* ++ * Copyright (c) 2010-2011 Broadcom. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ + +-FILE DESCRIPTION ++/*============================================================================= + VideoCore OS Abstraction Layer - reentrant mutexes created from regular ones. + =============================================================================*/ + +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/generic/vcos_generic_tls.h +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vcos/generic/vcos_generic_tls.h 2013-07-26 19:32:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/generic/vcos_generic_tls.h 2013-07-26 19:32:07.000000000 +0000 +@@ -1,11 +1,22 @@ +-/*============================================================================= +-Copyright (c) 2009 Broadcom Europe Limited. +-All rights reserved. +- +-Project : vcfw +-Module : chip driver ++/* ++ * Copyright (c) 2010-2011 Broadcom. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ + +-FILE DESCRIPTION ++/*============================================================================= + VideoCore OS Abstraction Layer - generic thread local storage + =============================================================================*/ + +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/generic/vcos_joinable_thread_from_plain.h +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vcos/generic/vcos_joinable_thread_from_plain.h 2013-07-26 19:32:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/generic/vcos_joinable_thread_from_plain.h 2013-07-26 19:32:07.000000000 +0000 +@@ -1,10 +1,22 @@ +-/*============================================================================= +-Copyright (c) 2009 Broadcom Europe Limited. +-All rights reserved. +- +-Module : vcos ++/* ++ * Copyright (c) 2010-2011 Broadcom. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ + +-FILE DESCRIPTION ++/*============================================================================= + VideoCore OS Abstraction Layer - implementation: joinable thread from plain + =============================================================================*/ + +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/generic/vcos_latch_from_sem.h +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vcos/generic/vcos_latch_from_sem.h 2013-07-26 19:32:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/generic/vcos_latch_from_sem.h 2013-07-26 19:32:07.000000000 +0000 +@@ -1,11 +1,22 @@ +-/*============================================================================= +-Copyright (c) 2009 Broadcom Europe Limited. +-All rights reserved. +- +-Project : vcfw +-Module : vcos ++/* ++ * Copyright (c) 2010-2011 Broadcom. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ + +-FILE DESCRIPTION ++/*============================================================================= + VideoCore OS Abstraction Layer - Construct a latch from a semaphore + =============================================================================*/ + +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/generic/vcos_logcat.c +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vcos/generic/vcos_logcat.c 2013-07-26 19:32:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/generic/vcos_logcat.c 2013-07-26 19:32:07.000000000 +0000 +@@ -1,11 +1,22 @@ +-/*============================================================================= +-Copyright (c) 2010 Broadcom Europe Limited. +-All rights reserved. +- +-Project : vcfw +-Module : vcos ++/* ++ * Copyright (c) 2010-2011 Broadcom. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ + +-FILE DESCRIPTION ++/*============================================================================= + Categorized logging for VCOS - a generic implementation. + =============================================================================*/ + +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/generic/vcos_mem_from_malloc.c +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vcos/generic/vcos_mem_from_malloc.c 2013-07-26 19:32:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/generic/vcos_mem_from_malloc.c 2013-07-26 19:32:07.000000000 +0000 +@@ -1,11 +1,22 @@ +-/*============================================================================= +-Copyright (c) 2009 Broadcom Europe Limited. +-All rights reserved. +- +-Project : vcfw +-Module : vcos ++/* ++ * Copyright (c) 2010-2011 Broadcom. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ + +-FILE DESCRIPTION ++/*============================================================================= + VideoCore OS Abstraction Layer - memory alloc implementation + =============================================================================*/ + +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/generic/vcos_mem_from_malloc.h +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vcos/generic/vcos_mem_from_malloc.h 2013-07-26 19:32:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/generic/vcos_mem_from_malloc.h 2013-07-26 19:32:07.000000000 +0000 +@@ -1,11 +1,22 @@ +-/*============================================================================= +-Copyright (c) 2009 Broadcom Europe Limited. +-All rights reserved. +- +-Project : VMCS Host Apps +-Module : Framework - VMCS ++/* ++ * Copyright (c) 2010-2011 Broadcom. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ + +-FILE DESCRIPTION ++/*============================================================================= + Create the vcos_malloc API from the regular system malloc/free + =============================================================================*/ + +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/generic/vcos_mutexes_are_reentrant.h +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vcos/generic/vcos_mutexes_are_reentrant.h 2013-07-26 19:32:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/generic/vcos_mutexes_are_reentrant.h 2013-07-26 19:32:07.000000000 +0000 +@@ -1,11 +1,22 @@ +-/*============================================================================= +-Copyright (c) 2009 Broadcom Europe Limited. +-All rights reserved. +- +-Project : vcfw +-Module : chip driver ++/* ++ * Copyright (c) 2010-2011 Broadcom. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ + +-FILE DESCRIPTION ++/*============================================================================= + VideoCore OS Abstraction Layer - reentrant mutexes mapped directly to regular ones + =============================================================================*/ + +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/generic/vcos_thread_reaper.h +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vcos/generic/vcos_thread_reaper.h 2013-07-26 19:32:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/generic/vcos_thread_reaper.h 2013-07-26 19:32:07.000000000 +0000 +@@ -1,11 +1,22 @@ +-/*============================================================================= +-Copyright (c) 2010 Broadcom Europe Limited. +-All rights reserved. +- +-Project : vcfw +-Module : vcos ++/* ++ * Copyright (c) 2010-2011 Broadcom. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ + +-FILE DESCRIPTION ++/*============================================================================= + VideoCore OS Abstraction Layer - thread reaping + =============================================================================*/ + +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/linuxkernel/stdint.h +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vcos/linuxkernel/stdint.h 2013-07-26 19:32:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/linuxkernel/stdint.h 2013-07-26 19:32:07.000000000 +0000 +@@ -1,8 +1,22 @@ +-/*============================================================================= +-Copyright (c) 2010 Broadcom Europe Limited. +-All rights reserved. ++/* ++ * Copyright (c) 2010-2011 Broadcom. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ + +-FILE DESCRIPTION ++/*============================================================================= + VideoCore OS fAbstraction Layer - stdint.h C standard header + =============================================================================*/ + +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/linuxkernel/vcos_linuxkernel.c +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vcos/linuxkernel/vcos_linuxkernel.c 2013-07-26 19:32:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/linuxkernel/vcos_linuxkernel.c 2013-07-26 19:32:07.000000000 +0000 +@@ -1,11 +1,22 @@ +-/*============================================================================= +-Copyright (c) 2009 Broadcom Europe Limited. +-All rights reserved. +- +-Project : vcfw +-Module : vcos ++/* ++ * Copyright (c) 2010-2011 Broadcom. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ + +-FILE DESCRIPTION ++/*============================================================================= + VideoCore OS Abstraction Layer - pthreads types + =============================================================================*/ + +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/linuxkernel/vcos_linuxkernel_misc.c +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vcos/linuxkernel/vcos_linuxkernel_misc.c 2013-07-26 19:32:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/linuxkernel/vcos_linuxkernel_misc.c 2013-07-26 19:32:07.000000000 +0000 +@@ -1,5 +1,3 @@ +-// ############################################################################# +-// START ####################################################################### + /***************************************************************************** + * Copyright 2009 - 2010 Broadcom Corporation. All rights reserved. + * +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/linuxkernel/vcos_platform.h +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vcos/linuxkernel/vcos_platform.h 2013-07-26 19:32:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/linuxkernel/vcos_platform.h 2013-07-26 19:32:07.000000000 +0000 +@@ -1,11 +1,22 @@ +-/*============================================================================= +-Copyright (c) 2009 Broadcom Europe Limited. +-All rights reserved. +- +-Project : vcfw +-Module : vcos ++/* ++ * Copyright (c) 2010-2011 Broadcom. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ + +-FILE DESCRIPTION ++/*============================================================================= + VideoCore OS Abstraction Layer - Linux kernel (partial) implementation. + =============================================================================*/ + +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/linuxkernel/vcos_platform_types.h +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vcos/linuxkernel/vcos_platform_types.h 2013-07-26 19:32:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/linuxkernel/vcos_platform_types.h 2013-07-26 19:32:07.000000000 +0000 +@@ -1,11 +1,22 @@ +-/*============================================================================= +-Copyright (c) 2009 Broadcom Europe Limited. +-All rights reserved. +- +-Project : vcfw +-Module : osal ++/* ++ * Copyright (c) 2010-2011 Broadcom. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ + +-FILE DESCRIPTION ++/*============================================================================= + VideoCore OS Abstraction Layer - platform-specific types and defines + =============================================================================*/ + +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos.h +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vcos/vcos.h 2013-07-26 19:32:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos.h 2013-07-26 19:32:07.000000000 +0000 +@@ -1,11 +1,22 @@ +-/*============================================================================= +-Copyright (c) 2009 Broadcom Europe Limited. +-All rights reserved. +- +-Project : vcfw +-Module : chip driver ++/* ++ * Copyright (c) 2010-2011 Broadcom. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ + +-FILE DESCRIPTION ++/*============================================================================= + VideoCore OS Abstraction Layer - public header file + =============================================================================*/ + +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_assert.h +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vcos/vcos_assert.h 2013-07-26 19:32:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_assert.h 2013-07-26 19:32:07.000000000 +0000 +@@ -1,11 +1,22 @@ +-/*============================================================================= +-Copyright (c) 2009 Broadcom Europe Limited. +-All rights reserved. +- +-Project : vcfw +-Module : osal ++/* ++ * Copyright (c) 2010-2011 Broadcom. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ + +-FILE DESCRIPTION ++/*============================================================================= + VideoCore OS Abstraction Layer - Assertion and error-handling macros. + =============================================================================*/ + +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_atomic_flags.h +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vcos/vcos_atomic_flags.h 2013-07-26 19:32:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_atomic_flags.h 2013-07-26 19:32:07.000000000 +0000 +@@ -1,11 +1,22 @@ +-/*============================================================================= +-Copyright (c) 2009 Broadcom Europe Limited. +-All rights reserved. +- +-Project : vcfw +-Module : chip driver (just for consistency with the rest of vcos ;) ++/* ++ * Copyright (c) 2010-2011 Broadcom. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ + +-FILE DESCRIPTION ++/*============================================================================= + VideoCore OS Abstraction Layer - public header file + =============================================================================*/ + +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_build_info.h +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vcos/vcos_build_info.h 2013-07-26 19:32:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_build_info.h 2013-07-26 19:32:07.000000000 +0000 +@@ -1,3 +1,21 @@ ++/* ++ * Copyright (c) 2010-2011 Broadcom. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ + const char *vcos_get_build_hostname( void ); + const char *vcos_get_build_version( void ); + const char *vcos_get_build_time( void ); +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_ctype.h +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vcos/vcos_ctype.h 2013-07-26 19:32:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_ctype.h 2013-07-26 19:32:07.000000000 +0000 +@@ -1,11 +1,22 @@ +-/*============================================================================= +-Copyright (c) 2009 Broadcom Europe Limited. +-All rights reserved. +- +-Project : vcfw +-Module : chip driver ++/* ++ * Copyright (c) 2010-2011 Broadcom. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ + +-FILE DESCRIPTION ++/*============================================================================= + VideoCore OS Abstraction Layer - public header file + =============================================================================*/ + +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_dlfcn.h +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vcos/vcos_dlfcn.h 2013-07-26 19:32:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_dlfcn.h 2013-07-26 19:32:07.000000000 +0000 +@@ -1,11 +1,22 @@ +-/*============================================================================= +-Copyright (c) 2010 Broadcom Europe Limited. +-All rights reserved. +- +-Project : vcfw +-Module : chip driver ++/* ++ * Copyright (c) 2010-2011 Broadcom. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ + +-FILE DESCRIPTION ++/*============================================================================= + VCOS - abstraction over dynamic library opening + =============================================================================*/ + +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_event.h +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vcos/vcos_event.h 2013-07-26 19:32:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_event.h 2013-07-26 19:32:07.000000000 +0000 +@@ -1,11 +1,22 @@ +-/*============================================================================= +-Copyright (c) 2009 Broadcom Europe Limited. +-All rights reserved. +- +-Project : vcfw +-Module : chip driver ++/* ++ * Copyright (c) 2010-2011 Broadcom. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ + +-FILE DESCRIPTION ++/*============================================================================= + VideoCore OS Abstraction Layer - public header file for events + =============================================================================*/ + +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_event_flags.h +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vcos/vcos_event_flags.h 2013-07-26 19:32:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_event_flags.h 2013-07-26 19:32:07.000000000 +0000 +@@ -1,11 +1,22 @@ +-/*============================================================================= +-Copyright (c) 2009 Broadcom Europe Limited. +-All rights reserved. +- +-Project : vcfw +-Module : chip driver ++/* ++ * Copyright (c) 2010-2011 Broadcom. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ + +-FILE DESCRIPTION ++/*============================================================================= + VideoCore OS Abstraction Layer - public header file + =============================================================================*/ + +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_init.h +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vcos/vcos_init.h 2013-07-26 19:32:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_init.h 2013-07-26 19:32:07.000000000 +0000 +@@ -1,11 +1,22 @@ +-/*============================================================================= +-Copyright (c) 2009 Broadcom Europe Limited. +-All rights reserved. +- +-Project : vcfw +-Module : chip driver ++/* ++ * Copyright (c) 2010-2011 Broadcom. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ + +-FILE DESCRIPTION ++/*============================================================================= + VideoCore OS Abstraction Layer - initialization routines + =============================================================================*/ + +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_logging.h +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vcos/vcos_logging.h 2013-07-26 19:32:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_logging.h 2013-07-26 19:32:07.000000000 +0000 +@@ -1,11 +1,22 @@ +-/*============================================================================= +-Copyright (c) 2009-2011 Broadcom Europe Limited. +-All rights reserved. +- +-Project : vcfw +-Module : chip driver ++/* ++ * Copyright (c) 2010-2011 Broadcom. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ + +-FILE DESCRIPTION ++/*============================================================================= + VideoCore OS Abstraction Layer - logging support + =============================================================================*/ + +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_lowlevel_thread.h +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vcos/vcos_lowlevel_thread.h 2013-07-26 19:32:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_lowlevel_thread.h 2013-07-26 19:32:07.000000000 +0000 +@@ -1,11 +1,22 @@ +-/*============================================================================= +-Copyright (c) 2009 Broadcom Europe Limited. +-All rights reserved. +- +-Project : vcfw +-Module : chip driver ++/* ++ * Copyright (c) 2010-2011 Broadcom. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ + +-FILE DESCRIPTION ++/*============================================================================= + VideoCore OS Abstraction Layer - low level thread support + =============================================================================*/ + +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_mem.h +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vcos/vcos_mem.h 2013-07-26 19:32:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_mem.h 2013-07-26 19:32:07.000000000 +0000 +@@ -1,11 +1,22 @@ +-/*============================================================================= +-Copyright (c) 2009 Broadcom Europe Limited. +-All rights reserved. +- +-Project : vcfw +-Module : chip driver ++/* ++ * Copyright (c) 2010-2011 Broadcom. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ + +-FILE DESCRIPTION ++/*============================================================================= + VideoCore OS Abstraction Layer - memory support + =============================================================================*/ + +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_msgqueue.h +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vcos/vcos_msgqueue.h 2013-07-26 19:32:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_msgqueue.h 2013-07-26 19:32:07.000000000 +0000 +@@ -1,11 +1,22 @@ +-/*============================================================================= +-Copyright (c) 2009 Broadcom Europe Limited. +-All rights reserved. +- +-Project : vcfw +-Module : chip driver ++/* ++ * Copyright (c) 2010-2011 Broadcom. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ + +-FILE DESCRIPTION ++/*============================================================================= + VCOS - packet-like messages, based loosely on those found in TRIPOS. + =============================================================================*/ + +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_mutex.h +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vcos/vcos_mutex.h 2013-07-26 19:32:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_mutex.h 2013-07-26 19:32:07.000000000 +0000 +@@ -1,11 +1,22 @@ +-/*============================================================================= +-Copyright (c) 2009 Broadcom Europe Limited. +-All rights reserved. +- +-Project : vcfw +-Module : chip driver ++/* ++ * Copyright (c) 2010-2011 Broadcom. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ + +-FILE DESCRIPTION ++/*============================================================================= + VideoCore OS Abstraction Layer - mutex public header file + =============================================================================*/ + +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_once.h +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vcos/vcos_once.h 2013-07-26 19:32:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_once.h 2013-07-26 19:32:07.000000000 +0000 +@@ -1,11 +1,22 @@ +-/*============================================================================= +-Copyright (c) 2011 Broadcom Europe Limited. +-All rights reserved. +- +-Project : vcfw +-Module : chip driver ++/* ++ * Copyright (c) 2010-2011 Broadcom. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ + +-FILE DESCRIPTION ++/*============================================================================= + VideoCore OS Abstraction Layer - 'once' + =============================================================================*/ + +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_semaphore.h +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vcos/vcos_semaphore.h 2013-07-26 19:32:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_semaphore.h 2013-07-26 19:32:07.000000000 +0000 +@@ -1,11 +1,22 @@ +-/*============================================================================= +-Copyright (c) 2009 Broadcom Europe Limited. +-All rights reserved. +- +-Project : vcfw +-Module : chip driver ++/* ++ * Copyright (c) 2010-2011 Broadcom. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ + +-FILE DESCRIPTION ++/*============================================================================= + VideoCore OS Abstraction Layer - public header file + =============================================================================*/ + +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_stdbool.h +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vcos/vcos_stdbool.h 2013-07-26 19:32:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_stdbool.h 2013-07-26 19:32:07.000000000 +0000 +@@ -1,3 +1,20 @@ ++/* ++ * Copyright (c) 2010-2011 Broadcom. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ + #ifndef VCOS_STDBOOL_H + #define VCOS_STDBOOL_H + +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_stdint.h +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vcos/vcos_stdint.h 2013-07-26 19:32:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_stdint.h 2013-07-26 19:32:07.000000000 +0000 +@@ -1,10 +1,20 @@ +-/*============================================================================= +-Copyright (c) 2011 Broadcom Europe Limited. +-All rights reserved. +- +-FILE DESCRIPTION +- +-=============================================================================*/ ++/* ++ * Copyright (c) 2010-2011 Broadcom. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ + + #ifndef VCOS_STDINT_H + #define VCOS_STDINT_H +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_string.h +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vcos/vcos_string.h 2013-07-26 19:32:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_string.h 2013-07-26 19:32:07.000000000 +0000 +@@ -1,11 +1,22 @@ +-/*============================================================================= +-Copyright (c) 2009 Broadcom Europe Limited. +-All rights reserved. +- +-Project : vcfw +-Module : chip driver ++/* ++ * Copyright (c) 2010-2011 Broadcom. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ + +-FILE DESCRIPTION ++/*============================================================================= + VideoCore OS Abstraction Layer - public header file + =============================================================================*/ + +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_thread.h +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vcos/vcos_thread.h 2013-07-26 19:32:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_thread.h 2013-07-26 19:32:07.000000000 +0000 +@@ -1,11 +1,22 @@ +-/*============================================================================= +-Copyright (c) 2009 Broadcom Europe Limited. +-All rights reserved. +- +-Project : vcfw +-Module : chip driver ++/* ++ * Copyright (c) 2010-2011 Broadcom. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ + +-FILE DESCRIPTION ++/*============================================================================= + VideoCore OS Abstraction Layer - public header file + =============================================================================*/ + +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_thread_attr.h +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vcos/vcos_thread_attr.h 2013-07-26 19:32:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_thread_attr.h 2013-07-26 19:32:07.000000000 +0000 +@@ -1,8 +1,22 @@ +-/*============================================================================= +-Copyright (c) 2009 Broadcom Europe Limited. +-All rights reserved. ++/* ++ * Copyright (c) 2010-2011 Broadcom. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ + +-FILE DESCRIPTION ++/*============================================================================= + VideoCore OS Abstraction Layer - thread attributes + =============================================================================*/ + +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_timer.h +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vcos/vcos_timer.h 2013-07-26 19:32:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_timer.h 2013-07-26 19:32:07.000000000 +0000 +@@ -1,11 +1,22 @@ +-/*============================================================================= +-Copyright (c) 2009 Broadcom Europe Limited. +-All rights reserved. +- +-Project : vcfw +-Module : chip driver ++/* ++ * Copyright (c) 2010-2011 Broadcom. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ + +-FILE DESCRIPTION ++/*============================================================================= + VideoCore OS Abstraction Layer - timer support + =============================================================================*/ + +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_types.h +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vcos/vcos_types.h 2013-07-26 19:32:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_types.h 2013-07-26 19:32:07.000000000 +0000 +@@ -1,8 +1,22 @@ +-/*============================================================================= +-Copyright (c) 2009 Broadcom Europe Limited. +-All rights reserved. ++/* ++ * Copyright (c) 2010-2011 Broadcom. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ + +-FILE DESCRIPTION ++/*============================================================================= + VideoCore OS Abstraction Layer - basic types + =============================================================================*/ + diff -Nru linux-3.2.46/debian/patches/rpi/rpi_107_92568ccbcfab09713e3748cd128b88d3313c346b.patch linux-3.2.46/debian/patches/rpi/rpi_107_92568ccbcfab09713e3748cd128b88d3313c346b.patch --- linux-3.2.46/debian/patches/rpi/rpi_107_92568ccbcfab09713e3748cd128b88d3313c346b.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_107_92568ccbcfab09713e3748cd128b88d3313c346b.patch 2013-07-26 19:32:13.000000000 +0000 @@ -0,0 +1,1437 @@ +commit 92568ccbcfab09713e3748cd128b88d3313c346b +Author: Dom Cobley +Date: Wed Feb 1 21:34:17 2012 +0000 + + Fix some issues reported. Lower case module parameters for fb. Set board rev and serial. Requires updated start.elf. + + Signed-off-by: Dom Cobley + +Index: linux-3.2.46/arch/arm/mach-bcm2708/bcm2708.c +=================================================================== +--- linux-3.2.46.orig/arch/arm/mach-bcm2708/bcm2708.c 2013-07-26 19:31:51.000000000 +0000 ++++ linux-3.2.46/arch/arm/mach-bcm2708/bcm2708.c 2013-07-26 19:32:11.000000000 +0000 +@@ -30,6 +30,7 @@ + #include + #include + #include ++#include + + #include + #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,38) +@@ -69,6 +70,9 @@ + */ + #define DMA_MASK_BITS_COMMON 32 + ++/* command line parameters */ ++static unsigned boardrev, serial; ++ + static void __init bcm2708_init_led(void); + + void __init bcm2708_init_irq(void) +@@ -78,58 +82,72 @@ + + static struct map_desc bcm2708_io_desc[] __initdata = { + { +- .virtual = IO_ADDRESS(ARMCTRL_BASE), +- .pfn = __phys_to_pfn(ARMCTRL_BASE), +- .length = SZ_4K, +- .type = MT_DEVICE +- }, { +- .virtual = IO_ADDRESS(UART0_BASE), +- .pfn = __phys_to_pfn(UART0_BASE), +- .length = SZ_4K, +- .type = MT_DEVICE +- }, { +- .virtual = IO_ADDRESS(UART1_BASE), +- .pfn = __phys_to_pfn(UART1_BASE), +- .length = SZ_4K, +- .type = MT_DEVICE +- }, { +-#ifdef CONFIG_MMC_BCM2708 /* broadcom legacy SD */ +- .virtual = IO_ADDRESS(MMCI0_BASE), +- .pfn = __phys_to_pfn(MMCI0_BASE), +- .length = SZ_4K, +- .type = MT_DEVICE +- }, { +-#endif +- .virtual = IO_ADDRESS(DMA_BASE), +- .pfn = __phys_to_pfn(DMA_BASE), +- .length = SZ_4K, +- .type = MT_DEVICE +- }, { +- .virtual = IO_ADDRESS(MCORE_BASE), +- .pfn = __phys_to_pfn(MCORE_BASE), +- .length = SZ_4K, +- .type = MT_DEVICE +- }, { +- .virtual = IO_ADDRESS(ST_BASE), +- .pfn = __phys_to_pfn(ST_BASE), +- .length = SZ_4K, +- .type = MT_DEVICE +- }, { +- .virtual = IO_ADDRESS(USB_BASE), +- .pfn = __phys_to_pfn(USB_BASE), +- .length = SZ_128K, +- .type = MT_DEVICE +- }, { +- .virtual = IO_ADDRESS(PM_BASE), +- .pfn = __phys_to_pfn(PM_BASE), +- .length = SZ_4K, +- .type = MT_DEVICE +- }, { +- .virtual = IO_ADDRESS(GPIO_BASE), +- .pfn = __phys_to_pfn(GPIO_BASE), +- .length = SZ_4K, +- .type = MT_DEVICE +- } ++ .virtual = IO_ADDRESS(ARMCTRL_BASE), ++ .pfn = __phys_to_pfn(ARMCTRL_BASE), ++ .length = SZ_4K, ++ .type = MT_DEVICE}, { ++ .virtual = IO_ADDRESS(UART0_BASE), ++ .pfn = __phys_to_pfn(UART0_BASE), ++ .length = SZ_4K, ++ .type = MT_DEVICE}, { ++ .virtual = ++ IO_ADDRESS(UART1_BASE), ++ .pfn = ++ __phys_to_pfn(UART1_BASE), ++ .length = SZ_4K, ++ .type = MT_DEVICE}, { ++#ifdef CONFIG_MMC_BCM2708 /* broadcom legacy SD */ ++ . ++ virtual ++ = ++ IO_ADDRESS ++ (MMCI0_BASE), ++ .pfn = ++ __phys_to_pfn ++ (MMCI0_BASE), ++ . ++ length = ++ SZ_4K, ++ .type = ++ MT_DEVICE}, ++ { ++#endif ++ .virtual = IO_ADDRESS(DMA_BASE), ++ .pfn = __phys_to_pfn(DMA_BASE), ++ .length = SZ_4K, ++ .type = MT_DEVICE}, { ++ .virtual = IO_ADDRESS(MCORE_BASE), ++ .pfn = __phys_to_pfn(MCORE_BASE), ++ .length = SZ_4K, ++ .type = MT_DEVICE}, { ++ .virtual = ++ IO_ADDRESS(ST_BASE), ++ .pfn = ++ __phys_to_pfn(ST_BASE), ++ .length = SZ_4K, ++ .type = MT_DEVICE}, { ++ . ++ virtual ++ = ++ IO_ADDRESS ++ (USB_BASE), ++ .pfn = ++ __phys_to_pfn ++ (USB_BASE), ++ . ++ length = ++ SZ_128K, ++ .type = ++ MT_DEVICE}, ++ { ++ .virtual = IO_ADDRESS(PM_BASE), ++ .pfn = __phys_to_pfn(PM_BASE), ++ .length = SZ_4K, ++ .type = MT_DEVICE}, { ++ .virtual = IO_ADDRESS(GPIO_BASE), ++ .pfn = __phys_to_pfn(GPIO_BASE), ++ .length = SZ_4K, ++ .type = MT_DEVICE} + }; + + void __init bcm2708_map_io(void) +@@ -140,7 +158,7 @@ + unsigned long frc_clock_ticks32(void) + { + /* STC: a free running counter that increments at the rate of 1MHz */ +- return readl(__io_address(ST_BASE+0x04)); ++ return readl(__io_address(ST_BASE + 0x04)); + } + + unsigned long long frc_clock_ticks63(void) +@@ -162,49 +180,50 @@ + * These are fixed clocks. + */ + static struct clk ref24_clk = { +- .rate = 3000000, /* The UART is clocked at 3MHz via APB_CLK */ ++ .rate = 3000000, /* The UART is clocked at 3MHz via APB_CLK */ + }; ++ + static struct clk osc_clk = { + #ifdef CONFIG_ARCH_BCM2708_CHIPIT +- .rate = 27000000, ++ .rate = 27000000, + #else +- .rate = 500000000, /* ARM clock is set from the VideoCore booter */ ++ .rate = 500000000, /* ARM clock is set from the VideoCore booter */ + #endif + }; ++ + /* warning - the USB needs a clock > 34MHz */ + + #ifdef CONFIG_MMC_BCM2708 + static struct clk sdhost_clk = { + #ifdef CONFIG_ARCH_BCM2708_CHIPIT +- .rate = 4000000, /* 4MHz */ ++ .rate = 4000000, /* 4MHz */ + #else +- .rate = 250000000, /* 250MHz */ ++ .rate = 250000000, /* 250MHz */ + #endif + }; + #endif + + static struct clk_lookup lookups[] = { +- { /* UART0 */ +- .dev_id = "dev:f1", +- .clk = &ref24_clk, +- }, +- { /* USB */ +- .dev_id = "bcm2708_usb", +- .clk = &osc_clk, ++ { /* UART0 */ ++ .dev_id = "dev:f1", ++ .clk = &ref24_clk, ++ }, ++ { /* USB */ ++ .dev_id = "bcm2708_usb", ++ .clk = &osc_clk, + #ifdef CONFIG_MMC_BCM2708 +- }, +- { /* MCI */ +- .dev_id = "bcm2708_mci.0", +- .clk = &sdhost_clk, ++ }, ++ { /* MCI */ ++ .dev_id = "bcm2708_mci.0", ++ .clk = &sdhost_clk, + #endif +- } ++ } + }; + +- + #define UART0_IRQ { IRQ_UART, NO_IRQ } + #define UART0_DMA { 15, 14 } + +-AMBA_DEVICE(uart0, "dev:f1", UART0, NULL); ++AMBA_DEVICE(uart0, "dev:f1", UART0, NULL); + + static struct amba_device *amba_devs[] __initdata = { + &uart0_device, +@@ -212,262 +231,221 @@ + + static struct resource bcm2708_dmaman_resources[] = { + { +- .start = DMA_BASE, +- .end = DMA_BASE + SZ_4K - 1, +- .flags = IORESOURCE_MEM, +- } ++ .start = DMA_BASE, ++ .end = DMA_BASE + SZ_4K - 1, ++ .flags = IORESOURCE_MEM, ++ } + }; + + static struct platform_device bcm2708_dmaman_device = { +- .name = BCM_DMAMAN_DRIVER_NAME, +- .id = 0, /* first bcm2708_dma */ +- .resource = bcm2708_dmaman_resources, +- .num_resources = ARRAY_SIZE(bcm2708_dmaman_resources), ++ .name = BCM_DMAMAN_DRIVER_NAME, ++ .id = 0, /* first bcm2708_dma */ ++ .resource = bcm2708_dmaman_resources, ++ .num_resources = ARRAY_SIZE(bcm2708_dmaman_resources), + }; + + #ifdef CONFIG_MMC_BCM2708 + static struct resource bcm2708_mci_resources[] = { + { +- .start = MMCI0_BASE, +- .end = MMCI0_BASE + SZ_4K - 1, +- .flags = IORESOURCE_MEM, +- }, { +- .start = IRQ_SDIO, +- .end = IRQ_SDIO, +- .flags = IORESOURCE_IRQ, +- } ++ .start = MMCI0_BASE, ++ .end = MMCI0_BASE + SZ_4K - 1, ++ .flags = IORESOURCE_MEM, ++ }, { ++ .start = IRQ_SDIO, ++ .end = IRQ_SDIO, ++ .flags = IORESOURCE_IRQ, ++ } + }; + +- + static struct platform_device bcm2708_mci_device = { +- .name = "bcm2708_mci", +- .id = 0, /* first bcm2708_mci */ +- .resource = bcm2708_mci_resources, +- .num_resources = ARRAY_SIZE(bcm2708_mci_resources), +- .dev = { +- .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON), +- }, ++ .name = "bcm2708_mci", ++ .id = 0, /* first bcm2708_mci */ ++ .resource = bcm2708_mci_resources, ++ .num_resources = ARRAY_SIZE(bcm2708_mci_resources), ++ .dev = { ++ .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON), ++ }, + }; + #endif /* CONFIG_MMC_BCM2708 */ + +- + static u64 fb_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON); + + static struct platform_device bcm2708_fb_device = { +- .name = "bcm2708_fb", +- .id = -1, /* only one bcm2708_fb */ +- .resource = NULL, +- .num_resources = 0, +- .dev = { +- .dma_mask = &fb_dmamask, +- .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON), +- }, ++ .name = "bcm2708_fb", ++ .id = -1, /* only one bcm2708_fb */ ++ .resource = NULL, ++ .num_resources = 0, ++ .dev = { ++ .dma_mask = &fb_dmamask, ++ .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON), ++ }, + }; + + static struct plat_serial8250_port bcm2708_uart1_platform_data[] = { + { +- .mapbase = UART1_BASE + 0x40, +- .irq = IRQ_AUX, +- .uartclk = 125000000, +- .regshift = 2, +- .iotype = UPIO_MEM, +- .flags = UPF_FIXED_TYPE | UPF_IOREMAP | UPF_SKIP_TEST, +- .type = PORT_8250, +- }, +- { }, ++ .mapbase = UART1_BASE + 0x40, ++ .irq = IRQ_AUX, ++ .uartclk = 125000000, ++ .regshift = 2, ++ .iotype = UPIO_MEM, ++ .flags = UPF_FIXED_TYPE | UPF_IOREMAP | UPF_SKIP_TEST, ++ .type = PORT_8250, ++ }, ++ {}, + }; + + static struct platform_device bcm2708_uart1_device = { +- .name = "serial8250", +- .id = PLAT8250_DEV_PLATFORM, +- .dev = { +- .platform_data = bcm2708_uart1_platform_data, +- }, ++ .name = "serial8250", ++ .id = PLAT8250_DEV_PLATFORM, ++ .dev = { ++ .platform_data = bcm2708_uart1_platform_data, ++ }, + }; + + static struct resource bcm2708_usb_resources[] = { +- [0] = { +- .start = USB_BASE, +- .end = USB_BASE + SZ_128K - 1, +- .flags = IORESOURCE_MEM, +- }, +- [1] = { +- .start = IRQ_USB, +- .end = IRQ_USB, +- .flags = IORESOURCE_IRQ, +- }, ++ [0] = { ++ .start = USB_BASE, ++ .end = USB_BASE + SZ_128K - 1, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = IRQ_USB, ++ .end = IRQ_USB, ++ .flags = IORESOURCE_IRQ, ++ }, + }; + + static u64 usb_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON); + + static struct platform_device bcm2708_usb_device = { +- .name = "bcm2708_usb", +- .id = -1, /* only one bcm2708_usb */ +- .resource = bcm2708_usb_resources, +- .num_resources = ARRAY_SIZE(bcm2708_usb_resources), +- .dev = { +- .dma_mask = &usb_dmamask, +- .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON), +- }, ++ .name = "bcm2708_usb", ++ .id = -1, /* only one bcm2708_usb */ ++ .resource = bcm2708_usb_resources, ++ .num_resources = ARRAY_SIZE(bcm2708_usb_resources), ++ .dev = { ++ .dma_mask = &usb_dmamask, ++ .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON), ++ }, + }; + + static struct resource bcm2708_vcio_resources[] = { +- [0] = { /* mailbox/semaphore/doorbell access */ +- .start = MCORE_BASE, +- .end = MCORE_BASE + SZ_4K - 1, +- .flags = IORESOURCE_MEM, +- }, ++ [0] = { /* mailbox/semaphore/doorbell access */ ++ .start = MCORE_BASE, ++ .end = MCORE_BASE + SZ_4K - 1, ++ .flags = IORESOURCE_MEM, ++ }, + }; + + static u64 vcio_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON); + + static struct platform_device bcm2708_vcio_device = { +- .name = BCM_VCIO_DRIVER_NAME, +- .id = -1, /* only one VideoCore I/O area */ +- .resource = bcm2708_vcio_resources, +- .num_resources = ARRAY_SIZE(bcm2708_vcio_resources), +- .dev = { +- .dma_mask = &vcio_dmamask, +- .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON), +- }, ++ .name = BCM_VCIO_DRIVER_NAME, ++ .id = -1, /* only one VideoCore I/O area */ ++ .resource = bcm2708_vcio_resources, ++ .num_resources = ARRAY_SIZE(bcm2708_vcio_resources), ++ .dev = { ++ .dma_mask = &vcio_dmamask, ++ .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON), ++ }, + }; + + #ifdef CONFIG_BCM2708_GPIO + #define BCM_GPIO_DRIVER_NAME "bcm2708_gpio" + + static struct resource bcm2708_gpio_resources[] = { +- [0] = { /* general purpose I/O */ +- .start = GPIO_BASE, +- .end = GPIO_BASE + SZ_4K - 1, +- .flags = IORESOURCE_MEM, +- }, ++ [0] = { /* general purpose I/O */ ++ .start = GPIO_BASE, ++ .end = GPIO_BASE + SZ_4K - 1, ++ .flags = IORESOURCE_MEM, ++ }, + }; + + static u64 gpio_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON); + + static struct platform_device bcm2708_gpio_device = { +- .name = BCM_GPIO_DRIVER_NAME, +- .id = -1, /* only one VideoCore I/O area */ +- .resource = bcm2708_gpio_resources, +- .num_resources = ARRAY_SIZE(bcm2708_gpio_resources), +- .dev = { +- .dma_mask = &gpio_dmamask, +- .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON), +- }, +-}; +-#endif +- +-#ifdef CONFIG_BCM2708_BUTTONS +-static struct resource bcm2708_vcbuttons_resources[] = { +-}; +- +-static u64 vcbuttons_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON); +- +-static struct platform_device bcm2708_vcbuttons_device = { +- .name = "bcm2708_vcbuttons", +- .id = -1, /* only one VideoCore I/O area */ +- .resource = bcm2708_vcbuttons_resources, +- .num_resources = ARRAY_SIZE(bcm2708_vcbuttons_resources), +- .dev = { +- .dma_mask = &vcbuttons_dmamask, +- .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON), +- }, +-}; +-#endif +- +-#ifdef CONFIG_BCM2708_TOUCHSCREEN +-static struct resource bcm2708_vctouch_resources[] = { +-}; +- +-static u64 vctouch_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON); +- +-static struct platform_device bcm2708_vctouch_device = { +- .name = "bcm2708_vctouch", +- .id = -1, /* only one VideoCore I/O area */ +- .resource = bcm2708_vctouch_resources, +- .num_resources = ARRAY_SIZE(bcm2708_vctouch_resources), +- .dev = { +- .dma_mask = &vctouch_dmamask, +- .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON), +- }, ++ .name = BCM_GPIO_DRIVER_NAME, ++ .id = -1, /* only one VideoCore I/O area */ ++ .resource = bcm2708_gpio_resources, ++ .num_resources = ARRAY_SIZE(bcm2708_gpio_resources), ++ .dev = { ++ .dma_mask = &gpio_dmamask, ++ .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON), ++ }, + }; + #endif + + static struct resource bcm2708_systemtimer_resources[] = { +- [0] = { /* system timer access */ +- .start = ST_BASE, +- .end = ST_BASE + SZ_4K - 1, +- .flags = IORESOURCE_MEM, +- }, { +- .start = IRQ_TIMER3, +- .end = IRQ_TIMER3, +- .flags = IORESOURCE_IRQ, +- } +- ++ [0] = { /* system timer access */ ++ .start = ST_BASE, ++ .end = ST_BASE + SZ_4K - 1, ++ .flags = IORESOURCE_MEM, ++ }, { ++ .start = IRQ_TIMER3, ++ .end = IRQ_TIMER3, ++ .flags = IORESOURCE_IRQ, ++ } + + }; + + static u64 systemtimer_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON); + + static struct platform_device bcm2708_systemtimer_device = { +- .name = "bcm2708_systemtimer", +- .id = -1, /* only one VideoCore I/O area */ +- .resource = bcm2708_systemtimer_resources, +- .num_resources = ARRAY_SIZE(bcm2708_systemtimer_resources), +- .dev = { +- .dma_mask = &systemtimer_dmamask, +- .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON), +- }, ++ .name = "bcm2708_systemtimer", ++ .id = -1, /* only one VideoCore I/O area */ ++ .resource = bcm2708_systemtimer_resources, ++ .num_resources = ARRAY_SIZE(bcm2708_systemtimer_resources), ++ .dev = { ++ .dma_mask = &systemtimer_dmamask, ++ .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON), ++ }, + }; + +-#ifdef CONFIG_MMC_SDHCI_BCM2708 /* Arasan emmc SD */ ++#ifdef CONFIG_MMC_SDHCI_BCM2708 /* Arasan emmc SD */ + static struct resource bcm2708_emmc_resources[] = { + [0] = { +- .start = EMMC_BASE, +- .end = EMMC_BASE + SZ_256 - 1, /* we only need this area */ +- /* the memory map actually makes SZ_4K available */ +- .flags = IORESOURCE_MEM, +- }, ++ .start = EMMC_BASE, ++ .end = EMMC_BASE + SZ_256 - 1, /* we only need this area */ ++ /* the memory map actually makes SZ_4K available */ ++ .flags = IORESOURCE_MEM, ++ }, + [1] = { +- .start = IRQ_ARASANSDIO, +- .end = IRQ_ARASANSDIO, +- .flags = IORESOURCE_IRQ, +- }, ++ .start = IRQ_ARASANSDIO, ++ .end = IRQ_ARASANSDIO, ++ .flags = IORESOURCE_IRQ, ++ }, + }; + + static u64 bcm2708_emmc_dmamask = 0xffffffffUL; + + struct platform_device bcm2708_emmc_device = { +- .name = "bcm2708_sdhci", +- .id = 0, +- .num_resources = ARRAY_SIZE(bcm2708_emmc_resources), +- .resource = bcm2708_emmc_resources, +- .dev = { +- .dma_mask = &bcm2708_emmc_dmamask, +- .coherent_dma_mask = 0xffffffffUL +- }, ++ .name = "bcm2708_sdhci", ++ .id = 0, ++ .num_resources = ARRAY_SIZE(bcm2708_emmc_resources), ++ .resource = bcm2708_emmc_resources, ++ .dev = { ++ .dma_mask = &bcm2708_emmc_dmamask, ++ .coherent_dma_mask = 0xffffffffUL}, + }; + #endif /* CONFIG_MMC_SDHCI_BCM2708 */ + + static struct resource bcm2708_powerman_resources[] = { + [0] = { +- .start = PM_BASE, +- .end = PM_BASE + SZ_256 - 1, +- .flags = IORESOURCE_MEM, +- }, ++ .start = PM_BASE, ++ .end = PM_BASE + SZ_256 - 1, ++ .flags = IORESOURCE_MEM, ++ }, + }; + + static u64 powerman_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON); + + struct platform_device bcm2708_powerman_device = { +- .name = "bcm2708_powerman", +- .id = 0, +- .num_resources = ARRAY_SIZE(bcm2708_powerman_resources), +- .resource = bcm2708_powerman_resources, +- .dev = { +- .dma_mask = &powerman_dmamask, +- .coherent_dma_mask = 0xffffffffUL +- }, ++ .name = "bcm2708_powerman", ++ .id = 0, ++ .num_resources = ARRAY_SIZE(bcm2708_powerman_resources), ++ .resource = bcm2708_powerman_resources, ++ .dev = { ++ .dma_mask = &powerman_dmamask, ++ .coherent_dma_mask = 0xffffffffUL}, + }; + + int __init bcm_register_device(struct platform_device *pdev) +@@ -501,30 +479,26 @@ + bcm_register_device(&bcm2708_fb_device); + bcm_register_device(&bcm2708_usb_device); + bcm_register_device(&bcm2708_uart1_device); +-#ifdef CONFIG_BCM2708_BUTTONS +- bcm_register_device(&bcm2708_vcbuttons_device); +-#endif +-#ifdef CONFIG_BCM2708_TOUCHSCREEN +- bcm_register_device(&bcm2708_vctouch_device); +-#endif + bcm_register_device(&bcm2708_powerman_device); + #ifdef CONFIG_MMC_SDHCI_BCM2708 + bcm_register_device(&bcm2708_emmc_device); + #endif +- bcm2708_init_led(); ++ bcm2708_init_led(); + #ifdef CONFIG_BCM2708_VCMEM +-{ +- extern void vc_mem_connected_init(void); +- vc_mem_connected_init(); +-} ++ { ++ extern void vc_mem_connected_init(void); ++ vc_mem_connected_init(); ++ } + #endif + for (i = 0; i < ARRAY_SIZE(amba_devs); i++) { + struct amba_device *d = amba_devs[i]; + amba_device_register(d, &iomem_resource); + } ++ system_rev = boardrev; ++ system_serial_low = serial; + } + +-#define TIMER_PERIOD 10000 /* HZ in microsecs */ ++#define TIMER_PERIOD 10000 /* HZ in microsecs */ + + static void timer_set_mode(enum clock_event_mode mode, + struct clock_event_device *clk) +@@ -533,16 +507,15 @@ + + switch (mode) { + case CLOCK_EVT_MODE_PERIODIC: +- stc = readl(__io_address(ST_BASE+0x04)); +- writel(stc + TIMER_PERIOD, +- __io_address(ST_BASE+0x18));/* stc3 */ ++ stc = readl(__io_address(ST_BASE + 0x04)); ++ writel(stc + TIMER_PERIOD, __io_address(ST_BASE + 0x18)); /* stc3 */ + break; + case CLOCK_EVT_MODE_ONESHOT: + case CLOCK_EVT_MODE_UNUSED: + case CLOCK_EVT_MODE_SHUTDOWN: + default: + printk(KERN_ERR "timer_set_mode: unhandled mode:%d\n", +- (int)mode); ++ (int)mode); + break; + } + +@@ -553,17 +526,17 @@ + { + unsigned long stc; + +- stc = readl(__io_address(ST_BASE + 0x04)); +- writel(stc + TIMER_PERIOD, __io_address(ST_BASE+0x18)); /* stc3 */ ++ stc = readl(__io_address(ST_BASE + 0x04)); ++ writel(stc + TIMER_PERIOD, __io_address(ST_BASE + 0x18)); /* stc3 */ + return 0; + } + +-static struct clock_event_device timer0_clockevent = { +- .name = "timer0", +- .shift = 32, +- .features = CLOCK_EVT_FEAT_ONESHOT, +- .set_mode = timer_set_mode, +- .set_next_event = timer_set_next_event, ++static struct clock_event_device timer0_clockevent = { ++ .name = "timer0", ++ .shift = 32, ++ .features = CLOCK_EVT_FEAT_ONESHOT, ++ .set_mode = timer_set_mode, ++ .set_next_event = timer_set_next_event, + }; + + /* +@@ -573,7 +546,7 @@ + { + struct clock_event_device *evt = &timer0_clockevent; + +- writel(1<<3, __io_address(ST_BASE+0x00)); /* stcs clear timer int */ ++ writel(1 << 3, __io_address(ST_BASE + 0x00)); /* stcs clear timer int */ + + evt->event_handler(evt); + +@@ -581,9 +554,9 @@ + } + + static struct irqaction bcm2708_timer_irq = { +- .name = "BCM2708 Timer Tick", +- .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, +- .handler = bcm2708_timer_interrupt, ++ .name = "BCM2708 Timer Tick", ++ .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, ++ .handler = bcm2708_timer_interrupt, + }; + + /* +@@ -601,18 +574,18 @@ + setup_irq(IRQ_TIMER3, &bcm2708_timer_irq); + + timer0_clockevent.mult = +- div_sc(1000000, NSEC_PER_SEC, timer0_clockevent.shift); ++ div_sc(1000000, NSEC_PER_SEC, timer0_clockevent.shift); + timer0_clockevent.max_delta_ns = +- clockevent_delta2ns(0xffffffff, &timer0_clockevent); ++ clockevent_delta2ns(0xffffffff, &timer0_clockevent); + timer0_clockevent.min_delta_ns = +- clockevent_delta2ns(0xf, &timer0_clockevent); ++ clockevent_delta2ns(0xf, &timer0_clockevent); + + timer0_clockevent.cpumask = cpumask_of(0); + clockevents_register_device(&timer0_clockevent); + } + + struct sys_timer bcm2708_timer = { +- .init = bcm2708_timer_init, ++ .init = bcm2708_timer_init, + }; + + #if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE) +@@ -620,24 +593,24 @@ + + static struct gpio_led bcm2708_leds[] = { + [0] = { +- .gpio = 16, +- .name = "led0", +- .default_trigger = "mmc0", +- .active_low = 0, +- }, ++ .gpio = 16, ++ .name = "led0", ++ .default_trigger = "mmc0", ++ .active_low = 0, ++ }, + }; + + static struct gpio_led_platform_data bcm2708_led_pdata = { +- .num_leds = ARRAY_SIZE(bcm2708_leds), +- .leds = bcm2708_leds, ++ .num_leds = ARRAY_SIZE(bcm2708_leds), ++ .leds = bcm2708_leds, + }; + + static struct platform_device bcm2708_led_device = { +- .name = "leds-gpio", +- .id = -1, +- .dev = { +- .platform_data = &bcm2708_led_pdata, +- }, ++ .name = "leds-gpio", ++ .id = -1, ++ .dev = { ++ .platform_data = &bcm2708_led_pdata, ++ }, + }; + + static void __init bcm2708_init_led(void) +@@ -645,14 +618,14 @@ + platform_device_register(&bcm2708_led_device); + } + #else +-static inline void bcm2708_init_led(void) {} ++static inline void bcm2708_init_led(void) ++{ ++} + #endif + +- + MACHINE_START(BCM2708, "BCM2708") +- /* Maintainer: Broadcom Europe Ltd. */ +- .map_io = bcm2708_map_io, +- .init_irq = bcm2708_init_irq, +- .timer = &bcm2708_timer, +- .init_machine = bcm2708_init, +-MACHINE_END ++ /* Maintainer: Broadcom Europe Ltd. */ ++.map_io = bcm2708_map_io,.init_irq = bcm2708_init_irq,.timer = ++ &bcm2708_timer,.init_machine = ++ bcm2708_init, MACHINE_END module_param(boardrev, uint, 0644); ++module_param(serial, uint, 0644); +Index: linux-3.2.46/drivers/usb/gadget/Kconfig +=================================================================== +--- linux-3.2.46.orig/drivers/usb/gadget/Kconfig 2013-07-26 19:31:19.000000000 +0000 ++++ linux-3.2.46/drivers/usb/gadget/Kconfig 2013-07-26 19:32:11.000000000 +0000 +@@ -566,20 +566,6 @@ + help + Enables LPM support. + +-config USB_GADGET_SNPS_DWC_OTG +- boolean "Synopsys Driver for DWC_otg Controller" +- depends on USB && EXPERIMENTAL +- select USB_OTG +- select USB_GADGET_DUALSPEED +- help +- Selects the Synopsys Driver for the DWC_otg Controller. +- +-config USB_DWC_OTG_LPM +- boolean "Enable LPM support" +- depends on USB && EXPERIMENTAL +- help +- Enables LPM support. +- + # + # USB Gadget Drivers + # +Index: linux-3.2.46/drivers/video/bcm2708_fb.c +=================================================================== +--- linux-3.2.46.orig/drivers/video/bcm2708_fb.c 2013-07-26 19:31:58.000000000 +0000 ++++ linux-3.2.46/drivers/video/bcm2708_fb.c 2013-07-26 19:32:11.000000000 +0000 +@@ -7,7 +7,11 @@ + * License. See the file COPYING in the main directory of this archive + * for more details. + * +- * Broadcom simple framebuffer driver ++ * Broadcom simple framebuffer driver ++ * ++ * This file is derived from cirrusfb.c ++ * Copyright 1999-2001 Jeff Garzik ++ * + */ + #include + #include +@@ -22,6 +26,7 @@ + #include + #include + #include ++#include + + #include + #include +@@ -38,26 +43,24 @@ + /* this data structure describes each frame buffer device we find */ + + struct fbinfo_s { +- int xres, yres, xres_virtual, yres_virtual; +- int pitch, bpp; +- int xoffset, yoffset; +- int base; +- int screen_size; ++ u32 xres, yres, xres_virtual, yres_virtual; ++ u32 pitch, bpp; ++ u32 xoffset, yoffset; ++ u32 base; ++ u32 screen_size; + }; + + struct bcm2708_fb { +- struct fb_info fb; +- struct platform_device *dev; +- void __iomem *regs; +- volatile struct fbinfo_s *info; +- dma_addr_t dma; +- u32 cmap[16]; ++ struct fb_info fb; ++ struct platform_device *dev; ++ struct fbinfo_s *info; ++ dma_addr_t dma; ++ u32 cmap[16]; + }; + + #define to_bcm2708(info) container_of(info, struct bcm2708_fb, fb) + +-static int +-bcm2708_fb_set_bitfields(struct fb_var_screeninfo *var) ++static int bcm2708_fb_set_bitfields(struct fb_var_screeninfo *var) + { + int ret = 0; + +@@ -72,12 +75,12 @@ + case 2: + case 4: + case 8: +- var->red.length = var->bits_per_pixel; +- var->red.offset = 0; +- var->green.length = var->bits_per_pixel; +- var->green.offset = 0; +- var->blue.length = var->bits_per_pixel; +- var->blue.offset = 0; ++ var->red.length = var->bits_per_pixel; ++ var->red.offset = 0; ++ var->green.length = var->bits_per_pixel; ++ var->green.offset = 0; ++ var->blue.length = var->bits_per_pixel; ++ var->blue.offset = 0; + break; + case 16: + var->red.length = 5; +@@ -90,9 +93,9 @@ + var->green.length = 6; + break; + case 32: +- var->red.length = 8; +- var->green.length = 8; +- var->blue.length = 8; ++ var->red.length = 8; ++ var->green.length = 8; ++ var->blue.length = 8; + break; + default: + ret = -EINVAL; +@@ -113,110 +116,119 @@ + return ret; + } + +-static int bcm2708_fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info) ++static int bcm2708_fb_check_var(struct fb_var_screeninfo *var, ++ struct fb_info *info) + { + +- // info input, var output +- int yres; +- /* memory size in pixels */ +- unsigned pixels = info->screen_size * 8 / var->bits_per_pixel; +- +- // info input, var output +- printk(KERN_ERR "bcm2708_fb_check_var info(%p) %dx%d (%dx%d), %d, %d\n", info, info->var.xres, info->var.yres, info->var.xres_virtual, info->var.yres_virtual, (int)info->screen_size, info->var.bits_per_pixel ); +- printk(KERN_ERR "bcm2708_fb_check_var var(%p) %dx%d (%dx%d), %d, %d\n", var, var->xres, var->yres, var->xres_virtual, var->yres_virtual, var->bits_per_pixel, pixels); +- +- if (!var->bits_per_pixel) var->bits_per_pixel = 16; +- +- if (0 && var->bits_per_pixel != 16 && var->bits_per_pixel != 32) { +- printk(KERN_ERR "bcm2708_fb_check_var: ERROR: bits_per_pixel=%d\n", var->bits_per_pixel); +- return -EINVAL; +- } +- +- bcm2708_fb_set_bitfields(var); +- +- if (var->xres_virtual < var->xres) +- var->xres_virtual = var->xres; +- /* use highest possible virtual resolution */ +- if (var->yres_virtual == -1) { +- var->yres_virtual = 480; //pixels / var->xres_virtual; +- +- printk(KERN_ERR +- "bcm2708_fb_check_var: virtual resolution set to maximum of %dx%d\n", +- var->xres_virtual, var->yres_virtual); +- } +- if (var->yres_virtual < var->yres) +- var->yres_virtual = var->yres; +- +- #if 0 +- if (var->xres_virtual * var->yres_virtual > pixels) { +- printk(KERN_ERR "bcm2708_fb_check_var: mode %dx%dx%d rejected... " +- "virtual resolution too high to fit into video memory!\n", +- var->xres_virtual, var->yres_virtual, +- var->bits_per_pixel); +- return -EINVAL; +- } +- #endif +- if (var->xoffset < 0) +- var->xoffset = 0; +- if (var->yoffset < 0) +- var->yoffset = 0; +- +- /* truncate xoffset and yoffset to maximum if too high */ +- if (var->xoffset > var->xres_virtual - var->xres) +- var->xoffset = var->xres_virtual - var->xres - 1; +- if (var->yoffset > var->yres_virtual - var->yres) +- var->yoffset = var->yres_virtual - var->yres - 1; +- +- var->red.msb_right = +- var->green.msb_right = +- var->blue.msb_right = +- var->transp.offset = +- var->transp.length = +- var->transp.msb_right = 0; +- +- yres = var->yres; +- if (var->vmode & FB_VMODE_DOUBLE) +- yres *= 2; +- else if (var->vmode & FB_VMODE_INTERLACED) +- yres = (yres + 1) / 2; +- +- if (yres > 1200) { +- printk(KERN_ERR "bcm2708_fb_check_var: ERROR: VerticalTotal >= 1200; " +- "special treatment required! (TODO)\n"); +- return -EINVAL; +- } ++ /* info input, var output */ ++ int yres; ++ /* memory size in pixels */ ++ unsigned pixels = info->screen_size * 8 / var->bits_per_pixel; ++ ++ /* info input, var output */ ++ pr_info("bcm2708_fb_check_var info(%p) %dx%d (%dx%d), %d, %d\n", info, ++ info->var.xres, info->var.yres, info->var.xres_virtual, ++ info->var.yres_virtual, (int)info->screen_size, ++ info->var.bits_per_pixel); ++ pr_info("bcm2708_fb_check_var var(%p) %dx%d (%dx%d), %d, %d\n", var, ++ var->xres, var->yres, var->xres_virtual, var->yres_virtual, ++ var->bits_per_pixel, pixels); ++ ++ if (!var->bits_per_pixel) ++ var->bits_per_pixel = 16; ++ ++ if (0 && var->bits_per_pixel != 16 && var->bits_per_pixel != 32) { ++ pr_err("bcm2708_fb_check_var: ERROR: bits_per_pixel=%d\n", ++ var->bits_per_pixel); ++ return -EINVAL; ++ } + +- //if (cirrusfb_check_pixclock(var, info)) +- // return -EINVAL; ++ bcm2708_fb_set_bitfields(var); + +- //if (!is_laguna(cinfo)) +- // var->accel_flags = FB_ACCELF_TEXT; ++ if (var->xres_virtual < var->xres) ++ var->xres_virtual = var->xres; ++ /* use highest possible virtual resolution */ ++ if (var->yres_virtual == -1) { ++ var->yres_virtual = 480; ++ ++ pr_err ++ ("bcm2708_fb_check_var: virtual resolution set to maximum of %dx%d\n", ++ var->xres_virtual, var->yres_virtual); ++ } ++ if (var->yres_virtual < var->yres) ++ var->yres_virtual = var->yres; + +- return 0; ++#if 0 ++ if (var->xres_virtual * var->yres_virtual > pixels) { ++ pr_err("bcm2708_fb_check_var: mode %dx%dx%d rejected... " ++ "virtual resolution too high to fit into video memory!\n", ++ var->xres_virtual, var->yres_virtual, ++ var->bits_per_pixel); ++ return -EINVAL; ++ } ++#endif ++ if (var->xoffset < 0) ++ var->xoffset = 0; ++ if (var->yoffset < 0) ++ var->yoffset = 0; ++ ++ /* truncate xoffset and yoffset to maximum if too high */ ++ if (var->xoffset > var->xres_virtual - var->xres) ++ var->xoffset = var->xres_virtual - var->xres - 1; ++ if (var->yoffset > var->yres_virtual - var->yres) ++ var->yoffset = var->yres_virtual - var->yres - 1; ++ ++ var->red.msb_right = ++ var->green.msb_right = ++ var->blue.msb_right = ++ var->transp.offset = var->transp.length = var->transp.msb_right = 0; ++ ++ yres = var->yres; ++ if (var->vmode & FB_VMODE_DOUBLE) ++ yres *= 2; ++ else if (var->vmode & FB_VMODE_INTERLACED) ++ yres = (yres + 1) / 2; ++ ++ if (yres > 1200) { ++ pr_err("bcm2708_fb_check_var: ERROR: VerticalTotal >= 1200; " ++ "special treatment required! (TODO)\n"); ++ return -EINVAL; ++ } ++ ++ return 0; + } + + static int bcm2708_fb_set_par(struct fb_info *info) + { +- unsigned val = 0; ++ unsigned val = 0; + struct bcm2708_fb *fb = to_bcm2708(info); +- volatile struct fbinfo_s *fbinfo = fb->info; +- fbinfo->xres = info->var.xres; +- fbinfo->yres = info->var.yres; +- fbinfo->xres_virtual = info->var.xres_virtual; +- fbinfo->yres_virtual = info->var.yres_virtual; +- fbinfo->bpp = info->var.bits_per_pixel; +- fbinfo->xoffset = info->var.xoffset; +- fbinfo->yoffset = info->var.yoffset; +- fbinfo->base = 0; // filled in by VC +- fbinfo->pitch = 0; // filled in by VC ++ volatile struct fbinfo_s *fbinfo = fb->info; ++ fbinfo->xres = info->var.xres; ++ fbinfo->yres = info->var.yres; ++ fbinfo->xres_virtual = info->var.xres_virtual; ++ fbinfo->yres_virtual = info->var.yres_virtual; ++ fbinfo->bpp = info->var.bits_per_pixel; ++ fbinfo->xoffset = info->var.xoffset; ++ fbinfo->yoffset = info->var.yoffset; ++ fbinfo->base = 0; /* filled in by VC */ ++ fbinfo->pitch = 0; /* filled in by VC */ ++ ++ pr_info("bcm2708_fb_set_par info(%p) %dx%d (%dx%d), %d, %d\n", info, ++ info->var.xres, info->var.yres, info->var.xres_virtual, ++ info->var.yres_virtual, (int)info->screen_size, ++ info->var.bits_per_pixel); + +- printk(KERN_ERR "bcm2708_fb_set_par info(%p) %dx%d (%dx%d), %d, %d\n", info, info->var.xres, info->var.yres, info->var.xres_virtual, info->var.yres_virtual, (int)info->screen_size, info->var.bits_per_pixel ); ++ /* ensure last write to fbinfo is visible to GPU */ ++ wmb(); + +- // inform vc about new framebuffer ++ /* inform vc about new framebuffer */ + bcm_mailbox_write(MBOX_CHAN_FB, fb->dma); + +- // wait for response +- bcm_mailbox_read(MBOX_CHAN_FB, &val); ++ /* wait for response */ ++ bcm_mailbox_read(MBOX_CHAN_FB, &val); ++ ++ /* ensure GPU writes are visible to us */ ++ rmb(); + + fb->fb.fix.line_length = fbinfo->pitch; + +@@ -225,13 +237,21 @@ + else + fb->fb.fix.visual = FB_VISUAL_TRUECOLOR; + +- fb->fb.fix.smem_start = fbinfo->base; +- fb->fb.fix.smem_len = fbinfo->pitch * fbinfo->yres_virtual; +- fb->fb.screen_size = fbinfo->screen_size; +- fb->fb.screen_base = (void *)ioremap_nocache(fb->fb.fix.smem_start, fb->fb.screen_size); +- +- printk(KERN_ERR "BCM2708FB: start = %p,%p,%p width=%d, height=%d, bpp=%d, pitch=%d\n", +- (void *)fb->fb.screen_base, (void *)fb->fb.fix.smem_start, (void *)val, fbinfo->xres, fbinfo->yres, fbinfo->bpp, fbinfo->pitch); ++ fb->fb.fix.smem_start = fbinfo->base; ++ fb->fb.fix.smem_len = fbinfo->pitch * fbinfo->yres_virtual; ++ fb->fb.screen_size = fbinfo->screen_size; ++ if (fb->fb.screen_base) ++ iounmap(fb->fb.screen_base); ++ fb->fb.screen_base = ++ (void *)ioremap_nocache(fb->fb.fix.smem_start, fb->fb.screen_size); ++ if (!fb->fb.screen_base) ++ BUG(); /* what can we do here */ ++ ++ pr_info ++ ("BCM2708FB: start = %p,%p,%p width=%d, height=%d, bpp=%d, pitch=%d\n", ++ (void *)fb->fb.screen_base, (void *)fb->fb.fix.smem_start, ++ (void *)val, fbinfo->xres, fbinfo->yres, fbinfo->bpp, ++ fbinfo->pitch); + + return val; + } +@@ -243,58 +263,61 @@ + return (val >> (16 - bf->length) & mask) << bf->offset; + } + +-static int bcm2708_fb_setcolreg(unsigned int regno, unsigned int red, unsigned int green, +- unsigned int blue, unsigned int transp, struct fb_info *info) ++static int bcm2708_fb_setcolreg(unsigned int regno, unsigned int red, ++ unsigned int green, unsigned int blue, ++ unsigned int transp, struct fb_info *info) + { + struct bcm2708_fb *fb = to_bcm2708(info); + + if (regno < 16) + fb->cmap[regno] = convert_bitfield(transp, &fb->fb.var.transp) | +- convert_bitfield(blue, &fb->fb.var.blue) | +- convert_bitfield(green, &fb->fb.var.green) | +- convert_bitfield(red, &fb->fb.var.red); ++ convert_bitfield(blue, &fb->fb.var.blue) | ++ convert_bitfield(green, &fb->fb.var.green) | ++ convert_bitfield(red, &fb->fb.var.red); + + return regno > 255; + } + + static int bcm2708_fb_blank(int blank_mode, struct fb_info *info) + { +-//printk(KERN_ERR "bcm2708_fb_blank\n"); ++ /*pr_info("bcm2708_fb_blank\n"); */ + return -1; + } + +-static void bcm2708_fb_fillrect(struct fb_info *info, const struct fb_fillrect *rect) ++static void bcm2708_fb_fillrect(struct fb_info *info, ++ const struct fb_fillrect *rect) + { +-// (is called) printk(KERN_ERR "bcm2708_fb_fillrect\n"); ++ /* (is called) pr_info("bcm2708_fb_fillrect\n"); */ + cfb_fillrect(info, rect); + } + +-static void bcm2708_fb_copyarea(struct fb_info *info, const struct fb_copyarea *region) ++static void bcm2708_fb_copyarea(struct fb_info *info, ++ const struct fb_copyarea *region) + { +-//printk(KERN_ERR "bcm2708_fb_copyarea\n"); ++ /*pr_info("bcm2708_fb_copyarea\n"); */ + cfb_copyarea(info, region); + } + +-static void bcm2708_fb_imageblit(struct fb_info *info, const struct fb_image *image) ++static void bcm2708_fb_imageblit(struct fb_info *info, ++ const struct fb_image *image) + { +-// (is called) printk(KERN_ERR "bcm2708_fb_imageblit\n"); ++ /* (is called) pr_info("bcm2708_fb_imageblit\n"); */ + cfb_imageblit(info, image); + } + + static struct fb_ops bcm2708_fb_ops = { +- .owner = THIS_MODULE, +- .fb_check_var = bcm2708_fb_check_var, +- .fb_set_par = bcm2708_fb_set_par, +- .fb_setcolreg = bcm2708_fb_setcolreg, +- .fb_blank = bcm2708_fb_blank, +- .fb_fillrect = bcm2708_fb_fillrect, +- .fb_copyarea = bcm2708_fb_copyarea, +- .fb_imageblit = bcm2708_fb_imageblit, ++ .owner = THIS_MODULE, ++ .fb_check_var = bcm2708_fb_check_var, ++ .fb_set_par = bcm2708_fb_set_par, ++ .fb_setcolreg = bcm2708_fb_setcolreg, ++ .fb_blank = bcm2708_fb_blank, ++ .fb_fillrect = bcm2708_fb_fillrect, ++ .fb_copyarea = bcm2708_fb_copyarea, ++ .fb_imageblit = bcm2708_fb_imageblit, + }; + +-static int FBWIDTH =800; /* module parameter */ +-static int FBHEIGHT =480; /* module parameter */ +- ++static int fbwidth = 800; /* module parameter */ ++static int fbheight = 480; /* module parameter */ + + static int bcm2708_fb_register(struct bcm2708_fb *fb) + { +@@ -302,45 +325,47 @@ + dma_addr_t dma; + void *mem; + +- mem = dma_alloc_coherent(NULL, PAGE_ALIGN(sizeof(*fb->info)), &dma, GFP_KERNEL); ++ mem = ++ dma_alloc_coherent(NULL, PAGE_ALIGN(sizeof(*fb->info)), &dma, ++ GFP_KERNEL); + + if (NULL == mem) { +- printk(KERN_ERR ": unable to allocate fbinfo buffer\n"); ++ pr_err(": unable to allocate fbinfo buffer\n"); + ret = -ENOMEM; + } else { + fb->info = (struct fbinfo_s *)mem; +- fb->dma = dma; +- } +- fb->fb.fbops = &bcm2708_fb_ops; +- fb->fb.flags = FBINFO_FLAG_DEFAULT | FBINFO_HWACCEL_COPYAREA | FBINFO_HWACCEL_FILLRECT | FBINFO_HWACCEL_IMAGEBLIT; +- fb->fb.pseudo_palette = fb->cmap; ++ fb->dma = dma; ++ } ++ fb->fb.fbops = &bcm2708_fb_ops; ++ fb->fb.flags = FBINFO_FLAG_DEFAULT; ++ fb->fb.pseudo_palette = fb->cmap; + + strncpy(fb->fb.fix.id, bcm2708_name, sizeof(fb->fb.fix.id)); +- fb->fb.fix.type = FB_TYPE_PACKED_PIXELS; +- fb->fb.fix.type_aux = 0; +- fb->fb.fix.xpanstep = 0; +- fb->fb.fix.ypanstep = 0; +- fb->fb.fix.ywrapstep = 0; +- fb->fb.fix.accel = FB_ACCEL_NONE; +- +- fb->fb.var.xres = FBWIDTH; +- fb->fb.var.yres = FBHEIGHT; +- fb->fb.var.xres_virtual = FBWIDTH; +- fb->fb.var.yres_virtual = FBHEIGHT; ++ fb->fb.fix.type = FB_TYPE_PACKED_PIXELS; ++ fb->fb.fix.type_aux = 0; ++ fb->fb.fix.xpanstep = 0; ++ fb->fb.fix.ypanstep = 0; ++ fb->fb.fix.ywrapstep = 0; ++ fb->fb.fix.accel = FB_ACCEL_NONE; ++ ++ fb->fb.var.xres = fbwidth; ++ fb->fb.var.yres = fbheight; ++ fb->fb.var.xres_virtual = fbwidth; ++ fb->fb.var.yres_virtual = fbheight; + fb->fb.var.bits_per_pixel = 16; +- fb->fb.var.vmode = FB_VMODE_NONINTERLACED; +- fb->fb.var.activate = FB_ACTIVATE_NOW; +- fb->fb.var.nonstd = 0; +- fb->fb.var.height = FBWIDTH; +- fb->fb.var.width = FBHEIGHT; +- fb->fb.var.accel_flags = 0; +- +- fb->fb.monspecs.hfmin = 0; +- fb->fb.monspecs.hfmax = 100000; +- fb->fb.monspecs.vfmin = 0; +- fb->fb.monspecs.vfmax = 400; ++ fb->fb.var.vmode = FB_VMODE_NONINTERLACED; ++ fb->fb.var.activate = FB_ACTIVATE_NOW; ++ fb->fb.var.nonstd = 0; ++ fb->fb.var.height = fbwidth; ++ fb->fb.var.width = fbheight; ++ fb->fb.var.accel_flags = 0; ++ ++ fb->fb.monspecs.hfmin = 0; ++ fb->fb.monspecs.hfmax = 100000; ++ fb->fb.monspecs.vfmin = 0; ++ fb->fb.monspecs.vfmax = 400; + fb->fb.monspecs.dclkmin = 1000000; +- fb->fb.monspecs.dclkmax = 100000000; ++ fb->fb.monspecs.dclkmax = 100000000; + + bcm2708_fb_set_bitfields(&fb->fb.var); + +@@ -350,17 +375,16 @@ + + fb_set_var(&fb->fb, &fb->fb.var); + +- printk(KERN_INFO "BCM2708FB: registering framebuffer (%d, %d)\n", FBWIDTH, FBHEIGHT); ++ pr_info("BCM2708FB: registering framebuffer (%d, %d)\n", fbwidth, ++ fbheight); + + ret = register_framebuffer(&fb->fb); +- printk(KERN_ERR "BCM2708FB: register framebuffer (%d)\n", ret); ++ pr_info("BCM2708FB: register framebuffer (%d)\n", ret); + if (ret == 0) + goto out; + +- printk(KERN_ERR "BCM2708FB: cannot register framebuffer (%d)\n", ret); +- +- iounmap(fb->regs); +- out: ++ pr_info("BCM2708FB: cannot register framebuffer (%d)\n", ret); ++out: + return ret; + } + +@@ -371,7 +395,8 @@ + + fb = kmalloc(sizeof(struct bcm2708_fb), GFP_KERNEL); + if (!fb) { +- dev_err(&dev->dev, "could not allocate new bcm2708_fb struct\n"); ++ dev_err(&dev->dev, ++ "could not allocate new bcm2708_fb struct\n"); + ret = -ENOMEM; + goto free_region; + } +@@ -386,9 +411,9 @@ + } + + kfree(fb); +- free_region: ++free_region: + dev_err(&dev->dev, "probe failed, err %d\n", ret); +- out: ++out: + return ret; + } + +@@ -398,22 +423,24 @@ + + platform_set_drvdata(dev, NULL); + ++ if (fb->fb.screen_base) ++ iounmap(fb->fb.screen_base); + unregister_framebuffer(&fb->fb); +- iounmap(fb->regs); + +- dma_free_coherent(NULL, PAGE_ALIGN(sizeof(*fb->info)), (void *)fb->info, fb->dma); ++ dma_free_coherent(NULL, PAGE_ALIGN(sizeof(*fb->info)), (void *)fb->info, ++ fb->dma); + kfree(fb); + + return 0; + } + + static struct platform_driver bcm2708_fb_driver = { +- .probe = bcm2708_fb_probe, +- .remove = bcm2708_fb_remove, +- .driver = { +- .name = DRIVER_NAME, +- .owner = THIS_MODULE, +- }, ++ .probe = bcm2708_fb_probe, ++ .remove = bcm2708_fb_remove, ++ .driver = { ++ .name = DRIVER_NAME, ++ .owner = THIS_MODULE, ++ }, + }; + + static int __init bcm2708_fb_init(void) +@@ -430,11 +457,11 @@ + + module_exit(bcm2708_fb_exit); + +-module_param(FBWIDTH, int, 0644); +-module_param(FBHEIGHT, int, 0644); ++module_param(fbwidth, int, 0644); ++module_param(fbheight, int, 0644); + + MODULE_DESCRIPTION("BCM2708 framebuffer driver"); + MODULE_LICENSE("GPL"); + +-MODULE_PARM_DESC(FBWIDTH, "Width of ARM Framebuffer"); +-MODULE_PARM_DESC(FBHEIGHT, "Height of ARM Framebuffer"); ++MODULE_PARM_DESC(fbwidth, "Width of ARM Framebuffer"); ++MODULE_PARM_DESC(fbheight, "Height of ARM Framebuffer"); diff -Nru linux-3.2.46/debian/patches/rpi/rpi_108_637034a7c44631ea517b24f5bb2eab54b663fea9.patch linux-3.2.46/debian/patches/rpi/rpi_108_637034a7c44631ea517b24f5bb2eab54b663fea9.patch --- linux-3.2.46/debian/patches/rpi/rpi_108_637034a7c44631ea517b24f5bb2eab54b663fea9.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_108_637034a7c44631ea517b24f5bb2eab54b663fea9.patch 2013-07-26 19:32:14.000000000 +0000 @@ -0,0 +1,1784 @@ +commit 637034a7c44631ea517b24f5bb2eab54b663fea9 +Author: Dom Cobley +Date: Wed Feb 1 21:35:47 2012 +0000 + + Build anything reasonable as a module. Thanks to asb + +Index: linux-3.2.46/arch/arm/configs/bcmrpi_cutdown_defconfig +=================================================================== +--- linux-3.2.46.orig/arch/arm/configs/bcmrpi_cutdown_defconfig 2013-07-26 19:31:51.000000000 +0000 ++++ linux-3.2.46/arch/arm/configs/bcmrpi_cutdown_defconfig 2013-07-26 19:32:13.000000000 +0000 +@@ -1,1307 +1,415 @@ +-# +-# Automatically generated file; DO NOT EDIT. +-# Linux/arm 3.1.9 Kernel Configuration +-# +-CONFIG_ARM=y +-CONFIG_SYS_SUPPORTS_APM_EMULATION=y +-CONFIG_GENERIC_GPIO=y +-# CONFIG_ARCH_USES_GETTIMEOFFSET is not set +-CONFIG_GENERIC_CLOCKEVENTS=y +-CONFIG_KTIME_SCALAR=y +-CONFIG_HAVE_PROC_CPU=y +-CONFIG_STACKTRACE_SUPPORT=y +-CONFIG_HAVE_LATENCYTOP_SUPPORT=y +-CONFIG_LOCKDEP_SUPPORT=y +-CONFIG_TRACE_IRQFLAGS_SUPPORT=y +-CONFIG_HARDIRQS_SW_RESEND=y +-CONFIG_GENERIC_IRQ_PROBE=y +-CONFIG_RWSEM_GENERIC_SPINLOCK=y +-CONFIG_ARCH_HAS_CPU_IDLE_WAIT=y +-CONFIG_GENERIC_HWEIGHT=y +-CONFIG_GENERIC_CALIBRATE_DELAY=y +-CONFIG_NEED_DMA_MAP_STATE=y +-CONFIG_VECTORS_BASE=0xffff0000 +-# CONFIG_ARM_PATCH_PHYS_VIRT is not set +-CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +-CONFIG_HAVE_IRQ_WORK=y +- +-# +-# General setup +-# + CONFIG_EXPERIMENTAL=y +-CONFIG_BROKEN_ON_SMP=y +-CONFIG_INIT_ENV_ARG_LIMIT=32 +-CONFIG_CROSS_COMPILE="" +-CONFIG_LOCALVERSION="" + # CONFIG_LOCALVERSION_AUTO is not set +-CONFIG_HAVE_KERNEL_GZIP=y +-CONFIG_HAVE_KERNEL_LZMA=y +-CONFIG_HAVE_KERNEL_LZO=y +-CONFIG_KERNEL_GZIP=y +-# CONFIG_KERNEL_LZMA is not set +-# CONFIG_KERNEL_LZO is not set +-CONFIG_DEFAULT_HOSTNAME="(none)" +-CONFIG_SWAP=y + CONFIG_SYSVIPC=y +-CONFIG_SYSVIPC_SYSCTL=y + CONFIG_POSIX_MQUEUE=y +-CONFIG_POSIX_MQUEUE_SYSCTL=y +-# CONFIG_BSD_PROCESS_ACCT is not set +-# CONFIG_FHANDLE is not set +-# CONFIG_TASKSTATS is not set +-# CONFIG_AUDIT is not set +-CONFIG_HAVE_GENERIC_HARDIRQS=y +- +-# +-# IRQ subsystem +-# +-CONFIG_GENERIC_HARDIRQS=y +-CONFIG_HAVE_SPARSE_IRQ=y +-CONFIG_GENERIC_IRQ_SHOW=y +-# CONFIG_SPARSE_IRQ is not set +- +-# +-# RCU Subsystem +-# +-CONFIG_TINY_RCU=y +-# CONFIG_PREEMPT_RCU is not set +-# CONFIG_RCU_TRACE is not set +-# CONFIG_TREE_RCU_TRACE is not set + CONFIG_IKCONFIG=y + CONFIG_IKCONFIG_PROC=y +-CONFIG_LOG_BUF_SHIFT=17 +-# CONFIG_CGROUPS is not set +-# CONFIG_NAMESPACES is not set +-# CONFIG_SCHED_AUTOGROUP is not set +-# CONFIG_SYSFS_DEPRECATED is not set +-# CONFIG_RELAY is not set +-# CONFIG_BLK_DEV_INITRD is not set +-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +-CONFIG_SYSCTL=y +-CONFIG_ANON_INODES=y +-CONFIG_EXPERT=y + # CONFIG_UID16 is not set +-CONFIG_SYSCTL_SYSCALL=y + # CONFIG_KALLSYMS is not set +-CONFIG_HOTPLUG=y +-CONFIG_PRINTK=y +-CONFIG_BUG=y +-# CONFIG_ELF_CORE is not set +-CONFIG_BASE_FULL=y +-CONFIG_FUTEX=y +-CONFIG_EPOLL=y +-CONFIG_SIGNALFD=y +-CONFIG_TIMERFD=y +-CONFIG_EVENTFD=y +-CONFIG_SHMEM=y +-CONFIG_AIO=y + CONFIG_EMBEDDED=y +-CONFIG_HAVE_PERF_EVENTS=y +-CONFIG_PERF_USE_VMALLOC=y +- +-# +-# Kernel Performance Events And Counters +-# +-# CONFIG_PERF_EVENTS is not set +-# CONFIG_PERF_COUNTERS is not set + # CONFIG_VM_EVENT_COUNTERS is not set + # CONFIG_COMPAT_BRK is not set + CONFIG_SLAB=y +-# CONFIG_SLUB is not set +-# CONFIG_SLOB is not set +-# CONFIG_PROFILING is not set +-CONFIG_HAVE_OPROFILE=y +-# CONFIG_KPROBES is not set +-CONFIG_HAVE_KPROBES=y +-CONFIG_HAVE_KRETPROBES=y +-CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y +-CONFIG_HAVE_CLK=y +-CONFIG_HAVE_DMA_API_DEBUG=y +- +-# +-# GCOV-based kernel profiling +-# +-CONFIG_HAVE_GENERIC_DMA_COHERENT=y +-CONFIG_SLABINFO=y +-CONFIG_RT_MUTEXES=y +-CONFIG_BASE_SMALL=0 + CONFIG_MODULES=y +-# CONFIG_MODULE_FORCE_LOAD is not set + CONFIG_MODULE_UNLOAD=y +-# CONFIG_MODULE_FORCE_UNLOAD is not set + CONFIG_MODVERSIONS=y + CONFIG_MODULE_SRCVERSION_ALL=y +-CONFIG_BLOCK=y +-CONFIG_LBDAF=y + # CONFIG_BLK_DEV_BSG is not set +-# CONFIG_BLK_DEV_BSGLIB is not set +-# CONFIG_BLK_DEV_INTEGRITY is not set +- +-# +-# IO Schedulers +-# +-CONFIG_IOSCHED_NOOP=y +-CONFIG_IOSCHED_DEADLINE=y +-CONFIG_IOSCHED_CFQ=y +-# CONFIG_DEFAULT_DEADLINE is not set +-CONFIG_DEFAULT_CFQ=y +-# CONFIG_DEFAULT_NOOP is not set +-CONFIG_DEFAULT_IOSCHED="cfq" +-# CONFIG_INLINE_SPIN_TRYLOCK is not set +-# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set +-# CONFIG_INLINE_SPIN_LOCK is not set +-# CONFIG_INLINE_SPIN_LOCK_BH is not set +-# CONFIG_INLINE_SPIN_LOCK_IRQ is not set +-# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set +-CONFIG_INLINE_SPIN_UNLOCK=y +-# CONFIG_INLINE_SPIN_UNLOCK_BH is not set +-CONFIG_INLINE_SPIN_UNLOCK_IRQ=y +-# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set +-# CONFIG_INLINE_READ_TRYLOCK is not set +-# CONFIG_INLINE_READ_LOCK is not set +-# CONFIG_INLINE_READ_LOCK_BH is not set +-# CONFIG_INLINE_READ_LOCK_IRQ is not set +-# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set +-CONFIG_INLINE_READ_UNLOCK=y +-# CONFIG_INLINE_READ_UNLOCK_BH is not set +-CONFIG_INLINE_READ_UNLOCK_IRQ=y +-# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set +-# CONFIG_INLINE_WRITE_TRYLOCK is not set +-# CONFIG_INLINE_WRITE_LOCK is not set +-# CONFIG_INLINE_WRITE_LOCK_BH is not set +-# CONFIG_INLINE_WRITE_LOCK_IRQ is not set +-# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set +-CONFIG_INLINE_WRITE_UNLOCK=y +-# CONFIG_INLINE_WRITE_UNLOCK_BH is not set +-CONFIG_INLINE_WRITE_UNLOCK_IRQ=y +-# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set +-# CONFIG_MUTEX_SPIN_ON_OWNER is not set +-CONFIG_FREEZER=y +- +-# +-# System Type +-# +-CONFIG_MMU=y +-# CONFIG_ARCH_INTEGRATOR is not set +-# CONFIG_ARCH_REALVIEW is not set +-# CONFIG_ARCH_VERSATILE is not set +-# CONFIG_ARCH_VEXPRESS is not set +-# CONFIG_ARCH_AT91 is not set +-# CONFIG_ARCH_BCMRING is not set +-# CONFIG_ARCH_CLPS711X is not set +-# CONFIG_ARCH_CNS3XXX is not set +-# CONFIG_ARCH_GEMINI is not set +-# CONFIG_ARCH_PRIMA2 is not set +-# CONFIG_ARCH_EBSA110 is not set +-# CONFIG_ARCH_EP93XX is not set +-# CONFIG_ARCH_FOOTBRIDGE is not set +-# CONFIG_ARCH_MXC is not set +-# CONFIG_ARCH_MXS is not set +-# CONFIG_ARCH_NETX is not set +-# CONFIG_ARCH_H720X is not set +-# CONFIG_ARCH_IOP13XX is not set +-# CONFIG_ARCH_IOP32X is not set +-# CONFIG_ARCH_IOP33X is not set +-# CONFIG_ARCH_IXP23XX is not set +-# CONFIG_ARCH_IXP2000 is not set +-# CONFIG_ARCH_IXP4XX is not set +-# CONFIG_ARCH_DOVE is not set +-# CONFIG_ARCH_KIRKWOOD is not set +-# CONFIG_ARCH_LPC32XX is not set +-# CONFIG_ARCH_MV78XX0 is not set +-# CONFIG_ARCH_ORION5X is not set +-# CONFIG_ARCH_MMP is not set +-# CONFIG_ARCH_KS8695 is not set +-# CONFIG_ARCH_W90X900 is not set +-# CONFIG_ARCH_NUC93X is not set +-# CONFIG_ARCH_TEGRA is not set +-# CONFIG_ARCH_PNX4008 is not set +-# CONFIG_ARCH_PXA is not set +-# CONFIG_ARCH_MSM is not set +-# CONFIG_ARCH_SHMOBILE is not set +-# CONFIG_ARCH_RPC is not set +-# CONFIG_ARCH_SA1100 is not set +-# CONFIG_ARCH_S3C2410 is not set +-# CONFIG_ARCH_S3C64XX is not set +-# CONFIG_ARCH_S5P64X0 is not set +-# CONFIG_ARCH_S5PC100 is not set +-# CONFIG_ARCH_S5PV210 is not set +-# CONFIG_ARCH_EXYNOS4 is not set +-# CONFIG_ARCH_SHARK is not set +-# CONFIG_ARCH_TCC_926 is not set +-# CONFIG_ARCH_U300 is not set +-# CONFIG_ARCH_U8500 is not set +-# CONFIG_ARCH_NOMADIK is not set +-# CONFIG_ARCH_DAVINCI is not set +-# CONFIG_ARCH_OMAP is not set +-# CONFIG_PLAT_SPEAR is not set + CONFIG_ARCH_BCM2708=y +-# CONFIG_ARCH_VT8500 is not set +-# CONFIG_ARCH_ZYNQ is not set +- +-# +-# System MMU +-# +- +-# +-# Broadcom BCM2708 Implementations +-# +-CONFIG_MACH_BCM2708=y +-CONFIG_BCM2708_GPIO=y +-CONFIG_BCM2708_VCMEM=y +- +-# +-# Processor Type +-# +-CONFIG_CPU_V6=y +-CONFIG_CPU_32v6=y +-CONFIG_CPU_ABRT_EV6=y +-CONFIG_CPU_PABRT_V6=y +-CONFIG_CPU_CACHE_V6=y +-CONFIG_CPU_CACHE_VIPT=y +-CONFIG_CPU_COPY_V6=y +-CONFIG_CPU_TLB_V6=y +-CONFIG_CPU_HAS_ASID=y +-CONFIG_CPU_CP15=y +-CONFIG_CPU_CP15_MMU=y +-CONFIG_CPU_USE_DOMAINS=y +- +-# +-# Processor Features +-# +-CONFIG_ARM_THUMB=y +-# CONFIG_CPU_ICACHE_DISABLE is not set +-# CONFIG_CPU_DCACHE_DISABLE is not set +-# CONFIG_CPU_BPREDICT_DISABLE is not set +-CONFIG_ARM_L1_CACHE_SHIFT=5 +-CONFIG_ARM_DMA_MEM_BUFFERABLE=y +-CONFIG_CPU_HAS_PMU=y +-CONFIG_ARM_ERRATA_411920=y +-# CONFIG_ARM_ERRATA_364296 is not set +- +-# +-# Bus support +-# +-CONFIG_ARM_AMBA=y +-# CONFIG_PCI_SYSCALL is not set +-# CONFIG_ARCH_SUPPORTS_MSI is not set +-# CONFIG_PCCARD is not set +- +-# +-# Kernel Features +-# +-CONFIG_TICK_ONESHOT=y + CONFIG_NO_HZ=y +-# CONFIG_HIGH_RES_TIMERS is not set +-CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +-CONFIG_VMSPLIT_3G=y +-# CONFIG_VMSPLIT_2G is not set +-# CONFIG_VMSPLIT_1G is not set +-CONFIG_PAGE_OFFSET=0xC0000000 +-CONFIG_PREEMPT_NONE=y +-# CONFIG_PREEMPT_VOLUNTARY is not set +-# CONFIG_PREEMPT is not set +-CONFIG_HZ=100 + CONFIG_AEABI=y +-CONFIG_OABI_COMPAT=y +-# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +-# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +-CONFIG_HAVE_ARCH_PFN_VALID=y +-# CONFIG_HIGHMEM is not set +-CONFIG_SELECT_MEMORY_MODEL=y +-CONFIG_FLATMEM_MANUAL=y +-CONFIG_FLATMEM=y +-CONFIG_FLAT_NODE_MEM_MAP=y +-CONFIG_HAVE_MEMBLOCK=y +-CONFIG_PAGEFLAGS_EXTENDED=y +-CONFIG_SPLIT_PTLOCK_CPUS=4 +-# CONFIG_COMPACTION is not set +-# CONFIG_PHYS_ADDR_T_64BIT is not set +-CONFIG_ZONE_DMA_FLAG=0 +-CONFIG_VIRT_TO_BUS=y +-# CONFIG_KSM is not set +-CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +-CONFIG_NEED_PER_CPU_KM=y +-# CONFIG_CLEANCACHE is not set +-CONFIG_FORCE_MAX_ZONEORDER=11 +-CONFIG_ALIGNMENT_TRAP=y +-# CONFIG_UACCESS_WITH_MEMCPY is not set +-# CONFIG_SECCOMP is not set +-# CONFIG_CC_STACKPROTECTOR is not set +-# CONFIG_DEPRECATED_PARAM_STRUCT is not set +- +-# +-# Boot options +-# +-# CONFIG_USE_OF is not set + CONFIG_ZBOOT_ROM_TEXT=0x0 + CONFIG_ZBOOT_ROM_BSS=0x0 + CONFIG_CMDLINE="dwc_otg.lpm_enable=0 console=ttyAMA0,115200 kgdboc=ttyAMA0,115200 root=/dev/mmcblk0p2 rootfstype=ext3 rootwait" +-CONFIG_CMDLINE_FROM_BOOTLOADER=y +-# CONFIG_CMDLINE_EXTEND is not set +-# CONFIG_CMDLINE_FORCE is not set +-# CONFIG_XIP_KERNEL is not set +-# CONFIG_KEXEC is not set +-# CONFIG_CRASH_DUMP is not set +-# CONFIG_AUTO_ZRELADDR is not set +- +-# +-# CPU Power Management +-# + CONFIG_CPU_IDLE=y +-CONFIG_CPU_IDLE_GOV_LADDER=y +-CONFIG_CPU_IDLE_GOV_MENU=y +- +-# +-# Floating point emulation +-# +- +-# +-# At least one emulation must be selected +-# +-# CONFIG_FPE_NWFPE is not set +-# CONFIG_FPE_FASTFPE is not set + CONFIG_VFP=y +- +-# +-# Userspace binary formats +-# +-CONFIG_BINFMT_ELF=y +-CONFIG_HAVE_AOUT=y +-# CONFIG_BINFMT_AOUT is not set +-# CONFIG_BINFMT_MISC is not set +- +-# +-# Power management options +-# +-CONFIG_SUSPEND=y +-CONFIG_SUSPEND_FREEZER=y +-CONFIG_PM_SLEEP=y +-# CONFIG_PM_RUNTIME is not set +-CONFIG_PM=y +-# CONFIG_PM_DEBUG is not set +-# CONFIG_APM_EMULATION is not set +-CONFIG_PM_CLK=y +-CONFIG_ARCH_SUSPEND_POSSIBLE=y ++CONFIG_BINFMT_MISC=m + CONFIG_NET=y +- +-# +-# Networking options +-# + CONFIG_PACKET=y + CONFIG_UNIX=y +-CONFIG_XFRM=y + CONFIG_XFRM_USER=y +-# CONFIG_XFRM_SUB_POLICY is not set +-# CONFIG_XFRM_MIGRATE is not set +-# CONFIG_XFRM_STATISTICS is not set + CONFIG_NET_KEY=m +-# CONFIG_NET_KEY_MIGRATE is not set + CONFIG_INET=y + CONFIG_IP_MULTICAST=y +-# CONFIG_IP_ADVANCED_ROUTER is not set + CONFIG_IP_PNP=y + CONFIG_IP_PNP_DHCP=y +-# CONFIG_IP_PNP_BOOTP is not set + CONFIG_IP_PNP_RARP=y +-# CONFIG_NET_IPIP is not set +-# CONFIG_NET_IPGRE_DEMUX is not set +-# CONFIG_IP_MROUTE is not set +-# CONFIG_ARPD is not set + CONFIG_SYN_COOKIES=y +-# CONFIG_INET_AH is not set +-# CONFIG_INET_ESP is not set +-# CONFIG_INET_IPCOMP is not set +-# CONFIG_INET_XFRM_TUNNEL is not set +-# CONFIG_INET_TUNNEL is not set + # CONFIG_INET_XFRM_MODE_TRANSPORT is not set + # CONFIG_INET_XFRM_MODE_TUNNEL is not set + # CONFIG_INET_XFRM_MODE_BEET is not set + # CONFIG_INET_LRO is not set + # CONFIG_INET_DIAG is not set +-# CONFIG_TCP_CONG_ADVANCED is not set +-CONFIG_TCP_CONG_CUBIC=y +-CONFIG_DEFAULT_TCP_CONG="cubic" +-# CONFIG_TCP_MD5SIG is not set + # CONFIG_IPV6 is not set +-# CONFIG_NETWORK_SECMARK is not set +-# CONFIG_NETWORK_PHY_TIMESTAMPING is not set +-# CONFIG_NETFILTER is not set +-# CONFIG_IP_DCCP is not set +-# CONFIG_IP_SCTP is not set +-# CONFIG_RDS is not set +-# CONFIG_TIPC is not set +-# CONFIG_ATM is not set +-# CONFIG_L2TP is not set +-# CONFIG_BRIDGE is not set +-# CONFIG_NET_DSA is not set +-# CONFIG_VLAN_8021Q is not set +-# CONFIG_DECNET is not set +-# CONFIG_LLC2 is not set +-# CONFIG_IPX is not set +-# CONFIG_ATALK is not set +-# CONFIG_X25 is not set +-# CONFIG_LAPB is not set +-# CONFIG_ECONET is not set +-# CONFIG_WAN_ROUTER is not set +-# CONFIG_PHONET is not set +-# CONFIG_IEEE802154 is not set +-# CONFIG_NET_SCHED is not set +-# CONFIG_DCB is not set +-CONFIG_DNS_RESOLVER=y +-# CONFIG_BATMAN_ADV is not set +- +-# +-# Network testing +-# + CONFIG_NET_PKTGEN=m +-# CONFIG_HAMRADIO is not set +-# CONFIG_CAN is not set +-# CONFIG_IRDA is not set +-# CONFIG_BT is not set +-# CONFIG_AF_RXRPC is not set +-CONFIG_WIRELESS=y +-CONFIG_WEXT_CORE=y +-CONFIG_WEXT_PROC=y +-CONFIG_CFG80211=y +-# CONFIG_NL80211_TESTMODE is not set +-# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set +-# CONFIG_CFG80211_REG_DEBUG is not set +-CONFIG_CFG80211_DEFAULT_PS=y +-# CONFIG_CFG80211_INTERNAL_REGDB is not set +-CONFIG_CFG80211_WEXT=y +-CONFIG_WIRELESS_EXT_SYSFS=y +-# CONFIG_LIB80211 is not set +-# CONFIG_MAC80211 is not set +-# CONFIG_WIMAX is not set +-# CONFIG_RFKILL is not set +-# CONFIG_NET_9P is not set +-# CONFIG_CAIF is not set +-# CONFIG_CEPH_LIB is not set +-# CONFIG_NFC is not set +- +-# +-# Device Drivers +-# +- +-# +-# Generic Driver Options +-# ++CONFIG_IRDA=m ++CONFIG_IRLAN=m ++CONFIG_IRCOMM=m ++CONFIG_IRDA_ULTRA=y ++CONFIG_IRDA_CACHE_LAST_LSAP=y ++CONFIG_IRDA_FAST_RR=y ++CONFIG_IRTTY_SIR=m ++CONFIG_KINGSUN_DONGLE=m ++CONFIG_KSDAZZLE_DONGLE=m ++CONFIG_KS959_DONGLE=m ++CONFIG_USB_IRDA=m ++CONFIG_SIGMATEL_FIR=m ++CONFIG_MCS_FIR=m ++CONFIG_BT=m ++CONFIG_BT_L2CAP=y ++CONFIG_BT_SCO=y ++CONFIG_BT_RFCOMM=m ++CONFIG_BT_RFCOMM_TTY=y ++CONFIG_BT_BNEP=m ++CONFIG_BT_BNEP_MC_FILTER=y ++CONFIG_BT_BNEP_PROTO_FILTER=y ++CONFIG_BT_HIDP=m ++CONFIG_BT_HCIBTUSB=m ++CONFIG_BT_HCIBCM203X=m ++CONFIG_BT_HCIBPA10X=m ++CONFIG_BT_HCIBFUSB=m ++CONFIG_BT_HCIVHCI=m ++CONFIG_BT_MRVL=m ++CONFIG_BT_MRVL_SDIO=m ++CONFIG_BT_ATH3K=m ++CONFIG_CFG80211=m ++CONFIG_MAC80211=m ++CONFIG_MAC80211_RC_PID=y ++CONFIG_MAC80211_MESH=y ++CONFIG_WIMAX=m ++CONFIG_NET_9P=m ++CONFIG_NFC=m ++CONFIG_NFC_PN533=m + CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +-# CONFIG_DEVTMPFS is not set +-CONFIG_STANDALONE=y +-CONFIG_PREVENT_FIRMWARE_BUILD=y +-CONFIG_FW_LOADER=y +-CONFIG_FIRMWARE_IN_KERNEL=y +-CONFIG_EXTRA_FIRMWARE="" +-# CONFIG_DEBUG_DRIVER is not set +-# CONFIG_DEBUG_DEVRES is not set +-# CONFIG_SYS_HYPERVISOR is not set +-# CONFIG_CONNECTOR is not set +-# CONFIG_MTD is not set +-# CONFIG_PARPORT is not set +-CONFIG_BLK_DEV=y +-# CONFIG_BLK_DEV_COW_COMMON is not set + CONFIG_BLK_DEV_LOOP=y +-CONFIG_BLK_DEV_LOOP_MIN_COUNT=8 +-# CONFIG_BLK_DEV_CRYPTOLOOP is not set +- +-# +-# DRBD disabled because PROC_FS, INET or CONNECTOR not selected +-# +-# CONFIG_BLK_DEV_NBD is not set +-# CONFIG_BLK_DEV_UB is not set ++CONFIG_BLK_DEV_CRYPTOLOOP=m ++CONFIG_BLK_DEV_NBD=m + CONFIG_BLK_DEV_RAM=y +-CONFIG_BLK_DEV_RAM_COUNT=16 +-CONFIG_BLK_DEV_RAM_SIZE=4096 +-# CONFIG_BLK_DEV_XIP is not set +-# CONFIG_CDROM_PKTCDVD is not set +-# CONFIG_ATA_OVER_ETH is not set +-# CONFIG_MG_DISK is not set +-# CONFIG_BLK_DEV_RBD is not set +-# CONFIG_SENSORS_LIS3LV02D is not set ++CONFIG_CDROM_PKTCDVD=m + CONFIG_MISC_DEVICES=y +-# CONFIG_ENCLOSURE_SERVICES is not set +-# CONFIG_C2PORT is not set +- +-# +-# EEPROM support +-# +-# CONFIG_EEPROM_93CX6 is not set +-# CONFIG_IWMC3200TOP is not set +- +-# +-# Texas Instruments shared transport line discipline +-# +-# CONFIG_TI_ST is not set +-CONFIG_BCM2708_VCHIQ=y +-CONFIG_HAVE_IDE=y +-# CONFIG_IDE is not set +- +-# +-# SCSI device support +-# +-CONFIG_SCSI_MOD=y +-# CONFIG_RAID_ATTRS is not set + CONFIG_SCSI=y +-CONFIG_SCSI_DMA=y +-# CONFIG_SCSI_TGT is not set +-# CONFIG_SCSI_NETLINK is not set + # CONFIG_SCSI_PROC_FS is not set +- +-# +-# SCSI support type (disk, tape, CD-ROM) +-# + CONFIG_BLK_DEV_SD=m +-# CONFIG_CHR_DEV_ST is not set +-# CONFIG_CHR_DEV_OSST is not set + CONFIG_BLK_DEV_SR=m +-# CONFIG_BLK_DEV_SR_VENDOR is not set +-# CONFIG_CHR_DEV_SG is not set +-# CONFIG_CHR_DEV_SCH is not set + CONFIG_SCSI_MULTI_LUN=y +-# CONFIG_SCSI_CONSTANTS is not set +-# CONFIG_SCSI_LOGGING is not set +-# CONFIG_SCSI_SCAN_ASYNC is not set +-CONFIG_SCSI_WAIT_SCAN=m +- +-# +-# SCSI Transports +-# +-# CONFIG_SCSI_SPI_ATTRS is not set +-# CONFIG_SCSI_FC_ATTRS is not set +-# CONFIG_SCSI_ISCSI_ATTRS is not set +-# CONFIG_SCSI_SAS_ATTRS is not set +-# CONFIG_SCSI_SAS_LIBSAS is not set +-# CONFIG_SCSI_SRP_ATTRS is not set + # CONFIG_SCSI_LOWLEVEL is not set +-# CONFIG_SCSI_DH is not set +-# CONFIG_SCSI_OSD_INITIATOR is not set +-# CONFIG_ATA is not set +-# CONFIG_MD is not set +-# CONFIG_TARGET_CORE is not set + CONFIG_NETDEVICES=y +-# CONFIG_DUMMY is not set +-# CONFIG_BONDING is not set +-# CONFIG_MACVLAN is not set +-# CONFIG_EQUALIZER is not set + CONFIG_TUN=m +-# CONFIG_VETH is not set +-CONFIG_MII=y + CONFIG_PHYLIB=m +- +-# +-# MII PHY device drivers +-# +-# CONFIG_MARVELL_PHY is not set +-# CONFIG_DAVICOM_PHY is not set +-# CONFIG_QSEMI_PHY is not set +-# CONFIG_LXT_PHY is not set +-# CONFIG_CICADA_PHY is not set +-# CONFIG_VITESSE_PHY is not set +-# CONFIG_SMSC_PHY is not set +-# CONFIG_BROADCOM_PHY is not set +-# CONFIG_ICPLUS_PHY is not set +-# CONFIG_REALTEK_PHY is not set +-# CONFIG_NATIONAL_PHY is not set +-# CONFIG_STE10XP is not set +-# CONFIG_LSI_ET1011C_PHY is not set +-# CONFIG_MICREL_PHY is not set + CONFIG_MDIO_BITBANG=m +-# CONFIG_MDIO_GPIO is not set + CONFIG_NET_ETHERNET=y +-CONFIG_AX88796=m +-# CONFIG_AX88796_93CX6 is not set +-# CONFIG_SMC91X is not set +-# CONFIG_DM9000 is not set +-# CONFIG_ETHOC is not set +-# CONFIG_SMC911X is not set +-# CONFIG_SMSC911X is not set +-# CONFIG_DNET is not set +-# CONFIG_IBM_NEW_EMAC_ZMII is not set +-# CONFIG_IBM_NEW_EMAC_RGMII is not set +-# CONFIG_IBM_NEW_EMAC_TAH is not set +-# CONFIG_IBM_NEW_EMAC_EMAC4 is not set +-# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +-# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +-# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set +-# CONFIG_B44 is not set +-# CONFIG_KS8851_MLL is not set +-# CONFIG_FTMAC100 is not set + # CONFIG_NETDEV_1000 is not set + # CONFIG_NETDEV_10000 is not set +-# CONFIG_WLAN is not set +- +-# +-# Enable WiMAX (Networking options) to see the WiMAX drivers +-# +- +-# +-# USB Network Adapters +-# +-# CONFIG_USB_CATC is not set +-# CONFIG_USB_KAWETH is not set +-# CONFIG_USB_PEGASUS is not set +-# CONFIG_USB_RTL8150 is not set ++CONFIG_LIBERTAS_THINFIRM=m ++CONFIG_LIBERTAS_THINFIRM_USB=m ++CONFIG_AT76C50X_USB=m ++CONFIG_USB_ZD1201=m ++CONFIG_USB_NET_RNDIS_WLAN=m ++CONFIG_RTL8187=m ++CONFIG_MAC80211_HWSIM=m ++CONFIG_ATH_COMMON=m ++CONFIG_ATH9K=m ++CONFIG_ATH9K_HTC=m ++CONFIG_CARL9170=m ++CONFIG_B43=m ++CONFIG_B43LEGACY=m ++CONFIG_HOSTAP=m ++CONFIG_IWM=m ++CONFIG_LIBERTAS=m ++CONFIG_LIBERTAS_USB=m ++CONFIG_LIBERTAS_SDIO=m ++CONFIG_P54_COMMON=m ++CONFIG_P54_USB=m ++CONFIG_RT2X00=m ++CONFIG_RT2500USB=m ++CONFIG_RT73USB=m ++CONFIG_RT2800USB=m ++CONFIG_RT2800USB_RT53XX=y ++CONFIG_RTL8192CU=m ++CONFIG_WL1251=m ++CONFIG_WL12XX_MENU=m ++CONFIG_ZD1211RW=m ++CONFIG_MWIFIEX=m ++CONFIG_MWIFIEX_SDIO=m ++CONFIG_WIMAX_I2400M_USB=m ++CONFIG_USB_CATC=m ++CONFIG_USB_KAWETH=m ++CONFIG_USB_PEGASUS=m ++CONFIG_USB_RTL8150=m + CONFIG_USB_USBNET=y + CONFIG_USB_NET_AX8817X=m +-# CONFIG_USB_NET_CDCETHER is not set +-# CONFIG_USB_NET_CDC_EEM is not set +-CONFIG_USB_NET_CDC_NCM=y +-# CONFIG_USB_NET_DM9601 is not set +-# CONFIG_USB_NET_SMSC75XX is not set ++CONFIG_USB_NET_CDCETHER=m ++CONFIG_USB_NET_CDC_EEM=m ++CONFIG_USB_NET_DM9601=m ++CONFIG_USB_NET_SMSC75XX=m + CONFIG_USB_NET_SMSC95XX=y +-# CONFIG_USB_NET_GL620A is not set +-# CONFIG_USB_NET_NET1080 is not set +-# CONFIG_USB_NET_PLUSB is not set +-# CONFIG_USB_NET_MCS7830 is not set +-# CONFIG_USB_NET_RNDIS_HOST is not set +-# CONFIG_USB_NET_CDC_SUBSET is not set ++CONFIG_USB_NET_GL620A=m ++CONFIG_USB_NET_NET1080=m ++CONFIG_USB_NET_PLUSB=m ++CONFIG_USB_NET_MCS7830=m ++CONFIG_USB_NET_CDC_SUBSET=m ++CONFIG_USB_ALI_M5632=y ++CONFIG_USB_AN2720=y ++CONFIG_USB_KC2190=y + # CONFIG_USB_NET_ZAURUS is not set +-# CONFIG_USB_NET_CX82310_ETH is not set +-# CONFIG_USB_NET_KALMIA is not set +-# CONFIG_USB_NET_INT51X1 is not set +-# CONFIG_USB_IPHETH is not set +-# CONFIG_USB_SIERRA_NET is not set +-# CONFIG_WAN is not set +- +-# +-# CAIF transport drivers +-# +-# CONFIG_PPP is not set +-# CONFIG_SLIP is not set +-# CONFIG_NETCONSOLE is not set +-# CONFIG_NETPOLL is not set +-# CONFIG_NET_POLL_CONTROLLER is not set +-# CONFIG_ISDN is not set +-# CONFIG_PHONE is not set +- +-# +-# Input device support +-# +-CONFIG_INPUT=y +-# CONFIG_INPUT_FF_MEMLESS is not set +-# CONFIG_INPUT_POLLDEV is not set +-# CONFIG_INPUT_SPARSEKMAP is not set +- +-# +-# Userland interfaces +-# +-CONFIG_INPUT_MOUSEDEV=y ++CONFIG_USB_NET_CX82310_ETH=m ++CONFIG_USB_NET_KALMIA=m ++CONFIG_USB_NET_INT51X1=m ++CONFIG_USB_IPHETH=m ++CONFIG_USB_SIERRA_NET=m ++CONFIG_USB_VL600=m ++CONFIG_PPP=m ++CONFIG_PPP_ASYNC=m ++CONFIG_PPP_SYNC_TTY=m ++CONFIG_PPP_DEFLATE=m ++CONFIG_PPP_BSDCOMP=m ++CONFIG_SLIP=m ++CONFIG_SLIP_COMPRESSED=y ++CONFIG_NETCONSOLE=m ++CONFIG_INPUT_POLLDEV=m + # CONFIG_INPUT_MOUSEDEV_PSAUX is not set +-CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +-CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +-# CONFIG_INPUT_JOYDEV is not set ++CONFIG_INPUT_JOYDEV=m + CONFIG_INPUT_EVDEV=m +-# CONFIG_INPUT_EVBUG is not set +- +-# +-# Input Device Drivers +-# + # CONFIG_INPUT_KEYBOARD is not set + # CONFIG_INPUT_MOUSE is not set +-# CONFIG_INPUT_JOYSTICK is not set +-# CONFIG_INPUT_TABLET is not set +-# CONFIG_INPUT_TOUCHSCREEN is not set + CONFIG_INPUT_MISC=y +-# CONFIG_INPUT_AD714X is not set +-# CONFIG_INPUT_ATI_REMOTE is not set +-# CONFIG_INPUT_ATI_REMOTE2 is not set +-# CONFIG_INPUT_KEYSPAN_REMOTE is not set +-# CONFIG_INPUT_POWERMATE is not set +-# CONFIG_INPUT_YEALINK is not set +-# CONFIG_INPUT_CM109 is not set ++CONFIG_INPUT_AD714X=m ++CONFIG_INPUT_ATI_REMOTE=m ++CONFIG_INPUT_ATI_REMOTE2=m ++CONFIG_INPUT_KEYSPAN_REMOTE=m ++CONFIG_INPUT_POWERMATE=m ++CONFIG_INPUT_YEALINK=m ++CONFIG_INPUT_CM109=m + CONFIG_INPUT_UINPUT=m +-# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set +-# CONFIG_INPUT_ADXL34X is not set +-# CONFIG_INPUT_CMA3000 is not set +- +-# +-# Hardware I/O ports +-# ++CONFIG_INPUT_GPIO_ROTARY_ENCODER=m ++CONFIG_INPUT_ADXL34X=m ++CONFIG_INPUT_CMA3000=m + CONFIG_SERIO=m +-CONFIG_SERIO_SERPORT=m +-# CONFIG_SERIO_AMBAKMI is not set +-# CONFIG_SERIO_LIBPS2 is not set + CONFIG_SERIO_RAW=m +-# CONFIG_SERIO_ALTERA_PS2 is not set +-# CONFIG_SERIO_PS2MULT is not set + CONFIG_GAMEPORT=m + CONFIG_GAMEPORT_NS558=m + CONFIG_GAMEPORT_L4=m +- +-# +-# Character devices +-# +-CONFIG_VT=y +-CONFIG_CONSOLE_TRANSLATIONS=y +-CONFIG_VT_CONSOLE=y +-CONFIG_HW_CONSOLE=y + CONFIG_VT_HW_CONSOLE_BINDING=y +-CONFIG_UNIX98_PTYS=y +-# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set + # CONFIG_LEGACY_PTYS is not set +-# CONFIG_SERIAL_NONSTANDARD is not set +-# CONFIG_N_GSM is not set +-# CONFIG_TRACE_SINK is not set + # CONFIG_DEVKMEM is not set +- +-# +-# Serial drivers +-# +-# CONFIG_SERIAL_8250 is not set +- +-# +-# Non-8250 serial port support +-# +-# CONFIG_SERIAL_AMBA_PL010 is not set + CONFIG_SERIAL_AMBA_PL011=y + CONFIG_SERIAL_AMBA_PL011_CONSOLE=y +-CONFIG_SERIAL_CORE=y +-CONFIG_SERIAL_CORE_CONSOLE=y +-# CONFIG_SERIAL_TIMBERDALE is not set +-# CONFIG_SERIAL_ALTERA_JTAGUART is not set +-# CONFIG_SERIAL_ALTERA_UART is not set +-# CONFIG_SERIAL_XILINX_PS_UART is not set +-# CONFIG_TTY_PRINTK is not set +-# CONFIG_HVC_DCC is not set +-# CONFIG_IPMI_HANDLER is not set + # CONFIG_HW_RANDOM is not set +-# CONFIG_R3964 is not set + CONFIG_RAW_DRIVER=y +-CONFIG_MAX_RAW_DEVS=256 +-# CONFIG_TCG_TPM is not set +-# CONFIG_RAMOOPS is not set +-# CONFIG_I2C is not set +-# CONFIG_SPI is not set +- +-# +-# PPS support +-# +-# CONFIG_PPS is not set +- +-# +-# PPS generators support +-# +- +-# +-# PTP clock support +-# +- +-# +-# Enable Device Drivers -> PPS to see the PTP clock options. +-# +-CONFIG_ARCH_REQUIRE_GPIOLIB=y +-CONFIG_GPIOLIB=y +-# CONFIG_DEBUG_GPIO is not set + CONFIG_GPIO_SYSFS=y +- +-# +-# Memory mapped GPIO drivers: +-# +-# CONFIG_GPIO_GENERIC_PLATFORM is not set +-# CONFIG_GPIO_IT8761E is not set +-# CONFIG_GPIO_PL061 is not set +- +-# +-# I2C GPIO expanders: +-# +- +-# +-# PCI GPIO expanders: +-# +- +-# +-# SPI GPIO expanders: +-# +- +-# +-# AC97 GPIO expanders: +-# +- +-# +-# MODULbus GPIO expanders: +-# +-# CONFIG_W1 is not set +-# CONFIG_POWER_SUPPLY is not set + # CONFIG_HWMON is not set +-# CONFIG_THERMAL is not set +-# CONFIG_WATCHDOG is not set +-CONFIG_SSB_POSSIBLE=y +- +-# +-# Sonics Silicon Backplane +-# +-# CONFIG_SSB is not set +-CONFIG_BCMA_POSSIBLE=y +- +-# +-# Broadcom specific AMBA +-# +-# CONFIG_BCMA is not set ++CONFIG_WATCHDOG=y ++CONFIG_BCM2708_WDT=m + # CONFIG_MFD_SUPPORT is not set +-# CONFIG_REGULATOR is not set +-# CONFIG_MEDIA_SUPPORT is not set +- +-# +-# Graphics support +-# +-# CONFIG_DRM is not set +-# CONFIG_VGASTATE is not set +-# CONFIG_VIDEO_OUTPUT_CONTROL is not set + CONFIG_FB=y +-# CONFIG_FIRMWARE_EDID is not set +-# CONFIG_FB_DDC is not set +-# CONFIG_FB_BOOT_VESA_SUPPORT is not set +-CONFIG_FB_CFB_FILLRECT=y +-CONFIG_FB_CFB_COPYAREA=y +-CONFIG_FB_CFB_IMAGEBLIT=y +-# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set +-# CONFIG_FB_SYS_FILLRECT is not set +-# CONFIG_FB_SYS_COPYAREA is not set +-# CONFIG_FB_SYS_IMAGEBLIT is not set +-# CONFIG_FB_FOREIGN_ENDIAN is not set +-# CONFIG_FB_SYS_FOPS is not set +-# CONFIG_FB_WMT_GE_ROPS is not set +-# CONFIG_FB_SVGALIB is not set +-# CONFIG_FB_MACMODES is not set +-# CONFIG_FB_BACKLIGHT is not set +-# CONFIG_FB_MODE_HELPERS is not set +-# CONFIG_FB_TILEBLITTING is not set +- +-# +-# Frame buffer hardware drivers +-# + CONFIG_FB_BCM2708=y +-# CONFIG_FB_ARMCLCD is not set +-# CONFIG_FB_S1D13XXX is not set +-# CONFIG_FB_UDL is not set +-# CONFIG_FB_VIRTUAL is not set +-# CONFIG_FB_METRONOME is not set +-# CONFIG_FB_BROADSHEET is not set +-# CONFIG_BACKLIGHT_LCD_SUPPORT is not set +- +-# +-# Display device support +-# +-# CONFIG_DISPLAY_SUPPORT is not set +- +-# +-# Console display driver support +-# +-CONFIG_DUMMY_CONSOLE=y + CONFIG_FRAMEBUFFER_CONSOLE=y +-# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set +-# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set +-# CONFIG_FONTS is not set +-CONFIG_FONT_8x8=y +-CONFIG_FONT_8x16=y + CONFIG_LOGO=y + # CONFIG_LOGO_LINUX_MONO is not set + # CONFIG_LOGO_LINUX_VGA16 is not set +-CONFIG_LOGO_LINUX_CLUT224=y +-# CONFIG_SOUND is not set +-CONFIG_HID_SUPPORT=y +-CONFIG_HID=y +-# CONFIG_HIDRAW is not set +- +-# +-# USB Input Devices +-# +-CONFIG_USB_HID=y + CONFIG_HID_PID=y + CONFIG_USB_HIDDEV=y +- +-# +-# Special HID drivers +-# + CONFIG_HID_A4TECH=m +-# CONFIG_HID_ACRUX is not set ++CONFIG_HID_ACRUX=m + CONFIG_HID_APPLE=m + CONFIG_HID_BELKIN=m + CONFIG_HID_CHERRY=m + CONFIG_HID_CHICONY=m + CONFIG_HID_CYPRESS=m + CONFIG_HID_DRAGONRISE=m +-# CONFIG_DRAGONRISE_FF is not set +-# CONFIG_HID_EMS_FF is not set ++CONFIG_HID_EMS_FF=m ++CONFIG_HID_ELECOM=m + CONFIG_HID_EZKEY=m +-# CONFIG_HID_HOLTEK is not set +-# CONFIG_HID_KEYTOUCH is not set ++CONFIG_HID_HOLTEK=m ++CONFIG_HID_KEYTOUCH=m + CONFIG_HID_KYE=m +-# CONFIG_HID_UCLOGIC is not set +-# CONFIG_HID_WALTOP is not set ++CONFIG_HID_UCLOGIC=m ++CONFIG_HID_WALTOP=m + CONFIG_HID_GYRATION=m + CONFIG_HID_TWINHAN=m + CONFIG_HID_KENSINGTON=m +-# CONFIG_HID_LCPOWER is not set ++CONFIG_HID_LCPOWER=m + CONFIG_HID_LOGITECH=m +-# CONFIG_LOGITECH_FF is not set +-# CONFIG_LOGIRUMBLEPAD2_FF is not set +-# CONFIG_LOGIG940_FF is not set +-# CONFIG_LOGIWII_FF is not set ++CONFIG_HID_MAGICMOUSE=m + CONFIG_HID_MICROSOFT=m + CONFIG_HID_MONTEREY=m +-# CONFIG_HID_MULTITOUCH is not set +-# CONFIG_HID_NTRIG is not set ++CONFIG_HID_MULTITOUCH=m ++CONFIG_HID_NTRIG=m + CONFIG_HID_ORTEK=m + CONFIG_HID_PANTHERLORD=m +-# CONFIG_PANTHERLORD_FF is not set + CONFIG_HID_PETALYNX=m +-# CONFIG_HID_PICOLCD is not set +-# CONFIG_HID_QUANTA is not set +-# CONFIG_HID_ROCCAT is not set ++CONFIG_HID_PICOLCD=m ++CONFIG_HID_QUANTA=m ++CONFIG_HID_ROCCAT=m + CONFIG_HID_SAMSUNG=m + CONFIG_HID_SONY=m +-# CONFIG_HID_SPEEDLINK is not set ++CONFIG_HID_SPEEDLINK=m + CONFIG_HID_SUNPLUS=m + CONFIG_HID_GREENASIA=m +-# CONFIG_GREENASIA_FF is not set + CONFIG_HID_SMARTJOYPLUS=m +-# CONFIG_SMARTJOYPLUS_FF is not set + CONFIG_HID_TOPSEED=m + CONFIG_HID_THRUSTMASTER=m +-# CONFIG_THRUSTMASTER_FF is not set ++CONFIG_HID_WACOM=m ++CONFIG_HID_WIIMOTE=m + CONFIG_HID_ZEROPLUS=m +-# CONFIG_ZEROPLUS_FF is not set +-# CONFIG_HID_ZYDACRON is not set +-CONFIG_USB_SUPPORT=y +-CONFIG_USB_ARCH_HAS_HCD=y +-# CONFIG_USB_ARCH_HAS_OHCI is not set +-# CONFIG_USB_ARCH_HAS_EHCI is not set ++CONFIG_HID_ZYDACRON=m + CONFIG_USB=y +-# CONFIG_USB_DEBUG is not set + CONFIG_USB_ANNOUNCE_NEW_DEVICES=y +- +-# +-# Miscellaneous USB options +-# +-# CONFIG_USB_DEVICEFS is not set +-CONFIG_USB_DEVICE_CLASS=y +-# CONFIG_USB_DYNAMIC_MINORS is not set +-# CONFIG_USB_OTG_WHITELIST is not set +-# CONFIG_USB_OTG_BLACKLIST_HUB is not set + CONFIG_USB_MON=m +-# CONFIG_USB_WUSB is not set +-# CONFIG_USB_WUSB_CBAF is not set +- +-# +-# USB Host Controller Drivers +-# +-# CONFIG_USB_C67X00_HCD is not set +-# CONFIG_USB_OXU210HP_HCD is not set +-# CONFIG_USB_ISP116X_HCD is not set +-# CONFIG_USB_ISP1760_HCD is not set +-# CONFIG_USB_ISP1362_HCD is not set +-# CONFIG_USB_SL811_HCD is not set +-# CONFIG_USB_R8A66597_HCD is not set +-# CONFIG_USB_HWA_HCD is not set + CONFIG_USB_DWCOTG=y +- +-# +-# USB Device Class drivers +-# +-# CONFIG_USB_ACM is not set +-# CONFIG_USB_PRINTER is not set +-# CONFIG_USB_WDM is not set +-# CONFIG_USB_TMC is not set +- +-# +-# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may +-# +- +-# +-# also be needed; see USB_STORAGE Help for more info +-# + CONFIG_USB_STORAGE=y +-# CONFIG_USB_STORAGE_DEBUG is not set +-# CONFIG_USB_STORAGE_REALTEK is not set +-# CONFIG_USB_STORAGE_DATAFAB is not set +-# CONFIG_USB_STORAGE_FREECOM is not set +-# CONFIG_USB_STORAGE_ISD200 is not set +-# CONFIG_USB_STORAGE_USBAT is not set +-# CONFIG_USB_STORAGE_SDDR09 is not set +-# CONFIG_USB_STORAGE_SDDR55 is not set +-# CONFIG_USB_STORAGE_JUMPSHOT is not set +-# CONFIG_USB_STORAGE_ALAUDA is not set +-# CONFIG_USB_STORAGE_ONETOUCH is not set +-# CONFIG_USB_STORAGE_KARMA is not set +-# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set +-# CONFIG_USB_STORAGE_ENE_UB6250 is not set +-# CONFIG_USB_UAS is not set ++CONFIG_USB_STORAGE_REALTEK=m ++CONFIG_USB_STORAGE_DATAFAB=m ++CONFIG_USB_STORAGE_FREECOM=m ++CONFIG_USB_STORAGE_ISD200=m ++CONFIG_USB_STORAGE_USBAT=m ++CONFIG_USB_STORAGE_SDDR09=m ++CONFIG_USB_STORAGE_SDDR55=m ++CONFIG_USB_STORAGE_JUMPSHOT=m ++CONFIG_USB_STORAGE_ALAUDA=m ++CONFIG_USB_STORAGE_ONETOUCH=m ++CONFIG_USB_STORAGE_KARMA=m ++CONFIG_USB_STORAGE_CYPRESS_ATACB=m ++CONFIG_USB_STORAGE_ENE_UB6250=m ++CONFIG_USB_UAS=m + CONFIG_USB_LIBUSUAL=y +- +-# +-# USB Imaging devices +-# +-# CONFIG_USB_MDC800 is not set +-# CONFIG_USB_MICROTEK is not set +- +-# +-# USB port drivers +-# +-# CONFIG_USB_SERIAL is not set +- +-# +-# USB Miscellaneous drivers +-# +-# CONFIG_USB_EMI62 is not set +-# CONFIG_USB_EMI26 is not set +-# CONFIG_USB_ADUTUX is not set +-# CONFIG_USB_SEVSEG is not set +-# CONFIG_USB_RIO500 is not set +-# CONFIG_USB_LEGOTOWER is not set +-# CONFIG_USB_LCD is not set +-# CONFIG_USB_LED is not set +-# CONFIG_USB_CYPRESS_CY7C63 is not set +-# CONFIG_USB_CYTHERM is not set +-# CONFIG_USB_IDMOUSE is not set +-# CONFIG_USB_FTDI_ELAN is not set +-# CONFIG_USB_APPLEDISPLAY is not set +-# CONFIG_USB_LD is not set +-# CONFIG_USB_TRANCEVIBRATOR is not set +-# CONFIG_USB_IOWARRIOR is not set +-# CONFIG_USB_TEST is not set +-# CONFIG_USB_ISIGHTFW is not set +-# CONFIG_USB_YUREX is not set +-# CONFIG_USB_GADGET is not set +- +-# +-# OTG and related infrastructure +-# +-# CONFIG_USB_GPIO_VBUS is not set +-# CONFIG_USB_ULPI is not set +-# CONFIG_NOP_USB_XCEIV is not set ++CONFIG_USB_MDC800=m ++CONFIG_USB_MICROTEK=m ++CONFIG_USB_SERIAL=m ++CONFIG_USB_SERIAL_GENERIC=y ++CONFIG_USB_SERIAL_AIRCABLE=m ++CONFIG_USB_SERIAL_ARK3116=m ++CONFIG_USB_SERIAL_BELKIN=m ++CONFIG_USB_SERIAL_CH341=m ++CONFIG_USB_SERIAL_WHITEHEAT=m ++CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m ++CONFIG_USB_SERIAL_CP210X=m ++CONFIG_USB_SERIAL_CYPRESS_M8=m ++CONFIG_USB_SERIAL_EMPEG=m ++CONFIG_USB_SERIAL_FTDI_SIO=m ++CONFIG_USB_SERIAL_FUNSOFT=m ++CONFIG_USB_SERIAL_VISOR=m ++CONFIG_USB_SERIAL_IPAQ=m ++CONFIG_USB_SERIAL_IR=m ++CONFIG_USB_SERIAL_EDGEPORT=m ++CONFIG_USB_SERIAL_EDGEPORT_TI=m ++CONFIG_USB_SERIAL_GARMIN=m ++CONFIG_USB_SERIAL_IPW=m ++CONFIG_USB_SERIAL_IUU=m ++CONFIG_USB_SERIAL_KEYSPAN_PDA=m ++CONFIG_USB_SERIAL_KEYSPAN=m ++CONFIG_USB_SERIAL_KLSI=m ++CONFIG_USB_SERIAL_KOBIL_SCT=m ++CONFIG_USB_SERIAL_MCT_U232=m ++CONFIG_USB_SERIAL_MOS7720=m ++CONFIG_USB_SERIAL_MOS7840=m ++CONFIG_USB_SERIAL_MOTOROLA=m ++CONFIG_USB_SERIAL_NAVMAN=m ++CONFIG_USB_SERIAL_PL2303=m ++CONFIG_USB_SERIAL_OTI6858=m ++CONFIG_USB_SERIAL_QCAUX=m ++CONFIG_USB_SERIAL_QUALCOMM=m ++CONFIG_USB_SERIAL_SPCP8X5=m ++CONFIG_USB_SERIAL_HP4X=m ++CONFIG_USB_SERIAL_SAFE=m ++CONFIG_USB_SERIAL_SIEMENS_MPI=m ++CONFIG_USB_SERIAL_SIERRAWIRELESS=m ++CONFIG_USB_SERIAL_SYMBOL=m ++CONFIG_USB_SERIAL_TI=m ++CONFIG_USB_SERIAL_CYBERJACK=m ++CONFIG_USB_SERIAL_XIRCOM=m ++CONFIG_USB_SERIAL_OPTION=m ++CONFIG_USB_SERIAL_OMNINET=m ++CONFIG_USB_SERIAL_OPTICON=m ++CONFIG_USB_SERIAL_VIVOPAY_SERIAL=m ++CONFIG_USB_SERIAL_ZIO=m ++CONFIG_USB_SERIAL_SSU100=m ++CONFIG_USB_SERIAL_DEBUG=m ++CONFIG_USB_EMI62=m ++CONFIG_USB_EMI26=m ++CONFIG_USB_ADUTUX=m ++CONFIG_USB_SEVSEG=m ++CONFIG_USB_RIO500=m ++CONFIG_USB_LEGOTOWER=m ++CONFIG_USB_LCD=m ++CONFIG_USB_LED=m ++CONFIG_USB_CYPRESS_CY7C63=m ++CONFIG_USB_CYTHERM=m ++CONFIG_USB_IDMOUSE=m ++CONFIG_USB_FTDI_ELAN=m ++CONFIG_USB_APPLEDISPLAY=m ++CONFIG_USB_LD=m ++CONFIG_USB_TRANCEVIBRATOR=m ++CONFIG_USB_IOWARRIOR=m ++CONFIG_USB_TEST=m ++CONFIG_USB_ISIGHTFW=m ++CONFIG_USB_YUREX=m + CONFIG_MMC=y +-# CONFIG_MMC_DEBUG is not set +-# CONFIG_MMC_UNSAFE_RESUME is not set +-# CONFIG_MMC_CLKGATE is not set +- +-# +-# MMC/SD/SDIO Card Drivers +-# +-CONFIG_MMC_BLOCK=y +-CONFIG_MMC_BLOCK_MINORS=8 +-CONFIG_MMC_BLOCK_BOUNCE=y +-# CONFIG_SDIO_UART is not set +-# CONFIG_MMC_TEST is not set +- +-# +-# MMC/SD/SDIO Host Controller Drivers +-# +-# CONFIG_MMC_ARMMMCI is not set + CONFIG_MMC_SDHCI=y +-CONFIG_MMC_SDHCI_IO_ACCESSORS=y + CONFIG_MMC_SDHCI_PLTFM=y +-# CONFIG_MMC_SDHCI_PXAV3 is not set +-# CONFIG_MMC_SDHCI_PXAV2 is not set + CONFIG_MMC_SDHCI_BCM2708=y + CONFIG_MMC_SDHCI_BCM2708_DMA=y +-# CONFIG_MMC_BCM2708 is not set +-# CONFIG_MMC_DW is not set +-# CONFIG_MMC_VUB300 is not set +-# CONFIG_MMC_USHC is not set +-# CONFIG_MEMSTICK is not set +-CONFIG_NEW_LEDS=y +-CONFIG_LEDS_CLASS=y +- +-# +-# LED drivers +-# + CONFIG_LEDS_GPIO=y +-# CONFIG_LEDS_LT3593 is not set +-CONFIG_LEDS_TRIGGERS=y +- +-# +-# LED Triggers +-# + CONFIG_LEDS_TRIGGER_TIMER=m + CONFIG_LEDS_TRIGGER_HEARTBEAT=m +-# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set +-# CONFIG_LEDS_TRIGGER_GPIO is not set + CONFIG_LEDS_TRIGGER_DEFAULT_ON=m +- +-# +-# iptables trigger is under Netfilter config (LED target) +-# +-# CONFIG_ACCESSIBILITY is not set +-CONFIG_RTC_LIB=y +-# CONFIG_RTC_CLASS is not set +-# CONFIG_DMADEVICES is not set +-# CONFIG_AUXDISPLAY is not set +-# CONFIG_UIO is not set +- +-# +-# Virtio drivers +-# +-# CONFIG_VIRTIO_BALLOON is not set +-# CONFIG_STAGING is not set +-CONFIG_CLKDEV_LOOKUP=y ++CONFIG_UIO=m ++CONFIG_UIO_PDRV=m ++CONFIG_UIO_PDRV_GENIRQ=m + # CONFIG_IOMMU_SUPPORT is not set +-# CONFIG_VIRT_DRIVERS is not set +- +-# +-# File systems +-# +-CONFIG_EXT2_FS=m +-CONFIG_EXT2_FS_XATTR=y +-CONFIG_EXT2_FS_POSIX_ACL=y +-CONFIG_EXT2_FS_SECURITY=y +-CONFIG_EXT2_FS_XIP=y +-CONFIG_EXT3_FS=y +-# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set +-CONFIG_EXT3_FS_XATTR=y +-CONFIG_EXT3_FS_POSIX_ACL=y +-CONFIG_EXT3_FS_SECURITY=y +-CONFIG_EXT4_FS=m +-CONFIG_EXT4_FS_XATTR=y ++CONFIG_EXT4_FS=y + CONFIG_EXT4_FS_POSIX_ACL=y + CONFIG_EXT4_FS_SECURITY=y +-# CONFIG_EXT4_DEBUG is not set +-CONFIG_FS_XIP=y +-CONFIG_JBD=y +-CONFIG_JBD2=m +-CONFIG_FS_MBCACHE=y +-# CONFIG_REISERFS_FS is not set +-# CONFIG_JFS_FS is not set +-# CONFIG_XFS_FS is not set +-# CONFIG_GFS2_FS is not set +-# CONFIG_OCFS2_FS is not set +-# CONFIG_BTRFS_FS is not set +-# CONFIG_NILFS2_FS is not set +-CONFIG_FS_POSIX_ACL=y +-CONFIG_FILE_LOCKING=y +-CONFIG_FSNOTIFY=y +-CONFIG_DNOTIFY=y +-CONFIG_INOTIFY_USER=y +-# CONFIG_FANOTIFY is not set +-# CONFIG_QUOTA is not set +-# CONFIG_QUOTACTL is not set ++CONFIG_REISERFS_FS=m ++CONFIG_REISERFS_FS_XATTR=y ++CONFIG_REISERFS_FS_POSIX_ACL=y ++CONFIG_REISERFS_FS_SECURITY=y ++CONFIG_JFS_FS=m ++CONFIG_JFS_POSIX_ACL=y ++CONFIG_JFS_SECURITY=y ++CONFIG_XFS_FS=m ++CONFIG_XFS_QUOTA=y ++CONFIG_XFS_POSIX_ACL=y ++CONFIG_XFS_RT=y ++CONFIG_GFS2_FS=m ++CONFIG_OCFS2_FS=m ++CONFIG_BTRFS_FS=m ++CONFIG_BTRFS_FS_POSIX_ACL=y ++CONFIG_NILFS2_FS=m + CONFIG_AUTOFS4_FS=y + CONFIG_FUSE_FS=m + CONFIG_CUSE=m +- +-# +-# Caches +-# + CONFIG_FSCACHE=y +-# CONFIG_FSCACHE_STATS is not set +-# CONFIG_FSCACHE_HISTOGRAM is not set +-# CONFIG_FSCACHE_DEBUG is not set +-# CONFIG_FSCACHE_OBJECT_LIST is not set + CONFIG_CACHEFILES=y +-# CONFIG_CACHEFILES_DEBUG is not set +-# CONFIG_CACHEFILES_HISTOGRAM is not set +- +-# +-# CD-ROM/DVD Filesystems +-# + CONFIG_ISO9660_FS=m + CONFIG_JOLIET=y + CONFIG_ZISOFS=y + CONFIG_UDF_FS=m +-CONFIG_UDF_NLS=y +- +-# +-# DOS/FAT/NT Filesystems +-# +-CONFIG_FAT_FS=y + CONFIG_MSDOS_FS=y + CONFIG_VFAT_FS=y +-CONFIG_FAT_DEFAULT_CODEPAGE=437 + CONFIG_FAT_DEFAULT_IOCHARSET="ascii" + CONFIG_NTFS_FS=m +-# CONFIG_NTFS_DEBUG is not set +-# CONFIG_NTFS_RW is not set +- +-# +-# Pseudo filesystems +-# +-CONFIG_PROC_FS=y +-CONFIG_PROC_SYSCTL=y +-CONFIG_PROC_PAGE_MONITOR=y +-CONFIG_SYSFS=y + CONFIG_TMPFS=y +-# CONFIG_TMPFS_POSIX_ACL is not set +-# CONFIG_TMPFS_XATTR is not set +-# CONFIG_HUGETLB_PAGE is not set ++CONFIG_TMPFS_POSIX_ACL=y + CONFIG_CONFIGFS_FS=y +-CONFIG_MISC_FILESYSTEMS=y +-# CONFIG_ADFS_FS is not set +-# CONFIG_AFFS_FS is not set +-# CONFIG_ECRYPT_FS is not set +-# CONFIG_HFS_FS is not set +-# CONFIG_HFSPLUS_FS is not set +-# CONFIG_BEFS_FS is not set +-# CONFIG_BFS_FS is not set +-# CONFIG_EFS_FS is not set +-# CONFIG_LOGFS is not set +-# CONFIG_CRAMFS is not set +-# CONFIG_SQUASHFS is not set +-# CONFIG_VXFS_FS is not set +-# CONFIG_MINIX_FS is not set +-# CONFIG_OMFS_FS is not set +-# CONFIG_HPFS_FS is not set +-# CONFIG_QNX4FS_FS is not set +-# CONFIG_ROMFS_FS is not set +-# CONFIG_PSTORE is not set +-# CONFIG_SYSV_FS is not set +-# CONFIG_UFS_FS is not set +-CONFIG_NETWORK_FILESYSTEMS=y ++CONFIG_SQUASHFS=m ++CONFIG_SQUASHFS_XATTR=y ++CONFIG_SQUASHFS_LZO=y ++CONFIG_SQUASHFS_XZ=y + CONFIG_NFS_FS=y + CONFIG_NFS_V3=y + CONFIG_NFS_V3_ACL=y + CONFIG_NFS_V4=y +-# CONFIG_NFS_V4_1 is not set + CONFIG_ROOT_NFS=y + CONFIG_NFS_FSCACHE=y +-# CONFIG_NFS_USE_LEGACY_DNS is not set +-CONFIG_NFS_USE_KERNEL_DNS=y +-# CONFIG_NFS_USE_NEW_IDMAPPER is not set +-# CONFIG_NFSD is not set +-CONFIG_LOCKD=y +-CONFIG_LOCKD_V4=y +-CONFIG_NFS_ACL_SUPPORT=y +-CONFIG_NFS_COMMON=y +-CONFIG_SUNRPC=y +-CONFIG_SUNRPC_GSS=y +-# CONFIG_CEPH_FS is not set + CONFIG_CIFS=m +-# CONFIG_CIFS_STATS is not set + CONFIG_CIFS_WEAK_PW_HASH=y +-# CONFIG_CIFS_UPCALL is not set + CONFIG_CIFS_XATTR=y + CONFIG_CIFS_POSIX=y +-# CONFIG_CIFS_DEBUG2 is not set +-# CONFIG_CIFS_DFS_UPCALL is not set +-# CONFIG_CIFS_FSCACHE is not set +-# CONFIG_CIFS_ACL is not set +-# CONFIG_NCP_FS is not set +-# CONFIG_CODA_FS is not set +-# CONFIG_AFS_FS is not set +- +-# +-# Partition Types +-# ++CONFIG_9P_FS=m + CONFIG_PARTITION_ADVANCED=y +-# CONFIG_ACORN_PARTITION is not set +-# CONFIG_OSF_PARTITION is not set +-# CONFIG_AMIGA_PARTITION is not set +-# CONFIG_ATARI_PARTITION is not set + CONFIG_MAC_PARTITION=y +-CONFIG_MSDOS_PARTITION=y +-# CONFIG_BSD_DISKLABEL is not set +-# CONFIG_MINIX_SUBPARTITION is not set +-# CONFIG_SOLARIS_X86_PARTITION is not set +-# CONFIG_UNIXWARE_DISKLABEL is not set +-# CONFIG_LDM_PARTITION is not set +-# CONFIG_SGI_PARTITION is not set +-# CONFIG_ULTRIX_PARTITION is not set +-# CONFIG_SUN_PARTITION is not set +-# CONFIG_KARMA_PARTITION is not set + CONFIG_EFI_PARTITION=y +-# CONFIG_SYSV68_PARTITION is not set +-CONFIG_NLS=y + CONFIG_NLS_DEFAULT="utf8" + CONFIG_NLS_CODEPAGE_437=y + CONFIG_NLS_CODEPAGE_737=m +@@ -1341,218 +449,25 @@ + CONFIG_NLS_KOI8_R=m + CONFIG_NLS_KOI8_U=m + CONFIG_NLS_UTF8=m +-# CONFIG_DLM is not set +- +-# +-# Kernel hacking +-# +-# CONFIG_PRINTK_TIME is not set +-CONFIG_DEFAULT_MESSAGE_LOGLEVEL=4 +-CONFIG_ENABLE_WARN_DEPRECATED=y +-CONFIG_ENABLE_MUST_CHECK=y +-CONFIG_FRAME_WARN=1024 +-# CONFIG_MAGIC_SYSRQ is not set +-# CONFIG_STRIP_ASM_SYMS is not set +-# CONFIG_UNUSED_SYMBOLS is not set +-# CONFIG_DEBUG_FS is not set +-# CONFIG_HEADERS_CHECK is not set +-# CONFIG_DEBUG_SECTION_MISMATCH is not set +-CONFIG_DEBUG_KERNEL=y +-# CONFIG_DEBUG_SHIRQ is not set +-# CONFIG_LOCKUP_DETECTOR is not set +-# CONFIG_HARDLOCKUP_DETECTOR is not set +-# CONFIG_DETECT_HUNG_TASK is not set + # CONFIG_SCHED_DEBUG is not set +-# CONFIG_SCHEDSTATS is not set +-# CONFIG_TIMER_STATS is not set +-# CONFIG_DEBUG_OBJECTS is not set +-# CONFIG_DEBUG_SLAB is not set +-# CONFIG_DEBUG_KMEMLEAK is not set +-# CONFIG_DEBUG_RT_MUTEXES is not set +-# CONFIG_RT_MUTEX_TESTER is not set +-# CONFIG_DEBUG_SPINLOCK is not set +-# CONFIG_DEBUG_MUTEXES is not set +-# CONFIG_DEBUG_LOCK_ALLOC is not set +-# CONFIG_PROVE_LOCKING is not set +-# CONFIG_SPARSE_RCU_POINTER is not set +-# CONFIG_LOCK_STAT is not set +-# CONFIG_DEBUG_ATOMIC_SLEEP is not set +-# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +-# CONFIG_DEBUG_STACK_USAGE is not set +-# CONFIG_DEBUG_KOBJECT is not set + # CONFIG_DEBUG_BUGVERBOSE is not set +-# CONFIG_DEBUG_INFO is not set +-# CONFIG_DEBUG_VM is not set +-# CONFIG_DEBUG_WRITECOUNT is not set +-# CONFIG_DEBUG_MEMORY_INIT is not set +-# CONFIG_DEBUG_LIST is not set +-# CONFIG_TEST_LIST_SORT is not set +-# CONFIG_DEBUG_SG is not set +-# CONFIG_DEBUG_NOTIFIERS is not set +-# CONFIG_DEBUG_CREDENTIALS is not set +-CONFIG_FRAME_POINTER=y +-# CONFIG_BOOT_PRINTK_DELAY is not set +-# CONFIG_RCU_TORTURE_TEST is not set +-# CONFIG_BACKTRACE_SELF_TEST is not set +-# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set +-# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set +-# CONFIG_FAULT_INJECTION is not set +-# CONFIG_LATENCYTOP is not set +-# CONFIG_SYSCTL_SYSCALL_CHECK is not set +-# CONFIG_DEBUG_PAGEALLOC is not set +-CONFIG_HAVE_FUNCTION_TRACER=y +-CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +-CONFIG_HAVE_DYNAMIC_FTRACE=y +-CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +-CONFIG_HAVE_C_RECORDMCOUNT=y +-CONFIG_TRACING_SUPPORT=y + # CONFIG_FTRACE is not set +-# CONFIG_DMA_API_DEBUG is not set +-# CONFIG_ATOMIC64_SELFTEST is not set +-# CONFIG_SAMPLES is not set +-CONFIG_HAVE_ARCH_KGDB=y +-# CONFIG_KGDB is not set +-# CONFIG_TEST_KSTRTOX is not set +-# CONFIG_STRICT_DEVMEM is not set + # CONFIG_ARM_UNWIND is not set +-# CONFIG_DEBUG_USER is not set +-# CONFIG_DEBUG_LL is not set +-# CONFIG_OC_ETM is not set +- +-# +-# Security options +-# +-CONFIG_KEYS=y +-# CONFIG_KEYS_DEBUG_PROC_KEYS is not set +-# CONFIG_SECURITY_DMESG_RESTRICT is not set +-# CONFIG_SECURITY is not set +-# CONFIG_SECURITYFS is not set +-CONFIG_DEFAULT_SECURITY_DAC=y +-CONFIG_DEFAULT_SECURITY="" +-CONFIG_CRYPTO=y +- +-# +-# Crypto core or helper +-# +-CONFIG_CRYPTO_ALGAPI=y +-CONFIG_CRYPTO_ALGAPI2=y +-CONFIG_CRYPTO_AEAD=m +-CONFIG_CRYPTO_AEAD2=y +-CONFIG_CRYPTO_BLKCIPHER=y +-CONFIG_CRYPTO_BLKCIPHER2=y +-CONFIG_CRYPTO_HASH=y +-CONFIG_CRYPTO_HASH2=y +-CONFIG_CRYPTO_RNG=m +-CONFIG_CRYPTO_RNG2=y +-CONFIG_CRYPTO_PCOMP2=y +-CONFIG_CRYPTO_MANAGER=y +-CONFIG_CRYPTO_MANAGER2=y +-CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y +-# CONFIG_CRYPTO_GF128MUL is not set +-# CONFIG_CRYPTO_NULL is not set +-CONFIG_CRYPTO_WORKQUEUE=y +-# CONFIG_CRYPTO_CRYPTD is not set + CONFIG_CRYPTO_AUTHENC=m +-# CONFIG_CRYPTO_TEST is not set +- +-# +-# Authenticated Encryption with Associated Data +-# +-# CONFIG_CRYPTO_CCM is not set +-# CONFIG_CRYPTO_GCM is not set + CONFIG_CRYPTO_SEQIV=m +- +-# +-# Block modes +-# + CONFIG_CRYPTO_CBC=y +-# CONFIG_CRYPTO_CTR is not set +-# CONFIG_CRYPTO_CTS is not set +-CONFIG_CRYPTO_ECB=m +-# CONFIG_CRYPTO_LRW is not set +-# CONFIG_CRYPTO_PCBC is not set +-# CONFIG_CRYPTO_XTS is not set +- +-# +-# Hash modes +-# + CONFIG_CRYPTO_HMAC=y + CONFIG_CRYPTO_XCBC=m +-# CONFIG_CRYPTO_VMAC is not set +- +-# +-# Digest +-# +-CONFIG_CRYPTO_CRC32C=y +-# CONFIG_CRYPTO_GHASH is not set +-CONFIG_CRYPTO_MD4=m + CONFIG_CRYPTO_MD5=y +-CONFIG_CRYPTO_MICHAEL_MIC=m +-# CONFIG_CRYPTO_RMD128 is not set +-# CONFIG_CRYPTO_RMD160 is not set +-# CONFIG_CRYPTO_RMD256 is not set +-# CONFIG_CRYPTO_RMD320 is not set + CONFIG_CRYPTO_SHA1=y + CONFIG_CRYPTO_SHA256=m + CONFIG_CRYPTO_SHA512=m + CONFIG_CRYPTO_TGR192=m + CONFIG_CRYPTO_WP512=m +- +-# +-# Ciphers +-# +-# CONFIG_CRYPTO_AES is not set +-# CONFIG_CRYPTO_ANUBIS is not set +-CONFIG_CRYPTO_ARC4=m +-# CONFIG_CRYPTO_BLOWFISH is not set +-# CONFIG_CRYPTO_CAMELLIA is not set + CONFIG_CRYPTO_CAST5=m +-# CONFIG_CRYPTO_CAST6 is not set + CONFIG_CRYPTO_DES=y +-# CONFIG_CRYPTO_FCRYPT is not set +-# CONFIG_CRYPTO_KHAZAD is not set +-# CONFIG_CRYPTO_SALSA20 is not set +-# CONFIG_CRYPTO_SEED is not set +-# CONFIG_CRYPTO_SERPENT is not set +-# CONFIG_CRYPTO_TEA is not set +-# CONFIG_CRYPTO_TWOFISH is not set +- +-# +-# Compression +-# + CONFIG_CRYPTO_DEFLATE=m +-# CONFIG_CRYPTO_ZLIB is not set +-# CONFIG_CRYPTO_LZO is not set +- +-# +-# Random Number Generation +-# + # CONFIG_CRYPTO_ANSI_CPRNG is not set +-# CONFIG_CRYPTO_USER_API_HASH is not set +-# CONFIG_CRYPTO_USER_API_SKCIPHER is not set + # CONFIG_CRYPTO_HW is not set +-# CONFIG_BINARY_PRINTF is not set +- +-# +-# Library routines +-# +-CONFIG_BITREVERSE=y +-CONFIG_CRC_CCITT=m +-CONFIG_CRC16=y +-# CONFIG_CRC_T10DIF is not set + CONFIG_CRC_ITU_T=y +-CONFIG_CRC32=y +-# CONFIG_CRC7 is not set + CONFIG_LIBCRC32C=y +-# CONFIG_CRC8 is not set +-CONFIG_ZLIB_INFLATE=m +-CONFIG_ZLIB_DEFLATE=m +-# CONFIG_XZ_DEC is not set +-# CONFIG_XZ_DEC_BCJ is not set +-CONFIG_HAS_IOMEM=y +-CONFIG_HAS_IOPORT=y +-CONFIG_HAS_DMA=y +-CONFIG_NLATTR=y +-CONFIG_GENERIC_ATOMIC64=y +-# CONFIG_AVERAGE is not set +-# CONFIG_CORDIC is not set diff -Nru linux-3.2.46/debian/patches/rpi/rpi_109_a9d4e49ac9ffdc8cef37485d72f894385486309a.patch linux-3.2.46/debian/patches/rpi/rpi_109_a9d4e49ac9ffdc8cef37485d72f894385486309a.patch --- linux-3.2.46/debian/patches/rpi/rpi_109_a9d4e49ac9ffdc8cef37485d72f894385486309a.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_109_a9d4e49ac9ffdc8cef37485d72f894385486309a.patch 2013-07-26 19:32:15.000000000 +0000 @@ -0,0 +1,42 @@ +commit a9d4e49ac9ffdc8cef37485d72f894385486309a +Author: Dom Cobley +Date: Sun Feb 12 20:27:35 2012 +0000 + + Add config option to enable L2 cache + + Signed-off-by: Dom Cobley + +Index: linux-3.2.46/arch/arm/mach-bcm2708/Kconfig +=================================================================== +--- linux-3.2.46.orig/arch/arm/mach-bcm2708/Kconfig 2013-07-26 19:31:51.000000000 +0000 ++++ linux-3.2.46/arch/arm/mach-bcm2708/Kconfig 2013-07-26 19:32:14.000000000 +0000 +@@ -22,4 +22,11 @@ + help + Helper for videocore memory access and total size allocation. + ++config BCM2708_L2CACHE ++ bool "Videocore L2 cache" ++ depends on MACH_BCM2708 ++ default n ++ help ++ Allow ARM to use GPU's L2 cache. Requires enable_l2cache in config.txt. ++ + endmenu +Index: linux-3.2.46/arch/arm/mach-bcm2708/include/mach/memory.h +=================================================================== +--- linux-3.2.46.orig/arch/arm/mach-bcm2708/include/mach/memory.h 2013-07-26 19:31:51.000000000 +0000 ++++ linux-3.2.46/arch/arm/mach-bcm2708/include/mach/memory.h 2013-07-26 19:32:14.000000000 +0000 +@@ -34,7 +34,12 @@ + */ + #define PHYS_OFFSET UL(0x00000000) + #define ARMMEM_OFFSET UL(0x00000000) /* offset in VC of ARM memory */ +-#define _REAL_BUS_OFFSET UL(0xC0000000) /* don't use L1 or L2 caches */ ++ ++#ifdef CONFIG_BCM2708_L2CACHE ++ #define _REAL_BUS_OFFSET UL(0x40000000) /* use L2 cache */ ++#else ++ #define _REAL_BUS_OFFSET UL(0xC0000000) /* don't use L1 or L2 caches */ ++#endif + + /* We're using the memory at 64M in the VideoCore for Linux - this adjustment + * will provide the offset into this area as well as setting the bits that diff -Nru linux-3.2.46/debian/patches/rpi/rpi_110_b3c82c8d884f1b1bd062d475d66eec965cd49625.patch linux-3.2.46/debian/patches/rpi/rpi_110_b3c82c8d884f1b1bd062d475d66eec965cd49625.patch --- linux-3.2.46/debian/patches/rpi/rpi_110_b3c82c8d884f1b1bd062d475d66eec965cd49625.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_110_b3c82c8d884f1b1bd062d475d66eec965cd49625.patch 2013-07-26 19:32:17.000000000 +0000 @@ -0,0 +1,21 @@ +commit b3c82c8d884f1b1bd062d475d66eec965cd49625 +Author: Dom Cobley +Date: Wed Feb 15 18:33:00 2012 +0000 + + Fix bug where vchiq fails when L2 enabled + + Signed-off-by: Dom Cobley + +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_2835_arm.c +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_2835_arm.c 2013-07-26 19:32:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_2835_arm.c 2013-07-26 19:32:16.000000000 +0000 +@@ -36,7 +36,7 @@ + #define TOTAL_SLOTS (VCHIQ_SLOT_ZERO_SLOTS + 2 * 32) + + #define VCHIQ_DOORBELL_IRQ IRQ_ARM_DOORBELL_0 +-#define VCHIQ_ARM_ADDRESS(x) __virt_to_bus(x) ++#define VCHIQ_ARM_ADDRESS(x) __virt_to_bus((unsigned)x) + + #include "vchiq_arm.h" + #include "vchiq_2835.h" diff -Nru linux-3.2.46/debian/patches/rpi/rpi_111_620c7805675cea7e398f8d210906685a09c27b1c.patch linux-3.2.46/debian/patches/rpi/rpi_111_620c7805675cea7e398f8d210906685a09c27b1c.patch --- linux-3.2.46/debian/patches/rpi/rpi_111_620c7805675cea7e398f8d210906685a09c27b1c.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_111_620c7805675cea7e398f8d210906685a09c27b1c.patch 2013-07-26 19:32:18.000000000 +0000 @@ -0,0 +1,1013 @@ +commit 620c7805675cea7e398f8d210906685a09c27b1c +Author: Dom Cobley +Date: Wed Mar 7 23:19:08 2012 +0000 + + Add devtmpfs for archlinux, and emergency and debug config + +Index: linux-3.2.46/arch/arm/configs/bcmrpi_cutdown_defconfig +=================================================================== +--- linux-3.2.46.orig/arch/arm/configs/bcmrpi_cutdown_defconfig 2013-07-26 19:32:13.000000000 +0000 ++++ linux-3.2.46/arch/arm/configs/bcmrpi_cutdown_defconfig 2013-07-26 19:32:17.000000000 +0000 +@@ -80,7 +80,7 @@ + CONFIG_NET_9P=m + CONFIG_NFC=m + CONFIG_NFC_PN533=m +-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" ++CONFIG_DEVTMPFS=y + CONFIG_BLK_DEV_LOOP=y + CONFIG_BLK_DEV_CRYPTOLOOP=m + CONFIG_BLK_DEV_NBD=m +Index: linux-3.2.46/arch/arm/configs/bcmrpi_defconfig +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/arch/arm/configs/bcmrpi_defconfig 2013-07-26 19:32:17.000000000 +0000 +@@ -0,0 +1,509 @@ ++CONFIG_EXPERIMENTAL=y ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_SYSVIPC=y ++CONFIG_POSIX_MQUEUE=y ++CONFIG_BSD_PROCESS_ACCT=y ++CONFIG_BSD_PROCESS_ACCT_V3=y ++CONFIG_FHANDLE=y ++CONFIG_AUDIT=y ++CONFIG_IKCONFIG=y ++CONFIG_IKCONFIG_PROC=y ++CONFIG_CGROUP_FREEZER=y ++CONFIG_CGROUP_DEVICE=y ++CONFIG_CGROUP_CPUACCT=y ++CONFIG_RESOURCE_COUNTERS=y ++CONFIG_BLK_CGROUP=y ++CONFIG_NAMESPACES=y ++CONFIG_SCHED_AUTOGROUP=y ++CONFIG_EMBEDDED=y ++# CONFIG_COMPAT_BRK is not set ++CONFIG_SLAB=y ++CONFIG_PROFILING=y ++CONFIG_OPROFILE=m ++CONFIG_KPROBES=y ++CONFIG_MODULES=y ++CONFIG_MODULE_UNLOAD=y ++CONFIG_MODVERSIONS=y ++CONFIG_MODULE_SRCVERSION_ALL=y ++# CONFIG_BLK_DEV_BSG is not set ++CONFIG_BLK_DEV_THROTTLING=y ++CONFIG_CFQ_GROUP_IOSCHED=y ++CONFIG_ARCH_BCM2708=y ++CONFIG_NO_HZ=y ++CONFIG_AEABI=y ++CONFIG_SECCOMP=y ++CONFIG_CC_STACKPROTECTOR=y ++CONFIG_ZBOOT_ROM_TEXT=0x0 ++CONFIG_ZBOOT_ROM_BSS=0x0 ++CONFIG_CMDLINE="dwc_otg.lpm_enable=0 console=ttyAMA0,115200 kgdboc=ttyAMA0,115200 root=/dev/mmcblk0p2 rootfstype=ext3 rootwait" ++CONFIG_KEXEC=y ++CONFIG_CPU_IDLE=y ++CONFIG_VFP=y ++CONFIG_BINFMT_MISC=m ++CONFIG_NET=y ++CONFIG_PACKET=y ++CONFIG_UNIX=y ++CONFIG_XFRM_USER=y ++CONFIG_NET_KEY=m ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_PNP=y ++CONFIG_IP_PNP_DHCP=y ++CONFIG_IP_PNP_RARP=y ++CONFIG_SYN_COOKIES=y ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_LRO is not set ++# CONFIG_INET_DIAG is not set ++# CONFIG_IPV6 is not set ++CONFIG_NET_PKTGEN=m ++CONFIG_IRDA=m ++CONFIG_IRLAN=m ++CONFIG_IRCOMM=m ++CONFIG_IRDA_ULTRA=y ++CONFIG_IRDA_CACHE_LAST_LSAP=y ++CONFIG_IRDA_FAST_RR=y ++CONFIG_IRTTY_SIR=m ++CONFIG_KINGSUN_DONGLE=m ++CONFIG_KSDAZZLE_DONGLE=m ++CONFIG_KS959_DONGLE=m ++CONFIG_USB_IRDA=m ++CONFIG_SIGMATEL_FIR=m ++CONFIG_MCS_FIR=m ++CONFIG_BT=m ++CONFIG_BT_L2CAP=y ++CONFIG_BT_SCO=y ++CONFIG_BT_RFCOMM=m ++CONFIG_BT_RFCOMM_TTY=y ++CONFIG_BT_BNEP=m ++CONFIG_BT_BNEP_MC_FILTER=y ++CONFIG_BT_BNEP_PROTO_FILTER=y ++CONFIG_BT_HIDP=m ++CONFIG_BT_HCIBTUSB=m ++CONFIG_BT_HCIBCM203X=m ++CONFIG_BT_HCIBPA10X=m ++CONFIG_BT_HCIBFUSB=m ++CONFIG_BT_HCIVHCI=m ++CONFIG_BT_MRVL=m ++CONFIG_BT_MRVL_SDIO=m ++CONFIG_BT_ATH3K=m ++CONFIG_CFG80211=m ++CONFIG_MAC80211=m ++CONFIG_MAC80211_RC_PID=y ++CONFIG_MAC80211_MESH=y ++CONFIG_WIMAX=m ++CONFIG_NET_9P=m ++CONFIG_NFC=m ++CONFIG_NFC_PN533=m ++CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" ++CONFIG_BLK_DEV_LOOP=y ++CONFIG_BLK_DEV_CRYPTOLOOP=m ++CONFIG_BLK_DEV_NBD=m ++CONFIG_BLK_DEV_RAM=y ++CONFIG_CDROM_PKTCDVD=m ++CONFIG_MISC_DEVICES=y ++CONFIG_SCSI=y ++# CONFIG_SCSI_PROC_FS is not set ++CONFIG_BLK_DEV_SD=m ++CONFIG_BLK_DEV_SR=m ++CONFIG_SCSI_MULTI_LUN=y ++# CONFIG_SCSI_LOWLEVEL is not set ++CONFIG_MD=y ++CONFIG_NETDEVICES=y ++CONFIG_TUN=m ++CONFIG_PHYLIB=m ++CONFIG_MDIO_BITBANG=m ++CONFIG_NET_ETHERNET=y ++# CONFIG_NETDEV_1000 is not set ++# CONFIG_NETDEV_10000 is not set ++CONFIG_LIBERTAS_THINFIRM=m ++CONFIG_LIBERTAS_THINFIRM_USB=m ++CONFIG_AT76C50X_USB=m ++CONFIG_USB_ZD1201=m ++CONFIG_USB_NET_RNDIS_WLAN=m ++CONFIG_RTL8187=m ++CONFIG_MAC80211_HWSIM=m ++CONFIG_ATH_COMMON=m ++CONFIG_ATH9K=m ++CONFIG_ATH9K_HTC=m ++CONFIG_CARL9170=m ++CONFIG_B43=m ++CONFIG_B43LEGACY=m ++CONFIG_HOSTAP=m ++CONFIG_IWM=m ++CONFIG_LIBERTAS=m ++CONFIG_LIBERTAS_USB=m ++CONFIG_LIBERTAS_SDIO=m ++CONFIG_P54_COMMON=m ++CONFIG_P54_USB=m ++CONFIG_RT2X00=m ++CONFIG_RT2500USB=m ++CONFIG_RT73USB=m ++CONFIG_RT2800USB=m ++CONFIG_RT2800USB_RT53XX=y ++CONFIG_RTL8192CU=m ++CONFIG_WL1251=m ++CONFIG_WL12XX_MENU=m ++CONFIG_ZD1211RW=m ++CONFIG_MWIFIEX=m ++CONFIG_MWIFIEX_SDIO=m ++CONFIG_WIMAX_I2400M_USB=m ++CONFIG_USB_CATC=m ++CONFIG_USB_KAWETH=m ++CONFIG_USB_PEGASUS=m ++CONFIG_USB_RTL8150=m ++CONFIG_USB_USBNET=y ++CONFIG_USB_NET_AX8817X=m ++CONFIG_USB_NET_CDCETHER=m ++CONFIG_USB_NET_CDC_EEM=m ++CONFIG_USB_NET_DM9601=m ++CONFIG_USB_NET_SMSC75XX=m ++CONFIG_USB_NET_SMSC95XX=y ++CONFIG_USB_NET_GL620A=m ++CONFIG_USB_NET_NET1080=m ++CONFIG_USB_NET_PLUSB=m ++CONFIG_USB_NET_MCS7830=m ++CONFIG_USB_NET_CDC_SUBSET=m ++CONFIG_USB_ALI_M5632=y ++CONFIG_USB_AN2720=y ++CONFIG_USB_KC2190=y ++# CONFIG_USB_NET_ZAURUS is not set ++CONFIG_USB_NET_CX82310_ETH=m ++CONFIG_USB_NET_KALMIA=m ++CONFIG_USB_NET_INT51X1=m ++CONFIG_USB_IPHETH=m ++CONFIG_USB_SIERRA_NET=m ++CONFIG_USB_VL600=m ++CONFIG_PPP=m ++CONFIG_PPP_ASYNC=m ++CONFIG_PPP_SYNC_TTY=m ++CONFIG_PPP_DEFLATE=m ++CONFIG_PPP_BSDCOMP=m ++CONFIG_SLIP=m ++CONFIG_SLIP_COMPRESSED=y ++CONFIG_NETCONSOLE=m ++CONFIG_INPUT_POLLDEV=m ++# CONFIG_INPUT_MOUSEDEV_PSAUX is not set ++CONFIG_INPUT_JOYDEV=m ++CONFIG_INPUT_EVDEV=m ++# CONFIG_INPUT_KEYBOARD is not set ++# CONFIG_INPUT_MOUSE is not set ++CONFIG_INPUT_MISC=y ++CONFIG_INPUT_AD714X=m ++CONFIG_INPUT_ATI_REMOTE=m ++CONFIG_INPUT_ATI_REMOTE2=m ++CONFIG_INPUT_KEYSPAN_REMOTE=m ++CONFIG_INPUT_POWERMATE=m ++CONFIG_INPUT_YEALINK=m ++CONFIG_INPUT_CM109=m ++CONFIG_INPUT_UINPUT=m ++CONFIG_INPUT_GPIO_ROTARY_ENCODER=m ++CONFIG_INPUT_ADXL34X=m ++CONFIG_INPUT_CMA3000=m ++CONFIG_SERIO=m ++CONFIG_SERIO_RAW=m ++CONFIG_GAMEPORT=m ++CONFIG_GAMEPORT_NS558=m ++CONFIG_GAMEPORT_L4=m ++CONFIG_VT_HW_CONSOLE_BINDING=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_DEVKMEM is not set ++CONFIG_SERIAL_AMBA_PL011=y ++CONFIG_SERIAL_AMBA_PL011_CONSOLE=y ++# CONFIG_HW_RANDOM is not set ++CONFIG_RAW_DRIVER=y ++CONFIG_GPIO_SYSFS=y ++# CONFIG_HWMON is not set ++CONFIG_WATCHDOG=y ++CONFIG_BCM2708_WDT=m ++# CONFIG_MFD_SUPPORT is not set ++CONFIG_FB=y ++CONFIG_FB_BCM2708=y ++CONFIG_FRAMEBUFFER_CONSOLE=y ++CONFIG_LOGO=y ++# CONFIG_LOGO_LINUX_MONO is not set ++# CONFIG_LOGO_LINUX_VGA16 is not set ++CONFIG_HID_PID=y ++CONFIG_USB_HIDDEV=y ++CONFIG_HID_A4TECH=m ++CONFIG_HID_ACRUX=m ++CONFIG_HID_APPLE=m ++CONFIG_HID_BELKIN=m ++CONFIG_HID_CHERRY=m ++CONFIG_HID_CHICONY=m ++CONFIG_HID_CYPRESS=m ++CONFIG_HID_DRAGONRISE=m ++CONFIG_HID_EMS_FF=m ++CONFIG_HID_ELECOM=m ++CONFIG_HID_EZKEY=m ++CONFIG_HID_HOLTEK=m ++CONFIG_HID_KEYTOUCH=m ++CONFIG_HID_KYE=m ++CONFIG_HID_UCLOGIC=m ++CONFIG_HID_WALTOP=m ++CONFIG_HID_GYRATION=m ++CONFIG_HID_TWINHAN=m ++CONFIG_HID_KENSINGTON=m ++CONFIG_HID_LCPOWER=m ++CONFIG_HID_LOGITECH=m ++CONFIG_HID_MAGICMOUSE=m ++CONFIG_HID_MICROSOFT=m ++CONFIG_HID_MONTEREY=m ++CONFIG_HID_MULTITOUCH=m ++CONFIG_HID_NTRIG=m ++CONFIG_HID_ORTEK=m ++CONFIG_HID_PANTHERLORD=m ++CONFIG_HID_PETALYNX=m ++CONFIG_HID_PICOLCD=m ++CONFIG_HID_QUANTA=m ++CONFIG_HID_ROCCAT=m ++CONFIG_HID_SAMSUNG=m ++CONFIG_HID_SONY=m ++CONFIG_HID_SPEEDLINK=m ++CONFIG_HID_SUNPLUS=m ++CONFIG_HID_GREENASIA=m ++CONFIG_HID_SMARTJOYPLUS=m ++CONFIG_HID_TOPSEED=m ++CONFIG_HID_THRUSTMASTER=m ++CONFIG_HID_WACOM=m ++CONFIG_HID_WIIMOTE=m ++CONFIG_HID_ZEROPLUS=m ++CONFIG_HID_ZYDACRON=m ++CONFIG_USB=y ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++CONFIG_USB_MON=m ++CONFIG_USB_DWCOTG=y ++CONFIG_USB_STORAGE=y ++CONFIG_USB_STORAGE_REALTEK=m ++CONFIG_USB_STORAGE_DATAFAB=m ++CONFIG_USB_STORAGE_FREECOM=m ++CONFIG_USB_STORAGE_ISD200=m ++CONFIG_USB_STORAGE_USBAT=m ++CONFIG_USB_STORAGE_SDDR09=m ++CONFIG_USB_STORAGE_SDDR55=m ++CONFIG_USB_STORAGE_JUMPSHOT=m ++CONFIG_USB_STORAGE_ALAUDA=m ++CONFIG_USB_STORAGE_ONETOUCH=m ++CONFIG_USB_STORAGE_KARMA=m ++CONFIG_USB_STORAGE_CYPRESS_ATACB=m ++CONFIG_USB_STORAGE_ENE_UB6250=m ++CONFIG_USB_UAS=m ++CONFIG_USB_LIBUSUAL=y ++CONFIG_USB_MDC800=m ++CONFIG_USB_MICROTEK=m ++CONFIG_USB_SERIAL=m ++CONFIG_USB_SERIAL_GENERIC=y ++CONFIG_USB_SERIAL_AIRCABLE=m ++CONFIG_USB_SERIAL_ARK3116=m ++CONFIG_USB_SERIAL_BELKIN=m ++CONFIG_USB_SERIAL_CH341=m ++CONFIG_USB_SERIAL_WHITEHEAT=m ++CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m ++CONFIG_USB_SERIAL_CP210X=m ++CONFIG_USB_SERIAL_CYPRESS_M8=m ++CONFIG_USB_SERIAL_EMPEG=m ++CONFIG_USB_SERIAL_FTDI_SIO=m ++CONFIG_USB_SERIAL_FUNSOFT=m ++CONFIG_USB_SERIAL_VISOR=m ++CONFIG_USB_SERIAL_IPAQ=m ++CONFIG_USB_SERIAL_IR=m ++CONFIG_USB_SERIAL_EDGEPORT=m ++CONFIG_USB_SERIAL_EDGEPORT_TI=m ++CONFIG_USB_SERIAL_GARMIN=m ++CONFIG_USB_SERIAL_IPW=m ++CONFIG_USB_SERIAL_IUU=m ++CONFIG_USB_SERIAL_KEYSPAN_PDA=m ++CONFIG_USB_SERIAL_KEYSPAN=m ++CONFIG_USB_SERIAL_KLSI=m ++CONFIG_USB_SERIAL_KOBIL_SCT=m ++CONFIG_USB_SERIAL_MCT_U232=m ++CONFIG_USB_SERIAL_MOS7720=m ++CONFIG_USB_SERIAL_MOS7840=m ++CONFIG_USB_SERIAL_MOTOROLA=m ++CONFIG_USB_SERIAL_NAVMAN=m ++CONFIG_USB_SERIAL_PL2303=m ++CONFIG_USB_SERIAL_OTI6858=m ++CONFIG_USB_SERIAL_QCAUX=m ++CONFIG_USB_SERIAL_QUALCOMM=m ++CONFIG_USB_SERIAL_SPCP8X5=m ++CONFIG_USB_SERIAL_HP4X=m ++CONFIG_USB_SERIAL_SAFE=m ++CONFIG_USB_SERIAL_SIEMENS_MPI=m ++CONFIG_USB_SERIAL_SIERRAWIRELESS=m ++CONFIG_USB_SERIAL_SYMBOL=m ++CONFIG_USB_SERIAL_TI=m ++CONFIG_USB_SERIAL_CYBERJACK=m ++CONFIG_USB_SERIAL_XIRCOM=m ++CONFIG_USB_SERIAL_OPTION=m ++CONFIG_USB_SERIAL_OMNINET=m ++CONFIG_USB_SERIAL_OPTICON=m ++CONFIG_USB_SERIAL_VIVOPAY_SERIAL=m ++CONFIG_USB_SERIAL_ZIO=m ++CONFIG_USB_SERIAL_SSU100=m ++CONFIG_USB_SERIAL_DEBUG=m ++CONFIG_USB_EMI62=m ++CONFIG_USB_EMI26=m ++CONFIG_USB_ADUTUX=m ++CONFIG_USB_SEVSEG=m ++CONFIG_USB_RIO500=m ++CONFIG_USB_LEGOTOWER=m ++CONFIG_USB_LCD=m ++CONFIG_USB_LED=m ++CONFIG_USB_CYPRESS_CY7C63=m ++CONFIG_USB_CYTHERM=m ++CONFIG_USB_IDMOUSE=m ++CONFIG_USB_FTDI_ELAN=m ++CONFIG_USB_APPLEDISPLAY=m ++CONFIG_USB_LD=m ++CONFIG_USB_TRANCEVIBRATOR=m ++CONFIG_USB_IOWARRIOR=m ++CONFIG_USB_TEST=m ++CONFIG_USB_ISIGHTFW=m ++CONFIG_USB_YUREX=m ++CONFIG_MMC=y ++CONFIG_MMC_SDHCI=y ++CONFIG_MMC_SDHCI_PLTFM=y ++CONFIG_MMC_SDHCI_BCM2708=y ++CONFIG_MMC_SDHCI_BCM2708_DMA=y ++CONFIG_LEDS_GPIO=y ++CONFIG_LEDS_TRIGGER_TIMER=m ++CONFIG_LEDS_TRIGGER_HEARTBEAT=m ++CONFIG_LEDS_TRIGGER_DEFAULT_ON=m ++CONFIG_UIO=m ++CONFIG_UIO_PDRV=m ++CONFIG_UIO_PDRV_GENIRQ=m ++# CONFIG_IOMMU_SUPPORT is not set ++CONFIG_EXT4_FS=y ++CONFIG_EXT4_FS_POSIX_ACL=y ++CONFIG_EXT4_FS_SECURITY=y ++CONFIG_REISERFS_FS=m ++CONFIG_REISERFS_FS_XATTR=y ++CONFIG_REISERFS_FS_POSIX_ACL=y ++CONFIG_REISERFS_FS_SECURITY=y ++CONFIG_JFS_FS=m ++CONFIG_JFS_POSIX_ACL=y ++CONFIG_JFS_SECURITY=y ++CONFIG_JFS_STATISTICS=y ++CONFIG_XFS_FS=m ++CONFIG_XFS_QUOTA=y ++CONFIG_XFS_POSIX_ACL=y ++CONFIG_XFS_RT=y ++CONFIG_GFS2_FS=m ++CONFIG_OCFS2_FS=m ++CONFIG_BTRFS_FS=m ++CONFIG_BTRFS_FS_POSIX_ACL=y ++CONFIG_NILFS2_FS=m ++CONFIG_FANOTIFY=y ++CONFIG_AUTOFS4_FS=y ++CONFIG_FUSE_FS=m ++CONFIG_CUSE=m ++CONFIG_FSCACHE=y ++CONFIG_FSCACHE_STATS=y ++CONFIG_FSCACHE_HISTOGRAM=y ++CONFIG_CACHEFILES=y ++CONFIG_ISO9660_FS=m ++CONFIG_JOLIET=y ++CONFIG_ZISOFS=y ++CONFIG_UDF_FS=m ++CONFIG_MSDOS_FS=y ++CONFIG_VFAT_FS=y ++CONFIG_FAT_DEFAULT_IOCHARSET="ascii" ++CONFIG_NTFS_FS=m ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++CONFIG_CONFIGFS_FS=y ++CONFIG_SQUASHFS=m ++CONFIG_SQUASHFS_XATTR=y ++CONFIG_SQUASHFS_LZO=y ++CONFIG_SQUASHFS_XZ=y ++CONFIG_NFS_FS=y ++CONFIG_NFS_V3=y ++CONFIG_NFS_V3_ACL=y ++CONFIG_NFS_V4=y ++CONFIG_ROOT_NFS=y ++CONFIG_NFS_FSCACHE=y ++CONFIG_CIFS=m ++CONFIG_CIFS_WEAK_PW_HASH=y ++CONFIG_CIFS_XATTR=y ++CONFIG_CIFS_POSIX=y ++CONFIG_9P_FS=m ++CONFIG_9P_FS_POSIX_ACL=y ++CONFIG_PARTITION_ADVANCED=y ++CONFIG_MAC_PARTITION=y ++CONFIG_EFI_PARTITION=y ++CONFIG_NLS_DEFAULT="utf8" ++CONFIG_NLS_CODEPAGE_437=y ++CONFIG_NLS_CODEPAGE_737=m ++CONFIG_NLS_CODEPAGE_775=m ++CONFIG_NLS_CODEPAGE_850=m ++CONFIG_NLS_CODEPAGE_852=m ++CONFIG_NLS_CODEPAGE_855=m ++CONFIG_NLS_CODEPAGE_857=m ++CONFIG_NLS_CODEPAGE_860=m ++CONFIG_NLS_CODEPAGE_861=m ++CONFIG_NLS_CODEPAGE_862=m ++CONFIG_NLS_CODEPAGE_863=m ++CONFIG_NLS_CODEPAGE_864=m ++CONFIG_NLS_CODEPAGE_865=m ++CONFIG_NLS_CODEPAGE_866=m ++CONFIG_NLS_CODEPAGE_869=m ++CONFIG_NLS_CODEPAGE_936=m ++CONFIG_NLS_CODEPAGE_950=m ++CONFIG_NLS_CODEPAGE_932=m ++CONFIG_NLS_CODEPAGE_949=m ++CONFIG_NLS_CODEPAGE_874=m ++CONFIG_NLS_ISO8859_8=m ++CONFIG_NLS_CODEPAGE_1250=m ++CONFIG_NLS_CODEPAGE_1251=m ++CONFIG_NLS_ASCII=y ++CONFIG_NLS_ISO8859_1=m ++CONFIG_NLS_ISO8859_2=m ++CONFIG_NLS_ISO8859_3=m ++CONFIG_NLS_ISO8859_4=m ++CONFIG_NLS_ISO8859_5=m ++CONFIG_NLS_ISO8859_6=m ++CONFIG_NLS_ISO8859_7=m ++CONFIG_NLS_ISO8859_9=m ++CONFIG_NLS_ISO8859_13=m ++CONFIG_NLS_ISO8859_14=m ++CONFIG_NLS_ISO8859_15=m ++CONFIG_NLS_KOI8_R=m ++CONFIG_NLS_KOI8_U=m ++CONFIG_NLS_UTF8=m ++CONFIG_PRINTK_TIME=y ++CONFIG_DETECT_HUNG_TASK=y ++CONFIG_TIMER_STATS=y ++CONFIG_DEBUG_STACK_USAGE=y ++CONFIG_DEBUG_INFO=y ++CONFIG_DEBUG_MEMORY_INIT=y ++CONFIG_BOOT_PRINTK_DELAY=y ++CONFIG_LATENCYTOP=y ++CONFIG_SYSCTL_SYSCALL_CHECK=y ++CONFIG_IRQSOFF_TRACER=y ++CONFIG_SCHED_TRACER=y ++CONFIG_STACK_TRACER=y ++CONFIG_BLK_DEV_IO_TRACE=y ++CONFIG_FUNCTION_PROFILER=y ++CONFIG_KGDB=y ++CONFIG_KGDB_KDB=y ++CONFIG_KDB_KEYBOARD=y ++CONFIG_STRICT_DEVMEM=y ++CONFIG_CRYPTO_AUTHENC=m ++CONFIG_CRYPTO_SEQIV=m ++CONFIG_CRYPTO_CBC=y ++CONFIG_CRYPTO_HMAC=y ++CONFIG_CRYPTO_XCBC=m ++CONFIG_CRYPTO_MD5=y ++CONFIG_CRYPTO_SHA1=y ++CONFIG_CRYPTO_SHA256=m ++CONFIG_CRYPTO_SHA512=m ++CONFIG_CRYPTO_TGR192=m ++CONFIG_CRYPTO_WP512=m ++CONFIG_CRYPTO_CAST5=m ++CONFIG_CRYPTO_DES=y ++CONFIG_CRYPTO_DEFLATE=m ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++# CONFIG_CRYPTO_HW is not set ++CONFIG_CRC_ITU_T=y ++CONFIG_LIBCRC32C=y +Index: linux-3.2.46/arch/arm/configs/bcmrpi_emergency_defconfig +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/arch/arm/configs/bcmrpi_emergency_defconfig 2013-07-26 19:32:17.000000000 +0000 +@@ -0,0 +1,475 @@ ++CONFIG_EXPERIMENTAL=y ++# CONFIG_LOCALVERSION_AUTO is not set ++CONFIG_SYSVIPC=y ++CONFIG_POSIX_MQUEUE=y ++CONFIG_IKCONFIG=y ++CONFIG_IKCONFIG_PROC=y ++CONFIG_BLK_DEV_INITRD=y ++CONFIG_INITRAMFS_SOURCE="../target_fs" ++# CONFIG_UID16 is not set ++# CONFIG_KALLSYMS is not set ++CONFIG_EMBEDDED=y ++# CONFIG_VM_EVENT_COUNTERS is not set ++# CONFIG_COMPAT_BRK is not set ++CONFIG_SLAB=y ++CONFIG_MODULES=y ++CONFIG_MODULE_UNLOAD=y ++CONFIG_MODVERSIONS=y ++CONFIG_MODULE_SRCVERSION_ALL=y ++# CONFIG_BLK_DEV_BSG is not set ++CONFIG_ARCH_BCM2708=y ++CONFIG_NO_HZ=y ++CONFIG_AEABI=y ++CONFIG_ZBOOT_ROM_TEXT=0x0 ++CONFIG_ZBOOT_ROM_BSS=0x0 ++CONFIG_CMDLINE="dwc_otg.lpm_enable=0 console=ttyAMA0,115200 kgdboc=ttyAMA0,115200 root=/dev/mmcblk0p2 rootfstype=ext3 rootwait" ++CONFIG_CPU_IDLE=y ++CONFIG_VFP=y ++CONFIG_BINFMT_MISC=m ++CONFIG_NET=y ++CONFIG_PACKET=y ++CONFIG_UNIX=y ++CONFIG_XFRM_USER=y ++CONFIG_NET_KEY=m ++CONFIG_INET=y ++CONFIG_IP_MULTICAST=y ++CONFIG_IP_PNP=y ++CONFIG_IP_PNP_DHCP=y ++CONFIG_IP_PNP_RARP=y ++CONFIG_SYN_COOKIES=y ++# CONFIG_INET_XFRM_MODE_TRANSPORT is not set ++# CONFIG_INET_XFRM_MODE_TUNNEL is not set ++# CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_LRO is not set ++# CONFIG_INET_DIAG is not set ++# CONFIG_IPV6 is not set ++CONFIG_NET_PKTGEN=m ++CONFIG_IRDA=m ++CONFIG_IRLAN=m ++CONFIG_IRCOMM=m ++CONFIG_IRDA_ULTRA=y ++CONFIG_IRDA_CACHE_LAST_LSAP=y ++CONFIG_IRDA_FAST_RR=y ++CONFIG_IRTTY_SIR=m ++CONFIG_KINGSUN_DONGLE=m ++CONFIG_KSDAZZLE_DONGLE=m ++CONFIG_KS959_DONGLE=m ++CONFIG_USB_IRDA=m ++CONFIG_SIGMATEL_FIR=m ++CONFIG_MCS_FIR=m ++CONFIG_BT=m ++CONFIG_BT_L2CAP=y ++CONFIG_BT_SCO=y ++CONFIG_BT_RFCOMM=m ++CONFIG_BT_RFCOMM_TTY=y ++CONFIG_BT_BNEP=m ++CONFIG_BT_BNEP_MC_FILTER=y ++CONFIG_BT_BNEP_PROTO_FILTER=y ++CONFIG_BT_HIDP=m ++CONFIG_BT_HCIBTUSB=m ++CONFIG_BT_HCIBCM203X=m ++CONFIG_BT_HCIBPA10X=m ++CONFIG_BT_HCIBFUSB=m ++CONFIG_BT_HCIVHCI=m ++CONFIG_BT_MRVL=m ++CONFIG_BT_MRVL_SDIO=m ++CONFIG_BT_ATH3K=m ++CONFIG_CFG80211=m ++CONFIG_MAC80211=m ++CONFIG_MAC80211_RC_PID=y ++CONFIG_MAC80211_MESH=y ++CONFIG_WIMAX=m ++CONFIG_NET_9P=m ++CONFIG_NFC=m ++CONFIG_NFC_PN533=m ++CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" ++CONFIG_BLK_DEV_LOOP=y ++CONFIG_BLK_DEV_CRYPTOLOOP=m ++CONFIG_BLK_DEV_NBD=m ++CONFIG_BLK_DEV_RAM=y ++CONFIG_CDROM_PKTCDVD=m ++CONFIG_MISC_DEVICES=y ++CONFIG_SCSI=y ++# CONFIG_SCSI_PROC_FS is not set ++CONFIG_BLK_DEV_SD=m ++CONFIG_BLK_DEV_SR=m ++CONFIG_SCSI_MULTI_LUN=y ++# CONFIG_SCSI_LOWLEVEL is not set ++CONFIG_NETDEVICES=y ++CONFIG_TUN=m ++CONFIG_PHYLIB=m ++CONFIG_MDIO_BITBANG=m ++CONFIG_NET_ETHERNET=y ++# CONFIG_NETDEV_1000 is not set ++# CONFIG_NETDEV_10000 is not set ++CONFIG_LIBERTAS_THINFIRM=m ++CONFIG_LIBERTAS_THINFIRM_USB=m ++CONFIG_AT76C50X_USB=m ++CONFIG_USB_ZD1201=m ++CONFIG_USB_NET_RNDIS_WLAN=m ++CONFIG_RTL8187=m ++CONFIG_MAC80211_HWSIM=m ++CONFIG_ATH_COMMON=m ++CONFIG_ATH9K=m ++CONFIG_ATH9K_HTC=m ++CONFIG_CARL9170=m ++CONFIG_B43=m ++CONFIG_B43LEGACY=m ++CONFIG_HOSTAP=m ++CONFIG_IWM=m ++CONFIG_LIBERTAS=m ++CONFIG_LIBERTAS_USB=m ++CONFIG_LIBERTAS_SDIO=m ++CONFIG_P54_COMMON=m ++CONFIG_P54_USB=m ++CONFIG_RT2X00=m ++CONFIG_RT2500USB=m ++CONFIG_RT73USB=m ++CONFIG_RT2800USB=m ++CONFIG_RT2800USB_RT53XX=y ++CONFIG_RTL8192CU=m ++CONFIG_WL1251=m ++CONFIG_WL12XX_MENU=m ++CONFIG_ZD1211RW=m ++CONFIG_MWIFIEX=m ++CONFIG_MWIFIEX_SDIO=m ++CONFIG_WIMAX_I2400M_USB=m ++CONFIG_USB_CATC=m ++CONFIG_USB_KAWETH=m ++CONFIG_USB_PEGASUS=m ++CONFIG_USB_RTL8150=m ++CONFIG_USB_USBNET=y ++CONFIG_USB_NET_AX8817X=m ++CONFIG_USB_NET_CDCETHER=m ++CONFIG_USB_NET_CDC_EEM=m ++CONFIG_USB_NET_DM9601=m ++CONFIG_USB_NET_SMSC75XX=m ++CONFIG_USB_NET_SMSC95XX=y ++CONFIG_USB_NET_GL620A=m ++CONFIG_USB_NET_NET1080=m ++CONFIG_USB_NET_PLUSB=m ++CONFIG_USB_NET_MCS7830=m ++CONFIG_USB_NET_CDC_SUBSET=m ++CONFIG_USB_ALI_M5632=y ++CONFIG_USB_AN2720=y ++CONFIG_USB_KC2190=y ++# CONFIG_USB_NET_ZAURUS is not set ++CONFIG_USB_NET_CX82310_ETH=m ++CONFIG_USB_NET_KALMIA=m ++CONFIG_USB_NET_INT51X1=m ++CONFIG_USB_IPHETH=m ++CONFIG_USB_SIERRA_NET=m ++CONFIG_USB_VL600=m ++CONFIG_PPP=m ++CONFIG_PPP_ASYNC=m ++CONFIG_PPP_SYNC_TTY=m ++CONFIG_PPP_DEFLATE=m ++CONFIG_PPP_BSDCOMP=m ++CONFIG_SLIP=m ++CONFIG_SLIP_COMPRESSED=y ++CONFIG_NETCONSOLE=m ++CONFIG_INPUT_POLLDEV=m ++# CONFIG_INPUT_MOUSEDEV_PSAUX is not set ++CONFIG_INPUT_JOYDEV=m ++CONFIG_INPUT_EVDEV=m ++# CONFIG_INPUT_KEYBOARD is not set ++# CONFIG_INPUT_MOUSE is not set ++CONFIG_INPUT_MISC=y ++CONFIG_INPUT_AD714X=m ++CONFIG_INPUT_ATI_REMOTE=m ++CONFIG_INPUT_ATI_REMOTE2=m ++CONFIG_INPUT_KEYSPAN_REMOTE=m ++CONFIG_INPUT_POWERMATE=m ++CONFIG_INPUT_YEALINK=m ++CONFIG_INPUT_CM109=m ++CONFIG_INPUT_UINPUT=m ++CONFIG_INPUT_GPIO_ROTARY_ENCODER=m ++CONFIG_INPUT_ADXL34X=m ++CONFIG_INPUT_CMA3000=m ++CONFIG_SERIO=m ++CONFIG_SERIO_RAW=m ++CONFIG_GAMEPORT=m ++CONFIG_GAMEPORT_NS558=m ++CONFIG_GAMEPORT_L4=m ++CONFIG_VT_HW_CONSOLE_BINDING=y ++# CONFIG_LEGACY_PTYS is not set ++# CONFIG_DEVKMEM is not set ++CONFIG_SERIAL_AMBA_PL011=y ++CONFIG_SERIAL_AMBA_PL011_CONSOLE=y ++# CONFIG_HW_RANDOM is not set ++CONFIG_RAW_DRIVER=y ++CONFIG_GPIO_SYSFS=y ++# CONFIG_HWMON is not set ++CONFIG_WATCHDOG=y ++CONFIG_BCM2708_WDT=m ++# CONFIG_MFD_SUPPORT is not set ++CONFIG_FB=y ++CONFIG_FB_BCM2708=y ++CONFIG_FRAMEBUFFER_CONSOLE=y ++CONFIG_LOGO=y ++# CONFIG_LOGO_LINUX_MONO is not set ++# CONFIG_LOGO_LINUX_VGA16 is not set ++CONFIG_HID_PID=y ++CONFIG_USB_HIDDEV=y ++CONFIG_HID_A4TECH=m ++CONFIG_HID_ACRUX=m ++CONFIG_HID_APPLE=m ++CONFIG_HID_BELKIN=m ++CONFIG_HID_CHERRY=m ++CONFIG_HID_CHICONY=m ++CONFIG_HID_CYPRESS=m ++CONFIG_HID_DRAGONRISE=m ++CONFIG_HID_EMS_FF=m ++CONFIG_HID_ELECOM=m ++CONFIG_HID_EZKEY=m ++CONFIG_HID_HOLTEK=m ++CONFIG_HID_KEYTOUCH=m ++CONFIG_HID_KYE=m ++CONFIG_HID_UCLOGIC=m ++CONFIG_HID_WALTOP=m ++CONFIG_HID_GYRATION=m ++CONFIG_HID_TWINHAN=m ++CONFIG_HID_KENSINGTON=m ++CONFIG_HID_LCPOWER=m ++CONFIG_HID_LOGITECH=m ++CONFIG_HID_MAGICMOUSE=m ++CONFIG_HID_MICROSOFT=m ++CONFIG_HID_MONTEREY=m ++CONFIG_HID_MULTITOUCH=m ++CONFIG_HID_NTRIG=m ++CONFIG_HID_ORTEK=m ++CONFIG_HID_PANTHERLORD=m ++CONFIG_HID_PETALYNX=m ++CONFIG_HID_PICOLCD=m ++CONFIG_HID_QUANTA=m ++CONFIG_HID_ROCCAT=m ++CONFIG_HID_SAMSUNG=m ++CONFIG_HID_SONY=m ++CONFIG_HID_SPEEDLINK=m ++CONFIG_HID_SUNPLUS=m ++CONFIG_HID_GREENASIA=m ++CONFIG_HID_SMARTJOYPLUS=m ++CONFIG_HID_TOPSEED=m ++CONFIG_HID_THRUSTMASTER=m ++CONFIG_HID_WACOM=m ++CONFIG_HID_WIIMOTE=m ++CONFIG_HID_ZEROPLUS=m ++CONFIG_HID_ZYDACRON=m ++CONFIG_USB=y ++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y ++CONFIG_USB_MON=m ++CONFIG_USB_DWCOTG=y ++CONFIG_USB_STORAGE=y ++CONFIG_USB_STORAGE_REALTEK=m ++CONFIG_USB_STORAGE_DATAFAB=m ++CONFIG_USB_STORAGE_FREECOM=m ++CONFIG_USB_STORAGE_ISD200=m ++CONFIG_USB_STORAGE_USBAT=m ++CONFIG_USB_STORAGE_SDDR09=m ++CONFIG_USB_STORAGE_SDDR55=m ++CONFIG_USB_STORAGE_JUMPSHOT=m ++CONFIG_USB_STORAGE_ALAUDA=m ++CONFIG_USB_STORAGE_ONETOUCH=m ++CONFIG_USB_STORAGE_KARMA=m ++CONFIG_USB_STORAGE_CYPRESS_ATACB=m ++CONFIG_USB_STORAGE_ENE_UB6250=m ++CONFIG_USB_UAS=m ++CONFIG_USB_LIBUSUAL=y ++CONFIG_USB_MDC800=m ++CONFIG_USB_MICROTEK=m ++CONFIG_USB_SERIAL=m ++CONFIG_USB_SERIAL_GENERIC=y ++CONFIG_USB_SERIAL_AIRCABLE=m ++CONFIG_USB_SERIAL_ARK3116=m ++CONFIG_USB_SERIAL_BELKIN=m ++CONFIG_USB_SERIAL_CH341=m ++CONFIG_USB_SERIAL_WHITEHEAT=m ++CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m ++CONFIG_USB_SERIAL_CP210X=m ++CONFIG_USB_SERIAL_CYPRESS_M8=m ++CONFIG_USB_SERIAL_EMPEG=m ++CONFIG_USB_SERIAL_FTDI_SIO=m ++CONFIG_USB_SERIAL_FUNSOFT=m ++CONFIG_USB_SERIAL_VISOR=m ++CONFIG_USB_SERIAL_IPAQ=m ++CONFIG_USB_SERIAL_IR=m ++CONFIG_USB_SERIAL_EDGEPORT=m ++CONFIG_USB_SERIAL_EDGEPORT_TI=m ++CONFIG_USB_SERIAL_GARMIN=m ++CONFIG_USB_SERIAL_IPW=m ++CONFIG_USB_SERIAL_IUU=m ++CONFIG_USB_SERIAL_KEYSPAN_PDA=m ++CONFIG_USB_SERIAL_KEYSPAN=m ++CONFIG_USB_SERIAL_KLSI=m ++CONFIG_USB_SERIAL_KOBIL_SCT=m ++CONFIG_USB_SERIAL_MCT_U232=m ++CONFIG_USB_SERIAL_MOS7720=m ++CONFIG_USB_SERIAL_MOS7840=m ++CONFIG_USB_SERIAL_MOTOROLA=m ++CONFIG_USB_SERIAL_NAVMAN=m ++CONFIG_USB_SERIAL_PL2303=m ++CONFIG_USB_SERIAL_OTI6858=m ++CONFIG_USB_SERIAL_QCAUX=m ++CONFIG_USB_SERIAL_QUALCOMM=m ++CONFIG_USB_SERIAL_SPCP8X5=m ++CONFIG_USB_SERIAL_HP4X=m ++CONFIG_USB_SERIAL_SAFE=m ++CONFIG_USB_SERIAL_SIEMENS_MPI=m ++CONFIG_USB_SERIAL_SIERRAWIRELESS=m ++CONFIG_USB_SERIAL_SYMBOL=m ++CONFIG_USB_SERIAL_TI=m ++CONFIG_USB_SERIAL_CYBERJACK=m ++CONFIG_USB_SERIAL_XIRCOM=m ++CONFIG_USB_SERIAL_OPTION=m ++CONFIG_USB_SERIAL_OMNINET=m ++CONFIG_USB_SERIAL_OPTICON=m ++CONFIG_USB_SERIAL_VIVOPAY_SERIAL=m ++CONFIG_USB_SERIAL_ZIO=m ++CONFIG_USB_SERIAL_SSU100=m ++CONFIG_USB_SERIAL_DEBUG=m ++CONFIG_USB_EMI62=m ++CONFIG_USB_EMI26=m ++CONFIG_USB_ADUTUX=m ++CONFIG_USB_SEVSEG=m ++CONFIG_USB_RIO500=m ++CONFIG_USB_LEGOTOWER=m ++CONFIG_USB_LCD=m ++CONFIG_USB_LED=m ++CONFIG_USB_CYPRESS_CY7C63=m ++CONFIG_USB_CYTHERM=m ++CONFIG_USB_IDMOUSE=m ++CONFIG_USB_FTDI_ELAN=m ++CONFIG_USB_APPLEDISPLAY=m ++CONFIG_USB_LD=m ++CONFIG_USB_TRANCEVIBRATOR=m ++CONFIG_USB_IOWARRIOR=m ++CONFIG_USB_TEST=m ++CONFIG_USB_ISIGHTFW=m ++CONFIG_USB_YUREX=m ++CONFIG_MMC=y ++CONFIG_MMC_SDHCI=y ++CONFIG_MMC_SDHCI_PLTFM=y ++CONFIG_MMC_SDHCI_BCM2708=y ++CONFIG_MMC_SDHCI_BCM2708_DMA=y ++CONFIG_LEDS_GPIO=y ++CONFIG_LEDS_TRIGGER_TIMER=m ++CONFIG_LEDS_TRIGGER_HEARTBEAT=m ++CONFIG_LEDS_TRIGGER_DEFAULT_ON=m ++CONFIG_UIO=m ++CONFIG_UIO_PDRV=m ++CONFIG_UIO_PDRV_GENIRQ=m ++# CONFIG_IOMMU_SUPPORT is not set ++CONFIG_EXT4_FS=y ++CONFIG_EXT4_FS_POSIX_ACL=y ++CONFIG_EXT4_FS_SECURITY=y ++CONFIG_REISERFS_FS=m ++CONFIG_REISERFS_FS_XATTR=y ++CONFIG_REISERFS_FS_POSIX_ACL=y ++CONFIG_REISERFS_FS_SECURITY=y ++CONFIG_JFS_FS=m ++CONFIG_JFS_POSIX_ACL=y ++CONFIG_JFS_SECURITY=y ++CONFIG_XFS_FS=m ++CONFIG_XFS_QUOTA=y ++CONFIG_XFS_POSIX_ACL=y ++CONFIG_XFS_RT=y ++CONFIG_GFS2_FS=m ++CONFIG_OCFS2_FS=m ++CONFIG_BTRFS_FS=m ++CONFIG_BTRFS_FS_POSIX_ACL=y ++CONFIG_NILFS2_FS=m ++CONFIG_AUTOFS4_FS=y ++CONFIG_FUSE_FS=m ++CONFIG_CUSE=m ++CONFIG_FSCACHE=y ++CONFIG_CACHEFILES=y ++CONFIG_ISO9660_FS=m ++CONFIG_JOLIET=y ++CONFIG_ZISOFS=y ++CONFIG_UDF_FS=m ++CONFIG_MSDOS_FS=y ++CONFIG_VFAT_FS=y ++CONFIG_FAT_DEFAULT_IOCHARSET="ascii" ++CONFIG_NTFS_FS=m ++CONFIG_TMPFS=y ++CONFIG_TMPFS_POSIX_ACL=y ++CONFIG_CONFIGFS_FS=y ++CONFIG_SQUASHFS=m ++CONFIG_SQUASHFS_XATTR=y ++CONFIG_SQUASHFS_LZO=y ++CONFIG_SQUASHFS_XZ=y ++CONFIG_NFS_FS=y ++CONFIG_NFS_V3=y ++CONFIG_NFS_V3_ACL=y ++CONFIG_NFS_V4=y ++CONFIG_ROOT_NFS=y ++CONFIG_NFS_FSCACHE=y ++CONFIG_CIFS=m ++CONFIG_CIFS_WEAK_PW_HASH=y ++CONFIG_CIFS_XATTR=y ++CONFIG_CIFS_POSIX=y ++CONFIG_9P_FS=m ++CONFIG_PARTITION_ADVANCED=y ++CONFIG_MAC_PARTITION=y ++CONFIG_EFI_PARTITION=y ++CONFIG_NLS_DEFAULT="utf8" ++CONFIG_NLS_CODEPAGE_437=y ++CONFIG_NLS_CODEPAGE_737=m ++CONFIG_NLS_CODEPAGE_775=m ++CONFIG_NLS_CODEPAGE_850=m ++CONFIG_NLS_CODEPAGE_852=m ++CONFIG_NLS_CODEPAGE_855=m ++CONFIG_NLS_CODEPAGE_857=m ++CONFIG_NLS_CODEPAGE_860=m ++CONFIG_NLS_CODEPAGE_861=m ++CONFIG_NLS_CODEPAGE_862=m ++CONFIG_NLS_CODEPAGE_863=m ++CONFIG_NLS_CODEPAGE_864=m ++CONFIG_NLS_CODEPAGE_865=m ++CONFIG_NLS_CODEPAGE_866=m ++CONFIG_NLS_CODEPAGE_869=m ++CONFIG_NLS_CODEPAGE_936=m ++CONFIG_NLS_CODEPAGE_950=m ++CONFIG_NLS_CODEPAGE_932=m ++CONFIG_NLS_CODEPAGE_949=m ++CONFIG_NLS_CODEPAGE_874=m ++CONFIG_NLS_ISO8859_8=m ++CONFIG_NLS_CODEPAGE_1250=m ++CONFIG_NLS_CODEPAGE_1251=m ++CONFIG_NLS_ASCII=y ++CONFIG_NLS_ISO8859_1=m ++CONFIG_NLS_ISO8859_2=m ++CONFIG_NLS_ISO8859_3=m ++CONFIG_NLS_ISO8859_4=m ++CONFIG_NLS_ISO8859_5=m ++CONFIG_NLS_ISO8859_6=m ++CONFIG_NLS_ISO8859_7=m ++CONFIG_NLS_ISO8859_9=m ++CONFIG_NLS_ISO8859_13=m ++CONFIG_NLS_ISO8859_14=m ++CONFIG_NLS_ISO8859_15=m ++CONFIG_NLS_KOI8_R=m ++CONFIG_NLS_KOI8_U=m ++CONFIG_NLS_UTF8=m ++# CONFIG_SCHED_DEBUG is not set ++# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_FTRACE is not set ++# CONFIG_ARM_UNWIND is not set ++CONFIG_CRYPTO_AUTHENC=m ++CONFIG_CRYPTO_SEQIV=m ++CONFIG_CRYPTO_CBC=y ++CONFIG_CRYPTO_HMAC=y ++CONFIG_CRYPTO_XCBC=m ++CONFIG_CRYPTO_MD5=y ++CONFIG_CRYPTO_SHA1=y ++CONFIG_CRYPTO_SHA256=m ++CONFIG_CRYPTO_SHA512=m ++CONFIG_CRYPTO_TGR192=m ++CONFIG_CRYPTO_WP512=m ++CONFIG_CRYPTO_CAST5=m ++CONFIG_CRYPTO_DES=y ++CONFIG_CRYPTO_DEFLATE=m ++# CONFIG_CRYPTO_ANSI_CPRNG is not set ++# CONFIG_CRYPTO_HW is not set ++CONFIG_CRC_ITU_T=y ++CONFIG_LIBCRC32C=y diff -Nru linux-3.2.46/debian/patches/rpi/rpi_112_4b461106c4c4d61682a1cc0d7dd200623e5649ec.patch linux-3.2.46/debian/patches/rpi/rpi_112_4b461106c4c4d61682a1cc0d7dd200623e5649ec.patch --- linux-3.2.46/debian/patches/rpi/rpi_112_4b461106c4c4d61682a1cc0d7dd200623e5649ec.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_112_4b461106c4c4d61682a1cc0d7dd200623e5649ec.patch 2013-07-26 19:32:19.000000000 +0000 @@ -0,0 +1,128 @@ +commit 4b461106c4c4d61682a1cc0d7dd200623e5649ec +Author: Dom Cobley +Date: Wed Mar 7 23:21:01 2012 +0000 + + Fix 32bpp framebuffer by adding alpha bits + +Index: linux-3.2.46/drivers/video/bcm2708_fb.c +=================================================================== +--- linux-3.2.46.orig/drivers/video/bcm2708_fb.c 2013-07-26 19:32:11.000000000 +0000 ++++ linux-3.2.46/drivers/video/bcm2708_fb.c 2013-07-26 19:32:18.000000000 +0000 +@@ -96,6 +96,7 @@ + var->red.length = 8; + var->green.length = 8; + var->blue.length = 8; ++ var->transp.length = 8; + break; + default: + ret = -EINVAL; +@@ -111,6 +112,7 @@ + var->blue.offset = 0; + var->green.offset = var->blue.offset + var->blue.length; + var->red.offset = var->green.offset + var->green.length; ++ var->transp.offset = var->red.offset + var->red.length; + } + + return ret; +@@ -119,7 +121,6 @@ + static int bcm2708_fb_check_var(struct fb_var_screeninfo *var, + struct fb_info *info) + { +- + /* info input, var output */ + int yres; + /* memory size in pixels */ +@@ -137,13 +138,12 @@ + if (!var->bits_per_pixel) + var->bits_per_pixel = 16; + +- if (0 && var->bits_per_pixel != 16 && var->bits_per_pixel != 32) { +- pr_err("bcm2708_fb_check_var: ERROR: bits_per_pixel=%d\n", +- var->bits_per_pixel); ++ if (bcm2708_fb_set_bitfields(var) != 0) { ++ pr_err("bcm2708_fb_check_var: invalid bits_per_pixel %d\n", ++ var->bits_per_pixel); + return -EINVAL; + } + +- bcm2708_fb_set_bitfields(var); + + if (var->xres_virtual < var->xres) + var->xres_virtual = var->xres; +@@ -158,15 +158,6 @@ + if (var->yres_virtual < var->yres) + var->yres_virtual = var->yres; + +-#if 0 +- if (var->xres_virtual * var->yres_virtual > pixels) { +- pr_err("bcm2708_fb_check_var: mode %dx%dx%d rejected... " +- "virtual resolution too high to fit into video memory!\n", +- var->xres_virtual, var->yres_virtual, +- var->bits_per_pixel); +- return -EINVAL; +- } +-#endif + if (var->xoffset < 0) + var->xoffset = 0; + if (var->yoffset < 0) +@@ -178,11 +169,6 @@ + if (var->yoffset > var->yres_virtual - var->yres) + var->yoffset = var->yres_virtual - var->yres - 1; + +- var->red.msb_right = +- var->green.msb_right = +- var->blue.msb_right = +- var->transp.offset = var->transp.length = var->transp.msb_right = 0; +- + yres = var->yres; + if (var->vmode & FB_VMODE_DOUBLE) + yres *= 2; +@@ -230,28 +216,29 @@ + /* ensure GPU writes are visible to us */ + rmb(); + +- fb->fb.fix.line_length = fbinfo->pitch; +- +- if (info->var.bits_per_pixel <= 8) +- fb->fb.fix.visual = FB_VISUAL_PSEUDOCOLOR; +- else +- fb->fb.fix.visual = FB_VISUAL_TRUECOLOR; +- +- fb->fb.fix.smem_start = fbinfo->base; +- fb->fb.fix.smem_len = fbinfo->pitch * fbinfo->yres_virtual; +- fb->fb.screen_size = fbinfo->screen_size; +- if (fb->fb.screen_base) +- iounmap(fb->fb.screen_base); +- fb->fb.screen_base = +- (void *)ioremap_nocache(fb->fb.fix.smem_start, fb->fb.screen_size); +- if (!fb->fb.screen_base) +- BUG(); /* what can we do here */ ++ if (val == 0) { ++ fb->fb.fix.line_length = fbinfo->pitch; + ++ if (info->var.bits_per_pixel <= 8) ++ fb->fb.fix.visual = FB_VISUAL_PSEUDOCOLOR; ++ else ++ fb->fb.fix.visual = FB_VISUAL_TRUECOLOR; ++ ++ fb->fb.fix.smem_start = fbinfo->base; ++ fb->fb.fix.smem_len = fbinfo->pitch * fbinfo->yres_virtual; ++ fb->fb.screen_size = fbinfo->screen_size; ++ if (fb->fb.screen_base) ++ iounmap(fb->fb.screen_base); ++ fb->fb.screen_base = ++ (void *)ioremap_wc(fb->fb.fix.smem_start, fb->fb.screen_size); ++ if (!fb->fb.screen_base) ++ BUG(); /* what can we do here */ ++ } + pr_info +- ("BCM2708FB: start = %p,%p,%p width=%d, height=%d, bpp=%d, pitch=%d\n", ++ ("BCM2708FB: start = %p,%p width=%d, height=%d, bpp=%d, pitch=%d size=%d success=%d\n", + (void *)fb->fb.screen_base, (void *)fb->fb.fix.smem_start, +- (void *)val, fbinfo->xres, fbinfo->yres, fbinfo->bpp, +- fbinfo->pitch); ++ fbinfo->xres, fbinfo->yres, fbinfo->bpp, ++ fbinfo->pitch, fb->fb.screen_size, val); + + return val; + } diff -Nru linux-3.2.46/debian/patches/rpi/rpi_113_05dc3103a587232b58a0ba175a07a780ba8a3ac0.patch linux-3.2.46/debian/patches/rpi/rpi_113_05dc3103a587232b58a0ba175a07a780ba8a3ac0.patch --- linux-3.2.46/debian/patches/rpi/rpi_113_05dc3103a587232b58a0ba175a07a780ba8a3ac0.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_113_05dc3103a587232b58a0ba175a07a780ba8a3ac0.patch 2013-07-26 19:32:21.000000000 +0000 @@ -0,0 +1,43 @@ +commit 05dc3103a587232b58a0ba175a07a780ba8a3ac0 +Author: Dom Cobley +Date: Wed Mar 7 23:22:59 2012 +0000 + + Enable L2 cache is now the default. Invert sense of L2 flags + +Index: linux-3.2.46/arch/arm/mach-bcm2708/Kconfig +=================================================================== +--- linux-3.2.46.orig/arch/arm/mach-bcm2708/Kconfig 2013-07-26 19:32:14.000000000 +0000 ++++ linux-3.2.46/arch/arm/mach-bcm2708/Kconfig 2013-07-26 19:32:20.000000000 +0000 +@@ -22,11 +22,11 @@ + help + Helper for videocore memory access and total size allocation. + +-config BCM2708_L2CACHE +- bool "Videocore L2 cache" ++config BCM2708_NOL2CACHE ++ bool "Videocore L2 cache disable" + depends on MACH_BCM2708 + default n + help +- Allow ARM to use GPU's L2 cache. Requires enable_l2cache in config.txt. ++ Do not allow ARM to use GPU's L2 cache. Requires disable_l2cache in config.txt. + + endmenu +Index: linux-3.2.46/arch/arm/mach-bcm2708/include/mach/memory.h +=================================================================== +--- linux-3.2.46.orig/arch/arm/mach-bcm2708/include/mach/memory.h 2013-07-26 19:32:14.000000000 +0000 ++++ linux-3.2.46/arch/arm/mach-bcm2708/include/mach/memory.h 2013-07-26 19:32:20.000000000 +0000 +@@ -35,10 +35,10 @@ + #define PHYS_OFFSET UL(0x00000000) + #define ARMMEM_OFFSET UL(0x00000000) /* offset in VC of ARM memory */ + +-#ifdef CONFIG_BCM2708_L2CACHE +- #define _REAL_BUS_OFFSET UL(0x40000000) /* use L2 cache */ +-#else ++#ifdef CONFIG_BCM2708_NOL2CACHE + #define _REAL_BUS_OFFSET UL(0xC0000000) /* don't use L1 or L2 caches */ ++#else ++ #define _REAL_BUS_OFFSET UL(0x40000000) /* use L2 cache */ + #endif + + /* We're using the memory at 64M in the VideoCore for Linux - this adjustment diff -Nru linux-3.2.46/debian/patches/rpi/rpi_114_bcf011fb144a3a90ed0aacc9042e7c548cb5edca.patch linux-3.2.46/debian/patches/rpi/rpi_114_bcf011fb144a3a90ed0aacc9042e7c548cb5edca.patch --- linux-3.2.46/debian/patches/rpi/rpi_114_bcf011fb144a3a90ed0aacc9042e7c548cb5edca.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_114_bcf011fb144a3a90ed0aacc9042e7c548cb5edca.patch 2013-07-26 19:32:22.000000000 +0000 @@ -0,0 +1,22 @@ +commit bcf011fb144a3a90ed0aacc9042e7c548cb5edca +Author: popcornmix +Date: Wed Mar 14 23:26:14 2012 +0000 + + Allow 24bpp for framebuffer + +Index: linux-3.2.46/drivers/video/bcm2708_fb.c +=================================================================== +--- linux-3.2.46.orig/drivers/video/bcm2708_fb.c 2013-07-26 19:32:18.000000000 +0000 ++++ linux-3.2.46/drivers/video/bcm2708_fb.c 2013-07-26 19:32:21.000000000 +0000 +@@ -92,6 +92,11 @@ + if (var->green.length != 5 && var->green.length != 6) + var->green.length = 6; + break; ++ case 24: ++ var->red.length = 8; ++ var->blue.length = 8; ++ var->green.length = 8; ++ break; + case 32: + var->red.length = 8; + var->green.length = 8; diff -Nru linux-3.2.46/debian/patches/rpi/rpi_115_da305c719abe61fb7e7a1ac8a6a3ae1b8633bf89.patch linux-3.2.46/debian/patches/rpi/rpi_115_da305c719abe61fb7e7a1ac8a6a3ae1b8633bf89.patch --- linux-3.2.46/debian/patches/rpi/rpi_115_da305c719abe61fb7e7a1ac8a6a3ae1b8633bf89.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_115_da305c719abe61fb7e7a1ac8a6a3ae1b8633bf89.patch 2013-07-26 19:32:23.000000000 +0000 @@ -0,0 +1,47 @@ +commit da305c719abe61fb7e7a1ac8a6a3ae1b8633bf89 +Author: popcornmix +Date: Sat Mar 17 23:05:37 2012 +0000 + + Disable debug code in dwc_otg driver unless CONFIG_USB_DEBUG is set + +Index: linux-3.2.46/drivers/usb/host/dwc_common_port/Makefile +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_common_port/Makefile 2013-07-26 19:31:19.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_common_port/Makefile 2013-07-26 19:32:22.000000000 +0000 +@@ -6,7 +6,9 @@ + + #CPPFLAGS += -DDEBUG_MEMORY + ++ifeq ($(CONFIG_USB_DEBUG),y) + CPPFLAGS += -DDEBUG ++endif + CPPFLAGS += -DDWC_LINUX + + obj-$(CONFIG_USB_DWCOTG) += dwc_common_port_lib.o +Index: linux-3.2.46/drivers/usb/host/dwc_common_port/dwc_os.h +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_common_port/dwc_os.h 2013-07-26 19:31:20.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_common_port/dwc_os.h 2013-07-26 19:32:22.000000000 +0000 +@@ -216,6 +216,7 @@ + #endif + #else + #define __DWC_DEBUG printk ++#include + #endif + + /** +Index: linux-3.2.46/drivers/usb/host/dwc_otg/Makefile +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/Makefile 2013-07-26 19:31:20.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/Makefile 2013-07-26 19:32:22.000000000 +0000 +@@ -9,7 +9,9 @@ + BUS_INTERFACE = -DPLATFORM_INTERFACE=1 + endif + +-CPPFLAGS += -DDEBUG ++ifeq ($(CONFIG_USB_DEBUG),y) ++CPPFLAGS += -DDEBUG ++endif + + # Use one of the following flags to compile the software in host-only or + # device-only mode. diff -Nru linux-3.2.46/debian/patches/rpi/rpi_116_c6b198bad4cbd38214a7604fbf71f7b915e30b8d.patch linux-3.2.46/debian/patches/rpi/rpi_116_c6b198bad4cbd38214a7604fbf71f7b915e30b8d.patch --- linux-3.2.46/debian/patches/rpi/rpi_116_c6b198bad4cbd38214a7604fbf71f7b915e30b8d.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_116_c6b198bad4cbd38214a7604fbf71f7b915e30b8d.patch 2013-07-26 19:32:25.000000000 +0000 @@ -0,0 +1,132 @@ +commit c6b198bad4cbd38214a7604fbf71f7b915e30b8d +Author: popcornmix +Date: Sat Mar 17 23:23:01 2012 +0000 + + Enable high resolution timers + +Index: linux-3.2.46/arch/arm/configs/bcmrpi_cutdown_defconfig +=================================================================== +--- linux-3.2.46.orig/arch/arm/configs/bcmrpi_cutdown_defconfig 2013-07-26 19:32:17.000000000 +0000 ++++ linux-3.2.46/arch/arm/configs/bcmrpi_cutdown_defconfig 2013-07-26 19:32:24.000000000 +0000 +@@ -17,6 +17,7 @@ + # CONFIG_BLK_DEV_BSG is not set + CONFIG_ARCH_BCM2708=y + CONFIG_NO_HZ=y ++CONFIG_HIGH_RES_TIMERS=y + CONFIG_AEABI=y + CONFIG_ZBOOT_ROM_TEXT=0x0 + CONFIG_ZBOOT_ROM_BSS=0x0 +Index: linux-3.2.46/arch/arm/configs/bcmrpi_defconfig +=================================================================== +--- linux-3.2.46.orig/arch/arm/configs/bcmrpi_defconfig 2013-07-26 19:32:17.000000000 +0000 ++++ linux-3.2.46/arch/arm/configs/bcmrpi_defconfig 2013-07-26 19:32:24.000000000 +0000 +@@ -30,6 +30,7 @@ + CONFIG_CFQ_GROUP_IOSCHED=y + CONFIG_ARCH_BCM2708=y + CONFIG_NO_HZ=y ++CONFIG_HIGH_RES_TIMERS=y + CONFIG_AEABI=y + CONFIG_SECCOMP=y + CONFIG_CC_STACKPROTECTOR=y +Index: linux-3.2.46/arch/arm/mach-bcm2708/bcm2708.c +=================================================================== +--- linux-3.2.46.orig/arch/arm/mach-bcm2708/bcm2708.c 2013-07-26 19:32:11.000000000 +0000 ++++ linux-3.2.46/arch/arm/mach-bcm2708/bcm2708.c 2013-07-26 19:32:24.000000000 +0000 +@@ -155,25 +155,44 @@ + iotable_init(bcm2708_io_desc, ARRAY_SIZE(bcm2708_io_desc)); + } + +-unsigned long frc_clock_ticks32(void) ++// The STC is a free running counter that increments at the rate of 1MHz ++#define STC_FREQ_HZ 1000000 ++ ++static cycle_t stc_read_cycles(struct clocksource *cs) + { + /* STC: a free running counter that increments at the rate of 1MHz */ +- return readl(__io_address(ST_BASE + 0x04)); ++ return (cycle_t)readl(__io_address(ST_BASE+0x04)); + } + +-unsigned long long frc_clock_ticks63(void) ++static struct clocksource clocksource_stc = { ++ .name = "stc", ++ .rating = 300, ++ .read = stc_read_cycles, ++ .mask = CLOCKSOURCE_MASK(32), ++ .flags = CLOCK_SOURCE_IS_CONTINUOUS, ++}; ++ ++unsigned long frc_clock_ticks32(void) + { +- unsigned long t = frc_clock_ticks32(); +- /* For cnt32_to_63 to work correctly we MUST call this routine +- * at least once every half-32-bit-wraparound period - that's once +- * every 35minutes or so - using it in sched_clock() should ensure this +- */ +- return cnt32_to_63(t); ++ return (unsigned long)stc_read_cycles(&clocksource_stc); ++} ++ ++static void __init bcm2708_clocksource_init(void) ++{ ++ // calculate .shift and .mult values and register clocksource ++ if (clocksource_register_hz(&clocksource_stc, STC_FREQ_HZ)) ++ { ++ printk(KERN_ERR "timer: failed to initialize clock " ++ "source %s\n", clocksource_stc.name); ++ } + } + + unsigned long long sched_clock(void) + { +- return 1000ull * frc_clock_ticks63(); ++ return clocksource_cyc2ns(clocksource_stc.read( ++ &clocksource_stc), ++ clocksource_stc.mult, ++ clocksource_stc.shift); + } + + /* +@@ -484,6 +503,7 @@ + bcm_register_device(&bcm2708_emmc_device); + #endif + bcm2708_init_led(); ++ + #ifdef CONFIG_BCM2708_VCMEM + { + extern void vc_mem_connected_init(void); +@@ -521,13 +541,13 @@ + + } + +-static int timer_set_next_event(unsigned long evt, ++static int timer_set_next_event(unsigned long cycles, + struct clock_event_device *unused) + { + unsigned long stc; + + stc = readl(__io_address(ST_BASE + 0x04)); +- writel(stc + TIMER_PERIOD, __io_address(ST_BASE + 0x18)); /* stc3 */ ++ writel(stc + cycles, __io_address(ST_BASE + 0x18)); /* stc3 */ + return 0; + } + +@@ -564,6 +584,9 @@ + */ + static void __init bcm2708_timer_init(void) + { ++ /* init high res timer */ ++ bcm2708_clocksource_init(); ++ + /* + * Initialise to a known state (all timers off) + */ +@@ -574,7 +597,7 @@ + setup_irq(IRQ_TIMER3, &bcm2708_timer_irq); + + timer0_clockevent.mult = +- div_sc(1000000, NSEC_PER_SEC, timer0_clockevent.shift); ++ div_sc(STC_FREQ_HZ, NSEC_PER_SEC, timer0_clockevent.shift); + timer0_clockevent.max_delta_ns = + clockevent_delta2ns(0xffffffff, &timer0_clockevent); + timer0_clockevent.min_delta_ns = diff -Nru linux-3.2.46/debian/patches/rpi/rpi_117_59615740bc33035372330bad54fa4b88e4e94ef7.patch linux-3.2.46/debian/patches/rpi/rpi_117_59615740bc33035372330bad54fa4b88e4e94ef7.patch --- linux-3.2.46/debian/patches/rpi/rpi_117_59615740bc33035372330bad54fa4b88e4e94ef7.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_117_59615740bc33035372330bad54fa4b88e4e94ef7.patch 2013-07-26 19:32:26.000000000 +0000 @@ -0,0 +1,223 @@ +commit 59615740bc33035372330bad54fa4b88e4e94ef7 +Author: popcornmix +Date: Sat Mar 17 23:28:22 2012 +0000 + + Fix for mmc timeouts when erasing multiple blocks + +Index: linux-3.2.46/arch/arm/mach-bcm2708/power.c +=================================================================== +--- linux-3.2.46.orig/arch/arm/mach-bcm2708/power.c 2013-07-26 19:31:51.000000000 +0000 ++++ linux-3.2.46/arch/arm/mach-bcm2708/power.c 2013-07-26 19:32:25.000000000 +0000 +@@ -14,6 +14,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -97,6 +98,7 @@ + global_request << 4); + + /* Wait for a response during power-up */ ++ mdelay(10); + if (global_request & ~g_state.global_request) { + rc = bcm_mailbox_read(MBOX_CHAN_POWER, + &actual); +@@ -111,14 +113,14 @@ + + if (rc == 0) { + if (actual != global_request) { +- printk(KERN_ERR +- "%s: prev global %x, new global %x, actual %x, request %x, others_request %x\n", ++ printk(KERN_INFO ++ "%s: Fail: prev global %x, new global %x, actual %x request %x, others_request %x\n", + __func__, + g_state.global_request, + global_request, actual, request, others_request); + /* A failure */ +- BUG_ON((others_request & actual) +- != others_request); ++ // BUG_ON((others_request & actual) ++ // != others_request); + request &= actual; + rc = -EIO; + } +Index: linux-3.2.46/drivers/mmc/host/sdhci-bcm2708.c +=================================================================== +--- linux-3.2.46.orig/drivers/mmc/host/sdhci-bcm2708.c 2013-07-26 19:31:51.000000000 +0000 ++++ linux-3.2.46/drivers/mmc/host/sdhci-bcm2708.c 2013-07-26 19:32:25.000000000 +0000 +@@ -26,7 +26,9 @@ + #include + #include + #include ++#include + #include ++#include + + #include + #include +@@ -68,6 +70,9 @@ + + #define BCM2708_SDHCI_SLEEP_TIMEOUT 1000 /* msecs */ + ++/* Mhz clock that the EMMC core is running at. Should match the platform clockman settings */ ++#define BCM2708_EMMC_CLOCK_FREQ 80000000 ++ + #define POWER_OFF 0 + #define POWER_LAZY_OFF 1 + #define POWER_ON 2 +@@ -222,6 +227,10 @@ + + static void sdhci_bcm2708_raw_writel(struct sdhci_host *host, u32 val, int reg) + { ++ u32 ier; ++ static bool timeout_disabled = false; ++ unsigned int ns_2clk = 0; ++ + /* The Arasan has a bugette whereby it may lose the content of + * successive writes to registers that are within two SD-card clock + * cycles of each other (a clock domain crossing problem). +@@ -234,7 +243,7 @@ + /* host->clock is the clock freq in Hz */ + static hptime_t last_write_hpt; + hptime_t now = hptime(); +- unsigned int ns_2clk = 2000000000/host->clock; ++ ns_2clk = 2000000000/host->clock; + + if (now == last_write_hpt || now == last_write_hpt+1) { + /* we can't guarantee any significant time has +@@ -250,6 +259,24 @@ + } + last_write_hpt = now; + } ++#if 1 ++ /* The Arasan is clocked for timeouts using the SD clock which is too fast ++ * for ERASE commands and causes issues. So we disable timeouts for ERASE */ ++ if (host->cmd != NULL && host->cmd->opcode == MMC_ERASE && reg == (SDHCI_COMMAND & ~3)) { ++ mod_timer(&host->timer, jiffies + 30 * HZ); ++ ier = readl(host->ioaddr + SDHCI_SIGNAL_ENABLE); ++ ier &= ~SDHCI_INT_DATA_TIMEOUT; ++ writel(ier, host->ioaddr + SDHCI_SIGNAL_ENABLE); ++ timeout_disabled = true; ++ udelay((ns_2clk+1000-1)/1000); ++ } else if (timeout_disabled) { ++ ier = readl(host->ioaddr + SDHCI_SIGNAL_ENABLE); ++ ier |= SDHCI_INT_DATA_TIMEOUT; ++ writel(ier, host->ioaddr + SDHCI_SIGNAL_ENABLE); ++ timeout_disabled = false; ++ udelay((ns_2clk+1000-1)/1000); ++ } ++#endif + writel(val, host->ioaddr + reg); + #else + void __iomem * regaddr = host->ioaddr + reg; +@@ -325,14 +352,68 @@ + + static unsigned int sdhci_bcm2708_get_max_clock(struct sdhci_host *host) + { +- return 100000000; // this value is in Hz (100MHz/4) ++ return 20000000; // this value is in Hz (20MHz) + } + + static unsigned int sdhci_bcm2708_get_timeout_clock(struct sdhci_host *host) + { +- return 100000; // this value is in kHz (100MHz/4) ++ if(host->clock) ++ return (host->clock / 1000); // this value is in kHz (100MHz) ++ else ++ return (sdhci_bcm2708_get_max_clock(host) / 1000); + } + ++static void sdhci_bcm2708_set_clock(struct sdhci_host *host, unsigned int clock) ++{ ++ int div = 0; ++ u16 clk = 0; ++ unsigned long timeout; ++ ++ if (clock == host->clock) ++ return; ++ ++ sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); ++ ++ if (clock == 0) ++ goto out; ++ ++ if (BCM2708_EMMC_CLOCK_FREQ <= clock) ++ div = 1; ++ else { ++ for (div = 2; div < SDHCI_MAX_DIV_SPEC_300; div += 2) { ++ if ((BCM2708_EMMC_CLOCK_FREQ / div) <= clock) ++ break; ++ } ++ } ++ ++ DBG( "desired SD clock: %d, actual: %d\n", ++ clock, BCM2708_EMMC_CLOCK_FREQ / div); ++ ++ clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT; ++ clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN) ++ << SDHCI_DIVIDER_HI_SHIFT; ++ clk |= SDHCI_CLOCK_INT_EN; ++ ++ sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); ++ ++ timeout = 20; ++ while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL)) ++ & SDHCI_CLOCK_INT_STABLE)) { ++ if (timeout == 0) { ++ printk(KERN_ERR "%s: Internal clock never " ++ "stabilised.\n", mmc_hostname(host->mmc)); ++ return; ++ } ++ timeout--; ++ mdelay(1); ++ } ++ ++ clk |= SDHCI_CLOCK_CARD_EN; ++ sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); ++out: ++ host->clock = clock; ++ } ++ + /*****************************************************************************\ + * * + * DMA Operation * +@@ -821,7 +902,7 @@ + continue; + + if (1000000-timeout > 4000) /*ave. is about 3250*/ +- printk(KERN_INFO "%s: note - long %s sync %luns - " ++ DBG("%s: note - long %s sync %luns - " + "%d its.\n", + mmc_hostname(host->mmc), + data->flags & MMC_DATA_READ? "read": "write", +@@ -1219,7 +1300,7 @@ + #error The BCM2708 SDHCI driver needs CONFIG_MMC_SDHCI_IO_ACCESSORS to be set + #endif + //.enable_dma = NULL, +- //.set_clock = NULL, ++ .set_clock = sdhci_bcm2708_set_clock, + .get_max_clock = sdhci_bcm2708_get_max_clock, + //.get_min_clock = NULL, + .get_timeout_clock = sdhci_bcm2708_get_timeout_clock, +@@ -1282,7 +1363,9 @@ + host->irq = platform_get_irq(pdev, 0); + + host->quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION | +- SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK; ++ SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | ++ SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | ++ SDHCI_QUIRK_NONSTANDARD_CLOCK; + #ifdef CONFIG_MMC_SDHCI_BCM2708_DMA + host->flags = SDHCI_USE_PLATDMA; + #endif +@@ -1349,6 +1432,8 @@ + host_priv->cb_base, (unsigned)host_priv->cb_handle, + host_priv->dma_chan, host_priv->dma_chan_base, + host_priv->dma_irq); ++ ++ host->mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED; + #endif + + ret = sdhci_add_host(host); diff -Nru linux-3.2.46/debian/patches/rpi/rpi_118_8a93b2aa9309fe8495c17cc549c71827d6bd3dc3.patch linux-3.2.46/debian/patches/rpi/rpi_118_8a93b2aa9309fe8495c17cc549c71827d6bd3dc3.patch --- linux-3.2.46/debian/patches/rpi/rpi_118_8a93b2aa9309fe8495c17cc549c71827d6bd3dc3.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_118_8a93b2aa9309fe8495c17cc549c71827d6bd3dc3.patch 2013-07-26 19:32:28.000000000 +0000 @@ -0,0 +1,30 @@ +commit 8a93b2aa9309fe8495c17cc549c71827d6bd3dc3 +Author: Dom Cobley +Date: Tue Mar 20 15:04:40 2012 +0000 + + Fix problem with dma that could corrupt sdcard, especially when L2 enabled + +Index: linux-3.2.46/drivers/mmc/host/sdhci-bcm2708.c +=================================================================== +--- linux-3.2.46.orig/drivers/mmc/host/sdhci-bcm2708.c 2013-07-26 19:32:25.000000000 +0000 ++++ linux-3.2.46/drivers/mmc/host/sdhci-bcm2708.c 2013-07-26 19:32:27.000000000 +0000 +@@ -510,7 +510,8 @@ + cb->stride = 0; + + if (is_last) { +- cb->info |= BCM2708_DMA_INT_EN; ++ cb->info |= BCM2708_DMA_INT_EN | ++ BCM2708_DMA_WAIT_RESP; + cb->next = 0; + } else + cb->next = host->cb_handle + +@@ -541,7 +542,8 @@ + cb->stride = 0; + + if (is_last) { +- cb->info |= BCM2708_DMA_INT_EN; ++ cb->info |= BCM2708_DMA_INT_EN | ++ BCM2708_DMA_WAIT_RESP; + cb->next = 0; + } else + cb->next = host->cb_handle + diff -Nru linux-3.2.46/debian/patches/rpi/rpi_119_f7f1991dc6b5db3310d6fb2e310e69fad769b492.patch linux-3.2.46/debian/patches/rpi/rpi_119_f7f1991dc6b5db3310d6fb2e310e69fad769b492.patch --- linux-3.2.46/debian/patches/rpi/rpi_119_f7f1991dc6b5db3310d6fb2e310e69fad769b492.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_119_f7f1991dc6b5db3310d6fb2e310e69fad769b492.patch 2013-07-26 19:32:30.000000000 +0000 @@ -0,0 +1,3201 @@ +commit f7f1991dc6b5db3310d6fb2e310e69fad769b492 +Author: popcornmix +Date: Mon Mar 26 22:10:01 2012 +0100 + + Update to match latest vc side vchiq. Allows vchiq calls from kernel. + +Index: linux-3.2.46/drivers/misc/vc04_services/Makefile +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/Makefile 2013-07-26 19:32:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/Makefile 2013-07-26 19:32:28.000000000 +0000 +@@ -2,6 +2,8 @@ + + vchiq-objs := \ + interface/vchiq_arm/vchiq_core.o \ ++ interface/vchiq_arm/vchiq_shim.o \ ++ interface/vchiq_arm/vchiq_util.o \ + interface/vchiq_arm/vchiq_arm.o \ + interface/vchiq_arm/vchiq_kern_lib.o \ + interface/vchiq_arm/vchiq_2835_arm.o \ +@@ -13,7 +15,7 @@ + interface/vcos/generic/vcos_mem_from_malloc.o \ + interface/vcos/generic/vcos_cmd.o + +-EXTRA_CFLAGS += -DVCOS_VERIFY_BKPTS=1 -Idrivers/misc/vc04_services -Idrivers/misc/vc04_services/interface/vcos/linuxkernel ++EXTRA_CFLAGS += -DVCOS_VERIFY_BKPTS=1 -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -Idrivers/misc/vc04_services -Idrivers/misc/vc04_services/interface/vcos/linuxkernel + + + +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vchi/connections/connection.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vchi/connections/connection.h 2013-07-26 19:32:28.000000000 +0000 +@@ -0,0 +1,309 @@ ++/* ++ * Copyright (c) 2010-2011 Broadcom Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++#ifndef CONNECTION_H_ ++#define CONNECTION_H_ ++ ++#include "interface/vchi/vchi_cfg_internal.h" ++#include "interface/vchi/vchi_common.h" ++#include "interface/vchi/message_drivers/message.h" ++ ++/****************************************************************************** ++ Global defs ++ *****************************************************************************/ ++ ++// Opaque handle for a connection / service pair ++typedef struct opaque_vchi_connection_connected_service_handle_t *VCHI_CONNECTION_SERVICE_HANDLE_T; ++ ++// opaque handle to the connection state information ++typedef struct opaque_vchi_connection_info_t VCHI_CONNECTION_STATE_T; ++ ++typedef struct vchi_connection_t VCHI_CONNECTION_T; ++ ++ ++/****************************************************************************** ++ API ++ *****************************************************************************/ ++ ++// Routine to init a connection with a particular low level driver ++typedef VCHI_CONNECTION_STATE_T * (*VCHI_CONNECTION_INIT_T)( struct vchi_connection_t * connection, ++ const VCHI_MESSAGE_DRIVER_T * driver ); ++ ++// Routine to control CRC enabling at a connection level ++typedef int32_t (*VCHI_CONNECTION_CRC_CONTROL_T)( VCHI_CONNECTION_STATE_T *state_handle, ++ VCHI_CRC_CONTROL_T control ); ++ ++// Routine to create a service ++typedef int32_t (*VCHI_CONNECTION_SERVICE_CONNECT_T)( VCHI_CONNECTION_STATE_T *state_handle, ++ vcos_fourcc_t service_id, ++ uint32_t rx_fifo_size, ++ uint32_t tx_fifo_size, ++ int server, ++ VCHI_CALLBACK_T callback, ++ void *callback_param, ++ vcos_bool_t want_crc, ++ vcos_bool_t want_unaligned_bulk_rx, ++ vcos_bool_t want_unaligned_bulk_tx, ++ VCHI_CONNECTION_SERVICE_HANDLE_T *service_handle ); ++ ++// Routine to close a service ++typedef int32_t (*VCHI_CONNECTION_SERVICE_DISCONNECT_T)( VCHI_CONNECTION_SERVICE_HANDLE_T service_handle ); ++ ++// Routine to queue a message ++typedef int32_t (*VCHI_CONNECTION_SERVICE_QUEUE_MESSAGE_T)( VCHI_CONNECTION_SERVICE_HANDLE_T service_handle, ++ const void *data, ++ uint32_t data_size, ++ VCHI_FLAGS_T flags, ++ void *msg_handle ); ++ ++// scatter-gather (vector) message queueing ++typedef int32_t (*VCHI_CONNECTION_SERVICE_QUEUE_MESSAGEV_T)( VCHI_CONNECTION_SERVICE_HANDLE_T service_handle, ++ VCHI_MSG_VECTOR_T *vector, ++ uint32_t count, ++ VCHI_FLAGS_T flags, ++ void *msg_handle ); ++ ++// Routine to dequeue a message ++typedef int32_t (*VCHI_CONNECTION_SERVICE_DEQUEUE_MESSAGE_T)( VCHI_CONNECTION_SERVICE_HANDLE_T service_handle, ++ void *data, ++ uint32_t max_data_size_to_read, ++ uint32_t *actual_msg_size, ++ VCHI_FLAGS_T flags ); ++ ++// Routine to peek at a message ++typedef int32_t (*VCHI_CONNECTION_SERVICE_PEEK_MESSAGE_T)( VCHI_CONNECTION_SERVICE_HANDLE_T service_handle, ++ void **data, ++ uint32_t *msg_size, ++ VCHI_FLAGS_T flags ); ++ ++// Routine to hold a message ++typedef int32_t (*VCHI_CONNECTION_SERVICE_HOLD_MESSAGE_T)( VCHI_CONNECTION_SERVICE_HANDLE_T service_handle, ++ void **data, ++ uint32_t *msg_size, ++ VCHI_FLAGS_T flags, ++ void **message_handle ); ++ ++// Routine to initialise a received message iterator ++typedef int32_t (*VCHI_CONNECTION_SERVICE_LOOKAHEAD_MESSAGE_T)( VCHI_CONNECTION_SERVICE_HANDLE_T service_handle, ++ VCHI_MSG_ITER_T *iter, ++ VCHI_FLAGS_T flags ); ++ ++// Routine to release a held message ++typedef int32_t (*VCHI_CONNECTION_HELD_MSG_RELEASE_T)( VCHI_CONNECTION_SERVICE_HANDLE_T service_handle, ++ void *message_handle ); ++ ++// Routine to get info on a held message ++typedef int32_t (*VCHI_CONNECTION_HELD_MSG_INFO_T)( VCHI_CONNECTION_SERVICE_HANDLE_T service_handle, ++ void *message_handle, ++ void **data, ++ int32_t *msg_size, ++ uint32_t *tx_timestamp, ++ uint32_t *rx_timestamp ); ++ ++// Routine to check whether the iterator has a next message ++typedef vcos_bool_t (*VCHI_CONNECTION_MSG_ITER_HAS_NEXT_T)( VCHI_CONNECTION_SERVICE_HANDLE_T service, ++ const VCHI_MSG_ITER_T *iter ); ++ ++// Routine to advance the iterator ++typedef int32_t (*VCHI_CONNECTION_MSG_ITER_NEXT_T)( VCHI_CONNECTION_SERVICE_HANDLE_T service, ++ VCHI_MSG_ITER_T *iter, ++ void **data, ++ uint32_t *msg_size ); ++ ++// Routine to remove the last message returned by the iterator ++typedef int32_t (*VCHI_CONNECTION_MSG_ITER_REMOVE_T)( VCHI_CONNECTION_SERVICE_HANDLE_T service, ++ VCHI_MSG_ITER_T *iter ); ++ ++// Routine to hold the last message returned by the iterator ++typedef int32_t (*VCHI_CONNECTION_MSG_ITER_HOLD_T)( VCHI_CONNECTION_SERVICE_HANDLE_T service, ++ VCHI_MSG_ITER_T *iter, ++ void **msg_handle ); ++ ++// Routine to transmit bulk data ++typedef int32_t (*VCHI_CONNECTION_BULK_QUEUE_TRANSMIT_T)( VCHI_CONNECTION_SERVICE_HANDLE_T service_handle, ++ const void *data_src, ++ uint32_t data_size, ++ VCHI_FLAGS_T flags, ++ void *bulk_handle ); ++ ++// Routine to receive data ++typedef int32_t (*VCHI_CONNECTION_BULK_QUEUE_RECEIVE_T)( VCHI_CONNECTION_SERVICE_HANDLE_T service_handle, ++ void *data_dst, ++ uint32_t data_size, ++ VCHI_FLAGS_T flags, ++ void *bulk_handle ); ++ ++// Routine to report if a server is available ++typedef int32_t (*VCHI_CONNECTION_SERVER_PRESENT)( VCHI_CONNECTION_STATE_T *state, vcos_fourcc_t service_id, int32_t peer_flags ); ++ ++// Routine to report the number of RX slots available ++typedef int (*VCHI_CONNECTION_RX_SLOTS_AVAILABLE)( const VCHI_CONNECTION_STATE_T *state ); ++ ++// Routine to report the RX slot size ++typedef uint32_t (*VCHI_CONNECTION_RX_SLOT_SIZE)( const VCHI_CONNECTION_STATE_T *state ); ++ ++// Callback to indicate that the other side has added a buffer to the rx bulk DMA FIFO ++typedef void (*VCHI_CONNECTION_RX_BULK_BUFFER_ADDED)(VCHI_CONNECTION_STATE_T *state, ++ vcos_fourcc_t service, ++ uint32_t length, ++ MESSAGE_TX_CHANNEL_T channel, ++ uint32_t channel_params, ++ uint32_t data_length, ++ uint32_t data_offset); ++ ++// Callback to inform a service that a Xon or Xoff message has been received ++typedef void (*VCHI_CONNECTION_FLOW_CONTROL)(VCHI_CONNECTION_STATE_T *state, vcos_fourcc_t service_id, int32_t xoff); ++ ++// Callback to inform a service that a server available reply message has been received ++typedef void (*VCHI_CONNECTION_SERVER_AVAILABLE_REPLY)(VCHI_CONNECTION_STATE_T *state, vcos_fourcc_t service_id, uint32_t flags); ++ ++// Callback to indicate that bulk auxiliary messages have arrived ++typedef void (*VCHI_CONNECTION_BULK_AUX_RECEIVED)(VCHI_CONNECTION_STATE_T *state); ++ ++// Callback to indicate that bulk auxiliary messages have arrived ++typedef void (*VCHI_CONNECTION_BULK_AUX_TRANSMITTED)(VCHI_CONNECTION_STATE_T *state, void *handle); ++ ++// Callback with all the connection info you require ++typedef void (*VCHI_CONNECTION_INFO)(VCHI_CONNECTION_STATE_T *state, uint32_t protocol_version, uint32_t slot_size, uint32_t num_slots, uint32_t min_bulk_size); ++ ++// Callback to inform of a disconnect ++typedef void (*VCHI_CONNECTION_DISCONNECT)(VCHI_CONNECTION_STATE_T *state, uint32_t flags); ++ ++// Callback to inform of a power control request ++typedef void (*VCHI_CONNECTION_POWER_CONTROL)(VCHI_CONNECTION_STATE_T *state, MESSAGE_TX_CHANNEL_T channel, vcos_bool_t enable); ++ ++// allocate memory suitably aligned for this connection ++typedef void * (*VCHI_BUFFER_ALLOCATE)(VCHI_CONNECTION_SERVICE_HANDLE_T service_handle, uint32_t * length); ++ ++// free memory allocated by buffer_allocate ++typedef void (*VCHI_BUFFER_FREE)(VCHI_CONNECTION_SERVICE_HANDLE_T service_handle, void * address); ++ ++ ++/****************************************************************************** ++ System driver struct ++ *****************************************************************************/ ++ ++struct opaque_vchi_connection_api_t ++{ ++ // Routine to init the connection ++ VCHI_CONNECTION_INIT_T init; ++ ++ // Connection-level CRC control ++ VCHI_CONNECTION_CRC_CONTROL_T crc_control; ++ ++ // Routine to connect to or create service ++ VCHI_CONNECTION_SERVICE_CONNECT_T service_connect; ++ ++ // Routine to disconnect from a service ++ VCHI_CONNECTION_SERVICE_DISCONNECT_T service_disconnect; ++ ++ // Routine to queue a message ++ VCHI_CONNECTION_SERVICE_QUEUE_MESSAGE_T service_queue_msg; ++ ++ // scatter-gather (vector) message queue ++ VCHI_CONNECTION_SERVICE_QUEUE_MESSAGEV_T service_queue_msgv; ++ ++ // Routine to dequeue a message ++ VCHI_CONNECTION_SERVICE_DEQUEUE_MESSAGE_T service_dequeue_msg; ++ ++ // Routine to peek at a message ++ VCHI_CONNECTION_SERVICE_PEEK_MESSAGE_T service_peek_msg; ++ ++ // Routine to hold a message ++ VCHI_CONNECTION_SERVICE_HOLD_MESSAGE_T service_hold_msg; ++ ++ // Routine to initialise a received message iterator ++ VCHI_CONNECTION_SERVICE_LOOKAHEAD_MESSAGE_T service_look_ahead_msg; ++ ++ // Routine to release a message ++ VCHI_CONNECTION_HELD_MSG_RELEASE_T held_msg_release; ++ ++ // Routine to get information on a held message ++ VCHI_CONNECTION_HELD_MSG_INFO_T held_msg_info; ++ ++ // Routine to check for next message on iterator ++ VCHI_CONNECTION_MSG_ITER_HAS_NEXT_T msg_iter_has_next; ++ ++ // Routine to get next message on iterator ++ VCHI_CONNECTION_MSG_ITER_NEXT_T msg_iter_next; ++ ++ // Routine to remove the last message returned by iterator ++ VCHI_CONNECTION_MSG_ITER_REMOVE_T msg_iter_remove; ++ ++ // Routine to hold the last message returned by iterator ++ VCHI_CONNECTION_MSG_ITER_HOLD_T msg_iter_hold; ++ ++ // Routine to transmit bulk data ++ VCHI_CONNECTION_BULK_QUEUE_TRANSMIT_T bulk_queue_transmit; ++ ++ // Routine to receive data ++ VCHI_CONNECTION_BULK_QUEUE_RECEIVE_T bulk_queue_receive; ++ ++ // Routine to report the available servers ++ VCHI_CONNECTION_SERVER_PRESENT server_present; ++ ++ // Routine to report the number of RX slots available ++ VCHI_CONNECTION_RX_SLOTS_AVAILABLE connection_rx_slots_available; ++ ++ // Routine to report the RX slot size ++ VCHI_CONNECTION_RX_SLOT_SIZE connection_rx_slot_size; ++ ++ // Callback to indicate that the other side has added a buffer to the rx bulk DMA FIFO ++ VCHI_CONNECTION_RX_BULK_BUFFER_ADDED rx_bulk_buffer_added; ++ ++ // Callback to inform a service that a Xon or Xoff message has been received ++ VCHI_CONNECTION_FLOW_CONTROL flow_control; ++ ++ // Callback to inform a service that a server available reply message has been received ++ VCHI_CONNECTION_SERVER_AVAILABLE_REPLY server_available_reply; ++ ++ // Callback to indicate that bulk auxiliary messages have arrived ++ VCHI_CONNECTION_BULK_AUX_RECEIVED bulk_aux_received; ++ ++ // Callback to indicate that a bulk auxiliary message has been transmitted ++ VCHI_CONNECTION_BULK_AUX_TRANSMITTED bulk_aux_transmitted; ++ ++ // Callback to provide information about the connection ++ VCHI_CONNECTION_INFO connection_info; ++ ++ // Callback to notify that peer has requested disconnect ++ VCHI_CONNECTION_DISCONNECT disconnect; ++ ++ // Callback to notify that peer has requested power change ++ VCHI_CONNECTION_POWER_CONTROL power_control; ++ ++ // allocate memory suitably aligned for this connection ++ VCHI_BUFFER_ALLOCATE buffer_allocate; ++ ++ // free memory allocated by buffer_allocate ++ VCHI_BUFFER_FREE buffer_free; ++ ++}; ++ ++struct vchi_connection_t { ++ const VCHI_CONNECTION_API_T *api; ++ VCHI_CONNECTION_STATE_T *state; ++#ifdef VCHI_COARSE_LOCKING ++ VCOS_SEMAPHORE_T sem; ++#endif ++}; ++ ++ ++#endif /* CONNECTION_H_ */ ++ ++/****************************** End of file **********************************/ +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vchi/message_drivers/message.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vchi/message_drivers/message.h 2013-07-26 19:32:28.000000000 +0000 +@@ -0,0 +1,186 @@ ++/* ++ * Copyright (c) 2010-2011 Broadcom Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++#ifndef _VCHI_MESSAGE_H_ ++#define _VCHI_MESSAGE_H_ ++ ++#include "interface/vchi/vchi_cfg_internal.h" ++#include "interface/vcos/vcos.h" ++#include "interface/vchi/vchi_common.h" ++ ++ ++typedef enum message_event_type { ++ MESSAGE_EVENT_NONE, ++ MESSAGE_EVENT_NOP, ++ MESSAGE_EVENT_MESSAGE, ++ MESSAGE_EVENT_SLOT_COMPLETE, ++ MESSAGE_EVENT_RX_BULK_PAUSED, ++ MESSAGE_EVENT_RX_BULK_COMPLETE, ++ MESSAGE_EVENT_TX_COMPLETE, ++ MESSAGE_EVENT_MSG_DISCARDED ++} MESSAGE_EVENT_TYPE_T; ++ ++typedef enum vchi_msg_flags ++{ ++ VCHI_MSG_FLAGS_NONE = 0x0, ++ VCHI_MSG_FLAGS_TERMINATE_DMA = 0x1 ++} VCHI_MSG_FLAGS_T; ++ ++typedef enum message_tx_channel ++{ ++ MESSAGE_TX_CHANNEL_MESSAGE = 0, ++ MESSAGE_TX_CHANNEL_BULK = 1 // drivers may provide multiple bulk channels, from 1 upwards ++} MESSAGE_TX_CHANNEL_T; ++ ++// Macros used for cycling through bulk channels ++#define MESSAGE_TX_CHANNEL_BULK_PREV(c) (MESSAGE_TX_CHANNEL_BULK+((c)-MESSAGE_TX_CHANNEL_BULK+VCHI_MAX_BULK_TX_CHANNELS_PER_CONNECTION-1)%VCHI_MAX_BULK_TX_CHANNELS_PER_CONNECTION) ++#define MESSAGE_TX_CHANNEL_BULK_NEXT(c) (MESSAGE_TX_CHANNEL_BULK+((c)-MESSAGE_TX_CHANNEL_BULK+1)%VCHI_MAX_BULK_TX_CHANNELS_PER_CONNECTION) ++ ++typedef enum message_rx_channel ++{ ++ MESSAGE_RX_CHANNEL_MESSAGE = 0, ++ MESSAGE_RX_CHANNEL_BULK = 1 // drivers may provide multiple bulk channels, from 1 upwards ++} MESSAGE_RX_CHANNEL_T; ++ ++// Message receive slot information ++typedef struct rx_msg_slot_info { ++ ++ struct rx_msg_slot_info *next; ++ //struct slot_info *prev; ++#if !defined VCHI_COARSE_LOCKING ++ VCOS_SEMAPHORE_T sem; ++#endif ++ ++ uint8_t *addr; // base address of slot ++ uint32_t len; // length of slot in bytes ++ ++ uint32_t write_ptr; // hardware causes this to advance ++ uint32_t read_ptr; // this module does the reading ++ int active; // is this slot in the hardware dma fifo? ++ uint32_t msgs_parsed; // count how many messages are in this slot ++ uint32_t msgs_released; // how many messages have been released ++ void *state; // connection state information ++ uint8_t ref_count[VCHI_MAX_SERVICES_PER_CONNECTION]; // reference count for slots held by services ++} RX_MSG_SLOTINFO_T; ++ ++// The message driver no longer needs to know about the fields of RX_BULK_SLOTINFO_T - sort this out. ++// In particular, it mustn't use addr and len - they're the client buffer, but the message ++// driver will be tasked with sending the aligned core section. ++typedef struct rx_bulk_slotinfo_t { ++ struct rx_bulk_slotinfo_t *next; ++ ++ VCOS_SEMAPHORE_T *blocking; ++ ++ // needed by DMA ++ void *addr; ++ uint32_t len; ++ ++ // needed for the callback ++ void *service; ++ void *handle; ++ VCHI_FLAGS_T flags; ++} RX_BULK_SLOTINFO_T; ++ ++ ++/* ---------------------------------------------------------------------- ++ * each connection driver will have a pool of the following struct. ++ * ++ * the pool will be managed by vchi_qman_* ++ * this means there will be multiple queues (single linked lists) ++ * a given struct message_info will be on exactly one of these queues ++ * at any one time ++ * -------------------------------------------------------------------- */ ++typedef struct rx_message_info { ++ ++ struct message_info *next; ++ //struct message_info *prev; ++ ++ uint8_t *addr; ++ uint32_t len; ++ RX_MSG_SLOTINFO_T *slot; // points to whichever slot contains this message ++ uint32_t tx_timestamp; ++ uint32_t rx_timestamp; ++ ++} RX_MESSAGE_INFO_T; ++ ++typedef struct { ++ MESSAGE_EVENT_TYPE_T type; ++ ++ struct { ++ // for messages ++ void *addr; // address of message ++ uint16_t slot_delta; // whether this message indicated slot delta ++ uint32_t len; // length of message ++ RX_MSG_SLOTINFO_T *slot; // slot this message is in ++ vcos_fourcc_t service; // service id this message is destined for ++ uint32_t tx_timestamp; // timestamp from the header ++ uint32_t rx_timestamp; // timestamp when we parsed it ++ } message; ++ ++ // FIXME: cleanup slot reporting... ++ RX_MSG_SLOTINFO_T *rx_msg; ++ RX_BULK_SLOTINFO_T *rx_bulk; ++ void *tx_handle; ++ MESSAGE_TX_CHANNEL_T tx_channel; ++ ++} MESSAGE_EVENT_T; ++ ++ ++// callbacks ++typedef void VCHI_MESSAGE_DRIVER_EVENT_CALLBACK_T( void *state ); ++ ++typedef struct { ++ VCHI_MESSAGE_DRIVER_EVENT_CALLBACK_T *event_callback; ++} VCHI_MESSAGE_DRIVER_OPEN_T; ++ ++ ++// handle to this instance of message driver (as returned by ->open) ++typedef struct opaque_mhandle_t *VCHI_MDRIVER_HANDLE_T; ++ ++struct opaque_vchi_message_driver_t { ++ VCHI_MDRIVER_HANDLE_T *(*open)( VCHI_MESSAGE_DRIVER_OPEN_T *params, void *state ); ++ int32_t (*suspending)( VCHI_MDRIVER_HANDLE_T *handle ); ++ int32_t (*resumed)( VCHI_MDRIVER_HANDLE_T *handle ); ++ int32_t (*power_control)( VCHI_MDRIVER_HANDLE_T *handle, MESSAGE_TX_CHANNEL_T, vcos_bool_t enable ); ++ int32_t (*add_msg_rx_slot)( VCHI_MDRIVER_HANDLE_T *handle, RX_MSG_SLOTINFO_T *slot ); // rx message ++ int32_t (*add_bulk_rx)( VCHI_MDRIVER_HANDLE_T *handle, void *data, uint32_t len, RX_BULK_SLOTINFO_T *slot ); // rx data (bulk) ++ int32_t (*send)( VCHI_MDRIVER_HANDLE_T *handle, MESSAGE_TX_CHANNEL_T channel, const void *data, uint32_t len, VCHI_MSG_FLAGS_T flags, void *send_handle ); // tx (message & bulk) ++ void (*next_event)( VCHI_MDRIVER_HANDLE_T *handle, MESSAGE_EVENT_T *event ); // get the next event from message_driver ++ int32_t (*enable)( VCHI_MDRIVER_HANDLE_T *handle ); ++ int32_t (*form_message)( VCHI_MDRIVER_HANDLE_T *handle, vcos_fourcc_t service_id, VCHI_MSG_VECTOR_T *vector, uint32_t count, void ++ *address, uint32_t length_avail, uint32_t max_total_length, vcos_bool_t pad_to_fill, vcos_bool_t allow_partial ); ++ ++ int32_t (*update_message)( VCHI_MDRIVER_HANDLE_T *handle, void *dest, int16_t *slot_count ); ++ int32_t (*buffer_aligned)( VCHI_MDRIVER_HANDLE_T *handle, int tx, int uncached, const void *address, const uint32_t length ); ++ void * (*allocate_buffer)( VCHI_MDRIVER_HANDLE_T *handle, uint32_t *length ); ++ void (*free_buffer)( VCHI_MDRIVER_HANDLE_T *handle, void *address ); ++ int (*rx_slot_size)( VCHI_MDRIVER_HANDLE_T *handle, int msg_size ); ++ int (*tx_slot_size)( VCHI_MDRIVER_HANDLE_T *handle, int msg_size ); ++ ++ vcos_bool_t (*tx_supports_terminate)( const VCHI_MDRIVER_HANDLE_T *handle, MESSAGE_TX_CHANNEL_T channel ); ++ uint32_t (*tx_bulk_chunk_size)( const VCHI_MDRIVER_HANDLE_T *handle, MESSAGE_TX_CHANNEL_T channel ); ++ int (*tx_alignment)( const VCHI_MDRIVER_HANDLE_T *handle, MESSAGE_TX_CHANNEL_T channel ); ++ int (*rx_alignment)( const VCHI_MDRIVER_HANDLE_T *handle, MESSAGE_RX_CHANNEL_T channel ); ++ void (*form_bulk_aux)( VCHI_MDRIVER_HANDLE_T *handle, MESSAGE_TX_CHANNEL_T channel, const void *data, uint32_t len, uint32_t chunk_size, const void **aux_data, int32_t *aux_len ); ++ void (*debug)( VCHI_MDRIVER_HANDLE_T *handle ); ++}; ++ ++ ++#endif // _VCHI_MESSAGE_H_ ++ ++/****************************** End of file ***********************************/ +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vchi/vchi.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vchi/vchi.h 2013-07-26 19:32:28.000000000 +0000 +@@ -0,0 +1,347 @@ ++/* ++ * Copyright (c) 2010-2011 Broadcom Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++/*============================================================================= ++Contains the protypes for the vchi functions. ++=============================================================================*/ ++ ++#ifndef VCHI_H_ ++#define VCHI_H_ ++ ++#include "interface/vcos/vcos.h" ++#include "interface/vchi/vchi_cfg.h" ++#include "interface/vchi/vchi_common.h" ++#include "interface/vchi/connections/connection.h" ++#include "vchi_mh.h" ++ ++ ++/****************************************************************************** ++ Global defs ++ *****************************************************************************/ ++ ++#define VCHI_BULK_ROUND_UP(x) ((((unsigned long)(x))+VCHI_BULK_ALIGN-1) & ~(VCHI_BULK_ALIGN-1)) ++#define VCHI_BULK_ROUND_DOWN(x) (((unsigned long)(x)) & ~(VCHI_BULK_ALIGN-1)) ++#define VCHI_BULK_ALIGN_NBYTES(x) (VCHI_BULK_ALIGNED(x) ? 0 : (VCHI_BULK_ALIGN - ((unsigned long)(x) & (VCHI_BULK_ALIGN-1)))) ++ ++#ifdef USE_VCHIQ_ARM ++#define VCHI_BULK_ALIGNED(x) 1 ++#else ++#define VCHI_BULK_ALIGNED(x) (((unsigned long)(x) & (VCHI_BULK_ALIGN-1)) == 0) ++#endif ++ ++ ++typedef enum ++{ ++ VCHI_VEC_POINTER, ++ VCHI_VEC_HANDLE, ++ VCHI_VEC_LIST ++} VCHI_MSG_VECTOR_TYPE_T; ++ ++typedef struct vchi_msg_vector_ex { ++ ++ VCHI_MSG_VECTOR_TYPE_T type; ++ union ++ { ++ // a memory handle ++ struct ++ { ++ VCHI_MEM_HANDLE_T handle; ++ uint32_t offset; ++ int32_t vec_len; ++ } handle; ++ ++ // an ordinary data pointer ++ struct ++ { ++ const void *vec_base; ++ int32_t vec_len; ++ } ptr; ++ ++ // a nested vector list ++ struct ++ { ++ struct vchi_msg_vector_ex *vec; ++ uint32_t vec_len; ++ } list; ++ } u; ++} VCHI_MSG_VECTOR_EX_T; ++ ++ ++// Construct an entry in a msg vector for a pointer (p) of length (l) ++#define VCHI_VEC_POINTER(p,l) VCHI_VEC_POINTER, { { (VCHI_MEM_HANDLE_T)(p), (l) } } ++ ++// Construct an entry in a msg vector for a message handle (h), starting at offset (o) of length (l) ++#define VCHI_VEC_HANDLE(h,o,l) VCHI_VEC_HANDLE, { { (h), (o), (l) } } ++ ++// Macros to manipulate fourcc_t values ++#define MAKE_FOURCC(x) ((fourcc_t)( (x[0] << 24) | (x[1] << 16) | (x[2] << 8) | x[3] )) ++#define FOURCC_TO_CHAR(x) (x >> 24) & 0xFF,(x >> 16) & 0xFF,(x >> 8) & 0xFF, x & 0xFF ++ ++ ++// Opaque service information ++struct opaque_vchi_service_t; ++ ++// Descriptor for a held message. Allocated by client, initialised by vchi_msg_hold, ++// vchi_msg_iter_hold or vchi_msg_iter_hold_next. Fields are for internal VCHI use only. ++typedef struct ++{ ++ struct opaque_vchi_service_t *service; ++ void *message; ++} VCHI_HELD_MSG_T; ++ ++ ++ ++// structure used to provide the information needed to open a server or a client ++typedef struct { ++ vcos_fourcc_t service_id; ++ VCHI_CONNECTION_T *connection; ++ uint32_t rx_fifo_size; ++ uint32_t tx_fifo_size; ++ VCHI_CALLBACK_T callback; ++ void *callback_param; ++ vcos_bool_t want_unaligned_bulk_rx; // client intends to receive bulk transfers of odd lengths or into unaligned buffers ++ vcos_bool_t want_unaligned_bulk_tx; // client intends to transmit bulk transfers of odd lengths or out of unaligned buffers ++ vcos_bool_t want_crc; // client wants to check CRCs on (bulk) transfers. Only needs to be set at 1 end - will do both directions. ++} SERVICE_CREATION_T; ++ ++// Opaque handle for a VCHI instance ++typedef struct opaque_vchi_instance_handle_t *VCHI_INSTANCE_T; ++ ++// Opaque handle for a server or client ++typedef struct opaque_vchi_service_handle_t *VCHI_SERVICE_HANDLE_T; ++ ++// Service registration & startup ++typedef void (*VCHI_SERVICE_INIT)(VCHI_INSTANCE_T initialise_instance, VCHI_CONNECTION_T **connections, uint32_t num_connections); ++ ++typedef struct service_info_tag { ++ const char * const vll_filename; /* VLL to load to start this service. This is an empty string if VLL is "static" */ ++ VCHI_SERVICE_INIT init; /* Service initialisation function */ ++ void *vll_handle; /* VLL handle; NULL when unloaded or a "static VLL" in build */ ++} SERVICE_INFO_T; ++ ++/****************************************************************************** ++ Global funcs - implementation is specific to which side you are on (local / remote) ++ *****************************************************************************/ ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++extern /*@observer@*/ VCHI_CONNECTION_T * vchi_create_connection( const VCHI_CONNECTION_API_T * function_table, ++ const VCHI_MESSAGE_DRIVER_T * low_level); ++ ++ ++// Routine used to initialise the vchi on both local + remote connections ++extern int32_t vchi_initialise( VCHI_INSTANCE_T *instance_handle ); ++ ++extern int32_t vchi_exit( void ); ++ ++extern int32_t vchi_connect( VCHI_CONNECTION_T **connections, ++ const uint32_t num_connections, ++ VCHI_INSTANCE_T instance_handle ); ++ ++//When this is called, ensure that all services have no data pending. ++//Bulk transfers can remain 'queued' ++extern int32_t vchi_disconnect( VCHI_INSTANCE_T instance_handle ); ++ ++// Global control over bulk CRC checking ++extern int32_t vchi_crc_control( VCHI_CONNECTION_T *connection, ++ VCHI_CRC_CONTROL_T control ); ++ ++// helper functions ++extern void * vchi_allocate_buffer(VCHI_SERVICE_HANDLE_T handle, uint32_t *length); ++extern void vchi_free_buffer(VCHI_SERVICE_HANDLE_T handle, void *address); ++extern uint32_t vchi_current_time(VCHI_INSTANCE_T instance_handle); ++ ++ ++/****************************************************************************** ++ Global service API ++ *****************************************************************************/ ++// Routine to create a named service ++extern int32_t vchi_service_create( VCHI_INSTANCE_T instance_handle, ++ SERVICE_CREATION_T *setup, ++ VCHI_SERVICE_HANDLE_T *handle ); ++ ++// Routine to destory a service ++extern int32_t vchi_service_destroy( const VCHI_SERVICE_HANDLE_T handle ); ++ ++// Routine to open a named service ++extern int32_t vchi_service_open( VCHI_INSTANCE_T instance_handle, ++ SERVICE_CREATION_T *setup, ++ VCHI_SERVICE_HANDLE_T *handle); ++ ++// Routine to close a named service ++extern int32_t vchi_service_close( const VCHI_SERVICE_HANDLE_T handle ); ++ ++// Routine to increment ref count on a named service ++extern int32_t vchi_service_use( const VCHI_SERVICE_HANDLE_T handle ); ++ ++// Routine to decrement ref count on a named service ++extern int32_t vchi_service_release( const VCHI_SERVICE_HANDLE_T handle ); ++ ++// Routine to send a message accross a service ++extern int32_t vchi_msg_queue( VCHI_SERVICE_HANDLE_T handle, ++ const void *data, ++ uint32_t data_size, ++ VCHI_FLAGS_T flags, ++ void *msg_handle ); ++ ++// scatter-gather (vector) and send message ++int32_t vchi_msg_queuev_ex( VCHI_SERVICE_HANDLE_T handle, ++ VCHI_MSG_VECTOR_EX_T *vector, ++ uint32_t count, ++ VCHI_FLAGS_T flags, ++ void *msg_handle ); ++ ++// legacy scatter-gather (vector) and send message, only handles pointers ++int32_t vchi_msg_queuev( VCHI_SERVICE_HANDLE_T handle, ++ VCHI_MSG_VECTOR_T *vector, ++ uint32_t count, ++ VCHI_FLAGS_T flags, ++ void *msg_handle ); ++ ++// Routine to receive a msg from a service ++// Dequeue is equivalent to hold, copy into client buffer, release ++extern int32_t vchi_msg_dequeue( VCHI_SERVICE_HANDLE_T handle, ++ void *data, ++ uint32_t max_data_size_to_read, ++ uint32_t *actual_msg_size, ++ VCHI_FLAGS_T flags ); ++ ++// Routine to look at a message in place. ++// The message is not dequeued, so a subsequent call to peek or dequeue ++// will return the same message. ++extern int32_t vchi_msg_peek( VCHI_SERVICE_HANDLE_T handle, ++ void **data, ++ uint32_t *msg_size, ++ VCHI_FLAGS_T flags ); ++ ++// Routine to remove a message after it has been read in place with peek ++// The first message on the queue is dequeued. ++extern int32_t vchi_msg_remove( VCHI_SERVICE_HANDLE_T handle ); ++ ++// Routine to look at a message in place. ++// The message is dequeued, so the caller is left holding it; the descriptor is ++// filled in and must be released when the user has finished with the message. ++extern int32_t vchi_msg_hold( VCHI_SERVICE_HANDLE_T handle, ++ void **data, // } may be NULL, as info can be ++ uint32_t *msg_size, // } obtained from HELD_MSG_T ++ VCHI_FLAGS_T flags, ++ VCHI_HELD_MSG_T *message_descriptor ); ++ ++// Initialise an iterator to look through messages in place ++extern int32_t vchi_msg_look_ahead( VCHI_SERVICE_HANDLE_T handle, ++ VCHI_MSG_ITER_T *iter, ++ VCHI_FLAGS_T flags ); ++ ++/****************************************************************************** ++ Global service support API - operations on held messages and message iterators ++ *****************************************************************************/ ++ ++// Routine to get the address of a held message ++extern void *vchi_held_msg_ptr( const VCHI_HELD_MSG_T *message ); ++ ++// Routine to get the size of a held message ++extern int32_t vchi_held_msg_size( const VCHI_HELD_MSG_T *message ); ++ ++// Routine to get the transmit timestamp as written into the header by the peer ++extern uint32_t vchi_held_msg_tx_timestamp( const VCHI_HELD_MSG_T *message ); ++ ++// Routine to get the reception timestamp, written as we parsed the header ++extern uint32_t vchi_held_msg_rx_timestamp( const VCHI_HELD_MSG_T *message ); ++ ++// Routine to release a held message after it has been processed ++extern int32_t vchi_held_msg_release( VCHI_HELD_MSG_T *message ); ++ ++// Indicates whether the iterator has a next message. ++extern vcos_bool_t vchi_msg_iter_has_next( const VCHI_MSG_ITER_T *iter ); ++ ++// Return the pointer and length for the next message and advance the iterator. ++extern int32_t vchi_msg_iter_next( VCHI_MSG_ITER_T *iter, ++ void **data, ++ uint32_t *msg_size ); ++ ++// Remove the last message returned by vchi_msg_iter_next. ++// Can only be called once after each call to vchi_msg_iter_next. ++extern int32_t vchi_msg_iter_remove( VCHI_MSG_ITER_T *iter ); ++ ++// Hold the last message returned by vchi_msg_iter_next. ++// Can only be called once after each call to vchi_msg_iter_next. ++extern int32_t vchi_msg_iter_hold( VCHI_MSG_ITER_T *iter, ++ VCHI_HELD_MSG_T *message ); ++ ++// Return information for the next message, and hold it, advancing the iterator. ++extern int32_t vchi_msg_iter_hold_next( VCHI_MSG_ITER_T *iter, ++ void **data, // } may be NULL ++ uint32_t *msg_size, // } ++ VCHI_HELD_MSG_T *message ); ++ ++ ++/****************************************************************************** ++ Global bulk API ++ *****************************************************************************/ ++ ++// Routine to prepare interface for a transfer from the other side ++extern int32_t vchi_bulk_queue_receive( VCHI_SERVICE_HANDLE_T handle, ++ void *data_dst, ++ uint32_t data_size, ++ VCHI_FLAGS_T flags, ++ void *transfer_handle ); ++ ++ ++// Prepare interface for a transfer from the other side into relocatable memory. ++int32_t vchi_bulk_queue_receive_reloc( const VCHI_SERVICE_HANDLE_T handle, ++ VCHI_MEM_HANDLE_T h_dst, ++ uint32_t offset, ++ uint32_t data_size, ++ const VCHI_FLAGS_T flags, ++ void * const bulk_handle ); ++ ++// Routine to queue up data ready for transfer to the other (once they have signalled they are ready) ++extern int32_t vchi_bulk_queue_transmit( VCHI_SERVICE_HANDLE_T handle, ++ const void *data_src, ++ uint32_t data_size, ++ VCHI_FLAGS_T flags, ++ void *transfer_handle ); ++ ++ ++/****************************************************************************** ++ Configuration plumbing ++ *****************************************************************************/ ++ ++// function prototypes for the different mid layers (the state info gives the different physical connections) ++extern const VCHI_CONNECTION_API_T *single_get_func_table( void ); ++//extern const VCHI_CONNECTION_API_T *local_server_get_func_table( void ); ++//extern const VCHI_CONNECTION_API_T *local_client_get_func_table( void ); ++ ++// declare all message drivers here ++const VCHI_MESSAGE_DRIVER_T *vchi_mphi_message_driver_func_table( void ); ++ ++#ifdef __cplusplus ++} ++#endif ++ ++extern int32_t vchi_bulk_queue_transmit_reloc( VCHI_SERVICE_HANDLE_T handle, ++ VCHI_MEM_HANDLE_T h_src, ++ uint32_t offset, ++ uint32_t data_size, ++ VCHI_FLAGS_T flags, ++ void *transfer_handle ); ++#endif /* VCHI_H_ */ ++ ++/****************************** End of file **********************************/ +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vchi/vchi_cfg.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vchi/vchi_cfg.h 2013-07-26 19:32:28.000000000 +0000 +@@ -0,0 +1,214 @@ ++/* ++ * Copyright (c) 2010-2011 Broadcom Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++/*============================================================================= ++Contains the #defines for the number of servers / clients etc, these can be ++over-ridden from the platform makefile if needed ++=============================================================================*/ ++ ++#ifndef VCHI_CFG_H_ ++#define VCHI_CFG_H_ ++ ++/**************************************************************************************** ++ * Defines in this first section are part of the VCHI API and may be examined by VCHI ++ * services. ++ ***************************************************************************************/ ++ ++/* Required alignment of base addresses for bulk transfer, if unaligned transfers are not enabled */ ++/* Really determined by the message driver, and should be available from a run-time call. */ ++#ifndef VCHI_BULK_ALIGN ++# if __VCCOREVER__ >= 0x04000000 ++# define VCHI_BULK_ALIGN 32 // Allows for the need to do cache cleans ++# else ++# define VCHI_BULK_ALIGN 16 ++# endif ++#endif ++ ++/* Required length multiple for bulk transfers, if unaligned transfers are not enabled */ ++/* May be less than or greater than VCHI_BULK_ALIGN */ ++/* Really determined by the message driver, and should be available from a run-time call. */ ++#ifndef VCHI_BULK_GRANULARITY ++# if __VCCOREVER__ >= 0x04000000 ++# define VCHI_BULK_GRANULARITY 32 // Allows for the need to do cache cleans ++# else ++# define VCHI_BULK_GRANULARITY 16 ++# endif ++#endif ++ ++/* The largest possible message to be queued with vchi_msg_queue. */ ++#ifndef VCHI_MAX_MSG_SIZE ++# if defined VCHI_LOCAL_HOST_PORT ++# define VCHI_MAX_MSG_SIZE 16384 // makes file transfers fast, but should they be using bulk? ++# else ++# define VCHI_MAX_MSG_SIZE 4096 // NOTE: THIS MUST BE LARGER THAN OR EQUAL TO THE SIZE OF THE KHRONOS MERGE BUFFER!! ++# endif ++#endif ++ ++/****************************************************************************************** ++ * Defines below are system configuration options, and should not be used by VCHI services. ++ *****************************************************************************************/ ++ ++/* How many connections can we support? A localhost implementation uses 2 connections, ++ * 1 for host-app, 1 for VMCS, and these are hooked together by a loopback MPHI VCFW ++ * driver. */ ++#ifndef VCHI_MAX_NUM_CONNECTIONS ++# define VCHI_MAX_NUM_CONNECTIONS 3 ++#endif ++ ++/* How many services can we open per connection? Extending this doesn't cost processing time, just a small ++ * amount of static memory. */ ++#ifndef VCHI_MAX_SERVICES_PER_CONNECTION ++# define VCHI_MAX_SERVICES_PER_CONNECTION 36 ++#endif ++ ++/* Adjust if using a message driver that supports more logical TX channels */ ++#ifndef VCHI_MAX_BULK_TX_CHANNELS_PER_CONNECTION ++# define VCHI_MAX_BULK_TX_CHANNELS_PER_CONNECTION 9 // 1 MPHI + 8 CCP2 logical channels ++#endif ++ ++/* Adjust if using a message driver that supports more logical RX channels */ ++#ifndef VCHI_MAX_BULK_RX_CHANNELS_PER_CONNECTION ++# define VCHI_MAX_BULK_RX_CHANNELS_PER_CONNECTION 1 // 1 MPHI ++#endif ++ ++/* How many receive slots do we use. This times VCHI_MAX_MSG_SIZE gives the effective ++ * receive queue space, less message headers. */ ++#ifndef VCHI_NUM_READ_SLOTS ++# if defined(VCHI_LOCAL_HOST_PORT) ++# define VCHI_NUM_READ_SLOTS 4 ++# else ++# define VCHI_NUM_READ_SLOTS 48 ++# endif ++#endif ++ ++/* Do we utilise overrun facility for receive message slots? Can aid peer transmit ++ * performance. Only define on VideoCore end, talking to host. ++ */ ++//#define VCHI_MSG_RX_OVERRUN ++ ++/* How many transmit slots do we use. Generally don't need many, as the hardware driver ++ * underneath VCHI will usually have its own buffering. */ ++#ifndef VCHI_NUM_WRITE_SLOTS ++# define VCHI_NUM_WRITE_SLOTS 4 ++#endif ++ ++/* If a service has held or queued received messages in VCHI_XOFF_THRESHOLD or more slots, ++ * then it's taking up too much buffer space, and the peer service will be told to stop ++ * transmitting with an XOFF message. For this to be effective, the VCHI_NUM_READ_SLOTS ++ * needs to be considerably bigger than VCHI_NUM_WRITE_SLOTS, or the transmit latency ++ * is too high. */ ++#ifndef VCHI_XOFF_THRESHOLD ++# define VCHI_XOFF_THRESHOLD (VCHI_NUM_READ_SLOTS / 2) ++#endif ++ ++/* After we've sent an XOFF, the peer will be told to resume transmission once the local ++ * service has dequeued/released enough messages that it's now occupying ++ * VCHI_XON_THRESHOLD slots or fewer. */ ++#ifndef VCHI_XON_THRESHOLD ++# define VCHI_XON_THRESHOLD (VCHI_NUM_READ_SLOTS / 4) ++#endif ++ ++/* A size below which a bulk transfer omits the handshake completely and always goes ++ * via the message channel, if bulk auxiliary is being sent on that service. (The user ++ * can guarantee this by enabling unaligned transmits). ++ * Not API. */ ++#ifndef VCHI_MIN_BULK_SIZE ++# define VCHI_MIN_BULK_SIZE ( VCHI_MAX_MSG_SIZE / 2 < 4096 ? VCHI_MAX_MSG_SIZE / 2 : 4096 ) ++#endif ++ ++/* Maximum size of bulk transmission chunks, for each interface type. A trade-off between ++ * speed and latency; the smaller the chunk size the better change of messages and other ++ * bulk transmissions getting in when big bulk transfers are happening. Set to 0 to not ++ * break transmissions into chunks. ++ */ ++#ifndef VCHI_MAX_BULK_CHUNK_SIZE_MPHI ++# define VCHI_MAX_BULK_CHUNK_SIZE_MPHI (16 * 1024) ++#endif ++ ++/* NB Chunked CCP2 transmissions violate the letter of the CCP2 spec by using "JPEG8" mode ++ * with multiple-line frames. Only use if the receiver can cope. */ ++#ifndef VCHI_MAX_BULK_CHUNK_SIZE_CCP2 ++# define VCHI_MAX_BULK_CHUNK_SIZE_CCP2 0 ++#endif ++ ++/* How many TX messages can we have pending in our transmit slots. Once exhausted, ++ * vchi_msg_queue will be blocked. */ ++#ifndef VCHI_TX_MSG_QUEUE_SIZE ++# define VCHI_TX_MSG_QUEUE_SIZE 256 ++#endif ++ ++/* How many RX messages can we have parsed in the receive slots. Once exhausted, parsing ++ * will be suspended until older messages are dequeued/released. */ ++#ifndef VCHI_RX_MSG_QUEUE_SIZE ++# define VCHI_RX_MSG_QUEUE_SIZE 256 ++#endif ++ ++/* Really should be able to cope if we run out of received message descriptors, by ++ * suspending parsing as the comment above says, but we don't. This sweeps the issue ++ * under the carpet. */ ++#if VCHI_RX_MSG_QUEUE_SIZE < (VCHI_MAX_MSG_SIZE/16 + 1) * VCHI_NUM_READ_SLOTS ++# undef VCHI_RX_MSG_QUEUE_SIZE ++# define VCHI_RX_MSG_QUEUE_SIZE (VCHI_MAX_MSG_SIZE/16 + 1) * VCHI_NUM_READ_SLOTS ++#endif ++ ++/* How many bulk transmits can we have pending. Once exhausted, vchi_bulk_queue_transmit ++ * will be blocked. */ ++#ifndef VCHI_TX_BULK_QUEUE_SIZE ++# define VCHI_TX_BULK_QUEUE_SIZE 64 ++#endif ++ ++/* How many bulk receives can we have pending. Once exhausted, vchi_bulk_queue_receive ++ * will be blocked. */ ++#ifndef VCHI_RX_BULK_QUEUE_SIZE ++# define VCHI_RX_BULK_QUEUE_SIZE 64 ++#endif ++ ++/* A limit on how many outstanding bulk requests we expect the peer to give us. If ++ * the peer asks for more than this, VCHI will fail and assert. The number is determined ++ * by the peer's hardware - it's the number of outstanding requests that can be queued ++ * on all bulk channels. VC3's MPHI peripheral allows 16. */ ++#ifndef VCHI_MAX_PEER_BULK_REQUESTS ++# define VCHI_MAX_PEER_BULK_REQUESTS 32 ++#endif ++ ++/* Define VCHI_CCP2TX_MANUAL_POWER if the host tells us when to turn the CCP2 ++ * transmitter on and off. ++ */ ++/*#define VCHI_CCP2TX_MANUAL_POWER*/ ++ ++#ifndef VCHI_CCP2TX_MANUAL_POWER ++ ++/* Timeout (in milliseconds) for putting the CCP2TX interface into IDLE state. Set ++ * negative for no IDLE. ++ */ ++# ifndef VCHI_CCP2TX_IDLE_TIMEOUT ++# define VCHI_CCP2TX_IDLE_TIMEOUT 5 ++# endif ++ ++/* Timeout (in milliseconds) for putting the CCP2TX interface into OFF state. Set ++ * negative for no OFF. ++ */ ++# ifndef VCHI_CCP2TX_OFF_TIMEOUT ++# define VCHI_CCP2TX_OFF_TIMEOUT 1000 ++# endif ++ ++#endif /* VCHI_CCP2TX_MANUAL_POWER */ ++ ++#endif /* VCHI_CFG_H_ */ ++ ++/****************************** End of file **********************************/ +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vchi/vchi_cfg_internal.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vchi/vchi_cfg_internal.h 2013-07-26 19:32:28.000000000 +0000 +@@ -0,0 +1,56 @@ ++/* ++ * Copyright (c) 2010-2011 Broadcom Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++#ifndef VCHI_CFG_INTERNAL_H_ ++#define VCHI_CFG_INTERNAL_H_ ++ ++/**************************************************************************************** ++ * Control optimisation attempts. ++ ***************************************************************************************/ ++ ++// Don't use lots of short-term locks - use great long ones, reducing the overall locks-per-second ++#define VCHI_COARSE_LOCKING ++ ++// Avoid lock then unlock on exit from blocking queue operations (msg tx, bulk rx/tx) ++// (only relevant if VCHI_COARSE_LOCKING) ++#define VCHI_ELIDE_BLOCK_EXIT_LOCK ++ ++// Avoid lock on non-blocking peek ++// (only relevant if VCHI_COARSE_LOCKING) ++#define VCHI_AVOID_PEEK_LOCK ++ ++// Use one slot-handler thread per connection, rather than 1 thread dealing with all connections in rotation. ++#define VCHI_MULTIPLE_HANDLER_THREADS ++ ++// Put free descriptors onto the head of the free queue, rather than the tail, so that we don't thrash ++// our way through the pool of descriptors. ++#define VCHI_PUSH_FREE_DESCRIPTORS_ONTO_HEAD ++ ++// Don't issue a MSG_AVAILABLE callback for every single message. Possibly only safe if VCHI_COARSE_LOCKING. ++#define VCHI_FEWER_MSG_AVAILABLE_CALLBACKS ++ ++// Don't use message descriptors for TX messages that don't need them ++#define VCHI_MINIMISE_TX_MSG_DESCRIPTORS ++ ++// Nano-locks for multiqueue ++//#define VCHI_MQUEUE_NANOLOCKS ++ ++// Lock-free(er) dequeuing ++//#define VCHI_RX_NANOLOCKS ++ ++#endif /*VCHI_CFG_INTERNAL_H_*/ +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vchi/vchi_common.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vchi/vchi_common.h 2013-07-26 19:32:28.000000000 +0000 +@@ -0,0 +1,152 @@ ++/* ++ * Copyright (c) 2010-2011 Broadcom Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++/*============================================================================= ++Contains global defs used by submodules within vchi. ++=============================================================================*/ ++ ++#ifndef VCHI_COMMON_H_ ++#define VCHI_COMMON_H_ ++ ++ ++//flags used when sending messages (must be bitmapped) ++typedef enum ++{ ++ VCHI_FLAGS_NONE = 0x0, ++ VCHI_FLAGS_BLOCK_UNTIL_OP_COMPLETE = 0x1, // waits for message to be received, or sent (NB. not the same as being seen on other side) ++ VCHI_FLAGS_CALLBACK_WHEN_OP_COMPLETE = 0x2, // run a callback when message sent ++ VCHI_FLAGS_BLOCK_UNTIL_QUEUED = 0x4, // return once the transfer is in a queue ready to go ++ VCHI_FLAGS_ALLOW_PARTIAL = 0x8, ++ VCHI_FLAGS_BLOCK_UNTIL_DATA_READ = 0x10, ++ VCHI_FLAGS_CALLBACK_WHEN_DATA_READ = 0x20, ++ ++ VCHI_FLAGS_ALIGN_SLOT = 0x000080, // internal use only ++ VCHI_FLAGS_BULK_AUX_QUEUED = 0x010000, // internal use only ++ VCHI_FLAGS_BULK_AUX_COMPLETE = 0x020000, // internal use only ++ VCHI_FLAGS_BULK_DATA_QUEUED = 0x040000, // internal use only ++ VCHI_FLAGS_BULK_DATA_COMPLETE = 0x080000, // internal use only ++ VCHI_FLAGS_INTERNAL = 0xFF0000 ++} VCHI_FLAGS_T; ++ ++// constants for vchi_crc_control() ++typedef enum { ++ VCHI_CRC_NOTHING = -1, ++ VCHI_CRC_PER_SERVICE = 0, ++ VCHI_CRC_EVERYTHING = 1, ++} VCHI_CRC_CONTROL_T; ++ ++//callback reasons when an event occurs on a service ++typedef enum ++{ ++ VCHI_CALLBACK_REASON_MIN, ++ ++ //This indicates that there is data available ++ //handle is the msg id that was transmitted with the data ++ // When a message is received and there was no FULL message available previously, send callback ++ // Tasks get kicked by the callback, reset their event and try and read from the fifo until it fails ++ VCHI_CALLBACK_MSG_AVAILABLE, ++ VCHI_CALLBACK_MSG_SENT, ++ VCHI_CALLBACK_MSG_SPACE_AVAILABLE, // XXX not yet implemented ++ ++ // This indicates that a transfer from the other side has completed ++ VCHI_CALLBACK_BULK_RECEIVED, ++ //This indicates that data queued up to be sent has now gone ++ //handle is the msg id that was used when sending the data ++ VCHI_CALLBACK_BULK_SENT, ++ VCHI_CALLBACK_BULK_RX_SPACE_AVAILABLE, // XXX not yet implemented ++ VCHI_CALLBACK_BULK_TX_SPACE_AVAILABLE, // XXX not yet implemented ++ ++ VCHI_CALLBACK_SERVICE_CLOSED, ++ ++ // this side has sent XOFF to peer due to lack of data consumption by service ++ // (suggests the service may need to take some recovery action if it has ++ // been deliberately holding off consuming data) ++ VCHI_CALLBACK_SENT_XOFF, ++ VCHI_CALLBACK_SENT_XON, ++ ++ // indicates that a bulk transfer has finished reading the source buffer ++ VCHI_CALLBACK_BULK_DATA_READ, ++ ++ // power notification events (currently host side only) ++ VCHI_CALLBACK_PEER_OFF, ++ VCHI_CALLBACK_PEER_SUSPENDED, ++ VCHI_CALLBACK_PEER_ON, ++ VCHI_CALLBACK_PEER_RESUMED, ++ VCHI_CALLBACK_FORCED_POWER_OFF, ++ ++#ifdef USE_VCHIQ_ARM ++ // some extra notifications provided by vchiq_arm ++ VCHI_CALLBACK_SERVICE_OPENED, ++ VCHI_CALLBACK_BULK_RECEIVE_ABORTED, ++ VCHI_CALLBACK_BULK_TRANSMIT_ABORTED, ++#endif ++ ++ VCHI_CALLBACK_REASON_MAX ++} VCHI_CALLBACK_REASON_T; ++ ++//Calback used by all services / bulk transfers ++typedef void (*VCHI_CALLBACK_T)( void *callback_param, //my service local param ++ VCHI_CALLBACK_REASON_T reason, ++ void *handle ); //for transmitting msg's only ++ ++ ++ ++/* ++ * Define vector struct for scatter-gather (vector) operations ++ * Vectors can be nested - if a vector element has negative length, then ++ * the data pointer is treated as pointing to another vector array, with ++ * '-vec_len' elements. Thus to append a header onto an existing vector, ++ * you can do this: ++ * ++ * void foo(const VCHI_MSG_VECTOR_T *v, int n) ++ * { ++ * VCHI_MSG_VECTOR_T nv[2]; ++ * nv[0].vec_base = my_header; ++ * nv[0].vec_len = sizeof my_header; ++ * nv[1].vec_base = v; ++ * nv[1].vec_len = -n; ++ * ... ++ * ++ */ ++typedef struct vchi_msg_vector { ++ const void *vec_base; ++ int32_t vec_len; ++} VCHI_MSG_VECTOR_T; ++ ++// Opaque type for a connection API ++typedef struct opaque_vchi_connection_api_t VCHI_CONNECTION_API_T; ++ ++// Opaque type for a message driver ++typedef struct opaque_vchi_message_driver_t VCHI_MESSAGE_DRIVER_T; ++ ++ ++// Iterator structure for reading ahead through received message queue. Allocated by client, ++// initialised by vchi_msg_look_ahead. Fields are for internal VCHI use only. ++// Iterates over messages in queue at the instant of the call to vchi_msg_lookahead - ++// will not proceed to messages received since. Behaviour is undefined if an iterator ++// is used again after messages for that service are removed/dequeued by any ++// means other than vchi_msg_iter_... calls on the iterator itself. ++typedef struct { ++ struct opaque_vchi_service_t *service; ++ void *last; ++ void *next; ++ void *remove; ++} VCHI_MSG_ITER_T; ++ ++ ++#endif // VCHI_COMMON_H_ +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_2835_arm.c +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_2835_arm.c 2013-07-26 19:32:16.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_2835_arm.c 2013-07-26 19:32:28.000000000 +0000 +@@ -36,7 +36,7 @@ + #define TOTAL_SLOTS (VCHIQ_SLOT_ZERO_SLOTS + 2 * 32) + + #define VCHIQ_DOORBELL_IRQ IRQ_ARM_DOORBELL_0 +-#define VCHIQ_ARM_ADDRESS(x) __virt_to_bus((unsigned)x) ++#define VCHIQ_ARM_ADDRESS(x) ((void *)__virt_to_bus((unsigned)x)) + + #include "vchiq_arm.h" + #include "vchiq_2835.h" +@@ -182,7 +182,15 @@ + int + vchiq_copy_from_user(void *dst, const void *src, int size) + { +- return copy_from_user(dst, src, size); ++ if ( (uint32_t)src < TASK_SIZE) ++ { ++ return copy_from_user(dst, src, size); ++ } ++ else ++ { ++ memcpy( dst, src, size ); ++ return 0; ++ } + } + + VCHIQ_STATUS_T +@@ -239,6 +247,22 @@ + vchiq_dump(dump_context, buf, len + 1); + } + ++VCHIQ_STATUS_T ++vchiq_platform_suspend(VCHIQ_STATE_T *state) ++{ ++ vcos_unused(state); ++ vcos_assert_msg(0, "Suspend/resume not supported"); ++ return VCHIQ_ERROR; ++} ++ ++VCHIQ_STATUS_T ++vchiq_platform_resume(VCHIQ_STATE_T *state) ++{ ++ vcos_unused(state); ++ vcos_assert_msg(0, "Suspend/resume not supported"); ++ return VCHIQ_ERROR; ++} ++ + void + vchiq_platform_paused(VCHIQ_STATE_T *state) + { +@@ -253,33 +277,40 @@ + vcos_assert_msg(0, "Suspend/resume not supported"); + } + +-VCHIQ_STATUS_T +-vchiq_use_service(VCHIQ_SERVICE_HANDLE_T handle) ++int ++vchiq_platform_videocore_wanted(VCHIQ_STATE_T* state) + { +- VCHIQ_SERVICE_T *service = (VCHIQ_SERVICE_T *)handle; +- if (!service) +- return VCHIQ_ERROR; +- return VCHIQ_SUCCESS; ++ vcos_unused(state); ++ return 1; // autosuspend not supported - videocore always wanted + } + +-VCHIQ_STATUS_T +-vchiq_release_service(VCHIQ_SERVICE_HANDLE_T handle) ++#if VCOS_HAVE_TIMER ++int ++vchiq_platform_use_suspend_timer(void) + { +- VCHIQ_SERVICE_T *service = (VCHIQ_SERVICE_T *)handle; +- if (!service) +- return VCHIQ_ERROR; +- return VCHIQ_SUCCESS; ++ return 0; ++} ++#endif ++void ++vchiq_dump_platform_use_state(VCHIQ_STATE_T *state) ++{ ++ vcos_unused(state); + } + + VCHIQ_STATUS_T +-vchiq_check_service(VCHIQ_SERVICE_HANDLE_T handle) ++vchiq_platform_init_state(VCHIQ_STATE_T *state) + { +- VCHIQ_SERVICE_T *service = (VCHIQ_SERVICE_T *)handle; +- if (!service) +- return VCHIQ_ERROR; ++ vcos_unused(state); + return VCHIQ_SUCCESS; + } + ++VCHIQ_ARM_STATE_T* ++vchiq_platform_get_arm_state(VCHIQ_STATE_T *state) ++{ ++ vcos_unused(state); ++ return NULL; ++} ++ + /* + * Local functions + */ +@@ -479,9 +510,3 @@ + kfree(pagelist); + } + +-VCHIQ_STATUS_T +-vchiq_platform_suspend(VCHIQ_STATE_T *state) +-{ +- vcos_unused(state); +- return VCHIQ_ERROR; +-} +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_arm.c +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_arm.c 2013-07-26 19:32:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_arm.c 2013-07-26 19:32:28.000000000 +0000 +@@ -23,6 +23,9 @@ + #include + #include + #include ++#include ++#include ++#include + + #include "vchiq_core.h" + #include "vchiq_ioctl.h" +@@ -44,6 +47,15 @@ + + #define VCOS_LOG_CATEGORY (&vchiq_arm_log_category) + ++#define VCHIQ_ARM_VCSUSPEND_TASK_STACK 4096 ++ ++#if VCOS_HAVE_TIMER ++#define SUSPEND_TIMER_TIMEOUT_MS 100 ++static VCOS_TIMER_T g_suspend_timer; ++static void suspend_timer_callback(void *context); ++#endif ++ ++ + typedef struct client_service_struct { + VCHIQ_SERVICE_T *service; + void *userdata; +@@ -106,10 +118,17 @@ + "GET_CONFIG", + "CLOSE_SERVICE", + "USE_SERVICE", +- "RELEASE_SERIVCE" ++ "RELEASE_SERVICE", ++ "SET_SERVICE_OPTION", ++ "DUMP_PHYS_MEM" + }; + +-VCOS_LOG_LEVEL_T vchiq_default_arm_log_level = VCOS_LOG_WARN; ++vcos_static_assert(vcos_countof(ioctl_names) == (VCHIQ_IOC_MAX + 1)); ++ ++VCOS_LOG_LEVEL_T vchiq_default_arm_log_level = VCOS_LOG_ERROR; ++ ++static void ++dump_phys_mem( void *virt_addr, uint32_t num_bytes ); + + /**************************************************************************** + * +@@ -524,7 +543,7 @@ + status = (cmd == VCHIQ_IOC_USE_SERVICE) ? vchiq_use_service(&user_service->service->base) : vchiq_release_service(&user_service->service->base); + if (status != VCHIQ_SUCCESS) + { +- ret = -EINVAL; // ??? ++ ret = -EINVAL; /* ??? */ + } + } + } +@@ -872,6 +891,21 @@ + } + break; + ++ case VCHIQ_IOC_DUMP_PHYS_MEM: ++ { ++ VCHIQ_DUMP_MEM_T args; ++ ++ if (copy_from_user ++ (&args, (const void __user *)arg, ++ sizeof(args)) != 0) { ++ ret = -EFAULT; ++ break; ++ } ++ dump_phys_mem( args.virt_addr, args.num_bytes ); ++ } ++ break; ++ ++ + default: + ret = -ENOTTY; + break; +@@ -1153,6 +1187,88 @@ + + /**************************************************************************** + * ++* dump_user_mem ++* ++***************************************************************************/ ++ ++static void ++dump_phys_mem( void *virt_addr, uint32_t num_bytes ) ++{ ++ int rc; ++ uint8_t *end_virt_addr = virt_addr + num_bytes; ++ int num_pages; ++ int offset; ++ int end_offset; ++ int page_idx; ++ int prev_idx; ++ struct page *page; ++ struct page **pages; ++ uint8_t *kmapped_virt_ptr; ++ ++ // Align virtAddr and endVirtAddr to 16 byte boundaries. ++ ++ virt_addr = (void *)((unsigned long)virt_addr & ~0x0fuL ); ++ end_virt_addr = (void *)(( (unsigned long)end_virt_addr + 15uL ) & ~0x0fuL); ++ ++ offset = (int)(long)virt_addr & ( PAGE_SIZE - 1 ); ++ end_offset = (int)(long)end_virt_addr & ( PAGE_SIZE - 1 ); ++ ++ num_pages = (offset + num_bytes + PAGE_SIZE - 1) / PAGE_SIZE; ++ ++ if (( pages = kmalloc( sizeof( struct page *) * num_pages, GFP_KERNEL )) == NULL ) ++ { ++ printk( KERN_ERR "Unable to allocation memory for %d pages\n", num_pages ); ++ return; ++ } ++ ++ down_read( ¤t->mm->mmap_sem ); ++ rc = get_user_pages( current, /* task */ ++ current->mm, /* mm */ ++ (unsigned long)virt_addr, /* start */ ++ num_pages, /* len */ ++ 0, /* write */ ++ 0, /* force */ ++ pages, /* pages (array of pointers to page) */ ++ NULL ); /* vmas */ ++ up_read( ¤t->mm->mmap_sem ); ++ ++ prev_idx = -1; ++ page = NULL; ++ ++ while ( offset < end_offset ) { ++ ++ int page_offset = offset % PAGE_SIZE; ++ page_idx = offset / PAGE_SIZE; ++ ++ if ( page_idx != prev_idx ) { ++ ++ if (page != NULL) { ++ kunmap( page ); ++ } ++ page = pages[page_idx]; ++ kmapped_virt_ptr = kmap( page ); ++ ++ prev_idx = page_idx; ++ } ++ ++ vcos_log_dump_mem_impl( &vchiq_arm_log_category, "ph", ++ (uint32_t)(unsigned long)&kmapped_virt_ptr[page_offset], ++ &kmapped_virt_ptr[page_offset], 16 ); ++ ++ offset += 16; ++ } ++ if (page != NULL) { ++ kunmap( page ); ++ } ++ ++ for ( page_idx = 0; page_idx < num_pages; page_idx++ ) { ++ page_cache_release( pages[page_idx] ); ++ } ++ kfree( pages ); ++} ++ ++/**************************************************************************** ++* + * vchiq_read + * + ***************************************************************************/ +@@ -1204,6 +1320,498 @@ + .read = vchiq_read + }; + ++/* ++ * Autosuspend related functionality ++ */ ++ ++static int vchiq_videocore_wanted(VCHIQ_STATE_T* state) ++{ ++ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state); ++ if(!arm_state) ++ { // autosuspend not supported - always return wanted ++ return 1; ++ } ++ else if(!arm_state->videocore_use_count) ++ { // usage count zero - check for override ++ return vchiq_platform_videocore_wanted(state); ++ } ++ else ++ { // non-zero usage count - videocore still required ++ return 1; ++ } ++} ++ ++ ++/* Called by the lp thread */ ++static void * ++lp_func(void *v) ++{ ++ VCHIQ_STATE_T *state = (VCHIQ_STATE_T *) v; ++ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state); ++ ++ while (1) { ++ vcos_event_wait(&arm_state->lp_evt); ++ ++ vcos_mutex_lock(&arm_state->use_count_mutex); ++ if (!vchiq_videocore_wanted(state)) ++ { ++ arm_state->suspend_pending = 1; ++ } ++ vcos_mutex_unlock(&arm_state->use_count_mutex); ++ ++ vchiq_arm_vcsuspend(state); ++ } ++ return NULL; ++} ++/* Called by the hp thread */ ++static void * ++hp_func(void *v) ++{ ++ VCHIQ_STATE_T *state = (VCHIQ_STATE_T *) v; ++ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state); ++ int send_pending; ++ ++ while (1) { ++ vcos_event_wait(&arm_state->hp_evt); ++ ++ send_pending = 0; ++ ++ vcos_mutex_lock(&arm_state->use_count_mutex); ++ if (vchiq_videocore_wanted(state)) ++ { ++ vchiq_arm_vcresume(state); ++ } ++ if(arm_state->use_notify_pending) ++ { ++ send_pending = 1; ++ arm_state->use_notify_pending = 0; ++ } ++ vcos_mutex_unlock(&arm_state->use_count_mutex); ++ if(send_pending) ++ { ++ vcos_log_info( "%s sending VCHIQ_MSG_REMOTE_USE_ACTIVE", __func__); ++ if ( vchiq_send_remote_use_active(state) != VCHIQ_SUCCESS) ++ { ++ BUG(); /* vc should be resumed, so shouldn't be a problem sending message */ ++ } ++ } ++ } ++ return NULL; ++} ++ ++VCHIQ_STATUS_T ++vchiq_arm_init_state(VCHIQ_STATE_T* state, VCHIQ_ARM_STATE_T *arm_state) ++{ ++ VCHIQ_STATUS_T status = VCHIQ_SUCCESS; ++ VCOS_THREAD_ATTR_T attrs; ++ char threadname[10]; ++ ++ if(arm_state) ++ { ++ vcos_mutex_create(&arm_state->use_count_mutex, "v.use_count_mutex"); ++ vcos_mutex_create(&arm_state->suspend_resume_mutex, "v.susp_res_mutex"); ++ ++ vcos_event_create(&arm_state->lp_evt, "LP_EVT"); ++ vcos_event_create(&arm_state->hp_evt, "HP_EVT"); ++ ++ vcos_thread_attr_init(&attrs); ++ vcos_thread_attr_setstacksize(&attrs, VCHIQ_ARM_VCSUSPEND_TASK_STACK); ++ vcos_thread_attr_setpriority(&attrs, VCOS_THREAD_PRI_LOWEST); ++ vcos_snprintf(threadname, sizeof(threadname), "VCHIQl-%d", state->id); ++ if(vcos_thread_create(&arm_state->lp_thread, threadname, &attrs, lp_func, state) != VCOS_SUCCESS) ++ { ++ vcos_log_error("vchiq: FATAL: couldn't create thread %s", threadname); ++ status = VCHIQ_ERROR; ++ } ++ else ++ { ++ vcos_thread_attr_init(&attrs); ++ vcos_thread_attr_setstacksize(&attrs, VCHIQ_ARM_VCSUSPEND_TASK_STACK); ++ vcos_thread_attr_setpriority(&attrs, VCOS_THREAD_PRI_HIGHEST); ++ vcos_snprintf(threadname, sizeof(threadname), "VCHIQh-%d", state->id); ++ ++ if(vcos_thread_create(&arm_state->hp_thread, threadname, &attrs, hp_func, state) != VCOS_SUCCESS) ++ { ++ vcos_log_error("vchiq: FATAL: couldn't create thread %s", threadname); ++ status = VCHIQ_ERROR; ++ } ++ } ++ } ++ return status; ++} ++ ++ ++VCHIQ_STATUS_T ++vchiq_arm_vcsuspend(VCHIQ_STATE_T *state) ++{ ++ VCHIQ_STATUS_T status = VCHIQ_SUCCESS; ++ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state); ++ ++ if (state->conn_state != VCHIQ_CONNSTATE_CONNECTED) ++ return VCHIQ_ERROR; ++ ++ if(arm_state->suspend_pending) ++ { ++ vcos_mutex_lock(&arm_state->suspend_resume_mutex); ++ if(arm_state->videocore_suspended) ++ { ++ vcos_log_info("%s - already suspended", __func__); ++ } ++ else ++ { ++ vcos_log_info("%s - suspending", __func__); ++ ++ status = vchiq_platform_suspend(state); ++ arm_state->videocore_suspended = (status == VCHIQ_SUCCESS) ? 1 : 0; ++ ++ vcos_mutex_unlock(&arm_state->suspend_resume_mutex); ++ ++ vcos_mutex_lock(&arm_state->use_count_mutex); ++ if(!arm_state->suspend_pending) ++ { /* Something has changed the suspend_pending state while we were suspending. ++ Run the HP task to check if we need to resume */ ++ vcos_log_info( "%s trigger HP task to check resume", __func__); ++ vcos_event_signal(&arm_state->hp_evt); ++ } ++ arm_state->suspend_pending = 0; ++ vcos_mutex_unlock(&arm_state->use_count_mutex); ++ } ++ } ++ else ++ { ++ vchiq_check_resume(state); ++ } ++ return status; ++} ++ ++ ++VCHIQ_STATUS_T ++vchiq_arm_vcresume(VCHIQ_STATE_T *state) ++{ ++ VCHIQ_STATUS_T status = VCHIQ_SUCCESS; ++ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state); ++ vcos_mutex_lock(&arm_state->suspend_resume_mutex); ++ ++ status = vchiq_platform_resume(state); ++ arm_state->videocore_suspended = (status == VCHIQ_RETRY) ? 1 : 0; ++ ++ vcos_mutex_unlock(&arm_state->suspend_resume_mutex); ++ ++ return status; ++} ++ ++void ++vchiq_check_resume(VCHIQ_STATE_T* state) ++{ ++ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state); ++ vcos_mutex_lock(&arm_state->use_count_mutex); ++ ++ if (arm_state->videocore_suspended && vchiq_videocore_wanted(state)) ++ { /* signal high priority task to resume vc */ ++ vcos_event_signal(&arm_state->hp_evt); ++ } ++ ++ vcos_mutex_unlock(&arm_state->use_count_mutex); ++} ++ ++void ++vchiq_check_suspend(VCHIQ_STATE_T* state) ++{ ++ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state); ++ ++ vcos_mutex_lock(&arm_state->use_count_mutex); ++ ++ if (!arm_state->videocore_suspended && !vchiq_videocore_wanted(state)) ++ { /* signal low priority task to suspend vc */ ++ vcos_event_signal(&arm_state->lp_evt); ++ } ++ ++ vcos_mutex_unlock(&arm_state->use_count_mutex); ++} ++ ++ ++ ++static VCHIQ_STATUS_T ++vchiq_use_internal(VCHIQ_STATE_T *state, VCHIQ_SERVICE_T *service, int block_while_resume) ++{ ++ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state); ++ VCHIQ_STATUS_T ret = VCHIQ_SUCCESS; ++ char entity[10]; ++ int* entity_uc; ++ ++ if(arm_state) ++ { ++ vcos_mutex_lock(&arm_state->use_count_mutex); ++ ++ if (service) ++ { ++ sprintf(entity, "%c%c%c%c:%03d",VCHIQ_FOURCC_AS_4CHARS(service->base.fourcc), service->client_id); ++ entity_uc = &service->service_use_count; ++ } ++ else ++ { ++ sprintf(entity, "PEER: "); ++ entity_uc = &arm_state->peer_use_count; ++ } ++ ++ if (!arm_state->videocore_suspended && !vchiq_videocore_wanted(state)) ++ { ++#if VCOS_HAVE_TIMER ++ if (vchiq_platform_use_suspend_timer()) ++ { ++ vcos_log_trace( "%s %s - cancel suspend timer", __func__, entity); ++ } ++ vcos_timer_cancel(&g_suspend_timer); ++#endif ++ } ++ ++ arm_state->videocore_use_count++; ++ (*entity_uc)++; ++ arm_state->suspend_pending = 0; ++ ++ if (arm_state->videocore_suspended && vchiq_videocore_wanted(state)) ++ { ++ vcos_log_info( "%s %s count %d, state count %d", __func__, entity, *entity_uc, arm_state->videocore_use_count); ++ if(block_while_resume) ++ { ++ ret = vchiq_arm_vcresume(state); ++ } ++ else ++ { ++ vcos_log_info( "%s trigger HP task to do resume", __func__); /* triggering is done below */ ++ } ++ } ++ else ++ { ++ vcos_log_trace( "%s %s count %d, state count %d", __func__, entity, *entity_uc, arm_state->videocore_use_count); ++ } ++ if(!block_while_resume) ++ { ++ arm_state->use_notify_pending = 1; ++ vcos_event_signal(&arm_state->hp_evt); /* hp task will check if we need to resume and also send use notify */ ++ } ++ ++ if (ret == VCHIQ_RETRY) ++ { /* if we're told to retry, decrement the counters. VCHIQ_ERROR probably means we're already resumed. */ ++ (*entity_uc)--; ++ arm_state->videocore_use_count--; ++ } ++ ++ vcos_mutex_unlock(&arm_state->use_count_mutex); ++ } ++ return ret; ++} ++ ++static VCHIQ_STATUS_T ++vchiq_release_internal(VCHIQ_STATE_T *state, VCHIQ_SERVICE_T *service) ++{ ++ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state); ++ VCHIQ_STATUS_T ret = VCHIQ_SUCCESS; ++ char entity[10]; ++ int* entity_uc; ++ ++ if(arm_state) ++ { ++ vcos_mutex_lock(&arm_state->use_count_mutex); ++ ++ if (service) ++ { ++ sprintf(entity, "%c%c%c%c:%03d",VCHIQ_FOURCC_AS_4CHARS(service->base.fourcc), service->client_id); ++ entity_uc = &service->service_use_count; ++ } ++ else ++ { ++ sprintf(entity, "PEER: "); ++ entity_uc = &arm_state->peer_use_count; ++ } ++ ++ if (*entity_uc && arm_state->videocore_use_count) ++ { ++ arm_state->videocore_use_count--; ++ (*entity_uc)--; ++ ++ if (!vchiq_videocore_wanted(state)) ++ { ++#if VCOS_HAVE_TIMER ++ if (vchiq_platform_use_suspend_timer()) ++ { ++ vcos_log_trace( "%s %s count %d, state count %d - starting suspend timer", __func__, entity, *entity_uc, arm_state->videocore_use_count); ++ vcos_timer_cancel(&g_suspend_timer); ++ vcos_timer_set(&g_suspend_timer, SUSPEND_TIMER_TIMEOUT_MS); ++ } ++ else ++#endif ++ { ++ vcos_log_info( "%s %s count %d, state count %d - suspend pending", __func__, entity, *entity_uc, arm_state->videocore_use_count); ++ vcos_event_signal(&arm_state->lp_evt); /* kick the lp thread to do the suspend */ ++ } ++ } ++ else ++ { ++ vcos_log_trace( "%s %s count %d, state count %d", __func__, entity, *entity_uc, arm_state->videocore_use_count); ++ } ++ } ++ else ++ { ++ vcos_log_error( "%s %s ERROR releasing service; count %d, state count %d", __func__, entity, *entity_uc, arm_state->videocore_use_count); ++ ret = VCHIQ_ERROR; ++ } ++ ++ vcos_mutex_unlock(&arm_state->use_count_mutex); ++ } ++ return ret; ++} ++ ++VCHIQ_STATUS_T ++vchiq_on_remote_use(VCHIQ_STATE_T *state) ++{ ++ vcos_log_info("%s state %p", __func__, state); ++ return state ? vchiq_use_internal(state, NULL, 0) : VCHIQ_ERROR; ++} ++ ++VCHIQ_STATUS_T ++vchiq_on_remote_release(VCHIQ_STATE_T *state) ++{ ++ vcos_log_info("%s state %p", __func__, state); ++ return state ? vchiq_release_internal(state, NULL) : VCHIQ_ERROR; ++} ++ ++VCHIQ_STATUS_T ++vchiq_use_service_internal(VCHIQ_SERVICE_T *service) ++{ ++ VCHIQ_STATE_T* state = NULL; ++ ++ if (service) ++ { ++ state = service->state; ++ } ++ ++ if (!service || !state) ++ { ++ return VCHIQ_ERROR; ++ } ++ return vchiq_use_internal(state, service, 1); ++} ++ ++VCHIQ_STATUS_T ++vchiq_release_service_internal(VCHIQ_SERVICE_T *service) ++{ ++ VCHIQ_STATE_T* state = NULL; ++ ++ if (service) ++ { ++ state = service->state; ++ } ++ ++ if (!service || !state) ++ { ++ return VCHIQ_ERROR; ++ } ++ return vchiq_release_internal(state, service); ++} ++ ++ ++#if VCOS_HAVE_TIMER ++static void suspend_timer_callback(void* context) ++{ ++ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state((VCHIQ_STATE_T*)context); ++ vcos_log_info( "%s - suspend pending", __func__); ++ vcos_event_signal(&arm_state->lp_evt); ++} ++#endif ++ ++VCHIQ_STATUS_T ++vchiq_use_service(VCHIQ_SERVICE_HANDLE_T handle) ++{ ++ VCHIQ_STATUS_T ret = VCHIQ_ERROR; ++ VCHIQ_SERVICE_T *service = (VCHIQ_SERVICE_T *) handle; ++ if (service) ++ { ++ ret = vchiq_use_service_internal(service); ++ } ++ return ret; ++} ++ ++VCHIQ_STATUS_T ++vchiq_release_service(VCHIQ_SERVICE_HANDLE_T handle) ++{ ++ VCHIQ_STATUS_T ret = VCHIQ_ERROR; ++ VCHIQ_SERVICE_T *service = (VCHIQ_SERVICE_T *) handle; ++ if (service) ++ { ++ ret = vchiq_release_service_internal(service); ++ } ++ return ret; ++} ++ ++void ++vchiq_dump_service_use_state(VCHIQ_STATE_T *state) ++{ ++ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state); ++ int i; ++ if(arm_state) ++ { ++ vcos_mutex_lock(&arm_state->suspend_resume_mutex); ++ if (arm_state->videocore_suspended) ++ { ++ vcos_log_warn("--VIDEOCORE SUSPENDED--"); ++ } ++ else ++ { ++ vcos_log_warn("--VIDEOCORE AWAKE--"); ++ } ++ for (i = 0; i < state->unused_service; i++) { ++ VCHIQ_SERVICE_T *service_ptr = state->services[i]; ++ if (service_ptr && (service_ptr->srvstate != VCHIQ_SRVSTATE_FREE)) ++ { ++ if (service_ptr->service_use_count) ++ vcos_log_error("----- %c%c%c%c:%d service count %d <-- preventing suspend", VCHIQ_FOURCC_AS_4CHARS(service_ptr->base.fourcc), service_ptr->client_id, service_ptr->service_use_count); ++ else ++ vcos_log_warn("----- %c%c%c%c:%d service count 0", VCHIQ_FOURCC_AS_4CHARS(service_ptr->base.fourcc), service_ptr->client_id); ++ } ++ } ++ vcos_log_warn("----- PEER use count count %d", arm_state->peer_use_count); ++ vcos_log_warn("--- Overall vchiq instance use count %d", arm_state->videocore_use_count); ++ ++ vchiq_dump_platform_use_state(state); ++ ++ vcos_mutex_unlock(&arm_state->suspend_resume_mutex); ++ } ++} ++ ++VCHIQ_STATUS_T ++vchiq_check_service(VCHIQ_SERVICE_T * service) ++{ ++ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(service->state); ++ VCHIQ_STATUS_T ret = VCHIQ_ERROR; ++ /* on 2835 vchiq does not have an arm_state */ ++ if (!arm_state) ++ return VCHIQ_SUCCESS; ++ if (service && arm_state) ++ { ++ vcos_mutex_lock(&arm_state->use_count_mutex); ++ if (!service->service_use_count) ++ { ++ vcos_log_error( "%s ERROR - %c%c%c%c:%d service count %d, state count %d, videocore_suspended %d", __func__,VCHIQ_FOURCC_AS_4CHARS(service->base.fourcc), service->client_id, service->service_use_count, arm_state->videocore_use_count, arm_state->videocore_suspended); ++ vchiq_dump_service_use_state(service->state); ++ vcos_assert(0); // vcos_assert should kill the calling thread, so a user thread shouldn't be able to kill the kernel. ++ } ++ else ++ { ++ ret = VCHIQ_SUCCESS; ++ } ++ vcos_mutex_unlock(&arm_state->use_count_mutex); ++ } ++ return ret; ++} ++ ++/* stub functions */ ++void vchiq_on_remote_use_active(VCHIQ_STATE_T *state) ++{ ++ vcos_unused(state); ++} ++ ++ + /**************************************************************************** + * + * vchiq_init - called when the module is loaded. +@@ -1250,6 +1858,10 @@ + if (err != 0) + goto failed_platform_init; + ++#if VCOS_HAVE_TIMER ++ vcos_timer_create( &g_suspend_timer, "suspend_timer", suspend_timer_callback, (void*)(&g_state)); ++#endif ++ + vcos_log_error("vchiq: initialised - version %d (min %d), device %d.%d", + VCHIQ_VERSION, VCHIQ_VERSION_MIN, + MAJOR(vchiq_devid), MINOR(vchiq_devid)); +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_arm.h +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_arm.h 2013-07-26 19:32:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_arm.h 2013-07-26 19:32:28.000000000 +0000 +@@ -21,6 +21,40 @@ + + #include "vchiq_core.h" + ++ ++typedef struct vchiq_arm_state_struct { ++ ++ VCOS_THREAD_T lp_thread; /* processes low priority messages (eg suspend) */ ++ VCOS_THREAD_T hp_thread; /* processes high priority messages (eg resume) */ ++ ++ VCOS_EVENT_T lp_evt; ++ VCOS_EVENT_T hp_evt; ++ ++ VCOS_MUTEX_T use_count_mutex; ++ VCOS_MUTEX_T suspend_resume_mutex; ++ ++ int suspend_pending; ++ ++ /* Global use count for videocore. ++ * This is equal to the sum of the use counts for all services. When this hits ++ * zero the videocore suspend procedure will be initiated. */ ++ int videocore_use_count; ++ ++ /* Use count to track requests from videocore peer. ++ * This use count is not associated with a service, so needs to be tracked separately ++ * with the state. ++ */ ++ int peer_use_count; ++ ++ /* Flag to indicate whether videocore is currently suspended */ ++ int videocore_suspended; ++ ++ /* Flag to indicate whether a notification is pending back to videocore that it's ++ * "remote use request" has been actioned */ ++ int use_notify_pending; ++} VCHIQ_ARM_STATE_T; ++ ++ + extern VCOS_LOG_CAT_T vchiq_arm_log_category; + + extern int __init +@@ -35,4 +69,50 @@ + extern VCHIQ_STATE_T * + vchiq_get_state(void); + ++extern VCHIQ_STATUS_T ++vchiq_arm_vcsuspend(VCHIQ_STATE_T *state); ++ ++extern VCHIQ_STATUS_T ++vchiq_arm_vcresume(VCHIQ_STATE_T *state); ++ ++extern VCHIQ_STATUS_T ++vchiq_arm_init_state(VCHIQ_STATE_T *state, VCHIQ_ARM_STATE_T *arm_state); ++ ++extern void ++vchiq_check_resume(VCHIQ_STATE_T* state); ++ ++extern void ++vchiq_check_suspend(VCHIQ_STATE_T* state); ++ ++extern VCHIQ_STATUS_T ++vchiq_use_service(VCHIQ_SERVICE_HANDLE_T handle); ++ ++extern VCHIQ_STATUS_T ++vchiq_release_service(VCHIQ_SERVICE_HANDLE_T handle); ++ ++extern VCHIQ_STATUS_T ++vchiq_check_service(VCHIQ_SERVICE_T * service); ++ ++extern VCHIQ_STATUS_T ++vchiq_platform_suspend(VCHIQ_STATE_T *state); ++ ++extern VCHIQ_STATUS_T ++vchiq_platform_resume(VCHIQ_STATE_T *state); ++ ++extern int ++vchiq_platform_videocore_wanted(VCHIQ_STATE_T* state); ++ ++extern int ++vchiq_platform_use_suspend_timer(void); ++ ++extern void ++vchiq_dump_platform_use_state(VCHIQ_STATE_T *state); ++ ++extern void ++vchiq_dump_service_use_state(VCHIQ_STATE_T *state); ++ ++extern VCHIQ_ARM_STATE_T* ++vchiq_platform_get_arm_state(VCHIQ_STATE_T *state); ++ ++ + #endif /* VCHIQ_ARM_H */ +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_core.c +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_core.c 2013-07-26 19:32:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_core.c 2013-07-26 19:32:28.000000000 +0000 +@@ -30,6 +30,11 @@ + + #define BULK_INDEX(x) (x & (VCHIQ_NUM_SERVICE_BULKS - 1)) + ++ ++/* Used to check use counts allow vchiq use. */ ++extern VCHIQ_STATUS_T vchiq_check_service(VCHIQ_SERVICE_T * service); ++ ++ + typedef struct bulk_waiter_struct + { + VCOS_EVENT_T event; +@@ -114,6 +119,13 @@ + service->srvstate = newstate; + } + ++static inline int ++is_valid_service(VCHIQ_SERVICE_T *service) ++{ ++ return ((service != NULL) && ++ (service->srvstate != VCHIQ_SRVSTATE_FREE)); ++} ++ + static inline VCHIQ_STATUS_T + make_service_callback(VCHIQ_SERVICE_T *service, VCHIQ_REASON_T reason, + VCHIQ_HEADER_T *header, void *bulk_userdata) +@@ -323,7 +335,7 @@ + + while (slot_queue_available != local->slot_queue_recycle) + { +- int pos; ++ unsigned int pos; + int slot_index = local->slot_queue[slot_queue_available++ & VCHIQ_SLOT_QUEUE_MASK]; + char *data = (char *)SLOT_DATA_FROM_INDEX(state, slot_index); + +@@ -343,17 +355,37 @@ + if (VCHIQ_MSG_TYPE(msgid) == VCHIQ_MSG_DATA) + { + int port = VCHIQ_MSG_SRCPORT(msgid); ++ VCHIQ_SERVICE_QUOTA_T *service_quota = ++ &state->service_quotas[port]; ++ int count; ++ count = service_quota->message_use_count; ++ if (count > 0) ++ { ++ service_quota->message_use_count = count - 1; ++ if (count == service_quota->message_quota) ++ { ++ /* Signal the service that it has dropped below its quota */ ++ vcos_event_signal(&service_quota->quota_event); ++ } ++ } ++ else ++ { ++ vcos_log_error("service %d message_use_count=%d (header %x," ++ " msgid %x, header->msgid %x, header->size %x)", ++ port, service_quota->message_use_count, ++ (unsigned int)header, msgid, header->msgid, ++ header->size); ++ vcos_assert(0); ++ } + if (!BITSET_IS_SET(service_found, port)) + { +- VCHIQ_SERVICE_QUOTA_T *service_quota = +- &state->service_quotas[port]; +- + /* Set the found bit for this service */ + BITSET_SET(service_found, port); + +- if (service_quota->slot_use_count > 0) ++ count = service_quota->slot_use_count; ++ if (count > 0) + { +- service_quota->slot_use_count--; ++ service_quota->slot_use_count = count - 1; + /* Signal the service in case it has dropped below its quota */ + vcos_event_signal(&service_quota->quota_event); + vcos_log_trace("%d: pfq:%d %x@%x - slot_use->%d", +@@ -376,7 +408,7 @@ + pos += calc_stride(header->size); + if (pos > VCHIQ_SLOT_SIZE) + { +- vcos_log_error("pos %x: header %x, msgid %x, header->msgid %x, header->size %x", ++ vcos_log_error("pfq - pos %x: header %x, msgid %x, header->msgid %x, header->size %x", + pos, (unsigned int)header, msgid, header->msgid, header->size); + vcos_assert(0); + } +@@ -431,20 +463,21 @@ + + service_quota = &state->service_quotas[service->localport]; + +- /* ...ensure it doesn't use more than its quota of slots */ +- while ((tx_end_index != service_quota->previous_tx_index) && +- (service_quota->slot_use_count == service_quota->slot_quota)) ++ /* ...ensure it doesn't use more than its quota of messages or slots */ ++ while ((service_quota->message_use_count == service_quota->message_quota) || ++ ((tx_end_index != service_quota->previous_tx_index) && ++ (service_quota->slot_use_count == service_quota->slot_quota))) + { +- vcos_log_trace("%d: qm:%d %s,%x - quota stall", ++ vcos_log_trace("%d: qm:%d %s,%x - quota stall (msg %d, slot %d)", + state->id, service->localport, +- msg_type_str(VCHIQ_MSG_TYPE(msgid)), size); ++ msg_type_str(VCHIQ_MSG_TYPE(msgid)), size, ++ service_quota->message_use_count, service_quota->slot_use_count); + VCHIQ_SERVICE_STATS_INC(service, quota_stalls); + vcos_mutex_unlock(&state->slot_mutex); + if (vcos_event_wait(&service_quota->quota_event) != VCOS_SUCCESS) + return VCHIQ_RETRY; + if (vcos_mutex_lock(&state->slot_mutex) != VCOS_SUCCESS) + return VCHIQ_RETRY; +- vcos_assert(service_quota->slot_use_count <= service_quota->slot_quota); + tx_end_index = SLOT_QUEUE_INDEX_FROM_POS(state->local_tx_pos + stride - 1); + } + } +@@ -498,6 +531,7 @@ + } + + service_quota->previous_tx_index = tx_end_index; ++ service_quota->message_use_count++; + VCHIQ_SERVICE_STATS_INC(service, ctrl_tx_count); + VCHIQ_SERVICE_STATS_ADD(service, ctrl_tx_bytes, size); + } else { +@@ -1232,6 +1266,17 @@ + vchiq_set_conn_state(state, VCHIQ_CONNSTATE_CONNECTED); + vchiq_platform_resumed(state); + break; ++ ++ case VCHIQ_MSG_REMOTE_USE: ++ vchiq_on_remote_use(state); ++ break; ++ case VCHIQ_MSG_REMOTE_RELEASE: ++ vchiq_on_remote_release(state); ++ break; ++ case VCHIQ_MSG_REMOTE_USE_ACTIVE: ++ vchiq_on_remote_use_active(state); ++ break; ++ + default: + vcos_log_error("%d: prs invalid msgid %x@%x,%x", + state->id, msgid, (unsigned int)header, size); +@@ -1326,8 +1371,6 @@ + return NULL; + } + +-extern VCHIQ_STATUS_T +-vchiq_platform_suspend(VCHIQ_STATE_T *state); + + /* Called by the recycle thread */ + static void * +@@ -1348,23 +1391,6 @@ + return NULL; + } + +-/* Called by the lp thread */ +-static void * +-lp_func(void *v) +-{ +- VCHIQ_STATE_T *state = (VCHIQ_STATE_T *) v; +- +- while (1) { +- vcos_event_wait(&state->lp_evt); +- vcos_mutex_lock(&state->use_count_mutex); +- if (state->videocore_use_count == 0) +- { +- vchiq_platform_suspend(state); +- } +- vcos_mutex_unlock(&state->use_count_mutex); +- } +- return NULL; +-} + + static void + init_bulk_queue(VCHIQ_BULK_QUEUE_T *queue) +@@ -1417,6 +1443,7 @@ + VCHIQ_SHARED_STATE_T *local; + VCHIQ_SHARED_STATE_T *remote; + VCOS_THREAD_ATTR_T attrs; ++ VCHIQ_STATUS_T status; + char threadname[10]; + static int id = 0; + int i; +@@ -1426,7 +1453,7 @@ + vcos_log_register("vchiq_core", &vchiq_core_log_category); + vcos_log_register("vchiq_core_msg", &vchiq_core_msg_log_category); + +- vcos_log_warn( "%s: slot_zero = 0x%08lx, is_master = %d\n", __func__, (unsigned long)slot_zero, is_master ); ++ vcos_log_warn( "%s: slot_zero = 0x%08lx, is_master = %d", __func__, (unsigned long)slot_zero, is_master ); + + /* Check the input configuration */ + +@@ -1501,6 +1528,7 @@ + } + + memset(state, 0, sizeof(VCHIQ_STATE_T)); ++ vcos_log_warn( "%s: called", __func__); + state->id = id++; + state->is_master = is_master; + +@@ -1523,8 +1551,6 @@ + + vcos_mutex_create(&state->slot_mutex, "v.slot_mutex"); + vcos_mutex_create(&state->recycle_mutex, "v.recycle_mutex"); +- vcos_mutex_create(&state->use_count_mutex, "v.use_count_mutex"); +- vcos_mutex_create(&state->suspend_resume_mutex, "v.susp_res_mutex"); + + vcos_event_create(&state->slot_available_event, "v.slot_available_event"); + vcos_event_create(&state->slot_remove_event, "v.slot_remove_event"); +@@ -1543,6 +1569,7 @@ + } + + state->default_slot_quota = state->slot_queue_available/2; ++ state->default_message_quota = vcos_min(state->default_slot_quota * 256, (unsigned short)~0); + + local->trigger.event = &state->trigger_event; + remote_event_create(&local->trigger); +@@ -1552,8 +1579,6 @@ + remote_event_create(&local->recycle); + local->slot_queue_recycle = state->slot_queue_available; + +- vcos_event_create(&state->lp_evt, "LP_EVT"); +- + local->debug[DEBUG_ENTRIES] = DEBUG_MAX; + + /* +@@ -1566,7 +1591,10 @@ + vcos_snprintf(threadname, sizeof(threadname), "VCHIQ-%d", state->id); + if (vcos_thread_create(&state->slot_handler_thread, threadname, + &attrs, slot_handler_func, state) != VCOS_SUCCESS) ++ { ++ vcos_log_error("vchiq: FATAL: couldn't create thread %s", threadname); + return VCHIQ_ERROR; ++ } + + vcos_thread_attr_init(&attrs); + vcos_thread_attr_setstacksize(&attrs, VCHIQ_SLOT_HANDLER_STACK); +@@ -1574,20 +1602,17 @@ + vcos_snprintf(threadname, sizeof(threadname), "VCHIQr-%d", state->id); + if (vcos_thread_create(&state->recycle_thread, threadname, + &attrs, recycle_func, state) != VCOS_SUCCESS) ++ { ++ vcos_log_error("vchiq: FATAL: couldn't create thread %s", threadname); + return VCHIQ_ERROR; ++ } + +- vcos_thread_attr_init(&attrs); +- vcos_thread_attr_setstacksize(&attrs, VCHIQ_SLOT_HANDLER_STACK); +- vcos_thread_attr_setpriority(&attrs, VCOS_THREAD_PRI_LOWEST); +- vcos_snprintf(threadname, sizeof(threadname), "VCHIQl-%d", state->id); +- if (vcos_thread_create(&state->lp_thread, threadname, +- &attrs, lp_func, state) != VCOS_SUCCESS) +- return VCHIQ_ERROR; ++ status = vchiq_platform_init_state(state); + + /* Indicate readiness to the other side */ + local->initialised = 1; + +- return VCHIQ_SUCCESS; ++ return status; + } + + /* Called from application thread when a client or server service is created. */ +@@ -1684,6 +1709,7 @@ + init_bulk_queue(&service->bulk_tx); + init_bulk_queue(&service->bulk_rx); + service_quota->slot_quota = state->default_slot_quota; ++ service_quota->message_quota = state->default_message_quota; + if (service_quota->slot_use_count == 0) + service_quota->previous_tx_index = + SLOT_QUEUE_INDEX_FROM_POS(state->local_tx_pos) - 1; +@@ -1833,9 +1859,13 @@ + + if (service->srvstate == VCHIQ_SRVSTATE_CLOSING) + { ++ int i; ++ int uc = service->service_use_count; + /* Complete the close process */ +- vchiq_release_service(&service->base); +- ++ for( i=0; iclient_id = 0; + + /* Now tell the client that the services is closed */ +@@ -1912,7 +1942,7 @@ + if (slot_info->release_count != slot_info->use_count) + { + char *data = (char *)SLOT_DATA_FROM_INDEX(state, i); +- int pos, end; ++ unsigned int pos, end; + + end = VCHIQ_SLOT_SIZE; + if (data == state->rx_data) +@@ -1938,6 +1968,12 @@ + } + } + pos += calc_stride(header->size); ++ if (pos > VCHIQ_SLOT_SIZE) ++ { ++ vcos_log_error("fsi - pos %x: header %x, msgid %x, header->msgid %x, header->size %x", ++ pos, (unsigned int)header, msgid, header->msgid, header->size); ++ vcos_assert(0); ++ } + } + } + } +@@ -2050,7 +2086,7 @@ + VCHIQ_SERVICE_T *service = (VCHIQ_SERVICE_T *) handle; + VCHIQ_STATUS_T status = VCHIQ_ERROR; + +- if (service == NULL) ++ if (!is_valid_service(service)) + return VCHIQ_ERROR; + + vcos_log_info("%d: close_service:%d", service->state->id, service->localport); +@@ -2080,7 +2116,7 @@ + VCHIQ_SERVICE_T *service = (VCHIQ_SERVICE_T *) handle; + VCHIQ_STATUS_T status = VCHIQ_SUCCESS; + +- if (service == NULL) ++ if (!is_valid_service(service)) + return VCHIQ_ERROR; + + vcos_log_info("%d: remove_service:%d", service->state->id, service->localport); +@@ -2137,15 +2173,14 @@ + const int dir_msgtype = (dir == VCHIQ_BULK_TRANSMIT) ? VCHIQ_MSG_BULK_TX : VCHIQ_MSG_BULK_RX; + VCHIQ_STATUS_T status = VCHIQ_ERROR; + +- if ((service == NULL) || +- ((memhandle == VCHI_MEM_HANDLE_INVALID) && (offset == NULL))) ++ if (!is_valid_service(service) || ++ (service->srvstate != VCHIQ_SRVSTATE_OPEN) || ++ ((memhandle == VCHI_MEM_HANDLE_INVALID) && (offset == NULL)) || ++ (vchiq_check_service(service) != VCHIQ_SUCCESS)) + return VCHIQ_ERROR; + + state = service->state; + +- if (service->srvstate != VCHIQ_SRVSTATE_OPEN) +- return VCHIQ_ERROR; /* Must be connected */ +- + if (vcos_mutex_lock(&service->bulk_mutex) != VCOS_SUCCESS) + return VCHIQ_RETRY; + +@@ -2325,8 +2360,9 @@ + unsigned int size = 0; + unsigned int i; + +- if ((service == NULL) || +- (service->srvstate != VCHIQ_SRVSTATE_OPEN)) ++ if (!is_valid_service(service) || ++ (service->srvstate != VCHIQ_SRVSTATE_OPEN) || ++ (vchiq_check_service(service) != VCHIQ_SUCCESS)) + return VCHIQ_ERROR; + + for (i = 0; i < (unsigned int)count; i++) +@@ -2361,7 +2397,7 @@ + int slot_index; + int msgid; + +- if (service == NULL) ++ if (!is_valid_service(service)) + return; + + state = service->state; +@@ -2418,7 +2454,7 @@ + VCHIQ_SERVICE_T *service = (VCHIQ_SERVICE_T *)handle; + VCHIQ_STATUS_T status = VCHIQ_ERROR; + +- if (service) ++ if (is_valid_service(service)) + { + switch (option) + { +@@ -2427,6 +2463,48 @@ + status = VCHIQ_SUCCESS; + break; + ++ case VCHIQ_SERVICE_OPTION_SLOT_QUOTA: ++ { ++ VCHIQ_SERVICE_QUOTA_T *service_quota = ++ &service->state->service_quotas[service->localport]; ++ if (value == 0) ++ value = service->state->default_slot_quota; ++ if ((value >= service_quota->slot_use_count) && ++ (value < (unsigned short)~0)) ++ { ++ service_quota->slot_quota = value; ++ if ((value >= service_quota->slot_use_count) && ++ (service_quota->message_quota >= service_quota->message_use_count)) ++ { ++ /* Signal the service that it may have dropped below its quota */ ++ vcos_event_signal(&service_quota->quota_event); ++ } ++ status = VCHIQ_SUCCESS; ++ } ++ } ++ break; ++ ++ case VCHIQ_SERVICE_OPTION_MESSAGE_QUOTA: ++ { ++ VCHIQ_SERVICE_QUOTA_T *service_quota = ++ &service->state->service_quotas[service->localport]; ++ if (value == 0) ++ value = service->state->default_message_quota; ++ if ((value >= service_quota->message_use_count) && ++ (value < (unsigned short)~0)) ++ { ++ service_quota->message_quota = value; ++ if ((value >= service_quota->message_use_count) && ++ (service_quota->slot_quota >= service_quota->slot_use_count)) ++ { ++ /* Signal the service that it may have dropped below its quota */ ++ vcos_event_signal(&service_quota->quota_event); ++ } ++ status = VCHIQ_SUCCESS; ++ } ++ } ++ break; ++ + default: + break; + } +@@ -2568,9 +2646,11 @@ + vcos_strcpy(remoteport, "n/a"); + + len += vcos_snprintf(buf + len, sizeof(buf) - len, +- " '%c%c%c%c' remote %s (slot use %d/%d)", ++ " '%c%c%c%c' remote %s (msg use %d/%d, slot use %d/%d)", + VCHIQ_FOURCC_AS_4CHARS(fourcc), + remoteport, ++ service_quota->message_use_count, ++ service_quota->message_quota, + service_quota->slot_use_count, + service_quota->slot_quota); + +@@ -2602,3 +2682,19 @@ + + vchiq_dump_platform_service_state(dump_context, service); + } ++ ++ ++VCHIQ_STATUS_T vchiq_send_remote_use(VCHIQ_STATE_T * state) ++{ ++ return queue_message(state, NULL, VCHIQ_MAKE_MSG(VCHIQ_MSG_REMOTE_USE, 0, 0), NULL, 0, 0, 0); ++} ++ ++VCHIQ_STATUS_T vchiq_send_remote_release(VCHIQ_STATE_T * state) ++{ ++ return queue_message(state, NULL, VCHIQ_MAKE_MSG(VCHIQ_MSG_REMOTE_RELEASE, 0, 0), NULL, 0, 0, 0); ++} ++ ++VCHIQ_STATUS_T vchiq_send_remote_use_active(VCHIQ_STATE_T * state) ++{ ++ return queue_message(state, NULL, VCHIQ_MAKE_MSG(VCHIQ_MSG_REMOTE_USE_ACTIVE, 0, 0), NULL, 0, 0, 0); ++} +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_core.h +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_core.h 2013-07-26 19:32:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_core.h 2013-07-26 19:32:28.000000000 +0000 +@@ -47,6 +47,9 @@ + #define VCHIQ_MSG_BULK_TX_DONE 9 // + (srcport, dstport), actual + #define VCHIQ_MSG_PAUSE 10 // - + #define VCHIQ_MSG_RESUME 11 // - ++#define VCHIQ_MSG_REMOTE_USE 12 // - ++#define VCHIQ_MSG_REMOTE_RELEASE 13 // - ++#define VCHIQ_MSG_REMOTE_USE_ACTIVE 14 // - + + #define VCHIQ_PORT_MAX (VCHIQ_MAX_SERVICES - 1) + #define VCHIQ_PORT_FREE 0x1000 +@@ -194,6 +197,8 @@ + VCOS_EVENT_T * event; + } REMOTE_EVENT_T; + ++typedef struct opaque_platform_state_t* VCHIQ_PLATFORM_STATE_T; ++ + typedef struct vchiq_state_struct VCHIQ_STATE_T; + + typedef struct vchiq_slot_struct { +@@ -253,8 +258,10 @@ + usage is carried over between users of the same port number. + */ + typedef struct vchiq_service_quota_struct { +- int slot_quota; +- int slot_use_count; ++ unsigned short slot_quota; ++ unsigned short slot_use_count; ++ unsigned short message_quota; ++ unsigned short message_use_count; + VCOS_EVENT_T quota_event; + int previous_tx_index; + } VCHIQ_SERVICE_QUOTA_T; +@@ -314,7 +321,8 @@ + VCHIQ_SHARED_STATE_T *remote; + VCHIQ_SLOT_T *slot_data; + +- int default_slot_quota; ++ unsigned short default_slot_quota; ++ unsigned short default_message_quota; + + VCOS_EVENT_T connect; // event indicating connect message received + VCOS_MUTEX_T mutex; // mutex protecting services +@@ -322,7 +330,6 @@ + + VCOS_THREAD_T slot_handler_thread; // processes incoming messages + VCOS_THREAD_T recycle_thread; // processes recycled slots +- VCOS_THREAD_T lp_thread; // processes low priority messages (eg suspend) + + /* Local implementation of the trigger remote event */ + VCOS_EVENT_T trigger_event; +@@ -330,8 +337,6 @@ + /* Local implementation of the recycle remote event */ + VCOS_EVENT_T recycle_event; + +- VCOS_EVENT_T lp_evt; +- + char *tx_data; + char *rx_data; + VCHIQ_SLOT_INFO_T *rx_info; +@@ -340,17 +345,6 @@ + + VCOS_MUTEX_T recycle_mutex; + +- VCOS_MUTEX_T suspend_resume_mutex; +- VCOS_MUTEX_T use_count_mutex; +- +- /* Global use count for videocore. +- * This is equal to the sum of the use counts for all services. When this hits +- * zero the videocore suspend procedure will be initiated. */ +- int videocore_use_count; +- +- /* Flag to indicate whether videocore is currently suspended */ +- int videocore_suspended; +- + /* Indicates the byte position within the stream from where the next message + will be read. The least significant bits are an index into the slot. + The next bits are the index of the slot in remote->slot_queue. */ +@@ -388,6 +382,8 @@ + VCHIQ_SERVICE_T *services[VCHIQ_MAX_SERVICES]; + VCHIQ_SERVICE_QUOTA_T service_quotas[VCHIQ_MAX_SERVICES]; + VCHIQ_SLOT_INFO_T slot_info[VCHIQ_MAX_SLOTS]; ++ ++ VCHIQ_PLATFORM_STATE_T platform_state; + }; + + extern VCHIQ_SLOT_ZERO_T * +@@ -477,4 +473,33 @@ + vchiq_dump_platform_service_state(void *dump_context, + VCHIQ_SERVICE_T *service); + ++extern VCHIQ_STATUS_T ++vchiq_use_service_internal(VCHIQ_SERVICE_T *service); ++ ++extern VCHIQ_STATUS_T ++vchiq_release_service_internal(VCHIQ_SERVICE_T *service); ++ ++extern VCHIQ_STATUS_T ++vchiq_on_remote_use(VCHIQ_STATE_T *state); ++ ++extern VCHIQ_STATUS_T ++vchiq_on_remote_release(VCHIQ_STATE_T *state); ++ ++extern VCHIQ_STATUS_T ++vchiq_platform_init_state(VCHIQ_STATE_T *state); ++ ++extern void ++vchiq_on_remote_use_active(VCHIQ_STATE_T *state); ++ ++extern VCHIQ_STATUS_T ++vchiq_send_remote_use(VCHIQ_STATE_T * state); ++ ++extern VCHIQ_STATUS_T ++vchiq_send_remote_release(VCHIQ_STATE_T * state); ++ ++extern VCHIQ_STATUS_T ++vchiq_send_remote_use_active(VCHIQ_STATE_T * state); ++ ++ ++ + #endif +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_if.h +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_if.h 2013-07-26 19:32:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_if.h 2013-07-26 19:32:28.000000000 +0000 +@@ -55,7 +55,9 @@ + + typedef enum + { +- VCHIQ_SERVICE_OPTION_AUTOCLOSE ++ VCHIQ_SERVICE_OPTION_AUTOCLOSE, ++ VCHIQ_SERVICE_OPTION_SLOT_QUOTA, ++ VCHIQ_SERVICE_OPTION_MESSAGE_QUOTA + } VCHIQ_SERVICE_OPTION_T; + + #ifdef __HIGHC__ +@@ -94,11 +96,11 @@ + } VCHIQ_SERVICE_BASE_T; + + typedef struct vchiq_service_params_struct { +- int fourcc; +- VCHIQ_CALLBACK_T callback; +- void *userdata; +- short version; /* Increment for non-trivial changes */ +- short version_min; /* Update for incompatible changes */ ++ int fourcc; ++ VCHIQ_CALLBACK_T callback; ++ void *userdata; ++ short version; /* Increment for non-trivial changes */ ++ short version_min; /* Update for incompatible changes */ + } VCHIQ_SERVICE_PARAMS_T; + + typedef struct vchiq_config_struct { +@@ -112,6 +114,8 @@ + } VCHIQ_CONFIG_T; + + typedef struct vchiq_instance_struct *VCHIQ_INSTANCE_T; ++typedef void (*VCHIQ_REMOTE_USE_CALLBACK_T)(void* cb_arg); ++ + + extern VCHIQ_STATUS_T vchiq_initialise(VCHIQ_INSTANCE_T *pinstance); + extern VCHIQ_STATUS_T vchiq_shutdown(VCHIQ_INSTANCE_T instance); +@@ -143,6 +147,9 @@ + extern VCHIQ_STATUS_T vchiq_get_config(VCHIQ_INSTANCE_T instance, int config_size, VCHIQ_CONFIG_T *pconfig); + extern VCHIQ_STATUS_T vchiq_set_service_option(VCHIQ_SERVICE_HANDLE_T service, VCHIQ_SERVICE_OPTION_T option, int value); + ++extern VCHIQ_STATUS_T vchiq_remote_use(VCHIQ_INSTANCE_T instance, VCHIQ_REMOTE_USE_CALLBACK_T callback, void* cb_arg); ++extern VCHIQ_STATUS_T vchiq_remote_release(VCHIQ_INSTANCE_T instance); ++ + extern VCHIQ_STATUS_T vchiq_dump_phys_mem( VCHIQ_SERVICE_HANDLE_T service, void *ptr, size_t num_bytes ); + + #endif /* VCHIQ_IF_H */ +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_lib.c +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_lib.c 2013-07-26 19:32:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_lib.c 2013-07-26 19:32:28.000000000 +0000 +@@ -97,6 +97,12 @@ + return (instance == &vchiq_instance) && (instance->initialised > 0); + } + ++static __inline int ++is_valid_service(VCHIQ_SERVICE_T *service) ++{ ++ return ((service != NULL) && (service->fd != VCHIQ_INVALID_HANDLE)); ++} ++ + /* + * VCHIQ API + */ +@@ -318,6 +324,9 @@ + + vcos_log_trace( "%s called service handle = 0x%08x", __func__, (uint32_t)handle ); + ++ if (!is_valid_service(service)) ++ return VCHIQ_ERROR; ++ + RETRY(ret,ioctl(service->fd, VCHIQ_IOC_CLOSE_SERVICE, service->handle)); + + if (ret != 0) +@@ -335,6 +344,9 @@ + + vcos_log_trace( "%s called service handle = 0x%08x", __func__, (uint32_t)handle ); + ++ if (!is_valid_service(service)) ++ return VCHIQ_ERROR; ++ + RETRY(ret,ioctl(service->fd, VCHIQ_IOC_REMOVE_SERVICE, service->handle)); + + if (ret != 0) +@@ -355,6 +367,9 @@ + + vcos_log_trace( "%s called service handle = 0x%08x", __func__, (uint32_t)handle ); + ++ if (!is_valid_service(service)) ++ return VCHIQ_ERROR; ++ + args.handle = service->handle; + args.elements = elements; + args.count = count; +@@ -384,6 +399,9 @@ + + vcos_log_trace( "%s called service handle = 0x%08x", __func__, (uint32_t)handle ); + ++ if (!is_valid_service(service)) ++ return VCHIQ_ERROR; ++ + args.handle = service->handle; + args.data = (void *)data; + args.size = size; +@@ -406,6 +424,9 @@ + + vcos_log_trace( "%s called service handle = 0x%08x", __func__, (uint32_t)handle ); + ++ if (!is_valid_service(service)) ++ return VCHIQ_ERROR; ++ + args.handle = service->handle; + args.data = data; + args.size = size; +@@ -457,6 +478,9 @@ + + vcos_log_trace( "%s called service handle = 0x%08x", __func__, (uint32_t)handle ); + ++ if (!is_valid_service(service)) ++ return VCHIQ_ERROR; ++ + args.handle = service->handle; + args.data = (void *)data; + args.size = size; +@@ -480,6 +504,9 @@ + + vcos_log_trace( "%s called service handle = 0x%08x", __func__, (uint32_t)handle ); + ++ if (!is_valid_service(service)) ++ return VCHIQ_ERROR; ++ + args.handle = service->handle; + args.data = data; + args.size = size; +@@ -521,6 +548,9 @@ + { + VCHIQ_SERVICE_T *service = (VCHIQ_SERVICE_T *)handle; + ++ if (!is_valid_service(service)) ++ return VCHIQ_ERROR; ++ + return ioctl(service->fd, VCHIQ_IOC_GET_CLIENT_ID, service->handle); + } + +@@ -546,10 +576,14 @@ + int32_t + vchiq_use_service( const VCHIQ_SERVICE_HANDLE_T handle ) + { +- VCHIQ_SERVICE_T *service = (VCHIQ_SERVICE_T *)handle; +- int ret; +- RETRY(ret,ioctl(service->fd, VCHIQ_IOC_USE_SERVICE, service->handle)); +- return ret; ++ VCHIQ_SERVICE_T *service = (VCHIQ_SERVICE_T *)handle; ++ int ret; ++ ++ if (!is_valid_service(service)) ++ return VCHIQ_ERROR; ++ ++ RETRY(ret,ioctl(service->fd, VCHIQ_IOC_USE_SERVICE, service->handle)); ++ return ret; + } + + int32_t +@@ -569,6 +603,9 @@ + VCHIQ_SERVICE_T *service = (VCHIQ_SERVICE_T *)handle; + int ret; + ++ if (!is_valid_service(service)) ++ return VCHIQ_ERROR; ++ + args.handle = service->handle; + args.option = option; + args.value = value; +@@ -633,6 +670,9 @@ + VCHI_SERVICE_T *service = (VCHI_SERVICE_T *)handle; + int ret; + ++ if (!is_valid_service(service)) ++ return VCHIQ_ERROR; ++ + ret = fill_peek_buf(service, flags); + + if (ret == 0) +@@ -659,6 +699,9 @@ + { + VCHI_SERVICE_T *service = (VCHI_SERVICE_T *)handle; + ++ if (!is_valid_service(service)) ++ return VCHIQ_ERROR; ++ + /* Why would you call vchi_msg_remove without calling vchi_msg_peek first? */ + vcos_assert(service->peek_size >= 0); + +@@ -697,6 +740,9 @@ + vcos_unused(msg_handle); + vcos_assert(flags == VCHI_FLAGS_BLOCK_UNTIL_QUEUED); + ++ if (!is_valid_service(service)) ++ return VCHIQ_ERROR; ++ + args.handle = service->handle; + args.elements = &element; + args.count = 1; +@@ -730,6 +776,9 @@ + VCHIQ_QUEUE_BULK_TRANSFER_T args; + int ret; + ++ if (!is_valid_service(service)) ++ return VCHIQ_ERROR; ++ + switch ((int)flags) { + case VCHI_FLAGS_CALLBACK_WHEN_OP_COMPLETE | VCHI_FLAGS_BLOCK_UNTIL_QUEUED: + args.mode = VCHIQ_BULK_MODE_CALLBACK; +@@ -780,6 +829,9 @@ + VCHIQ_QUEUE_BULK_TRANSFER_T args; + int ret; + ++ if (!is_valid_service(service)) ++ return VCHIQ_ERROR; ++ + switch ((int)flags) { + case VCHI_FLAGS_CALLBACK_WHEN_OP_COMPLETE | VCHI_FLAGS_BLOCK_UNTIL_QUEUED: + args.mode = VCHIQ_BULK_MODE_CALLBACK; +@@ -833,6 +885,9 @@ + + vcos_assert(flags == VCHI_FLAGS_NONE || flags == VCHI_FLAGS_BLOCK_UNTIL_OP_COMPLETE); + ++ if (!is_valid_service(service)) ++ return VCHIQ_ERROR; ++ + if (service->peek_size >= 0) + { + fprintf(stderr, "vchi_msg_dequeue -> using peek buffer\n"); +@@ -903,6 +958,9 @@ + + vcos_assert(flags == VCHI_FLAGS_BLOCK_UNTIL_QUEUED); + ++ if (!is_valid_service(service)) ++ return VCHIQ_ERROR; ++ + args.handle = service->handle; + args.elements = (const VCHIQ_ELEMENT_T *)vector; + args.count = count; +@@ -961,6 +1019,9 @@ + VCHI_SERVICE_T *service = (VCHI_SERVICE_T *)handle; + int ret; + ++ if (!is_valid_service(service)) ++ return VCHIQ_ERROR; ++ + ret = fill_peek_buf(service, flags); + + if (ret == 0) +@@ -1116,6 +1177,10 @@ + { + VCHI_SERVICE_T *service = (VCHI_SERVICE_T *)handle; + int ret; ++ ++ if (!is_valid_service(service)) ++ return VCHIQ_ERROR; ++ + RETRY(ret,ioctl(service->fd, VCHIQ_IOC_REMOVE_SERVICE, service->handle)); + + if (ret == 0) +@@ -1129,6 +1194,10 @@ + { + VCHI_SERVICE_T *service = (VCHI_SERVICE_T *)handle; + int ret; ++ ++ if (!is_valid_service(service)) ++ return VCHIQ_ERROR; ++ + RETRY(ret,ioctl(service->fd, VCHIQ_IOC_REMOVE_SERVICE, service->handle)); + + if (ret == 0) +@@ -1200,6 +1269,10 @@ + { + VCHI_SERVICE_T *service = (VCHI_SERVICE_T *)handle; + int ret; ++ ++ if (!is_valid_service(service)) ++ return VCHIQ_ERROR; ++ + RETRY(ret,ioctl(service->fd, VCHIQ_IOC_USE_SERVICE, service->handle)); + return ret; + } +@@ -1218,10 +1291,47 @@ + { + VCHI_SERVICE_T *service = (VCHI_SERVICE_T *)handle; + int ret; ++ ++ if (!is_valid_service(service)) ++ return VCHIQ_ERROR; ++ + RETRY(ret,ioctl(service->fd, VCHIQ_IOC_RELEASE_SERVICE, service->handle)); + return ret; + } + ++/*********************************************************** ++ * Name: vchiq_dump_phys_mem ++ * ++ * Arguments: const VCHI_SERVICE_HANDLE_T handle ++ * void *buffer ++ * size_t num_bytes ++ * ++ * Description: Dumps the physical memory associated with ++ * a buffer. ++ * ++ * Returns: void ++ * ++ ***********************************************************/ ++VCHIQ_STATUS_T vchiq_dump_phys_mem( VCHIQ_SERVICE_HANDLE_T handle, ++ void *ptr, ++ size_t num_bytes ) ++{ ++ VCHIQ_SERVICE_T *service = (VCHIQ_SERVICE_T *)handle; ++ VCHIQ_DUMP_MEM_T dump_mem; ++ int ret; ++ ++ if (!is_valid_service(service)) ++ return VCHIQ_ERROR; ++ ++ dump_mem.virt_addr = ptr; ++ dump_mem.num_bytes = num_bytes; ++ ++ RETRY(ret,ioctl(service->fd, VCHIQ_IOC_DUMP_PHYS_MEM, &dump_mem)); ++ return (ret >= 0) ? VCHIQ_SUCCESS : VCHIQ_ERROR; ++} ++ ++ ++ + /* + * Support functions + */ +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_shim.c +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_shim.c 2013-07-26 19:32:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_shim.c 2013-07-26 19:32:28.000000000 +0000 +@@ -859,10 +859,38 @@ + + int32_t vchi_service_close( const VCHI_SERVICE_HANDLE_T handle ) + { +- vcos_unused(handle); ++ int32_t ret = -1; ++ SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle; ++ if(service) ++ { ++ VCHIQ_STATUS_T status = vchiq_close_service(service->handle); ++ if (status == VCHIQ_SUCCESS) ++ { ++ service_free(service); ++ service = NULL; ++ } ++ ++ ret = vchiq_status_to_vchi( status ); ++ } ++ return ret; ++} + +- // YTI?? +- return 0; ++int32_t vchi_service_destroy( const VCHI_SERVICE_HANDLE_T handle ) ++{ ++ int32_t ret = -1; ++ SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle; ++ if(service) ++ { ++ VCHIQ_STATUS_T status = vchiq_remove_service(service->handle); ++ if (status == VCHIQ_SUCCESS) ++ { ++ service_free(service); ++ service = NULL; ++ } ++ ++ ret = vchiq_status_to_vchi( status ); ++ } ++ return ret; + } + + /* ---------------------------------------------------------------------- +@@ -962,9 +990,12 @@ + EXPORT_SYMBOL(vchi_msg_dequeue); + EXPORT_SYMBOL(vchi_msg_queue); + EXPORT_SYMBOL(vchi_msg_queuev); ++EXPORT_SYMBOL(vchi_msg_peek); ++EXPORT_SYMBOL(vchi_msg_remove); + EXPORT_SYMBOL(vchi_service_close); + EXPORT_SYMBOL(vchi_service_open); + EXPORT_SYMBOL(vchi_service_create); ++EXPORT_SYMBOL(vchi_service_destroy); + EXPORT_SYMBOL(vchi_service_use); + EXPORT_SYMBOL(vchi_service_release); + #endif diff -Nru linux-3.2.46/debian/patches/rpi/rpi_120_e81b5a8e4b0cc9e9658562d598572aff538ae407.patch linux-3.2.46/debian/patches/rpi/rpi_120_e81b5a8e4b0cc9e9658562d598572aff538ae407.patch --- linux-3.2.46/debian/patches/rpi/rpi_120_e81b5a8e4b0cc9e9658562d598572aff538ae407.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_120_e81b5a8e4b0cc9e9658562d598572aff538ae407.patch 2013-07-26 19:32:32.000000000 +0000 @@ -0,0 +1,2312 @@ +commit e81b5a8e4b0cc9e9658562d598572aff538ae407 +Author: popcornmix +Date: Mon Mar 26 22:15:50 2012 +0100 + + First pass at alsa sound driver. Some functionality, but also some underruns + +Index: linux-3.2.46/arch/arm/mach-bcm2708/bcm2708.c +=================================================================== +--- linux-3.2.46.orig/arch/arm/mach-bcm2708/bcm2708.c 2013-07-26 19:32:24.000000000 +0000 ++++ linux-3.2.46/arch/arm/mach-bcm2708/bcm2708.c 2013-07-26 19:32:30.000000000 +0000 +@@ -467,6 +467,16 @@ + .coherent_dma_mask = 0xffffffffUL}, + }; + ++ ++static struct platform_device bcm2708_alsa_devices[] = { ++ [0] = { ++ .name = "bcm2835_AUD0", ++ .id = 0, /* first audio device */ ++ .resource = 0, ++ .num_resources = 0, ++ }, ++}; ++ + int __init bcm_register_device(struct platform_device *pdev) + { + int ret; +@@ -503,6 +513,8 @@ + bcm_register_device(&bcm2708_emmc_device); + #endif + bcm2708_init_led(); ++ for (i = 0; i < ARRAY_SIZE(bcm2708_alsa_devices); i++) ++ bcm_register_device(&bcm2708_alsa_devices[i]); + + #ifdef CONFIG_BCM2708_VCMEM + { +Index: linux-3.2.46/sound/arm/Kconfig +=================================================================== +--- linux-3.2.46.orig/sound/arm/Kconfig 2013-05-30 13:35:16.000000000 +0000 ++++ linux-3.2.46/sound/arm/Kconfig 2013-07-26 19:32:31.000000000 +0000 +@@ -39,5 +39,12 @@ + Say Y or M if you want to support any AC97 codec attached to + the PXA2xx AC97 interface. + ++config SND_BCM2835 ++ tristate "BCM2835 ALSA driver" ++ depends on ARCH_BCM2708 && SND ++ select SND_PCM ++ help ++ Say Y or M if you want to support BCM2835 Alsa pcm card driver ++ + endif # SND_ARM + +Index: linux-3.2.46/sound/arm/Makefile +=================================================================== +--- linux-3.2.46.orig/sound/arm/Makefile 2013-05-30 13:35:16.000000000 +0000 ++++ linux-3.2.46/sound/arm/Makefile 2013-07-26 19:32:31.000000000 +0000 +@@ -14,3 +14,9 @@ + + obj-$(CONFIG_SND_PXA2XX_AC97) += snd-pxa2xx-ac97.o + snd-pxa2xx-ac97-objs := pxa2xx-ac97.o ++ ++obj-$(CONFIG_SND_BCM2835) += snd-bcm2835.o ++snd-bcm2835-objs := bcm2835.o bcm2835-ctl.o bcm2835-pcm.o bcm2835-vchiq.o ++ ++EXTRA_CFLAGS += -Idrivers/misc/vc04_services -Idrivers/misc/vc04_services/interface/vcos/linuxkernel ++ +Index: linux-3.2.46/sound/arm/bcm2835-ctl.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/sound/arm/bcm2835-ctl.c 2013-07-26 19:32:31.000000000 +0000 +@@ -0,0 +1,168 @@ ++/***************************************************************************** ++* Copyright 2011 Broadcom Corporation. All rights reserved. ++* ++* Unless you and Broadcom execute a separate written software license ++* agreement governing use of this software, this software is licensed to you ++* under the terms of the GNU General Public License version 2, available at ++* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). ++* ++* Notwithstanding the above, under no circumstances may you combine this ++* software in any way with any other Broadcom software provided under a ++* license other than the GPL, without Broadcom's express prior written ++* consent. ++*****************************************************************************/ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "bcm2835.h" ++ ++static int snd_bcm2835_ctl_info(struct snd_kcontrol * kcontrol, ++ struct snd_ctl_elem_info * uinfo) ++{ ++ if (kcontrol->private_value == PCM_PLAYBACK_VOLUME) { ++ uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; ++ uinfo->count = 1; ++ uinfo->value.integer.min = -10240; ++ uinfo->value.integer.max = 2303; ++ } else if (kcontrol->private_value == PCM_PLAYBACK_MUTE) { ++ uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; ++ uinfo->count = 1; ++ uinfo->value.integer.min = 0; ++ uinfo->value.integer.max = 1; ++ } else if (kcontrol->private_value == PCM_PLAYBACK_DEVICE) { ++ uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; ++ uinfo->count = 1; ++ uinfo->value.integer.min = AUDIO_DEST_LOCAL; ++ uinfo->value.integer.max = AUDIO_DEST_ALL; ++ } ++ ++ return 0; ++} ++ ++static int snd_bcm2835_ctl_get(struct snd_kcontrol * kcontrol, struct snd_ctl_elem_value * ucontrol) ++{ ++ struct bcm2835_chip *chip = snd_kcontrol_chip(kcontrol); ++ ++ BUG_ON(!chip && !(chip->avail_substreams & AVAIL_SUBSTREAMS_MASK)); ++ ++ if (kcontrol->private_value == PCM_PLAYBACK_VOLUME) ++ ucontrol->value.integer.value[0] = chip->volume; ++ else if (kcontrol->private_value == PCM_PLAYBACK_MUTE) ++ ucontrol->value.integer.value[0] = chip->mute; ++ else if (kcontrol->private_value == PCM_PLAYBACK_DEVICE) ++ ucontrol->value.integer.value[0] = chip->dest; ++ ++ return 0; ++} ++ ++static int snd_bcm2835_ctl_put(struct snd_kcontrol * kcontrol, struct snd_ctl_elem_value * ucontrol) ++{ ++ struct bcm2835_chip *chip = snd_kcontrol_chip(kcontrol); ++ int changed = 0; ++ ++ if (kcontrol->private_value == PCM_PLAYBACK_VOLUME) { ++ if (chip->mute) { ++ chip->mute = 0; ++ changed = 1; ++ } ++ if (changed || (ucontrol->value.integer.value[0] != chip->volume)) { ++ int atten; ++ ++ chip->volume = ucontrol->value.integer.value[0]; ++ changed = 1; ++ atten = -((chip->volume << 8) / 100); ++ chip->volume = atten; ++ } ++ ++ } else if (kcontrol->private_value == PCM_PLAYBACK_MUTE) { ++ // Not implemented ++ if (ucontrol->value.integer.value[0] != chip->mute) { ++ chip->mute = ucontrol->value.integer.value[0]; ++ changed = 0; ++ } ++ } else if (kcontrol->private_value == PCM_PLAYBACK_DEVICE) { ++ if (ucontrol->value.integer.value[0] != chip->dest && ucontrol->value.integer.value[0] != 1) { ++ chip->dest= ucontrol->value.integer.value[0]; ++ changed = 1; ++ } ++ } ++ ++ if (changed) { ++ if (bcm2835_audio_set_ctls(chip)) ++ printk(KERN_ERR"Failed to set ALSA controls..\n"); ++ } ++ ++ return changed; ++} ++ ++static DECLARE_TLV_DB_SCALE(snd_bcm2835_db_scale, -10240, 1, 1); ++ ++static struct snd_kcontrol_new snd_bcm2835_ctl[] __devinitdata = ++{ ++ { ++ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, ++ .name = "PCM Playback Volume", ++ .index = 0, ++ .access= SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_TLV_READWRITE, ++ .private_value = PCM_PLAYBACK_VOLUME, ++ .info = snd_bcm2835_ctl_info, ++ .get = snd_bcm2835_ctl_get, ++ .put = snd_bcm2835_ctl_put, ++ .count = 1, ++ .tlv = { .p = snd_bcm2835_db_scale } ++ }, ++ { ++ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, ++ .name = "PCM Playback Switch", ++ .index = 0, ++ .access= SNDRV_CTL_ELEM_ACCESS_READWRITE, ++ .private_value = PCM_PLAYBACK_MUTE, ++ .info = snd_bcm2835_ctl_info, ++ .get = snd_bcm2835_ctl_get, ++ .put = snd_bcm2835_ctl_put, ++ .count = 1, ++ }, ++ { ++ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, ++ .name = "PCM Playback Route", ++ .index = 0, ++ .access= SNDRV_CTL_ELEM_ACCESS_READWRITE, ++ .private_value = PCM_PLAYBACK_DEVICE, ++ .info = snd_bcm2835_ctl_info, ++ .get = snd_bcm2835_ctl_get, ++ .put = snd_bcm2835_ctl_put, ++ .count = 1, ++ }, ++}; ++ ++int __devinit snd_bcm2835_new_ctl(bcm2835_chip_t *chip) ++{ ++ int err; ++ unsigned int idx; ++ ++ strcpy(chip->card->mixername, "Broadcom Mixer"); ++ for (idx = 0; idx < ARRAY_SIZE(snd_bcm2835_ctl); idx++) ++ { ++ err = snd_ctl_add(chip->card, snd_ctl_new1(&snd_bcm2835_ctl[idx], chip)); ++ if (err < 0) ++ return err; ++ } ++ return 0; ++} +Index: linux-3.2.46/sound/arm/bcm2835-pcm.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/sound/arm/bcm2835-pcm.c 2013-07-26 19:32:31.000000000 +0000 +@@ -0,0 +1,391 @@ ++/***************************************************************************** ++* Copyright 2011 Broadcom Corporation. All rights reserved. ++* ++* Unless you and Broadcom execute a separate written software license ++* agreement governing use of this software, this software is licensed to you ++* under the terms of the GNU General Public License version 2, available at ++* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). ++* ++* Notwithstanding the above, under no circumstances may you combine this ++* software in any way with any other Broadcom software provided under a ++* license other than the GPL, without Broadcom's express prior written ++* consent. ++*****************************************************************************/ ++ ++#include ++#include ++ ++#include "bcm2835.h" ++ ++/* hardware definition */ ++static struct snd_pcm_hardware snd_bcm2835_playback_hw = { ++ .info = ( SNDRV_PCM_INFO_INTERLEAVED | ++ SNDRV_PCM_INFO_BLOCK_TRANSFER ), ++ .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE, ++ .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000, ++ .rate_min = 8000, ++ .rate_max = 48000, ++ .channels_min = 1, ++ .channels_max = 2, ++ .buffer_bytes_max = (4*8-1)*1024, /* Needs to be less than audioplay buffer size */ ++ .period_bytes_min = 1*1024, ++ .period_bytes_max = (4*8-1)*1024, ++ .periods_min = 1, ++ .periods_max = 4*8-1, ++}; ++ ++ ++static void snd_bcm2835_playback_free(struct snd_pcm_runtime *runtime) ++{ ++ audio_info("Freeing up alsa stream here ..\n"); ++ if (runtime->private_data) ++ kfree(runtime->private_data); ++ runtime->private_data = NULL; ++} ++ ++static irqreturn_t bcm2835_playback_fifo_irq(int irq, void *dev_id) ++{ ++ bcm2835_alsa_stream_t *alsa_stream = (bcm2835_alsa_stream_t *)dev_id; ++ uint32_t consumed = 0; ++ int new_period = 0; ++ ++ audio_debug(" .. IN\n"); ++ ++ audio_info("alsa_stream=%p substream=%p\n", alsa_stream, alsa_stream ? alsa_stream->substream:0); ++ ++ if (alsa_stream->open) ++ consumed = bcm2835_audio_retrieve_buffers(alsa_stream); ++ ++ /* We get called only if playback was triggered, So, the number of buffers we retrieve in ++ * each iteration are the buffers that have been played out already ++ */ ++ ++ if (alsa_stream->period_size) { ++ if ((alsa_stream->pos / alsa_stream->period_size) != ((alsa_stream->pos+consumed) / alsa_stream->period_size)) ++ new_period = 1; ++ } ++ audio_warning("updating pos cur: %d + %d max:%d new_period:%d\n", alsa_stream->pos, ++ (consumed /** AUDIO_IPC_BLOCK_BUFFER_SIZE*/), alsa_stream->buffer_size, new_period); ++ if (alsa_stream->buffer_size) { ++ alsa_stream->pos += consumed; ++ alsa_stream->pos %= alsa_stream->buffer_size; ++ } ++ if (alsa_stream->substream) { ++ if (new_period) ++ snd_pcm_period_elapsed(alsa_stream->substream); ++ } else { ++ audio_debug(" unexpected NULL substream\n"); ++ } ++ audio_debug(" .. OUT\n"); ++ ++ return IRQ_HANDLED; ++} ++ ++/* open callback */ ++static int snd_bcm2835_playback_open(struct snd_pcm_substream *substream) ++{ ++ bcm2835_chip_t *chip = snd_pcm_substream_chip(substream); ++ struct snd_pcm_runtime *runtime = substream->runtime; ++ bcm2835_alsa_stream_t *alsa_stream; ++ int idx; ++ int err; ++ ++ audio_info(" .. IN (%d)\n", substream->number); ++ ++ audio_warning(" .. open (%d)\n", substream->number); ++ idx = substream->number; ++ ++ if (idx > MAX_SUBSTREAMS) { ++ audio_error("substream(%d) device doesn't exist max(%d) substreams allowed\n", idx, MAX_SUBSTREAMS); ++ err = -ENODEV; ++ goto out; ++ } ++ ++ /* Check if we are ready */ ++ if (!(chip->avail_substreams & (1 << idx))) { ++ /* We are not ready yet */ ++ audio_error("substream(%d) device is not ready yet\n", idx); ++ err = -EAGAIN; ++ goto out; ++ } ++ ++ alsa_stream = kzalloc(sizeof(bcm2835_alsa_stream_t), GFP_KERNEL); ++ if (alsa_stream == NULL) { ++ return -ENOMEM; ++ } ++ ++ /* Initialise alsa_stream */ ++ alsa_stream->chip = chip; ++ alsa_stream->substream = substream; ++ chip->alsa_stream[idx] = alsa_stream; ++ ++ sema_init(&alsa_stream->buffers_update_sem, 0); ++ sema_init(&alsa_stream->control_sem, 0); ++ spin_lock_init(&alsa_stream->lock); ++ ++ /* Enabled in start trigger, called on each "fifo irq" after that */ ++ alsa_stream->enable_fifo_irq = 0; ++ alsa_stream->fifo_irq_handler = bcm2835_playback_fifo_irq; ++ ++ runtime->private_data = alsa_stream; ++ runtime->private_free = snd_bcm2835_playback_free; ++ runtime->hw = snd_bcm2835_playback_hw; ++ ++ /* minimum 16 bytes alignment (for vchiq bulk transfers) */ ++ snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 16); ++ ++ err = bcm2835_audio_open(alsa_stream); ++ if (err != 0) { ++ kfree(alsa_stream); ++ return err; ++ } ++ ++ alsa_stream->open = 1; ++ alsa_stream->draining = 1; ++ ++out: ++ audio_debug(" .. OUT =%d\n", err); ++ ++ return err; ++} ++ ++/* close callback */ ++static int snd_bcm2835_playback_close(struct snd_pcm_substream *substream) ++{ ++ /* the hardware-specific codes will be here */ ++ ++ struct snd_pcm_runtime *runtime = substream->runtime; ++ bcm2835_alsa_stream_t *alsa_stream = runtime->private_data; ++ ++ audio_debug(" .. IN\n"); ++ audio_warning("Alsa close\n"); ++ ++ /* ++ * Call stop if it's still running. This happens when app ++ * is force killed and we don't get a stop trigger. ++ */ ++ if (alsa_stream->running) { ++ int err; ++ err = bcm2835_audio_stop(alsa_stream); ++ alsa_stream->running = 0; ++ if (err != 0) ++ audio_error(" Failed to STOP alsa device\n"); ++ } ++ ++ alsa_stream->period_size = 0; ++ alsa_stream->buffer_size = 0; ++ ++ if (alsa_stream->open) { ++ alsa_stream->open = 0; ++ bcm2835_audio_close(alsa_stream); ++ } ++ ++ /* ++ * Do not free up alsa_stream here, it will be freed up by ++ * runtime->private_free callback we registered in *_open above ++ */ ++ ++ audio_debug(" .. OUT\n"); ++ ++ return 0; ++} ++ ++/* hw_params callback */ ++static int snd_bcm2835_pcm_hw_params(struct snd_pcm_substream *substream, ++ struct snd_pcm_hw_params *params) ++{ ++ int err; ++ struct snd_pcm_runtime *runtime = substream->runtime; ++ bcm2835_alsa_stream_t *alsa_stream = (bcm2835_alsa_stream_t *)runtime->private_data; ++ ++ audio_debug(" .. IN\n"); ++ ++ err = snd_pcm_lib_malloc_pages(substream, ++ params_buffer_bytes(params)); ++ if (err < 0) { ++ audio_error(" pcm_lib_malloc failed to allocated pages for buffers\n"); ++ return err; ++ } ++ ++ err = bcm2835_audio_set_params(alsa_stream, params_channels(params), ++ params_rate(params), snd_pcm_format_width(params_format(params))); ++ if (err < 0) { ++ audio_error(" error setting hw params\n"); ++ } ++ ++ bcm2835_audio_setup(alsa_stream); ++ audio_debug(" .. OUT\n"); ++ ++ return err; ++} ++ ++/* hw_free callback */ ++static int snd_bcm2835_pcm_hw_free(struct snd_pcm_substream *substream) ++{ ++ audio_debug(" .. IN\n"); ++ return snd_pcm_lib_free_pages(substream); ++} ++ ++/* prepare callback */ ++static int snd_bcm2835_pcm_prepare(struct snd_pcm_substream *substream) ++{ ++ struct snd_pcm_runtime *runtime = substream->runtime; ++ bcm2835_alsa_stream_t *alsa_stream = runtime->private_data; ++ ++ audio_debug(" .. IN\n"); ++ ++ alsa_stream->buffer_size = snd_pcm_lib_buffer_bytes(substream); ++ alsa_stream->period_size = snd_pcm_lib_period_bytes(substream); ++ alsa_stream->pos = 0; ++ ++ audio_warning("buffer_size=%d, period_size=%d pos=%d frame_bits=%d\n", alsa_stream->buffer_size, alsa_stream->period_size, alsa_stream->pos, runtime->frame_bits); ++ ++ audio_debug(" .. OUT\n"); ++ return 0; ++} ++ ++/* trigger callback */ ++static int snd_bcm2835_pcm_trigger(struct snd_pcm_substream *substream, int cmd) ++{ ++ struct snd_pcm_runtime *runtime = substream->runtime; ++ bcm2835_alsa_stream_t *alsa_stream = runtime->private_data; ++ int err = 0; ++ ++ audio_debug(" .. IN\n"); ++ ++ switch (cmd) { ++ case SNDRV_PCM_TRIGGER_START: ++ audio_warning("bcm2835_AUDIO_TRIGGER_START running=%d\n", alsa_stream->running); ++ if (!alsa_stream->running) { ++ err = bcm2835_audio_start(alsa_stream); ++ if (err == 0) ++ { ++ alsa_stream->running = 1; ++ alsa_stream->draining = 1; ++ } ++ } ++ break; ++ case SNDRV_PCM_TRIGGER_STOP: ++ audio_warning("bcm2835_AUDIO_TRIGGER_STOP running=%d draining=%d\n", runtime->status->state==SNDRV_PCM_STATE_DRAINING, alsa_stream->running); ++ if (runtime->status->state==SNDRV_PCM_STATE_DRAINING) ++ { ++ audio_info("DRAINING\n"); ++ alsa_stream->draining = 1; ++ } ++ else ++ { ++ audio_info("DROPPING\n"); ++ alsa_stream->draining=0; ++ } ++ if (alsa_stream->running) { ++ err = bcm2835_audio_stop(alsa_stream); ++ if (err != 0) ++ audio_error(" Failed to STOP alsa device\n"); ++ alsa_stream->running = 0; ++ } ++ break; ++ default: ++ err = -EINVAL; ++ } ++ ++ audio_debug(" .. OUT\n"); ++ return err; ++} ++ ++/* pointer callback */ ++static snd_pcm_uframes_t ++snd_bcm2835_pcm_pointer(struct snd_pcm_substream *substream) ++{ ++ struct snd_pcm_runtime *runtime = substream->runtime; ++ bcm2835_alsa_stream_t *alsa_stream = runtime->private_data; ++ ++ audio_debug(" .. IN\n"); ++ ++ audio_warning("pcm_pointer... (%d) hwptr=%d appl=%d pos=%d\n", 0, ++ frames_to_bytes(runtime, runtime->status->hw_ptr), frames_to_bytes(runtime, runtime->control->appl_ptr), alsa_stream->pos); ++ ++ audio_debug(" .. OUT\n"); ++ return bytes_to_frames(runtime, alsa_stream->pos); ++} ++ ++static int snd_bcm2835_pcm_copy(struct snd_pcm_substream *substream, int channel, ++ snd_pcm_uframes_t pos, void *src, snd_pcm_uframes_t count) ++{ ++ int ret; ++ struct snd_pcm_runtime *runtime = substream->runtime; ++ bcm2835_alsa_stream_t *alsa_stream = runtime->private_data; ++ ++ audio_debug(" .. IN\n"); ++ audio_warning("copy.......... (%d) hwptr=%d appl=%d pos=%d\n", frames_to_bytes(runtime, count), ++ frames_to_bytes(runtime, runtime->status->hw_ptr), frames_to_bytes(runtime, runtime->control->appl_ptr), alsa_stream->pos); ++ ret = bcm2835_audio_write(alsa_stream, frames_to_bytes(runtime, count), src); ++ audio_debug(" .. OUT\n"); ++ return ret; ++} ++ ++static int snd_bcm2835_pcm_silence(struct snd_pcm_substream *substream, int channel, ++ snd_pcm_uframes_t post, snd_pcm_uframes_t count) ++{ ++ int ret; ++ struct snd_pcm_runtime *runtime = substream->runtime; ++ bcm2835_alsa_stream_t *alsa_stream = runtime->private_data; ++ ++ audio_debug(" .. IN\n"); ++ audio_warning("silence....... (%d) hwptr=%d appl=%d pos=%d\n", frames_to_bytes(runtime, count), ++ frames_to_bytes(runtime, runtime->status->hw_ptr), frames_to_bytes(runtime, runtime->control->appl_ptr), alsa_stream->pos); ++ ret = bcm2835_audio_write(alsa_stream, frames_to_bytes(runtime, count), NULL); ++ audio_debug(" .. OUT\n"); ++ return ret; ++} ++ ++static int snd_bcm2835_pcm_lib_ioctl ( struct snd_pcm_substream * substream, unsigned int cmd, void * arg) ++{ ++ int ret = snd_pcm_lib_ioctl(substream, cmd, arg); ++ audio_debug(" .. substream=%p, cmd=%d, arg=%p (%x) ret=%d\n", substream, cmd, arg, arg ? *(unsigned *)arg:0, ret); ++ return ret; ++} ++ ++/* operators */ ++static struct snd_pcm_ops snd_bcm2835_playback_ops = { ++ .open = snd_bcm2835_playback_open, ++ .close = snd_bcm2835_playback_close, ++ .ioctl = snd_bcm2835_pcm_lib_ioctl, ++ .hw_params = snd_bcm2835_pcm_hw_params, ++ .hw_free = snd_bcm2835_pcm_hw_free, ++ .prepare = snd_bcm2835_pcm_prepare, ++ .trigger = snd_bcm2835_pcm_trigger, ++ .pointer = snd_bcm2835_pcm_pointer, ++ .copy = snd_bcm2835_pcm_copy, ++ .silence = snd_bcm2835_pcm_silence, ++}; ++ ++/* create a pcm device */ ++int __devinit snd_bcm2835_new_pcm(bcm2835_chip_t *chip) ++{ ++ struct snd_pcm *pcm; ++ int err; ++ ++ audio_debug(" .. IN\n"); ++ err = snd_pcm_new(chip->card, "bcm2835 ALSA", 0, MAX_SUBSTREAMS, 0, &pcm); ++ if (err < 0) ++ return err; ++ pcm->private_data = chip; ++ strcpy(pcm->name, "bcm2835 ALSA"); ++ chip->pcm = pcm; ++ chip->dest = AUDIO_DEST_LOCAL; ++ chip->volume = 100; ++ /* set operators */ ++ snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, ++ &snd_bcm2835_playback_ops); ++ ++ /* pre-allocation of buffers */ ++ /* NOTE: this may fail */ ++ snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_CONTINUOUS, ++ snd_dma_continuous_data(GFP_KERNEL), 64*1024, 64*1024); ++ ++ audio_debug(" .. OUT\n"); ++ ++ return 0; ++} ++ ++ +Index: linux-3.2.46/sound/arm/bcm2835-vchiq.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/sound/arm/bcm2835-vchiq.c 2013-07-26 19:32:31.000000000 +0000 +@@ -0,0 +1,863 @@ ++/***************************************************************************** ++* Copyright 2011 Broadcom Corporation. All rights reserved. ++* ++* Unless you and Broadcom execute a separate written software license ++* agreement governing use of this software, this software is licensed to you ++* under the terms of the GNU General Public License version 2, available at ++* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). ++* ++* Notwithstanding the above, under no circumstances may you combine this ++* software in any way with any other Broadcom software provided under a ++* license other than the GPL, without Broadcom's express prior written ++* consent. ++*****************************************************************************/ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "bcm2835.h" ++ ++ ++// ---- Include Files -------------------------------------------------------- ++ ++#include "interface/vchi/vchi.h" ++#include "interface/vcos/vcos.h" ++#include "interface/vcos/vcos_logging.h" ++#include "vc_vchi_audioserv_defs.h" ++ ++// ---- Private Constants and Types ------------------------------------------ ++ ++// VCOS logging category for this service ++#define VCOS_LOG_CATEGORY (&audio_log_category) ++ ++// Default VCOS logging level ++#define LOG_LEVEL VCOS_LOG_TRACE ++ ++// Logging macros (for remapping to other logging mechanisms, i.e., printf) ++#define LOG_ERR( fmt, arg... ) pr_err(fmt, ##arg) //vcos_log_error( fmt, ##arg ) ++#define LOG_WARN( fmt, arg... ) pr_err(fmt, ##arg) //vcos_log_warn( fmt, ##arg ) ++#define LOG_INFO( fmt, arg... ) pr_err(fmt, ##arg) //vcos_log_info( fmt, ##arg ) ++#define LOG_DBG( fmt, arg... ) pr_err( fmt, ##arg ) ++ ++typedef struct opaque_AUDIO_INSTANCE_T { ++ uint32_t num_connections; ++ VCHI_SERVICE_HANDLE_T vchi_handle[VCHI_MAX_NUM_CONNECTIONS]; ++ VCOS_EVENT_T msg_avail_event; ++ VCOS_MUTEX_T vchi_mutex; ++ bcm2835_alsa_stream_t *alsa_stream; ++ int32_t result, got_result; ++ atomic_t callbacks_expected, callbacks_received; ++} AUDIO_INSTANCE_T; ++ ++// ---- Private Variables ---------------------------------------------------- ++ ++// VCOS logging category for this service ++static VCOS_LOG_CAT_T audio_log_category; ++ ++// ---- Private Function Prototypes ------------------------------------------ ++ ++// ---- Private Functions ---------------------------------------------------- ++ ++static int bcm2835_audio_stop_worker(bcm2835_alsa_stream_t * alsa_stream); ++static int bcm2835_audio_start_worker(bcm2835_alsa_stream_t * alsa_stream); ++ ++#if 1 ++typedef struct { ++ struct work_struct my_work; ++ bcm2835_alsa_stream_t *alsa_stream; ++ int x; ++} my_work_t; ++ ++static void my_wq_function( struct work_struct *work) ++{ ++ my_work_t *w = (my_work_t *)work; ++ int ret=-9; ++ audio_debug(" .. IN %p:%d\n", w->alsa_stream, w->x); ++ switch (w->x) { ++ case 1: ret=bcm2835_audio_start_worker(w->alsa_stream); break; ++ case 2: ret=bcm2835_audio_stop_worker(w->alsa_stream); break; ++ default: audio_error(" Unexpected work: %p:%d\n", w->alsa_stream, w->x); break; ++ } ++ kfree( (void *)work ); ++ audio_debug(" .. OUT %d\n", ret); ++} ++ ++int bcm2835_audio_start(bcm2835_alsa_stream_t *alsa_stream) ++{ ++ int ret = -1; ++ audio_debug(" .. IN\n"); ++ if (alsa_stream->my_wq) { ++ my_work_t *work = kmalloc(sizeof(my_work_t), GFP_KERNEL); ++ /* Queue some work (item 1) */ ++ if (work) { ++ INIT_WORK( (struct work_struct *)work, my_wq_function ); ++ work->alsa_stream = alsa_stream; ++ work->x = 1; ++ if (queue_work( alsa_stream->my_wq, (struct work_struct *)work )) ++ ret = 0; ++ } else ++ audio_error(" .. Error: NULL work kmalloc\n"); ++ } ++ audio_debug(" .. OUT %d\n", ret); ++ return ret; ++} ++ ++int bcm2835_audio_stop(bcm2835_alsa_stream_t * alsa_stream) ++{ ++ int ret = -1; ++ audio_debug(" .. IN\n"); ++ if (alsa_stream->my_wq) { ++ my_work_t *work = kmalloc(sizeof(my_work_t), GFP_KERNEL); ++ /* Queue some work (item 1) */ ++ if (work) { ++ INIT_WORK( (struct work_struct *)work, my_wq_function ); ++ work->alsa_stream = alsa_stream; ++ work->x = 2; ++ if (queue_work( alsa_stream->my_wq, (struct work_struct *)work )) ++ ret = 0; ++ } else ++ audio_error(" .. Error: NULL work kmalloc\n"); ++ } ++ audio_debug(" .. OUT %d\n", ret); ++ return ret; ++} ++ ++void my_workqueue_init(bcm2835_alsa_stream_t * alsa_stream) ++{ ++ alsa_stream->my_wq = create_workqueue("my_queue"); ++} ++ ++void my_workqueue_quit(bcm2835_alsa_stream_t * alsa_stream) ++{ ++ if (alsa_stream->my_wq) { ++ flush_workqueue( alsa_stream->my_wq ); ++ destroy_workqueue( alsa_stream->my_wq ); ++ alsa_stream->my_wq = NULL; ++ } ++} ++ ++#else ++static void *my_tasklet_data; ++ ++/* Bottom Half Function */ ++void my_tasklet_function( unsigned long data ) ++{ ++ int err = 0; ++ bcm2835_alsa_stream_t *alsa_stream = (bcm2835_alsa_stream_t *)my_tasklet_data; ++ audio_info("IN ..(%d)\n", (int)data); ++ if (data) ++ err = bcm2835_audio_stop_worker(alsa_stream); ++ else ++ err = bcm2835_audio_start_worker(alsa_stream); ++ if (err != 0) ++ audio_error(" Failed to START/STOP alsa device\n"); ++ audio_info("OUT ..\n"); ++} ++ ++DECLARE_TASKLET( my_tasklet_start, my_tasklet_function, 0); ++DECLARE_TASKLET( my_tasklet_stop, my_tasklet_function, 1); ++ ++ ++int bcm2835_audio_start(bcm2835_alsa_stream_t * alsa_stream) ++{ ++ my_tasklet_data = alsa_stream; ++ tasklet_schedule( &my_tasklet_stop ); ++ ++} ++int bcm2835_audio_stop(bcm2835_alsa_stream_t * alsa_stream) ++{ ++ my_tasklet_data = alsa_stream; ++ tasklet_schedule( &my_tasklet_start ); ++} ++void my_workqueue_init(bcm2835_alsa_stream_t * alsa_stream){} ++void my_workqueue_quit(bcm2835_alsa_stream_t * alsa_stream){} ++ ++#endif ++static void audio_vchi_callback(void *param, ++ const VCHI_CALLBACK_REASON_T reason, ++ void *msg_handle) ++{ ++ AUDIO_INSTANCE_T *instance = (AUDIO_INSTANCE_T *)param; ++ int32_t status; ++ int32_t msg_len; ++ VC_AUDIO_MSG_T m; ++ bcm2835_alsa_stream_t *alsa_stream = 0; ++ audio_debug(" .. IN instance=%p, param=%p, reason=%d, handle=%p outstanding_completes=%d\n", instance, param, reason, msg_handle, atomic_read(&instance->callbacks_expected)-atomic_read(&instance->callbacks_received)); ++ ++ if (!instance || reason != VCHI_CALLBACK_MSG_AVAILABLE) { ++ return; ++ } ++ alsa_stream = instance->alsa_stream; ++ status = vchi_msg_dequeue(instance->vchi_handle[0], ++ &m, sizeof m, &msg_len, VCHI_FLAGS_NONE); ++ if (m.type == VC_AUDIO_MSG_TYPE_RESULT) { ++ audio_debug(" .. instance=%p, m.type=VC_AUDIO_MSG_TYPE_RESULT, success=%d\n", instance, m.u.result.success); ++ BUG_ON(instance->got_result); ++ instance->result = m.u.result.success; ++ instance->got_result = 1; ++ vcos_event_signal(&instance->msg_avail_event); ++ } else if (m.type == VC_AUDIO_MSG_TYPE_COMPLETE) { ++ irq_handler_t callback = (irq_handler_t)m.u.complete.callback; ++ audio_debug(" .. instance=%p, m.type=VC_AUDIO_MSG_TYPE_COMPLETE, complete=%d\n", instance, m.u.complete.count); ++ if (alsa_stream && callback) { ++ atomic_add(m.u.complete.count, &alsa_stream->retrieved); ++ callback(0, alsa_stream); ++ } else { ++ audio_debug(" .. unexpected alsa_stream=%p, callback=%p\n", alsa_stream, callback); ++ } ++ atomic_inc(&instance->callbacks_received); ++ //BUG_ON(atomic_read(&instance->callbacks_expected)-atomic_read(&instance->callbacks_received) < 0); ++ vcos_event_signal(&instance->msg_avail_event); ++ } else { ++ audio_debug(" .. unexpected m.type=%d\n", m.type); ++ } ++} ++ ++static AUDIO_INSTANCE_T *vc_vchi_audio_init(VCHI_INSTANCE_T vchi_instance, ++ VCHI_CONNECTION_T ** vchi_connections, ++ uint32_t num_connections) ++{ ++ uint32_t i; ++ AUDIO_INSTANCE_T *instance; ++ VCOS_STATUS_T status; ++ ++ LOG_DBG("%s: start", __func__); ++ ++ if (num_connections > VCHI_MAX_NUM_CONNECTIONS) { ++ LOG_ERR("%s: unsupported number of connections %u (max=%u)", ++ __func__, num_connections, VCHI_MAX_NUM_CONNECTIONS); ++ ++ return NULL; ++ } ++ // Allocate memory for this instance ++ instance = vcos_malloc(sizeof(*instance), "audio_instance"); ++ memset(instance, 0, sizeof(*instance)); ++ ++ instance->num_connections = num_connections; ++ // Create the message available event ++ status = ++ vcos_event_create(&instance->msg_avail_event, "audio_msg_avail"); ++ if (status != VCOS_SUCCESS) { ++ LOG_ERR("%s: failed to create event (status=%d)", __func__, ++ status); ++ ++ goto err_free_mem; ++ } ++ // Create a lock for exclusive, serialized VCHI connection access ++ status = vcos_mutex_create(&instance->vchi_mutex, "audio_vchi_mutex"); ++ if (status != VCOS_SUCCESS) { ++ LOG_ERR("%s: failed to create event (status=%d)", __func__, ++ status); ++ ++ goto err_delete_event; ++ } ++ // Open the VCHI service connections ++ for (i = 0; i < num_connections; i++) { ++ SERVICE_CREATION_T params = { ++ VC_AUDIO_SERVER_NAME, // 4cc service code ++ vchi_connections[i], // passed in fn pointers ++ 0, // rx fifo size (unused) ++ 0, // tx fifo size (unused) ++ audio_vchi_callback, // service callback ++ instance, // service callback parameter ++ VCOS_TRUE, //TODO: remove VCOS_FALSE, // unaligned bulk recieves ++ VCOS_TRUE, //TODO: remove VCOS_FALSE, // unaligned bulk transmits ++ VCOS_FALSE // want crc check on bulk transfers ++ }; ++ ++ status = vchi_service_open(vchi_instance, ¶ms, ++ &instance->vchi_handle[i]); ++ if (status != VCOS_SUCCESS) { ++ LOG_ERR ++ ("%s: failed to open VCHI service connection (status=%d)", ++ __func__, status); ++ ++ goto err_close_services; ++ } ++ // Finished with the service for now ++ vchi_service_release(instance->vchi_handle[i]); ++ } ++ ++ return instance; ++ ++err_close_services: ++ for (i = 0; i < instance->num_connections; i++) { ++ vchi_service_close(instance->vchi_handle[i]); ++ } ++ ++ vcos_mutex_delete(&instance->vchi_mutex); ++ ++err_delete_event: ++ vcos_event_delete(&instance->msg_avail_event); ++ ++err_free_mem: ++ vcos_free(instance); ++ ++ return NULL; ++} ++ ++static int32_t vc_vchi_audio_deinit(AUDIO_INSTANCE_T *instance) ++{ ++ uint32_t i; ++ ++ audio_debug(" .. IN\n"); ++ ++ if (instance == NULL) { ++ LOG_ERR("%s: invalid handle %p", __func__, instance); ++ ++ return -1; ++ } ++ ++ audio_debug(" .. about to lock (%d)\n", instance->num_connections); ++ vcos_mutex_lock(&instance->vchi_mutex); ++ ++ // Close all VCHI service connections ++ for (i = 0; i < instance->num_connections; i++) { ++ int32_t success; ++ audio_debug(" .. %i:closing %p\n", i, instance->vchi_handle[i]); ++ vchi_service_use(instance->vchi_handle[i]); ++ ++ success = vchi_service_close(instance->vchi_handle[i]); ++ if (success != 0) { ++ LOG_ERR ++ ("%s: failed to close VCHI service connection (status=%d)", ++ __func__, success); ++ } ++ } ++ ++ vcos_mutex_unlock(&instance->vchi_mutex); ++ ++ vcos_mutex_delete(&instance->vchi_mutex); ++ ++ vcos_event_delete(&instance->msg_avail_event); ++ ++ vcos_free(instance); ++ ++ // Unregister the log category so we can add it back next time ++ vcos_log_unregister(&audio_log_category); ++ ++ audio_debug(" .. OUT\n"); ++ ++ return 0; ++} ++ ++static int bcm2835_audio_open_connection(bcm2835_alsa_stream_t * alsa_stream) ++{ ++ int ret = 0, err; ++ static VCHI_INSTANCE_T vchi_instance; ++ static VCHI_CONNECTION_T *vchi_connection; ++ AUDIO_INSTANCE_T *instance = alsa_stream->instance; ++ audio_debug(" .. IN\n"); ++ ++ LOG_INFO("%s: start", __func__); ++ //BUG_ON(instance); ++ if (instance) { ++ LOG_ERR("%s: VCHI instance already open (%p)", ++ __func__, instance); ++ //BUG_ON(atomic_read(&instance->callbacks_expected)-atomic_read(&instance->callbacks_received) < 0); ++ instance->alsa_stream = alsa_stream; ++ alsa_stream->instance = instance; ++ ret = 0; // xxx todo -1; ++ goto err_free_mem; ++ } ++ ++ // Initialize and create a VCHI connection ++ ret = vchi_initialise(&vchi_instance); ++ if (ret != 0) { ++ LOG_ERR("%s: failed to initialise VCHI instance (ret=%d)", ++ __func__, ret); ++ ++ ret = -EIO; ++ goto err_free_mem; ++ } ++ ret = vchi_connect(NULL, 0, vchi_instance); ++ if (ret != 0) { ++ LOG_ERR("%s: failed to connect VCHI instance (ret=%d)", ++ __func__, ret); ++ ++ ret = -EIO; ++ goto err_free_mem; ++ } ++ ++ // Set up the VCOS logging ++ vcos_log_set_level(VCOS_LOG_CATEGORY, LOG_LEVEL); ++ vcos_log_register("audio", VCOS_LOG_CATEGORY); ++ ++ ++ // Initialize an instance of the audio service ++ instance = vc_vchi_audio_init(vchi_instance, &vchi_connection, 1); ++ ++ if (instance == NULL /*|| audio_handle != instance*/) { ++ LOG_ERR("%s: failed to initialize audio service", ++ __func__); ++ ++ ret = -EPERM; ++ goto err_free_mem; ++ } ++ ++ instance->alsa_stream = alsa_stream; ++ alsa_stream->instance = instance; ++ ++ ++ audio_debug(" success !\n"); ++err_free_mem: ++ audio_debug(" .. OUT\n"); ++ ++ return ret; ++} ++ ++int bcm2835_audio_open(bcm2835_alsa_stream_t * alsa_stream) ++{ ++ AUDIO_INSTANCE_T *instance; ++ VC_AUDIO_MSG_T m; ++ int32_t success; ++ int ret; ++ audio_debug(" .. IN\n"); ++ ++ my_workqueue_init(alsa_stream); ++ ++ ret = bcm2835_audio_open_connection(alsa_stream); ++ if (ret != 0) { ++ ret = -1; ++ goto exit; ++ } ++ instance = alsa_stream->instance; ++ ++ vcos_mutex_lock(&instance->vchi_mutex); ++ vchi_service_use(instance->vchi_handle[0]); ++ ++ m.type = VC_AUDIO_MSG_TYPE_OPEN; ++ ++ // Send the message to the videocore ++ success = vchi_msg_queue(instance->vchi_handle[0], ++ &m, sizeof m, ++ VCHI_FLAGS_BLOCK_UNTIL_QUEUED, NULL); ++ ++ if (success != 0) { ++ LOG_ERR("%s: failed on vchi_msg_queue (status=%d)", ++ __func__, success); ++ ++ ret = -1; ++ goto unlock; ++ } ++ ++ ret = 0; ++ ++unlock: ++ vchi_service_release(instance->vchi_handle[0]); ++ vcos_mutex_unlock(&instance->vchi_mutex); ++exit: ++ audio_debug(" .. OUT\n"); ++ return ret; ++} ++ ++ ++int bcm2835_audio_set_params(bcm2835_alsa_stream_t * alsa_stream, ++ uint32_t channels, uint32_t samplerate, ++ uint32_t bps) ++{ ++ VC_AUDIO_MSG_T m; ++ AUDIO_INSTANCE_T *instance = alsa_stream->instance; ++ int32_t success; ++ uint32_t msg_len; ++ int ret; ++ audio_debug(" .. IN\n"); ++ ++ if (channels < 1 || channels > 2) { ++ audio_error(" channels (%d) not supported\n", channels); ++ return -EINVAL; ++ } ++ ++ if (samplerate < 8000 || samplerate > 48000) { ++ audio_error(" samplerate (%d) not supported\n", samplerate); ++ return -EINVAL; ++ } ++ ++ if (bps != 8 && bps != 16) { ++ audio_error(" Bits per sample (%d) not supported\n", bps); ++ return -EINVAL; ++ } ++ ++ audio_info ++ (" Setting ALSA channels(%d), samplerate(%d), bits-per-sample(%d)\n", ++ channels, samplerate, bps); ++ ++ vcos_mutex_lock(&instance->vchi_mutex); ++ vchi_service_use(instance->vchi_handle[0]); ++ ++ instance->got_result = 0; ++ instance->result = -1; ++ ++ m.type = VC_AUDIO_MSG_TYPE_CONFIG; ++ m.u.config.channels = channels; ++ m.u.config.samplerate = samplerate; ++ m.u.config.bps = bps; ++ ++ // Send the message to the videocore ++ success = vchi_msg_queue(instance->vchi_handle[0], ++ &m, sizeof m, ++ VCHI_FLAGS_BLOCK_UNTIL_QUEUED, NULL); ++ ++ if (success != 0) { ++ LOG_ERR("%s: failed on vchi_msg_queue (status=%d)", ++ __func__, success); ++ ++ ret = -1; ++ goto unlock; ++ } ++ ++ // We are expecting a reply from the videocore ++ while (!instance->got_result) { ++ success = vcos_event_wait(&instance->msg_avail_event); ++ if (success != VCOS_SUCCESS) { ++ LOG_ERR("%s: failed on waiting for event (status=%d)", ++ __func__, success); ++ ++ ret = -1; ++ goto unlock; ++ } ++ } ++ ++ if (instance->result != 0) { ++ LOG_ERR("%s: result=%d", ++ __func__, instance->result); ++ ++ ret = -1; ++ goto unlock; ++ } ++ ++ ret = 0; ++ ++unlock: ++ vchi_service_release(instance->vchi_handle[0]); ++ vcos_mutex_unlock(&instance->vchi_mutex); ++ ++ audio_debug(" .. OUT\n"); ++ return ret; ++} ++ ++int bcm2835_audio_setup(bcm2835_alsa_stream_t * alsa_stream) ++{ ++ audio_debug(" .. IN\n"); ++ ++ audio_debug(" .. OUT\n"); ++ ++ return 0; ++} ++ ++ ++static int bcm2835_audio_start_worker(bcm2835_alsa_stream_t * alsa_stream) ++{ ++ VC_AUDIO_MSG_T m; ++ AUDIO_INSTANCE_T *instance = alsa_stream->instance; ++ int32_t success; ++ int ret; ++ audio_debug(" .. IN\n"); ++ ++ vcos_mutex_lock(&instance->vchi_mutex); ++ vchi_service_use(instance->vchi_handle[0]); ++ ++ m.type = VC_AUDIO_MSG_TYPE_START; ++ ++ // Send the message to the videocore ++ success = vchi_msg_queue(instance->vchi_handle[0], ++ &m, sizeof m, ++ VCHI_FLAGS_BLOCK_UNTIL_QUEUED, NULL); ++ ++ if (success != 0) { ++ LOG_ERR("%s: failed on vchi_msg_queue (status=%d)", ++ __func__, success); ++ ++ ret = -1; ++ goto unlock; ++ } ++ ++ ret = 0; ++ ++unlock: ++ vchi_service_release(instance->vchi_handle[0]); ++ vcos_mutex_unlock(&instance->vchi_mutex); ++ audio_debug(" .. OUT\n"); ++ return ret; ++} ++ ++ ++static int bcm2835_audio_stop_worker(bcm2835_alsa_stream_t * alsa_stream) ++{ ++ VC_AUDIO_MSG_T m; ++ AUDIO_INSTANCE_T *instance = alsa_stream->instance; ++ int32_t success; ++ int ret; ++ audio_debug(" .. IN\n"); ++ ++ vcos_mutex_lock(&instance->vchi_mutex); ++ vchi_service_use(instance->vchi_handle[0]); ++ ++ m.type = VC_AUDIO_MSG_TYPE_STOP; ++ m.u.stop.draining = alsa_stream->draining; ++ ++ // Send the message to the videocore ++ success = vchi_msg_queue(instance->vchi_handle[0], ++ &m, sizeof m, ++ VCHI_FLAGS_BLOCK_UNTIL_QUEUED, NULL); ++ ++ if (success != 0) { ++ LOG_ERR("%s: failed on vchi_msg_queue (status=%d)", ++ __func__, success); ++ ++ ret = -1; ++ goto unlock; ++ } ++ ++ ret = 0; ++ ++unlock: ++ vchi_service_release(instance->vchi_handle[0]); ++ vcos_mutex_unlock(&instance->vchi_mutex); ++ audio_debug(" .. OUT\n"); ++ return ret; ++} ++ ++int bcm2835_audio_close(bcm2835_alsa_stream_t * alsa_stream) ++{ ++ VC_AUDIO_MSG_T m; ++ AUDIO_INSTANCE_T *instance = alsa_stream->instance; ++ int32_t success; ++ int ret; ++ audio_debug(" .. IN outstanding_completes=%d\n", atomic_read(&instance->callbacks_expected)-atomic_read(&instance->callbacks_received)); ++ ++ my_workqueue_quit(alsa_stream); ++ ++ vcos_mutex_lock(&instance->vchi_mutex); ++ vchi_service_use(instance->vchi_handle[0]); ++ ++ m.type = VC_AUDIO_MSG_TYPE_CLOSE; ++ instance->got_result = 0; ++ // Send the message to the videocore ++ success = vchi_msg_queue(instance->vchi_handle[0], ++ &m, sizeof m, ++ VCHI_FLAGS_BLOCK_UNTIL_QUEUED, NULL); ++ ++ if (success != 0) { ++ LOG_ERR("%s: failed on vchi_msg_queue (status=%d)", ++ __func__, success); ++ ++ ret = -1; ++ goto unlock; ++ } ++ while (!instance->got_result /*|| atomic_read(&instance->callbacks_expected)-atomic_read(&instance->callbacks_received) < 0*/ ) { ++ success = vcos_event_wait(&instance->msg_avail_event); ++ if (success != VCOS_SUCCESS) { ++ LOG_ERR("%s: failed on waiting for event (status=%d)", ++ __func__, success); ++ ++ ret = -1; ++ goto unlock; ++ } ++ } ++ if (instance->result != 0) { ++ LOG_ERR("%s: failed result (status=%d)", ++ __func__, instance->result); ++ ++ ret = -1; ++ goto unlock; ++ } ++ ++ ret = 0; ++ ++unlock: ++ vchi_service_release(instance->vchi_handle[0]); ++ vcos_mutex_unlock(&instance->vchi_mutex); ++ ++ // Stop the audio service ++ if (instance) { ++ vc_vchi_audio_deinit(instance); ++ alsa_stream->instance = NULL; ++ } ++ audio_debug(" .. OUT\n"); ++ return ret; ++} ++ ++static int bcm2835_audio_set_ctls_chan(bcm2835_alsa_stream_t *alsa_stream, bcm2835_chip_t *chip) ++{ ++ VC_AUDIO_MSG_T m; ++ AUDIO_INSTANCE_T *instance = alsa_stream->instance; ++ int32_t success; ++ uint32_t msg_len; ++ int ret; ++ audio_debug(" .. IN\n"); ++ ++ audio_info ++ (" Setting ALSA dest(%d), volume(%d)\n", chip->dest, chip->volume); ++ ++ vcos_mutex_lock(&instance->vchi_mutex); ++ vchi_service_use(instance->vchi_handle[0]); ++ ++ instance->got_result = 0; ++ instance->result = -1; ++ ++ m.type = VC_AUDIO_MSG_TYPE_CONTROL; ++ m.u.control.dest = chip->dest; ++ m.u.control.volume = chip->volume; ++ ++ // Send the message to the videocore ++ success = vchi_msg_queue(instance->vchi_handle[0], ++ &m, sizeof m, ++ VCHI_FLAGS_BLOCK_UNTIL_QUEUED, NULL); ++ ++ if (success != 0) { ++ LOG_ERR("%s: failed on vchi_msg_queue (status=%d)", ++ __func__, success); ++ ++ ret = -1; ++ goto unlock; ++ } ++ ++ // We are expecting a reply from the videocore ++ while (!instance->got_result) { ++ success = vcos_event_wait(&instance->msg_avail_event); ++ if (success != VCOS_SUCCESS) { ++ LOG_ERR("%s: failed on waiting for event (status=%d)", ++ __func__, success); ++ ++ ret = -1; ++ goto unlock; ++ } ++ } ++ ++ if (instance->result != 0) { ++ LOG_ERR("%s: result=%d", ++ __func__, instance->result); ++ ++ ret = -1; ++ goto unlock; ++ } ++ ++ ret = 0; ++ ++unlock: ++ vchi_service_release(instance->vchi_handle[0]); ++ vcos_mutex_unlock(&instance->vchi_mutex); ++ ++ audio_debug(" .. OUT\n"); ++ return ret; ++} ++ ++ ++int bcm2835_audio_set_ctls(bcm2835_chip_t *chip) ++{ ++ int i; ++ int ret = 0; ++ audio_debug(" .. IN\n"); ++ ++ /* change ctls for all substreams */ ++ for (i = 0; i < MAX_SUBSTREAMS; i++) { ++ if (chip->avail_substreams & (1 << i)) { ++ if (!chip->alsa_stream[i]) ++ ret = -1; ++ else if (bcm2835_audio_set_ctls_chan(chip->alsa_stream[i], chip) != 0) ++ ret = -1; ++ } ++ } ++ audio_debug(" .. OUT ret=%d\n", ret); ++ return ret; ++} ++ ++int bcm2835_audio_write(bcm2835_alsa_stream_t * alsa_stream, uint32_t count, ++ void *src) ++{ ++ VC_AUDIO_MSG_T m; ++ AUDIO_INSTANCE_T *instance = alsa_stream->instance; ++ int32_t success; ++ int ret; ++ ++ audio_debug(" .. IN outstanding=%d\n", atomic_read(&instance->callbacks_expected)-atomic_read(&instance->callbacks_received)); ++ ++ audio_info ++ (" Writing %d bytes from %p\n", count, src); ++ ++ vcos_mutex_lock(&instance->vchi_mutex); ++ vchi_service_use(instance->vchi_handle[0]); ++ ++ m.type = VC_AUDIO_MSG_TYPE_WRITE; ++ m.u.write.count = count; ++ m.u.write.callback = alsa_stream->fifo_irq_handler; ++ m.u.write.cookie = alsa_stream; ++ m.u.write.silence = src == NULL; ++ ++ atomic_add(1, &instance->callbacks_expected); ++ // Send the message to the videocore ++ success = vchi_msg_queue(instance->vchi_handle[0], ++ &m, sizeof m, ++ VCHI_FLAGS_BLOCK_UNTIL_QUEUED, NULL); ++ ++ if (success != 0) { ++ LOG_ERR("%s: failed on vchi_msg_queue (status=%d)", ++ __func__, success); ++ ++ ret = -1; ++ goto unlock; ++ } ++ audio_debug(" ... send header\n"); ++ ++ // Send the message to the videocore ++ success = vchi_bulk_queue_transmit(instance->vchi_handle[0], ++ src, count, 0*VCHI_FLAGS_BLOCK_UNTIL_QUEUED + 1*VCHI_FLAGS_BLOCK_UNTIL_DATA_READ, NULL); ++ if (success != 0) { ++ LOG_ERR("%s: failed on vchi_msg_queue (status=%d)", ++ __func__, success); ++ ++ ret = -1; ++ goto unlock; ++ } ++ ret = 0; ++ ++unlock: ++ if (ret != 0) { ++ atomic_dec(&instance->callbacks_expected); ++ } ++ vchi_service_release(instance->vchi_handle[0]); ++ vcos_mutex_unlock(&instance->vchi_mutex); ++ audio_debug(" .. OUT\n"); ++ return ret; ++} ++ ++/** ++ * Returns all buffers from arm->vc ++ */ ++void bcm2835_audio_flush_buffers(bcm2835_alsa_stream_t * alsa_stream) ++{ ++ audio_debug(" .. IN\n"); ++ audio_debug(" .. OUT\n"); ++ return; ++} ++ ++/** ++ * Forces VC to flush(drop) its filled playback buffers and ++ * return them the us. (VC->ARM) ++ */ ++void bcm2835_audio_flush_playback_buffers(bcm2835_alsa_stream_t * alsa_stream) ++{ ++ audio_debug(" .. IN\n"); ++ audio_debug(" .. OUT\n"); ++} ++ ++uint32_t bcm2835_audio_retrieve_buffers(bcm2835_alsa_stream_t *alsa_stream) ++{ ++ uint32_t count = atomic_read(&alsa_stream->retrieved); ++ atomic_sub(count, &alsa_stream->retrieved); ++ return count; ++} ++ +Index: linux-3.2.46/sound/arm/bcm2835.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/sound/arm/bcm2835.c 2013-07-26 19:32:31.000000000 +0000 +@@ -0,0 +1,426 @@ ++/***************************************************************************** ++* Copyright 2011 Broadcom Corporation. All rights reserved. ++* ++* Unless you and Broadcom execute a separate written software license ++* agreement governing use of this software, this software is licensed to you ++* under the terms of the GNU General Public License version 2, available at ++* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). ++* ++* Notwithstanding the above, under no circumstances may you combine this ++* software in any way with any other Broadcom software provided under a ++* license other than the GPL, without Broadcom's express prior written ++* consent. ++*****************************************************************************/ ++ ++#include ++ ++#include ++#include ++ ++#include "bcm2835.h" ++ ++/* module parameters (see "Module Parameters") */ ++/* SNDRV_CARDS: maximum number of cards supported by this module */ ++static int index[MAX_SUBSTREAMS] = { [0 ... (MAX_SUBSTREAMS - 1)] = -1}; ++static char *id[MAX_SUBSTREAMS] = { [0 ... (MAX_SUBSTREAMS - 1)] = NULL}; ++static int enable[MAX_SUBSTREAMS] = { [0 ... (MAX_SUBSTREAMS - 1)] = 1 }; ++ ++/* HACKY global pointers needed for successive probes to work : ssp ++ * But compared against the changes we will have to do in VC audio_ipc code ++ * to export 8 audio_ipc devices as a single IPC device and then monitor all ++ * four devices in a thread, this gets things done quickly and should be easier ++ * to debug if we run into issues ++ */ ++ ++static struct snd_card *g_card = NULL; ++static bcm2835_chip_t *g_chip = NULL; ++ ++static int snd_bcm2835_free(bcm2835_chip_t *chip) ++{ ++ kfree(chip); ++ return 0; ++} ++ ++ ++/* component-destructor ++ * (see "Management of Cards and Components") ++ */ ++static int snd_bcm2835_dev_free(struct snd_device *device) ++{ ++ return snd_bcm2835_free(device->device_data); ++} ++ ++ ++/* chip-specific constructor ++ * (see "Management of Cards and Components") ++ */ ++static int __devinit snd_bcm2835_create(struct snd_card *card, ++ struct platform_device *pdev, ++ bcm2835_chip_t **rchip) ++{ ++ bcm2835_chip_t *chip; ++ int err; ++ static struct snd_device_ops ops = { ++ .dev_free = snd_bcm2835_dev_free, ++ }; ++ ++ *rchip = NULL; ++ ++ chip = kzalloc(sizeof(*chip), GFP_KERNEL); ++ if (chip == NULL) ++ return -ENOMEM; ++ ++ chip->card = card; ++ ++ err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops); ++ if (err < 0) { ++ snd_bcm2835_free(chip); ++ return err; ++ } ++ ++ *rchip = chip; ++ return 0; ++} ++ ++static int __devinit snd_bcm2835_alsa_probe(struct platform_device *pdev) ++{ ++ static int dev; ++ bcm2835_chip_t *chip; ++ struct snd_card *card; ++ int err; ++ printk(KERN_INFO"### snd_bcm2835_alsa_probe %p ###", pdev); ++ ++ printk("############ PROBING FOR bcm2835 ALSA device (%d):(%d) ###############\n", dev, enable[dev]); ++ ++ if (dev >= MAX_SUBSTREAMS) ++ return -ENODEV; ++ ++ if (!enable[dev]) { ++ dev++; ++ return -ENOENT; ++ } ++ ++ if (dev > 0) ++ goto add_register_map; ++ ++ printk("Creating card...\n"); ++ err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &g_card); ++ if (err < 0) ++ goto out; ++ ++ snd_card_set_dev(g_card, &pdev->dev); ++ strcpy(g_card->driver, "BRCM bcm2835 ALSA Driver"); ++ strcpy(g_card->shortname, "bcm2835 ALSA"); ++ sprintf(g_card->longname, "%s", g_card->shortname); ++ ++ printk("Creating device/chip ..\n"); ++ err = snd_bcm2835_create(g_card, pdev, &chip); ++ if (err < 0) { ++ printk(KERN_ERR"Failed to create bcm2835 chip\n"); ++ goto out_bcm2835_create; ++ } ++ ++ g_chip = chip; ++ err = snd_bcm2835_new_pcm(chip); ++ if (err < 0) { ++ printk(KERN_ERR"Failed to create new BCM2835 pcm device\n"); ++ goto out_bcm2835_new_pcm; ++ } ++ ++ printk("Adding controls ..\n"); ++ err = snd_bcm2835_new_ctl(chip); ++ if (err < 0) { ++ printk(KERN_ERR"Failed to create new BCM2835 ctl\n"); ++ goto out_bcm2835_new_ctl; ++ } ++ ++add_register_map: ++ card = g_card; ++ chip = g_chip; ++ ++ BUG_ON(!(card && chip)); ++ ++ chip->avail_substreams |= (1 << dev); ++ chip->pdev[dev] = pdev; ++ ++ if (dev == 0) { ++ printk("Registering card ....\n"); ++ err = snd_card_register(card); ++ if (err < 0) { ++ printk(KERN_ERR"Failed to register bcm2835 ALSA card \n"); ++ goto out_card_register; ++ } ++ platform_set_drvdata(pdev, card); ++ printk("bcm2835 ALSA CARD CREATED!\n"); ++ } else { ++ printk("bcm2835 ALSA CHIP CREATED!\n"); ++ platform_set_drvdata(pdev, (void *)dev); ++ } ++ ++ dev++; ++ ++ return 0; ++ ++out_card_register: ++out_bcm2835_new_ctl: ++out_bcm2835_new_pcm: ++out_bcm2835_create: ++ BUG_ON(!g_card); ++ if (snd_card_free(g_card)) ++ printk(KERN_ERR"Failed to free Registered alsa card\n"); ++ g_card = NULL; ++out: ++ dev = SNDRV_CARDS; /* stop more avail_substreams from being probed */ ++ printk(KERN_ERR"BCM2835 ALSA Probe failed !!\n"); ++ return err; ++} ++ ++static int snd_bcm2835_alsa_remove(struct platform_device *pdev) ++{ ++ uint32_t idx; ++ void *drv_data; ++ ++ drv_data = platform_get_drvdata(pdev); ++ ++ if (drv_data == (void *)g_card) { ++ /* This is the card device */ ++ snd_card_free((struct snd_card *)drv_data); ++ g_card = NULL; ++ g_chip = NULL; ++ } else { ++ idx = (uint32_t)drv_data; ++ if (g_card != NULL) { ++ BUG_ON(!g_chip); ++ /* We pass chip device numbers in audio ipc devices ++ * other than the one we registered our card with ++ */ ++ idx = (uint32_t)drv_data; ++ BUG_ON(!idx || idx > MAX_SUBSTREAMS); ++ g_chip->avail_substreams &= ~(1 << idx); ++ /* There should be atleast one substream registered ++ * after we are done here, as it wil be removed when ++ * the *remove* is called for the card device ++ */ ++ BUG_ON(!g_chip->avail_substreams); ++ } ++ } ++ ++ platform_set_drvdata(pdev, NULL); ++ ++ return 0; ++} ++ ++#ifdef CONFIG_PM ++static int snd_bcm2835_alsa_suspend(struct platform_device *pdev, pm_message_t state) ++{ ++ return 0; ++} ++ ++static int snd_bcm2835_alsa_resume(struct platform_device *pdev) ++{ ++ return 0; ++} ++ ++#endif ++ ++static struct platform_driver bcm2835_alsa0_driver = ++{ ++ .probe = snd_bcm2835_alsa_probe, ++ .remove = snd_bcm2835_alsa_remove, ++#ifdef CONFIG_PM ++ .suspend = snd_bcm2835_alsa_suspend, ++ .resume = snd_bcm2835_alsa_resume, ++#endif ++ .driver = { ++ .name = "bcm2835_AUD0", ++ .owner = THIS_MODULE, ++ }, ++}; ++ ++static struct platform_driver bcm2835_alsa1_driver = ++{ ++ .probe = snd_bcm2835_alsa_probe, ++ .remove = snd_bcm2835_alsa_remove, ++#ifdef CONFIG_PM ++ .suspend = snd_bcm2835_alsa_suspend, ++ .resume = snd_bcm2835_alsa_resume, ++#endif ++ .driver = { ++ .name = "bcm2835_AUD1", ++ .owner = THIS_MODULE, ++ }, ++}; ++ ++static struct platform_driver bcm2835_alsa2_driver = ++{ ++ .probe = snd_bcm2835_alsa_probe, ++ .remove = snd_bcm2835_alsa_remove, ++#ifdef CONFIG_PM ++ .suspend = snd_bcm2835_alsa_suspend, ++ .resume = snd_bcm2835_alsa_resume, ++#endif ++ .driver = { ++ .name = "bcm2835_AUD2", ++ .owner = THIS_MODULE, ++ }, ++}; ++ ++static struct platform_driver bcm2835_alsa3_driver = ++{ ++ .probe = snd_bcm2835_alsa_probe, ++ .remove = snd_bcm2835_alsa_remove, ++#ifdef CONFIG_PM ++ .suspend = snd_bcm2835_alsa_suspend, ++ .resume = snd_bcm2835_alsa_resume, ++#endif ++ .driver = { ++ .name = "bcm2835_AUD3", ++ .owner = THIS_MODULE, ++ }, ++}; ++ ++static struct platform_driver bcm2835_alsa4_driver = ++{ ++ .probe = snd_bcm2835_alsa_probe, ++ .remove = snd_bcm2835_alsa_remove, ++#ifdef CONFIG_PM ++ .suspend = snd_bcm2835_alsa_suspend, ++ .resume = snd_bcm2835_alsa_resume, ++#endif ++ .driver = { ++ .name = "bcm2835_AUD4", ++ .owner = THIS_MODULE, ++ }, ++}; ++ ++static struct platform_driver bcm2835_alsa5_driver = ++{ ++ .probe = snd_bcm2835_alsa_probe, ++ .remove = snd_bcm2835_alsa_remove, ++#ifdef CONFIG_PM ++ .suspend = snd_bcm2835_alsa_suspend, ++ .resume = snd_bcm2835_alsa_resume, ++#endif ++ .driver = { ++ .name = "bcm2835_AUD5", ++ .owner = THIS_MODULE, ++ }, ++}; ++ ++static struct platform_driver bcm2835_alsa6_driver = ++{ ++ .probe = snd_bcm2835_alsa_probe, ++ .remove = snd_bcm2835_alsa_remove, ++#ifdef CONFIG_PM ++ .suspend = snd_bcm2835_alsa_suspend, ++ .resume = snd_bcm2835_alsa_resume, ++#endif ++ .driver = { ++ .name = "bcm2835_AUD6", ++ .owner = THIS_MODULE, ++ }, ++}; ++ ++static struct platform_driver bcm2835_alsa7_driver = ++{ ++ .probe = snd_bcm2835_alsa_probe, ++ .remove = snd_bcm2835_alsa_remove, ++#ifdef CONFIG_PM ++ .suspend = snd_bcm2835_alsa_suspend, ++ .resume = snd_bcm2835_alsa_resume, ++#endif ++ .driver = { ++ .name = "bcm2835_AUD7", ++ .owner = THIS_MODULE, ++ }, ++}; ++ ++ ++static int __devinit bcm2835_alsa_device_init(void) ++{ ++ int err; ++ err = platform_driver_register(&bcm2835_alsa0_driver); ++ if (err) { ++ printk("Error registering bcm2835_alsa0_driver %d .\n", err); ++ goto out; ++ } ++ ++ err = platform_driver_register(&bcm2835_alsa1_driver); ++ if (err) { ++ printk("Error registering bcm2835_alsa1_driver %d .\n", err); ++ goto unregister_0; ++ } ++ ++ err = platform_driver_register(&bcm2835_alsa2_driver); ++ if (err) { ++ printk("Error registering bcm2835_alsa2_driver %d .\n", err); ++ goto unregister_1; ++ } ++ ++ err = platform_driver_register(&bcm2835_alsa3_driver); ++ if (err) { ++ printk("Error registering bcm2835_alsa3_driver %d .\n", err); ++ goto unregister_2; ++ } ++ ++ err = platform_driver_register(&bcm2835_alsa4_driver); ++ if (err) { ++ printk("Error registering bcm2835_alsa4_driver %d .\n", err); ++ goto unregister_3; ++ } ++ ++ err = platform_driver_register(&bcm2835_alsa5_driver); ++ if (err) { ++ printk("Error registering bcm2835_alsa5_driver %d .\n", err); ++ goto unregister_4; ++ } ++ ++ err = platform_driver_register(&bcm2835_alsa6_driver); ++ if (err) { ++ printk("Error registering bcm2835_alsa6_driver %d .\n", err); ++ goto unregister_5; ++ } ++ ++ err = platform_driver_register(&bcm2835_alsa7_driver); ++ if (err) { ++ printk("Error registering bcm2835_alsa7_driver %d .\n", err); ++ goto unregister_6; ++ } ++ printk(KERN_INFO"### BCM2835 ALSA driver init %s ### \n",err ? "FAILED": "OK"); ++ ++ return 0; ++ ++unregister_6: ++ platform_driver_unregister(&bcm2835_alsa6_driver); ++unregister_5: ++ platform_driver_unregister(&bcm2835_alsa5_driver); ++unregister_4: ++ platform_driver_unregister(&bcm2835_alsa4_driver); ++unregister_3: ++ platform_driver_unregister(&bcm2835_alsa3_driver); ++unregister_2: ++ platform_driver_unregister(&bcm2835_alsa2_driver); ++unregister_1: ++ platform_driver_unregister(&bcm2835_alsa1_driver); ++unregister_0: ++ platform_driver_unregister(&bcm2835_alsa0_driver); ++out: ++ return err; ++} ++ ++ ++ ++static void __devexit bcm2835_alsa_device_exit(void) ++{ ++ platform_driver_unregister(&bcm2835_alsa0_driver); ++ platform_driver_unregister(&bcm2835_alsa1_driver); ++ platform_driver_unregister(&bcm2835_alsa2_driver); ++ platform_driver_unregister(&bcm2835_alsa3_driver); ++ platform_driver_unregister(&bcm2835_alsa4_driver); ++ platform_driver_unregister(&bcm2835_alsa5_driver); ++ platform_driver_unregister(&bcm2835_alsa6_driver); ++ platform_driver_unregister(&bcm2835_alsa7_driver); ++} ++ ++late_initcall(bcm2835_alsa_device_init); ++module_exit(bcm2835_alsa_device_exit); +Index: linux-3.2.46/sound/arm/bcm2835.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/sound/arm/bcm2835.h 2013-07-26 19:32:31.000000000 +0000 +@@ -0,0 +1,239 @@ ++/***************************************************************************** ++* Copyright 2011 Broadcom Corporation. All rights reserved. ++* ++* Unless you and Broadcom execute a separate written software license ++* agreement governing use of this software, this software is licensed to you ++* under the terms of the GNU General Public License version 2, available at ++* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). ++* ++* Notwithstanding the above, under no circumstances may you combine this ++* software in any way with any other Broadcom software provided under a ++* license other than the GPL, without Broadcom's express prior written ++* consent. ++*****************************************************************************/ ++ ++#ifndef __SOUND_ARM_BCM2835_H ++#define __SOUND_ARM_BCM2835_H ++ ++#define SUBSTREAM_NUM 1 ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++/* #define DUMP_RAW_DATA */ ++#define AUDIO_DEBUG_ENABLE ++//#define AUDIO_VERBOSE_DEBUG_ENABLE ++ ++/* Debug macros */ ++#ifdef AUDIO_DEBUG_ENABLE ++ ++#ifdef AUDIO_VERBOSE_DEBUG_ENABLE ++ ++#define audio_debug(fmt, arg...) \ ++ printk(KERN_INFO"%s:%d " fmt, __func__, __LINE__, ##arg) ++ ++#define audio_info(fmt, arg...) \ ++ printk(KERN_INFO"%s:%d " fmt, __func__, __LINE__, ##arg) ++ ++#else ++ ++#define audio_debug(fmt, arg...) do {} while (0) ++ ++#define audio_info(fmt, arg...) do {} while (0) ++ ++#endif /* AUDIO_VERBOSE_DEBUG_ENABLE */ ++ ++#else ++ ++#define audio_debug(fmt, arg...) do {} while (0) ++ ++#define audio_info(fmt, arg...) do {} while (0) ++ ++#endif /* AUDIO_DEBUG_ENABLE */ ++ ++#define audio_error(fmt, arg...) \ ++ printk(KERN_ERR"%s:%d " fmt, __func__, __LINE__, ##arg) ++ ++#define audio_warning(fmt, arg...) \ ++ printk(KERN_WARNING"%s:%d " fmt, __func__, __LINE__, ##arg) ++ ++#define audio_alert(fmt, arg...) \ ++ printk(KERN_ALERT"%s:%d " fmt, __func__, __LINE__, ##arg) ++ ++#define MAX_SUBSTREAMS (8) ++#define AVAIL_SUBSTREAMS_MASK (0xff) ++ ++#define AUDIO_IPC_BLOCK_NUM_BUFFERS (8) ++#define AUDIO_IPC_BLOCK_BUFFER_SIZE (1024*8) ++ ++#define AUDIO_CONTROL_OFFSET (0x00) ++ #define CTRL_EN_SHIFT (0) ++ #define CTRL_EN_MASK (0x00000001) ++ #define CTRL_PLAY_SHIFT (1) ++ #define CTRL_PLAY_MASK (0x00000002) ++ #define CTRL_MUTE_SHIFT (2) ++ #define CTRL_MUTE_MASK (0x00000004) ++ #define CTRL_SETUP_SHIFT (3) ++ #define CTRL_SETUP_MASK (0x00000008) ++ #define CTRL_FLUSH_SHIFT (4) ++ #define CTRL_FLUSH_MASK (0x00000010) ++ #define CTRL_STOPMODE_SHIFT (5) ++ #define CTRL_STOPMODE_MASK (0x00000020) ++ ++#define AUDIO_STATUS_OFFSET (0x04) ++ #define STAT_EN_SHIFT (0) ++ #define STAT_EN_MASK (0x00000001) ++ #define STAT_PLAY_SHIFT (1) ++ #define STAT_PLAY_MASK (0x00000002) ++ #define STAT_MUTE_SHIFT (2) ++ #define STAT_MUTE_MASK (0x00000004) ++ #define STAT_SETUP_SHIFT (3) ++ #define STAT_SETUP_MASK (0x00000008) ++ #define STAT_FLUSH_SHIFT (4) ++ #define STAT_FLUSH_MASK (0x00000010) ++ #define STAT_STOPMODE_SHIFT (5) ++ #define STAT_STOPMODE_MASK (0x00000020) ++ ++/* Interrupt status */ ++#define AUDIO_INTSTAT_OFFSET (0x08) ++ #define INTSTAT_CONTROL_SHIFT (0) ++ #define INTSTAT_CONTROL_MASK (0x0000000f) ++ #define INTSTAT_FIFO_SHIFT (4) ++ #define INTSTAT_FIFO_MASK (0x000000f0) ++ ++/* Configuration */ ++#define AUDIO_DESTINATION_OFFSET (0x0C) ++#define AUDIO_SAMPLE_RATE_OFFSET (0x10) ++#define AUDIO_BIT_RATE_OFFSET (0x14) ++#define AUDIO_VOLUME_OFFSET (0x18) ++#define AUDIO_CHANNELS_OFFSET (0x1C) ++ ++/* Implemention of peterson's algorithm for shared memory semaphores */ ++#define AUDIO_FLAG0_OFFSET (0x20) ++#define AUDIO_FLAG1_OFFSET (0x24) ++#define AUDIO_TURN_OFFSET (0x28) ++ ++/* Fifo registers */ ++#define AUDIO_IN_WRITE_PTR_OFFSET (0x30) ++#define AUDIO_IN_READ_PTR_OFFSET (0x34) ++#define AUDIO_IN_FIFO_SIZE_OFFSET (0x38) ++#define AUDIO_IN_FIFO_ENTRY_OFFSET (0x3C) ++#define AUDIO_IN_FIFO_START_OFFSET (0x40) ++ ++/* 8 entries here of 4 words each = 0x80 gap from 0x50 */ ++#define AUDIO_IN_FIFO_OFFSET (0x50) ++ ++#define AUDIO_OUT_WRITE_PTR_OFFSET (0xD0) ++#define AUDIO_OUT_READ_PTR_OFFSET (0xD4) ++#define AUDIO_OUT_FIFO_SIZE_OFFSET (0xD8) ++#define AUDIO_OUT_FIFO_ENTRY_OFFSET (0xDC) ++#define AUDIO_OUT_FIFO_START_OFFSET (0xE0) ++ ++/* 8 entries here of 4 words each = 0x80 gap from 0xF0 */ ++#define AUDIO_OUT_FIFO_OFFSET (0xF0) ++ ++ ++/* Some constants for values .. */ ++typedef enum { ++ AUDIO_DEST_LOCAL = 0, ++ AUDIO_DEST_HDMI = 2, ++ AUDIO_DEST_ALL = 3, ++} SND_BCM2835_ROUTE_T; ++ ++typedef enum { ++ PCM_PLAYBACK_VOLUME, ++ PCM_PLAYBACK_MUTE, ++ PCM_PLAYBACK_DEVICE, ++} SND_BCM2835_CTRL_T; ++ ++/* this struct is tightly packed - its size is 16bytes */ ++typedef struct ++{ ++ uint32_t buffer_id; ++ uint32_t buffer_size; ++ uint32_t buffer_ptr; ++ uint32_t spare; ++ ++} AUDIO_FIFO_ENTRY_T; ++ ++/* definition of the chip-specific record */ ++typedef struct bcm2835_chip { ++ struct snd_card *card; ++ struct snd_pcm *pcm; ++ /* Bitmat for valid reg_base and irq numbers */ ++ uint32_t avail_substreams; ++ struct platform_device *pdev[MAX_SUBSTREAMS]; ++ struct bcm2835_alsa_stream *alsa_stream[MAX_SUBSTREAMS]; ++ ++ int volume; ++ int dest; ++ int mute; ++} bcm2835_chip_t; ++ ++typedef struct bcm2835_audio_buffer { ++ uint32_t buffer_id; ++ phys_addr_t bus_addr; ++ uint8_t __iomem *start; ++ uint32_t size; ++ uint32_t data_left; ++ struct list_head link; ++ ++} bcm2835_audio_buffer_t; ++ ++typedef struct bcm2835_alsa_stream { ++ bcm2835_chip_t *chip; ++ struct snd_pcm_substream *substream; ++ ++ struct semaphore buffers_update_sem; ++ struct semaphore control_sem; ++ spinlock_t lock; ++ volatile uint32_t control; ++ volatile uint32_t status; ++ ++ int open; ++ int running; ++ int draining; ++ ++#ifdef DUMP_RAW_DATA ++ /* for debug */ ++ int file; ++#endif ++ unsigned int pos; ++ unsigned int buffer_size; ++ unsigned int period_size; ++ ++ uint32_t enable_fifo_irq; ++ irq_handler_t fifo_irq_handler; ++ ++ atomic_t retrieved; ++ struct opaque_AUDIO_INSTANCE_T *instance; ++ struct workqueue_struct *my_wq; ++} bcm2835_alsa_stream_t; ++ ++int snd_bcm2835_new_ctl(bcm2835_chip_t *chip); ++int snd_bcm2835_new_pcm(bcm2835_chip_t *chip); ++ ++void bcm2835_audio_fifo_get_lock(bcm2835_alsa_stream_t *alsa_stream); ++void bcm2835_audio_fifo_put_lock(bcm2835_alsa_stream_t *alsa_stream); ++ ++int bcm2835_audio_open(bcm2835_alsa_stream_t *alsa_stream); ++int bcm2835_audio_close(bcm2835_alsa_stream_t *alsa_stream); ++int bcm2835_audio_set_params(bcm2835_alsa_stream_t *alsa_stream, uint32_t channels, uint32_t samplerate, uint32_t bps); ++int bcm2835_audio_setup(bcm2835_alsa_stream_t *alsa_stream); ++int bcm2835_audio_start(bcm2835_alsa_stream_t *alsa_stream); ++int bcm2835_audio_stop(bcm2835_alsa_stream_t *alsa_stream); ++int bcm2835_audio_set_ctls(bcm2835_chip_t *chip); ++int bcm2835_audio_write(bcm2835_alsa_stream_t *alsa_stream, uint32_t count, void *src); ++//uint32_t bcm2835_audio_buffers_consumed_bytes(bcm2835_alsa_stream_t *alsa_stream); ++uint32_t bcm2835_audio_retrieve_buffers(bcm2835_alsa_stream_t *alsa_stream); ++void bcm2835_audio_flush_buffers(bcm2835_alsa_stream_t *alsa_stream); ++void bcm2835_audio_flush_playback_buffers(bcm2835_alsa_stream_t *alsa_stream); ++ ++#endif /* __SOUND_ARM_BCM2835_H */ +Index: linux-3.2.46/sound/arm/vc_vchi_audioserv_defs.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/sound/arm/vc_vchi_audioserv_defs.h 2013-07-26 19:32:31.000000000 +0000 +@@ -0,0 +1,128 @@ ++/***************************************************************************** ++* Copyright 2011 Broadcom Corporation. All rights reserved. ++* ++* Unless you and Broadcom execute a separate written software license ++* agreement governing use of this software, this software is licensed to you ++* under the terms of the GNU General Public License version 2, available at ++* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). ++* ++* Notwithstanding the above, under no circumstances may you combine this ++* software in any way with any other Broadcom software provided under a ++* license other than the GPL, without Broadcom's express prior written ++* consent. ++*****************************************************************************/ ++ ++#ifndef _VC_AUDIO_DEFS_H_ ++#define _VC_AUDIO_DEFS_H_ ++ ++// FourCC code used for VCHI connection ++#define VC_AUDIO_SERVER_NAME MAKE_FOURCC("AUDS") ++ ++// Maximum message length ++#define VC_AUDIO_MAX_MSG_LEN (sizeof( VC_AUDIO_MSG_T )) ++ ++// List of screens that are currently supported ++// All message types supported for HOST->VC direction ++typedef enum ++{ ++ VC_AUDIO_MSG_TYPE_RESULT, // Generic result ++ VC_AUDIO_MSG_TYPE_COMPLETE, // Generic result ++ VC_AUDIO_MSG_TYPE_CONFIG, // Configure audio ++ VC_AUDIO_MSG_TYPE_CONTROL, // Configure audio ++ VC_AUDIO_MSG_TYPE_OPEN, // Configure audio ++ VC_AUDIO_MSG_TYPE_CLOSE, // Configure audio ++ VC_AUDIO_MSG_TYPE_START, // Configure audio ++ VC_AUDIO_MSG_TYPE_STOP, // Configure audio ++ VC_AUDIO_MSG_TYPE_WRITE, // Configure audio ++ VC_AUDIO_MSG_TYPE_MAX ++ ++} VC_AUDIO_MSG_TYPE; ++ ++ ++// configure the audio ++typedef struct ++{ ++ uint32_t channels; ++ uint32_t samplerate; ++ uint32_t bps; ++ ++} VC_AUDIO_CONFIG_T; ++ ++typedef struct ++{ ++ uint32_t volume; ++ uint32_t dest; ++ ++} VC_AUDIO_CONTROL_T; ++ ++// audio ++typedef struct ++{ ++ uint32_t dummy; ++ ++} VC_AUDIO_OPEN_T; ++ ++// audio ++typedef struct ++{ ++ uint32_t dummy; ++ ++} VC_AUDIO_CLOSE_T; ++// audio ++typedef struct ++{ ++ uint32_t dummy; ++ ++} VC_AUDIO_START_T; ++// audio ++typedef struct ++{ ++ uint32_t draining; ++ ++} VC_AUDIO_STOP_T; ++ ++// configure the write audio samples ++typedef struct ++{ ++ uint32_t count; // in bytes ++ void *callback; ++ void *cookie; ++ uint32_t silence; ++} VC_AUDIO_WRITE_T; ++ ++// Generic result for a request (VC->HOST) ++typedef struct ++{ ++ int32_t success; // Success value ++ ++} VC_AUDIO_RESULT_T; ++ ++// Generic result for a request (VC->HOST) ++typedef struct ++{ ++ int32_t count; // Success value ++ void *callback; ++ void *cookie; ++} VC_AUDIO_COMPLETE_T; ++ ++// Message header for all messages in HOST->VC direction ++typedef struct ++{ ++ int32_t type; // Message type (VC_AUDIO_MSG_TYPE) ++ union ++ { ++ VC_AUDIO_CONFIG_T config; ++ VC_AUDIO_CONTROL_T control; ++ VC_AUDIO_OPEN_T open; ++ VC_AUDIO_CLOSE_T close; ++ VC_AUDIO_START_T start; ++ VC_AUDIO_STOP_T stop; ++ VC_AUDIO_WRITE_T write; ++ VC_AUDIO_RESULT_T result; ++ VC_AUDIO_COMPLETE_T complete; ++ } u; ++} VC_AUDIO_MSG_T; ++ ++ ++#endif // _VC_AUDIO_DEFS_H_ ++ diff -Nru linux-3.2.46/debian/patches/rpi/rpi_121_2b4c39f7d2bb2d0b47ddd4c40250d54f1f3551aa.patch linux-3.2.46/debian/patches/rpi/rpi_121_2b4c39f7d2bb2d0b47ddd4c40250d54f1f3551aa.patch --- linux-3.2.46/debian/patches/rpi/rpi_121_2b4c39f7d2bb2d0b47ddd4c40250d54f1f3551aa.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_121_2b4c39f7d2bb2d0b47ddd4c40250d54f1f3551aa.patch 2013-07-26 19:32:33.000000000 +0000 @@ -0,0 +1,28 @@ +commit 2b4c39f7d2bb2d0b47ddd4c40250d54f1f3551aa +Author: Dom Cobley +Date: Mon Mar 26 22:18:37 2012 +0100 + + Cast to avoid warning + +Index: linux-3.2.46/drivers/video/bcm2708_fb.c +=================================================================== +--- linux-3.2.46.orig/drivers/video/bcm2708_fb.c 2013-07-26 19:32:21.000000000 +0000 ++++ linux-3.2.46/drivers/video/bcm2708_fb.c 2013-07-26 19:32:32.000000000 +0000 +@@ -191,7 +191,7 @@ + + static int bcm2708_fb_set_par(struct fb_info *info) + { +- unsigned val = 0; ++ uint32_t val = 0; + struct bcm2708_fb *fb = to_bcm2708(info); + volatile struct fbinfo_s *fbinfo = fb->info; + fbinfo->xres = info->var.xres; +@@ -243,7 +243,7 @@ + ("BCM2708FB: start = %p,%p width=%d, height=%d, bpp=%d, pitch=%d size=%d success=%d\n", + (void *)fb->fb.screen_base, (void *)fb->fb.fix.smem_start, + fbinfo->xres, fbinfo->yres, fbinfo->bpp, +- fbinfo->pitch, fb->fb.screen_size, val); ++ fbinfo->pitch, (int)fb->fb.screen_size, val); + + return val; + } diff -Nru linux-3.2.46/debian/patches/rpi/rpi_122_6496fce7ba616b8d8bbada9deb5505e013cbb46d.patch linux-3.2.46/debian/patches/rpi/rpi_122_6496fce7ba616b8d8bbada9deb5505e013cbb46d.patch --- linux-3.2.46/debian/patches/rpi/rpi_122_6496fce7ba616b8d8bbada9deb5505e013cbb46d.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_122_6496fce7ba616b8d8bbada9deb5505e013cbb46d.patch 2013-07-26 19:32:35.000000000 +0000 @@ -0,0 +1,91 @@ +commit 6496fce7ba616b8d8bbada9deb5505e013cbb46d +Author: Dom Cobley +Date: Mon Mar 26 22:19:16 2012 +0100 + + Add new ioctl to match latest vc side code + +Index: linux-3.2.46/arch/arm/mach-bcm2708/vc_mem.c +=================================================================== +--- linux-3.2.46.orig/arch/arm/mach-bcm2708/vc_mem.c 2013-07-26 19:31:51.000000000 +0000 ++++ linux-3.2.46/arch/arm/mach-bcm2708/vc_mem.c 2013-07-26 19:32:34.000000000 +0000 +@@ -85,9 +85,11 @@ + #endif + + unsigned int mm_vc_mem_size = 0; ++unsigned int mm_vc_mem_base = 0; + + EXPORT_SYMBOL(mm_vc_mem_phys_addr); + EXPORT_SYMBOL(mm_vc_mem_size); ++EXPORT_SYMBOL(mm_vc_mem_base); + + /**************************************************************************** + * +@@ -132,36 +134,19 @@ + static void + vc_mem_get_size(void) + { +-#ifdef CONFIG_ARCH_BCM2708 + mm_vc_mem_size = 256 * 1024 * 1024; // Static for now +-#else +- CHAL_IPC_HANDLE ipc_handle; +- uint32_t wakeup_register; +- +- // Get the videocore memory size from the IPC mailbox if not yet +- // assigned. +- if (mm_vc_mem_size == 0) { +- ipc_handle = chal_ipc_config(NULL); +- if (ipc_handle == NULL) { +- LOG_ERR("%s: failed to get IPC handlle", __func__); +- return; +- } ++} + +- chal_ipc_query_wakeup_vc(ipc_handle, &wakeup_register); +- if ((wakeup_register & ~1) == 0) { +- LOG_DBG("%s: videocore not yet loaded, skipping...", +- __func__); +- } else { +- if (chal_ipc_read_mailbox(ipc_handle, +- IPC_MAILBOX_ID_0, +- &mm_vc_mem_size) != +- BCM_SUCCESS) { +- LOG_ERR("%s: failed to read from IPC mailbox", +- __func__); +- } +- } +- } +-#endif ++/**************************************************************************** ++* ++* vc_mem_get_base ++* ++***************************************************************************/ ++ ++static void ++vc_mem_get_base(void) ++{ ++ mm_vc_mem_base = 128 * 1024 * 1024; // Static for now + } + + /**************************************************************************** +@@ -216,6 +201,20 @@ + mm_vc_mem_size); + + if (copy_to_user((void *) arg, &mm_vc_mem_size, ++ sizeof (mm_vc_mem_size)) != 0) { ++ rc = -EFAULT; ++ } ++ break; ++ } ++ case VC_MEM_IOC_MEM_BASE: ++ { ++ // Get the videocore memory size first ++ vc_mem_get_base(); ++ ++ LOG_DBG("%s: VC_MEM_IOC_MEM_BASE=%u", __func__, ++ mm_vc_mem_size); ++ ++ if (copy_to_user((void *) arg, &mm_vc_mem_size, + sizeof (mm_vc_mem_size)) != 0) { + rc = -EFAULT; + } diff -Nru linux-3.2.46/debian/patches/rpi/rpi_123_6a0c53faa0c37afbd224750ed4df073785fc5b04.patch linux-3.2.46/debian/patches/rpi/rpi_123_6a0c53faa0c37afbd224750ed4df073785fc5b04.patch --- linux-3.2.46/debian/patches/rpi/rpi_123_6a0c53faa0c37afbd224750ed4df073785fc5b04.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_123_6a0c53faa0c37afbd224750ed4df073785fc5b04.patch 2013-07-26 19:32:36.000000000 +0000 @@ -0,0 +1,2291 @@ +commit 6a0c53faa0c37afbd224750ed4df073785fc5b04 +Author: popcornmix +Date: Wed Mar 28 23:26:18 2012 +0100 + + Enable sound kernel modules. Tidy formatting. Fix ctl dest setting + +Index: linux-3.2.46/arch/arm/configs/bcmrpi_cutdown_defconfig +=================================================================== +--- linux-3.2.46.orig/arch/arm/configs/bcmrpi_cutdown_defconfig 2013-07-26 19:32:24.000000000 +0000 ++++ linux-3.2.46/arch/arm/configs/bcmrpi_cutdown_defconfig 2013-07-26 19:32:35.000000000 +0000 +@@ -208,6 +208,26 @@ + CONFIG_LOGO=y + # CONFIG_LOGO_LINUX_MONO is not set + # CONFIG_LOGO_LINUX_VGA16 is not set ++CONFIG_SOUND=y ++CONFIG_SND=m ++CONFIG_SND_SEQUENCER=m ++CONFIG_SND_SEQ_DUMMY=m ++CONFIG_SND_MIXER_OSS=m ++CONFIG_SND_PCM_OSS=m ++CONFIG_SND_SEQUENCER_OSS=y ++CONFIG_SND_HRTIMER=m ++CONFIG_SND_DUMMY=m ++CONFIG_SND_ALOOP=m ++CONFIG_SND_VIRMIDI=m ++CONFIG_SND_MTPAV=m ++CONFIG_SND_SERIAL_U16550=m ++CONFIG_SND_MPU401=m ++CONFIG_SND_BCM2835=m ++CONFIG_SND_USB_AUDIO=m ++CONFIG_SND_USB_UA101=m ++CONFIG_SND_USB_CAIAQ=m ++CONFIG_SND_USB_6FIRE=m ++CONFIG_SOUND_PRIME=m + CONFIG_HID_PID=y + CONFIG_USB_HIDDEV=y + CONFIG_HID_A4TECH=m +Index: linux-3.2.46/arch/arm/configs/bcmrpi_defconfig +=================================================================== +--- linux-3.2.46.orig/arch/arm/configs/bcmrpi_defconfig 2013-07-26 19:32:24.000000000 +0000 ++++ linux-3.2.46/arch/arm/configs/bcmrpi_defconfig 2013-07-26 19:32:35.000000000 +0000 +@@ -225,6 +225,26 @@ + CONFIG_LOGO=y + # CONFIG_LOGO_LINUX_MONO is not set + # CONFIG_LOGO_LINUX_VGA16 is not set ++CONFIG_SOUND=y ++CONFIG_SND=m ++CONFIG_SND_SEQUENCER=m ++CONFIG_SND_SEQ_DUMMY=m ++CONFIG_SND_MIXER_OSS=m ++CONFIG_SND_PCM_OSS=m ++CONFIG_SND_SEQUENCER_OSS=y ++CONFIG_SND_HRTIMER=m ++CONFIG_SND_DUMMY=m ++CONFIG_SND_ALOOP=m ++CONFIG_SND_VIRMIDI=m ++CONFIG_SND_MTPAV=m ++CONFIG_SND_SERIAL_U16550=m ++CONFIG_SND_MPU401=m ++CONFIG_SND_BCM2835=m ++CONFIG_SND_USB_AUDIO=m ++CONFIG_SND_USB_UA101=m ++CONFIG_SND_USB_CAIAQ=m ++CONFIG_SND_USB_6FIRE=m ++CONFIG_SOUND_PRIME=m + CONFIG_HID_PID=y + CONFIG_USB_HIDDEV=y + CONFIG_HID_A4TECH=m +Index: linux-3.2.46/sound/arm/bcm2835-ctl.c +=================================================================== +--- linux-3.2.46.orig/sound/arm/bcm2835-ctl.c 2013-07-26 19:32:31.000000000 +0000 ++++ linux-3.2.46/sound/arm/bcm2835-ctl.c 2013-07-26 19:32:35.000000000 +0000 +@@ -33,30 +33,31 @@ + + #include "bcm2835.h" + +-static int snd_bcm2835_ctl_info(struct snd_kcontrol * kcontrol, +- struct snd_ctl_elem_info * uinfo) ++static int snd_bcm2835_ctl_info(struct snd_kcontrol *kcontrol, ++ struct snd_ctl_elem_info *uinfo) + { + if (kcontrol->private_value == PCM_PLAYBACK_VOLUME) { +- uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; +- uinfo->count = 1; +- uinfo->value.integer.min = -10240; +- uinfo->value.integer.max = 2303; ++ uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; ++ uinfo->count = 1; ++ uinfo->value.integer.min = -10240; ++ uinfo->value.integer.max = 2303; + } else if (kcontrol->private_value == PCM_PLAYBACK_MUTE) { +- uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; +- uinfo->count = 1; +- uinfo->value.integer.min = 0; +- uinfo->value.integer.max = 1; ++ uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; ++ uinfo->count = 1; ++ uinfo->value.integer.min = 0; ++ uinfo->value.integer.max = 1; + } else if (kcontrol->private_value == PCM_PLAYBACK_DEVICE) { +- uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; +- uinfo->count = 1; +- uinfo->value.integer.min = AUDIO_DEST_LOCAL; +- uinfo->value.integer.max = AUDIO_DEST_ALL; ++ uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; ++ uinfo->count = 1; ++ uinfo->value.integer.min = 0; ++ uinfo->value.integer.max = AUDIO_DEST_MAX-0; + } + + return 0; + } + +-static int snd_bcm2835_ctl_get(struct snd_kcontrol * kcontrol, struct snd_ctl_elem_value * ucontrol) ++static int snd_bcm2835_ctl_get(struct snd_kcontrol *kcontrol, ++ struct snd_ctl_elem_value *ucontrol) + { + struct bcm2835_chip *chip = snd_kcontrol_chip(kcontrol); + +@@ -72,7 +73,8 @@ + return 0; + } + +-static int snd_bcm2835_ctl_put(struct snd_kcontrol * kcontrol, struct snd_ctl_elem_value * ucontrol) ++static int snd_bcm2835_ctl_put(struct snd_kcontrol *kcontrol, ++ struct snd_ctl_elem_value *ucontrol) + { + struct bcm2835_chip *chip = snd_kcontrol_chip(kcontrol); + int changed = 0; +@@ -82,7 +84,8 @@ + chip->mute = 0; + changed = 1; + } +- if (changed || (ucontrol->value.integer.value[0] != chip->volume)) { ++ if (changed ++ || (ucontrol->value.integer.value[0] != chip->volume)) { + int atten; + + chip->volume = ucontrol->value.integer.value[0]; +@@ -92,21 +95,21 @@ + } + + } else if (kcontrol->private_value == PCM_PLAYBACK_MUTE) { +- // Not implemented ++ /* Not implemented */ + if (ucontrol->value.integer.value[0] != chip->mute) { + chip->mute = ucontrol->value.integer.value[0]; + changed = 0; + } + } else if (kcontrol->private_value == PCM_PLAYBACK_DEVICE) { +- if (ucontrol->value.integer.value[0] != chip->dest && ucontrol->value.integer.value[0] != 1) { +- chip->dest= ucontrol->value.integer.value[0]; ++ if (ucontrol->value.integer.value[0] != chip->dest) { ++ chip->dest = ucontrol->value.integer.value[0]; + changed = 1; + } + } + + if (changed) { + if (bcm2835_audio_set_ctls(chip)) +- printk(KERN_ERR"Failed to set ALSA controls..\n"); ++ printk(KERN_ERR "Failed to set ALSA controls..\n"); + } + + return changed; +@@ -114,53 +117,54 @@ + + static DECLARE_TLV_DB_SCALE(snd_bcm2835_db_scale, -10240, 1, 1); + +-static struct snd_kcontrol_new snd_bcm2835_ctl[] __devinitdata = +-{ ++static struct snd_kcontrol_new snd_bcm2835_ctl[] __devinitdata = { + { +- .iface = SNDRV_CTL_ELEM_IFACE_MIXER, +- .name = "PCM Playback Volume", +- .index = 0, +- .access= SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_TLV_READWRITE, +- .private_value = PCM_PLAYBACK_VOLUME, +- .info = snd_bcm2835_ctl_info, +- .get = snd_bcm2835_ctl_get, +- .put = snd_bcm2835_ctl_put, +- .count = 1, +- .tlv = { .p = snd_bcm2835_db_scale } +- }, ++ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, ++ .name = "PCM Playback Volume", ++ .index = 0, ++ .access = ++ SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_TLV_READWRITE, ++ .private_value = PCM_PLAYBACK_VOLUME, ++ .info = snd_bcm2835_ctl_info, ++ .get = snd_bcm2835_ctl_get, ++ .put = snd_bcm2835_ctl_put, ++ .count = 1, ++ .tlv = {.p = snd_bcm2835_db_scale} ++ }, + { +- .iface = SNDRV_CTL_ELEM_IFACE_MIXER, +- .name = "PCM Playback Switch", +- .index = 0, +- .access= SNDRV_CTL_ELEM_ACCESS_READWRITE, +- .private_value = PCM_PLAYBACK_MUTE, +- .info = snd_bcm2835_ctl_info, +- .get = snd_bcm2835_ctl_get, +- .put = snd_bcm2835_ctl_put, +- .count = 1, +- }, ++ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, ++ .name = "PCM Playback Switch", ++ .index = 0, ++ .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, ++ .private_value = PCM_PLAYBACK_MUTE, ++ .info = snd_bcm2835_ctl_info, ++ .get = snd_bcm2835_ctl_get, ++ .put = snd_bcm2835_ctl_put, ++ .count = 1, ++ }, + { +- .iface = SNDRV_CTL_ELEM_IFACE_MIXER, +- .name = "PCM Playback Route", +- .index = 0, +- .access= SNDRV_CTL_ELEM_ACCESS_READWRITE, +- .private_value = PCM_PLAYBACK_DEVICE, +- .info = snd_bcm2835_ctl_info, +- .get = snd_bcm2835_ctl_get, +- .put = snd_bcm2835_ctl_put, +- .count = 1, +- }, ++ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, ++ .name = "PCM Playback Route", ++ .index = 0, ++ .access = SNDRV_CTL_ELEM_ACCESS_READWRITE, ++ .private_value = PCM_PLAYBACK_DEVICE, ++ .info = snd_bcm2835_ctl_info, ++ .get = snd_bcm2835_ctl_get, ++ .put = snd_bcm2835_ctl_put, ++ .count = 1, ++ }, + }; + +-int __devinit snd_bcm2835_new_ctl(bcm2835_chip_t *chip) ++int __devinit snd_bcm2835_new_ctl(bcm2835_chip_t * chip) + { + int err; + unsigned int idx; + + strcpy(chip->card->mixername, "Broadcom Mixer"); +- for (idx = 0; idx < ARRAY_SIZE(snd_bcm2835_ctl); idx++) +- { +- err = snd_ctl_add(chip->card, snd_ctl_new1(&snd_bcm2835_ctl[idx], chip)); ++ for (idx = 0; idx < ARRAY_SIZE(snd_bcm2835_ctl); idx++) { ++ err = ++ snd_ctl_add(chip->card, ++ snd_ctl_new1(&snd_bcm2835_ctl[idx], chip)); + if (err < 0) + return err; + } +Index: linux-3.2.46/sound/arm/bcm2835-pcm.c +=================================================================== +--- linux-3.2.46.orig/sound/arm/bcm2835-pcm.c 2013-07-26 19:32:31.000000000 +0000 ++++ linux-3.2.46/sound/arm/bcm2835-pcm.c 2013-07-26 19:32:35.000000000 +0000 +@@ -19,22 +19,20 @@ + + /* hardware definition */ + static struct snd_pcm_hardware snd_bcm2835_playback_hw = { +- .info = ( SNDRV_PCM_INFO_INTERLEAVED | +- SNDRV_PCM_INFO_BLOCK_TRANSFER ), +- .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE, +- .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000, +- .rate_min = 8000, +- .rate_max = 48000, +- .channels_min = 1, +- .channels_max = 2, +- .buffer_bytes_max = (4*8-1)*1024, /* Needs to be less than audioplay buffer size */ +- .period_bytes_min = 1*1024, +- .period_bytes_max = (4*8-1)*1024, +- .periods_min = 1, +- .periods_max = 4*8-1, ++ .info = (SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_BLOCK_TRANSFER), ++ .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE, ++ .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000, ++ .rate_min = 8000, ++ .rate_max = 48000, ++ .channels_min = 1, ++ .channels_max = 2, ++ .buffer_bytes_max = (4 * 8 - 1) * 1024, /* Needs to be less than audioplay buffer size */ ++ .period_bytes_min = 1 * 1024, ++ .period_bytes_max = (4 * 8 - 1) * 1024, ++ .periods_min = 1, ++ .periods_max = 4 * 8 - 1, + }; + +- + static void snd_bcm2835_playback_free(struct snd_pcm_runtime *runtime) + { + audio_info("Freeing up alsa stream here ..\n"); +@@ -45,13 +43,14 @@ + + static irqreturn_t bcm2835_playback_fifo_irq(int irq, void *dev_id) + { +- bcm2835_alsa_stream_t *alsa_stream = (bcm2835_alsa_stream_t *)dev_id; ++ bcm2835_alsa_stream_t *alsa_stream = (bcm2835_alsa_stream_t *) dev_id; + uint32_t consumed = 0; + int new_period = 0; + + audio_debug(" .. IN\n"); + +- audio_info("alsa_stream=%p substream=%p\n", alsa_stream, alsa_stream ? alsa_stream->substream:0); ++ audio_info("alsa_stream=%p substream=%p\n", alsa_stream, ++ alsa_stream ? alsa_stream->substream : 0); + + if (alsa_stream->open) + consumed = bcm2835_audio_retrieve_buffers(alsa_stream); +@@ -61,15 +60,18 @@ + */ + + if (alsa_stream->period_size) { +- if ((alsa_stream->pos / alsa_stream->period_size) != ((alsa_stream->pos+consumed) / alsa_stream->period_size)) ++ if ((alsa_stream->pos / alsa_stream->period_size) != ++ ((alsa_stream->pos + consumed) / alsa_stream->period_size)) + new_period = 1; + } +- audio_warning("updating pos cur: %d + %d max:%d new_period:%d\n", alsa_stream->pos, +- (consumed /** AUDIO_IPC_BLOCK_BUFFER_SIZE*/), alsa_stream->buffer_size, new_period); ++ audio_warning("updating pos cur: %d + %d max:%d new_period:%d\n", ++ alsa_stream->pos, ++ (consumed /** AUDIO_IPC_BLOCK_BUFFER_SIZE*/ ), ++ alsa_stream->buffer_size, new_period); + if (alsa_stream->buffer_size) { + alsa_stream->pos += consumed; + alsa_stream->pos %= alsa_stream->buffer_size; +- } ++ } + if (alsa_stream->substream) { + if (new_period) + snd_pcm_period_elapsed(alsa_stream->substream); +@@ -96,7 +98,9 @@ + idx = substream->number; + + if (idx > MAX_SUBSTREAMS) { +- audio_error("substream(%d) device doesn't exist max(%d) substreams allowed\n", idx, MAX_SUBSTREAMS); ++ audio_error ++ ("substream(%d) device doesn't exist max(%d) substreams allowed\n", ++ idx, MAX_SUBSTREAMS); + err = -ENODEV; + goto out; + } +@@ -117,6 +121,7 @@ + /* Initialise alsa_stream */ + alsa_stream->chip = chip; + alsa_stream->substream = substream; ++ alsa_stream->idx = idx; + chip->alsa_stream[idx] = alsa_stream; + + sema_init(&alsa_stream->buffers_update_sem, 0); +@@ -132,7 +137,8 @@ + runtime->hw = snd_bcm2835_playback_hw; + + /* minimum 16 bytes alignment (for vchiq bulk transfers) */ +- snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 16); ++ snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES, ++ 16); + + err = bcm2835_audio_open(alsa_stream); + if (err != 0) { +@@ -179,7 +185,8 @@ + alsa_stream->open = 0; + bcm2835_audio_close(alsa_stream); + } +- ++ if (alsa_stream->chip) ++ alsa_stream->chip->alsa_stream[alsa_stream->idx] = NULL; + /* + * Do not free up alsa_stream here, it will be freed up by + * runtime->private_free callback we registered in *_open above +@@ -192,23 +199,26 @@ + + /* hw_params callback */ + static int snd_bcm2835_pcm_hw_params(struct snd_pcm_substream *substream, +- struct snd_pcm_hw_params *params) ++ struct snd_pcm_hw_params *params) + { + int err; + struct snd_pcm_runtime *runtime = substream->runtime; +- bcm2835_alsa_stream_t *alsa_stream = (bcm2835_alsa_stream_t *)runtime->private_data; ++ bcm2835_alsa_stream_t *alsa_stream = ++ (bcm2835_alsa_stream_t *) runtime->private_data; + + audio_debug(" .. IN\n"); + +- err = snd_pcm_lib_malloc_pages(substream, +- params_buffer_bytes(params)); ++ err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(params)); + if (err < 0) { +- audio_error(" pcm_lib_malloc failed to allocated pages for buffers\n"); ++ audio_error ++ (" pcm_lib_malloc failed to allocated pages for buffers\n"); + return err; + } + + err = bcm2835_audio_set_params(alsa_stream, params_channels(params), +- params_rate(params), snd_pcm_format_width(params_format(params))); ++ params_rate(params), ++ snd_pcm_format_width(params_format ++ (params))); + if (err < 0) { + audio_error(" error setting hw params\n"); + } +@@ -238,7 +248,9 @@ + alsa_stream->period_size = snd_pcm_lib_period_bytes(substream); + alsa_stream->pos = 0; + +- audio_warning("buffer_size=%d, period_size=%d pos=%d frame_bits=%d\n", alsa_stream->buffer_size, alsa_stream->period_size, alsa_stream->pos, runtime->frame_bits); ++ audio_warning("buffer_size=%d, period_size=%d pos=%d frame_bits=%d\n", ++ alsa_stream->buffer_size, alsa_stream->period_size, ++ alsa_stream->pos, runtime->frame_bits); + + audio_debug(" .. OUT\n"); + return 0; +@@ -254,38 +266,38 @@ + audio_debug(" .. IN\n"); + + switch (cmd) { +- case SNDRV_PCM_TRIGGER_START: +- audio_warning("bcm2835_AUDIO_TRIGGER_START running=%d\n", alsa_stream->running); +- if (!alsa_stream->running) { +- err = bcm2835_audio_start(alsa_stream); +- if (err == 0) +- { +- alsa_stream->running = 1; +- alsa_stream->draining = 1; +- } +- } +- break; +- case SNDRV_PCM_TRIGGER_STOP: +- audio_warning("bcm2835_AUDIO_TRIGGER_STOP running=%d draining=%d\n", runtime->status->state==SNDRV_PCM_STATE_DRAINING, alsa_stream->running); +- if (runtime->status->state==SNDRV_PCM_STATE_DRAINING) +- { +- audio_info("DRAINING\n"); ++ case SNDRV_PCM_TRIGGER_START: ++ audio_warning("bcm2835_AUDIO_TRIGGER_START running=%d\n", ++ alsa_stream->running); ++ if (!alsa_stream->running) { ++ err = bcm2835_audio_start(alsa_stream); ++ if (err == 0) { ++ alsa_stream->running = 1; + alsa_stream->draining = 1; + } +- else +- { +- audio_info("DROPPING\n"); +- alsa_stream->draining=0; +- } +- if (alsa_stream->running) { +- err = bcm2835_audio_stop(alsa_stream); +- if (err != 0) +- audio_error(" Failed to STOP alsa device\n"); +- alsa_stream->running = 0; +- } +- break; +- default: +- err = -EINVAL; ++ } ++ break; ++ case SNDRV_PCM_TRIGGER_STOP: ++ audio_warning ++ ("bcm2835_AUDIO_TRIGGER_STOP running=%d draining=%d\n", ++ runtime->status->state == SNDRV_PCM_STATE_DRAINING, ++ alsa_stream->running); ++ if (runtime->status->state == SNDRV_PCM_STATE_DRAINING) { ++ audio_info("DRAINING\n"); ++ alsa_stream->draining = 1; ++ } else { ++ audio_info("DROPPING\n"); ++ alsa_stream->draining = 0; ++ } ++ if (alsa_stream->running) { ++ err = bcm2835_audio_stop(alsa_stream); ++ if (err != 0) ++ audio_error(" Failed to STOP alsa device\n"); ++ alsa_stream->running = 0; ++ } ++ break; ++ default: ++ err = -EINVAL; + } + + audio_debug(" .. OUT\n"); +@@ -302,77 +314,98 @@ + audio_debug(" .. IN\n"); + + audio_warning("pcm_pointer... (%d) hwptr=%d appl=%d pos=%d\n", 0, +- frames_to_bytes(runtime, runtime->status->hw_ptr), frames_to_bytes(runtime, runtime->control->appl_ptr), alsa_stream->pos); ++ frames_to_bytes(runtime, runtime->status->hw_ptr), ++ frames_to_bytes(runtime, runtime->control->appl_ptr), ++ alsa_stream->pos); + + audio_debug(" .. OUT\n"); + return bytes_to_frames(runtime, alsa_stream->pos); + } + +-static int snd_bcm2835_pcm_copy(struct snd_pcm_substream *substream, int channel, +- snd_pcm_uframes_t pos, void *src, snd_pcm_uframes_t count) ++static int snd_bcm2835_pcm_copy(struct snd_pcm_substream *substream, ++ int channel, snd_pcm_uframes_t pos, void *src, ++ snd_pcm_uframes_t count) + { + int ret; + struct snd_pcm_runtime *runtime = substream->runtime; + bcm2835_alsa_stream_t *alsa_stream = runtime->private_data; + + audio_debug(" .. IN\n"); +- audio_warning("copy.......... (%d) hwptr=%d appl=%d pos=%d\n", frames_to_bytes(runtime, count), +- frames_to_bytes(runtime, runtime->status->hw_ptr), frames_to_bytes(runtime, runtime->control->appl_ptr), alsa_stream->pos); +- ret = bcm2835_audio_write(alsa_stream, frames_to_bytes(runtime, count), src); ++ audio_warning("copy.......... (%d) hwptr=%d appl=%d pos=%d\n", ++ frames_to_bytes(runtime, count), frames_to_bytes(runtime, ++ runtime-> ++ status-> ++ hw_ptr), ++ frames_to_bytes(runtime, runtime->control->appl_ptr), ++ alsa_stream->pos); ++ ret = ++ bcm2835_audio_write(alsa_stream, frames_to_bytes(runtime, count), ++ src); + audio_debug(" .. OUT\n"); + return ret; + } + +-static int snd_bcm2835_pcm_silence(struct snd_pcm_substream *substream, int channel, +- snd_pcm_uframes_t post, snd_pcm_uframes_t count) ++static int snd_bcm2835_pcm_silence(struct snd_pcm_substream *substream, ++ int channel, snd_pcm_uframes_t post, ++ snd_pcm_uframes_t count) + { + int ret; + struct snd_pcm_runtime *runtime = substream->runtime; + bcm2835_alsa_stream_t *alsa_stream = runtime->private_data; + + audio_debug(" .. IN\n"); +- audio_warning("silence....... (%d) hwptr=%d appl=%d pos=%d\n", frames_to_bytes(runtime, count), +- frames_to_bytes(runtime, runtime->status->hw_ptr), frames_to_bytes(runtime, runtime->control->appl_ptr), alsa_stream->pos); +- ret = bcm2835_audio_write(alsa_stream, frames_to_bytes(runtime, count), NULL); ++ audio_warning("silence....... (%d) hwptr=%d appl=%d pos=%d\n", ++ frames_to_bytes(runtime, count), frames_to_bytes(runtime, ++ runtime-> ++ status-> ++ hw_ptr), ++ frames_to_bytes(runtime, runtime->control->appl_ptr), ++ alsa_stream->pos); ++ ret = ++ bcm2835_audio_write(alsa_stream, frames_to_bytes(runtime, count), ++ NULL); + audio_debug(" .. OUT\n"); + return ret; + } + +-static int snd_bcm2835_pcm_lib_ioctl ( struct snd_pcm_substream * substream, unsigned int cmd, void * arg) ++static int snd_bcm2835_pcm_lib_ioctl(struct snd_pcm_substream *substream, ++ unsigned int cmd, void *arg) + { + int ret = snd_pcm_lib_ioctl(substream, cmd, arg); +- audio_debug(" .. substream=%p, cmd=%d, arg=%p (%x) ret=%d\n", substream, cmd, arg, arg ? *(unsigned *)arg:0, ret); ++ audio_debug(" .. substream=%p, cmd=%d, arg=%p (%x) ret=%d\n", substream, ++ cmd, arg, arg ? *(unsigned *)arg : 0, ret); + return ret; + } +- ++ + /* operators */ + static struct snd_pcm_ops snd_bcm2835_playback_ops = { +- .open = snd_bcm2835_playback_open, +- .close = snd_bcm2835_playback_close, +- .ioctl = snd_bcm2835_pcm_lib_ioctl, +- .hw_params = snd_bcm2835_pcm_hw_params, +- .hw_free = snd_bcm2835_pcm_hw_free, +- .prepare = snd_bcm2835_pcm_prepare, +- .trigger = snd_bcm2835_pcm_trigger, +- .pointer = snd_bcm2835_pcm_pointer, +- .copy = snd_bcm2835_pcm_copy, +- .silence = snd_bcm2835_pcm_silence, ++ .open = snd_bcm2835_playback_open, ++ .close = snd_bcm2835_playback_close, ++ .ioctl = snd_bcm2835_pcm_lib_ioctl, ++ .hw_params = snd_bcm2835_pcm_hw_params, ++ .hw_free = snd_bcm2835_pcm_hw_free, ++ .prepare = snd_bcm2835_pcm_prepare, ++ .trigger = snd_bcm2835_pcm_trigger, ++ .pointer = snd_bcm2835_pcm_pointer, ++ .copy = snd_bcm2835_pcm_copy, ++ .silence = snd_bcm2835_pcm_silence, + }; + + /* create a pcm device */ +-int __devinit snd_bcm2835_new_pcm(bcm2835_chip_t *chip) ++int __devinit snd_bcm2835_new_pcm(bcm2835_chip_t * chip) + { + struct snd_pcm *pcm; + int err; + + audio_debug(" .. IN\n"); +- err = snd_pcm_new(chip->card, "bcm2835 ALSA", 0, MAX_SUBSTREAMS, 0, &pcm); +- if (err < 0) ++ err = ++ snd_pcm_new(chip->card, "bcm2835 ALSA", 0, MAX_SUBSTREAMS, 0, &pcm); ++ if (err < 0) + return err; + pcm->private_data = chip; + strcpy(pcm->name, "bcm2835 ALSA"); + chip->pcm = pcm; +- chip->dest = AUDIO_DEST_LOCAL; ++ chip->dest = AUDIO_DEST_AUTO; + chip->volume = 100; + /* set operators */ + snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, +@@ -381,11 +414,11 @@ + /* pre-allocation of buffers */ + /* NOTE: this may fail */ + snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_CONTINUOUS, +- snd_dma_continuous_data(GFP_KERNEL), 64*1024, 64*1024); ++ snd_dma_continuous_data ++ (GFP_KERNEL), 64 * 1024, ++ 64 * 1024); + + audio_debug(" .. OUT\n"); + + return 0; + } +- +- +Index: linux-3.2.46/sound/arm/bcm2835-vchiq.c +=================================================================== +--- linux-3.2.46.orig/sound/arm/bcm2835-vchiq.c 2013-07-26 19:32:31.000000000 +0000 ++++ linux-3.2.46/sound/arm/bcm2835-vchiq.c 2013-07-26 19:32:35.000000000 +0000 +@@ -29,27 +29,26 @@ + + #include "bcm2835.h" + +- +-// ---- Include Files -------------------------------------------------------- ++/* ---- Include Files -------------------------------------------------------- */ + + #include "interface/vchi/vchi.h" + #include "interface/vcos/vcos.h" + #include "interface/vcos/vcos_logging.h" + #include "vc_vchi_audioserv_defs.h" + +-// ---- Private Constants and Types ------------------------------------------ ++/* ---- Private Constants and Types ------------------------------------------ */ + +-// VCOS logging category for this service ++/* VCOS logging category for this service */ + #define VCOS_LOG_CATEGORY (&audio_log_category) + +-// Default VCOS logging level ++/* Default VCOS logging level */ + #define LOG_LEVEL VCOS_LOG_TRACE + +-// Logging macros (for remapping to other logging mechanisms, i.e., printf) +-#define LOG_ERR( fmt, arg... ) pr_err(fmt, ##arg) //vcos_log_error( fmt, ##arg ) +-#define LOG_WARN( fmt, arg... ) pr_err(fmt, ##arg) //vcos_log_warn( fmt, ##arg ) +-#define LOG_INFO( fmt, arg... ) pr_err(fmt, ##arg) //vcos_log_info( fmt, ##arg ) +-#define LOG_DBG( fmt, arg... ) pr_err( fmt, ##arg ) ++/* Logging macros (for remapping to other logging mechanisms, i.e., printf) */ ++#define LOG_ERR( fmt, arg... ) vcos_log_error( "%s:%d " fmt, __func__, __LINE__, ##arg) ++#define LOG_WARN( fmt, arg... ) vcos_log_warn( "%s:%d " fmt, __func__, __LINE__, ##arg) ++#define LOG_INFO( fmt, arg... ) vcos_log_info( "%s:%d " fmt, __func__, __LINE__, ##arg) ++#define LOG_DBG( fmt, arg... ) vcos_log_info( "%s:%d " fmt, __func__, __LINE__, ##arg) + + typedef struct opaque_AUDIO_INSTANCE_T { + uint32_t num_connections; +@@ -58,176 +57,150 @@ + VCOS_MUTEX_T vchi_mutex; + bcm2835_alsa_stream_t *alsa_stream; + int32_t result, got_result; +- atomic_t callbacks_expected, callbacks_received; + } AUDIO_INSTANCE_T; + +-// ---- Private Variables ---------------------------------------------------- ++/* ---- Private Variables ---------------------------------------------------- */ + +-// VCOS logging category for this service ++/* VCOS logging category for this service */ + static VCOS_LOG_CAT_T audio_log_category; + +-// ---- Private Function Prototypes ------------------------------------------ ++/* ---- Private Function Prototypes ------------------------------------------ */ + +-// ---- Private Functions ---------------------------------------------------- ++/* ---- Private Functions ---------------------------------------------------- */ + + static int bcm2835_audio_stop_worker(bcm2835_alsa_stream_t * alsa_stream); + static int bcm2835_audio_start_worker(bcm2835_alsa_stream_t * alsa_stream); + +-#if 1 + typedef struct { +- struct work_struct my_work; +- bcm2835_alsa_stream_t *alsa_stream; +- int x; ++ struct work_struct my_work; ++ bcm2835_alsa_stream_t *alsa_stream; ++ int x; + } my_work_t; + +-static void my_wq_function( struct work_struct *work) ++static void my_wq_function(struct work_struct *work) + { +- my_work_t *w = (my_work_t *)work; +- int ret=-9; +- audio_debug(" .. IN %p:%d\n", w->alsa_stream, w->x); +- switch (w->x) { +- case 1: ret=bcm2835_audio_start_worker(w->alsa_stream); break; +- case 2: ret=bcm2835_audio_stop_worker(w->alsa_stream); break; +- default: audio_error(" Unexpected work: %p:%d\n", w->alsa_stream, w->x); break; +- } +- kfree( (void *)work ); +- audio_debug(" .. OUT %d\n", ret); +-} +- +-int bcm2835_audio_start(bcm2835_alsa_stream_t *alsa_stream) +-{ +- int ret = -1; +- audio_debug(" .. IN\n"); +- if (alsa_stream->my_wq) { +- my_work_t *work = kmalloc(sizeof(my_work_t), GFP_KERNEL); +- /* Queue some work (item 1) */ +- if (work) { +- INIT_WORK( (struct work_struct *)work, my_wq_function ); +- work->alsa_stream = alsa_stream; +- work->x = 1; +- if (queue_work( alsa_stream->my_wq, (struct work_struct *)work )) +- ret = 0; +- } else +- audio_error(" .. Error: NULL work kmalloc\n"); +- } +- audio_debug(" .. OUT %d\n", ret); +- return ret; ++ my_work_t *w = (my_work_t *) work; ++ int ret = -9; ++ LOG_DBG(" .. IN %p:%d\n", w->alsa_stream, w->x); ++ switch (w->x) { ++ case 1: ++ ret = bcm2835_audio_start_worker(w->alsa_stream); ++ break; ++ case 2: ++ ret = bcm2835_audio_stop_worker(w->alsa_stream); ++ break; ++ default: ++ LOG_ERR(" Unexpected work: %p:%d\n", w->alsa_stream, w->x); ++ break; ++ } ++ kfree((void *)work); ++ LOG_DBG(" .. OUT %d\n", ret); + } + +-int bcm2835_audio_stop(bcm2835_alsa_stream_t * alsa_stream) ++int bcm2835_audio_start(bcm2835_alsa_stream_t * alsa_stream) + { +- int ret = -1; +- audio_debug(" .. IN\n"); +- if (alsa_stream->my_wq) { +- my_work_t *work = kmalloc(sizeof(my_work_t), GFP_KERNEL); +- /* Queue some work (item 1) */ +- if (work) { +- INIT_WORK( (struct work_struct *)work, my_wq_function ); +- work->alsa_stream = alsa_stream; +- work->x = 2; +- if (queue_work( alsa_stream->my_wq, (struct work_struct *)work )) +- ret = 0; +- } else +- audio_error(" .. Error: NULL work kmalloc\n"); +- } +- audio_debug(" .. OUT %d\n", ret); +- return ret; ++ int ret = -1; ++ LOG_DBG(" .. IN\n"); ++ if (alsa_stream->my_wq) { ++ my_work_t *work = kmalloc(sizeof(my_work_t), GFP_KERNEL); ++ /* Queue some work (item 1) */ ++ if (work) { ++ INIT_WORK((struct work_struct *)work, my_wq_function); ++ work->alsa_stream = alsa_stream; ++ work->x = 1; ++ if (queue_work ++ (alsa_stream->my_wq, (struct work_struct *)work)) ++ ret = 0; ++ } else ++ LOG_ERR(" .. Error: NULL work kmalloc\n"); ++ } ++ LOG_DBG(" .. OUT %d\n", ret); ++ return ret; + } + +-void my_workqueue_init(bcm2835_alsa_stream_t * alsa_stream) ++int bcm2835_audio_stop(bcm2835_alsa_stream_t * alsa_stream) + { +- alsa_stream->my_wq = create_workqueue("my_queue"); ++ int ret = -1; ++ LOG_DBG(" .. IN\n"); ++ if (alsa_stream->my_wq) { ++ my_work_t *work = kmalloc(sizeof(my_work_t), GFP_KERNEL); ++ /* Queue some work (item 1) */ ++ if (work) { ++ INIT_WORK((struct work_struct *)work, my_wq_function); ++ work->alsa_stream = alsa_stream; ++ work->x = 2; ++ if (queue_work ++ (alsa_stream->my_wq, (struct work_struct *)work)) ++ ret = 0; ++ } else ++ LOG_ERR(" .. Error: NULL work kmalloc\n"); ++ } ++ LOG_DBG(" .. OUT %d\n", ret); ++ return ret; + } + +-void my_workqueue_quit(bcm2835_alsa_stream_t * alsa_stream) ++void my_workqueue_init(bcm2835_alsa_stream_t * alsa_stream) + { +- if (alsa_stream->my_wq) { +- flush_workqueue( alsa_stream->my_wq ); +- destroy_workqueue( alsa_stream->my_wq ); +- alsa_stream->my_wq = NULL; +- } +-} +- +-#else +-static void *my_tasklet_data; +- +-/* Bottom Half Function */ +-void my_tasklet_function( unsigned long data ) +-{ +- int err = 0; +- bcm2835_alsa_stream_t *alsa_stream = (bcm2835_alsa_stream_t *)my_tasklet_data; +- audio_info("IN ..(%d)\n", (int)data); +- if (data) +- err = bcm2835_audio_stop_worker(alsa_stream); +- else +- err = bcm2835_audio_start_worker(alsa_stream); +- if (err != 0) +- audio_error(" Failed to START/STOP alsa device\n"); +- audio_info("OUT ..\n"); ++ alsa_stream->my_wq = create_workqueue("my_queue"); + } + +-DECLARE_TASKLET( my_tasklet_start, my_tasklet_function, 0); +-DECLARE_TASKLET( my_tasklet_stop, my_tasklet_function, 1); +- +- +-int bcm2835_audio_start(bcm2835_alsa_stream_t * alsa_stream) +-{ +- my_tasklet_data = alsa_stream; +- tasklet_schedule( &my_tasklet_stop ); +- +-} +-int bcm2835_audio_stop(bcm2835_alsa_stream_t * alsa_stream) ++void my_workqueue_quit(bcm2835_alsa_stream_t * alsa_stream) + { +- my_tasklet_data = alsa_stream; +- tasklet_schedule( &my_tasklet_start ); ++ if (alsa_stream->my_wq) { ++ flush_workqueue(alsa_stream->my_wq); ++ destroy_workqueue(alsa_stream->my_wq); ++ alsa_stream->my_wq = NULL; ++ } + } +-void my_workqueue_init(bcm2835_alsa_stream_t * alsa_stream){} +-void my_workqueue_quit(bcm2835_alsa_stream_t * alsa_stream){} + +-#endif + static void audio_vchi_callback(void *param, + const VCHI_CALLBACK_REASON_T reason, + void *msg_handle) + { +- AUDIO_INSTANCE_T *instance = (AUDIO_INSTANCE_T *)param; ++ AUDIO_INSTANCE_T *instance = (AUDIO_INSTANCE_T *) param; + int32_t status; + int32_t msg_len; + VC_AUDIO_MSG_T m; + bcm2835_alsa_stream_t *alsa_stream = 0; +- audio_debug(" .. IN instance=%p, param=%p, reason=%d, handle=%p outstanding_completes=%d\n", instance, param, reason, msg_handle, atomic_read(&instance->callbacks_expected)-atomic_read(&instance->callbacks_received)); ++ LOG_DBG(" .. IN instance=%p, param=%p, reason=%d, handle=%p\n", ++ instance, param, reason, msg_handle); + + if (!instance || reason != VCHI_CALLBACK_MSG_AVAILABLE) { + return; + } + alsa_stream = instance->alsa_stream; + status = vchi_msg_dequeue(instance->vchi_handle[0], +- &m, sizeof m, &msg_len, VCHI_FLAGS_NONE); ++ &m, sizeof m, &msg_len, VCHI_FLAGS_NONE); + if (m.type == VC_AUDIO_MSG_TYPE_RESULT) { +- audio_debug(" .. instance=%p, m.type=VC_AUDIO_MSG_TYPE_RESULT, success=%d\n", instance, m.u.result.success); ++ LOG_DBG ++ (" .. instance=%p, m.type=VC_AUDIO_MSG_TYPE_RESULT, success=%d\n", ++ instance, m.u.result.success); + BUG_ON(instance->got_result); + instance->result = m.u.result.success; + instance->got_result = 1; + vcos_event_signal(&instance->msg_avail_event); + } else if (m.type == VC_AUDIO_MSG_TYPE_COMPLETE) { +- irq_handler_t callback = (irq_handler_t)m.u.complete.callback; +- audio_debug(" .. instance=%p, m.type=VC_AUDIO_MSG_TYPE_COMPLETE, complete=%d\n", instance, m.u.complete.count); ++ irq_handler_t callback = (irq_handler_t) m.u.complete.callback; ++ LOG_DBG ++ (" .. instance=%p, m.type=VC_AUDIO_MSG_TYPE_COMPLETE, complete=%d\n", ++ instance, m.u.complete.count); + if (alsa_stream && callback) { + atomic_add(m.u.complete.count, &alsa_stream->retrieved); + callback(0, alsa_stream); + } else { +- audio_debug(" .. unexpected alsa_stream=%p, callback=%p\n", alsa_stream, callback); ++ LOG_DBG(" .. unexpected alsa_stream=%p, callback=%p\n", ++ alsa_stream, callback); + } +- atomic_inc(&instance->callbacks_received); +- //BUG_ON(atomic_read(&instance->callbacks_expected)-atomic_read(&instance->callbacks_received) < 0); + vcos_event_signal(&instance->msg_avail_event); + } else { +- audio_debug(" .. unexpected m.type=%d\n", m.type); ++ LOG_DBG(" .. unexpected m.type=%d\n", m.type); + } + } + + static AUDIO_INSTANCE_T *vc_vchi_audio_init(VCHI_INSTANCE_T vchi_instance, +- VCHI_CONNECTION_T ** vchi_connections, +- uint32_t num_connections) ++ VCHI_CONNECTION_T ** ++ vchi_connections, ++ uint32_t num_connections) + { + uint32_t i; + AUDIO_INSTANCE_T *instance; +@@ -241,12 +214,12 @@ + + return NULL; + } +- // Allocate memory for this instance ++ /* Allocate memory for this instance */ + instance = vcos_malloc(sizeof(*instance), "audio_instance"); + memset(instance, 0, sizeof(*instance)); + + instance->num_connections = num_connections; +- // Create the message available event ++ /* Create the message available event */ + status = + vcos_event_create(&instance->msg_avail_event, "audio_msg_avail"); + if (status != VCOS_SUCCESS) { +@@ -255,7 +228,7 @@ + + goto err_free_mem; + } +- // Create a lock for exclusive, serialized VCHI connection access ++ /* Create a lock for exclusive, serialized VCHI connection access */ + status = vcos_mutex_create(&instance->vchi_mutex, "audio_vchi_mutex"); + if (status != VCOS_SUCCESS) { + LOG_ERR("%s: failed to create event (status=%d)", __func__, +@@ -263,7 +236,7 @@ + + goto err_delete_event; + } +- // Open the VCHI service connections ++ /* Open the VCHI service connections */ + for (i = 0; i < num_connections; i++) { + SERVICE_CREATION_T params = { + VC_AUDIO_SERVER_NAME, // 4cc service code +@@ -272,8 +245,8 @@ + 0, // tx fifo size (unused) + audio_vchi_callback, // service callback + instance, // service callback parameter +- VCOS_TRUE, //TODO: remove VCOS_FALSE, // unaligned bulk recieves +- VCOS_TRUE, //TODO: remove VCOS_FALSE, // unaligned bulk transmits ++ VCOS_TRUE, //TODO: remove VCOS_FALSE, // unaligned bulk recieves ++ VCOS_TRUE, //TODO: remove VCOS_FALSE, // unaligned bulk transmits + VCOS_FALSE // want crc check on bulk transfers + }; + +@@ -286,7 +259,7 @@ + + goto err_close_services; + } +- // Finished with the service for now ++ /* Finished with the service for now */ + vchi_service_release(instance->vchi_handle[i]); + } + +@@ -308,11 +281,11 @@ + return NULL; + } + +-static int32_t vc_vchi_audio_deinit(AUDIO_INSTANCE_T *instance) ++static int32_t vc_vchi_audio_deinit(AUDIO_INSTANCE_T * instance) + { + uint32_t i; + +- audio_debug(" .. IN\n"); ++ LOG_DBG(" .. IN\n"); + + if (instance == NULL) { + LOG_ERR("%s: invalid handle %p", __func__, instance); +@@ -320,13 +293,13 @@ + return -1; + } + +- audio_debug(" .. about to lock (%d)\n", instance->num_connections); ++ LOG_DBG(" .. about to lock (%d)\n", instance->num_connections); + vcos_mutex_lock(&instance->vchi_mutex); + +- // Close all VCHI service connections ++ /* Close all VCHI service connections */ + for (i = 0; i < instance->num_connections; i++) { + int32_t success; +- audio_debug(" .. %i:closing %p\n", i, instance->vchi_handle[i]); ++ LOG_DBG(" .. %i:closing %p\n", i, instance->vchi_handle[i]); + vchi_service_use(instance->vchi_handle[i]); + + success = vchi_service_close(instance->vchi_handle[i]); +@@ -345,35 +318,34 @@ + + vcos_free(instance); + +- // Unregister the log category so we can add it back next time ++ /* Unregister the log category so we can add it back next time */ + vcos_log_unregister(&audio_log_category); + +- audio_debug(" .. OUT\n"); ++ LOG_DBG(" .. OUT\n"); + + return 0; + } + + static int bcm2835_audio_open_connection(bcm2835_alsa_stream_t * alsa_stream) + { +- int ret = 0, err; + static VCHI_INSTANCE_T vchi_instance; + static VCHI_CONNECTION_T *vchi_connection; + AUDIO_INSTANCE_T *instance = alsa_stream->instance; +- audio_debug(" .. IN\n"); ++ int ret; ++ LOG_DBG(" .. IN\n"); + + LOG_INFO("%s: start", __func__); + //BUG_ON(instance); + if (instance) { + LOG_ERR("%s: VCHI instance already open (%p)", + __func__, instance); +- //BUG_ON(atomic_read(&instance->callbacks_expected)-atomic_read(&instance->callbacks_received) < 0); + instance->alsa_stream = alsa_stream; + alsa_stream->instance = instance; +- ret = 0; // xxx todo -1; ++ ret = 0; // xxx todo -1; + goto err_free_mem; + } + +- // Initialize and create a VCHI connection ++ /* Initialize and create a VCHI connection */ + ret = vchi_initialise(&vchi_instance); + if (ret != 0) { + LOG_ERR("%s: failed to initialise VCHI instance (ret=%d)", +@@ -391,17 +363,15 @@ + goto err_free_mem; + } + +- // Set up the VCOS logging ++ /* Set up the VCOS logging */ + vcos_log_set_level(VCOS_LOG_CATEGORY, LOG_LEVEL); + vcos_log_register("audio", VCOS_LOG_CATEGORY); + +- +- // Initialize an instance of the audio service ++ /* Initialize an instance of the audio service */ + instance = vc_vchi_audio_init(vchi_instance, &vchi_connection, 1); + +- if (instance == NULL /*|| audio_handle != instance*/) { +- LOG_ERR("%s: failed to initialize audio service", +- __func__); ++ if (instance == NULL /*|| audio_handle != instance */ ) { ++ LOG_ERR("%s: failed to initialize audio service", __func__); + + ret = -EPERM; + goto err_free_mem; +@@ -410,10 +380,9 @@ + instance->alsa_stream = alsa_stream; + alsa_stream->instance = instance; + +- +- audio_debug(" success !\n"); ++ LOG_DBG(" success !\n"); + err_free_mem: +- audio_debug(" .. OUT\n"); ++ LOG_DBG(" .. OUT\n"); + + return ret; + } +@@ -424,11 +393,11 @@ + VC_AUDIO_MSG_T m; + int32_t success; + int ret; +- audio_debug(" .. IN\n"); ++ LOG_DBG(" .. IN\n"); + + my_workqueue_init(alsa_stream); + +- ret = bcm2835_audio_open_connection(alsa_stream); ++ ret = bcm2835_audio_open_connection(alsa_stream); + if (ret != 0) { + ret = -1; + goto exit; +@@ -440,7 +409,7 @@ + + m.type = VC_AUDIO_MSG_TYPE_OPEN; + +- // Send the message to the videocore ++ /* Send the message to the videocore */ + success = vchi_msg_queue(instance->vchi_handle[0], + &m, sizeof m, + VCHI_FLAGS_BLOCK_UNTIL_QUEUED, NULL); +@@ -459,40 +428,21 @@ + vchi_service_release(instance->vchi_handle[0]); + vcos_mutex_unlock(&instance->vchi_mutex); + exit: +- audio_debug(" .. OUT\n"); ++ LOG_DBG(" .. OUT\n"); + return ret; + } + +- +-int bcm2835_audio_set_params(bcm2835_alsa_stream_t * alsa_stream, +- uint32_t channels, uint32_t samplerate, +- uint32_t bps) ++static int bcm2835_audio_set_ctls_chan(bcm2835_alsa_stream_t * alsa_stream, ++ bcm2835_chip_t * chip) + { + VC_AUDIO_MSG_T m; + AUDIO_INSTANCE_T *instance = alsa_stream->instance; + int32_t success; +- uint32_t msg_len; + int ret; +- audio_debug(" .. IN\n"); +- +- if (channels < 1 || channels > 2) { +- audio_error(" channels (%d) not supported\n", channels); +- return -EINVAL; +- } +- +- if (samplerate < 8000 || samplerate > 48000) { +- audio_error(" samplerate (%d) not supported\n", samplerate); +- return -EINVAL; +- } +- +- if (bps != 8 && bps != 16) { +- audio_error(" Bits per sample (%d) not supported\n", bps); +- return -EINVAL; +- } ++ LOG_DBG(" .. IN\n"); + +- audio_info +- (" Setting ALSA channels(%d), samplerate(%d), bits-per-sample(%d)\n", +- channels, samplerate, bps); ++ LOG_INFO ++ (" Setting ALSA dest(%d), volume(%d)\n", chip->dest, chip->volume); + + vcos_mutex_lock(&instance->vchi_mutex); + vchi_service_use(instance->vchi_handle[0]); +@@ -500,12 +450,11 @@ + instance->got_result = 0; + instance->result = -1; + +- m.type = VC_AUDIO_MSG_TYPE_CONFIG; +- m.u.config.channels = channels; +- m.u.config.samplerate = samplerate; +- m.u.config.bps = bps; ++ m.type = VC_AUDIO_MSG_TYPE_CONTROL; ++ m.u.control.dest = chip->dest; ++ m.u.control.volume = chip->volume; + +- // Send the message to the videocore ++ /* Send the message to the videocore */ + success = vchi_msg_queue(instance->vchi_handle[0], + &m, sizeof m, + VCHI_FLAGS_BLOCK_UNTIL_QUEUED, NULL); +@@ -518,7 +467,7 @@ + goto unlock; + } + +- // We are expecting a reply from the videocore ++ /* We are expecting a reply from the videocore */ + while (!instance->got_result) { + success = vcos_event_wait(&instance->msg_avail_event); + if (success != VCOS_SUCCESS) { +@@ -531,8 +480,7 @@ + } + + if (instance->result != 0) { +- LOG_ERR("%s: result=%d", +- __func__, instance->result); ++ LOG_ERR("%s: result=%d", __func__, instance->result); + + ret = -1; + goto unlock; +@@ -544,34 +492,63 @@ + vchi_service_release(instance->vchi_handle[0]); + vcos_mutex_unlock(&instance->vchi_mutex); + +- audio_debug(" .. OUT\n"); ++ LOG_DBG(" .. OUT\n"); + return ret; + } + +-int bcm2835_audio_setup(bcm2835_alsa_stream_t * alsa_stream) ++int bcm2835_audio_set_ctls(bcm2835_chip_t * chip) + { +- audio_debug(" .. IN\n"); +- +- audio_debug(" .. OUT\n"); +- +- return 0; ++ int i; ++ int ret = 0; ++ LOG_DBG(" .. IN\n"); ++printk(KERN_ERR "set_ctls dest=%d volume=%d\n", chip->dest, chip->volume); ++ /* change ctls for all substreams */ ++ for (i = 0; i < MAX_SUBSTREAMS; i++) { ++ if (chip->avail_substreams & (1 << i)) { ++ if (!chip->alsa_stream[i]) ++ ret = 0; ++ else if (bcm2835_audio_set_ctls_chan ++ (chip->alsa_stream[i], chip) != 0) ++ ret = -1; ++ } ++ } ++ LOG_DBG(" .. OUT ret=%d\n", ret); ++ return ret; + } + +- +-static int bcm2835_audio_start_worker(bcm2835_alsa_stream_t * alsa_stream) ++int bcm2835_audio_set_params(bcm2835_alsa_stream_t * alsa_stream, ++ uint32_t channels, uint32_t samplerate, ++ uint32_t bps) + { + VC_AUDIO_MSG_T m; + AUDIO_INSTANCE_T *instance = alsa_stream->instance; + int32_t success; + int ret; +- audio_debug(" .. IN\n"); ++ LOG_DBG(" .. IN\n"); ++ ++ LOG_INFO ++ (" Setting ALSA channels(%d), samplerate(%d), bits-per-sample(%d)\n", ++ channels, samplerate, bps); ++ ++ /* resend ctls - alsa_stream may not have been open when first send */ ++ ret = bcm2835_audio_set_ctls_chan(alsa_stream, alsa_stream->chip); ++ if (ret != 0) { ++ LOG_ERR(" Alsa controls not supported\n"); ++ return -EINVAL; ++ } + + vcos_mutex_lock(&instance->vchi_mutex); + vchi_service_use(instance->vchi_handle[0]); + +- m.type = VC_AUDIO_MSG_TYPE_START; ++ instance->got_result = 0; ++ instance->result = -1; + +- // Send the message to the videocore ++ m.type = VC_AUDIO_MSG_TYPE_CONFIG; ++ m.u.config.channels = channels; ++ m.u.config.samplerate = samplerate; ++ m.u.config.bps = bps; ++ ++ /* Send the message to the videocore */ + success = vchi_msg_queue(instance->vchi_handle[0], + &m, sizeof m, + VCHI_FLAGS_BLOCK_UNTIL_QUEUED, NULL); +@@ -584,31 +561,58 @@ + goto unlock; + } + ++ /* We are expecting a reply from the videocore */ ++ while (!instance->got_result) { ++ success = vcos_event_wait(&instance->msg_avail_event); ++ if (success != VCOS_SUCCESS) { ++ LOG_ERR("%s: failed on waiting for event (status=%d)", ++ __func__, success); ++ ++ ret = -1; ++ goto unlock; ++ } ++ } ++ ++ if (instance->result != 0) { ++ LOG_ERR("%s: result=%d", __func__, instance->result); ++ ++ ret = -1; ++ goto unlock; ++ } ++ + ret = 0; + + unlock: + vchi_service_release(instance->vchi_handle[0]); + vcos_mutex_unlock(&instance->vchi_mutex); +- audio_debug(" .. OUT\n"); ++ ++ LOG_DBG(" .. OUT\n"); + return ret; + } + ++int bcm2835_audio_setup(bcm2835_alsa_stream_t * alsa_stream) ++{ ++ LOG_DBG(" .. IN\n"); ++ ++ LOG_DBG(" .. OUT\n"); + +-static int bcm2835_audio_stop_worker(bcm2835_alsa_stream_t * alsa_stream) ++ return 0; ++} ++ ++static int bcm2835_audio_start_worker(bcm2835_alsa_stream_t * alsa_stream) + { + VC_AUDIO_MSG_T m; + AUDIO_INSTANCE_T *instance = alsa_stream->instance; + int32_t success; + int ret; +- audio_debug(" .. IN\n"); ++ LOG_DBG(" .. IN\n"); + + vcos_mutex_lock(&instance->vchi_mutex); + vchi_service_use(instance->vchi_handle[0]); + +- m.type = VC_AUDIO_MSG_TYPE_STOP; +- m.u.stop.draining = alsa_stream->draining; ++ m.type = VC_AUDIO_MSG_TYPE_START; + +- // Send the message to the videocore ++ /* Send the message to the videocore */ + success = vchi_msg_queue(instance->vchi_handle[0], + &m, sizeof m, + VCHI_FLAGS_BLOCK_UNTIL_QUEUED, NULL); +@@ -626,26 +630,25 @@ + unlock: + vchi_service_release(instance->vchi_handle[0]); + vcos_mutex_unlock(&instance->vchi_mutex); +- audio_debug(" .. OUT\n"); ++ LOG_DBG(" .. OUT\n"); + return ret; + } + +-int bcm2835_audio_close(bcm2835_alsa_stream_t * alsa_stream) ++static int bcm2835_audio_stop_worker(bcm2835_alsa_stream_t * alsa_stream) + { + VC_AUDIO_MSG_T m; + AUDIO_INSTANCE_T *instance = alsa_stream->instance; + int32_t success; + int ret; +- audio_debug(" .. IN outstanding_completes=%d\n", atomic_read(&instance->callbacks_expected)-atomic_read(&instance->callbacks_received)); +- +- my_workqueue_quit(alsa_stream); ++ LOG_DBG(" .. IN\n"); + + vcos_mutex_lock(&instance->vchi_mutex); + vchi_service_use(instance->vchi_handle[0]); + +- m.type = VC_AUDIO_MSG_TYPE_CLOSE; +- instance->got_result = 0; +- // Send the message to the videocore ++ m.type = VC_AUDIO_MSG_TYPE_STOP; ++ m.u.stop.draining = alsa_stream->draining; ++ ++ /* Send the message to the videocore */ + success = vchi_msg_queue(instance->vchi_handle[0], + &m, sizeof m, + VCHI_FLAGS_BLOCK_UNTIL_QUEUED, NULL); +@@ -657,62 +660,32 @@ + ret = -1; + goto unlock; + } +- while (!instance->got_result /*|| atomic_read(&instance->callbacks_expected)-atomic_read(&instance->callbacks_received) < 0*/ ) { +- success = vcos_event_wait(&instance->msg_avail_event); +- if (success != VCOS_SUCCESS) { +- LOG_ERR("%s: failed on waiting for event (status=%d)", +- __func__, success); +- +- ret = -1; +- goto unlock; +- } +- } +- if (instance->result != 0) { +- LOG_ERR("%s: failed result (status=%d)", +- __func__, instance->result); +- +- ret = -1; +- goto unlock; +- } + + ret = 0; + + unlock: + vchi_service_release(instance->vchi_handle[0]); + vcos_mutex_unlock(&instance->vchi_mutex); +- +- // Stop the audio service +- if (instance) { +- vc_vchi_audio_deinit(instance); +- alsa_stream->instance = NULL; +- } +- audio_debug(" .. OUT\n"); ++ LOG_DBG(" .. OUT\n"); + return ret; + } + +-static int bcm2835_audio_set_ctls_chan(bcm2835_alsa_stream_t *alsa_stream, bcm2835_chip_t *chip) ++int bcm2835_audio_close(bcm2835_alsa_stream_t * alsa_stream) + { + VC_AUDIO_MSG_T m; + AUDIO_INSTANCE_T *instance = alsa_stream->instance; + int32_t success; +- uint32_t msg_len; + int ret; +- audio_debug(" .. IN\n"); ++ LOG_DBG(" .. IN\n"); + +- audio_info +- (" Setting ALSA dest(%d), volume(%d)\n", chip->dest, chip->volume); ++ my_workqueue_quit(alsa_stream); + + vcos_mutex_lock(&instance->vchi_mutex); + vchi_service_use(instance->vchi_handle[0]); + ++ m.type = VC_AUDIO_MSG_TYPE_CLOSE; + instance->got_result = 0; +- instance->result = -1; +- +- m.type = VC_AUDIO_MSG_TYPE_CONTROL; +- m.u.control.dest = chip->dest; +- m.u.control.volume = chip->volume; +- +- // Send the message to the videocore ++ /* Send the message to the videocore */ + success = vchi_msg_queue(instance->vchi_handle[0], + &m, sizeof m, + VCHI_FLAGS_BLOCK_UNTIL_QUEUED, NULL); +@@ -720,12 +693,9 @@ + if (success != 0) { + LOG_ERR("%s: failed on vchi_msg_queue (status=%d)", + __func__, success); +- + ret = -1; + goto unlock; + } +- +- // We are expecting a reply from the videocore + while (!instance->got_result) { + success = vcos_event_wait(&instance->msg_avail_event); + if (success != VCOS_SUCCESS) { +@@ -736,9 +706,8 @@ + goto unlock; + } + } +- + if (instance->result != 0) { +- LOG_ERR("%s: result=%d", ++ LOG_ERR("%s: failed result (status=%d)", + __func__, instance->result); + + ret = -1; +@@ -751,27 +720,12 @@ + vchi_service_release(instance->vchi_handle[0]); + vcos_mutex_unlock(&instance->vchi_mutex); + +- audio_debug(" .. OUT\n"); +- return ret; +-} +- +- +-int bcm2835_audio_set_ctls(bcm2835_chip_t *chip) +-{ +- int i; +- int ret = 0; +- audio_debug(" .. IN\n"); +- +- /* change ctls for all substreams */ +- for (i = 0; i < MAX_SUBSTREAMS; i++) { +- if (chip->avail_substreams & (1 << i)) { +- if (!chip->alsa_stream[i]) +- ret = -1; +- else if (bcm2835_audio_set_ctls_chan(chip->alsa_stream[i], chip) != 0) +- ret = -1; +- } ++ /* Stop the audio service */ ++ if (instance) { ++ vc_vchi_audio_deinit(instance); ++ alsa_stream->instance = NULL; + } +- audio_debug(" .. OUT ret=%d\n", ret); ++ LOG_DBG(" .. OUT\n"); + return ret; + } + +@@ -783,10 +737,9 @@ + int32_t success; + int ret; + +- audio_debug(" .. IN outstanding=%d\n", atomic_read(&instance->callbacks_expected)-atomic_read(&instance->callbacks_received)); ++ LOG_DBG(" .. IN\n"); + +- audio_info +- (" Writing %d bytes from %p\n", count, src); ++ LOG_INFO(" Writing %d bytes from %p\n", count, src); + + vcos_mutex_lock(&instance->vchi_mutex); + vchi_service_use(instance->vchi_handle[0]); +@@ -797,8 +750,7 @@ + m.u.write.cookie = alsa_stream; + m.u.write.silence = src == NULL; + +- atomic_add(1, &instance->callbacks_expected); +- // Send the message to the videocore ++ /* Send the message to the videocore */ + success = vchi_msg_queue(instance->vchi_handle[0], + &m, sizeof m, + VCHI_FLAGS_BLOCK_UNTIL_QUEUED, NULL); +@@ -810,11 +762,14 @@ + ret = -1; + goto unlock; + } +- audio_debug(" ... send header\n"); ++ LOG_DBG(" ... send header\n"); + +- // Send the message to the videocore ++ /* Send the message to the videocore */ + success = vchi_bulk_queue_transmit(instance->vchi_handle[0], +- src, count, 0*VCHI_FLAGS_BLOCK_UNTIL_QUEUED + 1*VCHI_FLAGS_BLOCK_UNTIL_DATA_READ, NULL); ++ src, count, ++ 0 * VCHI_FLAGS_BLOCK_UNTIL_QUEUED + ++ 1 * VCHI_FLAGS_BLOCK_UNTIL_DATA_READ, ++ NULL); + if (success != 0) { + LOG_ERR("%s: failed on vchi_msg_queue (status=%d)", + __func__, success); +@@ -825,12 +780,9 @@ + ret = 0; + + unlock: +- if (ret != 0) { +- atomic_dec(&instance->callbacks_expected); +- } + vchi_service_release(instance->vchi_handle[0]); + vcos_mutex_unlock(&instance->vchi_mutex); +- audio_debug(" .. OUT\n"); ++ LOG_DBG(" .. OUT\n"); + return ret; + } + +@@ -839,8 +791,8 @@ + */ + void bcm2835_audio_flush_buffers(bcm2835_alsa_stream_t * alsa_stream) + { +- audio_debug(" .. IN\n"); +- audio_debug(" .. OUT\n"); ++ LOG_DBG(" .. IN\n"); ++ LOG_DBG(" .. OUT\n"); + return; + } + +@@ -850,14 +802,13 @@ + */ + void bcm2835_audio_flush_playback_buffers(bcm2835_alsa_stream_t * alsa_stream) + { +- audio_debug(" .. IN\n"); +- audio_debug(" .. OUT\n"); ++ LOG_DBG(" .. IN\n"); ++ LOG_DBG(" .. OUT\n"); + } + +-uint32_t bcm2835_audio_retrieve_buffers(bcm2835_alsa_stream_t *alsa_stream) ++uint32_t bcm2835_audio_retrieve_buffers(bcm2835_alsa_stream_t * alsa_stream) + { + uint32_t count = atomic_read(&alsa_stream->retrieved); + atomic_sub(count, &alsa_stream->retrieved); + return count; + } +- +Index: linux-3.2.46/sound/arm/bcm2835.c +=================================================================== +--- linux-3.2.46.orig/sound/arm/bcm2835.c 2013-07-26 19:32:31.000000000 +0000 ++++ linux-3.2.46/sound/arm/bcm2835.c 2013-07-26 19:32:35.000000000 +0000 +@@ -21,9 +21,9 @@ + + /* module parameters (see "Module Parameters") */ + /* SNDRV_CARDS: maximum number of cards supported by this module */ +-static int index[MAX_SUBSTREAMS] = { [0 ... (MAX_SUBSTREAMS - 1)] = -1}; +-static char *id[MAX_SUBSTREAMS] = { [0 ... (MAX_SUBSTREAMS - 1)] = NULL}; +-static int enable[MAX_SUBSTREAMS] = { [0 ... (MAX_SUBSTREAMS - 1)] = 1 }; ++static int index[MAX_SUBSTREAMS] = {[0 ... (MAX_SUBSTREAMS - 1)] = -1 }; ++static char *id[MAX_SUBSTREAMS] = {[0 ... (MAX_SUBSTREAMS - 1)] = NULL }; ++static int enable[MAX_SUBSTREAMS] = {[0 ... (MAX_SUBSTREAMS - 1)] = 1 }; + + /* HACKY global pointers needed for successive probes to work : ssp + * But compared against the changes we will have to do in VC audio_ipc code +@@ -35,13 +35,12 @@ + static struct snd_card *g_card = NULL; + static bcm2835_chip_t *g_chip = NULL; + +-static int snd_bcm2835_free(bcm2835_chip_t *chip) ++static int snd_bcm2835_free(bcm2835_chip_t * chip) + { + kfree(chip); + return 0; + } + +- + /* component-destructor + * (see "Management of Cards and Components") + */ +@@ -50,13 +49,12 @@ + return snd_bcm2835_free(device->device_data); + } + +- + /* chip-specific constructor + * (see "Management of Cards and Components") + */ + static int __devinit snd_bcm2835_create(struct snd_card *card, +- struct platform_device *pdev, +- bcm2835_chip_t **rchip) ++ struct platform_device *pdev, ++ bcm2835_chip_t ** rchip) + { + bcm2835_chip_t *chip; + int err; +@@ -88,9 +86,11 @@ + bcm2835_chip_t *chip; + struct snd_card *card; + int err; +- printk(KERN_INFO"### snd_bcm2835_alsa_probe %p ###", pdev); ++ printk(KERN_INFO "### snd_bcm2835_alsa_probe %p ###", pdev); + +- printk("############ PROBING FOR bcm2835 ALSA device (%d):(%d) ###############\n", dev, enable[dev]); ++ printk ++ ("############ PROBING FOR bcm2835 ALSA device (%d):(%d) ###############\n", ++ dev, enable[dev]); + + if (dev >= MAX_SUBSTREAMS) + return -ENODEV; +@@ -116,21 +116,21 @@ + printk("Creating device/chip ..\n"); + err = snd_bcm2835_create(g_card, pdev, &chip); + if (err < 0) { +- printk(KERN_ERR"Failed to create bcm2835 chip\n"); ++ printk(KERN_ERR "Failed to create bcm2835 chip\n"); + goto out_bcm2835_create; + } + + g_chip = chip; + err = snd_bcm2835_new_pcm(chip); + if (err < 0) { +- printk(KERN_ERR"Failed to create new BCM2835 pcm device\n"); ++ printk(KERN_ERR "Failed to create new BCM2835 pcm device\n"); + goto out_bcm2835_new_pcm; + } + + printk("Adding controls ..\n"); + err = snd_bcm2835_new_ctl(chip); + if (err < 0) { +- printk(KERN_ERR"Failed to create new BCM2835 ctl\n"); ++ printk(KERN_ERR "Failed to create new BCM2835 ctl\n"); + goto out_bcm2835_new_ctl; + } + +@@ -147,7 +147,8 @@ + printk("Registering card ....\n"); + err = snd_card_register(card); + if (err < 0) { +- printk(KERN_ERR"Failed to register bcm2835 ALSA card \n"); ++ printk(KERN_ERR ++ "Failed to register bcm2835 ALSA card \n"); + goto out_card_register; + } + platform_set_drvdata(pdev, card); +@@ -167,11 +168,11 @@ + out_bcm2835_create: + BUG_ON(!g_card); + if (snd_card_free(g_card)) +- printk(KERN_ERR"Failed to free Registered alsa card\n"); ++ printk(KERN_ERR "Failed to free Registered alsa card\n"); + g_card = NULL; + out: +- dev = SNDRV_CARDS; /* stop more avail_substreams from being probed */ +- printk(KERN_ERR"BCM2835 ALSA Probe failed !!\n"); ++ dev = SNDRV_CARDS; /* stop more avail_substreams from being probed */ ++ printk(KERN_ERR "BCM2835 ALSA Probe failed !!\n"); + return err; + } + +@@ -187,14 +188,14 @@ + snd_card_free((struct snd_card *)drv_data); + g_card = NULL; + g_chip = NULL; +- } else { +- idx = (uint32_t)drv_data; ++ } else { ++ idx = (uint32_t) drv_data; + if (g_card != NULL) { + BUG_ON(!g_chip); + /* We pass chip device numbers in audio ipc devices + * other than the one we registered our card with + */ +- idx = (uint32_t)drv_data; ++ idx = (uint32_t) drv_data; + BUG_ON(!idx || idx > MAX_SUBSTREAMS); + g_chip->avail_substreams &= ~(1 << idx); + /* There should be atleast one substream registered +@@ -211,7 +212,8 @@ + } + + #ifdef CONFIG_PM +-static int snd_bcm2835_alsa_suspend(struct platform_device *pdev, pm_message_t state) ++static int snd_bcm2835_alsa_suspend(struct platform_device *pdev, ++ pm_message_t state) + { + return 0; + } +@@ -223,119 +225,110 @@ + + #endif + +-static struct platform_driver bcm2835_alsa0_driver = +-{ +- .probe = snd_bcm2835_alsa_probe, +- .remove = snd_bcm2835_alsa_remove, ++static struct platform_driver bcm2835_alsa0_driver = { ++ .probe = snd_bcm2835_alsa_probe, ++ .remove = snd_bcm2835_alsa_remove, + #ifdef CONFIG_PM +- .suspend = snd_bcm2835_alsa_suspend, +- .resume = snd_bcm2835_alsa_resume, ++ .suspend = snd_bcm2835_alsa_suspend, ++ .resume = snd_bcm2835_alsa_resume, + #endif +- .driver = { +- .name = "bcm2835_AUD0", +- .owner = THIS_MODULE, +- }, ++ .driver = { ++ .name = "bcm2835_AUD0", ++ .owner = THIS_MODULE, ++ }, + }; + +-static struct platform_driver bcm2835_alsa1_driver = +-{ +- .probe = snd_bcm2835_alsa_probe, +- .remove = snd_bcm2835_alsa_remove, ++static struct platform_driver bcm2835_alsa1_driver = { ++ .probe = snd_bcm2835_alsa_probe, ++ .remove = snd_bcm2835_alsa_remove, + #ifdef CONFIG_PM +- .suspend = snd_bcm2835_alsa_suspend, +- .resume = snd_bcm2835_alsa_resume, ++ .suspend = snd_bcm2835_alsa_suspend, ++ .resume = snd_bcm2835_alsa_resume, + #endif +- .driver = { +- .name = "bcm2835_AUD1", +- .owner = THIS_MODULE, +- }, ++ .driver = { ++ .name = "bcm2835_AUD1", ++ .owner = THIS_MODULE, ++ }, + }; + +-static struct platform_driver bcm2835_alsa2_driver = +-{ +- .probe = snd_bcm2835_alsa_probe, +- .remove = snd_bcm2835_alsa_remove, ++static struct platform_driver bcm2835_alsa2_driver = { ++ .probe = snd_bcm2835_alsa_probe, ++ .remove = snd_bcm2835_alsa_remove, + #ifdef CONFIG_PM +- .suspend = snd_bcm2835_alsa_suspend, +- .resume = snd_bcm2835_alsa_resume, ++ .suspend = snd_bcm2835_alsa_suspend, ++ .resume = snd_bcm2835_alsa_resume, + #endif +- .driver = { +- .name = "bcm2835_AUD2", +- .owner = THIS_MODULE, +- }, ++ .driver = { ++ .name = "bcm2835_AUD2", ++ .owner = THIS_MODULE, ++ }, + }; + +-static struct platform_driver bcm2835_alsa3_driver = +-{ +- .probe = snd_bcm2835_alsa_probe, +- .remove = snd_bcm2835_alsa_remove, ++static struct platform_driver bcm2835_alsa3_driver = { ++ .probe = snd_bcm2835_alsa_probe, ++ .remove = snd_bcm2835_alsa_remove, + #ifdef CONFIG_PM +- .suspend = snd_bcm2835_alsa_suspend, +- .resume = snd_bcm2835_alsa_resume, ++ .suspend = snd_bcm2835_alsa_suspend, ++ .resume = snd_bcm2835_alsa_resume, + #endif +- .driver = { +- .name = "bcm2835_AUD3", +- .owner = THIS_MODULE, +- }, ++ .driver = { ++ .name = "bcm2835_AUD3", ++ .owner = THIS_MODULE, ++ }, + }; + +-static struct platform_driver bcm2835_alsa4_driver = +-{ +- .probe = snd_bcm2835_alsa_probe, +- .remove = snd_bcm2835_alsa_remove, ++static struct platform_driver bcm2835_alsa4_driver = { ++ .probe = snd_bcm2835_alsa_probe, ++ .remove = snd_bcm2835_alsa_remove, + #ifdef CONFIG_PM +- .suspend = snd_bcm2835_alsa_suspend, +- .resume = snd_bcm2835_alsa_resume, ++ .suspend = snd_bcm2835_alsa_suspend, ++ .resume = snd_bcm2835_alsa_resume, + #endif +- .driver = { +- .name = "bcm2835_AUD4", +- .owner = THIS_MODULE, +- }, ++ .driver = { ++ .name = "bcm2835_AUD4", ++ .owner = THIS_MODULE, ++ }, + }; + +-static struct platform_driver bcm2835_alsa5_driver = +-{ +- .probe = snd_bcm2835_alsa_probe, +- .remove = snd_bcm2835_alsa_remove, ++static struct platform_driver bcm2835_alsa5_driver = { ++ .probe = snd_bcm2835_alsa_probe, ++ .remove = snd_bcm2835_alsa_remove, + #ifdef CONFIG_PM +- .suspend = snd_bcm2835_alsa_suspend, +- .resume = snd_bcm2835_alsa_resume, ++ .suspend = snd_bcm2835_alsa_suspend, ++ .resume = snd_bcm2835_alsa_resume, + #endif +- .driver = { +- .name = "bcm2835_AUD5", +- .owner = THIS_MODULE, +- }, ++ .driver = { ++ .name = "bcm2835_AUD5", ++ .owner = THIS_MODULE, ++ }, + }; + +-static struct platform_driver bcm2835_alsa6_driver = +-{ +- .probe = snd_bcm2835_alsa_probe, +- .remove = snd_bcm2835_alsa_remove, ++static struct platform_driver bcm2835_alsa6_driver = { ++ .probe = snd_bcm2835_alsa_probe, ++ .remove = snd_bcm2835_alsa_remove, + #ifdef CONFIG_PM +- .suspend = snd_bcm2835_alsa_suspend, +- .resume = snd_bcm2835_alsa_resume, ++ .suspend = snd_bcm2835_alsa_suspend, ++ .resume = snd_bcm2835_alsa_resume, + #endif +- .driver = { +- .name = "bcm2835_AUD6", +- .owner = THIS_MODULE, +- }, ++ .driver = { ++ .name = "bcm2835_AUD6", ++ .owner = THIS_MODULE, ++ }, + }; + +-static struct platform_driver bcm2835_alsa7_driver = +-{ +- .probe = snd_bcm2835_alsa_probe, +- .remove = snd_bcm2835_alsa_remove, ++static struct platform_driver bcm2835_alsa7_driver = { ++ .probe = snd_bcm2835_alsa_probe, ++ .remove = snd_bcm2835_alsa_remove, + #ifdef CONFIG_PM +- .suspend = snd_bcm2835_alsa_suspend, +- .resume = snd_bcm2835_alsa_resume, ++ .suspend = snd_bcm2835_alsa_suspend, ++ .resume = snd_bcm2835_alsa_resume, + #endif +- .driver = { +- .name = "bcm2835_AUD7", +- .owner = THIS_MODULE, +- }, ++ .driver = { ++ .name = "bcm2835_AUD7", ++ .owner = THIS_MODULE, ++ }, + }; + +- + static int __devinit bcm2835_alsa_device_init(void) + { + int err; +@@ -386,7 +379,8 @@ + printk("Error registering bcm2835_alsa7_driver %d .\n", err); + goto unregister_6; + } +- printk(KERN_INFO"### BCM2835 ALSA driver init %s ### \n",err ? "FAILED": "OK"); ++ printk(KERN_INFO "### BCM2835 ALSA driver init %s ### \n", ++ err ? "FAILED" : "OK"); + + return 0; + +@@ -408,19 +402,22 @@ + return err; + } + +- +- + static void __devexit bcm2835_alsa_device_exit(void) + { +- platform_driver_unregister(&bcm2835_alsa0_driver); +- platform_driver_unregister(&bcm2835_alsa1_driver); +- platform_driver_unregister(&bcm2835_alsa2_driver); +- platform_driver_unregister(&bcm2835_alsa3_driver); +- platform_driver_unregister(&bcm2835_alsa4_driver); +- platform_driver_unregister(&bcm2835_alsa5_driver); +- platform_driver_unregister(&bcm2835_alsa6_driver); +- platform_driver_unregister(&bcm2835_alsa7_driver); ++ platform_driver_unregister(&bcm2835_alsa0_driver); ++ platform_driver_unregister(&bcm2835_alsa1_driver); ++ platform_driver_unregister(&bcm2835_alsa2_driver); ++ platform_driver_unregister(&bcm2835_alsa3_driver); ++ platform_driver_unregister(&bcm2835_alsa4_driver); ++ platform_driver_unregister(&bcm2835_alsa5_driver); ++ platform_driver_unregister(&bcm2835_alsa6_driver); ++ platform_driver_unregister(&bcm2835_alsa7_driver); + } + + late_initcall(bcm2835_alsa_device_init); + module_exit(bcm2835_alsa_device_exit); ++ ++MODULE_AUTHOR("Dom Cobley"); ++MODULE_DESCRIPTION("Alsa driver for BCM2835 chip"); ++MODULE_LICENSE("GPL"); ++MODULE_ALIAS("platform:bcm2835_alsa"); +Index: linux-3.2.46/sound/arm/bcm2835.h +=================================================================== +--- linux-3.2.46.orig/sound/arm/bcm2835.h 2013-07-26 19:32:31.000000000 +0000 ++++ linux-3.2.46/sound/arm/bcm2835.h 2013-07-26 19:32:35.000000000 +0000 +@@ -13,7 +13,7 @@ + *****************************************************************************/ + + #ifndef __SOUND_ARM_BCM2835_H +-#define __SOUND_ARM_BCM2835_H ++#define __SOUND_ARM_BCM2835_H + + #define SUBSTREAM_NUM 1 + +@@ -74,39 +74,39 @@ + #define AUDIO_IPC_BLOCK_BUFFER_SIZE (1024*8) + + #define AUDIO_CONTROL_OFFSET (0x00) +- #define CTRL_EN_SHIFT (0) +- #define CTRL_EN_MASK (0x00000001) +- #define CTRL_PLAY_SHIFT (1) +- #define CTRL_PLAY_MASK (0x00000002) +- #define CTRL_MUTE_SHIFT (2) +- #define CTRL_MUTE_MASK (0x00000004) +- #define CTRL_SETUP_SHIFT (3) +- #define CTRL_SETUP_MASK (0x00000008) +- #define CTRL_FLUSH_SHIFT (4) +- #define CTRL_FLUSH_MASK (0x00000010) +- #define CTRL_STOPMODE_SHIFT (5) +- #define CTRL_STOPMODE_MASK (0x00000020) ++#define CTRL_EN_SHIFT (0) ++#define CTRL_EN_MASK (0x00000001) ++#define CTRL_PLAY_SHIFT (1) ++#define CTRL_PLAY_MASK (0x00000002) ++#define CTRL_MUTE_SHIFT (2) ++#define CTRL_MUTE_MASK (0x00000004) ++#define CTRL_SETUP_SHIFT (3) ++#define CTRL_SETUP_MASK (0x00000008) ++#define CTRL_FLUSH_SHIFT (4) ++#define CTRL_FLUSH_MASK (0x00000010) ++#define CTRL_STOPMODE_SHIFT (5) ++#define CTRL_STOPMODE_MASK (0x00000020) + + #define AUDIO_STATUS_OFFSET (0x04) +- #define STAT_EN_SHIFT (0) +- #define STAT_EN_MASK (0x00000001) +- #define STAT_PLAY_SHIFT (1) +- #define STAT_PLAY_MASK (0x00000002) +- #define STAT_MUTE_SHIFT (2) +- #define STAT_MUTE_MASK (0x00000004) +- #define STAT_SETUP_SHIFT (3) +- #define STAT_SETUP_MASK (0x00000008) +- #define STAT_FLUSH_SHIFT (4) +- #define STAT_FLUSH_MASK (0x00000010) +- #define STAT_STOPMODE_SHIFT (5) +- #define STAT_STOPMODE_MASK (0x00000020) ++#define STAT_EN_SHIFT (0) ++#define STAT_EN_MASK (0x00000001) ++#define STAT_PLAY_SHIFT (1) ++#define STAT_PLAY_MASK (0x00000002) ++#define STAT_MUTE_SHIFT (2) ++#define STAT_MUTE_MASK (0x00000004) ++#define STAT_SETUP_SHIFT (3) ++#define STAT_SETUP_MASK (0x00000008) ++#define STAT_FLUSH_SHIFT (4) ++#define STAT_FLUSH_MASK (0x00000010) ++#define STAT_STOPMODE_SHIFT (5) ++#define STAT_STOPMODE_MASK (0x00000020) + + /* Interrupt status */ + #define AUDIO_INTSTAT_OFFSET (0x08) +- #define INTSTAT_CONTROL_SHIFT (0) +- #define INTSTAT_CONTROL_MASK (0x0000000f) +- #define INTSTAT_FIFO_SHIFT (4) +- #define INTSTAT_FIFO_MASK (0x000000f0) ++#define INTSTAT_CONTROL_SHIFT (0) ++#define INTSTAT_CONTROL_MASK (0x0000000f) ++#define INTSTAT_FIFO_SHIFT (4) ++#define INTSTAT_FIFO_MASK (0x000000f0) + + /* Configuration */ + #define AUDIO_DESTINATION_OFFSET (0x0C) +@@ -139,12 +139,12 @@ + /* 8 entries here of 4 words each = 0x80 gap from 0xF0 */ + #define AUDIO_OUT_FIFO_OFFSET (0xF0) + +- + /* Some constants for values .. */ + typedef enum { +- AUDIO_DEST_LOCAL = 0, +- AUDIO_DEST_HDMI = 2, +- AUDIO_DEST_ALL = 3, ++ AUDIO_DEST_AUTO = 0, ++ AUDIO_DEST_HEADPHONES = 1, ++ AUDIO_DEST_HDMI = 2, ++ AUDIO_DEST_MAX, + } SND_BCM2835_ROUTE_T; + + typedef enum { +@@ -154,8 +154,7 @@ + } SND_BCM2835_CTRL_T; + + /* this struct is tightly packed - its size is 16bytes */ +-typedef struct +-{ ++typedef struct { + uint32_t buffer_id; + uint32_t buffer_size; + uint32_t buffer_ptr; +@@ -179,13 +178,13 @@ + + typedef struct bcm2835_audio_buffer { + uint32_t buffer_id; +- phys_addr_t bus_addr; +- uint8_t __iomem *start; ++ phys_addr_t bus_addr; ++ uint8_t __iomem *start; + uint32_t size; + uint32_t data_left; + struct list_head link; + +-} bcm2835_audio_buffer_t; ++} bcm2835_audio_buffer_t; + + typedef struct bcm2835_alsa_stream { + bcm2835_chip_t *chip; +@@ -215,25 +214,29 @@ + atomic_t retrieved; + struct opaque_AUDIO_INSTANCE_T *instance; + struct workqueue_struct *my_wq; ++ int idx; + } bcm2835_alsa_stream_t; + +-int snd_bcm2835_new_ctl(bcm2835_chip_t *chip); +-int snd_bcm2835_new_pcm(bcm2835_chip_t *chip); ++int snd_bcm2835_new_ctl(bcm2835_chip_t * chip); ++int snd_bcm2835_new_pcm(bcm2835_chip_t * chip); + +-void bcm2835_audio_fifo_get_lock(bcm2835_alsa_stream_t *alsa_stream); +-void bcm2835_audio_fifo_put_lock(bcm2835_alsa_stream_t *alsa_stream); ++void bcm2835_audio_fifo_get_lock(bcm2835_alsa_stream_t * alsa_stream); ++void bcm2835_audio_fifo_put_lock(bcm2835_alsa_stream_t * alsa_stream); + +-int bcm2835_audio_open(bcm2835_alsa_stream_t *alsa_stream); +-int bcm2835_audio_close(bcm2835_alsa_stream_t *alsa_stream); +-int bcm2835_audio_set_params(bcm2835_alsa_stream_t *alsa_stream, uint32_t channels, uint32_t samplerate, uint32_t bps); +-int bcm2835_audio_setup(bcm2835_alsa_stream_t *alsa_stream); +-int bcm2835_audio_start(bcm2835_alsa_stream_t *alsa_stream); +-int bcm2835_audio_stop(bcm2835_alsa_stream_t *alsa_stream); +-int bcm2835_audio_set_ctls(bcm2835_chip_t *chip); +-int bcm2835_audio_write(bcm2835_alsa_stream_t *alsa_stream, uint32_t count, void *src); ++int bcm2835_audio_open(bcm2835_alsa_stream_t * alsa_stream); ++int bcm2835_audio_close(bcm2835_alsa_stream_t * alsa_stream); ++int bcm2835_audio_set_params(bcm2835_alsa_stream_t * alsa_stream, ++ uint32_t channels, uint32_t samplerate, ++ uint32_t bps); ++int bcm2835_audio_setup(bcm2835_alsa_stream_t * alsa_stream); ++int bcm2835_audio_start(bcm2835_alsa_stream_t * alsa_stream); ++int bcm2835_audio_stop(bcm2835_alsa_stream_t * alsa_stream); ++int bcm2835_audio_set_ctls(bcm2835_chip_t * chip); ++int bcm2835_audio_write(bcm2835_alsa_stream_t * alsa_stream, uint32_t count, ++ void *src); + //uint32_t bcm2835_audio_buffers_consumed_bytes(bcm2835_alsa_stream_t *alsa_stream); +-uint32_t bcm2835_audio_retrieve_buffers(bcm2835_alsa_stream_t *alsa_stream); +-void bcm2835_audio_flush_buffers(bcm2835_alsa_stream_t *alsa_stream); +-void bcm2835_audio_flush_playback_buffers(bcm2835_alsa_stream_t *alsa_stream); ++uint32_t bcm2835_audio_retrieve_buffers(bcm2835_alsa_stream_t * alsa_stream); ++void bcm2835_audio_flush_buffers(bcm2835_alsa_stream_t * alsa_stream); ++void bcm2835_audio_flush_playback_buffers(bcm2835_alsa_stream_t * alsa_stream); + + #endif /* __SOUND_ARM_BCM2835_H */ +Index: linux-3.2.46/sound/arm/vc_vchi_audioserv_defs.h +=================================================================== +--- linux-3.2.46.orig/sound/arm/vc_vchi_audioserv_defs.h 2013-07-26 19:32:31.000000000 +0000 ++++ linux-3.2.46/sound/arm/vc_vchi_audioserv_defs.h 2013-07-26 19:32:35.000000000 +0000 +@@ -23,106 +23,90 @@ + + // List of screens that are currently supported + // All message types supported for HOST->VC direction +-typedef enum +-{ +- VC_AUDIO_MSG_TYPE_RESULT, // Generic result +- VC_AUDIO_MSG_TYPE_COMPLETE, // Generic result +- VC_AUDIO_MSG_TYPE_CONFIG, // Configure audio +- VC_AUDIO_MSG_TYPE_CONTROL, // Configure audio +- VC_AUDIO_MSG_TYPE_OPEN, // Configure audio +- VC_AUDIO_MSG_TYPE_CLOSE, // Configure audio +- VC_AUDIO_MSG_TYPE_START, // Configure audio +- VC_AUDIO_MSG_TYPE_STOP, // Configure audio +- VC_AUDIO_MSG_TYPE_WRITE, // Configure audio +- VC_AUDIO_MSG_TYPE_MAX +- ++typedef enum { ++ VC_AUDIO_MSG_TYPE_RESULT, // Generic result ++ VC_AUDIO_MSG_TYPE_COMPLETE, // Generic result ++ VC_AUDIO_MSG_TYPE_CONFIG, // Configure audio ++ VC_AUDIO_MSG_TYPE_CONTROL, // Configure audio ++ VC_AUDIO_MSG_TYPE_OPEN, // Configure audio ++ VC_AUDIO_MSG_TYPE_CLOSE, // Configure audio ++ VC_AUDIO_MSG_TYPE_START, // Configure audio ++ VC_AUDIO_MSG_TYPE_STOP, // Configure audio ++ VC_AUDIO_MSG_TYPE_WRITE, // Configure audio ++ VC_AUDIO_MSG_TYPE_MAX + } VC_AUDIO_MSG_TYPE; + +- + // configure the audio +-typedef struct +-{ +- uint32_t channels; +- uint32_t samplerate; +- uint32_t bps; ++typedef struct { ++ uint32_t channels; ++ uint32_t samplerate; ++ uint32_t bps; + + } VC_AUDIO_CONFIG_T; + +-typedef struct +-{ +- uint32_t volume; +- uint32_t dest; ++typedef struct { ++ uint32_t volume; ++ uint32_t dest; + + } VC_AUDIO_CONTROL_T; + + // audio +-typedef struct +-{ +- uint32_t dummy; ++typedef struct { ++ uint32_t dummy; + + } VC_AUDIO_OPEN_T; + + // audio +-typedef struct +-{ +- uint32_t dummy; ++typedef struct { ++ uint32_t dummy; + + } VC_AUDIO_CLOSE_T; + // audio +-typedef struct +-{ +- uint32_t dummy; ++typedef struct { ++ uint32_t dummy; + + } VC_AUDIO_START_T; + // audio +-typedef struct +-{ +- uint32_t draining; ++typedef struct { ++ uint32_t draining; + + } VC_AUDIO_STOP_T; + + // configure the write audio samples +-typedef struct +-{ +- uint32_t count; // in bytes +- void *callback; +- void *cookie; +- uint32_t silence; ++typedef struct { ++ uint32_t count; // in bytes ++ void *callback; ++ void *cookie; ++ uint32_t silence; + } VC_AUDIO_WRITE_T; + + // Generic result for a request (VC->HOST) +-typedef struct +-{ +- int32_t success; // Success value ++typedef struct { ++ int32_t success; // Success value + + } VC_AUDIO_RESULT_T; + + // Generic result for a request (VC->HOST) +-typedef struct +-{ +- int32_t count; // Success value +- void *callback; +- void *cookie; ++typedef struct { ++ int32_t count; // Success value ++ void *callback; ++ void *cookie; + } VC_AUDIO_COMPLETE_T; + + // Message header for all messages in HOST->VC direction +-typedef struct +-{ +- int32_t type; // Message type (VC_AUDIO_MSG_TYPE) +- union +- { +- VC_AUDIO_CONFIG_T config; +- VC_AUDIO_CONTROL_T control; +- VC_AUDIO_OPEN_T open; +- VC_AUDIO_CLOSE_T close; +- VC_AUDIO_START_T start; +- VC_AUDIO_STOP_T stop; +- VC_AUDIO_WRITE_T write; +- VC_AUDIO_RESULT_T result; +- VC_AUDIO_COMPLETE_T complete; +- } u; ++typedef struct { ++ int32_t type; // Message type (VC_AUDIO_MSG_TYPE) ++ union { ++ VC_AUDIO_CONFIG_T config; ++ VC_AUDIO_CONTROL_T control; ++ VC_AUDIO_OPEN_T open; ++ VC_AUDIO_CLOSE_T close; ++ VC_AUDIO_START_T start; ++ VC_AUDIO_STOP_T stop; ++ VC_AUDIO_WRITE_T write; ++ VC_AUDIO_RESULT_T result; ++ VC_AUDIO_COMPLETE_T complete; ++ } u; + } VC_AUDIO_MSG_T; + +- + #endif // _VC_AUDIO_DEFS_H_ +- diff -Nru linux-3.2.46/debian/patches/rpi/rpi_124_0294940099820f8a9169dd52a3c807436db2fc35.patch linux-3.2.46/debian/patches/rpi/rpi_124_0294940099820f8a9169dd52a3c807436db2fc35.patch --- linux-3.2.46/debian/patches/rpi/rpi_124_0294940099820f8a9169dd52a3c807436db2fc35.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_124_0294940099820f8a9169dd52a3c807436db2fc35.patch 2013-07-26 19:32:38.000000000 +0000 @@ -0,0 +1,18 @@ +commit 0294940099820f8a9169dd52a3c807436db2fc35 +Author: Dom Cobley +Date: Thu Mar 29 21:09:45 2012 +0100 + + Add missing header file update for vc_mem iocts + +Index: linux-3.2.46/arch/arm/mach-bcm2708/include/mach/vc_mem.h +=================================================================== +--- linux-3.2.46.orig/arch/arm/mach-bcm2708/include/mach/vc_mem.h 2013-07-26 19:31:51.000000000 +0000 ++++ linux-3.2.46/arch/arm/mach-bcm2708/include/mach/vc_mem.h 2013-07-26 19:32:37.000000000 +0000 +@@ -21,6 +21,7 @@ + + #define VC_MEM_IOC_MEM_PHYS_ADDR _IOR( VC_MEM_IOC_MAGIC, 0, unsigned long ) + #define VC_MEM_IOC_MEM_SIZE _IOR( VC_MEM_IOC_MAGIC, 1, unsigned int ) ++#define VC_MEM_IOC_MEM_BASE _IOR( VC_MEM_IOC_MAGIC, 2, unsigned int ) + + #if defined( __KERNEL__ ) + #define VC_MEM_TO_ARM_ADDR_MASK 0x3FFFFFFF diff -Nru linux-3.2.46/debian/patches/rpi/rpi_125_8816606c25ea723e67efd182d9efe538db519557.patch linux-3.2.46/debian/patches/rpi/rpi_125_8816606c25ea723e67efd182d9efe538db519557.patch --- linux-3.2.46/debian/patches/rpi/rpi_125_8816606c25ea723e67efd182d9efe538db519557.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_125_8816606c25ea723e67efd182d9efe538db519557.patch 2013-07-26 19:32:39.000000000 +0000 @@ -0,0 +1,275 @@ +commit 8816606c25ea723e67efd182d9efe538db519557 +Author: popcornmix +Date: Tue Apr 3 18:18:10 2012 +0100 + + Remove most of the alsa debug messages + +Index: linux-3.2.46/sound/arm/bcm2835-pcm.c +=================================================================== +--- linux-3.2.46.orig/sound/arm/bcm2835-pcm.c 2013-07-26 19:32:35.000000000 +0000 ++++ linux-3.2.46/sound/arm/bcm2835-pcm.c 2013-07-26 19:32:38.000000000 +0000 +@@ -47,7 +47,7 @@ + uint32_t consumed = 0; + int new_period = 0; + +- audio_debug(" .. IN\n"); ++ audio_info(" .. IN\n"); + + audio_info("alsa_stream=%p substream=%p\n", alsa_stream, + alsa_stream ? alsa_stream->substream : 0); +@@ -64,7 +64,7 @@ + ((alsa_stream->pos + consumed) / alsa_stream->period_size)) + new_period = 1; + } +- audio_warning("updating pos cur: %d + %d max:%d new_period:%d\n", ++ audio_debug("updating pos cur: %d + %d max:%d new_period:%d\n", + alsa_stream->pos, + (consumed /** AUDIO_IPC_BLOCK_BUFFER_SIZE*/ ), + alsa_stream->buffer_size, new_period); +@@ -76,9 +76,9 @@ + if (new_period) + snd_pcm_period_elapsed(alsa_stream->substream); + } else { +- audio_debug(" unexpected NULL substream\n"); ++ audio_warning(" unexpected NULL substream\n"); + } +- audio_debug(" .. OUT\n"); ++ audio_info(" .. OUT\n"); + + return IRQ_HANDLED; + } +@@ -94,7 +94,7 @@ + + audio_info(" .. IN (%d)\n", substream->number); + +- audio_warning(" .. open (%d)\n", substream->number); ++ audio_warning("Alsa open (%d)\n", substream->number); + idx = substream->number; + + if (idx > MAX_SUBSTREAMS) { +@@ -150,7 +150,7 @@ + alsa_stream->draining = 1; + + out: +- audio_debug(" .. OUT =%d\n", err); ++ audio_info(" .. OUT =%d\n", err); + + return err; + } +@@ -163,7 +163,7 @@ + struct snd_pcm_runtime *runtime = substream->runtime; + bcm2835_alsa_stream_t *alsa_stream = runtime->private_data; + +- audio_debug(" .. IN\n"); ++ audio_info(" .. IN\n"); + audio_warning("Alsa close\n"); + + /* +@@ -192,7 +192,7 @@ + * runtime->private_free callback we registered in *_open above + */ + +- audio_debug(" .. OUT\n"); ++ audio_info(" .. OUT\n"); + + return 0; + } +@@ -206,7 +206,7 @@ + bcm2835_alsa_stream_t *alsa_stream = + (bcm2835_alsa_stream_t *) runtime->private_data; + +- audio_debug(" .. IN\n"); ++ audio_info(" .. IN\n"); + + err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(params)); + if (err < 0) { +@@ -224,7 +224,7 @@ + } + + bcm2835_audio_setup(alsa_stream); +- audio_debug(" .. OUT\n"); ++ audio_info(" .. OUT\n"); + + return err; + } +@@ -232,7 +232,7 @@ + /* hw_free callback */ + static int snd_bcm2835_pcm_hw_free(struct snd_pcm_substream *substream) + { +- audio_debug(" .. IN\n"); ++ audio_info(" .. IN\n"); + return snd_pcm_lib_free_pages(substream); + } + +@@ -242,17 +242,17 @@ + struct snd_pcm_runtime *runtime = substream->runtime; + bcm2835_alsa_stream_t *alsa_stream = runtime->private_data; + +- audio_debug(" .. IN\n"); ++ audio_info(" .. IN\n"); + + alsa_stream->buffer_size = snd_pcm_lib_buffer_bytes(substream); + alsa_stream->period_size = snd_pcm_lib_period_bytes(substream); + alsa_stream->pos = 0; + +- audio_warning("buffer_size=%d, period_size=%d pos=%d frame_bits=%d\n", ++ audio_debug("buffer_size=%d, period_size=%d pos=%d frame_bits=%d\n", + alsa_stream->buffer_size, alsa_stream->period_size, + alsa_stream->pos, runtime->frame_bits); + +- audio_debug(" .. OUT\n"); ++ audio_info(" .. OUT\n"); + return 0; + } + +@@ -263,11 +263,11 @@ + bcm2835_alsa_stream_t *alsa_stream = runtime->private_data; + int err = 0; + +- audio_debug(" .. IN\n"); ++ audio_info(" .. IN\n"); + + switch (cmd) { + case SNDRV_PCM_TRIGGER_START: +- audio_warning("bcm2835_AUDIO_TRIGGER_START running=%d\n", ++ audio_debug("bcm2835_AUDIO_TRIGGER_START running=%d\n", + alsa_stream->running); + if (!alsa_stream->running) { + err = bcm2835_audio_start(alsa_stream); +@@ -278,7 +278,7 @@ + } + break; + case SNDRV_PCM_TRIGGER_STOP: +- audio_warning ++ audio_debug + ("bcm2835_AUDIO_TRIGGER_STOP running=%d draining=%d\n", + runtime->status->state == SNDRV_PCM_STATE_DRAINING, + alsa_stream->running); +@@ -300,7 +300,7 @@ + err = -EINVAL; + } + +- audio_debug(" .. OUT\n"); ++ audio_info(" .. OUT\n"); + return err; + } + +@@ -311,14 +311,14 @@ + struct snd_pcm_runtime *runtime = substream->runtime; + bcm2835_alsa_stream_t *alsa_stream = runtime->private_data; + +- audio_debug(" .. IN\n"); ++ audio_info(" .. IN\n"); + +- audio_warning("pcm_pointer... (%d) hwptr=%d appl=%d pos=%d\n", 0, ++ audio_debug("pcm_pointer... (%d) hwptr=%d appl=%d pos=%d\n", 0, + frames_to_bytes(runtime, runtime->status->hw_ptr), + frames_to_bytes(runtime, runtime->control->appl_ptr), + alsa_stream->pos); + +- audio_debug(" .. OUT\n"); ++ audio_info(" .. OUT\n"); + return bytes_to_frames(runtime, alsa_stream->pos); + } + +@@ -330,8 +330,8 @@ + struct snd_pcm_runtime *runtime = substream->runtime; + bcm2835_alsa_stream_t *alsa_stream = runtime->private_data; + +- audio_debug(" .. IN\n"); +- audio_warning("copy.......... (%d) hwptr=%d appl=%d pos=%d\n", ++ audio_info(" .. IN\n"); ++ audio_debug("copy.......... (%d) hwptr=%d appl=%d pos=%d\n", + frames_to_bytes(runtime, count), frames_to_bytes(runtime, + runtime-> + status-> +@@ -341,7 +341,7 @@ + ret = + bcm2835_audio_write(alsa_stream, frames_to_bytes(runtime, count), + src); +- audio_debug(" .. OUT\n"); ++ audio_info(" .. OUT\n"); + return ret; + } + +@@ -353,8 +353,8 @@ + struct snd_pcm_runtime *runtime = substream->runtime; + bcm2835_alsa_stream_t *alsa_stream = runtime->private_data; + +- audio_debug(" .. IN\n"); +- audio_warning("silence....... (%d) hwptr=%d appl=%d pos=%d\n", ++ audio_info(" .. IN\n"); ++ audio_debug("silence....... (%d) hwptr=%d appl=%d pos=%d\n", + frames_to_bytes(runtime, count), frames_to_bytes(runtime, + runtime-> + status-> +@@ -364,7 +364,7 @@ + ret = + bcm2835_audio_write(alsa_stream, frames_to_bytes(runtime, count), + NULL); +- audio_debug(" .. OUT\n"); ++ audio_info(" .. OUT\n"); + return ret; + } + +@@ -372,7 +372,7 @@ + unsigned int cmd, void *arg) + { + int ret = snd_pcm_lib_ioctl(substream, cmd, arg); +- audio_debug(" .. substream=%p, cmd=%d, arg=%p (%x) ret=%d\n", substream, ++ audio_info(" .. substream=%p, cmd=%d, arg=%p (%x) ret=%d\n", substream, + cmd, arg, arg ? *(unsigned *)arg : 0, ret); + return ret; + } +@@ -397,7 +397,7 @@ + struct snd_pcm *pcm; + int err; + +- audio_debug(" .. IN\n"); ++ audio_info(" .. IN\n"); + err = + snd_pcm_new(chip->card, "bcm2835 ALSA", 0, MAX_SUBSTREAMS, 0, &pcm); + if (err < 0) +@@ -418,7 +418,7 @@ + (GFP_KERNEL), 64 * 1024, + 64 * 1024); + +- audio_debug(" .. OUT\n"); ++ audio_info(" .. OUT\n"); + + return 0; + } +Index: linux-3.2.46/sound/arm/bcm2835-vchiq.c +=================================================================== +--- linux-3.2.46.orig/sound/arm/bcm2835-vchiq.c 2013-07-26 19:32:35.000000000 +0000 ++++ linux-3.2.46/sound/arm/bcm2835-vchiq.c 2013-07-26 19:32:38.000000000 +0000 +@@ -42,7 +42,7 @@ + #define VCOS_LOG_CATEGORY (&audio_log_category) + + /* Default VCOS logging level */ +-#define LOG_LEVEL VCOS_LOG_TRACE ++#define LOG_LEVEL VCOS_LOG_WARN + + /* Logging macros (for remapping to other logging mechanisms, i.e., printf) */ + #define LOG_ERR( fmt, arg... ) vcos_log_error( "%s:%d " fmt, __func__, __LINE__, ##arg) +@@ -501,7 +501,6 @@ + int i; + int ret = 0; + LOG_DBG(" .. IN\n"); +-printk(KERN_ERR "set_ctls dest=%d volume=%d\n", chip->dest, chip->volume); + /* change ctls for all substreams */ + for (i = 0; i < MAX_SUBSTREAMS; i++) { + if (chip->avail_substreams & (1 << i)) { +Index: linux-3.2.46/sound/arm/bcm2835.h +=================================================================== +--- linux-3.2.46.orig/sound/arm/bcm2835.h 2013-07-26 19:32:35.000000000 +0000 ++++ linux-3.2.46/sound/arm/bcm2835.h 2013-07-26 19:32:38.000000000 +0000 +@@ -28,7 +28,7 @@ + #include + + /* #define DUMP_RAW_DATA */ +-#define AUDIO_DEBUG_ENABLE ++//#define AUDIO_DEBUG_ENABLE + //#define AUDIO_VERBOSE_DEBUG_ENABLE + + /* Debug macros */ diff -Nru linux-3.2.46/debian/patches/rpi/rpi_126_c5d6cb6ab072e555d8747056a1d44156cded3b31.patch linux-3.2.46/debian/patches/rpi/rpi_126_c5d6cb6ab072e555d8747056a1d44156cded3b31.patch --- linux-3.2.46/debian/patches/rpi/rpi_126_c5d6cb6ab072e555d8747056a1d44156cded3b31.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_126_c5d6cb6ab072e555d8747056a1d44156cded3b31.patch 2013-07-26 19:32:41.000000000 +0000 @@ -0,0 +1,19 @@ +commit c5d6cb6ab072e555d8747056a1d44156cded3b31 +Author: popcornmix +Date: Thu Apr 12 12:16:31 2012 +0100 + + add temporary workaround for fbset crashes + +Index: linux-3.2.46/drivers/video/bcm2708_fb.c +=================================================================== +--- linux-3.2.46.orig/drivers/video/bcm2708_fb.c 2013-07-26 19:32:32.000000000 +0000 ++++ linux-3.2.46/drivers/video/bcm2708_fb.c 2013-07-26 19:32:40.000000000 +0000 +@@ -215,6 +215,8 @@ + /* inform vc about new framebuffer */ + bcm_mailbox_write(MBOX_CHAN_FB, fb->dma); + ++ /* workaround occasional failure to read results. TODO: replace fb driver with vchiq version */ ++ msleep(10); + /* wait for response */ + bcm_mailbox_read(MBOX_CHAN_FB, &val); + diff -Nru linux-3.2.46/debian/patches/rpi/rpi_127_369b60fd9ad144b91503c915d4952ee73cc01b91.patch linux-3.2.46/debian/patches/rpi/rpi_127_369b60fd9ad144b91503c915d4952ee73cc01b91.patch --- linux-3.2.46/debian/patches/rpi/rpi_127_369b60fd9ad144b91503c915d4952ee73cc01b91.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_127_369b60fd9ad144b91503c915d4952ee73cc01b91.patch 2013-07-26 19:32:42.000000000 +0000 @@ -0,0 +1,29 @@ +commit 369b60fd9ad144b91503c915d4952ee73cc01b91 +Author: popcornmix +Date: Mon Apr 16 12:55:39 2012 +0100 + + Fix harmless base/size typo + +Index: linux-3.2.46/arch/arm/mach-bcm2708/vc_mem.c +=================================================================== +--- linux-3.2.46.orig/arch/arm/mach-bcm2708/vc_mem.c 2013-07-26 19:32:34.000000000 +0000 ++++ linux-3.2.46/arch/arm/mach-bcm2708/vc_mem.c 2013-07-26 19:32:41.000000000 +0000 +@@ -208,14 +208,14 @@ + } + case VC_MEM_IOC_MEM_BASE: + { +- // Get the videocore memory size first ++ // Get the videocore memory base + vc_mem_get_base(); + + LOG_DBG("%s: VC_MEM_IOC_MEM_BASE=%u", __func__, +- mm_vc_mem_size); ++ mm_vc_mem_base); + +- if (copy_to_user((void *) arg, &mm_vc_mem_size, +- sizeof (mm_vc_mem_size)) != 0) { ++ if (copy_to_user((void *) arg, &mm_vc_mem_base, ++ sizeof (mm_vc_mem_base)) != 0) { + rc = -EFAULT; + } + break; diff -Nru linux-3.2.46/debian/patches/rpi/rpi_128_2456b9f1f160f9e67ba140beab23494cb03afcf5.patch linux-3.2.46/debian/patches/rpi/rpi_128_2456b9f1f160f9e67ba140beab23494cb03afcf5.patch --- linux-3.2.46/debian/patches/rpi/rpi_128_2456b9f1f160f9e67ba140beab23494cb03afcf5.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_128_2456b9f1f160f9e67ba140beab23494cb03afcf5.patch 2013-07-26 19:32:43.000000000 +0000 @@ -0,0 +1,61 @@ +commit 2456b9f1f160f9e67ba140beab23494cb03afcf5 +Author: Gray Girling +Date: Mon Apr 16 14:00:20 2012 +0100 + + Replace #if 1 sections by local configuration #defines (tidy) + +Index: linux-3.2.46/drivers/mmc/host/sdhci-bcm2708.c +=================================================================== +--- linux-3.2.46.orig/drivers/mmc/host/sdhci-bcm2708.c 2013-07-26 19:32:27.000000000 +0000 ++++ linux-3.2.46/drivers/mmc/host/sdhci-bcm2708.c 2013-07-26 19:32:42.000000000 +0000 +@@ -59,6 +59,9 @@ + //#define LOG_REGISTERS + + #define USE_SCHED_TIME ++#define USE_SPACED_WRITES_2CLK 1 /* space consecutive register writes */ ++#define USE_SOFTWARE_TIMEOUTS 1 /* not hardware timeouts */ ++#define SOFTWARE_ERASE_TIMEOUT_SEC 30 + + #define SDHCI_BCM_DMA_CHAN 4 /* this default is normally overriden */ + #define SDHCI_BCM_DMA_WAITS 0 /* delays slowing DMA transfers: 0-31 */ +@@ -228,9 +231,11 @@ + static void sdhci_bcm2708_raw_writel(struct sdhci_host *host, u32 val, int reg) + { + u32 ier; ++ ++#if USE_SPACED_WRITES_2CLK + static bool timeout_disabled = false; + unsigned int ns_2clk = 0; +- ++ + /* The Arasan has a bugette whereby it may lose the content of + * successive writes to registers that are within two SD-card clock + * cycles of each other (a clock domain crossing problem). +@@ -238,7 +243,6 @@ + * (Which is just as well - otherwise we'd have to nobble the DMA engine + * too) + */ +-#if 1 + if (reg != SDHCI_BUFFER && host->clock != 0) { + /* host->clock is the clock freq in Hz */ + static hptime_t last_write_hpt; +@@ -259,11 +263,14 @@ + } + last_write_hpt = now; + } +-#if 1 +- /* The Arasan is clocked for timeouts using the SD clock which is too fast +- * for ERASE commands and causes issues. So we disable timeouts for ERASE */ +- if (host->cmd != NULL && host->cmd->opcode == MMC_ERASE && reg == (SDHCI_COMMAND & ~3)) { +- mod_timer(&host->timer, jiffies + 30 * HZ); ++#if USE_SOFTWARE_TIMEOUTS ++ /* The Arasan is clocked for timeouts using the SD clock which is too ++ * fast for ERASE commands and causes issues. So we disable timeouts ++ * for ERASE */ ++ if (host->cmd != NULL && host->cmd->opcode == MMC_ERASE && ++ reg == (SDHCI_COMMAND & ~3)) { ++ mod_timer(&host->timer, ++ jiffies + SOFTWARE_ERASE_TIMEOUT_SEC * HZ); + ier = readl(host->ioaddr + SDHCI_SIGNAL_ENABLE); + ier &= ~SDHCI_INT_DATA_TIMEOUT; + writel(ier, host->ioaddr + SDHCI_SIGNAL_ENABLE); diff -Nru linux-3.2.46/debian/patches/rpi/rpi_129_7cb77d373f70f28b5b1ee9eb9746ee99a6c52715.patch linux-3.2.46/debian/patches/rpi/rpi_129_7cb77d373f70f28b5b1ee9eb9746ee99a6c52715.patch --- linux-3.2.46/debian/patches/rpi/rpi_129_7cb77d373f70f28b5b1ee9eb9746ee99a6c52715.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_129_7cb77d373f70f28b5b1ee9eb9746ee99a6c52715.patch 2013-07-26 19:32:45.000000000 +0000 @@ -0,0 +1,49 @@ +commit 7cb77d373f70f28b5b1ee9eb9746ee99a6c52715 +Author: popcornmix +Date: Tue Apr 17 00:33:10 2012 +0100 + + Don't send data block when emitting silence + +Index: linux-3.2.46/sound/arm/bcm2835-vchiq.c +=================================================================== +--- linux-3.2.46.orig/sound/arm/bcm2835-vchiq.c 2013-07-26 19:32:38.000000000 +0000 ++++ linux-3.2.46/sound/arm/bcm2835-vchiq.c 2013-07-26 19:32:44.000000000 +0000 +@@ -761,20 +761,25 @@ + ret = -1; + goto unlock; + } +- LOG_DBG(" ... send header\n"); ++ LOG_DBG(" ... sent header\n"); ++ if (!m.u.write.silence) { ++ /* Send the message to the videocore */ ++ success = vchi_bulk_queue_transmit(instance->vchi_handle[0], ++ src, count, ++ 0 * ++ VCHI_FLAGS_BLOCK_UNTIL_QUEUED ++ + ++ 1 * ++ VCHI_FLAGS_BLOCK_UNTIL_DATA_READ, ++ NULL); ++ if (success != 0) { ++ LOG_ERR ++ ("%s: failed on vchi_bulk_queue_transmit (status=%d)", ++ __func__, success); + +- /* Send the message to the videocore */ +- success = vchi_bulk_queue_transmit(instance->vchi_handle[0], +- src, count, +- 0 * VCHI_FLAGS_BLOCK_UNTIL_QUEUED + +- 1 * VCHI_FLAGS_BLOCK_UNTIL_DATA_READ, +- NULL); +- if (success != 0) { +- LOG_ERR("%s: failed on vchi_msg_queue (status=%d)", +- __func__, success); +- +- ret = -1; +- goto unlock; ++ ret = -1; ++ goto unlock; ++ } + } + ret = 0; + diff -Nru linux-3.2.46/debian/patches/rpi/rpi_130_4fc04b92fcafa7c8719e8f3c4f9fe5771dc78287.patch linux-3.2.46/debian/patches/rpi/rpi_130_4fc04b92fcafa7c8719e8f3c4f9fe5771dc78287.patch --- linux-3.2.46/debian/patches/rpi/rpi_130_4fc04b92fcafa7c8719e8f3c4f9fe5771dc78287.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_130_4fc04b92fcafa7c8719e8f3c4f9fe5771dc78287.patch 2013-07-26 19:32:46.000000000 +0000 @@ -0,0 +1,35 @@ +commit 4fc04b92fcafa7c8719e8f3c4f9fe5771dc78287 +Author: popcornmix +Date: Fri Apr 27 00:30:15 2012 +0100 + + Fix (hopefully) for DWC_MEMCPY kernel panics. Thanks to Naren Sankar for finding this + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_hcd.c +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/dwc_otg_hcd.c 2013-07-26 19:31:23.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_hcd.c 2013-07-26 19:32:45.000000000 +0000 +@@ -909,6 +909,10 @@ + return 0; + #endif + ++ if (((urb->actual_length < 0) || (urb->actual_length > urb->length)) && !dwc_otg_hcd_is_pipe_in(&urb->pipe_info)) ++ urb->actual_length = urb->length; ++ ++ + hc = DWC_CIRCLEQ_FIRST(&hcd->free_hc_list); + + /* Remove the host channel from the free list. */ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c 2013-07-26 19:31:23.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c 2013-07-26 19:32:45.000000000 +0000 +@@ -668,6 +668,9 @@ + urb->number_of_packets, + mem_flags == GFP_ATOMIC ? 1 : 0); + ++ if(dwc_otg_urb == NULL) ++ return -ENOMEM; ++ + urb->hcpriv = dwc_otg_urb; + + dwc_otg_hcd_urb_set_pipeinfo(dwc_otg_urb, usb_pipedevice(urb->pipe), diff -Nru linux-3.2.46/debian/patches/rpi/rpi_131_7487b3f7f684e829ad3e9eb1b835ac937ad63690.patch linux-3.2.46/debian/patches/rpi/rpi_131_7487b3f7f684e829ad3e9eb1b835ac937ad63690.patch --- linux-3.2.46/debian/patches/rpi/rpi_131_7487b3f7f684e829ad3e9eb1b835ac937ad63690.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_131_7487b3f7f684e829ad3e9eb1b835ac937ad63690.patch 2013-07-26 19:32:47.000000000 +0000 @@ -0,0 +1,50 @@ +commit 7487b3f7f684e829ad3e9eb1b835ac937ad63690 +Author: popcornmix +Date: Fri Apr 27 00:31:37 2012 +0100 + + Build modules needed for USB booting into kernel + +Index: linux-3.2.46/arch/arm/configs/bcmrpi_cutdown_defconfig +=================================================================== +--- linux-3.2.46.orig/arch/arm/configs/bcmrpi_cutdown_defconfig 2013-07-26 19:32:35.000000000 +0000 ++++ linux-3.2.46/arch/arm/configs/bcmrpi_cutdown_defconfig 2013-07-26 19:32:46.000000000 +0000 +@@ -90,7 +90,7 @@ + CONFIG_MISC_DEVICES=y + CONFIG_SCSI=y + # CONFIG_SCSI_PROC_FS is not set +-CONFIG_BLK_DEV_SD=m ++CONFIG_BLK_DEV_SD=y + CONFIG_BLK_DEV_SR=m + CONFIG_SCSI_MULTI_LUN=y + # CONFIG_SCSI_LOWLEVEL is not set +@@ -292,7 +292,7 @@ + CONFIG_USB_STORAGE_KARMA=m + CONFIG_USB_STORAGE_CYPRESS_ATACB=m + CONFIG_USB_STORAGE_ENE_UB6250=m +-CONFIG_USB_UAS=m ++CONFIG_USB_UAS=y + CONFIG_USB_LIBUSUAL=y + CONFIG_USB_MDC800=m + CONFIG_USB_MICROTEK=m +Index: linux-3.2.46/arch/arm/configs/bcmrpi_defconfig +=================================================================== +--- linux-3.2.46.orig/arch/arm/configs/bcmrpi_defconfig 2013-07-26 19:32:35.000000000 +0000 ++++ linux-3.2.46/arch/arm/configs/bcmrpi_defconfig 2013-07-26 19:32:46.000000000 +0000 +@@ -106,7 +106,7 @@ + CONFIG_MISC_DEVICES=y + CONFIG_SCSI=y + # CONFIG_SCSI_PROC_FS is not set +-CONFIG_BLK_DEV_SD=m ++CONFIG_BLK_DEV_SD=y + CONFIG_BLK_DEV_SR=m + CONFIG_SCSI_MULTI_LUN=y + # CONFIG_SCSI_LOWLEVEL is not set +@@ -309,7 +309,7 @@ + CONFIG_USB_STORAGE_KARMA=m + CONFIG_USB_STORAGE_CYPRESS_ATACB=m + CONFIG_USB_STORAGE_ENE_UB6250=m +-CONFIG_USB_UAS=m ++CONFIG_USB_UAS=y + CONFIG_USB_LIBUSUAL=y + CONFIG_USB_MDC800=m + CONFIG_USB_MICROTEK=m diff -Nru linux-3.2.46/debian/patches/rpi/rpi_132_0cc4514a13187219f561aaba71a88edb65a7fbf4.patch linux-3.2.46/debian/patches/rpi/rpi_132_0cc4514a13187219f561aaba71a88edb65a7fbf4.patch --- linux-3.2.46/debian/patches/rpi/rpi_132_0cc4514a13187219f561aaba71a88edb65a7fbf4.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_132_0cc4514a13187219f561aaba71a88edb65a7fbf4.patch 2013-07-26 19:32:49.000000000 +0000 @@ -0,0 +1,230 @@ +commit 0cc4514a13187219f561aaba71a88edb65a7fbf4 +Author: popcornmix +Date: Fri Apr 27 00:33:27 2012 +0100 + + Whitespace tidy. Thanks Roger + +Index: linux-3.2.46/arch/arm/mach-bcm2708/bcm2708.c +=================================================================== +--- linux-3.2.46.orig/arch/arm/mach-bcm2708/bcm2708.c 2013-07-26 19:32:30.000000000 +0000 ++++ linux-3.2.46/arch/arm/mach-bcm2708/bcm2708.c 2013-07-26 19:32:48.000000000 +0000 +@@ -85,69 +85,54 @@ + .virtual = IO_ADDRESS(ARMCTRL_BASE), + .pfn = __phys_to_pfn(ARMCTRL_BASE), + .length = SZ_4K, +- .type = MT_DEVICE}, { +- .virtual = IO_ADDRESS(UART0_BASE), +- .pfn = __phys_to_pfn(UART0_BASE), +- .length = SZ_4K, +- .type = MT_DEVICE}, { +- .virtual = +- IO_ADDRESS(UART1_BASE), +- .pfn = +- __phys_to_pfn(UART1_BASE), +- .length = SZ_4K, +- .type = MT_DEVICE}, { ++ .type = MT_DEVICE}, ++ { ++ .virtual = IO_ADDRESS(UART0_BASE), ++ .pfn = __phys_to_pfn(UART0_BASE), ++ .length = SZ_4K, ++ .type = MT_DEVICE}, ++ { ++ .virtual = IO_ADDRESS(UART1_BASE), ++ .pfn = __phys_to_pfn(UART1_BASE), ++ .length = SZ_4K, ++ .type = MT_DEVICE}, + #ifdef CONFIG_MMC_BCM2708 /* broadcom legacy SD */ +- . +- virtual +- = +- IO_ADDRESS +- (MMCI0_BASE), +- .pfn = +- __phys_to_pfn +- (MMCI0_BASE), +- . +- length = +- SZ_4K, +- .type = +- MT_DEVICE}, + { ++ .virtual = IO_ADDRESS(MMCI0_BASE), ++ .pfn = __phys_to_pfn(MMCI0_BASE), ++ .length = SZ_4K, ++ .type = MT_DEVICE}, + #endif ++ { + .virtual = IO_ADDRESS(DMA_BASE), + .pfn = __phys_to_pfn(DMA_BASE), + .length = SZ_4K, +- .type = MT_DEVICE}, { +- .virtual = IO_ADDRESS(MCORE_BASE), +- .pfn = __phys_to_pfn(MCORE_BASE), +- .length = SZ_4K, +- .type = MT_DEVICE}, { +- .virtual = +- IO_ADDRESS(ST_BASE), +- .pfn = +- __phys_to_pfn(ST_BASE), +- .length = SZ_4K, +- .type = MT_DEVICE}, { +- . +- virtual +- = +- IO_ADDRESS +- (USB_BASE), +- .pfn = +- __phys_to_pfn +- (USB_BASE), +- . +- length = +- SZ_128K, +- .type = +- MT_DEVICE}, ++ .type = MT_DEVICE}, ++ { ++ .virtual = IO_ADDRESS(MCORE_BASE), ++ .pfn = __phys_to_pfn(MCORE_BASE), ++ .length = SZ_4K, ++ .type = MT_DEVICE}, ++ { ++ .virtual = IO_ADDRESS(ST_BASE), ++ .pfn = __phys_to_pfn(ST_BASE), ++ .length = SZ_4K, ++ .type = MT_DEVICE}, ++ { ++ .virtual = IO_ADDRESS(USB_BASE), ++ .pfn = __phys_to_pfn(USB_BASE), ++ .length = SZ_128K, ++ .type = MT_DEVICE}, + { + .virtual = IO_ADDRESS(PM_BASE), + .pfn = __phys_to_pfn(PM_BASE), + .length = SZ_4K, +- .type = MT_DEVICE}, { +- .virtual = IO_ADDRESS(GPIO_BASE), +- .pfn = __phys_to_pfn(GPIO_BASE), +- .length = SZ_4K, +- .type = MT_DEVICE} ++ .type = MT_DEVICE}, ++ { ++ .virtual = IO_ADDRESS(GPIO_BASE), ++ .pfn = __phys_to_pfn(GPIO_BASE), ++ .length = SZ_4K, ++ .type = MT_DEVICE} + }; + + void __init bcm2708_map_io(void) +@@ -161,15 +146,15 @@ + static cycle_t stc_read_cycles(struct clocksource *cs) + { + /* STC: a free running counter that increments at the rate of 1MHz */ +- return (cycle_t)readl(__io_address(ST_BASE+0x04)); ++ return (cycle_t) readl(__io_address(ST_BASE + 0x04)); + } + + static struct clocksource clocksource_stc = { +- .name = "stc", +- .rating = 300, +- .read = stc_read_cycles, +- .mask = CLOCKSOURCE_MASK(32), +- .flags = CLOCK_SOURCE_IS_CONTINUOUS, ++ .name = "stc", ++ .rating = 300, ++ .read = stc_read_cycles, ++ .mask = CLOCKSOURCE_MASK(32), ++ .flags = CLOCK_SOURCE_IS_CONTINUOUS, + }; + + unsigned long frc_clock_ticks32(void) +@@ -180,19 +165,16 @@ + static void __init bcm2708_clocksource_init(void) + { + // calculate .shift and .mult values and register clocksource +- if (clocksource_register_hz(&clocksource_stc, STC_FREQ_HZ)) +- { ++ if (clocksource_register_hz(&clocksource_stc, STC_FREQ_HZ)) { + printk(KERN_ERR "timer: failed to initialize clock " +- "source %s\n", clocksource_stc.name); ++ "source %s\n", clocksource_stc.name); + } + } + + unsigned long long sched_clock(void) + { +- return clocksource_cyc2ns(clocksource_stc.read( +- &clocksource_stc), +- clocksource_stc.mult, +- clocksource_stc.shift); ++ return clocksource_cyc2ns(clocksource_stc.read(&clocksource_stc), ++ clocksource_stc.mult, clocksource_stc.shift); + } + + /* +@@ -269,11 +251,12 @@ + .start = MMCI0_BASE, + .end = MMCI0_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, +- }, { +- .start = IRQ_SDIO, +- .end = IRQ_SDIO, +- .flags = IORESOURCE_IRQ, +- } ++ }, ++ { ++ .start = IRQ_SDIO, ++ .end = IRQ_SDIO, ++ .flags = IORESOURCE_IRQ, ++ } + }; + + static struct platform_device bcm2708_mci_device = { +@@ -398,11 +381,12 @@ + .start = ST_BASE, + .end = ST_BASE + SZ_4K - 1, + .flags = IORESOURCE_MEM, +- }, { +- .start = IRQ_TIMER3, +- .end = IRQ_TIMER3, +- .flags = IORESOURCE_IRQ, +- } ++ }, ++ { ++ .start = IRQ_TIMER3, ++ .end = IRQ_TIMER3, ++ .flags = IORESOURCE_IRQ, ++ } + + }; + +@@ -467,14 +451,13 @@ + .coherent_dma_mask = 0xffffffffUL}, + }; + +- + static struct platform_device bcm2708_alsa_devices[] = { +- [0] = { +- .name = "bcm2835_AUD0", +- .id = 0, /* first audio device */ +- .resource = 0, +- .num_resources = 0, +- }, ++ [0] = { ++ .name = "bcm2835_AUD0", ++ .id = 0, /* first audio device */ ++ .resource = 0, ++ .num_resources = 0, ++ }, + }; + + int __init bcm_register_device(struct platform_device *pdev) +@@ -660,7 +643,7 @@ + + MACHINE_START(BCM2708, "BCM2708") + /* Maintainer: Broadcom Europe Ltd. */ +-.map_io = bcm2708_map_io,.init_irq = bcm2708_init_irq,.timer = ++ .map_io = bcm2708_map_io,.init_irq = bcm2708_init_irq,.timer = + &bcm2708_timer,.init_machine = + bcm2708_init, MACHINE_END module_param(boardrev, uint, 0644); + module_param(serial, uint, 0644); diff -Nru linux-3.2.46/debian/patches/rpi/rpi_133_06009f05c407b1b5333c9bec4fb390b440f36a16.patch linux-3.2.46/debian/patches/rpi/rpi_133_06009f05c407b1b5333c9bec4fb390b440f36a16.patch --- linux-3.2.46/debian/patches/rpi/rpi_133_06009f05c407b1b5333c9bec4fb390b440f36a16.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_133_06009f05c407b1b5333c9bec4fb390b440f36a16.patch 2013-07-26 19:32:50.000000000 +0000 @@ -0,0 +1,159 @@ +commit 06009f05c407b1b5333c9bec4fb390b440f36a16 +Author: popcornmix +Date: Fri Apr 27 12:43:54 2012 +0100 + + Update vchiq to match GPU version. Should still be compatible + +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_arm.c +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_arm.c 2013-07-26 19:32:28.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_arm.c 2013-07-26 19:32:49.000000000 +0000 +@@ -137,7 +137,7 @@ + ***************************************************************************/ + + static inline USER_SERVICE_T *find_service_by_handle( +- VCHIQ_INSTANCE_T instance, int handle ) ++ VCHIQ_INSTANCE_T instance, int handle ) + { + USER_SERVICE_T *user_service; + +@@ -1094,7 +1094,7 @@ + char cr = '\n'; + if (copy_to_user(context->buf + context->actual - 1, &cr, 1)) + { +- context->actual = -EFAULT; ++ context->actual = -EFAULT; + } + } + } +@@ -1383,11 +1383,11 @@ + } + if(arm_state->use_notify_pending) + { +- send_pending = 1; +- arm_state->use_notify_pending = 0; ++ send_pending = arm_state->use_notify_pending; ++ arm_state->use_notify_pending=0; + } + vcos_mutex_unlock(&arm_state->use_count_mutex); +- if(send_pending) ++ while(send_pending--) + { + vcos_log_info( "%s sending VCHIQ_MSG_REMOTE_USE_ACTIVE", __func__); + if ( vchiq_send_remote_use_active(state) != VCHIQ_SUCCESS) +@@ -1587,7 +1587,7 @@ + } + if(!block_while_resume) + { +- arm_state->use_notify_pending = 1; ++ arm_state->use_notify_pending++; + vcos_event_signal(&arm_state->hp_evt); /* hp task will check if we need to resume and also send use notify */ + } + +@@ -1811,6 +1811,13 @@ + vcos_unused(state); + } + ++void vchiq_platform_conn_state_changed(VCHIQ_STATE_T *state, VCHIQ_CONNSTATE_T oldstate, VCHIQ_CONNSTATE_T newstate) ++{ ++ vcos_unused(state); ++ vcos_unused(oldstate); ++ vcos_unused(oldstate); ++} ++ + + /**************************************************************************** + * +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_core.c +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_core.c 2013-07-26 19:32:28.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_core.c 2013-07-26 19:32:49.000000000 +0000 +@@ -139,10 +139,12 @@ + static inline void + vchiq_set_conn_state(VCHIQ_STATE_T *state, VCHIQ_CONNSTATE_T newstate) + { ++ VCHIQ_CONNSTATE_T oldstate = state->conn_state; + vcos_log_info("%d: %s->%s", state->id, +- conn_state_names[state->conn_state], ++ conn_state_names[oldstate], + conn_state_names[newstate]); + state->conn_state = newstate; ++ vchiq_platform_conn_state_changed(state, oldstate, newstate); + } + + static inline void +@@ -2686,15 +2688,30 @@ + + VCHIQ_STATUS_T vchiq_send_remote_use(VCHIQ_STATE_T * state) + { +- return queue_message(state, NULL, VCHIQ_MAKE_MSG(VCHIQ_MSG_REMOTE_USE, 0, 0), NULL, 0, 0, 0); ++ VCHIQ_STATUS_T status = VCHIQ_RETRY; ++ if(state->conn_state != VCHIQ_CONNSTATE_DISCONNECTED) ++ { ++ status = queue_message(state, NULL, VCHIQ_MAKE_MSG(VCHIQ_MSG_REMOTE_USE, 0, 0), NULL, 0, 0, 0); ++ } ++ return status; + } + + VCHIQ_STATUS_T vchiq_send_remote_release(VCHIQ_STATE_T * state) + { +- return queue_message(state, NULL, VCHIQ_MAKE_MSG(VCHIQ_MSG_REMOTE_RELEASE, 0, 0), NULL, 0, 0, 0); ++ VCHIQ_STATUS_T status = VCHIQ_RETRY; ++ if(state->conn_state != VCHIQ_CONNSTATE_DISCONNECTED) ++ { ++ status = queue_message(state, NULL, VCHIQ_MAKE_MSG(VCHIQ_MSG_REMOTE_RELEASE, 0, 0), NULL, 0, 0, 0); ++ } ++ return status; + } + + VCHIQ_STATUS_T vchiq_send_remote_use_active(VCHIQ_STATE_T * state) + { +- return queue_message(state, NULL, VCHIQ_MAKE_MSG(VCHIQ_MSG_REMOTE_USE_ACTIVE, 0, 0), NULL, 0, 0, 0); ++ VCHIQ_STATUS_T status = VCHIQ_RETRY; ++ if(state->conn_state != VCHIQ_CONNSTATE_DISCONNECTED) ++ { ++ status = queue_message(state, NULL, VCHIQ_MAKE_MSG(VCHIQ_MSG_REMOTE_USE_ACTIVE, 0, 0), NULL, 0, 0, 0); ++ } ++ return status; + } +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_core.h +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_core.h 2013-07-26 19:32:28.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_core.h 2013-07-26 19:32:49.000000000 +0000 +@@ -500,6 +500,7 @@ + extern VCHIQ_STATUS_T + vchiq_send_remote_use_active(VCHIQ_STATE_T * state); + +- ++extern void ++vchiq_platform_conn_state_changed(VCHIQ_STATE_T* state, VCHIQ_CONNSTATE_T oldstate, VCHIQ_CONNSTATE_T newstate); + + #endif +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_ioctl.h +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_ioctl.h 2013-07-26 19:32:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_ioctl.h 2013-07-26 19:32:49.000000000 +0000 +@@ -91,15 +91,15 @@ + #define VCHIQ_IOC_QUEUE_MESSAGE _IOW(VCHIQ_IOC_MAGIC, 4, VCHIQ_QUEUE_MESSAGE_T) + #define VCHIQ_IOC_QUEUE_BULK_TRANSMIT _IOW(VCHIQ_IOC_MAGIC, 5, VCHIQ_QUEUE_BULK_TRANSFER_T) + #define VCHIQ_IOC_QUEUE_BULK_RECEIVE _IOW(VCHIQ_IOC_MAGIC, 6, VCHIQ_QUEUE_BULK_TRANSFER_T) +-#define VCHIQ_IOC_AWAIT_COMPLETION _IOW(VCHIQ_IOC_MAGIC, 7, VCHIQ_AWAIT_COMPLETION_T) +-#define VCHIQ_IOC_DEQUEUE_MESSAGE _IOW(VCHIQ_IOC_MAGIC, 8, VCHIQ_DEQUEUE_MESSAGE_T) ++#define VCHIQ_IOC_AWAIT_COMPLETION _IOWR(VCHIQ_IOC_MAGIC, 7, VCHIQ_AWAIT_COMPLETION_T) ++#define VCHIQ_IOC_DEQUEUE_MESSAGE _IOWR(VCHIQ_IOC_MAGIC, 8, VCHIQ_DEQUEUE_MESSAGE_T) + #define VCHIQ_IOC_GET_CLIENT_ID _IO(VCHIQ_IOC_MAGIC, 9) +-#define VCHIQ_IOC_GET_CONFIG _IOW(VCHIQ_IOC_MAGIC, 10, VCHIQ_GET_CONFIG_T) +-#define VCHIQ_IOC_CLOSE_SERVICE _IO(VCHIQ_IOC_MAGIC, 11) +-#define VCHIQ_IOC_USE_SERVICE _IO(VCHIQ_IOC_MAGIC, 12) +-#define VCHIQ_IOC_RELEASE_SERVICE _IO(VCHIQ_IOC_MAGIC, 13) +-#define VCHIQ_IOC_SET_SERVICE_OPTION _IOW(VCHIQ_IOC_MAGIC, 14, VCHIQ_SET_SERVICE_OPTION_T) +-#define VCHIQ_IOC_DUMP_PHYS_MEM _IOW(VCHIQ_IOC_MAGIC, 15, VCHIQ_DUMP_MEM_T) ++#define VCHIQ_IOC_GET_CONFIG _IOWR(VCHIQ_IOC_MAGIC, 10, VCHIQ_GET_CONFIG_T) ++#define VCHIQ_IOC_CLOSE_SERVICE _IO(VCHIQ_IOC_MAGIC, 11) ++#define VCHIQ_IOC_USE_SERVICE _IO(VCHIQ_IOC_MAGIC, 12) ++#define VCHIQ_IOC_RELEASE_SERVICE _IO(VCHIQ_IOC_MAGIC, 13) ++#define VCHIQ_IOC_SET_SERVICE_OPTION _IOW(VCHIQ_IOC_MAGIC, 14, VCHIQ_SET_SERVICE_OPTION_T) ++#define VCHIQ_IOC_DUMP_PHYS_MEM _IOW(VCHIQ_IOC_MAGIC, 15, VCHIQ_DUMP_MEM_T) + #define VCHIQ_IOC_MAX 15 + + #endif diff -Nru linux-3.2.46/debian/patches/rpi/rpi_134_2c9450dceac031d05daa8b5dc292a1b1f775c767.patch linux-3.2.46/debian/patches/rpi/rpi_134_2c9450dceac031d05daa8b5dc292a1b1f775c767.patch --- linux-3.2.46/debian/patches/rpi/rpi_134_2c9450dceac031d05daa8b5dc292a1b1f775c767.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_134_2c9450dceac031d05daa8b5dc292a1b1f775c767.patch 2013-07-26 19:32:52.000000000 +0000 @@ -0,0 +1,39 @@ +commit 2c9450dceac031d05daa8b5dc292a1b1f775c767 +Author: Dom Cobley +Date: Mon Apr 30 14:45:52 2012 +0100 + + added support for TT in the USB driver. Thanks Naren + +Index: linux-3.2.46/drivers/usb/gadget/Kconfig +=================================================================== +--- linux-3.2.46.orig/drivers/usb/gadget/Kconfig 2013-07-26 19:32:11.000000000 +0000 ++++ linux-3.2.46/drivers/usb/gadget/Kconfig 2013-07-26 19:32:51.000000000 +0000 +@@ -552,14 +552,6 @@ + depends on USB_GADGET + depends on USB_GADGET_DUALSPEED + +-config USB_GADGET_SNPS_DWC_OTG +- boolean "Synopsys Driver for DWC_otg Controller" +- depends on USB && EXPERIMENTAL +- select USB_OTG +- select USB_GADGET_DUALSPEED +- help +- Selects the Synopsys Driver for the DWC_otg Controller. +- + config USB_DWC_OTG_LPM + boolean "Enable LPM support" + depends on USB && EXPERIMENTAL +Index: linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c 2013-07-26 19:32:45.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c 2013-07-26 19:32:51.000000000 +0000 +@@ -417,6 +417,9 @@ + + hcd->regs = otg_dev->base; + ++ /* Integrate TT in root hub */ ++ hcd->has_tt = 1; ++ + /* Initialize the DWC OTG HCD. */ + dwc_otg_hcd = dwc_otg_hcd_alloc_hcd(); + if (!dwc_otg_hcd) { diff -Nru linux-3.2.46/debian/patches/rpi/rpi_135_c86a03f8e6a874735feeead31385686ef66fdf14.patch linux-3.2.46/debian/patches/rpi/rpi_135_c86a03f8e6a874735feeead31385686ef66fdf14.patch --- linux-3.2.46/debian/patches/rpi/rpi_135_c86a03f8e6a874735feeead31385686ef66fdf14.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_135_c86a03f8e6a874735feeead31385686ef66fdf14.patch 2013-07-26 19:32:53.000000000 +0000 @@ -0,0 +1,64 @@ +commit c86a03f8e6a874735feeead31385686ef66fdf14 +Author: popcornmix +Date: Wed May 2 22:13:14 2012 +0100 + + Swap Red and Blue over in 32bpp framebuffer mode + +Index: linux-3.2.46/drivers/video/bcm2708_fb.c +=================================================================== +--- linux-3.2.46.orig/drivers/video/bcm2708_fb.c 2013-07-26 19:32:40.000000000 +0000 ++++ linux-3.2.46/drivers/video/bcm2708_fb.c 2013-07-26 19:32:52.000000000 +0000 +@@ -113,7 +113,12 @@ + * encoded in the pixel data. Calculate their position from + * the bitfield length defined above. + */ +- if (ret == 0 && var->bits_per_pixel >= 16) { ++ if (ret == 0 && var->bits_per_pixel >= 24) { ++ var->red.offset = 0; ++ var->green.offset = var->red.offset + var->red.length; ++ var->blue.offset = var->green.offset + var->green.length; ++ var->transp.offset = var->blue.offset + var->blue.length; ++ } else if (ret == 0 && var->bits_per_pixel >= 16) { + var->blue.offset = 0; + var->green.offset = var->blue.offset + var->blue.length; + var->red.offset = var->green.offset + var->green.length; +@@ -312,6 +317,7 @@ + + static int fbwidth = 800; /* module parameter */ + static int fbheight = 480; /* module parameter */ ++static int fbdepth = 16; /* module parameter */ + + static int bcm2708_fb_register(struct bcm2708_fb *fb) + { +@@ -346,7 +352,7 @@ + fb->fb.var.yres = fbheight; + fb->fb.var.xres_virtual = fbwidth; + fb->fb.var.yres_virtual = fbheight; +- fb->fb.var.bits_per_pixel = 16; ++ fb->fb.var.bits_per_pixel = fbdepth; + fb->fb.var.vmode = FB_VMODE_NONINTERLACED; + fb->fb.var.activate = FB_ACTIVATE_NOW; + fb->fb.var.nonstd = 0; +@@ -369,8 +375,8 @@ + + fb_set_var(&fb->fb, &fb->fb.var); + +- pr_info("BCM2708FB: registering framebuffer (%d, %d)\n", fbwidth, +- fbheight); ++ pr_info("BCM2708FB: registering framebuffer (%dx%d@%d)\n", fbwidth, ++ fbheight, fbdepth); + + ret = register_framebuffer(&fb->fb); + pr_info("BCM2708FB: register framebuffer (%d)\n", ret); +@@ -453,9 +459,11 @@ + + module_param(fbwidth, int, 0644); + module_param(fbheight, int, 0644); ++module_param(fbdepth, int, 0644); + + MODULE_DESCRIPTION("BCM2708 framebuffer driver"); + MODULE_LICENSE("GPL"); + + MODULE_PARM_DESC(fbwidth, "Width of ARM Framebuffer"); + MODULE_PARM_DESC(fbheight, "Height of ARM Framebuffer"); ++MODULE_PARM_DESC(fbdepth, "Bit depth of ARM Framebuffer"); diff -Nru linux-3.2.46/debian/patches/rpi/rpi_136_3352a69ac1bcc36c689c7908b3a5cd4613354984.patch linux-3.2.46/debian/patches/rpi/rpi_136_3352a69ac1bcc36c689c7908b3a5cd4613354984.patch --- linux-3.2.46/debian/patches/rpi/rpi_136_3352a69ac1bcc36c689c7908b3a5cd4613354984.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_136_3352a69ac1bcc36c689c7908b3a5cd4613354984.patch 2013-07-26 19:32:54.000000000 +0000 @@ -0,0 +1,166 @@ +commit 3352a69ac1bcc36c689c7908b3a5cd4613354984 +Author: popcornmix +Date: Sun May 6 16:58:07 2012 +0100 + + Update emergency config to match latest debug one + +Index: linux-3.2.46/arch/arm/configs/bcmrpi_emergency_defconfig +=================================================================== +--- linux-3.2.46.orig/arch/arm/configs/bcmrpi_emergency_defconfig 2013-07-26 19:32:17.000000000 +0000 ++++ linux-3.2.46/arch/arm/configs/bcmrpi_emergency_defconfig 2013-07-26 19:32:53.000000000 +0000 +@@ -2,27 +2,44 @@ + # CONFIG_LOCALVERSION_AUTO is not set + CONFIG_SYSVIPC=y + CONFIG_POSIX_MQUEUE=y ++CONFIG_BSD_PROCESS_ACCT=y ++CONFIG_BSD_PROCESS_ACCT_V3=y ++CONFIG_FHANDLE=y ++CONFIG_AUDIT=y + CONFIG_IKCONFIG=y + CONFIG_IKCONFIG_PROC=y + CONFIG_BLK_DEV_INITRD=y + CONFIG_INITRAMFS_SOURCE="../target_fs" +-# CONFIG_UID16 is not set +-# CONFIG_KALLSYMS is not set ++CONFIG_CGROUP_FREEZER=y ++CONFIG_CGROUP_DEVICE=y ++CONFIG_CGROUP_CPUACCT=y ++CONFIG_RESOURCE_COUNTERS=y ++CONFIG_BLK_CGROUP=y ++CONFIG_NAMESPACES=y ++CONFIG_SCHED_AUTOGROUP=y + CONFIG_EMBEDDED=y +-# CONFIG_VM_EVENT_COUNTERS is not set + # CONFIG_COMPAT_BRK is not set + CONFIG_SLAB=y ++CONFIG_PROFILING=y ++CONFIG_OPROFILE=m ++CONFIG_KPROBES=y + CONFIG_MODULES=y + CONFIG_MODULE_UNLOAD=y + CONFIG_MODVERSIONS=y + CONFIG_MODULE_SRCVERSION_ALL=y + # CONFIG_BLK_DEV_BSG is not set ++CONFIG_BLK_DEV_THROTTLING=y ++CONFIG_CFQ_GROUP_IOSCHED=y + CONFIG_ARCH_BCM2708=y + CONFIG_NO_HZ=y ++CONFIG_HIGH_RES_TIMERS=y + CONFIG_AEABI=y ++CONFIG_SECCOMP=y ++CONFIG_CC_STACKPROTECTOR=y + CONFIG_ZBOOT_ROM_TEXT=0x0 + CONFIG_ZBOOT_ROM_BSS=0x0 + CONFIG_CMDLINE="dwc_otg.lpm_enable=0 console=ttyAMA0,115200 kgdboc=ttyAMA0,115200 root=/dev/mmcblk0p2 rootfstype=ext3 rootwait" ++CONFIG_KEXEC=y + CONFIG_CPU_IDLE=y + CONFIG_VFP=y + CONFIG_BINFMT_MISC=m +@@ -91,10 +108,11 @@ + CONFIG_MISC_DEVICES=y + CONFIG_SCSI=y + # CONFIG_SCSI_PROC_FS is not set +-CONFIG_BLK_DEV_SD=m ++CONFIG_BLK_DEV_SD=y + CONFIG_BLK_DEV_SR=m + CONFIG_SCSI_MULTI_LUN=y + # CONFIG_SCSI_LOWLEVEL is not set ++CONFIG_MD=y + CONFIG_NETDEVICES=y + CONFIG_TUN=m + CONFIG_PHYLIB=m +@@ -209,6 +227,26 @@ + CONFIG_LOGO=y + # CONFIG_LOGO_LINUX_MONO is not set + # CONFIG_LOGO_LINUX_VGA16 is not set ++CONFIG_SOUND=y ++CONFIG_SND=m ++CONFIG_SND_SEQUENCER=m ++CONFIG_SND_SEQ_DUMMY=m ++CONFIG_SND_MIXER_OSS=m ++CONFIG_SND_PCM_OSS=m ++CONFIG_SND_SEQUENCER_OSS=y ++CONFIG_SND_HRTIMER=m ++CONFIG_SND_DUMMY=m ++CONFIG_SND_ALOOP=m ++CONFIG_SND_VIRMIDI=m ++CONFIG_SND_MTPAV=m ++CONFIG_SND_SERIAL_U16550=m ++CONFIG_SND_MPU401=m ++CONFIG_SND_BCM2835=m ++CONFIG_SND_USB_AUDIO=m ++CONFIG_SND_USB_UA101=m ++CONFIG_SND_USB_CAIAQ=m ++CONFIG_SND_USB_6FIRE=m ++CONFIG_SOUND_PRIME=m + CONFIG_HID_PID=y + CONFIG_USB_HIDDEV=y + CONFIG_HID_A4TECH=m +@@ -273,7 +311,7 @@ + CONFIG_USB_STORAGE_KARMA=m + CONFIG_USB_STORAGE_CYPRESS_ATACB=m + CONFIG_USB_STORAGE_ENE_UB6250=m +-CONFIG_USB_UAS=m ++CONFIG_USB_UAS=y + CONFIG_USB_LIBUSUAL=y + CONFIG_USB_MDC800=m + CONFIG_USB_MICROTEK=m +@@ -369,6 +407,7 @@ + CONFIG_JFS_FS=m + CONFIG_JFS_POSIX_ACL=y + CONFIG_JFS_SECURITY=y ++CONFIG_JFS_STATISTICS=y + CONFIG_XFS_FS=m + CONFIG_XFS_QUOTA=y + CONFIG_XFS_POSIX_ACL=y +@@ -378,10 +417,13 @@ + CONFIG_BTRFS_FS=m + CONFIG_BTRFS_FS_POSIX_ACL=y + CONFIG_NILFS2_FS=m ++CONFIG_FANOTIFY=y + CONFIG_AUTOFS4_FS=y + CONFIG_FUSE_FS=m + CONFIG_CUSE=m + CONFIG_FSCACHE=y ++CONFIG_FSCACHE_STATS=y ++CONFIG_FSCACHE_HISTOGRAM=y + CONFIG_CACHEFILES=y + CONFIG_ISO9660_FS=m + CONFIG_JOLIET=y +@@ -409,6 +451,7 @@ + CONFIG_CIFS_XATTR=y + CONFIG_CIFS_POSIX=y + CONFIG_9P_FS=m ++CONFIG_9P_FS_POSIX_ACL=y + CONFIG_PARTITION_ADVANCED=y + CONFIG_MAC_PARTITION=y + CONFIG_EFI_PARTITION=y +@@ -451,10 +494,24 @@ + CONFIG_NLS_KOI8_R=m + CONFIG_NLS_KOI8_U=m + CONFIG_NLS_UTF8=m +-# CONFIG_SCHED_DEBUG is not set +-# CONFIG_DEBUG_BUGVERBOSE is not set +-# CONFIG_FTRACE is not set +-# CONFIG_ARM_UNWIND is not set ++CONFIG_PRINTK_TIME=y ++CONFIG_DETECT_HUNG_TASK=y ++CONFIG_TIMER_STATS=y ++CONFIG_DEBUG_STACK_USAGE=y ++CONFIG_DEBUG_INFO=y ++CONFIG_DEBUG_MEMORY_INIT=y ++CONFIG_BOOT_PRINTK_DELAY=y ++CONFIG_LATENCYTOP=y ++CONFIG_SYSCTL_SYSCALL_CHECK=y ++CONFIG_IRQSOFF_TRACER=y ++CONFIG_SCHED_TRACER=y ++CONFIG_STACK_TRACER=y ++CONFIG_BLK_DEV_IO_TRACE=y ++CONFIG_FUNCTION_PROFILER=y ++CONFIG_KGDB=y ++CONFIG_KGDB_KDB=y ++CONFIG_KDB_KEYBOARD=y ++CONFIG_STRICT_DEVMEM=y + CONFIG_CRYPTO_AUTHENC=m + CONFIG_CRYPTO_SEQIV=m + CONFIG_CRYPTO_CBC=y diff -Nru linux-3.2.46/debian/patches/rpi/rpi_137_f8c99b57a05b626bf706edddf61f86c89232b213.patch linux-3.2.46/debian/patches/rpi/rpi_137_f8c99b57a05b626bf706edddf61f86c89232b213.patch --- linux-3.2.46/debian/patches/rpi/rpi_137_f8c99b57a05b626bf706edddf61f86c89232b213.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_137_f8c99b57a05b626bf706edddf61f86c89232b213.patch 2013-07-26 19:32:55.000000000 +0000 @@ -0,0 +1,31 @@ +commit f8c99b57a05b626bf706edddf61f86c89232b213 +Author: Stephane Fillod +Date: Fri Apr 20 09:39:23 2012 +0000 + + net: usb: smsc95xx: fix mtu + + Make smsc95xx recalculate the hard_mtu after adjusting the + hard_header_len. + + Without this, usbnet adjusts the MTU down to 1488 bytes, and the host is + unable to receive standard 1500-byte frames from the device. + + Inspired by same fix on cdc_eem 78fb72f7936c01d5b426c03a691eca082b03f2b9. + + Tested on ARM/Beagle. + + Signed-off-by: Stephane Fillod + Signed-off-by: David S. Miller + +Index: linux-3.2.46/drivers/net/usb/smsc95xx.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/usb/smsc95xx.c 2013-07-26 19:32:06.000000000 +0000 ++++ linux-3.2.46/drivers/net/usb/smsc95xx.c 2013-07-26 19:32:54.000000000 +0000 +@@ -1072,6 +1072,7 @@ + dev->net->ethtool_ops = &smsc95xx_ethtool_ops; + dev->net->flags |= IFF_MULTICAST; + dev->net->hard_header_len += SMSC95XX_TX_OVERHEAD_CSUM; ++ dev->hard_mtu = dev->net->mtu + dev->net->hard_header_len; + return 0; + } + diff -Nru linux-3.2.46/debian/patches/rpi/rpi_138_0c184a6618f4817030af0bbfdc7d55911e2b14ed.patch linux-3.2.46/debian/patches/rpi/rpi_138_0c184a6618f4817030af0bbfdc7d55911e2b14ed.patch --- linux-3.2.46/debian/patches/rpi/rpi_138_0c184a6618f4817030af0bbfdc7d55911e2b14ed.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_138_0c184a6618f4817030af0bbfdc7d55911e2b14ed.patch 2013-07-26 19:32:57.000000000 +0000 @@ -0,0 +1,28 @@ +commit 0c184a6618f4817030af0bbfdc7d55911e2b14ed +Author: popcornmix +Date: Tue May 8 23:09:44 2012 +0100 + + Use dwc_alloc_atomic. Thanks bootc + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_hcd.h +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/dwc_otg_hcd.h 2013-07-26 19:31:23.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_hcd.h 2013-07-26 19:32:56.000000000 +0000 +@@ -628,7 +628,7 @@ + * @return Returns the memory allocate or NULL on error. */ + static inline dwc_otg_qh_t *dwc_otg_hcd_qh_alloc(void) + { +- return (dwc_otg_qh_t *) dwc_alloc(sizeof(dwc_otg_qh_t)); ++ return (dwc_otg_qh_t *) dwc_alloc_atomic(sizeof(dwc_otg_qh_t)); + } + + extern dwc_otg_qtd_t *dwc_otg_hcd_qtd_create(dwc_otg_hcd_urb_t * urb); +@@ -640,7 +640,7 @@ + * @return Returns the memory allocate or NULL on error. */ + static inline dwc_otg_qtd_t *dwc_otg_hcd_qtd_alloc(void) + { +- return (dwc_otg_qtd_t *) dwc_alloc(sizeof(dwc_otg_qtd_t)); ++ return (dwc_otg_qtd_t *) dwc_alloc_atomic(sizeof(dwc_otg_qtd_t)); + } + + /** Frees the memory for a QTD structure. QTD should already be removed from diff -Nru linux-3.2.46/debian/patches/rpi/rpi_139_e9382f7c0690b2ae17972c64c2cecaca6a1ec87d.patch linux-3.2.46/debian/patches/rpi/rpi_139_e9382f7c0690b2ae17972c64c2cecaca6a1ec87d.patch --- linux-3.2.46/debian/patches/rpi/rpi_139_e9382f7c0690b2ae17972c64c2cecaca6a1ec87d.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_139_e9382f7c0690b2ae17972c64c2cecaca6a1ec87d.patch 2013-07-26 19:32:58.000000000 +0000 @@ -0,0 +1,33 @@ +commit e9382f7c0690b2ae17972c64c2cecaca6a1ec87d +Author: popcornmix +Date: Tue May 8 23:12:13 2012 +0100 + + possible fix for sdcard missing status. Thank naren + +Index: linux-3.2.46/drivers/mmc/host/sdhci-bcm2708.c +=================================================================== +--- linux-3.2.46.orig/drivers/mmc/host/sdhci-bcm2708.c 2013-07-26 19:32:42.000000000 +0000 ++++ linux-3.2.46/drivers/mmc/host/sdhci-bcm2708.c 2013-07-26 19:32:57.000000000 +0000 +@@ -1291,6 +1291,14 @@ + return 1; + } + ++static unsigned int sdhci_bcm2708_missing_status(struct sdhci_host *host) ++{ ++ if(host->last_cmdop == MMC_SEND_STATUS) ++ return 1; ++ else ++ return 0; ++} ++ + /***************************************************************************** \ + * * + * Device ops * +@@ -1328,6 +1336,7 @@ + .spurious_crc_acmd51 = sdhci_bcm2708_quirk_spurious_crc, + .voltage_broken = sdhci_bcm2708_quirk_voltage_broken, + .uhs_broken = sdhci_bcm2708_uhs_broken, ++ .missing_status = sdhci_bcm2708_missing_status, + }; + + /*****************************************************************************\ diff -Nru linux-3.2.46/debian/patches/rpi/rpi_140_dc0b877bf55f4d3a969015101d3bf9e738c4f0a9.patch linux-3.2.46/debian/patches/rpi/rpi_140_dc0b877bf55f4d3a969015101d3bf9e738c4f0a9.patch --- linux-3.2.46/debian/patches/rpi/rpi_140_dc0b877bf55f4d3a969015101d3bf9e738c4f0a9.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_140_dc0b877bf55f4d3a969015101d3bf9e738c4f0a9.patch 2013-07-26 19:32:59.000000000 +0000 @@ -0,0 +1,33 @@ +commit dc0b877bf55f4d3a969015101d3bf9e738c4f0a9 +Author: popcornmix +Date: Tue May 8 23:14:05 2012 +0100 + + Fix BUG() in bcm2708_fb_set_par doesn't work if the console is currently locked. Thanks lp0 + +Index: linux-3.2.46/drivers/video/bcm2708_fb.c +=================================================================== +--- linux-3.2.46.orig/drivers/video/bcm2708_fb.c 2013-07-26 19:32:52.000000000 +0000 ++++ linux-3.2.46/drivers/video/bcm2708_fb.c 2013-07-26 19:32:58.000000000 +0000 +@@ -27,6 +27,7 @@ + #include + #include + #include ++#include + + #include + #include +@@ -243,8 +244,13 @@ + iounmap(fb->fb.screen_base); + fb->fb.screen_base = + (void *)ioremap_wc(fb->fb.fix.smem_start, fb->fb.screen_size); +- if (!fb->fb.screen_base) ++ if (!fb->fb.screen_base) { ++ /* the console may currently be locked */ ++ console_trylock(); ++ console_unlock(); ++ + BUG(); /* what can we do here */ ++ } + } + pr_info + ("BCM2708FB: start = %p,%p width=%d, height=%d, bpp=%d, pitch=%d size=%d success=%d\n", diff -Nru linux-3.2.46/debian/patches/rpi/rpi_141_4b0ecd93e82e32453b25fec1dc59bcedfd2958fd.patch linux-3.2.46/debian/patches/rpi/rpi_141_4b0ecd93e82e32453b25fec1dc59bcedfd2958fd.patch --- linux-3.2.46/debian/patches/rpi/rpi_141_4b0ecd93e82e32453b25fec1dc59bcedfd2958fd.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_141_4b0ecd93e82e32453b25fec1dc59bcedfd2958fd.patch 2013-07-26 19:33:01.000000000 +0000 @@ -0,0 +1,26 @@ +commit 4b0ecd93e82e32453b25fec1dc59bcedfd2958fd +Author: popcornmix +Date: Tue May 15 15:24:40 2012 +0100 + + Fix for DWC OTG HCD URB Dequeue has NULL URB panic. Thanks Naren + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c 2013-07-26 19:32:51.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c 2013-07-26 19:33:00.000000000 +0000 +@@ -761,10 +761,12 @@ + dump_urb_info(urb, "urb_dequeue"); + } + #endif +- dwc_otg_hcd_urb_dequeue(dwc_otg_hcd, (dwc_otg_hcd_urb_t *)urb->hcpriv); ++ if(urb->hcpriv != NULL) { ++ dwc_otg_hcd_urb_dequeue(dwc_otg_hcd, (dwc_otg_hcd_urb_t *)urb->hcpriv); + +- dwc_free(urb->hcpriv); +- urb->hcpriv = NULL; ++ urb->hcpriv = NULL; ++ dwc_free(urb->hcpriv); ++ } + + /* Higher layer software sets URB status. */ + #if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30)) diff -Nru linux-3.2.46/debian/patches/rpi/rpi_142_b4f35d9f2a6284e8075bd1c6020a1bc55a8a7975.patch linux-3.2.46/debian/patches/rpi/rpi_142_b4f35d9f2a6284e8075bd1c6020a1bc55a8a7975.patch --- linux-3.2.46/debian/patches/rpi/rpi_142_b4f35d9f2a6284e8075bd1c6020a1bc55a8a7975.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_142_b4f35d9f2a6284e8075bd1c6020a1bc55a8a7975.patch 2013-07-26 19:33:02.000000000 +0000 @@ -0,0 +1,55 @@ +commit b4f35d9f2a6284e8075bd1c6020a1bc55a8a7975 +Author: popcornmix +Date: Wed May 16 14:15:12 2012 +0100 + + Fix for bug in mbox_read. Thanks lp0 + +Index: linux-3.2.46/arch/arm/mach-bcm2708/power.c +=================================================================== +--- linux-3.2.46.orig/arch/arm/mach-bcm2708/power.c 2013-07-26 19:32:25.000000000 +0000 ++++ linux-3.2.46/arch/arm/mach-bcm2708/power.c 2013-07-26 19:33:01.000000000 +0000 +@@ -97,8 +97,6 @@ + bcm_mailbox_write(MBOX_CHAN_POWER, + global_request << 4); + +- /* Wait for a response during power-up */ +- mdelay(10); + if (global_request & ~g_state.global_request) { + rc = bcm_mailbox_read(MBOX_CHAN_POWER, + &actual); +Index: linux-3.2.46/arch/arm/mach-bcm2708/vcio.c +=================================================================== +--- linux-3.2.46.orig/arch/arm/mach-bcm2708/vcio.c 2013-07-26 19:31:51.000000000 +0000 ++++ linux-3.2.46/arch/arm/mach-bcm2708/vcio.c 2013-07-26 19:33:01.000000000 +0000 +@@ -119,8 +119,7 @@ + if (mbox->magic != MBOX_MAGIC) + rc = -EINVAL; + else { +- if (mbox->msg[chan] || +- (down_interruptible(&mbox->sema[chan]) == 0)) { ++ if (down_interruptible(&mbox->sema[chan]) == 0) { + *data28 = MBOX_DATA28(mbox->msg[chan]); + mbox->msg[chan] = 0; + rc = 0; +Index: linux-3.2.46/drivers/video/bcm2708_fb.c +=================================================================== +--- linux-3.2.46.orig/drivers/video/bcm2708_fb.c 2013-07-26 19:32:58.000000000 +0000 ++++ linux-3.2.46/drivers/video/bcm2708_fb.c 2013-07-26 19:33:01.000000000 +0000 +@@ -18,7 +18,6 @@ + #include + #include + #include +-#include + #include + #include + #include +@@ -221,8 +220,7 @@ + /* inform vc about new framebuffer */ + bcm_mailbox_write(MBOX_CHAN_FB, fb->dma); + +- /* workaround occasional failure to read results. TODO: replace fb driver with vchiq version */ +- msleep(10); ++ /* TODO: replace fb driver with vchiq version */ + /* wait for response */ + bcm_mailbox_read(MBOX_CHAN_FB, &val); + diff -Nru linux-3.2.46/debian/patches/rpi/rpi_143_bd396799fb1289cb7acd59762ac6431bd3fec0ad.patch linux-3.2.46/debian/patches/rpi/rpi_143_bd396799fb1289cb7acd59762ac6431bd3fec0ad.patch --- linux-3.2.46/debian/patches/rpi/rpi_143_bd396799fb1289cb7acd59762ac6431bd3fec0ad.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_143_bd396799fb1289cb7acd59762ac6431bd3fec0ad.patch 2013-07-26 19:33:03.000000000 +0000 @@ -0,0 +1,17 @@ +commit bd396799fb1289cb7acd59762ac6431bd3fec0ad +Author: popcornmix +Date: Wed May 16 20:16:43 2012 +0100 + + Add __VCCOREVER__ to makefile + +Index: linux-3.2.46/sound/arm/Makefile +=================================================================== +--- linux-3.2.46.orig/sound/arm/Makefile 2013-07-26 19:32:31.000000000 +0000 ++++ linux-3.2.46/sound/arm/Makefile 2013-07-26 19:33:02.000000000 +0000 +@@ -18,5 +18,5 @@ + obj-$(CONFIG_SND_BCM2835) += snd-bcm2835.o + snd-bcm2835-objs := bcm2835.o bcm2835-ctl.o bcm2835-pcm.o bcm2835-vchiq.o + +-EXTRA_CFLAGS += -Idrivers/misc/vc04_services -Idrivers/misc/vc04_services/interface/vcos/linuxkernel ++EXTRA_CFLAGS += -Idrivers/misc/vc04_services -Idrivers/misc/vc04_services/interface/vcos/linuxkernel -D__VCCOREVER__=0x04000000 + diff -Nru linux-3.2.46/debian/patches/rpi/rpi_144_45dced6ad22bee4458b53c3ff7d3d79a4368bdcf.patch linux-3.2.46/debian/patches/rpi/rpi_144_45dced6ad22bee4458b53c3ff7d3d79a4368bdcf.patch --- linux-3.2.46/debian/patches/rpi/rpi_144_45dced6ad22bee4458b53c3ff7d3d79a4368bdcf.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_144_45dced6ad22bee4458b53c3ff7d3d79a4368bdcf.patch 2013-07-26 19:33:05.000000000 +0000 @@ -0,0 +1,30 @@ +commit 45dced6ad22bee4458b53c3ff7d3d79a4368bdcf +Author: popcornmix +Date: Thu May 17 14:40:44 2012 +0100 + + Change PHYS_OFFSET to PLAT_PHYS_OFFSET + +Index: linux-3.2.46/arch/arm/mach-bcm2708/include/mach/memory.h +=================================================================== +--- linux-3.2.46.orig/arch/arm/mach-bcm2708/include/mach/memory.h 2013-07-26 19:32:20.000000000 +0000 ++++ linux-3.2.46/arch/arm/mach-bcm2708/include/mach/memory.h 2013-07-26 19:33:04.000000000 +0000 +@@ -32,7 +32,7 @@ + /* + * Physical DRAM offset. + */ +-#define PHYS_OFFSET UL(0x00000000) ++#define PLAT_PHYS_OFFSET UL(0x00000000) + #define ARMMEM_OFFSET UL(0x00000000) /* offset in VC of ARM memory */ + + #ifdef CONFIG_BCM2708_NOL2CACHE +@@ -51,8 +51,8 @@ + #define BUS_OFFSET (ARMMEM_OFFSET + _REAL_BUS_OFFSET) + #define __virt_to_bus(x) ((x) + (BUS_OFFSET - PAGE_OFFSET)) + #define __bus_to_virt(x) ((x) - (BUS_OFFSET - PAGE_OFFSET)) +-#define __pfn_to_bus(x) (__pfn_to_phys(x) + (BUS_OFFSET - PHYS_OFFSET)) +-#define __bus_to_pfn(x) __phys_to_pfn((x) - (BUS_OFFSET - PHYS_OFFSET)) ++#define __pfn_to_bus(x) (__pfn_to_phys(x) + (BUS_OFFSET - PLAT_PHYS_OFFSET)) ++#define __bus_to_pfn(x) __phys_to_pfn((x) - (BUS_OFFSET - PLAT_PHYS_OFFSET)) + + /* + * Consistent DMA area set to 2M. Framebuffer now allocated on host diff -Nru linux-3.2.46/debian/patches/rpi/rpi_145_2d05297654e1c0e119deeb365585df4e904bcfe3.patch linux-3.2.46/debian/patches/rpi/rpi_145_2d05297654e1c0e119deeb365585df4e904bcfe3.patch --- linux-3.2.46/debian/patches/rpi/rpi_145_2d05297654e1c0e119deeb365585df4e904bcfe3.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_145_2d05297654e1c0e119deeb365585df4e904bcfe3.patch 2013-07-26 19:33:06.000000000 +0000 @@ -0,0 +1,55 @@ +commit 2d05297654e1c0e119deeb365585df4e904bcfe3 +Author: popcornmix +Date: Thu May 17 14:44:19 2012 +0100 + + sdcard patch improvements from naren + +Index: linux-3.2.46/drivers/mmc/host/sdhci-bcm2708.c +=================================================================== +--- linux-3.2.46.orig/drivers/mmc/host/sdhci-bcm2708.c 2013-07-26 19:32:57.000000000 +0000 ++++ linux-3.2.46/drivers/mmc/host/sdhci-bcm2708.c 2013-07-26 19:33:05.000000000 +0000 +@@ -896,8 +896,7 @@ + We get CRC and DEND errors unless we wait for + the SD controller to finish reading/writing to the card. */ + u32 state_mask; +- int timeout=1000000; +- hptime_t now = hptime(); ++ int timeout=1000; + + DBG("PDMA over - sync card\n"); + if (data->flags & MMC_DATA_READ) +@@ -905,17 +904,12 @@ + else + state_mask = SDHCI_DOING_WRITE; + +- while (0 != (sdhci_bcm2708_raw_readl(host, +- SDHCI_PRESENT_STATE) & +- state_mask) && --timeout > 0) ++ while (0 != (sdhci_bcm2708_raw_readl(host, SDHCI_PRESENT_STATE) ++ & state_mask) && --timeout > 0) ++ { ++ udelay(100); + continue; +- +- if (1000000-timeout > 4000) /*ave. is about 3250*/ +- DBG("%s: note - long %s sync %luns - " +- "%d its.\n", +- mmc_hostname(host->mmc), +- data->flags & MMC_DATA_READ? "read": "write", +- since_ns(now), 1000000-timeout); ++ } + if (timeout <= 0) + printk(KERN_ERR"%s: final %s to SD card still " + "running\n", +@@ -1293,10 +1287,7 @@ + + static unsigned int sdhci_bcm2708_missing_status(struct sdhci_host *host) + { +- if(host->last_cmdop == MMC_SEND_STATUS) +- return 1; +- else +- return 0; ++ return 1; + } + + /***************************************************************************** \ diff -Nru linux-3.2.46/debian/patches/rpi/rpi_146_21e287c2206a7a43c1546c8bb5abf0a7ced3dd5e.patch linux-3.2.46/debian/patches/rpi/rpi_146_21e287c2206a7a43c1546c8bb5abf0a7ced3dd5e.patch --- linux-3.2.46/debian/patches/rpi/rpi_146_21e287c2206a7a43c1546c8bb5abf0a7ced3dd5e.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_146_21e287c2206a7a43c1546c8bb5abf0a7ced3dd5e.patch 2013-07-26 19:33:07.000000000 +0000 @@ -0,0 +1,19 @@ +commit 21e287c2206a7a43c1546c8bb5abf0a7ced3dd5e +Author: popcornmix +Date: Thu May 17 14:45:40 2012 +0100 + + Invert sense of sdcard access trigger (OK LED), so it is on when accessing + +Index: linux-3.2.46/arch/arm/mach-bcm2708/bcm2708.c +=================================================================== +--- linux-3.2.46.orig/arch/arm/mach-bcm2708/bcm2708.c 2013-07-26 19:32:48.000000000 +0000 ++++ linux-3.2.46/arch/arm/mach-bcm2708/bcm2708.c 2013-07-26 19:33:07.000000000 +0000 +@@ -614,7 +614,7 @@ + .gpio = 16, + .name = "led0", + .default_trigger = "mmc0", +- .active_low = 0, ++ .active_low = 1, + }, + }; + diff -Nru linux-3.2.46/debian/patches/rpi/rpi_147_06cd09122641b2cc97bd56b8c22bd70905caceff.patch linux-3.2.46/debian/patches/rpi/rpi_147_06cd09122641b2cc97bd56b8c22bd70905caceff.patch --- linux-3.2.46/debian/patches/rpi/rpi_147_06cd09122641b2cc97bd56b8c22bd70905caceff.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_147_06cd09122641b2cc97bd56b8c22bd70905caceff.patch 2013-07-26 19:33:09.000000000 +0000 @@ -0,0 +1,33 @@ +commit 06cd09122641b2cc97bd56b8c22bd70905caceff +Author: popcornmix +Date: Sat May 26 16:40:51 2012 +0100 + + Added power off message to allow kexec to work. Thanks lp0 + +Index: linux-3.2.46/arch/arm/mach-bcm2708/power.c +=================================================================== +--- linux-3.2.46.orig/arch/arm/mach-bcm2708/power.c 2013-07-26 19:33:01.000000000 +0000 ++++ linux-3.2.46/arch/arm/mach-bcm2708/power.c 2013-07-26 19:33:08.000000000 +0000 +@@ -161,6 +161,7 @@ + int i; + + printk(KERN_INFO "bcm_power: Broadcom power driver\n"); ++ bcm_mailbox_write(MBOX_CHAN_POWER, 0); + + for (i = 0; i < BCM_POWER_MAXCLIENTS; i++) + g_state.client_request[i] = BCM_POWER_NOCLIENT; +Index: linux-3.2.46/arch/arm/mach-bcm2708/power.c.rej +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/arch/arm/mach-bcm2708/power.c.rej 2013-07-26 19:33:08.000000000 +0000 +@@ -0,0 +1,10 @@ ++--- arch/arm/mach-bcm2708/power.c +++++ arch/arm/mach-bcm2708/power.c ++@@ -163,6 +163,7 @@ ++ int i; ++ ++ printk(KERN_INFO "bcm_power: Broadcom power driver\n"); +++ bcm_mailbox_write(MBOX_CHAN_POWER, 0); ++ ++ for (i = 0; i < BCM_POWER_MAXCLIENTS; i++) ++ g_state.client_request[i] = BCM_POWER_NOCLIENT; diff -Nru linux-3.2.46/debian/patches/rpi/rpi_148_b7d47f6a347c56d20a75343e71ce5bda75e035d7.patch linux-3.2.46/debian/patches/rpi/rpi_148_b7d47f6a347c56d20a75343e71ce5bda75e035d7.patch --- linux-3.2.46/debian/patches/rpi/rpi_148_b7d47f6a347c56d20a75343e71ce5bda75e035d7.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_148_b7d47f6a347c56d20a75343e71ce5bda75e035d7.patch 2013-07-26 19:33:10.000000000 +0000 @@ -0,0 +1,21 @@ +commit b7d47f6a347c56d20a75343e71ce5bda75e035d7 +Author: popcornmix +Date: Sun May 27 19:24:35 2012 +0100 + + remove unwanted file + +Index: linux-3.2.46/arch/arm/mach-bcm2708/power.c.rej +=================================================================== +--- linux-3.2.46.orig/arch/arm/mach-bcm2708/power.c.rej 2013-07-26 19:33:08.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,10 +0,0 @@ +---- arch/arm/mach-bcm2708/power.c +-+++ arch/arm/mach-bcm2708/power.c +-@@ -163,6 +163,7 @@ +- int i; +- +- printk(KERN_INFO "bcm_power: Broadcom power driver\n"); +-+ bcm_mailbox_write(MBOX_CHAN_POWER, 0); +- +- for (i = 0; i < BCM_POWER_MAXCLIENTS; i++) +- g_state.client_request[i] = BCM_POWER_NOCLIENT; diff -Nru linux-3.2.46/debian/patches/rpi/rpi_149_cb17d60512da813af29a0315585caf32f19d3c77.patch linux-3.2.46/debian/patches/rpi/rpi_149_cb17d60512da813af29a0315585caf32f19d3c77.patch --- linux-3.2.46/debian/patches/rpi/rpi_149_cb17d60512da813af29a0315585caf32f19d3c77.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_149_cb17d60512da813af29a0315585caf32f19d3c77.patch 2013-07-26 19:33:11.000000000 +0000 @@ -0,0 +1,57 @@ +commit cb17d60512da813af29a0315585caf32f19d3c77 +Author: popcornmix +Date: Tue May 29 00:04:15 2012 +0100 + + Enable PREEMPT and SCHED_AUTOGROUP + +Index: linux-3.2.46/arch/arm/configs/bcmrpi_cutdown_defconfig +=================================================================== +--- linux-3.2.46.orig/arch/arm/configs/bcmrpi_cutdown_defconfig 2013-07-26 19:32:46.000000000 +0000 ++++ linux-3.2.46/arch/arm/configs/bcmrpi_cutdown_defconfig 2013-07-26 19:33:10.000000000 +0000 +@@ -2,8 +2,10 @@ + # CONFIG_LOCALVERSION_AUTO is not set + CONFIG_SYSVIPC=y + CONFIG_POSIX_MQUEUE=y ++CONFIG_TINY_RCU=y + CONFIG_IKCONFIG=y + CONFIG_IKCONFIG_PROC=y ++CONFIG_SCHED_AUTOGROUP=y + # CONFIG_UID16 is not set + # CONFIG_KALLSYMS is not set + CONFIG_EMBEDDED=y +@@ -18,6 +20,7 @@ + CONFIG_ARCH_BCM2708=y + CONFIG_NO_HZ=y + CONFIG_HIGH_RES_TIMERS=y ++CONFIG_PREEMPT=y + CONFIG_AEABI=y + CONFIG_ZBOOT_ROM_TEXT=0x0 + CONFIG_ZBOOT_ROM_BSS=0x0 +@@ -471,6 +474,7 @@ + CONFIG_NLS_KOI8_U=m + CONFIG_NLS_UTF8=m + # CONFIG_SCHED_DEBUG is not set ++# CONFIG_DEBUG_PREEMPT is not set + # CONFIG_DEBUG_BUGVERBOSE is not set + # CONFIG_FTRACE is not set + # CONFIG_ARM_UNWIND is not set +Index: linux-3.2.46/arch/arm/configs/bcmrpi_defconfig +=================================================================== +--- linux-3.2.46.orig/arch/arm/configs/bcmrpi_defconfig 2013-07-26 19:32:46.000000000 +0000 ++++ linux-3.2.46/arch/arm/configs/bcmrpi_defconfig 2013-07-26 19:33:10.000000000 +0000 +@@ -6,6 +6,7 @@ + CONFIG_BSD_PROCESS_ACCT_V3=y + CONFIG_FHANDLE=y + CONFIG_AUDIT=y ++CONFIG_TINY_RCU=y + CONFIG_IKCONFIG=y + CONFIG_IKCONFIG_PROC=y + CONFIG_CGROUP_FREEZER=y +@@ -31,6 +32,7 @@ + CONFIG_ARCH_BCM2708=y + CONFIG_NO_HZ=y + CONFIG_HIGH_RES_TIMERS=y ++CONFIG_PREEMPT=y + CONFIG_AEABI=y + CONFIG_SECCOMP=y + CONFIG_CC_STACKPROTECTOR=y diff -Nru linux-3.2.46/debian/patches/rpi/rpi_150_025a245c362b4ad3d8ca8b93512464d94247a182.patch linux-3.2.46/debian/patches/rpi/rpi_150_025a245c362b4ad3d8ca8b93512464d94247a182.patch --- linux-3.2.46/debian/patches/rpi/rpi_150_025a245c362b4ad3d8ca8b93512464d94247a182.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_150_025a245c362b4ad3d8ca8b93512464d94247a182.patch 2013-07-26 19:33:13.000000000 +0000 @@ -0,0 +1,184 @@ +commit 025a245c362b4ad3d8ca8b93512464d94247a182 +Author: popcornmix +Date: Wed May 30 11:57:52 2012 +0100 + + Added support for USB webcams + +Index: linux-3.2.46/arch/arm/configs/bcmrpi_cutdown_defconfig +=================================================================== +--- linux-3.2.46.orig/arch/arm/configs/bcmrpi_cutdown_defconfig 2013-07-26 19:33:10.000000000 +0000 ++++ linux-3.2.46/arch/arm/configs/bcmrpi_cutdown_defconfig 2013-07-26 19:33:12.000000000 +0000 +@@ -205,6 +205,58 @@ + CONFIG_WATCHDOG=y + CONFIG_BCM2708_WDT=m + # CONFIG_MFD_SUPPORT is not set ++CONFIG_MEDIA_SUPPORT=m ++CONFIG_VIDEO_DEV=m ++CONFIG_USB_VIDEO_CLASS=m ++CONFIG_USB_M5602=m ++CONFIG_USB_STV06XX=m ++CONFIG_USB_GL860=m ++CONFIG_USB_GSPCA_BENQ=m ++CONFIG_USB_GSPCA_CONEX=m ++CONFIG_USB_GSPCA_CPIA1=m ++CONFIG_USB_GSPCA_ETOMS=m ++CONFIG_USB_GSPCA_FINEPIX=m ++CONFIG_USB_GSPCA_JEILINJ=m ++CONFIG_USB_GSPCA_KINECT=m ++CONFIG_USB_GSPCA_KONICA=m ++CONFIG_USB_GSPCA_MARS=m ++CONFIG_USB_GSPCA_MR97310A=m ++CONFIG_USB_GSPCA_NW80X=m ++CONFIG_USB_GSPCA_OV519=m ++CONFIG_USB_GSPCA_OV534=m ++CONFIG_USB_GSPCA_OV534_9=m ++CONFIG_USB_GSPCA_PAC207=m ++CONFIG_USB_GSPCA_PAC7302=m ++CONFIG_USB_GSPCA_PAC7311=m ++CONFIG_USB_GSPCA_SE401=m ++CONFIG_USB_GSPCA_SN9C2028=m ++CONFIG_USB_GSPCA_SN9C20X=m ++CONFIG_USB_GSPCA_SONIXB=m ++CONFIG_USB_GSPCA_SONIXJ=m ++CONFIG_USB_GSPCA_SPCA500=m ++CONFIG_USB_GSPCA_SPCA501=m ++CONFIG_USB_GSPCA_SPCA505=m ++CONFIG_USB_GSPCA_SPCA506=m ++CONFIG_USB_GSPCA_SPCA508=m ++CONFIG_USB_GSPCA_SPCA561=m ++CONFIG_USB_GSPCA_SPCA1528=m ++CONFIG_USB_GSPCA_SQ905=m ++CONFIG_USB_GSPCA_SQ905C=m ++CONFIG_USB_GSPCA_SQ930X=m ++CONFIG_USB_GSPCA_STK014=m ++CONFIG_USB_GSPCA_STV0680=m ++CONFIG_USB_GSPCA_SUNPLUS=m ++CONFIG_USB_GSPCA_T613=m ++CONFIG_USB_GSPCA_TV8532=m ++CONFIG_USB_GSPCA_VC032X=m ++CONFIG_USB_GSPCA_VICAM=m ++CONFIG_USB_GSPCA_XIRLINK_CIT=m ++CONFIG_USB_GSPCA_ZC3XX=m ++CONFIG_VIDEO_HDPVR=m ++CONFIG_USB_PWC=m ++CONFIG_USB_ZR364XX=m ++CONFIG_USB_STKWEBCAM=m ++CONFIG_USB_S2255=m + CONFIG_FB=y + CONFIG_FB_BCM2708=y + CONFIG_FRAMEBUFFER_CONSOLE=y +Index: linux-3.2.46/arch/arm/configs/bcmrpi_defconfig +=================================================================== +--- linux-3.2.46.orig/arch/arm/configs/bcmrpi_defconfig 2013-07-26 19:33:10.000000000 +0000 ++++ linux-3.2.46/arch/arm/configs/bcmrpi_defconfig 2013-07-26 19:33:12.000000000 +0000 +@@ -29,19 +29,15 @@ + # CONFIG_BLK_DEV_BSG is not set + CONFIG_BLK_DEV_THROTTLING=y + CONFIG_CFQ_GROUP_IOSCHED=y +-CONFIG_ARCH_BCM2708=y ++CONFIG_PCI=y + CONFIG_NO_HZ=y + CONFIG_HIGH_RES_TIMERS=y + CONFIG_PREEMPT=y +-CONFIG_AEABI=y ++CONFIG_HIGHMEM=y + CONFIG_SECCOMP=y + CONFIG_CC_STACKPROTECTOR=y +-CONFIG_ZBOOT_ROM_TEXT=0x0 +-CONFIG_ZBOOT_ROM_BSS=0x0 +-CONFIG_CMDLINE="dwc_otg.lpm_enable=0 console=ttyAMA0,115200 kgdboc=ttyAMA0,115200 root=/dev/mmcblk0p2 rootfstype=ext3 rootwait" + CONFIG_KEXEC=y + CONFIG_CPU_IDLE=y +-CONFIG_VFP=y + CONFIG_BINFMT_MISC=m + CONFIG_NET=y + CONFIG_PACKET=y +@@ -212,17 +208,67 @@ + CONFIG_VT_HW_CONSOLE_BINDING=y + # CONFIG_LEGACY_PTYS is not set + # CONFIG_DEVKMEM is not set +-CONFIG_SERIAL_AMBA_PL011=y +-CONFIG_SERIAL_AMBA_PL011_CONSOLE=y + # CONFIG_HW_RANDOM is not set + CONFIG_RAW_DRIVER=y ++CONFIG_GPIOLIB=y + CONFIG_GPIO_SYSFS=y ++CONFIG_POWER_SUPPLY=y + # CONFIG_HWMON is not set ++CONFIG_THERMAL=y + CONFIG_WATCHDOG=y +-CONFIG_BCM2708_WDT=m + # CONFIG_MFD_SUPPORT is not set ++CONFIG_MEDIA_SUPPORT=m ++CONFIG_VIDEO_DEV=m ++CONFIG_USB_VIDEO_CLASS=m ++CONFIG_USB_M5602=m ++CONFIG_USB_STV06XX=m ++CONFIG_USB_GL860=m ++CONFIG_USB_GSPCA_BENQ=m ++CONFIG_USB_GSPCA_CONEX=m ++CONFIG_USB_GSPCA_CPIA1=m ++CONFIG_USB_GSPCA_ETOMS=m ++CONFIG_USB_GSPCA_FINEPIX=m ++CONFIG_USB_GSPCA_JEILINJ=m ++CONFIG_USB_GSPCA_KINECT=m ++CONFIG_USB_GSPCA_KONICA=m ++CONFIG_USB_GSPCA_MARS=m ++CONFIG_USB_GSPCA_MR97310A=m ++CONFIG_USB_GSPCA_NW80X=m ++CONFIG_USB_GSPCA_OV519=m ++CONFIG_USB_GSPCA_OV534=m ++CONFIG_USB_GSPCA_OV534_9=m ++CONFIG_USB_GSPCA_PAC207=m ++CONFIG_USB_GSPCA_PAC7302=m ++CONFIG_USB_GSPCA_PAC7311=m ++CONFIG_USB_GSPCA_SE401=m ++CONFIG_USB_GSPCA_SN9C2028=m ++CONFIG_USB_GSPCA_SN9C20X=m ++CONFIG_USB_GSPCA_SONIXB=m ++CONFIG_USB_GSPCA_SONIXJ=m ++CONFIG_USB_GSPCA_SPCA500=m ++CONFIG_USB_GSPCA_SPCA501=m ++CONFIG_USB_GSPCA_SPCA505=m ++CONFIG_USB_GSPCA_SPCA506=m ++CONFIG_USB_GSPCA_SPCA508=m ++CONFIG_USB_GSPCA_SPCA561=m ++CONFIG_USB_GSPCA_SPCA1528=m ++CONFIG_USB_GSPCA_SQ905=m ++CONFIG_USB_GSPCA_SQ905C=m ++CONFIG_USB_GSPCA_SQ930X=m ++CONFIG_USB_GSPCA_STK014=m ++CONFIG_USB_GSPCA_STV0680=m ++CONFIG_USB_GSPCA_SUNPLUS=m ++CONFIG_USB_GSPCA_T613=m ++CONFIG_USB_GSPCA_TV8532=m ++CONFIG_USB_GSPCA_VC032X=m ++CONFIG_USB_GSPCA_VICAM=m ++CONFIG_USB_GSPCA_XIRLINK_CIT=m ++CONFIG_USB_GSPCA_ZC3XX=m ++CONFIG_USB_PWC=m ++CONFIG_USB_ZR364XX=m ++CONFIG_USB_STKWEBCAM=m ++CONFIG_USB_S2255=m + CONFIG_FB=y +-CONFIG_FB_BCM2708=y + CONFIG_FRAMEBUFFER_CONSOLE=y + CONFIG_LOGO=y + # CONFIG_LOGO_LINUX_MONO is not set +@@ -241,7 +287,6 @@ + CONFIG_SND_MTPAV=m + CONFIG_SND_SERIAL_U16550=m + CONFIG_SND_MPU401=m +-CONFIG_SND_BCM2835=m + CONFIG_SND_USB_AUDIO=m + CONFIG_SND_USB_UA101=m + CONFIG_SND_USB_CAIAQ=m +@@ -387,8 +432,6 @@ + CONFIG_MMC=y + CONFIG_MMC_SDHCI=y + CONFIG_MMC_SDHCI_PLTFM=y +-CONFIG_MMC_SDHCI_BCM2708=y +-CONFIG_MMC_SDHCI_BCM2708_DMA=y + CONFIG_LEDS_GPIO=y + CONFIG_LEDS_TRIGGER_TIMER=m + CONFIG_LEDS_TRIGGER_HEARTBEAT=m diff -Nru linux-3.2.46/debian/patches/rpi/rpi_151_9c7a53428ac1ec88d250a0fd284e372e50b2b45d.patch linux-3.2.46/debian/patches/rpi/rpi_151_9c7a53428ac1ec88d250a0fd284e372e50b2b45d.patch --- linux-3.2.46/debian/patches/rpi/rpi_151_9c7a53428ac1ec88d250a0fd284e372e50b2b45d.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_151_9c7a53428ac1ec88d250a0fd284e372e50b2b45d.patch 2013-07-26 19:33:14.000000000 +0000 @@ -0,0 +1,32 @@ +commit 9c7a53428ac1ec88d250a0fd284e372e50b2b45d +Author: popcornmix +Date: Wed May 30 21:54:02 2012 +0100 + + Enable ipv6 due to popular demand + +Index: linux-3.2.46/arch/arm/configs/bcmrpi_cutdown_defconfig +=================================================================== +--- linux-3.2.46.orig/arch/arm/configs/bcmrpi_cutdown_defconfig 2013-07-26 19:33:12.000000000 +0000 ++++ linux-3.2.46/arch/arm/configs/bcmrpi_cutdown_defconfig 2013-07-26 19:33:13.000000000 +0000 +@@ -44,7 +44,7 @@ + # CONFIG_INET_XFRM_MODE_BEET is not set + # CONFIG_INET_LRO is not set + # CONFIG_INET_DIAG is not set +-# CONFIG_IPV6 is not set ++CONFIG_IPV6_PRIVACY=y + CONFIG_NET_PKTGEN=m + CONFIG_IRDA=m + CONFIG_IRLAN=m +Index: linux-3.2.46/arch/arm/configs/bcmrpi_defconfig +=================================================================== +--- linux-3.2.46.orig/arch/arm/configs/bcmrpi_defconfig 2013-07-26 19:33:12.000000000 +0000 ++++ linux-3.2.46/arch/arm/configs/bcmrpi_defconfig 2013-07-26 19:33:13.000000000 +0000 +@@ -55,7 +55,7 @@ + # CONFIG_INET_XFRM_MODE_BEET is not set + # CONFIG_INET_LRO is not set + # CONFIG_INET_DIAG is not set +-# CONFIG_IPV6 is not set ++CONFIG_IPV6_PRIVACY=y + CONFIG_NET_PKTGEN=m + CONFIG_IRDA=m + CONFIG_IRLAN=m diff -Nru linux-3.2.46/debian/patches/rpi/rpi_152_69020137b6172a263b77b98f4509293cfb9a202f.patch linux-3.2.46/debian/patches/rpi/rpi_152_69020137b6172a263b77b98f4509293cfb9a202f.patch --- linux-3.2.46/debian/patches/rpi/rpi_152_69020137b6172a263b77b98f4509293cfb9a202f.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_152_69020137b6172a263b77b98f4509293cfb9a202f.patch 2013-07-26 19:33:15.000000000 +0000 @@ -0,0 +1,81 @@ +commit 69020137b6172a263b77b98f4509293cfb9a202f +Author: popcornmix +Date: Thu May 31 13:01:16 2012 +0100 + + Fix regression in debug kernel config options + +Index: linux-3.2.46/arch/arm/configs/bcmrpi_defconfig +=================================================================== +--- linux-3.2.46.orig/arch/arm/configs/bcmrpi_defconfig 2013-07-26 19:33:13.000000000 +0000 ++++ linux-3.2.46/arch/arm/configs/bcmrpi_defconfig 2013-07-26 19:33:14.000000000 +0000 +@@ -29,15 +29,19 @@ + # CONFIG_BLK_DEV_BSG is not set + CONFIG_BLK_DEV_THROTTLING=y + CONFIG_CFQ_GROUP_IOSCHED=y +-CONFIG_PCI=y ++CONFIG_ARCH_BCM2708=y + CONFIG_NO_HZ=y + CONFIG_HIGH_RES_TIMERS=y + CONFIG_PREEMPT=y +-CONFIG_HIGHMEM=y ++CONFIG_AEABI=y + CONFIG_SECCOMP=y + CONFIG_CC_STACKPROTECTOR=y ++CONFIG_ZBOOT_ROM_TEXT=0x0 ++CONFIG_ZBOOT_ROM_BSS=0x0 ++CONFIG_CMDLINE="dwc_otg.lpm_enable=0 console=ttyAMA0,115200 kgdboc=ttyAMA0,115200 root=/dev/mmcblk0p2 rootfstype=ext3 rootwait" + CONFIG_KEXEC=y + CONFIG_CPU_IDLE=y ++CONFIG_VFP=y + CONFIG_BINFMT_MISC=m + CONFIG_NET=y + CONFIG_PACKET=y +@@ -208,14 +212,14 @@ + CONFIG_VT_HW_CONSOLE_BINDING=y + # CONFIG_LEGACY_PTYS is not set + # CONFIG_DEVKMEM is not set ++CONFIG_SERIAL_AMBA_PL011=y ++CONFIG_SERIAL_AMBA_PL011_CONSOLE=y + # CONFIG_HW_RANDOM is not set + CONFIG_RAW_DRIVER=y +-CONFIG_GPIOLIB=y + CONFIG_GPIO_SYSFS=y +-CONFIG_POWER_SUPPLY=y + # CONFIG_HWMON is not set +-CONFIG_THERMAL=y + CONFIG_WATCHDOG=y ++CONFIG_BCM2708_WDT=m + # CONFIG_MFD_SUPPORT is not set + CONFIG_MEDIA_SUPPORT=m + CONFIG_VIDEO_DEV=m +@@ -264,11 +268,13 @@ + CONFIG_USB_GSPCA_VICAM=m + CONFIG_USB_GSPCA_XIRLINK_CIT=m + CONFIG_USB_GSPCA_ZC3XX=m ++CONFIG_VIDEO_HDPVR=m + CONFIG_USB_PWC=m + CONFIG_USB_ZR364XX=m + CONFIG_USB_STKWEBCAM=m + CONFIG_USB_S2255=m + CONFIG_FB=y ++CONFIG_FB_BCM2708=y + CONFIG_FRAMEBUFFER_CONSOLE=y + CONFIG_LOGO=y + # CONFIG_LOGO_LINUX_MONO is not set +@@ -287,6 +293,7 @@ + CONFIG_SND_MTPAV=m + CONFIG_SND_SERIAL_U16550=m + CONFIG_SND_MPU401=m ++CONFIG_SND_BCM2835=m + CONFIG_SND_USB_AUDIO=m + CONFIG_SND_USB_UA101=m + CONFIG_SND_USB_CAIAQ=m +@@ -432,6 +439,8 @@ + CONFIG_MMC=y + CONFIG_MMC_SDHCI=y + CONFIG_MMC_SDHCI_PLTFM=y ++CONFIG_MMC_SDHCI_BCM2708=y ++CONFIG_MMC_SDHCI_BCM2708_DMA=y + CONFIG_LEDS_GPIO=y + CONFIG_LEDS_TRIGGER_TIMER=m + CONFIG_LEDS_TRIGGER_HEARTBEAT=m diff -Nru linux-3.2.46/debian/patches/rpi/rpi_153_999b9c7a9cb1d7cbb8b4407ddfa33a2a39ee09b2.patch linux-3.2.46/debian/patches/rpi/rpi_153_999b9c7a9cb1d7cbb8b4407ddfa33a2a39ee09b2.patch --- linux-3.2.46/debian/patches/rpi/rpi_153_999b9c7a9cb1d7cbb8b4407ddfa33a2a39ee09b2.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_153_999b9c7a9cb1d7cbb8b4407ddfa33a2a39ee09b2.patch 2013-07-26 19:33:17.000000000 +0000 @@ -0,0 +1,58 @@ +commit 999b9c7a9cb1d7cbb8b4407ddfa33a2a39ee09b2 +Author: Arne Fitzenreiter +Date: Wed Jun 6 08:02:10 2012 +0200 + + bcm2835-ctl: fix alsamixer control. + + alsamixer read the volume for the screen controller so we had to + scale the chipvol back to db for reading. + +Index: linux-3.2.46/sound/arm/bcm2835-ctl.c +=================================================================== +--- linux-3.2.46.orig/sound/arm/bcm2835-ctl.c 2013-07-26 19:32:35.000000000 +0000 ++++ linux-3.2.46/sound/arm/bcm2835-ctl.c 2013-07-26 19:33:16.000000000 +0000 +@@ -33,6 +33,19 @@ + + #include "bcm2835.h" + ++ ++/* functions to convert alsa to chip volume and back. */ ++int alsa2chip(int vol) ++{ ++ return -((vol << 8) / 100); ++} ++ ++int chip2alsa(int vol) ++{ ++ return -((vol * 100) >> 8); ++} ++ ++ + static int snd_bcm2835_ctl_info(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_info *uinfo) + { +@@ -64,7 +77,7 @@ + BUG_ON(!chip && !(chip->avail_substreams & AVAIL_SUBSTREAMS_MASK)); + + if (kcontrol->private_value == PCM_PLAYBACK_VOLUME) +- ucontrol->value.integer.value[0] = chip->volume; ++ ucontrol->value.integer.value[0] = chip2alsa(chip->volume); + else if (kcontrol->private_value == PCM_PLAYBACK_MUTE) + ucontrol->value.integer.value[0] = chip->mute; + else if (kcontrol->private_value == PCM_PLAYBACK_DEVICE) +@@ -85,13 +98,10 @@ + changed = 1; + } + if (changed +- || (ucontrol->value.integer.value[0] != chip->volume)) { +- int atten; ++ || (ucontrol->value.integer.value[0] != chip2alsa(chip->volume))) { + +- chip->volume = ucontrol->value.integer.value[0]; ++ chip->volume = alsa2chip(ucontrol->value.integer.value[0]); + changed = 1; +- atten = -((chip->volume << 8) / 100); +- chip->volume = atten; + } + + } else if (kcontrol->private_value == PCM_PLAYBACK_MUTE) { diff -Nru linux-3.2.46/debian/patches/rpi/rpi_154_eec485b89354fcfd8acb2f6c9943aad5496b467c.patch linux-3.2.46/debian/patches/rpi/rpi_154_eec485b89354fcfd8acb2f6c9943aad5496b467c.patch --- linux-3.2.46/debian/patches/rpi/rpi_154_eec485b89354fcfd8acb2f6c9943aad5496b467c.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_154_eec485b89354fcfd8acb2f6c9943aad5496b467c.patch 2013-07-26 19:33:18.000000000 +0000 @@ -0,0 +1,21 @@ +commit eec485b89354fcfd8acb2f6c9943aad5496b467c +Author: Arne Fitzenreiter +Date: Wed Jun 6 08:06:15 2012 +0200 + + bcm2835-ctl: limit maximal volume to 4db. + + it makes no sense to set 23.04db as maximum volume since around 3db it start to cliping. So with 4db the alsamixer is much better to control. (86% is 0db) + +Index: linux-3.2.46/sound/arm/bcm2835-ctl.c +=================================================================== +--- linux-3.2.46.orig/sound/arm/bcm2835-ctl.c 2013-07-26 19:33:16.000000000 +0000 ++++ linux-3.2.46/sound/arm/bcm2835-ctl.c 2013-07-26 19:33:17.000000000 +0000 +@@ -53,7 +53,7 @@ + uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; + uinfo->count = 1; + uinfo->value.integer.min = -10240; +- uinfo->value.integer.max = 2303; ++ uinfo->value.integer.max = 400; /* 2303 */ + } else if (kcontrol->private_value == PCM_PLAYBACK_MUTE) { + uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; + uinfo->count = 1; diff -Nru linux-3.2.46/debian/patches/rpi/rpi_155_0d390569262bfc90538ea3d3454916f866f06071.patch linux-3.2.46/debian/patches/rpi/rpi_155_0d390569262bfc90538ea3d3454916f866f06071.patch --- linux-3.2.46/debian/patches/rpi/rpi_155_0d390569262bfc90538ea3d3454916f866f06071.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_155_0d390569262bfc90538ea3d3454916f866f06071.patch 2013-07-26 19:33:19.000000000 +0000 @@ -0,0 +1,253 @@ +commit 0d390569262bfc90538ea3d3454916f866f06071 +Author: popcornmix +Date: Sun Jun 10 13:32:02 2012 +0100 + + Add iptables and devtmpfs_mount to non-cutdown config. This will become default kernel + +Index: linux-3.2.46/arch/arm/configs/bcmrpi_cutdown_defconfig +=================================================================== +--- linux-3.2.46.orig/arch/arm/configs/bcmrpi_cutdown_defconfig 2013-07-26 19:33:13.000000000 +0000 ++++ linux-3.2.46/arch/arm/configs/bcmrpi_cutdown_defconfig 2013-07-26 19:33:18.000000000 +0000 +@@ -85,6 +85,7 @@ + CONFIG_NFC=m + CONFIG_NFC_PN533=m + CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y + CONFIG_BLK_DEV_LOOP=y + CONFIG_BLK_DEV_CRYPTOLOOP=m + CONFIG_BLK_DEV_NBD=m +Index: linux-3.2.46/arch/arm/configs/bcmrpi_defconfig +=================================================================== +--- linux-3.2.46.orig/arch/arm/configs/bcmrpi_defconfig 2013-07-26 19:33:14.000000000 +0000 ++++ linux-3.2.46/arch/arm/configs/bcmrpi_defconfig 2013-07-26 19:33:18.000000000 +0000 +@@ -34,6 +34,7 @@ + CONFIG_HIGH_RES_TIMERS=y + CONFIG_PREEMPT=y + CONFIG_AEABI=y ++CONFIG_UACCESS_WITH_MEMCPY=y + CONFIG_SECCOMP=y + CONFIG_CC_STACKPROTECTOR=y + CONFIG_ZBOOT_ROM_TEXT=0x0 +@@ -50,19 +51,142 @@ + CONFIG_NET_KEY=m + CONFIG_INET=y + CONFIG_IP_MULTICAST=y ++CONFIG_IP_ADVANCED_ROUTER=y ++CONFIG_IP_MULTIPLE_TABLES=y ++CONFIG_IP_ROUTE_MULTIPATH=y ++CONFIG_IP_ROUTE_VERBOSE=y + CONFIG_IP_PNP=y + CONFIG_IP_PNP_DHCP=y + CONFIG_IP_PNP_RARP=y ++CONFIG_NET_IPIP=m + CONFIG_SYN_COOKIES=y + # CONFIG_INET_XFRM_MODE_TRANSPORT is not set + # CONFIG_INET_XFRM_MODE_TUNNEL is not set + # CONFIG_INET_XFRM_MODE_BEET is not set +-# CONFIG_INET_LRO is not set + # CONFIG_INET_DIAG is not set + CONFIG_IPV6_PRIVACY=y ++CONFIG_NETFILTER=y ++CONFIG_NF_CONNTRACK=m ++CONFIG_NF_CONNTRACK_ZONES=y ++CONFIG_NF_CONNTRACK_EVENTS=y ++CONFIG_NF_CONNTRACK_TIMESTAMP=y ++CONFIG_NF_CT_PROTO_DCCP=m ++CONFIG_NF_CT_PROTO_SCTP=m ++CONFIG_NF_CT_PROTO_UDPLITE=m ++CONFIG_NF_CONNTRACK_AMANDA=m ++CONFIG_NF_CONNTRACK_FTP=m ++CONFIG_NF_CONNTRACK_H323=m ++CONFIG_NF_CONNTRACK_IRC=m ++CONFIG_NF_CONNTRACK_NETBIOS_NS=m ++CONFIG_NF_CONNTRACK_SNMP=m ++CONFIG_NF_CONNTRACK_PPTP=m ++CONFIG_NF_CONNTRACK_SANE=m ++CONFIG_NF_CONNTRACK_SIP=m ++CONFIG_NF_CONNTRACK_TFTP=m ++CONFIG_NF_CT_NETLINK=m ++CONFIG_NETFILTER_TPROXY=m ++CONFIG_NETFILTER_XT_SET=m ++CONFIG_NETFILTER_XT_TARGET_AUDIT=m ++CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m ++CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m ++CONFIG_NETFILTER_XT_TARGET_CONNMARK=m ++CONFIG_NETFILTER_XT_TARGET_CT=m ++CONFIG_NETFILTER_XT_TARGET_DSCP=m ++CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m ++CONFIG_NETFILTER_XT_TARGET_LED=m ++CONFIG_NETFILTER_XT_TARGET_MARK=m ++CONFIG_NETFILTER_XT_TARGET_NFLOG=m ++CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m ++CONFIG_NETFILTER_XT_TARGET_NOTRACK=m ++CONFIG_NETFILTER_XT_TARGET_TEE=m ++CONFIG_NETFILTER_XT_TARGET_TPROXY=m ++CONFIG_NETFILTER_XT_TARGET_TRACE=m ++CONFIG_NETFILTER_XT_TARGET_TCPMSS=m ++CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m ++CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m ++CONFIG_NETFILTER_XT_MATCH_CLUSTER=m ++CONFIG_NETFILTER_XT_MATCH_COMMENT=m ++CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m ++CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m ++CONFIG_NETFILTER_XT_MATCH_CONNMARK=m ++CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m ++CONFIG_NETFILTER_XT_MATCH_CPU=m ++CONFIG_NETFILTER_XT_MATCH_DCCP=m ++CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m ++CONFIG_NETFILTER_XT_MATCH_DSCP=m ++CONFIG_NETFILTER_XT_MATCH_ESP=m ++CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m ++CONFIG_NETFILTER_XT_MATCH_HELPER=m ++CONFIG_NETFILTER_XT_MATCH_IPRANGE=m ++CONFIG_NETFILTER_XT_MATCH_LENGTH=m ++CONFIG_NETFILTER_XT_MATCH_LIMIT=m ++CONFIG_NETFILTER_XT_MATCH_MAC=m ++CONFIG_NETFILTER_XT_MATCH_MARK=m ++CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m ++CONFIG_NETFILTER_XT_MATCH_OSF=m ++CONFIG_NETFILTER_XT_MATCH_OWNER=m ++CONFIG_NETFILTER_XT_MATCH_POLICY=m ++CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m ++CONFIG_NETFILTER_XT_MATCH_QUOTA=m ++CONFIG_NETFILTER_XT_MATCH_RATEEST=m ++CONFIG_NETFILTER_XT_MATCH_REALM=m ++CONFIG_NETFILTER_XT_MATCH_RECENT=m ++CONFIG_NETFILTER_XT_MATCH_SCTP=m ++CONFIG_NETFILTER_XT_MATCH_SOCKET=m ++CONFIG_NETFILTER_XT_MATCH_STATE=m ++CONFIG_NETFILTER_XT_MATCH_STATISTIC=m ++CONFIG_NETFILTER_XT_MATCH_STRING=m ++CONFIG_NETFILTER_XT_MATCH_TCPMSS=m ++CONFIG_NETFILTER_XT_MATCH_TIME=m ++CONFIG_NETFILTER_XT_MATCH_U32=m ++CONFIG_IP_SET=m ++CONFIG_IP_SET_BITMAP_IP=m ++CONFIG_IP_SET_BITMAP_IPMAC=m ++CONFIG_IP_SET_BITMAP_PORT=m ++CONFIG_IP_SET_HASH_IP=m ++CONFIG_IP_SET_HASH_IPPORT=m ++CONFIG_IP_SET_HASH_IPPORTIP=m ++CONFIG_IP_SET_HASH_IPPORTNET=m ++CONFIG_IP_SET_HASH_NET=m ++CONFIG_IP_SET_HASH_NETPORT=m ++CONFIG_IP_SET_HASH_NETIFACE=m ++CONFIG_IP_SET_LIST_SET=m ++CONFIG_NF_CONNTRACK_IPV4=m ++CONFIG_IP_NF_IPTABLES=m ++CONFIG_IP_NF_MATCH_AH=m ++CONFIG_IP_NF_MATCH_ECN=m ++CONFIG_IP_NF_MATCH_TTL=m ++CONFIG_IP_NF_FILTER=m ++CONFIG_IP_NF_TARGET_REJECT=m ++CONFIG_IP_NF_TARGET_LOG=m ++CONFIG_IP_NF_TARGET_ULOG=m ++CONFIG_IP_NF_MANGLE=m ++CONFIG_IP_NF_TARGET_ECN=m ++CONFIG_IP_NF_TARGET_TTL=m ++CONFIG_IP_NF_RAW=m ++CONFIG_IP_NF_ARPTABLES=m ++CONFIG_IP_NF_ARPFILTER=m ++CONFIG_IP_NF_ARP_MANGLE=m ++CONFIG_NF_CONNTRACK_IPV6=m ++CONFIG_IP6_NF_IPTABLES=m ++CONFIG_IP6_NF_MATCH_AH=m ++CONFIG_IP6_NF_MATCH_EUI64=m ++CONFIG_IP6_NF_MATCH_FRAG=m ++CONFIG_IP6_NF_MATCH_OPTS=m ++CONFIG_IP6_NF_MATCH_HL=m ++CONFIG_IP6_NF_MATCH_IPV6HEADER=m ++CONFIG_IP6_NF_MATCH_MH=m ++CONFIG_IP6_NF_MATCH_RT=m ++CONFIG_IP6_NF_TARGET_HL=m ++CONFIG_IP6_NF_TARGET_LOG=m ++CONFIG_IP6_NF_FILTER=m ++CONFIG_IP6_NF_TARGET_REJECT=m ++CONFIG_IP6_NF_MANGLE=m ++CONFIG_IP6_NF_RAW=m + CONFIG_NET_PKTGEN=m + CONFIG_IRDA=m + CONFIG_IRLAN=m ++CONFIG_IRNET=m + CONFIG_IRCOMM=m + CONFIG_IRDA_ULTRA=y + CONFIG_IRDA_CACHE_LAST_LSAP=y +@@ -99,7 +223,8 @@ + CONFIG_NET_9P=m + CONFIG_NFC=m + CONFIG_NFC_PN533=m +-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" ++CONFIG_DEVTMPFS=y ++CONFIG_CONNECTOR=m + CONFIG_BLK_DEV_LOOP=y + CONFIG_BLK_DEV_CRYPTOLOOP=m + CONFIG_BLK_DEV_NBD=m +@@ -132,6 +257,7 @@ + CONFIG_ATH9K_HTC=m + CONFIG_CARL9170=m + CONFIG_B43=m ++CONFIG_B43_PHY_N=y + CONFIG_B43LEGACY=m + CONFIG_HOSTAP=m + CONFIG_IWM=m +@@ -183,6 +309,7 @@ + CONFIG_PPP_SYNC_TTY=m + CONFIG_PPP_DEFLATE=m + CONFIG_PPP_BSDCOMP=m ++CONFIG_PPPOE=m + CONFIG_SLIP=m + CONFIG_SLIP_COMPRESSED=y + CONFIG_NETCONSOLE=m +@@ -214,6 +341,7 @@ + # CONFIG_DEVKMEM is not set + CONFIG_SERIAL_AMBA_PL011=y + CONFIG_SERIAL_AMBA_PL011_CONSOLE=y ++CONFIG_TTY_PRINTK=y + # CONFIG_HW_RANDOM is not set + CONFIG_RAW_DRIVER=y + CONFIG_GPIO_SYSFS=y +@@ -273,6 +401,10 @@ + CONFIG_USB_ZR364XX=m + CONFIG_USB_STKWEBCAM=m + CONFIG_USB_S2255=m ++CONFIG_USB_DSBR=m ++CONFIG_RADIO_SI470X=y ++CONFIG_USB_SI470X=m ++CONFIG_USB_MR800=m + CONFIG_FB=y + CONFIG_FB_BCM2708=y + CONFIG_FRAMEBUFFER_CONSOLE=y +@@ -448,6 +580,11 @@ + CONFIG_UIO=m + CONFIG_UIO_PDRV=m + CONFIG_UIO_PDRV_GENIRQ=m ++CONFIG_STAGING=y ++CONFIG_W35UND=m ++CONFIG_PRISM2_USB=m ++CONFIG_R8712U=m ++CONFIG_ZRAM=m + # CONFIG_IOMMU_SUPPORT is not set + CONFIG_EXT4_FS=y + CONFIG_EXT4_FS_POSIX_ACL=y +@@ -549,13 +686,14 @@ + CONFIG_PRINTK_TIME=y + CONFIG_DETECT_HUNG_TASK=y + CONFIG_TIMER_STATS=y +-CONFIG_DEBUG_STACK_USAGE=y +-CONFIG_DEBUG_INFO=y ++# CONFIG_DEBUG_PREEMPT is not set + CONFIG_DEBUG_MEMORY_INIT=y + CONFIG_BOOT_PRINTK_DELAY=y + CONFIG_LATENCYTOP=y + CONFIG_SYSCTL_SYSCALL_CHECK=y ++# CONFIG_EVENT_POWER_TRACING_DEPRECATED is not set + CONFIG_IRQSOFF_TRACER=y ++CONFIG_PREEMPT_TRACER=y + CONFIG_SCHED_TRACER=y + CONFIG_STACK_TRACER=y + CONFIG_BLK_DEV_IO_TRACE=y +@@ -582,3 +720,4 @@ + # CONFIG_CRYPTO_HW is not set + CONFIG_CRC_ITU_T=y + CONFIG_LIBCRC32C=y ++ diff -Nru linux-3.2.46/debian/patches/rpi/rpi_156_48b347a6fe008dab487fb54327ed602a88602d7e.patch linux-3.2.46/debian/patches/rpi/rpi_156_48b347a6fe008dab487fb54327ed602a88602d7e.patch --- linux-3.2.46/debian/patches/rpi/rpi_156_48b347a6fe008dab487fb54327ed602a88602d7e.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_156_48b347a6fe008dab487fb54327ed602a88602d7e.patch 2013-07-26 19:33:21.000000000 +0000 @@ -0,0 +1,58 @@ +commit 48b347a6fe008dab487fb54327ed602a88602d7e +Author: Paul Walmsley +Date: Mon Mar 12 10:58:00 2012 -0600 + + mmc: use really long write timeout to deal with crappy cards + + mmc: use really long write timeout to deal with crappy cards + + Several people have noticed that crappy SD cards take much longer to + complete multiple block writes than the 300ms that Linux specifies. + Try to work around this by using a three second write timeout instead. + + This is a generalized version of a patch from Chase Maupin + , whose patch description said: + + * With certain SD cards timeouts like the following have been seen + due to an improper calculation of the dto value: + mmcblk0: error -110 transferring data, sector 4126233, nr 8, + card status 0xc00 + * By removing the dto calculation and setting the timeout value + to the maximum specified by the SD card specification part A2 + section 2.2.15 these timeouts can be avoided. + * This change has been used by beagleboard users as well as the + Texas Instruments SDK without a negative impact. + * There are multiple discussion threads about this but the most + relevant ones are: + * http://talk.maemo.org/showthread.php?p=1000707#post1000707 + * http://www.mail-archive.com/linux-omap@vger.kernel.org/msg42213.html + * Original proposal for this fix was done by Sukumar Ghoral of + Texas Instruments + * Tested using a Texas Instruments AM335x EVM + + Signed-off-by: Paul Walmsley + Tested-by: Tony Lindgren + Signed-off-by: Chris Ball + +Index: linux-3.2.46/drivers/mmc/core/core.c +=================================================================== +--- linux-3.2.46.orig/drivers/mmc/core/core.c 2013-05-30 13:35:16.000000000 +0000 ++++ linux-3.2.46/drivers/mmc/core/core.c 2013-07-26 19:33:20.000000000 +0000 +@@ -514,10 +514,14 @@ + + if (data->flags & MMC_DATA_WRITE) + /* +- * The limit is really 250 ms, but that is +- * insufficient for some crappy cards. ++ * The MMC spec "It is strongly recommended ++ * for hosts to implement more than 500ms ++ * timeout value even if the card indicates ++ * the 250ms maximum busy length." Even the ++ * previous value of 300ms is known to be ++ * insufficient for some cards. + */ +- limit_us = 300000; ++ limit_us = 3000000; + else + limit_us = 100000; + diff -Nru linux-3.2.46/debian/patches/rpi/rpi_157_8390fb8da8954332f546508e6d51906cb93c6e70.patch linux-3.2.46/debian/patches/rpi/rpi_157_8390fb8da8954332f546508e6d51906cb93c6e70.patch --- linux-3.2.46/debian/patches/rpi/rpi_157_8390fb8da8954332f546508e6d51906cb93c6e70.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_157_8390fb8da8954332f546508e6d51906cb93c6e70.patch 2013-07-26 19:33:22.000000000 +0000 @@ -0,0 +1,22 @@ +commit 8390fb8da8954332f546508e6d51906cb93c6e70 +Author: Grigori Goronzy +Date: Mon Jun 4 04:27:48 2012 +0200 + + sdhci-bcm2708: speed up DMA sync + + Experiments show that it doesn't really take that long to sync, so we + can reduce the poll interval slightly. Might improve performance a bit. + +Index: linux-3.2.46/drivers/mmc/host/sdhci-bcm2708.c +=================================================================== +--- linux-3.2.46.orig/drivers/mmc/host/sdhci-bcm2708.c 2013-07-26 19:33:05.000000000 +0000 ++++ linux-3.2.46/drivers/mmc/host/sdhci-bcm2708.c 2013-07-26 19:33:21.000000000 +0000 +@@ -907,7 +907,7 @@ + while (0 != (sdhci_bcm2708_raw_readl(host, SDHCI_PRESENT_STATE) + & state_mask) && --timeout > 0) + { +- udelay(100); ++ udelay(30); + continue; + } + if (timeout <= 0) diff -Nru linux-3.2.46/debian/patches/rpi/rpi_158_6ab6d02f9aaf7b35d941969a1ec8a7aff582ef2f.patch linux-3.2.46/debian/patches/rpi/rpi_158_6ab6d02f9aaf7b35d941969a1ec8a7aff582ef2f.patch --- linux-3.2.46/debian/patches/rpi/rpi_158_6ab6d02f9aaf7b35d941969a1ec8a7aff582ef2f.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_158_6ab6d02f9aaf7b35d941969a1ec8a7aff582ef2f.patch 2013-07-26 19:33:24.000000000 +0000 @@ -0,0 +1,95 @@ +commit 6ab6d02f9aaf7b35d941969a1ec8a7aff582ef2f +Author: Grigori Goronzy +Date: Mon Jun 11 18:52:04 2012 +0200 + + sdhci-bcm2708: remove custom clock handling + + The custom clock handling code is redundant and buggy. The MMC/SDHCI + subsystem does a better job than it, so remove it for good. + +Index: linux-3.2.46/drivers/mmc/host/sdhci-bcm2708.c +=================================================================== +--- linux-3.2.46.orig/drivers/mmc/host/sdhci-bcm2708.c 2013-07-26 19:33:21.000000000 +0000 ++++ linux-3.2.46/drivers/mmc/host/sdhci-bcm2708.c 2013-07-26 19:33:23.000000000 +0000 +@@ -359,68 +359,9 @@ + + static unsigned int sdhci_bcm2708_get_max_clock(struct sdhci_host *host) + { +- return 20000000; // this value is in Hz (20MHz) ++ return BCM2708_EMMC_CLOCK_FREQ; + } + +-static unsigned int sdhci_bcm2708_get_timeout_clock(struct sdhci_host *host) +-{ +- if(host->clock) +- return (host->clock / 1000); // this value is in kHz (100MHz) +- else +- return (sdhci_bcm2708_get_max_clock(host) / 1000); +-} +- +-static void sdhci_bcm2708_set_clock(struct sdhci_host *host, unsigned int clock) +-{ +- int div = 0; +- u16 clk = 0; +- unsigned long timeout; +- +- if (clock == host->clock) +- return; +- +- sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); +- +- if (clock == 0) +- goto out; +- +- if (BCM2708_EMMC_CLOCK_FREQ <= clock) +- div = 1; +- else { +- for (div = 2; div < SDHCI_MAX_DIV_SPEC_300; div += 2) { +- if ((BCM2708_EMMC_CLOCK_FREQ / div) <= clock) +- break; +- } +- } +- +- DBG( "desired SD clock: %d, actual: %d\n", +- clock, BCM2708_EMMC_CLOCK_FREQ / div); +- +- clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT; +- clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN) +- << SDHCI_DIVIDER_HI_SHIFT; +- clk |= SDHCI_CLOCK_INT_EN; +- +- sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); +- +- timeout = 20; +- while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL)) +- & SDHCI_CLOCK_INT_STABLE)) { +- if (timeout == 0) { +- printk(KERN_ERR "%s: Internal clock never " +- "stabilised.\n", mmc_hostname(host->mmc)); +- return; +- } +- timeout--; +- mdelay(1); +- } +- +- clk |= SDHCI_CLOCK_CARD_EN; +- sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); +-out: +- host->clock = clock; +- } +- + /*****************************************************************************\ + * * + * DMA Operation * +@@ -1307,11 +1248,7 @@ + #else + #error The BCM2708 SDHCI driver needs CONFIG_MMC_SDHCI_IO_ACCESSORS to be set + #endif +- //.enable_dma = NULL, +- .set_clock = sdhci_bcm2708_set_clock, + .get_max_clock = sdhci_bcm2708_get_max_clock, +- //.get_min_clock = NULL, +- .get_timeout_clock = sdhci_bcm2708_get_timeout_clock, + + .enable = sdhci_bcm2708_enable, + .disable = sdhci_bcm2708_disable, diff -Nru linux-3.2.46/debian/patches/rpi/rpi_159_8f82daa37d8734496e94a6a5c5ead20254abaa84.patch linux-3.2.46/debian/patches/rpi/rpi_159_8f82daa37d8734496e94a6a5c5ead20254abaa84.patch --- linux-3.2.46/debian/patches/rpi/rpi_159_8f82daa37d8734496e94a6a5c5ead20254abaa84.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_159_8f82daa37d8734496e94a6a5c5ead20254abaa84.patch 2013-07-26 19:33:25.000000000 +0000 @@ -0,0 +1,27 @@ +commit 8f82daa37d8734496e94a6a5c5ead20254abaa84 +Author: Grigori Goronzy +Date: Mon Jun 11 18:53:59 2012 +0200 + + sdhci-bcm2708: add additional quirks + + Some additional quirks are needed for correct operation. + There's no SDHCI capabilities register documented, and it always reads + zero, so add SDHCI_QUIRK_MISSING_CAPS. Apparently + SDHCI_QUIRK_NO_HISPD_BIT is needed for many cards to work correctly in + high-speed mode, so add it as well. + +Index: linux-3.2.46/drivers/mmc/host/sdhci-bcm2708.c +=================================================================== +--- linux-3.2.46.orig/drivers/mmc/host/sdhci-bcm2708.c 2013-07-26 19:33:23.000000000 +0000 ++++ linux-3.2.46/drivers/mmc/host/sdhci-bcm2708.c 2013-07-26 19:33:24.000000000 +0000 +@@ -1311,7 +1311,9 @@ + host->quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION | + SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | + SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | +- SDHCI_QUIRK_NONSTANDARD_CLOCK; ++ SDHCI_QUIRK_MISSING_CAPS | ++ SDHCI_QUIRK_NO_HISPD_BIT; ++ + #ifdef CONFIG_MMC_SDHCI_BCM2708_DMA + host->flags = SDHCI_USE_PLATDMA; + #endif diff -Nru linux-3.2.46/debian/patches/rpi/rpi_160_d7156c5567a90e0fe4d3a503968968d32b7ededd.patch linux-3.2.46/debian/patches/rpi/rpi_160_d7156c5567a90e0fe4d3a503968968d32b7ededd.patch --- linux-3.2.46/debian/patches/rpi/rpi_160_d7156c5567a90e0fe4d3a503968968d32b7ededd.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_160_d7156c5567a90e0fe4d3a503968968d32b7ededd.patch 2013-07-26 19:33:26.000000000 +0000 @@ -0,0 +1,45 @@ +commit d7156c5567a90e0fe4d3a503968968d32b7ededd +Author: Grigori Goronzy +Date: Mon Jun 11 18:57:13 2012 +0200 + + sdhci-bcm2708: add allow_highspeed parameter + + Add a parameter to disable high-speed mode for the few cards that + still might have problems. High-speed mode is enabled by default. + +Index: linux-3.2.46/drivers/mmc/host/sdhci-bcm2708.c +=================================================================== +--- linux-3.2.46.orig/drivers/mmc/host/sdhci-bcm2708.c 2013-07-26 19:33:24.000000000 +0000 ++++ linux-3.2.46/drivers/mmc/host/sdhci-bcm2708.c 2013-07-26 19:33:25.000000000 +0000 +@@ -135,6 +135,8 @@ + return (unsigned long)((hptime() - t) * HPTIME_CLK_NS); + } + ++static bool allow_highspeed = 1; ++ + #if 0 + static void hptime_test(void) + { +@@ -1381,7 +1383,8 @@ + host_priv->dma_chan, host_priv->dma_chan_base, + host_priv->dma_irq); + +- host->mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED; ++ if (allow_highspeed) ++ host->mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED; + #endif + + ret = sdhci_add_host(host); +@@ -1487,8 +1490,12 @@ + module_init(sdhci_drv_init); + module_exit(sdhci_drv_exit); + ++module_param(allow_highspeed, bool, 0444); ++ + MODULE_DESCRIPTION("Secure Digital Host Controller Interface platform driver"); + MODULE_AUTHOR("Broadcom "); + MODULE_LICENSE("GPL v2"); + MODULE_ALIAS("platform:"DRIVER_NAME); + ++MODULE_PARM_DESC(allow_highspeed, "Allow high speed transfers modes"); ++ diff -Nru linux-3.2.46/debian/patches/rpi/rpi_161_70b125d750757b0ba3c2853268b8f8dbac1a5192.patch linux-3.2.46/debian/patches/rpi/rpi_161_70b125d750757b0ba3c2853268b8f8dbac1a5192.patch --- linux-3.2.46/debian/patches/rpi/rpi_161_70b125d750757b0ba3c2853268b8f8dbac1a5192.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_161_70b125d750757b0ba3c2853268b8f8dbac1a5192.patch 2013-07-26 19:33:28.000000000 +0000 @@ -0,0 +1,23 @@ +commit 70b125d750757b0ba3c2853268b8f8dbac1a5192 +Author: Grigori Goronzy +Date: Mon Jun 11 18:58:40 2012 +0200 + + sdhci-bcm2708: assume 50 MHz eMMC clock + + 80 MHz clock isnt't suited well to be dividable to get SD clocks of 25 + MHz (default mode) or 50 MHz (high speed mode). 50 MHz are perfect to + drive the SD interface at ideal frequencies. + +Index: linux-3.2.46/drivers/mmc/host/sdhci-bcm2708.c +=================================================================== +--- linux-3.2.46.orig/drivers/mmc/host/sdhci-bcm2708.c 2013-07-26 19:33:25.000000000 +0000 ++++ linux-3.2.46/drivers/mmc/host/sdhci-bcm2708.c 2013-07-26 19:33:27.000000000 +0000 +@@ -74,7 +74,7 @@ + #define BCM2708_SDHCI_SLEEP_TIMEOUT 1000 /* msecs */ + + /* Mhz clock that the EMMC core is running at. Should match the platform clockman settings */ +-#define BCM2708_EMMC_CLOCK_FREQ 80000000 ++#define BCM2708_EMMC_CLOCK_FREQ 50000000 + + #define POWER_OFF 0 + #define POWER_LAZY_OFF 1 diff -Nru linux-3.2.46/debian/patches/rpi/rpi_162_84042ac41b3492df487acd35de058de1656d2a2a.patch linux-3.2.46/debian/patches/rpi/rpi_162_84042ac41b3492df487acd35de058de1656d2a2a.patch --- linux-3.2.46/debian/patches/rpi/rpi_162_84042ac41b3492df487acd35de058de1656d2a2a.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_162_84042ac41b3492df487acd35de058de1656d2a2a.patch 2013-07-26 19:33:29.000000000 +0000 @@ -0,0 +1,42 @@ +commit 84042ac41b3492df487acd35de058de1656d2a2a +Author: popcornmix +Date: Sat Jun 16 22:31:55 2012 +0100 + + Allow emmc clock to be specified as command line parameter + +Index: linux-3.2.46/drivers/mmc/host/sdhci-bcm2708.c +=================================================================== +--- linux-3.2.46.orig/drivers/mmc/host/sdhci-bcm2708.c 2013-07-26 19:33:27.000000000 +0000 ++++ linux-3.2.46/drivers/mmc/host/sdhci-bcm2708.c 2013-07-26 19:33:28.000000000 +0000 +@@ -136,6 +136,7 @@ + } + + static bool allow_highspeed = 1; ++static bool emmc_clock_freq = BCM2708_EMMC_CLOCK_FREQ; + + #if 0 + static void hptime_test(void) +@@ -361,7 +362,7 @@ + + static unsigned int sdhci_bcm2708_get_max_clock(struct sdhci_host *host) + { +- return BCM2708_EMMC_CLOCK_FREQ; ++ return emmc_clock_freq; + } + + /*****************************************************************************\ +@@ -1491,6 +1492,7 @@ + module_exit(sdhci_drv_exit); + + module_param(allow_highspeed, bool, 0444); ++module_param(emmc_clock_freq, bool, 0444); + + MODULE_DESCRIPTION("Secure Digital Host Controller Interface platform driver"); + MODULE_AUTHOR("Broadcom "); +@@ -1498,4 +1500,6 @@ + MODULE_ALIAS("platform:"DRIVER_NAME); + + MODULE_PARM_DESC(allow_highspeed, "Allow high speed transfers modes"); ++MODULE_PARM_DESC(emmc_clock_freq, "Specify the speed of emmc clock"); ++ + diff -Nru linux-3.2.46/debian/patches/rpi/rpi_163_d7afba1425d968e0675434215f04b3fac0213dec.patch linux-3.2.46/debian/patches/rpi/rpi_163_d7afba1425d968e0675434215f04b3fac0213dec.patch --- linux-3.2.46/debian/patches/rpi/rpi_163_d7afba1425d968e0675434215f04b3fac0213dec.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_163_d7afba1425d968e0675434215f04b3fac0213dec.patch 2013-07-26 19:33:30.000000000 +0000 @@ -0,0 +1,27 @@ +commit d7afba1425d968e0675434215f04b3fac0213dec +Author: popcornmix +Date: Sat Jun 16 22:35:38 2012 +0100 + + sdhci-bcm2708: raise DMA sync timeout + + Commit d64b84c by accident reduced the maximum overall DMA sync + timeout. The maximum overall timeout was reduced from 100ms to 30ms, + which isn't enough for many cards. Increase it to 150ms, just to be + extra safe. According to commit 872a8ff in the MMC subsystem, some + cards require crazy long timeouts (3s), but as we're busy-waiting, + and shouldn't delay for such a long time, let's hope 150ms will be + enough for most cards. + +Index: linux-3.2.46/drivers/mmc/host/sdhci-bcm2708.c +=================================================================== +--- linux-3.2.46.orig/drivers/mmc/host/sdhci-bcm2708.c 2013-07-26 19:33:28.000000000 +0000 ++++ linux-3.2.46/drivers/mmc/host/sdhci-bcm2708.c 2013-07-26 19:33:29.000000000 +0000 +@@ -840,7 +840,7 @@ + We get CRC and DEND errors unless we wait for + the SD controller to finish reading/writing to the card. */ + u32 state_mask; +- int timeout=1000; ++ int timeout=5000; + + DBG("PDMA over - sync card\n"); + if (data->flags & MMC_DATA_READ) diff -Nru linux-3.2.46/debian/patches/rpi/rpi_164_d34d49ef34fee0adae557b960bee4737220588be.patch linux-3.2.46/debian/patches/rpi/rpi_164_d34d49ef34fee0adae557b960bee4737220588be.patch --- linux-3.2.46/debian/patches/rpi/rpi_164_d34d49ef34fee0adae557b960bee4737220588be.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_164_d34d49ef34fee0adae557b960bee4737220588be.patch 2013-07-26 19:33:32.000000000 +0000 @@ -0,0 +1,19 @@ +commit d34d49ef34fee0adae557b960bee4737220588be +Author: popcornmix +Date: Sat Jun 16 23:26:28 2012 +0100 + + Fix bool/int error + +Index: linux-3.2.46/drivers/mmc/host/sdhci-bcm2708.c +=================================================================== +--- linux-3.2.46.orig/drivers/mmc/host/sdhci-bcm2708.c 2013-07-26 19:33:29.000000000 +0000 ++++ linux-3.2.46/drivers/mmc/host/sdhci-bcm2708.c 2013-07-26 19:33:31.000000000 +0000 +@@ -1492,7 +1492,7 @@ + module_exit(sdhci_drv_exit); + + module_param(allow_highspeed, bool, 0444); +-module_param(emmc_clock_freq, bool, 0444); ++module_param(emmc_clock_freq, int, 0444); + + MODULE_DESCRIPTION("Secure Digital Host Controller Interface platform driver"); + MODULE_AUTHOR("Broadcom "); diff -Nru linux-3.2.46/debian/patches/rpi/rpi_165_63aa16776175617687923466aae543b2528d4600.patch linux-3.2.46/debian/patches/rpi/rpi_165_63aa16776175617687923466aae543b2528d4600.patch --- linux-3.2.46/debian/patches/rpi/rpi_165_63aa16776175617687923466aae543b2528d4600.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_165_63aa16776175617687923466aae543b2528d4600.patch 2013-07-26 19:33:33.000000000 +0000 @@ -0,0 +1,19 @@ +commit 63aa16776175617687923466aae543b2528d4600 +Author: popcornmix +Date: Sat Jun 16 23:46:08 2012 +0100 + + Fix bool/int error, part 2 + +Index: linux-3.2.46/drivers/mmc/host/sdhci-bcm2708.c +=================================================================== +--- linux-3.2.46.orig/drivers/mmc/host/sdhci-bcm2708.c 2013-07-26 19:33:31.000000000 +0000 ++++ linux-3.2.46/drivers/mmc/host/sdhci-bcm2708.c 2013-07-26 19:33:32.000000000 +0000 +@@ -136,7 +136,7 @@ + } + + static bool allow_highspeed = 1; +-static bool emmc_clock_freq = BCM2708_EMMC_CLOCK_FREQ; ++static int emmc_clock_freq = BCM2708_EMMC_CLOCK_FREQ; + + #if 0 + static void hptime_test(void) diff -Nru linux-3.2.46/debian/patches/rpi/rpi_166_c5592fc5ae6c0b26e327809d0f572093284c2956.patch linux-3.2.46/debian/patches/rpi/rpi_166_c5592fc5ae6c0b26e327809d0f572093284c2956.patch --- linux-3.2.46/debian/patches/rpi/rpi_166_c5592fc5ae6c0b26e327809d0f572093284c2956.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_166_c5592fc5ae6c0b26e327809d0f572093284c2956.patch 2013-07-26 19:33:34.000000000 +0000 @@ -0,0 +1,87 @@ +commit c5592fc5ae6c0b26e327809d0f572093284c2956 +Author: popcornmix +Date: Sat Jun 16 23:49:52 2012 +0100 + + More config options for iptables, device mapper, PPP_MPPE + +Index: linux-3.2.46/arch/arm/configs/bcmrpi_defconfig +=================================================================== +--- linux-3.2.46.orig/arch/arm/configs/bcmrpi_defconfig 2013-07-26 19:33:18.000000000 +0000 ++++ linux-3.2.46/arch/arm/configs/bcmrpi_defconfig 2013-07-26 19:33:33.000000000 +0000 +@@ -160,6 +160,10 @@ + CONFIG_IP_NF_TARGET_REJECT=m + CONFIG_IP_NF_TARGET_LOG=m + CONFIG_IP_NF_TARGET_ULOG=m ++CONFIG_NF_NAT=m ++CONFIG_IP_NF_TARGET_MASQUERADE=m ++CONFIG_IP_NF_TARGET_NETMAP=m ++CONFIG_IP_NF_TARGET_REDIRECT=m + CONFIG_IP_NF_MANGLE=m + CONFIG_IP_NF_TARGET_ECN=m + CONFIG_IP_NF_TARGET_TTL=m +@@ -183,6 +187,29 @@ + CONFIG_IP6_NF_TARGET_REJECT=m + CONFIG_IP6_NF_MANGLE=m + CONFIG_IP6_NF_RAW=m ++CONFIG_BRIDGE_NF_EBTABLES=m ++CONFIG_BRIDGE_EBT_BROUTE=m ++CONFIG_BRIDGE_EBT_T_FILTER=m ++CONFIG_BRIDGE_EBT_T_NAT=m ++CONFIG_BRIDGE_EBT_802_3=m ++CONFIG_BRIDGE_EBT_AMONG=m ++CONFIG_BRIDGE_EBT_ARP=m ++CONFIG_BRIDGE_EBT_IP=m ++CONFIG_BRIDGE_EBT_IP6=m ++CONFIG_BRIDGE_EBT_LIMIT=m ++CONFIG_BRIDGE_EBT_MARK=m ++CONFIG_BRIDGE_EBT_PKTTYPE=m ++CONFIG_BRIDGE_EBT_STP=m ++CONFIG_BRIDGE_EBT_VLAN=m ++CONFIG_BRIDGE_EBT_ARPREPLY=m ++CONFIG_BRIDGE_EBT_DNAT=m ++CONFIG_BRIDGE_EBT_MARK_T=m ++CONFIG_BRIDGE_EBT_REDIRECT=m ++CONFIG_BRIDGE_EBT_SNAT=m ++CONFIG_BRIDGE_EBT_LOG=m ++CONFIG_BRIDGE_EBT_ULOG=m ++CONFIG_BRIDGE_EBT_NFLOG=m ++CONFIG_BRIDGE=m + CONFIG_NET_PKTGEN=m + CONFIG_IRDA=m + CONFIG_IRLAN=m +@@ -224,7 +251,6 @@ + CONFIG_NFC=m + CONFIG_NFC_PN533=m + CONFIG_DEVTMPFS=y +-CONFIG_CONNECTOR=m + CONFIG_BLK_DEV_LOOP=y + CONFIG_BLK_DEV_CRYPTOLOOP=m + CONFIG_BLK_DEV_NBD=m +@@ -238,6 +264,14 @@ + CONFIG_SCSI_MULTI_LUN=y + # CONFIG_SCSI_LOWLEVEL is not set + CONFIG_MD=y ++CONFIG_BLK_DEV_DM=m ++CONFIG_DM_CRYPT=m ++CONFIG_DM_SNAPSHOT=m ++CONFIG_DM_MIRROR=m ++CONFIG_DM_RAID=m ++CONFIG_DM_LOG_USERSPACE=m ++CONFIG_DM_ZERO=m ++CONFIG_DM_DELAY=m + CONFIG_NETDEVICES=y + CONFIG_TUN=m + CONFIG_PHYLIB=m +@@ -309,6 +343,7 @@ + CONFIG_PPP_SYNC_TTY=m + CONFIG_PPP_DEFLATE=m + CONFIG_PPP_BSDCOMP=m ++CONFIG_PPP_MPPE=m + CONFIG_PPPOE=m + CONFIG_SLIP=m + CONFIG_SLIP_COMPRESSED=y +@@ -720,4 +755,3 @@ + # CONFIG_CRYPTO_HW is not set + CONFIG_CRC_ITU_T=y + CONFIG_LIBCRC32C=y +- diff -Nru linux-3.2.46/debian/patches/rpi/rpi_167_fe2e727883a371f21e02454ad6b58eed407aa7b9.patch linux-3.2.46/debian/patches/rpi/rpi_167_fe2e727883a371f21e02454ad6b58eed407aa7b9.patch --- linux-3.2.46/debian/patches/rpi/rpi_167_fe2e727883a371f21e02454ad6b58eed407aa7b9.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_167_fe2e727883a371f21e02454ad6b58eed407aa7b9.patch 2013-07-26 19:33:35.000000000 +0000 @@ -0,0 +1,20 @@ +commit fe2e727883a371f21e02454ad6b58eed407aa7b9 +Author: popcornmix +Date: Sun Jun 17 00:14:54 2012 +0100 + + Explicitly set usb host channels to 8, as in the spec + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_core_if.h +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/dwc_otg_core_if.h 2013-07-26 19:31:23.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_core_if.h 2013-07-26 19:33:34.000000000 +0000 +@@ -267,7 +267,8 @@ + extern int dwc_otg_set_param_host_channels(dwc_otg_core_if_t * core_if, + int32_t val); + extern int32_t dwc_otg_get_param_host_channels(dwc_otg_core_if_t * core_if); +-#define dwc_param_host_channels_default 12 ++//#define dwc_param_host_channels_default 12 ++#define dwc_param_host_channels_default 8// Broadcom BCM2708 + + /** The number of endpoints in addition to EP0 available for device + * mode operations. diff -Nru linux-3.2.46/debian/patches/rpi/rpi_168_02b4b932b8119d0fb68d83873967497e050fb960.patch linux-3.2.46/debian/patches/rpi/rpi_168_02b4b932b8119d0fb68d83873967497e050fb960.patch --- linux-3.2.46/debian/patches/rpi/rpi_168_02b4b932b8119d0fb68d83873967497e050fb960.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_168_02b4b932b8119d0fb68d83873967497e050fb960.patch 2013-07-26 19:33:37.000000000 +0000 @@ -0,0 +1,27 @@ +commit 02b4b932b8119d0fb68d83873967497e050fb960 +Author: popcornmix +Date: Sun Jun 17 15:52:33 2012 +0100 + + Add hfs/hfsplus modules + +Index: linux-3.2.46/arch/arm/configs/bcmrpi_defconfig +=================================================================== +--- linux-3.2.46.orig/arch/arm/configs/bcmrpi_defconfig 2013-07-26 19:33:33.000000000 +0000 ++++ linux-3.2.46/arch/arm/configs/bcmrpi_defconfig 2013-07-26 19:33:36.000000000 +0000 +@@ -660,6 +660,8 @@ + CONFIG_TMPFS=y + CONFIG_TMPFS_POSIX_ACL=y + CONFIG_CONFIGFS_FS=y ++CONFIG_HFS_FS=m ++CONFIG_HFSPLUS_FS=m + CONFIG_SQUASHFS=m + CONFIG_SQUASHFS_XATTR=y + CONFIG_SQUASHFS_LZO=y +@@ -717,7 +719,6 @@ + CONFIG_NLS_ISO8859_15=m + CONFIG_NLS_KOI8_R=m + CONFIG_NLS_KOI8_U=m +-CONFIG_NLS_UTF8=m + CONFIG_PRINTK_TIME=y + CONFIG_DETECT_HUNG_TASK=y + CONFIG_TIMER_STATS=y diff -Nru linux-3.2.46/debian/patches/rpi/rpi_169_6dac22fdd8f0a510aa1c1a007eac118d99d86a3f.patch linux-3.2.46/debian/patches/rpi/rpi_169_6dac22fdd8f0a510aa1c1a007eac118d99d86a3f.patch --- linux-3.2.46/debian/patches/rpi/rpi_169_6dac22fdd8f0a510aa1c1a007eac118d99d86a3f.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_169_6dac22fdd8f0a510aa1c1a007eac118d99d86a3f.patch 2013-07-26 19:33:38.000000000 +0000 @@ -0,0 +1,70 @@ +commit 6dac22fdd8f0a510aa1c1a007eac118d99d86a3f +Author: popcornmix +Date: Thu Jun 21 01:31:08 2012 +0100 + + Remove silence method, and use atomic flags for kmalloc + +Index: linux-3.2.46/sound/arm/bcm2835-pcm.c +=================================================================== +--- linux-3.2.46.orig/sound/arm/bcm2835-pcm.c 2013-07-26 19:32:38.000000000 +0000 ++++ linux-3.2.46/sound/arm/bcm2835-pcm.c 2013-07-26 19:33:37.000000000 +0000 +@@ -345,29 +345,6 @@ + return ret; + } + +-static int snd_bcm2835_pcm_silence(struct snd_pcm_substream *substream, +- int channel, snd_pcm_uframes_t post, +- snd_pcm_uframes_t count) +-{ +- int ret; +- struct snd_pcm_runtime *runtime = substream->runtime; +- bcm2835_alsa_stream_t *alsa_stream = runtime->private_data; +- +- audio_info(" .. IN\n"); +- audio_debug("silence....... (%d) hwptr=%d appl=%d pos=%d\n", +- frames_to_bytes(runtime, count), frames_to_bytes(runtime, +- runtime-> +- status-> +- hw_ptr), +- frames_to_bytes(runtime, runtime->control->appl_ptr), +- alsa_stream->pos); +- ret = +- bcm2835_audio_write(alsa_stream, frames_to_bytes(runtime, count), +- NULL); +- audio_info(" .. OUT\n"); +- return ret; +-} +- + static int snd_bcm2835_pcm_lib_ioctl(struct snd_pcm_substream *substream, + unsigned int cmd, void *arg) + { +@@ -388,7 +365,6 @@ + .trigger = snd_bcm2835_pcm_trigger, + .pointer = snd_bcm2835_pcm_pointer, + .copy = snd_bcm2835_pcm_copy, +- .silence = snd_bcm2835_pcm_silence, + }; + + /* create a pcm device */ +Index: linux-3.2.46/sound/arm/bcm2835-vchiq.c +=================================================================== +--- linux-3.2.46.orig/sound/arm/bcm2835-vchiq.c 2013-07-26 19:32:44.000000000 +0000 ++++ linux-3.2.46/sound/arm/bcm2835-vchiq.c 2013-07-26 19:33:37.000000000 +0000 +@@ -102,7 +102,7 @@ + int ret = -1; + LOG_DBG(" .. IN\n"); + if (alsa_stream->my_wq) { +- my_work_t *work = kmalloc(sizeof(my_work_t), GFP_KERNEL); ++ my_work_t *work = kmalloc(sizeof(my_work_t), GFP_ATOMIC); + /* Queue some work (item 1) */ + if (work) { + INIT_WORK((struct work_struct *)work, my_wq_function); +@@ -123,7 +123,7 @@ + int ret = -1; + LOG_DBG(" .. IN\n"); + if (alsa_stream->my_wq) { +- my_work_t *work = kmalloc(sizeof(my_work_t), GFP_KERNEL); ++ my_work_t *work = kmalloc(sizeof(my_work_t), GFP_ATOMIC); + /* Queue some work (item 1) */ + if (work) { + INIT_WORK((struct work_struct *)work, my_wq_function); diff -Nru linux-3.2.46/debian/patches/rpi/rpi_170_2415c98cf5c0ab0521621e6759432e04f2891619.patch linux-3.2.46/debian/patches/rpi/rpi_170_2415c98cf5c0ab0521621e6759432e04f2891619.patch --- linux-3.2.46/debian/patches/rpi/rpi_170_2415c98cf5c0ab0521621e6759432e04f2891619.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_170_2415c98cf5c0ab0521621e6759432e04f2891619.patch 2013-07-26 19:33:39.000000000 +0000 @@ -0,0 +1,20 @@ +commit 2415c98cf5c0ab0521621e6759432e04f2891619 +Author: popcornmix +Date: Fri Jun 22 12:55:39 2012 +0100 + + Fix unintended line swap that cause cause memory leak in USB driver + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c 2013-07-26 19:33:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c 2013-07-26 19:33:38.000000000 +0000 +@@ -764,8 +764,8 @@ + if(urb->hcpriv != NULL) { + dwc_otg_hcd_urb_dequeue(dwc_otg_hcd, (dwc_otg_hcd_urb_t *)urb->hcpriv); + +- urb->hcpriv = NULL; + dwc_free(urb->hcpriv); ++ urb->hcpriv = NULL; + } + + /* Higher layer software sets URB status. */ diff -Nru linux-3.2.46/debian/patches/rpi/rpi_171_f1da243c55dd220600f56899b770c25b77d572a6.patch linux-3.2.46/debian/patches/rpi/rpi_171_f1da243c55dd220600f56899b770c25b77d572a6.patch --- linux-3.2.46/debian/patches/rpi/rpi_171_f1da243c55dd220600f56899b770c25b77d572a6.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_171_f1da243c55dd220600f56899b770c25b77d572a6.patch 2013-07-26 19:33:41.000000000 +0000 @@ -0,0 +1,43 @@ +commit f1da243c55dd220600f56899b770c25b77d572a6 +Author: popcornmix +Date: Fri Jun 22 12:57:42 2012 +0100 + + Use ndelay rather than udelay. Thanks lb + +Index: linux-3.2.46/drivers/mmc/host/sdhci-bcm2708.c +=================================================================== +--- linux-3.2.46.orig/drivers/mmc/host/sdhci-bcm2708.c 2013-07-26 19:33:32.000000000 +0000 ++++ linux-3.2.46/drivers/mmc/host/sdhci-bcm2708.c 2013-07-26 19:33:40.000000000 +0000 +@@ -255,14 +255,14 @@ + if (now == last_write_hpt || now == last_write_hpt+1) { + /* we can't guarantee any significant time has + * passed - we'll have to wait anyway ! */ +- udelay((ns_2clk+1000-1)/1000); ++ ndelay(ns_2clk); + } else + { + /* we must have waited at least this many ns: */ + unsigned int ns_wait = HPTIME_CLK_NS * + (last_write_hpt - now - 1); + if (ns_wait < ns_2clk) +- udelay((ns_2clk-ns_wait+500)/1000); ++ ndelay(ns_2clk - ns_wait); + } + last_write_hpt = now; + } +@@ -278,13 +278,13 @@ + ier &= ~SDHCI_INT_DATA_TIMEOUT; + writel(ier, host->ioaddr + SDHCI_SIGNAL_ENABLE); + timeout_disabled = true; +- udelay((ns_2clk+1000-1)/1000); ++ ndelay(ns_2clk); + } else if (timeout_disabled) { + ier = readl(host->ioaddr + SDHCI_SIGNAL_ENABLE); + ier |= SDHCI_INT_DATA_TIMEOUT; + writel(ier, host->ioaddr + SDHCI_SIGNAL_ENABLE); + timeout_disabled = false; +- udelay((ns_2clk+1000-1)/1000); ++ ndelay(ns_2clk); + } + #endif + writel(val, host->ioaddr + reg); diff -Nru linux-3.2.46/debian/patches/rpi/rpi_172_8f32eb69851e137c04e225cc3fab42a89566d7f0.patch linux-3.2.46/debian/patches/rpi/rpi_172_8f32eb69851e137c04e225cc3fab42a89566d7f0.patch --- linux-3.2.46/debian/patches/rpi/rpi_172_8f32eb69851e137c04e225cc3fab42a89566d7f0.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_172_8f32eb69851e137c04e225cc3fab42a89566d7f0.patch 2013-07-26 19:33:42.000000000 +0000 @@ -0,0 +1,46 @@ +commit 8f32eb69851e137c04e225cc3fab42a89566d7f0 +Author: popcornmix +Date: Fri Jun 22 18:48:00 2012 +0100 + + Add NFSD. Add some dvb options. Add CONFIG_LOCALVERSION for cutdown + +Index: linux-3.2.46/arch/arm/configs/bcmrpi_cutdown_defconfig +=================================================================== +--- linux-3.2.46.orig/arch/arm/configs/bcmrpi_cutdown_defconfig 2013-07-26 19:33:18.000000000 +0000 ++++ linux-3.2.46/arch/arm/configs/bcmrpi_cutdown_defconfig 2013-07-26 19:33:41.000000000 +0000 +@@ -1,4 +1,5 @@ + CONFIG_EXPERIMENTAL=y ++CONFIG_LOCALVERSION="-cutdown" + # CONFIG_LOCALVERSION_AUTO is not set + CONFIG_SYSVIPC=y + CONFIG_POSIX_MQUEUE=y +Index: linux-3.2.46/arch/arm/configs/bcmrpi_defconfig +=================================================================== +--- linux-3.2.46.orig/arch/arm/configs/bcmrpi_defconfig 2013-07-26 19:33:36.000000000 +0000 ++++ linux-3.2.46/arch/arm/configs/bcmrpi_defconfig 2013-07-26 19:33:41.000000000 +0000 +@@ -386,6 +386,8 @@ + # CONFIG_MFD_SUPPORT is not set + CONFIG_MEDIA_SUPPORT=m + CONFIG_VIDEO_DEV=m ++CONFIG_DVB_CORE=m ++CONFIG_MEDIA_ATTACH=y + CONFIG_USB_VIDEO_CLASS=m + CONFIG_USB_M5602=m + CONFIG_USB_STV06XX=m +@@ -440,6 +442,8 @@ + CONFIG_RADIO_SI470X=y + CONFIG_USB_SI470X=m + CONFIG_USB_MR800=m ++CONFIG_SMS_SIANO_MDTV=m ++CONFIG_SMS_USB_DRV=m + CONFIG_FB=y + CONFIG_FB_BCM2708=y + CONFIG_FRAMEBUFFER_CONSOLE=y +@@ -672,6 +676,7 @@ + CONFIG_NFS_V4=y + CONFIG_ROOT_NFS=y + CONFIG_NFS_FSCACHE=y ++CONFIG_NFSD=m + CONFIG_CIFS=m + CONFIG_CIFS_WEAK_PW_HASH=y + CONFIG_CIFS_XATTR=y diff -Nru linux-3.2.46/debian/patches/rpi/rpi_173_8544300faae04c4fb4e3e1acc5ff9a9733f1acce.patch linux-3.2.46/debian/patches/rpi/rpi_173_8544300faae04c4fb4e3e1acc5ff9a9733f1acce.patch --- linux-3.2.46/debian/patches/rpi/rpi_173_8544300faae04c4fb4e3e1acc5ff9a9733f1acce.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_173_8544300faae04c4fb4e3e1acc5ff9a9733f1acce.patch 2013-07-26 19:33:43.000000000 +0000 @@ -0,0 +1,91 @@ +commit 8544300faae04c4fb4e3e1acc5ff9a9733f1acce +Author: popcornmix +Date: Tue Jun 26 15:54:11 2012 +0100 + + Fixed issue with some keyboards giving too much data + resulting in overrun of the input buffer and memory + corruption causing an OOPS. We should be checking for the + fact that we might get more data than we want. Thanks Naren. + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_hcd_ddma.c +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/dwc_otg_hcd_ddma.c 2013-07-26 19:31:23.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_hcd_ddma.c 2013-07-26 19:33:42.000000000 +0000 +@@ -886,7 +886,7 @@ + if (hc->ep_type == DWC_OTG_EP_TYPE_CONTROL) { + if (qtd->control_phase == DWC_OTG_CONTROL_DATA) { + urb->actual_length += n_bytes - remain; +- if (remain || urb->actual_length == urb->length) { ++ if (remain || urb->actual_length >= urb->length) { + /* + * For Control Data stage do not set urb->status=0 to prevent + * URB callback. Set it when Status phase done. See below. +@@ -905,7 +905,7 @@ + else { + /* BULK and INTR */ + urb->actual_length += n_bytes - remain; +- if (remain || urb->actual_length == urb->length) { ++ if (remain || urb->actual_length >= urb->length) { + urb->status = 0; + *xfer_done = 1; + } +Index: linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c 2013-07-26 19:31:23.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c 2013-07-26 19:33:42.000000000 +0000 +@@ -567,7 +567,7 @@ + (urb->flags & URB_SEND_ZERO_PACKET) && (urb->actual_length == urb->length) && + !(urb->length % hc->max_packet)) { + xfer_done = 0; +- } else if (short_read || urb->actual_length == urb->length) { ++ } else if (short_read || urb->actual_length >= urb->length) { + xfer_done = 1; + urb->status = 0; + } +@@ -1876,10 +1876,10 @@ + } else if (hcint.b.xacterr && !hcd->core_if->dma_desc_enable) { + if (out_nak_enh) { + if (hcint.b.nyet || hcint.b.nak || hcint.b.ack) { +- DWC_DEBUG("XactErr with NYET/NAK/ACK\n"); ++ DWC_DEBUGPL(DBG_HCD, "XactErr with NYET/NAK/ACK\n"); + qtd->error_count = 0; + } else { +- DWC_DEBUG("XactErr without NYET/NAK/ACK\n"); ++ DWC_DEBUGPL(DBG_HCD, "XactErr without NYET/NAK/ACK\n"); + } + } + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c 2013-07-26 19:33:38.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c 2013-07-26 19:33:42.000000000 +0000 +@@ -190,6 +190,7 @@ + uint32_t * port_addr) + { + struct urb *urb = (struct urb *)urb_handle; ++ struct usb_bus *bus; + #if 1 //GRAYG - temporary + if (NULL == urb_handle) + DWC_ERROR("**** %s - NULL URB handle\n", __func__);//GRAYG +@@ -206,12 +207,18 @@ + *hub_addr = 0; //GRAYG + // we probably shouldn't have a transaction translator if + // there's no associated hub? +- } else +- *hub_addr = urb->dev->tt->hub->devnum; ++ } else { ++ bus = hcd_to_bus(dwc_otg_hcd_to_hcd(hcd)); ++ if (urb->dev->tt->hub == bus->root_hub) ++ *hub_addr = 0; ++ else ++ *hub_addr = urb->dev->tt->hub->devnum; ++ } ++ *port_addr = urb->dev->tt->multi ? urb->dev->ttport : 1; + } else { + *hub_addr = 0; ++ *port_addr = urb->dev->ttport; + } +- *port_addr = urb->dev->ttport; + return 0; + } + diff -Nru linux-3.2.46/debian/patches/rpi/rpi_174_973ebad9feb981465994f88448d2fb25d9bee941.patch linux-3.2.46/debian/patches/rpi/rpi_174_973ebad9feb981465994f88448d2fb25d9bee941.patch --- linux-3.2.46/debian/patches/rpi/rpi_174_973ebad9feb981465994f88448d2fb25d9bee941.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_174_973ebad9feb981465994f88448d2fb25d9bee941.patch 2013-07-26 19:33:45.000000000 +0000 @@ -0,0 +1,19 @@ +commit 973ebad9feb981465994f88448d2fb25d9bee941 +Author: popcornmix +Date: Sat Jun 30 11:40:33 2012 +0100 + + Add 802.1q vlan module + +Index: linux-3.2.46/arch/arm/configs/bcmrpi_defconfig +=================================================================== +--- linux-3.2.46.orig/arch/arm/configs/bcmrpi_defconfig 2013-07-26 19:33:41.000000000 +0000 ++++ linux-3.2.46/arch/arm/configs/bcmrpi_defconfig 2013-07-26 19:33:44.000000000 +0000 +@@ -210,6 +210,8 @@ + CONFIG_BRIDGE_EBT_ULOG=m + CONFIG_BRIDGE_EBT_NFLOG=m + CONFIG_BRIDGE=m ++CONFIG_VLAN_8021Q=m ++CONFIG_VLAN_8021Q_GVRP=y + CONFIG_NET_PKTGEN=m + CONFIG_IRDA=m + CONFIG_IRLAN=m diff -Nru linux-3.2.46/debian/patches/rpi/rpi_175_2f3523e91e1cdbfbb5871f0943333620b139e032.patch linux-3.2.46/debian/patches/rpi/rpi_175_2f3523e91e1cdbfbb5871f0943333620b139e032.patch --- linux-3.2.46/debian/patches/rpi/rpi_175_2f3523e91e1cdbfbb5871f0943333620b139e032.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_175_2f3523e91e1cdbfbb5871f0943333620b139e032.patch 2013-07-26 19:33:46.000000000 +0000 @@ -0,0 +1,467 @@ +commit 2f3523e91e1cdbfbb5871f0943333620b139e032 +Author: popcornmix +Date: Sat Jun 30 11:47:45 2012 +0100 + + Add interrupt support to gpio driver. Thanks Mrkva + +Index: linux-3.2.46/arch/arm/mach-bcm2708/bcm2708_gpio.c +=================================================================== +--- linux-3.2.46.orig/arch/arm/mach-bcm2708/bcm2708_gpio.c 2013-07-26 19:31:51.000000000 +0000 ++++ linux-3.2.46/arch/arm/mach-bcm2708/bcm2708_gpio.c 2013-07-26 19:33:45.000000000 +0000 +@@ -14,6 +14,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -22,7 +23,7 @@ + + #define BCM_GPIO_DRIVER_NAME "bcm2708_gpio" + #define DRIVER_NAME BCM_GPIO_DRIVER_NAME +-#define BCM_GPIO_USE_IRQ 0 ++#define BCM_GPIO_USE_IRQ 1 + + #define GPIOFSEL(x) (0x00+(x)*4) + #define GPIOSET(x) (0x1c+(x)*4) +@@ -38,40 +39,35 @@ + #define GPIOUD(x) (0x94+(x)*4) + #define GPIOUDCLK(x) (0x98+(x)*4) + +-enum { GPIO_FSEL_INPUT, GPIO_FSEL_OUTPUT, +- GPIO_FSEL_ALT5, GPIO_FSEL_ALT_4, +- GPIO_FSEL_ALT0, GPIO_FSEL_ALT1, +- GPIO_FSEL_ALT2, GPIO_FSEL_ALT3, }; ++enum { GPIO_FSEL_INPUT, GPIO_FSEL_OUTPUT, ++ GPIO_FSEL_ALT5, GPIO_FSEL_ALT_4, ++ GPIO_FSEL_ALT0, GPIO_FSEL_ALT1, ++ GPIO_FSEL_ALT2, GPIO_FSEL_ALT3, ++}; + + /* Each of the two spinlocks protects a different set of hardware + * regiters and data structurs. This decouples the code of the IRQ from + * the GPIO code. This also makes the case of a GPIO routine call from + * the IRQ code simpler. + */ +-static DEFINE_SPINLOCK(lock); /* GPIO registers */ +-static DEFINE_SPINLOCK(irq_lock); /* IRQ registers */ +- ++static DEFINE_SPINLOCK(lock); /* GPIO registers */ + + struct bcm2708_gpio { +- /* We use a list of bcm2708_gpio structs for each trigger IRQ in the main +- * interrupts controller of the system. We need this to support systems +- * in which more that one bcm2708s are connected to the same IRQ. The ISR +- * interates through this list to find the source of the interrupt. +- */ +- struct list_head list; +- +- void __iomem *base; +- unsigned irq_base; +- struct gpio_chip gc; ++ struct list_head list; ++ void __iomem *base; ++ struct gpio_chip gc; ++ unsigned long rising; ++ unsigned long falling; + }; + +-static int bcm2708_set_function(struct gpio_chip *gc, unsigned offset, int function) ++static int bcm2708_set_function(struct gpio_chip *gc, unsigned offset, ++ int function) + { + struct bcm2708_gpio *gpio = container_of(gc, struct bcm2708_gpio, gc); + unsigned long flags; + unsigned gpiodir; +- unsigned gpio_bank = offset/10; +- unsigned gpio_field_offset = (offset - 10*gpio_bank) * 3; ++ unsigned gpio_bank = offset / 10; ++ unsigned gpio_field_offset = (offset - 10 * gpio_bank) * 3; + + //printk(KERN_ERR DRIVER_NAME ": bcm2708_gpio_set_function %p (%d,%d)\n", gc, offset, function); + if (offset >= ARCH_NR_GPIOS) +@@ -81,7 +77,7 @@ + + gpiodir = readl(gpio->base + GPIOFSEL(gpio_bank)); + gpiodir &= ~(7 << gpio_field_offset); +- gpiodir |= function << gpio_field_offset; ++ gpiodir |= function << gpio_field_offset; + writel(gpiodir, gpio->base + GPIOFSEL(gpio_bank)); + spin_unlock_irqrestore(&lock, flags); + gpiodir = readl(gpio->base + GPIOFSEL(gpio_bank)); +@@ -89,157 +85,177 @@ + return 0; + } + +- + static int bcm2708_gpio_dir_in(struct gpio_chip *gc, unsigned offset) + { + return bcm2708_set_function(gc, offset, GPIO_FSEL_INPUT); + } + + static void bcm2708_gpio_set(struct gpio_chip *gc, unsigned offset, int value); +-static int bcm2708_gpio_dir_out(struct gpio_chip *gc, unsigned offset, int value) ++static int bcm2708_gpio_dir_out(struct gpio_chip *gc, unsigned offset, ++ int value) + { + int ret; +- ret = bcm2708_set_function(gc, offset, GPIO_FSEL_OUTPUT); +- if (ret >= 0) +- bcm2708_gpio_set(gc, offset, value); ++ ret = bcm2708_set_function(gc, offset, GPIO_FSEL_OUTPUT); ++ if (ret >= 0) ++ bcm2708_gpio_set(gc, offset, value); + return ret; + } + + static int bcm2708_gpio_get(struct gpio_chip *gc, unsigned offset) + { + struct bcm2708_gpio *gpio = container_of(gc, struct bcm2708_gpio, gc); +- unsigned gpio_bank = offset/32; +- unsigned gpio_field_offset = (offset - 32*gpio_bank); +- unsigned lev; ++ unsigned gpio_bank = offset / 32; ++ unsigned gpio_field_offset = (offset - 32 * gpio_bank); ++ unsigned lev; + + if (offset >= ARCH_NR_GPIOS) + return 0; +- lev = readl(gpio->base + GPIOLEV(gpio_bank)); ++ lev = readl(gpio->base + GPIOLEV(gpio_bank)); + //printk(KERN_ERR DRIVER_NAME ": bcm2708_gpio_get %p (%d)=%d\n", gc, offset, 0x1 & (lev>>gpio_field_offset)); +- return 0x1 & (lev>>gpio_field_offset); ++ return 0x1 & (lev >> gpio_field_offset); + } + + static void bcm2708_gpio_set(struct gpio_chip *gc, unsigned offset, int value) + { + struct bcm2708_gpio *gpio = container_of(gc, struct bcm2708_gpio, gc); +- unsigned gpio_bank = offset/32; +- unsigned gpio_field_offset = (offset - 32*gpio_bank); ++ unsigned gpio_bank = offset / 32; ++ unsigned gpio_field_offset = (offset - 32 * gpio_bank); + //printk(KERN_ERR DRIVER_NAME ": bcm2708_gpio_set %p (%d=%d)\n", gc, offset, value); + if (offset >= ARCH_NR_GPIOS) + return; + if (value) +- writel(1<base + GPIOSET(gpio_bank)); ++ writel(1 << gpio_field_offset, gpio->base + GPIOSET(gpio_bank)); + else +- writel(1<base + GPIOCLR(gpio_bank)); ++ writel(1 << gpio_field_offset, gpio->base + GPIOCLR(gpio_bank)); + } + +-/* ++/************************************************************************************************************************* + * bcm2708 GPIO IRQ + */ + + #if BCM_GPIO_USE_IRQ +-static void bcm2708_irq_disable(unsigned irq) +-{ +- struct bcm2708_gpio *chip = get_irq_chip_data(irq); +- //int offset = irq - gpio->irq_base; +- unsigned long flags; + +- spin_lock_irqsave(&chip->irq_lock, flags); +- // disable gpio interrupts here +- spin_unlock_irqrestore(&chip->irq_lock, flags); +-} ++#define IRQ_TO_GPIO(x) irq_to_gpio(x) + +-static void bcm2708_irq_enable(unsigned irq) ++static int bcm2708_gpio_to_irq(struct gpio_chip *chip, unsigned gpio) + { +- struct bcm2708_gpio *chip = get_irq_chip_data(irq); +- //int offset = irq - chip->irq_base; +- unsigned long flags; +- +- spin_lock_irqsave(&chip->irq_lock, flags); +- // enable gpio interrupts here +- spin_unlock_irqrestore(&chip->irq_lock, flags); ++ return gpio_to_irq(gpio); + } + +-static int bcm2708_irq_type(unsigned irq, unsigned trigger) ++static int bcm2708_gpio_irq_set_type(struct irq_data *d, unsigned type) + { +- struct bcm2708_gpio *chip = get_irq_chip_data(irq); +- int offset = irq - chip->irq_base; +- unsigned long flags; +- unsigned gpio_bank = offset/32; +- unsigned gpio_field_offset = (offset - 32*gpio_bank); +- unsigned gpioren, gpiofen, gpiohen, gpiolen; ++ unsigned irq = d->irq; ++ struct bcm2708_gpio *gpio = irq_get_chip_data(irq); + +- if (offset < 0 || offset >= ARCH_NR_GPIOS) ++ if (type & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) + return -EINVAL; + +- spin_lock_irqsave(&chip->irq_lock, flags); ++ if (type & IRQ_TYPE_EDGE_RISING) { ++ gpio->rising |= (1 << IRQ_TO_GPIO(irq)); ++ } else { ++ gpio->rising &= ~(1 << IRQ_TO_GPIO(irq)); ++ } + +- gpioren = readl(chip->base + GPIOREN(gpio_bank)); +- gpiofen = readl(chip->base + GPIOFEN(gpio_bank)); +- gpiohen = readl(chip->base + GPIOHEN(gpio_bank)); +- gpiolen = readl(chip->base + GPIOLEN(gpio_bank)); ++ if (type & IRQ_TYPE_EDGE_FALLING) { ++ gpio->falling |= (1 << IRQ_TO_GPIO(irq)); ++ } else { ++ gpio->falling &= ~(1 << IRQ_TO_GPIO(irq)); ++ } ++ return 0; ++} + +- if (trigger & (IRQ_TYPE_EDGE_RISING)) +- gpioren |= (1<irq; ++ struct bcm2708_gpio *gpio = irq_get_chip_data(irq); ++ unsigned gn = IRQ_TO_GPIO(irq); ++ unsigned gb = gn / 32; ++ unsigned long rising = readl(gpio->base + GPIOREN(gb)); ++ unsigned long falling = readl(gpio->base + GPIOFEN(gb)); + +- writel(gpioren, chip->base + GPIOREN(gpio_bank)); +- writel(gpiofen, chip->base + GPIOFEN(gpio_bank)); +- writel(gpiohen, chip->base + GPIOHEN(gpio_bank)); +- writel(gpiolen, chip->base + GPIOLEN(gpio_bank)); ++ writel(rising & ~(1 << gn), gpio->base + GPIOREN(gb)); ++ writel(falling & ~(1 << gn), gpio->base + GPIOFEN(gb)); ++} + +- spin_unlock_irqrestore(&chip->irq_lock, flags); ++static void bcm2708_gpio_irq_unmask(struct irq_data *d) ++{ ++ unsigned irq = d->irq; ++ struct bcm2708_gpio *gpio = irq_get_chip_data(irq); ++ unsigned gn = IRQ_TO_GPIO(irq); ++ unsigned gb = gn / 32; ++ unsigned long rising = readl(gpio->base + GPIOREN(gb)); ++ unsigned long falling = readl(gpio->base + GPIOFEN(gb)); + +- return 0; ++ gn = gn % 32; ++ ++ writel(1 << gn, gpio->base + GPIOEDS(gb)); ++ ++ if (gpio->rising & (1 << gn)) { ++ writel(rising | (1 << gn), gpio->base + GPIOREN(gb)); ++ } else { ++ writel(rising & ~(1 << gn), gpio->base + GPIOREN(gb)); ++ } ++ ++ if (gpio->falling & (1 << gn)) { ++ writel(falling | (1 << gn), gpio->base + GPIOFEN(gb)); ++ } else { ++ writel(falling & ~(1 << gn), gpio->base + GPIOFEN(gb)); ++ } + } + + static struct irq_chip bcm2708_irqchip = { +- .name = "GPIO", +- .enable = bcm2708_irq_enable, +- .disable = bcm2708_irq_disable, +- .set_type = bcm2708_irq_type, ++ .name = "GPIO", ++ .irq_enable = bcm2708_gpio_irq_unmask, ++ .irq_disable = bcm2708_gpio_irq_mask, ++ .irq_unmask = bcm2708_gpio_irq_unmask, ++ .irq_mask = bcm2708_gpio_irq_mask, ++ .irq_set_type = bcm2708_gpio_irq_set_type, + }; + +-static void bcm2708_irq_handler(unsigned irq, struct irq_desc *desc) ++static irqreturn_t bcm2708_gpio_interrupt(int irq, void *dev_id) + { +- struct list_head *chip_list = get_irq_data(irq); +- struct list_head *ptr; +- struct bcm2708_gpio *chip; +- unsigned gpio_bank; +- +- desc->chip->ack(irq); +- list_for_each(ptr, chip_list) { +- unsigned long pending; +- int offset; +- +- chip = list_entry(ptr, struct bcm2708_gpio, list); +- for (gpio_bank = 0; gpio_bank < ARCH_NR_GPIOS/32; gpio_bank++) { +- pending = readl(chip->base + GPIOEDS(gpio_bank)); +- writel(pending, chip->base + GPIOEDS(gpio_bank)); ++ unsigned long edsr; ++ unsigned bank; ++ int i; ++ unsigned gpio; ++ for (bank = 0; bank <= 1; bank++) { ++ edsr = readl(__io_address(GPIO_BASE) + GPIOEDS(bank)); ++ for_each_set_bit(i, &edsr, 32) { ++ gpio = i + bank * 32; ++ generic_handle_irq(gpio_to_irq(gpio)); ++ } ++ writel(0xffffffff, __io_address(GPIO_BASE) + GPIOEDS(bank)); ++ } ++ return IRQ_HANDLED; ++} + +- if (pending == 0) +- continue; ++static struct irqaction bcm2708_gpio_irq = { ++ .name = "BCM2708 GPIO catchall handler", ++ .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, ++ .handler = bcm2708_gpio_interrupt, ++}; + +- for_each_set_bit(offset, &pending, ARCH_NR_GPIOS) +- generic_handle_irq(gpio_to_irq(offset+32*gpio_bank)); +- } ++static void bcm2708_gpio_irq_init(struct bcm2708_gpio *ucb) ++{ ++ unsigned irq; ++ ++ ucb->gc.to_irq = bcm2708_gpio_to_irq; ++ ++ for (irq = GPIO_IRQ_START; irq < (GPIO_IRQ_START + GPIO_IRQS); irq++) { ++ irq_set_chip_data(irq, ucb); ++ irq_set_chip(irq, &bcm2708_irqchip); ++ set_irq_flags(irq, IRQF_VALID); + } +- desc->chip->unmask(irq); ++ setup_irq(IRQ_GPIO3, &bcm2708_gpio_irq); ++} ++ ++#else ++ ++static void bcm2708_gpio_irq_init(struct bcm2708_gpio *ucb) ++{ + } +-#endif /* #if BCM_GPIO_USE_IRQ */ ++ ++#endif /* #if BCM_GPIO_USE_IRQ ***************************************************************************************************************** */ + + static int bcm2708_gpio_probe(struct platform_device *dev) + { +@@ -247,7 +263,7 @@ + struct resource *res; + int err = 0; + +- printk(KERN_ERR DRIVER_NAME ": bcm2708_gpio_probe %p\n", dev); ++ printk(KERN_ERR DRIVER_NAME ": bcm2708_gpio_probe %p\n", dev); + + ucb = kzalloc(sizeof(*ucb), GFP_KERNEL); + if (NULL == ucb) { +@@ -260,7 +276,7 @@ + res = platform_get_resource(dev, IORESOURCE_MEM, 0); + + platform_set_drvdata(dev, ucb); +- ucb->base = __io_address(GPIO_BASE); ++ ucb->base = __io_address(GPIO_BASE); + + ucb->gc.label = "bcm2708_gpio"; + ucb->gc.base = 0; +@@ -273,6 +289,8 @@ + ucb->gc.set = bcm2708_gpio_set; + ucb->gc.can_sleep = 0; + ++ bcm2708_gpio_irq_init(ucb); ++ + err = gpiochip_add(&ucb->gc); + if (err) + goto err; +@@ -298,11 +316,10 @@ + } + + static struct platform_driver bcm2708_gpio_driver = { +- .probe = bcm2708_gpio_probe, +- .remove = bcm2708_gpio_remove, +- .driver = { +- .name = "bcm2708_gpio" +- }, ++ .probe = bcm2708_gpio_probe, ++ .remove = bcm2708_gpio_remove, ++ .driver = { ++ .name = "bcm2708_gpio"}, + }; + + static int __init bcm2708_gpio_init(void) +@@ -320,4 +337,3 @@ + + MODULE_DESCRIPTION("Broadcom BCM2708 GPIO driver"); + MODULE_LICENSE("GPL"); +- +Index: linux-3.2.46/arch/arm/mach-bcm2708/include/mach/gpio.h +=================================================================== +--- linux-3.2.46.orig/arch/arm/mach-bcm2708/include/mach/gpio.h 2013-07-26 19:31:51.000000000 +0000 ++++ linux-3.2.46/arch/arm/mach-bcm2708/include/mach/gpio.h 2013-07-26 19:33:45.000000000 +0000 +@@ -12,7 +12,8 @@ + #define ARCH_NR_GPIOS 54 // number of gpio lines + + #include +- ++#include ++#include + + #ifdef CONFIG_GPIOLIB + +@@ -31,18 +32,14 @@ + return __gpio_cansleep(gpio); + } + +-static inline int gpio_to_irq(unsigned gpio) +-{ +- WARN_ON(1); +- return -ENOSYS; +-} + +-static inline int irq_to_gpio(unsigned int irq) +-{ +- WARN_ON(1); +- return -EINVAL; ++static inline unsigned irq_to_gpio(unsigned irq) { ++ return (irq-GPIO_IRQ_START); + } + ++static inline unsigned gpio_to_irq(unsigned gpio) { ++ return GPIO_IRQ_START+gpio; ++} + #endif /* CONFIG_GPIOLIB */ + + #endif +Index: linux-3.2.46/arch/arm/mach-bcm2708/include/mach/irqs.h +=================================================================== +--- linux-3.2.46.orig/arch/arm/mach-bcm2708/include/mach/irqs.h 2013-07-26 19:31:51.000000000 +0000 ++++ linux-3.2.46/arch/arm/mach-bcm2708/include/mach/irqs.h 2013-07-26 19:33:45.000000000 +0000 +@@ -185,6 +185,12 @@ + #define FIQ_PENDING1 INT_PENDING1 + #define FIQ_PENDING2 INT_PENDING2 + +-#define NR_IRQS (64 + 21) ++#define HARD_IRQS (64 + 21) ++#define GPIO_IRQ_START HARD_IRQS ++ ++#define GPIO_IRQS 32*5 ++ ++#define NR_IRQS HARD_IRQS+GPIO_IRQS ++ + + #endif /* _BCM2708_IRQS_H_ */ diff -Nru linux-3.2.46/debian/patches/rpi/rpi_176_887af3c7add637e26c39bccc9156a65260721d69.patch linux-3.2.46/debian/patches/rpi/rpi_176_887af3c7add637e26c39bccc9156a65260721d69.patch --- linux-3.2.46/debian/patches/rpi/rpi_176_887af3c7add637e26c39bccc9156a65260721d69.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_176_887af3c7add637e26c39bccc9156a65260721d69.patch 2013-07-26 19:33:47.000000000 +0000 @@ -0,0 +1,75 @@ +commit 887af3c7add637e26c39bccc9156a65260721d69 +Author: popcornmix +Date: Sat Jun 30 16:07:18 2012 +0100 + + Add a pm_power_off function that resets us, and indicates to bootcode.bin not to reboot us. Should allow a lower power 'off' state + +Index: linux-3.2.46/arch/arm/mach-bcm2708/bcm2708.c +=================================================================== +--- linux-3.2.46.orig/arch/arm/mach-bcm2708/bcm2708.c 2013-07-26 19:33:07.000000000 +0000 ++++ linux-3.2.46/arch/arm/mach-bcm2708/bcm2708.c 2013-07-26 19:33:46.000000000 +0000 +@@ -53,6 +53,7 @@ + #include + #include + #include ++#include + + #include "bcm2708.h" + #include "armctrl.h" +@@ -472,10 +473,23 @@ + return ret; + } + ++/* We can't really power off, but if we do the normal reset scheme, and indicate to bootcode.bin not to reboot, then most of the chip will be powered off */ ++static void bcm2708_power_off(void) ++{ ++ /* we set the watchdog hard reset bit here to distinguish this reset from the normal (full) reset. bootcode.bin will not reboot after a hard reset */ ++ uint32_t pm_rsts = readl(IO_ADDRESS(PM_RSTS)); ++ pm_rsts = PM_PASSWORD | (pm_rsts & PM_RSTC_WRCFG_CLR) | PM_RSTS_HADWRH_SET; ++ writel(pm_rsts, IO_ADDRESS(PM_RSTS)); ++ /* continue with normal reset mechanism */ ++ arch_reset(0, ""); ++} ++ + void __init bcm2708_init(void) + { + int i; + ++ pm_power_off = bcm2708_power_off; ++ + for (i = 0; i < ARRAY_SIZE(lookups); i++) + clkdev_add(&lookups[i]); + +Index: linux-3.2.46/arch/arm/mach-bcm2708/include/mach/platform.h +=================================================================== +--- linux-3.2.46.orig/arch/arm/mach-bcm2708/include/mach/platform.h 2013-07-26 19:31:51.000000000 +0000 ++++ linux-3.2.46/arch/arm/mach-bcm2708/include/mach/platform.h 2013-07-26 19:33:46.000000000 +0000 +@@ -191,6 +191,7 @@ + * Watchdog + */ + #define PM_RSTC (PM_BASE+0x1c) ++#define PM_RSTS (PM_BASE+0x20) + #define PM_WDOG (PM_BASE+0x24) + + #define PM_WDOG_RESET 0000000000 +@@ -199,9 +200,18 @@ + #define PM_RSTC_WRCFG_CLR 0xffffffcf + #define PM_RSTC_WRCFG_SET 0x00000030 + #define PM_RSTC_WRCFG_FULL_RESET 0x00000020 +-#define PM_RSTC_RESET 0x00000102 +- ++#define PM_RSTC_RESET 0x00000102 + ++#define PM_RSTS_HADPOR_SET 0x00001000 ++#define PM_RSTS_HADSRH_SET 0x00000400 ++#define PM_RSTS_HADSRF_SET 0x00000200 ++#define PM_RSTS_HADSRQ_SET 0x00000100 ++#define PM_RSTS_HADWRH_SET 0x00000040 ++#define PM_RSTS_HADWRF_SET 0x00000020 ++#define PM_RSTS_HADWRQ_SET 0x00000010 ++#define PM_RSTS_HADDRH_SET 0x00000004 ++#define PM_RSTS_HADDRF_SET 0x00000002 ++#define PM_RSTS_HADDRQ_SET 0x00000001 + + + diff -Nru linux-3.2.46/debian/patches/rpi/rpi_177_8825835abbe587ef23e2eb64114ce67dfd391c44.patch linux-3.2.46/debian/patches/rpi/rpi_177_8825835abbe587ef23e2eb64114ce67dfd391c44.patch --- linux-3.2.46/debian/patches/rpi/rpi_177_8825835abbe587ef23e2eb64114ce67dfd391c44.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_177_8825835abbe587ef23e2eb64114ce67dfd391c44.patch 2013-07-26 19:33:49.000000000 +0000 @@ -0,0 +1,50 @@ +commit 8825835abbe587ef23e2eb64114ce67dfd391c44 +Author: popcornmix +Date: Sun Jul 1 12:09:52 2012 +0100 + + Store palette info where GPU can see it, so 8bpp modes can work. Requires updated start.elf to work properly + +Index: linux-3.2.46/drivers/video/bcm2708_fb.c +=================================================================== +--- linux-3.2.46.orig/drivers/video/bcm2708_fb.c 2013-07-26 19:33:01.000000000 +0000 ++++ linux-3.2.46/drivers/video/bcm2708_fb.c 2013-07-26 19:33:48.000000000 +0000 +@@ -48,6 +48,7 @@ + u32 xoffset, yoffset; + u32 base; + u32 screen_size; ++ u16 cmap[256]; + }; + + struct bcm2708_fb { +@@ -266,18 +267,31 @@ + return (val >> (16 - bf->length) & mask) << bf->offset; + } + ++ + static int bcm2708_fb_setcolreg(unsigned int regno, unsigned int red, + unsigned int green, unsigned int blue, + unsigned int transp, struct fb_info *info) + { + struct bcm2708_fb *fb = to_bcm2708(info); + ++ /*pr_info("BCM2708FB: setcolreg %d:(%02x,%02x,%02x,%02x) %x\n", regno, red, green, blue, transp, fb->fb.fix.visual);*/ + if (regno < 16) + fb->cmap[regno] = convert_bitfield(transp, &fb->fb.var.transp) | + convert_bitfield(blue, &fb->fb.var.blue) | + convert_bitfield(green, &fb->fb.var.green) | + convert_bitfield(red, &fb->fb.var.red); + ++ if (regno < 256) { ++ /* blue [0:4], green [5:10], red [11:15] */ ++ fb->info->cmap[regno] = ((red >> (16-5)) & 0x1f) << 11 | ++ ((green >> (16-6)) & 0x3f) << 5 | ++ ((blue >> (16-5)) & 0x1f) << 0; ++ } ++ /* Hack: we need to tell GPU the palette has changed, but currently bcm2708_fb_set_par takes noticable time when called for every (256) colour */ ++ /* So just call it for what looks like the last colour in a list for now. */ ++ if (regno == 15 || regno == 255) ++ bcm2708_fb_set_par(info); ++ + return regno > 255; + } + diff -Nru linux-3.2.46/debian/patches/rpi/rpi_178_56afa5ae9400b1948da1fd28b3f54787b13fa555.patch linux-3.2.46/debian/patches/rpi/rpi_178_56afa5ae9400b1948da1fd28b3f54787b13fa555.patch --- linux-3.2.46/debian/patches/rpi/rpi_178_56afa5ae9400b1948da1fd28b3f54787b13fa555.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_178_56afa5ae9400b1948da1fd28b3f54787b13fa555.patch 2013-07-26 19:33:50.000000000 +0000 @@ -0,0 +1,46 @@ +commit 56afa5ae9400b1948da1fd28b3f54787b13fa555 +Author: popcornmix +Date: Mon Jul 2 20:34:38 2012 +0100 + + Avoid blanking console when not in palettised mode + +Index: linux-3.2.46/drivers/video/bcm2708_fb.c +=================================================================== +--- linux-3.2.46.orig/drivers/video/bcm2708_fb.c 2013-07-26 19:33:48.000000000 +0000 ++++ linux-3.2.46/drivers/video/bcm2708_fb.c 2013-07-26 19:33:49.000000000 +0000 +@@ -275,23 +275,23 @@ + struct bcm2708_fb *fb = to_bcm2708(info); + + /*pr_info("BCM2708FB: setcolreg %d:(%02x,%02x,%02x,%02x) %x\n", regno, red, green, blue, transp, fb->fb.fix.visual);*/ +- if (regno < 16) ++ if (fb->fb.var.bits_per_pixel <= 8) { ++ if (regno < 256) { ++ /* blue [0:4], green [5:10], red [11:15] */ ++ fb->info->cmap[regno] = ((red >> (16-5)) & 0x1f) << 11 | ++ ((green >> (16-6)) & 0x3f) << 5 | ++ ((blue >> (16-5)) & 0x1f) << 0; ++ } ++ /* Hack: we need to tell GPU the palette has changed, but currently bcm2708_fb_set_par takes noticable time when called for every (256) colour */ ++ /* So just call it for what looks like the last colour in a list for now. */ ++ if (regno == 15 || regno == 255) ++ bcm2708_fb_set_par(info); ++ } else if (regno < 16) { + fb->cmap[regno] = convert_bitfield(transp, &fb->fb.var.transp) | + convert_bitfield(blue, &fb->fb.var.blue) | + convert_bitfield(green, &fb->fb.var.green) | + convert_bitfield(red, &fb->fb.var.red); +- +- if (regno < 256) { +- /* blue [0:4], green [5:10], red [11:15] */ +- fb->info->cmap[regno] = ((red >> (16-5)) & 0x1f) << 11 | +- ((green >> (16-6)) & 0x3f) << 5 | +- ((blue >> (16-5)) & 0x1f) << 0; + } +- /* Hack: we need to tell GPU the palette has changed, but currently bcm2708_fb_set_par takes noticable time when called for every (256) colour */ +- /* So just call it for what looks like the last colour in a list for now. */ +- if (regno == 15 || regno == 255) +- bcm2708_fb_set_par(info); +- + return regno > 255; + } + diff -Nru linux-3.2.46/debian/patches/rpi/rpi_179_13d7000c574bdc16681c01b23a79169984ecfe9e.patch linux-3.2.46/debian/patches/rpi/rpi_179_13d7000c574bdc16681c01b23a79169984ecfe9e.patch --- linux-3.2.46/debian/patches/rpi/rpi_179_13d7000c574bdc16681c01b23a79169984ecfe9e.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_179_13d7000c574bdc16681c01b23a79169984ecfe9e.patch 2013-07-26 19:33:52.000000000 +0000 @@ -0,0 +1,589 @@ +commit 13d7000c574bdc16681c01b23a79169984ecfe9e +Author: popcornmix +Date: Fri Jul 6 18:30:43 2012 +0100 + + Add mechanism to reduce the number of SOF interrupts in dwc_otg USB driver. Enable through /proc/dwc_sof/SOF_reduction + +Index: linux-3.2.46/drivers/usb/host/dwc_common_port/dwc_common_linux.c +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_common_port/dwc_common_linux.c 2013-07-26 19:31:19.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_common_port/dwc_common_linux.c 2013-07-26 19:33:51.000000000 +0000 +@@ -1021,7 +1021,7 @@ + { + dwc_timer_t *timer = (dwc_timer_t *)data; + set_scheduled(timer, 0); +- DWC_DEBUG("Timer %s callback", timer->name); ++ /*DWC_DEBUG("Timer %s callback", timer->name);*/ + timer->cb(timer->data); + } + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/Makefile +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/Makefile 2013-07-26 19:32:22.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/Makefile 2013-07-26 19:33:51.000000000 +0000 +@@ -15,9 +15,14 @@ + + # Use one of the following flags to compile the software in host-only or + # device-only mode. +-#CPPFLAGS += -DDWC_HOST_ONLY ++ifeq ($(CONFIG_USB_GADGET_DWCOTG),) ++CPPFLAGS += -DDWC_HOST_ONLY ++endif + #CPPFLAGS += -DDWC_DEVICE_ONLY + ++# Use this flag to reduce SOF interrupt service overhead ++CPPFLAGS += -DSOF_FIX ++ + CPPFLAGS += -Dlinux -DDWC_HS_ELECT_TST + #CGG: CPPFLAGS += -DDWC_EN_ISOC + CPPFLAGS += -I$(obj)/../dwc_common_port +Index: linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_driver.c +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/dwc_otg_driver.c 2013-07-26 19:31:23.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_driver.c 2013-07-26 19:33:51.000000000 +0000 +@@ -82,6 +82,11 @@ + + # include + ++#ifdef SOF_FIX ++#include ++#include ++#endif ++ + #include + + +@@ -178,6 +183,8 @@ + int32_t lpm_enable; + int32_t ic_usb_cap; + int32_t ahb_thr_ratio; ++ int32_t sof_setting; // 0=off, 1=on ++ int32_t proc_init_done; // 0=not done, 1=done + }; + + static struct dwc_otg_driver_module_params dwc_otg_module_params = { +@@ -254,9 +261,139 @@ + .lpm_enable = -1, + .ic_usb_cap = -1, + .ahb_thr_ratio = -1, ++ .sof_setting = 0, ++ .proc_init_done = 0, + }; + + /** ++ * PROC_FS SUPPORT ++ * proc_fs support for setting the Start-of-Frame (SOF) interrupt processing ++ * fix (reducing SOF interrupts by an order of magnitude). When set ++ * to "on" the SOF interrupt will only be turned on once per tick, for ++ * 3 micro-frame times. When set to "off" it will not turn off the ++ * SOF interrupt, and process all 8000 per second. ++ */ ++ ++#ifdef SOF_FIX ++ ++static struct proc_dir_entry *proc_dir, *proc_file; ++ ++int sof_setting(void) ++{ ++ return dwc_otg_module_params.sof_setting; ++} ++ ++static int sof_read_data (char *page, ++ char **start, ++ off_t off, ++ int count, ++ int *eof, ++ void *data) ++{ ++ ++ if (dwc_otg_module_params.sof_setting == 1) ++ { ++ sprintf(page, "on\n"); ++ return 4; ++ } ++ else ++ { ++ sprintf(page, "off\n"); ++ return 5; ++ } ++ return 0; ++} ++ ++#define PROC_FS_MAX_SIZE 1024 ++#define PROC_FS_NAME "SOF_reduction" ++ ++static char proc_fs_buffer[PROC_FS_MAX_SIZE]; ++ ++static int sof_write_data (struct file *file, ++ const char __user *buffer, ++ unsigned long count, ++ void *data) ++{ ++ unsigned long buffer_size = count; ++ ++ if (buffer_size > PROC_FS_MAX_SIZE) ++ buffer_size = PROC_FS_MAX_SIZE; ++ ++ memset(proc_fs_buffer, 0, sizeof(proc_fs_buffer)); ++ ++ if (copy_from_user(proc_fs_buffer, buffer, buffer_size)) ++ { ++ printk(KERN_ERR "\nSOF_write_data: copy_from_user failure\n"); ++ return -EFAULT; ++ } ++ ++ if ((strnlen(proc_fs_buffer, PROC_FS_MAX_SIZE) == 3) && ++ (strncmp(proc_fs_buffer, "on", 2) == 0)) ++ { ++ printk(KERN_ERR "\n%s: Setting SOF (reduction) ON.\n", PROC_FS_NAME); ++ dwc_otg_module_params.sof_setting = 1; ++ } ++ else if ((strnlen(proc_fs_buffer, PROC_FS_MAX_SIZE) == 4) && ++ (strncmp(proc_fs_buffer, "off", 3) == 0)) ++ { ++ printk(KERN_ERR "\n%s: Setting SOF reduction OFF.\n",PROC_FS_NAME); ++ dwc_otg_module_params.sof_setting = 0; ++ } ++ else ++ printk(KERN_ERR "\n%s: input not \'on\' or \'off\', ignored.\n", PROC_FS_NAME); ++#ifdef DEBUG_SOF_FIX ++ printk(KERN_ERR "\n%s:buffer %s, len = %d.\n",__func__, ++ proc_fs_buffer, strnlen(proc_fs_buffer, PROC_FS_MAX_SIZE)); ++#endif ++ ++ return buffer_size; ++} ++ ++/** ++ * Initialize proc_fs entry for SOF setting. ++ */ ++static int init_proc_fs(void) ++{ ++ int retval = 0; ++ ++ if (dwc_otg_module_params.proc_init_done) ++ return 0; ++ ++ proc_dir = proc_mkdir_mode("dwc_sof", 0755, NULL); ++ ++ if(proc_dir == NULL) ++ { ++ retval = -ENOMEM; ++ printk("Error creating dir\n"); ++ return retval; ++ } ++ ++ proc_file = create_proc_entry(PROC_FS_NAME, 0666, proc_dir); ++ ++ if (proc_file != NULL) ++ { ++ dwc_otg_module_params.proc_init_done = 1; ++ proc_file->read_proc = sof_read_data; ++ proc_file->write_proc = sof_write_data; ++ proc_file->mode = S_IFREG | S_IRUGO; ++ proc_file->uid = 0; ++ proc_file->gid = 0; ++ proc_file->gid = PROC_FS_MAX_SIZE; ++ } ++ else ++ { ++ retval = -ENOMEM; ++ printk("Error creating file\n"); ++ remove_proc_entry(PROC_FS_NAME, NULL); ++ } ++ ++ return retval; ++} ++ ++#endif ++ ++ ++/** + * This function shows the Driver Version. + */ + static ssize_t version_show(struct device_driver *dev, char *buf) +@@ -845,6 +982,12 @@ + dev_dbg(&_dev->dev, "Calling attr_create\n"); + dwc_otg_attr_create(_dev); + ++#ifdef SOF_FIX ++ retval = init_proc_fs(); ++ if (retval) ++ goto fail; ++#endif ++ + /* + * Disable the global interrupt until all the interrupt + * handlers are installed. +@@ -1015,6 +1158,7 @@ + * + * @return + */ ++ + static int __init dwc_otg_driver_init(void) + { + int retval = 0; +@@ -1049,6 +1193,11 @@ + error = driver_create_file(&dwc_otg_driver.driver, + &driver_attr_debuglevel); + #endif ++ ++#ifdef SOF_FIX ++ retval = init_proc_fs(); ++#endif ++ + return retval; + } + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_hcd.c +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/dwc_otg_hcd.c 2013-07-26 19:32:45.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_hcd.c 2013-07-26 19:33:51.000000000 +0000 +@@ -64,6 +64,37 @@ + __DWC_ERROR("Device Not Connected/Responding\n"); + } + ++/** ++ * SOF_FIX: Reduce the SOF overhead by disabling the SOF interrupt except ++ * when there are USB transfers pending. Re-enable the interrupt ++ * every tick for periodic transaction handling. MSO 5/31/12 ++ * SOF (Start of Frame) timeout function. Kick the driver by re-enabling ++ * the SOF interrupt ++ */ ++#ifdef SOF_FIX ++void dwc_otg_hcd_sof_timeout(void *ptr) ++{ ++ dwc_otg_hcd_t * hcd = (dwc_otg_hcd_t *)ptr; ++ dwc_otg_core_if_t *core_if = hcd->core_if; ++ gintmsk_data_t gintmsk = {.d32 = 0}; ++ dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs; ++ unsigned int intmsk; ++ ++ // turn on Start-of-Frame interrupt ++ gintmsk.d32 = dwc_read_reg32(&global_regs->gintmsk); ++ intmsk = gintmsk.d32; ++ gintmsk.b.sofintr |= 1; ++ dwc_write_reg32(&global_regs->gintmsk, gintmsk.d32); ++ DWC_TIMER_SCHEDULE(hcd->sof_timer, 1); /* 1ms */ ++#ifdef DEBUG_SOF_FIX ++ if ((++sof_timeout_count % 10000) == 0) ++ printk(KERN_ERR "%s: %d timeouts handled, read 0x%x wrote 0x%x.", ++ __FUNCTION__, sof_timeout_count, intmsk, gintmsk.d32); ++#endif ++ ++} ++#endif ++ + #ifdef DEBUG + static void dump_channel_info(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh) + { +@@ -792,6 +823,13 @@ + hcd->conn_timer = DWC_TIMER_ALLOC("Connection timer", + dwc_otg_hcd_connect_timeout, 0); + ++#ifdef SOF_FIX ++ /* Initialize the Start of Frame interrupt timeout timer. */ ++ hcd->sof_timer = DWC_TIMER_ALLOC("SOF timer", ++ dwc_otg_hcd_sof_timeout, hcd); ++ DWC_TIMER_SCHEDULE(hcd->sof_timer, 1); /* 1ms */ ++#endif ++ + /* Initialize reset tasklet. */ + hcd->reset_tasklet = DWC_TASK_ALLOC(reset_tasklet_func, hcd); + +@@ -1307,6 +1345,11 @@ + dwc_otg_qh_t *qh; + int num_channels; + dwc_otg_transaction_type_e ret_val = DWC_OTG_TRANSACTION_NONE; ++#ifdef SOF_FIX ++ dwc_otg_core_if_t *core_if = hcd->core_if; ++ gintmsk_data_t gintmsk = {.d32 = 0}; ++ dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs; ++#endif + + #ifdef DEBUG_SOF + DWC_DEBUGPL(DBG_HCD, " Select Transactions\n"); +@@ -1346,6 +1389,19 @@ + } + #endif + } ++#ifdef SOF_FIX ++ /* ++ * If there are transactions queued then enable the SOF interrupt to send them to ++ * the controller. ++ */ ++ if (ret_val != DWC_OTG_TRANSACTION_NONE) ++ { ++ // turn on Start-of-Frame interrupt ++ gintmsk.d32 = dwc_read_reg32(&global_regs->gintmsk); ++ gintmsk.b.sofintr |= 1; ++ dwc_write_reg32(&global_regs->gintmsk, gintmsk.d32); ++ } ++#endif + + /* + * Process entries in the inactive portion of the non-periodic +Index: linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_hcd.h +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/dwc_otg_hcd.h 2013-07-26 19:32:56.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_hcd.h 2013-07-26 19:33:51.000000000 +0000 +@@ -569,6 +569,15 @@ + uint32_t hfnum_other_samples_b; + uint64_t hfnum_other_frrem_accum_b; + #endif ++#ifdef SOF_FIX ++ /** ++ * SOF wakeup timer. We disable the SOF interrupt if there is nothing ++ * to do. However, that eventually gets us into trouble. So, re-enable ++ * the SOF interrupt every tick so we can handle any backlog that does ++ * not trigger any other interrupt. ++ */ ++ dwc_timer_t *sof_timer; ++#endif + }; + + /** @name Transaction Execution Functions */ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c 2013-07-26 19:33:42.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c 2013-07-26 19:33:51.000000000 +0000 +@@ -32,6 +32,8 @@ + * ========================================================================== */ + #ifndef DWC_DEVICE_ONLY + ++#include ++#include + #include "dwc_otg_hcd.h" + #include "dwc_otg_regs.h" + +@@ -39,6 +41,19 @@ + * This file contains the implementation of the HCD Interrupt handlers. + */ + ++/** ++ * SOF_FIX: Reduce SOF interrupt handling by disabling the SOF interrupt except ++ * when there are actual USB transfers pending. MSO 5/31/12 ++ */ ++#ifdef SOF_FIX ++ extern int sof_setting(void); ++ unsigned int g_dwc_otg_hcd_handle_intr_count = 0; ++ #ifdef DEBUG_SOF_FIX ++ unsigned int g_dwc_otg_interrupt_counts[10] = {0,0,0,0,0,0,0,0,0,0}; ++ extern int g_softintr_ref_cnt; ++ #endif ++#endif ++ + /** This function handles interrupts for the HCD. */ + int32_t dwc_otg_hcd_handle_intr(dwc_otg_hcd_t * dwc_otg_hcd) + { +@@ -46,9 +61,12 @@ + + dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if; + gintsts_data_t gintsts; +-#ifdef DEBUG ++#ifdef SOF_FIX + dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs; ++ gintmsk_data_t gintmsk; ++#endif + ++#ifdef DEBUG + //GRAYG: debugging + if (NULL == global_regs) { + DWC_DEBUGPL(DBG_HCD, "**** NULL regs: dwc_otg_hcd=%p " +@@ -57,7 +75,9 @@ + return retval; + } + #endif +- ++#ifdef SOF_FIX ++ g_dwc_otg_hcd_handle_intr_count++; ++#endif + /* Check if HOST Mode */ + if (dwc_otg_is_host_mode(core_if)) { + gintsts.d32 = dwc_otg_read_core_intr(core_if); +@@ -81,29 +101,64 @@ + gintsts.d32, core_if); + #endif + +- if (gintsts.b.sofintr) { ++ /* ++ * If SOF handle it. If not, it probably means that there is work to do, ++ * so enable SOF for the next micro-frame. ++ */ ++ if (gintsts.b.sofintr) ++ { ++#ifdef DEBUG_SOF_FIX ++ g_dwc_otg_interrupt_counts[0]++; ++#endif + retval |= dwc_otg_hcd_handle_sof_intr(dwc_otg_hcd); + } ++#ifdef SOF_FIX ++ else ++ { ++ // turn on Start-of-Frame interrupt ++ gintmsk.d32 = dwc_read_reg32(&global_regs->gintmsk); ++ gintmsk.b.sofintr |= 1; ++ dwc_write_reg32(&global_regs->gintmsk, gintmsk.d32); ++ } ++#endif + if (gintsts.b.rxstsqlvl) { ++#ifdef DEBUG_SOF_FIX ++ g_dwc_otg_interrupt_counts[1]++; ++#endif + retval |= + dwc_otg_hcd_handle_rx_status_q_level_intr + (dwc_otg_hcd); + } + if (gintsts.b.nptxfempty) { ++#ifdef DEBUG_SOF_FIX ++ g_dwc_otg_interrupt_counts[2]++; ++#endif + retval |= + dwc_otg_hcd_handle_np_tx_fifo_empty_intr + (dwc_otg_hcd); + } + if (gintsts.b.i2cintr) { ++#ifdef DEBUG_SOF_FIX ++ g_dwc_otg_interrupt_counts[3]++; ++#endif + /** @todo Implement i2cintr handler. */ + } + if (gintsts.b.portintr) { ++#ifdef DEBUG_SOF_FIX ++ g_dwc_otg_interrupt_counts[4]++; ++#endif + retval |= dwc_otg_hcd_handle_port_intr(dwc_otg_hcd); + } + if (gintsts.b.hcintr) { ++#ifdef DEBUG_SOF_FIX ++ g_dwc_otg_interrupt_counts[5]++; ++#endif + retval |= dwc_otg_hcd_handle_hc_intr(dwc_otg_hcd); + } + if (gintsts.b.ptxfempty) { ++#ifdef DEBUG_SOF_FIX ++ g_dwc_otg_interrupt_counts[6]++; ++#endif + retval |= + dwc_otg_hcd_handle_perio_tx_fifo_empty_intr + (dwc_otg_hcd); +@@ -130,7 +185,21 @@ + #endif + + } +- ++#if defined(SOF_FIX) && defined(DEBUG_SOF_FIX) ++ if ((g_dwc_otg_hcd_handle_intr_count % 80000) == 0) ++ { ++ printk(KERN_ERR "dwc_otg_hcd_handle_intr: %u handled, %u, %u, %u, %u, %u, %u, %u, %u.\n", ++ g_dwc_otg_hcd_handle_intr_count, ++ g_dwc_otg_interrupt_counts[0], ++ g_dwc_otg_interrupt_counts[1], ++ g_dwc_otg_interrupt_counts[2], ++ g_dwc_otg_interrupt_counts[3], ++ g_dwc_otg_interrupt_counts[4], ++ g_dwc_otg_interrupt_counts[5], ++ g_dwc_otg_interrupt_counts[6], ++ g_dwc_otg_interrupt_counts[7]); ++ } ++#endif + return retval; + } + +@@ -174,6 +243,10 @@ + * (micro)frame. Periodic transactions may be queued to the controller for the + * next (micro)frame. + */ ++#ifdef SOF_FIX ++#define SOF_INTR_DELAY_COUNT 3 ++static int g_sof_intr_delay_count = SOF_INTR_DELAY_COUNT; ++#endif + int32_t dwc_otg_hcd_handle_sof_intr(dwc_otg_hcd_t * hcd) + { + hfnum_data_t hfnum; +@@ -181,6 +254,11 @@ + dwc_otg_qh_t *qh; + dwc_otg_transaction_type_e tr_type; + gintsts_data_t gintsts = {.d32 = 0 }; ++#ifdef SOF_FIX ++ dwc_otg_core_if_t *core_if = hcd->core_if; ++ gintmsk_data_t gintmsk = {.d32 = 0 }; ++ dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs; ++#endif + + hfnum.d32 = + dwc_read_reg32(&hcd->core_if->host_if->host_global_regs->hfnum); +@@ -213,9 +291,24 @@ + } + } + tr_type = dwc_otg_hcd_select_transactions(hcd); +- if (tr_type != DWC_OTG_TRANSACTION_NONE) { ++ if (tr_type != DWC_OTG_TRANSACTION_NONE) ++ { + dwc_otg_hcd_queue_transactions(hcd, tr_type); + } ++#ifdef SOF_FIX ++ else ++ { ++ // turn off Start-of-Frame interrupt ++ if ((sof_setting()) && ++ (g_sof_intr_delay_count-- == 0)) ++ { ++ gintmsk.d32 = dwc_read_reg32(&global_regs->gintmsk); ++ gintmsk.b.sofintr &= 0; ++ dwc_write_reg32(&global_regs->gintmsk, gintmsk.d32); ++ g_sof_intr_delay_count = SOF_INTR_DELAY_COUNT; ++ } ++ } ++#endif + + /* Clear interrupt */ + gintsts.b.sofintr = 1; +Index: linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c 2013-07-26 19:33:42.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c 2013-07-26 19:33:51.000000000 +0000 +@@ -260,10 +260,19 @@ + * Sets the final status of an URB and returns it to the device driver. Any + * required cleanup of the URB is performed. + */ ++#ifdef DEBUG_SOF_FIX ++extern unsigned int g_dwc_otg_interrupt_counts[10]; ++#endif ++ + static int _complete(dwc_otg_hcd_t * hcd, void *urb_handle, + dwc_otg_hcd_urb_t * dwc_otg_urb, int32_t status) + { + struct urb *urb = (struct urb *)urb_handle; ++ ++#ifdef DEBUG_SOF_FIX ++ g_dwc_otg_interrupt_counts[7]++; ++#endif ++ + #ifdef DEBUG + if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) { + DWC_PRINTF("%s: urb %p, device %d, ep %d %s, status=%d\n", +@@ -810,6 +819,10 @@ + * interrupt. + * + * This function is called by the USB core when an interrupt occurs */ ++ ++#ifdef DEBUG_SOF_FIX ++unsigned int g_dwc_otg_hcd_irq_count = 0; ++#endif + static irqreturn_t dwc_otg_hcd_irq(struct usb_hcd *hcd) + { + dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd); +@@ -817,6 +830,12 @@ + if (retval != 0) { + S3C2410X_CLEAR_EINTPEND(); + } ++ ++#ifdef DEBUG_SOF_FIX ++ ++g_dwc_otg_hcd_irq_count; ++ if ((++g_dwc_otg_hcd_irq_count %10000) == 0) ++ printk(KERN_ERR "dwc_otg_hcd_irq: %u completions.\n", g_dwc_otg_hcd_irq_count); ++#endif + return IRQ_RETVAL(retval); + } + diff -Nru linux-3.2.46/debian/patches/rpi/rpi_180_105858e4506975bfb3e293f2e815d14eae40958c.patch linux-3.2.46/debian/patches/rpi/rpi_180_105858e4506975bfb3e293f2e815d14eae40958c.patch --- linux-3.2.46/debian/patches/rpi/rpi_180_105858e4506975bfb3e293f2e815d14eae40958c.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_180_105858e4506975bfb3e293f2e815d14eae40958c.patch 2013-07-26 19:33:53.000000000 +0000 @@ -0,0 +1,66 @@ +commit 105858e4506975bfb3e293f2e815d14eae40958c +Author: Bryan Kemp +Date: Sat Jul 7 16:24:07 2012 -0500 + + Updating dwc_otg driver to fix issue releasing pcm stream see: https://github.com/raspberrypi/firmware/issues/51 + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c 2013-07-26 19:33:51.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c 2013-07-26 19:33:52.000000000 +0000 +@@ -70,6 +70,7 @@ + #include "dwc_otg_hcd_if.h" + #include "dwc_otg_dbg.h" + #include "dwc_otg_driver.h" ++#include "dwc_otg_hcd.h" + + /** + * Gets the endpoint number from a _bEndpointAddress argument. The endpoint is +@@ -267,6 +268,7 @@ + static int _complete(dwc_otg_hcd_t * hcd, void *urb_handle, + dwc_otg_hcd_urb_t * dwc_otg_urb, int32_t status) + { ++ uint64_t flags; + struct urb *urb = (struct urb *)urb_handle; + + #ifdef DEBUG_SOF_FIX +@@ -356,7 +358,9 @@ + #if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30)) + usb_hcd_giveback_urb(dwc_otg_hcd_to_hcd(hcd), urb); + #else ++ DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags); + usb_hcd_unlink_urb_from_ep(dwc_otg_hcd_to_hcd(hcd), urb); ++ DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags); + usb_hcd_giveback_urb(dwc_otg_hcd_to_hcd(hcd), urb, status); + #endif + return 0; +@@ -767,6 +771,8 @@ + static int urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status) + #endif + { ++ int rc; ++ uint64_t flags; + dwc_otg_hcd_t *dwc_otg_hcd; + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD URB Dequeue\n"); + +@@ -788,8 +794,18 @@ + #if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30)) + usb_hcd_giveback_urb(hcd, urb); + #else +- usb_hcd_unlink_urb_from_ep(hcd, urb); +- usb_hcd_giveback_urb(hcd, urb, status); ++ DWC_SPINLOCK_IRQSAVE(dwc_otg_hcd->lock, &flags); ++ rc = usb_hcd_check_unlink_urb(hcd, urb, status); ++ if(!rc) ++ { ++ usb_hcd_unlink_urb_from_ep(hcd, urb); ++ } ++ ++ DWC_SPINUNLOCK_IRQRESTORE(dwc_otg_hcd->lock, flags); ++ if (!rc) ++ { ++ usb_hcd_giveback_urb(hcd, urb, status); ++ } + #endif + if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) { + DWC_PRINTF("Called usb_hcd_giveback_urb()\n"); diff -Nru linux-3.2.46/debian/patches/rpi/rpi_181_269b48f50f4fd07067c9b47c557c20e524cbca71.patch linux-3.2.46/debian/patches/rpi/rpi_181_269b48f50f4fd07067c9b47c557c20e524cbca71.patch --- linux-3.2.46/debian/patches/rpi/rpi_181_269b48f50f4fd07067c9b47c557c20e524cbca71.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_181_269b48f50f4fd07067c9b47c557c20e524cbca71.patch 2013-07-26 19:33:55.000000000 +0000 @@ -0,0 +1,251 @@ +commit 269b48f50f4fd07067c9b47c557c20e524cbca71 +Author: Number 27 +Date: Sun Jul 8 20:57:25 2012 +0100 + + Backport of Chris Boot's i2c and spi drivers. + +Index: linux-3.2.46/arch/arm/configs/bcmrpi_cutdown_defconfig +=================================================================== +--- linux-3.2.46.orig/arch/arm/configs/bcmrpi_cutdown_defconfig 2013-07-26 19:33:41.000000000 +0000 ++++ linux-3.2.46/arch/arm/configs/bcmrpi_cutdown_defconfig 2013-07-26 19:33:54.000000000 +0000 +@@ -550,3 +550,12 @@ + # CONFIG_CRYPTO_HW is not set + CONFIG_CRC_ITU_T=y + CONFIG_LIBCRC32C=y ++CONFIG_I2C=y ++CONFIG_I2C_BOARDINFO=y ++CONFIG_I2C_COMPAT=y ++CONFIG_I2C_CHARDEV=m ++CONFIG_I2C_HELPER_AUTO=y ++CONFIG_I2C_BCM2708=m ++CONFIG_SPI=y ++CONFIG_SPI_MASTER=y ++CONFIG_SPI_BCM2708=m +\ No newline at end of file +Index: linux-3.2.46/arch/arm/mach-bcm2708/bcm2708.c +=================================================================== +--- linux-3.2.46.orig/arch/arm/mach-bcm2708/bcm2708.c 2013-07-26 19:33:46.000000000 +0000 ++++ linux-3.2.46/arch/arm/mach-bcm2708/bcm2708.c 2013-07-26 19:33:54.000000000 +0000 +@@ -31,6 +31,7 @@ + #include + #include + #include ++#include + + #include + #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,38) +@@ -195,7 +196,6 @@ + + /* warning - the USB needs a clock > 34MHz */ + +-#ifdef CONFIG_MMC_BCM2708 + static struct clk sdhost_clk = { + #ifdef CONFIG_ARCH_BCM2708_CHIPIT + .rate = 4000000, /* 4MHz */ +@@ -203,7 +203,6 @@ + .rate = 250000000, /* 250MHz */ + #endif + }; +-#endif + + static struct clk_lookup lookups[] = { + { /* UART0 */ +@@ -219,6 +218,15 @@ + .dev_id = "bcm2708_mci.0", + .clk = &sdhost_clk, + #endif ++ }, { /* SPI */ ++ .dev_id = "bcm2708_spi.0", ++ .clk = &sdhost_clk, ++ }, { /* BSC0 */ ++ .dev_id = "bcm2708_i2c.0", ++ .clk = &sdhost_clk, ++ }, { /* BSC1 */ ++ .dev_id = "bcm2708_i2c.1", ++ .clk = &sdhost_clk, + } + }; + +@@ -461,6 +469,80 @@ + }, + }; + ++static struct resource bcm2708_spi_resources[] = { ++ { ++ .start = SPI0_BASE, ++ .end = SPI0_BASE + SZ_256 - 1, ++ .flags = IORESOURCE_MEM, ++ }, { ++ .start = IRQ_SPI, ++ .end = IRQ_SPI, ++ .flags = IORESOURCE_IRQ, ++ } ++}; ++ ++static struct platform_device bcm2708_spi_device = { ++ .name = "bcm2708_spi", ++ .id = 0, ++ .num_resources = ARRAY_SIZE(bcm2708_spi_resources), ++ .resource = bcm2708_spi_resources, ++}; ++ ++static struct spi_board_info bcm2708_spi_devices[] = { ++ { ++ .modalias = "spidev", ++ .max_speed_hz = 500000, ++ .bus_num = 0, ++ .chip_select = 0, ++ .mode = SPI_MODE_0, ++ }, { ++ .modalias = "spidev", ++ .max_speed_hz = 500000, ++ .bus_num = 0, ++ .chip_select = 1, ++ .mode = SPI_MODE_0, ++ } ++}; ++ ++static struct resource bcm2708_bsc0_resources[] = { ++ { ++ .start = BSC0_BASE, ++ .end = BSC0_BASE + SZ_256 - 1, ++ .flags = IORESOURCE_MEM, ++ }, { ++ .start = INTERRUPT_I2C, ++ .end = INTERRUPT_I2C, ++ .flags = IORESOURCE_IRQ, ++ } ++}; ++ ++static struct platform_device bcm2708_bsc0_device = { ++ .name = "bcm2708_i2c", ++ .id = 0, ++ .num_resources = ARRAY_SIZE(bcm2708_bsc0_resources), ++ .resource = bcm2708_bsc0_resources, ++}; ++ ++ ++static struct resource bcm2708_bsc1_resources[] = { ++ { ++ .start = BSC1_BASE, ++ .end = BSC1_BASE + SZ_256 - 1, ++ .flags = IORESOURCE_MEM, ++ }, { ++ .start = INTERRUPT_I2C, ++ .end = INTERRUPT_I2C, ++ .flags = IORESOURCE_IRQ, ++ } ++}; ++ ++static struct platform_device bcm2708_bsc1_device = { ++ .name = "bcm2708_i2c", ++ .id = 1, ++ .num_resources = ARRAY_SIZE(bcm2708_bsc1_resources), ++ .resource = bcm2708_bsc1_resources, ++}; ++ + int __init bcm_register_device(struct platform_device *pdev) + { + int ret; +@@ -513,6 +595,10 @@ + for (i = 0; i < ARRAY_SIZE(bcm2708_alsa_devices); i++) + bcm_register_device(&bcm2708_alsa_devices[i]); + ++ bcm_register_device(&bcm2708_spi_device); ++ bcm_register_device(&bcm2708_bsc0_device); ++ bcm_register_device(&bcm2708_bsc1_device); ++ + #ifdef CONFIG_BCM2708_VCMEM + { + extern void vc_mem_connected_init(void); +@@ -525,6 +611,11 @@ + } + system_rev = boardrev; + system_serial_low = serial; ++ ++#ifdef CONFIG_SPI ++ spi_register_board_info(bcm2708_spi_devices, ++ ARRAY_SIZE(bcm2708_spi_devices)); ++#endif + } + + #define TIMER_PERIOD 10000 /* HZ in microsecs */ +Index: linux-3.2.46/arch/arm/mach-bcm2708/include/mach/platform.h +=================================================================== +--- linux-3.2.46.orig/arch/arm/mach-bcm2708/include/mach/platform.h 2013-07-26 19:33:46.000000000 +0000 ++++ linux-3.2.46/arch/arm/mach-bcm2708/include/mach/platform.h 2013-07-26 19:33:54.000000000 +0000 +@@ -63,9 +63,12 @@ + #define GPIO_BASE (BCM2708_PERI_BASE + 0x200000) /* GPIO */ + #define UART0_BASE (BCM2708_PERI_BASE + 0x201000) /* Uart 0 */ + #define MMCI0_BASE (BCM2708_PERI_BASE + 0x202000) /* MMC interface */ ++#define SPI0_BASE (BCM2708_PERI_BASE + 0x204000) /* SPI0 */ ++#define BSC0_BASE (BCM2708_PERI_BASE + 0x205000) /* BSC0 I2C/TWI */ + #define UART1_BASE (BCM2708_PERI_BASE + 0x215000) /* Uart 1 */ + #define EMMC_BASE (BCM2708_PERI_BASE + 0x300000) /* eMMC interface */ + #define SMI_BASE (BCM2708_PERI_BASE + 0x600000) /* SMI */ ++#define BSC1_BASE (BCM2708_PERI_BASE + 0x804000) /* BSC1 I2C/TWI */ + #define USB_BASE (BCM2708_PERI_BASE + 0x980000) /* DTC_OTG USB controller */ + #define MCORE_BASE (BCM2708_PERI_BASE + 0x0000) /* Fake frame buffer device (actually the multicore sync block*/ + +Index: linux-3.2.46/drivers/i2c/busses/Kconfig +=================================================================== +--- linux-3.2.46.orig/drivers/i2c/busses/Kconfig 2013-05-30 13:35:16.000000000 +0000 ++++ linux-3.2.46/drivers/i2c/busses/Kconfig 2013-07-26 19:33:54.000000000 +0000 +@@ -310,6 +310,14 @@ + This driver can also be built as a module. If so, the module + will be called i2c-au1550. + ++config I2C_BCM2708 ++ tristate "BCM2708 BSC" ++ depends on MACH_BCM2708 ++ help ++ Enabling this option will add BSC (Broadcom Serial Controller) ++ support for the BCM2708. BSC is a Broadcom proprietary bus compatible ++ with I2C/TWI/SMBus. ++ + config I2C_BLACKFIN_TWI + tristate "Blackfin TWI I2C support" + depends on BLACKFIN +Index: linux-3.2.46/drivers/i2c/busses/Makefile +=================================================================== +--- linux-3.2.46.orig/drivers/i2c/busses/Makefile 2013-05-30 13:35:16.000000000 +0000 ++++ linux-3.2.46/drivers/i2c/busses/Makefile 2013-07-26 19:33:54.000000000 +0000 +@@ -30,6 +30,7 @@ + # Embedded system I2C/SMBus host controller drivers + obj-$(CONFIG_I2C_AT91) += i2c-at91.o + obj-$(CONFIG_I2C_AU1550) += i2c-au1550.o ++obj-$(CONFIG_I2C_BCM2708) += i2c-bcm2708.o + obj-$(CONFIG_I2C_BLACKFIN_TWI) += i2c-bfin-twi.o + obj-$(CONFIG_I2C_CPM) += i2c-cpm.o + obj-$(CONFIG_I2C_DAVINCI) += i2c-davinci.o +Index: linux-3.2.46/drivers/spi/Kconfig +=================================================================== +--- linux-3.2.46.orig/drivers/spi/Kconfig 2013-05-30 13:35:16.000000000 +0000 ++++ linux-3.2.46/drivers/spi/Kconfig 2013-07-26 19:33:54.000000000 +0000 +@@ -74,6 +74,14 @@ + This selects a driver for the Atmel SPI Controller, present on + many AT32 (AVR32) and AT91 (ARM) chips. + ++config SPI_BCM2708 ++ tristate "BCM2708 SPI controller driver (SPI0)" ++ depends on MACH_BCM2708 ++ help ++ This selects a driver for the Broadcom BCM2708 SPI master (SPI0). This ++ driver is not compatible with the "Universal SPI Master" or the SPI slave ++ device. ++ + config SPI_BFIN + tristate "SPI controller driver for ADI Blackfin5xx" + depends on BLACKFIN +Index: linux-3.2.46/drivers/spi/Makefile +=================================================================== +--- linux-3.2.46.orig/drivers/spi/Makefile 2013-05-30 13:35:16.000000000 +0000 ++++ linux-3.2.46/drivers/spi/Makefile 2013-07-26 19:33:54.000000000 +0000 +@@ -14,6 +14,7 @@ + obj-$(CONFIG_SPI_ATMEL) += spi-atmel.o + obj-$(CONFIG_SPI_ATH79) += spi-ath79.o + obj-$(CONFIG_SPI_AU1550) += spi-au1550.o ++obj-$(CONFIG_SPI_BCM2708) += spi-bcm2708.o + obj-$(CONFIG_SPI_BFIN) += spi-bfin5xx.o + obj-$(CONFIG_SPI_BFIN_SPORT) += spi-bfin-sport.o + obj-$(CONFIG_SPI_BITBANG) += spi-bitbang.o diff -Nru linux-3.2.46/debian/patches/rpi/rpi_182_6ba3db85388405df0b71da744943a7129827491f.patch linux-3.2.46/debian/patches/rpi/rpi_182_6ba3db85388405df0b71da744943a7129827491f.patch --- linux-3.2.46/debian/patches/rpi/rpi_182_6ba3db85388405df0b71da744943a7129827491f.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_182_6ba3db85388405df0b71da744943a7129827491f.patch 2013-07-26 19:33:56.000000000 +0000 @@ -0,0 +1,1006 @@ +commit 6ba3db85388405df0b71da744943a7129827491f +Author: Number 27 +Date: Sun Jul 8 21:39:42 2012 +0100 + + forgotten files.... + +Index: linux-3.2.46/drivers/i2c/busses/i2c-bcm2708.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/i2c/busses/i2c-bcm2708.c 2013-07-26 19:33:55.000000000 +0000 +@@ -0,0 +1,396 @@ ++/* ++ * Driver for Broadcom BCM2708 BSC Controllers ++ * ++ * Copyright (C) 2012 Chris Boot & Frank Buss ++ * ++ * This driver is inspired by: ++ * i2c-ocores.c, by Peter Korsgaard ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++/* BSC register offsets */ ++#define BSC_C 0x00 ++#define BSC_S 0x04 ++#define BSC_DLEN 0x08 ++#define BSC_A 0x0c ++#define BSC_FIFO 0x10 ++#define BSC_DIV 0x14 ++#define BSC_DEL 0x18 ++#define BSC_CLKT 0x1c ++ ++/* Bitfields in BSC_C */ ++#define BSC_C_I2CEN 0x00008000 ++#define BSC_C_INTR 0x00000400 ++#define BSC_C_INTT 0x00000200 ++#define BSC_C_INTD 0x00000100 ++#define BSC_C_ST 0x00000080 ++#define BSC_C_CLEAR_1 0x00000020 ++#define BSC_C_CLEAR_2 0x00000010 ++#define BSC_C_READ 0x00000001 ++ ++/* Bitfields in BSC_S */ ++#define BSC_S_CLKT 0x00000200 ++#define BSC_S_ERR 0x00000100 ++#define BSC_S_RXF 0x00000080 ++#define BSC_S_TXE 0x00000040 ++#define BSC_S_RXD 0x00000020 ++#define BSC_S_TXD 0x00000010 ++#define BSC_S_RXR 0x00000008 ++#define BSC_S_TXW 0x00000004 ++#define BSC_S_DONE 0x00000002 ++#define BSC_S_TA 0x00000001 ++ ++#define I2C_CLOCK_HZ 100000 /* FIXME: get from DT */ ++#define I2C_TIMEOUT_MS 150 ++ ++#define DRV_NAME "bcm2708_i2c" ++ ++struct bcm2708_i2c { ++ struct i2c_adapter adapter; ++ ++ spinlock_t lock; ++ void __iomem *base; ++ int irq; ++ struct clk *clk; ++ ++ struct completion done; ++ ++ struct i2c_msg *msg; ++ int pos; ++ int nmsgs; ++ bool error; ++}; ++ ++/* ++ * This function sets the ALT mode on the I2C pins so that we can use them with ++ * the BSC hardware. ++ * ++ * FIXME: This is a hack. Use pinmux / pinctrl. ++ */ ++static void bcm2708_i2c_init_pinmode(void) ++{ ++#define INP_GPIO(g) *(gpio+((g)/10)) &= ~(7<<(((g)%10)*3)) ++#define SET_GPIO_ALT(g,a) *(gpio+(((g)/10))) |= (((a)<=3?(a)+4:(a)==4?3:2)<<(((g)%10)*3)) ++ ++ int pin; ++ u32 *gpio = ioremap(0x20200000, SZ_16K); ++ ++ /* BSC0 is on GPIO 0 & 1, BSC1 is on GPIO 2 & 3 */ ++ for (pin = 0; pin <= 3; pin++) { ++ INP_GPIO(pin); /* set mode to GPIO input first */ ++ SET_GPIO_ALT(pin, 0); /* set mode to ALT 0 */ ++ } ++ ++ iounmap(gpio); ++ ++#undef INP_GPIO ++#undef SET_GPIO_ALT ++} ++ ++static inline u32 bcm2708_rd(struct bcm2708_i2c *bi, unsigned reg) ++{ ++ return readl(bi->base + reg); ++} ++ ++static inline void bcm2708_wr(struct bcm2708_i2c *bi, unsigned reg, u32 val) ++{ ++ writel(val, bi->base + reg); ++} ++ ++static inline void bcm2708_bsc_reset(struct bcm2708_i2c *bi) ++{ ++ bcm2708_wr(bi, BSC_C, 0); ++ bcm2708_wr(bi, BSC_S, BSC_S_CLKT | BSC_S_ERR | BSC_S_DONE); ++} ++ ++static inline void bcm2708_bsc_fifo_drain(struct bcm2708_i2c *bi) ++{ ++ while ((bcm2708_rd(bi, BSC_S) & BSC_S_RXD) && (bi->pos < bi->msg->len)) ++ bi->msg->buf[bi->pos++] = bcm2708_rd(bi, BSC_FIFO); ++} ++ ++static inline void bcm2708_bsc_fifo_fill(struct bcm2708_i2c *bi) ++{ ++ while ((bcm2708_rd(bi, BSC_S) & BSC_S_TXD) && (bi->pos < bi->msg->len)) ++ bcm2708_wr(bi, BSC_FIFO, bi->msg->buf[bi->pos++]); ++} ++ ++static inline void bcm2708_bsc_setup(struct bcm2708_i2c *bi) ++{ ++ unsigned long bus_hz; ++ u32 cdiv; ++ u32 c = BSC_C_I2CEN | BSC_C_INTD | BSC_C_ST | BSC_C_CLEAR_1; ++ ++ bus_hz = clk_get_rate(bi->clk); ++ cdiv = bus_hz / I2C_CLOCK_HZ; ++ ++ if (bi->msg->flags & I2C_M_RD) ++ c |= BSC_C_INTR | BSC_C_READ; ++ else ++ c |= BSC_C_INTT; ++ ++ bcm2708_wr(bi, BSC_DIV, cdiv); ++ bcm2708_wr(bi, BSC_A, bi->msg->addr); ++ bcm2708_wr(bi, BSC_DLEN, bi->msg->len); ++ bcm2708_wr(bi, BSC_C, c); ++} ++ ++static irqreturn_t bcm2708_i2c_interrupt(int irq, void *dev_id) ++{ ++ struct bcm2708_i2c *bi = dev_id; ++ bool handled = true; ++ u32 s; ++ ++ spin_lock(&bi->lock); ++ ++ s = bcm2708_rd(bi, BSC_S); ++ ++ if (s & (BSC_S_CLKT | BSC_S_ERR)) { ++ bcm2708_bsc_reset(bi); ++ bi->error = true; ++ ++ /* wake up our bh */ ++ complete(&bi->done); ++ } else if (s & BSC_S_DONE) { ++ bi->nmsgs--; ++ ++ if (bi->msg->flags & I2C_M_RD) ++ bcm2708_bsc_fifo_drain(bi); ++ ++ bcm2708_bsc_reset(bi); ++ ++ if (bi->nmsgs) { ++ /* advance to next message */ ++ bi->msg++; ++ bi->pos = 0; ++ bcm2708_bsc_setup(bi); ++ } else { ++ /* wake up our bh */ ++ complete(&bi->done); ++ } ++ } else if (s & BSC_S_TXW) { ++ bcm2708_bsc_fifo_fill(bi); ++ } else if (s & BSC_S_RXR) { ++ bcm2708_bsc_fifo_drain(bi); ++ } else { ++ handled = false; ++ } ++ ++ spin_unlock(&bi->lock); ++ ++ return handled ? IRQ_HANDLED : IRQ_NONE; ++} ++ ++static int bcm2708_i2c_master_xfer(struct i2c_adapter *adap, ++ struct i2c_msg *msgs, int num) ++{ ++ struct bcm2708_i2c *bi = adap->algo_data; ++ unsigned long flags; ++ int ret; ++ ++ spin_lock_irqsave(&bi->lock, flags); ++ ++ INIT_COMPLETION(bi->done); ++ bi->msg = msgs; ++ bi->pos = 0; ++ bi->nmsgs = num; ++ bi->error = false; ++ ++ spin_unlock_irqrestore(&bi->lock, flags); ++ ++ bcm2708_bsc_setup(bi); ++ ++ ret = wait_for_completion_timeout(&bi->done, ++ msecs_to_jiffies(I2C_TIMEOUT_MS)); ++ if (ret == 0) { ++ dev_err(&adap->dev, "transfer timed out\n"); ++ spin_lock_irqsave(&bi->lock, flags); ++ bcm2708_bsc_reset(bi); ++ spin_unlock_irqrestore(&bi->lock, flags); ++ return -ETIMEDOUT; ++ } ++ ++ return bi->error ? -EIO : num; ++} ++ ++static u32 bcm2708_i2c_functionality(struct i2c_adapter *adap) ++{ ++ return I2C_FUNC_I2C | /*I2C_FUNC_10BIT_ADDR |*/ I2C_FUNC_SMBUS_EMUL; ++} ++ ++static struct i2c_algorithm bcm2708_i2c_algorithm = { ++ .master_xfer = bcm2708_i2c_master_xfer, ++ .functionality = bcm2708_i2c_functionality, ++}; ++ ++static int __devinit bcm2708_i2c_probe(struct platform_device *pdev) ++{ ++ struct resource *regs; ++ int irq, err = -ENOMEM; ++ struct clk *clk; ++ struct bcm2708_i2c *bi; ++ struct i2c_adapter *adap; ++ ++ regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ if (!regs) { ++ dev_err(&pdev->dev, "could not get IO memory\n"); ++ return -ENXIO; ++ } ++ ++ irq = platform_get_irq(pdev, 0); ++ if (irq < 0) { ++ dev_err(&pdev->dev, "could not get IRQ\n"); ++ return irq; ++ } ++ ++ clk = clk_get(&pdev->dev, NULL); ++ if (IS_ERR(clk)) { ++ dev_err(&pdev->dev, "could not find clk: %ld\n", PTR_ERR(clk)); ++ return PTR_ERR(clk); ++ } ++ ++ bcm2708_i2c_init_pinmode(); ++ ++ bi = kzalloc(sizeof(*bi), GFP_KERNEL); ++ if (!bi) ++ goto out_clk_put; ++ ++ platform_set_drvdata(pdev, bi); ++ ++ adap = &bi->adapter; ++ adap->class = I2C_CLASS_HWMON | I2C_CLASS_DDC; ++ adap->algo = &bcm2708_i2c_algorithm; ++ adap->algo_data = bi; ++ adap->dev.parent = &pdev->dev; ++ adap->nr = pdev->id; ++ strlcpy(adap->name, dev_name(&pdev->dev), sizeof(adap->name)); ++ ++ switch (pdev->id) { ++ case 0: ++ adap->class = I2C_CLASS_HWMON; ++ break; ++ case 1: ++ adap->class = I2C_CLASS_DDC; ++ break; ++ default: ++ dev_err(&pdev->dev, "can only bind to BSC 0 or 1\n"); ++ err = -ENXIO; ++ goto out_free_bi; ++ } ++ ++ spin_lock_init(&bi->lock); ++ init_completion(&bi->done); ++ ++ bi->base = ioremap(regs->start, resource_size(regs)); ++ if (!bi->base) { ++ dev_err(&pdev->dev, "could not remap memory\n"); ++ goto out_free_bi; ++ } ++ ++ bi->irq = irq; ++ bi->clk = clk; ++ ++ err = request_irq(irq, bcm2708_i2c_interrupt, IRQF_SHARED, ++ dev_name(&pdev->dev), bi); ++ if (err) { ++ dev_err(&pdev->dev, "could not request IRQ: %d\n", err); ++ goto out_iounmap; ++ } ++ ++ bcm2708_bsc_reset(bi); ++ ++ err = i2c_add_numbered_adapter(adap); ++ if (err < 0) { ++ dev_err(&pdev->dev, "could not add I2C adapter: %d\n", err); ++ goto out_free_irq; ++ } ++ ++ dev_info(&pdev->dev, "BSC%d Controller at 0x%08lx (irq %d)\n", ++ pdev->id, (unsigned long)regs->start, irq); ++ ++ return 0; ++ ++out_free_irq: ++ free_irq(bi->irq, bi); ++out_iounmap: ++ iounmap(bi->base); ++out_free_bi: ++ kfree(bi); ++out_clk_put: ++ clk_put(clk); ++ return err; ++} ++ ++static int __devexit bcm2708_i2c_remove(struct platform_device *pdev) ++{ ++ struct bcm2708_i2c *bi = platform_get_drvdata(pdev); ++ ++ platform_set_drvdata(pdev, NULL); ++ ++ i2c_del_adapter(&bi->adapter); ++ free_irq(bi->irq, bi); ++ iounmap(bi->base); ++ clk_disable(bi->clk); ++ clk_put(bi->clk); ++ kfree(bi); ++ ++ return 0; ++} ++ ++static struct platform_driver bcm2708_i2c_driver = { ++ .driver = { ++ .name = DRV_NAME, ++ .owner = THIS_MODULE, ++ }, ++ .probe = bcm2708_i2c_probe, ++ .remove = __devexit_p(bcm2708_i2c_remove), ++}; ++ ++// module_platform_driver(bcm2708_i2c_driver); ++ ++ ++static int __init bcm2708_i2c_init(void) ++{ ++ return platform_driver_register(&bcm2708_i2c_driver); ++} ++ ++static void __exit bcm2708_i2c_exit(void) ++{ ++ platform_driver_unregister(&bcm2708_i2c_driver); ++} ++ ++module_init(bcm2708_i2c_init); ++module_exit(bcm2708_i2c_exit); ++ ++ ++ ++MODULE_DESCRIPTION("BSC controller driver for Broadcom BCM2708"); ++MODULE_AUTHOR("Chris Boot "); ++MODULE_LICENSE("GPL v2"); ++MODULE_ALIAS("platform:" DRV_NAME); +Index: linux-3.2.46/drivers/spi/spi-bcm2708.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/spi/spi-bcm2708.c 2013-07-26 19:33:55.000000000 +0000 +@@ -0,0 +1,594 @@ ++/* ++ * Driver for Broadcom BCM2708 SPI Controllers ++ * ++ * Copyright (C) 2012 Chris Boot ++ * ++ * This driver is inspired by: ++ * spi-ath79.c, Copyright (C) 2009-2011 Gabor Juhos ++ * spi-atmel.c, Copyright (C) 2006 Atmel Corporation ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++/* SPI register offsets */ ++#define SPI_CS 0x00 ++#define SPI_FIFO 0x04 ++#define SPI_CLK 0x08 ++#define SPI_DLEN 0x0c ++#define SPI_LTOH 0x10 ++#define SPI_DC 0x14 ++ ++/* Bitfields in CS */ ++#define SPI_CS_LEN_LONG 0x02000000 ++#define SPI_CS_DMA_LEN 0x01000000 ++#define SPI_CS_CSPOL2 0x00800000 ++#define SPI_CS_CSPOL1 0x00400000 ++#define SPI_CS_CSPOL0 0x00200000 ++#define SPI_CS_RXF 0x00100000 ++#define SPI_CS_RXR 0x00080000 ++#define SPI_CS_TXD 0x00040000 ++#define SPI_CS_RXD 0x00020000 ++#define SPI_CS_DONE 0x00010000 ++#define SPI_CS_LEN 0x00002000 ++#define SPI_CS_REN 0x00001000 ++#define SPI_CS_ADCS 0x00000800 ++#define SPI_CS_INTR 0x00000400 ++#define SPI_CS_INTD 0x00000200 ++#define SPI_CS_DMAEN 0x00000100 ++#define SPI_CS_TA 0x00000080 ++#define SPI_CS_CSPOL 0x00000040 ++#define SPI_CS_CLEAR_RX 0x00000020 ++#define SPI_CS_CLEAR_TX 0x00000010 ++#define SPI_CS_CPOL 0x00000008 ++#define SPI_CS_CPHA 0x00000004 ++#define SPI_CS_CS_10 0x00000002 ++#define SPI_CS_CS_01 0x00000001 ++ ++#define SPI_TIMEOUT_MS 150 ++ ++#define DRV_NAME "bcm2708_spi" ++ ++struct bcm2708_spi { ++ spinlock_t lock; ++ void __iomem *base; ++ int irq; ++ struct clk *clk; ++ bool stopping; ++ ++ struct list_head queue; ++ struct workqueue_struct *workq; ++ struct work_struct work; ++ struct completion done; ++ ++ const u8 *tx_buf; ++ u8 *rx_buf; ++ int len; ++}; ++ ++struct bcm2708_spi_state { ++ u32 cs; ++ u16 cdiv; ++}; ++ ++/* ++ * This function sets the ALT mode on the SPI pins so that we can use them with ++ * the SPI hardware. ++ * ++ * FIXME: This is a hack. Use pinmux / pinctrl. ++ */ ++static void bcm2708_init_pinmode(void) ++{ ++#define INP_GPIO(g) *(gpio+((g)/10)) &= ~(7<<(((g)%10)*3)) ++#define SET_GPIO_ALT(g,a) *(gpio+(((g)/10))) |= (((a)<=3?(a)+4:(a)==4?3:2)<<(((g)%10)*3)) ++ ++ int pin; ++ u32 *gpio = ioremap(0x20200000, SZ_16K); ++ ++ /* SPI is on GPIO 7..11 */ ++ for (pin = 7; pin <= 11; pin++) { ++ INP_GPIO(pin); /* set mode to GPIO input first */ ++ SET_GPIO_ALT(pin, 0); /* set mode to ALT 0 */ ++ } ++ ++ iounmap(gpio); ++ ++#undef INP_GPIO ++#undef SET_GPIO_ALT ++} ++ ++static inline u32 bcm2708_rd(struct bcm2708_spi *bs, unsigned reg) ++{ ++ return readl(bs->base + reg); ++} ++ ++static inline void bcm2708_wr(struct bcm2708_spi *bs, unsigned reg, u32 val) ++{ ++ writel(val, bs->base + reg); ++} ++ ++static inline void bcm2708_rd_fifo(struct bcm2708_spi *bs, int len) ++{ ++ u8 byte; ++ ++ while (len--) { ++ byte = bcm2708_rd(bs, SPI_FIFO); ++ if (bs->rx_buf) ++ *bs->rx_buf++ = byte; ++ } ++} ++ ++static inline void bcm2708_wr_fifo(struct bcm2708_spi *bs, int len) ++{ ++ u8 byte; ++ ++ if (len > bs->len) ++ len = bs->len; ++ ++ while (len--) { ++ byte = bs->tx_buf ? *bs->tx_buf++ : 0; ++ bcm2708_wr(bs, SPI_FIFO, byte); ++ bs->len--; ++ } ++} ++ ++static irqreturn_t bcm2708_spi_interrupt(int irq, void *dev_id) ++{ ++ struct spi_master *master = dev_id; ++ struct bcm2708_spi *bs = spi_master_get_devdata(master); ++ u32 cs; ++ ++ spin_lock(&bs->lock); ++ ++ cs = bcm2708_rd(bs, SPI_CS); ++ ++ if (cs & SPI_CS_DONE) { ++ if (bs->len) { /* first interrupt in a transfer */ ++ /* fill the TX fifo with up to 16 bytes */ ++ bcm2708_wr_fifo(bs, 16); ++ } else { /* transfer complete */ ++ /* disable interrupts */ ++ cs &= ~(SPI_CS_INTR | SPI_CS_INTD); ++ bcm2708_wr(bs, SPI_CS, cs); ++ ++ /* drain RX FIFO */ ++ while (cs & SPI_CS_RXD) { ++ bcm2708_rd_fifo(bs, 1); ++ cs = bcm2708_rd(bs, SPI_CS); ++ } ++ ++ /* wake up our bh */ ++ complete(&bs->done); ++ } ++ } else if (cs & SPI_CS_RXR) { ++ /* read 12 bytes of data */ ++ bcm2708_rd_fifo(bs, 12); ++ ++ /* write up to 12 bytes */ ++ bcm2708_wr_fifo(bs, 12); ++ } ++ ++ spin_unlock(&bs->lock); ++ ++ return IRQ_HANDLED; ++} ++ ++static int bcm2708_setup_state(struct spi_master *master, ++ struct device *dev, struct bcm2708_spi_state *state, ++ u32 hz, u8 csel, u8 mode, u8 bpw) ++{ ++ struct bcm2708_spi *bs = spi_master_get_devdata(master); ++ int cdiv; ++ unsigned long bus_hz; ++ u32 cs = 0; ++ ++ bus_hz = clk_get_rate(bs->clk); ++ ++ if (hz >= bus_hz) { ++ cdiv = 2; /* bus_hz / 2 is as fast as we can go */ ++ } else if (hz) { ++ cdiv = DIV_ROUND_UP(bus_hz, hz); ++ ++ /* CDIV must be a power of 2, so round up */ ++ cdiv = roundup_pow_of_two(cdiv); ++ ++ if (cdiv > 65536) { ++ dev_dbg(dev, ++ "setup: %d Hz too slow, cdiv %u; min %ld Hz\n", ++ hz, cdiv, bus_hz / 65536); ++ return -EINVAL; ++ } else if (cdiv == 65536) { ++ cdiv = 0; ++ } else if (cdiv == 1) { ++ cdiv = 2; /* 1 gets rounded down to 0; == 65536 */ ++ } ++ } else { ++ cdiv = 0; ++ } ++ ++ switch (bpw) { ++ case 8: ++ break; ++ default: ++ dev_dbg(dev, "setup: invalid bits_per_word %u (must be 8)\n", ++ bpw); ++ return -EINVAL; ++ } ++ ++ if (mode & SPI_CPOL) ++ cs |= SPI_CS_CPOL; ++ if (mode & SPI_CPHA) ++ cs |= SPI_CS_CPHA; ++ ++ if (!(mode & SPI_NO_CS)) { ++ if (mode & SPI_CS_HIGH) { ++ cs |= SPI_CS_CSPOL; ++ cs |= SPI_CS_CSPOL0 << csel; ++ } ++ ++ cs |= csel; ++ } else { ++ cs |= SPI_CS_CS_10 | SPI_CS_CS_01; ++ } ++ ++ if (state) { ++ state->cs = cs; ++ state->cdiv = cdiv; ++ } ++ ++ return 0; ++} ++ ++static int bcm2708_process_transfer(struct bcm2708_spi *bs, ++ struct spi_message *msg, struct spi_transfer *xfer) ++{ ++ struct spi_device *spi = msg->spi; ++ struct bcm2708_spi_state state, *stp; ++ int ret; ++ u32 cs; ++ ++ if (bs->stopping) ++ return -ESHUTDOWN; ++ ++ if (xfer->bits_per_word || xfer->speed_hz) { ++ ret = bcm2708_setup_state(spi->master, &spi->dev, &state, ++ spi->max_speed_hz, spi->chip_select, spi->mode, ++ spi->bits_per_word); ++ if (ret) ++ return ret; ++ ++ stp = &state; ++ } else { ++ stp = spi->controller_state; ++ } ++ ++ INIT_COMPLETION(bs->done); ++ bs->tx_buf = xfer->tx_buf; ++ bs->rx_buf = xfer->rx_buf; ++ bs->len = xfer->len; ++ ++ cs = stp->cs | SPI_CS_INTR | SPI_CS_INTD | SPI_CS_TA; ++ ++ bcm2708_wr(bs, SPI_CLK, stp->cdiv); ++ bcm2708_wr(bs, SPI_CS, cs); ++ ++ ret = wait_for_completion_timeout(&bs->done, ++ msecs_to_jiffies(SPI_TIMEOUT_MS)); ++ if (ret == 0) { ++ dev_err(&spi->dev, "transfer timed out\n"); ++ return -ETIMEDOUT; ++ } ++ ++ if (xfer->delay_usecs) ++ udelay(xfer->delay_usecs); ++ ++ if (list_is_last(&xfer->transfer_list, &msg->transfers) || ++ xfer->cs_change) { ++ /* clear TA and interrupt flags */ ++ bcm2708_wr(bs, SPI_CS, stp->cs); ++ } ++ ++ msg->actual_length += (xfer->len - bs->len); ++ ++ return 0; ++} ++ ++static void bcm2708_work(struct work_struct *work) ++{ ++ struct bcm2708_spi *bs = container_of(work, struct bcm2708_spi, work); ++ unsigned long flags; ++ struct spi_message *msg; ++ struct spi_transfer *xfer; ++ int status = 0; ++ ++ spin_lock_irqsave(&bs->lock, flags); ++ while (!list_empty(&bs->queue)) { ++ msg = list_first_entry(&bs->queue, struct spi_message, queue); ++ list_del_init(&msg->queue); ++ spin_unlock_irqrestore(&bs->lock, flags); ++ ++ list_for_each_entry(xfer, &msg->transfers, transfer_list) { ++ status = bcm2708_process_transfer(bs, msg, xfer); ++ if (status) ++ break; ++ } ++ ++ msg->status = status; ++ msg->complete(msg->context); ++ ++ spin_lock_irqsave(&bs->lock, flags); ++ } ++ spin_unlock_irqrestore(&bs->lock, flags); ++} ++ ++static int bcm2708_spi_setup(struct spi_device *spi) ++{ ++ struct bcm2708_spi *bs = spi_master_get_devdata(spi->master); ++ struct bcm2708_spi_state *state; ++ int ret; ++ ++ if (bs->stopping) ++ return -ESHUTDOWN; ++ ++ if (!(spi->mode & SPI_NO_CS) && ++ (spi->chip_select > spi->master->num_chipselect)) { ++ dev_dbg(&spi->dev, ++ "setup: invalid chipselect %u (%u defined)\n", ++ spi->chip_select, spi->master->num_chipselect); ++ return -EINVAL; ++ } ++ ++ state = spi->controller_state; ++ if (!state) { ++ state = kzalloc(sizeof(*state), GFP_KERNEL); ++ if (!state) ++ return -ENOMEM; ++ ++ spi->controller_state = state; ++ } ++ ++ ret = bcm2708_setup_state(spi->master, &spi->dev, state, ++ spi->max_speed_hz, spi->chip_select, spi->mode, ++ spi->bits_per_word); ++ if (ret < 0) { ++ kfree(state); ++ spi->controller_state = NULL; ++ } ++ ++ dev_dbg(&spi->dev, ++ "setup: cd %d: %d Hz, bpw %u, mode 0x%x -> CS=%08x CDIV=%04x\n", ++ spi->chip_select, spi->max_speed_hz, spi->bits_per_word, ++ spi->mode, state->cs, state->cdiv); ++ ++ return 0; ++} ++ ++static int bcm2708_spi_transfer(struct spi_device *spi, struct spi_message *msg) ++{ ++ struct bcm2708_spi *bs = spi_master_get_devdata(spi->master); ++ struct spi_transfer *xfer; ++ int ret; ++ unsigned long flags; ++ ++ if (unlikely(list_empty(&msg->transfers))) ++ return -EINVAL; ++ ++ if (bs->stopping) ++ return -ESHUTDOWN; ++ ++ list_for_each_entry(xfer, &msg->transfers, transfer_list) { ++ if (!(xfer->tx_buf || xfer->rx_buf) && xfer->len) { ++ dev_dbg(&spi->dev, "missing rx or tx buf\n"); ++ return -EINVAL; ++ } ++ ++ if (!xfer->bits_per_word || xfer->speed_hz) ++ continue; ++ ++ ret = bcm2708_setup_state(spi->master, &spi->dev, NULL, ++ xfer->speed_hz ? xfer->speed_hz : spi->max_speed_hz, ++ spi->chip_select, spi->mode, ++ xfer->bits_per_word ? xfer->bits_per_word : ++ spi->bits_per_word); ++ if (ret) ++ return ret; ++ } ++ ++ msg->status = -EINPROGRESS; ++ msg->actual_length = 0; ++ ++ spin_lock_irqsave(&bs->lock, flags); ++ list_add_tail(&msg->queue, &bs->queue); ++ queue_work(bs->workq, &bs->work); ++ spin_unlock_irqrestore(&bs->lock, flags); ++ ++ return 0; ++} ++ ++static void bcm2708_spi_cleanup(struct spi_device *spi) ++{ ++ if (spi->controller_state) { ++ kfree(spi->controller_state); ++ spi->controller_state = NULL; ++ } ++} ++ ++static int __devinit bcm2708_spi_probe(struct platform_device *pdev) ++{ ++ struct resource *regs; ++ int irq, err = -ENOMEM; ++ struct clk *clk; ++ struct spi_master *master; ++ struct bcm2708_spi *bs; ++ ++ regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ if (!regs) { ++ dev_err(&pdev->dev, "could not get IO memory\n"); ++ return -ENXIO; ++ } ++ ++ irq = platform_get_irq(pdev, 0); ++ if (irq < 0) { ++ dev_err(&pdev->dev, "could not get IRQ\n"); ++ return irq; ++ } ++ ++ clk = clk_get(&pdev->dev, NULL); ++ if (IS_ERR(clk)) { ++ dev_err(&pdev->dev, "could not find clk: %ld\n", PTR_ERR(clk)); ++ return PTR_ERR(clk); ++ } ++ ++ bcm2708_init_pinmode(); ++ ++ master = spi_alloc_master(&pdev->dev, sizeof(*bs)); ++ if (!master) { ++ dev_err(&pdev->dev, "spi_alloc_master() failed\n"); ++ goto out_clk_put; ++ } ++ ++ /* the spi->mode bits understood by this driver: */ ++ master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_NO_CS; ++ ++ master->bus_num = pdev->id; ++ master->num_chipselect = 3; ++ master->setup = bcm2708_spi_setup; ++ master->transfer = bcm2708_spi_transfer; ++ master->cleanup = bcm2708_spi_cleanup; ++ platform_set_drvdata(pdev, master); ++ ++ bs = spi_master_get_devdata(master); ++ ++ spin_lock_init(&bs->lock); ++ INIT_LIST_HEAD(&bs->queue); ++ init_completion(&bs->done); ++ INIT_WORK(&bs->work, bcm2708_work); ++ ++ bs->base = ioremap(regs->start, resource_size(regs)); ++ if (!bs->base) { ++ dev_err(&pdev->dev, "could not remap memory\n"); ++ goto out_master_put; ++ } ++ ++ bs->workq = create_singlethread_workqueue(dev_name(&pdev->dev)); ++ if (!bs->workq) { ++ dev_err(&pdev->dev, "could not create workqueue\n"); ++ goto out_iounmap; ++ } ++ ++ bs->irq = irq; ++ bs->clk = clk; ++ bs->stopping = false; ++ ++ err = request_irq(irq, bcm2708_spi_interrupt, 0, dev_name(&pdev->dev), ++ master); ++ if (err) { ++ dev_err(&pdev->dev, "could not request IRQ: %d\n", err); ++ goto out_workqueue; ++ } ++ ++ /* initialise the hardware */ ++ clk_enable(clk); ++ bcm2708_wr(bs, SPI_CS, SPI_CS_REN | SPI_CS_CLEAR_RX | SPI_CS_CLEAR_TX); ++ ++ err = spi_register_master(master); ++ if (err) { ++ dev_err(&pdev->dev, "could not register SPI master: %d\n", err); ++ goto out_free_irq; ++ } ++ ++ dev_info(&pdev->dev, "SPI Controller at 0x%08lx (irq %d)\n", ++ (unsigned long)regs->start, irq); ++ ++ return 0; ++ ++out_free_irq: ++ free_irq(bs->irq, master); ++out_workqueue: ++ destroy_workqueue(bs->workq); ++out_iounmap: ++ iounmap(bs->base); ++out_master_put: ++ spi_master_put(master); ++out_clk_put: ++ clk_put(clk); ++ return err; ++} ++ ++static int __devexit bcm2708_spi_remove(struct platform_device *pdev) ++{ ++ struct spi_master *master = platform_get_drvdata(pdev); ++ struct bcm2708_spi *bs = spi_master_get_devdata(master); ++ ++ /* reset the hardware and block queue progress */ ++ spin_lock_irq(&bs->lock); ++ bs->stopping = true; ++ bcm2708_wr(bs, SPI_CS, SPI_CS_CLEAR_RX | SPI_CS_CLEAR_TX); ++ spin_unlock_irq(&bs->lock); ++ ++ flush_work_sync(&bs->work); ++ ++ clk_disable(bs->clk); ++ clk_put(bs->clk); ++ free_irq(bs->irq, master); ++ iounmap(bs->base); ++ ++ spi_unregister_master(master); ++ ++ return 0; ++} ++ ++static struct platform_driver bcm2708_spi_driver = { ++ .driver = { ++ .name = DRV_NAME, ++ .owner = THIS_MODULE, ++ }, ++ .probe = bcm2708_spi_probe, ++ .remove = __devexit_p(bcm2708_spi_remove), ++}; ++ ++ ++static int __init bcm2708_spi_init(void) ++{ ++ return platform_driver_probe(&bcm2708_spi_driver, bcm2708_spi_probe); ++} ++module_init(bcm2708_spi_init); ++ ++static void __exit bcm2708_spi_exit(void) ++{ ++ platform_driver_unregister(&bcm2708_spi_driver); ++} ++module_exit(bcm2708_spi_exit); ++ ++ ++//module_platform_driver(bcm2708_spi_driver); ++ ++MODULE_DESCRIPTION("SPI controller driver for Broadcom BCM2708"); ++MODULE_AUTHOR("Chris Boot "); ++MODULE_LICENSE("GPL v2"); ++MODULE_ALIAS("platform:" DRV_NAME); diff -Nru linux-3.2.46/debian/patches/rpi/rpi_183_d32ab7b3e6d8c203543750dbc5c76980baaa17c3.patch linux-3.2.46/debian/patches/rpi/rpi_183_d32ab7b3e6d8c203543750dbc5c76980baaa17c3.patch --- linux-3.2.46/debian/patches/rpi/rpi_183_d32ab7b3e6d8c203543750dbc5c76980baaa17c3.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_183_d32ab7b3e6d8c203543750dbc5c76980baaa17c3.patch 2013-07-26 19:33:58.000000000 +0000 @@ -0,0 +1,40 @@ +commit d32ab7b3e6d8c203543750dbc5c76980baaa17c3 +Author: popcornmix +Date: Mon Jul 9 12:19:26 2012 +0100 + + Enable I2C and SPI modules in full config + +Index: linux-3.2.46/arch/arm/configs/bcmrpi_cutdown_defconfig +=================================================================== +--- linux-3.2.46.orig/arch/arm/configs/bcmrpi_cutdown_defconfig 2013-07-26 19:33:54.000000000 +0000 ++++ linux-3.2.46/arch/arm/configs/bcmrpi_cutdown_defconfig 2013-07-26 19:33:57.000000000 +0000 +@@ -550,12 +550,3 @@ + # CONFIG_CRYPTO_HW is not set + CONFIG_CRC_ITU_T=y + CONFIG_LIBCRC32C=y +-CONFIG_I2C=y +-CONFIG_I2C_BOARDINFO=y +-CONFIG_I2C_COMPAT=y +-CONFIG_I2C_CHARDEV=m +-CONFIG_I2C_HELPER_AUTO=y +-CONFIG_I2C_BCM2708=m +-CONFIG_SPI=y +-CONFIG_SPI_MASTER=y +-CONFIG_SPI_BCM2708=m +\ No newline at end of file +Index: linux-3.2.46/arch/arm/configs/bcmrpi_defconfig +=================================================================== +--- linux-3.2.46.orig/arch/arm/configs/bcmrpi_defconfig 2013-07-26 19:33:44.000000000 +0000 ++++ linux-3.2.46/arch/arm/configs/bcmrpi_defconfig 2013-07-26 19:33:57.000000000 +0000 +@@ -381,6 +381,11 @@ + CONFIG_TTY_PRINTK=y + # CONFIG_HW_RANDOM is not set + CONFIG_RAW_DRIVER=y ++CONFIG_I2C=y ++CONFIG_I2C_CHARDEV=m ++CONFIG_I2C_BCM2708=m ++CONFIG_SPI=y ++CONFIG_SPI_BCM2708=m + CONFIG_GPIO_SYSFS=y + # CONFIG_HWMON is not set + CONFIG_WATCHDOG=y diff -Nru linux-3.2.46/debian/patches/rpi/rpi_184_4c1987976a7498bf12bbf9840f9199af03a08993.patch linux-3.2.46/debian/patches/rpi/rpi_184_4c1987976a7498bf12bbf9840f9199af03a08993.patch --- linux-3.2.46/debian/patches/rpi/rpi_184_4c1987976a7498bf12bbf9840f9199af03a08993.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_184_4c1987976a7498bf12bbf9840f9199af03a08993.patch 2013-07-26 19:33:59.000000000 +0000 @@ -0,0 +1,32 @@ +commit 4c1987976a7498bf12bbf9840f9199af03a08993 +Author: popcornmix +Date: Tue Jul 10 00:14:48 2012 +0100 + + Possible fix for failure to boot with compressed kernels + +Index: linux-3.2.46/arch/arm/mach-bcm2708/include/mach/uncompress.h +=================================================================== +--- linux-3.2.46.orig/arch/arm/mach-bcm2708/include/mach/uncompress.h 2013-07-26 19:31:51.000000000 +0000 ++++ linux-3.2.46/arch/arm/mach-bcm2708/include/mach/uncompress.h 2013-07-26 19:33:58.000000000 +0000 +@@ -20,6 +20,7 @@ + */ + + #include ++#include + #include + + #define BCM2708_UART_DR __io_address(UART0_BASE + 0x00) +@@ -38,8 +39,12 @@ + + static inline void flush(void) + { +- while (readl(BCM2708_UART_FR) & (1 << 3)) ++ int fr; ++ ++ do { ++ fr = __raw_readl(BCM2708_UART_FR); + barrier(); ++ } while ((fr & (UART011_FR_TXFE | UART01x_FR_BUSY)) != UART011_FR_TXFE); + } + + /* diff -Nru linux-3.2.46/debian/patches/rpi/rpi_185_61923058dee45d1da0d90fe1c1a7848ba72dab81.patch linux-3.2.46/debian/patches/rpi/rpi_185_61923058dee45d1da0d90fe1c1a7848ba72dab81.patch --- linux-3.2.46/debian/patches/rpi/rpi_185_61923058dee45d1da0d90fe1c1a7848ba72dab81.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_185_61923058dee45d1da0d90fe1c1a7848ba72dab81.patch 2013-07-26 19:34:00.000000000 +0000 @@ -0,0 +1,74 @@ +commit 61923058dee45d1da0d90fe1c1a7848ba72dab81 +Author: popcornmix +Date: Wed Jul 11 00:29:52 2012 +0100 + + Another try at fixing compressed kernel booting + +Index: linux-3.2.46/arch/arm/mach-bcm2708/include/mach/uncompress.h +=================================================================== +--- linux-3.2.46.orig/arch/arm/mach-bcm2708/include/mach/uncompress.h 2013-07-26 19:33:58.000000000 +0000 ++++ linux-3.2.46/arch/arm/mach-bcm2708/include/mach/uncompress.h 2013-07-26 19:33:59.000000000 +0000 +@@ -23,18 +23,24 @@ + #include + #include + +-#define BCM2708_UART_DR __io_address(UART0_BASE + 0x00) +-#define BCM2708_UART_FR __io_address(UART0_BASE + 0x18) ++#define UART_BAUD 115200 ++ ++#define BCM2708_UART_DR UART0_BASE + UART01x_DR ++#define BCM2708_UART_FR UART0_BASE + UART01x_FR ++#define BCM2708_UART_IBRD UART0_BASE + UART011_IBRD ++#define BCM2708_UART_FBRD UART0_BASE + UART011_FBRD ++#define BCM2708_UART_LCRH UART0_BASE + UART011_LCRH ++#define BCM2708_UART_CR UART0_BASE + UART011_CR + + /* + * This does not append a newline + */ + static inline void putc(int c) + { +- while (readl(BCM2708_UART_FR) & (1 << 5)) ++ while (__raw_readl(BCM2708_UART_FR) & UART01x_FR_TXFF) + barrier(); + +- writel(c, BCM2708_UART_DR); ++ __raw_writel(c, BCM2708_UART_DR); + } + + static inline void flush(void) +@@ -47,8 +53,33 @@ + } while ((fr & (UART011_FR_TXFE | UART01x_FR_BUSY)) != UART011_FR_TXFE); + } + ++static inline void arch_decomp_setup(void) ++{ ++ int temp, div, rem, frac; ++ ++ temp = 16 * UART_BAUD; ++ div = UART0_CLOCK / temp; ++ rem = UART0_CLOCK % temp; ++ temp = (8 * rem) / UART_BAUD; ++ frac = (temp >> 1) + (temp & 1); ++ ++ /* Make sure the UART is disabled before we start */ ++ __raw_writel(0, BCM2708_UART_CR); ++ ++ /* Set the baud rate */ ++ __raw_writel(div, BCM2708_UART_IBRD); ++ __raw_writel(frac, BCM2708_UART_FBRD); ++ ++ /* Set the UART to 8n1, FIFO enabled */ ++ __raw_writel(UART01x_LCRH_WLEN_8 | UART01x_LCRH_FEN, BCM2708_UART_LCRH); ++ ++ /* Enable the UART */ ++ __raw_writel(UART01x_CR_UARTEN | UART011_CR_TXE | UART011_CR_RXE, ++ BCM2708_UART_CR); ++} ++ + /* + * nothing to do + */ +-#define arch_decomp_setup() + #define arch_decomp_wdog() ++ diff -Nru linux-3.2.46/debian/patches/rpi/rpi_186_f9b5246fd33f96fe2a31dbd74dce8d6da7df0fbc.patch linux-3.2.46/debian/patches/rpi/rpi_186_f9b5246fd33f96fe2a31dbd74dce8d6da7df0fbc.patch --- linux-3.2.46/debian/patches/rpi/rpi_186_f9b5246fd33f96fe2a31dbd74dce8d6da7df0fbc.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_186_f9b5246fd33f96fe2a31dbd74dce8d6da7df0fbc.patch 2013-07-26 19:34:02.000000000 +0000 @@ -0,0 +1,32 @@ +commit f9b5246fd33f96fe2a31dbd74dce8d6da7df0fbc +Author: popcornmix +Date: Wed Jul 11 13:55:11 2012 +0100 + + Add missing UART0_CLOCK from last commit + +Index: linux-3.2.46/arch/arm/mach-bcm2708/bcm2708.c +=================================================================== +--- linux-3.2.46.orig/arch/arm/mach-bcm2708/bcm2708.c 2013-07-26 19:33:54.000000000 +0000 ++++ linux-3.2.46/arch/arm/mach-bcm2708/bcm2708.c 2013-07-26 19:34:01.000000000 +0000 +@@ -183,7 +183,7 @@ + * These are fixed clocks. + */ + static struct clk ref24_clk = { +- .rate = 3000000, /* The UART is clocked at 3MHz via APB_CLK */ ++ .rate = UART0_CLOCK, /* The UART is clocked at 3MHz via APB_CLK */ + }; + + static struct clk osc_clk = { +Index: linux-3.2.46/arch/arm/mach-bcm2708/include/mach/platform.h +=================================================================== +--- linux-3.2.46.orig/arch/arm/mach-bcm2708/include/mach/platform.h 2013-07-26 19:33:54.000000000 +0000 ++++ linux-3.2.46/arch/arm/mach-bcm2708/include/mach/platform.h 2013-07-26 19:34:01.000000000 +0000 +@@ -216,7 +216,7 @@ + #define PM_RSTS_HADDRF_SET 0x00000002 + #define PM_RSTS_HADDRQ_SET 0x00000001 + +- ++#define UART0_CLOCK 3000000 + + #endif + diff -Nru linux-3.2.46/debian/patches/rpi/rpi_187_b3df416a54a7892e80f65d80b0c14dc7514bf26d.patch linux-3.2.46/debian/patches/rpi/rpi_187_b3df416a54a7892e80f65d80b0c14dc7514bf26d.patch --- linux-3.2.46/debian/patches/rpi/rpi_187_b3df416a54a7892e80f65d80b0c14dc7514bf26d.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_187_b3df416a54a7892e80f65d80b0c14dc7514bf26d.patch 2013-07-26 19:34:03.000000000 +0000 @@ -0,0 +1,19 @@ +commit b3df416a54a7892e80f65d80b0c14dc7514bf26d +Author: chrisw2 +Date: Wed Jul 11 00:19:00 2012 +0100 + + Change to add SCSI tape support as loadable modules to kernel config after line 264 add these two lines: CONFIG_CHR_DEV_ST=m CONFIG_CHR_DEV_OSST=m + +Index: linux-3.2.46/arch/arm/configs/bcmrpi_defconfig +=================================================================== +--- linux-3.2.46.orig/arch/arm/configs/bcmrpi_defconfig 2013-07-26 19:33:57.000000000 +0000 ++++ linux-3.2.46/arch/arm/configs/bcmrpi_defconfig 2013-07-26 19:34:02.000000000 +0000 +@@ -262,6 +262,8 @@ + CONFIG_SCSI=y + # CONFIG_SCSI_PROC_FS is not set + CONFIG_BLK_DEV_SD=y ++CONFIG_CHR_DEV_ST=m ++CONFIG_CHR_DEV_OSST=m + CONFIG_BLK_DEV_SR=m + CONFIG_SCSI_MULTI_LUN=y + # CONFIG_SCSI_LOWLEVEL is not set diff -Nru linux-3.2.46/debian/patches/rpi/rpi_188_005ab728605baa7dc15c7050644cc4163642f9ad.patch linux-3.2.46/debian/patches/rpi/rpi_188_005ab728605baa7dc15c7050644cc4163642f9ad.patch --- linux-3.2.46/debian/patches/rpi/rpi_188_005ab728605baa7dc15c7050644cc4163642f9ad.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_188_005ab728605baa7dc15c7050644cc4163642f9ad.patch 2013-07-26 19:34:04.000000000 +0000 @@ -0,0 +1,29 @@ +commit 005ab728605baa7dc15c7050644cc4163642f9ad +Author: popcornmix +Date: Fri Jul 13 18:34:18 2012 +0100 + + Add temporary fix for hang when quitting X + +Index: linux-3.2.46/drivers/video/bcm2708_fb.c +=================================================================== +--- linux-3.2.46.orig/drivers/video/bcm2708_fb.c 2013-07-26 19:33:49.000000000 +0000 ++++ linux-3.2.46/drivers/video/bcm2708_fb.c 2013-07-26 19:34:03.000000000 +0000 +@@ -18,6 +18,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -221,7 +222,9 @@ + /* inform vc about new framebuffer */ + bcm_mailbox_write(MBOX_CHAN_FB, fb->dma); + +- /* TODO: replace fb driver with vchiq version */ ++ /* workaround occasional failure to read results. TODO: fix */ ++ msleep(10); ++ + /* wait for response */ + bcm_mailbox_read(MBOX_CHAN_FB, &val); + diff -Nru linux-3.2.46/debian/patches/rpi/rpi_189_56c44908b2860bb551aaf532c232bcc63d4e584d.patch linux-3.2.46/debian/patches/rpi/rpi_189_56c44908b2860bb551aaf532c232bcc63d4e584d.patch --- linux-3.2.46/debian/patches/rpi/rpi_189_56c44908b2860bb551aaf532c232bcc63d4e584d.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_189_56c44908b2860bb551aaf532c232bcc63d4e584d.patch 2013-07-26 19:34:06.000000000 +0000 @@ -0,0 +1,43 @@ +commit 56c44908b2860bb551aaf532c232bcc63d4e584d +Author: popcornmix +Date: Sat Jul 14 18:38:58 2012 +0100 + + Better fix for quitting X hang. Interrupted mailbox reads are not something we can reliably recover from, so down_interruptable is not a safe call. + +Index: linux-3.2.46/arch/arm/mach-bcm2708/vcio.c +=================================================================== +--- linux-3.2.46.orig/arch/arm/mach-bcm2708/vcio.c 2013-07-26 19:33:01.000000000 +0000 ++++ linux-3.2.46/arch/arm/mach-bcm2708/vcio.c 2013-07-26 19:34:05.000000000 +0000 +@@ -119,14 +119,10 @@ + if (mbox->magic != MBOX_MAGIC) + rc = -EINVAL; + else { +- if (down_interruptible(&mbox->sema[chan]) == 0) { +- *data28 = MBOX_DATA28(mbox->msg[chan]); +- mbox->msg[chan] = 0; +- rc = 0; +- } else { +- /* The wait was interrupted */ +- rc = -EINTR; +- } ++ down(&mbox->sema[chan]); ++ *data28 = MBOX_DATA28(mbox->msg[chan]); ++ mbox->msg[chan] = 0; ++ rc = 0; + } + return rc; + } +Index: linux-3.2.46/drivers/video/bcm2708_fb.c +=================================================================== +--- linux-3.2.46.orig/drivers/video/bcm2708_fb.c 2013-07-26 19:34:03.000000000 +0000 ++++ linux-3.2.46/drivers/video/bcm2708_fb.c 2013-07-26 19:34:05.000000000 +0000 +@@ -222,9 +222,6 @@ + /* inform vc about new framebuffer */ + bcm_mailbox_write(MBOX_CHAN_FB, fb->dma); + +- /* workaround occasional failure to read results. TODO: fix */ +- msleep(10); +- + /* wait for response */ + bcm_mailbox_read(MBOX_CHAN_FB, &val); + diff -Nru linux-3.2.46/debian/patches/rpi/rpi_190_0bf26691a6ba1d82581f03508f3836f16d6df0bf.patch linux-3.2.46/debian/patches/rpi/rpi_190_0bf26691a6ba1d82581f03508f3836f16d6df0bf.patch --- linux-3.2.46/debian/patches/rpi/rpi_190_0bf26691a6ba1d82581f03508f3836f16d6df0bf.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_190_0bf26691a6ba1d82581f03508f3836f16d6df0bf.patch 2013-07-26 19:34:07.000000000 +0000 @@ -0,0 +1,112 @@ +commit 0bf26691a6ba1d82581f03508f3836f16d6df0bf +Author: popcornmix +Date: Tue Jul 17 00:48:27 2012 +0100 + + Add sync_after_dma module parameter + +Index: linux-3.2.46/drivers/mmc/host/sdhci-bcm2708.c +=================================================================== +--- linux-3.2.46.orig/drivers/mmc/host/sdhci-bcm2708.c 2013-07-26 19:33:40.000000000 +0000 ++++ linux-3.2.46/drivers/mmc/host/sdhci-bcm2708.c 2013-07-26 19:34:06.000000000 +0000 +@@ -52,7 +52,6 @@ + #undef CONFIG_MMC_SDHCI_BCM2708_DMA + #define CONFIG_MMC_SDHCI_BCM2708_DMA y + +-#define USE_SYNC_AFTER_DMA + #ifdef CONFIG_MMC_SDHCI_BCM2708_DMA + /* #define CHECK_DMA_USE */ + #endif +@@ -137,6 +136,7 @@ + + static bool allow_highspeed = 1; + static int emmc_clock_freq = BCM2708_EMMC_CLOCK_FREQ; ++static bool sync_after_dma = 1; + + #if 0 + static void hptime_test(void) +@@ -832,34 +832,34 @@ + SDHCI_INT_SPACE_AVAIL); + } + } else { +-#ifdef USE_SYNC_AFTER_DMA +- /* On the Arasan controller the stop command (which will be +- scheduled after this completes) does not seem to work +- properly if we allow it to be issued when we are +- transferring data to/from the SD card. +- We get CRC and DEND errors unless we wait for +- the SD controller to finish reading/writing to the card. */ +- u32 state_mask; +- int timeout=5000; ++ if (sync_after_dma) { ++ /* On the Arasan controller the stop command (which will be ++ scheduled after this completes) does not seem to work ++ properly if we allow it to be issued when we are ++ transferring data to/from the SD card. ++ We get CRC and DEND errors unless we wait for ++ the SD controller to finish reading/writing to the card. */ ++ u32 state_mask; ++ int timeout=30*5000; + +- DBG("PDMA over - sync card\n"); +- if (data->flags & MMC_DATA_READ) +- state_mask = SDHCI_DOING_READ; +- else +- state_mask = SDHCI_DOING_WRITE; ++ DBG("PDMA over - sync card\n"); ++ if (data->flags & MMC_DATA_READ) ++ state_mask = SDHCI_DOING_READ; ++ else ++ state_mask = SDHCI_DOING_WRITE; + +- while (0 != (sdhci_bcm2708_raw_readl(host, SDHCI_PRESENT_STATE) +- & state_mask) && --timeout > 0) +- { +- udelay(30); +- continue; ++ while (0 != (sdhci_bcm2708_raw_readl(host, SDHCI_PRESENT_STATE) ++ & state_mask) && --timeout > 0) ++ { ++ udelay(1); ++ continue; ++ } ++ if (timeout <= 0) ++ printk(KERN_ERR"%s: final %s to SD card still " ++ "running\n", ++ mmc_hostname(host->mmc), ++ data->flags & MMC_DATA_READ? "read": "write"); + } +- if (timeout <= 0) +- printk(KERN_ERR"%s: final %s to SD card still " +- "running\n", +- mmc_hostname(host->mmc), +- data->flags & MMC_DATA_READ? "read": "write"); +-#endif + if (host_priv->complete) { + (*host_priv->complete)(host); + DBG("PDMA %s complete\n", +@@ -1315,7 +1315,9 @@ + SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | + SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | + SDHCI_QUIRK_MISSING_CAPS | +- SDHCI_QUIRK_NO_HISPD_BIT; ++ SDHCI_QUIRK_NO_HISPD_BIT | ++ (sync_after_dma ? 0:SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12); ++ + + #ifdef CONFIG_MMC_SDHCI_BCM2708_DMA + host->flags = SDHCI_USE_PLATDMA; +@@ -1493,6 +1495,7 @@ + + module_param(allow_highspeed, bool, 0444); + module_param(emmc_clock_freq, int, 0444); ++module_param(sync_after_dma, bool, 0444); + + MODULE_DESCRIPTION("Secure Digital Host Controller Interface platform driver"); + MODULE_AUTHOR("Broadcom "); +@@ -1501,5 +1504,6 @@ + + MODULE_PARM_DESC(allow_highspeed, "Allow high speed transfers modes"); + MODULE_PARM_DESC(emmc_clock_freq, "Specify the speed of emmc clock"); ++MODULE_PARM_DESC(sync_after_dma, "Block in driver until dma complete"); + + diff -Nru linux-3.2.46/debian/patches/rpi/rpi_191_b7f136eba5ca61d42fbdd71e184cfadc4e87f9a3.patch linux-3.2.46/debian/patches/rpi/rpi_191_b7f136eba5ca61d42fbdd71e184cfadc4e87f9a3.patch --- linux-3.2.46/debian/patches/rpi/rpi_191_b7f136eba5ca61d42fbdd71e184cfadc4e87f9a3.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_191_b7f136eba5ca61d42fbdd71e184cfadc4e87f9a3.patch 2013-07-26 19:34:08.000000000 +0000 @@ -0,0 +1,18 @@ +commit b7f136eba5ca61d42fbdd71e184cfadc4e87f9a3 +Author: popcornmix +Date: Thu Jul 19 16:00:28 2012 +0100 + + Add SPI_SPI_DEV module + +Index: linux-3.2.46/arch/arm/configs/bcmrpi_defconfig +=================================================================== +--- linux-3.2.46.orig/arch/arm/configs/bcmrpi_defconfig 2013-07-26 19:34:02.000000000 +0000 ++++ linux-3.2.46/arch/arm/configs/bcmrpi_defconfig 2013-07-26 19:34:08.000000000 +0000 +@@ -388,6 +388,7 @@ + CONFIG_I2C_BCM2708=m + CONFIG_SPI=y + CONFIG_SPI_BCM2708=m ++CONFIG_SPI_SPIDEV=m + CONFIG_GPIO_SYSFS=y + # CONFIG_HWMON is not set + CONFIG_WATCHDOG=y diff -Nru linux-3.2.46/debian/patches/rpi/rpi_192_e76b20accf3be6b4ddd63dee9313771bdd8ff4b1.patch linux-3.2.46/debian/patches/rpi/rpi_192_e76b20accf3be6b4ddd63dee9313771bdd8ff4b1.patch --- linux-3.2.46/debian/patches/rpi/rpi_192_e76b20accf3be6b4ddd63dee9313771bdd8ff4b1.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_192_e76b20accf3be6b4ddd63dee9313771bdd8ff4b1.patch 2013-07-26 19:34:10.000000000 +0000 @@ -0,0 +1,21 @@ +commit e76b20accf3be6b4ddd63dee9313771bdd8ff4b1 +Author: popcornmix +Date: Tue Jul 24 11:11:03 2012 +0100 + + Fix var.width/var.height. They actually mean display size. See #65 + +Index: linux-3.2.46/drivers/video/bcm2708_fb.c +=================================================================== +--- linux-3.2.46.orig/drivers/video/bcm2708_fb.c 2013-07-26 19:34:05.000000000 +0000 ++++ linux-3.2.46/drivers/video/bcm2708_fb.c 2013-07-26 19:34:09.000000000 +0000 +@@ -374,8 +374,8 @@ + fb->fb.var.vmode = FB_VMODE_NONINTERLACED; + fb->fb.var.activate = FB_ACTIVATE_NOW; + fb->fb.var.nonstd = 0; +- fb->fb.var.height = fbwidth; +- fb->fb.var.width = fbheight; ++ fb->fb.var.height = -1; /* height of picture in mm */ ++ fb->fb.var.width = -1; /* width of picture in mm */ + fb->fb.var.accel_flags = 0; + + fb->fb.monspecs.hfmin = 0; diff -Nru linux-3.2.46/debian/patches/rpi/rpi_193_44987f59e8aa873338071637dea24ef125e329a9.patch linux-3.2.46/debian/patches/rpi/rpi_193_44987f59e8aa873338071637dea24ef125e329a9.patch --- linux-3.2.46/debian/patches/rpi/rpi_193_44987f59e8aa873338071637dea24ef125e329a9.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_193_44987f59e8aa873338071637dea24ef125e329a9.patch 2013-07-26 19:34:11.000000000 +0000 @@ -0,0 +1,19 @@ +commit 44987f59e8aa873338071637dea24ef125e329a9 +Author: Ian Tessier +Date: Wed Jul 25 12:22:35 2012 -0400 + + The TIMER_PERIOD should be calculated using the timer interrupt frequency. + +Index: linux-3.2.46/arch/arm/mach-bcm2708/bcm2708.c +=================================================================== +--- linux-3.2.46.orig/arch/arm/mach-bcm2708/bcm2708.c 2013-07-26 19:34:01.000000000 +0000 ++++ linux-3.2.46/arch/arm/mach-bcm2708/bcm2708.c 2013-07-26 19:34:10.000000000 +0000 +@@ -618,7 +618,7 @@ + #endif + } + +-#define TIMER_PERIOD 10000 /* HZ in microsecs */ ++#define TIMER_PERIOD DIV_ROUND_CLOSEST(STC_FREQ_HZ, HZ) + + static void timer_set_mode(enum clock_event_mode mode, + struct clock_event_device *clk) diff -Nru linux-3.2.46/debian/patches/rpi/rpi_194_1ad0baa517925ef794728f8446b9e63b34b1a9d1.patch linux-3.2.46/debian/patches/rpi/rpi_194_1ad0baa517925ef794728f8446b9e63b34b1a9d1.patch --- linux-3.2.46/debian/patches/rpi/rpi_194_1ad0baa517925ef794728f8446b9e63b34b1a9d1.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_194_1ad0baa517925ef794728f8446b9e63b34b1a9d1.patch 2013-07-26 19:34:12.000000000 +0000 @@ -0,0 +1,197 @@ +commit 1ad0baa517925ef794728f8446b9e63b34b1a9d1 +Author: Alex Bradbury +Date: Wed Jul 25 21:39:52 2012 +0100 + + update bcmrpi_defconfig with various user requests + +Index: linux-3.2.46/arch/arm/configs/bcmrpi_defconfig +=================================================================== +--- linux-3.2.46.orig/arch/arm/configs/bcmrpi_defconfig 2013-07-26 19:34:08.000000000 +0000 ++++ linux-3.2.46/arch/arm/configs/bcmrpi_defconfig 2013-07-26 19:34:12.000000000 +0000 +@@ -212,7 +212,62 @@ + CONFIG_BRIDGE=m + CONFIG_VLAN_8021Q=m + CONFIG_VLAN_8021Q_GVRP=y ++CONFIG_NET_SCHED=y ++CONFIG_NET_SCH_CBQ=m ++CONFIG_NET_SCH_HTB=m ++CONFIG_NET_SCH_HFSC=m ++CONFIG_NET_SCH_PRIO=m ++CONFIG_NET_SCH_MULTIQ=m ++CONFIG_NET_SCH_RED=m ++CONFIG_NET_SCH_SFB=m ++CONFIG_NET_SCH_SFQ=m ++CONFIG_NET_SCH_TEQL=m ++CONFIG_NET_SCH_TBF=m ++CONFIG_NET_SCH_GRED=m ++CONFIG_NET_SCH_DSMARK=m ++CONFIG_NET_SCH_NETEM=m ++CONFIG_NET_SCH_DRR=m ++CONFIG_NET_SCH_MQPRIO=m ++CONFIG_NET_SCH_CHOKE=m ++CONFIG_NET_SCH_QFQ=m ++CONFIG_NET_CLS_BASIC=m ++CONFIG_NET_CLS_TCINDEX=m ++CONFIG_NET_CLS_ROUTE4=m ++CONFIG_NET_CLS_FW=m ++CONFIG_NET_CLS_U32=m ++CONFIG_CLS_U32_MARK=y ++CONFIG_NET_CLS_RSVP=m ++CONFIG_NET_CLS_RSVP6=m ++CONFIG_NET_CLS_FLOW=m ++CONFIG_NET_CLS_CGROUP=m ++CONFIG_NET_EMATCH=y ++CONFIG_NET_EMATCH_CMP=m ++CONFIG_NET_EMATCH_NBYTE=m ++CONFIG_NET_EMATCH_U32=m ++CONFIG_NET_EMATCH_META=m ++CONFIG_NET_EMATCH_TEXT=m ++CONFIG_NET_CLS_ACT=y ++CONFIG_NET_ACT_POLICE=m ++CONFIG_NET_ACT_GACT=m ++CONFIG_GACT_PROB=y ++CONFIG_NET_ACT_MIRRED=m ++CONFIG_NET_ACT_IPT=m ++CONFIG_NET_ACT_NAT=m ++CONFIG_NET_ACT_PEDIT=m ++CONFIG_NET_ACT_SIMP=m ++CONFIG_NET_ACT_SKBEDIT=m ++CONFIG_NET_ACT_CSUM=m + CONFIG_NET_PKTGEN=m ++CONFIG_HAMRADIO=y ++CONFIG_AX25=m ++CONFIG_NETROM=m ++CONFIG_ROSE=m ++CONFIG_MKISS=m ++CONFIG_6PACK=m ++CONFIG_BPQETHER=m ++CONFIG_BAYCOM_SER_FDX=m ++CONFIG_BAYCOM_SER_HDX=m ++CONFIG_YAM=m + CONFIG_IRDA=m + CONFIG_IRLAN=m + CONFIG_IRNET=m +@@ -277,6 +332,8 @@ + CONFIG_DM_ZERO=m + CONFIG_DM_DELAY=m + CONFIG_NETDEVICES=y ++CONFIG_BONDING=m ++CONFIG_MACVLAN=m + CONFIG_TUN=m + CONFIG_PHYLIB=m + CONFIG_MDIO_BITBANG=m +@@ -343,6 +400,8 @@ + CONFIG_USB_SIERRA_NET=m + CONFIG_USB_VL600=m + CONFIG_PPP=m ++CONFIG_PPP_MULTILINK=y ++CONFIG_PPP_FILTER=y + CONFIG_PPP_ASYNC=m + CONFIG_PPP_SYNC_TTY=m + CONFIG_PPP_DEFLATE=m +@@ -351,6 +410,7 @@ + CONFIG_PPPOE=m + CONFIG_SLIP=m + CONFIG_SLIP_COMPRESSED=y ++CONFIG_SLIP_SMART=y + CONFIG_NETCONSOLE=m + CONFIG_INPUT_POLLDEV=m + # CONFIG_INPUT_MOUSEDEV_PSAUX is not set +@@ -390,6 +450,20 @@ + CONFIG_SPI_BCM2708=m + CONFIG_SPI_SPIDEV=m + CONFIG_GPIO_SYSFS=y ++CONFIG_W1=m ++CONFIG_W1_MASTER_DS2490=m ++CONFIG_W1_MASTER_DS2482=m ++CONFIG_W1_MASTER_DS1WM=m ++CONFIG_W1_MASTER_GPIO=m ++CONFIG_W1_SLAVE_THERM=m ++CONFIG_W1_SLAVE_SMEM=m ++CONFIG_W1_SLAVE_DS2408=m ++CONFIG_W1_SLAVE_DS2423=m ++CONFIG_W1_SLAVE_DS2431=m ++CONFIG_W1_SLAVE_DS2433=m ++CONFIG_W1_SLAVE_DS2760=m ++CONFIG_W1_SLAVE_DS2780=m ++CONFIG_W1_SLAVE_BQ27000=m + # CONFIG_HWMON is not set + CONFIG_WATCHDOG=y + CONFIG_BCM2708_WDT=m +@@ -443,7 +517,18 @@ + CONFIG_USB_GSPCA_VICAM=m + CONFIG_USB_GSPCA_XIRLINK_CIT=m + CONFIG_USB_GSPCA_ZC3XX=m ++CONFIG_VIDEO_PVRUSB2=m + CONFIG_VIDEO_HDPVR=m ++CONFIG_VIDEO_EM28XX=m ++CONFIG_VIDEO_EM28XX_ALSA=m ++CONFIG_VIDEO_EM28XX_DVB=m ++CONFIG_VIDEO_TLG2300=m ++CONFIG_VIDEO_CX231XX=m ++CONFIG_VIDEO_CX231XX_ALSA=m ++CONFIG_VIDEO_CX231XX_DVB=m ++CONFIG_VIDEO_USBVISION=m ++CONFIG_USB_ET61X251=m ++CONFIG_USB_SN9C102=m + CONFIG_USB_PWC=m + CONFIG_USB_ZR364XX=m + CONFIG_USB_STKWEBCAM=m +@@ -452,8 +537,41 @@ + CONFIG_RADIO_SI470X=y + CONFIG_USB_SI470X=m + CONFIG_USB_MR800=m ++CONFIG_DVB_USB=m ++CONFIG_DVB_USB_A800=m ++CONFIG_DVB_USB_DIBUSB_MB=m ++CONFIG_DVB_USB_DIBUSB_MC=m ++CONFIG_DVB_USB_DIB0700=m ++CONFIG_DVB_USB_UMT_010=m ++CONFIG_DVB_USB_CXUSB=m ++CONFIG_DVB_USB_M920X=m ++CONFIG_DVB_USB_GL861=m ++CONFIG_DVB_USB_AU6610=m ++CONFIG_DVB_USB_DIGITV=m ++CONFIG_DVB_USB_VP7045=m ++CONFIG_DVB_USB_VP702X=m ++CONFIG_DVB_USB_GP8PSK=m ++CONFIG_DVB_USB_NOVA_T_USB2=m ++CONFIG_DVB_USB_TTUSB2=m ++CONFIG_DVB_USB_DTT200U=m ++CONFIG_DVB_USB_OPERA1=m ++CONFIG_DVB_USB_AF9005=m ++CONFIG_DVB_USB_AF9005_REMOTE=m ++CONFIG_DVB_USB_DW2102=m ++CONFIG_DVB_USB_CINERGY_T2=m ++CONFIG_DVB_USB_ANYSEE=m ++CONFIG_DVB_USB_DTV5100=m ++CONFIG_DVB_USB_AF9015=m ++CONFIG_DVB_USB_CE6230=m ++CONFIG_DVB_USB_FRIIO=m ++CONFIG_DVB_USB_EC168=m ++CONFIG_DVB_USB_AZ6027=m ++CONFIG_DVB_USB_LME2510=m ++CONFIG_DVB_USB_TECHNISAT_USB2=m + CONFIG_SMS_SIANO_MDTV=m + CONFIG_SMS_USB_DRV=m ++CONFIG_DVB_B2C2_FLEXCOP=m ++CONFIG_DVB_B2C2_FLEXCOP_USB=m + CONFIG_FB=y + CONFIG_FB_BCM2708=y + CONFIG_FRAMEBUFFER_CONSOLE=y +@@ -633,6 +751,7 @@ + CONFIG_W35UND=m + CONFIG_PRISM2_USB=m + CONFIG_R8712U=m ++CONFIG_R8712_AP=y + CONFIG_ZRAM=m + # CONFIG_IOMMU_SUPPORT is not set + CONFIG_EXT4_FS=y +@@ -674,6 +793,7 @@ + CONFIG_TMPFS=y + CONFIG_TMPFS_POSIX_ACL=y + CONFIG_CONFIGFS_FS=y ++CONFIG_ECRYPT_FS=m + CONFIG_HFS_FS=m + CONFIG_HFSPLUS_FS=m + CONFIG_SQUASHFS=m diff -Nru linux-3.2.46/debian/patches/rpi/rpi_195_622a46ff94cc76cb4557dabb65c6752e32c0f11f.patch linux-3.2.46/debian/patches/rpi/rpi_195_622a46ff94cc76cb4557dabb65c6752e32c0f11f.patch --- linux-3.2.46/debian/patches/rpi/rpi_195_622a46ff94cc76cb4557dabb65c6752e32c0f11f.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_195_622a46ff94cc76cb4557dabb65c6752e32c0f11f.patch 2013-07-26 19:34:14.000000000 +0000 @@ -0,0 +1,38 @@ +commit 622a46ff94cc76cb4557dabb65c6752e32c0f11f +Author: popcornmix +Date: Fri Jul 27 10:32:03 2012 +0100 + + Possible fix for USB packets going missing. Thank gsh + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c 2013-07-26 19:33:51.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c 2013-07-26 19:34:13.000000000 +0000 +@@ -282,12 +282,21 @@ + qh = DWC_LIST_ENTRY(qh_entry, dwc_otg_qh_t, qh_list_entry); + qh_entry = qh_entry->next; + if (dwc_frame_num_le(qh->sched_frame, hcd->frame_number)) { +- /* +- * Move QH to the ready list to be executed next +- * (micro)frame. +- */ +- DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_ready, +- &qh->qh_list_entry); ++ ++ if(qh->do_split && qh->sched_frame != hcd->frame_number) ++ { ++ // If we're late we may have missed the beginning of the frame ++ qh->sched_frame += qh->interval; ++ } ++ else ++ { ++ /* ++ * Move QH to the ready list to be executed next ++ * (micro)frame. ++ */ ++ DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_ready, ++ &qh->qh_list_entry); ++ } + } + } + tr_type = dwc_otg_hcd_select_transactions(hcd); diff -Nru linux-3.2.46/debian/patches/rpi/rpi_196_f193e284f60382b90584520ab6787a4652626eaa.patch linux-3.2.46/debian/patches/rpi/rpi_196_f193e284f60382b90584520ab6787a4652626eaa.patch --- linux-3.2.46/debian/patches/rpi/rpi_196_f193e284f60382b90584520ab6787a4652626eaa.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_196_f193e284f60382b90584520ab6787a4652626eaa.patch 2013-07-26 19:34:15.000000000 +0000 @@ -0,0 +1,40 @@ +commit f193e284f60382b90584520ab6787a4652626eaa +Author: popcornmix +Date: Fri Jul 27 12:03:28 2012 +0100 + + Revert "Possible fix for USB packets going missing. Thank gsh" + + This reverts commit 7e7695894e9e86490558b92af0d8bebdfaadcfed. + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c 2013-07-26 19:34:13.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c 2013-07-26 19:34:14.000000000 +0000 +@@ -282,21 +282,12 @@ + qh = DWC_LIST_ENTRY(qh_entry, dwc_otg_qh_t, qh_list_entry); + qh_entry = qh_entry->next; + if (dwc_frame_num_le(qh->sched_frame, hcd->frame_number)) { +- +- if(qh->do_split && qh->sched_frame != hcd->frame_number) +- { +- // If we're late we may have missed the beginning of the frame +- qh->sched_frame += qh->interval; +- } +- else +- { +- /* +- * Move QH to the ready list to be executed next +- * (micro)frame. +- */ +- DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_ready, +- &qh->qh_list_entry); +- } ++ /* ++ * Move QH to the ready list to be executed next ++ * (micro)frame. ++ */ ++ DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_ready, ++ &qh->qh_list_entry); + } + } + tr_type = dwc_otg_hcd_select_transactions(hcd); diff -Nru linux-3.2.46/debian/patches/rpi/rpi_197_93afe723635802e875da48e526c754c13860d537.patch linux-3.2.46/debian/patches/rpi/rpi_197_93afe723635802e875da48e526c754c13860d537.patch --- linux-3.2.46/debian/patches/rpi/rpi_197_93afe723635802e875da48e526c754c13860d537.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_197_93afe723635802e875da48e526c754c13860d537.patch 2013-07-26 19:34:17.000000000 +0000 @@ -0,0 +1,1637 @@ +commit 93afe723635802e875da48e526c754c13860d537 +Author: Chris Boot +Date: Mon May 7 10:45:36 2012 +0100 + + dwc_common_port: remove unused cruft with onerous dependencies + + The dwc_common_port library used by the dwc_otg includes bignumber and + crypto functions which require 64x64 multiplication functions. Remove + this dead code. + + Signed-off-by: Chris Boot + +Index: linux-3.2.46/drivers/usb/host/dwc_common_port/Makefile +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_common_port/Makefile 2013-07-26 19:32:22.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_common_port/Makefile 2013-07-26 19:34:16.000000000 +0000 +@@ -12,8 +12,8 @@ + CPPFLAGS += -DDWC_LINUX + + obj-$(CONFIG_USB_DWCOTG) += dwc_common_port_lib.o +-dwc_common_port_lib-objs := dwc_cc.o dwc_modpow.o dwc_dh.o \ +- dwc_crypto.o dwc_notifier.o \ ++dwc_common_port_lib-objs := dwc_cc.o \ ++ dwc_notifier.o \ + dwc_common_linux.o dwc_mem.o + + kernrelwd := $(subst ., ,$(KERNELRELEASE)) +Index: linux-3.2.46/drivers/usb/host/dwc_common_port/dwc_common_linux.c +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_common_port/dwc_common_linux.c 2013-07-26 19:33:51.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_common_port/dwc_common_linux.c 2013-07-26 19:34:16.000000000 +0000 +@@ -1,7 +1,4 @@ + #include "dwc_cc.h" +-#include "dwc_modpow.h" +-#include "dwc_dh.h" +-#include "dwc_crypto.h" + #include "dwc_notifier.h" + + #include +@@ -51,24 +48,6 @@ + EXPORT_SYMBOL(dwc_cc_cdid); + EXPORT_SYMBOL(dwc_cc_name); + +-#ifndef CONFIG_MACH_IPMATE +-/* Modpow */ +-EXPORT_SYMBOL(dwc_modpow); +-/* DH */ +-EXPORT_SYMBOL(dwc_dh_modpow); +-EXPORT_SYMBOL(dwc_dh_derive_keys); +-EXPORT_SYMBOL(dwc_dh_pk); +-#endif /* CONFIG_MACH_IPMATE */ +-/* Crypto */ +-EXPORT_SYMBOL(dwc_wusb_aes_encrypt); +-EXPORT_SYMBOL(dwc_wusb_cmf); +-EXPORT_SYMBOL(dwc_wusb_prf); +-EXPORT_SYMBOL(dwc_wusb_fill_ccm_nonce); +-EXPORT_SYMBOL(dwc_wusb_gen_nonce); +-EXPORT_SYMBOL(dwc_wusb_gen_key); +-EXPORT_SYMBOL(dwc_wusb_gen_mic); +- +- + /* Notification */ + EXPORT_SYMBOL(dwc_alloc_notification_manager); + EXPORT_SYMBOL(dwc_free_notification_manager); +@@ -96,7 +75,6 @@ + #include + #include + #include +-#include + #include + #include + #include +@@ -457,93 +435,6 @@ + } + EXPORT_SYMBOL(__DWC_FREE); + +-/* dwc_crypto.h */ +- +-void DWC_RANDOM_BYTES(uint8_t *buffer, uint32_t length) +-{ +- get_random_bytes(buffer, length); +-} +-EXPORT_SYMBOL(DWC_RANDOM_BYTES); +- +-int DWC_AES_CBC(uint8_t *message, uint32_t messagelen, uint8_t *key, uint32_t keylen, uint8_t iv[16], uint8_t *out) +-{ +- struct crypto_blkcipher *tfm; +- struct blkcipher_desc desc; +- struct scatterlist sgd; +- struct scatterlist sgs; +- +- tfm = crypto_alloc_blkcipher("cbc(aes)", 0, CRYPTO_ALG_ASYNC); +- if (tfm == NULL) { +- printk("failed to load transform for aes CBC\n"); +- return -1; +- } +- +- crypto_blkcipher_setkey(tfm, key, keylen); +- crypto_blkcipher_set_iv(tfm, iv, 16); +- +- sg_init_one(&sgd, out, messagelen); +- sg_init_one(&sgs, message, messagelen); +- +- desc.tfm = tfm; +- desc.flags = 0; +- +- if(crypto_blkcipher_encrypt(&desc, &sgd, &sgs, messagelen)) { +- crypto_free_blkcipher(tfm); +- DWC_ERROR("AES CBC encryption failed"); +- return -1; +- } +- +- crypto_free_blkcipher(tfm); +- return 0; +-} +-EXPORT_SYMBOL(DWC_AES_CBC); +- +-int DWC_SHA256(uint8_t *message, uint32_t len, uint8_t *out) +-{ +- struct crypto_hash *tfm; +- struct hash_desc desc; +- struct scatterlist sg; +- +- tfm = crypto_alloc_hash("sha256", 0, CRYPTO_ALG_ASYNC); +- if (IS_ERR(tfm)) { +- DWC_ERROR("Failed to load transform for sha256: %ld\n", PTR_ERR(tfm)); +- return 0; +- } +- desc.tfm = tfm; +- desc.flags = 0; +- +- sg_init_one(&sg, message, len); +- crypto_hash_digest(&desc, &sg, len, out); +- crypto_free_hash(tfm); +- +- return 1; +-} +-EXPORT_SYMBOL(DWC_SHA256); +- +-int DWC_HMAC_SHA256(uint8_t *message, uint32_t messagelen, +- uint8_t *key, uint32_t keylen, uint8_t *out) +-{ +- struct crypto_hash *tfm; +- struct hash_desc desc; +- struct scatterlist sg; +- +- tfm = crypto_alloc_hash("hmac(sha256)", 0, CRYPTO_ALG_ASYNC); +- if (IS_ERR(tfm)) { +- DWC_ERROR("Failed to load transform for hmac(sha256): %ld\n", PTR_ERR(tfm)); +- return 0; +- } +- desc.tfm = tfm; +- desc.flags = 0; +- +- sg_init_one(&sg, message, messagelen); +- crypto_hash_setkey(tfm, key, keylen); +- crypto_hash_digest(&desc, &sg, messagelen, out); +- crypto_free_hash(tfm); +- +- return 1; +-} +-EXPORT_SYMBOL(DWC_HMAC_SHA256); +- + /* Byte Ordering Conversions. */ + uint32_t DWC_CPU_TO_LE32(void *p) + { +Index: linux-3.2.46/drivers/usb/host/dwc_common_port/dwc_crypto.c +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_common_port/dwc_crypto.c 2013-07-26 19:31:19.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,306 +0,0 @@ +-/* ========================================================================= +- * $File: //dwh/usb_iip/dev/software/dwc_common_port/dwc_crypto.c $ +- * $Revision: #1 $ +- * $Date: 2008/12/21 $ +- * $Change: 1156609 $ +- * +- * Synopsys Portability Library Software and documentation +- * (hereinafter, "Software") is an Unsupported proprietary work of +- * Synopsys, Inc. unless otherwise expressly agreed to in writing +- * between Synopsys and you. +- * +- * The Software IS NOT an item of Licensed Software or Licensed Product +- * under any End User Software License Agreement or Agreement for +- * Licensed Product with Synopsys or any supplement thereto. You are +- * permitted to use and redistribute this Software in source and binary +- * forms, with or without modification, provided that redistributions +- * of source code must retain this notice. You may not view, use, +- * disclose, copy or distribute this file or any information contained +- * herein except pursuant to this license grant from Synopsys. If you +- * do not agree with this notice, including the disclaimer below, then +- * you are not authorized to use the Software. +- * +- * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" +- * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +- * FOR A PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL +- * SYNOPSYS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, +- * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +- * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY +- * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE +- * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH +- * DAMAGE. +- * ========================================================================= */ +- +-/** @file +- * This file contains the WUSB cryptographic routines. +- */ +- +-#include "dwc_crypto.h" +-#include "usb.h" +- +-#ifdef DEBUG +-static inline void dump_bytes(char *name, uint8_t *bytes, int len) +-{ +- int i; +- DWC_PRINTF("%s: ", name); +- for (i=0; idst == src, then the bytes will be encrypted +- * in-place. +- * +- * @return 0 on success, negative error code on error. +- */ +-int dwc_wusb_aes_encrypt(u8 *src, u8 *key, u8 *dst) +-{ +- u8 block_t[16]; +- DWC_MEMSET(block_t, 0, 16); +- +- return DWC_AES_CBC(src, 16, key, 16, block_t, dst); +-} +- +-/** +- * The CCM-MAC-FUNCTION described in section 6.5 of the WUSB spec. +- * This function takes a data string and returns the encrypted CBC +- * Counter-mode MIC. +- * +- * @param key The 128-bit symmetric key. +- * @param nonce The CCM nonce. +- * @param label The unique 14-byte ASCII text label. +- * @param bytes The byte array to be encrypted. +- * @param len Length of the byte array. +- * @param result Byte array to receive the 8-byte encrypted MIC. +- */ +-void dwc_wusb_cmf(u8 *key, u8 *nonce, +- char *label, u8 *bytes, int len, u8 *result) +-{ +- u8 block_m[16]; +- u8 block_x[16]; +- u8 block_t[8]; +- int idx, blkNum; +- u16 la = (u16)(len + 14); +- +- /* Set the AES-128 key */ +- //dwc_aes_setkey(tfm, key, 16); +- +- /* Fill block B0 from flags = 0x59, N, and l(m) = 0 */ +- block_m[0] = 0x59; +- for (idx = 0; idx < 13; idx++) +- block_m[idx + 1] = nonce[idx]; +- block_m[14] = 0; +- block_m[15] = 0; +- +- /* Produce the CBC IV */ +- dwc_wusb_aes_encrypt(block_m, key, block_x); +- show_block(block_m, "CBC IV in: ", "\n", 0); +- show_block(block_x, "CBC IV out:", "\n", 0); +- +- /* Fill block B1 from l(a) = Blen + 14, and A */ +- block_x[0] ^= (u8)(la >> 8); +- block_x[1] ^= (u8)la; +- for (idx = 0; idx < 14; idx++) +- block_x[idx + 2] ^= label[idx]; +- show_block(block_x, "After xor: ", "b1\n", 16); +- +- dwc_wusb_aes_encrypt(block_x, key, block_x); +- show_block(block_x, "After AES: ", "b1\n", 16); +- +- idx = 0; +- blkNum = 0; +- +- /* Fill remaining blocks with B */ +- while (len-- > 0) { +- block_x[idx] ^= *bytes++; +- if (++idx >= 16) { +- idx = 0; +- show_block(block_x, "After xor: ", "\n", blkNum); +- dwc_wusb_aes_encrypt(block_x, key, block_x); +- show_block(block_x, "After AES: ", "\n", blkNum); +- blkNum++; +- } +- } +- +- /* Handle partial last block */ +- if (idx > 0) { +- show_block(block_x, "After xor: ", "\n", blkNum); +- dwc_wusb_aes_encrypt(block_x, key, block_x); +- show_block(block_x, "After AES: ", "\n", blkNum); +- } +- +- /* Save the MIC tag */ +- DWC_MEMCPY(block_t, block_x, 8); +- show_block(block_t, "MIC tag : ", NULL, 8); +- +- /* Fill block A0 from flags = 0x01, N, and counter = 0 */ +- block_m[0] = 0x01; +- block_m[14] = 0; +- block_m[15] = 0; +- +- /* Encrypt the counter */ +- dwc_wusb_aes_encrypt(block_m, key, block_x); +- show_block(block_x, "CTR[MIC] : ", NULL, 8); +- +- /* XOR with MIC tag */ +- for (idx = 0; idx < 8; idx++) { +- block_t[idx] ^= block_x[idx]; +- } +- +- /* Return result to caller */ +- DWC_MEMCPY(result, block_t, 8); +- show_block(result, "CCM-MIC : ", NULL, 8); +- +-} +- +-/** +- * The PRF function described in section 6.5 of the WUSB spec. This function +- * concatenates MIC values returned from dwc_cmf() to create a value of +- * the requested length. +- * +- * @param prf_len Length of the PRF function in bits (64, 128, or 256). +- * @param key, nonce, label, bytes, len Same as for dwc_cmf(). +- * @param result Byte array to receive the result. +- */ +-void dwc_wusb_prf(int prf_len, u8 *key, +- u8 *nonce, char *label, u8 *bytes, int len, u8 *result) +-{ +- int i; +- +- nonce[0] = 0; +- for (i = 0; i < prf_len >> 6; i++, nonce[0]++) { +- dwc_wusb_cmf(key, nonce, label, bytes, len, result); +- result += 8; +- } +-} +- +-/** +- * Fills in CCM Nonce per the WUSB spec. +- * +- * @param[in] haddr Host address. +- * @param[in] daddr Device address. +- * @param[in] tkid Session Key(PTK) identifier. +- * @param[out] nonce Pointer to where the CCM Nonce output is to be written. +- */ +-void dwc_wusb_fill_ccm_nonce(uint16_t haddr, uint16_t daddr, uint8_t *tkid, +- uint8_t *nonce) +-{ +- +- DWC_DEBUG("%s %x %x\n", __func__, daddr, haddr); +- +- DWC_MEMSET(&nonce[0], 0, 16); +- +- DWC_MEMCPY(&nonce[6], tkid, 3); +- nonce[9] = daddr & 0xFF; +- nonce[10] = (daddr >> 8) & 0xFF; +- nonce[11] = haddr & 0xFF; +- nonce[12] = (haddr >> 8) & 0xFF; +- +- dump_bytes("CCM nonce", nonce, 16); +-} +- +-/** +- * Generates a 16-byte cryptographic-grade random number for the Host/Device +- * Nonce. +- */ +-void dwc_wusb_gen_nonce(uint16_t addr, uint8_t *nonce) +-{ +- uint8_t inonce[16]; +- uint32_t temp[4]; +- +- /* Fill in the Nonce */ +- DWC_MEMSET(&inonce[0], 0, sizeof(inonce)); +- inonce[9] = addr & 0xFF; +- inonce[10] = (addr >> 8) & 0xFF; +- inonce[11] = inonce[9]; +- inonce[12] = inonce[10]; +- +- /* Collect "randomness samples" */ +- DWC_RANDOM_BYTES((uint8_t *)temp, 16); +- +- dwc_wusb_prf_128((uint8_t *)temp, nonce, +- "Random Numbers", (uint8_t *)temp, sizeof(temp), +- nonce); +-} +- +-/** +- * Generates the Session Key (PTK) and Key Confirmation Key (KCK) per the +- * WUSB spec. +- * +- * @param[in] ccm_nonce Pointer to CCM Nonce. +- * @param[in] mk Master Key to derive the session from +- * @param[in] hnonce Pointer to Host Nonce. +- * @param[in] dnonce Pointer to Device Nonce. +- * @param[out] kck Pointer to where the KCK output is to be written. +- * @param[out] ptk Pointer to where the PTK output is to be written. +- */ +-void dwc_wusb_gen_key(uint8_t *ccm_nonce, uint8_t *mk, uint8_t *hnonce, +- uint8_t *dnonce, uint8_t *kck, uint8_t *ptk) +-{ +- uint8_t idata[32]; +- uint8_t odata[32]; +- +- dump_bytes("ck", mk, 16); +- dump_bytes("hnonce", hnonce, 16); +- dump_bytes("dnonce", dnonce, 16); +- +- /* The data is the HNonce and DNonce concatenated */ +- DWC_MEMCPY(&idata[0], hnonce, 16); +- DWC_MEMCPY(&idata[16], dnonce, 16); +- +- dwc_wusb_prf_256(mk, ccm_nonce, "Pair-wise keys", idata, 32, odata); +- +- /* Low 16 bytes of the result is the KCK, high 16 is the PTK */ +- DWC_MEMCPY(kck, &odata[0], 16); +- DWC_MEMCPY(ptk, &odata[16], 16); +- +- dump_bytes("kck", kck, 16); +- dump_bytes("ptk", ptk, 16); +-} +- +-/** +- * Generates the Message Integrity Code over the Handshake data per the +- * WUSB spec. +- * +- * @param ccm_nonce Pointer to CCM Nonce. +- * @param kck Pointer to Key Confirmation Key. +- * @param data Pointer to Handshake data to be checked. +- * @param mic Pointer to where the MIC output is to be written. +- */ +-void dwc_wusb_gen_mic(uint8_t *ccm_nonce, uint8_t *kck, +- uint8_t *data, uint8_t *mic) +-{ +- +- dwc_wusb_prf_64(kck, ccm_nonce, "out-of-bandMIC", +- data, WUSB_HANDSHAKE_LEN_FOR_MIC, mic); +-} +- +Index: linux-3.2.46/drivers/usb/host/dwc_common_port/dwc_crypto.h +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_common_port/dwc_crypto.h 2013-07-26 19:31:19.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,103 +0,0 @@ +-/* ========================================================================= +- * $File: //dwh/usb_iip/dev/software/dwc_common_port/dwc_crypto.h $ +- * $Revision: #1 $ +- * $Date: 2008/12/21 $ +- * $Change: 1156609 $ +- * +- * Synopsys Portability Library Software and documentation +- * (hereinafter, "Software") is an Unsupported proprietary work of +- * Synopsys, Inc. unless otherwise expressly agreed to in writing +- * between Synopsys and you. +- * +- * The Software IS NOT an item of Licensed Software or Licensed Product +- * under any End User Software License Agreement or Agreement for +- * Licensed Product with Synopsys or any supplement thereto. You are +- * permitted to use and redistribute this Software in source and binary +- * forms, with or without modification, provided that redistributions +- * of source code must retain this notice. You may not view, use, +- * disclose, copy or distribute this file or any information contained +- * herein except pursuant to this license grant from Synopsys. If you +- * do not agree with this notice, including the disclaimer below, then +- * you are not authorized to use the Software. +- * +- * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" +- * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +- * FOR A PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL +- * SYNOPSYS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, +- * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +- * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY +- * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE +- * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH +- * DAMAGE. +- * ========================================================================= */ +- +-#ifndef _DWC_CRYPTO_H_ +-#define _DWC_CRYPTO_H_ +- +-/** @file +- * +- * This file contains declarations for the WUSB Cryptographic routines as +- * defined in the WUSB spec. They are only to be used internally by the DWC UWB +- * modules. +- */ +- +-#include "dwc_os.h" +- +-int dwc_wusb_aes_encrypt(u8 *src, u8 *key, u8 *dst); +- +-void dwc_wusb_cmf(u8 *key, u8 *nonce, +- char *label, u8 *bytes, int len, u8 *result); +-void dwc_wusb_prf(int prf_len, u8 *key, +- u8 *nonce, char *label, u8 *bytes, int len, u8 *result); +- +-/** +- * The PRF-64 function described in section 6.5 of the WUSB spec. +- * +- * @param key, nonce, label, bytes, len, result Same as for dwc_prf(). +- */ +-static inline void dwc_wusb_prf_64(u8 *key, u8 *nonce, +- char *label, u8 *bytes, int len, u8 *result) +-{ +- dwc_wusb_prf(64, key, nonce, label, bytes, len, result); +-} +- +-/** +- * The PRF-128 function described in section 6.5 of the WUSB spec. +- * +- * @param key, nonce, label, bytes, len, result Same as for dwc_prf(). +- */ +-static inline void dwc_wusb_prf_128(u8 *key, u8 *nonce, +- char *label, u8 *bytes, int len, u8 *result) +-{ +- dwc_wusb_prf(128, key, nonce, label, bytes, len, result); +-} +- +-/** +- * The PRF-256 function described in section 6.5 of the WUSB spec. +- * +- * @param key, nonce, label, bytes, len, result Same as for dwc_prf(). +- */ +-static inline void dwc_wusb_prf_256(u8 *key, u8 *nonce, +- char *label, u8 *bytes, int len, u8 *result) +-{ +- dwc_wusb_prf(256, key, nonce, label, bytes, len, result); +-} +- +- +-void dwc_wusb_fill_ccm_nonce(uint16_t haddr, uint16_t daddr, uint8_t *tkid, +- uint8_t *nonce); +-void dwc_wusb_gen_nonce(uint16_t addr, +- uint8_t *nonce); +- +-void dwc_wusb_gen_key(uint8_t *ccm_nonce, uint8_t *mk, +- uint8_t *hnonce, uint8_t *dnonce, +- uint8_t *kck, uint8_t *ptk); +- +- +-void dwc_wusb_gen_mic(uint8_t *ccm_nonce, uint8_t +- *kck, uint8_t *data, uint8_t *mic); +- +-#endif /* _DWC_CRYPTO_H_ */ +Index: linux-3.2.46/drivers/usb/host/dwc_common_port/dwc_dh.c +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_common_port/dwc_dh.c 2013-07-26 19:31:19.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,286 +0,0 @@ +-/* ========================================================================= +- * $File: //dwh/usb_iip/dev/software/dwc_common_port/dwc_dh.c $ +- * $Revision: #1 $ +- * $Date: 2008/12/21 $ +- * $Change: 1156609 $ +- * +- * Synopsys Portability Library Software and documentation +- * (hereinafter, "Software") is an Unsupported proprietary work of +- * Synopsys, Inc. unless otherwise expressly agreed to in writing +- * between Synopsys and you. +- * +- * The Software IS NOT an item of Licensed Software or Licensed Product +- * under any End User Software License Agreement or Agreement for +- * Licensed Product with Synopsys or any supplement thereto. You are +- * permitted to use and redistribute this Software in source and binary +- * forms, with or without modification, provided that redistributions +- * of source code must retain this notice. You may not view, use, +- * disclose, copy or distribute this file or any information contained +- * herein except pursuant to this license grant from Synopsys. If you +- * do not agree with this notice, including the disclaimer below, then +- * you are not authorized to use the Software. +- * +- * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" +- * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +- * FOR A PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL +- * SYNOPSYS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, +- * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +- * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY +- * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE +- * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH +- * DAMAGE. +- * ========================================================================= */ +-#ifndef CONFIG_MACH_IPMATE +-#include "dwc_dh.h" +-#include "dwc_modpow.h" +- +-#ifdef DEBUG +-/* This function prints out a buffer in the format described in the Association +- * Model specification. */ +-static void dh_dump(char *str, void *_num, int len) +-{ +- uint8_t *num = _num; +- int i; +- DWC_PRINTF("%s\n", str); +- for (i = 0; i < len; i ++) { +- DWC_PRINTF("%02x", num[i]); +- if (((i + 1) % 2) == 0) DWC_PRINTF(" "); +- if (((i + 1) % 26) == 0) DWC_PRINTF("\n"); +- } +- +- DWC_PRINTF("\n"); +-} +-#else +-#define dh_dump(_x...) do {; } while(0) +-#endif +- +-/* Constant g value */ +-static __u32 dh_g[] = { +- 0x02000000, +-}; +- +-/* Constant p value */ +-static __u32 dh_p[] = { +- 0xFFFFFFFF, 0xFFFFFFFF, 0xA2DA0FC9, 0x34C26821, 0x8B62C6C4, 0xD11CDC80, 0x084E0229, 0x74CC678A, +- 0xA6BE0B02, 0x229B133B, 0x79084A51, 0xDD04348E, 0xB31995EF, 0x1B433ACD, 0x6D0A2B30, 0x37145FF2, +- 0x6D35E14F, 0x45C2516D, 0x76B585E4, 0xC67E5E62, 0xE9424CF4, 0x6BED37A6, 0xB65CFF0B, 0xEDB706F4, +- 0xFB6B38EE, 0xA59F895A, 0x11249FAE, 0xE61F4B7C, 0x51662849, 0x3D5BE4EC, 0xB87C00C2, 0x05BF63A1, +- 0x3648DA98, 0x9AD3551C, 0xA83F1669, 0x5FCF24FD, 0x235D6583, 0x96ADA3DC, 0x56F3621C, 0xBB528520, +- 0x0729D59E, 0x6D969670, 0x4E350C67, 0x0498BC4A, 0x086C74F1, 0x7C2118CA, 0x465E9032, 0x3BCE362E, +- 0x2C779EE3, 0x03860E18, 0xA283279B, 0x8FA207EC, 0xF05DC5B5, 0xC9524C6F, 0xF6CB2BDE, 0x18175895, +- 0x7C499539, 0xE56A95EA, 0x1826D215, 0x1005FA98, 0x5A8E7215, 0x2DC4AA8A, 0x0D1733AD, 0x337A5004, +- 0xAB2155A8, 0x64BA1CDF, 0x0485FBEC, 0x0AEFDB58, 0x5771EA8A, 0x7D0C065D, 0x850F97B3, 0xC7E4E1A6, +- 0x8CAEF5AB, 0xD73309DB, 0xE0948C1E, 0x9D61254A, 0x26D2E3CE, 0x6BEED21A, 0x06FA2FF1, 0x64088AD9, +- 0x730276D8, 0x646AC83E, 0x182B1F52, 0x0C207B17, 0x5717E1BB, 0x6C5D617A, 0xC0880977, 0xE246D9BA, +- 0xA04FE208, 0x31ABE574, 0xFC5BDB43, 0x8E10FDE0, 0x20D1824B, 0xCAD23AA9, 0xFFFFFFFF, 0xFFFFFFFF, +-}; +- +-static void dh_swap_bytes(void *_in, void *_out, uint32_t len) +-{ +- uint8_t *in = _in; +- uint8_t *out = _out; +- int i; +- for (i=0; i= 0; i--) { +- t = 0; +- for (j = len - 1; j >= 0; j--) { +- t += MUL_WORD(a[i], (BignumDblInt) b[j]); +- t += (BignumDblInt) c[i + j + 1]; +- c[i + j + 1] = (BignumInt) t; +- t = t >> BIGNUM_INT_BITS; +- } +- c[i] = (BignumInt) t; +- } +-} +- +-static void internal_add_shifted(BignumInt *number, +- unsigned n, int shift) +-{ +- int word = 1 + (shift / BIGNUM_INT_BITS); +- int bshift = shift % BIGNUM_INT_BITS; +- BignumDblInt addend; +- +- addend = (BignumDblInt)n << bshift; +- +- while (addend) { +- addend += number[word]; +- number[word] = (BignumInt) addend & BIGNUM_INT_MASK; +- addend >>= BIGNUM_INT_BITS; +- word++; +- } +-} +- +-/* +- * Compute a = a % m. +- * Input in first alen words of a and first mlen words of m. +- * Output in first alen words of a +- * (of which first alen-mlen words will be zero). +- * The MSW of m MUST have its high bit set. +- * Quotient is accumulated in the `quotient' array, which is a Bignum +- * rather than the internal bigendian format. Quotient parts are shifted +- * left by `qshift' before adding into quot. +- */ +-static void internal_mod(BignumInt *a, int alen, +- BignumInt *m, int mlen, +- BignumInt *quot, int qshift) +-{ +- BignumInt m0, m1; +- unsigned int h; +- int i, k; +- +- m0 = m[0]; +- if (mlen > 1) +- m1 = m[1]; +- else +- m1 = 0; +- +- for (i = 0; i <= alen - mlen; i++) { +- BignumDblInt t; +- unsigned int q, r, c, ai1; +- +- if (i == 0) { +- h = 0; +- } else { +- h = a[i - 1]; +- a[i - 1] = 0; +- } +- +- if (i == alen - 1) +- ai1 = 0; +- else +- ai1 = a[i + 1]; +- +- /* Find q = h:a[i] / m0 */ +- if (h >= m0) { +- /* +- * Special case. +- * +- * To illustrate it, suppose a BignumInt is 8 bits, and +- * we are dividing (say) A1:23:45:67 by A1:B2:C3. Then +- * our initial division will be 0xA123 / 0xA1, which +- * will give a quotient of 0x100 and a divide overflow. +- * However, the invariants in this division algorithm +- * are not violated, since the full number A1:23:... is +- * _less_ than the quotient prefix A1:B2:... and so the +- * following correction loop would have sorted it out. +- * +- * In this situation we set q to be the largest +- * quotient we _can_ stomach (0xFF, of course). +- */ +- q = BIGNUM_INT_MASK; +- } else { +- /* Macro doesn't want an array subscript expression passed +- * into it (see definition), so use a temporary. */ +- BignumInt tmplo = a[i]; +- DIVMOD_WORD(q, r, h, tmplo, m0); +- +- /* Refine our estimate of q by looking at +- h:a[i]:a[i+1] / m0:m1 */ +- t = MUL_WORD(m1, q); +- if (t > ((BignumDblInt) r << BIGNUM_INT_BITS) + ai1) { +- q--; +- t -= m1; +- r = (r + m0) & BIGNUM_INT_MASK; /* overflow? */ +- if (r >= (BignumDblInt) m0 && +- t > ((BignumDblInt) r << BIGNUM_INT_BITS) + ai1) q--; +- } +- } +- +- /* Subtract q * m from a[i...] */ +- c = 0; +- for (k = mlen - 1; k >= 0; k--) { +- t = MUL_WORD(q, m[k]); +- t += c; +- c = (unsigned)(t >> BIGNUM_INT_BITS); +- if ((BignumInt) t > a[i + k]) +- c++; +- a[i + k] -= (BignumInt) t; +- } +- +- /* Add back m in case of borrow */ +- if (c != h) { +- t = 0; +- for (k = mlen - 1; k >= 0; k--) { +- t += m[k]; +- t += a[i + k]; +- a[i + k] = (BignumInt) t; +- t = t >> BIGNUM_INT_BITS; +- } +- q--; +- } +- if (quot) +- internal_add_shifted(quot, q, qshift + BIGNUM_INT_BITS * (alen - mlen - i)); +- } +-} +- +-/* +- * Compute p % mod. +- * The most significant word of mod MUST be non-zero. +- * We assume that the result array is the same size as the mod array. +- * We optionally write out a quotient if `quotient' is non-NULL. +- * We can avoid writing out the result if `result' is NULL. +- */ +-void bigdivmod(Bignum p, Bignum mod, Bignum result, Bignum quotient) +-{ +- BignumInt *n, *m; +- int mshift; +- int plen, mlen, i, j; +- +- /* Allocate m of size mlen, copy mod to m */ +- /* We use big endian internally */ +- mlen = mod[0]; +- m = snewn(mlen, BignumInt); +- for (j = 0; j < mlen; j++) +- m[j] = mod[mod[0] - j]; +- +- /* Shift m left to make msb bit set */ +- for (mshift = 0; mshift < BIGNUM_INT_BITS-1; mshift++) +- if ((m[0] << mshift) & BIGNUM_TOP_BIT) +- break; +- if (mshift) { +- for (i = 0; i < mlen - 1; i++) +- m[i] = (m[i] << mshift) | (m[i + 1] >> (BIGNUM_INT_BITS - mshift)); +- m[mlen - 1] = m[mlen - 1] << mshift; +- } +- +- plen = p[0]; +- /* Ensure plen > mlen */ +- if (plen <= mlen) +- plen = mlen + 1; +- +- /* Allocate n of size plen, copy p to n */ +- n = snewn(plen, BignumInt); +- for (j = 0; j < plen; j++) +- n[j] = 0; +- for (j = 1; j <= (int)p[0]; j++) +- n[plen - j] = p[j]; +- +- /* Main computation */ +- internal_mod(n, plen, m, mlen, quotient, mshift); +- +- /* Fixup result in case the modulus was shifted */ +- if (mshift) { +- for (i = plen - mlen - 1; i < plen - 1; i++) +- n[i] = (n[i] << mshift) | (n[i + 1] >> (BIGNUM_INT_BITS - mshift)); +- n[plen - 1] = n[plen - 1] << mshift; +- internal_mod(n, plen, m, mlen, quotient, 0); +- for (i = plen - 1; i >= plen - mlen; i--) +- n[i] = (n[i] >> mshift) | (n[i - 1] << (BIGNUM_INT_BITS - mshift)); +- } +- +- /* Copy result to buffer */ +- if (result) { +- for (i = 1; i <= (int)result[0]; i++) { +- int j = plen - i; +- result[i] = j >= 0 ? n[j] : 0; +- } +- } +- +- /* Free temporary arrays */ +- for (i = 0; i < mlen; i++) +- m[i] = 0; +- sfree(m); +- for (i = 0; i < plen; i++) +- n[i] = 0; +- sfree(n); +-} +- +-/* +- * Simple remainder. +- */ +-Bignum bigmod(Bignum a, Bignum b) +-{ +- Bignum r = newbn(b[0]); +- bigdivmod(a, b, r, NULL); +- return r; +-} +- +-/* +- * Compute (base ^ exp) % mod. +- */ +-Bignum dwc_modpow(Bignum base_in, Bignum exp, Bignum mod) +-{ +- BignumInt *a, *b, *n, *m; +- int mshift; +- int mlen, i, j; +- Bignum base, result; +- +- /* +- * The most significant word of mod needs to be non-zero. It +- * should already be, but let's make sure. +- */ +- //assert(mod[mod[0]] != 0); +- +- /* +- * Make sure the base is smaller than the modulus, by reducing +- * it modulo the modulus if not. +- */ +- base = bigmod(base_in, mod); +- +- /* Allocate m of size mlen, copy mod to m */ +- /* We use big endian internally */ +- mlen = mod[0]; +- m = snewn(mlen, BignumInt); +- for (j = 0; j < mlen; j++) +- m[j] = mod[mod[0] - j]; +- +- /* Shift m left to make msb bit set */ +- for (mshift = 0; mshift < BIGNUM_INT_BITS - 1; mshift++) +- if ((m[0] << mshift) & BIGNUM_TOP_BIT) +- break; +- if (mshift) { +- for (i = 0; i < mlen - 1; i++) +- m[i] = +- (m[i] << mshift) | (m[i + 1] >> +- (BIGNUM_INT_BITS - mshift)); +- m[mlen - 1] = m[mlen - 1] << mshift; +- } +- +- /* Allocate n of size mlen, copy base to n */ +- n = snewn(mlen, BignumInt); +- i = mlen - base[0]; +- for (j = 0; j < i; j++) +- n[j] = 0; +- for (j = 0; j < base[0]; j++) +- n[i + j] = base[base[0] - j]; +- +- /* Allocate a and b of size 2*mlen. Set a = 1 */ +- a = snewn(2 * mlen, BignumInt); +- b = snewn(2 * mlen, BignumInt); +- for (i = 0; i < 2 * mlen; i++) +- a[i] = 0; +- a[2 * mlen - 1] = 1; +- +- /* Skip leading zero bits of exp. */ +- i = 0; +- j = BIGNUM_INT_BITS - 1; +- while (i < exp[0] && (exp[exp[0] - i] & (1 << j)) == 0) { +- j--; +- if (j < 0) { +- i++; +- j = BIGNUM_INT_BITS - 1; +- } +- } +- +- /* Main computation */ +- while (i < exp[0]) { +- while (j >= 0) { +- internal_mul(a + mlen, a + mlen, b, mlen); +- internal_mod(b, mlen * 2, m, mlen, NULL, 0); +- if ((exp[exp[0] - i] & (1 << j)) != 0) { +- internal_mul(b + mlen, n, a, mlen); +- internal_mod(a, mlen * 2, m, mlen, NULL, 0); +- } else { +- BignumInt *t; +- t = a; +- a = b; +- b = t; +- } +- j--; +- } +- i++; +- j = BIGNUM_INT_BITS - 1; +- } +- +- /* Fixup result in case the modulus was shifted */ +- if (mshift) { +- for (i = mlen - 1; i < 2 * mlen - 1; i++) +- a[i] = +- (a[i] << mshift) | (a[i + 1] >> +- (BIGNUM_INT_BITS - mshift)); +- a[2 * mlen - 1] = a[2 * mlen - 1] << mshift; +- internal_mod(a, mlen * 2, m, mlen, NULL, 0); +- for (i = 2 * mlen - 1; i >= mlen; i--) +- a[i] = +- (a[i] >> mshift) | (a[i - 1] << +- (BIGNUM_INT_BITS - mshift)); +- } +- +- /* Copy result to buffer */ +- result = newbn(mod[0]); +- for (i = 0; i < mlen; i++) +- result[result[0] - i] = a[i + mlen]; +- while (result[0] > 1 && result[result[0]] == 0) +- result[0]--; +- +- /* Free temporary arrays */ +- for (i = 0; i < 2 * mlen; i++) +- a[i] = 0; +- sfree(a); +- for (i = 0; i < 2 * mlen; i++) +- b[i] = 0; +- sfree(b); +- for (i = 0; i < mlen; i++) +- m[i] = 0; +- sfree(m); +- for (i = 0; i < mlen; i++) +- n[i] = 0; +- sfree(n); +- +- freebn(base); +- +- return result; +-} +- +- +-#ifdef UNITTEST +- +-static __u32 dh_p[] = { +- 96, +- 0xFFFFFFFF, +- 0xFFFFFFFF, +- 0xA93AD2CA, +- 0x4B82D120, +- 0xE0FD108E, +- 0x43DB5BFC, +- 0x74E5AB31, +- 0x08E24FA0, +- 0xBAD946E2, +- 0x770988C0, +- 0x7A615D6C, +- 0xBBE11757, +- 0x177B200C, +- 0x521F2B18, +- 0x3EC86A64, +- 0xD8760273, +- 0xD98A0864, +- 0xF12FFA06, +- 0x1AD2EE6B, +- 0xCEE3D226, +- 0x4A25619D, +- 0x1E8C94E0, +- 0xDB0933D7, +- 0xABF5AE8C, +- 0xA6E1E4C7, +- 0xB3970F85, +- 0x5D060C7D, +- 0x8AEA7157, +- 0x58DBEF0A, +- 0xECFB8504, +- 0xDF1CBA64, +- 0xA85521AB, +- 0x04507A33, +- 0xAD33170D, +- 0x8AAAC42D, +- 0x15728E5A, +- 0x98FA0510, +- 0x15D22618, +- 0xEA956AE5, +- 0x3995497C, +- 0x95581718, +- 0xDE2BCBF6, +- 0x6F4C52C9, +- 0xB5C55DF0, +- 0xEC07A28F, +- 0x9B2783A2, +- 0x180E8603, +- 0xE39E772C, +- 0x2E36CE3B, +- 0x32905E46, +- 0xCA18217C, +- 0xF1746C08, +- 0x4ABC9804, +- 0x670C354E, +- 0x7096966D, +- 0x9ED52907, +- 0x208552BB, +- 0x1C62F356, +- 0xDCA3AD96, +- 0x83655D23, +- 0xFD24CF5F, +- 0x69163FA8, +- 0x1C55D39A, +- 0x98DA4836, +- 0xA163BF05, +- 0xC2007CB8, +- 0xECE45B3D, +- 0x49286651, +- 0x7C4B1FE6, +- 0xAE9F2411, +- 0x5A899FA5, +- 0xEE386BFB, +- 0xF406B7ED, +- 0x0BFF5CB6, +- 0xA637ED6B, +- 0xF44C42E9, +- 0x625E7EC6, +- 0xE485B576, +- 0x6D51C245, +- 0x4FE1356D, +- 0xF25F1437, +- 0x302B0A6D, +- 0xCD3A431B, +- 0xEF9519B3, +- 0x8E3404DD, +- 0x514A0879, +- 0x3B139B22, +- 0x020BBEA6, +- 0x8A67CC74, +- 0x29024E08, +- 0x80DC1CD1, +- 0xC4C6628B, +- 0x2168C234, +- 0xC90FDAA2, +- 0xFFFFFFFF, +- 0xFFFFFFFF, +-}; +- +-static __u32 dh_a[] = { +- 8, +- 0xdf367516, +- 0x86459caa, +- 0xe2d459a4, +- 0xd910dae0, +- 0x8a8b5e37, +- 0x67ab31c6, +- 0xf0b55ea9, +- 0x440051d6, +-}; +- +-static __u32 dh_b[] = { +- 8, +- 0xded92656, +- 0xe07a048a, +- 0x6fa452cd, +- 0x2df89d30, +- 0xc75f1b0f, +- 0x8ce3578f, +- 0x7980a324, +- 0x5daec786, +-}; +- +-static __u32 dh_g[] = { +- 1, +- 2, +-}; +- +-int main(void) +-{ +- int i; +- __u32 *k; +- k = modpow(dh_g, dh_a, dh_p); +- +- printf("\n\n"); +- for (i=0; i> 16; +- printf("%04x %04x ", m, l); +- if (!((i + 1)%13)) printf("\n"); +- } +- printf("\n\n"); +- +- if ((k[0] == 0x60) && (k[1] == 0x28e490e5) && (k[0x60] == 0x5a0d3d4e)) { +- printf("PASS\n\n"); +- } +- else { +- printf("FAIL\n\n"); +- } +- +-} +- +-#endif /* UNITTEST */ +- +-#endif /* CONFIG_MACH_IPMATE */ +Index: linux-3.2.46/drivers/usb/host/dwc_common_port/dwc_modpow.h +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_common_port/dwc_modpow.h 2013-07-26 19:31:20.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,26 +0,0 @@ +-/* +- * dwc_modpow.h +- * See dwc_modpow.c for license and changes +- */ +-#ifndef _DWC_MODPOW_H +-#define _DWC_MODPOW_H +- +-#include "dwc_os.h" +- +-/** @file +- * +- * This file defines the module exponentiation function which is only used +- * internally by the DWC UWB modules for calculation of PKs during numeric +- * association. The routine is taken from the PUTTY, an open source terminal +- * emulator. The PUTTY License is preserved in the dwc_modpow.c file. +- * +- */ +- +-typedef uint32_t BignumInt; +-typedef uint64_t BignumDblInt; +-typedef BignumInt *Bignum; +- +-/* Compute modular exponentiaion */ +-extern Bignum dwc_modpow(Bignum base_in, Bignum exp, Bignum mod); +- +-#endif /* _LINUX_BIGNUM_H */ diff -Nru linux-3.2.46/debian/patches/rpi/rpi_198_5f77a992eedc7ad8254195c9becbaccf112e592f.patch linux-3.2.46/debian/patches/rpi/rpi_198_5f77a992eedc7ad8254195c9becbaccf112e592f.patch --- linux-3.2.46/debian/patches/rpi/rpi_198_5f77a992eedc7ad8254195c9becbaccf112e592f.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_198_5f77a992eedc7ad8254195c9becbaccf112e592f.patch 2013-07-26 19:34:19.000000000 +0000 @@ -0,0 +1,1107 @@ +commit 5f77a992eedc7ad8254195c9becbaccf112e592f +Author: Chris Boot +Date: Mon May 7 10:56:11 2012 +0100 + + arm: remove divdi3, it's not necessary at all + + This was added for the DWC OTG driver in commit d5ef856. As we've + removed the dead code from that driver that depends on this, it is no + longer required at all. + + Signed-off-by: Chris Boot + +Index: linux-3.2.46/arch/arm/boot/compressed/Makefile +=================================================================== +--- linux-3.2.46.orig/arch/arm/boot/compressed/Makefile 2013-07-26 19:31:51.000000000 +0000 ++++ linux-3.2.46/arch/arm/boot/compressed/Makefile 2013-07-26 19:34:17.000000000 +0000 +@@ -145,17 +145,11 @@ + LDFLAGS_vmlinux += -T + + # For __aeabi_uidivmod +-lib1funcs = $(obj)/lib1funcs.o $(obj)/divdi3.o ++lib1funcs = $(obj)/lib1funcs.o + + $(obj)/lib1funcs.S: $(srctree)/arch/$(SRCARCH)/lib/lib1funcs.S + $(call cmd,shipped) + +-$(obj)/longlong.h: $(srctree)/arch/$(SRCARCH)/lib/longlong.h FORCE +- $(call cmd,shipped) +- +-$(obj)/divdi3.c: $(srctree)/arch/$(SRCARCH)/lib/divdi3.c $(obj)/longlong.h FORCE +- $(call cmd,shipped) +- + # We need to prevent any GOTOFF relocs being used with references + # to symbols in the .bss section since we cannot relocate them + # independently from the rest at run time. This can be achieved by +Index: linux-3.2.46/arch/arm/boot/compressed/divdi3.c +=================================================================== +--- linux-3.2.46.orig/arch/arm/boot/compressed/divdi3.c 2013-07-26 19:31:51.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,338 +0,0 @@ +-/* 64-bit multiplication and division +- Copyright (C) 1989, 1992-1999, 2000, 2001, 2002, 2003 +- Free Software Foundation, Inc. +- This file is part of the GNU C Library. +- +- The GNU C Library is free software; you can redistribute it and/or +- modify it under the terms of the GNU Lesser General Public +- License as published by the Free Software Foundation; either +- version 2.1 of the License, or (at your option) any later version. +- +- The GNU C Library is distributed in the hope that it will be useful, +- but WITHOUT ANY WARRANTY; without even the implied warranty of +- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +- Lesser General Public License for more details. +- +- You should have received a copy of the GNU Lesser General Public +- License along with the GNU C Library; if not, write to the Free +- Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA +- 02111-1307 USA. */ +- +-#include "longlong.h" +- +-#define W_TYPE_SIZE (sizeof(long)) +- +-#ifdef __ARMEB__ +-struct DWstruct { long high, low;}; +-#else +-struct DWstruct { long low, high;}; +-#endif +- +-typedef union { struct DWstruct s; long long ll; } DWunion; +- +-/* Prototypes of exported functions. */ +-long long __divdi3 (long long u, long long v); +-long long __moddi3 (long long u, long long v); +-unsigned long long __udivdi3 (unsigned long long u, unsigned long long v); +-unsigned long long __umoddi3 (unsigned long long u, unsigned long long v); +- +-static unsigned long long +-__udivmoddi4 (unsigned long long n, unsigned long long d, unsigned long long *rp) +-{ +- DWunion ww; +- DWunion nn, dd; +- DWunion rr; +- unsigned long d0, d1, n0, n1, n2; +- unsigned long q0, q1; +- unsigned long b, bm; +- +- nn.ll = n; +- dd.ll = d; +- +- d0 = dd.s.low; +- d1 = dd.s.high; +- n0 = nn.s.low; +- n1 = nn.s.high; +- +-#if !UDIV_NEEDS_NORMALIZATION +- if (d1 == 0) +- { +- if (d0 > n1) +- { +- /* 0q = nn / 0D */ +- +- udiv_qrnnd (q0, n0, n1, n0, d0); +- q1 = 0; +- +- /* Remainder in n0. */ +- } +- else +- { +- /* qq = NN / 0d */ +- +- if (d0 == 0) +- d0 = 1 / d0; /* Divide intentionally by zero. */ +- +- udiv_qrnnd (q1, n1, 0, n1, d0); +- udiv_qrnnd (q0, n0, n1, n0, d0); +- +- /* Remainder in n0. */ +- } +- +- if (rp != 0) +- { +- rr.s.low = n0; +- rr.s.high = 0; +- *rp = rr.ll; +- } +- } +- +-#else /* UDIV_NEEDS_NORMALIZATION */ +- +- if (d1 == 0) +- { +- if (d0 > n1) +- { +- /* 0q = nn / 0D */ +- +- count_leading_zeros (bm, d0); +- +- if (bm != 0) +- { +- /* Normalize, i.e. make the most significant bit of the +- denominator set. */ +- +- d0 = d0 << bm; +- n1 = (n1 << bm) | (n0 >> (W_TYPE_SIZE - bm)); +- n0 = n0 << bm; +- } +- +- udiv_qrnnd (q0, n0, n1, n0, d0); +- q1 = 0; +- +- /* Remainder in n0 >> bm. */ +- } +- else +- { +- /* qq = NN / 0d */ +- +- if (d0 == 0) +- d0 = 1 / d0; /* Divide intentionally by zero. */ +- +- count_leading_zeros (bm, d0); +- +- if (bm == 0) +- { +- /* From (n1 >= d0) /\ (the most significant bit of d0 is set), +- conclude (the most significant bit of n1 is set) /\ (the +- leading quotient digit q1 = 1). +- +- This special case is necessary, not an optimization. +- (Shifts counts of W_TYPE_SIZE are undefined.) */ +- +- n1 -= d0; +- q1 = 1; +- } +- else +- { +- /* Normalize. */ +- +- b = W_TYPE_SIZE - bm; +- +- d0 = d0 << bm; +- n2 = n1 >> b; +- n1 = (n1 << bm) | (n0 >> b); +- n0 = n0 << bm; +- +- udiv_qrnnd (q1, n1, n2, n1, d0); +- } +- +- /* n1 != d0... */ +- +- udiv_qrnnd (q0, n0, n1, n0, d0); +- +- /* Remainder in n0 >> bm. */ +- } +- +- if (rp != 0) +- { +- rr.s.low = n0 >> bm; +- rr.s.high = 0; +- *rp = rr.ll; +- } +- } +-#endif /* UDIV_NEEDS_NORMALIZATION */ +- +- else +- { +- if (d1 > n1) +- { +- /* 00 = nn / DD */ +- +- q0 = 0; +- q1 = 0; +- +- /* Remainder in n1n0. */ +- if (rp != 0) +- { +- rr.s.low = n0; +- rr.s.high = n1; +- *rp = rr.ll; +- } +- } +- else +- { +- /* 0q = NN / dd */ +- +- count_leading_zeros (bm, d1); +- if (bm == 0) +- { +- /* From (n1 >= d1) /\ (the most significant bit of d1 is set), +- conclude (the most significant bit of n1 is set) /\ (the +- quotient digit q0 = 0 or 1). +- +- This special case is necessary, not an optimization. */ +- +- /* The condition on the next line takes advantage of that +- n1 >= d1 (true due to program flow). */ +- if (n1 > d1 || n0 >= d0) +- { +- q0 = 1; +- sub_ddmmss (n1, n0, n1, n0, d1, d0); +- } +- else +- q0 = 0; +- +- q1 = 0; +- +- if (rp != 0) +- { +- rr.s.low = n0; +- rr.s.high = n1; +- *rp = rr.ll; +- } +- } +- else +- { +- unsigned long m1, m0; +- /* Normalize. */ +- +- b = W_TYPE_SIZE - bm; +- +- d1 = (d1 << bm) | (d0 >> b); +- d0 = d0 << bm; +- n2 = n1 >> b; +- n1 = (n1 << bm) | (n0 >> b); +- n0 = n0 << bm; +- +- udiv_qrnnd (q0, n1, n2, n1, d1); +- umul_ppmm (m1, m0, q0, d0); +- +- if (m1 > n1 || (m1 == n1 && m0 > n0)) +- { +- q0--; +- sub_ddmmss (m1, m0, m1, m0, d1, d0); +- } +- +- q1 = 0; +- +- /* Remainder in (n1n0 - m1m0) >> bm. */ +- if (rp != 0) +- { +- sub_ddmmss (n1, n0, n1, n0, m1, m0); +- rr.s.low = (n1 << b) | (n0 >> bm); +- rr.s.high = n1 >> bm; +- *rp = rr.ll; +- } +- } +- } +- } +- +- ww.s.low = q0; +- ww.s.high = q1; +- return ww.ll; +-} +- +-long long +-__divdi3 (long long u, long long v) +-{ +- long c = 0; +- long long w; +- +- if (u < 0) +- { +- c = ~c; +- u = -u; +- } +- if (v < 0) +- { +- c = ~c; +- v = -v; +- } +- w = __udivmoddi4 (u, v, 0); +- if (c) +- w = -w; +- return w; +-} +- +-long long +-__moddi3 (long long u, long long v) +-{ +- long c = 0; +- long long w; +- +- if (u < 0) +- { +- c = ~c; +- u = -u; +- } +- if (v < 0) +- v = -v; +- __udivmoddi4 (u, v, &w); +- if (c) +- w = -w; +- return w; +-} +- +-unsigned long long +-__udivdi3 (unsigned long long u, unsigned long long v) +-{ +- return __udivmoddi4 (u, v, 0); +-} +- +-unsigned long long +-__umoddi3 (unsigned long long u, unsigned long long v) +-{ +- unsigned long long w; +- +- __udivmoddi4 (u, v, &w); +- return w; +-} +- +-long long +-__gnu_ldivmod_helper (long long a, +- +- long long b, +- long long *remainder) +-{ +- long long quotient; +- +- quotient = __divdi3 (a, b); +- *remainder = a - b * quotient; +- +- return quotient; +-} +- +-unsigned long long +- +-__gnu_uldivmod_helper (unsigned long long a, +- +- unsigned long long b, +- unsigned long long *remainder) +-{ +- unsigned long long quotient; +- +- quotient = __udivdi3 (a, b); +- *remainder = a - b * quotient; +- return quotient; +-} +Index: linux-3.2.46/arch/arm/boot/compressed/longlong.h +=================================================================== +--- linux-3.2.46.orig/arch/arm/boot/compressed/longlong.h 2013-07-26 19:31:51.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,151 +0,0 @@ +-/* longlong.h -- based on code from gcc-2.95.3 +- +- definitions for mixed size 32/64 bit arithmetic. +- Copyright (C) 1991, 92, 94, 95, 96, 1997, 1998 Free Software Foundation, Inc. +- +- This definition file is free software; you can redistribute it +- and/or modify it under the terms of the GNU General Public +- License as published by the Free Software Foundation; either +- version 2, or (at your option) any later version. +- +- This definition file is distributed in the hope that it will be +- useful, but WITHOUT ANY WARRANTY; without even the implied +- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +- See the GNU General Public License for more details. +- +- You should have received a copy of the GNU General Public License +- along with this program; if not, write to the Free Software +- Foundation, Inc., 59 Temple Place - Suite 330, +- Boston, MA 02111-1307, USA. */ +- +-/* Borrowed from GCC 2.95.3, I Molton 29/07/01 */ +- +-#define USItype unsigned long +-#define SI_TYPE_SIZE sizeof(USItype) +- +-#define __BITS4 (SI_TYPE_SIZE / 4) +-#define __ll_B (1L << (SI_TYPE_SIZE / 2)) +-#define __ll_lowpart(t) ((USItype) (t) % __ll_B) +-#define __ll_highpart(t) ((USItype) (t) / __ll_B) +- +-/* Define auxiliary asm macros. +- +- 1) umul_ppmm(high_prod, low_prod, multipler, multiplicand) +- multiplies two USItype integers MULTIPLER and MULTIPLICAND, +- and generates a two-part USItype product in HIGH_PROD and +- LOW_PROD. +- +- 2) __umulsidi3(a,b) multiplies two USItype integers A and B, +- and returns a UDItype product. This is just a variant of umul_ppmm. +- +- 3) udiv_qrnnd(quotient, remainder, high_numerator, low_numerator, +- denominator) divides a two-word unsigned integer, composed by the +- integers HIGH_NUMERATOR and LOW_NUMERATOR, by DENOMINATOR and +- places the quotient in QUOTIENT and the remainder in REMAINDER. +- HIGH_NUMERATOR must be less than DENOMINATOR for correct operation. +- If, in addition, the most significant bit of DENOMINATOR must be 1, +- then the pre-processor symbol UDIV_NEEDS_NORMALIZATION is defined to 1. +- +- 4) sdiv_qrnnd(quotient, remainder, high_numerator, low_numerator, +- denominator). Like udiv_qrnnd but the numbers are signed. The +- quotient is rounded towards 0. +- +- 5) count_leading_zeros(count, x) counts the number of zero-bits from +- the msb to the first non-zero bit. This is the number of steps X +- needs to be shifted left to set the msb. Undefined for X == 0. +- +- 6) add_ssaaaa(high_sum, low_sum, high_addend_1, low_addend_1, +- high_addend_2, low_addend_2) adds two two-word unsigned integers, +- composed by HIGH_ADDEND_1 and LOW_ADDEND_1, and HIGH_ADDEND_2 and +- LOW_ADDEND_2 respectively. The result is placed in HIGH_SUM and +- LOW_SUM. Overflow (i.e. carry out) is not stored anywhere, and is +- lost. +- +- 7) sub_ddmmss(high_difference, low_difference, high_minuend, +- low_minuend, high_subtrahend, low_subtrahend) subtracts two +- two-word unsigned integers, composed by HIGH_MINUEND_1 and +- LOW_MINUEND_1, and HIGH_SUBTRAHEND_2 and LOW_SUBTRAHEND_2 +- respectively. The result is placed in HIGH_DIFFERENCE and +- LOW_DIFFERENCE. Overflow (i.e. carry out) is not stored anywhere, +- and is lost. +- +- If any of these macros are left undefined for a particular CPU, +- C macros are used. */ +- +-#if defined (__arm__) +-#define add_ssaaaa(sh, sl, ah, al, bh, bl) \ +- __asm__ ("adds %1, %4, %5 \n\ +- adc %0, %2, %3" \ +- : "=r" ((USItype) (sh)), \ +- "=&r" ((USItype) (sl)) \ +- : "%r" ((USItype) (ah)), \ +- "rI" ((USItype) (bh)), \ +- "%r" ((USItype) (al)), \ +- "rI" ((USItype) (bl))) +-#define sub_ddmmss(sh, sl, ah, al, bh, bl) \ +- __asm__ ("subs %1, %4, %5 \n\ +- sbc %0, %2, %3" \ +- : "=r" ((USItype) (sh)), \ +- "=&r" ((USItype) (sl)) \ +- : "r" ((USItype) (ah)), \ +- "rI" ((USItype) (bh)), \ +- "r" ((USItype) (al)), \ +- "rI" ((USItype) (bl))) +-#define umul_ppmm(xh, xl, a, b) \ +- __asm__ ("%@ Inlined umul_ppmm\n" \ +- "umull %r1, %r0, %r2, %r3" \ +- : "=&r" ((USItype)(xh)), \ +- "=r" ((USItype)(xl)) \ +- : "r" ((USItype)(a)), \ +- "r" ((USItype)(b)) \ +- : "r0", "r1") +-#define count_leading_zeros(count, x) \ +- __asm__ ("clz %0, %1" : "=r"(count) : "r"(x)) +-#define UMUL_TIME 20 +-#define UDIV_TIME 100 +-#endif /* __arm__ */ +- +-#define __umulsidi3(u, v) \ +- ({DIunion __w; \ +- umul_ppmm (__w.s.high, __w.s.low, u, v); \ +- __w.ll; }) +- +-#define __udiv_qrnnd_c(q, r, n1, n0, d) \ +- do { \ +- USItype __d1, __d0, __q1, __q0; \ +- USItype __r1, __r0, __m; \ +- __d1 = __ll_highpart (d); \ +- __d0 = __ll_lowpart (d); \ +- \ +- __r1 = (n1) % __d1; \ +- __q1 = (n1) / __d1; \ +- __m = (USItype) __q1 * __d0; \ +- __r1 = __r1 * __ll_B | __ll_highpart (n0); \ +- if (__r1 < __m) \ +- { \ +- __q1--, __r1 += (d); \ +- if (__r1 >= (d)) /* i.e. we didn't get carry when adding to __r1 */\ +- if (__r1 < __m) \ +- __q1--, __r1 += (d); \ +- } \ +- __r1 -= __m; \ +- \ +- __r0 = __r1 % __d1; \ +- __q0 = __r1 / __d1; \ +- __m = (USItype) __q0 * __d0; \ +- __r0 = __r0 * __ll_B | __ll_lowpart (n0); \ +- if (__r0 < __m) \ +- { \ +- __q0--, __r0 += (d); \ +- if (__r0 >= (d)) \ +- if (__r0 < __m) \ +- __q0--, __r0 += (d); \ +- } \ +- __r0 -= __m; \ +- \ +- (q) = (USItype) __q1 * __ll_B | __q0; \ +- (r) = __r0; \ +- } while (0) +- +-#define UDIV_NEEDS_NORMALIZATION 1 +-#define udiv_qrnnd __udiv_qrnnd_c +Index: linux-3.2.46/arch/arm/kernel/armksyms.c +=================================================================== +--- linux-3.2.46.orig/arch/arm/kernel/armksyms.c 2013-07-26 19:31:51.000000000 +0000 ++++ linux-3.2.46/arch/arm/kernel/armksyms.c 2013-07-26 19:34:17.000000000 +0000 +@@ -46,8 +46,6 @@ + extern void __aeabi_uidiv(void); + extern void __aeabi_uidivmod(void); + extern void __aeabi_ulcmp(void); +-extern void __aeabi_ldivmod(void); +-extern void __aeabi_uldivmod(void); + + extern void fpundefinstr(void); + +@@ -133,8 +131,6 @@ + EXPORT_SYMBOL(__aeabi_uidiv); + EXPORT_SYMBOL(__aeabi_uidivmod); + EXPORT_SYMBOL(__aeabi_ulcmp); +-EXPORT_SYMBOL(__aeabi_ldivmod); +-EXPORT_SYMBOL(__aeabi_uldivmod); + #endif + + /* bitops */ +Index: linux-3.2.46/arch/arm/lib/Makefile +=================================================================== +--- linux-3.2.46.orig/arch/arm/lib/Makefile 2013-07-26 19:31:51.000000000 +0000 ++++ linux-3.2.46/arch/arm/lib/Makefile 2013-07-26 19:34:17.000000000 +0000 +@@ -13,8 +13,7 @@ + testchangebit.o testclearbit.o testsetbit.o \ + ashldi3.o ashrdi3.o lshrdi3.o muldi3.o \ + ucmpdi2.o lib1funcs.o div64.o \ +- io-readsb.o io-writesb.o io-readsl.o io-writesl.o \ +- divdi3.o ++ io-readsb.o io-writesb.o io-readsl.o io-writesl.o + + mmu-y := clear_user.o copy_page.o getuser.o putuser.o + +Index: linux-3.2.46/arch/arm/lib/divdi3.c +=================================================================== +--- linux-3.2.46.orig/arch/arm/lib/divdi3.c 2013-07-26 19:31:51.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,338 +0,0 @@ +-/* 64-bit multiplication and division +- Copyright (C) 1989, 1992-1999, 2000, 2001, 2002, 2003 +- Free Software Foundation, Inc. +- This file is part of the GNU C Library. +- +- The GNU C Library is free software; you can redistribute it and/or +- modify it under the terms of the GNU Lesser General Public +- License as published by the Free Software Foundation; either +- version 2.1 of the License, or (at your option) any later version. +- +- The GNU C Library is distributed in the hope that it will be useful, +- but WITHOUT ANY WARRANTY; without even the implied warranty of +- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +- Lesser General Public License for more details. +- +- You should have received a copy of the GNU Lesser General Public +- License along with the GNU C Library; if not, write to the Free +- Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA +- 02111-1307 USA. */ +- +-#include "longlong.h" +- +-#define W_TYPE_SIZE (sizeof(long)) +- +-#ifdef __ARMEB__ +-struct DWstruct { long high, low;}; +-#else +-struct DWstruct { long low, high;}; +-#endif +- +-typedef union { struct DWstruct s; long long ll; } DWunion; +- +-/* Prototypes of exported functions. */ +-long long __divdi3 (long long u, long long v); +-long long __moddi3 (long long u, long long v); +-unsigned long long __udivdi3 (unsigned long long u, unsigned long long v); +-unsigned long long __umoddi3 (unsigned long long u, unsigned long long v); +- +-static unsigned long long +-__udivmoddi4 (unsigned long long n, unsigned long long d, unsigned long long *rp) +-{ +- DWunion ww; +- DWunion nn, dd; +- DWunion rr; +- unsigned long d0, d1, n0, n1, n2; +- unsigned long q0, q1; +- unsigned long b, bm; +- +- nn.ll = n; +- dd.ll = d; +- +- d0 = dd.s.low; +- d1 = dd.s.high; +- n0 = nn.s.low; +- n1 = nn.s.high; +- +-#if !UDIV_NEEDS_NORMALIZATION +- if (d1 == 0) +- { +- if (d0 > n1) +- { +- /* 0q = nn / 0D */ +- +- udiv_qrnnd (q0, n0, n1, n0, d0); +- q1 = 0; +- +- /* Remainder in n0. */ +- } +- else +- { +- /* qq = NN / 0d */ +- +- if (d0 == 0) +- d0 = 1 / d0; /* Divide intentionally by zero. */ +- +- udiv_qrnnd (q1, n1, 0, n1, d0); +- udiv_qrnnd (q0, n0, n1, n0, d0); +- +- /* Remainder in n0. */ +- } +- +- if (rp != 0) +- { +- rr.s.low = n0; +- rr.s.high = 0; +- *rp = rr.ll; +- } +- } +- +-#else /* UDIV_NEEDS_NORMALIZATION */ +- +- if (d1 == 0) +- { +- if (d0 > n1) +- { +- /* 0q = nn / 0D */ +- +- count_leading_zeros (bm, d0); +- +- if (bm != 0) +- { +- /* Normalize, i.e. make the most significant bit of the +- denominator set. */ +- +- d0 = d0 << bm; +- n1 = (n1 << bm) | (n0 >> (W_TYPE_SIZE - bm)); +- n0 = n0 << bm; +- } +- +- udiv_qrnnd (q0, n0, n1, n0, d0); +- q1 = 0; +- +- /* Remainder in n0 >> bm. */ +- } +- else +- { +- /* qq = NN / 0d */ +- +- if (d0 == 0) +- d0 = 1 / d0; /* Divide intentionally by zero. */ +- +- count_leading_zeros (bm, d0); +- +- if (bm == 0) +- { +- /* From (n1 >= d0) /\ (the most significant bit of d0 is set), +- conclude (the most significant bit of n1 is set) /\ (the +- leading quotient digit q1 = 1). +- +- This special case is necessary, not an optimization. +- (Shifts counts of W_TYPE_SIZE are undefined.) */ +- +- n1 -= d0; +- q1 = 1; +- } +- else +- { +- /* Normalize. */ +- +- b = W_TYPE_SIZE - bm; +- +- d0 = d0 << bm; +- n2 = n1 >> b; +- n1 = (n1 << bm) | (n0 >> b); +- n0 = n0 << bm; +- +- udiv_qrnnd (q1, n1, n2, n1, d0); +- } +- +- /* n1 != d0... */ +- +- udiv_qrnnd (q0, n0, n1, n0, d0); +- +- /* Remainder in n0 >> bm. */ +- } +- +- if (rp != 0) +- { +- rr.s.low = n0 >> bm; +- rr.s.high = 0; +- *rp = rr.ll; +- } +- } +-#endif /* UDIV_NEEDS_NORMALIZATION */ +- +- else +- { +- if (d1 > n1) +- { +- /* 00 = nn / DD */ +- +- q0 = 0; +- q1 = 0; +- +- /* Remainder in n1n0. */ +- if (rp != 0) +- { +- rr.s.low = n0; +- rr.s.high = n1; +- *rp = rr.ll; +- } +- } +- else +- { +- /* 0q = NN / dd */ +- +- count_leading_zeros (bm, d1); +- if (bm == 0) +- { +- /* From (n1 >= d1) /\ (the most significant bit of d1 is set), +- conclude (the most significant bit of n1 is set) /\ (the +- quotient digit q0 = 0 or 1). +- +- This special case is necessary, not an optimization. */ +- +- /* The condition on the next line takes advantage of that +- n1 >= d1 (true due to program flow). */ +- if (n1 > d1 || n0 >= d0) +- { +- q0 = 1; +- sub_ddmmss (n1, n0, n1, n0, d1, d0); +- } +- else +- q0 = 0; +- +- q1 = 0; +- +- if (rp != 0) +- { +- rr.s.low = n0; +- rr.s.high = n1; +- *rp = rr.ll; +- } +- } +- else +- { +- unsigned long m1, m0; +- /* Normalize. */ +- +- b = W_TYPE_SIZE - bm; +- +- d1 = (d1 << bm) | (d0 >> b); +- d0 = d0 << bm; +- n2 = n1 >> b; +- n1 = (n1 << bm) | (n0 >> b); +- n0 = n0 << bm; +- +- udiv_qrnnd (q0, n1, n2, n1, d1); +- umul_ppmm (m1, m0, q0, d0); +- +- if (m1 > n1 || (m1 == n1 && m0 > n0)) +- { +- q0--; +- sub_ddmmss (m1, m0, m1, m0, d1, d0); +- } +- +- q1 = 0; +- +- /* Remainder in (n1n0 - m1m0) >> bm. */ +- if (rp != 0) +- { +- sub_ddmmss (n1, n0, n1, n0, m1, m0); +- rr.s.low = (n1 << b) | (n0 >> bm); +- rr.s.high = n1 >> bm; +- *rp = rr.ll; +- } +- } +- } +- } +- +- ww.s.low = q0; +- ww.s.high = q1; +- return ww.ll; +-} +- +-long long +-__divdi3 (long long u, long long v) +-{ +- long c = 0; +- long long w; +- +- if (u < 0) +- { +- c = ~c; +- u = -u; +- } +- if (v < 0) +- { +- c = ~c; +- v = -v; +- } +- w = __udivmoddi4 (u, v, 0); +- if (c) +- w = -w; +- return w; +-} +- +-long long +-__moddi3 (long long u, long long v) +-{ +- long c = 0; +- long long w; +- +- if (u < 0) +- { +- c = ~c; +- u = -u; +- } +- if (v < 0) +- v = -v; +- __udivmoddi4 (u, v, &w); +- if (c) +- w = -w; +- return w; +-} +- +-unsigned long long +-__udivdi3 (unsigned long long u, unsigned long long v) +-{ +- return __udivmoddi4 (u, v, 0); +-} +- +-unsigned long long +-__umoddi3 (unsigned long long u, unsigned long long v) +-{ +- unsigned long long w; +- +- __udivmoddi4 (u, v, &w); +- return w; +-} +- +-long long +-__gnu_ldivmod_helper (long long a, +- +- long long b, +- long long *remainder) +-{ +- long long quotient; +- +- quotient = __divdi3 (a, b); +- *remainder = a - b * quotient; +- +- return quotient; +-} +- +-unsigned long long +- +-__gnu_uldivmod_helper (unsigned long long a, +- +- unsigned long long b, +- unsigned long long *remainder) +-{ +- unsigned long long quotient; +- +- quotient = __udivdi3 (a, b); +- *remainder = a - b * quotient; +- return quotient; +-} +Index: linux-3.2.46/arch/arm/lib/lib1funcs.S +=================================================================== +--- linux-3.2.46.orig/arch/arm/lib/lib1funcs.S 2013-07-26 19:31:51.000000000 +0000 ++++ linux-3.2.46/arch/arm/lib/lib1funcs.S 2013-07-26 19:34:17.000000000 +0000 +@@ -349,33 +349,6 @@ + UNWIND(.fnend) + ENDPROC(__aeabi_idivmod) + +-/* Added 64x64 bit division for use with OTG USB driver - multi-precision +- * arithmetic for RSA encyrption. +- */ +-ENTRY(__aeabi_ldivmod) +- +- sub sp, sp, #8 +- stmfd sp!, {sp, lr} +- bl __gnu_ldivmod_helper +- ldr lr, [sp, #4] +- add sp, sp, #8 +- ldmfd sp!, {r2, r3} +- mov pc, lr +- +-ENDPROC(__aeabi_ldivmod) +- +-ENTRY(__aeabi_uldivmod) +- +- sub sp, sp, #8 +- stmfd sp!, {sp, lr} +- bl __gnu_uldivmod_helper +- ldr lr, [sp, #4] +- add sp, sp, #8 +- ldmfd sp!, {r2, r3} +- mov pc, lr +- +-ENDPROC(__aeabi_uldivmod) +- + #endif + + Ldiv0: +Index: linux-3.2.46/arch/arm/lib/longlong.h +=================================================================== +--- linux-3.2.46.orig/arch/arm/lib/longlong.h 2013-07-26 19:31:51.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,151 +0,0 @@ +-/* longlong.h -- based on code from gcc-2.95.3 +- +- definitions for mixed size 32/64 bit arithmetic. +- Copyright (C) 1991, 92, 94, 95, 96, 1997, 1998 Free Software Foundation, Inc. +- +- This definition file is free software; you can redistribute it +- and/or modify it under the terms of the GNU General Public +- License as published by the Free Software Foundation; either +- version 2, or (at your option) any later version. +- +- This definition file is distributed in the hope that it will be +- useful, but WITHOUT ANY WARRANTY; without even the implied +- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. +- See the GNU General Public License for more details. +- +- You should have received a copy of the GNU General Public License +- along with this program; if not, write to the Free Software +- Foundation, Inc., 59 Temple Place - Suite 330, +- Boston, MA 02111-1307, USA. */ +- +-/* Borrowed from GCC 2.95.3, I Molton 29/07/01 */ +- +-#define USItype unsigned long +-#define SI_TYPE_SIZE sizeof(USItype) +- +-#define __BITS4 (SI_TYPE_SIZE / 4) +-#define __ll_B (1L << (SI_TYPE_SIZE / 2)) +-#define __ll_lowpart(t) ((USItype) (t) % __ll_B) +-#define __ll_highpart(t) ((USItype) (t) / __ll_B) +- +-/* Define auxiliary asm macros. +- +- 1) umul_ppmm(high_prod, low_prod, multipler, multiplicand) +- multiplies two USItype integers MULTIPLER and MULTIPLICAND, +- and generates a two-part USItype product in HIGH_PROD and +- LOW_PROD. +- +- 2) __umulsidi3(a,b) multiplies two USItype integers A and B, +- and returns a UDItype product. This is just a variant of umul_ppmm. +- +- 3) udiv_qrnnd(quotient, remainder, high_numerator, low_numerator, +- denominator) divides a two-word unsigned integer, composed by the +- integers HIGH_NUMERATOR and LOW_NUMERATOR, by DENOMINATOR and +- places the quotient in QUOTIENT and the remainder in REMAINDER. +- HIGH_NUMERATOR must be less than DENOMINATOR for correct operation. +- If, in addition, the most significant bit of DENOMINATOR must be 1, +- then the pre-processor symbol UDIV_NEEDS_NORMALIZATION is defined to 1. +- +- 4) sdiv_qrnnd(quotient, remainder, high_numerator, low_numerator, +- denominator). Like udiv_qrnnd but the numbers are signed. The +- quotient is rounded towards 0. +- +- 5) count_leading_zeros(count, x) counts the number of zero-bits from +- the msb to the first non-zero bit. This is the number of steps X +- needs to be shifted left to set the msb. Undefined for X == 0. +- +- 6) add_ssaaaa(high_sum, low_sum, high_addend_1, low_addend_1, +- high_addend_2, low_addend_2) adds two two-word unsigned integers, +- composed by HIGH_ADDEND_1 and LOW_ADDEND_1, and HIGH_ADDEND_2 and +- LOW_ADDEND_2 respectively. The result is placed in HIGH_SUM and +- LOW_SUM. Overflow (i.e. carry out) is not stored anywhere, and is +- lost. +- +- 7) sub_ddmmss(high_difference, low_difference, high_minuend, +- low_minuend, high_subtrahend, low_subtrahend) subtracts two +- two-word unsigned integers, composed by HIGH_MINUEND_1 and +- LOW_MINUEND_1, and HIGH_SUBTRAHEND_2 and LOW_SUBTRAHEND_2 +- respectively. The result is placed in HIGH_DIFFERENCE and +- LOW_DIFFERENCE. Overflow (i.e. carry out) is not stored anywhere, +- and is lost. +- +- If any of these macros are left undefined for a particular CPU, +- C macros are used. */ +- +-#if defined (__arm__) +-#define add_ssaaaa(sh, sl, ah, al, bh, bl) \ +- __asm__ ("adds %1, %4, %5 \n\ +- adc %0, %2, %3" \ +- : "=r" ((USItype) (sh)), \ +- "=&r" ((USItype) (sl)) \ +- : "%r" ((USItype) (ah)), \ +- "rI" ((USItype) (bh)), \ +- "%r" ((USItype) (al)), \ +- "rI" ((USItype) (bl))) +-#define sub_ddmmss(sh, sl, ah, al, bh, bl) \ +- __asm__ ("subs %1, %4, %5 \n\ +- sbc %0, %2, %3" \ +- : "=r" ((USItype) (sh)), \ +- "=&r" ((USItype) (sl)) \ +- : "r" ((USItype) (ah)), \ +- "rI" ((USItype) (bh)), \ +- "r" ((USItype) (al)), \ +- "rI" ((USItype) (bl))) +-#define umul_ppmm(xh, xl, a, b) \ +- __asm__ ("%@ Inlined umul_ppmm\n" \ +- "umull %r1, %r0, %r2, %r3" \ +- : "=&r" ((USItype)(xh)), \ +- "=r" ((USItype)(xl)) \ +- : "r" ((USItype)(a)), \ +- "r" ((USItype)(b)) \ +- : "r0", "r1") +-#define count_leading_zeros(count, x) \ +- __asm__ ("clz %0, %1" : "=r"(count) : "r"(x)) +-#define UMUL_TIME 20 +-#define UDIV_TIME 100 +-#endif /* __arm__ */ +- +-#define __umulsidi3(u, v) \ +- ({DIunion __w; \ +- umul_ppmm (__w.s.high, __w.s.low, u, v); \ +- __w.ll; }) +- +-#define __udiv_qrnnd_c(q, r, n1, n0, d) \ +- do { \ +- USItype __d1, __d0, __q1, __q0; \ +- USItype __r1, __r0, __m; \ +- __d1 = __ll_highpart (d); \ +- __d0 = __ll_lowpart (d); \ +- \ +- __r1 = (n1) % __d1; \ +- __q1 = (n1) / __d1; \ +- __m = (USItype) __q1 * __d0; \ +- __r1 = __r1 * __ll_B | __ll_highpart (n0); \ +- if (__r1 < __m) \ +- { \ +- __q1--, __r1 += (d); \ +- if (__r1 >= (d)) /* i.e. we didn't get carry when adding to __r1 */\ +- if (__r1 < __m) \ +- __q1--, __r1 += (d); \ +- } \ +- __r1 -= __m; \ +- \ +- __r0 = __r1 % __d1; \ +- __q0 = __r1 / __d1; \ +- __m = (USItype) __q0 * __d0; \ +- __r0 = __r0 * __ll_B | __ll_lowpart (n0); \ +- if (__r0 < __m) \ +- { \ +- __q0--, __r0 += (d); \ +- if (__r0 >= (d)) \ +- if (__r0 < __m) \ +- __q0--, __r0 += (d); \ +- } \ +- __r0 -= __m; \ +- \ +- (q) = (USItype) __q1 * __ll_B | __q0; \ +- (r) = __r0; \ +- } while (0) +- +-#define UDIV_NEEDS_NORMALIZATION 1 +-#define udiv_qrnnd __udiv_qrnnd_c diff -Nru linux-3.2.46/debian/patches/rpi/rpi_199_2674477a4805b63b695e012b2c653869ae08302b.patch linux-3.2.46/debian/patches/rpi/rpi_199_2674477a4805b63b695e012b2c653869ae08302b.patch --- linux-3.2.46/debian/patches/rpi/rpi_199_2674477a4805b63b695e012b2c653869ae08302b.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_199_2674477a4805b63b695e012b2c653869ae08302b.patch 2013-07-26 19:34:20.000000000 +0000 @@ -0,0 +1,413 @@ +commit 2674477a4805b63b695e012b2c653869ae08302b +Author: Chris Boot +Date: Mon May 7 10:58:15 2012 +0100 + + Remove some patch backup files + + Signed-off-by: Chris Boot + +Index: linux-3.2.46/arch/arm/mach-bcm2708/include/mach/irqs.h.orig +=================================================================== +--- linux-3.2.46.orig/arch/arm/mach-bcm2708/include/mach/irqs.h.orig 2013-07-26 19:31:51.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,185 +0,0 @@ +-/* +- * arch/arm/mach-bcm2708/include/mach/irqs.h +- * +- * Copyright (C) 2010 Broadcom +- * Copyright (C) 2003 ARM Limited +- * Copyright (C) 2000 Deep Blue Solutions Ltd. +- * +- * This program is free software; you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation; either version 2 of the License, or +- * (at your option) any later version. +- * +- * This program is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with this program; if not, write to the Free Software +- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +- */ +- +-#include +- +-/* +- * IRQ interrupts definitions are the same as the INT definitions +- * held within platform.h +- */ +-#define IRQ_ARMCTRL_START 0 +-#define IRQ_TIMER0 (IRQ_ARMCTRL_START + INTERRUPT_TIMER0) +-#define IRQ_TIMER1 (IRQ_ARMCTRL_START + INTERRUPT_TIMER1) +-#define IRQ_TIMER2 (IRQ_ARMCTRL_START + INTERRUPT_TIMER2) +-#define IRQ_TIMER3 (IRQ_ARMCTRL_START + INTERRUPT_TIMER3) +-#define IRQ_CODEC0 (IRQ_ARMCTRL_START + INTERRUPT_CODEC0) +-#define IRQ_CODEC1 (IRQ_ARMCTRL_START + INTERRUPT_CODEC1) +-#define IRQ_CODEC2 (IRQ_ARMCTRL_START + INTERRUPT_CODEC2) +-#define IRQ_JPEG (IRQ_ARMCTRL_START + INTERRUPT_JPEG) +-#define IRQ_ISP (IRQ_ARMCTRL_START + INTERRUPT_ISP) +-#define IRQ_USB (IRQ_ARMCTRL_START + INTERRUPT_USB) +-#define IRQ_3D (IRQ_ARMCTRL_START + INTERRUPT_3D) +-#define IRQ_TRANSPOSER (IRQ_ARMCTRL_START + INTERRUPT_TRANSPOSER) +-#define IRQ_MULTICORESYNC0 (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC0) +-#define IRQ_MULTICORESYNC1 (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC1) +-#define IRQ_MULTICORESYNC2 (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC2) +-#define IRQ_MULTICORESYNC3 (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC3) +-#define IRQ_DMA0 (IRQ_ARMCTRL_START + INTERRUPT_DMA0) +-#define IRQ_DMA1 (IRQ_ARMCTRL_START + INTERRUPT_DMA1) +-#define IRQ_DMA2 (IRQ_ARMCTRL_START + INTERRUPT_DMA2) +-#define IRQ_DMA3 (IRQ_ARMCTRL_START + INTERRUPT_DMA3) +-#define IRQ_DMA4 (IRQ_ARMCTRL_START + INTERRUPT_DMA4) +-#define IRQ_DMA5 (IRQ_ARMCTRL_START + INTERRUPT_DMA5) +-#define IRQ_DMA6 (IRQ_ARMCTRL_START + INTERRUPT_DMA6) +-#define IRQ_DMA7 (IRQ_ARMCTRL_START + INTERRUPT_DMA7) +-#define IRQ_DMA8 (IRQ_ARMCTRL_START + INTERRUPT_DMA8) +-#define IRQ_DMA9 (IRQ_ARMCTRL_START + INTERRUPT_DMA9) +-#define IRQ_DMA10 (IRQ_ARMCTRL_START + INTERRUPT_DMA10) +-#define IRQ_DMA11 (IRQ_ARMCTRL_START + INTERRUPT_DMA11) +-#define IRQ_DMA12 (IRQ_ARMCTRL_START + INTERRUPT_DMA12) +-#define IRQ_AUX (IRQ_ARMCTRL_START + INTERRUPT_AUX) +-#define IRQ_ARM (IRQ_ARMCTRL_START + INTERRUPT_ARM) +-#define IRQ_VPUDMA (IRQ_ARMCTRL_START + INTERRUPT_VPUDMA) +-#define IRQ_HOSTPORT (IRQ_ARMCTRL_START + INTERRUPT_HOSTPORT) +-#define IRQ_VIDEOSCALER (IRQ_ARMCTRL_START + INTERRUPT_VIDEOSCALER) +-#define IRQ_CCP2TX (IRQ_ARMCTRL_START + INTERRUPT_CCP2TX) +-#define IRQ_SDC (IRQ_ARMCTRL_START + INTERRUPT_SDC) +-#define IRQ_DSI0 (IRQ_ARMCTRL_START + INTERRUPT_DSI0) +-#define IRQ_AVE (IRQ_ARMCTRL_START + INTERRUPT_AVE) +-#define IRQ_CAM0 (IRQ_ARMCTRL_START + INTERRUPT_CAM0) +-#define IRQ_CAM1 (IRQ_ARMCTRL_START + INTERRUPT_CAM1) +-#define IRQ_HDMI0 (IRQ_ARMCTRL_START + INTERRUPT_HDMI0) +-#define IRQ_HDMI1 (IRQ_ARMCTRL_START + INTERRUPT_HDMI1) +-#define IRQ_PIXELVALVE1 (IRQ_ARMCTRL_START + INTERRUPT_PIXELVALVE1) +-#define IRQ_I2CSPISLV (IRQ_ARMCTRL_START + INTERRUPT_I2CSPISLV) +-#define IRQ_DSI1 (IRQ_ARMCTRL_START + INTERRUPT_DSI1) +-#define IRQ_PWA0 (IRQ_ARMCTRL_START + INTERRUPT_PWA0) +-#define IRQ_PWA1 (IRQ_ARMCTRL_START + INTERRUPT_PWA1) +-#define IRQ_CPR (IRQ_ARMCTRL_START + INTERRUPT_CPR) +-#define IRQ_SMI (IRQ_ARMCTRL_START + INTERRUPT_SMI) +-#define IRQ_GPIO0 (IRQ_ARMCTRL_START + INTERRUPT_GPIO0) +-#define IRQ_GPIO1 (IRQ_ARMCTRL_START + INTERRUPT_GPIO1) +-#define IRQ_GPIO2 (IRQ_ARMCTRL_START + INTERRUPT_GPIO2) +-#define IRQ_GPIO3 (IRQ_ARMCTRL_START + INTERRUPT_GPIO3) +-#define IRQ_I2C (IRQ_ARMCTRL_START + INTERRUPT_I2C) +-#define IRQ_SPI (IRQ_ARMCTRL_START + INTERRUPT_SPI) +-#define IRQ_I2SPCM (IRQ_ARMCTRL_START + INTERRUPT_I2SPCM) +-#define IRQ_SDIO (IRQ_ARMCTRL_START + INTERRUPT_SDIO) +-#define IRQ_UART (IRQ_ARMCTRL_START + INTERRUPT_UART) +-#define IRQ_SLIMBUS (IRQ_ARMCTRL_START + INTERRUPT_SLIMBUS) +-#define IRQ_VEC (IRQ_ARMCTRL_START + INTERRUPT_VEC) +-#define IRQ_CPG (IRQ_ARMCTRL_START + INTERRUPT_CPG) +-#define IRQ_RNG (IRQ_ARMCTRL_START + INTERRUPT_RNG) +-#define IRQ_ARASANSDIO (IRQ_ARMCTRL_START + INTERRUPT_ARASANSDIO) +-#define IRQ_AVSPMON (IRQ_ARMCTRL_START + INTERRUPT_AVSPMON) +- +-#define IRQ_ARM_TIMER (IRQ_ARMCTRL_START + INTERRUPT_ARM_TIMER) +-#define IRQ_ARM_MAILBOX (IRQ_ARMCTRL_START + INTERRUPT_ARM_MAILBOX) +-#define IRQ_ARM_DOORBELL_0 (IRQ_ARMCTRL_START + INTERRUPT_ARM_DOORBELL_0) +-#define IRQ_ARM_DOORBELL_1 (IRQ_ARMCTRL_START + INTERRUPT_ARM_DOORBELL_1) +-#define IRQ_VPU0_HALTED (IRQ_ARMCTRL_START + INTERRUPT_VPU0_HALTED) +-#define IRQ_VPU1_HALTED (IRQ_ARMCTRL_START + INTERRUPT_VPU1_HALTED) +-#define IRQ_ILLEGAL_TYPE0 (IRQ_ARMCTRL_START + INTERRUPT_ILLEGAL_TYPE0) +-#define IRQ_ILLEGAL_TYPE1 (IRQ_ARMCTRL_START + INTERRUPT_ILLEGAL_TYPE1) +-#define IRQ_PENDING1 (IRQ_ARMCTRL_START + INTERRUPT_PENDING1) +-#define IRQ_PENDING2 (IRQ_ARMCTRL_START + INTERRUPT_PENDING2) +- +-/* +- * FIQ interrupts definitions are the same as the INT definitions. +- */ +-#define FIQ_TIMER0 INT_TIMER0 +-#define FIQ_TIMER1 INT_TIMER1 +-#define FIQ_TIMER2 INT_TIMER2 +-#define FIQ_TIMER3 INT_TIMER3 +-#define FIQ_CODEC0 INT_CODEC0 +-#define FIQ_CODEC1 INT_CODEC1 +-#define FIQ_CODEC2 INT_CODEC2 +-#define FIQ_JPEG INT_JPEG +-#define FIQ_ISP INT_ISP +-#define FIQ_USB INT_USB +-#define FIQ_3D INT_3D +-#define FIQ_TRANSPOSER INT_TRANSPOSER +-#define FIQ_MULTICORESYNC0 INT_MULTICORESYNC0 +-#define FIQ_MULTICORESYNC1 INT_MULTICORESYNC1 +-#define FIQ_MULTICORESYNC2 INT_MULTICORESYNC2 +-#define FIQ_MULTICORESYNC3 INT_MULTICORESYNC3 +-#define FIQ_DMA0 INT_DMA0 +-#define FIQ_DMA1 INT_DMA1 +-#define FIQ_DMA2 INT_DMA2 +-#define FIQ_DMA3 INT_DMA3 +-#define FIQ_DMA4 INT_DMA4 +-#define FIQ_DMA5 INT_DMA5 +-#define FIQ_DMA6 INT_DMA6 +-#define FIQ_DMA7 INT_DMA7 +-#define FIQ_DMA8 INT_DMA8 +-#define FIQ_DMA9 INT_DMA9 +-#define FIQ_DMA10 INT_DMA10 +-#define FIQ_DMA11 INT_DMA11 +-#define FIQ_DMA12 INT_DMA12 +-#define FIQ_AUX INT_AUX +-#define FIQ_ARM INT_ARM +-#define FIQ_VPUDMA INT_VPUDMA +-#define FIQ_HOSTPORT INT_HOSTPORT +-#define FIQ_VIDEOSCALER INT_VIDEOSCALER +-#define FIQ_CCP2TX INT_CCP2TX +-#define FIQ_SDC INT_SDC +-#define FIQ_DSI0 INT_DSI0 +-#define FIQ_AVE INT_AVE +-#define FIQ_CAM0 INT_CAM0 +-#define FIQ_CAM1 INT_CAM1 +-#define FIQ_HDMI0 INT_HDMI0 +-#define FIQ_HDMI1 INT_HDMI1 +-#define FIQ_PIXELVALVE1 INT_PIXELVALVE1 +-#define FIQ_I2CSPISLV INT_I2CSPISLV +-#define FIQ_DSI1 INT_DSI1 +-#define FIQ_PWA0 INT_PWA0 +-#define FIQ_PWA1 INT_PWA1 +-#define FIQ_CPR INT_CPR +-#define FIQ_SMI INT_SMI +-#define FIQ_GPIO0 INT_GPIO0 +-#define FIQ_GPIO1 INT_GPIO1 +-#define FIQ_GPIO2 INT_GPIO2 +-#define FIQ_GPIO3 INT_GPIO3 +-#define FIQ_I2C INT_I2C +-#define FIQ_SPI INT_SPI +-#define FIQ_I2SPCM INT_I2SPCM +-#define FIQ_SDIO INT_SDIO +-#define FIQ_UART INT_UART +-#define FIQ_SLIMBUS INT_SLIMBUS +-#define FIQ_VEC INT_VEC +-#define FIQ_CPG INT_CPG +-#define FIQ_RNG INT_RNG +-#define FIQ_ARASANSDIO INT_ARASANSDIO +-#define FIQ_AVSPMON INT_AVSPMON +- +-#define FIQ_ARM_TIMER INT_ARM_TIMER +-#define FIQ_ARM_MAILBOX INT_ARM_MAILBOX +-#define FIQ_ARM_DOORBELL_0 INT_ARM_DOORBELL_0 +-#define FIQ_ARM_DOORBELL_1 INT_ARM_DOORBELL_1 +-#define FIQ_VPU0_HALTED INT_VPU0_HALTED +-#define FIQ_VPU1_HALTED INT_VPU1_HALTED +-#define FIQ_ILLEGAL_TYPE0 INT_ILLEGAL_TYPE0 +-#define FIQ_ILLEGAL_TYPE1 INT_ILLEGAL_TYPE1 +-#define FIQ_PENDING1 INT_PENDING1 +-#define FIQ_PENDING2 INT_PENDING2 +- +-#define NR_IRQS (64 + 21) +Index: linux-3.2.46/arch/arm/mach-bcm2708/include/mach/platform.h.orig +=================================================================== +--- linux-3.2.46.orig/arch/arm/mach-bcm2708/include/mach/platform.h.orig 2013-07-26 19:31:51.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,210 +0,0 @@ +-/* +- * arch/arm/mach-bcm2708/include/mach/platform.h +- * +- * Copyright (C) 2010 Broadcom +- * +- * This program is free software; you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation; either version 2 of the License, or +- * (at your option) any later version. +- * +- * This program is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with this program; if not, write to the Free Software +- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +- */ +- +-#ifndef _BCM2708_PLATFORM_H +-#define _BCM2708_PLATFORM_H +- +- +-/* macros to get at IO space when running virtually */ +-#define IO_ADDRESS(x) (((x) & 0x0fffffff) + (((x) >> 4) & 0x0f000000) + 0xf0000000) +- +-#define __io_address(a) __io(IO_ADDRESS(a)) +- +- +-/* +- * SDRAM +- */ +-#define BCM2708_SDRAM_BASE 0x00000000 +- +-/* +- * Logic expansion modules +- * +- */ +- +- +-/* ------------------------------------------------------------------------ +- * BCM2708 ARMCTRL Registers +- * ------------------------------------------------------------------------ +- */ +- +-#define HW_REGISTER_RW(addr) (addr) +-#define HW_REGISTER_RO(addr) (addr) +- +-#include "arm_control.h" +-#undef ARM_BASE +- +-/* +- * Definitions and addresses for the ARM CONTROL logic +- * This file is manually generated. +- */ +- +-#define BCM2708_PERI_BASE 0x20000000 +-#define ST_BASE (BCM2708_PERI_BASE + 0x3000) /* System Timer */ +-#define DMA_BASE (BCM2708_PERI_BASE + 0x7000) /* DMA controller */ +-#define ARM_BASE (BCM2708_PERI_BASE + 0xB000) /* BCM2708 ARM control block */ +-#define PM_BASE (BCM2708_PERI_BASE + 0x100000) /* Power Management, Reset controller and Watchdog registers */ +-#define GPIO_BASE (BCM2708_PERI_BASE + 0x200000) /* GPIO */ +-#define UART0_BASE (BCM2708_PERI_BASE + 0x201000) /* Uart 0 */ +-#define MMCI0_BASE (BCM2708_PERI_BASE + 0x202000) /* MMC interface */ +-#define UART1_BASE (BCM2708_PERI_BASE + 0x215000) /* Uart 1 */ +-#define EMMC_BASE (BCM2708_PERI_BASE + 0x300000) /* eMMC interface */ +-#define SMI_BASE (BCM2708_PERI_BASE + 0x600000) /* SMI */ +-#define USB_BASE (BCM2708_PERI_BASE + 0x980000) /* DTC_OTG USB controller */ +- +- +-#define ARMCTRL_BASE (ARM_BASE + 0x000) +-#define ARMCTRL_IC_BASE (ARM_BASE + 0x200) /* ARM interrupt controller */ +-#define ARMCTRL_TIMER0_1_BASE (ARM_BASE + 0x400) /* Timer 0 and 1 */ +-#define ARMCTRL_0_SBM_BASE (ARM_BASE + 0x800) /* User 0 (ARM)'s Semaphores Doorbells and Mailboxes */ +- +- +-/* +- * Interrupt assignments +- */ +- +-#define ARM_IRQ1_BASE 0 +-#define INTERRUPT_TIMER0 (ARM_IRQ1_BASE + 0) +-#define INTERRUPT_TIMER1 (ARM_IRQ1_BASE + 1) +-#define INTERRUPT_TIMER2 (ARM_IRQ1_BASE + 2) +-#define INTERRUPT_TIMER3 (ARM_IRQ1_BASE + 3) +-#define INTERRUPT_CODEC0 (ARM_IRQ1_BASE + 4) +-#define INTERRUPT_CODEC1 (ARM_IRQ1_BASE + 5) +-#define INTERRUPT_CODEC2 (ARM_IRQ1_BASE + 6) +-#define INTERRUPT_VC_JPEG (ARM_IRQ1_BASE + 7) +-#define INTERRUPT_ISP (ARM_IRQ1_BASE + 8) +-#define INTERRUPT_VC_USB (ARM_IRQ1_BASE + 9) +-#define INTERRUPT_VC_3D (ARM_IRQ1_BASE + 10) +-#define INTERRUPT_TRANSPOSER (ARM_IRQ1_BASE + 11) +-#define INTERRUPT_MULTICORESYNC0 (ARM_IRQ1_BASE + 12) +-#define INTERRUPT_MULTICORESYNC1 (ARM_IRQ1_BASE + 13) +-#define INTERRUPT_MULTICORESYNC2 (ARM_IRQ1_BASE + 14) +-#define INTERRUPT_MULTICORESYNC3 (ARM_IRQ1_BASE + 15) +-#define INTERRUPT_DMA0 (ARM_IRQ1_BASE + 16) +-#define INTERRUPT_DMA1 (ARM_IRQ1_BASE + 17) +-#define INTERRUPT_VC_DMA2 (ARM_IRQ1_BASE + 18) +-#define INTERRUPT_VC_DMA3 (ARM_IRQ1_BASE + 19) +-#define INTERRUPT_DMA4 (ARM_IRQ1_BASE + 20) +-#define INTERRUPT_DMA5 (ARM_IRQ1_BASE + 21) +-#define INTERRUPT_DMA6 (ARM_IRQ1_BASE + 22) +-#define INTERRUPT_DMA7 (ARM_IRQ1_BASE + 23) +-#define INTERRUPT_DMA8 (ARM_IRQ1_BASE + 24) +-#define INTERRUPT_DMA9 (ARM_IRQ1_BASE + 25) +-#define INTERRUPT_DMA10 (ARM_IRQ1_BASE + 26) +-#define INTERRUPT_DMA11 (ARM_IRQ1_BASE + 27) +-#define INTERRUPT_DMA12 (ARM_IRQ1_BASE + 28) +-#define INTERRUPT_AUX (ARM_IRQ1_BASE + 29) +-#define INTERRUPT_ARM (ARM_IRQ1_BASE + 30) +-#define INTERRUPT_VPUDMA (ARM_IRQ1_BASE + 31) +- +-#define ARM_IRQ2_BASE 32 +-#define INTERRUPT_HOSTPORT (ARM_IRQ2_BASE + 0) +-#define INTERRUPT_VIDEOSCALER (ARM_IRQ2_BASE + 1) +-#define INTERRUPT_CCP2TX (ARM_IRQ2_BASE + 2) +-#define INTERRUPT_SDC (ARM_IRQ2_BASE + 3) +-#define INTERRUPT_DSI0 (ARM_IRQ2_BASE + 4) +-#define INTERRUPT_AVE (ARM_IRQ2_BASE + 5) +-#define INTERRUPT_CAM0 (ARM_IRQ2_BASE + 6) +-#define INTERRUPT_CAM1 (ARM_IRQ2_BASE + 7) +-#define INTERRUPT_HDMI0 (ARM_IRQ2_BASE + 8) +-#define INTERRUPT_HDMI1 (ARM_IRQ2_BASE + 9) +-#define INTERRUPT_PIXELVALVE1 (ARM_IRQ2_BASE + 10) +-#define INTERRUPT_I2CSPISLV (ARM_IRQ2_BASE + 11) +-#define INTERRUPT_DSI1 (ARM_IRQ2_BASE + 12) +-#define INTERRUPT_PWA0 (ARM_IRQ2_BASE + 13) +-#define INTERRUPT_PWA1 (ARM_IRQ2_BASE + 14) +-#define INTERRUPT_CPR (ARM_IRQ2_BASE + 15) +-#define INTERRUPT_SMI (ARM_IRQ2_BASE + 16) +-#define INTERRUPT_GPIO0 (ARM_IRQ2_BASE + 17) +-#define INTERRUPT_GPIO1 (ARM_IRQ2_BASE + 18) +-#define INTERRUPT_GPIO2 (ARM_IRQ2_BASE + 19) +-#define INTERRUPT_GPIO3 (ARM_IRQ2_BASE + 20) +-#define INTERRUPT_VC_I2C (ARM_IRQ2_BASE + 21) +-#define INTERRUPT_VC_SPI (ARM_IRQ2_BASE + 22) +-#define INTERRUPT_VC_I2SPCM (ARM_IRQ2_BASE + 23) +-#define INTERRUPT_VC_SDIO (ARM_IRQ2_BASE + 24) +-#define INTERRUPT_VC_UART (ARM_IRQ2_BASE + 25) +-#define INTERRUPT_SLIMBUS (ARM_IRQ2_BASE + 26) +-#define INTERRUPT_VEC (ARM_IRQ2_BASE + 27) +-#define INTERRUPT_CPG (ARM_IRQ2_BASE + 28) +-#define INTERRUPT_RNG (ARM_IRQ2_BASE + 29) +-#define INTERRUPT_VC_ARASANSDIO (ARM_IRQ2_BASE + 30) +-#define INTERRUPT_AVSPMON (ARM_IRQ2_BASE + 31) +- +-#define ARM_IRQ0_BASE 64 +-#define INTERRUPT_ARM_TIMER (ARM_IRQ0_BASE + 0) +-#define INTERRUPT_ARM_MAILBOX (ARM_IRQ0_BASE + 1) +-#define INTERRUPT_ARM_DOORBELL_0 (ARM_IRQ0_BASE + 2) +-#define INTERRUPT_ARM_DOORBELL_1 (ARM_IRQ0_BASE + 3) +-#define INTERRUPT_VPU0_HALTED (ARM_IRQ0_BASE + 4) +-#define INTERRUPT_VPU1_HALTED (ARM_IRQ0_BASE + 5) +-#define INTERRUPT_ILLEGAL_TYPE0 (ARM_IRQ0_BASE + 6) +-#define INTERRUPT_ILLEGAL_TYPE1 (ARM_IRQ0_BASE + 7) +-#define INTERRUPT_PENDING1 (ARM_IRQ0_BASE + 8) +-#define INTERRUPT_PENDING2 (ARM_IRQ0_BASE + 9) +-#define INTERRUPT_JPEG (ARM_IRQ0_BASE + 10) +-#define INTERRUPT_USB (ARM_IRQ0_BASE + 11) +-#define INTERRUPT_3D (ARM_IRQ0_BASE + 12) +-#define INTERRUPT_DMA2 (ARM_IRQ0_BASE + 13) +-#define INTERRUPT_DMA3 (ARM_IRQ0_BASE + 14) +-#define INTERRUPT_I2C (ARM_IRQ0_BASE + 15) +-#define INTERRUPT_SPI (ARM_IRQ0_BASE + 16) +-#define INTERRUPT_I2SPCM (ARM_IRQ0_BASE + 17) +-#define INTERRUPT_SDIO (ARM_IRQ0_BASE + 18) +-#define INTERRUPT_UART (ARM_IRQ0_BASE + 19) +-#define INTERRUPT_ARASANSDIO (ARM_IRQ0_BASE + 20) +- +-#define MAXIRQNUM (32 + 32 + 20) +-#define MAXFIQNUM (32 + 32 + 20) +- +-#define MAX_TIMER 2 +-#define MAX_PERIOD 699050 +-#define TICKS_PER_uSEC 1 +- +-/* +- * These are useconds NOT ticks. +- * +- */ +-#define mSEC_1 1000 +-#define mSEC_5 (mSEC_1 * 5) +-#define mSEC_10 (mSEC_1 * 10) +-#define mSEC_25 (mSEC_1 * 25) +-#define SEC_1 (mSEC_1 * 1000) +- +-/* +- * Watchdog +- */ +-#define PM_RSTC (PM_BASE+0x1c) +-#define PM_WDOG (PM_BASE+0x24) +- +-#define PM_WDOG_RESET 0000000000 +-#define PM_PASSWORD 0x5a000000 +-#define PM_WDOG_TIME_SET 0x000fffff +-#define PM_RSTC_WRCFG_CLR 0xffffffcf +-#define PM_RSTC_WRCFG_SET 0x00000030 +-#define PM_RSTC_WRCFG_FULL_RESET 0x00000020 +-#define PM_RSTC_RESET 0x00000102 +- +- +- +- +- +-#endif +- +-/* END */ diff -Nru linux-3.2.46/debian/patches/rpi/rpi_200_ac15023c8b298c38d8def9c1ca3b21bed9fd9238.patch linux-3.2.46/debian/patches/rpi/rpi_200_ac15023c8b298c38d8def9c1ca3b21bed9fd9238.patch --- linux-3.2.46/debian/patches/rpi/rpi_200_ac15023c8b298c38d8def9c1ca3b21bed9fd9238.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_200_ac15023c8b298c38d8def9c1ca3b21bed9fd9238.patch 2013-07-26 19:34:21.000000000 +0000 @@ -0,0 +1,39 @@ +commit ac15023c8b298c38d8def9c1ca3b21bed9fd9238 +Author: Chris Boot +Date: Mon May 7 11:21:15 2012 +0100 + + mach-bcm2708: fix mach/debug-macro.S so that early printk works + + Not sure what the original code was trying to do as it was completely + wrong on many levels. This patch fixes the macro to return the correct + physical and virtual addresses of the PL011 UART on the RPi. + + Note that you need to boot the compressed kernel (zImage) so that the + UART is configured at boot, or your kernel will hang when it tries to + access the UART. + + Signed-off-by: Chris Boot + +Index: linux-3.2.46/arch/arm/mach-bcm2708/include/mach/debug-macro.S +=================================================================== +--- linux-3.2.46.orig/arch/arm/mach-bcm2708/include/mach/debug-macro.S 2013-07-26 19:31:51.000000000 +0000 ++++ linux-3.2.46/arch/arm/mach-bcm2708/include/mach/debug-macro.S 2013-07-26 19:34:20.000000000 +0000 +@@ -12,13 +12,11 @@ + * + */ + +- .macro addruart, rx, tmp +- mrc p15, 0, \rx, c1, c0 +- tst \rx, #1 @ MMU enabled? +- moveq \rx, #0x08000000 +- movne \rx, #0xf8000000 @ virtual base +- orr \rx, \rx, #0x00200000 +- orr \rx, \rx, #0x00001000 ++#include ++ ++ .macro addruart, rp, rv ++ ldr \rp, =UART0_BASE ++ ldr \rv, =IO_ADDRESS(UART0_BASE) + .endm + + #include diff -Nru linux-3.2.46/debian/patches/rpi/rpi_201_89816b2638f7232913df85499592d1422e0fb453.patch linux-3.2.46/debian/patches/rpi/rpi_201_89816b2638f7232913df85499592d1422e0fb453.patch --- linux-3.2.46/debian/patches/rpi/rpi_201_89816b2638f7232913df85499592d1422e0fb453.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_201_89816b2638f7232913df85499592d1422e0fb453.patch 2013-07-26 19:34:22.000000000 +0000 @@ -0,0 +1,20 @@ +commit 89816b2638f7232913df85499592d1422e0fb453 +Author: Chris Boot +Date: Tue May 8 14:49:59 2012 +0100 + + sound/arm/bcm2835.c: add linux/module.h include + + Signed-off-by: Chris Boot + +Index: linux-3.2.46/sound/arm/bcm2835.c +=================================================================== +--- linux-3.2.46.orig/sound/arm/bcm2835.c 2013-07-26 19:32:35.000000000 +0000 ++++ linux-3.2.46/sound/arm/bcm2835.c 2013-07-26 19:34:22.000000000 +0000 +@@ -16,6 +16,7 @@ + + #include + #include ++#include + + #include "bcm2835.h" + diff -Nru linux-3.2.46/debian/patches/rpi/rpi_202_7a681f9eb4fa7484956ea347e2c35f12d151aba4.patch linux-3.2.46/debian/patches/rpi/rpi_202_7a681f9eb4fa7484956ea347e2c35f12d151aba4.patch --- linux-3.2.46/debian/patches/rpi/rpi_202_7a681f9eb4fa7484956ea347e2c35f12d151aba4.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_202_7a681f9eb4fa7484956ea347e2c35f12d151aba4.patch 2013-07-26 19:34:24.000000000 +0000 @@ -0,0 +1,18 @@ +commit 7a681f9eb4fa7484956ea347e2c35f12d151aba4 +Author: Chris Boot +Date: Tue May 8 14:50:35 2012 +0100 + + vcos: add linux/kernel.h include + +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/linuxkernel/vcos_platform_types.h +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vcos/linuxkernel/vcos_platform_types.h 2013-07-26 19:32:07.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/linuxkernel/vcos_platform_types.h 2013-07-26 19:34:23.000000000 +0000 +@@ -26,6 +26,7 @@ + #include + #include + #include ++#include + + #define VCOSPRE_ extern + #define VCOSPOST_ diff -Nru linux-3.2.46/debian/patches/rpi/rpi_203_11fd94ce307965b3ae9574343059fb5c2ffbfc65.patch linux-3.2.46/debian/patches/rpi/rpi_203_11fd94ce307965b3ae9574343059fb5c2ffbfc65.patch --- linux-3.2.46/debian/patches/rpi/rpi_203_11fd94ce307965b3ae9574343059fb5c2ffbfc65.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_203_11fd94ce307965b3ae9574343059fb5c2ffbfc65.patch 2013-07-26 19:34:25.000000000 +0000 @@ -0,0 +1,150 @@ +commit 11fd94ce307965b3ae9574343059fb5c2ffbfc65 +Author: Chris Boot +Date: Tue May 8 14:51:16 2012 +0100 + + bcm2708: update for 3.2 kernel + + Signed-off-by: Chris Boot + + Conflicts: + + arch/arm/Kconfig.debug + arch/arm/mach-bcm2708/include/mach/memory.h + +Index: linux-3.2.46/arch/arm/Kconfig +=================================================================== +--- linux-3.2.46.orig/arch/arm/Kconfig 2013-07-26 19:31:51.000000000 +0000 ++++ linux-3.2.46/arch/arm/Kconfig 2013-07-26 19:34:24.000000000 +0000 +@@ -962,6 +962,8 @@ + select CPU_V6 + select ARM_AMBA + select HAVE_CLK ++ select HAVE_SCHED_CLOCK ++ select NEED_MACH_MEMORY_H + select CLKDEV_LOOKUP + select GENERIC_CLOCKEVENTS + select ARM_ERRATA_411920 +Index: linux-3.2.46/arch/arm/Kconfig.debug +=================================================================== +--- linux-3.2.46.orig/arch/arm/Kconfig.debug 2013-05-30 13:35:16.000000000 +0000 ++++ linux-3.2.46/arch/arm/Kconfig.debug 2013-07-26 19:34:24.000000000 +0000 +@@ -247,6 +247,14 @@ + their output to the standard serial port on the RealView + PB1176 platform. + ++ config DEBUG_BCM2708_UART0 ++ bool "Broadcom BCM2708 UART0 (PL011)" ++ depends on MACH_BCM2708 ++ help ++ Say Y here if you want the debug print routines to direct ++ their output to UART 0. The port must have been initialised ++ by the boot-loader before use. ++ + endchoice + + config EARLY_PRINTK +Index: linux-3.2.46/arch/arm/mach-bcm2708/bcm2708.c +=================================================================== +--- linux-3.2.46.orig/arch/arm/mach-bcm2708/bcm2708.c 2013-07-26 19:34:10.000000000 +0000 ++++ linux-3.2.46/arch/arm/mach-bcm2708/bcm2708.c 2013-07-26 19:34:24.000000000 +0000 +@@ -23,7 +23,7 @@ + #include + #include + #include +-#include ++#include + #include + #include + #include +@@ -34,16 +34,13 @@ + #include + + #include +-#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,38) + #include +-#else +-#include +-#endif + #include + #include + #include + #include + #include ++#include + + #include + #include +@@ -72,6 +69,8 @@ + */ + #define DMA_MASK_BITS_COMMON 32 + ++static DEFINE_CLOCK_DATA(cd); ++ + /* command line parameters */ + static unsigned boardrev, serial; + +@@ -175,8 +174,15 @@ + + unsigned long long sched_clock(void) + { +- return clocksource_cyc2ns(clocksource_stc.read(&clocksource_stc), +- clocksource_stc.mult, clocksource_stc.shift); ++ u32 cyc = clocksource_stc.read(&clocksource_stc); ++ return cyc_to_fixed_sched_clock(&cd, cyc, clocksource_stc.mask, ++ clocksource_stc.mult, clocksource_stc.shift); ++} ++ ++static void notrace bcm2708_update_sched_clock(void) ++{ ++ u32 cyc = clocksource_stc.read(&clocksource_stc); ++ update_sched_clock(&cd, cyc, clocksource_stc.mask); + } + + /* +@@ -696,6 +702,9 @@ + */ + setup_irq(IRQ_TIMER3, &bcm2708_timer_irq); + ++ init_fixed_sched_clock(&cd, bcm2708_update_sched_clock, 32, ++ STC_FREQ_HZ, clocksource_stc.mult, clocksource_stc.shift); ++ + timer0_clockevent.mult = + div_sc(STC_FREQ_HZ, NSEC_PER_SEC, timer0_clockevent.shift); + timer0_clockevent.max_delta_ns = +Index: linux-3.2.46/arch/arm/mach-bcm2708/include/mach/debug-macro.S +=================================================================== +--- linux-3.2.46.orig/arch/arm/mach-bcm2708/include/mach/debug-macro.S 2013-07-26 19:34:20.000000000 +0000 ++++ linux-3.2.46/arch/arm/mach-bcm2708/include/mach/debug-macro.S 2013-07-26 19:34:24.000000000 +0000 +@@ -14,7 +14,7 @@ + + #include + +- .macro addruart, rp, rv ++ .macro addruart, rp, rv, tmp + ldr \rp, =UART0_BASE + ldr \rv, =IO_ADDRESS(UART0_BASE) + .endm +Index: linux-3.2.46/arch/arm/mach-bcm2708/include/mach/memory.h +=================================================================== +--- linux-3.2.46.orig/arch/arm/mach-bcm2708/include/mach/memory.h 2013-07-26 19:33:04.000000000 +0000 ++++ linux-3.2.46/arch/arm/mach-bcm2708/include/mach/memory.h 2013-07-26 19:34:24.000000000 +0000 +@@ -32,8 +32,8 @@ + /* + * Physical DRAM offset. + */ +-#define PLAT_PHYS_OFFSET UL(0x00000000) +-#define ARMMEM_OFFSET UL(0x00000000) /* offset in VC of ARM memory */ ++#define PLAT_PHYS_OFFSET UL(0x00000000) ++#define VC_ARMMEM_OFFSET UL(0x00000000) /* offset in VC of ARM memory */ + + #ifdef CONFIG_BCM2708_NOL2CACHE + #define _REAL_BUS_OFFSET UL(0xC0000000) /* don't use L1 or L2 caches */ +@@ -48,7 +48,7 @@ + * WARNING: this only works because the ARM is given memory at a fixed location + * (ARMMEM_OFFSET) + */ +-#define BUS_OFFSET (ARMMEM_OFFSET + _REAL_BUS_OFFSET) ++#define BUS_OFFSET (VC_ARMMEM_OFFSET + _REAL_BUS_OFFSET) + #define __virt_to_bus(x) ((x) + (BUS_OFFSET - PAGE_OFFSET)) + #define __bus_to_virt(x) ((x) - (BUS_OFFSET - PAGE_OFFSET)) + #define __pfn_to_bus(x) (__pfn_to_phys(x) + (BUS_OFFSET - PLAT_PHYS_OFFSET)) diff -Nru linux-3.2.46/debian/patches/rpi/rpi_204_1574e957d51afddc59ae0912e41b57320dedc0c9.patch linux-3.2.46/debian/patches/rpi/rpi_204_1574e957d51afddc59ae0912e41b57320dedc0c9.patch --- linux-3.2.46/debian/patches/rpi/rpi_204_1574e957d51afddc59ae0912e41b57320dedc0c9.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_204_1574e957d51afddc59ae0912e41b57320dedc0c9.patch 2013-07-26 19:34:27.000000000 +0000 @@ -0,0 +1,64 @@ +commit 1574e957d51afddc59ae0912e41b57320dedc0c9 +Author: Chris Boot +Date: Sun Jul 15 16:52:11 2012 +0100 + + bcm2708: use a constant SC_MULT / SC_SHIFT + + The calculated values somehow don't agree with the sched_clock code and + we end up with warnings like: + + sched_clock: wrong multiply/shift: 2097152000>>21 vs calculated 4194304000>>22 + sched_clock: fix multiply/shift to avoid scheduler hiccups + + So use the constant values much like arch/arm/mach-tegra/timer.c does. + + Signed-off-by: Chris Boot + +Index: linux-3.2.46/arch/arm/mach-bcm2708/bcm2708.c +=================================================================== +--- linux-3.2.46.orig/arch/arm/mach-bcm2708/bcm2708.c 2013-07-26 19:34:24.000000000 +0000 ++++ linux-3.2.46/arch/arm/mach-bcm2708/bcm2708.c 2013-07-26 19:34:26.000000000 +0000 +@@ -141,9 +141,16 @@ + iotable_init(bcm2708_io_desc, ARRAY_SIZE(bcm2708_io_desc)); + } + +-// The STC is a free running counter that increments at the rate of 1MHz ++/* The STC is a free running counter that increments at the rate of 1MHz */ + #define STC_FREQ_HZ 1000000 + ++/* ++ * Constants generated by clocks_calc_mult_shift(m, s, 1MHz, NSEC_PER_SEC, 60). ++ * This gives a resolution of about 1us and a wrap period of about 1h11min. ++ */ ++#define SC_MULT 4194304000u ++#define SC_SHIFT 22 ++ + static cycle_t stc_read_cycles(struct clocksource *cs) + { + /* STC: a free running counter that increments at the rate of 1MHz */ +@@ -165,7 +172,6 @@ + + static void __init bcm2708_clocksource_init(void) + { +- // calculate .shift and .mult values and register clocksource + if (clocksource_register_hz(&clocksource_stc, STC_FREQ_HZ)) { + printk(KERN_ERR "timer: failed to initialize clock " + "source %s\n", clocksource_stc.name); +@@ -176,7 +182,7 @@ + { + u32 cyc = clocksource_stc.read(&clocksource_stc); + return cyc_to_fixed_sched_clock(&cd, cyc, clocksource_stc.mask, +- clocksource_stc.mult, clocksource_stc.shift); ++ SC_MULT, SC_SHIFT); + } + + static void notrace bcm2708_update_sched_clock(void) +@@ -703,7 +709,7 @@ + setup_irq(IRQ_TIMER3, &bcm2708_timer_irq); + + init_fixed_sched_clock(&cd, bcm2708_update_sched_clock, 32, +- STC_FREQ_HZ, clocksource_stc.mult, clocksource_stc.shift); ++ STC_FREQ_HZ, SC_MULT, SC_SHIFT); + + timer0_clockevent.mult = + div_sc(STC_FREQ_HZ, NSEC_PER_SEC, timer0_clockevent.shift); diff -Nru linux-3.2.46/debian/patches/rpi/rpi_205_04e71eb30083d387cdaabb046bedb3174999f7cd.patch linux-3.2.46/debian/patches/rpi/rpi_205_04e71eb30083d387cdaabb046bedb3174999f7cd.patch --- linux-3.2.46/debian/patches/rpi/rpi_205_04e71eb30083d387cdaabb046bedb3174999f7cd.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_205_04e71eb30083d387cdaabb046bedb3174999f7cd.patch 2013-07-26 19:34:28.000000000 +0000 @@ -0,0 +1,45 @@ +commit 04e71eb30083d387cdaabb046bedb3174999f7cd +Author: Dom Cobley +Date: Tue Jul 31 16:42:03 2012 +0100 + + Sync with bootc's file + +Index: linux-3.2.46/arch/arm/mach-bcm2708/power.c +=================================================================== +--- linux-3.2.46.orig/arch/arm/mach-bcm2708/power.c 2013-07-26 19:33:08.000000000 +0000 ++++ linux-3.2.46/arch/arm/mach-bcm2708/power.c 2013-07-26 19:34:27.000000000 +0000 +@@ -14,7 +14,6 @@ + #include + #include + #include +-#include + #include + #include + #include +@@ -97,6 +96,7 @@ + bcm_mailbox_write(MBOX_CHAN_POWER, + global_request << 4); + ++ /* Wait for a response during power-up */ + if (global_request & ~g_state.global_request) { + rc = bcm_mailbox_read(MBOX_CHAN_POWER, + &actual); +@@ -111,14 +111,14 @@ + + if (rc == 0) { + if (actual != global_request) { +- printk(KERN_INFO +- "%s: Fail: prev global %x, new global %x, actual %x request %x, others_request %x\n", ++ printk(KERN_ERR ++ "%s: prev global %x, new global %x, actual %x, request %x, others_request %x\n", + __func__, + g_state.global_request, + global_request, actual, request, others_request); + /* A failure */ +- // BUG_ON((others_request & actual) +- // != others_request); ++ BUG_ON((others_request & actual) ++ != others_request); + request &= actual; + rc = -EIO; + } diff -Nru linux-3.2.46/debian/patches/rpi/rpi_206_3a475430169654ef1beaf475d122ade24433ae16.patch linux-3.2.46/debian/patches/rpi/rpi_206_3a475430169654ef1beaf475d122ade24433ae16.patch --- linux-3.2.46/debian/patches/rpi/rpi_206_3a475430169654ef1beaf475d122ade24433ae16.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_206_3a475430169654ef1beaf475d122ade24433ae16.patch 2013-07-26 19:34:29.000000000 +0000 @@ -0,0 +1,47 @@ +commit 3a475430169654ef1beaf475d122ade24433ae16 +Author: Grigori Goronzy +Date: Thu Jun 21 00:57:59 2012 +0200 + + sdhci-bcm2708: use extension FIFO to buffer DMA transfers + + The additional FIFO might speed up transfers in some cases. + +Index: linux-3.2.46/drivers/mmc/host/sdhci-bcm2708.c +=================================================================== +--- linux-3.2.46.orig/drivers/mmc/host/sdhci-bcm2708.c 2013-07-26 19:34:06.000000000 +0000 ++++ linux-3.2.46/drivers/mmc/host/sdhci-bcm2708.c 2013-07-26 19:34:29.000000000 +0000 +@@ -79,6 +79,8 @@ + #define POWER_LAZY_OFF 1 + #define POWER_ON 2 + ++#define REG_EXRDFIFO_EN 0x80 ++#define REG_EXRDFIFO_CFG 0x84 + + /*****************************************************************************\ + * * +@@ -967,10 +969,12 @@ + int on = simple_strtol(buf, NULL, 0); + if (on) { + host->flags |= SDHCI_USE_PLATDMA; ++ sdhci_bcm2708_writel(host, 1, REG_EXRDFIFO_EN); + printk(KERN_INFO "%s: DMA enabled\n", + mmc_hostname(host->mmc)); + } else { + host->flags &= ~(SDHCI_USE_PLATDMA | SDHCI_REQ_USE_DMA); ++ sdhci_bcm2708_writel(host, 0, REG_EXRDFIFO_EN); + printk(KERN_INFO "%s: DMA disabled\n", + mmc_hostname(host->mmc)); + } +@@ -1399,6 +1403,12 @@ + ret = device_create_file(&pdev->dev, &dev_attr_dma_wait); + ret = device_create_file(&pdev->dev, &dev_attr_status); + ++#ifdef CONFIG_MMC_SDHCI_BCM2708_DMA ++ /* enable extension fifo for paced DMA transfers */ ++ sdhci_bcm2708_writel(host, 1, REG_EXRDFIFO_EN); ++ sdhci_bcm2708_writel(host, 4, REG_EXRDFIFO_CFG); ++#endif ++ + printk(KERN_INFO "%s: BCM2708 SDHC host at 0x%08llx DMA %d IRQ %d\n", + mmc_hostname(host->mmc), (unsigned long long)iomem->start, + host_priv->dma_chan, host_priv->dma_irq); diff -Nru linux-3.2.46/debian/patches/rpi/rpi_207_31c350f3e5f77dfd7b36d7428420c545a255a1cc.patch linux-3.2.46/debian/patches/rpi/rpi_207_31c350f3e5f77dfd7b36d7428420c545a255a1cc.patch --- linux-3.2.46/debian/patches/rpi/rpi_207_31c350f3e5f77dfd7b36d7428420c545a255a1cc.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_207_31c350f3e5f77dfd7b36d7428420c545a255a1cc.patch 2013-07-26 19:34:31.000000000 +0000 @@ -0,0 +1,50 @@ +commit 31c350f3e5f77dfd7b36d7428420c545a255a1cc +Author: Grigori Goronzy +Date: Tue Jul 31 23:18:12 2012 +0200 + + sdhci-bcm2708: use multiblock-type transfers for single blocks + + There are issues with both single block reads (missed completion) + and writes (data loss in some cases!). Just don't do single block + transfers anymore, and treat them like multiblock transfers. This + adds a quirk for this and uses it. + +Index: linux-3.2.46/drivers/mmc/card/block.c +=================================================================== +--- linux-3.2.46.orig/drivers/mmc/card/block.c 2013-05-30 13:35:16.000000000 +0000 ++++ linux-3.2.46/drivers/mmc/card/block.c 2013-07-26 19:34:30.000000000 +0000 +@@ -1075,7 +1075,7 @@ + brq->data.blocks = 1; + } + +- if (brq->data.blocks > 1 || do_rel_wr) { ++ if (brq->data.blocks > 1 || do_rel_wr || card->host->caps2 & MMC_CAP2_FORCE_MULTIBLOCK) { + /* SPI multiblock writes terminate using a special + * token, not a STOP_TRANSMISSION request. + */ +Index: linux-3.2.46/drivers/mmc/host/sdhci-bcm2708.c +=================================================================== +--- linux-3.2.46.orig/drivers/mmc/host/sdhci-bcm2708.c 2013-07-26 19:34:29.000000000 +0000 ++++ linux-3.2.46/drivers/mmc/host/sdhci-bcm2708.c 2013-07-26 19:34:30.000000000 +0000 +@@ -1392,6 +1392,9 @@ + + if (allow_highspeed) + host->mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED; ++ ++ /* single block writes cause data loss with some SD cards! */ ++ host->mmc->caps2 |= MMC_CAP2_FORCE_MULTIBLOCK; + #endif + + ret = sdhci_add_host(host); +Index: linux-3.2.46/include/linux/mmc/host.h +=================================================================== +--- linux-3.2.46.orig/include/linux/mmc/host.h 2013-05-30 13:35:16.000000000 +0000 ++++ linux-3.2.46/include/linux/mmc/host.h 2013-07-26 19:34:30.000000000 +0000 +@@ -242,6 +242,7 @@ + #define MMC_CAP2_CACHE_CTRL (1 << 1) /* Allow cache control */ + #define MMC_CAP2_POWEROFF_NOTIFY (1 << 2) /* Notify poweroff supported */ + #define MMC_CAP2_NO_MULTI_READ (1 << 3) /* Multiblock reads don't work */ ++#define MMC_CAP2_FORCE_MULTIBLOCK (1 << 4) /* Always use multiblock transfers */ + + mmc_pm_flag_t pm_caps; /* supported pm features */ + unsigned int power_notify_type; diff -Nru linux-3.2.46/debian/patches/rpi/rpi_208_147779ede8bf936e37b6337458d531d5738c5a06.patch linux-3.2.46/debian/patches/rpi/rpi_208_147779ede8bf936e37b6337458d531d5738c5a06.patch --- linux-3.2.46/debian/patches/rpi/rpi_208_147779ede8bf936e37b6337458d531d5738c5a06.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_208_147779ede8bf936e37b6337458d531d5738c5a06.patch 2013-07-26 19:34:32.000000000 +0000 @@ -0,0 +1,51 @@ +commit 147779ede8bf936e37b6337458d531d5738c5a06 +Author: popcornmix +Date: Wed Aug 1 19:02:14 2012 +0100 + + Add module parameter for missing_status quirk. sdhci-bcm2708.missing_status=0 may improve interrupt latency + +Index: linux-3.2.46/drivers/mmc/host/sdhci-bcm2708.c +=================================================================== +--- linux-3.2.46.orig/drivers/mmc/host/sdhci-bcm2708.c 2013-07-26 19:34:30.000000000 +0000 ++++ linux-3.2.46/drivers/mmc/host/sdhci-bcm2708.c 2013-07-26 19:34:31.000000000 +0000 +@@ -139,6 +139,7 @@ + static bool allow_highspeed = 1; + static int emmc_clock_freq = BCM2708_EMMC_CLOCK_FREQ; + static bool sync_after_dma = 1; ++static bool missing_status = 1; + + #if 0 + static void hptime_test(void) +@@ -1271,7 +1272,6 @@ + .spurious_crc_acmd51 = sdhci_bcm2708_quirk_spurious_crc, + .voltage_broken = sdhci_bcm2708_quirk_voltage_broken, + .uhs_broken = sdhci_bcm2708_uhs_broken, +- .missing_status = sdhci_bcm2708_missing_status, + }; + + /*****************************************************************************\ +@@ -1310,6 +1310,9 @@ + ret = PTR_ERR(host); + goto err; + } ++ if (missing_status) { ++ sdhci_bcm2708_ops.missing_status = sdhci_bcm2708_missing_status; ++ } + + host->hw_name = "BCM2708_Arasan"; + host->ops = &sdhci_bcm2708_ops; +@@ -1509,6 +1512,7 @@ + module_param(allow_highspeed, bool, 0444); + module_param(emmc_clock_freq, int, 0444); + module_param(sync_after_dma, bool, 0444); ++module_param(missing_status, bool, 0444); + + MODULE_DESCRIPTION("Secure Digital Host Controller Interface platform driver"); + MODULE_AUTHOR("Broadcom "); +@@ -1518,5 +1522,6 @@ + MODULE_PARM_DESC(allow_highspeed, "Allow high speed transfers modes"); + MODULE_PARM_DESC(emmc_clock_freq, "Specify the speed of emmc clock"); + MODULE_PARM_DESC(sync_after_dma, "Block in driver until dma complete"); ++MODULE_PARM_DESC(missing_status, "Use the missing status quirk"); + + diff -Nru linux-3.2.46/debian/patches/rpi/rpi_209_adebc4f82e2fcb7268e7e14f576648fcf6921217.patch linux-3.2.46/debian/patches/rpi/rpi_209_adebc4f82e2fcb7268e7e14f576648fcf6921217.patch --- linux-3.2.46/debian/patches/rpi/rpi_209_adebc4f82e2fcb7268e7e14f576648fcf6921217.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_209_adebc4f82e2fcb7268e7e14f576648fcf6921217.patch 2013-07-26 19:34:34.000000000 +0000 @@ -0,0 +1,514 @@ +commit adebc4f82e2fcb7268e7e14f576648fcf6921217 +Author: popcornmix +Date: Tue Aug 7 22:24:16 2012 +0100 + + Some fixed for ALSA. Mute and volume changing should be improved + +Index: linux-3.2.46/sound/arm/bcm2835-ctl.c +=================================================================== +--- linux-3.2.46.orig/sound/arm/bcm2835-ctl.c 2013-07-26 19:33:17.000000000 +0000 ++++ linux-3.2.46/sound/arm/bcm2835-ctl.c 2013-07-26 19:34:33.000000000 +0000 +@@ -33,29 +33,22 @@ + + #include "bcm2835.h" + +- +-/* functions to convert alsa to chip volume and back. */ +-int alsa2chip(int vol) +-{ +- return -((vol << 8) / 100); +-} +- +-int chip2alsa(int vol) +-{ +- return -((vol * 100) >> 8); +-} ++/* volume maximum and minimum in terms of 0.01dB */ ++#define CTRL_VOL_MAX 400 ++#define CTRL_VOL_MIN -10239 /* originally -10240 */ + + + static int snd_bcm2835_ctl_info(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_info *uinfo) + { ++ audio_info(" ... IN "); + if (kcontrol->private_value == PCM_PLAYBACK_VOLUME) { + uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; + uinfo->count = 1; +- uinfo->value.integer.min = -10240; +- uinfo->value.integer.max = 400; /* 2303 */ ++ uinfo->value.integer.min = CTRL_VOL_MIN; ++ uinfo->value.integer.max = CTRL_VOL_MAX; /* 2303 */ + } else if (kcontrol->private_value == PCM_PLAYBACK_MUTE) { +- uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; ++ uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN; + uinfo->count = 1; + uinfo->value.integer.min = 0; + uinfo->value.integer.max = 1; +@@ -63,12 +56,38 @@ + uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; + uinfo->count = 1; + uinfo->value.integer.min = 0; +- uinfo->value.integer.max = AUDIO_DEST_MAX-0; ++ uinfo->value.integer.max = AUDIO_DEST_MAX-1; + } +- ++ audio_info(" ... OUT "); + return 0; + } + ++/* toggles mute on or off depending on the value of nmute, and returns ++ * 1 if the mute value was changed, otherwise 0 ++ */ ++static int toggle_mute(struct bcm2835_chip *chip, int nmute) ++{ ++ /* if settings are ok, just return 0 */ ++ if(chip->mute == nmute) ++ return 0; ++ ++ /* if the sound is muted then we need to unmute */ ++ if(chip->mute == CTRL_VOL_MUTE) ++ { ++ chip->volume = chip->old_volume; /* copy the old volume back */ ++ audio_info("Unmuting, old_volume = %d, volume = %d ...", chip->old_volume, chip->volume); ++ } ++ else /* otherwise we mute */ ++ { ++ chip->old_volume = chip->volume; ++ chip->volume = 26214; /* set volume to minimum level AKA mute */ ++ audio_info("Muting, old_volume = %d, volume = %d ...", chip->old_volume, chip->volume); ++ } ++ ++ chip->mute = nmute; ++ return 1; ++} ++ + static int snd_bcm2835_ctl_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) + { +@@ -93,9 +112,10 @@ + int changed = 0; + + if (kcontrol->private_value == PCM_PLAYBACK_VOLUME) { +- if (chip->mute) { +- chip->mute = 0; +- changed = 1; ++ audio_info("Volume change attempted.. volume = %d new_volume = %d", chip->volume, (int)ucontrol->value.integer.value[0]); ++ if (chip->mute == CTRL_VOL_MUTE) { ++ /* changed = toggle_mute(chip, CTRL_VOL_UNMUTE); */ ++ return 1; /* should return 0 to signify no change but the mixer takes this as the opposite sign (no idea why) */ + } + if (changed + || (ucontrol->value.integer.value[0] != chip2alsa(chip->volume))) { +@@ -105,11 +125,10 @@ + } + + } else if (kcontrol->private_value == PCM_PLAYBACK_MUTE) { +- /* Not implemented */ +- if (ucontrol->value.integer.value[0] != chip->mute) { +- chip->mute = ucontrol->value.integer.value[0]; +- changed = 0; +- } ++ /* Now implemented */ ++ audio_info(" Mute attempted"); ++ changed = toggle_mute(chip, ucontrol->value.integer.value[0]); ++ + } else if (kcontrol->private_value == PCM_PLAYBACK_DEVICE) { + if (ucontrol->value.integer.value[0] != chip->dest) { + chip->dest = ucontrol->value.integer.value[0]; +@@ -125,22 +144,21 @@ + return changed; + } + +-static DECLARE_TLV_DB_SCALE(snd_bcm2835_db_scale, -10240, 1, 1); ++static DECLARE_TLV_DB_SCALE(snd_bcm2835_db_scale, CTRL_VOL_MIN, 1, 1); + + static struct snd_kcontrol_new snd_bcm2835_ctl[] __devinitdata = { + { + .iface = SNDRV_CTL_ELEM_IFACE_MIXER, + .name = "PCM Playback Volume", + .index = 0, +- .access = +- SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_TLV_READWRITE, ++ .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_TLV_READ, + .private_value = PCM_PLAYBACK_VOLUME, + .info = snd_bcm2835_ctl_info, + .get = snd_bcm2835_ctl_get, + .put = snd_bcm2835_ctl_put, + .count = 1, + .tlv = {.p = snd_bcm2835_db_scale} +- }, ++ }, + { + .iface = SNDRV_CTL_ELEM_IFACE_MIXER, + .name = "PCM Playback Switch", +@@ -162,7 +180,7 @@ + .get = snd_bcm2835_ctl_get, + .put = snd_bcm2835_ctl_put, + .count = 1, +- }, ++ }, + }; + + int __devinit snd_bcm2835_new_ctl(bcm2835_chip_t * chip) +Index: linux-3.2.46/sound/arm/bcm2835-pcm.c +=================================================================== +--- linux-3.2.46.orig/sound/arm/bcm2835-pcm.c 2013-07-26 19:33:37.000000000 +0000 ++++ linux-3.2.46/sound/arm/bcm2835-pcm.c 2013-07-26 19:34:33.000000000 +0000 +@@ -26,11 +26,11 @@ + .rate_max = 48000, + .channels_min = 1, + .channels_max = 2, +- .buffer_bytes_max = (4 * 8 - 1) * 1024, /* Needs to be less than audioplay buffer size */ ++ .buffer_bytes_max = 32 * 1024, /* Needs to be less than audioplay buffer size */ + .period_bytes_min = 1 * 1024, +- .period_bytes_max = (4 * 8 - 1) * 1024, ++ .period_bytes_max = 32 * 1024, + .periods_min = 1, +- .periods_max = 4 * 8 - 1, ++ .periods_max = 32, + }; + + static void snd_bcm2835_playback_free(struct snd_pcm_runtime *runtime) +@@ -64,14 +64,18 @@ + ((alsa_stream->pos + consumed) / alsa_stream->period_size)) + new_period = 1; + } +- audio_debug("updating pos cur: %d + %d max:%d new_period:%d\n", ++ audio_debug("updating pos cur: %d + %d max:%d period_bytes:%d, hw_ptr: %d new_period:%d\n", + alsa_stream->pos, +- (consumed /** AUDIO_IPC_BLOCK_BUFFER_SIZE*/ ), +- alsa_stream->buffer_size, new_period); ++ consumed, ++ alsa_stream->buffer_size, ++ (int)(alsa_stream->period_size*alsa_stream->substream->runtime->periods), ++ frames_to_bytes(alsa_stream->substream->runtime, alsa_stream->substream->runtime->status->hw_ptr), ++ new_period); + if (alsa_stream->buffer_size) { + alsa_stream->pos += consumed; + alsa_stream->pos %= alsa_stream->buffer_size; + } ++ + if (alsa_stream->substream) { + if (new_period) + snd_pcm_period_elapsed(alsa_stream->substream); +@@ -135,7 +139,6 @@ + runtime->private_data = alsa_stream; + runtime->private_free = snd_bcm2835_playback_free; + runtime->hw = snd_bcm2835_playback_hw; +- + /* minimum 16 bytes alignment (for vchiq bulk transfers) */ + snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES, + 16); +@@ -224,6 +227,10 @@ + } + + bcm2835_audio_setup(alsa_stream); ++ ++ /* in preparation of the stream, set the controls (volume level) of the stream */ ++ bcm2835_audio_set_ctls(alsa_stream->chip); ++ + audio_info(" .. OUT\n"); + + return err; +@@ -382,7 +389,8 @@ + strcpy(pcm->name, "bcm2835 ALSA"); + chip->pcm = pcm; + chip->dest = AUDIO_DEST_AUTO; +- chip->volume = 100; ++ chip->volume = alsa2chip(0); ++ chip->mute = CTRL_VOL_UNMUTE; /*disable mute on startup */ + /* set operators */ + snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, + &snd_bcm2835_playback_ops); +Index: linux-3.2.46/sound/arm/bcm2835-vchiq.c +=================================================================== +--- linux-3.2.46.orig/sound/arm/bcm2835-vchiq.c 2013-07-26 19:33:37.000000000 +0000 ++++ linux-3.2.46/sound/arm/bcm2835-vchiq.c 2013-07-26 19:34:33.000000000 +0000 +@@ -43,12 +43,18 @@ + + /* Default VCOS logging level */ + #define LOG_LEVEL VCOS_LOG_WARN +- + /* Logging macros (for remapping to other logging mechanisms, i.e., printf) */ +-#define LOG_ERR( fmt, arg... ) vcos_log_error( "%s:%d " fmt, __func__, __LINE__, ##arg) +-#define LOG_WARN( fmt, arg... ) vcos_log_warn( "%s:%d " fmt, __func__, __LINE__, ##arg) +-#define LOG_INFO( fmt, arg... ) vcos_log_info( "%s:%d " fmt, __func__, __LINE__, ##arg) +-#define LOG_DBG( fmt, arg... ) vcos_log_info( "%s:%d " fmt, __func__, __LINE__, ##arg) ++#ifdef AUDIO_DEBUG_ENABLE ++ #define LOG_ERR( fmt, arg... ) pr_err( "%s:%d " fmt, __func__, __LINE__, ##arg) ++ #define LOG_WARN( fmt, arg... ) pr_info( "%s:%d " fmt, __func__, __LINE__, ##arg) ++ #define LOG_INFO( fmt, arg... ) pr_info( "%s:%d " fmt, __func__, __LINE__, ##arg) ++ #define LOG_DBG( fmt, arg... ) pr_info( "%s:%d " fmt, __func__, __LINE__, ##arg) ++#else ++ #define LOG_ERR( fmt, arg... ) vcos_log_error( "%s:%d " fmt, __func__, __LINE__, ##arg) ++ #define LOG_WARN( fmt, arg... ) vcos_log_warn( "%s:%d " fmt, __func__, __LINE__, ##arg) ++ #define LOG_INFO( fmt, arg... ) vcos_log_info( "%s:%d " fmt, __func__, __LINE__, ##arg) ++ #define LOG_DBG( fmt, arg... ) vcos_log_info( "%s:%d " fmt, __func__, __LINE__, ##arg) ++#endif + + typedef struct opaque_AUDIO_INSTANCE_T { + uint32_t num_connections; +@@ -103,7 +109,7 @@ + LOG_DBG(" .. IN\n"); + if (alsa_stream->my_wq) { + my_work_t *work = kmalloc(sizeof(my_work_t), GFP_ATOMIC); +- /* Queue some work (item 1) */ ++ /*--- Queue some work (item 1) ---*/ + if (work) { + INIT_WORK((struct work_struct *)work, my_wq_function); + work->alsa_stream = alsa_stream; +@@ -124,7 +130,7 @@ + LOG_DBG(" .. IN\n"); + if (alsa_stream->my_wq) { + my_work_t *work = kmalloc(sizeof(my_work_t), GFP_ATOMIC); +- /* Queue some work (item 1) */ ++ /*--- Queue some work (item 1) ---*/ + if (work) { + INIT_WORK((struct work_struct *)work, my_wq_function); + work->alsa_stream = alsa_stream; +@@ -142,6 +148,7 @@ + void my_workqueue_init(bcm2835_alsa_stream_t * alsa_stream) + { + alsa_stream->my_wq = create_workqueue("my_queue"); ++ return; + } + + void my_workqueue_quit(bcm2835_alsa_stream_t * alsa_stream) +@@ -151,6 +158,7 @@ + destroy_workqueue(alsa_stream->my_wq); + alsa_stream->my_wq = NULL; + } ++ return; + } + + static void audio_vchi_callback(void *param, +@@ -501,14 +509,22 @@ + int i; + int ret = 0; + LOG_DBG(" .. IN\n"); ++ + /* change ctls for all substreams */ + for (i = 0; i < MAX_SUBSTREAMS; i++) { + if (chip->avail_substreams & (1 << i)) { + if (!chip->alsa_stream[i]) ++ { ++ LOG_DBG(" No ALSA stream available?! "); + ret = 0; +- else if (bcm2835_audio_set_ctls_chan ++ } ++ else if (bcm2835_audio_set_ctls_chan /* returns 0 on success */ + (chip->alsa_stream[i], chip) != 0) +- ret = -1; ++ { ++ LOG_DBG("Couldn't set the controls for stream %d", i); ++ ret = -1; ++ } ++ LOG_DBG(" Controls set for stream %d", i); + } + } + LOG_DBG(" .. OUT ret=%d\n", ret); +Index: linux-3.2.46/sound/arm/bcm2835.h +=================================================================== +--- linux-3.2.46.orig/sound/arm/bcm2835.h 2013-07-26 19:32:38.000000000 +0000 ++++ linux-3.2.46/sound/arm/bcm2835.h 2013-07-26 19:34:33.000000000 +0000 +@@ -15,8 +15,6 @@ + #ifndef __SOUND_ARM_BCM2835_H + #define __SOUND_ARM_BCM2835_H + +-#define SUBSTREAM_NUM 1 +- + #include + #include + #include +@@ -27,13 +25,14 @@ + #include + #include + +-/* #define DUMP_RAW_DATA */ +-//#define AUDIO_DEBUG_ENABLE +-//#define AUDIO_VERBOSE_DEBUG_ENABLE ++/* ++#define AUDIO_DEBUG_ENABLE ++#define AUDIO_VERBOSE_DEBUG_ENABLE ++*. + + /* Debug macros */ +-#ifdef AUDIO_DEBUG_ENABLE + ++#ifdef AUDIO_DEBUG_ENABLE + #ifdef AUDIO_VERBOSE_DEBUG_ENABLE + + #define audio_debug(fmt, arg...) \ +@@ -44,17 +43,17 @@ + + #else + +-#define audio_debug(fmt, arg...) do {} while (0) ++#define audio_debug(fmt, arg...) + +-#define audio_info(fmt, arg...) do {} while (0) ++#define audio_info(fmt, arg...) + + #endif /* AUDIO_VERBOSE_DEBUG_ENABLE */ + + #else + +-#define audio_debug(fmt, arg...) do {} while (0) ++#define audio_debug(fmt, arg...) + +-#define audio_info(fmt, arg...) do {} while (0) ++#define audio_info(fmt, arg...) + + #endif /* AUDIO_DEBUG_ENABLE */ + +@@ -69,75 +68,15 @@ + + #define MAX_SUBSTREAMS (8) + #define AVAIL_SUBSTREAMS_MASK (0xff) ++enum { ++ CTRL_VOL_MUTE, ++ CTRL_VOL_UNMUTE ++}; + +-#define AUDIO_IPC_BLOCK_NUM_BUFFERS (8) +-#define AUDIO_IPC_BLOCK_BUFFER_SIZE (1024*8) ++/* macros for alsa2chip and chip2alsa, instead of functions */ + +-#define AUDIO_CONTROL_OFFSET (0x00) +-#define CTRL_EN_SHIFT (0) +-#define CTRL_EN_MASK (0x00000001) +-#define CTRL_PLAY_SHIFT (1) +-#define CTRL_PLAY_MASK (0x00000002) +-#define CTRL_MUTE_SHIFT (2) +-#define CTRL_MUTE_MASK (0x00000004) +-#define CTRL_SETUP_SHIFT (3) +-#define CTRL_SETUP_MASK (0x00000008) +-#define CTRL_FLUSH_SHIFT (4) +-#define CTRL_FLUSH_MASK (0x00000010) +-#define CTRL_STOPMODE_SHIFT (5) +-#define CTRL_STOPMODE_MASK (0x00000020) +- +-#define AUDIO_STATUS_OFFSET (0x04) +-#define STAT_EN_SHIFT (0) +-#define STAT_EN_MASK (0x00000001) +-#define STAT_PLAY_SHIFT (1) +-#define STAT_PLAY_MASK (0x00000002) +-#define STAT_MUTE_SHIFT (2) +-#define STAT_MUTE_MASK (0x00000004) +-#define STAT_SETUP_SHIFT (3) +-#define STAT_SETUP_MASK (0x00000008) +-#define STAT_FLUSH_SHIFT (4) +-#define STAT_FLUSH_MASK (0x00000010) +-#define STAT_STOPMODE_SHIFT (5) +-#define STAT_STOPMODE_MASK (0x00000020) +- +-/* Interrupt status */ +-#define AUDIO_INTSTAT_OFFSET (0x08) +-#define INTSTAT_CONTROL_SHIFT (0) +-#define INTSTAT_CONTROL_MASK (0x0000000f) +-#define INTSTAT_FIFO_SHIFT (4) +-#define INTSTAT_FIFO_MASK (0x000000f0) +- +-/* Configuration */ +-#define AUDIO_DESTINATION_OFFSET (0x0C) +-#define AUDIO_SAMPLE_RATE_OFFSET (0x10) +-#define AUDIO_BIT_RATE_OFFSET (0x14) +-#define AUDIO_VOLUME_OFFSET (0x18) +-#define AUDIO_CHANNELS_OFFSET (0x1C) +- +-/* Implemention of peterson's algorithm for shared memory semaphores */ +-#define AUDIO_FLAG0_OFFSET (0x20) +-#define AUDIO_FLAG1_OFFSET (0x24) +-#define AUDIO_TURN_OFFSET (0x28) +- +-/* Fifo registers */ +-#define AUDIO_IN_WRITE_PTR_OFFSET (0x30) +-#define AUDIO_IN_READ_PTR_OFFSET (0x34) +-#define AUDIO_IN_FIFO_SIZE_OFFSET (0x38) +-#define AUDIO_IN_FIFO_ENTRY_OFFSET (0x3C) +-#define AUDIO_IN_FIFO_START_OFFSET (0x40) +- +-/* 8 entries here of 4 words each = 0x80 gap from 0x50 */ +-#define AUDIO_IN_FIFO_OFFSET (0x50) +- +-#define AUDIO_OUT_WRITE_PTR_OFFSET (0xD0) +-#define AUDIO_OUT_READ_PTR_OFFSET (0xD4) +-#define AUDIO_OUT_FIFO_SIZE_OFFSET (0xD8) +-#define AUDIO_OUT_FIFO_ENTRY_OFFSET (0xDC) +-#define AUDIO_OUT_FIFO_START_OFFSET (0xE0) +- +-/* 8 entries here of 4 words each = 0x80 gap from 0xF0 */ +-#define AUDIO_OUT_FIFO_OFFSET (0xF0) ++#define alsa2chip(vol) (uint)(-((vol << 8) / 100)) /* convert alsa to chip volume (defined as macro rather than function call) */ ++#define chip2alsa(vol) -((vol * 100) >> 8) /* convert chip to alsa volume */ + + /* Some constants for values .. */ + typedef enum { +@@ -153,15 +92,6 @@ + PCM_PLAYBACK_DEVICE, + } SND_BCM2835_CTRL_T; + +-/* this struct is tightly packed - its size is 16bytes */ +-typedef struct { +- uint32_t buffer_id; +- uint32_t buffer_size; +- uint32_t buffer_ptr; +- uint32_t spare; +- +-} AUDIO_FIFO_ENTRY_T; +- + /* definition of the chip-specific record */ + typedef struct bcm2835_chip { + struct snd_card *card; +@@ -172,20 +102,11 @@ + struct bcm2835_alsa_stream *alsa_stream[MAX_SUBSTREAMS]; + + int volume; ++ int old_volume; /* stores the volume value whist muted */ + int dest; + int mute; + } bcm2835_chip_t; + +-typedef struct bcm2835_audio_buffer { +- uint32_t buffer_id; +- phys_addr_t bus_addr; +- uint8_t __iomem *start; +- uint32_t size; +- uint32_t data_left; +- struct list_head link; +- +-} bcm2835_audio_buffer_t; +- + typedef struct bcm2835_alsa_stream { + bcm2835_chip_t *chip; + struct snd_pcm_substream *substream; +@@ -200,10 +121,6 @@ + int running; + int draining; + +-#ifdef DUMP_RAW_DATA +- /* for debug */ +- int file; +-#endif + unsigned int pos; + unsigned int buffer_size; + unsigned int period_size; +@@ -220,9 +137,6 @@ + int snd_bcm2835_new_ctl(bcm2835_chip_t * chip); + int snd_bcm2835_new_pcm(bcm2835_chip_t * chip); + +-void bcm2835_audio_fifo_get_lock(bcm2835_alsa_stream_t * alsa_stream); +-void bcm2835_audio_fifo_put_lock(bcm2835_alsa_stream_t * alsa_stream); +- + int bcm2835_audio_open(bcm2835_alsa_stream_t * alsa_stream); + int bcm2835_audio_close(bcm2835_alsa_stream_t * alsa_stream); + int bcm2835_audio_set_params(bcm2835_alsa_stream_t * alsa_stream, +@@ -234,7 +148,6 @@ + int bcm2835_audio_set_ctls(bcm2835_chip_t * chip); + int bcm2835_audio_write(bcm2835_alsa_stream_t * alsa_stream, uint32_t count, + void *src); +-//uint32_t bcm2835_audio_buffers_consumed_bytes(bcm2835_alsa_stream_t *alsa_stream); + uint32_t bcm2835_audio_retrieve_buffers(bcm2835_alsa_stream_t * alsa_stream); + void bcm2835_audio_flush_buffers(bcm2835_alsa_stream_t * alsa_stream); + void bcm2835_audio_flush_playback_buffers(bcm2835_alsa_stream_t * alsa_stream); diff -Nru linux-3.2.46/debian/patches/rpi/rpi_210_2c671b98f0d33b8416a55c50f8057a4067484bb0.patch linux-3.2.46/debian/patches/rpi/rpi_210_2c671b98f0d33b8416a55c50f8057a4067484bb0.patch --- linux-3.2.46/debian/patches/rpi/rpi_210_2c671b98f0d33b8416a55c50f8057a4067484bb0.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_210_2c671b98f0d33b8416a55c50f8057a4067484bb0.patch 2013-07-26 19:34:35.000000000 +0000 @@ -0,0 +1,55 @@ +commit 2c671b98f0d33b8416a55c50f8057a4067484bb0 +Author: ddv2005 +Date: Sun Aug 5 10:42:12 2012 -0400 + + Fix spinlock recursion in sdhci-bcm2708.c + +Index: linux-3.2.46/drivers/mmc/host/sdhci-bcm2708.c +=================================================================== +--- linux-3.2.46.orig/drivers/mmc/host/sdhci-bcm2708.c 2013-07-26 19:34:31.000000000 +0000 ++++ linux-3.2.46/drivers/mmc/host/sdhci-bcm2708.c 2013-07-26 19:34:34.000000000 +0000 +@@ -656,7 +656,7 @@ + + BUG_ON(NULL == host); + +- spin_lock_irqsave(&host->lock, flags); ++// spin_lock_irqsave(&host->lock, flags); + + if (host_priv->dma_wanted) { + if (NULL == data) { +@@ -736,7 +736,7 @@ + #endif + } + +- spin_unlock_irqrestore(&host->lock, flags); ++// spin_unlock_irqrestore(&host->lock, flags); + } + + +@@ -753,7 +753,7 @@ + + BUG_ON(NULL == host); + +- spin_lock_irqsave(&host->lock, flags); ++// spin_lock_irqsave(&host->lock, flags); + data = host->data; + + #ifdef CHECK_DMA_USE +@@ -778,7 +778,7 @@ + + if (NULL == data) { + DBG("PDMA unused completion - status 0x%X\n", dma_cs); +- spin_unlock_irqrestore(&host->lock, flags); ++// spin_unlock_irqrestore(&host->lock, flags); + return; + } + sg = data->sg; +@@ -871,7 +871,7 @@ + SDHCI_INT_SPACE_AVAIL); + } + } +- spin_unlock_irqrestore(&host->lock, flags); ++// spin_unlock_irqrestore(&host->lock, flags); + } + + static irqreturn_t sdhci_bcm2708_dma_irq(int irq, void *dev_id) diff -Nru linux-3.2.46/debian/patches/rpi/rpi_211_4cdeb7b0ca4bb80b68057108cf747a4a642e47b6.patch linux-3.2.46/debian/patches/rpi/rpi_211_4cdeb7b0ca4bb80b68057108cf747a4a642e47b6.patch --- linux-3.2.46/debian/patches/rpi/rpi_211_4cdeb7b0ca4bb80b68057108cf747a4a642e47b6.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_211_4cdeb7b0ca4bb80b68057108cf747a4a642e47b6.patch 2013-07-26 19:34:37.000000000 +0000 @@ -0,0 +1,592 @@ +commit 4cdeb7b0ca4bb80b68057108cf747a4a642e47b6 +Author: popcornmix +Date: Fri Aug 10 18:45:05 2012 +0100 + + Revert "Add mechanism to reduce the number of SOF interrupts in dwc_otg USB driver. Enable through /proc/dwc_sof/SOF_reduction" + + This reverts commit 85b7821857dd0b9cabab59d47f08eabed74679a3. + +Index: linux-3.2.46/drivers/usb/host/dwc_common_port/dwc_common_linux.c +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_common_port/dwc_common_linux.c 2013-07-26 19:34:16.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_common_port/dwc_common_linux.c 2013-07-26 19:34:36.000000000 +0000 +@@ -912,7 +912,7 @@ + { + dwc_timer_t *timer = (dwc_timer_t *)data; + set_scheduled(timer, 0); +- /*DWC_DEBUG("Timer %s callback", timer->name);*/ ++ DWC_DEBUG("Timer %s callback", timer->name); + timer->cb(timer->data); + } + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/Makefile +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/Makefile 2013-07-26 19:33:51.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/Makefile 2013-07-26 19:34:36.000000000 +0000 +@@ -15,14 +15,9 @@ + + # Use one of the following flags to compile the software in host-only or + # device-only mode. +-ifeq ($(CONFIG_USB_GADGET_DWCOTG),) +-CPPFLAGS += -DDWC_HOST_ONLY +-endif ++#CPPFLAGS += -DDWC_HOST_ONLY + #CPPFLAGS += -DDWC_DEVICE_ONLY + +-# Use this flag to reduce SOF interrupt service overhead +-CPPFLAGS += -DSOF_FIX +- + CPPFLAGS += -Dlinux -DDWC_HS_ELECT_TST + #CGG: CPPFLAGS += -DDWC_EN_ISOC + CPPFLAGS += -I$(obj)/../dwc_common_port +Index: linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_driver.c +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/dwc_otg_driver.c 2013-07-26 19:33:51.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_driver.c 2013-07-26 19:34:36.000000000 +0000 +@@ -82,11 +82,6 @@ + + # include + +-#ifdef SOF_FIX +-#include +-#include +-#endif +- + #include + + +@@ -183,8 +178,6 @@ + int32_t lpm_enable; + int32_t ic_usb_cap; + int32_t ahb_thr_ratio; +- int32_t sof_setting; // 0=off, 1=on +- int32_t proc_init_done; // 0=not done, 1=done + }; + + static struct dwc_otg_driver_module_params dwc_otg_module_params = { +@@ -261,139 +254,9 @@ + .lpm_enable = -1, + .ic_usb_cap = -1, + .ahb_thr_ratio = -1, +- .sof_setting = 0, +- .proc_init_done = 0, + }; + + /** +- * PROC_FS SUPPORT +- * proc_fs support for setting the Start-of-Frame (SOF) interrupt processing +- * fix (reducing SOF interrupts by an order of magnitude). When set +- * to "on" the SOF interrupt will only be turned on once per tick, for +- * 3 micro-frame times. When set to "off" it will not turn off the +- * SOF interrupt, and process all 8000 per second. +- */ +- +-#ifdef SOF_FIX +- +-static struct proc_dir_entry *proc_dir, *proc_file; +- +-int sof_setting(void) +-{ +- return dwc_otg_module_params.sof_setting; +-} +- +-static int sof_read_data (char *page, +- char **start, +- off_t off, +- int count, +- int *eof, +- void *data) +-{ +- +- if (dwc_otg_module_params.sof_setting == 1) +- { +- sprintf(page, "on\n"); +- return 4; +- } +- else +- { +- sprintf(page, "off\n"); +- return 5; +- } +- return 0; +-} +- +-#define PROC_FS_MAX_SIZE 1024 +-#define PROC_FS_NAME "SOF_reduction" +- +-static char proc_fs_buffer[PROC_FS_MAX_SIZE]; +- +-static int sof_write_data (struct file *file, +- const char __user *buffer, +- unsigned long count, +- void *data) +-{ +- unsigned long buffer_size = count; +- +- if (buffer_size > PROC_FS_MAX_SIZE) +- buffer_size = PROC_FS_MAX_SIZE; +- +- memset(proc_fs_buffer, 0, sizeof(proc_fs_buffer)); +- +- if (copy_from_user(proc_fs_buffer, buffer, buffer_size)) +- { +- printk(KERN_ERR "\nSOF_write_data: copy_from_user failure\n"); +- return -EFAULT; +- } +- +- if ((strnlen(proc_fs_buffer, PROC_FS_MAX_SIZE) == 3) && +- (strncmp(proc_fs_buffer, "on", 2) == 0)) +- { +- printk(KERN_ERR "\n%s: Setting SOF (reduction) ON.\n", PROC_FS_NAME); +- dwc_otg_module_params.sof_setting = 1; +- } +- else if ((strnlen(proc_fs_buffer, PROC_FS_MAX_SIZE) == 4) && +- (strncmp(proc_fs_buffer, "off", 3) == 0)) +- { +- printk(KERN_ERR "\n%s: Setting SOF reduction OFF.\n",PROC_FS_NAME); +- dwc_otg_module_params.sof_setting = 0; +- } +- else +- printk(KERN_ERR "\n%s: input not \'on\' or \'off\', ignored.\n", PROC_FS_NAME); +-#ifdef DEBUG_SOF_FIX +- printk(KERN_ERR "\n%s:buffer %s, len = %d.\n",__func__, +- proc_fs_buffer, strnlen(proc_fs_buffer, PROC_FS_MAX_SIZE)); +-#endif +- +- return buffer_size; +-} +- +-/** +- * Initialize proc_fs entry for SOF setting. +- */ +-static int init_proc_fs(void) +-{ +- int retval = 0; +- +- if (dwc_otg_module_params.proc_init_done) +- return 0; +- +- proc_dir = proc_mkdir_mode("dwc_sof", 0755, NULL); +- +- if(proc_dir == NULL) +- { +- retval = -ENOMEM; +- printk("Error creating dir\n"); +- return retval; +- } +- +- proc_file = create_proc_entry(PROC_FS_NAME, 0666, proc_dir); +- +- if (proc_file != NULL) +- { +- dwc_otg_module_params.proc_init_done = 1; +- proc_file->read_proc = sof_read_data; +- proc_file->write_proc = sof_write_data; +- proc_file->mode = S_IFREG | S_IRUGO; +- proc_file->uid = 0; +- proc_file->gid = 0; +- proc_file->gid = PROC_FS_MAX_SIZE; +- } +- else +- { +- retval = -ENOMEM; +- printk("Error creating file\n"); +- remove_proc_entry(PROC_FS_NAME, NULL); +- } +- +- return retval; +-} +- +-#endif +- +- +-/** + * This function shows the Driver Version. + */ + static ssize_t version_show(struct device_driver *dev, char *buf) +@@ -982,12 +845,6 @@ + dev_dbg(&_dev->dev, "Calling attr_create\n"); + dwc_otg_attr_create(_dev); + +-#ifdef SOF_FIX +- retval = init_proc_fs(); +- if (retval) +- goto fail; +-#endif +- + /* + * Disable the global interrupt until all the interrupt + * handlers are installed. +@@ -1158,7 +1015,6 @@ + * + * @return + */ +- + static int __init dwc_otg_driver_init(void) + { + int retval = 0; +@@ -1193,11 +1049,6 @@ + error = driver_create_file(&dwc_otg_driver.driver, + &driver_attr_debuglevel); + #endif +- +-#ifdef SOF_FIX +- retval = init_proc_fs(); +-#endif +- + return retval; + } + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_hcd.c +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/dwc_otg_hcd.c 2013-07-26 19:33:51.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_hcd.c 2013-07-26 19:34:36.000000000 +0000 +@@ -64,37 +64,6 @@ + __DWC_ERROR("Device Not Connected/Responding\n"); + } + +-/** +- * SOF_FIX: Reduce the SOF overhead by disabling the SOF interrupt except +- * when there are USB transfers pending. Re-enable the interrupt +- * every tick for periodic transaction handling. MSO 5/31/12 +- * SOF (Start of Frame) timeout function. Kick the driver by re-enabling +- * the SOF interrupt +- */ +-#ifdef SOF_FIX +-void dwc_otg_hcd_sof_timeout(void *ptr) +-{ +- dwc_otg_hcd_t * hcd = (dwc_otg_hcd_t *)ptr; +- dwc_otg_core_if_t *core_if = hcd->core_if; +- gintmsk_data_t gintmsk = {.d32 = 0}; +- dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs; +- unsigned int intmsk; +- +- // turn on Start-of-Frame interrupt +- gintmsk.d32 = dwc_read_reg32(&global_regs->gintmsk); +- intmsk = gintmsk.d32; +- gintmsk.b.sofintr |= 1; +- dwc_write_reg32(&global_regs->gintmsk, gintmsk.d32); +- DWC_TIMER_SCHEDULE(hcd->sof_timer, 1); /* 1ms */ +-#ifdef DEBUG_SOF_FIX +- if ((++sof_timeout_count % 10000) == 0) +- printk(KERN_ERR "%s: %d timeouts handled, read 0x%x wrote 0x%x.", +- __FUNCTION__, sof_timeout_count, intmsk, gintmsk.d32); +-#endif +- +-} +-#endif +- + #ifdef DEBUG + static void dump_channel_info(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh) + { +@@ -823,13 +792,6 @@ + hcd->conn_timer = DWC_TIMER_ALLOC("Connection timer", + dwc_otg_hcd_connect_timeout, 0); + +-#ifdef SOF_FIX +- /* Initialize the Start of Frame interrupt timeout timer. */ +- hcd->sof_timer = DWC_TIMER_ALLOC("SOF timer", +- dwc_otg_hcd_sof_timeout, hcd); +- DWC_TIMER_SCHEDULE(hcd->sof_timer, 1); /* 1ms */ +-#endif +- + /* Initialize reset tasklet. */ + hcd->reset_tasklet = DWC_TASK_ALLOC(reset_tasklet_func, hcd); + +@@ -1345,11 +1307,6 @@ + dwc_otg_qh_t *qh; + int num_channels; + dwc_otg_transaction_type_e ret_val = DWC_OTG_TRANSACTION_NONE; +-#ifdef SOF_FIX +- dwc_otg_core_if_t *core_if = hcd->core_if; +- gintmsk_data_t gintmsk = {.d32 = 0}; +- dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs; +-#endif + + #ifdef DEBUG_SOF + DWC_DEBUGPL(DBG_HCD, " Select Transactions\n"); +@@ -1389,19 +1346,6 @@ + } + #endif + } +-#ifdef SOF_FIX +- /* +- * If there are transactions queued then enable the SOF interrupt to send them to +- * the controller. +- */ +- if (ret_val != DWC_OTG_TRANSACTION_NONE) +- { +- // turn on Start-of-Frame interrupt +- gintmsk.d32 = dwc_read_reg32(&global_regs->gintmsk); +- gintmsk.b.sofintr |= 1; +- dwc_write_reg32(&global_regs->gintmsk, gintmsk.d32); +- } +-#endif + + /* + * Process entries in the inactive portion of the non-periodic +Index: linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_hcd.h +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/dwc_otg_hcd.h 2013-07-26 19:33:51.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_hcd.h 2013-07-26 19:34:36.000000000 +0000 +@@ -569,15 +569,6 @@ + uint32_t hfnum_other_samples_b; + uint64_t hfnum_other_frrem_accum_b; + #endif +-#ifdef SOF_FIX +- /** +- * SOF wakeup timer. We disable the SOF interrupt if there is nothing +- * to do. However, that eventually gets us into trouble. So, re-enable +- * the SOF interrupt every tick so we can handle any backlog that does +- * not trigger any other interrupt. +- */ +- dwc_timer_t *sof_timer; +-#endif + }; + + /** @name Transaction Execution Functions */ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c 2013-07-26 19:34:14.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c 2013-07-26 19:34:36.000000000 +0000 +@@ -32,8 +32,6 @@ + * ========================================================================== */ + #ifndef DWC_DEVICE_ONLY + +-#include +-#include + #include "dwc_otg_hcd.h" + #include "dwc_otg_regs.h" + +@@ -41,19 +39,6 @@ + * This file contains the implementation of the HCD Interrupt handlers. + */ + +-/** +- * SOF_FIX: Reduce SOF interrupt handling by disabling the SOF interrupt except +- * when there are actual USB transfers pending. MSO 5/31/12 +- */ +-#ifdef SOF_FIX +- extern int sof_setting(void); +- unsigned int g_dwc_otg_hcd_handle_intr_count = 0; +- #ifdef DEBUG_SOF_FIX +- unsigned int g_dwc_otg_interrupt_counts[10] = {0,0,0,0,0,0,0,0,0,0}; +- extern int g_softintr_ref_cnt; +- #endif +-#endif +- + /** This function handles interrupts for the HCD. */ + int32_t dwc_otg_hcd_handle_intr(dwc_otg_hcd_t * dwc_otg_hcd) + { +@@ -61,12 +46,9 @@ + + dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if; + gintsts_data_t gintsts; +-#ifdef SOF_FIX ++#ifdef DEBUG + dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs; +- gintmsk_data_t gintmsk; +-#endif + +-#ifdef DEBUG + //GRAYG: debugging + if (NULL == global_regs) { + DWC_DEBUGPL(DBG_HCD, "**** NULL regs: dwc_otg_hcd=%p " +@@ -75,9 +57,7 @@ + return retval; + } + #endif +-#ifdef SOF_FIX +- g_dwc_otg_hcd_handle_intr_count++; +-#endif ++ + /* Check if HOST Mode */ + if (dwc_otg_is_host_mode(core_if)) { + gintsts.d32 = dwc_otg_read_core_intr(core_if); +@@ -101,64 +81,29 @@ + gintsts.d32, core_if); + #endif + +- /* +- * If SOF handle it. If not, it probably means that there is work to do, +- * so enable SOF for the next micro-frame. +- */ +- if (gintsts.b.sofintr) +- { +-#ifdef DEBUG_SOF_FIX +- g_dwc_otg_interrupt_counts[0]++; +-#endif ++ if (gintsts.b.sofintr) { + retval |= dwc_otg_hcd_handle_sof_intr(dwc_otg_hcd); + } +-#ifdef SOF_FIX +- else +- { +- // turn on Start-of-Frame interrupt +- gintmsk.d32 = dwc_read_reg32(&global_regs->gintmsk); +- gintmsk.b.sofintr |= 1; +- dwc_write_reg32(&global_regs->gintmsk, gintmsk.d32); +- } +-#endif + if (gintsts.b.rxstsqlvl) { +-#ifdef DEBUG_SOF_FIX +- g_dwc_otg_interrupt_counts[1]++; +-#endif + retval |= + dwc_otg_hcd_handle_rx_status_q_level_intr + (dwc_otg_hcd); + } + if (gintsts.b.nptxfempty) { +-#ifdef DEBUG_SOF_FIX +- g_dwc_otg_interrupt_counts[2]++; +-#endif + retval |= + dwc_otg_hcd_handle_np_tx_fifo_empty_intr + (dwc_otg_hcd); + } + if (gintsts.b.i2cintr) { +-#ifdef DEBUG_SOF_FIX +- g_dwc_otg_interrupt_counts[3]++; +-#endif + /** @todo Implement i2cintr handler. */ + } + if (gintsts.b.portintr) { +-#ifdef DEBUG_SOF_FIX +- g_dwc_otg_interrupt_counts[4]++; +-#endif + retval |= dwc_otg_hcd_handle_port_intr(dwc_otg_hcd); + } + if (gintsts.b.hcintr) { +-#ifdef DEBUG_SOF_FIX +- g_dwc_otg_interrupt_counts[5]++; +-#endif + retval |= dwc_otg_hcd_handle_hc_intr(dwc_otg_hcd); + } + if (gintsts.b.ptxfempty) { +-#ifdef DEBUG_SOF_FIX +- g_dwc_otg_interrupt_counts[6]++; +-#endif + retval |= + dwc_otg_hcd_handle_perio_tx_fifo_empty_intr + (dwc_otg_hcd); +@@ -185,21 +130,7 @@ + #endif + + } +-#if defined(SOF_FIX) && defined(DEBUG_SOF_FIX) +- if ((g_dwc_otg_hcd_handle_intr_count % 80000) == 0) +- { +- printk(KERN_ERR "dwc_otg_hcd_handle_intr: %u handled, %u, %u, %u, %u, %u, %u, %u, %u.\n", +- g_dwc_otg_hcd_handle_intr_count, +- g_dwc_otg_interrupt_counts[0], +- g_dwc_otg_interrupt_counts[1], +- g_dwc_otg_interrupt_counts[2], +- g_dwc_otg_interrupt_counts[3], +- g_dwc_otg_interrupt_counts[4], +- g_dwc_otg_interrupt_counts[5], +- g_dwc_otg_interrupt_counts[6], +- g_dwc_otg_interrupt_counts[7]); +- } +-#endif ++ + return retval; + } + +@@ -243,10 +174,6 @@ + * (micro)frame. Periodic transactions may be queued to the controller for the + * next (micro)frame. + */ +-#ifdef SOF_FIX +-#define SOF_INTR_DELAY_COUNT 3 +-static int g_sof_intr_delay_count = SOF_INTR_DELAY_COUNT; +-#endif + int32_t dwc_otg_hcd_handle_sof_intr(dwc_otg_hcd_t * hcd) + { + hfnum_data_t hfnum; +@@ -254,11 +181,6 @@ + dwc_otg_qh_t *qh; + dwc_otg_transaction_type_e tr_type; + gintsts_data_t gintsts = {.d32 = 0 }; +-#ifdef SOF_FIX +- dwc_otg_core_if_t *core_if = hcd->core_if; +- gintmsk_data_t gintmsk = {.d32 = 0 }; +- dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs; +-#endif + + hfnum.d32 = + dwc_read_reg32(&hcd->core_if->host_if->host_global_regs->hfnum); +@@ -291,24 +213,9 @@ + } + } + tr_type = dwc_otg_hcd_select_transactions(hcd); +- if (tr_type != DWC_OTG_TRANSACTION_NONE) +- { ++ if (tr_type != DWC_OTG_TRANSACTION_NONE) { + dwc_otg_hcd_queue_transactions(hcd, tr_type); + } +-#ifdef SOF_FIX +- else +- { +- // turn off Start-of-Frame interrupt +- if ((sof_setting()) && +- (g_sof_intr_delay_count-- == 0)) +- { +- gintmsk.d32 = dwc_read_reg32(&global_regs->gintmsk); +- gintmsk.b.sofintr &= 0; +- dwc_write_reg32(&global_regs->gintmsk, gintmsk.d32); +- g_sof_intr_delay_count = SOF_INTR_DELAY_COUNT; +- } +- } +-#endif + + /* Clear interrupt */ + gintsts.b.sofintr = 1; +Index: linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c 2013-07-26 19:33:52.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c 2013-07-26 19:34:36.000000000 +0000 +@@ -261,20 +261,11 @@ + * Sets the final status of an URB and returns it to the device driver. Any + * required cleanup of the URB is performed. + */ +-#ifdef DEBUG_SOF_FIX +-extern unsigned int g_dwc_otg_interrupt_counts[10]; +-#endif +- + static int _complete(dwc_otg_hcd_t * hcd, void *urb_handle, + dwc_otg_hcd_urb_t * dwc_otg_urb, int32_t status) + { + uint64_t flags; + struct urb *urb = (struct urb *)urb_handle; +- +-#ifdef DEBUG_SOF_FIX +- g_dwc_otg_interrupt_counts[7]++; +-#endif +- + #ifdef DEBUG + if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) { + DWC_PRINTF("%s: urb %p, device %d, ep %d %s, status=%d\n", +@@ -835,10 +826,6 @@ + * interrupt. + * + * This function is called by the USB core when an interrupt occurs */ +- +-#ifdef DEBUG_SOF_FIX +-unsigned int g_dwc_otg_hcd_irq_count = 0; +-#endif + static irqreturn_t dwc_otg_hcd_irq(struct usb_hcd *hcd) + { + dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd); +@@ -846,12 +833,6 @@ + if (retval != 0) { + S3C2410X_CLEAR_EINTPEND(); + } +- +-#ifdef DEBUG_SOF_FIX +- ++g_dwc_otg_hcd_irq_count; +- if ((++g_dwc_otg_hcd_irq_count %10000) == 0) +- printk(KERN_ERR "dwc_otg_hcd_irq: %u completions.\n", g_dwc_otg_hcd_irq_count); +-#endif + return IRQ_RETVAL(retval); + } + diff -Nru linux-3.2.46/debian/patches/rpi/rpi_212_7880df43b92e1a99acf14ac421b4a233a1a687ec.patch linux-3.2.46/debian/patches/rpi/rpi_212_7880df43b92e1a99acf14ac421b4a233a1a687ec.patch --- linux-3.2.46/debian/patches/rpi/rpi_212_7880df43b92e1a99acf14ac421b4a233a1a687ec.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_212_7880df43b92e1a99acf14ac421b4a233a1a687ec.patch 2013-07-26 19:34:38.000000000 +0000 @@ -0,0 +1,18 @@ +commit 7880df43b92e1a99acf14ac421b4a233a1a687ec +Author: popcornmix +Date: Mon Aug 13 20:16:58 2012 +0100 + + Enable CONFIG_CRYPTO_XTS + +Index: linux-3.2.46/arch/arm/configs/bcmrpi_defconfig +=================================================================== +--- linux-3.2.46.orig/arch/arm/configs/bcmrpi_defconfig 2013-07-26 19:34:12.000000000 +0000 ++++ linux-3.2.46/arch/arm/configs/bcmrpi_defconfig 2013-07-26 19:34:37.000000000 +0000 +@@ -876,6 +876,7 @@ + CONFIG_CRYPTO_AUTHENC=m + CONFIG_CRYPTO_SEQIV=m + CONFIG_CRYPTO_CBC=y ++CONFIG_CRYPTO_XTS=m + CONFIG_CRYPTO_HMAC=y + CONFIG_CRYPTO_XCBC=m + CONFIG_CRYPTO_MD5=y diff -Nru linux-3.2.46/debian/patches/rpi/rpi_213_f599001496e2bbacd54e11fb9fbabda694d308f2.patch linux-3.2.46/debian/patches/rpi/rpi_213_f599001496e2bbacd54e11fb9fbabda694d308f2.patch --- linux-3.2.46/debian/patches/rpi/rpi_213_f599001496e2bbacd54e11fb9fbabda694d308f2.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_213_f599001496e2bbacd54e11fb9fbabda694d308f2.patch 2013-07-26 19:35:15.000000000 +0000 @@ -0,0 +1,176968 @@ +commit f599001496e2bbacd54e11fb9fbabda694d308f2 +Author: ddv2005 +Date: Wed Aug 15 15:09:24 2012 -0400 + + Update Synopsys USB OTG driver to v2.94a and disable CRYPTOLIB + +Index: linux-3.2.46/drivers/usb/host/dwc_common_port/Makefile +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_common_port/Makefile 2013-07-26 19:34:16.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_common_port/Makefile 2013-07-26 19:34:39.000000000 +0000 +@@ -4,21 +4,25 @@ + + ifneq ($(KERNELRELEASE),) + +-#CPPFLAGS += -DDEBUG_MEMORY +- +-ifeq ($(CONFIG_USB_DEBUG),y) +-CPPFLAGS += -DDEBUG +-endif +-CPPFLAGS += -DDWC_LINUX ++EXTRA_CFLAGS += -DDWC_LINUX ++#EXTRA_CFLAGS += -DDEBUG ++#EXTRA_CFLAGS += -DDWC_DEBUG_REGS ++#EXTRA_CFLAGS += -DDWC_DEBUG_MEMORY ++ ++EXTRA_CFLAGS += -DDWC_LIBMODULE ++EXTRA_CFLAGS += -DDWC_CCLIB ++#EXTRA_CFLAGS += -DDWC_CRYPTOLIB ++EXTRA_CFLAGS += -DDWC_NOTIFYLIB ++EXTRA_CFLAGS += -DDWC_UTFLIB + + obj-$(CONFIG_USB_DWCOTG) += dwc_common_port_lib.o +-dwc_common_port_lib-objs := dwc_cc.o \ +- dwc_notifier.o \ +- dwc_common_linux.o dwc_mem.o ++dwc_common_port_lib-objs := dwc_cc.o dwc_modpow.o dwc_dh.o \ ++ dwc_crypto.o dwc_notifier.o \ ++ dwc_common_linux.o dwc_mem.o + + kernrelwd := $(subst ., ,$(KERNELRELEASE)) + kernrel3 := $(word 1,$(kernrelwd)).$(word 2,$(kernrelwd)).$(word 3,$(kernrelwd)) +- ++ + ifneq ($(kernrel3),2.6.20) + # grayg - I only know that we use EXTRA_CFLAGS in 2.6.31 actually + EXTRA_CFLAGS += $(CPPFLAGS) +@@ -26,12 +30,21 @@ + + else + ++ifeq ($(KDIR),) ++$(error Must give "KDIR=/path/to/kernel/source" on command line or in environment) ++endif ++ ++ifeq ($(ARCH),) ++$(error Must give "ARCH=" on command line or in environment. Also, if \ ++ cross-compiling, must give "CROSS_COMPILE=/path/to/compiler/plus/tool-prefix-") ++endif ++ + ifeq ($(DOXYGEN),) +-DOXYGEN := $(DOXYGEN) ++DOXYGEN := doxygen + endif + + default: +- $(MAKE) -C$(KDIR) M=$(PWD) modules ++ $(MAKE) -C$(KDIR) M=$(PWD) ARCH=$(ARCH) CROSS_COMPILE=$(CROSS_COMPILE) modules + + docs: $(wildcard *.[hc]) doc/doxygen.cfg + $(DOXYGEN) doc/doxygen.cfg +@@ -42,5 +55,4 @@ + endif + + clean: +- rm -rf *.o *.ko .*cmd *.mod.c .tmp_versions Module.symvers +- ++ rm -rf *.o *.ko .*.cmd *.mod.c .*.o.d .*.o.tmp modules.order Module.markers Module.symvers .tmp_versions/ +Index: linux-3.2.46/drivers/usb/host/dwc_common_port/Makefile.fbsd +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_common_port/Makefile.fbsd 2013-07-26 19:34:39.000000000 +0000 +@@ -0,0 +1,17 @@ ++CFLAGS += -I/sys/i386/compile/GENERIC -I/sys/i386/include -I/usr/include ++CFLAGS += -DDWC_FREEBSD ++CFLAGS += -DDEBUG ++#CFLAGS += -DDWC_DEBUG_REGS ++#CFLAGS += -DDWC_DEBUG_MEMORY ++ ++#CFLAGS += -DDWC_LIBMODULE ++#CFLAGS += -DDWC_CCLIB ++#CFLAGS += -DDWC_CRYPTOLIB ++#CFLAGS += -DDWC_NOTIFYLIB ++#CFLAGS += -DDWC_UTFLIB ++ ++KMOD = dwc_common_port_lib ++SRCS = dwc_cc.c dwc_modpow.c dwc_dh.c dwc_crypto.c dwc_notifier.c \ ++ dwc_common_fbsd.c dwc_mem.c ++ ++.include +Index: linux-3.2.46/drivers/usb/host/dwc_common_port/Makefile.linux +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_common_port/Makefile.linux 2013-07-26 19:31:19.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_common_port/Makefile.linux 2013-07-26 19:34:39.000000000 +0000 +@@ -3,25 +3,39 @@ + # + ifneq ($(KERNELRELEASE),) + +-#CPPFLAGS += -DDEBUG_MEMORY +- +-#CPPFLAGS += -DDEBUG +-CPPFLAGS += -DDWC_LINUX +- +-obj-m := dwc_common_port_lib.o +-dwc_common_port_lib-objs := dwc_cc.o dwc_modpow.o dwc_dh.o \ +- dwc_crypto.o dwc_notifier.o \ +- dwc_common_linux.o dwc_mem.o ++EXTRA_CFLAGS += -DDWC_LINUX ++#EXTRA_CFLAGS += -DDEBUG ++#EXTRA_CFLAGS += -DDWC_DEBUG_REGS ++#EXTRA_CFLAGS += -DDWC_DEBUG_MEMORY ++ ++EXTRA_CFLAGS += -DDWC_LIBMODULE ++EXTRA_CFLAGS += -DDWC_CCLIB ++EXTRA_CFLAGS += -DDWC_CRYPTOLIB ++EXTRA_CFLAGS += -DDWC_NOTIFYLIB ++EXTRA_CFLAGS += -DDWC_UTFLIB ++ ++obj-m := dwc_common_port_lib.o ++dwc_common_port_lib-objs := dwc_cc.o dwc_modpow.o dwc_dh.o \ ++ dwc_crypto.o dwc_notifier.o \ ++ dwc_common_linux.o dwc_mem.o + + else + ++ifeq ($(KDIR),) ++$(error Must give "KDIR=/path/to/kernel/source" on command line or in environment) ++endif ++ ++ifeq ($(ARCH),) ++$(error Must give "ARCH=" on command line or in environment. Also, if \ ++ cross-compiling, must give "CROSS_COMPILE=/path/to/compiler/plus/tool-prefix-") ++endif + + ifeq ($(DOXYGEN),) +-DOXYGEN := $(DOXYGEN) ++DOXYGEN := doxygen + endif + + default: +- $(MAKE) -C$(KDIR) M=$(PWD) modules ++ $(MAKE) -C$(KDIR) M=$(PWD) ARCH=$(ARCH) CROSS_COMPILE=$(CROSS_COMPILE) modules + + docs: $(wildcard *.[hc]) doc/doxygen.cfg + $(DOXYGEN) doc/doxygen.cfg +@@ -32,5 +46,4 @@ + endif + + clean: +- rm -rf *.o *.ko .*cmd *.mod.c .tmp_versions Module.symvers +- ++ rm -rf *.o *.ko .*.cmd *.mod.c .*.o.d .*.o.tmp modules.order Module.markers Module.symvers .tmp_versions/ +Index: linux-3.2.46/drivers/usb/host/dwc_common_port/changes.txt +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_common_port/changes.txt 2013-07-26 19:34:39.000000000 +0000 +@@ -0,0 +1,174 @@ ++ ++dwc_read_reg32() and friends now take an additional parameter, a pointer to an ++IO context struct. The IO context struct should live in an os-dependent struct ++in your driver. As an example, the dwc_usb3 driver has an os-dependent struct ++named 'os_dep' embedded in the main device struct. So there these calls look ++like this: ++ ++ dwc_read_reg32(&usb3_dev->os_dep.ioctx, &pcd->dev_global_regs->dcfg); ++ ++ dwc_write_reg32(&usb3_dev->os_dep.ioctx, ++ &pcd->dev_global_regs->dcfg, 0); ++ ++Note that for the existing Linux driver ports, it is not necessary to actually ++define the 'ioctx' member in the os-dependent struct. Since Linux does not ++require an IO context, its macros for dwc_read_reg32() and friends do not ++use the context pointer, so it is optimized away by the compiler. But it is ++necessary to add the pointer parameter to all of the call sites, to be ready ++for any future ports (such as FreeBSD) which do require an IO context. ++ ++ ++Similarly, dwc_alloc(), dwc_alloc_atomic(), dwc_strdup(), and dwc_free() now ++take an additional parameter, a pointer to a memory context. Examples: ++ ++ addr = dwc_alloc(&usb3_dev->os_dep.memctx, size); ++ ++ dwc_free(&usb3_dev->os_dep.memctx, addr); ++ ++Again, for the Linux ports, it is not necessary to actually define the memctx ++member, but it is necessary to add the pointer parameter to all of the call ++sites. ++ ++ ++Same for dwc_dma_alloc() and dwc_dma_free(). Examples: ++ ++ virt_addr = dwc_dma_alloc(&usb3_dev->os_dep.dmactx, size, &phys_addr); ++ ++ dwc_dma_free(&usb3_dev->os_dep.dmactx, size, virt_addr, phys_addr); ++ ++ ++Same for dwc_mutex_alloc() and dwc_mutex_free(). Examples: ++ ++ mutex = dwc_mutex_alloc(&usb3_dev->os_dep.mtxctx); ++ ++ dwc_mutex_free(&usb3_dev->os_dep.mtxctx, mutex); ++ ++ ++Same for dwc_spinlock_alloc() and dwc_spinlock_free(). Examples: ++ ++ lock = dwc_spinlock_alloc(&usb3_dev->osdep.splctx); ++ ++ dwc_spinlock_free(&usb3_dev->osdep.splctx, lock); ++ ++ ++Same for dwc_timer_alloc(). Example: ++ ++ timer = dwc_timer_alloc(&usb3_dev->os_dep.tmrctx, "dwc_usb3_tmr1", ++ cb_func, cb_data); ++ ++ ++Same for dwc_waitq_alloc(). Example: ++ ++ waitq = dwc_waitq_alloc(&usb3_dev->os_dep.wtqctx); ++ ++ ++Same for dwc_thread_run(). Example: ++ ++ thread = dwc_thread_run(&usb3_dev->os_dep.thdctx, func, ++ "dwc_usb3_thd1", data); ++ ++ ++Same for dwc_workq_alloc(). Example: ++ ++ workq = dwc_workq_alloc(&usb3_dev->osdep.wkqctx, "dwc_usb3_wkq1"); ++ ++ ++Same for dwc_task_alloc(). Example: ++ ++ task = dwc_task_alloc(&usb3_dev->os_dep.tskctx, "dwc_usb3_tsk1", ++ cb_func, cb_data); ++ ++ ++In addition to the context pointer additions, a few core functions have had ++other changes made to their parameters: ++ ++The 'flags' parameter to dwc_spinlock_irqsave() and dwc_spinunlock_irqrestore() ++has been changed from a uint64_t to a dwc_irqflags_t. ++ ++dwc_thread_should_stop() now takes a 'dwc_thread_t *' parameter, because the ++FreeBSD equivalent of that function requires it. ++ ++And, in addition to the context pointer, dwc_task_alloc() also adds a ++'char *name' parameter, to be consistent with dwc_thread_run() and ++dwc_workq_alloc(), and because the FreeBSD equivalent of that function ++requires a unique name. ++ ++ ++Here is a complete list of the core functions that now take a pointer to a ++context as their first parameter: ++ ++ dwc_read_reg32 ++ dwc_read_reg64 ++ dwc_write_reg32 ++ dwc_write_reg64 ++ dwc_modify_reg32 ++ dwc_modify_reg64 ++ dwc_alloc ++ dwc_alloc_atomic ++ dwc_strdup ++ dwc_free ++ dwc_dma_alloc ++ dwc_dma_free ++ dwc_mutex_alloc ++ dwc_mutex_free ++ dwc_spinlock_alloc ++ dwc_spinlock_free ++ dwc_timer_alloc ++ dwc_waitq_alloc ++ dwc_thread_run ++ dwc_workq_alloc ++ dwc_task_alloc Also adds a 'char *name' as its 2nd parameter ++ ++And here are the core functions that have other changes to their parameters: ++ ++ dwc_spinlock_irqsave 'flags' param is now a 'dwc_irqflags_t *' ++ dwc_spinunlock_irqrestore 'flags' param is now a 'dwc_irqflags_t' ++ dwc_thread_should_stop Adds a 'dwc_thread_t *' parameter ++ ++ ++ ++The changes to the core functions also require some of the other library ++functions to change: ++ ++ dwc_cc_if_alloc() and dwc_cc_if_free() now take a 'void *memctx' ++ (for memory allocation) as the 1st param and a 'void *mtxctx' ++ (for mutex allocation) as the 2nd param. ++ ++ dwc_cc_clear(), dwc_cc_add(), dwc_cc_change(), dwc_cc_remove(), ++ dwc_cc_data_for_save(), and dwc_cc_restore_from_data() now take a ++ 'void *memctx' as the 1st param. ++ ++ dwc_dh_modpow(), dwc_dh_pk(), and dwc_dh_derive_keys() now take a ++ 'void *memctx' as the 1st param. ++ ++ dwc_modpow() now takes a 'void *memctx' as the 1st param. ++ ++ dwc_alloc_notification_manager() now takes a 'void *memctx' as the ++ 1st param and a 'void *wkqctx' (for work queue allocation) as the 2nd ++ param, and also now returns an integer value that is non-zero if ++ allocation of its data structures or work queue fails. ++ ++ dwc_register_notifier() now takes a 'void *memctx' as the 1st param. ++ ++ dwc_memory_debug_start() now takes a 'void *mem_ctx' as the first ++ param, and also now returns an integer value that is non-zero if ++ allocation of its data structures fails. ++ ++ ++ ++Other miscellaneous changes: ++ ++The DEBUG_MEMORY and DEBUG_REGS #define's have been renamed to ++DWC_DEBUG_MEMORY and DWC_DEBUG_REGS. ++ ++The following #define's have been added to allow selectively compiling library ++features: ++ ++ DWC_CCLIB ++ DWC_CRYPTOLIB ++ DWC_NOTIFYLIB ++ DWC_UTFLIB ++ ++A DWC_LIBMODULE #define has also been added. If this is not defined, then the ++module code in dwc_common_linux.c is not compiled in. This allows linking the ++library code directly into a driver module, instead of as a standalone module. +Index: linux-3.2.46/drivers/usb/host/dwc_common_port/doc/html/dir_c13d72e45af28cdc461a5f284d3d36fc.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_common_port/doc/html/dir_c13d72e45af28cdc461a5f284d3d36fc.html 2013-07-26 19:31:19.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,81 +0,0 @@ +- +- +-Synopsys DWC Portability and Common Library for UWB: dwc_common_port/ Directory Reference +- +- +- +- +-

+-
+-
+-dwc_common_port
+-

dwc_common_port Directory Reference

+-

+- +- +- +- +- +- +- +- +- +-

+-

+- +- +- +- +- +-

+-

+- +- +- +-

+-

+- +- +- +- +- +-

+-

+- +- +- +-

+-

+- +- +- +- +- +- +- +-

+-

+- +- +- +- +- +-

+-

+- +- +- +-

+-

+- +-

Files

file  dwc_cc.c
file  dwc_cc.h
 This file defines the Context Context library.
file  dwc_common_linux.c
file  dwc_crypto.c
 This file contains the WUSB cryptographic routines.
file  dwc_crypto.h
 This file contains declarations for the WUSB Cryptographic routines as defined in the WUSB spec.
file  dwc_dh.c
file  dwc_dh.h
 This file defines the common functions on device and host for performing numeric association as defined in the WUSB spec.
file  dwc_list.h
 This file defines linked list operations.
file  dwc_mem.c
file  dwc_modpow.c
file  dwc_modpow.h
 This file defines the module exponentiation function which is only used internally by the DWC UWB modules for calculation of PKs during numeric association.
file  dwc_notifier.c
file  dwc_notifier.h
 A simple implementation of the Observer pattern.
file  dwc_os.h
 DWC portability library, low level os-wrapper functions.
file  usb.h
+-

Generated on Tue May 5 02:22:50 2009 for Synopsys DWC Portability and Common Library for UWB by  +- +-doxygen 1.4.7
+- +- +Index: linux-3.2.46/drivers/usb/host/dwc_common_port/doc/html/dirs.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_common_port/doc/html/dirs.html 2013-07-26 19:31:19.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,22 +0,0 @@ +- +- +-Synopsys DWC Portability and Common Library for UWB: Directory Hierarchy +- +- +- +- +-
+-
+-

Synopsys DWC Portability and Common Library for UWB Directories

This directory hierarchy is sorted roughly, but not completely, alphabetically: +-
Generated on Tue May 5 02:22:50 2009 for Synopsys DWC Portability and Common Library for UWB by  +- +-doxygen 1.4.7
+- +- +Index: linux-3.2.46/drivers/usb/host/dwc_common_port/doc/html/doxygen.css +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_common_port/doc/html/doxygen.css 2013-07-26 19:31:19.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,358 +0,0 @@ +-BODY,H1,H2,H3,H4,H5,H6,P,CENTER,TD,TH,UL,DL,DIV { +- font-family: Geneva, Arial, Helvetica, sans-serif; +-} +-BODY,TD { +- font-size: 90%; +-} +-H1 { +- text-align: center; +- font-size: 160%; +-} +-H2 { +- font-size: 120%; +-} +-H3 { +- font-size: 100%; +-} +-CAPTION { font-weight: bold } +-DIV.qindex { +- width: 100%; +- background-color: #e8eef2; +- border: 1px solid #84b0c7; +- text-align: center; +- margin: 2px; +- padding: 2px; +- line-height: 140%; +-} +-DIV.nav { +- width: 100%; +- background-color: #e8eef2; +- border: 1px solid #84b0c7; +- text-align: center; +- margin: 2px; +- padding: 2px; +- line-height: 140%; +-} +-DIV.navtab { +- background-color: #e8eef2; +- border: 1px solid #84b0c7; +- text-align: center; +- margin: 2px; +- margin-right: 15px; +- padding: 2px; +-} +-TD.navtab { +- font-size: 70%; +-} +-A.qindex { +- text-decoration: none; +- font-weight: bold; +- color: #1A419D; +-} +-A.qindex:visited { +- text-decoration: none; +- font-weight: bold; +- color: #1A419D +-} +-A.qindex:hover { +- text-decoration: none; +- background-color: #ddddff; +-} +-A.qindexHL { +- text-decoration: none; +- font-weight: bold; +- background-color: #6666cc; +- color: #ffffff; +- border: 1px double #9295C2; +-} +-A.qindexHL:hover { +- text-decoration: none; +- background-color: #6666cc; +- color: #ffffff; +-} +-A.qindexHL:visited { text-decoration: none; background-color: #6666cc; color: #ffffff } +-A.el { text-decoration: none; font-weight: bold } +-A.elRef { font-weight: bold } +-A.code:link { text-decoration: none; font-weight: normal; color: #0000FF} +-A.code:visited { text-decoration: none; font-weight: normal; color: #0000FF} +-A.codeRef:link { font-weight: normal; color: #0000FF} +-A.codeRef:visited { font-weight: normal; color: #0000FF} +-A:hover { text-decoration: none; background-color: #f2f2ff } +-DL.el { margin-left: -1cm } +-.fragment { +- font-family: monospace, fixed; +- font-size: 95%; +-} +-PRE.fragment { +- border: 1px solid #CCCCCC; +- background-color: #f5f5f5; +- margin-top: 4px; +- margin-bottom: 4px; +- margin-left: 2px; +- margin-right: 8px; +- padding-left: 6px; +- padding-right: 6px; +- padding-top: 4px; +- padding-bottom: 4px; +-} +-DIV.ah { background-color: black; font-weight: bold; color: #ffffff; margin-bottom: 3px; margin-top: 3px } +- +-DIV.groupHeader { +- margin-left: 16px; +- margin-top: 12px; +- margin-bottom: 6px; +- font-weight: bold; +-} +-DIV.groupText { margin-left: 16px; font-style: italic; font-size: 90% } +-BODY { +- background: white; +- color: black; +- margin-right: 20px; +- margin-left: 20px; +-} +-TD.indexkey { +- background-color: #e8eef2; +- font-weight: bold; +- padding-right : 10px; +- padding-top : 2px; +- padding-left : 10px; +- padding-bottom : 2px; +- margin-left : 0px; +- margin-right : 0px; +- margin-top : 2px; +- margin-bottom : 2px; +- border: 1px solid #CCCCCC; +-} +-TD.indexvalue { +- background-color: #e8eef2; +- font-style: italic; +- padding-right : 10px; +- padding-top : 2px; +- padding-left : 10px; +- padding-bottom : 2px; +- margin-left : 0px; +- margin-right : 0px; +- margin-top : 2px; +- margin-bottom : 2px; +- border: 1px solid #CCCCCC; +-} +-TR.memlist { +- background-color: #f0f0f0; +-} +-P.formulaDsp { text-align: center; } +-IMG.formulaDsp { } +-IMG.formulaInl { vertical-align: middle; } +-SPAN.keyword { color: #008000 } +-SPAN.keywordtype { color: #604020 } +-SPAN.keywordflow { color: #e08000 } +-SPAN.comment { color: #800000 } +-SPAN.preprocessor { color: #806020 } +-SPAN.stringliteral { color: #002080 } +-SPAN.charliteral { color: #008080 } +-.mdescLeft { +- padding: 0px 8px 4px 8px; +- font-size: 80%; +- font-style: italic; +- background-color: #FAFAFA; +- border-top: 1px none #E0E0E0; +- border-right: 1px none #E0E0E0; +- border-bottom: 1px none #E0E0E0; +- border-left: 1px none #E0E0E0; +- margin: 0px; +-} +-.mdescRight { +- padding: 0px 8px 4px 8px; +- font-size: 80%; +- font-style: italic; +- background-color: #FAFAFA; +- border-top: 1px none #E0E0E0; +- border-right: 1px none #E0E0E0; +- border-bottom: 1px none #E0E0E0; +- border-left: 1px none #E0E0E0; +- margin: 0px; +-} +-.memItemLeft { +- padding: 1px 0px 0px 8px; +- margin: 4px; +- border-top-width: 1px; +- border-right-width: 1px; +- border-bottom-width: 1px; +- border-left-width: 1px; +- border-top-color: #E0E0E0; +- border-right-color: #E0E0E0; +- border-bottom-color: #E0E0E0; +- border-left-color: #E0E0E0; +- border-top-style: solid; +- border-right-style: none; +- border-bottom-style: none; +- border-left-style: none; +- background-color: #FAFAFA; +- font-size: 80%; +-} +-.memItemRight { +- padding: 1px 8px 0px 8px; +- margin: 4px; +- border-top-width: 1px; +- border-right-width: 1px; +- border-bottom-width: 1px; +- border-left-width: 1px; +- border-top-color: #E0E0E0; +- border-right-color: #E0E0E0; +- border-bottom-color: #E0E0E0; +- border-left-color: #E0E0E0; +- border-top-style: solid; +- border-right-style: none; +- border-bottom-style: none; +- border-left-style: none; +- background-color: #FAFAFA; +- font-size: 80%; +-} +-.memTemplItemLeft { +- padding: 1px 0px 0px 8px; +- margin: 4px; +- border-top-width: 1px; +- border-right-width: 1px; +- border-bottom-width: 1px; +- border-left-width: 1px; +- border-top-color: #E0E0E0; +- border-right-color: #E0E0E0; +- border-bottom-color: #E0E0E0; +- border-left-color: #E0E0E0; +- border-top-style: none; +- border-right-style: none; +- border-bottom-style: none; +- border-left-style: none; +- background-color: #FAFAFA; +- font-size: 80%; +-} +-.memTemplItemRight { +- padding: 1px 8px 0px 8px; +- margin: 4px; +- border-top-width: 1px; +- border-right-width: 1px; +- border-bottom-width: 1px; +- border-left-width: 1px; +- border-top-color: #E0E0E0; +- border-right-color: #E0E0E0; +- border-bottom-color: #E0E0E0; +- border-left-color: #E0E0E0; +- border-top-style: none; +- border-right-style: none; +- border-bottom-style: none; +- border-left-style: none; +- background-color: #FAFAFA; +- font-size: 80%; +-} +-.memTemplParams { +- padding: 1px 0px 0px 8px; +- margin: 4px; +- border-top-width: 1px; +- border-right-width: 1px; +- border-bottom-width: 1px; +- border-left-width: 1px; +- border-top-color: #E0E0E0; +- border-right-color: #E0E0E0; +- border-bottom-color: #E0E0E0; +- border-left-color: #E0E0E0; +- border-top-style: solid; +- border-right-style: none; +- border-bottom-style: none; +- border-left-style: none; +- color: #606060; +- background-color: #FAFAFA; +- font-size: 80%; +-} +-.search { color: #003399; +- font-weight: bold; +-} +-FORM.search { +- margin-bottom: 0px; +- margin-top: 0px; +-} +-INPUT.search { font-size: 75%; +- color: #000080; +- font-weight: normal; +- background-color: #e8eef2; +-} +-TD.tiny { font-size: 75%; +-} +-a { +- color: #1A41A8; +-} +-a:visited { +- color: #2A3798; +-} +-.dirtab { padding: 4px; +- border-collapse: collapse; +- border: 1px solid #84b0c7; +-} +-TH.dirtab { background: #e8eef2; +- font-weight: bold; +-} +-HR { height: 1px; +- border: none; +- border-top: 1px solid black; +-} +- +-/* Style for detailed member documentation */ +-.memtemplate { +- font-size: 80%; +- color: #606060; +- font-weight: normal; +-} +-.memnav { +- background-color: #e8eef2; +- border: 1px solid #84b0c7; +- text-align: center; +- margin: 2px; +- margin-right: 15px; +- padding: 2px; +-} +-.memitem { +- padding: 4px; +- background-color: #eef3f5; +- border-width: 1px; +- border-style: solid; +- border-color: #dedeee; +- -moz-border-radius: 8px 8px 8px 8px; +-} +-.memname { +- white-space: nowrap; +- font-weight: bold; +-} +-.memdoc{ +- padding-left: 10px; +-} +-.memproto { +- background-color: #d5e1e8; +- width: 100%; +- border-width: 1px; +- border-style: solid; +- border-color: #84b0c7; +- font-weight: bold; +- -moz-border-radius: 8px 8px 8px 8px; +-} +-.paramkey { +- text-align: right; +-} +-.paramtype { +- white-space: nowrap; +-} +-.paramname { +- color: #602020; +- font-style: italic; +-} +-/* End Styling for detailed member documentation */ +- +-/* for the tree view */ +-.ftvtree { +- font-family: sans-serif; +- margin:0.5em; +-} +-.directory { font-size: 9pt; font-weight: bold; } +-.directory h3 { margin: 0px; margin-top: 1em; font-size: 11pt; } +-.directory > h3 { margin-top: 0; } +-.directory p { margin: 0px; white-space: nowrap; } +-.directory div { display: none; margin: 0px; } +-.directory img { vertical-align: -30%; } +- +Index: linux-3.2.46/drivers/usb/host/dwc_common_port/doc/html/dwc__cc_8h.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_common_port/doc/html/dwc__cc_8h.html 2013-07-26 19:31:19.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,709 +0,0 @@ +- +- +-Synopsys DWC Portability and Common Library for UWB: dwc_cc.h File Reference +- +- +- +- +-
+-
+-
+-
+-
+-dwc_common_port
+-

dwc_cc.h File Reference

Detailed Description

+-This file defines the Context Context library. +-

+-The main data structure is dwc_cc_if_t which is returned by either the dwc_cc_if_alloc function or returned by the module to the user via a provided function. The data structure is opaque and should only be manipulated via the functions provied in this API.

+-It manages a list of connection contexts and operations can be performed to add, remove, query, search, and change, those contexts. Additionally, a dwc_notifier_t object can be requested from the manager so that the user can be notified whenever the context list has changed. +-

+- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-

Connection Context Operations

dwc_cc_if_t * dwc_cc_if_alloc (dwc_notifier_t *notifier, unsigned is_host)
 This function allocates memory for a dwc_cc_if_t structure, initializes fields to default values, and returns a pointer to the structure or NULL on error.
void dwc_cc_if_free (dwc_cc_if_t *cc_if)
 Frees the memory for the specified CC structure allocated from dwc_cc_if_alloc().
void dwc_cc_clear (dwc_cc_if_t *cc_if)
 Removes all contexts from the connection context list.
int32_t dwc_cc_add (dwc_cc_if_t *cc_if, uint8_t *chid, uint8_t *cdid, uint8_t *ck, uint8_t *name, uint8_t length)
 Adds a connection context (CHID, CK, CDID, Name) to the connection context list.
void dwc_cc_change (dwc_cc_if_t *cc_if, int32_t id, uint8_t *chid, uint8_t *cdid, uint8_t *ck, uint8_t *name, uint8_t length)
 Changes the CHID, CK, CDID, or Name values of a connection context in the list, preserving any accumulated statistics.
void dwc_cc_remove (dwc_cc_if_t *cc_if, int32_t id)
 Remove the specified connection context.
uint8_t * dwc_cc_data_for_save (dwc_cc_if_t *cc_if, unsigned int *length)
 Get a binary block of data for the connection context list and attributes.
void dwc_cc_restore_from_data (dwc_cc_if_t *cc_if, uint8_t *data, unsigned int length)
 Restore the connection context list from the binary data that was previously returned from a call to dwc_cc_data_for_save.
uint32_t dwc_cc_match_chid (dwc_cc_if_t *cc_if, uint8_t *chid)
 Find the connection context from the specified CHID.
uint32_t dwc_cc_match_cdid (dwc_cc_if_t *cc_if, uint8_t *cdid)
 Find the connection context from the specified CDID.
uint8_t * dwc_cc_ck (dwc_cc_if_t *cc_if, int32_t id)
 Retrieve the CK from the specified connection context.
uint8_t * dwc_cc_chid (dwc_cc_if_t *cc_if, int32_t id)
 Retrieve the CHID from the specified connection context.
uint8_t * dwc_cc_cdid (dwc_cc_if_t *cc_if, int32_t id)
 Retrieve the CDID from the specified connection context.
+-uint8_t * dwc_cc_name (dwc_cc_if_t *cc_if, int32_t id, uint8_t *length)
static unsigned dwc_assoc_is_not_zero_id (uint8_t *id)
 Checks a buffer for non-zero.
static unsigned dwc_assoc_is_zero_id (uint8_t *id)
 Checks a buffer for zero.
static int dwc_print_id_string (char *buffer, uint8_t *id)
 Prints an ASCII representation for the 16-byte chid, cdid, or ck, into buffer.

Defines

+-#define DWC_CC_LIST_CHANGED_NOTIFICATION   "DWC_CC_LIST_CHANGED_NOTIFICATION"

Typedefs

+-typedef dwc_cc_if dwc_cc_if_t
+-

Function Documentation

+- +-
+-
+- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
dwc_cc_if_t* dwc_cc_if_alloc (dwc_notifier_t *  notifier,
unsigned  is_host 
)
+-
+-
+- +-

+-This function allocates memory for a dwc_cc_if_t structure, initializes fields to default values, and returns a pointer to the structure or NULL on error. +-

+- +-

+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +-
void dwc_cc_if_free (dwc_cc_if_t *  cc_if  ) 
+-
+-
+- +-

+-Frees the memory for the specified CC structure allocated from dwc_cc_if_alloc(). +-

+- +-

+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +-
void dwc_cc_clear (dwc_cc_if_t *  cc_if  ) 
+-
+-
+- +-

+-Removes all contexts from the connection context list. +-

+- +-

+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
int32_t dwc_cc_add (dwc_cc_if_t *  cc_if,
uint8_t *  chid,
uint8_t *  cdid,
uint8_t *  ck,
uint8_t *  name,
uint8_t  length 
)
+-
+-
+- +-

+-Adds a connection context (CHID, CK, CDID, Name) to the connection context list. +-

+-If a CHID already exists, the CK and name are overwritten. Statistics are not overwritten.

+-

Parameters:
+- +- +- +- +- +- +- +-
cc_if The cc_if structure.
chid A pointer to the 16-byte CHID. This value will be copied.
ck A pointer to the 16-byte CK. This value will be copied.
cdid A pointer to the 16-byte CDID. This value will be copied.
name An optional host friendly name as defined in the association model spec. Must be a UTF16-LE unicode string. Can be NULL to indicated no name.
length The length othe unicode string.
+-
+-
Returns:
A unique identifier used to refer to this context that is valid for as long as this context is still in the list.
+- +-
+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
void dwc_cc_change (dwc_cc_if_t *  cc_if,
int32_t  id,
uint8_t *  chid,
uint8_t *  cdid,
uint8_t *  ck,
uint8_t *  name,
uint8_t  length 
)
+-
+-
+- +-

+-Changes the CHID, CK, CDID, or Name values of a connection context in the list, preserving any accumulated statistics. +-

+-This would typically be called if the host decideds to change the context with a SET_CONNECTION request.

+-

Parameters:
+- +- +- +- +- +- +- +- +-
cc_if The cc_if structure.
id The identifier of the connection context.
chid A pointer to the 16-byte CHID. This value will be copied. NULL indicates no change.
cdid A pointer to the 16-byte CDID. This value will be copied. NULL indicates no change.
ck A pointer to the 16-byte CK. This value will be copied. NULL indicates no change.
name Host friendly name UTF16-LE. NULL indicates no change.
length Length of name.
+-
+- +-
+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
void dwc_cc_remove (dwc_cc_if_t *  cc_if,
int32_t  id 
)
+-
+-
+- +-

+-Remove the specified connection context. +-

+-

Parameters:
+- +- +- +-
cc_if The cc_if structure.
id The identifier of the connection context to remove.
+-
+- +-
+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
uint8_t* dwc_cc_data_for_save (dwc_cc_if_t *  cc_if,
unsigned int *  length 
)
+-
+-
+- +-

+-Get a binary block of data for the connection context list and attributes. +-

+-This data can be used by the OS specific driver to save the connection context list into non-volatile memory.

+-

Parameters:
+- +- +- +-
cc_if The cc_if structure.
length Return the length of the data buffer.
+-
+-
Returns:
A pointer to the data buffer. The memory for this buffer should be freed with DWC_FREE() after use.
+- +-
+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
void dwc_cc_restore_from_data (dwc_cc_if_t *  cc_if,
uint8_t *  data,
unsigned int  length 
)
+-
+-
+- +-

+-Restore the connection context list from the binary data that was previously returned from a call to dwc_cc_data_for_save. +-

+-This can be used by the OS specific driver to load a connection context list from non-volatile memory.

+-

Parameters:
+- +- +- +- +-
cc_if The cc_if structure.
data The data bytes as returned from dwc_cc_data_for_save.
length The length of the data.
+-
+- +-
+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
uint32_t dwc_cc_match_chid (dwc_cc_if_t *  cc_if,
uint8_t *  chid 
)
+-
+-
+- +-

+-Find the connection context from the specified CHID. +-

+-

Parameters:
+- +- +- +-
cc_if The cc_if structure.
chid A pointer to the CHID data.
+-
+-
Returns:
A non-zero identifier of the connection context if the CHID matches. Otherwise returns 0.
+- +-
+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
uint32_t dwc_cc_match_cdid (dwc_cc_if_t *  cc_if,
uint8_t *  cdid 
)
+-
+-
+- +-

+-Find the connection context from the specified CDID. +-

+-

Parameters:
+- +- +- +-
cc_if The cc_if structure.
cdid A pointer to the CDID data.
+-
+-
Returns:
A non-zero identifier of the connection context if the CHID matches. Otherwise returns 0.
+- +-
+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
uint8_t* dwc_cc_ck (dwc_cc_if_t *  cc_if,
int32_t  id 
)
+-
+-
+- +-

+-Retrieve the CK from the specified connection context. +-

+-

Parameters:
+- +- +- +-
cc_if The cc_if structure.
id The identifier of the connection context.
+-
+-
Returns:
A pointer to the CK data. The memory does not need to be freed.
+- +-
+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
uint8_t* dwc_cc_chid (dwc_cc_if_t *  cc_if,
int32_t  id 
)
+-
+-
+- +-

+-Retrieve the CHID from the specified connection context. +-

+-

Parameters:
+- +- +- +-
cc_if The cc_if structure.
id The identifier of the connection context.
+-
+-
Returns:
A pointer to the CHID data. The memory does not need to be freed.
+- +-
+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
uint8_t* dwc_cc_cdid (dwc_cc_if_t *  cc_if,
int32_t  id 
)
+-
+-
+- +-

+-Retrieve the CDID from the specified connection context. +-

+-

Parameters:
+- +- +- +-
cc_if The cc_if structure.
id The identifier of the connection context.
+-
+-
Returns:
A pointer to the CDID data. The memory does not need to be freed.
+- +-
+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +-
static unsigned dwc_assoc_is_not_zero_id (uint8_t *  id  )  [inline, static]
+-
+-
+- +-

+-Checks a buffer for non-zero. +-

+-

Parameters:
+- +- +-
id A pointer to a 16 byte buffer.
+-
+-
Returns:
true if the 16 byte value is non-zero.
+- +-
+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +-
static unsigned dwc_assoc_is_zero_id (uint8_t *  id  )  [inline, static]
+-
+-
+- +-

+-Checks a buffer for zero. +-

+-

Parameters:
+- +- +-
id A pointer to a 16 byte buffer.
+-
+-
Returns:
true if the 16 byte value is zero.
+- +-
+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
static int dwc_print_id_string (char *  buffer,
uint8_t *  id 
) [inline, static]
+-
+-
+- +-

+-Prints an ASCII representation for the 16-byte chid, cdid, or ck, into buffer. +-

+- +-

+-

+-

Generated on Tue May 5 02:22:50 2009 for Synopsys DWC Portability and Common Library for UWB by  +- +-doxygen 1.4.7
+- +- +Index: linux-3.2.46/drivers/usb/host/dwc_common_port/doc/html/dwc__crypto_8c.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_common_port/doc/html/dwc__crypto_8c.html 2013-07-26 19:31:19.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,435 +0,0 @@ +- +- +-Synopsys DWC Portability and Common Library for UWB: dwc_crypto.c File Reference +- +- +- +- +-
+-
+-
+-
+-
+-dwc_common_port
+-

dwc_crypto.c File Reference

Detailed Description

+-This file contains the WUSB cryptographic routines. +-

+- +-

+- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-

Functions

+-static void dump_bytes (char *name, uint8_t *bytes, int len)
+-void show_block (const u8 *blk, const char *prefix, const char *suffix, int a)
int dwc_wusb_aes_encrypt (u8 *src, u8 *key, u8 *dst)
 Encrypts an array of bytes using the AES encryption engine.
void dwc_wusb_cmf (u8 *key, u8 *nonce, char *label, u8 *bytes, int len, u8 *result)
 The CCM-MAC-FUNCTION described in section 6.5 of the WUSB spec.
void dwc_wusb_prf (int prf_len, u8 *key, u8 *nonce, char *label, u8 *bytes, int len, u8 *result)
 The PRF function described in section 6.5 of the WUSB spec.
void dwc_wusb_fill_ccm_nonce (uint16_t haddr, uint16_t daddr, uint8_t *tkid, uint8_t *nonce)
 Fills in CCM Nonce per the WUSB spec.
void dwc_wusb_gen_nonce (uint16_t addr, uint8_t *nonce)
 Generates a 16-byte cryptographic-grade random number for the Host/Device Nonce.
void dwc_wusb_gen_key (uint8_t *ccm_nonce, uint8_t *mk, uint8_t *hnonce, uint8_t *dnonce, uint8_t *kck, uint8_t *ptk)
 Generates the Session Key (PTK) and Key Confirmation Key (KCK) per the WUSB spec.
void dwc_wusb_gen_mic (uint8_t *ccm_nonce, uint8_t *kck, uint8_t *data, uint8_t *mic)
 Generates the Message Integrity Code over the Handshake data per the WUSB spec.
+-

Function Documentation

+- +-
+-
+- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
int dwc_wusb_aes_encrypt (u8 *  src,
u8 *  key,
u8 *  dst 
)
+-
+-
+- +-

+-Encrypts an array of bytes using the AES encryption engine. +-

+-If dst == src, then the bytes will be encrypted in-place.

+-

Returns:
0 on success, negative error code on error.
+- +-
+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
void dwc_wusb_cmf (u8 *  key,
u8 *  nonce,
char *  label,
u8 *  bytes,
int  len,
u8 *  result 
)
+-
+-
+- +-

+-The CCM-MAC-FUNCTION described in section 6.5 of the WUSB spec. +-

+-This function takes a data string and returns the encrypted CBC Counter-mode MIC.

+-

Parameters:
+- +- +- +- +- +- +- +-
key The 128-bit symmetric key.
nonce The CCM nonce.
label The unique 14-byte ASCII text label.
bytes The byte array to be encrypted.
len Length of the byte array.
result Byte array to receive the 8-byte encrypted MIC.
+-
+- +-
+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
void dwc_wusb_prf (int  prf_len,
u8 *  key,
u8 *  nonce,
char *  label,
u8 *  bytes,
int  len,
u8 *  result 
)
+-
+-
+- +-

+-The PRF function described in section 6.5 of the WUSB spec. +-

+-This function concatenates MIC values returned from dwc_cmf() to create a value of the requested length.

+-

Parameters:
+- +- +- +- +-
prf_len Length of the PRF function in bits (64, 128, or 256).
key,nonce,label,bytes,len Same as for dwc_cmf().
result Byte array to receive the result.
+-
+- +-
+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
void dwc_wusb_fill_ccm_nonce (uint16_t  haddr,
uint16_t  daddr,
uint8_t *  tkid,
uint8_t *  nonce 
)
+-
+-
+- +-

+-Fills in CCM Nonce per the WUSB spec. +-

+-

Parameters:
+- +- +- +- +- +-
[in] haddr Host address.
[in] daddr Device address.
[in] tkid Session Key(PTK) identifier.
[out] nonce Pointer to where the CCM Nonce output is to be written.
+-
+- +-
+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
void dwc_wusb_gen_nonce (uint16_t  addr,
uint8_t *  nonce 
)
+-
+-
+- +-

+-Generates a 16-byte cryptographic-grade random number for the Host/Device Nonce. +-

+- +-

+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
void dwc_wusb_gen_key (uint8_t *  ccm_nonce,
uint8_t *  mk,
uint8_t *  hnonce,
uint8_t *  dnonce,
uint8_t *  kck,
uint8_t *  ptk 
)
+-
+-
+- +-

+-Generates the Session Key (PTK) and Key Confirmation Key (KCK) per the WUSB spec. +-

+-

Parameters:
+- +- +- +- +- +- +- +-
[in] ccm_nonce Pointer to CCM Nonce.
[in] mk Master Key to derive the session from
[in] hnonce Pointer to Host Nonce.
[in] dnonce Pointer to Device Nonce.
[out] kck Pointer to where the KCK output is to be written.
[out] ptk Pointer to where the PTK output is to be written.
+-
+- +-
+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
void dwc_wusb_gen_mic (uint8_t *  ccm_nonce,
uint8_t *  kck,
uint8_t *  data,
uint8_t *  mic 
)
+-
+-
+- +-

+-Generates the Message Integrity Code over the Handshake data per the WUSB spec. +-

+-

Parameters:
+- +- +- +- +- +-
ccm_nonce Pointer to CCM Nonce.
kck Pointer to Key Confirmation Key.
data Pointer to Handshake data to be checked.
mic Pointer to where the MIC output is to be written.
+-
+- +-
+-

+-

Generated on Tue May 5 02:22:50 2009 for Synopsys DWC Portability and Common Library for UWB by  +- +-doxygen 1.4.7
+- +- +Index: linux-3.2.46/drivers/usb/host/dwc_common_port/doc/html/dwc__crypto_8h.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_common_port/doc/html/dwc__crypto_8h.html 2013-07-26 19:31:19.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,618 +0,0 @@ +- +- +-Synopsys DWC Portability and Common Library for UWB: dwc_crypto.h File Reference +- +- +- +- +-
+-
+-
+-
+-
+-dwc_common_port
+-

dwc_crypto.h File Reference

Detailed Description

+-This file contains declarations for the WUSB Cryptographic routines as defined in the WUSB spec. +-

+-They are only to be used internally by the DWC UWB modules. +-

+- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-

Functions

int dwc_wusb_aes_encrypt (u8 *src, u8 *key, u8 *dst)
 Encrypts an array of bytes using the AES encryption engine.
void dwc_wusb_cmf (u8 *key, u8 *nonce, char *label, u8 *bytes, int len, u8 *result)
 The CCM-MAC-FUNCTION described in section 6.5 of the WUSB spec.
void dwc_wusb_prf (int prf_len, u8 *key, u8 *nonce, char *label, u8 *bytes, int len, u8 *result)
 The PRF function described in section 6.5 of the WUSB spec.
static void dwc_wusb_prf_64 (u8 *key, u8 *nonce, char *label, u8 *bytes, int len, u8 *result)
 The PRF-64 function described in section 6.5 of the WUSB spec.
static void dwc_wusb_prf_128 (u8 *key, u8 *nonce, char *label, u8 *bytes, int len, u8 *result)
 The PRF-128 function described in section 6.5 of the WUSB spec.
static void dwc_wusb_prf_256 (u8 *key, u8 *nonce, char *label, u8 *bytes, int len, u8 *result)
 The PRF-256 function described in section 6.5 of the WUSB spec.
void dwc_wusb_fill_ccm_nonce (uint16_t haddr, uint16_t daddr, uint8_t *tkid, uint8_t *nonce)
 Fills in CCM Nonce per the WUSB spec.
void dwc_wusb_gen_nonce (uint16_t addr, uint8_t *nonce)
 Generates a 16-byte cryptographic-grade random number for the Host/Device Nonce.
void dwc_wusb_gen_key (uint8_t *ccm_nonce, uint8_t *mk, uint8_t *hnonce, uint8_t *dnonce, uint8_t *kck, uint8_t *ptk)
 Generates the Session Key (PTK) and Key Confirmation Key (KCK) per the WUSB spec.
void dwc_wusb_gen_mic (uint8_t *ccm_nonce, uint8_t *kck, uint8_t *data, uint8_t *mic)
 Generates the Message Integrity Code over the Handshake data per the WUSB spec.
+-

Function Documentation

+- +-
+-
+- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
int dwc_wusb_aes_encrypt (u8 *  src,
u8 *  key,
u8 *  dst 
)
+-
+-
+- +-

+-Encrypts an array of bytes using the AES encryption engine. +-

+-If dst == src, then the bytes will be encrypted in-place.

+-

Returns:
0 on success, negative error code on error.
+- +-
+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
void dwc_wusb_cmf (u8 *  key,
u8 *  nonce,
char *  label,
u8 *  bytes,
int  len,
u8 *  result 
)
+-
+-
+- +-

+-The CCM-MAC-FUNCTION described in section 6.5 of the WUSB spec. +-

+-This function takes a data string and returns the encrypted CBC Counter-mode MIC.

+-

Parameters:
+- +- +- +- +- +- +- +-
key The 128-bit symmetric key.
nonce The CCM nonce.
label The unique 14-byte ASCII text label.
bytes The byte array to be encrypted.
len Length of the byte array.
result Byte array to receive the 8-byte encrypted MIC.
+-
+- +-
+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
void dwc_wusb_prf (int  prf_len,
u8 *  key,
u8 *  nonce,
char *  label,
u8 *  bytes,
int  len,
u8 *  result 
)
+-
+-
+- +-

+-The PRF function described in section 6.5 of the WUSB spec. +-

+-This function concatenates MIC values returned from dwc_cmf() to create a value of the requested length.

+-

Parameters:
+- +- +- +- +-
prf_len Length of the PRF function in bits (64, 128, or 256).
key,nonce,label,bytes,len Same as for dwc_cmf().
result Byte array to receive the result.
+-
+- +-
+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
static void dwc_wusb_prf_64 (u8 *  key,
u8 *  nonce,
char *  label,
u8 *  bytes,
int  len,
u8 *  result 
) [inline, static]
+-
+-
+- +-

+-The PRF-64 function described in section 6.5 of the WUSB spec. +-

+-

Parameters:
+- +- +-
key,nonce,label,bytes,len,result Same as for dwc_prf().
+-
+- +-
+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
static void dwc_wusb_prf_128 (u8 *  key,
u8 *  nonce,
char *  label,
u8 *  bytes,
int  len,
u8 *  result 
) [inline, static]
+-
+-
+- +-

+-The PRF-128 function described in section 6.5 of the WUSB spec. +-

+-

Parameters:
+- +- +-
key,nonce,label,bytes,len,result Same as for dwc_prf().
+-
+- +-
+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
static void dwc_wusb_prf_256 (u8 *  key,
u8 *  nonce,
char *  label,
u8 *  bytes,
int  len,
u8 *  result 
) [inline, static]
+-
+-
+- +-

+-The PRF-256 function described in section 6.5 of the WUSB spec. +-

+-

Parameters:
+- +- +-
key,nonce,label,bytes,len,result Same as for dwc_prf().
+-
+- +-
+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
void dwc_wusb_fill_ccm_nonce (uint16_t  haddr,
uint16_t  daddr,
uint8_t *  tkid,
uint8_t *  nonce 
)
+-
+-
+- +-

+-Fills in CCM Nonce per the WUSB spec. +-

+-

Parameters:
+- +- +- +- +- +-
[in] haddr Host address.
[in] daddr Device address.
[in] tkid Session Key(PTK) identifier.
[out] nonce Pointer to where the CCM Nonce output is to be written.
+-
+- +-
+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
void dwc_wusb_gen_nonce (uint16_t  addr,
uint8_t *  nonce 
)
+-
+-
+- +-

+-Generates a 16-byte cryptographic-grade random number for the Host/Device Nonce. +-

+- +-

+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
void dwc_wusb_gen_key (uint8_t *  ccm_nonce,
uint8_t *  mk,
uint8_t *  hnonce,
uint8_t *  dnonce,
uint8_t *  kck,
uint8_t *  ptk 
)
+-
+-
+- +-

+-Generates the Session Key (PTK) and Key Confirmation Key (KCK) per the WUSB spec. +-

+-

Parameters:
+- +- +- +- +- +- +- +-
[in] ccm_nonce Pointer to CCM Nonce.
[in] mk Master Key to derive the session from
[in] hnonce Pointer to Host Nonce.
[in] dnonce Pointer to Device Nonce.
[out] kck Pointer to where the KCK output is to be written.
[out] ptk Pointer to where the PTK output is to be written.
+-
+- +-
+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
void dwc_wusb_gen_mic (uint8_t *  ccm_nonce,
uint8_t *  kck,
uint8_t *  data,
uint8_t *  mic 
)
+-
+-
+- +-

+-Generates the Message Integrity Code over the Handshake data per the WUSB spec. +-

+-

Parameters:
+- +- +- +- +- +-
ccm_nonce Pointer to CCM Nonce.
kck Pointer to Key Confirmation Key.
data Pointer to Handshake data to be checked.
mic Pointer to where the MIC output is to be written.
+-
+- +-
+-

+-

Generated on Tue May 5 02:22:50 2009 for Synopsys DWC Portability and Common Library for UWB by  +- +-doxygen 1.4.7
+- +- +Index: linux-3.2.46/drivers/usb/host/dwc_common_port/doc/html/dwc__dh_8h.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_common_port/doc/html/dwc__dh_8h.html 2013-07-26 19:31:19.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,166 +0,0 @@ +- +- +-Synopsys DWC Portability and Common Library for UWB: dwc_dh.h File Reference +- +- +- +- +-
+-
+-
+-
+-
+-dwc_common_port
+-

dwc_dh.h File Reference

Detailed Description

+-This file defines the common functions on device and host for performing numeric association as defined in the WUSB spec. +-

+-They are only to be used internally by the DWC UWB modules. +-

+- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-

Functions

+-int dwc_dh_sha256 (uint8_t *message, uint32_t len, uint8_t *out)
+-int dwc_dh_hmac_sha256 (uint8_t *message, uint32_t messagelen, uint8_t *key, uint32_t keylen, uint8_t *out)
+-int dwc_dh_modpow (void *num, uint32_t num_len, void *exp, uint32_t exp_len, void *mod, uint32_t mod_len, void *out)
int dwc_dh_pk (uint8_t nd, uint8_t *exp, uint8_t *pkd, uint8_t *hash)
 Computes PKD or PKH, and SHA-256(PKd || Nd).
int dwc_dh_derive_keys (uint8_t nd, uint8_t *pkh, uint8_t *pkd, uint8_t *exp, int is_host, char *dd, uint8_t *ck, uint8_t *kdk)
 Computes the DHKEY, and VD.
+-

Function Documentation

+- +-
+-
+- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
int dwc_dh_pk (uint8_t  nd,
uint8_t *  exp,
uint8_t *  pkd,
uint8_t *  hash 
)
+-
+-
+- +-

+-Computes PKD or PKH, and SHA-256(PKd || Nd). +-

+-PK = g^exp mod p.

+-Input: Nd = Number of digits on the device.

+-Output: exp = A 32-byte buffer to be filled with a randomly generated number. used as either A or B. pk = A 384-byte buffer to be filled with the PKH or PKD. hash = A 32-byte buffer to be filled with SHA-256(PK || ND). +-

+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
int dwc_dh_derive_keys (uint8_t  nd,
uint8_t *  pkh,
uint8_t *  pkd,
uint8_t *  exp,
int  is_host,
char *  dd,
uint8_t *  ck,
uint8_t *  kdk 
)
+-
+-
+- +-

+-Computes the DHKEY, and VD. +-

+-If called from host, then it will comput DHKEY=PKD^exp % p. If called from device, then it will comput DHKEY=PKH^exp % p.

+-Input: pkd = The PKD value. pkh = The PKH value. exp = The A value (if device) or B value (if host) generated in dwc_wudev_dh_pk. is_host = Set to non zero if a WUSB host is calling this function.

+-Output:

+-dd = A pointer to an buffer to be set to the displayed digits string to be shown to the user. This buffer should be at 5 bytes long to hold 4 digits plus a null termination character. This buffer can be used directly for display. ck = A 16-byte buffer to be filled with the CK. kdk = A 32-byte buffer to be filled with the KDK. +-

+-

+-

Generated on Tue May 5 02:22:50 2009 for Synopsys DWC Portability and Common Library for UWB by  +- +-doxygen 1.4.7
+- +- +Index: linux-3.2.46/drivers/usb/host/dwc_common_port/doc/html/dwc__list_8h.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_common_port/doc/html/dwc__list_8h.html 2013-07-26 19:31:19.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,1844 +0,0 @@ +- +- +-Synopsys DWC Portability and Common Library for UWB: dwc_list.h File Reference +- +- +- +- +-
+-
+-
+-
+-
+-dwc_common_port
+-

dwc_list.h File Reference

Detailed Description

+-This file defines linked list operations. +-

+-It is derived from BSD with only the MACRO names being prefixed with DWC_. This is because a few of these names conflict with those on Linux. For documentation on use, see the inline comments in the source code. The original license for this source code applies and is preserved in the dwc_list.h source file. +-

+- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-

Data Structures

struct  dwc_list_link

Defines

#define DWC_LIST_INIT(link)
+-#define DWC_LIST_FIRST(link)   ((link)->next)
+-#define DWC_LIST_LAST(link)   ((link)->prev)
+-#define DWC_LIST_END(link)   (link)
+-#define DWC_LIST_NEXT(link)   ((link)->next)
+-#define DWC_LIST_PREV(link)   ((link)->prev)
+-#define DWC_LIST_EMPTY(link)   (DWC_LIST_FIRST(link) == DWC_LIST_END(link))
#define DWC_LIST_ENTRY(link, type, field)
#define DWC_LIST_INSERT_HEAD(list, link)
#define DWC_LIST_INSERT_TAIL(list, link)
#define DWC_LIST_REMOVE(link)
#define DWC_LIST_REMOVE_INIT(link)
#define DWC_LIST_MOVE_HEAD(list, link)
#define DWC_LIST_MOVE_TAIL(list, link)
#define DWC_LIST_FOREACH(var, list)
#define DWC_LIST_FOREACH_SAFE(var, var2, list)
#define DWC_LIST_FOREACH_REVERSE(var, list)
#define DWC_SLIST_HEAD(name, type)
+-#define DWC_SLIST_HEAD_INITIALIZER(head)   { NULL }
#define DWC_SLIST_ENTRY(type)
+-#define DWC_SLIST_FIRST(head)   ((head)->slh_first)
+-#define DWC_SLIST_END(head)   NULL
+-#define DWC_SLIST_EMPTY(head)   (SLIST_FIRST(head) == SLIST_END(head))
+-#define DWC_SLIST_NEXT(elm, field)   ((elm)->field.sle_next)
#define DWC_SLIST_FOREACH(var, head, field)
#define DWC_SLIST_FOREACH_PREVPTR(var, varp, head, field)
#define DWC_SLIST_INIT(head)
#define DWC_SLIST_INSERT_AFTER(slistelm, elm, field)
#define DWC_SLIST_INSERT_HEAD(head, elm, field)
#define DWC_SLIST_REMOVE_NEXT(head, elm, field)
#define DWC_SLIST_REMOVE_HEAD(head, field)
#define DWC_SLIST_REMOVE(head, elm, type, field)
#define DWC_SIMPLEQ_HEAD(name, type)
+-#define DWC_SIMPLEQ_HEAD_INITIALIZER(head)   { NULL, &(head).sqh_first }
#define DWC_SIMPLEQ_ENTRY(type)
+-#define DWC_SIMPLEQ_FIRST(head)   ((head)->sqh_first)
+-#define DWC_SIMPLEQ_END(head)   NULL
+-#define DWC_SIMPLEQ_EMPTY(head)   (SIMPLEQ_FIRST(head) == SIMPLEQ_END(head))
+-#define DWC_SIMPLEQ_NEXT(elm, field)   ((elm)->field.sqe_next)
#define DWC_SIMPLEQ_FOREACH(var, head, field)
#define DWC_SIMPLEQ_INIT(head)
#define DWC_SIMPLEQ_INSERT_HEAD(head, elm, field)
#define DWC_SIMPLEQ_INSERT_TAIL(head, elm, field)
#define DWC_SIMPLEQ_INSERT_AFTER(head, listelm, elm, field)
#define DWC_SIMPLEQ_REMOVE_HEAD(head, field)
#define DWC_TAILQ_HEAD(name, type)
+-#define DWC_TAILQ_HEAD_INITIALIZER(head)   { NULL, &(head).tqh_first }
#define DWC_TAILQ_ENTRY(type)
+-#define DWC_TAILQ_FIRST(head)   ((head)->tqh_first)
+-#define DWC_TAILQ_END(head)   NULL
+-#define DWC_TAILQ_NEXT(elm, field)   ((elm)->field.tqe_next)
+-#define DWC_TAILQ_LAST(head, headname)   (*(((struct headname *)((head)->tqh_last))->tqh_last))
+-#define DWC_TAILQ_PREV(elm, headname, field)   (*(((struct headname *)((elm)->field.tqe_prev))->tqh_last))
+-#define DWC_TAILQ_EMPTY(head)   (TAILQ_FIRST(head) == TAILQ_END(head))
#define DWC_TAILQ_FOREACH(var, head, field)
#define DWC_TAILQ_FOREACH_REVERSE(var, head, headname, field)
#define DWC_TAILQ_INIT(head)
#define DWC_TAILQ_INSERT_HEAD(head, elm, field)
#define DWC_TAILQ_INSERT_TAIL(head, elm, field)
#define DWC_TAILQ_INSERT_AFTER(head, listelm, elm, field)
#define DWC_TAILQ_INSERT_BEFORE(listelm, elm, field)
#define DWC_TAILQ_REMOVE(head, elm, field)
#define DWC_TAILQ_REPLACE(head, elm, elm2, field)
#define DWC_CIRCLEQ_HEAD(name, type)
+-#define DWC_CIRCLEQ_HEAD_INITIALIZER(head)   { DWC_CIRCLEQ_END(&head), DWC_CIRCLEQ_END(&head) }
#define DWC_CIRCLEQ_ENTRY(type)
+-#define DWC_CIRCLEQ_FIRST(head)   ((head)->cqh_first)
+-#define DWC_CIRCLEQ_LAST(head)   ((head)->cqh_last)
+-#define DWC_CIRCLEQ_END(head)   ((void *)(head))
+-#define DWC_CIRCLEQ_NEXT(elm, field)   ((elm)->field.cqe_next)
+-#define DWC_CIRCLEQ_PREV(elm, field)   ((elm)->field.cqe_prev)
+-#define DWC_CIRCLEQ_EMPTY(head)   (DWC_CIRCLEQ_FIRST(head) == DWC_CIRCLEQ_END(head))
+-#define DWC_CIRCLEQ_EMPTY_ENTRY(elm, field)   (((elm)->field.cqe_next == NULL) && ((elm)->field.cqe_prev == NULL))
#define DWC_CIRCLEQ_FOREACH(var, head, field)
#define DWC_CIRCLEQ_FOREACH_SAFE(var, var2, head, field)
#define DWC_CIRCLEQ_FOREACH_REVERSE(var, head, field)
#define DWC_CIRCLEQ_INIT(head)
#define DWC_CIRCLEQ_INIT_ENTRY(elm, field)
#define DWC_CIRCLEQ_INSERT_AFTER(head, listelm, elm, field)
#define DWC_CIRCLEQ_INSERT_BEFORE(head, listelm, elm, field)
#define DWC_CIRCLEQ_INSERT_HEAD(head, elm, field)
#define DWC_CIRCLEQ_INSERT_TAIL(head, elm, field)
#define DWC_CIRCLEQ_REMOVE(head, elm, field)
#define DWC_CIRCLEQ_REMOVE_INIT(head, elm, field)
#define DWC_CIRCLEQ_REPLACE(head, elm, elm2, field)

Typedefs

+-typedef dwc_list_link dwc_list_link_t
+-

Define Documentation

+- +-
+-
+- +- +- +- +- +- +- +- +- +-
#define DWC_LIST_INIT (link   ) 
+-
+-
+- +-

+-Value:

do{             \
+-        (link)->next = (link);          \
+-        (link)->prev = (link);          \
+-} while(0)
+-
+-
+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
#define DWC_LIST_ENTRY (link,
type,
field   ) 
+-
+-
+- +-

+-Value:

(type *)                \
+-        ((uint8_t *)(link) - (size_t)(&((type *)0)->field))
+-
+-
+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +- +- +- +-
#define DWC_LIST_INSERT_HEAD (list,
link   ) 
+-
+-
+- +-

+-Value:

do {                    \
+-        (link)->next = (list)->next;                            \
+-        (link)->prev = (list);                                  \
+-        (list)->next->prev = link;                              \
+-        (list)->next = link;                                    \
+-} while(0)
+-
+-
+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +- +- +- +-
#define DWC_LIST_INSERT_TAIL (list,
link   ) 
+-
+-
+- +-

+-Value:

do {                    \
+-        (link)->next = list;                                    \
+-        (link)->prev = (list)->prev;                            \
+-        (list)->prev->next = link;                              \
+-        (list)->prev = link;                                    \
+-} while(0)
+-
+-
+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +-
#define DWC_LIST_REMOVE (link   ) 
+-
+-
+- +-

+-Value:

do {                            \
+-        (link)->next->prev = (link)->prev;                      \
+-        (link)->prev->next = (link)->next;                      \
+-} while(0)
+-
+-
+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +-
#define DWC_LIST_REMOVE_INIT (link   ) 
+-
+-
+- +-

+-Value:

do {                            \
+-        DWC_LIST_REMOVE(link);                                  \
+-        DWC_LIST_INIT(link);                                    \
+-} while(0)
+-
+-
+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +- +- +- +-
#define DWC_LIST_MOVE_HEAD (list,
link   ) 
+-
+-
+- +-

+-Value:

do {                    \
+-        DWC_LIST_REMOVE(link);                                  \
+-        DWC_LIST_INSERT_HEAD(list, link);                       \
+-} while(0)
+-
+-
+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +- +- +- +-
#define DWC_LIST_MOVE_TAIL (list,
link   ) 
+-
+-
+- +-

+-Value:

do {                    \
+-        DWC_LIST_REMOVE(link);                                  \
+-        DWC_LIST_INSERT_TAIL(list, link);                       \
+-} while(0)
+-
+-
+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +- +- +- +-
#define DWC_LIST_FOREACH (var,
list   ) 
+-
+-
+- +-

+-Value:

for((var) = DWC_LIST_FIRST(list);                       \
+-            (var) != DWC_LIST_END(list);                        \
+-            (var) = DWC_LIST_NEXT(var))
+-
+-
+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
#define DWC_LIST_FOREACH_SAFE (var,
var2,
list   ) 
+-
+-
+- +-

+-Value:

for((var) = DWC_LIST_FIRST(list), var2 = DWC_LIST_NEXT(var);    \
+-            (var) != DWC_LIST_END(list);                        \
+-            (var) = (var2), var2 = DWC_LIST_NEXT(var2))
+-
+-
+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +- +- +- +-
#define DWC_LIST_FOREACH_REVERSE (var,
list   ) 
+-
+-
+- +-

+-Value:

for((var) = DWC_LIST_LAST(list);                        \
+-            (var) != DWC_LIST_END(list);                        \
+-            (var) = DWC_LIST_PREV(var))
+-
+-
+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +- +- +- +-
#define DWC_SLIST_HEAD (name,
type   ) 
+-
+-
+- +-

+-Value:

struct name {                                                           \
+-        struct type *slh_first; /* first element */                     \
+-}
+-
+-
+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +-
#define DWC_SLIST_ENTRY (type   ) 
+-
+-
+- +-

+-Value:

struct {                                                                \
+-        struct type *sle_next;  /* next element */                      \
+-}
+-
+-
+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
#define DWC_SLIST_FOREACH (var,
head,
field   ) 
+-
+-
+- +-

+-Value:

for((var) = SLIST_FIRST(head);                                  \
+-            (var) != SLIST_END(head);                                   \
+-            (var) = SLIST_NEXT(var, field))
+-
+-
+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
#define DWC_SLIST_FOREACH_PREVPTR (var,
varp,
head,
field   ) 
+-
+-
+- +-

+-Value:

for ((varp) = &SLIST_FIRST((head));                             \
+-            ((var) = *(varp)) != SLIST_END(head);                       \
+-            (varp) = &SLIST_NEXT((var), field))
+-
+-
+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +-
#define DWC_SLIST_INIT (head   ) 
+-
+-
+- +-

+-Value:

{                                               \
+-        SLIST_FIRST(head) = SLIST_END(head);                            \
+-}
+-
+-
+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
#define DWC_SLIST_INSERT_AFTER (slistelm,
elm,
field   ) 
+-
+-
+- +-

+-Value:

do {                    \
+-        (elm)->field.sle_next = (slistelm)->field.sle_next;             \
+-        (slistelm)->field.sle_next = (elm);                             \
+-} while (0)
+-
+-
+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
#define DWC_SLIST_INSERT_HEAD (head,
elm,
field   ) 
+-
+-
+- +-

+-Value:

do {                    \
+-        (elm)->field.sle_next = (head)->slh_first;                      \
+-        (head)->slh_first = (elm);                                      \
+-} while (0)
+-
+-
+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
#define DWC_SLIST_REMOVE_NEXT (head,
elm,
field   ) 
+-
+-
+- +-

+-Value:

do {                    \
+-        (elm)->field.sle_next = (elm)->field.sle_next->field.sle_next;  \
+-} while (0)
+-
+-
+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +- +- +- +-
#define DWC_SLIST_REMOVE_HEAD (head,
field   ) 
+-
+-
+- +-

+-Value:

do {                            \
+-        (head)->slh_first = (head)->slh_first->field.sle_next;          \
+-} while (0)
+-
+-
+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
#define DWC_SLIST_REMOVE (head,
elm,
type,
field   ) 
+-
+-
+- +-

+-Value:

do {                    \
+-        if ((head)->slh_first == (elm)) {                               \
+-                SLIST_REMOVE_HEAD((head), field);                       \
+-        }                                                               \
+-        else {                                                          \
+-                struct type *curelm = (head)->slh_first;                \
+-                while( curelm->field.sle_next != (elm) )                \
+-                        curelm = curelm->field.sle_next;                \
+-                curelm->field.sle_next =                                \
+-                    curelm->field.sle_next->field.sle_next;             \
+-        }                                                               \
+-} while (0)
+-
+-
+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +- +- +- +-
#define DWC_SIMPLEQ_HEAD (name,
type   ) 
+-
+-
+- +-

+-Value:

struct name {                                                           \
+-        struct type *sqh_first; /* first element */                     \
+-        struct type **sqh_last; /* addr of last next element */         \
+-}
+-
+-
+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +-
#define DWC_SIMPLEQ_ENTRY (type   ) 
+-
+-
+- +-

+-Value:

struct {                                                                \
+-        struct type *sqe_next;  /* next element */                      \
+-}
+-
+-
+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
#define DWC_SIMPLEQ_FOREACH (var,
head,
field   ) 
+-
+-
+- +-

+-Value:

for((var) = SIMPLEQ_FIRST(head);                                \
+-            (var) != SIMPLEQ_END(head);                                 \
+-            (var) = SIMPLEQ_NEXT(var, field))
+-
+-
+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +-
#define DWC_SIMPLEQ_INIT (head   ) 
+-
+-
+- +-

+-Value:

do {                                            \
+-        (head)->sqh_first = NULL;                                       \
+-        (head)->sqh_last = &(head)->sqh_first;                          \
+-} while (0)
+-
+-
+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
#define DWC_SIMPLEQ_INSERT_HEAD (head,
elm,
field   ) 
+-
+-
+- +-

+-Value:

do {                    \
+-        if (((elm)->field.sqe_next = (head)->sqh_first) == NULL)        \
+-                (head)->sqh_last = &(elm)->field.sqe_next;              \
+-        (head)->sqh_first = (elm);                                      \
+-} while (0)
+-
+-
+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
#define DWC_SIMPLEQ_INSERT_TAIL (head,
elm,
field   ) 
+-
+-
+- +-

+-Value:

do {                    \
+-        (elm)->field.sqe_next = NULL;                                   \
+-        *(head)->sqh_last = (elm);                                      \
+-        (head)->sqh_last = &(elm)->field.sqe_next;                      \
+-} while (0)
+-
+-
+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
#define DWC_SIMPLEQ_INSERT_AFTER (head,
listelm,
elm,
field   ) 
+-
+-
+- +-

+-Value:

do {            \
+-        if (((elm)->field.sqe_next = (listelm)->field.sqe_next) == NULL)\
+-                (head)->sqh_last = &(elm)->field.sqe_next;              \
+-        (listelm)->field.sqe_next = (elm);                              \
+-} while (0)
+-
+-
+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +- +- +- +-
#define DWC_SIMPLEQ_REMOVE_HEAD (head,
field   ) 
+-
+-
+- +-

+-Value:

do {                    \
+-        if (((head)->sqh_first = (head)->sqh_first->field.sqe_next) == NULL) \
+-                (head)->sqh_last = &(head)->sqh_first;                  \
+-} while (0)
+-
+-
+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +- +- +- +-
#define DWC_TAILQ_HEAD (name,
type   ) 
+-
+-
+- +-

+-Value:

struct name {                                                           \
+-        struct type *tqh_first; /* first element */                     \
+-        struct type **tqh_last; /* addr of last next element */         \
+-}
+-
+-
+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +-
#define DWC_TAILQ_ENTRY (type   ) 
+-
+-
+- +-

+-Value:

struct {                                                                \
+-        struct type *tqe_next;  /* next element */                      \
+-        struct type **tqe_prev; /* address of previous next element */  \
+-}
+-
+-
+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
#define DWC_TAILQ_FOREACH (var,
head,
field   ) 
+-
+-
+- +-

+-Value:

for((var) = TAILQ_FIRST(head);                                  \
+-            (var) != TAILQ_END(head);                                   \
+-            (var) = TAILQ_NEXT(var, field))
+-
+-
+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
#define DWC_TAILQ_FOREACH_REVERSE (var,
head,
headname,
field   ) 
+-
+-
+- +-

+-Value:

for((var) = TAILQ_LAST(head, headname);                         \
+-            (var) != TAILQ_END(head);                                   \
+-            (var) = TAILQ_PREV(var, headname, field))
+-
+-
+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +-
#define DWC_TAILQ_INIT (head   ) 
+-
+-
+- +-

+-Value:

do {                                            \
+-        (head)->tqh_first = NULL;                                       \
+-        (head)->tqh_last = &(head)->tqh_first;                          \
+-} while (0)
+-
+-
+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
#define DWC_TAILQ_INSERT_HEAD (head,
elm,
field   ) 
+-
+-
+- +-

+-Value:

do {                    \
+-        if (((elm)->field.tqe_next = (head)->tqh_first) != NULL)        \
+-                (head)->tqh_first->field.tqe_prev =                     \
+-                    &(elm)->field.tqe_next;                             \
+-        else                                                            \
+-                (head)->tqh_last = &(elm)->field.tqe_next;              \
+-        (head)->tqh_first = (elm);                                      \
+-        (elm)->field.tqe_prev = &(head)->tqh_first;                     \
+-} while (0)
+-
+-
+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
#define DWC_TAILQ_INSERT_TAIL (head,
elm,
field   ) 
+-
+-
+- +-

+-Value:

do {                    \
+-        (elm)->field.tqe_next = NULL;                                   \
+-        (elm)->field.tqe_prev = (head)->tqh_last;                       \
+-        *(head)->tqh_last = (elm);                                      \
+-        (head)->tqh_last = &(elm)->field.tqe_next;                      \
+-} while (0)
+-
+-
+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
#define DWC_TAILQ_INSERT_AFTER (head,
listelm,
elm,
field   ) 
+-
+-
+- +-

+-Value:

do {            \
+-        if (((elm)->field.tqe_next = (listelm)->field.tqe_next) != NULL)\
+-                (elm)->field.tqe_next->field.tqe_prev =                 \
+-                    &(elm)->field.tqe_next;                             \
+-        else                                                            \
+-                (head)->tqh_last = &(elm)->field.tqe_next;              \
+-        (listelm)->field.tqe_next = (elm);                              \
+-        (elm)->field.tqe_prev = &(listelm)->field.tqe_next;             \
+-} while (0)
+-
+-
+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
#define DWC_TAILQ_INSERT_BEFORE (listelm,
elm,
field   ) 
+-
+-
+- +-

+-Value:

do {                    \
+-        (elm)->field.tqe_prev = (listelm)->field.tqe_prev;              \
+-        (elm)->field.tqe_next = (listelm);                              \
+-        *(listelm)->field.tqe_prev = (elm);                             \
+-        (listelm)->field.tqe_prev = &(elm)->field.tqe_next;             \
+-} while (0)
+-
+-
+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
#define DWC_TAILQ_REMOVE (head,
elm,
field   ) 
+-
+-
+- +-

+-Value:

do {                            \
+-        if (((elm)->field.tqe_next) != NULL)                            \
+-                (elm)->field.tqe_next->field.tqe_prev =                 \
+-                    (elm)->field.tqe_prev;                              \
+-        else                                                            \
+-                (head)->tqh_last = (elm)->field.tqe_prev;               \
+-        *(elm)->field.tqe_prev = (elm)->field.tqe_next;                 \
+-} while (0)
+-
+-
+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
#define DWC_TAILQ_REPLACE (head,
elm,
elm2,
field   ) 
+-
+-
+- +-

+-Value:

do {                    \
+-        if (((elm2)->field.tqe_next = (elm)->field.tqe_next) != NULL)   \
+-                (elm2)->field.tqe_next->field.tqe_prev =                \
+-                    &(elm2)->field.tqe_next;                            \
+-        else                                                            \
+-                (head)->tqh_last = &(elm2)->field.tqe_next;             \
+-        (elm2)->field.tqe_prev = (elm)->field.tqe_prev;                 \
+-        *(elm2)->field.tqe_prev = (elm2);                               \
+-} while (0)
+-
+-
+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +- +- +- +-
#define DWC_CIRCLEQ_HEAD (name,
type   ) 
+-
+-
+- +-

+-Value:

struct name {                                                           \
+-        struct type *cqh_first;         /* first element */             \
+-        struct type *cqh_last;          /* last element */              \
+-}
+-
+-
+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +-
#define DWC_CIRCLEQ_ENTRY (type   ) 
+-
+-
+- +-

+-Value:

struct {                                                                \
+-        struct type *cqe_next;          /* next element */              \
+-        struct type *cqe_prev;          /* previous element */          \
+-}
+-
+-
+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
#define DWC_CIRCLEQ_FOREACH (var,
head,
field   ) 
+-
+-
+- +-

+-Value:

for((var) = DWC_CIRCLEQ_FIRST(head);                            \
+-            (var) != DWC_CIRCLEQ_END(head);                                     \
+-            (var) = DWC_CIRCLEQ_NEXT(var, field))
+-
+-
+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
#define DWC_CIRCLEQ_FOREACH_SAFE (var,
var2,
head,
field   ) 
+-
+-
+- +-

+-Value:

for((var) = DWC_CIRCLEQ_FIRST(head), var2 = DWC_CIRCLEQ_NEXT(var, field);                               \
+-            (var) != DWC_CIRCLEQ_END(head);                                     \
+-            (var) = var2, var2 = DWC_CIRCLEQ_NEXT(var, field))
+-
+-
+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
#define DWC_CIRCLEQ_FOREACH_REVERSE (var,
head,
field   ) 
+-
+-
+- +-

+-Value:

for((var) = DWC_CIRCLEQ_LAST(head);                                     \
+-            (var) != DWC_CIRCLEQ_END(head);                                     \
+-            (var) = DWC_CIRCLEQ_PREV(var, field))
+-
+-
+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +-
#define DWC_CIRCLEQ_INIT (head   ) 
+-
+-
+- +-

+-Value:

do {                                            \
+-        (head)->cqh_first = DWC_CIRCLEQ_END(head);                              \
+-        (head)->cqh_last = DWC_CIRCLEQ_END(head);                               \
+-} while (0)
+-
+-
+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +- +- +- +-
#define DWC_CIRCLEQ_INIT_ENTRY (elm,
field   ) 
+-
+-
+- +-

+-Value:

do { \
+-        (elm)->field.cqe_next = NULL; \
+-        (elm)->field.cqe_prev = NULL; \
+-} while (0)
+-
+-
+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
#define DWC_CIRCLEQ_INSERT_AFTER (head,
listelm,
elm,
field   ) 
+-
+-
+- +-

+-Value:

do {            \
+-        (elm)->field.cqe_next = (listelm)->field.cqe_next;              \
+-        (elm)->field.cqe_prev = (listelm);                              \
+-        if ((listelm)->field.cqe_next == DWC_CIRCLEQ_END(head))         \
+-                (head)->cqh_last = (elm);                               \
+-        else                                                            \
+-                (listelm)->field.cqe_next->field.cqe_prev = (elm);      \
+-        (listelm)->field.cqe_next = (elm);                              \
+-} while (0)
+-
+-
+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
#define DWC_CIRCLEQ_INSERT_BEFORE (head,
listelm,
elm,
field   ) 
+-
+-
+- +-

+-Value:

do {            \
+-        (elm)->field.cqe_next = (listelm);                              \
+-        (elm)->field.cqe_prev = (listelm)->field.cqe_prev;              \
+-        if ((listelm)->field.cqe_prev == DWC_CIRCLEQ_END(head))         \
+-                (head)->cqh_first = (elm);                              \
+-        else                                                            \
+-                (listelm)->field.cqe_prev->field.cqe_next = (elm);      \
+-        (listelm)->field.cqe_prev = (elm);                              \
+-} while (0)
+-
+-
+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
#define DWC_CIRCLEQ_INSERT_HEAD (head,
elm,
field   ) 
+-
+-
+- +-

+-Value:

do {                    \
+-        (elm)->field.cqe_next = (head)->cqh_first;                      \
+-        (elm)->field.cqe_prev = DWC_CIRCLEQ_END(head);                  \
+-        if ((head)->cqh_last == DWC_CIRCLEQ_END(head))                  \
+-                (head)->cqh_last = (elm);                               \
+-        else                                                            \
+-                (head)->cqh_first->field.cqe_prev = (elm);              \
+-        (head)->cqh_first = (elm);                                      \
+-} while (0)
+-
+-
+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
#define DWC_CIRCLEQ_INSERT_TAIL (head,
elm,
field   ) 
+-
+-
+- +-

+-Value:

do {                    \
+-        (elm)->field.cqe_next = DWC_CIRCLEQ_END(head);                  \
+-        (elm)->field.cqe_prev = (head)->cqh_last;                       \
+-        if ((head)->cqh_first == DWC_CIRCLEQ_END(head))                 \
+-                (head)->cqh_first = (elm);                              \
+-        else                                                            \
+-                (head)->cqh_last->field.cqe_next = (elm);               \
+-        (head)->cqh_last = (elm);                                       \
+-} while (0)
+-
+-
+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
#define DWC_CIRCLEQ_REMOVE (head,
elm,
field   ) 
+-
+-
+- +-

+-Value:

do {                            \
+-        if ((elm)->field.cqe_next == DWC_CIRCLEQ_END(head))                     \
+-                (head)->cqh_last = (elm)->field.cqe_prev;               \
+-        else                                                            \
+-                (elm)->field.cqe_next->field.cqe_prev =                 \
+-                    (elm)->field.cqe_prev;                              \
+-        if ((elm)->field.cqe_prev == DWC_CIRCLEQ_END(head))                     \
+-                (head)->cqh_first = (elm)->field.cqe_next;              \
+-        else                                                            \
+-                (elm)->field.cqe_prev->field.cqe_next =                 \
+-                    (elm)->field.cqe_next;                              \
+-} while (0)
+-
+-
+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
#define DWC_CIRCLEQ_REMOVE_INIT (head,
elm,
field   ) 
+-
+-
+- +-

+-Value:

do { \
+-        DWC_CIRCLEQ_REMOVE(head, elm, field); \
+-        DWC_CIRCLEQ_INIT_ENTRY(elm, field); \
+-} while (0)
+-
+-
+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
#define DWC_CIRCLEQ_REPLACE (head,
elm,
elm2,
field   ) 
+-
+-
+- +-

+-Value:

do {                    \
+-        if (((elm2)->field.cqe_next = (elm)->field.cqe_next) ==         \
+-            DWC_CIRCLEQ_END(head))                                              \
+-                (head).cqh_last = (elm2);                               \
+-        else                                                            \
+-                (elm2)->field.cqe_next->field.cqe_prev = (elm2);        \
+-        if (((elm2)->field.cqe_prev = (elm)->field.cqe_prev) ==         \
+-            DWC_CIRCLEQ_END(head))                                              \
+-                (head).cqh_first = (elm2);                              \
+-        else                                                            \
+-                (elm2)->field.cqe_prev->field.cqe_next = (elm2);        \
+-} while (0)
+-
+-
+-

+-

Generated on Tue May 5 02:22:50 2009 for Synopsys DWC Portability and Common Library for UWB by  +- +-doxygen 1.4.7
+- +- +Index: linux-3.2.46/drivers/usb/host/dwc_common_port/doc/html/dwc__modpow_8h.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_common_port/doc/html/dwc__modpow_8h.html 2013-07-26 19:31:19.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,48 +0,0 @@ +- +- +-Synopsys DWC Portability and Common Library for UWB: dwc_modpow.h File Reference +- +- +- +- +-
+-
+-
+-
+-
+-dwc_common_port
+-

dwc_modpow.h File Reference

Detailed Description

+-This file defines the module exponentiation function which is only used internally by the DWC UWB modules for calculation of PKs during numeric association. +-

+-The routine is taken from the PUTTY, an open source terminal emulator. The PUTTY License is preserved in the dwc_modpow.c file. +-

+- +- +- +- +- +- +- +- +- +- +- +- +-

Typedefs

+-typedef uint32_t BignumInt
+-typedef uint64_t BignumDblInt
+-typedef BignumInt * Bignum

Functions

+-Bignum dwc_modpow (Bignum base_in, Bignum exp, Bignum mod)
+-

Generated on Tue May 5 02:22:50 2009 for Synopsys DWC Portability and Common Library for UWB by  +- +-doxygen 1.4.7
+- +- +Index: linux-3.2.46/drivers/usb/host/dwc_common_port/doc/html/dwc__notifier_8h.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_common_port/doc/html/dwc__notifier_8h.html 2013-07-26 19:31:19.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,306 +0,0 @@ +- +- +-Synopsys DWC Portability and Common Library for UWB: dwc_notifier.h File Reference +- +- +- +- +-
+-
+-
+-
+-
+-dwc_common_port
+-

dwc_notifier.h File Reference

Detailed Description

+-A simple implementation of the Observer pattern. +-

+-Any "module" can register as an observer or notifier. The notion of "module" is abstract and can mean anything used to identify either an observer or notifier. Usually it will be a pointer to a data structure which contains some state, ie an object.

+-Before any notifiers can be added, the global notification manager must be brought up with dwc_alloc_notification_manager(). dwc_free_notification_manager() will bring it down and free all resources. These would typically be called upon module load and unload. The notification manager is a single global instance that handles all registered observable modules and observers so this should be done only once.

+-A module can be observable by using Notifications to publicize some general information about it's state or operation. It does not care who listens, or even if anyone listens, or what they do with the information. The observable modules do not need to know any information about it's observers or their interface, or their state or data.

+-Any module can register to emit Notifications. It should publish a list of notifications that it can emit and their behavior, such as when they will get triggered, and what information will be provided to the observer. Then it should register itself as an observable module. See dwc_register_notifier().

+-Any module can observe any observable, registered module, provided it has a handle to the other module and knows what notifications to observe. See dwc_add_observer().

+-A function of type dwc_notifier_callback_t is called whenever a notification is triggered with one or more observers observing it. This function is called in it's own process so it may sleep or block if needed. It is guaranteed to be called sometime after the notification has occurred and will be called once per each time the notification is triggered. It will NOT be called in the same process context used to trigger the notification.

+-Limitiations

+-Keep in mind that Notifications that can be triggered in rapid sucession may schedule too many processes too handle. Be aware of this limitation when designing to use notifications, and only add notifications for appropriate observable information.

+-Also Notification callbacks are not synchronous. If you need to synchronize the behavior between module/observer you must use other means. And perhaps that will mean Notifications are not the proper solution. +-

+- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-

Typedefs

+-typedef dwc_notifier dwc_notifier_t
typedef void(*) dwc_notifier_callback_t (void *object, char *notification, void *observer, void *notification_data, void *user_data)
 The callback function must be of this type.

Functions

void dwc_alloc_notification_manager (void)
 Brings up the notification manager.
void dwc_free_notification_manager (void)
 Brings down the notification manager.
dwc_notifier_t * dwc_register_notifier (void *object)
 This function register an observable module.
void dwc_unregister_notifier (dwc_notifier_t *notifier)
 This function unregister an observable module.
int dwc_add_observer (void *observer, void *object, char *notification, dwc_notifier_callback_t callback, void *user_data)
 Add a module as an observer to the observable module.
int dwc_remove_observer (void *observer)
 Removes the specified observer from all notifications that it is currently observing.
void dwc_notify (dwc_notifier_t *notifier, char *notification, void *notification_data)
 This function triggers a Notification.
+-

Typedef Documentation

+- +-
+-
+- +- +- +- +-
typedef void(*) dwc_notifier_callback_t(void *object, char *notification, void *observer, void *notification_data, void *user_data)
+-
+-
+- +-

+-The callback function must be of this type. +-

+-

Parameters:
+- +- +- +- +- +- +-
object This is the object that is being observed.
notification This is the notification that was triggered.
observer This is the observer
notification_data This is notification-specific data that the notifier has included in this notification. The value of this should be published in the documentation of the observable module with the notifications.
user_data This is any custom data that the observer provided when adding itself as an observer to the notification.
+-
+- +-
+-

+-

Function Documentation

+- +-
+-
+- +- +- +- +- +- +- +- +- +-
void dwc_alloc_notification_manager (void   ) 
+-
+-
+- +-

+-Brings up the notification manager. +-

+- +-

+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +-
void dwc_free_notification_manager (void   ) 
+-
+-
+- +-

+-Brings down the notification manager. +-

+- +-

+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +-
dwc_notifier_t* dwc_register_notifier (void *  object  ) 
+-
+-
+- +-

+-This function register an observable module. +-

+-A dwc_notifier_t object is returned to the observable module. This is an opaque object that is used by the observable module to trigger notifications. This object should only be accessible to functions that are authorized to trigger notifications for this module. Observers do not need this object. +-

+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +-
void dwc_unregister_notifier (dwc_notifier_t *  notifier  ) 
+-
+-
+- +-

+-This function unregister an observable module. +-

+-All observers have to be removed prior to unregistration. +-

+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
int dwc_add_observer (void *  observer,
void *  object,
char *  notification,
dwc_notifier_callback_t  callback,
void *  user_data 
)
+-
+-
+- +-

+-Add a module as an observer to the observable module. +-

+-The observable module needs to have previously registered with the notification manager.

+-

Parameters:
+- +- +- +- +- +- +-
observer The observer module
object The module to observe
notification The notification to observe
callback The callback function to call
user_data Any additional user data to pass into the callback function
+-
+- +-
+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +-
int dwc_remove_observer (void *  observer  ) 
+-
+-
+- +-

+-Removes the specified observer from all notifications that it is currently observing. +-

+- +-

+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
void dwc_notify (dwc_notifier_t *  notifier,
char *  notification,
void *  notification_data 
)
+-
+-
+- +-

+-This function triggers a Notification. +-

+-It should be called by the observable module, or any module or library which the observable module allows to trigger notification on it's behalf. Such as the dwc_cc_t.

+-dwc_notify is a non-blocking function. Callbacks are scheduled called in their own process context for each trigger. Callbacks can be blocking. dwc_notify can be called from interrupt context if needed. +-

+-

+-

Generated on Tue May 5 02:22:50 2009 for Synopsys DWC Portability and Common Library for UWB by  +- +-doxygen 1.4.7
+- +- +Index: linux-3.2.46/drivers/usb/host/dwc_common_port/doc/html/dwc__os_8h.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_common_port/doc/html/dwc__os_8h.html 2013-07-26 19:31:19.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,3090 +0,0 @@ +- +- +-Synopsys DWC Portability and Common Library for UWB: dwc_os.h File Reference +- +- +- +- +-
+-
+-
+-
+-
+-dwc_common_port
+-

dwc_os.h File Reference

Detailed Description

+-DWC portability library, low level os-wrapper functions. +-

+- +-

+- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-

Primitive Types and Values

+-#define YES   1
+-#define NO   0
typedef uint8_t dwc_bool_t
 We define a boolean type for consistency.

Error Codes

+-#define DWC_E_INVALID   1001
+-#define DWC_E_NO_MEMORY   1002
+-#define DWC_E_NO_DEVICE   1003
+-#define DWC_E_NOT_SUPPORTED   1004
+-#define DWC_E_TIMEOUT   1005
+-#define DWC_E_BUSY   1006
+-#define DWC_E_AGAIN   1007
+-#define DWC_E_RESTART   1008
+-#define DWC_E_ABORT   1009
+-#define DWC_E_SHUTDOWN   1010
+-#define DWC_E_NO_DATA   1011
+-#define DWC_E_DISCONNECT   2000
+-#define DWC_E_UNKNOWN   3000
+-#define DWC_E_NO_STREAM_RES   4001
+-#define DWC_E_COMMUNICATION   4002
+-#define DWC_E_OVERFLOW   4003
+-#define DWC_E_PROTOCOL   4004
+-#define DWC_E_IN_PROGRESS   4005
+-#define DWC_E_PIPE   4006
+-#define DWC_E_IO   4007
+-#define DWC_E_NO_SPACE   4008

Tracing/Logging Functions

These function provide the capability to add tracing, debugging, and error messages, as well exceptions as assertions. The WUDEV uses these extensively. These could be logged to the main console, the serial port, an internal buffer, etc. These functions could also be no-op if they are too expensive on your system. By default undefining the DEBUG macro already no-ops some of these functions.

+-#define dwc_in_irq   DWC_IN_IRQ
+-#define dwc_vprintf   DWC_VPRINTF
+-#define dwc_vsnprintf   DWC_VSNPRINTF
+-#define dwc_printf   DWC_PRINTF
+-#define dwc_sprintf   DWC_SPRINTF
+-#define dwc_snprintf   DWC_SNPRINTF
+-#define dwc_exception   DWC_EXCEPTION
#define DWC_DEBUG(_format, _args...)   __DWC_DEBUG("DEBUG:%s:%s: " _format "\n", __func__, dwc_irq(), ## _args)
 Prints out a Debug message.
+-#define dwc_debug   DWC_DEBUG
#define DWC_INFO(_format, _args...)   DWC_PRINTF("INFO:%s: " _format "\n", dwc_irq(), ## _args)
 Prints out an informative message.
+-#define dwc_info   DWC_INFO
#define DWC_WARN(_format, _args...)   __DWC_WARN("WARN:%s:%s:%d: " _format "\n", dwc_irq(), __func__, __LINE__, ## _args)
 Prints out a warning message.
+-#define dwc_warn   DWC_WARN
#define DWC_ERROR(_format, _args...)   __DWC_ERROR("ERROR:%s:%s:%d: " _format "\n", dwc_irq(), __func__, __LINE__, ## _args)
 Prints out an error message.
+-#define dwc_error   DWC_ERROR
+-#define DWC_PROTO_ERROR(_format, _args...)   __DWC_WARN("ERROR:%s:%s:%d: " _format "\n", dwc_irq(), __func__, __LINE__, ## _args)
+-#define dwc_proto_error   DWC_PROTO_ERROR
#define DWC_ASSERT(_expr, _format, _args...)   if (!(_expr)) { DWC_EXCEPTION("%s:%s:%d: " _format "\n", dwc_irq(), __FILE__, __LINE__, ## _args); }
 Prints out a exception error message if the _expr expression fails.
+-#define dwc_assert   DWC_ASSERT
dwc_bool_t DWC_IN_IRQ (void)
 Returns non-zero if in interrupt context.
static char * dwc_irq (void)
 Returns "IRQ" if DWC_IN_IRQ is true.
void DWC_VPRINTF (char *format, va_list args)
 A vprintf() clone.
int DWC_VSNPRINTF (char *str, int size, char *format, va_list args)
 A vsnprintf() clone.
void DWC_PRINTF (char *format,...)
 printf() clone.
int DWC_SPRINTF (char *string, char *format,...)
 sprintf() clone.
int DWC_SNPRINTF (char *string, int size, char *format,...)
 snprintf() clone.
void __DWC_WARN (char *format,...)
 Prints a WARNING message.
void __DWC_ERROR (char *format,...)
 Prints an error message.
void DWC_EXCEPTION (char *format,...)
 Prints an exception error message and takes some user-defined action such as print out a backtrace or trigger a breakpoint.
void __DWC_DEBUG (char *format,...)
 Prints out a debug message.

Byter Ordering

The following functions are for conversions between processor's byte ordering and specific ordering you want.

+-#define dwc_cpu_to_le32   DWC_CPU_TO_LE32
+-#define dwc_cpu_to_be32   DWC_CPU_TO_BE32
+-#define dwc_le32_to_cpu   DWC_LE32_TO_CPU
+-#define dwc_be32_to_cpu   DWC_BE32_TO_CPU
+-#define dwc_cpu_to_le16   DWC_CPU_TO_LE16
+-#define dwc_cpu_to_be16   DWC_CPU_TO_BE16
+-#define dwc_le16_to_cpu   DWC_LE16_TO_CPU
+-#define dwc_be16_to_cpu   DWC_BE16_TO_CPU
uint32_t DWC_CPU_TO_LE32 (void *p)
 Converts 32 bit data in CPU byte ordering to little endian.
uint32_t DWC_CPU_TO_BE32 (void *p)
 Converts 32 bit data in CPU byte orderint to big endian.
uint32_t DWC_LE32_TO_CPU (void *p)
 Converts 32 bit little endian data to CPU byte ordering.
uint32_t DWC_BE32_TO_CPU (void *p)
 Converts 32 bit big endian data to CPU byte ordering.
uint16_t DWC_CPU_TO_LE16 (void *p)
 Converts 16 bit data in CPU byte ordering to little endian.
uint16_t DWC_CPU_TO_BE16 (void *p)
 Converts 16 bit data in CPU byte orderint to big endian.
uint16_t DWC_LE16_TO_CPU (void *p)
 Converts 16 bit little endian data to CPU byte ordering.
uint16_t DWC_BE16_TO_CPU (void *p)
 Converts 16 bit bi endian data to CPU byte ordering.

Register Read/Write

The following five functions should be implemented to read/write registers of 32-bit and 64-bit sizes. All modules use this to read/write register values. The reg value is a pointer to the register calculated from the void *base variable passed into the driver when it is started.

+-#define dwc_read_reg32   DWC_READ_REG32
+-#define dwc_read_reg64   DWC_READ_REG64
+-#define dwc_write_reg32   DWC_WRITE_REG32
+-#define dwc_write_reg64   DWC_WRITE_REG64
+-#define dwc_modify_reg32   DWC_MODIFY_REG32
uint32_t DWC_READ_REG32 (uint32_t volatile *reg)
 Reads the content of a 32-bit register.
uint64_t DWC_READ_REG64 (uint64_t volatile *reg)
 Reads the content of a 64-bit register.
void DWC_WRITE_REG32 (uint32_t volatile *reg, uint32_t value)
 Writes to a 32-bit register.
void DWC_WRITE_REG64 (uint64_t volatile *reg, uint64_t value)
 Writes to a 64-bit register.
void DWC_MODIFY_REG32 (uint32_t volatile *reg, uint32_t clear_mask, uint32_t set_mask)
 Modify bit values in a register.

Crypto Functions

These are the low-level cryptographic functions used by the driver.

+-#define dwc_aes_cbc   DWC_AES_CBC
+-#define dwc_random_bytes   DWC_RANDOM_BYTES
+-#define dwc_sha256   DWC_SHA256
+-#define dwc_hmac_sha256   DWC_HMAC_SHA256
int DWC_AES_CBC (uint8_t *message, uint32_t messagelen, uint8_t *key, uint32_t keylen, uint8_t iv[16], uint8_t *out)
 Perform AES CBC.
void DWC_RANDOM_BYTES (uint8_t *buffer, uint32_t length)
 Fill the provided buffer with random bytes.
int DWC_SHA256 (uint8_t *message, uint32_t len, uint8_t *out)
 Perform the SHA-256 hash function.
int DWC_HMAC_SHA256 (uint8_t *message, uint32_t messagelen, uint8_t *key, uint32_t keylen, uint8_t *out)
 Calculated the HMAC-SHA256.

Memory Allocation

These function provide access to memory allocation. There are only 2 DMA functions and 3 Regular memory functions that need to be implemented. None of the memory debugging routines need to be implemented. The allocation routines all ZERO the contents of the memory.

+-Defining DEBUG_MEMORY turns on memory debugging and statistic gathering. This checks for memory leaks, keeping track of alloc/free pairs. It also keeps track of how much memory the driver is using at any given time.

+-#define DWC_PAGE_SIZE   4096
+-#define DWC_PAGE_OFFSET(addr)   (((uint32_t)addr) & 0xfff)
+-#define DWC_PAGE_ALIGNED(addr)   ((((uint32_t)addr) & 0xfff) == 0)
+-#define DWC_INVALID_DMA_ADDR   0x0
+-#define DWC_ALLOC(_size_)   (dwc_alloc_debug(_size_, __func__, __LINE__))
+-#define DWC_ALLOC_ATOMIC(_size_)   (dwc_alloc_atomic_debug(_size_, __func__, __LINE__))
+-#define DWC_FREE(_addr_)   (dwc_free_debug(_addr_, __func__, __LINE__))
+-#define DWC_DMA_ALLOC(_size_, _dma_)   dwc_dma_alloc_debug(_size_, _dma_, __func__, __LINE__)
+-#define DWC_DMA_FREE(_size_, _virt_, _dma_)   dwc_dma_free_debug(_size_, _virt_, _dma_, __func__, __LINE__)
+-#define dwc_alloc   DWC_ALLOC
+-#define dwc_alloc_atomic   DWC_ALLOC_ATOMIC
+-#define dwc_free   DWC_FREE
+-#define dwc_dma_alloc   DWC_DMA_ALLOC
+-#define dwc_dma_free   DWC_DMA_FREE
+-typedef uint32_t dwc_dma_t
void * __DWC_DMA_ALLOC (uint32_t size, dwc_dma_t *dma_addr)
 Allocates a DMA capable buffer and zeroes its contents.
void __DWC_DMA_FREE (uint32_t size, void *virt_addr, dwc_dma_t dma_addr)
 Frees a previosly allocated buffer.
void * __DWC_ALLOC (uint32_t size)
 Allocates a block of memory and zeroes its contents.
void * __DWC_ALLOC_ATOMIC (uint32_t size)
 Allocates a block of memory and zeroes its contents, in an atomic manner which can be used inside interrupt context.
void __DWC_FREE (void *addr)
 Frees a previously allocated buffer.
+-void * dwc_alloc_debug (uint32_t size, char const *func, int line)
+-void * dwc_alloc_atomic_debug (uint32_t size, char const *func, int line)
+-void dwc_free_debug (void *addr, char const *func, int line)
+-void * dwc_dma_alloc_debug (uint32_t size, dwc_dma_t *dma_addr, char const *func, int line)
+-void dwc_dma_free_debug (uint32_t size, void *virt_addr, dwc_dma_t dma_addr, char const *func, int line)
+-void dwc_memory_debug_start (void)
+-void dwc_memory_debug_stop (void)
+-void dwc_memory_debug_report (void)

Memory and String Processing

+-#define dwc_memset   DWC_MEMSET
+-#define dwc_memcpy   DWC_MEMCPY
+-#define dwc_memmove   DWC_MEMMOVE
+-#define dwc_memcmp   DWC_MEMCMP
+-#define dwc_strcmp   DWC_STRCMP
+-#define dwc_strncmp   DWC_STRNCMP
+-#define dwc_strlen   DWC_STRLEN
+-#define dwc_strcpy   DWC_STRCPY
+-#define dwc_strdup   DWC_STRDUP
+-#define dwc_atoi   DWC_ATOI
+-#define dwc_atoui   DWC_ATOUI
+-#define dwc_utf8_to_utf16le   DWC_UTF8_TO_UTF16LE
void * DWC_MEMSET (void *dest, uint8_t byte, uint32_t size)
 memset() clone
void * DWC_MEMCPY (void *dest, void const *src, uint32_t size)
 memcpy() clone
void * DWC_MEMMOVE (void *dest, void *src, uint32_t size)
 memmove() clone
int DWC_MEMCMP (void *m1, void *m2, uint32_t size)
 memcmp() clone
int DWC_STRCMP (void *s1, void *s2)
 strcmp() clone
int DWC_STRNCMP (void *s1, void *s2, uint32_t size)
 strncmp() clone
int DWC_STRLEN (char const *str)
 strlen() clone, for NULL terminated ASCII strings
char * DWC_STRCPY (char *to, const char *from)
 strcpy() clone, for NULL terminated ASCII strings
char * DWC_STRDUP (char const *str)
 strdup() clone.
int DWC_ATOI (char *str, int32_t *value)
 NOT an atoi() clone.
int DWC_ATOUI (char *str, uint32_t *value)
 Same as above but for unsigned.
int DWC_UTF8_TO_UTF16LE (uint8_t const *utf8string, uint16_t *utf16string, unsigned len)
 This routine returns a UTF16LE unicode encoded string from a UTF8 string.

Wait queues

Wait queues provide a means of synchronizing between threads or processes. A process can block on a waitq if some condition is not true, waiting for it to become true. When the waitq is triggered all waiting process will get unblocked and the condition will be check again. Waitqs should be triggered every time a condition can potentially change.

+-#define dwc_waitq_alloc   DWC_WAITQ_ALLOC
+-#define dwc_waitq_free   DWC_WAITQ_FREE
+-#define dwc_waitq_wait   DWC_WAITQ_WAIT;
+-#define dwc_waitq_wait_timeout   DWC_WAITQ_WAIT_TIMEOUT
+-#define dwc_waitq_trigger   DWC_WAITQ_TRIGGER
+-#define dwc_waitq_abort   DWC_WAITQ_ABORT
+-typedef dwc_waitq dwc_waitq_t
typedef int(*) dwc_waitq_condition_t (void *data)
 The type of waitq condition callback function.
dwc_waitq_t * DWC_WAITQ_ALLOC (void)
 Allocate a waitq.
void DWC_WAITQ_FREE (dwc_waitq_t *wq)
 Free a waitq.
int32_t DWC_WAITQ_WAIT (dwc_waitq_t *wq, dwc_waitq_condition_t condition, void *data)
 Check the condition and if it is false, block on the waitq.
int32_t DWC_WAITQ_WAIT_TIMEOUT (dwc_waitq_t *wq, dwc_waitq_condition_t condition, void *data, int32_t msecs)
 Check the condition and if it is false, block on the waitq.
void DWC_WAITQ_TRIGGER (dwc_waitq_t *wq)
 Trigger a waitq, unblocking all processes.
void DWC_WAITQ_ABORT (dwc_waitq_t *wq)
 Unblock all processes waiting on the waitq with an ABORTED result.

Threads

A thread must be explicitly stopped. It must check DWC_THREAD_SHOULD_STOP whenever it is woken up, and then return. The DWC_THREAD_STOP function returns the value from the thread.

+-#define dwc_thread_run   DWC_THREAD_RUN
+-#define dwc_thread_stop   DWC_THREAD_STOP
+-#define dwc_thread_should_stop   DWC_THREAD_SHOULD_STOP
+-typedef dwc_thread dwc_thread_t
typedef int(*) dwc_thread_function_t (void *data)
 The thread function.
dwc_thread_t * DWC_THREAD_RUN (dwc_thread_function_t thread_function, char *name, void *data)
 Create a thread and start it running the thread_function.
int DWC_THREAD_STOP (dwc_thread_t *thread)
 Stops a thread.
dwc_bool_t DWC_THREAD_SHOULD_STOP (void)
 Signifies to the thread that it must stop.

Work queues

Workqs are used to queue a callback function to be called at some later time, in another thread.

+-#define dwc_workq_alloc   DWC_WORKQ_ALLOC
+-#define dwc_workq_free   DWC_WORKQ_FREE
+-#define dwc_workq_schedule   DWC_WORKQ_SCHEDULE
+-#define dwc_workq_schedule_delayed   DWC_WORKQ_SCHEDULE_DELAYED
+-#define dwc_workq_pending   DWC_WORKQ_PENDING
+-#define dwc_workq_wait_work_done   DWC_WORKQ_WAIT_WORK_DONE
+-typedef dwc_workq dwc_workq_t
typedef void(*) dwc_work_callback_t (void *data)
 The type of the callback function to be called.
dwc_workq_t * DWC_WORKQ_ALLOC (char *name)
 Allocate a workq.
void DWC_WORKQ_FREE (dwc_workq_t *workq)
 Free a workq.
void DWC_WORKQ_SCHEDULE (dwc_workq_t *workq, dwc_work_callback_t work_cb, void *data, char *format,...)
 Schedule a callback on the workq, passing in data.
void DWC_WORKQ_SCHEDULE_DELAYED (dwc_workq_t *workq, dwc_work_callback_t work_cb, void *data, uint32_t time, char *format,...)
 Schedule a callback on the workq, that will be called until at least given number miliseconds have passed.
int DWC_WORKQ_PENDING (dwc_workq_t *workq)
 The number of processes in the workq.
int DWC_WORKQ_WAIT_WORK_DONE (dwc_workq_t *workq, int timeout)
 Blocks until all the work in the workq is complete or timed out.

Tasklets

+-#define dwc_task_alloc   DWC_TASK_ALLOC
+-#define dwc_task_free   DWC_TASK_FREE
+-#define dwc_task_schedule   DWC_TASK_SCHEDULE
+-typedef dwc_tasklet dwc_tasklet_t
+-typedef void(*) dwc_tasklet_callback_t (void *data)
+-dwc_tasklet_t * DWC_TASK_ALLOC (dwc_tasklet_callback_t cb, void *data)
+-void DWC_TASK_FREE (dwc_tasklet_t *t)
+-void DWC_TASK_SCHEDULE (dwc_tasklet_t *task)

Timer

Callbacks must be small and atomic.

+-#define dwc_timer_alloc   DWC_TIMER_ALLOC
+-#define dwc_timer_free   DWC_TIMER_FREE
+-#define dwc_timer_schedule   DWC_TIMER_SCHEDULE
+-#define dwc_timer_cancel   DWC_TIMER_CANCEL
+-typedef dwc_timer dwc_timer_t
+-typedef void(*) dwc_timer_callback_t (void *data)
+-dwc_timer_t * DWC_TIMER_ALLOC (char *name, dwc_timer_callback_t cb, void *data)
+-void DWC_TIMER_FREE (dwc_timer_t *timer)
void DWC_TIMER_SCHEDULE (dwc_timer_t *timer, uint32_t time)
 Schedules the timer to run at time ms from now.
void DWC_TIMER_CANCEL (dwc_timer_t *timer)
 Disables the timer from execution.

Spinlocks

These locks are used when the work between the lock/unlock is atomic and short. Interrupts are also disabled during the lock/unlock and thus they are suitable to lock between interrupt/non-interrupt context. They also lock between processes if you have multiple CPUs or Preemption. If you don't have multiple CPUS or Preemption, then the you can simply implement the DWC_SPINLOCK and DWC_SPINUNLOCK to disable and enable interrupts. Because the work between the lock/unlock is atomic, the process context will never change, and so you never have to lock between processes.

+-#define dwc_spinlock_alloc   DWC_SPINLOCK_ALLOC
+-#define dwc_spinlock_free   DWC_SPINLOCK_FREE
+-#define dwc_spinlock_irqsave   DWC_SPINLOCK_IRQSAVE
+-#define dwc_spinunlock_irqrestore   DWC_SPINUNLOCK_IRQRESTORE
+-#define dwc_spinlock   DWC_SPINLOCK
+-#define dwc_spinunlock   DWC_SPINUNLOCK
+-typedef dwc_spinlock dwc_spinlock_t
dwc_spinlock_t * DWC_SPINLOCK_ALLOC (void)
 Returns an initialized lock variable.
void DWC_SPINLOCK_FREE (dwc_spinlock_t *lock)
 Frees an initialized lock variable.
void DWC_SPINLOCK_IRQSAVE (dwc_spinlock_t *lock, uint64_t *flags)
 Disables interrupts and blocks until it acquires the lock.
void DWC_SPINUNLOCK_IRQRESTORE (dwc_spinlock_t *lock, uint64_t flags)
 Re-enables the interrupt and releases the lock.
void DWC_SPINLOCK (dwc_spinlock_t *lock)
 Blocks until it acquires the lock.
void DWC_SPINUNLOCK (dwc_spinlock_t *lock)
 Releases the lock.

Mutexes

Unlike spinlocks Mutexes lock only between processes and the work between the lock/unlock CAN block, therefore it CANNOT be called from interrupt context.

+-#define dwc_mutex_alloc   DWC_MUTEX_ALLOC
+-#define dwc_mutex_free   DWC_MUTEX_FREE
+-#define dwc_mutex_lock   DWC_MUTEX_LOCK
+-#define dwc_mutex_trylock   DWC_MUTEX_TRYLOCK
+-#define dwc_mutex_unlock   DWC_MUTEX_UNLOCK
+-typedef dwc_mutex dwc_mutex_t
+-dwc_mutex_t * DWC_MUTEX_ALLOC (void)
+-void DWC_MUTEX_FREE (dwc_mutex_t *mutex)
+-void DWC_MUTEX_LOCK (dwc_mutex_t *mutex)
int DWC_MUTEX_TRYLOCK (dwc_mutex_t *mutex)
 Non-blocking lock returns 1 on successful lock.
+-void DWC_MUTEX_UNLOCK (dwc_mutex_t *mutex)

Time

+-#define dwc_udelay   DWC_UDELAY
+-#define dwc_mdelay   DWC_MDELAY
+-#define dwc_msleep   DWC_MSLEEP
+-#define dwc_time   DWC_TIME
void DWC_UDELAY (uint32_t usecs)
 Microsecond delay.
void DWC_MDELAY (uint32_t msecs)
 Millisecond delay.
void DWC_MSLEEP (uint32_t msecs)
 Non-busy waiting.
+-uint32_t DWC_TIME (void)
+-

Define Documentation

+- +-
+-
+- +- +- +- +- +- +- +- +- +- +- +- +-
#define DWC_DEBUG (_format,
_args...   )    __DWC_DEBUG("DEBUG:%s:%s: " _format "\n", __func__, dwc_irq(), ## _args)
+-
+-
+- +-

+-Prints out a Debug message. +-

+- +-

+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +- +- +- +-
#define DWC_INFO (_format,
_args...   )    DWC_PRINTF("INFO:%s: " _format "\n", dwc_irq(), ## _args)
+-
+-
+- +-

+-Prints out an informative message. +-

+- +-

+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +- +- +- +-
#define DWC_WARN (_format,
_args...   )    __DWC_WARN("WARN:%s:%s:%d: " _format "\n", dwc_irq(), __func__, __LINE__, ## _args)
+-
+-
+- +-

+-Prints out a warning message. +-

+- +-

+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +- +- +- +-
#define DWC_ERROR (_format,
_args...   )    __DWC_ERROR("ERROR:%s:%s:%d: " _format "\n", dwc_irq(), __func__, __LINE__, ## _args)
+-
+-
+- +-

+-Prints out an error message. +-

+- +-

+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
#define DWC_ASSERT (_expr,
_format,
_args...   )    if (!(_expr)) { DWC_EXCEPTION("%s:%s:%d: " _format "\n", dwc_irq(), __FILE__, __LINE__, ## _args); }
+-
+-
+- +-

+-Prints out a exception error message if the _expr expression fails. +-

+-Disabled if DEBUG is not enabled. +-

+-

+-

Typedef Documentation

+- +-
+-
+- +- +- +- +-
typedef uint8_t dwc_bool_t
+-
+-
+- +-

+-We define a boolean type for consistency. +-

+-Can be either YES or NO +-

+-

+- +-

+-
+- +- +- +- +-
typedef int(*) dwc_waitq_condition_t(void *data)
+-
+-
+- +-

+-The type of waitq condition callback function. +-

+-This is called every time condition is evaluated. +-

+-

+- +-

+-
+- +- +- +- +-
typedef int(*) dwc_thread_function_t(void *data)
+-
+-
+- +-

+-The thread function. +-

+- +-

+-

+- +-

+-
+- +- +- +- +-
typedef void(*) dwc_work_callback_t(void *data)
+-
+-
+- +-

+-The type of the callback function to be called. +-

+- +-

+-

+-

Function Documentation

+- +-
+-
+- +- +- +- +- +- +- +- +- +-
dwc_bool_t DWC_IN_IRQ (void   ) 
+-
+-
+- +-

+-Returns non-zero if in interrupt context. +-

+- +-

+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +-
static char* dwc_irq (void   )  [inline, static]
+-
+-
+- +-

+-Returns "IRQ" if DWC_IN_IRQ is true. +-

+- +-

+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
void DWC_VPRINTF (char *  format,
va_list  args 
)
+-
+-
+- +-

+-A vprintf() clone. +-

+-Just call vprintf if you've got it. +-

+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
int DWC_VSNPRINTF (char *  str,
int  size,
char *  format,
va_list  args 
)
+-
+-
+- +-

+-A vsnprintf() clone. +-

+-Just call vprintf if you've got it. +-

+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
void DWC_PRINTF (char *  format,
  ... 
)
+-
+-
+- +-

+-printf() clone. +-

+-Just call printf if you've go it. +-

+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
int DWC_SPRINTF (char *  string,
char *  format,
  ... 
)
+-
+-
+- +-

+-sprintf() clone. +-

+-Just call sprintf if you've got it. +-

+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
int DWC_SNPRINTF (char *  string,
int  size,
char *  format,
  ... 
)
+-
+-
+- +-

+-snprintf() clone. +-

+-Just call snprintf if you've got it. +-

+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
void __DWC_WARN (char *  format,
  ... 
)
+-
+-
+- +-

+-Prints a WARNING message. +-

+-On systems that don't differentiate between warnings and regular log messages, just print it. Indicates that something may be wrong with the driver. Works like printf().

+-Use the DWC_WARN macro to call this function. +-

+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
void __DWC_ERROR (char *  format,
  ... 
)
+-
+-
+- +-

+-Prints an error message. +-

+-On systems that don't differentiate between errors and regular log messages, just print it. Indicates that something went wrong with the driver, but it can be recovered from. Works like printf().

+-Use the DWC_ERROR macro to call this function. +-

+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
void DWC_EXCEPTION (char *  format,
  ... 
)
+-
+-
+- +-

+-Prints an exception error message and takes some user-defined action such as print out a backtrace or trigger a breakpoint. +-

+-Indicates that something went abnormally wrong with the driver such as programmer error, or other exceptional condition. It should not be ignored so even on systems without printing capability, some action should be taken to notify the developer of it. Works like printf(). +-

+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
void __DWC_DEBUG (char *  format,
  ... 
)
+-
+-
+- +-

+-Prints out a debug message. +-

+-Used for logging/trace messages.

+-Use the DWC_DEBUG macro to call this function +-

+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +-
uint32_t DWC_CPU_TO_LE32 (void *  p  ) 
+-
+-
+- +-

+-Converts 32 bit data in CPU byte ordering to little endian. +-

+- +-

+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +-
uint32_t DWC_CPU_TO_BE32 (void *  p  ) 
+-
+-
+- +-

+-Converts 32 bit data in CPU byte orderint to big endian. +-

+- +-

+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +-
uint32_t DWC_LE32_TO_CPU (void *  p  ) 
+-
+-
+- +-

+-Converts 32 bit little endian data to CPU byte ordering. +-

+- +-

+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +-
uint32_t DWC_BE32_TO_CPU (void *  p  ) 
+-
+-
+- +-

+-Converts 32 bit big endian data to CPU byte ordering. +-

+- +-

+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +-
uint16_t DWC_CPU_TO_LE16 (void *  p  ) 
+-
+-
+- +-

+-Converts 16 bit data in CPU byte ordering to little endian. +-

+- +-

+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +-
uint16_t DWC_CPU_TO_BE16 (void *  p  ) 
+-
+-
+- +-

+-Converts 16 bit data in CPU byte orderint to big endian. +-

+- +-

+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +-
uint16_t DWC_LE16_TO_CPU (void *  p  ) 
+-
+-
+- +-

+-Converts 16 bit little endian data to CPU byte ordering. +-

+- +-

+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +-
uint16_t DWC_BE16_TO_CPU (void *  p  ) 
+-
+-
+- +-

+-Converts 16 bit bi endian data to CPU byte ordering. +-

+- +-

+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +-
uint32_t DWC_READ_REG32 (uint32_t volatile *  reg  ) 
+-
+-
+- +-

+-Reads the content of a 32-bit register. +-

+- +-

+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +-
uint64_t DWC_READ_REG64 (uint64_t volatile *  reg  ) 
+-
+-
+- +-

+-Reads the content of a 64-bit register. +-

+- +-

+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
void DWC_WRITE_REG32 (uint32_t volatile *  reg,
uint32_t  value 
)
+-
+-
+- +-

+-Writes to a 32-bit register. +-

+- +-

+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
void DWC_WRITE_REG64 (uint64_t volatile *  reg,
uint64_t  value 
)
+-
+-
+- +-

+-Writes to a 64-bit register. +-

+- +-

+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
void DWC_MODIFY_REG32 (uint32_t volatile *  reg,
uint32_t  clear_mask,
uint32_t  set_mask 
)
+-
+-
+- +-

+-Modify bit values in a register. +-

+-Using the algorithm: (reg_contents & ~clear_mask) | set_mask. +-

+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
int DWC_AES_CBC (uint8_t *  message,
uint32_t  messagelen,
uint8_t *  key,
uint32_t  keylen,
uint8_t  iv[16],
uint8_t *  out 
)
+-
+-
+- +-

+-Perform AES CBC. +-

+- +-

+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
void DWC_RANDOM_BYTES (uint8_t *  buffer,
uint32_t  length 
)
+-
+-
+- +-

+-Fill the provided buffer with random bytes. +-

+-These should be cryptographic grade random numbers. +-

+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
int DWC_SHA256 (uint8_t *  message,
uint32_t  len,
uint8_t *  out 
)
+-
+-
+- +-

+-Perform the SHA-256 hash function. +-

+- +-

+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
int DWC_HMAC_SHA256 (uint8_t *  message,
uint32_t  messagelen,
uint8_t *  key,
uint32_t  keylen,
uint8_t *  out 
)
+-
+-
+- +-

+-Calculated the HMAC-SHA256. +-

+- +-

+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
void* __DWC_DMA_ALLOC (uint32_t  size,
dwc_dma_t *  dma_addr 
)
+-
+-
+- +-

+-Allocates a DMA capable buffer and zeroes its contents. +-

+- +-

+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
void __DWC_DMA_FREE (uint32_t  size,
void *  virt_addr,
dwc_dma_t  dma_addr 
)
+-
+-
+- +-

+-Frees a previosly allocated buffer. +-

+- +-

+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +-
void* __DWC_ALLOC (uint32_t  size  ) 
+-
+-
+- +-

+-Allocates a block of memory and zeroes its contents. +-

+- +-

+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +-
void* __DWC_ALLOC_ATOMIC (uint32_t  size  ) 
+-
+-
+- +-

+-Allocates a block of memory and zeroes its contents, in an atomic manner which can be used inside interrupt context. +-

+-The size should be sufficiently small, a few KB at most, such that failures are not likely to occur. Can just call __DWC_ALLOC if it is atomic. +-

+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +-
void __DWC_FREE (void *  addr  ) 
+-
+-
+- +-

+-Frees a previously allocated buffer. +-

+- +-

+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
void* DWC_MEMSET (void *  dest,
uint8_t  byte,
uint32_t  size 
)
+-
+-
+- +-

+-memset() clone +-

+- +-

+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
void* DWC_MEMCPY (void *  dest,
void const *  src,
uint32_t  size 
)
+-
+-
+- +-

+-memcpy() clone +-

+- +-

+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
void* DWC_MEMMOVE (void *  dest,
void *  src,
uint32_t  size 
)
+-
+-
+- +-

+-memmove() clone +-

+- +-

+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
int DWC_MEMCMP (void *  m1,
void *  m2,
uint32_t  size 
)
+-
+-
+- +-

+-memcmp() clone +-

+- +-

+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
int DWC_STRCMP (void *  s1,
void *  s2 
)
+-
+-
+- +-

+-strcmp() clone +-

+- +-

+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
int DWC_STRNCMP (void *  s1,
void *  s2,
uint32_t  size 
)
+-
+-
+- +-

+-strncmp() clone +-

+- +-

+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +-
int DWC_STRLEN (char const *  str  ) 
+-
+-
+- +-

+-strlen() clone, for NULL terminated ASCII strings +-

+- +-

+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
char* DWC_STRCPY (char *  to,
const char *  from 
)
+-
+-
+- +-

+-strcpy() clone, for NULL terminated ASCII strings +-

+- +-

+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +-
char* DWC_STRDUP (char const *  str  ) 
+-
+-
+- +-

+-strdup() clone. +-

+-If you wish to use memory allocation debugging, this implementation of strdup should use the DWC_* memory routines instead of calling a predefined strdup. Otherwise the memory allocated by this routine will not be seen by the debugging routines. +-

+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
int DWC_ATOI (char *  str,
int32_t *  value 
)
+-
+-
+- +-

+-NOT an atoi() clone. +-

+-Read the description carefully. Returns an integer converted from the string str in base 10 unless the string begins with a "0x" in which case it is base 16. String must be a NULL terminated sequence of ASCII characters and may optionally begin with whitespace, a + or -, and a "0x" prefix if base 16. The remaining characters must be valid digits for the number and end with a NULL character. If any invalid characters are encountered or it returns with a negative error code and the results of the conversion are undefined. On sucess it returns 0. Overflow conditions are undefined. An example implementation using atoi() can be referenced from the Linux implementation. +-

+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
int DWC_ATOUI (char *  str,
uint32_t *  value 
)
+-
+-
+- +-

+-Same as above but for unsigned. +-

+- +-

+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
int DWC_UTF8_TO_UTF16LE (uint8_t const *  utf8string,
uint16_t *  utf16string,
unsigned  len 
)
+-
+-
+- +-

+-This routine returns a UTF16LE unicode encoded string from a UTF8 string. +-

+- +-

+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +-
dwc_waitq_t* DWC_WAITQ_ALLOC (void   ) 
+-
+-
+- +-

+-Allocate a waitq. +-

+- +-

+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +-
void DWC_WAITQ_FREE (dwc_waitq_t *  wq  ) 
+-
+-
+- +-

+-Free a waitq. +-

+- +-

+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
int32_t DWC_WAITQ_WAIT (dwc_waitq_t *  wq,
dwc_waitq_condition_t  condition,
void *  data 
)
+-
+-
+- +-

+-Check the condition and if it is false, block on the waitq. +-

+-When unblocked, check the condition again. The function returns when the condition becomes true. The return value is 0 on condition true, DWC_WAITQ_ABORTED on abort or killed, or DWC_WAITQ_UNKNOWN on error. +-

+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
int32_t DWC_WAITQ_WAIT_TIMEOUT (dwc_waitq_t *  wq,
dwc_waitq_condition_t  condition,
void *  data,
int32_t  msecs 
)
+-
+-
+- +-

+-Check the condition and if it is false, block on the waitq. +-

+-When unblocked, check the condition again. The function returns when the condition become true or the timeout has passed. The return value is 0 on condition true or DWC_TIMED_OUT on timeout, or DWC_WAITQ_ABORTED, or DWC_WAITQ_UNKNOWN on error. +-

+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +-
void DWC_WAITQ_TRIGGER (dwc_waitq_t *  wq  ) 
+-
+-
+- +-

+-Trigger a waitq, unblocking all processes. +-

+-This should be called whenever a condition has potentially changed. +-

+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +-
void DWC_WAITQ_ABORT (dwc_waitq_t *  wq  ) 
+-
+-
+- +-

+-Unblock all processes waiting on the waitq with an ABORTED result. +-

+- +-

+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
dwc_thread_t* DWC_THREAD_RUN (dwc_thread_function_t  thread_function,
char *  name,
void *  data 
)
+-
+-
+- +-

+-Create a thread and start it running the thread_function. +-

+-Returns a handle to the thread +-

+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +-
int DWC_THREAD_STOP (dwc_thread_t *  thread  ) 
+-
+-
+- +-

+-Stops a thread. +-

+-Return the value returned by the thread. Or will return DWC_ABORT if the thread never started. +-

+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +-
dwc_bool_t DWC_THREAD_SHOULD_STOP (void   ) 
+-
+-
+- +-

+-Signifies to the thread that it must stop. +-

+- +-

+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +-
dwc_workq_t* DWC_WORKQ_ALLOC (char *  name  ) 
+-
+-
+- +-

+-Allocate a workq. +-

+- +-

+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +-
void DWC_WORKQ_FREE (dwc_workq_t *  workq  ) 
+-
+-
+- +-

+-Free a workq. +-

+-All work must be completed before being freed. +-

+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
void DWC_WORKQ_SCHEDULE (dwc_workq_t *  workq,
dwc_work_callback_t  work_cb,
void *  data,
char *  format,
  ... 
)
+-
+-
+- +-

+-Schedule a callback on the workq, passing in data. +-

+-The function will be scheduled at some later time. +-

+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
void DWC_WORKQ_SCHEDULE_DELAYED (dwc_workq_t *  workq,
dwc_work_callback_t  work_cb,
void *  data,
uint32_t  time,
char *  format,
  ... 
)
+-
+-
+- +-

+-Schedule a callback on the workq, that will be called until at least given number miliseconds have passed. +-

+- +-

+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +-
int DWC_WORKQ_PENDING (dwc_workq_t *  workq  ) 
+-
+-
+- +-

+-The number of processes in the workq. +-

+- +-

+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
int DWC_WORKQ_WAIT_WORK_DONE (dwc_workq_t *  workq,
int  timeout 
)
+-
+-
+- +-

+-Blocks until all the work in the workq is complete or timed out. +-

+-Returns < 0 on timeout. +-

+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
void DWC_TIMER_SCHEDULE (dwc_timer_t *  timer,
uint32_t  time 
)
+-
+-
+- +-

+-Schedules the timer to run at time ms from now. +-

+-And will repeat at every repeat_interval msec therafter

+-Modifies a timer that is still awaiting execution to a new expiration time. The mod_time is added to the old time. +-

+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +-
void DWC_TIMER_CANCEL (dwc_timer_t *  timer  ) 
+-
+-
+- +-

+-Disables the timer from execution. +-

+- +-

+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +-
dwc_spinlock_t* DWC_SPINLOCK_ALLOC (void   ) 
+-
+-
+- +-

+-Returns an initialized lock variable. +-

+-This function should allocate and initialize the OS-specific data structure used for locking. This data structure is to be used for the DWC_LOCK and DWC_UNLOCK functions and should be freed by the DWC_FREE_LOCK when it is no longer used. +-

+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +-
void DWC_SPINLOCK_FREE (dwc_spinlock_t *  lock  ) 
+-
+-
+- +-

+-Frees an initialized lock variable. +-

+- +-

+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
void DWC_SPINLOCK_IRQSAVE (dwc_spinlock_t *  lock,
uint64_t *  flags 
)
+-
+-
+- +-

+-Disables interrupts and blocks until it acquires the lock. +-

+-

Parameters:
+- +- +- +-
lock Pointer to the spinlock.
flags Unsigned long for irq flags storage.
+-
+- +-
+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
void DWC_SPINUNLOCK_IRQRESTORE (dwc_spinlock_t *  lock,
uint64_t  flags 
)
+-
+-
+- +-

+-Re-enables the interrupt and releases the lock. +-

+-

Parameters:
+- +- +- +-
lock Pointer to the spinlock.
flags Unsigned long for irq flags storage. Must be the same as was passed into DWC_LOCK.
+-
+- +-
+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +-
void DWC_SPINLOCK (dwc_spinlock_t *  lock  ) 
+-
+-
+- +-

+-Blocks until it acquires the lock. +-

+-

Parameters:
+- +- +-
lock Pointer to the spinlock.
+-
+- +-
+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +-
void DWC_SPINUNLOCK (dwc_spinlock_t *  lock  ) 
+-
+-
+- +-

+-Releases the lock. +-

+-

Parameters:
+- +- +-
lock Pointer to the spinlock.
+-
+- +-
+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +-
int DWC_MUTEX_TRYLOCK (dwc_mutex_t *  mutex  ) 
+-
+-
+- +-

+-Non-blocking lock returns 1 on successful lock. +-

+- +-

+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +-
void DWC_UDELAY (uint32_t  usecs  ) 
+-
+-
+- +-

+-Microsecond delay. +-

+-

Parameters:
+- +- +-
usecs Microseconds to delay.
+-
+- +-
+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +-
void DWC_MDELAY (uint32_t  msecs  ) 
+-
+-
+- +-

+-Millisecond delay. +-

+-

Parameters:
+- +- +-
msecs Milliseconds to delay.
+-
+- +-
+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +-
void DWC_MSLEEP (uint32_t  msecs  ) 
+-
+-
+- +-

+-Non-busy waiting. +-

+-Sleeps for specified number of milliseconds.

+-

Parameters:
+- +- +-
msecs Milliseconds to sleep.
+-
+- +-
+-

+-

Generated on Tue May 5 02:22:50 2009 for Synopsys DWC Portability and Common Library for UWB by  +- +-doxygen 1.4.7
+- +- +Index: linux-3.2.46/drivers/usb/host/dwc_common_port/doc/html/files.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_common_port/doc/html/files.html 2013-07-26 19:31:19.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,34 +0,0 @@ +- +- +-Synopsys DWC Portability and Common Library for UWB: File Index +- +- +- +- +-
+-
+-
+-
+-

Synopsys DWC Portability and Common Library for UWB File List

Here is a list of all documented files with brief descriptions: +- +- +- +- +- +- +- +- +-
dwc_cc.hThis file defines the Context Context library
dwc_crypto.cThis file contains the WUSB cryptographic routines
dwc_crypto.hThis file contains declarations for the WUSB Cryptographic routines as defined in the WUSB spec
dwc_dh.hThis file defines the common functions on device and host for performing numeric association as defined in the WUSB spec
dwc_list.hThis file defines linked list operations
dwc_modpow.hThis file defines the module exponentiation function which is only used internally by the DWC UWB modules for calculation of PKs during numeric association
dwc_notifier.hA simple implementation of the Observer pattern
dwc_os.hDWC portability library, low level os-wrapper functions
+-
Generated on Tue May 5 02:22:50 2009 for Synopsys DWC Portability and Common Library for UWB by  +- +-doxygen 1.4.7
+- +- +Index: linux-3.2.46/drivers/usb/host/dwc_common_port/doc/html/globals.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_common_port/doc/html/globals.html 2013-07-26 19:31:19.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,163 +0,0 @@ +- +- +-Synopsys DWC Portability and Common Library for UWB: Data Fields +- +- +- +- +-
+-
+-
+-
+-
+- +-
+-
+-
    +-
  • _
    • +-
  • d
    • +-
+-
+- +-

+-Here is a list of all documented functions, variables, defines, enums, and typedefs with links to the documentation: +-

+-

- _ -

+-

- d -

+-
Generated on Tue May 5 02:22:50 2009 for Synopsys DWC Portability and Common Library for UWB by  +- +-doxygen 1.4.7
+- +- +Index: linux-3.2.46/drivers/usb/host/dwc_common_port/doc/html/globals_defs.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_common_port/doc/html/globals_defs.html 2013-07-26 19:31:19.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,41 +0,0 @@ +- +- +-Synopsys DWC Portability and Common Library for UWB: Data Fields +- +- +- +- +-
+-
+-
+-
+-
+- +-
+-  +-

+-

+-
Generated on Tue May 5 02:22:50 2009 for Synopsys DWC Portability and Common Library for UWB by  +- +-doxygen 1.4.7
+- +- +Index: linux-3.2.46/drivers/usb/host/dwc_common_port/doc/html/globals_func.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_common_port/doc/html/globals_func.html 2013-07-26 19:31:19.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,153 +0,0 @@ +- +- +-Synopsys DWC Portability and Common Library for UWB: Data Fields +- +- +- +- +-
+-
+-
+-
+-
+- +-
+-
+-
    +-
  • _
    • +-
  • d
    • +-
+-
+- +-

+-  +-

+-

- _ -

+-

- d -

+-
Generated on Tue May 5 02:22:50 2009 for Synopsys DWC Portability and Common Library for UWB by  +- +-doxygen 1.4.7
+- +- +Index: linux-3.2.46/drivers/usb/host/dwc_common_port/doc/html/globals_type.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_common_port/doc/html/globals_type.html 2013-07-26 19:31:19.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,41 +0,0 @@ +- +- +-Synopsys DWC Portability and Common Library for UWB: Data Fields +- +- +- +- +-
+-
+-
+-
+-
+- +-
+-  +-

+-

+-
Generated on Tue May 5 02:22:50 2009 for Synopsys DWC Portability and Common Library for UWB by  +- +-doxygen 1.4.7
+- +- +Index: linux-3.2.46/drivers/usb/host/dwc_common_port/doc/html/index.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_common_port/doc/html/index.html 2013-07-26 19:31:19.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,8 +0,0 @@ +- +- +-Synopsys DWC Portability and Common Library for UWB +- +- +- +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_common_port/doc/html/main.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_common_port/doc/html/main.html 2013-07-26 19:31:19.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,45 +0,0 @@ +- +- +-Synopsys DWC Portability and Common Library for UWB: DWC Portability and Common Library +- +- +- +- +-
+-
+-

DWC Portability and Common Library

+-

+-This is the documentation for the DWC Portability and Common Library.

+-Introduction

+-The DWC Portability library consists of wrapper calls and data structures to all low-level functions which are typically provided by the OS. The WUDEV driver uses only these functions. In order to port the WUDEV driver, only the functions in this library need to be re-implemented, with the same behavior as documented here.

+-The Common library consists of higher level functions, which rely only on calling the functions from the DWC Portability library. These common routines are shared across modules. Some of the common libraries need to be used directly by the driver programmer when porting WUDEV. Such as the parameter and notification libraries.

+-Portability Library OS Wrapper Functions

+-Any function starting with DWC and in all CAPS is a low-level OS-wrapper that needs to be implemented when porting, for example DWC_MUTEX_ALLOC(). All of these functions are included in the dwc_os.h file.

+-There are many functions here covering a wide array of OS services. Please see dwc_os.h for details, and implementation notes for each function.

+-Common Library Functions

+-Any function starting with dwc and in all lowercase is a common library routine. These functions have a portable implementation and do not need to be reimplemented when porting. The common routines can be used by any driver, and some must be used by the end user to control the drivers. For example, you must use the Parameter common library in order to set the parameters in the WUDEV module.

+-The common libraries consist of the following:

+-

    +-
  • Connection Contexts - Used internally and can be used by end-user. See dwc_cc.h
  • Parameters - Used internally and can be used by end-user. See dwc_params.h
  • Notifications - Used internally and can be used by end-user. See dwc_notifier.h
  • Lists - Used internally and can be used by end-user. See dwc_list.h
  • Memory Debugging - Used internally and can be used by end-user. See dwc_os.h
  • Modpow - Used internally only. See dwc_modpow.h
  • DH - Used internally only. See dwc_dh.h
  • Crypto - Used internally only. See dwc_crypto.h
+-

+-Prerequistes For dwc_os.h

+-

+-Data Types

+-The dwc_os.h file assumes that several low-level data types are pre defined for the compilation environment. These data types are:

+-

    +-
  • uint8_t - unsigned 8-bit data type
  • int8_t - signed 8-bit data type
  • uint16_t - unsigned 16-bit data type
  • int16_t - signed 16-bit data type
  • uint32_t - unsigned 32-bit data type
  • int32_t - signed 32-bit data type
  • uint64_t - unsigned 64-bit data type
  • int64_t - signed 64-bit data type
+-

+-Ensure that these are defined before using dwc_os.h. The easiest way to do that is to modify the top of the file to include the appropriate header. This is already done for the Linux environment. If the DWC_LINUX macro is defined, the correct header will be added. A standard header <stdint.h> is also used for environments where standard C headers are available.

+-Variable Arguments

+-Variable arguments are provided by a standard C header <stdarg.h>. it is available in Both the Linux and ANSI C enviornment. An equivalent must be provided in your enviornment in order to use dwc_os.h with the debug and tracing message functionality.

+-Threading

+-WUDEV Core must be run on an operating system that provides for multiple threads/processes. Threading can be implemented in many ways, even in embedded systems without an operating system. At the bare minimum, the system should be able to start any number of processes at any time to handle special work. It need not be a pre-emptive system. Process context can change upon a call to a blocking function. The hardware interrupt context that calls the module's ISR() function must be differentiable from process context, even if your processes are impemented via a hardware interrupt. Further locking mechanism between process must exist (or be implemented), and process context must have a way to disable interrupts for a period of time to lock them out. If all of this exists, the functions in dwc_os.h related to threading should be able to be implemented with the defined behavior.
Generated on Tue May 5 02:22:50 2009 for Synopsys DWC Portability and Common Library for UWB by  +- +-doxygen 1.4.7
+- +- +Index: linux-3.2.46/drivers/usb/host/dwc_common_port/doc/html/pages.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_common_port/doc/html/pages.html 2013-07-26 19:31:19.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,23 +0,0 @@ +- +- +-Synopsys DWC Portability and Common Library for UWB: Page Index +- +- +- +- +-
+-
+-

Synopsys DWC Portability and Common Library for UWB Related Pages

Here is a list of all related documentation pages: +-
Generated on Tue May 5 02:22:50 2009 for Synopsys DWC Portability and Common Library for UWB by  +- +-doxygen 1.4.7
+- +- +Index: linux-3.2.46/drivers/usb/host/dwc_common_port/doc/html/tabs.css +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_common_port/doc/html/tabs.css 2013-07-26 19:31:19.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,102 +0,0 @@ +-/* tabs styles, based on http://www.alistapart.com/articles/slidingdoors */ +- +-DIV.tabs +-{ +- float : left; +- width : 100%; +- background : url("tab_b.gif") repeat-x bottom; +- margin-bottom : 4px; +-} +- +-DIV.tabs UL +-{ +- margin : 0px; +- padding-left : 10px; +- list-style : none; +-} +- +-DIV.tabs LI, DIV.tabs FORM +-{ +- display : inline; +- margin : 0px; +- padding : 0px; +-} +- +-DIV.tabs FORM +-{ +- float : right; +-} +- +-DIV.tabs A +-{ +- float : left; +- background : url("tab_r.gif") no-repeat right top; +- border-bottom : 1px solid #84B0C7; +- font-size : x-small; +- font-weight : bold; +- text-decoration : none; +-} +- +-DIV.tabs A:hover +-{ +- background-position: 100% -150px; +-} +- +-DIV.tabs A:link, DIV.tabs A:visited, +-DIV.tabs A:active, DIV.tabs A:hover +-{ +- color: #1A419D; +-} +- +-DIV.tabs SPAN +-{ +- float : left; +- display : block; +- background : url("tab_l.gif") no-repeat left top; +- padding : 5px 9px; +- white-space : nowrap; +-} +- +-DIV.tabs INPUT +-{ +- float : right; +- display : inline; +- font-size : 1em; +-} +- +-DIV.tabs TD +-{ +- font-size : x-small; +- font-weight : bold; +- text-decoration : none; +-} +- +- +- +-/* Commented Backslash Hack hides rule from IE5-Mac \*/ +-DIV.tabs SPAN {float : none;} +-/* End IE5-Mac hack */ +- +-DIV.tabs A:hover SPAN +-{ +- background-position: 0% -150px; +-} +- +-DIV.tabs LI#current A +-{ +- background-position: 100% -150px; +- border-width : 0px; +-} +- +-DIV.tabs LI#current SPAN +-{ +- background-position: 0% -150px; +- padding-bottom : 6px; +-} +- +-DIV.nav +-{ +- background : none; +- border : none; +- border-bottom : 1px solid #84B0C7; +-} +Index: linux-3.2.46/drivers/usb/host/dwc_common_port/doc/html/todo.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_common_port/doc/html/todo.html 2013-07-26 19:31:19.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,23 +0,0 @@ +- +- +-Synopsys DWC Portability and Common Library for UWB: Todo List +- +- +- +- +-
+-
+-

Todo List

+-
Global __DWC_DMA_ALLOC
+-
these functions will be added in the future
+-
+-
Generated on Tue May 5 02:22:50 2009 for Synopsys DWC Portability and Common Library for UWB by  +- +-doxygen 1.4.7
+- +- +Index: linux-3.2.46/drivers/usb/host/dwc_common_port/doc/html/tree.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_common_port/doc/html/tree.html 2013-07-26 19:31:19.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,90 +0,0 @@ +- +- +- +- +- +- +- TreeView +- +- +- +- +-
+-

Synopsys DWC Portability and Common Library for UWB

+- +-
+- +- +Index: linux-3.2.46/drivers/usb/host/dwc_common_port/dwc_cc.c +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_common_port/dwc_cc.c 2013-07-26 19:31:19.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_common_port/dwc_cc.c 2013-07-26 19:34:39.000000000 +0000 +@@ -1,8 +1,8 @@ + /* ========================================================================= +- * $File: //dwh/usb_iip/dev/software/dwc_common_port/dwc_cc.c $ +- * $Revision: #1 $ +- * $Date: 2008/12/21 $ +- * $Change: 1156609 $ ++ * $File: //dwh/usb_iip/dev/software/dwc_common_port_2/dwc_cc.c $ ++ * $Revision: #4 $ ++ * $Date: 2010/11/04 $ ++ * $Change: 1621692 $ + * + * Synopsys Portability Library Software and documentation + * (hereinafter, "Software") is an Unsupported proprietary work of +@@ -33,6 +33,8 @@ + * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH + * DAMAGE. + * ========================================================================= */ ++#ifdef DWC_CCLIB ++ + #include "dwc_cc.h" + + typedef struct dwc_cc +@@ -75,9 +77,9 @@ + #define dump_bytes(x...) + #endif + +-static dwc_cc_t *alloc_cc(uint8_t *name, uint32_t length) ++static dwc_cc_t *alloc_cc(void *mem_ctx, uint8_t *name, uint32_t length) + { +- dwc_cc_t *cc = DWC_ALLOC(sizeof(dwc_cc_t)); ++ dwc_cc_t *cc = dwc_alloc(mem_ctx, sizeof(dwc_cc_t)); + if (!cc) { + return NULL; + } +@@ -85,19 +87,24 @@ + + if (name) { + cc->length = length; +- cc->name = DWC_ALLOC(length); ++ cc->name = dwc_alloc(mem_ctx, length); ++ if (!cc->name) { ++ dwc_free(mem_ctx, cc); ++ return NULL; ++ } ++ + DWC_MEMCPY(cc->name, name, length); + } + + return cc; + } + +-static void free_cc(dwc_cc_t *cc) ++static void free_cc(void *mem_ctx, dwc_cc_t *cc) + { + if (cc->name) { +- DWC_FREE(cc->name); ++ dwc_free(mem_ctx, cc->name); + } +- DWC_FREE(cc); ++ dwc_free(mem_ctx, cc); + } + + static uint32_t next_uid(dwc_cc_if_t *cc_if) +@@ -169,7 +176,8 @@ + } + + /* Internal cc_add */ +-static int32_t cc_add(dwc_cc_if_t *cc_if, uint8_t *chid, uint8_t *cdid, uint8_t *ck, uint8_t *name, uint8_t length) ++static int32_t cc_add(void *mem_ctx, dwc_cc_if_t *cc_if, uint8_t *chid, ++ uint8_t *cdid, uint8_t *ck, uint8_t *name, uint8_t length) + { + dwc_cc_t *cc; + uint32_t uid; +@@ -182,11 +190,11 @@ + } + + if (uid) { +- DWC_DEBUG("Replacing previous connection context id=%d name=%p name_len=%d", uid, name, length); ++ DWC_DEBUGC("Replacing previous connection context id=%d name=%p name_len=%d", uid, name, length); + cc = cc_find(cc_if, uid); + } + else { +- cc = alloc_cc(name, length); ++ cc = alloc_cc(mem_ctx, name, length); + cc->uid = next_uid(cc_if); + DWC_CIRCLEQ_INSERT_TAIL(&cc_if->list, cc, list_entry); + } +@@ -195,7 +203,7 @@ + DWC_MEMCPY(&(cc->cdid[0]), cdid, 16); + DWC_MEMCPY(&(cc->ck[0]), ck, 16); + +- DWC_DEBUG("Added connection context id=%d name=%p name_len=%d", cc->uid, name, length); ++ DWC_DEBUGC("Added connection context id=%d name=%p name_len=%d", cc->uid, name, length); + dump_bytes("CHID", cc->chid, 16); + dump_bytes("CDID", cc->cdid, 16); + dump_bytes("CK", cc->ck, 16); +@@ -203,41 +211,51 @@ + } + + /* Internal cc_clear */ +-static void cc_clear(dwc_cc_if_t *cc_if) ++static void cc_clear(void *mem_ctx, dwc_cc_if_t *cc_if) + { + while (!DWC_CIRCLEQ_EMPTY(&cc_if->list)) { + dwc_cc_t *cc = DWC_CIRCLEQ_FIRST(&cc_if->list); + DWC_CIRCLEQ_REMOVE_INIT(&cc_if->list, cc, list_entry); +- free_cc(cc); ++ free_cc(mem_ctx, cc); + } + } + +-dwc_cc_if_t *dwc_cc_if_alloc(dwc_notifier_t *notifier, unsigned is_host) ++dwc_cc_if_t *dwc_cc_if_alloc(void *mem_ctx, void *mtx_ctx, ++ dwc_notifier_t *notifier, unsigned is_host) + { + dwc_cc_if_t *cc_if = NULL; + + /* Allocate a common_cc_if structure */ +- cc_if = DWC_ALLOC(sizeof(dwc_cc_if_t)); ++ cc_if = dwc_alloc(mem_ctx, sizeof(dwc_cc_if_t)); + +- if(!cc_if) ++ if (!cc_if) + return NULL; + + #if (defined(DWC_LINUX) && defined(CONFIG_DEBUG_MUTEXES)) + DWC_MUTEX_ALLOC_LINUX_DEBUG(cc_if->mutex); + #else +- cc_if->mutex = DWC_MUTEX_ALLOC(); ++ cc_if->mutex = dwc_mutex_alloc(mtx_ctx); + #endif ++ if (!cc_if->mutex) { ++ dwc_free(mem_ctx, cc_if); ++ return NULL; ++ } ++ + DWC_CIRCLEQ_INIT(&cc_if->list); + cc_if->is_host = is_host; + cc_if->notifier = notifier; + return cc_if; + } + +-void dwc_cc_if_free(dwc_cc_if_t *cc_if) ++void dwc_cc_if_free(void *mem_ctx, void *mtx_ctx, dwc_cc_if_t *cc_if) + { ++#if (defined(DWC_LINUX) && defined(CONFIG_DEBUG_MUTEXES)) + DWC_MUTEX_FREE(cc_if->mutex); +- cc_clear(cc_if); +- DWC_FREE(cc_if); ++#else ++ dwc_mutex_free(mtx_ctx, cc_if->mutex); ++#endif ++ cc_clear(mem_ctx, cc_if); ++ dwc_free(mem_ctx, cc_if); + } + + static void cc_changed(dwc_cc_if_t *cc_if) +@@ -247,37 +265,38 @@ + } + } + +-void dwc_cc_clear(dwc_cc_if_t *cc_if) ++void dwc_cc_clear(void *mem_ctx, dwc_cc_if_t *cc_if) + { + DWC_MUTEX_LOCK(cc_if->mutex); +- cc_clear(cc_if); ++ cc_clear(mem_ctx, cc_if); + DWC_MUTEX_UNLOCK(cc_if->mutex); + cc_changed(cc_if); + } + +-int32_t dwc_cc_add(dwc_cc_if_t *cc_if, uint8_t *chid, uint8_t *cdid, uint8_t *ck, uint8_t *name, uint8_t length) ++int32_t dwc_cc_add(void *mem_ctx, dwc_cc_if_t *cc_if, uint8_t *chid, ++ uint8_t *cdid, uint8_t *ck, uint8_t *name, uint8_t length) + { + uint32_t uid; + + DWC_MUTEX_LOCK(cc_if->mutex); +- uid = cc_add(cc_if, chid, cdid, ck, name, length); ++ uid = cc_add(mem_ctx, cc_if, chid, cdid, ck, name, length); + DWC_MUTEX_UNLOCK(cc_if->mutex); + cc_changed(cc_if); + + return uid; + } + +-void dwc_cc_change(dwc_cc_if_t *cc_if, int32_t id, +- uint8_t *chid, uint8_t *cdid, uint8_t *ck, uint8_t *name, uint8_t length) ++void dwc_cc_change(void *mem_ctx, dwc_cc_if_t *cc_if, int32_t id, uint8_t *chid, ++ uint8_t *cdid, uint8_t *ck, uint8_t *name, uint8_t length) + { + dwc_cc_t* cc; + +- DWC_DEBUG("Change connection context %d", id); ++ DWC_DEBUGC("Change connection context %d", id); + + DWC_MUTEX_LOCK(cc_if->mutex); + cc = cc_find(cc_if, id); + if (!cc) { +- DWC_ERROR("Uid %d not found in cc list", id); ++ DWC_ERROR("Uid %d not found in cc list\n", id); + DWC_MUTEX_UNLOCK(cc_if->mutex); + return; + } +@@ -294,9 +313,14 @@ + + if (name) { + if (cc->name) { +- DWC_FREE(cc->name); ++ dwc_free(mem_ctx, cc->name); ++ } ++ cc->name = dwc_alloc(mem_ctx, length); ++ if (!cc->name) { ++ DWC_ERROR("Out of memory in dwc_cc_change()\n"); ++ DWC_MUTEX_UNLOCK(cc_if->mutex); ++ return; + } +- cc->name = DWC_ALLOC(length); + cc->length = length; + DWC_MEMCPY(cc->name, name, length); + } +@@ -305,34 +329,34 @@ + + cc_changed(cc_if); + +- DWC_DEBUG("Changed connection context id=%d\n", id); ++ DWC_DEBUGC("Changed connection context id=%d\n", id); + dump_bytes("New CHID", cc->chid, 16); + dump_bytes("New CDID", cc->cdid, 16); + dump_bytes("New CK", cc->ck, 16); + } + +-void dwc_cc_remove(dwc_cc_if_t *cc_if, int32_t id) ++void dwc_cc_remove(void *mem_ctx, dwc_cc_if_t *cc_if, int32_t id) + { + dwc_cc_t *cc; + +- DWC_DEBUG("Removing connection context %d", id); ++ DWC_DEBUGC("Removing connection context %d", id); + + DWC_MUTEX_LOCK(cc_if->mutex); + cc = cc_find(cc_if, id); + if (!cc) { +- DWC_ERROR("Uid %d not found in cc list", id); ++ DWC_ERROR("Uid %d not found in cc list\n", id); + DWC_MUTEX_UNLOCK(cc_if->mutex); + return; + } + + DWC_CIRCLEQ_REMOVE_INIT(&cc_if->list, cc, list_entry); + DWC_MUTEX_UNLOCK(cc_if->mutex); +- free_cc(cc); ++ free_cc(mem_ctx, cc); + + cc_changed(cc_if); + } + +-uint8_t *dwc_cc_data_for_save(dwc_cc_if_t *cc_if, unsigned int *length) ++uint8_t *dwc_cc_data_for_save(void *mem_ctx, dwc_cc_if_t *cc_if, unsigned int *length) + { + uint8_t *buf, *x; + uint8_t zero = 0; +@@ -345,9 +369,9 @@ + return NULL; + } + +- DWC_DEBUG("Creating data for saving (length=%d)", *length); ++ DWC_DEBUGC("Creating data for saving (length=%d)", *length); + +- buf = DWC_ALLOC(*length); ++ buf = dwc_alloc(mem_ctx, *length); + if (!buf) { + *length = 0; + DWC_MUTEX_UNLOCK(cc_if->mutex); +@@ -378,7 +402,7 @@ + return buf; + } + +-void dwc_cc_restore_from_data(dwc_cc_if_t *cc_if, uint8_t *data, uint32_t length) ++void dwc_cc_restore_from_data(void *mem_ctx, dwc_cc_if_t *cc_if, uint8_t *data, uint32_t length) + { + uint8_t name_length; + uint8_t *name; +@@ -388,7 +412,7 @@ + uint32_t i = 0; + + DWC_MUTEX_LOCK(cc_if->mutex); +- cc_clear(cc_if); ++ cc_clear(mem_ctx, cc_if); + + while (i < length) { + chid = &data[i]; +@@ -412,11 +436,11 @@ + /* check to see if we haven't overflown the buffer */ + if (i > length) { + DWC_ERROR("Data format error while attempting to load CCs " +- "(nlen=%d, iter=%d, buflen=%d).", name_length, i, length); ++ "(nlen=%d, iter=%d, buflen=%d).\n", name_length, i, length); + break; + } + +- cc_add(cc_if, chid, cdid, ck, name, name_length); ++ cc_add(mem_ctx, cc_if, chid, cdid, ck, name, name_length); + } + DWC_MUTEX_UNLOCK(cc_if->mutex); + +@@ -504,3 +528,5 @@ + + return retval; + } ++ ++#endif /* DWC_CCLIB */ +Index: linux-3.2.46/drivers/usb/host/dwc_common_port/dwc_cc.h +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_common_port/dwc_cc.h 2013-07-26 19:31:19.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_common_port/dwc_cc.h 2013-07-26 19:34:39.000000000 +0000 +@@ -1,8 +1,8 @@ + /* ========================================================================= +- * $File: //dwh/usb_iip/dev/software/dwc_common_port/dwc_cc.h $ +- * $Revision: #1 $ +- * $Date: 2008/12/21 $ +- * $Change: 1156609 $ ++ * $File: //dwh/usb_iip/dev/software/dwc_common_port_2/dwc_cc.h $ ++ * $Revision: #4 $ ++ * $Date: 2010/09/28 $ ++ * $Change: 1596182 $ + * + * Synopsys Portability Library Software and documentation + * (hereinafter, "Software") is an Unsupported proprietary work of +@@ -36,6 +36,10 @@ + #ifndef _DWC_CC_H_ + #define _DWC_CC_H_ + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ + /** @file + * + * This file defines the Context Context library. +@@ -69,14 +73,15 @@ + /** This function allocates memory for a dwc_cc_if_t structure, initializes + * fields to default values, and returns a pointer to the structure or NULL on + * error. */ +-extern dwc_cc_if_t *dwc_cc_if_alloc(dwc_notifier_t *notifier, unsigned is_host); ++extern dwc_cc_if_t *dwc_cc_if_alloc(void *mem_ctx, void *mtx_ctx, ++ dwc_notifier_t *notifier, unsigned is_host); + + /** Frees the memory for the specified CC structure allocated from + * dwc_cc_if_alloc(). */ +-extern void dwc_cc_if_free(dwc_cc_if_t *cc_if); ++extern void dwc_cc_if_free(void *mem_ctx, void *mtx_ctx, dwc_cc_if_t *cc_if); + + /** Removes all contexts from the connection context list */ +-extern void dwc_cc_clear(dwc_cc_if_t *cc_if); ++extern void dwc_cc_clear(void *mem_ctx, dwc_cc_if_t *cc_if); + + /** Adds a connection context (CHID, CK, CDID, Name) to the connection context list. + * If a CHID already exists, the CK and name are overwritten. Statistics are +@@ -91,7 +96,9 @@ + * @param length The length othe unicode string. + * @return A unique identifier used to refer to this context that is valid for + * as long as this context is still in the list. */ +-extern int32_t dwc_cc_add(dwc_cc_if_t *cc_if, uint8_t *chid, uint8_t *cdid, uint8_t *ck, uint8_t *name, uint8_t length); ++extern int32_t dwc_cc_add(void *mem_ctx, dwc_cc_if_t *cc_if, uint8_t *chid, ++ uint8_t *cdid, uint8_t *ck, uint8_t *name, ++ uint8_t length); + + /** Changes the CHID, CK, CDID, or Name values of a connection context in the + * list, preserving any accumulated statistics. This would typically be called +@@ -107,12 +114,14 @@ + * indicates no change. + * @param name Host friendly name UTF16-LE. NULL indicates no change. + * @param length Length of name. */ +-extern void dwc_cc_change(dwc_cc_if_t *cc_if, int32_t id, uint8_t *chid, uint8_t *cdid, uint8_t *ck, uint8_t *name, uint8_t length); ++extern void dwc_cc_change(void *mem_ctx, dwc_cc_if_t *cc_if, int32_t id, ++ uint8_t *chid, uint8_t *cdid, uint8_t *ck, ++ uint8_t *name, uint8_t length); + + /** Remove the specified connection context. + * @param cc_if The cc_if structure. + * @param id The identifier of the connection context to remove. */ +-extern void dwc_cc_remove(dwc_cc_if_t *cc_if, int32_t id); ++extern void dwc_cc_remove(void *mem_ctx, dwc_cc_if_t *cc_if, int32_t id); + + /** Get a binary block of data for the connection context list and attributes. + * This data can be used by the OS specific driver to save the connection +@@ -120,8 +129,10 @@ + * + * @param cc_if The cc_if structure. + * @param length Return the length of the data buffer. +- * @return A pointer to the data buffer. The memory for this buffer should be freed with DWC_FREE() after use. */ +-extern uint8_t *dwc_cc_data_for_save(dwc_cc_if_t *cc_if, unsigned int *length); ++ * @return A pointer to the data buffer. The memory for this buffer should be ++ * freed with DWC_FREE() after use. */ ++extern uint8_t *dwc_cc_data_for_save(void *mem_ctx, dwc_cc_if_t *cc_if, ++ unsigned int *length); + + /** Restore the connection context list from the binary data that was previously + * returned from a call to dwc_cc_data_for_save. This can be used by the OS specific +@@ -130,7 +141,8 @@ + * @param cc_if The cc_if structure. + * @param data The data bytes as returned from dwc_cc_data_for_save. + * @param length The length of the data. */ +-extern void dwc_cc_restore_from_data(dwc_cc_if_t *cc_if, uint8_t *data, unsigned int length); ++extern void dwc_cc_restore_from_data(void *mem_ctx, dwc_cc_if_t *cc_if, ++ uint8_t *data, unsigned int length); + + /** Find the connection context from the specified CHID. + * +@@ -205,5 +217,9 @@ + + /** @} */ + ++#ifdef __cplusplus ++} ++#endif ++ + #endif /* _DWC_CC_H_ */ + +Index: linux-3.2.46/drivers/usb/host/dwc_common_port/dwc_common_fbsd.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_common_port/dwc_common_fbsd.c 2013-07-26 19:34:39.000000000 +0000 +@@ -0,0 +1,1308 @@ ++#include "dwc_os.h" ++#include "dwc_list.h" ++ ++#ifdef DWC_CCLIB ++# include "dwc_cc.h" ++#endif ++ ++#ifdef DWC_CRYPTOLIB ++# include "dwc_modpow.h" ++# include "dwc_dh.h" ++# include "dwc_crypto.h" ++#endif ++ ++#ifdef DWC_NOTIFYLIB ++# include "dwc_notifier.h" ++#endif ++ ++/* OS-Level Implementations */ ++ ++/* This is the FreeBSD 7.0 kernel implementation of the DWC platform library. */ ++ ++ ++/* MISC */ ++ ++void *DWC_MEMSET(void *dest, uint8_t byte, uint32_t size) ++{ ++ return memset(dest, byte, size); ++} ++ ++void *DWC_MEMCPY(void *dest, void const *src, uint32_t size) ++{ ++ return memcpy(dest, src, size); ++} ++ ++void *DWC_MEMMOVE(void *dest, void *src, uint32_t size) ++{ ++ bcopy(src, dest, size); ++ return dest; ++} ++ ++int DWC_MEMCMP(void *m1, void *m2, uint32_t size) ++{ ++ return memcmp(m1, m2, size); ++} ++ ++int DWC_STRNCMP(void *s1, void *s2, uint32_t size) ++{ ++ return strncmp(s1, s2, size); ++} ++ ++int DWC_STRCMP(void *s1, void *s2) ++{ ++ return strcmp(s1, s2); ++} ++ ++int DWC_STRLEN(char const *str) ++{ ++ return strlen(str); ++} ++ ++char *DWC_STRCPY(char *to, char const *from) ++{ ++ return strcpy(to, from); ++} ++ ++char *DWC_STRDUP(char const *str) ++{ ++ int len = DWC_STRLEN(str) + 1; ++ char *new = DWC_ALLOC_ATOMIC(len); ++ ++ if (!new) { ++ return NULL; ++ } ++ ++ DWC_MEMCPY(new, str, len); ++ return new; ++} ++ ++int DWC_ATOI(char *str, int32_t *value) ++{ ++ char *end = NULL; ++ ++ *value = strtol(str, &end, 0); ++ if (*end == '\0') { ++ return 0; ++ } ++ ++ return -1; ++} ++ ++int DWC_ATOUI(char *str, uint32_t *value) ++{ ++ char *end = NULL; ++ ++ *value = strtoul(str, &end, 0); ++ if (*end == '\0') { ++ return 0; ++ } ++ ++ return -1; ++} ++ ++ ++#ifdef DWC_UTFLIB ++/* From usbstring.c */ ++ ++int DWC_UTF8_TO_UTF16LE(uint8_t const *s, uint16_t *cp, unsigned len) ++{ ++ int count = 0; ++ u8 c; ++ u16 uchar; ++ ++ /* this insists on correct encodings, though not minimal ones. ++ * BUT it currently rejects legit 4-byte UTF-8 code points, ++ * which need surrogate pairs. (Unicode 3.1 can use them.) ++ */ ++ while (len != 0 && (c = (u8) *s++) != 0) { ++ if (unlikely(c & 0x80)) { ++ // 2-byte sequence: ++ // 00000yyyyyxxxxxx = 110yyyyy 10xxxxxx ++ if ((c & 0xe0) == 0xc0) { ++ uchar = (c & 0x1f) << 6; ++ ++ c = (u8) *s++; ++ if ((c & 0xc0) != 0xc0) ++ goto fail; ++ c &= 0x3f; ++ uchar |= c; ++ ++ // 3-byte sequence (most CJKV characters): ++ // zzzzyyyyyyxxxxxx = 1110zzzz 10yyyyyy 10xxxxxx ++ } else if ((c & 0xf0) == 0xe0) { ++ uchar = (c & 0x0f) << 12; ++ ++ c = (u8) *s++; ++ if ((c & 0xc0) != 0xc0) ++ goto fail; ++ c &= 0x3f; ++ uchar |= c << 6; ++ ++ c = (u8) *s++; ++ if ((c & 0xc0) != 0xc0) ++ goto fail; ++ c &= 0x3f; ++ uchar |= c; ++ ++ /* no bogus surrogates */ ++ if (0xd800 <= uchar && uchar <= 0xdfff) ++ goto fail; ++ ++ // 4-byte sequence (surrogate pairs, currently rare): ++ // 11101110wwwwzzzzyy + 110111yyyyxxxxxx ++ // = 11110uuu 10uuzzzz 10yyyyyy 10xxxxxx ++ // (uuuuu = wwww + 1) ++ // FIXME accept the surrogate code points (only) ++ } else ++ goto fail; ++ } else ++ uchar = c; ++ put_unaligned (cpu_to_le16 (uchar), cp++); ++ count++; ++ len--; ++ } ++ return count; ++fail: ++ return -1; ++} ++ ++#endif /* DWC_UTFLIB */ ++ ++ ++/* dwc_debug.h */ ++ ++dwc_bool_t DWC_IN_IRQ(void) ++{ ++// return in_irq(); ++ return 0; ++} ++ ++dwc_bool_t DWC_IN_BH(void) ++{ ++// return in_softirq(); ++ return 0; ++} ++ ++void DWC_VPRINTF(char *format, va_list args) ++{ ++ vprintf(format, args); ++} ++ ++int DWC_VSNPRINTF(char *str, int size, char *format, va_list args) ++{ ++ return vsnprintf(str, size, format, args); ++} ++ ++void DWC_PRINTF(char *format, ...) ++{ ++ va_list args; ++ ++ va_start(args, format); ++ DWC_VPRINTF(format, args); ++ va_end(args); ++} ++ ++int DWC_SPRINTF(char *buffer, char *format, ...) ++{ ++ int retval; ++ va_list args; ++ ++ va_start(args, format); ++ retval = vsprintf(buffer, format, args); ++ va_end(args); ++ return retval; ++} ++ ++int DWC_SNPRINTF(char *buffer, int size, char *format, ...) ++{ ++ int retval; ++ va_list args; ++ ++ va_start(args, format); ++ retval = vsnprintf(buffer, size, format, args); ++ va_end(args); ++ return retval; ++} ++ ++void __DWC_WARN(char *format, ...) ++{ ++ va_list args; ++ ++ va_start(args, format); ++ DWC_VPRINTF(format, args); ++ va_end(args); ++} ++ ++void __DWC_ERROR(char *format, ...) ++{ ++ va_list args; ++ ++ va_start(args, format); ++ DWC_VPRINTF(format, args); ++ va_end(args); ++} ++ ++void DWC_EXCEPTION(char *format, ...) ++{ ++ va_list args; ++ ++ va_start(args, format); ++ DWC_VPRINTF(format, args); ++ va_end(args); ++// BUG_ON(1); ??? ++} ++ ++#ifdef DEBUG ++void __DWC_DEBUG(char *format, ...) ++{ ++ va_list args; ++ ++ va_start(args, format); ++ DWC_VPRINTF(format, args); ++ va_end(args); ++} ++#endif ++ ++ ++/* dwc_mem.h */ ++ ++#if 0 ++dwc_pool_t *DWC_DMA_POOL_CREATE(uint32_t size, ++ uint32_t align, ++ uint32_t alloc) ++{ ++ struct dma_pool *pool = dma_pool_create("Pool", NULL, ++ size, align, alloc); ++ return (dwc_pool_t *)pool; ++} ++ ++void DWC_DMA_POOL_DESTROY(dwc_pool_t *pool) ++{ ++ dma_pool_destroy((struct dma_pool *)pool); ++} ++ ++void *DWC_DMA_POOL_ALLOC(dwc_pool_t *pool, uint64_t *dma_addr) ++{ ++// return dma_pool_alloc((struct dma_pool *)pool, GFP_KERNEL, dma_addr); ++ return dma_pool_alloc((struct dma_pool *)pool, M_WAITOK, dma_addr); ++} ++ ++void *DWC_DMA_POOL_ZALLOC(dwc_pool_t *pool, uint64_t *dma_addr) ++{ ++ void *vaddr = DWC_DMA_POOL_ALLOC(pool, dma_addr); ++ memset(..); ++} ++ ++void DWC_DMA_POOL_FREE(dwc_pool_t *pool, void *vaddr, void *daddr) ++{ ++ dma_pool_free(pool, vaddr, daddr); ++} ++#endif ++ ++static void dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) ++{ ++ if (error) ++ return; ++ *(bus_addr_t *)arg = segs[0].ds_addr; ++} ++ ++void *__DWC_DMA_ALLOC(void *dma_ctx, uint32_t size, dwc_dma_t *dma_addr) ++{ ++ dwc_dmactx_t *dma = (dwc_dmactx_t *)dma_ctx; ++ int error; ++ ++ error = bus_dma_tag_create( ++#if __FreeBSD_version >= 700000 ++ bus_get_dma_tag(dma->dev), /* parent */ ++#else ++ NULL, /* parent */ ++#endif ++ 4, 0, /* alignment, bounds */ ++ BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ ++ BUS_SPACE_MAXADDR, /* highaddr */ ++ NULL, NULL, /* filter, filterarg */ ++ size, /* maxsize */ ++ 1, /* nsegments */ ++ size, /* maxsegsize */ ++ 0, /* flags */ ++ NULL, /* lockfunc */ ++ NULL, /* lockarg */ ++ &dma->dma_tag); ++ if (error) { ++ device_printf(dma->dev, "%s: bus_dma_tag_create failed: %d\n", ++ __func__, error); ++ goto fail_0; ++ } ++ ++ error = bus_dmamem_alloc(dma->dma_tag, &dma->dma_vaddr, ++ BUS_DMA_NOWAIT | BUS_DMA_COHERENT, &dma->dma_map); ++ if (error) { ++ device_printf(dma->dev, "%s: bus_dmamem_alloc(%ju) failed: %d\n", ++ __func__, (uintmax_t)size, error); ++ goto fail_1; ++ } ++ ++ dma->dma_paddr = 0; ++ error = bus_dmamap_load(dma->dma_tag, dma->dma_map, dma->dma_vaddr, size, ++ dmamap_cb, &dma->dma_paddr, BUS_DMA_NOWAIT); ++ if (error || dma->dma_paddr == 0) { ++ device_printf(dma->dev, "%s: bus_dmamap_load failed: %d\n", ++ __func__, error); ++ goto fail_2; ++ } ++ ++ *dma_addr = dma->dma_paddr; ++ return dma->dma_vaddr; ++ ++fail_2: ++ bus_dmamap_unload(dma->dma_tag, dma->dma_map); ++fail_1: ++ bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); ++ bus_dma_tag_destroy(dma->dma_tag); ++fail_0: ++ dma->dma_map = NULL; ++ dma->dma_tag = NULL; ++ ++ return NULL; ++} ++ ++void __DWC_DMA_FREE(void *dma_ctx, uint32_t size, void *virt_addr, dwc_dma_t dma_addr) ++{ ++ dwc_dmactx_t *dma = (dwc_dmactx_t *)dma_ctx; ++ ++ if (dma->dma_tag == NULL) ++ return; ++ if (dma->dma_map != NULL) { ++ bus_dmamap_sync(dma->dma_tag, dma->dma_map, ++ BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); ++ bus_dmamap_unload(dma->dma_tag, dma->dma_map); ++ bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); ++ dma->dma_map = NULL; ++ } ++ ++ bus_dma_tag_destroy(dma->dma_tag); ++ dma->dma_tag = NULL; ++} ++ ++void *__DWC_ALLOC(void *mem_ctx, uint32_t size) ++{ ++ return malloc(size, M_DEVBUF, M_WAITOK | M_ZERO); ++} ++ ++void *__DWC_ALLOC_ATOMIC(void *mem_ctx, uint32_t size) ++{ ++ return malloc(size, M_DEVBUF, M_NOWAIT | M_ZERO); ++} ++ ++void __DWC_FREE(void *mem_ctx, void *addr) ++{ ++ free(addr, M_DEVBUF); ++} ++ ++ ++#ifdef DWC_CRYPTOLIB ++/* dwc_crypto.h */ ++ ++void DWC_RANDOM_BYTES(uint8_t *buffer, uint32_t length) ++{ ++ get_random_bytes(buffer, length); ++} ++ ++int DWC_AES_CBC(uint8_t *message, uint32_t messagelen, uint8_t *key, uint32_t keylen, uint8_t iv[16], uint8_t *out) ++{ ++ struct crypto_blkcipher *tfm; ++ struct blkcipher_desc desc; ++ struct scatterlist sgd; ++ struct scatterlist sgs; ++ ++ tfm = crypto_alloc_blkcipher("cbc(aes)", 0, CRYPTO_ALG_ASYNC); ++ if (tfm == NULL) { ++ printk("failed to load transform for aes CBC\n"); ++ return -1; ++ } ++ ++ crypto_blkcipher_setkey(tfm, key, keylen); ++ crypto_blkcipher_set_iv(tfm, iv, 16); ++ ++ sg_init_one(&sgd, out, messagelen); ++ sg_init_one(&sgs, message, messagelen); ++ ++ desc.tfm = tfm; ++ desc.flags = 0; ++ ++ if (crypto_blkcipher_encrypt(&desc, &sgd, &sgs, messagelen)) { ++ crypto_free_blkcipher(tfm); ++ DWC_ERROR("AES CBC encryption failed"); ++ return -1; ++ } ++ ++ crypto_free_blkcipher(tfm); ++ return 0; ++} ++ ++int DWC_SHA256(uint8_t *message, uint32_t len, uint8_t *out) ++{ ++ struct crypto_hash *tfm; ++ struct hash_desc desc; ++ struct scatterlist sg; ++ ++ tfm = crypto_alloc_hash("sha256", 0, CRYPTO_ALG_ASYNC); ++ if (IS_ERR(tfm)) { ++ DWC_ERROR("Failed to load transform for sha256: %ld", PTR_ERR(tfm)); ++ return 0; ++ } ++ desc.tfm = tfm; ++ desc.flags = 0; ++ ++ sg_init_one(&sg, message, len); ++ crypto_hash_digest(&desc, &sg, len, out); ++ crypto_free_hash(tfm); ++ ++ return 1; ++} ++ ++int DWC_HMAC_SHA256(uint8_t *message, uint32_t messagelen, ++ uint8_t *key, uint32_t keylen, uint8_t *out) ++{ ++ struct crypto_hash *tfm; ++ struct hash_desc desc; ++ struct scatterlist sg; ++ ++ tfm = crypto_alloc_hash("hmac(sha256)", 0, CRYPTO_ALG_ASYNC); ++ if (IS_ERR(tfm)) { ++ DWC_ERROR("Failed to load transform for hmac(sha256): %ld", PTR_ERR(tfm)); ++ return 0; ++ } ++ desc.tfm = tfm; ++ desc.flags = 0; ++ ++ sg_init_one(&sg, message, messagelen); ++ crypto_hash_setkey(tfm, key, keylen); ++ crypto_hash_digest(&desc, &sg, messagelen, out); ++ crypto_free_hash(tfm); ++ ++ return 1; ++} ++ ++#endif /* DWC_CRYPTOLIB */ ++ ++ ++/* Byte Ordering Conversions */ ++ ++uint32_t DWC_CPU_TO_LE32(uint32_t *p) ++{ ++#ifdef __LITTLE_ENDIAN ++ return *p; ++#else ++ uint8_t *u_p = (uint8_t *)p; ++ ++ return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24)); ++#endif ++} ++ ++uint32_t DWC_CPU_TO_BE32(uint32_t *p) ++{ ++#ifdef __BIG_ENDIAN ++ return *p; ++#else ++ uint8_t *u_p = (uint8_t *)p; ++ ++ return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24)); ++#endif ++} ++ ++uint32_t DWC_LE32_TO_CPU(uint32_t *p) ++{ ++#ifdef __LITTLE_ENDIAN ++ return *p; ++#else ++ uint8_t *u_p = (uint8_t *)p; ++ ++ return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24)); ++#endif ++} ++ ++uint32_t DWC_BE32_TO_CPU(uint32_t *p) ++{ ++#ifdef __BIG_ENDIAN ++ return *p; ++#else ++ uint8_t *u_p = (uint8_t *)p; ++ ++ return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24)); ++#endif ++} ++ ++uint16_t DWC_CPU_TO_LE16(uint16_t *p) ++{ ++#ifdef __LITTLE_ENDIAN ++ return *p; ++#else ++ uint8_t *u_p = (uint8_t *)p; ++ return (u_p[1] | (u_p[0] << 8)); ++#endif ++} ++ ++uint16_t DWC_CPU_TO_BE16(uint16_t *p) ++{ ++#ifdef __BIG_ENDIAN ++ return *p; ++#else ++ uint8_t *u_p = (uint8_t *)p; ++ return (u_p[1] | (u_p[0] << 8)); ++#endif ++} ++ ++uint16_t DWC_LE16_TO_CPU(uint16_t *p) ++{ ++#ifdef __LITTLE_ENDIAN ++ return *p; ++#else ++ uint8_t *u_p = (uint8_t *)p; ++ return (u_p[1] | (u_p[0] << 8)); ++#endif ++} ++ ++uint16_t DWC_BE16_TO_CPU(uint16_t *p) ++{ ++#ifdef __BIG_ENDIAN ++ return *p; ++#else ++ uint8_t *u_p = (uint8_t *)p; ++ return (u_p[1] | (u_p[0] << 8)); ++#endif ++} ++ ++ ++/* Registers */ ++ ++uint32_t DWC_READ_REG32(void *io_ctx, uint32_t volatile *reg) ++{ ++ dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx; ++ bus_size_t ior = (bus_size_t)reg; ++ ++ return bus_space_read_4(io->iot, io->ioh, ior); ++} ++ ++#if 0 ++uint64_t DWC_READ_REG64(void *io_ctx, uint64_t volatile *reg) ++{ ++ dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx; ++ bus_size_t ior = (bus_size_t)reg; ++ ++ return bus_space_read_8(io->iot, io->ioh, ior); ++} ++#endif ++ ++void DWC_WRITE_REG32(void *io_ctx, uint32_t volatile *reg, uint32_t value) ++{ ++ dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx; ++ bus_size_t ior = (bus_size_t)reg; ++ ++ bus_space_write_4(io->iot, io->ioh, ior, value); ++} ++ ++#if 0 ++void DWC_WRITE_REG64(void *io_ctx, uint64_t volatile *reg, uint64_t value) ++{ ++ dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx; ++ bus_size_t ior = (bus_size_t)reg; ++ ++ bus_space_write_8(io->iot, io->ioh, ior, value); ++} ++#endif ++ ++void DWC_MODIFY_REG32(void *io_ctx, uint32_t volatile *reg, uint32_t clear_mask, ++ uint32_t set_mask) ++{ ++ dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx; ++ bus_size_t ior = (bus_size_t)reg; ++ ++ bus_space_write_4(io->iot, io->ioh, ior, ++ (bus_space_read_4(io->iot, io->ioh, ior) & ++ ~clear_mask) | set_mask); ++} ++ ++#if 0 ++void DWC_MODIFY_REG64(void *io_ctx, uint64_t volatile *reg, uint64_t clear_mask, ++ uint64_t set_mask) ++{ ++ dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx; ++ bus_size_t ior = (bus_size_t)reg; ++ ++ bus_space_write_8(io->iot, io->ioh, ior, ++ (bus_space_read_8(io->iot, io->ioh, ior) & ++ ~clear_mask) | set_mask); ++} ++#endif ++ ++ ++/* Locking */ ++ ++dwc_spinlock_t *DWC_SPINLOCK_ALLOC(void) ++{ ++ struct mtx *sl = DWC_ALLOC(sizeof(*sl)); ++ ++ if (!sl) { ++ DWC_ERROR("Cannot allocate memory for spinlock"); ++ return NULL; ++ } ++ ++ mtx_init(sl, "dw3spn", NULL, MTX_SPIN); ++ return (dwc_spinlock_t *)sl; ++} ++ ++void DWC_SPINLOCK_FREE(dwc_spinlock_t *lock) ++{ ++ struct mtx *sl = (struct mtx *)lock; ++ ++ mtx_destroy(sl); ++ DWC_FREE(sl); ++} ++ ++void DWC_SPINLOCK(dwc_spinlock_t *lock) ++{ ++ mtx_lock_spin((struct mtx *)lock); // ??? ++} ++ ++void DWC_SPINUNLOCK(dwc_spinlock_t *lock) ++{ ++ mtx_unlock_spin((struct mtx *)lock); // ??? ++} ++ ++void DWC_SPINLOCK_IRQSAVE(dwc_spinlock_t *lock, dwc_irqflags_t *flags) ++{ ++ mtx_lock_spin((struct mtx *)lock); ++} ++ ++void DWC_SPINUNLOCK_IRQRESTORE(dwc_spinlock_t *lock, dwc_irqflags_t flags) ++{ ++ mtx_unlock_spin((struct mtx *)lock); ++} ++ ++dwc_mutex_t *DWC_MUTEX_ALLOC(void) ++{ ++ struct mtx *m; ++ dwc_mutex_t *mutex = (dwc_mutex_t *)DWC_ALLOC(sizeof(struct mtx)); ++ ++ if (!mutex) { ++ DWC_ERROR("Cannot allocate memory for mutex"); ++ return NULL; ++ } ++ ++ m = (struct mtx *)mutex; ++ mtx_init(m, "dw3mtx", NULL, MTX_DEF); ++ return mutex; ++} ++ ++#if (defined(DWC_LINUX) && defined(CONFIG_DEBUG_MUTEXES)) ++#else ++void DWC_MUTEX_FREE(dwc_mutex_t *mutex) ++{ ++ mtx_destroy((struct mtx *)mutex); ++ DWC_FREE(mutex); ++} ++#endif ++ ++void DWC_MUTEX_LOCK(dwc_mutex_t *mutex) ++{ ++ struct mtx *m = (struct mtx *)mutex; ++ ++ mtx_lock(m); ++} ++ ++int DWC_MUTEX_TRYLOCK(dwc_mutex_t *mutex) ++{ ++ struct mtx *m = (struct mtx *)mutex; ++ ++ return mtx_trylock(m); ++} ++ ++void DWC_MUTEX_UNLOCK(dwc_mutex_t *mutex) ++{ ++ struct mtx *m = (struct mtx *)mutex; ++ ++ mtx_unlock(m); ++} ++ ++ ++/* Timing */ ++ ++void DWC_UDELAY(uint32_t usecs) ++{ ++ DELAY(usecs); ++} ++ ++void DWC_MDELAY(uint32_t msecs) ++{ ++ do { ++ DELAY(1000); ++ } while (--msecs); ++} ++ ++void DWC_MSLEEP(uint32_t msecs) ++{ ++ struct timeval tv; ++ ++ tv.tv_sec = msecs / 1000; ++ tv.tv_usec = (msecs - tv.tv_sec * 1000) * 1000; ++ pause("dw3slp", tvtohz(&tv)); ++} ++ ++uint32_t DWC_TIME(void) ++{ ++ struct timeval tv; ++ ++ microuptime(&tv); // or getmicrouptime? (less precise, but faster) ++ return tv.tv_sec * 1000 + tv.tv_usec / 1000; ++} ++ ++ ++/* Timers */ ++ ++struct dwc_timer { ++ struct callout t; ++ char *name; ++ dwc_spinlock_t *lock; ++ dwc_timer_callback_t cb; ++ void *data; ++}; ++ ++dwc_timer_t *DWC_TIMER_ALLOC(char *name, dwc_timer_callback_t cb, void *data) ++{ ++ dwc_timer_t *t = DWC_ALLOC(sizeof(*t)); ++ ++ if (!t) { ++ DWC_ERROR("Cannot allocate memory for timer"); ++ return NULL; ++ } ++ ++ callout_init(&t->t, 1); ++ ++ t->name = DWC_STRDUP(name); ++ if (!t->name) { ++ DWC_ERROR("Cannot allocate memory for timer->name"); ++ goto no_name; ++ } ++ ++ t->lock = DWC_SPINLOCK_ALLOC(); ++ if (!t->lock) { ++ DWC_ERROR("Cannot allocate memory for lock"); ++ goto no_lock; ++ } ++ ++ t->cb = cb; ++ t->data = data; ++ ++ return t; ++ ++ no_lock: ++ DWC_FREE(t->name); ++ no_name: ++ DWC_FREE(t); ++ ++ return NULL; ++} ++ ++void DWC_TIMER_FREE(dwc_timer_t *timer) ++{ ++ callout_stop(&timer->t); ++ DWC_SPINLOCK_FREE(timer->lock); ++ DWC_FREE(timer->name); ++ DWC_FREE(timer); ++} ++ ++void DWC_TIMER_SCHEDULE(dwc_timer_t *timer, uint32_t time) ++{ ++ struct timeval tv; ++ ++ tv.tv_sec = time / 1000; ++ tv.tv_usec = (time - tv.tv_sec * 1000) * 1000; ++ callout_reset(&timer->t, tvtohz(&tv), timer->cb, timer->data); ++} ++ ++void DWC_TIMER_CANCEL(dwc_timer_t *timer) ++{ ++ callout_stop(&timer->t); ++} ++ ++ ++/* Wait Queues */ ++ ++struct dwc_waitq { ++ struct mtx lock; ++ int abort; ++}; ++ ++dwc_waitq_t *DWC_WAITQ_ALLOC(void) ++{ ++ dwc_waitq_t *wq = DWC_ALLOC(sizeof(*wq)); ++ ++ if (!wq) { ++ DWC_ERROR("Cannot allocate memory for waitqueue"); ++ return NULL; ++ } ++ ++ mtx_init(&wq->lock, "dw3wtq", NULL, MTX_DEF); ++ wq->abort = 0; ++ ++ return wq; ++} ++ ++void DWC_WAITQ_FREE(dwc_waitq_t *wq) ++{ ++ mtx_destroy(&wq->lock); ++ DWC_FREE(wq); ++} ++ ++int32_t DWC_WAITQ_WAIT(dwc_waitq_t *wq, dwc_waitq_condition_t cond, void *data) ++{ ++// intrmask_t ipl; ++ int result = 0; ++ ++ mtx_lock(&wq->lock); ++// ipl = splbio(); ++ ++ /* Skip the sleep if already aborted or triggered */ ++ if (!wq->abort && !cond(data)) { ++// splx(ipl); ++ result = msleep(wq, &wq->lock, PCATCH, "dw3wat", 0); // infinite timeout ++// ipl = splbio(); ++ } ++ ++ if (result == ERESTART) { // signaled - restart ++ result = -DWC_E_RESTART; ++ ++ } else if (result == EINTR) { // signaled - interrupt ++ result = -DWC_E_ABORT; ++ ++ } else if (wq->abort) { ++ result = -DWC_E_ABORT; ++ ++ } else { ++ result = 0; ++ } ++ ++ wq->abort = 0; ++// splx(ipl); ++ mtx_unlock(&wq->lock); ++ return result; ++} ++ ++int32_t DWC_WAITQ_WAIT_TIMEOUT(dwc_waitq_t *wq, dwc_waitq_condition_t cond, ++ void *data, int32_t msecs) ++{ ++ struct timeval tv, tv1, tv2; ++// intrmask_t ipl; ++ int result = 0; ++ ++ tv.tv_sec = msecs / 1000; ++ tv.tv_usec = (msecs - tv.tv_sec * 1000) * 1000; ++ ++ mtx_lock(&wq->lock); ++// ipl = splbio(); ++ ++ /* Skip the sleep if already aborted or triggered */ ++ if (!wq->abort && !cond(data)) { ++// splx(ipl); ++ getmicrouptime(&tv1); ++ result = msleep(wq, &wq->lock, PCATCH, "dw3wto", tvtohz(&tv)); ++ getmicrouptime(&tv2); ++// ipl = splbio(); ++ } ++ ++ if (result == 0) { // awoken ++ if (wq->abort) { ++ result = -DWC_E_ABORT; ++ } else { ++ tv2.tv_usec -= tv1.tv_usec; ++ if (tv2.tv_usec < 0) { ++ tv2.tv_usec += 1000000; ++ tv2.tv_sec--; ++ } ++ ++ tv2.tv_sec -= tv1.tv_sec; ++ result = tv2.tv_sec * 1000 + tv2.tv_usec / 1000; ++ result = msecs - result; ++ if (result <= 0) ++ result = 1; ++ } ++ } else if (result == ERESTART) { // signaled - restart ++ result = -DWC_E_RESTART; ++ ++ } else if (result == EINTR) { // signaled - interrupt ++ result = -DWC_E_ABORT; ++ ++ } else { // timed out ++ result = -DWC_E_TIMEOUT; ++ } ++ ++ wq->abort = 0; ++// splx(ipl); ++ mtx_unlock(&wq->lock); ++ return result; ++} ++ ++void DWC_WAITQ_TRIGGER(dwc_waitq_t *wq) ++{ ++ wakeup(wq); ++} ++ ++void DWC_WAITQ_ABORT(dwc_waitq_t *wq) ++{ ++// intrmask_t ipl; ++ ++ mtx_lock(&wq->lock); ++// ipl = splbio(); ++ wq->abort = 1; ++ wakeup(wq); ++// splx(ipl); ++ mtx_unlock(&wq->lock); ++} ++ ++ ++/* Threading */ ++ ++struct dwc_thread { ++ struct proc *proc; ++ int abort; ++}; ++ ++dwc_thread_t *DWC_THREAD_RUN(dwc_thread_function_t func, char *name, void *data) ++{ ++ int retval; ++ dwc_thread_t *thread = DWC_ALLOC(sizeof(*thread)); ++ ++ if (!thread) { ++ return NULL; ++ } ++ ++ thread->abort = 0; ++ retval = kthread_create((void (*)(void *))func, data, &thread->proc, ++ RFPROC | RFNOWAIT, 0, "%s", name); ++ if (retval) { ++ DWC_FREE(thread); ++ return NULL; ++ } ++ ++ return thread; ++} ++ ++int DWC_THREAD_STOP(dwc_thread_t *thread) ++{ ++ int retval; ++ ++ thread->abort = 1; ++ retval = tsleep(&thread->abort, 0, "dw3stp", 60 * hz); ++ ++ if (retval == 0) { ++ /* DWC_THREAD_EXIT() will free the thread struct */ ++ return 0; ++ } ++ ++ /* NOTE: We leak the thread struct if thread doesn't die */ ++ ++ if (retval == EWOULDBLOCK) { ++ return -DWC_E_TIMEOUT; ++ } ++ ++ return -DWC_E_UNKNOWN; ++} ++ ++dwc_bool_t DWC_THREAD_SHOULD_STOP(dwc_thread_t *thread) ++{ ++ return thread->abort; ++} ++ ++void DWC_THREAD_EXIT(dwc_thread_t *thread) ++{ ++ wakeup(&thread->abort); ++ DWC_FREE(thread); ++ kthread_exit(0); ++} ++ ++ ++/* tasklets ++ - Runs in interrupt context (cannot sleep) ++ - Each tasklet runs on a single CPU [ How can we ensure this on FreeBSD? Does it matter? ] ++ - Different tasklets can be running simultaneously on different CPUs [ shouldn't matter ] ++ */ ++struct dwc_tasklet { ++ struct task t; ++ dwc_tasklet_callback_t cb; ++ void *data; ++}; ++ ++static void tasklet_callback(void *data, int pending) // what to do with pending ??? ++{ ++ dwc_tasklet_t *task = (dwc_tasklet_t *)data; ++ ++ task->cb(task->data); ++} ++ ++dwc_tasklet_t *DWC_TASK_ALLOC(char *name, dwc_tasklet_callback_t cb, void *data) ++{ ++ dwc_tasklet_t *task = DWC_ALLOC(sizeof(*task)); ++ ++ if (task) { ++ task->cb = cb; ++ task->data = data; ++ TASK_INIT(&task->t, 0, tasklet_callback, task); ++ } else { ++ DWC_ERROR("Cannot allocate memory for tasklet"); ++ } ++ ++ return task; ++} ++ ++void DWC_TASK_FREE(dwc_tasklet_t *task) ++{ ++ taskqueue_drain(taskqueue_fast, &task->t); // ??? ++ DWC_FREE(task); ++} ++ ++void DWC_TASK_SCHEDULE(dwc_tasklet_t *task) ++{ ++ /* Uses predefined system queue */ ++ taskqueue_enqueue_fast(taskqueue_fast, &task->t); ++} ++ ++ ++/* workqueues ++ - Runs in process context (can sleep) ++ */ ++typedef struct work_container { ++ dwc_work_callback_t cb; ++ void *data; ++ dwc_workq_t *wq; ++ char *name; ++ int hz; ++ ++#ifdef DEBUG ++ DWC_CIRCLEQ_ENTRY(work_container) entry; ++#endif ++ struct task task; ++} work_container_t; ++ ++#ifdef DEBUG ++DWC_CIRCLEQ_HEAD(work_container_queue, work_container); ++#endif ++ ++struct dwc_workq { ++ struct taskqueue *taskq; ++ dwc_spinlock_t *lock; ++ dwc_waitq_t *waitq; ++ int pending; ++ ++#ifdef DEBUG ++ struct work_container_queue entries; ++#endif ++}; ++ ++static void do_work(void *data, int pending) // what to do with pending ??? ++{ ++ work_container_t *container = (work_container_t *)data; ++ dwc_workq_t *wq = container->wq; ++ dwc_irqflags_t flags; ++ ++ if (container->hz) { ++ pause("dw3wrk", container->hz); ++ } ++ ++ container->cb(container->data); ++ DWC_DEBUG("Work done: %s, container=%p", container->name, container); ++ ++ DWC_SPINLOCK_IRQSAVE(wq->lock, &flags); ++ ++#ifdef DEBUG ++ DWC_CIRCLEQ_REMOVE(&wq->entries, container, entry); ++#endif ++ if (container->name) ++ DWC_FREE(container->name); ++ DWC_FREE(container); ++ wq->pending--; ++ DWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags); ++ DWC_WAITQ_TRIGGER(wq->waitq); ++} ++ ++static int work_done(void *data) ++{ ++ dwc_workq_t *workq = (dwc_workq_t *)data; ++ ++ return workq->pending == 0; ++} ++ ++int DWC_WORKQ_WAIT_WORK_DONE(dwc_workq_t *workq, int timeout) ++{ ++ return DWC_WAITQ_WAIT_TIMEOUT(workq->waitq, work_done, workq, timeout); ++} ++ ++dwc_workq_t *DWC_WORKQ_ALLOC(char *name) ++{ ++ dwc_workq_t *wq = DWC_ALLOC(sizeof(*wq)); ++ ++ if (!wq) { ++ DWC_ERROR("Cannot allocate memory for workqueue"); ++ return NULL; ++ } ++ ++ wq->taskq = taskqueue_create(name, M_NOWAIT, taskqueue_thread_enqueue, &wq->taskq); ++ if (!wq->taskq) { ++ DWC_ERROR("Cannot allocate memory for taskqueue"); ++ goto no_taskq; ++ } ++ ++ wq->pending = 0; ++ ++ wq->lock = DWC_SPINLOCK_ALLOC(); ++ if (!wq->lock) { ++ DWC_ERROR("Cannot allocate memory for spinlock"); ++ goto no_lock; ++ } ++ ++ wq->waitq = DWC_WAITQ_ALLOC(); ++ if (!wq->waitq) { ++ DWC_ERROR("Cannot allocate memory for waitqueue"); ++ goto no_waitq; ++ } ++ ++ taskqueue_start_threads(&wq->taskq, 1, PWAIT, "%s taskq", "dw3tsk"); ++ ++#ifdef DEBUG ++ DWC_CIRCLEQ_INIT(&wq->entries); ++#endif ++ return wq; ++ ++ no_waitq: ++ DWC_SPINLOCK_FREE(wq->lock); ++ no_lock: ++ taskqueue_free(wq->taskq); ++ no_taskq: ++ DWC_FREE(wq); ++ ++ return NULL; ++} ++ ++void DWC_WORKQ_FREE(dwc_workq_t *wq) ++{ ++#ifdef DEBUG ++ dwc_irqflags_t flags; ++ ++ DWC_SPINLOCK_IRQSAVE(wq->lock, &flags); ++ ++ if (wq->pending != 0) { ++ struct work_container *container; ++ ++ DWC_ERROR("Destroying work queue with pending work"); ++ ++ DWC_CIRCLEQ_FOREACH(container, &wq->entries, entry) { ++ DWC_ERROR("Work %s still pending", container->name); ++ } ++ } ++ ++ DWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags); ++#endif ++ DWC_WAITQ_FREE(wq->waitq); ++ DWC_SPINLOCK_FREE(wq->lock); ++ taskqueue_free(wq->taskq); ++ DWC_FREE(wq); ++} ++ ++void DWC_WORKQ_SCHEDULE(dwc_workq_t *wq, dwc_work_callback_t cb, void *data, ++ char *format, ...) ++{ ++ dwc_irqflags_t flags; ++ work_container_t *container; ++ static char name[128]; ++ va_list args; ++ ++ va_start(args, format); ++ DWC_VSNPRINTF(name, 128, format, args); ++ va_end(args); ++ ++ DWC_SPINLOCK_IRQSAVE(wq->lock, &flags); ++ wq->pending++; ++ DWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags); ++ DWC_WAITQ_TRIGGER(wq->waitq); ++ ++ container = DWC_ALLOC_ATOMIC(sizeof(*container)); ++ if (!container) { ++ DWC_ERROR("Cannot allocate memory for container"); ++ return; ++ } ++ ++ container->name = DWC_STRDUP(name); ++ if (!container->name) { ++ DWC_ERROR("Cannot allocate memory for container->name"); ++ DWC_FREE(container); ++ return; ++ } ++ ++ container->cb = cb; ++ container->data = data; ++ container->wq = wq; ++ container->hz = 0; ++ ++ DWC_DEBUG("Queueing work: %s, container=%p", container->name, container); ++ ++ TASK_INIT(&container->task, 0, do_work, container); ++ ++#ifdef DEBUG ++ DWC_CIRCLEQ_INSERT_TAIL(&wq->entries, container, entry); ++#endif ++ taskqueue_enqueue_fast(wq->taskq, &container->task); ++} ++ ++void DWC_WORKQ_SCHEDULE_DELAYED(dwc_workq_t *wq, dwc_work_callback_t cb, ++ void *data, uint32_t time, char *format, ...) ++{ ++ dwc_irqflags_t flags; ++ work_container_t *container; ++ static char name[128]; ++ struct timeval tv; ++ va_list args; ++ ++ va_start(args, format); ++ DWC_VSNPRINTF(name, 128, format, args); ++ va_end(args); ++ ++ DWC_SPINLOCK_IRQSAVE(wq->lock, &flags); ++ wq->pending++; ++ DWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags); ++ DWC_WAITQ_TRIGGER(wq->waitq); ++ ++ container = DWC_ALLOC_ATOMIC(sizeof(*container)); ++ if (!container) { ++ DWC_ERROR("Cannot allocate memory for container"); ++ return; ++ } ++ ++ container->name = DWC_STRDUP(name); ++ if (!container->name) { ++ DWC_ERROR("Cannot allocate memory for container->name"); ++ DWC_FREE(container); ++ return; ++ } ++ ++ container->cb = cb; ++ container->data = data; ++ container->wq = wq; ++ ++ tv.tv_sec = time / 1000; ++ tv.tv_usec = (time - tv.tv_sec * 1000) * 1000; ++ container->hz = tvtohz(&tv); ++ ++ DWC_DEBUG("Queueing work: %s, container=%p", container->name, container); ++ ++ TASK_INIT(&container->task, 0, do_work, container); ++ ++#ifdef DEBUG ++ DWC_CIRCLEQ_INSERT_TAIL(&wq->entries, container, entry); ++#endif ++ taskqueue_enqueue_fast(wq->taskq, &container->task); ++} ++ ++int DWC_WORKQ_PENDING(dwc_workq_t *wq) ++{ ++ return wq->pending; ++} +Index: linux-3.2.46/drivers/usb/host/dwc_common_port/dwc_common_linux.c +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_common_port/dwc_common_linux.c 2013-07-26 19:34:36.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_common_port/dwc_common_linux.c 2013-07-26 19:34:39.000000000 +0000 +@@ -1,80 +1,28 @@ +-#include "dwc_cc.h" +-#include "dwc_notifier.h" +- + #include + #include + #include + #include + +-MODULE_DESCRIPTION("DWC Common Library - Portable version"); +-MODULE_AUTHOR("Synopsys Inc."); +-MODULE_LICENSE ("GPL"); +- +-static int dwc_common_port_init_module(void) +-{ +- printk( KERN_DEBUG "Module dwc_common_port init\n" ); +-#ifdef DEBUG_MEMORY +- dwc_memory_debug_start(); ++#ifdef DWC_CCLIB ++# include "dwc_cc.h" + #endif +- dwc_alloc_notification_manager(); +- return 0; +-} + +-static void dwc_common_port_exit_module(void) +-{ +- printk( KERN_DEBUG "Module dwc_common_port exit\n" ); +- dwc_free_notification_manager(); +-#ifdef DEBUG_MEMORY +- dwc_memory_debug_stop(); ++#ifdef DWC_CRYPTOLIB ++# include "dwc_modpow.h" ++# include "dwc_dh.h" ++# include "dwc_crypto.h" + #endif +-} +- +-module_init(dwc_common_port_init_module); +-module_exit(dwc_common_port_exit_module); +- +-/* CC */ +-EXPORT_SYMBOL(dwc_cc_if_alloc); +-EXPORT_SYMBOL(dwc_cc_if_free); +-EXPORT_SYMBOL(dwc_cc_clear); +-EXPORT_SYMBOL(dwc_cc_add); +-EXPORT_SYMBOL(dwc_cc_remove); +-EXPORT_SYMBOL(dwc_cc_change); +-EXPORT_SYMBOL(dwc_cc_data_for_save); +-EXPORT_SYMBOL(dwc_cc_restore_from_data); +-EXPORT_SYMBOL(dwc_cc_match_chid); +-EXPORT_SYMBOL(dwc_cc_match_cdid); +-EXPORT_SYMBOL(dwc_cc_ck); +-EXPORT_SYMBOL(dwc_cc_chid); +-EXPORT_SYMBOL(dwc_cc_cdid); +-EXPORT_SYMBOL(dwc_cc_name); +- +-/* Notification */ +-EXPORT_SYMBOL(dwc_alloc_notification_manager); +-EXPORT_SYMBOL(dwc_free_notification_manager); +-EXPORT_SYMBOL(dwc_register_notifier); +-EXPORT_SYMBOL(dwc_unregister_notifier); +-EXPORT_SYMBOL(dwc_add_observer); +-EXPORT_SYMBOL(dwc_remove_observer); +-EXPORT_SYMBOL(dwc_notify); + +-/* Memory Debugging Routines */ +-#ifdef DEBUG_MEMORY +-EXPORT_SYMBOL(dwc_alloc_debug); +-EXPORT_SYMBOL(dwc_alloc_atomic_debug); +-EXPORT_SYMBOL(dwc_free_debug); +-EXPORT_SYMBOL(dwc_dma_alloc_debug); +-EXPORT_SYMBOL(dwc_dma_alloc_atomic_debug); +-EXPORT_SYMBOL(dwc_dma_free_debug); ++#ifdef DWC_NOTIFYLIB ++# include "dwc_notifier.h" + #endif + + /* OS-Level Implementations */ + + /* This is the Linux kernel implementation of the DWC platform library. */ +-#include +-#include +-#include + #include + #include ++#include + #include + #include + #include +@@ -84,24 +32,30 @@ + #include + #include + #include ++#include ++#include + #include + #include + #include + #include +-#include + #include +-#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30)) +-#include ++ ++#include ++ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,24) ++# include + #else +-#include ++# include + #endif +-#include ++ + #include + #include + #include + #include +-#include +-#include ++ ++#include "dwc_os.h" ++#include "dwc_list.h" ++ + + /* MISC */ + +@@ -109,86 +63,83 @@ + { + return memset(dest, byte, size); + } +-EXPORT_SYMBOL(DWC_MEMSET); + + void *DWC_MEMCPY(void *dest, void const *src, uint32_t size) + { + return memcpy(dest, src, size); + } +-EXPORT_SYMBOL(DWC_MEMCPY); + + void *DWC_MEMMOVE(void *dest, void *src, uint32_t size) + { + return memmove(dest, src, size); + } +-EXPORT_SYMBOL(DWC_MEMMOVE); + + int DWC_MEMCMP(void *m1, void *m2, uint32_t size) + { + return memcmp(m1, m2, size); + } +-EXPORT_SYMBOL(DWC_MEMCMP); + + int DWC_STRNCMP(void *s1, void *s2, uint32_t size) + { + return strncmp(s1, s2, size); + } +-EXPORT_SYMBOL(DWC_STRNCMP); + + int DWC_STRCMP(void *s1, void *s2) + { + return strcmp(s1, s2); + } +-EXPORT_SYMBOL(DWC_STRCMP); + + int DWC_STRLEN(char const *str) + { + return strlen(str); + } +-EXPORT_SYMBOL(DWC_STRLEN); + +-char *DWC_STRCPY(char *to, const char *from) ++char *DWC_STRCPY(char *to, char const *from) + { + return strcpy(to, from); + } +-EXPORT_SYMBOL(DWC_STRCPY); + + char *DWC_STRDUP(char const *str) + { + int len = DWC_STRLEN(str) + 1; + char *new = DWC_ALLOC_ATOMIC(len); ++ + if (!new) { + return NULL; + } ++ + DWC_MEMCPY(new, str, len); + return new; + } +-EXPORT_SYMBOL(DWC_STRDUP); + +-int DWC_ATOI(char *str, int32_t *value) ++int DWC_ATOI(const char *str, int32_t *value) + { + char *end = NULL; ++ + *value = simple_strtol(str, &end, 0); + if (*end == '\0') { + return 0; + } ++ + return -1; + } +-EXPORT_SYMBOL(DWC_ATOI); + +-int DWC_ATOUI(char *str, uint32_t *value) ++int DWC_ATOUI(const char *str, uint32_t *value) + { + char *end = NULL; ++ + *value = simple_strtoul(str, &end, 0); + if (*end == '\0') { + return 0; + } ++ + return -1; + } +-EXPORT_SYMBOL(DWC_ATOUI); + + ++#ifdef DWC_UTFLIB + /* From usbstring.c */ ++ + int DWC_UTF8_TO_UTF16LE(uint8_t const *s, uint16_t *cp, unsigned len) + { + int count = 0; +@@ -238,7 +189,6 @@ + // = 11110uuu 10uuzzzz 10yyyyyy 10xxxxxx + // (uuuuu = wwww + 1) + // FIXME accept the surrogate code points (only) +- + } else + goto fail; + } else +@@ -251,7 +201,8 @@ + fail: + return -1; + } +-EXPORT_SYMBOL(DWC_UTF8_TO_UTF16LE); ++#endif /* DWC_UTFLIB */ ++ + + /* dwc_debug.h */ + +@@ -259,19 +210,16 @@ + { + return in_irq(); + } +-EXPORT_SYMBOL(DWC_IN_IRQ); + +-int DWC_IN_BH(void) ++dwc_bool_t DWC_IN_BH(void) + { + return in_softirq(); + } +-EXPORT_SYMBOL(DWC_IN_BH); + + void DWC_VPRINTF(char *format, va_list args) + { + vprintk(format, args); + } +-EXPORT_SYMBOL(DWC_VPRINTF); + + int DWC_VSNPRINTF(char *str, int size, char *format, va_list args) + { +@@ -281,79 +229,78 @@ + void DWC_PRINTF(char *format, ...) + { + va_list args; ++ + va_start(args, format); + DWC_VPRINTF(format, args); + va_end(args); + } +-EXPORT_SYMBOL(DWC_PRINTF); + + int DWC_SPRINTF(char *buffer, char *format, ...) + { + int retval; + va_list args; ++ + va_start(args, format); + retval = vsprintf(buffer, format, args); + va_end(args); + return retval; + } +-EXPORT_SYMBOL(DWC_SPRINTF); + + int DWC_SNPRINTF(char *buffer, int size, char *format, ...) + { + int retval; + va_list args; ++ + va_start(args, format); + retval = vsnprintf(buffer, size, format, args); + va_end(args); + return retval; + } +-EXPORT_SYMBOL(DWC_SNPRINTF); + + void __DWC_WARN(char *format, ...) + { + va_list args; ++ + va_start(args, format); + DWC_PRINTF(KERN_WARNING); + DWC_VPRINTF(format, args); + va_end(args); + } +-EXPORT_SYMBOL(__DWC_WARN); + + void __DWC_ERROR(char *format, ...) + { + va_list args; ++ + va_start(args, format); + DWC_PRINTF(KERN_ERR); + DWC_VPRINTF(format, args); + va_end(args); + } +-EXPORT_SYMBOL(__DWC_ERROR); + + void DWC_EXCEPTION(char *format, ...) + { + va_list args; ++ + va_start(args, format); + DWC_PRINTF(KERN_ERR); + DWC_VPRINTF(format, args); + va_end(args); + BUG_ON(1); + } +-EXPORT_SYMBOL(DWC_EXCEPTION); + + #ifdef DEBUG + void __DWC_DEBUG(char *format, ...) + { + va_list args; ++ + va_start(args, format); + DWC_PRINTF(KERN_DEBUG); + DWC_VPRINTF(format, args); + va_end(args); + } +-EXPORT_SYMBOL(__DWC_DEBUG); + #endif + + +- + /* dwc_mem.h */ + + #if 0 +@@ -371,42 +318,39 @@ + dma_pool_destroy((struct dma_pool *)pool); + } + +-void *DWC_DMA_POOL_ALLOC(dwc_pool_t *pool, U64 *dma_addr) ++void *DWC_DMA_POOL_ALLOC(dwc_pool_t *pool, uint64_t *dma_addr) + { + return dma_pool_alloc((struct dma_pool *)pool, GFP_KERNEL, dma_addr); + } + +-void *DWC_DMA_POOL_ZALLOC(dwc_pool_t *pool, U64 *dma_addr) ++void *DWC_DMA_POOL_ZALLOC(dwc_pool_t *pool, uint64_t *dma_addr) + { + void *vaddr = DWC_DMA_POOL_ALLOC(pool, dma_addr); +- memset(); ++ memset(..); + } + + void DWC_DMA_POOL_FREE(dwc_pool_t *pool, void *vaddr, void *daddr) + { + dma_pool_free(pool, vaddr, daddr); + } +- + #endif + +-void *__DWC_DMA_ALLOC(uint32_t size, dwc_dma_t *dma_addr) ++void *__DWC_DMA_ALLOC(void *dma_ctx, uint32_t size, dwc_dma_t *dma_addr) + { +- void *buf = dma_alloc_coherent(NULL, (size_t)size, dma_addr, GFP_KERNEL); ++#ifdef xxCOSIM /* Only works for 32-bit cosim */ ++ void *buf = dma_alloc_coherent(dma_ctx, (size_t)size, dma_addr, GFP_KERNEL); ++#else ++ void *buf = dma_alloc_coherent(dma_ctx, (size_t)size, dma_addr, GFP_KERNEL | GFP_DMA32); ++#endif + if (!buf) { + return NULL; + } ++ + memset(buf, 0, (size_t)size); + return buf; + } +-EXPORT_SYMBOL(__DWC_DMA_ALLOC); +- +-void __DWC_DMA_FREE(uint32_t size, void *virt_addr, dwc_dma_t dma_addr) +-{ +- dma_free_coherent(NULL, size, virt_addr, dma_addr); +-} +-EXPORT_SYMBOL(__DWC_DMA_FREE); + +-void *__DWC_DMA_ALLOC_ATOMIC(uint32_t size, dwc_dma_t *dma_addr) ++void *__DWC_DMA_ALLOC_ATOMIC(void *dma_ctx, uint32_t size, dwc_dma_t *dma_addr) + { + void *buf = dma_alloc_coherent(NULL, (size_t)size, dma_addr, GFP_ATOMIC); + if (!buf) { +@@ -415,119 +359,199 @@ + memset(buf, 0, (size_t)size); + return buf; + } +-EXPORT_SYMBOL(__DWC_DMA_ALLOC_ATOMIC); + +-void *__DWC_ALLOC(uint32_t size) ++void __DWC_DMA_FREE(void *dma_ctx, uint32_t size, void *virt_addr, dwc_dma_t dma_addr) ++{ ++ dma_free_coherent(dma_ctx, size, virt_addr, dma_addr); ++} ++ ++void *__DWC_ALLOC(void *mem_ctx, uint32_t size) + { + return kzalloc(size, GFP_KERNEL); + } +-EXPORT_SYMBOL(__DWC_ALLOC); + +-void *__DWC_ALLOC_ATOMIC(uint32_t size) ++void *__DWC_ALLOC_ATOMIC(void *mem_ctx, uint32_t size) + { + return kzalloc(size, GFP_ATOMIC); + } +-EXPORT_SYMBOL(__DWC_ALLOC_ATOMIC); + +-void __DWC_FREE(void *addr) ++void __DWC_FREE(void *mem_ctx, void *addr) + { + kfree(addr); + } +-EXPORT_SYMBOL(__DWC_FREE); + +-/* Byte Ordering Conversions. */ +-uint32_t DWC_CPU_TO_LE32(void *p) ++ ++#ifdef DWC_CRYPTOLIB ++/* dwc_crypto.h */ ++ ++void DWC_RANDOM_BYTES(uint8_t *buffer, uint32_t length) ++{ ++ get_random_bytes(buffer, length); ++} ++ ++int DWC_AES_CBC(uint8_t *message, uint32_t messagelen, uint8_t *key, uint32_t keylen, uint8_t iv[16], uint8_t *out) ++{ ++ struct crypto_blkcipher *tfm; ++ struct blkcipher_desc desc; ++ struct scatterlist sgd; ++ struct scatterlist sgs; ++ ++ tfm = crypto_alloc_blkcipher("cbc(aes)", 0, CRYPTO_ALG_ASYNC); ++ if (tfm == NULL) { ++ printk("failed to load transform for aes CBC\n"); ++ return -1; ++ } ++ ++ crypto_blkcipher_setkey(tfm, key, keylen); ++ crypto_blkcipher_set_iv(tfm, iv, 16); ++ ++ sg_init_one(&sgd, out, messagelen); ++ sg_init_one(&sgs, message, messagelen); ++ ++ desc.tfm = tfm; ++ desc.flags = 0; ++ ++ if (crypto_blkcipher_encrypt(&desc, &sgd, &sgs, messagelen)) { ++ crypto_free_blkcipher(tfm); ++ DWC_ERROR("AES CBC encryption failed"); ++ return -1; ++ } ++ ++ crypto_free_blkcipher(tfm); ++ return 0; ++} ++ ++int DWC_SHA256(uint8_t *message, uint32_t len, uint8_t *out) ++{ ++ struct crypto_hash *tfm; ++ struct hash_desc desc; ++ struct scatterlist sg; ++ ++ tfm = crypto_alloc_hash("sha256", 0, CRYPTO_ALG_ASYNC); ++ if (IS_ERR(tfm)) { ++ DWC_ERROR("Failed to load transform for sha256: %ld\n", PTR_ERR(tfm)); ++ return 0; ++ } ++ desc.tfm = tfm; ++ desc.flags = 0; ++ ++ sg_init_one(&sg, message, len); ++ crypto_hash_digest(&desc, &sg, len, out); ++ crypto_free_hash(tfm); ++ ++ return 1; ++} ++ ++int DWC_HMAC_SHA256(uint8_t *message, uint32_t messagelen, ++ uint8_t *key, uint32_t keylen, uint8_t *out) ++{ ++ struct crypto_hash *tfm; ++ struct hash_desc desc; ++ struct scatterlist sg; ++ ++ tfm = crypto_alloc_hash("hmac(sha256)", 0, CRYPTO_ALG_ASYNC); ++ if (IS_ERR(tfm)) { ++ DWC_ERROR("Failed to load transform for hmac(sha256): %ld\n", PTR_ERR(tfm)); ++ return 0; ++ } ++ desc.tfm = tfm; ++ desc.flags = 0; ++ ++ sg_init_one(&sg, message, messagelen); ++ crypto_hash_setkey(tfm, key, keylen); ++ crypto_hash_digest(&desc, &sg, messagelen, out); ++ crypto_free_hash(tfm); ++ ++ return 1; ++} ++#endif /* DWC_CRYPTOLIB */ ++ ++ ++/* Byte Ordering Conversions */ ++ ++uint32_t DWC_CPU_TO_LE32(uint32_t *p) + { + #ifdef __LITTLE_ENDIAN +- return *((uint32_t *)p); ++ return *p; + #else + uint8_t *u_p = (uint8_t *)p; + + return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24)); + #endif + } +-EXPORT_SYMBOL(DWC_CPU_TO_LE32); + +-uint32_t DWC_CPU_TO_BE32(void *p) ++uint32_t DWC_CPU_TO_BE32(uint32_t *p) + { + #ifdef __BIG_ENDIAN +- return *((uint32_t *)p); ++ return *p; + #else + uint8_t *u_p = (uint8_t *)p; + + return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24)); + #endif + } +-EXPORT_SYMBOL(DWC_CPU_TO_BE32); + +-uint32_t DWC_LE32_TO_CPU(void *p) ++uint32_t DWC_LE32_TO_CPU(uint32_t *p) + { + #ifdef __LITTLE_ENDIAN +- return *((uint32_t *)p); ++ return *p; + #else + uint8_t *u_p = (uint8_t *)p; + + return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24)); +- + #endif + } +-EXPORT_SYMBOL(DWC_LE32_TO_CPU); + +-uint32_t DWC_BE32_TO_CPU(void *p) ++uint32_t DWC_BE32_TO_CPU(uint32_t *p) + { + #ifdef __BIG_ENDIAN +- return *((uint32_t *)p); ++ return *p; + #else + uint8_t *u_p = (uint8_t *)p; + + return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24)); + #endif + } +-EXPORT_SYMBOL(DWC_BE32_TO_CPU); + +-uint16_t DWC_CPU_TO_LE16(void *p) ++uint16_t DWC_CPU_TO_LE16(uint16_t *p) + { + #ifdef __LITTLE_ENDIAN +- return *((uint16_t *)p); ++ return *p; + #else + uint8_t *u_p = (uint8_t *)p; + return (u_p[1] | (u_p[0] << 8)); + #endif + } +-EXPORT_SYMBOL(DWC_CPU_TO_LE16); + +-uint16_t DWC_CPU_TO_BE16(void *p) ++uint16_t DWC_CPU_TO_BE16(uint16_t *p) + { + #ifdef __BIG_ENDIAN +- return *((uint16_t *)p); ++ return *p; + #else + uint8_t *u_p = (uint8_t *)p; + return (u_p[1] | (u_p[0] << 8)); + #endif + } +-EXPORT_SYMBOL(DWC_CPU_TO_BE16); + +-uint16_t DWC_LE16_TO_CPU(void *p) ++uint16_t DWC_LE16_TO_CPU(uint16_t *p) + { + #ifdef __LITTLE_ENDIAN +- return *((uint16_t *)p); ++ return *p; + #else + uint8_t *u_p = (uint8_t *)p; + return (u_p[1] | (u_p[0] << 8)); + #endif + } +-EXPORT_SYMBOL(DWC_LE16_TO_CPU); + +-uint16_t DWC_BE16_TO_CPU(void *p) ++uint16_t DWC_BE16_TO_CPU(uint16_t *p) + { + #ifdef __BIG_ENDIAN +- return *((uint16_t *p)p); ++ return *p; + #else + uint8_t *u_p = (uint8_t *)p; + return (u_p[1] | (u_p[0] << 8)); + #endif + } +-EXPORT_SYMBOL(DWC_BE16_TO_CPU); + + + /* Registers */ +@@ -536,7 +560,6 @@ + { + return readl(reg); + } +-EXPORT_SYMBOL(DWC_READ_REG32); + + #if 0 + uint64_t DWC_READ_REG64(uint64_t volatile *reg) +@@ -548,7 +571,6 @@ + { + writel(value, reg); + } +-EXPORT_SYMBOL(DWC_WRITE_REG32); + + #if 0 + void DWC_WRITE_REG64(uint64_t volatile *reg, uint64_t value) +@@ -558,330 +580,145 @@ + + void DWC_MODIFY_REG32(uint32_t volatile *reg, uint32_t clear_mask, uint32_t set_mask) + { +- writel( (readl(reg) & ~clear_mask) | set_mask, reg ); ++ writel((readl(reg) & ~clear_mask) | set_mask, reg); + } +-EXPORT_SYMBOL(DWC_MODIFY_REG32); + + #if 0 +-void DWC_MODIFY_REG64(uint64_t volatile *reg, uint64_t value) ++void DWC_MODIFY_REG64(uint64_t volatile *reg, uint64_t clear_mask, uint64_t set_mask) + { + } + #endif + + ++/* Locking */ + +-/* Threading */ +- +-typedef struct work_container ++dwc_spinlock_t *DWC_SPINLOCK_ALLOC(void) + { +- dwc_work_callback_t cb; +- void *data; +- dwc_workq_t *wq; +- char *name; ++ spinlock_t *sl = (spinlock_t *)1; + +-#ifdef DEBUG +- DWC_CIRCLEQ_ENTRY(work_container) entry; +-#endif ++#if defined(CONFIG_PREEMPT) || defined(CONFIG_SMP) ++ sl = DWC_ALLOC(sizeof(*sl)); ++ if (!sl) { ++ DWC_ERROR("Cannot allocate memory for spinlock\n"); ++ return NULL; ++ } + +- struct delayed_work work; +-} work_container_t; ++ spin_lock_init(sl); ++#endif ++ return (dwc_spinlock_t *)sl; ++} + +-#ifdef DEBUG +-DWC_CIRCLEQ_HEAD(work_container_queue, work_container); ++void DWC_SPINLOCK_FREE(dwc_spinlock_t *lock) ++{ ++#if defined(CONFIG_PREEMPT) || defined(CONFIG_SMP) ++ DWC_FREE(lock); + #endif ++} + +-struct dwc_workq ++void DWC_SPINLOCK(dwc_spinlock_t *lock) + { +- struct workqueue_struct *wq; +- int pending; +- dwc_spinlock_t *lock; +- dwc_waitq_t *waitq; ++#if defined(CONFIG_PREEMPT) || defined(CONFIG_SMP) ++ spin_lock((spinlock_t *)lock); ++#endif ++} + +-#ifdef DEBUG +- struct work_container_queue entries; ++void DWC_SPINUNLOCK(dwc_spinlock_t *lock) ++{ ++#if defined(CONFIG_PREEMPT) || defined(CONFIG_SMP) ++ spin_unlock((spinlock_t *)lock); + #endif +-}; ++} + +-static void do_work(struct work_struct *work) ++void DWC_SPINLOCK_IRQSAVE(dwc_spinlock_t *lock, dwc_irqflags_t *flags) + { +- int64_t flags; +- struct delayed_work *dw = container_of(work, struct delayed_work, work); +- work_container_t *container = container_of(dw, struct work_container, work); +- dwc_workq_t *wq = container->wq; ++ dwc_irqflags_t f; + +- container->cb(container->data); ++#if defined(CONFIG_PREEMPT) || defined(CONFIG_SMP) ++ spin_lock_irqsave((spinlock_t *)lock, f); ++#else ++ local_irq_save(f); ++#endif ++ *flags = f; ++} + +-#ifdef DEBUG +- DWC_CIRCLEQ_REMOVE(&wq->entries, container, entry); ++void DWC_SPINUNLOCK_IRQRESTORE(dwc_spinlock_t *lock, dwc_irqflags_t flags) ++{ ++#if defined(CONFIG_PREEMPT) || defined(CONFIG_SMP) ++ spin_unlock_irqrestore((spinlock_t *)lock, flags); ++#else ++ local_irq_restore(flags); + #endif ++} + +- if (container->name) { +- DWC_DEBUG("Work done: %s, container=%p", +- container->name, container); //GRAYG +- DWC_FREE(container->name); ++dwc_mutex_t *DWC_MUTEX_ALLOC(void) ++{ ++ struct mutex *m; ++ dwc_mutex_t *mutex = (dwc_mutex_t *)DWC_ALLOC(sizeof(struct mutex)); ++ ++ if (!mutex) { ++ DWC_ERROR("Cannot allocate memory for mutex\n"); ++ return NULL; + } +- DWC_FREE(container); + +- DWC_SPINLOCK_IRQSAVE(wq->lock, &flags); +- wq->pending --; +- DWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags); +- DWC_WAITQ_TRIGGER(wq->waitq); ++ m = (struct mutex *)mutex; ++ mutex_init(m); ++ return mutex; + } + +-static int work_done(void *data) ++#if (defined(DWC_LINUX) && defined(CONFIG_DEBUG_MUTEXES)) ++#else ++void DWC_MUTEX_FREE(dwc_mutex_t *mutex) + { +- dwc_workq_t *workq = (dwc_workq_t *)data; +- return workq->pending == 0; ++ mutex_destroy((struct mutex *)mutex); ++ DWC_FREE(mutex); + } ++#endif + +-int DWC_WORKQ_WAIT_WORK_DONE(dwc_workq_t *workq, int timeout) ++void DWC_MUTEX_LOCK(dwc_mutex_t *mutex) + { +- return DWC_WAITQ_WAIT_TIMEOUT(workq->waitq, work_done, workq, timeout); ++ struct mutex *m = (struct mutex *)mutex; ++ mutex_lock(m); + } +-EXPORT_SYMBOL(DWC_WORKQ_WAIT_WORK_DONE); + +-dwc_workq_t *DWC_WORKQ_ALLOC(char *name) ++int DWC_MUTEX_TRYLOCK(dwc_mutex_t *mutex) + { +- dwc_workq_t *wq = DWC_ALLOC(sizeof(*wq)); +- wq->wq = create_singlethread_workqueue(name); +- wq->pending = 0; +- wq->lock = DWC_SPINLOCK_ALLOC(); +- wq->waitq = DWC_WAITQ_ALLOC(); +-#ifdef DEBUG +- DWC_CIRCLEQ_INIT(&wq->entries); +-#endif +- return wq; +-} +-EXPORT_SYMBOL(DWC_WORKQ_ALLOC); +- +-void DWC_WORKQ_FREE(dwc_workq_t *wq) +-{ +-#ifdef DEBUG +- if (wq->pending != 0) { +- struct work_container *wc; +- DWC_ERROR("Destroying work queue with pending work"); +- DWC_CIRCLEQ_FOREACH(wc, &wq->entries, entry) { +- DWC_ERROR("Work %s still pending", wc->name); +- } +- } +-#endif +- destroy_workqueue((struct workqueue_struct *)wq->wq); +- DWC_SPINLOCK_FREE(wq->lock); +- DWC_WAITQ_FREE(wq->waitq); +- DWC_FREE(wq); +-} +-EXPORT_SYMBOL(DWC_WORKQ_FREE); +- +-void DWC_WORKQ_SCHEDULE(dwc_workq_t *wq, dwc_work_callback_t work_cb, void *data, char *format, ...) +-{ +- int64_t flags; +- work_container_t *container; +- static char name[128]; +- +- va_list args; +- va_start(args, format); +- if (format) +- DWC_VSNPRINTF(name, 128, format, args); +- va_end(args); +- +- DWC_SPINLOCK_IRQSAVE(wq->lock, &flags); +- wq->pending ++; +- DWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags); +- DWC_WAITQ_TRIGGER(wq->waitq); +- +- container = DWC_ALLOC_ATOMIC(sizeof(*container)); +- +- container->data = data; +- container->cb = work_cb; +- container->wq = wq; +- if (format) { +- container->name = DWC_STRDUP(name); +- DWC_DEBUG("Queueing work: %s, contianer=%p", +- container->name, container); +- } else +- container->name = NULL; +- +- INIT_WORK(&container->work.work, do_work); +- +-#ifdef DEBUG +- DWC_CIRCLEQ_INSERT_TAIL(&wq->entries, container, entry); +-#endif +- +- queue_work(wq->wq, &container->work.work); +- +-} +-EXPORT_SYMBOL(DWC_WORKQ_SCHEDULE); +- +-void DWC_WORKQ_SCHEDULE_DELAYED(dwc_workq_t *wq, dwc_work_callback_t work_cb, void *data, uint32_t time, char *format, ...) +-{ +- int64_t flags; +- work_container_t *container; +- static char name[128]; +- +- va_list args; +- va_start(args, format); +- if (format) +- DWC_VSNPRINTF(name, 128, format, args); +- va_end(args); +- +- DWC_SPINLOCK_IRQSAVE(wq->lock, &flags); +- wq->pending ++; +- DWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags); +- DWC_WAITQ_TRIGGER(wq->waitq); +- +- container = DWC_ALLOC_ATOMIC(sizeof(*container)); +- +- container->data = data; +- container->cb = work_cb; +- container->wq = wq; +- if (format) { //GRAYG +- container->name = DWC_STRDUP(name); +- DWC_DEBUG("Queueing work: %s, contianer=%p", +- container->name, container); +- } else +- container->name = NULL; +- INIT_DELAYED_WORK(&container->work, do_work); +- +-#ifdef DEBUG +- DWC_CIRCLEQ_INSERT_TAIL(&wq->entries, container, entry); +-#endif +- +- queue_delayed_work(wq->wq, &container->work, msecs_to_jiffies(time)); +- +-} +-EXPORT_SYMBOL(DWC_WORKQ_SCHEDULE_DELAYED); +- +- +-int DWC_WORKQ_PENDING(dwc_workq_t *wq) +-{ +- return wq->pending; +-} +-EXPORT_SYMBOL(DWC_WORKQ_PENDING); +- +-dwc_spinlock_t *DWC_SPINLOCK_ALLOC(void) +-{ +- spinlock_t *sl = (spinlock_t *)1; +-#if defined(CONFIG_PREEMPT) || defined(CONFIG_SMP) +- sl = DWC_ALLOC(sizeof(*sl)); +- spin_lock_init(sl); +-#endif +- return (dwc_spinlock_t *)sl; +-} +-EXPORT_SYMBOL(DWC_SPINLOCK_ALLOC); +- +-void DWC_SPINLOCK_FREE(dwc_spinlock_t *lock) +-{ +-#if defined(CONFIG_PREEMPT) || defined(CONFIG_SMP) +- DWC_FREE(lock); +-#endif +-} +-EXPORT_SYMBOL(DWC_SPINLOCK_FREE); +- +-void DWC_SPINLOCK(dwc_spinlock_t *lock) +-{ +-#if defined(CONFIG_PREEMPT) || defined(CONFIG_SMP) +- spin_lock((spinlock_t *)lock); +-#endif +-} +-EXPORT_SYMBOL(DWC_SPINLOCK); +- +-void DWC_SPINUNLOCK(dwc_spinlock_t *lock) +-{ +-#if defined(CONFIG_PREEMPT) || defined(CONFIG_SMP) +- spin_unlock((spinlock_t *)lock); +-#endif +-} +-EXPORT_SYMBOL(DWC_SPINUNLOCK); +- +-void DWC_SPINLOCK_IRQSAVE(dwc_spinlock_t *lock, uint64_t *flags) +-{ +- unsigned long f; +-#if defined(CONFIG_PREEMPT) || defined(CONFIG_SMP) +- spin_lock_irqsave((spinlock_t *)lock, f); +-#else +- local_irq_save(f); +-#endif +- *flags = f; +-} +-EXPORT_SYMBOL(DWC_SPINLOCK_IRQSAVE); +- +-void DWC_SPINUNLOCK_IRQRESTORE(dwc_spinlock_t *lock, uint64_t flags) +-{ +-#if defined(CONFIG_PREEMPT) || defined(CONFIG_SMP) +- spin_unlock_irqrestore((spinlock_t *)lock, flags); +-#else +- // in kernel 2.6.31, at least, we check for unsigned long +- local_irq_restore((unsigned long)flags); +-#endif ++ struct mutex *m = (struct mutex *)mutex; ++ return mutex_trylock(m); + } +-EXPORT_SYMBOL(DWC_SPINUNLOCK_IRQRESTORE); + +-dwc_mutex_t *DWC_MUTEX_ALLOC(void) ++void DWC_MUTEX_UNLOCK(dwc_mutex_t *mutex) + { +- dwc_mutex_t *mutex = (dwc_mutex_t*)DWC_ALLOC(sizeof(struct mutex)); + struct mutex *m = (struct mutex *)mutex; +- mutex_init(m); +- return mutex; ++ mutex_unlock(m); + } +-EXPORT_SYMBOL(DWC_MUTEX_ALLOC); + +-#if (defined(DWC_LINUX) && defined(CONFIG_DEBUG_MUTEXES)) +-#else +-void DWC_MUTEX_FREE(dwc_mutex_t *mutex) +-{ +- mutex_destroy((struct mutex *)mutex); +- DWC_FREE(mutex); +-} +-EXPORT_SYMBOL(DWC_MUTEX_FREE); +-#endif + +-void DWC_MUTEX_LOCK(dwc_mutex_t *mutex) +-{ +- struct mutex *m = (struct mutex *)mutex; +- mutex_lock(m); +-} +-EXPORT_SYMBOL(DWC_MUTEX_LOCK); ++/* Timing */ + +-int DWC_MUTEX_TRYLOCK(dwc_mutex_t *mutex) ++void DWC_UDELAY(uint32_t usecs) + { +- struct mutex *m = (struct mutex *)mutex; +- return mutex_trylock(m); ++ udelay(usecs); + } +-EXPORT_SYMBOL(DWC_MUTEX_TRYLOCK); + +-void DWC_MUTEX_UNLOCK(dwc_mutex_t *mutex) ++void DWC_MDELAY(uint32_t msecs) + { +- struct mutex *m = (struct mutex *)mutex; +- mutex_unlock(m); ++ mdelay(msecs); + } +-EXPORT_SYMBOL(DWC_MUTEX_UNLOCK); + +-dwc_thread_t *DWC_THREAD_RUN(dwc_thread_function_t thread_function, char *name, void *data) ++void DWC_MSLEEP(uint32_t msecs) + { +- struct task_struct *thread = kthread_run(thread_function, data, name); +- if (thread == ERR_PTR(-ENOMEM)) { +- return NULL; +- } +- return (dwc_thread_t *)thread; ++ msleep(msecs); + } +-EXPORT_SYMBOL(DWC_THREAD_RUN); + +-int DWC_THREAD_STOP(dwc_thread_t *thread) ++uint32_t DWC_TIME(void) + { +- return kthread_stop((struct task_struct *)thread); ++ return jiffies_to_msecs(jiffies); + } +-EXPORT_SYMBOL(DWC_THREAD_STOP); + +-dwc_bool_t DWC_THREAD_SHOULD_STOP() +-{ +- return kthread_should_stop(); +-} +-EXPORT_SYMBOL(DWC_THREAD_SHOULD_STOP); + + /* Timers */ + +-struct dwc_timer +-{ ++struct dwc_timer { + struct timer_list *t; + char *name; + dwc_timer_callback_t cb; +@@ -890,39 +727,27 @@ + dwc_spinlock_t *lock; + }; + +-static void set_scheduled(dwc_timer_t *t, int s) +-{ +- uint64_t flags; +- DWC_SPINLOCK_IRQSAVE(t->lock, &flags); +- t->scheduled = s; +- DWC_SPINUNLOCK_IRQRESTORE(t->lock, flags); +-} +- +-static int get_scheduled(dwc_timer_t *t) +-{ +- int s; +- uint64_t flags; +- DWC_SPINLOCK_IRQSAVE(t->lock, &flags); +- s = t->scheduled; +- DWC_SPINUNLOCK_IRQRESTORE(t->lock, flags); +- return s; +-} +- + static void timer_callback(unsigned long data) + { + dwc_timer_t *timer = (dwc_timer_t *)data; +- set_scheduled(timer, 0); +- DWC_DEBUG("Timer %s callback", timer->name); ++ dwc_irqflags_t flags; ++ ++ DWC_SPINLOCK_IRQSAVE(timer->lock, &flags); ++ timer->scheduled = 0; ++ DWC_SPINUNLOCK_IRQRESTORE(timer->lock, flags); ++ DWC_DEBUGC("Timer %s callback", timer->name); + timer->cb(timer->data); + } + + dwc_timer_t *DWC_TIMER_ALLOC(char *name, dwc_timer_callback_t cb, void *data) + { + dwc_timer_t *t = DWC_ALLOC(sizeof(*t)); ++ + if (!t) { + DWC_ERROR("Cannot allocate memory for timer"); + return NULL; + } ++ + t->t = DWC_ALLOC(sizeof(*t->t)); + if (!t->t) { + DWC_ERROR("Cannot allocate memory for timer->t"); +@@ -940,6 +765,7 @@ + DWC_ERROR("Cannot allocate memory for lock"); + goto no_lock; + } ++ + t->scheduled = 0; + t->t->base = &boot_tvec_bases; + t->t->expires = jiffies; +@@ -958,181 +784,638 @@ + DWC_FREE(t); + return NULL; + } +-EXPORT_SYMBOL(DWC_TIMER_ALLOC); + + void DWC_TIMER_FREE(dwc_timer_t *timer) + { +- if (get_scheduled(timer)) { ++ dwc_irqflags_t flags; ++ ++ DWC_SPINLOCK_IRQSAVE(timer->lock, &flags); ++ ++ if (timer->scheduled) { + del_timer(timer->t); ++ timer->scheduled = 0; + } + ++ DWC_SPINUNLOCK_IRQRESTORE(timer->lock, flags); + DWC_SPINLOCK_FREE(timer->lock); + DWC_FREE(timer->t); + DWC_FREE(timer->name); + DWC_FREE(timer); + } +-EXPORT_SYMBOL(DWC_TIMER_FREE); + + void DWC_TIMER_SCHEDULE(dwc_timer_t *timer, uint32_t time) + { +- if (!get_scheduled(timer)) { +- set_scheduled(timer, 1); +- //cgg: DWC_DEBUG("Scheduling timer %s to expire in +%d msec", timer->name, time); ++ dwc_irqflags_t flags; ++ ++ DWC_SPINLOCK_IRQSAVE(timer->lock, &flags); ++ ++ if (!timer->scheduled) { ++ timer->scheduled = 1; ++ DWC_DEBUGC("Scheduling timer %s to expire in +%d msec", timer->name, time); + timer->t->expires = jiffies + msecs_to_jiffies(time); + add_timer(timer->t); +- } +- else { +- //cgg: DWC_DEBUG("Modifying timer %s to expire in +%d msec", timer->name, time); ++ } else { ++ DWC_DEBUGC("Modifying timer %s to expire in +%d msec", timer->name, time); + mod_timer(timer->t, jiffies + msecs_to_jiffies(time)); + } ++ ++ DWC_SPINUNLOCK_IRQRESTORE(timer->lock, flags); + } +-EXPORT_SYMBOL(DWC_TIMER_SCHEDULE); + + void DWC_TIMER_CANCEL(dwc_timer_t *timer) + { + del_timer(timer->t); + } +-EXPORT_SYMBOL(DWC_TIMER_CANCEL); + +-struct dwc_tasklet +-{ +- struct tasklet_struct t; +- dwc_tasklet_callback_t cb; +- void *data; ++ ++/* Wait Queues */ ++ ++struct dwc_waitq { ++ wait_queue_head_t queue; ++ int abort; + }; + +-static void tasklet_callback(unsigned long data) ++dwc_waitq_t *DWC_WAITQ_ALLOC(void) + { +- dwc_tasklet_t *t = (dwc_tasklet_t *)data; +- t->cb(t->data); +-} ++ dwc_waitq_t *wq = DWC_ALLOC(sizeof(*wq)); + +-dwc_tasklet_t *DWC_TASK_ALLOC(dwc_tasklet_callback_t cb, void *data) +-{ +- dwc_tasklet_t *t = DWC_ALLOC(sizeof(*t)); +- +- if(t) { +- t->data = data; +- t->cb = cb; +- tasklet_init(&t->t, tasklet_callback, (unsigned long)t); +- } else { +- DWC_ERROR("Cannot allocate memory for tasklet\n"); ++ if (!wq) { ++ DWC_ERROR("Cannot allocate memory for waitqueue\n"); ++ return NULL; + } +- +- return t; ++ ++ init_waitqueue_head(&wq->queue); ++ wq->abort = 0; ++ return wq; + } +-EXPORT_SYMBOL(DWC_TASK_ALLOC); + +-void DWC_TASK_FREE(dwc_tasklet_t *t) ++void DWC_WAITQ_FREE(dwc_waitq_t *wq) + { +- DWC_FREE(t); ++ DWC_FREE(wq); + } +-EXPORT_SYMBOL(DWC_TASK_FREE); + +-void DWC_TASK_SCHEDULE(dwc_tasklet_t *task) ++int32_t DWC_WAITQ_WAIT(dwc_waitq_t *wq, dwc_waitq_condition_t cond, void *data) + { +- tasklet_schedule(&task->t); +-} +-EXPORT_SYMBOL(DWC_TASK_SCHEDULE); ++ int result = wait_event_interruptible(wq->queue, ++ cond(data) || wq->abort); ++ if (result == -ERESTARTSYS) { ++ wq->abort = 0; ++ return -DWC_E_RESTART; ++ } + +-/* Timing */ ++ if (wq->abort == 1) { ++ wq->abort = 0; ++ return -DWC_E_ABORT; ++ } + +-void DWC_UDELAY(uint32_t usecs) +-{ +- udelay(usecs); +-} +-EXPORT_SYMBOL(DWC_UDELAY); ++ wq->abort = 0; + +-void DWC_MDELAY(uint32_t msecs) +-{ +- mdelay(msecs); ++ if (result == 0) { ++ return 0; ++ } ++ ++ return -DWC_E_UNKNOWN; + } +-EXPORT_SYMBOL(DWC_MDELAY); + +-void DWC_MSLEEP(uint32_t msecs) ++int32_t DWC_WAITQ_WAIT_TIMEOUT(dwc_waitq_t *wq, dwc_waitq_condition_t cond, ++ void *data, int32_t msecs) + { +- msleep(msecs); ++ int32_t tmsecs; ++ int result = wait_event_interruptible_timeout(wq->queue, ++ cond(data) || wq->abort, ++ msecs_to_jiffies(msecs)); ++ if (result == -ERESTARTSYS) { ++ wq->abort = 0; ++ return -DWC_E_RESTART; ++ } ++ ++ if (wq->abort == 1) { ++ wq->abort = 0; ++ return -DWC_E_ABORT; ++ } ++ ++ wq->abort = 0; ++ ++ if (result > 0) { ++ tmsecs = jiffies_to_msecs(result); ++ if (!tmsecs) { ++ return 1; ++ } ++ ++ return tmsecs; ++ } ++ ++ if (result == 0) { ++ return -DWC_E_TIMEOUT; ++ } ++ ++ return -DWC_E_UNKNOWN; + } +-EXPORT_SYMBOL(DWC_MSLEEP); + +-uint32_t DWC_TIME(void) ++void DWC_WAITQ_TRIGGER(dwc_waitq_t *wq) + { +- return jiffies_to_msecs(jiffies); ++ wq->abort = 0; ++ wake_up_interruptible(&wq->queue); ++} ++ ++void DWC_WAITQ_ABORT(dwc_waitq_t *wq) ++{ ++ wq->abort = 1; ++ wake_up_interruptible(&wq->queue); + } +-EXPORT_SYMBOL(DWC_TIME); + + +-/* Wait Queues */ ++/* Threading */ + +-struct dwc_waitq ++dwc_thread_t *DWC_THREAD_RUN(dwc_thread_function_t func, char *name, void *data) + { +- wait_queue_head_t queue; +- int abort; ++ struct task_struct *thread = kthread_run(func, data, name); ++ ++ if (thread == ERR_PTR(-ENOMEM)) { ++ return NULL; ++ } ++ ++ return (dwc_thread_t *)thread; ++} ++ ++int DWC_THREAD_STOP(dwc_thread_t *thread) ++{ ++ return kthread_stop((struct task_struct *)thread); ++} ++ ++dwc_bool_t DWC_THREAD_SHOULD_STOP(void) ++{ ++ return kthread_should_stop(); ++} ++ ++ ++/* tasklets ++ - run in interrupt context (cannot sleep) ++ - each tasklet runs on a single CPU ++ - different tasklets can be running simultaneously on different CPUs ++ */ ++struct dwc_tasklet { ++ struct tasklet_struct t; ++ dwc_tasklet_callback_t cb; ++ void *data; + }; + +-dwc_waitq_t *DWC_WAITQ_ALLOC(void) ++static void tasklet_callback(unsigned long data) + { +- dwc_waitq_t *wq = DWC_ALLOC(sizeof(*wq)); +- init_waitqueue_head(&wq->queue); +- wq->abort = 0; +- return wq; ++ dwc_tasklet_t *t = (dwc_tasklet_t *)data; ++ t->cb(t->data); + } +-EXPORT_SYMBOL(DWC_WAITQ_ALLOC); + +-void DWC_WAITQ_FREE(dwc_waitq_t *wq) ++dwc_tasklet_t *DWC_TASK_ALLOC(char *name, dwc_tasklet_callback_t cb, void *data) + { ++ dwc_tasklet_t *t = DWC_ALLOC(sizeof(*t)); ++ ++ if (t) { ++ t->cb = cb; ++ t->data = data; ++ tasklet_init(&t->t, tasklet_callback, (unsigned long)t); ++ } else { ++ DWC_ERROR("Cannot allocate memory for tasklet\n"); ++ } ++ ++ return t; ++} ++ ++void DWC_TASK_FREE(dwc_tasklet_t *task) ++{ ++ DWC_FREE(task); ++} ++ ++void DWC_TASK_SCHEDULE(dwc_tasklet_t *task) ++{ ++ tasklet_schedule(&task->t); ++} ++ ++ ++/* workqueues ++ - run in process context (can sleep) ++ */ ++typedef struct work_container { ++ dwc_work_callback_t cb; ++ void *data; ++ dwc_workq_t *wq; ++ char *name; ++ ++#ifdef DEBUG ++ DWC_CIRCLEQ_ENTRY(work_container) entry; ++#endif ++ struct delayed_work work; ++} work_container_t; ++ ++#ifdef DEBUG ++DWC_CIRCLEQ_HEAD(work_container_queue, work_container); ++#endif ++ ++struct dwc_workq { ++ struct workqueue_struct *wq; ++ dwc_spinlock_t *lock; ++ dwc_waitq_t *waitq; ++ int pending; ++ ++#ifdef DEBUG ++ struct work_container_queue entries; ++#endif ++}; ++ ++static void do_work(struct work_struct *work) ++{ ++ dwc_irqflags_t flags; ++ struct delayed_work *dw = container_of(work, struct delayed_work, work); ++ work_container_t *container = container_of(dw, struct work_container, work); ++ dwc_workq_t *wq = container->wq; ++ ++ container->cb(container->data); ++ ++#ifdef DEBUG ++ DWC_CIRCLEQ_REMOVE(&wq->entries, container, entry); ++#endif ++ DWC_DEBUGC("Work done: %s, container=%p", container->name, container); ++ if (container->name) { ++ DWC_FREE(container->name); ++ } ++ DWC_FREE(container); ++ ++ DWC_SPINLOCK_IRQSAVE(wq->lock, &flags); ++ wq->pending--; ++ DWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags); ++ DWC_WAITQ_TRIGGER(wq->waitq); ++} ++ ++static int work_done(void *data) ++{ ++ dwc_workq_t *workq = (dwc_workq_t *)data; ++ return workq->pending == 0; ++} ++ ++int DWC_WORKQ_WAIT_WORK_DONE(dwc_workq_t *workq, int timeout) ++{ ++ return DWC_WAITQ_WAIT_TIMEOUT(workq->waitq, work_done, workq, timeout); ++} ++ ++dwc_workq_t *DWC_WORKQ_ALLOC(char *name) ++{ ++ dwc_workq_t *wq = DWC_ALLOC(sizeof(*wq)); ++ ++ if (!wq) { ++ return NULL; ++ } ++ ++ wq->wq = create_singlethread_workqueue(name); ++ if (!wq->wq) { ++ goto no_wq; ++ } ++ ++ wq->pending = 0; ++ ++ wq->lock = DWC_SPINLOCK_ALLOC(); ++ if (!wq->lock) { ++ goto no_lock; ++ } ++ ++ wq->waitq = DWC_WAITQ_ALLOC(); ++ if (!wq->waitq) { ++ goto no_waitq; ++ } ++ ++#ifdef DEBUG ++ DWC_CIRCLEQ_INIT(&wq->entries); ++#endif ++ return wq; ++ ++ no_waitq: ++ DWC_SPINLOCK_FREE(wq->lock); ++ no_lock: ++ destroy_workqueue(wq->wq); ++ no_wq: + DWC_FREE(wq); ++ ++ return NULL; + } +-EXPORT_SYMBOL(DWC_WAITQ_FREE); + +-static int32_t check_result(dwc_waitq_t *wq, int result) +-{ int32_t msecs; +- if (result > 0) { +- msecs = jiffies_to_msecs(result); +- if (!msecs) { +- return 1; ++void DWC_WORKQ_FREE(dwc_workq_t *wq) ++{ ++#ifdef DEBUG ++ if (wq->pending != 0) { ++ struct work_container *wc; ++ DWC_ERROR("Destroying work queue with pending work"); ++ DWC_CIRCLEQ_FOREACH(wc, &wq->entries, entry) { ++ DWC_ERROR("Work %s still pending", wc->name); + } +- return msecs; + } ++#endif ++ destroy_workqueue(wq->wq); ++ DWC_SPINLOCK_FREE(wq->lock); ++ DWC_WAITQ_FREE(wq->waitq); ++ DWC_FREE(wq); ++} + +- if (result == 0) { +- return -DWC_E_TIMEOUT; ++void DWC_WORKQ_SCHEDULE(dwc_workq_t *wq, dwc_work_callback_t cb, void *data, ++ char *format, ...) ++{ ++ dwc_irqflags_t flags; ++ work_container_t *container; ++ static char name[128]; ++ va_list args; ++ ++ va_start(args, format); ++ DWC_VSNPRINTF(name, 128, format, args); ++ va_end(args); ++ ++ DWC_SPINLOCK_IRQSAVE(wq->lock, &flags); ++ wq->pending++; ++ DWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags); ++ DWC_WAITQ_TRIGGER(wq->waitq); ++ ++ container = DWC_ALLOC_ATOMIC(sizeof(*container)); ++ if (!container) { ++ DWC_ERROR("Cannot allocate memory for container\n"); ++ return; + } + +- if ((result == -ERESTARTSYS) || (wq->abort == 1)) { +- return -DWC_E_ABORT; ++ container->name = DWC_STRDUP(name); ++ if (!container->name) { ++ DWC_ERROR("Cannot allocate memory for container->name\n"); ++ DWC_FREE(container); ++ return; + } + +- return -DWC_E_UNKNOWN; ++ container->cb = cb; ++ container->data = data; ++ container->wq = wq; ++ DWC_DEBUGC("Queueing work: %s, container=%p", container->name, container); ++ INIT_WORK(&container->work.work, do_work); ++ ++#ifdef DEBUG ++ DWC_CIRCLEQ_INSERT_TAIL(&wq->entries, container, entry); ++#endif ++ queue_work(wq->wq, &container->work.work); + } + +-int32_t DWC_WAITQ_WAIT(dwc_waitq_t *wq, dwc_waitq_condition_t condition, void *data) ++void DWC_WORKQ_SCHEDULE_DELAYED(dwc_workq_t *wq, dwc_work_callback_t cb, ++ void *data, uint32_t time, char *format, ...) + { +- int result = wait_event_interruptible(wq->queue, +- condition(data) || wq->abort); +- return check_result(wq, result); ++ dwc_irqflags_t flags; ++ work_container_t *container; ++ static char name[128]; ++ va_list args; ++ ++ va_start(args, format); ++ DWC_VSNPRINTF(name, 128, format, args); ++ va_end(args); ++ ++ DWC_SPINLOCK_IRQSAVE(wq->lock, &flags); ++ wq->pending++; ++ DWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags); ++ DWC_WAITQ_TRIGGER(wq->waitq); ++ ++ container = DWC_ALLOC_ATOMIC(sizeof(*container)); ++ if (!container) { ++ DWC_ERROR("Cannot allocate memory for container\n"); ++ return; ++ } ++ ++ container->name = DWC_STRDUP(name); ++ if (!container->name) { ++ DWC_ERROR("Cannot allocate memory for container->name\n"); ++ DWC_FREE(container); ++ return; ++ } ++ ++ container->cb = cb; ++ container->data = data; ++ container->wq = wq; ++ DWC_DEBUGC("Queueing work: %s, container=%p", container->name, container); ++ INIT_DELAYED_WORK(&container->work, do_work); ++ ++#ifdef DEBUG ++ DWC_CIRCLEQ_INSERT_TAIL(&wq->entries, container, entry); ++#endif ++ queue_delayed_work(wq->wq, &container->work, msecs_to_jiffies(time)); + } +-EXPORT_SYMBOL(DWC_WAITQ_WAIT); + +-int32_t DWC_WAITQ_WAIT_TIMEOUT(dwc_waitq_t *wq, dwc_waitq_condition_t condition, +- void *data, int32_t msecs) ++int DWC_WORKQ_PENDING(dwc_workq_t *wq) + { +- int result = wait_event_interruptible_timeout(wq->queue, +- condition(data) || wq->abort, +- msecs_to_jiffies(msecs)); +- return check_result(wq, result); ++ return wq->pending; + } ++ ++ ++#ifdef DWC_LIBMODULE ++ ++#ifdef DWC_CCLIB ++/* CC */ ++EXPORT_SYMBOL(dwc_cc_if_alloc); ++EXPORT_SYMBOL(dwc_cc_if_free); ++EXPORT_SYMBOL(dwc_cc_clear); ++EXPORT_SYMBOL(dwc_cc_add); ++EXPORT_SYMBOL(dwc_cc_remove); ++EXPORT_SYMBOL(dwc_cc_change); ++EXPORT_SYMBOL(dwc_cc_data_for_save); ++EXPORT_SYMBOL(dwc_cc_restore_from_data); ++EXPORT_SYMBOL(dwc_cc_match_chid); ++EXPORT_SYMBOL(dwc_cc_match_cdid); ++EXPORT_SYMBOL(dwc_cc_ck); ++EXPORT_SYMBOL(dwc_cc_chid); ++EXPORT_SYMBOL(dwc_cc_cdid); ++EXPORT_SYMBOL(dwc_cc_name); ++#endif /* DWC_CCLIB */ ++ ++#ifdef DWC_CRYPTOLIB ++# ifndef CONFIG_MACH_IPMATE ++/* Modpow */ ++EXPORT_SYMBOL(dwc_modpow); ++ ++/* DH */ ++EXPORT_SYMBOL(dwc_dh_modpow); ++EXPORT_SYMBOL(dwc_dh_derive_keys); ++EXPORT_SYMBOL(dwc_dh_pk); ++# endif /* CONFIG_MACH_IPMATE */ ++ ++/* Crypto */ ++EXPORT_SYMBOL(dwc_wusb_aes_encrypt); ++EXPORT_SYMBOL(dwc_wusb_cmf); ++EXPORT_SYMBOL(dwc_wusb_prf); ++EXPORT_SYMBOL(dwc_wusb_fill_ccm_nonce); ++EXPORT_SYMBOL(dwc_wusb_gen_nonce); ++EXPORT_SYMBOL(dwc_wusb_gen_key); ++EXPORT_SYMBOL(dwc_wusb_gen_mic); ++#endif /* DWC_CRYPTOLIB */ ++ ++/* Notification */ ++#ifdef DWC_NOTIFYLIB ++EXPORT_SYMBOL(dwc_alloc_notification_manager); ++EXPORT_SYMBOL(dwc_free_notification_manager); ++EXPORT_SYMBOL(dwc_register_notifier); ++EXPORT_SYMBOL(dwc_unregister_notifier); ++EXPORT_SYMBOL(dwc_add_observer); ++EXPORT_SYMBOL(dwc_remove_observer); ++EXPORT_SYMBOL(dwc_notify); ++#endif ++ ++/* Memory Debugging Routines */ ++#ifdef DWC_DEBUG_MEMORY ++EXPORT_SYMBOL(dwc_alloc_debug); ++EXPORT_SYMBOL(dwc_alloc_atomic_debug); ++EXPORT_SYMBOL(dwc_free_debug); ++EXPORT_SYMBOL(dwc_dma_alloc_debug); ++EXPORT_SYMBOL(dwc_dma_free_debug); ++#endif ++ ++EXPORT_SYMBOL(DWC_MEMSET); ++EXPORT_SYMBOL(DWC_MEMCPY); ++EXPORT_SYMBOL(DWC_MEMMOVE); ++EXPORT_SYMBOL(DWC_MEMCMP); ++EXPORT_SYMBOL(DWC_STRNCMP); ++EXPORT_SYMBOL(DWC_STRCMP); ++EXPORT_SYMBOL(DWC_STRLEN); ++EXPORT_SYMBOL(DWC_STRCPY); ++EXPORT_SYMBOL(DWC_STRDUP); ++EXPORT_SYMBOL(DWC_ATOI); ++EXPORT_SYMBOL(DWC_ATOUI); ++ ++#ifdef DWC_UTFLIB ++EXPORT_SYMBOL(DWC_UTF8_TO_UTF16LE); ++#endif /* DWC_UTFLIB */ ++ ++EXPORT_SYMBOL(DWC_IN_IRQ); ++EXPORT_SYMBOL(DWC_IN_BH); ++EXPORT_SYMBOL(DWC_VPRINTF); ++EXPORT_SYMBOL(DWC_VSNPRINTF); ++EXPORT_SYMBOL(DWC_PRINTF); ++EXPORT_SYMBOL(DWC_SPRINTF); ++EXPORT_SYMBOL(DWC_SNPRINTF); ++EXPORT_SYMBOL(__DWC_WARN); ++EXPORT_SYMBOL(__DWC_ERROR); ++EXPORT_SYMBOL(DWC_EXCEPTION); ++ ++#ifdef DEBUG ++EXPORT_SYMBOL(__DWC_DEBUG); ++#endif ++ ++EXPORT_SYMBOL(__DWC_DMA_ALLOC); ++EXPORT_SYMBOL(__DWC_DMA_ALLOC_ATOMIC); ++EXPORT_SYMBOL(__DWC_DMA_FREE); ++EXPORT_SYMBOL(__DWC_ALLOC); ++EXPORT_SYMBOL(__DWC_ALLOC_ATOMIC); ++EXPORT_SYMBOL(__DWC_FREE); ++ ++#ifdef DWC_CRYPTOLIB ++EXPORT_SYMBOL(DWC_RANDOM_BYTES); ++EXPORT_SYMBOL(DWC_AES_CBC); ++EXPORT_SYMBOL(DWC_SHA256); ++EXPORT_SYMBOL(DWC_HMAC_SHA256); ++#endif ++ ++EXPORT_SYMBOL(DWC_CPU_TO_LE32); ++EXPORT_SYMBOL(DWC_CPU_TO_BE32); ++EXPORT_SYMBOL(DWC_LE32_TO_CPU); ++EXPORT_SYMBOL(DWC_BE32_TO_CPU); ++EXPORT_SYMBOL(DWC_CPU_TO_LE16); ++EXPORT_SYMBOL(DWC_CPU_TO_BE16); ++EXPORT_SYMBOL(DWC_LE16_TO_CPU); ++EXPORT_SYMBOL(DWC_BE16_TO_CPU); ++EXPORT_SYMBOL(DWC_READ_REG32); ++EXPORT_SYMBOL(DWC_WRITE_REG32); ++EXPORT_SYMBOL(DWC_MODIFY_REG32); ++ ++#if 0 ++EXPORT_SYMBOL(DWC_READ_REG64); ++EXPORT_SYMBOL(DWC_WRITE_REG64); ++EXPORT_SYMBOL(DWC_MODIFY_REG64); ++#endif ++ ++EXPORT_SYMBOL(DWC_SPINLOCK_ALLOC); ++EXPORT_SYMBOL(DWC_SPINLOCK_FREE); ++EXPORT_SYMBOL(DWC_SPINLOCK); ++EXPORT_SYMBOL(DWC_SPINUNLOCK); ++EXPORT_SYMBOL(DWC_SPINLOCK_IRQSAVE); ++EXPORT_SYMBOL(DWC_SPINUNLOCK_IRQRESTORE); ++EXPORT_SYMBOL(DWC_MUTEX_ALLOC); ++ ++#if (!defined(DWC_LINUX) || !defined(CONFIG_DEBUG_MUTEXES)) ++EXPORT_SYMBOL(DWC_MUTEX_FREE); ++#endif ++ ++EXPORT_SYMBOL(DWC_MUTEX_LOCK); ++EXPORT_SYMBOL(DWC_MUTEX_TRYLOCK); ++EXPORT_SYMBOL(DWC_MUTEX_UNLOCK); ++EXPORT_SYMBOL(DWC_UDELAY); ++EXPORT_SYMBOL(DWC_MDELAY); ++EXPORT_SYMBOL(DWC_MSLEEP); ++EXPORT_SYMBOL(DWC_TIME); ++EXPORT_SYMBOL(DWC_TIMER_ALLOC); ++EXPORT_SYMBOL(DWC_TIMER_FREE); ++EXPORT_SYMBOL(DWC_TIMER_SCHEDULE); ++EXPORT_SYMBOL(DWC_TIMER_CANCEL); ++EXPORT_SYMBOL(DWC_WAITQ_ALLOC); ++EXPORT_SYMBOL(DWC_WAITQ_FREE); ++EXPORT_SYMBOL(DWC_WAITQ_WAIT); + EXPORT_SYMBOL(DWC_WAITQ_WAIT_TIMEOUT); ++EXPORT_SYMBOL(DWC_WAITQ_TRIGGER); ++EXPORT_SYMBOL(DWC_WAITQ_ABORT); ++EXPORT_SYMBOL(DWC_THREAD_RUN); ++EXPORT_SYMBOL(DWC_THREAD_STOP); ++EXPORT_SYMBOL(DWC_THREAD_SHOULD_STOP); ++EXPORT_SYMBOL(DWC_TASK_ALLOC); ++EXPORT_SYMBOL(DWC_TASK_FREE); ++EXPORT_SYMBOL(DWC_TASK_SCHEDULE); ++EXPORT_SYMBOL(DWC_WORKQ_WAIT_WORK_DONE); ++EXPORT_SYMBOL(DWC_WORKQ_ALLOC); ++EXPORT_SYMBOL(DWC_WORKQ_FREE); ++EXPORT_SYMBOL(DWC_WORKQ_SCHEDULE); ++EXPORT_SYMBOL(DWC_WORKQ_SCHEDULE_DELAYED); ++EXPORT_SYMBOL(DWC_WORKQ_PENDING); + +-void DWC_WAITQ_TRIGGER(dwc_waitq_t *wq) ++static int dwc_common_port_init_module(void) + { +- wake_up_interruptible(&wq->queue); ++ int result = 0; ++ ++ printk(KERN_DEBUG "Module dwc_common_port init\n" ); ++ ++#ifdef DWC_DEBUG_MEMORY ++ result = dwc_memory_debug_start(NULL); ++ if (result) { ++ printk(KERN_ERR ++ "dwc_memory_debug_start() failed with error %d\n", ++ result); ++ return result; ++ } ++#endif ++ ++#ifdef DWC_NOTIFYLIB ++ result = dwc_alloc_notification_manager(NULL, NULL); ++ if (result) { ++ printk(KERN_ERR ++ "dwc_alloc_notification_manager() failed with error %d\n", ++ result); ++ return result; ++ } ++#endif ++ return result; + } +-EXPORT_SYMBOL(DWC_WAITQ_TRIGGER); + +-void DWC_WAITQ_ABORT(dwc_waitq_t *wq) ++static void dwc_common_port_exit_module(void) + { +- wq->abort = 1; +- DWC_WAITQ_TRIGGER(wq); ++ printk(KERN_DEBUG "Module dwc_common_port exit\n" ); ++ ++#ifdef DWC_NOTIFYLIB ++ dwc_free_notification_manager(); ++#endif ++ ++#ifdef DWC_DEBUG_MEMORY ++ dwc_memory_debug_stop(); ++#endif + } +-EXPORT_SYMBOL(DWC_WAITQ_ABORT); ++ ++module_init(dwc_common_port_init_module); ++module_exit(dwc_common_port_exit_module); ++ ++MODULE_DESCRIPTION("DWC Common Library - Portable version"); ++MODULE_AUTHOR("Synopsys Inc."); ++MODULE_LICENSE ("GPL"); ++ ++#endif /* DWC_LIBMODULE */ +Index: linux-3.2.46/drivers/usb/host/dwc_common_port/dwc_common_nbsd.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_common_port/dwc_common_nbsd.c 2013-07-26 19:34:39.000000000 +0000 +@@ -0,0 +1,1275 @@ ++#include "dwc_os.h" ++#include "dwc_list.h" ++ ++#ifdef DWC_CCLIB ++# include "dwc_cc.h" ++#endif ++ ++#ifdef DWC_CRYPTOLIB ++# include "dwc_modpow.h" ++# include "dwc_dh.h" ++# include "dwc_crypto.h" ++#endif ++ ++#ifdef DWC_NOTIFYLIB ++# include "dwc_notifier.h" ++#endif ++ ++/* OS-Level Implementations */ ++ ++/* This is the NetBSD 4.0.1 kernel implementation of the DWC platform library. */ ++ ++ ++/* MISC */ ++ ++void *DWC_MEMSET(void *dest, uint8_t byte, uint32_t size) ++{ ++ return memset(dest, byte, size); ++} ++ ++void *DWC_MEMCPY(void *dest, void const *src, uint32_t size) ++{ ++ return memcpy(dest, src, size); ++} ++ ++void *DWC_MEMMOVE(void *dest, void *src, uint32_t size) ++{ ++ bcopy(src, dest, size); ++ return dest; ++} ++ ++int DWC_MEMCMP(void *m1, void *m2, uint32_t size) ++{ ++ return memcmp(m1, m2, size); ++} ++ ++int DWC_STRNCMP(void *s1, void *s2, uint32_t size) ++{ ++ return strncmp(s1, s2, size); ++} ++ ++int DWC_STRCMP(void *s1, void *s2) ++{ ++ return strcmp(s1, s2); ++} ++ ++int DWC_STRLEN(char const *str) ++{ ++ return strlen(str); ++} ++ ++char *DWC_STRCPY(char *to, char const *from) ++{ ++ return strcpy(to, from); ++} ++ ++char *DWC_STRDUP(char const *str) ++{ ++ int len = DWC_STRLEN(str) + 1; ++ char *new = DWC_ALLOC_ATOMIC(len); ++ ++ if (!new) { ++ return NULL; ++ } ++ ++ DWC_MEMCPY(new, str, len); ++ return new; ++} ++ ++int DWC_ATOI(char *str, int32_t *value) ++{ ++ char *end = NULL; ++ ++ /* NetBSD doesn't have 'strtol' in the kernel, but 'strtoul' ++ * should be equivalent on 2's complement machines ++ */ ++ *value = strtoul(str, &end, 0); ++ if (*end == '\0') { ++ return 0; ++ } ++ ++ return -1; ++} ++ ++int DWC_ATOUI(char *str, uint32_t *value) ++{ ++ char *end = NULL; ++ ++ *value = strtoul(str, &end, 0); ++ if (*end == '\0') { ++ return 0; ++ } ++ ++ return -1; ++} ++ ++ ++#ifdef DWC_UTFLIB ++/* From usbstring.c */ ++ ++int DWC_UTF8_TO_UTF16LE(uint8_t const *s, uint16_t *cp, unsigned len) ++{ ++ int count = 0; ++ u8 c; ++ u16 uchar; ++ ++ /* this insists on correct encodings, though not minimal ones. ++ * BUT it currently rejects legit 4-byte UTF-8 code points, ++ * which need surrogate pairs. (Unicode 3.1 can use them.) ++ */ ++ while (len != 0 && (c = (u8) *s++) != 0) { ++ if (unlikely(c & 0x80)) { ++ // 2-byte sequence: ++ // 00000yyyyyxxxxxx = 110yyyyy 10xxxxxx ++ if ((c & 0xe0) == 0xc0) { ++ uchar = (c & 0x1f) << 6; ++ ++ c = (u8) *s++; ++ if ((c & 0xc0) != 0xc0) ++ goto fail; ++ c &= 0x3f; ++ uchar |= c; ++ ++ // 3-byte sequence (most CJKV characters): ++ // zzzzyyyyyyxxxxxx = 1110zzzz 10yyyyyy 10xxxxxx ++ } else if ((c & 0xf0) == 0xe0) { ++ uchar = (c & 0x0f) << 12; ++ ++ c = (u8) *s++; ++ if ((c & 0xc0) != 0xc0) ++ goto fail; ++ c &= 0x3f; ++ uchar |= c << 6; ++ ++ c = (u8) *s++; ++ if ((c & 0xc0) != 0xc0) ++ goto fail; ++ c &= 0x3f; ++ uchar |= c; ++ ++ /* no bogus surrogates */ ++ if (0xd800 <= uchar && uchar <= 0xdfff) ++ goto fail; ++ ++ // 4-byte sequence (surrogate pairs, currently rare): ++ // 11101110wwwwzzzzyy + 110111yyyyxxxxxx ++ // = 11110uuu 10uuzzzz 10yyyyyy 10xxxxxx ++ // (uuuuu = wwww + 1) ++ // FIXME accept the surrogate code points (only) ++ } else ++ goto fail; ++ } else ++ uchar = c; ++ put_unaligned (cpu_to_le16 (uchar), cp++); ++ count++; ++ len--; ++ } ++ return count; ++fail: ++ return -1; ++} ++ ++#endif /* DWC_UTFLIB */ ++ ++ ++/* dwc_debug.h */ ++ ++dwc_bool_t DWC_IN_IRQ(void) ++{ ++// return in_irq(); ++ return 0; ++} ++ ++dwc_bool_t DWC_IN_BH(void) ++{ ++// return in_softirq(); ++ return 0; ++} ++ ++void DWC_VPRINTF(char *format, va_list args) ++{ ++ vprintf(format, args); ++} ++ ++int DWC_VSNPRINTF(char *str, int size, char *format, va_list args) ++{ ++ return vsnprintf(str, size, format, args); ++} ++ ++void DWC_PRINTF(char *format, ...) ++{ ++ va_list args; ++ ++ va_start(args, format); ++ DWC_VPRINTF(format, args); ++ va_end(args); ++} ++ ++int DWC_SPRINTF(char *buffer, char *format, ...) ++{ ++ int retval; ++ va_list args; ++ ++ va_start(args, format); ++ retval = vsprintf(buffer, format, args); ++ va_end(args); ++ return retval; ++} ++ ++int DWC_SNPRINTF(char *buffer, int size, char *format, ...) ++{ ++ int retval; ++ va_list args; ++ ++ va_start(args, format); ++ retval = vsnprintf(buffer, size, format, args); ++ va_end(args); ++ return retval; ++} ++ ++void __DWC_WARN(char *format, ...) ++{ ++ va_list args; ++ ++ va_start(args, format); ++ DWC_VPRINTF(format, args); ++ va_end(args); ++} ++ ++void __DWC_ERROR(char *format, ...) ++{ ++ va_list args; ++ ++ va_start(args, format); ++ DWC_VPRINTF(format, args); ++ va_end(args); ++} ++ ++void DWC_EXCEPTION(char *format, ...) ++{ ++ va_list args; ++ ++ va_start(args, format); ++ DWC_VPRINTF(format, args); ++ va_end(args); ++// BUG_ON(1); ??? ++} ++ ++#ifdef DEBUG ++void __DWC_DEBUG(char *format, ...) ++{ ++ va_list args; ++ ++ va_start(args, format); ++ DWC_VPRINTF(format, args); ++ va_end(args); ++} ++#endif ++ ++ ++/* dwc_mem.h */ ++ ++#if 0 ++dwc_pool_t *DWC_DMA_POOL_CREATE(uint32_t size, ++ uint32_t align, ++ uint32_t alloc) ++{ ++ struct dma_pool *pool = dma_pool_create("Pool", NULL, ++ size, align, alloc); ++ return (dwc_pool_t *)pool; ++} ++ ++void DWC_DMA_POOL_DESTROY(dwc_pool_t *pool) ++{ ++ dma_pool_destroy((struct dma_pool *)pool); ++} ++ ++void *DWC_DMA_POOL_ALLOC(dwc_pool_t *pool, uint64_t *dma_addr) ++{ ++// return dma_pool_alloc((struct dma_pool *)pool, GFP_KERNEL, dma_addr); ++ return dma_pool_alloc((struct dma_pool *)pool, M_WAITOK, dma_addr); ++} ++ ++void *DWC_DMA_POOL_ZALLOC(dwc_pool_t *pool, uint64_t *dma_addr) ++{ ++ void *vaddr = DWC_DMA_POOL_ALLOC(pool, dma_addr); ++ memset(..); ++} ++ ++void DWC_DMA_POOL_FREE(dwc_pool_t *pool, void *vaddr, void *daddr) ++{ ++ dma_pool_free(pool, vaddr, daddr); ++} ++#endif ++ ++void *__DWC_DMA_ALLOC(void *dma_ctx, uint32_t size, dwc_dma_t *dma_addr) ++{ ++ dwc_dmactx_t *dma = (dwc_dmactx_t *)dma_ctx; ++ int error; ++ ++ error = bus_dmamem_alloc(dma->dma_tag, size, 1, size, dma->segs, ++ sizeof(dma->segs) / sizeof(dma->segs[0]), ++ &dma->nsegs, BUS_DMA_NOWAIT); ++ if (error) { ++ printf("%s: bus_dmamem_alloc(%ju) failed: %d\n", __func__, ++ (uintmax_t)size, error); ++ goto fail_0; ++ } ++ ++ error = bus_dmamem_map(dma->dma_tag, dma->segs, dma->nsegs, size, ++ (caddr_t *)&dma->dma_vaddr, ++ BUS_DMA_NOWAIT | BUS_DMA_COHERENT); ++ if (error) { ++ printf("%s: bus_dmamem_map failed: %d\n", __func__, error); ++ goto fail_1; ++ } ++ ++ error = bus_dmamap_create(dma->dma_tag, size, 1, size, 0, ++ BUS_DMA_NOWAIT, &dma->dma_map); ++ if (error) { ++ printf("%s: bus_dmamap_create failed: %d\n", __func__, error); ++ goto fail_2; ++ } ++ ++ error = bus_dmamap_load(dma->dma_tag, dma->dma_map, dma->dma_vaddr, ++ size, NULL, BUS_DMA_NOWAIT); ++ if (error) { ++ printf("%s: bus_dmamap_load failed: %d\n", __func__, error); ++ goto fail_3; ++ } ++ ++ dma->dma_paddr = (bus_addr_t)dma->segs[0].ds_addr; ++ *dma_addr = dma->dma_paddr; ++ return dma->dma_vaddr; ++ ++fail_3: ++ bus_dmamap_destroy(dma->dma_tag, dma->dma_map); ++fail_2: ++ bus_dmamem_unmap(dma->dma_tag, dma->dma_vaddr, size); ++fail_1: ++ bus_dmamem_free(dma->dma_tag, dma->segs, dma->nsegs); ++fail_0: ++ dma->dma_map = NULL; ++ dma->dma_vaddr = NULL; ++ dma->nsegs = 0; ++ ++ return NULL; ++} ++ ++void __DWC_DMA_FREE(void *dma_ctx, uint32_t size, void *virt_addr, dwc_dma_t dma_addr) ++{ ++ dwc_dmactx_t *dma = (dwc_dmactx_t *)dma_ctx; ++ ++ if (dma->dma_map != NULL) { ++ bus_dmamap_sync(dma->dma_tag, dma->dma_map, 0, size, ++ BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); ++ bus_dmamap_unload(dma->dma_tag, dma->dma_map); ++ bus_dmamap_destroy(dma->dma_tag, dma->dma_map); ++ bus_dmamem_unmap(dma->dma_tag, dma->dma_vaddr, size); ++ bus_dmamem_free(dma->dma_tag, dma->segs, dma->nsegs); ++ dma->dma_paddr = 0; ++ dma->dma_map = NULL; ++ dma->dma_vaddr = NULL; ++ dma->nsegs = 0; ++ } ++} ++ ++void *__DWC_ALLOC(void *mem_ctx, uint32_t size) ++{ ++ return malloc(size, M_DEVBUF, M_WAITOK | M_ZERO); ++} ++ ++void *__DWC_ALLOC_ATOMIC(void *mem_ctx, uint32_t size) ++{ ++ return malloc(size, M_DEVBUF, M_NOWAIT | M_ZERO); ++} ++ ++void __DWC_FREE(void *mem_ctx, void *addr) ++{ ++ free(addr, M_DEVBUF); ++} ++ ++ ++#ifdef DWC_CRYPTOLIB ++/* dwc_crypto.h */ ++ ++void DWC_RANDOM_BYTES(uint8_t *buffer, uint32_t length) ++{ ++ get_random_bytes(buffer, length); ++} ++ ++int DWC_AES_CBC(uint8_t *message, uint32_t messagelen, uint8_t *key, uint32_t keylen, uint8_t iv[16], uint8_t *out) ++{ ++ struct crypto_blkcipher *tfm; ++ struct blkcipher_desc desc; ++ struct scatterlist sgd; ++ struct scatterlist sgs; ++ ++ tfm = crypto_alloc_blkcipher("cbc(aes)", 0, CRYPTO_ALG_ASYNC); ++ if (tfm == NULL) { ++ printk("failed to load transform for aes CBC\n"); ++ return -1; ++ } ++ ++ crypto_blkcipher_setkey(tfm, key, keylen); ++ crypto_blkcipher_set_iv(tfm, iv, 16); ++ ++ sg_init_one(&sgd, out, messagelen); ++ sg_init_one(&sgs, message, messagelen); ++ ++ desc.tfm = tfm; ++ desc.flags = 0; ++ ++ if (crypto_blkcipher_encrypt(&desc, &sgd, &sgs, messagelen)) { ++ crypto_free_blkcipher(tfm); ++ DWC_ERROR("AES CBC encryption failed"); ++ return -1; ++ } ++ ++ crypto_free_blkcipher(tfm); ++ return 0; ++} ++ ++int DWC_SHA256(uint8_t *message, uint32_t len, uint8_t *out) ++{ ++ struct crypto_hash *tfm; ++ struct hash_desc desc; ++ struct scatterlist sg; ++ ++ tfm = crypto_alloc_hash("sha256", 0, CRYPTO_ALG_ASYNC); ++ if (IS_ERR(tfm)) { ++ DWC_ERROR("Failed to load transform for sha256: %ld", PTR_ERR(tfm)); ++ return 0; ++ } ++ desc.tfm = tfm; ++ desc.flags = 0; ++ ++ sg_init_one(&sg, message, len); ++ crypto_hash_digest(&desc, &sg, len, out); ++ crypto_free_hash(tfm); ++ ++ return 1; ++} ++ ++int DWC_HMAC_SHA256(uint8_t *message, uint32_t messagelen, ++ uint8_t *key, uint32_t keylen, uint8_t *out) ++{ ++ struct crypto_hash *tfm; ++ struct hash_desc desc; ++ struct scatterlist sg; ++ ++ tfm = crypto_alloc_hash("hmac(sha256)", 0, CRYPTO_ALG_ASYNC); ++ if (IS_ERR(tfm)) { ++ DWC_ERROR("Failed to load transform for hmac(sha256): %ld", PTR_ERR(tfm)); ++ return 0; ++ } ++ desc.tfm = tfm; ++ desc.flags = 0; ++ ++ sg_init_one(&sg, message, messagelen); ++ crypto_hash_setkey(tfm, key, keylen); ++ crypto_hash_digest(&desc, &sg, messagelen, out); ++ crypto_free_hash(tfm); ++ ++ return 1; ++} ++ ++#endif /* DWC_CRYPTOLIB */ ++ ++ ++/* Byte Ordering Conversions */ ++ ++uint32_t DWC_CPU_TO_LE32(uint32_t *p) ++{ ++#ifdef __LITTLE_ENDIAN ++ return *p; ++#else ++ uint8_t *u_p = (uint8_t *)p; ++ ++ return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24)); ++#endif ++} ++ ++uint32_t DWC_CPU_TO_BE32(uint32_t *p) ++{ ++#ifdef __BIG_ENDIAN ++ return *p; ++#else ++ uint8_t *u_p = (uint8_t *)p; ++ ++ return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24)); ++#endif ++} ++ ++uint32_t DWC_LE32_TO_CPU(uint32_t *p) ++{ ++#ifdef __LITTLE_ENDIAN ++ return *p; ++#else ++ uint8_t *u_p = (uint8_t *)p; ++ ++ return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24)); ++#endif ++} ++ ++uint32_t DWC_BE32_TO_CPU(uint32_t *p) ++{ ++#ifdef __BIG_ENDIAN ++ return *p; ++#else ++ uint8_t *u_p = (uint8_t *)p; ++ ++ return (u_p[3] | (u_p[2] << 8) | (u_p[1] << 16) | (u_p[0] << 24)); ++#endif ++} ++ ++uint16_t DWC_CPU_TO_LE16(uint16_t *p) ++{ ++#ifdef __LITTLE_ENDIAN ++ return *p; ++#else ++ uint8_t *u_p = (uint8_t *)p; ++ return (u_p[1] | (u_p[0] << 8)); ++#endif ++} ++ ++uint16_t DWC_CPU_TO_BE16(uint16_t *p) ++{ ++#ifdef __BIG_ENDIAN ++ return *p; ++#else ++ uint8_t *u_p = (uint8_t *)p; ++ return (u_p[1] | (u_p[0] << 8)); ++#endif ++} ++ ++uint16_t DWC_LE16_TO_CPU(uint16_t *p) ++{ ++#ifdef __LITTLE_ENDIAN ++ return *p; ++#else ++ uint8_t *u_p = (uint8_t *)p; ++ return (u_p[1] | (u_p[0] << 8)); ++#endif ++} ++ ++uint16_t DWC_BE16_TO_CPU(uint16_t *p) ++{ ++#ifdef __BIG_ENDIAN ++ return *p; ++#else ++ uint8_t *u_p = (uint8_t *)p; ++ return (u_p[1] | (u_p[0] << 8)); ++#endif ++} ++ ++ ++/* Registers */ ++ ++uint32_t DWC_READ_REG32(void *io_ctx, uint32_t volatile *reg) ++{ ++ dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx; ++ bus_size_t ior = (bus_size_t)reg; ++ ++ return bus_space_read_4(io->iot, io->ioh, ior); ++} ++ ++#if 0 ++uint64_t DWC_READ_REG64(void *io_ctx, uint64_t volatile *reg) ++{ ++ dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx; ++ bus_size_t ior = (bus_size_t)reg; ++ ++ return bus_space_read_8(io->iot, io->ioh, ior); ++} ++#endif ++ ++void DWC_WRITE_REG32(void *io_ctx, uint32_t volatile *reg, uint32_t value) ++{ ++ dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx; ++ bus_size_t ior = (bus_size_t)reg; ++ ++ bus_space_write_4(io->iot, io->ioh, ior, value); ++} ++ ++#if 0 ++void DWC_WRITE_REG64(void *io_ctx, uint64_t volatile *reg, uint64_t value) ++{ ++ dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx; ++ bus_size_t ior = (bus_size_t)reg; ++ ++ bus_space_write_8(io->iot, io->ioh, ior, value); ++} ++#endif ++ ++void DWC_MODIFY_REG32(void *io_ctx, uint32_t volatile *reg, uint32_t clear_mask, ++ uint32_t set_mask) ++{ ++ dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx; ++ bus_size_t ior = (bus_size_t)reg; ++ ++ bus_space_write_4(io->iot, io->ioh, ior, ++ (bus_space_read_4(io->iot, io->ioh, ior) & ++ ~clear_mask) | set_mask); ++} ++ ++#if 0 ++void DWC_MODIFY_REG64(void *io_ctx, uint64_t volatile *reg, uint64_t clear_mask, ++ uint64_t set_mask) ++{ ++ dwc_ioctx_t *io = (dwc_ioctx_t *)io_ctx; ++ bus_size_t ior = (bus_size_t)reg; ++ ++ bus_space_write_8(io->iot, io->ioh, ior, ++ (bus_space_read_8(io->iot, io->ioh, ior) & ++ ~clear_mask) | set_mask); ++} ++#endif ++ ++ ++/* Locking */ ++ ++dwc_spinlock_t *DWC_SPINLOCK_ALLOC(void) ++{ ++ struct simplelock *sl = DWC_ALLOC(sizeof(*sl)); ++ ++ if (!sl) { ++ DWC_ERROR("Cannot allocate memory for spinlock"); ++ return NULL; ++ } ++ ++ simple_lock_init(sl); ++ return (dwc_spinlock_t *)sl; ++} ++ ++void DWC_SPINLOCK_FREE(dwc_spinlock_t *lock) ++{ ++ struct simplelock *sl = (struct simplelock *)lock; ++ ++ DWC_FREE(sl); ++} ++ ++void DWC_SPINLOCK(dwc_spinlock_t *lock) ++{ ++ simple_lock((struct simplelock *)lock); ++} ++ ++void DWC_SPINUNLOCK(dwc_spinlock_t *lock) ++{ ++ simple_unlock((struct simplelock *)lock); ++} ++ ++void DWC_SPINLOCK_IRQSAVE(dwc_spinlock_t *lock, dwc_irqflags_t *flags) ++{ ++ simple_lock((struct simplelock *)lock); ++ *flags = splbio(); ++} ++ ++void DWC_SPINUNLOCK_IRQRESTORE(dwc_spinlock_t *lock, dwc_irqflags_t flags) ++{ ++ splx(flags); ++ simple_unlock((struct simplelock *)lock); ++} ++ ++dwc_mutex_t *DWC_MUTEX_ALLOC(void) ++{ ++ dwc_mutex_t *mutex = DWC_ALLOC(sizeof(struct lock)); ++ ++ if (!mutex) { ++ DWC_ERROR("Cannot allocate memory for mutex"); ++ return NULL; ++ } ++ ++ lockinit((struct lock *)mutex, 0, "dw3mtx", 0, 0); ++ return mutex; ++} ++ ++#if (defined(DWC_LINUX) && defined(CONFIG_DEBUG_MUTEXES)) ++#else ++void DWC_MUTEX_FREE(dwc_mutex_t *mutex) ++{ ++ DWC_FREE(mutex); ++} ++#endif ++ ++void DWC_MUTEX_LOCK(dwc_mutex_t *mutex) ++{ ++ lockmgr((struct lock *)mutex, LK_EXCLUSIVE, NULL); ++} ++ ++int DWC_MUTEX_TRYLOCK(dwc_mutex_t *mutex) ++{ ++ int status; ++ ++ status = lockmgr((struct lock *)mutex, LK_EXCLUSIVE | LK_NOWAIT, NULL); ++ return status == 0; ++} ++ ++void DWC_MUTEX_UNLOCK(dwc_mutex_t *mutex) ++{ ++ lockmgr((struct lock *)mutex, LK_RELEASE, NULL); ++} ++ ++ ++/* Timing */ ++ ++void DWC_UDELAY(uint32_t usecs) ++{ ++ DELAY(usecs); ++} ++ ++void DWC_MDELAY(uint32_t msecs) ++{ ++ do { ++ DELAY(1000); ++ } while (--msecs); ++} ++ ++void DWC_MSLEEP(uint32_t msecs) ++{ ++ struct timeval tv; ++ ++ tv.tv_sec = msecs / 1000; ++ tv.tv_usec = (msecs - tv.tv_sec * 1000) * 1000; ++ tsleep(&tv, 0, "dw3slp", tvtohz(&tv)); ++} ++ ++uint32_t DWC_TIME(void) ++{ ++ struct timeval tv; ++ ++ microuptime(&tv); // or getmicrouptime? (less precise, but faster) ++ return tv.tv_sec * 1000 + tv.tv_usec / 1000; ++} ++ ++ ++/* Timers */ ++ ++struct dwc_timer { ++ struct callout t; ++ char *name; ++ dwc_spinlock_t *lock; ++ dwc_timer_callback_t cb; ++ void *data; ++}; ++ ++dwc_timer_t *DWC_TIMER_ALLOC(char *name, dwc_timer_callback_t cb, void *data) ++{ ++ dwc_timer_t *t = DWC_ALLOC(sizeof(*t)); ++ ++ if (!t) { ++ DWC_ERROR("Cannot allocate memory for timer"); ++ return NULL; ++ } ++ ++ callout_init(&t->t); ++ ++ t->name = DWC_STRDUP(name); ++ if (!t->name) { ++ DWC_ERROR("Cannot allocate memory for timer->name"); ++ goto no_name; ++ } ++ ++ t->lock = DWC_SPINLOCK_ALLOC(); ++ if (!t->lock) { ++ DWC_ERROR("Cannot allocate memory for timer->lock"); ++ goto no_lock; ++ } ++ ++ t->cb = cb; ++ t->data = data; ++ ++ return t; ++ ++ no_lock: ++ DWC_FREE(t->name); ++ no_name: ++ DWC_FREE(t); ++ ++ return NULL; ++} ++ ++void DWC_TIMER_FREE(dwc_timer_t *timer) ++{ ++ callout_stop(&timer->t); ++ DWC_SPINLOCK_FREE(timer->lock); ++ DWC_FREE(timer->name); ++ DWC_FREE(timer); ++} ++ ++void DWC_TIMER_SCHEDULE(dwc_timer_t *timer, uint32_t time) ++{ ++ struct timeval tv; ++ ++ tv.tv_sec = time / 1000; ++ tv.tv_usec = (time - tv.tv_sec * 1000) * 1000; ++ callout_reset(&timer->t, tvtohz(&tv), timer->cb, timer->data); ++} ++ ++void DWC_TIMER_CANCEL(dwc_timer_t *timer) ++{ ++ callout_stop(&timer->t); ++} ++ ++ ++/* Wait Queues */ ++ ++struct dwc_waitq { ++ struct simplelock lock; ++ int abort; ++}; ++ ++dwc_waitq_t *DWC_WAITQ_ALLOC(void) ++{ ++ dwc_waitq_t *wq = DWC_ALLOC(sizeof(*wq)); ++ ++ if (!wq) { ++ DWC_ERROR("Cannot allocate memory for waitqueue"); ++ return NULL; ++ } ++ ++ simple_lock_init(&wq->lock); ++ wq->abort = 0; ++ ++ return wq; ++} ++ ++void DWC_WAITQ_FREE(dwc_waitq_t *wq) ++{ ++ DWC_FREE(wq); ++} ++ ++int32_t DWC_WAITQ_WAIT(dwc_waitq_t *wq, dwc_waitq_condition_t cond, void *data) ++{ ++ int ipl; ++ int result = 0; ++ ++ simple_lock(&wq->lock); ++ ipl = splbio(); ++ ++ /* Skip the sleep if already aborted or triggered */ ++ if (!wq->abort && !cond(data)) { ++ splx(ipl); ++ result = ltsleep(wq, PCATCH, "dw3wat", 0, &wq->lock); // infinite timeout ++ ipl = splbio(); ++ } ++ ++ if (result == 0) { // awoken ++ if (wq->abort) { ++ wq->abort = 0; ++ result = -DWC_E_ABORT; ++ } else { ++ result = 0; ++ } ++ ++ splx(ipl); ++ simple_unlock(&wq->lock); ++ } else { ++ wq->abort = 0; ++ splx(ipl); ++ simple_unlock(&wq->lock); ++ ++ if (result == ERESTART) { // signaled - restart ++ result = -DWC_E_RESTART; ++ } else { // signaled - must be EINTR ++ result = -DWC_E_ABORT; ++ } ++ } ++ ++ return result; ++} ++ ++int32_t DWC_WAITQ_WAIT_TIMEOUT(dwc_waitq_t *wq, dwc_waitq_condition_t cond, ++ void *data, int32_t msecs) ++{ ++ struct timeval tv, tv1, tv2; ++ int ipl; ++ int result = 0; ++ ++ tv.tv_sec = msecs / 1000; ++ tv.tv_usec = (msecs - tv.tv_sec * 1000) * 1000; ++ ++ simple_lock(&wq->lock); ++ ipl = splbio(); ++ ++ /* Skip the sleep if already aborted or triggered */ ++ if (!wq->abort && !cond(data)) { ++ splx(ipl); ++ getmicrouptime(&tv1); ++ result = ltsleep(wq, PCATCH, "dw3wto", tvtohz(&tv), &wq->lock); ++ getmicrouptime(&tv2); ++ ipl = splbio(); ++ } ++ ++ if (result == 0) { // awoken ++ if (wq->abort) { ++ wq->abort = 0; ++ splx(ipl); ++ simple_unlock(&wq->lock); ++ result = -DWC_E_ABORT; ++ } else { ++ splx(ipl); ++ simple_unlock(&wq->lock); ++ ++ tv2.tv_usec -= tv1.tv_usec; ++ if (tv2.tv_usec < 0) { ++ tv2.tv_usec += 1000000; ++ tv2.tv_sec--; ++ } ++ ++ tv2.tv_sec -= tv1.tv_sec; ++ result = tv2.tv_sec * 1000 + tv2.tv_usec / 1000; ++ result = msecs - result; ++ if (result <= 0) ++ result = 1; ++ } ++ } else { ++ wq->abort = 0; ++ splx(ipl); ++ simple_unlock(&wq->lock); ++ ++ if (result == ERESTART) { // signaled - restart ++ result = -DWC_E_RESTART; ++ ++ } else if (result == EINTR) { // signaled - interrupt ++ result = -DWC_E_ABORT; ++ ++ } else { // timed out ++ result = -DWC_E_TIMEOUT; ++ } ++ } ++ ++ return result; ++} ++ ++void DWC_WAITQ_TRIGGER(dwc_waitq_t *wq) ++{ ++ wakeup(wq); ++} ++ ++void DWC_WAITQ_ABORT(dwc_waitq_t *wq) ++{ ++ int ipl; ++ ++ simple_lock(&wq->lock); ++ ipl = splbio(); ++ wq->abort = 1; ++ wakeup(wq); ++ splx(ipl); ++ simple_unlock(&wq->lock); ++} ++ ++ ++/* Threading */ ++ ++struct dwc_thread { ++ struct proc *proc; ++ int abort; ++}; ++ ++dwc_thread_t *DWC_THREAD_RUN(dwc_thread_function_t func, char *name, void *data) ++{ ++ int retval; ++ dwc_thread_t *thread = DWC_ALLOC(sizeof(*thread)); ++ ++ if (!thread) { ++ return NULL; ++ } ++ ++ thread->abort = 0; ++ retval = kthread_create1((void (*)(void *))func, data, &thread->proc, ++ "%s", name); ++ if (retval) { ++ DWC_FREE(thread); ++ return NULL; ++ } ++ ++ return thread; ++} ++ ++int DWC_THREAD_STOP(dwc_thread_t *thread) ++{ ++ int retval; ++ ++ thread->abort = 1; ++ retval = tsleep(&thread->abort, 0, "dw3stp", 60 * hz); ++ ++ if (retval == 0) { ++ /* DWC_THREAD_EXIT() will free the thread struct */ ++ return 0; ++ } ++ ++ /* NOTE: We leak the thread struct if thread doesn't die */ ++ ++ if (retval == EWOULDBLOCK) { ++ return -DWC_E_TIMEOUT; ++ } ++ ++ return -DWC_E_UNKNOWN; ++} ++ ++dwc_bool_t DWC_THREAD_SHOULD_STOP(dwc_thread_t *thread) ++{ ++ return thread->abort; ++} ++ ++void DWC_THREAD_EXIT(dwc_thread_t *thread) ++{ ++ wakeup(&thread->abort); ++ DWC_FREE(thread); ++ kthread_exit(0); ++} ++ ++/* tasklets ++ - Runs in interrupt context (cannot sleep) ++ - Each tasklet runs on a single CPU ++ - Different tasklets can be running simultaneously on different CPUs ++ [ On NetBSD there is no corresponding mechanism, drivers don't have bottom- ++ halves. So we just call the callback directly from DWC_TASK_SCHEDULE() ] ++ */ ++struct dwc_tasklet { ++ dwc_tasklet_callback_t cb; ++ void *data; ++}; ++ ++static void tasklet_callback(void *data) ++{ ++ dwc_tasklet_t *task = (dwc_tasklet_t *)data; ++ ++ task->cb(task->data); ++} ++ ++dwc_tasklet_t *DWC_TASK_ALLOC(char *name, dwc_tasklet_callback_t cb, void *data) ++{ ++ dwc_tasklet_t *task = DWC_ALLOC(sizeof(*task)); ++ ++ if (task) { ++ task->cb = cb; ++ task->data = data; ++ } else { ++ DWC_ERROR("Cannot allocate memory for tasklet"); ++ } ++ ++ return task; ++} ++ ++void DWC_TASK_FREE(dwc_tasklet_t *task) ++{ ++ DWC_FREE(task); ++} ++ ++void DWC_TASK_SCHEDULE(dwc_tasklet_t *task) ++{ ++ tasklet_callback(task); ++} ++ ++ ++/* workqueues ++ - Runs in process context (can sleep) ++ */ ++typedef struct work_container { ++ dwc_work_callback_t cb; ++ void *data; ++ dwc_workq_t *wq; ++ char *name; ++ int hz; ++ struct work task; ++} work_container_t; ++ ++struct dwc_workq { ++ struct workqueue *taskq; ++ dwc_spinlock_t *lock; ++ dwc_waitq_t *waitq; ++ int pending; ++ struct work_container *container; ++}; ++ ++static void do_work(struct work *task, void *data) ++{ ++ dwc_workq_t *wq = (dwc_workq_t *)data; ++ work_container_t *container = wq->container; ++ dwc_irqflags_t flags; ++ ++ if (container->hz) { ++ tsleep(container, 0, "dw3wrk", container->hz); ++ } ++ ++ container->cb(container->data); ++ DWC_DEBUG("Work done: %s, container=%p", container->name, container); ++ ++ DWC_SPINLOCK_IRQSAVE(wq->lock, &flags); ++ if (container->name) ++ DWC_FREE(container->name); ++ DWC_FREE(container); ++ wq->pending--; ++ DWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags); ++ DWC_WAITQ_TRIGGER(wq->waitq); ++} ++ ++static int work_done(void *data) ++{ ++ dwc_workq_t *workq = (dwc_workq_t *)data; ++ ++ return workq->pending == 0; ++} ++ ++int DWC_WORKQ_WAIT_WORK_DONE(dwc_workq_t *workq, int timeout) ++{ ++ return DWC_WAITQ_WAIT_TIMEOUT(workq->waitq, work_done, workq, timeout); ++} ++ ++dwc_workq_t *DWC_WORKQ_ALLOC(char *name) ++{ ++ int result; ++ dwc_workq_t *wq = DWC_ALLOC(sizeof(*wq)); ++ ++ if (!wq) { ++ DWC_ERROR("Cannot allocate memory for workqueue"); ++ return NULL; ++ } ++ ++ result = workqueue_create(&wq->taskq, name, do_work, wq, 0 /*PWAIT*/, ++ IPL_BIO, 0); ++ if (result) { ++ DWC_ERROR("Cannot create workqueue"); ++ goto no_taskq; ++ } ++ ++ wq->pending = 0; ++ ++ wq->lock = DWC_SPINLOCK_ALLOC(); ++ if (!wq->lock) { ++ DWC_ERROR("Cannot allocate memory for spinlock"); ++ goto no_lock; ++ } ++ ++ wq->waitq = DWC_WAITQ_ALLOC(); ++ if (!wq->waitq) { ++ DWC_ERROR("Cannot allocate memory for waitqueue"); ++ goto no_waitq; ++ } ++ ++ return wq; ++ ++ no_waitq: ++ DWC_SPINLOCK_FREE(wq->lock); ++ no_lock: ++ workqueue_destroy(wq->taskq); ++ no_taskq: ++ DWC_FREE(wq); ++ ++ return NULL; ++} ++ ++void DWC_WORKQ_FREE(dwc_workq_t *wq) ++{ ++#ifdef DEBUG ++ dwc_irqflags_t flags; ++ ++ DWC_SPINLOCK_IRQSAVE(wq->lock, &flags); ++ ++ if (wq->pending != 0) { ++ struct work_container *container = wq->container; ++ ++ DWC_ERROR("Destroying work queue with pending work"); ++ ++ if (container && container->name) { ++ DWC_ERROR("Work %s still pending", container->name); ++ } ++ } ++ ++ DWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags); ++#endif ++ DWC_WAITQ_FREE(wq->waitq); ++ DWC_SPINLOCK_FREE(wq->lock); ++ workqueue_destroy(wq->taskq); ++ DWC_FREE(wq); ++} ++ ++void DWC_WORKQ_SCHEDULE(dwc_workq_t *wq, dwc_work_callback_t cb, void *data, ++ char *format, ...) ++{ ++ dwc_irqflags_t flags; ++ work_container_t *container; ++ static char name[128]; ++ va_list args; ++ ++ va_start(args, format); ++ DWC_VSNPRINTF(name, 128, format, args); ++ va_end(args); ++ ++ DWC_SPINLOCK_IRQSAVE(wq->lock, &flags); ++ wq->pending++; ++ DWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags); ++ DWC_WAITQ_TRIGGER(wq->waitq); ++ ++ container = DWC_ALLOC_ATOMIC(sizeof(*container)); ++ if (!container) { ++ DWC_ERROR("Cannot allocate memory for container"); ++ return; ++ } ++ ++ container->name = DWC_STRDUP(name); ++ if (!container->name) { ++ DWC_ERROR("Cannot allocate memory for container->name"); ++ DWC_FREE(container); ++ return; ++ } ++ ++ container->cb = cb; ++ container->data = data; ++ container->wq = wq; ++ container->hz = 0; ++ wq->container = container; ++ ++ DWC_DEBUG("Queueing work: %s, container=%p", container->name, container); ++ workqueue_enqueue(wq->taskq, &container->task); ++} ++ ++void DWC_WORKQ_SCHEDULE_DELAYED(dwc_workq_t *wq, dwc_work_callback_t cb, ++ void *data, uint32_t time, char *format, ...) ++{ ++ dwc_irqflags_t flags; ++ work_container_t *container; ++ static char name[128]; ++ struct timeval tv; ++ va_list args; ++ ++ va_start(args, format); ++ DWC_VSNPRINTF(name, 128, format, args); ++ va_end(args); ++ ++ DWC_SPINLOCK_IRQSAVE(wq->lock, &flags); ++ wq->pending++; ++ DWC_SPINUNLOCK_IRQRESTORE(wq->lock, flags); ++ DWC_WAITQ_TRIGGER(wq->waitq); ++ ++ container = DWC_ALLOC_ATOMIC(sizeof(*container)); ++ if (!container) { ++ DWC_ERROR("Cannot allocate memory for container"); ++ return; ++ } ++ ++ container->name = DWC_STRDUP(name); ++ if (!container->name) { ++ DWC_ERROR("Cannot allocate memory for container->name"); ++ DWC_FREE(container); ++ return; ++ } ++ ++ container->cb = cb; ++ container->data = data; ++ container->wq = wq; ++ tv.tv_sec = time / 1000; ++ tv.tv_usec = (time - tv.tv_sec * 1000) * 1000; ++ container->hz = tvtohz(&tv); ++ wq->container = container; ++ ++ DWC_DEBUG("Queueing work: %s, container=%p", container->name, container); ++ workqueue_enqueue(wq->taskq, &container->task); ++} ++ ++int DWC_WORKQ_PENDING(dwc_workq_t *wq) ++{ ++ return wq->pending; ++} +Index: linux-3.2.46/drivers/usb/host/dwc_common_port/dwc_crypto.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_common_port/dwc_crypto.c 2013-07-26 19:34:39.000000000 +0000 +@@ -0,0 +1,308 @@ ++/* ========================================================================= ++ * $File: //dwh/usb_iip/dev/software/dwc_common_port_2/dwc_crypto.c $ ++ * $Revision: #5 $ ++ * $Date: 2010/09/28 $ ++ * $Change: 1596182 $ ++ * ++ * Synopsys Portability Library Software and documentation ++ * (hereinafter, "Software") is an Unsupported proprietary work of ++ * Synopsys, Inc. unless otherwise expressly agreed to in writing ++ * between Synopsys and you. ++ * ++ * The Software IS NOT an item of Licensed Software or Licensed Product ++ * under any End User Software License Agreement or Agreement for ++ * Licensed Product with Synopsys or any supplement thereto. You are ++ * permitted to use and redistribute this Software in source and binary ++ * forms, with or without modification, provided that redistributions ++ * of source code must retain this notice. You may not view, use, ++ * disclose, copy or distribute this file or any information contained ++ * herein except pursuant to this license grant from Synopsys. If you ++ * do not agree with this notice, including the disclaimer below, then ++ * you are not authorized to use the Software. ++ * ++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" ++ * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT ++ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ++ * FOR A PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL ++ * SYNOPSYS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, ++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, ++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR ++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY ++ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE ++ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH ++ * DAMAGE. ++ * ========================================================================= */ ++ ++/** @file ++ * This file contains the WUSB cryptographic routines. ++ */ ++ ++#ifdef DWC_CRYPTOLIB ++ ++#include "dwc_crypto.h" ++#include "usb.h" ++ ++#ifdef DEBUG ++static inline void dump_bytes(char *name, uint8_t *bytes, int len) ++{ ++ int i; ++ DWC_PRINTF("%s: ", name); ++ for (i=0; idst == src, then the bytes will be encrypted ++ * in-place. ++ * ++ * @return 0 on success, negative error code on error. ++ */ ++int dwc_wusb_aes_encrypt(u8 *src, u8 *key, u8 *dst) ++{ ++ u8 block_t[16]; ++ DWC_MEMSET(block_t, 0, 16); ++ ++ return DWC_AES_CBC(src, 16, key, 16, block_t, dst); ++} ++ ++/** ++ * The CCM-MAC-FUNCTION described in section 6.5 of the WUSB spec. ++ * This function takes a data string and returns the encrypted CBC ++ * Counter-mode MIC. ++ * ++ * @param key The 128-bit symmetric key. ++ * @param nonce The CCM nonce. ++ * @param label The unique 14-byte ASCII text label. ++ * @param bytes The byte array to be encrypted. ++ * @param len Length of the byte array. ++ * @param result Byte array to receive the 8-byte encrypted MIC. ++ */ ++void dwc_wusb_cmf(u8 *key, u8 *nonce, ++ char *label, u8 *bytes, int len, u8 *result) ++{ ++ u8 block_m[16]; ++ u8 block_x[16]; ++ u8 block_t[8]; ++ int idx, blkNum; ++ u16 la = (u16)(len + 14); ++ ++ /* Set the AES-128 key */ ++ //dwc_aes_setkey(tfm, key, 16); ++ ++ /* Fill block B0 from flags = 0x59, N, and l(m) = 0 */ ++ block_m[0] = 0x59; ++ for (idx = 0; idx < 13; idx++) ++ block_m[idx + 1] = nonce[idx]; ++ block_m[14] = 0; ++ block_m[15] = 0; ++ ++ /* Produce the CBC IV */ ++ dwc_wusb_aes_encrypt(block_m, key, block_x); ++ show_block(block_m, "CBC IV in: ", "\n", 0); ++ show_block(block_x, "CBC IV out:", "\n", 0); ++ ++ /* Fill block B1 from l(a) = Blen + 14, and A */ ++ block_x[0] ^= (u8)(la >> 8); ++ block_x[1] ^= (u8)la; ++ for (idx = 0; idx < 14; idx++) ++ block_x[idx + 2] ^= label[idx]; ++ show_block(block_x, "After xor: ", "b1\n", 16); ++ ++ dwc_wusb_aes_encrypt(block_x, key, block_x); ++ show_block(block_x, "After AES: ", "b1\n", 16); ++ ++ idx = 0; ++ blkNum = 0; ++ ++ /* Fill remaining blocks with B */ ++ while (len-- > 0) { ++ block_x[idx] ^= *bytes++; ++ if (++idx >= 16) { ++ idx = 0; ++ show_block(block_x, "After xor: ", "\n", blkNum); ++ dwc_wusb_aes_encrypt(block_x, key, block_x); ++ show_block(block_x, "After AES: ", "\n", blkNum); ++ blkNum++; ++ } ++ } ++ ++ /* Handle partial last block */ ++ if (idx > 0) { ++ show_block(block_x, "After xor: ", "\n", blkNum); ++ dwc_wusb_aes_encrypt(block_x, key, block_x); ++ show_block(block_x, "After AES: ", "\n", blkNum); ++ } ++ ++ /* Save the MIC tag */ ++ DWC_MEMCPY(block_t, block_x, 8); ++ show_block(block_t, "MIC tag : ", NULL, 8); ++ ++ /* Fill block A0 from flags = 0x01, N, and counter = 0 */ ++ block_m[0] = 0x01; ++ block_m[14] = 0; ++ block_m[15] = 0; ++ ++ /* Encrypt the counter */ ++ dwc_wusb_aes_encrypt(block_m, key, block_x); ++ show_block(block_x, "CTR[MIC] : ", NULL, 8); ++ ++ /* XOR with MIC tag */ ++ for (idx = 0; idx < 8; idx++) { ++ block_t[idx] ^= block_x[idx]; ++ } ++ ++ /* Return result to caller */ ++ DWC_MEMCPY(result, block_t, 8); ++ show_block(result, "CCM-MIC : ", NULL, 8); ++ ++} ++ ++/** ++ * The PRF function described in section 6.5 of the WUSB spec. This function ++ * concatenates MIC values returned from dwc_cmf() to create a value of ++ * the requested length. ++ * ++ * @param prf_len Length of the PRF function in bits (64, 128, or 256). ++ * @param key, nonce, label, bytes, len Same as for dwc_cmf(). ++ * @param result Byte array to receive the result. ++ */ ++void dwc_wusb_prf(int prf_len, u8 *key, ++ u8 *nonce, char *label, u8 *bytes, int len, u8 *result) ++{ ++ int i; ++ ++ nonce[0] = 0; ++ for (i = 0; i < prf_len >> 6; i++, nonce[0]++) { ++ dwc_wusb_cmf(key, nonce, label, bytes, len, result); ++ result += 8; ++ } ++} ++ ++/** ++ * Fills in CCM Nonce per the WUSB spec. ++ * ++ * @param[in] haddr Host address. ++ * @param[in] daddr Device address. ++ * @param[in] tkid Session Key(PTK) identifier. ++ * @param[out] nonce Pointer to where the CCM Nonce output is to be written. ++ */ ++void dwc_wusb_fill_ccm_nonce(uint16_t haddr, uint16_t daddr, uint8_t *tkid, ++ uint8_t *nonce) ++{ ++ ++ DWC_DEBUG("%s %x %x\n", __func__, daddr, haddr); ++ ++ DWC_MEMSET(&nonce[0], 0, 16); ++ ++ DWC_MEMCPY(&nonce[6], tkid, 3); ++ nonce[9] = daddr & 0xFF; ++ nonce[10] = (daddr >> 8) & 0xFF; ++ nonce[11] = haddr & 0xFF; ++ nonce[12] = (haddr >> 8) & 0xFF; ++ ++ dump_bytes("CCM nonce", nonce, 16); ++} ++ ++/** ++ * Generates a 16-byte cryptographic-grade random number for the Host/Device ++ * Nonce. ++ */ ++void dwc_wusb_gen_nonce(uint16_t addr, uint8_t *nonce) ++{ ++ uint8_t inonce[16]; ++ uint32_t temp[4]; ++ ++ /* Fill in the Nonce */ ++ DWC_MEMSET(&inonce[0], 0, sizeof(inonce)); ++ inonce[9] = addr & 0xFF; ++ inonce[10] = (addr >> 8) & 0xFF; ++ inonce[11] = inonce[9]; ++ inonce[12] = inonce[10]; ++ ++ /* Collect "randomness samples" */ ++ DWC_RANDOM_BYTES((uint8_t *)temp, 16); ++ ++ dwc_wusb_prf_128((uint8_t *)temp, nonce, ++ "Random Numbers", (uint8_t *)temp, sizeof(temp), ++ nonce); ++} ++ ++/** ++ * Generates the Session Key (PTK) and Key Confirmation Key (KCK) per the ++ * WUSB spec. ++ * ++ * @param[in] ccm_nonce Pointer to CCM Nonce. ++ * @param[in] mk Master Key to derive the session from ++ * @param[in] hnonce Pointer to Host Nonce. ++ * @param[in] dnonce Pointer to Device Nonce. ++ * @param[out] kck Pointer to where the KCK output is to be written. ++ * @param[out] ptk Pointer to where the PTK output is to be written. ++ */ ++void dwc_wusb_gen_key(uint8_t *ccm_nonce, uint8_t *mk, uint8_t *hnonce, ++ uint8_t *dnonce, uint8_t *kck, uint8_t *ptk) ++{ ++ uint8_t idata[32]; ++ uint8_t odata[32]; ++ ++ dump_bytes("ck", mk, 16); ++ dump_bytes("hnonce", hnonce, 16); ++ dump_bytes("dnonce", dnonce, 16); ++ ++ /* The data is the HNonce and DNonce concatenated */ ++ DWC_MEMCPY(&idata[0], hnonce, 16); ++ DWC_MEMCPY(&idata[16], dnonce, 16); ++ ++ dwc_wusb_prf_256(mk, ccm_nonce, "Pair-wise keys", idata, 32, odata); ++ ++ /* Low 16 bytes of the result is the KCK, high 16 is the PTK */ ++ DWC_MEMCPY(kck, &odata[0], 16); ++ DWC_MEMCPY(ptk, &odata[16], 16); ++ ++ dump_bytes("kck", kck, 16); ++ dump_bytes("ptk", ptk, 16); ++} ++ ++/** ++ * Generates the Message Integrity Code over the Handshake data per the ++ * WUSB spec. ++ * ++ * @param ccm_nonce Pointer to CCM Nonce. ++ * @param kck Pointer to Key Confirmation Key. ++ * @param data Pointer to Handshake data to be checked. ++ * @param mic Pointer to where the MIC output is to be written. ++ */ ++void dwc_wusb_gen_mic(uint8_t *ccm_nonce, uint8_t *kck, ++ uint8_t *data, uint8_t *mic) ++{ ++ ++ dwc_wusb_prf_64(kck, ccm_nonce, "out-of-bandMIC", ++ data, WUSB_HANDSHAKE_LEN_FOR_MIC, mic); ++} ++ ++#endif /* DWC_CRYPTOLIB */ +Index: linux-3.2.46/drivers/usb/host/dwc_common_port/dwc_crypto.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_common_port/dwc_crypto.h 2013-07-26 19:34:39.000000000 +0000 +@@ -0,0 +1,111 @@ ++/* ========================================================================= ++ * $File: //dwh/usb_iip/dev/software/dwc_common_port_2/dwc_crypto.h $ ++ * $Revision: #3 $ ++ * $Date: 2010/09/28 $ ++ * $Change: 1596182 $ ++ * ++ * Synopsys Portability Library Software and documentation ++ * (hereinafter, "Software") is an Unsupported proprietary work of ++ * Synopsys, Inc. unless otherwise expressly agreed to in writing ++ * between Synopsys and you. ++ * ++ * The Software IS NOT an item of Licensed Software or Licensed Product ++ * under any End User Software License Agreement or Agreement for ++ * Licensed Product with Synopsys or any supplement thereto. You are ++ * permitted to use and redistribute this Software in source and binary ++ * forms, with or without modification, provided that redistributions ++ * of source code must retain this notice. You may not view, use, ++ * disclose, copy or distribute this file or any information contained ++ * herein except pursuant to this license grant from Synopsys. If you ++ * do not agree with this notice, including the disclaimer below, then ++ * you are not authorized to use the Software. ++ * ++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" ++ * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT ++ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ++ * FOR A PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL ++ * SYNOPSYS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, ++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, ++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR ++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY ++ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE ++ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH ++ * DAMAGE. ++ * ========================================================================= */ ++ ++#ifndef _DWC_CRYPTO_H_ ++#define _DWC_CRYPTO_H_ ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/** @file ++ * ++ * This file contains declarations for the WUSB Cryptographic routines as ++ * defined in the WUSB spec. They are only to be used internally by the DWC UWB ++ * modules. ++ */ ++ ++#include "dwc_os.h" ++ ++int dwc_wusb_aes_encrypt(u8 *src, u8 *key, u8 *dst); ++ ++void dwc_wusb_cmf(u8 *key, u8 *nonce, ++ char *label, u8 *bytes, int len, u8 *result); ++void dwc_wusb_prf(int prf_len, u8 *key, ++ u8 *nonce, char *label, u8 *bytes, int len, u8 *result); ++ ++/** ++ * The PRF-64 function described in section 6.5 of the WUSB spec. ++ * ++ * @param key, nonce, label, bytes, len, result Same as for dwc_prf(). ++ */ ++static inline void dwc_wusb_prf_64(u8 *key, u8 *nonce, ++ char *label, u8 *bytes, int len, u8 *result) ++{ ++ dwc_wusb_prf(64, key, nonce, label, bytes, len, result); ++} ++ ++/** ++ * The PRF-128 function described in section 6.5 of the WUSB spec. ++ * ++ * @param key, nonce, label, bytes, len, result Same as for dwc_prf(). ++ */ ++static inline void dwc_wusb_prf_128(u8 *key, u8 *nonce, ++ char *label, u8 *bytes, int len, u8 *result) ++{ ++ dwc_wusb_prf(128, key, nonce, label, bytes, len, result); ++} ++ ++/** ++ * The PRF-256 function described in section 6.5 of the WUSB spec. ++ * ++ * @param key, nonce, label, bytes, len, result Same as for dwc_prf(). ++ */ ++static inline void dwc_wusb_prf_256(u8 *key, u8 *nonce, ++ char *label, u8 *bytes, int len, u8 *result) ++{ ++ dwc_wusb_prf(256, key, nonce, label, bytes, len, result); ++} ++ ++ ++void dwc_wusb_fill_ccm_nonce(uint16_t haddr, uint16_t daddr, uint8_t *tkid, ++ uint8_t *nonce); ++void dwc_wusb_gen_nonce(uint16_t addr, ++ uint8_t *nonce); ++ ++void dwc_wusb_gen_key(uint8_t *ccm_nonce, uint8_t *mk, ++ uint8_t *hnonce, uint8_t *dnonce, ++ uint8_t *kck, uint8_t *ptk); ++ ++ ++void dwc_wusb_gen_mic(uint8_t *ccm_nonce, uint8_t ++ *kck, uint8_t *data, uint8_t *mic); ++ ++#ifdef __cplusplus ++} ++#endif ++ ++#endif /* _DWC_CRYPTO_H_ */ +Index: linux-3.2.46/drivers/usb/host/dwc_common_port/dwc_dh.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_common_port/dwc_dh.c 2013-07-26 19:34:39.000000000 +0000 +@@ -0,0 +1,291 @@ ++/* ========================================================================= ++ * $File: //dwh/usb_iip/dev/software/dwc_common_port_2/dwc_dh.c $ ++ * $Revision: #3 $ ++ * $Date: 2010/09/28 $ ++ * $Change: 1596182 $ ++ * ++ * Synopsys Portability Library Software and documentation ++ * (hereinafter, "Software") is an Unsupported proprietary work of ++ * Synopsys, Inc. unless otherwise expressly agreed to in writing ++ * between Synopsys and you. ++ * ++ * The Software IS NOT an item of Licensed Software or Licensed Product ++ * under any End User Software License Agreement or Agreement for ++ * Licensed Product with Synopsys or any supplement thereto. You are ++ * permitted to use and redistribute this Software in source and binary ++ * forms, with or without modification, provided that redistributions ++ * of source code must retain this notice. You may not view, use, ++ * disclose, copy or distribute this file or any information contained ++ * herein except pursuant to this license grant from Synopsys. If you ++ * do not agree with this notice, including the disclaimer below, then ++ * you are not authorized to use the Software. ++ * ++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" ++ * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT ++ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ++ * FOR A PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL ++ * SYNOPSYS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, ++ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, ++ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR ++ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY ++ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE ++ * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH ++ * DAMAGE. ++ * ========================================================================= */ ++#ifdef DWC_CRYPTOLIB ++ ++#ifndef CONFIG_MACH_IPMATE ++ ++#include "dwc_dh.h" ++#include "dwc_modpow.h" ++ ++#ifdef DEBUG ++/* This function prints out a buffer in the format described in the Association ++ * Model specification. */ ++static void dh_dump(char *str, void *_num, int len) ++{ ++ uint8_t *num = _num; ++ int i; ++ DWC_PRINTF("%s\n", str); ++ for (i = 0; i < len; i ++) { ++ DWC_PRINTF("%02x", num[i]); ++ if (((i + 1) % 2) == 0) DWC_PRINTF(" "); ++ if (((i + 1) % 26) == 0) DWC_PRINTF("\n"); ++ } ++ ++ DWC_PRINTF("\n"); ++} ++#else ++#define dh_dump(_x...) do {; } while(0) ++#endif ++ ++/* Constant g value */ ++static __u32 dh_g[] = { ++ 0x02000000, ++}; ++ ++/* Constant p value */ ++static __u32 dh_p[] = { ++ 0xFFFFFFFF, 0xFFFFFFFF, 0xA2DA0FC9, 0x34C26821, 0x8B62C6C4, 0xD11CDC80, 0x084E0229, 0x74CC678A, ++ 0xA6BE0B02, 0x229B133B, 0x79084A51, 0xDD04348E, 0xB31995EF, 0x1B433ACD, 0x6D0A2B30, 0x37145FF2, ++ 0x6D35E14F, 0x45C2516D, 0x76B585E4, 0xC67E5E62, 0xE9424CF4, 0x6BED37A6, 0xB65CFF0B, 0xEDB706F4, ++ 0xFB6B38EE, 0xA59F895A, 0x11249FAE, 0xE61F4B7C, 0x51662849, 0x3D5BE4EC, 0xB87C00C2, 0x05BF63A1, ++ 0x3648DA98, 0x9AD3551C, 0xA83F1669, 0x5FCF24FD, 0x235D6583, 0x96ADA3DC, 0x56F3621C, 0xBB528520, ++ 0x0729D59E, 0x6D969670, 0x4E350C67, 0x0498BC4A, 0x086C74F1, 0x7C2118CA, 0x465E9032, 0x3BCE362E, ++ 0x2C779EE3, 0x03860E18, 0xA283279B, 0x8FA207EC, 0xF05DC5B5, 0xC9524C6F, 0xF6CB2BDE, 0x18175895, ++ 0x7C499539, 0xE56A95EA, 0x1826D215, 0x1005FA98, 0x5A8E7215, 0x2DC4AA8A, 0x0D1733AD, 0x337A5004, ++ 0xAB2155A8, 0x64BA1CDF, 0x0485FBEC, 0x0AEFDB58, 0x5771EA8A, 0x7D0C065D, 0x850F97B3, 0xC7E4E1A6, ++ 0x8CAEF5AB, 0xD73309DB, 0xE0948C1E, 0x9D61254A, 0x26D2E3CE, 0x6BEED21A, 0x06FA2FF1, 0x64088AD9, ++ 0x730276D8, 0x646AC83E, 0x182B1F52, 0x0C207B17, 0x5717E1BB, 0x6C5D617A, 0xC0880977, 0xE246D9BA, ++ 0xA04FE208, 0x31ABE574, 0xFC5BDB43, 0x8E10FDE0, 0x20D1824B, 0xCAD23AA9, 0xFFFFFFFF, 0xFFFFFFFF, ++}; ++ ++static void dh_swap_bytes(void *_in, void *_out, uint32_t len) ++{ ++ uint8_t *in = _in; ++ uint8_t *out = _out; ++ int i; ++ for (i=0; inext = (link); \ + (link)->prev = (link); \ +-} while(0) ++} while (0) + + #define DWC_LIST_FIRST(link) ((link)->next) + #define DWC_LIST_LAST(link) ((link)->prev) +@@ -113,42 +116,95 @@ + #define DWC_LIST_PREV(link) ((link)->prev) + #define DWC_LIST_EMPTY(link) \ + (DWC_LIST_FIRST(link) == DWC_LIST_END(link)) +-#define DWC_LIST_ENTRY(link, type, field) (type *) \ +- ((uint8_t *)(link) - (size_t)(&((type *)0)->field)) ++#define DWC_LIST_ENTRY(link, type, field) \ ++ (type *)((uint8_t *)(link) - (size_t)(&((type *)0)->field)) + ++#if 0 + #define DWC_LIST_INSERT_HEAD(list, link) do { \ + (link)->next = (list)->next; \ + (link)->prev = (list); \ +- (list)->next->prev = link; \ +- (list)->next = link; \ +-} while(0) ++ (list)->next->prev = (link); \ ++ (list)->next = (link); \ ++} while (0) + + #define DWC_LIST_INSERT_TAIL(list, link) do { \ +- (link)->next = list; \ ++ (link)->next = (list); \ + (link)->prev = (list)->prev; \ +- (list)->prev->next = link; \ +- (list)->prev = link; \ +-} while(0) ++ (list)->prev->next = (link); \ ++ (list)->prev = (link); \ ++} while (0) ++#else ++#define DWC_LIST_INSERT_HEAD(list, link) do { \ ++ dwc_list_link_t *__next__ = (list)->next; \ ++ __next__->prev = (link); \ ++ (link)->next = __next__; \ ++ (link)->prev = (list); \ ++ (list)->next = (link); \ ++} while (0) ++ ++#define DWC_LIST_INSERT_TAIL(list, link) do { \ ++ dwc_list_link_t *__prev__ = (list)->prev; \ ++ (list)->prev = (link); \ ++ (link)->next = (list); \ ++ (link)->prev = __prev__; \ ++ __prev__->next = (link); \ ++} while (0) ++#endif ++ ++#if 0 ++static inline void __list_add(struct list_head *new, ++ struct list_head *prev, ++ struct list_head *next) ++{ ++ next->prev = new; ++ new->next = next; ++ new->prev = prev; ++ prev->next = new; ++} ++ ++static inline void list_add(struct list_head *new, struct list_head *head) ++{ ++ __list_add(new, head, head->next); ++} ++ ++static inline void list_add_tail(struct list_head *new, struct list_head *head) ++{ ++ __list_add(new, head->prev, head); ++} ++ ++static inline void __list_del(struct list_head * prev, struct list_head * next) ++{ ++ next->prev = prev; ++ prev->next = next; ++} ++ ++static inline void list_del(struct list_head *entry) ++{ ++ __list_del(entry->prev, entry->next); ++ entry->next = LIST_POISON1; ++ entry->prev = LIST_POISON2; ++} ++#endif + + #define DWC_LIST_REMOVE(link) do { \ + (link)->next->prev = (link)->prev; \ + (link)->prev->next = (link)->next; \ +-} while(0) ++} while (0) + + #define DWC_LIST_REMOVE_INIT(link) do { \ + DWC_LIST_REMOVE(link); \ + DWC_LIST_INIT(link); \ +-} while(0) ++} while (0) + + #define DWC_LIST_MOVE_HEAD(list, link) do { \ + DWC_LIST_REMOVE(link); \ + DWC_LIST_INSERT_HEAD(list, link); \ +-} while(0) ++} while (0) + + #define DWC_LIST_MOVE_TAIL(list, link) do { \ + DWC_LIST_REMOVE(link); \ + DWC_LIST_INSERT_TAIL(list, link); \ +-} while(0) ++} while (0) + + #define DWC_LIST_FOREACH(var, list) \ + for((var) = DWC_LIST_FIRST(list); \ +@@ -156,9 +212,9 @@ + (var) = DWC_LIST_NEXT(var)) + + #define DWC_LIST_FOREACH_SAFE(var, var2, list) \ +- for((var) = DWC_LIST_FIRST(list), var2 = DWC_LIST_NEXT(var); \ ++ for((var) = DWC_LIST_FIRST(list), (var2) = DWC_LIST_NEXT(var); \ + (var) != DWC_LIST_END(list); \ +- (var) = (var2), var2 = DWC_LIST_NEXT(var2)) ++ (var) = (var2), (var2) = DWC_LIST_NEXT(var2)) + + #define DWC_LIST_FOREACH_REVERSE(var, list) \ + for((var) = DWC_LIST_LAST(list); \ +@@ -172,15 +228,15 @@ + struct name { \ + struct type *slh_first; /* first element */ \ + } +- +-#define DWC_SLIST_HEAD_INITIALIZER(head) \ ++ ++#define DWC_SLIST_HEAD_INITIALIZER(head) \ + { NULL } +- ++ + #define DWC_SLIST_ENTRY(type) \ + struct { \ + struct type *sle_next; /* next element */ \ + } +- ++ + /* + * Singly-linked List access methods. + */ +@@ -189,13 +245,13 @@ + #define DWC_SLIST_EMPTY(head) (SLIST_FIRST(head) == SLIST_END(head)) + #define DWC_SLIST_NEXT(elm, field) ((elm)->field.sle_next) + +-#define DWC_SLIST_FOREACH(var, head, field) \ ++#define DWC_SLIST_FOREACH(var, head, field) \ + for((var) = SLIST_FIRST(head); \ + (var) != SLIST_END(head); \ + (var) = SLIST_NEXT(var, field)) + +-#define DWC_SLIST_FOREACH_PREVPTR(var, varp, head, field) \ +- for ((varp) = &SLIST_FIRST((head)); \ ++#define DWC_SLIST_FOREACH_PREVPTR(var, varp, head, field) \ ++ for((varp) = &SLIST_FIRST((head)); \ + ((var) = *(varp)) != SLIST_END(head); \ + (varp) = &SLIST_NEXT((var), field)) + +@@ -206,7 +262,7 @@ + SLIST_FIRST(head) = SLIST_END(head); \ + } + +-#define DWC_SLIST_INSERT_AFTER(slistelm, elm, field) do { \ ++#define DWC_SLIST_INSERT_AFTER(slistelm, elm, field) do { \ + (elm)->field.sle_next = (slistelm)->field.sle_next; \ + (slistelm)->field.sle_next = (elm); \ + } while (0) +@@ -237,88 +293,6 @@ + } \ + } while (0) + +-#if 0 +- +-/* +- * List definitions. +- */ +-#define DWC_LIST_HEAD(name, type) \ +-struct name { \ +- struct type *lh_first; /* first element */ \ +-} +- +-#define DWC_LIST_HEAD_INITIALIZER(head) \ +- { NULL } +- +-#define DWC_LIST_ENTRY(type) \ +-struct { \ +- struct type *le_next; /* next element */ \ +- struct type **le_prev; /* address of previous next element */ \ +-} +- +-/* +- * List access methods +- */ +-#define DWC_LIST_FIRST(head) ((head)->lh_first) +-#define DWC_LIST_END(head) NULL +-#define DWC_LIST_EMPTY(head) (DWC_LIST_FIRST(head) == DWC_LIST_END(head)) +-#define DWC_LIST_NEXT(elm, field) ((elm)->field.le_next) +- +-#define DWC_LIST_FOREACH(var, head, field) \ +- for((var) = DWC_LIST_FIRST(head); \ +- (var)!= DWC_LIST_END(head); \ +- (var) = DWC_LIST_NEXT(var, field)) +-#define DWC_LIST_FOREACH_SAFE(var, var2, head, field) \ +- for((var) = DWC_LIST_FIRST(head), var2 = DWC_LIST_NEXT(var, field); \ +- (var) != DWC_LIST_END(head); \ +- (var) = var2, var2 = DWC_LIST_NEXT(var, field)) +- +-/* +- * List functions. +- */ +-#define DWC_LIST_INIT(head) do { \ +- DWC_LIST_FIRST(head) = DWC_LIST_END(head); \ +-} while (0) +- +-#define DWC_LIST_INSERT_AFTER(listelm, elm, field) do { \ +- if (((elm)->field.le_next = (listelm)->field.le_next) != NULL) \ +- (listelm)->field.le_next->field.le_prev = \ +- &(elm)->field.le_next; \ +- (listelm)->field.le_next = (elm); \ +- (elm)->field.le_prev = &(listelm)->field.le_next; \ +-} while (0) +- +-#define DWC_LIST_INSERT_BEFORE(listelm, elm, field) do { \ +- (elm)->field.le_prev = (listelm)->field.le_prev; \ +- (elm)->field.le_next = (listelm); \ +- *(listelm)->field.le_prev = (elm); \ +- (listelm)->field.le_prev = &(elm)->field.le_next; \ +-} while (0) +- +-#define DWC_LIST_INSERT_HEAD(head, elm, field) do { \ +- if (((elm)->field.le_next = (head)->lh_first) != NULL) \ +- (head)->lh_first->field.le_prev = &(elm)->field.le_next;\ +- (head)->lh_first = (elm); \ +- (elm)->field.le_prev = &(head)->lh_first; \ +-} while (0) +- +-#define DWC_LIST_REMOVE(elm, field) do { \ +- if ((elm)->field.le_next != NULL) \ +- (elm)->field.le_next->field.le_prev = \ +- (elm)->field.le_prev; \ +- *(elm)->field.le_prev = (elm)->field.le_next; \ +-} while (0) +- +-#define DWC_LIST_REPLACE(elm, elm2, field) do { \ +- if (((elm2)->field.le_next = (elm)->field.le_next) != NULL) \ +- (elm2)->field.le_next->field.le_prev = \ +- &(elm2)->field.le_next; \ +- (elm2)->field.le_prev = (elm)->field.le_prev; \ +- *(elm2)->field.le_prev = (elm2); \ +-} while (0) +- +-#endif +- + /* + * Simple queue definitions. + */ +@@ -328,7 +302,7 @@ + struct type **sqh_last; /* addr of last next element */ \ + } + +-#define DWC_SIMPLEQ_HEAD_INITIALIZER(head) \ ++#define DWC_SIMPLEQ_HEAD_INITIALIZER(head) \ + { NULL, &(head).sqh_first } + + #define DWC_SIMPLEQ_ENTRY(type) \ +@@ -352,7 +326,7 @@ + /* + * Simple queue functions. + */ +-#define DWC_SIMPLEQ_INIT(head) do { \ ++#define DWC_SIMPLEQ_INIT(head) do { \ + (head)->sqh_first = NULL; \ + (head)->sqh_last = &(head)->sqh_first; \ + } while (0) +@@ -369,7 +343,7 @@ + (head)->sqh_last = &(elm)->field.sqe_next; \ + } while (0) + +-#define DWC_SIMPLEQ_INSERT_AFTER(head, listelm, elm, field) do { \ ++#define DWC_SIMPLEQ_INSERT_AFTER(head, listelm, elm, field) do { \ + if (((elm)->field.sqe_next = (listelm)->field.sqe_next) == NULL)\ + (head)->sqh_last = &(elm)->field.sqe_next; \ + (listelm)->field.sqe_next = (elm); \ +@@ -383,13 +357,13 @@ + /* + * Tail queue definitions. + */ +-#define DWC_TAILQ_HEAD(name, type) \ ++#define DWC_TAILQ_HEAD(name, type) \ + struct name { \ + struct type *tqh_first; /* first element */ \ + struct type **tqh_last; /* addr of last next element */ \ + } + +-#define DWC_TAILQ_HEAD_INITIALIZER(head) \ ++#define DWC_TAILQ_HEAD_INITIALIZER(head) \ + { NULL, &(head).tqh_first } + + #define DWC_TAILQ_ENTRY(type) \ +@@ -398,12 +372,12 @@ + struct type **tqe_prev; /* address of previous next element */ \ + } + +-/* +- * tail queue access methods ++/* ++ * tail queue access methods + */ + #define DWC_TAILQ_FIRST(head) ((head)->tqh_first) +-#define DWC_TAILQ_END(head) NULL +-#define DWC_TAILQ_NEXT(elm, field) ((elm)->field.tqe_next) ++#define DWC_TAILQ_END(head) NULL ++#define DWC_TAILQ_NEXT(elm, field) ((elm)->field.tqe_next) + #define DWC_TAILQ_LAST(head, headname) \ + (*(((struct headname *)((head)->tqh_last))->tqh_last)) + /* XXX */ +@@ -412,7 +386,7 @@ + #define DWC_TAILQ_EMPTY(head) \ + (TAILQ_FIRST(head) == TAILQ_END(head)) + +-#define DWC_TAILQ_FOREACH(var, head, field) \ ++#define DWC_TAILQ_FOREACH(var, head, field) \ + for((var) = TAILQ_FIRST(head); \ + (var) != TAILQ_END(head); \ + (var) = TAILQ_NEXT(var, field)) +@@ -425,7 +399,7 @@ + /* + * Tail queue functions. + */ +-#define DWC_TAILQ_INIT(head) do { \ ++#define DWC_TAILQ_INIT(head) do { \ + (head)->tqh_first = NULL; \ + (head)->tqh_last = &(head)->tqh_first; \ + } while (0) +@@ -457,7 +431,7 @@ + (elm)->field.tqe_prev = &(listelm)->field.tqe_next; \ + } while (0) + +-#define DWC_TAILQ_INSERT_BEFORE(listelm, elm, field) do { \ ++#define DWC_TAILQ_INSERT_BEFORE(listelm, elm, field) do { \ + (elm)->field.tqe_prev = (listelm)->field.tqe_prev; \ + (elm)->field.tqe_next = (listelm); \ + *(listelm)->field.tqe_prev = (elm); \ +@@ -492,7 +466,7 @@ + struct type *cqh_last; /* last element */ \ + } + +-#define DWC_CIRCLEQ_HEAD_INITIALIZER(head) \ ++#define DWC_CIRCLEQ_HEAD_INITIALIZER(head) \ + { DWC_CIRCLEQ_END(&head), DWC_CIRCLEQ_END(&head) } + + #define DWC_CIRCLEQ_ENTRY(type) \ +@@ -502,7 +476,7 @@ + } + + /* +- * Circular queue access methods ++ * Circular queue access methods + */ + #define DWC_CIRCLEQ_FIRST(head) ((head)->cqh_first) + #define DWC_CIRCLEQ_LAST(head) ((head)->cqh_last) +@@ -516,33 +490,33 @@ + + #define DWC_CIRCLEQ_FOREACH(var, head, field) \ + for((var) = DWC_CIRCLEQ_FIRST(head); \ +- (var) != DWC_CIRCLEQ_END(head); \ ++ (var) != DWC_CIRCLEQ_END(head); \ + (var) = DWC_CIRCLEQ_NEXT(var, field)) + +-#define DWC_CIRCLEQ_FOREACH_SAFE(var, var2, head, field) \ +- for((var) = DWC_CIRCLEQ_FIRST(head), var2 = DWC_CIRCLEQ_NEXT(var, field); \ ++#define DWC_CIRCLEQ_FOREACH_SAFE(var, var2, head, field) \ ++ for((var) = DWC_CIRCLEQ_FIRST(head), var2 = DWC_CIRCLEQ_NEXT(var, field); \ + (var) != DWC_CIRCLEQ_END(head); \ + (var) = var2, var2 = DWC_CIRCLEQ_NEXT(var, field)) + + #define DWC_CIRCLEQ_FOREACH_REVERSE(var, head, field) \ +- for((var) = DWC_CIRCLEQ_LAST(head); \ +- (var) != DWC_CIRCLEQ_END(head); \ ++ for((var) = DWC_CIRCLEQ_LAST(head); \ ++ (var) != DWC_CIRCLEQ_END(head); \ + (var) = DWC_CIRCLEQ_PREV(var, field)) + + /* + * Circular queue functions. + */ +-#define DWC_CIRCLEQ_INIT(head) do { \ +- (head)->cqh_first = DWC_CIRCLEQ_END(head); \ +- (head)->cqh_last = DWC_CIRCLEQ_END(head); \ ++#define DWC_CIRCLEQ_INIT(head) do { \ ++ (head)->cqh_first = DWC_CIRCLEQ_END(head); \ ++ (head)->cqh_last = DWC_CIRCLEQ_END(head); \ + } while (0) + +-#define DWC_CIRCLEQ_INIT_ENTRY(elm, field) do { \ +- (elm)->field.cqe_next = NULL; \ +- (elm)->field.cqe_prev = NULL; \ ++#define DWC_CIRCLEQ_INIT_ENTRY(elm, field) do { \ ++ (elm)->field.cqe_next = NULL; \ ++ (elm)->field.cqe_prev = NULL; \ + } while (0) + +-#define DWC_CIRCLEQ_INSERT_AFTER(head, listelm, elm, field) do { \ ++#define DWC_CIRCLEQ_INSERT_AFTER(head, listelm, elm, field) do { \ + (elm)->field.cqe_next = (listelm)->field.cqe_next; \ + (elm)->field.cqe_prev = (listelm); \ + if ((listelm)->field.cqe_next == DWC_CIRCLEQ_END(head)) \ +@@ -552,7 +526,7 @@ + (listelm)->field.cqe_next = (elm); \ + } while (0) + +-#define DWC_CIRCLEQ_INSERT_BEFORE(head, listelm, elm, field) do { \ ++#define DWC_CIRCLEQ_INSERT_BEFORE(head, listelm, elm, field) do { \ + (elm)->field.cqe_next = (listelm); \ + (elm)->field.cqe_prev = (listelm)->field.cqe_prev; \ + if ((listelm)->field.cqe_prev == DWC_CIRCLEQ_END(head)) \ +@@ -582,35 +556,39 @@ + (head)->cqh_last = (elm); \ + } while (0) + +-#define DWC_CIRCLEQ_REMOVE(head, elm, field) do { \ +- if ((elm)->field.cqe_next == DWC_CIRCLEQ_END(head)) \ ++#define DWC_CIRCLEQ_REMOVE(head, elm, field) do { \ ++ if ((elm)->field.cqe_next == DWC_CIRCLEQ_END(head)) \ + (head)->cqh_last = (elm)->field.cqe_prev; \ + else \ + (elm)->field.cqe_next->field.cqe_prev = \ + (elm)->field.cqe_prev; \ +- if ((elm)->field.cqe_prev == DWC_CIRCLEQ_END(head)) \ ++ if ((elm)->field.cqe_prev == DWC_CIRCLEQ_END(head)) \ + (head)->cqh_first = (elm)->field.cqe_next; \ + else \ + (elm)->field.cqe_prev->field.cqe_next = \ + (elm)->field.cqe_next; \ + } while (0) + +-#define DWC_CIRCLEQ_REMOVE_INIT(head, elm, field) do { \ +- DWC_CIRCLEQ_REMOVE(head, elm, field); \ +- DWC_CIRCLEQ_INIT_ENTRY(elm, field); \ ++#define DWC_CIRCLEQ_REMOVE_INIT(head, elm, field) do { \ ++ DWC_CIRCLEQ_REMOVE(head, elm, field); \ ++ DWC_CIRCLEQ_INIT_ENTRY(elm, field); \ + } while (0) + +-#define DWC_CIRCLEQ_REPLACE(head, elm, elm2, field) do { \ ++#define DWC_CIRCLEQ_REPLACE(head, elm, elm2, field) do { \ + if (((elm2)->field.cqe_next = (elm)->field.cqe_next) == \ +- DWC_CIRCLEQ_END(head)) \ ++ DWC_CIRCLEQ_END(head)) \ + (head).cqh_last = (elm2); \ + else \ + (elm2)->field.cqe_next->field.cqe_prev = (elm2); \ + if (((elm2)->field.cqe_prev = (elm)->field.cqe_prev) == \ +- DWC_CIRCLEQ_END(head)) \ ++ DWC_CIRCLEQ_END(head)) \ + (head).cqh_first = (elm2); \ + else \ + (elm2)->field.cqe_prev->field.cqe_next = (elm2); \ + } while (0) + +-#endif /* !_SYS_QUEUE_H_ */ ++#ifdef __cplusplus ++} ++#endif ++ ++#endif /* _DWC_LIST_H_ */ +Index: linux-3.2.46/drivers/usb/host/dwc_common_port/dwc_mem.c +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_common_port/dwc_mem.c 2013-07-26 19:31:19.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_common_port/dwc_mem.c 2013-07-26 19:34:39.000000000 +0000 +@@ -1,12 +1,12 @@ ++/* Memory Debugging */ ++#ifdef DWC_DEBUG_MEMORY ++ + #include "dwc_os.h" + #include "dwc_list.h" + +-/* Memory Debugging */ +-#ifdef DEBUG_MEMORY +- +-struct allocation +-{ ++struct allocation { + void *addr; ++ void *ctx; + char *func; + int line; + uint32_t size; +@@ -16,8 +16,8 @@ + + DWC_CIRCLEQ_HEAD(allocation_queue, allocation); + +-struct allocation_manager +-{ ++struct allocation_manager { ++ void *mem_ctx; + struct allocation_queue allocations; + + /* statistics */ +@@ -25,148 +25,221 @@ + int num_freed; + int num_active; + uint32_t total; +- uint32_t current; ++ uint32_t cur; + uint32_t max; + }; + +- + static struct allocation_manager *manager = NULL; + +-static void add_allocation(uint32_t size, char const* func, int line, void *addr, int dma) ++static int add_allocation(void *ctx, uint32_t size, char const *func, int line, void *addr, ++ int dma) + { +- struct allocation *a = __DWC_ALLOC_ATOMIC(sizeof(*a)); +- a->func = __DWC_ALLOC_ATOMIC(DWC_STRLEN(func)+1); +- DWC_MEMCPY(a->func, func, DWC_STRLEN(func)+1); ++ struct allocation *a; ++ ++ DWC_ASSERT(manager != NULL, "manager not allocated"); ++ ++ a = __DWC_ALLOC_ATOMIC(manager->mem_ctx, sizeof(*a)); ++ if (!a) { ++ return -DWC_E_NO_MEMORY; ++ } ++ ++ a->func = __DWC_ALLOC_ATOMIC(manager->mem_ctx, DWC_STRLEN(func) + 1); ++ if (!a->func) { ++ __DWC_FREE(manager->mem_ctx, a); ++ return -DWC_E_NO_MEMORY; ++ } ++ ++ DWC_MEMCPY(a->func, func, DWC_STRLEN(func) + 1); ++ a->addr = addr; ++ a->ctx = ctx; + a->line = line; + a->size = size; +- a->addr = addr; + a->dma = dma; + DWC_CIRCLEQ_INSERT_TAIL(&manager->allocations, a, entry); + + /* Update stats */ +- manager->num ++; +- manager->num_active ++; ++ manager->num++; ++ manager->num_active++; + manager->total += size; +- manager->current += size; +- if (manager->max < manager->current) { +- manager->max = manager->current; ++ manager->cur += size; ++ ++ if (manager->max < manager->cur) { ++ manager->max = manager->cur; + } ++ ++ return 0; + } + +-static struct allocation *find_allocation(void *addr) ++static struct allocation *find_allocation(void *ctx, void *addr) + { + struct allocation *a; ++ + DWC_CIRCLEQ_FOREACH(a, &manager->allocations, entry) { +- if (a->addr == addr) { ++ if (a->ctx == ctx && a->addr == addr) { + return a; + } + } ++ + return NULL; + } + +-static void free_allocation(void *addr, char const* func, int line) ++static void free_allocation(void *ctx, void *addr, char const *func, int line) + { +- struct allocation *a = find_allocation(addr); +- if (!a && func && (line >= 0)) { +- DWC_ASSERT(0, "Free of address %p that was never allocated or already freed %s:%d", addr, func, line); ++ struct allocation *a = find_allocation(ctx, addr); ++ ++ if (!a) { ++ DWC_ASSERT(0, ++ "Free of address %p that was never allocated or already freed %s:%d", ++ addr, func, line); + return; + } ++ + DWC_CIRCLEQ_REMOVE(&manager->allocations, a, entry); + +- manager->num_active --; +- manager->num_freed ++; +- manager->current -= a->size; +- __DWC_FREE(a->func); +- __DWC_FREE(a); ++ manager->num_active--; ++ manager->num_freed++; ++ manager->cur -= a->size; ++ __DWC_FREE(manager->mem_ctx, a->func); ++ __DWC_FREE(manager->mem_ctx, a); + } + +-void dwc_memory_debug_start(void) ++int dwc_memory_debug_start(void *mem_ctx) + { + DWC_ASSERT(manager == NULL, "Memory debugging has already started\n"); +- if (manager == NULL) { +- manager = __DWC_ALLOC(sizeof(*manager)); ++ ++ if (manager) { ++ return -DWC_E_BUSY; ++ } ++ ++ manager = __DWC_ALLOC(mem_ctx, sizeof(*manager)); ++ if (!manager) { ++ return -DWC_E_NO_MEMORY; + } + + DWC_CIRCLEQ_INIT(&manager->allocations); ++ manager->mem_ctx = mem_ctx; + manager->num = 0; + manager->num_freed = 0; + manager->num_active = 0; + manager->total = 0; +- manager->current = 0; ++ manager->cur = 0; + manager->max = 0; ++ ++ return 0; + } + + void dwc_memory_debug_stop(void) + { + struct allocation *a; ++ + dwc_memory_debug_report(); + + DWC_CIRCLEQ_FOREACH(a, &manager->allocations, entry) { + DWC_ERROR("Memory leaked from %s:%d\n", a->func, a->line); +- free_allocation(a->addr, NULL, -1); ++ free_allocation(a->ctx, a->addr, NULL, -1); + } + +- __DWC_FREE(manager); ++ __DWC_FREE(manager->mem_ctx, manager); + } + + void dwc_memory_debug_report(void) + { + struct allocation *a; ++ + DWC_PRINTF("\n\n\n----------------- Memory Debugging Report -----------------\n\n"); + DWC_PRINTF("Num Allocations = %d\n", manager->num); + DWC_PRINTF("Freed = %d\n", manager->num_freed); + DWC_PRINTF("Active = %d\n", manager->num_active); +- DWC_PRINTF("Current Memory Used = %d\n", manager->current); ++ DWC_PRINTF("Current Memory Used = %d\n", manager->cur); + DWC_PRINTF("Total Memory Used = %d\n", manager->total); + DWC_PRINTF("Maximum Memory Used at Once = %d\n", manager->max); + DWC_PRINTF("Unfreed allocations:\n"); + + DWC_CIRCLEQ_FOREACH(a, &manager->allocations, entry) { +- DWC_PRINTF(" addr=%p, size=%d from %s:%d, DMA=%d\n", a->addr, a->size, a->func, a->line, a->dma); ++ DWC_PRINTF(" addr=%p, size=%d from %s:%d, DMA=%d\n", ++ a->addr, a->size, a->func, a->line, a->dma); + } + } + +- +- + /* The replacement functions */ +-void *dwc_alloc_debug(uint32_t size, char const* func, int line) ++void *dwc_alloc_debug(void *mem_ctx, uint32_t size, char const *func, int line) + { +- void *addr = __DWC_ALLOC(size); +- add_allocation(size, func, line, addr, 0); ++ void *addr = __DWC_ALLOC(mem_ctx, size); ++ ++ if (!addr) { ++ return NULL; ++ } ++ ++ if (add_allocation(mem_ctx, size, func, line, addr, 0)) { ++ __DWC_FREE(mem_ctx, addr); ++ return NULL; ++ } ++ + return addr; + } + +-void *dwc_alloc_atomic_debug(uint32_t size, char const* func, int line) ++void *dwc_alloc_atomic_debug(void *mem_ctx, uint32_t size, char const *func, ++ int line) + { +- void *addr = __DWC_ALLOC_ATOMIC(size); +- add_allocation(size, func, line, addr, 0); ++ void *addr = __DWC_ALLOC_ATOMIC(mem_ctx, size); ++ ++ if (!addr) { ++ return NULL; ++ } ++ ++ if (add_allocation(mem_ctx, size, func, line, addr, 0)) { ++ __DWC_FREE(mem_ctx, addr); ++ return NULL; ++ } ++ + return addr; + } + +-void dwc_free_debug(void *addr, char const* func, int line) ++void dwc_free_debug(void *mem_ctx, void *addr, char const *func, int line) + { +- free_allocation(addr, func, line); +- __DWC_FREE(addr); ++ free_allocation(mem_ctx, addr, func, line); ++ __DWC_FREE(mem_ctx, addr); + } + +-void *dwc_dma_alloc_debug(uint32_t size, dwc_dma_t *dma_addr, char const *func, int line) ++void *dwc_dma_alloc_debug(void *dma_ctx, uint32_t size, dwc_dma_t *dma_addr, ++ char const *func, int line) + { +- void *addr = __DWC_DMA_ALLOC(size, dma_addr); +- add_allocation(size, func, line, addr, 1); ++ void *addr = __DWC_DMA_ALLOC(dma_ctx, size, dma_addr); ++ ++ if (!addr) { ++ return NULL; ++ } ++ ++ if (add_allocation(dma_ctx, size, func, line, addr, 1)) { ++ __DWC_DMA_FREE(dma_ctx, size, addr, *dma_addr); ++ return NULL; ++ } ++ + return addr; + } + +-void *dwc_dma_alloc_atomic_debug(uint32_t size, dwc_dma_t *dma_addr, char const *func, int line) ++void *dwc_dma_alloc_atomic_debug(void *dma_ctx, uint32_t size, ++ dwc_dma_t *dma_addr, char const *func, int line) + { +- void *addr = __DWC_DMA_ALLOC_ATOMIC(size, dma_addr); +- add_allocation(size, func, line, addr, 1); ++ void *addr = __DWC_DMA_ALLOC_ATOMIC(dma_ctx, size, dma_addr); ++ ++ if (!addr) { ++ return NULL; ++ } ++ ++ if (add_allocation(dma_ctx, size, func, line, addr, 1)) { ++ __DWC_DMA_FREE(dma_ctx, size, addr, *dma_addr); ++ return NULL; ++ } ++ + return addr; + } + +-void dwc_dma_free_debug(uint32_t size, void *virt_addr, dwc_dma_t dma_addr, char const *func, int line) ++void dwc_dma_free_debug(void *dma_ctx, uint32_t size, void *virt_addr, ++ dwc_dma_t dma_addr, char const *func, int line) + { +- free_allocation(virt_addr, func, line); +- __DWC_DMA_FREE(size, virt_addr, dma_addr); ++ free_allocation(dma_ctx, virt_addr, func, line); ++ __DWC_DMA_FREE(dma_ctx, size, virt_addr, dma_addr); + } + +-#endif /* DEBUG_MEMORY */ ++#endif /* DWC_DEBUG_MEMORY */ +Index: linux-3.2.46/drivers/usb/host/dwc_common_port/dwc_modpow.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_common_port/dwc_modpow.c 2013-07-26 19:34:39.000000000 +0000 +@@ -0,0 +1,636 @@ ++/* Bignum routines adapted from PUTTY sources. PuTTY copyright notice follows. ++ * ++ * PuTTY is copyright 1997-2007 Simon Tatham. ++ * ++ * Portions copyright Robert de Bath, Joris van Rantwijk, Delian ++ * Delchev, Andreas Schultz, Jeroen Massar, Wez Furlong, Nicolas Barry, ++ * Justin Bradford, Ben Harris, Malcolm Smith, Ahmad Khalifa, Markus ++ * Kuhn, and CORE SDI S.A. ++ * ++ * Permission is hereby granted, free of charge, to any person ++ * obtaining a copy of this software and associated documentation files ++ * (the "Software"), to deal in the Software without restriction, ++ * including without limitation the rights to use, copy, modify, merge, ++ * publish, distribute, sublicense, and/or sell copies of the Software, ++ * and to permit persons to whom the Software is furnished to do so, ++ * subject to the following conditions: ++ * ++ * The above copyright notice and this permission notice shall be ++ * included in all copies or substantial portions of the Software. ++ ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, ++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF ++ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND ++ * NONINFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE ++ * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF ++ * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION ++ * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. ++ * ++ */ ++#ifdef DWC_CRYPTOLIB ++ ++#ifndef CONFIG_MACH_IPMATE ++ ++#include "dwc_modpow.h" ++ ++#define BIGNUM_INT_MASK 0xFFFFFFFFUL ++#define BIGNUM_TOP_BIT 0x80000000UL ++#define BIGNUM_INT_BITS 32 ++ ++ ++static void *snmalloc(void *mem_ctx, size_t n, size_t size) ++{ ++ void *p; ++ size *= n; ++ if (size == 0) size = 1; ++ p = dwc_alloc(mem_ctx, size); ++ return p; ++} ++ ++#define snewn(ctx, n, type) ((type *)snmalloc((ctx), (n), sizeof(type))) ++#define sfree dwc_free ++ ++/* ++ * Usage notes: ++ * * Do not call the DIVMOD_WORD macro with expressions such as array ++ * subscripts, as some implementations object to this (see below). ++ * * Note that none of the division methods below will cope if the ++ * quotient won't fit into BIGNUM_INT_BITS. Callers should be careful ++ * to avoid this case. ++ * If this condition occurs, in the case of the x86 DIV instruction, ++ * an overflow exception will occur, which (according to a correspondent) ++ * will manifest on Windows as something like ++ * 0xC0000095: Integer overflow ++ * The C variant won't give the right answer, either. ++ */ ++ ++#define MUL_WORD(w1, w2) ((BignumDblInt)w1 * w2) ++ ++#if defined __GNUC__ && defined __i386__ ++#define DIVMOD_WORD(q, r, hi, lo, w) \ ++ __asm__("div %2" : \ ++ "=d" (r), "=a" (q) : \ ++ "r" (w), "d" (hi), "a" (lo)) ++#else ++#define DIVMOD_WORD(q, r, hi, lo, w) do { \ ++ BignumDblInt n = (((BignumDblInt)hi) << BIGNUM_INT_BITS) | lo; \ ++ q = n / w; \ ++ r = n % w; \ ++} while (0) ++#endif ++ ++// q = n / w; ++// r = n % w; ++ ++#define BIGNUM_INT_BYTES (BIGNUM_INT_BITS / 8) ++ ++#define BIGNUM_INTERNAL ++ ++static Bignum newbn(void *mem_ctx, int length) ++{ ++ Bignum b = snewn(mem_ctx, length + 1, BignumInt); ++ //if (!b) ++ //abort(); /* FIXME */ ++ DWC_MEMSET(b, 0, (length + 1) * sizeof(*b)); ++ b[0] = length; ++ return b; ++} ++ ++void freebn(void *mem_ctx, Bignum b) ++{ ++ /* ++ * Burn the evidence, just in case. ++ */ ++ DWC_MEMSET(b, 0, sizeof(b[0]) * (b[0] + 1)); ++ sfree(mem_ctx, b); ++} ++ ++/* ++ * Compute c = a * b. ++ * Input is in the first len words of a and b. ++ * Result is returned in the first 2*len words of c. ++ */ ++static void internal_mul(BignumInt *a, BignumInt *b, ++ BignumInt *c, int len) ++{ ++ int i, j; ++ BignumDblInt t; ++ ++ for (j = 0; j < 2 * len; j++) ++ c[j] = 0; ++ ++ for (i = len - 1; i >= 0; i--) { ++ t = 0; ++ for (j = len - 1; j >= 0; j--) { ++ t += MUL_WORD(a[i], (BignumDblInt) b[j]); ++ t += (BignumDblInt) c[i + j + 1]; ++ c[i + j + 1] = (BignumInt) t; ++ t = t >> BIGNUM_INT_BITS; ++ } ++ c[i] = (BignumInt) t; ++ } ++} ++ ++static void internal_add_shifted(BignumInt *number, ++ unsigned n, int shift) ++{ ++ int word = 1 + (shift / BIGNUM_INT_BITS); ++ int bshift = shift % BIGNUM_INT_BITS; ++ BignumDblInt addend; ++ ++ addend = (BignumDblInt)n << bshift; ++ ++ while (addend) { ++ addend += number[word]; ++ number[word] = (BignumInt) addend & BIGNUM_INT_MASK; ++ addend >>= BIGNUM_INT_BITS; ++ word++; ++ } ++} ++ ++/* ++ * Compute a = a % m. ++ * Input in first alen words of a and first mlen words of m. ++ * Output in first alen words of a ++ * (of which first alen-mlen words will be zero). ++ * The MSW of m MUST have its high bit set. ++ * Quotient is accumulated in the `quotient' array, which is a Bignum ++ * rather than the internal bigendian format. Quotient parts are shifted ++ * left by `qshift' before adding into quot. ++ */ ++static void internal_mod(BignumInt *a, int alen, ++ BignumInt *m, int mlen, ++ BignumInt *quot, int qshift) ++{ ++ BignumInt m0, m1; ++ unsigned int h; ++ int i, k; ++ ++ m0 = m[0]; ++ if (mlen > 1) ++ m1 = m[1]; ++ else ++ m1 = 0; ++ ++ for (i = 0; i <= alen - mlen; i++) { ++ BignumDblInt t; ++ unsigned int q, r, c, ai1; ++ ++ if (i == 0) { ++ h = 0; ++ } else { ++ h = a[i - 1]; ++ a[i - 1] = 0; ++ } ++ ++ if (i == alen - 1) ++ ai1 = 0; ++ else ++ ai1 = a[i + 1]; ++ ++ /* Find q = h:a[i] / m0 */ ++ if (h >= m0) { ++ /* ++ * Special case. ++ * ++ * To illustrate it, suppose a BignumInt is 8 bits, and ++ * we are dividing (say) A1:23:45:67 by A1:B2:C3. Then ++ * our initial division will be 0xA123 / 0xA1, which ++ * will give a quotient of 0x100 and a divide overflow. ++ * However, the invariants in this division algorithm ++ * are not violated, since the full number A1:23:... is ++ * _less_ than the quotient prefix A1:B2:... and so the ++ * following correction loop would have sorted it out. ++ * ++ * In this situation we set q to be the largest ++ * quotient we _can_ stomach (0xFF, of course). ++ */ ++ q = BIGNUM_INT_MASK; ++ } else { ++ /* Macro doesn't want an array subscript expression passed ++ * into it (see definition), so use a temporary. */ ++ BignumInt tmplo = a[i]; ++ DIVMOD_WORD(q, r, h, tmplo, m0); ++ ++ /* Refine our estimate of q by looking at ++ h:a[i]:a[i+1] / m0:m1 */ ++ t = MUL_WORD(m1, q); ++ if (t > ((BignumDblInt) r << BIGNUM_INT_BITS) + ai1) { ++ q--; ++ t -= m1; ++ r = (r + m0) & BIGNUM_INT_MASK; /* overflow? */ ++ if (r >= (BignumDblInt) m0 && ++ t > ((BignumDblInt) r << BIGNUM_INT_BITS) + ai1) q--; ++ } ++ } ++ ++ /* Subtract q * m from a[i...] */ ++ c = 0; ++ for (k = mlen - 1; k >= 0; k--) { ++ t = MUL_WORD(q, m[k]); ++ t += c; ++ c = (unsigned)(t >> BIGNUM_INT_BITS); ++ if ((BignumInt) t > a[i + k]) ++ c++; ++ a[i + k] -= (BignumInt) t; ++ } ++ ++ /* Add back m in case of borrow */ ++ if (c != h) { ++ t = 0; ++ for (k = mlen - 1; k >= 0; k--) { ++ t += m[k]; ++ t += a[i + k]; ++ a[i + k] = (BignumInt) t; ++ t = t >> BIGNUM_INT_BITS; ++ } ++ q--; ++ } ++ if (quot) ++ internal_add_shifted(quot, q, qshift + BIGNUM_INT_BITS * (alen - mlen - i)); ++ } ++} ++ ++/* ++ * Compute p % mod. ++ * The most significant word of mod MUST be non-zero. ++ * We assume that the result array is the same size as the mod array. ++ * We optionally write out a quotient if `quotient' is non-NULL. ++ * We can avoid writing out the result if `result' is NULL. ++ */ ++void bigdivmod(void *mem_ctx, Bignum p, Bignum mod, Bignum result, Bignum quotient) ++{ ++ BignumInt *n, *m; ++ int mshift; ++ int plen, mlen, i, j; ++ ++ /* Allocate m of size mlen, copy mod to m */ ++ /* We use big endian internally */ ++ mlen = mod[0]; ++ m = snewn(mem_ctx, mlen, BignumInt); ++ //if (!m) ++ //abort(); /* FIXME */ ++ for (j = 0; j < mlen; j++) ++ m[j] = mod[mod[0] - j]; ++ ++ /* Shift m left to make msb bit set */ ++ for (mshift = 0; mshift < BIGNUM_INT_BITS-1; mshift++) ++ if ((m[0] << mshift) & BIGNUM_TOP_BIT) ++ break; ++ if (mshift) { ++ for (i = 0; i < mlen - 1; i++) ++ m[i] = (m[i] << mshift) | (m[i + 1] >> (BIGNUM_INT_BITS - mshift)); ++ m[mlen - 1] = m[mlen - 1] << mshift; ++ } ++ ++ plen = p[0]; ++ /* Ensure plen > mlen */ ++ if (plen <= mlen) ++ plen = mlen + 1; ++ ++ /* Allocate n of size plen, copy p to n */ ++ n = snewn(mem_ctx, plen, BignumInt); ++ //if (!n) ++ //abort(); /* FIXME */ ++ for (j = 0; j < plen; j++) ++ n[j] = 0; ++ for (j = 1; j <= (int)p[0]; j++) ++ n[plen - j] = p[j]; ++ ++ /* Main computation */ ++ internal_mod(n, plen, m, mlen, quotient, mshift); ++ ++ /* Fixup result in case the modulus was shifted */ ++ if (mshift) { ++ for (i = plen - mlen - 1; i < plen - 1; i++) ++ n[i] = (n[i] << mshift) | (n[i + 1] >> (BIGNUM_INT_BITS - mshift)); ++ n[plen - 1] = n[plen - 1] << mshift; ++ internal_mod(n, plen, m, mlen, quotient, 0); ++ for (i = plen - 1; i >= plen - mlen; i--) ++ n[i] = (n[i] >> mshift) | (n[i - 1] << (BIGNUM_INT_BITS - mshift)); ++ } ++ ++ /* Copy result to buffer */ ++ if (result) { ++ for (i = 1; i <= (int)result[0]; i++) { ++ int j = plen - i; ++ result[i] = j >= 0 ? n[j] : 0; ++ } ++ } ++ ++ /* Free temporary arrays */ ++ for (i = 0; i < mlen; i++) ++ m[i] = 0; ++ sfree(mem_ctx, m); ++ for (i = 0; i < plen; i++) ++ n[i] = 0; ++ sfree(mem_ctx, n); ++} ++ ++/* ++ * Simple remainder. ++ */ ++Bignum bigmod(void *mem_ctx, Bignum a, Bignum b) ++{ ++ Bignum r = newbn(mem_ctx, b[0]); ++ bigdivmod(mem_ctx, a, b, r, NULL); ++ return r; ++} ++ ++/* ++ * Compute (base ^ exp) % mod. ++ */ ++Bignum dwc_modpow(void *mem_ctx, Bignum base_in, Bignum exp, Bignum mod) ++{ ++ BignumInt *a, *b, *n, *m; ++ int mshift; ++ int mlen, i, j; ++ Bignum base, result; ++ ++ /* ++ * The most significant word of mod needs to be non-zero. It ++ * should already be, but let's make sure. ++ */ ++ //assert(mod[mod[0]] != 0); ++ ++ /* ++ * Make sure the base is smaller than the modulus, by reducing ++ * it modulo the modulus if not. ++ */ ++ base = bigmod(mem_ctx, base_in, mod); ++ ++ /* Allocate m of size mlen, copy mod to m */ ++ /* We use big endian internally */ ++ mlen = mod[0]; ++ m = snewn(mem_ctx, mlen, BignumInt); ++ //if (!m) ++ //abort(); /* FIXME */ ++ for (j = 0; j < mlen; j++) ++ m[j] = mod[mod[0] - j]; ++ ++ /* Shift m left to make msb bit set */ ++ for (mshift = 0; mshift < BIGNUM_INT_BITS - 1; mshift++) ++ if ((m[0] << mshift) & BIGNUM_TOP_BIT) ++ break; ++ if (mshift) { ++ for (i = 0; i < mlen - 1; i++) ++ m[i] = ++ (m[i] << mshift) | (m[i + 1] >> ++ (BIGNUM_INT_BITS - mshift)); ++ m[mlen - 1] = m[mlen - 1] << mshift; ++ } ++ ++ /* Allocate n of size mlen, copy base to n */ ++ n = snewn(mem_ctx, mlen, BignumInt); ++ //if (!n) ++ //abort(); /* FIXME */ ++ i = mlen - base[0]; ++ for (j = 0; j < i; j++) ++ n[j] = 0; ++ for (j = 0; j < base[0]; j++) ++ n[i + j] = base[base[0] - j]; ++ ++ /* Allocate a and b of size 2*mlen. Set a = 1 */ ++ a = snewn(mem_ctx, 2 * mlen, BignumInt); ++ //if (!a) ++ //abort(); /* FIXME */ ++ b = snewn(mem_ctx, 2 * mlen, BignumInt); ++ //if (!b) ++ //abort(); /* FIXME */ ++ for (i = 0; i < 2 * mlen; i++) ++ a[i] = 0; ++ a[2 * mlen - 1] = 1; ++ ++ /* Skip leading zero bits of exp. */ ++ i = 0; ++ j = BIGNUM_INT_BITS - 1; ++ while (i < exp[0] && (exp[exp[0] - i] & (1 << j)) == 0) { ++ j--; ++ if (j < 0) { ++ i++; ++ j = BIGNUM_INT_BITS - 1; ++ } ++ } ++ ++ /* Main computation */ ++ while (i < exp[0]) { ++ while (j >= 0) { ++ internal_mul(a + mlen, a + mlen, b, mlen); ++ internal_mod(b, mlen * 2, m, mlen, NULL, 0); ++ if ((exp[exp[0] - i] & (1 << j)) != 0) { ++ internal_mul(b + mlen, n, a, mlen); ++ internal_mod(a, mlen * 2, m, mlen, NULL, 0); ++ } else { ++ BignumInt *t; ++ t = a; ++ a = b; ++ b = t; ++ } ++ j--; ++ } ++ i++; ++ j = BIGNUM_INT_BITS - 1; ++ } ++ ++ /* Fixup result in case the modulus was shifted */ ++ if (mshift) { ++ for (i = mlen - 1; i < 2 * mlen - 1; i++) ++ a[i] = ++ (a[i] << mshift) | (a[i + 1] >> ++ (BIGNUM_INT_BITS - mshift)); ++ a[2 * mlen - 1] = a[2 * mlen - 1] << mshift; ++ internal_mod(a, mlen * 2, m, mlen, NULL, 0); ++ for (i = 2 * mlen - 1; i >= mlen; i--) ++ a[i] = ++ (a[i] >> mshift) | (a[i - 1] << ++ (BIGNUM_INT_BITS - mshift)); ++ } ++ ++ /* Copy result to buffer */ ++ result = newbn(mem_ctx, mod[0]); ++ for (i = 0; i < mlen; i++) ++ result[result[0] - i] = a[i + mlen]; ++ while (result[0] > 1 && result[result[0]] == 0) ++ result[0]--; ++ ++ /* Free temporary arrays */ ++ for (i = 0; i < 2 * mlen; i++) ++ a[i] = 0; ++ sfree(mem_ctx, a); ++ for (i = 0; i < 2 * mlen; i++) ++ b[i] = 0; ++ sfree(mem_ctx, b); ++ for (i = 0; i < mlen; i++) ++ m[i] = 0; ++ sfree(mem_ctx, m); ++ for (i = 0; i < mlen; i++) ++ n[i] = 0; ++ sfree(mem_ctx, n); ++ ++ freebn(mem_ctx, base); ++ ++ return result; ++} ++ ++ ++#ifdef UNITTEST ++ ++static __u32 dh_p[] = { ++ 96, ++ 0xFFFFFFFF, ++ 0xFFFFFFFF, ++ 0xA93AD2CA, ++ 0x4B82D120, ++ 0xE0FD108E, ++ 0x43DB5BFC, ++ 0x74E5AB31, ++ 0x08E24FA0, ++ 0xBAD946E2, ++ 0x770988C0, ++ 0x7A615D6C, ++ 0xBBE11757, ++ 0x177B200C, ++ 0x521F2B18, ++ 0x3EC86A64, ++ 0xD8760273, ++ 0xD98A0864, ++ 0xF12FFA06, ++ 0x1AD2EE6B, ++ 0xCEE3D226, ++ 0x4A25619D, ++ 0x1E8C94E0, ++ 0xDB0933D7, ++ 0xABF5AE8C, ++ 0xA6E1E4C7, ++ 0xB3970F85, ++ 0x5D060C7D, ++ 0x8AEA7157, ++ 0x58DBEF0A, ++ 0xECFB8504, ++ 0xDF1CBA64, ++ 0xA85521AB, ++ 0x04507A33, ++ 0xAD33170D, ++ 0x8AAAC42D, ++ 0x15728E5A, ++ 0x98FA0510, ++ 0x15D22618, ++ 0xEA956AE5, ++ 0x3995497C, ++ 0x95581718, ++ 0xDE2BCBF6, ++ 0x6F4C52C9, ++ 0xB5C55DF0, ++ 0xEC07A28F, ++ 0x9B2783A2, ++ 0x180E8603, ++ 0xE39E772C, ++ 0x2E36CE3B, ++ 0x32905E46, ++ 0xCA18217C, ++ 0xF1746C08, ++ 0x4ABC9804, ++ 0x670C354E, ++ 0x7096966D, ++ 0x9ED52907, ++ 0x208552BB, ++ 0x1C62F356, ++ 0xDCA3AD96, ++ 0x83655D23, ++ 0xFD24CF5F, ++ 0x69163FA8, ++ 0x1C55D39A, ++ 0x98DA4836, ++ 0xA163BF05, ++ 0xC2007CB8, ++ 0xECE45B3D, ++ 0x49286651, ++ 0x7C4B1FE6, ++ 0xAE9F2411, ++ 0x5A899FA5, ++ 0xEE386BFB, ++ 0xF406B7ED, ++ 0x0BFF5CB6, ++ 0xA637ED6B, ++ 0xF44C42E9, ++ 0x625E7EC6, ++ 0xE485B576, ++ 0x6D51C245, ++ 0x4FE1356D, ++ 0xF25F1437, ++ 0x302B0A6D, ++ 0xCD3A431B, ++ 0xEF9519B3, ++ 0x8E3404DD, ++ 0x514A0879, ++ 0x3B139B22, ++ 0x020BBEA6, ++ 0x8A67CC74, ++ 0x29024E08, ++ 0x80DC1CD1, ++ 0xC4C6628B, ++ 0x2168C234, ++ 0xC90FDAA2, ++ 0xFFFFFFFF, ++ 0xFFFFFFFF, ++}; ++ ++static __u32 dh_a[] = { ++ 8, ++ 0xdf367516, ++ 0x86459caa, ++ 0xe2d459a4, ++ 0xd910dae0, ++ 0x8a8b5e37, ++ 0x67ab31c6, ++ 0xf0b55ea9, ++ 0x440051d6, ++}; ++ ++static __u32 dh_b[] = { ++ 8, ++ 0xded92656, ++ 0xe07a048a, ++ 0x6fa452cd, ++ 0x2df89d30, ++ 0xc75f1b0f, ++ 0x8ce3578f, ++ 0x7980a324, ++ 0x5daec786, ++}; ++ ++static __u32 dh_g[] = { ++ 1, ++ 2, ++}; ++ ++int main(void) ++{ ++ int i; ++ __u32 *k; ++ k = dwc_modpow(NULL, dh_g, dh_a, dh_p); ++ ++ printf("\n\n"); ++ for (i=0; i> 16; ++ printf("%04x %04x ", m, l); ++ if (!((i + 1)%13)) printf("\n"); ++ } ++ printf("\n\n"); ++ ++ if ((k[0] == 0x60) && (k[1] == 0x28e490e5) && (k[0x60] == 0x5a0d3d4e)) { ++ printf("PASS\n\n"); ++ } ++ else { ++ printf("FAIL\n\n"); ++ } ++ ++} ++ ++#endif /* UNITTEST */ ++ ++#endif /* CONFIG_MACH_IPMATE */ ++ ++#endif /*DWC_CRYPTOLIB */ +Index: linux-3.2.46/drivers/usb/host/dwc_common_port/dwc_modpow.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_common_port/dwc_modpow.h 2013-07-26 19:34:39.000000000 +0000 +@@ -0,0 +1,34 @@ ++/* ++ * dwc_modpow.h ++ * See dwc_modpow.c for license and changes ++ */ ++#ifndef _DWC_MODPOW_H ++#define _DWC_MODPOW_H ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++#include "dwc_os.h" ++ ++/** @file ++ * ++ * This file defines the module exponentiation function which is only used ++ * internally by the DWC UWB modules for calculation of PKs during numeric ++ * association. The routine is taken from the PUTTY, an open source terminal ++ * emulator. The PUTTY License is preserved in the dwc_modpow.c file. ++ * ++ */ ++ ++typedef uint32_t BignumInt; ++typedef uint64_t BignumDblInt; ++typedef BignumInt *Bignum; ++ ++/* Compute modular exponentiaion */ ++extern Bignum dwc_modpow(void *mem_ctx, Bignum base_in, Bignum exp, Bignum mod); ++ ++#ifdef __cplusplus ++} ++#endif ++ ++#endif /* _LINUX_BIGNUM_H */ +Index: linux-3.2.46/drivers/usb/host/dwc_common_port/dwc_notifier.c +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_common_port/dwc_notifier.c 2013-07-26 19:31:20.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_common_port/dwc_notifier.c 2013-07-26 19:34:39.000000000 +0000 +@@ -1,8 +1,9 @@ ++#ifdef DWC_NOTIFYLIB ++ + #include "dwc_notifier.h" + #include "dwc_list.h" + +-typedef struct dwc_observer +-{ ++typedef struct dwc_observer { + void *observer; + dwc_notifier_callback_t callback; + void *data; +@@ -12,8 +13,8 @@ + + DWC_CIRCLEQ_HEAD(observer_queue, dwc_observer); + +-typedef struct dwc_notifier +-{ ++typedef struct dwc_notifier { ++ void *mem_ctx; + void *object; + struct observer_queue observers; + DWC_CIRCLEQ_ENTRY(dwc_notifier) list_entry; +@@ -21,30 +22,43 @@ + + DWC_CIRCLEQ_HEAD(notifier_queue, dwc_notifier); + +-typedef struct manager +-{ ++typedef struct manager { ++ void *mem_ctx; ++ void *wkq_ctx; + dwc_workq_t *wq; +- dwc_mutex_t *mutex; ++// dwc_mutex_t *mutex; + struct notifier_queue notifiers; + } manager_t; + + static manager_t *manager = NULL; + +-static void create_manager(void) ++static int create_manager(void *mem_ctx, void *wkq_ctx) + { +- manager = DWC_ALLOC(sizeof(manager_t)); ++ manager = dwc_alloc(mem_ctx, sizeof(manager_t)); ++ if (!manager) { ++ return -DWC_E_NO_MEMORY; ++ } ++ + DWC_CIRCLEQ_INIT(&manager->notifiers); +- manager->wq = DWC_WORKQ_ALLOC("DWC Notification WorkQ"); ++ ++ manager->wq = dwc_workq_alloc(wkq_ctx, "DWC Notification WorkQ"); ++ if (!manager->wq) { ++ return -DWC_E_NO_MEMORY; ++ } ++ ++ return 0; + } + + static void free_manager(void) + { +- DWC_WORKQ_FREE(manager->wq); ++ dwc_workq_free(manager->wq); ++ + /* All notifiers must have unregistered themselves before this module + * can be removed. Hitting this assertion indicates a programmer + * error. */ +- DWC_ASSERT(DWC_CIRCLEQ_EMPTY(&manager->notifiers), "Notification manager being freed before all notifiers have been removed"); +- DWC_FREE(manager); ++ DWC_ASSERT(DWC_CIRCLEQ_EMPTY(&manager->notifiers), ++ "Notification manager being freed before all notifiers have been removed"); ++ dwc_free(manager->mem_ctx, manager); + } + + #ifdef DEBUG +@@ -52,12 +66,14 @@ + { + notifier_t *n; + observer_t *o; ++ + DWC_ASSERT(manager, "Notification manager not found"); +- DWC_DEBUG("List of all notifiers and observers:"); ++ ++ DWC_DEBUG("List of all notifiers and observers:\n"); + DWC_CIRCLEQ_FOREACH(n, &manager->notifiers, list_entry) { +- DWC_DEBUG("Notifier %p has observers:", n->object); ++ DWC_DEBUG("Notifier %p has observers:\n", n->object); + DWC_CIRCLEQ_FOREACH(o, &n->observers, list_entry) { +- DWC_DEBUG(" %p watching %s", o->observer, o->notification); ++ DWC_DEBUG(" %p watching %s\n", o->observer, o->notification); + } + } + } +@@ -65,9 +81,15 @@ + #define dump_manager(...) + #endif + +-static observer_t *alloc_observer(void *observer, char *notification, dwc_notifier_callback_t callback, void *data) ++static observer_t *alloc_observer(void *mem_ctx, void *observer, char *notification, ++ dwc_notifier_callback_t callback, void *data) + { +- observer_t *new_observer = DWC_ALLOC(sizeof(observer_t)); ++ observer_t *new_observer = dwc_alloc(mem_ctx, sizeof(observer_t)); ++ ++ if (!new_observer) { ++ return NULL; ++ } ++ + DWC_CIRCLEQ_INIT_ENTRY(new_observer, list_entry); + new_observer->observer = observer; + new_observer->notification = notification; +@@ -76,12 +98,12 @@ + return new_observer; + } + +-static void free_observer(observer_t *observer) ++static void free_observer(void *mem_ctx, observer_t *observer) + { +- DWC_FREE(observer); ++ dwc_free(mem_ctx, observer); + } + +-static notifier_t *alloc_notifier(void *object) ++static notifier_t *alloc_notifier(void *mem_ctx, void *object) + { + notifier_t *notifier; + +@@ -89,10 +111,15 @@ + return NULL; + } + +- notifier = DWC_ALLOC(sizeof(notifier_t)); ++ notifier = dwc_alloc(mem_ctx, sizeof(notifier_t)); ++ if (!notifier) { ++ return NULL; ++ } ++ + DWC_CIRCLEQ_INIT(¬ifier->observers); + DWC_CIRCLEQ_INIT_ENTRY(notifier, list_entry); + ++ notifier->mem_ctx = mem_ctx; + notifier->object = object; + return notifier; + } +@@ -100,30 +127,36 @@ + static void free_notifier(notifier_t *notifier) + { + observer_t *observer; ++ + DWC_CIRCLEQ_FOREACH(observer, ¬ifier->observers, list_entry) { +- free_observer(observer); ++ free_observer(notifier->mem_ctx, observer); + } +- DWC_FREE(notifier); ++ ++ dwc_free(notifier->mem_ctx, notifier); + } + + static notifier_t *find_notifier(void *object) + { + notifier_t *notifier; ++ ++ DWC_ASSERT(manager, "Notification manager not found"); ++ + if (!object) { + return NULL; + } +- DWC_ASSERT(manager, "Notification manager not found"); ++ + DWC_CIRCLEQ_FOREACH(notifier, &manager->notifiers, list_entry) { + if (notifier->object == object) { + return notifier; + } + } ++ + return NULL; + } + +-void dwc_alloc_notification_manager(void) ++int dwc_alloc_notification_manager(void *mem_ctx, void *wkq_ctx) + { +- create_manager(); ++ return create_manager(mem_ctx, wkq_ctx); + } + + void dwc_free_notification_manager(void) +@@ -131,18 +164,24 @@ + free_manager(); + } + +-dwc_notifier_t *dwc_register_notifier(void *object) ++dwc_notifier_t *dwc_register_notifier(void *mem_ctx, void *object) + { +- notifier_t *notifier = find_notifier(object); ++ notifier_t *notifier; ++ + DWC_ASSERT(manager, "Notification manager not found"); ++ ++ notifier = find_notifier(object); + if (notifier) { +- DWC_ERROR("Notifier %p is already registered", object); ++ DWC_ERROR("Notifier %p is already registered\n", object); + return NULL; + } + +- notifier = alloc_notifier(object); +- DWC_CIRCLEQ_INSERT_TAIL(&manager->notifiers, notifier, list_entry); ++ notifier = alloc_notifier(mem_ctx, object); ++ if (!notifier) { ++ return NULL; ++ } + ++ DWC_CIRCLEQ_INSERT_TAIL(&manager->notifiers, notifier, list_entry); + + DWC_INFO("Notifier %p registered", object); + dump_manager(); +@@ -153,13 +192,17 @@ + void dwc_unregister_notifier(dwc_notifier_t *notifier) + { + DWC_ASSERT(manager, "Notification manager not found"); ++ + if (!DWC_CIRCLEQ_EMPTY(¬ifier->observers)) { + observer_t *o; +- DWC_ERROR("Notifier %p has active observers when removing", notifier->object); ++ ++ DWC_ERROR("Notifier %p has active observers when removing\n", notifier->object); + DWC_CIRCLEQ_FOREACH(o, ¬ifier->observers, list_entry) { +- DWC_DEBUG(" %p watching %s", o->observer, o->notification); ++ DWC_DEBUGC(" %p watching %s\n", o->observer, o->notification); + } +- DWC_ASSERT(DWC_CIRCLEQ_EMPTY(¬ifier->observers), "Notifier %p has active observers when removing", notifier); ++ ++ DWC_ASSERT(DWC_CIRCLEQ_EMPTY(¬ifier->observers), ++ "Notifier %p has active observers when removing", notifier); + } + + DWC_CIRCLEQ_REMOVE_INIT(&manager->notifiers, notifier, list_entry); +@@ -170,16 +213,21 @@ + } + + /* Add an observer to observe the notifier for a particular state, event, or notification. */ +-int dwc_add_observer(void *observer, void *object, char *notification, dwc_notifier_callback_t callback, void *data) ++int dwc_add_observer(void *observer, void *object, char *notification, ++ dwc_notifier_callback_t callback, void *data) + { + notifier_t *notifier = find_notifier(object); + observer_t *new_observer; ++ + if (!notifier) { +- DWC_ERROR("Notifier %p is not found when adding observer", object); +- return -1; ++ DWC_ERROR("Notifier %p is not found when adding observer\n", object); ++ return -DWC_E_INVALID; + } + +- new_observer = alloc_observer(observer, notification, callback, data); ++ new_observer = alloc_observer(notifier->mem_ctx, observer, notification, callback, data); ++ if (!new_observer) { ++ return -DWC_E_NO_MEMORY; ++ } + + DWC_CIRCLEQ_INSERT_TAIL(¬ifier->observers, new_observer, list_entry); + +@@ -193,16 +241,19 @@ + int dwc_remove_observer(void *observer) + { + notifier_t *n; ++ + DWC_ASSERT(manager, "Notification manager not found"); ++ + DWC_CIRCLEQ_FOREACH(n, &manager->notifiers, list_entry) { + observer_t *o; + observer_t *o2; ++ + DWC_CIRCLEQ_FOREACH_SAFE(o, o2, &n->observers, list_entry) { + if (o->observer == observer) { + DWC_CIRCLEQ_REMOVE_INIT(&n->observers, o, list_entry); + DWC_INFO("Removing observer %p from notifier %p watching notification %s:", + o->observer, n->object, o->notification); +- free_observer(o); ++ free_observer(n->mem_ctx, o); + } + } + } +@@ -211,42 +262,53 @@ + return 0; + } + +-typedef struct callback_data +-{ ++typedef struct callback_data { ++ void *mem_ctx; + dwc_notifier_callback_t cb; + void *observer; + void *data; + void *object; +- void *notification; ++ char *notification; + void *notification_data; + } cb_data_t; + + static void cb_task(void *data) + { + cb_data_t *cb = (cb_data_t *)data; ++ + cb->cb(cb->object, cb->notification, cb->observer, cb->notification_data, cb->data); +- DWC_FREE(cb); ++ dwc_free(cb->mem_ctx, cb); + } + + void dwc_notify(dwc_notifier_t *notifier, char *notification, void *notification_data) + { + observer_t *o; ++ + DWC_ASSERT(manager, "Notification manager not found"); ++ + DWC_CIRCLEQ_FOREACH(o, ¬ifier->observers, list_entry) { + int len = DWC_STRLEN(notification); ++ + if (DWC_STRLEN(o->notification) != len) { + continue; + } + + if (DWC_STRNCMP(o->notification, notification, len) == 0) { +- cb_data_t *cb_data = DWC_ALLOC(sizeof(cb_data_t)); ++ cb_data_t *cb_data = dwc_alloc(notifier->mem_ctx, sizeof(cb_data_t)); ++ ++ if (!cb_data) { ++ DWC_ERROR("Failed to allocate callback data\n"); ++ return; ++ } ++ ++ cb_data->mem_ctx = notifier->mem_ctx; + cb_data->cb = o->callback; + cb_data->observer = o->observer; + cb_data->data = o->data; + cb_data->object = notifier->object; + cb_data->notification = notification; + cb_data->notification_data = notification_data; +- DWC_DEBUG("Observer found %p for notification %s", o->observer, notification); ++ DWC_DEBUGC("Observer found %p for notification %s\n", o->observer, notification); + DWC_WORKQ_SCHEDULE(manager->wq, cb_task, cb_data, + "Notify callback from %p for Notification %s, to observer %p", + cb_data->object, notification, cb_data->observer); +@@ -254,3 +316,4 @@ + } + } + ++#endif /* DWC_NOTIFYLIB */ +Index: linux-3.2.46/drivers/usb/host/dwc_common_port/dwc_notifier.h +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_common_port/dwc_notifier.h 2013-07-26 19:31:20.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_common_port/dwc_notifier.h 2013-07-26 19:34:39.000000000 +0000 +@@ -2,6 +2,10 @@ + #ifndef __DWC_NOTIFIER_H__ + #define __DWC_NOTIFIER_H__ + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ + #include "dwc_os.h" + + /** @file +@@ -66,21 +70,22 @@ + * the documentation of the observable module with the notifications. + * @param user_data This is any custom data that the observer provided when + * adding itself as an observer to the notification. */ +-typedef void (*dwc_notifier_callback_t)(void *object, char *notification, void *observer, void *notification_data, void *user_data); ++typedef void (*dwc_notifier_callback_t)(void *object, char *notification, void *observer, ++ void *notification_data, void *user_data); + + /** Brings up the notification manager. */ +-extern void dwc_alloc_notification_manager(void); ++extern int dwc_alloc_notification_manager(void *mem_ctx, void *wkq_ctx); + /** Brings down the notification manager. */ + extern void dwc_free_notification_manager(void); + +-/** This function register an observable module. A dwc_notifier_t object is ++/** This function registers an observable module. A dwc_notifier_t object is + * returned to the observable module. This is an opaque object that is used by + * the observable module to trigger notifications. This object should only be + * accessible to functions that are authorized to trigger notifications for this + * module. Observers do not need this object. */ +-extern dwc_notifier_t *dwc_register_notifier(void *object); ++extern dwc_notifier_t *dwc_register_notifier(void *mem_ctx, void *object); + +-/** This function unregister an observable module. All observers have to be ++/** This function unregisters an observable module. All observers have to be + * removed prior to unregistration. */ + extern void dwc_unregister_notifier(dwc_notifier_t *notifier); + +@@ -92,7 +97,8 @@ + * @param notification The notification to observe + * @param callback The callback function to call + * @param user_data Any additional user data to pass into the callback function */ +-extern int dwc_add_observer(void *observer, void *object, char *notification, dwc_notifier_callback_t callback, void *user_data); ++extern int dwc_add_observer(void *observer, void *object, char *notification, ++ dwc_notifier_callback_t callback, void *user_data); + + /** Removes the specified observer from all notifications that it is currently + * observing. */ +@@ -109,4 +115,8 @@ + */ + void dwc_notify(dwc_notifier_t *notifier, char *notification, void *notification_data); + ++#ifdef __cplusplus ++} ++#endif ++ + #endif /* __DWC_NOTIFIER_H__ */ +Index: linux-3.2.46/drivers/usb/host/dwc_common_port/dwc_os.h +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_common_port/dwc_os.h 2013-07-26 19:32:22.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_common_port/dwc_os.h 2013-07-26 19:34:39.000000000 +0000 +@@ -1,8 +1,8 @@ + /* ========================================================================= +- * $File: //dwh/usb_iip/dev/software/dwc_common_port/dwc_os.h $ +- * $Revision: #2 $ +- * $Date: 2009/04/02 $ +- * $Change: 1224130 $ ++ * $File: //dwh/usb_iip/dev/software/dwc_common_port_2/dwc_os.h $ ++ * $Revision: #14 $ ++ * $Date: 2010/11/04 $ ++ * $Change: 1621695 $ + * + * Synopsys Portability Library Software and documentation + * (hereinafter, "Software") is an Unsupported proprietary work of +@@ -36,6 +36,10 @@ + #ifndef _DWC_OS_H_ + #define _DWC_OS_H_ + ++#ifdef __cplusplus ++extern "C" { ++#endif ++ + /** @file + * + * DWC portability library, low level os-wrapper functions +@@ -51,12 +55,16 @@ + */ + + #ifdef DWC_LINUX +-# include +-# ifdef CONFIG_DEBUG_MUTEXES +-# include +-# endif +-#else +-# include ++# include ++# ifdef CONFIG_DEBUG_MUTEXES ++# include ++# endif ++# include ++# include ++#endif ++ ++#if defined(DWC_FREEBSD) || defined(DWC_NETBSD) ++# include + #endif + + +@@ -67,29 +75,58 @@ + #define YES 1 + #define NO 0 + +-/** @todo make them positive and return the negative error code */ ++#ifdef DWC_LINUX ++ ++/** @name Error Codes */ ++#define DWC_E_INVALID EINVAL ++#define DWC_E_NO_MEMORY ENOMEM ++#define DWC_E_NO_DEVICE ENODEV ++#define DWC_E_NOT_SUPPORTED EOPNOTSUPP ++#define DWC_E_TIMEOUT ETIMEDOUT ++#define DWC_E_BUSY EBUSY ++#define DWC_E_AGAIN EAGAIN ++#define DWC_E_RESTART ERESTART ++#define DWC_E_ABORT ECONNABORTED ++#define DWC_E_SHUTDOWN ESHUTDOWN ++#define DWC_E_NO_DATA ENODATA ++#define DWC_E_DISCONNECT ECONNRESET ++#define DWC_E_UNKNOWN EINVAL ++#define DWC_E_NO_STREAM_RES ENOSR ++#define DWC_E_COMMUNICATION ECOMM ++#define DWC_E_OVERFLOW EOVERFLOW ++#define DWC_E_PROTOCOL EPROTO ++#define DWC_E_IN_PROGRESS EINPROGRESS ++#define DWC_E_PIPE EPIPE ++#define DWC_E_IO EIO ++#define DWC_E_NO_SPACE ENOSPC ++ ++#else ++ + /** @name Error Codes */ +-#define DWC_E_INVALID 1001 +-#define DWC_E_NO_MEMORY 1002 +-#define DWC_E_NO_DEVICE 1003 +-#define DWC_E_NOT_SUPPORTED 1004 +-#define DWC_E_TIMEOUT 1005 +-#define DWC_E_BUSY 1006 +-#define DWC_E_AGAIN 1007 +-#define DWC_E_RESTART 1008 +-#define DWC_E_ABORT 1009 +-#define DWC_E_SHUTDOWN 1010 +-#define DWC_E_NO_DATA 1011 +-#define DWC_E_DISCONNECT 2000 +-#define DWC_E_UNKNOWN 3000 +-#define DWC_E_NO_STREAM_RES 4001 +-#define DWC_E_COMMUNICATION 4002 +-#define DWC_E_OVERFLOW 4003 +-#define DWC_E_PROTOCOL 4004 +-#define DWC_E_IN_PROGRESS 4005 +-#define DWC_E_PIPE 4006 +-#define DWC_E_IO 4007 +-#define DWC_E_NO_SPACE 4008 ++#define DWC_E_INVALID 1001 ++#define DWC_E_NO_MEMORY 1002 ++#define DWC_E_NO_DEVICE 1003 ++#define DWC_E_NOT_SUPPORTED 1004 ++#define DWC_E_TIMEOUT 1005 ++#define DWC_E_BUSY 1006 ++#define DWC_E_AGAIN 1007 ++#define DWC_E_RESTART 1008 ++#define DWC_E_ABORT 1009 ++#define DWC_E_SHUTDOWN 1010 ++#define DWC_E_NO_DATA 1011 ++#define DWC_E_DISCONNECT 2000 ++#define DWC_E_UNKNOWN 3000 ++#define DWC_E_NO_STREAM_RES 4001 ++#define DWC_E_COMMUNICATION 4002 ++#define DWC_E_OVERFLOW 4003 ++#define DWC_E_PROTOCOL 4004 ++#define DWC_E_IN_PROGRESS 4005 ++#define DWC_E_PIPE 4006 ++#define DWC_E_IO 4007 ++#define DWC_E_NO_SPACE 4008 ++ ++#endif ++ + + /** @name Tracing/Logging Functions + * +@@ -100,8 +137,6 @@ + * expensive on your system. By default undefining the DEBUG macro already + * no-ops some of these functions. */ + +-#include +- + /** Returns non-zero if in interrupt context. */ + extern dwc_bool_t DWC_IN_IRQ(void); + #define dwc_in_irq DWC_IN_IRQ +@@ -111,6 +146,15 @@ + return DWC_IN_IRQ() ? "IRQ" : ""; + } + ++/** Returns non-zero if in bottom-half context. */ ++extern dwc_bool_t DWC_IN_BH(void); ++#define dwc_in_bh DWC_IN_BH ++ ++/** Returns "BH" if DWC_IN_BH is true. */ ++static inline char *dwc_bh(void) { ++ return DWC_IN_BH() ? "BH" : ""; ++} ++ + /** + * A vprintf() clone. Just call vprintf if you've got it. + */ +@@ -132,7 +176,7 @@ + #ifdef __GNUC__ + __attribute__ ((format(printf, 1, 2))); + #else +- ; ++ ; + #endif + #define dwc_printf DWC_PRINTF + +@@ -141,9 +185,9 @@ + */ + extern int DWC_SPRINTF(char *string, char *format, ...) + #ifdef __GNUC__ +- __attribute__ ((format(printf, 2, 3))); ++ __attribute__ ((format(printf, 2, 3))); + #else +- ; ++ ; + #endif + #define dwc_sprintf DWC_SPRINTF + +@@ -152,9 +196,9 @@ + */ + extern int DWC_SNPRINTF(char *string, int size, char *format, ...) + #ifdef __GNUC__ +- __attribute__ ((format(printf, 3, 4))); ++ __attribute__ ((format(printf, 3, 4))); + #else +- ; ++ ; + #endif + #define dwc_snprintf DWC_SNPRINTF + +@@ -167,23 +211,23 @@ + */ + extern void __DWC_WARN(char *format, ...) + #ifdef __GNUC__ +- __attribute__ ((format(printf, 1, 2))); ++ __attribute__ ((format(printf, 1, 2))); + #else +- ; ++ ; + #endif + + /** + * Prints an error message. On systems that don't differentiate between errors + * and regular log messages, just print it. Indicates that something went wrong +- * with the driver, but it can be recovered from. Works like printf(). ++ * with the driver. Works like printf(). + * + * Use the DWC_ERROR macro to call this function. + */ + extern void __DWC_ERROR(char *format, ...) + #ifdef __GNUC__ +- __attribute__ ((format(printf, 1, 2))); ++ __attribute__ ((format(printf, 1, 2))); + #else +- ; ++ ; + #endif + + /** +@@ -196,12 +240,16 @@ + */ + extern void DWC_EXCEPTION(char *format, ...) + #ifdef __GNUC__ +- __attribute__ ((format(printf, 1, 2))); ++ __attribute__ ((format(printf, 1, 2))); + #else +- ; ++ ; + #endif + #define dwc_exception DWC_EXCEPTION + ++#ifndef DWC_OTG_DEBUG_LEV ++#define DWC_OTG_DEBUG_LEV 0 ++#endif ++ + #ifdef DEBUG + /** + * Prints out a debug message. Used for logging/trace messages. +@@ -210,120 +258,203 @@ + */ + extern void __DWC_DEBUG(char *format, ...) + #ifdef __GNUC__ +- __attribute__ ((format(printf, 1, 2))); ++ __attribute__ ((format(printf, 1, 2))); + #else +- ; ++ ; + #endif + #else + #define __DWC_DEBUG printk +-#include + #endif + + /** + * Prints out a Debug message. + */ +-#define DWC_DEBUG(_format, _args...) __DWC_DEBUG("DEBUG:%s:%s: " _format "\n", __func__, dwc_irq(), ## _args) ++#define DWC_DEBUG(_format, _args...) __DWC_DEBUG("DEBUG:%s:%s: " _format "\n", \ ++ __func__, dwc_irq(), ## _args) + #define dwc_debug DWC_DEBUG + /** ++ * Prints out a Debug message if enabled at compile time. ++ */ ++#if DWC_OTG_DEBUG_LEV > 0 ++#define DWC_DEBUGC(_format, _args...) DWC_DEBUG(_format, ##_args ) ++#else ++#define DWC_DEBUGC(_format, _args...) ++#endif ++#define dwc_debugc DWC_DEBUGC ++/** + * Prints out an informative message. + */ +-#define DWC_INFO(_format, _args...) DWC_PRINTF("INFO:%s: " _format "\n", dwc_irq(), ## _args) ++#define DWC_INFO(_format, _args...) DWC_PRINTF("INFO:%s: " _format "\n", \ ++ dwc_irq(), ## _args) + #define dwc_info DWC_INFO + /** ++ * Prints out an informative message if enabled at compile time. ++ */ ++#if DWC_OTG_DEBUG_LEV > 1 ++#define DWC_INFOC(_format, _args...) DWC_INFO(_format, ##_args ) ++#else ++#define DWC_INFOC(_format, _args...) ++#endif ++#define dwc_infoc DWC_INFOC ++/** + * Prints out a warning message. + */ +-#define DWC_WARN(_format, _args...) __DWC_WARN("WARN:%s:%s:%d: " _format "\n", dwc_irq(), __func__, __LINE__, ## _args) ++#define DWC_WARN(_format, _args...) __DWC_WARN("WARN:%s:%s:%d: " _format "\n", \ ++ dwc_irq(), __func__, __LINE__, ## _args) + #define dwc_warn DWC_WARN + /** + * Prints out an error message. + */ +-#define DWC_ERROR(_format, _args...) __DWC_ERROR("ERROR:%s:%s:%d: " _format "\n", dwc_irq(), __func__, __LINE__, ## _args) ++#define DWC_ERROR(_format, _args...) __DWC_ERROR("ERROR:%s:%s:%d: " _format "\n", \ ++ dwc_irq(), __func__, __LINE__, ## _args) + #define dwc_error DWC_ERROR + +-#define DWC_PROTO_ERROR(_format, _args...) __DWC_WARN("ERROR:%s:%s:%d: " _format "\n", dwc_irq(), __func__, __LINE__, ## _args) ++#define DWC_PROTO_ERROR(_format, _args...) __DWC_WARN("ERROR:%s:%s:%d: " _format "\n", \ ++ dwc_irq(), __func__, __LINE__, ## _args) + #define dwc_proto_error DWC_PROTO_ERROR + + #ifdef DEBUG + /** Prints out a exception error message if the _expr expression fails. Disabled + * if DEBUG is not enabled. */ +-#define DWC_ASSERT(_expr, _format, _args...) if (!(_expr)) { DWC_EXCEPTION("%s:%s:%d: " _format "\n", dwc_irq(), __FILE__, __LINE__, ## _args); } ++#define DWC_ASSERT(_expr, _format, _args...) do { \ ++ if (!(_expr)) { DWC_EXCEPTION("%s:%s:%d: " _format "\n", dwc_irq(), \ ++ __FILE__, __LINE__, ## _args); } \ ++ } while (0) + #else + #define DWC_ASSERT(_x...) + #endif + #define dwc_assert DWC_ASSERT + +-/** @name Byter Ordering ++ ++/** @name Byte Ordering + * The following functions are for conversions between processor's byte ordering + * and specific ordering you want. + */ + + /** Converts 32 bit data in CPU byte ordering to little endian. */ +-extern uint32_t DWC_CPU_TO_LE32(void *p); ++extern uint32_t DWC_CPU_TO_LE32(uint32_t *p); + #define dwc_cpu_to_le32 DWC_CPU_TO_LE32 ++ + /** Converts 32 bit data in CPU byte orderint to big endian. */ +-extern uint32_t DWC_CPU_TO_BE32(void *p); ++extern uint32_t DWC_CPU_TO_BE32(uint32_t *p); + #define dwc_cpu_to_be32 DWC_CPU_TO_BE32 + + /** Converts 32 bit little endian data to CPU byte ordering. */ +-extern uint32_t DWC_LE32_TO_CPU(void *p); ++extern uint32_t DWC_LE32_TO_CPU(uint32_t *p); + #define dwc_le32_to_cpu DWC_LE32_TO_CPU ++ + /** Converts 32 bit big endian data to CPU byte ordering. */ +-extern uint32_t DWC_BE32_TO_CPU(void *p); ++extern uint32_t DWC_BE32_TO_CPU(uint32_t *p); + #define dwc_be32_to_cpu DWC_BE32_TO_CPU + + /** Converts 16 bit data in CPU byte ordering to little endian. */ +-extern uint16_t DWC_CPU_TO_LE16(void *p); ++extern uint16_t DWC_CPU_TO_LE16(uint16_t *p); + #define dwc_cpu_to_le16 DWC_CPU_TO_LE16 ++ + /** Converts 16 bit data in CPU byte orderint to big endian. */ +-extern uint16_t DWC_CPU_TO_BE16(void *p); ++extern uint16_t DWC_CPU_TO_BE16(uint16_t *p); + #define dwc_cpu_to_be16 DWC_CPU_TO_BE16 + + /** Converts 16 bit little endian data to CPU byte ordering. */ +-extern uint16_t DWC_LE16_TO_CPU(void *p); ++extern uint16_t DWC_LE16_TO_CPU(uint16_t *p); + #define dwc_le16_to_cpu DWC_LE16_TO_CPU ++ + /** Converts 16 bit bi endian data to CPU byte ordering. */ +-extern uint16_t DWC_BE16_TO_CPU(void *p); ++extern uint16_t DWC_BE16_TO_CPU(uint16_t *p); + #define dwc_be16_to_cpu DWC_BE16_TO_CPU + ++ + /** @name Register Read/Write + * +- * The following five functions should be implemented to read/write registers of ++ * The following six functions should be implemented to read/write registers of + * 32-bit and 64-bit sizes. All modules use this to read/write register values. + * The reg value is a pointer to the register calculated from the void *base + * variable passed into the driver when it is started. */ + ++#ifdef DWC_LINUX ++/* Linux doesn't need any extra parameters for register read/write, so we ++ * just throw away the IO context parameter. ++ */ + /** Reads the content of a 32-bit register. */ + extern uint32_t DWC_READ_REG32(uint32_t volatile *reg); +-#define dwc_read_reg32 DWC_READ_REG32 ++#define dwc_read_reg32(_ctx_,_reg_) DWC_READ_REG32(_reg_) ++ + /** Reads the content of a 64-bit register. */ + extern uint64_t DWC_READ_REG64(uint64_t volatile *reg); +-#define dwc_read_reg64 DWC_READ_REG64 ++#define dwc_read_reg64(_ctx_,_reg_) DWC_READ_REG64(_reg_) ++ + /** Writes to a 32-bit register. */ + extern void DWC_WRITE_REG32(uint32_t volatile *reg, uint32_t value); +-#define dwc_write_reg32 DWC_WRITE_REG32 ++#define dwc_write_reg32(_ctx_,_reg_,_val_) DWC_WRITE_REG32(_reg_, _val_) ++ + /** Writes to a 64-bit register. */ + extern void DWC_WRITE_REG64(uint64_t volatile *reg, uint64_t value); +-#define dwc_write_reg64 DWC_WRITE_REG64 +-/** ++#define dwc_write_reg64(_ctx_,_reg_,_val_) DWC_WRITE_REG64(_reg_, _val_) ++ ++/** + * Modify bit values in a register. Using the + * algorithm: (reg_contents & ~clear_mask) | set_mask. + */ + extern void DWC_MODIFY_REG32(uint32_t volatile *reg, uint32_t clear_mask, uint32_t set_mask); ++#define dwc_modify_reg32(_ctx_,_reg_,_cmsk_,_smsk_) DWC_MODIFY_REG32(_reg_,_cmsk_,_smsk_) ++extern void DWC_MODIFY_REG64(uint64_t volatile *reg, uint64_t clear_mask, uint64_t set_mask); ++#define dwc_modify_reg64(_ctx_,_reg_,_cmsk_,_smsk_) DWC_MODIFY_REG64(_reg_,_cmsk_,_smsk_) ++ ++#endif /* DWC_LINUX */ ++ ++#if defined(DWC_FREEBSD) || defined(DWC_NETBSD) ++typedef struct dwc_ioctx { ++ struct device *dev; ++ bus_space_tag_t iot; ++ bus_space_handle_t ioh; ++} dwc_ioctx_t; ++ ++/** BSD needs two extra parameters for register read/write, so we pass ++ * them in using the IO context parameter. ++ */ ++/** Reads the content of a 32-bit register. */ ++extern uint32_t DWC_READ_REG32(void *io_ctx, uint32_t volatile *reg); ++#define dwc_read_reg32 DWC_READ_REG32 ++ ++/** Reads the content of a 64-bit register. */ ++extern uint64_t DWC_READ_REG64(void *io_ctx, uint64_t volatile *reg); ++#define dwc_read_reg64 DWC_READ_REG64 ++ ++/** Writes to a 32-bit register. */ ++extern void DWC_WRITE_REG32(void *io_ctx, uint32_t volatile *reg, uint32_t value); ++#define dwc_write_reg32 DWC_WRITE_REG32 ++ ++/** Writes to a 64-bit register. */ ++extern void DWC_WRITE_REG64(void *io_ctx, uint64_t volatile *reg, uint64_t value); ++#define dwc_write_reg64 DWC_WRITE_REG64 ++ ++/** ++ * Modify bit values in a register. Using the ++ * algorithm: (reg_contents & ~clear_mask) | set_mask. ++ */ ++extern void DWC_MODIFY_REG32(void *io_ctx, uint32_t volatile *reg, uint32_t clear_mask, uint32_t set_mask); + #define dwc_modify_reg32 DWC_MODIFY_REG32 ++extern void DWC_MODIFY_REG64(void *io_ctx, uint64_t volatile *reg, uint64_t clear_mask, uint64_t set_mask); ++#define dwc_modify_reg64 DWC_MODIFY_REG64 ++ ++#endif /* DWC_FREEBSD || DWC_NETBSD */ + + /** @cond */ + +-/** @name Some convenience MACROS used internally. Define DEBUG_REGS to log the ++/** @name Some convenience MACROS used internally. Define DWC_DEBUG_REGS to log the + * register writes. */ + +-#ifdef DEBUG_REGS ++#ifdef DWC_LINUX ++ ++# ifdef DWC_DEBUG_REGS + + #define dwc_define_read_write_reg_n(_reg,_container_type) \ + static inline uint32_t dwc_read_##_reg##_n(_container_type *container, int num) { \ + return DWC_READ_REG32(&container->regs->_reg[num]); \ + } \ + static inline void dwc_write_##_reg##_n(_container_type *container, int num, uint32_t data) { \ +- DWC_DEBUG("WRITING %8s[%d]: %p: %08x", #_reg, num, &(((uint32_t*)container->regs->_reg)[num]), data); \ ++ DWC_DEBUG("WRITING %8s[%d]: %p: %08x", #_reg, num, \ ++ &(((uint32_t*)container->regs->_reg)[num]), data); \ + DWC_WRITE_REG32(&(((uint32_t*)container->regs->_reg)[num]), data); \ + } + +@@ -332,11 +463,11 @@ + return DWC_READ_REG32(&container->regs->_reg); \ + } \ + static inline void dwc_write_##_reg(_container_type *container, uint32_t data) { \ +- DWC_DEBUG("WRITING %11s: %p: %08x", #_reg, &container->regs->_reg, data); \ ++ DWC_DEBUG("WRITING %11s: %p: %08x", #_reg, &container->regs->_reg, data); \ + DWC_WRITE_REG32(&container->regs->_reg, data); \ + } + +-#else ++# else /* DWC_DEBUG_REGS */ + + #define dwc_define_read_write_reg_n(_reg,_container_type) \ + static inline uint32_t dwc_read_##_reg##_n(_container_type *container, int num) { \ +@@ -354,11 +485,59 @@ + DWC_WRITE_REG32(&container->regs->_reg, data); \ + } + +-#endif ++# endif /* DWC_DEBUG_REGS */ ++ ++#endif /* DWC_LINUX */ ++ ++#if defined(DWC_FREEBSD) || defined(DWC_NETBSD) ++ ++# ifdef DWC_DEBUG_REGS ++ ++#define dwc_define_read_write_reg_n(_reg,_container_type) \ ++static inline uint32_t dwc_read_##_reg##_n(void *io_ctx, _container_type *container, int num) { \ ++ return DWC_READ_REG32(io_ctx, &container->regs->_reg[num]); \ ++} \ ++static inline void dwc_write_##_reg##_n(void *io_ctx, _container_type *container, int num, uint32_t data) { \ ++ DWC_DEBUG("WRITING %8s[%d]: %p: %08x", #_reg, num, \ ++ &(((uint32_t*)container->regs->_reg)[num]), data); \ ++ DWC_WRITE_REG32(io_ctx, &(((uint32_t*)container->regs->_reg)[num]), data); \ ++} ++ ++#define dwc_define_read_write_reg(_reg,_container_type) \ ++static inline uint32_t dwc_read_##_reg(void *io_ctx, _container_type *container) { \ ++ return DWC_READ_REG32(io_ctx, &container->regs->_reg); \ ++} \ ++static inline void dwc_write_##_reg(void *io_ctx, _container_type *container, uint32_t data) { \ ++ DWC_DEBUG("WRITING %11s: %p: %08x", #_reg, &container->regs->_reg, data); \ ++ DWC_WRITE_REG32(io_ctx, &container->regs->_reg, data); \ ++} ++ ++# else /* DWC_DEBUG_REGS */ ++ ++#define dwc_define_read_write_reg_n(_reg,_container_type) \ ++static inline uint32_t dwc_read_##_reg##_n(void *io_ctx, _container_type *container, int num) { \ ++ return DWC_READ_REG32(io_ctx, &container->regs->_reg[num]); \ ++} \ ++static inline void dwc_write_##_reg##_n(void *io_ctx, _container_type *container, int num, uint32_t data) { \ ++ DWC_WRITE_REG32(io_ctx, &(((uint32_t*)container->regs->_reg)[num]), data); \ ++} ++ ++#define dwc_define_read_write_reg(_reg,_container_type) \ ++static inline uint32_t dwc_read_##_reg(void *io_ctx, _container_type *container) { \ ++ return DWC_READ_REG32(io_ctx, &container->regs->_reg); \ ++} \ ++static inline void dwc_write_##_reg(void *io_ctx, _container_type *container, uint32_t data) { \ ++ DWC_WRITE_REG32(io_ctx, &container->regs->_reg, data); \ ++} ++ ++# endif /* DWC_DEBUG_REGS */ ++ ++#endif /* DWC_FREEBSD || DWC_NETBSD */ + + /** @endcond */ + + ++#ifdef DWC_CRYPTOLIB + /** @name Crypto Functions + * + * These are the low-level cryptographic functions used by the driver. */ +@@ -366,16 +545,21 @@ + /** Perform AES CBC */ + extern int DWC_AES_CBC(uint8_t *message, uint32_t messagelen, uint8_t *key, uint32_t keylen, uint8_t iv[16], uint8_t *out); + #define dwc_aes_cbc DWC_AES_CBC ++ + /** Fill the provided buffer with random bytes. These should be cryptographic grade random numbers. */ + extern void DWC_RANDOM_BYTES(uint8_t *buffer, uint32_t length); + #define dwc_random_bytes DWC_RANDOM_BYTES ++ + /** Perform the SHA-256 hash function */ + extern int DWC_SHA256(uint8_t *message, uint32_t len, uint8_t *out); + #define dwc_sha256 DWC_SHA256 ++ + /** Calculated the HMAC-SHA256 */ + extern int DWC_HMAC_SHA256(uint8_t *message, uint32_t messagelen, uint8_t *key, uint32_t keylen, uint8_t *out); + #define dwc_hmac_sha256 DWC_HMAC_SHA256 + ++#endif /* DWC_CRYPTOLIB */ ++ + + /** @name Memory Allocation + * +@@ -384,7 +568,7 @@ + * of the memory debugging routines need to be implemented. The allocation + * routines all ZERO the contents of the memory. + * +- * Defining DEBUG_MEMORY turns on memory debugging and statistic gathering. ++ * Defining DWC_DEBUG_MEMORY turns on memory debugging and statistic gathering. + * This checks for memory leaks, keeping track of alloc/free pairs. It also + * keeps track of how much memory the driver is using at any given time. */ + +@@ -394,9 +578,38 @@ + + #define DWC_INVALID_DMA_ADDR 0x0 + +-typedef uint32_t dwc_dma_t; ++#ifdef DWC_LINUX ++/** Type for a DMA address */ ++typedef dma_addr_t dwc_dma_t; ++#endif ++ ++#if defined(DWC_FREEBSD) || defined(DWC_NETBSD) ++typedef bus_addr_t dwc_dma_t; ++#endif ++ ++#ifdef DWC_FREEBSD ++typedef struct dwc_dmactx { ++ struct device *dev; ++ bus_dma_tag_t dma_tag; ++ bus_dmamap_t dma_map; ++ bus_addr_t dma_paddr; ++ void *dma_vaddr; ++} dwc_dmactx_t; ++#endif ++ ++#ifdef DWC_NETBSD ++typedef struct dwc_dmactx { ++ struct device *dev; ++ bus_dma_tag_t dma_tag; ++ bus_dmamap_t dma_map; ++ bus_dma_segment_t segs[1]; ++ int nsegs; ++ bus_addr_t dma_paddr; ++ void *dma_vaddr; ++} dwc_dmactx_t; ++#endif + +-/** @todo these functions will be added in the future */ ++/* @todo these functions will be added in the future */ + #if 0 + /** + * Creates a DMA pool from which you can allocate DMA buffers. Buffers +@@ -416,79 +629,121 @@ + * when you are done with it. + */ + extern dwc_pool_t *DWC_DMA_POOL_CREATE(uint32_t size, uint32_t align, uint32_t boundary); ++ + /** + * Destroy a DMA pool. All buffers allocated from that pool must be freed first. + */ + extern void DWC_DMA_POOL_DESTROY(dwc_pool_t *pool); ++ + /** + * Allocate a buffer from the specified DMA pool and zeros its contents. + */ + extern void *DWC_DMA_POOL_ALLOC(dwc_pool_t *pool, uint64_t *dma_addr); ++ + /** + * Free a previously allocated buffer from the DMA pool. + */ + extern void DWC_DMA_POOL_FREE(dwc_pool_t *pool, void *vaddr, void *daddr); + #endif + +- + /** Allocates a DMA capable buffer and zeroes its contents. */ +-extern void *__DWC_DMA_ALLOC(uint32_t size, dwc_dma_t *dma_addr); ++extern void *__DWC_DMA_ALLOC(void *dma_ctx, uint32_t size, dwc_dma_t *dma_addr); + + /** Allocates a DMA capable buffer and zeroes its contents in atomic contest */ +-extern void *__DWC_DMA_ALLOC_ATOMIC(uint32_t size, dwc_dma_t *dma_addr); ++extern void *__DWC_DMA_ALLOC_ATOMIC(void *dma_ctx, uint32_t size, dwc_dma_t *dma_addr); + +-/** Frees a previosly allocated buffer. */ +-extern void __DWC_DMA_FREE(uint32_t size, void *virt_addr, dwc_dma_t dma_addr); ++/** Frees a previously allocated buffer. */ ++extern void __DWC_DMA_FREE(void *dma_ctx, uint32_t size, void *virt_addr, dwc_dma_t dma_addr); + + /** Allocates a block of memory and zeroes its contents. */ +-extern void *__DWC_ALLOC(uint32_t size); ++extern void *__DWC_ALLOC(void *mem_ctx, uint32_t size); + + /** Allocates a block of memory and zeroes its contents, in an atomic manner + * which can be used inside interrupt context. The size should be sufficiently + * small, a few KB at most, such that failures are not likely to occur. Can just call + * __DWC_ALLOC if it is atomic. */ +-extern void *__DWC_ALLOC_ATOMIC(uint32_t size); ++extern void *__DWC_ALLOC_ATOMIC(void *mem_ctx, uint32_t size); + + /** Frees a previously allocated buffer. */ +-extern void __DWC_FREE(void *addr); ++extern void __DWC_FREE(void *mem_ctx, void *addr); + +-#ifndef DEBUG_MEMORY ++#ifndef DWC_DEBUG_MEMORY + +-#define DWC_ALLOC(_size_) __DWC_ALLOC(_size_) +-#define DWC_ALLOC_ATOMIC(_size_) __DWC_ALLOC_ATOMIC(_size_) +-#define DWC_FREE(_addr_) __DWC_FREE(_addr_) +-#define DWC_DMA_ALLOC(_size_,_dma_) __DWC_DMA_ALLOC(_size_,_dma_) +-#define DWC_DMA_ALLOC_ATOMIC(_size_,_dma_) __DWC_DMA_ALLOC_ATOMIC(_size_,_dma_) +-#define DWC_DMA_FREE(_size_,_virt_,_dma_) __DWC_DMA_FREE(_size_,_virt_,_dma_) ++#define DWC_ALLOC(_size_) __DWC_ALLOC(NULL, _size_) ++#define DWC_ALLOC_ATOMIC(_size_) __DWC_ALLOC_ATOMIC(NULL, _size_) ++#define DWC_FREE(_addr_) __DWC_FREE(NULL, _addr_) ++ ++# ifdef DWC_LINUX ++#define DWC_DMA_ALLOC(_size_,_dma_) __DWC_DMA_ALLOC(NULL, _size_, _dma_) ++#define DWC_DMA_ALLOC_ATOMIC(_size_,_dma_) __DWC_DMA_ALLOC_ATOMIC(NULL, _size_,_dma_) ++#define DWC_DMA_FREE(_size_,_virt_,_dma_) __DWC_DMA_FREE(NULL, _size_, _virt_, _dma_) ++# endif ++ ++# if defined(DWC_FREEBSD) || defined(DWC_NETBSD) ++#define DWC_DMA_ALLOC __DWC_DMA_ALLOC ++#define DWC_DMA_FREE __DWC_DMA_FREE ++# endif ++extern void *dwc_dma_alloc_atomic_debug(uint32_t size, dwc_dma_t *dma_addr, char const *func, int line); + +-#else ++#else /* DWC_DEBUG_MEMORY */ + +-extern void *dwc_alloc_debug(uint32_t size, char const *func, int line); +-extern void *dwc_alloc_atomic_debug(uint32_t size, char const *func, int line); +-extern void dwc_free_debug(void *addr, char const *func, int line); +-extern void *dwc_dma_alloc_debug(uint32_t size, dwc_dma_t *dma_addr, char const *func, int line); +-extern void *dwc_dma_alloc_atomic_debug(uint32_t size, dwc_dma_t *dma_addr, char const *func, int line); +-extern void dwc_dma_free_debug(uint32_t size, void *virt_addr, dwc_dma_t dma_addr, char const *func, int line); ++extern void *dwc_alloc_debug(void *mem_ctx, uint32_t size, char const *func, int line); ++extern void *dwc_alloc_atomic_debug(void *mem_ctx, uint32_t size, char const *func, int line); ++extern void dwc_free_debug(void *mem_ctx, void *addr, char const *func, int line); ++extern void *dwc_dma_alloc_debug(void *dma_ctx, uint32_t size, dwc_dma_t *dma_addr, ++ char const *func, int line); ++extern void *dwc_dma_alloc_atomic_debug(void *dma_ctx, uint32_t size, dwc_dma_t *dma_addr, ++ char const *func, int line); ++extern void dwc_dma_free_debug(void *dma_ctx, uint32_t size, void *virt_addr, ++ dwc_dma_t dma_addr, char const *func, int line); + +-extern void dwc_memory_debug_start(void); ++extern int dwc_memory_debug_start(void *mem_ctx); + extern void dwc_memory_debug_stop(void); + extern void dwc_memory_debug_report(void); + +-#define DWC_ALLOC(_size_) (dwc_alloc_debug(_size_, __func__, __LINE__)) +-#define DWC_ALLOC_ATOMIC(_size_) (dwc_alloc_atomic_debug(_size_, __func__, __LINE__)) +-#define DWC_FREE(_addr_) (dwc_free_debug(_addr_, __func__, __LINE__)) +-#define DWC_DMA_ALLOC(_size_,_dma_) dwc_dma_alloc_debug(_size_, _dma_, __func__, __LINE__) +-#define DWC_DMA_ALLOC_ATOMIC(_size_,_dma_) dwc_dma_alloc_atomic_debug(_size_, _dma_, __func__, __LINE__) +-#define DWC_DMA_FREE(_size_,_virt_,_dma_) dwc_dma_free_debug(_size_, _virt_, _dma_, __func__, __LINE__) +- +-#endif /* DEBUG_MEMORY */ +- +-#define dwc_alloc DWC_ALLOC +-#define dwc_alloc_atomic DWC_ALLOC_ATOMIC +-#define dwc_free DWC_FREE ++#define DWC_ALLOC(_size_) dwc_alloc_debug(NULL, _size_, __func__, __LINE__) ++#define DWC_ALLOC_ATOMIC(_size_) dwc_alloc_atomic_debug(NULL, _size_, \ ++ __func__, __LINE__) ++#define DWC_FREE(_addr_) dwc_free_debug(NULL, _addr_, __func__, __LINE__) ++ ++# ifdef DWC_LINUX ++#define DWC_DMA_ALLOC(_size_,_dma_) dwc_dma_alloc_debug(NULL, _size_, \ ++ _dma_, __func__, __LINE__) ++#define DWC_DMA_ALLOC_ATOMIC(_size_,_dma_) dwc_dma_alloc_atomic_debug(NULL, _size_, \ ++ _dma_, __func__, __LINE__) ++#define DWC_DMA_FREE(_size_,_virt_,_dma_) dwc_dma_free_debug(NULL, _size_, \ ++ _virt_, _dma_, __func__, __LINE__) ++# endif ++ ++# if defined(DWC_FREEBSD) || defined(DWC_NETBSD) ++#define DWC_DMA_ALLOC(_ctx_,_size_,_dma_) dwc_dma_alloc_debug(_ctx_, _size_, \ ++ _dma_, __func__, __LINE__) ++#define DWC_DMA_FREE(_ctx_,_size_,_virt_,_dma_) dwc_dma_free_debug(_ctx_, _size_, \ ++ _virt_, _dma_, __func__, __LINE__) ++# endif ++ ++#endif /* DWC_DEBUG_MEMORY */ ++ ++#define dwc_alloc(_ctx_,_size_) DWC_ALLOC(_size_) ++#define dwc_alloc_atomic(_ctx_,_size_) DWC_ALLOC_ATOMIC(_size_) ++#define dwc_free(_ctx_,_addr_) DWC_FREE(_addr_) ++ ++#ifdef DWC_LINUX ++/* Linux doesn't need any extra parameters for DMA buffer allocation, so we ++ * just throw away the DMA context parameter. ++ */ ++#define dwc_dma_alloc(_ctx_,_size_,_dma_) DWC_DMA_ALLOC(_size_, _dma_) ++#define dwc_dma_alloc_atomic(_ctx_,_size_,_dma_) DWC_DMA_ALLOC_ATOMIC(_size_, _dma_) ++#define dwc_dma_free(_ctx_,_size_,_virt_,_dma_) DWC_DMA_FREE(_size_, _virt_, _dma_) ++#endif ++ ++#if defined(DWC_FREEBSD) || defined(DWC_NETBSD) ++/** BSD needs several extra parameters for DMA buffer allocation, so we pass ++ * them in using the DMA context parameter. ++ */ + #define dwc_dma_alloc DWC_DMA_ALLOC +-#define dwc_dma_alloc_atomic DWC_DMA_ALLOC_ATOMIC + #define dwc_dma_free DWC_DMA_FREE ++#endif + + + /** @name Memory and String Processing */ +@@ -496,24 +751,31 @@ + /** memset() clone */ + extern void *DWC_MEMSET(void *dest, uint8_t byte, uint32_t size); + #define dwc_memset DWC_MEMSET ++ + /** memcpy() clone */ + extern void *DWC_MEMCPY(void *dest, void const *src, uint32_t size); + #define dwc_memcpy DWC_MEMCPY ++ + /** memmove() clone */ + extern void *DWC_MEMMOVE(void *dest, void *src, uint32_t size); + #define dwc_memmove DWC_MEMMOVE ++ + /** memcmp() clone */ + extern int DWC_MEMCMP(void *m1, void *m2, uint32_t size); + #define dwc_memcmp DWC_MEMCMP ++ + /** strcmp() clone */ + extern int DWC_STRCMP(void *s1, void *s2); + #define dwc_strcmp DWC_STRCMP ++ + /** strncmp() clone */ + extern int DWC_STRNCMP(void *s1, void *s2, uint32_t size); + #define dwc_strncmp DWC_STRNCMP ++ + /** strlen() clone, for NULL terminated ASCII strings */ + extern int DWC_STRLEN(char const *str); + #define dwc_strlen DWC_STRLEN ++ + /** strcpy() clone, for NULL terminated ASCII strings */ + extern char *DWC_STRCPY(char *to, const char *from); + #define dwc_strcpy DWC_STRCPY +@@ -523,7 +785,7 @@ + * calling a predefined strdup. Otherwise the memory allocated by this routine + * will not be seen by the debugging routines. */ + extern char *DWC_STRDUP(char const *str); +-#define dwc_strdup DWC_STRDUP ++#define dwc_strdup(_ctx_,_str_) DWC_STRDUP(_str_) + + /** NOT an atoi() clone. Read the description carefully. Returns an integer + * converted from the string str in base 10 unless the string begins with a "0x" +@@ -535,14 +797,19 @@ + * conversion are undefined. On sucess it returns 0. Overflow conditions are + * undefined. An example implementation using atoi() can be referenced from the + * Linux implementation. */ +-extern int DWC_ATOI(char *str, int32_t *value); ++extern int DWC_ATOI(const char *str, int32_t *value); + #define dwc_atoi DWC_ATOI ++ + /** Same as above but for unsigned. */ +-extern int DWC_ATOUI(char *str, uint32_t *value); ++extern int DWC_ATOUI(const char *str, uint32_t *value); + #define dwc_atoui DWC_ATOUI ++ ++#ifdef DWC_UTFLIB + /** This routine returns a UTF16LE unicode encoded string from a UTF8 string. */ + extern int DWC_UTF8_TO_UTF16LE(uint8_t const *utf8string, uint16_t *utf16string, unsigned len); + #define dwc_utf8_to_utf16le DWC_UTF8_TO_UTF16LE ++#endif ++ + + /** @name Wait queues + * +@@ -552,6 +819,8 @@ + * unblocked and the condition will be check again. Waitqs should be triggered + * every time a condition can potentially change.*/ + struct dwc_waitq; ++ ++/** Type for a waitq */ + typedef struct dwc_waitq dwc_waitq_t; + + /** The type of waitq condition callback function. This is called every time +@@ -560,7 +829,8 @@ + + /** Allocate a waitq */ + extern dwc_waitq_t *DWC_WAITQ_ALLOC(void); +-#define dwc_waitq_alloc DWC_WAITQ_ALLOC ++#define dwc_waitq_alloc(_ctx_) DWC_WAITQ_ALLOC() ++ + /** Free a waitq */ + extern void DWC_WAITQ_FREE(dwc_waitq_t *wq); + #define dwc_waitq_free DWC_WAITQ_FREE +@@ -568,23 +838,28 @@ + /** Check the condition and if it is false, block on the waitq. When unblocked, check the + * condition again. The function returns when the condition becomes true. The return value + * is 0 on condition true, DWC_WAITQ_ABORTED on abort or killed, or DWC_WAITQ_UNKNOWN on error. */ +-extern int32_t DWC_WAITQ_WAIT(dwc_waitq_t *wq, dwc_waitq_condition_t condition, void *data); +-#define dwc_waitq_wait DWC_WAITQ_WAIT; ++extern int32_t DWC_WAITQ_WAIT(dwc_waitq_t *wq, dwc_waitq_condition_t cond, void *data); ++#define dwc_waitq_wait DWC_WAITQ_WAIT ++ + /** Check the condition and if it is false, block on the waitq. When unblocked, + * check the condition again. The function returns when the condition become + * true or the timeout has passed. The return value is 0 on condition true or + * DWC_TIMED_OUT on timeout, or DWC_WAITQ_ABORTED, or DWC_WAITQ_UNKNOWN on + * error. */ +-extern int32_t DWC_WAITQ_WAIT_TIMEOUT(dwc_waitq_t *wq, dwc_waitq_condition_t condition, void *data, int32_t msecs); ++extern int32_t DWC_WAITQ_WAIT_TIMEOUT(dwc_waitq_t *wq, dwc_waitq_condition_t cond, ++ void *data, int32_t msecs); + #define dwc_waitq_wait_timeout DWC_WAITQ_WAIT_TIMEOUT ++ + /** Trigger a waitq, unblocking all processes. This should be called whenever a condition + * has potentially changed. */ + extern void DWC_WAITQ_TRIGGER(dwc_waitq_t *wq); + #define dwc_waitq_trigger DWC_WAITQ_TRIGGER ++ + /** Unblock all processes waiting on the waitq with an ABORTED result. */ + extern void DWC_WAITQ_ABORT(dwc_waitq_t *wq); + #define dwc_waitq_abort DWC_WAITQ_ABORT + ++ + /** @name Threads + * + * A thread must be explicitly stopped. It must check DWC_THREAD_SHOULD_STOP +@@ -593,6 +868,8 @@ + */ + + struct dwc_thread; ++ ++/** Type for a thread */ + typedef struct dwc_thread dwc_thread_t; + + /** The thread function */ +@@ -600,21 +877,42 @@ + + /** Create a thread and start it running the thread_function. Returns a handle + * to the thread */ +-extern dwc_thread_t *DWC_THREAD_RUN(dwc_thread_function_t thread_function, char *name, void *data); +-#define dwc_thread_run DWC_THREAD_RUN ++extern dwc_thread_t *DWC_THREAD_RUN(dwc_thread_function_t func, char *name, void *data); ++#define dwc_thread_run(_ctx_,_func_,_name_,_data_) DWC_THREAD_RUN(_func_, _name_, _data_) ++ + /** Stops a thread. Return the value returned by the thread. Or will return + * DWC_ABORT if the thread never started. */ + extern int DWC_THREAD_STOP(dwc_thread_t *thread); + #define dwc_thread_stop DWC_THREAD_STOP ++ + /** Signifies to the thread that it must stop. */ ++#ifdef DWC_LINUX ++/* Linux doesn't need any parameters for kthread_should_stop() */ + extern dwc_bool_t DWC_THREAD_SHOULD_STOP(void); ++#define dwc_thread_should_stop(_thrd_) DWC_THREAD_SHOULD_STOP() ++ ++/* No thread_exit function in Linux */ ++#define dwc_thread_exit(_thrd_) ++#endif ++ ++#if defined(DWC_FREEBSD) || defined(DWC_NETBSD) ++/** BSD needs the thread pointer for kthread_suspend_check() */ ++extern dwc_bool_t DWC_THREAD_SHOULD_STOP(dwc_thread_t *thread); + #define dwc_thread_should_stop DWC_THREAD_SHOULD_STOP + ++/** The thread must call this to exit. */ ++extern void DWC_THREAD_EXIT(dwc_thread_t *thread); ++#define dwc_thread_exit DWC_THREAD_EXIT ++#endif ++ ++ + /** @name Work queues + * + * Workqs are used to queue a callback function to be called at some later time, + * in another thread. */ + struct dwc_workq; ++ ++/** Type for a workq */ + typedef struct dwc_workq dwc_workq_t; + + /** The type of the callback function to be called. */ +@@ -622,33 +920,38 @@ + + /** Allocate a workq */ + extern dwc_workq_t *DWC_WORKQ_ALLOC(char *name); +-#define dwc_workq_alloc DWC_WORKQ_ALLOC ++#define dwc_workq_alloc(_ctx_,_name_) DWC_WORKQ_ALLOC(_name_) ++ + /** Free a workq. All work must be completed before being freed. */ + extern void DWC_WORKQ_FREE(dwc_workq_t *workq); + #define dwc_workq_free DWC_WORKQ_FREE ++ + /** Schedule a callback on the workq, passing in data. The function will be + * scheduled at some later time. */ +-extern void DWC_WORKQ_SCHEDULE(dwc_workq_t *workq, dwc_work_callback_t work_cb, void *data, char *format, ...) ++extern void DWC_WORKQ_SCHEDULE(dwc_workq_t *workq, dwc_work_callback_t cb, ++ void *data, char *format, ...) + #ifdef __GNUC__ + __attribute__ ((format(printf, 4, 5))); + #else +- ; ++ ; + #endif + #define dwc_workq_schedule DWC_WORKQ_SCHEDULE + +-/** Schedule a callback on the workq, that will be called until at least ++/** Schedule a callback on the workq, that will be called until at least + * given number miliseconds have passed. */ +-extern void DWC_WORKQ_SCHEDULE_DELAYED(dwc_workq_t *workq, dwc_work_callback_t work_cb, void *data, uint32_t time, char *format, ...) ++extern void DWC_WORKQ_SCHEDULE_DELAYED(dwc_workq_t *workq, dwc_work_callback_t cb, ++ void *data, uint32_t time, char *format, ...) + #ifdef __GNUC__ + __attribute__ ((format(printf, 5, 6))); + #else +- ; ++ ; + #endif + #define dwc_workq_schedule_delayed DWC_WORKQ_SCHEDULE_DELAYED + + /** The number of processes in the workq */ + extern int DWC_WORKQ_PENDING(dwc_workq_t *workq); + #define dwc_workq_pending DWC_WORKQ_PENDING ++ + /** Blocks until all the work in the workq is complete or timed out. Returns < + * 0 on timeout. */ + extern int DWC_WORKQ_WAIT_WORK_DONE(dwc_workq_t *workq, int timeout); +@@ -659,14 +962,22 @@ + * + */ + struct dwc_tasklet; ++ ++/** Type for a tasklet */ + typedef struct dwc_tasklet dwc_tasklet_t; + ++/** The type of the callback function to be called */ + typedef void (*dwc_tasklet_callback_t)(void *data); + +-extern dwc_tasklet_t *DWC_TASK_ALLOC(dwc_tasklet_callback_t cb, void *data); +-#define dwc_task_alloc DWC_TASK_ALLOC +-extern void DWC_TASK_FREE(dwc_tasklet_t *t); ++/** Allocates a tasklet */ ++extern dwc_tasklet_t *DWC_TASK_ALLOC(char *name, dwc_tasklet_callback_t cb, void *data); ++#define dwc_task_alloc(_ctx_,_name_,_cb_,_data_) DWC_TASK_ALLOC(_name_, _cb_, _data_) ++ ++/** Frees a tasklet */ ++extern void DWC_TASK_FREE(dwc_tasklet_t *task); + #define dwc_task_free DWC_TASK_FREE ++ ++/** Schedules a tasklet to run */ + extern void DWC_TASK_SCHEDULE(dwc_tasklet_t *task); + #define dwc_task_schedule DWC_TASK_SCHEDULE + +@@ -676,12 +987,18 @@ + * Callbacks must be small and atomic. + */ + struct dwc_timer; ++ ++/** Type for a timer */ + typedef struct dwc_timer dwc_timer_t; + ++/** The type of the callback function to be called */ + typedef void (*dwc_timer_callback_t)(void *data); + ++/** Allocates a timer */ + extern dwc_timer_t *DWC_TIMER_ALLOC(char *name, dwc_timer_callback_t cb, void *data); +-#define dwc_timer_alloc DWC_TIMER_ALLOC ++#define dwc_timer_alloc(_ctx_,_name_,_cb_,_data_) DWC_TIMER_ALLOC(_name_,_cb_,_data_) ++ ++/** Frees a timer */ + extern void DWC_TIMER_FREE(dwc_timer_t *timer); + #define dwc_timer_free DWC_TIMER_FREE + +@@ -698,7 +1015,6 @@ + #define dwc_timer_cancel DWC_TIMER_CANCEL + + +- + /** @name Spinlocks + * + * These locks are used when the work between the lock/unlock is atomic and +@@ -711,25 +1027,30 @@ + * change, and so you never have to lock between processes. */ + + struct dwc_spinlock; ++ ++/** Type for a spinlock */ + typedef struct dwc_spinlock dwc_spinlock_t; + ++/** Type for the 'flags' argument to spinlock funtions */ ++typedef unsigned long dwc_irqflags_t; ++ + /** Returns an initialized lock variable. This function should allocate and + * initialize the OS-specific data structure used for locking. This data + * structure is to be used for the DWC_LOCK and DWC_UNLOCK functions and should + * be freed by the DWC_FREE_LOCK when it is no longer used. */ + extern dwc_spinlock_t *DWC_SPINLOCK_ALLOC(void); +-#define dwc_spinlock_alloc DWC_SPINLOCK_ALLOC ++#define dwc_spinlock_alloc(_ctx_) DWC_SPINLOCK_ALLOC() + + /** Frees an initialized lock variable. */ + extern void DWC_SPINLOCK_FREE(dwc_spinlock_t *lock); +-#define dwc_spinlock_free DWC_SPINLOCK_FREE ++#define dwc_spinlock_free(_ctx_,_lock_) DWC_SPINLOCK_FREE(_lock_) + + /** Disables interrupts and blocks until it acquires the lock. + * + * @param lock Pointer to the spinlock. + * @param flags Unsigned long for irq flags storage. + */ +-extern void DWC_SPINLOCK_IRQSAVE(dwc_spinlock_t *lock, uint64_t *flags); ++extern void DWC_SPINLOCK_IRQSAVE(dwc_spinlock_t *lock, dwc_irqflags_t *flags); + #define dwc_spinlock_irqsave DWC_SPINLOCK_IRQSAVE + + /** Re-enables the interrupt and releases the lock. +@@ -738,7 +1059,7 @@ + * @param flags Unsigned long for irq flags storage. Must be the same as was + * passed into DWC_LOCK. + */ +-extern void DWC_SPINUNLOCK_IRQRESTORE(dwc_spinlock_t *lock, uint64_t flags); ++extern void DWC_SPINUNLOCK_IRQRESTORE(dwc_spinlock_t *lock, dwc_irqflags_t flags); + #define dwc_spinunlock_irqrestore DWC_SPINUNLOCK_IRQRESTORE + + /** Blocks until it acquires the lock. +@@ -755,6 +1076,7 @@ + extern void DWC_SPINUNLOCK(dwc_spinlock_t *lock); + #define dwc_spinunlock DWC_SPINUNLOCK + ++ + /** @name Mutexes + * + * Unlike spinlocks Mutexes lock only between processes and the work between the +@@ -762,43 +1084,49 @@ + */ + + struct dwc_mutex; +-typedef struct dwc_mutex dwc_mutex_t; + ++/** Type for a mutex */ ++typedef struct dwc_mutex dwc_mutex_t; + + /* For Linux Mutex Debugging make it inline because the debugging routines use + * the symbol to determine recursive locking. This makes it falsely think + * recursive locking occurs. */ +-#if (defined(DWC_LINUX) && defined(CONFIG_DEBUG_MUTEXES)) ++#if defined(DWC_LINUX) && defined(CONFIG_DEBUG_MUTEXES) + #define DWC_MUTEX_ALLOC_LINUX_DEBUG(__mutexp) ({ \ + __mutexp = (dwc_mutex_t *)DWC_ALLOC(sizeof(struct mutex)); \ + mutex_init((struct mutex *)__mutexp); \ + }) + #endif ++ ++/** Allocate a mutex */ + extern dwc_mutex_t *DWC_MUTEX_ALLOC(void); +-#define dwc_mutex_alloc DWC_MUTEX_ALLOC ++#define dwc_mutex_alloc(_ctx_) DWC_MUTEX_ALLOC() + + /* For memory leak debugging when using Linux Mutex Debugging */ +-#if (defined(DWC_LINUX) && defined(CONFIG_DEBUG_MUTEXES)) ++#if defined(DWC_LINUX) && defined(CONFIG_DEBUG_MUTEXES) + #define DWC_MUTEX_FREE(__mutexp) do { \ + mutex_destroy((struct mutex *)__mutexp); \ + DWC_FREE(__mutexp); \ + } while(0) + #else ++/** Free a mutex */ + extern void DWC_MUTEX_FREE(dwc_mutex_t *mutex); +-#define dwc_mutex_free DWC_MUTEX_FREE ++#define dwc_mutex_free(_ctx_,_mutex_) DWC_MUTEX_FREE(_mutex_) + #endif + ++/** Lock a mutex */ + extern void DWC_MUTEX_LOCK(dwc_mutex_t *mutex); + #define dwc_mutex_lock DWC_MUTEX_LOCK ++ + /** Non-blocking lock returns 1 on successful lock. */ + extern int DWC_MUTEX_TRYLOCK(dwc_mutex_t *mutex); + #define dwc_mutex_trylock DWC_MUTEX_TRYLOCK ++ ++/** Unlock a mutex */ + extern void DWC_MUTEX_UNLOCK(dwc_mutex_t *mutex); + #define dwc_mutex_unlock DWC_MUTEX_UNLOCK + + +- +- + /** @name Time */ + + /** Microsecond delay. +@@ -823,15 +1151,16 @@ + extern void DWC_MSLEEP(uint32_t msecs); + #define dwc_msleep DWC_MSLEEP + ++/** ++ * Returns number of milliseconds since boot. ++ */ + extern uint32_t DWC_TIME(void); + #define dwc_time DWC_TIME + +-#endif // _DWC_OS_H_ + + + +- +-/** @mainpage DWC Portability and Common Library ++/* @mainpage DWC Portability and Common Library + * + * This is the documentation for the DWC Portability and Common Library. + * +@@ -923,3 +1252,9 @@ + * threading should be able to be implemented with the defined behavior. + * + */ ++ ++#ifdef __cplusplus ++} ++#endif ++ ++#endif /* _DWC_OS_H_ */ +Index: linux-3.2.46/drivers/usb/host/dwc_common_port/usb.h +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_common_port/usb.h 2013-07-26 19:31:20.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_common_port/usb.h 2013-07-26 19:34:39.000000000 +0000 +@@ -41,7 +41,9 @@ + #ifndef _USB_H_ + #define _USB_H_ + +-#include "dwc_os.h" ++#ifdef __cplusplus ++extern "C" { ++#endif + + /* + * The USB records contain some unaligned little-endian word +@@ -54,6 +56,9 @@ + typedef u_int8_t uDWord[4]; + + #define USETW2(w,h,l) ((w)[0] = (u_int8_t)(l), (w)[1] = (u_int8_t)(h)) ++#define UCONSTW(x) { (x) & 0xff, ((x) >> 8) & 0xff } ++#define UCONSTDW(x) { (x) & 0xff, ((x) >> 8) & 0xff, \ ++ ((x) >> 16) & 0xff, ((x) >> 24) & 0xff } + + #if 1 + #define UGETW(w) ((w)[0] | ((w)[1] << 8)) +@@ -74,6 +79,21 @@ + #define USETDW(w,v) (*(u_int32_t *)(w) = (v)) + #endif + ++/* ++ * Macros for accessing UAS IU fields, which are big-endian ++ */ ++#define IUSETW2(w,h,l) ((w)[0] = (u_int8_t)(h), (w)[1] = (u_int8_t)(l)) ++#define IUCONSTW(x) { ((x) >> 8) & 0xff, (x) & 0xff } ++#define IUCONSTDW(x) { ((x) >> 24) & 0xff, ((x) >> 16) & 0xff, \ ++ ((x) >> 8) & 0xff, (x) & 0xff } ++#define IUGETW(w) (((w)[0] << 8) | (w)[1]) ++#define IUSETW(w,v) ((w)[0] = (u_int8_t)((v) >> 8), (w)[1] = (u_int8_t)(v)) ++#define IUGETDW(w) (((w)[0] << 24) | ((w)[1] << 16) | ((w)[2] << 8) | (w)[3]) ++#define IUSETDW(w,v) ((w)[0] = (u_int8_t)((v) >> 24), \ ++ (w)[1] = (u_int8_t)((v) >> 16), \ ++ (w)[2] = (u_int8_t)((v) >> 8), \ ++ (w)[3] = (u_int8_t)(v)) ++ + #define UPACKED __attribute__((__packed__)) + + typedef struct { +@@ -140,6 +160,7 @@ + #define UDESC_STRING 0x03 + #define UDESC_INTERFACE 0x04 + #define UDESC_ENDPOINT 0x05 ++#define UDESC_SS_USB_COMPANION 0x30 + #define UDESC_DEVICE_QUALIFIER 0x06 + #define UDESC_OTHER_SPEED_CONFIGURATION 0x07 + #define UDESC_INTERFACE_POWER 0x08 +@@ -157,6 +178,8 @@ + #define WUDESC_BOS 0x0f + #define WUDESC_DEVICE_CAPABILITY 0x10 + #define WUDESC_WIRELESS_ENDPOINT_COMPANION 0x11 ++#define UDESC_BOS 0x0f ++#define UDESC_DEVICE_CAPABILITY 0x10 + #define UDESC_CS_DEVICE 0x21 /* class specific */ + #define UDESC_CS_CONFIG 0x22 + #define UDESC_CS_STRING 0x23 +@@ -177,11 +200,11 @@ + #define WUR_SET_SECURITY_DATA 0x12 + #define WUR_GET_SECURITY_DATA 0x13 + #define WUR_SET_WUSB_DATA 0x14 +-#define WUDATA_DRPIE_INFO 0x01 +-#define WUDATA_TRANSMIT_DATA 0x02 +-#define WUDATA_TRANSMIT_PARAMS 0x03 +-#define WUDATA_RECEIVE_PARAMS 0x04 +-#define WUDATA_TRANSMIT_POWER 0x05 ++#define WUDATA_DRPIE_INFO 0x01 ++#define WUDATA_TRANSMIT_DATA 0x02 ++#define WUDATA_TRANSMIT_PARAMS 0x03 ++#define WUDATA_RECEIVE_PARAMS 0x04 ++#define WUDATA_TRANSMIT_POWER 0x05 + #define WUR_LOOPBACK_DATA_WRITE 0x15 + #define WUR_LOOPBACK_DATA_READ 0x16 + #define WUR_SET_INTERFACE_DS 0x17 +@@ -193,11 +216,15 @@ + #define UF_DEVICE_B_HNP_ENABLE 3 + #define UF_DEVICE_A_HNP_SUPPORT 4 + #define UF_DEVICE_A_ALT_HNP_SUPPORT 5 +-#define WUF_WUSB 3 +-#define WUF_TX_DRPIE 0x0 +-#define WUF_DEV_XMIT_PACKET 0x1 +-#define WUF_COUNT_PACKETS 0x2 +-#define WUF_CAPTURE_PACKETS 0x3 ++#define WUF_WUSB 3 ++#define WUF_TX_DRPIE 0x0 ++#define WUF_DEV_XMIT_PACKET 0x1 ++#define WUF_COUNT_PACKETS 0x2 ++#define WUF_CAPTURE_PACKETS 0x3 ++#define UF_FUNCTION_SUSPEND 0 ++#define UF_U1_ENABLE 48 ++#define UF_U2_ENABLE 49 ++#define UF_LTM_ENABLE 50 + + /* Class requests from the USB 2.0 hub spec, table 11-15 */ + #define UCR_CLEAR_HUB_FEATURE (0x2000 | UR_CLEAR_FEATURE) +@@ -209,6 +236,10 @@ + #define UCR_SET_PORT_FEATURE (0x2300 | UR_SET_FEATURE) + #define UCR_SET_AND_TEST_PORT_FEATURE (0xa300 | UR_SET_AND_TEST_FEATURE) + ++#ifdef _MSC_VER ++#include ++#endif ++ + typedef struct { + uByte bLength; + uByte bDescriptorType; +@@ -218,6 +249,11 @@ + typedef struct { + uByte bLength; + uByte bDescriptorType; ++} UPACKED usb_descriptor_header_t; ++ ++typedef struct { ++ uByte bLength; ++ uByte bDescriptorType; + uWord bcdUSB; + #define UD_USB_2_0 0x0200 + #define UD_IS_USB2(d) (UGETW((d)->bcdUSB) >= UD_USB_2_0) +@@ -243,6 +279,10 @@ + uByte bNumInterface; + uByte bConfigurationValue; + uByte iConfiguration; ++#define UC_ATT_ONE (1 << 7) /* must be set */ ++#define UC_ATT_SELFPOWER (1 << 6) /* self powered */ ++#define UC_ATT_WAKEUP (1 << 5) /* can wakeup */ ++#define UC_ATT_BATTERY (1 << 4) /* battery powered */ + uByte bmAttributes; + #define UC_BUS_POWERED 0x80 + #define UC_SELF_POWERED 0x40 +@@ -292,6 +332,19 @@ + } UPACKED usb_endpoint_descriptor_t; + #define USB_ENDPOINT_DESCRIPTOR_SIZE 7 + ++typedef struct ss_endpoint_companion_descriptor { ++ uByte bLength; ++ uByte bDescriptorType; ++ uByte bMaxBurst; ++#define USSE_GET_MAX_STREAMS(a) ((a) & 0x1f) ++#define USSE_SET_MAX_STREAMS(a, b) ((a) | ((b) & 0x1f)) ++#define USSE_GET_MAX_PACKET_NUM(a) ((a) & 0x03) ++#define USSE_SET_MAX_PACKET_NUM(a, b) ((a) | ((b) & 0x03)) ++ uByte bmAttributes; ++ uWord wBytesPerInterval; ++} UPACKED ss_endpoint_companion_descriptor_t; ++#define USB_SS_ENDPOINT_COMPANION_DESCRIPTOR_SIZE 6 ++ + typedef struct { + uByte bLength; + uByte bDescriptorType; +@@ -420,6 +473,10 @@ + #define UPS_C_PORT_RESET 0x0010 + } UPACKED usb_port_status_t; + ++#ifdef _MSC_VER ++#include ++#endif ++ + /* Device class codes */ + #define UDCLASS_IN_INTERFACE 0x00 + #define UDCLASS_COMM 0x02 +@@ -443,13 +500,13 @@ + #define UISUBCLASS_MIDISTREAM 3 + + #define UICLASS_CDC 0x02 /* communication */ +-#define UISUBCLASS_DIRECT_LINE_CONTROL_MODEL 1 ++#define UISUBCLASS_DIRECT_LINE_CONTROL_MODEL 1 + #define UISUBCLASS_ABSTRACT_CONTROL_MODEL 2 +-#define UISUBCLASS_TELEPHONE_CONTROL_MODEL 3 +-#define UISUBCLASS_MULTICHANNEL_CONTROL_MODEL 4 +-#define UISUBCLASS_CAPI_CONTROLMODEL 5 +-#define UISUBCLASS_ETHERNET_NETWORKING_CONTROL_MODEL 6 +-#define UISUBCLASS_ATM_NETWORKING_CONTROL_MODEL 7 ++#define UISUBCLASS_TELEPHONE_CONTROL_MODEL 3 ++#define UISUBCLASS_MULTICHANNEL_CONTROL_MODEL 4 ++#define UISUBCLASS_CAPI_CONTROLMODEL 5 ++#define UISUBCLASS_ETHERNET_NETWORKING_CONTROL_MODEL 6 ++#define UISUBCLASS_ATM_NETWORKING_CONTROL_MODEL 7 + #define UIPROTO_CDC_AT 1 + + #define UICLASS_HID 0x03 +@@ -519,7 +576,6 @@ + + #define UICLASS_VENDOR 0xff + +- + #define USB_HUB_MAX_DEPTH 5 + + /* +@@ -558,7 +614,6 @@ + + #define USB_BUS_RESET_DELAY 100 /* ms XXX?*/ + +- + #define USB_UNCONFIG_NO 0 + #define USB_UNCONFIG_INDEX (-1) + +@@ -638,9 +693,12 @@ + u_int8_t udi_protocol; + u_int8_t udi_config; + u_int8_t udi_speed; +-#define USB_SPEED_LOW 1 +-#define USB_SPEED_FULL 2 +-#define USB_SPEED_HIGH 3 ++#define USB_SPEED_UNKNOWN 0 ++#define USB_SPEED_LOW 1 ++#define USB_SPEED_FULL 2 ++#define USB_SPEED_HIGH 3 ++#define USB_SPEED_VARIABLE 4 ++#define USB_SPEED_SUPER 5 + int udi_power; /* power consumption in mA, 0 if selfpowered */ + int udi_nports; + char udi_devnames[USB_MAX_DEVNAMES][USB_MAX_DEVNAMELEN]; +@@ -660,17 +718,14 @@ + u_long uds_requests[4]; /* indexed by transfer type UE_* */ + }; + +- +- +- + #define WUSB_MIN_IE 0x80 + #define WUSB_WCTA_IE 0x80 + #define WUSB_WCONNECTACK_IE 0x81 + #define WUSB_WHOSTINFO_IE 0x82 + #define WUHI_GET_CA(_bmAttributes_) ((_bmAttributes_) & 0x3) +-#define WUHI_CA_RECONN 0x00 +-#define WUHI_CA_LIMITED 0x01 +-#define WUHI_CA_ALL 0x03 ++#define WUHI_CA_RECONN 0x00 ++#define WUHI_CA_LIMITED 0x01 ++#define WUHI_CA_ALL 0x03 + #define WUHI_GET_MLSI(_bmAttributes_) (((_bmAttributes_) & 0x38) >> 3) + #define WUSB_WCHCHANGEANNOUNCE_IE 0x83 + #define WUSB_WDEV_DISCONNECT_IE 0x84 +@@ -701,150 +756,191 @@ + #define WUSB_DN_ALIVE 0x07 + #define WUSB_DN_MAX 0x07 + ++#ifdef _MSC_VER ++#include ++#endif + + /* WUSB Handshake Data. Used during the SET/GET HANDSHAKE requests */ + typedef struct wusb_hndshk_data { +- uint8_t bMessageNumber; +- uint8_t bStatus; +- uint8_t tTKID[3]; +- uint8_t bReserved; +- uint8_t CDID[16]; +- uint8_t Nonce[16]; +- uint8_t MIC[8]; ++ uByte bMessageNumber; ++ uByte bStatus; ++ uByte tTKID[3]; ++ uByte bReserved; ++ uByte CDID[16]; ++ uByte Nonce[16]; ++ uByte MIC[8]; + } UPACKED wusb_hndshk_data_t; + #define WUSB_HANDSHAKE_LEN_FOR_MIC 38 + + /* WUSB Connection Context */ + typedef struct wusb_conn_context { +- uint8_t CHID [16]; +- uint8_t CDID [16]; +- uint8_t CK [16]; ++ uByte CHID [16]; ++ uByte CDID [16]; ++ uByte CK [16]; + } UPACKED wusb_conn_context_t; + + /* WUSB Security Descriptor */ + typedef struct wusb_security_desc { +- uint8_t bLength; +- uint8_t bDescriptorType; +- uint16_t wTotalLength; +- uint8_t bNumEncryptionTypes; ++ uByte bLength; ++ uByte bDescriptorType; ++ uWord wTotalLength; ++ uByte bNumEncryptionTypes; + } UPACKED wusb_security_desc_t; + + /* WUSB Encryption Type Descriptor */ + typedef struct wusb_encrypt_type_desc { +- uint8_t bLength; +- uint8_t bDescriptorType; ++ uByte bLength; ++ uByte bDescriptorType; + +- uint8_t bEncryptionType; +-#define WUETD_UNSECURE 0 ++ uByte bEncryptionType; ++#define WUETD_UNSECURE 0 + #define WUETD_WIRED 1 + #define WUETD_CCM_1 2 + #define WUETD_RSA_1 3 + +- uint8_t bEncryptionValue; +- uint8_t bAuthKeyIndex; ++ uByte bEncryptionValue; ++ uByte bAuthKeyIndex; + } UPACKED wusb_encrypt_type_desc_t; + + /* WUSB Key Descriptor */ + typedef struct wusb_key_desc { +- uint8_t bLength; +- uint8_t bDescriptorType; +- uint8_t tTKID[3]; +- uint8_t bReserved; +- uint8_t KeyData[1]; /* variable length */ ++ uByte bLength; ++ uByte bDescriptorType; ++ uByte tTKID[3]; ++ uByte bReserved; ++ uByte KeyData[1]; /* variable length */ + } UPACKED wusb_key_desc_t; + + /* WUSB BOS Descriptor (Binary device Object Store) */ + typedef struct wusb_bos_desc { +- uint8_t bLength; +- uint8_t bDescriptorType; +- uint16_t wTotalLength; +- uint8_t bNumDeviceCaps; ++ uByte bLength; ++ uByte bDescriptorType; ++ uWord wTotalLength; ++ uByte bNumDeviceCaps; + } UPACKED wusb_bos_desc_t; + ++#define USB_DEVICE_CAPABILITY_20_EXTENSION 0x02 ++typedef struct usb_dev_cap_20_ext_desc { ++ uByte bLength; ++ uByte bDescriptorType; ++ uByte bDevCapabilityType; ++#define USB_20_EXT_LPM 0x02 ++ uDWord bmAttributes; ++} UPACKED usb_dev_cap_20_ext_desc_t; ++ ++#define USB_DEVICE_CAPABILITY_SS_USB 0x03 ++typedef struct usb_dev_cap_ss_usb { ++ uByte bLength; ++ uByte bDescriptorType; ++ uByte bDevCapabilityType; ++#define USB_DC_SS_USB_LTM_CAPABLE 0x02 ++ uByte bmAttributes; ++#define USB_DC_SS_USB_SPEED_SUPPORT_LOW 0x01 ++#define USB_DC_SS_USB_SPEED_SUPPORT_FULL 0x02 ++#define USB_DC_SS_USB_SPEED_SUPPORT_HIGH 0x04 ++#define USB_DC_SS_USB_SPEED_SUPPORT_SS 0x08 ++ uWord wSpeedsSupported; ++ uByte bFunctionalitySupport; ++ uByte bU1DevExitLat; ++ uWord wU2DevExitLat; ++} UPACKED usb_dev_cap_ss_usb_t; ++ ++#define USB_DEVICE_CAPABILITY_CONTAINER_ID 0x04 ++typedef struct usb_dev_cap_container_id { ++ uByte bLength; ++ uByte bDescriptorType; ++ uByte bDevCapabilityType; ++ uByte bReserved; ++ uByte containerID[16]; ++} UPACKED usb_dev_cap_container_id_t; + + /* Device Capability Type Codes */ + #define WUSB_DEVICE_CAPABILITY_WIRELESS_USB 0x01 + + /* Device Capability Descriptor */ + typedef struct wusb_dev_cap_desc { +- uint8_t bLength; +- uint8_t bDescriptorType; +- uint8_t bDevCapabilityType; +- uint8_t caps[1]; /* Variable length */ ++ uByte bLength; ++ uByte bDescriptorType; ++ uByte bDevCapabilityType; ++ uByte caps[1]; /* Variable length */ + } UPACKED wusb_dev_cap_desc_t; + + /* Device Capability Descriptor */ + typedef struct wusb_dev_cap_uwb_desc { +- uint8_t bLength; +- uint8_t bDescriptorType; +- uint8_t bDevCapabilityType; +- uint8_t bmAttributes; +- uint16_t wPHYRates; /* Bitmap */ +- uint8_t bmTFITXPowerInfo; +- uint8_t bmFFITXPowerInfo; +- uint16_t bmBandGroup; +- uint8_t bReserved; ++ uByte bLength; ++ uByte bDescriptorType; ++ uByte bDevCapabilityType; ++ uByte bmAttributes; ++ uWord wPHYRates; /* Bitmap */ ++ uByte bmTFITXPowerInfo; ++ uByte bmFFITXPowerInfo; ++ uWord bmBandGroup; ++ uByte bReserved; + } UPACKED wusb_dev_cap_uwb_desc_t; + + /* Wireless USB Endpoint Companion Descriptor */ + typedef struct wusb_endpoint_companion_desc { +- uint8_t bLength; +- uint8_t bDescriptorType; +- uint8_t bMaxBurst; +- uint8_t bMaxSequence; +- uint16_t wMaxStreamDelay; +- uint16_t wOverTheAirPacketSize; +- uint8_t bOverTheAirInterval; +- uint8_t bmCompAttributes; ++ uByte bLength; ++ uByte bDescriptorType; ++ uByte bMaxBurst; ++ uByte bMaxSequence; ++ uWord wMaxStreamDelay; ++ uWord wOverTheAirPacketSize; ++ uByte bOverTheAirInterval; ++ uByte bmCompAttributes; + } UPACKED wusb_endpoint_companion_desc_t; + +- + /* Wireless USB Numeric Association M1 Data Structure */ + typedef struct wusb_m1_data { +- uint8_t version; +- uint16_t langId; +- uint8_t deviceFriendlyNameLength; +- uint8_t sha_256_m3[32]; +- uint8_t deviceFriendlyName[256]; ++ uByte version; ++ uWord langId; ++ uByte deviceFriendlyNameLength; ++ uByte sha_256_m3[32]; ++ uByte deviceFriendlyName[256]; + } UPACKED wusb_m1_data_t; + + typedef struct wusb_m2_data { +- uint8_t version; +- uint16_t langId; +- uint8_t hostFriendlyNameLength; +- uint8_t pkh[384]; +- uint8_t hostFriendlyName[256]; ++ uByte version; ++ uWord langId; ++ uByte hostFriendlyNameLength; ++ uByte pkh[384]; ++ uByte hostFriendlyName[256]; + } UPACKED wusb_m2_data_t; + + typedef struct wusb_m3_data { +- uint8_t pkd[384]; +- uint8_t nd; ++ uByte pkd[384]; ++ uByte nd; + } UPACKED wusb_m3_data_t; + + typedef struct wusb_m4_data { +- uint32_t _attributeTypeIdAndLength_1; +- uint16_t associationTypeId; ++ uDWord _attributeTypeIdAndLength_1; ++ uWord associationTypeId; + +- uint32_t _attributeTypeIdAndLength_2; +- uint16_t associationSubTypeId; ++ uDWord _attributeTypeIdAndLength_2; ++ uWord associationSubTypeId; + +- uint32_t _attributeTypeIdAndLength_3; +- uint32_t length; ++ uDWord _attributeTypeIdAndLength_3; ++ uDWord length; + +- uint32_t _attributeTypeIdAndLength_4; +- uint32_t associationStatus; ++ uDWord _attributeTypeIdAndLength_4; ++ uDWord associationStatus; + +- uint32_t _attributeTypeIdAndLength_5; +- uint8_t chid[16]; ++ uDWord _attributeTypeIdAndLength_5; ++ uByte chid[16]; + +- uint32_t _attributeTypeIdAndLength_6; +- uint8_t cdid[16]; ++ uDWord _attributeTypeIdAndLength_6; ++ uByte cdid[16]; + +- uint32_t _attributeTypeIdAndLength_7; +- uint8_t bandGroups[2]; ++ uDWord _attributeTypeIdAndLength_7; ++ uByte bandGroups[2]; + } UPACKED wusb_m4_data_t; + ++#ifdef _MSC_VER ++#include ++#endif + +- ++#ifdef __cplusplus ++} ++#endif + + #endif /* _USB_H_ */ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/Makefile +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/Makefile 2013-07-26 19:34:36.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/Makefile 2013-07-26 19:34:39.000000000 +0000 +@@ -4,27 +4,30 @@ + + ifneq ($(KERNELRELEASE),) + ++# Use the BUS_INTERFACE variable to compile the software for either ++# PCI(PCI_INTERFACE) or LM(LM_INTERFACE) bus. + ifeq ($(BUS_INTERFACE),) +- # BUS_INTERFACE = -DLM_INTERFACE +- BUS_INTERFACE = -DPLATFORM_INTERFACE=1 ++# BUS_INTERFACE = -DPCI_INTERFACE ++# BUS_INTERFACE = -DLM_INTERFACE ++ BUS_INTERFACE = -DPLATFORM_INTERFACE + endif + +-ifeq ($(CONFIG_USB_DEBUG),y) +-CPPFLAGS += -DDEBUG +-endif ++#EXTRA_CFLAGS += -DDEBUG ++#EXTRA_CFLAGS += -DDWC_OTG_DEBUGLEV=1 # reduce common debug msgs + + # Use one of the following flags to compile the software in host-only or + # device-only mode. +-#CPPFLAGS += -DDWC_HOST_ONLY +-#CPPFLAGS += -DDWC_DEVICE_ONLY ++#EXTRA_CFLAGS += -DDWC_HOST_ONLY ++#EXTRA_CFLAGS += -DDWC_DEVICE_ONLY + +-CPPFLAGS += -Dlinux -DDWC_HS_ELECT_TST +-#CGG: CPPFLAGS += -DDWC_EN_ISOC +-CPPFLAGS += -I$(obj)/../dwc_common_port +-#CPPFLAGS += -I$(PORTLIB) +-CPPFLAGS += -DDWC_LINUX +-CPPFLAGS += $(CFI) +-CPPFLAGS += $(BUS_INTERFACE) ++EXTRA_CFLAGS += -Dlinux -DDWC_HS_ELECT_TST ++#EXTRA_CFLAGS += -DDWC_EN_ISOC ++EXTRA_CFLAGS += -I$(obj)/../dwc_common_port ++#EXTRA_CFLAGS += -I$(PORTLIB) ++EXTRA_CFLAGS += -DDWC_LINUX ++EXTRA_CFLAGS += $(CFI) ++EXTRA_CFLAGS += $(BUS_INTERFACE) ++#EXTRA_CFLAGS += -DDWC_DEV_SRPCAP + + obj-$(CONFIG_USB_DWCOTG) += dwc_otg.o + +@@ -32,6 +35,7 @@ + dwc_otg-objs += dwc_otg_cil.o dwc_otg_cil_intr.o + dwc_otg-objs += dwc_otg_pcd_linux.o dwc_otg_pcd.o dwc_otg_pcd_intr.o + dwc_otg-objs += dwc_otg_hcd.o dwc_otg_hcd_linux.o dwc_otg_hcd_intr.o dwc_otg_hcd_queue.o dwc_otg_hcd_ddma.o ++dwc_otg-objs += dwc_otg_adp.o + ifneq ($(CFI),) + dwc_otg-objs += dwc_otg_cfi.o + endif +@@ -56,12 +60,8 @@ + $(MAKE) -C$(KDIR) M=$(PWD) ARCH=$(ARCH) CROSS_COMPILE=$(CROSS_COMPILE) modules + + install: default +-ifneq ($(INSTALL_MOD_PATH),) + $(MAKE) -C$(KDIR) M=$(PORTLIB) modules_install + $(MAKE) -C$(KDIR) M=$(PWD) modules_install +-else +- @echo "No install path defined" +-endif + + portlib: + $(MAKE) -C$(KDIR) M=$(PORTLIB) ARCH=$(ARCH) CROSS_COMPILE=$(CROSS_COMPILE) modules +@@ -75,6 +75,6 @@ + + + clean: +- rm -rf *.o *.ko .*cmd *.mod.c .tmp_versions ++ rm -rf *.o *.ko .*cmd *.mod.c .tmp_versions Module.symvers + + endif +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/doxygen.cfg +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/doxygen.cfg 2013-07-26 19:31:20.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/doxygen.cfg 2013-07-26 19:34:39.000000000 +0000 +@@ -4,7 +4,7 @@ + # Project related configuration options + #--------------------------------------------------------------------------- + PROJECT_NAME = "DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver" +-PROJECT_NUMBER = v2.90a ++PROJECT_NUMBER = v2.94a + OUTPUT_DIRECTORY = ./doc/ + CREATE_SUBDIRS = NO + OUTPUT_LANGUAGE = English +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/annotated.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/annotated.html 2013-07-26 19:31:20.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/annotated.html 2013-07-26 19:34:39.000000000 +0000 +@@ -2,21 +2,9 @@ + + DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Structures + +- + +- +-
+-
+-
+-
++ ++
Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
+

DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver Data Structures

Here are the data structures with brief descriptions: + + +@@ -24,14 +12,13 @@ + + + ++ + +- + + + + +- +- ++ + + + +@@ -43,31 +30,24 @@ + + + +- ++ + + +- ++ + + + +- ++ + + + +- ++ + + + +- + + + +- +- +- +- + + + +@@ -78,8 +58,9 @@ + + + +- + ++ ++ + + + +@@ -87,7 +68,11 @@ + + + ++ ++ + ++ ++ + + + +@@ -96,25 +81,21 @@ + + + +- + + + + + + +- + + + + + + +- +- +
_ddma_align_buffer_setupDescriptor DMA Alignment Buffer setup structure
_ddma_concat_buffer_setupDescriptor DMA Concatenation Buffer setup structure
_ddma_sg_buffer_setupDescriptor DMA SG Buffer setup structure (SG buffer)
_rx_fifo_size_setupTransmit FIFO Size setup structure
_tx_fifo_size_setupTransmit FIFO Size setup structure
adpctl_dataThis union represents the bit fields of the Core ADP Timer, Control and Status Register (ADPTIMCTLSTS)
cfi_all_features_headerThis structure is the header of the Core Features dataset returned to the Host
cfi_dma_buff
cfi_epThe CFI wrapper of the enabled and activated dwc_otg_pcd_ep structures
cfi_feature_desc_headerThis structure is a header of the Core Feature descriptor dataset returned to the Host after the VEN_CORE_GET_FEATURES request
cfi_opsThis is the interface for the CFI operations
cfi_stringThis structure describes a NULL terminated string referenced by its id field
cfi_usb_ctrlrequestStruct cfi_usb_ctrlrequest - the CFI implementation of the struct usb_ctrlrequest This structure encapsulates the standard usb_ctrlrequest and adds a pointer to the data returned in the data stage of a 3-stage Control Write requests
cfiobject
cfi_usb_ctrlrequestStruct cfi_usb_ctrlrequest - the CFI implementation of the struct usb_ctrlrequest This structure encapsulates the standard usb_ctrlrequest and adds a pointer to the data returned in the data stage of a 3-stage Control Write requests
daint_dataThis union represents the bit fields in the Device All EP Interrupt and Mask Registers
dcfg_dataThis union represents the bit fields in the Device Configuration Register
dctl_dataThis union represents the bit fields in the Device Control Register
diepint_dataThis union represents the bit fields in the Device IN EP Interrupt Register and the Device IN EP Common Mask Register
doepint_dataThis union represents the bit fields in the Device OUT EP Interrupt Registerand Device OUT EP Common Interrupt Mask Register
dsts_dataThis union represents the bit fields in the Device Status Register
dthrctl_dataThis union represents Threshold control Register
    +-
  • Read and write the register into the d32 member
+-
dthrctl_dataThis union represents Threshold control Register Read and write the register into the d32 member
dtknq1_dataThis union represents the bit fields in the Device IN Token Queue Read Registers
dtxfsts_dataThis union represents the bit fields in the Transmit FIFO Status Register (DTXFSTS)
dwc_epThe dwc_ep structure represents the state of a single endpoint when acting in device mode
dwc_epThe dwc_ep structure represents the state of a single endpoint when acting in device mode
dwc_hcHost channel descriptor
dwc_otg_cil_callbacksDWC_otg CIL callback structure
dwc_otg_core_global_regsDWC_otg Core registers
dwc_otg_core_ifThe dwc_otg_core_if structure contains information needed to manage the DWC_otg controller acting in either host or device mode
dwc_otg_core_ifThe dwc_otg_core_if structure contains information needed to manage the DWC_otg controller acting in either host or device mode
dwc_otg_core_paramsThe following parameters may be specified when starting the module
dwc_otg_dev_dma_descDMA Descriptor structure
dwc_otg_dev_global_regsDevice Global Registers
dwc_otg_dev_ifThe dwc_otg_dev_if structure contains information needed to manage the DWC_otg controller acting in device mode
dwc_otg_dev_ifThe dwc_otg_dev_if structure contains information needed to manage the DWC_otg controller acting in device mode
dwc_otg_dev_in_ep_regsDevice Logical IN Endpoint-Specific Registers
dwc_otg_dev_out_ep_regsDevice Logical OUT Endpoint-Specific Registers
dwc_otg_deviceThis structure is a wrapper that encapsulates the driver components used to manage a single DWC_otg controller
dwc_otg_driver_module_params
dwc_otg_hc_regsHost Channel Specific Registers
dwc_otg_hcdThis structure holds the state of the HCD, including the non-periodic and periodic schedules
dwc_otg_hcd::dwc_otg_hcd_internal_flagsInternal DWC HCD Flags
dwc_otg_hcd_function_ops
dwc_otg_hcd_iso_packet_desc
dwc_otg_hcd_pipe_info
dwc_otg_hcd_urb
dwc_otg_host_dma_descHost-mode DMA Descriptor structure
dwc_otg_host_global_regsThe Host Global Registers structure defines the size and relative field offsets for the Host Mode Global Registers
dwc_otg_host_ifOTG Host Interface Structure
dwc_otg_qhA Queue Head (QH) holds the static characteristics of an endpoint and maintains a list of transfers (QTDs) for that endpoint
dwc_otg_qtdA Queue Transfer Descriptor (QTD) holds the state of a bulk, control, interrupt, or isochronous transfer
fifosize_dataThis union represents the bit fields in the FIFO Size Registers (HPTXFSIZ, GNPTXFSIZ, DPTXFSIZn, DIEPTXFn)
gadget_wrapper
gahbcfg_dataThis union represents the bit fields of the Core AHB Configuration Register (GAHBCFG)
gdfifocfg_dataThis union represents the bit fields in the Global Data FIFO Software Configuration Register
ggpio_dataThis union represents the bit fields in the General Purpose Input/Output Register (GGPIO)
gi2cctl_dataThis union represents the bit fields in the I2C Control Register (I2CCTL)
gintmsk_dataThis union represents the bit fields of the Core Interrupt Mask Register (GINTMSK)
gintsts_dataThis union represents the bit fields of the Core Interrupt Register (GINTSTS)
gnptxsts_dataThis union represents the bit fields in the Non-Periodic Transmit FIFO/Queue Status Register (GNPTXSTS)
gotgctl_dataThis union represents the bit fields of the Core OTG Control and Status Register (GOTGCTL)
gotgint_dataThis union represents the bit fields of the Core OTG Interrupt Register (GOTGINT)
gpvndctl_dataThis union represents the bit fields in the PHY Vendor Control Register (GPVNDCTL)
gpwrdn_dataThis union represents the bit fields in the Global Power Down Register Register
grstctl_dataThis union represents the bit fields of the Core Reset Register (GRSTCTL)
gsnpsid_dataThis union represents the bit fields in the Synopsys ID Register (GSNPSID)
guid_dataThis union represents the bit fields in the User ID Register (GUID)
gusbcfg_dataThis union represents the bit fields of the Core USB Configuration Register (GUSBCFG)
haint_dataThis union represents the bit fields in the Host All Interrupt Register
haintmsk_dataThis union represents the bit fields in the Host All Interrupt Register
hcfg_dataThis union represents the bit fields in the Host Configuration Register
hcint_dataThis union represents the bit fields in the Host All Interrupt Register
hcintmsk_dataThis union represents the bit fields in the Host Channel Interrupt Mask Register
hcsplt_data
hctsiz_dataThis union represents the bit fields in the Host Channel Transfer Size Register
hfir_dataThis union represents the bit fields in the Host Frame Remaing/Number Register
hfnum_dataThis union represents the bit fields in the Host Frame Remaing/Number Register
host_dma_desc_stsThis union represents the bit fields in the DMA Descriptor status quadlet for host mode
host_grxsts_dataThis union represents the bit fields in the Host Receive Status Read and Pop Registers (GRXSTSR, GRXSTSP) Read the register into the d32 element then read out the bits using the bit elements
hprt0_dataThis union represents the bit fields in the Host Port Control and Status Register
hptxsts_data
hwcfg1_dataThis union represents the bit fields in the User HW Config1 Register
hwcfg2_dataThis union represents the bit fields in the User HW Config2 Register
hwcfg3_dataThis union represents the bit fields in the User HW Config3 Register
hwcfg4_dataThis union represents the bit fields in the User HW Config4 Register
iso_pkt_infoInformation for each ISOC packet
pcgcctl_dataThis union represents the bit fields in the Power and Clock Gating Control Register
wrapper_priv_data
zero_dev
+-
Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++
Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
++doxygen 1.3.9.1
+ + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/doxygen.css +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/doxygen.css 2013-07-26 19:31:20.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/doxygen.css 2013-07-26 19:34:39.000000000 +0000 +@@ -1,24 +1,14 @@ + BODY,H1,H2,H3,H4,H5,H6,P,CENTER,TD,TH,UL,DL,DIV { + font-family: Geneva, Arial, Helvetica, sans-serif; + } +-BODY,TD { +- font-size: 90%; +-} + H1 { + text-align: center; +- font-size: 160%; +-} +-H2 { +- font-size: 120%; +-} +-H3 { +- font-size: 100%; + } + CAPTION { font-weight: bold } + DIV.qindex { + width: 100%; +- background-color: #e8eef2; +- border: 1px solid #84b0c7; ++ background-color: #eeeeff; ++ border: 1px solid #b0b0b0; + text-align: center; + margin: 2px; + padding: 2px; +@@ -26,24 +16,13 @@ + } + DIV.nav { + width: 100%; +- background-color: #e8eef2; +- border: 1px solid #84b0c7; ++ background-color: #eeeeff; ++ border: 1px solid #b0b0b0; + text-align: center; + margin: 2px; + padding: 2px; + line-height: 140%; + } +-DIV.navtab { +- background-color: #e8eef2; +- border: 1px solid #84b0c7; +- text-align: center; +- margin: 2px; +- margin-right: 15px; +- padding: 2px; +-} +-TD.navtab { +- font-size: 70%; +-} + A.qindex { + text-decoration: none; + font-weight: bold; +@@ -80,8 +59,7 @@ + A:hover { text-decoration: none; background-color: #f2f2ff } + DL.el { margin-left: -1cm } + .fragment { +- font-family: monospace, fixed; +- font-size: 95%; ++ font-family: monospace + } + PRE.fragment { + border: 1px solid #CCCCCC; +@@ -96,14 +74,16 @@ + padding-bottom: 4px; + } + DIV.ah { background-color: black; font-weight: bold; color: #ffffff; margin-bottom: 3px; margin-top: 3px } +- ++TD.md { background-color: #F4F4FB; font-weight: bold; } ++TD.mdname1 { background-color: #F4F4FB; font-weight: bold; color: #602020; } ++TD.mdname { background-color: #F4F4FB; font-weight: bold; color: #602020; width: 600px; } + DIV.groupHeader { + margin-left: 16px; + margin-top: 12px; + margin-bottom: 6px; + font-weight: bold; + } +-DIV.groupText { margin-left: 16px; font-style: italic; font-size: 90% } ++DIV.groupText { margin-left: 16px; font-style: italic; font-size: 14px } + BODY { + background: white; + color: black; +@@ -111,7 +91,7 @@ + margin-left: 20px; + } + TD.indexkey { +- background-color: #e8eef2; ++ background-color: #eeeeff; + font-weight: bold; + padding-right : 10px; + padding-top : 2px; +@@ -124,7 +104,7 @@ + border: 1px solid #CCCCCC; + } + TD.indexvalue { +- background-color: #e8eef2; ++ background-color: #eeeeff; + font-style: italic; + padding-right : 10px; + padding-top : 2px; +@@ -149,9 +129,16 @@ + SPAN.preprocessor { color: #806020 } + SPAN.stringliteral { color: #002080 } + SPAN.charliteral { color: #008080 } ++.mdTable { ++ border: 1px solid #868686; ++ background-color: #F4F4FB; ++} ++.mdRow { ++ padding: 8px 10px; ++} + .mdescLeft { + padding: 0px 8px 4px 8px; +- font-size: 80%; ++ font-size: 12px; + font-style: italic; + background-color: #FAFAFA; + border-top: 1px none #E0E0E0; +@@ -162,7 +149,7 @@ + } + .mdescRight { + padding: 0px 8px 4px 8px; +- font-size: 80%; ++ font-size: 12px; + font-style: italic; + background-color: #FAFAFA; + border-top: 1px none #E0E0E0; +@@ -187,7 +174,7 @@ + border-bottom-style: none; + border-left-style: none; + background-color: #FAFAFA; +- font-size: 80%; ++ font-size: 12px; + } + .memItemRight { + padding: 1px 8px 0px 8px; +@@ -205,7 +192,7 @@ + border-bottom-style: none; + border-left-style: none; + background-color: #FAFAFA; +- font-size: 80%; ++ font-size: 13px; + } + .memTemplItemLeft { + padding: 1px 0px 0px 8px; +@@ -223,7 +210,7 @@ + border-bottom-style: none; + border-left-style: none; + background-color: #FAFAFA; +- font-size: 80%; ++ font-size: 12px; + } + .memTemplItemRight { + padding: 1px 8px 0px 8px; +@@ -241,7 +228,7 @@ + border-bottom-style: none; + border-left-style: none; + background-color: #FAFAFA; +- font-size: 80%; ++ font-size: 13px; + } + .memTemplParams { + padding: 1px 0px 0px 8px; +@@ -260,7 +247,7 @@ + border-left-style: none; + color: #606060; + background-color: #FAFAFA; +- font-size: 80%; ++ font-size: 12px; + } + .search { color: #003399; + font-weight: bold; +@@ -272,87 +259,13 @@ + INPUT.search { font-size: 75%; + color: #000080; + font-weight: normal; +- background-color: #e8eef2; ++ background-color: #eeeeff; + } + TD.tiny { font-size: 75%; + } + a { +- color: #1A41A8; ++ color: #252E78; + } + a:visited { +- color: #2A3798; ++ color: #3D2185; + } +-.dirtab { padding: 4px; +- border-collapse: collapse; +- border: 1px solid #84b0c7; +-} +-TH.dirtab { background: #e8eef2; +- font-weight: bold; +-} +-HR { height: 1px; +- border: none; +- border-top: 1px solid black; +-} +- +-/* Style for detailed member documentation */ +-.memtemplate { +- font-size: 80%; +- color: #606060; +- font-weight: normal; +-} +-.memnav { +- background-color: #e8eef2; +- border: 1px solid #84b0c7; +- text-align: center; +- margin: 2px; +- margin-right: 15px; +- padding: 2px; +-} +-.memitem { +- padding: 4px; +- background-color: #eef3f5; +- border-width: 1px; +- border-style: solid; +- border-color: #dedeee; +- -moz-border-radius: 8px 8px 8px 8px; +-} +-.memname { +- white-space: nowrap; +- font-weight: bold; +-} +-.memdoc{ +- padding-left: 10px; +-} +-.memproto { +- background-color: #d5e1e8; +- width: 100%; +- border-width: 1px; +- border-style: solid; +- border-color: #84b0c7; +- font-weight: bold; +- -moz-border-radius: 8px 8px 8px 8px; +-} +-.paramkey { +- text-align: right; +-} +-.paramtype { +- white-space: nowrap; +-} +-.paramname { +- color: #602020; +- font-style: italic; +-} +-/* End Styling for detailed member documentation */ +- +-/* for the tree view */ +-.ftvtree { +- font-family: sans-serif; +- margin:0.5em; +-} +-.directory { font-size: 9pt; font-weight: bold; } +-.directory h3 { margin: 0px; margin-top: 1em; font-size: 11pt; } +-.directory > h3 { margin-top: 0; } +-.directory p { margin: 0px; white-space: nowrap; } +-.directory div { display: none; margin: 0px; } +-.directory img { vertical-align: -30%; } +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dummy__audio_8c-source.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/dummy__audio_8c-source.html 2013-07-26 19:31:20.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,1550 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dummy_audio.c Source File +- +- +- +- +-
+-
+-
+-
+-

dummy_audio.c

00001 /*
+-00002  * zero.c -- Gadget Zero, for USB development
+-00003  *
+-00004  * Copyright (C) 2003-2004 David Brownell
+-00005  * All rights reserved.
+-00006  *
+-00007  * Redistribution and use in source and binary forms, with or without
+-00008  * modification, are permitted provided that the following conditions
+-00009  * are met:
+-00010  * 1. Redistributions of source code must retain the above copyright
+-00011  *    notice, this list of conditions, and the following disclaimer,
+-00012  *    without modification.
+-00013  * 2. Redistributions in binary form must reproduce the above copyright
+-00014  *    notice, this list of conditions and the following disclaimer in the
+-00015  *    documentation and/or other materials provided with the distribution.
+-00016  * 3. The names of the above-listed copyright holders may not be used
+-00017  *    to endorse or promote products derived from this software without
+-00018  *    specific prior written permission.
+-00019  *
+-00020  * ALTERNATIVELY, this software may be distributed under the terms of the
+-00021  * GNU General Public License ("GPL") as published by the Free Software
+-00022  * Foundation, either version 2 of that License or (at your option) any
+-00023  * later version.
+-00024  *
+-00025  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+-00026  * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-00027  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-00028  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+-00029  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+-00030  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+-00031  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+-00032  * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+-00033  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+-00034  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+-00035  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+-00036  */
+-00037 
+-00038 
+-00039 /*
+-00040  * Gadget Zero only needs two bulk endpoints, and is an example of how you
+-00041  * can write a hardware-agnostic gadget driver running inside a USB device.
+-00042  *
+-00043  * Hardware details are visible (see CONFIG_USB_ZERO_* below) but don't
+-00044  * affect most of the driver.
+-00045  *
+-00046  * Use it with the Linux host/master side "usbtest" driver to get a basic
+-00047  * functional test of your device-side usb stack, or with "usb-skeleton".
+-00048  *
+-00049  * It supports two similar configurations.  One sinks whatever the usb host
+-00050  * writes, and in return sources zeroes.  The other loops whatever the host
+-00051  * writes back, so the host can read it.  Module options include:
+-00052  *
+-00053  *   buflen=N           default N=4096, buffer size used
+-00054  *   qlen=N             default N=32, how many buffers in the loopback queue
+-00055  *   loopdefault        default false, list loopback config first
+-00056  *
+-00057  * Many drivers will only have one configuration, letting them be much
+-00058  * simpler if they also don't support high speed operation (like this
+-00059  * driver does).
+-00060  */
+-00061 
+-00062 #include <linux/config.h>
+-00063 #include <linux/module.h>
+-00064 #include <linux/kernel.h>
+-00065 #include <linux/delay.h>
+-00066 #include <linux/ioport.h>
+-00067 #include <linux/sched.h>
+-00068 #include <linux/slab.h>
+-00069 #include <linux/smp_lock.h>
+-00070 #include <linux/errno.h>
+-00071 #include <linux/init.h>
+-00072 #include <linux/timer.h>
+-00073 #include <linux/list.h>
+-00074 #include <linux/interrupt.h>
+-00075 #include <linux/uts.h>
+-00076 #include <linux/version.h>
+-00077 #include <linux/device.h>
+-00078 #include <linux/moduleparam.h>
+-00079 #include <linux/proc_fs.h>
+-00080 
+-00081 #include <asm/byteorder.h>
+-00082 #include <asm/io.h>
+-00083 #include <asm/irq.h>
+-00084 #include <asm/system.h>
+-00085 #include <asm/unaligned.h>
+-00086 
+-00087 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,21)
+-00088 # include <linux/usb/ch9.h>
+-00089 #else
+-00090 # include <linux/usb_ch9.h>
+-00091 #endif
+-00092 
+-00093 #include <linux/usb_gadget.h>
+-00094 
+-00095 
+-00096 /*-------------------------------------------------------------------------*/
+-00097 /*-------------------------------------------------------------------------*/
+-00098 
+-00099 
+-00100 static int utf8_to_utf16le(const char *s, u16 *cp, unsigned len)
+-00101 {
+-00102         int     count = 0;
+-00103         u8      c;
+-00104         u16     uchar;
+-00105 
+-00106         /* this insists on correct encodings, though not minimal ones.
+-00107          * BUT it currently rejects legit 4-byte UTF-8 code points,
+-00108          * which need surrogate pairs.  (Unicode 3.1 can use them.)
+-00109          */
+-00110         while (len != 0 && (c = (u8) *s++) != 0) {
+-00111                 if (unlikely(c & 0x80)) {
+-00112                         // 2-byte sequence:
+-00113                         // 00000yyyyyxxxxxx = 110yyyyy 10xxxxxx
+-00114                         if ((c & 0xe0) == 0xc0) {
+-00115                                 uchar = (c & 0x1f) << 6;
+-00116 
+-00117                                 c = (u8) *s++;
+-00118                                 if ((c & 0xc0) != 0xc0)
+-00119                                         goto fail;
+-00120                                 c &= 0x3f;
+-00121                                 uchar |= c;
+-00122 
+-00123                         // 3-byte sequence (most CJKV characters):
+-00124                         // zzzzyyyyyyxxxxxx = 1110zzzz 10yyyyyy 10xxxxxx
+-00125                         } else if ((c & 0xf0) == 0xe0) {
+-00126                                 uchar = (c & 0x0f) << 12;
+-00127 
+-00128                                 c = (u8) *s++;
+-00129                                 if ((c & 0xc0) != 0xc0)
+-00130                                         goto fail;
+-00131                                 c &= 0x3f;
+-00132                                 uchar |= c << 6;
+-00133 
+-00134                                 c = (u8) *s++;
+-00135                                 if ((c & 0xc0) != 0xc0)
+-00136                                         goto fail;
+-00137                                 c &= 0x3f;
+-00138                                 uchar |= c;
+-00139 
+-00140                                 /* no bogus surrogates */
+-00141                                 if (0xd800 <= uchar && uchar <= 0xdfff)
+-00142                                         goto fail;
+-00143 
+-00144                         // 4-byte sequence (surrogate pairs, currently rare):
+-00145                         // 11101110wwwwzzzzyy + 110111yyyyxxxxxx
+-00146                         //     = 11110uuu 10uuzzzz 10yyyyyy 10xxxxxx
+-00147                         // (uuuuu = wwww + 1)
+-00148                         // FIXME accept the surrogate code points (only)
+-00149 
+-00150                         } else
+-00151                                 goto fail;
+-00152                 } else
+-00153                         uchar = c;
+-00154                 put_unaligned (cpu_to_le16 (uchar), cp++);
+-00155                 count++;
+-00156                 len--;
+-00157         }
+-00158         return count;
+-00159 fail:
+-00160         return -1;
+-00161 }
+-00162 
+-00163 
+-00181 int
+-00182 usb_gadget_get_string (struct usb_gadget_strings *table, int id, u8 *buf)
+-00183 {
+-00184         struct usb_string       *s;
+-00185         int                     len;
+-00186 
+-00187         /* descriptor 0 has the language id */
+-00188         if (id == 0) {
+-00189                 buf [0] = 4;
+-00190                 buf [1] = USB_DT_STRING;
+-00191                 buf [2] = (u8) table->language;
+-00192                 buf [3] = (u8) (table->language >> 8);
+-00193                 return 4;
+-00194         }
+-00195         for (s = table->strings; s && s->s; s++)
+-00196                 if (s->id == id)
+-00197                         break;
+-00198 
+-00199         /* unrecognized: stall. */
+-00200         if (!s || !s->s)
+-00201                 return -EINVAL;
+-00202 
+-00203         /* string descriptors have length, tag, then UTF16-LE text */
+-00204         len = min ((size_t) 126, strlen (s->s));
+-00205         memset (buf + 2, 0, 2 * len);   /* zero all the bytes */
+-00206         len = utf8_to_utf16le(s->s, (u16 *)&buf[2], len);
+-00207         if (len < 0)
+-00208                 return -EINVAL;
+-00209         buf [0] = (len + 1) * 2;
+-00210         buf [1] = USB_DT_STRING;
+-00211         return buf [0];
+-00212 }
+-00213 
+-00214 
+-00215 /*-------------------------------------------------------------------------*/
+-00216 /*-------------------------------------------------------------------------*/
+-00217 
+-00218 
+-00231 int
+-00232 usb_descriptor_fillbuf(void *buf, unsigned buflen,
+-00233                 const struct usb_descriptor_header **src)
+-00234 {
+-00235         u8      *dest = buf;
+-00236 
+-00237         if (!src)
+-00238                 return -EINVAL;
+-00239 
+-00240         /* fill buffer from src[] until null descriptor ptr */
+-00241         for (; 0 != *src; src++) {
+-00242                 unsigned                len = (*src)->bLength;
+-00243 
+-00244                 if (len > buflen)
+-00245                         return -EINVAL;
+-00246                 memcpy(dest, *src, len);
+-00247                 buflen -= len;
+-00248                 dest += len;
+-00249         }
+-00250         return dest - (u8 *)buf;
+-00251 }
+-00252 
+-00253 
+-00274 int usb_gadget_config_buf(
+-00275         const struct usb_config_descriptor      *config,
+-00276         void                                    *buf,
+-00277         unsigned                                length,
+-00278         const struct usb_descriptor_header      **desc
+-00279 )
+-00280 {
+-00281         struct usb_config_descriptor            *cp = buf;
+-00282         int                                     len;
+-00283 
+-00284         /* config descriptor first */
+-00285         if (length < USB_DT_CONFIG_SIZE || !desc)
+-00286                 return -EINVAL;
+-00287         *cp = *config; 
+-00288 
+-00289         /* then interface/endpoint/class/vendor/... */
+-00290         len = usb_descriptor_fillbuf(USB_DT_CONFIG_SIZE + (u8*)buf,
+-00291                         length - USB_DT_CONFIG_SIZE, desc);
+-00292         if (len < 0)
+-00293                 return len;
+-00294         len += USB_DT_CONFIG_SIZE;
+-00295         if (len > 0xffff)
+-00296                 return -EINVAL;
+-00297 
+-00298         /* patch up the config descriptor */
+-00299         cp->bLength = USB_DT_CONFIG_SIZE;
+-00300         cp->bDescriptorType = USB_DT_CONFIG;
+-00301         cp->wTotalLength = cpu_to_le16(len);
+-00302         cp->bmAttributes |= USB_CONFIG_ATT_ONE;
+-00303         return len;
+-00304 }
+-00305 
+-00306 /*-------------------------------------------------------------------------*/
+-00307 /*-------------------------------------------------------------------------*/
+-00308 
+-00309 
+-00310 #define RBUF_LEN (1024*1024)
+-00311 static int rbuf_start;
+-00312 static int rbuf_len;
+-00313 static __u8 rbuf[RBUF_LEN];
+-00314 
+-00315 /*-------------------------------------------------------------------------*/
+-00316 
+-00317 #define DRIVER_VERSION          "St Patrick's Day 2004"
+-00318 
+-00319 static const char shortname [] = "zero";
+-00320 static const char longname [] = "YAMAHA YST-MS35D USB Speaker  ";
+-00321 
+-00322 static const char source_sink [] = "source and sink data";
+-00323 static const char loopback [] = "loop input to output";
+-00324 
+-00325 /*-------------------------------------------------------------------------*/
+-00326 
+-00327 /*
+-00328  * driver assumes self-powered hardware, and
+-00329  * has no way for users to trigger remote wakeup.
+-00330  *
+-00331  * this version autoconfigures as much as possible,
+-00332  * which is reasonable for most "bulk-only" drivers.
+-00333  */
+-00334 static const char *EP_IN_NAME;          /* source */
+-00335 static const char *EP_OUT_NAME;         /* sink */
+-00336 
+-00337 /*-------------------------------------------------------------------------*/
+-00338 
+-00339 /* big enough to hold our biggest descriptor */
+-00340 #define USB_BUFSIZ      512
+-00341 
+-00342 struct zero_dev {
+-00343         spinlock_t              lock;
+-00344         struct usb_gadget       *gadget;
+-00345         struct usb_request      *req;           /* for control responses */
+-00346 
+-00347         /* when configured, we have one of two configs:
+-00348          * - source data (in to host) and sink it (out from host)
+-00349          * - or loop it back (out from host back in to host)
+-00350          */
+-00351         u8                      config;
+-00352         struct usb_ep           *in_ep, *out_ep;
+-00353 
+-00354         /* autoresume timer */
+-00355         struct timer_list       resume;
+-00356 };
+-00357 
+-00358 #define xprintk(d,level,fmt,args...) \
+-00359         dev_printk(level , &(d)->gadget->dev , fmt , ## args)
+-00360 
+-00361 #ifdef DEBUG
+-00362 #define DBG(dev,fmt,args...) \
+-00363         xprintk(dev , KERN_DEBUG , fmt , ## args)
+-00364 #else
+-00365 #define DBG(dev,fmt,args...) \
+-00366         do { } while (0)
+-00367 #endif /* DEBUG */
+-00368 
+-00369 #ifdef VERBOSE
+-00370 #define VDBG    DBG
+-00371 #else
+-00372 #define VDBG(dev,fmt,args...) \
+-00373         do { } while (0)
+-00374 #endif /* VERBOSE */
+-00375 
+-00376 #define ERROR(dev,fmt,args...) \
+-00377         xprintk(dev , KERN_ERR , fmt , ## args)
+-00378 #define WARN(dev,fmt,args...) \
+-00379         xprintk(dev , KERN_WARNING , fmt , ## args)
+-00380 #define INFO(dev,fmt,args...) \
+-00381         xprintk(dev , KERN_INFO , fmt , ## args)
+-00382 
+-00383 /*-------------------------------------------------------------------------*/
+-00384 
+-00385 static unsigned buflen = 4096;
+-00386 static unsigned qlen = 32;
+-00387 static unsigned pattern = 0;
+-00388 
+-00389 module_param (buflen, uint, S_IRUGO|S_IWUSR);
+-00390 module_param (qlen, uint, S_IRUGO|S_IWUSR);
+-00391 module_param (pattern, uint, S_IRUGO|S_IWUSR);
+-00392 
+-00393 /*
+-00394  * if it's nonzero, autoresume says how many seconds to wait
+-00395  * before trying to wake up the host after suspend.
+-00396  */
+-00397 static unsigned autoresume = 0;
+-00398 module_param (autoresume, uint, 0);
+-00399 
+-00400 /*
+-00401  * Normally the "loopback" configuration is second (index 1) so
+-00402  * it's not the default.  Here's where to change that order, to
+-00403  * work better with hosts where config changes are problematic.
+-00404  * Or controllers (like superh) that only support one config.
+-00405  */
+-00406 static int loopdefault = 0;
+-00407 
+-00408 module_param (loopdefault, bool, S_IRUGO|S_IWUSR);
+-00409 
+-00410 /*-------------------------------------------------------------------------*/
+-00411 
+-00412 /* Thanks to NetChip Technologies for donating this product ID.
+-00413  *
+-00414  * DO NOT REUSE THESE IDs with a protocol-incompatible driver!!  Ever!!
+-00415  * Instead:  allocate your own, using normal USB-IF procedures.
+-00416  */
+-00417 #ifndef CONFIG_USB_ZERO_HNPTEST
+-00418 #define DRIVER_VENDOR_NUM       0x0525          /* NetChip */
+-00419 #define DRIVER_PRODUCT_NUM      0xa4a0          /* Linux-USB "Gadget Zero" */
+-00420 #else
+-00421 #define DRIVER_VENDOR_NUM       0x1a0a          /* OTG test device IDs */
+-00422 #define DRIVER_PRODUCT_NUM      0xbadd
+-00423 #endif
+-00424 
+-00425 /*-------------------------------------------------------------------------*/
+-00426 
+-00427 /*
+-00428  * DESCRIPTORS ... most are static, but strings and (full)
+-00429  * configuration descriptors are built on demand.
+-00430  */
+-00431 
+-00432 /*
+-00433 #define STRING_MANUFACTURER             25
+-00434 #define STRING_PRODUCT                  42
+-00435 #define STRING_SERIAL                   101
+-00436 */
+-00437 #define STRING_MANUFACTURER             1
+-00438 #define STRING_PRODUCT                  2
+-00439 #define STRING_SERIAL                   3
+-00440 
+-00441 #define STRING_SOURCE_SINK              250
+-00442 #define STRING_LOOPBACK                 251
+-00443 
+-00444 /*
+-00445  * This device advertises two configurations; these numbers work
+-00446  * on a pxa250 as well as more flexible hardware.
+-00447  */
+-00448 #define CONFIG_SOURCE_SINK      3
+-00449 #define CONFIG_LOOPBACK         2
+-00450 
+-00451 /*
+-00452 static struct usb_device_descriptor
+-00453 device_desc = {
+-00454         .bLength =              sizeof device_desc,
+-00455         .bDescriptorType =      USB_DT_DEVICE,
+-00456 
+-00457         .bcdUSB =               __constant_cpu_to_le16 (0x0200),
+-00458         .bDeviceClass =         USB_CLASS_VENDOR_SPEC,
+-00459 
+-00460         .idVendor =             __constant_cpu_to_le16 (DRIVER_VENDOR_NUM),
+-00461         .idProduct =            __constant_cpu_to_le16 (DRIVER_PRODUCT_NUM),
+-00462         .iManufacturer =        STRING_MANUFACTURER,
+-00463         .iProduct =             STRING_PRODUCT,
+-00464         .iSerialNumber =        STRING_SERIAL,
+-00465         .bNumConfigurations =   2,
+-00466 };
+-00467 */
+-00468 static struct usb_device_descriptor
+-00469 device_desc = {
+-00470         .bLength =              sizeof device_desc,
+-00471         .bDescriptorType =      USB_DT_DEVICE,
+-00472         .bcdUSB =               __constant_cpu_to_le16 (0x0100),
+-00473         .bDeviceClass =         USB_CLASS_PER_INTERFACE,
+-00474         .bDeviceSubClass =      0,
+-00475         .bDeviceProtocol =      0,
+-00476         .bMaxPacketSize0 =      64,
+-00477         .bcdDevice =            __constant_cpu_to_le16 (0x0100),
+-00478         .idVendor =             __constant_cpu_to_le16 (0x0499),
+-00479         .idProduct =            __constant_cpu_to_le16 (0x3002),
+-00480         .iManufacturer =        STRING_MANUFACTURER,
+-00481         .iProduct =             STRING_PRODUCT,
+-00482         .iSerialNumber =        STRING_SERIAL,
+-00483         .bNumConfigurations =   1,
+-00484 };
+-00485 
+-00486 static struct usb_config_descriptor
+-00487 z_config = {
+-00488         .bLength =              sizeof z_config,
+-00489         .bDescriptorType =      USB_DT_CONFIG,
+-00490 
+-00491         /* compute wTotalLength on the fly */
+-00492         .bNumInterfaces =       2,
+-00493         .bConfigurationValue =  1,
+-00494         .iConfiguration =       0,
+-00495         .bmAttributes =         0x40,
+-00496         .bMaxPower =            0,      /* self-powered */
+-00497 };
+-00498 
+-00499 
+-00500 static struct usb_otg_descriptor
+-00501 otg_descriptor = {
+-00502         .bLength =              sizeof otg_descriptor,
+-00503         .bDescriptorType =      USB_DT_OTG,
+-00504 
+-00505         .bmAttributes =         USB_OTG_SRP,
+-00506 };
+-00507 
+-00508 /* one interface in each configuration */
+-00509 #ifdef  CONFIG_USB_GADGET_DUALSPEED
+-00510 
+-00511 /*
+-00512  * usb 2.0 devices need to expose both high speed and full speed
+-00513  * descriptors, unless they only run at full speed.
+-00514  *
+-00515  * that means alternate endpoint descriptors (bigger packets)
+-00516  * and a "device qualifier" ... plus more construction options
+-00517  * for the config descriptor.
+-00518  */
+-00519 
+-00520 static struct usb_qualifier_descriptor
+-00521 dev_qualifier = {
+-00522         .bLength =              sizeof dev_qualifier,
+-00523         .bDescriptorType =      USB_DT_DEVICE_QUALIFIER,
+-00524 
+-00525         .bcdUSB =               __constant_cpu_to_le16 (0x0200),
+-00526         .bDeviceClass =         USB_CLASS_VENDOR_SPEC,
+-00527 
+-00528         .bNumConfigurations =   2,
+-00529 };
+-00530 
+-00531 
+-00532 struct usb_cs_as_general_descriptor {
+-00533         __u8  bLength;
+-00534         __u8  bDescriptorType;
+-00535 
+-00536         __u8  bDescriptorSubType;
+-00537         __u8  bTerminalLink;
+-00538         __u8  bDelay;
+-00539         __u16  wFormatTag;
+-00540 } __attribute__ ((packed));
+-00541 
+-00542 struct usb_cs_as_format_descriptor {
+-00543         __u8  bLength;
+-00544         __u8  bDescriptorType;
+-00545 
+-00546         __u8  bDescriptorSubType;
+-00547         __u8  bFormatType;
+-00548         __u8  bNrChannels;
+-00549         __u8  bSubframeSize;
+-00550         __u8  bBitResolution;
+-00551         __u8  bSamfreqType;
+-00552         __u8  tLowerSamFreq[3];
+-00553         __u8  tUpperSamFreq[3];
+-00554 } __attribute__ ((packed));
+-00555 
+-00556 static const struct usb_interface_descriptor
+-00557 z_audio_control_if_desc = {
+-00558         .bLength =              sizeof z_audio_control_if_desc,
+-00559         .bDescriptorType =      USB_DT_INTERFACE,
+-00560         .bInterfaceNumber = 0,
+-00561         .bAlternateSetting = 0,
+-00562         .bNumEndpoints = 0,
+-00563         .bInterfaceClass = USB_CLASS_AUDIO,
+-00564         .bInterfaceSubClass = 0x1,
+-00565         .bInterfaceProtocol = 0,
+-00566         .iInterface = 0,
+-00567 };
+-00568 
+-00569 static const struct usb_interface_descriptor
+-00570 z_audio_if_desc = {
+-00571         .bLength =              sizeof z_audio_if_desc,
+-00572         .bDescriptorType =      USB_DT_INTERFACE,
+-00573         .bInterfaceNumber = 1,
+-00574         .bAlternateSetting = 0,
+-00575         .bNumEndpoints = 0,
+-00576         .bInterfaceClass = USB_CLASS_AUDIO,
+-00577         .bInterfaceSubClass = 0x2,
+-00578         .bInterfaceProtocol = 0,
+-00579         .iInterface = 0,
+-00580 };
+-00581 
+-00582 static const struct usb_interface_descriptor
+-00583 z_audio_if_desc2 = {
+-00584         .bLength =              sizeof z_audio_if_desc,
+-00585         .bDescriptorType =      USB_DT_INTERFACE,
+-00586         .bInterfaceNumber = 1,
+-00587         .bAlternateSetting = 1,
+-00588         .bNumEndpoints = 1,
+-00589         .bInterfaceClass = USB_CLASS_AUDIO,
+-00590         .bInterfaceSubClass = 0x2,
+-00591         .bInterfaceProtocol = 0,
+-00592         .iInterface = 0,
+-00593 };
+-00594 
+-00595 static const struct usb_cs_as_general_descriptor
+-00596 z_audio_cs_as_if_desc = {
+-00597         .bLength = 7,
+-00598         .bDescriptorType = 0x24,
+-00599         
+-00600         .bDescriptorSubType = 0x01,
+-00601         .bTerminalLink = 0x01,
+-00602         .bDelay = 0x0,
+-00603         .wFormatTag = __constant_cpu_to_le16 (0x0001)
+-00604 };
+-00605 
+-00606 
+-00607 static const struct usb_cs_as_format_descriptor 
+-00608 z_audio_cs_as_format_desc = {
+-00609         .bLength = 0xe,
+-00610         .bDescriptorType = 0x24,
+-00611         
+-00612         .bDescriptorSubType = 2,
+-00613         .bFormatType = 1,
+-00614         .bNrChannels = 1,
+-00615         .bSubframeSize = 1,
+-00616         .bBitResolution = 8,
+-00617         .bSamfreqType = 0,
+-00618         .tLowerSamFreq = {0x7e, 0x13, 0x00},
+-00619         .tUpperSamFreq = {0xe2, 0xd6, 0x00},
+-00620 };
+-00621 
+-00622 static const struct usb_endpoint_descriptor 
+-00623 z_iso_ep = {
+-00624         .bLength = 0x09,
+-00625         .bDescriptorType = 0x05,
+-00626         .bEndpointAddress = 0x04,
+-00627         .bmAttributes = 0x09,
+-00628         .wMaxPacketSize = 0x0038,
+-00629         .bInterval = 0x01,
+-00630         .bRefresh = 0x00,
+-00631         .bSynchAddress = 0x00,  
+-00632 };
+-00633 
+-00634 static char z_iso_ep2[] = {0x07, 0x25, 0x01, 0x00, 0x02, 0x00, 0x02};
+-00635 
+-00636 // 9 bytes
+-00637 static char z_ac_interface_header_desc[] = 
+-00638 { 0x09, 0x24, 0x01, 0x00, 0x01, 0x2b, 0x00, 0x01, 0x01 };
+-00639 
+-00640 // 12 bytes
+-00641 static char z_0[] = {0x0c, 0x24, 0x02, 0x01, 0x01, 0x01, 0x00, 0x02, 
+-00642                      0x03, 0x00, 0x00, 0x00};
+-00643 // 13 bytes
+-00644 static char z_1[] = {0x0d, 0x24, 0x06, 0x02, 0x01, 0x02, 0x15, 0x00, 
+-00645                      0x02, 0x00, 0x02, 0x00, 0x00};
+-00646 // 9 bytes
+-00647 static char z_2[] = {0x09, 0x24, 0x03, 0x03, 0x01, 0x03, 0x00, 0x02, 
+-00648                      0x00};
+-00649 
+-00650 static char za_0[] = {0x09, 0x04, 0x01, 0x02, 0x01, 0x01, 0x02, 0x00, 
+-00651                       0x00};
+-00652 
+-00653 static char za_1[] = {0x07, 0x24, 0x01, 0x01, 0x00, 0x01, 0x00};
+-00654 
+-00655 static char za_2[] = {0x0e, 0x24, 0x02, 0x01, 0x02, 0x01, 0x08, 0x00, 
+-00656                       0x7e, 0x13, 0x00, 0xe2, 0xd6, 0x00};
+-00657 
+-00658 static char za_3[] = {0x09, 0x05, 0x04, 0x09, 0x70, 0x00, 0x01, 0x00,
+-00659                       0x00};
+-00660 
+-00661 static char za_4[] = {0x07, 0x25, 0x01, 0x00, 0x02, 0x00, 0x02};
+-00662 
+-00663 static char za_5[] = {0x09, 0x04, 0x01, 0x03, 0x01, 0x01, 0x02, 0x00,
+-00664                       0x00};
+-00665 
+-00666 static char za_6[] = {0x07, 0x24, 0x01, 0x01, 0x00, 0x01, 0x00};
+-00667 
+-00668 static char za_7[] = {0x0e, 0x24, 0x02, 0x01, 0x01, 0x02, 0x10, 0x00,
+-00669                       0x7e, 0x13, 0x00, 0xe2, 0xd6, 0x00};
+-00670 
+-00671 static char za_8[] = {0x09, 0x05, 0x04, 0x09, 0x70, 0x00, 0x01, 0x00,
+-00672                       0x00};
+-00673 
+-00674 static char za_9[] = {0x07, 0x25, 0x01, 0x00, 0x02, 0x00, 0x02};
+-00675 
+-00676 static char za_10[] = {0x09, 0x04, 0x01, 0x04, 0x01, 0x01, 0x02, 0x00,
+-00677                        0x00};
+-00678 
+-00679 static char za_11[] = {0x07, 0x24, 0x01, 0x01, 0x00, 0x01, 0x00};
+-00680 
+-00681 static char za_12[] = {0x0e, 0x24, 0x02, 0x01, 0x02, 0x02, 0x10, 0x00,
+-00682                        0x73, 0x13, 0x00, 0xe2, 0xd6, 0x00};
+-00683 
+-00684 static char za_13[] = {0x09, 0x05, 0x04, 0x09, 0xe0, 0x00, 0x01, 0x00,
+-00685                        0x00};
+-00686 
+-00687 static char za_14[] = {0x07, 0x25, 0x01, 0x00, 0x02, 0x00, 0x02};
+-00688 
+-00689 static char za_15[] = {0x09, 0x04, 0x01, 0x05, 0x01, 0x01, 0x02, 0x00, 
+-00690                        0x00};
+-00691 
+-00692 static char za_16[] = {0x07, 0x24, 0x01, 0x01, 0x00, 0x01, 0x00};
+-00693 
+-00694 static char za_17[] = {0x0e, 0x24, 0x02, 0x01, 0x01, 0x03, 0x14, 0x00, 
+-00695                        0x7e, 0x13, 0x00, 0xe2, 0xd6, 0x00};
+-00696 
+-00697 static char za_18[] = {0x09, 0x05, 0x04, 0x09, 0xa8, 0x00, 0x01, 0x00,
+-00698                        0x00};
+-00699 
+-00700 static char za_19[] = {0x07, 0x25, 0x01, 0x00, 0x02, 0x00, 0x02};
+-00701 
+-00702 static char za_20[] = {0x09, 0x04, 0x01, 0x06, 0x01, 0x01, 0x02, 0x00,
+-00703                        0x00};
+-00704 
+-00705 static char za_21[] = {0x07, 0x24, 0x01, 0x01, 0x00, 0x01, 0x00};
+-00706 
+-00707 static char za_22[] = {0x0e, 0x24, 0x02, 0x01, 0x02, 0x03, 0x14, 0x00, 
+-00708                        0x7e, 0x13, 0x00, 0xe2, 0xd6, 0x00};
+-00709 
+-00710 static char za_23[] = {0x09, 0x05, 0x04, 0x09, 0x50, 0x01, 0x01, 0x00,
+-00711                        0x00};
+-00712 
+-00713 static char za_24[] = {0x07, 0x25, 0x01, 0x00, 0x02, 0x00, 0x02};
+-00714 
+-00715 
+-00716 
+-00717 static const struct usb_descriptor_header *z_function [] = {
+-00718         (struct usb_descriptor_header *) &z_audio_control_if_desc,
+-00719         (struct usb_descriptor_header *) &z_ac_interface_header_desc,
+-00720         (struct usb_descriptor_header *) &z_0,
+-00721         (struct usb_descriptor_header *) &z_1,
+-00722         (struct usb_descriptor_header *) &z_2,
+-00723         (struct usb_descriptor_header *) &z_audio_if_desc,
+-00724         (struct usb_descriptor_header *) &z_audio_if_desc2,
+-00725         (struct usb_descriptor_header *) &z_audio_cs_as_if_desc,
+-00726         (struct usb_descriptor_header *) &z_audio_cs_as_format_desc,
+-00727         (struct usb_descriptor_header *) &z_iso_ep,
+-00728         (struct usb_descriptor_header *) &z_iso_ep2,
+-00729         (struct usb_descriptor_header *) &za_0,
+-00730         (struct usb_descriptor_header *) &za_1,
+-00731         (struct usb_descriptor_header *) &za_2,
+-00732         (struct usb_descriptor_header *) &za_3,
+-00733         (struct usb_descriptor_header *) &za_4,
+-00734         (struct usb_descriptor_header *) &za_5,
+-00735         (struct usb_descriptor_header *) &za_6,
+-00736         (struct usb_descriptor_header *) &za_7,
+-00737         (struct usb_descriptor_header *) &za_8,
+-00738         (struct usb_descriptor_header *) &za_9,
+-00739         (struct usb_descriptor_header *) &za_10,
+-00740         (struct usb_descriptor_header *) &za_11,
+-00741         (struct usb_descriptor_header *) &za_12,
+-00742         (struct usb_descriptor_header *) &za_13,
+-00743         (struct usb_descriptor_header *) &za_14,
+-00744         (struct usb_descriptor_header *) &za_15,
+-00745         (struct usb_descriptor_header *) &za_16,
+-00746         (struct usb_descriptor_header *) &za_17,
+-00747         (struct usb_descriptor_header *) &za_18,
+-00748         (struct usb_descriptor_header *) &za_19,
+-00749         (struct usb_descriptor_header *) &za_20,
+-00750         (struct usb_descriptor_header *) &za_21,
+-00751         (struct usb_descriptor_header *) &za_22,
+-00752         (struct usb_descriptor_header *) &za_23,
+-00753         (struct usb_descriptor_header *) &za_24,
+-00754         NULL,
+-00755 };
+-00756 
+-00757 /* maxpacket and other transfer characteristics vary by speed. */
+-00758 #define ep_desc(g,hs,fs) (((g)->speed==USB_SPEED_HIGH)?(hs):(fs))
+-00759 
+-00760 #else
+-00761 
+-00762 /* if there's no high speed support, maxpacket doesn't change. */
+-00763 #define ep_desc(g,hs,fs) fs
+-00764 
+-00765 #endif  /* !CONFIG_USB_GADGET_DUALSPEED */
+-00766 
+-00767 static char                             manufacturer [40];
+-00768 //static char                           serial [40];
+-00769 static char                             serial [] = "Ser 00 em";
+-00770 
+-00771 /* static strings, in UTF-8 */
+-00772 static struct usb_string                strings [] = {
+-00773         { STRING_MANUFACTURER, manufacturer, },
+-00774         { STRING_PRODUCT, longname, },
+-00775         { STRING_SERIAL, serial, },
+-00776         { STRING_LOOPBACK, loopback, },
+-00777         { STRING_SOURCE_SINK, source_sink, },
+-00778         {  }                    /* end of list */
+-00779 };
+-00780 
+-00781 static struct usb_gadget_strings        stringtab = {
+-00782         .language       = 0x0409,       /* en-us */
+-00783         .strings        = strings,
+-00784 };
+-00785 
+-00786 /*
+-00787  * config descriptors are also handcrafted.  these must agree with code
+-00788  * that sets configurations, and with code managing interfaces and their
+-00789  * altsettings.  other complexity may come from:
+-00790  *
+-00791  *  - high speed support, including "other speed config" rules
+-00792  *  - multiple configurations
+-00793  *  - interfaces with alternate settings
+-00794  *  - embedded class or vendor-specific descriptors
+-00795  *
+-00796  * this handles high speed, and has a second config that could as easily
+-00797  * have been an alternate interface setting (on most hardware).
+-00798  *
+-00799  * NOTE:  to demonstrate (and test) more USB capabilities, this driver
+-00800  * should include an altsetting to test interrupt transfers, including
+-00801  * high bandwidth modes at high speed.  (Maybe work like Intel's test
+-00802  * device?)
+-00803  */
+-00804 static int
+-00805 config_buf (struct usb_gadget *gadget, u8 *buf, u8 type, unsigned index)
+-00806 {
+-00807         int len;
+-00808         const struct usb_descriptor_header **function;
+-00809         
+-00810         function = z_function;
+-00811         len = usb_gadget_config_buf (&z_config, buf, USB_BUFSIZ, function);
+-00812         if (len < 0)
+-00813                 return len;
+-00814         ((struct usb_config_descriptor *) buf)->bDescriptorType = type;
+-00815         return len;
+-00816 }
+-00817 
+-00818 /*-------------------------------------------------------------------------*/
+-00819 
+-00820 static struct usb_request *
+-00821 alloc_ep_req (struct usb_ep *ep, unsigned length)
+-00822 {
+-00823         struct usb_request      *req;
+-00824 
+-00825         req = usb_ep_alloc_request (ep, GFP_ATOMIC);
+-00826         if (req) {
+-00827                 req->length = length;
+-00828                 req->buf = usb_ep_alloc_buffer (ep, length,
+-00829                                 &req->dma, GFP_ATOMIC);
+-00830                 if (!req->buf) {
+-00831                         usb_ep_free_request (ep, req);
+-00832                         req = NULL;
+-00833                 }
+-00834         }
+-00835         return req;
+-00836 }
+-00837 
+-00838 static void free_ep_req (struct usb_ep *ep, struct usb_request *req)
+-00839 {
+-00840         if (req->buf)
+-00841                 usb_ep_free_buffer (ep, req->buf, req->dma, req->length);
+-00842         usb_ep_free_request (ep, req);
+-00843 }
+-00844 
+-00845 /*-------------------------------------------------------------------------*/
+-00846 
+-00847 /* optionally require specific source/sink data patterns  */
+-00848 
+-00849 static int
+-00850 check_read_data (
+-00851         struct zero_dev         *dev,
+-00852         struct usb_ep           *ep,
+-00853         struct usb_request      *req
+-00854 )
+-00855 {
+-00856         unsigned        i;
+-00857         u8              *buf = req->buf;
+-00858 
+-00859         for (i = 0; i < req->actual; i++, buf++) {
+-00860                 switch (pattern) {
+-00861                 /* all-zeroes has no synchronization issues */
+-00862                 case 0:
+-00863                         if (*buf == 0)
+-00864                                 continue;
+-00865                         break;
+-00866                 /* mod63 stays in sync with short-terminated transfers,
+-00867                  * or otherwise when host and gadget agree on how large
+-00868                  * each usb transfer request should be.  resync is done
+-00869                  * with set_interface or set_config.
+-00870                  */
+-00871                 case 1:
+-00872                         if (*buf == (u8)(i % 63))
+-00873                                 continue;
+-00874                         break;
+-00875                 }
+-00876                 ERROR (dev, "bad OUT byte, buf [%d] = %d\n", i, *buf);
+-00877                 usb_ep_set_halt (ep);
+-00878                 return -EINVAL;
+-00879         }
+-00880         return 0;
+-00881 }
+-00882 
+-00883 /*-------------------------------------------------------------------------*/
+-00884 
+-00885 static void zero_reset_config (struct zero_dev *dev)
+-00886 {
+-00887         if (dev->config == 0)
+-00888                 return;
+-00889 
+-00890         DBG (dev, "reset config\n");
+-00891 
+-00892         /* just disable endpoints, forcing completion of pending i/o.
+-00893          * all our completion handlers free their requests in this case.
+-00894          */
+-00895         if (dev->in_ep) {
+-00896                 usb_ep_disable (dev->in_ep);
+-00897                 dev->in_ep = NULL;
+-00898         }
+-00899         if (dev->out_ep) {
+-00900                 usb_ep_disable (dev->out_ep);
+-00901                 dev->out_ep = NULL;
+-00902         }
+-00903         dev->config = 0;
+-00904         del_timer (&dev->resume);
+-00905 }
+-00906 
+-00907 #define _write(f, buf, sz) (f->f_op->write(f, buf, sz, &f->f_pos))
+-00908 
+-00909 static void 
+-00910 zero_isoc_complete (struct usb_ep *ep, struct usb_request *req)
+-00911 {
+-00912         struct zero_dev *dev = ep->driver_data;
+-00913         int             status = req->status;
+-00914         int i, j;
+-00915 
+-00916         switch (status) {
+-00917 
+-00918         case 0:                         /* normal completion? */
+-00919                 //printk ("\nzero ---------------> isoc normal completion %d bytes\n", req->actual);
+-00920                 for (i=0, j=rbuf_start; i<req->actual; i++) {
+-00921                         //printk ("%02x ", ((__u8*)req->buf)[i]);
+-00922                         rbuf[j] = ((__u8*)req->buf)[i];
+-00923                         j++;
+-00924                         if (j >= RBUF_LEN) j=0;
+-00925                 }
+-00926                 rbuf_start = j;
+-00927                 //printk ("\n\n");
+-00928 
+-00929                 if (rbuf_len < RBUF_LEN) {
+-00930                         rbuf_len += req->actual;
+-00931                         if (rbuf_len > RBUF_LEN) {
+-00932                                 rbuf_len = RBUF_LEN;
+-00933                         }
+-00934                 }
+-00935 
+-00936                 break;
+-00937 
+-00938         /* this endpoint is normally active while we're configured */
+-00939         case -ECONNABORTED:             /* hardware forced ep reset */
+-00940         case -ECONNRESET:               /* request dequeued */
+-00941         case -ESHUTDOWN:                /* disconnect from host */
+-00942                 VDBG (dev, "%s gone (%d), %d/%d\n", ep->name, status,
+-00943                                 req->actual, req->length);
+-00944                 if (ep == dev->out_ep)
+-00945                         check_read_data (dev, ep, req);
+-00946                 free_ep_req (ep, req);
+-00947                 return;
+-00948 
+-00949         case -EOVERFLOW:                /* buffer overrun on read means that
+-00950                                          * we didn't provide a big enough
+-00951                                          * buffer.
+-00952                                          */
+-00953         default:
+-00954 #if 1
+-00955                 DBG (dev, "%s complete --> %d, %d/%d\n", ep->name,
+-00956                                 status, req->actual, req->length);
+-00957 #endif
+-00958         case -EREMOTEIO:                /* short read */
+-00959                 break;
+-00960         }
+-00961 
+-00962         status = usb_ep_queue (ep, req, GFP_ATOMIC);
+-00963         if (status) {
+-00964                 ERROR (dev, "kill %s:  resubmit %d bytes --> %d\n",
+-00965                                 ep->name, req->length, status);
+-00966                 usb_ep_set_halt (ep);
+-00967                 /* FIXME recover later ... somehow */
+-00968         }
+-00969 }
+-00970 
+-00971 static struct usb_request *
+-00972 zero_start_isoc_ep (struct usb_ep *ep, int gfp_flags)
+-00973 {
+-00974         struct usb_request      *req;
+-00975         int                     status;
+-00976 
+-00977         req = alloc_ep_req (ep, 512);
+-00978         if (!req)
+-00979                 return NULL;
+-00980 
+-00981         req->complete = zero_isoc_complete;
+-00982 
+-00983         status = usb_ep_queue (ep, req, gfp_flags);
+-00984         if (status) {
+-00985                 struct zero_dev *dev = ep->driver_data;
+-00986 
+-00987                 ERROR (dev, "start %s --> %d\n", ep->name, status);
+-00988                 free_ep_req (ep, req);
+-00989                 req = NULL;
+-00990         }
+-00991 
+-00992         return req;
+-00993 }
+-00994 
+-00995 /* change our operational config.  this code must agree with the code
+-00996  * that returns config descriptors, and altsetting code.
+-00997  *
+-00998  * it's also responsible for power management interactions. some
+-00999  * configurations might not work with our current power sources.
+-01000  *
+-01001  * note that some device controller hardware will constrain what this
+-01002  * code can do, perhaps by disallowing more than one configuration or
+-01003  * by limiting configuration choices (like the pxa2xx).
+-01004  */
+-01005 static int
+-01006 zero_set_config (struct zero_dev *dev, unsigned number, int gfp_flags)
+-01007 {
+-01008         int                     result = 0;
+-01009         struct usb_gadget       *gadget = dev->gadget;
+-01010         const struct usb_endpoint_descriptor    *d;
+-01011         struct usb_ep           *ep;
+-01012 
+-01013         if (number == dev->config)
+-01014                 return 0;
+-01015 
+-01016         zero_reset_config (dev);
+-01017 
+-01018         gadget_for_each_ep (ep, gadget) {
+-01019 
+-01020                 if (strcmp (ep->name, "ep4") == 0) {
+-01021 
+-01022                         d = (struct usb_endpoint_descripter *)&za_23; // isoc ep desc for audio i/f alt setting 6
+-01023                         result = usb_ep_enable (ep, d);
+-01024 
+-01025                         if (result == 0) {
+-01026                                 ep->driver_data = dev;
+-01027                                 dev->in_ep = ep;
+-01028 
+-01029                                 if (zero_start_isoc_ep (ep, gfp_flags) != 0) {
+-01030 
+-01031                                         dev->in_ep = ep;
+-01032                                         continue;
+-01033                                 }
+-01034 
+-01035                                 usb_ep_disable (ep);
+-01036                                 result = -EIO;
+-01037                         }
+-01038                 }
+-01039 
+-01040         }
+-01041 
+-01042         dev->config = number;
+-01043         return result;
+-01044 }
+-01045 
+-01046 /*-------------------------------------------------------------------------*/
+-01047 
+-01048 static void zero_setup_complete (struct usb_ep *ep, struct usb_request *req)
+-01049 {
+-01050         if (req->status || req->actual != req->length)
+-01051                 DBG ((struct zero_dev *) ep->driver_data,
+-01052                                 "setup complete --> %d, %d/%d\n",
+-01053                                 req->status, req->actual, req->length);
+-01054 }
+-01055 
+-01056 /*
+-01057  * The setup() callback implements all the ep0 functionality that's
+-01058  * not handled lower down, in hardware or the hardware driver (like
+-01059  * device and endpoint feature flags, and their status).  It's all
+-01060  * housekeeping for the gadget function we're implementing.  Most of
+-01061  * the work is in config-specific setup.
+-01062  */
+-01063 static int
+-01064 zero_setup (struct usb_gadget *gadget, const struct usb_ctrlrequest *ctrl)
+-01065 {
+-01066         struct zero_dev         *dev = get_gadget_data (gadget);
+-01067         struct usb_request      *req = dev->req;
+-01068         int                     value = -EOPNOTSUPP;
+-01069 
+-01070         /* usually this stores reply data in the pre-allocated ep0 buffer,
+-01071          * but config change events will reconfigure hardware.
+-01072          */
+-01073         req->zero = 0;
+-01074         switch (ctrl->bRequest) {
+-01075 
+-01076         case USB_REQ_GET_DESCRIPTOR:
+-01077 
+-01078                 switch (ctrl->wValue >> 8) {
+-01079 
+-01080                 case USB_DT_DEVICE:
+-01081                         value = min (ctrl->wLength, (u16) sizeof device_desc);
+-01082                         memcpy (req->buf, &device_desc, value);
+-01083                         break;
+-01084 #ifdef CONFIG_USB_GADGET_DUALSPEED
+-01085                 case USB_DT_DEVICE_QUALIFIER:
+-01086                         if (!gadget->is_dualspeed)
+-01087                                 break;
+-01088                         value = min (ctrl->wLength, (u16) sizeof dev_qualifier);
+-01089                         memcpy (req->buf, &dev_qualifier, value);
+-01090                         break;
+-01091 
+-01092                 case USB_DT_OTHER_SPEED_CONFIG:
+-01093                         if (!gadget->is_dualspeed)
+-01094                                 break;
+-01095                         // FALLTHROUGH
+-01096 #endif /* CONFIG_USB_GADGET_DUALSPEED */
+-01097                 case USB_DT_CONFIG:
+-01098                         value = config_buf (gadget, req->buf,
+-01099                                         ctrl->wValue >> 8,
+-01100                                         ctrl->wValue & 0xff);
+-01101                         if (value >= 0)
+-01102                                 value = min (ctrl->wLength, (u16) value);
+-01103                         break;
+-01104 
+-01105                 case USB_DT_STRING:
+-01106                         /* wIndex == language code.
+-01107                          * this driver only handles one language, you can
+-01108                          * add string tables for other languages, using
+-01109                          * any UTF-8 characters
+-01110                          */
+-01111                         value = usb_gadget_get_string (&stringtab,
+-01112                                         ctrl->wValue & 0xff, req->buf);
+-01113                         if (value >= 0) {
+-01114                                 value = min (ctrl->wLength, (u16) value);
+-01115                         }
+-01116                         break;
+-01117                 }
+-01118                 break;
+-01119 
+-01120         /* currently two configs, two speeds */
+-01121         case USB_REQ_SET_CONFIGURATION:
+-01122                 if (ctrl->bRequestType != 0)
+-01123                         goto unknown;
+-01124 
+-01125                 spin_lock (&dev->lock);
+-01126                 value = zero_set_config (dev, ctrl->wValue, GFP_ATOMIC);
+-01127                 spin_unlock (&dev->lock);
+-01128                 break;
+-01129         case USB_REQ_GET_CONFIGURATION:
+-01130                 if (ctrl->bRequestType != USB_DIR_IN)
+-01131                         goto unknown;
+-01132                 *(u8 *)req->buf = dev->config;
+-01133                 value = min (ctrl->wLength, (u16) 1);
+-01134                 break;
+-01135 
+-01136         /* until we add altsetting support, or other interfaces,
+-01137          * only 0/0 are possible.  pxa2xx only supports 0/0 (poorly)
+-01138          * and already killed pending endpoint I/O.
+-01139          */
+-01140         case USB_REQ_SET_INTERFACE:
+-01141 
+-01142                 if (ctrl->bRequestType != USB_RECIP_INTERFACE)
+-01143                         goto unknown;
+-01144                 spin_lock (&dev->lock);
+-01145                 if (dev->config) {
+-01146                         u8              config = dev->config;
+-01147 
+-01148                         /* resets interface configuration, forgets about
+-01149                          * previous transaction state (queued bufs, etc)
+-01150                          * and re-inits endpoint state (toggle etc)
+-01151                          * no response queued, just zero status == success.
+-01152                          * if we had more than one interface we couldn't
+-01153                          * use this "reset the config" shortcut.
+-01154                          */
+-01155                         zero_reset_config (dev);
+-01156                         zero_set_config (dev, config, GFP_ATOMIC);
+-01157                         value = 0;
+-01158                 }
+-01159                 spin_unlock (&dev->lock);
+-01160                 break;
+-01161         case USB_REQ_GET_INTERFACE:
+-01162                 if ((ctrl->bRequestType == 0x21) && (ctrl->wIndex == 0x02)) {
+-01163                         value = ctrl->wLength;
+-01164                         break;
+-01165                 }
+-01166                 else {
+-01167                         if (ctrl->bRequestType != (USB_DIR_IN|USB_RECIP_INTERFACE))
+-01168                                 goto unknown;
+-01169                         if (!dev->config)
+-01170                                 break;
+-01171                         if (ctrl->wIndex != 0) {
+-01172                                 value = -EDOM;
+-01173                                 break;
+-01174                         }
+-01175                         *(u8 *)req->buf = 0;
+-01176                         value = min (ctrl->wLength, (u16) 1);
+-01177                 }
+-01178                 break;
+-01179 
+-01180         /*
+-01181          * These are the same vendor-specific requests supported by
+-01182          * Intel's USB 2.0 compliance test devices.  We exceed that
+-01183          * device spec by allowing multiple-packet requests.
+-01184          */
+-01185         case 0x5b:      /* control WRITE test -- fill the buffer */
+-01186                 if (ctrl->bRequestType != (USB_DIR_OUT|USB_TYPE_VENDOR))
+-01187                         goto unknown;
+-01188                 if (ctrl->wValue || ctrl->wIndex)
+-01189                         break;
+-01190                 /* just read that many bytes into the buffer */
+-01191                 if (ctrl->wLength > USB_BUFSIZ)
+-01192                         break;
+-01193                 value = ctrl->wLength;
+-01194                 break;
+-01195         case 0x5c:      /* control READ test -- return the buffer */
+-01196                 if (ctrl->bRequestType != (USB_DIR_IN|USB_TYPE_VENDOR))
+-01197                         goto unknown;
+-01198                 if (ctrl->wValue || ctrl->wIndex)
+-01199                         break;
+-01200                 /* expect those bytes are still in the buffer; send back */
+-01201                 if (ctrl->wLength > USB_BUFSIZ
+-01202                                 || ctrl->wLength != req->length)
+-01203                         break;
+-01204                 value = ctrl->wLength;
+-01205                 break;
+-01206 
+-01207         case 0x01: // SET_CUR
+-01208         case 0x02:
+-01209         case 0x03:
+-01210         case 0x04:
+-01211         case 0x05:
+-01212                 value = ctrl->wLength;
+-01213                 break;
+-01214         case 0x81:
+-01215                 switch (ctrl->wValue) {
+-01216                 case 0x0201:
+-01217                 case 0x0202:
+-01218                         ((u8*)req->buf)[0] = 0x00;
+-01219                         ((u8*)req->buf)[1] = 0xe3;
+-01220                         break;
+-01221                 case 0x0300:
+-01222                 case 0x0500:
+-01223                         ((u8*)req->buf)[0] = 0x00;
+-01224                         break;
+-01225                 }
+-01226                 //((u8*)req->buf)[0] = 0x81;
+-01227                 //((u8*)req->buf)[1] = 0x81;
+-01228                 value = ctrl->wLength;
+-01229                 break;
+-01230         case 0x82:
+-01231                 switch (ctrl->wValue) {
+-01232                 case 0x0201:
+-01233                 case 0x0202:
+-01234                         ((u8*)req->buf)[0] = 0x00;
+-01235                         ((u8*)req->buf)[1] = 0xc3;
+-01236                         break;
+-01237                 case 0x0300:
+-01238                 case 0x0500:
+-01239                         ((u8*)req->buf)[0] = 0x00;
+-01240                         break;
+-01241                 }
+-01242                 //((u8*)req->buf)[0] = 0x82;
+-01243                 //((u8*)req->buf)[1] = 0x82;
+-01244                 value = ctrl->wLength;
+-01245                 break;
+-01246         case 0x83:
+-01247                 switch (ctrl->wValue) {
+-01248                 case 0x0201:
+-01249                 case 0x0202:
+-01250                         ((u8*)req->buf)[0] = 0x00;
+-01251                         ((u8*)req->buf)[1] = 0x00;
+-01252                         break;
+-01253                 case 0x0300:
+-01254                         ((u8*)req->buf)[0] = 0x60;
+-01255                         break;
+-01256                 case 0x0500:    
+-01257                         ((u8*)req->buf)[0] = 0x18;
+-01258                         break;
+-01259                 }
+-01260                 //((u8*)req->buf)[0] = 0x83;
+-01261                 //((u8*)req->buf)[1] = 0x83;
+-01262                 value = ctrl->wLength;
+-01263                 break;
+-01264         case 0x84:
+-01265                 switch (ctrl->wValue) {
+-01266                 case 0x0201:
+-01267                 case 0x0202:
+-01268                         ((u8*)req->buf)[0] = 0x00;
+-01269                         ((u8*)req->buf)[1] = 0x01;
+-01270                         break;
+-01271                 case 0x0300:
+-01272                 case 0x0500:
+-01273                         ((u8*)req->buf)[0] = 0x08;
+-01274                         break;
+-01275                 }
+-01276                 //((u8*)req->buf)[0] = 0x84;
+-01277                 //((u8*)req->buf)[1] = 0x84;
+-01278                 value = ctrl->wLength;
+-01279                 break;
+-01280         case 0x85:
+-01281                 ((u8*)req->buf)[0] = 0x85;
+-01282                 ((u8*)req->buf)[1] = 0x85;
+-01283                 value = ctrl->wLength;
+-01284                 break;
+-01285 
+-01286         
+-01287         default:
+-01288 unknown:
+-01289                 printk("unknown control req%02x.%02x v%04x i%04x l%d\n",
+-01290                         ctrl->bRequestType, ctrl->bRequest,
+-01291                         ctrl->wValue, ctrl->wIndex, ctrl->wLength);
+-01292         }
+-01293 
+-01294         /* respond with data transfer before status phase? */
+-01295         if (value >= 0) {
+-01296                 req->length = value;
+-01297                 req->zero = value < ctrl->wLength
+-01298                                 && (value % gadget->ep0->maxpacket) == 0;
+-01299                 value = usb_ep_queue (gadget->ep0, req, GFP_ATOMIC);
+-01300                 if (value < 0) {
+-01301                         DBG (dev, "ep_queue < 0 --> %d\n", value);
+-01302                         req->status = 0;
+-01303                         zero_setup_complete (gadget->ep0, req);
+-01304                 }
+-01305         }
+-01306 
+-01307         /* device either stalls (value < 0) or reports success */
+-01308         return value;
+-01309 }
+-01310 
+-01311 static void
+-01312 zero_disconnect (struct usb_gadget *gadget)
+-01313 {
+-01314         struct zero_dev         *dev = get_gadget_data (gadget);
+-01315         unsigned long           flags;
+-01316 
+-01317         spin_lock_irqsave (&dev->lock, flags);
+-01318         zero_reset_config (dev);
+-01319 
+-01320         /* a more significant application might have some non-usb
+-01321          * activities to quiesce here, saving resources like power
+-01322          * or pushing the notification up a network stack.
+-01323          */
+-01324         spin_unlock_irqrestore (&dev->lock, flags);
+-01325 
+-01326         /* next we may get setup() calls to enumerate new connections;
+-01327          * or an unbind() during shutdown (including removing module).
+-01328          */
+-01329 }
+-01330 
+-01331 static void
+-01332 zero_autoresume (unsigned long _dev)
+-01333 {
+-01334         struct zero_dev *dev = (struct zero_dev *) _dev;
+-01335         int             status;
+-01336 
+-01337         /* normally the host would be woken up for something
+-01338          * more significant than just a timer firing...
+-01339          */
+-01340         if (dev->gadget->speed != USB_SPEED_UNKNOWN) {
+-01341                 status = usb_gadget_wakeup (dev->gadget);
+-01342                 DBG (dev, "wakeup --> %d\n", status);
+-01343         }
+-01344 }
+-01345 
+-01346 /*-------------------------------------------------------------------------*/
+-01347 
+-01348 static void
+-01349 zero_unbind (struct usb_gadget *gadget)
+-01350 {
+-01351         struct zero_dev         *dev = get_gadget_data (gadget);
+-01352 
+-01353         DBG (dev, "unbind\n");
+-01354 
+-01355         /* we've already been disconnected ... no i/o is active */
+-01356         if (dev->req)
+-01357                 free_ep_req (gadget->ep0, dev->req);
+-01358         del_timer_sync (&dev->resume);
+-01359         kfree (dev);
+-01360         set_gadget_data (gadget, NULL);
+-01361 }
+-01362 
+-01363 static int
+-01364 zero_bind (struct usb_gadget *gadget)
+-01365 {
+-01366         struct zero_dev         *dev;
+-01367         //struct usb_ep         *ep;
+-01368 
+-01369         printk("binding\n");
+-01370         /*
+-01371          * DRIVER POLICY CHOICE:  you may want to do this differently.
+-01372          * One thing to avoid is reusing a bcdDevice revision code
+-01373          * with different host-visible configurations or behavior
+-01374          * restrictions -- using ep1in/ep2out vs ep1out/ep3in, etc
+-01375          */
+-01376         //device_desc.bcdDevice = __constant_cpu_to_le16 (0x0201);
+-01377 
+-01378 
+-01379         /* ok, we made sense of the hardware ... */
+-01380         dev = kmalloc (sizeof *dev, SLAB_KERNEL);
+-01381         if (!dev)
+-01382                 return -ENOMEM;
+-01383         memset (dev, 0, sizeof *dev);
+-01384         spin_lock_init (&dev->lock);
+-01385         dev->gadget = gadget;
+-01386         set_gadget_data (gadget, dev);
+-01387 
+-01388         /* preallocate control response and buffer */
+-01389         dev->req = usb_ep_alloc_request (gadget->ep0, GFP_KERNEL);
+-01390         if (!dev->req)
+-01391                 goto enomem;
+-01392         dev->req->buf = usb_ep_alloc_buffer (gadget->ep0, USB_BUFSIZ,
+-01393                                 &dev->req->dma, GFP_KERNEL);
+-01394         if (!dev->req->buf)
+-01395                 goto enomem;
+-01396 
+-01397         dev->req->complete = zero_setup_complete;
+-01398 
+-01399         device_desc.bMaxPacketSize0 = gadget->ep0->maxpacket;
+-01400 
+-01401 #ifdef CONFIG_USB_GADGET_DUALSPEED
+-01402         /* assume ep0 uses the same value for both speeds ... */
+-01403         dev_qualifier.bMaxPacketSize0 = device_desc.bMaxPacketSize0;
+-01404 
+-01405         /* and that all endpoints are dual-speed */
+-01406         //hs_source_desc.bEndpointAddress = fs_source_desc.bEndpointAddress;
+-01407         //hs_sink_desc.bEndpointAddress = fs_sink_desc.bEndpointAddress;
+-01408 #endif
+-01409 
+-01410         usb_gadget_set_selfpowered (gadget);
+-01411 
+-01412         init_timer (&dev->resume);
+-01413         dev->resume.function = zero_autoresume;
+-01414         dev->resume.data = (unsigned long) dev;
+-01415 
+-01416         gadget->ep0->driver_data = dev;
+-01417 
+-01418         INFO (dev, "%s, version: " DRIVER_VERSION "\n", longname);
+-01419         INFO (dev, "using %s, OUT %s IN %s\n", gadget->name,
+-01420                 EP_OUT_NAME, EP_IN_NAME);
+-01421 
+-01422         snprintf (manufacturer, sizeof manufacturer,
+-01423                 UTS_SYSNAME " " UTS_RELEASE " with %s",
+-01424                 gadget->name);
+-01425 
+-01426         return 0;
+-01427 
+-01428 enomem:
+-01429         zero_unbind (gadget);
+-01430         return -ENOMEM;
+-01431 }
+-01432 
+-01433 /*-------------------------------------------------------------------------*/
+-01434 
+-01435 static void
+-01436 zero_suspend (struct usb_gadget *gadget)
+-01437 {
+-01438         struct zero_dev         *dev = get_gadget_data (gadget);
+-01439 
+-01440         if (gadget->speed == USB_SPEED_UNKNOWN)
+-01441                 return;
+-01442 
+-01443         if (autoresume) {
+-01444                 mod_timer (&dev->resume, jiffies + (HZ * autoresume));
+-01445                 DBG (dev, "suspend, wakeup in %d seconds\n", autoresume);
+-01446         } else
+-01447                 DBG (dev, "suspend\n");
+-01448 }
+-01449 
+-01450 static void
+-01451 zero_resume (struct usb_gadget *gadget)
+-01452 {
+-01453         struct zero_dev         *dev = get_gadget_data (gadget);
+-01454 
+-01455         DBG (dev, "resume\n");
+-01456         del_timer (&dev->resume);
+-01457 }
+-01458 
+-01459 
+-01460 /*-------------------------------------------------------------------------*/
+-01461 
+-01462 static struct usb_gadget_driver zero_driver = {
+-01463 #ifdef CONFIG_USB_GADGET_DUALSPEED
+-01464         .speed          = USB_SPEED_HIGH,
+-01465 #else
+-01466         .speed          = USB_SPEED_FULL,
+-01467 #endif
+-01468         .function       = (char *) longname,
+-01469         .bind           = zero_bind,
+-01470         .unbind         = zero_unbind,
+-01471 
+-01472         .setup          = zero_setup,
+-01473         .disconnect     = zero_disconnect,
+-01474 
+-01475         .suspend        = zero_suspend,
+-01476         .resume         = zero_resume,
+-01477 
+-01478         .driver         = {
+-01479                 .name           = (char *) shortname,
+-01480                 // .shutdown = ...
+-01481                 // .suspend = ...
+-01482                 // .resume = ...
+-01483         },
+-01484 };
+-01485 
+-01486 MODULE_AUTHOR ("David Brownell");
+-01487 MODULE_LICENSE ("Dual BSD/GPL");
+-01488 
+-01489 static struct proc_dir_entry *pdir, *pfile;
+-01490 
+-01491 static int isoc_read_data (char *page, char **start,
+-01492                            off_t off, int count,
+-01493                            int *eof, void *data)
+-01494 {
+-01495         int i;
+-01496         static int c = 0;
+-01497         static int done = 0;
+-01498         static int s = 0;
+-01499 
+-01500 /*
+-01501         printk ("\ncount: %d\n", count);
+-01502         printk ("rbuf_start: %d\n", rbuf_start);
+-01503         printk ("rbuf_len: %d\n", rbuf_len);
+-01504         printk ("off: %d\n", off);
+-01505         printk ("start: %p\n\n", *start);
+-01506 */
+-01507         if (done) {
+-01508                 c = 0;
+-01509                 done = 0;
+-01510                 *eof = 1;
+-01511                 return 0;
+-01512         }
+-01513 
+-01514         if (c == 0) {
+-01515                 if (rbuf_len == RBUF_LEN)
+-01516                         s = rbuf_start;
+-01517                 else s = 0;
+-01518         }
+-01519 
+-01520         for (i=0; i<count && c<rbuf_len; i++, c++) {
+-01521                 page[i] = rbuf[(c+s) % RBUF_LEN];
+-01522         }
+-01523         *start = page;
+-01524         
+-01525         if (c >= rbuf_len) {
+-01526                 *eof = 1;
+-01527                 done = 1;
+-01528         }
+-01529 
+-01530 
+-01531         return i;
+-01532 }
+-01533 
+-01534 static int __init init (void)
+-01535 {
+-01536 
+-01537         int retval = 0;
+-01538 
+-01539         pdir = proc_mkdir("isoc_test", NULL);
+-01540         if(pdir == NULL) {
+-01541                 retval = -ENOMEM;
+-01542                 printk("Error creating dir\n");
+-01543                 goto done;
+-01544         }
+-01545         pdir->owner = THIS_MODULE;
+-01546 
+-01547         pfile = create_proc_read_entry("isoc_data",
+-01548                                        0444, pdir,
+-01549                                        isoc_read_data,
+-01550                                        NULL);
+-01551         if (pfile == NULL) {
+-01552                 retval = -ENOMEM;
+-01553                 printk("Error creating file\n");
+-01554                 goto no_file;
+-01555         }
+-01556         pfile->owner = THIS_MODULE;
+-01557 
+-01558         return usb_gadget_register_driver (&zero_driver);
+-01559 
+-01560  no_file:
+-01561         remove_proc_entry("isoc_data", NULL);
+-01562  done:
+-01563         return retval;
+-01564 }
+-01565 module_init (init);
+-01566 
+-01567 static void __exit cleanup (void)
+-01568 {
+-01569 
+-01570         usb_gadget_unregister_driver (&zero_driver);
+-01571         
+-01572         remove_proc_entry("isoc_data", pdir);
+-01573         remove_proc_entry("isoc_test", NULL);
+-01574 }
+-01575 module_exit (cleanup);
+-
Generated on Tue May 5 02:22:48 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.4.7
+- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__cfi__common_8h-source.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/dwc__cfi__common_8h-source.html 2013-07-26 19:31:20.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__cfi__common_8h-source.html 2013-07-26 19:34:39.000000000 +0000 +@@ -2,114 +2,102 @@ + + DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_cfi_common.h Source File + +- + +- +-
+-
+-
+-
+-

dwc_cfi_common.h

Go to the documentation of this file.
00001 /* ==========================================================================
+-00002  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
+-00003  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
+-00004  * otherwise expressly agreed to in writing between Synopsys and you.
+-00005  * 
+-00006  * The Software IS NOT an item of Licensed Software or Licensed Product under
+-00007  * any End User Software License Agreement or Agreement for Licensed Product
+-00008  * with Synopsys or any supplement thereto. You are permitted to use and
+-00009  * redistribute this Software in source and binary forms, with or without
+-00010  * modification, provided that redistributions of source code must retain this
+-00011  * notice. You may not view, use, disclose, copy or distribute this file or
+-00012  * any information contained herein except pursuant to this license grant from
+-00013  * Synopsys. If you do not agree with this notice, including the disclaimer
+-00014  * below, then you are not authorized to use the Software.
+-00015  * 
+-00016  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
+-00017  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+-00018  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+-00019  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
+-00020  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+-00021  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+-00022  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+-00023  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+-00024  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+-00025  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+-00026  * DAMAGE.
+-00027  * ========================================================================== */
+-00028 
+-00029 #if !defined(__DWC_CFI_COMMON_H__)
+-00030 #define __DWC_CFI_COMMON_H__
+-00031 
+-00032 //#include <linux/types.h>
+-00033 
+-00044 #define VEN_CORE_GET_FEATURES           0xB1
+-00045 
+-00047 #define VEN_CORE_GET_FEATURE            0xB2
+-00048 
+-00050 #define VEN_CORE_SET_FEATURE            0xB3
+-00051 
+-00055 #define VEN_CORE_RESET_FEATURES         0xB4
+-00056 
+-00058 #define VEN_CORE_ACTIVATE_FEATURES      0xB5
+-00059 
+-00061 #define VEN_CORE_READ_REGISTER          0xB6
+-00062 
+-00064 #define VEN_CORE_WRITE_REGISTER         0xB7
+-00065 
++
++
Main Page | Data Structures | File List | Data Fields | Globals | Related Pages

++
dwc_cfi_common.h
Go to the documentation of this file.
00001 /* ==========================================================================
++00002  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
++00003  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
++00004  * otherwise expressly agreed to in writing between Synopsys and you.
++00005  * 
++00006  * The Software IS NOT an item of Licensed Software or Licensed Product under
++00007  * any End User Software License Agreement or Agreement for Licensed Product
++00008  * with Synopsys or any supplement thereto. You are permitted to use and
++00009  * redistribute this Software in source and binary forms, with or without
++00010  * modification, provided that redistributions of source code must retain this
++00011  * notice. You may not view, use, disclose, copy or distribute this file or
++00012  * any information contained herein except pursuant to this license grant from
++00013  * Synopsys. If you do not agree with this notice, including the disclaimer
++00014  * below, then you are not authorized to use the Software.
++00015  * 
++00016  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
++00017  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++00018  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++00019  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
++00020  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++00021  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
++00022  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
++00023  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
++00024  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
++00025  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
++00026  * DAMAGE.
++00027  * ========================================================================== */
++00028 
++00029 #if !defined(__DWC_CFI_COMMON_H__)
++00030 #define __DWC_CFI_COMMON_H__
++00031 
++00032 //#include <linux/types.h>
++00033 
++00044 #define VEN_CORE_GET_FEATURES           0xB1
++00045 
++00047 #define VEN_CORE_GET_FEATURE            0xB2
++00048 
++00050 #define VEN_CORE_SET_FEATURE            0xB3
++00051 
++00055 #define VEN_CORE_RESET_FEATURES         0xB4
++00056 
++00058 #define VEN_CORE_ACTIVATE_FEATURES      0xB5
++00059 
++00061 #define VEN_CORE_READ_REGISTER          0xB6
++00062 
++00064 #define VEN_CORE_WRITE_REGISTER         0xB7
++00065 
+ 00069 struct cfi_all_features_header {
+-00071 #define CFI_ALL_FEATURES_HDR_LEN                8
+-00072 
+-00075         uint16_t wTotalLen;
+-00076 
+-00082         uint16_t wVersion;
+-00083 
+-00085         uint16_t wCoreID;
+-00086 #define CFI_CORE_ID_UDC         1
+-00087 #define CFI_CORE_ID_OTG         2
+-00088 #define CFI_CORE_ID_WUDEV       3
+-00089 
+-00091         uint16_t wNumFeatures;
+-00092 } UPACKED;
+-00093 
+-00094 typedef struct cfi_all_features_header cfi_all_features_header_t;
+-00095 
++00071 #define CFI_ALL_FEATURES_HDR_LEN                8
++00072 
++00075         uint16_t wTotalLen;
++00076 
++00082         uint16_t wVersion;
++00083 
++00085         uint16_t wCoreID;
++00086 #define CFI_CORE_ID_UDC         1
++00087 #define CFI_CORE_ID_OTG         2
++00088 #define CFI_CORE_ID_WUDEV       3
++00089 
++00091         uint16_t wNumFeatures;
++00092 } UPACKED;
++00093 
++00094 typedef struct cfi_all_features_header cfi_all_features_header_t;
++00095 
+ 00099 struct cfi_feature_desc_header {
+-00100 #define CFI_FEATURE_DESC_HDR_LEN        8
+-00101 
+-00103         uint16_t wFeatureID;
+-00104 
+-00108         uint16_t wLength;
+-00109 
+-00111         uint16_t wDataLength;
+-00112 
+-00119         uint8_t bmAttributes;
+-00120 #define CFI_FEATURE_ATTR_RO             1
+-00121 #define CFI_FEATURE_ATTR_RW             0
+-00122 
+-00124         uint8_t bNameLen;
+-00125 
+-00127         //uint8_t *name;
+-00128 } UPACKED;
+-00129 
+-00130 typedef struct cfi_feature_desc_header cfi_feature_desc_header_t;
+-00131 
++00100 #define CFI_FEATURE_DESC_HDR_LEN        8
++00101 
++00103         uint16_t wFeatureID;
++00104 
++00108         uint16_t wLength;
++00109 
++00111         uint16_t wDataLength;
++00112 
++00119         uint8_t bmAttributes;
++00120 #define CFI_FEATURE_ATTR_RO             1
++00121 #define CFI_FEATURE_ATTR_RW             0
++00122 
++00124         uint8_t bNameLen;
++00125 
++00127         //uint8_t *name;
++00128 } UPACKED;
++00129 
++00130 typedef struct cfi_feature_desc_header cfi_feature_desc_header_t;
++00131 
+ 00136 struct cfi_string {
+-00137         uint16_t id;
+-00138         const uint8_t *s;
+-00139 };
+-00140 typedef struct cfi_string cfi_string_t;
+-00141 
+-00142 #endif
+-
Generated on Tue May 5 02:22:48 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by 
++00137         uint16_t id;
++00138         const uint8_t *s;
++00139 };
++00140 typedef struct cfi_string cfi_string_t;
++00141 
++00142 #endif
++
Generated on Thu Oct 27 03:56:37 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
++doxygen 1.3.9.1 + + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__cfi__common_8h.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/dwc__cfi__common_8h.html 2013-07-26 19:31:20.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__cfi__common_8h.html 2013-07-26 19:34:39.000000000 +0000 +@@ -2,21 +2,9 @@ + + DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_cfi_common.h File Reference + +- + +- +-
+-
+-
+-
++ ++
Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
+

dwc_cfi_common.h File Reference

This file contains the CFI specific common constants, interfaces (functions and macros) and structures for Linux. More... +

+ +@@ -34,86 +22,82 @@ + +  This structure describes a NULL terminated string referenced by its id field. More...
+

Defines

+- +-#define __DWC_CFI_COMMON_H__ ++ ++#define __DWC_CFI_COMMON_H__ + +- +-#define VEN_CORE_GET_FEATURES   0xB1 ++ ++#define VEN_CORE_GET_FEATURES   0xB1 + +  This is a request for all Core Features.
+- +-#define VEN_CORE_GET_FEATURE   0xB2 ++ ++#define VEN_CORE_GET_FEATURE   0xB2 + +  This is a request to get the value of a specific Core Feature.
+- +-#define VEN_CORE_SET_FEATURE   0xB3 ++ ++#define VEN_CORE_SET_FEATURE   0xB3 + +  This command allows the host to set the value of a specific Core Feature.
+- +-#define VEN_CORE_RESET_FEATURES   0xB4 ++ ++#define VEN_CORE_RESET_FEATURES   0xB4 + +  This command allows the host to set the default values of either all or any specific Core Feature.
+- +-#define VEN_CORE_ACTIVATE_FEATURES   0xB5 ++ ++#define VEN_CORE_ACTIVATE_FEATURES   0xB5 + +  This command forces the PCD to write the deferred values of a Core Features.
+- +-#define VEN_CORE_READ_REGISTER   0xB6 ++ ++#define VEN_CORE_READ_REGISTER   0xB6 + +  This request reads a DWORD value from a register at the specified offset.
+- +-#define VEN_CORE_WRITE_REGISTER   0xB7 ++ ++#define VEN_CORE_WRITE_REGISTER   0xB7 + +  This request writes a DWORD value into a register at the specified offset.
+- +-#define CFI_ALL_FEATURES_HDR_LEN   8 ++ ++#define CFI_ALL_FEATURES_HDR_LEN   8 + +  The features header structure length is.
+- +-#define CFI_CORE_ID_UDC   1 ++ ++#define CFI_CORE_ID_UDC   1 + +- +-#define CFI_CORE_ID_OTG   2 ++ ++#define CFI_CORE_ID_OTG   2 + +- +-#define CFI_CORE_ID_WUDEV   3 ++ ++#define CFI_CORE_ID_WUDEV   3 + +- +-#define CFI_FEATURE_DESC_HDR_LEN   8 ++ ++#define CFI_FEATURE_DESC_HDR_LEN   8 + +- +-#define CFI_FEATURE_ATTR_RO   1 ++ ++#define CFI_FEATURE_ATTR_RO   1 + +- +-#define CFI_FEATURE_ATTR_RW   0 ++ ++#define CFI_FEATURE_ATTR_RW   0 + +

Typedefs

+- +-typedef cfi_all_features_header cfi_all_features_header_t ++ ++typedef cfi_all_features_header cfi_all_features_header_t + +- +-typedef cfi_feature_desc_header cfi_feature_desc_header_t ++ ++typedef cfi_feature_desc_header cfi_feature_desc_header_t + +- +-typedef cfi_string cfi_string_t ++ ++typedef cfi_string cfi_string_t + +

Variables

+- +-cfi_all_features_header UPACKED ++ ++cfi_all_features_header UPACKED + +  This structure is the header of the Core Features dataset returned to the Host.
+- +-cfi_feature_desc_header UPACKED +- +- This structure is a header of the Core Feature descriptor dataset returned to the Host after the VEN_CORE_GET_FEATURES request.
+ +

Detailed Description

+ This file contains the CFI specific common constants, interfaces (functions and macros) and structures for Linux. +

+-No PCD specific data structure or definition is to be included in this file. ++No PCD specific data structure or definition is to be included in this file. +

+-Definition in file dwc_cfi_common.h.

Generated on Tue May 5 02:22:48 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++Definition in file dwc_cfi_common.h.
Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
++doxygen 1.3.9.1
+ + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__adp_8c-source.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__adp_8c-source.html 2013-07-26 19:34:39.000000000 +0000 +@@ -0,0 +1,769 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_adp.c Source File ++ ++ ++ ++
Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
++

dwc_otg_adp.c

Go to the documentation of this file.
00001 /* ==========================================================================
++00002  * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_adp.c $
++00003  * $Revision: #12 $
++00004  * $Date: 2011/10/26 $
++00005  * $Change: 1873028 $
++00006  *
++00007  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
++00008  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
++00009  * otherwise expressly agreed to in writing between Synopsys and you.
++00010  *
++00011  * The Software IS NOT an item of Licensed Software or Licensed Product under
++00012  * any End User Software License Agreement or Agreement for Licensed Product
++00013  * with Synopsys or any supplement thereto. You are permitted to use and
++00014  * redistribute this Software in source and binary forms, with or without
++00015  * modification, provided that redistributions of source code must retain this
++00016  * notice. You may not view, use, disclose, copy or distribute this file or
++00017  * any information contained herein except pursuant to this license grant from
++00018  * Synopsys. If you do not agree with this notice, including the disclaimer
++00019  * below, then you are not authorized to use the Software.
++00020  *
++00021  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
++00022  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++00023  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++00024  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
++00025  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++00026  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
++00027  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
++00028  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
++00029  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
++00030  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
++00031  * DAMAGE.
++00032  * ========================================================================== */
++00033 
++00034 #include "dwc_os.h"
++00035 #include "dwc_otg_regs.h"
++00036 #include "dwc_otg_cil.h"
++00037 #include "dwc_otg_adp.h"
++00038 
++00046 void dwc_otg_adp_write_reg(dwc_otg_core_if_t * core_if, uint32_t value)
++00047 {
++00048         adpctl_data_t adpctl;
++00049 
++00050         adpctl.d32 = value;
++00051         adpctl.b.ar = 0x2;
++00052 
++00053         DWC_WRITE_REG32(&core_if->core_global_regs->adpctl, adpctl.d32);
++00054 
++00055         while (adpctl.b.ar) {
++00056                 adpctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->adpctl);
++00057         }
++00058 
++00059 }
++00060 
++00064 uint32_t dwc_otg_adp_read_reg(dwc_otg_core_if_t * core_if)
++00065 {
++00066         adpctl_data_t adpctl;
++00067 
++00068         adpctl.d32 = 0;
++00069         adpctl.b.ar = 0x1;
++00070 
++00071         DWC_WRITE_REG32(&core_if->core_global_regs->adpctl, adpctl.d32);
++00072 
++00073         while (adpctl.b.ar) {
++00074                 adpctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->adpctl);
++00075         }
++00076 
++00077         return adpctl.d32;
++00078 }
++00079 
++00083 uint32_t dwc_otg_adp_read_reg_filter(dwc_otg_core_if_t * core_if)
++00084 {
++00085         adpctl_data_t adpctl;
++00086 
++00087         adpctl.d32 = dwc_otg_adp_read_reg(core_if);
++00088         adpctl.b.adp_tmout_int = 0;
++00089         adpctl.b.adp_prb_int = 0;
++00090         adpctl.b.adp_tmout_int = 0;
++00091                 
++00092         return adpctl.d32;
++00093 }
++00094 
++00098 void dwc_otg_adp_modify_reg(dwc_otg_core_if_t * core_if, uint32_t clr,
++00099                             uint32_t set)
++00100 {
++00101         dwc_otg_adp_write_reg(core_if,
++00102                               (dwc_otg_adp_read_reg(core_if) & (~clr)) | set);
++00103 }
++00104 
++00105 static void adp_sense_timeout(void *ptr)
++00106 {
++00107         dwc_otg_core_if_t *core_if = (dwc_otg_core_if_t *) ptr;
++00108         core_if->adp.sense_timer_started = 0;
++00109         DWC_PRINTF("ADP SENSE TIMEOUT\n");
++00110         if (core_if->adp_enable) {
++00111                 dwc_otg_adp_sense_stop(core_if);
++00112                 dwc_otg_adp_probe_start(core_if);
++00113         }
++00114 }
++00115 
++00119 static void adp_vbuson_timeout(void *ptr)
++00120 {
++00121         gpwrdn_data_t gpwrdn;
++00122         dwc_otg_core_if_t *core_if = (dwc_otg_core_if_t *) ptr;
++00123         hprt0_data_t hprt0 = {.d32 = 0 };
++00124         pcgcctl_data_t pcgcctl = {.d32 = 0 };
++00125         DWC_PRINTF("%s: 1.1 seconds expire after turning on VBUS\n",__FUNCTION__);
++00126         if (core_if) {
++00127                 core_if->adp.vbuson_timer_started = 0;
++00128                 /* Turn off vbus */
++00129                 hprt0.b.prtpwr = 1;
++00130                 DWC_MODIFY_REG32(core_if->host_if->hprt0, hprt0.d32, 0);
++00131                 gpwrdn.d32 = 0;
++00132 
++00133                 /* Power off the core */
++00134                 if (core_if->power_down == 2) {
++00135                         /* Enable Wakeup Logic */
++00136 //                      gpwrdn.b.wkupactiv = 1;
++00137                         gpwrdn.b.pmuactv = 0;
++00138                         gpwrdn.b.pwrdnrstn = 1;
++00139                         gpwrdn.b.pwrdnclmp = 1;
++00140                         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0,
++00141                                          gpwrdn.d32);
++00142 
++00143                         /* Suspend the Phy Clock */
++00144                         pcgcctl.b.stoppclk = 1;
++00145                         DWC_MODIFY_REG32(core_if->pcgcctl, 0, pcgcctl.d32);
++00146 
++00147                         /* Switch on VDD */
++00148 //                      gpwrdn.b.wkupactiv = 1;
++00149                         gpwrdn.b.pmuactv = 1;
++00150                         gpwrdn.b.pwrdnrstn = 1;
++00151                         gpwrdn.b.pwrdnclmp = 1;
++00152                         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0,
++00153                                          gpwrdn.d32);
++00154                 } else {
++00155                         /* Enable Power Down Logic */
++00156                         gpwrdn.b.pmuintsel = 1;
++00157                         gpwrdn.b.pmuactv = 1;
++00158                         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
++00159                 }
++00160 
++00161                 /* Power off the core */
++00162                 if (core_if->power_down == 2) {
++00163                         gpwrdn.d32 = 0;
++00164                         gpwrdn.b.pwrdnswtch = 1;
++00165                         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn,
++00166                                          gpwrdn.d32, 0);
++00167                 }
++00168 
++00169                 /* Unmask SRP detected interrupt from Power Down Logic */
++00170                 gpwrdn.d32 = 0;
++00171                 gpwrdn.b.srp_det_msk = 1;
++00172                 DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
++00173 
++00174                 dwc_otg_adp_probe_start(core_if);
++00175                 dwc_otg_dump_global_registers(core_if);
++00176                 dwc_otg_dump_host_registers(core_if);
++00177         }
++00178 
++00179 }
++00180 
++00187 void dwc_otg_adp_vbuson_timer_start(dwc_otg_core_if_t * core_if)
++00188 {
++00189         core_if->adp.vbuson_timer_started = 1;
++00190         if (core_if->adp.vbuson_timer)
++00191         {
++00192                 DWC_PRINTF("SCHEDULING VBUSON TIMER\n");
++00193                 /* 1.1 secs + 60ms necessary for cil_hcd_start*/
++00194                 DWC_TIMER_SCHEDULE(core_if->adp.vbuson_timer, 1160);
++00195         } else {
++00196                 DWC_WARN("VBUSON_TIMER = %p\n",core_if->adp.vbuson_timer);
++00197         }
++00198 }
++00199 
++00200 #if 0
++00201 
++00205 static void mask_all_interrupts(dwc_otg_core_if_t * core_if)
++00206 {
++00207         int i;
++00208         gahbcfg_data_t ahbcfg = {.d32 = 0 };
++00209 
++00210         /* Mask Host Interrupts */
++00211 
++00212         /* Clear and disable HCINTs */
++00213         for (i = 0; i < core_if->core_params->host_channels; i++) {
++00214                 DWC_WRITE_REG32(&core_if->host_if->hc_regs[i]->hcintmsk, 0);
++00215                 DWC_WRITE_REG32(&core_if->host_if->hc_regs[i]->hcint, 0xFFFFFFFF);
++00216 
++00217         }
++00218 
++00219         /* Clear and disable HAINT */
++00220         DWC_WRITE_REG32(&core_if->host_if->host_global_regs->haintmsk, 0x0000);
++00221         DWC_WRITE_REG32(&core_if->host_if->host_global_regs->haint, 0xFFFFFFFF);
++00222 
++00223         /* Mask Device Interrupts */
++00224         if (!core_if->multiproc_int_enable) {
++00225                 /* Clear and disable IN Endpoint interrupts */
++00226                 DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->diepmsk, 0);
++00227                 for (i = 0; i <= core_if->dev_if->num_in_eps; i++) {
++00228                         DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[i]->
++00229                                         diepint, 0xFFFFFFFF);
++00230                 }
++00231 
++00232                 /* Clear and disable OUT Endpoint interrupts */
++00233                 DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->doepmsk, 0);
++00234                 for (i = 0; i <= core_if->dev_if->num_out_eps; i++) {
++00235                         DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[i]->
++00236                                         doepint, 0xFFFFFFFF);
++00237                 }
++00238 
++00239                 /* Clear and disable DAINT */
++00240                 DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->daint,
++00241                                 0xFFFFFFFF);
++00242                 DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->daintmsk, 0);
++00243         } else {
++00244                 for (i = 0; i < core_if->dev_if->num_in_eps; ++i) {
++00245                         DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->
++00246                                         diepeachintmsk[i], 0);
++00247                         DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[i]->
++00248                                         diepint, 0xFFFFFFFF);
++00249                 }
++00250 
++00251                 for (i = 0; i < core_if->dev_if->num_out_eps; ++i) {
++00252                         DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->
++00253                                         doepeachintmsk[i], 0);
++00254                         DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[i]->
++00255                                         doepint, 0xFFFFFFFF);
++00256                 }
++00257 
++00258                 DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->deachintmsk,
++00259                                 0);
++00260                 DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->deachint,
++00261                                 0xFFFFFFFF);
++00262 
++00263         }
++00264 
++00265         /* Disable interrupts */
++00266         ahbcfg.b.glblintrmsk = 1;
++00267         DWC_MODIFY_REG32(&core_if->core_global_regs->gahbcfg, ahbcfg.d32, 0);
++00268 
++00269         /* Disable all interrupts. */
++00270         DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, 0);
++00271 
++00272         /* Clear any pending interrupts */
++00273         DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
++00274 
++00275         /* Clear any pending OTG Interrupts */
++00276         DWC_WRITE_REG32(&core_if->core_global_regs->gotgint, 0xFFFFFFFF);
++00277 }
++00278 
++00283 static void unmask_conn_det_intr(dwc_otg_core_if_t * core_if)
++00284 {
++00285         gintmsk_data_t gintmsk = {.d32 = 0,.b.portintr = 1 };
++00286 
++00287         DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, gintmsk.d32);
++00288 }
++00289 #endif
++00290 
++00296 uint32_t dwc_otg_adp_probe_start(dwc_otg_core_if_t * core_if)
++00297 {
++00298 
++00299         adpctl_data_t adpctl = {.d32 = 0};
++00300         gpwrdn_data_t gpwrdn;
++00301 #if 0
++00302         adpctl_data_t adpctl_int = {.d32 = 0, .b.adp_prb_int = 1,
++00303                                                                 .b.adp_sns_int = 1, b.adp_tmout_int};
++00304 #endif
++00305         dwc_otg_disable_global_interrupts(core_if);
++00306         DWC_PRINTF("ADP Probe Start\n");
++00307         core_if->adp.probe_enabled = 1;
++00308 
++00309         adpctl.b.adpres = 1;
++00310         dwc_otg_adp_write_reg(core_if, adpctl.d32);
++00311 
++00312         while (adpctl.b.adpres) {
++00313                 adpctl.d32 = dwc_otg_adp_read_reg(core_if);
++00314         }
++00315 
++00316         adpctl.d32 = 0;
++00317         gpwrdn.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
++00318 
++00319         /* In Host mode unmask SRP detected interrupt */
++00320         gpwrdn.d32 = 0;
++00321         gpwrdn.b.sts_chngint_msk = 1;
++00322         if (!gpwrdn.b.idsts) {
++00323                 gpwrdn.b.srp_det_msk = 1;
++00324         }
++00325         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
++00326 
++00327         adpctl.b.adp_tmout_int_msk = 1;
++00328         adpctl.b.adp_prb_int_msk = 1;
++00329         adpctl.b.prb_dschg = 1;
++00330         adpctl.b.prb_delta = 1;
++00331         adpctl.b.prb_per = 1;
++00332         adpctl.b.adpen = 1;
++00333         adpctl.b.enaprb = 1;
++00334 
++00335         dwc_otg_adp_write_reg(core_if, adpctl.d32);
++00336         DWC_PRINTF("ADP Probe Finish\n");
++00337         return 0;
++00338 }
++00339 
++00346 void dwc_otg_adp_sense_timer_start(dwc_otg_core_if_t * core_if)
++00347 {
++00348         core_if->adp.sense_timer_started = 1;
++00349         DWC_TIMER_SCHEDULE(core_if->adp.sense_timer, 3000 /* 3 secs */ );
++00350 }
++00351 
++00357 uint32_t dwc_otg_adp_sense_start(dwc_otg_core_if_t * core_if)
++00358 {
++00359         adpctl_data_t adpctl;
++00360 
++00361         DWC_PRINTF("ADP Sense Start\n");
++00362 
++00363         /* Unmask ADP sense interrupt and mask all other from the core */
++00364         adpctl.d32 = dwc_otg_adp_read_reg_filter(core_if);
++00365         adpctl.b.adp_sns_int_msk = 1;
++00366         dwc_otg_adp_write_reg(core_if, adpctl.d32);
++00367         dwc_otg_disable_global_interrupts(core_if); // vahrama 
++00368 
++00369         /* Set ADP reset bit*/
++00370         adpctl.d32 = dwc_otg_adp_read_reg_filter(core_if);
++00371         adpctl.b.adpres = 1;
++00372         dwc_otg_adp_write_reg(core_if, adpctl.d32);
++00373 
++00374         while (adpctl.b.adpres) {
++00375                 adpctl.d32 = dwc_otg_adp_read_reg(core_if);
++00376         }
++00377 
++00378         adpctl.b.adpres = 0;
++00379         adpctl.b.adpen = 1;
++00380         adpctl.b.enasns = 1;
++00381         dwc_otg_adp_write_reg(core_if, adpctl.d32);
++00382 
++00383         dwc_otg_adp_sense_timer_start(core_if);
++00384 
++00385         return 0;
++00386 }
++00387 
++00393 uint32_t dwc_otg_adp_probe_stop(dwc_otg_core_if_t * core_if)
++00394 {
++00395 
++00396         adpctl_data_t adpctl;
++00397         DWC_PRINTF("Stop ADP probe\n");
++00398         core_if->adp.probe_enabled = 0;
++00399         core_if->adp.probe_counter = 0;
++00400         adpctl.d32 = dwc_otg_adp_read_reg(core_if);
++00401 
++00402         adpctl.b.adpen = 0;
++00403         adpctl.b.adp_prb_int = 1;
++00404         adpctl.b.adp_tmout_int = 1;
++00405         adpctl.b.adp_sns_int = 1;
++00406         dwc_otg_adp_write_reg(core_if, adpctl.d32);
++00407 
++00408         return 0;
++00409 }
++00410 
++00416 uint32_t dwc_otg_adp_sense_stop(dwc_otg_core_if_t * core_if)
++00417 {
++00418         adpctl_data_t adpctl;
++00419 
++00420         core_if->adp.sense_enabled = 0;
++00421 
++00422         adpctl.d32 = dwc_otg_adp_read_reg_filter(core_if);
++00423         adpctl.b.enasns = 0;
++00424         adpctl.b.adp_sns_int = 1;
++00425         dwc_otg_adp_write_reg(core_if, adpctl.d32);
++00426 
++00427         return 0;
++00428 }
++00429 
++00437 void dwc_otg_adp_turnon_vbus(dwc_otg_core_if_t * core_if)
++00438 {
++00439         hprt0_data_t hprt0 = {.d32 = 0 };
++00440         hprt0.d32 = dwc_otg_read_hprt0(core_if);
++00441         DWC_PRINTF("Turn on VBUS for 1.1s, port power is %d\n", hprt0.b.prtpwr);
++00442 
++00443         if (hprt0.b.prtpwr == 0) {
++00444                 hprt0.b.prtpwr = 1;
++00445                 //DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
++00446         }
++00447         
++00448         dwc_otg_adp_vbuson_timer_start(core_if);
++00449 }
++00450 
++00458 void dwc_otg_adp_start(dwc_otg_core_if_t * core_if, uint8_t is_host)
++00459 {
++00460         gpwrdn_data_t gpwrdn;
++00461 
++00462         DWC_PRINTF("ADP Initial Start\n");
++00463         core_if->adp.adp_started = 1;
++00464 
++00465         DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
++00466         dwc_otg_disable_global_interrupts(core_if);
++00467         if (is_host) {
++00468                 DWC_PRINTF("HOST MODE\n");
++00469                 /* Enable Power Down Logic Interrupt*/
++00470                 gpwrdn.d32 = 0;
++00471                 gpwrdn.b.pmuintsel = 1;
++00472                 gpwrdn.b.pmuactv = 1;
++00473                 DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
++00474                 /* Initialize first ADP probe to obtain Ramp Time value */
++00475                 core_if->adp.initial_probe = 1;
++00476                 dwc_otg_adp_probe_start(core_if);
++00477         } else {
++00478                 gotgctl_data_t gotgctl;
++00479                 gotgctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->gotgctl);
++00480                 DWC_PRINTF("DEVICE MODE\n");
++00481                 if (gotgctl.b.bsesvld == 0) {
++00482                         /* Enable Power Down Logic Interrupt*/
++00483                         gpwrdn.d32 = 0;
++00484                         DWC_PRINTF("VBUS is not valid - start ADP probe\n");
++00485                         gpwrdn.b.pmuintsel = 1;
++00486                         gpwrdn.b.pmuactv = 1;
++00487                         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
++00488                         core_if->adp.initial_probe = 1;
++00489                         dwc_otg_adp_probe_start(core_if);
++00490                 } else {
++00491                         DWC_PRINTF("VBUS is valid - initialize core as a Device\n");
++00492                         core_if->op_state = B_PERIPHERAL;
++00493                         dwc_otg_core_init(core_if);
++00494                         dwc_otg_enable_global_interrupts(core_if);
++00495                         cil_pcd_start(core_if);
++00496                         dwc_otg_dump_global_registers(core_if);
++00497                         dwc_otg_dump_dev_registers(core_if);
++00498                 }
++00499         }
++00500 }
++00501 
++00502 void dwc_otg_adp_init(dwc_otg_core_if_t * core_if)
++00503 {
++00504         core_if->adp.adp_started = 0;
++00505         core_if->adp.initial_probe = 0;
++00506         core_if->adp.probe_timer_values[0] = -1;
++00507         core_if->adp.probe_timer_values[1] = -1;
++00508         core_if->adp.probe_enabled = 0;
++00509         core_if->adp.sense_enabled = 0;
++00510         core_if->adp.sense_timer_started = 0;
++00511         core_if->adp.vbuson_timer_started = 0;
++00512         core_if->adp.probe_counter = 0;
++00513         core_if->adp.gpwrdn = 0;
++00514         core_if->adp.attached = DWC_OTG_ADP_UNKOWN;
++00515         /* Initialize timers */
++00516         core_if->adp.sense_timer =
++00517             DWC_TIMER_ALLOC("ADP SENSE TIMER", adp_sense_timeout, core_if);
++00518         core_if->adp.vbuson_timer =
++00519             DWC_TIMER_ALLOC("ADP VBUS ON TIMER", adp_vbuson_timeout, core_if);
++00520         if (!core_if->adp.sense_timer || !core_if->adp.vbuson_timer)
++00521         {
++00522                 DWC_ERROR("Could not allocate memory for ADP timers\n");
++00523         }
++00524 }
++00525 
++00526 void dwc_otg_adp_remove(dwc_otg_core_if_t * core_if)
++00527 {
++00528         gpwrdn_data_t gpwrdn = { .d32 = 0 };
++00529         gpwrdn.b.pmuintsel = 1;
++00530         gpwrdn.b.pmuactv = 1;
++00531         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
++00532 
++00533         if (core_if->adp.probe_enabled)         
++00534                 dwc_otg_adp_probe_stop(core_if);
++00535         if (core_if->adp.sense_enabled)         
++00536                 dwc_otg_adp_sense_stop(core_if);
++00537         if (core_if->adp.sense_timer_started)           
++00538                 DWC_TIMER_CANCEL(core_if->adp.sense_timer);
++00539         if (core_if->adp.vbuson_timer_started)          
++00540                 DWC_TIMER_CANCEL(core_if->adp.vbuson_timer);
++00541         DWC_TIMER_FREE(core_if->adp.sense_timer);
++00542         DWC_TIMER_FREE(core_if->adp.vbuson_timer);
++00543 }
++00544 
++00548 
++00551 static uint32_t set_timer_value(dwc_otg_core_if_t * core_if, uint32_t val)
++00552 {
++00553         if (core_if->adp.probe_timer_values[0] == -1) {
++00554                 core_if->adp.probe_timer_values[0] = val;
++00555                 core_if->adp.probe_timer_values[1] = -1;
++00556                 return 1;
++00557         } else {
++00558                 core_if->adp.probe_timer_values[1] =
++00559                     core_if->adp.probe_timer_values[0];
++00560                 core_if->adp.probe_timer_values[0] = val;
++00561                 return 0;
++00562         }
++00563 }
++00564 
++00568 static uint32_t compare_timer_values(dwc_otg_core_if_t * core_if)
++00569 {
++00570         uint32_t diff;
++00571         if (core_if->adp.probe_timer_values[0]>=core_if->adp.probe_timer_values[1])
++00572                         diff = core_if->adp.probe_timer_values[0]-core_if->adp.probe_timer_values[1];
++00573         else
++00574                         diff = core_if->adp.probe_timer_values[1]-core_if->adp.probe_timer_values[0];           
++00575         if(diff < 2) {
++00576                 return 0;
++00577         } else {
++00578                 return 1;
++00579         }
++00580 }
++00581 
++00585 static int32_t dwc_otg_adp_handle_prb_intr(dwc_otg_core_if_t * core_if,
++00586                                                  uint32_t val)
++00587 {
++00588         adpctl_data_t adpctl = {.d32 = 0 };
++00589         gpwrdn_data_t gpwrdn, temp;
++00590         adpctl.d32 = val;
++00591 
++00592         temp.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
++00593         core_if->adp.probe_counter++;
++00594         core_if->adp.gpwrdn = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
++00595         if (adpctl.b.rtim == 0 && !temp.b.idsts){
++00596                 DWC_PRINTF("RTIM value is 0\n");        
++00597                 goto exit;
++00598         }
++00599         if (set_timer_value(core_if, adpctl.b.rtim) &&
++00600             core_if->adp.initial_probe) {
++00601                 core_if->adp.initial_probe = 0;
++00602                 dwc_otg_adp_probe_stop(core_if);
++00603                 gpwrdn.d32 = 0;
++00604                 gpwrdn.b.pmuactv = 1;
++00605                 gpwrdn.b.pmuintsel = 1;
++00606                 DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
++00607                 DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
++00608 
++00609                 /* check which value is for device mode and which for Host mode */
++00610                 if (!temp.b.idsts) {    /* considered host mode value is 0 */
++00611                         /*
++00612                          * Turn on VBUS after initial ADP probe.
++00613                          */
++00614                         core_if->op_state = A_HOST;
++00615                         dwc_otg_enable_global_interrupts(core_if);
++00616                         DWC_SPINUNLOCK(core_if->lock);
++00617                         cil_hcd_start(core_if);
++00618                         dwc_otg_adp_turnon_vbus(core_if);
++00619                         DWC_SPINLOCK(core_if->lock);
++00620                 } else {
++00621                         /*
++00622                          * Initiate SRP after initial ADP probe.
++00623                          */
++00624                         dwc_otg_enable_global_interrupts(core_if);
++00625                         dwc_otg_initiate_srp(core_if);
++00626                 }
++00627         } else if (core_if->adp.probe_counter > 2){
++00628                 gpwrdn.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
++00629                 if (compare_timer_values(core_if)) {
++00630                         DWC_PRINTF("Difference in timer values !!! \n");
++00631 //                      core_if->adp.attached = DWC_OTG_ADP_ATTACHED;
++00632                         dwc_otg_adp_probe_stop(core_if);
++00633 
++00634                         /* Power on the core */
++00635                         if (core_if->power_down == 2) {
++00636                                 gpwrdn.b.pwrdnswtch = 1;
++00637                                 DWC_MODIFY_REG32(&core_if->core_global_regs->
++00638                                                  gpwrdn, 0, gpwrdn.d32);
++00639                         }
++00640 
++00641                         /* check which value is for device mode and which for Host mode */
++00642                         if (!temp.b.idsts) {    /* considered host mode value is 0 */
++00643                                 /* Disable Interrupt from Power Down Logic */
++00644                                 gpwrdn.d32 = 0;
++00645                                 gpwrdn.b.pmuintsel = 1;
++00646                                 gpwrdn.b.pmuactv = 1;
++00647                                 DWC_MODIFY_REG32(&core_if->core_global_regs->
++00648                                                  gpwrdn, gpwrdn.d32, 0);
++00649 
++00650                                 /*
++00651                                  * Initialize the Core for Host mode.
++00652                                  */
++00653                                 core_if->op_state = A_HOST;
++00654                                 dwc_otg_core_init(core_if);
++00655                                 dwc_otg_enable_global_interrupts(core_if);
++00656                                 cil_hcd_start(core_if);
++00657                         } else {
++00658                                 gotgctl_data_t gotgctl;
++00659                                 /* Mask SRP detected interrupt from Power Down Logic */
++00660                                 gpwrdn.d32 = 0;
++00661                                 gpwrdn.b.srp_det_msk = 1;
++00662                                 DWC_MODIFY_REG32(&core_if->core_global_regs->
++00663                                                  gpwrdn, gpwrdn.d32, 0);
++00664 
++00665                                 /* Disable Power Down Logic */
++00666                                 gpwrdn.d32 = 0;
++00667                                 gpwrdn.b.pmuintsel = 1;
++00668                                 gpwrdn.b.pmuactv = 1;
++00669                                 DWC_MODIFY_REG32(&core_if->core_global_regs->
++00670                                                  gpwrdn, gpwrdn.d32, 0);
++00671 
++00672                                 /*
++00673                                  * Initialize the Core for Device mode.
++00674                                  */
++00675                                 core_if->op_state = B_PERIPHERAL;
++00676                                 dwc_otg_core_init(core_if);
++00677                                 dwc_otg_enable_global_interrupts(core_if);
++00678                                 cil_pcd_start(core_if);
++00679 
++00680                                 gotgctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->gotgctl);
++00681                                 if (!gotgctl.b.bsesvld) {
++00682                                         dwc_otg_initiate_srp(core_if);
++00683                                 }
++00684                         }
++00685                 }
++00686                 if (core_if->power_down == 2) {
++00687                         if (gpwrdn.b.bsessvld) {
++00688                                 /* Mask SRP detected interrupt from Power Down Logic */
++00689                                 gpwrdn.d32 = 0;
++00690                                 gpwrdn.b.srp_det_msk = 1;
++00691                                 DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
++00692                                 
++00693                                 /* Disable Power Down Logic */
++00694                                 gpwrdn.d32 = 0;
++00695                                 gpwrdn.b.pmuactv = 1;
++00696                                 DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
++00697 
++00698                                 /*
++00699                                  * Initialize the Core for Device mode.
++00700                                  */
++00701                                 core_if->op_state = B_PERIPHERAL;
++00702                                 dwc_otg_core_init(core_if);
++00703                                 dwc_otg_enable_global_interrupts(core_if);
++00704                                 cil_pcd_start(core_if);
++00705                         }
++00706                 }
++00707         }
++00708 exit:
++00709         /* Clear interrupt */
++00710         adpctl.d32 = dwc_otg_adp_read_reg(core_if);
++00711         adpctl.b.adp_prb_int = 1;
++00712         dwc_otg_adp_write_reg(core_if, adpctl.d32);
++00713 
++00714         return 0;
++00715 }
++00716 
++00720 static int32_t dwc_otg_adp_handle_sns_intr(dwc_otg_core_if_t * core_if)
++00721 {
++00722         adpctl_data_t adpctl;
++00723         /* Stop ADP Sense timer */
++00724         DWC_TIMER_CANCEL(core_if->adp.sense_timer);
++00725 
++00726         /* Restart ADP Sense timer */
++00727         dwc_otg_adp_sense_timer_start(core_if);
++00728         
++00729         /* Clear interrupt */
++00730         adpctl.d32 = dwc_otg_adp_read_reg(core_if);
++00731         adpctl.b.adp_sns_int = 1;
++00732         dwc_otg_adp_write_reg(core_if, adpctl.d32);
++00733 
++00734         return 0;
++00735 }
++00736 
++00740 static int32_t dwc_otg_adp_handle_prb_tmout_intr(dwc_otg_core_if_t * core_if,
++00741                                                  uint32_t val)
++00742 {
++00743         adpctl_data_t adpctl = {.d32 = 0 };
++00744         adpctl.d32 = val;
++00745         set_timer_value(core_if, adpctl.b.rtim);
++00746         
++00747         /* Clear interrupt */
++00748         adpctl.d32 = dwc_otg_adp_read_reg(core_if);
++00749         adpctl.b.adp_tmout_int = 1;
++00750         dwc_otg_adp_write_reg(core_if, adpctl.d32);
++00751 
++00752         return 0;
++00753 }
++00754 
++00759 int32_t dwc_otg_adp_handle_intr(dwc_otg_core_if_t * core_if)
++00760 {
++00761         int retval = 0;
++00762         adpctl_data_t adpctl = {.d32 = 0};
++00763 
++00764         adpctl.d32 = dwc_otg_adp_read_reg(core_if);
++00765         DWC_PRINTF("ADPCTL = %08x\n",adpctl.d32);
++00766 
++00767         if (adpctl.b.adp_sns_int & adpctl.b.adp_sns_int_msk) {
++00768                 DWC_PRINTF("ADP Sense interrupt\n");
++00769                 retval |= dwc_otg_adp_handle_sns_intr(core_if);
++00770         }
++00771         if (adpctl.b.adp_tmout_int & adpctl.b.adp_tmout_int_msk) {
++00772                 DWC_PRINTF("ADP timeout interrupt\n");
++00773                 retval |= dwc_otg_adp_handle_prb_tmout_intr(core_if, adpctl.d32);
++00774         }
++00775         if (adpctl.b.adp_prb_int & adpctl.b.adp_prb_int_msk) {
++00776                 DWC_PRINTF("ADP Probe interrupt\n");
++00777                 adpctl.b.adp_prb_int = 1;       
++00778                 retval |= dwc_otg_adp_handle_prb_intr(core_if, adpctl.d32);
++00779         }
++00780 
++00781 //      dwc_otg_adp_modify_reg(core_if, adpctl.d32, 0);
++00782         //dwc_otg_adp_write_reg(core_if, adpctl.d32);
++00783         DWC_PRINTF("RETURN FROM ADP ISR\n");
++00784 
++00785         return retval;
++00786 }
++00787 
++00792 int32_t dwc_otg_adp_handle_srp_intr(dwc_otg_core_if_t * core_if)
++00793 {
++00794 
++00795 #ifndef DWC_HOST_ONLY
++00796         hprt0_data_t hprt0;
++00797         gpwrdn_data_t gpwrdn;
++00798         DWC_DEBUGPL(DBG_ANY, "++ Power Down Logic Session Request Interrupt++\n");
++00799 
++00800         gpwrdn.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
++00801         /* check which value is for device mode and which for Host mode */
++00802         if (!gpwrdn.b.idsts) {  /* considered host mode value is 0 */
++00803                 DWC_PRINTF("SRP: Host mode\n");
++00804 
++00805                 if (core_if->adp_enable) {
++00806                         dwc_otg_adp_probe_stop(core_if);
++00807 
++00808                         /* Power on the core */
++00809                         if (core_if->power_down == 2) {
++00810                                 gpwrdn.b.pwrdnswtch = 1;
++00811                                 DWC_MODIFY_REG32(&core_if->core_global_regs->
++00812                                                  gpwrdn, 0, gpwrdn.d32);
++00813                         }
++00814 
++00815                         core_if->op_state = A_HOST;
++00816                         dwc_otg_core_init(core_if);
++00817                         dwc_otg_enable_global_interrupts(core_if);
++00818                         cil_hcd_start(core_if);
++00819                 }
++00820 
++00821                 /* Turn on the port power bit. */
++00822                 hprt0.d32 = dwc_otg_read_hprt0(core_if);
++00823                 hprt0.b.prtpwr = 1;
++00824                 DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
++00825 
++00826                 /* Start the Connection timer. So a message can be displayed
++00827                  * if connect does not occur within 10 seconds. */
++00828                 cil_hcd_session_start(core_if);
++00829         } else {
++00830                 DWC_PRINTF("SRP: Device mode %s\n", __FUNCTION__);
++00831                 if (core_if->adp_enable) {
++00832                         dwc_otg_adp_probe_stop(core_if);
++00833 
++00834                         /* Power on the core */
++00835                         if (core_if->power_down == 2) {
++00836                                 gpwrdn.b.pwrdnswtch = 1;
++00837                                 DWC_MODIFY_REG32(&core_if->core_global_regs->
++00838                                                  gpwrdn, 0, gpwrdn.d32);
++00839                         }
++00840 
++00841                         gpwrdn.d32 = 0;
++00842                         gpwrdn.b.pmuactv = 0;
++00843                         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0,
++00844                                          gpwrdn.d32);
++00845 
++00846                         core_if->op_state = B_PERIPHERAL;
++00847                         dwc_otg_core_init(core_if);
++00848                         dwc_otg_enable_global_interrupts(core_if);
++00849                         cil_pcd_start(core_if);
++00850                 }
++00851         }
++00852 #endif
++00853         return 1;
++00854 }
++
Generated on Thu Oct 27 03:56:37 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.3.9.1
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__adp_8c.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__adp_8c.html 2013-07-26 19:34:39.000000000 +0000 +@@ -0,0 +1,482 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_adp.c File Reference ++ ++ ++ ++
Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
++

dwc_otg_adp.c File Reference

This file contains the most of the Attach Detect Protocol implementation for the driver to support OTG Rev2.0. More... ++

++#include "dwc_os.h"
++#include "dwc_otg_regs.h"
++#include "dwc_otg_cil.h"
++#include "dwc_otg_adp.h"
++ ++

++Go to the source code of this file. ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++

Functions

++void dwc_otg_adp_write_reg (dwc_otg_core_if_t *core_if, uint32_t value)
 Attach Detect Protocol functions.
++uint32_t dwc_otg_adp_read_reg (dwc_otg_core_if_t *core_if)
 Function is called to read ADP registers.
++uint32_t dwc_otg_adp_read_reg_filter (dwc_otg_core_if_t *core_if)
 Function is called to read ADPCTL register and filter Write-clear bits.
++void dwc_otg_adp_modify_reg (dwc_otg_core_if_t *core_if, uint32_t clr, uint32_t set)
 Function is called to write ADP registers.
++void adp_sense_timeout (void *ptr)
void adp_vbuson_timeout (void *ptr)
 This function is called when the ADP vbus timer expires.
void dwc_otg_adp_vbuson_timer_start (dwc_otg_core_if_t *core_if)
 Start the ADP Initial Probe timer to detect if Port Connected interrupt is not asserted within 1.1 seconds.
uint32_t dwc_otg_adp_probe_start (dwc_otg_core_if_t *core_if)
 Starts the ADP Probing.
void dwc_otg_adp_sense_timer_start (dwc_otg_core_if_t *core_if)
 Starts the ADP Sense timer to detect if ADP Sense interrupt is not asserted within 3 seconds.
uint32_t dwc_otg_adp_sense_start (dwc_otg_core_if_t *core_if)
 Starts the ADP Sense.
uint32_t dwc_otg_adp_probe_stop (dwc_otg_core_if_t *core_if)
 Stops the ADP Probing.
uint32_t dwc_otg_adp_sense_stop (dwc_otg_core_if_t *core_if)
 Stops the ADP Sensing.
void dwc_otg_adp_turnon_vbus (dwc_otg_core_if_t *core_if)
 Called to turn on the VBUS after initial ADP probe in host mode.
void dwc_otg_adp_start (dwc_otg_core_if_t *core_if, uint8_t is_host)
 Called right after driver is loaded to perform initial actions for ADP.
++void dwc_otg_adp_init (dwc_otg_core_if_t *core_if)
++void dwc_otg_adp_remove (dwc_otg_core_if_t *core_if)
++uint32_t set_timer_value (dwc_otg_core_if_t *core_if, uint32_t val)
 This function sets Ramp Timer values.
++uint32_t compare_timer_values (dwc_otg_core_if_t *core_if)
 This function compares Ramp Timer values.
++int32_t dwc_otg_adp_handle_prb_intr (dwc_otg_core_if_t *core_if, uint32_t val)
 This function handles ADP Probe Interrupts.
++int32_t dwc_otg_adp_handle_sns_intr (dwc_otg_core_if_t *core_if)
 This function hadles ADP Sense Interrupt.
++int32_t dwc_otg_adp_handle_prb_tmout_intr (dwc_otg_core_if_t *core_if, uint32_t val)
 This function handles ADP Probe Interrupts.
++int32_t dwc_otg_adp_handle_intr (dwc_otg_core_if_t *core_if)
 ADP Interrupt handler.
int32_t dwc_otg_adp_handle_srp_intr (dwc_otg_core_if_t *core_if)
++

Detailed Description

++This file contains the most of the Attach Detect Protocol implementation for the driver to support OTG Rev2.0. ++

++ ++

++Definition in file dwc_otg_adp.c.

Function Documentation

++

++ ++ ++ ++ ++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void adp_vbuson_timeout ( void *  ptr  )  [static]
++
++ ++ ++ ++ ++ ++
++   ++ ++ ++

++This function is called when the ADP vbus timer expires. ++

++Timeout is 1.1s. ++

++Definition at line 119 of file dwc_otg_adp.c.

++

++ ++ ++ ++ ++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_otg_adp_vbuson_timer_start ( dwc_otg_core_if_t *  core_if  ) 
++
++ ++ ++ ++ ++ ++
++   ++ ++ ++

++Start the ADP Initial Probe timer to detect if Port Connected interrupt is not asserted within 1.1 seconds. ++

++

Parameters:
++ ++ ++
core_if the pointer to core_if strucure.
++
++ ++

++Definition at line 187 of file dwc_otg_adp.c.

++

++ ++ ++ ++ ++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
uint32_t dwc_otg_adp_probe_start ( dwc_otg_core_if_t *  core_if  ) 
++
++ ++ ++ ++ ++ ++
++   ++ ++ ++

++Starts the ADP Probing. ++

++

Parameters:
++ ++ ++
core_if the pointer to core_if structure.
++
++ ++

++Definition at line 296 of file dwc_otg_adp.c.

++

++ ++ ++ ++ ++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_otg_adp_sense_timer_start ( dwc_otg_core_if_t *  core_if  ) 
++
++ ++ ++ ++ ++ ++
++   ++ ++ ++

++Starts the ADP Sense timer to detect if ADP Sense interrupt is not asserted within 3 seconds. ++

++

Parameters:
++ ++ ++
core_if the pointer to core_if strucure.
++
++ ++

++Definition at line 346 of file dwc_otg_adp.c.

++

++ ++ ++ ++ ++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
uint32_t dwc_otg_adp_sense_start ( dwc_otg_core_if_t *  core_if  ) 
++
++ ++ ++ ++ ++ ++
++   ++ ++ ++

++Starts the ADP Sense. ++

++

Parameters:
++ ++ ++
core_if the pointer to core_if strucure.
++
++ ++

++Definition at line 357 of file dwc_otg_adp.c.

++

++ ++ ++ ++ ++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
uint32_t dwc_otg_adp_probe_stop ( dwc_otg_core_if_t *  core_if  ) 
++
++ ++ ++ ++ ++ ++
++   ++ ++ ++

++Stops the ADP Probing. ++

++

Parameters:
++ ++ ++
core_if the pointer to core_if strucure.
++
++ ++

++Definition at line 393 of file dwc_otg_adp.c.

++

++ ++ ++ ++ ++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
uint32_t dwc_otg_adp_sense_stop ( dwc_otg_core_if_t *  core_if  ) 
++
++ ++ ++ ++ ++ ++
++   ++ ++ ++

++Stops the ADP Sensing. ++

++

Parameters:
++ ++ ++
core_if the pointer to core_if strucure.
++
++ ++

++Definition at line 416 of file dwc_otg_adp.c.

++

++ ++ ++ ++ ++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_otg_adp_turnon_vbus ( dwc_otg_core_if_t *  core_if  ) 
++
++ ++ ++ ++ ++ ++
++   ++ ++ ++

++Called to turn on the VBUS after initial ADP probe in host mode. ++

++If port power was already enabled in cil_hcd_start function then only schedule a timer.

++

Parameters:
++ ++ ++
core_if the pointer to core_if structure.
++
++ ++

++Definition at line 437 of file dwc_otg_adp.c.

++

++ ++ ++ ++ ++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_otg_adp_start ( dwc_otg_core_if_t *  core_if,
uint8_t  is_host
) 
++
++ ++ ++ ++ ++ ++
++   ++ ++ ++

++Called right after driver is loaded to perform initial actions for ADP. ++

++

Parameters:
++ ++ ++ ++
core_if the pointer to core_if structure.
is_host - flag for current mode of operation either from GINTSTS or GPWRDN
++
++ ++

++Definition at line 458 of file dwc_otg_adp.c.

++

++ ++ ++ ++ ++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int32_t dwc_otg_adp_handle_srp_intr ( dwc_otg_core_if_t *  core_if  ) 
++
++ ++ ++ ++ ++ ++
++   ++ ++ ++

++

Parameters:
++ ++ ++
core_if Programming view of DWC_otg controller.
++
++ ++

++Definition at line 792 of file dwc_otg_adp.c.

++

Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.3.9.1
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__adp_8h-source.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__adp_8h-source.html 2013-07-26 19:34:39.000000000 +0000 +@@ -0,0 +1,80 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_adp.h Source File ++ ++ ++ ++
Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
++

dwc_otg_adp.h

Go to the documentation of this file.
00001 /* ==========================================================================
++00002  * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_adp.h $
++00003  * $Revision: #7 $
++00004  * $Date: 2011/10/24 $
++00005  * $Change: 1871159 $
++00006  *
++00007  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
++00008  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
++00009  * otherwise expressly agreed to in writing between Synopsys and you.
++00010  *
++00011  * The Software IS NOT an item of Licensed Software or Licensed Product under
++00012  * any End User Software License Agreement or Agreement for Licensed Product
++00013  * with Synopsys or any supplement thereto. You are permitted to use and
++00014  * redistribute this Software in source and binary forms, with or without
++00015  * modification, provided that redistributions of source code must retain this
++00016  * notice. You may not view, use, disclose, copy or distribute this file or
++00017  * any information contained herein except pursuant to this license grant from
++00018  * Synopsys. If you do not agree with this notice, including the disclaimer
++00019  * below, then you are not authorized to use the Software.
++00020  *
++00021  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
++00022  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++00023  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++00024  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
++00025  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++00026  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
++00027  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
++00028  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
++00029  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
++00030  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
++00031  * DAMAGE.
++00032  * ========================================================================== */
++00033 
++00034 #ifndef __DWC_OTG_ADP_H__
++00035 #define __DWC_OTG_ADP_H__
++00036 
++00045 #define DWC_OTG_ADP_UNATTACHED  0
++00046 #define DWC_OTG_ADP_ATTACHED    1
++00047 #define DWC_OTG_ADP_UNKOWN      2
++00048 
++00049 typedef struct dwc_otg_adp {
++00050         uint32_t adp_started;   
++00051         uint32_t initial_probe;
++00052         int32_t probe_timer_values[2];
++00053         uint32_t probe_enabled;
++00054         uint32_t sense_enabled;
++00055         dwc_timer_t *sense_timer;
++00056         uint32_t sense_timer_started;
++00057         dwc_timer_t *vbuson_timer;
++00058         uint32_t vbuson_timer_started;
++00059         uint32_t attached;
++00060         uint32_t probe_counter;
++00061         uint32_t gpwrdn;
++00062 } dwc_otg_adp_t;
++00063 
++00068 extern void dwc_otg_adp_write_reg(dwc_otg_core_if_t * core_if, uint32_t value);
++00069 extern uint32_t dwc_otg_adp_read_reg(dwc_otg_core_if_t * core_if);
++00070 extern uint32_t dwc_otg_adp_probe_start(dwc_otg_core_if_t * core_if);
++00071 extern uint32_t dwc_otg_adp_sense_start(dwc_otg_core_if_t * core_if);
++00072 extern uint32_t dwc_otg_adp_probe_stop(dwc_otg_core_if_t * core_if);
++00073 extern uint32_t dwc_otg_adp_sense_stop(dwc_otg_core_if_t * core_if);
++00074 extern void dwc_otg_adp_start(dwc_otg_core_if_t * core_if, uint8_t is_host);
++00075 extern void dwc_otg_adp_init(dwc_otg_core_if_t * core_if);
++00076 extern void dwc_otg_adp_remove(dwc_otg_core_if_t * core_if);
++00077 extern int32_t dwc_otg_adp_handle_intr(dwc_otg_core_if_t * core_if);
++00078 extern int32_t dwc_otg_adp_handle_srp_intr(dwc_otg_core_if_t * core_if);
++00079 
++00080 #endif //__DWC_OTG_ADP_H__
++
Generated on Thu Oct 27 03:56:37 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.3.9.1
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__adp_8h.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__adp_8h.html 2013-07-26 19:34:39.000000000 +0000 +@@ -0,0 +1,308 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_adp.h File Reference ++ ++ ++ ++
Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
++

dwc_otg_adp.h File Reference

This file contains the Attach Detect Protocol interfaces and defines (functions) and structures for Linux. More... ++

++ ++

++Go to the source code of this file. ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++

Data Structures

struct  dwc_otg_adp

Defines

++#define DWC_OTG_ADP_UNATTACHED   0
++#define DWC_OTG_ADP_ATTACHED   1
++#define DWC_OTG_ADP_UNKOWN   2

Typedefs

++typedef dwc_otg_adp dwc_otg_adp_t

Functions

++void dwc_otg_adp_write_reg (dwc_otg_core_if_t *core_if, uint32_t value)
 Attach Detect Protocol functions.
++uint32_t dwc_otg_adp_read_reg (dwc_otg_core_if_t *core_if)
 Function is called to read ADP registers.
uint32_t dwc_otg_adp_probe_start (dwc_otg_core_if_t *core_if)
 Starts the ADP Probing.
uint32_t dwc_otg_adp_sense_start (dwc_otg_core_if_t *core_if)
 Starts the ADP Sense.
uint32_t dwc_otg_adp_probe_stop (dwc_otg_core_if_t *core_if)
 Stops the ADP Probing.
uint32_t dwc_otg_adp_sense_stop (dwc_otg_core_if_t *core_if)
 Stops the ADP Sensing.
void dwc_otg_adp_start (dwc_otg_core_if_t *core_if, uint8_t is_host)
 Called right after driver is loaded to perform initial actions for ADP.
++void dwc_otg_adp_init (dwc_otg_core_if_t *core_if)
++void dwc_otg_adp_remove (dwc_otg_core_if_t *core_if)
++int32_t dwc_otg_adp_handle_intr (dwc_otg_core_if_t *core_if)
 ADP Interrupt handler.
int32_t dwc_otg_adp_handle_srp_intr (dwc_otg_core_if_t *core_if)
++

Detailed Description

++This file contains the Attach Detect Protocol interfaces and defines (functions) and structures for Linux. ++

++ ++

++Definition in file dwc_otg_adp.h.

Function Documentation

++

++ ++ ++ ++ ++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
uint32_t dwc_otg_adp_probe_start ( dwc_otg_core_if_t *  core_if  ) 
++
++ ++ ++ ++ ++ ++
++   ++ ++ ++

++Starts the ADP Probing. ++

++

Parameters:
++ ++ ++
core_if the pointer to core_if structure.
++
++ ++

++Definition at line 296 of file dwc_otg_adp.c.

++

++ ++ ++ ++ ++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
uint32_t dwc_otg_adp_sense_start ( dwc_otg_core_if_t *  core_if  ) 
++
++ ++ ++ ++ ++ ++
++   ++ ++ ++

++Starts the ADP Sense. ++

++

Parameters:
++ ++ ++
core_if the pointer to core_if strucure.
++
++ ++

++Definition at line 357 of file dwc_otg_adp.c.

++

++ ++ ++ ++ ++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
uint32_t dwc_otg_adp_probe_stop ( dwc_otg_core_if_t *  core_if  ) 
++
++ ++ ++ ++ ++ ++
++   ++ ++ ++

++Stops the ADP Probing. ++

++

Parameters:
++ ++ ++
core_if the pointer to core_if strucure.
++
++ ++

++Definition at line 393 of file dwc_otg_adp.c.

++

++ ++ ++ ++ ++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
uint32_t dwc_otg_adp_sense_stop ( dwc_otg_core_if_t *  core_if  ) 
++
++ ++ ++ ++ ++ ++
++   ++ ++ ++

++Stops the ADP Sensing. ++

++

Parameters:
++ ++ ++
core_if the pointer to core_if strucure.
++
++ ++

++Definition at line 416 of file dwc_otg_adp.c.

++

++ ++ ++ ++ ++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
void dwc_otg_adp_start ( dwc_otg_core_if_t *  core_if,
uint8_t  is_host
) 
++
++ ++ ++ ++ ++ ++
++   ++ ++ ++

++Called right after driver is loaded to perform initial actions for ADP. ++

++

Parameters:
++ ++ ++ ++
core_if the pointer to core_if structure.
is_host - flag for current mode of operation either from GINTSTS or GPWRDN
++
++ ++

++Definition at line 458 of file dwc_otg_adp.c.

++

++ ++ ++ ++ ++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++
int32_t dwc_otg_adp_handle_srp_intr ( dwc_otg_core_if_t *  core_if  ) 
++
++ ++ ++ ++ ++ ++
++   ++ ++ ++

++

Parameters:
++ ++ ++
core_if Programming view of DWC_otg controller.
++
++ ++

++Definition at line 792 of file dwc_otg_adp.c.

++

Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.3.9.1
++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__attr_8c-source.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/dwc__otg__attr_8c-source.html 2013-07-26 19:31:20.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__attr_8c-source.html 2013-07-26 19:34:39.000000000 +0000 +@@ -2,827 +2,928 @@ + + DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_attr.c Source File + +- + +- +-
+-
+-
+-
+-

dwc_otg_attr.c

Go to the documentation of this file.
00001 /* ==========================================================================
+-00002  * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_attr.c $
+-00003  * $Revision: #35 $
+-00004  * $Date: 2009/04/03 $
+-00005  * $Change: 1225160 $
+-00006  *
+-00007  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
+-00008  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
+-00009  * otherwise expressly agreed to in writing between Synopsys and you.
+-00010  *
+-00011  * The Software IS NOT an item of Licensed Software or Licensed Product under
+-00012  * any End User Software License Agreement or Agreement for Licensed Product
+-00013  * with Synopsys or any supplement thereto. You are permitted to use and
+-00014  * redistribute this Software in source and binary forms, with or without
+-00015  * modification, provided that redistributions of source code must retain this
+-00016  * notice. You may not view, use, disclose, copy or distribute this file or
+-00017  * any information contained herein except pursuant to this license grant from
+-00018  * Synopsys. If you do not agree with this notice, including the disclaimer
+-00019  * below, then you are not authorized to use the Software.
+-00020  *
+-00021  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
+-00022  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+-00023  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+-00024  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
+-00025  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+-00026  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+-00027  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+-00028  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+-00029  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+-00030  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+-00031  * DAMAGE.
+-00032  * ========================================================================== */
+-00033 
+-00286 #include <linux/kernel.h>
+-00287 #include <linux/module.h>
+-00288 #include <linux/moduleparam.h>
+-00289 #include <linux/init.h>
+-00290 #include <linux/device.h>
+-00291 #include <linux/errno.h>
+-00292 #include <linux/types.h>
+-00293 #include <linux/stat.h>         /* permission constants */
+-00294 #include <linux/version.h>
+-00295 #include <linux/param.h>
+-00296 #include <linux/delay.h>
+-00297 #include <linux/jiffies.h>
+-00298 
+-00299 
+-00300 #ifdef LM_INTERFACE
+-00301 #include <asm/sizes.h>
+-00302 #include <asm/arch/lm.h>
+-00303 #endif
+-00304 
+-00305 #include <asm/io.h>
+-00306 
+-00307 #include "dwc_os.h"
+-00308 #include "dwc_otg_driver.h"
+-00309 #include "dwc_otg_attr.h"
+-00310 #include "dwc_otg_core_if.h"
+-00311 #include "dwc_otg_pcd_if.h"
+-00312 #include "dwc_otg_hcd_if.h"
+-00313 
+-00314 /*
+-00315  * MACROs for defining sysfs attribute
+-00316  */
+-00317 #ifdef LM_INTERFACE
+-00318 
+-00319 #define DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_string_) \
+-00320 static ssize_t _otg_attr_name_##_show (struct device *_dev, struct device_attribute *attr, char *buf) \
+-00321 { \
+-00322         struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev); \
+-00323         dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);             \
+-00324         uint32_t val; \
+-00325         val = dwc_otg_get_##_otg_attr_name_ (otg_dev->core_if); \
+-00326         return sprintf (buf, "%s = 0x%x\n", _string_, val); \
+-00327 }
+-00328 #define DWC_OTG_DEVICE_ATTR_BITFIELD_STORE(_otg_attr_name_,_string_) \
+-00329 static ssize_t _otg_attr_name_##_store (struct device *_dev, struct device_attribute *attr, \
+-00330                                         const char *buf, size_t count) \
+-00331 { \
+-00332         struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev); \
+-00333         dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev); \
+-00334         uint32_t set = simple_strtoul(buf, NULL, 16); \
+-00335         dwc_otg_set_##_otg_attr_name_(otg_dev->core_if, set);\
+-00336         return count; \
+-00337 }
+-00338 
+-00339 #elif PCI_INTERFACE
+-00340 
+-00341 #define DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_string_) \
+-00342 static ssize_t _otg_attr_name_##_show (struct device *_dev, struct device_attribute *attr, char *buf) \
+-00343 { \
+-00344         dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);      \
+-00345         uint32_t val; \
+-00346         val = dwc_otg_get_##_otg_attr_name_ (otg_dev->core_if); \
+-00347         return sprintf (buf, "%s = 0x%x\n", _string_, val); \
+-00348 }
+-00349 #define DWC_OTG_DEVICE_ATTR_BITFIELD_STORE(_otg_attr_name_,_string_) \
+-00350 static ssize_t _otg_attr_name_##_store (struct device *_dev, struct device_attribute *attr, \
+-00351                                         const char *buf, size_t count) \
+-00352 { \
+-00353         dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);  \
+-00354         uint32_t set = simple_strtoul(buf, NULL, 16); \
+-00355         dwc_otg_set_##_otg_attr_name_(otg_dev->core_if, set);\
+-00356         return count; \
+-00357 }
+-00358 
+-00359 #endif
+-00360 
+-00361 /*
+-00362  * MACROs for defining sysfs attribute for 32-bit registers
+-00363  */
+-00364 #ifdef LM_INTERFACE
+-00365 #define DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_string_) \
+-00366 static ssize_t _otg_attr_name_##_show (struct device *_dev, struct device_attribute *attr, char *buf) \
+-00367 { \
+-00368         struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev); \
+-00369         dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev); \
+-00370         uint32_t val; \
+-00371         val = dwc_otg_get_##_otg_attr_name_ (otg_dev->core_if); \
+-00372         return sprintf (buf, "%s = 0x%08x\n", _string_, val); \
+-00373 }
+-00374 #define DWC_OTG_DEVICE_ATTR_REG_STORE(_otg_attr_name_,_string_) \
+-00375 static ssize_t _otg_attr_name_##_store (struct device *_dev, struct device_attribute *attr, \
+-00376                                         const char *buf, size_t count) \
+-00377 { \
+-00378         struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev); \
+-00379         dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev); \
+-00380         uint32_t val = simple_strtoul(buf, NULL, 16); \
+-00381         dwc_otg_set_##_otg_attr_name_ (otg_dev->core_if, val); \
+-00382         return count; \
+-00383 }
+-00384 #elif PCI_INTERFACE
+-00385 #define DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_string_) \
+-00386 static ssize_t _otg_attr_name_##_show (struct device *_dev, struct device_attribute *attr, char *buf) \
+-00387 { \
+-00388         dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);  \
+-00389         uint32_t val; \
+-00390         val = dwc_otg_get_##_otg_attr_name_ (otg_dev->core_if); \
+-00391         return sprintf (buf, "%s = 0x%08x\n", _string_, val); \
+-00392 }
+-00393 #define DWC_OTG_DEVICE_ATTR_REG_STORE(_otg_attr_name_,_string_) \
+-00394 static ssize_t _otg_attr_name_##_store (struct device *_dev, struct device_attribute *attr, \
+-00395                                         const char *buf, size_t count) \
+-00396 { \
+-00397         dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);  \
+-00398         uint32_t val = simple_strtoul(buf, NULL, 16); \
+-00399         dwc_otg_set_##_otg_attr_name_ (otg_dev->core_if, val); \
+-00400         return count; \
+-00401 }
+-00402 
+-00403 #endif
+-00404 
+-00405 #define DWC_OTG_DEVICE_ATTR_BITFIELD_RW(_otg_attr_name_,_string_) \
+-00406 DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_string_) \
+-00407 DWC_OTG_DEVICE_ATTR_BITFIELD_STORE(_otg_attr_name_,_string_) \
+-00408 DEVICE_ATTR(_otg_attr_name_,0644,_otg_attr_name_##_show,_otg_attr_name_##_store);
+-00409 
+-00410 #define DWC_OTG_DEVICE_ATTR_BITFIELD_RO(_otg_attr_name_,_string_) \
+-00411 DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_string_) \
+-00412 DEVICE_ATTR(_otg_attr_name_,0444,_otg_attr_name_##_show,NULL);
+-00413 
+-00414 #define DWC_OTG_DEVICE_ATTR_REG32_RW(_otg_attr_name_,_addr_,_string_) \
+-00415 DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_string_) \
+-00416 DWC_OTG_DEVICE_ATTR_REG_STORE(_otg_attr_name_,_string_) \
+-00417 DEVICE_ATTR(_otg_attr_name_,0644,_otg_attr_name_##_show,_otg_attr_name_##_store);
+-00418 
+-00419 #define DWC_OTG_DEVICE_ATTR_REG32_RO(_otg_attr_name_,_addr_,_string_) \
+-00420 DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_string_) \
+-00421 DEVICE_ATTR(_otg_attr_name_,0444,_otg_attr_name_##_show,NULL);
+-00422 
+-00429 static ssize_t regoffset_show(struct device *_dev,
+-00430                               struct device_attribute *attr, char *buf)
+-00431 {
+-00432 #ifdef LM_INTERFACE
+-00433         struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
+-00434         dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
+-00435 #elif PCI_INTERFACE
+-00436         dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
+-00437 #endif
+-00438 
+-00439         return snprintf(buf, sizeof("0xFFFFFFFF\n") + 1, "0x%08x\n",
+-00440                         otg_dev->reg_offset);
+-00441 }
+-00442 
+-00446 static ssize_t regoffset_store(struct device *_dev,
+-00447                                struct device_attribute *attr,
+-00448                                const char *buf, size_t count)
+-00449 {
+-00450 #ifdef LM_INTERFACE
+-00451         struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
+-00452         dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
+-00453 #elif PCI_INTERFACE
+-00454         dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
+-00455 #endif
+-00456 
+-00457         uint32_t offset = simple_strtoul(buf, NULL, 16);
+-00458 #ifdef LM_INTERFACE
+-00459         if (offset < SZ_256K) {
+-00460 #elif  PCI_INTERFACE
+-00461         if (offset < 0x00040000) {
+-00462 #endif
+-00463                 otg_dev->reg_offset = offset;
+-00464         } else {
+-00465                 dev_err(_dev, "invalid offset\n");
+-00466         }
+-00467 
+-00468         return count;
+-00469 }
+-00470 
+-00471 DEVICE_ATTR(regoffset, S_IRUGO | S_IWUSR, regoffset_show, regoffset_store);
+-00472 
+-00477 static ssize_t regvalue_show(struct device *_dev,
+-00478                              struct device_attribute *attr, char *buf)
+-00479 {
+-00480 #ifdef LM_INTERFACE
+-00481         struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
+-00482         dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
+-00483 #elif PCI_INTERFACE
+-00484         dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
+-00485 #endif
+-00486 
+-00487         uint32_t val;
+-00488         volatile uint32_t *addr;
+-00489 
+-00490         if (otg_dev->reg_offset != 0xFFFFFFFF && 0 != otg_dev->base) {
+-00491                 /* Calculate the address */
+-00492                 addr = (uint32_t *) (otg_dev->reg_offset +
+-00493                                      (uint8_t *) otg_dev->base);
+-00494                 val = dwc_read_reg32(addr);
+-00495                 return snprintf(buf,
+-00496                                 sizeof("Reg@0xFFFFFFFF = 0xFFFFFFFF\n") + 1,
+-00497                                 "Reg@0x%06x = 0x%08x\n", otg_dev->reg_offset,
+-00498                                 val);
+-00499         } else {
+-00500                 dev_err(_dev, "Invalid offset (0x%0x)\n", otg_dev->reg_offset);
+-00501                 return sprintf(buf, "invalid offset\n");
+-00502         }
+-00503 }
+-00504 
+-00510 static ssize_t regvalue_store(struct device *_dev,
+-00511                               struct device_attribute *attr,
+-00512                               const char *buf, size_t count)
+-00513 {
+-00514 #ifdef LM_INTERFACE
+-00515         struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
+-00516         dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
+-00517 #elif PCI_INTERFACE
+-00518         dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
+-00519 #endif
+-00520 
+-00521         volatile uint32_t *addr;
+-00522         uint32_t val = simple_strtoul(buf, NULL, 16);
+-00523         //dev_dbg(_dev, "Offset=0x%08x Val=0x%08x\n", otg_dev->reg_offset, val);
+-00524         if (otg_dev->reg_offset != 0xFFFFFFFF && 0 != otg_dev->base) {
+-00525                 /* Calculate the address */
+-00526                 addr = (uint32_t *) (otg_dev->reg_offset +
+-00527                                      (uint8_t *) otg_dev->base);
+-00528                 dwc_write_reg32(addr, val);
+-00529         } else {
+-00530                 dev_err(_dev, "Invalid Register Offset (0x%08x)\n",
+-00531                         otg_dev->reg_offset);
+-00532         }
+-00533         return count;
+-00534 }
+-00535 
+-00536 DEVICE_ATTR(regvalue, S_IRUGO | S_IWUSR, regvalue_show, regvalue_store);
+-00537 
+-00538 /*
+-00539  * Attributes
+-00540  */
+-00541 DWC_OTG_DEVICE_ATTR_BITFIELD_RO(mode, "Mode");
+-00542 DWC_OTG_DEVICE_ATTR_BITFIELD_RW(hnpcapable, "HNPCapable");
+-00543 DWC_OTG_DEVICE_ATTR_BITFIELD_RW(srpcapable, "Mode");
+-00544 DWC_OTG_DEVICE_ATTR_BITFIELD_RW(hsic_connect, "HSIC Connect");
+-00545 DWC_OTG_DEVICE_ATTR_BITFIELD_RW(inv_sel_hsic, "Invert Select HSIC");
+-00546 
+-00547 //DWC_OTG_DEVICE_ATTR_BITFIELD_RW(buspower,&(otg_dev->core_if->core_global_regs->gotgctl),(1<<8),8,"Mode");
+-00548 //DWC_OTG_DEVICE_ATTR_BITFIELD_RW(bussuspend,&(otg_dev->core_if->core_global_regs->gotgctl),(1<<8),8,"Mode");
+-00549 DWC_OTG_DEVICE_ATTR_BITFIELD_RO(busconnected, "Bus Connected");
+-00550 
+-00551 DWC_OTG_DEVICE_ATTR_REG32_RW(gotgctl, 0, "GOTGCTL");
+-00552 DWC_OTG_DEVICE_ATTR_REG32_RW(gusbcfg,
+-00553                              &(otg_dev->core_if->core_global_regs->gusbcfg),
+-00554                              "GUSBCFG");
+-00555 DWC_OTG_DEVICE_ATTR_REG32_RW(grxfsiz,
+-00556                              &(otg_dev->core_if->core_global_regs->grxfsiz),
+-00557                              "GRXFSIZ");
+-00558 DWC_OTG_DEVICE_ATTR_REG32_RW(gnptxfsiz,
+-00559                              &(otg_dev->core_if->core_global_regs->gnptxfsiz),
+-00560                              "GNPTXFSIZ");
+-00561 DWC_OTG_DEVICE_ATTR_REG32_RW(gpvndctl,
+-00562                              &(otg_dev->core_if->core_global_regs->gpvndctl),
+-00563                              "GPVNDCTL");
+-00564 DWC_OTG_DEVICE_ATTR_REG32_RW(ggpio,
+-00565                              &(otg_dev->core_if->core_global_regs->ggpio),
+-00566                              "GGPIO");
+-00567 DWC_OTG_DEVICE_ATTR_REG32_RW(guid, &(otg_dev->core_if->core_global_regs->guid),
+-00568                              "GUID");
+-00569 DWC_OTG_DEVICE_ATTR_REG32_RO(gsnpsid,
+-00570                              &(otg_dev->core_if->core_global_regs->gsnpsid),
+-00571                              "GSNPSID");
+-00572 DWC_OTG_DEVICE_ATTR_BITFIELD_RW(devspeed, "Device Speed");
+-00573 DWC_OTG_DEVICE_ATTR_BITFIELD_RO(enumspeed, "Device Enumeration Speed");
+-00574 
+-00575 DWC_OTG_DEVICE_ATTR_REG32_RO(hptxfsiz,
+-00576                              &(otg_dev->core_if->core_global_regs->hptxfsiz),
+-00577                              "HPTXFSIZ");
+-00578 DWC_OTG_DEVICE_ATTR_REG32_RW(hprt0, otg_dev->core_if->host_if->hprt0, "HPRT0");
+-00579 
+-00586 static ssize_t hnp_show(struct device *_dev,
+-00587                         struct device_attribute *attr, char *buf)
+-00588 {
+-00589 #ifdef LM_INTERFACE
+-00590         struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
+-00591         dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
+-00592 #elif PCI_INTERFACE
+-00593         dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
+-00594 #endif
+-00595         return sprintf(buf, "HstNegScs = 0x%x\n",
+-00596                        dwc_otg_get_hnpstatus(otg_dev->core_if));
+-00597 }
+-00598 
+-00602 static ssize_t hnp_store(struct device *_dev,
+-00603                          struct device_attribute *attr,
+-00604                          const char *buf, size_t count)
+-00605 {
+-00606 #ifdef LM_INTERFACE
+-00607         struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
+-00608         dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
+-00609 #elif PCI_INTERFACE
+-00610         dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
+-00611 #endif
+-00612         uint32_t in = simple_strtoul(buf, NULL, 16);
+-00613         dwc_otg_set_hnpreq(otg_dev->core_if, in);
+-00614         return count;
+-00615 }
+-00616 
+-00617 DEVICE_ATTR(hnp, 0644, hnp_show, hnp_store);
+-00618 
+-00625 static ssize_t srp_show(struct device *_dev,
+-00626                         struct device_attribute *attr, char *buf)
+-00627 {
+-00628 #ifndef DWC_HOST_ONLY
+-00629 #ifdef LM_INTERFACE
+-00630         struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
+-00631         dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
+-00632 #elif PCI_INTERFACE
+-00633         dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
+-00634 #endif
+-00635         return sprintf(buf, "SesReqScs = 0x%x\n",
+-00636                        dwc_otg_get_srpstatus(otg_dev->core_if));
+-00637 #else
+-00638         return sprintf(buf, "Host Only Mode!\n");
+-00639 #endif
+-00640 }
+-00641 
+-00645 static ssize_t srp_store(struct device *_dev,
+-00646                          struct device_attribute *attr,
+-00647                          const char *buf, size_t count)
+-00648 {
+-00649 #ifndef DWC_HOST_ONLY
+-00650 #ifdef LM_INTERFACE
+-00651         struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
+-00652         dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
+-00653 #elif PCI_INTERFACE
+-00654         dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
+-00655 #endif
+-00656         dwc_otg_pcd_initiate_srp(otg_dev->pcd);
+-00657 #endif
+-00658         return count;
+-00659 }
+-00660 
+-00661 DEVICE_ATTR(srp, 0644, srp_show, srp_store);
+-00662 
+-00669 static ssize_t buspower_show(struct device *_dev,
+-00670                              struct device_attribute *attr, char *buf)
+-00671 {
+-00672 #ifdef LM_INTERFACE
+-00673         struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
+-00674         dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
+-00675 #elif PCI_INTERFACE
+-00676         dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
+-00677 #endif
+-00678         return sprintf(buf, "Bus Power = 0x%x\n",
+-00679                        dwc_otg_get_prtpower(otg_dev->core_if));
+-00680 }
+-00681 
+-00685 static ssize_t buspower_store(struct device *_dev,
+-00686                               struct device_attribute *attr,
+-00687                               const char *buf, size_t count)
+-00688 {
+-00689 #ifdef LM_INTERFACE
+-00690         struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
+-00691         dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
+-00692 #elif PCI_INTERFACE
+-00693         dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
+-00694 #endif
+-00695         uint32_t on = simple_strtoul(buf, NULL, 16);
+-00696         dwc_otg_set_prtpower(otg_dev->core_if, on);
+-00697         return count;
+-00698 }
+-00699 
+-00700 DEVICE_ATTR(buspower, 0644, buspower_show, buspower_store);
+-00701 
+-00708 static ssize_t bussuspend_show(struct device *_dev,
+-00709                                struct device_attribute *attr, char *buf)
+-00710 {
+-00711 #ifdef LM_INTERFACE
+-00712         struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
+-00713         dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
+-00714 #elif PCI_INTERFACE
+-00715         dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
+-00716 #endif
+-00717 
+-00718         return sprintf(buf, "Bus Suspend = 0x%x\n",
+-00719                        dwc_otg_get_prtsuspend(otg_dev->core_if));
+-00720 }
+-00721 
+-00725 static ssize_t bussuspend_store(struct device *_dev,
+-00726                                 struct device_attribute *attr,
+-00727                                 const char *buf, size_t count)
+-00728 {
+-00729 #ifdef LM_INTERFACE
+-00730         struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
+-00731         dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
+-00732 #elif PCI_INTERFACE
+-00733         dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
+-00734 #endif
+-00735 
+-00736         uint32_t in = simple_strtoul(buf, NULL, 16);
+-00737         dwc_otg_set_prtsuspend(otg_dev->core_if, in);
+-00738         return count;
+-00739 }
+-00740 
+-00741 DEVICE_ATTR(bussuspend, 0644, bussuspend_show, bussuspend_store);
+-00742 
+-00746 static ssize_t remote_wakeup_show(struct device *_dev,
+-00747                                   struct device_attribute *attr, char *buf)
+-00748 {
+-00749 #ifndef DWC_HOST_ONLY
+-00750 #ifdef LM_INTERFACE
+-00751         struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
+-00752         dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
+-00753 #elif PCI_INTERFACE
+-00754         dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
+-00755 #endif
+-00756 
+-00757         return sprintf(buf,
+-00758                        "Remote Wakeup Sig = %d Enabled = %d LPM Remote Wakeup = %d\n",
+-00759                        dwc_otg_get_remotewakesig(otg_dev->core_if),
+-00760                        dwc_otg_pcd_get_rmwkup_enable(otg_dev->pcd),
+-00761                        dwc_otg_get_lpm_remotewakeenabled(otg_dev->core_if));
+-00762 #else
+-00763         return sprintf(buf, "Host Only Mode!\n");
+-00764 #endif /* DWC_HOST_ONLY */
+-00765 }
+-00766 
+-00773 static ssize_t remote_wakeup_store(struct device *_dev,
+-00774                                    struct device_attribute *attr,
+-00775                                    const char *buf, size_t count)
+-00776 {
+-00777 #ifndef DWC_HOST_ONLY
+-00778 #ifdef LM_INTERFACE
+-00779         struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
+-00780         dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
+-00781 #elif PCI_INTERFACE
+-00782         dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
+-00783 #endif
+-00784 
+-00785         uint32_t val = simple_strtoul(buf, NULL, 16);
+-00786 
+-00787         if (val & 1) {
+-00788                 dwc_otg_pcd_remote_wakeup(otg_dev->pcd, 1);
+-00789         } else {
+-00790                 dwc_otg_pcd_remote_wakeup(otg_dev->pcd, 0);
+-00791         }
+-00792 #endif /* DWC_HOST_ONLY */
+-00793         return count;
+-00794 }
+-00795 
+-00796 DEVICE_ATTR(remote_wakeup, S_IRUGO | S_IWUSR, remote_wakeup_show,
+-00797             remote_wakeup_store);
+-00798 
+-00803 static ssize_t regdump_show(struct device *_dev,
+-00804                             struct device_attribute *attr, char *buf)
+-00805 {
+-00806 #ifdef LM_INTERFACE
+-00807         struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
+-00808         dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
+-00809 #elif PCI_INTERFACE
+-00810         dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
+-00811 #endif
+-00812 
+-00813         dwc_otg_dump_global_registers(otg_dev->core_if);
+-00814         if (dwc_otg_is_host_mode(otg_dev->core_if)) {
+-00815                 dwc_otg_dump_host_registers(otg_dev->core_if);
+-00816         } else {
+-00817                 dwc_otg_dump_dev_registers(otg_dev->core_if);
+-00818 
+-00819         }
+-00820         return sprintf(buf, "Register Dump\n");
+-00821 }
+-00822 
+-00823 DEVICE_ATTR(regdump, S_IRUGO | S_IWUSR, regdump_show, 0);
+-00824 
+-00829 static ssize_t spramdump_show(struct device *_dev,
+-00830                               struct device_attribute *attr, char *buf)
+-00831 {
+-00832 #ifdef LM_INTERFACE
+-00833         struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
+-00834         dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
+-00835 #elif PCI_INTERFACE
+-00836         dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
+-00837 #endif
+-00838 
+-00839         dwc_otg_dump_spram(otg_dev->core_if);
+-00840 
+-00841         return sprintf(buf, "SPRAM Dump\n");
+-00842 }
+-00843 
+-00844 DEVICE_ATTR(spramdump, S_IRUGO | S_IWUSR, spramdump_show, 0);
+-00845 
+-00849 static ssize_t hcddump_show(struct device *_dev,
+-00850                             struct device_attribute *attr, char *buf)
+-00851 {
+-00852 #ifndef DWC_DEVICE_ONLY
+-00853 #ifdef LM_INTERFACE
+-00854         struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
+-00855         dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
+-00856 #elif PCI_INTERFACE
+-00857         dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
+-00858 #endif
+-00859 
+-00860         dwc_otg_hcd_dump_state(otg_dev->hcd);
+-00861 #endif /* DWC_DEVICE_ONLY */
+-00862         return sprintf(buf, "HCD Dump\n");
+-00863 }
+-00864 
+-00865 DEVICE_ATTR(hcddump, S_IRUGO | S_IWUSR, hcddump_show, 0);
+-00866 
+-00872 static ssize_t hcd_frrem_show(struct device *_dev,
+-00873                               struct device_attribute *attr, char *buf)
+-00874 {
+-00875 #ifndef DWC_DEVICE_ONLY
+-00876 #ifdef LM_INTERFACE
+-00877         struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
+-00878         dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
+-00879 #elif PCI_INTERFACE
+-00880         dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
+-00881 #endif
+-00882 
+-00883         dwc_otg_hcd_dump_frrem(otg_dev->hcd);
+-00884 #endif /* DWC_DEVICE_ONLY */
+-00885         return sprintf(buf, "HCD Dump Frame Remaining\n");
+-00886 }
+-00887 
+-00888 DEVICE_ATTR(hcd_frrem, S_IRUGO | S_IWUSR, hcd_frrem_show, 0);
+-00889 
+-00894 #define RW_REG_COUNT 10000000
+-00895 #define MSEC_PER_JIFFIE 1000/HZ
+-00896 static ssize_t rd_reg_test_show(struct device *_dev,
+-00897                                 struct device_attribute *attr, char *buf)
+-00898 {
+-00899 #ifdef LM_INTERFACE
+-00900         struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
+-00901         dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
+-00902 #elif PCI_INTERFACE
+-00903         dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
+-00904 #endif
+-00905 
+-00906         int i;
+-00907         int time;
+-00908         int start_jiffies;
+-00909 
+-00910         printk("HZ %d, MSEC_PER_JIFFIE %d, loops_per_jiffy %lu\n",
+-00911                HZ, MSEC_PER_JIFFIE, loops_per_jiffy);
+-00912         start_jiffies = jiffies;
+-00913         for (i = 0; i < RW_REG_COUNT; i++) {
+-00914                 dwc_otg_get_gnptxfsiz(otg_dev->core_if);
+-00915         }
+-00916         time = jiffies - start_jiffies;
+-00917         return sprintf(buf,
+-00918                        "Time to read GNPTXFSIZ reg %d times: %d msecs (%d jiffies)\n",
+-00919                        RW_REG_COUNT, time * MSEC_PER_JIFFIE, time);
+-00920 }
+-00921 
+-00922 DEVICE_ATTR(rd_reg_test, S_IRUGO | S_IWUSR, rd_reg_test_show, 0);
+-00923 
+-00928 static ssize_t wr_reg_test_show(struct device *_dev,
+-00929                                 struct device_attribute *attr, char *buf)
+-00930 {
+-00931 #ifdef LM_INTERFACE
+-00932         struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
+-00933         dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
+-00934 #elif PCI_INTERFACE
+-00935         dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
+-00936 #endif
+-00937 
+-00938         uint32_t reg_val;
+-00939         int i;
+-00940         int time;
+-00941         int start_jiffies;
+-00942 
+-00943         printk("HZ %d, MSEC_PER_JIFFIE %d, loops_per_jiffy %lu\n",
+-00944                HZ, MSEC_PER_JIFFIE, loops_per_jiffy);
+-00945         reg_val = dwc_otg_get_gnptxfsiz(otg_dev->core_if);
+-00946         start_jiffies = jiffies;
+-00947         for (i = 0; i < RW_REG_COUNT; i++) {
+-00948                 dwc_otg_set_gnptxfsiz(otg_dev->core_if, reg_val);
+-00949         }
+-00950         time = jiffies - start_jiffies;
+-00951         return sprintf(buf,
+-00952                        "Time to write GNPTXFSIZ reg %d times: %d msecs (%d jiffies)\n",
+-00953                        RW_REG_COUNT, time * MSEC_PER_JIFFIE, time);
+-00954 }
+-00955 
+-00956 DEVICE_ATTR(wr_reg_test, S_IRUGO | S_IWUSR, wr_reg_test_show, 0);
+-00957 
+-00958 #ifdef CONFIG_USB_DWC_OTG_LPM
+-00959 
+-00963 static ssize_t lpmresp_show(struct device *_dev,
+-00964                             struct device_attribute *attr, char *buf)
+-00965 {
+-00966 #ifdef LM_INTERFACE
+-00967         struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
+-00968         dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
+-00969 #elif PCI_INTERFACE
+-00970         dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
+-00971 #endif
+-00972 
+-00973         if (!dwc_otg_get_param_lpm_enable(otg_dev->core_if))
+-00974                 return sprintf(buf, "** LPM is DISABLED **\n");
+-00975 
+-00976         if (!dwc_otg_is_device_mode(otg_dev->core_if)) {
+-00977                 return sprintf(buf, "** Current mode is not device mode\n");
+-00978         }
+-00979         return sprintf(buf, "lpm_response = %d\n",
+-00980                        dwc_otg_get_lpmresponse(otg_dev->core_if));
+-00981 }
+-00982 
+-00986 static ssize_t lpmresp_store(struct device *_dev,
+-00987                              struct device_attribute *attr,
+-00988                              const char *buf, size_t count)
+-00989 {
+-00990 #ifdef LM_INTERFACE
+-00991         struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
+-00992         dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
+-00993 #elif PCI_INTERFACE
+-00994         dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
+-00995 #endif
+-00996 
+-00997         uint32_t val = simple_strtoul(buf, NULL, 16);
+-00998 
+-00999         if (!dwc_otg_get_param_lpm_enable(otg_dev->core_if)) {
+-01000                 return 0;
+-01001         }
+-01002 
+-01003         if (!dwc_otg_is_device_mode(otg_dev->core_if)) {
+-01004                 return 0;
+-01005         }
+-01006 
+-01007         dwc_otg_set_lpmresponse(otg_dev->core_if, val);
+-01008         return count;
+-01009 }
+-01010 
+-01011 DEVICE_ATTR(lpm_response, S_IRUGO | S_IWUSR, lpmresp_show, lpmresp_store);
+-01012 
+-01016 static ssize_t sleepstatus_show(struct device *_dev,
+-01017                                 struct device_attribute *attr, char *buf)
+-01018 {
+-01019 #ifdef LM_INTERFACE
+-01020         struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
+-01021         dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
+-01022 #elif PCI_INTERFACE
+-01023         dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
+-01024 #endif
+-01025 
+-01026 
+-01027         return sprintf(buf, "Sleep Status = %d\n",
+-01028                        dwc_otg_get_lpm_portsleepstatus(otg_dev->core_if));
+-01029 }
+-01030 
+-01034 static ssize_t sleepstatus_store(struct device *_dev,
+-01035                                  struct device_attribute *attr,
+-01036                                  const char *buf, size_t count)
+-01037 {
+-01038 #ifdef LM_INTERFACE
+-01039         struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
+-01040         dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
+-01041 #elif PCI_INTERFACE
+-01042         dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
+-01043 #endif
+-01044 
+-01045         dwc_otg_core_if_t *core_if = otg_dev->core_if;
+-01046 
+-01047         if (dwc_otg_get_lpm_portsleepstatus(otg_dev->core_if)) {
+-01048                 if (dwc_otg_is_host_mode(core_if)) {
+-01049 
+-01050                         DWC_PRINTF("Host initiated resume\n");
+-01051                         dwc_otg_set_prtresume(otg_dev->core_if, 1);
+-01052                 }
+-01053         }
+-01054 
+-01055         return count;
+-01056 }
+-01057 
+-01058 DEVICE_ATTR(sleep_status, S_IRUGO | S_IWUSR, sleepstatus_show,
+-01059             sleepstatus_store);
+-01060 
+-01061 #endif                          /* CONFIG_USB_DWC_OTG_LPM_ENABLE */
+-01062 
+-01068 void dwc_otg_attr_create (
+-01069 #ifdef LM_INTERFACE
+-01070         struct lm_device *dev
+-01071 #elif  PCI_INTERFACE
+-01072         struct pci_dev *dev
+-01073 #endif
+-01074         )
+-01075 
+-01076 {
+-01077         int error;
+-01078 
+-01079         error = device_create_file(&dev->dev, &dev_attr_regoffset);
+-01080         error = device_create_file(&dev->dev, &dev_attr_regvalue);
+-01081         error = device_create_file(&dev->dev, &dev_attr_mode);
+-01082         error = device_create_file(&dev->dev, &dev_attr_hnpcapable);
+-01083         error = device_create_file(&dev->dev, &dev_attr_srpcapable);
+-01084         error = device_create_file(&dev->dev, &dev_attr_hsic_connect);
+-01085         error = device_create_file(&dev->dev, &dev_attr_inv_sel_hsic);
+-01086         error = device_create_file(&dev->dev, &dev_attr_hnp);
+-01087         error = device_create_file(&dev->dev, &dev_attr_srp);
+-01088         error = device_create_file(&dev->dev, &dev_attr_buspower);
+-01089         error = device_create_file(&dev->dev, &dev_attr_bussuspend);
+-01090         error = device_create_file(&dev->dev, &dev_attr_busconnected);
+-01091         error = device_create_file(&dev->dev, &dev_attr_gotgctl);
+-01092         error = device_create_file(&dev->dev, &dev_attr_gusbcfg);
+-01093         error = device_create_file(&dev->dev, &dev_attr_grxfsiz);
+-01094         error = device_create_file(&dev->dev, &dev_attr_gnptxfsiz);
+-01095         error = device_create_file(&dev->dev, &dev_attr_gpvndctl);
+-01096         error = device_create_file(&dev->dev, &dev_attr_ggpio);
+-01097         error = device_create_file(&dev->dev, &dev_attr_guid);
+-01098         error = device_create_file(&dev->dev, &dev_attr_gsnpsid);
+-01099         error = device_create_file(&dev->dev, &dev_attr_devspeed);
+-01100         error = device_create_file(&dev->dev, &dev_attr_enumspeed);
+-01101         error = device_create_file(&dev->dev, &dev_attr_hptxfsiz);
+-01102         error = device_create_file(&dev->dev, &dev_attr_hprt0);
+-01103         error = device_create_file(&dev->dev, &dev_attr_remote_wakeup);
+-01104         error = device_create_file(&dev->dev, &dev_attr_regdump);
+-01105         error = device_create_file(&dev->dev, &dev_attr_spramdump);
+-01106         error = device_create_file(&dev->dev, &dev_attr_hcddump);
+-01107         error = device_create_file(&dev->dev, &dev_attr_hcd_frrem);
+-01108         error = device_create_file(&dev->dev, &dev_attr_rd_reg_test);
+-01109         error = device_create_file(&dev->dev, &dev_attr_wr_reg_test);
+-01110 #ifdef CONFIG_USB_DWC_OTG_LPM
+-01111         error = device_create_file(&dev->dev, &dev_attr_lpm_response);
+-01112         error = device_create_file(&dev->dev, &dev_attr_sleep_status);
+-01113 #endif
+-01114 }
+-01115 
+-01119 void dwc_otg_attr_remove (
+-01120 #ifdef LM_INTERFACE
+-01121         struct lm_device *dev
+-01122 #elif  PCI_INTERFACE
+-01123         struct pci_dev *dev
+-01124 #endif
+-01125        )
+-01126 
+-01127 {
+-01128         device_remove_file(&dev->dev, &dev_attr_regoffset);
+-01129         device_remove_file(&dev->dev, &dev_attr_regvalue);
+-01130         device_remove_file(&dev->dev, &dev_attr_mode);
+-01131         device_remove_file(&dev->dev, &dev_attr_hnpcapable);
+-01132         device_remove_file(&dev->dev, &dev_attr_srpcapable);
+-01133         device_remove_file(&dev->dev, &dev_attr_hsic_connect);
+-01134         device_remove_file(&dev->dev, &dev_attr_inv_sel_hsic);
+-01135         device_remove_file(&dev->dev, &dev_attr_hnp);
+-01136         device_remove_file(&dev->dev, &dev_attr_srp);
+-01137         device_remove_file(&dev->dev, &dev_attr_buspower);
+-01138         device_remove_file(&dev->dev, &dev_attr_bussuspend);
+-01139         device_remove_file(&dev->dev, &dev_attr_busconnected);
+-01140         device_remove_file(&dev->dev, &dev_attr_gotgctl);
+-01141         device_remove_file(&dev->dev, &dev_attr_gusbcfg);
+-01142         device_remove_file(&dev->dev, &dev_attr_grxfsiz);
+-01143         device_remove_file(&dev->dev, &dev_attr_gnptxfsiz);
+-01144         device_remove_file(&dev->dev, &dev_attr_gpvndctl);
+-01145         device_remove_file(&dev->dev, &dev_attr_ggpio);
+-01146         device_remove_file(&dev->dev, &dev_attr_guid);
+-01147         device_remove_file(&dev->dev, &dev_attr_gsnpsid);
+-01148         device_remove_file(&dev->dev, &dev_attr_devspeed);
+-01149         device_remove_file(&dev->dev, &dev_attr_enumspeed);
+-01150         device_remove_file(&dev->dev, &dev_attr_hptxfsiz);
+-01151         device_remove_file(&dev->dev, &dev_attr_hprt0);
+-01152         device_remove_file(&dev->dev, &dev_attr_remote_wakeup);
+-01153         device_remove_file(&dev->dev, &dev_attr_regdump);
+-01154         device_remove_file(&dev->dev, &dev_attr_spramdump);
+-01155         device_remove_file(&dev->dev, &dev_attr_hcddump);
+-01156         device_remove_file(&dev->dev, &dev_attr_hcd_frrem);
+-01157         device_remove_file(&dev->dev, &dev_attr_rd_reg_test);
+-01158         device_remove_file(&dev->dev, &dev_attr_wr_reg_test);
+-01159 #ifdef CONFIG_USB_DWC_OTG_LPM
+-01160         device_remove_file(&dev->dev, &dev_attr_lpm_response);
+-01161         device_remove_file(&dev->dev, &dev_attr_sleep_status);
+-01162 #endif
+-01163 }
+-
Generated on Tue May 5 02:22:48 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++
Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
++

dwc_otg_attr.c

Go to the documentation of this file.
00001 /* ==========================================================================
++00002  * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_attr.c $
++00003  * $Revision: #44 $
++00004  * $Date: 2010/11/29 $
++00005  * $Change: 1636033 $
++00006  *
++00007  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
++00008  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
++00009  * otherwise expressly agreed to in writing between Synopsys and you.
++00010  *
++00011  * The Software IS NOT an item of Licensed Software or Licensed Product under
++00012  * any End User Software License Agreement or Agreement for Licensed Product
++00013  * with Synopsys or any supplement thereto. You are permitted to use and
++00014  * redistribute this Software in source and binary forms, with or without
++00015  * modification, provided that redistributions of source code must retain this
++00016  * notice. You may not view, use, disclose, copy or distribute this file or
++00017  * any information contained herein except pursuant to this license grant from
++00018  * Synopsys. If you do not agree with this notice, including the disclaimer
++00019  * below, then you are not authorized to use the Software.
++00020  *
++00021  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
++00022  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++00023  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++00024  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
++00025  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++00026  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
++00027  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
++00028  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
++00029  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
++00030  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
++00031  * DAMAGE.
++00032  * ========================================================================== */
++00033 
++00311 #include "dwc_otg_os_dep.h"
++00312 #include "dwc_os.h"
++00313 #include "dwc_otg_driver.h"
++00314 #include "dwc_otg_attr.h"
++00315 #include "dwc_otg_core_if.h"
++00316 #include "dwc_otg_pcd_if.h"
++00317 #include "dwc_otg_hcd_if.h"
++00318 
++00319 /*
++00320  * MACROs for defining sysfs attribute
++00321  */
++00322 #ifdef LM_INTERFACE
++00323 
++00324 #define DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_string_) \
++00325 static ssize_t _otg_attr_name_##_show (struct device *_dev, struct device_attribute *attr, char *buf) \
++00326 { \
++00327         struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev); \
++00328         dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);             \
++00329         uint32_t val; \
++00330         val = dwc_otg_get_##_otg_attr_name_ (otg_dev->core_if); \
++00331         return sprintf (buf, "%s = 0x%x\n", _string_, val); \
++00332 }
++00333 #define DWC_OTG_DEVICE_ATTR_BITFIELD_STORE(_otg_attr_name_,_string_) \
++00334 static ssize_t _otg_attr_name_##_store (struct device *_dev, struct device_attribute *attr, \
++00335                                         const char *buf, size_t count) \
++00336 { \
++00337         struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev); \
++00338         dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev); \
++00339         uint32_t set = simple_strtoul(buf, NULL, 16); \
++00340         dwc_otg_set_##_otg_attr_name_(otg_dev->core_if, set);\
++00341         return count; \
++00342 }
++00343 
++00344 #elif defined(PCI_INTERFACE)
++00345 
++00346 #define DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_string_) \
++00347 static ssize_t _otg_attr_name_##_show (struct device *_dev, struct device_attribute *attr, char *buf) \
++00348 { \
++00349         dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);      \
++00350         uint32_t val; \
++00351         val = dwc_otg_get_##_otg_attr_name_ (otg_dev->core_if); \
++00352         return sprintf (buf, "%s = 0x%x\n", _string_, val); \
++00353 }
++00354 #define DWC_OTG_DEVICE_ATTR_BITFIELD_STORE(_otg_attr_name_,_string_) \
++00355 static ssize_t _otg_attr_name_##_store (struct device *_dev, struct device_attribute *attr, \
++00356                                         const char *buf, size_t count) \
++00357 { \
++00358         dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);  \
++00359         uint32_t set = simple_strtoul(buf, NULL, 16); \
++00360         dwc_otg_set_##_otg_attr_name_(otg_dev->core_if, set);\
++00361         return count; \
++00362 }
++00363 
++00364 #endif
++00365 
++00366 /*
++00367  * MACROs for defining sysfs attribute for 32-bit registers
++00368  */
++00369 #ifdef LM_INTERFACE
++00370 #define DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_string_) \
++00371 static ssize_t _otg_attr_name_##_show (struct device *_dev, struct device_attribute *attr, char *buf) \
++00372 { \
++00373         struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev); \
++00374         dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev); \
++00375         uint32_t val; \
++00376         val = dwc_otg_get_##_otg_attr_name_ (otg_dev->core_if); \
++00377         return sprintf (buf, "%s = 0x%08x\n", _string_, val); \
++00378 }
++00379 #define DWC_OTG_DEVICE_ATTR_REG_STORE(_otg_attr_name_,_string_) \
++00380 static ssize_t _otg_attr_name_##_store (struct device *_dev, struct device_attribute *attr, \
++00381                                         const char *buf, size_t count) \
++00382 { \
++00383         struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev); \
++00384         dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev); \
++00385         uint32_t val = simple_strtoul(buf, NULL, 16); \
++00386         dwc_otg_set_##_otg_attr_name_ (otg_dev->core_if, val); \
++00387         return count; \
++00388 }
++00389 #elif defined(PCI_INTERFACE)
++00390 #define DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_string_) \
++00391 static ssize_t _otg_attr_name_##_show (struct device *_dev, struct device_attribute *attr, char *buf) \
++00392 { \
++00393         dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);  \
++00394         uint32_t val; \
++00395         val = dwc_otg_get_##_otg_attr_name_ (otg_dev->core_if); \
++00396         return sprintf (buf, "%s = 0x%08x\n", _string_, val); \
++00397 }
++00398 #define DWC_OTG_DEVICE_ATTR_REG_STORE(_otg_attr_name_,_string_) \
++00399 static ssize_t _otg_attr_name_##_store (struct device *_dev, struct device_attribute *attr, \
++00400                                         const char *buf, size_t count) \
++00401 { \
++00402         dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);  \
++00403         uint32_t val = simple_strtoul(buf, NULL, 16); \
++00404         dwc_otg_set_##_otg_attr_name_ (otg_dev->core_if, val); \
++00405         return count; \
++00406 }
++00407 
++00408 #endif
++00409 
++00410 #define DWC_OTG_DEVICE_ATTR_BITFIELD_RW(_otg_attr_name_,_string_) \
++00411 DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_string_) \
++00412 DWC_OTG_DEVICE_ATTR_BITFIELD_STORE(_otg_attr_name_,_string_) \
++00413 DEVICE_ATTR(_otg_attr_name_,0644,_otg_attr_name_##_show,_otg_attr_name_##_store);
++00414 
++00415 #define DWC_OTG_DEVICE_ATTR_BITFIELD_RO(_otg_attr_name_,_string_) \
++00416 DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_string_) \
++00417 DEVICE_ATTR(_otg_attr_name_,0444,_otg_attr_name_##_show,NULL);
++00418 
++00419 #define DWC_OTG_DEVICE_ATTR_REG32_RW(_otg_attr_name_,_addr_,_string_) \
++00420 DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_string_) \
++00421 DWC_OTG_DEVICE_ATTR_REG_STORE(_otg_attr_name_,_string_) \
++00422 DEVICE_ATTR(_otg_attr_name_,0644,_otg_attr_name_##_show,_otg_attr_name_##_store);
++00423 
++00424 #define DWC_OTG_DEVICE_ATTR_REG32_RO(_otg_attr_name_,_addr_,_string_) \
++00425 DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_string_) \
++00426 DEVICE_ATTR(_otg_attr_name_,0444,_otg_attr_name_##_show,NULL);
++00427 
++00434 static ssize_t regoffset_show(struct device *_dev,
++00435                               struct device_attribute *attr, char *buf)
++00436 {
++00437 #ifdef LM_INTERFACE
++00438         struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
++00439         dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
++00440 #elif defined(PCI_INTERFACE)
++00441         dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
++00442 #endif
++00443 
++00444         return snprintf(buf, sizeof("0xFFFFFFFF\n") + 1, "0x%08x\n",
++00445                         otg_dev->os_dep.reg_offset);
++00446 }
++00447 
++00451 static ssize_t regoffset_store(struct device *_dev,
++00452                                struct device_attribute *attr,
++00453                                const char *buf, size_t count)
++00454 {
++00455 #ifdef LM_INTERFACE
++00456         struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
++00457         dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
++00458 #elif defined(PCI_INTERFACE)
++00459         dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
++00460 #endif
++00461 
++00462         uint32_t offset = simple_strtoul(buf, NULL, 16);
++00463 #ifdef LM_INTERFACE
++00464         if (offset < SZ_256K) {
++00465 #elif  defined(PCI_INTERFACE)
++00466         if (offset < 0x00040000) {
++00467 #endif
++00468                 otg_dev->os_dep.reg_offset = offset;
++00469         } else {
++00470                 dev_err(_dev, "invalid offset\n");
++00471         }
++00472 
++00473         return count;
++00474 }
++00475 
++00476 DEVICE_ATTR(regoffset, S_IRUGO | S_IWUSR, regoffset_show, regoffset_store);
++00477 
++00482 static ssize_t regvalue_show(struct device *_dev,
++00483                              struct device_attribute *attr, char *buf)
++00484 {
++00485 #ifdef LM_INTERFACE
++00486         struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
++00487         dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
++00488 #elif defined(PCI_INTERFACE)
++00489         dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
++00490 #endif
++00491 
++00492         uint32_t val;
++00493         volatile uint32_t *addr;
++00494 
++00495         if (otg_dev->os_dep.reg_offset != 0xFFFFFFFF && 0 != otg_dev->os_dep.base) {
++00496                 /* Calculate the address */
++00497                 addr = (uint32_t *) (otg_dev->os_dep.reg_offset +
++00498                                      (uint8_t *) otg_dev->os_dep.base);
++00499                 val = DWC_READ_REG32(addr);
++00500                 return snprintf(buf,
++00501                                 sizeof("Reg@0xFFFFFFFF = 0xFFFFFFFF\n") + 1,
++00502                                 "Reg@0x%06x = 0x%08x\n", otg_dev->os_dep.reg_offset,
++00503                                 val);
++00504         } else {
++00505                 dev_err(_dev, "Invalid offset (0x%0x)\n", otg_dev->os_dep.reg_offset);
++00506                 return sprintf(buf, "invalid offset\n");
++00507         }
++00508 }
++00509 
++00515 static ssize_t regvalue_store(struct device *_dev,
++00516                               struct device_attribute *attr,
++00517                               const char *buf, size_t count)
++00518 {
++00519 #ifdef LM_INTERFACE
++00520         struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
++00521         dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
++00522 #elif defined(PCI_INTERFACE)
++00523         dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
++00524 #endif
++00525 
++00526         volatile uint32_t *addr;
++00527         uint32_t val = simple_strtoul(buf, NULL, 16);
++00528         //dev_dbg(_dev, "Offset=0x%08x Val=0x%08x\n", otg_dev->reg_offset, val);
++00529         if (otg_dev->os_dep.reg_offset != 0xFFFFFFFF && 0 != otg_dev->os_dep.base) {
++00530                 /* Calculate the address */
++00531                 addr = (uint32_t *) (otg_dev->os_dep.reg_offset +
++00532                                      (uint8_t *) otg_dev->os_dep.base);
++00533                 DWC_WRITE_REG32(addr, val);
++00534         } else {
++00535                 dev_err(_dev, "Invalid Register Offset (0x%08x)\n",
++00536                         otg_dev->os_dep.reg_offset);
++00537         }
++00538         return count;
++00539 }
++00540 
++00541 DEVICE_ATTR(regvalue, S_IRUGO | S_IWUSR, regvalue_show, regvalue_store);
++00542 
++00543 /*
++00544  * Attributes
++00545  */
++00546 DWC_OTG_DEVICE_ATTR_BITFIELD_RO(mode, "Mode");
++00547 DWC_OTG_DEVICE_ATTR_BITFIELD_RW(hnpcapable, "HNPCapable");
++00548 DWC_OTG_DEVICE_ATTR_BITFIELD_RW(srpcapable, "SRPCapable");
++00549 DWC_OTG_DEVICE_ATTR_BITFIELD_RW(hsic_connect, "HSIC Connect");
++00550 DWC_OTG_DEVICE_ATTR_BITFIELD_RW(inv_sel_hsic, "Invert Select HSIC");
++00551 
++00552 //DWC_OTG_DEVICE_ATTR_BITFIELD_RW(buspower,&(otg_dev->core_if->core_global_regs->gotgctl),(1<<8),8,"Mode");
++00553 //DWC_OTG_DEVICE_ATTR_BITFIELD_RW(bussuspend,&(otg_dev->core_if->core_global_regs->gotgctl),(1<<8),8,"Mode");
++00554 DWC_OTG_DEVICE_ATTR_BITFIELD_RO(busconnected, "Bus Connected");
++00555 
++00556 DWC_OTG_DEVICE_ATTR_REG32_RW(gotgctl, 0, "GOTGCTL");
++00557 DWC_OTG_DEVICE_ATTR_REG32_RW(gusbcfg,
++00558                              &(otg_dev->core_if->core_global_regs->gusbcfg),
++00559                              "GUSBCFG");
++00560 DWC_OTG_DEVICE_ATTR_REG32_RW(grxfsiz,
++00561                              &(otg_dev->core_if->core_global_regs->grxfsiz),
++00562                              "GRXFSIZ");
++00563 DWC_OTG_DEVICE_ATTR_REG32_RW(gnptxfsiz,
++00564                              &(otg_dev->core_if->core_global_regs->gnptxfsiz),
++00565                              "GNPTXFSIZ");
++00566 DWC_OTG_DEVICE_ATTR_REG32_RW(gpvndctl,
++00567                              &(otg_dev->core_if->core_global_regs->gpvndctl),
++00568                              "GPVNDCTL");
++00569 DWC_OTG_DEVICE_ATTR_REG32_RW(ggpio,
++00570                              &(otg_dev->core_if->core_global_regs->ggpio),
++00571                              "GGPIO");
++00572 DWC_OTG_DEVICE_ATTR_REG32_RW(guid, &(otg_dev->core_if->core_global_regs->guid),
++00573                              "GUID");
++00574 DWC_OTG_DEVICE_ATTR_REG32_RO(gsnpsid,
++00575                              &(otg_dev->core_if->core_global_regs->gsnpsid),
++00576                              "GSNPSID");
++00577 DWC_OTG_DEVICE_ATTR_BITFIELD_RW(devspeed, "Device Speed");
++00578 DWC_OTG_DEVICE_ATTR_BITFIELD_RO(enumspeed, "Device Enumeration Speed");
++00579 
++00580 DWC_OTG_DEVICE_ATTR_REG32_RO(hptxfsiz,
++00581                              &(otg_dev->core_if->core_global_regs->hptxfsiz),
++00582                              "HPTXFSIZ");
++00583 DWC_OTG_DEVICE_ATTR_REG32_RW(hprt0, otg_dev->core_if->host_if->hprt0, "HPRT0");
++00584 
++00591 static ssize_t hnp_show(struct device *_dev,
++00592                         struct device_attribute *attr, char *buf)
++00593 {
++00594 #ifdef LM_INTERFACE
++00595         struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
++00596         dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
++00597 #elif defined(PCI_INTERFACE)
++00598         dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
++00599 #endif
++00600         return sprintf(buf, "HstNegScs = 0x%x\n",
++00601                        dwc_otg_get_hnpstatus(otg_dev->core_if));
++00602 }
++00603 
++00607 static ssize_t hnp_store(struct device *_dev,
++00608                          struct device_attribute *attr,
++00609                          const char *buf, size_t count)
++00610 {
++00611 #ifdef LM_INTERFACE
++00612         struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
++00613         dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
++00614 #elif defined(PCI_INTERFACE)
++00615         dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
++00616 #endif
++00617         uint32_t in = simple_strtoul(buf, NULL, 16);
++00618         dwc_otg_set_hnpreq(otg_dev->core_if, in);
++00619         return count;
++00620 }
++00621 
++00622 DEVICE_ATTR(hnp, 0644, hnp_show, hnp_store);
++00623 
++00630 static ssize_t srp_show(struct device *_dev,
++00631                         struct device_attribute *attr, char *buf)
++00632 {
++00633 #ifndef DWC_HOST_ONLY
++00634 #ifdef LM_INTERFACE
++00635         struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
++00636         dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
++00637 #elif defined(PCI_INTERFACE)
++00638         dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
++00639 #endif
++00640         return sprintf(buf, "SesReqScs = 0x%x\n",
++00641                        dwc_otg_get_srpstatus(otg_dev->core_if));
++00642 #else
++00643         return sprintf(buf, "Host Only Mode!\n");
++00644 #endif
++00645 }
++00646 
++00650 static ssize_t srp_store(struct device *_dev,
++00651                          struct device_attribute *attr,
++00652                          const char *buf, size_t count)
++00653 {
++00654 #ifndef DWC_HOST_ONLY
++00655 #ifdef LM_INTERFACE
++00656         struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
++00657         dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
++00658 #elif defined(PCI_INTERFACE)
++00659         dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
++00660 #endif
++00661         dwc_otg_pcd_initiate_srp(otg_dev->pcd);
++00662 #endif
++00663         return count;
++00664 }
++00665 
++00666 DEVICE_ATTR(srp, 0644, srp_show, srp_store);
++00667 
++00674 static ssize_t buspower_show(struct device *_dev,
++00675                              struct device_attribute *attr, char *buf)
++00676 {
++00677 #ifdef LM_INTERFACE
++00678         struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
++00679         dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
++00680 #elif defined(PCI_INTERFACE)
++00681         dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
++00682 #endif
++00683         return sprintf(buf, "Bus Power = 0x%x\n",
++00684                        dwc_otg_get_prtpower(otg_dev->core_if));
++00685 }
++00686 
++00690 static ssize_t buspower_store(struct device *_dev,
++00691                               struct device_attribute *attr,
++00692                               const char *buf, size_t count)
++00693 {
++00694 #ifdef LM_INTERFACE
++00695         struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
++00696         dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
++00697 #elif defined(PCI_INTERFACE)
++00698         dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
++00699 #endif
++00700         uint32_t on = simple_strtoul(buf, NULL, 16);
++00701         dwc_otg_set_prtpower(otg_dev->core_if, on);
++00702         return count;
++00703 }
++00704 
++00705 DEVICE_ATTR(buspower, 0644, buspower_show, buspower_store);
++00706 
++00713 static ssize_t bussuspend_show(struct device *_dev,
++00714                                struct device_attribute *attr, char *buf)
++00715 {
++00716 #ifdef LM_INTERFACE
++00717         struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
++00718         dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
++00719 #elif defined(PCI_INTERFACE)
++00720         dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
++00721 #endif
++00722 
++00723         return sprintf(buf, "Bus Suspend = 0x%x\n",
++00724                        dwc_otg_get_prtsuspend(otg_dev->core_if));
++00725 }
++00726 
++00730 static ssize_t bussuspend_store(struct device *_dev,
++00731                                 struct device_attribute *attr,
++00732                                 const char *buf, size_t count)
++00733 {
++00734 #ifdef LM_INTERFACE
++00735         struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
++00736         dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
++00737 #elif defined(PCI_INTERFACE)
++00738         dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
++00739 #endif
++00740 
++00741         uint32_t in = simple_strtoul(buf, NULL, 16);
++00742         dwc_otg_set_prtsuspend(otg_dev->core_if, in);
++00743         return count;
++00744 }
++00745 
++00746 DEVICE_ATTR(bussuspend, 0644, bussuspend_show, bussuspend_store);
++00747 
++00751 static ssize_t mode_ch_tim_en_show(struct device *_dev,
++00752                                    struct device_attribute *attr, char *buf)
++00753 {
++00754 #ifdef LM_INTERFACE
++00755         struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
++00756         dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
++00757 #elif defined(PCI_INTERFACE)
++00758         dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
++00759 #endif
++00760 
++00761         return sprintf(buf, "Mode Change Ready Timer Enable = 0x%x\n",
++00762                        dwc_otg_get_mode_ch_tim(otg_dev->core_if));
++00763 }
++00764 
++00768 static ssize_t mode_ch_tim_en_store(struct device *_dev,
++00769                                     struct device_attribute *attr,
++00770                                     const char *buf, size_t count)
++00771 {
++00772 #ifdef LM_INTERFACE
++00773         struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
++00774         dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
++00775 #elif defined(PCI_INTERFACE)
++00776         dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
++00777 #endif
++00778 
++00779         uint32_t in = simple_strtoul(buf, NULL, 16);
++00780         dwc_otg_set_mode_ch_tim(otg_dev->core_if, in);
++00781         return count;
++00782 }
++00783 
++00784 DEVICE_ATTR(mode_ch_tim_en, 0644, mode_ch_tim_en_show, mode_ch_tim_en_store);
++00785 
++00789 static ssize_t fr_interval_show(struct device *_dev,
++00790                                 struct device_attribute *attr, char *buf)
++00791 {
++00792 #ifdef LM_INTERFACE
++00793         struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
++00794         dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
++00795 #elif defined(PCI_INTERFACE)
++00796         dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
++00797 #endif
++00798 
++00799         return sprintf(buf, "Frame Interval = 0x%x\n",
++00800                        dwc_otg_get_fr_interval(otg_dev->core_if));
++00801 }
++00802 
++00806 static ssize_t fr_interval_store(struct device *_dev,
++00807                                  struct device_attribute *attr,
++00808                                  const char *buf, size_t count)
++00809 {
++00810 #ifdef LM_INTERFACE
++00811         struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
++00812         dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
++00813 #elif defined(PCI_INTERFACE)
++00814         dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
++00815 #endif
++00816 
++00817         uint32_t in = simple_strtoul(buf, NULL, 10);
++00818         dwc_otg_set_fr_interval(otg_dev->core_if, in);
++00819         return count;
++00820 }
++00821 
++00822 DEVICE_ATTR(fr_interval, 0644, fr_interval_show, fr_interval_store);
++00823 
++00827 static ssize_t remote_wakeup_show(struct device *_dev,
++00828                                   struct device_attribute *attr, char *buf)
++00829 {
++00830 #ifndef DWC_HOST_ONLY
++00831 #ifdef LM_INTERFACE
++00832         struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
++00833         dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
++00834 #elif defined(PCI_INTERFACE)
++00835         dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
++00836 #endif
++00837 
++00838         return sprintf(buf,
++00839                        "Remote Wakeup Sig = %d Enabled = %d LPM Remote Wakeup = %d\n",
++00840                        dwc_otg_get_remotewakesig(otg_dev->core_if),
++00841                        dwc_otg_pcd_get_rmwkup_enable(otg_dev->pcd),
++00842                        dwc_otg_get_lpm_remotewakeenabled(otg_dev->core_if));
++00843 #else
++00844         return sprintf(buf, "Host Only Mode!\n");
++00845 #endif /* DWC_HOST_ONLY */
++00846 }
++00847 
++00854 static ssize_t remote_wakeup_store(struct device *_dev,
++00855                                    struct device_attribute *attr,
++00856                                    const char *buf, size_t count)
++00857 {
++00858 #ifndef DWC_HOST_ONLY
++00859 #ifdef LM_INTERFACE
++00860         struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
++00861         dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
++00862 #elif defined(PCI_INTERFACE)
++00863         dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
++00864 #endif
++00865 
++00866         uint32_t val = simple_strtoul(buf, NULL, 16);
++00867 
++00868         if (val & 1) {
++00869                 dwc_otg_pcd_remote_wakeup(otg_dev->pcd, 1);
++00870         } else {
++00871                 dwc_otg_pcd_remote_wakeup(otg_dev->pcd, 0);
++00872         }
++00873 #endif /* DWC_HOST_ONLY */
++00874         return count;
++00875 }
++00876 
++00877 DEVICE_ATTR(remote_wakeup, S_IRUGO | S_IWUSR, remote_wakeup_show,
++00878             remote_wakeup_store);
++00879 
++00883 static ssize_t rem_wakeup_pwrdn_show(struct device *_dev,
++00884                                      struct device_attribute *attr, char *buf)
++00885 {
++00886 #ifndef DWC_HOST_ONLY
++00887 #ifdef LM_INTERFACE
++00888         struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
++00889         dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
++00890 #elif defined(PCI_INTERFACE)
++00891         dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
++00892 #endif
++00893         if (dwc_otg_get_core_state(otg_dev->core_if)) {
++00894                 DWC_PRINTF("Core is in hibernation\n");
++00895         } else {
++00896                 DWC_PRINTF("Core is not in hibernation\n");
++00897         }
++00898 #endif /* DWC_HOST_ONLY */
++00899         return 0;
++00900 }
++00901 
++00902 extern int dwc_otg_device_hibernation_restore(dwc_otg_core_if_t * core_if,
++00903                                               int rem_wakeup, int reset);
++00904 
++00908 static ssize_t rem_wakeup_pwrdn_store(struct device *_dev,
++00909                                       struct device_attribute *attr,
++00910                                       const char *buf, size_t count)
++00911 {
++00912 #ifndef DWC_HOST_ONLY
++00913 #ifdef LM_INTERFACE
++00914         struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
++00915         dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
++00916 #elif defined(PCI_INTERFACE)
++00917         dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
++00918 #endif
++00919         dwc_otg_device_hibernation_restore(otg_dev->core_if, 1, 0);
++00920 #endif
++00921         return count;
++00922 }
++00923 
++00924 DEVICE_ATTR(rem_wakeup_pwrdn, S_IRUGO | S_IWUSR, rem_wakeup_pwrdn_show,
++00925             rem_wakeup_pwrdn_store);
++00926 
++00927 static ssize_t disconnect_us(struct device *_dev,
++00928                              struct device_attribute *attr,
++00929                              const char *buf, size_t count)
++00930 {
++00931 
++00932 #ifndef DWC_HOST_ONLY
++00933 #ifdef LM_INTERFACE
++00934         struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
++00935         dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
++00936 #elif defined(PCI_INTERFACE)
++00937         dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
++00938 #endif
++00939         uint32_t val = simple_strtoul(buf, NULL, 16);
++00940         DWC_PRINTF("The Passed value is %04x\n", val);
++00941 
++00942         dwc_otg_pcd_disconnect_us(otg_dev->pcd, 50);
++00943 
++00944 #endif /* DWC_HOST_ONLY */
++00945         return count;
++00946 }
++00947 
++00948 DEVICE_ATTR(disconnect_us, S_IWUSR, 0, disconnect_us);
++00949 
++00954 static ssize_t regdump_show(struct device *_dev,
++00955                             struct device_attribute *attr, char *buf)
++00956 {
++00957 #ifdef LM_INTERFACE
++00958         struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
++00959         dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
++00960 #elif defined(PCI_INTERFACE)
++00961         dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
++00962 #endif
++00963 
++00964         dwc_otg_dump_global_registers(otg_dev->core_if);
++00965         if (dwc_otg_is_host_mode(otg_dev->core_if)) {
++00966                 dwc_otg_dump_host_registers(otg_dev->core_if);
++00967         } else {
++00968                 dwc_otg_dump_dev_registers(otg_dev->core_if);
++00969 
++00970         }
++00971         return sprintf(buf, "Register Dump\n");
++00972 }
++00973 
++00974 DEVICE_ATTR(regdump, S_IRUGO | S_IWUSR, regdump_show, 0);
++00975 
++00980 static ssize_t spramdump_show(struct device *_dev,
++00981                               struct device_attribute *attr, char *buf)
++00982 {
++00983 #ifdef LM_INTERFACE
++00984         struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
++00985         dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
++00986 #elif defined(PCI_INTERFACE)
++00987         dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
++00988 #endif
++00989 
++00990         dwc_otg_dump_spram(otg_dev->core_if);
++00991 
++00992         return sprintf(buf, "SPRAM Dump\n");
++00993 }
++00994 
++00995 DEVICE_ATTR(spramdump, S_IRUGO | S_IWUSR, spramdump_show, 0);
++00996 
++01000 static ssize_t hcddump_show(struct device *_dev,
++01001                             struct device_attribute *attr, char *buf)
++01002 {
++01003 #ifndef DWC_DEVICE_ONLY
++01004 #ifdef LM_INTERFACE
++01005         struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
++01006         dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
++01007 #elif defined(PCI_INTERFACE)
++01008         dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
++01009 #endif
++01010 
++01011         dwc_otg_hcd_dump_state(otg_dev->hcd);
++01012 #endif /* DWC_DEVICE_ONLY */
++01013         return sprintf(buf, "HCD Dump\n");
++01014 }
++01015 
++01016 DEVICE_ATTR(hcddump, S_IRUGO | S_IWUSR, hcddump_show, 0);
++01017 
++01023 static ssize_t hcd_frrem_show(struct device *_dev,
++01024                               struct device_attribute *attr, char *buf)
++01025 {
++01026 #ifndef DWC_DEVICE_ONLY
++01027 #ifdef LM_INTERFACE
++01028         struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
++01029         dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
++01030 #elif defined(PCI_INTERFACE)
++01031         dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
++01032 #endif
++01033 
++01034         dwc_otg_hcd_dump_frrem(otg_dev->hcd);
++01035 #endif /* DWC_DEVICE_ONLY */
++01036         return sprintf(buf, "HCD Dump Frame Remaining\n");
++01037 }
++01038 
++01039 DEVICE_ATTR(hcd_frrem, S_IRUGO | S_IWUSR, hcd_frrem_show, 0);
++01040 
++01045 #define RW_REG_COUNT 10000000
++01046 #define MSEC_PER_JIFFIE 1000/HZ
++01047 static ssize_t rd_reg_test_show(struct device *_dev,
++01048                                 struct device_attribute *attr, char *buf)
++01049 {
++01050 #ifdef LM_INTERFACE
++01051         struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
++01052         dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
++01053 #elif defined(PCI_INTERFACE)
++01054         dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
++01055 #endif
++01056 
++01057         int i;
++01058         int time;
++01059         int start_jiffies;
++01060 
++01061         printk("HZ %d, MSEC_PER_JIFFIE %d, loops_per_jiffy %lu\n",
++01062                HZ, MSEC_PER_JIFFIE, loops_per_jiffy);
++01063         start_jiffies = jiffies;
++01064         for (i = 0; i < RW_REG_COUNT; i++) {
++01065                 dwc_otg_get_gnptxfsiz(otg_dev->core_if);
++01066         }
++01067         time = jiffies - start_jiffies;
++01068         return sprintf(buf,
++01069                        "Time to read GNPTXFSIZ reg %d times: %d msecs (%d jiffies)\n",
++01070                        RW_REG_COUNT, time * MSEC_PER_JIFFIE, time);
++01071 }
++01072 
++01073 DEVICE_ATTR(rd_reg_test, S_IRUGO | S_IWUSR, rd_reg_test_show, 0);
++01074 
++01079 static ssize_t wr_reg_test_show(struct device *_dev,
++01080                                 struct device_attribute *attr, char *buf)
++01081 {
++01082 #ifdef LM_INTERFACE
++01083         struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
++01084         dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
++01085 #elif defined(PCI_INTERFACE)
++01086         dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
++01087 #endif
++01088 
++01089         uint32_t reg_val;
++01090         int i;
++01091         int time;
++01092         int start_jiffies;
++01093 
++01094         printk("HZ %d, MSEC_PER_JIFFIE %d, loops_per_jiffy %lu\n",
++01095                HZ, MSEC_PER_JIFFIE, loops_per_jiffy);
++01096         reg_val = dwc_otg_get_gnptxfsiz(otg_dev->core_if);
++01097         start_jiffies = jiffies;
++01098         for (i = 0; i < RW_REG_COUNT; i++) {
++01099                 dwc_otg_set_gnptxfsiz(otg_dev->core_if, reg_val);
++01100         }
++01101         time = jiffies - start_jiffies;
++01102         return sprintf(buf,
++01103                        "Time to write GNPTXFSIZ reg %d times: %d msecs (%d jiffies)\n",
++01104                        RW_REG_COUNT, time * MSEC_PER_JIFFIE, time);
++01105 }
++01106 
++01107 DEVICE_ATTR(wr_reg_test, S_IRUGO | S_IWUSR, wr_reg_test_show, 0);
++01108 
++01109 #ifdef CONFIG_USB_DWC_OTG_LPM
++01110 
++01114 static ssize_t lpmresp_show(struct device *_dev,
++01115                             struct device_attribute *attr, char *buf)
++01116 {
++01117 #ifdef LM_INTERFACE
++01118         struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
++01119         dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
++01120 #elif defined(PCI_INTERFACE)
++01121         dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
++01122 #endif
++01123 
++01124         if (!dwc_otg_get_param_lpm_enable(otg_dev->core_if))
++01125                 return sprintf(buf, "** LPM is DISABLED **\n");
++01126 
++01127         if (!dwc_otg_is_device_mode(otg_dev->core_if)) {
++01128                 return sprintf(buf, "** Current mode is not device mode\n");
++01129         }
++01130         return sprintf(buf, "lpm_response = %d\n",
++01131                        dwc_otg_get_lpmresponse(otg_dev->core_if));
++01132 }
++01133 
++01137 static ssize_t lpmresp_store(struct device *_dev,
++01138                              struct device_attribute *attr,
++01139                              const char *buf, size_t count)
++01140 {
++01141 #ifdef LM_INTERFACE
++01142         struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
++01143         dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
++01144 #elif defined(PCI_INTERFACE)
++01145         dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
++01146 #endif
++01147 
++01148         uint32_t val = simple_strtoul(buf, NULL, 16);
++01149 
++01150         if (!dwc_otg_get_param_lpm_enable(otg_dev->core_if)) {
++01151                 return 0;
++01152         }
++01153 
++01154         if (!dwc_otg_is_device_mode(otg_dev->core_if)) {
++01155                 return 0;
++01156         }
++01157 
++01158         dwc_otg_set_lpmresponse(otg_dev->core_if, val);
++01159         return count;
++01160 }
++01161 
++01162 DEVICE_ATTR(lpm_response, S_IRUGO | S_IWUSR, lpmresp_show, lpmresp_store);
++01163 
++01167 static ssize_t sleepstatus_show(struct device *_dev,
++01168                                 struct device_attribute *attr, char *buf)
++01169 {
++01170 #ifdef LM_INTERFACE
++01171         struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
++01172         dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
++01173 #elif defined(PCI_INTERFACE)
++01174         dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
++01175 #endif
++01176 
++01177         return sprintf(buf, "Sleep Status = %d\n",
++01178                        dwc_otg_get_lpm_portsleepstatus(otg_dev->core_if));
++01179 }
++01180 
++01184 static ssize_t sleepstatus_store(struct device *_dev,
++01185                                  struct device_attribute *attr,
++01186                                  const char *buf, size_t count)
++01187 {
++01188 #ifdef LM_INTERFACE
++01189         struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
++01190         dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
++01191 #elif defined(PCI_INTERFACE)
++01192         dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
++01193 #endif
++01194 
++01195         dwc_otg_core_if_t *core_if = otg_dev->core_if;
++01196 
++01197         if (dwc_otg_get_lpm_portsleepstatus(otg_dev->core_if)) {
++01198                 if (dwc_otg_is_host_mode(core_if)) {
++01199 
++01200                         DWC_PRINTF("Host initiated resume\n");
++01201                         dwc_otg_set_prtresume(otg_dev->core_if, 1);
++01202                 }
++01203         }
++01204 
++01205         return count;
++01206 }
++01207 
++01208 DEVICE_ATTR(sleep_status, S_IRUGO | S_IWUSR, sleepstatus_show,
++01209             sleepstatus_store);
++01210 
++01211 #endif /* CONFIG_USB_DWC_OTG_LPM_ENABLE */
++01212 
++01218 void dwc_otg_attr_create(
++01219 #ifdef LM_INTERFACE
++01220                                 struct lm_device *dev
++01221 #elif  defined(PCI_INTERFACE)
++01222                                 struct pci_dev *dev
++01223 #endif
++01224     )
++01225 {
++01226         int error;
++01227 
++01228         error = device_create_file(&dev->dev, &dev_attr_regoffset);
++01229         error = device_create_file(&dev->dev, &dev_attr_regvalue);
++01230         error = device_create_file(&dev->dev, &dev_attr_mode);
++01231         error = device_create_file(&dev->dev, &dev_attr_hnpcapable);
++01232         error = device_create_file(&dev->dev, &dev_attr_srpcapable);
++01233         error = device_create_file(&dev->dev, &dev_attr_hsic_connect);
++01234         error = device_create_file(&dev->dev, &dev_attr_inv_sel_hsic);
++01235         error = device_create_file(&dev->dev, &dev_attr_hnp);
++01236         error = device_create_file(&dev->dev, &dev_attr_srp);
++01237         error = device_create_file(&dev->dev, &dev_attr_buspower);
++01238         error = device_create_file(&dev->dev, &dev_attr_bussuspend);
++01239         error = device_create_file(&dev->dev, &dev_attr_mode_ch_tim_en);
++01240         error = device_create_file(&dev->dev, &dev_attr_fr_interval);
++01241         error = device_create_file(&dev->dev, &dev_attr_busconnected);
++01242         error = device_create_file(&dev->dev, &dev_attr_gotgctl);
++01243         error = device_create_file(&dev->dev, &dev_attr_gusbcfg);
++01244         error = device_create_file(&dev->dev, &dev_attr_grxfsiz);
++01245         error = device_create_file(&dev->dev, &dev_attr_gnptxfsiz);
++01246         error = device_create_file(&dev->dev, &dev_attr_gpvndctl);
++01247         error = device_create_file(&dev->dev, &dev_attr_ggpio);
++01248         error = device_create_file(&dev->dev, &dev_attr_guid);
++01249         error = device_create_file(&dev->dev, &dev_attr_gsnpsid);
++01250         error = device_create_file(&dev->dev, &dev_attr_devspeed);
++01251         error = device_create_file(&dev->dev, &dev_attr_enumspeed);
++01252         error = device_create_file(&dev->dev, &dev_attr_hptxfsiz);
++01253         error = device_create_file(&dev->dev, &dev_attr_hprt0);
++01254         error = device_create_file(&dev->dev, &dev_attr_remote_wakeup);
++01255         error = device_create_file(&dev->dev, &dev_attr_rem_wakeup_pwrdn);
++01256         error = device_create_file(&dev->dev, &dev_attr_disconnect_us);
++01257         error = device_create_file(&dev->dev, &dev_attr_regdump);
++01258         error = device_create_file(&dev->dev, &dev_attr_spramdump);
++01259         error = device_create_file(&dev->dev, &dev_attr_hcddump);
++01260         error = device_create_file(&dev->dev, &dev_attr_hcd_frrem);
++01261         error = device_create_file(&dev->dev, &dev_attr_rd_reg_test);
++01262         error = device_create_file(&dev->dev, &dev_attr_wr_reg_test);
++01263 #ifdef CONFIG_USB_DWC_OTG_LPM
++01264         error = device_create_file(&dev->dev, &dev_attr_lpm_response);
++01265         error = device_create_file(&dev->dev, &dev_attr_sleep_status);
++01266 #endif
++01267 }
++01268 
++01272 void dwc_otg_attr_remove(
++01273 #ifdef LM_INTERFACE
++01274                                 struct lm_device *dev
++01275 #elif  defined(PCI_INTERFACE)
++01276                                 struct pci_dev *dev
++01277 #endif
++01278     )
++01279 {
++01280         device_remove_file(&dev->dev, &dev_attr_regoffset);
++01281         device_remove_file(&dev->dev, &dev_attr_regvalue);
++01282         device_remove_file(&dev->dev, &dev_attr_mode);
++01283         device_remove_file(&dev->dev, &dev_attr_hnpcapable);
++01284         device_remove_file(&dev->dev, &dev_attr_srpcapable);
++01285         device_remove_file(&dev->dev, &dev_attr_hsic_connect);
++01286         device_remove_file(&dev->dev, &dev_attr_inv_sel_hsic);
++01287         device_remove_file(&dev->dev, &dev_attr_hnp);
++01288         device_remove_file(&dev->dev, &dev_attr_srp);
++01289         device_remove_file(&dev->dev, &dev_attr_buspower);
++01290         device_remove_file(&dev->dev, &dev_attr_bussuspend);
++01291         device_remove_file(&dev->dev, &dev_attr_mode_ch_tim_en);
++01292         device_remove_file(&dev->dev, &dev_attr_fr_interval);
++01293         device_remove_file(&dev->dev, &dev_attr_busconnected);
++01294         device_remove_file(&dev->dev, &dev_attr_gotgctl);
++01295         device_remove_file(&dev->dev, &dev_attr_gusbcfg);
++01296         device_remove_file(&dev->dev, &dev_attr_grxfsiz);
++01297         device_remove_file(&dev->dev, &dev_attr_gnptxfsiz);
++01298         device_remove_file(&dev->dev, &dev_attr_gpvndctl);
++01299         device_remove_file(&dev->dev, &dev_attr_ggpio);
++01300         device_remove_file(&dev->dev, &dev_attr_guid);
++01301         device_remove_file(&dev->dev, &dev_attr_gsnpsid);
++01302         device_remove_file(&dev->dev, &dev_attr_devspeed);
++01303         device_remove_file(&dev->dev, &dev_attr_enumspeed);
++01304         device_remove_file(&dev->dev, &dev_attr_hptxfsiz);
++01305         device_remove_file(&dev->dev, &dev_attr_hprt0);
++01306         device_remove_file(&dev->dev, &dev_attr_remote_wakeup);
++01307         device_remove_file(&dev->dev, &dev_attr_rem_wakeup_pwrdn);
++01308         device_remove_file(&dev->dev, &dev_attr_disconnect_us);
++01309         device_remove_file(&dev->dev, &dev_attr_regdump);
++01310         device_remove_file(&dev->dev, &dev_attr_spramdump);
++01311         device_remove_file(&dev->dev, &dev_attr_hcddump);
++01312         device_remove_file(&dev->dev, &dev_attr_hcd_frrem);
++01313         device_remove_file(&dev->dev, &dev_attr_rd_reg_test);
++01314         device_remove_file(&dev->dev, &dev_attr_wr_reg_test);
++01315 #ifdef CONFIG_USB_DWC_OTG_LPM
++01316         device_remove_file(&dev->dev, &dev_attr_lpm_response);
++01317         device_remove_file(&dev->dev, &dev_attr_sleep_status);
++01318 #endif
++01319 }
++
Generated on Thu Oct 27 03:56:37 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
++doxygen 1.3.9.1
+ + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__attr_8c.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/dwc__otg__attr_8c.html 2013-07-26 19:31:20.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__attr_8c.html 2013-07-26 19:34:39.000000000 +0000 +@@ -2,357 +2,392 @@ + + DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_attr.c File Reference + +- + +- +-
+-
+-
+-
++ ++
Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
+

dwc_otg_attr.c File Reference

The diagnostic interface will provide access to the controller for bringing up the hardware and testing. More... +

+-#include <linux/kernel.h>
+-#include <linux/module.h>
+-#include <linux/moduleparam.h>
+-#include <linux/init.h>
+-#include <linux/device.h>
+-#include <linux/errno.h>
+-#include <linux/types.h>
+-#include <linux/stat.h>
+-#include <linux/version.h>
+-#include <linux/param.h>
+-#include <linux/delay.h>
+-#include <linux/jiffies.h>
+-#include <asm/io.h>
+-#include "dwc_os.h"
+-#include "dwc_otg_driver.h"
+-#include "dwc_otg_attr.h"
+-#include "dwc_otg_core_if.h"
+-#include "dwc_otg_pcd_if.h"
+-#include "dwc_otg_hcd_if.h"
++#include "dwc_otg_os_dep.h"
++#include "dwc_os.h"
++#include "dwc_otg_driver.h"
++#include "dwc_otg_attr.h"
++#include "dwc_otg_core_if.h"
++#include "dwc_otg_pcd_if.h"
++#include "dwc_otg_hcd_if.h"
+ +

+ Go to the source code of this file. + + +- ++ + + +- ++ + +- ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ + +- ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ + + +- ++ ++ ++ ++ ++ ++ ++ + +- +- ++ ++ ++ ++ ++ ++ + + +- ++ + + +- ++ + + +- ++ + +- +- ++ ++ + +- ++ + + +- ++ ++ ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ ++ ++ + + +- ++ + +- ++ + +- ++ + +- ++ + + +- ++ + + +- ++ + + +

Functions for Show/Store of Attributes

+-#define RW_REG_COUNT   10000000
++#define RW_REG_COUNT   10000000
 Displays the time required to read the GNPTXFSIZ register many times (the output shows the number of times the register is read).
+-#define MSEC_PER_JIFFIE   1000/HZ
++#define MSEC_PER_JIFFIE   1000/HZ
+-static ssize_t regoffset_show (struct device *_dev, struct device_attribute *attr, char *buf)
++ssize_t regoffset_show (struct device *_dev, struct device_attribute *attr, char *buf)
 Show the register offset of the Register Access.
+-static ssize_t regoffset_store (struct device *_dev, struct device_attribute *attr, const char *buf, size_t count)
++ssize_t regoffset_store (struct device *_dev, struct device_attribute *attr, const char *buf, size_t count)
 Set the register offset for the next Register Access Read/Write.
+-static ssize_t regvalue_show (struct device *_dev, struct device_attribute *attr, char *buf)
++ssize_t regvalue_show (struct device *_dev, struct device_attribute *attr, char *buf)
 Show the value of the register at the offset in the reg_offset attribute.
+-static ssize_t regvalue_store (struct device *_dev, struct device_attribute *attr, const char *buf, size_t count)
++ssize_t regvalue_store (struct device *_dev, struct device_attribute *attr, const char *buf, size_t count)
 Store the value in the register at the offset in the reg_offset attribute.
+- DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW (mode,"Mode")
++ DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW (mode,"Mode")
+-static ssize_t hnp_store (struct device *_dev, struct device_attribute *attr, const char *buf, size_t count)
++ssize_t hnp_store (struct device *_dev, struct device_attribute *attr, const char *buf, size_t count)
 Set the HNP Request bit.
+-static ssize_t srp_show (struct device *_dev, struct device_attribute *attr, char *buf)
++ssize_t srp_show (struct device *_dev, struct device_attribute *attr, char *buf)
 Show the SRP status bit.
+-static ssize_t srp_store (struct device *_dev, struct device_attribute *attr, const char *buf, size_t count)
++ssize_t srp_store (struct device *_dev, struct device_attribute *attr, const char *buf, size_t count)
 Set the SRP Request bit.
+-static ssize_t buspower_show (struct device *_dev, struct device_attribute *attr, char *buf)
++ssize_t buspower_show (struct device *_dev, struct device_attribute *attr, char *buf)
 Show the Bus Power status.
+-static ssize_t buspower_store (struct device *_dev, struct device_attribute *attr, const char *buf, size_t count)
++ssize_t buspower_store (struct device *_dev, struct device_attribute *attr, const char *buf, size_t count)
 Set the Bus Power status.
+-static ssize_t bussuspend_show (struct device *_dev, struct device_attribute *attr, char *buf)
++ssize_t bussuspend_show (struct device *_dev, struct device_attribute *attr, char *buf)
 Show the Bus Suspend status.
+-static ssize_t bussuspend_store (struct device *_dev, struct device_attribute *attr, const char *buf, size_t count)
++ssize_t bussuspend_store (struct device *_dev, struct device_attribute *attr, const char *buf, size_t count)
 Set the Bus Suspend status.
+-static ssize_t remote_wakeup_show (struct device *_dev, struct device_attribute *attr, char *buf)
++ssize_t mode_ch_tim_en_show (struct device *_dev, struct device_attribute *attr, char *buf)
 Show the Mode Change Ready Timer status.
++ssize_t mode_ch_tim_en_store (struct device *_dev, struct device_attribute *attr, const char *buf, size_t count)
 Set the Mode Change Ready Timer status.
++ssize_t fr_interval_show (struct device *_dev, struct device_attribute *attr, char *buf)
 Show the value of HFIR Frame Interval bitfield.
++ssize_t fr_interval_store (struct device *_dev, struct device_attribute *attr, const char *buf, size_t count)
 Set the HFIR Frame Interval value.
++ssize_t remote_wakeup_show (struct device *_dev, struct device_attribute *attr, char *buf)
 Show the status of Remote Wakeup.
static ssize_t remote_wakeup_store (struct device *_dev, struct device_attribute *attr, const char *buf, size_t count)
ssize_t remote_wakeup_store (struct device *_dev, struct device_attribute *attr, const char *buf, size_t count)
 Initiate a remote wakeup of the host.
ssize_t rem_wakeup_pwrdn_show (struct device *_dev, struct device_attribute *attr, char *buf)
 Show the whether core is hibernated or not.
++int dwc_otg_device_hibernation_restore (dwc_otg_core_if_t *core_if, int rem_wakeup, int reset)
 Initiate a remote wakeup of the host.
+-static ssize_t regdump_show (struct device *_dev, struct device_attribute *attr, char *buf)
++ssize_t rem_wakeup_pwrdn_store (struct device *_dev, struct device_attribute *attr, const char *buf, size_t count)
 Initiate a remote wakeup of the device to exit from hibernation.
++ssize_t disconnect_us (struct device *_dev, struct device_attribute *attr, const char *buf, size_t count)
++ssize_t regdump_show (struct device *_dev, struct device_attribute *attr, char *buf)
 Dump global registers and either host or device registers (depending on the current mode of the core).
+-S_IRUGO static ssize_t spramdump_show (struct device *_dev, struct device_attribute *attr, char *buf)
++ssize_t spramdump_show (struct device *_dev, struct device_attribute *attr, char *buf)
 Dump global registers and either host or device registers (depending on the current mode of the core).
+-S_IRUGO static ssize_t hcddump_show (struct device *_dev, struct device_attribute *attr, char *buf)
++ssize_t hcddump_show (struct device *_dev, struct device_attribute *attr, char *buf)
 Dump the current hcd state.
S_IRUGO static ssize_t hcd_frrem_show (struct device *_dev, struct device_attribute *attr, char *buf)
ssize_t hcd_frrem_show (struct device *_dev, struct device_attribute *attr, char *buf)
 Dump the average frame remaining at SOF.
+-static ssize_t rd_reg_test_show (struct device *_dev, struct device_attribute *attr, char *buf)
 Dump the average frame remaining at SOF.
++ssize_t rd_reg_test_show (struct device *_dev, struct device_attribute *attr, char *buf)
+-S_IRUGO static ssize_t wr_reg_test_show (struct device *_dev, struct device_attribute *attr, char *buf)
++ssize_t wr_reg_test_show (struct device *_dev, struct device_attribute *attr, char *buf)
 Displays the time required to write the GNPTXFSIZ register many times (the output shows the number of times the register is written).
+- regoffset
++ regoffset
++S_IRUGO S_IWUSR
+-S_IRUGO S_IWUSR
++S_IRUGO regoffset_show
+-S_IRUGO regoffset_show
++S_IRUGO regoffset_store
+-S_IRUGO regoffset_store
++ regvalue
+- regvalue
++S_IRUGO regvalue_show
+-S_IRUGO S_IWUSR
++S_IRUGO regvalue_store
+-S_IRUGO regvalue_show
++ hnp
+-S_IRUGO regvalue_store
++ hnp_show
+- hnp
++ hnp_store
+- hnp_show
++ srp
+- hnp_store
++ srp_show
+- srp
++ srp_store
+- srp_show
++ buspower
+- srp_store
++ buspower_show
+- buspower
++ buspower_store
+- buspower_show
++ bussuspend
+- buspower_store
++ bussuspend_show
+- bussuspend
++ bussuspend_store
+- bussuspend_show
++ mode_ch_tim_en
+- bussuspend_store
++ mode_ch_tim_en_show
+- remote_wakeup
++ mode_ch_tim_en_store
+-S_IRUGO S_IWUSR
++ fr_interval
+-S_IRUGO remote_wakeup_show
++ fr_interval_show
+-S_IRUGO remote_wakeup_store
++ fr_interval_store
+- regdump
++ remote_wakeup
+-S_IRUGO S_IWUSR
++S_IRUGO remote_wakeup_show
+-S_IRUGO regdump_show
++S_IRUGO remote_wakeup_store
+- spramdump
++ rem_wakeup_pwrdn
+-S_IRUGO S_IWUSR
++S_IRUGO rem_wakeup_pwrdn_show
+-S_IRUGO spramdump_show
++S_IRUGO rem_wakeup_pwrdn_store
+- hcddump
++ disconnect_us
+-S_IRUGO S_IWUSR
++ regdump
+-S_IRUGO hcddump_show
++S_IRUGO regdump_show
+- hcd_frrem
++ spramdump
+-S_IRUGO S_IWUSR
++S_IRUGO spramdump_show
+-S_IRUGO hcd_frrem_show
++ hcddump
+- rd_reg_test
++S_IRUGO hcddump_show
+-S_IRUGO S_IWUSR
++ hcd_frrem
+-S_IRUGO rd_reg_test_show
++S_IRUGO hcd_frrem_show
+- wr_reg_test
++ rd_reg_test
+-S_IRUGO S_IWUSR
++S_IRUGO rd_reg_test_show
+-S_IRUGO wr_reg_test_show
++ wr_reg_test
++S_IRUGO wr_reg_test_show

Defines

#define DWC_OTG_DEVICE_ATTR_BITFIELD_RW(_otg_attr_name_, _string_)
#define DWC_OTG_DEVICE_ATTR_BITFIELD_RW(_otg_attr_name_, _string_)
#define DWC_OTG_DEVICE_ATTR_BITFIELD_RO(_otg_attr_name_, _string_)
#define DWC_OTG_DEVICE_ATTR_BITFIELD_RO(_otg_attr_name_, _string_)
#define DWC_OTG_DEVICE_ATTR_REG32_RW(_otg_attr_name_, _addr_, _string_)
#define DWC_OTG_DEVICE_ATTR_REG32_RW(_otg_attr_name_, _addr_, _string_)
#define DWC_OTG_DEVICE_ATTR_REG32_RO(_otg_attr_name_, _addr_, _string_)
#define DWC_OTG_DEVICE_ATTR_REG32_RO(_otg_attr_name_, _addr_, _string_)

Functions

+-S_IRUGO void dwc_otg_attr_create ()
++void dwc_otg_attr_create ()
 Create the device files.
+-void dwc_otg_attr_remove ()
++void dwc_otg_attr_remove ()
 Remove the device files.
+

Detailed Description

+ The diagnostic interface will provide access to the controller for bringing up the hardware and testing. +

+-The Linux driver attributes feature will be used to provide the Linux Diagnostic Interface. These attributes are accessed through sysfs. ++The Linux driver attributes feature will be used to provide the Linux Diagnostic Interface. These attributes are accessed through sysfs. +

+ Definition in file dwc_otg_attr.c.

Define Documentation

+- +-
+-
+- +- +- +- +- +- +- +- +- +- +- ++

++

#define DWC_OTG_DEVICE_ATTR_BITFIELD_RW (_otg_attr_name_,
_string_   ) 
++ ++ ++ ++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ + +
#define DWC_OTG_DEVICE_ATTR_BITFIELD_RW ( _otg_attr_name_,
_string_   ) 
+- +-
++
++ ++ ++ ++
++   ++ + +

+-Value:

DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_string_) \
++Value:
DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_string_) \
+ DWC_OTG_DEVICE_ATTR_BITFIELD_STORE(_otg_attr_name_,_string_) \
+ DEVICE_ATTR(_otg_attr_name_,0644,_otg_attr_name_##_show,_otg_attr_name_##_store);
+ 

+ 

+-Definition at line 405 of file dwc_otg_attr.c.
+-
+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +- +- ++Definition at line 410 of file dwc_otg_attr.c. ++ ++
#define DWC_OTG_DEVICE_ATTR_BITFIELD_RO (_otg_attr_name_,
_string_   ) 
++

++ ++ ++ ++ ++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ + +
#define DWC_OTG_DEVICE_ATTR_BITFIELD_RO ( _otg_attr_name_,
_string_   ) 
+- +-
++
++ ++ ++ ++
++   ++ + +

+-Value:

DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_string_) \
++Value:
DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_string_) \
+ DEVICE_ATTR(_otg_attr_name_,0444,_otg_attr_name_##_show,NULL);
+ 

+ 

+-Definition at line 410 of file dwc_otg_attr.c.
+-
+-

+- +-

+-
+- +- +- +- +- +- +- +- +- +- +- +- +- +- ++Definition at line 415 of file dwc_otg_attr.c. ++ ++
#define DWC_OTG_DEVICE_ATTR_REG32_RW (_otg_attr_name_,
_addr_,
_string_   ) 
++

++ ++ ++ ++ ++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ + +
#define DWC_OTG_DEVICE_ATTR_REG32_RW ( _otg_attr_name_,
_addr_,
_string_   ) 
+- +-
++
++ ++ ++ ++
++   ++ + +

+ Value:

DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_string_) \
+@@ -360,126 +395,197 @@
+ DEVICE_ATTR(_otg_attr_name_,0644,_otg_attr_name_##_show,_otg_attr_name_##_store);
+
+

+-Definition at line 414 of file dwc_otg_attr.c. +- +-

+- +-

+-
+- +- +- +- +- +- +- +- +- +- +- +- +- +- ++Definition at line 419 of file dwc_otg_attr.c. ++ ++
#define DWC_OTG_DEVICE_ATTR_REG32_RO (_otg_attr_name_,
_addr_,
_string_   ) 
++

++ ++ ++ ++ ++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ + +
#define DWC_OTG_DEVICE_ATTR_REG32_RO ( _otg_attr_name_,
_addr_,
_string_   ) 
+- +-
++
++ ++ ++ ++ ++ ++
++   ++ + +

+ Value:

DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_string_) \
+ DEVICE_ATTR(_otg_attr_name_,0444,_otg_attr_name_##_show,NULL);
+
+

+-Definition at line 419 of file dwc_otg_attr.c. +- +-

++Definition at line 424 of file dwc_otg_attr.c.

+

Function Documentation

+- +-
+-
+- ++

++

++ ++ ++ ++
++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
static ssize_t remote_wakeup_store (struct device *  _dev, ssize_t remote_wakeup_store ( struct device *  _dev,
struct device_attribute *  attr, struct device_attribute *  attr,
const char *  buf, const char *  buf,
size_t  count size_t  count
) [static])  [static]
+- +-
++
++ ++ ++ ++ +
++   ++ + +

+ Initiate a remote wakeup of the host. +

+ The Device control register Remote Wakeup Signal bit is written if the PCD Remote wakeup enable flag is set. +

+-Definition at line 773 of file dwc_otg_attr.c. +- +-

+- +-

+-
+- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- ++Definition at line 854 of file dwc_otg_attr.c. ++ ++
S_IRUGO static ssize_t hcd_frrem_show (struct device *  _dev,
struct device_attribute *  attr,
char *  buf 
) [static]
++

++ ++ ++ ++ ++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
ssize_t rem_wakeup_pwrdn_show ( struct device *  _dev,
struct device_attribute *  attr,
char *  buf
)  [static]
++
++ ++ ++ ++ ++ ++
++   ++ ++ ++

++Show the whether core is hibernated or not. ++

++ ++

++Definition at line 883 of file dwc_otg_attr.c.

++

++ ++ ++ ++ ++
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ + +
ssize_t hcd_frrem_show ( struct device *  _dev,
struct device_attribute *  attr,
char *  buf
)  [static]
+- +-
++
++ ++ ++ ++ ++ ++
++   ++ + +

+ Dump the average frame remaining at SOF. +

+ This can be used to determine average interrupt latency. Frame remaining is also shown for start transfer and two additional sample points. +

+-Definition at line 872 of file dwc_otg_attr.c. +- +-

+-

Generated on Tue May 5 02:22:48 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++Definition at line 1023 of file dwc_otg_attr.c.
++

Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
++doxygen 1.3.9.1 + + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__attr_8h-source.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/dwc__otg__attr_8h-source.html 2013-07-26 19:31:20.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__attr_8h-source.html 2013-07-26 19:34:39.000000000 +0000 +@@ -2,104 +2,93 @@ + + DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_attr.h Source File + +- + +- +-
+-
+-
+-
+-

dwc_otg_attr.h

Go to the documentation of this file.
00001 /* ==========================================================================
+-00002  * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_attr.h $
+-00003  * $Revision: #11 $
+-00004  * $Date: 2009/04/03 $
+-00005  * $Change: 1225160 $
+-00006  *
+-00007  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
+-00008  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
+-00009  * otherwise expressly agreed to in writing between Synopsys and you.
+-00010  * 
+-00011  * The Software IS NOT an item of Licensed Software or Licensed Product under
+-00012  * any End User Software License Agreement or Agreement for Licensed Product
+-00013  * with Synopsys or any supplement thereto. You are permitted to use and
+-00014  * redistribute this Software in source and binary forms, with or without
+-00015  * modification, provided that redistributions of source code must retain this
+-00016  * notice. You may not view, use, disclose, copy or distribute this file or
+-00017  * any information contained herein except pursuant to this license grant from
+-00018  * Synopsys. If you do not agree with this notice, including the disclaimer
+-00019  * below, then you are not authorized to use the Software.
+-00020  * 
+-00021  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
+-00022  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+-00023  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+-00024  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
+-00025  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+-00026  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+-00027  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+-00028  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+-00029  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+-00030  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+-00031  * DAMAGE.
+-00032  * ========================================================================== */
+-00033 
+-00034 #if !defined(__DWC_OTG_ATTR_H__)
+-00035 #define __DWC_OTG_ATTR_H__
+-00036 
+-00040 extern struct device_attribute dev_attr_regoffset;
+-00041 extern struct device_attribute dev_attr_regvalue;
+-00042 
+-00043 extern struct device_attribute dev_attr_mode;
+-00044 extern struct device_attribute dev_attr_hnpcapable;
+-00045 extern struct device_attribute dev_attr_srpcapable;
+-00046 extern struct device_attribute dev_attr_hnp;
+-00047 extern struct device_attribute dev_attr_srp;
+-00048 extern struct device_attribute dev_attr_buspower;
+-00049 extern struct device_attribute dev_attr_bussuspend;
+-00050 extern struct device_attribute dev_attr_busconnected;
+-00051 extern struct device_attribute dev_attr_gotgctl;
+-00052 extern struct device_attribute dev_attr_gusbcfg;
+-00053 extern struct device_attribute dev_attr_grxfsiz;
+-00054 extern struct device_attribute dev_attr_gnptxfsiz;
+-00055 extern struct device_attribute dev_attr_gpvndctl;
+-00056 extern struct device_attribute dev_attr_ggpio;
+-00057 extern struct device_attribute dev_attr_guid;
+-00058 extern struct device_attribute dev_attr_gsnpsid;
+-00059 extern struct device_attribute dev_attr_devspeed;
+-00060 extern struct device_attribute dev_attr_enumspeed;
+-00061 extern struct device_attribute dev_attr_hptxfsiz;
+-00062 extern struct device_attribute dev_attr_hprt0;
+-00063 #ifdef CONFIG_USB_DWC_OTG_LPM
+-00064 extern struct device_attribute dev_attr_lpm_response;
+-00065 extern struct device_attribute dev_attr_sleep_local_dev;
+-00066 extern struct device_attribute devi_attr_sleep_status;
+-00067 #endif
+-00068 
+-00069 void dwc_otg_attr_create (
+-00070 #ifdef LM_INTERFACE
+-00071         struct lm_device *dev
+-00072 #elif  PCI_INTERFACE
+-00073         struct pci_dev *dev
+-00074 #endif
+-00075         );
+-00076 
+-00077 void dwc_otg_attr_remove (
+-00078 #ifdef LM_INTERFACE
+-00079         struct lm_device *dev
+-00080 #elif  PCI_INTERFACE
+-00081         struct pci_dev *dev
+-00082 #endif
+-00083         );
+-00084 #endif
+-
Generated on Tue May 5 02:22:48 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++
Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
++

dwc_otg_attr.h

Go to the documentation of this file.
00001 /* ==========================================================================
++00002  * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_attr.h $
++00003  * $Revision: #13 $
++00004  * $Date: 2010/06/21 $
++00005  * $Change: 1532021 $
++00006  *
++00007  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
++00008  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
++00009  * otherwise expressly agreed to in writing between Synopsys and you.
++00010  * 
++00011  * The Software IS NOT an item of Licensed Software or Licensed Product under
++00012  * any End User Software License Agreement or Agreement for Licensed Product
++00013  * with Synopsys or any supplement thereto. You are permitted to use and
++00014  * redistribute this Software in source and binary forms, with or without
++00015  * modification, provided that redistributions of source code must retain this
++00016  * notice. You may not view, use, disclose, copy or distribute this file or
++00017  * any information contained herein except pursuant to this license grant from
++00018  * Synopsys. If you do not agree with this notice, including the disclaimer
++00019  * below, then you are not authorized to use the Software.
++00020  * 
++00021  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
++00022  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++00023  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++00024  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
++00025  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++00026  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
++00027  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
++00028  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
++00029  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
++00030  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
++00031  * DAMAGE.
++00032  * ========================================================================== */
++00033 
++00034 #if !defined(__DWC_OTG_ATTR_H__)
++00035 #define __DWC_OTG_ATTR_H__
++00036 
++00040 extern struct device_attribute dev_attr_regoffset;
++00041 extern struct device_attribute dev_attr_regvalue;
++00042 
++00043 extern struct device_attribute dev_attr_mode;
++00044 extern struct device_attribute dev_attr_hnpcapable;
++00045 extern struct device_attribute dev_attr_srpcapable;
++00046 extern struct device_attribute dev_attr_hnp;
++00047 extern struct device_attribute dev_attr_srp;
++00048 extern struct device_attribute dev_attr_buspower;
++00049 extern struct device_attribute dev_attr_bussuspend;
++00050 extern struct device_attribute dev_attr_mode_ch_tim_en;
++00051 extern struct device_attribute dev_attr_fr_interval;
++00052 extern struct device_attribute dev_attr_busconnected;
++00053 extern struct device_attribute dev_attr_gotgctl;
++00054 extern struct device_attribute dev_attr_gusbcfg;
++00055 extern struct device_attribute dev_attr_grxfsiz;
++00056 extern struct device_attribute dev_attr_gnptxfsiz;
++00057 extern struct device_attribute dev_attr_gpvndctl;
++00058 extern struct device_attribute dev_attr_ggpio;
++00059 extern struct device_attribute dev_attr_guid;
++00060 extern struct device_attribute dev_attr_gsnpsid;
++00061 extern struct device_attribute dev_attr_devspeed;
++00062 extern struct device_attribute dev_attr_enumspeed;
++00063 extern struct device_attribute dev_attr_hptxfsiz;
++00064 extern struct device_attribute dev_attr_hprt0;
++00065 #ifdef CONFIG_USB_DWC_OTG_LPM
++00066 extern struct device_attribute dev_attr_lpm_response;
++00067 extern struct device_attribute devi_attr_sleep_status;
++00068 #endif
++00069 
++00070 void dwc_otg_attr_create(
++00071 #ifdef LM_INTERFACE
++00072                                 struct lm_device *dev
++00073 #elif  PCI_INTERFACE
++00074                                 struct pci_dev *dev
++00075 #endif
++00076     );
++00077 
++00078 void dwc_otg_attr_remove(
++00079 #ifdef LM_INTERFACE
++00080                                 struct lm_device *dev
++00081 #elif  PCI_INTERFACE
++00082                                 struct pci_dev *dev
++00083 #endif
++00084     );
++00085 #endif
++
Generated on Thu Oct 27 03:56:37 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
++doxygen 1.3.9.1
+ + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__attr_8h.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/dwc__otg__attr_8h.html 2013-07-26 19:31:20.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__attr_8h.html 2013-07-26 19:34:39.000000000 +0000 +@@ -2,105 +2,95 @@ + + DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_attr.h File Reference + +- + +- +-
+-
+-
+-
++ ++
Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
+

dwc_otg_attr.h File Reference

This file contains the interface to the Linux device attributes. More... +

+ +

+ Go to the source code of this file. + +- +- +- + +- ++ + + +- ++ + + + +- + +- + +- + +- + +- + +- + +- + +- + +- + +- ++ ++ ++ ++ + +- + +- + +- + +- + +- + +- + +- + +- + +- + +- + +- + +- + +

Defines

+-#define __DWC_OTG_ATTR_H__

Functions

+-void dwc_otg_attr_create ()
++void dwc_otg_attr_create ()
 Create the device files.
+-void dwc_otg_attr_remove ()
++void dwc_otg_attr_remove ()
 Remove the device files.

Variables

++
+ device_attribute dev_attr_regoffset
++
+ device_attribute dev_attr_regvalue
++
+ device_attribute dev_attr_mode
++
+ device_attribute dev_attr_hnpcapable
++
+ device_attribute dev_attr_srpcapable
++
+ device_attribute dev_attr_hnp
++
+ device_attribute dev_attr_srp
++
+ device_attribute dev_attr_buspower
++
+ device_attribute dev_attr_bussuspend
++
++device_attribute dev_attr_mode_ch_tim_en
++device_attribute dev_attr_fr_interval
+ device_attribute dev_attr_busconnected
++
+ device_attribute dev_attr_gotgctl
++
+ device_attribute dev_attr_gusbcfg
++
+ device_attribute dev_attr_grxfsiz
++
+ device_attribute dev_attr_gnptxfsiz
++
+ device_attribute dev_attr_gpvndctl
++
+ device_attribute dev_attr_ggpio
++
+ device_attribute dev_attr_guid
++
+ device_attribute dev_attr_gsnpsid
++
+ device_attribute dev_attr_devspeed
++
+ device_attribute dev_attr_enumspeed
++
+ device_attribute dev_attr_hptxfsiz
++
+ device_attribute dev_attr_hprt0
+@@ -109,8 +99,8 @@ +

+ +

+-Definition in file dwc_otg_attr.h.

Generated on Tue May 5 02:22:48 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++Definition in file dwc_otg_attr.h.
Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
++doxygen 1.3.9.1
+ + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__cfi_8c-source.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/dwc__otg__cfi_8c-source.html 2013-07-26 19:31:20.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__cfi_8c-source.html 2013-07-26 19:34:39.000000000 +0000 +@@ -2,1723 +2,1710 @@ + + DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_cfi.c Source File + +- + +- +-
+-
+-
+-
+-

dwc_otg_cfi.c

Go to the documentation of this file.
00001 /* ==========================================================================
+-00002  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
+-00003  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
+-00004  * otherwise expressly agreed to in writing between Synopsys and you.
+-00005  * 
+-00006  * The Software IS NOT an item of Licensed Software or Licensed Product under
+-00007  * any End User Software License Agreement or Agreement for Licensed Product
+-00008  * with Synopsys or any supplement thereto. You are permitted to use and
+-00009  * redistribute this Software in source and binary forms, with or without
+-00010  * modification, provided that redistributions of source code must retain this
+-00011  * notice. You may not view, use, disclose, copy or distribute this file or
+-00012  * any information contained herein except pursuant to this license grant from
+-00013  * Synopsys. If you do not agree with this notice, including the disclaimer
+-00014  * below, then you are not authorized to use the Software.
+-00015  * 
+-00016  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
+-00017  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+-00018  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+-00019  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
+-00020  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+-00021  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+-00022  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+-00023  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+-00024  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+-00025  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+-00026  * DAMAGE.
+-00027  * ========================================================================== */
+-00028 
+-00034 #ifdef DWC_UTE_CFI
+-00035 
+-00036 #include "dwc_otg_pcd.h"
+-00037 #include "dwc_otg_cfi.h"
+-00038 
+-00040 #define DWC_CONSTANT_CPU_TO_LE16(x) (x)
+-00041 
+-00042 extern dwc_otg_pcd_ep_t *get_ep_by_addr(dwc_otg_pcd_t * pcd, u16 wIndex);
+-00043 
+-00044 static int cfi_core_features_buf(uint8_t * buf, uint16_t buflen);
+-00045 static int cfi_get_feature_value(uint8_t * buf, uint16_t buflen,
+-00046                                  struct dwc_otg_pcd *pcd,
+-00047                                  struct cfi_usb_ctrlrequest *ctrl_req);
+-00048 static int cfi_set_feature_value(struct dwc_otg_pcd *pcd);
+-00049 static int cfi_ep_get_sg_val(uint8_t * buf, struct dwc_otg_pcd *pcd,
+-00050                              struct cfi_usb_ctrlrequest *req);
+-00051 static int cfi_ep_get_concat_val(uint8_t * buf, struct dwc_otg_pcd *pcd,
+-00052                                  struct cfi_usb_ctrlrequest *req);
+-00053 static int cfi_ep_get_align_val(uint8_t * buf, struct dwc_otg_pcd *pcd,
+-00054                                 struct cfi_usb_ctrlrequest *req);
+-00055 static int cfi_preproc_reset(struct dwc_otg_pcd *pcd,
+-00056                              struct cfi_usb_ctrlrequest *req);
+-00057 static void cfi_free_ep_bs_dyn_data(cfi_ep_t * cfiep);
+-00058 
+-00059 static uint16_t get_dfifo_size(dwc_otg_core_if_t * core_if);
+-00060 static int32_t get_rxfifo_size(dwc_otg_core_if_t * core_if, uint16_t wValue);
+-00061 static int32_t get_txfifo_size(struct dwc_otg_pcd *pcd, uint16_t wValue);
+-00062 
+-00063 static uint8_t resize_fifos(dwc_otg_core_if_t * core_if);
+-00064 
+-00066 static cfi_all_features_header_t all_props_desc_header = {
+-00067         .wVersion = DWC_CONSTANT_CPU_TO_LE16(0x100),
+-00068         .wCoreID = DWC_CONSTANT_CPU_TO_LE16(CFI_CORE_ID_OTG),
+-00069         .wNumFeatures = DWC_CONSTANT_CPU_TO_LE16(9),
+-00070 };
+-00071 
+-00073 static cfi_feature_desc_header_t prop_descs[] = {
+-00074 
+-00075         /* FT_ID_DMA_MODE */
+-00076         {
+-00077          .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_DMA_MODE),
+-00078          .bmAttributes = CFI_FEATURE_ATTR_RW,
+-00079          .wDataLength = DWC_CONSTANT_CPU_TO_LE16(1),
+-00080          },
+-00081 
+-00082         /* FT_ID_DMA_BUFFER_SETUP */
+-00083         {
+-00084          .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_DMA_BUFFER_SETUP),
+-00085          .bmAttributes = CFI_FEATURE_ATTR_RW,
+-00086          .wDataLength = DWC_CONSTANT_CPU_TO_LE16(6),
+-00087          },
+-00088 
+-00089         /* FT_ID_DMA_BUFF_ALIGN */
+-00090         {
+-00091          .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_DMA_BUFF_ALIGN),
+-00092          .bmAttributes = CFI_FEATURE_ATTR_RW,
+-00093          .wDataLength = DWC_CONSTANT_CPU_TO_LE16(2),
+-00094          },
+-00095 
+-00096         /* FT_ID_DMA_CONCAT_SETUP */
+-00097         {
+-00098          .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_DMA_CONCAT_SETUP),
+-00099          .bmAttributes = CFI_FEATURE_ATTR_RW,
+-00100          //.wDataLength  = DWC_CONSTANT_CPU_TO_LE16(6),
+-00101          },
+-00102 
+-00103         /* FT_ID_DMA_CIRCULAR */
+-00104         {
+-00105          .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_DMA_CIRCULAR),
+-00106          .bmAttributes = CFI_FEATURE_ATTR_RW,
+-00107          .wDataLength = DWC_CONSTANT_CPU_TO_LE16(6),
+-00108          },
+-00109 
+-00110         /* FT_ID_THRESHOLD_SETUP */
+-00111         {
+-00112          .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_THRESHOLD_SETUP),
+-00113          .bmAttributes = CFI_FEATURE_ATTR_RW,
+-00114          .wDataLength = DWC_CONSTANT_CPU_TO_LE16(6),
+-00115          },
+-00116 
+-00117         /* FT_ID_DFIFO_DEPTH */
+-00118         {
+-00119          .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_DFIFO_DEPTH),
+-00120          .bmAttributes = CFI_FEATURE_ATTR_RO,
+-00121          .wDataLength = DWC_CONSTANT_CPU_TO_LE16(2),
+-00122          },
+-00123 
+-00124         /* FT_ID_TX_FIFO_DEPTH */
+-00125         {
+-00126          .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_TX_FIFO_DEPTH),
+-00127          .bmAttributes = CFI_FEATURE_ATTR_RW,
+-00128          .wDataLength = DWC_CONSTANT_CPU_TO_LE16(2),
+-00129          },
+-00130 
+-00131         /* FT_ID_RX_FIFO_DEPTH */
+-00132         {
+-00133          .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_RX_FIFO_DEPTH),
+-00134          .bmAttributes = CFI_FEATURE_ATTR_RW,
+-00135          .wDataLength = DWC_CONSTANT_CPU_TO_LE16(2),
+-00136          }
+-00137 };
+-00138 
+-00140 cfi_string_t prop_name_table[] = {
+-00141         {FT_ID_DMA_MODE, "dma_mode"},
+-00142         {FT_ID_DMA_BUFFER_SETUP, "buffer_setup"},
+-00143         {FT_ID_DMA_BUFF_ALIGN, "buffer_align"},
+-00144         {FT_ID_DMA_CONCAT_SETUP, "concat_setup"},
+-00145         {FT_ID_DMA_CIRCULAR, "buffer_circular"},
+-00146         {FT_ID_THRESHOLD_SETUP, "threshold_setup"},
+-00147         {FT_ID_DFIFO_DEPTH, "dfifo_depth"},
+-00148         {FT_ID_TX_FIFO_DEPTH, "txfifo_depth"},
+-00149         {FT_ID_RX_FIFO_DEPTH, "rxfifo_depth"},
+-00150         {}
+-00151 };
+-00152 
+-00153 /************************************************************************/
+-00154 
+-00160 const uint8_t *get_prop_name(uint16_t prop_id, int *len)
+-00161 {
+-00162         cfi_string_t *pstr;
+-00163         *len = 0;
+-00164 
+-00165         for (pstr = prop_name_table; pstr && pstr->s; pstr++) {
+-00166                 if (pstr->id == prop_id) {
+-00167                         *len = DWC_STRLEN(pstr->s);
+-00168                         return pstr->s;
+-00169                 }
+-00170         }
+-00171         return NULL;
+-00172 }
+-00173 
+-00179 int cfi_setup(struct dwc_otg_pcd *pcd, struct cfi_usb_ctrlrequest *ctrl)
+-00180 {
+-00181         int retval = 0;
+-00182         dwc_otg_pcd_ep_t *ep = NULL;
+-00183         cfiobject_t *cfi = pcd->cfi;
+-00184         struct dwc_otg_core_if *coreif = GET_CORE_IF(pcd);
+-00185         uint16_t wLen = DWC_LE16_TO_CPU(&ctrl->wLength);
+-00186         uint16_t wValue = DWC_LE16_TO_CPU(&ctrl->wValue);
+-00187         uint16_t wIndex = DWC_LE16_TO_CPU(&ctrl->wIndex);
+-00188         uint32_t regaddr = 0;
+-00189         uint32_t regval = 0;
+-00190 
+-00191         /* Save this Control Request in the CFI object. 
+-00192          * The data field will be assigned in the data stage completion CB function.
+-00193          */
+-00194         cfi->ctrl_req = *ctrl;
+-00195         cfi->ctrl_req.data = NULL;
+-00196 
+-00197         cfi->need_gadget_att = 0;
+-00198         cfi->need_status_in_complete = 0;
+-00199 
+-00200         switch (ctrl->bRequest) {
+-00201         case VEN_CORE_GET_FEATURES:
+-00202                 retval = cfi_core_features_buf(cfi->buf_in.buf, CFI_IN_BUF_LEN);
+-00203                 if (retval >= 0) {
+-00204                         //dump_msg(cfi->buf_in.buf, retval);
+-00205                         ep = &pcd->ep0;
+-00206 
+-00207                         retval = min((uint16_t) retval, wLen);
+-00208                         /* Transfer this buffer to the host through the EP0-IN EP */
+-00209                         ep->dwc_ep.dma_addr = cfi->buf_in.addr;
+-00210                         ep->dwc_ep.start_xfer_buff = cfi->buf_in.buf;
+-00211                         ep->dwc_ep.xfer_buff = cfi->buf_in.buf;
+-00212                         ep->dwc_ep.xfer_len = retval;
+-00213                         ep->dwc_ep.xfer_count = 0;
+-00214                         ep->dwc_ep.sent_zlp = 0;
+-00215                         ep->dwc_ep.total_len = ep->dwc_ep.xfer_len;
+-00216 
+-00217                         pcd->ep0_pending = 1;
+-00218                         dwc_otg_ep0_start_transfer(coreif, &ep->dwc_ep);
+-00219                 }
+-00220                 retval = 0;
+-00221                 break;
+-00222 
+-00223         case VEN_CORE_GET_FEATURE:
+-00224                 CFI_INFO("VEN_CORE_GET_FEATURE\n");
+-00225                 retval = cfi_get_feature_value(cfi->buf_in.buf, CFI_IN_BUF_LEN,
+-00226                                                pcd, ctrl);
+-00227                 if (retval >= 0) {
+-00228                         ep = &pcd->ep0;
+-00229 
+-00230                         retval = min((uint16_t) retval, wLen);
+-00231                         /* Transfer this buffer to the host through the EP0-IN EP */
+-00232                         ep->dwc_ep.dma_addr = cfi->buf_in.addr;
+-00233                         ep->dwc_ep.start_xfer_buff = cfi->buf_in.buf;
+-00234                         ep->dwc_ep.xfer_buff = cfi->buf_in.buf;
+-00235                         ep->dwc_ep.xfer_len = retval;
+-00236                         ep->dwc_ep.xfer_count = 0;
+-00237                         ep->dwc_ep.sent_zlp = 0;
+-00238                         ep->dwc_ep.total_len = ep->dwc_ep.xfer_len;
+-00239 
+-00240                         pcd->ep0_pending = 1;
+-00241                         dwc_otg_ep0_start_transfer(coreif, &ep->dwc_ep);
+-00242                 }
+-00243                 CFI_INFO("VEN_CORE_GET_FEATURE=%d\n", retval);
+-00244                 dump_msg(cfi->buf_in.buf, retval);
+-00245                 break;
+-00246 
+-00247         case VEN_CORE_SET_FEATURE:
+-00248                 CFI_INFO("VEN_CORE_SET_FEATURE\n");
+-00249                 /* Set up an XFER to get the data stage of the control request,
+-00250                  * which is the new value of the feature to be modified.
+-00251                  */
+-00252                 ep = &pcd->ep0;
+-00253                 ep->dwc_ep.is_in = 0;
+-00254                 ep->dwc_ep.dma_addr = cfi->buf_out.addr;
+-00255                 ep->dwc_ep.start_xfer_buff = cfi->buf_out.buf;
+-00256                 ep->dwc_ep.xfer_buff = cfi->buf_out.buf;
+-00257                 ep->dwc_ep.xfer_len = wLen;
+-00258                 ep->dwc_ep.xfer_count = 0;
+-00259                 ep->dwc_ep.sent_zlp = 0;
+-00260                 ep->dwc_ep.total_len = ep->dwc_ep.xfer_len;
+-00261 
+-00262                 pcd->ep0_pending = 1;
+-00263                 /* Read the control write's data stage */
+-00264                 dwc_otg_ep0_start_transfer(coreif, &ep->dwc_ep);
+-00265                 retval = 0;
+-00266                 break;
+-00267 
+-00268         case VEN_CORE_RESET_FEATURES:
+-00269                 CFI_INFO("VEN_CORE_RESET_FEATURES\n");
+-00270                 cfi->need_gadget_att = 1;
+-00271                 cfi->need_status_in_complete = 1;
+-00272                 retval = cfi_preproc_reset(pcd, ctrl);
+-00273                 CFI_INFO("VEN_CORE_RESET_FEATURES = (%d)\n", retval);
+-00274                 break;
+-00275 
+-00276         case VEN_CORE_ACTIVATE_FEATURES:
+-00277                 CFI_INFO("VEN_CORE_ACTIVATE_FEATURES\n");
+-00278                 break;
+-00279 
+-00280         case VEN_CORE_READ_REGISTER:
+-00281                 CFI_INFO("VEN_CORE_READ_REGISTER\n");
+-00282                 /* wValue optionally contains the HI WORD of the register offset and
+-00283                  * wIndex contains the LOW WORD of the register offset 
+-00284                  */
+-00285                 if (wValue == 0) {
+-00286                         /* @TODO - MAS - fix the access to the base field */
+-00287                         regaddr = 0;
+-00288                         //regaddr = (uint32_t) pcd->otg_dev->base;
+-00289                         //GET_CORE_IF(pcd)->co
+-00290                         regaddr |= wIndex;
+-00291                 } else {
+-00292                         regaddr = (wValue << 16) | wIndex;
+-00293                 }
+-00294 
+-00295                 /* Read a 32-bit value of the memory at the regaddr */
+-00296                 regval = dwc_read_reg32((uint32_t *) regaddr);
+-00297 
+-00298                 ep = &pcd->ep0;
+-00299                 dwc_memcpy(cfi->buf_in.buf, &regval, sizeof(uint32_t));
+-00300                 ep->dwc_ep.is_in = 1;
+-00301                 ep->dwc_ep.dma_addr = cfi->buf_in.addr;
+-00302                 ep->dwc_ep.start_xfer_buff = cfi->buf_in.buf;
+-00303                 ep->dwc_ep.xfer_buff = cfi->buf_in.buf;
+-00304                 ep->dwc_ep.xfer_len = wLen;
+-00305                 ep->dwc_ep.xfer_count = 0;
+-00306                 ep->dwc_ep.sent_zlp = 0;
+-00307                 ep->dwc_ep.total_len = ep->dwc_ep.xfer_len;
+-00308 
+-00309                 pcd->ep0_pending = 1;
+-00310                 dwc_otg_ep0_start_transfer(coreif, &ep->dwc_ep);
+-00311                 cfi->need_gadget_att = 0;
+-00312                 retval = 0;
+-00313                 break;
+-00314 
+-00315         case VEN_CORE_WRITE_REGISTER:
+-00316                 CFI_INFO("VEN_CORE_WRITE_REGISTER\n");
+-00317                 /* Set up an XFER to get the data stage of the control request,
+-00318                  * which is the new value of the register to be modified.
+-00319                  */
+-00320                 ep = &pcd->ep0;
+-00321                 ep->dwc_ep.is_in = 0;
+-00322                 ep->dwc_ep.dma_addr = cfi->buf_out.addr;
+-00323                 ep->dwc_ep.start_xfer_buff = cfi->buf_out.buf;
+-00324                 ep->dwc_ep.xfer_buff = cfi->buf_out.buf;
+-00325                 ep->dwc_ep.xfer_len = wLen;
+-00326                 ep->dwc_ep.xfer_count = 0;
+-00327                 ep->dwc_ep.sent_zlp = 0;
+-00328                 ep->dwc_ep.total_len = ep->dwc_ep.xfer_len;
+-00329 
+-00330                 pcd->ep0_pending = 1;
+-00331                 /* Read the control write's data stage */
+-00332                 dwc_otg_ep0_start_transfer(coreif, &ep->dwc_ep);
+-00333                 retval = 0;
+-00334                 break;
+-00335 
+-00336         default:
+-00337                 retval = -DWC_E_NOT_SUPPORTED;
+-00338                 break;
+-00339         }
+-00340 
+-00341         return retval;
+-00342 }
+-00343 
+-00355 static int cfi_core_features_buf(uint8_t * buf, uint16_t buflen)
+-00356 {
+-00357         cfi_feature_desc_header_t *prop_hdr = prop_descs;
+-00358         cfi_feature_desc_header_t *prop;
+-00359         cfi_all_features_header_t *all_props_hdr = &all_props_desc_header;
+-00360         cfi_all_features_header_t *tmp;
+-00361         uint8_t *tmpbuf = buf;
+-00362         const uint8_t *pname = NULL;
+-00363         int i, j, namelen = 0, totlen;
+-00364 
+-00365         /* Prepare and copy the core features into the buffer */
+-00366         CFI_INFO("%s:\n", __func__);
+-00367 
+-00368         tmp = (cfi_all_features_header_t *) tmpbuf;
+-00369         *tmp = *all_props_hdr;
+-00370         tmpbuf += CFI_ALL_FEATURES_HDR_LEN;
+-00371 
+-00372         j = sizeof(prop_descs) / sizeof(cfi_all_features_header_t);
+-00373         for (i = 0; i < j; i++, prop_hdr++) {
+-00374                 pname = get_prop_name(prop_hdr->wFeatureID, &namelen);
+-00375                 prop = (cfi_feature_desc_header_t *) tmpbuf;
+-00376                 *prop = *prop_hdr;
+-00377 
+-00378                 prop->bNameLen = namelen;
+-00379                 prop->wLength =
+-00380                     DWC_CONSTANT_CPU_TO_LE16(CFI_FEATURE_DESC_HDR_LEN +
+-00381                                              namelen);
+-00382 
+-00383                 tmpbuf += CFI_FEATURE_DESC_HDR_LEN;
+-00384                 dwc_memcpy(tmpbuf, pname, namelen);
+-00385                 tmpbuf += namelen;
+-00386         }
+-00387 
+-00388         totlen = tmpbuf - buf;
+-00389 
+-00390         if (totlen > 0) {
+-00391                 tmp = (cfi_all_features_header_t *) buf;
+-00392                 tmp->wTotalLen = DWC_CONSTANT_CPU_TO_LE16(totlen);
+-00393         }
+-00394 
+-00395         return totlen;
+-00396 }
+-00397 
+-00401 static void cfi_release(cfiobject_t * cfiobj)
+-00402 {
+-00403         cfi_ep_t *cfiep;
+-00404         dwc_list_link_t *tmp;
+-00405 
+-00406         CFI_INFO("%s\n", __func__);
+-00407 
+-00408         if (cfiobj->buf_in.buf) {
+-00409                 dwc_dma_free(CFI_IN_BUF_LEN, cfiobj->buf_in.buf,
+-00410                              cfiobj->buf_in.addr);
+-00411                 cfiobj->buf_in.buf = NULL;
+-00412         }
+-00413 
+-00414         if (cfiobj->buf_out.buf) {
+-00415                 dwc_dma_free(CFI_OUT_BUF_LEN, cfiobj->buf_out.buf,
+-00416                              cfiobj->buf_out.addr);
+-00417                 cfiobj->buf_out.buf = NULL;
+-00418         }
+-00419 
+-00420         /* Free the Buffer Setup values for each EP */
+-00421         //list_for_each_entry(cfiep, &cfiobj->active_eps, lh) {
+-00422         DWC_LIST_FOREACH(tmp, &cfiobj->active_eps) {
+-00423                 cfiep = DWC_LIST_ENTRY(tmp, struct cfi_ep, lh);
+-00424                 cfi_free_ep_bs_dyn_data(cfiep);
+-00425         }
+-00426 }
+-00427 
+-00431 static void cfi_free_ep_bs_dyn_data(cfi_ep_t * cfiep)
+-00432 {
+-00433         if (cfiep->bm_sg) {
+-00434                 dwc_free(cfiep->bm_sg);
+-00435                 cfiep->bm_sg = NULL;
+-00436         }
+-00437 
+-00438         if (cfiep->bm_align) {
+-00439                 dwc_free(cfiep->bm_align);
+-00440                 cfiep->bm_align = NULL;
+-00441         }
+-00442 
+-00443         if (cfiep->bm_concat) {
+-00444                 if (NULL != cfiep->bm_concat->wTxBytes) {
+-00445                         dwc_free(cfiep->bm_concat->wTxBytes);
+-00446                         cfiep->bm_concat->wTxBytes = NULL;
+-00447                 }
+-00448                 dwc_free(cfiep->bm_concat);
+-00449                 cfiep->bm_concat = NULL;
+-00450         }
+-00451 }
+-00452 
+-00458 static int cfi_ep_init_defaults(struct dwc_otg_pcd *pcd, cfi_ep_t * cfiep)
+-00459 {
+-00460         int retval = 0;
+-00461 
+-00462         cfiep->bm_sg = dwc_alloc(sizeof(ddma_sg_buffer_setup_t));
+-00463         if (NULL == cfiep->bm_sg) {
+-00464                 CFI_INFO("Failed to allocate memory for SG feature value\n");
+-00465                 return -DWC_E_NO_MEMORY;
+-00466         }
+-00467         dwc_memset(cfiep->bm_sg, 0, sizeof(ddma_sg_buffer_setup_t));
+-00468 
+-00469         /* For the Concatenation feature's default value we do not allocate
+-00470          * memory for the wTxBytes field - it will be done in the set_feature_value
+-00471          * request handler.
+-00472          */
+-00473         cfiep->bm_concat = dwc_alloc(sizeof(ddma_concat_buffer_setup_t));
+-00474         if (NULL == cfiep->bm_concat) {
+-00475                 CFI_INFO
+-00476                     ("Failed to allocate memory for CONCATENATION feature value\n");
+-00477                 dwc_free(cfiep->bm_sg);
+-00478                 return -DWC_E_NO_MEMORY;
+-00479         }
+-00480         dwc_memset(cfiep->bm_concat, 0, sizeof(ddma_concat_buffer_setup_t));
+-00481 
+-00482         cfiep->bm_align = dwc_alloc(sizeof(ddma_align_buffer_setup_t));
+-00483         if (NULL == cfiep->bm_align) {
+-00484                 CFI_INFO
+-00485                     ("Failed to allocate memory for Alignment feature value\n");
+-00486                 dwc_free(cfiep->bm_sg);
+-00487                 dwc_free(cfiep->bm_concat);
+-00488                 return -DWC_E_NO_MEMORY;
+-00489         }
+-00490         dwc_memset(cfiep->bm_align, 0, sizeof(ddma_align_buffer_setup_t));
+-00491 
+-00492         return retval;
+-00493 }
+-00494 
+-00506 static int cfi_ep_enable(struct cfiobject *cfi, struct dwc_otg_pcd *pcd,
+-00507                          struct dwc_otg_pcd_ep *ep)
+-00508 {
+-00509         cfi_ep_t *cfiep;
+-00510         int retval = -DWC_E_NOT_SUPPORTED;
+-00511 
+-00512         CFI_INFO("%s: epname=%s; epnum=0x%02x\n", __func__,
+-00513                  "EP_" /*ep->ep.name */ , ep->desc->bEndpointAddress);
+-00514         /* MAS - Check whether this endpoint already is in the list */
+-00515         cfiep = get_cfi_ep_by_pcd_ep(cfi, ep);
+-00516 
+-00517         if (NULL == cfiep) {
+-00518                 /* Allocate a cfi_ep_t object */
+-00519                 cfiep = dwc_alloc(sizeof(cfi_ep_t));
+-00520                 if (NULL == cfiep) {
+-00521                         CFI_INFO
+-00522                             ("Unable to allocate memory for <cfiep> in function %s\n",
+-00523                              __func__);
+-00524                         return -DWC_E_NO_MEMORY;
+-00525                 }
+-00526                 dwc_memset(cfiep, 0, sizeof(cfi_ep_t));
+-00527 
+-00528                 /* Save the dwc_otg_pcd_ep pointer in the cfiep object */
+-00529                 cfiep->ep = ep;
+-00530 
+-00531                 /* Allocate the DMA Descriptors chain of MAX_DMA_DESCS_PER_EP count */
+-00532                 ep->dwc_ep.descs =
+-00533                     dwc_dma_alloc(MAX_DMA_DESCS_PER_EP *
+-00534                                   sizeof(dwc_otg_dma_desc_t),
+-00535                                   &ep->dwc_ep.descs_dma_addr);
+-00536 
+-00537                 if (NULL == ep->dwc_ep.descs) {
+-00538                         dwc_free(cfiep);
+-00539                         return -DWC_E_NO_MEMORY;
+-00540                 }
+-00541 
+-00542                 DWC_LIST_INIT(&cfiep->lh);
+-00543 
+-00544                 /* Set the buffer mode to BM_STANDARD. It will be modified 
+-00545                  * when building descriptors for a specific buffer mode */
+-00546                 ep->dwc_ep.buff_mode = BM_STANDARD;
+-00547 
+-00548                 /* Create and initialize the default values for this EP's Buffer modes */
+-00549                 if ((retval = cfi_ep_init_defaults(pcd, cfiep)) < 0)
+-00550                         return retval;
+-00551 
+-00552                 /* Add the cfi_ep_t object to the CFI object's list of active endpoints */
+-00553                 DWC_LIST_INSERT_TAIL(&cfi->active_eps, &cfiep->lh);
+-00554                 retval = 0;
+-00555         } else {                /* The sought EP already is in the list */
+-00556                 CFI_INFO("%s: The sought EP already is in the list\n",
+-00557                          __func__);
+-00558         }
+-00559 
+-00560         return retval;
+-00561 }
+-00562 
+-00568 static int cfi_ctrl_write_complete(struct cfiobject *cfi,
+-00569                                    struct dwc_otg_pcd *pcd)
+-00570 {
+-00571         uint32_t addr, reg_value;
+-00572         uint16_t wIndex, wValue;
+-00573         uint8_t bRequest;
+-00574         uint8_t *buf = cfi->buf_out.buf;
+-00575         //struct usb_ctrlrequest *ctrl_req = &cfi->ctrl_req_saved;
+-00576         struct cfi_usb_ctrlrequest *ctrl_req = &cfi->ctrl_req;
+-00577         int retval = -DWC_E_NOT_SUPPORTED;
+-00578 
+-00579         CFI_INFO("%s\n", __func__);
+-00580 
+-00581         bRequest = ctrl_req->bRequest;
+-00582         wIndex = DWC_CONSTANT_CPU_TO_LE16(ctrl_req->wIndex);
+-00583         wValue = DWC_CONSTANT_CPU_TO_LE16(ctrl_req->wValue);
+-00584 
+-00585         /* 
+-00586          * Save the pointer to the data stage in the ctrl_req's <data> field.
+-00587          * The request should be already saved in the command stage by now.
+-00588          */
+-00589         ctrl_req->data = cfi->buf_out.buf;
+-00590         cfi->need_status_in_complete = 0;
+-00591         cfi->need_gadget_att = 0;
+-00592 
+-00593         switch (bRequest) {
+-00594         case VEN_CORE_WRITE_REGISTER:
+-00595                 /* The buffer contains raw data of the new value for the register */
+-00596                 reg_value = *((uint32_t *) buf);
+-00597                 if (wValue == 0) {
+-00598                         addr = 0;
+-00599                         //addr = (uint32_t) pcd->otg_dev->base;
+-00600                         addr += wIndex;
+-00601                 } else {
+-00602                         addr = (wValue << 16) | wIndex;
+-00603                 }
+-00604 
+-00605                 //writel(reg_value, addr);
+-00606 
+-00607                 retval = 0;
+-00608                 cfi->need_status_in_complete = 1;
+-00609                 break;
+-00610 
+-00611         case VEN_CORE_SET_FEATURE:
+-00612                 /* The buffer contains raw data of the new value of the feature */
+-00613                 retval = cfi_set_feature_value(pcd);
+-00614                 if (retval < 0)
+-00615                         return retval;
+-00616 
+-00617                 cfi->need_status_in_complete = 1;
+-00618                 break;
+-00619 
+-00620         default:
+-00621                 break;
+-00622         }
+-00623 
+-00624         return retval;
+-00625 }
+-00626 
+-00630 static void cfi_build_sg_descs(struct cfiobject *cfi, cfi_ep_t * cfiep,
+-00631                                dwc_otg_pcd_request_t * req)
+-00632 {
+-00633         struct dwc_otg_pcd_ep *ep = cfiep->ep;
+-00634         ddma_sg_buffer_setup_t *sgval = cfiep->bm_sg;
+-00635         struct dwc_otg_dma_desc *desc = cfiep->ep->dwc_ep.descs;
+-00636         struct dwc_otg_dma_desc *desc_last = cfiep->ep->dwc_ep.descs;
+-00637         dma_addr_t buff_addr = req->dma;
+-00638         int i;
+-00639         uint32_t txsize, off;
+-00640 
+-00641         txsize = sgval->wSize;
+-00642         off = sgval->bOffset;
+-00643 
+-00644 //      CFI_INFO("%s: %s TXSIZE=0x%08x; OFFSET=0x%08x\n", 
+-00645 //              __func__, cfiep->ep->ep.name, txsize, off);
+-00646 
+-00647         for (i = 0; i < sgval->bCount; i++) {
+-00648                 desc->status.b.bs = BS_HOST_BUSY;
+-00649                 desc->buf = buff_addr;
+-00650                 desc->status.b.l = 0;
+-00651                 desc->status.b.ioc = 0;
+-00652                 desc->status.b.sp = 0;
+-00653                 desc->status.b.bytes = txsize;
+-00654                 desc->status.b.bs = BS_HOST_READY;
+-00655 
+-00656                 /* Set the next address of the buffer */
+-00657                 buff_addr += txsize + off;
+-00658                 desc_last = desc;
+-00659                 desc++;
+-00660         }
+-00661 
+-00662         /* Set the last, ioc and sp bits on the Last DMA Descriptor */
+-00663         desc_last->status.b.l = 1;
+-00664         desc_last->status.b.ioc = 1;
+-00665         desc_last->status.b.sp = ep->dwc_ep.sent_zlp;
+-00666         /* Save the last DMA descriptor pointer */
+-00667         cfiep->dma_desc_last = desc_last;
+-00668         cfiep->desc_count = sgval->bCount;
+-00669 }
+-00670 
+-00674 static void cfi_build_concat_descs(struct cfiobject *cfi, cfi_ep_t * cfiep,
+-00675                                    dwc_otg_pcd_request_t * req)
+-00676 {
+-00677         struct dwc_otg_pcd_ep *ep = cfiep->ep;
+-00678         ddma_concat_buffer_setup_t *concatval = cfiep->bm_concat;
+-00679         struct dwc_otg_dma_desc *desc = cfiep->ep->dwc_ep.descs;
+-00680         struct dwc_otg_dma_desc *desc_last = cfiep->ep->dwc_ep.descs;
+-00681         dma_addr_t buff_addr = req->dma;
+-00682         int i;
+-00683         uint16_t *txsize;
+-00684 
+-00685         txsize = concatval->wTxBytes;
+-00686 
+-00687         for (i = 0; i < concatval->hdr.bDescCount; i++) {
+-00688                 desc->buf = buff_addr;
+-00689                 desc->status.b.bs = BS_HOST_BUSY;
+-00690                 desc->status.b.l = 0;
+-00691                 desc->status.b.ioc = 0;
+-00692                 desc->status.b.sp = 0;
+-00693                 desc->status.b.bytes = *txsize;
+-00694                 desc->status.b.bs = BS_HOST_READY;
+-00695 
+-00696                 txsize++;
+-00697                 /* Set the next address of the buffer */
+-00698                 buff_addr += UGETW(ep->desc->wMaxPacketSize);
+-00699                 desc_last = desc;
+-00700                 desc++;
+-00701         }
+-00702 
+-00703         /* Set the last, ioc and sp bits on the Last DMA Descriptor */
+-00704         desc_last->status.b.l = 1;
+-00705         desc_last->status.b.ioc = 1;
+-00706         desc_last->status.b.sp = ep->dwc_ep.sent_zlp;
+-00707         cfiep->dma_desc_last = desc_last;
+-00708         cfiep->desc_count = concatval->hdr.bDescCount;
+-00709 }
+-00710 
+-00714 static void cfi_build_circ_descs(struct cfiobject *cfi, cfi_ep_t * cfiep,
+-00715                                  dwc_otg_pcd_request_t * req)
+-00716 {
+-00717         /* @todo: MAS - add implementation when this feature needs to be tested */
+-00718 }
+-00719 
+-00723 static void cfi_build_align_descs(struct cfiobject *cfi, cfi_ep_t * cfiep,
+-00724                                   dwc_otg_pcd_request_t * req)
+-00725 {
+-00726         struct dwc_otg_pcd_ep *ep = cfiep->ep;
+-00727         ddma_align_buffer_setup_t *alignval = cfiep->bm_align;
+-00728         struct dwc_otg_dma_desc *desc = cfiep->ep->dwc_ep.descs;
+-00729         dma_addr_t buff_addr = req->dma;
+-00730 
+-00731         desc->status.b.bs = BS_HOST_BUSY;
+-00732         desc->status.b.l = 1;
+-00733         desc->status.b.ioc = 1;
+-00734         desc->status.b.sp = ep->dwc_ep.sent_zlp;
+-00735         desc->status.b.bytes = req->length;
+-00736         /* Adjust the buffer alignment */
+-00737         desc->buf = (buff_addr + alignval->bAlign);
+-00738         desc->status.b.bs = BS_HOST_READY;
+-00739         cfiep->dma_desc_last = desc;
+-00740         cfiep->desc_count = 1;
+-00741 }
+-00742 
+-00747 static void cfi_build_descriptors(struct cfiobject *cfi,
+-00748                                   struct dwc_otg_pcd *pcd,
+-00749                                   struct dwc_otg_pcd_ep *ep,
+-00750                                   dwc_otg_pcd_request_t * req)
+-00751 {
+-00752         cfi_ep_t *cfiep;
+-00753 
+-00754         /* Get the cfiep by the dwc_otg_pcd_ep */
+-00755         cfiep = get_cfi_ep_by_pcd_ep(cfi, ep);
+-00756         if (NULL == cfiep) {
+-00757                 CFI_INFO("%s: Unable to find a matching active endpoint\n",
+-00758                          __func__);
+-00759                 return;
+-00760         }
+-00761 
+-00762         cfiep->xfer_len = req->length;
+-00763 
+-00764         /* Iterate through all the DMA descriptors */
+-00765         switch (cfiep->ep->dwc_ep.buff_mode) {
+-00766         case BM_SG:
+-00767                 cfi_build_sg_descs(cfi, cfiep, req);
+-00768                 break;
+-00769 
+-00770         case BM_CONCAT:
+-00771                 cfi_build_concat_descs(cfi, cfiep, req);
+-00772                 break;
+-00773 
+-00774         case BM_CIRCULAR:
+-00775                 cfi_build_circ_descs(cfi, cfiep, req);
+-00776                 break;
+-00777 
+-00778         case BM_ALIGN:
+-00779                 cfi_build_align_descs(cfi, cfiep, req);
+-00780                 break;
+-00781 
+-00782         default:
+-00783                 break;
+-00784         }
+-00785 }
+-00786 
+-00790 static void *cfi_ep_alloc_buf(struct cfiobject *cfi, struct dwc_otg_pcd *pcd,
+-00791                               struct dwc_otg_pcd_ep *ep, dma_addr_t * dma,
+-00792                               unsigned size, gfp_t flags)
+-00793 {
+-00794         return dwc_dma_alloc(size, dma);
+-00795 }
+-00796 
+-00800 int init_cfi(cfiobject_t * cfiobj)
+-00801 {
+-00802         CFI_INFO("%s\n", __func__);
+-00803 
+-00804         /* Allocate a buffer for IN XFERs */
+-00805         cfiobj->buf_in.buf =
+-00806             dwc_dma_alloc(CFI_IN_BUF_LEN, &cfiobj->buf_in.addr);
+-00807         if (NULL == cfiobj->buf_in.buf) {
+-00808                 CFI_INFO("Unable to allocate buffer for INs\n");
+-00809                 return -DWC_E_NO_MEMORY;
+-00810         }
+-00811 
+-00812         /* Allocate a buffer for OUT XFERs */
+-00813         cfiobj->buf_out.buf =
+-00814             dwc_dma_alloc(CFI_OUT_BUF_LEN, &cfiobj->buf_out.addr);
+-00815         if (NULL == cfiobj->buf_out.buf) {
+-00816                 CFI_INFO("Unable to allocate buffer for OUT\n");
+-00817                 return -DWC_E_NO_MEMORY;
+-00818         }
+-00819 
+-00820         /* Initialize the callback function pointers */
+-00821         cfiobj->ops.release = cfi_release;
+-00822         cfiobj->ops.ep_enable = cfi_ep_enable;
+-00823         cfiobj->ops.ctrl_write_complete = cfi_ctrl_write_complete;
+-00824         cfiobj->ops.build_descriptors = cfi_build_descriptors;
+-00825         cfiobj->ops.ep_alloc_buf = cfi_ep_alloc_buf;
+-00826 
+-00827         /* Initialize the list of active endpoints in the CFI object */
+-00828         DWC_LIST_INIT(&cfiobj->active_eps);
+-00829 
+-00830         return 0;
+-00831 }
+-00832 
+-00838 static int cfi_get_feature_value(uint8_t * buf, uint16_t buflen,
+-00839                                  struct dwc_otg_pcd *pcd,
+-00840                                  struct cfi_usb_ctrlrequest *ctrl_req)
+-00841 {
+-00842         int retval = -DWC_E_NOT_SUPPORTED;
+-00843         struct dwc_otg_core_if *coreif = GET_CORE_IF(pcd);
+-00844         uint16_t dfifo, rxfifo, txfifo;
+-00845 
+-00846         switch (ctrl_req->wIndex) {
+-00847                 /* Whether the DDMA is enabled or not */
+-00848         case FT_ID_DMA_MODE:
+-00849                 *buf = (coreif->dma_enable && coreif->dma_desc_enable) ? 1 : 0;
+-00850                 retval = 1;
+-00851                 break;
+-00852 
+-00853         case FT_ID_DMA_BUFFER_SETUP:
+-00854                 retval = cfi_ep_get_sg_val(buf, pcd, ctrl_req);
+-00855                 break;
+-00856 
+-00857         case FT_ID_DMA_BUFF_ALIGN:
+-00858                 retval = cfi_ep_get_align_val(buf, pcd, ctrl_req);
+-00859                 break;
+-00860 
+-00861         case FT_ID_DMA_CONCAT_SETUP:
+-00862                 retval = cfi_ep_get_concat_val(buf, pcd, ctrl_req);
+-00863                 break;
+-00864 
+-00865         case FT_ID_DMA_CIRCULAR:
+-00866                 CFI_INFO("GetFeature value (FT_ID_DMA_CIRCULAR)\n");
+-00867                 break;
+-00868 
+-00869         case FT_ID_THRESHOLD_SETUP:
+-00870                 CFI_INFO("GetFeature value (FT_ID_THRESHOLD_SETUP)\n");
+-00871                 break;
+-00872 
+-00873         case FT_ID_DFIFO_DEPTH:
+-00874                 dfifo = get_dfifo_size(coreif);
+-00875                 *((uint16_t *) buf) = dfifo;
+-00876                 retval = sizeof(uint16_t);
+-00877                 break;
+-00878 
+-00879         case FT_ID_TX_FIFO_DEPTH:
+-00880                 retval = get_txfifo_size(pcd, ctrl_req->wValue);
+-00881                 if (retval >= 0) {
+-00882                         txfifo = retval;
+-00883                         *((uint16_t *) buf) = txfifo;
+-00884                         retval = sizeof(uint16_t);
+-00885                 }
+-00886                 break;
+-00887 
+-00888         case FT_ID_RX_FIFO_DEPTH:
+-00889                 retval = get_rxfifo_size(coreif, ctrl_req->wValue);
+-00890                 if (retval >= 0) {
+-00891                         rxfifo = retval;
+-00892                         *((uint16_t *) buf) = rxfifo;
+-00893                         retval = sizeof(uint16_t);
+-00894                 }
+-00895                 break;
+-00896         }
+-00897 
+-00898         return retval;
+-00899 }
+-00900 
+-00904 static int cfi_reset_sg_val(cfi_ep_t * cfiep)
+-00905 {
+-00906         dwc_memset(cfiep->bm_sg, 0, sizeof(ddma_sg_buffer_setup_t));
+-00907         return 0;
+-00908 }
+-00909 
+-00913 static int cfi_reset_align_val(cfi_ep_t * cfiep)
+-00914 {
+-00915         dwc_memset(cfiep->bm_sg, 0, sizeof(ddma_sg_buffer_setup_t));
+-00916         return 0;
+-00917 }
+-00918 
+-00924 static int cfi_reset_concat_val(cfi_ep_t * cfiep)
+-00925 {
+-00926         /* First we need to free the wTxBytes field */
+-00927         if (cfiep->bm_concat->wTxBytes) {
+-00928                 dwc_free(cfiep->bm_concat->wTxBytes);
+-00929                 cfiep->bm_concat->wTxBytes = NULL;
+-00930         }
+-00931 
+-00932         dwc_memset(cfiep->bm_concat, 0, sizeof(ddma_concat_buffer_setup_t));
+-00933         return 0;
+-00934 }
+-00935 
+-00939 static int cfi_ep_reset_all_setup_vals(cfi_ep_t * cfiep)
+-00940 {
+-00941         cfi_reset_sg_val(cfiep);
+-00942         cfi_reset_align_val(cfiep);
+-00943         cfi_reset_concat_val(cfiep);
+-00944         return 0;
+-00945 }
+-00946 
+-00947 static int cfi_handle_reset_fifo_val(struct dwc_otg_pcd *pcd, uint8_t ep_addr,
+-00948                                      uint8_t rx_rst, uint8_t tx_rst)
+-00949 {
+-00950         int retval = -DWC_E_INVALID;
+-00951         uint16_t tx_siz[15];
+-00952         uint16_t rx_siz = 0;
+-00953         dwc_otg_pcd_ep_t *ep = NULL;
+-00954         dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
+-00955         dwc_otg_core_params_t *params = GET_CORE_IF(pcd)->core_params;
+-00956 
+-00957         if (rx_rst) {
+-00958                 rx_siz = params->dev_rx_fifo_size;
+-00959                 params->dev_rx_fifo_size = GET_CORE_IF(pcd)->init_rxfsiz;
+-00960         }
+-00961 
+-00962         if (tx_rst) {
+-00963                 if (ep_addr == 0) {
+-00964                         int i;
+-00965 
+-00966                         for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {
+-00967                                 tx_siz[i] =
+-00968                                     core_if->core_params->dev_tx_fifo_size[i];
+-00969                                 core_if->core_params->dev_tx_fifo_size[i] =
+-00970                                     core_if->init_txfsiz[i];
+-00971                         }
+-00972                 } else {
+-00973 
+-00974                         ep = get_ep_by_addr(pcd, ep_addr);
+-00975 
+-00976                         if (NULL == ep) {
+-00977                                 CFI_INFO
+-00978                                     ("%s: Unable to get the endpoint addr=0x%02x\n",
+-00979                                      __func__, ep_addr);
+-00980                                 return -DWC_E_INVALID;
+-00981                         }
+-00982 
+-00983                         tx_siz[0] =
+-00984                             params->dev_tx_fifo_size[ep->dwc_ep.tx_fifo_num -
+-00985                                                      1];
+-00986                         params->dev_tx_fifo_size[ep->dwc_ep.tx_fifo_num - 1] =
+-00987                             GET_CORE_IF(pcd)->init_txfsiz[ep->dwc_ep.
+-00988                                                           tx_fifo_num - 1];
+-00989                 }
+-00990         }
+-00991 
+-00992         if (resize_fifos(GET_CORE_IF(pcd))) {
+-00993                 retval = 0;
+-00994         } else {
+-00995                 CFI_INFO
+-00996                     ("%s: Error resetting the feature Reset All(FIFO size)\n",
+-00997                      __func__);
+-00998                 if (rx_rst) {
+-00999                         params->dev_rx_fifo_size = rx_siz;
+-01000                 }
+-01001 
+-01002                 if (tx_rst) {
+-01003                         if (ep_addr == 0) {
+-01004                                 int i;
+-01005                                 for (i = 0; i < core_if->hwcfg4.b.num_in_eps;
+-01006                                      i++) {
+-01007                                         core_if->core_params->
+-01008                                             dev_tx_fifo_size[i] = tx_siz[i];
+-01009                                 }
+-01010                         } else {
+-01011                                 params->dev_tx_fifo_size[ep->dwc_ep.
+-01012                                                          tx_fifo_num - 1] =
+-01013                                     tx_siz[0];
+-01014                         }
+-01015                 }
+-01016                 retval = -DWC_E_INVALID;
+-01017         }
+-01018         return retval;
+-01019 }
+-01020 
+-01021 static int cfi_handle_reset_all(struct dwc_otg_pcd *pcd, uint8_t addr)
+-01022 {
+-01023         int retval = 0;
+-01024         cfi_ep_t *cfiep;
+-01025         cfiobject_t *cfi = pcd->cfi;
+-01026         dwc_list_link_t *tmp;
+-01027 
+-01028         retval = cfi_handle_reset_fifo_val(pcd, addr, 1, 1);
+-01029         if (retval < 0) {
+-01030                 return retval;
+-01031         }
+-01032 
+-01033         /* If the EP address is known then reset the features for only that EP */
+-01034         if (addr) {
+-01035                 cfiep = get_cfi_ep_by_addr(pcd->cfi, addr);
+-01036                 if (NULL == cfiep) {
+-01037                         CFI_INFO("%s: Error getting the EP address 0x%02x\n",
+-01038                                  __func__, addr);
+-01039                         return -DWC_E_INVALID;
+-01040                 }
+-01041                 retval = cfi_ep_reset_all_setup_vals(cfiep);
+-01042                 cfiep->ep->dwc_ep.buff_mode = BM_STANDARD;
+-01043         }
+-01044         /* Otherwise (wValue == 0), reset all features of all EP's */
+-01045         else {
+-01046                 /* Traverse all the active EP's and reset the feature(s) value(s) */
+-01047                 //list_for_each_entry(cfiep, &cfi->active_eps, lh) {
+-01048                 DWC_LIST_FOREACH(tmp, &cfi->active_eps) {
+-01049                         cfiep = DWC_LIST_ENTRY(tmp, struct cfi_ep, lh);
+-01050                         retval = cfi_ep_reset_all_setup_vals(cfiep);
+-01051                         cfiep->ep->dwc_ep.buff_mode = BM_STANDARD;
+-01052                         if (retval < 0) {
+-01053                                 CFI_INFO
+-01054                                     ("%s: Error resetting the feature Reset All\n",
+-01055                                      __func__);
+-01056                                 return retval;
+-01057                         }
+-01058                 }
+-01059         }
+-01060         return retval;
+-01061 }
+-01062 
+-01063 static int cfi_handle_reset_dma_buff_setup(struct dwc_otg_pcd *pcd,
+-01064                                            uint8_t addr)
+-01065 {
+-01066         int retval = 0;
+-01067         cfi_ep_t *cfiep;
+-01068         cfiobject_t *cfi = pcd->cfi;
+-01069         dwc_list_link_t *tmp;
+-01070 
+-01071         /* If the EP address is known then reset the features for only that EP */
+-01072         if (addr) {
+-01073                 cfiep = get_cfi_ep_by_addr(pcd->cfi, addr);
+-01074                 if (NULL == cfiep) {
+-01075                         CFI_INFO("%s: Error getting the EP address 0x%02x\n",
+-01076                                  __func__, addr);
+-01077                         return -DWC_E_INVALID;
+-01078                 }
+-01079                 retval = cfi_reset_sg_val(cfiep);
+-01080         }
+-01081         /* Otherwise (wValue == 0), reset all features of all EP's */
+-01082         else {
+-01083                 /* Traverse all the active EP's and reset the feature(s) value(s) */
+-01084                 //list_for_each_entry(cfiep, &cfi->active_eps, lh) {
+-01085                 DWC_LIST_FOREACH(tmp, &cfi->active_eps) {
+-01086                         cfiep = DWC_LIST_ENTRY(tmp, struct cfi_ep, lh);
+-01087                         retval = cfi_reset_sg_val(cfiep);
+-01088                         if (retval < 0) {
+-01089                                 CFI_INFO
+-01090                                     ("%s: Error resetting the feature Buffer Setup\n",
+-01091                                      __func__);
+-01092                                 return retval;
+-01093                         }
+-01094                 }
+-01095         }
+-01096         return retval;
+-01097 }
+-01098 
+-01099 static int cfi_handle_reset_concat_val(struct dwc_otg_pcd *pcd, uint8_t addr)
+-01100 {
+-01101         int retval = 0;
+-01102         cfi_ep_t *cfiep;
+-01103         cfiobject_t *cfi = pcd->cfi;
+-01104         dwc_list_link_t *tmp;
+-01105 
+-01106         /* If the EP address is known then reset the features for only that EP */
+-01107         if (addr) {
+-01108                 cfiep = get_cfi_ep_by_addr(pcd->cfi, addr);
+-01109                 if (NULL == cfiep) {
+-01110                         CFI_INFO("%s: Error getting the EP address 0x%02x\n",
+-01111                                  __func__, addr);
+-01112                         return -DWC_E_INVALID;
+-01113                 }
+-01114                 retval = cfi_reset_concat_val(cfiep);
+-01115         }
+-01116         /* Otherwise (wValue == 0), reset all features of all EP's */
+-01117         else {
+-01118                 /* Traverse all the active EP's and reset the feature(s) value(s) */
+-01119                 //list_for_each_entry(cfiep, &cfi->active_eps, lh) {
+-01120                 DWC_LIST_FOREACH(tmp, &cfi->active_eps) {
+-01121                         cfiep = DWC_LIST_ENTRY(tmp, struct cfi_ep, lh);
+-01122                         retval = cfi_reset_concat_val(cfiep);
+-01123                         if (retval < 0) {
+-01124                                 CFI_INFO
+-01125                                     ("%s: Error resetting the feature Concatenation Value\n",
+-01126                                      __func__);
+-01127                                 return retval;
+-01128                         }
+-01129                 }
+-01130         }
+-01131         return retval;
+-01132 }
+-01133 
+-01134 static int cfi_handle_reset_align_val(struct dwc_otg_pcd *pcd, uint8_t addr)
+-01135 {
+-01136         int retval = 0;
+-01137         cfi_ep_t *cfiep;
+-01138         cfiobject_t *cfi = pcd->cfi;
+-01139         dwc_list_link_t *tmp;
+-01140 
+-01141         /* If the EP address is known then reset the features for only that EP */
+-01142         if (addr) {
+-01143                 cfiep = get_cfi_ep_by_addr(pcd->cfi, addr);
+-01144                 if (NULL == cfiep) {
+-01145                         CFI_INFO("%s: Error getting the EP address 0x%02x\n",
+-01146                                  __func__, addr);
+-01147                         return -DWC_E_INVALID;
+-01148                 }
+-01149                 retval = cfi_reset_align_val(cfiep);
+-01150         }
+-01151         /* Otherwise (wValue == 0), reset all features of all EP's */
+-01152         else {
+-01153                 /* Traverse all the active EP's and reset the feature(s) value(s) */
+-01154                 //list_for_each_entry(cfiep, &cfi->active_eps, lh) {
+-01155                 DWC_LIST_FOREACH(tmp, &cfi->active_eps) {
+-01156                         cfiep = DWC_LIST_ENTRY(tmp, struct cfi_ep, lh);
+-01157                         retval = cfi_reset_align_val(cfiep);
+-01158                         if (retval < 0) {
+-01159                                 CFI_INFO
+-01160                                     ("%s: Error resetting the feature Aliignment Value\n",
+-01161                                      __func__);
+-01162                                 return retval;
+-01163                         }
+-01164                 }
+-01165         }
+-01166         return retval;
+-01167 
+-01168 }
+-01169 
+-01170 static int cfi_preproc_reset(struct dwc_otg_pcd *pcd,
+-01171                              struct cfi_usb_ctrlrequest *req)
+-01172 {
+-01173         int retval = 0;
+-01174 
+-01175         switch (req->wIndex) {
+-01176         case 0:
+-01177                 /* Reset all features */
+-01178                 retval = cfi_handle_reset_all(pcd, req->wValue & 0xff);
+-01179                 break;
+-01180 
+-01181         case FT_ID_DMA_BUFFER_SETUP:
+-01182                 /* Reset the SG buffer setup */
+-01183                 retval =
+-01184                     cfi_handle_reset_dma_buff_setup(pcd, req->wValue & 0xff);
+-01185                 break;
+-01186 
+-01187         case FT_ID_DMA_CONCAT_SETUP:
+-01188                 /* Reset the Concatenation buffer setup */
+-01189                 retval = cfi_handle_reset_concat_val(pcd, req->wValue & 0xff);
+-01190                 break;
+-01191 
+-01192         case FT_ID_DMA_BUFF_ALIGN:
+-01193                 /* Reset the Alignment buffer setup */
+-01194                 retval = cfi_handle_reset_align_val(pcd, req->wValue & 0xff);
+-01195                 break;
+-01196 
+-01197         case FT_ID_TX_FIFO_DEPTH:
+-01198                 retval =
+-01199                     cfi_handle_reset_fifo_val(pcd, req->wValue & 0xff, 0, 1);
+-01200                 pcd->cfi->need_gadget_att = 0;
+-01201                 break;
+-01202 
+-01203         case FT_ID_RX_FIFO_DEPTH:
+-01204                 retval = cfi_handle_reset_fifo_val(pcd, 0, 1, 0);
+-01205                 pcd->cfi->need_gadget_att = 0;
+-01206                 break;
+-01207         default:
+-01208                 break;
+-01209         }
+-01210         return retval;
+-01211 }
+-01212 
+-01216 static int cfi_ep_set_sg_val(uint8_t * buf, struct dwc_otg_pcd *pcd)
+-01217 {
+-01218         uint8_t inaddr, outaddr;
+-01219         cfi_ep_t *epin, *epout;
+-01220         ddma_sg_buffer_setup_t *psgval;
+-01221         uint32_t desccount, size;
+-01222 
+-01223         CFI_INFO("%s\n", __func__);
+-01224 
+-01225         psgval = (ddma_sg_buffer_setup_t *) buf;
+-01226         desccount = (uint32_t) psgval->bCount;
+-01227         size = (uint32_t) psgval->wSize;
+-01228 
+-01229         /* Check the DMA descriptor count */
+-01230         if ((desccount > MAX_DMA_DESCS_PER_EP) || (desccount == 0)) {
+-01231                 CFI_INFO
+-01232                     ("%s: The count of DMA Descriptors should be between 1 and %d\n",
+-01233                      __func__, MAX_DMA_DESCS_PER_EP);
+-01234                 return -DWC_E_INVALID;
+-01235         }
+-01236 
+-01237         /* Check the DMA descriptor count */
+-01238 
+-01239         if (size == 0) {
+-01240 
+-01241                 CFI_INFO("%s: The transfer size should be at least 1 byte\n",
+-01242                          __func__);
+-01243 
+-01244                 return -DWC_E_INVALID;
+-01245 
+-01246         }
+-01247 
+-01248         inaddr = psgval->bInEndpointAddress;
+-01249         outaddr = psgval->bOutEndpointAddress;
+-01250 
+-01251         epin = get_cfi_ep_by_addr(pcd->cfi, inaddr);
+-01252         epout = get_cfi_ep_by_addr(pcd->cfi, outaddr);
+-01253 
+-01254         if (NULL == epin || NULL == epout) {
+-01255                 CFI_INFO
+-01256                     ("%s: Unable to get the endpoints inaddr=0x%02x outaddr=0x%02x\n",
+-01257                      __func__, inaddr, outaddr);
+-01258                 return -DWC_E_INVALID;
+-01259         }
+-01260 
+-01261         epin->ep->dwc_ep.buff_mode = BM_SG;
+-01262         dwc_memcpy(epin->bm_sg, psgval, sizeof(ddma_sg_buffer_setup_t));
+-01263 
+-01264         epout->ep->dwc_ep.buff_mode = BM_SG;
+-01265         dwc_memcpy(epout->bm_sg, psgval, sizeof(ddma_sg_buffer_setup_t));
+-01266 
+-01267         return 0;
+-01268 }
+-01269 
+-01273 static int cfi_ep_set_alignment_val(uint8_t * buf, struct dwc_otg_pcd *pcd)
+-01274 {
+-01275         cfi_ep_t *ep;
+-01276         uint8_t addr;
+-01277         ddma_align_buffer_setup_t *palignval;
+-01278 
+-01279         palignval = (ddma_align_buffer_setup_t *) buf;
+-01280         addr = palignval->bEndpointAddress;
+-01281 
+-01282         ep = get_cfi_ep_by_addr(pcd->cfi, addr);
+-01283 
+-01284         if (NULL == ep) {
+-01285                 CFI_INFO("%s: Unable to get the endpoint addr=0x%02x\n",
+-01286                          __func__, addr);
+-01287                 return -DWC_E_INVALID;
+-01288         }
+-01289 
+-01290         ep->ep->dwc_ep.buff_mode = BM_ALIGN;
+-01291         dwc_memcpy(ep->bm_align, palignval, sizeof(ddma_align_buffer_setup_t));
+-01292 
+-01293         return 0;
+-01294 }
+-01295 
+-01299 static int cfi_ep_set_concat_val(uint8_t * buf, struct dwc_otg_pcd *pcd)
+-01300 {
+-01301         uint8_t addr;
+-01302         cfi_ep_t *ep;
+-01303         struct _ddma_concat_buffer_setup_hdr *pConcatValHdr;
+-01304         uint16_t *pVals;
+-01305         uint32_t desccount;
+-01306         int i;
+-01307         uint16_t mps;
+-01308 
+-01309         pConcatValHdr = (struct _ddma_concat_buffer_setup_hdr *)buf;
+-01310         desccount = (uint32_t) pConcatValHdr->bDescCount;
+-01311         pVals = (uint16_t *) (buf + BS_CONCAT_VAL_HDR_LEN);
+-01312 
+-01313         /* Check the DMA descriptor count */
+-01314         if (desccount > MAX_DMA_DESCS_PER_EP) {
+-01315                 CFI_INFO("%s: Maximum DMA Descriptor count should be %d\n",
+-01316                          __func__, MAX_DMA_DESCS_PER_EP);
+-01317                 return -DWC_E_INVALID;
+-01318         }
+-01319 
+-01320         addr = pConcatValHdr->bEndpointAddress;
+-01321         ep = get_cfi_ep_by_addr(pcd->cfi, addr);
+-01322         if (NULL == ep) {
+-01323                 CFI_INFO("%s: Unable to get the endpoint addr=0x%02x\n",
+-01324                          __func__, addr);
+-01325                 return -DWC_E_INVALID;
+-01326         }
+-01327 
+-01328         mps = UGETW(ep->ep->desc->wMaxPacketSize);
+-01329 
+-01330 #if 0
+-01331         for (i = 0; i < desccount; i++) {
+-01332                 CFI_INFO("%s: wTxSize[%d]=0x%04x\n", __func__, i, pVals[i]);
+-01333         }
+-01334         CFI_INFO("%s: epname=%s; mps=%d\n", __func__, ep->ep->ep.name, mps);
+-01335 #endif
+-01336 
+-01337         /* Check the wTxSizes to be less than or equal to the mps */
+-01338         for (i = 0; i < desccount; i++) {
+-01339                 if (pVals[i] > mps) {
+-01340                         CFI_INFO
+-01341                             ("%s: ERROR - the wTxSize[%d] should be <= MPS (wTxSize=%d)\n",
+-01342                              __func__, i, pVals[i]);
+-01343                         return -DWC_E_INVALID;
+-01344                 }
+-01345         }
+-01346 
+-01347         ep->ep->dwc_ep.buff_mode = BM_CONCAT;
+-01348         dwc_memcpy(ep->bm_concat, pConcatValHdr, BS_CONCAT_VAL_HDR_LEN);
+-01349 
+-01350         /* Free the previously allocated storage for the wTxBytes */
+-01351         if (ep->bm_concat->wTxBytes) {
+-01352                 dwc_free(ep->bm_concat->wTxBytes);
+-01353         }
+-01354 
+-01355         /* Allocate a new storage for the wTxBytes field */
+-01356         ep->bm_concat->wTxBytes =
+-01357             dwc_alloc(sizeof(uint16_t) * pConcatValHdr->bDescCount);
+-01358         if (NULL == ep->bm_concat->wTxBytes) {
+-01359                 CFI_INFO("%s: Unable to allocate memory\n", __func__);
+-01360                 return -DWC_E_NO_MEMORY;
+-01361         }
+-01362 
+-01363         /* Copy the new values into the wTxBytes filed */
+-01364         dwc_memcpy(ep->bm_concat->wTxBytes, buf + BS_CONCAT_VAL_HDR_LEN,
+-01365                    sizeof(uint16_t) * pConcatValHdr->bDescCount);
+-01366 
+-01367         return 0;
+-01368 }
+-01369 
+-01378 static uint16_t get_dfifo_size(dwc_otg_core_if_t * core_if)
+-01379 {
+-01380         dwc_otg_core_params_t *params = core_if->core_params;
+-01381         uint16_t dfifo_total = 0;
+-01382         int i;
+-01383 
+-01384         /* The shared RxFIFO size */
+-01385         dfifo_total =
+-01386             params->dev_rx_fifo_size + params->dev_nperio_tx_fifo_size;
+-01387 
+-01388         /* Add up each TxFIFO size to the total */
+-01389         for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {
+-01390                 dfifo_total += params->dev_tx_fifo_size[i];
+-01391         }
+-01392 
+-01393         return dfifo_total;
+-01394 }
+-01395 
+-01404 static int32_t get_rxfifo_size(dwc_otg_core_if_t * core_if, uint16_t wValue)
+-01405 {
+-01406         switch (wValue >> 8) {
+-01407         case 0:
+-01408                 return (core_if->pwron_rxfsiz <
+-01409                         32768) ? core_if->pwron_rxfsiz : 32768;
+-01410                 break;
+-01411         case 1:
+-01412                 return core_if->core_params->dev_rx_fifo_size;
+-01413                 break;
+-01414         default:
+-01415                 return -DWC_E_INVALID;
+-01416                 break;
+-01417         }
+-01418 }
+-01419 
+-01428 static int32_t get_txfifo_size(struct dwc_otg_pcd *pcd, uint16_t wValue)
+-01429 {
+-01430         dwc_otg_pcd_ep_t *ep;
+-01431 
+-01432         ep = get_ep_by_addr(pcd, wValue & 0xff);
+-01433 
+-01434         if (NULL == ep) {
+-01435                 CFI_INFO("%s: Unable to get the endpoint addr=0x%02x\n",
+-01436                          __func__, wValue & 0xff);
+-01437                 return -DWC_E_INVALID;
+-01438         }
+-01439 
+-01440         if (!ep->dwc_ep.is_in) {
+-01441                 CFI_INFO
+-01442                     ("%s: No Tx FIFO assingned to the Out endpoint addr=0x%02x\n",
+-01443                      __func__, wValue & 0xff);
+-01444                 return -DWC_E_INVALID;
+-01445         }
+-01446 
+-01447         switch (wValue >> 8) {
+-01448         case 0:
+-01449                 return (GET_CORE_IF(pcd)->
+-01450                         pwron_txfsiz[ep->dwc_ep.tx_fifo_num - 1] <
+-01451                         768) ? GET_CORE_IF(pcd)->pwron_txfsiz[ep->dwc_ep.
+-01452                                                               tx_fifo_num -
+-01453                                                               1] : 32768;
+-01454                 break;
+-01455         case 1:
+-01456                 return GET_CORE_IF(pcd)->core_params->dev_tx_fifo_size[ep->
+-01457                                                                        dwc_ep.
+-01458                                                                        num - 1];
+-01459                 break;
+-01460         default:
+-01461                 return -DWC_E_INVALID;
+-01462                 break;
+-01463         }
+-01464 }
+-01465 
+-01475 static uint8_t check_fifo_sizes(dwc_otg_core_if_t * core_if)
+-01476 {
+-01477         uint16_t dfifo_actual = 0;
+-01478         dwc_otg_core_params_t *params = core_if->core_params;
+-01479         uint16_t start_addr = 0;
+-01480         int i;
+-01481 
+-01482         dfifo_actual =
+-01483             params->dev_rx_fifo_size + params->dev_nperio_tx_fifo_size;
+-01484 
+-01485         for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {
+-01486                 dfifo_actual += params->dev_tx_fifo_size[i];
+-01487         }
+-01488 
+-01489         if (dfifo_actual > core_if->total_fifo_size) {
+-01490                 return 0;
+-01491         }
+-01492 
+-01493         if (params->dev_rx_fifo_size > 32768 || params->dev_rx_fifo_size < 16)
+-01494                 return 0;
+-01495 
+-01496         if (params->dev_nperio_tx_fifo_size > 32768
+-01497             || params->dev_nperio_tx_fifo_size < 16)
+-01498                 return 0;
+-01499 
+-01500         for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {
+-01501 
+-01502                 if (params->dev_tx_fifo_size[i] > 768
+-01503                     || params->dev_tx_fifo_size[i] < 4)
+-01504                         return 0;
+-01505         }
+-01506 
+-01507         if (params->dev_rx_fifo_size > core_if->pwron_rxfsiz)
+-01508                 return 0;
+-01509         start_addr = params->dev_rx_fifo_size;
+-01510 
+-01511         if (params->dev_nperio_tx_fifo_size > core_if->pwron_gnptxfsiz)
+-01512                 return 0;
+-01513         start_addr += params->dev_nperio_tx_fifo_size;
+-01514 
+-01515         for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {
+-01516 
+-01517                 if (params->dev_tx_fifo_size[i] > core_if->pwron_txfsiz[i])
+-01518                         return 0;
+-01519                 start_addr += params->dev_tx_fifo_size[i];
+-01520         }
+-01521 
+-01522         return 1;
+-01523 }
+-01524 
+-01533 static uint8_t resize_fifos(dwc_otg_core_if_t * core_if)
+-01534 {
+-01535         int i = 0;
+-01536         dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
+-01537         dwc_otg_core_params_t *params = core_if->core_params;
+-01538         uint32_t rx_fifo_size;
+-01539         fifosize_data_t nptxfifosize;
+-01540         fifosize_data_t txfifosize[15];
+-01541 
+-01542         uint32_t rx_fsz_bak;
+-01543         uint32_t nptxfsz_bak;
+-01544         uint32_t txfsz_bak[15];
+-01545 
+-01546         uint16_t start_address;
+-01547         uint8_t retval = 1;
+-01548 
+-01549         if (!check_fifo_sizes(core_if)) {
+-01550                 return 0;
+-01551         }
+-01552 
+-01553         /* Configure data FIFO sizes */
+-01554         if (core_if->hwcfg2.b.dynamic_fifo && params->enable_dynamic_fifo) {
+-01555                 rx_fsz_bak = dwc_read_reg32(&global_regs->grxfsiz);
+-01556                 rx_fifo_size = params->dev_rx_fifo_size;
+-01557                 dwc_write_reg32(&global_regs->grxfsiz, rx_fifo_size);
+-01558 
+-01559                 /*
+-01560                  * Tx FIFOs These FIFOs are numbered from 1 to 15.
+-01561                  * Indexes of the FIFO size module parameters in the
+-01562                  * dev_tx_fifo_size array and the FIFO size registers in
+-01563                  * the dptxfsiz_dieptxf array run from 0 to 14.
+-01564                  */
+-01565 
+-01566                 /* Non-periodic Tx FIFO */
+-01567                 nptxfsz_bak = dwc_read_reg32(&global_regs->gnptxfsiz);
+-01568                 nptxfifosize.b.depth = params->dev_nperio_tx_fifo_size;
+-01569                 start_address = params->dev_rx_fifo_size;
+-01570                 nptxfifosize.b.startaddr = start_address;
+-01571 
+-01572                 dwc_write_reg32(&global_regs->gnptxfsiz, nptxfifosize.d32);
+-01573 
+-01574                 start_address += nptxfifosize.b.depth;
+-01575 
+-01576                 for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {
+-01577                         txfsz_bak[i] =
+-01578                             dwc_read_reg32(&global_regs->dptxfsiz_dieptxf[i]);
+-01579 
+-01580                         txfifosize[i].b.depth = params->dev_tx_fifo_size[i];
+-01581                         txfifosize[i].b.startaddr = start_address;
+-01582                         dwc_write_reg32(&global_regs->dptxfsiz_dieptxf[i],
+-01583                                         txfifosize[i].d32);
+-01584 
+-01585                         start_address += txfifosize[i].b.depth;
+-01586                 }
+-01587 
+-01589                 if (rx_fifo_size != dwc_read_reg32(&global_regs->grxfsiz)) {
+-01590                         retval = 0;
+-01591                 }
+-01592 
+-01593                 if (nptxfifosize.d32 != dwc_read_reg32(&global_regs->gnptxfsiz)) {
+-01594                         retval = 0;
+-01595                 }
+-01596 
+-01597                 for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {
+-01598                         if (txfifosize[i].d32 !=
+-01599                             dwc_read_reg32(&global_regs->dptxfsiz_dieptxf[i])) {
+-01600                                 retval = 0;
+-01601                         }
+-01602                 }
+-01603 
+-01605                 if (retval == 0) {
+-01606                         dwc_write_reg32(&global_regs->grxfsiz, rx_fsz_bak);
+-01607 
+-01608                         /* Non-periodic Tx FIFO */
+-01609                         dwc_write_reg32(&global_regs->gnptxfsiz, nptxfsz_bak);
+-01610 
+-01611                         for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {
+-01612                                 dwc_write_reg32(&global_regs->
+-01613                                                 dptxfsiz_dieptxf[i],
+-01614                                                 txfsz_bak[i]);
+-01615                         }
+-01616                 }
+-01617         } else {
+-01618                 return 0;
+-01619         }
+-01620 
+-01621         /* Flush the FIFOs */
+-01622         dwc_otg_flush_tx_fifo(core_if, 0x10);   /* all Tx FIFOs */
+-01623         dwc_otg_flush_rx_fifo(core_if);
+-01624 
+-01625         return retval;
+-01626 }
+-01627 
+-01631 static int cfi_ep_set_tx_fifo_val(uint8_t * buf, dwc_otg_pcd_t * pcd)
+-01632 {
+-01633         int retval;
+-01634         uint32_t fsiz;
+-01635         uint16_t size;
+-01636         uint16_t ep_addr;
+-01637         dwc_otg_pcd_ep_t *ep;
+-01638         dwc_otg_core_params_t *params = GET_CORE_IF(pcd)->core_params;
+-01639         tx_fifo_size_setup_t *ptxfifoval;
+-01640 
+-01641         ptxfifoval = (tx_fifo_size_setup_t *) buf;
+-01642         ep_addr = ptxfifoval->bEndpointAddress;
+-01643         size = ptxfifoval->wDepth;
+-01644 
+-01645         ep = get_ep_by_addr(pcd, ep_addr);
+-01646 
+-01647         CFI_INFO
+-01648             ("%s: Set Tx FIFO size: endpoint addr=0x%02x, depth=%d, FIFO Num=%d\n",
+-01649              __func__, ep_addr, size, ep->dwc_ep.tx_fifo_num);
+-01650 
+-01651         if (NULL == ep) {
+-01652                 CFI_INFO("%s: Unable to get the endpoint addr=0x%02x\n",
+-01653                          __func__, ep_addr);
+-01654                 return -DWC_E_INVALID;
+-01655         }
+-01656 
+-01657         fsiz = params->dev_tx_fifo_size[ep->dwc_ep.tx_fifo_num - 1];
+-01658         params->dev_tx_fifo_size[ep->dwc_ep.tx_fifo_num - 1] = size;
+-01659 
+-01660         if (resize_fifos(GET_CORE_IF(pcd))) {
+-01661                 retval = 0;
+-01662         } else {
+-01663                 CFI_INFO
+-01664                     ("%s: Error setting the feature Tx FIFO Size for EP%d\n",
+-01665                      __func__, ep_addr);
+-01666                 params->dev_tx_fifo_size[ep->dwc_ep.tx_fifo_num - 1] = fsiz;
+-01667                 retval = -DWC_E_INVALID;
+-01668         }
+-01669 
+-01670         return retval;
+-01671 }
+-01672 
+-01676 static int cfi_set_rx_fifo_val(uint8_t * buf, dwc_otg_pcd_t * pcd)
+-01677 {
+-01678         int retval;
+-01679         uint32_t fsiz;
+-01680         uint16_t size;
+-01681         dwc_otg_core_params_t *params = GET_CORE_IF(pcd)->core_params;
+-01682         rx_fifo_size_setup_t *prxfifoval;
+-01683 
+-01684         prxfifoval = (rx_fifo_size_setup_t *) buf;
+-01685         size = prxfifoval->wDepth;
+-01686 
+-01687         fsiz = params->dev_rx_fifo_size;
+-01688         params->dev_rx_fifo_size = size;
+-01689 
+-01690         if (resize_fifos(GET_CORE_IF(pcd))) {
+-01691                 retval = 0;
+-01692         } else {
+-01693                 CFI_INFO("%s: Error setting the feature Rx FIFO Size\n",
+-01694                          __func__);
+-01695                 params->dev_rx_fifo_size = fsiz;
+-01696                 retval = -DWC_E_INVALID;
+-01697         }
+-01698 
+-01699         return retval;
+-01700 }
+-01701 
+-01705 static int cfi_ep_get_sg_val(uint8_t * buf, struct dwc_otg_pcd *pcd,
+-01706                              struct cfi_usb_ctrlrequest *req)
+-01707 {
+-01708         int retval = -DWC_E_INVALID;
+-01709         uint8_t addr;
+-01710         cfi_ep_t *ep;
+-01711 
+-01712         /* The Low Byte of the wValue contains a non-zero address of the endpoint */
+-01713         addr = req->wValue & 0xFF;
+-01714         if (addr == 0)          /* The address should be non-zero */
+-01715                 return retval;
+-01716 
+-01717         ep = get_cfi_ep_by_addr(pcd->cfi, addr);
+-01718         if (NULL == ep) {
+-01719                 CFI_INFO("%s: Unable to get the endpoint address(0x%02x)\n",
+-01720                          __func__, addr);
+-01721                 return retval;
+-01722         }
+-01723 
+-01724         dwc_memcpy(buf, ep->bm_sg, BS_SG_VAL_DESC_LEN);
+-01725         retval = BS_SG_VAL_DESC_LEN;
+-01726         return retval;
+-01727 }
+-01728 
+-01733 static int cfi_ep_get_concat_val(uint8_t * buf, struct dwc_otg_pcd *pcd,
+-01734                                  struct cfi_usb_ctrlrequest *req)
+-01735 {
+-01736         int retval = -DWC_E_INVALID;
+-01737         uint8_t addr;
+-01738         cfi_ep_t *ep;
+-01739         uint8_t desc_count;
+-01740 
+-01741         /* The Low Byte of the wValue contains a non-zero address of the endpoint */
+-01742         addr = req->wValue & 0xFF;
+-01743         if (addr == 0)          /* The address should be non-zero */
+-01744                 return retval;
+-01745 
+-01746         ep = get_cfi_ep_by_addr(pcd->cfi, addr);
+-01747         if (NULL == ep) {
+-01748                 CFI_INFO("%s: Unable to get the endpoint address(0x%02x)\n",
+-01749                          __func__, addr);
+-01750                 return retval;
+-01751         }
+-01752 
+-01753         /* Copy the header to the buffer */
+-01754         dwc_memcpy(buf, ep->bm_concat, BS_CONCAT_VAL_HDR_LEN);
+-01755         /* Advance the buffer pointer by the header size */
+-01756         buf += BS_CONCAT_VAL_HDR_LEN;
+-01757 
+-01758         desc_count = ep->bm_concat->hdr.bDescCount;
+-01759         /* Copy alll the wTxBytes to the buffer */
+-01760         dwc_memcpy(buf, ep->bm_concat->wTxBytes, sizeof(uid16_t) * desc_count);
+-01761 
+-01762         retval = BS_CONCAT_VAL_HDR_LEN + sizeof(uid16_t) * desc_count;
+-01763         return retval;
+-01764 }
+-01765 
+-01772 static int cfi_ep_get_align_val(uint8_t * buf, struct dwc_otg_pcd *pcd,
+-01773                                 struct cfi_usb_ctrlrequest *req)
+-01774 {
+-01775         int retval = -DWC_E_INVALID;
+-01776         uint8_t addr;
+-01777         cfi_ep_t *ep;
+-01778 
+-01779         /* The Low Byte of the wValue contains a non-zero address of the endpoint */
+-01780         addr = req->wValue & 0xFF;
+-01781         if (addr == 0)          /* The address should be non-zero */
+-01782                 return retval;
+-01783 
+-01784         ep = get_cfi_ep_by_addr(pcd->cfi, addr);
+-01785         if (NULL == ep) {
+-01786                 CFI_INFO("%s: Unable to get the endpoint address(0x%02x)\n",
+-01787                          __func__, addr);
+-01788                 return retval;
+-01789         }
+-01790 
+-01791         dwc_memcpy(buf, ep->bm_align, BS_ALIGN_VAL_HDR_LEN);
+-01792         retval = BS_ALIGN_VAL_HDR_LEN;
+-01793 
+-01794         return retval;
+-01795 }
+-01796 
+-01804 static int cfi_set_feature_value(struct dwc_otg_pcd *pcd)
+-01805 {
+-01806         int retval = -DWC_E_NOT_SUPPORTED;
+-01807         uint16_t wIndex, wValue;
+-01808         uint8_t bRequest;
+-01809         struct dwc_otg_core_if *coreif;
+-01810         cfiobject_t *cfi = pcd->cfi;
+-01811         struct cfi_usb_ctrlrequest *ctrl_req;
+-01812         uint8_t *buf;
+-01813         ctrl_req = &cfi->ctrl_req;
+-01814 
+-01815         buf = pcd->cfi->ctrl_req.data;
+-01816 
+-01817         coreif = GET_CORE_IF(pcd);
+-01818         bRequest = ctrl_req->bRequest;
+-01819         wIndex = DWC_CONSTANT_CPU_TO_LE16(ctrl_req->wIndex);
+-01820         wValue = DWC_CONSTANT_CPU_TO_LE16(ctrl_req->wValue);
+-01821 
+-01822         /* See which feature is to be modified */
+-01823         switch (wIndex) {
+-01824         case FT_ID_DMA_BUFFER_SETUP:
+-01825                 /* Modify the feature */
+-01826                 if ((retval = cfi_ep_set_sg_val(buf, pcd)) < 0)
+-01827                         return retval;
+-01828 
+-01829                 /* And send this request to the gadget */
+-01830                 cfi->need_gadget_att = 1;
+-01831                 break;
+-01832 
+-01833         case FT_ID_DMA_BUFF_ALIGN:
+-01834                 if ((retval = cfi_ep_set_alignment_val(buf, pcd)) < 0)
+-01835                         return retval;
+-01836                 cfi->need_gadget_att = 1;
+-01837                 break;
+-01838 
+-01839         case FT_ID_DMA_CONCAT_SETUP:
+-01840                 /* Modify the feature */
+-01841                 if ((retval = cfi_ep_set_concat_val(buf, pcd)) < 0)
+-01842                         return retval;
+-01843                 cfi->need_gadget_att = 1;
+-01844                 break;
+-01845 
+-01846         case FT_ID_DMA_CIRCULAR:
+-01847                 CFI_INFO("FT_ID_DMA_CIRCULAR\n");
+-01848                 break;
+-01849 
+-01850         case FT_ID_THRESHOLD_SETUP:
+-01851                 CFI_INFO("FT_ID_THRESHOLD_SETUP\n");
+-01852                 break;
+-01853 
+-01854         case FT_ID_DFIFO_DEPTH:
+-01855                 CFI_INFO("FT_ID_DFIFO_DEPTH\n");
+-01856                 break;
+-01857 
+-01858         case FT_ID_TX_FIFO_DEPTH:
+-01859                 CFI_INFO("FT_ID_TX_FIFO_DEPTH\n");
+-01860                 if ((retval = cfi_ep_set_tx_fifo_val(buf, pcd)) < 0)
+-01861                         return retval;
+-01862                 cfi->need_gadget_att = 0;
+-01863                 break;
+-01864 
+-01865         case FT_ID_RX_FIFO_DEPTH:
+-01866                 CFI_INFO("FT_ID_RX_FIFO_DEPTH\n");
+-01867                 if ((retval = cfi_set_rx_fifo_val(buf, pcd)) < 0)
+-01868                         return retval;
+-01869                 cfi->need_gadget_att = 0;
+-01870                 break;
+-01871         }
+-01872 
+-01873         return retval;
+-01874 }
+-01875 
+-01876 #endif                          //DWC_UTE_CFI
+-
Generated on Tue May 5 02:22:48 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++
Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
++

dwc_otg_cfi.c

Go to the documentation of this file.
00001 /* ==========================================================================
++00002  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
++00003  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
++00004  * otherwise expressly agreed to in writing between Synopsys and you.
++00005  * 
++00006  * The Software IS NOT an item of Licensed Software or Licensed Product under
++00007  * any End User Software License Agreement or Agreement for Licensed Product
++00008  * with Synopsys or any supplement thereto. You are permitted to use and
++00009  * redistribute this Software in source and binary forms, with or without
++00010  * modification, provided that redistributions of source code must retain this
++00011  * notice. You may not view, use, disclose, copy or distribute this file or
++00012  * any information contained herein except pursuant to this license grant from
++00013  * Synopsys. If you do not agree with this notice, including the disclaimer
++00014  * below, then you are not authorized to use the Software.
++00015  * 
++00016  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
++00017  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++00018  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++00019  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
++00020  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++00021  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
++00022  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
++00023  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
++00024  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
++00025  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
++00026  * DAMAGE.
++00027  * ========================================================================== */
++00028 
++00035 #ifdef DWC_UTE_CFI
++00036 
++00037 #include "dwc_otg_pcd.h"
++00038 #include "dwc_otg_cfi.h"
++00039 
++00041 #define DWC_CONSTANT_CPU_TO_LE16(x) (x)
++00042 
++00043 extern dwc_otg_pcd_ep_t *get_ep_by_addr(dwc_otg_pcd_t * pcd, u16 wIndex);
++00044 
++00045 static int cfi_core_features_buf(uint8_t * buf, uint16_t buflen);
++00046 static int cfi_get_feature_value(uint8_t * buf, uint16_t buflen,
++00047                                  struct dwc_otg_pcd *pcd,
++00048                                  struct cfi_usb_ctrlrequest *ctrl_req);
++00049 static int cfi_set_feature_value(struct dwc_otg_pcd *pcd);
++00050 static int cfi_ep_get_sg_val(uint8_t * buf, struct dwc_otg_pcd *pcd,
++00051                              struct cfi_usb_ctrlrequest *req);
++00052 static int cfi_ep_get_concat_val(uint8_t * buf, struct dwc_otg_pcd *pcd,
++00053                                  struct cfi_usb_ctrlrequest *req);
++00054 static int cfi_ep_get_align_val(uint8_t * buf, struct dwc_otg_pcd *pcd,
++00055                                 struct cfi_usb_ctrlrequest *req);
++00056 static int cfi_preproc_reset(struct dwc_otg_pcd *pcd,
++00057                              struct cfi_usb_ctrlrequest *req);
++00058 static void cfi_free_ep_bs_dyn_data(cfi_ep_t * cfiep);
++00059 
++00060 static uint16_t get_dfifo_size(dwc_otg_core_if_t * core_if);
++00061 static int32_t get_rxfifo_size(dwc_otg_core_if_t * core_if, uint16_t wValue);
++00062 static int32_t get_txfifo_size(struct dwc_otg_pcd *pcd, uint16_t wValue);
++00063 
++00064 static uint8_t resize_fifos(dwc_otg_core_if_t * core_if);
++00065 
++00067 static cfi_all_features_header_t all_props_desc_header = {
++00068         .wVersion = DWC_CONSTANT_CPU_TO_LE16(0x100),
++00069         .wCoreID = DWC_CONSTANT_CPU_TO_LE16(CFI_CORE_ID_OTG),
++00070         .wNumFeatures = DWC_CONSTANT_CPU_TO_LE16(9),
++00071 };
++00072 
++00074 static cfi_feature_desc_header_t prop_descs[] = {
++00075 
++00076         /* FT_ID_DMA_MODE */
++00077         {
++00078          .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_DMA_MODE),
++00079          .bmAttributes = CFI_FEATURE_ATTR_RW,
++00080          .wDataLength = DWC_CONSTANT_CPU_TO_LE16(1),
++00081          },
++00082 
++00083         /* FT_ID_DMA_BUFFER_SETUP */
++00084         {
++00085          .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_DMA_BUFFER_SETUP),
++00086          .bmAttributes = CFI_FEATURE_ATTR_RW,
++00087          .wDataLength = DWC_CONSTANT_CPU_TO_LE16(6),
++00088          },
++00089 
++00090         /* FT_ID_DMA_BUFF_ALIGN */
++00091         {
++00092          .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_DMA_BUFF_ALIGN),
++00093          .bmAttributes = CFI_FEATURE_ATTR_RW,
++00094          .wDataLength = DWC_CONSTANT_CPU_TO_LE16(2),
++00095          },
++00096 
++00097         /* FT_ID_DMA_CONCAT_SETUP */
++00098         {
++00099          .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_DMA_CONCAT_SETUP),
++00100          .bmAttributes = CFI_FEATURE_ATTR_RW,
++00101          //.wDataLength  = DWC_CONSTANT_CPU_TO_LE16(6),
++00102          },
++00103 
++00104         /* FT_ID_DMA_CIRCULAR */
++00105         {
++00106          .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_DMA_CIRCULAR),
++00107          .bmAttributes = CFI_FEATURE_ATTR_RW,
++00108          .wDataLength = DWC_CONSTANT_CPU_TO_LE16(6),
++00109          },
++00110 
++00111         /* FT_ID_THRESHOLD_SETUP */
++00112         {
++00113          .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_THRESHOLD_SETUP),
++00114          .bmAttributes = CFI_FEATURE_ATTR_RW,
++00115          .wDataLength = DWC_CONSTANT_CPU_TO_LE16(6),
++00116          },
++00117 
++00118         /* FT_ID_DFIFO_DEPTH */
++00119         {
++00120          .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_DFIFO_DEPTH),
++00121          .bmAttributes = CFI_FEATURE_ATTR_RO,
++00122          .wDataLength = DWC_CONSTANT_CPU_TO_LE16(2),
++00123          },
++00124 
++00125         /* FT_ID_TX_FIFO_DEPTH */
++00126         {
++00127          .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_TX_FIFO_DEPTH),
++00128          .bmAttributes = CFI_FEATURE_ATTR_RW,
++00129          .wDataLength = DWC_CONSTANT_CPU_TO_LE16(2),
++00130          },
++00131 
++00132         /* FT_ID_RX_FIFO_DEPTH */
++00133         {
++00134          .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_RX_FIFO_DEPTH),
++00135          .bmAttributes = CFI_FEATURE_ATTR_RW,
++00136          .wDataLength = DWC_CONSTANT_CPU_TO_LE16(2),
++00137          }
++00138 };
++00139 
++00141 cfi_string_t prop_name_table[] = {
++00142         {FT_ID_DMA_MODE, "dma_mode"},
++00143         {FT_ID_DMA_BUFFER_SETUP, "buffer_setup"},
++00144         {FT_ID_DMA_BUFF_ALIGN, "buffer_align"},
++00145         {FT_ID_DMA_CONCAT_SETUP, "concat_setup"},
++00146         {FT_ID_DMA_CIRCULAR, "buffer_circular"},
++00147         {FT_ID_THRESHOLD_SETUP, "threshold_setup"},
++00148         {FT_ID_DFIFO_DEPTH, "dfifo_depth"},
++00149         {FT_ID_TX_FIFO_DEPTH, "txfifo_depth"},
++00150         {FT_ID_RX_FIFO_DEPTH, "rxfifo_depth"},
++00151         {}
++00152 };
++00153 
++00154 /************************************************************************/
++00155 
++00161 const uint8_t *get_prop_name(uint16_t prop_id, int *len)
++00162 {
++00163         cfi_string_t *pstr;
++00164         *len = 0;
++00165 
++00166         for (pstr = prop_name_table; pstr && pstr->s; pstr++) {
++00167                 if (pstr->id == prop_id) {
++00168                         *len = DWC_STRLEN(pstr->s);
++00169                         return pstr->s;
++00170                 }
++00171         }
++00172         return NULL;
++00173 }
++00174 
++00180 int cfi_setup(struct dwc_otg_pcd *pcd, struct cfi_usb_ctrlrequest *ctrl)
++00181 {
++00182         int retval = 0;
++00183         dwc_otg_pcd_ep_t *ep = NULL;
++00184         cfiobject_t *cfi = pcd->cfi;
++00185         struct dwc_otg_core_if *coreif = GET_CORE_IF(pcd);
++00186         uint16_t wLen = DWC_LE16_TO_CPU(&ctrl->wLength);
++00187         uint16_t wValue = DWC_LE16_TO_CPU(&ctrl->wValue);
++00188         uint16_t wIndex = DWC_LE16_TO_CPU(&ctrl->wIndex);
++00189         uint32_t regaddr = 0;
++00190         uint32_t regval = 0;
++00191 
++00192         /* Save this Control Request in the CFI object. 
++00193          * The data field will be assigned in the data stage completion CB function.
++00194          */
++00195         cfi->ctrl_req = *ctrl;
++00196         cfi->ctrl_req.data = NULL;
++00197 
++00198         cfi->need_gadget_att = 0;
++00199         cfi->need_status_in_complete = 0;
++00200 
++00201         switch (ctrl->bRequest) {
++00202         case VEN_CORE_GET_FEATURES:
++00203                 retval = cfi_core_features_buf(cfi->buf_in.buf, CFI_IN_BUF_LEN);
++00204                 if (retval >= 0) {
++00205                         //dump_msg(cfi->buf_in.buf, retval);
++00206                         ep = &pcd->ep0;
++00207 
++00208                         retval = min((uint16_t) retval, wLen);
++00209                         /* Transfer this buffer to the host through the EP0-IN EP */
++00210                         ep->dwc_ep.dma_addr = cfi->buf_in.addr;
++00211                         ep->dwc_ep.start_xfer_buff = cfi->buf_in.buf;
++00212                         ep->dwc_ep.xfer_buff = cfi->buf_in.buf;
++00213                         ep->dwc_ep.xfer_len = retval;
++00214                         ep->dwc_ep.xfer_count = 0;
++00215                         ep->dwc_ep.sent_zlp = 0;
++00216                         ep->dwc_ep.total_len = ep->dwc_ep.xfer_len;
++00217 
++00218                         pcd->ep0_pending = 1;
++00219                         dwc_otg_ep0_start_transfer(coreif, &ep->dwc_ep);
++00220                 }
++00221                 retval = 0;
++00222                 break;
++00223 
++00224         case VEN_CORE_GET_FEATURE:
++00225                 CFI_INFO("VEN_CORE_GET_FEATURE\n");
++00226                 retval = cfi_get_feature_value(cfi->buf_in.buf, CFI_IN_BUF_LEN,
++00227                                                pcd, ctrl);
++00228                 if (retval >= 0) {
++00229                         ep = &pcd->ep0;
++00230 
++00231                         retval = min((uint16_t) retval, wLen);
++00232                         /* Transfer this buffer to the host through the EP0-IN EP */
++00233                         ep->dwc_ep.dma_addr = cfi->buf_in.addr;
++00234                         ep->dwc_ep.start_xfer_buff = cfi->buf_in.buf;
++00235                         ep->dwc_ep.xfer_buff = cfi->buf_in.buf;
++00236                         ep->dwc_ep.xfer_len = retval;
++00237                         ep->dwc_ep.xfer_count = 0;
++00238                         ep->dwc_ep.sent_zlp = 0;
++00239                         ep->dwc_ep.total_len = ep->dwc_ep.xfer_len;
++00240 
++00241                         pcd->ep0_pending = 1;
++00242                         dwc_otg_ep0_start_transfer(coreif, &ep->dwc_ep);
++00243                 }
++00244                 CFI_INFO("VEN_CORE_GET_FEATURE=%d\n", retval);
++00245                 dump_msg(cfi->buf_in.buf, retval);
++00246                 break;
++00247 
++00248         case VEN_CORE_SET_FEATURE:
++00249                 CFI_INFO("VEN_CORE_SET_FEATURE\n");
++00250                 /* Set up an XFER to get the data stage of the control request,
++00251                  * which is the new value of the feature to be modified.
++00252                  */
++00253                 ep = &pcd->ep0;
++00254                 ep->dwc_ep.is_in = 0;
++00255                 ep->dwc_ep.dma_addr = cfi->buf_out.addr;
++00256                 ep->dwc_ep.start_xfer_buff = cfi->buf_out.buf;
++00257                 ep->dwc_ep.xfer_buff = cfi->buf_out.buf;
++00258                 ep->dwc_ep.xfer_len = wLen;
++00259                 ep->dwc_ep.xfer_count = 0;
++00260                 ep->dwc_ep.sent_zlp = 0;
++00261                 ep->dwc_ep.total_len = ep->dwc_ep.xfer_len;
++00262 
++00263                 pcd->ep0_pending = 1;
++00264                 /* Read the control write's data stage */
++00265                 dwc_otg_ep0_start_transfer(coreif, &ep->dwc_ep);
++00266                 retval = 0;
++00267                 break;
++00268 
++00269         case VEN_CORE_RESET_FEATURES:
++00270                 CFI_INFO("VEN_CORE_RESET_FEATURES\n");
++00271                 cfi->need_gadget_att = 1;
++00272                 cfi->need_status_in_complete = 1;
++00273                 retval = cfi_preproc_reset(pcd, ctrl);
++00274                 CFI_INFO("VEN_CORE_RESET_FEATURES = (%d)\n", retval);
++00275                 break;
++00276 
++00277         case VEN_CORE_ACTIVATE_FEATURES:
++00278                 CFI_INFO("VEN_CORE_ACTIVATE_FEATURES\n");
++00279                 break;
++00280 
++00281         case VEN_CORE_READ_REGISTER:
++00282                 CFI_INFO("VEN_CORE_READ_REGISTER\n");
++00283                 /* wValue optionally contains the HI WORD of the register offset and
++00284                  * wIndex contains the LOW WORD of the register offset 
++00285                  */
++00286                 if (wValue == 0) {
++00287                         /* @TODO - MAS - fix the access to the base field */
++00288                         regaddr = 0;
++00289                         //regaddr = (uint32_t) pcd->otg_dev->os_dep.base;
++00290                         //GET_CORE_IF(pcd)->co
++00291                         regaddr |= wIndex;
++00292                 } else {
++00293                         regaddr = (wValue << 16) | wIndex;
++00294                 }
++00295 
++00296                 /* Read a 32-bit value of the memory at the regaddr */
++00297                 regval = DWC_READ_REG32((uint32_t *) regaddr);
++00298 
++00299                 ep = &pcd->ep0;
++00300                 dwc_memcpy(cfi->buf_in.buf, &regval, sizeof(uint32_t));
++00301                 ep->dwc_ep.is_in = 1;
++00302                 ep->dwc_ep.dma_addr = cfi->buf_in.addr;
++00303                 ep->dwc_ep.start_xfer_buff = cfi->buf_in.buf;
++00304                 ep->dwc_ep.xfer_buff = cfi->buf_in.buf;
++00305                 ep->dwc_ep.xfer_len = wLen;
++00306                 ep->dwc_ep.xfer_count = 0;
++00307                 ep->dwc_ep.sent_zlp = 0;
++00308                 ep->dwc_ep.total_len = ep->dwc_ep.xfer_len;
++00309 
++00310                 pcd->ep0_pending = 1;
++00311                 dwc_otg_ep0_start_transfer(coreif, &ep->dwc_ep);
++00312                 cfi->need_gadget_att = 0;
++00313                 retval = 0;
++00314                 break;
++00315 
++00316         case VEN_CORE_WRITE_REGISTER:
++00317                 CFI_INFO("VEN_CORE_WRITE_REGISTER\n");
++00318                 /* Set up an XFER to get the data stage of the control request,
++00319                  * which is the new value of the register to be modified.
++00320                  */
++00321                 ep = &pcd->ep0;
++00322                 ep->dwc_ep.is_in = 0;
++00323                 ep->dwc_ep.dma_addr = cfi->buf_out.addr;
++00324                 ep->dwc_ep.start_xfer_buff = cfi->buf_out.buf;
++00325                 ep->dwc_ep.xfer_buff = cfi->buf_out.buf;
++00326                 ep->dwc_ep.xfer_len = wLen;
++00327                 ep->dwc_ep.xfer_count = 0;
++00328                 ep->dwc_ep.sent_zlp = 0;
++00329                 ep->dwc_ep.total_len = ep->dwc_ep.xfer_len;
++00330 
++00331                 pcd->ep0_pending = 1;
++00332                 /* Read the control write's data stage */
++00333                 dwc_otg_ep0_start_transfer(coreif, &ep->dwc_ep);
++00334                 retval = 0;
++00335                 break;
++00336 
++00337         default:
++00338                 retval = -DWC_E_NOT_SUPPORTED;
++00339                 break;
++00340         }
++00341 
++00342         return retval;
++00343 }
++00344 
++00356 static int cfi_core_features_buf(uint8_t * buf, uint16_t buflen)
++00357 {
++00358         cfi_feature_desc_header_t *prop_hdr = prop_descs;
++00359         cfi_feature_desc_header_t *prop;
++00360         cfi_all_features_header_t *all_props_hdr = &all_props_desc_header;
++00361         cfi_all_features_header_t *tmp;
++00362         uint8_t *tmpbuf = buf;
++00363         const uint8_t *pname = NULL;
++00364         int i, j, namelen = 0, totlen;
++00365 
++00366         /* Prepare and copy the core features into the buffer */
++00367         CFI_INFO("%s:\n", __func__);
++00368 
++00369         tmp = (cfi_all_features_header_t *) tmpbuf;
++00370         *tmp = *all_props_hdr;
++00371         tmpbuf += CFI_ALL_FEATURES_HDR_LEN;
++00372 
++00373         j = sizeof(prop_descs) / sizeof(cfi_all_features_header_t);
++00374         for (i = 0; i < j; i++, prop_hdr++) {
++00375                 pname = get_prop_name(prop_hdr->wFeatureID, &namelen);
++00376                 prop = (cfi_feature_desc_header_t *) tmpbuf;
++00377                 *prop = *prop_hdr;
++00378 
++00379                 prop->bNameLen = namelen;
++00380                 prop->wLength =
++00381                     DWC_CONSTANT_CPU_TO_LE16(CFI_FEATURE_DESC_HDR_LEN +
++00382                                              namelen);
++00383 
++00384                 tmpbuf += CFI_FEATURE_DESC_HDR_LEN;
++00385                 dwc_memcpy(tmpbuf, pname, namelen);
++00386                 tmpbuf += namelen;
++00387         }
++00388 
++00389         totlen = tmpbuf - buf;
++00390 
++00391         if (totlen > 0) {
++00392                 tmp = (cfi_all_features_header_t *) buf;
++00393                 tmp->wTotalLen = DWC_CONSTANT_CPU_TO_LE16(totlen);
++00394         }
++00395 
++00396         return totlen;
++00397 }
++00398 
++00402 static void cfi_release(cfiobject_t * cfiobj)
++00403 {
++00404         cfi_ep_t *cfiep;
++00405         dwc_list_link_t *tmp;
++00406 
++00407         CFI_INFO("%s\n", __func__);
++00408 
++00409         if (cfiobj->buf_in.buf) {
++00410                 DWC_DMA_FREE(CFI_IN_BUF_LEN, cfiobj->buf_in.buf,
++00411                              cfiobj->buf_in.addr);
++00412                 cfiobj->buf_in.buf = NULL;
++00413         }
++00414 
++00415         if (cfiobj->buf_out.buf) {
++00416                 DWC_DMA_FREE(CFI_OUT_BUF_LEN, cfiobj->buf_out.buf,
++00417                              cfiobj->buf_out.addr);
++00418                 cfiobj->buf_out.buf = NULL;
++00419         }
++00420 
++00421         /* Free the Buffer Setup values for each EP */
++00422         //list_for_each_entry(cfiep, &cfiobj->active_eps, lh) {
++00423         DWC_LIST_FOREACH(tmp, &cfiobj->active_eps) {
++00424                 cfiep = DWC_LIST_ENTRY(tmp, struct cfi_ep, lh);
++00425                 cfi_free_ep_bs_dyn_data(cfiep);
++00426         }
++00427 }
++00428 
++00432 static void cfi_free_ep_bs_dyn_data(cfi_ep_t * cfiep)
++00433 {
++00434         if (cfiep->bm_sg) {
++00435                 DWC_FREE(cfiep->bm_sg);
++00436                 cfiep->bm_sg = NULL;
++00437         }
++00438 
++00439         if (cfiep->bm_align) {
++00440                 DWC_FREE(cfiep->bm_align);
++00441                 cfiep->bm_align = NULL;
++00442         }
++00443 
++00444         if (cfiep->bm_concat) {
++00445                 if (NULL != cfiep->bm_concat->wTxBytes) {
++00446                         DWC_FREE(cfiep->bm_concat->wTxBytes);
++00447                         cfiep->bm_concat->wTxBytes = NULL;
++00448                 }
++00449                 DWC_FREE(cfiep->bm_concat);
++00450                 cfiep->bm_concat = NULL;
++00451         }
++00452 }
++00453 
++00459 static int cfi_ep_init_defaults(struct dwc_otg_pcd *pcd, cfi_ep_t * cfiep)
++00460 {
++00461         int retval = 0;
++00462 
++00463         cfiep->bm_sg = DWC_ALLOC(sizeof(ddma_sg_buffer_setup_t));
++00464         if (NULL == cfiep->bm_sg) {
++00465                 CFI_INFO("Failed to allocate memory for SG feature value\n");
++00466                 return -DWC_E_NO_MEMORY;
++00467         }
++00468         dwc_memset(cfiep->bm_sg, 0, sizeof(ddma_sg_buffer_setup_t));
++00469 
++00470         /* For the Concatenation feature's default value we do not allocate
++00471          * memory for the wTxBytes field - it will be done in the set_feature_value
++00472          * request handler.
++00473          */
++00474         cfiep->bm_concat = DWC_ALLOC(sizeof(ddma_concat_buffer_setup_t));
++00475         if (NULL == cfiep->bm_concat) {
++00476                 CFI_INFO
++00477                     ("Failed to allocate memory for CONCATENATION feature value\n");
++00478                 DWC_FREE(cfiep->bm_sg);
++00479                 return -DWC_E_NO_MEMORY;
++00480         }
++00481         dwc_memset(cfiep->bm_concat, 0, sizeof(ddma_concat_buffer_setup_t));
++00482 
++00483         cfiep->bm_align = DWC_ALLOC(sizeof(ddma_align_buffer_setup_t));
++00484         if (NULL == cfiep->bm_align) {
++00485                 CFI_INFO
++00486                     ("Failed to allocate memory for Alignment feature value\n");
++00487                 DWC_FREE(cfiep->bm_sg);
++00488                 DWC_FREE(cfiep->bm_concat);
++00489                 return -DWC_E_NO_MEMORY;
++00490         }
++00491         dwc_memset(cfiep->bm_align, 0, sizeof(ddma_align_buffer_setup_t));
++00492 
++00493         return retval;
++00494 }
++00495 
++00507 static int cfi_ep_enable(struct cfiobject *cfi, struct dwc_otg_pcd *pcd,
++00508                          struct dwc_otg_pcd_ep *ep)
++00509 {
++00510         cfi_ep_t *cfiep;
++00511         int retval = -DWC_E_NOT_SUPPORTED;
++00512 
++00513         CFI_INFO("%s: epname=%s; epnum=0x%02x\n", __func__,
++00514                  "EP_" /*ep->ep.name */ , ep->desc->bEndpointAddress);
++00515         /* MAS - Check whether this endpoint already is in the list */
++00516         cfiep = get_cfi_ep_by_pcd_ep(cfi, ep);
++00517 
++00518         if (NULL == cfiep) {
++00519                 /* Allocate a cfi_ep_t object */
++00520                 cfiep = DWC_ALLOC(sizeof(cfi_ep_t));
++00521                 if (NULL == cfiep) {
++00522                         CFI_INFO
++00523                             ("Unable to allocate memory for <cfiep> in function %s\n",
++00524                              __func__);
++00525                         return -DWC_E_NO_MEMORY;
++00526                 }
++00527                 dwc_memset(cfiep, 0, sizeof(cfi_ep_t));
++00528 
++00529                 /* Save the dwc_otg_pcd_ep pointer in the cfiep object */
++00530                 cfiep->ep = ep;
++00531 
++00532                 /* Allocate the DMA Descriptors chain of MAX_DMA_DESCS_PER_EP count */
++00533                 ep->dwc_ep.descs =
++00534                     DWC_DMA_ALLOC(MAX_DMA_DESCS_PER_EP *
++00535                                   sizeof(dwc_otg_dma_desc_t),
++00536                                   &ep->dwc_ep.descs_dma_addr);
++00537 
++00538                 if (NULL == ep->dwc_ep.descs) {
++00539                         DWC_FREE(cfiep);
++00540                         return -DWC_E_NO_MEMORY;
++00541                 }
++00542 
++00543                 DWC_LIST_INIT(&cfiep->lh);
++00544 
++00545                 /* Set the buffer mode to BM_STANDARD. It will be modified 
++00546                  * when building descriptors for a specific buffer mode */
++00547                 ep->dwc_ep.buff_mode = BM_STANDARD;
++00548 
++00549                 /* Create and initialize the default values for this EP's Buffer modes */
++00550                 if ((retval = cfi_ep_init_defaults(pcd, cfiep)) < 0)
++00551                         return retval;
++00552 
++00553                 /* Add the cfi_ep_t object to the CFI object's list of active endpoints */
++00554                 DWC_LIST_INSERT_TAIL(&cfi->active_eps, &cfiep->lh);
++00555                 retval = 0;
++00556         } else {                /* The sought EP already is in the list */
++00557                 CFI_INFO("%s: The sought EP already is in the list\n",
++00558                          __func__);
++00559         }
++00560 
++00561         return retval;
++00562 }
++00563 
++00569 static int cfi_ctrl_write_complete(struct cfiobject *cfi,
++00570                                    struct dwc_otg_pcd *pcd)
++00571 {
++00572         uint32_t addr, reg_value;
++00573         uint16_t wIndex, wValue;
++00574         uint8_t bRequest;
++00575         uint8_t *buf = cfi->buf_out.buf;
++00576         //struct usb_ctrlrequest *ctrl_req = &cfi->ctrl_req_saved;
++00577         struct cfi_usb_ctrlrequest *ctrl_req = &cfi->ctrl_req;
++00578         int retval = -DWC_E_NOT_SUPPORTED;
++00579 
++00580         CFI_INFO("%s\n", __func__);
++00581 
++00582         bRequest = ctrl_req->bRequest;
++00583         wIndex = DWC_CONSTANT_CPU_TO_LE16(ctrl_req->wIndex);
++00584         wValue = DWC_CONSTANT_CPU_TO_LE16(ctrl_req->wValue);
++00585 
++00586         /* 
++00587          * Save the pointer to the data stage in the ctrl_req's <data> field.
++00588          * The request should be already saved in the command stage by now.
++00589          */
++00590         ctrl_req->data = cfi->buf_out.buf;
++00591         cfi->need_status_in_complete = 0;
++00592         cfi->need_gadget_att = 0;
++00593 
++00594         switch (bRequest) {
++00595         case VEN_CORE_WRITE_REGISTER:
++00596                 /* The buffer contains raw data of the new value for the register */
++00597                 reg_value = *((uint32_t *) buf);
++00598                 if (wValue == 0) {
++00599                         addr = 0;
++00600                         //addr = (uint32_t) pcd->otg_dev->os_dep.base;
++00601                         addr += wIndex;
++00602                 } else {
++00603                         addr = (wValue << 16) | wIndex;
++00604                 }
++00605 
++00606                 //writel(reg_value, addr);
++00607 
++00608                 retval = 0;
++00609                 cfi->need_status_in_complete = 1;
++00610                 break;
++00611 
++00612         case VEN_CORE_SET_FEATURE:
++00613                 /* The buffer contains raw data of the new value of the feature */
++00614                 retval = cfi_set_feature_value(pcd);
++00615                 if (retval < 0)
++00616                         return retval;
++00617 
++00618                 cfi->need_status_in_complete = 1;
++00619                 break;
++00620 
++00621         default:
++00622                 break;
++00623         }
++00624 
++00625         return retval;
++00626 }
++00627 
++00631 static void cfi_build_sg_descs(struct cfiobject *cfi, cfi_ep_t * cfiep,
++00632                                dwc_otg_pcd_request_t * req)
++00633 {
++00634         struct dwc_otg_pcd_ep *ep = cfiep->ep;
++00635         ddma_sg_buffer_setup_t *sgval = cfiep->bm_sg;
++00636         struct dwc_otg_dma_desc *desc = cfiep->ep->dwc_ep.descs;
++00637         struct dwc_otg_dma_desc *desc_last = cfiep->ep->dwc_ep.descs;
++00638         dma_addr_t buff_addr = req->dma;
++00639         int i;
++00640         uint32_t txsize, off;
++00641 
++00642         txsize = sgval->wSize;
++00643         off = sgval->bOffset;
++00644 
++00645 //      CFI_INFO("%s: %s TXSIZE=0x%08x; OFFSET=0x%08x\n", 
++00646 //              __func__, cfiep->ep->ep.name, txsize, off);
++00647 
++00648         for (i = 0; i < sgval->bCount; i++) {
++00649                 desc->status.b.bs = BS_HOST_BUSY;
++00650                 desc->buf = buff_addr;
++00651                 desc->status.b.l = 0;
++00652                 desc->status.b.ioc = 0;
++00653                 desc->status.b.sp = 0;
++00654                 desc->status.b.bytes = txsize;
++00655                 desc->status.b.bs = BS_HOST_READY;
++00656 
++00657                 /* Set the next address of the buffer */
++00658                 buff_addr += txsize + off;
++00659                 desc_last = desc;
++00660                 desc++;
++00661         }
++00662 
++00663         /* Set the last, ioc and sp bits on the Last DMA Descriptor */
++00664         desc_last->status.b.l = 1;
++00665         desc_last->status.b.ioc = 1;
++00666         desc_last->status.b.sp = ep->dwc_ep.sent_zlp;
++00667         /* Save the last DMA descriptor pointer */
++00668         cfiep->dma_desc_last = desc_last;
++00669         cfiep->desc_count = sgval->bCount;
++00670 }
++00671 
++00675 static void cfi_build_concat_descs(struct cfiobject *cfi, cfi_ep_t * cfiep,
++00676                                    dwc_otg_pcd_request_t * req)
++00677 {
++00678         struct dwc_otg_pcd_ep *ep = cfiep->ep;
++00679         ddma_concat_buffer_setup_t *concatval = cfiep->bm_concat;
++00680         struct dwc_otg_dma_desc *desc = cfiep->ep->dwc_ep.descs;
++00681         struct dwc_otg_dma_desc *desc_last = cfiep->ep->dwc_ep.descs;
++00682         dma_addr_t buff_addr = req->dma;
++00683         int i;
++00684         uint16_t *txsize;
++00685 
++00686         txsize = concatval->wTxBytes;
++00687 
++00688         for (i = 0; i < concatval->hdr.bDescCount; i++) {
++00689                 desc->buf = buff_addr;
++00690                 desc->status.b.bs = BS_HOST_BUSY;
++00691                 desc->status.b.l = 0;
++00692                 desc->status.b.ioc = 0;
++00693                 desc->status.b.sp = 0;
++00694                 desc->status.b.bytes = *txsize;
++00695                 desc->status.b.bs = BS_HOST_READY;
++00696 
++00697                 txsize++;
++00698                 /* Set the next address of the buffer */
++00699                 buff_addr += UGETW(ep->desc->wMaxPacketSize);
++00700                 desc_last = desc;
++00701                 desc++;
++00702         }
++00703 
++00704         /* Set the last, ioc and sp bits on the Last DMA Descriptor */
++00705         desc_last->status.b.l = 1;
++00706         desc_last->status.b.ioc = 1;
++00707         desc_last->status.b.sp = ep->dwc_ep.sent_zlp;
++00708         cfiep->dma_desc_last = desc_last;
++00709         cfiep->desc_count = concatval->hdr.bDescCount;
++00710 }
++00711 
++00715 static void cfi_build_circ_descs(struct cfiobject *cfi, cfi_ep_t * cfiep,
++00716                                  dwc_otg_pcd_request_t * req)
++00717 {
++00718         /* @todo: MAS - add implementation when this feature needs to be tested */
++00719 }
++00720 
++00724 static void cfi_build_align_descs(struct cfiobject *cfi, cfi_ep_t * cfiep,
++00725                                   dwc_otg_pcd_request_t * req)
++00726 {
++00727         struct dwc_otg_pcd_ep *ep = cfiep->ep;
++00728         ddma_align_buffer_setup_t *alignval = cfiep->bm_align;
++00729         struct dwc_otg_dma_desc *desc = cfiep->ep->dwc_ep.descs;
++00730         dma_addr_t buff_addr = req->dma;
++00731 
++00732         desc->status.b.bs = BS_HOST_BUSY;
++00733         desc->status.b.l = 1;
++00734         desc->status.b.ioc = 1;
++00735         desc->status.b.sp = ep->dwc_ep.sent_zlp;
++00736         desc->status.b.bytes = req->length;
++00737         /* Adjust the buffer alignment */
++00738         desc->buf = (buff_addr + alignval->bAlign);
++00739         desc->status.b.bs = BS_HOST_READY;
++00740         cfiep->dma_desc_last = desc;
++00741         cfiep->desc_count = 1;
++00742 }
++00743 
++00748 static void cfi_build_descriptors(struct cfiobject *cfi,
++00749                                   struct dwc_otg_pcd *pcd,
++00750                                   struct dwc_otg_pcd_ep *ep,
++00751                                   dwc_otg_pcd_request_t * req)
++00752 {
++00753         cfi_ep_t *cfiep;
++00754 
++00755         /* Get the cfiep by the dwc_otg_pcd_ep */
++00756         cfiep = get_cfi_ep_by_pcd_ep(cfi, ep);
++00757         if (NULL == cfiep) {
++00758                 CFI_INFO("%s: Unable to find a matching active endpoint\n",
++00759                          __func__);
++00760                 return;
++00761         }
++00762 
++00763         cfiep->xfer_len = req->length;
++00764 
++00765         /* Iterate through all the DMA descriptors */
++00766         switch (cfiep->ep->dwc_ep.buff_mode) {
++00767         case BM_SG:
++00768                 cfi_build_sg_descs(cfi, cfiep, req);
++00769                 break;
++00770 
++00771         case BM_CONCAT:
++00772                 cfi_build_concat_descs(cfi, cfiep, req);
++00773                 break;
++00774 
++00775         case BM_CIRCULAR:
++00776                 cfi_build_circ_descs(cfi, cfiep, req);
++00777                 break;
++00778 
++00779         case BM_ALIGN:
++00780                 cfi_build_align_descs(cfi, cfiep, req);
++00781                 break;
++00782 
++00783         default:
++00784                 break;
++00785         }
++00786 }
++00787 
++00791 static void *cfi_ep_alloc_buf(struct cfiobject *cfi, struct dwc_otg_pcd *pcd,
++00792                               struct dwc_otg_pcd_ep *ep, dma_addr_t * dma,
++00793                               unsigned size, gfp_t flags)
++00794 {
++00795         return DWC_DMA_ALLOC(size, dma);
++00796 }
++00797 
++00801 int init_cfi(cfiobject_t * cfiobj)
++00802 {
++00803         CFI_INFO("%s\n", __func__);
++00804 
++00805         /* Allocate a buffer for IN XFERs */
++00806         cfiobj->buf_in.buf =
++00807             DWC_DMA_ALLOC(CFI_IN_BUF_LEN, &cfiobj->buf_in.addr);
++00808         if (NULL == cfiobj->buf_in.buf) {
++00809                 CFI_INFO("Unable to allocate buffer for INs\n");
++00810                 return -DWC_E_NO_MEMORY;
++00811         }
++00812 
++00813         /* Allocate a buffer for OUT XFERs */
++00814         cfiobj->buf_out.buf =
++00815             DWC_DMA_ALLOC(CFI_OUT_BUF_LEN, &cfiobj->buf_out.addr);
++00816         if (NULL == cfiobj->buf_out.buf) {
++00817                 CFI_INFO("Unable to allocate buffer for OUT\n");
++00818                 return -DWC_E_NO_MEMORY;
++00819         }
++00820 
++00821         /* Initialize the callback function pointers */
++00822         cfiobj->ops.release = cfi_release;
++00823         cfiobj->ops.ep_enable = cfi_ep_enable;
++00824         cfiobj->ops.ctrl_write_complete = cfi_ctrl_write_complete;
++00825         cfiobj->ops.build_descriptors = cfi_build_descriptors;
++00826         cfiobj->ops.ep_alloc_buf = cfi_ep_alloc_buf;
++00827 
++00828         /* Initialize the list of active endpoints in the CFI object */
++00829         DWC_LIST_INIT(&cfiobj->active_eps);
++00830 
++00831         return 0;
++00832 }
++00833 
++00839 static int cfi_get_feature_value(uint8_t * buf, uint16_t buflen,
++00840                                  struct dwc_otg_pcd *pcd,
++00841                                  struct cfi_usb_ctrlrequest *ctrl_req)
++00842 {
++00843         int retval = -DWC_E_NOT_SUPPORTED;
++00844         struct dwc_otg_core_if *coreif = GET_CORE_IF(pcd);
++00845         uint16_t dfifo, rxfifo, txfifo;
++00846 
++00847         switch (ctrl_req->wIndex) {
++00848                 /* Whether the DDMA is enabled or not */
++00849         case FT_ID_DMA_MODE:
++00850                 *buf = (coreif->dma_enable && coreif->dma_desc_enable) ? 1 : 0;
++00851                 retval = 1;
++00852                 break;
++00853 
++00854         case FT_ID_DMA_BUFFER_SETUP:
++00855                 retval = cfi_ep_get_sg_val(buf, pcd, ctrl_req);
++00856                 break;
++00857 
++00858         case FT_ID_DMA_BUFF_ALIGN:
++00859                 retval = cfi_ep_get_align_val(buf, pcd, ctrl_req);
++00860                 break;
++00861 
++00862         case FT_ID_DMA_CONCAT_SETUP:
++00863                 retval = cfi_ep_get_concat_val(buf, pcd, ctrl_req);
++00864                 break;
++00865 
++00866         case FT_ID_DMA_CIRCULAR:
++00867                 CFI_INFO("GetFeature value (FT_ID_DMA_CIRCULAR)\n");
++00868                 break;
++00869 
++00870         case FT_ID_THRESHOLD_SETUP:
++00871                 CFI_INFO("GetFeature value (FT_ID_THRESHOLD_SETUP)\n");
++00872                 break;
++00873 
++00874         case FT_ID_DFIFO_DEPTH:
++00875                 dfifo = get_dfifo_size(coreif);
++00876                 *((uint16_t *) buf) = dfifo;
++00877                 retval = sizeof(uint16_t);
++00878                 break;
++00879 
++00880         case FT_ID_TX_FIFO_DEPTH:
++00881                 retval = get_txfifo_size(pcd, ctrl_req->wValue);
++00882                 if (retval >= 0) {
++00883                         txfifo = retval;
++00884                         *((uint16_t *) buf) = txfifo;
++00885                         retval = sizeof(uint16_t);
++00886                 }
++00887                 break;
++00888 
++00889         case FT_ID_RX_FIFO_DEPTH:
++00890                 retval = get_rxfifo_size(coreif, ctrl_req->wValue);
++00891                 if (retval >= 0) {
++00892                         rxfifo = retval;
++00893                         *((uint16_t *) buf) = rxfifo;
++00894                         retval = sizeof(uint16_t);
++00895                 }
++00896                 break;
++00897         }
++00898 
++00899         return retval;
++00900 }
++00901 
++00905 static int cfi_reset_sg_val(cfi_ep_t * cfiep)
++00906 {
++00907         dwc_memset(cfiep->bm_sg, 0, sizeof(ddma_sg_buffer_setup_t));
++00908         return 0;
++00909 }
++00910 
++00914 static int cfi_reset_align_val(cfi_ep_t * cfiep)
++00915 {
++00916         dwc_memset(cfiep->bm_sg, 0, sizeof(ddma_sg_buffer_setup_t));
++00917         return 0;
++00918 }
++00919 
++00925 static int cfi_reset_concat_val(cfi_ep_t * cfiep)
++00926 {
++00927         /* First we need to free the wTxBytes field */
++00928         if (cfiep->bm_concat->wTxBytes) {
++00929                 DWC_FREE(cfiep->bm_concat->wTxBytes);
++00930                 cfiep->bm_concat->wTxBytes = NULL;
++00931         }
++00932 
++00933         dwc_memset(cfiep->bm_concat, 0, sizeof(ddma_concat_buffer_setup_t));
++00934         return 0;
++00935 }
++00936 
++00940 static int cfi_ep_reset_all_setup_vals(cfi_ep_t * cfiep)
++00941 {
++00942         cfi_reset_sg_val(cfiep);
++00943         cfi_reset_align_val(cfiep);
++00944         cfi_reset_concat_val(cfiep);
++00945         return 0;
++00946 }
++00947 
++00948 static int cfi_handle_reset_fifo_val(struct dwc_otg_pcd *pcd, uint8_t ep_addr,
++00949                                      uint8_t rx_rst, uint8_t tx_rst)
++00950 {
++00951         int retval = -DWC_E_INVALID;
++00952         uint16_t tx_siz[15];
++00953         uint16_t rx_siz = 0;
++00954         dwc_otg_pcd_ep_t *ep = NULL;
++00955         dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
++00956         dwc_otg_core_params_t *params = GET_CORE_IF(pcd)->core_params;
++00957 
++00958         if (rx_rst) {
++00959                 rx_siz = params->dev_rx_fifo_size;
++00960                 params->dev_rx_fifo_size = GET_CORE_IF(pcd)->init_rxfsiz;
++00961         }
++00962 
++00963         if (tx_rst) {
++00964                 if (ep_addr == 0) {
++00965                         int i;
++00966 
++00967                         for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {
++00968                                 tx_siz[i] =
++00969                                     core_if->core_params->dev_tx_fifo_size[i];
++00970                                 core_if->core_params->dev_tx_fifo_size[i] =
++00971                                     core_if->init_txfsiz[i];
++00972                         }
++00973                 } else {
++00974 
++00975                         ep = get_ep_by_addr(pcd, ep_addr);
++00976 
++00977                         if (NULL == ep) {
++00978                                 CFI_INFO
++00979                                     ("%s: Unable to get the endpoint addr=0x%02x\n",
++00980                                      __func__, ep_addr);
++00981                                 return -DWC_E_INVALID;
++00982                         }
++00983 
++00984                         tx_siz[0] =
++00985                             params->dev_tx_fifo_size[ep->dwc_ep.tx_fifo_num -
++00986                                                      1];
++00987                         params->dev_tx_fifo_size[ep->dwc_ep.tx_fifo_num - 1] =
++00988                             GET_CORE_IF(pcd)->init_txfsiz[ep->
++00989                                                           dwc_ep.tx_fifo_num -
++00990                                                           1];
++00991                 }
++00992         }
++00993 
++00994         if (resize_fifos(GET_CORE_IF(pcd))) {
++00995                 retval = 0;
++00996         } else {
++00997                 CFI_INFO
++00998                     ("%s: Error resetting the feature Reset All(FIFO size)\n",
++00999                      __func__);
++01000                 if (rx_rst) {
++01001                         params->dev_rx_fifo_size = rx_siz;
++01002                 }
++01003 
++01004                 if (tx_rst) {
++01005                         if (ep_addr == 0) {
++01006                                 int i;
++01007                                 for (i = 0; i < core_if->hwcfg4.b.num_in_eps;
++01008                                      i++) {
++01009                                         core_if->
++01010                                             core_params->dev_tx_fifo_size[i] =
++01011                                             tx_siz[i];
++01012                                 }
++01013                         } else {
++01014                                 params->dev_tx_fifo_size[ep->
++01015                                                          dwc_ep.tx_fifo_num -
++01016                                                          1] = tx_siz[0];
++01017                         }
++01018                 }
++01019                 retval = -DWC_E_INVALID;
++01020         }
++01021         return retval;
++01022 }
++01023 
++01024 static int cfi_handle_reset_all(struct dwc_otg_pcd *pcd, uint8_t addr)
++01025 {
++01026         int retval = 0;
++01027         cfi_ep_t *cfiep;
++01028         cfiobject_t *cfi = pcd->cfi;
++01029         dwc_list_link_t *tmp;
++01030 
++01031         retval = cfi_handle_reset_fifo_val(pcd, addr, 1, 1);
++01032         if (retval < 0) {
++01033                 return retval;
++01034         }
++01035 
++01036         /* If the EP address is known then reset the features for only that EP */
++01037         if (addr) {
++01038                 cfiep = get_cfi_ep_by_addr(pcd->cfi, addr);
++01039                 if (NULL == cfiep) {
++01040                         CFI_INFO("%s: Error getting the EP address 0x%02x\n",
++01041                                  __func__, addr);
++01042                         return -DWC_E_INVALID;
++01043                 }
++01044                 retval = cfi_ep_reset_all_setup_vals(cfiep);
++01045                 cfiep->ep->dwc_ep.buff_mode = BM_STANDARD;
++01046         }
++01047         /* Otherwise (wValue == 0), reset all features of all EP's */
++01048         else {
++01049                 /* Traverse all the active EP's and reset the feature(s) value(s) */
++01050                 //list_for_each_entry(cfiep, &cfi->active_eps, lh) {
++01051                 DWC_LIST_FOREACH(tmp, &cfi->active_eps) {
++01052                         cfiep = DWC_LIST_ENTRY(tmp, struct cfi_ep, lh);
++01053                         retval = cfi_ep_reset_all_setup_vals(cfiep);
++01054                         cfiep->ep->dwc_ep.buff_mode = BM_STANDARD;
++01055                         if (retval < 0) {
++01056                                 CFI_INFO
++01057                                     ("%s: Error resetting the feature Reset All\n",
++01058                                      __func__);
++01059                                 return retval;
++01060                         }
++01061                 }
++01062         }
++01063         return retval;
++01064 }
++01065 
++01066 static int cfi_handle_reset_dma_buff_setup(struct dwc_otg_pcd *pcd,
++01067                                            uint8_t addr)
++01068 {
++01069         int retval = 0;
++01070         cfi_ep_t *cfiep;
++01071         cfiobject_t *cfi = pcd->cfi;
++01072         dwc_list_link_t *tmp;
++01073 
++01074         /* If the EP address is known then reset the features for only that EP */
++01075         if (addr) {
++01076                 cfiep = get_cfi_ep_by_addr(pcd->cfi, addr);
++01077                 if (NULL == cfiep) {
++01078                         CFI_INFO("%s: Error getting the EP address 0x%02x\n",
++01079                                  __func__, addr);
++01080                         return -DWC_E_INVALID;
++01081                 }
++01082                 retval = cfi_reset_sg_val(cfiep);
++01083         }
++01084         /* Otherwise (wValue == 0), reset all features of all EP's */
++01085         else {
++01086                 /* Traverse all the active EP's and reset the feature(s) value(s) */
++01087                 //list_for_each_entry(cfiep, &cfi->active_eps, lh) {
++01088                 DWC_LIST_FOREACH(tmp, &cfi->active_eps) {
++01089                         cfiep = DWC_LIST_ENTRY(tmp, struct cfi_ep, lh);
++01090                         retval = cfi_reset_sg_val(cfiep);
++01091                         if (retval < 0) {
++01092                                 CFI_INFO
++01093                                     ("%s: Error resetting the feature Buffer Setup\n",
++01094                                      __func__);
++01095                                 return retval;
++01096                         }
++01097                 }
++01098         }
++01099         return retval;
++01100 }
++01101 
++01102 static int cfi_handle_reset_concat_val(struct dwc_otg_pcd *pcd, uint8_t addr)
++01103 {
++01104         int retval = 0;
++01105         cfi_ep_t *cfiep;
++01106         cfiobject_t *cfi = pcd->cfi;
++01107         dwc_list_link_t *tmp;
++01108 
++01109         /* If the EP address is known then reset the features for only that EP */
++01110         if (addr) {
++01111                 cfiep = get_cfi_ep_by_addr(pcd->cfi, addr);
++01112                 if (NULL == cfiep) {
++01113                         CFI_INFO("%s: Error getting the EP address 0x%02x\n",
++01114                                  __func__, addr);
++01115                         return -DWC_E_INVALID;
++01116                 }
++01117                 retval = cfi_reset_concat_val(cfiep);
++01118         }
++01119         /* Otherwise (wValue == 0), reset all features of all EP's */
++01120         else {
++01121                 /* Traverse all the active EP's and reset the feature(s) value(s) */
++01122                 //list_for_each_entry(cfiep, &cfi->active_eps, lh) {
++01123                 DWC_LIST_FOREACH(tmp, &cfi->active_eps) {
++01124                         cfiep = DWC_LIST_ENTRY(tmp, struct cfi_ep, lh);
++01125                         retval = cfi_reset_concat_val(cfiep);
++01126                         if (retval < 0) {
++01127                                 CFI_INFO
++01128                                     ("%s: Error resetting the feature Concatenation Value\n",
++01129                                      __func__);
++01130                                 return retval;
++01131                         }
++01132                 }
++01133         }
++01134         return retval;
++01135 }
++01136 
++01137 static int cfi_handle_reset_align_val(struct dwc_otg_pcd *pcd, uint8_t addr)
++01138 {
++01139         int retval = 0;
++01140         cfi_ep_t *cfiep;
++01141         cfiobject_t *cfi = pcd->cfi;
++01142         dwc_list_link_t *tmp;
++01143 
++01144         /* If the EP address is known then reset the features for only that EP */
++01145         if (addr) {
++01146                 cfiep = get_cfi_ep_by_addr(pcd->cfi, addr);
++01147                 if (NULL == cfiep) {
++01148                         CFI_INFO("%s: Error getting the EP address 0x%02x\n",
++01149                                  __func__, addr);
++01150                         return -DWC_E_INVALID;
++01151                 }
++01152                 retval = cfi_reset_align_val(cfiep);
++01153         }
++01154         /* Otherwise (wValue == 0), reset all features of all EP's */
++01155         else {
++01156                 /* Traverse all the active EP's and reset the feature(s) value(s) */
++01157                 //list_for_each_entry(cfiep, &cfi->active_eps, lh) {
++01158                 DWC_LIST_FOREACH(tmp, &cfi->active_eps) {
++01159                         cfiep = DWC_LIST_ENTRY(tmp, struct cfi_ep, lh);
++01160                         retval = cfi_reset_align_val(cfiep);
++01161                         if (retval < 0) {
++01162                                 CFI_INFO
++01163                                     ("%s: Error resetting the feature Aliignment Value\n",
++01164                                      __func__);
++01165                                 return retval;
++01166                         }
++01167                 }
++01168         }
++01169         return retval;
++01170 
++01171 }
++01172 
++01173 static int cfi_preproc_reset(struct dwc_otg_pcd *pcd,
++01174                              struct cfi_usb_ctrlrequest *req)
++01175 {
++01176         int retval = 0;
++01177 
++01178         switch (req->wIndex) {
++01179         case 0:
++01180                 /* Reset all features */
++01181                 retval = cfi_handle_reset_all(pcd, req->wValue & 0xff);
++01182                 break;
++01183 
++01184         case FT_ID_DMA_BUFFER_SETUP:
++01185                 /* Reset the SG buffer setup */
++01186                 retval =
++01187                     cfi_handle_reset_dma_buff_setup(pcd, req->wValue & 0xff);
++01188                 break;
++01189 
++01190         case FT_ID_DMA_CONCAT_SETUP:
++01191                 /* Reset the Concatenation buffer setup */
++01192                 retval = cfi_handle_reset_concat_val(pcd, req->wValue & 0xff);
++01193                 break;
++01194 
++01195         case FT_ID_DMA_BUFF_ALIGN:
++01196                 /* Reset the Alignment buffer setup */
++01197                 retval = cfi_handle_reset_align_val(pcd, req->wValue & 0xff);
++01198                 break;
++01199 
++01200         case FT_ID_TX_FIFO_DEPTH:
++01201                 retval =
++01202                     cfi_handle_reset_fifo_val(pcd, req->wValue & 0xff, 0, 1);
++01203                 pcd->cfi->need_gadget_att = 0;
++01204                 break;
++01205 
++01206         case FT_ID_RX_FIFO_DEPTH:
++01207                 retval = cfi_handle_reset_fifo_val(pcd, 0, 1, 0);
++01208                 pcd->cfi->need_gadget_att = 0;
++01209                 break;
++01210         default:
++01211                 break;
++01212         }
++01213         return retval;
++01214 }
++01215 
++01219 static int cfi_ep_set_sg_val(uint8_t * buf, struct dwc_otg_pcd *pcd)
++01220 {
++01221         uint8_t inaddr, outaddr;
++01222         cfi_ep_t *epin, *epout;
++01223         ddma_sg_buffer_setup_t *psgval;
++01224         uint32_t desccount, size;
++01225 
++01226         CFI_INFO("%s\n", __func__);
++01227 
++01228         psgval = (ddma_sg_buffer_setup_t *) buf;
++01229         desccount = (uint32_t) psgval->bCount;
++01230         size = (uint32_t) psgval->wSize;
++01231 
++01232         /* Check the DMA descriptor count */
++01233         if ((desccount > MAX_DMA_DESCS_PER_EP) || (desccount == 0)) {
++01234                 CFI_INFO
++01235                     ("%s: The count of DMA Descriptors should be between 1 and %d\n",
++01236                      __func__, MAX_DMA_DESCS_PER_EP);
++01237                 return -DWC_E_INVALID;
++01238         }
++01239 
++01240         /* Check the DMA descriptor count */
++01241 
++01242         if (size == 0) {
++01243 
++01244                 CFI_INFO("%s: The transfer size should be at least 1 byte\n",
++01245                          __func__);
++01246 
++01247                 return -DWC_E_INVALID;
++01248 
++01249         }
++01250 
++01251         inaddr = psgval->bInEndpointAddress;
++01252         outaddr = psgval->bOutEndpointAddress;
++01253 
++01254         epin = get_cfi_ep_by_addr(pcd->cfi, inaddr);
++01255         epout = get_cfi_ep_by_addr(pcd->cfi, outaddr);
++01256 
++01257         if (NULL == epin || NULL == epout) {
++01258                 CFI_INFO
++01259                     ("%s: Unable to get the endpoints inaddr=0x%02x outaddr=0x%02x\n",
++01260                      __func__, inaddr, outaddr);
++01261                 return -DWC_E_INVALID;
++01262         }
++01263 
++01264         epin->ep->dwc_ep.buff_mode = BM_SG;
++01265         dwc_memcpy(epin->bm_sg, psgval, sizeof(ddma_sg_buffer_setup_t));
++01266 
++01267         epout->ep->dwc_ep.buff_mode = BM_SG;
++01268         dwc_memcpy(epout->bm_sg, psgval, sizeof(ddma_sg_buffer_setup_t));
++01269 
++01270         return 0;
++01271 }
++01272 
++01276 static int cfi_ep_set_alignment_val(uint8_t * buf, struct dwc_otg_pcd *pcd)
++01277 {
++01278         cfi_ep_t *ep;
++01279         uint8_t addr;
++01280         ddma_align_buffer_setup_t *palignval;
++01281 
++01282         palignval = (ddma_align_buffer_setup_t *) buf;
++01283         addr = palignval->bEndpointAddress;
++01284 
++01285         ep = get_cfi_ep_by_addr(pcd->cfi, addr);
++01286 
++01287         if (NULL == ep) {
++01288                 CFI_INFO("%s: Unable to get the endpoint addr=0x%02x\n",
++01289                          __func__, addr);
++01290                 return -DWC_E_INVALID;
++01291         }
++01292 
++01293         ep->ep->dwc_ep.buff_mode = BM_ALIGN;
++01294         dwc_memcpy(ep->bm_align, palignval, sizeof(ddma_align_buffer_setup_t));
++01295 
++01296         return 0;
++01297 }
++01298 
++01302 static int cfi_ep_set_concat_val(uint8_t * buf, struct dwc_otg_pcd *pcd)
++01303 {
++01304         uint8_t addr;
++01305         cfi_ep_t *ep;
++01306         struct _ddma_concat_buffer_setup_hdr *pConcatValHdr;
++01307         uint16_t *pVals;
++01308         uint32_t desccount;
++01309         int i;
++01310         uint16_t mps;
++01311 
++01312         pConcatValHdr = (struct _ddma_concat_buffer_setup_hdr *)buf;
++01313         desccount = (uint32_t) pConcatValHdr->bDescCount;
++01314         pVals = (uint16_t *) (buf + BS_CONCAT_VAL_HDR_LEN);
++01315 
++01316         /* Check the DMA descriptor count */
++01317         if (desccount > MAX_DMA_DESCS_PER_EP) {
++01318                 CFI_INFO("%s: Maximum DMA Descriptor count should be %d\n",
++01319                          __func__, MAX_DMA_DESCS_PER_EP);
++01320                 return -DWC_E_INVALID;
++01321         }
++01322 
++01323         addr = pConcatValHdr->bEndpointAddress;
++01324         ep = get_cfi_ep_by_addr(pcd->cfi, addr);
++01325         if (NULL == ep) {
++01326                 CFI_INFO("%s: Unable to get the endpoint addr=0x%02x\n",
++01327                          __func__, addr);
++01328                 return -DWC_E_INVALID;
++01329         }
++01330 
++01331         mps = UGETW(ep->ep->desc->wMaxPacketSize);
++01332 
++01333 #if 0
++01334         for (i = 0; i < desccount; i++) {
++01335                 CFI_INFO("%s: wTxSize[%d]=0x%04x\n", __func__, i, pVals[i]);
++01336         }
++01337         CFI_INFO("%s: epname=%s; mps=%d\n", __func__, ep->ep->ep.name, mps);
++01338 #endif
++01339 
++01340         /* Check the wTxSizes to be less than or equal to the mps */
++01341         for (i = 0; i < desccount; i++) {
++01342                 if (pVals[i] > mps) {
++01343                         CFI_INFO
++01344                             ("%s: ERROR - the wTxSize[%d] should be <= MPS (wTxSize=%d)\n",
++01345                              __func__, i, pVals[i]);
++01346                         return -DWC_E_INVALID;
++01347                 }
++01348         }
++01349 
++01350         ep->ep->dwc_ep.buff_mode = BM_CONCAT;
++01351         dwc_memcpy(ep->bm_concat, pConcatValHdr, BS_CONCAT_VAL_HDR_LEN);
++01352 
++01353         /* Free the previously allocated storage for the wTxBytes */
++01354         if (ep->bm_concat->wTxBytes) {
++01355                 DWC_FREE(ep->bm_concat->wTxBytes);
++01356         }
++01357 
++01358         /* Allocate a new storage for the wTxBytes field */
++01359         ep->bm_concat->wTxBytes =
++01360             DWC_ALLOC(sizeof(uint16_t) * pConcatValHdr->bDescCount);
++01361         if (NULL == ep->bm_concat->wTxBytes) {
++01362                 CFI_INFO("%s: Unable to allocate memory\n", __func__);
++01363                 return -DWC_E_NO_MEMORY;
++01364         }
++01365 
++01366         /* Copy the new values into the wTxBytes filed */
++01367         dwc_memcpy(ep->bm_concat->wTxBytes, buf + BS_CONCAT_VAL_HDR_LEN,
++01368                    sizeof(uint16_t) * pConcatValHdr->bDescCount);
++01369 
++01370         return 0;
++01371 }
++01372 
++01381 static uint16_t get_dfifo_size(dwc_otg_core_if_t * core_if)
++01382 {
++01383         dwc_otg_core_params_t *params = core_if->core_params;
++01384         uint16_t dfifo_total = 0;
++01385         int i;
++01386 
++01387         /* The shared RxFIFO size */
++01388         dfifo_total =
++01389             params->dev_rx_fifo_size + params->dev_nperio_tx_fifo_size;
++01390 
++01391         /* Add up each TxFIFO size to the total */
++01392         for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {
++01393                 dfifo_total += params->dev_tx_fifo_size[i];
++01394         }
++01395 
++01396         return dfifo_total;
++01397 }
++01398 
++01407 static int32_t get_rxfifo_size(dwc_otg_core_if_t * core_if, uint16_t wValue)
++01408 {
++01409         switch (wValue >> 8) {
++01410         case 0:
++01411                 return (core_if->pwron_rxfsiz <
++01412                         32768) ? core_if->pwron_rxfsiz : 32768;
++01413                 break;
++01414         case 1:
++01415                 return core_if->core_params->dev_rx_fifo_size;
++01416                 break;
++01417         default:
++01418                 return -DWC_E_INVALID;
++01419                 break;
++01420         }
++01421 }
++01422 
++01431 static int32_t get_txfifo_size(struct dwc_otg_pcd *pcd, uint16_t wValue)
++01432 {
++01433         dwc_otg_pcd_ep_t *ep;
++01434 
++01435         ep = get_ep_by_addr(pcd, wValue & 0xff);
++01436 
++01437         if (NULL == ep) {
++01438                 CFI_INFO("%s: Unable to get the endpoint addr=0x%02x\n",
++01439                          __func__, wValue & 0xff);
++01440                 return -DWC_E_INVALID;
++01441         }
++01442 
++01443         if (!ep->dwc_ep.is_in) {
++01444                 CFI_INFO
++01445                     ("%s: No Tx FIFO assingned to the Out endpoint addr=0x%02x\n",
++01446                      __func__, wValue & 0xff);
++01447                 return -DWC_E_INVALID;
++01448         }
++01449 
++01450         switch (wValue >> 8) {
++01451         case 0:
++01452                 return (GET_CORE_IF(pcd)->pwron_txfsiz
++01453                         [ep->dwc_ep.tx_fifo_num - 1] <
++01454                         768) ? GET_CORE_IF(pcd)->pwron_txfsiz[ep->
++01455                                                               dwc_ep.tx_fifo_num
++01456                                                               - 1] : 32768;
++01457                 break;
++01458         case 1:
++01459                 return GET_CORE_IF(pcd)->core_params->
++01460                     dev_tx_fifo_size[ep->dwc_ep.num - 1];
++01461                 break;
++01462         default:
++01463                 return -DWC_E_INVALID;
++01464                 break;
++01465         }
++01466 }
++01467 
++01477 static uint8_t check_fifo_sizes(dwc_otg_core_if_t * core_if)
++01478 {
++01479         uint16_t dfifo_actual = 0;
++01480         dwc_otg_core_params_t *params = core_if->core_params;
++01481         uint16_t start_addr = 0;
++01482         int i;
++01483 
++01484         dfifo_actual =
++01485             params->dev_rx_fifo_size + params->dev_nperio_tx_fifo_size;
++01486 
++01487         for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {
++01488                 dfifo_actual += params->dev_tx_fifo_size[i];
++01489         }
++01490 
++01491         if (dfifo_actual > core_if->total_fifo_size) {
++01492                 return 0;
++01493         }
++01494 
++01495         if (params->dev_rx_fifo_size > 32768 || params->dev_rx_fifo_size < 16)
++01496                 return 0;
++01497 
++01498         if (params->dev_nperio_tx_fifo_size > 32768
++01499             || params->dev_nperio_tx_fifo_size < 16)
++01500                 return 0;
++01501 
++01502         for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {
++01503 
++01504                 if (params->dev_tx_fifo_size[i] > 768
++01505                     || params->dev_tx_fifo_size[i] < 4)
++01506                         return 0;
++01507         }
++01508 
++01509         if (params->dev_rx_fifo_size > core_if->pwron_rxfsiz)
++01510                 return 0;
++01511         start_addr = params->dev_rx_fifo_size;
++01512 
++01513         if (params->dev_nperio_tx_fifo_size > core_if->pwron_gnptxfsiz)
++01514                 return 0;
++01515         start_addr += params->dev_nperio_tx_fifo_size;
++01516 
++01517         for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {
++01518 
++01519                 if (params->dev_tx_fifo_size[i] > core_if->pwron_txfsiz[i])
++01520                         return 0;
++01521                 start_addr += params->dev_tx_fifo_size[i];
++01522         }
++01523 
++01524         return 1;
++01525 }
++01526 
++01535 static uint8_t resize_fifos(dwc_otg_core_if_t * core_if)
++01536 {
++01537         int i = 0;
++01538         dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
++01539         dwc_otg_core_params_t *params = core_if->core_params;
++01540         uint32_t rx_fifo_size;
++01541         fifosize_data_t nptxfifosize;
++01542         fifosize_data_t txfifosize[15];
++01543 
++01544         uint32_t rx_fsz_bak;
++01545         uint32_t nptxfsz_bak;
++01546         uint32_t txfsz_bak[15];
++01547 
++01548         uint16_t start_address;
++01549         uint8_t retval = 1;
++01550 
++01551         if (!check_fifo_sizes(core_if)) {
++01552                 return 0;
++01553         }
++01554 
++01555         /* Configure data FIFO sizes */
++01556         if (core_if->hwcfg2.b.dynamic_fifo && params->enable_dynamic_fifo) {
++01557                 rx_fsz_bak = DWC_READ_REG32(&global_regs->grxfsiz);
++01558                 rx_fifo_size = params->dev_rx_fifo_size;
++01559                 DWC_WRITE_REG32(&global_regs->grxfsiz, rx_fifo_size);
++01560 
++01561                 /*
++01562                  * Tx FIFOs These FIFOs are numbered from 1 to 15.
++01563                  * Indexes of the FIFO size module parameters in the
++01564                  * dev_tx_fifo_size array and the FIFO size registers in
++01565                  * the dtxfsiz array run from 0 to 14.
++01566                  */
++01567 
++01568                 /* Non-periodic Tx FIFO */
++01569                 nptxfsz_bak = DWC_READ_REG32(&global_regs->gnptxfsiz);
++01570                 nptxfifosize.b.depth = params->dev_nperio_tx_fifo_size;
++01571                 start_address = params->dev_rx_fifo_size;
++01572                 nptxfifosize.b.startaddr = start_address;
++01573 
++01574                 DWC_WRITE_REG32(&global_regs->gnptxfsiz, nptxfifosize.d32);
++01575 
++01576                 start_address += nptxfifosize.b.depth;
++01577 
++01578                 for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {
++01579                         txfsz_bak[i] = DWC_READ_REG32(&global_regs->dtxfsiz[i]);
++01580 
++01581                         txfifosize[i].b.depth = params->dev_tx_fifo_size[i];
++01582                         txfifosize[i].b.startaddr = start_address;
++01583                         DWC_WRITE_REG32(&global_regs->dtxfsiz[i],
++01584                                         txfifosize[i].d32);
++01585 
++01586                         start_address += txfifosize[i].b.depth;
++01587                 }
++01588 
++01590                 if (rx_fifo_size != DWC_READ_REG32(&global_regs->grxfsiz)) {
++01591                         retval = 0;
++01592                 }
++01593 
++01594                 if (nptxfifosize.d32 != DWC_READ_REG32(&global_regs->gnptxfsiz)) {
++01595                         retval = 0;
++01596                 }
++01597 
++01598                 for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {
++01599                         if (txfifosize[i].d32 !=
++01600                             DWC_READ_REG32(&global_regs->dtxfsiz[i])) {
++01601                                 retval = 0;
++01602                         }
++01603                 }
++01604 
++01606                 if (retval == 0) {
++01607                         DWC_WRITE_REG32(&global_regs->grxfsiz, rx_fsz_bak);
++01608 
++01609                         /* Non-periodic Tx FIFO */
++01610                         DWC_WRITE_REG32(&global_regs->gnptxfsiz, nptxfsz_bak);
++01611 
++01612                         for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {
++01613                                 DWC_WRITE_REG32(&global_regs->dtxfsiz[i],
++01614                                                 txfsz_bak[i]);
++01615                         }
++01616                 }
++01617         } else {
++01618                 return 0;
++01619         }
++01620 
++01621         /* Flush the FIFOs */
++01622         dwc_otg_flush_tx_fifo(core_if, 0x10);   /* all Tx FIFOs */
++01623         dwc_otg_flush_rx_fifo(core_if);
++01624 
++01625         return retval;
++01626 }
++01627 
++01631 static int cfi_ep_set_tx_fifo_val(uint8_t * buf, dwc_otg_pcd_t * pcd)
++01632 {
++01633         int retval;
++01634         uint32_t fsiz;
++01635         uint16_t size;
++01636         uint16_t ep_addr;
++01637         dwc_otg_pcd_ep_t *ep;
++01638         dwc_otg_core_params_t *params = GET_CORE_IF(pcd)->core_params;
++01639         tx_fifo_size_setup_t *ptxfifoval;
++01640 
++01641         ptxfifoval = (tx_fifo_size_setup_t *) buf;
++01642         ep_addr = ptxfifoval->bEndpointAddress;
++01643         size = ptxfifoval->wDepth;
++01644 
++01645         ep = get_ep_by_addr(pcd, ep_addr);
++01646 
++01647         CFI_INFO
++01648             ("%s: Set Tx FIFO size: endpoint addr=0x%02x, depth=%d, FIFO Num=%d\n",
++01649              __func__, ep_addr, size, ep->dwc_ep.tx_fifo_num);
++01650 
++01651         if (NULL == ep) {
++01652                 CFI_INFO("%s: Unable to get the endpoint addr=0x%02x\n",
++01653                          __func__, ep_addr);
++01654                 return -DWC_E_INVALID;
++01655         }
++01656 
++01657         fsiz = params->dev_tx_fifo_size[ep->dwc_ep.tx_fifo_num - 1];
++01658         params->dev_tx_fifo_size[ep->dwc_ep.tx_fifo_num - 1] = size;
++01659 
++01660         if (resize_fifos(GET_CORE_IF(pcd))) {
++01661                 retval = 0;
++01662         } else {
++01663                 CFI_INFO
++01664                     ("%s: Error setting the feature Tx FIFO Size for EP%d\n",
++01665                      __func__, ep_addr);
++01666                 params->dev_tx_fifo_size[ep->dwc_ep.tx_fifo_num - 1] = fsiz;
++01667                 retval = -DWC_E_INVALID;
++01668         }
++01669 
++01670         return retval;
++01671 }
++01672 
++01676 static int cfi_set_rx_fifo_val(uint8_t * buf, dwc_otg_pcd_t * pcd)
++01677 {
++01678         int retval;
++01679         uint32_t fsiz;
++01680         uint16_t size;
++01681         dwc_otg_core_params_t *params = GET_CORE_IF(pcd)->core_params;
++01682         rx_fifo_size_setup_t *prxfifoval;
++01683 
++01684         prxfifoval = (rx_fifo_size_setup_t *) buf;
++01685         size = prxfifoval->wDepth;
++01686 
++01687         fsiz = params->dev_rx_fifo_size;
++01688         params->dev_rx_fifo_size = size;
++01689 
++01690         if (resize_fifos(GET_CORE_IF(pcd))) {
++01691                 retval = 0;
++01692         } else {
++01693                 CFI_INFO("%s: Error setting the feature Rx FIFO Size\n",
++01694                          __func__);
++01695                 params->dev_rx_fifo_size = fsiz;
++01696                 retval = -DWC_E_INVALID;
++01697         }
++01698 
++01699         return retval;
++01700 }
++01701 
++01705 static int cfi_ep_get_sg_val(uint8_t * buf, struct dwc_otg_pcd *pcd,
++01706                              struct cfi_usb_ctrlrequest *req)
++01707 {
++01708         int retval = -DWC_E_INVALID;
++01709         uint8_t addr;
++01710         cfi_ep_t *ep;
++01711 
++01712         /* The Low Byte of the wValue contains a non-zero address of the endpoint */
++01713         addr = req->wValue & 0xFF;
++01714         if (addr == 0)          /* The address should be non-zero */
++01715                 return retval;
++01716 
++01717         ep = get_cfi_ep_by_addr(pcd->cfi, addr);
++01718         if (NULL == ep) {
++01719                 CFI_INFO("%s: Unable to get the endpoint address(0x%02x)\n",
++01720                          __func__, addr);
++01721                 return retval;
++01722         }
++01723 
++01724         dwc_memcpy(buf, ep->bm_sg, BS_SG_VAL_DESC_LEN);
++01725         retval = BS_SG_VAL_DESC_LEN;
++01726         return retval;
++01727 }
++01728 
++01733 static int cfi_ep_get_concat_val(uint8_t * buf, struct dwc_otg_pcd *pcd,
++01734                                  struct cfi_usb_ctrlrequest *req)
++01735 {
++01736         int retval = -DWC_E_INVALID;
++01737         uint8_t addr;
++01738         cfi_ep_t *ep;
++01739         uint8_t desc_count;
++01740 
++01741         /* The Low Byte of the wValue contains a non-zero address of the endpoint */
++01742         addr = req->wValue & 0xFF;
++01743         if (addr == 0)          /* The address should be non-zero */
++01744                 return retval;
++01745 
++01746         ep = get_cfi_ep_by_addr(pcd->cfi, addr);
++01747         if (NULL == ep) {
++01748                 CFI_INFO("%s: Unable to get the endpoint address(0x%02x)\n",
++01749                          __func__, addr);
++01750                 return retval;
++01751         }
++01752 
++01753         /* Copy the header to the buffer */
++01754         dwc_memcpy(buf, ep->bm_concat, BS_CONCAT_VAL_HDR_LEN);
++01755         /* Advance the buffer pointer by the header size */
++01756         buf += BS_CONCAT_VAL_HDR_LEN;
++01757 
++01758         desc_count = ep->bm_concat->hdr.bDescCount;
++01759         /* Copy alll the wTxBytes to the buffer */
++01760         dwc_memcpy(buf, ep->bm_concat->wTxBytes, sizeof(uid16_t) * desc_count);
++01761 
++01762         retval = BS_CONCAT_VAL_HDR_LEN + sizeof(uid16_t) * desc_count;
++01763         return retval;
++01764 }
++01765 
++01772 static int cfi_ep_get_align_val(uint8_t * buf, struct dwc_otg_pcd *pcd,
++01773                                 struct cfi_usb_ctrlrequest *req)
++01774 {
++01775         int retval = -DWC_E_INVALID;
++01776         uint8_t addr;
++01777         cfi_ep_t *ep;
++01778 
++01779         /* The Low Byte of the wValue contains a non-zero address of the endpoint */
++01780         addr = req->wValue & 0xFF;
++01781         if (addr == 0)          /* The address should be non-zero */
++01782                 return retval;
++01783 
++01784         ep = get_cfi_ep_by_addr(pcd->cfi, addr);
++01785         if (NULL == ep) {
++01786                 CFI_INFO("%s: Unable to get the endpoint address(0x%02x)\n",
++01787                          __func__, addr);
++01788                 return retval;
++01789         }
++01790 
++01791         dwc_memcpy(buf, ep->bm_align, BS_ALIGN_VAL_HDR_LEN);
++01792         retval = BS_ALIGN_VAL_HDR_LEN;
++01793 
++01794         return retval;
++01795 }
++01796 
++01804 static int cfi_set_feature_value(struct dwc_otg_pcd *pcd)
++01805 {
++01806         int retval = -DWC_E_NOT_SUPPORTED;
++01807         uint16_t wIndex, wValue;
++01808         uint8_t bRequest;
++01809         struct dwc_otg_core_if *coreif;
++01810         cfiobject_t *cfi = pcd->cfi;
++01811         struct cfi_usb_ctrlrequest *ctrl_req;
++01812         uint8_t *buf;
++01813         ctrl_req = &cfi->ctrl_req;
++01814 
++01815         buf = pcd->cfi->ctrl_req.data;
++01816 
++01817         coreif = GET_CORE_IF(pcd);
++01818         bRequest = ctrl_req->bRequest;
++01819         wIndex = DWC_CONSTANT_CPU_TO_LE16(ctrl_req->wIndex);
++01820         wValue = DWC_CONSTANT_CPU_TO_LE16(ctrl_req->wValue);
++01821 
++01822         /* See which feature is to be modified */
++01823         switch (wIndex) {
++01824         case FT_ID_DMA_BUFFER_SETUP:
++01825                 /* Modify the feature */
++01826                 if ((retval = cfi_ep_set_sg_val(buf, pcd)) < 0)
++01827                         return retval;
++01828 
++01829                 /* And send this request to the gadget */
++01830                 cfi->need_gadget_att = 1;
++01831                 break;
++01832 
++01833         case FT_ID_DMA_BUFF_ALIGN:
++01834                 if ((retval = cfi_ep_set_alignment_val(buf, pcd)) < 0)
++01835                         return retval;
++01836                 cfi->need_gadget_att = 1;
++01837                 break;
++01838 
++01839         case FT_ID_DMA_CONCAT_SETUP:
++01840                 /* Modify the feature */
++01841                 if ((retval = cfi_ep_set_concat_val(buf, pcd)) < 0)
++01842                         return retval;
++01843                 cfi->need_gadget_att = 1;
++01844                 break;
++01845 
++01846         case FT_ID_DMA_CIRCULAR:
++01847                 CFI_INFO("FT_ID_DMA_CIRCULAR\n");
++01848                 break;
++01849 
++01850         case FT_ID_THRESHOLD_SETUP:
++01851                 CFI_INFO("FT_ID_THRESHOLD_SETUP\n");
++01852                 break;
++01853 
++01854         case FT_ID_DFIFO_DEPTH:
++01855                 CFI_INFO("FT_ID_DFIFO_DEPTH\n");
++01856                 break;
++01857 
++01858         case FT_ID_TX_FIFO_DEPTH:
++01859                 CFI_INFO("FT_ID_TX_FIFO_DEPTH\n");
++01860                 if ((retval = cfi_ep_set_tx_fifo_val(buf, pcd)) < 0)
++01861                         return retval;
++01862                 cfi->need_gadget_att = 0;
++01863                 break;
++01864 
++01865         case FT_ID_RX_FIFO_DEPTH:
++01866                 CFI_INFO("FT_ID_RX_FIFO_DEPTH\n");
++01867                 if ((retval = cfi_set_rx_fifo_val(buf, pcd)) < 0)
++01868                         return retval;
++01869                 cfi->need_gadget_att = 0;
++01870                 break;
++01871         }
++01872 
++01873         return retval;
++01874 }
++01875 
++01876 #endif //DWC_UTE_CFI
++
Generated on Thu Oct 27 03:56:37 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
++doxygen 1.3.9.1
+ + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__cfi_8c.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/dwc__otg__cfi_8c.html 2013-07-26 19:31:20.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__cfi_8c.html 2013-07-26 19:34:39.000000000 +0000 +@@ -2,22 +2,10 @@ + + DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_cfi.c File Reference + +- + +- +-
+-
+-
+-
+-

dwc_otg_cfi.c File Reference

This file contains the most of the CFI implementation for the OTG. More... ++ ++
Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
++

dwc_otg_cfi.c File Reference

This file contains the most of the CFI(Core Feature Interface) implementation for the OTG. More... +

+ +

+@@ -25,12 +13,12 @@ +

+

Detailed Description

+-This file contains the most of the CFI implementation for the OTG. ++This file contains the most of the CFI(Core Feature Interface) implementation for the OTG. +

+ +

+-Definition in file dwc_otg_cfi.c.

Generated on Tue May 5 02:22:48 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++Definition in file dwc_otg_cfi.c.
Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
++doxygen 1.3.9.1
+ + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__cfi_8h-source.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/dwc__otg__cfi_8h-source.html 2013-07-26 19:31:20.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__cfi_8h-source.html 2013-07-26 19:34:39.000000000 +0000 +@@ -2,298 +2,286 @@ + + DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_cfi.h Source File + +- + +- +-
+-
+-
+-
+-

dwc_otg_cfi.h

Go to the documentation of this file.
00001 /* ==========================================================================
+-00002  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
+-00003  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
+-00004  * otherwise expressly agreed to in writing between Synopsys and you.
+-00005  * 
+-00006  * The Software IS NOT an item of Licensed Software or Licensed Product under
+-00007  * any End User Software License Agreement or Agreement for Licensed Product
+-00008  * with Synopsys or any supplement thereto. You are permitted to use and
+-00009  * redistribute this Software in source and binary forms, with or without
+-00010  * modification, provided that redistributions of source code must retain this
+-00011  * notice. You may not view, use, disclose, copy or distribute this file or
+-00012  * any information contained herein except pursuant to this license grant from
+-00013  * Synopsys. If you do not agree with this notice, including the disclaimer
+-00014  * below, then you are not authorized to use the Software.
+-00015  * 
+-00016  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
+-00017  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+-00018  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+-00019  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
+-00020  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+-00021  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+-00022  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+-00023  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+-00024  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+-00025  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+-00026  * DAMAGE.
+-00027  * ========================================================================== */
+-00028 
+-00029 #if !defined(__DWC_OTG_CFI_H__)
+-00030 #define __DWC_OTG_CFI_H__
+-00031 
+-00032 #include "dwc_otg_pcd.h"
+-00033 #include "dwc_cfi_common.h"
+-00034 
+-00043 struct dwc_otg_pcd;
+-00044 struct dwc_otg_pcd_ep;
+-00045 
+-00048 #define FT_ID_DMA_MODE                                  0x0001
+-00049 #define FT_ID_DMA_BUFFER_SETUP                  0x0002
+-00050 #define FT_ID_DMA_BUFF_ALIGN                    0x0003
+-00051 #define FT_ID_DMA_CONCAT_SETUP                  0x0004
+-00052 #define FT_ID_DMA_CIRCULAR                              0x0005
+-00053 #define FT_ID_THRESHOLD_SETUP                   0x0006
+-00054 #define FT_ID_DFIFO_DEPTH                               0x0007
+-00055 #define FT_ID_TX_FIFO_DEPTH                             0x0008
+-00056 #define FT_ID_RX_FIFO_DEPTH                             0x0009
+-00057 
+-00058 /**********************************************************/
+-00059 #define CFI_INFO_DEF
+-00060 
+-00061 #ifdef CFI_INFO_DEF
+-00062 #define CFI_INFO(fmt...)        DWC_PRINTF("CFI: " fmt);
+-00063 #else
+-00064 #define CFI_INFO(fmt...)
+-00065 #endif
+-00066 
+-00067 #define min(x,y) ({ \
+-00068         x < y ? x : y; })
+-00069 
+-00070 #define max(x,y) ({ \
+-00071         x > y ? x : y; })
+-00072 
+-00077 struct _ddma_sg_buffer_setup {
+-00078 #define BS_SG_VAL_DESC_LEN      6
+-00079         /* The OUT EP address */
+-00080         uint8_t bOutEndpointAddress;
+-00081         /* The IN EP address */
+-00082         uint8_t bInEndpointAddress;
+-00083         /* Number of bytes to put between transfer segments (must be DWORD boundaries) */
+-00084         uint8_t bOffset;
+-00085         /* The number of transfer segments (a DMA descriptors per each segment) */
+-00086         uint8_t bCount;
+-00087         /* Size (in byte) of each transfer segment */
+-00088         uint16_t wSize;
+-00089 } __attribute__ ((packed));
+-00090 typedef struct _ddma_sg_buffer_setup ddma_sg_buffer_setup_t;
+-00091 
+-00093 struct _ddma_concat_buffer_setup_hdr {
+-00094 #define BS_CONCAT_VAL_HDR_LEN   4
+-00095         /* The endpoint for which the buffer is to be set up */
+-00096         uint8_t bEndpointAddress;
+-00097         /* The count of descriptors to be used */
+-00098         uint8_t bDescCount;
+-00099         /* The total size of the transfer */
+-00100         uint16_t wSize;
+-00101 } __attribute__ ((packed));
+-00102 typedef struct _ddma_concat_buffer_setup_hdr ddma_concat_buffer_setup_hdr_t;
+-00103 
+-00105 struct _ddma_concat_buffer_setup {
+-00106         /* The SG header */
+-00107         ddma_concat_buffer_setup_hdr_t hdr;
+-00108 
+-00109         /* The XFER sizes pointer (allocated dynamically) */
+-00110         uint16_t *wTxBytes;
+-00111 } __attribute__ ((packed));
+-00112 typedef struct _ddma_concat_buffer_setup ddma_concat_buffer_setup_t;
+-00113 
+-00115 struct _ddma_align_buffer_setup {
+-00116 #define BS_ALIGN_VAL_HDR_LEN    2
+-00117         uint8_t bEndpointAddress;
+-00118         uint8_t bAlign;
+-00119 } __attribute__ ((packed));
+-00120 typedef struct _ddma_align_buffer_setup ddma_align_buffer_setup_t;
+-00121 
+-00123 struct _tx_fifo_size_setup {
+-00124         uint8_t bEndpointAddress;
+-00125         uint16_t wDepth;
+-00126 } __attribute__ ((packed));
+-00127 typedef struct _tx_fifo_size_setup tx_fifo_size_setup_t;
+-00128 
+-00130 struct _rx_fifo_size_setup {
+-00131         uint16_t wDepth;
+-00132 } __attribute__ ((packed));
+-00133 typedef struct _rx_fifo_size_setup rx_fifo_size_setup_t;
+-00134 
+-00140 struct cfi_usb_ctrlrequest {
+-00141         uint8_t bRequestType;
+-00142         uint8_t bRequest;
+-00143         uint16_t wValue;
+-00144         uint16_t wIndex;
+-00145         uint16_t wLength;
+-00146         uint8_t *data;
+-00147 } UPACKED;
+-00148 
+-00149 /*---------------------------------------------------------------------------*/
+-00150 
+-00156 struct cfi_ep {
+-00157         /* Entry for the list container */
+-00158         dwc_list_link_t lh;
+-00159         /* Pointer to the active PCD endpoint structure */
+-00160         struct dwc_otg_pcd_ep *ep;
+-00161         /* The last descriptor in the chain of DMA descriptors of the endpoint */
+-00162         struct dwc_otg_dma_desc *dma_desc_last;
+-00163         /* The SG feature value */
+-00164         ddma_sg_buffer_setup_t *bm_sg;
+-00165         /* The Circular feature value */
+-00166         ddma_sg_buffer_setup_t *bm_circ;
+-00167         /* The Concatenation feature value */
+-00168         ddma_concat_buffer_setup_t *bm_concat;
+-00169         /* The Alignment feature value */
+-00170         ddma_align_buffer_setup_t *bm_align;
+-00171         /* XFER length */
+-00172         uint32_t xfer_len;
+-00173         /* 
+-00174          * Count of DMA descriptors currently used.
+-00175          * The total should not exceed the MAX_DMA_DESCS_PER_EP value
+-00176          * defined in the dwc_otg_cil.h
+-00177          */
+-00178         uint32_t desc_count;
+-00179 };
+-00180 typedef struct cfi_ep cfi_ep_t;
+-00181 
+-00182 typedef struct cfi_dma_buff {
+-00183 #define CFI_IN_BUF_LEN  1024
+-00184 #define CFI_OUT_BUF_LEN 1024
+-00185         dma_addr_t addr;
+-00186         uint8_t *buf;
+-00187 } cfi_dma_buff_t;
+-00188 
+-00189 struct cfiobject;
+-00190 
+-00199 typedef struct cfi_ops {
+-00200         int (*ep_enable) (struct cfiobject * cfi, struct dwc_otg_pcd * pcd,
+-00201                           struct dwc_otg_pcd_ep * ep);
+-00202         void *(*ep_alloc_buf) (struct cfiobject * cfi, struct dwc_otg_pcd * pcd,
+-00203                                struct dwc_otg_pcd_ep * ep, dma_addr_t * dma,
+-00204                                unsigned size, gfp_t flags);
+-00205         void (*release) (struct cfiobject * cfi);
+-00206         int (*ctrl_write_complete) (struct cfiobject * cfi,
+-00207                                     struct dwc_otg_pcd * pcd);
+-00208         void (*build_descriptors) (struct cfiobject * cfi,
+-00209                                    struct dwc_otg_pcd * pcd,
+-00210                                    struct dwc_otg_pcd_ep * ep,
+-00211                                    dwc_otg_pcd_request_t * req);
+-00212 } cfi_ops_t;
+-00213 
+-00214 struct cfiobject {
+-00215         cfi_ops_t ops;
+-00216         struct dwc_otg_pcd *pcd;
+-00217         struct usb_gadget *gadget;
+-00218 
+-00219         /* Buffers used to send/receive CFI-related request data */
+-00220         cfi_dma_buff_t buf_in;
+-00221         cfi_dma_buff_t buf_out;
+-00222 
+-00223         /* CFI specific Control request wrapper */
+-00224         struct cfi_usb_ctrlrequest ctrl_req;
+-00225 
+-00226         /* The list of active EP's in the PCD of type cfi_ep_t */
+-00227         dwc_list_link_t active_eps;
+-00228 
+-00229         /* This flag shall control the propagation of a specific request
+-00230          * to the gadget's processing routines.
+-00231          * 0 - no gadget handling
+-00232          * 1 - the gadget needs to know about this request (w/o completing a status 
+-00233          * phase - just return a 0 to the _setup callback)
+-00234          */
+-00235         uint8_t need_gadget_att;
+-00236 
+-00237         /* Flag indicating whether the status IN phase needs to be 
+-00238          * completed by the PCD
+-00239          */
+-00240         uint8_t need_status_in_complete;
+-00241 };
+-00242 typedef struct cfiobject cfiobject_t;
+-00243 
+-00244 #define DUMP_MSG
+-00245 
+-00246 #if defined(DUMP_MSG)
+-00247 static inline void dump_msg(const u8 * buf, unsigned int length)
+-00248 {
+-00249         unsigned int start, num, i;
+-00250         char line[52], *p;
+-00251 
+-00252         if (length >= 512)
+-00253                 return;
+-00254 
+-00255         start = 0;
+-00256         while (length > 0) {
+-00257                 num = min(length, 16u);
+-00258                 p = line;
+-00259                 for (i = 0; i < num; ++i) {
+-00260                         if (i == 8)
+-00261                                 *p++ = ' ';
+-00262                         DWC_SPRINTF(p, " %02x", buf[i]);
+-00263                         p += 3;
+-00264                 }
+-00265                 *p = 0;
+-00266                 DWC_DEBUG("%6x: %s\n", start, line);
+-00267                 buf += num;
+-00268                 start += num;
+-00269                 length -= num;
+-00270         }
+-00271 }
+-00272 #else
+-00273 static inline void dump_msg(const u8 * buf, unsigned int length)
+-00274 {
+-00275 }
+-00276 #endif
+-00277 
+-00281 static inline struct cfi_ep *get_cfi_ep_by_addr(struct cfiobject *cfi,
+-00282                                                 uint8_t addr)
+-00283 {
+-00284         struct cfi_ep *pcfiep;
+-00285         dwc_list_link_t *tmp;
+-00286 
+-00287         DWC_LIST_FOREACH(tmp, &cfi->active_eps) {
+-00288                 pcfiep = DWC_LIST_ENTRY(tmp, struct cfi_ep, lh);
+-00289 
+-00290                 if (pcfiep->ep->desc->bEndpointAddress == addr) {
+-00291                         return pcfiep;
+-00292                 }
+-00293         }
+-00294 
+-00295         return NULL;
+-00296 }
+-00297 
+-00302 static inline struct cfi_ep *get_cfi_ep_by_pcd_ep(struct cfiobject *cfi,
+-00303                                                   struct dwc_otg_pcd_ep *ep)
+-00304 {
+-00305         struct cfi_ep *pcfiep = NULL;
+-00306         dwc_list_link_t *tmp;
+-00307 
+-00308         DWC_LIST_FOREACH(tmp, &cfi->active_eps) {
+-00309                 pcfiep = DWC_LIST_ENTRY(tmp, struct cfi_ep, lh);
+-00310                 if (pcfiep->ep == ep) {
+-00311                         return pcfiep;
+-00312                 }
+-00313         }
+-00314         return NULL;
+-00315 }
+-00316 
+-00317 int cfi_setup(struct dwc_otg_pcd *pcd, struct cfi_usb_ctrlrequest *ctrl);
+-00318 
+-00319 #endif                          /* (__DWC_OTG_CFI_H__) */
+-
Generated on Tue May 5 02:22:48 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++
Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
++

dwc_otg_cfi.h

Go to the documentation of this file.
00001 /* ==========================================================================
++00002  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
++00003  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
++00004  * otherwise expressly agreed to in writing between Synopsys and you.
++00005  *
++00006  * The Software IS NOT an item of Licensed Software or Licensed Product under
++00007  * any End User Software License Agreement or Agreement for Licensed Product
++00008  * with Synopsys or any supplement thereto. You are permitted to use and
++00009  * redistribute this Software in source and binary forms, with or without
++00010  * modification, provided that redistributions of source code must retain this
++00011  * notice. You may not view, use, disclose, copy or distribute this file or
++00012  * any information contained herein except pursuant to this license grant from
++00013  * Synopsys. If you do not agree with this notice, including the disclaimer
++00014  * below, then you are not authorized to use the Software.
++00015  *
++00016  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
++00017  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++00018  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++00019  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
++00020  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++00021  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
++00022  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
++00023  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
++00024  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
++00025  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
++00026  * DAMAGE.
++00027  * ========================================================================== */
++00028 
++00029 #if !defined(__DWC_OTG_CFI_H__)
++00030 #define __DWC_OTG_CFI_H__
++00031 
++00032 #include "dwc_otg_pcd.h"
++00033 #include "dwc_cfi_common.h"
++00034 
++00044 struct dwc_otg_pcd;
++00045 struct dwc_otg_pcd_ep;
++00046 
++00049 #define FT_ID_DMA_MODE                                  0x0001
++00050 #define FT_ID_DMA_BUFFER_SETUP                  0x0002
++00051 #define FT_ID_DMA_BUFF_ALIGN                    0x0003
++00052 #define FT_ID_DMA_CONCAT_SETUP                  0x0004
++00053 #define FT_ID_DMA_CIRCULAR                              0x0005
++00054 #define FT_ID_THRESHOLD_SETUP                   0x0006
++00055 #define FT_ID_DFIFO_DEPTH                               0x0007
++00056 #define FT_ID_TX_FIFO_DEPTH                             0x0008
++00057 #define FT_ID_RX_FIFO_DEPTH                             0x0009
++00058 
++00059 /**********************************************************/
++00060 #define CFI_INFO_DEF
++00061 
++00062 #ifdef CFI_INFO_DEF
++00063 #define CFI_INFO(fmt...)        DWC_PRINTF("CFI: " fmt);
++00064 #else
++00065 #define CFI_INFO(fmt...)
++00066 #endif
++00067 
++00068 #define min(x,y) ({ \
++00069         x < y ? x : y; })
++00070 
++00071 #define max(x,y) ({ \
++00072         x > y ? x : y; })
++00073 
++00078 struct _ddma_sg_buffer_setup {
++00079 #define BS_SG_VAL_DESC_LEN      6
++00080         /* The OUT EP address */
++00081         uint8_t bOutEndpointAddress;
++00082         /* The IN EP address */
++00083         uint8_t bInEndpointAddress;
++00084         /* Number of bytes to put between transfer segments (must be DWORD boundaries) */
++00085         uint8_t bOffset;
++00086         /* The number of transfer segments (a DMA descriptors per each segment) */
++00087         uint8_t bCount;
++00088         /* Size (in byte) of each transfer segment */
++00089         uint16_t wSize;
++00090 } __attribute__ ((packed));
++00091 typedef struct _ddma_sg_buffer_setup ddma_sg_buffer_setup_t;
++00092 
++00094 struct _ddma_concat_buffer_setup_hdr {
++00095 #define BS_CONCAT_VAL_HDR_LEN   4
++00096         /* The endpoint for which the buffer is to be set up */
++00097         uint8_t bEndpointAddress;
++00098         /* The count of descriptors to be used */
++00099         uint8_t bDescCount;
++00100         /* The total size of the transfer */
++00101         uint16_t wSize;
++00102 } __attribute__ ((packed));
++00103 typedef struct _ddma_concat_buffer_setup_hdr ddma_concat_buffer_setup_hdr_t;
++00104 
++00106 struct _ddma_concat_buffer_setup {
++00107         /* The SG header */
++00108         ddma_concat_buffer_setup_hdr_t hdr;
++00109 
++00110         /* The XFER sizes pointer (allocated dynamically) */
++00111         uint16_t *wTxBytes;
++00112 } __attribute__ ((packed));
++00113 typedef struct _ddma_concat_buffer_setup ddma_concat_buffer_setup_t;
++00114 
++00116 struct _ddma_align_buffer_setup {
++00117 #define BS_ALIGN_VAL_HDR_LEN    2
++00118         uint8_t bEndpointAddress;
++00119         uint8_t bAlign;
++00120 } __attribute__ ((packed));
++00121 typedef struct _ddma_align_buffer_setup ddma_align_buffer_setup_t;
++00122 
++00124 struct _tx_fifo_size_setup {
++00125         uint8_t bEndpointAddress;
++00126         uint16_t wDepth;
++00127 } __attribute__ ((packed));
++00128 typedef struct _tx_fifo_size_setup tx_fifo_size_setup_t;
++00129 
++00131 struct _rx_fifo_size_setup {
++00132         uint16_t wDepth;
++00133 } __attribute__ ((packed));
++00134 typedef struct _rx_fifo_size_setup rx_fifo_size_setup_t;
++00135 
++00141 struct cfi_usb_ctrlrequest {
++00142         uint8_t bRequestType;
++00143         uint8_t bRequest;
++00144         uint16_t wValue;
++00145         uint16_t wIndex;
++00146         uint16_t wLength;
++00147         uint8_t *data;
++00148 } UPACKED;
++00149 
++00150 /*---------------------------------------------------------------------------*/
++00151 
++00157 struct cfi_ep {
++00158         /* Entry for the list container */
++00159         dwc_list_link_t lh;
++00160         /* Pointer to the active PCD endpoint structure */
++00161         struct dwc_otg_pcd_ep *ep;
++00162         /* The last descriptor in the chain of DMA descriptors of the endpoint */
++00163         struct dwc_otg_dma_desc *dma_desc_last;
++00164         /* The SG feature value */
++00165         ddma_sg_buffer_setup_t *bm_sg;
++00166         /* The Circular feature value */
++00167         ddma_sg_buffer_setup_t *bm_circ;
++00168         /* The Concatenation feature value */
++00169         ddma_concat_buffer_setup_t *bm_concat;
++00170         /* The Alignment feature value */
++00171         ddma_align_buffer_setup_t *bm_align;
++00172         /* XFER length */
++00173         uint32_t xfer_len;
++00174         /*
++00175          * Count of DMA descriptors currently used.
++00176          * The total should not exceed the MAX_DMA_DESCS_PER_EP value
++00177          * defined in the dwc_otg_cil.h
++00178          */
++00179         uint32_t desc_count;
++00180 };
++00181 typedef struct cfi_ep cfi_ep_t;
++00182 
++00183 typedef struct cfi_dma_buff {
++00184 #define CFI_IN_BUF_LEN  1024
++00185 #define CFI_OUT_BUF_LEN 1024
++00186         dma_addr_t addr;
++00187         uint8_t *buf;
++00188 } cfi_dma_buff_t;
++00189 
++00190 struct cfiobject;
++00191 
++00200 typedef struct cfi_ops {
++00201         int (*ep_enable) (struct cfiobject * cfi, struct dwc_otg_pcd * pcd,
++00202                           struct dwc_otg_pcd_ep * ep);
++00203         void *(*ep_alloc_buf) (struct cfiobject * cfi, struct dwc_otg_pcd * pcd,
++00204                                struct dwc_otg_pcd_ep * ep, dma_addr_t * dma,
++00205                                unsigned size, gfp_t flags);
++00206         void (*release) (struct cfiobject * cfi);
++00207         int (*ctrl_write_complete) (struct cfiobject * cfi,
++00208                                     struct dwc_otg_pcd * pcd);
++00209         void (*build_descriptors) (struct cfiobject * cfi,
++00210                                    struct dwc_otg_pcd * pcd,
++00211                                    struct dwc_otg_pcd_ep * ep,
++00212                                    dwc_otg_pcd_request_t * req);
++00213 } cfi_ops_t;
++00214 
++00215 struct cfiobject {
++00216         cfi_ops_t ops;
++00217         struct dwc_otg_pcd *pcd;
++00218         struct usb_gadget *gadget;
++00219 
++00220         /* Buffers used to send/receive CFI-related request data */
++00221         cfi_dma_buff_t buf_in;
++00222         cfi_dma_buff_t buf_out;
++00223 
++00224         /* CFI specific Control request wrapper */
++00225         struct cfi_usb_ctrlrequest ctrl_req;
++00226 
++00227         /* The list of active EP's in the PCD of type cfi_ep_t */
++00228         dwc_list_link_t active_eps;
++00229 
++00230         /* This flag shall control the propagation of a specific request
++00231          * to the gadget's processing routines.
++00232          * 0 - no gadget handling
++00233          * 1 - the gadget needs to know about this request (w/o completing a status
++00234          * phase - just return a 0 to the _setup callback)
++00235          */
++00236         uint8_t need_gadget_att;
++00237 
++00238         /* Flag indicating whether the status IN phase needs to be
++00239          * completed by the PCD
++00240          */
++00241         uint8_t need_status_in_complete;
++00242 };
++00243 typedef struct cfiobject cfiobject_t;
++00244 
++00245 #define DUMP_MSG
++00246 
++00247 #if defined(DUMP_MSG)
++00248 static inline void dump_msg(const u8 * buf, unsigned int length)
++00249 {
++00250         unsigned int start, num, i;
++00251         char line[52], *p;
++00252 
++00253         if (length >= 512)
++00254                 return;
++00255 
++00256         start = 0;
++00257         while (length > 0) {
++00258                 num = min(length, 16u);
++00259                 p = line;
++00260                 for (i = 0; i < num; ++i) {
++00261                         if (i == 8)
++00262                                 *p++ = ' ';
++00263                         DWC_SPRINTF(p, " %02x", buf[i]);
++00264                         p += 3;
++00265                 }
++00266                 *p = 0;
++00267                 DWC_DEBUG("%6x: %s\n", start, line);
++00268                 buf += num;
++00269                 start += num;
++00270                 length -= num;
++00271         }
++00272 }
++00273 #else
++00274 static inline void dump_msg(const u8 * buf, unsigned int length)
++00275 {
++00276 }
++00277 #endif
++00278 
++00282 static inline struct cfi_ep *get_cfi_ep_by_addr(struct cfiobject *cfi,
++00283                                                 uint8_t addr)
++00284 {
++00285         struct cfi_ep *pcfiep;
++00286         dwc_list_link_t *tmp;
++00287 
++00288         DWC_LIST_FOREACH(tmp, &cfi->active_eps) {
++00289                 pcfiep = DWC_LIST_ENTRY(tmp, struct cfi_ep, lh);
++00290 
++00291                 if (pcfiep->ep->desc->bEndpointAddress == addr) {
++00292                         return pcfiep;
++00293                 }
++00294         }
++00295 
++00296         return NULL;
++00297 }
++00298 
++00303 static inline struct cfi_ep *get_cfi_ep_by_pcd_ep(struct cfiobject *cfi,
++00304                                                   struct dwc_otg_pcd_ep *ep)
++00305 {
++00306         struct cfi_ep *pcfiep = NULL;
++00307         dwc_list_link_t *tmp;
++00308 
++00309         DWC_LIST_FOREACH(tmp, &cfi->active_eps) {
++00310                 pcfiep = DWC_LIST_ENTRY(tmp, struct cfi_ep, lh);
++00311                 if (pcfiep->ep == ep) {
++00312                         return pcfiep;
++00313                 }
++00314         }
++00315         return NULL;
++00316 }
++00317 
++00318 int cfi_setup(struct dwc_otg_pcd *pcd, struct cfi_usb_ctrlrequest *ctrl);
++00319 
++00320 #endif /* (__DWC_OTG_CFI_H__) */
++
Generated on Thu Oct 27 03:56:37 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
++doxygen 1.3.9.1
+ + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__cfi_8h.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/dwc__otg__cfi_8h.html 2013-07-26 19:31:20.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__cfi_8h.html 2013-07-26 19:34:39.000000000 +0000 +@@ -2,25 +2,13 @@ + + DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_cfi.h File Reference + +- + +- +-
+-
+-
+-
+-

dwc_otg_cfi.h File Reference

This file contains the CFI related OTG PCD specific common constants, interfaces (functions and macros) and data structures. More... ++ ++
Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
++

dwc_otg_cfi.h File Reference

This file contains the CFI related OTG PCD specific common constants, interfaces(functions and macros) and data structures.The CFI Protocol is an optional interface for internal testing purposes that a DUT may implement to support testing of configurable features. More... +

+-#include "dwc_otg_pcd.h"
+-#include "dwc_cfi_common.h"
++#include "dwc_otg_pcd.h"
++#include "dwc_cfi_common.h"
+ +

+ Go to the source code of this file. +@@ -46,223 +34,227 @@ + + + +- ++ + + + +- ++ + + + + +- ++ + + +- ++ + +- ++ + + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- +- ++ ++ + + +- ++ + +- ++ + + +- ++ + + +- + + +- ++ + +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- ++ ++ + + +
 Transmit FIFO Size setup structure. More...
struct  cfi_usb_ctrlrequest
 struct cfi_usb_ctrlrequest - the CFI implementation of the struct usb_ctrlrequest This structure encapsulates the standard usb_ctrlrequest and adds a pointer to the data returned in the data stage of a 3-stage Control Write requests. More...
 struct cfi_usb_ctrlrequest - the CFI implementation of the struct usb_ctrlrequest This structure encapsulates the standard usb_ctrlrequest and adds a pointer to the data returned in the data stage of a 3-stage Control Write requests. More...
struct  cfi_ep
 The CFI wrapper of the enabled and activated dwc_otg_pcd_ep structures. More...
struct  cfi_dma_buff
struct  cfi_dma_buff
struct  cfi_ops
 This is the interface for the CFI operations. More...
struct  cfiobject
struct  cfiobject

Defines

+-#define __DWC_OTG_CFI_H__
++#define __DWC_OTG_CFI_H__
+-#define FT_ID_DMA_MODE   0x0001
++#define FT_ID_DMA_MODE   0x0001
 This is a request for all Core Features.
+-#define FT_ID_DMA_BUFFER_SETUP   0x0002
++#define FT_ID_DMA_BUFFER_SETUP   0x0002
+-#define FT_ID_DMA_BUFF_ALIGN   0x0003
++#define FT_ID_DMA_BUFF_ALIGN   0x0003
+-#define FT_ID_DMA_CONCAT_SETUP   0x0004
++#define FT_ID_DMA_CONCAT_SETUP   0x0004
+-#define FT_ID_DMA_CIRCULAR   0x0005
++#define FT_ID_DMA_CIRCULAR   0x0005
+-#define FT_ID_THRESHOLD_SETUP   0x0006
++#define FT_ID_THRESHOLD_SETUP   0x0006
+-#define FT_ID_DFIFO_DEPTH   0x0007
++#define FT_ID_DFIFO_DEPTH   0x0007
+-#define FT_ID_TX_FIFO_DEPTH   0x0008
++#define FT_ID_TX_FIFO_DEPTH   0x0008
+-#define FT_ID_RX_FIFO_DEPTH   0x0009
++#define FT_ID_RX_FIFO_DEPTH   0x0009
+-#define CFI_INFO_DEF
++#define CFI_INFO_DEF
+-#define CFI_INFO(fmt...)   DWC_PRINTF("CFI: " fmt);
++#define CFI_INFO(fmt...)   DWC_PRINTF("CFI: " fmt);
#define min(x, y)
#define min(x, y)
#define max(x, y)
#define max(x, y)
+-#define BS_SG_VAL_DESC_LEN   6
++#define BS_SG_VAL_DESC_LEN   6
+-#define BS_CONCAT_VAL_HDR_LEN   4
++#define BS_CONCAT_VAL_HDR_LEN   4
+-#define BS_ALIGN_VAL_HDR_LEN   2
++#define BS_ALIGN_VAL_HDR_LEN   2
+-#define CFI_IN_BUF_LEN   1024
++#define CFI_IN_BUF_LEN   1024
+-#define CFI_OUT_BUF_LEN   1024
++#define CFI_OUT_BUF_LEN   1024
+-#define DUMP_MSG
++#define DUMP_MSG

Typedefs

+-typedef _ddma_sg_buffer_setup ddma_sg_buffer_setup_t
++typedef _ddma_sg_buffer_setup ddma_sg_buffer_setup_t
+-typedef _ddma_concat_buffer_setup_hdr ddma_concat_buffer_setup_hdr_t
++typedef _ddma_concat_buffer_setup_hdr ddma_concat_buffer_setup_hdr_t
+-typedef _ddma_concat_buffer_setup ddma_concat_buffer_setup_t
++typedef _ddma_concat_buffer_setup ddma_concat_buffer_setup_t
+-typedef _ddma_align_buffer_setup ddma_align_buffer_setup_t
++typedef _ddma_align_buffer_setup ddma_align_buffer_setup_t
+-typedef _tx_fifo_size_setup tx_fifo_size_setup_t
++typedef _tx_fifo_size_setup tx_fifo_size_setup_t
+-typedef _rx_fifo_size_setup rx_fifo_size_setup_t
++typedef _rx_fifo_size_setup rx_fifo_size_setup_t
+-typedef cfi_ep cfi_ep_t
++typedef cfi_ep cfi_ep_t
+-typedef cfi_dma_buff cfi_dma_buff_t
++typedef cfi_dma_buff cfi_dma_buff_t
typedef cfi_ops cfi_ops_t
typedef cfi_ops cfi_ops_t
 This is the interface for the CFI operations.
+-typedef cfiobject cfiobject_t
 This is the interface for the CFI operations.
++typedef cfiobject cfiobject_t

Functions

+-static void dump_msg (const u8 *buf, unsigned int length)
++void dump_msg (const u8 *buf, unsigned int length)
+-static struct cfi_ep * get_cfi_ep_by_addr (struct cfiobject *cfi, uint8_t addr)
++cfi_ep * get_cfi_ep_by_addr (struct cfiobject *cfi, uint8_t addr)
 This function returns a pointer to cfi_ep_t object with the addr address.
+-static struct cfi_ep * get_cfi_ep_by_pcd_ep (struct cfiobject *cfi, struct dwc_otg_pcd_ep *ep)
++cfi_ep * get_cfi_ep_by_pcd_ep (struct cfiobject *cfi, struct dwc_otg_pcd_ep *ep)
 This function returns a pointer to cfi_ep_t object that matches the dwc_otg_pcd_ep object.
++
+ int cfi_setup (struct dwc_otg_pcd *pcd, struct cfi_usb_ctrlrequest *ctrl)

Variables

_ddma_sg_buffer_setup packed
_ddma_sg_buffer_setup packed
 Descriptor DMA SG Buffer setup structure (SG buffer).
+-_ddma_concat_buffer_setup_hdr packed
 Descriptor DMA Concatenation Buffer setup structure.
+-_ddma_concat_buffer_setup packed
 Descriptor DMA Concatenation Buffer setup structure.
+-_ddma_align_buffer_setup packed
 Descriptor DMA Alignment Buffer setup structure.
+-_tx_fifo_size_setup packed
 Transmit FIFO Size setup structure.
+-_rx_fifo_size_setup packed
 Transmit FIFO Size setup structure.
+-cfi_usb_ctrlrequest UPACKED
 Descriptor DMA SG Buffer setup structure (SG buffer).
++cfi_usb_ctrlrequest UPACKED
 struct cfi_usb_ctrlrequest - the CFI implementation of the struct usb_ctrlrequest This structure encapsulates the standard usb_ctrlrequest and adds a pointer to the data returned in the data stage of a 3-stage Control Write requests.
+

Detailed Description

+-This file contains the CFI related OTG PCD specific common constants, interfaces (functions and macros) and data structures. ++This file contains the CFI related OTG PCD specific common constants, interfaces(functions and macros) and data structures.The CFI Protocol is an optional interface for internal testing purposes that a DUT may implement to support testing of configurable features. +

+ +

+ Definition in file dwc_otg_cfi.h.

Define Documentation

+- +-
+-
+- ++

++

++ ++ ++ ++
++ + +- +- +- +- +- +- +- +- +- ++ ++ ++ ++ ++ ++ ++ ++ ++ + +
#define min (x,
y   ) #define min ( x,
y   ) 
+- +-
++
++ ++ ++ ++ ++ ++
++   ++ + +

+ Value:

({ \
+         x < y ? x : y; })
+
+

+-Definition at line 67 of file dwc_otg_cfi.h. +- +-

+- +-

+-
+- ++Definition at line 68 of file dwc_otg_cfi.h. ++ ++
++

++ ++ ++ ++ ++
++ + +- +- +- +- +- +- +- +- +- ++ ++ ++ ++ ++ ++ ++ ++ ++ + +
#define max (x,
y   ) #define max ( x,
y   ) 
+- +-
++
++ ++ ++ ++ ++ ++
++   ++ + +

+ Value:

({ \
+         x > y ? x : y; })
+
+

+-Definition at line 70 of file dwc_otg_cfi.h. +- +-

++Definition at line 71 of file dwc_otg_cfi.h.

+

Typedef Documentation

+- +-
+-
+- ++

++

++ ++ ++ ++
++ + +- ++ + +
typedef struct cfi_ops cfi_ops_t typedef struct cfi_ops cfi_ops_t
+- +-
++
++ ++ ++ ++ +
++   ++ + +

+ This is the interface for the CFI operations. +@@ -274,29 +266,37 @@ +

ctrl_write_complete Called when the data stage of the request is complete
+ +- +-
+-

++

+

Variable Documentation

+- +-
+-
+- ++

++

++ ++ ++ ++
++ + +- ++ + +
struct _ddma_sg_buffer_setup packed struct _rx_fifo_size_setup packed
+- +-
++
++ ++ ++ ++ ++ ++
++   ++ + +

+ Descriptor DMA SG Buffer setup structure (SG buffer). +

+-This structure is also used for setting up a buffer for Circular DDMA. +- +-

+-

Generated on Tue May 5 02:22:48 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++This structure is also used for setting up a buffer for Circular DDMA.
++
Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
++doxygen 1.3.9.1 + + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__cil_8c-source.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/dwc__otg__cil_8c-source.html 2013-07-26 19:31:20.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__cil_8c-source.html 2013-07-26 19:34:40.000000000 +0000 +@@ -2,4921 +2,6559 @@ + + DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_cil.c Source File + +- + +- +-
+-
+-
+-
+-

dwc_otg_cil.c

Go to the documentation of this file.
00001 /* ==========================================================================
+-00002  * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_cil.c $
+-00003  * $Revision: #159 $
+-00004  * $Date: 2009/04/21 $
+-00005  * $Change: 1237465 $
+-00006  *
+-00007  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
+-00008  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
+-00009  * otherwise expressly agreed to in writing between Synopsys and you.
+-00010  * 
+-00011  * The Software IS NOT an item of Licensed Software or Licensed Product under
+-00012  * any End User Software License Agreement or Agreement for Licensed Product
+-00013  * with Synopsys or any supplement thereto. You are permitted to use and
+-00014  * redistribute this Software in source and binary forms, with or without
+-00015  * modification, provided that redistributions of source code must retain this
+-00016  * notice. You may not view, use, disclose, copy or distribute this file or
+-00017  * any information contained herein except pursuant to this license grant from
+-00018  * Synopsys. If you do not agree with this notice, including the disclaimer
+-00019  * below, then you are not authorized to use the Software.
+-00020  * 
+-00021  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
+-00022  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+-00023  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+-00024  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
+-00025  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+-00026  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+-00027  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+-00028  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+-00029  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+-00030  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+-00031  * DAMAGE.
+-00032  * ========================================================================== */
+-00033 
+-00060 #include "dwc_os.h"
+-00061 #include "dwc_otg_regs.h"
+-00062 #include "dwc_otg_cil.h"
+-00063 
+-00064 static int dwc_otg_setup_params(dwc_otg_core_if_t * core_if);
+-00065 
+-00078 dwc_otg_core_if_t *dwc_otg_cil_init(const uint32_t * reg_base_addr)
+-00079 {
+-00080         dwc_otg_core_if_t *core_if = 0;
+-00081         dwc_otg_dev_if_t *dev_if = 0;
+-00082         dwc_otg_host_if_t *host_if = 0;
+-00083         uint8_t *reg_base = (uint8_t *) reg_base_addr;
+-00084         int i = 0;
+-00085 
+-00086         DWC_DEBUGPL(DBG_CILV, "%s(%p)\n", __func__, reg_base_addr);
+-00087 
+-00088         core_if = dwc_alloc(sizeof(dwc_otg_core_if_t));
+-00089 
+-00090         if (core_if == 0) {
+-00091                 DWC_DEBUGPL(DBG_CIL,
+-00092                             "Allocation of dwc_otg_core_if_t failed\n");
+-00093                 return 0;
+-00094         }
+-00095         core_if->core_global_regs = (dwc_otg_core_global_regs_t *) reg_base;
+-00096 
+-00097         /*
+-00098          * Allocate the Device Mode structures.
+-00099          */
+-00100         dev_if = dwc_alloc(sizeof(dwc_otg_dev_if_t));
+-00101 
+-00102         if (dev_if == 0) {
+-00103                 DWC_DEBUGPL(DBG_CIL, "Allocation of dwc_otg_dev_if_t failed\n");
+-00104                 dwc_free(core_if);
+-00105                 return 0;
+-00106         }
+-00107 
+-00108         dev_if->dev_global_regs =
+-00109             (dwc_otg_device_global_regs_t *) (reg_base +
+-00110                                               DWC_DEV_GLOBAL_REG_OFFSET);
+-00111 
+-00112         for (i = 0; i < MAX_EPS_CHANNELS; i++) {
+-00113                 dev_if->in_ep_regs[i] = (dwc_otg_dev_in_ep_regs_t *)
+-00114                     (reg_base + DWC_DEV_IN_EP_REG_OFFSET +
+-00115                      (i * DWC_EP_REG_OFFSET));
+-00116 
+-00117                 dev_if->out_ep_regs[i] = (dwc_otg_dev_out_ep_regs_t *)
+-00118                     (reg_base + DWC_DEV_OUT_EP_REG_OFFSET +
+-00119                      (i * DWC_EP_REG_OFFSET));
+-00120                 DWC_DEBUGPL(DBG_CILV, "in_ep_regs[%d]->diepctl=%p\n",
+-00121                             i, &dev_if->in_ep_regs[i]->diepctl);
+-00122                 DWC_DEBUGPL(DBG_CILV, "out_ep_regs[%d]->doepctl=%p\n",
+-00123                             i, &dev_if->out_ep_regs[i]->doepctl);
+-00124         }
+-00125 
+-00126         dev_if->speed = 0;      // unknown
+-00127 
+-00128         core_if->dev_if = dev_if;
+-00129 
+-00130         /*
+-00131          * Allocate the Host Mode structures.
+-00132          */
+-00133         host_if = dwc_alloc(sizeof(dwc_otg_host_if_t));
+-00134 
+-00135         if (host_if == 0) {
+-00136                 DWC_DEBUGPL(DBG_CIL,
+-00137                             "Allocation of dwc_otg_host_if_t failed\n");
+-00138                 dwc_free(dev_if);
+-00139                 dwc_free(core_if);
+-00140                 return 0;
+-00141         }
+-00142 
+-00143         host_if->host_global_regs = (dwc_otg_host_global_regs_t *)
+-00144             (reg_base + DWC_OTG_HOST_GLOBAL_REG_OFFSET);
+-00145 
+-00146         host_if->hprt0 =
+-00147             (uint32_t *) (reg_base + DWC_OTG_HOST_PORT_REGS_OFFSET);
+-00148 
+-00149         for (i = 0; i < MAX_EPS_CHANNELS; i++) {
+-00150                 host_if->hc_regs[i] = (dwc_otg_hc_regs_t *)
+-00151                     (reg_base + DWC_OTG_HOST_CHAN_REGS_OFFSET +
+-00152                      (i * DWC_OTG_CHAN_REGS_OFFSET));
+-00153                 DWC_DEBUGPL(DBG_CILV, "hc_reg[%d]->hcchar=%p\n",
+-00154                             i, &host_if->hc_regs[i]->hcchar);
+-00155         }
+-00156 
+-00157         host_if->num_host_channels = MAX_EPS_CHANNELS;
+-00158         core_if->host_if = host_if;
+-00159 
+-00160         for (i = 0; i < MAX_EPS_CHANNELS; i++) {
+-00161                 core_if->data_fifo[i] =
+-00162                     (uint32_t *) (reg_base + DWC_OTG_DATA_FIFO_OFFSET +
+-00163                                   (i * DWC_OTG_DATA_FIFO_SIZE));
+-00164                 DWC_DEBUGPL(DBG_CILV, "data_fifo[%d]=0x%08x\n",
+-00165                             i, (unsigned)core_if->data_fifo[i]);
+-00166         }
+-00167 
+-00168         core_if->pcgcctl = (uint32_t *) (reg_base + DWC_OTG_PCGCCTL_OFFSET);
+-00169 
+-00170         /* Initiate lx_state to L3 disconnected state */
+-00171         core_if->lx_state = DWC_OTG_L3;
+-00172         /*
+-00173          * Store the contents of the hardware configuration registers here for
+-00174          * easy access later.
+-00175          */
+-00176         core_if->hwcfg1.d32 =
+-00177             dwc_read_reg32(&core_if->core_global_regs->ghwcfg1);
+-00178         core_if->hwcfg2.d32 =
+-00179             dwc_read_reg32(&core_if->core_global_regs->ghwcfg2);
+-00180         core_if->hwcfg3.d32 =
+-00181             dwc_read_reg32(&core_if->core_global_regs->ghwcfg3);
+-00182         core_if->hwcfg4.d32 =
+-00183             dwc_read_reg32(&core_if->core_global_regs->ghwcfg4);
+-00184 
+-00185         DWC_DEBUGPL(DBG_CILV, "hwcfg1=%08x\n", core_if->hwcfg1.d32);
+-00186         DWC_DEBUGPL(DBG_CILV, "hwcfg2=%08x\n", core_if->hwcfg2.d32);
+-00187         DWC_DEBUGPL(DBG_CILV, "hwcfg3=%08x\n", core_if->hwcfg3.d32);
+-00188         DWC_DEBUGPL(DBG_CILV, "hwcfg4=%08x\n", core_if->hwcfg4.d32);
+-00189 
+-00190         core_if->hcfg.d32 =
+-00191             dwc_read_reg32(&core_if->host_if->host_global_regs->hcfg);
+-00192         core_if->dcfg.d32 =
+-00193             dwc_read_reg32(&core_if->dev_if->dev_global_regs->dcfg);
+-00194 
+-00195         DWC_DEBUGPL(DBG_CILV, "hcfg=%08x\n", core_if->hcfg.d32);
+-00196         DWC_DEBUGPL(DBG_CILV, "dcfg=%08x\n", core_if->dcfg.d32);
+-00197 
+-00198         DWC_DEBUGPL(DBG_CILV, "op_mode=%0x\n", core_if->hwcfg2.b.op_mode);
+-00199         DWC_DEBUGPL(DBG_CILV, "arch=%0x\n", core_if->hwcfg2.b.architecture);
+-00200         DWC_DEBUGPL(DBG_CILV, "num_dev_ep=%d\n", core_if->hwcfg2.b.num_dev_ep);
+-00201         DWC_DEBUGPL(DBG_CILV, "num_host_chan=%d\n",
+-00202                     core_if->hwcfg2.b.num_host_chan);
+-00203         DWC_DEBUGPL(DBG_CILV, "nonperio_tx_q_depth=0x%0x\n",
+-00204                     core_if->hwcfg2.b.nonperio_tx_q_depth);
+-00205         DWC_DEBUGPL(DBG_CILV, "host_perio_tx_q_depth=0x%0x\n",
+-00206                     core_if->hwcfg2.b.host_perio_tx_q_depth);
+-00207         DWC_DEBUGPL(DBG_CILV, "dev_token_q_depth=0x%0x\n",
+-00208                     core_if->hwcfg2.b.dev_token_q_depth);
+-00209 
+-00210         DWC_DEBUGPL(DBG_CILV, "Total FIFO SZ=%d\n",
+-00211                     core_if->hwcfg3.b.dfifo_depth);
+-00212         DWC_DEBUGPL(DBG_CILV, "xfer_size_cntr_width=%0x\n",
+-00213                     core_if->hwcfg3.b.xfer_size_cntr_width);
+-00214 
+-00215         /*
+-00216          * Set the SRP sucess bit for FS-I2c
+-00217          */
+-00218         core_if->srp_success = 0;
+-00219         core_if->srp_timer_started = 0;
+-00220 
+-00221         /*
+-00222          * Create new workqueue and init works
+-00223          */
+-00224         core_if->wq_otg = DWC_WORKQ_ALLOC("dwc_otg");
+-00225         if (core_if->wq_otg == 0) {
+-00226                 DWC_WARN("DWC_WORKQ_ALLOC failed\n");
+-00227                 dwc_free(host_if);
+-00228                 dwc_free(dev_if);
+-00229                 dwc_free(core_if);
+-00230                 return 0;
+-00231         }
+-00232 
+-00233         core_if->snpsid = dwc_read_reg32(&core_if->core_global_regs->gsnpsid);
+-00234 
+-00235         DWC_PRINTF("Core Release: %x.%x%x%x\n",
+-00236                    (core_if->snpsid >> 12 & 0xF),
+-00237                    (core_if->snpsid >> 8 & 0xF),
+-00238                    (core_if->snpsid >> 4 & 0xF), (core_if->snpsid & 0xF));
+-00239 
+-00240         core_if->wkp_timer = DWC_TIMER_ALLOC("Wake Up Timer",
+-00241                                              w_wakeup_detected, core_if);
+-00242         if (core_if->wkp_timer == 0) {
+-00243                 DWC_WARN("DWC_TIMER_ALLOC failed\n");
+-00244                 dwc_free(host_if);
+-00245                 dwc_free(dev_if);
+-00246                 DWC_WORKQ_FREE(core_if->wq_otg);
+-00247                 dwc_free(core_if);
+-00248                 return 0;
+-00249         }
+-00250 
+-00251         if (dwc_otg_setup_params(core_if)) {
+-00252                 DWC_WARN("Error while setting core params\n");
+-00253         }
+-00254 
+-00255         return core_if;
+-00256 }
+-00257 
+-00265 void dwc_otg_cil_remove(dwc_otg_core_if_t * core_if)
+-00266 {
+-00267         /* Disable all interrupts */
+-00268         dwc_modify_reg32(&core_if->core_global_regs->gahbcfg, 1, 0);
+-00269         dwc_write_reg32(&core_if->core_global_regs->gintmsk, 0);
+-00270 
+-00271         if (core_if->wq_otg) {
+-00272                 DWC_WORKQ_WAIT_WORK_DONE(core_if->wq_otg, 500);
+-00273                 DWC_WORKQ_FREE(core_if->wq_otg);
+-00274         }
+-00275         if (core_if->dev_if) {
+-00276                 dwc_free(core_if->dev_if);
+-00277         }
+-00278         if (core_if->host_if) {
+-00279                 dwc_free(core_if->host_if);
+-00280         }
+-00281         dwc_free(core_if);
+-00282         DWC_TIMER_FREE(core_if->wkp_timer);
+-00283         DWC_FREE(core_if->core_params);
+-00284 }
+-00285 
+-00292 void dwc_otg_enable_global_interrupts(dwc_otg_core_if_t * core_if)
+-00293 {
+-00294         gahbcfg_data_t ahbcfg = {.d32 = 0 };
+-00295         ahbcfg.b.glblintrmsk = 1;       /* Enable interrupts */
+-00296         dwc_modify_reg32(&core_if->core_global_regs->gahbcfg, 0, ahbcfg.d32);
+-00297 }
+-00298 
+-00305 void dwc_otg_disable_global_interrupts(dwc_otg_core_if_t * core_if)
+-00306 {
+-00307         gahbcfg_data_t ahbcfg = {.d32 = 0 };
+-00308         ahbcfg.b.glblintrmsk = 1;       /* Enable interrupts */
+-00309         dwc_modify_reg32(&core_if->core_global_regs->gahbcfg, ahbcfg.d32, 0);
+-00310 }
+-00311 
+-00319 static void dwc_otg_enable_common_interrupts(dwc_otg_core_if_t * core_if)
+-00320 {
+-00321         dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
+-00322         gintmsk_data_t intr_mask = {.d32 = 0 };
+-00323 
+-00324         /* Clear any pending OTG Interrupts */
+-00325         dwc_write_reg32(&global_regs->gotgint, 0xFFFFFFFF);
+-00326 
+-00327         /* Clear any pending interrupts */
+-00328         dwc_write_reg32(&global_regs->gintsts, 0xFFFFFFFF);
+-00329 
+-00330         /* 
+-00331          * Enable the interrupts in the GINTMSK. 
+-00332          */
+-00333         intr_mask.b.modemismatch = 1;
+-00334         intr_mask.b.otgintr = 1;
+-00335 
+-00336         if (!core_if->dma_enable) {
+-00337                 intr_mask.b.rxstsqlvl = 1;
+-00338         }
+-00339 
+-00340         intr_mask.b.conidstschng = 1;
+-00341         intr_mask.b.wkupintr = 1;
+-00342         intr_mask.b.disconnect = 1;
+-00343         intr_mask.b.usbsuspend = 1;
+-00344         intr_mask.b.sessreqintr = 1;
+-00345 #ifdef CONFIG_USB_DWC_OTG_LPM
+-00346         if (core_if->core_params->lpm_enable) {
+-00347                 intr_mask.b.lpmtranrcvd = 1;
+-00348         }
+-00349 #endif
+-00350         dwc_write_reg32(&global_regs->gintmsk, intr_mask.d32);
+-00351 }
+-00352 
+-00357 static void init_fslspclksel(dwc_otg_core_if_t * core_if)
+-00358 {
+-00359         uint32_t val;
+-00360         hcfg_data_t hcfg;
+-00361 
+-00362         if (((core_if->hwcfg2.b.hs_phy_type == 2) &&
+-00363              (core_if->hwcfg2.b.fs_phy_type == 1) &&
+-00364              (core_if->core_params->ulpi_fs_ls)) ||
+-00365             (core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS)) {
+-00366                 /* Full speed PHY */
+-00367                 val = DWC_HCFG_48_MHZ;
+-00368         } else {
+-00369                 /* High speed PHY running at full speed or high speed */
+-00370                 val = DWC_HCFG_30_60_MHZ;
+-00371         }
+-00372 
+-00373         DWC_DEBUGPL(DBG_CIL, "Initializing HCFG.FSLSPClkSel to 0x%1x\n", val);
+-00374         hcfg.d32 = dwc_read_reg32(&core_if->host_if->host_global_regs->hcfg);
+-00375         hcfg.b.fslspclksel = val;
+-00376         dwc_write_reg32(&core_if->host_if->host_global_regs->hcfg, hcfg.d32);
+-00377 }
+-00378 
+-00383 static void init_devspd(dwc_otg_core_if_t * core_if)
+-00384 {
+-00385         uint32_t val;
+-00386         dcfg_data_t dcfg;
+-00387 
+-00388         if (((core_if->hwcfg2.b.hs_phy_type == 2) &&
+-00389              (core_if->hwcfg2.b.fs_phy_type == 1) &&
+-00390              (core_if->core_params->ulpi_fs_ls)) ||
+-00391             (core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS)) {
+-00392                 /* Full speed PHY */
+-00393                 val = 0x3;
+-00394         } else if (core_if->core_params->speed == DWC_SPEED_PARAM_FULL) {
+-00395                 /* High speed PHY running at full speed */
+-00396                 val = 0x1;
+-00397         } else {
+-00398                 /* High speed PHY running at high speed */
+-00399                 val = 0x0;
+-00400         }
+-00401 
+-00402         DWC_DEBUGPL(DBG_CIL, "Initializing DCFG.DevSpd to 0x%1x\n", val);
+-00403 
+-00404         dcfg.d32 = dwc_read_reg32(&core_if->dev_if->dev_global_regs->dcfg);
+-00405         dcfg.b.devspd = val;
+-00406         dwc_write_reg32(&core_if->dev_if->dev_global_regs->dcfg, dcfg.d32);
+-00407 }
+-00408 
+-00415 static uint32_t calc_num_in_eps(dwc_otg_core_if_t * core_if)
+-00416 {
+-00417         uint32_t num_in_eps = 0;
+-00418         uint32_t num_eps = core_if->hwcfg2.b.num_dev_ep;
+-00419         uint32_t hwcfg1 = core_if->hwcfg1.d32 >> 3;
+-00420         uint32_t num_tx_fifos = core_if->hwcfg4.b.num_in_eps;
+-00421         int i;
+-00422 
+-00423         for (i = 0; i < num_eps; ++i) {
+-00424                 if (!(hwcfg1 & 0x1))
+-00425                         num_in_eps++;
+-00426 
+-00427                 hwcfg1 >>= 2;
+-00428         }
+-00429 
+-00430         if (core_if->hwcfg4.b.ded_fifo_en) {
+-00431                 num_in_eps =
+-00432                     (num_in_eps > num_tx_fifos) ? num_tx_fifos : num_in_eps;
+-00433         }
+-00434 
+-00435         return num_in_eps;
+-00436 }
+-00437 
+-00444 static uint32_t calc_num_out_eps(dwc_otg_core_if_t * core_if)
+-00445 {
+-00446         uint32_t num_out_eps = 0;
+-00447         uint32_t num_eps = core_if->hwcfg2.b.num_dev_ep;
+-00448         uint32_t hwcfg1 = core_if->hwcfg1.d32 >> 2;
+-00449         int i;
+-00450 
+-00451         for (i = 0; i < num_eps; ++i) {
+-00452                 if (!(hwcfg1 & 0x1))
+-00453                         num_out_eps++;
+-00454 
+-00455                 hwcfg1 >>= 2;
+-00456         }
+-00457         return num_out_eps;
+-00458 }
+-00459 
+-00467 void dwc_otg_core_init(dwc_otg_core_if_t * core_if)
+-00468 {
+-00469         int i = 0;
+-00470         dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
+-00471         dwc_otg_dev_if_t *dev_if = core_if->dev_if;
+-00472         gahbcfg_data_t ahbcfg = {.d32 = 0 };
+-00473         gusbcfg_data_t usbcfg = {.d32 = 0 };
+-00474         gi2cctl_data_t i2cctl = {.d32 = 0 };
+-00475 
+-00476         DWC_DEBUGPL(DBG_CILV, "dwc_otg_core_init(%p)\n", core_if);
+-00477 
+-00478         /* Common Initialization */
+-00479 
+-00480         usbcfg.d32 = dwc_read_reg32(&global_regs->gusbcfg);
+-00481 
+-00482         /* Program the ULPI External VBUS bit if needed */
+-00483         usbcfg.b.ulpi_ext_vbus_drv =
+-00484             (core_if->core_params->phy_ulpi_ext_vbus ==
+-00485              DWC_PHY_ULPI_EXTERNAL_VBUS) ? 1 : 0;
+-00486 
+-00487         /* Set external TS Dline pulsing */
+-00488         usbcfg.b.term_sel_dl_pulse =
+-00489             (core_if->core_params->ts_dline == 1) ? 1 : 0;
+-00490         dwc_write_reg32(&global_regs->gusbcfg, usbcfg.d32);
+-00491 
+-00492         /* Reset the Controller */
+-00493         dwc_otg_core_reset(core_if);
+-00494 
+-00495         /* Initialize parameters from Hardware configuration registers. */
+-00496         dev_if->num_in_eps = calc_num_in_eps(core_if);
+-00497         dev_if->num_out_eps = calc_num_out_eps(core_if);
+-00498 
+-00499         DWC_DEBUGPL(DBG_CIL, "num_dev_perio_in_ep=%d\n",
+-00500                     core_if->hwcfg4.b.num_dev_perio_in_ep);
+-00501 
+-00502         for (i = 0; i < core_if->hwcfg4.b.num_dev_perio_in_ep; i++) {
+-00503                 dev_if->perio_tx_fifo_size[i] =
+-00504                     dwc_read_reg32(&global_regs->dptxfsiz_dieptxf[i]) >> 16;
+-00505                 DWC_DEBUGPL(DBG_CIL, "Periodic Tx FIFO SZ #%d=0x%0x\n",
+-00506                             i, dev_if->perio_tx_fifo_size[i]);
+-00507         }
+-00508 
+-00509         for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {
+-00510                 dev_if->tx_fifo_size[i] =
+-00511                     dwc_read_reg32(&global_regs->dptxfsiz_dieptxf[i]) >> 16;
+-00512                 DWC_DEBUGPL(DBG_CIL, "Tx FIFO SZ #%d=0x%0x\n",
+-00513                             i, dev_if->perio_tx_fifo_size[i]);
+-00514         }
+-00515 
+-00516         core_if->total_fifo_size = core_if->hwcfg3.b.dfifo_depth;
+-00517         core_if->rx_fifo_size = dwc_read_reg32(&global_regs->grxfsiz);
+-00518         core_if->nperio_tx_fifo_size =
+-00519             dwc_read_reg32(&global_regs->gnptxfsiz) >> 16;
+-00520 
+-00521         DWC_DEBUGPL(DBG_CIL, "Total FIFO SZ=%d\n", core_if->total_fifo_size);
+-00522         DWC_DEBUGPL(DBG_CIL, "Rx FIFO SZ=%d\n", core_if->rx_fifo_size);
+-00523         DWC_DEBUGPL(DBG_CIL, "NP Tx FIFO SZ=%d\n",
+-00524                     core_if->nperio_tx_fifo_size);
+-00525 
+-00526         /* This programming sequence needs to happen in FS mode before any other
+-00527          * programming occurs */
+-00528         if ((core_if->core_params->speed == DWC_SPEED_PARAM_FULL) &&
+-00529             (core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS)) {
+-00530                 /* If FS mode with FS PHY */
+-00531 
+-00532                 /* core_init() is now called on every switch so only call the
+-00533                  * following for the first time through. */
+-00534                 if (!core_if->phy_init_done) {
+-00535                         core_if->phy_init_done = 1;
+-00536                         DWC_DEBUGPL(DBG_CIL, "FS_PHY detected\n");
+-00537                         usbcfg.d32 = dwc_read_reg32(&global_regs->gusbcfg);
+-00538                         usbcfg.b.physel = 1;
+-00539                         dwc_write_reg32(&global_regs->gusbcfg, usbcfg.d32);
+-00540 
+-00541                         /* Reset after a PHY select */
+-00542                         dwc_otg_core_reset(core_if);
+-00543                 }
+-00544 
+-00545                 /* Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS.      Also
+-00546                  * do this on HNP Dev/Host mode switches (done in dev_init and
+-00547                  * host_init). */
+-00548                 if (dwc_otg_is_host_mode(core_if)) {
+-00549                         init_fslspclksel(core_if);
+-00550                 } else {
+-00551                         init_devspd(core_if);
+-00552                 }
+-00553 
+-00554                 if (core_if->core_params->i2c_enable) {
+-00555                         DWC_DEBUGPL(DBG_CIL, "FS_PHY Enabling I2c\n");
+-00556                         /* Program GUSBCFG.OtgUtmifsSel to I2C */
+-00557                         usbcfg.d32 = dwc_read_reg32(&global_regs->gusbcfg);
+-00558                         usbcfg.b.otgutmifssel = 1;
+-00559                         dwc_write_reg32(&global_regs->gusbcfg, usbcfg.d32);
+-00560 
+-00561                         /* Program GI2CCTL.I2CEn */
+-00562                         i2cctl.d32 = dwc_read_reg32(&global_regs->gi2cctl);
+-00563                         i2cctl.b.i2cdevaddr = 1;
+-00564                         i2cctl.b.i2cen = 0;
+-00565                         dwc_write_reg32(&global_regs->gi2cctl, i2cctl.d32);
+-00566                         i2cctl.b.i2cen = 1;
+-00567                         dwc_write_reg32(&global_regs->gi2cctl, i2cctl.d32);
+-00568                 }
+-00569 
+-00570         } /* endif speed == DWC_SPEED_PARAM_FULL */
+-00571         else {
+-00572                 /* High speed PHY. */
+-00573                 if (!core_if->phy_init_done) {
+-00574                         core_if->phy_init_done = 1;
+-00575                         /* HS PHY parameters.  These parameters are preserved
+-00576                          * during soft reset so only program the first time.  Do
+-00577                          * a soft reset immediately after setting phyif.  */
+-00578                         usbcfg.b.ulpi_utmi_sel = core_if->core_params->phy_type;
+-00579                         if (usbcfg.b.ulpi_utmi_sel == 1) {
+-00580                                 /* ULPI interface */
+-00581                                 usbcfg.b.phyif = 0;
+-00582                                 usbcfg.b.ddrsel =
+-00583                                     core_if->core_params->phy_ulpi_ddr;
+-00584                         } else {
+-00585                                 /* UTMI+ interface */
+-00586                                 if (core_if->core_params->phy_utmi_width == 16) {
+-00587                                         usbcfg.b.phyif = 1;
+-00588 
+-00589                                 } else {
+-00590                                         usbcfg.b.phyif = 0;
+-00591                                 }
+-00592 
+-00593                         }
+-00594 
+-00595                         dwc_write_reg32(&global_regs->gusbcfg, usbcfg.d32);
+-00596                         /* Reset after setting the PHY parameters */
+-00597                         dwc_otg_core_reset(core_if);
+-00598                 }
+-00599         }
+-00600 
+-00601         if ((core_if->hwcfg2.b.hs_phy_type == 2) &&
+-00602             (core_if->hwcfg2.b.fs_phy_type == 1) &&
+-00603             (core_if->core_params->ulpi_fs_ls)) {
+-00604                 DWC_DEBUGPL(DBG_CIL, "Setting ULPI FSLS\n");
+-00605                 usbcfg.d32 = dwc_read_reg32(&global_regs->gusbcfg);
+-00606                 usbcfg.b.ulpi_fsls = 1;
+-00607                 usbcfg.b.ulpi_clk_sus_m = 1;
+-00608                 dwc_write_reg32(&global_regs->gusbcfg, usbcfg.d32);
+-00609         } else {
+-00610                 usbcfg.d32 = dwc_read_reg32(&global_regs->gusbcfg);
+-00611                 usbcfg.b.ulpi_fsls = 0;
+-00612                 usbcfg.b.ulpi_clk_sus_m = 0;
+-00613                 dwc_write_reg32(&global_regs->gusbcfg, usbcfg.d32);
+-00614         }
+-00615 
+-00616         /* Program the GAHBCFG Register. */
+-00617         switch (core_if->hwcfg2.b.architecture) {
+-00618 
+-00619         case DWC_SLAVE_ONLY_ARCH:
+-00620                 DWC_DEBUGPL(DBG_CIL, "Slave Only Mode\n");
+-00621                 ahbcfg.b.nptxfemplvl_txfemplvl =
+-00622                     DWC_GAHBCFG_TXFEMPTYLVL_HALFEMPTY;
+-00623                 ahbcfg.b.ptxfemplvl = DWC_GAHBCFG_TXFEMPTYLVL_HALFEMPTY;
+-00624                 core_if->dma_enable = 0;
+-00625                 core_if->dma_desc_enable = 0;
+-00626                 break;
+-00627 
+-00628         case DWC_EXT_DMA_ARCH:
+-00629                 DWC_DEBUGPL(DBG_CIL, "External DMA Mode\n");
+-00630                 {
+-00631                         uint8_t brst_sz = core_if->core_params->dma_burst_size;
+-00632                         ahbcfg.b.hburstlen = 0;
+-00633                         while (brst_sz > 1) {
+-00634                                 ahbcfg.b.hburstlen++;
+-00635                                 brst_sz >>= 1;
+-00636                         }
+-00637                 }
+-00638                 core_if->dma_enable = (core_if->core_params->dma_enable != 0);
+-00639                 core_if->dma_desc_enable =
+-00640                     (core_if->core_params->dma_desc_enable != 0);
+-00641                 break;
+-00642 
+-00643         case DWC_INT_DMA_ARCH:
+-00644                 DWC_DEBUGPL(DBG_CIL, "Internal DMA Mode\n");
+-00645                 ahbcfg.b.hburstlen = DWC_GAHBCFG_INT_DMA_BURST_INCR;
+-00646                 core_if->dma_enable = (core_if->core_params->dma_enable != 0);
+-00647                 core_if->dma_desc_enable =
+-00648                     (core_if->core_params->dma_desc_enable != 0);
+-00649                 break;
+-00650 
+-00651         }
+-00652         if (core_if->dma_enable) {
+-00653                 if (core_if->dma_desc_enable) {
+-00654                         DWC_PRINTF("Using Descriptor DMA mode\n");
+-00655                 } else {
+-00656                         DWC_PRINTF("Using Buffer DMA mode\n");
+-00657 
+-00658                 }
+-00659         } else {
+-00660                 DWC_PRINTF("Using Slave mode\n");
+-00661                 core_if->dma_desc_enable = 0;
+-00662         }
+-00663         
+-00664         ahbcfg.b.dmaenable = core_if->dma_enable;
+-00665         dwc_write_reg32(&global_regs->gahbcfg, ahbcfg.d32);
+-00666 
+-00667         core_if->en_multiple_tx_fifo = core_if->hwcfg4.b.ded_fifo_en;
+-00668 
+-00669         core_if->pti_enh_enable = core_if->core_params->pti_enable != 0;
+-00670         core_if->multiproc_int_enable = core_if->core_params->mpi_enable;
+-00671         DWC_PRINTF("Periodic Transfer Interrupt Enhancement - %s\n",
+-00672                    ((core_if->pti_enh_enable) ? "enabled" : "disabled"));
+-00673         DWC_PRINTF("Multiprocessor Interrupt Enhancement - %s\n",
+-00674                    ((core_if->multiproc_int_enable) ? "enabled" : "disabled"));
+-00675 
+-00676         /* 
+-00677          * Program the GUSBCFG register. 
+-00678          */
+-00679         usbcfg.d32 = dwc_read_reg32(&global_regs->gusbcfg);
+-00680 
+-00681         switch (core_if->hwcfg2.b.op_mode) {
+-00682         case DWC_MODE_HNP_SRP_CAPABLE:
+-00683                 usbcfg.b.hnpcap = (core_if->core_params->otg_cap ==
+-00684                                    DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE);
+-00685                 usbcfg.b.srpcap = (core_if->core_params->otg_cap !=
+-00686                                    DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE);
+-00687                 break;
+-00688 
+-00689         case DWC_MODE_SRP_ONLY_CAPABLE:
+-00690                 usbcfg.b.hnpcap = 0;
+-00691                 usbcfg.b.srpcap = (core_if->core_params->otg_cap !=
+-00692                                    DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE);
+-00693                 break;
+-00694 
+-00695         case DWC_MODE_NO_HNP_SRP_CAPABLE:
+-00696                 usbcfg.b.hnpcap = 0;
+-00697                 usbcfg.b.srpcap = 0;
+-00698                 break;
+-00699 
+-00700         case DWC_MODE_SRP_CAPABLE_DEVICE:
+-00701                 usbcfg.b.hnpcap = 0;
+-00702                 usbcfg.b.srpcap = (core_if->core_params->otg_cap !=
+-00703                                    DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE);
+-00704                 break;
+-00705 
+-00706         case DWC_MODE_NO_SRP_CAPABLE_DEVICE:
+-00707                 usbcfg.b.hnpcap = 0;
+-00708                 usbcfg.b.srpcap = 0;
+-00709                 break;
+-00710 
+-00711         case DWC_MODE_SRP_CAPABLE_HOST:
+-00712                 usbcfg.b.hnpcap = 0;
+-00713                 usbcfg.b.srpcap = (core_if->core_params->otg_cap !=
+-00714                                    DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE);
+-00715                 break;
+-00716 
+-00717         case DWC_MODE_NO_SRP_CAPABLE_HOST:
+-00718                 usbcfg.b.hnpcap = 0;
+-00719                 usbcfg.b.srpcap = 0;
+-00720                 break;
+-00721         }
+-00722 
+-00723         dwc_write_reg32(&global_regs->gusbcfg, usbcfg.d32);
+-00724 
+-00725 #ifdef CONFIG_USB_DWC_OTG_LPM
+-00726         if (core_if->core_params->lpm_enable) {
+-00727                 glpmcfg_data_t lpmcfg = {.d32 = 0 };
+-00728 
+-00729                 /* To enable LPM support set lpm_cap_en bit */
+-00730                 lpmcfg.b.lpm_cap_en = 1;
+-00731 
+-00732                 /* Make AppL1Res ACK */
+-00733                 lpmcfg.b.appl_resp = 1;
+-00734 
+-00735                 /* Retry 3 times */
+-00736                 lpmcfg.b.retry_count = 3;
+-00737 
+-00738                 dwc_modify_reg32(&core_if->core_global_regs->glpmcfg,
+-00739                                  0, lpmcfg.d32);
+-00740 
+-00741         }
+-00742 #endif
+-00743         if (core_if->core_params->ic_usb_cap) {
+-00744                 gusbcfg_data_t gusbcfg = {.d32 = 0 };
+-00745                 gusbcfg.b.ic_usb_cap = 1;
+-00746                 dwc_modify_reg32(&core_if->core_global_regs->gusbcfg,
+-00747                                  0, gusbcfg.d32);
+-00748         }
+-00749 
+-00750         /* Enable common interrupts */
+-00751         dwc_otg_enable_common_interrupts(core_if);
+-00752 
+-00753         /* Do device or host intialization based on mode during PCD
+-00754          * and HCD initialization  */
+-00755         if (dwc_otg_is_host_mode(core_if)) {
+-00756                 DWC_DEBUGPL(DBG_ANY, "Host Mode\n");
+-00757                 core_if->op_state = A_HOST;
+-00758         } else {
+-00759                 DWC_DEBUGPL(DBG_ANY, "Device Mode\n");
+-00760                 core_if->op_state = B_PERIPHERAL;
+-00761 #ifdef DWC_DEVICE_ONLY
+-00762                 dwc_otg_core_dev_init(core_if);
+-00763 #endif
+-00764         }
+-00765 }
+-00766 
+-00772 void dwc_otg_enable_device_interrupts(dwc_otg_core_if_t * core_if)
+-00773 {
+-00774         gintmsk_data_t intr_mask = {.d32 = 0 };
+-00775         dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
+-00776 
+-00777         DWC_DEBUGPL(DBG_CIL, "%s()\n", __func__);
+-00778 
+-00779         /* Disable all interrupts. */
+-00780         dwc_write_reg32(&global_regs->gintmsk, 0);
+-00781 
+-00782         /* Clear any pending interrupts */
+-00783         dwc_write_reg32(&global_regs->gintsts, 0xFFFFFFFF);
+-00784 
+-00785         /* Enable the common interrupts */
+-00786         dwc_otg_enable_common_interrupts(core_if);
+-00787 
+-00788         /* Enable interrupts */
+-00789         intr_mask.b.usbreset = 1;
+-00790         intr_mask.b.enumdone = 1;
+-00791 
+-00792         if (!core_if->multiproc_int_enable) {
+-00793                 intr_mask.b.inepintr = 1;
+-00794                 intr_mask.b.outepintr = 1;
+-00795         }
+-00796 
+-00797         intr_mask.b.erlysuspend = 1;
+-00798 
+-00799         if (core_if->en_multiple_tx_fifo == 0) {
+-00800                 intr_mask.b.epmismatch = 1;
+-00801         }
+-00802 #ifdef DWC_EN_ISOC
+-00803         if (core_if->dma_enable) {
+-00804                 if (core_if->dma_desc_enable == 0) {
+-00805                         if (core_if->pti_enh_enable) {
+-00806                                 dctl_data_t dctl = {.d32 = 0 };
+-00807                                 dctl.b.ifrmnum = 1;
+-00808                                 dwc_modify_reg32(&core_if->dev_if->
+-00809                                                  dev_global_regs->dctl, 0,
+-00810                                                  dctl.d32);
+-00811                         } else {
+-00812                                 intr_mask.b.incomplisoin = 1;
+-00813                                 intr_mask.b.incomplisoout = 1;
+-00814                         }
+-00815                 }
+-00816         } else {
+-00817                 intr_mask.b.incomplisoin = 1;
+-00818                 intr_mask.b.incomplisoout = 1;
+-00819         }
+-00820 #endif                          /* DWC_EN_ISOC */
+-00821 
+-00823 #ifdef USE_PERIODIC_EP
+-00824         intr_mask.b.isooutdrop = 1;
+-00825         intr_mask.b.eopframe = 1;
+-00826         intr_mask.b.incomplisoin = 1;
+-00827         intr_mask.b.incomplisoout = 1;
+-00828 #endif
+-00829 
+-00830         dwc_modify_reg32(&global_regs->gintmsk, intr_mask.d32, intr_mask.d32);
+-00831 
+-00832         DWC_DEBUGPL(DBG_CIL, "%s() gintmsk=%0x\n", __func__,
+-00833                     dwc_read_reg32(&global_regs->gintmsk));
+-00834 }
+-00835 
+-00843 void dwc_otg_core_dev_init(dwc_otg_core_if_t * core_if)
+-00844 {
+-00845         int i;
+-00846         dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
+-00847         dwc_otg_dev_if_t *dev_if = core_if->dev_if;
+-00848         dwc_otg_core_params_t *params = core_if->core_params;
+-00849         dcfg_data_t dcfg = {.d32 = 0 };
+-00850         grstctl_t resetctl = {.d32 = 0 };
+-00851         uint32_t rx_fifo_size;
+-00852         fifosize_data_t nptxfifosize;
+-00853         fifosize_data_t txfifosize;
+-00854         dthrctl_data_t dthrctl;
+-00855         fifosize_data_t ptxfifosize;
+-00856 
+-00857         /* Restart the Phy Clock */
+-00858         dwc_write_reg32(core_if->pcgcctl, 0);
+-00859 
+-00860         /* Device configuration register */
+-00861         init_devspd(core_if);
+-00862         dcfg.d32 = dwc_read_reg32(&dev_if->dev_global_regs->dcfg);
+-00863         dcfg.b.descdma = (core_if->dma_desc_enable) ? 1 : 0;
+-00864         dcfg.b.perfrint = DWC_DCFG_FRAME_INTERVAL_80;
+-00865 
+-00866         dwc_write_reg32(&dev_if->dev_global_regs->dcfg, dcfg.d32);
+-00867 
+-00868         /* Configure data FIFO sizes */
+-00869         if (core_if->hwcfg2.b.dynamic_fifo && params->enable_dynamic_fifo) {
+-00870                 DWC_DEBUGPL(DBG_CIL, "Total FIFO Size=%d\n",
+-00871                             core_if->total_fifo_size);
+-00872                 DWC_DEBUGPL(DBG_CIL, "Rx FIFO Size=%d\n",
+-00873                             params->dev_rx_fifo_size);
+-00874                 DWC_DEBUGPL(DBG_CIL, "NP Tx FIFO Size=%d\n",
+-00875                             params->dev_nperio_tx_fifo_size);
+-00876 
+-00877                 /* Rx FIFO */
+-00878                 DWC_DEBUGPL(DBG_CIL, "initial grxfsiz=%08x\n",
+-00879                             dwc_read_reg32(&global_regs->grxfsiz));
+-00880 
+-00881 #ifdef DWC_UTE_CFI
+-00882                 core_if->pwron_rxfsiz = dwc_read_reg32(&global_regs->grxfsiz);
+-00883                 core_if->init_rxfsiz = params->dev_rx_fifo_size;
+-00884 #endif
+-00885                 rx_fifo_size = params->dev_rx_fifo_size;
+-00886                 dwc_write_reg32(&global_regs->grxfsiz, rx_fifo_size);
+-00887 
+-00888                 DWC_DEBUGPL(DBG_CIL, "new grxfsiz=%08x\n",
+-00889                             dwc_read_reg32(&global_regs->grxfsiz));
+-00890 
+-00892                 core_if->p_tx_msk = 0;
+-00893 
+-00895                 core_if->tx_msk = 0;
+-00896 
+-00897                 if (core_if->en_multiple_tx_fifo == 0) {
+-00898                         /* Non-periodic Tx FIFO */
+-00899                         DWC_DEBUGPL(DBG_CIL, "initial gnptxfsiz=%08x\n",
+-00900                                     dwc_read_reg32(&global_regs->gnptxfsiz));
+-00901 
+-00902                         nptxfifosize.b.depth = params->dev_nperio_tx_fifo_size;
+-00903                         nptxfifosize.b.startaddr = params->dev_rx_fifo_size;
+-00904 
+-00905                         dwc_write_reg32(&global_regs->gnptxfsiz,
+-00906                                         nptxfifosize.d32);
+-00907 
+-00908                         DWC_DEBUGPL(DBG_CIL, "new gnptxfsiz=%08x\n",
+-00909                                     dwc_read_reg32(&global_regs->gnptxfsiz));
+-00910 
+-00912                         /*
+-00913                          * Periodic Tx FIFOs These FIFOs are numbered from 1 to 15.
+-00914                          * Indexes of the FIFO size module parameters in the
+-00915                          * dev_perio_tx_fifo_size array and the FIFO size registers in
+-00916                          * the dptxfsiz array run from 0 to 14.
+-00917                          */
+-00919                         ptxfifosize.b.startaddr =
+-00920                             nptxfifosize.b.startaddr + nptxfifosize.b.depth;
+-00921                         for (i = 0; i < core_if->hwcfg4.b.num_dev_perio_in_ep;
+-00922                              i++) {
+-00923                                 ptxfifosize.b.depth =
+-00924                                     params->dev_perio_tx_fifo_size[i];
+-00925                                 DWC_DEBUGPL(DBG_CIL,
+-00926                                             "initial dptxfsiz_dieptxf[%d]=%08x\n",
+-00927                                             i,
+-00928                                             dwc_read_reg32(&global_regs->
+-00929                                                            dptxfsiz_dieptxf
+-00930                                                            [i]));
+-00931                                 dwc_write_reg32(&global_regs->
+-00932                                                 dptxfsiz_dieptxf[i],
+-00933                                                 ptxfifosize.d32);
+-00934                                 DWC_DEBUGPL(DBG_CIL,
+-00935                                             "new dptxfsiz_dieptxf[%d]=%08x\n",
+-00936                                             i,
+-00937                                             dwc_read_reg32(&global_regs->
+-00938                                                            dptxfsiz_dieptxf
+-00939                                                            [i]));
+-00940                                 ptxfifosize.b.startaddr += ptxfifosize.b.depth;
+-00941                         }
+-00942                 } else {
+-00943                         /*
+-00944                          * Tx FIFOs These FIFOs are numbered from 1 to 15.
+-00945                          * Indexes of the FIFO size module parameters in the
+-00946                          * dev_tx_fifo_size array and the FIFO size registers in
+-00947                          * the dptxfsiz_dieptxf array run from 0 to 14.
+-00948                          */
+-00949 
+-00950                         /* Non-periodic Tx FIFO */
+-00951                         DWC_DEBUGPL(DBG_CIL, "initial gnptxfsiz=%08x\n",
+-00952                                     dwc_read_reg32(&global_regs->gnptxfsiz));
+-00953 
+-00954 #ifdef DWC_UTE_CFI
+-00955                         core_if->pwron_gnptxfsiz =
+-00956                             (dwc_read_reg32(&global_regs->gnptxfsiz) >> 16);
+-00957                         core_if->init_gnptxfsiz =
+-00958                             params->dev_nperio_tx_fifo_size;
+-00959 #endif
+-00960                         nptxfifosize.b.depth = params->dev_nperio_tx_fifo_size;
+-00961                         nptxfifosize.b.startaddr = params->dev_rx_fifo_size;
+-00962 
+-00963                         dwc_write_reg32(&global_regs->gnptxfsiz,
+-00964                                         nptxfifosize.d32);
+-00965 
+-00966                         DWC_DEBUGPL(DBG_CIL, "new gnptxfsiz=%08x\n",
+-00967                                     dwc_read_reg32(&global_regs->gnptxfsiz));
+-00968 
+-00969                         txfifosize.b.startaddr =
+-00970                             nptxfifosize.b.startaddr + nptxfifosize.b.depth;
+-00971 
+-00972                         for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {
+-00973 
+-00974                                 txfifosize.b.depth =
+-00975                                     params->dev_tx_fifo_size[i];
+-00976 
+-00977                                 DWC_DEBUGPL(DBG_CIL,
+-00978                                             "initial dptxfsiz_dieptxf[%d]=%08x\n",
+-00979                                             i,
+-00980                                             dwc_read_reg32(&global_regs->
+-00981                                                            dptxfsiz_dieptxf
+-00982                                                            [i]));
+-00983 
+-00984 #ifdef DWC_UTE_CFI
+-00985                                 core_if->pwron_txfsiz[i] =
+-00986                                     (dwc_read_reg32
+-00987                                      (&global_regs->dptxfsiz_dieptxf[i]) >> 16);
+-00988                                 core_if->init_txfsiz[i] =
+-00989                                     params->dev_tx_fifo_size[i];
+-00990 #endif
+-00991                                 dwc_write_reg32(&global_regs->
+-00992                                                 dptxfsiz_dieptxf[i],
+-00993                                                 txfifosize.d32);
+-00994 
+-00995                                 DWC_DEBUGPL(DBG_CIL,
+-00996                                             "new dptxfsiz_dieptxf[%d]=%08x\n",
+-00997                                             i,
+-00998                                             dwc_read_reg32(&global_regs->
+-00999                                                            dptxfsiz_dieptxf
+-01000                                                            [i]));
+-01001 
+-01002                                 txfifosize.b.startaddr += txfifosize.b.depth;
+-01003                         }
+-01004                 }
+-01005         }
+-01006         /* Flush the FIFOs */
+-01007         dwc_otg_flush_tx_fifo(core_if, 0x10);   /* all Tx FIFOs */
+-01008         dwc_otg_flush_rx_fifo(core_if);
+-01009 
+-01010         /* Flush the Learning Queue. */
+-01011         resetctl.b.intknqflsh = 1;
+-01012         dwc_write_reg32(&core_if->core_global_regs->grstctl, resetctl.d32);
+-01013 
+-01014         /* Clear all pending Device Interrupts */
+-01018         if (core_if->multiproc_int_enable) {
+-01019                 for (i = 0; i < core_if->dev_if->num_in_eps; ++i) {
+-01020                         dwc_write_reg32(&dev_if->dev_global_regs->
+-01021                                         diepeachintmsk[i], 0);
+-01022                 }
+-01023 
+-01024                 for (i = 0; i < core_if->dev_if->num_out_eps; ++i) {
+-01025                         dwc_write_reg32(&dev_if->dev_global_regs->
+-01026                                         doepeachintmsk[i], 0);
+-01027                 }
+-01028 
+-01029                 dwc_write_reg32(&dev_if->dev_global_regs->deachint, 0xFFFFFFFF);
+-01030                 dwc_write_reg32(&dev_if->dev_global_regs->deachintmsk, 0);
+-01031         } else {
+-01032                 dwc_write_reg32(&dev_if->dev_global_regs->diepmsk, 0);
+-01033                 dwc_write_reg32(&dev_if->dev_global_regs->doepmsk, 0);
+-01034                 dwc_write_reg32(&dev_if->dev_global_regs->daint, 0xFFFFFFFF);
+-01035                 dwc_write_reg32(&dev_if->dev_global_regs->daintmsk, 0);
+-01036         }
+-01037 
+-01038         for (i = 0; i <= dev_if->num_in_eps; i++) {
+-01039                 depctl_data_t depctl;
+-01040                 depctl.d32 = dwc_read_reg32(&dev_if->in_ep_regs[i]->diepctl);
+-01041                 if (depctl.b.epena) {
+-01042                         depctl.d32 = 0;
+-01043                         depctl.b.epdis = 1;
+-01044                         depctl.b.snak = 1;
+-01045                 } else {
+-01046                         depctl.d32 = 0;
+-01047                 }
+-01048 
+-01049                 dwc_write_reg32(&dev_if->in_ep_regs[i]->diepctl, depctl.d32);
+-01050 
+-01051                 dwc_write_reg32(&dev_if->in_ep_regs[i]->dieptsiz, 0);
+-01052                 dwc_write_reg32(&dev_if->in_ep_regs[i]->diepdma, 0);
+-01053                 dwc_write_reg32(&dev_if->in_ep_regs[i]->diepint, 0xFF);
+-01054         }
+-01055 
+-01056         for (i = 0; i <= dev_if->num_out_eps; i++) {
+-01057                 depctl_data_t depctl;
+-01058                 depctl.d32 = dwc_read_reg32(&dev_if->out_ep_regs[i]->doepctl);
+-01059                 if (depctl.b.epena) {
+-01060                         depctl.d32 = 0;
+-01061                         depctl.b.epdis = 1;
+-01062                         depctl.b.snak = 1;
+-01063                 } else {
+-01064                         depctl.d32 = 0;
+-01065                 }
+-01066 
+-01067                 dwc_write_reg32(&dev_if->out_ep_regs[i]->doepctl, depctl.d32);
+-01068 
+-01069                 dwc_write_reg32(&dev_if->out_ep_regs[i]->doeptsiz, 0);
+-01070                 dwc_write_reg32(&dev_if->out_ep_regs[i]->doepdma, 0);
+-01071                 dwc_write_reg32(&dev_if->out_ep_regs[i]->doepint, 0xFF);
+-01072         }
+-01073 
+-01074         if (core_if->en_multiple_tx_fifo && core_if->dma_enable) {
+-01075                 dev_if->non_iso_tx_thr_en = params->thr_ctl & 0x1;
+-01076                 dev_if->iso_tx_thr_en = (params->thr_ctl >> 1) & 0x1;
+-01077                 dev_if->rx_thr_en = (params->thr_ctl >> 2) & 0x1;
+-01078 
+-01079                 dev_if->rx_thr_length = params->rx_thr_length;
+-01080                 dev_if->tx_thr_length = params->tx_thr_length;
+-01081 
+-01082                 dev_if->setup_desc_index = 0;
+-01083 
+-01084                 dthrctl.d32 = 0;
+-01085                 dthrctl.b.non_iso_thr_en = dev_if->non_iso_tx_thr_en;
+-01086                 dthrctl.b.iso_thr_en = dev_if->iso_tx_thr_en;
+-01087                 dthrctl.b.tx_thr_len = dev_if->tx_thr_length;
+-01088                 dthrctl.b.rx_thr_en = dev_if->rx_thr_en;
+-01089                 dthrctl.b.rx_thr_len = dev_if->rx_thr_length;
+-01090                 dthrctl.b.ahb_thr_ratio = params->ahb_thr_ratio;
+-01091 
+-01092                 dwc_write_reg32(&dev_if->dev_global_regs->dtknqr3_dthrctl,
+-01093                                 dthrctl.d32);
+-01094 
+-01095                 DWC_DEBUGPL(DBG_CIL,
+-01096                             "Non ISO Tx Thr - %d\nISO Tx Thr - %d\nRx Thr - %d\nTx Thr Len - %d\nRx Thr Len - %d\n",
+-01097                             dthrctl.b.non_iso_thr_en, dthrctl.b.iso_thr_en,
+-01098                             dthrctl.b.rx_thr_en, dthrctl.b.tx_thr_len,
+-01099                             dthrctl.b.rx_thr_len);
+-01100 
+-01101         }
+-01102 
+-01103         dwc_otg_enable_device_interrupts(core_if);
+-01104 
+-01105         {
+-01106                 diepmsk_data_t msk = {.d32 = 0 };
+-01107                 msk.b.txfifoundrn = 1;
+-01108                 if (core_if->multiproc_int_enable) {
+-01109                         dwc_modify_reg32(&dev_if->dev_global_regs->
+-01110                                          diepeachintmsk[0], msk.d32, msk.d32);
+-01111                 } else {
+-01112                         dwc_modify_reg32(&dev_if->dev_global_regs->diepmsk,
+-01113                                          msk.d32, msk.d32);
+-01114                 }
+-01115         }
+-01116 
+-01117         if (core_if->multiproc_int_enable) {
+-01118                 /* Set NAK on Babble */
+-01119                 dctl_data_t dctl = {.d32 = 0 };
+-01120                 dctl.b.nakonbble = 1;
+-01121                 dwc_modify_reg32(&dev_if->dev_global_regs->dctl, 0, dctl.d32);
+-01122         }
+-01123 }
+-01124 
+-01130 void dwc_otg_enable_host_interrupts(dwc_otg_core_if_t * core_if)
+-01131 {
+-01132         dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
+-01133         gintmsk_data_t intr_mask = {.d32 = 0 };
+-01134 
+-01135         DWC_DEBUGPL(DBG_CIL, "%s()\n", __func__);
+-01136 
+-01137         /* Disable all interrupts. */
+-01138         dwc_write_reg32(&global_regs->gintmsk, 0);
+-01139 
+-01140         /* Clear any pending interrupts. */
+-01141         dwc_write_reg32(&global_regs->gintsts, 0xFFFFFFFF);
+-01142 
+-01143         /* Enable the common interrupts */
+-01144         dwc_otg_enable_common_interrupts(core_if);
+-01145 
+-01146         /*
+-01147          * Enable host mode interrupts without disturbing common
+-01148          * interrupts.
+-01149          */
+-01150          
+-01151         /* Do not need sof interrupt for Descriptor DMA*/ 
+-01152         if (!core_if->dma_desc_enable) 
+-01153         intr_mask.b.sofintr = 1;
+-01154         intr_mask.b.portintr = 1;
+-01155         intr_mask.b.hcintr = 1;
+-01156 
+-01157         dwc_modify_reg32(&global_regs->gintmsk, intr_mask.d32, intr_mask.d32);
+-01158 }
+-01159 
+-01165 void dwc_otg_disable_host_interrupts(dwc_otg_core_if_t * core_if)
+-01166 {
+-01167         dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
+-01168         gintmsk_data_t intr_mask = {.d32 = 0 };
+-01169 
+-01170         DWC_DEBUGPL(DBG_CILV, "%s()\n", __func__);
+-01171 
+-01172         /*
+-01173          * Disable host mode interrupts without disturbing common
+-01174          * interrupts.
+-01175          */
+-01176         intr_mask.b.sofintr = 1;
+-01177         intr_mask.b.portintr = 1;
+-01178         intr_mask.b.hcintr = 1;
+-01179         intr_mask.b.ptxfempty = 1;
+-01180         intr_mask.b.nptxfempty = 1;
+-01181 
+-01182         dwc_modify_reg32(&global_regs->gintmsk, intr_mask.d32, 0);
+-01183 }
+-01184 
+-01196 void dwc_otg_core_host_init(dwc_otg_core_if_t * core_if)
+-01197 {
+-01198         dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
+-01199         dwc_otg_host_if_t *host_if = core_if->host_if;
+-01200         dwc_otg_core_params_t *params = core_if->core_params;
+-01201         hprt0_data_t hprt0 = {.d32 = 0 };
+-01202         fifosize_data_t nptxfifosize;
+-01203         fifosize_data_t ptxfifosize;
+-01204         int i;
+-01205         hcchar_data_t hcchar;
+-01206         hcfg_data_t hcfg;
+-01207         dwc_otg_hc_regs_t *hc_regs;
+-01208         int num_channels;
+-01209         gotgctl_data_t gotgctl = {.d32 = 0 };
+-01210 
+-01211         DWC_DEBUGPL(DBG_CILV, "%s(%p)\n", __func__, core_if);
+-01212 
+-01213         /* Restart the Phy Clock */
+-01214         dwc_write_reg32(core_if->pcgcctl, 0);
+-01215 
+-01216         /* Initialize Host Configuration Register */
+-01217         init_fslspclksel(core_if);
+-01218         if (core_if->core_params->speed == DWC_SPEED_PARAM_FULL) {
+-01219                 hcfg.d32 = dwc_read_reg32(&host_if->host_global_regs->hcfg);
+-01220                 hcfg.b.fslssupp = 1;
+-01221                 dwc_write_reg32(&host_if->host_global_regs->hcfg, hcfg.d32);
+-01222                 
+-01223         }
+-01224 
+-01225         if (core_if->core_params->dma_desc_enable) {
+-01226                 uint8_t op_mode = core_if->hwcfg2.b.op_mode;    
+-01227                 if (!(core_if->hwcfg4.b.desc_dma && (core_if->snpsid >= OTG_CORE_REV_2_90a) &&
+-01228                                 ((op_mode == DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG) ||
+-01229                                 (op_mode == DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG) || 
+-01230                                 (op_mode == DWC_HWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE_OTG) ||
+-01231                                 (op_mode == DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST) ||
+-01232                                 (op_mode == DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST)))) {
+-01233                                 
+-01234                                 DWC_ERROR("Host can't operate in Descriptor DMA mode.\n"
+-01235                                           "Either core version is below 2.90a or "
+-01236                                           "GHWCFG2, GHWCFG4 registers' values do not allow Descriptor DMA in host mode.\n"
+-01237                                           "To run the driver in Buffer DMA host mode set dma_desc_enable "
+-01238                                           "module parameter to 0.\n");
+-01239                                 return;
+-01240                 }               
+-01241                 hcfg.d32 = dwc_read_reg32(&host_if->host_global_regs->hcfg);
+-01242                 hcfg.b.descdma = 1;
+-01243                 dwc_write_reg32(&host_if->host_global_regs->hcfg, hcfg.d32);
+-01244         }
+-01245         
+-01246         /* Configure data FIFO sizes */
+-01247         if (core_if->hwcfg2.b.dynamic_fifo && params->enable_dynamic_fifo) {
+-01248                 DWC_DEBUGPL(DBG_CIL, "Total FIFO Size=%d\n",
+-01249                             core_if->total_fifo_size);
+-01250                 DWC_DEBUGPL(DBG_CIL, "Rx FIFO Size=%d\n",
+-01251                             params->host_rx_fifo_size);
+-01252                 DWC_DEBUGPL(DBG_CIL, "NP Tx FIFO Size=%d\n",
+-01253                             params->host_nperio_tx_fifo_size);
+-01254                 DWC_DEBUGPL(DBG_CIL, "P Tx FIFO Size=%d\n",
+-01255                             params->host_perio_tx_fifo_size);
+-01256 
+-01257                 /* Rx FIFO */
+-01258                 DWC_DEBUGPL(DBG_CIL, "initial grxfsiz=%08x\n",
+-01259                             dwc_read_reg32(&global_regs->grxfsiz));
+-01260                 dwc_write_reg32(&global_regs->grxfsiz,
+-01261                                 params->host_rx_fifo_size);
+-01262                 DWC_DEBUGPL(DBG_CIL, "new grxfsiz=%08x\n",
+-01263                             dwc_read_reg32(&global_regs->grxfsiz));
+-01264 
+-01265                 /* Non-periodic Tx FIFO */
+-01266                 DWC_DEBUGPL(DBG_CIL, "initial gnptxfsiz=%08x\n",
+-01267                             dwc_read_reg32(&global_regs->gnptxfsiz));
+-01268                 nptxfifosize.b.depth = params->host_nperio_tx_fifo_size;
+-01269                 nptxfifosize.b.startaddr = params->host_rx_fifo_size;
+-01270                 dwc_write_reg32(&global_regs->gnptxfsiz, nptxfifosize.d32);
+-01271                 DWC_DEBUGPL(DBG_CIL, "new gnptxfsiz=%08x\n",
+-01272                             dwc_read_reg32(&global_regs->gnptxfsiz));
+-01273 
+-01274                 /* Periodic Tx FIFO */
+-01275                 DWC_DEBUGPL(DBG_CIL, "initial hptxfsiz=%08x\n",
+-01276                             dwc_read_reg32(&global_regs->hptxfsiz));
+-01277                 ptxfifosize.b.depth = params->host_perio_tx_fifo_size;
+-01278                 ptxfifosize.b.startaddr =
+-01279                     nptxfifosize.b.startaddr + nptxfifosize.b.depth;
+-01280                 dwc_write_reg32(&global_regs->hptxfsiz, ptxfifosize.d32);
+-01281                 DWC_DEBUGPL(DBG_CIL, "new hptxfsiz=%08x\n",
+-01282                             dwc_read_reg32(&global_regs->hptxfsiz));
+-01283         }
+-01284 
+-01285         /* Clear Host Set HNP Enable in the OTG Control Register */
+-01286         gotgctl.b.hstsethnpen = 1;
+-01287         dwc_modify_reg32(&global_regs->gotgctl, gotgctl.d32, 0);
+-01288 
+-01289         /* Make sure the FIFOs are flushed. */
+-01290         dwc_otg_flush_tx_fifo(core_if, 0x10 /* all Tx FIFOs */ );
+-01291         dwc_otg_flush_rx_fifo(core_if);
+-01292 
+-01293         if(!core_if->core_params->dma_desc_enable) {
+-01294                 /* Flush out any leftover queued requests. */
+-01295                 num_channels = core_if->core_params->host_channels;
+-01296         
+-01297                 for (i = 0; i < num_channels; i++) {
+-01298                         hc_regs = core_if->host_if->hc_regs[i];
+-01299                         hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
+-01300                         hcchar.b.chen = 0;
+-01301                         hcchar.b.chdis = 1;
+-01302                         hcchar.b.epdir = 0;
+-01303                         dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
+-01304                 }
+-01305 
+-01306                 /* Halt all channels to put them into a known state. */
+-01307                 for (i = 0; i < num_channels; i++) {
+-01308                         int count = 0;
+-01309                         hc_regs = core_if->host_if->hc_regs[i];
+-01310                         hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
+-01311                         hcchar.b.chen = 1;
+-01312                         hcchar.b.chdis = 1;
+-01313                         hcchar.b.epdir = 0;
+-01314                         dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
+-01315                         DWC_DEBUGPL(DBG_HCDV, "%s: Halt channel %d\n", __func__, i);
+-01316                         do {
+-01317                                 hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
+-01318                                 if (++count > 1000) {
+-01319                                         DWC_ERROR
+-01320                                             ("%s: Unable to clear halt on channel %d\n",
+-01321                                              __func__, i);
+-01322                                         break;
+-01323                                 }
+-01324                                 dwc_udelay(1);
+-01325                         } while (hcchar.b.chen);
+-01326                 }
+-01327         }
+-01328         
+-01329         /* Turn on the vbus power. */
+-01330         DWC_PRINTF("Init: Port Power? op_state=%d\n", core_if->op_state);
+-01331         if (core_if->op_state == A_HOST) {
+-01332                 hprt0.d32 = dwc_otg_read_hprt0(core_if);
+-01333                 DWC_PRINTF("Init: Power Port (%d)\n", hprt0.b.prtpwr);
+-01334                 if (hprt0.b.prtpwr == 0) {
+-01335                         hprt0.b.prtpwr = 1;
+-01336                         dwc_write_reg32(host_if->hprt0, hprt0.d32);
+-01337                 }
+-01338         }
+-01339 
+-01340         dwc_otg_enable_host_interrupts(core_if);
+-01341 }
+-01342 
+-01352 void dwc_otg_hc_init(dwc_otg_core_if_t * core_if, dwc_hc_t * hc)
+-01353 {
+-01354         uint32_t intr_enable;
+-01355         hcintmsk_data_t hc_intr_mask;
+-01356         gintmsk_data_t gintmsk = {.d32 = 0 };
+-01357         hcchar_data_t hcchar;
+-01358         hcsplt_data_t hcsplt;
+-01359 
+-01360         uint8_t hc_num = hc->hc_num;
+-01361         dwc_otg_host_if_t *host_if = core_if->host_if;
+-01362         dwc_otg_hc_regs_t *hc_regs = host_if->hc_regs[hc_num];
+-01363 
+-01364         /* Clear old interrupt conditions for this host channel. */
+-01365         hc_intr_mask.d32 = 0xFFFFFFFF;
+-01366         hc_intr_mask.b.reserved14_31 = 0;
+-01367         dwc_write_reg32(&hc_regs->hcint, hc_intr_mask.d32);
+-01368 
+-01369         /* Enable channel interrupts required for this transfer. */
+-01370         hc_intr_mask.d32 = 0;
+-01371         hc_intr_mask.b.chhltd = 1;
+-01372         if (core_if->dma_enable) {
+-01373                 /* For Descriptor DMA mode core halts the channel on AHB error. Interrupt is not required */
+-01374                 if (!core_if->dma_desc_enable)
+-01375                         hc_intr_mask.b.ahberr = 1;
+-01376                 else {
+-01377                         if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC) 
+-01378                                 hc_intr_mask.b.xfercompl = 1;
+-01379                 }
+-01380                 
+-01381                 if (hc->error_state && !hc->do_split &&
+-01382                     hc->ep_type != DWC_OTG_EP_TYPE_ISOC) {
+-01383                         hc_intr_mask.b.ack = 1;
+-01384                         if (hc->ep_is_in) {
+-01385                                 hc_intr_mask.b.datatglerr = 1;
+-01386                                 if (hc->ep_type != DWC_OTG_EP_TYPE_INTR) {
+-01387                                         hc_intr_mask.b.nak = 1;
+-01388                                 }
+-01389                         }
+-01390                 }
+-01391         } else {
+-01392                 switch (hc->ep_type) {
+-01393                 case DWC_OTG_EP_TYPE_CONTROL:
+-01394                 case DWC_OTG_EP_TYPE_BULK:
+-01395                         hc_intr_mask.b.xfercompl = 1;
+-01396                         hc_intr_mask.b.stall = 1;
+-01397                         hc_intr_mask.b.xacterr = 1;
+-01398                         hc_intr_mask.b.datatglerr = 1;
+-01399                         if (hc->ep_is_in) {
+-01400                                 hc_intr_mask.b.bblerr = 1;
+-01401                         } else {
+-01402                                 hc_intr_mask.b.nak = 1;
+-01403                                 hc_intr_mask.b.nyet = 1;
+-01404                                 if (hc->do_ping) {
+-01405                                         hc_intr_mask.b.ack = 1;
+-01406                                 }
+-01407                         }
+-01408 
+-01409                         if (hc->do_split) {
+-01410                                 hc_intr_mask.b.nak = 1;
+-01411                                 if (hc->complete_split) {
+-01412                                         hc_intr_mask.b.nyet = 1;
+-01413                                 } else {
+-01414                                         hc_intr_mask.b.ack = 1;
+-01415                                 }
+-01416                         }
+-01417 
+-01418                         if (hc->error_state) {
+-01419                                 hc_intr_mask.b.ack = 1;
+-01420                         }
+-01421                         break;
+-01422                 case DWC_OTG_EP_TYPE_INTR:
+-01423                         hc_intr_mask.b.xfercompl = 1;
+-01424                         hc_intr_mask.b.nak = 1;
+-01425                         hc_intr_mask.b.stall = 1;
+-01426                         hc_intr_mask.b.xacterr = 1;
+-01427                         hc_intr_mask.b.datatglerr = 1;
+-01428                         hc_intr_mask.b.frmovrun = 1;
+-01429 
+-01430                         if (hc->ep_is_in) {
+-01431                                 hc_intr_mask.b.bblerr = 1;
+-01432                         }
+-01433                         if (hc->error_state) {
+-01434                                 hc_intr_mask.b.ack = 1;
+-01435                         }
+-01436                         if (hc->do_split) {
+-01437                                 if (hc->complete_split) {
+-01438                                         hc_intr_mask.b.nyet = 1;
+-01439                                 } else {
+-01440                                         hc_intr_mask.b.ack = 1;
+-01441                                 }
+-01442                         }
+-01443                         break;
+-01444                 case DWC_OTG_EP_TYPE_ISOC:
+-01445                         hc_intr_mask.b.xfercompl = 1;
+-01446                         hc_intr_mask.b.frmovrun = 1;
+-01447                         hc_intr_mask.b.ack = 1;
+-01448 
+-01449                         if (hc->ep_is_in) {
+-01450                                 hc_intr_mask.b.xacterr = 1;
+-01451                                 hc_intr_mask.b.bblerr = 1;
+-01452                         }
+-01453                         break;
+-01454                 }
+-01455         }
+-01456         dwc_write_reg32(&hc_regs->hcintmsk, hc_intr_mask.d32);
+-01457 
+-01458         /* Enable the top level host channel interrupt. */
+-01459         intr_enable = (1 << hc_num);
+-01460         dwc_modify_reg32(&host_if->host_global_regs->haintmsk, 0, intr_enable);
+-01461 
+-01462         /* Make sure host channel interrupts are enabled. */
+-01463         gintmsk.b.hcintr = 1;
+-01464         dwc_modify_reg32(&core_if->core_global_regs->gintmsk, 0, gintmsk.d32);
+-01465 
+-01466         /*
+-01467          * Program the HCCHARn register with the endpoint characteristics for
+-01468          * the current transfer.
+-01469          */
+-01470         hcchar.d32 = 0;
+-01471         hcchar.b.devaddr = hc->dev_addr;
+-01472         hcchar.b.epnum = hc->ep_num;
+-01473         hcchar.b.epdir = hc->ep_is_in;
+-01474         hcchar.b.lspddev = (hc->speed == DWC_OTG_EP_SPEED_LOW);
+-01475         hcchar.b.eptype = hc->ep_type;
+-01476         hcchar.b.mps = hc->max_packet;
+-01477 
+-01478         dwc_write_reg32(&host_if->hc_regs[hc_num]->hcchar, hcchar.d32);
+-01479 
+-01480         DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num);
+-01481         DWC_DEBUGPL(DBG_HCDV, "  Dev Addr: %d\n", hcchar.b.devaddr);
+-01482         DWC_DEBUGPL(DBG_HCDV, "  Ep Num: %d\n", hcchar.b.epnum);
+-01483         DWC_DEBUGPL(DBG_HCDV, "  Is In: %d\n", hcchar.b.epdir);
+-01484         DWC_DEBUGPL(DBG_HCDV, "  Is Low Speed: %d\n", hcchar.b.lspddev);
+-01485         DWC_DEBUGPL(DBG_HCDV, "  Ep Type: %d\n", hcchar.b.eptype);
+-01486         DWC_DEBUGPL(DBG_HCDV, "  Max Pkt: %d\n", hcchar.b.mps);
+-01487         DWC_DEBUGPL(DBG_HCDV, "  Multi Cnt: %d\n", hcchar.b.multicnt);
+-01488 
+-01489         /*
+-01490          * Program the HCSPLIT register for SPLITs
+-01491          */
+-01492         hcsplt.d32 = 0;
+-01493         if (hc->do_split) {
+-01494                 DWC_DEBUGPL(DBG_HCDV, "Programming HC %d with split --> %s\n",
+-01495                             hc->hc_num,
+-01496                             hc->complete_split ? "CSPLIT" : "SSPLIT");
+-01497                 hcsplt.b.compsplt = hc->complete_split;
+-01498                 hcsplt.b.xactpos = hc->xact_pos;
+-01499                 hcsplt.b.hubaddr = hc->hub_addr;
+-01500                 hcsplt.b.prtaddr = hc->port_addr;
+-01501                 DWC_DEBUGPL(DBG_HCDV, "   comp split %d\n", hc->complete_split);
+-01502                 DWC_DEBUGPL(DBG_HCDV, "   xact pos %d\n", hc->xact_pos);
+-01503                 DWC_DEBUGPL(DBG_HCDV, "   hub addr %d\n", hc->hub_addr);
+-01504                 DWC_DEBUGPL(DBG_HCDV, "   port addr %d\n", hc->port_addr);
+-01505                 DWC_DEBUGPL(DBG_HCDV, "   is_in %d\n", hc->ep_is_in);
+-01506                 DWC_DEBUGPL(DBG_HCDV, "   Max Pkt: %d\n", hcchar.b.mps);
+-01507                 DWC_DEBUGPL(DBG_HCDV, "   xferlen: %d\n", hc->xfer_len);
+-01508         }
+-01509         dwc_write_reg32(&host_if->hc_regs[hc_num]->hcsplt, hcsplt.d32);
+-01510 
+-01511 }
+-01512 
+-01540 void dwc_otg_hc_halt(dwc_otg_core_if_t * core_if,
+-01541                      dwc_hc_t * hc, dwc_otg_halt_status_e halt_status)
+-01542 {
+-01543         gnptxsts_data_t nptxsts;
+-01544         hptxsts_data_t hptxsts;
+-01545         hcchar_data_t hcchar;
+-01546         dwc_otg_hc_regs_t *hc_regs;
+-01547         dwc_otg_core_global_regs_t *global_regs;
+-01548         dwc_otg_host_global_regs_t *host_global_regs;
+-01549 
+-01550         hc_regs = core_if->host_if->hc_regs[hc->hc_num];
+-01551         global_regs = core_if->core_global_regs;
+-01552         host_global_regs = core_if->host_if->host_global_regs;
+-01553 
+-01554         DWC_ASSERT(!(halt_status == DWC_OTG_HC_XFER_NO_HALT_STATUS),
+-01555                    "halt_status = %d\n", halt_status);
+-01556 
+-01557         if (halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE ||
+-01558             halt_status == DWC_OTG_HC_XFER_AHB_ERR) {
+-01559                 /*
+-01560                  * Disable all channel interrupts except Ch Halted. The QTD
+-01561                  * and QH state associated with this transfer has been cleared
+-01562                  * (in the case of URB_DEQUEUE), so the channel needs to be
+-01563                  * shut down carefully to prevent crashes.
+-01564                  */
+-01565                 hcintmsk_data_t hcintmsk;
+-01566                 hcintmsk.d32 = 0;
+-01567                 hcintmsk.b.chhltd = 1;
+-01568                 dwc_write_reg32(&hc_regs->hcintmsk, hcintmsk.d32);
+-01569 
+-01570                 /*
+-01571                  * Make sure no other interrupts besides halt are currently
+-01572                  * pending. Handling another interrupt could cause a crash due
+-01573                  * to the QTD and QH state.
+-01574                  */
+-01575                 dwc_write_reg32(&hc_regs->hcint, ~hcintmsk.d32);
+-01576 
+-01577                 /*
+-01578                  * Make sure the halt status is set to URB_DEQUEUE or AHB_ERR
+-01579                  * even if the channel was already halted for some other
+-01580                  * reason.
+-01581                  */
+-01582                 hc->halt_status = halt_status;
+-01583 
+-01584                 hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
+-01585                 if (hcchar.b.chen == 0) {
+-01586                         /*
+-01587                          * The channel is either already halted or it hasn't
+-01588                          * started yet. In DMA mode, the transfer may halt if
+-01589                          * it finishes normally or a condition occurs that
+-01590                          * requires driver intervention. Don't want to halt
+-01591                          * the channel again. In either Slave or DMA mode,
+-01592                          * it's possible that the transfer has been assigned
+-01593                          * to a channel, but not started yet when an URB is
+-01594                          * dequeued. Don't want to halt a channel that hasn't
+-01595                          * started yet.
+-01596                          */
+-01597                         return;
+-01598                 }
+-01599         }
+-01600         if (hc->halt_pending) {
+-01601                 /*
+-01602                  * A halt has already been issued for this channel. This might
+-01603                  * happen when a transfer is aborted by a higher level in
+-01604                  * the stack.
+-01605                  */
+-01606 #ifdef DEBUG
+-01607                 DWC_PRINTF
+-01608                     ("*** %s: Channel %d, _hc->halt_pending already set ***\n",
+-01609                      __func__, hc->hc_num);
+-01610 
+-01611 #endif
+-01612                 return;
+-01613         }
+-01614 
+-01615         hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
+-01616         
+-01617         /* No need to set the bit in DDMA for disabling the channel */
+-01618         //TODO check it everywhere channel is disabled          
+-01619         if(!core_if->core_params->dma_desc_enable)
+-01620                 hcchar.b.chen = 1;
+-01621         hcchar.b.chdis = 1;
+-01622         
+-01623         if (!core_if->dma_enable) {
+-01624                 /* Check for space in the request queue to issue the halt. */
+-01625                 if (hc->ep_type == DWC_OTG_EP_TYPE_CONTROL ||
+-01626                     hc->ep_type == DWC_OTG_EP_TYPE_BULK) {
+-01627                         nptxsts.d32 = dwc_read_reg32(&global_regs->gnptxsts);
+-01628                         if (nptxsts.b.nptxqspcavail == 0) {
+-01629                                 hcchar.b.chen = 0;
+-01630                         }
+-01631                 } else {
+-01632                         hptxsts.d32 =
+-01633                             dwc_read_reg32(&host_global_regs->hptxsts);
+-01634                         if ((hptxsts.b.ptxqspcavail == 0)
+-01635                             || (core_if->queuing_high_bandwidth)) {
+-01636                                 hcchar.b.chen = 0;
+-01637                         }
+-01638                 }
+-01639         }
+-01640         dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
+-01641 
+-01642         hc->halt_status = halt_status;
+-01643 
+-01644         if (hcchar.b.chen) {
+-01645                 hc->halt_pending = 1;
+-01646                 hc->halt_on_queue = 0;
+-01647         } else {
+-01648                 hc->halt_on_queue = 1;
+-01649         }
+-01650 
+-01651         DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num);
+-01652         DWC_DEBUGPL(DBG_HCDV, "  hcchar: 0x%08x\n", hcchar.d32);
+-01653         DWC_DEBUGPL(DBG_HCDV, "  halt_pending: %d\n", hc->halt_pending);
+-01654         DWC_DEBUGPL(DBG_HCDV, "  halt_on_queue: %d\n", hc->halt_on_queue);
+-01655         DWC_DEBUGPL(DBG_HCDV, "  halt_status: %d\n", hc->halt_status);
+-01656 
+-01657         return;
+-01658 }
+-01659 
+-01667 void dwc_otg_hc_cleanup(dwc_otg_core_if_t * core_if, dwc_hc_t * hc)
+-01668 {
+-01669         dwc_otg_hc_regs_t *hc_regs;
+-01670 
+-01671         hc->xfer_started = 0;
+-01672 
+-01673         /*
+-01674          * Clear channel interrupt enables and any unhandled channel interrupt
+-01675          * conditions.
+-01676          */
+-01677         hc_regs = core_if->host_if->hc_regs[hc->hc_num];
+-01678         dwc_write_reg32(&hc_regs->hcintmsk, 0);
+-01679         dwc_write_reg32(&hc_regs->hcint, 0xFFFFFFFF);
+-01680 #ifdef DEBUG
+-01681         DWC_TIMER_CANCEL(core_if->hc_xfer_timer[hc->hc_num]);
+-01682 #endif
+-01683 }
+-01684 
+-01695 static inline void hc_set_even_odd_frame(dwc_otg_core_if_t * core_if,
+-01696                                          dwc_hc_t * hc, hcchar_data_t * hcchar)
+-01697 {
+-01698         if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
+-01699             hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
+-01700                 hfnum_data_t hfnum;
+-01701                 hfnum.d32 =
+-01702                     dwc_read_reg32(&core_if->host_if->host_global_regs->hfnum);
+-01703 
+-01704                 /* 1 if _next_ frame is odd, 0 if it's even */
+-01705                 hcchar->b.oddfrm = (hfnum.b.frnum & 0x1) ? 0 : 1;
+-01706 #ifdef DEBUG
+-01707                 if (hc->ep_type == DWC_OTG_EP_TYPE_INTR && hc->do_split
+-01708                     && !hc->complete_split) {
+-01709                         switch (hfnum.b.frnum & 0x7) {
+-01710                         case 7:
+-01711                                 core_if->hfnum_7_samples++;
+-01712                                 core_if->hfnum_7_frrem_accum += hfnum.b.frrem;
+-01713                                 break;
+-01714                         case 0:
+-01715                                 core_if->hfnum_0_samples++;
+-01716                                 core_if->hfnum_0_frrem_accum += hfnum.b.frrem;
+-01717                                 break;
+-01718                         default:
+-01719                                 core_if->hfnum_other_samples++;
+-01720                                 core_if->hfnum_other_frrem_accum +=
+-01721                                     hfnum.b.frrem;
+-01722                                 break;
+-01723                         }
+-01724                 }
+-01725 #endif
+-01726         }
+-01727 }
+-01728 
+-01729 #ifdef DEBUG
+-01730 void hc_xfer_timeout(void *ptr)
+-01731 {
+-01732         hc_xfer_info_t *xfer_info = (hc_xfer_info_t *) ptr;
+-01733         int hc_num = xfer_info->hc->hc_num;
+-01734         DWC_WARN("%s: timeout on channel %d\n", __func__, hc_num);
+-01735         DWC_WARN("      start_hcchar_val 0x%08x\n",
+-01736                  xfer_info->core_if->start_hcchar_val[hc_num]);
+-01737 }
+-01738 #endif
+-01739 
+-01740 void set_pid_isoc(dwc_hc_t * hc)
+-01741 {
+-01742         /* Set up the initial PID for the transfer. */
+-01743         if (hc->speed == DWC_OTG_EP_SPEED_HIGH) {
+-01744                 if (hc->ep_is_in) {
+-01745                         if (hc->multi_count == 1) {
+-01746                                 hc->data_pid_start =
+-01747                                     DWC_OTG_HC_PID_DATA0;
+-01748                         } else if (hc->multi_count == 2) {
+-01749                                 hc->data_pid_start =
+-01750                                     DWC_OTG_HC_PID_DATA1;
+-01751                         } else {
+-01752                                 hc->data_pid_start =
+-01753                                     DWC_OTG_HC_PID_DATA2;
+-01754                         }
+-01755                 } else {
+-01756                         if (hc->multi_count == 1) {
+-01757                                 hc->data_pid_start =
+-01758                                     DWC_OTG_HC_PID_DATA0;
+-01759                         } else {
+-01760                                 hc->data_pid_start =
+-01761                                     DWC_OTG_HC_PID_MDATA;
+-01762                         }
+-01763                 }
+-01764         } else {
+-01765                 hc->data_pid_start = DWC_OTG_HC_PID_DATA0;
+-01766         }
+-01767 }
+-01768 
+-01800 void dwc_otg_hc_start_transfer(dwc_otg_core_if_t * core_if, dwc_hc_t * hc)
+-01801 {
+-01802         hcchar_data_t hcchar;
+-01803         hctsiz_data_t hctsiz;
+-01804         uint16_t num_packets;
+-01805         uint32_t max_hc_xfer_size = core_if->core_params->max_transfer_size;
+-01806         uint16_t max_hc_pkt_count = core_if->core_params->max_packet_count;
+-01807         dwc_otg_hc_regs_t *hc_regs = core_if->host_if->hc_regs[hc->hc_num];
+-01808 
+-01809         hctsiz.d32 = 0;
+-01810 
+-01811         if (hc->do_ping) {
+-01812                 if (!core_if->dma_enable) {
+-01813                         dwc_otg_hc_do_ping(core_if, hc);
+-01814                         hc->xfer_started = 1;
+-01815                         return;
+-01816                 } else {
+-01817                         hctsiz.b.dopng = 1;
+-01818                 }
+-01819         }
+-01820 
+-01821         if (hc->do_split) {
+-01822                 num_packets = 1;
+-01823 
+-01824                 if (hc->complete_split && !hc->ep_is_in) {
+-01825                         /* For CSPLIT OUT Transfer, set the size to 0 so the
+-01826                          * core doesn't expect any data written to the FIFO */
+-01827                         hc->xfer_len = 0;
+-01828                 } else if (hc->ep_is_in || (hc->xfer_len > hc->max_packet)) {
+-01829                         hc->xfer_len = hc->max_packet;
+-01830                 } else if (!hc->ep_is_in && (hc->xfer_len > 188)) {
+-01831                         hc->xfer_len = 188;
+-01832                 }
+-01833 
+-01834                 hctsiz.b.xfersize = hc->xfer_len;
+-01835         } else {
+-01836                 /*
+-01837                  * Ensure that the transfer length and packet count will fit
+-01838                  * in the widths allocated for them in the HCTSIZn register.
+-01839                  */
+-01840                 if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
+-01841                     hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
+-01842                         /*
+-01843                          * Make sure the transfer size is no larger than one
+-01844                          * (micro)frame's worth of data. (A check was done
+-01845                          * when the periodic transfer was accepted to ensure
+-01846                          * that a (micro)frame's worth of data can be
+-01847                          * programmed into a channel.)
+-01848                          */
+-01849                         uint32_t max_periodic_len =
+-01850                             hc->multi_count * hc->max_packet;
+-01851                         if (hc->xfer_len > max_periodic_len) {
+-01852                                 hc->xfer_len = max_periodic_len;
+-01853                         } else {
+-01854                         }
+-01855                 } else if (hc->xfer_len > max_hc_xfer_size) {
+-01856                         /* Make sure that xfer_len is a multiple of max packet size. */
+-01857                         hc->xfer_len = max_hc_xfer_size - hc->max_packet + 1;
+-01858                 }
+-01859 
+-01860                 if (hc->xfer_len > 0) {
+-01861                         num_packets =
+-01862                             (hc->xfer_len + hc->max_packet -
+-01863                              1) / hc->max_packet;
+-01864                         if (num_packets > max_hc_pkt_count) {
+-01865                                 num_packets = max_hc_pkt_count;
+-01866                                 hc->xfer_len = num_packets * hc->max_packet;
+-01867                         }
+-01868                 } else {
+-01869                         /* Need 1 packet for transfer length of 0. */
+-01870                         num_packets = 1;
+-01871                 }
+-01872 
+-01873                 if (hc->ep_is_in) {
+-01874                         /* Always program an integral # of max packets for IN transfers. */
+-01875                         hc->xfer_len = num_packets * hc->max_packet;
+-01876                 }
+-01877 
+-01878                 if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
+-01879                     hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
+-01880                         /*
+-01881                          * Make sure that the multi_count field matches the
+-01882                          * actual transfer length.
+-01883                          */
+-01884                         hc->multi_count = num_packets;
+-01885                 }
+-01886 
+-01887                 if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC)
+-01888                         set_pid_isoc(hc);
+-01889 
+-01890                 hctsiz.b.xfersize = hc->xfer_len;
+-01891         }
+-01892 
+-01893         hc->start_pkt_count = num_packets;
+-01894         hctsiz.b.pktcnt = num_packets;
+-01895         hctsiz.b.pid = hc->data_pid_start;
+-01896         dwc_write_reg32(&hc_regs->hctsiz, hctsiz.d32);
+-01897 
+-01898         DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num);
+-01899         DWC_DEBUGPL(DBG_HCDV, "  Xfer Size: %d\n", hctsiz.b.xfersize);
+-01900         DWC_DEBUGPL(DBG_HCDV, "  Num Pkts: %d\n", hctsiz.b.pktcnt);
+-01901         DWC_DEBUGPL(DBG_HCDV, "  Start PID: %d\n", hctsiz.b.pid);
+-01902 
+-01903         if (core_if->dma_enable) {
+-01904                 dwc_dma_t dma_addr;
+-01905                 if (hc->align_buff) {
+-01906                         dma_addr = hc->align_buff;
+-01907                 } else {
+-01908                         dma_addr = (uint32_t)hc->xfer_buff;
+-01909                 }
+-01910                 dwc_write_reg32(&hc_regs->hcdma, dma_addr);
+-01911         }
+-01912 
+-01913         /* Start the split */
+-01914         if (hc->do_split) {
+-01915                 hcsplt_data_t hcsplt;
+-01916                 hcsplt.d32 = dwc_read_reg32(&hc_regs->hcsplt);
+-01917                 hcsplt.b.spltena = 1;
+-01918                 dwc_write_reg32(&hc_regs->hcsplt, hcsplt.d32);
+-01919         }
+-01920 
+-01921         hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
+-01922         hcchar.b.multicnt = hc->multi_count;
+-01923         hc_set_even_odd_frame(core_if, hc, &hcchar);
+-01924 #ifdef DEBUG
+-01925         core_if->start_hcchar_val[hc->hc_num] = hcchar.d32;
+-01926         if (hcchar.b.chdis) {
+-01927                 DWC_WARN("%s: chdis set, channel %d, hcchar 0x%08x\n",
+-01928                          __func__, hc->hc_num, hcchar.d32);
+-01929         }
+-01930 #endif
+-01931 
+-01932         /* Set host channel enable after all other setup is complete. */
+-01933         hcchar.b.chen = 1;
+-01934         hcchar.b.chdis = 0;
+-01935         dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
+-01936 
+-01937         hc->xfer_started = 1;
+-01938         hc->requests++;
+-01939 
+-01940         if (!core_if->dma_enable && !hc->ep_is_in && hc->xfer_len > 0) {
+-01941                 /* Load OUT packet into the appropriate Tx FIFO. */
+-01942                 dwc_otg_hc_write_packet(core_if, hc);
+-01943         }
+-01944 #ifdef DEBUG
+-01945         if (hc->ep_type != DWC_OTG_EP_TYPE_INTR) {
+-01946                 core_if->hc_xfer_info[hc->hc_num].core_if = core_if;
+-01947                 core_if->hc_xfer_info[hc->hc_num].hc = hc;
+-01948                 /* Start a timer for this transfer. */
+-01949                 DWC_TIMER_SCHEDULE(core_if->hc_xfer_timer[hc->hc_num], 10000);
+-01950         }
+-01951 #endif
+-01952 }
+-01953 
+-01968 void dwc_otg_hc_start_transfer_ddma(dwc_otg_core_if_t * core_if, dwc_hc_t * hc)
+-01969 {
+-01970         dwc_otg_hc_regs_t *hc_regs = core_if->host_if->hc_regs[hc->hc_num];     
+-01971         hcchar_data_t hcchar;
+-01972         hctsiz_data_t hctsiz;
+-01973         hcdma_data_t  hcdma;
+-01974         
+-01975         hctsiz.d32 = 0;
+-01976 
+-01977         if (hc->do_ping && !hc->ep_is_in)
+-01978                 hctsiz.b_ddma.dopng = 1;
+-01979 
+-01980         if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC)
+-01981                 set_pid_isoc(hc);
+-01982         
+-01983         /* Packet Count and Xfer Size are not used in Descriptor DMA mode */
+-01984         hctsiz.b_ddma.pid = hc->data_pid_start;
+-01985         hctsiz.b_ddma.ntd = hc->ntd - 1; /* 0 - 1 descriptor, 1 - 2 descriptors, etc. */
+-01986         hctsiz.b_ddma.schinfo = hc->schinfo; /* Non-zero only for high-speed interrupt endpoints */
+-01987         
+-01988         DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num);
+-01989         DWC_DEBUGPL(DBG_HCDV, "  Start PID: %d\n", hctsiz.b.pid);
+-01990         DWC_DEBUGPL(DBG_HCDV, "  NTD: %d\n", hctsiz.b_ddma.ntd);        
+-01991 
+-01992         dwc_write_reg32(&hc_regs->hctsiz, hctsiz.d32);
+-01993 
+-01994         hcdma.d32 = 0;
+-01995         hcdma.b.dma_addr = ((uint32_t)hc->desc_list_addr) >> 11;
+-01996                 
+-01997         /* Always start from first descriptor. */
+-01998         hcdma.b.ctd = 0;
+-01999         dwc_write_reg32(&hc_regs->hcdma, hcdma.d32);
+-02000 
+-02001         hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
+-02002         hcchar.b.multicnt = hc->multi_count;
+-02003         
+-02004 #ifdef DEBUG
+-02005         core_if->start_hcchar_val[hc->hc_num] = hcchar.d32;
+-02006         if (hcchar.b.chdis) {
+-02007                 DWC_WARN("%s: chdis set, channel %d, hcchar 0x%08x\n",
+-02008                          __func__, hc->hc_num, hcchar.d32);
+-02009         }
+-02010 #endif
+-02011 
+-02012         /* Set host channel enable after all other setup is complete. */
+-02013         hcchar.b.chen = 1;
+-02014         hcchar.b.chdis = 0;
+-02015         
+-02016         dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
+-02017 
+-02018         hc->xfer_started = 1;
+-02019         hc->requests++;
+-02020         
+-02021 #ifdef DEBUG
+-02022         if ((hc->ep_type != DWC_OTG_EP_TYPE_INTR) && (hc->ep_type != DWC_OTG_EP_TYPE_ISOC)) {
+-02023                 core_if->hc_xfer_info[hc->hc_num].core_if = core_if;
+-02024                 core_if->hc_xfer_info[hc->hc_num].hc = hc;
+-02025                 /* Start a timer for this transfer. */
+-02026                 DWC_TIMER_SCHEDULE(core_if->hc_xfer_timer[hc->hc_num], 10000);
+-02027         }
+-02028 
+-02029 #endif
+-02030         
+-02031 }
+-02032         
+-02048 int dwc_otg_hc_continue_transfer(dwc_otg_core_if_t * core_if, dwc_hc_t * hc)
+-02049 {
+-02050         DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num);
+-02051 
+-02052         if (hc->do_split) {
+-02053                 /* SPLITs always queue just once per channel */
+-02054                 return 0;
+-02055         } else if (hc->data_pid_start == DWC_OTG_HC_PID_SETUP) {
+-02056                 /* SETUPs are queued only once since they can't be NAKed. */
+-02057                 return 0;
+-02058         } else if (hc->ep_is_in) {
+-02059                 /*
+-02060                  * Always queue another request for other IN transfers. If
+-02061                  * back-to-back INs are issued and NAKs are received for both,
+-02062                  * the driver may still be processing the first NAK when the
+-02063                  * second NAK is received. When the interrupt handler clears
+-02064                  * the NAK interrupt for the first NAK, the second NAK will
+-02065                  * not be seen. So we can't depend on the NAK interrupt
+-02066                  * handler to requeue a NAKed request. Instead, IN requests
+-02067                  * are issued each time this function is called. When the
+-02068                  * transfer completes, the extra requests for the channel will
+-02069                  * be flushed.
+-02070                  */
+-02071                 hcchar_data_t hcchar;
+-02072                 dwc_otg_hc_regs_t *hc_regs =
+-02073                     core_if->host_if->hc_regs[hc->hc_num];
+-02074 
+-02075                 hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
+-02076                 hc_set_even_odd_frame(core_if, hc, &hcchar);
+-02077                 hcchar.b.chen = 1;
+-02078                 hcchar.b.chdis = 0;
+-02079                 DWC_DEBUGPL(DBG_HCDV, "  IN xfer: hcchar = 0x%08x\n",
+-02080                             hcchar.d32);
+-02081                 dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
+-02082                 hc->requests++;
+-02083                 return 1;
+-02084         } else {
+-02085                 /* OUT transfers. */
+-02086                 if (hc->xfer_count < hc->xfer_len) {
+-02087                         if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
+-02088                             hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
+-02089                                 hcchar_data_t hcchar;
+-02090                                 dwc_otg_hc_regs_t *hc_regs;
+-02091                                 hc_regs = core_if->host_if->hc_regs[hc->hc_num];
+-02092                                 hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
+-02093                                 hc_set_even_odd_frame(core_if, hc, &hcchar);
+-02094                         }
+-02095 
+-02096                         /* Load OUT packet into the appropriate Tx FIFO. */
+-02097                         dwc_otg_hc_write_packet(core_if, hc);
+-02098                         hc->requests++;
+-02099                         return 1;
+-02100                 } else {
+-02101                         return 0;
+-02102                 }
+-02103         }
+-02104 }
+-02105 
+-02110 void dwc_otg_hc_do_ping(dwc_otg_core_if_t * core_if, dwc_hc_t * hc)
+-02111 {
+-02112         hcchar_data_t hcchar;
+-02113         hctsiz_data_t hctsiz;
+-02114         dwc_otg_hc_regs_t *hc_regs = core_if->host_if->hc_regs[hc->hc_num];
+-02115 
+-02116         DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num);
+-02117 
+-02118         hctsiz.d32 = 0;
+-02119         hctsiz.b.dopng = 1;
+-02120         hctsiz.b.pktcnt = 1;
+-02121         dwc_write_reg32(&hc_regs->hctsiz, hctsiz.d32);
+-02122 
+-02123         hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
+-02124         hcchar.b.chen = 1;
+-02125         hcchar.b.chdis = 0;
+-02126         dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
+-02127 }
+-02128 
+-02129 /*
+-02130  * This function writes a packet into the Tx FIFO associated with the Host
+-02131  * Channel. For a channel associated with a non-periodic EP, the non-periodic
+-02132  * Tx FIFO is written. For a channel associated with a periodic EP, the
+-02133  * periodic Tx FIFO is written. This function should only be called in Slave
+-02134  * mode.
+-02135  *
+-02136  * Upon return the xfer_buff and xfer_count fields in _hc are incremented by
+-02137  * then number of bytes written to the Tx FIFO.
+-02138  */
+-02139 void dwc_otg_hc_write_packet(dwc_otg_core_if_t * core_if, dwc_hc_t * hc)
+-02140 {
+-02141         uint32_t i;
+-02142         uint32_t remaining_count;
+-02143         uint32_t byte_count;
+-02144         uint32_t dword_count;
+-02145 
+-02146         uint32_t *data_buff = (uint32_t *) (hc->xfer_buff);
+-02147         uint32_t *data_fifo = core_if->data_fifo[hc->hc_num];
+-02148 
+-02149         remaining_count = hc->xfer_len - hc->xfer_count;
+-02150         if (remaining_count > hc->max_packet) {
+-02151                 byte_count = hc->max_packet;
+-02152         } else {
+-02153                 byte_count = remaining_count;
+-02154         }
+-02155 
+-02156         dword_count = (byte_count + 3) / 4;
+-02157 
+-02158         if ((((unsigned long)data_buff) & 0x3) == 0) {
+-02159                 /* xfer_buff is DWORD aligned. */
+-02160                 for (i = 0; i < dword_count; i++, data_buff++) {
+-02161                         dwc_write_reg32(data_fifo, *data_buff);
+-02162                 }
+-02163         } else {
+-02164                 /* xfer_buff is not DWORD aligned. */
+-02165                 for (i = 0; i < dword_count; i++, data_buff++) {
+-02166                         uint32_t data;
+-02167                         data =
+-02168                             (data_buff[0] | data_buff[1] << 8 | data_buff[2] <<
+-02169                              16 | data_buff[3] << 24);
+-02170                         dwc_write_reg32(data_fifo, data);
+-02171                 }
+-02172         }
+-02173 
+-02174         hc->xfer_count += byte_count;
+-02175         hc->xfer_buff += byte_count;
+-02176 }
+-02177 
+-02182 uint32_t dwc_otg_get_frame_number(dwc_otg_core_if_t * core_if)
+-02183 {
+-02184         dsts_data_t dsts;
+-02185         dsts.d32 = dwc_read_reg32(&core_if->dev_if->dev_global_regs->dsts);
+-02186 
+-02187         /* read current frame/microframe number from DSTS register */
+-02188         return dsts.b.soffn;
+-02189 }
+-02190 
+-02199 void dwc_otg_read_setup_packet(dwc_otg_core_if_t * core_if, uint32_t * dest)
+-02200 {
+-02201         /* Get the 8 bytes of a setup transaction data */
+-02202 
+-02203         /* Pop 2 DWORDS off the receive data FIFO into memory */
+-02204         dest[0] = dwc_read_reg32(core_if->data_fifo[0]);
+-02205         dest[1] = dwc_read_reg32(core_if->data_fifo[0]);
+-02206 }
+-02207 
+-02216 void dwc_otg_ep0_activate(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
+-02217 {
+-02218         dwc_otg_dev_if_t *dev_if = core_if->dev_if;
+-02219         dsts_data_t dsts;
+-02220         depctl_data_t diepctl;
+-02221         depctl_data_t doepctl;
+-02222         dctl_data_t dctl = {.d32 = 0 };
+-02223 
+-02224         /* Read the Device Status and Endpoint 0 Control registers */
+-02225         dsts.d32 = dwc_read_reg32(&dev_if->dev_global_regs->dsts);
+-02226         diepctl.d32 = dwc_read_reg32(&dev_if->in_ep_regs[0]->diepctl);
+-02227         doepctl.d32 = dwc_read_reg32(&dev_if->out_ep_regs[0]->doepctl);
+-02228 
+-02229         /* Set the MPS of the IN EP based on the enumeration speed */
+-02230         switch (dsts.b.enumspd) {
+-02231         case DWC_DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ:
+-02232         case DWC_DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ:
+-02233         case DWC_DSTS_ENUMSPD_FS_PHY_48MHZ:
+-02234                 diepctl.b.mps = DWC_DEP0CTL_MPS_64;
+-02235                 break;
+-02236         case DWC_DSTS_ENUMSPD_LS_PHY_6MHZ:
+-02237                 diepctl.b.mps = DWC_DEP0CTL_MPS_8;
+-02238                 break;
+-02239         }
+-02240 
+-02241         dwc_write_reg32(&dev_if->in_ep_regs[0]->diepctl, diepctl.d32);
+-02242 
+-02243         /* Enable OUT EP for receive */
+-02244         doepctl.b.epena = 1;
+-02245         dwc_write_reg32(&dev_if->out_ep_regs[0]->doepctl, doepctl.d32);
+-02246 
+-02247 #ifdef VERBOSE
+-02248         DWC_DEBUGPL(DBG_PCDV, "doepctl0=%0x\n",
+-02249                     dwc_read_reg32(&dev_if->out_ep_regs[0]->doepctl));
+-02250         DWC_DEBUGPL(DBG_PCDV, "diepctl0=%0x\n",
+-02251                     dwc_read_reg32(&dev_if->in_ep_regs[0]->diepctl));
+-02252 #endif
+-02253         dctl.b.cgnpinnak = 1;
+-02254 
+-02255         dwc_modify_reg32(&dev_if->dev_global_regs->dctl, dctl.d32, dctl.d32);
+-02256         DWC_DEBUGPL(DBG_PCDV, "dctl=%0x\n",
+-02257                     dwc_read_reg32(&dev_if->dev_global_regs->dctl));
+-02258 }
+-02259 
+-02268 void dwc_otg_ep_activate(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
+-02269 {
+-02270         dwc_otg_dev_if_t *dev_if = core_if->dev_if;
+-02271         depctl_data_t depctl;
+-02272         volatile uint32_t *addr;
+-02273         daint_data_t daintmsk = {.d32 = 0 };
+-02274 
+-02275         DWC_DEBUGPL(DBG_PCDV, "%s() EP%d-%s\n", __func__, ep->num,
+-02276                     (ep->is_in ? "IN" : "OUT"));
+-02277 
+-02278         /* Read DEPCTLn register */
+-02279         if (ep->is_in == 1) {
+-02280                 addr = &dev_if->in_ep_regs[ep->num]->diepctl;
+-02281                 daintmsk.ep.in = 1 << ep->num;
+-02282         } else {
+-02283                 addr = &dev_if->out_ep_regs[ep->num]->doepctl;
+-02284                 daintmsk.ep.out = 1 << ep->num;
+-02285         }
+-02286 
+-02287         /* If the EP is already active don't change the EP Control
+-02288          * register. */
+-02289         depctl.d32 = dwc_read_reg32(addr);
+-02290         if (!depctl.b.usbactep) {
+-02291                 depctl.b.mps = ep->maxpacket;
+-02292                 depctl.b.eptype = ep->type;
+-02293                 depctl.b.txfnum = ep->tx_fifo_num;
+-02294 
+-02295                 if (ep->type == DWC_OTG_EP_TYPE_ISOC) {
+-02296                         depctl.b.setd0pid = 1;  // ??? 
+-02297                 } else {
+-02298                         depctl.b.setd0pid = 1;
+-02299                 }
+-02300                 depctl.b.usbactep = 1;
+-02301 
+-02302                 dwc_write_reg32(addr, depctl.d32);
+-02303                 DWC_DEBUGPL(DBG_PCDV, "DEPCTL=%08x\n", dwc_read_reg32(addr));
+-02304         }
+-02305 
+-02306         /* Enable the Interrupt for this EP */
+-02307         if (core_if->multiproc_int_enable) {
+-02308                 if (ep->is_in == 1) {
+-02309                         diepmsk_data_t diepmsk = {.d32 = 0 };
+-02310                         diepmsk.b.xfercompl = 1;
+-02311                         diepmsk.b.timeout = 1;
+-02312                         diepmsk.b.epdisabled = 1;
+-02313                         diepmsk.b.ahberr = 1;
+-02314                         diepmsk.b.intknepmis = 1;
+-02315                         diepmsk.b.txfifoundrn = 1;      //?????
+-02316 
+-02317                         if (core_if->dma_desc_enable) {
+-02318                                 diepmsk.b.bna = 1;
+-02319                         }
+-02320 /*                      
+-02321                         if(core_if->dma_enable) {
+-02322                                 doepmsk.b.nak = 1;
+-02323                         }
+-02324 */
+-02325                         dwc_write_reg32(&dev_if->dev_global_regs->
+-02326                                         diepeachintmsk[ep->num], diepmsk.d32);
+-02327 
+-02328                 } else {
+-02329                         doepmsk_data_t doepmsk = {.d32 = 0 };
+-02330                         doepmsk.b.xfercompl = 1;
+-02331                         doepmsk.b.ahberr = 1;
+-02332                         doepmsk.b.epdisabled = 1;
+-02333 
+-02334                         if (core_if->dma_desc_enable) {
+-02335                                 doepmsk.b.bna = 1;
+-02336                         }
+-02337 /*                      
+-02338                         doepmsk.b.babble = 1;
+-02339                         doepmsk.b.nyet = 1;
+-02340                         doepmsk.b.nak = 1;
+-02341 */
+-02342                         dwc_write_reg32(&dev_if->dev_global_regs->
+-02343                                         doepeachintmsk[ep->num], doepmsk.d32);
+-02344                 }
+-02345                 dwc_modify_reg32(&dev_if->dev_global_regs->deachintmsk,
+-02346                                  0, daintmsk.d32);
+-02347         } else {
+-02348                 dwc_modify_reg32(&dev_if->dev_global_regs->daintmsk,
+-02349                                  0, daintmsk.d32);
+-02350         }
+-02351 
+-02352         DWC_DEBUGPL(DBG_PCDV, "DAINTMSK=%0x\n",
+-02353                     dwc_read_reg32(&dev_if->dev_global_regs->daintmsk));
+-02354 
+-02355         ep->stall_clear_flag = 0;
+-02356         return;
+-02357 }
+-02358 
+-02367 void dwc_otg_ep_deactivate(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
+-02368 {
+-02369         depctl_data_t depctl = {.d32 = 0 };
+-02370         volatile uint32_t *addr;
+-02371         daint_data_t daintmsk = {.d32 = 0 };
+-02372 
+-02373         /* Read DEPCTLn register */
+-02374         if (ep->is_in == 1) {
+-02375                 addr = &core_if->dev_if->in_ep_regs[ep->num]->diepctl;
+-02376                 daintmsk.ep.in = 1 << ep->num;
+-02377         } else {
+-02378                 addr = &core_if->dev_if->out_ep_regs[ep->num]->doepctl;
+-02379                 daintmsk.ep.out = 1 << ep->num;
+-02380         }
+-02381 
+-02382         depctl.d32 = dwc_read_reg32(addr);
+-02383 
+-02384         depctl.b.usbactep = 0;
+-02385 
+-02386         if (core_if->dma_desc_enable)
+-02387                 depctl.b.epdis = 1;
+-02388 
+-02389         dwc_write_reg32(addr, depctl.d32);
+-02390 
+-02391         /* Disable the Interrupt for this EP */
+-02392         if (core_if->multiproc_int_enable) {
+-02393                 dwc_modify_reg32(&core_if->dev_if->dev_global_regs->deachintmsk,
+-02394                                  daintmsk.d32, 0);
+-02395 
+-02396                 if (ep->is_in == 1) {
+-02397                         dwc_write_reg32(&core_if->dev_if->dev_global_regs->
+-02398                                         diepeachintmsk[ep->num], 0);
+-02399                 } else {
+-02400                         dwc_write_reg32(&core_if->dev_if->dev_global_regs->
+-02401                                         doepeachintmsk[ep->num], 0);
+-02402                 }
+-02403         } else {
+-02404                 dwc_modify_reg32(&core_if->dev_if->dev_global_regs->daintmsk,
+-02405                                  daintmsk.d32, 0);
+-02406         }
+-02407 }
+-02408 
+-02415 static void init_dma_desc_chain(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
+-02416 {
+-02417         dwc_otg_dev_dma_desc_t *dma_desc;
+-02418         uint32_t offset;
+-02419         uint32_t xfer_est;
+-02420         int i;
+-02421 
+-02422         ep->desc_cnt = (ep->total_len / ep->maxxfer) +
+-02423             ((ep->total_len % ep->maxxfer) ? 1 : 0);
+-02424         if (!ep->desc_cnt)
+-02425                 ep->desc_cnt = 1;
+-02426 
+-02427         dma_desc = ep->desc_addr;
+-02428         xfer_est = ep->total_len;
+-02429         offset = 0;
+-02430         for (i = 0; i < ep->desc_cnt; ++i) {
+-02432                 if (xfer_est > ep->maxxfer) {
+-02433                         dma_desc->status.b.bs = BS_HOST_BUSY;
+-02434                         dma_desc->status.b.l = 0;
+-02435                         dma_desc->status.b.ioc = 0;
+-02436                         dma_desc->status.b.sp = 0;
+-02437                         dma_desc->status.b.bytes = ep->maxxfer;
+-02438                         dma_desc->buf = ep->dma_addr + offset;
+-02439                         dma_desc->status.b.bs = BS_HOST_READY;
+-02440 
+-02441                         xfer_est -= ep->maxxfer;
+-02442                         offset += ep->maxxfer;
+-02443                 } else {
+-02444                         dma_desc->status.b.bs = BS_HOST_BUSY;
+-02445                         dma_desc->status.b.l = 1;
+-02446                         dma_desc->status.b.ioc = 1;
+-02447                         if (ep->is_in) {
+-02448                                 dma_desc->status.b.sp =
+-02449                                     (xfer_est %
+-02450                                      ep->maxpacket) ? 1 : ((ep->
+-02451                                                             sent_zlp) ? 1 : 0);
+-02452                                 dma_desc->status.b.bytes = xfer_est;
+-02453                         } else {
+-02454                                 dma_desc->status.b.bytes =
+-02455                                     xfer_est + ((4 - (xfer_est & 0x3)) & 0x3);
+-02456                         }
+-02457 
+-02458                         dma_desc->buf = ep->dma_addr + offset;
+-02459                         dma_desc->status.b.bs = BS_HOST_READY;
+-02460                 }
+-02461                 dma_desc++;
+-02462         }
+-02463 }
+-02464 
+-02475 void dwc_otg_ep_start_transfer(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
+-02476 {
+-02477         depctl_data_t depctl;
+-02478         deptsiz_data_t deptsiz;
+-02479         gintmsk_data_t intr_mask = {.d32 = 0 };
+-02480 
+-02481         DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "%s()\n", __func__);
+-02482         DWC_DEBUGPL(DBG_PCD, "ep%d-%s xfer_len=%d xfer_cnt=%d "
+-02483                     "xfer_buff=%p start_xfer_buff=%p, total_len = %d\n",
+-02484                     ep->num, (ep->is_in ? "IN" : "OUT"), ep->xfer_len,
+-02485                     ep->xfer_count, ep->xfer_buff, ep->start_xfer_buff,
+-02486                     ep->total_len);
+-02487         /* IN endpoint */
+-02488         if (ep->is_in == 1) {
+-02489                 dwc_otg_dev_in_ep_regs_t *in_regs =
+-02490                     core_if->dev_if->in_ep_regs[ep->num];
+-02491 
+-02492                 gnptxsts_data_t gtxstatus;
+-02493 
+-02494                 gtxstatus.d32 =
+-02495                     dwc_read_reg32(&core_if->core_global_regs->gnptxsts);
+-02496 
+-02497                 if (core_if->en_multiple_tx_fifo == 0
+-02498                     && gtxstatus.b.nptxqspcavail == 0) {
+-02499 #ifdef DEBUG
+-02500                         DWC_PRINTF("TX Queue Full (0x%0x)\n", gtxstatus.d32);
+-02501 #endif
+-02502                         return;
+-02503                 }
+-02504 
+-02505                 depctl.d32 = dwc_read_reg32(&(in_regs->diepctl));
+-02506                 deptsiz.d32 = dwc_read_reg32(&(in_regs->dieptsiz));
+-02507 
+-02508                 ep->xfer_len += (ep->maxxfer < (ep->total_len - ep->xfer_len)) ?
+-02509                     ep->maxxfer : (ep->total_len - ep->xfer_len);
+-02510 
+-02511                 /* Zero Length Packet? */
+-02512                 if ((ep->xfer_len - ep->xfer_count) == 0) {
+-02513                         deptsiz.b.xfersize = 0;
+-02514                         deptsiz.b.pktcnt = 1;
+-02515                 } else {
+-02516                         /* Program the transfer size and packet count
+-02517                          *      as follows: xfersize = N * maxpacket +
+-02518                          *      short_packet pktcnt = N + (short_packet
+-02519                          *      exist ? 1 : 0)  
+-02520                          */
+-02521                         deptsiz.b.xfersize = ep->xfer_len - ep->xfer_count;
+-02522                         deptsiz.b.pktcnt =
+-02523                             (ep->xfer_len - ep->xfer_count - 1 +
+-02524                              ep->maxpacket) / ep->maxpacket;
+-02525                 }
+-02526 
+-02527                 /* Write the DMA register */
+-02528                 if (core_if->dma_enable) {
+-02529                         if (core_if->dma_desc_enable == 0) {
+-02530                                 dwc_write_reg32(&in_regs->dieptsiz,
+-02531                                                 deptsiz.d32);
+-02532                                 dwc_write_reg32(&(in_regs->diepdma),
+-02533                                                 (uint32_t) ep->dma_addr);
+-02534                         } else {
+-02535 #ifdef DWC_UTE_CFI
+-02536                                 /* The descriptor chain should be already initialized by now */
+-02537                                 if (ep->buff_mode != BM_STANDARD) {
+-02538                                         dwc_write_reg32(&in_regs->diepdma,
+-02539                                                         ep->descs_dma_addr);
+-02540                                 } else {
+-02541 #endif
+-02542                                 init_dma_desc_chain(core_if, ep);
+-02544                                 dwc_write_reg32(&in_regs->diepdma,
+-02545                                                 ep->dma_desc_addr);
+-02546 #ifdef DWC_UTE_CFI
+-02547                         }
+-02548 #endif
+-02549                         }
+-02550                 } else {
+-02551                         dwc_write_reg32(&in_regs->dieptsiz, deptsiz.d32);
+-02552                         if (ep->type != DWC_OTG_EP_TYPE_ISOC) {
+-02558                                 if (core_if->en_multiple_tx_fifo == 0) {
+-02559                                         intr_mask.b.nptxfempty = 1;
+-02560                                         dwc_modify_reg32(&core_if->
+-02561                                                          core_global_regs->
+-02562                                                          gintmsk, intr_mask.d32,
+-02563                                                          intr_mask.d32);
+-02564                                 } else {
+-02565                                         /* Enable the Tx FIFO Empty Interrupt for this EP */
+-02566                                         if (ep->xfer_len > 0) {
+-02567                                                 uint32_t fifoemptymsk = 0;
+-02568                                                 fifoemptymsk = 1 << ep->num;
+-02569                                                 dwc_modify_reg32(&core_if->
+-02570                                                                  dev_if->
+-02571                                                                  dev_global_regs->
+-02572                                                                  dtknqr4_fifoemptymsk,
+-02573                                                                  0,
+-02574                                                                  fifoemptymsk);
+-02575 
+-02576                                         }
+-02577                                 }
+-02578                         }
+-02579                 }
+-02580 
+-02581                 /* EP enable, IN data in FIFO */
+-02582                 depctl.b.cnak = 1;
+-02583                 depctl.b.epena = 1;
+-02584                 dwc_write_reg32(&in_regs->diepctl, depctl.d32);
+-02585 
+-02586                 depctl.d32 =
+-02587                     dwc_read_reg32(&core_if->dev_if->in_ep_regs[0]->diepctl);
+-02588                 depctl.b.nextep = ep->num;
+-02589                 dwc_write_reg32(&core_if->dev_if->in_ep_regs[0]->diepctl,
+-02590                                 depctl.d32);
+-02591 
+-02592         } else {
+-02593                 /* OUT endpoint */
+-02594                 dwc_otg_dev_out_ep_regs_t *out_regs =
+-02595                     core_if->dev_if->out_ep_regs[ep->num];
+-02596 
+-02597                 depctl.d32 = dwc_read_reg32(&(out_regs->doepctl));
+-02598                 deptsiz.d32 = dwc_read_reg32(&(out_regs->doeptsiz));
+-02599 
+-02600                 ep->xfer_len += (ep->maxxfer < (ep->total_len - ep->xfer_len)) ?
+-02601                     ep->maxxfer : (ep->total_len - ep->xfer_len);
+-02602 
+-02603                 /* Program the transfer size and packet count as follows:
+-02604                  * 
+-02605                  *      pktcnt = N                                                                                 
+-02606                  *      xfersize = N * maxpacket
+-02607                  */
+-02608                 if ((ep->xfer_len - ep->xfer_count) == 0) {
+-02609                         /* Zero Length Packet */
+-02610                         deptsiz.b.xfersize = ep->maxpacket;
+-02611                         deptsiz.b.pktcnt = 1;
+-02612                 } else {
+-02613                         deptsiz.b.pktcnt =
+-02614                             (ep->xfer_len - ep->xfer_count +
+-02615                              (ep->maxpacket - 1)) / ep->maxpacket;
+-02616                         ep->xfer_len =
+-02617                             deptsiz.b.pktcnt * ep->maxpacket + ep->xfer_count;
+-02618                         deptsiz.b.xfersize = ep->xfer_len - ep->xfer_count;
+-02619                 }
+-02620 
+-02621                 DWC_DEBUGPL(DBG_PCDV, "ep%d xfersize=%d pktcnt=%d\n",
+-02622                             ep->num, deptsiz.b.xfersize, deptsiz.b.pktcnt);
+-02623 
+-02624                 if (core_if->dma_enable) {
+-02625                         if (!core_if->dma_desc_enable) {
+-02626                                 dwc_write_reg32(&out_regs->doeptsiz,
+-02627                                                 deptsiz.d32);
+-02628 
+-02629                                 dwc_write_reg32(&(out_regs->doepdma),
+-02630                                                 (uint32_t) ep->dma_addr);
+-02631                         } else {
+-02632 #ifdef DWC_UTE_CFI
+-02633                                 /* The descriptor chain should be already initialized by now */
+-02634                                 if (ep->buff_mode != BM_STANDARD) {
+-02635                                         dwc_write_reg32(&out_regs->doepdma,
+-02636                                                         ep->descs_dma_addr);
+-02637                                 } else {
+-02638 #endif
+-02639 
+-02640                                 init_dma_desc_chain(core_if, ep);
+-02641 
+-02643                                 dwc_write_reg32(&out_regs->doepdma,
+-02644                                                 ep->dma_desc_addr);
+-02645 #ifdef DWC_UTE_CFI
+-02646                                 }
+-02647 #endif
+-02648                         }
+-02649                 } else {
+-02650                         dwc_write_reg32(&out_regs->doeptsiz, deptsiz.d32);
+-02651                 }
+-02652 
+-02653                 /* EP enable */
+-02654                 depctl.b.cnak = 1;
+-02655                 depctl.b.epena = 1;
+-02656 
+-02657                 dwc_write_reg32(&out_regs->doepctl, depctl.d32);
+-02658 
+-02659                 DWC_DEBUGPL(DBG_PCD, "DOEPCTL=%08x DOEPTSIZ=%08x\n",
+-02660                             dwc_read_reg32(&out_regs->doepctl),
+-02661                             dwc_read_reg32(&out_regs->doeptsiz));
+-02662                 DWC_DEBUGPL(DBG_PCD, "DAINTMSK=%08x GINTMSK=%08x\n",
+-02663                             dwc_read_reg32(&core_if->dev_if->dev_global_regs->
+-02664                                            daintmsk),
+-02665                             dwc_read_reg32(&core_if->core_global_regs->
+-02666                                            gintmsk));
+-02667         }
+-02668 }
+-02669 
+-02678 void dwc_otg_ep_start_zl_transfer(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
+-02679 {
+-02680 
+-02681         depctl_data_t depctl;
+-02682         deptsiz_data_t deptsiz;
+-02683         gintmsk_data_t intr_mask = {.d32 = 0 };
+-02684 
+-02685         DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "%s()\n", __func__);
+-02686         DWC_PRINTF("zero length transfer is called\n");
+-02687 
+-02688         /* IN endpoint */
+-02689         if (ep->is_in == 1) {
+-02690                 dwc_otg_dev_in_ep_regs_t *in_regs =
+-02691                     core_if->dev_if->in_ep_regs[ep->num];
+-02692 
+-02693                 depctl.d32 = dwc_read_reg32(&(in_regs->diepctl));
+-02694                 deptsiz.d32 = dwc_read_reg32(&(in_regs->dieptsiz));
+-02695 
+-02696                 deptsiz.b.xfersize = 0;
+-02697                 deptsiz.b.pktcnt = 1;
+-02698 
+-02699                 /* Write the DMA register */
+-02700                 if (core_if->dma_enable) {
+-02701                         if (core_if->dma_desc_enable == 0) {
+-02702                                 dwc_write_reg32(&in_regs->dieptsiz,
+-02703                                                 deptsiz.d32);
+-02704                                 dwc_write_reg32(&(in_regs->diepdma),
+-02705                                                 (uint32_t) ep->dma_addr);
+-02706                         }
+-02707                 } else {
+-02708                         dwc_write_reg32(&in_regs->dieptsiz, deptsiz.d32);
+-02714                         if (core_if->en_multiple_tx_fifo == 0) {
+-02715                                 intr_mask.b.nptxfempty = 1;
+-02716                                 dwc_modify_reg32(&core_if->core_global_regs->
+-02717                                                  gintmsk, intr_mask.d32,
+-02718                                                  intr_mask.d32);
+-02719                         } else {
+-02720                                 /* Enable the Tx FIFO Empty Interrupt for this EP */
+-02721                                 if (ep->xfer_len > 0) {
+-02722                                         uint32_t fifoemptymsk = 0;
+-02723                                         fifoemptymsk = 1 << ep->num;
+-02724                                         dwc_modify_reg32(&core_if->dev_if->
+-02725                                                          dev_global_regs->
+-02726                                                          dtknqr4_fifoemptymsk,
+-02727                                                          0, fifoemptymsk);
+-02728                                 }
+-02729                         }
+-02730                 }
+-02731 
+-02732                 /* EP enable, IN data in FIFO */
+-02733                 depctl.b.cnak = 1;
+-02734                 depctl.b.epena = 1;
+-02735                 dwc_write_reg32(&in_regs->diepctl, depctl.d32);
+-02736 
+-02737                 depctl.d32 =
+-02738                     dwc_read_reg32(&core_if->dev_if->in_ep_regs[0]->diepctl);
+-02739                 depctl.b.nextep = ep->num;
+-02740                 dwc_write_reg32(&core_if->dev_if->in_ep_regs[0]->diepctl,
+-02741                                 depctl.d32);
+-02742 
+-02743         } else {
+-02744                 /* OUT endpoint */
+-02745                 dwc_otg_dev_out_ep_regs_t *out_regs =
+-02746                     core_if->dev_if->out_ep_regs[ep->num];
+-02747 
+-02748                 depctl.d32 = dwc_read_reg32(&(out_regs->doepctl));
+-02749                 deptsiz.d32 = dwc_read_reg32(&(out_regs->doeptsiz));
+-02750 
+-02751                 /* Zero Length Packet */
+-02752                 deptsiz.b.xfersize = ep->maxpacket;
+-02753                 deptsiz.b.pktcnt = 1;
+-02754 
+-02755                 if (core_if->dma_enable) {
+-02756                         if (!core_if->dma_desc_enable) {
+-02757                                 dwc_write_reg32(&out_regs->doeptsiz,
+-02758                                                 deptsiz.d32);
+-02759 
+-02760                                 dwc_write_reg32(&(out_regs->doepdma),
+-02761                                                 (uint32_t) ep->dma_addr);
+-02762                         }
+-02763                 } else {
+-02764                         dwc_write_reg32(&out_regs->doeptsiz, deptsiz.d32);
+-02765                 }
+-02766 
+-02767                 /* EP enable */
+-02768                 depctl.b.cnak = 1;
+-02769                 depctl.b.epena = 1;
+-02770 
+-02771                 dwc_write_reg32(&out_regs->doepctl, depctl.d32);
+-02772 
+-02773         }
+-02774 }
+-02775 
+-02785 void dwc_otg_ep0_start_transfer(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
+-02786 {
+-02787         depctl_data_t depctl;
+-02788         deptsiz0_data_t deptsiz;
+-02789         gintmsk_data_t intr_mask = {.d32 = 0 };
+-02790         dwc_otg_dev_dma_desc_t *dma_desc;
+-02791 
+-02792         DWC_DEBUGPL(DBG_PCD, "ep%d-%s xfer_len=%d xfer_cnt=%d "
+-02793                     "xfer_buff=%p start_xfer_buff=%p \n",
+-02794                     ep->num, (ep->is_in ? "IN" : "OUT"), ep->xfer_len,
+-02795                     ep->xfer_count, ep->xfer_buff, ep->start_xfer_buff);
+-02796 
+-02797         ep->total_len = ep->xfer_len;
+-02798 
+-02799         /* IN endpoint */
+-02800         if (ep->is_in == 1) {
+-02801                 dwc_otg_dev_in_ep_regs_t *in_regs =
+-02802                     core_if->dev_if->in_ep_regs[0];
+-02803 
+-02804                 gnptxsts_data_t gtxstatus;
+-02805 
+-02806                 gtxstatus.d32 =
+-02807                     dwc_read_reg32(&core_if->core_global_regs->gnptxsts);
+-02808 
+-02809                 if (core_if->en_multiple_tx_fifo == 0
+-02810                     && gtxstatus.b.nptxqspcavail == 0) {
+-02811 #ifdef DEBUG
+-02812                         deptsiz.d32 = dwc_read_reg32(&in_regs->dieptsiz);
+-02813                         DWC_DEBUGPL(DBG_PCD, "DIEPCTL0=%0x\n",
+-02814                                     dwc_read_reg32(&in_regs->diepctl));
+-02815                         DWC_DEBUGPL(DBG_PCD, "DIEPTSIZ0=%0x (sz=%d, pcnt=%d)\n",
+-02816                                     deptsiz.d32,
+-02817                                     deptsiz.b.xfersize, deptsiz.b.pktcnt);
+-02818                         DWC_PRINTF("TX Queue or FIFO Full (0x%0x)\n",
+-02819                                    gtxstatus.d32);
+-02820 #endif
+-02821                         return;
+-02822                 }
+-02823 
+-02824                 depctl.d32 = dwc_read_reg32(&in_regs->diepctl);
+-02825                 deptsiz.d32 = dwc_read_reg32(&in_regs->dieptsiz);
+-02826 
+-02827                 /* Zero Length Packet? */
+-02828                 if (ep->xfer_len == 0) {
+-02829                         deptsiz.b.xfersize = 0;
+-02830                         deptsiz.b.pktcnt = 1;
+-02831                 } else {
+-02832                         /* Program the transfer size and packet count
+-02833                          *      as follows: xfersize = N * maxpacket +
+-02834                          *      short_packet pktcnt = N + (short_packet
+-02835                          *      exist ? 1 : 0)  
+-02836                          */
+-02837                         if (ep->xfer_len > ep->maxpacket) {
+-02838                                 ep->xfer_len = ep->maxpacket;
+-02839                                 deptsiz.b.xfersize = ep->maxpacket;
+-02840                         } else {
+-02841                                 deptsiz.b.xfersize = ep->xfer_len;
+-02842                         }
+-02843                         deptsiz.b.pktcnt = 1;
+-02844 
+-02845                 }
+-02846                 DWC_DEBUGPL(DBG_PCDV,
+-02847                             "IN len=%d  xfersize=%d pktcnt=%d [%08x]\n",
+-02848                             ep->xfer_len, deptsiz.b.xfersize, deptsiz.b.pktcnt,
+-02849                             deptsiz.d32);
+-02850 
+-02851                 /* Write the DMA register */
+-02852                 if (core_if->dma_enable) {
+-02853                         if (core_if->dma_desc_enable == 0) {
+-02854                                 dwc_write_reg32(&in_regs->dieptsiz,
+-02855                                                 deptsiz.d32);
+-02856 
+-02857                                 dwc_write_reg32(&(in_regs->diepdma),
+-02858                                                 (uint32_t) ep->dma_addr);
+-02859                         } else {
+-02860                                 dma_desc = core_if->dev_if->in_desc_addr;
+-02861 
+-02863                                 dma_desc->status.b.bs = BS_HOST_BUSY;
+-02864                                 dma_desc->status.b.l = 1;
+-02865                                 dma_desc->status.b.ioc = 1;
+-02866                                 dma_desc->status.b.sp =
+-02867                                     (ep->xfer_len == ep->maxpacket) ? 0 : 1;
+-02868                                 dma_desc->status.b.bytes = ep->xfer_len;
+-02869                                 dma_desc->buf = ep->dma_addr;
+-02870                                 dma_desc->status.b.bs = BS_HOST_READY;
+-02871 
+-02873                                 dwc_write_reg32(&in_regs->diepdma,
+-02874                                                 core_if->dev_if->
+-02875                                                 dma_in_desc_addr);
+-02876                         }
+-02877                 } else {
+-02878                         dwc_write_reg32(&in_regs->dieptsiz, deptsiz.d32);
+-02879                 }
+-02880 
+-02881                 /* EP enable, IN data in FIFO */
+-02882                 depctl.b.cnak = 1;
+-02883                 depctl.b.epena = 1;
+-02884                 dwc_write_reg32(&in_regs->diepctl, depctl.d32);
+-02885 
+-02890                 if (!core_if->dma_enable) {
+-02891                         if (core_if->en_multiple_tx_fifo == 0) {
+-02892                                 intr_mask.b.nptxfempty = 1;
+-02893                                 dwc_modify_reg32(&core_if->core_global_regs->
+-02894                                                  gintmsk, intr_mask.d32,
+-02895                                                  intr_mask.d32);
+-02896                         } else {
+-02897                                 /* Enable the Tx FIFO Empty Interrupt for this EP */
+-02898                                 if (ep->xfer_len > 0) {
+-02899                                         uint32_t fifoemptymsk = 0;
+-02900                                         fifoemptymsk |= 1 << ep->num;
+-02901                                         dwc_modify_reg32(&core_if->dev_if->
+-02902                                                          dev_global_regs->
+-02903                                                          dtknqr4_fifoemptymsk,
+-02904                                                          0, fifoemptymsk);
+-02905                                 }
+-02906                         }
+-02907                 }
+-02908         } else {
+-02909                 /* OUT endpoint */
+-02910                 dwc_otg_dev_out_ep_regs_t *out_regs =
+-02911                     core_if->dev_if->out_ep_regs[0];
+-02912 
+-02913                 depctl.d32 = dwc_read_reg32(&out_regs->doepctl);
+-02914                 deptsiz.d32 = dwc_read_reg32(&out_regs->doeptsiz);
+-02915 
+-02916                 /* Program the transfer size and packet count as follows:
+-02917                  *      xfersize = N * (maxpacket + 4 - (maxpacket % 4))
+-02918                  *      pktcnt = N                                                                                      */
+-02919                 /* Zero Length Packet */
+-02920                 deptsiz.b.xfersize = ep->maxpacket;
+-02921                 deptsiz.b.pktcnt = 1;
+-02922 
+-02923                 DWC_DEBUGPL(DBG_PCDV, "len=%d  xfersize=%d pktcnt=%d\n",
+-02924                             ep->xfer_len, deptsiz.b.xfersize, deptsiz.b.pktcnt);
+-02925 
+-02926                 if (core_if->dma_enable) {
+-02927                         if (!core_if->dma_desc_enable) {
+-02928                                 dwc_write_reg32(&out_regs->doeptsiz,
+-02929                                                 deptsiz.d32);
+-02930 
+-02931                                 dwc_write_reg32(&(out_regs->doepdma),
+-02932                                                 (uint32_t) ep->dma_addr);
+-02933                         } else {
+-02934                                 dma_desc = core_if->dev_if->out_desc_addr;
+-02935 
+-02937                                 dma_desc->status.b.bs = BS_HOST_BUSY;
+-02938                                 dma_desc->status.b.l = 1;
+-02939                                 dma_desc->status.b.ioc = 1;
+-02940                                 dma_desc->status.b.bytes = ep->maxpacket;
+-02941                                 dma_desc->buf = ep->dma_addr;
+-02942                                 dma_desc->status.b.bs = BS_HOST_READY;
+-02943 
+-02945                                 dwc_write_reg32(&out_regs->doepdma,
+-02946                                                 core_if->dev_if->
+-02947                                                 dma_out_desc_addr);
+-02948                         }
+-02949                 } else {
+-02950                         dwc_write_reg32(&out_regs->doeptsiz, deptsiz.d32);
+-02951                 }
+-02952 
+-02953                 /* EP enable */
+-02954                 depctl.b.cnak = 1;
+-02955                 depctl.b.epena = 1;
+-02956                 dwc_write_reg32(&(out_regs->doepctl), depctl.d32);
+-02957         }
+-02958 }
+-02959 
+-02969 void dwc_otg_ep0_continue_transfer(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
+-02970 {
+-02971         depctl_data_t depctl;
+-02972         deptsiz0_data_t deptsiz;
+-02973         gintmsk_data_t intr_mask = {.d32 = 0 };
+-02974         dwc_otg_dev_dma_desc_t *dma_desc;
+-02975 
+-02976         if (ep->is_in == 1) {
+-02977                 dwc_otg_dev_in_ep_regs_t *in_regs =
+-02978                     core_if->dev_if->in_ep_regs[0];
+-02979                 gnptxsts_data_t tx_status = {.d32 = 0 };
+-02980 
+-02981                 tx_status.d32 =
+-02982                     dwc_read_reg32(&core_if->core_global_regs->gnptxsts);
+-02986                 depctl.d32 = dwc_read_reg32(&in_regs->diepctl);
+-02987                 deptsiz.d32 = dwc_read_reg32(&in_regs->dieptsiz);
+-02988 
+-02989                 /* Program the transfer size and packet count
+-02990                  *      as follows: xfersize = N * maxpacket +
+-02991                  *      short_packet pktcnt = N + (short_packet
+-02992                  *      exist ? 1 : 0)  
+-02993                  */
+-02994 
+-02995                 if (core_if->dma_desc_enable == 0) {
+-02996                         deptsiz.b.xfersize =
+-02997                             (ep->total_len - ep->xfer_count) >
+-02998                             ep->maxpacket ? ep->maxpacket : (ep->total_len -
+-02999                                                              ep->xfer_count);
+-03000                         deptsiz.b.pktcnt = 1;
+-03001                         if (core_if->dma_enable == 0) {
+-03002                                 ep->xfer_len += deptsiz.b.xfersize;
+-03003                         } else {
+-03004                                 ep->xfer_len = deptsiz.b.xfersize;
+-03005                         }
+-03006                         dwc_write_reg32(&in_regs->dieptsiz, deptsiz.d32);
+-03007                 } else {
+-03008                         ep->xfer_len =
+-03009                             (ep->total_len - ep->xfer_count) >
+-03010                             ep->maxpacket ? ep->maxpacket : (ep->total_len -
+-03011                                                              ep->xfer_count);
+-03012 
+-03013                         dma_desc = core_if->dev_if->in_desc_addr;
+-03014 
+-03016                         dma_desc->status.b.bs = BS_HOST_BUSY;
+-03017                         dma_desc->status.b.l = 1;
+-03018                         dma_desc->status.b.ioc = 1;
+-03019                         dma_desc->status.b.sp =
+-03020                             (ep->xfer_len == ep->maxpacket) ? 0 : 1;
+-03021                         dma_desc->status.b.bytes = ep->xfer_len;
+-03022                         dma_desc->buf = ep->dma_addr;
+-03023                         dma_desc->status.b.bs = BS_HOST_READY;
+-03024 
+-03026                         dwc_write_reg32(&in_regs->diepdma,
+-03027                                         core_if->dev_if->dma_in_desc_addr);
+-03028                 }
+-03029 
+-03030                 DWC_DEBUGPL(DBG_PCDV,
+-03031                             "IN len=%d  xfersize=%d pktcnt=%d [%08x]\n",
+-03032                             ep->xfer_len, deptsiz.b.xfersize, deptsiz.b.pktcnt,
+-03033                             deptsiz.d32);
+-03034 
+-03035                 /* Write the DMA register */
+-03036                 if (core_if->hwcfg2.b.architecture == DWC_INT_DMA_ARCH) {
+-03037                         if (core_if->dma_desc_enable == 0)
+-03038                                 dwc_write_reg32(&(in_regs->diepdma),
+-03039                                                 (uint32_t) ep->dma_addr);
+-03040                 }
+-03041 
+-03042                 /* EP enable, IN data in FIFO */
+-03043                 depctl.b.cnak = 1;
+-03044                 depctl.b.epena = 1;
+-03045                 dwc_write_reg32(&in_regs->diepctl, depctl.d32);
+-03046 
+-03051                 if (!core_if->dma_enable) {
+-03052                         if (core_if->en_multiple_tx_fifo == 0) {
+-03053                                 /* First clear it from GINTSTS */
+-03054                                 intr_mask.b.nptxfempty = 1;
+-03055                                 dwc_modify_reg32(&core_if->core_global_regs->
+-03056                                                  gintmsk, intr_mask.d32,
+-03057                                                  intr_mask.d32);
+-03058 
+-03059                         } else {
+-03060                                 /* Enable the Tx FIFO Empty Interrupt for this EP */
+-03061                                 if (ep->xfer_len > 0) {
+-03062                                         uint32_t fifoemptymsk = 0;
+-03063                                         fifoemptymsk |= 1 << ep->num;
+-03064                                         dwc_modify_reg32(&core_if->dev_if->
+-03065                                                          dev_global_regs->
+-03066                                                          dtknqr4_fifoemptymsk,
+-03067                                                          0, fifoemptymsk);
+-03068                                 }
+-03069                         }
+-03070                 }
+-03071         } else {
+-03072                 dwc_otg_dev_out_ep_regs_t *out_regs =
+-03073                     core_if->dev_if->out_ep_regs[0];
+-03074 
+-03075                 depctl.d32 = dwc_read_reg32(&out_regs->doepctl);
+-03076                 deptsiz.d32 = dwc_read_reg32(&out_regs->doeptsiz);
+-03077 
+-03078                 /* Program the transfer size and packet count
+-03079                  *      as follows: xfersize = N * maxpacket +
+-03080                  *      short_packet pktcnt = N + (short_packet
+-03081                  *      exist ? 1 : 0)  
+-03082                  */
+-03083                 deptsiz.b.xfersize = ep->maxpacket;
+-03084                 deptsiz.b.pktcnt = 1;
+-03085 
+-03086                 if (core_if->dma_desc_enable == 0) {
+-03087                         dwc_write_reg32(&out_regs->doeptsiz, deptsiz.d32);
+-03088                 } else {
+-03089                         dma_desc = core_if->dev_if->out_desc_addr;
+-03090 
+-03092                         dma_desc->status.b.bs = BS_HOST_BUSY;
+-03093                         dma_desc->status.b.l = 1;
+-03094                         dma_desc->status.b.ioc = 1;
+-03095                         dma_desc->status.b.bytes = ep->maxpacket;
+-03096                         dma_desc->buf = ep->dma_addr;
+-03097                         dma_desc->status.b.bs = BS_HOST_READY;
+-03098 
+-03100                         dwc_write_reg32(&out_regs->doepdma,
+-03101                                         core_if->dev_if->dma_out_desc_addr);
+-03102                 }
+-03103 
+-03104                 DWC_DEBUGPL(DBG_PCDV,
+-03105                             "IN len=%d  xfersize=%d pktcnt=%d [%08x]\n",
+-03106                             ep->xfer_len, deptsiz.b.xfersize, deptsiz.b.pktcnt,
+-03107                             deptsiz.d32);
+-03108 
+-03109                 /* Write the DMA register */
+-03110                 if (core_if->hwcfg2.b.architecture == DWC_INT_DMA_ARCH) {
+-03111                         if (core_if->dma_desc_enable == 0)
+-03112                                 dwc_write_reg32(&(out_regs->doepdma),
+-03113                                                 (uint32_t) ep->dma_addr);
+-03114                 }
+-03115 
+-03116                 /* EP enable, IN data in FIFO */
+-03117                 depctl.b.cnak = 1;
+-03118                 depctl.b.epena = 1;
+-03119                 dwc_write_reg32(&out_regs->doepctl, depctl.d32);
+-03120 
+-03121         }
+-03122 }
+-03123 
+-03124 #ifdef DEBUG
+-03125 void dump_msg(const u8 * buf, unsigned int length)
+-03126 {
+-03127         unsigned int start, num, i;
+-03128         char line[52], *p;
+-03129 
+-03130         if (length >= 512)
+-03131                 return;
+-03132         start = 0;
+-03133         while (length > 0) {
+-03134                 num = length < 16u ? length : 16u;
+-03135                 p = line;
+-03136                 for (i = 0; i < num; ++i) {
+-03137                         if (i == 8)
+-03138                                 *p++ = ' ';
+-03139                         DWC_SPRINTF(p, " %02x", buf[i]);
+-03140                         p += 3;
+-03141                 }
+-03142                 *p = 0;
+-03143                 DWC_PRINTF("%6x: %s\n", start, line);
+-03144                 buf += num;
+-03145                 start += num;
+-03146                 length -= num;
+-03147         }
+-03148 }
+-03149 #else
+-03150 static inline void dump_msg(const u8 * buf, unsigned int length)
+-03151 {
+-03152 }
+-03153 #endif
+-03154 
+-03165 void dwc_otg_ep_write_packet(dwc_otg_core_if_t * core_if, dwc_ep_t * ep,
+-03166                              int dma)
+-03167 {
+-03183         uint32_t i;
+-03184         uint32_t byte_count;
+-03185         uint32_t dword_count;
+-03186         uint32_t *fifo;
+-03187         uint32_t *data_buff = (uint32_t *) ep->xfer_buff;
+-03188 
+-03189         DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "%s(%p,%p)\n", __func__, core_if,
+-03190                     ep);
+-03191         if (ep->xfer_count >= ep->xfer_len) {
+-03192                 DWC_WARN("%s() No data for EP%d!!!\n", __func__, ep->num);
+-03193                 return;
+-03194         }
+-03195 
+-03196         /* Find the byte length of the packet either short packet or MPS */
+-03197         if ((ep->xfer_len - ep->xfer_count) < ep->maxpacket) {
+-03198                 byte_count = ep->xfer_len - ep->xfer_count;
+-03199         } else {
+-03200                 byte_count = ep->maxpacket;
+-03201         }
+-03202 
+-03203         /* Find the DWORD length, padded by extra bytes as neccessary if MPS
+-03204          * is not a multiple of DWORD */
+-03205         dword_count = (byte_count + 3) / 4;
+-03206 
+-03207 #ifdef VERBOSE
+-03208         dump_msg(ep->xfer_buff, byte_count);
+-03209 #endif
+-03210 
+-03214         fifo = core_if->data_fifo[ep->num];
+-03215 
+-03216         DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "fifo=%p buff=%p *p=%08x bc=%d\n",
+-03217                     fifo, data_buff, *data_buff, byte_count);
+-03218 
+-03219         if (!dma) {
+-03220                 for (i = 0; i < dword_count; i++, data_buff++) {
+-03221                         dwc_write_reg32(fifo, *data_buff);
+-03222                 }
+-03223         }
+-03224 
+-03225         ep->xfer_count += byte_count;
+-03226         ep->xfer_buff += byte_count;
+-03227         ep->dma_addr += byte_count;
+-03228 }
+-03229 
+-03236 void dwc_otg_ep_set_stall(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
+-03237 {
+-03238         depctl_data_t depctl;
+-03239         volatile uint32_t *depctl_addr;
+-03240 
+-03241         DWC_DEBUGPL(DBG_PCD, "%s ep%d-%s\n", __func__, ep->num,
+-03242                     (ep->is_in ? "IN" : "OUT"));
+-03243 
+-03244         if (ep->is_in == 1) {
+-03245                 depctl_addr = &(core_if->dev_if->in_ep_regs[ep->num]->diepctl);
+-03246                 depctl.d32 = dwc_read_reg32(depctl_addr);
+-03247 
+-03248                 /* set the disable and stall bits */
+-03249                 if (depctl.b.epena) {
+-03250                         depctl.b.epdis = 1;
+-03251                 }
+-03252                 depctl.b.stall = 1;
+-03253                 dwc_write_reg32(depctl_addr, depctl.d32);
+-03254         } else {
+-03255                 depctl_addr = &(core_if->dev_if->out_ep_regs[ep->num]->doepctl);
+-03256                 depctl.d32 = dwc_read_reg32(depctl_addr);
+-03257 
+-03258                 /* set the stall bit */
+-03259                 depctl.b.stall = 1;
+-03260                 dwc_write_reg32(depctl_addr, depctl.d32);
+-03261         }
+-03262 
+-03263         DWC_DEBUGPL(DBG_PCD, "DEPCTL=%0x\n", dwc_read_reg32(depctl_addr));
+-03264 
+-03265         return;
+-03266 }
+-03267 
+-03274 void dwc_otg_ep_clear_stall(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
+-03275 {
+-03276         depctl_data_t depctl;
+-03277         volatile uint32_t *depctl_addr;
+-03278 
+-03279         DWC_DEBUGPL(DBG_PCD, "%s ep%d-%s\n", __func__, ep->num,
+-03280                     (ep->is_in ? "IN" : "OUT"));
+-03281 
+-03282         if (ep->is_in == 1) {
+-03283                 depctl_addr = &(core_if->dev_if->in_ep_regs[ep->num]->diepctl);
+-03284         } else {
+-03285                 depctl_addr = &(core_if->dev_if->out_ep_regs[ep->num]->doepctl);
+-03286         }
+-03287 
+-03288         depctl.d32 = dwc_read_reg32(depctl_addr);
+-03289 
+-03290         /* clear the stall bits */
+-03291         depctl.b.stall = 0;
+-03292 
+-03293         /* 
+-03294          * USB Spec 9.4.5: For endpoints using data toggle, regardless
+-03295          * of whether an endpoint has the Halt feature set, a
+-03296          * ClearFeature(ENDPOINT_HALT) request always results in the
+-03297          * data toggle being reinitialized to DATA0.
+-03298          */
+-03299         if (ep->type == DWC_OTG_EP_TYPE_INTR ||
+-03300             ep->type == DWC_OTG_EP_TYPE_BULK) {
+-03301                 depctl.b.setd0pid = 1;  /* DATA0 */
+-03302         }
+-03303 
+-03304         dwc_write_reg32(depctl_addr, depctl.d32);
+-03305         DWC_DEBUGPL(DBG_PCD, "DEPCTL=%0x\n", dwc_read_reg32(depctl_addr));
+-03306         return;
+-03307 }
+-03308 
+-03317 void dwc_otg_read_packet(dwc_otg_core_if_t * core_if,
+-03318                          uint8_t * dest, uint16_t bytes)
+-03319 {
+-03320         int i;
+-03321         int word_count = (bytes + 3) / 4;
+-03322 
+-03323         volatile uint32_t *fifo = core_if->data_fifo[0];
+-03324         uint32_t *data_buff = (uint32_t *) dest;
+-03325 
+-03332         DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "%s(%p,%p,%d)\n", __func__,
+-03333                     core_if, dest, bytes);
+-03334 
+-03335         for (i = 0; i < word_count; i++, data_buff++) {
+-03336                 *data_buff = dwc_read_reg32(fifo);
+-03337         }
+-03338 
+-03339         return;
+-03340 }
+-03341 
+-03347 void dwc_otg_dump_dev_registers(dwc_otg_core_if_t * core_if)
+-03348 {
+-03349         int i;
+-03350         volatile uint32_t *addr;
+-03351 
+-03352         DWC_PRINTF("Device Global Registers\n");
+-03353         addr = &core_if->dev_if->dev_global_regs->dcfg;
+-03354         DWC_PRINTF("DCFG                 @0x%08X : 0x%08X\n", (uint32_t) addr,
+-03355                    dwc_read_reg32(addr));
+-03356         addr = &core_if->dev_if->dev_global_regs->dctl;
+-03357         DWC_PRINTF("DCTL                 @0x%08X : 0x%08X\n", (uint32_t) addr,
+-03358                    dwc_read_reg32(addr));
+-03359         addr = &core_if->dev_if->dev_global_regs->dsts;
+-03360         DWC_PRINTF("DSTS                 @0x%08X : 0x%08X\n", (uint32_t) addr,
+-03361                    dwc_read_reg32(addr));
+-03362         addr = &core_if->dev_if->dev_global_regs->diepmsk;
+-03363         DWC_PRINTF("DIEPMSK      @0x%08X : 0x%08X\n", (uint32_t) addr,
+-03364                    dwc_read_reg32(addr));
+-03365         addr = &core_if->dev_if->dev_global_regs->doepmsk;
+-03366         DWC_PRINTF("DOEPMSK      @0x%08X : 0x%08X\n", (uint32_t) addr,
+-03367                    dwc_read_reg32(addr));
+-03368         addr = &core_if->dev_if->dev_global_regs->daint;
+-03369         DWC_PRINTF("DAINT        @0x%08X : 0x%08X\n", (uint32_t) addr,
+-03370                    dwc_read_reg32(addr));
+-03371         addr = &core_if->dev_if->dev_global_regs->daintmsk;
+-03372         DWC_PRINTF("DAINTMSK     @0x%08X : 0x%08X\n", (uint32_t) addr,
+-03373                    dwc_read_reg32(addr));
+-03374         addr = &core_if->dev_if->dev_global_regs->dtknqr1;
+-03375         DWC_PRINTF("DTKNQR1      @0x%08X : 0x%08X\n", (uint32_t) addr,
+-03376                    dwc_read_reg32(addr));
+-03377         if (core_if->hwcfg2.b.dev_token_q_depth > 6) {
+-03378                 addr = &core_if->dev_if->dev_global_regs->dtknqr2;
+-03379                 DWC_PRINTF("DTKNQR2      @0x%08X : 0x%08X\n",
+-03380                            (uint32_t) addr, dwc_read_reg32(addr));
+-03381         }
+-03382 
+-03383         addr = &core_if->dev_if->dev_global_regs->dvbusdis;
+-03384         DWC_PRINTF("DVBUSID      @0x%08X : 0x%08X\n", (uint32_t) addr,
+-03385                    dwc_read_reg32(addr));
+-03386 
+-03387         addr = &core_if->dev_if->dev_global_regs->dvbuspulse;
+-03388         DWC_PRINTF("DVBUSPULSE  @0x%08X : 0x%08X\n",
+-03389                    (uint32_t) addr, dwc_read_reg32(addr));
+-03390 
+-03391                 addr = &core_if->dev_if->dev_global_regs->dtknqr3_dthrctl;
+-03392                 DWC_PRINTF("DTKNQR3_DTHRCTL      @0x%08X : 0x%08X\n",
+-03393                            (uint32_t) addr, dwc_read_reg32(addr));
+-03394 
+-03395         if (core_if->hwcfg2.b.dev_token_q_depth > 22) {
+-03396                 addr = &core_if->dev_if->dev_global_regs->dtknqr4_fifoemptymsk;
+-03397                 DWC_PRINTF("DTKNQR4      @0x%08X : 0x%08X\n",
+-03398                            (uint32_t) addr, dwc_read_reg32(addr));
+-03399         }
+-03400 
+-03401         addr = &core_if->dev_if->dev_global_regs->dtknqr4_fifoemptymsk;
+-03402         DWC_PRINTF("FIFOEMPMSK   @0x%08X : 0x%08X\n", (uint32_t) addr,
+-03403                    dwc_read_reg32(addr));
+-03404 
+-03405         addr = &core_if->dev_if->dev_global_regs->deachint;
+-03406         DWC_PRINTF("DEACHINT     @0x%08X : 0x%08X\n", (uint32_t) addr,
+-03407                    dwc_read_reg32(addr));
+-03408         addr = &core_if->dev_if->dev_global_regs->deachintmsk;
+-03409         DWC_PRINTF("DEACHINTMSK  @0x%08X : 0x%08X\n", (uint32_t) addr,
+-03410                    dwc_read_reg32(addr));
+-03411 
+-03412         for (i = 0; i <= core_if->dev_if->num_in_eps; i++) {
+-03413                 addr = &core_if->dev_if->dev_global_regs->diepeachintmsk[i];
+-03414                 DWC_PRINTF("DIEPEACHINTMSK[%d]   @0x%08X : 0x%08X\n", i,
+-03415                            (uint32_t) addr, dwc_read_reg32(addr));
+-03416         }
+-03417 
+-03418         for (i = 0; i <= core_if->dev_if->num_out_eps; i++) {
+-03419                 addr = &core_if->dev_if->dev_global_regs->doepeachintmsk[i];
+-03420                 DWC_PRINTF("DOEPEACHINTMSK[%d]   @0x%08X : 0x%08X\n", i,
+-03421                            (uint32_t) addr, dwc_read_reg32(addr));
+-03422         }
+-03423 
+-03424         for (i = 0; i <= core_if->dev_if->num_in_eps; i++) {
+-03425                 DWC_PRINTF("Device IN EP %d Registers\n", i);
+-03426                 addr = &core_if->dev_if->in_ep_regs[i]->diepctl;
+-03427                 DWC_PRINTF("DIEPCTL      @0x%08X : 0x%08X\n", (uint32_t) addr,
+-03428                            dwc_read_reg32(addr));
+-03429                 addr = &core_if->dev_if->in_ep_regs[i]->diepint;
+-03430                 DWC_PRINTF("DIEPINT      @0x%08X : 0x%08X\n", (uint32_t) addr,
+-03431                            dwc_read_reg32(addr));
+-03432                 addr = &core_if->dev_if->in_ep_regs[i]->dieptsiz;
+-03433                 DWC_PRINTF("DIETSIZ      @0x%08X : 0x%08X\n", (uint32_t) addr,
+-03434                            dwc_read_reg32(addr));
+-03435                 addr = &core_if->dev_if->in_ep_regs[i]->diepdma;
+-03436                 DWC_PRINTF("DIEPDMA      @0x%08X : 0x%08X\n", (uint32_t) addr,
+-03437                            dwc_read_reg32(addr));
+-03438                 addr = &core_if->dev_if->in_ep_regs[i]->dtxfsts;
+-03439                 DWC_PRINTF("DTXFSTS      @0x%08X : 0x%08X\n", (uint32_t) addr,
+-03440                            dwc_read_reg32(addr));
+-03441                 addr = &core_if->dev_if->in_ep_regs[i]->diepdmab;
+-03442                 DWC_PRINTF("DIEPDMAB     @0x%08X : 0x%08X\n", (uint32_t) addr,
+-03443                            0 /*dwc_read_reg32(addr) */ );
+-03444         }
+-03445 
+-03446         for (i = 0; i <= core_if->dev_if->num_out_eps; i++) {
+-03447                 DWC_PRINTF("Device OUT EP %d Registers\n", i);
+-03448                 addr = &core_if->dev_if->out_ep_regs[i]->doepctl;
+-03449                 DWC_PRINTF("DOEPCTL      @0x%08X : 0x%08X\n", (uint32_t) addr,
+-03450                            dwc_read_reg32(addr));
+-03451                 addr = &core_if->dev_if->out_ep_regs[i]->doepfn;
+-03452                 DWC_PRINTF("DOEPFN       @0x%08X : 0x%08X\n", (uint32_t) addr,
+-03453                            dwc_read_reg32(addr));
+-03454                 addr = &core_if->dev_if->out_ep_regs[i]->doepint;
+-03455                 DWC_PRINTF("DOEPINT      @0x%08X : 0x%08X\n", (uint32_t) addr,
+-03456                            dwc_read_reg32(addr));
+-03457                 addr = &core_if->dev_if->out_ep_regs[i]->doeptsiz;
+-03458                 DWC_PRINTF("DOETSIZ      @0x%08X : 0x%08X\n", (uint32_t) addr,
+-03459                            dwc_read_reg32(addr));
+-03460                 addr = &core_if->dev_if->out_ep_regs[i]->doepdma;
+-03461                 DWC_PRINTF("DOEPDMA      @0x%08X : 0x%08X\n", (uint32_t) addr,
+-03462                            dwc_read_reg32(addr));
+-03463                 if (core_if->dma_enable) {      /* Don't access this register in SLAVE mode */
+-03464                         addr = &core_if->dev_if->out_ep_regs[i]->doepdmab;
+-03465                         DWC_PRINTF("DOEPDMAB     @0x%08X : 0x%08X\n",
+-03466                                    (uint32_t) addr, dwc_read_reg32(addr));
+-03467                 }
+-03468 
+-03469         }
+-03470 }
+-03471 
+-03477 void dwc_otg_dump_spram(dwc_otg_core_if_t * core_if)
+-03478 {
+-03479         volatile uint8_t *addr, *start_addr, *end_addr;
+-03480 
+-03481         DWC_PRINTF("SPRAM Data:\n");
+-03482         start_addr = (void *)core_if->core_global_regs;
+-03483         DWC_PRINTF("Base Address: 0x%8X\n", (uint32_t) start_addr);
+-03484         start_addr += 0x00028000;
+-03485         end_addr = (void *)core_if->core_global_regs;
+-03486         end_addr += 0x000280e0;
+-03487 
+-03488         for (addr = start_addr; addr < end_addr; addr += 16) {
+-03489                 DWC_PRINTF
+-03490                     ("0x%8X:\t%2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X\n",
+-03491                      (uint32_t) addr, addr[0], addr[1], addr[2], addr[3],
+-03492                      addr[4], addr[5], addr[6], addr[7], addr[8], addr[9],
+-03493                      addr[10], addr[11], addr[12], addr[13], addr[14], addr[15]
+-03494                     );
+-03495         }
+-03496 
+-03497         return;
+-03498 }
+-03499 
+-03505 void dwc_otg_dump_host_registers(dwc_otg_core_if_t * core_if)
+-03506 {
+-03507         int i;
+-03508         volatile uint32_t *addr;
+-03509 
+-03510         DWC_PRINTF("Host Global Registers\n");
+-03511         addr = &core_if->host_if->host_global_regs->hcfg;
+-03512         DWC_PRINTF("HCFG                 @0x%08X : 0x%08X\n", (uint32_t) addr,
+-03513                    dwc_read_reg32(addr));
+-03514         addr = &core_if->host_if->host_global_regs->hfir;
+-03515         DWC_PRINTF("HFIR                 @0x%08X : 0x%08X\n", (uint32_t) addr,
+-03516                    dwc_read_reg32(addr));
+-03517         addr = &core_if->host_if->host_global_regs->hfnum;
+-03518         DWC_PRINTF("HFNUM        @0x%08X : 0x%08X\n", (uint32_t) addr,
+-03519                    dwc_read_reg32(addr));
+-03520         addr = &core_if->host_if->host_global_regs->hptxsts;
+-03521         DWC_PRINTF("HPTXSTS      @0x%08X : 0x%08X\n", (uint32_t) addr,
+-03522                    dwc_read_reg32(addr));
+-03523         addr = &core_if->host_if->host_global_regs->haint;
+-03524         DWC_PRINTF("HAINT        @0x%08X : 0x%08X\n", (uint32_t) addr,
+-03525                    dwc_read_reg32(addr));
+-03526         addr = &core_if->host_if->host_global_regs->haintmsk;
+-03527         DWC_PRINTF("HAINTMSK     @0x%08X : 0x%08X\n", (uint32_t) addr,
+-03528                    dwc_read_reg32(addr));
+-03529         if (core_if->dma_desc_enable) {
+-03530                 addr = &core_if->host_if->host_global_regs->hflbaddr;
+-03531                 DWC_PRINTF("HFLBADDR     @0x%08X : 0x%08X\n",(uint32_t) addr,
+-03532                            dwc_read_reg32(addr));
+-03533         }
+-03534         
+-03535         addr = core_if->host_if->hprt0;
+-03536         DWC_PRINTF("HPRT0        @0x%08X : 0x%08X\n", (uint32_t) addr,
+-03537                    dwc_read_reg32(addr));
+-03538 
+-03539         for (i = 0; i < core_if->core_params->host_channels; i++) {
+-03540                 DWC_PRINTF("Host Channel %d Specific Registers\n", i);
+-03541                 addr = &core_if->host_if->hc_regs[i]->hcchar;
+-03542                 DWC_PRINTF("HCCHAR       @0x%08X : 0x%08X\n", (uint32_t) addr,
+-03543                            dwc_read_reg32(addr));
+-03544                 addr = &core_if->host_if->hc_regs[i]->hcsplt;
+-03545                 DWC_PRINTF("HCSPLT       @0x%08X : 0x%08X\n", (uint32_t) addr,
+-03546                            dwc_read_reg32(addr));
+-03547                 addr = &core_if->host_if->hc_regs[i]->hcint;
+-03548                 DWC_PRINTF("HCINT        @0x%08X : 0x%08X\n", (uint32_t) addr,
+-03549                            dwc_read_reg32(addr));
+-03550                 addr = &core_if->host_if->hc_regs[i]->hcintmsk;
+-03551                 DWC_PRINTF("HCINTMSK     @0x%08X : 0x%08X\n", (uint32_t) addr,
+-03552                            dwc_read_reg32(addr));
+-03553                 addr = &core_if->host_if->hc_regs[i]->hctsiz;
+-03554                 DWC_PRINTF("HCTSIZ       @0x%08X : 0x%08X\n", (uint32_t) addr,
+-03555                            dwc_read_reg32(addr));
+-03556                 addr = &core_if->host_if->hc_regs[i]->hcdma;
+-03557                 DWC_PRINTF("HCDMA        @0x%08X : 0x%08X\n", (uint32_t) addr,
+-03558                            dwc_read_reg32(addr));
+-03559                 if (core_if->dma_desc_enable) {
+-03560                         addr=&core_if->host_if->hc_regs[i]->hcdmab;
+-03561                         DWC_PRINTF("HCDMAB       @0x%08X : 0x%08X\n",(uint32_t) addr, dwc_read_reg32(addr));
+-03562         }
+-03563 
+-03564         }
+-03565         return;
+-03566 }
+-03567 
+-03573 void dwc_otg_dump_global_registers(dwc_otg_core_if_t * core_if)
+-03574 {
+-03575         int i;
+-03576         volatile uint32_t *addr;
+-03577 
+-03578         DWC_PRINTF("Core Global Registers\n");
+-03579         addr = &core_if->core_global_regs->gotgctl;
+-03580         DWC_PRINTF("GOTGCTL      @0x%08X : 0x%08X\n", (uint32_t) addr,
+-03581                    dwc_read_reg32(addr));
+-03582         addr = &core_if->core_global_regs->gotgint;
+-03583         DWC_PRINTF("GOTGINT      @0x%08X : 0x%08X\n", (uint32_t) addr,
+-03584                    dwc_read_reg32(addr));
+-03585         addr = &core_if->core_global_regs->gahbcfg;
+-03586         DWC_PRINTF("GAHBCFG      @0x%08X : 0x%08X\n", (uint32_t) addr,
+-03587                    dwc_read_reg32(addr));
+-03588         addr = &core_if->core_global_regs->gusbcfg;
+-03589         DWC_PRINTF("GUSBCFG      @0x%08X : 0x%08X\n", (uint32_t) addr,
+-03590                    dwc_read_reg32(addr));
+-03591         addr = &core_if->core_global_regs->grstctl;
+-03592         DWC_PRINTF("GRSTCTL      @0x%08X : 0x%08X\n", (uint32_t) addr,
+-03593                    dwc_read_reg32(addr));
+-03594         addr = &core_if->core_global_regs->gintsts;
+-03595         DWC_PRINTF("GINTSTS      @0x%08X : 0x%08X\n", (uint32_t) addr,
+-03596                    dwc_read_reg32(addr));
+-03597         addr = &core_if->core_global_regs->gintmsk;
+-03598         DWC_PRINTF("GINTMSK      @0x%08X : 0x%08X\n", (uint32_t) addr,
+-03599                    dwc_read_reg32(addr));
+-03600         addr = &core_if->core_global_regs->grxstsr;
+-03601         DWC_PRINTF("GRXSTSR      @0x%08X : 0x%08X\n", (uint32_t) addr,
+-03602                    dwc_read_reg32(addr));
+-03603         addr = &core_if->core_global_regs->grxfsiz;
+-03604         DWC_PRINTF("GRXFSIZ      @0x%08X : 0x%08X\n", (uint32_t) addr,
+-03605                    dwc_read_reg32(addr));
+-03606         addr = &core_if->core_global_regs->gnptxfsiz;
+-03607         DWC_PRINTF("GNPTXFSIZ @0x%08X : 0x%08X\n", (uint32_t) addr,
+-03608                    dwc_read_reg32(addr));
+-03609         addr = &core_if->core_global_regs->gnptxsts;
+-03610         DWC_PRINTF("GNPTXSTS     @0x%08X : 0x%08X\n", (uint32_t) addr,
+-03611                    dwc_read_reg32(addr));
+-03612         addr = &core_if->core_global_regs->gi2cctl;
+-03613         DWC_PRINTF("GI2CCTL      @0x%08X : 0x%08X\n", (uint32_t) addr,
+-03614                    dwc_read_reg32(addr));
+-03615         addr = &core_if->core_global_regs->gpvndctl;
+-03616         DWC_PRINTF("GPVNDCTL     @0x%08X : 0x%08X\n", (uint32_t) addr,
+-03617                    dwc_read_reg32(addr));
+-03618         addr = &core_if->core_global_regs->ggpio;
+-03619         DWC_PRINTF("GGPIO        @0x%08X : 0x%08X\n", (uint32_t) addr,
+-03620                    dwc_read_reg32(addr));
+-03621         addr = &core_if->core_global_regs->guid;
+-03622         DWC_PRINTF("GUID                 @0x%08X : 0x%08X\n", (uint32_t) addr,
+-03623                    dwc_read_reg32(addr));
+-03624         addr = &core_if->core_global_regs->gsnpsid;
+-03625         DWC_PRINTF("GSNPSID      @0x%08X : 0x%08X\n", (uint32_t) addr,
+-03626                    dwc_read_reg32(addr));
+-03627         addr = &core_if->core_global_regs->ghwcfg1;
+-03628         DWC_PRINTF("GHWCFG1      @0x%08X : 0x%08X\n", (uint32_t) addr,
+-03629                    dwc_read_reg32(addr));
+-03630         addr = &core_if->core_global_regs->ghwcfg2;
+-03631         DWC_PRINTF("GHWCFG2      @0x%08X : 0x%08X\n", (uint32_t) addr,
+-03632                    dwc_read_reg32(addr));
+-03633         addr = &core_if->core_global_regs->ghwcfg3;
+-03634         DWC_PRINTF("GHWCFG3      @0x%08X : 0x%08X\n", (uint32_t) addr,
+-03635                    dwc_read_reg32(addr));
+-03636         addr = &core_if->core_global_regs->ghwcfg4;
+-03637         DWC_PRINTF("GHWCFG4      @0x%08X : 0x%08X\n", (uint32_t) addr,
+-03638                    dwc_read_reg32(addr));
+-03639         addr = &core_if->core_global_regs->glpmcfg;
+-03640         DWC_PRINTF("GLPMCFG      @0x%08X : 0x%08X\n", (uint32_t) addr,
+-03641                    dwc_read_reg32(addr));
+-03642         addr = &core_if->core_global_regs->hptxfsiz;
+-03643         DWC_PRINTF("HPTXFSIZ     @0x%08X : 0x%08X\n", (uint32_t) addr,
+-03644                    dwc_read_reg32(addr));
+-03645 
+-03646         for (i = 0; i < core_if->hwcfg4.b.num_dev_perio_in_ep; i++) {
+-03647                 addr = &core_if->core_global_regs->dptxfsiz_dieptxf[i];
+-03648                 DWC_PRINTF("DPTXFSIZ[%d] @0x%08X : 0x%08X\n", i,
+-03649                            (uint32_t) addr, dwc_read_reg32(addr));
+-03650         }
+-03651         addr = core_if->pcgcctl;
+-03652         DWC_PRINTF("PCGCCTL      @0x%08X : 0x%08X\n", (uint32_t) addr,
+-03653                    dwc_read_reg32(addr));
+-03654 }
+-03655 
+-03662 void dwc_otg_flush_tx_fifo(dwc_otg_core_if_t * core_if, const int num)
+-03663 {
+-03664         dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
+-03665         volatile grstctl_t greset = {.d32 = 0 };
+-03666         int count = 0;
+-03667 
+-03668         DWC_DEBUGPL((DBG_CIL | DBG_PCDV), "Flush Tx FIFO %d\n", num);
+-03669 
+-03670         greset.b.txfflsh = 1;
+-03671         greset.b.txfnum = num;
+-03672         dwc_write_reg32(&global_regs->grstctl, greset.d32);
+-03673 
+-03674         do {
+-03675                 greset.d32 = dwc_read_reg32(&global_regs->grstctl);
+-03676                 if (++count > 10000) {
+-03677                         DWC_WARN("%s() HANG! GRSTCTL=%0x GNPTXSTS=0x%08x\n",
+-03678                                  __func__, greset.d32,
+-03679                                  dwc_read_reg32(&global_regs->gnptxsts));
+-03680                         break;
+-03681                 }
+-03682                 dwc_udelay(1);
+-03683         } while (greset.b.txfflsh == 1);
+-03684 
+-03685         /* Wait for 3 PHY Clocks */
+-03686         dwc_udelay(1);
+-03687 }
+-03688 
+-03694 void dwc_otg_flush_rx_fifo(dwc_otg_core_if_t * core_if)
+-03695 {
+-03696         dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
+-03697         volatile grstctl_t greset = {.d32 = 0 };
+-03698         int count = 0;
+-03699 
+-03700         DWC_DEBUGPL((DBG_CIL | DBG_PCDV), "%s\n", __func__);
+-03701         /*
+-03702          * 
+-03703          */
+-03704         greset.b.rxfflsh = 1;
+-03705         dwc_write_reg32(&global_regs->grstctl, greset.d32);
+-03706 
+-03707         do {
+-03708                 greset.d32 = dwc_read_reg32(&global_regs->grstctl);
+-03709                 if (++count > 10000) {
+-03710                         DWC_WARN("%s() HANG! GRSTCTL=%0x\n", __func__,
+-03711                                  greset.d32);
+-03712                         break;
+-03713                 }
+-03714                 dwc_udelay(1);
+-03715         } while (greset.b.rxfflsh == 1);
+-03716 
+-03717         /* Wait for 3 PHY Clocks */
+-03718         dwc_udelay(1);
+-03719 }
+-03720 
+-03725 void dwc_otg_core_reset(dwc_otg_core_if_t * core_if)
+-03726 {
+-03727         dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
+-03728         volatile grstctl_t greset = {.d32 = 0 };
+-03729         int count = 0;
+-03730 
+-03731         DWC_DEBUGPL(DBG_CILV, "%s\n", __func__);
+-03732         /* Wait for AHB master IDLE state. */
+-03733         do {
+-03734                 dwc_udelay(10);
+-03735                 greset.d32 = dwc_read_reg32(&global_regs->grstctl);
+-03736                 if (++count > 100000) {
+-03737                         DWC_WARN("%s() HANG! AHB Idle GRSTCTL=%0x\n", __func__,
+-03738                                  greset.d32);
+-03739                         return;
+-03740                 }
+-03741         }
+-03742         while (greset.b.ahbidle == 0);
+-03743 
+-03744         /* Core Soft Reset */
+-03745         count = 0;
+-03746         greset.b.csftrst = 1;
+-03747         dwc_write_reg32(&global_regs->grstctl, greset.d32);
+-03748         do {
+-03749                 greset.d32 = dwc_read_reg32(&global_regs->grstctl);
+-03750                 if (++count > 10000) {
+-03751                         DWC_WARN("%s() HANG! Soft Reset GRSTCTL=%0x\n",
+-03752                                  __func__, greset.d32);
+-03753                         break;
+-03754                 }
+-03755                 dwc_udelay(1);
+-03756         }
+-03757         while (greset.b.csftrst == 1);
+-03758 
+-03759         /* Wait for 3 PHY Clocks */
+-03760         dwc_mdelay(100);
+-03761 }
+-03762 
+-03763 uint8_t dwc_otg_is_device_mode(dwc_otg_core_if_t * _core_if)
+-03764 {
+-03765         return (dwc_otg_mode(_core_if) != DWC_HOST_MODE);
+-03766 }
+-03767 
+-03768 uint8_t dwc_otg_is_host_mode(dwc_otg_core_if_t * _core_if)
+-03769 {
+-03770         return (dwc_otg_mode(_core_if) == DWC_HOST_MODE);
+-03771 }
+-03772 
+-03781 void dwc_otg_cil_register_hcd_callbacks(dwc_otg_core_if_t * core_if,
+-03782                                         dwc_otg_cil_callbacks_t * cb, void *p)
+-03783 {
+-03784         core_if->hcd_cb = cb;
+-03785         cb->p = p;
+-03786 }
+-03787 
+-03796 void dwc_otg_cil_register_pcd_callbacks(dwc_otg_core_if_t * core_if,
+-03797                                         dwc_otg_cil_callbacks_t * cb, void *p)
+-03798 {
+-03799         core_if->pcd_cb = cb;
+-03800         cb->p = p;
+-03801 }
+-03802 
+-03803 #ifdef DWC_EN_ISOC
+-03804 
+-03812 void write_isoc_frame_data(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
+-03813 {
+-03814         dwc_otg_dev_in_ep_regs_t *ep_regs;
+-03815         dtxfsts_data_t txstatus = {.d32 = 0 };
+-03816         uint32_t len = 0;
+-03817         uint32_t dwords;
+-03818 
+-03819         ep->xfer_len = ep->data_per_frame;
+-03820         ep->xfer_count = 0;
+-03821 
+-03822         ep_regs = core_if->dev_if->in_ep_regs[ep->num];
+-03823 
+-03824         len = ep->xfer_len - ep->xfer_count;
+-03825 
+-03826         if (len > ep->maxpacket) {
+-03827                 len = ep->maxpacket;
+-03828         }
+-03829 
+-03830         dwords = (len + 3) / 4;
+-03831 
+-03832         /* While there is space in the queue and space in the FIFO and
+-03833          * More data to tranfer, Write packets to the Tx FIFO */
+-03834         txstatus.d32 =
+-03835             dwc_read_reg32(&core_if->dev_if->in_ep_regs[ep->num]->dtxfsts);
+-03836         DWC_DEBUGPL(DBG_PCDV, "b4 dtxfsts[%d]=0x%08x\n", ep->num, txstatus.d32);
+-03837 
+-03838         while (txstatus.b.txfspcavail > dwords &&
+-03839                ep->xfer_count < ep->xfer_len && ep->xfer_len != 0) {
+-03840                 /* Write the FIFO */
+-03841                 dwc_otg_ep_write_packet(core_if, ep, 0);
+-03842 
+-03843                 len = ep->xfer_len - ep->xfer_count;
+-03844                 if (len > ep->maxpacket) {
+-03845                         len = ep->maxpacket;
+-03846                 }
+-03847 
+-03848                 dwords = (len + 3) / 4;
+-03849                 txstatus.d32 =
+-03850                     dwc_read_reg32(&core_if->dev_if->in_ep_regs[ep->num]->
+-03851                                    dtxfsts);
+-03852                 DWC_DEBUGPL(DBG_PCDV, "dtxfsts[%d]=0x%08x\n", ep->num,
+-03853                             txstatus.d32);
+-03854         }
+-03855 }
+-03856 
+-03864 void dwc_otg_iso_ep_start_frm_transfer(dwc_otg_core_if_t * core_if,
+-03865                                        dwc_ep_t * ep)
+-03866 {
+-03867         deptsiz_data_t deptsiz = {.d32 = 0 };
+-03868         depctl_data_t depctl = {.d32 = 0 };
+-03869         dsts_data_t dsts = {.d32 = 0 };
+-03870         volatile uint32_t *addr;
+-03871 
+-03872         if (ep->is_in) {
+-03873                 addr = &core_if->dev_if->in_ep_regs[ep->num]->diepctl;
+-03874         } else {
+-03875                 addr = &core_if->dev_if->out_ep_regs[ep->num]->doepctl;
+-03876         }
+-03877 
+-03878         ep->xfer_len = ep->data_per_frame;
+-03879         ep->xfer_count = 0;
+-03880         ep->xfer_buff = ep->cur_pkt_addr;
+-03881         ep->dma_addr = ep->cur_pkt_dma_addr;
+-03882 
+-03883         if (ep->is_in) {
+-03884                 /* Program the transfer size and packet count
+-03885                  *      as follows: xfersize = N * maxpacket +
+-03886                  *      short_packet pktcnt = N + (short_packet
+-03887                  *      exist ? 1 : 0)  
+-03888                  */
+-03889                 deptsiz.b.xfersize = ep->xfer_len;
+-03890                 deptsiz.b.pktcnt =
+-03891                     (ep->xfer_len - 1 + ep->maxpacket) / ep->maxpacket;
+-03892                 deptsiz.b.mc = deptsiz.b.pktcnt;
+-03893                 dwc_write_reg32(&core_if->dev_if->in_ep_regs[ep->num]->dieptsiz,
+-03894                                 deptsiz.d32);
+-03895 
+-03896                 /* Write the DMA register */
+-03897                 if (core_if->dma_enable) {
+-03898                         dwc_write_reg32(&
+-03899                                         (core_if->dev_if->in_ep_regs[ep->num]->
+-03900                                          diepdma), (uint32_t) ep->dma_addr);
+-03901                 }
+-03902         } else {
+-03903                 deptsiz.b.pktcnt =
+-03904                     (ep->xfer_len + (ep->maxpacket - 1)) / ep->maxpacket;
+-03905                 deptsiz.b.xfersize = deptsiz.b.pktcnt * ep->maxpacket;
+-03906 
+-03907                 dwc_write_reg32(&core_if->dev_if->out_ep_regs[ep->num]->
+-03908                                 doeptsiz, deptsiz.d32);
+-03909 
+-03910                 if (core_if->dma_enable) {
+-03911                         dwc_write_reg32(&
+-03912                                         (core_if->dev_if->out_ep_regs[ep->num]->
+-03913                                          doepdma), (uint32_t) ep->dma_addr);
+-03914                 }
+-03915         }
+-03916 
+-03919         depctl.d32 = 0;
+-03920         if (ep->bInterval == 1) {
+-03921                 dsts.d32 =
+-03922                     dwc_read_reg32(&core_if->dev_if->dev_global_regs->dsts);
+-03923                 ep->next_frame = dsts.b.soffn + ep->bInterval;
+-03924 
+-03925                 if (ep->next_frame & 0x1) {
+-03926                         depctl.b.setd1pid = 1;
+-03927                 } else {
+-03928                         depctl.b.setd0pid = 1;
+-03929                 }
+-03930         } else {
+-03931                 ep->next_frame += ep->bInterval;
+-03932 
+-03933                 if (ep->next_frame & 0x1) {
+-03934                         depctl.b.setd1pid = 1;
+-03935                 } else {
+-03936                         depctl.b.setd0pid = 1;
+-03937                 }
+-03938         }
+-03939         depctl.b.epena = 1;
+-03940         depctl.b.cnak = 1;
+-03941 
+-03942         dwc_modify_reg32(addr, 0, depctl.d32);
+-03943         depctl.d32 = dwc_read_reg32(addr);
+-03944 
+-03945         if (ep->is_in && core_if->dma_enable == 0) {
+-03946                 write_isoc_frame_data(core_if, ep);
+-03947         }
+-03948 
+-03949 }
+-03950 #endif                          /* DWC_EN_ISOC */
+-03951 
+-03952 static void dwc_otg_set_uninitialized(int32_t * p, int size)
+-03953 {
+-03954         int i;
+-03955         for (i = 0; i < size; i++) {
+-03956                 p[i] = -1;
+-03957         }
+-03958 }
+-03959 
+-03960 static int dwc_otg_param_initialized(int32_t val)
+-03961 {
+-03962         return val != -1;
+-03963 }
+-03964 
+-03965 static int dwc_otg_setup_params(dwc_otg_core_if_t * core_if)
+-03966 {
+-03967         int i;
+-03968         core_if->core_params = DWC_ALLOC(sizeof(*core_if->core_params));
+-03969         if (!core_if->core_params) {
+-03970                 return -DWC_E_NO_MEMORY;
+-03971         }
+-03972         dwc_otg_set_uninitialized((int32_t *) core_if->core_params,
+-03973                                   sizeof(*core_if->core_params) /
+-03974                                   sizeof(int32_t));
+-03975         DWC_PRINTF("Setting default values for core params\n");
+-03976         dwc_otg_set_param_otg_cap(core_if, dwc_param_otg_cap_default);
+-03977         dwc_otg_set_param_dma_enable(core_if, dwc_param_dma_enable_default);
+-03978         dwc_otg_set_param_dma_desc_enable(core_if,
+-03979                                           dwc_param_dma_desc_enable_default);
+-03980         dwc_otg_set_param_opt(core_if, dwc_param_opt_default);
+-03981         dwc_otg_set_param_dma_burst_size(core_if,
+-03982                                          dwc_param_dma_burst_size_default);
+-03983         dwc_otg_set_param_host_support_fs_ls_low_power(core_if,
+-03984                                                        dwc_param_host_support_fs_ls_low_power_default);
+-03985         dwc_otg_set_param_enable_dynamic_fifo(core_if,
+-03986                                               dwc_param_enable_dynamic_fifo_default);
+-03987         dwc_otg_set_param_data_fifo_size(core_if,
+-03988                                          dwc_param_data_fifo_size_default);
+-03989         dwc_otg_set_param_dev_rx_fifo_size(core_if,
+-03990                                            dwc_param_dev_rx_fifo_size_default);
+-03991         dwc_otg_set_param_dev_nperio_tx_fifo_size(core_if,
+-03992                                                   dwc_param_dev_nperio_tx_fifo_size_default);
+-03993         dwc_otg_set_param_host_rx_fifo_size(core_if,
+-03994                                             dwc_param_host_rx_fifo_size_default);
+-03995         dwc_otg_set_param_host_nperio_tx_fifo_size(core_if,
+-03996                                                    dwc_param_host_nperio_tx_fifo_size_default);
+-03997         dwc_otg_set_param_host_perio_tx_fifo_size(core_if,
+-03998                                                   dwc_param_host_perio_tx_fifo_size_default);
+-03999         dwc_otg_set_param_max_transfer_size(core_if,
+-04000                                             dwc_param_max_transfer_size_default);
+-04001         dwc_otg_set_param_max_packet_count(core_if,
+-04002                                            dwc_param_max_packet_count_default);
+-04003         dwc_otg_set_param_host_channels(core_if,
+-04004                                         dwc_param_host_channels_default);
+-04005         dwc_otg_set_param_dev_endpoints(core_if,
+-04006                                         dwc_param_dev_endpoints_default);
+-04007         dwc_otg_set_param_phy_type(core_if, dwc_param_phy_type_default);
+-04008         dwc_otg_set_param_speed(core_if, dwc_param_speed_default);
+-04009         dwc_otg_set_param_host_ls_low_power_phy_clk(core_if,
+-04010                                                     dwc_param_host_ls_low_power_phy_clk_default);
+-04011         dwc_otg_set_param_phy_ulpi_ddr(core_if, dwc_param_phy_ulpi_ddr_default);
+-04012         dwc_otg_set_param_phy_ulpi_ext_vbus(core_if,
+-04013                                             dwc_param_phy_ulpi_ext_vbus_default);
+-04014         dwc_otg_set_param_phy_utmi_width(core_if,
+-04015                                          dwc_param_phy_utmi_width_default);
+-04016         dwc_otg_set_param_ts_dline(core_if, dwc_param_ts_dline_default);
+-04017         dwc_otg_set_param_i2c_enable(core_if, dwc_param_i2c_enable_default);
+-04018         dwc_otg_set_param_ulpi_fs_ls(core_if, dwc_param_ulpi_fs_ls_default);
+-04019         dwc_otg_set_param_en_multiple_tx_fifo(core_if,
+-04020                                               dwc_param_en_multiple_tx_fifo_default);
+-04021         for (i = 0; i < 15; i++) {
+-04022                 dwc_otg_set_param_dev_perio_tx_fifo_size(core_if,
+-04023                                                          dwc_param_dev_perio_tx_fifo_size_default,
+-04024                                                          i);
+-04025         }
+-04026 
+-04027         for (i = 0; i < 15; i++) {
+-04028                 dwc_otg_set_param_dev_tx_fifo_size(core_if,
+-04029                                                    dwc_param_dev_tx_fifo_size_default,
+-04030                                                    i);
+-04031         }
+-04032         dwc_otg_set_param_thr_ctl(core_if, dwc_param_thr_ctl_default);
+-04033         dwc_otg_set_param_mpi_enable(core_if, dwc_param_mpi_enable_default);
+-04034         dwc_otg_set_param_pti_enable(core_if, dwc_param_pti_enable_default);
+-04035         dwc_otg_set_param_lpm_enable(core_if, dwc_param_lpm_enable_default);
+-04036         dwc_otg_set_param_ic_usb_cap(core_if, dwc_param_ic_usb_cap_default);
+-04037         dwc_otg_set_param_tx_thr_length(core_if,
+-04038                                         dwc_param_tx_thr_length_default);
+-04039         dwc_otg_set_param_rx_thr_length(core_if,
+-04040                                         dwc_param_rx_thr_length_default);
+-04041         dwc_otg_set_param_ahb_thr_ratio(core_if, dwc_param_ahb_thr_ratio_default);
+-04042         return 0;
+-04043 }
+-04044 
+-04045 uint8_t dwc_otg_is_dma_enable(dwc_otg_core_if_t * core_if)
+-04046 {
+-04047         return core_if->dma_enable;
+-04048 }
+-04049 
+-04050 /* Checks if the parameter is outside of its valid range of values */
+-04051 #define DWC_OTG_PARAM_TEST(_param_, _low_, _high_) \
+-04052                 (((_param_) < (_low_)) || \
+-04053                 ((_param_) > (_high_)))
+-04054 
+-04055 /* Parameter access functions */
+-04056 int dwc_otg_set_param_otg_cap(dwc_otg_core_if_t * core_if, int32_t val)
+-04057 {
+-04058         int valid;
+-04059         int retval = 0;
+-04060         if (DWC_OTG_PARAM_TEST(val, 0, 2)) {
+-04061                 DWC_WARN("Wrong value for otg_cap parameter\n");
+-04062                 DWC_WARN("otg_cap parameter must be 0,1 or 2\n");
+-04063                 retval = -DWC_E_INVALID;
+-04064                 goto out;
+-04065         }
+-04066 
+-04067         valid = 1;
+-04068         switch (val) {
+-04069         case DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE:
+-04070                 if (core_if->hwcfg2.b.op_mode !=
+-04071                     DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG)
+-04072                         valid = 0;
+-04073                 break;
+-04074         case DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE:
+-04075                 if ((core_if->hwcfg2.b.op_mode !=
+-04076                      DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG)
+-04077                     && (core_if->hwcfg2.b.op_mode !=
+-04078                         DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG)
+-04079                     && (core_if->hwcfg2.b.op_mode !=
+-04080                         DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE)
+-04081                     && (core_if->hwcfg2.b.op_mode !=
+-04082                       DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST)) {
+-04083                         valid = 0;
+-04084                 }
+-04085                 break;
+-04086         case DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE:
+-04087                 /* always valid */
+-04088                 break;
+-04089         }
+-04090         if (!valid) {
+-04091                 if (dwc_otg_param_initialized(core_if->core_params->otg_cap)) {
+-04092                         DWC_ERROR
+-04093                             ("%d invalid for otg_cap paremter. Check HW configuration.\n",
+-04094                              val);
+-04095                 }
+-04096                 val =
+-04097                     (((core_if->hwcfg2.b.op_mode ==
+-04098                        DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG)
+-04099                       || (core_if->hwcfg2.b.op_mode ==
+-04100                           DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG)
+-04101                       || (core_if->hwcfg2.b.op_mode ==
+-04102                           DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE)
+-04103                       || (core_if->hwcfg2.b.op_mode ==
+-04104                           DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST)) ?
+-04105                      DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE :
+-04106                      DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE);
+-04107                 retval = -DWC_E_INVALID;
+-04108         }
+-04109 
+-04110         core_if->core_params->otg_cap = val;
+-04111       out:
+-04112         return retval;
+-04113 }
+-04114 
+-04115 int32_t dwc_otg_get_param_otg_cap(dwc_otg_core_if_t * core_if)
+-04116 {
+-04117         return core_if->core_params->otg_cap;
+-04118 }
+-04119 
+-04120 int dwc_otg_set_param_opt(dwc_otg_core_if_t * core_if, int32_t val)
+-04121 {
+-04122         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
+-04123                 DWC_WARN("Wrong value for opt parameter\n");
+-04124                 return -DWC_E_INVALID;
+-04125         }
+-04126         core_if->core_params->opt = val;
+-04127         return 0;
+-04128 }
+-04129 
+-04130 int32_t dwc_otg_get_param_opt(dwc_otg_core_if_t * core_if)
+-04131 {
+-04132         return core_if->core_params->opt;
+-04133 }
+-04134 
+-04135 int dwc_otg_set_param_dma_enable(dwc_otg_core_if_t * core_if, int32_t val)
+-04136 {
+-04137         int retval = 0;
+-04138         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
+-04139                 DWC_WARN("Wrong value for dma enable\n");
+-04140                 return -DWC_E_INVALID;
+-04141         }
+-04142 
+-04143         if ((val == 1) && (core_if->hwcfg2.b.architecture == 0)) {
+-04144                 if (dwc_otg_param_initialized(core_if->core_params->dma_enable)) {
+-04145                         DWC_ERROR
+-04146                             ("%d invalid for dma_enable paremter. Check HW configuration.\n",
+-04147                              val);
+-04148                 }
+-04149                 val = 0;
+-04150                 retval = -DWC_E_INVALID;
+-04151         }
+-04152 
+-04153         core_if->core_params->dma_enable = val;
+-04154         if (val == 0) {
+-04155                 dwc_otg_set_param_dma_desc_enable(core_if, 0);
+-04156         }
+-04157         return retval;
+-04158 }
+-04159 
+-04160 int32_t dwc_otg_get_param_dma_enable(dwc_otg_core_if_t * core_if)
+-04161 {
+-04162         return core_if->core_params->dma_enable;
+-04163 }
+-04164 
+-04165 int dwc_otg_set_param_dma_desc_enable(dwc_otg_core_if_t * core_if, int32_t val)
+-04166 {
+-04167         int retval = 0;
+-04168         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
+-04169                 DWC_WARN("Wrong value for dma_enable\n");
+-04170                 DWC_WARN("dma_desc_enable must be 0 or 1\n");
+-04171                 return -DWC_E_INVALID;
+-04172         }
+-04173 
+-04174         if ((val == 1)
+-04175             && ((dwc_otg_get_param_dma_enable(core_if) == 0)
+-04176                 || (core_if->hwcfg4.b.desc_dma == 0))) {
+-04177                 if (dwc_otg_param_initialized
+-04178                     (core_if->core_params->dma_desc_enable)) {
+-04179                         DWC_ERROR
+-04180                             ("%d invalid for dma_desc_enable paremter. Check HW configuration.\n",
+-04181                              val);
+-04182                 }
+-04183                 val = 0;
+-04184                 retval = -DWC_E_INVALID;
+-04185         }
+-04186         core_if->core_params->dma_desc_enable = val;
+-04187         return retval;
+-04188 }
+-04189 
+-04190 int32_t dwc_otg_get_param_dma_desc_enable(dwc_otg_core_if_t * core_if)
+-04191 {
+-04192         return core_if->core_params->dma_desc_enable;
+-04193 }
+-04194 
+-04195 int dwc_otg_set_param_host_support_fs_ls_low_power(dwc_otg_core_if_t * core_if,
+-04196                                                    int32_t val)
+-04197 {
+-04198         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
+-04199                 DWC_WARN("Wrong value for host_support_fs_low_power\n");
+-04200                 DWC_WARN("host_support_fs_low_power must be 0 or 1\n");
+-04201                 return -DWC_E_INVALID;
+-04202         }
+-04203         core_if->core_params->host_support_fs_ls_low_power = val;
+-04204         return 0;
+-04205 }
+-04206 
+-04207 int32_t dwc_otg_get_param_host_support_fs_ls_low_power(dwc_otg_core_if_t *
+-04208                                                        core_if)
+-04209 {
+-04210         return core_if->core_params->host_support_fs_ls_low_power;
+-04211 }
+-04212 
+-04213 int dwc_otg_set_param_enable_dynamic_fifo(dwc_otg_core_if_t * core_if,
+-04214                                           int32_t val)
+-04215 {
+-04216         int retval = 0;
+-04217         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
+-04218                 DWC_WARN("Wrong value for enable_dynamic_fifo\n");
+-04219                 DWC_WARN("enable_dynamic_fifo must be 0 or 1\n");
+-04220                 return -DWC_E_INVALID;
+-04221         }
+-04222 
+-04223         if ((val == 1) && (core_if->hwcfg2.b.dynamic_fifo == 0)) {
+-04224                 if (dwc_otg_param_initialized
+-04225                     (core_if->core_params->enable_dynamic_fifo)) {
+-04226                         DWC_ERROR
+-04227                             ("%d invalid for enable_dynamic_fifo paremter. Check HW configuration.\n",
+-04228                              val);
+-04229                 }
+-04230                 val = 0;
+-04231                 retval = -DWC_E_INVALID;
+-04232         }
+-04233         core_if->core_params->enable_dynamic_fifo = val;
+-04234         return retval;
+-04235 }
+-04236 
+-04237 int32_t dwc_otg_get_param_enable_dynamic_fifo(dwc_otg_core_if_t * core_if)
+-04238 {
+-04239         return core_if->core_params->enable_dynamic_fifo;
+-04240 }
+-04241 
+-04242 int dwc_otg_set_param_data_fifo_size(dwc_otg_core_if_t * core_if, int32_t val)
+-04243 {
+-04244         int retval = 0;
+-04245         if (DWC_OTG_PARAM_TEST(val, 32, 32768)) {
+-04246                 DWC_WARN("Wrong value for data_fifo_size\n");
+-04247                 DWC_WARN("data_fifo_size must be 32-32768\n");
+-04248                 return -DWC_E_INVALID;
+-04249         }
+-04250 
+-04251         if (val > core_if->hwcfg3.b.dfifo_depth) {
+-04252                 if (dwc_otg_param_initialized
+-04253                     (core_if->core_params->data_fifo_size)) {
+-04254                         DWC_ERROR
+-04255                             ("%d invalid for data_fifo_size parameter. Check HW configuration.\n",
+-04256                              val);
+-04257                 }
+-04258                 val = core_if->hwcfg3.b.dfifo_depth;
+-04259                 retval = -DWC_E_INVALID;
+-04260         }
+-04261 
+-04262         core_if->core_params->data_fifo_size = val;
+-04263         return retval;
+-04264 }
+-04265 
+-04266 int32_t dwc_otg_get_param_data_fifo_size(dwc_otg_core_if_t * core_if)
+-04267 {
+-04268         return core_if->core_params->data_fifo_size;
+-04269 }
+-04270 
+-04271 int dwc_otg_set_param_dev_rx_fifo_size(dwc_otg_core_if_t * core_if, int32_t val)
+-04272 {
+-04273         int retval = 0;
+-04274         if (DWC_OTG_PARAM_TEST(val, 16, 32768)) {
+-04275                 DWC_WARN("Wrong value for dev_rx_fifo_size\n");
+-04276                 DWC_WARN("dev_rx_fifo_size must be 16-32768\n");
+-04277                 return -DWC_E_INVALID;
+-04278         }
+-04279 
+-04280         if (val > dwc_read_reg32(&core_if->core_global_regs->grxfsiz)) {
+-04281                 if(dwc_otg_param_initialized(core_if->core_params->dev_rx_fifo_size)) {
+-04282                 DWC_WARN("%d invalid for dev_rx_fifo_size parameter\n", val);
+-04283                 }
+-04284                 val = dwc_read_reg32(&core_if->core_global_regs->grxfsiz);
+-04285                 retval = -DWC_E_INVALID;
+-04286         }
+-04287 
+-04288         core_if->core_params->dev_rx_fifo_size = val;
+-04289         return retval;
+-04290 }
+-04291 
+-04292 int32_t dwc_otg_get_param_dev_rx_fifo_size(dwc_otg_core_if_t * core_if)
+-04293 {
+-04294         return core_if->core_params->dev_rx_fifo_size;
+-04295 }
+-04296 
+-04297 int dwc_otg_set_param_dev_nperio_tx_fifo_size(dwc_otg_core_if_t * core_if,
+-04298                                               int32_t val)
+-04299 {
+-04300         int retval = 0;
+-04301 
+-04302         if (DWC_OTG_PARAM_TEST(val, 16, 32768)) {
+-04303                 DWC_WARN("Wrong value for dev_nperio_tx_fifo\n");
+-04304                 DWC_WARN("dev_nperio_tx_fifo must be 16-32768\n");
+-04305                 return -DWC_E_INVALID;
+-04306         }
+-04307 
+-04308         if (val > (dwc_read_reg32(&core_if->core_global_regs->gnptxfsiz) >> 16)) {
+-04309                 if (dwc_otg_param_initialized
+-04310                     (core_if->core_params->dev_nperio_tx_fifo_size)) {
+-04311                         DWC_ERROR
+-04312                             ("%d invalid for dev_nperio_tx_fifo_size. Check HW configuration.\n",
+-04313                              val);
+-04314                 }
+-04315                 val =
+-04316                     (dwc_read_reg32(&core_if->core_global_regs->gnptxfsiz) >>
+-04317                      16);
+-04318                 retval = -DWC_E_INVALID;
+-04319         }
+-04320 
+-04321         core_if->core_params->dev_nperio_tx_fifo_size = val;
+-04322         return retval;
+-04323 }
+-04324 
+-04325 int32_t dwc_otg_get_param_dev_nperio_tx_fifo_size(dwc_otg_core_if_t * core_if)
+-04326 {
+-04327         return core_if->core_params->dev_nperio_tx_fifo_size;
+-04328 }
+-04329 
+-04330 int dwc_otg_set_param_host_rx_fifo_size(dwc_otg_core_if_t * core_if,
+-04331                                         int32_t val)
+-04332 {
+-04333         int retval = 0;
+-04334 
+-04335         if (DWC_OTG_PARAM_TEST(val, 16, 32768)) {
+-04336                 DWC_WARN("Wrong value for host_rx_fifo_size\n");
+-04337                 DWC_WARN("host_rx_fifo_size must be 16-32768\n");
+-04338                 return -DWC_E_INVALID;
+-04339         }
+-04340 
+-04341         if (val > dwc_read_reg32(&core_if->core_global_regs->grxfsiz)) {
+-04342                 if (dwc_otg_param_initialized
+-04343                     (core_if->core_params->host_rx_fifo_size)) {
+-04344                         DWC_ERROR
+-04345                             ("%d invalid for host_rx_fifo_size. Check HW configuration.\n",
+-04346                              val);
+-04347                 }
+-04348                 val = dwc_read_reg32(&core_if->core_global_regs->grxfsiz);
+-04349                 retval = -DWC_E_INVALID;
+-04350         }
+-04351 
+-04352         core_if->core_params->host_rx_fifo_size = val;
+-04353         return retval;
+-04354 
+-04355 }
+-04356 
+-04357 int32_t dwc_otg_get_param_host_rx_fifo_size(dwc_otg_core_if_t * core_if)
+-04358 {
+-04359         return core_if->core_params->host_rx_fifo_size;
+-04360 }
+-04361 
+-04362 int dwc_otg_set_param_host_nperio_tx_fifo_size(dwc_otg_core_if_t * core_if,
+-04363                                                int32_t val)
+-04364 {
+-04365         int retval = 0;
+-04366 
+-04367         if (DWC_OTG_PARAM_TEST(val, 16, 32768)) {
+-04368                 DWC_WARN("Wrong value for host_nperio_tx_fifo_size\n");
+-04369                 DWC_WARN("host_nperio_tx_fifo_size must be 16-32768\n");
+-04370                 return -DWC_E_INVALID;
+-04371         }
+-04372 
+-04373         if (val > (dwc_read_reg32(&core_if->core_global_regs->gnptxfsiz) >> 16)) {
+-04374                 if (dwc_otg_param_initialized
+-04375                     (core_if->core_params->host_nperio_tx_fifo_size)) {
+-04376                         DWC_ERROR
+-04377                             ("%d invalid for host_nperio_tx_fifo_size. Check HW configuration.\n",
+-04378                              val);
+-04379                 }
+-04380                 val =
+-04381                     (dwc_read_reg32(&core_if->core_global_regs->gnptxfsiz) >>
+-04382                      16);
+-04383                 retval = -DWC_E_INVALID;
+-04384         }
+-04385 
+-04386         core_if->core_params->host_nperio_tx_fifo_size = val;
+-04387         return retval;
+-04388 }
+-04389 
+-04390 int32_t dwc_otg_get_param_host_nperio_tx_fifo_size(dwc_otg_core_if_t * core_if)
+-04391 {
+-04392         return core_if->core_params->host_nperio_tx_fifo_size;
+-04393 }
+-04394 
+-04395 int dwc_otg_set_param_host_perio_tx_fifo_size(dwc_otg_core_if_t * core_if,
+-04396                                               int32_t val)
+-04397 {
+-04398         int retval = 0;
+-04399         if (DWC_OTG_PARAM_TEST(val, 16, 32768)) {
+-04400                 DWC_WARN("Wrong value for host_perio_tx_fifo_size\n");
+-04401                 DWC_WARN("host_perio_tx_fifo_size must be 16-32768\n");
+-04402                 return -DWC_E_INVALID;
+-04403         }
+-04404 
+-04405         if (val >
+-04406             ((dwc_read_reg32(&core_if->core_global_regs->hptxfsiz) >> 16))) {
+-04407                 if (dwc_otg_param_initialized
+-04408                     (core_if->core_params->host_perio_tx_fifo_size)) {
+-04409                         DWC_ERROR
+-04410                             ("%d invalid for host_perio_tx_fifo_size. Check HW configuration.\n",
+-04411                              val);
+-04412                 }
+-04413                 val =
+-04414                     (dwc_read_reg32(&core_if->core_global_regs->hptxfsiz) >>
+-04415                      16);
+-04416                 retval = -DWC_E_INVALID;
+-04417         }
+-04418 
+-04419         core_if->core_params->host_perio_tx_fifo_size = val;
+-04420         return retval;
+-04421 }
+-04422 
+-04423 int32_t dwc_otg_get_param_host_perio_tx_fifo_size(dwc_otg_core_if_t * core_if)
+-04424 {
+-04425         return core_if->core_params->host_perio_tx_fifo_size;
+-04426 }
+-04427 
+-04428 int dwc_otg_set_param_max_transfer_size(dwc_otg_core_if_t * core_if,
+-04429                                         int32_t val)
+-04430 {
+-04431         int retval = 0;
+-04432 
+-04433         if (DWC_OTG_PARAM_TEST(val, 2047, 524288)) {
+-04434                 DWC_WARN("Wrong value for max_transfer_size\n");
+-04435                 DWC_WARN("max_transfer_size must be 2047-524288\n");
+-04436                 return -DWC_E_INVALID;
+-04437         }
+-04438 
+-04439         if (val >= (1 << (core_if->hwcfg3.b.xfer_size_cntr_width + 11))) {
+-04440                 if (dwc_otg_param_initialized
+-04441                     (core_if->core_params->max_transfer_size)) {
+-04442                         DWC_ERROR
+-04443                             ("%d invalid for max_transfer_size. Check HW configuration.\n",
+-04444                              val);
+-04445                 }
+-04446                 val =
+-04447                     ((1 << (core_if->hwcfg3.b.packet_size_cntr_width + 11)) -
+-04448                      1);
+-04449                 retval = -DWC_E_INVALID;
+-04450         }
+-04451 
+-04452         core_if->core_params->max_transfer_size = val;
+-04453         return retval;
+-04454 }
+-04455 
+-04456 int32_t dwc_otg_get_param_max_transfer_size(dwc_otg_core_if_t * core_if)
+-04457 {
+-04458         return core_if->core_params->max_transfer_size;
+-04459 }
+-04460 
+-04461 int dwc_otg_set_param_max_packet_count(dwc_otg_core_if_t * core_if, int32_t val)
+-04462 {
+-04463         int retval = 0;
+-04464 
+-04465         if (DWC_OTG_PARAM_TEST(val, 15, 511)) {
+-04466                 DWC_WARN("Wrong value for max_packet_count\n");
+-04467                 DWC_WARN("max_packet_count must be 15-511\n");
+-04468                 return -DWC_E_INVALID;
+-04469         }
+-04470 
+-04471         if (val > (1 << (core_if->hwcfg3.b.packet_size_cntr_width + 4))) {
+-04472                 if (dwc_otg_param_initialized
+-04473                     (core_if->core_params->max_packet_count)) {
+-04474                         DWC_ERROR
+-04475                             ("%d invalid for max_packet_count. Check HW configuration.\n",
+-04476                              val);
+-04477                 }
+-04478                 val =
+-04479                     ((1 << (core_if->hwcfg3.b.packet_size_cntr_width + 4)) - 1);
+-04480                 retval = -DWC_E_INVALID;
+-04481         }
+-04482 
+-04483         core_if->core_params->max_packet_count = val;
+-04484         return retval;
+-04485 }
+-04486 
+-04487 int32_t dwc_otg_get_param_max_packet_count(dwc_otg_core_if_t * core_if)
+-04488 {
+-04489         return core_if->core_params->max_packet_count;
+-04490 }
+-04491 
+-04492 int dwc_otg_set_param_host_channels(dwc_otg_core_if_t * core_if, int32_t val)
+-04493 {
+-04494         int retval = 0;
+-04495 
+-04496         if (DWC_OTG_PARAM_TEST(val, 1, 16)) {
+-04497                 DWC_WARN("Wrong value for host_channels\n");
+-04498                 DWC_WARN("host_channels must be 1-16\n");
+-04499                 return -DWC_E_INVALID;
+-04500         }
+-04501 
+-04502         if (val > (core_if->hwcfg2.b.num_host_chan + 1)) {
+-04503                 if (dwc_otg_param_initialized
+-04504                     (core_if->core_params->host_channels)) {
+-04505                         DWC_ERROR
+-04506                             ("%d invalid for host_channels. Check HW configurations.\n",
+-04507                              val);
+-04508                 }
+-04509                 val = (core_if->hwcfg2.b.num_host_chan + 1);
+-04510                 retval = -DWC_E_INVALID;
+-04511         }
+-04512 
+-04513         core_if->core_params->host_channels = val;
+-04514         return retval;
+-04515 }
+-04516 
+-04517 int32_t dwc_otg_get_param_host_channels(dwc_otg_core_if_t * core_if)
+-04518 {
+-04519         return core_if->core_params->host_channels;
+-04520 }
+-04521 
+-04522 int dwc_otg_set_param_dev_endpoints(dwc_otg_core_if_t * core_if, int32_t val)
+-04523 {
+-04524         int retval = 0;
+-04525 
+-04526         if (DWC_OTG_PARAM_TEST(val, 1, 15)) {
+-04527                 DWC_WARN("Wrong value for dev_endpoints\n");
+-04528                 DWC_WARN("dev_endpoints must be 1-15\n");
+-04529                 return -DWC_E_INVALID;
+-04530         }
+-04531 
+-04532         if (val > (core_if->hwcfg2.b.num_dev_ep)) {
+-04533                 if (dwc_otg_param_initialized
+-04534                     (core_if->core_params->dev_endpoints)) {
+-04535                         DWC_ERROR
+-04536                             ("%d invalid for dev_endpoints. Check HW configurations.\n",
+-04537                              val);
+-04538                 }
+-04539                 val = core_if->hwcfg2.b.num_dev_ep;
+-04540                 retval = -DWC_E_INVALID;
+-04541         }
+-04542 
+-04543         core_if->core_params->dev_endpoints = val;
+-04544         return retval;
+-04545 }
+-04546 
+-04547 int32_t dwc_otg_get_param_dev_endpoints(dwc_otg_core_if_t * core_if)
+-04548 {
+-04549         return core_if->core_params->dev_endpoints;
+-04550 }
+-04551 
+-04552 int dwc_otg_set_param_phy_type(dwc_otg_core_if_t * core_if, int32_t val)
+-04553 {
+-04554         int retval = 0;
+-04555         int valid = 0;
+-04556 
+-04557         if (DWC_OTG_PARAM_TEST(val, 0, 2)) {
+-04558                 DWC_WARN("Wrong value for phy_type\n");
+-04559                 DWC_WARN("phy_type must be 0,1 or 2\n");
+-04560                 return -DWC_E_INVALID;
+-04561         }
+-04562 #ifndef NO_FS_PHY_HW_CHECKS
+-04563         if ((val == DWC_PHY_TYPE_PARAM_UTMI) &&
+-04564             ((core_if->hwcfg2.b.hs_phy_type == 1) ||
+-04565              (core_if->hwcfg2.b.hs_phy_type == 3))) {
+-04566                 valid = 1;
+-04567         } else if ((val == DWC_PHY_TYPE_PARAM_ULPI) &&
+-04568                    ((core_if->hwcfg2.b.hs_phy_type == 2) ||
+-04569                     (core_if->hwcfg2.b.hs_phy_type == 3))) {
+-04570                 valid = 1;
+-04571         } else if ((val == DWC_PHY_TYPE_PARAM_FS) &&
+-04572                    (core_if->hwcfg2.b.fs_phy_type == 1)) {
+-04573                 valid = 1;
+-04574         }
+-04575         if (!valid) {
+-04576                 if (dwc_otg_param_initialized(core_if->core_params->phy_type)) {
+-04577                         DWC_ERROR
+-04578                             ("%d invalid for phy_type. Check HW configurations.\n",
+-04579                              val);
+-04580                 }
+-04581                 if (core_if->hwcfg2.b.hs_phy_type) {
+-04582                         if ((core_if->hwcfg2.b.hs_phy_type == 3) ||
+-04583                             (core_if->hwcfg2.b.hs_phy_type == 1)) {
+-04584                                 val = DWC_PHY_TYPE_PARAM_UTMI;
+-04585                         } else {
+-04586                                 val = DWC_PHY_TYPE_PARAM_ULPI;
+-04587                         }
+-04588                 }
+-04589                 retval = -DWC_E_INVALID;
+-04590         }
+-04591 #endif
+-04592         core_if->core_params->phy_type = val;
+-04593         return retval;
+-04594 }
+-04595 
+-04596 int32_t dwc_otg_get_param_phy_type(dwc_otg_core_if_t * core_if)
+-04597 {
+-04598         return core_if->core_params->phy_type;
+-04599 }
+-04600 
+-04601 int dwc_otg_set_param_speed(dwc_otg_core_if_t * core_if, int32_t val)
+-04602 {
+-04603         int retval = 0;
+-04604         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
+-04605                 DWC_WARN("Wrong value for speed parameter\n");
+-04606                 DWC_WARN("max_speed parameter must be 0 or 1\n");
+-04607                 return -DWC_E_INVALID;
+-04608         }
+-04609         if ((val == 0)
+-04610             && dwc_otg_get_param_phy_type(core_if) == DWC_PHY_TYPE_PARAM_FS) {
+-04611                 if (dwc_otg_param_initialized(core_if->core_params->speed)) {
+-04612                         DWC_ERROR
+-04613                             ("%d invalid for speed paremter. Check HW configuration.\n",
+-04614                              val);
+-04615                 }
+-04616                 val =
+-04617                     (dwc_otg_get_param_phy_type(core_if) ==
+-04618                      DWC_PHY_TYPE_PARAM_FS ? 1 : 0);
+-04619                 retval = -DWC_E_INVALID;
+-04620         }
+-04621         core_if->core_params->speed = val;
+-04622         return retval;
+-04623 }
+-04624 
+-04625 int32_t dwc_otg_get_param_speed(dwc_otg_core_if_t * core_if)
+-04626 {
+-04627         return core_if->core_params->speed;
+-04628 }
+-04629 
+-04630 int dwc_otg_set_param_host_ls_low_power_phy_clk(dwc_otg_core_if_t * core_if,
+-04631                                                 int32_t val)
+-04632 {
+-04633         int retval = 0;
+-04634 
+-04635         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
+-04636                 DWC_WARN
+-04637                     ("Wrong value for host_ls_low_power_phy_clk parameter\n");
+-04638                 DWC_WARN("host_ls_low_power_phy_clk must be 0 or 1\n");
+-04639                 return -DWC_E_INVALID;
+-04640         }
+-04641 
+-04642         if ((val == DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ)
+-04643             && (dwc_otg_get_param_phy_type(core_if) == DWC_PHY_TYPE_PARAM_FS)) {
+-04644                 if(dwc_otg_param_initialized(core_if->core_params->host_ls_low_power_phy_clk)) {
+-04645                         DWC_ERROR("%d invalid for host_ls_low_power_phy_clk. Check HW configuration.\n",
+-04646                      val);
+-04647                 }
+-04648                 val =
+-04649                     (dwc_otg_get_param_phy_type(core_if) ==
+-04650                      DWC_PHY_TYPE_PARAM_FS) ?
+-04651                     DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ :
+-04652                     DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ;
+-04653                 retval = -DWC_E_INVALID;
+-04654         }
+-04655 
+-04656         core_if->core_params->host_ls_low_power_phy_clk = val;
+-04657         return retval;
+-04658 }
+-04659 
+-04660 int32_t dwc_otg_get_param_host_ls_low_power_phy_clk(dwc_otg_core_if_t * core_if)
+-04661 {
+-04662         return core_if->core_params->host_ls_low_power_phy_clk;
+-04663 }
+-04664 
+-04665 int dwc_otg_set_param_phy_ulpi_ddr(dwc_otg_core_if_t * core_if, int32_t val)
+-04666 {
+-04667         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
+-04668                 DWC_WARN("Wrong value for phy_ulpi_ddr\n");
+-04669                 DWC_WARN("phy_upli_ddr must be 0 or 1\n");
+-04670                 return -DWC_E_INVALID;
+-04671         }
+-04672 
+-04673         core_if->core_params->phy_ulpi_ddr = val;
+-04674         return 0;
+-04675 }
+-04676 
+-04677 int32_t dwc_otg_get_param_phy_ulpi_ddr(dwc_otg_core_if_t * core_if)
+-04678 {
+-04679         return core_if->core_params->phy_ulpi_ddr;
+-04680 }
+-04681 
+-04682 int dwc_otg_set_param_phy_ulpi_ext_vbus(dwc_otg_core_if_t * core_if,
+-04683                                         int32_t val)
+-04684 {
+-04685         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
+-04686                 DWC_WARN("Wrong valaue for phy_ulpi_ext_vbus\n");
+-04687                 DWC_WARN("phy_ulpi_ext_vbus must be 0 or 1\n");
+-04688                 return -DWC_E_INVALID;
+-04689         }
+-04690 
+-04691         core_if->core_params->phy_ulpi_ext_vbus = val;
+-04692         return 0;
+-04693 }
+-04694 
+-04695 int32_t dwc_otg_get_param_phy_ulpi_ext_vbus(dwc_otg_core_if_t * core_if)
+-04696 {
+-04697         return core_if->core_params->phy_ulpi_ext_vbus;
+-04698 }
+-04699 
+-04700 int dwc_otg_set_param_phy_utmi_width(dwc_otg_core_if_t * core_if, int32_t val)
+-04701 {
+-04702         if (DWC_OTG_PARAM_TEST(val, 8, 8) && DWC_OTG_PARAM_TEST(val, 16, 16)) {
+-04703                 DWC_WARN("Wrong valaue for phy_utmi_width\n");
+-04704                 DWC_WARN("phy_utmi_width must be 8 or 16\n");
+-04705                 return -DWC_E_INVALID;
+-04706         }
+-04707 
+-04708         core_if->core_params->phy_utmi_width = val;
+-04709         return 0;
+-04710 }
+-04711 
+-04712 int32_t dwc_otg_get_param_phy_utmi_width(dwc_otg_core_if_t * core_if)
+-04713 {
+-04714         return core_if->core_params->phy_utmi_width;
+-04715 }
+-04716 
+-04717 int dwc_otg_set_param_ulpi_fs_ls(dwc_otg_core_if_t * core_if, int32_t val)
+-04718 {
+-04719         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
+-04720                 DWC_WARN("Wrong valaue for ulpi_fs_ls\n");
+-04721                 DWC_WARN("ulpi_fs_ls must be 0 or 1\n");
+-04722                 return -DWC_E_INVALID;
+-04723         }
+-04724 
+-04725         core_if->core_params->ulpi_fs_ls = val;
+-04726         return 0;
+-04727 }
+-04728 
+-04729 int32_t dwc_otg_get_param_ulpi_fs_ls(dwc_otg_core_if_t * core_if)
+-04730 {
+-04731         return core_if->core_params->ulpi_fs_ls;
+-04732 }
+-04733 
+-04734 int dwc_otg_set_param_ts_dline(dwc_otg_core_if_t * core_if, int32_t val)
+-04735 {
+-04736         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
+-04737                 DWC_WARN("Wrong valaue for ts_dline\n");
+-04738                 DWC_WARN("ts_dline must be 0 or 1\n");
+-04739                 return -DWC_E_INVALID;
+-04740         }
+-04741 
+-04742         core_if->core_params->ts_dline = val;
+-04743         return 0;
+-04744 }
+-04745 
+-04746 int32_t dwc_otg_get_param_ts_dline(dwc_otg_core_if_t * core_if)
+-04747 {
+-04748         return core_if->core_params->ts_dline;
+-04749 }
+-04750 
+-04751 int dwc_otg_set_param_i2c_enable(dwc_otg_core_if_t * core_if, int32_t val)
+-04752 {
+-04753         int retval = 0;
+-04754         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
+-04755                 DWC_WARN("Wrong valaue for i2c_enable\n");
+-04756                 DWC_WARN("i2c_enable must be 0 or 1\n");
+-04757                 return -DWC_E_INVALID;
+-04758         }
+-04759 #ifndef NO_FS_PHY_HW_CHECK
+-04760         if (val == 1 && core_if->hwcfg3.b.i2c == 0) {
+-04761                 if(dwc_otg_param_initialized(core_if->core_params->i2c_enable)) {
+-04762                         DWC_ERROR("%d invalid for i2c_enable. Check HW configuration.\n",
+-04763                      val);
+-04764                 }
+-04765                 val = 0;
+-04766                 retval = -DWC_E_INVALID;
+-04767         }
+-04768 #endif
+-04769 
+-04770         core_if->core_params->i2c_enable = val;
+-04771         return retval;
+-04772 }
+-04773 
+-04774 int32_t dwc_otg_get_param_i2c_enable(dwc_otg_core_if_t * core_if)
+-04775 {
+-04776         return core_if->core_params->i2c_enable;
+-04777 }
+-04778 
+-04779 int dwc_otg_set_param_dev_perio_tx_fifo_size(dwc_otg_core_if_t * core_if,
+-04780                                              int32_t val, int fifo_num)
+-04781 {
+-04782         int retval = 0;
+-04783 
+-04784         if (DWC_OTG_PARAM_TEST(val, 4, 768)) {
+-04785                 DWC_WARN("Wrong value for dev_perio_tx_fifo_size\n");
+-04786                 DWC_WARN("dev_perio_tx_fifo_size must be 4-768\n");
+-04787                 return -DWC_E_INVALID;
+-04788         }
+-04789 
+-04790         if (val > (dwc_read_reg32(&core_if->core_global_regs->dptxfsiz_dieptxf[fifo_num]))) {
+-04791                 if(dwc_otg_param_initialized(core_if->core_params->dev_perio_tx_fifo_size[fifo_num])) {
+-04792                         DWC_ERROR("`%d' invalid for parameter `dev_perio_fifo_size_%d'. Check HW configuration.\n",
+-04793                      val, fifo_num);
+-04794                 }
+-04795                 val = (dwc_read_reg32(&core_if->core_global_regs->dptxfsiz_dieptxf[fifo_num]));
+-04796                 retval = -DWC_E_INVALID;
+-04797         }
+-04798 
+-04799         core_if->core_params->dev_perio_tx_fifo_size[fifo_num] = val;
+-04800         return retval;
+-04801 }
+-04802 
+-04803 int32_t dwc_otg_get_param_dev_perio_tx_fifo_size(dwc_otg_core_if_t * core_if,
+-04804                                                  int fifo_num)
+-04805 {
+-04806         return core_if->core_params->dev_perio_tx_fifo_size[fifo_num];
+-04807 }
+-04808 
+-04809 int dwc_otg_set_param_en_multiple_tx_fifo(dwc_otg_core_if_t * core_if,
+-04810                                           int32_t val)
+-04811 {
+-04812         int retval = 0;
+-04813         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
+-04814                 DWC_WARN("Wrong valaue for en_multiple_tx_fifo,\n");
+-04815                 DWC_WARN("en_multiple_tx_fifo must be 0 or 1\n");
+-04816                 return -DWC_E_INVALID;
+-04817         }
+-04818 
+-04819         if (val == 1 && core_if->hwcfg4.b.ded_fifo_en == 0) {
+-04820                 if(dwc_otg_param_initialized(core_if->core_params->en_multiple_tx_fifo)) {
+-04821                         DWC_ERROR("%d invalid for parameter en_multiple_tx_fifo. Check HW configuration.\n",
+-04822                      val);
+-04823                 }
+-04824                 val = 0;
+-04825                 retval = -DWC_E_INVALID;
+-04826         }
+-04827 
+-04828         core_if->core_params->en_multiple_tx_fifo = val;
+-04829         return retval;
+-04830 }
+-04831 
+-04832 int32_t dwc_otg_get_param_en_multiple_tx_fifo(dwc_otg_core_if_t * core_if)
+-04833 {
+-04834         return core_if->core_params->en_multiple_tx_fifo;
+-04835 }
+-04836 
+-04837 int dwc_otg_set_param_dev_tx_fifo_size(dwc_otg_core_if_t * core_if, int32_t val,
+-04838                                        int fifo_num)
+-04839 {
+-04840         int retval = 0;
+-04841 
+-04842         if (DWC_OTG_PARAM_TEST(val, 4, 768)) {
+-04843                 DWC_WARN("Wrong value for dev_tx_fifo_size\n");
+-04844                 DWC_WARN("dev_tx_fifo_size must be 4-768\n");
+-04845                 return -DWC_E_INVALID;
+-04846         }
+-04847 
+-04848         if (val > (dwc_read_reg32(&core_if->core_global_regs->dptxfsiz_dieptxf[fifo_num]))) {
+-04849                 if(dwc_otg_param_initialized(core_if->core_params->dev_tx_fifo_size[fifo_num])) {
+-04850                         DWC_ERROR("`%d' invalid for parameter `dev_tx_fifo_size_%d'. Check HW configuration.\n",
+-04851                      val, fifo_num);
+-04852                 }
+-04853                 val = (dwc_read_reg32(&core_if->core_global_regs->dptxfsiz_dieptxf[fifo_num]));
+-04854                 retval = -DWC_E_INVALID;
+-04855         }
+-04856 
+-04857         core_if->core_params->dev_tx_fifo_size[fifo_num] = val;
+-04858         return retval;
+-04859 }
+-04860 
+-04861 int32_t dwc_otg_get_param_dev_tx_fifo_size(dwc_otg_core_if_t * core_if,
+-04862                                            int fifo_num)
+-04863 {
+-04864         return core_if->core_params->dev_tx_fifo_size[fifo_num];
+-04865 }
+-04866 
+-04867 int dwc_otg_set_param_thr_ctl(dwc_otg_core_if_t * core_if, int32_t val)
+-04868 {
+-04869         int retval = 0;
+-04870 
+-04871         if (DWC_OTG_PARAM_TEST(val, 0, 7)) {
+-04872                 DWC_WARN("Wrong value for thr_ctl\n");
+-04873                 DWC_WARN("thr_ctl must be 0-7\n");
+-04874                 return -DWC_E_INVALID;
+-04875         }
+-04876 
+-04877         if ((val != 0) &&
+-04878             (!dwc_otg_get_param_dma_enable(core_if) ||
+-04879              !core_if->hwcfg4.b.ded_fifo_en)) {
+-04880                 if(dwc_otg_param_initialized(core_if->core_params->thr_ctl)) {
+-04881                         DWC_ERROR("%d invalid for parameter thr_ctl. Check HW configuration.\n",
+-04882                      val);
+-04883                 }
+-04884                 val = 0;
+-04885                 retval = -DWC_E_INVALID;
+-04886         }
+-04887 
+-04888         core_if->core_params->thr_ctl = val;
+-04889         return retval;
+-04890 }
+-04891 
+-04892 int32_t dwc_otg_get_param_thr_ctl(dwc_otg_core_if_t * core_if)
+-04893 {
+-04894         return core_if->core_params->thr_ctl;
+-04895 }
+-04896 
+-04897 int dwc_otg_set_param_lpm_enable(dwc_otg_core_if_t * core_if, int32_t val)
+-04898 {
+-04899         int retval = 0;
+-04900 
+-04901         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
+-04902                 DWC_WARN("Wrong value for lpm_enable\n");
+-04903                 DWC_WARN("lpm_enable must be 0 or 1\n");
+-04904                 return -DWC_E_INVALID;
+-04905         }
+-04906 
+-04907         if (val && !core_if->hwcfg3.b.otg_lpm_en) {
+-04908                 if(dwc_otg_param_initialized(core_if->core_params->lpm_enable)) {
+-04909                         DWC_ERROR("%d invalid for parameter lpm_enable. Check HW configuration.\n",
+-04910                      val);
+-04911                 }
+-04912                 val = 0;
+-04913                 retval = -DWC_E_INVALID;
+-04914         }
+-04915 
+-04916         core_if->core_params->lpm_enable = val;
+-04917         return retval;
+-04918 }
+-04919 
+-04920 int32_t dwc_otg_get_param_lpm_enable(dwc_otg_core_if_t * core_if)
+-04921 {
+-04922         return core_if->core_params->lpm_enable;
+-04923 }
+-04924 
+-04925 int dwc_otg_set_param_tx_thr_length(dwc_otg_core_if_t * core_if, int32_t val)
+-04926 {
+-04927         if (DWC_OTG_PARAM_TEST(val, 8, 128)) {
+-04928                 DWC_WARN("Wrong valaue for tx_thr_length\n");
+-04929                 DWC_WARN("tx_thr_length must be 8 - 128\n");
+-04930                 return -DWC_E_INVALID;
+-04931         }
+-04932 
+-04933         core_if->core_params->tx_thr_length = val;
+-04934         return 0;
+-04935 }
+-04936 
+-04937 int32_t dwc_otg_get_param_tx_thr_length(dwc_otg_core_if_t * core_if)
+-04938 {
+-04939         return core_if->core_params->tx_thr_length;
+-04940 }
+-04941 
+-04942 int dwc_otg_set_param_rx_thr_length(dwc_otg_core_if_t * core_if, int32_t val)
+-04943 {
+-04944         if (DWC_OTG_PARAM_TEST(val, 8, 128)) {
+-04945                 DWC_WARN("Wrong valaue for rx_thr_length\n");
+-04946                 DWC_WARN("rx_thr_length must be 8 - 128\n");
+-04947                 return -DWC_E_INVALID;
+-04948         }
+-04949 
+-04950         core_if->core_params->rx_thr_length = val;
+-04951         return 0;
+-04952 }
+-04953 
+-04954 int32_t dwc_otg_get_param_rx_thr_length(dwc_otg_core_if_t * core_if)
+-04955 {
+-04956         return core_if->core_params->rx_thr_length;
+-04957 }
+-04958 
+-04959 int dwc_otg_set_param_dma_burst_size(dwc_otg_core_if_t * core_if, int32_t val)
+-04960 {
+-04961         if (DWC_OTG_PARAM_TEST(val, 1, 1) &&
+-04962             DWC_OTG_PARAM_TEST(val, 4, 4) &&
+-04963             DWC_OTG_PARAM_TEST(val, 8, 8) &&
+-04964             DWC_OTG_PARAM_TEST(val, 16, 16) &&
+-04965             DWC_OTG_PARAM_TEST(val, 32, 32) &&
+-04966             DWC_OTG_PARAM_TEST(val, 64, 64) &&
+-04967             DWC_OTG_PARAM_TEST(val, 128, 128) &&
+-04968             DWC_OTG_PARAM_TEST(val, 256, 256)) {
+-04969                 DWC_WARN("`%d' invalid for parameter `dma_burst_size'\n", val);
+-04970                 return -DWC_E_INVALID;
+-04971         }
+-04972         core_if->core_params->dma_burst_size = val;
+-04973         return 0;
+-04974 }
+-04975 
+-04976 int32_t dwc_otg_get_param_dma_burst_size(dwc_otg_core_if_t * core_if)
+-04977 {
+-04978         return core_if->core_params->dma_burst_size;
+-04979 }
+-04980 
+-04981 int dwc_otg_set_param_pti_enable(dwc_otg_core_if_t * core_if, int32_t val)
+-04982 {
+-04983         int retval = 0;
+-04984         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
+-04985                 DWC_WARN("`%d' invalid for parameter `pti_enable'\n", val);
+-04986                 return -DWC_E_INVALID;
+-04987         }
+-04988         if (val && (core_if->snpsid < OTG_CORE_REV_2_72a)) {
+-04989                 if (dwc_otg_param_initialized(core_if->core_params->pti_enable)) {
+-04990                         DWC_ERROR("%d invalid for parameter pti_enable. Check HW configuration.\n",
+-04991                              val);
+-04992                 }
+-04993                 retval = -DWC_E_INVALID;
+-04994                 val = 0;
+-04995         }
+-04996         core_if->core_params->pti_enable = val;
+-04997         return retval;
+-04998 }
+-04999 
+-05000 int32_t dwc_otg_get_param_pti_enable(dwc_otg_core_if_t * core_if)
+-05001 {
+-05002         return core_if->core_params->pti_enable;
+-05003 }
+-05004 
+-05005 int dwc_otg_set_param_mpi_enable(dwc_otg_core_if_t * core_if, int32_t val)
+-05006 {
+-05007         int retval = 0;
+-05008         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
+-05009                 DWC_WARN("`%d' invalid for parameter `mpi_enable'\n", val);
+-05010                 return -DWC_E_INVALID;
+-05011         }
+-05012         if (val && (core_if->hwcfg2.b.multi_proc_int == 0)) {
+-05013                 if (dwc_otg_param_initialized(core_if->core_params->mpi_enable)) {
+-05014                         DWC_ERROR("%d invalid for parameter mpi_enable. Check HW configuration.\n",
+-05015                              val);
+-05016                 }
+-05017                 retval = -DWC_E_INVALID;
+-05018                 val = 0;
+-05019         }
+-05020         core_if->core_params->mpi_enable = val;
+-05021         return retval;
+-05022 }
+-05023 
+-05024 int32_t dwc_otg_get_param_mpi_enable(dwc_otg_core_if_t * core_if)
+-05025 {
+-05026         return core_if->core_params->mpi_enable;
+-05027 }
+-05028 
+-05029 int dwc_otg_set_param_ic_usb_cap(dwc_otg_core_if_t * core_if,
+-05030                                         int32_t val)
+-05031 {
+-05032         int retval = 0;
+-05033         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
+-05034                 DWC_WARN("`%d' invalid for parameter `ic_usb_cap'\n", val);
+-05035                 DWC_WARN("ic_usb_cap must be 0 or 1\n");
+-05036                 return -DWC_E_INVALID;
+-05037         }
+-05038 
+-05039         if (val && (core_if->hwcfg3.b.otg_enable_ic_usb == 0)) {
+-05040                 if (dwc_otg_param_initialized(core_if->core_params->ic_usb_cap)) {
+-05041                         DWC_ERROR("%d invalid for parameter ic_usb_cap. Check HW configuration.\n",
+-05042                              val);
+-05043                 }
+-05044                 retval = -DWC_E_INVALID;
+-05045                 val = 0;
+-05046         }
+-05047         core_if->core_params->ic_usb_cap = val;
+-05048         return retval;
+-05049 }
+-05050 int32_t dwc_otg_get_param_ic_usb_cap(dwc_otg_core_if_t * core_if)
+-05051 {
+-05052         return core_if->core_params->ic_usb_cap;
+-05053 }
+-05054 
+-05055 int dwc_otg_set_param_ahb_thr_ratio(dwc_otg_core_if_t * core_if, int32_t val)
+-05056 {
+-05057         int retval = 0;
+-05058         int valid = 1;
+-05059 
+-05060         if(DWC_OTG_PARAM_TEST(val, 0, 3)) {
+-05061                 DWC_WARN("`%d' invalid for parameter `ahb_thr_ratio'\n", val);
+-05062                 DWC_WARN("ahb_thr_ratio must be 0 - 3\n");
+-05063                 return -DWC_E_INVALID;
+-05064         }
+-05065 
+-05066         if(val && (core_if->snpsid < OTG_CORE_REV_2_81a || !dwc_otg_get_param_thr_ctl(core_if))) {
+-05067                 valid = 0;
+-05068         } else if(val && ((dwc_otg_get_param_tx_thr_length(core_if) / (1 << val)) < 4)) {
+-05069                 valid = 0;
+-05070         }
+-05071         if(valid == 0) {
+-05072                 if(dwc_otg_param_initialized(core_if->core_params->ahb_thr_ratio)) {
+-05073                         DWC_ERROR("%d invalid for parameter ahb_thr_ratio. Chack HW configuration.\n", val);
+-05074                 }
+-05075                 retval = -DWC_E_INVALID;
+-05076                 val = 0;
+-05077         }
+-05078 
+-05079         core_if->core_params->ahb_thr_ratio = val;
+-05080         return retval;
+-05081 }
+-05082 int32_t dwc_otg_get_param_ahb_thr_ratio(dwc_otg_core_if_t * core_if)
+-05083 {
+-05084         return core_if->core_params->ahb_thr_ratio;
+-05085 }
+-05086 
+-05087 
+-05088 uint32_t dwc_otg_get_hnpstatus(dwc_otg_core_if_t * core_if)
+-05089 {
+-05090         gotgctl_data_t otgctl;
+-05091         otgctl.d32 = dwc_read_reg32(&core_if->core_global_regs->gotgctl);
+-05092         return otgctl.b.hstnegscs;
+-05093 }
+-05094 
+-05095 uint32_t dwc_otg_get_srpstatus(dwc_otg_core_if_t * core_if)
+-05096 {
+-05097         gotgctl_data_t otgctl;
+-05098         otgctl.d32 = dwc_read_reg32(&core_if->core_global_regs->gotgctl);
+-05099         return otgctl.b.sesreqscs;
+-05100 }
+-05101 
+-05102 void dwc_otg_set_hnpreq(dwc_otg_core_if_t * core_if, uint32_t val)
+-05103 {
+-05104         gotgctl_data_t otgctl;
+-05105         otgctl.d32 = dwc_read_reg32(&core_if->core_global_regs->gotgctl);
+-05106         otgctl.b.hnpreq = val;
+-05107         dwc_write_reg32(&core_if->core_global_regs->gotgctl, otgctl.d32);
+-05108 }
+-05109 
+-05110 uint32_t dwc_otg_get_gsnpsid(dwc_otg_core_if_t * core_if)
+-05111 {
+-05112         return core_if->snpsid;
+-05113 }
+-05114 
+-05115 uint32_t dwc_otg_get_mode(dwc_otg_core_if_t * core_if)
+-05116 {
+-05117         gotgctl_data_t otgctl;
+-05118         otgctl.d32 = dwc_read_reg32(&core_if->core_global_regs->gotgctl);
+-05119         return otgctl.b.currmod;
+-05120 }
+-05121 
+-05122 uint32_t dwc_otg_get_hnpcapable(dwc_otg_core_if_t * core_if)
+-05123 {
+-05124         gusbcfg_data_t usbcfg;
+-05125         usbcfg.d32 = dwc_read_reg32(&core_if->core_global_regs->gusbcfg);
+-05126         return usbcfg.b.hnpcap;
+-05127 }
+-05128 
+-05129 void dwc_otg_set_hnpcapable(dwc_otg_core_if_t * core_if, uint32_t val)
+-05130 {
+-05131         gusbcfg_data_t usbcfg;
+-05132         usbcfg.d32 = dwc_read_reg32(&core_if->core_global_regs->gusbcfg);
+-05133         usbcfg.b.hnpcap = val;
+-05134         dwc_write_reg32(&core_if->core_global_regs->gusbcfg, usbcfg.d32);
+-05135 }
+-05136 
+-05137 uint32_t dwc_otg_get_srpcapable(dwc_otg_core_if_t * core_if)
+-05138 {
+-05139         gusbcfg_data_t usbcfg;
+-05140         usbcfg.d32 = dwc_read_reg32(&core_if->core_global_regs->gusbcfg);
+-05141         return usbcfg.b.srpcap;
+-05142 }
+-05143 
+-05144 void dwc_otg_set_srpcapable(dwc_otg_core_if_t * core_if, uint32_t val)
+-05145 {
+-05146         gusbcfg_data_t usbcfg;
+-05147         usbcfg.d32 = dwc_read_reg32(&core_if->core_global_regs->gusbcfg);
+-05148         usbcfg.b.srpcap = val;
+-05149         dwc_write_reg32(&core_if->core_global_regs->gusbcfg, usbcfg.d32);
+-05150 }
+-05151 
+-05152 uint32_t dwc_otg_get_devspeed(dwc_otg_core_if_t * core_if)
+-05153 {
+-05154         dcfg_data_t dcfg;
+-05155         dcfg.d32 = dwc_read_reg32(&core_if->dev_if->dev_global_regs->dcfg);
+-05156         return dcfg.b.devspd;
+-05157 }
+-05158 
+-05159 void dwc_otg_set_devspeed(dwc_otg_core_if_t * core_if, uint32_t val)
+-05160 {
+-05161         dcfg_data_t dcfg;
+-05162         dcfg.d32 = dwc_read_reg32(&core_if->dev_if->dev_global_regs->dcfg);
+-05163         dcfg.b.devspd = val;
+-05164         dwc_write_reg32(&core_if->dev_if->dev_global_regs->dcfg, dcfg.d32);
+-05165 }
+-05166 
+-05167 uint32_t dwc_otg_get_busconnected(dwc_otg_core_if_t * core_if)
+-05168 {
+-05169         hprt0_data_t hprt0;
+-05170         hprt0.d32 = dwc_read_reg32(core_if->host_if->hprt0);
+-05171         return hprt0.b.prtconnsts;
+-05172 }
+-05173 
+-05174 uint32_t dwc_otg_get_enumspeed(dwc_otg_core_if_t * core_if)
+-05175 {
+-05176         dsts_data_t dsts;
+-05177         dsts.d32 = dwc_read_reg32(&core_if->dev_if->dev_global_regs->dsts);
+-05178         return dsts.b.enumspd;
+-05179 }
+-05180 
+-05181 uint32_t dwc_otg_get_prtpower(dwc_otg_core_if_t * core_if)
+-05182 {
+-05183         hprt0_data_t hprt0;
+-05184         hprt0.d32 = dwc_read_reg32(core_if->host_if->hprt0);
+-05185         return hprt0.b.prtpwr;
+-05186 
+-05187 }
+-05188 
+-05189 void dwc_otg_set_prtpower(dwc_otg_core_if_t * core_if, uint32_t val)
+-05190 {
+-05191         hprt0_data_t hprt0;
+-05192         hprt0.d32 = dwc_read_reg32(core_if->host_if->hprt0);
+-05193         hprt0.b.prtpwr = val;
+-05194         dwc_write_reg32(core_if->host_if->hprt0, val);
+-05195 }
+-05196 
+-05197 uint32_t dwc_otg_get_prtsuspend(dwc_otg_core_if_t * core_if)
+-05198 {
+-05199         hprt0_data_t hprt0;
+-05200         hprt0.d32 = dwc_read_reg32(core_if->host_if->hprt0);
+-05201         return hprt0.b.prtsusp;
+-05202 
+-05203 }
+-05204 
+-05205 void dwc_otg_set_prtsuspend(dwc_otg_core_if_t * core_if, uint32_t val)
+-05206 {
+-05207         hprt0_data_t hprt0;
+-05208         hprt0.d32 = dwc_read_reg32(core_if->host_if->hprt0);
+-05209         hprt0.b.prtsusp = val;
+-05210         dwc_write_reg32(core_if->host_if->hprt0, val);
+-05211 }
+-05212 
+-05213 void dwc_otg_set_prtresume(dwc_otg_core_if_t * core_if, uint32_t val)
+-05214 {
+-05215         hprt0_data_t hprt0;
+-05216         hprt0.d32 = dwc_read_reg32(core_if->host_if->hprt0);
+-05217         hprt0.b.prtres = val;
+-05218         dwc_write_reg32(core_if->host_if->hprt0, val);
+-05219 }
+-05220 
+-05221 uint32_t dwc_otg_get_remotewakesig(dwc_otg_core_if_t * core_if)
+-05222 {
+-05223         dctl_data_t dctl;
+-05224         dctl.d32 = dwc_read_reg32(&core_if->dev_if->dev_global_regs->dctl);
+-05225         return dctl.b.rmtwkupsig;
+-05226 }
+-05227 
+-05228 uint32_t dwc_otg_get_lpm_portsleepstatus(dwc_otg_core_if_t * core_if)
+-05229 {
+-05230         glpmcfg_data_t lpmcfg;
+-05231         lpmcfg.d32 = dwc_read_reg32(&core_if->core_global_regs->glpmcfg);
+-05232 
+-05233         DWC_ASSERT(!
+-05234                    ((core_if->lx_state == DWC_OTG_L1) ^ lpmcfg.b.prt_sleep_sts),
+-05235                    "lx_state = %d, lmpcfg.prt_sleep_sts = %d\n",
+-05236                    core_if->lx_state, lpmcfg.b.prt_sleep_sts);
+-05237 
+-05238         return lpmcfg.b.prt_sleep_sts;
+-05239 }
+-05240 
+-05241 uint32_t dwc_otg_get_lpm_remotewakeenabled(dwc_otg_core_if_t * core_if)
+-05242 {
+-05243         glpmcfg_data_t lpmcfg;
+-05244         lpmcfg.d32 = dwc_read_reg32(&core_if->core_global_regs->glpmcfg);
+-05245         return lpmcfg.b.rem_wkup_en;
+-05246 }
+-05247 
+-05248 uint32_t dwc_otg_get_lpmresponse(dwc_otg_core_if_t * core_if)
+-05249 {
+-05250         glpmcfg_data_t lpmcfg;
+-05251         lpmcfg.d32 = dwc_read_reg32(&core_if->core_global_regs->glpmcfg);
+-05252         return lpmcfg.b.appl_resp;
+-05253 }
+-05254 
+-05255 void dwc_otg_set_lpmresponse(dwc_otg_core_if_t * core_if, uint32_t val)
+-05256 {
+-05257         glpmcfg_data_t lpmcfg;
+-05258         lpmcfg.d32 = dwc_read_reg32(&core_if->core_global_regs->glpmcfg);
+-05259         lpmcfg.b.appl_resp = val;
+-05260         dwc_write_reg32(&core_if->core_global_regs->glpmcfg, lpmcfg.d32);
+-05261 }
+-05262 
+-05263 uint32_t dwc_otg_get_hsic_connect(dwc_otg_core_if_t * core_if)
+-05264 {
+-05265         glpmcfg_data_t lpmcfg;
+-05266         lpmcfg.d32 = dwc_read_reg32(&core_if->core_global_regs->glpmcfg);
+-05267         return lpmcfg.b.hsic_connect;
+-05268 }
+-05269 
+-05270 void dwc_otg_set_hsic_connect(dwc_otg_core_if_t * core_if, uint32_t val)
+-05271 {
+-05272         glpmcfg_data_t lpmcfg;
+-05273         lpmcfg.d32 = dwc_read_reg32(&core_if->core_global_regs->glpmcfg);
+-05274         lpmcfg.b.hsic_connect = val;
+-05275         dwc_write_reg32(&core_if->core_global_regs->glpmcfg, lpmcfg.d32);
+-05276 }
+-05277 
+-05278 uint32_t dwc_otg_get_inv_sel_hsic(dwc_otg_core_if_t * core_if)
+-05279 {
+-05280         glpmcfg_data_t lpmcfg;
+-05281         lpmcfg.d32 = dwc_read_reg32(&core_if->core_global_regs->glpmcfg);
+-05282         return lpmcfg.b.inv_sel_hsic;
+-05283 
+-05284 }
+-05285 
+-05286 void dwc_otg_set_inv_sel_hsic(dwc_otg_core_if_t * core_if, uint32_t val)
+-05287 {
+-05288         glpmcfg_data_t lpmcfg;
+-05289         lpmcfg.d32 = dwc_read_reg32(&core_if->core_global_regs->glpmcfg);
+-05290         lpmcfg.b.inv_sel_hsic = val;
+-05291         dwc_write_reg32(&core_if->core_global_regs->glpmcfg, lpmcfg.d32);
+-05292 }
+-05293 
+-05294 uint32_t dwc_otg_get_gotgctl(dwc_otg_core_if_t * core_if)
+-05295 {
+-05296         return dwc_read_reg32(&core_if->core_global_regs->gotgctl);
+-05297 }
+-05298 
+-05299 void dwc_otg_set_gotgctl(dwc_otg_core_if_t * core_if, uint32_t val)
+-05300 {
+-05301         dwc_write_reg32(&core_if->core_global_regs->gotgctl, val);
+-05302 }
+-05303 
+-05304 uint32_t dwc_otg_get_gusbcfg(dwc_otg_core_if_t * core_if)
+-05305 {
+-05306         return dwc_read_reg32(&core_if->core_global_regs->gusbcfg);
+-05307 }
+-05308 
+-05309 void dwc_otg_set_gusbcfg(dwc_otg_core_if_t * core_if, uint32_t val)
+-05310 {
+-05311         dwc_write_reg32(&core_if->core_global_regs->gusbcfg, val);
+-05312 }
+-05313 
+-05314 uint32_t dwc_otg_get_grxfsiz(dwc_otg_core_if_t * core_if)
+-05315 {
+-05316         return dwc_read_reg32(&core_if->core_global_regs->grxfsiz);
+-05317 }
+-05318 
+-05319 void dwc_otg_set_grxfsiz(dwc_otg_core_if_t * core_if, uint32_t val)
+-05320 {
+-05321         dwc_write_reg32(&core_if->core_global_regs->grxfsiz, val);
+-05322 }
+-05323 
+-05324 uint32_t dwc_otg_get_gnptxfsiz(dwc_otg_core_if_t * core_if)
+-05325 {
+-05326         return dwc_read_reg32(&core_if->core_global_regs->gnptxfsiz);
+-05327 }
+-05328 
+-05329 void dwc_otg_set_gnptxfsiz(dwc_otg_core_if_t * core_if, uint32_t val)
+-05330 {
+-05331         dwc_write_reg32(&core_if->core_global_regs->gnptxfsiz, val);
+-05332 }
+-05333 
+-05334 uint32_t dwc_otg_get_gpvndctl(dwc_otg_core_if_t * core_if)
+-05335 {
+-05336         return dwc_read_reg32(&core_if->core_global_regs->gpvndctl);
+-05337 }
+-05338 
+-05339 void dwc_otg_set_gpvndctl(dwc_otg_core_if_t * core_if, uint32_t val)
+-05340 {
+-05341         dwc_write_reg32(&core_if->core_global_regs->gpvndctl, val);
+-05342 }
+-05343 
+-05344 uint32_t dwc_otg_get_ggpio(dwc_otg_core_if_t * core_if)
+-05345 {
+-05346         return dwc_read_reg32(&core_if->core_global_regs->ggpio);
+-05347 }
+-05348 
+-05349 void dwc_otg_set_ggpio(dwc_otg_core_if_t * core_if, uint32_t val)
+-05350 {
+-05351         dwc_write_reg32(&core_if->core_global_regs->ggpio, val);
+-05352 }
+-05353 
+-05354 uint32_t dwc_otg_get_hprt0(dwc_otg_core_if_t * core_if)
+-05355 {
+-05356         return dwc_read_reg32(core_if->host_if->hprt0);
+-05357 
+-05358 }
+-05359 
+-05360 void dwc_otg_set_hprt0(dwc_otg_core_if_t * core_if, uint32_t val)
+-05361 {
+-05362         dwc_write_reg32(core_if->host_if->hprt0, val);
+-05363 }
+-05364 
+-05365 uint32_t dwc_otg_get_guid(dwc_otg_core_if_t * core_if)
+-05366 {
+-05367         return dwc_read_reg32(&core_if->core_global_regs->guid);
+-05368 }
+-05369 
+-05370 void dwc_otg_set_guid(dwc_otg_core_if_t * core_if, uint32_t val)
+-05371 {
+-05372         dwc_write_reg32(&core_if->core_global_regs->guid, val);
+-05373 }
+-05374 
+-05375 uint32_t dwc_otg_get_hptxfsiz(dwc_otg_core_if_t * core_if)
+-05376 {
+-05377         return dwc_read_reg32(&core_if->core_global_regs->hptxfsiz);
+-05378 }
+-
Generated on Tue May 5 02:22:48 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++
Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
++

dwc_otg_cil.c

Go to the documentation of this file.
00001 /* ==========================================================================
++00002  * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_cil.c $
++00003  * $Revision: #189 $
++00004  * $Date: 2011/10/24 $
++00005  * $Change: 1871160 $
++00006  *
++00007  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
++00008  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
++00009  * otherwise expressly agreed to in writing between Synopsys and you.
++00010  *
++00011  * The Software IS NOT an item of Licensed Software or Licensed Product under
++00012  * any End User Software License Agreement or Agreement for Licensed Product
++00013  * with Synopsys or any supplement thereto. You are permitted to use and
++00014  * redistribute this Software in source and binary forms, with or without
++00015  * modification, provided that redistributions of source code must retain this
++00016  * notice. You may not view, use, disclose, copy or distribute this file or
++00017  * any information contained herein except pursuant to this license grant from
++00018  * Synopsys. If you do not agree with this notice, including the disclaimer
++00019  * below, then you are not authorized to use the Software.
++00020  *
++00021  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
++00022  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++00023  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++00024  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
++00025  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++00026  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
++00027  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
++00028  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
++00029  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
++00030  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
++00031  * DAMAGE.
++00032  * ========================================================================== */
++00033 
++00060 #include "dwc_os.h"
++00061 #include "dwc_otg_regs.h"
++00062 #include "dwc_otg_cil.h"
++00063 
++00064 static int dwc_otg_setup_params(dwc_otg_core_if_t * core_if);
++00065 
++00078 dwc_otg_core_if_t *dwc_otg_cil_init(const uint32_t * reg_base_addr)
++00079 {
++00080         dwc_otg_core_if_t *core_if = 0;
++00081         dwc_otg_dev_if_t *dev_if = 0;
++00082         dwc_otg_host_if_t *host_if = 0;
++00083         uint8_t *reg_base = (uint8_t *) reg_base_addr;
++00084         int i = 0;
++00085 
++00086         DWC_DEBUGPL(DBG_CILV, "%s(%p)\n", __func__, reg_base_addr);
++00087 
++00088         core_if = DWC_ALLOC(sizeof(dwc_otg_core_if_t));
++00089 
++00090         if (core_if == NULL) {
++00091                 DWC_DEBUGPL(DBG_CIL,
++00092                             "Allocation of dwc_otg_core_if_t failed\n");
++00093                 return 0;
++00094         }
++00095         core_if->core_global_regs = (dwc_otg_core_global_regs_t *) reg_base;
++00096 
++00097         /*
++00098          * Allocate the Device Mode structures.
++00099          */
++00100         dev_if = DWC_ALLOC(sizeof(dwc_otg_dev_if_t));
++00101 
++00102         if (dev_if == NULL) {
++00103                 DWC_DEBUGPL(DBG_CIL, "Allocation of dwc_otg_dev_if_t failed\n");
++00104                 DWC_FREE(core_if);
++00105                 return 0;
++00106         }
++00107 
++00108         dev_if->dev_global_regs =
++00109             (dwc_otg_device_global_regs_t *) (reg_base +
++00110                                               DWC_DEV_GLOBAL_REG_OFFSET);
++00111 
++00112         for (i = 0; i < MAX_EPS_CHANNELS; i++) {
++00113                 dev_if->in_ep_regs[i] = (dwc_otg_dev_in_ep_regs_t *)
++00114                     (reg_base + DWC_DEV_IN_EP_REG_OFFSET +
++00115                      (i * DWC_EP_REG_OFFSET));
++00116 
++00117                 dev_if->out_ep_regs[i] = (dwc_otg_dev_out_ep_regs_t *)
++00118                     (reg_base + DWC_DEV_OUT_EP_REG_OFFSET +
++00119                      (i * DWC_EP_REG_OFFSET));
++00120                 DWC_DEBUGPL(DBG_CILV, "in_ep_regs[%d]->diepctl=%p\n",
++00121                             i, &dev_if->in_ep_regs[i]->diepctl);
++00122                 DWC_DEBUGPL(DBG_CILV, "out_ep_regs[%d]->doepctl=%p\n",
++00123                             i, &dev_if->out_ep_regs[i]->doepctl);
++00124         }
++00125 
++00126         dev_if->speed = 0;      // unknown
++00127 
++00128         core_if->dev_if = dev_if;
++00129 
++00130         /*
++00131          * Allocate the Host Mode structures.
++00132          */
++00133         host_if = DWC_ALLOC(sizeof(dwc_otg_host_if_t));
++00134 
++00135         if (host_if == NULL) {
++00136                 DWC_DEBUGPL(DBG_CIL,
++00137                             "Allocation of dwc_otg_host_if_t failed\n");
++00138                 DWC_FREE(dev_if);
++00139                 DWC_FREE(core_if);
++00140                 return 0;
++00141         }
++00142 
++00143         host_if->host_global_regs = (dwc_otg_host_global_regs_t *)
++00144             (reg_base + DWC_OTG_HOST_GLOBAL_REG_OFFSET);
++00145 
++00146         host_if->hprt0 =
++00147             (uint32_t *) (reg_base + DWC_OTG_HOST_PORT_REGS_OFFSET);
++00148 
++00149         for (i = 0; i < MAX_EPS_CHANNELS; i++) {
++00150                 host_if->hc_regs[i] = (dwc_otg_hc_regs_t *)
++00151                     (reg_base + DWC_OTG_HOST_CHAN_REGS_OFFSET +
++00152                      (i * DWC_OTG_CHAN_REGS_OFFSET));
++00153                 DWC_DEBUGPL(DBG_CILV, "hc_reg[%d]->hcchar=%p\n",
++00154                             i, &host_if->hc_regs[i]->hcchar);
++00155         }
++00156 
++00157         host_if->num_host_channels = MAX_EPS_CHANNELS;
++00158         core_if->host_if = host_if;
++00159 
++00160         for (i = 0; i < MAX_EPS_CHANNELS; i++) {
++00161                 core_if->data_fifo[i] =
++00162                     (uint32_t *) (reg_base + DWC_OTG_DATA_FIFO_OFFSET +
++00163                                   (i * DWC_OTG_DATA_FIFO_SIZE));
++00164                 DWC_DEBUGPL(DBG_CILV, "data_fifo[%d]=0x%08lx\n",
++00165                             i, (unsigned long)core_if->data_fifo[i]);
++00166         }
++00167 
++00168         core_if->pcgcctl = (uint32_t *) (reg_base + DWC_OTG_PCGCCTL_OFFSET);
++00169 
++00170         /* Initiate lx_state to L3 disconnected state */
++00171         core_if->lx_state = DWC_OTG_L3;
++00172         /*
++00173          * Store the contents of the hardware configuration registers here for
++00174          * easy access later.
++00175          */
++00176         core_if->hwcfg1.d32 =
++00177             DWC_READ_REG32(&core_if->core_global_regs->ghwcfg1);
++00178         core_if->hwcfg2.d32 =
++00179             DWC_READ_REG32(&core_if->core_global_regs->ghwcfg2);
++00180         core_if->hwcfg3.d32 =
++00181             DWC_READ_REG32(&core_if->core_global_regs->ghwcfg3);
++00182         core_if->hwcfg4.d32 =
++00183             DWC_READ_REG32(&core_if->core_global_regs->ghwcfg4);
++00184 
++00185         /* Force host mode to get HPTXFSIZ exact power on value */
++00186         {
++00187                 gusbcfg_data_t gusbcfg = {.d32 = 0 };
++00188                 gusbcfg.d32 =  DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
++00189                 gusbcfg.b.force_host_mode = 1;
++00190                 DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, gusbcfg.d32);
++00191                 dwc_mdelay(100); 
++00192                 core_if->hptxfsiz.d32 =
++00193                 DWC_READ_REG32(&core_if->core_global_regs->hptxfsiz);
++00194                 gusbcfg.d32 =  DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
++00195                 gusbcfg.b.force_host_mode = 0;
++00196                 DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, gusbcfg.d32);
++00197                 dwc_mdelay(100); 
++00198         }
++00199 
++00200         DWC_DEBUGPL(DBG_CILV, "hwcfg1=%08x\n", core_if->hwcfg1.d32);
++00201         DWC_DEBUGPL(DBG_CILV, "hwcfg2=%08x\n", core_if->hwcfg2.d32);
++00202         DWC_DEBUGPL(DBG_CILV, "hwcfg3=%08x\n", core_if->hwcfg3.d32);
++00203         DWC_DEBUGPL(DBG_CILV, "hwcfg4=%08x\n", core_if->hwcfg4.d32);
++00204 
++00205         core_if->hcfg.d32 =
++00206             DWC_READ_REG32(&core_if->host_if->host_global_regs->hcfg);
++00207         core_if->dcfg.d32 =
++00208             DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg);
++00209 
++00210         DWC_DEBUGPL(DBG_CILV, "hcfg=%08x\n", core_if->hcfg.d32);
++00211         DWC_DEBUGPL(DBG_CILV, "dcfg=%08x\n", core_if->dcfg.d32);
++00212 
++00213         DWC_DEBUGPL(DBG_CILV, "op_mode=%0x\n", core_if->hwcfg2.b.op_mode);
++00214         DWC_DEBUGPL(DBG_CILV, "arch=%0x\n", core_if->hwcfg2.b.architecture);
++00215         DWC_DEBUGPL(DBG_CILV, "num_dev_ep=%d\n", core_if->hwcfg2.b.num_dev_ep);
++00216         DWC_DEBUGPL(DBG_CILV, "num_host_chan=%d\n",
++00217                     core_if->hwcfg2.b.num_host_chan);
++00218         DWC_DEBUGPL(DBG_CILV, "nonperio_tx_q_depth=0x%0x\n",
++00219                     core_if->hwcfg2.b.nonperio_tx_q_depth);
++00220         DWC_DEBUGPL(DBG_CILV, "host_perio_tx_q_depth=0x%0x\n",
++00221                     core_if->hwcfg2.b.host_perio_tx_q_depth);
++00222         DWC_DEBUGPL(DBG_CILV, "dev_token_q_depth=0x%0x\n",
++00223                     core_if->hwcfg2.b.dev_token_q_depth);
++00224 
++00225         DWC_DEBUGPL(DBG_CILV, "Total FIFO SZ=%d\n",
++00226                     core_if->hwcfg3.b.dfifo_depth);
++00227         DWC_DEBUGPL(DBG_CILV, "xfer_size_cntr_width=%0x\n",
++00228                     core_if->hwcfg3.b.xfer_size_cntr_width);
++00229 
++00230         /*
++00231          * Set the SRP sucess bit for FS-I2c
++00232          */
++00233         core_if->srp_success = 0;
++00234         core_if->srp_timer_started = 0;
++00235 
++00236         /*
++00237          * Create new workqueue and init works
++00238          */
++00239         core_if->wq_otg = DWC_WORKQ_ALLOC("dwc_otg");
++00240         if (core_if->wq_otg == 0) {
++00241                 DWC_WARN("DWC_WORKQ_ALLOC failed\n");
++00242                 DWC_FREE(host_if);
++00243                 DWC_FREE(dev_if);
++00244                 DWC_FREE(core_if);
++00245                 return 0;
++00246         }
++00247 
++00248         core_if->snpsid = DWC_READ_REG32(&core_if->core_global_regs->gsnpsid);
++00249 
++00250         DWC_PRINTF("Core Release: %x.%x%x%x\n",
++00251                    (core_if->snpsid >> 12 & 0xF),
++00252                    (core_if->snpsid >> 8 & 0xF),
++00253                    (core_if->snpsid >> 4 & 0xF), (core_if->snpsid & 0xF));
++00254 
++00255         core_if->wkp_timer = DWC_TIMER_ALLOC("Wake Up Timer",
++00256                                              w_wakeup_detected, core_if);
++00257         if (core_if->wkp_timer == 0) {
++00258                 DWC_WARN("DWC_TIMER_ALLOC failed\n");
++00259                 DWC_FREE(host_if);
++00260                 DWC_FREE(dev_if);
++00261                 DWC_WORKQ_FREE(core_if->wq_otg);
++00262                 DWC_FREE(core_if);
++00263                 return 0;
++00264         }
++00265 
++00266         if (dwc_otg_setup_params(core_if)) {
++00267                 DWC_WARN("Error while setting core params\n");
++00268         }
++00269 
++00270         core_if->hibernation_suspend = 0;
++00271 
++00273         dwc_otg_adp_init(core_if);
++00274         
++00275         return core_if;
++00276 }
++00277 
++00285 void dwc_otg_cil_remove(dwc_otg_core_if_t * core_if)
++00286 {
++00287         /* Disable all interrupts */
++00288         DWC_MODIFY_REG32(&core_if->core_global_regs->gahbcfg, 1, 0);
++00289         DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, 0);
++00290 
++00291         if (core_if->wq_otg) {
++00292                 DWC_WORKQ_WAIT_WORK_DONE(core_if->wq_otg, 500);
++00293                 DWC_WORKQ_FREE(core_if->wq_otg);
++00294         }
++00295         if (core_if->dev_if) {
++00296                 DWC_FREE(core_if->dev_if);
++00297         }
++00298         if (core_if->host_if) {
++00299                 DWC_FREE(core_if->host_if);
++00300         }
++00301 
++00303         dwc_otg_adp_remove(core_if);
++00304         if (core_if->core_params) {
++00305                 DWC_FREE(core_if->core_params);
++00306         }
++00307         if (core_if->wkp_timer) {
++00308                 DWC_TIMER_FREE(core_if->wkp_timer);
++00309         }
++00310         if (core_if->srp_timer) {
++00311                 DWC_TIMER_FREE(core_if->srp_timer);
++00312         }
++00313         DWC_FREE(core_if);
++00314 }
++00315 
++00322 void dwc_otg_enable_global_interrupts(dwc_otg_core_if_t * core_if)
++00323 {
++00324         gahbcfg_data_t ahbcfg = {.d32 = 0 };
++00325         ahbcfg.b.glblintrmsk = 1;       /* Enable interrupts */
++00326         DWC_MODIFY_REG32(&core_if->core_global_regs->gahbcfg, 0, ahbcfg.d32);
++00327 }
++00328 
++00335 void dwc_otg_disable_global_interrupts(dwc_otg_core_if_t * core_if)
++00336 {
++00337         gahbcfg_data_t ahbcfg = {.d32 = 0 };
++00338         ahbcfg.b.glblintrmsk = 1;       /* Disable interrupts */
++00339         DWC_MODIFY_REG32(&core_if->core_global_regs->gahbcfg, ahbcfg.d32, 0);
++00340 }
++00341 
++00349 static void dwc_otg_enable_common_interrupts(dwc_otg_core_if_t * core_if)
++00350 {
++00351         dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
++00352         gintmsk_data_t intr_mask = {.d32 = 0 };
++00353 
++00354         /* Clear any pending OTG Interrupts */
++00355         DWC_WRITE_REG32(&global_regs->gotgint, 0xFFFFFFFF);
++00356 
++00357         /* Clear any pending interrupts */
++00358         DWC_WRITE_REG32(&global_regs->gintsts, 0xFFFFFFFF);
++00359 
++00360         /*
++00361          * Enable the interrupts in the GINTMSK.
++00362          */
++00363         intr_mask.b.modemismatch = 1;
++00364         intr_mask.b.otgintr = 1;
++00365 
++00366         if (!core_if->dma_enable) {
++00367                 intr_mask.b.rxstsqlvl = 1;
++00368         }
++00369 
++00370         intr_mask.b.conidstschng = 1;
++00371         intr_mask.b.wkupintr = 1;
++00372         intr_mask.b.disconnect = 0;
++00373         intr_mask.b.usbsuspend = 1;
++00374         intr_mask.b.sessreqintr = 1;
++00375 #ifdef CONFIG_USB_DWC_OTG_LPM
++00376         if (core_if->core_params->lpm_enable) {
++00377                 intr_mask.b.lpmtranrcvd = 1;
++00378         }
++00379 #endif
++00380         DWC_WRITE_REG32(&global_regs->gintmsk, intr_mask.d32);
++00381 }
++00382 
++00383 /*
++00384  * The restore operation is modified to support Synopsys Emulated Powerdown and
++00385  * Hibernation. This function is for exiting from Device mode hibernation by
++00386  * Host Initiated Resume/Reset and Device Initiated Remote-Wakeup.
++00387  * @param core_if Programming view of DWC_otg controller.
++00388  * @param rem_wakeup - indicates whether resume is initiated by Device or Host.
++00389  * @param reset - indicates whether resume is initiated by Reset.
++00390  */
++00391 int dwc_otg_device_hibernation_restore(dwc_otg_core_if_t * core_if,
++00392                                        int rem_wakeup, int reset)
++00393 {
++00394         gpwrdn_data_t gpwrdn = {.d32 = 0 };
++00395         pcgcctl_data_t pcgcctl = {.d32 = 0 };
++00396         dctl_data_t dctl = {.d32 = 0 };
++00397 
++00398         int timeout = 2000;
++00399 
++00400         if (!core_if->hibernation_suspend) {
++00401                 DWC_PRINTF("Already exited from Hibernation\n");
++00402                 return 1;
++00403         }
++00404 
++00405         DWC_DEBUGPL(DBG_PCD, "%s called\n", __FUNCTION__);
++00406         /* Switch-on voltage to the core */
++00407         gpwrdn.b.pwrdnswtch = 1;
++00408         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
++00409         dwc_udelay(10);
++00410 
++00411         /* Reset core */
++00412         gpwrdn.d32 = 0;
++00413         gpwrdn.b.pwrdnrstn = 1;
++00414         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
++00415         dwc_udelay(10);
++00416 
++00417         /* Assert Restore signal */
++00418         gpwrdn.d32 = 0;
++00419         gpwrdn.b.restore = 1;
++00420         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
++00421         dwc_udelay(10);
++00422 
++00423         /* Disable power clamps */
++00424         gpwrdn.d32 = 0;
++00425         gpwrdn.b.pwrdnclmp = 1;
++00426         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
++00427 
++00428         if (rem_wakeup) {
++00429                 dwc_udelay(70);
++00430         }
++00431 
++00432         /* Deassert Reset core */
++00433         gpwrdn.d32 = 0;
++00434         gpwrdn.b.pwrdnrstn = 1;
++00435         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
++00436         dwc_udelay(10);
++00437 
++00438         /* Disable PMU interrupt */
++00439         gpwrdn.d32 = 0;
++00440         gpwrdn.b.pmuintsel = 1;
++00441         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
++00442 
++00443         /* Mask interrupts from gpwrdn */
++00444         gpwrdn.d32 = 0;
++00445         gpwrdn.b.connect_det_msk = 1;
++00446         gpwrdn.b.srp_det_msk = 1;
++00447         gpwrdn.b.disconn_det_msk = 1;
++00448         gpwrdn.b.rst_det_msk = 1;
++00449         gpwrdn.b.lnstchng_msk = 1;
++00450         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
++00451 
++00452         /* Indicates that we are going out from hibernation */
++00453         core_if->hibernation_suspend = 0;
++00454 
++00455         /*
++00456          * Set Restore Essential Regs bit in PCGCCTL register, restore_mode = 1
++00457          * indicates restore from remote_wakeup
++00458          */
++00459         restore_essential_regs(core_if, rem_wakeup, 0);
++00460 
++00461         /*
++00462          * Wait a little for seeing new value of variable hibernation_suspend if
++00463          * Restore done interrupt received before polling
++00464          */
++00465         dwc_udelay(10);
++00466 
++00467         if (core_if->hibernation_suspend == 0) {
++00468                 /*
++00469                  * Wait For Restore_done Interrupt. This mechanism of polling the 
++00470                  * interrupt is introduced to avoid any possible race conditions
++00471                  */
++00472                 do {
++00473                         gintsts_data_t gintsts;
++00474                         gintsts.d32 =
++00475                             DWC_READ_REG32(&core_if->core_global_regs->gintsts);
++00476                         if (gintsts.b.restoredone) {
++00477                                 gintsts.d32 = 0;
++00478                                 gintsts.b.restoredone = 1;
++00479                                 DWC_WRITE_REG32(&core_if->core_global_regs->
++00480                                                 gintsts, gintsts.d32);
++00481                                 DWC_PRINTF("Restore Done Interrupt seen\n");
++00482                                 break;
++00483                         }
++00484                         dwc_udelay(10);
++00485                 } while (--timeout);
++00486                 if (!timeout) {
++00487                         DWC_PRINTF("Restore Done interrupt wasn't generated here\n");
++00488                 }
++00489         }
++00490         /* Clear all pending interupts */
++00491         DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
++00492 
++00493         /* De-assert Restore */
++00494         gpwrdn.d32 = 0;
++00495         gpwrdn.b.restore = 1;
++00496         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
++00497         dwc_udelay(10);
++00498 
++00499         if (!rem_wakeup) {
++00500                 pcgcctl.d32 = 0;
++00501                 pcgcctl.b.rstpdwnmodule = 1;
++00502                 DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32, 0);
++00503         }
++00504 
++00505         /* Restore GUSBCFG and DCFG */
++00506         DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg,
++00507                         core_if->gr_backup->gusbcfg_local);
++00508         DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dcfg,
++00509                         core_if->dr_backup->dcfg);
++00510 
++00511         /* De-assert Wakeup Logic */
++00512         gpwrdn.d32 = 0;
++00513         gpwrdn.b.pmuactv = 1;
++00514         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
++00515         dwc_udelay(10);
++00516 
++00517         if (!rem_wakeup) {
++00518                 /* Set Device programming done bit */
++00519                 dctl.b.pwronprgdone = 1;
++00520                 DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, 0, dctl.d32);
++00521         } else {
++00522                 /* Start Remote Wakeup Signaling */
++00523                 dctl.d32 = core_if->dr_backup->dctl;
++00524                 dctl.b.rmtwkupsig = 1;
++00525                 DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32);
++00526         }
++00527 
++00528         dwc_mdelay(2);
++00529         /* Clear all pending interupts */
++00530         DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
++00531 
++00532         /* Restore global registers */
++00533         dwc_otg_restore_global_regs(core_if);
++00534         /* Restore device global registers */
++00535         dwc_otg_restore_dev_regs(core_if, rem_wakeup);
++00536 
++00537         if (rem_wakeup) {
++00538                 dwc_mdelay(7);
++00539                 dctl.d32 = 0;
++00540                 dctl.b.rmtwkupsig = 1;
++00541                 DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32, 0);
++00542         }
++00543 
++00544         core_if->hibernation_suspend = 0;
++00545         /* The core will be in ON STATE */
++00546         core_if->lx_state = DWC_OTG_L0;
++00547         DWC_PRINTF("Hibernation recovery completes here\n");
++00548 
++00549         return 1;
++00550 }
++00551 
++00552 /*
++00553  * The restore operation is modified to support Synopsys Emulated Powerdown and
++00554  * Hibernation. This function is for exiting from Host mode hibernation by
++00555  * Host Initiated Resume/Reset and Device Initiated Remote-Wakeup.
++00556  * @param core_if Programming view of DWC_otg controller.
++00557  * @param rem_wakeup - indicates whether resume is initiated by Device or Host.
++00558  * @param reset - indicates whether resume is initiated by Reset.
++00559  */
++00560 int dwc_otg_host_hibernation_restore(dwc_otg_core_if_t * core_if,
++00561                                      int rem_wakeup, int reset)
++00562 {
++00563         gpwrdn_data_t gpwrdn = {.d32 = 0 };
++00564         hprt0_data_t hprt0 = {.d32 = 0 };
++00565 
++00566         int timeout = 2000;
++00567 
++00568         DWC_DEBUGPL(DBG_HCD, "%s called\n", __FUNCTION__);
++00569         /* Switch-on voltage to the core */
++00570         gpwrdn.b.pwrdnswtch = 1;
++00571         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
++00572         dwc_udelay(10);
++00573 
++00574         /* Reset core */
++00575         gpwrdn.d32 = 0;
++00576         gpwrdn.b.pwrdnrstn = 1;
++00577         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
++00578         dwc_udelay(10);
++00579 
++00580         /* Assert Restore signal */
++00581         gpwrdn.d32 = 0;
++00582         gpwrdn.b.restore = 1;
++00583         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
++00584         dwc_udelay(10);
++00585 
++00586         /* Disable power clamps */
++00587         gpwrdn.d32 = 0;
++00588         gpwrdn.b.pwrdnclmp = 1;
++00589         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
++00590 
++00591         if (!rem_wakeup) {
++00592                 dwc_udelay(50);
++00593         }
++00594 
++00595         /* Deassert Reset core */
++00596         gpwrdn.d32 = 0;
++00597         gpwrdn.b.pwrdnrstn = 1;
++00598         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
++00599         dwc_udelay(10);
++00600 
++00601         /* Disable PMU interrupt */
++00602         gpwrdn.d32 = 0;
++00603         gpwrdn.b.pmuintsel = 1;
++00604         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
++00605 
++00606         gpwrdn.d32 = 0;
++00607         gpwrdn.b.connect_det_msk = 1;
++00608         gpwrdn.b.srp_det_msk = 1;
++00609         gpwrdn.b.disconn_det_msk = 1;
++00610         gpwrdn.b.rst_det_msk = 1;
++00611         gpwrdn.b.lnstchng_msk = 1;
++00612         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
++00613 
++00614         /* Indicates that we are going out from hibernation */
++00615         core_if->hibernation_suspend = 0;
++00616 
++00617         /* Set Restore Essential Regs bit in PCGCCTL register */
++00618         restore_essential_regs(core_if, rem_wakeup, 1);
++00619 
++00620         /* Wait a little for seeing new value of variable hibernation_suspend if
++00621          * Restore done interrupt received before polling */
++00622         dwc_udelay(10);
++00623 
++00624         if (core_if->hibernation_suspend == 0) {
++00625                 /* Wait For Restore_done Interrupt. This mechanism of polling the
++00626                  * interrupt is introduced to avoid any possible race conditions
++00627                  */
++00628                 do {
++00629                         gintsts_data_t gintsts;
++00630                         gintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts);
++00631                         if (gintsts.b.restoredone) {
++00632                                 gintsts.d32 = 0;
++00633                                 gintsts.b.restoredone = 1;
++00634                         DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
++00635                                 DWC_DEBUGPL(DBG_HCD,"Restore Done Interrupt seen\n");   
++00636                                 break;
++00637                         }
++00638                         dwc_udelay(10);
++00639                 } while (--timeout);
++00640                 if (!timeout) {
++00641                         DWC_WARN("Restore Done interrupt wasn't generated\n");
++00642                 }
++00643         }
++00644 
++00645         /* Set the flag's value to 0 again after receiving restore done interrupt */
++00646         core_if->hibernation_suspend = 0;
++00647 
++00648         /* This step is not described in functional spec but if not wait for this
++00649          * delay, mismatch interrupts occurred because just after restore core is
++00650          * in Device mode(gintsts.curmode == 0) */
++00651         dwc_mdelay(100);
++00652 
++00653         /* Clear all pending interrupts */
++00654         DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
++00655 
++00656         /* De-assert Restore */
++00657         gpwrdn.d32 = 0;
++00658         gpwrdn.b.restore = 1;
++00659         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
++00660         dwc_udelay(10);
++00661 
++00662         /* Restore GUSBCFG and HCFG */
++00663         DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg,
++00664                         core_if->gr_backup->gusbcfg_local);
++00665         DWC_WRITE_REG32(&core_if->host_if->host_global_regs->hcfg,
++00666                         core_if->hr_backup->hcfg_local);
++00667 
++00668         /* De-assert Wakeup Logic */
++00669         gpwrdn.d32 = 0;
++00670         gpwrdn.b.pmuactv = 1;
++00671         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
++00672         dwc_udelay(10);
++00673 
++00674         /* Start the Resume operation by programming HPRT0 */
++00675         hprt0.d32 = core_if->hr_backup->hprt0_local;
++00676         hprt0.b.prtpwr = 1;
++00677         hprt0.b.prtena = 0;
++00678         hprt0.b.prtsusp = 0;
++00679         DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
++00680 
++00681         DWC_PRINTF("Resume Starts Now\n");
++00682         if (!reset) {           // Indicates it is Resume Operation
++00683                 hprt0.d32 = core_if->hr_backup->hprt0_local;
++00684                 hprt0.b.prtres = 1;
++00685                 hprt0.b.prtpwr = 1;
++00686                 hprt0.b.prtena = 0;
++00687                 hprt0.b.prtsusp = 0;
++00688                 DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
++00689 
++00690                 if (!rem_wakeup)
++00691                         hprt0.b.prtres = 0;
++00692                 /* Wait for Resume time and then program HPRT again */
++00693                 dwc_mdelay(100);
++00694                 DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
++00695 
++00696         } else {                // Indicates it is Reset Operation
++00697                 hprt0.d32 = core_if->hr_backup->hprt0_local;
++00698                 hprt0.b.prtrst = 1;
++00699                 hprt0.b.prtpwr = 1;
++00700                 hprt0.b.prtena = 0;
++00701                 hprt0.b.prtsusp = 0;
++00702                 DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
++00703                 /* Wait for Reset time and then program HPRT again */
++00704                 dwc_mdelay(60);
++00705                 hprt0.b.prtrst = 0;
++00706                 DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
++00707         }
++00708         /* Clear all interrupt status */
++00709         hprt0.d32 = dwc_otg_read_hprt0(core_if);
++00710         hprt0.b.prtconndet = 1;
++00711         hprt0.b.prtenchng = 1;
++00712         DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
++00713 
++00714         /* Clear all pending interupts */
++00715         DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
++00716 
++00717         /* Restore global registers */
++00718         dwc_otg_restore_global_regs(core_if);
++00719         /* Restore host global registers */
++00720         dwc_otg_restore_host_regs(core_if, reset);
++00721 
++00722         /* The core will be in ON STATE */
++00723         core_if->lx_state = DWC_OTG_L0;
++00724         DWC_PRINTF("Hibernation recovery is complete here\n");
++00725         return 0;
++00726 }
++00727 
++00729 int dwc_otg_save_global_regs(dwc_otg_core_if_t * core_if)
++00730 {
++00731         struct dwc_otg_global_regs_backup *gr;
++00732         int i;
++00733 
++00734         gr = core_if->gr_backup;
++00735         if (!gr) {
++00736                 gr = DWC_ALLOC(sizeof(*gr));
++00737                 if (!gr) {
++00738                         return -DWC_E_NO_MEMORY;
++00739                 }
++00740                 core_if->gr_backup = gr;
++00741         }
++00742 
++00743         gr->gotgctl_local = DWC_READ_REG32(&core_if->core_global_regs->gotgctl);
++00744         gr->gintmsk_local = DWC_READ_REG32(&core_if->core_global_regs->gintmsk);
++00745         gr->gahbcfg_local = DWC_READ_REG32(&core_if->core_global_regs->gahbcfg);
++00746         gr->gusbcfg_local = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
++00747         gr->grxfsiz_local = DWC_READ_REG32(&core_if->core_global_regs->grxfsiz);
++00748         gr->gnptxfsiz_local = DWC_READ_REG32(&core_if->core_global_regs->gnptxfsiz);
++00749         gr->hptxfsiz_local = DWC_READ_REG32(&core_if->core_global_regs->hptxfsiz);
++00750 #ifdef CONFIG_USB_DWC_OTG_LPM
++00751         gr->glpmcfg_local = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
++00752 #endif
++00753         gr->gi2cctl_local = DWC_READ_REG32(&core_if->core_global_regs->gi2cctl);
++00754         gr->pcgcctl_local = DWC_READ_REG32(core_if->pcgcctl);
++00755         gr->gdfifocfg_local =
++00756             DWC_READ_REG32(&core_if->core_global_regs->gdfifocfg);
++00757         for (i = 0; i < MAX_EPS_CHANNELS; i++) {
++00758                 gr->dtxfsiz_local[i] =
++00759                     DWC_READ_REG32(&(core_if->core_global_regs->dtxfsiz[i]));
++00760         }
++00761 
++00762         DWC_DEBUGPL(DBG_ANY, "===========Backing Global registers==========\n");
++00763         DWC_DEBUGPL(DBG_ANY, "Backed up gotgctl   = %08x\n", gr->gotgctl_local);
++00764         DWC_DEBUGPL(DBG_ANY, "Backed up gintmsk   = %08x\n", gr->gintmsk_local);
++00765         DWC_DEBUGPL(DBG_ANY, "Backed up gahbcfg   = %08x\n", gr->gahbcfg_local);
++00766         DWC_DEBUGPL(DBG_ANY, "Backed up gusbcfg   = %08x\n", gr->gusbcfg_local);
++00767         DWC_DEBUGPL(DBG_ANY, "Backed up grxfsiz   = %08x\n", gr->grxfsiz_local);
++00768         DWC_DEBUGPL(DBG_ANY, "Backed up gnptxfsiz = %08x\n",
++00769                     gr->gnptxfsiz_local);
++00770         DWC_DEBUGPL(DBG_ANY, "Backed up hptxfsiz  = %08x\n",
++00771                     gr->hptxfsiz_local);
++00772 #ifdef CONFIG_USB_DWC_OTG_LPM
++00773         DWC_DEBUGPL(DBG_ANY, "Backed up glpmcfg   = %08x\n", gr->glpmcfg_local);
++00774 #endif
++00775         DWC_DEBUGPL(DBG_ANY, "Backed up gi2cctl   = %08x\n", gr->gi2cctl_local);
++00776         DWC_DEBUGPL(DBG_ANY, "Backed up pcgcctl   = %08x\n", gr->pcgcctl_local);
++00777         DWC_DEBUGPL(DBG_ANY,"Backed up gdfifocfg   = %08x\n",gr->gdfifocfg_local);
++00778 
++00779         return 0;
++00780 }
++00781 
++00783 int dwc_otg_save_gintmsk_reg(dwc_otg_core_if_t * core_if)
++00784 {
++00785         struct dwc_otg_global_regs_backup *gr;
++00786 
++00787         gr = core_if->gr_backup;
++00788         if (!gr) {
++00789                 gr = DWC_ALLOC(sizeof(*gr));
++00790                 if (!gr) {
++00791                         return -DWC_E_NO_MEMORY;
++00792                 }
++00793                 core_if->gr_backup = gr;
++00794         }
++00795 
++00796         gr->gintmsk_local = DWC_READ_REG32(&core_if->core_global_regs->gintmsk);
++00797 
++00798         DWC_DEBUGPL(DBG_ANY,"=============Backing GINTMSK registers============\n");
++00799         DWC_DEBUGPL(DBG_ANY, "Backed up gintmsk   = %08x\n", gr->gintmsk_local);
++00800 
++00801         return 0;
++00802 }
++00803 
++00804 int dwc_otg_save_dev_regs(dwc_otg_core_if_t * core_if)
++00805 {
++00806         struct dwc_otg_dev_regs_backup *dr;
++00807         int i;
++00808 
++00809         dr = core_if->dr_backup;
++00810         if (!dr) {
++00811                 dr = DWC_ALLOC(sizeof(*dr));
++00812                 if (!dr) {
++00813                         return -DWC_E_NO_MEMORY;
++00814                 }
++00815                 core_if->dr_backup = dr;
++00816         }
++00817 
++00818         dr->dcfg = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg);
++00819         dr->dctl = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dctl);
++00820         dr->daintmsk =
++00821             DWC_READ_REG32(&core_if->dev_if->dev_global_regs->daintmsk);
++00822         dr->diepmsk =
++00823             DWC_READ_REG32(&core_if->dev_if->dev_global_regs->diepmsk);
++00824         dr->doepmsk =
++00825             DWC_READ_REG32(&core_if->dev_if->dev_global_regs->doepmsk);
++00826 
++00827         for (i = 0; i < core_if->dev_if->num_in_eps; ++i) {
++00828                 dr->diepctl[i] =
++00829                     DWC_READ_REG32(&core_if->dev_if->in_ep_regs[i]->diepctl);
++00830                 dr->dieptsiz[i] =
++00831                     DWC_READ_REG32(&core_if->dev_if->in_ep_regs[i]->dieptsiz);
++00832                 dr->diepdma[i] =
++00833                     DWC_READ_REG32(&core_if->dev_if->in_ep_regs[i]->diepdma);
++00834         }
++00835 
++00836         DWC_DEBUGPL(DBG_ANY,
++00837                     "=============Backing Host registers==============\n");
++00838         DWC_DEBUGPL(DBG_ANY, "Backed up dcfg            = %08x\n", dr->dcfg);
++00839         DWC_DEBUGPL(DBG_ANY, "Backed up dctl        = %08x\n", dr->dctl);
++00840         DWC_DEBUGPL(DBG_ANY, "Backed up daintmsk            = %08x\n",
++00841                     dr->daintmsk);
++00842         DWC_DEBUGPL(DBG_ANY, "Backed up diepmsk        = %08x\n", dr->diepmsk);
++00843         DWC_DEBUGPL(DBG_ANY, "Backed up doepmsk        = %08x\n", dr->doepmsk);
++00844         for (i = 0; i < core_if->dev_if->num_in_eps; ++i) {
++00845                 DWC_DEBUGPL(DBG_ANY, "Backed up diepctl[%d]        = %08x\n", i,
++00846                             dr->diepctl[i]);
++00847                 DWC_DEBUGPL(DBG_ANY, "Backed up dieptsiz[%d]        = %08x\n",
++00848                             i, dr->dieptsiz[i]);
++00849                 DWC_DEBUGPL(DBG_ANY, "Backed up diepdma[%d]        = %08x\n", i,
++00850                             dr->diepdma[i]);
++00851         }
++00852 
++00853         return 0;
++00854 }
++00855 
++00856 int dwc_otg_save_host_regs(dwc_otg_core_if_t * core_if)
++00857 {
++00858         struct dwc_otg_host_regs_backup *hr;
++00859         int i;
++00860 
++00861         hr = core_if->hr_backup;
++00862         if (!hr) {
++00863                 hr = DWC_ALLOC(sizeof(*hr));
++00864                 if (!hr) {
++00865                         return -DWC_E_NO_MEMORY;
++00866                 }
++00867                 core_if->hr_backup = hr;
++00868         }
++00869 
++00870         hr->hcfg_local =
++00871             DWC_READ_REG32(&core_if->host_if->host_global_regs->hcfg);
++00872         hr->haintmsk_local =
++00873             DWC_READ_REG32(&core_if->host_if->host_global_regs->haintmsk);
++00874         for (i = 0; i < dwc_otg_get_param_host_channels(core_if); ++i) {
++00875                 hr->hcintmsk_local[i] =
++00876                     DWC_READ_REG32(&core_if->host_if->hc_regs[i]->hcintmsk);
++00877         }
++00878         hr->hprt0_local = DWC_READ_REG32(core_if->host_if->hprt0);
++00879         hr->hfir_local =
++00880             DWC_READ_REG32(&core_if->host_if->host_global_regs->hfir);
++00881 
++00882         DWC_DEBUGPL(DBG_ANY,
++00883                     "=============Backing Host registers===============\n");
++00884         DWC_DEBUGPL(DBG_ANY, "Backed up hcfg            = %08x\n",
++00885                     hr->hcfg_local);
++00886         DWC_DEBUGPL(DBG_ANY, "Backed up haintmsk = %08x\n", hr->haintmsk_local);
++00887         for (i = 0; i < dwc_otg_get_param_host_channels(core_if); ++i) {
++00888                 DWC_DEBUGPL(DBG_ANY, "Backed up hcintmsk[%02d]=%08x\n", i,
++00889                             hr->hcintmsk_local[i]);
++00890         }
++00891         DWC_DEBUGPL(DBG_ANY, "Backed up hprt0           = %08x\n",
++00892                     hr->hprt0_local);
++00893         DWC_DEBUGPL(DBG_ANY, "Backed up hfir           = %08x\n",
++00894                     hr->hfir_local);
++00895 
++00896         return 0;
++00897 }
++00898 
++00899 int dwc_otg_restore_global_regs(dwc_otg_core_if_t *core_if)
++00900 {
++00901         struct dwc_otg_global_regs_backup *gr;
++00902         int i;
++00903 
++00904         gr = core_if->gr_backup;
++00905         if (!gr) {
++00906                 return -DWC_E_INVALID;
++00907         }
++00908    
++00909         DWC_WRITE_REG32(&core_if->core_global_regs->gotgctl, gr->gotgctl_local);
++00910         DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, gr->gintmsk_local);
++00911         DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, gr->gusbcfg_local);
++00912         DWC_WRITE_REG32(&core_if->core_global_regs->gahbcfg, gr->gahbcfg_local);
++00913         DWC_WRITE_REG32(&core_if->core_global_regs->grxfsiz, gr->grxfsiz_local);
++00914         DWC_WRITE_REG32(&core_if->core_global_regs->gnptxfsiz,
++00915                         gr->gnptxfsiz_local);
++00916         DWC_WRITE_REG32(&core_if->core_global_regs->hptxfsiz,
++00917                         gr->hptxfsiz_local);
++00918         DWC_WRITE_REG32(&core_if->core_global_regs->gdfifocfg,
++00919                         gr->gdfifocfg_local);
++00920         for (i = 0; i < MAX_EPS_CHANNELS; i++) {
++00921                 DWC_WRITE_REG32(&core_if->core_global_regs->dtxfsiz[i],
++00922                                 gr->dtxfsiz_local[i]);
++00923         }
++00924 
++00925         DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
++00926         DWC_WRITE_REG32(core_if->host_if->hprt0, 0x0000100A);
++00927         DWC_WRITE_REG32(&core_if->core_global_regs->gahbcfg,
++00928                         (gr->gahbcfg_local));
++00929         return 0;
++00930 }
++00931 
++00932 int dwc_otg_restore_dev_regs(dwc_otg_core_if_t * core_if, int rem_wakeup)
++00933 {
++00934         struct dwc_otg_dev_regs_backup *dr;
++00935         int i;
++00936 
++00937         dr = core_if->dr_backup;
++00938 
++00939         if (!dr) {
++00940                 return -DWC_E_INVALID;
++00941         }
++00942 
++00943         if (!rem_wakeup)
++00944         {
++00945                 DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl, dr->dctl);
++00946         }
++00947         
++00948         DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->daintmsk, dr->daintmsk);
++00949         DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->diepmsk, dr->diepmsk);
++00950         DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->doepmsk, dr->doepmsk);
++00951 
++00952         for (i = 0; i < core_if->dev_if->num_in_eps; ++i) {
++00953                 DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[i]->diepctl, dr->diepctl[i]);
++00954                 DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[i]->dieptsiz, dr->dieptsiz[i]);
++00955                 DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[i]->diepdma, dr->diepdma[i]);
++00956         }
++00957         
++00958         return 0;
++00959 }
++00960 
++00961 int dwc_otg_restore_host_regs(dwc_otg_core_if_t * core_if, int reset)
++00962 {
++00963         struct dwc_otg_host_regs_backup *hr;
++00964         int i;
++00965         hr = core_if->hr_backup;
++00966 
++00967         if (!hr) {
++00968                 return -DWC_E_INVALID;
++00969         }
++00970 
++00971         DWC_WRITE_REG32(&core_if->host_if->host_global_regs->hcfg, hr->hcfg_local);
++00972         //if (!reset)
++00973         //{
++00974         //      DWC_WRITE_REG32(&core_if->host_if->host_global_regs->hfir, hr->hfir_local);
++00975         //}
++00976 
++00977         DWC_WRITE_REG32(&core_if->host_if->host_global_regs->haintmsk,
++00978                         hr->haintmsk_local);
++00979         for (i = 0; i < dwc_otg_get_param_host_channels(core_if); ++i) {
++00980                 DWC_WRITE_REG32(&core_if->host_if->hc_regs[i]->hcintmsk,
++00981                                 hr->hcintmsk_local[i]);
++00982         }
++00983 
++00984         return 0;
++00985 }
++00986 
++00987 int restore_lpm_i2c_regs(dwc_otg_core_if_t * core_if)
++00988 {
++00989         struct dwc_otg_global_regs_backup *gr;
++00990 
++00991         gr = core_if->gr_backup;
++00992 
++00993         /* Restore values for LPM and I2C */
++00994 #ifdef CONFIG_USB_DWC_OTG_LPM
++00995         DWC_WRITE_REG32(&core_if->core_global_regs->glpmcfg, gr->glpmcfg_local);
++00996 #endif
++00997         DWC_WRITE_REG32(&core_if->core_global_regs->gi2cctl, gr->gi2cctl_local);
++00998 
++00999         return 0;
++01000 }
++01001 
++01002 int restore_essential_regs(dwc_otg_core_if_t * core_if, int rmode, int is_host)
++01003 {
++01004         struct dwc_otg_global_regs_backup *gr;
++01005         pcgcctl_data_t pcgcctl = {.d32 = 0 };
++01006         gahbcfg_data_t gahbcfg = {.d32 = 0 };
++01007         gusbcfg_data_t gusbcfg = {.d32 = 0 };
++01008         gintmsk_data_t gintmsk = {.d32 = 0 };
++01009 
++01010         /* Restore LPM and I2C registers */
++01011         restore_lpm_i2c_regs(core_if);
++01012 
++01013         /* Set PCGCCTL to 0 */
++01014         DWC_WRITE_REG32(core_if->pcgcctl, 0x00000000);
++01015 
++01016         gr = core_if->gr_backup;
++01017         /* Load restore values for [31:14] bits */
++01018         DWC_WRITE_REG32(core_if->pcgcctl,
++01019                         ((gr->pcgcctl_local & 0xffffc000) | 0x00020000));
++01020 
++01021         /* Umnask global Interrupt in GAHBCFG and restore it */
++01022         gahbcfg.d32 = gr->gahbcfg_local;
++01023         gahbcfg.b.glblintrmsk = 1;
++01024         DWC_WRITE_REG32(&core_if->core_global_regs->gahbcfg, gahbcfg.d32);
++01025 
++01026         /* Clear all pending interupts */
++01027         DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
++01028 
++01029         /* Unmask restore done interrupt */
++01030         gintmsk.b.restoredone = 1;
++01031         DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, gintmsk.d32);
++01032 
++01033         /* Restore GUSBCFG and HCFG/DCFG */
++01034         gusbcfg.d32 = core_if->gr_backup->gusbcfg_local;
++01035         DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, gusbcfg.d32);
++01036 
++01037         if (is_host) {
++01038                 hcfg_data_t hcfg = {.d32 = 0 };
++01039                 hcfg.d32 = core_if->hr_backup->hcfg_local;
++01040                 DWC_WRITE_REG32(&core_if->host_if->host_global_regs->hcfg,
++01041                                 hcfg.d32);
++01042 
++01043                 /* Load restore values for [31:14] bits */
++01044                 pcgcctl.d32 = gr->pcgcctl_local & 0xffffc000;
++01045                 pcgcctl.d32 = gr->pcgcctl_local | 0x00020000;
++01046 
++01047                 if (rmode)
++01048                         pcgcctl.b.restoremode = 1;
++01049                 DWC_WRITE_REG32(core_if->pcgcctl, pcgcctl.d32);
++01050                 dwc_udelay(10);
++01051 
++01052                 /* Load restore values for [31:14] bits and set EssRegRestored bit */
++01053                 pcgcctl.d32 = gr->pcgcctl_local | 0xffffc000;
++01054                 pcgcctl.d32 = gr->pcgcctl_local & 0xffffc000;
++01055                 pcgcctl.b.ess_reg_restored = 1;
++01056                 if (rmode)
++01057                         pcgcctl.b.restoremode = 1;
++01058                 DWC_WRITE_REG32(core_if->pcgcctl, pcgcctl.d32);
++01059         } else {
++01060                 dcfg_data_t dcfg = {.d32 = 0 };
++01061                 dcfg.d32 = core_if->dr_backup->dcfg;
++01062                 DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dcfg, dcfg.d32);
++01063 
++01064                 /* Load restore values for [31:14] bits */
++01065                 pcgcctl.d32 = gr->pcgcctl_local & 0xffffc000;
++01066                 pcgcctl.d32 = gr->pcgcctl_local | 0x00020000;
++01067                 if (!rmode) {
++01068                         pcgcctl.d32 |= 0x208;
++01069                 }
++01070                 DWC_WRITE_REG32(core_if->pcgcctl, pcgcctl.d32);
++01071                 dwc_udelay(10);
++01072 
++01073                 /* Load restore values for [31:14] bits */
++01074                 pcgcctl.d32 = gr->pcgcctl_local & 0xffffc000;
++01075                 pcgcctl.d32 = gr->pcgcctl_local | 0x00020000;
++01076                 pcgcctl.b.ess_reg_restored = 1;
++01077                 if (!rmode)
++01078                         pcgcctl.d32 |= 0x208;
++01079                 DWC_WRITE_REG32(core_if->pcgcctl, pcgcctl.d32);
++01080         }
++01081 
++01082         return 0;
++01083 }
++01084 
++01089 static void init_fslspclksel(dwc_otg_core_if_t * core_if)
++01090 {
++01091         uint32_t val;
++01092         hcfg_data_t hcfg;
++01093 
++01094         if (((core_if->hwcfg2.b.hs_phy_type == 2) &&
++01095              (core_if->hwcfg2.b.fs_phy_type == 1) &&
++01096              (core_if->core_params->ulpi_fs_ls)) ||
++01097             (core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS)) {
++01098                 /* Full speed PHY */
++01099                 val = DWC_HCFG_48_MHZ;
++01100         } else {
++01101                 /* High speed PHY running at full speed or high speed */
++01102                 val = DWC_HCFG_30_60_MHZ;
++01103         }
++01104 
++01105         DWC_DEBUGPL(DBG_CIL, "Initializing HCFG.FSLSPClkSel to 0x%1x\n", val);
++01106         hcfg.d32 = DWC_READ_REG32(&core_if->host_if->host_global_regs->hcfg);
++01107         hcfg.b.fslspclksel = val;
++01108         DWC_WRITE_REG32(&core_if->host_if->host_global_regs->hcfg, hcfg.d32);
++01109 }
++01110 
++01115 static void init_devspd(dwc_otg_core_if_t * core_if)
++01116 {
++01117         uint32_t val;
++01118         dcfg_data_t dcfg;
++01119 
++01120         if (((core_if->hwcfg2.b.hs_phy_type == 2) &&
++01121              (core_if->hwcfg2.b.fs_phy_type == 1) &&
++01122              (core_if->core_params->ulpi_fs_ls)) ||
++01123             (core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS)) {
++01124                 /* Full speed PHY */
++01125                 val = 0x3;
++01126         } else if (core_if->core_params->speed == DWC_SPEED_PARAM_FULL) {
++01127                 /* High speed PHY running at full speed */
++01128                 val = 0x1;
++01129         } else {
++01130                 /* High speed PHY running at high speed */
++01131                 val = 0x0;
++01132         }
++01133 
++01134         DWC_DEBUGPL(DBG_CIL, "Initializing DCFG.DevSpd to 0x%1x\n", val);
++01135 
++01136         dcfg.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg);
++01137         dcfg.b.devspd = val;
++01138         DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dcfg, dcfg.d32);
++01139 }
++01140 
++01147 static uint32_t calc_num_in_eps(dwc_otg_core_if_t * core_if)
++01148 {
++01149         uint32_t num_in_eps = 0;
++01150         uint32_t num_eps = core_if->hwcfg2.b.num_dev_ep;
++01151         uint32_t hwcfg1 = core_if->hwcfg1.d32 >> 3;
++01152         uint32_t num_tx_fifos = core_if->hwcfg4.b.num_in_eps;
++01153         int i;
++01154 
++01155         for (i = 0; i < num_eps; ++i) {
++01156                 if (!(hwcfg1 & 0x1))
++01157                         num_in_eps++;
++01158 
++01159                 hwcfg1 >>= 2;
++01160         }
++01161 
++01162         if (core_if->hwcfg4.b.ded_fifo_en) {
++01163                 num_in_eps =
++01164                     (num_in_eps > num_tx_fifos) ? num_tx_fifos : num_in_eps;
++01165         }
++01166 
++01167         return num_in_eps;
++01168 }
++01169 
++01176 static uint32_t calc_num_out_eps(dwc_otg_core_if_t * core_if)
++01177 {
++01178         uint32_t num_out_eps = 0;
++01179         uint32_t num_eps = core_if->hwcfg2.b.num_dev_ep;
++01180         uint32_t hwcfg1 = core_if->hwcfg1.d32 >> 2;
++01181         int i;
++01182 
++01183         for (i = 0; i < num_eps; ++i) {
++01184                 if (!(hwcfg1 & 0x1))
++01185                         num_out_eps++;
++01186 
++01187                 hwcfg1 >>= 2;
++01188         }
++01189         return num_out_eps;
++01190 }
++01191 
++01199 void dwc_otg_core_init(dwc_otg_core_if_t * core_if)
++01200 {
++01201         int i = 0;
++01202         dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
++01203         dwc_otg_dev_if_t *dev_if = core_if->dev_if;
++01204         gahbcfg_data_t ahbcfg = {.d32 = 0 };
++01205         gusbcfg_data_t usbcfg = {.d32 = 0 };
++01206         gi2cctl_data_t i2cctl = {.d32 = 0 };
++01207 
++01208         DWC_DEBUGPL(DBG_CILV, "dwc_otg_core_init(%p)\n", core_if);
++01209 
++01210         /* Common Initialization */
++01211         usbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg);
++01212 
++01213         /* Program the ULPI External VBUS bit if needed */
++01214         usbcfg.b.ulpi_ext_vbus_drv =
++01215             (core_if->core_params->phy_ulpi_ext_vbus ==
++01216              DWC_PHY_ULPI_EXTERNAL_VBUS) ? 1 : 0;
++01217 
++01218         /* Set external TS Dline pulsing */
++01219         usbcfg.b.term_sel_dl_pulse =
++01220             (core_if->core_params->ts_dline == 1) ? 1 : 0;
++01221         DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32);
++01222 
++01223         /* Reset the Controller */
++01224         dwc_otg_core_reset(core_if);
++01225 
++01226         core_if->adp_enable = core_if->core_params->adp_supp_enable;
++01227         core_if->power_down = core_if->core_params->power_down;
++01228         core_if->otg_sts = 0;
++01229 
++01230         /* Initialize parameters from Hardware configuration registers. */
++01231         dev_if->num_in_eps = calc_num_in_eps(core_if);
++01232         dev_if->num_out_eps = calc_num_out_eps(core_if);
++01233 
++01234         DWC_DEBUGPL(DBG_CIL, "num_dev_perio_in_ep=%d\n",
++01235                     core_if->hwcfg4.b.num_dev_perio_in_ep);
++01236 
++01237         for (i = 0; i < core_if->hwcfg4.b.num_dev_perio_in_ep; i++) {
++01238                 dev_if->perio_tx_fifo_size[i] =
++01239                     DWC_READ_REG32(&global_regs->dtxfsiz[i]) >> 16;
++01240                 DWC_DEBUGPL(DBG_CIL, "Periodic Tx FIFO SZ #%d=0x%0x\n",
++01241                             i, dev_if->perio_tx_fifo_size[i]);
++01242         }
++01243 
++01244         for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {
++01245                 dev_if->tx_fifo_size[i] =
++01246                     DWC_READ_REG32(&global_regs->dtxfsiz[i]) >> 16;
++01247                 DWC_DEBUGPL(DBG_CIL, "Tx FIFO SZ #%d=0x%0x\n",
++01248                             i, dev_if->tx_fifo_size[i]);
++01249         }
++01250 
++01251         core_if->total_fifo_size = core_if->hwcfg3.b.dfifo_depth;
++01252         core_if->rx_fifo_size = DWC_READ_REG32(&global_regs->grxfsiz);
++01253         core_if->nperio_tx_fifo_size =
++01254             DWC_READ_REG32(&global_regs->gnptxfsiz) >> 16;
++01255 
++01256         DWC_DEBUGPL(DBG_CIL, "Total FIFO SZ=%d\n", core_if->total_fifo_size);
++01257         DWC_DEBUGPL(DBG_CIL, "Rx FIFO SZ=%d\n", core_if->rx_fifo_size);
++01258         DWC_DEBUGPL(DBG_CIL, "NP Tx FIFO SZ=%d\n",
++01259                     core_if->nperio_tx_fifo_size);
++01260 
++01261         /* This programming sequence needs to happen in FS mode before any other
++01262          * programming occurs */
++01263         if ((core_if->core_params->speed == DWC_SPEED_PARAM_FULL) &&
++01264             (core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS)) {
++01265                 /* If FS mode with FS PHY */
++01266 
++01267                 /* core_init() is now called on every switch so only call the
++01268                  * following for the first time through. */
++01269                 if (!core_if->phy_init_done) {
++01270                         core_if->phy_init_done = 1;
++01271                         DWC_DEBUGPL(DBG_CIL, "FS_PHY detected\n");
++01272                         usbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg);
++01273                         usbcfg.b.physel = 1;
++01274                         DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32);
++01275 
++01276                         /* Reset after a PHY select */
++01277                         dwc_otg_core_reset(core_if);
++01278                 }
++01279 
++01280                 /* Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS.      Also
++01281                  * do this on HNP Dev/Host mode switches (done in dev_init and
++01282                  * host_init). */
++01283                 if (dwc_otg_is_host_mode(core_if)) {
++01284                         init_fslspclksel(core_if);
++01285                 } else {
++01286                         init_devspd(core_if);
++01287                 }
++01288 
++01289                 if (core_if->core_params->i2c_enable) {
++01290                         DWC_DEBUGPL(DBG_CIL, "FS_PHY Enabling I2c\n");
++01291                         /* Program GUSBCFG.OtgUtmifsSel to I2C */
++01292                         usbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg);
++01293                         usbcfg.b.otgutmifssel = 1;
++01294                         DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32);
++01295 
++01296                         /* Program GI2CCTL.I2CEn */
++01297                         i2cctl.d32 = DWC_READ_REG32(&global_regs->gi2cctl);
++01298                         i2cctl.b.i2cdevaddr = 1;
++01299                         i2cctl.b.i2cen = 0;
++01300                         DWC_WRITE_REG32(&global_regs->gi2cctl, i2cctl.d32);
++01301                         i2cctl.b.i2cen = 1;
++01302                         DWC_WRITE_REG32(&global_regs->gi2cctl, i2cctl.d32);
++01303                 }
++01304 
++01305         } /* endif speed == DWC_SPEED_PARAM_FULL */
++01306         else {
++01307                 /* High speed PHY. */
++01308                 if (!core_if->phy_init_done) {
++01309                         core_if->phy_init_done = 1;
++01310                         /* HS PHY parameters.  These parameters are preserved
++01311                          * during soft reset so only program the first time.  Do
++01312                          * a soft reset immediately after setting phyif.  */
++01313 
++01314                         if (core_if->core_params->phy_type == 2) {
++01315                                 /* ULPI interface */
++01316                                 usbcfg.b.ulpi_utmi_sel = 1;
++01317                                 usbcfg.b.phyif = 0;
++01318                                 usbcfg.b.ddrsel =
++01319                                     core_if->core_params->phy_ulpi_ddr;
++01320                         } else if (core_if->core_params->phy_type == 1) {
++01321                                 /* UTMI+ interface */
++01322                                 usbcfg.b.ulpi_utmi_sel = 0;
++01323                                 if (core_if->core_params->phy_utmi_width == 16) {
++01324                                         usbcfg.b.phyif = 1;
++01325 
++01326                                 } else {
++01327                                         usbcfg.b.phyif = 0;
++01328                                 }
++01329                         } else {
++01330                                 DWC_ERROR("FS PHY TYPE\n");
++01331                         }
++01332                         DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32);
++01333                         /* Reset after setting the PHY parameters */
++01334                         dwc_otg_core_reset(core_if);
++01335                 }
++01336         }
++01337 
++01338         if ((core_if->hwcfg2.b.hs_phy_type == 2) &&
++01339             (core_if->hwcfg2.b.fs_phy_type == 1) &&
++01340             (core_if->core_params->ulpi_fs_ls)) {
++01341                 DWC_DEBUGPL(DBG_CIL, "Setting ULPI FSLS\n");
++01342                 usbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg);
++01343                 usbcfg.b.ulpi_fsls = 1;
++01344                 usbcfg.b.ulpi_clk_sus_m = 1;
++01345                 DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32);
++01346         } else {
++01347                 usbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg);
++01348                 usbcfg.b.ulpi_fsls = 0;
++01349                 usbcfg.b.ulpi_clk_sus_m = 0;
++01350                 DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32);
++01351         }
++01352 
++01353         /* Program the GAHBCFG Register. */
++01354         switch (core_if->hwcfg2.b.architecture) {
++01355 
++01356         case DWC_SLAVE_ONLY_ARCH:
++01357                 DWC_DEBUGPL(DBG_CIL, "Slave Only Mode\n");
++01358                 ahbcfg.b.nptxfemplvl_txfemplvl =
++01359                     DWC_GAHBCFG_TXFEMPTYLVL_HALFEMPTY;
++01360                 ahbcfg.b.ptxfemplvl = DWC_GAHBCFG_TXFEMPTYLVL_HALFEMPTY;
++01361                 core_if->dma_enable = 0;
++01362                 core_if->dma_desc_enable = 0;
++01363                 break;
++01364 
++01365         case DWC_EXT_DMA_ARCH:
++01366                 DWC_DEBUGPL(DBG_CIL, "External DMA Mode\n");
++01367                 {
++01368                         uint8_t brst_sz = core_if->core_params->dma_burst_size;
++01369                         ahbcfg.b.hburstlen = 0;
++01370                         while (brst_sz > 1) {
++01371                                 ahbcfg.b.hburstlen++;
++01372                                 brst_sz >>= 1;
++01373                         }
++01374                 }
++01375                 core_if->dma_enable = (core_if->core_params->dma_enable != 0);
++01376                 core_if->dma_desc_enable =
++01377                     (core_if->core_params->dma_desc_enable != 0);
++01378                 break;
++01379 
++01380         case DWC_INT_DMA_ARCH:
++01381                 DWC_DEBUGPL(DBG_CIL, "Internal DMA Mode\n");
++01382                 /* Old value was DWC_GAHBCFG_INT_DMA_BURST_INCR - done for 
++01383                   Host mode ISOC in issue fix - vahrama */
++01384                 ahbcfg.b.hburstlen = DWC_GAHBCFG_INT_DMA_BURST_INCR4;
++01385                 core_if->dma_enable = (core_if->core_params->dma_enable != 0);
++01386                 core_if->dma_desc_enable =
++01387                     (core_if->core_params->dma_desc_enable != 0);
++01388                 break;
++01389 
++01390         }
++01391         if (core_if->dma_enable) {
++01392                 if (core_if->dma_desc_enable) {
++01393                         DWC_PRINTF("Using Descriptor DMA mode\n");
++01394                 } else {
++01395                         DWC_PRINTF("Using Buffer DMA mode\n");
++01396 
++01397                 }
++01398         } else {
++01399                 DWC_PRINTF("Using Slave mode\n");
++01400                 core_if->dma_desc_enable = 0;
++01401         }
++01402 
++01403         if (core_if->core_params->ahb_single) {
++01404                 ahbcfg.b.ahbsingle = 1;
++01405         }
++01406         
++01407         ahbcfg.b.dmaenable = core_if->dma_enable;
++01408         DWC_WRITE_REG32(&global_regs->gahbcfg, ahbcfg.d32);
++01409 
++01410         core_if->en_multiple_tx_fifo = core_if->hwcfg4.b.ded_fifo_en;
++01411 
++01412         core_if->pti_enh_enable = core_if->core_params->pti_enable != 0;
++01413         core_if->multiproc_int_enable = core_if->core_params->mpi_enable;
++01414         DWC_PRINTF("Periodic Transfer Interrupt Enhancement - %s\n",
++01415                    ((core_if->pti_enh_enable) ? "enabled" : "disabled"));
++01416         DWC_PRINTF("Multiprocessor Interrupt Enhancement - %s\n",
++01417                    ((core_if->multiproc_int_enable) ? "enabled" : "disabled"));
++01418 
++01419         /*
++01420          * Program the GUSBCFG register.
++01421          */
++01422         usbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg);
++01423 
++01424         switch (core_if->hwcfg2.b.op_mode) {
++01425         case DWC_MODE_HNP_SRP_CAPABLE:
++01426                 usbcfg.b.hnpcap = (core_if->core_params->otg_cap ==
++01427                                    DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE);
++01428                 usbcfg.b.srpcap = (core_if->core_params->otg_cap !=
++01429                                    DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE);
++01430                 break;
++01431 
++01432         case DWC_MODE_SRP_ONLY_CAPABLE:
++01433                 usbcfg.b.hnpcap = 0;
++01434                 usbcfg.b.srpcap = (core_if->core_params->otg_cap !=
++01435                                    DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE);
++01436                 break;
++01437 
++01438         case DWC_MODE_NO_HNP_SRP_CAPABLE:
++01439                 usbcfg.b.hnpcap = 0;
++01440                 usbcfg.b.srpcap = 0;
++01441                 break;
++01442 
++01443         case DWC_MODE_SRP_CAPABLE_DEVICE:
++01444                 usbcfg.b.hnpcap = 0;
++01445                 usbcfg.b.srpcap = (core_if->core_params->otg_cap !=
++01446                                    DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE);
++01447                 break;
++01448 
++01449         case DWC_MODE_NO_SRP_CAPABLE_DEVICE:
++01450                 usbcfg.b.hnpcap = 0;
++01451                 usbcfg.b.srpcap = 0;
++01452                 break;
++01453 
++01454         case DWC_MODE_SRP_CAPABLE_HOST:
++01455                 usbcfg.b.hnpcap = 0;
++01456                 usbcfg.b.srpcap = (core_if->core_params->otg_cap !=
++01457                                    DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE);
++01458                 break;
++01459 
++01460         case DWC_MODE_NO_SRP_CAPABLE_HOST:
++01461                 usbcfg.b.hnpcap = 0;
++01462                 usbcfg.b.srpcap = 0;
++01463                 break;
++01464         }
++01465 
++01466         DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32);
++01467 
++01468 #ifdef CONFIG_USB_DWC_OTG_LPM
++01469         if (core_if->core_params->lpm_enable) {
++01470                 glpmcfg_data_t lpmcfg = {.d32 = 0 };
++01471 
++01472                 /* To enable LPM support set lpm_cap_en bit */
++01473                 lpmcfg.b.lpm_cap_en = 1;
++01474 
++01475                 /* Make AppL1Res ACK */
++01476                 lpmcfg.b.appl_resp = 1;
++01477 
++01478                 /* Retry 3 times */
++01479                 lpmcfg.b.retry_count = 3;
++01480 
++01481                 DWC_MODIFY_REG32(&core_if->core_global_regs->glpmcfg,
++01482                                  0, lpmcfg.d32);
++01483 
++01484         }
++01485 #endif
++01486         if (core_if->core_params->ic_usb_cap) {
++01487                 gusbcfg_data_t gusbcfg = {.d32 = 0 };
++01488                 gusbcfg.b.ic_usb_cap = 1;
++01489                 DWC_MODIFY_REG32(&core_if->core_global_regs->gusbcfg,
++01490                                  0, gusbcfg.d32);
++01491         }
++01492         {
++01493                 gotgctl_data_t gotgctl = {.d32 = 0 };
++01494                 gotgctl.b.otgver = core_if->core_params->otg_ver;
++01495                 DWC_MODIFY_REG32(&core_if->core_global_regs->gotgctl, 0,
++01496                                  gotgctl.d32);
++01497                 /* Set OTG version supported */
++01498                 core_if->otg_ver = core_if->core_params->otg_ver;
++01499                 DWC_PRINTF("OTG VER PARAM: %d, OTG VER FLAG: %d\n",
++01500                            core_if->core_params->otg_ver, core_if->otg_ver);
++01501         }
++01502         
++01503 
++01504         /* Enable common interrupts */
++01505         dwc_otg_enable_common_interrupts(core_if);
++01506 
++01507         /* Do device or host intialization based on mode during PCD
++01508          * and HCD initialization  */
++01509         if (dwc_otg_is_host_mode(core_if)) {
++01510                 DWC_DEBUGPL(DBG_ANY, "Host Mode\n");
++01511                 core_if->op_state = A_HOST;
++01512         } else {
++01513                 DWC_DEBUGPL(DBG_ANY, "Device Mode\n");
++01514                 core_if->op_state = B_PERIPHERAL;
++01515 #ifdef DWC_DEVICE_ONLY
++01516                 dwc_otg_core_dev_init(core_if);
++01517 #endif
++01518         }
++01519 }
++01520 
++01526 void dwc_otg_enable_device_interrupts(dwc_otg_core_if_t * core_if)
++01527 {
++01528         gintmsk_data_t intr_mask = {.d32 = 0 };
++01529         dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
++01530 
++01531         DWC_DEBUGPL(DBG_CIL, "%s()\n", __func__);
++01532 
++01533         /* Disable all interrupts. */
++01534         DWC_WRITE_REG32(&global_regs->gintmsk, 0);
++01535 
++01536         /* Clear any pending interrupts */
++01537         DWC_WRITE_REG32(&global_regs->gintsts, 0xFFFFFFFF);
++01538 
++01539         /* Enable the common interrupts */
++01540         dwc_otg_enable_common_interrupts(core_if);
++01541 
++01542         /* Enable interrupts */
++01543         intr_mask.b.usbreset = 1;
++01544         intr_mask.b.enumdone = 1;
++01545         /* Disable Disconnect interrupt in Device mode */
++01546         intr_mask.b.disconnect = 0;
++01547 
++01548         if (!core_if->multiproc_int_enable) {
++01549                 intr_mask.b.inepintr = 1;
++01550                 intr_mask.b.outepintr = 1;
++01551         }
++01552 
++01553         intr_mask.b.erlysuspend = 1;
++01554 
++01555         if (core_if->en_multiple_tx_fifo == 0) {
++01556                 intr_mask.b.epmismatch = 1;
++01557         }
++01558 
++01559         //intr_mask.b.incomplisoout = 1;
++01560         intr_mask.b.incomplisoin = 1;
++01561         
++01562 /* Enable the ignore frame number for ISOC xfers - MAS */
++01563 /* Disable to support high bandwith ISOC transfers - manukz */
++01564 #if 0
++01565 #ifdef DWC_UTE_PER_IO
++01566         if (core_if->dma_enable) {
++01567                 if (core_if->dma_desc_enable) {
++01568                         dctl_data_t dctl1 = {.d32 = 0 };
++01569                         dctl1.b.ifrmnum = 1;
++01570                         DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->
++01571                                          dctl, 0, dctl1.d32);
++01572                         DWC_DEBUG("----Enabled Ignore frame number (0x%08x)",
++01573                                   DWC_READ_REG32(&core_if->dev_if->
++01574                                                  dev_global_regs->dctl));
++01575                 }
++01576         }
++01577 #endif
++01578 #endif
++01579 #ifdef DWC_EN_ISOC
++01580         if (core_if->dma_enable) {
++01581                 if (core_if->dma_desc_enable == 0) {
++01582                         if (core_if->pti_enh_enable) {
++01583                                 dctl_data_t dctl = {.d32 = 0 };
++01584                                 dctl.b.ifrmnum = 1;
++01585                                 DWC_MODIFY_REG32(&core_if->
++01586                                                  dev_if->dev_global_regs->dctl,
++01587                                                  0, dctl.d32);
++01588                         } else {
++01589                                 intr_mask.b.incomplisoin = 1;
++01590                                 intr_mask.b.incomplisoout = 1;
++01591                         }
++01592                 }
++01593         } else {
++01594                 intr_mask.b.incomplisoin = 1;
++01595                 intr_mask.b.incomplisoout = 1;
++01596         }
++01597 #endif /* DWC_EN_ISOC */
++01598 
++01600 #ifdef USE_PERIODIC_EP
++01601         intr_mask.b.isooutdrop = 1;
++01602         intr_mask.b.eopframe = 1;
++01603         intr_mask.b.incomplisoin = 1;
++01604         intr_mask.b.incomplisoout = 1;
++01605 #endif
++01606 
++01607         DWC_MODIFY_REG32(&global_regs->gintmsk, intr_mask.d32, intr_mask.d32);
++01608 
++01609         DWC_DEBUGPL(DBG_CIL, "%s() gintmsk=%0x\n", __func__,
++01610                     DWC_READ_REG32(&global_regs->gintmsk));
++01611 }
++01612 
++01620 void dwc_otg_core_dev_init(dwc_otg_core_if_t * core_if)
++01621 {
++01622         int i;
++01623         dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
++01624         dwc_otg_dev_if_t *dev_if = core_if->dev_if;
++01625         dwc_otg_core_params_t *params = core_if->core_params;
++01626         dcfg_data_t dcfg = {.d32 = 0 };
++01627         depctl_data_t diepctl = {.d32 = 0 };
++01628         grstctl_t resetctl = {.d32 = 0 };
++01629         uint32_t rx_fifo_size;
++01630         fifosize_data_t nptxfifosize;
++01631         fifosize_data_t txfifosize;
++01632         dthrctl_data_t dthrctl;
++01633         fifosize_data_t ptxfifosize;
++01634         uint16_t rxfsiz, nptxfsiz;
++01635         gdfifocfg_data_t gdfifocfg = {.d32 = 0 };
++01636         hwcfg3_data_t hwcfg3 = {.d32 = 0 };
++01637 
++01638         /* Restart the Phy Clock */
++01639         DWC_WRITE_REG32(core_if->pcgcctl, 0);
++01640 
++01641         /* Device configuration register */
++01642         init_devspd(core_if);
++01643         dcfg.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->dcfg);
++01644         dcfg.b.descdma = (core_if->dma_desc_enable) ? 1 : 0;
++01645         dcfg.b.perfrint = DWC_DCFG_FRAME_INTERVAL_80;
++01646         /* Enable Device OUT NAK in case of DDMA mode*/
++01647         if (core_if->core_params->dev_out_nak) {
++01648                 dcfg.b.endevoutnak = 1;         
++01649         }
++01650 
++01651         if (core_if->core_params->cont_on_bna) {
++01652                 dctl_data_t dctl = {.d32 = 0 };
++01653                 dctl.b.encontonbna = 1;
++01654                 DWC_MODIFY_REG32(&dev_if->dev_global_regs->dctl, 0, dctl.d32);
++01655         }
++01656         
++01657 
++01658         DWC_WRITE_REG32(&dev_if->dev_global_regs->dcfg, dcfg.d32);
++01659 
++01660         /* Configure data FIFO sizes */
++01661         if (core_if->hwcfg2.b.dynamic_fifo && params->enable_dynamic_fifo) {
++01662                 DWC_DEBUGPL(DBG_CIL, "Total FIFO Size=%d\n",
++01663                             core_if->total_fifo_size);
++01664                 DWC_DEBUGPL(DBG_CIL, "Rx FIFO Size=%d\n",
++01665                             params->dev_rx_fifo_size);
++01666                 DWC_DEBUGPL(DBG_CIL, "NP Tx FIFO Size=%d\n",
++01667                             params->dev_nperio_tx_fifo_size);
++01668 
++01669                 /* Rx FIFO */
++01670                 DWC_DEBUGPL(DBG_CIL, "initial grxfsiz=%08x\n",
++01671                             DWC_READ_REG32(&global_regs->grxfsiz));
++01672 
++01673 #ifdef DWC_UTE_CFI
++01674                 core_if->pwron_rxfsiz = DWC_READ_REG32(&global_regs->grxfsiz);
++01675                 core_if->init_rxfsiz = params->dev_rx_fifo_size;
++01676 #endif
++01677                 rx_fifo_size = params->dev_rx_fifo_size;
++01678                 DWC_WRITE_REG32(&global_regs->grxfsiz, rx_fifo_size);
++01679 
++01680                 DWC_DEBUGPL(DBG_CIL, "new grxfsiz=%08x\n",
++01681                             DWC_READ_REG32(&global_regs->grxfsiz));
++01682 
++01684                 core_if->p_tx_msk = 0;
++01685 
++01687                 core_if->tx_msk = 0;
++01688 
++01689                 if (core_if->en_multiple_tx_fifo == 0) {
++01690                         /* Non-periodic Tx FIFO */
++01691                         DWC_DEBUGPL(DBG_CIL, "initial gnptxfsiz=%08x\n",
++01692                                     DWC_READ_REG32(&global_regs->gnptxfsiz));
++01693 
++01694                         nptxfifosize.b.depth = params->dev_nperio_tx_fifo_size;
++01695                         nptxfifosize.b.startaddr = params->dev_rx_fifo_size;
++01696 
++01697                         DWC_WRITE_REG32(&global_regs->gnptxfsiz,
++01698                                         nptxfifosize.d32);
++01699 
++01700                         DWC_DEBUGPL(DBG_CIL, "new gnptxfsiz=%08x\n",
++01701                                     DWC_READ_REG32(&global_regs->gnptxfsiz));
++01702 
++01704                         /*
++01705                          * Periodic Tx FIFOs These FIFOs are numbered from 1 to 15.
++01706                          * Indexes of the FIFO size module parameters in the
++01707                          * dev_perio_tx_fifo_size array and the FIFO size registers in
++01708                          * the dptxfsiz array run from 0 to 14.
++01709                          */
++01711                         ptxfifosize.b.startaddr =
++01712                             nptxfifosize.b.startaddr + nptxfifosize.b.depth;
++01713                         for (i = 0; i < core_if->hwcfg4.b.num_dev_perio_in_ep; i++) {
++01714                                 ptxfifosize.b.depth =
++01715                                     params->dev_perio_tx_fifo_size[i];
++01716                                 DWC_DEBUGPL(DBG_CIL,
++01717                                             "initial dtxfsiz[%d]=%08x\n", i,
++01718                                             DWC_READ_REG32(&global_regs->dtxfsiz
++01719                                                            [i]));
++01720                                 DWC_WRITE_REG32(&global_regs->dtxfsiz[i],
++01721                                                 ptxfifosize.d32);
++01722                                 DWC_DEBUGPL(DBG_CIL, "new dtxfsiz[%d]=%08x\n",
++01723                                             i,
++01724                                             DWC_READ_REG32(&global_regs->dtxfsiz
++01725                                                            [i]));
++01726                                 ptxfifosize.b.startaddr += ptxfifosize.b.depth;
++01727                         }
++01728                 } else {
++01729                         /*
++01730                          * Tx FIFOs These FIFOs are numbered from 1 to 15.
++01731                          * Indexes of the FIFO size module parameters in the
++01732                          * dev_tx_fifo_size array and the FIFO size registers in
++01733                          * the dtxfsiz array run from 0 to 14.
++01734                          */
++01735 
++01736                         /* Non-periodic Tx FIFO */
++01737                         DWC_DEBUGPL(DBG_CIL, "initial gnptxfsiz=%08x\n",
++01738                                     DWC_READ_REG32(&global_regs->gnptxfsiz));
++01739 
++01740 #ifdef DWC_UTE_CFI
++01741                         core_if->pwron_gnptxfsiz =
++01742                             (DWC_READ_REG32(&global_regs->gnptxfsiz) >> 16);
++01743                         core_if->init_gnptxfsiz =
++01744                             params->dev_nperio_tx_fifo_size;
++01745 #endif
++01746                         nptxfifosize.b.depth = params->dev_nperio_tx_fifo_size;
++01747                         nptxfifosize.b.startaddr = params->dev_rx_fifo_size;
++01748 
++01749                         DWC_WRITE_REG32(&global_regs->gnptxfsiz,
++01750                                         nptxfifosize.d32);
++01751 
++01752                         DWC_DEBUGPL(DBG_CIL, "new gnptxfsiz=%08x\n",
++01753                                     DWC_READ_REG32(&global_regs->gnptxfsiz));
++01754 
++01755                         txfifosize.b.startaddr =
++01756                             nptxfifosize.b.startaddr + nptxfifosize.b.depth;
++01757 
++01758                         for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {
++01759 
++01760                                 txfifosize.b.depth =
++01761                                     params->dev_tx_fifo_size[i];
++01762 
++01763                                 DWC_DEBUGPL(DBG_CIL,
++01764                                             "initial dtxfsiz[%d]=%08x\n",
++01765                                             i,
++01766                                             DWC_READ_REG32(&global_regs->dtxfsiz
++01767                                                            [i]));
++01768 
++01769 #ifdef DWC_UTE_CFI
++01770                                 core_if->pwron_txfsiz[i] =
++01771                                     (DWC_READ_REG32
++01772                                      (&global_regs->dtxfsiz[i]) >> 16);
++01773                                 core_if->init_txfsiz[i] =
++01774                                     params->dev_tx_fifo_size[i];
++01775 #endif
++01776                                 DWC_WRITE_REG32(&global_regs->dtxfsiz[i],
++01777                                                 txfifosize.d32);
++01778 
++01779                                 DWC_DEBUGPL(DBG_CIL,
++01780                                             "new dtxfsiz[%d]=%08x\n",
++01781                                             i,
++01782                                             DWC_READ_REG32(&global_regs->dtxfsiz
++01783                                                            [i]));
++01784 
++01785                                 txfifosize.b.startaddr += txfifosize.b.depth;
++01786                         }
++01787                         /* Calculating DFIFOCFG for Device mode to include RxFIFO and NPTXFIFO */
++01788                         gdfifocfg.d32 = DWC_READ_REG32(&global_regs->gdfifocfg);
++01789                         hwcfg3.d32 = DWC_READ_REG32(&global_regs->ghwcfg3);
++01790                         gdfifocfg.b.gdfifocfg = (DWC_READ_REG32(&global_regs->ghwcfg3) >> 16);
++01791                         DWC_WRITE_REG32(&global_regs->gdfifocfg, gdfifocfg.d32);
++01792                         rxfsiz = (DWC_READ_REG32(&global_regs->grxfsiz) & 0x0000ffff);
++01793                         nptxfsiz = (DWC_READ_REG32(&global_regs->gnptxfsiz) >> 16);
++01794                         gdfifocfg.b.epinfobase = rxfsiz + nptxfsiz;
++01795                         DWC_WRITE_REG32(&global_regs->gdfifocfg, gdfifocfg.d32);
++01796                 }
++01797         }
++01798 
++01799         /* Flush the FIFOs */
++01800         dwc_otg_flush_tx_fifo(core_if, 0x10);   /* all Tx FIFOs */
++01801         dwc_otg_flush_rx_fifo(core_if);
++01802 
++01803         /* Flush the Learning Queue. */
++01804         resetctl.b.intknqflsh = 1;
++01805         DWC_WRITE_REG32(&core_if->core_global_regs->grstctl, resetctl.d32);
++01806 
++01807         if (!core_if->core_params->en_multiple_tx_fifo && core_if->dma_enable) {
++01808                 core_if->start_predict = 0;
++01809                 for (i = 0; i<= core_if->dev_if->num_in_eps; ++i) {
++01810                         core_if->nextep_seq[i] = 0xff;  // 0xff - EP not active
++01811                 }
++01812                 core_if->nextep_seq[0] = 0;     
++01813                 core_if->first_in_nextep_seq = 0;
++01814                 diepctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[0]->diepctl);
++01815                 diepctl.b.nextep = 0;
++01816                 DWC_WRITE_REG32(&dev_if->in_ep_regs[0]->diepctl, diepctl.d32);
++01817                 
++01818                 /* Update IN Endpoint Mismatch Count by active IN NP EP count + 1 */
++01819                 dcfg.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->dcfg);
++01820                 dcfg.b.epmscnt = 2;
++01821                 DWC_WRITE_REG32(&dev_if->dev_global_regs->dcfg, dcfg.d32);
++01822 
++01823                 DWC_DEBUGPL(DBG_CILV,"%s first_in_nextep_seq= %2d; nextep_seq[]:\n", 
++01824                         __func__, core_if->first_in_nextep_seq);
++01825                 for (i=0; i <= core_if->dev_if->num_in_eps; i++) {
++01826                         DWC_DEBUGPL(DBG_CILV, "%2d ", core_if->nextep_seq[i]);
++01827                 }
++01828                 DWC_DEBUGPL(DBG_CILV,"\n");
++01829         }
++01830         
++01831         /* Clear all pending Device Interrupts */
++01835         if (core_if->multiproc_int_enable) {
++01836                 for (i = 0; i < core_if->dev_if->num_in_eps; ++i) {
++01837                         DWC_WRITE_REG32(&dev_if->
++01838                                         dev_global_regs->diepeachintmsk[i], 0);
++01839                 }
++01840 
++01841                 for (i = 0; i < core_if->dev_if->num_out_eps; ++i) {
++01842                         DWC_WRITE_REG32(&dev_if->
++01843                                         dev_global_regs->doepeachintmsk[i], 0);
++01844                 }
++01845 
++01846                 DWC_WRITE_REG32(&dev_if->dev_global_regs->deachint, 0xFFFFFFFF);
++01847                 DWC_WRITE_REG32(&dev_if->dev_global_regs->deachintmsk, 0);
++01848         } else {
++01849                 DWC_WRITE_REG32(&dev_if->dev_global_regs->diepmsk, 0);
++01850                 DWC_WRITE_REG32(&dev_if->dev_global_regs->doepmsk, 0);
++01851                 DWC_WRITE_REG32(&dev_if->dev_global_regs->daint, 0xFFFFFFFF);
++01852                 DWC_WRITE_REG32(&dev_if->dev_global_regs->daintmsk, 0);
++01853         }
++01854 
++01855         for (i = 0; i <= dev_if->num_in_eps; i++) {
++01856                 depctl_data_t depctl;
++01857                 depctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl);
++01858                 if (depctl.b.epena) {
++01859                         depctl.d32 = 0;
++01860                         depctl.b.epdis = 1;
++01861                         depctl.b.snak = 1;
++01862                 } else {
++01863                         depctl.d32 = 0;
++01864                 }
++01865 
++01866                 DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->diepctl, depctl.d32);
++01867 
++01868                 DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->dieptsiz, 0);
++01869                 DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->diepdma, 0);
++01870                 DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->diepint, 0xFF);
++01871         }
++01872 
++01873         for (i = 0; i <= dev_if->num_out_eps; i++) {
++01874                 depctl_data_t depctl;
++01875                 depctl.d32 = DWC_READ_REG32(&dev_if->out_ep_regs[i]->doepctl);
++01876                 if (depctl.b.epena) {
++01877                         depctl.d32 = 0;
++01878                         depctl.b.epdis = 1;
++01879                         depctl.b.snak = 1;
++01880                 } else {
++01881                         depctl.d32 = 0;
++01882                 }
++01883 
++01884                 DWC_WRITE_REG32(&dev_if->out_ep_regs[i]->doepctl, depctl.d32);
++01885 
++01886                 DWC_WRITE_REG32(&dev_if->out_ep_regs[i]->doeptsiz, 0);
++01887                 DWC_WRITE_REG32(&dev_if->out_ep_regs[i]->doepdma, 0);
++01888                 DWC_WRITE_REG32(&dev_if->out_ep_regs[i]->doepint, 0xFF);
++01889         }
++01890 
++01891         if (core_if->en_multiple_tx_fifo && core_if->dma_enable) {
++01892                 dev_if->non_iso_tx_thr_en = params->thr_ctl & 0x1;
++01893                 dev_if->iso_tx_thr_en = (params->thr_ctl >> 1) & 0x1;
++01894                 dev_if->rx_thr_en = (params->thr_ctl >> 2) & 0x1;
++01895 
++01896                 dev_if->rx_thr_length = params->rx_thr_length;
++01897                 dev_if->tx_thr_length = params->tx_thr_length;
++01898 
++01899                 dev_if->setup_desc_index = 0;
++01900 
++01901                 dthrctl.d32 = 0;
++01902                 dthrctl.b.non_iso_thr_en = dev_if->non_iso_tx_thr_en;
++01903                 dthrctl.b.iso_thr_en = dev_if->iso_tx_thr_en;
++01904                 dthrctl.b.tx_thr_len = dev_if->tx_thr_length;
++01905                 dthrctl.b.rx_thr_en = dev_if->rx_thr_en;
++01906                 dthrctl.b.rx_thr_len = dev_if->rx_thr_length;
++01907                 dthrctl.b.ahb_thr_ratio = params->ahb_thr_ratio;
++01908 
++01909                 DWC_WRITE_REG32(&dev_if->dev_global_regs->dtknqr3_dthrctl,
++01910                                 dthrctl.d32);
++01911 
++01912                 DWC_DEBUGPL(DBG_CIL,
++01913                             "Non ISO Tx Thr - %d\nISO Tx Thr - %d\nRx Thr - %d\nTx Thr Len - %d\nRx Thr Len - %d\n",
++01914                             dthrctl.b.non_iso_thr_en, dthrctl.b.iso_thr_en,
++01915                             dthrctl.b.rx_thr_en, dthrctl.b.tx_thr_len,
++01916                             dthrctl.b.rx_thr_len);
++01917 
++01918         }
++01919 
++01920         dwc_otg_enable_device_interrupts(core_if);
++01921 
++01922         {
++01923                 diepmsk_data_t msk = {.d32 = 0 };
++01924                 msk.b.txfifoundrn = 1;
++01925                 if (core_if->multiproc_int_enable) {
++01926                         DWC_MODIFY_REG32(&dev_if->
++01927                                          dev_global_regs->diepeachintmsk[0],
++01928                                          msk.d32, msk.d32);
++01929                 } else {
++01930                         DWC_MODIFY_REG32(&dev_if->dev_global_regs->diepmsk,
++01931                                          msk.d32, msk.d32);
++01932                 }
++01933         }
++01934 
++01935         if (core_if->multiproc_int_enable) {
++01936                 /* Set NAK on Babble */
++01937                 dctl_data_t dctl = {.d32 = 0 };
++01938                 dctl.b.nakonbble = 1;
++01939                 DWC_MODIFY_REG32(&dev_if->dev_global_regs->dctl, 0, dctl.d32);
++01940         }
++01941 
++01942         if (core_if->snpsid >= OTG_CORE_REV_2_94a) {
++01943                 dctl_data_t dctl = {.d32 = 0 };
++01944                 dctl.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->dctl);
++01945                 dctl.b.sftdiscon = 0;
++01946                 DWC_WRITE_REG32(&dev_if->dev_global_regs->dctl, dctl.d32);
++01947         }
++01948 }
++01949 
++01955 void dwc_otg_enable_host_interrupts(dwc_otg_core_if_t * core_if)
++01956 {
++01957         dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
++01958         gintmsk_data_t intr_mask = {.d32 = 0 };
++01959 
++01960         DWC_DEBUGPL(DBG_CIL, "%s()\n", __func__);
++01961 
++01962         /* Disable all interrupts. */
++01963         DWC_WRITE_REG32(&global_regs->gintmsk, 0);
++01964 
++01965         /* Clear any pending interrupts. */
++01966         DWC_WRITE_REG32(&global_regs->gintsts, 0xFFFFFFFF);
++01967 
++01968         /* Enable the common interrupts */
++01969         dwc_otg_enable_common_interrupts(core_if);
++01970 
++01971         /*
++01972          * Enable host mode interrupts without disturbing common
++01973          * interrupts.
++01974          */
++01975 
++01976         intr_mask.b.disconnect = 1;
++01977         intr_mask.b.portintr = 1;
++01978         intr_mask.b.hcintr = 1;
++01979 
++01980         DWC_MODIFY_REG32(&global_regs->gintmsk, intr_mask.d32, intr_mask.d32);
++01981 }
++01982 
++01988 void dwc_otg_disable_host_interrupts(dwc_otg_core_if_t * core_if)
++01989 {
++01990         dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
++01991         gintmsk_data_t intr_mask = {.d32 = 0 };
++01992 
++01993         DWC_DEBUGPL(DBG_CILV, "%s()\n", __func__);
++01994 
++01995         /*
++01996          * Disable host mode interrupts without disturbing common
++01997          * interrupts.
++01998          */
++01999         intr_mask.b.sofintr = 1;
++02000         intr_mask.b.portintr = 1;
++02001         intr_mask.b.hcintr = 1;
++02002         intr_mask.b.ptxfempty = 1;
++02003         intr_mask.b.nptxfempty = 1;
++02004 
++02005         DWC_MODIFY_REG32(&global_regs->gintmsk, intr_mask.d32, 0);
++02006 }
++02007 
++02019 void dwc_otg_core_host_init(dwc_otg_core_if_t * core_if)
++02020 {
++02021         dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
++02022         dwc_otg_host_if_t *host_if = core_if->host_if;
++02023         dwc_otg_core_params_t *params = core_if->core_params;
++02024         hprt0_data_t hprt0 = {.d32 = 0 };
++02025         fifosize_data_t nptxfifosize;
++02026         fifosize_data_t ptxfifosize;
++02027         uint16_t rxfsiz, nptxfsiz, hptxfsiz;
++02028         gdfifocfg_data_t gdfifocfg = {.d32 = 0 };
++02029         int i;
++02030         hcchar_data_t hcchar;
++02031         hcfg_data_t hcfg;
++02032         hfir_data_t hfir;
++02033         dwc_otg_hc_regs_t *hc_regs;
++02034         int num_channels;
++02035         gotgctl_data_t gotgctl = {.d32 = 0 };
++02036 
++02037         DWC_DEBUGPL(DBG_CILV, "%s(%p)\n", __func__, core_if);
++02038 
++02039         /* Restart the Phy Clock */
++02040         DWC_WRITE_REG32(core_if->pcgcctl, 0);
++02041 
++02042         /* Initialize Host Configuration Register */
++02043         init_fslspclksel(core_if);
++02044         if (core_if->core_params->speed == DWC_SPEED_PARAM_FULL) {
++02045                 hcfg.d32 = DWC_READ_REG32(&host_if->host_global_regs->hcfg);
++02046                 hcfg.b.fslssupp = 1;
++02047                 DWC_WRITE_REG32(&host_if->host_global_regs->hcfg, hcfg.d32);
++02048 
++02049         }
++02050 
++02051         /* This bit allows dynamic reloading of the HFIR register
++02052          * during runtime. This bit needs to be programmed during 
++02053          * initial configuration and its value must not be changed
++02054          * during runtime.*/
++02055         if (core_if->core_params->reload_ctl == 1) {
++02056                 hfir.d32 = DWC_READ_REG32(&host_if->host_global_regs->hfir);
++02057                 hfir.b.hfirrldctrl = 1;
++02058                 DWC_WRITE_REG32(&host_if->host_global_regs->hfir, hfir.d32);
++02059         }
++02060 
++02061         if (core_if->core_params->dma_desc_enable) {
++02062                 uint8_t op_mode = core_if->hwcfg2.b.op_mode;
++02063                 if (!
++02064                     (core_if->hwcfg4.b.desc_dma
++02065                      && (core_if->snpsid >= OTG_CORE_REV_2_90a)
++02066                      && ((op_mode == DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG)
++02067                          || (op_mode == DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG)
++02068                          || (op_mode ==
++02069                              DWC_HWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE_OTG)
++02070                          || (op_mode == DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST)
++02071                          || (op_mode ==
++02072                              DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST)))) {
++02073 
++02074                         DWC_ERROR("Host can't operate in Descriptor DMA mode.\n"
++02075                                   "Either core version is below 2.90a or "
++02076                                   "GHWCFG2, GHWCFG4 registers' values do not allow Descriptor DMA in host mode.\n"
++02077                                   "To run the driver in Buffer DMA host mode set dma_desc_enable "
++02078                                   "module parameter to 0.\n");
++02079                         return;
++02080                 }
++02081                 hcfg.d32 = DWC_READ_REG32(&host_if->host_global_regs->hcfg);
++02082                 hcfg.b.descdma = 1;
++02083                 DWC_WRITE_REG32(&host_if->host_global_regs->hcfg, hcfg.d32);
++02084         }
++02085 
++02086         /* Configure data FIFO sizes */
++02087         if (core_if->hwcfg2.b.dynamic_fifo && params->enable_dynamic_fifo) {
++02088                 DWC_DEBUGPL(DBG_CIL, "Total FIFO Size=%d\n",
++02089                             core_if->total_fifo_size);
++02090                 DWC_DEBUGPL(DBG_CIL, "Rx FIFO Size=%d\n",
++02091                             params->host_rx_fifo_size);
++02092                 DWC_DEBUGPL(DBG_CIL, "NP Tx FIFO Size=%d\n",
++02093                             params->host_nperio_tx_fifo_size);
++02094                 DWC_DEBUGPL(DBG_CIL, "P Tx FIFO Size=%d\n",
++02095                             params->host_perio_tx_fifo_size);
++02096 
++02097                 /* Rx FIFO */
++02098                 DWC_DEBUGPL(DBG_CIL, "initial grxfsiz=%08x\n",
++02099                             DWC_READ_REG32(&global_regs->grxfsiz));
++02100                 DWC_WRITE_REG32(&global_regs->grxfsiz,
++02101                                 params->host_rx_fifo_size);
++02102                 DWC_DEBUGPL(DBG_CIL, "new grxfsiz=%08x\n",
++02103                             DWC_READ_REG32(&global_regs->grxfsiz));
++02104 
++02105                 /* Non-periodic Tx FIFO */
++02106                 DWC_DEBUGPL(DBG_CIL, "initial gnptxfsiz=%08x\n",
++02107                             DWC_READ_REG32(&global_regs->gnptxfsiz));
++02108                 nptxfifosize.b.depth = params->host_nperio_tx_fifo_size;
++02109                 nptxfifosize.b.startaddr = params->host_rx_fifo_size;
++02110                 DWC_WRITE_REG32(&global_regs->gnptxfsiz, nptxfifosize.d32);
++02111                 DWC_DEBUGPL(DBG_CIL, "new gnptxfsiz=%08x\n",
++02112                             DWC_READ_REG32(&global_regs->gnptxfsiz));
++02113 
++02114                 /* Periodic Tx FIFO */
++02115                 DWC_DEBUGPL(DBG_CIL, "initial hptxfsiz=%08x\n",
++02116                             DWC_READ_REG32(&global_regs->hptxfsiz));
++02117                 ptxfifosize.b.depth = params->host_perio_tx_fifo_size;
++02118                 ptxfifosize.b.startaddr =
++02119                     nptxfifosize.b.startaddr + nptxfifosize.b.depth;
++02120                 DWC_WRITE_REG32(&global_regs->hptxfsiz, ptxfifosize.d32);
++02121                 DWC_DEBUGPL(DBG_CIL, "new hptxfsiz=%08x\n",
++02122                             DWC_READ_REG32(&global_regs->hptxfsiz));
++02123                 
++02124                 if (core_if->en_multiple_tx_fifo) {
++02125                         /* Global DFIFOCFG calculation for Host mode - include RxFIFO, NPTXFIFO and HPTXFIFO */
++02126                         gdfifocfg.d32 = DWC_READ_REG32(&global_regs->gdfifocfg);
++02127                         rxfsiz = (DWC_READ_REG32(&global_regs->grxfsiz) & 0x0000ffff);
++02128                         nptxfsiz = (DWC_READ_REG32(&global_regs->gnptxfsiz) >> 16);
++02129                         hptxfsiz = (DWC_READ_REG32(&global_regs->hptxfsiz) >> 16);
++02130                         gdfifocfg.b.epinfobase = rxfsiz + nptxfsiz + hptxfsiz;
++02131                         DWC_WRITE_REG32(&global_regs->gdfifocfg, gdfifocfg.d32);
++02132                 }
++02133         }
++02134 
++02135         /* TODO - check this */
++02136         /* Clear Host Set HNP Enable in the OTG Control Register */
++02137         gotgctl.b.hstsethnpen = 1;
++02138         DWC_MODIFY_REG32(&global_regs->gotgctl, gotgctl.d32, 0);
++02139         /* Make sure the FIFOs are flushed. */
++02140         dwc_otg_flush_tx_fifo(core_if, 0x10 /* all TX FIFOs */ );
++02141         dwc_otg_flush_rx_fifo(core_if);
++02142 
++02143         /* Clear Host Set HNP Enable in the OTG Control Register */
++02144         gotgctl.b.hstsethnpen = 1;
++02145         DWC_MODIFY_REG32(&global_regs->gotgctl, gotgctl.d32, 0);
++02146 
++02147         if (!core_if->core_params->dma_desc_enable) {
++02148                 /* Flush out any leftover queued requests. */
++02149                 num_channels = core_if->core_params->host_channels;
++02150 
++02151                 for (i = 0; i < num_channels; i++) {
++02152                         hc_regs = core_if->host_if->hc_regs[i];
++02153                         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
++02154                         hcchar.b.chen = 0;
++02155                         hcchar.b.chdis = 1;
++02156                         hcchar.b.epdir = 0;
++02157                         DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
++02158                 }
++02159 
++02160                 /* Halt all channels to put them into a known state. */
++02161                 for (i = 0; i < num_channels; i++) {
++02162                         int count = 0;
++02163                         hc_regs = core_if->host_if->hc_regs[i];
++02164                         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
++02165                         hcchar.b.chen = 1;
++02166                         hcchar.b.chdis = 1;
++02167                         hcchar.b.epdir = 0;
++02168                         DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
++02169                         DWC_DEBUGPL(DBG_HCDV, "%s: Halt channel %d\n", __func__, i);
++02170                         do {
++02171                                 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
++02172                                 if (++count > 1000) {
++02173                                         DWC_ERROR
++02174                                             ("%s: Unable to clear halt on channel %d\n",
++02175                                              __func__, i);
++02176                                         break;
++02177                                 }
++02178                                 dwc_udelay(1);
++02179                         } while (hcchar.b.chen);
++02180                 }
++02181         }
++02182 
++02183         /* Turn on the vbus power. */
++02184         DWC_PRINTF("Init: Port Power? op_state=%d\n", core_if->op_state);
++02185         if (core_if->op_state == A_HOST) {
++02186                 hprt0.d32 = dwc_otg_read_hprt0(core_if);
++02187                 DWC_PRINTF("Init: Power Port (%d)\n", hprt0.b.prtpwr);
++02188                 if (hprt0.b.prtpwr == 0) {
++02189                         hprt0.b.prtpwr = 1;
++02190                         DWC_WRITE_REG32(host_if->hprt0, hprt0.d32);
++02191                 }
++02192         }
++02193 
++02194         dwc_otg_enable_host_interrupts(core_if);
++02195 }
++02196 
++02206 void dwc_otg_hc_init(dwc_otg_core_if_t * core_if, dwc_hc_t * hc)
++02207 {
++02208         uint32_t intr_enable;
++02209         hcintmsk_data_t hc_intr_mask;
++02210         gintmsk_data_t gintmsk = {.d32 = 0 };
++02211         hcchar_data_t hcchar;
++02212         hcsplt_data_t hcsplt;
++02213 
++02214         uint8_t hc_num = hc->hc_num;
++02215         dwc_otg_host_if_t *host_if = core_if->host_if;
++02216         dwc_otg_hc_regs_t *hc_regs = host_if->hc_regs[hc_num];
++02217 
++02218         /* Clear old interrupt conditions for this host channel. */
++02219         hc_intr_mask.d32 = 0xFFFFFFFF;
++02220         hc_intr_mask.b.reserved14_31 = 0;
++02221         DWC_WRITE_REG32(&hc_regs->hcint, hc_intr_mask.d32);
++02222 
++02223         /* Enable channel interrupts required for this transfer. */
++02224         hc_intr_mask.d32 = 0;
++02225         hc_intr_mask.b.chhltd = 1;
++02226         if (core_if->dma_enable) {
++02227                 /* For Descriptor DMA mode core halts the channel on AHB error. Interrupt is not required */
++02228                 if (!core_if->dma_desc_enable)
++02229                         hc_intr_mask.b.ahberr = 1;
++02230                 else {
++02231                         if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC)
++02232                                 hc_intr_mask.b.xfercompl = 1;
++02233                 }
++02234 
++02235                 if (hc->error_state && !hc->do_split &&
++02236                     hc->ep_type != DWC_OTG_EP_TYPE_ISOC) {
++02237                         hc_intr_mask.b.ack = 1;
++02238                         if (hc->ep_is_in) {
++02239                                 hc_intr_mask.b.datatglerr = 1;
++02240                                 if (hc->ep_type != DWC_OTG_EP_TYPE_INTR) {
++02241                                         hc_intr_mask.b.nak = 1;
++02242                                 }
++02243                         }
++02244                 }
++02245         } else {
++02246                 switch (hc->ep_type) {
++02247                 case DWC_OTG_EP_TYPE_CONTROL:
++02248                 case DWC_OTG_EP_TYPE_BULK:
++02249                         hc_intr_mask.b.xfercompl = 1;
++02250                         hc_intr_mask.b.stall = 1;
++02251                         hc_intr_mask.b.xacterr = 1;
++02252                         hc_intr_mask.b.datatglerr = 1;
++02253                         if (hc->ep_is_in) {
++02254                                 hc_intr_mask.b.bblerr = 1;
++02255                         } else {
++02256                                 hc_intr_mask.b.nak = 1;
++02257                                 hc_intr_mask.b.nyet = 1;
++02258                                 if (hc->do_ping) {
++02259                                         hc_intr_mask.b.ack = 1;
++02260                                 }
++02261                         }
++02262 
++02263                         if (hc->do_split) {
++02264                                 hc_intr_mask.b.nak = 1;
++02265                                 if (hc->complete_split) {
++02266                                         hc_intr_mask.b.nyet = 1;
++02267                                 } else {
++02268                                         hc_intr_mask.b.ack = 1;
++02269                                 }
++02270                         }
++02271 
++02272                         if (hc->error_state) {
++02273                                 hc_intr_mask.b.ack = 1;
++02274                         }
++02275                         break;
++02276                 case DWC_OTG_EP_TYPE_INTR:
++02277                         hc_intr_mask.b.xfercompl = 1;
++02278                         hc_intr_mask.b.nak = 1;
++02279                         hc_intr_mask.b.stall = 1;
++02280                         hc_intr_mask.b.xacterr = 1;
++02281                         hc_intr_mask.b.datatglerr = 1;
++02282                         hc_intr_mask.b.frmovrun = 1;
++02283 
++02284                         if (hc->ep_is_in) {
++02285                                 hc_intr_mask.b.bblerr = 1;
++02286                         }
++02287                         if (hc->error_state) {
++02288                                 hc_intr_mask.b.ack = 1;
++02289                         }
++02290                         if (hc->do_split) {
++02291                                 if (hc->complete_split) {
++02292                                         hc_intr_mask.b.nyet = 1;
++02293                                 } else {
++02294                                         hc_intr_mask.b.ack = 1;
++02295                                 }
++02296                         }
++02297                         break;
++02298                 case DWC_OTG_EP_TYPE_ISOC:
++02299                         hc_intr_mask.b.xfercompl = 1;
++02300                         hc_intr_mask.b.frmovrun = 1;
++02301                         hc_intr_mask.b.ack = 1;
++02302 
++02303                         if (hc->ep_is_in) {
++02304                                 hc_intr_mask.b.xacterr = 1;
++02305                                 hc_intr_mask.b.bblerr = 1;
++02306                         }
++02307                         break;
++02308                 }
++02309         }
++02310         DWC_WRITE_REG32(&hc_regs->hcintmsk, hc_intr_mask.d32);
++02311 
++02312         /* Enable the top level host channel interrupt. */
++02313         intr_enable = (1 << hc_num);
++02314         DWC_MODIFY_REG32(&host_if->host_global_regs->haintmsk, 0, intr_enable);
++02315 
++02316         /* Make sure host channel interrupts are enabled. */
++02317         gintmsk.b.hcintr = 1;
++02318         DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, 0, gintmsk.d32);
++02319 
++02320         /*
++02321          * Program the HCCHARn register with the endpoint characteristics for
++02322          * the current transfer.
++02323          */
++02324         hcchar.d32 = 0;
++02325         hcchar.b.devaddr = hc->dev_addr;
++02326         hcchar.b.epnum = hc->ep_num;
++02327         hcchar.b.epdir = hc->ep_is_in;
++02328         hcchar.b.lspddev = (hc->speed == DWC_OTG_EP_SPEED_LOW);
++02329         hcchar.b.eptype = hc->ep_type;
++02330         hcchar.b.mps = hc->max_packet;
++02331 
++02332         DWC_WRITE_REG32(&host_if->hc_regs[hc_num]->hcchar, hcchar.d32);
++02333 
++02334         DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num);
++02335         DWC_DEBUGPL(DBG_HCDV, "  Dev Addr: %d\n", hcchar.b.devaddr);
++02336         DWC_DEBUGPL(DBG_HCDV, "  Ep Num: %d\n", hcchar.b.epnum);
++02337         DWC_DEBUGPL(DBG_HCDV, "  Is In: %d\n", hcchar.b.epdir);
++02338         DWC_DEBUGPL(DBG_HCDV, "  Is Low Speed: %d\n", hcchar.b.lspddev);
++02339         DWC_DEBUGPL(DBG_HCDV, "  Ep Type: %d\n", hcchar.b.eptype);
++02340         DWC_DEBUGPL(DBG_HCDV, "  Max Pkt: %d\n", hcchar.b.mps);
++02341         DWC_DEBUGPL(DBG_HCDV, "  Multi Cnt: %d\n", hcchar.b.multicnt);
++02342 
++02343         /*
++02344          * Program the HCSPLIT register for SPLITs
++02345          */
++02346         hcsplt.d32 = 0;
++02347         if (hc->do_split) {
++02348                 DWC_DEBUGPL(DBG_HCDV, "Programming HC %d with split --> %s\n",
++02349                             hc->hc_num,
++02350                             hc->complete_split ? "CSPLIT" : "SSPLIT");
++02351                 hcsplt.b.compsplt = hc->complete_split;
++02352                 hcsplt.b.xactpos = hc->xact_pos;
++02353                 hcsplt.b.hubaddr = hc->hub_addr;
++02354                 hcsplt.b.prtaddr = hc->port_addr;
++02355                 DWC_DEBUGPL(DBG_HCDV, "   comp split %d\n", hc->complete_split);
++02356                 DWC_DEBUGPL(DBG_HCDV, "   xact pos %d\n", hc->xact_pos);
++02357                 DWC_DEBUGPL(DBG_HCDV, "   hub addr %d\n", hc->hub_addr);
++02358                 DWC_DEBUGPL(DBG_HCDV, "   port addr %d\n", hc->port_addr);
++02359                 DWC_DEBUGPL(DBG_HCDV, "   is_in %d\n", hc->ep_is_in);
++02360                 DWC_DEBUGPL(DBG_HCDV, "   Max Pkt: %d\n", hcchar.b.mps);
++02361                 DWC_DEBUGPL(DBG_HCDV, "   xferlen: %d\n", hc->xfer_len);
++02362         }
++02363         DWC_WRITE_REG32(&host_if->hc_regs[hc_num]->hcsplt, hcsplt.d32);
++02364 
++02365 }
++02366 
++02394 void dwc_otg_hc_halt(dwc_otg_core_if_t * core_if,
++02395                      dwc_hc_t * hc, dwc_otg_halt_status_e halt_status)
++02396 {
++02397         gnptxsts_data_t nptxsts;
++02398         hptxsts_data_t hptxsts;
++02399         hcchar_data_t hcchar;
++02400         dwc_otg_hc_regs_t *hc_regs;
++02401         dwc_otg_core_global_regs_t *global_regs;
++02402         dwc_otg_host_global_regs_t *host_global_regs;
++02403 
++02404         hc_regs = core_if->host_if->hc_regs[hc->hc_num];
++02405         global_regs = core_if->core_global_regs;
++02406         host_global_regs = core_if->host_if->host_global_regs;
++02407 
++02408         DWC_ASSERT(!(halt_status == DWC_OTG_HC_XFER_NO_HALT_STATUS),
++02409                    "halt_status = %d\n", halt_status);
++02410 
++02411         if (halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE ||
++02412             halt_status == DWC_OTG_HC_XFER_AHB_ERR) {
++02413                 /*
++02414                  * Disable all channel interrupts except Ch Halted. The QTD
++02415                  * and QH state associated with this transfer has been cleared
++02416                  * (in the case of URB_DEQUEUE), so the channel needs to be
++02417                  * shut down carefully to prevent crashes.
++02418                  */
++02419                 hcintmsk_data_t hcintmsk;
++02420                 hcintmsk.d32 = 0;
++02421                 hcintmsk.b.chhltd = 1;
++02422                 DWC_WRITE_REG32(&hc_regs->hcintmsk, hcintmsk.d32);
++02423 
++02424                 /*
++02425                  * Make sure no other interrupts besides halt are currently
++02426                  * pending. Handling another interrupt could cause a crash due
++02427                  * to the QTD and QH state.
++02428                  */
++02429                 DWC_WRITE_REG32(&hc_regs->hcint, ~hcintmsk.d32);
++02430 
++02431                 /*
++02432                  * Make sure the halt status is set to URB_DEQUEUE or AHB_ERR
++02433                  * even if the channel was already halted for some other
++02434                  * reason.
++02435                  */
++02436                 hc->halt_status = halt_status;
++02437 
++02438                 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
++02439                 if (hcchar.b.chen == 0) {
++02440                         /*
++02441                          * The channel is either already halted or it hasn't
++02442                          * started yet. In DMA mode, the transfer may halt if
++02443                          * it finishes normally or a condition occurs that
++02444                          * requires driver intervention. Don't want to halt
++02445                          * the channel again. In either Slave or DMA mode,
++02446                          * it's possible that the transfer has been assigned
++02447                          * to a channel, but not started yet when an URB is
++02448                          * dequeued. Don't want to halt a channel that hasn't
++02449                          * started yet.
++02450                          */
++02451                         return;
++02452                 }
++02453         }
++02454         if (hc->halt_pending) {
++02455                 /*
++02456                  * A halt has already been issued for this channel. This might
++02457                  * happen when a transfer is aborted by a higher level in
++02458                  * the stack.
++02459                  */
++02460 #ifdef DEBUG
++02461                 DWC_PRINTF
++02462                     ("*** %s: Channel %d, _hc->halt_pending already set ***\n",
++02463                      __func__, hc->hc_num);
++02464 
++02465 #endif
++02466                 return;
++02467         }
++02468 
++02469         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
++02470 
++02471         /* No need to set the bit in DDMA for disabling the channel */
++02472         //TODO check it everywhere channel is disabled          
++02473         if (!core_if->core_params->dma_desc_enable)
++02474                 hcchar.b.chen = 1;
++02475         hcchar.b.chdis = 1;
++02476 
++02477         if (!core_if->dma_enable) {
++02478                 /* Check for space in the request queue to issue the halt. */
++02479                 if (hc->ep_type == DWC_OTG_EP_TYPE_CONTROL ||
++02480                     hc->ep_type == DWC_OTG_EP_TYPE_BULK) {
++02481                         nptxsts.d32 = DWC_READ_REG32(&global_regs->gnptxsts);
++02482                         if (nptxsts.b.nptxqspcavail == 0) {
++02483                                 hcchar.b.chen = 0;
++02484                         }
++02485                 } else {
++02486                         hptxsts.d32 =
++02487                             DWC_READ_REG32(&host_global_regs->hptxsts);
++02488                         if ((hptxsts.b.ptxqspcavail == 0)
++02489                             || (core_if->queuing_high_bandwidth)) {
++02490                                 hcchar.b.chen = 0;
++02491                         }
++02492                 }
++02493         }
++02494         DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
++02495 
++02496         hc->halt_status = halt_status;
++02497 
++02498         if (hcchar.b.chen) {
++02499                 hc->halt_pending = 1;
++02500                 hc->halt_on_queue = 0;
++02501         } else {
++02502                 hc->halt_on_queue = 1;
++02503         }
++02504 
++02505         DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num);
++02506         DWC_DEBUGPL(DBG_HCDV, "  hcchar: 0x%08x\n", hcchar.d32);
++02507         DWC_DEBUGPL(DBG_HCDV, "  halt_pending: %d\n", hc->halt_pending);
++02508         DWC_DEBUGPL(DBG_HCDV, "  halt_on_queue: %d\n", hc->halt_on_queue);
++02509         DWC_DEBUGPL(DBG_HCDV, "  halt_status: %d\n", hc->halt_status);
++02510 
++02511         return;
++02512 }
++02513 
++02521 void dwc_otg_hc_cleanup(dwc_otg_core_if_t * core_if, dwc_hc_t * hc)
++02522 {
++02523         dwc_otg_hc_regs_t *hc_regs;
++02524 
++02525         hc->xfer_started = 0;
++02526 
++02527         /*
++02528          * Clear channel interrupt enables and any unhandled channel interrupt
++02529          * conditions.
++02530          */
++02531         hc_regs = core_if->host_if->hc_regs[hc->hc_num];
++02532         DWC_WRITE_REG32(&hc_regs->hcintmsk, 0);
++02533         DWC_WRITE_REG32(&hc_regs->hcint, 0xFFFFFFFF);
++02534 #ifdef DEBUG
++02535         DWC_TIMER_CANCEL(core_if->hc_xfer_timer[hc->hc_num]);
++02536 #endif
++02537 }
++02538 
++02549 static inline void hc_set_even_odd_frame(dwc_otg_core_if_t * core_if,
++02550                                          dwc_hc_t * hc, hcchar_data_t * hcchar)
++02551 {
++02552         if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
++02553             hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
++02554                 hfnum_data_t hfnum;
++02555                 hfnum.d32 =
++02556                     DWC_READ_REG32(&core_if->host_if->host_global_regs->hfnum);
++02557 
++02558                 /* 1 if _next_ frame is odd, 0 if it's even */
++02559                 hcchar->b.oddfrm = (hfnum.b.frnum & 0x1) ? 0 : 1;
++02560 #ifdef DEBUG
++02561                 if (hc->ep_type == DWC_OTG_EP_TYPE_INTR && hc->do_split
++02562                     && !hc->complete_split) {
++02563                         switch (hfnum.b.frnum & 0x7) {
++02564                         case 7:
++02565                                 core_if->hfnum_7_samples++;
++02566                                 core_if->hfnum_7_frrem_accum += hfnum.b.frrem;
++02567                                 break;
++02568                         case 0:
++02569                                 core_if->hfnum_0_samples++;
++02570                                 core_if->hfnum_0_frrem_accum += hfnum.b.frrem;
++02571                                 break;
++02572                         default:
++02573                                 core_if->hfnum_other_samples++;
++02574                                 core_if->hfnum_other_frrem_accum +=
++02575                                     hfnum.b.frrem;
++02576                                 break;
++02577                         }
++02578                 }
++02579 #endif
++02580         }
++02581 }
++02582 
++02583 #ifdef DEBUG
++02584 void hc_xfer_timeout(void *ptr)
++02585 {
++02586         hc_xfer_info_t *xfer_info = NULL;
++02587         int hc_num = 0;
++02588 
++02589         if (ptr)
++02590                 xfer_info = (hc_xfer_info_t *) ptr;
++02591 
++02592         if (!xfer_info->hc) {
++02593                 DWC_ERROR("xfer_info->hc = %p\n", xfer_info->hc);
++02594                 return;
++02595         }
++02596 
++02597         hc_num = xfer_info->hc->hc_num;
++02598         DWC_WARN("%s: timeout on channel %d\n", __func__, hc_num);
++02599         DWC_WARN("      start_hcchar_val 0x%08x\n",
++02600                  xfer_info->core_if->start_hcchar_val[hc_num]);
++02601 }
++02602 #endif
++02603 
++02604 void ep_xfer_timeout(void *ptr)
++02605 {
++02606         ep_xfer_info_t *xfer_info = NULL;
++02607         int ep_num = 0;
++02608         dctl_data_t dctl = {.d32 = 0 };
++02609         gintsts_data_t gintsts = {.d32 = 0 };
++02610         gintmsk_data_t gintmsk = {.d32 = 0 };
++02611 
++02612         if (ptr)
++02613                 xfer_info = (ep_xfer_info_t *) ptr;
++02614 
++02615         if (!xfer_info->ep) {
++02616                 DWC_ERROR("xfer_info->ep = %p\n", xfer_info->ep);
++02617                 return;
++02618         }
++02619 
++02620         ep_num = xfer_info->ep->num;
++02621         DWC_WARN("%s: timeout on endpoit %d\n", __func__, ep_num);
++02622         /* Put the sate to 2 as it was time outed */
++02623         xfer_info->state = 2;
++02624 
++02625         dctl.d32 = DWC_READ_REG32(&xfer_info->core_if->
++02626                 dev_if->dev_global_regs->dctl);
++02627         gintsts.d32 = DWC_READ_REG32(&xfer_info->core_if->
++02628                 core_global_regs->gintsts);
++02629         gintmsk.d32 = DWC_READ_REG32(&xfer_info->core_if->
++02630                 core_global_regs->gintmsk);
++02631 
++02632         if (!gintmsk.b.goutnakeff) {
++02633                 /* Unmask it */
++02634                 gintmsk.b.goutnakeff = 1;
++02635                 DWC_WRITE_REG32(&xfer_info->core_if->
++02636                         core_global_regs->gintmsk, gintmsk.d32);
++02637 
++02638         }
++02639 
++02640         if (!gintsts.b.goutnakeff) {
++02641                 dctl.b.sgoutnak = 1;
++02642         }
++02643         DWC_WRITE_REG32(&xfer_info->core_if->dev_if->
++02644                 dev_global_regs->dctl, dctl.d32);
++02645 
++02646 }
++02647 
++02648 void set_pid_isoc(dwc_hc_t * hc)
++02649 {
++02650         /* Set up the initial PID for the transfer. */
++02651         if (hc->speed == DWC_OTG_EP_SPEED_HIGH) {
++02652                 if (hc->ep_is_in) {
++02653                         if (hc->multi_count == 1) {
++02654                                 hc->data_pid_start = DWC_OTG_HC_PID_DATA0;
++02655                         } else if (hc->multi_count == 2) {
++02656                                 hc->data_pid_start = DWC_OTG_HC_PID_DATA1;
++02657                         } else {
++02658                                 hc->data_pid_start = DWC_OTG_HC_PID_DATA2;
++02659                         }
++02660                 } else {
++02661                         if (hc->multi_count == 1) {
++02662                                 hc->data_pid_start = DWC_OTG_HC_PID_DATA0;
++02663                         } else {
++02664                                 hc->data_pid_start = DWC_OTG_HC_PID_MDATA;
++02665                         }
++02666                 }
++02667         } else {
++02668                 hc->data_pid_start = DWC_OTG_HC_PID_DATA0;
++02669         }
++02670 }
++02671 
++02703 void dwc_otg_hc_start_transfer(dwc_otg_core_if_t * core_if, dwc_hc_t * hc)
++02704 {
++02705         hcchar_data_t hcchar;
++02706         hctsiz_data_t hctsiz;
++02707         uint16_t num_packets;
++02708         uint32_t max_hc_xfer_size = core_if->core_params->max_transfer_size;
++02709         uint16_t max_hc_pkt_count = core_if->core_params->max_packet_count;
++02710         dwc_otg_hc_regs_t *hc_regs = core_if->host_if->hc_regs[hc->hc_num];
++02711 
++02712         hctsiz.d32 = 0;
++02713 
++02714         if (hc->do_ping) {
++02715                 if (!core_if->dma_enable) {
++02716                         dwc_otg_hc_do_ping(core_if, hc);
++02717                         hc->xfer_started = 1;
++02718                         return;
++02719                 } else {
++02720                         hctsiz.b.dopng = 1;
++02721                 }
++02722         }
++02723 
++02724         if (hc->do_split) {
++02725                 num_packets = 1;
++02726 
++02727                 if (hc->complete_split && !hc->ep_is_in) {
++02728                         /* For CSPLIT OUT Transfer, set the size to 0 so the
++02729                          * core doesn't expect any data written to the FIFO */
++02730                         hc->xfer_len = 0;
++02731                 } else if (hc->ep_is_in || (hc->xfer_len > hc->max_packet)) {
++02732                         hc->xfer_len = hc->max_packet;
++02733                 } else if (!hc->ep_is_in && (hc->xfer_len > 188)) {
++02734                         hc->xfer_len = 188;
++02735                 }
++02736 
++02737                 hctsiz.b.xfersize = hc->xfer_len;
++02738         } else {
++02739                 /*
++02740                  * Ensure that the transfer length and packet count will fit
++02741                  * in the widths allocated for them in the HCTSIZn register.
++02742                  */
++02743                 if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
++02744                     hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
++02745                         /*
++02746                          * Make sure the transfer size is no larger than one
++02747                          * (micro)frame's worth of data. (A check was done
++02748                          * when the periodic transfer was accepted to ensure
++02749                          * that a (micro)frame's worth of data can be
++02750                          * programmed into a channel.)
++02751                          */
++02752                         uint32_t max_periodic_len =
++02753                             hc->multi_count * hc->max_packet;
++02754                         if (hc->xfer_len > max_periodic_len) {
++02755                                 hc->xfer_len = max_periodic_len;
++02756                         } else {
++02757                         }
++02758                 } else if (hc->xfer_len > max_hc_xfer_size) {
++02759                         /* Make sure that xfer_len is a multiple of max packet size. */
++02760                         hc->xfer_len = max_hc_xfer_size - hc->max_packet + 1;
++02761                 }
++02762 
++02763                 if (hc->xfer_len > 0) {
++02764                         num_packets =
++02765                             (hc->xfer_len + hc->max_packet -
++02766                              1) / hc->max_packet;
++02767                         if (num_packets > max_hc_pkt_count) {
++02768                                 num_packets = max_hc_pkt_count;
++02769                                 hc->xfer_len = num_packets * hc->max_packet;
++02770                         }
++02771                 } else {
++02772                         /* Need 1 packet for transfer length of 0. */
++02773                         num_packets = 1;
++02774                 }
++02775 
++02776                 if (hc->ep_is_in) {
++02777                         /* Always program an integral # of max packets for IN transfers. */
++02778                         hc->xfer_len = num_packets * hc->max_packet;
++02779                 }
++02780 
++02781                 if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
++02782                     hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
++02783                         /*
++02784                          * Make sure that the multi_count field matches the
++02785                          * actual transfer length.
++02786                          */
++02787                         hc->multi_count = num_packets;
++02788                 }
++02789 
++02790                 if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC)
++02791                         set_pid_isoc(hc);
++02792 
++02793                 hctsiz.b.xfersize = hc->xfer_len;
++02794         }
++02795 
++02796         hc->start_pkt_count = num_packets;
++02797         hctsiz.b.pktcnt = num_packets;
++02798         hctsiz.b.pid = hc->data_pid_start;
++02799         DWC_WRITE_REG32(&hc_regs->hctsiz, hctsiz.d32);
++02800 
++02801         DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num);
++02802         DWC_DEBUGPL(DBG_HCDV, "  Xfer Size: %d\n", hctsiz.b.xfersize);
++02803         DWC_DEBUGPL(DBG_HCDV, "  Num Pkts: %d\n", hctsiz.b.pktcnt);
++02804         DWC_DEBUGPL(DBG_HCDV, "  Start PID: %d\n", hctsiz.b.pid);
++02805 
++02806         if (core_if->dma_enable) {
++02807                 dwc_dma_t dma_addr;
++02808                 if (hc->align_buff) {
++02809                         dma_addr = hc->align_buff;
++02810                 } else {
++02811                         dma_addr = ((unsigned long)hc->xfer_buff & 0xffffffff);
++02812                 }
++02813                 DWC_WRITE_REG32(&hc_regs->hcdma, dma_addr);
++02814         }
++02815 
++02816         /* Start the split */
++02817         if (hc->do_split) {
++02818                 hcsplt_data_t hcsplt;
++02819                 hcsplt.d32 = DWC_READ_REG32(&hc_regs->hcsplt);
++02820                 hcsplt.b.spltena = 1;
++02821                 DWC_WRITE_REG32(&hc_regs->hcsplt, hcsplt.d32);
++02822         }
++02823 
++02824         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
++02825         hcchar.b.multicnt = hc->multi_count;
++02826         hc_set_even_odd_frame(core_if, hc, &hcchar);
++02827 #ifdef DEBUG
++02828         core_if->start_hcchar_val[hc->hc_num] = hcchar.d32;
++02829         if (hcchar.b.chdis) {
++02830                 DWC_WARN("%s: chdis set, channel %d, hcchar 0x%08x\n",
++02831                          __func__, hc->hc_num, hcchar.d32);
++02832         }
++02833 #endif
++02834 
++02835         /* Set host channel enable after all other setup is complete. */
++02836         hcchar.b.chen = 1;
++02837         hcchar.b.chdis = 0;
++02838         DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
++02839 
++02840         hc->xfer_started = 1;
++02841         hc->requests++;
++02842 
++02843         if (!core_if->dma_enable && !hc->ep_is_in && hc->xfer_len > 0) {
++02844                 /* Load OUT packet into the appropriate Tx FIFO. */
++02845                 dwc_otg_hc_write_packet(core_if, hc);
++02846         }
++02847 #ifdef DEBUG
++02848         if (hc->ep_type != DWC_OTG_EP_TYPE_INTR) {
++02849                 core_if->hc_xfer_info[hc->hc_num].core_if = core_if;
++02850                 core_if->hc_xfer_info[hc->hc_num].hc = hc;
++02851 
++02852                 /* Start a timer for this transfer. */
++02853                 DWC_TIMER_SCHEDULE(core_if->hc_xfer_timer[hc->hc_num], 10000);
++02854         }
++02855 #endif
++02856 }
++02857 
++02872 void dwc_otg_hc_start_transfer_ddma(dwc_otg_core_if_t * core_if, dwc_hc_t * hc)
++02873 {
++02874         dwc_otg_hc_regs_t *hc_regs = core_if->host_if->hc_regs[hc->hc_num];
++02875         hcchar_data_t hcchar;
++02876         hctsiz_data_t hctsiz;
++02877         hcdma_data_t hcdma;
++02878 
++02879         hctsiz.d32 = 0;
++02880 
++02881         if (hc->do_ping)
++02882                 hctsiz.b_ddma.dopng = 1;
++02883 
++02884         if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC)
++02885                 set_pid_isoc(hc);
++02886 
++02887         /* Packet Count and Xfer Size are not used in Descriptor DMA mode */
++02888         hctsiz.b_ddma.pid = hc->data_pid_start;
++02889         hctsiz.b_ddma.ntd = hc->ntd - 1;        /* 0 - 1 descriptor, 1 - 2 descriptors, etc. */
++02890         hctsiz.b_ddma.schinfo = hc->schinfo;    /* Non-zero only for high-speed interrupt endpoints */
++02891 
++02892         DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num);
++02893         DWC_DEBUGPL(DBG_HCDV, "  Start PID: %d\n", hctsiz.b.pid);
++02894         DWC_DEBUGPL(DBG_HCDV, "  NTD: %d\n", hctsiz.b_ddma.ntd);
++02895 
++02896         DWC_WRITE_REG32(&hc_regs->hctsiz, hctsiz.d32);
++02897 
++02898         hcdma.d32 = 0;
++02899         hcdma.b.dma_addr = ((uint32_t) hc->desc_list_addr) >> 11;
++02900 
++02901         /* Always start from first descriptor. */
++02902         hcdma.b.ctd = 0;
++02903         DWC_WRITE_REG32(&hc_regs->hcdma, hcdma.d32);
++02904 
++02905         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
++02906         hcchar.b.multicnt = hc->multi_count;
++02907 
++02908 #ifdef DEBUG
++02909         core_if->start_hcchar_val[hc->hc_num] = hcchar.d32;
++02910         if (hcchar.b.chdis) {
++02911                 DWC_WARN("%s: chdis set, channel %d, hcchar 0x%08x\n",
++02912                          __func__, hc->hc_num, hcchar.d32);
++02913         }
++02914 #endif
++02915 
++02916         /* Set host channel enable after all other setup is complete. */
++02917         hcchar.b.chen = 1;
++02918         hcchar.b.chdis = 0;
++02919 
++02920         DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
++02921 
++02922         hc->xfer_started = 1;
++02923         hc->requests++;
++02924 
++02925 #ifdef DEBUG
++02926         if ((hc->ep_type != DWC_OTG_EP_TYPE_INTR)
++02927             && (hc->ep_type != DWC_OTG_EP_TYPE_ISOC)) {
++02928                 core_if->hc_xfer_info[hc->hc_num].core_if = core_if;
++02929                 core_if->hc_xfer_info[hc->hc_num].hc = hc;
++02930                 /* Start a timer for this transfer. */
++02931                 DWC_TIMER_SCHEDULE(core_if->hc_xfer_timer[hc->hc_num], 10000);
++02932         }
++02933 #endif
++02934 
++02935 }
++02936 
++02952 int dwc_otg_hc_continue_transfer(dwc_otg_core_if_t * core_if, dwc_hc_t * hc)
++02953 {
++02954         DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num);
++02955 
++02956         if (hc->do_split) {
++02957                 /* SPLITs always queue just once per channel */
++02958                 return 0;
++02959         } else if (hc->data_pid_start == DWC_OTG_HC_PID_SETUP) {
++02960                 /* SETUPs are queued only once since they can't be NAKed. */
++02961                 return 0;
++02962         } else if (hc->ep_is_in) {
++02963                 /*
++02964                  * Always queue another request for other IN transfers. If
++02965                  * back-to-back INs are issued and NAKs are received for both,
++02966                  * the driver may still be processing the first NAK when the
++02967                  * second NAK is received. When the interrupt handler clears
++02968                  * the NAK interrupt for the first NAK, the second NAK will
++02969                  * not be seen. So we can't depend on the NAK interrupt
++02970                  * handler to requeue a NAKed request. Instead, IN requests
++02971                  * are issued each time this function is called. When the
++02972                  * transfer completes, the extra requests for the channel will
++02973                  * be flushed.
++02974                  */
++02975                 hcchar_data_t hcchar;
++02976                 dwc_otg_hc_regs_t *hc_regs =
++02977                     core_if->host_if->hc_regs[hc->hc_num];
++02978 
++02979                 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
++02980                 hc_set_even_odd_frame(core_if, hc, &hcchar);
++02981                 hcchar.b.chen = 1;
++02982                 hcchar.b.chdis = 0;
++02983                 DWC_DEBUGPL(DBG_HCDV, "  IN xfer: hcchar = 0x%08x\n",
++02984                             hcchar.d32);
++02985                 DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
++02986                 hc->requests++;
++02987                 return 1;
++02988         } else {
++02989                 /* OUT transfers. */
++02990                 if (hc->xfer_count < hc->xfer_len) {
++02991                         if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
++02992                             hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
++02993                                 hcchar_data_t hcchar;
++02994                                 dwc_otg_hc_regs_t *hc_regs;
++02995                                 hc_regs = core_if->host_if->hc_regs[hc->hc_num];
++02996                                 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
++02997                                 hc_set_even_odd_frame(core_if, hc, &hcchar);
++02998                         }
++02999 
++03000                         /* Load OUT packet into the appropriate Tx FIFO. */
++03001                         dwc_otg_hc_write_packet(core_if, hc);
++03002                         hc->requests++;
++03003                         return 1;
++03004                 } else {
++03005                         return 0;
++03006                 }
++03007         }
++03008 }
++03009 
++03014 void dwc_otg_hc_do_ping(dwc_otg_core_if_t * core_if, dwc_hc_t * hc)
++03015 {
++03016         hcchar_data_t hcchar;
++03017         hctsiz_data_t hctsiz;
++03018         dwc_otg_hc_regs_t *hc_regs = core_if->host_if->hc_regs[hc->hc_num];
++03019 
++03020         DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num);
++03021 
++03022         hctsiz.d32 = 0;
++03023         hctsiz.b.dopng = 1;
++03024         hctsiz.b.pktcnt = 1;
++03025         DWC_WRITE_REG32(&hc_regs->hctsiz, hctsiz.d32);
++03026 
++03027         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
++03028         hcchar.b.chen = 1;
++03029         hcchar.b.chdis = 0;
++03030         DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
++03031 }
++03032 
++03033 /*
++03034  * This function writes a packet into the Tx FIFO associated with the Host
++03035  * Channel. For a channel associated with a non-periodic EP, the non-periodic
++03036  * Tx FIFO is written. For a channel associated with a periodic EP, the
++03037  * periodic Tx FIFO is written. This function should only be called in Slave
++03038  * mode.
++03039  *
++03040  * Upon return the xfer_buff and xfer_count fields in _hc are incremented by
++03041  * then number of bytes written to the Tx FIFO.
++03042  */
++03043 void dwc_otg_hc_write_packet(dwc_otg_core_if_t * core_if, dwc_hc_t * hc)
++03044 {
++03045         uint32_t i;
++03046         uint32_t remaining_count;
++03047         uint32_t byte_count;
++03048         uint32_t dword_count;
++03049 
++03050         uint32_t *data_buff = (uint32_t *) (hc->xfer_buff);
++03051         uint32_t *data_fifo = core_if->data_fifo[hc->hc_num];
++03052 
++03053         remaining_count = hc->xfer_len - hc->xfer_count;
++03054         if (remaining_count > hc->max_packet) {
++03055                 byte_count = hc->max_packet;
++03056         } else {
++03057                 byte_count = remaining_count;
++03058         }
++03059 
++03060         dword_count = (byte_count + 3) / 4;
++03061 
++03062         if ((((unsigned long)data_buff) & 0x3) == 0) {
++03063                 /* xfer_buff is DWORD aligned. */
++03064                 for (i = 0; i < dword_count; i++, data_buff++) {
++03065                         DWC_WRITE_REG32(data_fifo, *data_buff);
++03066                 }
++03067         } else {
++03068                 /* xfer_buff is not DWORD aligned. */
++03069                 for (i = 0; i < dword_count; i++, data_buff++) {
++03070                         uint32_t data;
++03071                         data =
++03072                             (data_buff[0] | data_buff[1] << 8 | data_buff[2] <<
++03073                              16 | data_buff[3] << 24);
++03074                         DWC_WRITE_REG32(data_fifo, data);
++03075                 }
++03076         }
++03077 
++03078         hc->xfer_count += byte_count;
++03079         hc->xfer_buff += byte_count;
++03080 }
++03081 
++03086 uint32_t dwc_otg_get_frame_number(dwc_otg_core_if_t * core_if)
++03087 {
++03088         dsts_data_t dsts;
++03089         dsts.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts);
++03090 
++03091         /* read current frame/microframe number from DSTS register */
++03092         return dsts.b.soffn;
++03093 }
++03094 
++03102 uint32_t calc_frame_interval(dwc_otg_core_if_t * core_if)
++03103 {
++03104         gusbcfg_data_t usbcfg;
++03105         hwcfg2_data_t hwcfg2;
++03106         hprt0_data_t hprt0;
++03107         int clock = 60;         // default value
++03108         usbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
++03109         hwcfg2.d32 = DWC_READ_REG32(&core_if->core_global_regs->ghwcfg2);
++03110         hprt0.d32 = DWC_READ_REG32(core_if->host_if->hprt0);
++03111         if (!usbcfg.b.physel && usbcfg.b.ulpi_utmi_sel && !usbcfg.b.phyif)
++03112                 clock = 60;
++03113         if (usbcfg.b.physel && hwcfg2.b.fs_phy_type == 3)
++03114                 clock = 48;
++03115         if (!usbcfg.b.phylpwrclksel && !usbcfg.b.physel &&
++03116             !usbcfg.b.ulpi_utmi_sel && usbcfg.b.phyif)
++03117                 clock = 30;
++03118         if (!usbcfg.b.phylpwrclksel && !usbcfg.b.physel &&
++03119             !usbcfg.b.ulpi_utmi_sel && !usbcfg.b.phyif)
++03120                 clock = 60;
++03121         if (usbcfg.b.phylpwrclksel && !usbcfg.b.physel &&
++03122             !usbcfg.b.ulpi_utmi_sel && usbcfg.b.phyif)
++03123                 clock = 48;
++03124         if (usbcfg.b.physel && !usbcfg.b.phyif && hwcfg2.b.fs_phy_type == 2)
++03125                 clock = 48;
++03126         if (usbcfg.b.physel && hwcfg2.b.fs_phy_type == 1)
++03127                 clock = 48;
++03128         if (hprt0.b.prtspd == 0)
++03129                 /* High speed case */
++03130                 return 125 * clock;
++03131         else
++03132                 /* FS/LS case */
++03133                 return 1000 * clock;
++03134 }
++03135 
++03144 void dwc_otg_read_setup_packet(dwc_otg_core_if_t * core_if, uint32_t * dest)
++03145 {
++03146         /* Get the 8 bytes of a setup transaction data */
++03147 
++03148         /* Pop 2 DWORDS off the receive data FIFO into memory */
++03149         dest[0] = DWC_READ_REG32(core_if->data_fifo[0]);
++03150         dest[1] = DWC_READ_REG32(core_if->data_fifo[0]);
++03151 }
++03152 
++03161 void dwc_otg_ep0_activate(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
++03162 {
++03163         dwc_otg_dev_if_t *dev_if = core_if->dev_if;
++03164         dsts_data_t dsts;
++03165         depctl_data_t diepctl;
++03166         depctl_data_t doepctl;
++03167         dctl_data_t dctl = {.d32 = 0 };
++03168 
++03169         /* Read the Device Status and Endpoint 0 Control registers */
++03170         dsts.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->dsts);
++03171         diepctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[0]->diepctl);
++03172         doepctl.d32 = DWC_READ_REG32(&dev_if->out_ep_regs[0]->doepctl);
++03173 
++03174         /* Set the MPS of the IN EP based on the enumeration speed */
++03175         switch (dsts.b.enumspd) {
++03176         case DWC_DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ:
++03177         case DWC_DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ:
++03178         case DWC_DSTS_ENUMSPD_FS_PHY_48MHZ:
++03179                 diepctl.b.mps = DWC_DEP0CTL_MPS_64;
++03180                 break;
++03181         case DWC_DSTS_ENUMSPD_LS_PHY_6MHZ:
++03182                 diepctl.b.mps = DWC_DEP0CTL_MPS_8;
++03183                 break;
++03184         }
++03185 
++03186         DWC_WRITE_REG32(&dev_if->in_ep_regs[0]->diepctl, diepctl.d32);
++03187 
++03188         /* Enable OUT EP for receive */
++03189         doepctl.b.epena = 1;
++03190         DWC_WRITE_REG32(&dev_if->out_ep_regs[0]->doepctl, doepctl.d32);
++03191 
++03192 #ifdef VERBOSE
++03193         DWC_DEBUGPL(DBG_PCDV, "doepctl0=%0x\n",
++03194                     DWC_READ_REG32(&dev_if->out_ep_regs[0]->doepctl));
++03195         DWC_DEBUGPL(DBG_PCDV, "diepctl0=%0x\n",
++03196                     DWC_READ_REG32(&dev_if->in_ep_regs[0]->diepctl));
++03197 #endif
++03198         dctl.b.cgnpinnak = 1;
++03199 
++03200         DWC_MODIFY_REG32(&dev_if->dev_global_regs->dctl, dctl.d32, dctl.d32);
++03201         DWC_DEBUGPL(DBG_PCDV, "dctl=%0x\n",
++03202                     DWC_READ_REG32(&dev_if->dev_global_regs->dctl));
++03203 
++03204 }
++03205 
++03214 void dwc_otg_ep_activate(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
++03215 {
++03216         dwc_otg_dev_if_t *dev_if = core_if->dev_if;
++03217         depctl_data_t depctl;
++03218         volatile uint32_t *addr;
++03219         daint_data_t daintmsk = {.d32 = 0 };
++03220         dcfg_data_t dcfg;
++03221         uint8_t i;
++03222 
++03223         DWC_DEBUGPL(DBG_PCDV, "%s() EP%d-%s\n", __func__, ep->num,
++03224                     (ep->is_in ? "IN" : "OUT"));
++03225 
++03226 #ifdef DWC_UTE_PER_IO
++03227         ep->xiso_frame_num = 0xFFFFFFFF;
++03228         ep->xiso_active_xfers = 0;
++03229         ep->xiso_queued_xfers = 0;
++03230 #endif
++03231         /* Read DEPCTLn register */
++03232         if (ep->is_in == 1) {
++03233                 addr = &dev_if->in_ep_regs[ep->num]->diepctl;
++03234                 daintmsk.ep.in = 1 << ep->num;
++03235         } else {
++03236                 addr = &dev_if->out_ep_regs[ep->num]->doepctl;
++03237                 daintmsk.ep.out = 1 << ep->num;
++03238         }
++03239 
++03240         /* If the EP is already active don't change the EP Control
++03241          * register. */
++03242         depctl.d32 = DWC_READ_REG32(addr);
++03243         if (!depctl.b.usbactep) {
++03244                 depctl.b.mps = ep->maxpacket;
++03245                 depctl.b.eptype = ep->type;
++03246                 depctl.b.txfnum = ep->tx_fifo_num;
++03247 
++03248                 if (ep->type == DWC_OTG_EP_TYPE_ISOC) {
++03249                         depctl.b.setd0pid = 1;  // ???
++03250                 } else {
++03251                         depctl.b.setd0pid = 1;
++03252                 }
++03253                 depctl.b.usbactep = 1;
++03254 
++03255                 /* Update nextep_seq array and EPMSCNT in DCFG*/
++03256                 if (!(depctl.b.eptype & 1) && (ep->is_in == 1)) {       // NP IN EP
++03257                         for (i = 0; i <= core_if->dev_if->num_in_eps; i++) {
++03258                                 if (core_if->nextep_seq[i] == core_if->first_in_nextep_seq)
++03259                                 break;
++03260                         }
++03261                         core_if->nextep_seq[i] = ep->num;       
++03262                         core_if->nextep_seq[ep->num] = core_if->first_in_nextep_seq;
++03263                         depctl.b.nextep = core_if->nextep_seq[ep->num];
++03264                         dcfg.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->dcfg);
++03265                         dcfg.b.epmscnt++;
++03266                         DWC_WRITE_REG32(&dev_if->dev_global_regs->dcfg, dcfg.d32);
++03267 
++03268                         DWC_DEBUGPL(DBG_PCDV,"%s first_in_nextep_seq= %2d; nextep_seq[]:\n", 
++03269                                 __func__, core_if->first_in_nextep_seq);
++03270                         for (i=0; i <= core_if->dev_if->num_in_eps; i++) {
++03271                                 DWC_DEBUGPL(DBG_PCDV, "%2d\n", core_if->nextep_seq[i]);
++03272                         }
++03273 
++03274                 }
++03275 
++03276 
++03277                 DWC_WRITE_REG32(addr, depctl.d32);
++03278                 DWC_DEBUGPL(DBG_PCDV, "DEPCTL=%08x\n", DWC_READ_REG32(addr));
++03279         }
++03280 
++03281         /* Enable the Interrupt for this EP */
++03282         if (core_if->multiproc_int_enable) {
++03283                 if (ep->is_in == 1) {
++03284                         diepmsk_data_t diepmsk = {.d32 = 0 };
++03285                         diepmsk.b.xfercompl = 1;
++03286                         diepmsk.b.timeout = 1;
++03287                         diepmsk.b.epdisabled = 1;
++03288                         diepmsk.b.ahberr = 1;
++03289                         diepmsk.b.intknepmis = 1;
++03290                         if (!core_if->en_multiple_tx_fifo && core_if->dma_enable)
++03291                                 diepmsk.b.intknepmis = 0; 
++03292                         diepmsk.b.txfifoundrn = 1;      //?????
++03293                         if (ep->type == DWC_OTG_EP_TYPE_ISOC) {
++03294                                 diepmsk.b.nak = 1;
++03295                         }
++03296 
++03297                         
++03298                         
++03299 /*
++03300                         if (core_if->dma_desc_enable) {
++03301                                 diepmsk.b.bna = 1;
++03302                         }
++03303 */
++03304 /*                      
++03305                         if (core_if->dma_enable) {
++03306                                 doepmsk.b.nak = 1;
++03307                         }
++03308 */
++03309                         DWC_WRITE_REG32(&dev_if->dev_global_regs->
++03310                                         diepeachintmsk[ep->num], diepmsk.d32);
++03311 
++03312                 } else {
++03313                         doepmsk_data_t doepmsk = {.d32 = 0 };
++03314                         doepmsk.b.xfercompl = 1;
++03315                         doepmsk.b.ahberr = 1;
++03316                         doepmsk.b.epdisabled = 1;
++03317                         if (ep->type == DWC_OTG_EP_TYPE_ISOC)
++03318                                 doepmsk.b.outtknepdis = 1;
++03319 
++03320 /*                      
++03321 
++03322                         if (core_if->dma_desc_enable) {
++03323                                 doepmsk.b.bna = 1;
++03324                         }
++03325 */
++03326 /*                      
++03327                         doepmsk.b.babble = 1;
++03328                         doepmsk.b.nyet = 1;
++03329                         doepmsk.b.nak = 1;
++03330 */
++03331                         DWC_WRITE_REG32(&dev_if->dev_global_regs->
++03332                                         doepeachintmsk[ep->num], doepmsk.d32);
++03333                 }
++03334                 DWC_MODIFY_REG32(&dev_if->dev_global_regs->deachintmsk,
++03335                                  0, daintmsk.d32);
++03336         } else {
++03337                 if (ep->type == DWC_OTG_EP_TYPE_ISOC) {
++03338                         if (ep->is_in)
++03339                         {
++03340                                 diepmsk_data_t diepmsk = {.d32 = 0 };
++03341                                 diepmsk.b.nak = 1;
++03342                                 DWC_MODIFY_REG32(&dev_if->dev_global_regs->diepmsk, 0, diepmsk.d32);
++03343                         } else {
++03344                                 doepmsk_data_t doepmsk = {.d32 = 0 };
++03345                                 doepmsk.b.outtknepdis = 1;
++03346                                 DWC_MODIFY_REG32(&dev_if->dev_global_regs->doepmsk, 0, doepmsk.d32);
++03347                         }
++03348                 }
++03349                 DWC_MODIFY_REG32(&dev_if->dev_global_regs->daintmsk,
++03350                                  0, daintmsk.d32);
++03351         }
++03352 
++03353         DWC_DEBUGPL(DBG_PCDV, "DAINTMSK=%0x\n",
++03354                     DWC_READ_REG32(&dev_if->dev_global_regs->daintmsk));
++03355 
++03356         ep->stall_clear_flag = 0;
++03357 
++03358         return;
++03359 }
++03360 
++03369 void dwc_otg_ep_deactivate(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
++03370 {
++03371         depctl_data_t depctl = {.d32 = 0 };
++03372         volatile uint32_t *addr;
++03373         daint_data_t daintmsk = {.d32 = 0 };
++03374         dcfg_data_t dcfg;
++03375         uint8_t i = 0;
++03376 
++03377 #ifdef DWC_UTE_PER_IO
++03378         ep->xiso_frame_num = 0xFFFFFFFF;
++03379         ep->xiso_active_xfers = 0;
++03380         ep->xiso_queued_xfers = 0;
++03381 #endif
++03382 
++03383         /* Read DEPCTLn register */
++03384         if (ep->is_in == 1) {
++03385                 addr = &core_if->dev_if->in_ep_regs[ep->num]->diepctl;
++03386                 daintmsk.ep.in = 1 << ep->num;
++03387         } else {
++03388                 addr = &core_if->dev_if->out_ep_regs[ep->num]->doepctl;
++03389                 daintmsk.ep.out = 1 << ep->num;
++03390         }
++03391 
++03392         depctl.d32 = DWC_READ_REG32(addr);
++03393 
++03394         depctl.b.usbactep = 0;
++03395         
++03396         /* Update nextep_seq array and EPMSCNT in DCFG*/
++03397         if (!(depctl.b.eptype & 1) && ep->is_in == 1) { // NP EP IN
++03398                 for (i = 0; i <= core_if->dev_if->num_in_eps; i++) {
++03399                         if (core_if->nextep_seq[i] == ep->num)
++03400                         break;
++03401                 }
++03402                 core_if->nextep_seq[i] = core_if->nextep_seq[ep->num];  
++03403                 if (core_if->first_in_nextep_seq == ep->num)
++03404                         core_if->first_in_nextep_seq = i;
++03405                 core_if->nextep_seq[ep->num] = 0xff;
++03406                 depctl.b.nextep = 0;
++03407                 dcfg.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg);
++03408                 dcfg.b.epmscnt--;
++03409                 DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dcfg, dcfg.d32);
++03410 
++03411                         DWC_DEBUGPL(DBG_PCDV,"%s first_in_nextep_seq= %2d; nextep_seq[]:\n", 
++03412                                 __func__, core_if->first_in_nextep_seq);
++03413                         for (i=0; i <= core_if->dev_if->num_in_eps; i++) {
++03414                                 DWC_DEBUGPL(DBG_PCDV, "%2d\n", core_if->nextep_seq[i]);
++03415                         }
++03416         }
++03417                 
++03418         if (ep->is_in == 1)
++03419                 depctl.b.txfnum = 0;
++03420 
++03421         if (core_if->dma_desc_enable)
++03422                 depctl.b.epdis = 1;
++03423 
++03424         DWC_WRITE_REG32(addr, depctl.d32);
++03425         depctl.d32 = DWC_READ_REG32(addr);
++03426         if (core_if->dma_enable && ep->type == DWC_OTG_EP_TYPE_ISOC && depctl.b.epena)
++03427         {
++03428                 depctl_data_t depctl = {.d32 = 0};
++03429                 if (ep->is_in)
++03430                 {
++03431                         diepint_data_t diepint = {.d32 = 0};
++03432                         
++03433                         depctl.b.snak = 1;
++03434                         DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[ep->num]->diepctl, depctl.d32);
++03435                         do 
++03436                         {
++03437                                 dwc_udelay(10);
++03438                                 diepint.d32 = DWC_READ_REG32(&core_if->dev_if->
++03439                                                                                         in_ep_regs[ep->num]->diepint);
++03440                         } while (!diepint.b.inepnakeff); 
++03441                         diepint.b.inepnakeff = 1;
++03442                         DWC_WRITE_REG32(&core_if->dev_if->
++03443                                                         in_ep_regs[ep->num]->diepint, diepint.d32);
++03444                         depctl.d32 = 0;
++03445                         depctl.b.epdis = 1;
++03446                         DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[ep->num]->diepctl, depctl.d32);
++03447                         do 
++03448                         {
++03449                                 dwc_udelay(10);
++03450                                 diepint.d32 = DWC_READ_REG32(&core_if->dev_if->
++03451                                                                                         in_ep_regs[ep->num]->diepint);
++03452                         } while (!diepint.b.epdisabled); 
++03453                         diepint.b.epdisabled = 1;
++03454                         DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[ep->num]->diepint, diepint.d32);
++03455                 } else {
++03456                         dctl_data_t dctl = {.d32 = 0};
++03457                         gintmsk_data_t gintsts = {.d32 = 0};
++03458                         doepint_data_t doepint = {.d32 = 0};
++03459                         dctl.b.sgoutnak = 1;
++03460                         DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, 0, dctl.d32);
++03461                         do 
++03462                         {
++03463                                 dwc_udelay(10);
++03464                                 gintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts);
++03465                         } while (!gintsts.b.goutnakeff); 
++03466                         gintsts.d32 = 0;
++03467                         gintsts.b.goutnakeff = 1;
++03468                         DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
++03469 
++03470                         depctl.d32 = 0;
++03471                         depctl.b.epdis = 1;
++03472                         depctl.b.snak = 1;
++03473                         DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[ep->num]->doepctl, depctl.d32);
++03474                         do 
++03475                         {
++03476                                 dwc_udelay(10);
++03477                                 doepint.d32 = DWC_READ_REG32(&core_if->dev_if->
++03478                                                                                         out_ep_regs[ep->num]->doepint);
++03479                         } while (!doepint.b.epdisabled); 
++03480 
++03481                         doepint.b.epdisabled = 1;
++03482                         DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[ep->num]->doepint, doepint.d32);
++03483 
++03484                         dctl.d32 = 0;
++03485                         dctl.b.cgoutnak = 1;
++03486                         DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, 0, dctl.d32);
++03487                 }               
++03488         }
++03489 
++03490         /* Disable the Interrupt for this EP */
++03491         if (core_if->multiproc_int_enable) {
++03492                 DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->deachintmsk,
++03493                                  daintmsk.d32, 0);
++03494 
++03495                 if (ep->is_in == 1) {
++03496                         DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->
++03497                                         diepeachintmsk[ep->num], 0);
++03498                 } else {
++03499                         DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->
++03500                                         doepeachintmsk[ep->num], 0);
++03501                 }
++03502         } else {
++03503                 DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->daintmsk,
++03504                                  daintmsk.d32, 0);
++03505         }
++03506 
++03507 }
++03508 
++03515 static void init_dma_desc_chain(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
++03516 {
++03517         dwc_otg_dev_dma_desc_t *dma_desc;
++03518         uint32_t offset;
++03519         uint32_t xfer_est;
++03520         int i;
++03521         unsigned maxxfer_local, total_len;
++03522         
++03523         if (!ep->is_in && ep->type == DWC_OTG_EP_TYPE_INTR && 
++03524                                         (ep->maxpacket%4)) {
++03525                 maxxfer_local = ep->maxpacket;
++03526                 total_len = ep->xfer_len;
++03527         } else {
++03528                 maxxfer_local = ep->maxxfer;
++03529                 total_len = ep->total_len;
++03530         }
++03531 
++03532         ep->desc_cnt = (total_len / maxxfer_local) +
++03533             ((total_len % maxxfer_local) ? 1 : 0);
++03534 
++03535         if (!ep->desc_cnt)
++03536                 ep->desc_cnt = 1;
++03537 
++03538         if (ep->desc_cnt > MAX_DMA_DESC_CNT)
++03539                 ep->desc_cnt = MAX_DMA_DESC_CNT;
++03540 
++03541         dma_desc = ep->desc_addr;
++03542         if (maxxfer_local == ep->maxpacket) {
++03543                 if ((total_len % maxxfer_local) &&
++03544                                 (total_len/maxxfer_local < MAX_DMA_DESC_CNT)) {
++03545                         xfer_est = (ep->desc_cnt - 1) * maxxfer_local +
++03546                                         (total_len % maxxfer_local);
++03547                 } else
++03548                         xfer_est = ep->desc_cnt * maxxfer_local;
++03549         }
++03550         else
++03551                 xfer_est = total_len;
++03552         offset = 0;
++03553         for (i = 0; i < ep->desc_cnt; ++i) {
++03555                 if (xfer_est > maxxfer_local) {
++03556                         dma_desc->status.b.bs = BS_HOST_BUSY;
++03557                         dma_desc->status.b.l = 0;
++03558                         dma_desc->status.b.ioc = 0;
++03559                         dma_desc->status.b.sp = 0;
++03560                         dma_desc->status.b.bytes = maxxfer_local;
++03561                         dma_desc->buf = ep->dma_addr + offset;
++03562                         dma_desc->status.b.sts = 0;
++03563                         dma_desc->status.b.bs = BS_HOST_READY;
++03564 
++03565                         xfer_est -= maxxfer_local;
++03566                         offset += maxxfer_local;
++03567                 } else {
++03568                         dma_desc->status.b.bs = BS_HOST_BUSY;
++03569                         dma_desc->status.b.l = 1;
++03570                         dma_desc->status.b.ioc = 1;
++03571                         if (ep->is_in) {
++03572                                 dma_desc->status.b.sp =
++03573                                     (xfer_est %
++03574                                      ep->maxpacket) ? 1 : ((ep->
++03575                                                             sent_zlp) ? 1 : 0);
++03576                                 dma_desc->status.b.bytes = xfer_est;
++03577                         } else {
++03578                                 if (maxxfer_local == ep->maxpacket)
++03579                                         dma_desc->status.b.bytes = xfer_est;
++03580                                 else    
++03581                                         dma_desc->status.b.bytes =
++03582                                                 xfer_est + ((4 - (xfer_est & 0x3)) & 0x3);
++03583                         }
++03584 
++03585                         dma_desc->buf = ep->dma_addr + offset;
++03586                         dma_desc->status.b.sts = 0;
++03587                         dma_desc->status.b.bs = BS_HOST_READY;
++03588                 }
++03589                 dma_desc++;
++03590         }
++03591 }
++03596 static int32_t write_isoc_tx_fifo(dwc_otg_core_if_t * core_if, dwc_ep_t * dwc_ep)
++03597 {
++03598         dwc_otg_dev_if_t *dev_if = core_if->dev_if;
++03599         dwc_otg_dev_in_ep_regs_t *ep_regs;
++03600         dtxfsts_data_t txstatus = {.d32 = 0 };
++03601         uint32_t len = 0;
++03602         int epnum = dwc_ep->num;
++03603         int dwords;
++03604 
++03605         DWC_DEBUGPL(DBG_PCD, "Dedicated TxFifo Empty: %d \n", epnum);
++03606 
++03607         ep_regs = core_if->dev_if->in_ep_regs[epnum];
++03608 
++03609         len = dwc_ep->xfer_len - dwc_ep->xfer_count;
++03610 
++03611         if (len > dwc_ep->maxpacket) {
++03612                 len = dwc_ep->maxpacket;
++03613         }
++03614 
++03615         dwords = (len + 3) / 4;
++03616 
++03617         /* While there is space in the queue and space in the FIFO and
++03618          * More data to tranfer, Write packets to the Tx FIFO */
++03619         txstatus.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->dtxfsts);
++03620         DWC_DEBUGPL(DBG_PCDV, "b4 dtxfsts[%d]=0x%08x\n", epnum, txstatus.d32);
++03621 
++03622         while (txstatus.b.txfspcavail > dwords &&
++03623                dwc_ep->xfer_count < dwc_ep->xfer_len &&
++03624                dwc_ep->xfer_len != 0) {
++03625                 /* Write the FIFO */
++03626                 dwc_otg_ep_write_packet(core_if, dwc_ep, 0);
++03627 
++03628                 len = dwc_ep->xfer_len - dwc_ep->xfer_count;
++03629                 if (len > dwc_ep->maxpacket) {
++03630                         len = dwc_ep->maxpacket;
++03631                 }
++03632 
++03633                 dwords = (len + 3) / 4;
++03634                 txstatus.d32 =
++03635                     DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->dtxfsts);
++03636                 DWC_DEBUGPL(DBG_PCDV, "dtxfsts[%d]=0x%08x\n", epnum,
++03637                             txstatus.d32);
++03638         }
++03639 
++03640         DWC_DEBUGPL(DBG_PCDV, "b4 dtxfsts[%d]=0x%08x\n", epnum,
++03641                     DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->dtxfsts));
++03642 
++03643         return 1;
++03644 }
++03655 void dwc_otg_ep_start_transfer(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
++03656 {
++03657         depctl_data_t depctl;
++03658         deptsiz_data_t deptsiz;
++03659         gintmsk_data_t intr_mask = {.d32 = 0 };
++03660 
++03661         DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "%s()\n", __func__);
++03662         DWC_DEBUGPL(DBG_PCD, "ep%d-%s xfer_len=%d xfer_cnt=%d "
++03663                     "xfer_buff=%p start_xfer_buff=%p, total_len = %d\n",
++03664                     ep->num, (ep->is_in ? "IN" : "OUT"), ep->xfer_len,
++03665                     ep->xfer_count, ep->xfer_buff, ep->start_xfer_buff,
++03666                     ep->total_len);
++03667         /* IN endpoint */
++03668         if (ep->is_in == 1) {
++03669                 dwc_otg_dev_in_ep_regs_t *in_regs =
++03670                     core_if->dev_if->in_ep_regs[ep->num];
++03671 
++03672                 gnptxsts_data_t gtxstatus;
++03673 
++03674                 gtxstatus.d32 =
++03675                     DWC_READ_REG32(&core_if->core_global_regs->gnptxsts);
++03676 
++03677                 if (core_if->en_multiple_tx_fifo == 0
++03678                     && gtxstatus.b.nptxqspcavail == 0
++03679                     && !core_if->dma_enable) {
++03680 #ifdef DEBUG
++03681                         DWC_PRINTF("TX Queue Full (0x%0x)\n", gtxstatus.d32);
++03682 #endif
++03683                         return;
++03684                 }
++03685 
++03686                 depctl.d32 = DWC_READ_REG32(&(in_regs->diepctl));
++03687                 deptsiz.d32 = DWC_READ_REG32(&(in_regs->dieptsiz));
++03688 
++03689                 if (ep->maxpacket > ep->maxxfer / MAX_PKT_CNT)
++03690                         ep->xfer_len += (ep->maxxfer < (ep->total_len - ep->xfer_len)) ?
++03691                                 ep->maxxfer : (ep->total_len - ep->xfer_len);
++03692                 else 
++03693                         ep->xfer_len += (MAX_PKT_CNT * ep->maxpacket < (ep->total_len - ep->xfer_len)) ?
++03694                                  MAX_PKT_CNT * ep->maxpacket : (ep->total_len - ep->xfer_len);
++03695 
++03696 
++03697                 /* Zero Length Packet? */
++03698                 if ((ep->xfer_len - ep->xfer_count) == 0) {
++03699                         deptsiz.b.xfersize = 0;
++03700                         deptsiz.b.pktcnt = 1;
++03701                 } else {
++03702                         /* Program the transfer size and packet count
++03703                          *      as follows: xfersize = N * maxpacket +
++03704                          *      short_packet pktcnt = N + (short_packet
++03705                          *      exist ? 1 : 0) 
++03706                          */
++03707                         deptsiz.b.xfersize = ep->xfer_len - ep->xfer_count;
++03708                         deptsiz.b.pktcnt =
++03709                             (ep->xfer_len - ep->xfer_count - 1 +
++03710                              ep->maxpacket) / ep->maxpacket;
++03711                         if (deptsiz.b.pktcnt > MAX_PKT_CNT) {
++03712                                 deptsiz.b.pktcnt = MAX_PKT_CNT;
++03713                                 deptsiz.b.xfersize = deptsiz.b.pktcnt * ep->maxpacket;
++03714                         } 
++03715                         if (ep->type == DWC_OTG_EP_TYPE_ISOC) 
++03716                                 deptsiz.b.mc = deptsiz.b.pktcnt;
++03717                 }
++03718 
++03719                 /* Write the DMA register */
++03720                 if (core_if->dma_enable) {
++03721                         if (core_if->dma_desc_enable == 0) {
++03722                                 if (ep->type != DWC_OTG_EP_TYPE_ISOC)
++03723                                         deptsiz.b.mc = 1;
++03724                                 DWC_WRITE_REG32(&in_regs->dieptsiz,
++03725                                                 deptsiz.d32);
++03726                                 DWC_WRITE_REG32(&(in_regs->diepdma),
++03727                                                 (uint32_t) ep->dma_addr);
++03728                         } else {
++03729 #ifdef DWC_UTE_CFI
++03730                                 /* The descriptor chain should be already initialized by now */
++03731                                 if (ep->buff_mode != BM_STANDARD) {
++03732                                         DWC_WRITE_REG32(&in_regs->diepdma,
++03733                                                         ep->descs_dma_addr);
++03734                                 } else {
++03735 #endif
++03736                                         init_dma_desc_chain(core_if, ep);
++03738                                         DWC_WRITE_REG32(&in_regs->diepdma,
++03739                                                         ep->dma_desc_addr);
++03740 #ifdef DWC_UTE_CFI
++03741                                 }
++03742 #endif
++03743                         }
++03744                 } else {
++03745                         DWC_WRITE_REG32(&in_regs->dieptsiz, deptsiz.d32);
++03746                         if (ep->type != DWC_OTG_EP_TYPE_ISOC) {
++03752                                 if (core_if->en_multiple_tx_fifo == 0) {
++03753                                         intr_mask.b.nptxfempty = 1;
++03754                                         DWC_MODIFY_REG32
++03755                                             (&core_if->core_global_regs->gintmsk,
++03756                                              intr_mask.d32, intr_mask.d32);
++03757                                 } else {
++03758                                         /* Enable the Tx FIFO Empty Interrupt for this EP */
++03759                                         if (ep->xfer_len > 0) {
++03760                                                 uint32_t fifoemptymsk = 0;
++03761                                                 fifoemptymsk = 1 << ep->num;
++03762                                                 DWC_MODIFY_REG32
++03763                                                     (&core_if->dev_if->dev_global_regs->dtknqr4_fifoemptymsk,
++03764                                                      0, fifoemptymsk);
++03765 
++03766                                         }
++03767                                 }
++03768                         }  else {
++03769                                          write_isoc_tx_fifo(core_if, ep);
++03770                         }
++03771                 }
++03772                 if (!core_if->core_params->en_multiple_tx_fifo && core_if->dma_enable)
++03773                         depctl.b.nextep = core_if->nextep_seq[ep->num];
++03774                 
++03775                 if (ep->type == DWC_OTG_EP_TYPE_ISOC)
++03776                 {
++03777                         dsts_data_t dsts = {.d32 = 0};
++03778                         if (ep->bInterval == 1) {
++03779                                 dsts.d32 =
++03780                                         DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts);
++03781                                 ep->frame_num = dsts.b.soffn + ep->bInterval;
++03782                                 if (ep->frame_num > 0x3FFF)
++03783                                 {
++03784                                         ep->frm_overrun = 1;
++03785                                         ep->frame_num &= 0x3FFF;
++03786                                 } else 
++03787                                         ep->frm_overrun = 0;
++03788                                 if (ep->frame_num & 0x1) {
++03789                                         depctl.b.setd1pid = 1;
++03790                                 } else {
++03791                                         depctl.b.setd0pid = 1;
++03792                                 }
++03793                         }
++03794                 }
++03795                 /* EP enable, IN data in FIFO */
++03796                 depctl.b.cnak = 1;
++03797                 depctl.b.epena = 1;
++03798                 DWC_WRITE_REG32(&in_regs->diepctl, depctl.d32);
++03799 
++03800         } else {
++03801                 /* OUT endpoint */
++03802                 dwc_otg_dev_out_ep_regs_t *out_regs =
++03803                     core_if->dev_if->out_ep_regs[ep->num];
++03804 
++03805                 depctl.d32 = DWC_READ_REG32(&(out_regs->doepctl));
++03806                 deptsiz.d32 = DWC_READ_REG32(&(out_regs->doeptsiz));
++03807 
++03808                 if (!core_if->dma_desc_enable) {        
++03809                         if (ep->maxpacket > ep->maxxfer / MAX_PKT_CNT)
++03810                                 ep->xfer_len += (ep->maxxfer < (ep->total_len - ep->xfer_len)) ?
++03811                                 ep->maxxfer : (ep->total_len - ep->xfer_len);
++03812                 else
++03813                                         ep->xfer_len += (MAX_PKT_CNT * ep->maxpacket < (ep->total_len 
++03814                                         - ep->xfer_len)) ? MAX_PKT_CNT * ep->maxpacket : (ep->total_len - ep->xfer_len);
++03815                 }
++03816 
++03817                 /* Program the transfer size and packet count as follows:
++03818                  *
++03819                  *      pktcnt = N                                                                                
++03820                  *      xfersize = N * maxpacket
++03821                  */
++03822                 if ((ep->xfer_len - ep->xfer_count) == 0) {
++03823                         /* Zero Length Packet */
++03824                         deptsiz.b.xfersize = ep->maxpacket;
++03825                         deptsiz.b.pktcnt = 1;
++03826                 } else {
++03827                         deptsiz.b.pktcnt =
++03828                             (ep->xfer_len - ep->xfer_count +
++03829                              (ep->maxpacket - 1)) / ep->maxpacket;
++03830                         if (deptsiz.b.pktcnt > MAX_PKT_CNT) {
++03831                                 deptsiz.b.pktcnt = MAX_PKT_CNT;
++03832                         }
++03833                         if (!core_if->dma_desc_enable) {
++03834                                 ep->xfer_len =
++03835                                         deptsiz.b.pktcnt * ep->maxpacket + ep->xfer_count;
++03836                         }
++03837                         deptsiz.b.xfersize = ep->xfer_len - ep->xfer_count;
++03838                 }
++03839 
++03840                 DWC_DEBUGPL(DBG_PCDV, "ep%d xfersize=%d pktcnt=%d\n",
++03841                             ep->num, deptsiz.b.xfersize, deptsiz.b.pktcnt);
++03842 
++03843                 if (core_if->dma_enable) {
++03844                         if (!core_if->dma_desc_enable) {
++03845                                 DWC_WRITE_REG32(&out_regs->doeptsiz,
++03846                                                 deptsiz.d32);
++03847 
++03848                                 DWC_WRITE_REG32(&(out_regs->doepdma),
++03849                                                 (uint32_t) ep->dma_addr);
++03850                         } else {
++03851 #ifdef DWC_UTE_CFI
++03852                                 /* The descriptor chain should be already initialized by now */
++03853                                 if (ep->buff_mode != BM_STANDARD) {
++03854                                         DWC_WRITE_REG32(&out_regs->doepdma,
++03855                                                         ep->descs_dma_addr);
++03856                                 } else {
++03857 #endif
++03858 
++03859                                         if (!ep->xfer_len)
++03860                                                 ep->xfer_len = ep->total_len;
++03861                                         init_dma_desc_chain(core_if, ep);
++03862 
++03863                                         if (core_if->core_params->dev_out_nak) {
++03864                                                 if (ep->type == DWC_OTG_EP_TYPE_BULK) {
++03865                                                         deptsiz.b.pktcnt = (ep->total_len +
++03866                                                                 (ep->maxpacket - 1)) / ep->maxpacket;
++03867                                                         deptsiz.b.xfersize = ep->total_len;
++03868                                                         /* Remember initial value of doeptsiz */
++03869                                                         core_if->start_doeptsiz_val[ep->num] = deptsiz.d32;
++03870                                                         DWC_WRITE_REG32(&out_regs->doeptsiz,
++03871                                                                 deptsiz.d32);                                                                                                   
++03872                                                 }
++03873                                         }
++03875                                         DWC_WRITE_REG32(&out_regs->doepdma,
++03876                                                         ep->dma_desc_addr);
++03877 #ifdef DWC_UTE_CFI
++03878                                 }
++03879 #endif
++03880                         }
++03881                 } else {
++03882                         DWC_WRITE_REG32(&out_regs->doeptsiz, deptsiz.d32);
++03883                 }
++03884 
++03885                 if (ep->type == DWC_OTG_EP_TYPE_ISOC)
++03886                 {
++03887                         dsts_data_t dsts = {.d32 = 0};
++03888                         if (ep->bInterval == 1) {
++03889                                 dsts.d32 =
++03890                                         DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts);
++03891                                 ep->frame_num = dsts.b.soffn + ep->bInterval;
++03892                                 if (ep->frame_num > 0x3FFF)
++03893                                 {
++03894                                         ep->frm_overrun = 1;
++03895                                         ep->frame_num &= 0x3FFF;
++03896                                 } else 
++03897                                         ep->frm_overrun = 0;
++03898 
++03899                                 if (ep->frame_num & 0x1) {
++03900                                         depctl.b.setd1pid = 1;
++03901                                 } else {
++03902                                         depctl.b.setd0pid = 1;
++03903                                 }
++03904                         }
++03905                 }
++03906 
++03907                 /* EP enable */
++03908                 depctl.b.cnak = 1;
++03909                 depctl.b.epena = 1;
++03910 
++03911                 DWC_WRITE_REG32(&out_regs->doepctl, depctl.d32);
++03912 
++03913                 DWC_DEBUGPL(DBG_PCD, "DOEPCTL=%08x DOEPTSIZ=%08x\n",
++03914                             DWC_READ_REG32(&out_regs->doepctl),
++03915                             DWC_READ_REG32(&out_regs->doeptsiz));
++03916                 DWC_DEBUGPL(DBG_PCD, "DAINTMSK=%08x GINTMSK=%08x\n",
++03917                             DWC_READ_REG32(&core_if->dev_if->
++03918                                            dev_global_regs->daintmsk),
++03919                             DWC_READ_REG32(&core_if->
++03920                                            core_global_regs->gintmsk));
++03921 
++03922 
++03923                 /* Timer is scheduling only for out bulk transfers for 
++03924                  * "Device DDMA OUT NAK Enhancement" feature to inform user 
++03925                  * about received data payload in case of timeout 
++03926                  */
++03927                 if (core_if->core_params->dev_out_nak) {
++03928                         if (ep->type == DWC_OTG_EP_TYPE_BULK) {
++03929                                 core_if->ep_xfer_info[ep->num].core_if = core_if;
++03930                                 core_if->ep_xfer_info[ep->num].ep = ep;
++03931                                 core_if->ep_xfer_info[ep->num].state = 1;
++03932 
++03933                                 /* Start a timer for this transfer. */
++03934                                 DWC_TIMER_SCHEDULE(core_if->ep_xfer_timer[ep->num], 10000);
++03935                         }
++03936                 }
++03937         }
++03938 }
++03939 
++03948 void dwc_otg_ep_start_zl_transfer(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
++03949 {
++03950 
++03951         depctl_data_t depctl;
++03952         deptsiz_data_t deptsiz;
++03953         gintmsk_data_t intr_mask = {.d32 = 0 };
++03954 
++03955         DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "%s()\n", __func__);
++03956         DWC_PRINTF("zero length transfer is called\n");
++03957 
++03958         /* IN endpoint */
++03959         if (ep->is_in == 1) {
++03960                 dwc_otg_dev_in_ep_regs_t *in_regs =
++03961                     core_if->dev_if->in_ep_regs[ep->num];
++03962 
++03963                 depctl.d32 = DWC_READ_REG32(&(in_regs->diepctl));
++03964                 deptsiz.d32 = DWC_READ_REG32(&(in_regs->dieptsiz));
++03965 
++03966                 deptsiz.b.xfersize = 0;
++03967                 deptsiz.b.pktcnt = 1;
++03968 
++03969                 /* Write the DMA register */
++03970                 if (core_if->dma_enable) {
++03971                         if (core_if->dma_desc_enable == 0) {
++03972                                 deptsiz.b.mc = 1;
++03973                                 DWC_WRITE_REG32(&in_regs->dieptsiz,
++03974                                                 deptsiz.d32);
++03975                                 DWC_WRITE_REG32(&(in_regs->diepdma),
++03976                                                 (uint32_t) ep->dma_addr);
++03977                         }
++03978                 } else {
++03979                         DWC_WRITE_REG32(&in_regs->dieptsiz, deptsiz.d32);
++03985                         if (core_if->en_multiple_tx_fifo == 0) {
++03986                                 intr_mask.b.nptxfempty = 1;
++03987                                 DWC_MODIFY_REG32(&core_if->
++03988                                                  core_global_regs->gintmsk,
++03989                                                  intr_mask.d32, intr_mask.d32);
++03990                         } else {
++03991                                 /* Enable the Tx FIFO Empty Interrupt for this EP */
++03992                                 if (ep->xfer_len > 0) {
++03993                                         uint32_t fifoemptymsk = 0;
++03994                                         fifoemptymsk = 1 << ep->num;
++03995                                         DWC_MODIFY_REG32(&core_if->
++03996                                                          dev_if->dev_global_regs->dtknqr4_fifoemptymsk,
++03997                                                          0, fifoemptymsk);
++03998                                 }
++03999                         }
++04000                 }
++04001 
++04002                 if (!core_if->core_params->en_multiple_tx_fifo && core_if->dma_enable)
++04003                         depctl.b.nextep = core_if->nextep_seq[ep->num];
++04004                 /* EP enable, IN data in FIFO */
++04005                 depctl.b.cnak = 1;
++04006                 depctl.b.epena = 1;
++04007                 DWC_WRITE_REG32(&in_regs->diepctl, depctl.d32);
++04008 
++04009         } else {
++04010                 /* OUT endpoint */
++04011                 dwc_otg_dev_out_ep_regs_t *out_regs =
++04012                     core_if->dev_if->out_ep_regs[ep->num];
++04013 
++04014                 depctl.d32 = DWC_READ_REG32(&(out_regs->doepctl));
++04015                 deptsiz.d32 = DWC_READ_REG32(&(out_regs->doeptsiz));
++04016 
++04017                 /* Zero Length Packet */
++04018                 deptsiz.b.xfersize = ep->maxpacket;
++04019                 deptsiz.b.pktcnt = 1;
++04020 
++04021                 if (core_if->dma_enable) {
++04022                         if (!core_if->dma_desc_enable) {
++04023                                 DWC_WRITE_REG32(&out_regs->doeptsiz,
++04024                                                 deptsiz.d32);
++04025 
++04026                                 DWC_WRITE_REG32(&(out_regs->doepdma),
++04027                                                 (uint32_t) ep->dma_addr);
++04028                         }
++04029                 } else {
++04030                         DWC_WRITE_REG32(&out_regs->doeptsiz, deptsiz.d32);
++04031                 }
++04032 
++04033                 /* EP enable */
++04034                 depctl.b.cnak = 1;
++04035                 depctl.b.epena = 1;
++04036 
++04037                 DWC_WRITE_REG32(&out_regs->doepctl, depctl.d32);
++04038 
++04039         }
++04040 }
++04041 
++04051 void dwc_otg_ep0_start_transfer(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
++04052 {
++04053         depctl_data_t depctl;
++04054         deptsiz0_data_t deptsiz;
++04055         gintmsk_data_t intr_mask = {.d32 = 0 };
++04056         dwc_otg_dev_dma_desc_t *dma_desc;
++04057 
++04058         DWC_DEBUGPL(DBG_PCD, "ep%d-%s xfer_len=%d xfer_cnt=%d "
++04059                     "xfer_buff=%p start_xfer_buff=%p \n",
++04060                     ep->num, (ep->is_in ? "IN" : "OUT"), ep->xfer_len,
++04061                     ep->xfer_count, ep->xfer_buff, ep->start_xfer_buff);
++04062 
++04063         ep->total_len = ep->xfer_len;
++04064 
++04065         /* IN endpoint */
++04066         if (ep->is_in == 1) {
++04067                 dwc_otg_dev_in_ep_regs_t *in_regs =
++04068                     core_if->dev_if->in_ep_regs[0];
++04069 
++04070                 gnptxsts_data_t gtxstatus;
++04071 
++04072                 gtxstatus.d32 =
++04073                     DWC_READ_REG32(&core_if->core_global_regs->gnptxsts);
++04074 
++04075                 if (core_if->en_multiple_tx_fifo == 0
++04076                     && gtxstatus.b.nptxqspcavail == 0
++04077                     && !core_if->dma_enable) {
++04078 #ifdef DEBUG
++04079                         deptsiz.d32 = DWC_READ_REG32(&in_regs->dieptsiz);
++04080                         DWC_DEBUGPL(DBG_PCD, "DIEPCTL0=%0x\n",
++04081                                     DWC_READ_REG32(&in_regs->diepctl));
++04082                         DWC_DEBUGPL(DBG_PCD, "DIEPTSIZ0=%0x (sz=%d, pcnt=%d)\n",
++04083                                     deptsiz.d32,
++04084                                     deptsiz.b.xfersize, deptsiz.b.pktcnt);
++04085                         DWC_PRINTF("TX Queue or FIFO Full (0x%0x)\n",
++04086                                    gtxstatus.d32);
++04087 #endif
++04088                         return;
++04089                 }
++04090 
++04091                 depctl.d32 = DWC_READ_REG32(&in_regs->diepctl);
++04092                 deptsiz.d32 = DWC_READ_REG32(&in_regs->dieptsiz);
++04093 
++04094                 /* Zero Length Packet? */
++04095                 if (ep->xfer_len == 0) {
++04096                         deptsiz.b.xfersize = 0;
++04097                         deptsiz.b.pktcnt = 1;
++04098                 } else {
++04099                         /* Program the transfer size and packet count
++04100                          *      as follows: xfersize = N * maxpacket +
++04101                          *      short_packet pktcnt = N + (short_packet
++04102                          *      exist ? 1 : 0) 
++04103                          */
++04104                         if (ep->xfer_len > ep->maxpacket) {
++04105                                 ep->xfer_len = ep->maxpacket;
++04106                                 deptsiz.b.xfersize = ep->maxpacket;
++04107                         } else {
++04108                                 deptsiz.b.xfersize = ep->xfer_len;
++04109                         }
++04110                         deptsiz.b.pktcnt = 1;
++04111 
++04112                 }
++04113                 DWC_DEBUGPL(DBG_PCDV,
++04114                             "IN len=%d  xfersize=%d pktcnt=%d [%08x]\n",
++04115                             ep->xfer_len, deptsiz.b.xfersize, deptsiz.b.pktcnt,
++04116                             deptsiz.d32);
++04117 
++04118                 /* Write the DMA register */
++04119                 if (core_if->dma_enable) {
++04120                         if (core_if->dma_desc_enable == 0) {
++04121                                 DWC_WRITE_REG32(&in_regs->dieptsiz,
++04122                                                 deptsiz.d32);
++04123 
++04124                                 DWC_WRITE_REG32(&(in_regs->diepdma),
++04125                                                 (uint32_t) ep->dma_addr);
++04126                         } else {
++04127                                 dma_desc = core_if->dev_if->in_desc_addr;
++04128 
++04130                                 dma_desc->status.b.bs = BS_HOST_BUSY;
++04131                                 dma_desc->status.b.l = 1;
++04132                                 dma_desc->status.b.ioc = 1;
++04133                                 dma_desc->status.b.sp =
++04134                                     (ep->xfer_len == ep->maxpacket) ? 0 : 1;
++04135                                 dma_desc->status.b.bytes = ep->xfer_len;
++04136                                 dma_desc->buf = ep->dma_addr;
++04137                                 dma_desc->status.b.sts = 0;
++04138                                 dma_desc->status.b.bs = BS_HOST_READY;
++04139 
++04141                                 DWC_WRITE_REG32(&in_regs->diepdma,
++04142                                                 core_if->
++04143                                                 dev_if->dma_in_desc_addr);
++04144                         }
++04145                 } else {
++04146                         DWC_WRITE_REG32(&in_regs->dieptsiz, deptsiz.d32);
++04147                 }
++04148 
++04149                 if (!core_if->core_params->en_multiple_tx_fifo && core_if->dma_enable)
++04150                         depctl.b.nextep = core_if->nextep_seq[ep->num];
++04151                 /* EP enable, IN data in FIFO */
++04152                 depctl.b.cnak = 1;
++04153                 depctl.b.epena = 1;
++04154                 DWC_WRITE_REG32(&in_regs->diepctl, depctl.d32);
++04155 
++04160                 if (!core_if->dma_enable) {
++04161                         if (core_if->en_multiple_tx_fifo == 0) {
++04162                                 intr_mask.b.nptxfempty = 1;
++04163                                 DWC_MODIFY_REG32(&core_if->
++04164                                                  core_global_regs->gintmsk,
++04165                                                  intr_mask.d32, intr_mask.d32);
++04166                         } else {
++04167                                 /* Enable the Tx FIFO Empty Interrupt for this EP */
++04168                                 if (ep->xfer_len > 0) {
++04169                                         uint32_t fifoemptymsk = 0;
++04170                                         fifoemptymsk |= 1 << ep->num;
++04171                                         DWC_MODIFY_REG32(&core_if->
++04172                                                          dev_if->dev_global_regs->dtknqr4_fifoemptymsk,
++04173                                                          0, fifoemptymsk);
++04174                                 }
++04175                         }
++04176                 }
++04177         } else {
++04178                 /* OUT endpoint */
++04179                 dwc_otg_dev_out_ep_regs_t *out_regs =
++04180                     core_if->dev_if->out_ep_regs[0];
++04181 
++04182                 depctl.d32 = DWC_READ_REG32(&out_regs->doepctl);
++04183                 deptsiz.d32 = DWC_READ_REG32(&out_regs->doeptsiz);
++04184 
++04185                 /* Program the transfer size and packet count as follows:
++04186                  *      xfersize = N * (maxpacket + 4 - (maxpacket % 4))
++04187                  *      pktcnt = N                                                                                      */
++04188                 /* Zero Length Packet */
++04189                 deptsiz.b.xfersize = ep->maxpacket;
++04190                 deptsiz.b.pktcnt = 1;
++04191 
++04192                 DWC_DEBUGPL(DBG_PCDV, "len=%d  xfersize=%d pktcnt=%d\n",
++04193                             ep->xfer_len, deptsiz.b.xfersize, deptsiz.b.pktcnt);
++04194 
++04195                 if (core_if->dma_enable) {
++04196                         if (!core_if->dma_desc_enable) {
++04197                                 DWC_WRITE_REG32(&out_regs->doeptsiz,
++04198                                                 deptsiz.d32);
++04199 
++04200                                 DWC_WRITE_REG32(&(out_regs->doepdma),
++04201                                                 (uint32_t) ep->dma_addr);
++04202                         } else {
++04203                                 dma_desc = core_if->dev_if->out_desc_addr;
++04204 
++04206                                 dma_desc->status.b.bs = BS_HOST_BUSY;
++04207                                 dma_desc->status.b.l = 1;
++04208                                 dma_desc->status.b.ioc = 1;
++04209                                 dma_desc->status.b.bytes = ep->maxpacket;
++04210                                 dma_desc->buf = ep->dma_addr;
++04211                                 dma_desc->status.b.sts = 0;
++04212                                 dma_desc->status.b.bs = BS_HOST_READY;
++04213 
++04215                                 DWC_WRITE_REG32(&out_regs->doepdma,
++04216                                                 core_if->
++04217                                                 dev_if->dma_out_desc_addr);
++04218                         }
++04219                 } else {
++04220                         DWC_WRITE_REG32(&out_regs->doeptsiz, deptsiz.d32);
++04221                 }
++04222 
++04223                 /* EP enable */
++04224                 depctl.b.cnak = 1;
++04225                 depctl.b.epena = 1;
++04226                 DWC_WRITE_REG32(&(out_regs->doepctl), depctl.d32);
++04227         }
++04228 }
++04229 
++04239 void dwc_otg_ep0_continue_transfer(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
++04240 {
++04241         depctl_data_t depctl;
++04242         deptsiz0_data_t deptsiz;
++04243         gintmsk_data_t intr_mask = {.d32 = 0 };
++04244         dwc_otg_dev_dma_desc_t *dma_desc;
++04245 
++04246         if (ep->is_in == 1) {
++04247                 dwc_otg_dev_in_ep_regs_t *in_regs =
++04248                     core_if->dev_if->in_ep_regs[0];
++04249                 gnptxsts_data_t tx_status = {.d32 = 0 };
++04250 
++04251                 tx_status.d32 =
++04252                     DWC_READ_REG32(&core_if->core_global_regs->gnptxsts);
++04256                 depctl.d32 = DWC_READ_REG32(&in_regs->diepctl);
++04257                 deptsiz.d32 = DWC_READ_REG32(&in_regs->dieptsiz);
++04258 
++04259                 /* Program the transfer size and packet count
++04260                  *      as follows: xfersize = N * maxpacket +
++04261                  *      short_packet pktcnt = N + (short_packet
++04262                  *      exist ? 1 : 0) 
++04263                  */
++04264 
++04265                 if (core_if->dma_desc_enable == 0) {
++04266                         deptsiz.b.xfersize =
++04267                             (ep->total_len - ep->xfer_count) >
++04268                             ep->maxpacket ? ep->maxpacket : (ep->total_len -
++04269                                                              ep->xfer_count);
++04270                         deptsiz.b.pktcnt = 1;
++04271                         if (core_if->dma_enable == 0) {
++04272                                 ep->xfer_len += deptsiz.b.xfersize;
++04273                         } else {
++04274                                 ep->xfer_len = deptsiz.b.xfersize;
++04275                         }
++04276                         DWC_WRITE_REG32(&in_regs->dieptsiz, deptsiz.d32);
++04277                 } else {
++04278                         ep->xfer_len =
++04279                             (ep->total_len - ep->xfer_count) >
++04280                             ep->maxpacket ? ep->maxpacket : (ep->total_len -
++04281                                                              ep->xfer_count);
++04282 
++04283                         dma_desc = core_if->dev_if->in_desc_addr;
++04284 
++04286                         dma_desc->status.b.bs = BS_HOST_BUSY;
++04287                         dma_desc->status.b.l = 1;
++04288                         dma_desc->status.b.ioc = 1;
++04289                         dma_desc->status.b.sp =
++04290                             (ep->xfer_len == ep->maxpacket) ? 0 : 1;
++04291                         dma_desc->status.b.bytes = ep->xfer_len;
++04292                         dma_desc->buf = ep->dma_addr;
++04293                         dma_desc->status.b.sts = 0;
++04294                         dma_desc->status.b.bs = BS_HOST_READY;
++04295 
++04297                         DWC_WRITE_REG32(&in_regs->diepdma,
++04298                                         core_if->dev_if->dma_in_desc_addr);
++04299                 }
++04300 
++04301                 DWC_DEBUGPL(DBG_PCDV,
++04302                             "IN len=%d  xfersize=%d pktcnt=%d [%08x]\n",
++04303                             ep->xfer_len, deptsiz.b.xfersize, deptsiz.b.pktcnt,
++04304                             deptsiz.d32);
++04305 
++04306                 /* Write the DMA register */
++04307                 if (core_if->hwcfg2.b.architecture == DWC_INT_DMA_ARCH) {
++04308                         if (core_if->dma_desc_enable == 0)
++04309                                 DWC_WRITE_REG32(&(in_regs->diepdma),
++04310                                                 (uint32_t) ep->dma_addr);
++04311                 }
++04312                 if (!core_if->core_params->en_multiple_tx_fifo && core_if->dma_enable)
++04313                         depctl.b.nextep = core_if->nextep_seq[ep->num];
++04314                 /* EP enable, IN data in FIFO */
++04315                 depctl.b.cnak = 1;
++04316                 depctl.b.epena = 1;
++04317                 DWC_WRITE_REG32(&in_regs->diepctl, depctl.d32);
++04318 
++04323                 if (!core_if->dma_enable) {
++04324                         if (core_if->en_multiple_tx_fifo == 0) {
++04325                                 /* First clear it from GINTSTS */
++04326                                 intr_mask.b.nptxfempty = 1;
++04327                                 DWC_MODIFY_REG32(&core_if->
++04328                                                  core_global_regs->gintmsk,
++04329                                                  intr_mask.d32, intr_mask.d32);
++04330 
++04331                         } else {
++04332                                 /* Enable the Tx FIFO Empty Interrupt for this EP */
++04333                                 if (ep->xfer_len > 0) {
++04334                                         uint32_t fifoemptymsk = 0;
++04335                                         fifoemptymsk |= 1 << ep->num;
++04336                                         DWC_MODIFY_REG32(&core_if->
++04337                                                          dev_if->dev_global_regs->dtknqr4_fifoemptymsk,
++04338                                                          0, fifoemptymsk);
++04339                                 }
++04340                         }
++04341                 }
++04342         } else {
++04343                 dwc_otg_dev_out_ep_regs_t *out_regs =
++04344                     core_if->dev_if->out_ep_regs[0];
++04345 
++04346                 depctl.d32 = DWC_READ_REG32(&out_regs->doepctl);
++04347                 deptsiz.d32 = DWC_READ_REG32(&out_regs->doeptsiz);
++04348 
++04349                 /* Program the transfer size and packet count
++04350                  *      as follows: xfersize = N * maxpacket +
++04351                  *      short_packet pktcnt = N + (short_packet
++04352                  *      exist ? 1 : 0) 
++04353                  */
++04354                 deptsiz.b.xfersize = ep->maxpacket;
++04355                 deptsiz.b.pktcnt = 1;
++04356 
++04357                 if (core_if->dma_desc_enable == 0) {
++04358                         DWC_WRITE_REG32(&out_regs->doeptsiz, deptsiz.d32);
++04359                 } else {
++04360                         dma_desc = core_if->dev_if->out_desc_addr;
++04361 
++04363                         dma_desc->status.b.bs = BS_HOST_BUSY;
++04364                         dma_desc->status.b.l = 1;
++04365                         dma_desc->status.b.ioc = 1;
++04366                         dma_desc->status.b.bytes = ep->maxpacket;
++04367                         dma_desc->buf = ep->dma_addr;
++04368                         dma_desc->status.b.sts = 0;
++04369                         dma_desc->status.b.bs = BS_HOST_READY;
++04370 
++04372                         DWC_WRITE_REG32(&out_regs->doepdma,
++04373                                         core_if->dev_if->dma_out_desc_addr);
++04374                 }
++04375 
++04376                 DWC_DEBUGPL(DBG_PCDV,
++04377                             "IN len=%d  xfersize=%d pktcnt=%d [%08x]\n",
++04378                             ep->xfer_len, deptsiz.b.xfersize, deptsiz.b.pktcnt,
++04379                             deptsiz.d32);
++04380 
++04381                 /* Write the DMA register */
++04382                 if (core_if->hwcfg2.b.architecture == DWC_INT_DMA_ARCH) {
++04383                         if (core_if->dma_desc_enable == 0)
++04384                                 DWC_WRITE_REG32(&(out_regs->doepdma),
++04385                                                 (uint32_t) ep->dma_addr);
++04386 
++04387                 }
++04388 
++04389                 /* EP enable, IN data in FIFO */
++04390                 depctl.b.cnak = 1;
++04391                 depctl.b.epena = 1;
++04392                 DWC_WRITE_REG32(&out_regs->doepctl, depctl.d32);
++04393 
++04394         }
++04395 }
++04396 
++04397 #ifdef DEBUG
++04398 void dump_msg(const u8 * buf, unsigned int length)
++04399 {
++04400         unsigned int start, num, i;
++04401         char line[52], *p;
++04402 
++04403         if (length >= 512)
++04404                 return;
++04405         start = 0;
++04406         while (length > 0) {
++04407                 num = length < 16u ? length : 16u;
++04408                 p = line;
++04409                 for (i = 0; i < num; ++i) {
++04410                         if (i == 8)
++04411                                 *p++ = ' ';
++04412                         DWC_SPRINTF(p, " %02x", buf[i]);
++04413                         p += 3;
++04414                 }
++04415                 *p = 0;
++04416                 DWC_PRINTF("%6x: %s\n", start, line);
++04417                 buf += num;
++04418                 start += num;
++04419                 length -= num;
++04420         }
++04421 }
++04422 #else
++04423 static inline void dump_msg(const u8 * buf, unsigned int length)
++04424 {
++04425 }
++04426 #endif
++04427 
++04438 void dwc_otg_ep_write_packet(dwc_otg_core_if_t * core_if, dwc_ep_t * ep,
++04439                              int dma)
++04440 {
++04456         uint32_t i;
++04457         uint32_t byte_count;
++04458         uint32_t dword_count;
++04459         uint32_t *fifo;
++04460         uint32_t *data_buff = (uint32_t *) ep->xfer_buff;
++04461 
++04462         DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "%s(%p,%p)\n", __func__, core_if,
++04463                     ep);
++04464         if (ep->xfer_count >= ep->xfer_len) {
++04465                 DWC_WARN("%s() No data for EP%d!!!\n", __func__, ep->num);
++04466                 return;
++04467         }
++04468 
++04469         /* Find the byte length of the packet either short packet or MPS */
++04470         if ((ep->xfer_len - ep->xfer_count) < ep->maxpacket) {
++04471                 byte_count = ep->xfer_len - ep->xfer_count;
++04472         } else {
++04473                 byte_count = ep->maxpacket;
++04474         }
++04475 
++04476         /* Find the DWORD length, padded by extra bytes as neccessary if MPS
++04477          * is not a multiple of DWORD */
++04478         dword_count = (byte_count + 3) / 4;
++04479 
++04480 #ifdef VERBOSE
++04481         dump_msg(ep->xfer_buff, byte_count);
++04482 #endif
++04483 
++04487         fifo = core_if->data_fifo[ep->num];
++04488 
++04489         DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "fifo=%p buff=%p *p=%08x bc=%d\n",
++04490                     fifo, data_buff, *data_buff, byte_count);
++04491 
++04492         if (!dma) {
++04493                 for (i = 0; i < dword_count; i++, data_buff++) {
++04494                         DWC_WRITE_REG32(fifo, *data_buff);
++04495                 }
++04496         }
++04497 
++04498         ep->xfer_count += byte_count;
++04499         ep->xfer_buff += byte_count;
++04500         ep->dma_addr += byte_count;
++04501 }
++04502 
++04509 void dwc_otg_ep_set_stall(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
++04510 {
++04511         depctl_data_t depctl;
++04512         volatile uint32_t *depctl_addr;
++04513 
++04514         DWC_DEBUGPL(DBG_PCD, "%s ep%d-%s\n", __func__, ep->num,
++04515                     (ep->is_in ? "IN" : "OUT"));
++04516 
++04517         if (ep->is_in == 1) {
++04518                 depctl_addr = &(core_if->dev_if->in_ep_regs[ep->num]->diepctl);
++04519                 depctl.d32 = DWC_READ_REG32(depctl_addr);
++04520 
++04521                 /* set the disable and stall bits */
++04522                 if (depctl.b.epena) {
++04523                         depctl.b.epdis = 1;
++04524                 }
++04525                 depctl.b.stall = 1;
++04526                 DWC_WRITE_REG32(depctl_addr, depctl.d32);
++04527         } else {
++04528                 depctl_addr = &(core_if->dev_if->out_ep_regs[ep->num]->doepctl);
++04529                 depctl.d32 = DWC_READ_REG32(depctl_addr);
++04530 
++04531                 /* set the stall bit */
++04532                 depctl.b.stall = 1;
++04533                 DWC_WRITE_REG32(depctl_addr, depctl.d32);
++04534         }
++04535 
++04536         DWC_DEBUGPL(DBG_PCD, "DEPCTL=%0x\n", DWC_READ_REG32(depctl_addr));
++04537 
++04538         return;
++04539 }
++04540 
++04547 void dwc_otg_ep_clear_stall(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
++04548 {
++04549         depctl_data_t depctl;
++04550         volatile uint32_t *depctl_addr;
++04551 
++04552         DWC_DEBUGPL(DBG_PCD, "%s ep%d-%s\n", __func__, ep->num,
++04553                     (ep->is_in ? "IN" : "OUT"));
++04554 
++04555         if (ep->is_in == 1) {
++04556                 depctl_addr = &(core_if->dev_if->in_ep_regs[ep->num]->diepctl);
++04557         } else {
++04558                 depctl_addr = &(core_if->dev_if->out_ep_regs[ep->num]->doepctl);
++04559         }
++04560 
++04561         depctl.d32 = DWC_READ_REG32(depctl_addr);
++04562 
++04563         /* clear the stall bits */
++04564         depctl.b.stall = 0;
++04565 
++04566         /*
++04567          * USB Spec 9.4.5: For endpoints using data toggle, regardless
++04568          * of whether an endpoint has the Halt feature set, a
++04569          * ClearFeature(ENDPOINT_HALT) request always results in the
++04570          * data toggle being reinitialized to DATA0.
++04571          */
++04572         if (ep->type == DWC_OTG_EP_TYPE_INTR ||
++04573             ep->type == DWC_OTG_EP_TYPE_BULK) {
++04574                 depctl.b.setd0pid = 1;  /* DATA0 */
++04575         }
++04576 
++04577         DWC_WRITE_REG32(depctl_addr, depctl.d32);
++04578         DWC_DEBUGPL(DBG_PCD, "DEPCTL=%0x\n", DWC_READ_REG32(depctl_addr));
++04579         return;
++04580 }
++04581 
++04590 void dwc_otg_read_packet(dwc_otg_core_if_t * core_if,
++04591                          uint8_t * dest, uint16_t bytes)
++04592 {
++04593         int i;
++04594         int word_count = (bytes + 3) / 4;
++04595 
++04596         volatile uint32_t *fifo = core_if->data_fifo[0];
++04597         uint32_t *data_buff = (uint32_t *) dest;
++04598 
++04605         DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "%s(%p,%p,%d)\n", __func__,
++04606                     core_if, dest, bytes);
++04607 
++04608         for (i = 0; i < word_count; i++, data_buff++) {
++04609                 *data_buff = DWC_READ_REG32(fifo);
++04610         }
++04611 
++04612         return;
++04613 }
++04614 
++04620 void dwc_otg_dump_dev_registers(dwc_otg_core_if_t * core_if)
++04621 {
++04622         int i;
++04623         volatile uint32_t *addr;
++04624 
++04625         DWC_PRINTF("Device Global Registers\n");
++04626         addr = &core_if->dev_if->dev_global_regs->dcfg;
++04627         DWC_PRINTF("DCFG                 @0x%08lX : 0x%08X\n", (unsigned long) addr,
++04628                    DWC_READ_REG32(addr));
++04629         addr = &core_if->dev_if->dev_global_regs->dctl;
++04630         DWC_PRINTF("DCTL                 @0x%08lX : 0x%08X\n", (unsigned long) addr,
++04631                    DWC_READ_REG32(addr));
++04632         addr = &core_if->dev_if->dev_global_regs->dsts;
++04633         DWC_PRINTF("DSTS                 @0x%08lX : 0x%08X\n", (unsigned long) addr,
++04634                    DWC_READ_REG32(addr));
++04635         addr = &core_if->dev_if->dev_global_regs->diepmsk;
++04636         DWC_PRINTF("DIEPMSK      @0x%08lX : 0x%08X\n", (unsigned long)addr,
++04637                    DWC_READ_REG32(addr));
++04638         addr = &core_if->dev_if->dev_global_regs->doepmsk;
++04639         DWC_PRINTF("DOEPMSK      @0x%08lX : 0x%08X\n", (unsigned long)addr,
++04640                    DWC_READ_REG32(addr));
++04641         addr = &core_if->dev_if->dev_global_regs->daint;
++04642         DWC_PRINTF("DAINT        @0x%08lX : 0x%08X\n", (unsigned long)addr,
++04643                    DWC_READ_REG32(addr));
++04644         addr = &core_if->dev_if->dev_global_regs->daintmsk;
++04645         DWC_PRINTF("DAINTMSK     @0x%08lX : 0x%08X\n", (unsigned long)addr,
++04646                    DWC_READ_REG32(addr));
++04647         addr = &core_if->dev_if->dev_global_regs->dtknqr1;
++04648         DWC_PRINTF("DTKNQR1      @0x%08lX : 0x%08X\n", (unsigned long)addr,
++04649                    DWC_READ_REG32(addr));
++04650         if (core_if->hwcfg2.b.dev_token_q_depth > 6) {
++04651                 addr = &core_if->dev_if->dev_global_regs->dtknqr2;
++04652                 DWC_PRINTF("DTKNQR2      @0x%08lX : 0x%08X\n",
++04653                            (unsigned long)addr, DWC_READ_REG32(addr));
++04654         }
++04655 
++04656         addr = &core_if->dev_if->dev_global_regs->dvbusdis;
++04657         DWC_PRINTF("DVBUSID      @0x%08lX : 0x%08X\n", (unsigned long)addr,
++04658                    DWC_READ_REG32(addr));
++04659 
++04660         addr = &core_if->dev_if->dev_global_regs->dvbuspulse;
++04661         DWC_PRINTF("DVBUSPULSE  @0x%08lX : 0x%08X\n",
++04662                    (unsigned long)addr, DWC_READ_REG32(addr));
++04663 
++04664         addr = &core_if->dev_if->dev_global_regs->dtknqr3_dthrctl;
++04665         DWC_PRINTF("DTKNQR3_DTHRCTL      @0x%08lX : 0x%08X\n",
++04666                    (unsigned long)addr, DWC_READ_REG32(addr));
++04667 
++04668         if (core_if->hwcfg2.b.dev_token_q_depth > 22) {
++04669                 addr = &core_if->dev_if->dev_global_regs->dtknqr4_fifoemptymsk;
++04670                 DWC_PRINTF("DTKNQR4      @0x%08lX : 0x%08X\n",
++04671                            (unsigned long)addr, DWC_READ_REG32(addr));
++04672         }
++04673 
++04674         addr = &core_if->dev_if->dev_global_regs->dtknqr4_fifoemptymsk;
++04675         DWC_PRINTF("FIFOEMPMSK   @0x%08lX : 0x%08X\n", (unsigned long)addr,
++04676                    DWC_READ_REG32(addr));
++04677 
++04678         if (core_if->hwcfg2.b.multi_proc_int) {
++04679 
++04680                 addr = &core_if->dev_if->dev_global_regs->deachint;
++04681                 DWC_PRINTF("DEACHINT     @0x%08lX : 0x%08X\n",
++04682                            (unsigned long)addr, DWC_READ_REG32(addr));
++04683                 addr = &core_if->dev_if->dev_global_regs->deachintmsk;
++04684                 DWC_PRINTF("DEACHINTMSK  @0x%08lX : 0x%08X\n",
++04685                            (unsigned long)addr, DWC_READ_REG32(addr));
++04686 
++04687                 for (i = 0; i <= core_if->dev_if->num_in_eps; i++) {
++04688                         addr =
++04689                             &core_if->dev_if->dev_global_regs->
++04690                             diepeachintmsk[i];
++04691                         DWC_PRINTF("DIEPEACHINTMSK[%d]   @0x%08lX : 0x%08X\n",
++04692                                    i, (unsigned long)addr,
++04693                                    DWC_READ_REG32(addr));
++04694                 }
++04695 
++04696                 for (i = 0; i <= core_if->dev_if->num_out_eps; i++) {
++04697                         addr =
++04698                             &core_if->dev_if->dev_global_regs->
++04699                             doepeachintmsk[i];
++04700                         DWC_PRINTF("DOEPEACHINTMSK[%d]   @0x%08lX : 0x%08X\n",
++04701                                    i, (unsigned long)addr,
++04702                                    DWC_READ_REG32(addr));
++04703                 }
++04704         }
++04705 
++04706         for (i = 0; i <= core_if->dev_if->num_in_eps; i++) {
++04707                 DWC_PRINTF("Device IN EP %d Registers\n", i);
++04708                 addr = &core_if->dev_if->in_ep_regs[i]->diepctl;
++04709                 DWC_PRINTF("DIEPCTL      @0x%08lX : 0x%08X\n",
++04710                            (unsigned long)addr, DWC_READ_REG32(addr));
++04711                 addr = &core_if->dev_if->in_ep_regs[i]->diepint;
++04712                 DWC_PRINTF("DIEPINT      @0x%08lX : 0x%08X\n",
++04713                            (unsigned long)addr, DWC_READ_REG32(addr));
++04714                 addr = &core_if->dev_if->in_ep_regs[i]->dieptsiz;
++04715                 DWC_PRINTF("DIETSIZ      @0x%08lX : 0x%08X\n",
++04716                            (unsigned long)addr, DWC_READ_REG32(addr));
++04717                 addr = &core_if->dev_if->in_ep_regs[i]->diepdma;
++04718                 DWC_PRINTF("DIEPDMA      @0x%08lX : 0x%08X\n",
++04719                            (unsigned long)addr, DWC_READ_REG32(addr));
++04720                 addr = &core_if->dev_if->in_ep_regs[i]->dtxfsts;
++04721                 DWC_PRINTF("DTXFSTS      @0x%08lX : 0x%08X\n",
++04722                            (unsigned long)addr, DWC_READ_REG32(addr));
++04723                 addr = &core_if->dev_if->in_ep_regs[i]->diepdmab;
++04724                 DWC_PRINTF("DIEPDMAB     @0x%08lX : 0x%08X\n",
++04725                            (unsigned long)addr, 0 /*DWC_READ_REG32(addr) */ );
++04726         }
++04727 
++04728         for (i = 0; i <= core_if->dev_if->num_out_eps; i++) {
++04729                 DWC_PRINTF("Device OUT EP %d Registers\n", i);
++04730                 addr = &core_if->dev_if->out_ep_regs[i]->doepctl;
++04731                 DWC_PRINTF("DOEPCTL      @0x%08lX : 0x%08X\n",
++04732                            (unsigned long)addr, DWC_READ_REG32(addr));
++04733                 addr = &core_if->dev_if->out_ep_regs[i]->doepint;
++04734                 DWC_PRINTF("DOEPINT      @0x%08lX : 0x%08X\n",
++04735                            (unsigned long)addr, DWC_READ_REG32(addr));
++04736                 addr = &core_if->dev_if->out_ep_regs[i]->doeptsiz;
++04737                 DWC_PRINTF("DOETSIZ      @0x%08lX : 0x%08X\n",
++04738                            (unsigned long)addr, DWC_READ_REG32(addr));
++04739                 addr = &core_if->dev_if->out_ep_regs[i]->doepdma;
++04740                 DWC_PRINTF("DOEPDMA      @0x%08lX : 0x%08X\n",
++04741                            (unsigned long)addr, DWC_READ_REG32(addr));
++04742                 if (core_if->dma_enable) {      /* Don't access this register in SLAVE mode */
++04743                         addr = &core_if->dev_if->out_ep_regs[i]->doepdmab;
++04744                         DWC_PRINTF("DOEPDMAB     @0x%08lX : 0x%08X\n",
++04745                                    (unsigned long)addr, DWC_READ_REG32(addr));
++04746                 }
++04747 
++04748         }
++04749 }
++04750 
++04756 void dwc_otg_dump_spram(dwc_otg_core_if_t * core_if)
++04757 {
++04758         volatile uint8_t *addr, *start_addr, *end_addr;
++04759 
++04760         DWC_PRINTF("SPRAM Data:\n");
++04761         start_addr = (void *)core_if->core_global_regs;
++04762         DWC_PRINTF("Base Address: 0x%8lX\n", (unsigned long)start_addr);
++04763         start_addr += 0x00028000;
++04764         end_addr = (void *)core_if->core_global_regs;
++04765         end_addr += 0x000280e0;
++04766 
++04767         for (addr = start_addr; addr < end_addr; addr += 16) {
++04768                 DWC_PRINTF
++04769                     ("0x%8lX:\t%2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X\n",
++04770                      (unsigned long)addr, addr[0], addr[1], addr[2], addr[3],
++04771                      addr[4], addr[5], addr[6], addr[7], addr[8], addr[9],
++04772                      addr[10], addr[11], addr[12], addr[13], addr[14], addr[15]
++04773                     );
++04774         }
++04775 
++04776         return;
++04777 }
++04778 
++04784 void dwc_otg_dump_host_registers(dwc_otg_core_if_t * core_if)
++04785 {
++04786         int i;
++04787         volatile uint32_t *addr;
++04788 
++04789         DWC_PRINTF("Host Global Registers\n");
++04790         addr = &core_if->host_if->host_global_regs->hcfg;
++04791         DWC_PRINTF("HCFG                 @0x%08lX : 0x%08X\n",
++04792                    (unsigned long)addr, DWC_READ_REG32(addr));
++04793         addr = &core_if->host_if->host_global_regs->hfir;
++04794         DWC_PRINTF("HFIR                 @0x%08lX : 0x%08X\n",
++04795                    (unsigned long)addr, DWC_READ_REG32(addr));
++04796         addr = &core_if->host_if->host_global_regs->hfnum;
++04797         DWC_PRINTF("HFNUM        @0x%08lX : 0x%08X\n", (unsigned long)addr,
++04798                    DWC_READ_REG32(addr));
++04799         addr = &core_if->host_if->host_global_regs->hptxsts;
++04800         DWC_PRINTF("HPTXSTS      @0x%08lX : 0x%08X\n", (unsigned long)addr,
++04801                    DWC_READ_REG32(addr));
++04802         addr = &core_if->host_if->host_global_regs->haint;
++04803         DWC_PRINTF("HAINT        @0x%08lX : 0x%08X\n", (unsigned long)addr,
++04804                    DWC_READ_REG32(addr));
++04805         addr = &core_if->host_if->host_global_regs->haintmsk;
++04806         DWC_PRINTF("HAINTMSK     @0x%08lX : 0x%08X\n", (unsigned long)addr,
++04807                    DWC_READ_REG32(addr));
++04808         if (core_if->dma_desc_enable) {
++04809                 addr = &core_if->host_if->host_global_regs->hflbaddr;
++04810                 DWC_PRINTF("HFLBADDR     @0x%08lX : 0x%08X\n",
++04811                            (unsigned long)addr, DWC_READ_REG32(addr));
++04812         }
++04813 
++04814         addr = core_if->host_if->hprt0;
++04815         DWC_PRINTF("HPRT0        @0x%08lX : 0x%08X\n", (unsigned long)addr,
++04816                    DWC_READ_REG32(addr));
++04817 
++04818         for (i = 0; i < core_if->core_params->host_channels; i++) {
++04819                 DWC_PRINTF("Host Channel %d Specific Registers\n", i);
++04820                 addr = &core_if->host_if->hc_regs[i]->hcchar;
++04821                 DWC_PRINTF("HCCHAR       @0x%08lX : 0x%08X\n",
++04822                            (unsigned long)addr, DWC_READ_REG32(addr));
++04823                 addr = &core_if->host_if->hc_regs[i]->hcsplt;
++04824                 DWC_PRINTF("HCSPLT       @0x%08lX : 0x%08X\n",
++04825                            (unsigned long)addr, DWC_READ_REG32(addr));
++04826                 addr = &core_if->host_if->hc_regs[i]->hcint;
++04827                 DWC_PRINTF("HCINT        @0x%08lX : 0x%08X\n",
++04828                            (unsigned long)addr, DWC_READ_REG32(addr));
++04829                 addr = &core_if->host_if->hc_regs[i]->hcintmsk;
++04830                 DWC_PRINTF("HCINTMSK     @0x%08lX : 0x%08X\n",
++04831                            (unsigned long)addr, DWC_READ_REG32(addr));
++04832                 addr = &core_if->host_if->hc_regs[i]->hctsiz;
++04833                 DWC_PRINTF("HCTSIZ       @0x%08lX : 0x%08X\n",
++04834                            (unsigned long)addr, DWC_READ_REG32(addr));
++04835                 addr = &core_if->host_if->hc_regs[i]->hcdma;
++04836                 DWC_PRINTF("HCDMA        @0x%08lX : 0x%08X\n",
++04837                            (unsigned long)addr, DWC_READ_REG32(addr));
++04838                 if (core_if->dma_desc_enable) {
++04839                         addr = &core_if->host_if->hc_regs[i]->hcdmab;
++04840                         DWC_PRINTF("HCDMAB       @0x%08lX : 0x%08X\n",
++04841                                    (unsigned long)addr, DWC_READ_REG32(addr));
++04842                 }
++04843 
++04844         }
++04845         return;
++04846 }
++04847 
++04853 void dwc_otg_dump_global_registers(dwc_otg_core_if_t * core_if)
++04854 {
++04855         int i, ep_num;
++04856         volatile uint32_t *addr;
++04857         char *txfsiz;
++04858 
++04859         DWC_PRINTF("Core Global Registers\n");
++04860         addr = &core_if->core_global_regs->gotgctl;
++04861         DWC_PRINTF("GOTGCTL      @0x%08lX : 0x%08X\n", (unsigned long)addr,
++04862                    DWC_READ_REG32(addr));
++04863         addr = &core_if->core_global_regs->gotgint;
++04864         DWC_PRINTF("GOTGINT      @0x%08lX : 0x%08X\n", (unsigned long)addr,
++04865                    DWC_READ_REG32(addr));
++04866         addr = &core_if->core_global_regs->gahbcfg;
++04867         DWC_PRINTF("GAHBCFG      @0x%08lX : 0x%08X\n", (unsigned long)addr,
++04868                    DWC_READ_REG32(addr));
++04869         addr = &core_if->core_global_regs->gusbcfg;
++04870         DWC_PRINTF("GUSBCFG      @0x%08lX : 0x%08X\n", (unsigned long)addr,
++04871                    DWC_READ_REG32(addr));
++04872         addr = &core_if->core_global_regs->grstctl;
++04873         DWC_PRINTF("GRSTCTL      @0x%08lX : 0x%08X\n", (unsigned long)addr,
++04874                    DWC_READ_REG32(addr));
++04875         addr = &core_if->core_global_regs->gintsts;
++04876         DWC_PRINTF("GINTSTS      @0x%08lX : 0x%08X\n", (unsigned long)addr,
++04877                    DWC_READ_REG32(addr));
++04878         addr = &core_if->core_global_regs->gintmsk;
++04879         DWC_PRINTF("GINTMSK      @0x%08lX : 0x%08X\n", (unsigned long)addr,
++04880                    DWC_READ_REG32(addr));
++04881         addr = &core_if->core_global_regs->grxstsr;
++04882         DWC_PRINTF("GRXSTSR      @0x%08lX : 0x%08X\n", (unsigned long)addr,
++04883                    DWC_READ_REG32(addr));
++04884         addr = &core_if->core_global_regs->grxfsiz;
++04885         DWC_PRINTF("GRXFSIZ      @0x%08lX : 0x%08X\n", (unsigned long)addr,
++04886                    DWC_READ_REG32(addr));
++04887         addr = &core_if->core_global_regs->gnptxfsiz;
++04888         DWC_PRINTF("GNPTXFSIZ @0x%08lX : 0x%08X\n", (unsigned long)addr,
++04889                    DWC_READ_REG32(addr));
++04890         addr = &core_if->core_global_regs->gnptxsts;
++04891         DWC_PRINTF("GNPTXSTS     @0x%08lX : 0x%08X\n", (unsigned long)addr,
++04892                    DWC_READ_REG32(addr));
++04893         addr = &core_if->core_global_regs->gi2cctl;
++04894         DWC_PRINTF("GI2CCTL      @0x%08lX : 0x%08X\n", (unsigned long)addr,
++04895                    DWC_READ_REG32(addr));
++04896         addr = &core_if->core_global_regs->gpvndctl;
++04897         DWC_PRINTF("GPVNDCTL     @0x%08lX : 0x%08X\n", (unsigned long)addr,
++04898                    DWC_READ_REG32(addr));
++04899         addr = &core_if->core_global_regs->ggpio;
++04900         DWC_PRINTF("GGPIO        @0x%08lX : 0x%08X\n", (unsigned long)addr,
++04901                    DWC_READ_REG32(addr));
++04902         addr = &core_if->core_global_regs->guid;
++04903         DWC_PRINTF("GUID                 @0x%08lX : 0x%08X\n",
++04904                    (unsigned long)addr, DWC_READ_REG32(addr));
++04905         addr = &core_if->core_global_regs->gsnpsid;
++04906         DWC_PRINTF("GSNPSID      @0x%08lX : 0x%08X\n", (unsigned long)addr,
++04907                    DWC_READ_REG32(addr));
++04908         addr = &core_if->core_global_regs->ghwcfg1;
++04909         DWC_PRINTF("GHWCFG1      @0x%08lX : 0x%08X\n", (unsigned long)addr,
++04910                    DWC_READ_REG32(addr));
++04911         addr = &core_if->core_global_regs->ghwcfg2;
++04912         DWC_PRINTF("GHWCFG2      @0x%08lX : 0x%08X\n", (unsigned long)addr,
++04913                    DWC_READ_REG32(addr));
++04914         addr = &core_if->core_global_regs->ghwcfg3;
++04915         DWC_PRINTF("GHWCFG3      @0x%08lX : 0x%08X\n", (unsigned long)addr,
++04916                    DWC_READ_REG32(addr));
++04917         addr = &core_if->core_global_regs->ghwcfg4;
++04918         DWC_PRINTF("GHWCFG4      @0x%08lX : 0x%08X\n", (unsigned long)addr,
++04919                    DWC_READ_REG32(addr));
++04920         addr = &core_if->core_global_regs->glpmcfg;
++04921         DWC_PRINTF("GLPMCFG      @0x%08lX : 0x%08X\n", (unsigned long)addr,
++04922                    DWC_READ_REG32(addr));
++04923         addr = &core_if->core_global_regs->gpwrdn;
++04924         DWC_PRINTF("GPWRDN       @0x%08lX : 0x%08X\n", (unsigned long)addr,
++04925                    DWC_READ_REG32(addr));
++04926         addr = &core_if->core_global_regs->gdfifocfg;
++04927         DWC_PRINTF("GDFIFOCFG    @0x%08lX : 0x%08X\n", (unsigned long)addr,
++04928                    DWC_READ_REG32(addr));
++04929         addr = &core_if->core_global_regs->adpctl;
++04930         DWC_PRINTF("ADPCTL       @0x%08lX : 0x%08X\n", (unsigned long)addr,
++04931                    dwc_otg_adp_read_reg(core_if));
++04932         addr = &core_if->core_global_regs->hptxfsiz;
++04933         DWC_PRINTF("HPTXFSIZ     @0x%08lX : 0x%08X\n", (unsigned long)addr,
++04934                    DWC_READ_REG32(addr));
++04935 
++04936         if (core_if->en_multiple_tx_fifo == 0) {
++04937                 ep_num = core_if->hwcfg4.b.num_dev_perio_in_ep;
++04938                 txfsiz = "DPTXFSIZ";
++04939         } else {
++04940                 ep_num = core_if->hwcfg4.b.num_in_eps;
++04941                 txfsiz = "DIENPTXF";
++04942         }
++04943         for (i = 0; i < ep_num; i++) {
++04944                 addr = &core_if->core_global_regs->dtxfsiz[i];
++04945                 DWC_PRINTF("%s[%d] @0x%08lX : 0x%08X\n", txfsiz, i + 1,
++04946                            (unsigned long)addr, DWC_READ_REG32(addr));
++04947         }
++04948         addr = core_if->pcgcctl;
++04949         DWC_PRINTF("PCGCCTL      @0x%08lX : 0x%08X\n", (unsigned long)addr,
++04950                    DWC_READ_REG32(addr));
++04951 }
++04952 
++04959 void dwc_otg_flush_tx_fifo(dwc_otg_core_if_t * core_if, const int num)
++04960 {
++04961         dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
++04962         volatile grstctl_t greset = {.d32 = 0 };
++04963         int count = 0;
++04964 
++04965         DWC_DEBUGPL((DBG_CIL | DBG_PCDV), "Flush Tx FIFO %d\n", num);
++04966 
++04967         greset.b.txfflsh = 1;
++04968         greset.b.txfnum = num;
++04969         DWC_WRITE_REG32(&global_regs->grstctl, greset.d32);
++04970 
++04971         do {
++04972                 greset.d32 = DWC_READ_REG32(&global_regs->grstctl);
++04973                 if (++count > 10000) {
++04974                         DWC_WARN("%s() HANG! GRSTCTL=%0x GNPTXSTS=0x%08x\n",
++04975                                  __func__, greset.d32,
++04976                                  DWC_READ_REG32(&global_regs->gnptxsts));
++04977                         break;
++04978                 }
++04979                 dwc_udelay(1);
++04980         } while (greset.b.txfflsh == 1);
++04981 
++04982         /* Wait for 3 PHY Clocks */
++04983         dwc_udelay(1);
++04984 }
++04985 
++04991 void dwc_otg_flush_rx_fifo(dwc_otg_core_if_t * core_if)
++04992 {
++04993         dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
++04994         volatile grstctl_t greset = {.d32 = 0 };
++04995         int count = 0;
++04996 
++04997         DWC_DEBUGPL((DBG_CIL | DBG_PCDV), "%s\n", __func__);
++04998         /*
++04999          *
++05000          */
++05001         greset.b.rxfflsh = 1;
++05002         DWC_WRITE_REG32(&global_regs->grstctl, greset.d32);
++05003 
++05004         do {
++05005                 greset.d32 = DWC_READ_REG32(&global_regs->grstctl);
++05006                 if (++count > 10000) {
++05007                         DWC_WARN("%s() HANG! GRSTCTL=%0x\n", __func__,
++05008                                  greset.d32);
++05009                         break;
++05010                 }
++05011                 dwc_udelay(1);
++05012         } while (greset.b.rxfflsh == 1);
++05013 
++05014         /* Wait for 3 PHY Clocks */
++05015         dwc_udelay(1);
++05016 }
++05017 
++05022 void dwc_otg_core_reset(dwc_otg_core_if_t * core_if)
++05023 {
++05024         dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
++05025         volatile grstctl_t greset = {.d32 = 0 };
++05026         int count = 0;
++05027 
++05028         DWC_DEBUGPL(DBG_CILV, "%s\n", __func__);
++05029         /* Wait for AHB master IDLE state. */
++05030         do {
++05031                 dwc_udelay(10);
++05032                 greset.d32 = DWC_READ_REG32(&global_regs->grstctl);
++05033                 if (++count > 100000) {
++05034                         DWC_WARN("%s() HANG! AHB Idle GRSTCTL=%0x\n", __func__,
++05035                                  greset.d32);
++05036                         return;
++05037                 }
++05038         }
++05039         while (greset.b.ahbidle == 0);
++05040 
++05041         /* Core Soft Reset */
++05042         count = 0;
++05043         greset.b.csftrst = 1;
++05044         DWC_WRITE_REG32(&global_regs->grstctl, greset.d32);
++05045         do {
++05046                 greset.d32 = DWC_READ_REG32(&global_regs->grstctl);
++05047                 if (++count > 10000) {
++05048                         DWC_WARN("%s() HANG! Soft Reset GRSTCTL=%0x\n",
++05049                                  __func__, greset.d32);
++05050                         break;
++05051                 }
++05052                 dwc_udelay(1);
++05053         }
++05054         while (greset.b.csftrst == 1);
++05055 
++05056         /* Wait for 3 PHY Clocks */
++05057         dwc_mdelay(100);
++05058 }
++05059 
++05060 uint8_t dwc_otg_is_device_mode(dwc_otg_core_if_t * _core_if)
++05061 {
++05062         return (dwc_otg_mode(_core_if) != DWC_HOST_MODE);
++05063 }
++05064 
++05065 uint8_t dwc_otg_is_host_mode(dwc_otg_core_if_t * _core_if)
++05066 {
++05067         return (dwc_otg_mode(_core_if) == DWC_HOST_MODE);
++05068 }
++05069 
++05078 void dwc_otg_cil_register_hcd_callbacks(dwc_otg_core_if_t * core_if,
++05079                                         dwc_otg_cil_callbacks_t * cb, void *p)
++05080 {
++05081         core_if->hcd_cb = cb;
++05082         cb->p = p;
++05083 }
++05084 
++05093 void dwc_otg_cil_register_pcd_callbacks(dwc_otg_core_if_t * core_if,
++05094                                         dwc_otg_cil_callbacks_t * cb, void *p)
++05095 {
++05096         core_if->pcd_cb = cb;
++05097         cb->p = p;
++05098 }
++05099 
++05100 #ifdef DWC_EN_ISOC
++05101 
++05109 void write_isoc_frame_data(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
++05110 {
++05111         dwc_otg_dev_in_ep_regs_t *ep_regs;
++05112         dtxfsts_data_t txstatus = {.d32 = 0 };
++05113         uint32_t len = 0;
++05114         uint32_t dwords;
++05115 
++05116         ep->xfer_len = ep->data_per_frame;
++05117         ep->xfer_count = 0;
++05118 
++05119         ep_regs = core_if->dev_if->in_ep_regs[ep->num];
++05120 
++05121         len = ep->xfer_len - ep->xfer_count;
++05122 
++05123         if (len > ep->maxpacket) {
++05124                 len = ep->maxpacket;
++05125         }
++05126 
++05127         dwords = (len + 3) / 4;
++05128 
++05129         /* While there is space in the queue and space in the FIFO and
++05130          * More data to tranfer, Write packets to the Tx FIFO */
++05131         txstatus.d32 =
++05132             DWC_READ_REG32(&core_if->dev_if->in_ep_regs[ep->num]->dtxfsts);
++05133         DWC_DEBUGPL(DBG_PCDV, "b4 dtxfsts[%d]=0x%08x\n", ep->num, txstatus.d32);
++05134 
++05135         while (txstatus.b.txfspcavail > dwords &&
++05136                ep->xfer_count < ep->xfer_len && ep->xfer_len != 0) {
++05137                 /* Write the FIFO */
++05138                 dwc_otg_ep_write_packet(core_if, ep, 0);
++05139 
++05140                 len = ep->xfer_len - ep->xfer_count;
++05141                 if (len > ep->maxpacket) {
++05142                         len = ep->maxpacket;
++05143                 }
++05144 
++05145                 dwords = (len + 3) / 4;
++05146                 txstatus.d32 =
++05147                     DWC_READ_REG32(&core_if->dev_if->
++05148                                    in_ep_regs[ep->num]->dtxfsts);
++05149                 DWC_DEBUGPL(DBG_PCDV, "dtxfsts[%d]=0x%08x\n", ep->num,
++05150                             txstatus.d32);
++05151         }
++05152 }
++05153 
++05161 void dwc_otg_iso_ep_start_frm_transfer(dwc_otg_core_if_t * core_if,
++05162                                        dwc_ep_t * ep)
++05163 {
++05164         deptsiz_data_t deptsiz = {.d32 = 0 };
++05165         depctl_data_t depctl = {.d32 = 0 };
++05166         dsts_data_t dsts = {.d32 = 0 };
++05167         volatile uint32_t *addr;
++05168 
++05169         if (ep->is_in) {
++05170                 addr = &core_if->dev_if->in_ep_regs[ep->num]->diepctl;
++05171         } else {
++05172                 addr = &core_if->dev_if->out_ep_regs[ep->num]->doepctl;
++05173         }
++05174 
++05175         ep->xfer_len = ep->data_per_frame;
++05176         ep->xfer_count = 0;
++05177         ep->xfer_buff = ep->cur_pkt_addr;
++05178         ep->dma_addr = ep->cur_pkt_dma_addr;
++05179 
++05180         if (ep->is_in) {
++05181                 /* Program the transfer size and packet count
++05182                  *      as follows: xfersize = N * maxpacket +
++05183                  *      short_packet pktcnt = N + (short_packet
++05184                  *      exist ? 1 : 0) 
++05185                  */
++05186                 deptsiz.b.xfersize = ep->xfer_len;
++05187                 deptsiz.b.pktcnt =
++05188                     (ep->xfer_len - 1 + ep->maxpacket) / ep->maxpacket;
++05189                 deptsiz.b.mc = deptsiz.b.pktcnt;
++05190                 DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[ep->num]->dieptsiz,
++05191                                 deptsiz.d32);
++05192 
++05193                 /* Write the DMA register */
++05194                 if (core_if->dma_enable) {
++05195                         DWC_WRITE_REG32(&
++05196                                         (core_if->dev_if->in_ep_regs[ep->num]->
++05197                                          diepdma), (uint32_t) ep->dma_addr);
++05198                 }
++05199         } else {
++05200                 deptsiz.b.pktcnt =
++05201                     (ep->xfer_len + (ep->maxpacket - 1)) / ep->maxpacket;
++05202                 deptsiz.b.xfersize = deptsiz.b.pktcnt * ep->maxpacket;
++05203 
++05204                 DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[ep->num]->
++05205                                 doeptsiz, deptsiz.d32);
++05206 
++05207                 if (core_if->dma_enable) {
++05208                         DWC_WRITE_REG32(&
++05209                                         (core_if->dev_if->out_ep_regs[ep->num]->
++05210                                          doepdma), (uint32_t) ep->dma_addr);
++05211                 }
++05212         }
++05213 
++05216         depctl.d32 = 0;
++05217         if (ep->bInterval == 1) {
++05218                 dsts.d32 =
++05219                     DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts);
++05220                 ep->next_frame = dsts.b.soffn + ep->bInterval;
++05221 
++05222                 if (ep->next_frame & 0x1) {
++05223                         depctl.b.setd1pid = 1;
++05224                 } else {
++05225                         depctl.b.setd0pid = 1;
++05226                 }
++05227         } else {
++05228                 ep->next_frame += ep->bInterval;
++05229 
++05230                 if (ep->next_frame & 0x1) {
++05231                         depctl.b.setd1pid = 1;
++05232                 } else {
++05233                         depctl.b.setd0pid = 1;
++05234                 }
++05235         }
++05236         depctl.b.epena = 1;
++05237         depctl.b.cnak = 1;
++05238 
++05239         DWC_MODIFY_REG32(addr, 0, depctl.d32);
++05240         depctl.d32 = DWC_READ_REG32(addr);
++05241 
++05242         if (ep->is_in && core_if->dma_enable == 0) {
++05243                 write_isoc_frame_data(core_if, ep);
++05244         }
++05245 
++05246 }
++05247 #endif /* DWC_EN_ISOC */
++05248 
++05249 static void dwc_otg_set_uninitialized(int32_t * p, int size)
++05250 {
++05251         int i;
++05252         for (i = 0; i < size; i++) {
++05253                 p[i] = -1;
++05254         }
++05255 }
++05256 
++05257 static int dwc_otg_param_initialized(int32_t val)
++05258 {
++05259         return val != -1;
++05260 }
++05261 
++05262 static int dwc_otg_setup_params(dwc_otg_core_if_t * core_if)
++05263 {
++05264         int i;
++05265         core_if->core_params = DWC_ALLOC(sizeof(*core_if->core_params));
++05266         if (!core_if->core_params) {
++05267                 return -DWC_E_NO_MEMORY;
++05268         }
++05269         dwc_otg_set_uninitialized((int32_t *) core_if->core_params,
++05270                                   sizeof(*core_if->core_params) /
++05271                                   sizeof(int32_t));
++05272         DWC_PRINTF("Setting default values for core params\n");
++05273         dwc_otg_set_param_otg_cap(core_if, dwc_param_otg_cap_default);
++05274         dwc_otg_set_param_dma_enable(core_if, dwc_param_dma_enable_default);
++05275         dwc_otg_set_param_dma_desc_enable(core_if,
++05276                                           dwc_param_dma_desc_enable_default);
++05277         dwc_otg_set_param_opt(core_if, dwc_param_opt_default);
++05278         dwc_otg_set_param_dma_burst_size(core_if,
++05279                                          dwc_param_dma_burst_size_default);
++05280         dwc_otg_set_param_host_support_fs_ls_low_power(core_if,
++05281                                                        dwc_param_host_support_fs_ls_low_power_default);
++05282         dwc_otg_set_param_enable_dynamic_fifo(core_if,
++05283                                               dwc_param_enable_dynamic_fifo_default);
++05284         dwc_otg_set_param_data_fifo_size(core_if,
++05285                                          dwc_param_data_fifo_size_default);
++05286         dwc_otg_set_param_dev_rx_fifo_size(core_if,
++05287                                            dwc_param_dev_rx_fifo_size_default);
++05288         dwc_otg_set_param_dev_nperio_tx_fifo_size(core_if,
++05289                                                   dwc_param_dev_nperio_tx_fifo_size_default);
++05290         dwc_otg_set_param_host_rx_fifo_size(core_if,
++05291                                             dwc_param_host_rx_fifo_size_default);
++05292         dwc_otg_set_param_host_nperio_tx_fifo_size(core_if,
++05293                                                    dwc_param_host_nperio_tx_fifo_size_default);
++05294         dwc_otg_set_param_host_perio_tx_fifo_size(core_if,
++05295                                                   dwc_param_host_perio_tx_fifo_size_default);
++05296         dwc_otg_set_param_max_transfer_size(core_if,
++05297                                             dwc_param_max_transfer_size_default);
++05298         dwc_otg_set_param_max_packet_count(core_if,
++05299                                            dwc_param_max_packet_count_default);
++05300         dwc_otg_set_param_host_channels(core_if,
++05301                                         dwc_param_host_channels_default);
++05302         dwc_otg_set_param_dev_endpoints(core_if,
++05303                                         dwc_param_dev_endpoints_default);
++05304         dwc_otg_set_param_phy_type(core_if, dwc_param_phy_type_default);
++05305         dwc_otg_set_param_speed(core_if, dwc_param_speed_default);
++05306         dwc_otg_set_param_host_ls_low_power_phy_clk(core_if,
++05307                                                     dwc_param_host_ls_low_power_phy_clk_default);
++05308         dwc_otg_set_param_phy_ulpi_ddr(core_if, dwc_param_phy_ulpi_ddr_default);
++05309         dwc_otg_set_param_phy_ulpi_ext_vbus(core_if,
++05310                                             dwc_param_phy_ulpi_ext_vbus_default);
++05311         dwc_otg_set_param_phy_utmi_width(core_if,
++05312                                          dwc_param_phy_utmi_width_default);
++05313         dwc_otg_set_param_ts_dline(core_if, dwc_param_ts_dline_default);
++05314         dwc_otg_set_param_i2c_enable(core_if, dwc_param_i2c_enable_default);
++05315         dwc_otg_set_param_ulpi_fs_ls(core_if, dwc_param_ulpi_fs_ls_default);
++05316         dwc_otg_set_param_en_multiple_tx_fifo(core_if,
++05317                                               dwc_param_en_multiple_tx_fifo_default);
++05318         for (i = 0; i < 15; i++) {
++05319                 dwc_otg_set_param_dev_perio_tx_fifo_size(core_if,
++05320                                                          dwc_param_dev_perio_tx_fifo_size_default,
++05321                                                          i);
++05322         }
++05323 
++05324         for (i = 0; i < 15; i++) {
++05325                 dwc_otg_set_param_dev_tx_fifo_size(core_if,
++05326                                                    dwc_param_dev_tx_fifo_size_default,
++05327                                                    i);
++05328         }
++05329         dwc_otg_set_param_thr_ctl(core_if, dwc_param_thr_ctl_default);
++05330         dwc_otg_set_param_mpi_enable(core_if, dwc_param_mpi_enable_default);
++05331         dwc_otg_set_param_pti_enable(core_if, dwc_param_pti_enable_default);
++05332         dwc_otg_set_param_lpm_enable(core_if, dwc_param_lpm_enable_default);
++05333         dwc_otg_set_param_ic_usb_cap(core_if, dwc_param_ic_usb_cap_default);
++05334         dwc_otg_set_param_tx_thr_length(core_if,
++05335                                         dwc_param_tx_thr_length_default);
++05336         dwc_otg_set_param_rx_thr_length(core_if,
++05337                                         dwc_param_rx_thr_length_default);
++05338         dwc_otg_set_param_ahb_thr_ratio(core_if,
++05339                                         dwc_param_ahb_thr_ratio_default);
++05340         dwc_otg_set_param_power_down(core_if, dwc_param_power_down_default);
++05341         dwc_otg_set_param_reload_ctl(core_if, dwc_param_reload_ctl_default);
++05342         dwc_otg_set_param_dev_out_nak(core_if, dwc_param_dev_out_nak_default);
++05343         dwc_otg_set_param_cont_on_bna(core_if, dwc_param_cont_on_bna_default);
++05344         dwc_otg_set_param_ahb_single(core_if, dwc_param_ahb_single_default);
++05345         dwc_otg_set_param_otg_ver(core_if, dwc_param_otg_ver_default);
++05346         dwc_otg_set_param_adp_enable(core_if, dwc_param_adp_enable_default);
++05347         return 0;
++05348 }
++05349 
++05350 uint8_t dwc_otg_is_dma_enable(dwc_otg_core_if_t * core_if)
++05351 {
++05352         return core_if->dma_enable;
++05353 }
++05354 
++05355 /* Checks if the parameter is outside of its valid range of values */
++05356 #define DWC_OTG_PARAM_TEST(_param_, _low_, _high_) \
++05357                 (((_param_) < (_low_)) || \
++05358                 ((_param_) > (_high_)))
++05359 
++05360 /* Parameter access functions */
++05361 int dwc_otg_set_param_otg_cap(dwc_otg_core_if_t * core_if, int32_t val)
++05362 {
++05363         int valid;
++05364         int retval = 0;
++05365         if (DWC_OTG_PARAM_TEST(val, 0, 2)) {
++05366                 DWC_WARN("Wrong value for otg_cap parameter\n");
++05367                 DWC_WARN("otg_cap parameter must be 0,1 or 2\n");
++05368                 retval = -DWC_E_INVALID;
++05369                 goto out;
++05370         }
++05371 
++05372         valid = 1;
++05373         switch (val) {
++05374         case DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE:
++05375                 if (core_if->hwcfg2.b.op_mode !=
++05376                     DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG)
++05377                         valid = 0;
++05378                 break;
++05379         case DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE:
++05380                 if ((core_if->hwcfg2.b.op_mode !=
++05381                      DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG)
++05382                     && (core_if->hwcfg2.b.op_mode !=
++05383                         DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG)
++05384                     && (core_if->hwcfg2.b.op_mode !=
++05385                         DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE)
++05386                     && (core_if->hwcfg2.b.op_mode !=
++05387                         DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST)) {
++05388                         valid = 0;
++05389                 }
++05390                 break;
++05391         case DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE:
++05392                 /* always valid */
++05393                 break;
++05394         }
++05395         if (!valid) {
++05396                 if (dwc_otg_param_initialized(core_if->core_params->otg_cap)) {
++05397                         DWC_ERROR
++05398                             ("%d invalid for otg_cap paremter. Check HW configuration.\n",
++05399                              val);
++05400                 }
++05401                 val =
++05402                     (((core_if->hwcfg2.b.op_mode ==
++05403                        DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG)
++05404                       || (core_if->hwcfg2.b.op_mode ==
++05405                           DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG)
++05406                       || (core_if->hwcfg2.b.op_mode ==
++05407                           DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE)
++05408                       || (core_if->hwcfg2.b.op_mode ==
++05409                           DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST)) ?
++05410                      DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE :
++05411                      DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE);
++05412                 retval = -DWC_E_INVALID;
++05413         }
++05414 
++05415         core_if->core_params->otg_cap = val;
++05416 out:
++05417         return retval;
++05418 }
++05419 
++05420 int32_t dwc_otg_get_param_otg_cap(dwc_otg_core_if_t * core_if)
++05421 {
++05422         return core_if->core_params->otg_cap;
++05423 }
++05424 
++05425 int dwc_otg_set_param_opt(dwc_otg_core_if_t * core_if, int32_t val)
++05426 {
++05427         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
++05428                 DWC_WARN("Wrong value for opt parameter\n");
++05429                 return -DWC_E_INVALID;
++05430         }
++05431         core_if->core_params->opt = val;
++05432         return 0;
++05433 }
++05434 
++05435 int32_t dwc_otg_get_param_opt(dwc_otg_core_if_t * core_if)
++05436 {
++05437         return core_if->core_params->opt;
++05438 }
++05439 
++05440 int dwc_otg_set_param_dma_enable(dwc_otg_core_if_t * core_if, int32_t val)
++05441 {
++05442         int retval = 0;
++05443         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
++05444                 DWC_WARN("Wrong value for dma enable\n");
++05445                 return -DWC_E_INVALID;
++05446         }
++05447 
++05448         if ((val == 1) && (core_if->hwcfg2.b.architecture == 0)) {
++05449                 if (dwc_otg_param_initialized(core_if->core_params->dma_enable)) {
++05450                         DWC_ERROR
++05451                             ("%d invalid for dma_enable paremter. Check HW configuration.\n",
++05452                              val);
++05453                 }
++05454                 val = 0;
++05455                 retval = -DWC_E_INVALID;
++05456         }
++05457 
++05458         core_if->core_params->dma_enable = val;
++05459         if (val == 0) {
++05460                 dwc_otg_set_param_dma_desc_enable(core_if, 0);
++05461         }
++05462         return retval;
++05463 }
++05464 
++05465 int32_t dwc_otg_get_param_dma_enable(dwc_otg_core_if_t * core_if)
++05466 {
++05467         return core_if->core_params->dma_enable;
++05468 }
++05469 
++05470 int dwc_otg_set_param_dma_desc_enable(dwc_otg_core_if_t * core_if, int32_t val)
++05471 {
++05472         int retval = 0;
++05473         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
++05474                 DWC_WARN("Wrong value for dma_enable\n");
++05475                 DWC_WARN("dma_desc_enable must be 0 or 1\n");
++05476                 return -DWC_E_INVALID;
++05477         }
++05478 
++05479         if ((val == 1)
++05480             && ((dwc_otg_get_param_dma_enable(core_if) == 0)
++05481                 || (core_if->hwcfg4.b.desc_dma == 0))) {
++05482                 if (dwc_otg_param_initialized
++05483                     (core_if->core_params->dma_desc_enable)) {
++05484                         DWC_ERROR
++05485                             ("%d invalid for dma_desc_enable paremter. Check HW configuration.\n",
++05486                              val);
++05487                 }
++05488                 val = 0;
++05489                 retval = -DWC_E_INVALID;
++05490         }
++05491         core_if->core_params->dma_desc_enable = val;
++05492         return retval;
++05493 }
++05494 
++05495 int32_t dwc_otg_get_param_dma_desc_enable(dwc_otg_core_if_t * core_if)
++05496 {
++05497         return core_if->core_params->dma_desc_enable;
++05498 }
++05499 
++05500 int dwc_otg_set_param_host_support_fs_ls_low_power(dwc_otg_core_if_t * core_if,
++05501                                                    int32_t val)
++05502 {
++05503         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
++05504                 DWC_WARN("Wrong value for host_support_fs_low_power\n");
++05505                 DWC_WARN("host_support_fs_low_power must be 0 or 1\n");
++05506                 return -DWC_E_INVALID;
++05507         }
++05508         core_if->core_params->host_support_fs_ls_low_power = val;
++05509         return 0;
++05510 }
++05511 
++05512 int32_t dwc_otg_get_param_host_support_fs_ls_low_power(dwc_otg_core_if_t *
++05513                                                        core_if)
++05514 {
++05515         return core_if->core_params->host_support_fs_ls_low_power;
++05516 }
++05517 
++05518 int dwc_otg_set_param_enable_dynamic_fifo(dwc_otg_core_if_t * core_if,
++05519                                           int32_t val)
++05520 {
++05521         int retval = 0;
++05522         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
++05523                 DWC_WARN("Wrong value for enable_dynamic_fifo\n");
++05524                 DWC_WARN("enable_dynamic_fifo must be 0 or 1\n");
++05525                 return -DWC_E_INVALID;
++05526         }
++05527 
++05528         if ((val == 1) && (core_if->hwcfg2.b.dynamic_fifo == 0)) {
++05529                 if (dwc_otg_param_initialized
++05530                     (core_if->core_params->enable_dynamic_fifo)) {
++05531                         DWC_ERROR
++05532                             ("%d invalid for enable_dynamic_fifo paremter. Check HW configuration.\n",
++05533                              val);
++05534                 }
++05535                 val = 0;
++05536                 retval = -DWC_E_INVALID;
++05537         }
++05538         core_if->core_params->enable_dynamic_fifo = val;
++05539         return retval;
++05540 }
++05541 
++05542 int32_t dwc_otg_get_param_enable_dynamic_fifo(dwc_otg_core_if_t * core_if)
++05543 {
++05544         return core_if->core_params->enable_dynamic_fifo;
++05545 }
++05546 
++05547 int dwc_otg_set_param_data_fifo_size(dwc_otg_core_if_t * core_if, int32_t val)
++05548 {
++05549         int retval = 0;
++05550         if (DWC_OTG_PARAM_TEST(val, 32, 32768)) {
++05551                 DWC_WARN("Wrong value for data_fifo_size\n");
++05552                 DWC_WARN("data_fifo_size must be 32-32768\n");
++05553                 return -DWC_E_INVALID;
++05554         }
++05555 
++05556         if (val > core_if->hwcfg3.b.dfifo_depth) {
++05557                 if (dwc_otg_param_initialized
++05558                     (core_if->core_params->data_fifo_size)) {
++05559                         DWC_ERROR
++05560                             ("%d invalid for data_fifo_size parameter. Check HW configuration.\n",
++05561                              val);
++05562                 }
++05563                 val = core_if->hwcfg3.b.dfifo_depth;
++05564                 retval = -DWC_E_INVALID;
++05565         }
++05566 
++05567         core_if->core_params->data_fifo_size = val;
++05568         return retval;
++05569 }
++05570 
++05571 int32_t dwc_otg_get_param_data_fifo_size(dwc_otg_core_if_t * core_if)
++05572 {
++05573         return core_if->core_params->data_fifo_size;
++05574 }
++05575 
++05576 int dwc_otg_set_param_dev_rx_fifo_size(dwc_otg_core_if_t * core_if, int32_t val)
++05577 {
++05578         int retval = 0;
++05579         if (DWC_OTG_PARAM_TEST(val, 16, 32768)) {
++05580                 DWC_WARN("Wrong value for dev_rx_fifo_size\n");
++05581                 DWC_WARN("dev_rx_fifo_size must be 16-32768\n");
++05582                 return -DWC_E_INVALID;
++05583         }
++05584 
++05585         if (val > DWC_READ_REG32(&core_if->core_global_regs->grxfsiz)) {
++05586                 if (dwc_otg_param_initialized(core_if->core_params->dev_rx_fifo_size)) {
++05587                 DWC_WARN("%d invalid for dev_rx_fifo_size parameter\n", val);
++05588                 }
++05589                 val = DWC_READ_REG32(&core_if->core_global_regs->grxfsiz);
++05590                 retval = -DWC_E_INVALID;
++05591         }
++05592 
++05593         core_if->core_params->dev_rx_fifo_size = val;
++05594         return retval;
++05595 }
++05596 
++05597 int32_t dwc_otg_get_param_dev_rx_fifo_size(dwc_otg_core_if_t * core_if)
++05598 {
++05599         return core_if->core_params->dev_rx_fifo_size;
++05600 }
++05601 
++05602 int dwc_otg_set_param_dev_nperio_tx_fifo_size(dwc_otg_core_if_t * core_if,
++05603                                               int32_t val)
++05604 {
++05605         int retval = 0;
++05606 
++05607         if (DWC_OTG_PARAM_TEST(val, 16, 32768)) {
++05608                 DWC_WARN("Wrong value for dev_nperio_tx_fifo\n");
++05609                 DWC_WARN("dev_nperio_tx_fifo must be 16-32768\n");
++05610                 return -DWC_E_INVALID;
++05611         }
++05612 
++05613         if (val > (DWC_READ_REG32(&core_if->core_global_regs->gnptxfsiz) >> 16)) {
++05614                 if (dwc_otg_param_initialized
++05615                     (core_if->core_params->dev_nperio_tx_fifo_size)) {
++05616                         DWC_ERROR
++05617                             ("%d invalid for dev_nperio_tx_fifo_size. Check HW configuration.\n",
++05618                              val);
++05619                 }
++05620                 val =
++05621                     (DWC_READ_REG32(&core_if->core_global_regs->gnptxfsiz) >>
++05622                      16);
++05623                 retval = -DWC_E_INVALID;
++05624         }
++05625 
++05626         core_if->core_params->dev_nperio_tx_fifo_size = val;
++05627         return retval;
++05628 }
++05629 
++05630 int32_t dwc_otg_get_param_dev_nperio_tx_fifo_size(dwc_otg_core_if_t * core_if)
++05631 {
++05632         return core_if->core_params->dev_nperio_tx_fifo_size;
++05633 }
++05634 
++05635 int dwc_otg_set_param_host_rx_fifo_size(dwc_otg_core_if_t * core_if,
++05636                                         int32_t val)
++05637 {
++05638         int retval = 0;
++05639 
++05640         if (DWC_OTG_PARAM_TEST(val, 16, 32768)) {
++05641                 DWC_WARN("Wrong value for host_rx_fifo_size\n");
++05642                 DWC_WARN("host_rx_fifo_size must be 16-32768\n");
++05643                 return -DWC_E_INVALID;
++05644         }
++05645 
++05646         if (val > DWC_READ_REG32(&core_if->core_global_regs->grxfsiz)) {
++05647                 if (dwc_otg_param_initialized
++05648                     (core_if->core_params->host_rx_fifo_size)) {
++05649                         DWC_ERROR
++05650                             ("%d invalid for host_rx_fifo_size. Check HW configuration.\n",
++05651                              val);
++05652                 }
++05653                 val = DWC_READ_REG32(&core_if->core_global_regs->grxfsiz);
++05654                 retval = -DWC_E_INVALID;
++05655         }
++05656 
++05657         core_if->core_params->host_rx_fifo_size = val;
++05658         return retval;
++05659 
++05660 }
++05661 
++05662 int32_t dwc_otg_get_param_host_rx_fifo_size(dwc_otg_core_if_t * core_if)
++05663 {
++05664         return core_if->core_params->host_rx_fifo_size;
++05665 }
++05666 
++05667 int dwc_otg_set_param_host_nperio_tx_fifo_size(dwc_otg_core_if_t * core_if,
++05668                                                int32_t val)
++05669 {
++05670         int retval = 0;
++05671 
++05672         if (DWC_OTG_PARAM_TEST(val, 16, 32768)) {
++05673                 DWC_WARN("Wrong value for host_nperio_tx_fifo_size\n");
++05674                 DWC_WARN("host_nperio_tx_fifo_size must be 16-32768\n");
++05675                 return -DWC_E_INVALID;
++05676         }
++05677 
++05678         if (val > (DWC_READ_REG32(&core_if->core_global_regs->gnptxfsiz) >> 16)) {
++05679                 if (dwc_otg_param_initialized
++05680                     (core_if->core_params->host_nperio_tx_fifo_size)) {
++05681                         DWC_ERROR
++05682                             ("%d invalid for host_nperio_tx_fifo_size. Check HW configuration.\n",
++05683                              val);
++05684                 }
++05685                 val =
++05686                     (DWC_READ_REG32(&core_if->core_global_regs->gnptxfsiz) >>
++05687                      16);
++05688                 retval = -DWC_E_INVALID;
++05689         }
++05690 
++05691         core_if->core_params->host_nperio_tx_fifo_size = val;
++05692         return retval;
++05693 }
++05694 
++05695 int32_t dwc_otg_get_param_host_nperio_tx_fifo_size(dwc_otg_core_if_t * core_if)
++05696 {
++05697         return core_if->core_params->host_nperio_tx_fifo_size;
++05698 }
++05699 
++05700 int dwc_otg_set_param_host_perio_tx_fifo_size(dwc_otg_core_if_t * core_if,
++05701                                               int32_t val)
++05702 {
++05703         int retval = 0;
++05704         if (DWC_OTG_PARAM_TEST(val, 16, 32768)) {
++05705                 DWC_WARN("Wrong value for host_perio_tx_fifo_size\n");
++05706                 DWC_WARN("host_perio_tx_fifo_size must be 16-32768\n");
++05707                 return -DWC_E_INVALID;
++05708         }
++05709 
++05710         if (val >
++05711                 ((core_if->hptxfsiz.d32)>> 16)) {
++05712                 if (dwc_otg_param_initialized
++05713                     (core_if->core_params->host_perio_tx_fifo_size)) {
++05714                         DWC_ERROR
++05715                             ("%d invalid for host_perio_tx_fifo_size. Check HW configuration.\n",
++05716                              val);
++05717                 }
++05718                 val = (core_if->hptxfsiz.d32) >> 16;
++05719                 retval = -DWC_E_INVALID;
++05720         }
++05721 
++05722         core_if->core_params->host_perio_tx_fifo_size = val;
++05723         return retval;
++05724 }
++05725 
++05726 int32_t dwc_otg_get_param_host_perio_tx_fifo_size(dwc_otg_core_if_t * core_if)
++05727 {
++05728         return core_if->core_params->host_perio_tx_fifo_size;
++05729 }
++05730 
++05731 int dwc_otg_set_param_max_transfer_size(dwc_otg_core_if_t * core_if,
++05732                                         int32_t val)
++05733 {
++05734         int retval = 0;
++05735 
++05736         if (DWC_OTG_PARAM_TEST(val, 2047, 524288)) {
++05737                 DWC_WARN("Wrong value for max_transfer_size\n");
++05738                 DWC_WARN("max_transfer_size must be 2047-524288\n");
++05739                 return -DWC_E_INVALID;
++05740         }
++05741 
++05742         if (val >= (1 << (core_if->hwcfg3.b.xfer_size_cntr_width + 11))) {
++05743                 if (dwc_otg_param_initialized
++05744                     (core_if->core_params->max_transfer_size)) {
++05745                         DWC_ERROR
++05746                             ("%d invalid for max_transfer_size. Check HW configuration.\n",
++05747                              val);
++05748                 }
++05749                 val =
++05750                     ((1 << (core_if->hwcfg3.b.packet_size_cntr_width + 11)) -
++05751                      1);
++05752                 retval = -DWC_E_INVALID;
++05753         }
++05754 
++05755         core_if->core_params->max_transfer_size = val;
++05756         return retval;
++05757 }
++05758 
++05759 int32_t dwc_otg_get_param_max_transfer_size(dwc_otg_core_if_t * core_if)
++05760 {
++05761         return core_if->core_params->max_transfer_size;
++05762 }
++05763 
++05764 int dwc_otg_set_param_max_packet_count(dwc_otg_core_if_t * core_if, int32_t val)
++05765 {
++05766         int retval = 0;
++05767 
++05768         if (DWC_OTG_PARAM_TEST(val, 15, 511)) {
++05769                 DWC_WARN("Wrong value for max_packet_count\n");
++05770                 DWC_WARN("max_packet_count must be 15-511\n");
++05771                 return -DWC_E_INVALID;
++05772         }
++05773 
++05774         if (val > (1 << (core_if->hwcfg3.b.packet_size_cntr_width + 4))) {
++05775                 if (dwc_otg_param_initialized
++05776                     (core_if->core_params->max_packet_count)) {
++05777                         DWC_ERROR
++05778                             ("%d invalid for max_packet_count. Check HW configuration.\n",
++05779                              val);
++05780                 }
++05781                 val =
++05782                     ((1 << (core_if->hwcfg3.b.packet_size_cntr_width + 4)) - 1);
++05783                 retval = -DWC_E_INVALID;
++05784         }
++05785 
++05786         core_if->core_params->max_packet_count = val;
++05787         return retval;
++05788 }
++05789 
++05790 int32_t dwc_otg_get_param_max_packet_count(dwc_otg_core_if_t * core_if)
++05791 {
++05792         return core_if->core_params->max_packet_count;
++05793 }
++05794 
++05795 int dwc_otg_set_param_host_channels(dwc_otg_core_if_t * core_if, int32_t val)
++05796 {
++05797         int retval = 0;
++05798 
++05799         if (DWC_OTG_PARAM_TEST(val, 1, 16)) {
++05800                 DWC_WARN("Wrong value for host_channels\n");
++05801                 DWC_WARN("host_channels must be 1-16\n");
++05802                 return -DWC_E_INVALID;
++05803         }
++05804 
++05805         if (val > (core_if->hwcfg2.b.num_host_chan + 1)) {
++05806                 if (dwc_otg_param_initialized
++05807                     (core_if->core_params->host_channels)) {
++05808                         DWC_ERROR
++05809                             ("%d invalid for host_channels. Check HW configurations.\n",
++05810                              val);
++05811                 }
++05812                 val = (core_if->hwcfg2.b.num_host_chan + 1);
++05813                 retval = -DWC_E_INVALID;
++05814         }
++05815 
++05816         core_if->core_params->host_channels = val;
++05817         return retval;
++05818 }
++05819 
++05820 int32_t dwc_otg_get_param_host_channels(dwc_otg_core_if_t * core_if)
++05821 {
++05822         return core_if->core_params->host_channels;
++05823 }
++05824 
++05825 int dwc_otg_set_param_dev_endpoints(dwc_otg_core_if_t * core_if, int32_t val)
++05826 {
++05827         int retval = 0;
++05828 
++05829         if (DWC_OTG_PARAM_TEST(val, 1, 15)) {
++05830                 DWC_WARN("Wrong value for dev_endpoints\n");
++05831                 DWC_WARN("dev_endpoints must be 1-15\n");
++05832                 return -DWC_E_INVALID;
++05833         }
++05834 
++05835         if (val > (core_if->hwcfg2.b.num_dev_ep)) {
++05836                 if (dwc_otg_param_initialized
++05837                     (core_if->core_params->dev_endpoints)) {
++05838                         DWC_ERROR
++05839                             ("%d invalid for dev_endpoints. Check HW configurations.\n",
++05840                              val);
++05841                 }
++05842                 val = core_if->hwcfg2.b.num_dev_ep;
++05843                 retval = -DWC_E_INVALID;
++05844         }
++05845 
++05846         core_if->core_params->dev_endpoints = val;
++05847         return retval;
++05848 }
++05849 
++05850 int32_t dwc_otg_get_param_dev_endpoints(dwc_otg_core_if_t * core_if)
++05851 {
++05852         return core_if->core_params->dev_endpoints;
++05853 }
++05854 
++05855 int dwc_otg_set_param_phy_type(dwc_otg_core_if_t * core_if, int32_t val)
++05856 {
++05857         int retval = 0;
++05858         int valid = 0;
++05859 
++05860         if (DWC_OTG_PARAM_TEST(val, 0, 2)) {
++05861                 DWC_WARN("Wrong value for phy_type\n");
++05862                 DWC_WARN("phy_type must be 0,1 or 2\n");
++05863                 return -DWC_E_INVALID;
++05864         }
++05865 #ifndef NO_FS_PHY_HW_CHECKS
++05866         if ((val == DWC_PHY_TYPE_PARAM_UTMI) &&
++05867             ((core_if->hwcfg2.b.hs_phy_type == 1) ||
++05868              (core_if->hwcfg2.b.hs_phy_type == 3))) {
++05869                 valid = 1;
++05870         } else if ((val == DWC_PHY_TYPE_PARAM_ULPI) &&
++05871                    ((core_if->hwcfg2.b.hs_phy_type == 2) ||
++05872                     (core_if->hwcfg2.b.hs_phy_type == 3))) {
++05873                 valid = 1;
++05874         } else if ((val == DWC_PHY_TYPE_PARAM_FS) &&
++05875                    (core_if->hwcfg2.b.fs_phy_type == 1)) {
++05876                 valid = 1;
++05877         }
++05878         if (!valid) {
++05879                 if (dwc_otg_param_initialized(core_if->core_params->phy_type)) {
++05880                         DWC_ERROR
++05881                             ("%d invalid for phy_type. Check HW configurations.\n",
++05882                              val);
++05883                 }
++05884                 if (core_if->hwcfg2.b.hs_phy_type) {
++05885                         if ((core_if->hwcfg2.b.hs_phy_type == 3) ||
++05886                             (core_if->hwcfg2.b.hs_phy_type == 1)) {
++05887                                 val = DWC_PHY_TYPE_PARAM_UTMI;
++05888                         } else {
++05889                                 val = DWC_PHY_TYPE_PARAM_ULPI;
++05890                         }
++05891                 }
++05892                 retval = -DWC_E_INVALID;
++05893         }
++05894 #endif
++05895         core_if->core_params->phy_type = val;
++05896         return retval;
++05897 }
++05898 
++05899 int32_t dwc_otg_get_param_phy_type(dwc_otg_core_if_t * core_if)
++05900 {
++05901         return core_if->core_params->phy_type;
++05902 }
++05903 
++05904 int dwc_otg_set_param_speed(dwc_otg_core_if_t * core_if, int32_t val)
++05905 {
++05906         int retval = 0;
++05907         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
++05908                 DWC_WARN("Wrong value for speed parameter\n");
++05909                 DWC_WARN("max_speed parameter must be 0 or 1\n");
++05910                 return -DWC_E_INVALID;
++05911         }
++05912         if ((val == 0)
++05913             && dwc_otg_get_param_phy_type(core_if) == DWC_PHY_TYPE_PARAM_FS) {
++05914                 if (dwc_otg_param_initialized(core_if->core_params->speed)) {
++05915                         DWC_ERROR
++05916                             ("%d invalid for speed paremter. Check HW configuration.\n",
++05917                              val);
++05918                 }
++05919                 val =
++05920                     (dwc_otg_get_param_phy_type(core_if) ==
++05921                      DWC_PHY_TYPE_PARAM_FS ? 1 : 0);
++05922                 retval = -DWC_E_INVALID;
++05923         }
++05924         core_if->core_params->speed = val;
++05925         return retval;
++05926 }
++05927 
++05928 int32_t dwc_otg_get_param_speed(dwc_otg_core_if_t * core_if)
++05929 {
++05930         return core_if->core_params->speed;
++05931 }
++05932 
++05933 int dwc_otg_set_param_host_ls_low_power_phy_clk(dwc_otg_core_if_t * core_if,
++05934                                                 int32_t val)
++05935 {
++05936         int retval = 0;
++05937 
++05938         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
++05939                 DWC_WARN
++05940                     ("Wrong value for host_ls_low_power_phy_clk parameter\n");
++05941                 DWC_WARN("host_ls_low_power_phy_clk must be 0 or 1\n");
++05942                 return -DWC_E_INVALID;
++05943         }
++05944 
++05945         if ((val == DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ)
++05946             && (dwc_otg_get_param_phy_type(core_if) == DWC_PHY_TYPE_PARAM_FS)) {
++05947                 if (dwc_otg_param_initialized
++05948                     (core_if->core_params->host_ls_low_power_phy_clk)) {
++05949                         DWC_ERROR
++05950                             ("%d invalid for host_ls_low_power_phy_clk. Check HW configuration.\n",
++05951                              val);
++05952                 }
++05953                 val =
++05954                     (dwc_otg_get_param_phy_type(core_if) ==
++05955                      DWC_PHY_TYPE_PARAM_FS) ?
++05956                     DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ :
++05957                     DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ;
++05958                 retval = -DWC_E_INVALID;
++05959         }
++05960 
++05961         core_if->core_params->host_ls_low_power_phy_clk = val;
++05962         return retval;
++05963 }
++05964 
++05965 int32_t dwc_otg_get_param_host_ls_low_power_phy_clk(dwc_otg_core_if_t * core_if)
++05966 {
++05967         return core_if->core_params->host_ls_low_power_phy_clk;
++05968 }
++05969 
++05970 int dwc_otg_set_param_phy_ulpi_ddr(dwc_otg_core_if_t * core_if, int32_t val)
++05971 {
++05972         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
++05973                 DWC_WARN("Wrong value for phy_ulpi_ddr\n");
++05974                 DWC_WARN("phy_upli_ddr must be 0 or 1\n");
++05975                 return -DWC_E_INVALID;
++05976         }
++05977 
++05978         core_if->core_params->phy_ulpi_ddr = val;
++05979         return 0;
++05980 }
++05981 
++05982 int32_t dwc_otg_get_param_phy_ulpi_ddr(dwc_otg_core_if_t * core_if)
++05983 {
++05984         return core_if->core_params->phy_ulpi_ddr;
++05985 }
++05986 
++05987 int dwc_otg_set_param_phy_ulpi_ext_vbus(dwc_otg_core_if_t * core_if,
++05988                                         int32_t val)
++05989 {
++05990         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
++05991                 DWC_WARN("Wrong valaue for phy_ulpi_ext_vbus\n");
++05992                 DWC_WARN("phy_ulpi_ext_vbus must be 0 or 1\n");
++05993                 return -DWC_E_INVALID;
++05994         }
++05995 
++05996         core_if->core_params->phy_ulpi_ext_vbus = val;
++05997         return 0;
++05998 }
++05999 
++06000 int32_t dwc_otg_get_param_phy_ulpi_ext_vbus(dwc_otg_core_if_t * core_if)
++06001 {
++06002         return core_if->core_params->phy_ulpi_ext_vbus;
++06003 }
++06004 
++06005 int dwc_otg_set_param_phy_utmi_width(dwc_otg_core_if_t * core_if, int32_t val)
++06006 {
++06007         if (DWC_OTG_PARAM_TEST(val, 8, 8) && DWC_OTG_PARAM_TEST(val, 16, 16)) {
++06008                 DWC_WARN("Wrong valaue for phy_utmi_width\n");
++06009                 DWC_WARN("phy_utmi_width must be 8 or 16\n");
++06010                 return -DWC_E_INVALID;
++06011         }
++06012 
++06013         core_if->core_params->phy_utmi_width = val;
++06014         return 0;
++06015 }
++06016 
++06017 int32_t dwc_otg_get_param_phy_utmi_width(dwc_otg_core_if_t * core_if)
++06018 {
++06019         return core_if->core_params->phy_utmi_width;
++06020 }
++06021 
++06022 int dwc_otg_set_param_ulpi_fs_ls(dwc_otg_core_if_t * core_if, int32_t val)
++06023 {
++06024         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
++06025                 DWC_WARN("Wrong valaue for ulpi_fs_ls\n");
++06026                 DWC_WARN("ulpi_fs_ls must be 0 or 1\n");
++06027                 return -DWC_E_INVALID;
++06028         }
++06029 
++06030         core_if->core_params->ulpi_fs_ls = val;
++06031         return 0;
++06032 }
++06033 
++06034 int32_t dwc_otg_get_param_ulpi_fs_ls(dwc_otg_core_if_t * core_if)
++06035 {
++06036         return core_if->core_params->ulpi_fs_ls;
++06037 }
++06038 
++06039 int dwc_otg_set_param_ts_dline(dwc_otg_core_if_t * core_if, int32_t val)
++06040 {
++06041         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
++06042                 DWC_WARN("Wrong valaue for ts_dline\n");
++06043                 DWC_WARN("ts_dline must be 0 or 1\n");
++06044                 return -DWC_E_INVALID;
++06045         }
++06046 
++06047         core_if->core_params->ts_dline = val;
++06048         return 0;
++06049 }
++06050 
++06051 int32_t dwc_otg_get_param_ts_dline(dwc_otg_core_if_t * core_if)
++06052 {
++06053         return core_if->core_params->ts_dline;
++06054 }
++06055 
++06056 int dwc_otg_set_param_i2c_enable(dwc_otg_core_if_t * core_if, int32_t val)
++06057 {
++06058         int retval = 0;
++06059         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
++06060                 DWC_WARN("Wrong valaue for i2c_enable\n");
++06061                 DWC_WARN("i2c_enable must be 0 or 1\n");
++06062                 return -DWC_E_INVALID;
++06063         }
++06064 #ifndef NO_FS_PHY_HW_CHECK
++06065         if (val == 1 && core_if->hwcfg3.b.i2c == 0) {
++06066                 if (dwc_otg_param_initialized(core_if->core_params->i2c_enable)) {
++06067                         DWC_ERROR
++06068                             ("%d invalid for i2c_enable. Check HW configuration.\n",
++06069                              val);
++06070                 }
++06071                 val = 0;
++06072                 retval = -DWC_E_INVALID;
++06073         }
++06074 #endif
++06075 
++06076         core_if->core_params->i2c_enable = val;
++06077         return retval;
++06078 }
++06079 
++06080 int32_t dwc_otg_get_param_i2c_enable(dwc_otg_core_if_t * core_if)
++06081 {
++06082         return core_if->core_params->i2c_enable;
++06083 }
++06084 
++06085 int dwc_otg_set_param_dev_perio_tx_fifo_size(dwc_otg_core_if_t * core_if,
++06086                                              int32_t val, int fifo_num)
++06087 {
++06088         int retval = 0;
++06089 
++06090         if (DWC_OTG_PARAM_TEST(val, 4, 768)) {
++06091                 DWC_WARN("Wrong value for dev_perio_tx_fifo_size\n");
++06092                 DWC_WARN("dev_perio_tx_fifo_size must be 4-768\n");
++06093                 return -DWC_E_INVALID;
++06094         }
++06095 
++06096         if (val >
++06097             (DWC_READ_REG32(&core_if->core_global_regs->dtxfsiz[fifo_num]))) {
++06098                 if (dwc_otg_param_initialized
++06099                     (core_if->core_params->dev_perio_tx_fifo_size[fifo_num])) {
++06100                         DWC_ERROR
++06101                             ("`%d' invalid for parameter `dev_perio_fifo_size_%d'. Check HW configuration.\n",
++06102                              val, fifo_num);
++06103                 }
++06104                 val = (DWC_READ_REG32(&core_if->core_global_regs->dtxfsiz[fifo_num]));
++06105                 retval = -DWC_E_INVALID;
++06106         }
++06107 
++06108         core_if->core_params->dev_perio_tx_fifo_size[fifo_num] = val;
++06109         return retval;
++06110 }
++06111 
++06112 int32_t dwc_otg_get_param_dev_perio_tx_fifo_size(dwc_otg_core_if_t * core_if,
++06113                                                  int fifo_num)
++06114 {
++06115         return core_if->core_params->dev_perio_tx_fifo_size[fifo_num];
++06116 }
++06117 
++06118 int dwc_otg_set_param_en_multiple_tx_fifo(dwc_otg_core_if_t * core_if,
++06119                                           int32_t val)
++06120 {
++06121         int retval = 0;
++06122         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
++06123                 DWC_WARN("Wrong valaue for en_multiple_tx_fifo,\n");
++06124                 DWC_WARN("en_multiple_tx_fifo must be 0 or 1\n");
++06125                 return -DWC_E_INVALID;
++06126         }
++06127 
++06128         if (val == 1 && core_if->hwcfg4.b.ded_fifo_en == 0) {
++06129                 if (dwc_otg_param_initialized
++06130                     (core_if->core_params->en_multiple_tx_fifo)) {
++06131                         DWC_ERROR
++06132                             ("%d invalid for parameter en_multiple_tx_fifo. Check HW configuration.\n",
++06133                              val);
++06134                 }
++06135                 val = 0;
++06136                 retval = -DWC_E_INVALID;
++06137         }
++06138 
++06139         core_if->core_params->en_multiple_tx_fifo = val;
++06140         return retval;
++06141 }
++06142 
++06143 int32_t dwc_otg_get_param_en_multiple_tx_fifo(dwc_otg_core_if_t * core_if)
++06144 {
++06145         return core_if->core_params->en_multiple_tx_fifo;
++06146 }
++06147 
++06148 int dwc_otg_set_param_dev_tx_fifo_size(dwc_otg_core_if_t * core_if, int32_t val,
++06149                                        int fifo_num)
++06150 {
++06151         int retval = 0;
++06152 
++06153         if (DWC_OTG_PARAM_TEST(val, 4, 768)) {
++06154                 DWC_WARN("Wrong value for dev_tx_fifo_size\n");
++06155                 DWC_WARN("dev_tx_fifo_size must be 4-768\n");
++06156                 return -DWC_E_INVALID;
++06157         }
++06158 
++06159         if (val >
++06160             (DWC_READ_REG32(&core_if->core_global_regs->dtxfsiz[fifo_num]))) {
++06161                 if (dwc_otg_param_initialized
++06162                     (core_if->core_params->dev_tx_fifo_size[fifo_num])) {
++06163                         DWC_ERROR
++06164                             ("`%d' invalid for parameter `dev_tx_fifo_size_%d'. Check HW configuration.\n",
++06165                              val, fifo_num);
++06166                 }
++06167                 val = (DWC_READ_REG32(&core_if->core_global_regs->dtxfsiz[fifo_num]));
++06168                 retval = -DWC_E_INVALID;
++06169         }
++06170 
++06171         core_if->core_params->dev_tx_fifo_size[fifo_num] = val;
++06172         return retval;
++06173 }
++06174 
++06175 int32_t dwc_otg_get_param_dev_tx_fifo_size(dwc_otg_core_if_t * core_if,
++06176                                            int fifo_num)
++06177 {
++06178         return core_if->core_params->dev_tx_fifo_size[fifo_num];
++06179 }
++06180 
++06181 int dwc_otg_set_param_thr_ctl(dwc_otg_core_if_t * core_if, int32_t val)
++06182 {
++06183         int retval = 0;
++06184 
++06185         if (DWC_OTG_PARAM_TEST(val, 0, 7)) {
++06186                 DWC_WARN("Wrong value for thr_ctl\n");
++06187                 DWC_WARN("thr_ctl must be 0-7\n");
++06188                 return -DWC_E_INVALID;
++06189         }
++06190 
++06191         if ((val != 0) &&
++06192             (!dwc_otg_get_param_dma_enable(core_if) ||
++06193              !core_if->hwcfg4.b.ded_fifo_en)) {
++06194                 if (dwc_otg_param_initialized(core_if->core_params->thr_ctl)) {
++06195                         DWC_ERROR
++06196                             ("%d invalid for parameter thr_ctl. Check HW configuration.\n",
++06197                              val);
++06198                 }
++06199                 val = 0;
++06200                 retval = -DWC_E_INVALID;
++06201         }
++06202 
++06203         core_if->core_params->thr_ctl = val;
++06204         return retval;
++06205 }
++06206 
++06207 int32_t dwc_otg_get_param_thr_ctl(dwc_otg_core_if_t * core_if)
++06208 {
++06209         return core_if->core_params->thr_ctl;
++06210 }
++06211 
++06212 int dwc_otg_set_param_lpm_enable(dwc_otg_core_if_t * core_if, int32_t val)
++06213 {
++06214         int retval = 0;
++06215 
++06216         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
++06217                 DWC_WARN("Wrong value for lpm_enable\n");
++06218                 DWC_WARN("lpm_enable must be 0 or 1\n");
++06219                 return -DWC_E_INVALID;
++06220         }
++06221 
++06222         if (val && !core_if->hwcfg3.b.otg_lpm_en) {
++06223                 if (dwc_otg_param_initialized(core_if->core_params->lpm_enable)) {
++06224                         DWC_ERROR
++06225                             ("%d invalid for parameter lpm_enable. Check HW configuration.\n",
++06226                              val);
++06227                 }
++06228                 val = 0;
++06229                 retval = -DWC_E_INVALID;
++06230         }
++06231 
++06232         core_if->core_params->lpm_enable = val;
++06233         return retval;
++06234 }
++06235 
++06236 int32_t dwc_otg_get_param_lpm_enable(dwc_otg_core_if_t * core_if)
++06237 {
++06238         return core_if->core_params->lpm_enable;
++06239 }
++06240 
++06241 int dwc_otg_set_param_tx_thr_length(dwc_otg_core_if_t * core_if, int32_t val)
++06242 {
++06243         if (DWC_OTG_PARAM_TEST(val, 8, 128)) {
++06244                 DWC_WARN("Wrong valaue for tx_thr_length\n");
++06245                 DWC_WARN("tx_thr_length must be 8 - 128\n");
++06246                 return -DWC_E_INVALID;
++06247         }
++06248 
++06249         core_if->core_params->tx_thr_length = val;
++06250         return 0;
++06251 }
++06252 
++06253 int32_t dwc_otg_get_param_tx_thr_length(dwc_otg_core_if_t * core_if)
++06254 {
++06255         return core_if->core_params->tx_thr_length;
++06256 }
++06257 
++06258 int dwc_otg_set_param_rx_thr_length(dwc_otg_core_if_t * core_if, int32_t val)
++06259 {
++06260         if (DWC_OTG_PARAM_TEST(val, 8, 128)) {
++06261                 DWC_WARN("Wrong valaue for rx_thr_length\n");
++06262                 DWC_WARN("rx_thr_length must be 8 - 128\n");
++06263                 return -DWC_E_INVALID;
++06264         }
++06265 
++06266         core_if->core_params->rx_thr_length = val;
++06267         return 0;
++06268 }
++06269 
++06270 int32_t dwc_otg_get_param_rx_thr_length(dwc_otg_core_if_t * core_if)
++06271 {
++06272         return core_if->core_params->rx_thr_length;
++06273 }
++06274 
++06275 int dwc_otg_set_param_dma_burst_size(dwc_otg_core_if_t * core_if, int32_t val)
++06276 {
++06277         if (DWC_OTG_PARAM_TEST(val, 1, 1) &&
++06278             DWC_OTG_PARAM_TEST(val, 4, 4) &&
++06279             DWC_OTG_PARAM_TEST(val, 8, 8) &&
++06280             DWC_OTG_PARAM_TEST(val, 16, 16) &&
++06281             DWC_OTG_PARAM_TEST(val, 32, 32) &&
++06282             DWC_OTG_PARAM_TEST(val, 64, 64) &&
++06283             DWC_OTG_PARAM_TEST(val, 128, 128) &&
++06284             DWC_OTG_PARAM_TEST(val, 256, 256)) {
++06285                 DWC_WARN("`%d' invalid for parameter `dma_burst_size'\n", val);
++06286                 return -DWC_E_INVALID;
++06287         }
++06288         core_if->core_params->dma_burst_size = val;
++06289         return 0;
++06290 }
++06291 
++06292 int32_t dwc_otg_get_param_dma_burst_size(dwc_otg_core_if_t * core_if)
++06293 {
++06294         return core_if->core_params->dma_burst_size;
++06295 }
++06296 
++06297 int dwc_otg_set_param_pti_enable(dwc_otg_core_if_t * core_if, int32_t val)
++06298 {
++06299         int retval = 0;
++06300         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
++06301                 DWC_WARN("`%d' invalid for parameter `pti_enable'\n", val);
++06302                 return -DWC_E_INVALID;
++06303         }
++06304         if (val && (core_if->snpsid < OTG_CORE_REV_2_72a)) {
++06305                 if (dwc_otg_param_initialized(core_if->core_params->pti_enable)) {
++06306                         DWC_ERROR
++06307                             ("%d invalid for parameter pti_enable. Check HW configuration.\n",
++06308                              val);
++06309                 }
++06310                 retval = -DWC_E_INVALID;
++06311                 val = 0;
++06312         }
++06313         core_if->core_params->pti_enable = val;
++06314         return retval;
++06315 }
++06316 
++06317 int32_t dwc_otg_get_param_pti_enable(dwc_otg_core_if_t * core_if)
++06318 {
++06319         return core_if->core_params->pti_enable;
++06320 }
++06321 
++06322 int dwc_otg_set_param_mpi_enable(dwc_otg_core_if_t * core_if, int32_t val)
++06323 {
++06324         int retval = 0;
++06325         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
++06326                 DWC_WARN("`%d' invalid for parameter `mpi_enable'\n", val);
++06327                 return -DWC_E_INVALID;
++06328         }
++06329         if (val && (core_if->hwcfg2.b.multi_proc_int == 0)) {
++06330                 if (dwc_otg_param_initialized(core_if->core_params->mpi_enable)) {
++06331                         DWC_ERROR
++06332                             ("%d invalid for parameter mpi_enable. Check HW configuration.\n",
++06333                              val);
++06334                 }
++06335                 retval = -DWC_E_INVALID;
++06336                 val = 0;
++06337         }
++06338         core_if->core_params->mpi_enable = val;
++06339         return retval;
++06340 }
++06341 
++06342 int32_t dwc_otg_get_param_mpi_enable(dwc_otg_core_if_t * core_if)
++06343 {
++06344         return core_if->core_params->mpi_enable;
++06345 }
++06346 
++06347 int dwc_otg_set_param_adp_enable(dwc_otg_core_if_t * core_if, int32_t val)
++06348 {
++06349         int retval = 0;
++06350         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
++06351                 DWC_WARN("`%d' invalid for parameter `adp_enable'\n", val);
++06352                 return -DWC_E_INVALID;
++06353         }
++06354         if (val && (core_if->hwcfg3.b.adp_supp == 0)) {
++06355                 if (dwc_otg_param_initialized
++06356                     (core_if->core_params->adp_supp_enable)) {
++06357                         DWC_ERROR
++06358                             ("%d invalid for parameter adp_enable. Check HW configuration.\n",
++06359                              val);
++06360                 }
++06361                 retval = -DWC_E_INVALID;
++06362                 val = 0;
++06363         }
++06364         core_if->core_params->adp_supp_enable = val;
++06365         /*Set OTG version 2.0 in case of enabling ADP*/
++06366         if (val)
++06367                 dwc_otg_set_param_otg_ver(core_if, 1);
++06368 
++06369         return retval;
++06370 }
++06371 
++06372 int32_t dwc_otg_get_param_adp_enable(dwc_otg_core_if_t * core_if)
++06373 {
++06374         return core_if->core_params->adp_supp_enable;
++06375 }
++06376 
++06377 int dwc_otg_set_param_ic_usb_cap(dwc_otg_core_if_t * core_if, int32_t val)
++06378 {
++06379         int retval = 0;
++06380         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
++06381                 DWC_WARN("`%d' invalid for parameter `ic_usb_cap'\n", val);
++06382                 DWC_WARN("ic_usb_cap must be 0 or 1\n");
++06383                 return -DWC_E_INVALID;
++06384         }
++06385 
++06386         if (val && (core_if->hwcfg2.b.otg_enable_ic_usb == 0)) {
++06387                 if (dwc_otg_param_initialized(core_if->core_params->ic_usb_cap)) {
++06388                         DWC_ERROR
++06389                             ("%d invalid for parameter ic_usb_cap. Check HW configuration.\n",
++06390                              val);
++06391                 }
++06392                 retval = -DWC_E_INVALID;
++06393                 val = 0;
++06394         }
++06395         core_if->core_params->ic_usb_cap = val;
++06396         return retval;
++06397 }
++06398 
++06399 int32_t dwc_otg_get_param_ic_usb_cap(dwc_otg_core_if_t * core_if)
++06400 {
++06401         return core_if->core_params->ic_usb_cap;
++06402 }
++06403 
++06404 int dwc_otg_set_param_ahb_thr_ratio(dwc_otg_core_if_t * core_if, int32_t val)
++06405 {
++06406         int retval = 0;
++06407         int valid = 1;
++06408 
++06409         if (DWC_OTG_PARAM_TEST(val, 0, 3)) {
++06410                 DWC_WARN("`%d' invalid for parameter `ahb_thr_ratio'\n", val);
++06411                 DWC_WARN("ahb_thr_ratio must be 0 - 3\n");
++06412                 return -DWC_E_INVALID;
++06413         }
++06414 
++06415         if (val
++06416             && (core_if->snpsid < OTG_CORE_REV_2_81a
++06417                 || !dwc_otg_get_param_thr_ctl(core_if))) {
++06418                 valid = 0;
++06419         } else if (val
++06420                    && ((dwc_otg_get_param_tx_thr_length(core_if) / (1 << val)) <
++06421                        4)) {
++06422                 valid = 0;
++06423         }
++06424         if (valid == 0) {
++06425                 if (dwc_otg_param_initialized
++06426                     (core_if->core_params->ahb_thr_ratio)) {
++06427                         DWC_ERROR
++06428                             ("%d invalid for parameter ahb_thr_ratio. Check HW configuration.\n",
++06429                              val);
++06430                 }
++06431                 retval = -DWC_E_INVALID;
++06432                 val = 0;
++06433         }
++06434 
++06435         core_if->core_params->ahb_thr_ratio = val;
++06436         return retval;
++06437 }
++06438 
++06439 int32_t dwc_otg_get_param_ahb_thr_ratio(dwc_otg_core_if_t * core_if)
++06440 {
++06441         return core_if->core_params->ahb_thr_ratio;
++06442 }
++06443 
++06444 int dwc_otg_set_param_power_down(dwc_otg_core_if_t * core_if, int32_t val)
++06445 {
++06446         int retval = 0;
++06447         int valid = 1;
++06448 
++06449         if (DWC_OTG_PARAM_TEST(val, 0, 2)) {
++06450                 DWC_WARN("`%d' invalid for parameter `power_down'\n", val);
++06451                 DWC_WARN("power_down must be 0 - 2\n");
++06452                 return -DWC_E_INVALID;
++06453         }
++06454 
++06455         if ((val == 2) && (core_if->snpsid < OTG_CORE_REV_2_91a)) {
++06456                 valid = 0;
++06457         }
++06458         if (valid == 0) {
++06459                 if (dwc_otg_param_initialized(core_if->core_params->power_down)) {
++06460                         DWC_ERROR
++06461                             ("%d invalid for parameter power_down. Check HW configuration.\n",
++06462                              val);
++06463                 }
++06464                 retval = -DWC_E_INVALID;
++06465                 val = 0;
++06466         }
++06467         core_if->core_params->power_down = val;
++06468         return retval;
++06469 }
++06470 
++06471 int32_t dwc_otg_get_param_power_down(dwc_otg_core_if_t * core_if)
++06472 {
++06473         return core_if->core_params->power_down;
++06474 }
++06475 
++06476 int dwc_otg_set_param_reload_ctl(dwc_otg_core_if_t * core_if, int32_t val)
++06477 {
++06478         int retval = 0;
++06479         int valid = 1;
++06480 
++06481         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
++06482                 DWC_WARN("`%d' invalid for parameter `reload_ctl'\n", val);
++06483                 DWC_WARN("reload_ctl must be 0 or 1\n");
++06484                 return -DWC_E_INVALID;
++06485         }
++06486 
++06487         if ((val == 1) && (core_if->snpsid < OTG_CORE_REV_2_92a)) {
++06488                 valid = 0;
++06489         }
++06490         if (valid == 0) {
++06491                 if (dwc_otg_param_initialized(core_if->core_params->reload_ctl)) {
++06492                         DWC_ERROR("%d invalid for parameter reload_ctl."
++06493                                   "Check HW configuration.\n", val);
++06494                 }
++06495                 retval = -DWC_E_INVALID;
++06496                 val = 0;
++06497         }
++06498         core_if->core_params->reload_ctl = val;
++06499         return retval;
++06500 }
++06501 
++06502 int32_t dwc_otg_get_param_reload_ctl(dwc_otg_core_if_t * core_if)
++06503 {
++06504         return core_if->core_params->reload_ctl;
++06505 }
++06506 
++06507 int dwc_otg_set_param_dev_out_nak(dwc_otg_core_if_t * core_if, int32_t val)
++06508 {
++06509         int retval = 0;
++06510         int valid = 1;
++06511 
++06512         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
++06513                 DWC_WARN("`%d' invalid for parameter `dev_out_nak'\n", val);
++06514                 DWC_WARN("dev_out_nak must be 0 or 1\n");
++06515                 return -DWC_E_INVALID;
++06516         }
++06517 
++06518         if ((val == 1) && ((core_if->snpsid < OTG_CORE_REV_2_93a) ||
++06519                 !(core_if->core_params->dma_desc_enable))) {
++06520                 valid = 0;
++06521         }
++06522         if (valid == 0) {
++06523                 if (dwc_otg_param_initialized(core_if->core_params->dev_out_nak)) {
++06524                         DWC_ERROR("%d invalid for parameter dev_out_nak."
++06525                                 "Check HW configuration.\n", val);
++06526                 }
++06527                 retval = -DWC_E_INVALID;
++06528                 val = 0;
++06529         }
++06530         core_if->core_params->dev_out_nak = val;
++06531         return retval;
++06532 }
++06533 
++06534 int32_t dwc_otg_get_param_dev_out_nak(dwc_otg_core_if_t * core_if)
++06535 {
++06536         return core_if->core_params->dev_out_nak;
++06537 }
++06538 
++06539 int dwc_otg_set_param_cont_on_bna(dwc_otg_core_if_t * core_if, int32_t val)
++06540 {
++06541         int retval = 0;
++06542         int valid = 1;
++06543 
++06544         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
++06545                 DWC_WARN("`%d' invalid for parameter `cont_on_bna'\n", val);
++06546                 DWC_WARN("cont_on_bna must be 0 or 1\n");
++06547                 return -DWC_E_INVALID;
++06548         }
++06549 
++06550         if ((val == 1) && ((core_if->snpsid < OTG_CORE_REV_2_94a) ||
++06551                 !(core_if->core_params->dma_desc_enable))) {
++06552                         valid = 0;
++06553         }
++06554         if (valid == 0) {
++06555                 if (dwc_otg_param_initialized(core_if->core_params->cont_on_bna)) {
++06556                         DWC_ERROR("%d invalid for parameter cont_on_bna."
++06557                                 "Check HW configuration.\n", val);
++06558                 }
++06559                 retval = -DWC_E_INVALID;
++06560                 val = 0;
++06561         }
++06562         core_if->core_params->cont_on_bna = val;
++06563         return retval;
++06564 }
++06565 
++06566 int32_t dwc_otg_get_param_cont_on_bna(dwc_otg_core_if_t * core_if)
++06567 {
++06568         return core_if->core_params->cont_on_bna;
++06569 }
++06570 
++06571 int dwc_otg_set_param_ahb_single(dwc_otg_core_if_t * core_if, int32_t val)
++06572 {
++06573         int retval = 0;
++06574         int valid = 1;
++06575 
++06576         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
++06577                 DWC_WARN("`%d' invalid for parameter `ahb_single'\n", val);
++06578                 DWC_WARN("ahb_single must be 0 or 1\n");
++06579                 return -DWC_E_INVALID;
++06580         }
++06581 
++06582         if ((val == 1) && (core_if->snpsid < OTG_CORE_REV_2_94a)) {
++06583                         valid = 0;
++06584         }
++06585         if (valid == 0) {
++06586                 if (dwc_otg_param_initialized(core_if->core_params->ahb_single)) {
++06587                         DWC_ERROR("%d invalid for parameter ahb_single."
++06588                                 "Check HW configuration.\n", val);
++06589                 }
++06590                 retval = -DWC_E_INVALID;
++06591                 val = 0;
++06592         }
++06593         core_if->core_params->ahb_single = val;
++06594         return retval;
++06595 }
++06596 
++06597 int32_t dwc_otg_get_param_ahb_single(dwc_otg_core_if_t * core_if)
++06598 {
++06599         return core_if->core_params->ahb_single;
++06600 }
++06601 
++06602 int dwc_otg_set_param_otg_ver(dwc_otg_core_if_t * core_if, int32_t val)
++06603 {
++06604         int retval = 0;
++06605 
++06606         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
++06607                 DWC_WARN("`%d' invalid for parameter `otg_ver'\n", val);
++06608                 DWC_WARN
++06609                     ("otg_ver must be 0(for OTG 1.3 support) or 1(for OTG 2.0 support)\n");
++06610                 return -DWC_E_INVALID;
++06611         }
++06612 
++06613         core_if->core_params->otg_ver = val;
++06614         return retval;
++06615 }
++06616 
++06617 int32_t dwc_otg_get_param_otg_ver(dwc_otg_core_if_t * core_if)
++06618 {
++06619         return core_if->core_params->otg_ver;
++06620 }
++06621 
++06622 uint32_t dwc_otg_get_hnpstatus(dwc_otg_core_if_t * core_if)
++06623 {
++06624         gotgctl_data_t otgctl;
++06625         otgctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->gotgctl);
++06626         return otgctl.b.hstnegscs;
++06627 }
++06628 
++06629 uint32_t dwc_otg_get_srpstatus(dwc_otg_core_if_t * core_if)
++06630 {
++06631         gotgctl_data_t otgctl;
++06632         otgctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->gotgctl);
++06633         return otgctl.b.sesreqscs;
++06634 }
++06635 
++06636 void dwc_otg_set_hnpreq(dwc_otg_core_if_t * core_if, uint32_t val)
++06637 {
++06638         if(core_if->otg_ver == 0) {
++06639                 gotgctl_data_t otgctl;
++06640                 otgctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->gotgctl);
++06641                 otgctl.b.hnpreq = val;
++06642                 DWC_WRITE_REG32(&core_if->core_global_regs->gotgctl, otgctl.d32);
++06643         } else {
++06644                 core_if->otg_sts = val;
++06645         }
++06646 }
++06647 
++06648 uint32_t dwc_otg_get_gsnpsid(dwc_otg_core_if_t * core_if)
++06649 {
++06650         return core_if->snpsid;
++06651 }
++06652 
++06653 uint32_t dwc_otg_get_mode(dwc_otg_core_if_t * core_if)
++06654 {
++06655         gintsts_data_t gintsts;
++06656         gintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts);
++06657         return gintsts.b.curmode;
++06658 }
++06659 
++06660 uint32_t dwc_otg_get_hnpcapable(dwc_otg_core_if_t * core_if)
++06661 {
++06662         gusbcfg_data_t usbcfg;
++06663         usbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
++06664         return usbcfg.b.hnpcap;
++06665 }
++06666 
++06667 void dwc_otg_set_hnpcapable(dwc_otg_core_if_t * core_if, uint32_t val)
++06668 {
++06669         gusbcfg_data_t usbcfg;
++06670         usbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
++06671         usbcfg.b.hnpcap = val;
++06672         DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, usbcfg.d32);
++06673 }
++06674 
++06675 uint32_t dwc_otg_get_srpcapable(dwc_otg_core_if_t * core_if)
++06676 {
++06677         gusbcfg_data_t usbcfg;
++06678         usbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
++06679         return usbcfg.b.srpcap;
++06680 }
++06681 
++06682 void dwc_otg_set_srpcapable(dwc_otg_core_if_t * core_if, uint32_t val)
++06683 {
++06684         gusbcfg_data_t usbcfg;
++06685         usbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
++06686         usbcfg.b.srpcap = val;
++06687         DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, usbcfg.d32);
++06688 }
++06689 
++06690 uint32_t dwc_otg_get_devspeed(dwc_otg_core_if_t * core_if)
++06691 {
++06692         dcfg_data_t dcfg;
++06693         dcfg.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg);
++06694         return dcfg.b.devspd;
++06695 }
++06696 
++06697 void dwc_otg_set_devspeed(dwc_otg_core_if_t * core_if, uint32_t val)
++06698 {
++06699         dcfg_data_t dcfg;
++06700         dcfg.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg);
++06701         dcfg.b.devspd = val;
++06702         DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dcfg, dcfg.d32);
++06703 }
++06704 
++06705 uint32_t dwc_otg_get_busconnected(dwc_otg_core_if_t * core_if)
++06706 {
++06707         hprt0_data_t hprt0;
++06708         hprt0.d32 = DWC_READ_REG32(core_if->host_if->hprt0);
++06709         return hprt0.b.prtconnsts;
++06710 }
++06711 
++06712 uint32_t dwc_otg_get_enumspeed(dwc_otg_core_if_t * core_if)
++06713 {
++06714         dsts_data_t dsts;
++06715         dsts.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts);
++06716         return dsts.b.enumspd;
++06717 }
++06718 
++06719 uint32_t dwc_otg_get_prtpower(dwc_otg_core_if_t * core_if)
++06720 {
++06721         hprt0_data_t hprt0;
++06722         hprt0.d32 = DWC_READ_REG32(core_if->host_if->hprt0);
++06723         return hprt0.b.prtpwr;
++06724 
++06725 }
++06726 
++06727 uint32_t dwc_otg_get_core_state(dwc_otg_core_if_t * core_if)
++06728 {
++06729         return core_if->hibernation_suspend;
++06730 }
++06731 
++06732 void dwc_otg_set_prtpower(dwc_otg_core_if_t * core_if, uint32_t val)
++06733 {
++06734         hprt0_data_t hprt0;
++06735         hprt0.d32 = dwc_otg_read_hprt0(core_if);
++06736         hprt0.b.prtpwr = val;
++06737         DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
++06738 }
++06739 
++06740 uint32_t dwc_otg_get_prtsuspend(dwc_otg_core_if_t * core_if)
++06741 {
++06742         hprt0_data_t hprt0;
++06743         hprt0.d32 = DWC_READ_REG32(core_if->host_if->hprt0);
++06744         return hprt0.b.prtsusp;
++06745 
++06746 }
++06747 
++06748 void dwc_otg_set_prtsuspend(dwc_otg_core_if_t * core_if, uint32_t val)
++06749 {
++06750         hprt0_data_t hprt0;
++06751         hprt0.d32 = dwc_otg_read_hprt0(core_if);
++06752         hprt0.b.prtsusp = val;
++06753         DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
++06754 }
++06755 
++06756 uint32_t dwc_otg_get_fr_interval(dwc_otg_core_if_t * core_if)
++06757 {
++06758         hfir_data_t hfir;
++06759         hfir.d32 = DWC_READ_REG32(&core_if->host_if->host_global_regs->hfir);
++06760         return hfir.b.frint;
++06761 
++06762 }
++06763 
++06764 void dwc_otg_set_fr_interval(dwc_otg_core_if_t * core_if, uint32_t val)
++06765 {
++06766         hfir_data_t hfir;
++06767         uint32_t fram_int;
++06768         fram_int = calc_frame_interval(core_if);
++06769         hfir.d32 = DWC_READ_REG32(&core_if->host_if->host_global_regs->hfir);
++06770         if (!core_if->core_params->reload_ctl) {
++06771                 DWC_WARN("\nCannot reload HFIR register.HFIR.HFIRRldCtrl bit is"
++06772                          "not set to 1.\nShould load driver with reload_ctl=1"
++06773                          " module parameter\n");
++06774                 return;
++06775         }
++06776         switch (fram_int) {
++06777         case 3750:
++06778                 if ((val < 3350) || (val > 4150)) {
++06779                         DWC_WARN("HFIR interval for HS core and 30 MHz"
++06780                                  "clock freq should be from 3350 to 4150\n");
++06781                         return;
++06782                 }
++06783                 break;
++06784         case 30000:
++06785                 if ((val < 26820) || (val > 33180)) {
++06786                         DWC_WARN("HFIR interval for FS/LS core and 30 MHz"
++06787                                  "clock freq should be from 26820 to 33180\n");
++06788                         return;
++06789                 }
++06790                 break;
++06791         case 6000:
++06792                 if ((val < 5360) || (val > 6640)) {
++06793                         DWC_WARN("HFIR interval for HS core and 48 MHz"
++06794                                  "clock freq should be from 5360 to 6640\n");
++06795                         return;
++06796                 }
++06797                 break;
++06798         case 48000:
++06799                 if ((val < 42912) || (val > 53088)) {
++06800                         DWC_WARN("HFIR interval for FS/LS core and 48 MHz"
++06801                                  "clock freq should be from 42912 to 53088\n");
++06802                         return;
++06803                 }
++06804                 break;
++06805         case 7500:
++06806                 if ((val < 6700) || (val > 8300)) {
++06807                         DWC_WARN("HFIR interval for HS core and 60 MHz"
++06808                                  "clock freq should be from 6700 to 8300\n");
++06809                         return;
++06810                 }
++06811                 break;
++06812         case 60000:
++06813                 if ((val < 53640) || (val > 65536)) {
++06814                         DWC_WARN("HFIR interval for FS/LS core and 60 MHz"
++06815                                  "clock freq should be from 53640 to 65536\n");
++06816                         return;
++06817                 }
++06818                 break;
++06819         default:
++06820                 DWC_WARN("Unknown frame interval\n");
++06821                 return;
++06822                 break;
++06823 
++06824         }
++06825         hfir.b.frint = val;
++06826         DWC_WRITE_REG32(&core_if->host_if->host_global_regs->hfir, hfir.d32);
++06827 }
++06828 
++06829 uint32_t dwc_otg_get_mode_ch_tim(dwc_otg_core_if_t * core_if)
++06830 {
++06831         hcfg_data_t hcfg;
++06832         hcfg.d32 = DWC_READ_REG32(&core_if->host_if->host_global_regs->hcfg);
++06833         return hcfg.b.modechtimen;
++06834 
++06835 }
++06836 
++06837 void dwc_otg_set_mode_ch_tim(dwc_otg_core_if_t * core_if, uint32_t val)
++06838 {
++06839         hcfg_data_t hcfg;
++06840         hcfg.d32 = DWC_READ_REG32(&core_if->host_if->host_global_regs->hcfg);
++06841         hcfg.b.modechtimen = val;
++06842         DWC_WRITE_REG32(&core_if->host_if->host_global_regs->hcfg, hcfg.d32);
++06843 }
++06844 
++06845 void dwc_otg_set_prtresume(dwc_otg_core_if_t * core_if, uint32_t val)
++06846 {
++06847         hprt0_data_t hprt0;
++06848         hprt0.d32 = dwc_otg_read_hprt0(core_if);
++06849         hprt0.b.prtres = val;
++06850         DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
++06851 }
++06852 
++06853 uint32_t dwc_otg_get_remotewakesig(dwc_otg_core_if_t * core_if)
++06854 {
++06855         dctl_data_t dctl;
++06856         dctl.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dctl);
++06857         return dctl.b.rmtwkupsig;
++06858 }
++06859 
++06860 uint32_t dwc_otg_get_lpm_portsleepstatus(dwc_otg_core_if_t * core_if)
++06861 {
++06862         glpmcfg_data_t lpmcfg;
++06863         lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
++06864 
++06865         DWC_ASSERT(!
++06866                    ((core_if->lx_state == DWC_OTG_L1) ^ lpmcfg.b.prt_sleep_sts),
++06867                    "lx_state = %d, lmpcfg.prt_sleep_sts = %d\n",
++06868                    core_if->lx_state, lpmcfg.b.prt_sleep_sts);
++06869 
++06870         return lpmcfg.b.prt_sleep_sts;
++06871 }
++06872 
++06873 uint32_t dwc_otg_get_lpm_remotewakeenabled(dwc_otg_core_if_t * core_if)
++06874 {
++06875         glpmcfg_data_t lpmcfg;
++06876         lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
++06877         return lpmcfg.b.rem_wkup_en;
++06878 }
++06879 
++06880 uint32_t dwc_otg_get_lpmresponse(dwc_otg_core_if_t * core_if)
++06881 {
++06882         glpmcfg_data_t lpmcfg;
++06883         lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
++06884         return lpmcfg.b.appl_resp;
++06885 }
++06886 
++06887 void dwc_otg_set_lpmresponse(dwc_otg_core_if_t * core_if, uint32_t val)
++06888 {
++06889         glpmcfg_data_t lpmcfg;
++06890         lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
++06891         lpmcfg.b.appl_resp = val;
++06892         DWC_WRITE_REG32(&core_if->core_global_regs->glpmcfg, lpmcfg.d32);
++06893 }
++06894 
++06895 uint32_t dwc_otg_get_hsic_connect(dwc_otg_core_if_t * core_if)
++06896 {
++06897         glpmcfg_data_t lpmcfg;
++06898         lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
++06899         return lpmcfg.b.hsic_connect;
++06900 }
++06901 
++06902 void dwc_otg_set_hsic_connect(dwc_otg_core_if_t * core_if, uint32_t val)
++06903 {
++06904         glpmcfg_data_t lpmcfg;
++06905         lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
++06906         lpmcfg.b.hsic_connect = val;
++06907         DWC_WRITE_REG32(&core_if->core_global_regs->glpmcfg, lpmcfg.d32);
++06908 }
++06909 
++06910 uint32_t dwc_otg_get_inv_sel_hsic(dwc_otg_core_if_t * core_if)
++06911 {
++06912         glpmcfg_data_t lpmcfg;
++06913         lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
++06914         return lpmcfg.b.inv_sel_hsic;
++06915 
++06916 }
++06917 
++06918 void dwc_otg_set_inv_sel_hsic(dwc_otg_core_if_t * core_if, uint32_t val)
++06919 {
++06920         glpmcfg_data_t lpmcfg;
++06921         lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
++06922         lpmcfg.b.inv_sel_hsic = val;
++06923         DWC_WRITE_REG32(&core_if->core_global_regs->glpmcfg, lpmcfg.d32);
++06924 }
++06925 
++06926 uint32_t dwc_otg_get_gotgctl(dwc_otg_core_if_t * core_if)
++06927 {
++06928         return DWC_READ_REG32(&core_if->core_global_regs->gotgctl);
++06929 }
++06930 
++06931 void dwc_otg_set_gotgctl(dwc_otg_core_if_t * core_if, uint32_t val)
++06932 {
++06933         DWC_WRITE_REG32(&core_if->core_global_regs->gotgctl, val);
++06934 }
++06935 
++06936 uint32_t dwc_otg_get_gusbcfg(dwc_otg_core_if_t * core_if)
++06937 {
++06938         return DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
++06939 }
++06940 
++06941 void dwc_otg_set_gusbcfg(dwc_otg_core_if_t * core_if, uint32_t val)
++06942 {
++06943         DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, val);
++06944 }
++06945 
++06946 uint32_t dwc_otg_get_grxfsiz(dwc_otg_core_if_t * core_if)
++06947 {
++06948         return DWC_READ_REG32(&core_if->core_global_regs->grxfsiz);
++06949 }
++06950 
++06951 void dwc_otg_set_grxfsiz(dwc_otg_core_if_t * core_if, uint32_t val)
++06952 {
++06953         DWC_WRITE_REG32(&core_if->core_global_regs->grxfsiz, val);
++06954 }
++06955 
++06956 uint32_t dwc_otg_get_gnptxfsiz(dwc_otg_core_if_t * core_if)
++06957 {
++06958         return DWC_READ_REG32(&core_if->core_global_regs->gnptxfsiz);
++06959 }
++06960 
++06961 void dwc_otg_set_gnptxfsiz(dwc_otg_core_if_t * core_if, uint32_t val)
++06962 {
++06963         DWC_WRITE_REG32(&core_if->core_global_regs->gnptxfsiz, val);
++06964 }
++06965 
++06966 uint32_t dwc_otg_get_gpvndctl(dwc_otg_core_if_t * core_if)
++06967 {
++06968         return DWC_READ_REG32(&core_if->core_global_regs->gpvndctl);
++06969 }
++06970 
++06971 void dwc_otg_set_gpvndctl(dwc_otg_core_if_t * core_if, uint32_t val)
++06972 {
++06973         DWC_WRITE_REG32(&core_if->core_global_regs->gpvndctl, val);
++06974 }
++06975 
++06976 uint32_t dwc_otg_get_ggpio(dwc_otg_core_if_t * core_if)
++06977 {
++06978         return DWC_READ_REG32(&core_if->core_global_regs->ggpio);
++06979 }
++06980 
++06981 void dwc_otg_set_ggpio(dwc_otg_core_if_t * core_if, uint32_t val)
++06982 {
++06983         DWC_WRITE_REG32(&core_if->core_global_regs->ggpio, val);
++06984 }
++06985 
++06986 uint32_t dwc_otg_get_hprt0(dwc_otg_core_if_t * core_if)
++06987 {
++06988         return DWC_READ_REG32(core_if->host_if->hprt0);
++06989 
++06990 }
++06991 
++06992 void dwc_otg_set_hprt0(dwc_otg_core_if_t * core_if, uint32_t val)
++06993 {
++06994         DWC_WRITE_REG32(core_if->host_if->hprt0, val);
++06995 }
++06996 
++06997 uint32_t dwc_otg_get_guid(dwc_otg_core_if_t * core_if)
++06998 {
++06999         return DWC_READ_REG32(&core_if->core_global_regs->guid);
++07000 }
++07001 
++07002 void dwc_otg_set_guid(dwc_otg_core_if_t * core_if, uint32_t val)
++07003 {
++07004         DWC_WRITE_REG32(&core_if->core_global_regs->guid, val);
++07005 }
++07006 
++07007 uint32_t dwc_otg_get_hptxfsiz(dwc_otg_core_if_t * core_if)
++07008 {
++07009         return DWC_READ_REG32(&core_if->core_global_regs->hptxfsiz);
++07010 }
++07011 
++07012 uint16_t dwc_otg_get_otg_version(dwc_otg_core_if_t * core_if)
++07013 {
++07014         return ((core_if->otg_ver == 1) ? (uint16_t)0x0200 : (uint16_t)0x0103);
++07015 }
++07016 
++07023 void dwc_otg_pcd_start_srp_timer(dwc_otg_core_if_t * core_if)
++07024 {
++07025         core_if->srp_timer_started = 1;
++07026         DWC_TIMER_SCHEDULE(core_if->srp_timer, 6000 /* 6 secs */ );
++07027 }
++07028 
++07029 void dwc_otg_initiate_srp(dwc_otg_core_if_t * core_if)
++07030 {
++07031         uint32_t *addr = (uint32_t *) & (core_if->core_global_regs->gotgctl);
++07032         gotgctl_data_t mem;
++07033         gotgctl_data_t val;
++07034 
++07035         val.d32 = DWC_READ_REG32(addr);
++07036         if (val.b.sesreq) {
++07037                 DWC_ERROR("Session Request Already active!\n");
++07038                 return;
++07039         }
++07040 
++07041         DWC_INFO("Session Request Initated\n"); //NOTICE
++07042         mem.d32 = DWC_READ_REG32(addr);
++07043         mem.b.sesreq = 1;
++07044         DWC_WRITE_REG32(addr, mem.d32);
++07045 
++07046         /* Start the SRP timer */
++07047         dwc_otg_pcd_start_srp_timer(core_if);
++07048         return;
++07049 }
++
Generated on Thu Oct 27 03:56:37 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
++doxygen 1.3.9.1
+ + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__cil_8c.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/dwc__otg__cil_8c.html 2013-07-26 19:31:20.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__cil_8c.html 2013-07-26 19:34:40.000000000 +0000 +@@ -2,605 +2,716 @@ + + DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_cil.c File Reference + +- + +- +-
+-
+-
+-
++ ++
Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
+

dwc_otg_cil.c File Reference

The Core Interface Layer provides basic services for accessing and managing the DWC_otg hardware. More... +

+-#include "dwc_os.h"
+-#include "dwc_otg_regs.h"
+-#include "dwc_otg_cil.h"
++#include "dwc_os.h"
++#include "dwc_otg_regs.h"
++#include "dwc_otg_cil.h"
+ +

+ Go to the source code of this file. + + +- ++ + + +- ++ + +- ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ + + +- ++ + + +- ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ + +- +- ++ + +- +- ++ ++ + +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ + +- +- ++ ++ + +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- ++ + +- ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- ++ + +- ++ + +- ++ + +- +- ++ ++ + +- ++ + +- ++ + +- ++ + +- +- ++ ++ + +- ++ + +- +- ++ ++ + +- ++ + +- +- ++ ++ + +- ++ + + +- ++ + +- ++ + +- +- ++ ++ + +- ++ + +- +- ++ ++ + +- ++ + +- +- ++ ++ + +- ++ + +- +- ++ ++ + +- ++ + +- +- ++ ++ + +- ++ + +- +- ++ ++ + +- ++ + +- +- ++ ++ + +- ++ + +- +- ++ ++ + +- ++ + +- +- ++ ++ + +- ++ + +- +- ++ ++ + +- ++ + +- +- ++ ++ + +- ++ + +- +- ++ ++ + +- ++ + +- +- ++ ++ + +- ++ + +- +- ++ ++ + +- ++ + + +- ++ + +- ++ + +- +- ++ ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- +- ++ ++ + +- ++ + +- +- ++ ++ + +- ++ + + +- ++ + +- ++ + +- ++ + +- ++ + + +- ++ + +- ++ + + +- ++ + +- ++ + + +- ++ + +- ++ + + +- ++ + +- ++ + +- +- ++ ++ + +- ++ + + +- ++ + +- ++ + + +- ++ + +- ++ ++ ++ ++ ++ ++ + + +- ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ + +- ++ + +- ++ + +- ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ + +- +- ++ ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ ++ ++ ++ + + +- ++ + + +- ++ + + +- ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ + +- ++ + + +- ++ + +- ++ + + +- ++ + +- ++ + + +- ++ + +- ++ + +- ++ + +- ++ + + +- ++ + +- ++ + + +- ++ + +- ++ + + +- ++ + +- ++ + + ++ ++ ++ ++ ++ ++ ++ ++ +

Defines

#define DWC_OTG_PARAM_TEST(_param_, _low_, _high_)
#define DWC_OTG_PARAM_TEST(_param_, _low_, _high_)

Functions

+-static int dwc_otg_setup_params (dwc_otg_core_if_t *core_if)
++int dwc_otg_setup_params (dwc_otg_core_if_t *core_if)
dwc_otg_core_if_t * dwc_otg_cil_init (const uint32_t *reg_base_addr)
dwc_otg_core_if_t * dwc_otg_cil_init (const uint32_t *reg_base_addr)
 This function is called to initialize the DWC_otg CSR data structures.
void dwc_otg_cil_remove (dwc_otg_core_if_t *core_if)
 This function is called to initialize the DWC_otg CSR data structures.
void dwc_otg_cil_remove (dwc_otg_core_if_t *core_if)
 This function frees the structures allocated by dwc_otg_cil_init().
void dwc_otg_enable_global_interrupts (dwc_otg_core_if_t *core_if)
 This function frees the structures allocated by dwc_otg_cil_init().
void dwc_otg_enable_global_interrupts (dwc_otg_core_if_t *core_if)
 This function enables the controller's Global Interrupt in the AHB Config register.
void dwc_otg_disable_global_interrupts (dwc_otg_core_if_t *core_if)
 This function enables the controller's Global Interrupt in the AHB Config register.
void dwc_otg_disable_global_interrupts (dwc_otg_core_if_t *core_if)
 This function disables the controller's Global Interrupt in the AHB Config register.
static void dwc_otg_enable_common_interrupts (dwc_otg_core_if_t *core_if)
 This function disables the controller's Global Interrupt in the AHB Config register.
void dwc_otg_enable_common_interrupts (dwc_otg_core_if_t *core_if)
 This function initializes the commmon interrupts, used in both device and host modes.
+-static void init_fslspclksel (dwc_otg_core_if_t *core_if)
 This function initializes the commmon interrupts, used in both device and host modes.
++int dwc_otg_device_hibernation_restore (dwc_otg_core_if_t *core_if, int rem_wakeup, int reset)
++int dwc_otg_host_hibernation_restore (dwc_otg_core_if_t *core_if, int rem_wakeup, int reset)
++int dwc_otg_save_global_regs (dwc_otg_core_if_t *core_if)
 Saves global register values into system memory.
++int dwc_otg_save_gintmsk_reg (dwc_otg_core_if_t *core_if)
 Saves GINTMSK register before setting the msk bits.
++int dwc_otg_save_dev_regs (dwc_otg_core_if_t *core_if)
 Saves device register values into system memory.
++int dwc_otg_save_host_regs (dwc_otg_core_if_t *core_if)
 Saves host register values into system memory.
++int dwc_otg_restore_global_regs (dwc_otg_core_if_t *core_if)
 Restore global register values.
++int dwc_otg_restore_dev_regs (dwc_otg_core_if_t *core_if, int rem_wakeup)
 Restore device register values.
++int dwc_otg_restore_host_regs (dwc_otg_core_if_t *core_if, int reset)
 Restore host register values.
++int restore_lpm_i2c_regs (dwc_otg_core_if_t *core_if)
++int restore_essential_regs (dwc_otg_core_if_t *core_if, int rmode, int is_host)
++void init_fslspclksel (dwc_otg_core_if_t *core_if)
 Initializes the FSLSPClkSel field of the HCFG register depending on the PHY type.
+-static void init_devspd (dwc_otg_core_if_t *core_if)
++void init_devspd (dwc_otg_core_if_t *core_if)
 Initializes the DevSpd field of the DCFG register depending on the PHY type and the enumeration speed of the device.
static uint32_t calc_num_in_eps (dwc_otg_core_if_t *core_if)
uint32_t calc_num_in_eps (dwc_otg_core_if_t *core_if)
 This function calculates the number of IN EPS using GHWCFG1 and GHWCFG2 registers values.
uint32_t calc_num_out_eps (dwc_otg_core_if_t *core_if)
 This function calculates the number of OUT EPS using GHWCFG1 and GHWCFG2 registers values.
void dwc_otg_core_init (dwc_otg_core_if_t *core_if)
 This function initializes the DWC_otg controller registers and prepares the core for device mode or host mode operation.
void dwc_otg_enable_device_interrupts (dwc_otg_core_if_t *core_if)
 This function calculates the number of IN EPS using GHWCFG1 and GHWCFG2 registers values.
static uint32_t calc_num_out_eps (dwc_otg_core_if_t *core_if)
 This function enables the Device mode interrupts.
void dwc_otg_core_dev_init (dwc_otg_core_if_t *core_if)
 This function calculates the number of OUT EPS using GHWCFG1 and GHWCFG2 registers values.
void dwc_otg_core_init (dwc_otg_core_if_t *core_if)
 This function initializes the DWC_otg controller registers for device mode.
void dwc_otg_enable_host_interrupts (dwc_otg_core_if_t *core_if)
 This function initializes the DWC_otg controller registers and prepares the core for device mode or host mode operation.
void dwc_otg_enable_device_interrupts (dwc_otg_core_if_t *core_if)
 This function enables the Host mode interrupts.
void dwc_otg_disable_host_interrupts (dwc_otg_core_if_t *core_if)
 This function enables the Device mode interrupts.
void dwc_otg_core_dev_init (dwc_otg_core_if_t *core_if)
 This function disables the Host Mode interrupts.
void dwc_otg_core_host_init (dwc_otg_core_if_t *core_if)
 This function initializes the DWC_otg controller registers for device mode.
void dwc_otg_enable_host_interrupts (dwc_otg_core_if_t *core_if)
 This function initializes the DWC_otg controller registers for host mode.
void dwc_otg_hc_init (dwc_otg_core_if_t *core_if, dwc_hc_t *hc)
 This function enables the Host mode interrupts.
void dwc_otg_disable_host_interrupts (dwc_otg_core_if_t *core_if)
 Prepares a host channel for transferring packets to/from a specific endpoint.
void dwc_otg_hc_halt (dwc_otg_core_if_t *core_if, dwc_hc_t *hc, dwc_otg_halt_status_e halt_status)
 This function disables the Host Mode interrupts.
void dwc_otg_core_host_init (dwc_otg_core_if_t *core_if)
 Attempts to halt a host channel.
void dwc_otg_hc_cleanup (dwc_otg_core_if_t *core_if, dwc_hc_t *hc)
 This function initializes the DWC_otg controller registers for host mode.
void dwc_otg_hc_init (dwc_otg_core_if_t *core_if, dwc_hc_t *hc)
 Clears the transfer state for a host channel.
void hc_set_even_odd_frame (dwc_otg_core_if_t *core_if, dwc_hc_t *hc, hcchar_data_t *hcchar)
 Prepares a host channel for transferring packets to/from a specific endpoint.
void dwc_otg_hc_halt (dwc_otg_core_if_t *core_if, dwc_hc_t *hc, dwc_otg_halt_status_e halt_status)
 Sets the channel property that indicates in which frame a periodic transfer should occur.
++void ep_xfer_timeout (void *ptr)
 Attempts to halt a host channel.
void dwc_otg_hc_cleanup (dwc_otg_core_if_t *core_if, dwc_hc_t *hc)
++void set_pid_isoc (dwc_hc_t *hc)
 Clears the transfer state for a host channel.
static void hc_set_even_odd_frame (dwc_otg_core_if_t *core_if, dwc_hc_t *hc, hcchar_data_t *hcchar)
void dwc_otg_hc_start_transfer (dwc_otg_core_if_t *core_if, dwc_hc_t *hc)
 Sets the channel property that indicates in which frame a periodic transfer should occur.
+-void set_pid_isoc (dwc_hc_t *hc)
 This function does the setup for a data transfer for a host channel and starts the transfer.
void dwc_otg_hc_start_transfer_ddma (dwc_otg_core_if_t *core_if, dwc_hc_t *hc)
void dwc_otg_hc_start_transfer (dwc_otg_core_if_t *core_if, dwc_hc_t *hc)
 This function does the setup for a data transfer for a host channel and starts the transfer in Descriptor DMA mode.
int dwc_otg_hc_continue_transfer (dwc_otg_core_if_t *core_if, dwc_hc_t *hc)
 This function does the setup for a data transfer for a host channel and starts the transfer.
void dwc_otg_hc_start_transfer_ddma (dwc_otg_core_if_t *core_if, dwc_hc_t *hc)
 This function continues a data transfer that was started by previous call to dwc_otg_hc_start_transfer.
void dwc_otg_hc_do_ping (dwc_otg_core_if_t *core_if, dwc_hc_t *hc)
 This function does the setup for a data transfer for a host channel and starts the transfer in Descriptor DMA mode.
int dwc_otg_hc_continue_transfer (dwc_otg_core_if_t *core_if, dwc_hc_t *hc)
 Starts a PING transfer.
++void dwc_otg_hc_write_packet (dwc_otg_core_if_t *core_if, dwc_hc_t *hc)
 This function continues a data transfer that was started by previous call to dwc_otg_hc_start_transfer.
void dwc_otg_hc_do_ping (dwc_otg_core_if_t *core_if, dwc_hc_t *hc)
uint32_t dwc_otg_get_frame_number (dwc_otg_core_if_t *core_if)
 Starts a PING transfer.
+-void dwc_otg_hc_write_packet (dwc_otg_core_if_t *core_if, dwc_hc_t *hc)
 Gets the current USB frame number.
++uint32_t calc_frame_interval (dwc_otg_core_if_t *core_if)
uint32_t dwc_otg_get_frame_number (dwc_otg_core_if_t *core_if)
 Calculates and gets the frame Interval value of HFIR register according PHY type and speed.The application can modify a value of HFIR register only after the Port Enable bit of the Host Port Control and Status register (HPRT.PrtEnaPort) has been set.
void dwc_otg_read_setup_packet (dwc_otg_core_if_t *core_if, uint32_t *dest)
 Gets the current USB frame number.
void dwc_otg_read_setup_packet (dwc_otg_core_if_t *core_if, uint32_t *dest)
 This function reads a setup packet from the Rx FIFO into the destination buffer.
void dwc_otg_ep0_activate (dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
 This function reads a setup packet from the Rx FIFO into the destination buffer.
void dwc_otg_ep0_activate (dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
 This function enables EP0 OUT to receive SETUP packets and configures EP0 IN for transmitting packets.
void dwc_otg_ep_activate (dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
 This function enables EP0 OUT to receive SETUP packets and configures EP0 IN for transmitting packets.
void dwc_otg_ep_activate (dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
 This function activates an EP.
void dwc_otg_ep_deactivate (dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
 This function activates an EP.
void dwc_otg_ep_deactivate (dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
 This function deactivates an EP.
void init_dma_desc_chain (dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
 This function deactivates an EP.
static void init_dma_desc_chain (dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
 This function initializes dma descriptor chain.
++int32_t write_isoc_tx_fifo (dwc_otg_core_if_t *core_if, dwc_ep_t *dwc_ep)
 This function initializes dma descriptor chain.
void dwc_otg_ep_start_transfer (dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
 This function is called when to write ISOC data into appropriate dedicated periodic FIFO.
void dwc_otg_ep_start_transfer (dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
 This function does the setup for a data transfer for an EP and starts the transfer.
void dwc_otg_ep_start_zl_transfer (dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
 This function does the setup for a data transfer for an EP and starts the transfer.
void dwc_otg_ep_start_zl_transfer (dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
 This function setup a zero length transfer in Buffer DMA and Slave modes for usb requests with zero field set.
void dwc_otg_ep0_start_transfer (dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
 This function setup a zero length transfer in Buffer DMA and Slave modes for usb requests with zero field set.
void dwc_otg_ep0_start_transfer (dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
 This function does the setup for a data transfer for EP0 and starts the transfer.
void dwc_otg_ep0_continue_transfer (dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
 This function does the setup for a data transfer for EP0 and starts the transfer.
void dwc_otg_ep0_continue_transfer (dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
 This function continues control IN transfers started by dwc_otg_ep0_start_transfer, when the transfer does not fit in a single packet.
+-static void dump_msg (const u8 *buf, unsigned int length)
 This function continues control IN transfers started by dwc_otg_ep0_start_transfer, when the transfer does not fit in a single packet.
++void dump_msg (const u8 *buf, unsigned int length)
void dwc_otg_ep_write_packet (dwc_otg_core_if_t *core_if, dwc_ep_t *ep, int dma)
void dwc_otg_ep_write_packet (dwc_otg_core_if_t *core_if, dwc_ep_t *ep, int dma)
 This function writes a packet into the Tx FIFO associated with the EP.
void dwc_otg_ep_set_stall (dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
 This function writes a packet into the Tx FIFO associated with the EP.
void dwc_otg_ep_set_stall (dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
 Set the EP STALL.
void dwc_otg_ep_clear_stall (dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
 Set the EP STALL.
void dwc_otg_ep_clear_stall (dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
 Clear the EP STALL.
void dwc_otg_read_packet (dwc_otg_core_if_t *core_if, uint8_t *dest, uint16_t bytes)
 Clear the EP STALL.
void dwc_otg_read_packet (dwc_otg_core_if_t *core_if, uint8_t *dest, uint16_t bytes)
 This function reads a packet from the Rx FIFO into the destination buffer.
void dwc_otg_dump_dev_registers (dwc_otg_core_if_t *core_if)
 This function reads a packet from the Rx FIFO into the destination buffer.
void dwc_otg_dump_dev_registers (dwc_otg_core_if_t *core_if)
 Dump core registers and SPRAM.
void dwc_otg_dump_spram (dwc_otg_core_if_t *core_if)
 Dump core registers and SPRAM.
void dwc_otg_dump_spram (dwc_otg_core_if_t *core_if)
 This functions reads the SPRAM and prints its content.
void dwc_otg_dump_host_registers (dwc_otg_core_if_t *core_if)
 This functions reads the SPRAM and prints its content.
void dwc_otg_dump_host_registers (dwc_otg_core_if_t *core_if)
 This function reads the host registers and prints them.
void dwc_otg_dump_global_registers (dwc_otg_core_if_t *core_if)
 This function reads the host registers and prints them.
void dwc_otg_dump_global_registers (dwc_otg_core_if_t *core_if)
 This function reads the core global registers and prints them.
void dwc_otg_flush_tx_fifo (dwc_otg_core_if_t *core_if, const int num)
 This function reads the core global registers and prints them.
void dwc_otg_flush_tx_fifo (dwc_otg_core_if_t *core_if, const int num)
 Flush a Tx FIFO.
void dwc_otg_flush_rx_fifo (dwc_otg_core_if_t *core_if)
 Flush a Tx FIFO.
void dwc_otg_flush_rx_fifo (dwc_otg_core_if_t *core_if)
 Flush Rx FIFO.
void dwc_otg_core_reset (dwc_otg_core_if_t *core_if)
 Flush Rx FIFO.
void dwc_otg_core_reset (dwc_otg_core_if_t *core_if)
 Do core a soft reset of the core.
+-uint8_t dwc_otg_is_device_mode (dwc_otg_core_if_t *_core_if)
 Do core a soft reset of the core.
++uint8_t dwc_otg_is_device_mode (dwc_otg_core_if_t *_core_if)
+-uint8_t dwc_otg_is_host_mode (dwc_otg_core_if_t *_core_if)
++uint8_t dwc_otg_is_host_mode (dwc_otg_core_if_t *_core_if)
void dwc_otg_cil_register_hcd_callbacks (dwc_otg_core_if_t *core_if, dwc_otg_cil_callbacks_t *cb, void *p)
void dwc_otg_cil_register_hcd_callbacks (dwc_otg_core_if_t *core_if, dwc_otg_cil_callbacks_t *cb, void *p)
 Register HCD callbacks.
void dwc_otg_cil_register_pcd_callbacks (dwc_otg_core_if_t *core_if, dwc_otg_cil_callbacks_t *cb, void *p)
 Register HCD callbacks.
void dwc_otg_cil_register_pcd_callbacks (dwc_otg_core_if_t *core_if, dwc_otg_cil_callbacks_t *cb, void *p)
 Register PCD callbacks.
void write_isoc_frame_data (dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
 Register PCD callbacks.
void write_isoc_frame_data (dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
 This function writes isoc data per 1 (micro)frame into tx fifo.
void dwc_otg_iso_ep_start_frm_transfer (dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
 This function writes isoc data per 1 (micro)frame into tx fifo.
void dwc_otg_iso_ep_start_frm_transfer (dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
 This function initializes a descriptor chain for Isochronous transfer.
+-static void dwc_otg_set_uninitialized (int32_t *p, int size)
 This function initializes a descriptor chain for Isochronous transfer.
++void dwc_otg_set_uninitialized (int32_t *p, int size)
+-static int dwc_otg_param_initialized (int32_t val)
++int dwc_otg_param_initialized (int32_t val)
+-uint8_t dwc_otg_is_dma_enable (dwc_otg_core_if_t *core_if)
++uint8_t dwc_otg_is_dma_enable (dwc_otg_core_if_t *core_if)
int dwc_otg_set_param_otg_cap (dwc_otg_core_if_t *core_if, int32_t val)
int dwc_otg_set_param_otg_cap (dwc_otg_core_if_t *core_if, int32_t val)
 Specifies the OTG capabilities.
+-int32_t dwc_otg_get_param_otg_cap (dwc_otg_core_if_t *core_if)
 Specifies the OTG capabilities.
++int32_t dwc_otg_get_param_otg_cap (dwc_otg_core_if_t *core_if)
+-int dwc_otg_set_param_opt (dwc_otg_core_if_t *core_if, int32_t val)
++int dwc_otg_set_param_opt (dwc_otg_core_if_t *core_if, int32_t val)
+-int32_t dwc_otg_get_param_opt (dwc_otg_core_if_t *core_if)
++int32_t dwc_otg_get_param_opt (dwc_otg_core_if_t *core_if)
int dwc_otg_set_param_dma_enable (dwc_otg_core_if_t *core_if, int32_t val)
int dwc_otg_set_param_dma_enable (dwc_otg_core_if_t *core_if, int32_t val)
 Specifies whether to use slave or DMA mode for accessing the data FIFOs.
+-int32_t dwc_otg_get_param_dma_enable (dwc_otg_core_if_t *core_if)
 Specifies whether to use slave or DMA mode for accessing the data FIFOs.
++int32_t dwc_otg_get_param_dma_enable (dwc_otg_core_if_t *core_if)
int dwc_otg_set_param_dma_desc_enable (dwc_otg_core_if_t *core_if, int32_t val)
int dwc_otg_set_param_dma_desc_enable (dwc_otg_core_if_t *core_if, int32_t val)
 When DMA mode is enabled specifies whether to use address DMA or DMA Descritor mode for accessing the data FIFOs in device mode.
+-int32_t dwc_otg_get_param_dma_desc_enable (dwc_otg_core_if_t *core_if)
 When DMA mode is enabled specifies whether to use address DMA or DMA Descritor mode for accessing the data FIFOs in device mode.
++int32_t dwc_otg_get_param_dma_desc_enable (dwc_otg_core_if_t *core_if)
int dwc_otg_set_param_host_support_fs_ls_low_power (dwc_otg_core_if_t *core_if, int32_t val)
int dwc_otg_set_param_host_support_fs_ls_low_power (dwc_otg_core_if_t *core_if, int32_t val)
 Specifies whether low power mode is supported when attached to a Full Speed or Low Speed device in host mode.
+-int32_t dwc_otg_get_param_host_support_fs_ls_low_power (dwc_otg_core_if_t *core_if)
 Specifies whether low power mode is supported when attached to a Full Speed or Low Speed device in host mode.
++int32_t dwc_otg_get_param_host_support_fs_ls_low_power (dwc_otg_core_if_t *core_if)
+-int dwc_otg_set_param_enable_dynamic_fifo (dwc_otg_core_if_t *core_if, int32_t val)
++int dwc_otg_set_param_enable_dynamic_fifo (dwc_otg_core_if_t *core_if, int32_t val)
 0 - Use cC FIFO size parameters 1 - Allow dynamic FIFO sizing (default)
+-int32_t dwc_otg_get_param_enable_dynamic_fifo (dwc_otg_core_if_t *core_if)
++int32_t dwc_otg_get_param_enable_dynamic_fifo (dwc_otg_core_if_t *core_if)
int dwc_otg_set_param_data_fifo_size (dwc_otg_core_if_t *core_if, int32_t val)
int dwc_otg_set_param_data_fifo_size (dwc_otg_core_if_t *core_if, int32_t val)
 Total number of 4-byte words in the data FIFO memory.
+-int32_t dwc_otg_get_param_data_fifo_size (dwc_otg_core_if_t *core_if)
 Total number of 4-byte words in the data FIFO memory.
++int32_t dwc_otg_get_param_data_fifo_size (dwc_otg_core_if_t *core_if)
int dwc_otg_set_param_dev_rx_fifo_size (dwc_otg_core_if_t *core_if, int32_t val)
int dwc_otg_set_param_dev_rx_fifo_size (dwc_otg_core_if_t *core_if, int32_t val)
 Number of 4-byte words in the Rx FIFO in device mode when dynamic FIFO sizing is enabled.
+-int32_t dwc_otg_get_param_dev_rx_fifo_size (dwc_otg_core_if_t *core_if)
 Number of 4-byte words in the Rx FIFO in device mode when dynamic FIFO sizing is enabled.
++int32_t dwc_otg_get_param_dev_rx_fifo_size (dwc_otg_core_if_t *core_if)
int dwc_otg_set_param_dev_nperio_tx_fifo_size (dwc_otg_core_if_t *core_if, int32_t val)
int dwc_otg_set_param_dev_nperio_tx_fifo_size (dwc_otg_core_if_t *core_if, int32_t val)
 Number of 4-byte words in the non-periodic Tx FIFO in device mode when dynamic FIFO sizing is enabled.
+-int32_t dwc_otg_get_param_dev_nperio_tx_fifo_size (dwc_otg_core_if_t *core_if)
 Number of 4-byte words in the non-periodic Tx FIFO in device mode when dynamic FIFO sizing is enabled.
++int32_t dwc_otg_get_param_dev_nperio_tx_fifo_size (dwc_otg_core_if_t *core_if)
int dwc_otg_set_param_host_rx_fifo_size (dwc_otg_core_if_t *core_if, int32_t val)
int dwc_otg_set_param_host_rx_fifo_size (dwc_otg_core_if_t *core_if, int32_t val)
 Number of 4-byte words in the Rx FIFO in host mode when dynamic FIFO sizing is enabled.
+-int32_t dwc_otg_get_param_host_rx_fifo_size (dwc_otg_core_if_t *core_if)
 Number of 4-byte words in the Rx FIFO in host mode when dynamic FIFO sizing is enabled.
++int32_t dwc_otg_get_param_host_rx_fifo_size (dwc_otg_core_if_t *core_if)
int dwc_otg_set_param_host_nperio_tx_fifo_size (dwc_otg_core_if_t *core_if, int32_t val)
int dwc_otg_set_param_host_nperio_tx_fifo_size (dwc_otg_core_if_t *core_if, int32_t val)
 Number of 4-byte words in the non-periodic Tx FIFO in host mode when Dynamic FIFO sizing is enabled in the core.
+-int32_t dwc_otg_get_param_host_nperio_tx_fifo_size (dwc_otg_core_if_t *core_if)
 Number of 4-byte words in the non-periodic Tx FIFO in host mode when Dynamic FIFO sizing is enabled in the core.
++int32_t dwc_otg_get_param_host_nperio_tx_fifo_size (dwc_otg_core_if_t *core_if)
int dwc_otg_set_param_host_perio_tx_fifo_size (dwc_otg_core_if_t *core_if, int32_t val)
int dwc_otg_set_param_host_perio_tx_fifo_size (dwc_otg_core_if_t *core_if, int32_t val)
 Number of 4-byte words in the host periodic Tx FIFO when dynamic FIFO sizing is enabled.
+-int32_t dwc_otg_get_param_host_perio_tx_fifo_size (dwc_otg_core_if_t *core_if)
 Number of 4-byte words in the host periodic Tx FIFO when dynamic FIFO sizing is enabled.
++int32_t dwc_otg_get_param_host_perio_tx_fifo_size (dwc_otg_core_if_t *core_if)
int dwc_otg_set_param_max_transfer_size (dwc_otg_core_if_t *core_if, int32_t val)
int dwc_otg_set_param_max_transfer_size (dwc_otg_core_if_t *core_if, int32_t val)
 The maximum transfer size supported in bytes.
+-int32_t dwc_otg_get_param_max_transfer_size (dwc_otg_core_if_t *core_if)
 The maximum transfer size supported in bytes.
++int32_t dwc_otg_get_param_max_transfer_size (dwc_otg_core_if_t *core_if)
int dwc_otg_set_param_max_packet_count (dwc_otg_core_if_t *core_if, int32_t val)
int dwc_otg_set_param_max_packet_count (dwc_otg_core_if_t *core_if, int32_t val)
 The maximum number of packets in a transfer.
+-int32_t dwc_otg_get_param_max_packet_count (dwc_otg_core_if_t *core_if)
 The maximum number of packets in a transfer.
++int32_t dwc_otg_get_param_max_packet_count (dwc_otg_core_if_t *core_if)
int dwc_otg_set_param_host_channels (dwc_otg_core_if_t *core_if, int32_t val)
int dwc_otg_set_param_host_channels (dwc_otg_core_if_t *core_if, int32_t val)
 The number of host channel registers to use.
+-int32_t dwc_otg_get_param_host_channels (dwc_otg_core_if_t *core_if)
 The number of host channel registers to use.
++int32_t dwc_otg_get_param_host_channels (dwc_otg_core_if_t *core_if)
int dwc_otg_set_param_dev_endpoints (dwc_otg_core_if_t *core_if, int32_t val)
int dwc_otg_set_param_dev_endpoints (dwc_otg_core_if_t *core_if, int32_t val)
 The number of endpoints in addition to EP0 available for device mode operations.
+-int32_t dwc_otg_get_param_dev_endpoints (dwc_otg_core_if_t *core_if)
 The number of endpoints in addition to EP0 available for device mode operations.
++int32_t dwc_otg_get_param_dev_endpoints (dwc_otg_core_if_t *core_if)
int dwc_otg_set_param_phy_type (dwc_otg_core_if_t *core_if, int32_t val)
int dwc_otg_set_param_phy_type (dwc_otg_core_if_t *core_if, int32_t val)
 Specifies the type of PHY interface to use.
+-int32_t dwc_otg_get_param_phy_type (dwc_otg_core_if_t *core_if)
 Specifies the type of PHY interface to use.
++int32_t dwc_otg_get_param_phy_type (dwc_otg_core_if_t *core_if)
int dwc_otg_set_param_speed (dwc_otg_core_if_t *core_if, int32_t val)
int dwc_otg_set_param_speed (dwc_otg_core_if_t *core_if, int32_t val)
 Specifies the maximum speed of operation in host and device mode.
+-int32_t dwc_otg_get_param_speed (dwc_otg_core_if_t *core_if)
 Specifies the maximum speed of operation in host and device mode.
++int32_t dwc_otg_get_param_speed (dwc_otg_core_if_t *core_if)
int dwc_otg_set_param_host_ls_low_power_phy_clk (dwc_otg_core_if_t *core_if, int32_t val)
int dwc_otg_set_param_host_ls_low_power_phy_clk (dwc_otg_core_if_t *core_if, int32_t val)
 Specifies the PHY clock rate in low power mode when connected to a Low Speed device in host mode.
+-int32_t dwc_otg_get_param_host_ls_low_power_phy_clk (dwc_otg_core_if_t *core_if)
 Specifies the PHY clock rate in low power mode when connected to a Low Speed device in host mode.
++int32_t dwc_otg_get_param_host_ls_low_power_phy_clk (dwc_otg_core_if_t *core_if)
int dwc_otg_set_param_phy_ulpi_ddr (dwc_otg_core_if_t *core_if, int32_t val)
int dwc_otg_set_param_phy_ulpi_ddr (dwc_otg_core_if_t *core_if, int32_t val)
 Specifies whether the ULPI operates at double or single data rate.
+-int32_t dwc_otg_get_param_phy_ulpi_ddr (dwc_otg_core_if_t *core_if)
 Specifies whether the ULPI operates at double or single data rate.
++int32_t dwc_otg_get_param_phy_ulpi_ddr (dwc_otg_core_if_t *core_if)
+-int dwc_otg_set_param_phy_ulpi_ext_vbus (dwc_otg_core_if_t *core_if, int32_t val)
++int dwc_otg_set_param_phy_ulpi_ext_vbus (dwc_otg_core_if_t *core_if, int32_t val)
 Specifies whether to use the internal or external supply to drive the vbus with a ULPI phy.
+-int32_t dwc_otg_get_param_phy_ulpi_ext_vbus (dwc_otg_core_if_t *core_if)
++int32_t dwc_otg_get_param_phy_ulpi_ext_vbus (dwc_otg_core_if_t *core_if)
int dwc_otg_set_param_phy_utmi_width (dwc_otg_core_if_t *core_if, int32_t val)
int dwc_otg_set_param_phy_utmi_width (dwc_otg_core_if_t *core_if, int32_t val)
 Specifies the UTMI+ Data Width.
+-int32_t dwc_otg_get_param_phy_utmi_width (dwc_otg_core_if_t *core_if)
 Specifies the UTMI+ Data Width.
++int32_t dwc_otg_get_param_phy_utmi_width (dwc_otg_core_if_t *core_if)
+-int dwc_otg_set_param_ulpi_fs_ls (dwc_otg_core_if_t *core_if, int32_t val)
++int dwc_otg_set_param_ulpi_fs_ls (dwc_otg_core_if_t *core_if, int32_t val)
+-int32_t dwc_otg_get_param_ulpi_fs_ls (dwc_otg_core_if_t *core_if)
++int32_t dwc_otg_get_param_ulpi_fs_ls (dwc_otg_core_if_t *core_if)
+-int dwc_otg_set_param_ts_dline (dwc_otg_core_if_t *core_if, int32_t val)
++int dwc_otg_set_param_ts_dline (dwc_otg_core_if_t *core_if, int32_t val)
+-int32_t dwc_otg_get_param_ts_dline (dwc_otg_core_if_t *core_if)
++int32_t dwc_otg_get_param_ts_dline (dwc_otg_core_if_t *core_if)
int dwc_otg_set_param_i2c_enable (dwc_otg_core_if_t *core_if, int32_t val)
int dwc_otg_set_param_i2c_enable (dwc_otg_core_if_t *core_if, int32_t val)
 Specifies whether to use the I2Cinterface for full speed PHY.
+-int32_t dwc_otg_get_param_i2c_enable (dwc_otg_core_if_t *core_if)
 Specifies whether to use the I2Cinterface for full speed PHY.
++int32_t dwc_otg_get_param_i2c_enable (dwc_otg_core_if_t *core_if)
int dwc_otg_set_param_dev_perio_tx_fifo_size (dwc_otg_core_if_t *core_if, int32_t val, int fifo_num)
int dwc_otg_set_param_dev_perio_tx_fifo_size (dwc_otg_core_if_t *core_if, int32_t val, int fifo_num)
 Number of 4-byte words in each of the periodic Tx FIFOs in device mode when dynamic FIFO sizing is enabled.
+-int32_t dwc_otg_get_param_dev_perio_tx_fifo_size (dwc_otg_core_if_t *core_if, int fifo_num)
 Number of 4-byte words in each of the periodic Tx FIFOs in device mode when dynamic FIFO sizing is enabled.
++int32_t dwc_otg_get_param_dev_perio_tx_fifo_size (dwc_otg_core_if_t *core_if, int fifo_num)
+-int dwc_otg_set_param_en_multiple_tx_fifo (dwc_otg_core_if_t *core_if, int32_t val)
++int dwc_otg_set_param_en_multiple_tx_fifo (dwc_otg_core_if_t *core_if, int32_t val)
 Specifies whether dedicated transmit FIFOs are enabled for non periodic IN endpoints in device mode 0 - No 1 - Yes.
+-int32_t dwc_otg_get_param_en_multiple_tx_fifo (dwc_otg_core_if_t *core_if)
++int32_t dwc_otg_get_param_en_multiple_tx_fifo (dwc_otg_core_if_t *core_if)
+-int dwc_otg_set_param_dev_tx_fifo_size (dwc_otg_core_if_t *core_if, int32_t val, int fifo_num)
++int dwc_otg_set_param_dev_tx_fifo_size (dwc_otg_core_if_t *core_if, int32_t val, int fifo_num)
+-int32_t dwc_otg_get_param_dev_tx_fifo_size (dwc_otg_core_if_t *core_if, int fifo_num)
++int32_t dwc_otg_get_param_dev_tx_fifo_size (dwc_otg_core_if_t *core_if, int fifo_num)
+-int dwc_otg_set_param_thr_ctl (dwc_otg_core_if_t *core_if, int32_t val)
++int dwc_otg_set_param_thr_ctl (dwc_otg_core_if_t *core_if, int32_t val)
 Thresholding enable flag- bit 0 - enable non-ISO Tx thresholding bit 1 - enable ISO Tx thresholding bit 2 - enable Rx thresholding.
+-int32_t dwc_otg_get_param_thr_ctl (dwc_otg_core_if_t *core_if)
++int32_t dwc_otg_get_param_thr_ctl (dwc_otg_core_if_t *core_if)
+-int dwc_otg_set_param_lpm_enable (dwc_otg_core_if_t *core_if, int32_t val)
++int dwc_otg_set_param_lpm_enable (dwc_otg_core_if_t *core_if, int32_t val)
 Specifies whether LPM (Link Power Management) support is enabled.
+-int32_t dwc_otg_get_param_lpm_enable (dwc_otg_core_if_t *core_if)
++int32_t dwc_otg_get_param_lpm_enable (dwc_otg_core_if_t *core_if)
+-int dwc_otg_set_param_tx_thr_length (dwc_otg_core_if_t *core_if, int32_t val)
++int dwc_otg_set_param_tx_thr_length (dwc_otg_core_if_t *core_if, int32_t val)
 Thresholding length for Tx FIFOs in 32 bit DWORDs.
+-int32_t dwc_otg_get_param_tx_thr_length (dwc_otg_core_if_t *core_if)
++int32_t dwc_otg_get_param_tx_thr_length (dwc_otg_core_if_t *core_if)
+-int dwc_otg_set_param_rx_thr_length (dwc_otg_core_if_t *core_if, int32_t val)
++int dwc_otg_set_param_rx_thr_length (dwc_otg_core_if_t *core_if, int32_t val)
 Thresholding length for Rx FIFOs in 32 bit DWORDs.
+-int32_t dwc_otg_get_param_rx_thr_length (dwc_otg_core_if_t *core_if)
++int32_t dwc_otg_get_param_rx_thr_length (dwc_otg_core_if_t *core_if)
int dwc_otg_set_param_dma_burst_size (dwc_otg_core_if_t *core_if, int32_t val)
int dwc_otg_set_param_dma_burst_size (dwc_otg_core_if_t *core_if, int32_t val)
 The DMA Burst size (applicable only for External DMA Mode).
+-int32_t dwc_otg_get_param_dma_burst_size (dwc_otg_core_if_t *core_if)
 The DMA Burst size (applicable only for External DMA Mode).
++int32_t dwc_otg_get_param_dma_burst_size (dwc_otg_core_if_t *core_if)
+-int dwc_otg_set_param_pti_enable (dwc_otg_core_if_t *core_if, int32_t val)
++int dwc_otg_set_param_pti_enable (dwc_otg_core_if_t *core_if, int32_t val)
 Specifies whether PTI enhancement is enabled.
+-int32_t dwc_otg_get_param_pti_enable (dwc_otg_core_if_t *core_if)
++int32_t dwc_otg_get_param_pti_enable (dwc_otg_core_if_t *core_if)
+-int dwc_otg_set_param_mpi_enable (dwc_otg_core_if_t *core_if, int32_t val)
++int dwc_otg_set_param_mpi_enable (dwc_otg_core_if_t *core_if, int32_t val)
 Specifies whether MPI enhancement is enabled.
+-int32_t dwc_otg_get_param_mpi_enable (dwc_otg_core_if_t *core_if)
++int32_t dwc_otg_get_param_mpi_enable (dwc_otg_core_if_t *core_if)
+-int dwc_otg_set_param_ic_usb_cap (dwc_otg_core_if_t *core_if, int32_t val)
++int dwc_otg_set_param_adp_enable (dwc_otg_core_if_t *core_if, int32_t val)
 Specifies whether ADP capability is enabled.
++int32_t dwc_otg_get_param_adp_enable (dwc_otg_core_if_t *core_if)
++int dwc_otg_set_param_ic_usb_cap (dwc_otg_core_if_t *core_if, int32_t val)
 Specifies whether IC_USB capability is enabled.
+-int32_t dwc_otg_get_param_ic_usb_cap (dwc_otg_core_if_t *core_if)
++int32_t dwc_otg_get_param_ic_usb_cap (dwc_otg_core_if_t *core_if)
++int dwc_otg_set_param_ahb_thr_ratio (dwc_otg_core_if_t *core_if, int32_t val)
++int32_t dwc_otg_get_param_ahb_thr_ratio (dwc_otg_core_if_t *core_if)
++int dwc_otg_set_param_power_down (dwc_otg_core_if_t *core_if, int32_t val)
++int32_t dwc_otg_get_param_power_down (dwc_otg_core_if_t *core_if)
++int dwc_otg_set_param_reload_ctl (dwc_otg_core_if_t *core_if, int32_t val)
++int32_t dwc_otg_get_param_reload_ctl (dwc_otg_core_if_t *core_if)
++int dwc_otg_set_param_dev_out_nak (dwc_otg_core_if_t *core_if, int32_t val)
++int32_t dwc_otg_get_param_dev_out_nak (dwc_otg_core_if_t *core_if)
++int dwc_otg_set_param_cont_on_bna (dwc_otg_core_if_t *core_if, int32_t val)
++int32_t dwc_otg_get_param_cont_on_bna (dwc_otg_core_if_t *core_if)
++int dwc_otg_set_param_ahb_single (dwc_otg_core_if_t *core_if, int32_t val)
++int32_t dwc_otg_get_param_ahb_single (dwc_otg_core_if_t *core_if)
+-int dwc_otg_set_param_ahb_thr_ratio (dwc_otg_core_if_t *core_if, int32_t val)
++int dwc_otg_set_param_otg_ver (dwc_otg_core_if_t *core_if, int32_t val)
+-int32_t dwc_otg_get_param_ahb_thr_ratio (dwc_otg_core_if_t *core_if)
++int32_t dwc_otg_get_param_otg_ver (dwc_otg_core_if_t *core_if)
+-uint32_t dwc_otg_get_hnpstatus (dwc_otg_core_if_t *core_if)
++uint32_t dwc_otg_get_hnpstatus (dwc_otg_core_if_t *core_if)
 Get host negotiation status.
+-uint32_t dwc_otg_get_srpstatus (dwc_otg_core_if_t *core_if)
++uint32_t dwc_otg_get_srpstatus (dwc_otg_core_if_t *core_if)
 Get srp status.
+-void dwc_otg_set_hnpreq (dwc_otg_core_if_t *core_if, uint32_t val)
++void dwc_otg_set_hnpreq (dwc_otg_core_if_t *core_if, uint32_t val)
 Set hnpreq bit in the GOTGCTL register.
+-uint32_t dwc_otg_get_gsnpsid (dwc_otg_core_if_t *core_if)
++uint32_t dwc_otg_get_gsnpsid (dwc_otg_core_if_t *core_if)
 Get Content of SNPSID register.
uint32_t dwc_otg_get_mode (dwc_otg_core_if_t *core_if)
uint32_t dwc_otg_get_mode (dwc_otg_core_if_t *core_if)
 Get current mode.
+-uint32_t dwc_otg_get_hnpcapable (dwc_otg_core_if_t *core_if)
 Get current mode.
++uint32_t dwc_otg_get_hnpcapable (dwc_otg_core_if_t *core_if)
 Get value of hnpcapable field in the GUSBCFG register.
+-void dwc_otg_set_hnpcapable (dwc_otg_core_if_t *core_if, uint32_t val)
++void dwc_otg_set_hnpcapable (dwc_otg_core_if_t *core_if, uint32_t val)
 Set value of hnpcapable field in the GUSBCFG register.
+-uint32_t dwc_otg_get_srpcapable (dwc_otg_core_if_t *core_if)
++uint32_t dwc_otg_get_srpcapable (dwc_otg_core_if_t *core_if)
 Get value of srpcapable field in the GUSBCFG register.
+-void dwc_otg_set_srpcapable (dwc_otg_core_if_t *core_if, uint32_t val)
++void dwc_otg_set_srpcapable (dwc_otg_core_if_t *core_if, uint32_t val)
 Set value of srpcapable field in the GUSBCFG register.
+-uint32_t dwc_otg_get_devspeed (dwc_otg_core_if_t *core_if)
++uint32_t dwc_otg_get_devspeed (dwc_otg_core_if_t *core_if)
 Get value of devspeed field in the DCFG register.
+-void dwc_otg_set_devspeed (dwc_otg_core_if_t *core_if, uint32_t val)
++void dwc_otg_set_devspeed (dwc_otg_core_if_t *core_if, uint32_t val)
 Set value of devspeed field in the DCFG register.
+-uint32_t dwc_otg_get_busconnected (dwc_otg_core_if_t *core_if)
++uint32_t dwc_otg_get_busconnected (dwc_otg_core_if_t *core_if)
 Get the value of busconnected field from the HPRT0 register.
+-uint32_t dwc_otg_get_enumspeed (dwc_otg_core_if_t *core_if)
++uint32_t dwc_otg_get_enumspeed (dwc_otg_core_if_t *core_if)
 Gets the device enumeration Speed.
+-uint32_t dwc_otg_get_prtpower (dwc_otg_core_if_t *core_if)
++uint32_t dwc_otg_get_prtpower (dwc_otg_core_if_t *core_if)
 Get value of prtpwr field from the HPRT0 register.
+-void dwc_otg_set_prtpower (dwc_otg_core_if_t *core_if, uint32_t val)
++uint32_t dwc_otg_get_core_state (dwc_otg_core_if_t *core_if)
 Get value of flag indicating core state - hibernated or not.
++void dwc_otg_set_prtpower (dwc_otg_core_if_t *core_if, uint32_t val)
 Set value of prtpwr field from the HPRT0 register.
+-uint32_t dwc_otg_get_prtsuspend (dwc_otg_core_if_t *core_if)
++uint32_t dwc_otg_get_prtsuspend (dwc_otg_core_if_t *core_if)
 Get value of prtsusp field from the HPRT0 regsiter.
+-void dwc_otg_set_prtsuspend (dwc_otg_core_if_t *core_if, uint32_t val)
++void dwc_otg_set_prtsuspend (dwc_otg_core_if_t *core_if, uint32_t val)
 Set value of prtpwr field from the HPRT0 register.
+-void dwc_otg_set_prtresume (dwc_otg_core_if_t *core_if, uint32_t val)
++uint32_t dwc_otg_get_fr_interval (dwc_otg_core_if_t *core_if)
 Get value of Fram Interval field from the HFIR regsiter.
++void dwc_otg_set_fr_interval (dwc_otg_core_if_t *core_if, uint32_t val)
 Set value of Frame Interval field from the HFIR regsiter.
++uint32_t dwc_otg_get_mode_ch_tim (dwc_otg_core_if_t *core_if)
 Get value of ModeChTimEn field from the HCFG regsiter.
++void dwc_otg_set_mode_ch_tim (dwc_otg_core_if_t *core_if, uint32_t val)
 Set value of ModeChTimEn field from the HCFG regsiter.
++void dwc_otg_set_prtresume (dwc_otg_core_if_t *core_if, uint32_t val)
 Set value of prtres field from the HPRT0 register FIXME Remove?
+-uint32_t dwc_otg_get_remotewakesig (dwc_otg_core_if_t *core_if)
++uint32_t dwc_otg_get_remotewakesig (dwc_otg_core_if_t *core_if)
 Get value of rmtwkupsig bit in DCTL register.
+-uint32_t dwc_otg_get_lpm_portsleepstatus (dwc_otg_core_if_t *core_if)
++uint32_t dwc_otg_get_lpm_portsleepstatus (dwc_otg_core_if_t *core_if)
 Get value of prt_sleep_sts field from the GLPMCFG register.
+-uint32_t dwc_otg_get_lpm_remotewakeenabled (dwc_otg_core_if_t *core_if)
++uint32_t dwc_otg_get_lpm_remotewakeenabled (dwc_otg_core_if_t *core_if)
 Get value of rem_wkup_en field from the GLPMCFG register.
+-uint32_t dwc_otg_get_lpmresponse (dwc_otg_core_if_t *core_if)
++uint32_t dwc_otg_get_lpmresponse (dwc_otg_core_if_t *core_if)
 Get value of appl_resp field from the GLPMCFG register.
+-void dwc_otg_set_lpmresponse (dwc_otg_core_if_t *core_if, uint32_t val)
++void dwc_otg_set_lpmresponse (dwc_otg_core_if_t *core_if, uint32_t val)
 Set value of appl_resp field from the GLPMCFG register.
+-uint32_t dwc_otg_get_hsic_connect (dwc_otg_core_if_t *core_if)
++uint32_t dwc_otg_get_hsic_connect (dwc_otg_core_if_t *core_if)
 Get value of hsic_connect field from the GLPMCFG register.
+-void dwc_otg_set_hsic_connect (dwc_otg_core_if_t *core_if, uint32_t val)
++void dwc_otg_set_hsic_connect (dwc_otg_core_if_t *core_if, uint32_t val)
 Set value of hsic_connect field from the GLPMCFG register.
+-uint32_t dwc_otg_get_inv_sel_hsic (dwc_otg_core_if_t *core_if)
++uint32_t dwc_otg_get_inv_sel_hsic (dwc_otg_core_if_t *core_if)
 Get value of inv_sel_hsic field from the GLPMCFG register.
+-void dwc_otg_set_inv_sel_hsic (dwc_otg_core_if_t *core_if, uint32_t val)
++void dwc_otg_set_inv_sel_hsic (dwc_otg_core_if_t *core_if, uint32_t val)
 Set value of inv_sel_hsic field from the GLPMFG register.
+-uint32_t dwc_otg_get_gotgctl (dwc_otg_core_if_t *core_if)
++uint32_t dwc_otg_get_gotgctl (dwc_otg_core_if_t *core_if)
 GOTGCTL register.
+-void dwc_otg_set_gotgctl (dwc_otg_core_if_t *core_if, uint32_t val)
++void dwc_otg_set_gotgctl (dwc_otg_core_if_t *core_if, uint32_t val)
+-uint32_t dwc_otg_get_gusbcfg (dwc_otg_core_if_t *core_if)
++uint32_t dwc_otg_get_gusbcfg (dwc_otg_core_if_t *core_if)
 GUSBCFG register.
+-void dwc_otg_set_gusbcfg (dwc_otg_core_if_t *core_if, uint32_t val)
++void dwc_otg_set_gusbcfg (dwc_otg_core_if_t *core_if, uint32_t val)
+-uint32_t dwc_otg_get_grxfsiz (dwc_otg_core_if_t *core_if)
++uint32_t dwc_otg_get_grxfsiz (dwc_otg_core_if_t *core_if)
 GRXFSIZ register.
+-void dwc_otg_set_grxfsiz (dwc_otg_core_if_t *core_if, uint32_t val)
++void dwc_otg_set_grxfsiz (dwc_otg_core_if_t *core_if, uint32_t val)
+-uint32_t dwc_otg_get_gnptxfsiz (dwc_otg_core_if_t *core_if)
++uint32_t dwc_otg_get_gnptxfsiz (dwc_otg_core_if_t *core_if)
 GNPTXFSIZ register.
+-void dwc_otg_set_gnptxfsiz (dwc_otg_core_if_t *core_if, uint32_t val)
++void dwc_otg_set_gnptxfsiz (dwc_otg_core_if_t *core_if, uint32_t val)
+-uint32_t dwc_otg_get_gpvndctl (dwc_otg_core_if_t *core_if)
++uint32_t dwc_otg_get_gpvndctl (dwc_otg_core_if_t *core_if)
+-void dwc_otg_set_gpvndctl (dwc_otg_core_if_t *core_if, uint32_t val)
++void dwc_otg_set_gpvndctl (dwc_otg_core_if_t *core_if, uint32_t val)
+-uint32_t dwc_otg_get_ggpio (dwc_otg_core_if_t *core_if)
++uint32_t dwc_otg_get_ggpio (dwc_otg_core_if_t *core_if)
 GGPIO register.
+-void dwc_otg_set_ggpio (dwc_otg_core_if_t *core_if, uint32_t val)
++void dwc_otg_set_ggpio (dwc_otg_core_if_t *core_if, uint32_t val)
+-uint32_t dwc_otg_get_hprt0 (dwc_otg_core_if_t *core_if)
++uint32_t dwc_otg_get_hprt0 (dwc_otg_core_if_t *core_if)
 HPRT0 register.
+-void dwc_otg_set_hprt0 (dwc_otg_core_if_t *core_if, uint32_t val)
++void dwc_otg_set_hprt0 (dwc_otg_core_if_t *core_if, uint32_t val)
+-uint32_t dwc_otg_get_guid (dwc_otg_core_if_t *core_if)
++uint32_t dwc_otg_get_guid (dwc_otg_core_if_t *core_if)
 GUID register.
+-void dwc_otg_set_guid (dwc_otg_core_if_t *core_if, uint32_t val)
++void dwc_otg_set_guid (dwc_otg_core_if_t *core_if, uint32_t val)
+-uint32_t dwc_otg_get_hptxfsiz (dwc_otg_core_if_t *core_if)
++uint32_t dwc_otg_get_hptxfsiz (dwc_otg_core_if_t *core_if)
 GHPTXFSIZE.
uint16_t dwc_otg_get_otg_version (dwc_otg_core_if_t *core_if)
 Returns OTG version - either 1.3 or 2.0.
void dwc_otg_pcd_start_srp_timer (dwc_otg_core_if_t *core_if)
 Start the SRP timer to detect when the SRP does not complete within 6 seconds.
++void dwc_otg_initiate_srp (dwc_otg_core_if_t *core_if)
+

Detailed Description

+ The Core Interface Layer provides basic services for accessing and managing the DWC_otg hardware. +@@ -608,56 +719,72 @@ + These services are used by both the Host Controller Driver and the Peripheral Controller Driver.

+ The CIL manages the memory map for the core so that the HCD and PCD don't have to do this separately. It also handles basic tasks like reading/writing the registers and data FIFOs in the controller. Some of the data access functions provide encapsulation of several operations required to perform a task, such as writing multiple registers to start a transfer. Finally, the CIL performs basic services that are not specific to either the host or device modes of operation. These services include management of the OTG Host Negotiation Protocol (HNP) and Session Request Protocol (SRP). A Diagnostic API is also provided to allow testing of the controller hardware.

+ The Core Interface Layer has the following requirements:

    +-
  • Provides basic controller operations.
  • Minimal use of OS services.
  • The OS services used will be abstracted by using inline functions or macros.
++
  • Provides basic controller operations.
  • Minimal use of OS services.
  • The OS services used will be abstracted by using inline functions or macros.
    • + +

    + Definition in file dwc_otg_cil.c.

    Define Documentation

    +- +-
    +-
    +- +- +- +- +- +- +- +- +- +- +- +- +- +- ++

    ++

    #define DWC_OTG_PARAM_TEST (_param_,
    _low_,
    _high_   ) 
    ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ + +
    #define DWC_OTG_PARAM_TEST ( _param_,
    _low_,
    _high_   ) 
    +- +-
    ++
    ++ ++ ++ ++ ++ ++
    ++   ++ + +

    + Value:

    (((_param_) < (_low_)) || \
+                 ((_param_) > (_high_)))
+
    +

    +-Definition at line 4051 of file dwc_otg_cil.c. +- +-

    ++Definition at line 5356 of file dwc_otg_cil.c.

    +

    Function Documentation

    +- +-
    +-
    +- +- +- +- +- +- +- +- ++

    ++

    dwc_otg_core_if_t* dwc_otg_cil_init (const uint32_t *  reg_base_addr  ) 
    ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ + +
    dwc_otg_core_if_t* dwc_otg_cil_init ( const uint32_t *  reg_base_addr  ) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + This function is called to initialize the DWC_otg CSR data structures. +@@ -665,58 +792,76 @@ + The register addresses in the device and host structures are initialized from the base address supplied by the caller. The calling function must make the OS calls to get the base address of the DWC_otg controller registers. The core_params argument holds the parameters that specify how the core should be configured.

    +

    Parameters:
    + +- ++ +
    reg_base_addr Base address of DWC_otg core registers
    reg_base_addr Base address of DWC_otg core registers
    +
    +- +

    +-Definition at line 78 of file dwc_otg_cil.c. +- +-

    +- +-

    +-
    +- +- +- +- +- +- +- +- ++ADP initialization ++

    ++Definition at line 78 of file dwc_otg_cil.c. ++

    ++
    void dwc_otg_cil_remove (dwc_otg_core_if_t *  core_if  ) 
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ + +
    void dwc_otg_cil_remove ( dwc_otg_core_if_t *  core_if  ) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    +-This function frees the structures allocated by dwc_otg_cil_init(). ++This function frees the structures allocated by dwc_otg_cil_init(). +

    +

    Parameters:
    + +- ++ +
    core_if The core interface pointer returned from dwc_otg_cil_init().
    core_if The core interface pointer returned from dwc_otg_cil_init().
    +
    +- +

    +-Definition at line 265 of file dwc_otg_cil.c. +- +-

    +- +-

    +-
    +- +- +- +- +- +- +- +- ++Remove ADP Stuff ++

    ++Definition at line 285 of file dwc_otg_cil.c. ++

    ++
    void dwc_otg_enable_global_interrupts (dwc_otg_core_if_t *  core_if  ) 
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ + +
    void dwc_otg_enable_global_interrupts ( dwc_otg_core_if_t *  core_if  ) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + This function enables the controller's Global Interrupt in the AHB Config register. +@@ -728,24 +873,32 @@ + + +

    +-Definition at line 292 of file dwc_otg_cil.c. +- +-

    +- +-

    +-
    +- +- +- +- +- +- +- +- ++Definition at line 322 of file dwc_otg_cil.c. ++ ++
    void dwc_otg_disable_global_interrupts (dwc_otg_core_if_t *  core_if  ) 
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ + +
    void dwc_otg_disable_global_interrupts ( dwc_otg_core_if_t *  core_if  ) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + This function disables the controller's Global Interrupt in the AHB Config register. +@@ -757,24 +910,32 @@ + + +

    +-Definition at line 305 of file dwc_otg_cil.c. +- +-

    +- +-

    +-
    +- +- +- +- +- +- +- +- ++Definition at line 335 of file dwc_otg_cil.c. ++ ++
    static void dwc_otg_enable_common_interrupts (dwc_otg_core_if_t *  core_if  )  [static]
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ + +
    void dwc_otg_enable_common_interrupts ( dwc_otg_core_if_t *  core_if  )  [static]
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + This function initializes the commmon interrupts, used in both device and host modes. +@@ -786,24 +947,32 @@ + + +

    +-Definition at line 319 of file dwc_otg_cil.c. +- +-

    +- +-

    +-
    +- +- +- +- +- +- +- +- ++Definition at line 349 of file dwc_otg_cil.c. ++ ++
    static uint32_t calc_num_in_eps (dwc_otg_core_if_t *  core_if  )  [static]
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ + +
    uint32_t calc_num_in_eps ( dwc_otg_core_if_t *  core_if  )  [static]
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + This function calculates the number of IN EPS using GHWCFG1 and GHWCFG2 registers values. +@@ -815,24 +984,32 @@ + + +

    +-Definition at line 415 of file dwc_otg_cil.c. +- +-

    +- +-

    +-
    +- +- +- +- +- +- +- +- ++Definition at line 1147 of file dwc_otg_cil.c. ++ ++
    static uint32_t calc_num_out_eps (dwc_otg_core_if_t *  core_if  )  [static]
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ + +
    uint32_t calc_num_out_eps ( dwc_otg_core_if_t *  core_if  )  [static]
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + This function calculates the number of OUT EPS using GHWCFG1 and GHWCFG2 registers values. +@@ -844,24 +1021,32 @@ + + +

    +-Definition at line 444 of file dwc_otg_cil.c. +- +-

    +- +-

    +-
    +- +- +- +- +- +- +- +- ++Definition at line 1176 of file dwc_otg_cil.c. ++ ++
    void dwc_otg_core_init (dwc_otg_core_if_t *  core_if  ) 
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ + +
    void dwc_otg_core_init ( dwc_otg_core_if_t *  core_if  ) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + This function initializes the DWC_otg controller registers and prepares the core for device mode or host mode operation. +@@ -873,96 +1058,114 @@ + + +

    +-Definition at line 467 of file dwc_otg_cil.c. +- +-

    +- +-

    +-
    +- +- +- +- +- +- +- +- ++Definition at line 1199 of file dwc_otg_cil.c. ++ ++
    void dwc_otg_enable_device_interrupts (dwc_otg_core_if_t *  core_if  ) 
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ + +
    void dwc_otg_enable_device_interrupts ( dwc_otg_core_if_t *  core_if  ) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + This function enables the Device mode interrupts. +

    +

    Parameters:
    + +- ++ +
    core_if Programming view of DWC_otg controller
    core_if Programming view of DWC_otg controller
    +
    +- +

    +-

    Todo:
    NGS: Should this be a module parameter?
    ++
    Todo:
    NGS: Should this be a module parameter?
    + +

    +-Definition at line 772 of file dwc_otg_cil.c. +- +-

    +- +-

    +-
    +- +- +- +- +- +- +- +- ++Definition at line 1526 of file dwc_otg_cil.c. ++ ++
    void dwc_otg_core_dev_init (dwc_otg_core_if_t *  core_if  ) 
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ + +
    void dwc_otg_core_dev_init ( dwc_otg_core_if_t *  core_if  ) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + This function initializes the DWC_otg controller registers for device mode. +

    +

    Parameters:
    + +- ++ +
    core_if Programming view of DWC_otg controller
    core_if Programming view of DWC_otg controller
    +
    ++

    ++Set Periodic Tx FIFO Mask all bits 0

    ++Set Tx FIFO Mask all bits 0

    ++

    Todo:
    NGS: Fix Periodic FIFO Sizing!

    ++Finish debug of this

    ++- if the condition needed to be checked or in any case all pending interrutps should be cleared?

    + +

    +-Set Periodic Tx FIFO Mask all bits 0

    +-Set Tx FIFO Mask all bits 0

    +-

    Todo:
    NGS: Fix Periodic FIFO Sizing!
    +-

    +-

    Todo:
    Finish debug of this
    +-

    +-

    Todo:
      +-
    • if the condition needed to be checked or in any case all pending interrutps should be cleared?
    +-
    +- +-

    +-Definition at line 843 of file dwc_otg_cil.c. +- +-

    +- +-

    +-
    +- +- +- +- +- +- +- +- ++Definition at line 1620 of file dwc_otg_cil.c. ++ ++
    void dwc_otg_enable_host_interrupts (dwc_otg_core_if_t *  core_if  ) 
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ + +
    void dwc_otg_enable_host_interrupts ( dwc_otg_core_if_t *  core_if  ) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + This function enables the Host mode interrupts. +@@ -974,24 +1177,32 @@ + + +

    +-Definition at line 1130 of file dwc_otg_cil.c. +- +-

    +- +-

    +-
    +- +- +- +- +- +- +- +- ++Definition at line 1955 of file dwc_otg_cil.c. ++ ++
    void dwc_otg_disable_host_interrupts (dwc_otg_core_if_t *  core_if  ) 
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ + +
    void dwc_otg_disable_host_interrupts ( dwc_otg_core_if_t *  core_if  ) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + This function disables the Host Mode interrupts. +@@ -1003,24 +1214,32 @@ + + +

    +-Definition at line 1165 of file dwc_otg_cil.c. +- +-

    +- +-

    +-
    +- +- +- +- +- +- +- +- ++Definition at line 1988 of file dwc_otg_cil.c. ++ ++
    void dwc_otg_core_host_init (dwc_otg_core_if_t *  core_if  ) 
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ + +
    void dwc_otg_core_host_init ( dwc_otg_core_if_t *  core_if  ) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + This function initializes the DWC_otg controller registers for host mode. +@@ -1033,33 +1252,41 @@ + + +

    +-Definition at line 1196 of file dwc_otg_cil.c. +- +-

    +- +-

    +-
    +- ++Definition at line 2019 of file dwc_otg_cil.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    void dwc_otg_hc_init (dwc_otg_core_if_t *  core_if, void dwc_otg_hc_init ( dwc_otg_core_if_t *  core_if,
    dwc_hc_t *  hc dwc_hc_t *  hc
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Prepares a host channel for transferring packets to/from a specific endpoint. +@@ -1073,39 +1300,47 @@ + + +

    +-Definition at line 1352 of file dwc_otg_cil.c. +- +-

    +- +-

    +-
    +- ++Definition at line 2206 of file dwc_otg_cil.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    void dwc_otg_hc_halt (dwc_otg_core_if_t *  core_if, void dwc_otg_hc_halt ( dwc_otg_core_if_t *  core_if,
    dwc_hc_t *  hc, dwc_hc_t *  hc,
    dwc_otg_halt_status_e  halt_status dwc_otg_halt_status_e  halt_status
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Attempts to halt a host channel. +@@ -1123,33 +1358,41 @@ + + +

    +-Definition at line 1540 of file dwc_otg_cil.c. +- +-

    +- +-

    +-
    +- ++Definition at line 2394 of file dwc_otg_cil.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    void dwc_otg_hc_cleanup (dwc_otg_core_if_t *  core_if, void dwc_otg_hc_cleanup ( dwc_otg_core_if_t *  core_if,
    dwc_hc_t *  hc dwc_hc_t *  hc
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Clears the transfer state for a host channel. +@@ -1163,39 +1406,47 @@ + + +

    +-Definition at line 1667 of file dwc_otg_cil.c. +- +-

    +- +-

    +-
    +- ++Definition at line 2521 of file dwc_otg_cil.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    static void hc_set_even_odd_frame (dwc_otg_core_if_t *  core_if, void hc_set_even_odd_frame ( dwc_otg_core_if_t *  core_if,
    dwc_hc_t *  hc, dwc_hc_t *  hc,
    hcchar_data_t *  hcchar hcchar_data_t *  hcchar
    ) [inline, static])  [inline, static]
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Sets the channel property that indicates in which frame a periodic transfer should occur. +@@ -1210,33 +1461,41 @@ + + +

    +-Definition at line 1695 of file dwc_otg_cil.c. +- +-

    +- +-

    +-
    +- ++Definition at line 2549 of file dwc_otg_cil.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    void dwc_otg_hc_start_transfer (dwc_otg_core_if_t *  core_if, void dwc_otg_hc_start_transfer ( dwc_otg_core_if_t *  core_if,
    dwc_hc_t *  hc dwc_hc_t *  hc
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + This function does the setup for a data transfer for a host channel and starts the transfer. +@@ -1254,33 +1513,41 @@ + + +

    +-Definition at line 1800 of file dwc_otg_cil.c. +- +-

    +- +-

    +-
    +- ++Definition at line 2703 of file dwc_otg_cil.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    void dwc_otg_hc_start_transfer_ddma (dwc_otg_core_if_t *  core_if, void dwc_otg_hc_start_transfer_ddma ( dwc_otg_core_if_t *  core_if,
    dwc_hc_t *  hc dwc_hc_t *  hc
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + This function does the setup for a data transfer for a host channel and starts the transfer in Descriptor DMA mode. +@@ -1295,33 +1562,41 @@ + + +

    +-Definition at line 1968 of file dwc_otg_cil.c. +- +-

    +- +-

    +-
    +- ++Definition at line 2872 of file dwc_otg_cil.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    int dwc_otg_hc_continue_transfer (dwc_otg_core_if_t *  core_if, int dwc_otg_hc_continue_transfer ( dwc_otg_core_if_t *  core_if,
    dwc_hc_t *  hc dwc_hc_t *  hc
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + This function continues a data transfer that was started by previous call to dwc_otg_hc_start_transfer. +@@ -1331,90 +1606,114 @@ +

    Returns:
    1 if a new request is queued, 0 if no more requests are required for this transfer.
    + +

    +-Definition at line 2048 of file dwc_otg_cil.c. +- +-

    +- +-

    +-
    +- ++Definition at line 2952 of file dwc_otg_cil.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    void dwc_otg_hc_do_ping (dwc_otg_core_if_t *  core_if, void dwc_otg_hc_do_ping ( dwc_otg_core_if_t *  core_if,
    dwc_hc_t *  hc dwc_hc_t *  hc
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Starts a PING transfer. +

    + This function should only be called in Slave mode. The Do Ping bit is set in the HCTSIZ register, then the channel is enabled. +

    +-Definition at line 2110 of file dwc_otg_cil.c. +- +-

    +- +-

    +-
    +- +- +- +- +- +- +- +- ++Definition at line 3014 of file dwc_otg_cil.c. ++ ++
    uint32_t dwc_otg_get_frame_number (dwc_otg_core_if_t *  core_if  ) 
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ + +
    uint32_t dwc_otg_get_frame_number ( dwc_otg_core_if_t *  core_if  ) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Gets the current USB frame number. +

    + This is the frame number from the last SOF packet. +

    +-Definition at line 2182 of file dwc_otg_cil.c. +- +-

    +- +-

    +-
    +- ++Definition at line 3086 of file dwc_otg_cil.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    void dwc_otg_read_setup_packet (dwc_otg_core_if_t *  core_if, void dwc_otg_read_setup_packet ( dwc_otg_core_if_t *  core_if,
    uint32_t *  dest uint32_t *  dest
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + This function reads a setup packet from the Rx FIFO into the destination buffer. +@@ -1428,33 +1727,41 @@ + + +

    +-Definition at line 2199 of file dwc_otg_cil.c. +- +-

    +- +-

    +-
    +- ++Definition at line 3144 of file dwc_otg_cil.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    void dwc_otg_ep0_activate (dwc_otg_core_if_t *  core_if, void dwc_otg_ep0_activate ( dwc_otg_core_if_t *  core_if,
    dwc_ep_t *  ep dwc_ep_t *  ep
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + This function enables EP0 OUT to receive SETUP packets and configures EP0 IN for transmitting packets. +@@ -1468,33 +1775,41 @@ + + +

    +-Definition at line 2216 of file dwc_otg_cil.c. +- +-

    +- +-

    +-
    +- ++Definition at line 3161 of file dwc_otg_cil.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    void dwc_otg_ep_activate (dwc_otg_core_if_t *  core_if, void dwc_otg_ep_activate ( dwc_otg_core_if_t *  core_if,
    dwc_ep_t *  ep dwc_ep_t *  ep
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + This function activates an EP. +@@ -1508,33 +1823,41 @@ + + +

    +-Definition at line 2268 of file dwc_otg_cil.c. +- +-

    +- +-

    +-
    +- ++Definition at line 3214 of file dwc_otg_cil.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    void dwc_otg_ep_deactivate (dwc_otg_core_if_t *  core_if, void dwc_otg_ep_deactivate ( dwc_otg_core_if_t *  core_if,
    dwc_ep_t *  ep dwc_ep_t *  ep
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + This function deactivates an EP. +@@ -1548,33 +1871,41 @@ + + +

    +-Definition at line 2367 of file dwc_otg_cil.c. +- +-

    +- +-

    +-
    +- ++Definition at line 3369 of file dwc_otg_cil.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    static void init_dma_desc_chain (dwc_otg_core_if_t *  core_if, void init_dma_desc_chain ( dwc_otg_core_if_t *  core_if,
    dwc_ep_t *  ep dwc_ep_t *  ep
    ) [static])  [static]
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + This function initializes dma descriptor chain. +@@ -1582,40 +1913,47 @@ +

    Parameters:
    + + +- ++ +
    core_if Programming view of DWC_otg controller.
    ep The EP to start the transfer on.
    ep The EP to start the transfer on.
    +
    +- +

    + DMA Descriptor Setup +

    +-Definition at line 2415 of file dwc_otg_cil.c. +- +-

    +- +-

    +-
    +- ++Definition at line 3515 of file dwc_otg_cil.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    void dwc_otg_ep_start_transfer (dwc_otg_core_if_t *  core_if, void dwc_otg_ep_start_transfer ( dwc_otg_core_if_t *  core_if,
    dwc_ep_t *  ep dwc_ep_t *  ep
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + This function does the setup for a data transfer for an EP and starts the transfer. +@@ -1624,42 +1962,50 @@ +

    Parameters:
    + + +- ++ +
    core_if Programming view of DWC_otg controller.
    ep The EP to start the transfer on.
    ep The EP to start the transfer on.
    +
    +- +

    +-DIEPDMAn Register write

    +-Enable the Non-Periodic Tx FIFO empty interrupt, or the Tx FIFO epmty interrupt in dedicated Tx FIFO mode, the data will be written into the fifo by the ISR.

    ++DIEPDMAn Register write

    ++Enable the Non-Periodic Tx FIFO empty interrupt, or the Tx FIFO epmty interrupt in dedicated Tx FIFO mode, the data will be written into the fifo by the ISR.

    ++This is used for interrupt out transfers

    + DOEPDMAn Register write +

    +-Definition at line 2475 of file dwc_otg_cil.c. +- +-

    +- +-

    +-
    +- ++Definition at line 3655 of file dwc_otg_cil.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    void dwc_otg_ep_start_zl_transfer (dwc_otg_core_if_t *  core_if, void dwc_otg_ep_start_zl_transfer ( dwc_otg_core_if_t *  core_if,
    dwc_ep_t *  ep dwc_ep_t *  ep
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + This function setup a zero length transfer in Buffer DMA and Slave modes for usb requests with zero field set. +@@ -1667,40 +2013,47 @@ +

    Parameters:
    + + +- ++ +
    core_if Programming view of DWC_otg controller.
    ep The EP to start the transfer on.
    ep The EP to start the transfer on.
    +
    +- +

    +-Enable the Non-Periodic Tx FIFO empty interrupt, or the Tx FIFO epmty interrupt in dedicated Tx FIFO mode, the data will be written into the fifo by the ISR. ++Enable the Non-Periodic Tx FIFO empty interrupt, or the Tx FIFO epmty interrupt in dedicated Tx FIFO mode, the data will be written into the fifo by the ISR. +

    +-Definition at line 2678 of file dwc_otg_cil.c. +- +-

    +- +-

    +-
    +- ++Definition at line 3948 of file dwc_otg_cil.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    void dwc_otg_ep0_start_transfer (dwc_otg_core_if_t *  core_if, void dwc_otg_ep0_start_transfer ( dwc_otg_core_if_t *  core_if,
    dwc_ep_t *  ep dwc_ep_t *  ep
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + This function does the setup for a data transfer for EP0 and starts the transfer. +@@ -1709,44 +2062,51 @@ +

    Parameters:
    + + +- ++ +
    core_if Programming view of DWC_otg controller.
    ep The EP0 data.
    ep The EP0 data.
    +
    +- +

    +-DMA Descriptor Setup

    +-DIEPDMA0 Register write

    +-Enable the Non-Periodic Tx FIFO empty interrupt, the data will be written into the fifo by the ISR.

    +-DMA Descriptor Setup

    ++DMA Descriptor Setup

    ++DIEPDMA0 Register write

    ++Enable the Non-Periodic Tx FIFO empty interrupt, the data will be written into the fifo by the ISR.

    ++DMA Descriptor Setup

    + DOEPDMA0 Register write +

    +-Definition at line 2785 of file dwc_otg_cil.c. +- +-

    +- +-

    +-
    +- ++Definition at line 4051 of file dwc_otg_cil.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    void dwc_otg_ep0_continue_transfer (dwc_otg_core_if_t *  core_if, void dwc_otg_ep0_continue_transfer ( dwc_otg_core_if_t *  core_if,
    dwc_ep_t *  ep dwc_ep_t *  ep
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + This function continues control IN transfers started by dwc_otg_ep0_start_transfer, when the transfer does not fit in a single packet. +@@ -1755,52 +2115,59 @@ +

    Parameters:
    + + +- ++ +
    core_if Programming view of DWC_otg controller.
    ep The EP0 data.
    ep The EP0 data.
    +
    +- +

    +-

    Todo:
    Should there be check for room in the Tx Status Queue. If not remove the code above this comment.
    ++
    Todo:
    Should there be check for room in the Tx Status Queue. If not remove the code above this comment.
    +

    +-DMA Descriptor Setup

    +-DIEPDMA0 Register write

    +-Enable the Non-Periodic Tx FIFO empty interrupt, the data will be written into the fifo by the ISR.

    +-DMA Descriptor Setup

    ++DMA Descriptor Setup

    ++DIEPDMA0 Register write

    ++Enable the Non-Periodic Tx FIFO empty interrupt, the data will be written into the fifo by the ISR.

    ++DMA Descriptor Setup

    + DOEPDMA0 Register write +

    +-Definition at line 2969 of file dwc_otg_cil.c. +- +-

    +- +-

    +-
    +- ++Definition at line 4239 of file dwc_otg_cil.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    void dwc_otg_ep_write_packet (dwc_otg_core_if_t *  core_if, void dwc_otg_ep_write_packet ( dwc_otg_core_if_t *  core_if,
    dwc_ep_t *  ep, dwc_ep_t *  ep,
    int  dma int  dma
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + This function writes a packet into the Tx FIFO associated with the EP. +@@ -1810,46 +2177,53 @@ + + + +- ++ +
    core_if Programming view of DWC_otg controller.
    ep The EP to write packet for.
    dma Indicates if DMA is being used.
    dma Indicates if DMA is being used.
    + +- +

    + The buffer is padded to DWORD on a per packet basis in slave/dma mode if the MPS is not DWORD aligned. The last packet, if short, is also padded to a multiple of DWORD.

    + ep->xfer_buff always starts DWORD aligned in memory and is a multiple of DWORD in length

    + ep->xfer_len can be any number of bytes

    + ep->xfer_count is a multiple of ep->maxpacket until the last packet

    +-FIFO access is DWORD

    +-

    Todo:
    NGS Where are the Periodic Tx FIFO addresses intialized? What should this be?
    ++FIFO access is DWORD

    ++

    Todo:
    NGS Where are the Periodic Tx FIFO addresses intialized? What should this be?
    + +

    +-Definition at line 3165 of file dwc_otg_cil.c. +- +-

    +- +-

    +-
    +- ++Definition at line 4438 of file dwc_otg_cil.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    void dwc_otg_ep_set_stall (dwc_otg_core_if_t *  core_if, void dwc_otg_ep_set_stall ( dwc_otg_core_if_t *  core_if,
    dwc_ep_t *  ep dwc_ep_t *  ep
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Set the EP STALL. +@@ -1862,33 +2236,41 @@ + + +

    +-Definition at line 3236 of file dwc_otg_cil.c. +- +-

    +- +-

    +-
    +- ++Definition at line 4509 of file dwc_otg_cil.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    void dwc_otg_ep_clear_stall (dwc_otg_core_if_t *  core_if, void dwc_otg_ep_clear_stall ( dwc_otg_core_if_t *  core_if,
    dwc_ep_t *  ep dwc_ep_t *  ep
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Clear the EP STALL. +@@ -1901,39 +2283,47 @@ + + +

    +-Definition at line 3274 of file dwc_otg_cil.c. +- +-

    +- +-

    +-
    +- ++Definition at line 4547 of file dwc_otg_cil.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    void dwc_otg_read_packet (dwc_otg_core_if_t *  core_if, void dwc_otg_read_packet ( dwc_otg_core_if_t *  core_if,
    uint8_t *  dest, uint8_t *  dest,
    uint16_t  bytes uint16_t  bytes
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + This function reads a packet from the Rx FIFO into the destination buffer. +@@ -1943,32 +2333,39 @@ + + + +- ++ +
    core_if Programming view of DWC_otg controller.
    dest Destination buffer for the packet.
    bytes Number of bytes to copy to the destination.
    bytes Number of bytes to copy to the destination.
    + +- +

    +-

    Todo:
    Account for the case where _dest is not dword aligned. This requires reading data from the FIFO into a uint32_t temp buffer, then moving it into the data buffer.
    ++
    Todo:
    Account for the case where _dest is not dword aligned. This requires reading data from the FIFO into a uint32_t temp buffer, then moving it into the data buffer.
    + +

    +-Definition at line 3317 of file dwc_otg_cil.c. +- +-

    +- +-

    +-
    +- +- +- +- +- +- +- +- ++Definition at line 4590 of file dwc_otg_cil.c. ++ ++
    void dwc_otg_dump_dev_registers (dwc_otg_core_if_t *  core_if  ) 
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ + +
    void dwc_otg_dump_dev_registers ( dwc_otg_core_if_t *  core_if  ) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Dump core registers and SPRAM. +@@ -1980,24 +2377,32 @@ + + +

    +-Definition at line 3347 of file dwc_otg_cil.c. +- +-

    +- +-

    +-
    +- +- +- +- +- +- +- +- ++Definition at line 4620 of file dwc_otg_cil.c. ++ ++
    void dwc_otg_dump_spram (dwc_otg_core_if_t *  core_if  ) 
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ + +
    void dwc_otg_dump_spram ( dwc_otg_core_if_t *  core_if  ) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + This functions reads the SPRAM and prints its content. +@@ -2009,24 +2414,32 @@ + + +

    +-Definition at line 3477 of file dwc_otg_cil.c. +- +-

    +- +-

    +-
    +- +- +- +- +- +- +- +- ++Definition at line 4756 of file dwc_otg_cil.c. ++ ++
    void dwc_otg_dump_host_registers (dwc_otg_core_if_t *  core_if  ) 
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ + +
    void dwc_otg_dump_host_registers ( dwc_otg_core_if_t *  core_if  ) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + This function reads the host registers and prints them. +@@ -2038,24 +2451,32 @@ + + +

    +-Definition at line 3505 of file dwc_otg_cil.c. +- +-

    +- +-

    +-
    +- +- +- +- +- +- +- +- ++Definition at line 4784 of file dwc_otg_cil.c. ++ ++
    void dwc_otg_dump_global_registers (dwc_otg_core_if_t *  core_if  ) 
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ + +
    void dwc_otg_dump_global_registers ( dwc_otg_core_if_t *  core_if  ) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + This function reads the core global registers and prints them. +@@ -2067,33 +2488,41 @@ + + +

    +-Definition at line 3573 of file dwc_otg_cil.c. +- +-

    +- +-

    +-
    +- ++Definition at line 4853 of file dwc_otg_cil.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    void dwc_otg_flush_tx_fifo (dwc_otg_core_if_t *  core_if, void dwc_otg_flush_tx_fifo ( dwc_otg_core_if_t *  core_if,
    const int  num const int  num
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Flush a Tx FIFO. +@@ -2106,24 +2535,32 @@ + + +

    +-Definition at line 3662 of file dwc_otg_cil.c. +- +-

    +- +-

    +-
    +- +- +- +- +- +- +- +- ++Definition at line 4959 of file dwc_otg_cil.c. ++ ++
    void dwc_otg_flush_rx_fifo (dwc_otg_core_if_t *  core_if  ) 
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ + +
    void dwc_otg_flush_rx_fifo ( dwc_otg_core_if_t *  core_if  ) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Flush Rx FIFO. +@@ -2135,63 +2572,79 @@ + + +

    +-Definition at line 3694 of file dwc_otg_cil.c. +- +-

    +- +-

    +-
    +- +- +- +- +- +- +- +- ++Definition at line 4991 of file dwc_otg_cil.c. ++ ++
    void dwc_otg_core_reset (dwc_otg_core_if_t *  core_if  ) 
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ + +
    void dwc_otg_core_reset ( dwc_otg_core_if_t *  core_if  ) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Do core a soft reset of the core. +

    + Be careful with this because it resets all the internal state machines of the core. +

    +-Definition at line 3725 of file dwc_otg_cil.c. +- +-

    +- +-

    +-
    +- ++Definition at line 5022 of file dwc_otg_cil.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    void dwc_otg_cil_register_hcd_callbacks (dwc_otg_core_if_t *  core_if, void dwc_otg_cil_register_hcd_callbacks ( dwc_otg_core_if_t *  core_if,
    dwc_otg_cil_callbacks_t *  cb, dwc_otg_cil_callbacks_t *  cb,
    void *  p void *  p
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Register HCD callbacks. +@@ -2206,39 +2659,47 @@ + + +

    +-Definition at line 3781 of file dwc_otg_cil.c. +- +-

    +- +-

    +-
    +- ++Definition at line 5078 of file dwc_otg_cil.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    void dwc_otg_cil_register_pcd_callbacks (dwc_otg_core_if_t *  core_if, void dwc_otg_cil_register_pcd_callbacks ( dwc_otg_core_if_t *  core_if,
    dwc_otg_cil_callbacks_t *  cb, dwc_otg_cil_callbacks_t *  cb,
    void *  p void *  p
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Register PCD callbacks. +@@ -2253,33 +2714,41 @@ + + +

    +-Definition at line 3796 of file dwc_otg_cil.c. +- +-

    +- +-

    +-
    +- ++Definition at line 5093 of file dwc_otg_cil.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    void write_isoc_frame_data (dwc_otg_core_if_t *  core_if, void write_isoc_frame_data ( dwc_otg_core_if_t *  core_if,
    dwc_ep_t *  ep dwc_ep_t *  ep
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + This function writes isoc data per 1 (micro)frame into tx fifo. +@@ -2292,33 +2761,41 @@ + + +

    +-Definition at line 3812 of file dwc_otg_cil.c. +- +-

    +- +-

    +-
    +- ++Definition at line 5109 of file dwc_otg_cil.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    void dwc_otg_iso_ep_start_frm_transfer (dwc_otg_core_if_t *  core_if, void dwc_otg_iso_ep_start_frm_transfer ( dwc_otg_core_if_t *  core_if,
    dwc_ep_t *  ep dwc_ep_t *  ep
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + This function initializes a descriptor chain for Isochronous transfer. +@@ -2326,502 +2803,621 @@ +

    Parameters:
    + + +- ++ +
    core_if Programming view of DWC_otg controller.
    ep The EP to start the transfer on.
    ep The EP to start the transfer on.
    +
    +- +

    + Enable endpoint, clear nak +

    +-Definition at line 3864 of file dwc_otg_cil.c. +- +-

    +- +-

    +-
    +- ++Definition at line 5161 of file dwc_otg_cil.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    int dwc_otg_set_param_otg_cap (dwc_otg_core_if_t *  core_if, int dwc_otg_set_param_otg_cap ( dwc_otg_core_if_t *  core_if,
    int32_t  val int32_t  val
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Specifies the OTG capabilities. +

    + The driver will automatically detect the value for this parameter if none is specified. 0 - HNP and SRP capable (default) 1 - SRP Only capable 2 - No HNP/SRP capable +

    +-Definition at line 4056 of file dwc_otg_cil.c. +- +-

    +- +-

    +-
    +- ++Definition at line 5361 of file dwc_otg_cil.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    int dwc_otg_set_param_dma_enable (dwc_otg_core_if_t *  core_if, int dwc_otg_set_param_dma_enable ( dwc_otg_core_if_t *  core_if,
    int32_t  val int32_t  val
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Specifies whether to use slave or DMA mode for accessing the data FIFOs. +

    + The driver will automatically detect the value for this parameter if none is specified. 0 - Slave 1 - DMA (default, if available) +

    +-Definition at line 4135 of file dwc_otg_cil.c. +- +-

    +- +-

    +-
    +- ++Definition at line 5440 of file dwc_otg_cil.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    int dwc_otg_set_param_dma_desc_enable (dwc_otg_core_if_t *  core_if, int dwc_otg_set_param_dma_desc_enable ( dwc_otg_core_if_t *  core_if,
    int32_t  val int32_t  val
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + When DMA mode is enabled specifies whether to use address DMA or DMA Descritor mode for accessing the data FIFOs in device mode. +

    + The driver will automatically detect the value for this parameter if none is specified. 0 - address DMA 1 - DMA Descriptor(default, if available) +

    +-Definition at line 4165 of file dwc_otg_cil.c. +- +-

    +- +-

    +-
    +- ++Definition at line 5470 of file dwc_otg_cil.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    int dwc_otg_set_param_host_support_fs_ls_low_power (dwc_otg_core_if_t *  core_if, int dwc_otg_set_param_host_support_fs_ls_low_power ( dwc_otg_core_if_t *  core_if,
    int32_t  val int32_t  val
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Specifies whether low power mode is supported when attached to a Full Speed or Low Speed device in host mode. +

    + 0 - Don't support low power mode (default) 1 - Support low power mode +

    +-Definition at line 4195 of file dwc_otg_cil.c. +- +-

    +- +-

    +-
    +- ++Definition at line 5500 of file dwc_otg_cil.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    int dwc_otg_set_param_data_fifo_size (dwc_otg_core_if_t *  core_if, int dwc_otg_set_param_data_fifo_size ( dwc_otg_core_if_t *  core_if,
    int32_t  val int32_t  val
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Total number of 4-byte words in the data FIFO memory. +

    + This memory includes the Rx FIFO, non-periodic Tx FIFO, and periodic Tx FIFOs. 32 to 32768 (default 8192) Note: The total FIFO memory depth in the FPGA configuration is 8192. +

    +-Definition at line 4242 of file dwc_otg_cil.c. +- +-

    +- +-

    +-
    +- ++Definition at line 5547 of file dwc_otg_cil.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    int dwc_otg_set_param_dev_rx_fifo_size (dwc_otg_core_if_t *  core_if, int dwc_otg_set_param_dev_rx_fifo_size ( dwc_otg_core_if_t *  core_if,
    int32_t  val int32_t  val
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Number of 4-byte words in the Rx FIFO in device mode when dynamic FIFO sizing is enabled. +

    + 16 to 32768 (default 1064) +

    +-Definition at line 4271 of file dwc_otg_cil.c. +- +-

    +- +-

    +-
    +- ++Definition at line 5576 of file dwc_otg_cil.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    int dwc_otg_set_param_dev_nperio_tx_fifo_size (dwc_otg_core_if_t *  core_if, int dwc_otg_set_param_dev_nperio_tx_fifo_size ( dwc_otg_core_if_t *  core_if,
    int32_t  val int32_t  val
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Number of 4-byte words in the non-periodic Tx FIFO in device mode when dynamic FIFO sizing is enabled. +

    + 16 to 32768 (default 1024) +

    +-Definition at line 4297 of file dwc_otg_cil.c. +- +-

    +- +-

    +-
    +- ++Definition at line 5602 of file dwc_otg_cil.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    int dwc_otg_set_param_host_rx_fifo_size (dwc_otg_core_if_t *  core_if, int dwc_otg_set_param_host_rx_fifo_size ( dwc_otg_core_if_t *  core_if,
    int32_t  val int32_t  val
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Number of 4-byte words in the Rx FIFO in host mode when dynamic FIFO sizing is enabled. +

    + 16 to 32768 (default 1024) +

    +-Definition at line 4330 of file dwc_otg_cil.c. +- +-

    +- +-

    +-
    +- ++Definition at line 5635 of file dwc_otg_cil.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    int dwc_otg_set_param_host_nperio_tx_fifo_size (dwc_otg_core_if_t *  core_if, int dwc_otg_set_param_host_nperio_tx_fifo_size ( dwc_otg_core_if_t *  core_if,
    int32_t  val int32_t  val
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Number of 4-byte words in the non-periodic Tx FIFO in host mode when Dynamic FIFO sizing is enabled in the core. +

    + 16 to 32768 (default 1024) +

    +-Definition at line 4362 of file dwc_otg_cil.c. +- +-

    +- +-

    +-
    +- ++Definition at line 5667 of file dwc_otg_cil.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    int dwc_otg_set_param_host_perio_tx_fifo_size (dwc_otg_core_if_t *  core_if, int dwc_otg_set_param_host_perio_tx_fifo_size ( dwc_otg_core_if_t *  core_if,
    int32_t  val int32_t  val
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Number of 4-byte words in the host periodic Tx FIFO when dynamic FIFO sizing is enabled. +

    + 16 to 32768 (default 1024) +

    +-Definition at line 4395 of file dwc_otg_cil.c. +- +-

    +- +-

    +-
    +- ++Definition at line 5700 of file dwc_otg_cil.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    int dwc_otg_set_param_max_transfer_size (dwc_otg_core_if_t *  core_if, int dwc_otg_set_param_max_transfer_size ( dwc_otg_core_if_t *  core_if,
    int32_t  val int32_t  val
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + The maximum transfer size supported in bytes. +

    + 2047 to 65,535 (default 65,535) +

    +-Definition at line 4428 of file dwc_otg_cil.c. +- +-

    +- +-

    +-
    +- ++Definition at line 5731 of file dwc_otg_cil.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    int dwc_otg_set_param_max_packet_count (dwc_otg_core_if_t *  core_if, int dwc_otg_set_param_max_packet_count ( dwc_otg_core_if_t *  core_if,
    int32_t  val int32_t  val
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + The maximum number of packets in a transfer. +

    + 15 to 511 (default 511) +

    +-Definition at line 4461 of file dwc_otg_cil.c. +- +-

    +- +-

    +-
    +- ++Definition at line 5764 of file dwc_otg_cil.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    int dwc_otg_set_param_host_channels (dwc_otg_core_if_t *  core_if, int dwc_otg_set_param_host_channels ( dwc_otg_core_if_t *  core_if,
    int32_t  val int32_t  val
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + The number of host channel registers to use. +

    + 1 to 16 (default 12) Note: The FPGA configuration supports a maximum of 12 host channels. +

    +-Definition at line 4492 of file dwc_otg_cil.c. +- +-

    +- +-

    +-
    +- ++Definition at line 5795 of file dwc_otg_cil.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    int dwc_otg_set_param_dev_endpoints (dwc_otg_core_if_t *  core_if, int dwc_otg_set_param_dev_endpoints ( dwc_otg_core_if_t *  core_if,
    int32_t  val int32_t  val
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + The number of endpoints in addition to EP0 available for device mode operations. +

    + 1 to 15 (default 6 IN and OUT) Note: The FPGA configuration supports a maximum of 6 IN and OUT endpoints in addition to EP0. +

    +-Definition at line 4522 of file dwc_otg_cil.c. +- +-

    +- +-

    +-
    +- ++Definition at line 5825 of file dwc_otg_cil.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    int dwc_otg_set_param_phy_type (dwc_otg_core_if_t *  core_if, int dwc_otg_set_param_phy_type ( dwc_otg_core_if_t *  core_if,
    int32_t  val int32_t  val
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Specifies the type of PHY interface to use. +@@ -2829,66 +3425,82 @@ + By default, the driver will automatically detect the phy_type.

    + 0 - Full Speed PHY 1 - UTMI+ (default) 2 - ULPI +

    +-Definition at line 4552 of file dwc_otg_cil.c. +- +-

    +- +-

    +-
    +- ++Definition at line 5855 of file dwc_otg_cil.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    int dwc_otg_set_param_speed (dwc_otg_core_if_t *  core_if, int dwc_otg_set_param_speed ( dwc_otg_core_if_t *  core_if,
    int32_t  val int32_t  val
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Specifies the maximum speed of operation in host and device mode. +

    + The actual speed depends on the speed of the attached device and the value of phy_type. The actual speed depends on the speed of the attached device. 0 - High Speed (default) 1 - Full Speed +

    +-Definition at line 4601 of file dwc_otg_cil.c. +- +-

    +- +-

    +-
    +- ++Definition at line 5904 of file dwc_otg_cil.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    int dwc_otg_set_param_host_ls_low_power_phy_clk (dwc_otg_core_if_t *  core_if, int dwc_otg_set_param_host_ls_low_power_phy_clk ( dwc_otg_core_if_t *  core_if,
    int32_t  val int32_t  val
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Specifies the PHY clock rate in low power mode when connected to a Low Speed device in host mode. +@@ -2896,33 +3508,41 @@ + This parameter is applicable only if HOST_SUPPORT_FS_LS_LOW_POWER is enabled. If PHY_TYPE is set to FS then defaults to 6 MHZ otherwise 48 MHZ.

    + 0 - 48 MHz 1 - 6 MHz +

    +-Definition at line 4630 of file dwc_otg_cil.c. +- +-

    +- +-

    +-
    +- ++Definition at line 5933 of file dwc_otg_cil.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    int dwc_otg_set_param_phy_ulpi_ddr (dwc_otg_core_if_t *  core_if, int dwc_otg_set_param_phy_ulpi_ddr ( dwc_otg_core_if_t *  core_if,
    int32_t  val int32_t  val
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Specifies whether the ULPI operates at double or single data rate. +@@ -2930,33 +3550,41 @@ + This parameter is only applicable if PHY_TYPE is ULPI.

    + 0 - single data rate ULPI interface with 8 bit wide data bus (default) 1 - double data rate ULPI interface with 4 bit wide data bus +

    +-Definition at line 4665 of file dwc_otg_cil.c. +- +-

    +- +-

    +-
    +- ++Definition at line 5970 of file dwc_otg_cil.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    int dwc_otg_set_param_phy_utmi_width (dwc_otg_core_if_t *  core_if, int dwc_otg_set_param_phy_utmi_width ( dwc_otg_core_if_t *  core_if,
    int32_t  val int32_t  val
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Specifies the UTMI+ Data Width. +@@ -2964,140 +3592,246 @@ + This parameter is applicable for a PHY_TYPE of UTMI+ or ULPI. (For a ULPI PHY_TYPE, this parameter indicates the data width between the MAC and the ULPI Wrapper.) Also, this parameter is applicable only if the OTG_HSPHY_WIDTH cC parameter was set to "8 and 16 bits", meaning that the core has been configured to work at either data path width.

    + 8 or 16 bits (default 16) +

    +-Definition at line 4700 of file dwc_otg_cil.c. +- +-

    +- +-

    +-
    +- ++Definition at line 6005 of file dwc_otg_cil.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    int dwc_otg_set_param_i2c_enable (dwc_otg_core_if_t *  core_if, int dwc_otg_set_param_i2c_enable ( dwc_otg_core_if_t *  core_if,
    int32_t  val int32_t  val
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Specifies whether to use the I2Cinterface for full speed PHY. +

    + This parameter is only applicable if PHY_TYPE is FS. 0 - No (default) 1 - Yes +

    +-Definition at line 4751 of file dwc_otg_cil.c. +- +-

    +- +-

    +-
    +- ++Definition at line 6056 of file dwc_otg_cil.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    int dwc_otg_set_param_dev_perio_tx_fifo_size (dwc_otg_core_if_t *  core_if, int dwc_otg_set_param_dev_perio_tx_fifo_size ( dwc_otg_core_if_t *  core_if,
    int32_t  val, int32_t  val,
    int  fifo_num int  fifo_num
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Number of 4-byte words in each of the periodic Tx FIFOs in device mode when dynamic FIFO sizing is enabled. +

    + 4 to 768 (default 256) +

    +-Definition at line 4779 of file dwc_otg_cil.c. +- +-

    +- +-

    +-
    +- ++Definition at line 6085 of file dwc_otg_cil.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    int dwc_otg_set_param_dma_burst_size (dwc_otg_core_if_t *  core_if, int dwc_otg_set_param_dma_burst_size ( dwc_otg_core_if_t *  core_if,
    int32_t  val int32_t  val
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + The DMA Burst size (applicable only for External DMA Mode). +

    + 1, 4, 8 16, 32, 64, 128, 256 (default 32) +

    +-Definition at line 4959 of file dwc_otg_cil.c. +- +-

    +- +-

    +-
    +- +- +- +- +- +- +- +- ++Definition at line 6275 of file dwc_otg_cil.c. ++ ++
    uint32_t dwc_otg_get_mode (dwc_otg_core_if_t *  core_if  ) 
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ + +
    uint32_t dwc_otg_get_mode ( dwc_otg_core_if_t *  core_if  ) 
    +- +-
    ++
    ++ ++ ++ ++ ++ ++
    ++   ++ + +

    + Get current mode. +

    + Returns 0 if in device mode, and 1 if in host mode. +

    +-Definition at line 5115 of file dwc_otg_cil.c. +- +-

    +-

    Generated on Tue May 5 02:22:48 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++Definition at line 6653 of file dwc_otg_cil.c.
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
    uint16_t dwc_otg_get_otg_version ( dwc_otg_core_if_t *  core_if  ) 
    ++
    ++ ++ ++ ++ ++ ++
    ++   ++ ++ ++

    ++Returns OTG version - either 1.3 or 2.0. ++

    ++

    Parameters:
    ++ ++ ++
    core_if The core_if structure pointer
    ++
    ++ ++

    ++Definition at line 7012 of file dwc_otg_cil.c.

    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
    void dwc_otg_pcd_start_srp_timer ( dwc_otg_core_if_t *  core_if  ) 
    ++
    ++ ++ ++ ++ ++ ++
    ++   ++ ++ ++

    ++Start the SRP timer to detect when the SRP does not complete within 6 seconds. ++

    ++

    Parameters:
    ++ ++ ++
    core_if the pointer to core_if strucure.
    ++
    ++ ++

    ++Definition at line 7023 of file dwc_otg_cil.c.

    ++

    Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
    ++doxygen 1.3.9.1 + + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__cil_8h-source.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/dwc__otg__cil_8h-source.html 2013-07-26 19:31:20.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__cil_8h-source.html 2013-07-26 19:34:40.000000000 +0000 +@@ -2,708 +2,907 @@ + + DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_cil.h Source File + +- + +- +-
    +-
    +-
    +-
    +-

    dwc_otg_cil.h

    Go to the documentation of this file.
    00001 /* ==========================================================================
+-00002  * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_cil.h $
+-00003  * $Revision: #99 $
+-00004  * $Date: 2009/04/21 $
+-00005  * $Change: 1237466 $
+-00006  *
+-00007  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
+-00008  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
+-00009  * otherwise expressly agreed to in writing between Synopsys and you.
+-00010  * 
+-00011  * The Software IS NOT an item of Licensed Software or Licensed Product under
+-00012  * any End User Software License Agreement or Agreement for Licensed Product
+-00013  * with Synopsys or any supplement thereto. You are permitted to use and
+-00014  * redistribute this Software in source and binary forms, with or without
+-00015  * modification, provided that redistributions of source code must retain this
+-00016  * notice. You may not view, use, disclose, copy or distribute this file or
+-00017  * any information contained herein except pursuant to this license grant from
+-00018  * Synopsys. If you do not agree with this notice, including the disclaimer
+-00019  * below, then you are not authorized to use the Software.
+-00020  * 
+-00021  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
+-00022  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+-00023  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+-00024  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
+-00025  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+-00026  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+-00027  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+-00028  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+-00029  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+-00030  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+-00031  * DAMAGE.
+-00032  * ========================================================================== */
+-00033 
+-00034 #if !defined(__DWC_CIL_H__)
+-00035 #define __DWC_CIL_H__
+-00036 
+-00037 #include "dwc_os.h"
+-00038 #include "dwc_list.h"
+-00039 #include "dwc_otg_dbg.h"
+-00040 #include "dwc_otg_regs.h"
+-00041 
+-00042 #include "dwc_otg_core_if.h"
+-00043 
+-00049 #ifdef DWC_UTE_CFI
+-00050 
+-00051 #define MAX_DMA_DESCS_PER_EP    256
+-00052 
+-00056 typedef enum _data_buffer_mode {
+-00057         BM_STANDARD = 0,        /* data buffer is in normal mode */
+-00058         BM_SG = 1,              /* data buffer uses the scatter/gather mode */
+-00059         BM_CONCAT = 2,          /* data buffer uses the concatenation mode */
+-00060         BM_CIRCULAR = 3,        /* data buffer uses the circular DMA mode */
+-00061         BM_ALIGN = 4            /* data buffer is in buffer alignment mode */
+-00062 } data_buffer_mode_e;
+-00063 #endif                          //DWC_UTE_CFI
+-00064 
+-00067 #define OTG_CORE_REV_2_60a      0x4F54260A
+-00068 #define OTG_CORE_REV_2_71a      0x4F54271A
+-00069 #define OTG_CORE_REV_2_72a      0x4F54272A
+-00070 #define OTG_CORE_REV_2_80a      0x4F54280A
+-00071 #define OTG_CORE_REV_2_81a      0x4F54281A
+-00072 #define OTG_CORE_REV_2_90a      0x4F54290A              
+-00073 
+-00077 typedef struct iso_pkt_info {
+-00078         uint32_t offset;
+-00079         uint32_t length;
+-00080         int32_t status;
+-00081 } iso_pkt_info_t;
+-00082 
+-00088 typedef struct dwc_ep {
+-00090         uint8_t num;
+-00092         unsigned is_in:1;
+-00094         unsigned active:1;
+-00095 
+-00098         unsigned tx_fifo_num:4;
+-00100         unsigned type:2;
+-00101 #define DWC_OTG_EP_TYPE_CONTROL    0
+-00102 #define DWC_OTG_EP_TYPE_ISOC       1
+-00103 #define DWC_OTG_EP_TYPE_BULK       2
+-00104 #define DWC_OTG_EP_TYPE_INTR       3
+-00105 
+-00107         unsigned data_pid_start:1;
+-00109         unsigned even_odd_frame:1;
+-00111         unsigned maxpacket:11;
+-00112 
+-00114         uint32_t maxxfer;
+-00115 
+-00124         dwc_dma_t dma_addr;
+-00125 
+-00126         dwc_dma_t dma_desc_addr;
+-00127         dwc_otg_dev_dma_desc_t *desc_addr;
+-00128 
+-00129         uint8_t *start_xfer_buff;
+-00131         uint8_t *xfer_buff;
+-00133         unsigned xfer_len:19;
+-00135         unsigned xfer_count:19;
+-00137         unsigned sent_zlp:1;
+-00139         unsigned total_len:19;
+-00140 
+-00142         unsigned stall_clear_flag:1;
+-00143 
+-00144 #ifdef DWC_UTE_CFI
+-00145         /* The buffer mode */
+-00146         data_buffer_mode_e buff_mode;
+-00147 
+-00148         /* The chain of DMA descriptors.
+-00149          * MAX_DMA_DESCS_PER_EP will be allocated for each active EP.
+-00150          */
+-00151         dwc_otg_dma_desc_t *descs;
+-00152 
+-00153         /* The DMA address of the descriptors chain start */
+-00154         dma_addr_t descs_dma_addr;
+-00156         uint32_t cfi_req_len;
+-00157 #endif                          //DWC_UTE_CFI
+-00158 
+-00160         uint32_t desc_cnt;
+-00161 
+-00162 #ifdef DWC_EN_ISOC
+-00163 
+-00168         dwc_dma_t dma_addr0;
+-00169         dwc_dma_t dma_addr1;
+-00170 
+-00171         dwc_dma_t iso_dma_desc_addr;
+-00172         dwc_otg_dev_dma_desc_t *iso_desc_addr;
+-00173 
+-00175         uint8_t *xfer_buff0;
+-00176         uint8_t *xfer_buff1;
+-00177 
+-00179         uint32_t proc_buf_num;
+-00181         uint32_t buf_proc_intrvl;
+-00183         uint32_t data_per_frame;
+-00184 
+-00185         /* todo - pattern data support is to be implemented in the future */
+-00187         uint32_t data_pattern_frame;
+-00189         uint32_t sync_frame;
+-00190 
+-00192         uint32_t bInterval;
+-00194         uint32_t pkt_per_frm;
+-00196         uint32_t next_frame;
+-00198         uint32_t pkt_cnt;
+-00200         iso_pkt_info_t *pkt_info;
+-00202         uint32_t cur_pkt;
+-00204         uint8_t *cur_pkt_addr;
+-00206         uint32_t cur_pkt_dma_addr;
+-00207 #endif                          /* DWC_EN_ISOC */
+-00208 
+-00210 } dwc_ep_t;
+-00211 
+-00212 /*
+-00213  * Reasons for halting a host channel.
+-00214  */
+-00215 typedef enum dwc_otg_halt_status {
+-00216         DWC_OTG_HC_XFER_NO_HALT_STATUS,
+-00217         DWC_OTG_HC_XFER_COMPLETE,
+-00218         DWC_OTG_HC_XFER_URB_COMPLETE,
+-00219         DWC_OTG_HC_XFER_ACK,
+-00220         DWC_OTG_HC_XFER_NAK,
+-00221         DWC_OTG_HC_XFER_NYET,
+-00222         DWC_OTG_HC_XFER_STALL,
+-00223         DWC_OTG_HC_XFER_XACT_ERR,
+-00224         DWC_OTG_HC_XFER_FRAME_OVERRUN,
+-00225         DWC_OTG_HC_XFER_BABBLE_ERR,
+-00226         DWC_OTG_HC_XFER_DATA_TOGGLE_ERR,
+-00227         DWC_OTG_HC_XFER_AHB_ERR,
+-00228         DWC_OTG_HC_XFER_PERIODIC_INCOMPLETE,
+-00229         DWC_OTG_HC_XFER_URB_DEQUEUE
+-00230 } dwc_otg_halt_status_e;
+-00231 
+-00237 typedef struct dwc_hc {
+-00239         uint8_t hc_num;
+-00240 
+-00242         unsigned dev_addr:7;
+-00243 
+-00245         unsigned ep_num:4;
+-00246 
+-00248         unsigned ep_is_in:1;
+-00249 
+-00257         unsigned speed:2;
+-00258 #define DWC_OTG_EP_SPEED_LOW    0
+-00259 #define DWC_OTG_EP_SPEED_FULL   1
+-00260 #define DWC_OTG_EP_SPEED_HIGH   2
+-00261 
+-00270         unsigned ep_type:2;
+-00271 
+-00273         unsigned max_packet:11;
+-00274 
+-00283         unsigned data_pid_start:2;
+-00284 #define DWC_OTG_HC_PID_DATA0 0
+-00285 #define DWC_OTG_HC_PID_DATA2 1
+-00286 #define DWC_OTG_HC_PID_DATA1 2
+-00287 #define DWC_OTG_HC_PID_MDATA 3
+-00288 #define DWC_OTG_HC_PID_SETUP 3
+-00289 
+-00291         unsigned multi_count:2;
+-00292 
+-00297         uint8_t *xfer_buff;
+-00302         dwc_dma_t align_buff;
+-00304         uint32_t xfer_len;
+-00306         uint32_t xfer_count;
+-00308         uint16_t start_pkt_count;
+-00309 
+-00314         uint8_t xfer_started;
+-00315 
+-00320         uint8_t do_ping;
+-00321 
+-00326         uint8_t error_state;
+-00327 
+-00334         uint8_t halt_on_queue;
+-00335 
+-00340         uint8_t halt_pending;
+-00341 
+-00345         dwc_otg_halt_status_e halt_status;
+-00346 
+-00347         /*
+-00348          * Split settings for the host channel
+-00349          */
+-00350         uint8_t do_split;                  
+-00351         uint8_t complete_split;    
+-00352         uint8_t hub_addr;                  
+-00354         uint8_t port_addr;                 
+-00361         uint8_t xact_pos;
+-00362 
+-00364         uint8_t short_read;
+-00365 
+-00370         uint8_t requests;
+-00371 
+-00375         struct dwc_otg_qh *qh;
+-00376 
+-00380          DWC_CIRCLEQ_ENTRY(dwc_hc) hc_list_entry;
+-00381         
+-00386         uint16_t ntd;
+-00387         
+-00389         dwc_dma_t desc_list_addr;
+-00390         
+-00392         uint8_t schinfo;
+-00393         
+-00395 } dwc_hc_t;
+-00396 
+-00401 typedef struct dwc_otg_core_params {
+-00402         int32_t opt;
+-00403 
+-00411         int32_t otg_cap;
+-00412 
+-00420         int32_t dma_enable;
+-00421 
+-00429         int32_t dma_desc_enable;
+-00433         int32_t dma_burst_size; /* Translate this to GAHBCFG values */
+-00434 
+-00443         int32_t speed;
+-00449         int32_t host_support_fs_ls_low_power;
+-00450 
+-00459         int32_t host_ls_low_power_phy_clk;
+-00460 
+-00465         int32_t enable_dynamic_fifo;
+-00466 
+-00473         int32_t data_fifo_size;
+-00474 
+-00479         int32_t dev_rx_fifo_size;
+-00480 
+-00485         int32_t dev_nperio_tx_fifo_size;
+-00486 
+-00491         uint32_t dev_perio_tx_fifo_size[MAX_PERIO_FIFOS];
+-00492 
+-00497         int32_t host_rx_fifo_size;
+-00498 
+-00503         int32_t host_nperio_tx_fifo_size;
+-00504 
+-00509         int32_t host_perio_tx_fifo_size;
+-00510 
+-00514         int32_t max_transfer_size;
+-00515 
+-00519         int32_t max_packet_count;
+-00520 
+-00525         int32_t host_channels;
+-00526 
+-00533         int32_t dev_endpoints;
+-00534 
+-00543         int32_t phy_type;
+-00544 
+-00556         int32_t phy_utmi_width;
+-00557 
+-00568         int32_t phy_ulpi_ddr;
+-00569 
+-00574         int32_t phy_ulpi_ext_vbus;
+-00575 
+-00582         int32_t i2c_enable;
+-00583 
+-00584         int32_t ulpi_fs_ls;
+-00585 
+-00586         int32_t ts_dline;
+-00587 
+-00594         int32_t en_multiple_tx_fifo;
+-00595 
+-00600         uint32_t dev_tx_fifo_size[MAX_TX_FIFOS];
+-00601 
+-00607         uint32_t thr_ctl;
+-00608 
+-00612         uint32_t tx_thr_length;
+-00613 
+-00617         uint32_t rx_thr_length;
+-00618 
+-00622         int32_t lpm_enable;
+-00623 
+-00629         int32_t pti_enable;
+-00630 
+-00636         int32_t mpi_enable;
+-00637 
+-00642         int32_t ic_usb_cap;
+-00643 
+-00650         int32_t ahb_thr_ratio;
+-00651 
+-00652 } dwc_otg_core_params_t;
+-00653 
+-00654 #ifdef DEBUG
+-00655 struct dwc_otg_core_if;
+-00656 typedef struct hc_xfer_info {
+-00657         struct dwc_otg_core_if *core_if;
+-00658         dwc_hc_t *hc;
+-00659 } hc_xfer_info_t;
+-00660 #endif
+-00661 /*
+-00662  * Device States
+-00663  */
+-00664 typedef enum dwc_otg_lx_state {
+-00666         DWC_OTG_L0,
+-00668         DWC_OTG_L1,
+-00670         DWC_OTG_L2,
+-00672         DWC_OTG_L3
+-00673 } dwc_otg_lx_state_e;
+-00674 
+-00680 struct dwc_otg_core_if {
+-00682         dwc_otg_core_params_t *core_params;
+-00683 
+-00685         dwc_otg_core_global_regs_t *core_global_regs;
+-00686 
+-00688         dwc_otg_dev_if_t *dev_if;
+-00690         dwc_otg_host_if_t *host_if;
+-00691 
+-00693         uint32_t snpsid;
+-00694 
+-00695         /*
+-00696          * Set to 1 if the core PHY interface bits in USBCFG have been
+-00697          * initialized.
+-00698          */
+-00699         uint8_t phy_init_done;
+-00700 
+-00701         /*
+-00702          * SRP Success flag, set by srp success interrupt in FS I2C mode
+-00703          */
+-00704         uint8_t srp_success;
+-00705         uint8_t srp_timer_started;
+-00706 
+-00707         /* Common configuration information */
+-00709         volatile uint32_t *pcgcctl;
+-00710 #define DWC_OTG_PCGCCTL_OFFSET 0xE00
+-00711 
+-00713         uint32_t *data_fifo[MAX_EPS_CHANNELS];
+-00714 #define DWC_OTG_DATA_FIFO_OFFSET 0x1000
+-00715 #define DWC_OTG_DATA_FIFO_SIZE 0x1000
+-00716 
+-00718         uint16_t total_fifo_size;
+-00720         uint16_t rx_fifo_size;
+-00722         uint16_t nperio_tx_fifo_size;
+-00723 
+-00725         uint8_t dma_enable;
+-00726 
+-00728         uint8_t dma_desc_enable;
+-00729 
+-00731         uint8_t pti_enh_enable;
+-00732 
+-00734         uint8_t multiproc_int_enable;
+-00735 
+-00737         uint8_t en_multiple_tx_fifo;
+-00738 
+-00741         uint8_t queuing_high_bandwidth;
+-00742 
+-00744         hwcfg1_data_t hwcfg1;
+-00745         hwcfg2_data_t hwcfg2;
+-00746         hwcfg3_data_t hwcfg3;
+-00747         hwcfg4_data_t hwcfg4;
+-00748 
+-00750         hcfg_data_t hcfg;
+-00751         dcfg_data_t dcfg;
+-00752 
+-00758         uint8_t op_state;
+-00759 
+-00765         uint8_t restart_hcd_on_session_req;
+-00766 
+-00769 #define A_HOST          (1)
+-00770 
+-00771 #define A_SUSPEND       (2)
+-00772 
+-00773 #define A_PERIPHERAL    (3)
+-00774 
+-00775 #define B_PERIPHERAL    (4)
+-00776 
+-00777 #define B_HOST          (5)
+-00778 
+-00780         struct dwc_otg_cil_callbacks *hcd_cb;
+-00782         struct dwc_otg_cil_callbacks *pcd_cb;
+-00783 
+-00785         uint32_t p_tx_msk;
+-00787         uint32_t tx_msk;
+-00788 
+-00790         dwc_workq_t *wq_otg;
+-00791 
+-00793         dwc_timer_t *wkp_timer;
+-00794 
+-00795 #ifdef DEBUG
+-00796         uint32_t start_hcchar_val[MAX_EPS_CHANNELS];
+-00797 
+-00798         hc_xfer_info_t hc_xfer_info[MAX_EPS_CHANNELS];
+-00799         dwc_timer_t *hc_xfer_timer[MAX_EPS_CHANNELS];
+-00800 
+-00801         uint32_t hfnum_7_samples;
+-00802         uint64_t hfnum_7_frrem_accum;
+-00803         uint32_t hfnum_0_samples;
+-00804         uint64_t hfnum_0_frrem_accum;
+-00805         uint32_t hfnum_other_samples;
+-00806         uint64_t hfnum_other_frrem_accum;
+-00807 #endif
+-00808 
+-00809 #ifdef DWC_UTE_CFI
+-00810         uint16_t pwron_rxfsiz;
+-00811         uint16_t pwron_gnptxfsiz;
+-00812         uint16_t pwron_txfsiz[15];
+-00813 
+-00814         uint16_t init_rxfsiz;
+-00815         uint16_t init_gnptxfsiz;
+-00816         uint16_t init_txfsiz[15];
+-00817 #endif
+-00818 
+-00820         dwc_otg_lx_state_e lx_state;
+-00821 
+-00822 };
+-00823 
+-00824 #ifdef DEBUG
+-00825 /*
+-00826  * This function is called when transfer is timed out.
+-00827  */
+-00828 extern void hc_xfer_timeout(void *ptr);
+-00829 #endif
+-00830 
+-00831 /*
+-00832  * The following functions are functions for works 
+-00833  * using during handling some interrupts
+-00834  */
+-00835 extern void w_conn_id_status_change(void *p);
+-00836 
+-00837 extern void w_wakeup_detected(void *p);
+-00838 
+-00839 /*
+-00840  * The following functions support initialization of the CIL driver component
+-00841  * and the DWC_otg controller.
+-00842  */
+-00843 extern void dwc_otg_core_host_init(dwc_otg_core_if_t * _core_if);
+-00844 extern void dwc_otg_core_dev_init(dwc_otg_core_if_t * _core_if);
+-00845 
+-00851 extern void dwc_otg_wakeup(dwc_otg_core_if_t * _core_if);
+-00852 extern void dwc_otg_read_setup_packet(dwc_otg_core_if_t * _core_if,
+-00853                                       uint32_t * _dest);
+-00854 extern uint32_t dwc_otg_get_frame_number(dwc_otg_core_if_t * _core_if);
+-00855 extern void dwc_otg_ep0_activate(dwc_otg_core_if_t * _core_if, dwc_ep_t * _ep);
+-00856 extern void dwc_otg_ep_activate(dwc_otg_core_if_t * _core_if, dwc_ep_t * _ep);
+-00857 extern void dwc_otg_ep_deactivate(dwc_otg_core_if_t * _core_if, dwc_ep_t * _ep);
+-00858 extern void dwc_otg_ep_start_transfer(dwc_otg_core_if_t * _core_if,
+-00859                                       dwc_ep_t * _ep);
+-00860 extern void dwc_otg_ep_start_zl_transfer(dwc_otg_core_if_t * _core_if,
+-00861                                          dwc_ep_t * _ep);
+-00862 extern void dwc_otg_ep0_start_transfer(dwc_otg_core_if_t * _core_if,
+-00863                                        dwc_ep_t * _ep);
+-00864 extern void dwc_otg_ep0_continue_transfer(dwc_otg_core_if_t * _core_if,
+-00865                                           dwc_ep_t * _ep);
+-00866 extern void dwc_otg_ep_write_packet(dwc_otg_core_if_t * _core_if,
+-00867                                     dwc_ep_t * _ep, int _dma);
+-00868 extern void dwc_otg_ep_set_stall(dwc_otg_core_if_t * _core_if, dwc_ep_t * _ep);
+-00869 extern void dwc_otg_ep_clear_stall(dwc_otg_core_if_t * _core_if,
+-00870                                    dwc_ep_t * _ep);
+-00871 extern void dwc_otg_enable_device_interrupts(dwc_otg_core_if_t * _core_if);
+-00872 
+-00873 #ifdef DWC_EN_ISOC
+-00874 extern void dwc_otg_iso_ep_start_frm_transfer(dwc_otg_core_if_t * core_if,
+-00875                                               dwc_ep_t * ep);
+-00876 extern void dwc_otg_iso_ep_start_buf_transfer(dwc_otg_core_if_t * core_if,
+-00877                                               dwc_ep_t * ep);
+-00878 #endif                          /* DWC_EN_ISOC */
+-00879 
+-00886 extern void dwc_otg_hc_init(dwc_otg_core_if_t * _core_if, dwc_hc_t * _hc);
+-00887 extern void dwc_otg_hc_halt(dwc_otg_core_if_t * _core_if,
+-00888                             dwc_hc_t * _hc, dwc_otg_halt_status_e _halt_status);
+-00889 extern void dwc_otg_hc_cleanup(dwc_otg_core_if_t * _core_if, dwc_hc_t * _hc);
+-00890 extern void dwc_otg_hc_start_transfer(dwc_otg_core_if_t * _core_if,
+-00891                                       dwc_hc_t * _hc);
+-00892 extern int dwc_otg_hc_continue_transfer(dwc_otg_core_if_t * _core_if,
+-00893                                         dwc_hc_t * _hc);
+-00894 extern void dwc_otg_hc_do_ping(dwc_otg_core_if_t * _core_if, dwc_hc_t * _hc);
+-00895 extern void dwc_otg_hc_write_packet(dwc_otg_core_if_t * _core_if,
+-00896                                     dwc_hc_t * _hc);
+-00897 extern void dwc_otg_enable_host_interrupts(dwc_otg_core_if_t * _core_if);
+-00898 extern void dwc_otg_disable_host_interrupts(dwc_otg_core_if_t * _core_if);
+-00899 
+-00900 extern void dwc_otg_hc_start_transfer_ddma(dwc_otg_core_if_t * core_if, dwc_hc_t * hc);
+-00901 
+-00902 /* Macro used to clear one channel interrupt */
+-00903 #define clear_hc_int(_hc_regs_, _intr_) \
+-00904 do { \
+-00905         hcint_data_t hcint_clear = {.d32 = 0}; \
+-00906         hcint_clear.b._intr_ = 1; \
+-00907         dwc_write_reg32(&(_hc_regs_)->hcint, hcint_clear.d32); \
+-00908 } while (0)
+-00909 
+-00910 /*
+-00911  * Macro used to disable one channel interrupt. Channel interrupts are
+-00912  * disabled when the channel is halted or released by the interrupt handler.
+-00913  * There is no need to handle further interrupts of that type until the
+-00914  * channel is re-assigned. In fact, subsequent handling may cause crashes
+-00915  * because the channel structures are cleaned up when the channel is released.
+-00916  */
+-00917 #define disable_hc_int(_hc_regs_, _intr_) \
+-00918 do { \
+-00919         hcintmsk_data_t hcintmsk = {.d32 = 0}; \
+-00920         hcintmsk.b._intr_ = 1; \
+-00921         dwc_modify_reg32(&(_hc_regs_)->hcintmsk, hcintmsk.d32, 0); \
+-00922 } while (0)
+-00923                 
+-00929 static inline uint32_t dwc_otg_read_hprt0(dwc_otg_core_if_t * _core_if)
+-00930 {
+-00931         hprt0_data_t hprt0;
+-00932         hprt0.d32 = dwc_read_reg32(_core_if->host_if->hprt0);
+-00933         hprt0.b.prtena = 0;
+-00934         hprt0.b.prtconndet = 0;
+-00935         hprt0.b.prtenchng = 0;
+-00936         hprt0.b.prtovrcurrchng = 0;
+-00937         return hprt0.d32;
+-00938 }
+-00939 
+-00948 extern void dwc_otg_read_packet(dwc_otg_core_if_t * core_if,
+-00949                                 uint8_t * dest, uint16_t bytes);
+-00950 
+-00951 extern void dwc_otg_flush_tx_fifo(dwc_otg_core_if_t * _core_if, const int _num);
+-00952 extern void dwc_otg_flush_rx_fifo(dwc_otg_core_if_t * _core_if);
+-00953 extern void dwc_otg_core_reset(dwc_otg_core_if_t * _core_if);
+-00954 
+-00958 static inline uint32_t dwc_otg_read_core_intr(dwc_otg_core_if_t * core_if)
+-00959 {
+-00960         return (dwc_read_reg32(&core_if->core_global_regs->gintsts) &
+-00961                 dwc_read_reg32(&core_if->core_global_regs->gintmsk));
+-00962 }
+-00963 
+-00967 static inline uint32_t dwc_otg_read_otg_intr(dwc_otg_core_if_t * core_if)
+-00968 {
+-00969         return (dwc_read_reg32(&core_if->core_global_regs->gotgint));
+-00970 }
+-00971 
+-00976 static inline uint32_t dwc_otg_read_dev_all_in_ep_intr(dwc_otg_core_if_t *
+-00977                                                        core_if)
+-00978 {
+-00979 
+-00980         uint32_t v;
+-00981 
+-00982         if (core_if->multiproc_int_enable) {
+-00983                 v = dwc_read_reg32(&core_if->dev_if->dev_global_regs->
+-00984                                    deachint) & dwc_read_reg32(&core_if->dev_if->
+-00985                                                               dev_global_regs->
+-00986                                                               deachintmsk);
+-00987         } else {
+-00988                 v = dwc_read_reg32(&core_if->dev_if->dev_global_regs->daint) &
+-00989                     dwc_read_reg32(&core_if->dev_if->dev_global_regs->daintmsk);
+-00990         }
+-00991         return (v & 0xffff);
+-00992 }
+-00993 
+-00998 static inline uint32_t dwc_otg_read_dev_all_out_ep_intr(dwc_otg_core_if_t *
+-00999                                                         core_if)
+-01000 {
+-01001         uint32_t v;
+-01002 
+-01003         if (core_if->multiproc_int_enable) {
+-01004                 v = dwc_read_reg32(&core_if->dev_if->dev_global_regs->
+-01005                                    deachint) & dwc_read_reg32(&core_if->dev_if->
+-01006                                                               dev_global_regs->
+-01007                                                               deachintmsk);
+-01008         } else {
+-01009                 v = dwc_read_reg32(&core_if->dev_if->dev_global_regs->daint) &
+-01010                     dwc_read_reg32(&core_if->dev_if->dev_global_regs->daintmsk);
+-01011         }
+-01012 
+-01013         return ((v & 0xffff0000) >> 16);
+-01014 }
+-01015 
+-01019 static inline uint32_t dwc_otg_read_dev_in_ep_intr(dwc_otg_core_if_t * core_if,
+-01020                                                    dwc_ep_t * ep)
+-01021 {
+-01022         dwc_otg_dev_if_t *dev_if = core_if->dev_if;
+-01023         uint32_t v, msk, emp;
+-01024 
+-01025         if (core_if->multiproc_int_enable) {
+-01026                 msk =
+-01027                     dwc_read_reg32(&dev_if->dev_global_regs->
+-01028                                    diepeachintmsk[ep->num]);
+-01029                 emp =
+-01030                     dwc_read_reg32(&dev_if->dev_global_regs->
+-01031                                    dtknqr4_fifoemptymsk);
+-01032                 msk |= ((emp >> ep->num) & 0x1) << 7;
+-01033                 v = dwc_read_reg32(&dev_if->in_ep_regs[ep->num]->diepint) & msk;
+-01034         } else {
+-01035                 msk = dwc_read_reg32(&dev_if->dev_global_regs->diepmsk);
+-01036                 emp =
+-01037                     dwc_read_reg32(&dev_if->dev_global_regs->
+-01038                                    dtknqr4_fifoemptymsk);
+-01039                 msk |= ((emp >> ep->num) & 0x1) << 7;
+-01040                 v = dwc_read_reg32(&dev_if->in_ep_regs[ep->num]->diepint) & msk;
+-01041         }
+-01042 
+-01043         return v;
+-01044 }
+-01045 
+-01049 static inline uint32_t dwc_otg_read_dev_out_ep_intr(dwc_otg_core_if_t *
+-01050                                                     _core_if, dwc_ep_t * _ep)
+-01051 {
+-01052         dwc_otg_dev_if_t *dev_if = _core_if->dev_if;
+-01053         uint32_t v;
+-01054         doepmsk_data_t msk = {.d32 = 0 };
+-01055 
+-01056         if (_core_if->multiproc_int_enable) {
+-01057                 msk.d32 =
+-01058                     dwc_read_reg32(&dev_if->dev_global_regs->
+-01059                                    doepeachintmsk[_ep->num]);
+-01060                 if (_core_if->pti_enh_enable) {
+-01061                         msk.b.pktdrpsts = 1;
+-01062                 }
+-01063                 v = dwc_read_reg32(&dev_if->out_ep_regs[_ep->num]->
+-01064                                    doepint) & msk.d32;
+-01065         } else {
+-01066                 msk.d32 = dwc_read_reg32(&dev_if->dev_global_regs->doepmsk);
+-01067                 if (_core_if->pti_enh_enable) {
+-01068                         msk.b.pktdrpsts = 1;
+-01069                 }
+-01070                 v = dwc_read_reg32(&dev_if->out_ep_regs[_ep->num]->
+-01071                                    doepint) & msk.d32;
+-01072         }
+-01073         return v;
+-01074 }
+-01075 
+-01079 static inline uint32_t dwc_otg_read_host_all_channels_intr(dwc_otg_core_if_t *
+-01080                                                            _core_if)
+-01081 {
+-01082         return (dwc_read_reg32(&_core_if->host_if->host_global_regs->haint));
+-01083 }
+-01084 
+-01085 static inline uint32_t dwc_otg_read_host_channel_intr(dwc_otg_core_if_t *
+-01086                                                       _core_if, dwc_hc_t * _hc)
+-01087 {
+-01088         return (dwc_read_reg32
+-01089                 (&_core_if->host_if->hc_regs[_hc->hc_num]->hcint));
+-01090 }
+-01091 
+-01097 static inline uint32_t dwc_otg_mode(dwc_otg_core_if_t * _core_if)
+-01098 {
+-01099         return (dwc_read_reg32(&_core_if->core_global_regs->gintsts) & 0x1);
+-01100 }
+-01101 
+-01109 typedef struct dwc_otg_cil_callbacks {
+-01111         int (*start) (void *_p);
+-01113         int (*stop) (void *_p);
+-01115         int (*disconnect) (void *_p);
+-01117         int (*resume_wakeup) (void *_p);
+-01119         int (*suspend) (void *_p);
+-01121         int (*session_start) (void *_p);
+-01122 #ifdef CONFIG_USB_DWC_OTG_LPM
+-01123 
+-01124         int (*sleep) (void *_p);
+-01125 #endif
+-01126 
+-01127         void *p;
+-01128 } dwc_otg_cil_callbacks_t;
+-01129 
+-01130 extern void dwc_otg_cil_register_pcd_callbacks(dwc_otg_core_if_t * _core_if,
+-01131                                                dwc_otg_cil_callbacks_t * _cb,
+-01132                                                void *_p);
+-01133 extern void dwc_otg_cil_register_hcd_callbacks(dwc_otg_core_if_t * _core_if,
+-01134                                                dwc_otg_cil_callbacks_t * _cb,
+-01135                                                void *_p);
+-01136 
+-01137 #endif
+-
    Generated on Tue May 5 02:22:48 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++
    Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
    ++

    dwc_otg_cil.h

    Go to the documentation of this file.
    00001 /* ==========================================================================
++00002  * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_cil.h $
++00003  * $Revision: #122 $
++00004  * $Date: 2011/10/24 $
++00005  * $Change: 1871160 $
++00006  *
++00007  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
++00008  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
++00009  * otherwise expressly agreed to in writing between Synopsys and you.
++00010  *
++00011  * The Software IS NOT an item of Licensed Software or Licensed Product under
++00012  * any End User Software License Agreement or Agreement for Licensed Product
++00013  * with Synopsys or any supplement thereto. You are permitted to use and
++00014  * redistribute this Software in source and binary forms, with or without
++00015  * modification, provided that redistributions of source code must retain this
++00016  * notice. You may not view, use, disclose, copy or distribute this file or
++00017  * any information contained herein except pursuant to this license grant from
++00018  * Synopsys. If you do not agree with this notice, including the disclaimer
++00019  * below, then you are not authorized to use the Software.
++00020  *
++00021  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
++00022  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++00023  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++00024  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
++00025  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++00026  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
++00027  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
++00028  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
++00029  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
++00030  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
++00031  * DAMAGE.
++00032  * ========================================================================== */
++00033 
++00034 #if !defined(__DWC_CIL_H__)
++00035 #define __DWC_CIL_H__
++00036 
++00037 #include "dwc_list.h"
++00038 #include "dwc_otg_dbg.h"
++00039 #include "dwc_otg_regs.h"
++00040 
++00041 #include "dwc_otg_core_if.h"
++00042 #include "dwc_otg_adp.h"
++00043 
++00049 #ifdef DWC_UTE_CFI
++00050 
++00051 #define MAX_DMA_DESCS_PER_EP    256
++00052 
++00056 typedef enum _data_buffer_mode {
++00057         BM_STANDARD = 0,        /* data buffer is in normal mode */
++00058         BM_SG = 1,              /* data buffer uses the scatter/gather mode */
++00059         BM_CONCAT = 2,          /* data buffer uses the concatenation mode */
++00060         BM_CIRCULAR = 3,        /* data buffer uses the circular DMA mode */
++00061         BM_ALIGN = 4            /* data buffer is in buffer alignment mode */
++00062 } data_buffer_mode_e;
++00063 #endif //DWC_UTE_CFI
++00064 
++00067 #define OTG_CORE_REV_2_60a      0x4F54260A
++00068 #define OTG_CORE_REV_2_71a      0x4F54271A
++00069 #define OTG_CORE_REV_2_72a      0x4F54272A
++00070 #define OTG_CORE_REV_2_80a      0x4F54280A
++00071 #define OTG_CORE_REV_2_81a      0x4F54281A
++00072 #define OTG_CORE_REV_2_90a      0x4F54290A
++00073 #define OTG_CORE_REV_2_91a      0x4F54291A
++00074 #define OTG_CORE_REV_2_92a      0x4F54292A
++00075 #define OTG_CORE_REV_2_93a      0x4F54293A
++00076 #define OTG_CORE_REV_2_94a      0x4F54294A
++00077 
++00081 typedef struct iso_pkt_info {
++00082         uint32_t offset;
++00083         uint32_t length;
++00084         int32_t status;
++00085 } iso_pkt_info_t;
++00086 
++00092 typedef struct dwc_ep {
++00094         uint8_t num;
++00096         unsigned is_in:1;
++00098         unsigned active:1;
++00099 
++00103         unsigned tx_fifo_num:4;
++00105         unsigned type:2;
++00106 #define DWC_OTG_EP_TYPE_CONTROL    0
++00107 #define DWC_OTG_EP_TYPE_ISOC       1
++00108 #define DWC_OTG_EP_TYPE_BULK       2
++00109 #define DWC_OTG_EP_TYPE_INTR       3
++00110 
++00112         unsigned data_pid_start:1;
++00114         unsigned even_odd_frame:1;
++00116         unsigned maxpacket:11;
++00117 
++00119         uint32_t maxxfer;
++00120 
++00129         dwc_dma_t dma_addr;
++00130 
++00131         dwc_dma_t dma_desc_addr;
++00132         dwc_otg_dev_dma_desc_t *desc_addr;
++00133 
++00134         uint8_t *start_xfer_buff;
++00136         uint8_t *xfer_buff;
++00138         unsigned xfer_len:19;
++00140         unsigned xfer_count:19;
++00142         unsigned sent_zlp:1;
++00144         unsigned total_len:19;
++00145 
++00147         unsigned stall_clear_flag:1;
++00148 
++00149 #ifdef DWC_UTE_CFI
++00150         /* The buffer mode */
++00151         data_buffer_mode_e buff_mode;
++00152 
++00153         /* The chain of DMA descriptors.
++00154          * MAX_DMA_DESCS_PER_EP will be allocated for each active EP.
++00155          */
++00156         dwc_otg_dma_desc_t *descs;
++00157 
++00158         /* The DMA address of the descriptors chain start */
++00159         dma_addr_t descs_dma_addr;
++00161         uint32_t cfi_req_len;
++00162 #endif                          //DWC_UTE_CFI
++00163 
++00165 #define MAX_DMA_DESC_CNT 256
++00166 
++00167         uint32_t desc_cnt;
++00168         
++00170         uint32_t bInterval;
++00172         uint32_t frame_num;
++00174         uint8_t frm_overrun;
++00175 
++00176 #ifdef DWC_UTE_PER_IO
++00177 
++00178         uint32_t xiso_frame_num;
++00180         uint32_t xiso_bInterval;
++00182         int xiso_active_xfers;
++00183         int xiso_queued_xfers;
++00184 #endif
++00185 #ifdef DWC_EN_ISOC
++00186 
++00191         dwc_dma_t dma_addr0;
++00192         dwc_dma_t dma_addr1;
++00193 
++00194         dwc_dma_t iso_dma_desc_addr;
++00195         dwc_otg_dev_dma_desc_t *iso_desc_addr;
++00196 
++00198         uint8_t *xfer_buff0;
++00199         uint8_t *xfer_buff1;
++00200 
++00202         uint32_t proc_buf_num;
++00204         uint32_t buf_proc_intrvl;
++00206         uint32_t data_per_frame;
++00207 
++00208         /* todo - pattern data support is to be implemented in the future */
++00210         uint32_t data_pattern_frame;
++00212         uint32_t sync_frame;
++00213 
++00215         uint32_t bInterval;
++00217         uint32_t pkt_per_frm;
++00219         uint32_t next_frame;
++00221         uint32_t pkt_cnt;
++00223         iso_pkt_info_t *pkt_info;
++00225         uint32_t cur_pkt;
++00227         uint8_t *cur_pkt_addr;
++00229         uint32_t cur_pkt_dma_addr;
++00230 #endif                          /* DWC_EN_ISOC */
++00231 
++00233 } dwc_ep_t;
++00234 
++00235 /*
++00236  * Reasons for halting a host channel.
++00237  */
++00238 typedef enum dwc_otg_halt_status {
++00239         DWC_OTG_HC_XFER_NO_HALT_STATUS,
++00240         DWC_OTG_HC_XFER_COMPLETE,
++00241         DWC_OTG_HC_XFER_URB_COMPLETE,
++00242         DWC_OTG_HC_XFER_ACK,
++00243         DWC_OTG_HC_XFER_NAK,
++00244         DWC_OTG_HC_XFER_NYET,
++00245         DWC_OTG_HC_XFER_STALL,
++00246         DWC_OTG_HC_XFER_XACT_ERR,
++00247         DWC_OTG_HC_XFER_FRAME_OVERRUN,
++00248         DWC_OTG_HC_XFER_BABBLE_ERR,
++00249         DWC_OTG_HC_XFER_DATA_TOGGLE_ERR,
++00250         DWC_OTG_HC_XFER_AHB_ERR,
++00251         DWC_OTG_HC_XFER_PERIODIC_INCOMPLETE,
++00252         DWC_OTG_HC_XFER_URB_DEQUEUE
++00253 } dwc_otg_halt_status_e;
++00254 
++00260 typedef struct dwc_hc {
++00262         uint8_t hc_num;
++00263 
++00265         unsigned dev_addr:7;
++00266 
++00268         unsigned ep_num:4;
++00269 
++00271         unsigned ep_is_in:1;
++00272 
++00280         unsigned speed:2;
++00281 #define DWC_OTG_EP_SPEED_LOW    0
++00282 #define DWC_OTG_EP_SPEED_FULL   1
++00283 #define DWC_OTG_EP_SPEED_HIGH   2
++00284 
++00293         unsigned ep_type:2;
++00294 
++00296         unsigned max_packet:11;
++00297 
++00306         unsigned data_pid_start:2;
++00307 #define DWC_OTG_HC_PID_DATA0 0
++00308 #define DWC_OTG_HC_PID_DATA2 1
++00309 #define DWC_OTG_HC_PID_DATA1 2
++00310 #define DWC_OTG_HC_PID_MDATA 3
++00311 #define DWC_OTG_HC_PID_SETUP 3
++00312 
++00314         unsigned multi_count:2;
++00315 
++00320         uint8_t *xfer_buff;
++00325         dwc_dma_t align_buff;
++00327         uint32_t xfer_len;
++00329         uint32_t xfer_count;
++00331         uint16_t start_pkt_count;
++00332 
++00337         uint8_t xfer_started;
++00338 
++00343         uint8_t do_ping;
++00344 
++00349         uint8_t error_state;
++00350 
++00357         uint8_t halt_on_queue;
++00358 
++00363         uint8_t halt_pending;
++00364 
++00368         dwc_otg_halt_status_e halt_status;
++00369 
++00370         /*
++00371          * Split settings for the host channel
++00372          */
++00373         uint8_t do_split;                  
++00374         uint8_t complete_split;    
++00375         uint8_t hub_addr;                  
++00377         uint8_t port_addr;                 
++00384         uint8_t xact_pos;
++00385 
++00387         uint8_t short_read;
++00388 
++00393         uint8_t requests;
++00394 
++00398         struct dwc_otg_qh *qh;
++00399 
++00403          DWC_CIRCLEQ_ENTRY(dwc_hc) hc_list_entry;
++00404 
++00409         uint16_t ntd;
++00410 
++00412         dwc_dma_t desc_list_addr;
++00413 
++00415         uint8_t schinfo;
++00416 
++00418 } dwc_hc_t;
++00419 
++00424 typedef struct dwc_otg_core_params {
++00425         int32_t opt;
++00426 
++00434         int32_t otg_cap;
++00435 
++00443         int32_t dma_enable;
++00444 
++00452         int32_t dma_desc_enable;
++00456         int32_t dma_burst_size; /* Translate this to GAHBCFG values */
++00457 
++00466         int32_t speed;
++00472         int32_t host_support_fs_ls_low_power;
++00473 
++00482         int32_t host_ls_low_power_phy_clk;
++00483 
++00488         int32_t enable_dynamic_fifo;
++00489 
++00496         int32_t data_fifo_size;
++00497 
++00502         int32_t dev_rx_fifo_size;
++00503 
++00508         int32_t dev_nperio_tx_fifo_size;
++00509 
++00514         uint32_t dev_perio_tx_fifo_size[MAX_PERIO_FIFOS];
++00515 
++00520         int32_t host_rx_fifo_size;
++00521 
++00526         int32_t host_nperio_tx_fifo_size;
++00527 
++00532         int32_t host_perio_tx_fifo_size;
++00533 
++00537         int32_t max_transfer_size;
++00538 
++00542         int32_t max_packet_count;
++00543 
++00548         int32_t host_channels;
++00549 
++00556         int32_t dev_endpoints;
++00557 
++00566         int32_t phy_type;
++00567 
++00579         int32_t phy_utmi_width;
++00580 
++00591         int32_t phy_ulpi_ddr;
++00592 
++00597         int32_t phy_ulpi_ext_vbus;
++00598 
++00605         int32_t i2c_enable;
++00606 
++00607         int32_t ulpi_fs_ls;
++00608 
++00609         int32_t ts_dline;
++00610 
++00617         int32_t en_multiple_tx_fifo;
++00618 
++00623         uint32_t dev_tx_fifo_size[MAX_TX_FIFOS];
++00624 
++00630         uint32_t thr_ctl;
++00631 
++00635         uint32_t tx_thr_length;
++00636 
++00640         uint32_t rx_thr_length;
++00641 
++00645         int32_t lpm_enable;
++00646 
++00652         int32_t pti_enable;
++00653 
++00659         int32_t mpi_enable;
++00660 
++00665         int32_t ic_usb_cap;
++00666 
++00673         int32_t ahb_thr_ratio;
++00674 
++00679         int32_t adp_supp_enable;
++00680 
++00685         int32_t reload_ctl;
++00686 
++00691         int32_t dev_out_nak;
++00692 
++00699         int32_t cont_on_bna;
++00700 
++00707         int32_t ahb_single;
++00708 
++00714         int32_t power_down;
++00715 
++00720         int32_t otg_ver;
++00721 
++00722 } dwc_otg_core_params_t;
++00723 
++00724 #ifdef DEBUG
++00725 struct dwc_otg_core_if;
++00726 typedef struct hc_xfer_info {
++00727         struct dwc_otg_core_if *core_if;
++00728         dwc_hc_t *hc;
++00729 } hc_xfer_info_t;
++00730 #endif
++00731 
++00732 typedef struct ep_xfer_info {
++00733         struct dwc_otg_core_if *core_if;
++00734         dwc_ep_t *ep;
++00735         uint8_t state;
++00736 } ep_xfer_info_t;
++00737 /*
++00738  * Device States
++00739  */
++00740 typedef enum dwc_otg_lx_state {
++00742         DWC_OTG_L0,
++00744         DWC_OTG_L1,
++00746         DWC_OTG_L2,
++00748         DWC_OTG_L3
++00749 } dwc_otg_lx_state_e;
++00750 
++00751 struct dwc_otg_global_regs_backup {
++00752         uint32_t gotgctl_local;
++00753         uint32_t gintmsk_local;
++00754         uint32_t gahbcfg_local;
++00755         uint32_t gusbcfg_local;
++00756         uint32_t grxfsiz_local;
++00757         uint32_t gnptxfsiz_local;
++00758 #ifdef CONFIG_USB_DWC_OTG_LPM
++00759         uint32_t glpmcfg_local;
++00760 #endif
++00761         uint32_t gi2cctl_local;
++00762         uint32_t hptxfsiz_local;
++00763         uint32_t pcgcctl_local;
++00764         uint32_t gdfifocfg_local;
++00765         uint32_t dtxfsiz_local[MAX_EPS_CHANNELS];
++00766         uint32_t gpwrdn_local;
++00767 };
++00768 
++00769 struct dwc_otg_host_regs_backup {
++00770         uint32_t hcfg_local;
++00771         uint32_t haintmsk_local;
++00772         uint32_t hcintmsk_local[MAX_EPS_CHANNELS];
++00773         uint32_t hprt0_local;
++00774         uint32_t hfir_local;
++00775 };
++00776 
++00777 struct dwc_otg_dev_regs_backup {
++00778         uint32_t dcfg;
++00779         uint32_t dctl;
++00780         uint32_t daintmsk;
++00781         uint32_t diepmsk;
++00782         uint32_t doepmsk;
++00783         uint32_t diepctl[MAX_EPS_CHANNELS];
++00784         uint32_t dieptsiz[MAX_EPS_CHANNELS];
++00785         uint32_t diepdma[MAX_EPS_CHANNELS];
++00786 };
++00792 struct dwc_otg_core_if {
++00794         dwc_otg_core_params_t *core_params;
++00795 
++00797         dwc_otg_core_global_regs_t *core_global_regs;
++00798 
++00800         dwc_otg_dev_if_t *dev_if;
++00802         dwc_otg_host_if_t *host_if;
++00803 
++00805         uint32_t snpsid;
++00806 
++00807         /*
++00808          * Set to 1 if the core PHY interface bits in USBCFG have been
++00809          * initialized.
++00810          */
++00811         uint8_t phy_init_done;
++00812 
++00813         /*
++00814          * SRP Success flag, set by srp success interrupt in FS I2C mode
++00815          */
++00816         uint8_t srp_success;
++00817         uint8_t srp_timer_started;
++00820         dwc_timer_t *srp_timer;
++00821 
++00822 #ifdef DWC_DEV_SRPCAP
++00823         /* This timer is needed to power on the hibernated host core if SRP is not
++00824          * initiated on connected SRP capable device for limited period of time
++00825          */
++00826         uint8_t pwron_timer_started;
++00827         dwc_timer_t *pwron_timer;
++00828 #endif
++00829         /* Common configuration information */
++00831         volatile uint32_t *pcgcctl;
++00832 #define DWC_OTG_PCGCCTL_OFFSET 0xE00
++00833 
++00835         uint32_t *data_fifo[MAX_EPS_CHANNELS];
++00836 #define DWC_OTG_DATA_FIFO_OFFSET 0x1000
++00837 #define DWC_OTG_DATA_FIFO_SIZE 0x1000
++00838 
++00840         uint16_t total_fifo_size;
++00842         uint16_t rx_fifo_size;
++00844         uint16_t nperio_tx_fifo_size;
++00845 
++00847         uint8_t dma_enable;
++00848 
++00850         uint8_t dma_desc_enable;
++00851 
++00853         uint8_t pti_enh_enable;
++00854 
++00856         uint8_t multiproc_int_enable;
++00857 
++00859         uint8_t en_multiple_tx_fifo;
++00860 
++00863         uint8_t queuing_high_bandwidth;
++00864 
++00866         hwcfg1_data_t hwcfg1;
++00867         hwcfg2_data_t hwcfg2;
++00868         hwcfg3_data_t hwcfg3;
++00869         hwcfg4_data_t hwcfg4;
++00870         fifosize_data_t hptxfsiz;
++00871 
++00873         hcfg_data_t hcfg;
++00874         dcfg_data_t dcfg;
++00875 
++00881         uint8_t op_state;
++00882 
++00888         uint8_t restart_hcd_on_session_req;
++00889 
++00892 #define A_HOST          (1)
++00893 
++00894 #define A_SUSPEND       (2)
++00895 
++00896 #define A_PERIPHERAL    (3)
++00897 
++00898 #define B_PERIPHERAL    (4)
++00899 
++00900 #define B_HOST          (5)
++00901 
++00903         struct dwc_otg_cil_callbacks *hcd_cb;
++00905         struct dwc_otg_cil_callbacks *pcd_cb;
++00906 
++00908         uint32_t p_tx_msk;
++00910         uint32_t tx_msk;
++00911 
++00913         dwc_workq_t *wq_otg;
++00914 
++00916         dwc_timer_t *wkp_timer;
++00918         uint32_t start_doeptsiz_val[MAX_EPS_CHANNELS];
++00919         ep_xfer_info_t ep_xfer_info[MAX_EPS_CHANNELS];
++00920         dwc_timer_t *ep_xfer_timer[MAX_EPS_CHANNELS];
++00921 #ifdef DEBUG
++00922         uint32_t start_hcchar_val[MAX_EPS_CHANNELS];
++00923 
++00924         hc_xfer_info_t hc_xfer_info[MAX_EPS_CHANNELS];
++00925         dwc_timer_t *hc_xfer_timer[MAX_EPS_CHANNELS];
++00926 
++00927         uint32_t hfnum_7_samples;
++00928         uint64_t hfnum_7_frrem_accum;
++00929         uint32_t hfnum_0_samples;
++00930         uint64_t hfnum_0_frrem_accum;
++00931         uint32_t hfnum_other_samples;
++00932         uint64_t hfnum_other_frrem_accum;
++00933 #endif
++00934 
++00935 #ifdef DWC_UTE_CFI
++00936         uint16_t pwron_rxfsiz;
++00937         uint16_t pwron_gnptxfsiz;
++00938         uint16_t pwron_txfsiz[15];
++00939 
++00940         uint16_t init_rxfsiz;
++00941         uint16_t init_gnptxfsiz;
++00942         uint16_t init_txfsiz[15];
++00943 #endif
++00944 
++00946         dwc_otg_lx_state_e lx_state;
++00947 
++00949         struct dwc_otg_global_regs_backup *gr_backup;
++00951         struct dwc_otg_host_regs_backup *hr_backup;
++00953         struct dwc_otg_dev_regs_backup *dr_backup;
++00954 
++00956         uint32_t power_down;
++00957 
++00959         uint32_t adp_enable;
++00960 
++00962         dwc_otg_adp_t adp;
++00963 
++00965         int hibernation_suspend;
++00966 
++00968         uint32_t otg_ver;
++00969 
++00971         uint8_t otg_sts;
++00972 
++00974         dwc_spinlock_t *lock;
++00975 
++00978         uint8_t start_predict;
++00979 
++00982         uint8_t nextep_seq[MAX_EPS_CHANNELS];
++00983 
++00985         uint8_t first_in_nextep_seq;
++00986 
++00988         uint32_t frame_num; 
++00989 
++00990 };
++00991 
++00992 #ifdef DEBUG
++00993 /*
++00994  * This function is called when transfer is timed out.
++00995  */
++00996 extern void hc_xfer_timeout(void *ptr);
++00997 #endif
++00998 
++00999 /*
++01000  * This function is called when transfer is timed out on endpoint.
++01001  */
++01002 extern void ep_xfer_timeout(void *ptr);
++01003 
++01004 /*
++01005  * The following functions are functions for works
++01006  * using during handling some interrupts
++01007  */
++01008 extern void w_conn_id_status_change(void *p);
++01009 
++01010 extern void w_wakeup_detected(void *p);
++01011 
++01013 extern int dwc_otg_save_global_regs(dwc_otg_core_if_t * core_if);
++01015 extern int dwc_otg_save_dev_regs(dwc_otg_core_if_t * core_if);
++01017 extern int dwc_otg_save_host_regs(dwc_otg_core_if_t * core_if);
++01019 extern int dwc_otg_restore_global_regs(dwc_otg_core_if_t * core_if);
++01021 extern int dwc_otg_restore_host_regs(dwc_otg_core_if_t * core_if, int reset);
++01023 extern int dwc_otg_restore_dev_regs(dwc_otg_core_if_t * core_if,
++01024                                     int rem_wakeup);
++01025 extern int restore_lpm_i2c_regs(dwc_otg_core_if_t * core_if);
++01026 extern int restore_essential_regs(dwc_otg_core_if_t * core_if, int rmode,
++01027                                   int is_host);
++01028 
++01029 extern int dwc_otg_host_hibernation_restore(dwc_otg_core_if_t * core_if,
++01030                                             int restore_mode, int reset);
++01031 extern int dwc_otg_device_hibernation_restore(dwc_otg_core_if_t * core_if,
++01032                                               int rem_wakeup, int reset);
++01033 
++01034 /*
++01035  * The following functions support initialization of the CIL driver component
++01036  * and the DWC_otg controller.
++01037  */
++01038 extern void dwc_otg_core_host_init(dwc_otg_core_if_t * _core_if);
++01039 extern void dwc_otg_core_dev_init(dwc_otg_core_if_t * _core_if);
++01040 
++01046 extern void dwc_otg_wakeup(dwc_otg_core_if_t * _core_if);
++01047 extern void dwc_otg_read_setup_packet(dwc_otg_core_if_t * _core_if,
++01048                                       uint32_t * _dest);
++01049 extern uint32_t dwc_otg_get_frame_number(dwc_otg_core_if_t * _core_if);
++01050 extern void dwc_otg_ep0_activate(dwc_otg_core_if_t * _core_if, dwc_ep_t * _ep);
++01051 extern void dwc_otg_ep_activate(dwc_otg_core_if_t * _core_if, dwc_ep_t * _ep);
++01052 extern void dwc_otg_ep_deactivate(dwc_otg_core_if_t * _core_if, dwc_ep_t * _ep);
++01053 extern void dwc_otg_ep_start_transfer(dwc_otg_core_if_t * _core_if,
++01054                                       dwc_ep_t * _ep);
++01055 extern void dwc_otg_ep_start_zl_transfer(dwc_otg_core_if_t * _core_if,
++01056                                          dwc_ep_t * _ep);
++01057 extern void dwc_otg_ep0_start_transfer(dwc_otg_core_if_t * _core_if,
++01058                                        dwc_ep_t * _ep);
++01059 extern void dwc_otg_ep0_continue_transfer(dwc_otg_core_if_t * _core_if,
++01060                                           dwc_ep_t * _ep);
++01061 extern void dwc_otg_ep_write_packet(dwc_otg_core_if_t * _core_if,
++01062                                     dwc_ep_t * _ep, int _dma);
++01063 extern void dwc_otg_ep_set_stall(dwc_otg_core_if_t * _core_if, dwc_ep_t * _ep);
++01064 extern void dwc_otg_ep_clear_stall(dwc_otg_core_if_t * _core_if,
++01065                                    dwc_ep_t * _ep);
++01066 extern void dwc_otg_enable_device_interrupts(dwc_otg_core_if_t * _core_if);
++01067 
++01068 #ifdef DWC_EN_ISOC
++01069 extern void dwc_otg_iso_ep_start_frm_transfer(dwc_otg_core_if_t * core_if,
++01070                                               dwc_ep_t * ep);
++01071 extern void dwc_otg_iso_ep_start_buf_transfer(dwc_otg_core_if_t * core_if,
++01072                                               dwc_ep_t * ep);
++01073 #endif /* DWC_EN_ISOC */
++01074 
++01081 extern void dwc_otg_hc_init(dwc_otg_core_if_t * _core_if, dwc_hc_t * _hc);
++01082 extern void dwc_otg_hc_halt(dwc_otg_core_if_t * _core_if,
++01083                             dwc_hc_t * _hc, dwc_otg_halt_status_e _halt_status);
++01084 extern void dwc_otg_hc_cleanup(dwc_otg_core_if_t * _core_if, dwc_hc_t * _hc);
++01085 extern void dwc_otg_hc_start_transfer(dwc_otg_core_if_t * _core_if,
++01086                                       dwc_hc_t * _hc);
++01087 extern int dwc_otg_hc_continue_transfer(dwc_otg_core_if_t * _core_if,
++01088                                         dwc_hc_t * _hc);
++01089 extern void dwc_otg_hc_do_ping(dwc_otg_core_if_t * _core_if, dwc_hc_t * _hc);
++01090 extern void dwc_otg_hc_write_packet(dwc_otg_core_if_t * _core_if,
++01091                                     dwc_hc_t * _hc);
++01092 extern void dwc_otg_enable_host_interrupts(dwc_otg_core_if_t * _core_if);
++01093 extern void dwc_otg_disable_host_interrupts(dwc_otg_core_if_t * _core_if);
++01094 
++01095 extern void dwc_otg_hc_start_transfer_ddma(dwc_otg_core_if_t * core_if,
++01096                                            dwc_hc_t * hc);
++01097 
++01098 extern uint32_t calc_frame_interval(dwc_otg_core_if_t * core_if);
++01099 
++01100 /* Macro used to clear one channel interrupt */
++01101 #define clear_hc_int(_hc_regs_, _intr_) \
++01102 do { \
++01103         hcint_data_t hcint_clear = {.d32 = 0}; \
++01104         hcint_clear.b._intr_ = 1; \
++01105         DWC_WRITE_REG32(&(_hc_regs_)->hcint, hcint_clear.d32); \
++01106 } while (0)
++01107 
++01108 /*
++01109  * Macro used to disable one channel interrupt. Channel interrupts are
++01110  * disabled when the channel is halted or released by the interrupt handler.
++01111  * There is no need to handle further interrupts of that type until the
++01112  * channel is re-assigned. In fact, subsequent handling may cause crashes
++01113  * because the channel structures are cleaned up when the channel is released.
++01114  */
++01115 #define disable_hc_int(_hc_regs_, _intr_) \
++01116 do { \
++01117         hcintmsk_data_t hcintmsk = {.d32 = 0}; \
++01118         hcintmsk.b._intr_ = 1; \
++01119         DWC_MODIFY_REG32(&(_hc_regs_)->hcintmsk, hcintmsk.d32, 0); \
++01120 } while (0)
++01121 
++01127 static inline uint32_t dwc_otg_read_hprt0(dwc_otg_core_if_t * _core_if)
++01128 {
++01129         hprt0_data_t hprt0;
++01130         hprt0.d32 = DWC_READ_REG32(_core_if->host_if->hprt0);
++01131         hprt0.b.prtena = 0;
++01132         hprt0.b.prtconndet = 0;
++01133         hprt0.b.prtenchng = 0;
++01134         hprt0.b.prtovrcurrchng = 0;
++01135         return hprt0.d32;
++01136 }
++01137 
++01146 extern void dwc_otg_read_packet(dwc_otg_core_if_t * core_if,
++01147                                 uint8_t * dest, uint16_t bytes);
++01148 
++01149 extern void dwc_otg_flush_tx_fifo(dwc_otg_core_if_t * _core_if, const int _num);
++01150 extern void dwc_otg_flush_rx_fifo(dwc_otg_core_if_t * _core_if);
++01151 extern void dwc_otg_core_reset(dwc_otg_core_if_t * _core_if);
++01152 
++01156 static inline uint32_t dwc_otg_read_core_intr(dwc_otg_core_if_t * core_if)
++01157 {
++01158         return (DWC_READ_REG32(&core_if->core_global_regs->gintsts) &
++01159                 DWC_READ_REG32(&core_if->core_global_regs->gintmsk));
++01160 }
++01161 
++01165 static inline uint32_t dwc_otg_read_otg_intr(dwc_otg_core_if_t * core_if)
++01166 {
++01167         return (DWC_READ_REG32(&core_if->core_global_regs->gotgint));
++01168 }
++01169 
++01174 static inline uint32_t dwc_otg_read_dev_all_in_ep_intr(dwc_otg_core_if_t *
++01175                                                        core_if)
++01176 {
++01177 
++01178         uint32_t v;
++01179 
++01180         if (core_if->multiproc_int_enable) {
++01181                 v = DWC_READ_REG32(&core_if->dev_if->
++01182                                    dev_global_regs->deachint) &
++01183                     DWC_READ_REG32(&core_if->
++01184                                    dev_if->dev_global_regs->deachintmsk);
++01185         } else {
++01186                 v = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->daint) &
++01187                     DWC_READ_REG32(&core_if->dev_if->dev_global_regs->daintmsk);
++01188         }
++01189         return (v & 0xffff);
++01190 }
++01191 
++01196 static inline uint32_t dwc_otg_read_dev_all_out_ep_intr(dwc_otg_core_if_t *
++01197                                                         core_if)
++01198 {
++01199         uint32_t v;
++01200 
++01201         if (core_if->multiproc_int_enable) {
++01202                 v = DWC_READ_REG32(&core_if->dev_if->
++01203                                    dev_global_regs->deachint) &
++01204                     DWC_READ_REG32(&core_if->
++01205                                    dev_if->dev_global_regs->deachintmsk);
++01206         } else {
++01207                 v = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->daint) &
++01208                     DWC_READ_REG32(&core_if->dev_if->dev_global_regs->daintmsk);
++01209         }
++01210 
++01211         return ((v & 0xffff0000) >> 16);
++01212 }
++01213 
++01217 static inline uint32_t dwc_otg_read_dev_in_ep_intr(dwc_otg_core_if_t * core_if,
++01218                                                    dwc_ep_t * ep)
++01219 {
++01220         dwc_otg_dev_if_t *dev_if = core_if->dev_if;
++01221         uint32_t v, msk, emp;
++01222 
++01223         if (core_if->multiproc_int_enable) {
++01224                 msk =
++01225                     DWC_READ_REG32(&dev_if->
++01226                                    dev_global_regs->diepeachintmsk[ep->num]);
++01227                 emp =
++01228                     DWC_READ_REG32(&dev_if->
++01229                                    dev_global_regs->dtknqr4_fifoemptymsk);
++01230                 msk |= ((emp >> ep->num) & 0x1) << 7;
++01231                 v = DWC_READ_REG32(&dev_if->in_ep_regs[ep->num]->diepint) & msk;
++01232         } else {
++01233                 msk = DWC_READ_REG32(&dev_if->dev_global_regs->diepmsk);
++01234                 emp =
++01235                     DWC_READ_REG32(&dev_if->
++01236                                    dev_global_regs->dtknqr4_fifoemptymsk);
++01237                 msk |= ((emp >> ep->num) & 0x1) << 7;
++01238                 v = DWC_READ_REG32(&dev_if->in_ep_regs[ep->num]->diepint) & msk;
++01239         }
++01240 
++01241         return v;
++01242 }
++01243 
++01247 static inline uint32_t dwc_otg_read_dev_out_ep_intr(dwc_otg_core_if_t *
++01248                                                     _core_if, dwc_ep_t * _ep)
++01249 {
++01250         dwc_otg_dev_if_t *dev_if = _core_if->dev_if;
++01251         uint32_t v;
++01252         doepmsk_data_t msk = {.d32 = 0 };
++01253 
++01254         if (_core_if->multiproc_int_enable) {
++01255                 msk.d32 =
++01256                     DWC_READ_REG32(&dev_if->
++01257                                    dev_global_regs->doepeachintmsk[_ep->num]);
++01258                 if (_core_if->pti_enh_enable) {
++01259                         msk.b.pktdrpsts = 1;
++01260                 }
++01261                 v = DWC_READ_REG32(&dev_if->
++01262                                    out_ep_regs[_ep->num]->doepint) & msk.d32;
++01263         } else {
++01264                 msk.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->doepmsk);
++01265                 if (_core_if->pti_enh_enable) {
++01266                         msk.b.pktdrpsts = 1;
++01267                 }
++01268                 v = DWC_READ_REG32(&dev_if->
++01269                                    out_ep_regs[_ep->num]->doepint) & msk.d32;
++01270         }
++01271         return v;
++01272 }
++01273 
++01277 static inline uint32_t dwc_otg_read_host_all_channels_intr(dwc_otg_core_if_t *
++01278                                                            _core_if)
++01279 {
++01280         return (DWC_READ_REG32(&_core_if->host_if->host_global_regs->haint));
++01281 }
++01282 
++01283 static inline uint32_t dwc_otg_read_host_channel_intr(dwc_otg_core_if_t *
++01284                                                       _core_if, dwc_hc_t * _hc)
++01285 {
++01286         return (DWC_READ_REG32
++01287                 (&_core_if->host_if->hc_regs[_hc->hc_num]->hcint));
++01288 }
++01289 
++01295 static inline uint32_t dwc_otg_mode(dwc_otg_core_if_t * _core_if)
++01296 {
++01297         return (DWC_READ_REG32(&_core_if->core_global_regs->gintsts) & 0x1);
++01298 }
++01299 
++01307 typedef struct dwc_otg_cil_callbacks {
++01309         int (*start) (void *_p);
++01311         int (*stop) (void *_p);
++01313         int (*disconnect) (void *_p);
++01315         int (*resume_wakeup) (void *_p);
++01317         int (*suspend) (void *_p);
++01319         int (*session_start) (void *_p);
++01320 #ifdef CONFIG_USB_DWC_OTG_LPM
++01321 
++01322         int (*sleep) (void *_p);
++01323 #endif
++01324 
++01325         void *p;
++01326 } dwc_otg_cil_callbacks_t;
++01327 
++01328 extern void dwc_otg_cil_register_pcd_callbacks(dwc_otg_core_if_t * _core_if,
++01329                                                dwc_otg_cil_callbacks_t * _cb,
++01330                                                void *_p);
++01331 extern void dwc_otg_cil_register_hcd_callbacks(dwc_otg_core_if_t * _core_if,
++01332                                                dwc_otg_cil_callbacks_t * _cb,
++01333                                                void *_p);
++01334 
++01335 void dwc_otg_initiate_srp(dwc_otg_core_if_t * core_if);
++01336 
++01338 
++01342 static inline void cil_hcd_start(dwc_otg_core_if_t * core_if)
++01343 {
++01344         if (core_if->hcd_cb && core_if->hcd_cb->start) {
++01345                 core_if->hcd_cb->start(core_if->hcd_cb->p);
++01346         }
++01347 }
++01348 
++01353 static inline void cil_hcd_stop(dwc_otg_core_if_t * core_if)
++01354 {
++01355         if (core_if->hcd_cb && core_if->hcd_cb->stop) {
++01356                 core_if->hcd_cb->stop(core_if->hcd_cb->p);
++01357         }
++01358 }
++01359 
++01364 static inline void cil_hcd_disconnect(dwc_otg_core_if_t * core_if)
++01365 {
++01366         if (core_if->hcd_cb && core_if->hcd_cb->disconnect) {
++01367                 core_if->hcd_cb->disconnect(core_if->hcd_cb->p);
++01368         }
++01369 }
++01370 
++01376 static inline void cil_hcd_session_start(dwc_otg_core_if_t * core_if)
++01377 {
++01378         if (core_if->hcd_cb && core_if->hcd_cb->session_start) {
++01379                 core_if->hcd_cb->session_start(core_if->hcd_cb->p);
++01380         }
++01381 }
++01382 
++01383 #ifdef CONFIG_USB_DWC_OTG_LPM
++01384 
++01390 static inline void cil_hcd_sleep(dwc_otg_core_if_t * core_if)
++01391 {
++01392         if (core_if->hcd_cb && core_if->hcd_cb->sleep) {
++01393                 core_if->hcd_cb->sleep(core_if->hcd_cb->p);
++01394         }
++01395 }
++01396 #endif
++01397 
++01402 static inline void cil_hcd_resume(dwc_otg_core_if_t * core_if)
++01403 {
++01404         if (core_if->hcd_cb && core_if->hcd_cb->resume_wakeup) {
++01405                 core_if->hcd_cb->resume_wakeup(core_if->hcd_cb->p);
++01406         }
++01407 }
++01408 
++01413 static inline void cil_pcd_start(dwc_otg_core_if_t * core_if)
++01414 {
++01415         if (core_if->pcd_cb && core_if->pcd_cb->start) {
++01416                 core_if->pcd_cb->start(core_if->pcd_cb->p);
++01417         }
++01418 }
++01419 
++01424 static inline void cil_pcd_stop(dwc_otg_core_if_t * core_if)
++01425 {
++01426         if (core_if->pcd_cb && core_if->pcd_cb->stop) {
++01427                 core_if->pcd_cb->stop(core_if->pcd_cb->p);
++01428         }
++01429 }
++01430 
++01435 static inline void cil_pcd_suspend(dwc_otg_core_if_t * core_if)
++01436 {
++01437         if (core_if->pcd_cb && core_if->pcd_cb->suspend) {
++01438                 core_if->pcd_cb->suspend(core_if->pcd_cb->p);
++01439         }
++01440 }
++01441 
++01446 static inline void cil_pcd_resume(dwc_otg_core_if_t * core_if)
++01447 {
++01448         if (core_if->pcd_cb && core_if->pcd_cb->resume_wakeup) {
++01449                 core_if->pcd_cb->resume_wakeup(core_if->pcd_cb->p);
++01450         }
++01451 }
++01452 
++01454 
++01455 #endif
++
    Generated on Thu Oct 27 03:56:37 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
    ++doxygen 1.3.9.1
    + + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__cil_8h.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/dwc__otg__cil_8h.html 2013-07-26 19:31:20.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__cil_8h.html 2013-07-26 19:34:40.000000000 +0000 +@@ -2,28 +2,16 @@ + + DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_cil.h File Reference + +- + +- +-
    +-
    +-
    +-
    ++ ++
    Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
    +

    dwc_otg_cil.h File Reference

    This file contains the interface to the Core Interface Layer. More... +

    +-#include "dwc_os.h"
    +-#include "dwc_list.h"
    +-#include "dwc_otg_dbg.h"
    +-#include "dwc_otg_regs.h"
    +-#include "dwc_otg_core_if.h"
    ++#include "dwc_list.h"
    ++#include "dwc_otg_dbg.h"
    ++#include "dwc_otg_regs.h"
    ++#include "dwc_otg_core_if.h"
    ++#include "dwc_otg_adp.h"
    + +

    + Go to the source code of this file. +@@ -34,269 +22,301 @@ + + + +- ++ + + + + + + ++ ++ ++ ++ ++ ++ ++ ++ + + +- ++ + + + ++ ++ ++ ++ + + +- ++ + +- ++ + +- ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- ++ ++ ++ ++ + + +- + +- ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- ++ + + +- ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ + +- ++ + +- ++ + +- ++ ++ ++ ++ ++ ++ ++ ++ + +- ++ + +- +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ ++ ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ + + + +- ++ + + +- ++ ++ ++ ++ + +- +- ++ + +- ++ ++ + +- +- ++ ++ + +- +- ++ + +- ++ + +- ++ + +- + +- + + +- ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ + +- ++ ++ + +- ++ ++ + +- +- ++ ++ + +- +- ++ + +- +- ++ + +- ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ +
     Information for each ISOC packet. More...
    struct  dwc_ep
     The dwc_ep structure represents the state of a single endpoint when acting in device mode. More...
     The dwc_ep structure represents the state of a single endpoint when acting in device mode. More...
    struct  dwc_hc
     Host channel descriptor. More...
    struct  dwc_otg_core_params
     The following parameters may be specified when starting the module. More...
    struct  ep_xfer_info
    struct  dwc_otg_global_regs_backup
    struct  dwc_otg_host_regs_backup
    struct  dwc_otg_dev_regs_backup
    struct  dwc_otg_core_if
     The dwc_otg_core_if structure contains information needed to manage the DWC_otg controller acting in either host or device mode. More...
     The dwc_otg_core_if structure contains information needed to manage the DWC_otg controller acting in either host or device mode. More...
    struct  dwc_otg_cil_callbacks
     DWC_otg CIL callback structure. More...

    Transfer state

    ++#define MAX_DMA_DESC_CNT   256
     Max DMA Descriptor count for any EP.

    Host CIL Functions

    The following functions support managing the DWC_otg controller in host mode.

    #define clear_hc_int(_hc_regs_, _intr_)
    #define clear_hc_int(_hc_regs_, _intr_)
    #define disable_hc_int(_hc_regs_, _intr_)
    #define disable_hc_int(_hc_regs_, _intr_)
    void dwc_otg_hc_init (dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc)
    void dwc_otg_hc_init (dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc)
     Prepares a host channel for transferring packets to/from a specific endpoint.
    void dwc_otg_hc_halt (dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc, dwc_otg_halt_status_e _halt_status)
     Prepares a host channel for transferring packets to/from a specific endpoint.
    void dwc_otg_hc_halt (dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc, dwc_otg_halt_status_e _halt_status)
     Attempts to halt a host channel.
    void dwc_otg_hc_cleanup (dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc)
     Attempts to halt a host channel.
    void dwc_otg_hc_cleanup (dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc)
     Clears the transfer state for a host channel.
    void dwc_otg_hc_start_transfer (dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc)
     Clears the transfer state for a host channel.
    void dwc_otg_hc_start_transfer (dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc)
     This function does the setup for a data transfer for a host channel and starts the transfer.
    int dwc_otg_hc_continue_transfer (dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc)
     This function does the setup for a data transfer for a host channel and starts the transfer.
    int dwc_otg_hc_continue_transfer (dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc)
     This function continues a data transfer that was started by previous call to dwc_otg_hc_start_transfer.
    void dwc_otg_hc_do_ping (dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc)
     This function continues a data transfer that was started by previous call to dwc_otg_hc_start_transfer.
    void dwc_otg_hc_do_ping (dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc)
     Starts a PING transfer.
    +-void dwc_otg_hc_write_packet (dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc)
     Starts a PING transfer.
    ++void dwc_otg_hc_write_packet (dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc)
    void dwc_otg_enable_host_interrupts (dwc_otg_core_if_t *_core_if)
    void dwc_otg_enable_host_interrupts (dwc_otg_core_if_t *_core_if)
     This function enables the Host mode interrupts.
    void dwc_otg_disable_host_interrupts (dwc_otg_core_if_t *_core_if)
     This function enables the Host mode interrupts.
    void dwc_otg_disable_host_interrupts (dwc_otg_core_if_t *_core_if)
     This function disables the Host Mode interrupts.
    void dwc_otg_hc_start_transfer_ddma (dwc_otg_core_if_t *core_if, dwc_hc_t *hc)
     This function disables the Host Mode interrupts.
    void dwc_otg_hc_start_transfer_ddma (dwc_otg_core_if_t *core_if, dwc_hc_t *hc)
     This function does the setup for a data transfer for a host channel and starts the transfer in Descriptor DMA mode.
    static uint32_t dwc_otg_read_hprt0 (dwc_otg_core_if_t *_core_if)
     This function does the setup for a data transfer for a host channel and starts the transfer in Descriptor DMA mode.
    ++uint32_t calc_frame_interval (dwc_otg_core_if_t *core_if)
     This function Reads HPRT0 in preparation to modify.
     Calculates and gets the frame Interval value of HFIR register according PHY type and speed.The application can modify a value of HFIR register only after the Port Enable bit of the Host Port Control and Status register (HPRT.PrtEnaPort) has been set.
    uint32_t dwc_otg_read_hprt0 (dwc_otg_core_if_t *_core_if)
     This function Reads HPRT0 in preparation to modify.

    Device CIL Functions

    The following functions support managing the DWC_otg controller in device mode.

    ++
    + void dwc_otg_wakeup (dwc_otg_core_if_t *_core_if)
    void dwc_otg_read_setup_packet (dwc_otg_core_if_t *_core_if, uint32_t *_dest)
    void dwc_otg_read_setup_packet (dwc_otg_core_if_t *_core_if, uint32_t *_dest)
     This function reads a setup packet from the Rx FIFO into the destination buffer.
    uint32_t dwc_otg_get_frame_number (dwc_otg_core_if_t *_core_if)
     This function reads a setup packet from the Rx FIFO into the destination buffer.
    uint32_t dwc_otg_get_frame_number (dwc_otg_core_if_t *_core_if)
     Gets the current USB frame number.
    void dwc_otg_ep0_activate (dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep)
     Gets the current USB frame number.
    void dwc_otg_ep0_activate (dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep)
     This function enables EP0 OUT to receive SETUP packets and configures EP0 IN for transmitting packets.
    void dwc_otg_ep_activate (dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep)
     This function enables EP0 OUT to receive SETUP packets and configures EP0 IN for transmitting packets.
    void dwc_otg_ep_activate (dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep)
     This function activates an EP.
    void dwc_otg_ep_deactivate (dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep)
     This function activates an EP.
    void dwc_otg_ep_deactivate (dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep)
     This function deactivates an EP.
    void dwc_otg_ep_start_transfer (dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep)
     This function deactivates an EP.
    void dwc_otg_ep_start_transfer (dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep)
     This function does the setup for a data transfer for an EP and starts the transfer.
    void dwc_otg_ep_start_zl_transfer (dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep)
     This function does the setup for a data transfer for an EP and starts the transfer.
    void dwc_otg_ep_start_zl_transfer (dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep)
     This function setup a zero length transfer in Buffer DMA and Slave modes for usb requests with zero field set.
    void dwc_otg_ep0_start_transfer (dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep)
     This function setup a zero length transfer in Buffer DMA and Slave modes for usb requests with zero field set.
    void dwc_otg_ep0_start_transfer (dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep)
     This function does the setup for a data transfer for EP0 and starts the transfer.
    void dwc_otg_ep0_continue_transfer (dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep)
     This function does the setup for a data transfer for EP0 and starts the transfer.
    void dwc_otg_ep0_continue_transfer (dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep)
     This function continues control IN transfers started by dwc_otg_ep0_start_transfer, when the transfer does not fit in a single packet.
    void dwc_otg_ep_write_packet (dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep, int _dma)
     This function continues control IN transfers started by dwc_otg_ep0_start_transfer, when the transfer does not fit in a single packet.
    void dwc_otg_ep_write_packet (dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep, int _dma)
     This function writes a packet into the Tx FIFO associated with the EP.
    void dwc_otg_ep_set_stall (dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep)
     This function writes a packet into the Tx FIFO associated with the EP.
    void dwc_otg_ep_set_stall (dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep)
     Set the EP STALL.
    void dwc_otg_ep_clear_stall (dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep)
     Set the EP STALL.
    void dwc_otg_ep_clear_stall (dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep)
     Clear the EP STALL.
    void dwc_otg_enable_device_interrupts (dwc_otg_core_if_t *_core_if)
     Clear the EP STALL.
    void dwc_otg_enable_device_interrupts (dwc_otg_core_if_t *_core_if)
     This function enables the Device mode interrupts.
    void dwc_otg_iso_ep_start_frm_transfer (dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
     This function enables the Device mode interrupts.
    void dwc_otg_iso_ep_start_frm_transfer (dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
     This function initializes a descriptor chain for Isochronous transfer.
    void dwc_otg_iso_ep_start_buf_transfer (dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
     This function initializes a descriptor chain for Isochronous transfer.
    void dwc_otg_iso_ep_start_buf_transfer (dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
     This function initializes a descriptor chain for Isochronous transfer.
     This function initializes a descriptor chain for Isochronous transfer.

    Common CIL Functions

    The following functions support managing the DWC_otg controller in either device or host mode.

    void dwc_otg_read_packet (dwc_otg_core_if_t *core_if, uint8_t *dest, uint16_t bytes)
    void dwc_otg_read_packet (dwc_otg_core_if_t *core_if, uint8_t *dest, uint16_t bytes)
     This function reads a packet from the Rx FIFO into the destination buffer.
    void dwc_otg_flush_tx_fifo (dwc_otg_core_if_t *_core_if, const int _num)
     This function reads a packet from the Rx FIFO into the destination buffer.
    void dwc_otg_flush_tx_fifo (dwc_otg_core_if_t *_core_if, const int _num)
     Flush a Tx FIFO.
    void dwc_otg_flush_rx_fifo (dwc_otg_core_if_t *_core_if)
     Flush a Tx FIFO.
    void dwc_otg_flush_rx_fifo (dwc_otg_core_if_t *_core_if)
     Flush Rx FIFO.
    void dwc_otg_core_reset (dwc_otg_core_if_t *_core_if)
     Flush Rx FIFO.
    void dwc_otg_core_reset (dwc_otg_core_if_t *_core_if)
     Do core a soft reset of the core.
    +-static uint32_t dwc_otg_read_core_intr (dwc_otg_core_if_t *core_if)
     Do core a soft reset of the core.
    ++uint32_t dwc_otg_read_core_intr (dwc_otg_core_if_t *core_if)
     This function returns the Core Interrupt register.
    +-static uint32_t dwc_otg_read_otg_intr (dwc_otg_core_if_t *core_if)
    ++uint32_t dwc_otg_read_otg_intr (dwc_otg_core_if_t *core_if)
     This function returns the OTG Interrupt register.
    +-static uint32_t dwc_otg_read_dev_all_in_ep_intr (dwc_otg_core_if_t *core_if)
    ++uint32_t dwc_otg_read_dev_all_in_ep_intr (dwc_otg_core_if_t *core_if)
     This function reads the Device All Endpoints Interrupt register and returns the IN endpoint interrupt bits.
    +-static uint32_t dwc_otg_read_dev_all_out_ep_intr (dwc_otg_core_if_t *core_if)
    ++uint32_t dwc_otg_read_dev_all_out_ep_intr (dwc_otg_core_if_t *core_if)
     This function reads the Device All Endpoints Interrupt register and returns the OUT endpoint interrupt bits.
    +-static uint32_t dwc_otg_read_dev_in_ep_intr (dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
    ++uint32_t dwc_otg_read_dev_in_ep_intr (dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
     This function returns the Device IN EP Interrupt register.
    +-static uint32_t dwc_otg_read_dev_out_ep_intr (dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep)
    ++uint32_t dwc_otg_read_dev_out_ep_intr (dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep)
     This function returns the Device OUT EP Interrupt register.
    +-static uint32_t dwc_otg_read_host_all_channels_intr (dwc_otg_core_if_t *_core_if)
    ++uint32_t dwc_otg_read_host_all_channels_intr (dwc_otg_core_if_t *_core_if)
     This function returns the Host All Channel Interrupt register.
    +-static uint32_t dwc_otg_read_host_channel_intr (dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc)
    ++uint32_t dwc_otg_read_host_channel_intr (dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc)
    static uint32_t dwc_otg_mode (dwc_otg_core_if_t *_core_if)
    uint32_t dwc_otg_mode (dwc_otg_core_if_t *_core_if)
     This function returns the mode of the operation, host or device.
     This function returns the mode of the operation, host or device.

    Defines

    +-#define __DWC_CIL_H__
    ++#define __DWC_CIL_H__
    ++#define OTG_CORE_REV_2_60a   0x4F54260A
     Macros defined for DWC OTG HW Release version.
    ++#define OTG_CORE_REV_2_71a   0x4F54271A
    ++#define OTG_CORE_REV_2_72a   0x4F54272A
    +-#define OTG_CORE_REV_2_60a   0x4F54260A
    ++#define OTG_CORE_REV_2_80a   0x4F54280A
     Macros defined for DWC OTG HW Release verison.
    +-#define OTG_CORE_REV_2_71a   0x4F54271A
    ++#define OTG_CORE_REV_2_81a   0x4F54281A
    +-#define OTG_CORE_REV_2_72a   0x4F54272A
    ++#define OTG_CORE_REV_2_90a   0x4F54290A
    +-#define OTG_CORE_REV_2_80a   0x4F54280A
    ++#define OTG_CORE_REV_2_91a   0x4F54291A
    +-#define OTG_CORE_REV_2_81a   0x4F54281A
    ++#define OTG_CORE_REV_2_92a   0x4F54292A
    +-#define OTG_CORE_REV_2_90a   0x4F54290A
    ++#define OTG_CORE_REV_2_93a   0x4F54293A
    +-#define DWC_OTG_EP_TYPE_CONTROL   0
    ++#define OTG_CORE_REV_2_94a   0x4F54294A
    +-#define DWC_OTG_EP_TYPE_ISOC   1
    ++#define DWC_OTG_EP_TYPE_CONTROL   0
    +-#define DWC_OTG_EP_TYPE_BULK   2
    ++#define DWC_OTG_EP_TYPE_ISOC   1
    +-#define DWC_OTG_EP_TYPE_INTR   3
    ++#define DWC_OTG_EP_TYPE_BULK   2
    +-#define DWC_OTG_EP_SPEED_LOW   0
    ++#define DWC_OTG_EP_TYPE_INTR   3
    +-#define DWC_OTG_EP_SPEED_FULL   1
    ++#define DWC_OTG_EP_SPEED_LOW   0
    +-#define DWC_OTG_EP_SPEED_HIGH   2
    ++#define DWC_OTG_EP_SPEED_FULL   1
    +-#define DWC_OTG_HC_PID_DATA0   0
    ++#define DWC_OTG_EP_SPEED_HIGH   2
    +-#define DWC_OTG_HC_PID_DATA2   1
    ++#define DWC_OTG_HC_PID_DATA0   0
    +-#define DWC_OTG_HC_PID_DATA1   2
    ++#define DWC_OTG_HC_PID_DATA2   1
    +-#define DWC_OTG_HC_PID_MDATA   3
    ++#define DWC_OTG_HC_PID_DATA1   2
    +-#define DWC_OTG_HC_PID_SETUP   3
    ++#define DWC_OTG_HC_PID_MDATA   3
    +-#define DWC_OTG_PCGCCTL_OFFSET   0xE00
    ++#define DWC_OTG_HC_PID_SETUP   3
    +-#define DWC_OTG_DATA_FIFO_OFFSET   0x1000
    ++#define DWC_OTG_PCGCCTL_OFFSET   0xE00
    +-#define DWC_OTG_DATA_FIFO_SIZE   0x1000
    ++#define DWC_OTG_DATA_FIFO_OFFSET   0x1000
    +-#define A_HOST   (1)
    ++#define DWC_OTG_DATA_FIFO_SIZE   0x1000
    ++#define A_HOST   (1)
     A-Device is a_host.
    +-#define A_SUSPEND   (2)
    ++#define A_SUSPEND   (2)
     A-Device is a_suspend.
    +-#define A_PERIPHERAL   (3)
    ++#define A_PERIPHERAL   (3)
     A-Device is a_peripherial.
    +-#define B_PERIPHERAL   (4)
    ++#define B_PERIPHERAL   (4)
     B-Device is operating as a Peripheral.
    +-#define B_HOST   (5)
    ++#define B_HOST   (5)
     B-Device is operating as a Host.

    Typedefs

    +-typedef iso_pkt_info iso_pkt_info_t
    ++typedef iso_pkt_info iso_pkt_info_t
     Information for each ISOC packet.
    typedef dwc_ep dwc_ep_t
    typedef dwc_ep dwc_ep_t
     The dwc_ep structure represents the state of a single endpoint when acting in device mode.
    ++typedef enum dwc_otg_halt_status dwc_otg_halt_status_e
     The dwc_ep structure represents the state of a single endpoint when acting in device mode.
    +-typedef enum dwc_otg_halt_status dwc_otg_halt_status_e
    typedef dwc_hc dwc_hc_t
    typedef dwc_hc dwc_hc_t
     Host channel descriptor.
    typedef dwc_otg_core_params dwc_otg_core_params_t
     Host channel descriptor.
    typedef dwc_otg_core_params dwc_otg_core_params_t
     The following parameters may be specified when starting the module.
    ++typedef ep_xfer_info ep_xfer_info_t
     The following parameters may be specified when starting the module.
    +-typedef enum dwc_otg_lx_state dwc_otg_lx_state_e
    ++typedef enum dwc_otg_lx_state dwc_otg_lx_state_e
    typedef dwc_otg_cil_callbacks dwc_otg_cil_callbacks_t
    typedef dwc_otg_cil_callbacks dwc_otg_cil_callbacks_t
     DWC_otg CIL callback structure.
     DWC_otg CIL callback structure.

    Enumerations

    enum  dwc_otg_halt_status {
    ++
    enum  dwc_otg_halt_status {
    +   DWC_OTG_HC_XFER_NO_HALT_STATUS, + DWC_OTG_HC_XFER_COMPLETE, + DWC_OTG_HC_XFER_URB_COMPLETE, +@@ -317,30 +337,99 @@ +
    + }
    enum  dwc_otg_lx_state { DWC_OTG_L0, +-DWC_OTG_L1, +-DWC_OTG_L2, +-DWC_OTG_L3 ++
    enum  dwc_otg_lx_state { DWC_OTG_L0, ++DWC_OTG_L1, ++DWC_OTG_L2, ++DWC_OTG_L3 + }

    Functions

    +-void w_conn_id_status_change (void *p)
    ++void ep_xfer_timeout (void *ptr)
    ++void w_conn_id_status_change (void *p)
    void w_wakeup_detected (void *p)
    ++int dwc_otg_save_global_regs (dwc_otg_core_if_t *core_if)
     Saves global register values into system memory.
    ++int dwc_otg_save_dev_regs (dwc_otg_core_if_t *core_if)
     Saves device register values into system memory.
    ++int dwc_otg_save_host_regs (dwc_otg_core_if_t *core_if)
     Saves host register values into system memory.
    ++int dwc_otg_restore_global_regs (dwc_otg_core_if_t *core_if)
    void w_wakeup_detected (void *p)
     Restore global register values.
    ++int dwc_otg_restore_host_regs (dwc_otg_core_if_t *core_if, int reset)
    void dwc_otg_core_host_init (dwc_otg_core_if_t *_core_if)
     Restore host register values.
    ++int dwc_otg_restore_dev_regs (dwc_otg_core_if_t *core_if, int rem_wakeup)
     This function initializes the DWC_otg controller registers for host mode.
    void dwc_otg_core_dev_init (dwc_otg_core_if_t *_core_if)
     Restore device register values.
    ++int restore_lpm_i2c_regs (dwc_otg_core_if_t *core_if)
     This function initializes the DWC_otg controller registers for device mode.
    void dwc_otg_cil_register_pcd_callbacks (dwc_otg_core_if_t *_core_if, dwc_otg_cil_callbacks_t *_cb, void *_p)
    ++int restore_essential_regs (dwc_otg_core_if_t *core_if, int rmode, int is_host)
     Register PCD callbacks.
    void dwc_otg_cil_register_hcd_callbacks (dwc_otg_core_if_t *_core_if, dwc_otg_cil_callbacks_t *_cb, void *_p)
    ++int dwc_otg_host_hibernation_restore (dwc_otg_core_if_t *core_if, int restore_mode, int reset)
     Register HCD callbacks.
    ++int dwc_otg_device_hibernation_restore (dwc_otg_core_if_t *core_if, int rem_wakeup, int reset)
    void dwc_otg_core_host_init (dwc_otg_core_if_t *_core_if)
     This function initializes the DWC_otg controller registers for host mode.
    void dwc_otg_core_dev_init (dwc_otg_core_if_t *_core_if)
     This function initializes the DWC_otg controller registers for device mode.
    void dwc_otg_cil_register_pcd_callbacks (dwc_otg_core_if_t *_core_if, dwc_otg_cil_callbacks_t *_cb, void *_p)
     Register PCD callbacks.
    void dwc_otg_cil_register_hcd_callbacks (dwc_otg_core_if_t *_core_if, dwc_otg_cil_callbacks_t *_cb, void *_p)
     Register HCD callbacks.
    ++void dwc_otg_initiate_srp (dwc_otg_core_if_t *core_if)
    void cil_hcd_start (dwc_otg_core_if_t *core_if)
     Start the HCD.
    void cil_hcd_stop (dwc_otg_core_if_t *core_if)
     Stop the HCD.
    void cil_hcd_disconnect (dwc_otg_core_if_t *core_if)
     Disconnect the HCD.
    void cil_hcd_session_start (dwc_otg_core_if_t *core_if)
     Inform the HCD the a New Session has begun.
    void cil_hcd_resume (dwc_otg_core_if_t *core_if)
     Resume the HCD.
    void cil_pcd_start (dwc_otg_core_if_t *core_if)
     Start the PCD.
    void cil_pcd_stop (dwc_otg_core_if_t *core_if)
     Stop the PCD.
    void cil_pcd_suspend (dwc_otg_core_if_t *core_if)
     Suspend the PCD.
    void cil_pcd_resume (dwc_otg_core_if_t *core_if)
     Resume the PCD.
    +

    Detailed Description

    + This file contains the interface to the Core Interface Layer. +@@ -348,203 +437,275 @@ + +

    + Definition in file dwc_otg_cil.h.

    Define Documentation

    +- +-
    +-
    +- +- +- +- +- +- +- +- +- +- +- ++

    ++

    #define clear_hc_int (_hc_regs_,
    _intr_   ) 
    ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ + +
    #define clear_hc_int ( _hc_regs_,
    _intr_   ) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Value:

    do { \
+         hcint_data_t hcint_clear = {.d32 = 0}; \
+-        hcint_clear.b._intr_ = 1; \
+-        dwc_write_reg32(&(_hc_regs_)->hcint, hcint_clear.d32); \
++        hcint_clear.b._intr_ = 1; \
++        DWC_WRITE_REG32(&(_hc_regs_)->hcint, hcint_clear.d32); \
+ } while (0)
+
    +

    +-Definition at line 903 of file dwc_otg_cil.h. +- +-

    +- +-

    +-
    +- +- +- +- +- +- +- +- +- +- +- ++Definition at line 1101 of file dwc_otg_cil.h. ++ ++
    #define disable_hc_int (_hc_regs_,
    _intr_   ) 
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ + +
    #define disable_hc_int ( _hc_regs_,
    _intr_   ) 
    +- +-
    ++
    ++ ++ ++ ++ ++ ++
    ++   ++ + +

    + Value:

    do { \
+         hcintmsk_data_t hcintmsk = {.d32 = 0}; \
+-        hcintmsk.b._intr_ = 1; \
+-        dwc_modify_reg32(&(_hc_regs_)->hcintmsk, hcintmsk.d32, 0); \
++        hcintmsk.b._intr_ = 1; \
++        DWC_MODIFY_REG32(&(_hc_regs_)->hcintmsk, hcintmsk.d32, 0); \
+ } while (0)
+
    +

    +-Definition at line 917 of file dwc_otg_cil.h. +- +-

    ++Definition at line 1115 of file dwc_otg_cil.h.

    +

    Typedef Documentation

    +- +-
    +-
    +- ++

    ++

    ++ ++ ++ ++
    ++ + +- ++ + +
    typedef struct dwc_ep dwc_ep_t typedef struct dwc_ep dwc_ep_t
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + The dwc_ep structure represents the state of a single endpoint when acting in device mode. +

    +-It contains the data items needed for an endpoint to be activated and transfer packets. +- +-

    +- +-

    +-
    +- ++It contains the data items needed for an endpoint to be activated and transfer packets. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- ++ + +
    typedef struct dwc_hc dwc_hc_t typedef struct dwc_hc dwc_hc_t
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Host channel descriptor. +

    +-This structure represents the state of a single host channel when acting in host mode. It contains the data items needed to transfer packets to an endpoint via a host channel. +- +-

    +- +-

    +-
    +- ++This structure represents the state of a single host channel when acting in host mode. It contains the data items needed to transfer packets to an endpoint via a host channel. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- ++ + +
    typedef struct dwc_otg_core_params dwc_otg_core_params_t typedef struct dwc_otg_core_params dwc_otg_core_params_t
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + The following parameters may be specified when starting the module. +

    +-These parameters define how the DWC_otg controller should be configured. +- +-

    +- +-

    +-
    +- ++These parameters define how the DWC_otg controller should be configured. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- ++ + +
    typedef struct dwc_otg_cil_callbacks dwc_otg_cil_callbacks_t typedef struct dwc_otg_cil_callbacks dwc_otg_cil_callbacks_t
    +- +-
    ++
    ++ ++ ++ ++ ++ ++
    ++   ++ + +

    + DWC_otg CIL callback structure. +

    +-This structure allows the HCD and PCD to register functions used for starting and stopping the PCD and HCD for role change on for a DRD. +- +-

    ++This structure allows the HCD and PCD to register functions used for starting and stopping the PCD and HCD for role change on for a DRD.

    +

    Enumeration Type Documentation

    +- +-
    +-
    +- ++

    ++

    ++ ++ ++ ++
    ++ + +- ++ + +
    enum dwc_otg_lx_state enum dwc_otg_lx_state
    +- +-
    ++
    ++ ++ ++ ++ ++ ++
    ++   ++ + +

    +-

    Enumerator:
    ++
    Enumeration values:
    + +- +- +- +- +
    DWC_OTG_L0  ++
    DWC_OTG_L0  + On state.
    DWC_OTG_L1  ++
    DWC_OTG_L1  + LPM sleep state.
    DWC_OTG_L2  ++
    DWC_OTG_L2  + USB suspend state.
    DWC_OTG_L3  ++
    DWC_OTG_L3  + Off state.
    +
    + +

    +-Definition at line 664 of file dwc_otg_cil.h. +- +-

    ++Definition at line 740 of file dwc_otg_cil.h.

    +

    Function Documentation

    +- +-
    +-
    +- +- +- +- +- +- +- +- ++

    ++

    void w_wakeup_detected (void *  p  ) 
    ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ + +
    void w_wakeup_detected ( void *  p  ) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    +- ++Change to L0 state +

    +-Definition at line 473 of file dwc_otg_cil_intr.c. +- +-

    +- +-

    +-
    +- +- +- +- +- +- +- +- ++Definition at line 398 of file dwc_otg_cil_intr.c. ++ ++
    void dwc_otg_core_host_init (dwc_otg_core_if_t *  core_if  ) 
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ + +
    void dwc_otg_core_host_init ( dwc_otg_core_if_t *  core_if  ) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + This function initializes the DWC_otg controller registers for host mode. +@@ -557,73 +718,84 @@ + + +

    +-Definition at line 1196 of file dwc_otg_cil.c. +- +-

    +- +-

    +-
    +- +- +- +- +- +- +- +- ++Definition at line 2019 of file dwc_otg_cil.c. ++ ++
    void dwc_otg_core_dev_init (dwc_otg_core_if_t *  core_if  ) 
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ + +
    void dwc_otg_core_dev_init ( dwc_otg_core_if_t *  core_if  ) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + This function initializes the DWC_otg controller registers for device mode. +

    +

    Parameters:
    + +- ++ +
    core_if Programming view of DWC_otg controller
    core_if Programming view of DWC_otg controller
    +
    +- +-

    +-Set Periodic Tx FIFO Mask all bits 0

    +-Set Tx FIFO Mask all bits 0

    +-

    Todo:
    NGS: Fix Periodic FIFO Sizing!
    +-

    +-

    Todo:
    Finish debug of this
    +

    +-

    Todo:
      +-
    • if the condition needed to be checked or in any case all pending interrutps should be cleared?
    +-
    ++Set Periodic Tx FIFO Mask all bits 0

    ++Set Tx FIFO Mask all bits 0

    ++

    Todo:
    NGS: Fix Periodic FIFO Sizing!

    ++Finish debug of this

    ++- if the condition needed to be checked or in any case all pending interrutps should be cleared?

    + +

    +-Definition at line 843 of file dwc_otg_cil.c. +- +-

    +- +-

    +-
    +- ++Definition at line 1620 of file dwc_otg_cil.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    void dwc_otg_read_setup_packet (dwc_otg_core_if_t *  core_if, void dwc_otg_read_setup_packet ( dwc_otg_core_if_t *  core_if,
    uint32_t *  dest uint32_t *  dest
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + This function reads a setup packet from the Rx FIFO into the destination buffer. +@@ -637,57 +809,73 @@ + + +

    +-Definition at line 2199 of file dwc_otg_cil.c. +- +-

    +- +-

    +-
    +- +- +- +- +- +- +- +- ++Definition at line 3144 of file dwc_otg_cil.c. ++ ++
    uint32_t dwc_otg_get_frame_number (dwc_otg_core_if_t *  core_if  ) 
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ + +
    uint32_t dwc_otg_get_frame_number ( dwc_otg_core_if_t *  core_if  ) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Gets the current USB frame number. +

    + This is the frame number from the last SOF packet. +

    +-Definition at line 2182 of file dwc_otg_cil.c. +- +-

    +- +-

    +-
    +- ++Definition at line 3086 of file dwc_otg_cil.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    void dwc_otg_ep0_activate (dwc_otg_core_if_t *  core_if, void dwc_otg_ep0_activate ( dwc_otg_core_if_t *  core_if,
    dwc_ep_t *  ep dwc_ep_t *  ep
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + This function enables EP0 OUT to receive SETUP packets and configures EP0 IN for transmitting packets. +@@ -701,33 +889,41 @@ + + +

    +-Definition at line 2216 of file dwc_otg_cil.c. +- +-

    +- +-

    +-
    +- ++Definition at line 3161 of file dwc_otg_cil.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    void dwc_otg_ep_activate (dwc_otg_core_if_t *  core_if, void dwc_otg_ep_activate ( dwc_otg_core_if_t *  core_if,
    dwc_ep_t *  ep dwc_ep_t *  ep
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + This function activates an EP. +@@ -741,33 +937,41 @@ + + +

    +-Definition at line 2268 of file dwc_otg_cil.c. +- +-

    +- +-

    +-
    +- ++Definition at line 3214 of file dwc_otg_cil.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    void dwc_otg_ep_deactivate (dwc_otg_core_if_t *  core_if, void dwc_otg_ep_deactivate ( dwc_otg_core_if_t *  core_if,
    dwc_ep_t *  ep dwc_ep_t *  ep
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + This function deactivates an EP. +@@ -781,33 +985,41 @@ + + +

    +-Definition at line 2367 of file dwc_otg_cil.c. +- +-

    +- +-

    +-
    +- ++Definition at line 3369 of file dwc_otg_cil.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    void dwc_otg_ep_start_transfer (dwc_otg_core_if_t *  core_if, void dwc_otg_ep_start_transfer ( dwc_otg_core_if_t *  core_if,
    dwc_ep_t *  ep dwc_ep_t *  ep
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + This function does the setup for a data transfer for an EP and starts the transfer. +@@ -816,42 +1028,50 @@ +

    Parameters:
    + + +- ++ +
    core_if Programming view of DWC_otg controller.
    ep The EP to start the transfer on.
    ep The EP to start the transfer on.
    +
    +- +

    +-DIEPDMAn Register write

    +-Enable the Non-Periodic Tx FIFO empty interrupt, or the Tx FIFO epmty interrupt in dedicated Tx FIFO mode, the data will be written into the fifo by the ISR.

    ++DIEPDMAn Register write

    ++Enable the Non-Periodic Tx FIFO empty interrupt, or the Tx FIFO epmty interrupt in dedicated Tx FIFO mode, the data will be written into the fifo by the ISR.

    ++This is used for interrupt out transfers

    + DOEPDMAn Register write +

    +-Definition at line 2475 of file dwc_otg_cil.c. +- +-

    +- +-

    +-
    +- ++Definition at line 3655 of file dwc_otg_cil.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    void dwc_otg_ep_start_zl_transfer (dwc_otg_core_if_t *  core_if, void dwc_otg_ep_start_zl_transfer ( dwc_otg_core_if_t *  core_if,
    dwc_ep_t *  ep dwc_ep_t *  ep
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + This function setup a zero length transfer in Buffer DMA and Slave modes for usb requests with zero field set. +@@ -859,40 +1079,47 @@ +

    Parameters:
    + + +- ++ +
    core_if Programming view of DWC_otg controller.
    ep The EP to start the transfer on.
    ep The EP to start the transfer on.
    +
    +- +

    +-Enable the Non-Periodic Tx FIFO empty interrupt, or the Tx FIFO epmty interrupt in dedicated Tx FIFO mode, the data will be written into the fifo by the ISR. ++Enable the Non-Periodic Tx FIFO empty interrupt, or the Tx FIFO epmty interrupt in dedicated Tx FIFO mode, the data will be written into the fifo by the ISR. +

    +-Definition at line 2678 of file dwc_otg_cil.c. +- +-

    +- +-

    +-
    +- ++Definition at line 3948 of file dwc_otg_cil.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    void dwc_otg_ep0_start_transfer (dwc_otg_core_if_t *  core_if, void dwc_otg_ep0_start_transfer ( dwc_otg_core_if_t *  core_if,
    dwc_ep_t *  ep dwc_ep_t *  ep
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + This function does the setup for a data transfer for EP0 and starts the transfer. +@@ -901,44 +1128,51 @@ +

    Parameters:
    + + +- ++ +
    core_if Programming view of DWC_otg controller.
    ep The EP0 data.
    ep The EP0 data.
    +
    +- +

    +-DMA Descriptor Setup

    +-DIEPDMA0 Register write

    +-Enable the Non-Periodic Tx FIFO empty interrupt, the data will be written into the fifo by the ISR.

    +-DMA Descriptor Setup

    ++DMA Descriptor Setup

    ++DIEPDMA0 Register write

    ++Enable the Non-Periodic Tx FIFO empty interrupt, the data will be written into the fifo by the ISR.

    ++DMA Descriptor Setup

    + DOEPDMA0 Register write +

    +-Definition at line 2785 of file dwc_otg_cil.c. +- +-

    +- +-

    +-
    +- ++Definition at line 4051 of file dwc_otg_cil.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    void dwc_otg_ep0_continue_transfer (dwc_otg_core_if_t *  core_if, void dwc_otg_ep0_continue_transfer ( dwc_otg_core_if_t *  core_if,
    dwc_ep_t *  ep dwc_ep_t *  ep
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + This function continues control IN transfers started by dwc_otg_ep0_start_transfer, when the transfer does not fit in a single packet. +@@ -947,52 +1181,59 @@ +

    Parameters:
    + + +- ++ +
    core_if Programming view of DWC_otg controller.
    ep The EP0 data.
    ep The EP0 data.
    +
    +- +

    +-

    Todo:
    Should there be check for room in the Tx Status Queue. If not remove the code above this comment.
    ++
    Todo:
    Should there be check for room in the Tx Status Queue. If not remove the code above this comment.
    +

    +-DMA Descriptor Setup

    +-DIEPDMA0 Register write

    +-Enable the Non-Periodic Tx FIFO empty interrupt, the data will be written into the fifo by the ISR.

    +-DMA Descriptor Setup

    ++DMA Descriptor Setup

    ++DIEPDMA0 Register write

    ++Enable the Non-Periodic Tx FIFO empty interrupt, the data will be written into the fifo by the ISR.

    ++DMA Descriptor Setup

    + DOEPDMA0 Register write +

    +-Definition at line 2969 of file dwc_otg_cil.c. +- +-

    +- +-

    +-
    +- ++Definition at line 4239 of file dwc_otg_cil.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    void dwc_otg_ep_write_packet (dwc_otg_core_if_t *  core_if, void dwc_otg_ep_write_packet ( dwc_otg_core_if_t *  core_if,
    dwc_ep_t *  ep, dwc_ep_t *  ep,
    int  dma int  dma
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + This function writes a packet into the Tx FIFO associated with the EP. +@@ -1002,46 +1243,53 @@ + + + +- ++ +
    core_if Programming view of DWC_otg controller.
    ep The EP to write packet for.
    dma Indicates if DMA is being used.
    dma Indicates if DMA is being used.
    + +- +

    + The buffer is padded to DWORD on a per packet basis in slave/dma mode if the MPS is not DWORD aligned. The last packet, if short, is also padded to a multiple of DWORD.

    + ep->xfer_buff always starts DWORD aligned in memory and is a multiple of DWORD in length

    + ep->xfer_len can be any number of bytes

    + ep->xfer_count is a multiple of ep->maxpacket until the last packet

    +-FIFO access is DWORD

    +-

    Todo:
    NGS Where are the Periodic Tx FIFO addresses intialized? What should this be?
    ++FIFO access is DWORD

    ++

    Todo:
    NGS Where are the Periodic Tx FIFO addresses intialized? What should this be?
    + +

    +-Definition at line 3165 of file dwc_otg_cil.c. +- +-

    +- +-

    +-
    +- ++Definition at line 4438 of file dwc_otg_cil.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    void dwc_otg_ep_set_stall (dwc_otg_core_if_t *  core_if, void dwc_otg_ep_set_stall ( dwc_otg_core_if_t *  core_if,
    dwc_ep_t *  ep dwc_ep_t *  ep
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Set the EP STALL. +@@ -1054,33 +1302,41 @@ + + +

    +-Definition at line 3236 of file dwc_otg_cil.c. +- +-

    +- +-

    +-
    +- ++Definition at line 4509 of file dwc_otg_cil.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    void dwc_otg_ep_clear_stall (dwc_otg_core_if_t *  core_if, void dwc_otg_ep_clear_stall ( dwc_otg_core_if_t *  core_if,
    dwc_ep_t *  ep dwc_ep_t *  ep
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Clear the EP STALL. +@@ -1093,65 +1349,80 @@ + + +

    +-Definition at line 3274 of file dwc_otg_cil.c. +- +-

    +- +-

    +-
    +- +- +- +- +- +- +- +- ++Definition at line 4547 of file dwc_otg_cil.c. ++ ++
    void dwc_otg_enable_device_interrupts (dwc_otg_core_if_t *  core_if  ) 
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ + +
    void dwc_otg_enable_device_interrupts ( dwc_otg_core_if_t *  core_if  ) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + This function enables the Device mode interrupts. +

    +

    Parameters:
    + +- ++ +
    core_if Programming view of DWC_otg controller
    core_if Programming view of DWC_otg controller
    +
    +- +

    +-

    Todo:
    NGS: Should this be a module parameter?
    ++
    Todo:
    NGS: Should this be a module parameter?
    + +

    +-Definition at line 772 of file dwc_otg_cil.c. +- +-

    +- +-

    +-
    +- ++Definition at line 1526 of file dwc_otg_cil.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    void dwc_otg_iso_ep_start_frm_transfer (dwc_otg_core_if_t *  core_if, void dwc_otg_iso_ep_start_frm_transfer ( dwc_otg_core_if_t *  core_if,
    dwc_ep_t *  ep dwc_ep_t *  ep
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + This function initializes a descriptor chain for Isochronous transfer. +@@ -1159,40 +1430,47 @@ +

    Parameters:
    + + +- ++ +
    core_if Programming view of DWC_otg controller.
    ep The EP to start the transfer on.
    ep The EP to start the transfer on.
    +
    +- +

    + Enable endpoint, clear nak +

    +-Definition at line 3864 of file dwc_otg_cil.c. +- +-

    +- +-

    +-
    +- ++Definition at line 5161 of file dwc_otg_cil.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    void dwc_otg_iso_ep_start_buf_transfer (dwc_otg_core_if_t *  core_if, void dwc_otg_iso_ep_start_buf_transfer ( dwc_otg_core_if_t *  core_if,
    dwc_ep_t *  ep dwc_ep_t *  ep
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + This function initializes a descriptor chain for Isochronous transfer. +@@ -1200,40 +1478,47 @@ +

    Parameters:
    + + +- ++ +
    core_if Programming view of DWC_otg controller.
    ep The EP to start the transfer on.
    ep The EP to start the transfer on.
    +
    +- +

    + Enable endpoint, clear nak +

    +-Definition at line 517 of file dwc_otg_pcd.c. +- +-

    +- +-

    +-
    +- ++Definition at line 540 of file dwc_otg_pcd.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    void dwc_otg_hc_init (dwc_otg_core_if_t *  core_if, void dwc_otg_hc_init ( dwc_otg_core_if_t *  core_if,
    dwc_hc_t *  hc dwc_hc_t *  hc
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Prepares a host channel for transferring packets to/from a specific endpoint. +@@ -1247,39 +1532,47 @@ + + +

    +-Definition at line 1352 of file dwc_otg_cil.c. +- +-

    +- +-

    +-
    +- ++Definition at line 2206 of file dwc_otg_cil.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    void dwc_otg_hc_halt (dwc_otg_core_if_t *  core_if, void dwc_otg_hc_halt ( dwc_otg_core_if_t *  core_if,
    dwc_hc_t *  hc, dwc_hc_t *  hc,
    dwc_otg_halt_status_e  halt_status dwc_otg_halt_status_e  halt_status
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Attempts to halt a host channel. +@@ -1297,33 +1590,41 @@ + + +

    +-Definition at line 1540 of file dwc_otg_cil.c. +- +-

    +- +-

    +-
    +- ++Definition at line 2394 of file dwc_otg_cil.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    void dwc_otg_hc_cleanup (dwc_otg_core_if_t *  core_if, void dwc_otg_hc_cleanup ( dwc_otg_core_if_t *  core_if,
    dwc_hc_t *  hc dwc_hc_t *  hc
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Clears the transfer state for a host channel. +@@ -1337,33 +1638,41 @@ + + +

    +-Definition at line 1667 of file dwc_otg_cil.c. +- +-

    +- +-

    +-
    +- ++Definition at line 2521 of file dwc_otg_cil.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    void dwc_otg_hc_start_transfer (dwc_otg_core_if_t *  core_if, void dwc_otg_hc_start_transfer ( dwc_otg_core_if_t *  core_if,
    dwc_hc_t *  hc dwc_hc_t *  hc
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + This function does the setup for a data transfer for a host channel and starts the transfer. +@@ -1381,33 +1690,41 @@ + + +

    +-Definition at line 1800 of file dwc_otg_cil.c. +- +-

    +- +-

    +-
    +- ++Definition at line 2703 of file dwc_otg_cil.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    int dwc_otg_hc_continue_transfer (dwc_otg_core_if_t *  core_if, int dwc_otg_hc_continue_transfer ( dwc_otg_core_if_t *  core_if,
    dwc_hc_t *  hc dwc_hc_t *  hc
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + This function continues a data transfer that was started by previous call to dwc_otg_hc_start_transfer. +@@ -1417,57 +1734,73 @@ +

    Returns:
    1 if a new request is queued, 0 if no more requests are required for this transfer.
    + +

    +-Definition at line 2048 of file dwc_otg_cil.c. +- +-

    +- +-

    +-
    +- ++Definition at line 2952 of file dwc_otg_cil.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    void dwc_otg_hc_do_ping (dwc_otg_core_if_t *  core_if, void dwc_otg_hc_do_ping ( dwc_otg_core_if_t *  core_if,
    dwc_hc_t *  hc dwc_hc_t *  hc
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Starts a PING transfer. +

    + This function should only be called in Slave mode. The Do Ping bit is set in the HCTSIZ register, then the channel is enabled. +

    +-Definition at line 2110 of file dwc_otg_cil.c. +- +-

    +- +-

    +-
    +- +- +- +- +- +- +- +- ++Definition at line 3014 of file dwc_otg_cil.c. ++ ++
    void dwc_otg_enable_host_interrupts (dwc_otg_core_if_t *  core_if  ) 
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ + +
    void dwc_otg_enable_host_interrupts ( dwc_otg_core_if_t *  core_if  ) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + This function enables the Host mode interrupts. +@@ -1479,24 +1812,32 @@ + + +

    +-Definition at line 1130 of file dwc_otg_cil.c. +- +-

    +- +-

    +-
    +- +- +- +- +- +- +- +- ++Definition at line 1955 of file dwc_otg_cil.c. ++ ++
    void dwc_otg_disable_host_interrupts (dwc_otg_core_if_t *  core_if  ) 
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ + +
    void dwc_otg_disable_host_interrupts ( dwc_otg_core_if_t *  core_if  ) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + This function disables the Host Mode interrupts. +@@ -1508,33 +1849,41 @@ + + +

    +-Definition at line 1165 of file dwc_otg_cil.c. +- +-

    +- +-

    +-
    +- ++Definition at line 1988 of file dwc_otg_cil.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    void dwc_otg_hc_start_transfer_ddma (dwc_otg_core_if_t *  core_if, void dwc_otg_hc_start_transfer_ddma ( dwc_otg_core_if_t *  core_if,
    dwc_hc_t *  hc dwc_hc_t *  hc
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + This function does the setup for a data transfer for a host channel and starts the transfer in Descriptor DMA mode. +@@ -1549,63 +1898,79 @@ + + +

    +-Definition at line 1968 of file dwc_otg_cil.c. +- +-

    +- +-

    +-
    +- +- +- +- +- +- +- +- ++Definition at line 2872 of file dwc_otg_cil.c. ++ ++
    static uint32_t dwc_otg_read_hprt0 (dwc_otg_core_if_t *  _core_if  )  [inline, static]
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ + +
    uint32_t dwc_otg_read_hprt0 ( dwc_otg_core_if_t *  _core_if  )  [inline, static]
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + This function Reads HPRT0 in preparation to modify. +

    + It keeps the WC bits 0 so that if they are read as 1, they won't clear when you write it back +

    +-Definition at line 929 of file dwc_otg_cil.h. +- +-

    +- +-

    +-
    +- ++Definition at line 1127 of file dwc_otg_cil.h. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    void dwc_otg_read_packet (dwc_otg_core_if_t *  core_if, void dwc_otg_read_packet ( dwc_otg_core_if_t *  core_if,
    uint8_t *  dest, uint8_t *  dest,
    uint16_t  bytes uint16_t  bytes
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + This function reads a packet from the Rx FIFO into the destination buffer. +@@ -1615,41 +1980,48 @@ + + + +- ++ +
    core_if Programming view of DWC_otg controller.
    dest Destination buffer for the packet.
    bytes Number of bytes to copy to the destination.
    bytes Number of bytes to copy to the destination.
    + +- +

    +-

    Todo:
    Account for the case where _dest is not dword aligned. This requires reading data from the FIFO into a uint32_t temp buffer, then moving it into the data buffer.
    ++
    Todo:
    Account for the case where _dest is not dword aligned. This requires reading data from the FIFO into a uint32_t temp buffer, then moving it into the data buffer.
    + +

    +-Definition at line 3317 of file dwc_otg_cil.c. +- +-

    +- +-

    +-
    +- ++Definition at line 4590 of file dwc_otg_cil.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    void dwc_otg_flush_tx_fifo (dwc_otg_core_if_t *  core_if, void dwc_otg_flush_tx_fifo ( dwc_otg_core_if_t *  core_if,
    const int  num const int  num
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Flush a Tx FIFO. +@@ -1662,24 +2034,32 @@ + + +

    +-Definition at line 3662 of file dwc_otg_cil.c. +- +-

    +- +-

    +-
    +- +- +- +- +- +- +- +- ++Definition at line 4959 of file dwc_otg_cil.c. ++ ++
    void dwc_otg_flush_rx_fifo (dwc_otg_core_if_t *  core_if  ) 
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ + +
    void dwc_otg_flush_rx_fifo ( dwc_otg_core_if_t *  core_if  ) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Flush Rx FIFO. +@@ -1691,48 +2071,64 @@ + + +

    +-Definition at line 3694 of file dwc_otg_cil.c. +- +-

    +- +-

    +-
    +- +- +- +- +- +- +- +- ++Definition at line 4991 of file dwc_otg_cil.c. ++ ++
    void dwc_otg_core_reset (dwc_otg_core_if_t *  core_if  ) 
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ + +
    void dwc_otg_core_reset ( dwc_otg_core_if_t *  core_if  ) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Do core a soft reset of the core. +

    + Be careful with this because it resets all the internal state machines of the core. +

    +-Definition at line 3725 of file dwc_otg_cil.c. +- +-

    +- +-

    +-
    +- +- +- +- +- +- +- +- ++Definition at line 5022 of file dwc_otg_cil.c. ++ ++
    static uint32_t dwc_otg_mode (dwc_otg_core_if_t *  _core_if  )  [inline, static]
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ + +
    uint32_t dwc_otg_mode ( dwc_otg_core_if_t *  _core_if  )  [inline, static]
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + This function returns the mode of the operation, host or device. +@@ -1740,39 +2136,47 @@ +

    Returns:
    0 - Device Mode, 1 - Host Mode
    + +

    +-Definition at line 1097 of file dwc_otg_cil.h. +- +-

    +- +-

    +-
    +- ++Definition at line 1295 of file dwc_otg_cil.h. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    void dwc_otg_cil_register_pcd_callbacks (dwc_otg_core_if_t *  core_if, void dwc_otg_cil_register_pcd_callbacks ( dwc_otg_core_if_t *  core_if,
    dwc_otg_cil_callbacks_t *  cb, dwc_otg_cil_callbacks_t *  cb,
    void *  p void *  p
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Register PCD callbacks. +@@ -1787,39 +2191,47 @@ + + +

    +-Definition at line 3796 of file dwc_otg_cil.c. +- +-

    +- +-

    +-
    +- ++Definition at line 5093 of file dwc_otg_cil.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    void dwc_otg_cil_register_hcd_callbacks (dwc_otg_core_if_t *  core_if, void dwc_otg_cil_register_hcd_callbacks ( dwc_otg_core_if_t *  core_if,
    dwc_otg_cil_callbacks_t *  cb, dwc_otg_cil_callbacks_t *  cb,
    void *  p void *  p
    )) 
    +- +-
    ++
    ++ ++ ++ ++ ++ ++
    ++   ++ + +

    + Register HCD callbacks. +@@ -1834,11 +2246,353 @@ + + +

    +-Definition at line 3781 of file dwc_otg_cil.c. +- +-

    +-

    Generated on Tue May 5 02:22:48 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++Definition at line 5078 of file dwc_otg_cil.c.
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
    void cil_hcd_start ( dwc_otg_core_if_t *  core_if  )  [inline, static]
    ++
    ++ ++ ++ ++ ++ ++
    ++   ++ ++ ++

    ++Start the HCD. ++

    ++Helper function for using the HCD callbacks.

    ++

    Parameters:
    ++ ++ ++
    core_if Programming view of DWC_otg controller.
    ++
    ++ ++

    ++Definition at line 1342 of file dwc_otg_cil.h.

    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
    void cil_hcd_stop ( dwc_otg_core_if_t *  core_if  )  [inline, static]
    ++
    ++ ++ ++ ++ ++ ++
    ++   ++ ++ ++

    ++Stop the HCD. ++

    ++Helper function for using the HCD callbacks.

    ++

    Parameters:
    ++ ++ ++
    core_if Programming view of DWC_otg controller.
    ++
    ++ ++

    ++Definition at line 1353 of file dwc_otg_cil.h.

    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
    void cil_hcd_disconnect ( dwc_otg_core_if_t *  core_if  )  [inline, static]
    ++
    ++ ++ ++ ++ ++ ++
    ++   ++ ++ ++

    ++Disconnect the HCD. ++

    ++Helper function for using the HCD callbacks.

    ++

    Parameters:
    ++ ++ ++
    core_if Programming view of DWC_otg controller.
    ++
    ++ ++

    ++Definition at line 1364 of file dwc_otg_cil.h.

    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
    void cil_hcd_session_start ( dwc_otg_core_if_t *  core_if  )  [inline, static]
    ++
    ++ ++ ++ ++ ++ ++
    ++   ++ ++ ++

    ++Inform the HCD the a New Session has begun. ++

    ++Helper function for using the HCD callbacks.

    ++

    Parameters:
    ++ ++ ++
    core_if Programming view of DWC_otg controller.
    ++
    ++ ++

    ++Definition at line 1376 of file dwc_otg_cil.h.

    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
    void cil_hcd_resume ( dwc_otg_core_if_t *  core_if  )  [inline, static]
    ++
    ++ ++ ++ ++ ++ ++
    ++   ++ ++ ++

    ++Resume the HCD. ++

    ++Helper function for using the HCD callbacks.

    ++

    Parameters:
    ++ ++ ++
    core_if Programming view of DWC_otg controller.
    ++
    ++ ++

    ++Definition at line 1402 of file dwc_otg_cil.h.

    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
    void cil_pcd_start ( dwc_otg_core_if_t *  core_if  )  [inline, static]
    ++
    ++ ++ ++ ++ ++ ++
    ++   ++ ++ ++

    ++Start the PCD. ++

    ++Helper function for using the PCD callbacks.

    ++

    Parameters:
    ++ ++ ++
    core_if Programming view of DWC_otg controller.
    ++
    ++ ++

    ++Definition at line 1413 of file dwc_otg_cil.h.

    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
    void cil_pcd_stop ( dwc_otg_core_if_t *  core_if  )  [inline, static]
    ++
    ++ ++ ++ ++ ++ ++
    ++   ++ ++ ++

    ++Stop the PCD. ++

    ++Helper function for using the PCD callbacks.

    ++

    Parameters:
    ++ ++ ++
    core_if Programming view of DWC_otg controller.
    ++
    ++ ++

    ++Definition at line 1424 of file dwc_otg_cil.h.

    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
    void cil_pcd_suspend ( dwc_otg_core_if_t *  core_if  )  [inline, static]
    ++
    ++ ++ ++ ++ ++ ++
    ++   ++ ++ ++

    ++Suspend the PCD. ++

    ++Helper function for using the PCD callbacks.

    ++

    Parameters:
    ++ ++ ++
    core_if Programming view of DWC_otg controller.
    ++
    ++ ++

    ++Definition at line 1435 of file dwc_otg_cil.h.

    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
    void cil_pcd_resume ( dwc_otg_core_if_t *  core_if  )  [inline, static]
    ++
    ++ ++ ++ ++ ++ ++
    ++   ++ ++ ++

    ++Resume the PCD. ++

    ++Helper function for using the PCD callbacks.

    ++

    Parameters:
    ++ ++ ++
    core_if Programming view of DWC_otg controller.
    ++
    ++ ++

    ++Definition at line 1446 of file dwc_otg_cil.h.

    ++

    Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
    ++doxygen 1.3.9.1 + + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__cil__intr_8c-source.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/dwc__otg__cil__intr_8c-source.html 2013-07-26 19:31:20.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__cil__intr_8c-source.html 2013-07-26 19:34:40.000000000 +0000 +@@ -2,741 +2,1296 @@ + + DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_cil_intr.c Source File + +- + +- +-
    +-
    +-
    +-
    +-

    dwc_otg_cil_intr.c

    Go to the documentation of this file.
    00001 /* ==========================================================================
+-00002  * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_cil_intr.c $
+-00003  * $Revision: #15 $
+-00004  * $Date: 2009/04/15 $
+-00005  * $Change: 1234129 $
+-00006  *
+-00007  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
+-00008  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
+-00009  * otherwise expressly agreed to in writing between Synopsys and you.
+-00010  *
+-00011  * The Software IS NOT an item of Licensed Software or Licensed Product under
+-00012  * any End User Software License Agreement or Agreement for Licensed Product
+-00013  * with Synopsys or any supplement thereto. You are permitted to use and
+-00014  * redistribute this Software in source and binary forms, with or without
+-00015  * modification, provided that redistributions of source code must retain this
+-00016  * notice. You may not view, use, disclose, copy or distribute this file or
+-00017  * any information contained herein except pursuant to this license grant from
+-00018  * Synopsys. If you do not agree with this notice, including the disclaimer
+-00019  * below, then you are not authorized to use the Software.
+-00020  *
+-00021  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
+-00022  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+-00023  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+-00024  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
+-00025  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+-00026  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+-00027  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+-00028  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+-00029  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+-00030  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+-00031  * DAMAGE.
+-00032  * ========================================================================== */
+-00033 
+-00042 #include "dwc_os.h"
+-00043 #include "dwc_otg_regs.h"
+-00044 #include "dwc_otg_cil.h"
+-00045 
+-00046 #ifdef DEBUG
+-00047 inline const char *op_state_str(dwc_otg_core_if_t * core_if)
+-00048 {
+-00049         return (core_if->op_state == A_HOST ? "a_host" :
+-00050                 (core_if->op_state == A_SUSPEND ? "a_suspend" :
+-00051                  (core_if->op_state == A_PERIPHERAL ? "a_peripheral" :
+-00052                   (core_if->op_state == B_PERIPHERAL ? "b_peripheral" :
+-00053                    (core_if->op_state == B_HOST ? "b_host" : "unknown")))));
+-00054 }
+-00055 #endif
+-00056 
+-00061 int32_t dwc_otg_handle_mode_mismatch_intr(dwc_otg_core_if_t * core_if)
+-00062 {
+-00063         gintsts_data_t gintsts;
+-00064         DWC_WARN("Mode Mismatch Interrupt: currently in %s mode\n",
+-00065                  dwc_otg_mode(core_if) ? "Host" : "Device");
+-00066 
+-00067         /* Clear interrupt */
+-00068         gintsts.d32 = 0;
+-00069         gintsts.b.modemismatch = 1;
+-00070         dwc_write_reg32(&core_if->core_global_regs->gintsts, gintsts.d32);
+-00071         return 1;
+-00072 }
+-00073 
+-00078 static inline void hcd_start(dwc_otg_core_if_t * core_if)
+-00079 {
+-00080         if (core_if->hcd_cb && core_if->hcd_cb->start) {
+-00081                 core_if->hcd_cb->start(core_if->hcd_cb->p);
+-00082         }
+-00083 }
+-00084 
+-00089 static inline void hcd_stop(dwc_otg_core_if_t * core_if)
+-00090 {
+-00091         if (core_if->hcd_cb && core_if->hcd_cb->stop) {
+-00092                 core_if->hcd_cb->stop(core_if->hcd_cb->p);
+-00093         }
+-00094 }
+-00095 
+-00100 static inline void hcd_disconnect(dwc_otg_core_if_t * core_if)
+-00101 {
+-00102         if (core_if->hcd_cb && core_if->hcd_cb->disconnect) {
+-00103                 core_if->hcd_cb->disconnect(core_if->hcd_cb->p);
+-00104         }
+-00105 }
+-00106 
+-00112 static inline void hcd_session_start(dwc_otg_core_if_t * core_if)
+-00113 {
+-00114         if (core_if->hcd_cb && core_if->hcd_cb->session_start) {
+-00115                 core_if->hcd_cb->session_start(core_if->hcd_cb->p);
+-00116         }
+-00117 }
+-00118 
+-00119 #ifdef CONFIG_USB_DWC_OTG_LPM
+-00120 
+-00126 static inline void hcd_sleep(dwc_otg_core_if_t * core_if)
+-00127 {
+-00128         if (core_if->hcd_cb && core_if->hcd_cb->sleep) {
+-00129                 core_if->hcd_cb->sleep(core_if->hcd_cb->p);
+-00130         }
+-00131 }
+-00132 #endif
+-00133 
+-00138 static inline void hcd_resume(dwc_otg_core_if_t * core_if)
+-00139 {
+-00140         if (core_if->hcd_cb && core_if->hcd_cb->resume_wakeup) {
+-00141                 core_if->hcd_cb->resume_wakeup(core_if->hcd_cb->p);
+-00142         }
+-00143 }
+-00144 
+-00149 static inline void pcd_start(dwc_otg_core_if_t * core_if)
+-00150 {
+-00151         if (core_if->pcd_cb && core_if->pcd_cb->start) {
+-00152                 core_if->pcd_cb->start(core_if->pcd_cb->p);
+-00153         }
+-00154 }
+-00155 
+-00160 static inline void pcd_stop(dwc_otg_core_if_t * core_if)
+-00161 {
+-00162         if (core_if->pcd_cb && core_if->pcd_cb->stop) {
+-00163                 core_if->pcd_cb->stop(core_if->pcd_cb->p);
+-00164         }
+-00165 }
+-00166 
+-00171 static inline void pcd_suspend(dwc_otg_core_if_t * core_if)
+-00172 {
+-00173         if (core_if->pcd_cb && core_if->pcd_cb->suspend) {
+-00174                 core_if->pcd_cb->suspend(core_if->pcd_cb->p);
+-00175         }
+-00176 }
+-00177 
+-00182 static inline void pcd_resume(dwc_otg_core_if_t * core_if)
+-00183 {
+-00184         if (core_if->pcd_cb && core_if->pcd_cb->resume_wakeup) {
+-00185                 core_if->pcd_cb->resume_wakeup(core_if->pcd_cb->p);
+-00186         }
+-00187 }
+-00188 
+-00196 int32_t dwc_otg_handle_otg_intr(dwc_otg_core_if_t * core_if)
+-00197 {
+-00198         dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
+-00199         gotgint_data_t gotgint;
+-00200         gotgctl_data_t gotgctl;
+-00201         gintmsk_data_t gintmsk;
+-00202 
+-00203         gotgint.d32 = dwc_read_reg32(&global_regs->gotgint);
+-00204         gotgctl.d32 = dwc_read_reg32(&global_regs->gotgctl);
+-00205         DWC_DEBUGPL(DBG_CIL, "++OTG Interrupt gotgint=%0x [%s]\n", gotgint.d32,
+-00206                     op_state_str(core_if));
+-00207 
+-00208         if (gotgint.b.sesenddet) {
+-00209                 DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: "
+-00210                             "Session End Detected++ (%s)\n",
+-00211                             op_state_str(core_if));
+-00212                 gotgctl.d32 = dwc_read_reg32(&global_regs->gotgctl);
+-00213 
+-00214                 if (core_if->op_state == B_HOST) {
+-00215                         pcd_start(core_if);
+-00216                         core_if->op_state = B_PERIPHERAL;
+-00217                 } else {
+-00218                         /* If not B_HOST and Device HNP still set. HNP
+-00219                          * Did not succeed!*/
+-00220                         if (gotgctl.b.devhnpen) {
+-00221                                 DWC_DEBUGPL(DBG_ANY, "Session End Detected\n");
+-00222                                 __DWC_ERROR("Device Not Connected/Responding!\n");
+-00223                         }
+-00224 
+-00225                         /* If Session End Detected the B-Cable has
+-00226                          * been disconnected. */
+-00227                         /* Reset PCD and Gadget driver to a
+-00228                          * clean state. */
+-00229                         core_if->lx_state = DWC_OTG_L0;
+-00230                         pcd_stop(core_if);
+-00231                 }
+-00232                 gotgctl.d32 = 0;
+-00233                 gotgctl.b.devhnpen = 1;
+-00234                 dwc_modify_reg32(&global_regs->gotgctl, gotgctl.d32, 0);
+-00235         }
+-00236         if (gotgint.b.sesreqsucstschng) {
+-00237                 DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: "
+-00238                             "Session Reqeust Success Status Change++\n");
+-00239                 gotgctl.d32 = dwc_read_reg32(&global_regs->gotgctl);
+-00240                 if (gotgctl.b.sesreqscs) {
+-00241                         if ((core_if->core_params->phy_type ==
+-00242                              DWC_PHY_TYPE_PARAM_FS) && (core_if->core_params->i2c_enable)) {
+-00243                                 core_if->srp_success = 1;
+-00244                         } else {
+-00245                                 pcd_resume(core_if);
+-00246                                 /* Clear Session Request */
+-00247                                 gotgctl.d32 = 0;
+-00248                                 gotgctl.b.sesreq = 1;
+-00249                                 dwc_modify_reg32(&global_regs->gotgctl,
+-00250                                                  gotgctl.d32, 0);
+-00251                         }
+-00252                 }
+-00253         }
+-00254         if (gotgint.b.hstnegsucstschng) {
+-00255                 /* Print statements during the HNP interrupt handling
+-00256                  * can cause it to fail.*/
+-00257                 gotgctl.d32 = dwc_read_reg32(&global_regs->gotgctl);
+-00258                 if (gotgctl.b.hstnegscs) {
+-00259                         if (dwc_otg_is_host_mode(core_if)) {
+-00260                                 core_if->op_state = B_HOST;
+-00261                                 /*
+-00262                                  * Need to disable SOF interrupt immediately.
+-00263                                  * When switching from device to host, the PCD
+-00264                                  * interrupt handler won't handle the
+-00265                                  * interrupt if host mode is already set. The
+-00266                                  * HCD interrupt handler won't get called if
+-00267                                  * the HCD state is HALT. This means that the
+-00268                                  * interrupt does not get handled and Linux
+-00269                                  * complains loudly.
+-00270                                  */
+-00271                                 gintmsk.d32 = 0;
+-00272                                 gintmsk.b.sofintr = 1;
+-00273                                 dwc_modify_reg32(&global_regs->gintmsk,
+-00274                                                  gintmsk.d32, 0);
+-00275                                 pcd_stop(core_if);
+-00276                                 /*
+-00277                                  * Initialize the Core for Host mode.
+-00278                                  */
+-00279                                 hcd_start(core_if);
+-00280                                 core_if->op_state = B_HOST;
+-00281                         }
+-00282                 } else {
+-00283                         gotgctl.d32 = 0;
+-00284                         gotgctl.b.hnpreq = 1;
+-00285                         gotgctl.b.devhnpen = 1;
+-00286                         dwc_modify_reg32(&global_regs->gotgctl, gotgctl.d32, 0);
+-00287                         DWC_DEBUGPL(DBG_ANY, "HNP Failed\n");
+-00288                         __DWC_ERROR("Device Not Connected/Responding\n");
+-00289                 }
+-00290         }
+-00291         if (gotgint.b.hstnegdet) {
+-00292                 /* The disconnect interrupt is set at the same time as
+-00293                  * Host Negotiation Detected.  During the mode
+-00294                  * switch all interrupts are cleared so the disconnect
+-00295                  * interrupt handler will not get executed.
+-00296                  */
+-00297                 DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: "
+-00298                             "Host Negotiation Detected++ (%s)\n",
+-00299                             (dwc_otg_is_host_mode(core_if) ? "Host" :
+-00300                              "Device"));
+-00301                 if (dwc_otg_is_device_mode(core_if)) {
+-00302                         DWC_DEBUGPL(DBG_ANY, "a_suspend->a_peripheral (%d)\n",
+-00303                                     core_if->op_state);
+-00304                         hcd_disconnect(core_if);
+-00305                         pcd_start(core_if);
+-00306                         core_if->op_state = A_PERIPHERAL;
+-00307                 } else {
+-00308                         /*
+-00309                          * Need to disable SOF interrupt immediately. When
+-00310                          * switching from device to host, the PCD interrupt
+-00311                          * handler won't handle the interrupt if host mode is
+-00312                          * already set. The HCD interrupt handler won't get
+-00313                          * called if the HCD state is HALT. This means that
+-00314                          * the interrupt does not get handled and Linux
+-00315                          * complains loudly.
+-00316                          */
+-00317                         gintmsk.d32 = 0;
+-00318                         gintmsk.b.sofintr = 1;
+-00319                         dwc_modify_reg32(&global_regs->gintmsk, gintmsk.d32, 0);
+-00320                         pcd_stop(core_if);
+-00321                         hcd_start(core_if);
+-00322                         core_if->op_state = A_HOST;
+-00323                 }
+-00324         }
+-00325         if (gotgint.b.adevtoutchng) {
+-00326                 DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: "
+-00327                             "A-Device Timeout Change++\n");
+-00328         }
+-00329         if (gotgint.b.debdone) {
+-00330                 DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: " "Debounce Done++\n");
+-00331         }
+-00332 
+-00333         /* Clear GOTGINT */
+-00334         dwc_write_reg32(&core_if->core_global_regs->gotgint, gotgint.d32);
+-00335 
+-00336         return 1;
+-00337 }
+-00338 
+-00339 void w_conn_id_status_change(void *p)
+-00340 {
+-00341         dwc_otg_core_if_t *core_if = p;
+-00342         uint32_t count = 0;
+-00343         gotgctl_data_t gotgctl = {.d32 = 0 };
+-00344 
+-00345         gotgctl.d32 = dwc_read_reg32(&core_if->core_global_regs->gotgctl);
+-00346         DWC_DEBUGPL(DBG_CIL, "gotgctl=%0x\n", gotgctl.d32);
+-00347         DWC_DEBUGPL(DBG_CIL, "gotgctl.b.conidsts=%d\n", gotgctl.b.conidsts);
+-00348 
+-00349         /* B-Device connector (Device Mode) */
+-00350         if (gotgctl.b.conidsts) {
+-00351                 /* Wait for switch to device mode. */
+-00352                 while (!dwc_otg_is_device_mode(core_if)) {
+-00353                         DWC_PRINTF("Waiting for Peripheral Mode, Mode=%s\n",
+-00354                                    (dwc_otg_is_host_mode(core_if) ? "Host" :
+-00355                                     "Peripheral"));
+-00356                         dwc_mdelay(100);
+-00357                         if (++count > 10000)
+-00358                                 break;
+-00359                 }
+-00360                 DWC_ASSERT(++count < 10000,
+-00361                            "Connection id status change timed out");
+-00362                 core_if->op_state = B_PERIPHERAL;
+-00363                 dwc_otg_core_init(core_if);
+-00364                 dwc_otg_enable_global_interrupts(core_if);
+-00365                 pcd_start(core_if);
+-00366         } else {
+-00367                 /* A-Device connector (Host Mode) */
+-00368                 while (!dwc_otg_is_host_mode(core_if)) {
+-00369                         DWC_PRINTF("Waiting for Host Mode, Mode=%s\n",
+-00370                                    (dwc_otg_is_host_mode(core_if) ? "Host" :
+-00371                                     "Peripheral"));
+-00372                         dwc_mdelay(100);
+-00373                         if (++count > 10000)
+-00374                                 break;
+-00375                 }
+-00376                 DWC_ASSERT(++count < 10000,
+-00377                            "Connection id status change timed out");
+-00378                 core_if->op_state = A_HOST;
+-00379                 /*
+-00380                  * Initialize the Core for Host mode.
+-00381                  */
+-00382                 dwc_otg_core_init(core_if);
+-00383                 dwc_otg_enable_global_interrupts(core_if);
+-00384                 hcd_start(core_if);
+-00385         }
+-00386 }
+-00387 
+-00399 int32_t dwc_otg_handle_conn_id_status_change_intr(dwc_otg_core_if_t * core_if)
+-00400 {
+-00401 
+-00402         /*
+-00403          * Need to disable SOF interrupt immediately. If switching from device
+-00404          * to host, the PCD interrupt handler won't handle the interrupt if
+-00405          * host mode is already set. The HCD interrupt handler won't get
+-00406          * called if the HCD state is HALT. This means that the interrupt does
+-00407          * not get handled and Linux complains loudly.
+-00408          */
+-00409         gintmsk_data_t gintmsk = {.d32 = 0 };
+-00410         gintsts_data_t gintsts = {.d32 = 0 };
+-00411 
+-00412         gintmsk.b.sofintr = 1;
+-00413         dwc_modify_reg32(&core_if->core_global_regs->gintmsk, gintmsk.d32, 0);
+-00414 
+-00415         DWC_DEBUGPL(DBG_CIL,
+-00416                     " ++Connector ID Status Change Interrupt++  (%s)\n",
+-00417                     (dwc_otg_is_host_mode(core_if) ? "Host" : "Device"));
+-00418 
+-00419         /*
+-00420          * Need to schedule a work, as there are possible DELAY function calls
+-00421          */
+-00422         DWC_WORKQ_SCHEDULE(core_if->wq_otg, w_conn_id_status_change,
+-00423                            core_if, "connection id status change");
+-00424 
+-00425         /* Set flag and clear interrupt */
+-00426         gintsts.b.conidstschng = 1;
+-00427         dwc_write_reg32(&core_if->core_global_regs->gintsts, gintsts.d32);
+-00428 
+-00429         return 1;
+-00430 }
+-00431 
+-00441 int32_t dwc_otg_handle_session_req_intr(dwc_otg_core_if_t * core_if)
+-00442 {
+-00443         hprt0_data_t hprt0;
+-00444         gintsts_data_t gintsts;
+-00445 
+-00446 #ifndef DWC_HOST_ONLY
+-00447         DWC_DEBUGPL(DBG_ANY, "++Session Request Interrupt++\n");
+-00448 
+-00449         if (dwc_otg_is_device_mode(core_if)) {
+-00450                 DWC_PRINTF("SRP: Device mode\n");
+-00451         } else {
+-00452                 DWC_PRINTF("SRP: Host mode\n");
+-00453 
+-00454                 /* Turn on the port power bit. */
+-00455                 hprt0.d32 = dwc_otg_read_hprt0(core_if);
+-00456                 hprt0.b.prtpwr = 1;
+-00457                 dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
+-00458 
+-00459                 /* Start the Connection timer. So a message can be displayed
+-00460                  * if connect does not occur within 10 seconds. */
+-00461                 hcd_session_start(core_if);
+-00462         }
+-00463 #endif
+-00464 
+-00465         /* Clear interrupt */
+-00466         gintsts.d32 = 0;
+-00467         gintsts.b.sessreqintr = 1;
+-00468         dwc_write_reg32(&core_if->core_global_regs->gintsts, gintsts.d32);
+-00469 
+-00470         return 1;
+-00471 }
+-00472 
+-00473 void w_wakeup_detected(void *p)
+-00474 {
+-00475         dwc_otg_core_if_t *core_if = (dwc_otg_core_if_t *) p;
+-00476         /*
+-00477          * Clear the Resume after 70ms. (Need 20 ms minimum. Use 70 ms
+-00478          * so that OPT tests pass with all PHYs).
+-00479          */
+-00480         hprt0_data_t hprt0 = {.d32 = 0 };
+-00481 #if 0
+-00482         pcgcctl_data_t pcgcctl = {.d32 = 0 };
+-00483         /* Restart the Phy Clock */
+-00484         pcgcctl.b.stoppclk = 1;
+-00485         dwc_modify_reg32(core_if->pcgcctl, pcgcctl.d32, 0);
+-00486         dwc_udelay(10);
+-00487 #endif                          //0
+-00488         hprt0.d32 = dwc_otg_read_hprt0(core_if);
+-00489         DWC_DEBUGPL(DBG_ANY, "Resume: HPRT0=%0x\n", hprt0.d32);
+-00490 //      dwc_mdelay(70);
+-00491         hprt0.b.prtres = 0;     /* Resume */
+-00492         dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
+-00493         DWC_DEBUGPL(DBG_ANY, "Clear Resume: HPRT0=%0x\n",
+-00494                     dwc_read_reg32(core_if->host_if->hprt0));
+-00495 
+-00496         hcd_resume(core_if);
+-00497 
+-00499         core_if->lx_state = DWC_OTG_L0;
+-00500 
+-00501 }
+-00502 
+-00510 int32_t dwc_otg_handle_wakeup_detected_intr(dwc_otg_core_if_t * core_if)
+-00511 {
+-00512         gintsts_data_t gintsts;
+-00513 
+-00514         DWC_DEBUGPL(DBG_ANY,
+-00515                     "++Resume and Remote Wakeup Detected Interrupt++\n");
+-00516 
+-00517         DWC_PRINTF("%s lxstate = %d\n", __func__, core_if->lx_state);
+-00518 
+-00519         if (dwc_otg_is_device_mode(core_if)) {
+-00520                 dctl_data_t dctl = {.d32 = 0 };
+-00521                 DWC_DEBUGPL(DBG_PCD, "DSTS=0x%0x\n",
+-00522                             dwc_read_reg32(&core_if->dev_if->dev_global_regs->
+-00523                                            dsts));
+-00524                 if (core_if->lx_state == DWC_OTG_L2) {
+-00525 #ifdef PARTIAL_POWER_DOWN
+-00526                         if (core_if->hwcfg4.b.power_optimiz) {
+-00527                                 pcgcctl_data_t power = {.d32 = 0 };
+-00528 
+-00529                                 power.d32 = dwc_read_reg32(core_if->pcgcctl);
+-00530                                 DWC_DEBUGPL(DBG_CIL, "PCGCCTL=%0x\n",
+-00531                                             power.d32);
+-00532 
+-00533                                 power.b.stoppclk = 0;
+-00534                                 dwc_write_reg32(core_if->pcgcctl, power.d32);
+-00535 
+-00536                                 power.b.pwrclmp = 0;
+-00537                                 dwc_write_reg32(core_if->pcgcctl, power.d32);
+-00538 
+-00539                                 power.b.rstpdwnmodule = 0;
+-00540                                 dwc_write_reg32(core_if->pcgcctl, power.d32);
+-00541                         }
+-00542 #endif
+-00543                         /* Clear the Remote Wakeup Signalling */
+-00544                         dctl.b.rmtwkupsig = 1;
+-00545                         dwc_modify_reg32(&core_if->dev_if->dev_global_regs->
+-00546                                          dctl, dctl.d32, 0);
+-00547 
+-00548                         if (core_if->pcd_cb && core_if->pcd_cb->resume_wakeup) {
+-00549                                 core_if->pcd_cb->resume_wakeup(core_if->pcd_cb->
+-00550                                                                p);
+-00551                         }
+-00552                 } else {
+-00553                         glpmcfg_data_t lpmcfg;
+-00554                         lpmcfg.d32 =
+-00555                             dwc_read_reg32(&core_if->core_global_regs->glpmcfg);
+-00556                         lpmcfg.b.hird_thres &= (~(1 << 4));
+-00557                         dwc_write_reg32(&core_if->core_global_regs->glpmcfg,
+-00558                                         lpmcfg.d32);
+-00559                 }
+-00561                 core_if->lx_state = DWC_OTG_L0;
+-00562         } else {
+-00563                 if (core_if->lx_state != DWC_OTG_L1) {
+-00564                         pcgcctl_data_t pcgcctl = {.d32 = 0 };
+-00565 
+-00566                         /* Restart the Phy Clock */
+-00567                         pcgcctl.b.stoppclk = 1;
+-00568                         dwc_modify_reg32(core_if->pcgcctl, pcgcctl.d32, 0);
+-00569 
+-00570                         DWC_TIMER_SCHEDULE(core_if->wkp_timer, 71);
+-00571                 } else {
+-00573                         core_if->lx_state = DWC_OTG_L0;
+-00574                 }
+-00575         }
+-00576 
+-00577         /* Clear interrupt */
+-00578         gintsts.d32 = 0;
+-00579         gintsts.b.wkupintr = 1;
+-00580         dwc_write_reg32(&core_if->core_global_regs->gintsts, gintsts.d32);
+-00581 
+-00582         return 1;
+-00583 }
+-00584 
+-00589 int32_t dwc_otg_handle_disconnect_intr(dwc_otg_core_if_t * core_if)
+-00590 {
+-00591         gintsts_data_t gintsts;
+-00592 
+-00593         DWC_DEBUGPL(DBG_ANY, "++Disconnect Detected Interrupt++ (%s) %s\n",
+-00594                     (dwc_otg_is_host_mode(core_if) ? "Host" : "Device"),
+-00595                     op_state_str(core_if));
+-00596 
+-00598 #ifndef DWC_HOST_ONLY
+-00599         if (core_if->op_state == B_HOST) {
+-00600                 /* If in device mode Disconnect and stop the HCD, then
+-00601                  * start the PCD. */
+-00602                 hcd_disconnect(core_if);
+-00603                 pcd_start(core_if);
+-00604                 core_if->op_state = B_PERIPHERAL;
+-00605         } else if (dwc_otg_is_device_mode(core_if)) {
+-00606                 gotgctl_data_t gotgctl = {.d32 = 0 };
+-00607                 gotgctl.d32 =
+-00608                     dwc_read_reg32(&core_if->core_global_regs->gotgctl);
+-00609                 if (gotgctl.b.hstsethnpen == 1) {
+-00610                         /* Do nothing, if HNP in process the OTG
+-00611                          * interrupt "Host Negotiation Detected"
+-00612                          * interrupt will do the mode switch.
+-00613                          */
+-00614                 } else if (gotgctl.b.devhnpen == 0) {
+-00615                         /* If in device mode Disconnect and stop the HCD, then
+-00616                          * start the PCD. */
+-00617                         hcd_disconnect(core_if);
+-00618                         pcd_start(core_if);
+-00619                         core_if->op_state = B_PERIPHERAL;
+-00620                 } else {
+-00621                         DWC_DEBUGPL(DBG_ANY, "!a_peripheral && !devhnpen\n");
+-00622                 }
+-00623         } else {
+-00624                 if (core_if->op_state == A_HOST) {
+-00625                         /* A-Cable still connected but device disconnected. */
+-00626                         hcd_disconnect(core_if);
+-00627                 }
+-00628         }
+-00629 #endif
+-00630         /* Change to L3(OFF) state */
+-00631         core_if->lx_state = DWC_OTG_L3;
+-00632 
+-00633         gintsts.d32 = 0;
+-00634         gintsts.b.disconnect = 1;
+-00635         dwc_write_reg32(&core_if->core_global_regs->gintsts, gintsts.d32);
+-00636         return 1;
+-00637 }
+-00638 
+-00649 int32_t dwc_otg_handle_usb_suspend_intr(dwc_otg_core_if_t * core_if)
+-00650 {
+-00651         dsts_data_t dsts;
+-00652         gintsts_data_t gintsts;
+-00653 
+-00654         DWC_DEBUGPL(DBG_ANY, "USB SUSPEND\n");
+-00655 
+-00656         if (dwc_otg_is_device_mode(core_if)) {
+-00657                 /* Check the Device status register to determine if the Suspend
+-00658                  * state is active. */
+-00659                 dsts.d32 =
+-00660                     dwc_read_reg32(&core_if->dev_if->dev_global_regs->dsts);
+-00661                 DWC_DEBUGPL(DBG_PCD, "DSTS=0x%0x\n", dsts.d32);
+-00662                 DWC_DEBUGPL(DBG_PCD, "DSTS.Suspend Status=%d "
+-00663                             "HWCFG4.power Optimize=%d\n",
+-00664                             dsts.b.suspsts, core_if->hwcfg4.b.power_optimiz);
+-00665 
+-00666 #ifdef PARTIAL_POWER_DOWN
+-00667 
+-00669                 if (dsts.b.suspsts && core_if->hwcfg4.b.power_optimiz) {
+-00670                         pcgcctl_data_t power = {.d32 = 0 };
+-00671                         DWC_DEBUGPL(DBG_CIL, "suspend\n");
+-00672 
+-00673                         power.b.pwrclmp = 1;
+-00674                         dwc_write_reg32(core_if->pcgcctl, power.d32);
+-00675 
+-00676                         power.b.rstpdwnmodule = 1;
+-00677                         dwc_modify_reg32(core_if->pcgcctl, 0, power.d32);
+-00678 
+-00679                         power.b.stoppclk = 1;
+-00680                         dwc_modify_reg32(core_if->pcgcctl, 0, power.d32);
+-00681 
+-00682                 } else {
+-00683                         DWC_DEBUGPL(DBG_ANY, "disconnect?\n");
+-00684                 }
+-00685 #endif
+-00686                 /* PCD callback for suspend. */
+-00687                 pcd_suspend(core_if);
+-00688         } else {
+-00689                 if (core_if->op_state == A_PERIPHERAL) {
+-00690                         DWC_DEBUGPL(DBG_ANY, "a_peripheral->a_host\n");
+-00691                         /* Clear the a_peripheral flag, back to a_host. */
+-00692                         pcd_stop(core_if);
+-00693                         hcd_start(core_if);
+-00694                         core_if->op_state = A_HOST;
+-00695                 }
+-00696         }
+-00697 
+-00698         /* Change to L2(suspend) state */
+-00699         core_if->lx_state = DWC_OTG_L2;
+-00700 
+-00701         /* Clear interrupt */
+-00702         gintsts.d32 = 0;
+-00703         gintsts.b.usbsuspend = 1;
+-00704         dwc_write_reg32(&core_if->core_global_regs->gintsts, gintsts.d32);
+-00705 
+-00706         return 1;
+-00707 }
+-00708 
+-00709 #ifdef CONFIG_USB_DWC_OTG_LPM
+-00710 
+-00713 static int32_t dwc_otg_handle_lpm_intr(dwc_otg_core_if_t * core_if)
+-00714 {
+-00715         glpmcfg_data_t lpmcfg;
+-00716         gintsts_data_t gintsts;
+-00717 
+-00718         if (!core_if->core_params->lpm_enable) {
+-00719                 DWC_PRINTF("Unexpected LPM interrupt\n");
+-00720         }
+-00721 
+-00722         lpmcfg.d32 = dwc_read_reg32(&core_if->core_global_regs->glpmcfg);
+-00723         DWC_PRINTF("LPM config register = 0x%08x\n", lpmcfg.d32);
+-00724 
+-00725         if (dwc_otg_is_host_mode(core_if)) {
+-00726                 hcd_sleep(core_if);
+-00727         } else {
+-00728                 lpmcfg.b.hird_thres |= (1 << 4);
+-00729                 dwc_write_reg32(&core_if->core_global_regs->glpmcfg,
+-00730                                 lpmcfg.d32);
+-00731         }
+-00732 
+-00733         /* Examine prt_sleep_sts after TL1TokenTetry period max (10 us) */      
+-00734         dwc_udelay(10);
+-00735         lpmcfg.d32 = dwc_read_reg32(&core_if->core_global_regs->glpmcfg);
+-00736         if (lpmcfg.b.prt_sleep_sts) {
+-00737                 /* Save the current state */
+-00738                 core_if->lx_state = DWC_OTG_L1;
+-00739         }
+-00740 
+-00741         /* Clear interrupt  */
+-00742         gintsts.d32 = 0;
+-00743         gintsts.b.lpmtranrcvd = 1;
+-00744         dwc_write_reg32(&core_if->core_global_regs->gintsts, gintsts.d32);
+-00745         return 1;
+-00746 }
+-00747 #endif                          /* CONFIG_USB_DWC_OTG_LPM */
+-00748 
+-00752 static inline uint32_t dwc_otg_read_common_intr(dwc_otg_core_if_t * core_if)
+-00753 {
+-00754         gintsts_data_t gintsts;
+-00755         gintmsk_data_t gintmsk;
+-00756         gintmsk_data_t gintmsk_common = {.d32 = 0 };
+-00757         gintmsk_common.b.wkupintr = 1;
+-00758         gintmsk_common.b.sessreqintr = 1;
+-00759         gintmsk_common.b.conidstschng = 1;
+-00760         gintmsk_common.b.otgintr = 1;
+-00761         gintmsk_common.b.modemismatch = 1;
+-00762         gintmsk_common.b.disconnect = 1;
+-00763         gintmsk_common.b.usbsuspend = 1;
+-00764 #ifdef CONFIG_USB_DWC_OTG_LPM
+-00765         gintmsk_common.b.lpmtranrcvd = 1;
+-00766 #endif
+-00767 
+-00770         gintmsk_common.b.portintr = 1;
+-00771 
+-00772         gintsts.d32 = dwc_read_reg32(&core_if->core_global_regs->gintsts);
+-00773         gintmsk.d32 = dwc_read_reg32(&core_if->core_global_regs->gintmsk);
+-00774 #ifdef DEBUG
+-00775         /* if any common interrupts set */
+-00776         if (gintsts.d32 & gintmsk_common.d32) {
+-00777                 DWC_DEBUGPL(DBG_ANY, "gintsts=%08x  gintmsk=%08x\n",
+-00778                             gintsts.d32, gintmsk.d32);
+-00779         }
+-00780 #endif
+-00781 
+-00782         return ((gintsts.d32 & gintmsk.d32) & gintmsk_common.d32);
+-00783 
+-00784 }
+-00785 
+-00800 int32_t dwc_otg_handle_common_intr(dwc_otg_core_if_t * core_if)
+-00801 {
+-00802         int retval = 0;
+-00803         gintsts_data_t gintsts;
+-00804 
+-00805         gintsts.d32 = dwc_otg_read_common_intr(core_if);
+-00806 
+-00807         if (gintsts.b.modemismatch) {
+-00808                 retval |= dwc_otg_handle_mode_mismatch_intr(core_if);
+-00809         }
+-00810         if (gintsts.b.otgintr) {
+-00811                 retval |= dwc_otg_handle_otg_intr(core_if);
+-00812         }
+-00813         if (gintsts.b.conidstschng) {
+-00814                 retval |= dwc_otg_handle_conn_id_status_change_intr(core_if);
+-00815         }
+-00816         if (gintsts.b.disconnect) {
+-00817                 retval |= dwc_otg_handle_disconnect_intr(core_if);
+-00818         }
+-00819         if (gintsts.b.sessreqintr) {
+-00820                 retval |= dwc_otg_handle_session_req_intr(core_if);
+-00821         }
+-00822         if (gintsts.b.wkupintr) {
+-00823                 retval |= dwc_otg_handle_wakeup_detected_intr(core_if);
+-00824         }
+-00825         if (gintsts.b.usbsuspend) {
+-00826                 retval |= dwc_otg_handle_usb_suspend_intr(core_if);
+-00827         }
+-00828 #ifdef CONFIG_USB_DWC_OTG_LPM
+-00829         if (gintsts.b.lpmtranrcvd) {
+-00830                 retval |= dwc_otg_handle_lpm_intr(core_if);
+-00831         }
+-00832 #endif
+-00833 
+-00834         if (gintsts.b.portintr && dwc_otg_is_device_mode(core_if)) {
+-00835                 /* The port interrupt occurs while in device mode with HPRT0
+-00836                  * Port Enable/Disable.
+-00837                  */
+-00838                 gintsts.d32 = 0;
+-00839                 gintsts.b.portintr = 1;
+-00840                 dwc_write_reg32(&core_if->core_global_regs->gintsts,
+-00841                                 gintsts.d32);
+-00842                 retval |= 1;
+-00843 
+-00844         }
+-00845         return retval;
+-00846 }
+-
    Generated on Tue May 5 02:22:48 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++
    Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
    ++

    dwc_otg_cil_intr.c

    Go to the documentation of this file.
    00001 /* ==========================================================================
++00002  * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_cil_intr.c $
++00003  * $Revision: #31 $
++00004  * $Date: 2011/10/24 $
++00005  * $Change: 1871286 $
++00006  *
++00007  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
++00008  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
++00009  * otherwise expressly agreed to in writing between Synopsys and you.
++00010  *
++00011  * The Software IS NOT an item of Licensed Software or Licensed Product under
++00012  * any End User Software License Agreement or Agreement for Licensed Product
++00013  * with Synopsys or any supplement thereto. You are permitted to use and
++00014  * redistribute this Software in source and binary forms, with or without
++00015  * modification, provided that redistributions of source code must retain this
++00016  * notice. You may not view, use, disclose, copy or distribute this file or
++00017  * any information contained herein except pursuant to this license grant from
++00018  * Synopsys. If you do not agree with this notice, including the disclaimer
++00019  * below, then you are not authorized to use the Software.
++00020  *
++00021  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
++00022  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++00023  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++00024  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
++00025  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++00026  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
++00027  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
++00028  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
++00029  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
++00030  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
++00031  * DAMAGE.
++00032  * ========================================================================== */
++00033 
++00042 #include "dwc_os.h"
++00043 #include "dwc_otg_regs.h"
++00044 #include "dwc_otg_cil.h"
++00045 #include "dwc_otg_driver.h"
++00046 #include "dwc_otg_pcd.h"
++00047 #include "dwc_otg_hcd.h"
++00048 
++00049 #ifdef DEBUG
++00050 inline const char *op_state_str(dwc_otg_core_if_t * core_if)
++00051 {
++00052         return (core_if->op_state == A_HOST ? "a_host" :
++00053                 (core_if->op_state == A_SUSPEND ? "a_suspend" :
++00054                  (core_if->op_state == A_PERIPHERAL ? "a_peripheral" :
++00055                   (core_if->op_state == B_PERIPHERAL ? "b_peripheral" :
++00056                    (core_if->op_state == B_HOST ? "b_host" : "unknown")))));
++00057 }
++00058 #endif
++00059 
++00064 int32_t dwc_otg_handle_mode_mismatch_intr(dwc_otg_core_if_t * core_if)
++00065 {
++00066         gintsts_data_t gintsts;
++00067         DWC_WARN("Mode Mismatch Interrupt: currently in %s mode\n",
++00068                  dwc_otg_mode(core_if) ? "Host" : "Device");
++00069 
++00070         /* Clear interrupt */
++00071         gintsts.d32 = 0;
++00072         gintsts.b.modemismatch = 1;
++00073         DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
++00074         return 1;
++00075 }
++00076 
++00084 int32_t dwc_otg_handle_otg_intr(dwc_otg_core_if_t * core_if)
++00085 {
++00086         dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
++00087         gotgint_data_t gotgint;
++00088         gotgctl_data_t gotgctl;
++00089         gintmsk_data_t gintmsk;
++00090         gpwrdn_data_t gpwrdn;
++00091 
++00092         gotgint.d32 = DWC_READ_REG32(&global_regs->gotgint);
++00093         gotgctl.d32 = DWC_READ_REG32(&global_regs->gotgctl);
++00094         DWC_DEBUGPL(DBG_CIL, "++OTG Interrupt gotgint=%0x [%s]\n", gotgint.d32,
++00095                     op_state_str(core_if));
++00096 
++00097         if (gotgint.b.sesenddet) {
++00098                 DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: "
++00099                             "Session End Detected++ (%s)\n",
++00100                             op_state_str(core_if));
++00101                 gotgctl.d32 = DWC_READ_REG32(&global_regs->gotgctl);
++00102 
++00103                 if (core_if->op_state == B_HOST) {
++00104                         cil_pcd_start(core_if);
++00105                         core_if->op_state = B_PERIPHERAL;
++00106                 } else {
++00107                         /* If not B_HOST and Device HNP still set. HNP
++00108                          * Did not succeed!*/
++00109                         if (gotgctl.b.devhnpen) {
++00110                                 DWC_DEBUGPL(DBG_ANY, "Session End Detected\n");
++00111                                 __DWC_ERROR("Device Not Connected/Responding!\n");
++00112                         }
++00113 
++00114                         /* If Session End Detected the B-Cable has
++00115                          * been disconnected. */
++00116                         /* Reset PCD and Gadget driver to a
++00117                          * clean state. */
++00118                         core_if->lx_state = DWC_OTG_L0;
++00119                         DWC_SPINUNLOCK(core_if->lock);
++00120                         cil_pcd_stop(core_if);
++00121                         DWC_SPINLOCK(core_if->lock);
++00122 
++00123                         if (core_if->adp_enable) {
++00124                                 if (core_if->power_down == 2) {
++00125                                         gpwrdn.d32 = 0;
++00126                                         gpwrdn.b.pwrdnswtch = 1;
++00127                                         DWC_MODIFY_REG32(&core_if->
++00128                                                          core_global_regs->
++00129                                                          gpwrdn, gpwrdn.d32, 0);
++00130                                 }
++00131 
++00132                                 gpwrdn.d32 = 0;
++00133                                 gpwrdn.b.pmuintsel = 1;
++00134                                 gpwrdn.b.pmuactv = 1;
++00135                                 DWC_MODIFY_REG32(&core_if->core_global_regs->
++00136                                                  gpwrdn, 0, gpwrdn.d32);
++00137 
++00138                                 dwc_otg_adp_sense_start(core_if);
++00139                         }
++00140                 }
++00141 
++00142                 gotgctl.d32 = 0;
++00143                 gotgctl.b.devhnpen = 1;
++00144                 DWC_MODIFY_REG32(&global_regs->gotgctl, gotgctl.d32, 0);
++00145         }
++00146         if (gotgint.b.sesreqsucstschng) {
++00147                 DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: "
++00148                             "Session Reqeust Success Status Change++\n");
++00149                 gotgctl.d32 = DWC_READ_REG32(&global_regs->gotgctl);
++00150                 if (gotgctl.b.sesreqscs) {
++00151 
++00152                         if ((core_if->core_params->phy_type ==
++00153                              DWC_PHY_TYPE_PARAM_FS) && (core_if->core_params->i2c_enable)) {
++00154                                 core_if->srp_success = 1;
++00155                         } else {
++00156                                 DWC_SPINUNLOCK(core_if->lock);
++00157                                 cil_pcd_resume(core_if);
++00158                                 DWC_SPINLOCK(core_if->lock);
++00159                                 /* Clear Session Request */
++00160                                 gotgctl.d32 = 0;
++00161                                 gotgctl.b.sesreq = 1;
++00162                                 DWC_MODIFY_REG32(&global_regs->gotgctl,
++00163                                                  gotgctl.d32, 0);
++00164                         }
++00165                 }
++00166         }
++00167         if (gotgint.b.hstnegsucstschng) {
++00168                 /* Print statements during the HNP interrupt handling
++00169                  * can cause it to fail.*/
++00170                 gotgctl.d32 = DWC_READ_REG32(&global_regs->gotgctl);
++00171                 if (gotgctl.b.hstnegscs) {
++00172                         if (dwc_otg_is_host_mode(core_if)) {
++00173                                 core_if->op_state = B_HOST;
++00174                                 /*
++00175                                  * Need to disable SOF interrupt immediately.
++00176                                  * When switching from device to host, the PCD
++00177                                  * interrupt handler won't handle the
++00178                                  * interrupt if host mode is already set. The
++00179                                  * HCD interrupt handler won't get called if
++00180                                  * the HCD state is HALT. This means that the
++00181                                  * interrupt does not get handled and Linux
++00182                                  * complains loudly.
++00183                                  */
++00184                                 gintmsk.d32 = 0;
++00185                                 gintmsk.b.sofintr = 1;
++00186                                 DWC_MODIFY_REG32(&global_regs->gintmsk,
++00187                                                  gintmsk.d32, 0);
++00188                                 /* Call callback function with spin lock released */
++00189                                 DWC_SPINUNLOCK(core_if->lock);
++00190                                 cil_pcd_stop(core_if);
++00191                                 /*
++00192                                  * Initialize the Core for Host mode.
++00193                                  */
++00194                                 cil_hcd_start(core_if);
++00195                                 DWC_SPINLOCK(core_if->lock);
++00196                                 core_if->op_state = B_HOST;
++00197                         }
++00198                 } else {
++00199                         gotgctl.d32 = 0;
++00200                         gotgctl.b.hnpreq = 1;
++00201                         gotgctl.b.devhnpen = 1;
++00202                         DWC_MODIFY_REG32(&global_regs->gotgctl, gotgctl.d32, 0);
++00203                         DWC_DEBUGPL(DBG_ANY, "HNP Failed\n");
++00204                         __DWC_ERROR("Device Not Connected/Responding\n");
++00205                 }
++00206         }
++00207         if (gotgint.b.hstnegdet) {
++00208                 /* The disconnect interrupt is set at the same time as
++00209                  * Host Negotiation Detected.  During the mode
++00210                  * switch all interrupts are cleared so the disconnect
++00211                  * interrupt handler will not get executed.
++00212                  */
++00213                 DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: "
++00214                             "Host Negotiation Detected++ (%s)\n",
++00215                             (dwc_otg_is_host_mode(core_if) ? "Host" :
++00216                              "Device"));
++00217                 if (dwc_otg_is_device_mode(core_if)) {
++00218                         DWC_DEBUGPL(DBG_ANY, "a_suspend->a_peripheral (%d)\n",
++00219                                     core_if->op_state);
++00220                         DWC_SPINUNLOCK(core_if->lock);
++00221                         cil_hcd_disconnect(core_if);
++00222                         cil_pcd_start(core_if);
++00223                         DWC_SPINLOCK(core_if->lock);
++00224                         core_if->op_state = A_PERIPHERAL;
++00225                 } else {
++00226                         /*
++00227                          * Need to disable SOF interrupt immediately. When
++00228                          * switching from device to host, the PCD interrupt
++00229                          * handler won't handle the interrupt if host mode is
++00230                          * already set. The HCD interrupt handler won't get
++00231                          * called if the HCD state is HALT. This means that
++00232                          * the interrupt does not get handled and Linux
++00233                          * complains loudly.
++00234                          */
++00235                         gintmsk.d32 = 0;
++00236                         gintmsk.b.sofintr = 1;
++00237                         DWC_MODIFY_REG32(&global_regs->gintmsk, gintmsk.d32, 0);
++00238                         DWC_SPINUNLOCK(core_if->lock);
++00239                         cil_pcd_stop(core_if);
++00240                         cil_hcd_start(core_if);
++00241                         DWC_SPINLOCK(core_if->lock);
++00242                         core_if->op_state = A_HOST;
++00243                 }
++00244         }
++00245         if (gotgint.b.adevtoutchng) {
++00246                 DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: "
++00247                             "A-Device Timeout Change++\n");
++00248         }
++00249         if (gotgint.b.debdone) {
++00250                 DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: " "Debounce Done++\n");
++00251         }
++00252 
++00253         /* Clear GOTGINT */
++00254         DWC_WRITE_REG32(&core_if->core_global_regs->gotgint, gotgint.d32);
++00255 
++00256         return 1;
++00257 }
++00258 
++00259 void w_conn_id_status_change(void *p)
++00260 {
++00261         dwc_otg_core_if_t *core_if = p;
++00262         uint32_t count = 0;
++00263         gotgctl_data_t gotgctl = {.d32 = 0 };
++00264 
++00265         gotgctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->gotgctl);
++00266         DWC_DEBUGPL(DBG_CIL, "gotgctl=%0x\n", gotgctl.d32);
++00267         DWC_DEBUGPL(DBG_CIL, "gotgctl.b.conidsts=%d\n", gotgctl.b.conidsts);
++00268 
++00269         /* B-Device connector (Device Mode) */
++00270         if (gotgctl.b.conidsts) {
++00271                 /* Wait for switch to device mode. */
++00272                 while (!dwc_otg_is_device_mode(core_if)) {
++00273                         DWC_PRINTF("Waiting for Peripheral Mode, Mode=%s\n",
++00274                                    (dwc_otg_is_host_mode(core_if) ? "Host" :
++00275                                     "Peripheral"));
++00276                         dwc_mdelay(100);
++00277                         if (++count > 10000)
++00278                                 break;
++00279                 }
++00280                 DWC_ASSERT(++count < 10000,
++00281                            "Connection id status change timed out");
++00282                 core_if->op_state = B_PERIPHERAL;
++00283                 dwc_otg_core_init(core_if);
++00284                 dwc_otg_enable_global_interrupts(core_if);
++00285                 cil_pcd_start(core_if);
++00286         } else {
++00287                 /* A-Device connector (Host Mode) */
++00288                 while (!dwc_otg_is_host_mode(core_if)) {
++00289                         DWC_PRINTF("Waiting for Host Mode, Mode=%s\n",
++00290                                    (dwc_otg_is_host_mode(core_if) ? "Host" :
++00291                                     "Peripheral"));
++00292                         dwc_mdelay(100);
++00293                         if (++count > 10000)
++00294                                 break;
++00295                 }
++00296                 DWC_ASSERT(++count < 10000,
++00297                            "Connection id status change timed out");
++00298                 core_if->op_state = A_HOST;
++00299                 /*
++00300                  * Initialize the Core for Host mode.
++00301                  */
++00302                 dwc_otg_core_init(core_if);
++00303                 dwc_otg_enable_global_interrupts(core_if);
++00304                 cil_hcd_start(core_if);
++00305         }
++00306 }
++00307 
++00319 int32_t dwc_otg_handle_conn_id_status_change_intr(dwc_otg_core_if_t * core_if)
++00320 {
++00321 
++00322         /*
++00323          * Need to disable SOF interrupt immediately. If switching from device
++00324          * to host, the PCD interrupt handler won't handle the interrupt if
++00325          * host mode is already set. The HCD interrupt handler won't get
++00326          * called if the HCD state is HALT. This means that the interrupt does
++00327          * not get handled and Linux complains loudly.
++00328          */
++00329         gintmsk_data_t gintmsk = {.d32 = 0 };
++00330         gintsts_data_t gintsts = {.d32 = 0 };
++00331 
++00332         gintmsk.b.sofintr = 1;
++00333         DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, gintmsk.d32, 0);
++00334 
++00335         DWC_DEBUGPL(DBG_CIL,
++00336                     " ++Connector ID Status Change Interrupt++  (%s)\n",
++00337                     (dwc_otg_is_host_mode(core_if) ? "Host" : "Device"));
++00338         
++00339         DWC_SPINUNLOCK(core_if->lock);
++00340 
++00341         /*
++00342          * Need to schedule a work, as there are possible DELAY function calls
++00343          * Release lock before scheduling workq as it holds spinlock during scheduling
++00344          */
++00345 
++00346         DWC_WORKQ_SCHEDULE(core_if->wq_otg, w_conn_id_status_change,
++00347                            core_if, "connection id status change");
++00348         DWC_SPINLOCK(core_if->lock);
++00349 
++00350         /* Set flag and clear interrupt */
++00351         gintsts.b.conidstschng = 1;
++00352         DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
++00353 
++00354         return 1;
++00355 }
++00356 
++00366 int32_t dwc_otg_handle_session_req_intr(dwc_otg_core_if_t * core_if)
++00367 {
++00368         gintsts_data_t gintsts;
++00369 
++00370 #ifndef DWC_HOST_ONLY
++00371         DWC_DEBUGPL(DBG_ANY, "++Session Request Interrupt++\n");
++00372 
++00373         if (dwc_otg_is_device_mode(core_if)) {
++00374                 DWC_PRINTF("SRP: Device mode\n");
++00375         } else {
++00376                 hprt0_data_t hprt0;
++00377                 DWC_PRINTF("SRP: Host mode\n");
++00378 
++00379                 /* Turn on the port power bit. */
++00380                 hprt0.d32 = dwc_otg_read_hprt0(core_if);
++00381                 hprt0.b.prtpwr = 1;
++00382                 DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
++00383 
++00384                 /* Start the Connection timer. So a message can be displayed
++00385                  * if connect does not occur within 10 seconds. */
++00386                 cil_hcd_session_start(core_if);
++00387         }
++00388 #endif
++00389 
++00390         /* Clear interrupt */
++00391         gintsts.d32 = 0;
++00392         gintsts.b.sessreqintr = 1;
++00393         DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
++00394 
++00395         return 1;
++00396 }
++00397 
++00398 void w_wakeup_detected(void *p)
++00399 {
++00400         dwc_otg_core_if_t *core_if = (dwc_otg_core_if_t *) p;
++00401         /*
++00402          * Clear the Resume after 70ms. (Need 20 ms minimum. Use 70 ms
++00403          * so that OPT tests pass with all PHYs).
++00404          */
++00405         hprt0_data_t hprt0 = {.d32 = 0 };
++00406 #if 0
++00407         pcgcctl_data_t pcgcctl = {.d32 = 0 };
++00408         /* Restart the Phy Clock */
++00409         pcgcctl.b.stoppclk = 1;
++00410         DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32, 0);
++00411         dwc_udelay(10);
++00412 #endif //0
++00413         hprt0.d32 = dwc_otg_read_hprt0(core_if);
++00414         DWC_DEBUGPL(DBG_ANY, "Resume: HPRT0=%0x\n", hprt0.d32);
++00415 //      dwc_mdelay(70);
++00416         hprt0.b.prtres = 0;     /* Resume */
++00417         DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
++00418         DWC_DEBUGPL(DBG_ANY, "Clear Resume: HPRT0=%0x\n",
++00419                     DWC_READ_REG32(core_if->host_if->hprt0));
++00420 
++00421         cil_hcd_resume(core_if);
++00422 
++00424         core_if->lx_state = DWC_OTG_L0;
++00425 }
++00426 
++00434 int32_t dwc_otg_handle_wakeup_detected_intr(dwc_otg_core_if_t * core_if)
++00435 {
++00436         gintsts_data_t gintsts;
++00437 
++00438         DWC_DEBUGPL(DBG_ANY,
++00439                     "++Resume and Remote Wakeup Detected Interrupt++\n");
++00440 
++00441         DWC_PRINTF("%s lxstate = %d\n", __func__, core_if->lx_state);
++00442 
++00443         if (dwc_otg_is_device_mode(core_if)) {
++00444                 dctl_data_t dctl = {.d32 = 0 };
++00445                 DWC_DEBUGPL(DBG_PCD, "DSTS=0x%0x\n",
++00446                             DWC_READ_REG32(&core_if->dev_if->
++00447                                            dev_global_regs->dsts));
++00448                 if (core_if->lx_state == DWC_OTG_L2) {
++00449 #ifdef PARTIAL_POWER_DOWN
++00450                         if (core_if->hwcfg4.b.power_optimiz) {
++00451                                 pcgcctl_data_t power = {.d32 = 0 };
++00452 
++00453                                 power.d32 = DWC_READ_REG32(core_if->pcgcctl);
++00454                                 DWC_DEBUGPL(DBG_CIL, "PCGCCTL=%0x\n",
++00455                                             power.d32);
++00456 
++00457                                 power.b.stoppclk = 0;
++00458                                 DWC_WRITE_REG32(core_if->pcgcctl, power.d32);
++00459 
++00460                                 power.b.pwrclmp = 0;
++00461                                 DWC_WRITE_REG32(core_if->pcgcctl, power.d32);
++00462 
++00463                                 power.b.rstpdwnmodule = 0;
++00464                                 DWC_WRITE_REG32(core_if->pcgcctl, power.d32);
++00465                         }
++00466 #endif
++00467                         /* Clear the Remote Wakeup Signaling */
++00468                         dctl.b.rmtwkupsig = 1;
++00469                         DWC_MODIFY_REG32(&core_if->dev_if->
++00470                                          dev_global_regs->dctl, dctl.d32, 0);
++00471 
++00472                         DWC_SPINUNLOCK(core_if->lock);
++00473                         if (core_if->pcd_cb && core_if->pcd_cb->resume_wakeup) {
++00474                                 core_if->pcd_cb->resume_wakeup(core_if->pcd_cb->p);
++00475                         }
++00476                         DWC_SPINLOCK(core_if->lock);
++00477                 } else {
++00478                         glpmcfg_data_t lpmcfg;
++00479                         lpmcfg.d32 =
++00480                             DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
++00481                         lpmcfg.b.hird_thres &= (~(1 << 4));
++00482                         DWC_WRITE_REG32(&core_if->core_global_regs->glpmcfg,
++00483                                         lpmcfg.d32);
++00484                 }
++00486                 core_if->lx_state = DWC_OTG_L0;
++00487         } else {
++00488                 if (core_if->lx_state != DWC_OTG_L1) {
++00489                         pcgcctl_data_t pcgcctl = {.d32 = 0 };
++00490 
++00491                         /* Restart the Phy Clock */
++00492                         pcgcctl.b.stoppclk = 1;
++00493                         DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32, 0);
++00494                         DWC_TIMER_SCHEDULE(core_if->wkp_timer, 71);
++00495                 } else {
++00497                         core_if->lx_state = DWC_OTG_L0;
++00498                 }
++00499         }
++00500 
++00501         /* Clear interrupt */
++00502         gintsts.d32 = 0;
++00503         gintsts.b.wkupintr = 1;
++00504         DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
++00505 
++00506         return 1;
++00507 }
++00508 
++00513 static int32_t dwc_otg_handle_pwrdn_disconnect_intr(dwc_otg_core_if_t *core_if)
++00514 {
++00515         gpwrdn_data_t gpwrdn = { .d32 = 0 };
++00516         gpwrdn_data_t gpwrdn_temp = { .d32 = 0 };
++00517         gpwrdn_temp.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
++00518 
++00519         DWC_PRINTF("%s called\n", __FUNCTION__);
++00520 
++00521         if (!core_if->hibernation_suspend) {
++00522                 DWC_PRINTF("Already exited from Hibernation\n");
++00523                 return 1;
++00524         }
++00525 
++00526         /* Switch on the voltage to the core */
++00527         gpwrdn.b.pwrdnswtch = 1;
++00528         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
++00529         dwc_udelay(10);
++00530 
++00531         /* Reset the core */
++00532         gpwrdn.d32 = 0;
++00533         gpwrdn.b.pwrdnrstn = 1;
++00534         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
++00535         dwc_udelay(10);
++00536 
++00537         /* Disable power clamps*/
++00538         gpwrdn.d32 = 0;
++00539         gpwrdn.b.pwrdnclmp = 1;
++00540         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
++00541 
++00542         /* Remove reset the core signal */
++00543         gpwrdn.d32 = 0;
++00544         gpwrdn.b.pwrdnrstn = 1;
++00545         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
++00546         dwc_udelay(10);
++00547 
++00548         /* Disable PMU interrupt */
++00549         gpwrdn.d32 = 0;
++00550         gpwrdn.b.pmuintsel = 1;
++00551         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
++00552 
++00553         core_if->hibernation_suspend = 0;
++00554 
++00555         /* Disable PMU */
++00556         gpwrdn.d32 = 0;
++00557         gpwrdn.b.pmuactv = 1;
++00558         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
++00559         dwc_udelay(10);
++00560 
++00561         if (gpwrdn_temp.b.idsts) {
++00562                 core_if->op_state = B_PERIPHERAL;
++00563                 dwc_otg_core_init(core_if);
++00564                 dwc_otg_enable_global_interrupts(core_if);
++00565                 cil_pcd_start(core_if);
++00566         } else {
++00567                 core_if->op_state = A_HOST;
++00568                 dwc_otg_core_init(core_if);
++00569                 dwc_otg_enable_global_interrupts(core_if);
++00570                 cil_hcd_start(core_if);
++00571         }
++00572 
++00573         return 1;
++00574 }
++00575 
++00580 static int32_t dwc_otg_handle_pwrdn_wakeup_detected_intr(dwc_otg_core_if_t * core_if)
++00581 {
++00582         gpwrdn_data_t gpwrdn = {.d32 = 0 };
++00583         DWC_DEBUGPL(DBG_ANY,
++00584                     "++Powerdown Remote Wakeup Detected Interrupt++\n");
++00585 
++00586         if (!core_if->hibernation_suspend) {
++00587                 DWC_PRINTF("Already exited from Hibernation\n");
++00588                 return 1;
++00589         }
++00590 
++00591         gpwrdn.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
++00592         if (gpwrdn.b.idsts) {   // Device Mode
++00593                 if ((core_if->power_down == 2)
++00594                     && (core_if->hibernation_suspend == 1)) {
++00595                         dwc_otg_device_hibernation_restore(core_if, 0, 0);
++00596                 }
++00597         } else {
++00598                 if ((core_if->power_down == 2)
++00599                     && (core_if->hibernation_suspend == 1)) {
++00600                         dwc_otg_host_hibernation_restore(core_if, 1, 0);
++00601                 }
++00602         }
++00603         return 1;
++00604 }
++00605 
++00606 static int32_t dwc_otg_handle_pwrdn_idsts_change(dwc_otg_device_t *otg_dev)
++00607 {
++00608         gpwrdn_data_t gpwrdn = {.d32 = 0 };
++00609         gpwrdn_data_t gpwrdn_temp = {.d32 = 0 };
++00610         dwc_otg_core_if_t *core_if = otg_dev->core_if;
++00611 
++00612         DWC_DEBUGPL(DBG_ANY, "%s called\n", __FUNCTION__);
++00613         gpwrdn_temp.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
++00614         if (core_if->power_down == 2)
++00615         {               
++00616                 if (!core_if->hibernation_suspend) {
++00617                         DWC_PRINTF("Already exited from Hibernation\n");
++00618                         return 1;
++00619                 }
++00620                 DWC_DEBUGPL(DBG_ANY, "Exit from hibernation on ID sts change\n");
++00621                 /* Switch on the voltage to the core */
++00622                 gpwrdn.b.pwrdnswtch = 1;
++00623                 DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
++00624                 dwc_udelay(10);
++00625 
++00626                 /* Reset the core */
++00627                 gpwrdn.d32 = 0;
++00628                 gpwrdn.b.pwrdnrstn = 1;
++00629                 DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
++00630                 dwc_udelay(10);
++00631 
++00632                 /* Disable power clamps */
++00633                 gpwrdn.d32 = 0;
++00634                 gpwrdn.b.pwrdnclmp = 1;
++00635                 DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
++00636 
++00637                 /* Remove reset the core signal */
++00638                 gpwrdn.d32 = 0;
++00639                 gpwrdn.b.pwrdnrstn = 1;
++00640                 DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
++00641                 dwc_udelay(10);
++00642 
++00643                 /* Disable PMU interrupt */
++00644                 gpwrdn.d32 = 0;
++00645                 gpwrdn.b.pmuintsel = 1;
++00646                 DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
++00647 
++00648                 /*Indicates that we are exiting from hibernation */
++00649                 core_if->hibernation_suspend = 0;
++00650 
++00651                 /* Disable PMU */
++00652                 gpwrdn.d32 = 0;
++00653                 gpwrdn.b.pmuactv = 1;
++00654                 DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
++00655                 dwc_udelay(10);
++00656 
++00657                 gpwrdn.d32 = core_if->gr_backup->gpwrdn_local;
++00658                 if (gpwrdn.b.dis_vbus == 1) {
++00659                         gpwrdn.d32 = 0;
++00660                         gpwrdn.b.dis_vbus = 1;
++00661                         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
++00662                 }
++00663 
++00664                 if (gpwrdn_temp.b.idsts) {
++00665                         core_if->op_state = B_PERIPHERAL;
++00666                         dwc_otg_core_init(core_if);
++00667                         dwc_otg_enable_global_interrupts(core_if);
++00668                         cil_pcd_start(core_if);
++00669                 } else {
++00670                         core_if->op_state = A_HOST;
++00671                         dwc_otg_core_init(core_if);
++00672                         dwc_otg_enable_global_interrupts(core_if);
++00673                         cil_hcd_start(core_if);
++00674                 }
++00675         }
++00676 
++00677         if (core_if->adp_enable)
++00678         {
++00679                 uint8_t is_host = 0;
++00680                 DWC_SPINUNLOCK(core_if->lock);
++00681                 /* Change the core_if's lock to hcd/pcd lock depend on mode? */
++00682 #ifndef DWC_HOST_ONLY           
++00683                 if (gpwrdn_temp.b.idsts)
++00684                         core_if->lock = otg_dev->pcd->lock;
++00685 #endif
++00686 #ifndef DWC_DEVICE_ONLY
++00687                 if (!gpwrdn_temp.b.idsts) {
++00688                                 core_if->lock = otg_dev->hcd->lock;     
++00689                                 is_host = 1;
++00690                 }
++00691 #endif
++00692                 DWC_PRINTF("RESTART ADP\n");
++00693                 if (core_if->adp.probe_enabled)         
++00694                         dwc_otg_adp_probe_stop(core_if);
++00695                 if (core_if->adp.sense_enabled)         
++00696                         dwc_otg_adp_sense_stop(core_if);
++00697                 if (core_if->adp.sense_timer_started)           
++00698                         DWC_TIMER_CANCEL(core_if->adp.sense_timer);
++00699                 if (core_if->adp.vbuson_timer_started)          
++00700                         DWC_TIMER_CANCEL(core_if->adp.vbuson_timer);
++00701                 core_if->adp.probe_timer_values[0] = -1;
++00702                 core_if->adp.probe_timer_values[1] = -1;
++00703                 core_if->adp.sense_timer_started = 0;
++00704                 core_if->adp.vbuson_timer_started = 0;
++00705                 core_if->adp.probe_counter = 0;
++00706                 core_if->adp.gpwrdn = 0;
++00707                 
++00708                 /* Disable PMU and restart ADP */
++00709                 gpwrdn_temp.d32 = 0;
++00710                 gpwrdn_temp.b.pmuactv = 1;
++00711                 gpwrdn_temp.b.pmuintsel = 1;
++00712                 DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
++00713                 DWC_PRINTF("Check point 1\n");
++00714                 dwc_mdelay(110);
++00715                 dwc_otg_adp_start(core_if, is_host);
++00716                 DWC_SPINLOCK(core_if->lock);
++00717         }
++00718         
++00719 
++00720         return 1;
++00721 }
++00722 
++00723 static int32_t dwc_otg_handle_pwrdn_session_change(dwc_otg_core_if_t * core_if)
++00724 {
++00725         gpwrdn_data_t gpwrdn = {.d32 = 0 };
++00726         int32_t otg_cap_param = core_if->core_params->otg_cap;
++00727         DWC_DEBUGPL(DBG_ANY, "%s called\n", __FUNCTION__);
++00728 
++00729         gpwrdn.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
++00730         if (core_if->power_down == 2) {
++00731                 if (!core_if->hibernation_suspend) {
++00732                         DWC_PRINTF("Already exited from Hibernation\n");
++00733                         return 1;
++00734                 }
++00735 
++00736                 if ((otg_cap_param != DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE ||
++00737                          otg_cap_param != DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE) &&
++00738                         gpwrdn.b.bsessvld == 0) {
++00739                         /* Save gpwrdn register for further usage if stschng interrupt */
++00740                         core_if->gr_backup->gpwrdn_local =
++00741                                 DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
++00742                         /*Exit from ISR and wait for stschng interrupt with bsessvld = 1 */
++00743                         return 1;
++00744                 }
++00745 
++00746                 /* Switch on the voltage to the core */
++00747                 gpwrdn.d32 = 0;
++00748                 gpwrdn.b.pwrdnswtch = 1;
++00749                 DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
++00750                 dwc_udelay(10);
++00751 
++00752                 /* Reset the core */
++00753                 gpwrdn.d32 = 0;
++00754                 gpwrdn.b.pwrdnrstn = 1;
++00755                 DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
++00756                 dwc_udelay(10);
++00757 
++00758                 /* Disable power clamps */
++00759                 gpwrdn.d32 = 0;
++00760                 gpwrdn.b.pwrdnclmp = 1;
++00761                 DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
++00762 
++00763                 /* Remove reset the core signal */
++00764                 gpwrdn.d32 = 0;
++00765                 gpwrdn.b.pwrdnrstn = 1;
++00766                 DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
++00767                 dwc_udelay(10);
++00768 
++00769                 /* Disable PMU interrupt */
++00770                 gpwrdn.d32 = 0;
++00771                 gpwrdn.b.pmuintsel = 1;
++00772                 DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
++00773                 dwc_udelay(10);
++00774 
++00775                 /*Indicates that we are exiting from hibernation */
++00776                 core_if->hibernation_suspend = 0;
++00777 
++00778                 /* Disable PMU */
++00779                 gpwrdn.d32 = 0;
++00780                 gpwrdn.b.pmuactv = 1;
++00781                 DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
++00782                 dwc_udelay(10);
++00783 
++00784                 core_if->op_state = B_PERIPHERAL;
++00785                 dwc_otg_core_init(core_if);
++00786                 dwc_otg_enable_global_interrupts(core_if);
++00787                 cil_pcd_start(core_if);
++00788 
++00789                 if (otg_cap_param == DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE ||
++00790                         otg_cap_param == DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE) {
++00791                         /*
++00792                          * Initiate SRP after initial ADP probe.
++00793                          */
++00794                         dwc_otg_initiate_srp(core_if);  
++00795                 }
++00796         }
++00797 
++00798         return 1;
++00799 }
++00804 static uint32_t dwc_otg_handle_pwrdn_stschng_intr(dwc_otg_device_t *otg_dev)
++00805 {
++00806         int retval;
++00807         gpwrdn_data_t gpwrdn = {.d32 = 0 };
++00808         gpwrdn_data_t gpwrdn_temp = {.d32 = 0 };
++00809         dwc_otg_core_if_t *core_if = otg_dev->core_if;
++00810 
++00811         DWC_PRINTF("%s called\n", __FUNCTION__);
++00812         
++00813         if (core_if->power_down == 2) {
++00814                 if (core_if->hibernation_suspend <= 0) {
++00815                         DWC_PRINTF("Already exited from Hibernation\n");
++00816                         return 1;
++00817                 } else
++00818                         gpwrdn_temp.d32 = core_if->gr_backup->gpwrdn_local;
++00819 
++00820         } else {
++00821                 gpwrdn_temp.d32 = core_if->adp.gpwrdn;
++00822         }
++00823 
++00824         gpwrdn.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
++00825         
++00826         if (gpwrdn.b.idsts ^ gpwrdn_temp.b.idsts) {
++00827                 retval = dwc_otg_handle_pwrdn_idsts_change(otg_dev);
++00828         } else if (gpwrdn.b.bsessvld ^ gpwrdn_temp.b.bsessvld) {
++00829                 retval = dwc_otg_handle_pwrdn_session_change(core_if);
++00830         }
++00831 
++00832         return retval;
++00833 }
++00834 
++00839 static int32_t dwc_otg_handle_pwrdn_srp_intr(dwc_otg_core_if_t * core_if)
++00840 {
++00841         gpwrdn_data_t gpwrdn = {.d32 = 0 };
++00842 
++00843         DWC_PRINTF("%s called\n", __FUNCTION__);
++00844 
++00845         if (!core_if->hibernation_suspend) {
++00846                 DWC_PRINTF("Already exited from Hibernation\n");
++00847                 return 1;
++00848         }
++00849 #ifdef DWC_DEV_SRPCAP
++00850         if (core_if->pwron_timer_started) {
++00851                 core_if->pwron_timer_started = 0;
++00852                 DWC_TIMER_CANCEL(core_if->pwron_timer);
++00853         }
++00854 #endif
++00855 
++00856         /* Switch on the voltage to the core */
++00857         gpwrdn.b.pwrdnswtch = 1;
++00858         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
++00859         dwc_udelay(10);
++00860 
++00861         /* Reset the core */
++00862         gpwrdn.d32 = 0;
++00863         gpwrdn.b.pwrdnrstn = 1;
++00864         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
++00865         dwc_udelay(10);
++00866 
++00867         /* Disable power clamps */
++00868         gpwrdn.d32 = 0;
++00869         gpwrdn.b.pwrdnclmp = 1;
++00870         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
++00871 
++00872         /* Remove reset the core signal */
++00873         gpwrdn.d32 = 0;
++00874         gpwrdn.b.pwrdnrstn = 1;
++00875         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
++00876         dwc_udelay(10);
++00877 
++00878         /* Disable PMU interrupt */
++00879         gpwrdn.d32 = 0;
++00880         gpwrdn.b.pmuintsel = 1;
++00881         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
++00882 
++00883         /* Indicates that we are exiting from hibernation */
++00884         core_if->hibernation_suspend = 0;
++00885 
++00886         /* Disable PMU */
++00887         gpwrdn.d32 = 0;
++00888         gpwrdn.b.pmuactv = 1;
++00889         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
++00890         dwc_udelay(10);
++00891 
++00892         /* Programm Disable VBUS to 0 */
++00893         gpwrdn.d32 = 0;
++00894         gpwrdn.b.dis_vbus = 1;
++00895         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
++00896 
++00897         /*Initialize the core as Host */
++00898         core_if->op_state = A_HOST;
++00899         dwc_otg_core_init(core_if);
++00900         dwc_otg_enable_global_interrupts(core_if);
++00901         cil_hcd_start(core_if);
++00902 
++00903         return 1;
++00904 }
++00905 
++00908 int32_t dwc_otg_handle_restore_done_intr(dwc_otg_core_if_t * core_if)
++00909 {
++00910         pcgcctl_data_t pcgcctl;
++00911         DWC_DEBUGPL(DBG_ANY, "++Restore Done Interrupt++\n");
++00912 
++00913         //TODO De-assert restore signal. 8.a
++00914         pcgcctl.d32 = DWC_READ_REG32(core_if->pcgcctl);
++00915         if (pcgcctl.b.restoremode == 1) {
++00916                 gintmsk_data_t gintmsk = {.d32 = 0 };
++00917                 /*
++00918                  * If restore mode is Remote Wakeup,
++00919                  * unmask Remote Wakeup interrupt.
++00920                  */
++00921                 gintmsk.b.wkupintr = 1;
++00922                 DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk,
++00923                                  0, gintmsk.d32);
++00924         }
++00925 
++00926         return 1;
++00927 }
++00928 
++00933 int32_t dwc_otg_handle_disconnect_intr(dwc_otg_core_if_t * core_if)
++00934 {
++00935         gintsts_data_t gintsts;
++00936 
++00937         DWC_DEBUGPL(DBG_ANY, "++Disconnect Detected Interrupt++ (%s) %s\n",
++00938                     (dwc_otg_is_host_mode(core_if) ? "Host" : "Device"),
++00939                     op_state_str(core_if));
++00940 
++00942 #ifndef DWC_HOST_ONLY
++00943         if (core_if->op_state == B_HOST) {
++00944                 /* If in device mode Disconnect and stop the HCD, then
++00945                  * start the PCD. */
++00946                 DWC_SPINUNLOCK(core_if->lock);
++00947                 cil_hcd_disconnect(core_if);
++00948                 cil_pcd_start(core_if);
++00949                 DWC_SPINLOCK(core_if->lock);
++00950                 core_if->op_state = B_PERIPHERAL;
++00951         } else if (dwc_otg_is_device_mode(core_if)) {
++00952                 gotgctl_data_t gotgctl = {.d32 = 0 };
++00953                 gotgctl.d32 =
++00954                     DWC_READ_REG32(&core_if->core_global_regs->gotgctl);
++00955                 if (gotgctl.b.hstsethnpen == 1) {
++00956                         /* Do nothing, if HNP in process the OTG
++00957                          * interrupt "Host Negotiation Detected"
++00958                          * interrupt will do the mode switch.
++00959                          */
++00960                 } else if (gotgctl.b.devhnpen == 0) {
++00961                         /* If in device mode Disconnect and stop the HCD, then
++00962                          * start the PCD. */
++00963                         DWC_SPINUNLOCK(core_if->lock);
++00964                         cil_hcd_disconnect(core_if);
++00965                         cil_pcd_start(core_if);
++00966                         DWC_SPINLOCK(core_if->lock);
++00967                         core_if->op_state = B_PERIPHERAL;
++00968                 } else {
++00969                         DWC_DEBUGPL(DBG_ANY, "!a_peripheral && !devhnpen\n");
++00970                 }
++00971         } else {
++00972                 if (core_if->op_state == A_HOST) {
++00973                         /* A-Cable still connected but device disconnected. */
++00974                         cil_hcd_disconnect(core_if);
++00975                         if (core_if->adp_enable) {
++00976                                 gpwrdn_data_t gpwrdn = { .d32 = 0 };
++00977                                 cil_hcd_stop(core_if);
++00978                                 /* Enable Power Down Logic */
++00979                                 gpwrdn.b.pmuintsel = 1;
++00980                                 gpwrdn.b.pmuactv = 1;
++00981                                 DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
++00982                                 dwc_otg_adp_probe_start(core_if);
++00983 
++00984                                 /* Power off the core */
++00985                                 if (core_if->power_down == 2) {
++00986                                         gpwrdn.d32 = 0;
++00987                                         gpwrdn.b.pwrdnswtch = 1;
++00988                                         DWC_MODIFY_REG32(&core_if->
++00989                                                          core_global_regs->
++00990                                                          gpwrdn, gpwrdn.d32, 0);
++00991                                 }
++00992                         }
++00993                 }
++00994         }
++00995 #endif
++00996         /* Change to L3(OFF) state */
++00997         core_if->lx_state = DWC_OTG_L3;
++00998 
++00999         gintsts.d32 = 0;
++01000         gintsts.b.disconnect = 1;
++01001         DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
++01002         return 1;
++01003 }
++01004 
++01015 int32_t dwc_otg_handle_usb_suspend_intr(dwc_otg_core_if_t * core_if)
++01016 {
++01017         dsts_data_t dsts;
++01018         gintsts_data_t gintsts;
++01019         dcfg_data_t dcfg;
++01020 
++01021         DWC_DEBUGPL(DBG_ANY, "USB SUSPEND\n");
++01022 
++01023         if (dwc_otg_is_device_mode(core_if)) {
++01024                 /* Check the Device status register to determine if the Suspend
++01025                  * state is active. */
++01026                 dsts.d32 =
++01027                     DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts);
++01028                 DWC_DEBUGPL(DBG_PCD, "DSTS=0x%0x\n", dsts.d32);
++01029                 DWC_DEBUGPL(DBG_PCD, "DSTS.Suspend Status=%d "
++01030                             "HWCFG4.power Optimize=%d\n",
++01031                             dsts.b.suspsts, core_if->hwcfg4.b.power_optimiz);
++01032 
++01033 #ifdef PARTIAL_POWER_DOWN
++01034 
++01036                 if (dsts.b.suspsts && core_if->hwcfg4.b.power_optimiz) {
++01037                         pcgcctl_data_t power = {.d32 = 0 };
++01038                         DWC_DEBUGPL(DBG_CIL, "suspend\n");
++01039 
++01040                         power.b.pwrclmp = 1;
++01041                         DWC_WRITE_REG32(core_if->pcgcctl, power.d32);
++01042 
++01043                         power.b.rstpdwnmodule = 1;
++01044                         DWC_MODIFY_REG32(core_if->pcgcctl, 0, power.d32);
++01045 
++01046                         power.b.stoppclk = 1;
++01047                         DWC_MODIFY_REG32(core_if->pcgcctl, 0, power.d32);
++01048 
++01049                 } else {
++01050                         DWC_DEBUGPL(DBG_ANY, "disconnect?\n");
++01051                 }
++01052 #endif
++01053                 /* PCD callback for suspend. Release the lock inside of callback function */
++01054                 cil_pcd_suspend(core_if);
++01055                 if (core_if->power_down == 2)
++01056                 {
++01057                         dcfg.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg);
++01058                         DWC_DEBUGPL(DBG_ANY,"lx_state = %08x\n",core_if->lx_state);
++01059                         DWC_DEBUGPL(DBG_ANY," device address = %08d\n",dcfg.b.devaddr);
++01060 
++01061                         if (core_if->lx_state != DWC_OTG_L3 && dcfg.b.devaddr) {
++01062                                 pcgcctl_data_t pcgcctl = {.d32 = 0 };
++01063                                 gpwrdn_data_t gpwrdn = {.d32 = 0 };
++01064                                 gusbcfg_data_t gusbcfg = {.d32 = 0 };
++01065 
++01066                                 /* Change to L2(suspend) state */
++01067                                 core_if->lx_state = DWC_OTG_L2;
++01068 
++01069                                 /* Clear interrupt in gintsts */
++01070                                 gintsts.d32 = 0;
++01071                                 gintsts.b.usbsuspend = 1;
++01072                                 DWC_WRITE_REG32(&core_if->core_global_regs->
++01073                                                 gintsts, gintsts.d32);
++01074                                 DWC_PRINTF("Start of hibernation completed\n");
++01075                                 dwc_otg_save_global_regs(core_if);
++01076                                 dwc_otg_save_dev_regs(core_if);
++01077 
++01078                                 gusbcfg.d32 =
++01079                                     DWC_READ_REG32(&core_if->core_global_regs->
++01080                                                    gusbcfg);
++01081                                 if (gusbcfg.b.ulpi_utmi_sel == 1) {
++01082                                         /* ULPI interface */
++01083                                         /* Suspend the Phy Clock */
++01084                                         pcgcctl.d32 = 0;
++01085                                         pcgcctl.b.stoppclk = 1;
++01086                                         DWC_MODIFY_REG32(core_if->pcgcctl, 0,
++01087                                                          pcgcctl.d32);
++01088                                         dwc_udelay(10);
++01089                                         gpwrdn.b.pmuactv = 1;
++01090                                         DWC_MODIFY_REG32(&core_if->
++01091                                                          core_global_regs->
++01092                                                          gpwrdn, 0, gpwrdn.d32);
++01093                                 } else {
++01094                                         /* UTMI+ Interface */
++01095                                         gpwrdn.b.pmuactv = 1;
++01096                                         DWC_MODIFY_REG32(&core_if->
++01097                                                          core_global_regs->
++01098                                                          gpwrdn, 0, gpwrdn.d32);
++01099                                         dwc_udelay(10);
++01100                                         pcgcctl.b.stoppclk = 1;
++01101                                         DWC_MODIFY_REG32(core_if->pcgcctl, 0,
++01102                                                          pcgcctl.d32);
++01103                                         dwc_udelay(10);
++01104                                 }
++01105 
++01106                                 /* Set flag to indicate that we are in hibernation */
++01107                                 core_if->hibernation_suspend = 1;
++01108                                 /* Enable interrupts from wake up logic */
++01109                                 gpwrdn.d32 = 0;
++01110                                 gpwrdn.b.pmuintsel = 1;
++01111                                 DWC_MODIFY_REG32(&core_if->core_global_regs->
++01112                                                  gpwrdn, 0, gpwrdn.d32);
++01113                                 dwc_udelay(10);
++01114 
++01115                                 /* Unmask device mode interrupts in GPWRDN */
++01116                                 gpwrdn.d32 = 0;
++01117                                 gpwrdn.b.rst_det_msk = 1;
++01118                                 gpwrdn.b.lnstchng_msk = 1;
++01119                                 gpwrdn.b.sts_chngint_msk = 1;
++01120                                 DWC_MODIFY_REG32(&core_if->core_global_regs->
++01121                                                  gpwrdn, 0, gpwrdn.d32);
++01122                                 dwc_udelay(10);
++01123 
++01124                                 /* Enable Power Down Clamp */
++01125                                 gpwrdn.d32 = 0;
++01126                                 gpwrdn.b.pwrdnclmp = 1;
++01127                                 DWC_MODIFY_REG32(&core_if->core_global_regs->
++01128                                                  gpwrdn, 0, gpwrdn.d32);
++01129                                 dwc_udelay(10);
++01130 
++01131                                 /* Switch off VDD */
++01132                                 gpwrdn.d32 = 0;
++01133                                 gpwrdn.b.pwrdnswtch = 1;
++01134                                 DWC_MODIFY_REG32(&core_if->core_global_regs->
++01135                                                  gpwrdn, 0, gpwrdn.d32);
++01136 
++01137                                 /* Save gpwrdn register for further usage if stschng interrupt */
++01138                                 core_if->gr_backup->gpwrdn_local =
++01139                                                         DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
++01140                                 DWC_PRINTF("Hibernation completed\n");
++01141 
++01142                                 return 1;
++01143                         }
++01144                 }
++01145         } else {
++01146                 if (core_if->op_state == A_PERIPHERAL) {
++01147                         DWC_DEBUGPL(DBG_ANY, "a_peripheral->a_host\n");
++01148                         /* Clear the a_peripheral flag, back to a_host. */
++01149                         DWC_SPINUNLOCK(core_if->lock);
++01150                         cil_pcd_stop(core_if);
++01151                         cil_hcd_start(core_if);
++01152                         DWC_SPINLOCK(core_if->lock);
++01153                         core_if->op_state = A_HOST;
++01154                 }
++01155         }
++01156 
++01157         /* Change to L2(suspend) state */
++01158         core_if->lx_state = DWC_OTG_L2;
++01159 
++01160         /* Clear interrupt */
++01161         gintsts.d32 = 0;
++01162         gintsts.b.usbsuspend = 1;
++01163         DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
++01164 
++01165         return 1;
++01166 }
++01167 
++01168 #ifdef CONFIG_USB_DWC_OTG_LPM
++01169 
++01172 static int32_t dwc_otg_handle_lpm_intr(dwc_otg_core_if_t * core_if)
++01173 {
++01174         glpmcfg_data_t lpmcfg;
++01175         gintsts_data_t gintsts;
++01176 
++01177         if (!core_if->core_params->lpm_enable) {
++01178                 DWC_PRINTF("Unexpected LPM interrupt\n");
++01179         }
++01180 
++01181         lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
++01182         DWC_PRINTF("LPM config register = 0x%08x\n", lpmcfg.d32);
++01183 
++01184         if (dwc_otg_is_host_mode(core_if)) {
++01185                 cil_hcd_sleep(core_if);
++01186         } else {
++01187                 lpmcfg.b.hird_thres |= (1 << 4);
++01188                 DWC_WRITE_REG32(&core_if->core_global_regs->glpmcfg,
++01189                                 lpmcfg.d32);
++01190         }
++01191 
++01192         /* Examine prt_sleep_sts after TL1TokenTetry period max (10 us) */
++01193         dwc_udelay(10);
++01194         lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
++01195         if (lpmcfg.b.prt_sleep_sts) {
++01196                 /* Save the current state */
++01197                 core_if->lx_state = DWC_OTG_L1;
++01198         }
++01199 
++01200         /* Clear interrupt  */
++01201         gintsts.d32 = 0;
++01202         gintsts.b.lpmtranrcvd = 1;
++01203         DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
++01204         return 1;
++01205 }
++01206 #endif /* CONFIG_USB_DWC_OTG_LPM */
++01207 
++01211 static inline uint32_t dwc_otg_read_common_intr(dwc_otg_core_if_t * core_if)
++01212 {
++01213         gahbcfg_data_t gahbcfg = {.d32 = 0 };
++01214         gintsts_data_t gintsts;
++01215         gintmsk_data_t gintmsk;
++01216         gintmsk_data_t gintmsk_common = {.d32 = 0 };
++01217         gintmsk_common.b.wkupintr = 1;
++01218         gintmsk_common.b.sessreqintr = 1;
++01219         gintmsk_common.b.conidstschng = 1;
++01220         gintmsk_common.b.otgintr = 1;
++01221         gintmsk_common.b.modemismatch = 1;
++01222         gintmsk_common.b.disconnect = 1;
++01223         gintmsk_common.b.usbsuspend = 1;
++01224 #ifdef CONFIG_USB_DWC_OTG_LPM
++01225         gintmsk_common.b.lpmtranrcvd = 1;
++01226 #endif
++01227         gintmsk_common.b.restoredone = 1;
++01231         gintmsk_common.b.portintr = 1;
++01232 
++01233         gintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts);
++01234         gintmsk.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintmsk);
++01235         gahbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gahbcfg);
++01236 
++01237 #ifdef DEBUG
++01238         /* if any common interrupts set */
++01239         if (gintsts.d32 & gintmsk_common.d32) {
++01240                 DWC_DEBUGPL(DBG_ANY, "gintsts=%08x  gintmsk=%08x\n",
++01241                             gintsts.d32, gintmsk.d32);
++01242         }
++01243 #endif
++01244         if (gahbcfg.b.glblintrmsk)      
++01245                 return ((gintsts.d32 & gintmsk.d32) & gintmsk_common.d32);
++01246         else
++01247                 return 0;
++01248 
++01249 }
++01250 
++01251 /* MACRO for clearing interupt bits in GPWRDN register */
++01252 #define CLEAR_GPWRDN_INTR(__core_if,__intr) \
++01253 do { \
++01254                 gpwrdn_data_t gpwrdn = {.d32=0}; \
++01255                 gpwrdn.b.__intr = 1; \
++01256                 DWC_MODIFY_REG32(&__core_if->core_global_regs->gpwrdn, \
++01257                 0, gpwrdn.d32); \
++01258 } while (0)
++01259 
++01275 int32_t dwc_otg_handle_common_intr(void *dev)
++01276 {
++01277         int retval = 0;
++01278         gintsts_data_t gintsts;
++01279         gpwrdn_data_t gpwrdn = {.d32 = 0 };
++01280         dwc_otg_device_t *otg_dev = dev;
++01281         dwc_otg_core_if_t *core_if = otg_dev->core_if;
++01282         gpwrdn.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
++01283         if (dwc_otg_is_device_mode(core_if))
++01284                 core_if->frame_num = dwc_otg_get_frame_number(core_if);
++01285                 
++01286         if (core_if->lock)
++01287                 DWC_SPINLOCK(core_if->lock);
++01288 
++01289         if (core_if->hibernation_suspend <= 0) {
++01290                 gintsts.d32 = dwc_otg_read_common_intr(core_if);
++01291 
++01292                 if (gintsts.b.modemismatch) {
++01293                         retval |= dwc_otg_handle_mode_mismatch_intr(core_if);
++01294                 }
++01295                 if (gintsts.b.otgintr) {
++01296                         retval |= dwc_otg_handle_otg_intr(core_if);
++01297                 }
++01298                 if (gintsts.b.conidstschng) {
++01299                         retval |= dwc_otg_handle_conn_id_status_change_intr(core_if);
++01300                 }
++01301                 if (gintsts.b.disconnect) {
++01302                         retval |= dwc_otg_handle_disconnect_intr(core_if);
++01303                 }
++01304                 if (gintsts.b.sessreqintr) {
++01305                         retval |= dwc_otg_handle_session_req_intr(core_if);
++01306                 }
++01307                 if (gintsts.b.wkupintr) {
++01308                         retval |= dwc_otg_handle_wakeup_detected_intr(core_if);
++01309                 }
++01310                 if (gintsts.b.usbsuspend) {
++01311                         retval |= dwc_otg_handle_usb_suspend_intr(core_if);
++01312                 }
++01313 #ifdef CONFIG_USB_DWC_OTG_LPM
++01314                 if (gintsts.b.lpmtranrcvd) {
++01315                         retval |= dwc_otg_handle_lpm_intr(core_if);
++01316                 }
++01317 #endif
++01318                 if (gintsts.b.restoredone) {
++01319                         gintsts.d32 = 0;
++01320                         if (core_if->power_down == 2)
++01321                                 core_if->hibernation_suspend = -1;
++01322                         gintsts.b.restoredone = 1;
++01323                         DWC_WRITE_REG32(&core_if->core_global_regs->gintsts,gintsts.d32);
++01324                         DWC_PRINTF(" --Restore done interrupt received-- \n");
++01325                         retval |= 1;
++01326                 }
++01327                 if (gintsts.b.portintr && dwc_otg_is_device_mode(core_if)) {
++01328                         /* The port interrupt occurs while in device mode with HPRT0
++01329                          * Port Enable/Disable.
++01330                          */
++01331                         gintsts.d32 = 0;
++01332                         gintsts.b.portintr = 1;
++01333                         DWC_WRITE_REG32(&core_if->core_global_regs->gintsts,gintsts.d32);
++01334                         retval |= 1;
++01335 
++01336                 }
++01337         } else {
++01338                 DWC_DEBUGPL(DBG_ANY, "gpwrdn=%08x\n", gpwrdn.d32);
++01339 
++01340                 if (gpwrdn.b.disconn_det && gpwrdn.b.disconn_det_msk) {
++01341                         CLEAR_GPWRDN_INTR(core_if, disconn_det);
++01342                         if (gpwrdn.b.linestate == 0) {
++01343                                 dwc_otg_handle_pwrdn_disconnect_intr(core_if);
++01344                         } else {
++01345                                 DWC_PRINTF("Disconnect detected while linestate is not 0\n");
++01346                         }
++01347 
++01348                         retval |= 1;
++01349                 }
++01350                 if (gpwrdn.b.lnstschng && gpwrdn.b.lnstchng_msk) {
++01351                         CLEAR_GPWRDN_INTR(core_if, lnstschng);
++01352                         /* remote wakeup from hibernation */
++01353                         if (gpwrdn.b.linestate == 2 || gpwrdn.b.linestate == 1) {
++01354                                 dwc_otg_handle_pwrdn_wakeup_detected_intr(core_if);
++01355                         } else {
++01356                                 DWC_PRINTF("gpwrdn.linestate = %d\n", gpwrdn.b.linestate);
++01357                         }
++01358                         retval |= 1;
++01359                 }
++01360                 if (gpwrdn.b.rst_det && gpwrdn.b.rst_det_msk) {
++01361                         CLEAR_GPWRDN_INTR(core_if, rst_det);
++01362                         if (gpwrdn.b.linestate == 0) {
++01363                                 DWC_PRINTF("Reset detected\n");
++01364                                 retval |= dwc_otg_device_hibernation_restore(core_if, 0, 1);
++01365                         }
++01366                 }
++01367                 if (gpwrdn.b.srp_det && gpwrdn.b.srp_det_msk) {
++01368                         CLEAR_GPWRDN_INTR(core_if, srp_det);
++01369                         dwc_otg_handle_pwrdn_srp_intr(core_if);
++01370                         retval |= 1;
++01371                 }
++01372         }
++01373         /* Handle ADP interrupt here */
++01374         if (gpwrdn.b.adp_int) {
++01375                 DWC_PRINTF("ADP interrupt\n");
++01376                 CLEAR_GPWRDN_INTR(core_if, adp_int);
++01377                 dwc_otg_adp_handle_intr(core_if);
++01378                 retval |= 1;
++01379         }
++01380         if (gpwrdn.b.sts_chngint && gpwrdn.b.sts_chngint_msk) {
++01381                 DWC_PRINTF("STS CHNG interrupt asserted\n");
++01382                 CLEAR_GPWRDN_INTR(core_if, sts_chngint);
++01383                 dwc_otg_handle_pwrdn_stschng_intr(otg_dev);
++01384 
++01385                 retval |= 1;
++01386         }
++01387         if (core_if->lock)
++01388                 DWC_SPINUNLOCK(core_if->lock);
++01389 
++01390         return retval;
++01391 }
++
    Generated on Thu Oct 27 03:56:37 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
    ++doxygen 1.3.9.1
    + + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__cil__intr_8c.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/dwc__otg__cil__intr_8c.html 2013-07-26 19:31:20.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__cil__intr_8c.html 2013-07-26 19:34:40.000000000 +0000 +@@ -2,387 +2,158 @@ + + DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_cil_intr.c File Reference + +- + +- +-
    +-
    +-
    +-
    ++ ++
    Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
    +

    dwc_otg_cil_intr.c File Reference

    The Core Interface Layer provides basic services for accessing and managing the DWC_otg hardware. More... +

    +-#include "dwc_os.h"
    +-#include "dwc_otg_regs.h"
    +-#include "dwc_otg_cil.h"
    ++#include "dwc_os.h"
    ++#include "dwc_otg_regs.h"
    ++#include "dwc_otg_cil.h"
    ++#include "dwc_otg_driver.h"
    ++#include "dwc_otg_pcd.h"
    ++#include "dwc_otg_hcd.h"
    + +

    + Go to the source code of this file. + +- +- +- +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- ++ + +- +- ++ + +- +- ++ ++ + +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- ++ +

    Functions

    int32_t dwc_otg_handle_mode_mismatch_intr (dwc_otg_core_if_t *core_if)
     This function will log a debug message.
    static void hcd_start (dwc_otg_core_if_t *core_if)

    Defines

    #define CLEAR_GPWRDN_INTR(__core_if, __intr)
     Start the HCD.
    static void hcd_stop (dwc_otg_core_if_t *core_if)

    Functions

    int32_t dwc_otg_handle_mode_mismatch_intr (dwc_otg_core_if_t *core_if)
     Stop the HCD.
    static void hcd_disconnect (dwc_otg_core_if_t *core_if)
     This function will log a debug message.
    int32_t dwc_otg_handle_otg_intr (dwc_otg_core_if_t *core_if)
     Disconnect the HCD.
    static void hcd_session_start (dwc_otg_core_if_t *core_if)
     This function handles the OTG Interrupts.
    ++void w_conn_id_status_change (void *p)
     Inform the HCD the a New Session has begun.
    static void hcd_resume (dwc_otg_core_if_t *core_if)
    int32_t dwc_otg_handle_conn_id_status_change_intr (dwc_otg_core_if_t *core_if)
     Resume the HCD.
    static void pcd_start (dwc_otg_core_if_t *core_if)
     This function handles the Connector ID Status Change Interrupt.
    int32_t dwc_otg_handle_session_req_intr (dwc_otg_core_if_t *core_if)
     Start the PCD.
    static void pcd_stop (dwc_otg_core_if_t *core_if)
     This interrupt indicates that a device is initiating the Session Request Protocol to request the host to turn on bus power so a new session can begin.
    void w_wakeup_detected (void *p)
     Stop the PCD.
    static void pcd_suspend (dwc_otg_core_if_t *core_if)
    int32_t dwc_otg_handle_wakeup_detected_intr (dwc_otg_core_if_t *core_if)
     Suspend the PCD.
    static void pcd_resume (dwc_otg_core_if_t *core_if)
     This interrupt indicates that the DWC_otg controller has detected a resume or remote wakeup sequence.
    ++int32_t dwc_otg_handle_pwrdn_disconnect_intr (dwc_otg_core_if_t *core_if)
     Resume the PCD.
    int32_t dwc_otg_handle_otg_intr (dwc_otg_core_if_t *core_if)
     This interrupt indicates that the Wakeup Logic has detected a Device disconnect.
    ++int32_t dwc_otg_handle_pwrdn_wakeup_detected_intr (dwc_otg_core_if_t *core_if)
     This function handles the OTG Interrupts.
    +-void w_conn_id_status_change (void *p)
     This interrupt indicates that the Wakeup Logic has detected a remote wakeup sequence.
    ++int32_t dwc_otg_handle_pwrdn_idsts_change (dwc_otg_device_t *otg_dev)
    int32_t dwc_otg_handle_conn_id_status_change_intr (dwc_otg_core_if_t *core_if)
    ++int32_t dwc_otg_handle_pwrdn_session_change (dwc_otg_core_if_t *core_if)
     This function handles the Connector ID Status Change Interrupt.
    int32_t dwc_otg_handle_session_req_intr (dwc_otg_core_if_t *core_if)
    ++uint32_t dwc_otg_handle_pwrdn_stschng_intr (dwc_otg_device_t *otg_dev)
     This interrupt indicates that a device is initiating the Session Request Protocol to request the host to turn on bus power so a new session can begin.
    void w_wakeup_detected (void *p)
     This interrupt indicates that the Wakeup Logic has detected a status change either on IDDIG or BSessVld.
    ++int32_t dwc_otg_handle_pwrdn_srp_intr (dwc_otg_core_if_t *core_if)
    int32_t dwc_otg_handle_wakeup_detected_intr (dwc_otg_core_if_t *core_if)
     This interrupt indicates that the Wakeup Logic has detected a SRP.
    ++int32_t dwc_otg_handle_restore_done_intr (dwc_otg_core_if_t *core_if)
     This interrupt indicates that the DWC_otg controller has detected a resume or remote wakeup sequence.
    int32_t dwc_otg_handle_disconnect_intr (dwc_otg_core_if_t *core_if)
     This interrupt indicates that restore command after Hibernation was completed by the core.
    int32_t dwc_otg_handle_disconnect_intr (dwc_otg_core_if_t *core_if)
     This interrupt indicates that a device has been disconnected from the root port.
    int32_t dwc_otg_handle_usb_suspend_intr (dwc_otg_core_if_t *core_if)
     This interrupt indicates that a device has been disconnected from the root port.
    int32_t dwc_otg_handle_usb_suspend_intr (dwc_otg_core_if_t *core_if)
     This interrupt indicates that SUSPEND state has been detected on the USB.
    static uint32_t dwc_otg_read_common_intr (dwc_otg_core_if_t *core_if)
     This interrupt indicates that SUSPEND state has been detected on the USB.
    uint32_t dwc_otg_read_common_intr (dwc_otg_core_if_t *core_if)
     This function returns the Core Interrupt register.
    int32_t dwc_otg_handle_common_intr (dwc_otg_core_if_t *core_if)
     This function returns the Core Interrupt register.
    int32_t dwc_otg_handle_common_intr (void *dev)
     This function should be called on every hardware interrupt.
     This function should be called on every hardware interrupt.
    +

    Detailed Description

    + The Core Interface Layer provides basic services for accessing and managing the DWC_otg hardware. +

    + These services are used by both the Host Controller Driver and the Peripheral Controller Driver.

    +-This file contains the Common Interrupt handlers. +-

    +-Definition in file dwc_otg_cil_intr.c.

    Function Documentation

    +- +-
    +-
    +- +- +- +- +- +- +- +- +- +-
    int32_t dwc_otg_handle_mode_mismatch_intr (dwc_otg_core_if_t *  core_if  ) 
    +-
    +-
    +- +-

    +-This function will log a debug message. +-

    +-

    Parameters:
    +- +- +-
    core_if Programming view of DWC_otg controller.
    +-
    +- +-

    +-Definition at line 61 of file dwc_otg_cil_intr.c. +-

    +-

    +- +-

    +-
    +- +- +- +- +- +- +- +- +- +-
    static void hcd_start (dwc_otg_core_if_t *  core_if  )  [inline, static]
    +-
    +-
    +- +-

    +-Start the HCD. +-

    +-Helper function for using the HCD callbacks.

    +-

    Parameters:
    +- +- +-
    core_if Programming view of DWC_otg controller.
    +-
    +- +-

    +-Definition at line 78 of file dwc_otg_cil_intr.c. +-

    +-

    +- +-

    +-
    +- +- +- +- +- +- +- +- +- +-
    static void hcd_stop (dwc_otg_core_if_t *  core_if  )  [inline, static]
    +-
    +-
    +- +-

    +-Stop the HCD. +-

    +-Helper function for using the HCD callbacks.

    +-

    Parameters:
    +- +- +-
    core_if Programming view of DWC_otg controller.
    +-
    +- +-

    +-Definition at line 89 of file dwc_otg_cil_intr.c. +-

    +-

    +- +-

    +-
    +- +- +- +- +- +- +- +- +- +-
    static void hcd_disconnect (dwc_otg_core_if_t *  core_if  )  [inline, static]
    +-
    +-
    +- +-

    +-Disconnect the HCD. +-

    +-Helper function for using the HCD callbacks.

    +-

    Parameters:
    +- +- +-
    core_if Programming view of DWC_otg controller.
    +-
    +- +-

    +-Definition at line 100 of file dwc_otg_cil_intr.c. +-

    +-

    +- +-

    +-
    +- +- +- +- +- +- +- +- +- +-
    static void hcd_session_start (dwc_otg_core_if_t *  core_if  )  [inline, static]
    +-
    +-
    +- +-

    +-Inform the HCD the a New Session has begun. +-

    +-Helper function for using the HCD callbacks.

    +-

    Parameters:
    +- +- +-
    core_if Programming view of DWC_otg controller.
    +-
    +- +-

    +-Definition at line 112 of file dwc_otg_cil_intr.c. +-

    +-

    +- +-

    +-
    +- +- +- +- +- +- +- +- +- +-
    static void hcd_resume (dwc_otg_core_if_t *  core_if  )  [inline, static]
    +-
    +-
    +- +-

    +-Resume the HCD. +-

    +-Helper function for using the HCD callbacks.

    +-

    Parameters:
    +- +- +-
    core_if Programming view of DWC_otg controller.
    +-
    +- +-

    +-Definition at line 138 of file dwc_otg_cil_intr.c. +-

    +-

    +- +-

    +-
    +- +- +- +- +- +- +- +- +- +-
    static void pcd_start (dwc_otg_core_if_t *  core_if  )  [inline, static]
    +-
    +-
    +- +-

    +-Start the PCD. +-

    +-Helper function for using the PCD callbacks.

    +-

    Parameters:
    +- +- +-
    core_if Programming view of DWC_otg controller.
    +-
    +- ++This file contains the Common Interrupt handlers. +

    +-Definition at line 149 of file dwc_otg_cil_intr.c. +-

    +-

    +- +-

    +-
    +- +- +- +- +- +- +- +- ++Definition in file dwc_otg_cil_intr.c.

    Define Documentation

    ++

    ++

    static void pcd_stop (dwc_otg_core_if_t *  core_if  )  [inline, static]
    ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ + +
    #define CLEAR_GPWRDN_INTR ( __core_if,
    __intr   ) 
    +- +-
    +- +-

    +-Stop the PCD. +-

    +-Helper function for using the PCD callbacks.

    +-

    Parameters:
    +- +- +-
    core_if Programming view of DWC_otg controller.
    +-
    +- +-

    +-Definition at line 160 of file dwc_otg_cil_intr.c. +-

    +-

    +- +-

    +-
    +- +- +- +- +- +- +- +- +- +-
    static void pcd_suspend (dwc_otg_core_if_t *  core_if  )  [inline, static]
    +-
    +-
    +- +-

    +-Suspend the PCD. +-

    +-Helper function for using the PCD callbacks.

    +-

    Parameters:
    +- +- +-
    core_if Programming view of DWC_otg controller.
    +-
    +- ++
    ++ ++ ++ ++
    ++   ++ ++ ++

    ++Value:

    do { \
++                gpwrdn_data_t gpwrdn = {.d32=0}; \
++                gpwrdn.b.__intr = 1; \
++                DWC_MODIFY_REG32(&__core_if->core_global_regs->gpwrdn, \
++                0, gpwrdn.d32); \
++} while (0)
++
    +

    +-Definition at line 171 of file dwc_otg_cil_intr.c. +- +-

    +- +-

    +-
    +- +- +- +- +- +- +- +- ++Definition at line 1252 of file dwc_otg_cil_intr.c. ++ ++
    static void pcd_resume (dwc_otg_core_if_t *  core_if  )  [inline, static]
    ++

    Function Documentation

    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ + +
    int32_t dwc_otg_handle_mode_mismatch_intr ( dwc_otg_core_if_t *  core_if  ) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    +-Resume the PCD. ++This function will log a debug message. +

    +-Helper function for using the PCD callbacks.

    +

    Parameters:
    + + +@@ -390,24 +161,32 @@ + + +

    +-Definition at line 182 of file dwc_otg_cil_intr.c. +- +-

    +- +-

    +-
    +-
    core_if Programming view of DWC_otg controller.
    +- +- +- +- +- +- +- ++Definition at line 64 of file dwc_otg_cil_intr.c. ++ ++
    int32_t dwc_otg_handle_otg_intr (dwc_otg_core_if_t *  core_if  ) 
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ + +
    int32_t dwc_otg_handle_otg_intr ( dwc_otg_core_if_t *  core_if  ) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + This function handles the OTG Interrupts. +@@ -420,24 +199,32 @@ + + +

    +-Definition at line 196 of file dwc_otg_cil_intr.c. +- +-

    +- +-

    +-
    +- +- +- +- +- +- +- +- ++Definition at line 84 of file dwc_otg_cil_intr.c. ++ ++
    int32_t dwc_otg_handle_conn_id_status_change_intr (dwc_otg_core_if_t *  core_if  ) 
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ + +
    int32_t dwc_otg_handle_conn_id_status_change_intr ( dwc_otg_core_if_t *  core_if  ) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + This function handles the Connector ID Status Change Interrupt. +@@ -451,24 +238,32 @@ + + +

    +-Definition at line 399 of file dwc_otg_cil_intr.c. +- +-

    +- +-

    +-
    +- +- +- +- +- +- +- +- ++Definition at line 319 of file dwc_otg_cil_intr.c. ++ ++
    int32_t dwc_otg_handle_session_req_intr (dwc_otg_core_if_t *  core_if  ) 
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ + +
    int32_t dwc_otg_handle_session_req_intr ( dwc_otg_core_if_t *  core_if  ) 
    +- +-
    ++
    ++ ++ ++ ++ ++ ++
    ++   ++ + +

    + This interrupt indicates that a device is initiating the Session Request Protocol to request the host to turn on bus power so a new session can begin. +@@ -481,100 +276,129 @@ + + +

    +-Definition at line 441 of file dwc_otg_cil_intr.c. +- +-

    +- +-

    +-
    +- +- +- +- +- +- +- +- +- +-
    void w_wakeup_detected (void *  p  ) 
    +-
    +-
    ++Definition at line 366 of file dwc_otg_cil_intr.c.
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
    void w_wakeup_detected ( void *  p  ) 
    ++
    ++ ++ ++ ++
    ++   ++ + +

    +- ++Change to L0 state +

    +-Definition at line 473 of file dwc_otg_cil_intr.c. +- +-

    +- +-

    +-
    +- +- +- +- +- +- +- +- ++Definition at line 398 of file dwc_otg_cil_intr.c. ++ ++
    int32_t dwc_otg_handle_wakeup_detected_intr (dwc_otg_core_if_t *  core_if  ) 
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ + +
    int32_t dwc_otg_handle_wakeup_detected_intr ( dwc_otg_core_if_t *  core_if  ) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + This interrupt indicates that the DWC_otg controller has detected a resume or remote wakeup sequence. +

    +-If the DWC_otg controller is in low power mode, the handler must brings the controller out of low power mode. The controller automatically begins resume signaling. The handler schedules a time to stop resume signaling. +-

    ++If the DWC_otg controller is in low power mode, the handler must brings the controller out of low power mode. The controller automatically begins resume signaling. The handler schedules a time to stop resume signaling.

    + Change to L0 state

    + Change to L0 state +

    +-Definition at line 510 of file dwc_otg_cil_intr.c. +- +-

    +- +-

    +-
    +- +- +- +- +- +- +- +- ++Definition at line 434 of file dwc_otg_cil_intr.c. ++ ++
    int32_t dwc_otg_handle_disconnect_intr (dwc_otg_core_if_t *  core_if  ) 
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ + +
    int32_t dwc_otg_handle_disconnect_intr ( dwc_otg_core_if_t *  core_if  ) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + This interrupt indicates that a device has been disconnected from the root port. +

    ++

    Todo:
    Consolidate this if statement.
    + +

    +-

    Todo:
    Consolidate this if statement.
    +- +-

    +-Definition at line 589 of file dwc_otg_cil_intr.c. +- +-

    +- +-

    +-
    +- +- +- +- +- +- +- +- ++Definition at line 933 of file dwc_otg_cil_intr.c. ++ ++
    int32_t dwc_otg_handle_usb_suspend_intr (dwc_otg_core_if_t *  core_if  ) 
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ + +
    int32_t dwc_otg_handle_usb_suspend_intr ( dwc_otg_core_if_t *  core_if  ) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + This interrupt indicates that SUSPEND state has been detected on the USB. +@@ -582,64 +406,78 @@ + For HNP the USB Suspend interrupt signals the change from "a_peripheral" to "a_host".

    + When power management is enabled the core will be put in low power mode. +

    +-Definition at line 649 of file dwc_otg_cil_intr.c. +- +-

    +- +-

    +-
    +- +- +- +- +- +- +- +- ++Definition at line 1015 of file dwc_otg_cil_intr.c. ++ ++
    static uint32_t dwc_otg_read_common_intr (dwc_otg_core_if_t *  core_if  )  [inline, static]
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ + +
    uint32_t dwc_otg_read_common_intr ( dwc_otg_core_if_t *  core_if  )  [inline, static]
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + This function returns the Core Interrupt register. +

    ++

    Todo:
    : The port interrupt occurs while in device mode. Added code to CIL to clear the interrupt for now!
    + +

    +-

    Todo:
    : The port interrupt occurs while in device mode. Added code to CIL to clear the interrupt for now!
    +- +-

    +-Definition at line 752 of file dwc_otg_cil_intr.c. +- +-

    +- +-

    +-
    +- +- +- +- +- +- +- +- ++Definition at line 1211 of file dwc_otg_cil_intr.c. ++ ++
    int32_t dwc_otg_handle_common_intr (dwc_otg_core_if_t *  core_if  ) 
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ + +
    int32_t dwc_otg_handle_common_intr ( void *  dev  ) 
    +- +-
    ++
    ++ ++ ++ ++ ++ ++
    ++   ++ + +

    + This function should be called on every hardware interrupt. +

    + The common interrupts are those that occur in both Host and Device mode. This handler handles the following interrupts:

      +-
    • Mode Mismatch Interrupt
    • Disconnect Interrupt
    • OTG Interrupt
    • Connector ID Status Change Interrupt
    • Session Request Interrupt.
    • Resume / Remote Wakeup Detected Interrupt.
    • LPM Transaction Received Interrutp
    ++
  • Mode Mismatch Interrupt
  • Disconnect Interrupt
  • OTG Interrupt
  • Connector ID Status Change Interrupt
  • Session Request Interrupt.
  • Resume / Remote Wakeup Detected Interrupt.
  • LPM Transaction Received Interrupt
  • ADP Transaction Received Interrupt
    • + +

    +-Definition at line 800 of file dwc_otg_cil_intr.c. +- +-

    +-

    Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++Definition at line 1275 of file dwc_otg_cil_intr.c.
    ++

    Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
    ++doxygen 1.3.9.1 + + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__core__if_8h-source.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/dwc__otg__core__if_8h-source.html 2013-07-26 19:31:20.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__core__if_8h-source.html 2013-07-26 19:34:40.000000000 +0000 +@@ -2,364 +2,396 @@ + + DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_core_if.h Source File + +- + +- +-
    +-
    +-
    +-
    +-

    dwc_otg_core_if.h

    Go to the documentation of this file.
    00001 /* ==========================================================================
+-00002  * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_core_if.h $
+-00003  * $Revision: #4 $
+-00004  * $Date: 2008/12/18 $
+-00005  * $Change: 1155299 $
+-00006  *
+-00007  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
+-00008  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
+-00009  * otherwise expressly agreed to in writing between Synopsys and you.
+-00010  *
+-00011  * The Software IS NOT an item of Licensed Software or Licensed Product under
+-00012  * any End User Software License Agreement or Agreement for Licensed Product
+-00013  * with Synopsys or any supplement thereto. You are permitted to use and
+-00014  * redistribute this Software in source and binary forms, with or without
+-00015  * modification, provided that redistributions of source code must retain this
+-00016  * notice. You may not view, use, disclose, copy or distribute this file or
+-00017  * any information contained herein except pursuant to this license grant from
+-00018  * Synopsys. If you do not agree with this notice, including the disclaimer
+-00019  * below, then you are not authorized to use the Software.
+-00020  *
+-00021  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
+-00022  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+-00023  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+-00024  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
+-00025  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+-00026  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+-00027  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+-00028  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+-00029  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+-00030  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+-00031  * DAMAGE.
+-00032  * ========================================================================== */
+-00033 #if !defined(__DWC_CORE_IF_H__)
+-00034 #define __DWC_CORE_IF_H__
+-00035 
+-00036 #include "dwc_os.h"
+-00037 
+-00042 struct dwc_otg_core_if;
+-00043 typedef struct dwc_otg_core_if dwc_otg_core_if_t;
+-00044 
+-00046 #define MAX_PERIO_FIFOS 15
+-00047 
+-00048 #define MAX_TX_FIFOS 15
+-00049 
+-00051 #define MAX_EPS_CHANNELS 16
+-00052 
+-00053 extern dwc_otg_core_if_t *dwc_otg_cil_init(const uint32_t * _reg_base_addr);
+-00054 extern void dwc_otg_core_init(dwc_otg_core_if_t * _core_if);
+-00055 extern void dwc_otg_cil_remove(dwc_otg_core_if_t * _core_if);
+-00056 
+-00057 extern void dwc_otg_enable_global_interrupts(dwc_otg_core_if_t * _core_if);
+-00058 extern void dwc_otg_disable_global_interrupts(dwc_otg_core_if_t * _core_if);
+-00059 
+-00060 extern uint8_t dwc_otg_is_device_mode(dwc_otg_core_if_t * _core_if);
+-00061 extern uint8_t dwc_otg_is_host_mode(dwc_otg_core_if_t * _core_if);
+-00062 
+-00063 extern uint8_t dwc_otg_is_dma_enable(dwc_otg_core_if_t * core_if);
+-00064 
+-00066 extern int32_t dwc_otg_handle_common_intr(dwc_otg_core_if_t * _core_if);
+-00067 
+-00078 extern int dwc_otg_set_param_otg_cap(dwc_otg_core_if_t * core_if, int32_t val);
+-00079 extern int32_t dwc_otg_get_param_otg_cap(dwc_otg_core_if_t * core_if);
+-00080 #define DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE 0
+-00081 #define DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE 1
+-00082 #define DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE 2
+-00083 #define dwc_param_otg_cap_default DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE
+-00084 
+-00085 extern int dwc_otg_set_param_opt(dwc_otg_core_if_t * core_if, int32_t val);
+-00086 extern int32_t dwc_otg_get_param_opt(dwc_otg_core_if_t * core_if);
+-00087 #define dwc_param_opt_default 1
+-00088 
+-00096 extern int dwc_otg_set_param_dma_enable(dwc_otg_core_if_t * core_if,
+-00097                                         int32_t val);
+-00098 extern int32_t dwc_otg_get_param_dma_enable(dwc_otg_core_if_t * core_if);
+-00099 #define dwc_param_dma_enable_default 1
+-00100 
+-00109 extern int dwc_otg_set_param_dma_desc_enable(dwc_otg_core_if_t * core_if,
+-00110                                              int32_t val);
+-00111 extern int32_t dwc_otg_get_param_dma_desc_enable(dwc_otg_core_if_t * core_if);
+-00112 #define dwc_param_dma_desc_enable_default 1
+-00113 
+-00117 extern int dwc_otg_set_param_dma_burst_size(dwc_otg_core_if_t * core_if,
+-00118                                             int32_t val);
+-00119 extern int32_t dwc_otg_get_param_dma_burst_size(dwc_otg_core_if_t * core_if);
+-00120 #define dwc_param_dma_burst_size_default 32
+-00121 
+-00130 extern int dwc_otg_set_param_speed(dwc_otg_core_if_t * core_if, int32_t val);
+-00131 extern int32_t dwc_otg_get_param_speed(dwc_otg_core_if_t * core_if);
+-00132 #define dwc_param_speed_default 0
+-00133 #define DWC_SPEED_PARAM_HIGH 0
+-00134 #define DWC_SPEED_PARAM_FULL 1
+-00135 
+-00141 extern int dwc_otg_set_param_host_support_fs_ls_low_power(dwc_otg_core_if_t *
+-00142                                                           core_if, int32_t val);
+-00143 extern int32_t dwc_otg_get_param_host_support_fs_ls_low_power(dwc_otg_core_if_t
+-00144                                                               * core_if);
+-00145 #define dwc_param_host_support_fs_ls_low_power_default 0
+-00146 
+-00155 extern int dwc_otg_set_param_host_ls_low_power_phy_clk(dwc_otg_core_if_t *
+-00156                                                        core_if, int32_t val);
+-00157 extern int32_t dwc_otg_get_param_host_ls_low_power_phy_clk(dwc_otg_core_if_t *
+-00158                                                            core_if);
+-00159 #define dwc_param_host_ls_low_power_phy_clk_default 0
+-00160 #define DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ 0
+-00161 #define DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ 1
+-00162 
+-00167 extern int dwc_otg_set_param_enable_dynamic_fifo(dwc_otg_core_if_t * core_if,
+-00168                                                  int32_t val);
+-00169 extern int32_t dwc_otg_get_param_enable_dynamic_fifo(dwc_otg_core_if_t *
+-00170                                                      core_if);
+-00171 #define dwc_param_enable_dynamic_fifo_default 1
+-00172 
+-00179 extern int dwc_otg_set_param_data_fifo_size(dwc_otg_core_if_t * core_if,
+-00180                                             int32_t val);
+-00181 extern int32_t dwc_otg_get_param_data_fifo_size(dwc_otg_core_if_t * core_if);
+-00182 #define dwc_param_data_fifo_size_default 8192
+-00183 
+-00188 extern int dwc_otg_set_param_dev_rx_fifo_size(dwc_otg_core_if_t * core_if,
+-00189                                               int32_t val);
+-00190 extern int32_t dwc_otg_get_param_dev_rx_fifo_size(dwc_otg_core_if_t * core_if);
+-00191 #define dwc_param_dev_rx_fifo_size_default 1064
+-00192 
+-00197 extern int dwc_otg_set_param_dev_nperio_tx_fifo_size(dwc_otg_core_if_t *
+-00198                                                      core_if, int32_t val);
+-00199 extern int32_t dwc_otg_get_param_dev_nperio_tx_fifo_size(dwc_otg_core_if_t *
+-00200                                                          core_if);
+-00201 #define dwc_param_dev_nperio_tx_fifo_size_default 1024
+-00202 
+-00207 extern int dwc_otg_set_param_dev_perio_tx_fifo_size(dwc_otg_core_if_t * core_if,
+-00208                                                     int32_t val, int fifo_num);
+-00209 extern int32_t dwc_otg_get_param_dev_perio_tx_fifo_size(dwc_otg_core_if_t *
+-00210                                                         core_if, int fifo_num);
+-00211 #define dwc_param_dev_perio_tx_fifo_size_default 256
+-00212 
+-00217 extern int dwc_otg_set_param_host_rx_fifo_size(dwc_otg_core_if_t * core_if,
+-00218                                                int32_t val);
+-00219 extern int32_t dwc_otg_get_param_host_rx_fifo_size(dwc_otg_core_if_t * core_if);
+-00220 #define dwc_param_host_rx_fifo_size_default 1024
+-00221 
+-00226 extern int dwc_otg_set_param_host_nperio_tx_fifo_size(dwc_otg_core_if_t *
+-00227                                                       core_if, int32_t val);
+-00228 extern int32_t dwc_otg_get_param_host_nperio_tx_fifo_size(dwc_otg_core_if_t *
+-00229                                                           core_if);
+-00230 #define dwc_param_host_nperio_tx_fifo_size_default 1024
+-00231 
+-00236 extern int dwc_otg_set_param_host_perio_tx_fifo_size(dwc_otg_core_if_t *
+-00237                                                      core_if, int32_t val);
+-00238 extern int32_t dwc_otg_get_param_host_perio_tx_fifo_size(dwc_otg_core_if_t *
+-00239                                                          core_if);
+-00240 #define dwc_param_host_perio_tx_fifo_size_default 1024
+-00241 
+-00245 extern int dwc_otg_set_param_max_transfer_size(dwc_otg_core_if_t * core_if,
+-00246                                                int32_t val);
+-00247 extern int32_t dwc_otg_get_param_max_transfer_size(dwc_otg_core_if_t * core_if);
+-00248 #define dwc_param_max_transfer_size_default 65535
+-00249 
+-00253 extern int dwc_otg_set_param_max_packet_count(dwc_otg_core_if_t * core_if,
+-00254                                               int32_t val);
+-00255 extern int32_t dwc_otg_get_param_max_packet_count(dwc_otg_core_if_t * core_if);
+-00256 #define dwc_param_max_packet_count_default 511
+-00257 
+-00262 extern int dwc_otg_set_param_host_channels(dwc_otg_core_if_t * core_if,
+-00263                                            int32_t val);
+-00264 extern int32_t dwc_otg_get_param_host_channels(dwc_otg_core_if_t * core_if);
+-00265 #define dwc_param_host_channels_default 12
+-00266 
+-00273 extern int dwc_otg_set_param_dev_endpoints(dwc_otg_core_if_t * core_if,
+-00274                                            int32_t val);
+-00275 extern int32_t dwc_otg_get_param_dev_endpoints(dwc_otg_core_if_t * core_if);
+-00276 #define dwc_param_dev_endpoints_default 6
+-00277 
+-00286 extern int dwc_otg_set_param_phy_type(dwc_otg_core_if_t * core_if, int32_t val);
+-00287 extern int32_t dwc_otg_get_param_phy_type(dwc_otg_core_if_t * core_if);
+-00288 #define DWC_PHY_TYPE_PARAM_FS 0
+-00289 #define DWC_PHY_TYPE_PARAM_UTMI 1
+-00290 #define DWC_PHY_TYPE_PARAM_ULPI 2
+-00291 #define dwc_param_phy_type_default DWC_PHY_TYPE_PARAM_UTMI
+-00292 
+-00304 extern int dwc_otg_set_param_phy_utmi_width(dwc_otg_core_if_t * core_if,
+-00305                                             int32_t val);
+-00306 extern int32_t dwc_otg_get_param_phy_utmi_width(dwc_otg_core_if_t * core_if);
+-00307 #define dwc_param_phy_utmi_width_default 16
+-00308 
+-00319 extern int dwc_otg_set_param_phy_ulpi_ddr(dwc_otg_core_if_t * core_if,
+-00320                                           int32_t val);
+-00321 extern int32_t dwc_otg_get_param_phy_ulpi_ddr(dwc_otg_core_if_t * core_if);
+-00322 #define dwc_param_phy_ulpi_ddr_default 0
+-00323 
+-00328 extern int dwc_otg_set_param_phy_ulpi_ext_vbus(dwc_otg_core_if_t * core_if,
+-00329                                                int32_t val);
+-00330 extern int32_t dwc_otg_get_param_phy_ulpi_ext_vbus(dwc_otg_core_if_t * core_if);
+-00331 #define DWC_PHY_ULPI_INTERNAL_VBUS 0
+-00332 #define DWC_PHY_ULPI_EXTERNAL_VBUS 1
+-00333 #define dwc_param_phy_ulpi_ext_vbus_default DWC_PHY_ULPI_INTERNAL_VBUS
+-00334 
+-00341 extern int dwc_otg_set_param_i2c_enable(dwc_otg_core_if_t * core_if,
+-00342                                         int32_t val);
+-00343 extern int32_t dwc_otg_get_param_i2c_enable(dwc_otg_core_if_t * core_if);
+-00344 #define dwc_param_i2c_enable_default 0
+-00345 
+-00346 extern int dwc_otg_set_param_ulpi_fs_ls(dwc_otg_core_if_t * core_if,
+-00347                                         int32_t val);
+-00348 extern int32_t dwc_otg_get_param_ulpi_fs_ls(dwc_otg_core_if_t * core_if);
+-00349 #define dwc_param_ulpi_fs_ls_default 0
+-00350 
+-00351 extern int dwc_otg_set_param_ts_dline(dwc_otg_core_if_t * core_if, int32_t val);
+-00352 extern int32_t dwc_otg_get_param_ts_dline(dwc_otg_core_if_t * core_if);
+-00353 #define dwc_param_ts_dline_default 0
+-00354 
+-00361 extern int dwc_otg_set_param_en_multiple_tx_fifo(dwc_otg_core_if_t * core_if,
+-00362                                                  int32_t val);
+-00363 extern int32_t dwc_otg_get_param_en_multiple_tx_fifo(dwc_otg_core_if_t *
+-00364                                                      core_if);
+-00365 #define dwc_param_en_multiple_tx_fifo_default 1
+-00366 
+-00371 extern int dwc_otg_set_param_dev_tx_fifo_size(dwc_otg_core_if_t * core_if,
+-00372                                               int fifo_num, int32_t val);
+-00373 extern int32_t dwc_otg_get_param_dev_tx_fifo_size(dwc_otg_core_if_t * core_if,
+-00374                                                   int fifo_num);
+-00375 #define dwc_param_dev_tx_fifo_size_default 256
+-00376 
+-00382 extern int dwc_otg_set_param_thr_ctl(dwc_otg_core_if_t * core_if, int32_t val);
+-00383 extern int32_t dwc_otg_get_thr_ctl(dwc_otg_core_if_t * core_if, int fifo_num);
+-00384 #define dwc_param_thr_ctl_default 0
+-00385 
+-00389 extern int dwc_otg_set_param_tx_thr_length(dwc_otg_core_if_t * core_if,
+-00390                                            int32_t val);
+-00391 extern int32_t dwc_otg_get_tx_thr_length(dwc_otg_core_if_t * core_if);
+-00392 #define dwc_param_tx_thr_length_default 64
+-00393 
+-00397 extern int dwc_otg_set_param_rx_thr_length(dwc_otg_core_if_t * core_if,
+-00398                                            int32_t val);
+-00399 extern int32_t dwc_otg_get_rx_thr_length(dwc_otg_core_if_t * core_if);
+-00400 #define dwc_param_rx_thr_length_default 64
+-00401 
+-00405 extern int dwc_otg_set_param_lpm_enable(dwc_otg_core_if_t * core_if,
+-00406                                         int32_t val);
+-00407 extern int32_t dwc_otg_get_param_lpm_enable(dwc_otg_core_if_t * core_if);
+-00408 #define dwc_param_lpm_enable_default 1
+-00409 
+-00413 extern int dwc_otg_set_param_pti_enable(dwc_otg_core_if_t * core_if,
+-00414                                         int32_t val);
+-00415 extern int32_t dwc_otg_get_param_pti_enable(dwc_otg_core_if_t * core_if);
+-00416 #define dwc_param_pti_enable_default 0
+-00417 
+-00421 extern int dwc_otg_set_param_mpi_enable(dwc_otg_core_if_t * core_if,
+-00422                                         int32_t val);
+-00423 extern int32_t dwc_otg_get_param_mpi_enable(dwc_otg_core_if_t * core_if);
+-00424 #define dwc_param_mpi_enable_default 0
+-00425 
+-00429 extern int dwc_otg_set_param_ic_usb_cap(dwc_otg_core_if_t * core_if,
+-00430                                         int32_t val);
+-00431 extern int32_t dwc_otg_get_param_ic_usb_cap(dwc_otg_core_if_t * core_if);
+-00432 #define dwc_param_ic_usb_cap_default 0
+-00433 
+-00434 extern int dwc_otg_set_param_ahb_thr_ratio(dwc_otg_core_if_t * core_if, int32_t val);
+-00435 extern int32_t dwc_otg_get_param_ahb_thr_ratio(dwc_otg_core_if_t * core_if);
+-00436 #define dwc_param_ahb_thr_ratio_default 0
+-00437 
+-00445 extern void dwc_otg_dump_dev_registers(dwc_otg_core_if_t * _core_if);
+-00446 extern void dwc_otg_dump_spram(dwc_otg_core_if_t * _core_if);
+-00447 extern void dwc_otg_dump_host_registers(dwc_otg_core_if_t * _core_if);
+-00448 extern void dwc_otg_dump_global_registers(dwc_otg_core_if_t * _core_if);
+-00449 
+-00453 extern uint32_t dwc_otg_get_hnpstatus(dwc_otg_core_if_t * core_if);
+-00454 
+-00458 extern uint32_t dwc_otg_get_srpstatus(dwc_otg_core_if_t * core_if);
+-00459 
+-00463 extern void dwc_otg_set_hnpreq(dwc_otg_core_if_t * core_if, uint32_t val);
+-00464 
+-00468 extern uint32_t dwc_otg_get_gsnpsid(dwc_otg_core_if_t * core_if);
+-00469 
+-00474 extern uint32_t dwc_otg_get_mode(dwc_otg_core_if_t * core_if);
+-00475 
+-00479 extern uint32_t dwc_otg_get_hnpcapable(dwc_otg_core_if_t * core_if);
+-00483 extern void dwc_otg_set_hnpcapable(dwc_otg_core_if_t * core_if, uint32_t val);
+-00484 
+-00488 extern uint32_t dwc_otg_get_srpcapable(dwc_otg_core_if_t * core_if);
+-00492 extern void dwc_otg_set_srpcapable(dwc_otg_core_if_t * core_if, uint32_t val);
+-00493 
+-00497 extern uint32_t dwc_otg_get_devspeed(dwc_otg_core_if_t * core_if);
+-00501 extern void dwc_otg_set_devspeed(dwc_otg_core_if_t * core_if, uint32_t val);
+-00502 
+-00506 extern uint32_t dwc_otg_get_busconnected(dwc_otg_core_if_t * core_if);
+-00507 
+-00511 extern uint32_t dwc_otg_get_enumspeed(dwc_otg_core_if_t * core_if);
+-00512 
+-00516 extern uint32_t dwc_otg_get_prtpower(dwc_otg_core_if_t * core_if);
+-00520 extern void dwc_otg_set_prtpower(dwc_otg_core_if_t * core_if, uint32_t val);
+-00521 
+-00525 extern uint32_t dwc_otg_get_prtsuspend(dwc_otg_core_if_t * core_if);
+-00529 extern void dwc_otg_set_prtsuspend(dwc_otg_core_if_t * core_if, uint32_t val);
+-00530 
+-00535 extern void dwc_otg_set_prtresume(dwc_otg_core_if_t * core_if, uint32_t val);
+-00536 
+-00540 extern uint32_t dwc_otg_get_remotewakesig(dwc_otg_core_if_t * core_if);
+-00541 
+-00545 extern uint32_t dwc_otg_get_lpm_portsleepstatus(dwc_otg_core_if_t * core_if);
+-00546 
+-00550 extern uint32_t dwc_otg_get_lpm_remotewakeenabled(dwc_otg_core_if_t * core_if);
+-00551 
+-00555 extern uint32_t dwc_otg_get_lpmresponse(dwc_otg_core_if_t * core_if);
+-00559 extern void dwc_otg_set_lpmresponse(dwc_otg_core_if_t * core_if, uint32_t val);
+-00560 
+-00564 extern uint32_t dwc_otg_get_hsic_connect(dwc_otg_core_if_t * core_if);
+-00568 extern void dwc_otg_set_hsic_connect(dwc_otg_core_if_t * core_if, uint32_t val);
+-00569 
+-00573 extern uint32_t dwc_otg_get_inv_sel_hsic(dwc_otg_core_if_t * core_if);
+-00577 extern void dwc_otg_set_inv_sel_hsic(dwc_otg_core_if_t * core_if, uint32_t val);
+-00578 
+-00579 /*
+-00580  * Some functions for accessing registers
+-00581  */
+-00582 
+-00586 extern uint32_t dwc_otg_get_gotgctl(dwc_otg_core_if_t * core_if);
+-00587 extern void dwc_otg_set_gotgctl(dwc_otg_core_if_t * core_if, uint32_t val);
+-00588 
+-00592 extern uint32_t dwc_otg_get_gusbcfg(dwc_otg_core_if_t * core_if);
+-00593 extern void dwc_otg_set_gusbcfg(dwc_otg_core_if_t * core_if, uint32_t val);
+-00594 
+-00598 extern uint32_t dwc_otg_get_grxfsiz(dwc_otg_core_if_t * core_if);
+-00599 extern void dwc_otg_set_grxfsiz(dwc_otg_core_if_t * core_if, uint32_t val);
+-00600 
+-00604 extern uint32_t dwc_otg_get_gnptxfsiz(dwc_otg_core_if_t * core_if);
+-00605 extern void dwc_otg_set_gnptxfsiz(dwc_otg_core_if_t * core_if, uint32_t val);
+-00606 
+-00607 extern uint32_t dwc_otg_get_gpvndctl(dwc_otg_core_if_t * core_if);
+-00608 extern void dwc_otg_set_gpvndctl(dwc_otg_core_if_t * core_if, uint32_t val);
+-00609 
+-00613 extern uint32_t dwc_otg_get_ggpio(dwc_otg_core_if_t * core_if);
+-00614 extern void dwc_otg_set_ggpio(dwc_otg_core_if_t * core_if, uint32_t val);
+-00615 
+-00619 extern uint32_t dwc_otg_get_guid(dwc_otg_core_if_t * core_if);
+-00620 extern void dwc_otg_set_guid(dwc_otg_core_if_t * core_if, uint32_t val);
+-00621 
+-00625 extern uint32_t dwc_otg_get_hprt0(dwc_otg_core_if_t * core_if);
+-00626 extern void dwc_otg_set_hprt0(dwc_otg_core_if_t * core_if, uint32_t val);
+-00627 
+-00631 extern uint32_t dwc_otg_get_hptxfsiz(dwc_otg_core_if_t * core_if);
+-00632 
+-00635 #endif                          /* __DWC_CORE_IF_H__ */
+-
    Generated on Tue May 5 02:22:48 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++
    Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
    ++

    dwc_otg_core_if.h

    Go to the documentation of this file.
    00001 /* ==========================================================================
++00002  * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_core_if.h $
++00003  * $Revision: #12 $
++00004  * $Date: 2011/10/24 $
++00005  * $Change: 1871159 $
++00006  *
++00007  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
++00008  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
++00009  * otherwise expressly agreed to in writing between Synopsys and you.
++00010  *
++00011  * The Software IS NOT an item of Licensed Software or Licensed Product under
++00012  * any End User Software License Agreement or Agreement for Licensed Product
++00013  * with Synopsys or any supplement thereto. You are permitted to use and
++00014  * redistribute this Software in source and binary forms, with or without
++00015  * modification, provided that redistributions of source code must retain this
++00016  * notice. You may not view, use, disclose, copy or distribute this file or
++00017  * any information contained herein except pursuant to this license grant from
++00018  * Synopsys. If you do not agree with this notice, including the disclaimer
++00019  * below, then you are not authorized to use the Software.
++00020  *
++00021  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
++00022  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++00023  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++00024  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
++00025  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++00026  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
++00027  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
++00028  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
++00029  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
++00030  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
++00031  * DAMAGE.
++00032  * ========================================================================== */
++00033 #if !defined(__DWC_CORE_IF_H__)
++00034 #define __DWC_CORE_IF_H__
++00035 
++00036 #include "dwc_os.h"
++00037 
++00042 struct dwc_otg_core_if;
++00043 typedef struct dwc_otg_core_if dwc_otg_core_if_t;
++00044 
++00046 #define MAX_PERIO_FIFOS 15
++00047 
++00048 #define MAX_TX_FIFOS 15
++00049 
++00051 #define MAX_EPS_CHANNELS 16
++00052 
++00053 extern dwc_otg_core_if_t *dwc_otg_cil_init(const uint32_t * _reg_base_addr);
++00054 extern void dwc_otg_core_init(dwc_otg_core_if_t * _core_if);
++00055 extern void dwc_otg_cil_remove(dwc_otg_core_if_t * _core_if);
++00056 
++00057 extern void dwc_otg_enable_global_interrupts(dwc_otg_core_if_t * _core_if);
++00058 extern void dwc_otg_disable_global_interrupts(dwc_otg_core_if_t * _core_if);
++00059 
++00060 extern uint8_t dwc_otg_is_device_mode(dwc_otg_core_if_t * _core_if);
++00061 extern uint8_t dwc_otg_is_host_mode(dwc_otg_core_if_t * _core_if);
++00062 
++00063 extern uint8_t dwc_otg_is_dma_enable(dwc_otg_core_if_t * core_if);
++00064 
++00066 extern int32_t dwc_otg_handle_common_intr(void *otg_dev);
++00067 
++00078 extern int dwc_otg_set_param_otg_cap(dwc_otg_core_if_t * core_if, int32_t val);
++00079 extern int32_t dwc_otg_get_param_otg_cap(dwc_otg_core_if_t * core_if);
++00080 #define DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE 0
++00081 #define DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE 1
++00082 #define DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE 2
++00083 #define dwc_param_otg_cap_default DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE
++00084 
++00085 extern int dwc_otg_set_param_opt(dwc_otg_core_if_t * core_if, int32_t val);
++00086 extern int32_t dwc_otg_get_param_opt(dwc_otg_core_if_t * core_if);
++00087 #define dwc_param_opt_default 1
++00088 
++00096 extern int dwc_otg_set_param_dma_enable(dwc_otg_core_if_t * core_if,
++00097                                         int32_t val);
++00098 extern int32_t dwc_otg_get_param_dma_enable(dwc_otg_core_if_t * core_if);
++00099 #define dwc_param_dma_enable_default 1
++00100 
++00109 extern int dwc_otg_set_param_dma_desc_enable(dwc_otg_core_if_t * core_if,
++00110                                              int32_t val);
++00111 extern int32_t dwc_otg_get_param_dma_desc_enable(dwc_otg_core_if_t * core_if);
++00112 #define dwc_param_dma_desc_enable_default 1
++00113 
++00117 extern int dwc_otg_set_param_dma_burst_size(dwc_otg_core_if_t * core_if,
++00118                                             int32_t val);
++00119 extern int32_t dwc_otg_get_param_dma_burst_size(dwc_otg_core_if_t * core_if);
++00120 #define dwc_param_dma_burst_size_default 32
++00121 
++00130 extern int dwc_otg_set_param_speed(dwc_otg_core_if_t * core_if, int32_t val);
++00131 extern int32_t dwc_otg_get_param_speed(dwc_otg_core_if_t * core_if);
++00132 #define dwc_param_speed_default 0
++00133 #define DWC_SPEED_PARAM_HIGH 0
++00134 #define DWC_SPEED_PARAM_FULL 1
++00135 
++00141 extern int dwc_otg_set_param_host_support_fs_ls_low_power(dwc_otg_core_if_t *
++00142                                                           core_if, int32_t val);
++00143 extern int32_t dwc_otg_get_param_host_support_fs_ls_low_power(dwc_otg_core_if_t
++00144                                                               * core_if);
++00145 #define dwc_param_host_support_fs_ls_low_power_default 0
++00146 
++00155 extern int dwc_otg_set_param_host_ls_low_power_phy_clk(dwc_otg_core_if_t *
++00156                                                        core_if, int32_t val);
++00157 extern int32_t dwc_otg_get_param_host_ls_low_power_phy_clk(dwc_otg_core_if_t *
++00158                                                            core_if);
++00159 #define dwc_param_host_ls_low_power_phy_clk_default 0
++00160 #define DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ 0
++00161 #define DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ 1
++00162 
++00167 extern int dwc_otg_set_param_enable_dynamic_fifo(dwc_otg_core_if_t * core_if,
++00168                                                  int32_t val);
++00169 extern int32_t dwc_otg_get_param_enable_dynamic_fifo(dwc_otg_core_if_t *
++00170                                                      core_if);
++00171 #define dwc_param_enable_dynamic_fifo_default 1
++00172 
++00179 extern int dwc_otg_set_param_data_fifo_size(dwc_otg_core_if_t * core_if,
++00180                                             int32_t val);
++00181 extern int32_t dwc_otg_get_param_data_fifo_size(dwc_otg_core_if_t * core_if);
++00182 #define dwc_param_data_fifo_size_default 8192
++00183 
++00188 extern int dwc_otg_set_param_dev_rx_fifo_size(dwc_otg_core_if_t * core_if,
++00189                                               int32_t val);
++00190 extern int32_t dwc_otg_get_param_dev_rx_fifo_size(dwc_otg_core_if_t * core_if);
++00191 #define dwc_param_dev_rx_fifo_size_default 1064
++00192 
++00197 extern int dwc_otg_set_param_dev_nperio_tx_fifo_size(dwc_otg_core_if_t *
++00198                                                      core_if, int32_t val);
++00199 extern int32_t dwc_otg_get_param_dev_nperio_tx_fifo_size(dwc_otg_core_if_t *
++00200                                                          core_if);
++00201 #define dwc_param_dev_nperio_tx_fifo_size_default 1024
++00202 
++00207 extern int dwc_otg_set_param_dev_perio_tx_fifo_size(dwc_otg_core_if_t * core_if,
++00208                                                     int32_t val, int fifo_num);
++00209 extern int32_t dwc_otg_get_param_dev_perio_tx_fifo_size(dwc_otg_core_if_t *
++00210                                                         core_if, int fifo_num);
++00211 #define dwc_param_dev_perio_tx_fifo_size_default 256
++00212 
++00217 extern int dwc_otg_set_param_host_rx_fifo_size(dwc_otg_core_if_t * core_if,
++00218                                                int32_t val);
++00219 extern int32_t dwc_otg_get_param_host_rx_fifo_size(dwc_otg_core_if_t * core_if);
++00220 #define dwc_param_host_rx_fifo_size_default 1024
++00221 
++00226 extern int dwc_otg_set_param_host_nperio_tx_fifo_size(dwc_otg_core_if_t *
++00227                                                       core_if, int32_t val);
++00228 extern int32_t dwc_otg_get_param_host_nperio_tx_fifo_size(dwc_otg_core_if_t *
++00229                                                           core_if);
++00230 #define dwc_param_host_nperio_tx_fifo_size_default 1024
++00231 
++00236 extern int dwc_otg_set_param_host_perio_tx_fifo_size(dwc_otg_core_if_t *
++00237                                                      core_if, int32_t val);
++00238 extern int32_t dwc_otg_get_param_host_perio_tx_fifo_size(dwc_otg_core_if_t *
++00239                                                          core_if);
++00240 #define dwc_param_host_perio_tx_fifo_size_default 1024
++00241 
++00245 extern int dwc_otg_set_param_max_transfer_size(dwc_otg_core_if_t * core_if,
++00246                                                int32_t val);
++00247 extern int32_t dwc_otg_get_param_max_transfer_size(dwc_otg_core_if_t * core_if);
++00248 #define dwc_param_max_transfer_size_default 65535
++00249 
++00253 extern int dwc_otg_set_param_max_packet_count(dwc_otg_core_if_t * core_if,
++00254                                               int32_t val);
++00255 extern int32_t dwc_otg_get_param_max_packet_count(dwc_otg_core_if_t * core_if);
++00256 #define dwc_param_max_packet_count_default 511
++00257 
++00262 extern int dwc_otg_set_param_host_channels(dwc_otg_core_if_t * core_if,
++00263                                            int32_t val);
++00264 extern int32_t dwc_otg_get_param_host_channels(dwc_otg_core_if_t * core_if);
++00265 #define dwc_param_host_channels_default 12
++00266 
++00273 extern int dwc_otg_set_param_dev_endpoints(dwc_otg_core_if_t * core_if,
++00274                                            int32_t val);
++00275 extern int32_t dwc_otg_get_param_dev_endpoints(dwc_otg_core_if_t * core_if);
++00276 #define dwc_param_dev_endpoints_default 6
++00277 
++00286 extern int dwc_otg_set_param_phy_type(dwc_otg_core_if_t * core_if, int32_t val);
++00287 extern int32_t dwc_otg_get_param_phy_type(dwc_otg_core_if_t * core_if);
++00288 #define DWC_PHY_TYPE_PARAM_FS 0
++00289 #define DWC_PHY_TYPE_PARAM_UTMI 1
++00290 #define DWC_PHY_TYPE_PARAM_ULPI 2
++00291 #define dwc_param_phy_type_default DWC_PHY_TYPE_PARAM_UTMI
++00292 
++00304 extern int dwc_otg_set_param_phy_utmi_width(dwc_otg_core_if_t * core_if,
++00305                                             int32_t val);
++00306 extern int32_t dwc_otg_get_param_phy_utmi_width(dwc_otg_core_if_t * core_if);
++00307 #define dwc_param_phy_utmi_width_default 16
++00308 
++00319 extern int dwc_otg_set_param_phy_ulpi_ddr(dwc_otg_core_if_t * core_if,
++00320                                           int32_t val);
++00321 extern int32_t dwc_otg_get_param_phy_ulpi_ddr(dwc_otg_core_if_t * core_if);
++00322 #define dwc_param_phy_ulpi_ddr_default 0
++00323 
++00328 extern int dwc_otg_set_param_phy_ulpi_ext_vbus(dwc_otg_core_if_t * core_if,
++00329                                                int32_t val);
++00330 extern int32_t dwc_otg_get_param_phy_ulpi_ext_vbus(dwc_otg_core_if_t * core_if);
++00331 #define DWC_PHY_ULPI_INTERNAL_VBUS 0
++00332 #define DWC_PHY_ULPI_EXTERNAL_VBUS 1
++00333 #define dwc_param_phy_ulpi_ext_vbus_default DWC_PHY_ULPI_INTERNAL_VBUS
++00334 
++00341 extern int dwc_otg_set_param_i2c_enable(dwc_otg_core_if_t * core_if,
++00342                                         int32_t val);
++00343 extern int32_t dwc_otg_get_param_i2c_enable(dwc_otg_core_if_t * core_if);
++00344 #define dwc_param_i2c_enable_default 0
++00345 
++00346 extern int dwc_otg_set_param_ulpi_fs_ls(dwc_otg_core_if_t * core_if,
++00347                                         int32_t val);
++00348 extern int32_t dwc_otg_get_param_ulpi_fs_ls(dwc_otg_core_if_t * core_if);
++00349 #define dwc_param_ulpi_fs_ls_default 0
++00350 
++00351 extern int dwc_otg_set_param_ts_dline(dwc_otg_core_if_t * core_if, int32_t val);
++00352 extern int32_t dwc_otg_get_param_ts_dline(dwc_otg_core_if_t * core_if);
++00353 #define dwc_param_ts_dline_default 0
++00354 
++00361 extern int dwc_otg_set_param_en_multiple_tx_fifo(dwc_otg_core_if_t * core_if,
++00362                                                  int32_t val);
++00363 extern int32_t dwc_otg_get_param_en_multiple_tx_fifo(dwc_otg_core_if_t *
++00364                                                      core_if);
++00365 #define dwc_param_en_multiple_tx_fifo_default 1
++00366 
++00371 extern int dwc_otg_set_param_dev_tx_fifo_size(dwc_otg_core_if_t * core_if,
++00372                                               int fifo_num, int32_t val);
++00373 extern int32_t dwc_otg_get_param_dev_tx_fifo_size(dwc_otg_core_if_t * core_if,
++00374                                                   int fifo_num);
++00375 #define dwc_param_dev_tx_fifo_size_default 768
++00376 
++00382 extern int dwc_otg_set_param_thr_ctl(dwc_otg_core_if_t * core_if, int32_t val);
++00383 extern int32_t dwc_otg_get_thr_ctl(dwc_otg_core_if_t * core_if, int fifo_num);
++00384 #define dwc_param_thr_ctl_default 0
++00385 
++00389 extern int dwc_otg_set_param_tx_thr_length(dwc_otg_core_if_t * core_if,
++00390                                            int32_t val);
++00391 extern int32_t dwc_otg_get_tx_thr_length(dwc_otg_core_if_t * core_if);
++00392 #define dwc_param_tx_thr_length_default 64
++00393 
++00397 extern int dwc_otg_set_param_rx_thr_length(dwc_otg_core_if_t * core_if,
++00398                                            int32_t val);
++00399 extern int32_t dwc_otg_get_rx_thr_length(dwc_otg_core_if_t * core_if);
++00400 #define dwc_param_rx_thr_length_default 64
++00401 
++00405 extern int dwc_otg_set_param_lpm_enable(dwc_otg_core_if_t * core_if,
++00406                                         int32_t val);
++00407 extern int32_t dwc_otg_get_param_lpm_enable(dwc_otg_core_if_t * core_if);
++00408 #define dwc_param_lpm_enable_default 1
++00409 
++00413 extern int dwc_otg_set_param_pti_enable(dwc_otg_core_if_t * core_if,
++00414                                         int32_t val);
++00415 extern int32_t dwc_otg_get_param_pti_enable(dwc_otg_core_if_t * core_if);
++00416 #define dwc_param_pti_enable_default 0
++00417 
++00421 extern int dwc_otg_set_param_mpi_enable(dwc_otg_core_if_t * core_if,
++00422                                         int32_t val);
++00423 extern int32_t dwc_otg_get_param_mpi_enable(dwc_otg_core_if_t * core_if);
++00424 #define dwc_param_mpi_enable_default 0
++00425 
++00429 extern int dwc_otg_set_param_adp_enable(dwc_otg_core_if_t * core_if,
++00430                                         int32_t val);
++00431 extern int32_t dwc_otg_get_param_adp_enable(dwc_otg_core_if_t * core_if);
++00432 #define dwc_param_adp_enable_default 0
++00433 
++00438 extern int dwc_otg_set_param_ic_usb_cap(dwc_otg_core_if_t * core_if,
++00439                                         int32_t val);
++00440 extern int32_t dwc_otg_get_param_ic_usb_cap(dwc_otg_core_if_t * core_if);
++00441 #define dwc_param_ic_usb_cap_default 0
++00442 
++00443 extern int dwc_otg_set_param_ahb_thr_ratio(dwc_otg_core_if_t * core_if,
++00444                                            int32_t val);
++00445 extern int32_t dwc_otg_get_param_ahb_thr_ratio(dwc_otg_core_if_t * core_if);
++00446 #define dwc_param_ahb_thr_ratio_default 0
++00447 
++00448 extern int dwc_otg_set_param_power_down(dwc_otg_core_if_t * core_if,
++00449                                         int32_t val);
++00450 extern int32_t dwc_otg_get_param_power_down(dwc_otg_core_if_t * core_if);
++00451 #define dwc_param_power_down_default 0
++00452 
++00453 extern int dwc_otg_set_param_reload_ctl(dwc_otg_core_if_t * core_if,
++00454                                         int32_t val);
++00455 extern int32_t dwc_otg_get_param_reload_ctl(dwc_otg_core_if_t * core_if);
++00456 #define dwc_param_reload_ctl_default 0
++00457 
++00458 extern int dwc_otg_set_param_dev_out_nak(dwc_otg_core_if_t * core_if,
++00459                                                                                 int32_t val);
++00460 extern int32_t dwc_otg_get_param_dev_out_nak(dwc_otg_core_if_t * core_if);
++00461 #define dwc_param_dev_out_nak_default 0
++00462 
++00463 extern int dwc_otg_set_param_cont_on_bna(dwc_otg_core_if_t * core_if,
++00464                                                                                  int32_t val);
++00465 extern int32_t dwc_otg_get_param_cont_on_bna(dwc_otg_core_if_t * core_if);
++00466 #define dwc_param_cont_on_bna_default 0
++00467 
++00468 extern int dwc_otg_set_param_ahb_single(dwc_otg_core_if_t * core_if,
++00469                                                                                  int32_t val);
++00470 extern int32_t dwc_otg_get_param_ahb_single(dwc_otg_core_if_t * core_if);
++00471 #define dwc_param_ahb_single_default 0
++00472 
++00473 extern int dwc_otg_set_param_otg_ver(dwc_otg_core_if_t * core_if, int32_t val);
++00474 extern int32_t dwc_otg_get_param_otg_ver(dwc_otg_core_if_t * core_if);
++00475 #define dwc_param_otg_ver_default 0
++00476 
++00484 extern void dwc_otg_dump_dev_registers(dwc_otg_core_if_t * _core_if);
++00485 extern void dwc_otg_dump_spram(dwc_otg_core_if_t * _core_if);
++00486 extern void dwc_otg_dump_host_registers(dwc_otg_core_if_t * _core_if);
++00487 extern void dwc_otg_dump_global_registers(dwc_otg_core_if_t * _core_if);
++00488 
++00492 extern uint32_t dwc_otg_get_hnpstatus(dwc_otg_core_if_t * core_if);
++00493 
++00497 extern uint32_t dwc_otg_get_srpstatus(dwc_otg_core_if_t * core_if);
++00498 
++00502 extern void dwc_otg_set_hnpreq(dwc_otg_core_if_t * core_if, uint32_t val);
++00503 
++00507 extern uint32_t dwc_otg_get_gsnpsid(dwc_otg_core_if_t * core_if);
++00508 
++00513 extern uint32_t dwc_otg_get_mode(dwc_otg_core_if_t * core_if);
++00514 
++00518 extern uint32_t dwc_otg_get_hnpcapable(dwc_otg_core_if_t * core_if);
++00522 extern void dwc_otg_set_hnpcapable(dwc_otg_core_if_t * core_if, uint32_t val);
++00523 
++00527 extern uint32_t dwc_otg_get_srpcapable(dwc_otg_core_if_t * core_if);
++00531 extern void dwc_otg_set_srpcapable(dwc_otg_core_if_t * core_if, uint32_t val);
++00532 
++00536 extern uint32_t dwc_otg_get_devspeed(dwc_otg_core_if_t * core_if);
++00540 extern void dwc_otg_set_devspeed(dwc_otg_core_if_t * core_if, uint32_t val);
++00541 
++00545 extern uint32_t dwc_otg_get_busconnected(dwc_otg_core_if_t * core_if);
++00546 
++00550 extern uint32_t dwc_otg_get_enumspeed(dwc_otg_core_if_t * core_if);
++00551 
++00555 extern uint32_t dwc_otg_get_prtpower(dwc_otg_core_if_t * core_if);
++00556 
++00560 extern uint32_t dwc_otg_get_core_state(dwc_otg_core_if_t * core_if);
++00561 
++00565 extern void dwc_otg_set_prtpower(dwc_otg_core_if_t * core_if, uint32_t val);
++00566 
++00570 extern uint32_t dwc_otg_get_prtsuspend(dwc_otg_core_if_t * core_if);
++00574 extern void dwc_otg_set_prtsuspend(dwc_otg_core_if_t * core_if, uint32_t val);
++00575 
++00579 extern uint32_t dwc_otg_get_mode_ch_tim(dwc_otg_core_if_t * core_if);
++00583 extern void dwc_otg_set_mode_ch_tim(dwc_otg_core_if_t * core_if, uint32_t val);
++00584 
++00588 extern uint32_t dwc_otg_get_fr_interval(dwc_otg_core_if_t * core_if);
++00592 extern void dwc_otg_set_fr_interval(dwc_otg_core_if_t * core_if, uint32_t val);
++00593 
++00598 extern void dwc_otg_set_prtresume(dwc_otg_core_if_t * core_if, uint32_t val);
++00599 
++00603 extern uint32_t dwc_otg_get_remotewakesig(dwc_otg_core_if_t * core_if);
++00604 
++00608 extern uint32_t dwc_otg_get_lpm_portsleepstatus(dwc_otg_core_if_t * core_if);
++00609 
++00613 extern uint32_t dwc_otg_get_lpm_remotewakeenabled(dwc_otg_core_if_t * core_if);
++00614 
++00618 extern uint32_t dwc_otg_get_lpmresponse(dwc_otg_core_if_t * core_if);
++00622 extern void dwc_otg_set_lpmresponse(dwc_otg_core_if_t * core_if, uint32_t val);
++00623 
++00627 extern uint32_t dwc_otg_get_hsic_connect(dwc_otg_core_if_t * core_if);
++00631 extern void dwc_otg_set_hsic_connect(dwc_otg_core_if_t * core_if, uint32_t val);
++00632 
++00636 extern uint32_t dwc_otg_get_inv_sel_hsic(dwc_otg_core_if_t * core_if);
++00640 extern void dwc_otg_set_inv_sel_hsic(dwc_otg_core_if_t * core_if, uint32_t val);
++00641 
++00642 /*
++00643  * Some functions for accessing registers
++00644  */
++00645 
++00649 extern uint32_t dwc_otg_get_gotgctl(dwc_otg_core_if_t * core_if);
++00650 extern void dwc_otg_set_gotgctl(dwc_otg_core_if_t * core_if, uint32_t val);
++00651 
++00655 extern uint32_t dwc_otg_get_gusbcfg(dwc_otg_core_if_t * core_if);
++00656 extern void dwc_otg_set_gusbcfg(dwc_otg_core_if_t * core_if, uint32_t val);
++00657 
++00661 extern uint32_t dwc_otg_get_grxfsiz(dwc_otg_core_if_t * core_if);
++00662 extern void dwc_otg_set_grxfsiz(dwc_otg_core_if_t * core_if, uint32_t val);
++00663 
++00667 extern uint32_t dwc_otg_get_gnptxfsiz(dwc_otg_core_if_t * core_if);
++00668 extern void dwc_otg_set_gnptxfsiz(dwc_otg_core_if_t * core_if, uint32_t val);
++00669 
++00670 extern uint32_t dwc_otg_get_gpvndctl(dwc_otg_core_if_t * core_if);
++00671 extern void dwc_otg_set_gpvndctl(dwc_otg_core_if_t * core_if, uint32_t val);
++00672 
++00676 extern uint32_t dwc_otg_get_ggpio(dwc_otg_core_if_t * core_if);
++00677 extern void dwc_otg_set_ggpio(dwc_otg_core_if_t * core_if, uint32_t val);
++00678 
++00682 extern uint32_t dwc_otg_get_guid(dwc_otg_core_if_t * core_if);
++00683 extern void dwc_otg_set_guid(dwc_otg_core_if_t * core_if, uint32_t val);
++00684 
++00688 extern uint32_t dwc_otg_get_hprt0(dwc_otg_core_if_t * core_if);
++00689 extern void dwc_otg_set_hprt0(dwc_otg_core_if_t * core_if, uint32_t val);
++00690 
++00694 extern uint32_t dwc_otg_get_hptxfsiz(dwc_otg_core_if_t * core_if);
++00695 
++00698 #endif                          /* __DWC_CORE_IF_H__ */
++
    Generated on Thu Oct 27 03:56:37 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
    ++doxygen 1.3.9.1
    + + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__core__if_8h.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/dwc__otg__core__if_8h.html 2013-07-26 19:31:20.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__core__if_8h.html 2013-07-26 19:34:40.000000000 +0000 +@@ -2,635 +2,707 @@ + + DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_core_if.h File Reference + +- + +- +-
    +-
    +-
    +-
    ++ ++
    Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
    +

    dwc_otg_core_if.h File Reference

    This file defines DWC_OTG Core API. More... +

    +-#include "dwc_os.h"
    ++#include "dwc_os.h"
    + +

    + Go to the source code of this file. + + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- +- ++ + +- ++ + +- ++ + +- ++ + +- +- ++ + +- ++ + +- +- ++ + +- ++ ++ + +- +- ++ + +- ++ + +- +- ++ + +- ++ ++ + +- +- ++ + +- ++ ++ + +- +- ++ + +- ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ + + +- ++ + +- ++ + +- +- ++ ++ + +- ++ + +- +- ++ ++ + +- ++ + +- +- ++ ++ + +- ++ + +- +- ++ ++ + +- ++ + +- +- ++ ++ + +- ++ + +- +- ++ ++ + +- ++ + +- +- ++ ++ + +- ++ + +- +- ++ ++ + +- ++ + +- +- ++ ++ + +- ++ + +- +- ++ ++ + +- ++ + +- +- ++ ++ + +- ++ + +- +- ++ ++ + +- ++ + +- +- ++ ++ + +- ++ + +- +- ++ ++ + +- ++ + + +- ++ + +- ++ + +- +- ++ ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + + +- ++ + +- ++ + +- +- ++ ++ + +- ++ + + +- + +- ++ + + +- + +- ++ + + +- + +- ++ + + +- ++ + +- ++ + + +- ++ + +- ++ + + +- ++ ++ ++ ++ ++ ++ + +- ++ + + +- ++ ++ ++ ++ ++ ++ ++ + +- ++ + +- ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ + + +- ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ + +- +- ++ ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ ++ ++ ++ + + +- ++ + + +- ++ + + +- ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ + +- ++ + + +- ++ + +- ++ + + +- ++ + +- ++ + + +- ++ + +- ++ + +- ++ + +- ++ + + +- ++ + +- ++ + + +- ++ + +- ++ + + +- ++ + +- ++ + + + +- ++ + +- ++ + + +- ++ + + +- ++ + + + +- ++ + + +- ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- ++ + +- ++ + +- ++ + +- ++ +

    OTG Core Parameters

    +-#define DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE   0
    ++#define DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE   0
    +-#define DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE   1
    ++#define DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE   1
    +-#define DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE   2
    ++#define DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE   2
    +-#define dwc_param_otg_cap_default   DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE
    ++#define dwc_param_otg_cap_default   DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE
    +-#define dwc_param_opt_default   1
    ++#define dwc_param_opt_default   1
    +-#define dwc_param_dma_enable_default   1
    ++#define dwc_param_dma_enable_default   1
    +-#define dwc_param_dma_desc_enable_default   1
    ++#define dwc_param_dma_desc_enable_default   1
    +-#define dwc_param_dma_burst_size_default   32
    ++#define dwc_param_dma_burst_size_default   32
    +-#define dwc_param_speed_default   0
    ++#define dwc_param_speed_default   0
    +-#define DWC_SPEED_PARAM_HIGH   0
    ++#define DWC_SPEED_PARAM_HIGH   0
    +-#define DWC_SPEED_PARAM_FULL   1
    ++#define DWC_SPEED_PARAM_FULL   1
    +-#define dwc_param_host_support_fs_ls_low_power_default   0
    ++#define dwc_param_host_support_fs_ls_low_power_default   0
    +-#define dwc_param_host_ls_low_power_phy_clk_default   0
    ++#define dwc_param_host_ls_low_power_phy_clk_default   0
    +-#define DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ   0
    ++#define DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ   0
    +-#define DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ   1
    ++#define DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ   1
    +-#define dwc_param_enable_dynamic_fifo_default   1
    ++#define dwc_param_enable_dynamic_fifo_default   1
    +-#define dwc_param_data_fifo_size_default   8192
    ++#define dwc_param_data_fifo_size_default   8192
    +-#define dwc_param_dev_rx_fifo_size_default   1064
    ++#define dwc_param_dev_rx_fifo_size_default   1064
    +-#define dwc_param_dev_nperio_tx_fifo_size_default   1024
    ++#define dwc_param_dev_nperio_tx_fifo_size_default   1024
    +-#define dwc_param_dev_perio_tx_fifo_size_default   256
    ++#define dwc_param_dev_perio_tx_fifo_size_default   256
    +-#define dwc_param_host_rx_fifo_size_default   1024
    ++#define dwc_param_host_rx_fifo_size_default   1024
    +-#define dwc_param_host_nperio_tx_fifo_size_default   1024
    ++#define dwc_param_host_nperio_tx_fifo_size_default   1024
    +-#define dwc_param_host_perio_tx_fifo_size_default   1024
    ++#define dwc_param_host_perio_tx_fifo_size_default   1024
    +-#define dwc_param_max_transfer_size_default   65535
    ++#define dwc_param_max_transfer_size_default   65535
    +-#define dwc_param_max_packet_count_default   511
    ++#define dwc_param_max_packet_count_default   511
    +-#define dwc_param_host_channels_default   12
    ++#define dwc_param_host_channels_default   12
    +-#define dwc_param_dev_endpoints_default   6
    ++#define dwc_param_dev_endpoints_default   6
    +-#define DWC_PHY_TYPE_PARAM_FS   0
    ++#define DWC_PHY_TYPE_PARAM_FS   0
    +-#define DWC_PHY_TYPE_PARAM_UTMI   1
    ++#define DWC_PHY_TYPE_PARAM_UTMI   1
    +-#define DWC_PHY_TYPE_PARAM_ULPI   2
    ++#define DWC_PHY_TYPE_PARAM_ULPI   2
    +-#define dwc_param_phy_type_default   DWC_PHY_TYPE_PARAM_UTMI
    ++#define dwc_param_phy_type_default   DWC_PHY_TYPE_PARAM_UTMI
    +-#define dwc_param_phy_utmi_width_default   16
    ++#define dwc_param_phy_utmi_width_default   16
    +-#define dwc_param_phy_ulpi_ddr_default   0
    ++#define dwc_param_phy_ulpi_ddr_default   0
    +-#define DWC_PHY_ULPI_INTERNAL_VBUS   0
    ++#define DWC_PHY_ULPI_INTERNAL_VBUS   0
    +-#define DWC_PHY_ULPI_EXTERNAL_VBUS   1
    ++#define DWC_PHY_ULPI_EXTERNAL_VBUS   1
    +-#define dwc_param_phy_ulpi_ext_vbus_default   DWC_PHY_ULPI_INTERNAL_VBUS
    ++#define dwc_param_phy_ulpi_ext_vbus_default   DWC_PHY_ULPI_INTERNAL_VBUS
    +-#define dwc_param_i2c_enable_default   0
    ++#define dwc_param_i2c_enable_default   0
    +-#define dwc_param_ulpi_fs_ls_default   0
    ++#define dwc_param_ulpi_fs_ls_default   0
    +-#define dwc_param_ts_dline_default   0
    ++#define dwc_param_ts_dline_default   0
    +-#define dwc_param_en_multiple_tx_fifo_default   1
    ++#define dwc_param_en_multiple_tx_fifo_default   1
    +-#define dwc_param_dev_tx_fifo_size_default   256
    ++#define dwc_param_dev_tx_fifo_size_default   768
    +-#define dwc_param_thr_ctl_default   0
    ++#define dwc_param_thr_ctl_default   0
    +-#define dwc_param_tx_thr_length_default   64
    ++#define dwc_param_tx_thr_length_default   64
    +-#define dwc_param_rx_thr_length_default   64
    ++#define dwc_param_rx_thr_length_default   64
    +-#define dwc_param_lpm_enable_default   1
    ++#define dwc_param_lpm_enable_default   1
    +-#define dwc_param_pti_enable_default   0
    ++#define dwc_param_pti_enable_default   0
    +-#define dwc_param_mpi_enable_default   0
    ++#define dwc_param_mpi_enable_default   0
    +-#define dwc_param_ic_usb_cap_default   0
    ++#define dwc_param_adp_enable_default   0
    +-#define dwc_param_ahb_thr_ratio_default   0
    ++#define dwc_param_ic_usb_cap_default   0
    int dwc_otg_set_param_otg_cap (dwc_otg_core_if_t *core_if, int32_t val)
    ++#define dwc_param_ahb_thr_ratio_default   0
     Specifies the OTG capabilities.
    +-int32_t dwc_otg_get_param_otg_cap (dwc_otg_core_if_t *core_if)
    ++#define dwc_param_power_down_default   0
    +-int dwc_otg_set_param_opt (dwc_otg_core_if_t *core_if, int32_t val)
    ++#define dwc_param_reload_ctl_default   0
    +-int32_t dwc_otg_get_param_opt (dwc_otg_core_if_t *core_if)
    ++#define dwc_param_dev_out_nak_default   0
    int dwc_otg_set_param_dma_enable (dwc_otg_core_if_t *core_if, int32_t val)
    ++#define dwc_param_cont_on_bna_default   0
     Specifies whether to use slave or DMA mode for accessing the data FIFOs.
    +-int32_t dwc_otg_get_param_dma_enable (dwc_otg_core_if_t *core_if)
    ++#define dwc_param_ahb_single_default   0
    int dwc_otg_set_param_dma_desc_enable (dwc_otg_core_if_t *core_if, int32_t val)
    ++#define dwc_param_otg_ver_default   0
     When DMA mode is enabled specifies whether to use address DMA or DMA Descritor mode for accessing the data FIFOs in device mode.
    +-int32_t dwc_otg_get_param_dma_desc_enable (dwc_otg_core_if_t *core_if)
    int dwc_otg_set_param_otg_cap (dwc_otg_core_if_t *core_if, int32_t val)
    int dwc_otg_set_param_dma_burst_size (dwc_otg_core_if_t *core_if, int32_t val)
     Specifies the OTG capabilities.
    ++int32_t dwc_otg_get_param_otg_cap (dwc_otg_core_if_t *core_if)
     The DMA Burst size (applicable only for External DMA Mode).
    +-int32_t dwc_otg_get_param_dma_burst_size (dwc_otg_core_if_t *core_if)
    ++int dwc_otg_set_param_opt (dwc_otg_core_if_t *core_if, int32_t val)
    int dwc_otg_set_param_speed (dwc_otg_core_if_t *core_if, int32_t val)
    ++int32_t dwc_otg_get_param_opt (dwc_otg_core_if_t *core_if)
     Specifies the maximum speed of operation in host and device mode.
    +-int32_t dwc_otg_get_param_speed (dwc_otg_core_if_t *core_if)
    int dwc_otg_set_param_dma_enable (dwc_otg_core_if_t *core_if, int32_t val)
    int dwc_otg_set_param_host_support_fs_ls_low_power (dwc_otg_core_if_t *core_if, int32_t val)
     Specifies whether to use slave or DMA mode for accessing the data FIFOs.
    ++int32_t dwc_otg_get_param_dma_enable (dwc_otg_core_if_t *core_if)
     Specifies whether low power mode is supported when attached to a Full Speed or Low Speed device in host mode.
    +-int32_t dwc_otg_get_param_host_support_fs_ls_low_power (dwc_otg_core_if_t *core_if)
    int dwc_otg_set_param_dma_desc_enable (dwc_otg_core_if_t *core_if, int32_t val)
    int dwc_otg_set_param_host_ls_low_power_phy_clk (dwc_otg_core_if_t *core_if, int32_t val)
     When DMA mode is enabled specifies whether to use address DMA or DMA Descritor mode for accessing the data FIFOs in device mode.
    ++int32_t dwc_otg_get_param_dma_desc_enable (dwc_otg_core_if_t *core_if)
     Specifies the PHY clock rate in low power mode when connected to a Low Speed device in host mode.
    +-int32_t dwc_otg_get_param_host_ls_low_power_phy_clk (dwc_otg_core_if_t *core_if)
    int dwc_otg_set_param_dma_burst_size (dwc_otg_core_if_t *core_if, int32_t val)
    +-int dwc_otg_set_param_enable_dynamic_fifo (dwc_otg_core_if_t *core_if, int32_t val)
     The DMA Burst size (applicable only for External DMA Mode).
    ++int32_t dwc_otg_get_param_dma_burst_size (dwc_otg_core_if_t *core_if)
    int dwc_otg_set_param_speed (dwc_otg_core_if_t *core_if, int32_t val)
     Specifies the maximum speed of operation in host and device mode.
    ++int32_t dwc_otg_get_param_speed (dwc_otg_core_if_t *core_if)
    int dwc_otg_set_param_host_support_fs_ls_low_power (dwc_otg_core_if_t *core_if, int32_t val)
     Specifies whether low power mode is supported when attached to a Full Speed or Low Speed device in host mode.
    ++int32_t dwc_otg_get_param_host_support_fs_ls_low_power (dwc_otg_core_if_t *core_if)
    int dwc_otg_set_param_host_ls_low_power_phy_clk (dwc_otg_core_if_t *core_if, int32_t val)
     Specifies the PHY clock rate in low power mode when connected to a Low Speed device in host mode.
    ++int32_t dwc_otg_get_param_host_ls_low_power_phy_clk (dwc_otg_core_if_t *core_if)
    ++int dwc_otg_set_param_enable_dynamic_fifo (dwc_otg_core_if_t *core_if, int32_t val)
     0 - Use cC FIFO size parameters 1 - Allow dynamic FIFO sizing (default)
    +-int32_t dwc_otg_get_param_enable_dynamic_fifo (dwc_otg_core_if_t *core_if)
    ++int32_t dwc_otg_get_param_enable_dynamic_fifo (dwc_otg_core_if_t *core_if)
    int dwc_otg_set_param_data_fifo_size (dwc_otg_core_if_t *core_if, int32_t val)
    int dwc_otg_set_param_data_fifo_size (dwc_otg_core_if_t *core_if, int32_t val)
     Total number of 4-byte words in the data FIFO memory.
    +-int32_t dwc_otg_get_param_data_fifo_size (dwc_otg_core_if_t *core_if)
     Total number of 4-byte words in the data FIFO memory.
    ++int32_t dwc_otg_get_param_data_fifo_size (dwc_otg_core_if_t *core_if)
    int dwc_otg_set_param_dev_rx_fifo_size (dwc_otg_core_if_t *core_if, int32_t val)
    int dwc_otg_set_param_dev_rx_fifo_size (dwc_otg_core_if_t *core_if, int32_t val)
     Number of 4-byte words in the Rx FIFO in device mode when dynamic FIFO sizing is enabled.
    +-int32_t dwc_otg_get_param_dev_rx_fifo_size (dwc_otg_core_if_t *core_if)
     Number of 4-byte words in the Rx FIFO in device mode when dynamic FIFO sizing is enabled.
    ++int32_t dwc_otg_get_param_dev_rx_fifo_size (dwc_otg_core_if_t *core_if)
    int dwc_otg_set_param_dev_nperio_tx_fifo_size (dwc_otg_core_if_t *core_if, int32_t val)
    int dwc_otg_set_param_dev_nperio_tx_fifo_size (dwc_otg_core_if_t *core_if, int32_t val)
     Number of 4-byte words in the non-periodic Tx FIFO in device mode when dynamic FIFO sizing is enabled.
    +-int32_t dwc_otg_get_param_dev_nperio_tx_fifo_size (dwc_otg_core_if_t *core_if)
     Number of 4-byte words in the non-periodic Tx FIFO in device mode when dynamic FIFO sizing is enabled.
    ++int32_t dwc_otg_get_param_dev_nperio_tx_fifo_size (dwc_otg_core_if_t *core_if)
    int dwc_otg_set_param_dev_perio_tx_fifo_size (dwc_otg_core_if_t *core_if, int32_t val, int fifo_num)
    int dwc_otg_set_param_dev_perio_tx_fifo_size (dwc_otg_core_if_t *core_if, int32_t val, int fifo_num)
     Number of 4-byte words in each of the periodic Tx FIFOs in device mode when dynamic FIFO sizing is enabled.
    +-int32_t dwc_otg_get_param_dev_perio_tx_fifo_size (dwc_otg_core_if_t *core_if, int fifo_num)
     Number of 4-byte words in each of the periodic Tx FIFOs in device mode when dynamic FIFO sizing is enabled.
    ++int32_t dwc_otg_get_param_dev_perio_tx_fifo_size (dwc_otg_core_if_t *core_if, int fifo_num)
    int dwc_otg_set_param_host_rx_fifo_size (dwc_otg_core_if_t *core_if, int32_t val)
    int dwc_otg_set_param_host_rx_fifo_size (dwc_otg_core_if_t *core_if, int32_t val)
     Number of 4-byte words in the Rx FIFO in host mode when dynamic FIFO sizing is enabled.
    +-int32_t dwc_otg_get_param_host_rx_fifo_size (dwc_otg_core_if_t *core_if)
     Number of 4-byte words in the Rx FIFO in host mode when dynamic FIFO sizing is enabled.
    ++int32_t dwc_otg_get_param_host_rx_fifo_size (dwc_otg_core_if_t *core_if)
    int dwc_otg_set_param_host_nperio_tx_fifo_size (dwc_otg_core_if_t *core_if, int32_t val)
    int dwc_otg_set_param_host_nperio_tx_fifo_size (dwc_otg_core_if_t *core_if, int32_t val)
     Number of 4-byte words in the non-periodic Tx FIFO in host mode when Dynamic FIFO sizing is enabled in the core.
    +-int32_t dwc_otg_get_param_host_nperio_tx_fifo_size (dwc_otg_core_if_t *core_if)
     Number of 4-byte words in the non-periodic Tx FIFO in host mode when Dynamic FIFO sizing is enabled in the core.
    ++int32_t dwc_otg_get_param_host_nperio_tx_fifo_size (dwc_otg_core_if_t *core_if)
    int dwc_otg_set_param_host_perio_tx_fifo_size (dwc_otg_core_if_t *core_if, int32_t val)
    int dwc_otg_set_param_host_perio_tx_fifo_size (dwc_otg_core_if_t *core_if, int32_t val)
     Number of 4-byte words in the host periodic Tx FIFO when dynamic FIFO sizing is enabled.
    +-int32_t dwc_otg_get_param_host_perio_tx_fifo_size (dwc_otg_core_if_t *core_if)
     Number of 4-byte words in the host periodic Tx FIFO when dynamic FIFO sizing is enabled.
    ++int32_t dwc_otg_get_param_host_perio_tx_fifo_size (dwc_otg_core_if_t *core_if)
    int dwc_otg_set_param_max_transfer_size (dwc_otg_core_if_t *core_if, int32_t val)
    int dwc_otg_set_param_max_transfer_size (dwc_otg_core_if_t *core_if, int32_t val)
     The maximum transfer size supported in bytes.
    +-int32_t dwc_otg_get_param_max_transfer_size (dwc_otg_core_if_t *core_if)
     The maximum transfer size supported in bytes.
    ++int32_t dwc_otg_get_param_max_transfer_size (dwc_otg_core_if_t *core_if)
    int dwc_otg_set_param_max_packet_count (dwc_otg_core_if_t *core_if, int32_t val)
    int dwc_otg_set_param_max_packet_count (dwc_otg_core_if_t *core_if, int32_t val)
     The maximum number of packets in a transfer.
    +-int32_t dwc_otg_get_param_max_packet_count (dwc_otg_core_if_t *core_if)
     The maximum number of packets in a transfer.
    ++int32_t dwc_otg_get_param_max_packet_count (dwc_otg_core_if_t *core_if)
    int dwc_otg_set_param_host_channels (dwc_otg_core_if_t *core_if, int32_t val)
    int dwc_otg_set_param_host_channels (dwc_otg_core_if_t *core_if, int32_t val)
     The number of host channel registers to use.
    +-int32_t dwc_otg_get_param_host_channels (dwc_otg_core_if_t *core_if)
     The number of host channel registers to use.
    ++int32_t dwc_otg_get_param_host_channels (dwc_otg_core_if_t *core_if)
    int dwc_otg_set_param_dev_endpoints (dwc_otg_core_if_t *core_if, int32_t val)
    int dwc_otg_set_param_dev_endpoints (dwc_otg_core_if_t *core_if, int32_t val)
     The number of endpoints in addition to EP0 available for device mode operations.
    +-int32_t dwc_otg_get_param_dev_endpoints (dwc_otg_core_if_t *core_if)
     The number of endpoints in addition to EP0 available for device mode operations.
    ++int32_t dwc_otg_get_param_dev_endpoints (dwc_otg_core_if_t *core_if)
    int dwc_otg_set_param_phy_type (dwc_otg_core_if_t *core_if, int32_t val)
    int dwc_otg_set_param_phy_type (dwc_otg_core_if_t *core_if, int32_t val)
     Specifies the type of PHY interface to use.
    +-int32_t dwc_otg_get_param_phy_type (dwc_otg_core_if_t *core_if)
     Specifies the type of PHY interface to use.
    ++int32_t dwc_otg_get_param_phy_type (dwc_otg_core_if_t *core_if)
    int dwc_otg_set_param_phy_utmi_width (dwc_otg_core_if_t *core_if, int32_t val)
    int dwc_otg_set_param_phy_utmi_width (dwc_otg_core_if_t *core_if, int32_t val)
     Specifies the UTMI+ Data Width.
    +-int32_t dwc_otg_get_param_phy_utmi_width (dwc_otg_core_if_t *core_if)
     Specifies the UTMI+ Data Width.
    ++int32_t dwc_otg_get_param_phy_utmi_width (dwc_otg_core_if_t *core_if)
    int dwc_otg_set_param_phy_ulpi_ddr (dwc_otg_core_if_t *core_if, int32_t val)
    int dwc_otg_set_param_phy_ulpi_ddr (dwc_otg_core_if_t *core_if, int32_t val)
     Specifies whether the ULPI operates at double or single data rate.
    +-int32_t dwc_otg_get_param_phy_ulpi_ddr (dwc_otg_core_if_t *core_if)
     Specifies whether the ULPI operates at double or single data rate.
    ++int32_t dwc_otg_get_param_phy_ulpi_ddr (dwc_otg_core_if_t *core_if)
    +-int dwc_otg_set_param_phy_ulpi_ext_vbus (dwc_otg_core_if_t *core_if, int32_t val)
    ++int dwc_otg_set_param_phy_ulpi_ext_vbus (dwc_otg_core_if_t *core_if, int32_t val)
     Specifies whether to use the internal or external supply to drive the vbus with a ULPI phy.
    +-int32_t dwc_otg_get_param_phy_ulpi_ext_vbus (dwc_otg_core_if_t *core_if)
    ++int32_t dwc_otg_get_param_phy_ulpi_ext_vbus (dwc_otg_core_if_t *core_if)
    int dwc_otg_set_param_i2c_enable (dwc_otg_core_if_t *core_if, int32_t val)
    int dwc_otg_set_param_i2c_enable (dwc_otg_core_if_t *core_if, int32_t val)
     Specifies whether to use the I2Cinterface for full speed PHY.
    +-int32_t dwc_otg_get_param_i2c_enable (dwc_otg_core_if_t *core_if)
     Specifies whether to use the I2Cinterface for full speed PHY.
    ++int32_t dwc_otg_get_param_i2c_enable (dwc_otg_core_if_t *core_if)
    +-int dwc_otg_set_param_ulpi_fs_ls (dwc_otg_core_if_t *core_if, int32_t val)
    ++int dwc_otg_set_param_ulpi_fs_ls (dwc_otg_core_if_t *core_if, int32_t val)
    +-int32_t dwc_otg_get_param_ulpi_fs_ls (dwc_otg_core_if_t *core_if)
    ++int32_t dwc_otg_get_param_ulpi_fs_ls (dwc_otg_core_if_t *core_if)
    +-int dwc_otg_set_param_ts_dline (dwc_otg_core_if_t *core_if, int32_t val)
    ++int dwc_otg_set_param_ts_dline (dwc_otg_core_if_t *core_if, int32_t val)
    +-int32_t dwc_otg_get_param_ts_dline (dwc_otg_core_if_t *core_if)
    ++int32_t dwc_otg_get_param_ts_dline (dwc_otg_core_if_t *core_if)
    +-int dwc_otg_set_param_en_multiple_tx_fifo (dwc_otg_core_if_t *core_if, int32_t val)
    ++int dwc_otg_set_param_en_multiple_tx_fifo (dwc_otg_core_if_t *core_if, int32_t val)
     Specifies whether dedicated transmit FIFOs are enabled for non periodic IN endpoints in device mode 0 - No 1 - Yes.
    +-int32_t dwc_otg_get_param_en_multiple_tx_fifo (dwc_otg_core_if_t *core_if)
    ++int32_t dwc_otg_get_param_en_multiple_tx_fifo (dwc_otg_core_if_t *core_if)
    int dwc_otg_set_param_dev_tx_fifo_size (dwc_otg_core_if_t *core_if, int fifo_num, int32_t val)
    int dwc_otg_set_param_dev_tx_fifo_size (dwc_otg_core_if_t *core_if, int fifo_num, int32_t val)
     Number of 4-byte words in each of the Tx FIFOs in device mode when dynamic FIFO sizing is enabled.
    +-int32_t dwc_otg_get_param_dev_tx_fifo_size (dwc_otg_core_if_t *core_if, int fifo_num)
     Number of 4-byte words in each of the Tx FIFOs in device mode when dynamic FIFO sizing is enabled.
    ++int32_t dwc_otg_get_param_dev_tx_fifo_size (dwc_otg_core_if_t *core_if, int fifo_num)
    +-int dwc_otg_set_param_thr_ctl (dwc_otg_core_if_t *core_if, int32_t val)
    ++int dwc_otg_set_param_thr_ctl (dwc_otg_core_if_t *core_if, int32_t val)
     Thresholding enable flag- bit 0 - enable non-ISO Tx thresholding bit 1 - enable ISO Tx thresholding bit 2 - enable Rx thresholding.
    ++
    + int32_t dwc_otg_get_thr_ctl (dwc_otg_core_if_t *core_if, int fifo_num)
    +-int dwc_otg_set_param_tx_thr_length (dwc_otg_core_if_t *core_if, int32_t val)
    ++int dwc_otg_set_param_tx_thr_length (dwc_otg_core_if_t *core_if, int32_t val)
     Thresholding length for Tx FIFOs in 32 bit DWORDs.
    ++
    + int32_t dwc_otg_get_tx_thr_length (dwc_otg_core_if_t *core_if)
    +-int dwc_otg_set_param_rx_thr_length (dwc_otg_core_if_t *core_if, int32_t val)
    ++int dwc_otg_set_param_rx_thr_length (dwc_otg_core_if_t *core_if, int32_t val)
     Thresholding length for Rx FIFOs in 32 bit DWORDs.
    ++
    + int32_t dwc_otg_get_rx_thr_length (dwc_otg_core_if_t *core_if)
    +-int dwc_otg_set_param_lpm_enable (dwc_otg_core_if_t *core_if, int32_t val)
    ++int dwc_otg_set_param_lpm_enable (dwc_otg_core_if_t *core_if, int32_t val)
     Specifies whether LPM (Link Power Management) support is enabled.
    +-int32_t dwc_otg_get_param_lpm_enable (dwc_otg_core_if_t *core_if)
    ++int32_t dwc_otg_get_param_lpm_enable (dwc_otg_core_if_t *core_if)
    +-int dwc_otg_set_param_pti_enable (dwc_otg_core_if_t *core_if, int32_t val)
    ++int dwc_otg_set_param_pti_enable (dwc_otg_core_if_t *core_if, int32_t val)
     Specifies whether PTI enhancement is enabled.
    +-int32_t dwc_otg_get_param_pti_enable (dwc_otg_core_if_t *core_if)
    ++int32_t dwc_otg_get_param_pti_enable (dwc_otg_core_if_t *core_if)
    +-int dwc_otg_set_param_mpi_enable (dwc_otg_core_if_t *core_if, int32_t val)
    ++int dwc_otg_set_param_mpi_enable (dwc_otg_core_if_t *core_if, int32_t val)
     Specifies whether MPI enhancement is enabled.
    +-int32_t dwc_otg_get_param_mpi_enable (dwc_otg_core_if_t *core_if)
    ++int32_t dwc_otg_get_param_mpi_enable (dwc_otg_core_if_t *core_if)
    ++int dwc_otg_set_param_adp_enable (dwc_otg_core_if_t *core_if, int32_t val)
     Specifies whether ADP capability is enabled.
    ++int32_t dwc_otg_get_param_adp_enable (dwc_otg_core_if_t *core_if)
    +-int dwc_otg_set_param_ic_usb_cap (dwc_otg_core_if_t *core_if, int32_t val)
    ++int dwc_otg_set_param_ic_usb_cap (dwc_otg_core_if_t *core_if, int32_t val)
     Specifies whether IC_USB capability is enabled.
    +-int32_t dwc_otg_get_param_ic_usb_cap (dwc_otg_core_if_t *core_if)
    ++int32_t dwc_otg_get_param_ic_usb_cap (dwc_otg_core_if_t *core_if)
    ++int dwc_otg_set_param_ahb_thr_ratio (dwc_otg_core_if_t *core_if, int32_t val)
    ++int32_t dwc_otg_get_param_ahb_thr_ratio (dwc_otg_core_if_t *core_if)
    ++int dwc_otg_set_param_power_down (dwc_otg_core_if_t *core_if, int32_t val)
    +-int dwc_otg_set_param_ahb_thr_ratio (dwc_otg_core_if_t *core_if, int32_t val)
    ++int32_t dwc_otg_get_param_power_down (dwc_otg_core_if_t *core_if)
    +-int32_t dwc_otg_get_param_ahb_thr_ratio (dwc_otg_core_if_t *core_if)
    ++int dwc_otg_set_param_reload_ctl (dwc_otg_core_if_t *core_if, int32_t val)
    ++int32_t dwc_otg_get_param_reload_ctl (dwc_otg_core_if_t *core_if)
    ++int dwc_otg_set_param_dev_out_nak (dwc_otg_core_if_t *core_if, int32_t val)
    ++int32_t dwc_otg_get_param_dev_out_nak (dwc_otg_core_if_t *core_if)
    ++int dwc_otg_set_param_cont_on_bna (dwc_otg_core_if_t *core_if, int32_t val)
    ++int32_t dwc_otg_get_param_cont_on_bna (dwc_otg_core_if_t *core_if)
    ++int dwc_otg_set_param_ahb_single (dwc_otg_core_if_t *core_if, int32_t val)
    ++int32_t dwc_otg_get_param_ahb_single (dwc_otg_core_if_t *core_if)
    ++int dwc_otg_set_param_otg_ver (dwc_otg_core_if_t *core_if, int32_t val)
    ++int32_t dwc_otg_get_param_otg_ver (dwc_otg_core_if_t *core_if)

    Access to registers and bit-fields

    void dwc_otg_dump_dev_registers (dwc_otg_core_if_t *_core_if)
    void dwc_otg_dump_dev_registers (dwc_otg_core_if_t *_core_if)
     Dump core registers and SPRAM.
    void dwc_otg_dump_spram (dwc_otg_core_if_t *_core_if)
     Dump core registers and SPRAM.
    void dwc_otg_dump_spram (dwc_otg_core_if_t *_core_if)
     This functions reads the SPRAM and prints its content.
    void dwc_otg_dump_host_registers (dwc_otg_core_if_t *_core_if)
     This functions reads the SPRAM and prints its content.
    void dwc_otg_dump_host_registers (dwc_otg_core_if_t *_core_if)
     This function reads the host registers and prints them.
    void dwc_otg_dump_global_registers (dwc_otg_core_if_t *_core_if)
     This function reads the host registers and prints them.
    void dwc_otg_dump_global_registers (dwc_otg_core_if_t *_core_if)
     This function reads the core global registers and prints them.
    +-uint32_t dwc_otg_get_hnpstatus (dwc_otg_core_if_t *core_if)
     This function reads the core global registers and prints them.
    ++uint32_t dwc_otg_get_hnpstatus (dwc_otg_core_if_t *core_if)
     Get host negotiation status.
    +-uint32_t dwc_otg_get_srpstatus (dwc_otg_core_if_t *core_if)
    ++uint32_t dwc_otg_get_srpstatus (dwc_otg_core_if_t *core_if)
     Get srp status.
    +-void dwc_otg_set_hnpreq (dwc_otg_core_if_t *core_if, uint32_t val)
    ++void dwc_otg_set_hnpreq (dwc_otg_core_if_t *core_if, uint32_t val)
     Set hnpreq bit in the GOTGCTL register.
    +-uint32_t dwc_otg_get_gsnpsid (dwc_otg_core_if_t *core_if)
    ++uint32_t dwc_otg_get_gsnpsid (dwc_otg_core_if_t *core_if)
     Get Content of SNPSID register.
    uint32_t dwc_otg_get_mode (dwc_otg_core_if_t *core_if)
    uint32_t dwc_otg_get_mode (dwc_otg_core_if_t *core_if)
     Get current mode.
    +-uint32_t dwc_otg_get_hnpcapable (dwc_otg_core_if_t *core_if)
     Get current mode.
    ++uint32_t dwc_otg_get_hnpcapable (dwc_otg_core_if_t *core_if)
     Get value of hnpcapable field in the GUSBCFG register.
    +-void dwc_otg_set_hnpcapable (dwc_otg_core_if_t *core_if, uint32_t val)
    ++void dwc_otg_set_hnpcapable (dwc_otg_core_if_t *core_if, uint32_t val)
     Set value of hnpcapable field in the GUSBCFG register.
    +-uint32_t dwc_otg_get_srpcapable (dwc_otg_core_if_t *core_if)
    ++uint32_t dwc_otg_get_srpcapable (dwc_otg_core_if_t *core_if)
     Get value of srpcapable field in the GUSBCFG register.
    +-void dwc_otg_set_srpcapable (dwc_otg_core_if_t *core_if, uint32_t val)
    ++void dwc_otg_set_srpcapable (dwc_otg_core_if_t *core_if, uint32_t val)
     Set value of srpcapable field in the GUSBCFG register.
    +-uint32_t dwc_otg_get_devspeed (dwc_otg_core_if_t *core_if)
    ++uint32_t dwc_otg_get_devspeed (dwc_otg_core_if_t *core_if)
     Get value of devspeed field in the DCFG register.
    +-void dwc_otg_set_devspeed (dwc_otg_core_if_t *core_if, uint32_t val)
    ++void dwc_otg_set_devspeed (dwc_otg_core_if_t *core_if, uint32_t val)
     Set value of devspeed field in the DCFG register.
    +-uint32_t dwc_otg_get_busconnected (dwc_otg_core_if_t *core_if)
    ++uint32_t dwc_otg_get_busconnected (dwc_otg_core_if_t *core_if)
     Get the value of busconnected field from the HPRT0 register.
    +-uint32_t dwc_otg_get_enumspeed (dwc_otg_core_if_t *core_if)
    ++uint32_t dwc_otg_get_enumspeed (dwc_otg_core_if_t *core_if)
     Gets the device enumeration Speed.
    +-uint32_t dwc_otg_get_prtpower (dwc_otg_core_if_t *core_if)
    ++uint32_t dwc_otg_get_prtpower (dwc_otg_core_if_t *core_if)
     Get value of prtpwr field from the HPRT0 register.
    +-void dwc_otg_set_prtpower (dwc_otg_core_if_t *core_if, uint32_t val)
    ++uint32_t dwc_otg_get_core_state (dwc_otg_core_if_t *core_if)
     Get value of flag indicating core state - hibernated or not.
    ++void dwc_otg_set_prtpower (dwc_otg_core_if_t *core_if, uint32_t val)
     Set value of prtpwr field from the HPRT0 register.
    +-uint32_t dwc_otg_get_prtsuspend (dwc_otg_core_if_t *core_if)
    ++uint32_t dwc_otg_get_prtsuspend (dwc_otg_core_if_t *core_if)
     Get value of prtsusp field from the HPRT0 regsiter.
    +-void dwc_otg_set_prtsuspend (dwc_otg_core_if_t *core_if, uint32_t val)
    ++void dwc_otg_set_prtsuspend (dwc_otg_core_if_t *core_if, uint32_t val)
     Set value of prtpwr field from the HPRT0 register.
    +-void dwc_otg_set_prtresume (dwc_otg_core_if_t *core_if, uint32_t val)
    ++uint32_t dwc_otg_get_mode_ch_tim (dwc_otg_core_if_t *core_if)
     Get value of ModeChTimEn field from the HCFG regsiter.
    ++void dwc_otg_set_mode_ch_tim (dwc_otg_core_if_t *core_if, uint32_t val)
     Set value of ModeChTimEn field from the HCFG regsiter.
    ++uint32_t dwc_otg_get_fr_interval (dwc_otg_core_if_t *core_if)
     Get value of Fram Interval field from the HFIR regsiter.
    ++void dwc_otg_set_fr_interval (dwc_otg_core_if_t *core_if, uint32_t val)
     Set value of Frame Interval field from the HFIR regsiter.
    ++void dwc_otg_set_prtresume (dwc_otg_core_if_t *core_if, uint32_t val)
     Set value of prtres field from the HPRT0 register FIXME Remove?
    +-uint32_t dwc_otg_get_remotewakesig (dwc_otg_core_if_t *core_if)
    ++uint32_t dwc_otg_get_remotewakesig (dwc_otg_core_if_t *core_if)
     Get value of rmtwkupsig bit in DCTL register.
    +-uint32_t dwc_otg_get_lpm_portsleepstatus (dwc_otg_core_if_t *core_if)
    ++uint32_t dwc_otg_get_lpm_portsleepstatus (dwc_otg_core_if_t *core_if)
     Get value of prt_sleep_sts field from the GLPMCFG register.
    +-uint32_t dwc_otg_get_lpm_remotewakeenabled (dwc_otg_core_if_t *core_if)
    ++uint32_t dwc_otg_get_lpm_remotewakeenabled (dwc_otg_core_if_t *core_if)
     Get value of rem_wkup_en field from the GLPMCFG register.
    +-uint32_t dwc_otg_get_lpmresponse (dwc_otg_core_if_t *core_if)
    ++uint32_t dwc_otg_get_lpmresponse (dwc_otg_core_if_t *core_if)
     Get value of appl_resp field from the GLPMCFG register.
    +-void dwc_otg_set_lpmresponse (dwc_otg_core_if_t *core_if, uint32_t val)
    ++void dwc_otg_set_lpmresponse (dwc_otg_core_if_t *core_if, uint32_t val)
     Set value of appl_resp field from the GLPMCFG register.
    +-uint32_t dwc_otg_get_hsic_connect (dwc_otg_core_if_t *core_if)
    ++uint32_t dwc_otg_get_hsic_connect (dwc_otg_core_if_t *core_if)
     Get value of hsic_connect field from the GLPMCFG register.
    +-void dwc_otg_set_hsic_connect (dwc_otg_core_if_t *core_if, uint32_t val)
    ++void dwc_otg_set_hsic_connect (dwc_otg_core_if_t *core_if, uint32_t val)
     Set value of hsic_connect field from the GLPMCFG register.
    +-uint32_t dwc_otg_get_inv_sel_hsic (dwc_otg_core_if_t *core_if)
    ++uint32_t dwc_otg_get_inv_sel_hsic (dwc_otg_core_if_t *core_if)
     Get value of inv_sel_hsic field from the GLPMCFG register.
    +-void dwc_otg_set_inv_sel_hsic (dwc_otg_core_if_t *core_if, uint32_t val)
    ++void dwc_otg_set_inv_sel_hsic (dwc_otg_core_if_t *core_if, uint32_t val)
     Set value of inv_sel_hsic field from the GLPMFG register.
    +-uint32_t dwc_otg_get_gotgctl (dwc_otg_core_if_t *core_if)
    ++uint32_t dwc_otg_get_gotgctl (dwc_otg_core_if_t *core_if)
     GOTGCTL register.
    +-void dwc_otg_set_gotgctl (dwc_otg_core_if_t *core_if, uint32_t val)
    ++void dwc_otg_set_gotgctl (dwc_otg_core_if_t *core_if, uint32_t val)
    +-uint32_t dwc_otg_get_gusbcfg (dwc_otg_core_if_t *core_if)
    ++uint32_t dwc_otg_get_gusbcfg (dwc_otg_core_if_t *core_if)
     GUSBCFG register.
    +-void dwc_otg_set_gusbcfg (dwc_otg_core_if_t *core_if, uint32_t val)
    ++void dwc_otg_set_gusbcfg (dwc_otg_core_if_t *core_if, uint32_t val)
    +-uint32_t dwc_otg_get_grxfsiz (dwc_otg_core_if_t *core_if)
    ++uint32_t dwc_otg_get_grxfsiz (dwc_otg_core_if_t *core_if)
     GRXFSIZ register.
    +-void dwc_otg_set_grxfsiz (dwc_otg_core_if_t *core_if, uint32_t val)
    ++void dwc_otg_set_grxfsiz (dwc_otg_core_if_t *core_if, uint32_t val)
    +-uint32_t dwc_otg_get_gnptxfsiz (dwc_otg_core_if_t *core_if)
    ++uint32_t dwc_otg_get_gnptxfsiz (dwc_otg_core_if_t *core_if)
     GNPTXFSIZ register.
    +-void dwc_otg_set_gnptxfsiz (dwc_otg_core_if_t *core_if, uint32_t val)
    ++void dwc_otg_set_gnptxfsiz (dwc_otg_core_if_t *core_if, uint32_t val)
    +-uint32_t dwc_otg_get_gpvndctl (dwc_otg_core_if_t *core_if)
    ++uint32_t dwc_otg_get_gpvndctl (dwc_otg_core_if_t *core_if)
    +-void dwc_otg_set_gpvndctl (dwc_otg_core_if_t *core_if, uint32_t val)
    ++void dwc_otg_set_gpvndctl (dwc_otg_core_if_t *core_if, uint32_t val)
    +-uint32_t dwc_otg_get_ggpio (dwc_otg_core_if_t *core_if)
    ++uint32_t dwc_otg_get_ggpio (dwc_otg_core_if_t *core_if)
     GGPIO register.
    +-void dwc_otg_set_ggpio (dwc_otg_core_if_t *core_if, uint32_t val)
    ++void dwc_otg_set_ggpio (dwc_otg_core_if_t *core_if, uint32_t val)
    +-uint32_t dwc_otg_get_guid (dwc_otg_core_if_t *core_if)
    ++uint32_t dwc_otg_get_guid (dwc_otg_core_if_t *core_if)
     GUID register.
    +-void dwc_otg_set_guid (dwc_otg_core_if_t *core_if, uint32_t val)
    ++void dwc_otg_set_guid (dwc_otg_core_if_t *core_if, uint32_t val)
    +-uint32_t dwc_otg_get_hprt0 (dwc_otg_core_if_t *core_if)
    ++uint32_t dwc_otg_get_hprt0 (dwc_otg_core_if_t *core_if)
     HPRT0 register.
    +-void dwc_otg_set_hprt0 (dwc_otg_core_if_t *core_if, uint32_t val)
    ++void dwc_otg_set_hprt0 (dwc_otg_core_if_t *core_if, uint32_t val)
    +-uint32_t dwc_otg_get_hptxfsiz (dwc_otg_core_if_t *core_if)
    ++uint32_t dwc_otg_get_hptxfsiz (dwc_otg_core_if_t *core_if)
     GHPTXFSIZE.

    Defines

    +-#define __DWC_CORE_IF_H__
    ++#define __DWC_CORE_IF_H__
    +-#define MAX_PERIO_FIFOS   15
    ++#define MAX_PERIO_FIFOS   15
     Maximum number of Periodic FIFOs.
    +-#define MAX_TX_FIFOS   15
    ++#define MAX_TX_FIFOS   15
     Maximum number of Periodic FIFOs.
    +-#define MAX_EPS_CHANNELS   16
    ++#define MAX_EPS_CHANNELS   16
     Maximum number of Endpoints/HostChannels.

    Typedefs

    +-typedef dwc_otg_core_if dwc_otg_core_if_t
    ++typedef dwc_otg_core_if dwc_otg_core_if_t

    Functions

    dwc_otg_core_if_t * dwc_otg_cil_init (const uint32_t *_reg_base_addr)
    dwc_otg_core_if_t * dwc_otg_cil_init (const uint32_t *_reg_base_addr)
     This function is called to initialize the DWC_otg CSR data structures.
    void dwc_otg_core_init (dwc_otg_core_if_t *_core_if)
     This function is called to initialize the DWC_otg CSR data structures.
    void dwc_otg_core_init (dwc_otg_core_if_t *_core_if)
     This function initializes the DWC_otg controller registers and prepares the core for device mode or host mode operation.
    void dwc_otg_cil_remove (dwc_otg_core_if_t *_core_if)
     This function initializes the DWC_otg controller registers and prepares the core for device mode or host mode operation.
    void dwc_otg_cil_remove (dwc_otg_core_if_t *_core_if)
     This function frees the structures allocated by dwc_otg_cil_init().
    void dwc_otg_enable_global_interrupts (dwc_otg_core_if_t *_core_if)
     This function frees the structures allocated by dwc_otg_cil_init().
    void dwc_otg_enable_global_interrupts (dwc_otg_core_if_t *_core_if)
     This function enables the controller's Global Interrupt in the AHB Config register.
    void dwc_otg_disable_global_interrupts (dwc_otg_core_if_t *_core_if)
     This function enables the controller's Global Interrupt in the AHB Config register.
    void dwc_otg_disable_global_interrupts (dwc_otg_core_if_t *_core_if)
     This function disables the controller's Global Interrupt in the AHB Config register.
    +-uint8_t dwc_otg_is_device_mode (dwc_otg_core_if_t *_core_if)
     This function disables the controller's Global Interrupt in the AHB Config register.
    ++uint8_t dwc_otg_is_device_mode (dwc_otg_core_if_t *_core_if)
    +-uint8_t dwc_otg_is_host_mode (dwc_otg_core_if_t *_core_if)
    ++uint8_t dwc_otg_is_host_mode (dwc_otg_core_if_t *_core_if)
    +-uint8_t dwc_otg_is_dma_enable (dwc_otg_core_if_t *core_if)
    ++uint8_t dwc_otg_is_dma_enable (dwc_otg_core_if_t *core_if)
    int32_t dwc_otg_handle_common_intr (dwc_otg_core_if_t *_core_if)
    int32_t dwc_otg_handle_common_intr (void *otg_dev)
     This function should be called on every hardware interrupt.
     This function should be called on every hardware interrupt.
    +

    Detailed Description

    + This file defines DWC_OTG Core API. +@@ -638,21 +710,29 @@ + +

    + Definition in file dwc_otg_core_if.h.

    Function Documentation

    +- +-
    +-
    +- +- +- +- +- +- +- +- ++

    ++

    dwc_otg_core_if_t* dwc_otg_cil_init (const uint32_t *  reg_base_addr  ) 
    ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ + +
    dwc_otg_core_if_t* dwc_otg_cil_init ( const uint32_t *  reg_base_addr  ) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + This function is called to initialize the DWC_otg CSR data structures. +@@ -660,29 +740,38 @@ + The register addresses in the device and host structures are initialized from the base address supplied by the caller. The calling function must make the OS calls to get the base address of the DWC_otg controller registers. The core_params argument holds the parameters that specify how the core should be configured.

    +

    Parameters:
    + +- ++ +
    reg_base_addr Base address of DWC_otg core registers
    reg_base_addr Base address of DWC_otg core registers
    +
    +- +

    +-Definition at line 78 of file dwc_otg_cil.c. +- +-

    +- +-

    +-
    +- +- +- +- +- +- +- +- ++ADP initialization ++

    ++Definition at line 78 of file dwc_otg_cil.c. ++

    ++
    void dwc_otg_core_init (dwc_otg_core_if_t *  core_if  ) 
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ + +
    void dwc_otg_core_init ( dwc_otg_core_if_t *  core_if  ) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + This function initializes the DWC_otg controller registers and prepares the core for device mode or host mode operation. +@@ -694,53 +783,70 @@ + + +

    +-Definition at line 467 of file dwc_otg_cil.c. +- +-

    +- +-

    +-
    +- +- +- +- +- +- +- +- ++Definition at line 1199 of file dwc_otg_cil.c. ++ ++
    void dwc_otg_cil_remove (dwc_otg_core_if_t *  core_if  ) 
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ + +
    void dwc_otg_cil_remove ( dwc_otg_core_if_t *  core_if  ) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    +-This function frees the structures allocated by dwc_otg_cil_init(). ++This function frees the structures allocated by dwc_otg_cil_init(). +

    +

    Parameters:
    + +- ++ +
    core_if The core interface pointer returned from dwc_otg_cil_init().
    core_if The core interface pointer returned from dwc_otg_cil_init().
    +
    +- +

    +-Definition at line 265 of file dwc_otg_cil.c. +- +-

    +- +-

    +-
    +- +- +- +- +- +- +- +- ++Remove ADP Stuff ++

    ++Definition at line 285 of file dwc_otg_cil.c. ++

    ++
    void dwc_otg_enable_global_interrupts (dwc_otg_core_if_t *  core_if  ) 
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ + +
    void dwc_otg_enable_global_interrupts ( dwc_otg_core_if_t *  core_if  ) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + This function enables the controller's Global Interrupt in the AHB Config register. +@@ -752,24 +858,32 @@ + + +

    +-Definition at line 292 of file dwc_otg_cil.c. +- +-

    +- +-

    +-
    +- +- +- +- +- +- +- +- ++Definition at line 322 of file dwc_otg_cil.c. ++ ++
    void dwc_otg_disable_global_interrupts (dwc_otg_core_if_t *  core_if  ) 
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ + +
    void dwc_otg_disable_global_interrupts ( dwc_otg_core_if_t *  core_if  ) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + This function disables the controller's Global Interrupt in the AHB Config register. +@@ -781,257 +895,321 @@ + + +

    +-Definition at line 305 of file dwc_otg_cil.c. +- +-

    +- +-

    +-
    +- +- +- +- +- +- +- +- ++Definition at line 335 of file dwc_otg_cil.c. ++ ++
    int32_t dwc_otg_handle_common_intr (dwc_otg_core_if_t *  core_if  ) 
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ + +
    int32_t dwc_otg_handle_common_intr ( void *  dev  ) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + This function should be called on every hardware interrupt. +

    + The common interrupts are those that occur in both Host and Device mode. This handler handles the following interrupts:

      +-
    • Mode Mismatch Interrupt
    • Disconnect Interrupt
    • OTG Interrupt
    • Connector ID Status Change Interrupt
    • Session Request Interrupt.
    • Resume / Remote Wakeup Detected Interrupt.
    • LPM Transaction Received Interrutp
    ++
  • Mode Mismatch Interrupt
  • Disconnect Interrupt
  • OTG Interrupt
  • Connector ID Status Change Interrupt
  • Session Request Interrupt.
  • Resume / Remote Wakeup Detected Interrupt.
  • LPM Transaction Received Interrupt
  • ADP Transaction Received Interrupt
    • + +

    +-Definition at line 800 of file dwc_otg_cil_intr.c. +- +-

    +- +-

    +-
    +- ++Definition at line 1275 of file dwc_otg_cil_intr.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    int dwc_otg_set_param_otg_cap (dwc_otg_core_if_t *  core_if, int dwc_otg_set_param_otg_cap ( dwc_otg_core_if_t *  core_if,
    int32_t  val int32_t  val
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Specifies the OTG capabilities. +

    + The driver will automatically detect the value for this parameter if none is specified. 0 - HNP and SRP capable (default) 1 - SRP Only capable 2 - No HNP/SRP capable +

    +-Definition at line 4056 of file dwc_otg_cil.c. +- +-

    +- +-

    +-
    +- ++Definition at line 5361 of file dwc_otg_cil.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    int dwc_otg_set_param_dma_enable (dwc_otg_core_if_t *  core_if, int dwc_otg_set_param_dma_enable ( dwc_otg_core_if_t *  core_if,
    int32_t  val int32_t  val
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Specifies whether to use slave or DMA mode for accessing the data FIFOs. +

    + The driver will automatically detect the value for this parameter if none is specified. 0 - Slave 1 - DMA (default, if available) +

    +-Definition at line 4135 of file dwc_otg_cil.c. +- +-

    +- +-

    +-
    +- ++Definition at line 5440 of file dwc_otg_cil.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    int dwc_otg_set_param_dma_desc_enable (dwc_otg_core_if_t *  core_if, int dwc_otg_set_param_dma_desc_enable ( dwc_otg_core_if_t *  core_if,
    int32_t  val int32_t  val
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + When DMA mode is enabled specifies whether to use address DMA or DMA Descritor mode for accessing the data FIFOs in device mode. +

    + The driver will automatically detect the value for this parameter if none is specified. 0 - address DMA 1 - DMA Descriptor(default, if available) +

    +-Definition at line 4165 of file dwc_otg_cil.c. +- +-

    +- +-

    +-
    +- ++Definition at line 5470 of file dwc_otg_cil.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    int dwc_otg_set_param_dma_burst_size (dwc_otg_core_if_t *  core_if, int dwc_otg_set_param_dma_burst_size ( dwc_otg_core_if_t *  core_if,
    int32_t  val int32_t  val
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + The DMA Burst size (applicable only for External DMA Mode). +

    + 1, 4, 8 16, 32, 64, 128, 256 (default 32) +

    +-Definition at line 4959 of file dwc_otg_cil.c. +- +-

    +- +-

    +-
    +- ++Definition at line 6275 of file dwc_otg_cil.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    int dwc_otg_set_param_speed (dwc_otg_core_if_t *  core_if, int dwc_otg_set_param_speed ( dwc_otg_core_if_t *  core_if,
    int32_t  val int32_t  val
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Specifies the maximum speed of operation in host and device mode. +

    + The actual speed depends on the speed of the attached device and the value of phy_type. The actual speed depends on the speed of the attached device. 0 - High Speed (default) 1 - Full Speed +

    +-Definition at line 4601 of file dwc_otg_cil.c. +- +-

    +- +-

    +-
    +- ++Definition at line 5904 of file dwc_otg_cil.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    int dwc_otg_set_param_host_support_fs_ls_low_power (dwc_otg_core_if_t *  core_if, int dwc_otg_set_param_host_support_fs_ls_low_power ( dwc_otg_core_if_t *  core_if,
    int32_t  val int32_t  val
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Specifies whether low power mode is supported when attached to a Full Speed or Low Speed device in host mode. +

    + 0 - Don't support low power mode (default) 1 - Support low power mode +

    +-Definition at line 4195 of file dwc_otg_cil.c. +- +-

    +- +-

    +-
    +- ++Definition at line 5500 of file dwc_otg_cil.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    int dwc_otg_set_param_host_ls_low_power_phy_clk (dwc_otg_core_if_t *  core_if, int dwc_otg_set_param_host_ls_low_power_phy_clk ( dwc_otg_core_if_t *  core_if,
    int32_t  val int32_t  val
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Specifies the PHY clock rate in low power mode when connected to a Low Speed device in host mode. +@@ -1039,402 +1217,498 @@ + This parameter is applicable only if HOST_SUPPORT_FS_LS_LOW_POWER is enabled. If PHY_TYPE is set to FS then defaults to 6 MHZ otherwise 48 MHZ.

    + 0 - 48 MHz 1 - 6 MHz +

    +-Definition at line 4630 of file dwc_otg_cil.c. +- +-

    +- +-

    +-
    +- ++Definition at line 5933 of file dwc_otg_cil.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    int dwc_otg_set_param_data_fifo_size (dwc_otg_core_if_t *  core_if, int dwc_otg_set_param_data_fifo_size ( dwc_otg_core_if_t *  core_if,
    int32_t  val int32_t  val
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Total number of 4-byte words in the data FIFO memory. +

    + This memory includes the Rx FIFO, non-periodic Tx FIFO, and periodic Tx FIFOs. 32 to 32768 (default 8192) Note: The total FIFO memory depth in the FPGA configuration is 8192. +

    +-Definition at line 4242 of file dwc_otg_cil.c. +- +-

    +- +-

    +-
    +- ++Definition at line 5547 of file dwc_otg_cil.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    int dwc_otg_set_param_dev_rx_fifo_size (dwc_otg_core_if_t *  core_if, int dwc_otg_set_param_dev_rx_fifo_size ( dwc_otg_core_if_t *  core_if,
    int32_t  val int32_t  val
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Number of 4-byte words in the Rx FIFO in device mode when dynamic FIFO sizing is enabled. +

    + 16 to 32768 (default 1064) +

    +-Definition at line 4271 of file dwc_otg_cil.c. +- +-

    +- +-

    +-
    +- ++Definition at line 5576 of file dwc_otg_cil.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    int dwc_otg_set_param_dev_nperio_tx_fifo_size (dwc_otg_core_if_t *  core_if, int dwc_otg_set_param_dev_nperio_tx_fifo_size ( dwc_otg_core_if_t *  core_if,
    int32_t  val int32_t  val
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Number of 4-byte words in the non-periodic Tx FIFO in device mode when dynamic FIFO sizing is enabled. +

    + 16 to 32768 (default 1024) +

    +-Definition at line 4297 of file dwc_otg_cil.c. +- +-

    +- +-

    +-
    +- ++Definition at line 5602 of file dwc_otg_cil.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    int dwc_otg_set_param_dev_perio_tx_fifo_size (dwc_otg_core_if_t *  core_if, int dwc_otg_set_param_dev_perio_tx_fifo_size ( dwc_otg_core_if_t *  core_if,
    int32_t  val, int32_t  val,
    int  fifo_num int  fifo_num
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Number of 4-byte words in each of the periodic Tx FIFOs in device mode when dynamic FIFO sizing is enabled. +

    + 4 to 768 (default 256) +

    +-Definition at line 4779 of file dwc_otg_cil.c. +- +-

    +- +-

    +-
    +- ++Definition at line 6085 of file dwc_otg_cil.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    int dwc_otg_set_param_host_rx_fifo_size (dwc_otg_core_if_t *  core_if, int dwc_otg_set_param_host_rx_fifo_size ( dwc_otg_core_if_t *  core_if,
    int32_t  val int32_t  val
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Number of 4-byte words in the Rx FIFO in host mode when dynamic FIFO sizing is enabled. +

    + 16 to 32768 (default 1024) +

    +-Definition at line 4330 of file dwc_otg_cil.c. +- +-

    +- +-

    +-
    +- ++Definition at line 5635 of file dwc_otg_cil.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    int dwc_otg_set_param_host_nperio_tx_fifo_size (dwc_otg_core_if_t *  core_if, int dwc_otg_set_param_host_nperio_tx_fifo_size ( dwc_otg_core_if_t *  core_if,
    int32_t  val int32_t  val
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Number of 4-byte words in the non-periodic Tx FIFO in host mode when Dynamic FIFO sizing is enabled in the core. +

    + 16 to 32768 (default 1024) +

    +-Definition at line 4362 of file dwc_otg_cil.c. +- +-

    +- +-

    +-
    +- ++Definition at line 5667 of file dwc_otg_cil.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    int dwc_otg_set_param_host_perio_tx_fifo_size (dwc_otg_core_if_t *  core_if, int dwc_otg_set_param_host_perio_tx_fifo_size ( dwc_otg_core_if_t *  core_if,
    int32_t  val int32_t  val
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Number of 4-byte words in the host periodic Tx FIFO when dynamic FIFO sizing is enabled. +

    + 16 to 32768 (default 1024) +

    +-Definition at line 4395 of file dwc_otg_cil.c. +- +-

    +- +-

    +-
    +- ++Definition at line 5700 of file dwc_otg_cil.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    int dwc_otg_set_param_max_transfer_size (dwc_otg_core_if_t *  core_if, int dwc_otg_set_param_max_transfer_size ( dwc_otg_core_if_t *  core_if,
    int32_t  val int32_t  val
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + The maximum transfer size supported in bytes. +

    + 2047 to 65,535 (default 65,535) +

    +-Definition at line 4428 of file dwc_otg_cil.c. +- +-

    +- +-

    +-
    +- ++Definition at line 5731 of file dwc_otg_cil.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    int dwc_otg_set_param_max_packet_count (dwc_otg_core_if_t *  core_if, int dwc_otg_set_param_max_packet_count ( dwc_otg_core_if_t *  core_if,
    int32_t  val int32_t  val
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + The maximum number of packets in a transfer. +

    + 15 to 511 (default 511) +

    +-Definition at line 4461 of file dwc_otg_cil.c. +- +-

    +- +-

    +-
    +- ++Definition at line 5764 of file dwc_otg_cil.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    int dwc_otg_set_param_host_channels (dwc_otg_core_if_t *  core_if, int dwc_otg_set_param_host_channels ( dwc_otg_core_if_t *  core_if,
    int32_t  val int32_t  val
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + The number of host channel registers to use. +

    + 1 to 16 (default 12) Note: The FPGA configuration supports a maximum of 12 host channels. +

    +-Definition at line 4492 of file dwc_otg_cil.c. +- +-

    +- +-

    +-
    +- ++Definition at line 5795 of file dwc_otg_cil.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    int dwc_otg_set_param_dev_endpoints (dwc_otg_core_if_t *  core_if, int dwc_otg_set_param_dev_endpoints ( dwc_otg_core_if_t *  core_if,
    int32_t  val int32_t  val
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + The number of endpoints in addition to EP0 available for device mode operations. +

    + 1 to 15 (default 6 IN and OUT) Note: The FPGA configuration supports a maximum of 6 IN and OUT endpoints in addition to EP0. +

    +-Definition at line 4522 of file dwc_otg_cil.c. +- +-

    +- +-

    +-
    +- ++Definition at line 5825 of file dwc_otg_cil.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    int dwc_otg_set_param_phy_type (dwc_otg_core_if_t *  core_if, int dwc_otg_set_param_phy_type ( dwc_otg_core_if_t *  core_if,
    int32_t  val int32_t  val
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Specifies the type of PHY interface to use. +@@ -1442,33 +1716,41 @@ + By default, the driver will automatically detect the phy_type.

    + 0 - Full Speed PHY 1 - UTMI+ (default) 2 - ULPI +

    +-Definition at line 4552 of file dwc_otg_cil.c. +- +-

    +- +-

    +-
    +- ++Definition at line 5855 of file dwc_otg_cil.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    int dwc_otg_set_param_phy_utmi_width (dwc_otg_core_if_t *  core_if, int dwc_otg_set_param_phy_utmi_width ( dwc_otg_core_if_t *  core_if,
    int32_t  val int32_t  val
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Specifies the UTMI+ Data Width. +@@ -1476,33 +1758,41 @@ + This parameter is applicable for a PHY_TYPE of UTMI+ or ULPI. (For a ULPI PHY_TYPE, this parameter indicates the data width between the MAC and the ULPI Wrapper.) Also, this parameter is applicable only if the OTG_HSPHY_WIDTH cC parameter was set to "8 and 16 bits", meaning that the core has been configured to work at either data path width.

    + 8 or 16 bits (default 16) +

    +-Definition at line 4700 of file dwc_otg_cil.c. +- +-

    +- +-

    +-
    +- ++Definition at line 6005 of file dwc_otg_cil.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    int dwc_otg_set_param_phy_ulpi_ddr (dwc_otg_core_if_t *  core_if, int dwc_otg_set_param_phy_ulpi_ddr ( dwc_otg_core_if_t *  core_if,
    int32_t  val int32_t  val
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Specifies whether the ULPI operates at double or single data rate. +@@ -1510,94 +1800,118 @@ + This parameter is only applicable if PHY_TYPE is ULPI.

    + 0 - single data rate ULPI interface with 8 bit wide data bus (default) 1 - double data rate ULPI interface with 4 bit wide data bus +

    +-Definition at line 4665 of file dwc_otg_cil.c. +- +-

    +- +-

    +-
    +- ++Definition at line 5970 of file dwc_otg_cil.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    int dwc_otg_set_param_i2c_enable (dwc_otg_core_if_t *  core_if, int dwc_otg_set_param_i2c_enable ( dwc_otg_core_if_t *  core_if,
    int32_t  val int32_t  val
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Specifies whether to use the I2Cinterface for full speed PHY. +

    + This parameter is only applicable if PHY_TYPE is FS. 0 - No (default) 1 - Yes +

    +-Definition at line 4751 of file dwc_otg_cil.c. +- +-

    +- +-

    +-
    +- ++Definition at line 6056 of file dwc_otg_cil.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    int dwc_otg_set_param_dev_tx_fifo_size (dwc_otg_core_if_t *  core_if, int dwc_otg_set_param_dev_tx_fifo_size ( dwc_otg_core_if_t *  core_if,
    int  fifo_num, int  fifo_num,
    int32_t  val int32_t  val
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Number of 4-byte words in each of the Tx FIFOs in device mode when dynamic FIFO sizing is enabled. +

    +-4 to 768 (default 256) +- +-

    +- +-

    +-
    +- +- +- +- +- +- +- +- ++4 to 768 (default 256) ++ ++
    void dwc_otg_dump_dev_registers (dwc_otg_core_if_t *  core_if  ) 
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ + +
    void dwc_otg_dump_dev_registers ( dwc_otg_core_if_t *  core_if  ) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Dump core registers and SPRAM. +@@ -1609,24 +1923,32 @@ + + +

    +-Definition at line 3347 of file dwc_otg_cil.c. +- +-

    +- +-

    +-
    +- +- +- +- +- +- +- +- ++Definition at line 4620 of file dwc_otg_cil.c. ++ ++
    void dwc_otg_dump_spram (dwc_otg_core_if_t *  core_if  ) 
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ + +
    void dwc_otg_dump_spram ( dwc_otg_core_if_t *  core_if  ) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + This functions reads the SPRAM and prints its content. +@@ -1638,24 +1960,32 @@ + + +

    +-Definition at line 3477 of file dwc_otg_cil.c. +- +-

    +- +-

    +-
    +- +- +- +- +- +- +- +- ++Definition at line 4756 of file dwc_otg_cil.c. ++ ++
    void dwc_otg_dump_host_registers (dwc_otg_core_if_t *  core_if  ) 
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ + +
    void dwc_otg_dump_host_registers ( dwc_otg_core_if_t *  core_if  ) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + This function reads the host registers and prints them. +@@ -1667,24 +1997,32 @@ + + +

    +-Definition at line 3505 of file dwc_otg_cil.c. +- +-

    +- +-

    +-
    +- +- +- +- +- +- +- +- ++Definition at line 4784 of file dwc_otg_cil.c. ++ ++
    void dwc_otg_dump_global_registers (dwc_otg_core_if_t *  core_if  ) 
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ + +
    void dwc_otg_dump_global_registers ( dwc_otg_core_if_t *  core_if  ) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + This function reads the core global registers and prints them. +@@ -1696,35 +2034,43 @@ + + +

    +-Definition at line 3573 of file dwc_otg_cil.c. +- +-

    +- +-

    +-
    +- +- +- +- +- +- +- +- ++Definition at line 4853 of file dwc_otg_cil.c. ++ ++
    uint32_t dwc_otg_get_mode (dwc_otg_core_if_t *  core_if  ) 
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ + +
    uint32_t dwc_otg_get_mode ( dwc_otg_core_if_t *  core_if  ) 
    +- +-
    ++
    ++ ++ ++ ++ ++ ++
    ++   ++ + +

    + Get current mode. +

    + Returns 0 if in device mode, and 1 if in host mode. +

    +-Definition at line 5115 of file dwc_otg_cil.c. +- +-

    +-

    Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++Definition at line 6653 of file dwc_otg_cil.c.
    ++

    Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
    ++doxygen 1.3.9.1 + + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__dbg_8h-source.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/dwc__otg__dbg_8h-source.html 2013-07-26 19:31:20.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__dbg_8h-source.html 2013-07-26 19:34:40.000000000 +0000 +@@ -2,99 +2,87 @@ + + DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_dbg.h Source File + +- + +- +-
    +-
    +-
    +-
    +-

    dwc_otg_dbg.h

    Go to the documentation of this file.
    00001 /* ==========================================================================
+-00002  *
+-00003  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
+-00004  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
+-00005  * otherwise expressly agreed to in writing between Synopsys and you.
+-00006  * 
+-00007  * The Software IS NOT an item of Licensed Software or Licensed Product under
+-00008  * any End User Software License Agreement or Agreement for Licensed Product
+-00009  * with Synopsys or any supplement thereto. You are permitted to use and
+-00010  * redistribute this Software in source and binary forms, with or without
+-00011  * modification, provided that redistributions of source code must retain this
+-00012  * notice. You may not view, use, disclose, copy or distribute this file or
+-00013  * any information contained herein except pursuant to this license grant from
+-00014  * Synopsys. If you do not agree with this notice, including the disclaimer
+-00015  * below, then you are not authorized to use the Software.
+-00016  * 
+-00017  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
+-00018  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+-00019  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+-00020  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
+-00021  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+-00022  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+-00023  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+-00024  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+-00025  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+-00026  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+-00027  * DAMAGE.
+-00028  * ========================================================================== */
+-00029 
+-00030 #ifndef __DWC_OTG_DBG_H__
+-00031 #define __DWC_OTG_DBG_H__
+-00032 
+-00041 extern uint32_t g_dbg_lvl;
+-00045 static inline uint32_t SET_DEBUG_LEVEL(const uint32_t new)
+-00046 {
+-00047         uint32_t old = g_dbg_lvl;
+-00048         g_dbg_lvl = new;
+-00049         return old;
+-00050 }
+-00051 
+-00053 #define DBG_CIL         (0x2)
+-00054 
+-00056 #define DBG_CILV        (0x20)
+-00057 
+-00059 #define DBG_PCD         (0x4)
+-00060 
+-00062 #define DBG_PCDV        (0x40)
+-00063 
+-00064 #define DBG_HCD         (0x8)
+-00065 
+-00067 #define DBG_HCDV        (0x80)
+-00068 
+-00070 #define DBG_HCD_URB     (0x800)
+-00071 
+-00073 #define DBG_ANY         (0xFF)
+-00074 
+-00076 #define DBG_OFF         0
+-00077 
+-00079 #define USB_DWC "DWC_otg: "
+-00080 
+-00098 #ifdef DEBUG
+-00099 
+-00100 # define DWC_DEBUGPL(lvl, x...) do{ if ((lvl)&g_dbg_lvl)__DWC_DEBUG(USB_DWC x ); }while(0)
+-00101 # define DWC_DEBUGP(x...)       DWC_DEBUGPL(DBG_ANY, x )
+-00102 
+-00103 # define CHK_DEBUG_LEVEL(level) ((level) & g_dbg_lvl)
+-00104 
+-00105 #else
+-00106 
+-00107 # define DWC_DEBUGPL(lvl, x...) do{}while(0)
+-00108 # define DWC_DEBUGP(x...)
+-00109 
+-00110 # define CHK_DEBUG_LEVEL(level) (0)
+-00111 
+-00112 #endif /*DEBUG*/
+-00113 #endif
+-
    Generated on Tue May 5 02:22:48 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++
    Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
    ++

    dwc_otg_dbg.h

    Go to the documentation of this file.
    00001 /* ==========================================================================
++00002  *
++00003  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
++00004  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
++00005  * otherwise expressly agreed to in writing between Synopsys and you.
++00006  * 
++00007  * The Software IS NOT an item of Licensed Software or Licensed Product under
++00008  * any End User Software License Agreement or Agreement for Licensed Product
++00009  * with Synopsys or any supplement thereto. You are permitted to use and
++00010  * redistribute this Software in source and binary forms, with or without
++00011  * modification, provided that redistributions of source code must retain this
++00012  * notice. You may not view, use, disclose, copy or distribute this file or
++00013  * any information contained herein except pursuant to this license grant from
++00014  * Synopsys. If you do not agree with this notice, including the disclaimer
++00015  * below, then you are not authorized to use the Software.
++00016  * 
++00017  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
++00018  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++00019  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++00020  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
++00021  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++00022  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
++00023  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
++00024  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
++00025  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
++00026  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
++00027  * DAMAGE.
++00028  * ========================================================================== */
++00029 
++00030 #ifndef __DWC_OTG_DBG_H__
++00031 #define __DWC_OTG_DBG_H__
++00032 
++00041 extern uint32_t g_dbg_lvl;
++00045 static inline uint32_t SET_DEBUG_LEVEL(const uint32_t new)
++00046 {
++00047         uint32_t old = g_dbg_lvl;
++00048         g_dbg_lvl = new;
++00049         return old;
++00050 }
++00051 
++00053 #define DBG_CIL         (0x2)
++00054 
++00056 #define DBG_CILV        (0x20)
++00057 
++00059 #define DBG_PCD         (0x4)
++00060 
++00062 #define DBG_PCDV        (0x40)
++00063 
++00064 #define DBG_HCD         (0x8)
++00065 
++00067 #define DBG_HCDV        (0x80)
++00068 
++00070 #define DBG_HCD_URB     (0x800)
++00071 
++00073 #define DBG_ANY         (0xFF)
++00074 
++00076 #define DBG_OFF         0
++00077 
++00079 #define USB_DWC "DWC_otg: "
++00080 
++00098 #ifdef DEBUG
++00099 
++00100 # define DWC_DEBUGPL(lvl, x...) do{ if ((lvl)&g_dbg_lvl)__DWC_DEBUG(USB_DWC x ); }while(0)
++00101 # define DWC_DEBUGP(x...)       DWC_DEBUGPL(DBG_ANY, x )
++00102 
++00103 # define CHK_DEBUG_LEVEL(level) ((level) & g_dbg_lvl)
++00104 
++00105 #else
++00106 
++00107 # define DWC_DEBUGPL(lvl, x...) do{}while(0)
++00108 # define DWC_DEBUGP(x...)
++00109 
++00110 # define CHK_DEBUG_LEVEL(level) (0)
++00111 
++00112 #endif /*DEBUG*/
++00113 #endif
++
    Generated on Thu Oct 27 03:56:37 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
    ++doxygen 1.3.9.1
    + + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__dbg_8h.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/dwc__otg__dbg_8h.html 2013-07-26 19:31:20.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__dbg_8h.html 2013-07-26 19:34:40.000000000 +0000 +@@ -2,21 +2,9 @@ + + DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_dbg.h File Reference + +- + +- +-
    +-
    +-
    +-
    ++ ++
    Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
    +

    dwc_otg_dbg.h File Reference

    This file defines debug levels. More... +

    + +@@ -24,90 +12,98 @@ + Go to the source code of this file. + + +- ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ + +- +- ++ ++ + +- ++ + + +- ++ + + + +- ++ + + +

    Defines

    +-#define DBG_CIL   (0x2)
    ++#define DBG_CIL   (0x2)
     When debug level has the DBG_CIL bit set, display CIL Debug messages.
    +-#define DBG_CILV   (0x20)
    ++#define DBG_CILV   (0x20)
     When debug level has the DBG_CILV bit set, display CIL Verbose debug messages.
    +-#define DBG_PCD   (0x4)
    ++#define DBG_PCD   (0x4)
     When debug level has the DBG_PCD bit set, display PCD (Device) debug messages.
    +-#define DBG_PCDV   (0x40)
    ++#define DBG_PCDV   (0x40)
     When debug level has the DBG_PCDV set, display PCD (Device) Verbose debug messages.
    +-#define DBG_HCD   (0x8)
    ++#define DBG_HCD   (0x8)
     When debug level has the DBG_HCD bit set, display Host debug messages.
    +-#define DBG_HCDV   (0x80)
    ++#define DBG_HCDV   (0x80)
     When debug level has the DBG_HCDV bit set, display Verbose Host debug messages.
    +-#define DBG_HCD_URB   (0x800)
    ++#define DBG_HCD_URB   (0x800)
     When debug level has the DBG_HCD_URB bit set, display enqueued URBs in host mode.
    +-#define DBG_ANY   (0xFF)
    ++#define DBG_ANY   (0xFF)
     When debug level has any bit set, display debug messages.
    +-#define DBG_OFF   0
    ++#define DBG_OFF   0
     All debug messages off.
    +-#define USB_DWC   "DWC_otg: "
    ++#define USB_DWC   "DWC_otg: "
     Prefix string for DWC_DEBUG print macros.
    #define DWC_DEBUGPL(lvl, x...)   do{}while(0)
    #define DWC_DEBUGPL(lvl, x...)   do{}while(0)
     Print a debug message when the Global debug level variable contains the bit defined in lvl.
    +-#define DWC_DEBUGP(x...)
     Print a debug message when the Global debug level variable contains the bit defined in lvl.
    ++#define DWC_DEBUGP(x...)
    +-#define CHK_DEBUG_LEVEL(level)   (0)
    ++#define CHK_DEBUG_LEVEL(level)   (0)

    Functions

    +-static uint32_t SET_DEBUG_LEVEL (const uint32_t new)
    ++uint32_t SET_DEBUG_LEVEL (const uint32_t new)
     Set the Debug Level variable.

    Variables

    +-uint32_t g_dbg_lvl
    ++uint32_t g_dbg_lvl
     The Debug Level bit-mask variable.
    +

    Detailed Description

    + This file defines debug levels. +

    +-Debugging support vanishes in non-debug builds. ++Debugging support vanishes in non-debug builds. +

    + Definition in file dwc_otg_dbg.h.

    Define Documentation

    +- +-
    +-
    +- ++

    ++

    ++ ++ ++ ++
    ++ + +- +- +- +- +- +- +- +- +- ++ ++ ++ ++ ++ ++ ++ ++ ++ + +
    #define DWC_DEBUGPL (lvl,
    x...   )    do{}while(0)#define DWC_DEBUGPL ( lvl,
    x...   )    do{}while(0)
    +- +-
    ++
    ++ ++ ++ ++ ++ ++
    ++   ++ + +

    + Print a debug message when the Global debug level variable contains the bit defined in lvl. +@@ -123,11 +119,11 @@ + results in:
    + usb-DWC_otg: dwc_otg_cil_init(ca867000) +

    +-Definition at line 107 of file dwc_otg_dbg.h. +- +-

    +-

    Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++Definition at line 107 of file dwc_otg_dbg.h.
    ++
    Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
    ++doxygen 1.3.9.1 + + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__driver_8c-source.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/dwc__otg__driver_8c-source.html 2013-07-26 19:31:20.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__driver_8c-source.html 2013-07-26 19:34:40.000000000 +0000 +@@ -2,1078 +2,1140 @@ + + DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_driver.c Source File + +- + +- +-
    +-
    +-
    +-
    +-

    dwc_otg_driver.c

    Go to the documentation of this file.
    00001 /* ==========================================================================
+-00002  * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_driver.c $
+-00003  * $Revision: #76 $
+-00004  * $Date: 2009/05/03 $
+-00005  * $Change: 1245589 $
+-00006  *
+-00007  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
+-00008  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
+-00009  * otherwise expressly agreed to in writing between Synopsys and you.
+-00010  *
+-00011  * The Software IS NOT an item of Licensed Software or Licensed Product under
+-00012  * any End User Software License Agreement or Agreement for Licensed Product
+-00013  * with Synopsys or any supplement thereto. You are permitted to use and
+-00014  * redistribute this Software in source and binary forms, with or without
+-00015  * modification, provided that redistributions of source code must retain this
+-00016  * notice. You may not view, use, disclose, copy or distribute this file or
+-00017  * any information contained herein except pursuant to this license grant from
+-00018  * Synopsys. If you do not agree with this notice, including the disclaimer
+-00019  * below, then you are not authorized to use the Software.
+-00020  *
+-00021  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
+-00022  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+-00023  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+-00024  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
+-00025  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+-00026  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+-00027  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+-00028  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+-00029  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+-00030  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+-00031  * DAMAGE.
+-00032  * ========================================================================== */
+-00033 
+-00051 #include <linux/kernel.h>
+-00052 #include <linux/module.h>
+-00053 #include <linux/moduleparam.h>
+-00054 #include <linux/init.h>
+-00055 #include <linux/device.h>
+-00056 #include <linux/errno.h>
+-00057 #include <linux/types.h>
+-00058 #include <linux/stat.h>         /* permission constants */
+-00059 #include <linux/version.h>
+-00060 #include <linux/interrupt.h>
+-00061 
+-00062 #ifdef LM_INTERFACE
+-00063 #include <asm/arch/regs-irq.h>
+-00064 #include <asm/arch/lm.h>
+-00065 #include <asm/sizes.h>
+-00066 #endif
+-00067 
+-00068 # include <linux/irq.h>
+-00069 
+-00070 #include <asm/io.h>
+-00071 
+-00072 
+-00073 #include "dwc_os.h"
+-00074 #include "dwc_otg_dbg.h"
+-00075 #include "dwc_otg_driver.h"
+-00076 #include "dwc_otg_attr.h"
+-00077 #include "dwc_otg_core_if.h"
+-00078 #include "dwc_otg_pcd_if.h"
+-00079 #include "dwc_otg_hcd_if.h"
+-00080 
+-00081 #define DWC_DRIVER_VERSION      "2.90a 23-APR-2009"
+-00082 #define DWC_DRIVER_DESC         "HS OTG USB Controller driver"
+-00083 
+-00084 static const char dwc_driver_name[] = "dwc_otg";
+-00085 
+-00086 extern int pcd_init(
+-00087 #ifdef LM_INTERFACE
+-00088         struct lm_device *_dev
+-00089 #elif  PCI_INTERFACE
+-00090         struct pci_dev *_dev
+-00091 #endif
+-00092         );
+-00093 extern int hcd_init(
+-00094 #ifdef LM_INTERFACE
+-00095         struct lm_device *_dev
+-00096 #elif  PCI_INTERFACE
+-00097         struct pci_dev *_dev
+-00098 #endif
+-00099         );
+-00100 
+-00101 extern int pcd_remove(
+-00102 #ifdef LM_INTERFACE
+-00103         struct lm_device *_dev
+-00104 #elif  PCI_INTERFACE
+-00105         struct pci_dev *_dev
+-00106 #endif
+-00107         );
+-00108 
+-00109 extern void hcd_remove(
+-00110 #ifdef LM_INTERFACE
+-00111         struct lm_device *_dev
+-00112 #elif  PCI_INTERFACE
+-00113         struct pci_dev *_dev
+-00114 #endif
+-00115         );
+-00116 
+-00117 /*-------------------------------------------------------------------------*/
+-00118 /* Encapsulate the module parameter settings */
+-00119 
+-00120 struct dwc_otg_driver_module_params {
+-00121         int32_t opt;
+-00122         int32_t otg_cap;
+-00123         int32_t dma_enable;
+-00124         int32_t dma_desc_enable;
+-00125         int32_t dma_burst_size;
+-00126         int32_t speed;
+-00127         int32_t host_support_fs_ls_low_power;
+-00128         int32_t host_ls_low_power_phy_clk;
+-00129         int32_t enable_dynamic_fifo;
+-00130         int32_t data_fifo_size;
+-00131         int32_t dev_rx_fifo_size;
+-00132         int32_t dev_nperio_tx_fifo_size;
+-00133         uint32_t dev_perio_tx_fifo_size[MAX_PERIO_FIFOS];
+-00134         int32_t host_rx_fifo_size;
+-00135         int32_t host_nperio_tx_fifo_size;
+-00136         int32_t host_perio_tx_fifo_size;
+-00137         int32_t max_transfer_size;
+-00138         int32_t max_packet_count;
+-00139         int32_t host_channels;
+-00140         int32_t dev_endpoints;
+-00141         int32_t phy_type;
+-00142         int32_t phy_utmi_width;
+-00143         int32_t phy_ulpi_ddr;
+-00144         int32_t phy_ulpi_ext_vbus;
+-00145         int32_t i2c_enable;
+-00146         int32_t ulpi_fs_ls;
+-00147         int32_t ts_dline;
+-00148         int32_t en_multiple_tx_fifo;
+-00149         uint32_t dev_tx_fifo_size[MAX_TX_FIFOS];
+-00150         uint32_t thr_ctl;
+-00151         uint32_t tx_thr_length;
+-00152         uint32_t rx_thr_length;
+-00153         int32_t pti_enable;
+-00154         int32_t mpi_enable;
+-00155         int32_t lpm_enable;
+-00156         int32_t ic_usb_cap;
+-00157         int32_t ahb_thr_ratio;
+-00158 };
+-00159 
+-00160 static struct dwc_otg_driver_module_params dwc_otg_module_params = {
+-00161         .opt = -1,
+-00162         .otg_cap = -1,
+-00163         .dma_enable = -1,
+-00164         .dma_desc_enable = -1,
+-00165         .dma_burst_size = -1,
+-00166         .speed = -1,
+-00167         .host_support_fs_ls_low_power = -1,
+-00168         .host_ls_low_power_phy_clk = -1,
+-00169         .enable_dynamic_fifo = -1,
+-00170         .data_fifo_size = -1,
+-00171         .dev_rx_fifo_size = -1,
+-00172         .dev_nperio_tx_fifo_size = -1,
+-00173         .dev_perio_tx_fifo_size = {
+-00174                                    /* dev_perio_tx_fifo_size_1 */
+-00175                                    -1,
+-00176                                    -1,
+-00177                                    -1,
+-00178                                    -1,
+-00179                                    -1,
+-00180                                    -1,
+-00181                                    -1,
+-00182                                    -1,
+-00183                                    -1,
+-00184                                    -1,
+-00185                                    -1,
+-00186                                    -1,
+-00187                                    -1,
+-00188                                    -1,
+-00189                                    -1
+-00190                                    /* 15 */
+-00191                                    },
+-00192         .host_rx_fifo_size = -1,
+-00193         .host_nperio_tx_fifo_size = -1,
+-00194         .host_perio_tx_fifo_size = -1,
+-00195         .max_transfer_size = -1,
+-00196         .max_packet_count = -1,
+-00197         .host_channels = -1,
+-00198         .dev_endpoints = -1,
+-00199         .phy_type = -1,
+-00200         .phy_utmi_width = -1,
+-00201         .phy_ulpi_ddr = -1,
+-00202         .phy_ulpi_ext_vbus = -1,
+-00203         .i2c_enable = -1,
+-00204         .ulpi_fs_ls = -1,
+-00205         .ts_dline = -1,
+-00206         .en_multiple_tx_fifo = -1,
+-00207         .dev_tx_fifo_size = {
+-00208                              /* dev_tx_fifo_size */
+-00209                              -1,
+-00210                              -1,
+-00211                              -1,
+-00212                              -1,
+-00213                              -1,
+-00214                              -1,
+-00215                              -1,
+-00216                              -1,
+-00217                              -1,
+-00218                              -1,
+-00219                              -1,
+-00220                              -1,
+-00221                              -1,
+-00222                              -1,
+-00223                              -1
+-00224                              /* 15 */
+-00225                              },
+-00226         .thr_ctl = -1,
+-00227         .tx_thr_length = -1,
+-00228         .rx_thr_length = -1,
+-00229         .pti_enable = -1,
+-00230         .mpi_enable = -1,
+-00231         .lpm_enable = -1,
+-00232         .ic_usb_cap = -1,
+-00233         .ahb_thr_ratio = -1,
+-00234 };
+-00235 
+-00239 static ssize_t version_show(struct device_driver *dev, char *buf)
+-00240 {
+-00241         return snprintf(buf, sizeof(DWC_DRIVER_VERSION) + 2, "%s\n",
+-00242                         DWC_DRIVER_VERSION);
+-00243 }
+-00244 
+-00245 static DRIVER_ATTR(version, S_IRUGO, version_show, NULL);
+-00246 
+-00250 uint32_t g_dbg_lvl = 0;         /* OFF */
+-00251 
+-00255 static ssize_t dbg_level_show(struct device_driver *drv, char *buf)
+-00256 {
+-00257         return sprintf(buf, "0x%0x\n", g_dbg_lvl);
+-00258 }
+-00259 
+-00263 static ssize_t dbg_level_store(struct device_driver *drv, const char *buf,
+-00264                                size_t count)
+-00265 {
+-00266         g_dbg_lvl = simple_strtoul(buf, NULL, 16);
+-00267         return count;
+-00268 }
+-00269 
+-00270 static DRIVER_ATTR(debuglevel, S_IRUGO | S_IWUSR, dbg_level_show,
+-00271                    dbg_level_store);
+-00272 
+-00277 static int set_parameters(dwc_otg_core_if_t * core_if)
+-00278 {
+-00279         int retval = 0;
+-00280         int i;
+-00281 
+-00282         if (dwc_otg_module_params.otg_cap != -1) {
+-00283                 retval +=
+-00284                     dwc_otg_set_param_otg_cap(core_if,
+-00285                                               dwc_otg_module_params.otg_cap);
+-00286         }
+-00287         if (dwc_otg_module_params.dma_enable != -1) {
+-00288                 retval +=
+-00289                     dwc_otg_set_param_dma_enable(core_if,
+-00290                                                  dwc_otg_module_params.
+-00291                                                  dma_enable);
+-00292         }
+-00293         if (dwc_otg_module_params.dma_desc_enable != -1) {
+-00294                 retval +=
+-00295                     dwc_otg_set_param_dma_desc_enable(core_if,
+-00296                                                       dwc_otg_module_params.
+-00297                                                       dma_desc_enable);
+-00298         }
+-00299         if (dwc_otg_module_params.opt != -1) {
+-00300                 retval +=
+-00301                     dwc_otg_set_param_opt(core_if, dwc_otg_module_params.opt);
+-00302         }
+-00303         if (dwc_otg_module_params.dma_burst_size != -1) {
+-00304                 retval +=
+-00305                     dwc_otg_set_param_dma_burst_size(core_if,
+-00306                                                      dwc_otg_module_params.
+-00307                                                      dma_burst_size);
+-00308         }
+-00309         if (dwc_otg_module_params.host_support_fs_ls_low_power != -1) {
+-00310                 retval +=
+-00311                     dwc_otg_set_param_host_support_fs_ls_low_power(core_if,
+-00312                                                                    dwc_otg_module_params.
+-00313                                                                    host_support_fs_ls_low_power);
+-00314         }
+-00315         if (dwc_otg_module_params.enable_dynamic_fifo != -1) {
+-00316                 retval +=
+-00317                     dwc_otg_set_param_enable_dynamic_fifo(core_if,
+-00318                                                           dwc_otg_module_params.
+-00319                                                           enable_dynamic_fifo);
+-00320         }
+-00321         if (dwc_otg_module_params.data_fifo_size != -1) {
+-00322                 retval +=
+-00323                     dwc_otg_set_param_data_fifo_size(core_if,
+-00324                                                      dwc_otg_module_params.
+-00325                                                      data_fifo_size);
+-00326         }
+-00327         if (dwc_otg_module_params.dev_rx_fifo_size != -1) {
+-00328                 retval +=
+-00329                     dwc_otg_set_param_dev_rx_fifo_size(core_if,
+-00330                                                        dwc_otg_module_params.
+-00331                                                        dev_rx_fifo_size);
+-00332         }
+-00333         if (dwc_otg_module_params.dev_nperio_tx_fifo_size != -1) {
+-00334                 retval +=
+-00335                     dwc_otg_set_param_dev_nperio_tx_fifo_size(core_if,
+-00336                                                               dwc_otg_module_params.
+-00337                                                               dev_nperio_tx_fifo_size);
+-00338         }
+-00339         if (dwc_otg_module_params.host_rx_fifo_size != -1) {
+-00340                 retval +=
+-00341                     dwc_otg_set_param_host_rx_fifo_size(core_if,
+-00342                                                         dwc_otg_module_params.host_rx_fifo_size);
+-00343         }
+-00344         if (dwc_otg_module_params.host_nperio_tx_fifo_size != -1) {
+-00345                 retval +=
+-00346                     dwc_otg_set_param_host_nperio_tx_fifo_size(core_if,
+-00347                                                                dwc_otg_module_params.
+-00348                                                                host_nperio_tx_fifo_size);
+-00349         }
+-00350         if (dwc_otg_module_params.host_perio_tx_fifo_size != -1) {
+-00351                 retval +=
+-00352                     dwc_otg_set_param_host_perio_tx_fifo_size(core_if,
+-00353                                                               dwc_otg_module_params.
+-00354                                                               host_perio_tx_fifo_size);
+-00355         }
+-00356         if (dwc_otg_module_params.max_transfer_size != -1) {
+-00357                 retval +=
+-00358                     dwc_otg_set_param_max_transfer_size(core_if,
+-00359                                                         dwc_otg_module_params.
+-00360                                                         max_transfer_size);
+-00361         }
+-00362         if (dwc_otg_module_params.max_packet_count != -1) {
+-00363                 retval +=
+-00364                     dwc_otg_set_param_max_packet_count(core_if,
+-00365                                                        dwc_otg_module_params.
+-00366                                                        max_packet_count);
+-00367         }
+-00368         if (dwc_otg_module_params.host_channels != -1) {
+-00369                 retval +=
+-00370                     dwc_otg_set_param_host_channels(core_if,
+-00371                                                     dwc_otg_module_params.
+-00372                                                     host_channels);
+-00373         }
+-00374         if (dwc_otg_module_params.dev_endpoints != -1) {
+-00375                 retval +=
+-00376                     dwc_otg_set_param_dev_endpoints(core_if,
+-00377                                                     dwc_otg_module_params.
+-00378                                                     dev_endpoints);
+-00379         }
+-00380         if (dwc_otg_module_params.phy_type != -1) {
+-00381                 retval +=
+-00382                     dwc_otg_set_param_phy_type(core_if,
+-00383                                                dwc_otg_module_params.phy_type);
+-00384         }
+-00385         if (dwc_otg_module_params.speed != -1) {
+-00386                 retval +=
+-00387                     dwc_otg_set_param_speed(core_if,
+-00388                                             dwc_otg_module_params.speed);
+-00389         }
+-00390         if (dwc_otg_module_params.host_ls_low_power_phy_clk != -1) {
+-00391                 retval +=
+-00392                     dwc_otg_set_param_host_ls_low_power_phy_clk(core_if,
+-00393                                                                 dwc_otg_module_params.
+-00394                                                                 host_ls_low_power_phy_clk);
+-00395         }
+-00396         if (dwc_otg_module_params.phy_ulpi_ddr != -1) {
+-00397                 retval +=
+-00398                     dwc_otg_set_param_phy_ulpi_ddr(core_if,
+-00399                                                    dwc_otg_module_params.
+-00400                                                    phy_ulpi_ddr);
+-00401         }
+-00402         if (dwc_otg_module_params.phy_ulpi_ext_vbus != -1) {
+-00403                 retval +=
+-00404                     dwc_otg_set_param_phy_ulpi_ext_vbus(core_if,
+-00405                                                         dwc_otg_module_params.
+-00406                                                         phy_ulpi_ext_vbus);
+-00407         }
+-00408         if (dwc_otg_module_params.phy_utmi_width != -1) {
+-00409                 retval +=
+-00410                     dwc_otg_set_param_phy_utmi_width(core_if,
+-00411                                                      dwc_otg_module_params.
+-00412                                                      phy_utmi_width);
+-00413         }
+-00414         if (dwc_otg_module_params.ulpi_fs_ls != -1) {
+-00415                 retval +=
+-00416                     dwc_otg_set_param_ulpi_fs_ls(core_if, dwc_otg_module_params.ulpi_fs_ls);
+-00417         }
+-00418         if (dwc_otg_module_params.ts_dline != -1) {
+-00419                 retval +=
+-00420                     dwc_otg_set_param_ts_dline(core_if,
+-00421                                                dwc_otg_module_params.ts_dline);
+-00422         }
+-00423         if (dwc_otg_module_params.i2c_enable != -1) {
+-00424                 retval +=
+-00425                     dwc_otg_set_param_i2c_enable(core_if,
+-00426                                                  dwc_otg_module_params.
+-00427                                                  i2c_enable);
+-00428         }
+-00429         if (dwc_otg_module_params.en_multiple_tx_fifo != -1) {
+-00430                 retval +=
+-00431                     dwc_otg_set_param_en_multiple_tx_fifo(core_if,
+-00432                                                           dwc_otg_module_params.
+-00433                                                           en_multiple_tx_fifo);
+-00434         }
+-00435         for (i = 0; i < 15; i++) {
+-00436                 if (dwc_otg_module_params.dev_perio_tx_fifo_size[i] != -1) {
+-00437                         retval +=
+-00438                             dwc_otg_set_param_dev_perio_tx_fifo_size(core_if,
+-00439                                                                      dwc_otg_module_params.
+-00440                                                                      dev_perio_tx_fifo_size
+-00441                                                                      [i], i);
+-00442                 }
+-00443         }
+-00444 
+-00445         for (i = 0; i < 15; i++) {
+-00446                 if (dwc_otg_module_params.dev_tx_fifo_size[i] != -1) {
+-00447                         retval += dwc_otg_set_param_dev_tx_fifo_size(core_if,
+-00448                                                                      dwc_otg_module_params.
+-00449                                                                      dev_tx_fifo_size
+-00450                                                                      [i], i);
+-00451                 }
+-00452         }
+-00453         if (dwc_otg_module_params.thr_ctl != -1) {
+-00454                 retval +=
+-00455                     dwc_otg_set_param_thr_ctl(core_if,
+-00456                                               dwc_otg_module_params.thr_ctl);
+-00457         }
+-00458         if (dwc_otg_module_params.mpi_enable != -1) {
+-00459                 retval +=
+-00460                     dwc_otg_set_param_mpi_enable(core_if,
+-00461                                                  dwc_otg_module_params.
+-00462                                                  mpi_enable);
+-00463         }
+-00464         if (dwc_otg_module_params.pti_enable != -1) {
+-00465                 retval +=
+-00466                     dwc_otg_set_param_pti_enable(core_if,
+-00467                                                  dwc_otg_module_params.
+-00468                                                  pti_enable);
+-00469         }
+-00470         if (dwc_otg_module_params.lpm_enable != -1) {
+-00471                 retval +=
+-00472                     dwc_otg_set_param_lpm_enable(core_if,
+-00473                                                  dwc_otg_module_params.
+-00474                                                  lpm_enable);
+-00475         }
+-00476         if (dwc_otg_module_params.ic_usb_cap != -1) {
+-00477                 retval +=
+-00478                     dwc_otg_set_param_ic_usb_cap(core_if,
+-00479                                                  dwc_otg_module_params.
+-00480                                                  ic_usb_cap);
+-00481         }
+-00482         if (dwc_otg_module_params.tx_thr_length != -1) {
+-00483                 retval +=
+-00484                     dwc_otg_set_param_tx_thr_length(core_if,
+-00485                                                     dwc_otg_module_params.tx_thr_length);
+-00486         }
+-00487         if (dwc_otg_module_params.rx_thr_length != -1) {
+-00488                 retval +=
+-00489                     dwc_otg_set_param_rx_thr_length(core_if,
+-00490                                                     dwc_otg_module_params.
+-00491                                                     rx_thr_length);
+-00492         }
+-00493         if(dwc_otg_module_params.ahb_thr_ratio != -1) {
+-00494                 retval +=
+-00495                     dwc_otg_set_param_ahb_thr_ratio(core_if, dwc_otg_module_params.ahb_thr_ratio);
+-00496         }
+-00497         return retval;
+-00498 }
+-00499 
+-00504 static irqreturn_t dwc_otg_common_irq(int irq, void *dev)
+-00505 {
+-00506         dwc_otg_device_t *otg_dev = dev;
+-00507         int32_t retval = IRQ_NONE;
+-00508 
+-00509         retval = dwc_otg_handle_common_intr(otg_dev->core_if);
+-00510         if (retval != 0) {
+-00511                 S3C2410X_CLEAR_EINTPEND();
+-00512         }
+-00513         return IRQ_RETVAL(retval);
+-00514 }
+-00515 
+-00525 static void dwc_otg_driver_remove(
+-00526 #ifdef LM_INTERFACE
+-00527      struct lm_device *_dev
+-00528 #elif PCI_INTERFACE
+-00529      struct pci_dev *_dev
+-00530 #endif
+-00531 )
+-00532 
+-00533 {
+-00534 #ifdef LM_INTERFACE
+-00535         dwc_otg_device_t *otg_dev = lm_get_drvdata(_dev);
+-00536 #elif PCI_INTERFACE
+-00537         dwc_otg_device_t *otg_dev = pci_get_drvdata(_dev);
+-00538 #endif
+-00539 
+-00540 
+-00541         DWC_DEBUGPL(DBG_ANY, "%s(%p)\n", __func__, _dev);
+-00542 
+-00543         if (!otg_dev) {
+-00544                 /* Memory allocation for the dwc_otg_device failed. */
+-00545                 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev NULL!\n", __func__);
+-00546                 return;
+-00547         }
+-00548 #ifndef DWC_DEVICE_ONLY
+-00549         if (otg_dev->hcd) {
+-00550                 hcd_remove(_dev);
+-00551         } else {
+-00552                 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->hcd NULL!\n", __func__);
+-00553                 return;
+-00554         }
+-00555 #endif
+-00556 
+-00557 #ifndef DWC_HOST_ONLY
+-00558         if (otg_dev->pcd) {
+-00559                 pcd_remove(_dev);
+-00560         }
+-00561 #endif
+-00562         /*
+-00563          * Free the IRQ
+-00564          */
+-00565         if (otg_dev->common_irq_installed) {
+-00566                 free_irq(_dev->irq, otg_dev);
+-00567         }
+-00568 
+-00569         if (otg_dev->core_if) {
+-00570                 dwc_otg_cil_remove(otg_dev->core_if);
+-00571         }
+-00572 
+-00573         /*
+-00574          * Remove the device attributes
+-00575          */
+-00576         dwc_otg_attr_remove(_dev);
+-00577 
+-00578         /*
+-00579          * Return the memory.
+-00580          */
+-00581         if (otg_dev->base) {
+-00582                 iounmap(otg_dev->base);
+-00583         }
+-00584         dwc_free(otg_dev);
+-00585 
+-00586         /*
+-00587          * Clear the drvdata pointer.
+-00588          */
+-00589 #ifdef LM_INTERFACE
+-00590         lm_set_drvdata(_dev, 0);
+-00591 #elif PCI_INTERFACE
+-00592         release_mem_region(otg_dev->rsrc_start, otg_dev->rsrc_len);
+-00593         pci_set_drvdata(_dev, 0);
+-00594 #endif
+-00595 }
+-00596 
+-00608 static int dwc_otg_driver_probe(
+-00609 #ifdef LM_INTERFACE
+-00610 struct lm_device *_dev
+-00611 #elif PCI_INTERFACE
+-00612 struct pci_dev *_dev,  const struct pci_device_id *id
+-00613 #endif
+-00614 )
+-00615 {
+-00616         int retval = 0;
+-00617         dwc_otg_device_t *dwc_otg_device;
+-00618 
+-00619         dev_dbg(&_dev->dev, "dwc_otg_driver_probe(%p)\n", _dev);
+-00620 #ifdef LM_INTERFACE
+-00621         dev_dbg(&_dev->dev, "start=0x%08x\n", (unsigned)_dev->resource.start);
+-00622 #elif PCI_INTERFACE
+-00623         if (!id) {
+-00624         DWC_ERROR("Invalid pci_device_id %p", id);
+-00625                 return -EINVAL;
+-00626         }
+-00627 
+-00628         if (!_dev || (pci_enable_device(_dev) < 0)) {
+-00629                 DWC_ERROR("Invalid pci_device %p", _dev);
+-00630                 return -ENODEV;
+-00631         }
+-00632         dev_dbg(&_dev->dev, "start=0x%08x\n", (unsigned)pci_resource_start(_dev,0));
+-00633         /* other stuff needed as well? */
+-00634 
+-00635 #endif
+-00636 
+-00637 
+-00638         dwc_otg_device = dwc_alloc(sizeof(dwc_otg_device_t));
+-00639 
+-00640         if (!dwc_otg_device) {
+-00641                 dev_err(&_dev->dev, "kmalloc of dwc_otg_device failed\n");
+-00642                 retval = -ENOMEM;
+-00643                 goto fail;
+-00644         }
+-00645 
+-00646         memset(dwc_otg_device, 0, sizeof(*dwc_otg_device));
+-00647         dwc_otg_device->reg_offset = 0xFFFFFFFF;
+-00648 
+-00649         /*
+-00650          * Map the DWC_otg Core memory into virtual address space.
+-00651          */
+-00652 #ifdef LM_INTERFACE
+-00653         dwc_otg_device->base = ioremap(_dev->resource.start, SZ_256K);
+-00654 
+-00655         if (!dwc_otg_device->base) {
+-00656                 dev_err(&_dev->dev, "ioremap() failed\n");
+-00657                 retval = -ENOMEM;
+-00658                 goto fail;
+-00659         }
+-00660         dev_dbg(&_dev->dev, "base=0x%08x\n", (unsigned)dwc_otg_device->base);
+-00661 #elif PCI_INTERFACE
+-00662         _dev->current_state = PCI_D0;
+-00663         _dev->dev.power.power_state = PMSG_ON;
+-00664         
+-00665         if (!_dev->irq) {
+-00666                 DWC_ERROR("Found HC with no IRQ. Check BIOS/PCI %s setup!", pci_name(_dev));
+-00667                 retval = -ENODEV;
+-00668                 goto fail;
+-00669         }
+-00670 
+-00671         dwc_otg_device->rsrc_start = pci_resource_start(_dev,0);
+-00672         dwc_otg_device->rsrc_len = pci_resource_len(_dev,0);
+-00673         DWC_DEBUGPL(DBG_ANY,"PCI resource: start=%08x, len=%08x\n",
+-00674                     dwc_otg_device->rsrc_start,
+-00675                     dwc_otg_device->rsrc_len);
+-00676         if (!request_mem_region(dwc_otg_device->rsrc_start, dwc_otg_device->rsrc_len, "dwc_otg")) {
+-00677           dev_dbg(&_dev->dev, "error mapping memory\n");
+-00678           retval = -EFAULT;
+-00679           goto fail;
+-00680         }
+-00681 
+-00682         dwc_otg_device->base = ioremap_nocache(dwc_otg_device->rsrc_start, dwc_otg_device->rsrc_len);
+-00683         if (dwc_otg_device->base == NULL) {
+-00684                 dev_dbg(&_dev->dev, "error mapping memory\n");
+-00685                 retval = -EFAULT;
+-00686                 goto fail;
+-00687         }
+-00688         dev_dbg(&_dev->dev, "base=0x%p (before adjust) \n", dwc_otg_device->base);
+-00689         dwc_otg_device->base = (char *)dwc_otg_device->base;
+-00690         dev_dbg(&_dev->dev, "base=0x%p (after adjust) \n", dwc_otg_device->base);
+-00691         dev_dbg(&_dev->dev, "%s: mapped PA 0x%x to VA 0x%p\n", __func__,
+-00692                 (unsigned)dwc_otg_device->rsrc_start, dwc_otg_device->base);
+-00693         //
+-00694         pci_set_drvdata(_dev, dwc_otg_device); 
+-00695         pci_set_master(_dev);
+-00696 #endif
+-00697 
+-00698         /*
+-00699          * Initialize driver data to point to the global DWC_otg
+-00700          * Device structure.
+-00701          */
+-00702 #ifdef LM_INTERFACE
+-00703         lm_set_drvdata(_dev, dwc_otg_device);
+-00704 #endif
+-00705         dev_dbg(&_dev->dev, "dwc_otg_device=0x%p\n", dwc_otg_device);
+-00706 
+-00707         dwc_otg_device->core_if = dwc_otg_cil_init(dwc_otg_device->base);
+-00708         if (!dwc_otg_device->core_if) {
+-00709                 dev_err(&_dev->dev, "CIL initialization failed!\n");
+-00710                 retval = -ENOMEM;
+-00711                 goto fail;
+-00712         }
+-00713 
+-00714         /*
+-00715          * Attempt to ensure this device is really a DWC_otg Controller.
+-00716          * Read and verify the SNPSID register contents. The value should be
+-00717          * 0x45F42XXX, which corresponds to "OT2", as in "OTG version 2.XX".
+-00718          */
+-00719 
+-00720         if ((dwc_otg_get_gsnpsid(dwc_otg_device->core_if) & 0xFFFFF000) !=
+-00721             0x4F542000) {
+-00722                 dev_err(&_dev->dev, "Bad value for SNPSID: 0x%08x\n",
+-00723                         dwc_otg_get_gsnpsid(dwc_otg_device->core_if));
+-00724                 dwc_otg_cil_remove(dwc_otg_device->core_if);
+-00725                 dwc_free(dwc_otg_device);
+-00726                 retval = -EINVAL;
+-00727                 goto fail;
+-00728         }
+-00729 
+-00730         /*
+-00731          * Validate parameter values.
+-00732          */
+-00733         if (set_parameters(dwc_otg_device->core_if)) {
+-00734                 dwc_otg_cil_remove(dwc_otg_device->core_if);
+-00735                 retval = -EINVAL;
+-00736                 goto fail;
+-00737         }
+-00738 
+-00739         /*
+-00740          * Create Device Attributes in sysfs
+-00741          */
+-00742         dwc_otg_attr_create(_dev);
+-00743 
+-00744         /*
+-00745          * Disable the global interrupt until all the interrupt
+-00746          * handlers are installed.
+-00747          */
+-00748         dwc_otg_disable_global_interrupts(dwc_otg_device->core_if);
+-00749 
+-00750         /*
+-00751          * Install the interrupt handler for the common interrupts before
+-00752          * enabling common interrupts in core_init below.
+-00753          */
+-00754         DWC_DEBUGPL(DBG_CIL, "registering (common) handler for irq%d\n",
+-00755                     _dev->irq);
+-00756         retval = request_irq(_dev->irq, dwc_otg_common_irq,
+-00757                              SA_SHIRQ, "dwc_otg", dwc_otg_device);
+-00758         if (retval) {
+-00759                 DWC_ERROR("request of irq%d failed\n", _dev->irq);
+-00760                 retval = -EBUSY;
+-00761                 goto fail;
+-00762         } else {
+-00763                 dwc_otg_device->common_irq_installed = 1;
+-00764         }
+-00765 
+-00766 #ifdef LM_INTERFACE
+-00767         set_irq_type(_dev->irq, IRQT_LOW);
+-00768 #endif
+-00769 
+-00770         /*
+-00771          * Initialize the DWC_otg core.
+-00772          */
+-00773         dwc_otg_core_init(dwc_otg_device->core_if);
+-00774 
+-00775 #ifndef DWC_HOST_ONLY
+-00776         /*
+-00777          * Initialize the PCD
+-00778          */
+-00779         retval = pcd_init(_dev);
+-00780         if (retval != 0) {
+-00781                 DWC_ERROR("pcd_init failed\n");
+-00782                 dwc_otg_device->pcd = NULL;
+-00783                 goto fail;
+-00784         }
+-00785 #endif
+-00786 #ifndef DWC_DEVICE_ONLY
+-00787         /*
+-00788          * Initialize the HCD
+-00789          */
+-00790         retval = hcd_init(_dev);
+-00791         if (retval != 0) {
+-00792                 DWC_ERROR("hcd_init failed\n");
+-00793                 dwc_otg_device->hcd = NULL;
+-00794                 goto fail;
+-00795         }
+-00796 #endif
+-00797 #ifdef PCI_INTERFACE    
+-00798         pci_set_drvdata(_dev, dwc_otg_device);
+-00799 #endif
+-00800 
+-00801         /*
+-00802          * Enable the global interrupt after all the interrupt
+-00803          * handlers are installed.
+-00804          */
+-00805         dwc_otg_enable_global_interrupts(dwc_otg_device->core_if);
+-00806 
+-00807         return 0;
+-00808 
+-00809       fail:
+-00810         dwc_otg_driver_remove(_dev);
+-00811         return retval;
+-00812 }
+-00813 
+-00825 #ifdef LM_INTERFACE
+-00826 static struct lm_driver dwc_otg_driver = {
+-00827         .drv = {
+-00828                 .name = (char *)dwc_driver_name,
+-00829                 },
+-00830         .probe = dwc_otg_driver_probe,
+-00831         .remove = dwc_otg_driver_remove,
+-00832 };
+-00833 #elif PCI_INTERFACE
+-00834 static const struct pci_device_id pci_ids[] = { {
+-00835         PCI_DEVICE(0x16c3, 0xabcd),
+-00836         .driver_data = (unsigned long) 0xdeadbeef,
+-00837         }, { /* end: all zeroes */ }
+-00838 };
+-00839 MODULE_DEVICE_TABLE(pci, pci_ids);
+-00840 
+-00841 /* pci driver glue; this is a "new style" PCI driver module */
+-00842 static struct pci_driver dwc_otg_driver = {
+-00843         .name =         "dwc_otg",
+-00844         .id_table =     pci_ids,
+-00845 
+-00846         .probe =        dwc_otg_driver_probe,
+-00847         .remove =       dwc_otg_driver_remove,
+-00848 
+-00849         .driver = {
+-00850                 .name   = (char*)dwc_driver_name,
+-00851         },
+-00852 };
+-00853 #endif
+-00854 
+-00855 
+-00866 static int __init dwc_otg_driver_init(void)
+-00867 {
+-00868         int retval = 0;
+-00869         int error;
+-00870         printk(KERN_INFO "%s: version %s\n", dwc_driver_name,
+-00871                DWC_DRIVER_VERSION);
+-00872 #ifdef LM_INTERFACE
+-00873         retval = lm_driver_register(&dwc_otg_driver);
+-00874 #elif PCI_INTERFACE
+-00875         retval = pci_register_driver(&dwc_otg_driver);
+-00876 #endif
+-00877         if (retval < 0) {
+-00878                 printk(KERN_ERR "%s retval=%d\n", __func__, retval);
+-00879                 return retval;
+-00880         }
+-00881 #ifdef LM_INTERFACE
+-00882         error = driver_create_file(&dwc_otg_driver.drv, &driver_attr_version);
+-00883         error = driver_create_file(&dwc_otg_driver.drv, &driver_attr_debuglevel);
+-00884 #elif PCI_INTERFACE
+-00885         error = driver_create_file(&dwc_otg_driver.driver, &driver_attr_version);
+-00886         error = driver_create_file(&dwc_otg_driver.driver, &driver_attr_debuglevel);
+-00887 #endif
+-00888         return retval;
+-00889 }
+-00890 
+-00891 module_init(dwc_otg_driver_init);
+-00892 
+-00899 static void __exit dwc_otg_driver_cleanup(void)
+-00900 {
+-00901         printk(KERN_DEBUG "dwc_otg_driver_cleanup()\n");
+-00902 
+-00903 #ifdef LM_INTERFACE
+-00904         driver_remove_file(&dwc_otg_driver.drv, &driver_attr_debuglevel);
+-00905         driver_remove_file(&dwc_otg_driver.drv, &driver_attr_version);
+-00906         lm_driver_unregister(&dwc_otg_driver);
+-00907 #elif PCI_INTERFACE
+-00908         driver_remove_file(&dwc_otg_driver.driver, &driver_attr_debuglevel);
+-00909         driver_remove_file(&dwc_otg_driver.driver, &driver_attr_version);
+-00910         pci_unregister_driver(&dwc_otg_driver);
+-00911 #endif
+-00912 
+-00913         printk(KERN_INFO "%s module removed\n", dwc_driver_name);
+-00914 }
+-00915 module_exit(dwc_otg_driver_cleanup);
+-00916 
+-00917 MODULE_DESCRIPTION(DWC_DRIVER_DESC);
+-00918 MODULE_AUTHOR("Synopsys Inc.");
+-00919 MODULE_LICENSE("GPL");
+-00920 
+-00921 module_param_named(otg_cap, dwc_otg_module_params.otg_cap, int, 0444);
+-00922 MODULE_PARM_DESC(otg_cap, "OTG Capabilities 0=HNP&SRP 1=SRP Only 2=None");
+-00923 module_param_named(opt, dwc_otg_module_params.opt, int, 0444);
+-00924 MODULE_PARM_DESC(opt, "OPT Mode");
+-00925 module_param_named(dma_enable, dwc_otg_module_params.dma_enable, int, 0444);
+-00926 MODULE_PARM_DESC(dma_enable, "DMA Mode 0=Slave 1=DMA enabled");
+-00927 
+-00928 module_param_named(dma_desc_enable, dwc_otg_module_params.dma_desc_enable, int,
+-00929                    0444);
+-00930 MODULE_PARM_DESC(dma_desc_enable,
+-00931                  "DMA Desc Mode 0=Address DMA 1=DMA Descriptor enabled");
+-00932 
+-00933 module_param_named(dma_burst_size, dwc_otg_module_params.dma_burst_size, int,
+-00934                    0444);
+-00935 MODULE_PARM_DESC(dma_burst_size,
+-00936                  "DMA Burst Size 1, 4, 8, 16, 32, 64, 128, 256");
+-00937 module_param_named(speed, dwc_otg_module_params.speed, int, 0444);
+-00938 MODULE_PARM_DESC(speed, "Speed 0=High Speed 1=Full Speed");
+-00939 module_param_named(host_support_fs_ls_low_power,
+-00940                    dwc_otg_module_params.host_support_fs_ls_low_power, int,
+-00941                    0444);
+-00942 MODULE_PARM_DESC(host_support_fs_ls_low_power,
+-00943                  "Support Low Power w/FS or LS 0=Support 1=Don't Support");
+-00944 module_param_named(host_ls_low_power_phy_clk,
+-00945                    dwc_otg_module_params.host_ls_low_power_phy_clk, int, 0444);
+-00946 MODULE_PARM_DESC(host_ls_low_power_phy_clk,
+-00947                  "Low Speed Low Power Clock 0=48Mhz 1=6Mhz");
+-00948 module_param_named(enable_dynamic_fifo,
+-00949                    dwc_otg_module_params.enable_dynamic_fifo, int, 0444);
+-00950 MODULE_PARM_DESC(enable_dynamic_fifo, "0=cC Setting 1=Allow Dynamic Sizing");
+-00951 module_param_named(data_fifo_size, dwc_otg_module_params.data_fifo_size, int,
+-00952                    0444);
+-00953 MODULE_PARM_DESC(data_fifo_size,
+-00954                  "Total number of words in the data FIFO memory 32-32768");
+-00955 module_param_named(dev_rx_fifo_size, dwc_otg_module_params.dev_rx_fifo_size,
+-00956                    int, 0444);
+-00957 MODULE_PARM_DESC(dev_rx_fifo_size, "Number of words in the Rx FIFO 16-32768");
+-00958 module_param_named(dev_nperio_tx_fifo_size,
+-00959                    dwc_otg_module_params.dev_nperio_tx_fifo_size, int, 0444);
+-00960 MODULE_PARM_DESC(dev_nperio_tx_fifo_size,
+-00961                  "Number of words in the non-periodic Tx FIFO 16-32768");
+-00962 module_param_named(dev_perio_tx_fifo_size_1,
+-00963                    dwc_otg_module_params.dev_perio_tx_fifo_size[0], int, 0444);
+-00964 MODULE_PARM_DESC(dev_perio_tx_fifo_size_1,
+-00965                  "Number of words in the periodic Tx FIFO 4-768");
+-00966 module_param_named(dev_perio_tx_fifo_size_2,
+-00967                    dwc_otg_module_params.dev_perio_tx_fifo_size[1], int, 0444);
+-00968 MODULE_PARM_DESC(dev_perio_tx_fifo_size_2,
+-00969                  "Number of words in the periodic Tx FIFO 4-768");
+-00970 module_param_named(dev_perio_tx_fifo_size_3,
+-00971                    dwc_otg_module_params.dev_perio_tx_fifo_size[2], int, 0444);
+-00972 MODULE_PARM_DESC(dev_perio_tx_fifo_size_3,
+-00973                  "Number of words in the periodic Tx FIFO 4-768");
+-00974 module_param_named(dev_perio_tx_fifo_size_4,
+-00975                    dwc_otg_module_params.dev_perio_tx_fifo_size[3], int, 0444);
+-00976 MODULE_PARM_DESC(dev_perio_tx_fifo_size_4,
+-00977                  "Number of words in the periodic Tx FIFO 4-768");
+-00978 module_param_named(dev_perio_tx_fifo_size_5,
+-00979                    dwc_otg_module_params.dev_perio_tx_fifo_size[4], int, 0444);
+-00980 MODULE_PARM_DESC(dev_perio_tx_fifo_size_5,
+-00981                  "Number of words in the periodic Tx FIFO 4-768");
+-00982 module_param_named(dev_perio_tx_fifo_size_6,
+-00983                    dwc_otg_module_params.dev_perio_tx_fifo_size[5], int, 0444);
+-00984 MODULE_PARM_DESC(dev_perio_tx_fifo_size_6,
+-00985                  "Number of words in the periodic Tx FIFO 4-768");
+-00986 module_param_named(dev_perio_tx_fifo_size_7,
+-00987                    dwc_otg_module_params.dev_perio_tx_fifo_size[6], int, 0444);
+-00988 MODULE_PARM_DESC(dev_perio_tx_fifo_size_7,
+-00989                  "Number of words in the periodic Tx FIFO 4-768");
+-00990 module_param_named(dev_perio_tx_fifo_size_8,
+-00991                    dwc_otg_module_params.dev_perio_tx_fifo_size[7], int, 0444);
+-00992 MODULE_PARM_DESC(dev_perio_tx_fifo_size_8,
+-00993                  "Number of words in the periodic Tx FIFO 4-768");
+-00994 module_param_named(dev_perio_tx_fifo_size_9,
+-00995                    dwc_otg_module_params.dev_perio_tx_fifo_size[8], int, 0444);
+-00996 MODULE_PARM_DESC(dev_perio_tx_fifo_size_9,
+-00997                  "Number of words in the periodic Tx FIFO 4-768");
+-00998 module_param_named(dev_perio_tx_fifo_size_10,
+-00999                    dwc_otg_module_params.dev_perio_tx_fifo_size[9], int, 0444);
+-01000 MODULE_PARM_DESC(dev_perio_tx_fifo_size_10,
+-01001                  "Number of words in the periodic Tx FIFO 4-768");
+-01002 module_param_named(dev_perio_tx_fifo_size_11,
+-01003                    dwc_otg_module_params.dev_perio_tx_fifo_size[10], int, 0444);
+-01004 MODULE_PARM_DESC(dev_perio_tx_fifo_size_11,
+-01005                  "Number of words in the periodic Tx FIFO 4-768");
+-01006 module_param_named(dev_perio_tx_fifo_size_12,
+-01007                    dwc_otg_module_params.dev_perio_tx_fifo_size[11], int, 0444);
+-01008 MODULE_PARM_DESC(dev_perio_tx_fifo_size_12,
+-01009                  "Number of words in the periodic Tx FIFO 4-768");
+-01010 module_param_named(dev_perio_tx_fifo_size_13,
+-01011                    dwc_otg_module_params.dev_perio_tx_fifo_size[12], int, 0444);
+-01012 MODULE_PARM_DESC(dev_perio_tx_fifo_size_13,
+-01013                  "Number of words in the periodic Tx FIFO 4-768");
+-01014 module_param_named(dev_perio_tx_fifo_size_14,
+-01015                    dwc_otg_module_params.dev_perio_tx_fifo_size[13], int, 0444);
+-01016 MODULE_PARM_DESC(dev_perio_tx_fifo_size_14,
+-01017                  "Number of words in the periodic Tx FIFO 4-768");
+-01018 module_param_named(dev_perio_tx_fifo_size_15,
+-01019                    dwc_otg_module_params.dev_perio_tx_fifo_size[14], int, 0444);
+-01020 MODULE_PARM_DESC(dev_perio_tx_fifo_size_15,
+-01021                  "Number of words in the periodic Tx FIFO 4-768");
+-01022 module_param_named(host_rx_fifo_size, dwc_otg_module_params.host_rx_fifo_size,
+-01023                    int, 0444);
+-01024 MODULE_PARM_DESC(host_rx_fifo_size, "Number of words in the Rx FIFO 16-32768");
+-01025 module_param_named(host_nperio_tx_fifo_size,
+-01026                    dwc_otg_module_params.host_nperio_tx_fifo_size, int, 0444);
+-01027 MODULE_PARM_DESC(host_nperio_tx_fifo_size,
+-01028                  "Number of words in the non-periodic Tx FIFO 16-32768");
+-01029 module_param_named(host_perio_tx_fifo_size,
+-01030                    dwc_otg_module_params.host_perio_tx_fifo_size, int, 0444);
+-01031 MODULE_PARM_DESC(host_perio_tx_fifo_size,
+-01032                  "Number of words in the host periodic Tx FIFO 16-32768");
+-01033 module_param_named(max_transfer_size, dwc_otg_module_params.max_transfer_size,
+-01034                    int, 0444);
+-01036 MODULE_PARM_DESC(max_transfer_size,
+-01037                  "The maximum transfer size supported in bytes 2047-65535");
+-01038 module_param_named(max_packet_count, dwc_otg_module_params.max_packet_count,
+-01039                    int, 0444);
+-01040 MODULE_PARM_DESC(max_packet_count,
+-01041                  "The maximum number of packets in a transfer 15-511");
+-01042 module_param_named(host_channels, dwc_otg_module_params.host_channels, int,
+-01043                    0444);
+-01044 MODULE_PARM_DESC(host_channels,
+-01045                  "The number of host channel registers to use 1-16");
+-01046 module_param_named(dev_endpoints, dwc_otg_module_params.dev_endpoints, int,
+-01047                    0444);
+-01048 MODULE_PARM_DESC(dev_endpoints,
+-01049                  "The number of endpoints in addition to EP0 available for device mode 1-15");
+-01050 module_param_named(phy_type, dwc_otg_module_params.phy_type, int, 0444);
+-01051 MODULE_PARM_DESC(phy_type, "0=Reserved 1=UTMI+ 2=ULPI");
+-01052 module_param_named(phy_utmi_width, dwc_otg_module_params.phy_utmi_width, int,
+-01053                    0444);
+-01054 MODULE_PARM_DESC(phy_utmi_width, "Specifies the UTMI+ Data Width 8 or 16 bits");
+-01055 module_param_named(phy_ulpi_ddr, dwc_otg_module_params.phy_ulpi_ddr, int, 0444);
+-01056 MODULE_PARM_DESC(phy_ulpi_ddr,
+-01057                  "ULPI at double or single data rate 0=Single 1=Double");
+-01058 module_param_named(phy_ulpi_ext_vbus, dwc_otg_module_params.phy_ulpi_ext_vbus,
+-01059                    int, 0444);
+-01060 MODULE_PARM_DESC(phy_ulpi_ext_vbus,
+-01061                  "ULPI PHY using internal or external vbus 0=Internal");
+-01062 module_param_named(i2c_enable, dwc_otg_module_params.i2c_enable, int, 0444);
+-01063 MODULE_PARM_DESC(i2c_enable, "FS PHY Interface");
+-01064 module_param_named(ulpi_fs_ls, dwc_otg_module_params.ulpi_fs_ls, int, 0444);
+-01065 MODULE_PARM_DESC(ulpi_fs_ls, "ULPI PHY FS/LS mode only");
+-01066 module_param_named(ts_dline, dwc_otg_module_params.ts_dline, int, 0444);
+-01067 MODULE_PARM_DESC(ts_dline, "Term select Dline pulsing for all PHYs");
+-01068 module_param_named(debug, g_dbg_lvl, int, 0444);
+-01069 MODULE_PARM_DESC(debug, "");
+-01070 
+-01071 module_param_named(en_multiple_tx_fifo,
+-01072                    dwc_otg_module_params.en_multiple_tx_fifo, int, 0444);
+-01073 MODULE_PARM_DESC(en_multiple_tx_fifo,
+-01074                  "Dedicated Non Periodic Tx FIFOs 0=disabled 1=enabled");
+-01075 module_param_named(dev_tx_fifo_size_1,
+-01076                    dwc_otg_module_params.dev_tx_fifo_size[0], int, 0444);
+-01077 MODULE_PARM_DESC(dev_tx_fifo_size_1, "Number of words in the Tx FIFO 4-768");
+-01078 module_param_named(dev_tx_fifo_size_2,
+-01079                    dwc_otg_module_params.dev_tx_fifo_size[1], int, 0444);
+-01080 MODULE_PARM_DESC(dev_tx_fifo_size_2, "Number of words in the Tx FIFO 4-768");
+-01081 module_param_named(dev_tx_fifo_size_3,
+-01082                    dwc_otg_module_params.dev_tx_fifo_size[2], int, 0444);
+-01083 MODULE_PARM_DESC(dev_tx_fifo_size_3, "Number of words in the Tx FIFO 4-768");
+-01084 module_param_named(dev_tx_fifo_size_4,
+-01085                    dwc_otg_module_params.dev_tx_fifo_size[3], int, 0444);
+-01086 MODULE_PARM_DESC(dev_tx_fifo_size_4, "Number of words in the Tx FIFO 4-768");
+-01087 module_param_named(dev_tx_fifo_size_5,
+-01088                    dwc_otg_module_params.dev_tx_fifo_size[4], int, 0444);
+-01089 MODULE_PARM_DESC(dev_tx_fifo_size_5, "Number of words in the Tx FIFO 4-768");
+-01090 module_param_named(dev_tx_fifo_size_6,
+-01091                    dwc_otg_module_params.dev_tx_fifo_size[5], int, 0444);
+-01092 MODULE_PARM_DESC(dev_tx_fifo_size_6, "Number of words in the Tx FIFO 4-768");
+-01093 module_param_named(dev_tx_fifo_size_7,
+-01094                    dwc_otg_module_params.dev_tx_fifo_size[6], int, 0444);
+-01095 MODULE_PARM_DESC(dev_tx_fifo_size_7, "Number of words in the Tx FIFO 4-768");
+-01096 module_param_named(dev_tx_fifo_size_8,
+-01097                    dwc_otg_module_params.dev_tx_fifo_size[7], int, 0444);
+-01098 MODULE_PARM_DESC(dev_tx_fifo_size_8, "Number of words in the Tx FIFO 4-768");
+-01099 module_param_named(dev_tx_fifo_size_9,
+-01100                    dwc_otg_module_params.dev_tx_fifo_size[8], int, 0444);
+-01101 MODULE_PARM_DESC(dev_tx_fifo_size_9, "Number of words in the Tx FIFO 4-768");
+-01102 module_param_named(dev_tx_fifo_size_10,
+-01103                    dwc_otg_module_params.dev_tx_fifo_size[9], int, 0444);
+-01104 MODULE_PARM_DESC(dev_tx_fifo_size_10, "Number of words in the Tx FIFO 4-768");
+-01105 module_param_named(dev_tx_fifo_size_11,
+-01106                    dwc_otg_module_params.dev_tx_fifo_size[10], int, 0444);
+-01107 MODULE_PARM_DESC(dev_tx_fifo_size_11, "Number of words in the Tx FIFO 4-768");
+-01108 module_param_named(dev_tx_fifo_size_12,
+-01109                    dwc_otg_module_params.dev_tx_fifo_size[11], int, 0444);
+-01110 MODULE_PARM_DESC(dev_tx_fifo_size_12, "Number of words in the Tx FIFO 4-768");
+-01111 module_param_named(dev_tx_fifo_size_13,
+-01112                    dwc_otg_module_params.dev_tx_fifo_size[12], int, 0444);
+-01113 MODULE_PARM_DESC(dev_tx_fifo_size_13, "Number of words in the Tx FIFO 4-768");
+-01114 module_param_named(dev_tx_fifo_size_14,
+-01115                    dwc_otg_module_params.dev_tx_fifo_size[13], int, 0444);
+-01116 MODULE_PARM_DESC(dev_tx_fifo_size_14, "Number of words in the Tx FIFO 4-768");
+-01117 module_param_named(dev_tx_fifo_size_15,
+-01118                    dwc_otg_module_params.dev_tx_fifo_size[14], int, 0444);
+-01119 MODULE_PARM_DESC(dev_tx_fifo_size_15, "Number of words in the Tx FIFO 4-768");
+-01120 
+-01121 module_param_named(thr_ctl, dwc_otg_module_params.thr_ctl, int, 0444);
+-01122 MODULE_PARM_DESC(thr_ctl,
+-01123                  "Thresholding enable flag bit 0 - non ISO Tx thr., 1 - ISO Tx thr., 2 - Rx thr.- bit 0=disabled 1=enabled");
+-01124 module_param_named(tx_thr_length, dwc_otg_module_params.tx_thr_length, int,
+-01125                    0444);
+-01126 MODULE_PARM_DESC(tx_thr_length, "Tx Threshold length in 32 bit DWORDs");
+-01127 module_param_named(rx_thr_length, dwc_otg_module_params.rx_thr_length, int,
+-01128                    0444);
+-01129 MODULE_PARM_DESC(rx_thr_length, "Rx Threshold length in 32 bit DWORDs");
+-01130 
+-01131 module_param_named(pti_enable, dwc_otg_module_params.pti_enable, int, 0444);
+-01132 module_param_named(mpi_enable, dwc_otg_module_params.mpi_enable, int, 0444);
+-01133 module_param_named(lpm_enable, dwc_otg_module_params.lpm_enable, int, 0444);
+-01134 MODULE_PARM_DESC(lpm_enable, "LPM Enable 0=LPM Disabled 1=LPM Enabled");
+-01135 module_param_named(ic_usb_cap, dwc_otg_module_params.ic_usb_cap, int, 0444);
+-01136 MODULE_PARM_DESC(ic_usb_cap,
+-01137                  "IC_USB Capability 0=IC_USB Disabled 1=IC_USB Enabled");
+-01138 module_param_named(ahb_thr_ratio, dwc_otg_module_params.ahb_thr_ratio, int, 0444);
+-01139 MODULE_PARM_DESC(ahb_thr_ratio, "AHB Threshold Ratio");
+-01140 
+-
    Generated on Tue May 5 02:22:48 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++
    Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
    ++

    dwc_otg_driver.c

    Go to the documentation of this file.
    00001 /* ==========================================================================
++00002  * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_driver.c $
++00003  * $Revision: #91 $
++00004  * $Date: 2011/10/24 $
++00005  * $Change: 1871159 $
++00006  *
++00007  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
++00008  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
++00009  * otherwise expressly agreed to in writing between Synopsys and you.
++00010  *
++00011  * The Software IS NOT an item of Licensed Software or Licensed Product under
++00012  * any End User Software License Agreement or Agreement for Licensed Product
++00013  * with Synopsys or any supplement thereto. You are permitted to use and
++00014  * redistribute this Software in source and binary forms, with or without
++00015  * modification, provided that redistributions of source code must retain this
++00016  * notice. You may not view, use, disclose, copy or distribute this file or
++00017  * any information contained herein except pursuant to this license grant from
++00018  * Synopsys. If you do not agree with this notice, including the disclaimer
++00019  * below, then you are not authorized to use the Software.
++00020  *
++00021  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
++00022  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++00023  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++00024  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
++00025  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++00026  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
++00027  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
++00028  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
++00029  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
++00030  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
++00031  * DAMAGE.
++00032  * ========================================================================== */
++00033 
++00051 #include "dwc_otg_os_dep.h"
++00052 #include "dwc_os.h"
++00053 #include "dwc_otg_dbg.h"
++00054 #include "dwc_otg_driver.h"
++00055 #include "dwc_otg_attr.h"
++00056 #include "dwc_otg_core_if.h"
++00057 #include "dwc_otg_pcd_if.h"
++00058 #include "dwc_otg_hcd_if.h"
++00059 
++00060 #define DWC_DRIVER_VERSION      "2.94a 27-OCT-2011"
++00061 #define DWC_DRIVER_DESC         "HS OTG USB Controller driver"
++00062 
++00063 static const char dwc_driver_name[] = "dwc_otg";
++00064 
++00065 extern int pcd_init(
++00066 #ifdef LM_INTERFACE
++00067                            struct lm_device *_dev
++00068 #elif  defined(PCI_INTERFACE)
++00069                            struct pci_dev *_dev
++00070 #endif
++00071     );
++00072 extern int hcd_init(
++00073 #ifdef LM_INTERFACE
++00074                            struct lm_device *_dev
++00075 #elif  defined(PCI_INTERFACE)
++00076                            struct pci_dev *_dev
++00077 #endif
++00078     );
++00079 
++00080 extern int pcd_remove(
++00081 #ifdef LM_INTERFACE
++00082                              struct lm_device *_dev
++00083 #elif  defined(PCI_INTERFACE)
++00084                              struct pci_dev *_dev
++00085 #endif
++00086     );
++00087 
++00088 extern void hcd_remove(
++00089 #ifdef LM_INTERFACE
++00090                               struct lm_device *_dev
++00091 #elif  defined(PCI_INTERFACE)
++00092                               struct pci_dev *_dev
++00093 #endif
++00094     );
++00095 
++00096 extern void dwc_otg_adp_start(dwc_otg_core_if_t * core_if, uint8_t is_host);
++00097 
++00098 /*-------------------------------------------------------------------------*/
++00099 /* Encapsulate the module parameter settings */
++00100 
++00101 struct dwc_otg_driver_module_params {
++00102         int32_t opt;
++00103         int32_t otg_cap;
++00104         int32_t dma_enable;
++00105         int32_t dma_desc_enable;
++00106         int32_t dma_burst_size;
++00107         int32_t speed;
++00108         int32_t host_support_fs_ls_low_power;
++00109         int32_t host_ls_low_power_phy_clk;
++00110         int32_t enable_dynamic_fifo;
++00111         int32_t data_fifo_size;
++00112         int32_t dev_rx_fifo_size;
++00113         int32_t dev_nperio_tx_fifo_size;
++00114         uint32_t dev_perio_tx_fifo_size[MAX_PERIO_FIFOS];
++00115         int32_t host_rx_fifo_size;
++00116         int32_t host_nperio_tx_fifo_size;
++00117         int32_t host_perio_tx_fifo_size;
++00118         int32_t max_transfer_size;
++00119         int32_t max_packet_count;
++00120         int32_t host_channels;
++00121         int32_t dev_endpoints;
++00122         int32_t phy_type;
++00123         int32_t phy_utmi_width;
++00124         int32_t phy_ulpi_ddr;
++00125         int32_t phy_ulpi_ext_vbus;
++00126         int32_t i2c_enable;
++00127         int32_t ulpi_fs_ls;
++00128         int32_t ts_dline;
++00129         int32_t en_multiple_tx_fifo;
++00130         uint32_t dev_tx_fifo_size[MAX_TX_FIFOS];
++00131         uint32_t thr_ctl;
++00132         uint32_t tx_thr_length;
++00133         uint32_t rx_thr_length;
++00134         int32_t pti_enable;
++00135         int32_t mpi_enable;
++00136         int32_t lpm_enable;
++00137         int32_t ic_usb_cap;
++00138         int32_t ahb_thr_ratio;
++00139         int32_t power_down;
++00140         int32_t reload_ctl;
++00141         int32_t dev_out_nak;
++00142         int32_t cont_on_bna;
++00143         int32_t ahb_single;
++00144         int32_t otg_ver;
++00145         int32_t adp_enable;
++00146 };
++00147 
++00148 static struct dwc_otg_driver_module_params dwc_otg_module_params = {
++00149         .opt = -1,
++00150         .otg_cap = -1,
++00151         .dma_enable = -1,
++00152         .dma_desc_enable = -1,
++00153         .dma_burst_size = -1,
++00154         .speed = -1,
++00155         .host_support_fs_ls_low_power = -1,
++00156         .host_ls_low_power_phy_clk = -1,
++00157         .enable_dynamic_fifo = -1,
++00158         .data_fifo_size = -1,
++00159         .dev_rx_fifo_size = -1,
++00160         .dev_nperio_tx_fifo_size = -1,
++00161         .dev_perio_tx_fifo_size = {
++00162                                    /* dev_perio_tx_fifo_size_1 */
++00163                                    -1,
++00164                                    -1,
++00165                                    -1,
++00166                                    -1,
++00167                                    -1,
++00168                                    -1,
++00169                                    -1,
++00170                                    -1,
++00171                                    -1,
++00172                                    -1,
++00173                                    -1,
++00174                                    -1,
++00175                                    -1,
++00176                                    -1,
++00177                                    -1
++00178                                    /* 15 */
++00179                                    },
++00180         .host_rx_fifo_size = -1,
++00181         .host_nperio_tx_fifo_size = -1,
++00182         .host_perio_tx_fifo_size = -1,
++00183         .max_transfer_size = -1,
++00184         .max_packet_count = -1,
++00185         .host_channels = -1,
++00186         .dev_endpoints = -1,
++00187         .phy_type = -1,
++00188         .phy_utmi_width = -1,
++00189         .phy_ulpi_ddr = -1,
++00190         .phy_ulpi_ext_vbus = -1,
++00191         .i2c_enable = -1,
++00192         .ulpi_fs_ls = -1,
++00193         .ts_dline = -1,
++00194         .en_multiple_tx_fifo = -1,
++00195         .dev_tx_fifo_size = {
++00196                              /* dev_tx_fifo_size */
++00197                              -1,
++00198                              -1,
++00199                              -1,
++00200                              -1,
++00201                              -1,
++00202                              -1,
++00203                              -1,
++00204                              -1,
++00205                              -1,
++00206                              -1,
++00207                              -1,
++00208                              -1,
++00209                              -1,
++00210                              -1,
++00211                              -1
++00212                              /* 15 */
++00213                              },
++00214         .thr_ctl = -1,
++00215         .tx_thr_length = -1,
++00216         .rx_thr_length = -1,
++00217         .pti_enable = -1,
++00218         .mpi_enable = -1,
++00219         .lpm_enable = -1,
++00220         .ic_usb_cap = -1,
++00221         .ahb_thr_ratio = -1,
++00222         .power_down = -1,
++00223         .reload_ctl = -1,
++00224         .dev_out_nak = -1,
++00225         .cont_on_bna = -1,
++00226         .ahb_single = -1,
++00227         .otg_ver = -1,
++00228         .adp_enable = -1,
++00229 };
++00230 
++00234 static ssize_t version_show(struct device_driver *dev, char *buf)
++00235 {
++00236         return snprintf(buf, sizeof(DWC_DRIVER_VERSION) + 2, "%s\n",
++00237                         DWC_DRIVER_VERSION);
++00238 }
++00239 
++00240 static DRIVER_ATTR(version, S_IRUGO, version_show, NULL);
++00241 
++00245 uint32_t g_dbg_lvl = 0;         /* OFF */
++00246 
++00250 static ssize_t dbg_level_show(struct device_driver *drv, char *buf)
++00251 {
++00252         return sprintf(buf, "0x%0x\n", g_dbg_lvl);
++00253 }
++00254 
++00258 static ssize_t dbg_level_store(struct device_driver *drv, const char *buf,
++00259                                size_t count)
++00260 {
++00261         g_dbg_lvl = simple_strtoul(buf, NULL, 16);
++00262         return count;
++00263 }
++00264 
++00265 static DRIVER_ATTR(debuglevel, S_IRUGO | S_IWUSR, dbg_level_show,
++00266                    dbg_level_store);
++00267 
++00272 static int set_parameters(dwc_otg_core_if_t * core_if)
++00273 {
++00274         int retval = 0;
++00275         int i;
++00276 
++00277         if (dwc_otg_module_params.otg_cap != -1) {
++00278                 retval +=
++00279                     dwc_otg_set_param_otg_cap(core_if,
++00280                                               dwc_otg_module_params.otg_cap);
++00281         }
++00282         if (dwc_otg_module_params.dma_enable != -1) {
++00283                 retval +=
++00284                     dwc_otg_set_param_dma_enable(core_if,
++00285                                                  dwc_otg_module_params.
++00286                                                  dma_enable);
++00287         }
++00288         if (dwc_otg_module_params.dma_desc_enable != -1) {
++00289                 retval +=
++00290                     dwc_otg_set_param_dma_desc_enable(core_if,
++00291                                                       dwc_otg_module_params.
++00292                                                       dma_desc_enable);
++00293         }
++00294         if (dwc_otg_module_params.opt != -1) {
++00295                 retval +=
++00296                     dwc_otg_set_param_opt(core_if, dwc_otg_module_params.opt);
++00297         }
++00298         if (dwc_otg_module_params.dma_burst_size != -1) {
++00299                 retval +=
++00300                     dwc_otg_set_param_dma_burst_size(core_if,
++00301                                                      dwc_otg_module_params.
++00302                                                      dma_burst_size);
++00303         }
++00304         if (dwc_otg_module_params.host_support_fs_ls_low_power != -1) {
++00305                 retval +=
++00306                     dwc_otg_set_param_host_support_fs_ls_low_power(core_if,
++00307                                                                    dwc_otg_module_params.
++00308                                                                    host_support_fs_ls_low_power);
++00309         }
++00310         if (dwc_otg_module_params.enable_dynamic_fifo != -1) {
++00311                 retval +=
++00312                     dwc_otg_set_param_enable_dynamic_fifo(core_if,
++00313                                                           dwc_otg_module_params.
++00314                                                           enable_dynamic_fifo);
++00315         }
++00316         if (dwc_otg_module_params.data_fifo_size != -1) {
++00317                 retval +=
++00318                     dwc_otg_set_param_data_fifo_size(core_if,
++00319                                                      dwc_otg_module_params.
++00320                                                      data_fifo_size);
++00321         }
++00322         if (dwc_otg_module_params.dev_rx_fifo_size != -1) {
++00323                 retval +=
++00324                     dwc_otg_set_param_dev_rx_fifo_size(core_if,
++00325                                                        dwc_otg_module_params.
++00326                                                        dev_rx_fifo_size);
++00327         }
++00328         if (dwc_otg_module_params.dev_nperio_tx_fifo_size != -1) {
++00329                 retval +=
++00330                     dwc_otg_set_param_dev_nperio_tx_fifo_size(core_if,
++00331                                                               dwc_otg_module_params.
++00332                                                               dev_nperio_tx_fifo_size);
++00333         }
++00334         if (dwc_otg_module_params.host_rx_fifo_size != -1) {
++00335                 retval +=
++00336                     dwc_otg_set_param_host_rx_fifo_size(core_if,
++00337                                                         dwc_otg_module_params.host_rx_fifo_size);
++00338         }
++00339         if (dwc_otg_module_params.host_nperio_tx_fifo_size != -1) {
++00340                 retval +=
++00341                     dwc_otg_set_param_host_nperio_tx_fifo_size(core_if,
++00342                                                                dwc_otg_module_params.
++00343                                                                host_nperio_tx_fifo_size);
++00344         }
++00345         if (dwc_otg_module_params.host_perio_tx_fifo_size != -1) {
++00346                 retval +=
++00347                     dwc_otg_set_param_host_perio_tx_fifo_size(core_if,
++00348                                                               dwc_otg_module_params.
++00349                                                               host_perio_tx_fifo_size);
++00350         }
++00351         if (dwc_otg_module_params.max_transfer_size != -1) {
++00352                 retval +=
++00353                     dwc_otg_set_param_max_transfer_size(core_if,
++00354                                                         dwc_otg_module_params.
++00355                                                         max_transfer_size);
++00356         }
++00357         if (dwc_otg_module_params.max_packet_count != -1) {
++00358                 retval +=
++00359                     dwc_otg_set_param_max_packet_count(core_if,
++00360                                                        dwc_otg_module_params.
++00361                                                        max_packet_count);
++00362         }
++00363         if (dwc_otg_module_params.host_channels != -1) {
++00364                 retval +=
++00365                     dwc_otg_set_param_host_channels(core_if,
++00366                                                     dwc_otg_module_params.
++00367                                                     host_channels);
++00368         }
++00369         if (dwc_otg_module_params.dev_endpoints != -1) {
++00370                 retval +=
++00371                     dwc_otg_set_param_dev_endpoints(core_if,
++00372                                                     dwc_otg_module_params.
++00373                                                     dev_endpoints);
++00374         }
++00375         if (dwc_otg_module_params.phy_type != -1) {
++00376                 retval +=
++00377                     dwc_otg_set_param_phy_type(core_if,
++00378                                                dwc_otg_module_params.phy_type);
++00379         }
++00380         if (dwc_otg_module_params.speed != -1) {
++00381                 retval +=
++00382                     dwc_otg_set_param_speed(core_if,
++00383                                             dwc_otg_module_params.speed);
++00384         }
++00385         if (dwc_otg_module_params.host_ls_low_power_phy_clk != -1) {
++00386                 retval +=
++00387                     dwc_otg_set_param_host_ls_low_power_phy_clk(core_if,
++00388                                                                 dwc_otg_module_params.
++00389                                                                 host_ls_low_power_phy_clk);
++00390         }
++00391         if (dwc_otg_module_params.phy_ulpi_ddr != -1) {
++00392                 retval +=
++00393                     dwc_otg_set_param_phy_ulpi_ddr(core_if,
++00394                                                    dwc_otg_module_params.
++00395                                                    phy_ulpi_ddr);
++00396         }
++00397         if (dwc_otg_module_params.phy_ulpi_ext_vbus != -1) {
++00398                 retval +=
++00399                     dwc_otg_set_param_phy_ulpi_ext_vbus(core_if,
++00400                                                         dwc_otg_module_params.
++00401                                                         phy_ulpi_ext_vbus);
++00402         }
++00403         if (dwc_otg_module_params.phy_utmi_width != -1) {
++00404                 retval +=
++00405                     dwc_otg_set_param_phy_utmi_width(core_if,
++00406                                                      dwc_otg_module_params.
++00407                                                      phy_utmi_width);
++00408         }
++00409         if (dwc_otg_module_params.ulpi_fs_ls != -1) {
++00410                 retval +=
++00411                     dwc_otg_set_param_ulpi_fs_ls(core_if,
++00412                                                  dwc_otg_module_params.ulpi_fs_ls);
++00413         }
++00414         if (dwc_otg_module_params.ts_dline != -1) {
++00415                 retval +=
++00416                     dwc_otg_set_param_ts_dline(core_if,
++00417                                                dwc_otg_module_params.ts_dline);
++00418         }
++00419         if (dwc_otg_module_params.i2c_enable != -1) {
++00420                 retval +=
++00421                     dwc_otg_set_param_i2c_enable(core_if,
++00422                                                  dwc_otg_module_params.
++00423                                                  i2c_enable);
++00424         }
++00425         if (dwc_otg_module_params.en_multiple_tx_fifo != -1) {
++00426                 retval +=
++00427                     dwc_otg_set_param_en_multiple_tx_fifo(core_if,
++00428                                                           dwc_otg_module_params.
++00429                                                           en_multiple_tx_fifo);
++00430         }
++00431         for (i = 0; i < 15; i++) {
++00432                 if (dwc_otg_module_params.dev_perio_tx_fifo_size[i] != -1) {
++00433                         retval +=
++00434                             dwc_otg_set_param_dev_perio_tx_fifo_size(core_if,
++00435                                                                      dwc_otg_module_params.
++00436                                                                      dev_perio_tx_fifo_size
++00437                                                                      [i], i);
++00438                 }
++00439         }
++00440 
++00441         for (i = 0; i < 15; i++) {
++00442                 if (dwc_otg_module_params.dev_tx_fifo_size[i] != -1) {
++00443                         retval += dwc_otg_set_param_dev_tx_fifo_size(core_if,
++00444                                                                      dwc_otg_module_params.
++00445                                                                      dev_tx_fifo_size
++00446                                                                      [i], i);
++00447                 }
++00448         }
++00449         if (dwc_otg_module_params.thr_ctl != -1) {
++00450                 retval +=
++00451                     dwc_otg_set_param_thr_ctl(core_if,
++00452                                               dwc_otg_module_params.thr_ctl);
++00453         }
++00454         if (dwc_otg_module_params.mpi_enable != -1) {
++00455                 retval +=
++00456                     dwc_otg_set_param_mpi_enable(core_if,
++00457                                                  dwc_otg_module_params.
++00458                                                  mpi_enable);
++00459         }
++00460         if (dwc_otg_module_params.pti_enable != -1) {
++00461                 retval +=
++00462                     dwc_otg_set_param_pti_enable(core_if,
++00463                                                  dwc_otg_module_params.
++00464                                                  pti_enable);
++00465         }
++00466         if (dwc_otg_module_params.lpm_enable != -1) {
++00467                 retval +=
++00468                     dwc_otg_set_param_lpm_enable(core_if,
++00469                                                  dwc_otg_module_params.
++00470                                                  lpm_enable);
++00471         }
++00472         if (dwc_otg_module_params.ic_usb_cap != -1) {
++00473                 retval +=
++00474                     dwc_otg_set_param_ic_usb_cap(core_if,
++00475                                                  dwc_otg_module_params.
++00476                                                  ic_usb_cap);
++00477         }
++00478         if (dwc_otg_module_params.tx_thr_length != -1) {
++00479                 retval +=
++00480                     dwc_otg_set_param_tx_thr_length(core_if,
++00481                                                     dwc_otg_module_params.tx_thr_length);
++00482         }
++00483         if (dwc_otg_module_params.rx_thr_length != -1) {
++00484                 retval +=
++00485                     dwc_otg_set_param_rx_thr_length(core_if,
++00486                                                     dwc_otg_module_params.
++00487                                                     rx_thr_length);
++00488         }
++00489         if (dwc_otg_module_params.ahb_thr_ratio != -1) {
++00490                 retval +=
++00491                     dwc_otg_set_param_ahb_thr_ratio(core_if,
++00492                                                     dwc_otg_module_params.ahb_thr_ratio);
++00493         }
++00494         if (dwc_otg_module_params.power_down != -1) {
++00495                 retval +=
++00496                     dwc_otg_set_param_power_down(core_if,
++00497                                                  dwc_otg_module_params.power_down);
++00498         }
++00499         if (dwc_otg_module_params.reload_ctl != -1) {
++00500                 retval +=
++00501                     dwc_otg_set_param_reload_ctl(core_if,
++00502                                                  dwc_otg_module_params.reload_ctl);
++00503         }
++00504 
++00505         if (dwc_otg_module_params.dev_out_nak != -1) {
++00506                 retval +=
++00507                         dwc_otg_set_param_dev_out_nak(core_if,
++00508                         dwc_otg_module_params.dev_out_nak);
++00509         }
++00510 
++00511         if (dwc_otg_module_params.cont_on_bna != -1) {
++00512                 retval +=
++00513                         dwc_otg_set_param_cont_on_bna(core_if,
++00514                         dwc_otg_module_params.cont_on_bna);
++00515         }
++00516 
++00517         if (dwc_otg_module_params.ahb_single != -1) {
++00518                 retval +=
++00519                         dwc_otg_set_param_ahb_single(core_if,
++00520                         dwc_otg_module_params.ahb_single);
++00521         }
++00522 
++00523         if (dwc_otg_module_params.otg_ver != -1) {
++00524                 retval +=
++00525                     dwc_otg_set_param_otg_ver(core_if,
++00526                                               dwc_otg_module_params.otg_ver);
++00527         }
++00528         if (dwc_otg_module_params.adp_enable != -1) {
++00529                 retval +=
++00530                     dwc_otg_set_param_adp_enable(core_if,
++00531                                                  dwc_otg_module_params.
++00532                                                  adp_enable);
++00533         }
++00534         return retval;
++00535 }
++00536 
++00541 static irqreturn_t dwc_otg_common_irq(int irq, void *dev)
++00542 {
++00543         int32_t retval = IRQ_NONE;
++00544 
++00545         retval = dwc_otg_handle_common_intr(dev);
++00546         if (retval != 0) {
++00547                 S3C2410X_CLEAR_EINTPEND();
++00548         }
++00549         return IRQ_RETVAL(retval);
++00550 }
++00551 
++00561 static void dwc_otg_driver_remove(
++00562 #ifdef LM_INTERFACE
++00563                                          struct lm_device *_dev
++00564 #elif defined(PCI_INTERFACE)
++00565                                          struct pci_dev *_dev
++00566 #endif
++00567     )
++00568 {
++00569 #ifdef LM_INTERFACE
++00570         dwc_otg_device_t *otg_dev = lm_get_drvdata(_dev);
++00571 #elif defined(PCI_INTERFACE)
++00572         dwc_otg_device_t *otg_dev = pci_get_drvdata(_dev);
++00573 #endif
++00574 
++00575         DWC_DEBUGPL(DBG_ANY, "%s(%p)\n", __func__, _dev);
++00576 
++00577         if (!otg_dev) {
++00578                 /* Memory allocation for the dwc_otg_device failed. */
++00579                 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev NULL!\n", __func__);
++00580                 return;
++00581         }
++00582 #ifndef DWC_DEVICE_ONLY
++00583         if (otg_dev->hcd) {
++00584                 hcd_remove(_dev);
++00585         } else {
++00586                 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->hcd NULL!\n", __func__);
++00587                 return;
++00588         }
++00589 #endif
++00590 
++00591 #ifndef DWC_HOST_ONLY
++00592         if (otg_dev->pcd) {
++00593                 pcd_remove(_dev);
++00594         } else {
++00595                 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->pcd NULL!\n", __func__);
++00596                 return;
++00597         }
++00598 #endif
++00599         /*
++00600          * Free the IRQ
++00601          */
++00602         if (otg_dev->common_irq_installed) {
++00603                 free_irq(_dev->irq, otg_dev);
++00604         } else {
++00605                 DWC_DEBUGPL(DBG_ANY, "%s: There is no installed irq!\n", __func__);
++00606                 return;
++00607         }
++00608 
++00609         if (otg_dev->core_if) {
++00610                 dwc_otg_cil_remove(otg_dev->core_if);
++00611         } else {
++00612                 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->core_if NULL!\n", __func__);
++00613                 return;
++00614         }
++00615 
++00616         /*
++00617          * Remove the device attributes
++00618          */
++00619         dwc_otg_attr_remove(_dev);
++00620 
++00621         /*
++00622          * Return the memory.
++00623          */
++00624         if (otg_dev->os_dep.base) {
++00625                 iounmap(otg_dev->os_dep.base);
++00626         }
++00627         DWC_FREE(otg_dev);
++00628 
++00629         /*
++00630          * Clear the drvdata pointer.
++00631          */
++00632 #ifdef LM_INTERFACE
++00633         lm_set_drvdata(_dev, 0);
++00634 #elif defined(PCI_INTERFACE)
++00635     release_mem_region(otg_dev->os_dep.rsrc_start, otg_dev->os_dep.rsrc_len);
++00636         pci_set_drvdata(_dev, 0);
++00637 #endif
++00638 }
++00639 
++00651 static int dwc_otg_driver_probe(
++00652 #ifdef LM_INTERFACE
++00653                                        struct lm_device *_dev
++00654 #elif defined(PCI_INTERFACE)
++00655                                        struct pci_dev *_dev,
++00656                                        const struct pci_device_id *id
++00657 #endif
++00658     )
++00659 {
++00660         int retval = 0;
++00661         dwc_otg_device_t *dwc_otg_device;
++00662 
++00663         dev_dbg(&_dev->dev, "dwc_otg_driver_probe(%p)\n", _dev);
++00664 #ifdef LM_INTERFACE
++00665         dev_dbg(&_dev->dev, "start=0x%08x\n", (unsigned)_dev->resource.start);
++00666 #elif defined(PCI_INTERFACE)
++00667         if (!id) {
++00668                 DWC_ERROR("Invalid pci_device_id %p", id);
++00669                 return -EINVAL;
++00670         }
++00671 
++00672         if (!_dev || (pci_enable_device(_dev) < 0)) {
++00673                 DWC_ERROR("Invalid pci_device %p", _dev);
++00674                 return -ENODEV;
++00675         }
++00676         dev_dbg(&_dev->dev, "start=0x%08x\n", (unsigned)pci_resource_start(_dev,0));
++00677         /* other stuff needed as well? */
++00678 
++00679 #endif
++00680 
++00681         dwc_otg_device = DWC_ALLOC(sizeof(dwc_otg_device_t));
++00682 
++00683         if (!dwc_otg_device) {
++00684                 dev_err(&_dev->dev, "kmalloc of dwc_otg_device failed\n");
++00685                 return -ENOMEM;
++00686         }
++00687 
++00688         memset(dwc_otg_device, 0, sizeof(*dwc_otg_device));
++00689         dwc_otg_device->os_dep.reg_offset = 0xFFFFFFFF;
++00690 
++00691         /*
++00692          * Map the DWC_otg Core memory into virtual address space.
++00693          */
++00694 #ifdef LM_INTERFACE
++00695         dwc_otg_device->os_dep.base = ioremap(_dev->resource.start, SZ_256K);
++00696 
++00697         if (!dwc_otg_device->os_dep.base) {
++00698                 dev_err(&_dev->dev, "ioremap() failed\n");
++00699                 DWC_FREE(dwc_otg_device);
++00700                 return -ENOMEM;
++00701         }
++00702         dev_dbg(&_dev->dev, "base=0x%08x\n",
++00703                 (unsigned)dwc_otg_device->os_dep.base);
++00704 #elif defined(PCI_INTERFACE)
++00705         _dev->current_state = PCI_D0;
++00706         _dev->dev.power.power_state = PMSG_ON;
++00707 
++00708         if (!_dev->irq) {
++00709                 DWC_ERROR("Found HC with no IRQ. Check BIOS/PCI %s setup!",
++00710                           pci_name(_dev));
++00711                 iounmap(dwc_otg_device->os_dep.base);
++00712                 DWC_FREE(dwc_otg_device);
++00713                 return -ENODEV;
++00714         }
++00715 
++00716         dwc_otg_device->os_dep.rsrc_start = pci_resource_start(_dev, 0);
++00717         dwc_otg_device->os_dep.rsrc_len = pci_resource_len(_dev, 0);
++00718         DWC_DEBUGPL(DBG_ANY, "PCI resource: start=%08x, len=%08x\n",
++00719                     (unsigned)dwc_otg_device->os_dep.rsrc_start,
++00720                     (unsigned)dwc_otg_device->os_dep.rsrc_len);
++00721         if (!request_mem_region
++00722             (dwc_otg_device->os_dep.rsrc_start, dwc_otg_device->os_dep.rsrc_len,
++00723              "dwc_otg")) {
++00724                 dev_dbg(&_dev->dev, "error requesting memory\n");
++00725                 iounmap(dwc_otg_device->os_dep.base);
++00726                 DWC_FREE(dwc_otg_device);
++00727                 return -EFAULT;
++00728         }
++00729 
++00730         dwc_otg_device->os_dep.base =
++00731             ioremap_nocache(dwc_otg_device->os_dep.rsrc_start,
++00732                             dwc_otg_device->os_dep.rsrc_len);
++00733         if (dwc_otg_device->os_dep.base == NULL) {
++00734                 dev_dbg(&_dev->dev, "error mapping memory\n");
++00735                 release_mem_region(dwc_otg_device->os_dep.rsrc_start,
++00736                                    dwc_otg_device->os_dep.rsrc_len);
++00737                 iounmap(dwc_otg_device->os_dep.base);
++00738                 DWC_FREE(dwc_otg_device);
++00739                 return -EFAULT;
++00740         }
++00741         dev_dbg(&_dev->dev, "base=0x%p (before adjust) \n",
++00742                 dwc_otg_device->os_dep.base);
++00743         dwc_otg_device->os_dep.base = (char *)dwc_otg_device->os_dep.base;
++00744         dev_dbg(&_dev->dev, "base=0x%p (after adjust) \n",
++00745                 dwc_otg_device->os_dep.base);
++00746         dev_dbg(&_dev->dev, "%s: mapped PA 0x%x to VA 0x%p\n", __func__,
++00747                 (unsigned)dwc_otg_device->os_dep.rsrc_start,
++00748                 dwc_otg_device->os_dep.base);
++00749 
++00750         pci_set_master(_dev);
++00751         pci_set_drvdata(_dev, dwc_otg_device);
++00752 #endif
++00753 
++00754         /*
++00755          * Initialize driver data to point to the global DWC_otg
++00756          * Device structure.
++00757          */
++00758 #ifdef LM_INTERFACE
++00759         lm_set_drvdata(_dev, dwc_otg_device);
++00760 #endif
++00761         dev_dbg(&_dev->dev, "dwc_otg_device=0x%p\n", dwc_otg_device);
++00762 
++00763         dwc_otg_device->core_if = dwc_otg_cil_init(dwc_otg_device->os_dep.base);
++00764         if (!dwc_otg_device->core_if) {
++00765                 dev_err(&_dev->dev, "CIL initialization failed!\n");
++00766                 retval = -ENOMEM;
++00767                 goto fail;
++00768         }
++00769 
++00770         /*
++00771          * Attempt to ensure this device is really a DWC_otg Controller.
++00772          * Read and verify the SNPSID register contents. The value should be
++00773          * 0x45F42XXX, which corresponds to "OT2", as in "OTG version 2.XX".
++00774          */
++00775 
++00776         if ((dwc_otg_get_gsnpsid(dwc_otg_device->core_if) & 0xFFFFF000) !=
++00777             0x4F542000) {
++00778                 dev_err(&_dev->dev, "Bad value for SNPSID: 0x%08x\n",
++00779                         dwc_otg_get_gsnpsid(dwc_otg_device->core_if));
++00780                 retval = -EINVAL;
++00781                 goto fail;
++00782         }
++00783 
++00784         /*
++00785          * Validate parameter values.
++00786          */
++00787         if (set_parameters(dwc_otg_device->core_if)) {
++00788                 retval = -EINVAL;
++00789                 goto fail;
++00790         }
++00791 
++00792         /*
++00793          * Create Device Attributes in sysfs
++00794          */
++00795         dwc_otg_attr_create(_dev);
++00796 
++00797         /*
++00798          * Disable the global interrupt until all the interrupt
++00799          * handlers are installed.
++00800          */
++00801         dwc_otg_disable_global_interrupts(dwc_otg_device->core_if);
++00802 
++00803         /*
++00804          * Install the interrupt handler for the common interrupts before
++00805          * enabling common interrupts in core_init below.
++00806          */
++00807         DWC_DEBUGPL(DBG_CIL, "registering (common) handler for irq%d\n",
++00808                     _dev->irq);
++00809         retval = request_irq(_dev->irq, dwc_otg_common_irq,
++00810                              IRQF_SHARED | IRQF_DISABLED | IRQ_LEVEL, "dwc_otg",
++00811                              dwc_otg_device);
++00812         if (retval) {
++00813                 DWC_ERROR("request of irq%d failed\n", _dev->irq);
++00814                 retval = -EBUSY;
++00815                 goto fail;
++00816         } else {
++00817                 dwc_otg_device->common_irq_installed = 1;
++00818         }
++00819 
++00820 #ifdef LM_INTERFACE
++00821         set_irq_type(_dev->irq, IRQT_LOW);
++00822 #endif
++00823         /*
++00824          * Initialize the DWC_otg core.
++00825          */
++00826         dwc_otg_core_init(dwc_otg_device->core_if);
++00827                 
++00828 #ifndef DWC_HOST_ONLY
++00829         /*
++00830          * Initialize the PCD
++00831          */
++00832         retval = pcd_init(_dev);
++00833         if (retval != 0) {
++00834                 DWC_ERROR("pcd_init failed\n");
++00835                 dwc_otg_device->pcd = NULL;
++00836                 goto fail;
++00837         }       
++00838 #endif
++00839 #ifndef DWC_DEVICE_ONLY
++00840         /*
++00841          * Initialize the HCD
++00842          */
++00843         retval = hcd_init(_dev);
++00844         if (retval != 0) {
++00845                 DWC_ERROR("hcd_init failed\n");
++00846                 dwc_otg_device->hcd = NULL;
++00847                 goto fail;
++00848         }
++00849 #endif
++00850 #ifdef PCI_INTERFACE
++00851         pci_set_drvdata(_dev, dwc_otg_device);
++00852         dwc_otg_device->os_dep.pcidev = _dev;
++00853 #endif
++00854 
++00855         /*
++00856          * Enable the global interrupt after all the interrupt
++00857          * handlers are installed if there is no ADP support else 
++00858          * perform initial actions required for Internal ADP logic.
++00859          */
++00860         if (!dwc_otg_get_param_adp_enable(dwc_otg_device->core_if))     
++00861                 dwc_otg_enable_global_interrupts(dwc_otg_device->core_if);
++00862         else
++00863                 dwc_otg_adp_start(dwc_otg_device->core_if, 
++00864                                                         dwc_otg_is_host_mode(dwc_otg_device->core_if));
++00865 
++00866         return 0;
++00867 
++00868 fail:
++00869         dwc_otg_driver_remove(_dev);
++00870         return retval;
++00871 }
++00872 
++00884 #ifdef LM_INTERFACE
++00885 static struct lm_driver dwc_otg_driver = {
++00886         .drv = {.name = (char *)dwc_driver_name,},
++00887         .probe = dwc_otg_driver_probe,
++00888         .remove = dwc_otg_driver_remove,
++00889 };
++00890 #elif defined(PCI_INTERFACE)
++00891 static const struct pci_device_id pci_ids[] = { {
++00892                                                  PCI_DEVICE(0x16c3, 0xabcd),
++00893                                                  .driver_data =
++00894                                                  (unsigned long)0xdeadbeef,
++00895                                                  }, { /* end: all zeroes */ }
++00896 };
++00897 
++00898 MODULE_DEVICE_TABLE(pci, pci_ids);
++00899 
++00900 /* pci driver glue; this is a "new style" PCI driver module */
++00901 static struct pci_driver dwc_otg_driver = {
++00902         .name = "dwc_otg",
++00903         .id_table = pci_ids,
++00904 
++00905         .probe = dwc_otg_driver_probe,
++00906         .remove = dwc_otg_driver_remove,
++00907 
++00908         .driver = {
++00909                    .name = (char *)dwc_driver_name,
++00910                    },
++00911 };
++00912 #endif
++00913 
++00924 static int __init dwc_otg_driver_init(void)
++00925 {
++00926         int retval = 0;
++00927         int error;
++00928         printk(KERN_INFO "%s: version %s\n", dwc_driver_name,
++00929                DWC_DRIVER_VERSION);
++00930 #ifdef LM_INTERFACE
++00931         retval = lm_driver_register(&dwc_otg_driver);
++00932 #elif defined(PCI_INTERFACE)
++00933         retval = pci_register_driver(&dwc_otg_driver);
++00934 #endif
++00935         if (retval < 0) {
++00936                 printk(KERN_ERR "%s retval=%d\n", __func__, retval);
++00937                 return retval;
++00938         }
++00939 #ifdef LM_INTERFACE
++00940         error = driver_create_file(&dwc_otg_driver.drv, &driver_attr_version);
++00941         error = driver_create_file(&dwc_otg_driver.drv, &driver_attr_debuglevel);
++00942 #elif defined(PCI_INTERFACE)
++00943         error = driver_create_file(&dwc_otg_driver.driver, &driver_attr_version);
++00944         error = driver_create_file(&dwc_otg_driver.driver, &driver_attr_debuglevel);
++00945 #endif
++00946         return retval;
++00947 }
++00948 
++00949 module_init(dwc_otg_driver_init);
++00950 
++00957 static void __exit dwc_otg_driver_cleanup(void)
++00958 {
++00959         printk(KERN_DEBUG "dwc_otg_driver_cleanup()\n");
++00960 
++00961 #ifdef LM_INTERFACE
++00962         driver_remove_file(&dwc_otg_driver.drv, &driver_attr_debuglevel);
++00963         driver_remove_file(&dwc_otg_driver.drv, &driver_attr_version);
++00964         lm_driver_unregister(&dwc_otg_driver);
++00965 #elif defined(PCI_INTERFACE)
++00966         driver_remove_file(&dwc_otg_driver.driver, &driver_attr_debuglevel);
++00967         driver_remove_file(&dwc_otg_driver.driver, &driver_attr_version);
++00968         pci_unregister_driver(&dwc_otg_driver);
++00969 #endif
++00970 
++00971         printk(KERN_INFO "%s module removed\n", dwc_driver_name);
++00972 }
++00973 
++00974 module_exit(dwc_otg_driver_cleanup);
++00975 
++00976 MODULE_DESCRIPTION(DWC_DRIVER_DESC);
++00977 MODULE_AUTHOR("Synopsys Inc.");
++00978 MODULE_LICENSE("GPL");
++00979 
++00980 module_param_named(otg_cap, dwc_otg_module_params.otg_cap, int, 0444);
++00981 MODULE_PARM_DESC(otg_cap, "OTG Capabilities 0=HNP&SRP 1=SRP Only 2=None");
++00982 module_param_named(opt, dwc_otg_module_params.opt, int, 0444);
++00983 MODULE_PARM_DESC(opt, "OPT Mode");
++00984 module_param_named(dma_enable, dwc_otg_module_params.dma_enable, int, 0444);
++00985 MODULE_PARM_DESC(dma_enable, "DMA Mode 0=Slave 1=DMA enabled");
++00986 
++00987 module_param_named(dma_desc_enable, dwc_otg_module_params.dma_desc_enable, int,
++00988                    0444);
++00989 MODULE_PARM_DESC(dma_desc_enable,
++00990                  "DMA Desc Mode 0=Address DMA 1=DMA Descriptor enabled");
++00991 
++00992 module_param_named(dma_burst_size, dwc_otg_module_params.dma_burst_size, int,
++00993                    0444);
++00994 MODULE_PARM_DESC(dma_burst_size,
++00995                  "DMA Burst Size 1, 4, 8, 16, 32, 64, 128, 256");
++00996 module_param_named(speed, dwc_otg_module_params.speed, int, 0444);
++00997 MODULE_PARM_DESC(speed, "Speed 0=High Speed 1=Full Speed");
++00998 module_param_named(host_support_fs_ls_low_power,
++00999                    dwc_otg_module_params.host_support_fs_ls_low_power, int,
++01000                    0444);
++01001 MODULE_PARM_DESC(host_support_fs_ls_low_power,
++01002                  "Support Low Power w/FS or LS 0=Support 1=Don't Support");
++01003 module_param_named(host_ls_low_power_phy_clk,
++01004                    dwc_otg_module_params.host_ls_low_power_phy_clk, int, 0444);
++01005 MODULE_PARM_DESC(host_ls_low_power_phy_clk,
++01006                  "Low Speed Low Power Clock 0=48Mhz 1=6Mhz");
++01007 module_param_named(enable_dynamic_fifo,
++01008                    dwc_otg_module_params.enable_dynamic_fifo, int, 0444);
++01009 MODULE_PARM_DESC(enable_dynamic_fifo, "0=cC Setting 1=Allow Dynamic Sizing");
++01010 module_param_named(data_fifo_size, dwc_otg_module_params.data_fifo_size, int,
++01011                    0444);
++01012 MODULE_PARM_DESC(data_fifo_size,
++01013                  "Total number of words in the data FIFO memory 32-32768");
++01014 module_param_named(dev_rx_fifo_size, dwc_otg_module_params.dev_rx_fifo_size,
++01015                    int, 0444);
++01016 MODULE_PARM_DESC(dev_rx_fifo_size, "Number of words in the Rx FIFO 16-32768");
++01017 module_param_named(dev_nperio_tx_fifo_size,
++01018                    dwc_otg_module_params.dev_nperio_tx_fifo_size, int, 0444);
++01019 MODULE_PARM_DESC(dev_nperio_tx_fifo_size,
++01020                  "Number of words in the non-periodic Tx FIFO 16-32768");
++01021 module_param_named(dev_perio_tx_fifo_size_1,
++01022                    dwc_otg_module_params.dev_perio_tx_fifo_size[0], int, 0444);
++01023 MODULE_PARM_DESC(dev_perio_tx_fifo_size_1,
++01024                  "Number of words in the periodic Tx FIFO 4-768");
++01025 module_param_named(dev_perio_tx_fifo_size_2,
++01026                    dwc_otg_module_params.dev_perio_tx_fifo_size[1], int, 0444);
++01027 MODULE_PARM_DESC(dev_perio_tx_fifo_size_2,
++01028                  "Number of words in the periodic Tx FIFO 4-768");
++01029 module_param_named(dev_perio_tx_fifo_size_3,
++01030                    dwc_otg_module_params.dev_perio_tx_fifo_size[2], int, 0444);
++01031 MODULE_PARM_DESC(dev_perio_tx_fifo_size_3,
++01032                  "Number of words in the periodic Tx FIFO 4-768");
++01033 module_param_named(dev_perio_tx_fifo_size_4,
++01034                    dwc_otg_module_params.dev_perio_tx_fifo_size[3], int, 0444);
++01035 MODULE_PARM_DESC(dev_perio_tx_fifo_size_4,
++01036                  "Number of words in the periodic Tx FIFO 4-768");
++01037 module_param_named(dev_perio_tx_fifo_size_5,
++01038                    dwc_otg_module_params.dev_perio_tx_fifo_size[4], int, 0444);
++01039 MODULE_PARM_DESC(dev_perio_tx_fifo_size_5,
++01040                  "Number of words in the periodic Tx FIFO 4-768");
++01041 module_param_named(dev_perio_tx_fifo_size_6,
++01042                    dwc_otg_module_params.dev_perio_tx_fifo_size[5], int, 0444);
++01043 MODULE_PARM_DESC(dev_perio_tx_fifo_size_6,
++01044                  "Number of words in the periodic Tx FIFO 4-768");
++01045 module_param_named(dev_perio_tx_fifo_size_7,
++01046                    dwc_otg_module_params.dev_perio_tx_fifo_size[6], int, 0444);
++01047 MODULE_PARM_DESC(dev_perio_tx_fifo_size_7,
++01048                  "Number of words in the periodic Tx FIFO 4-768");
++01049 module_param_named(dev_perio_tx_fifo_size_8,
++01050                    dwc_otg_module_params.dev_perio_tx_fifo_size[7], int, 0444);
++01051 MODULE_PARM_DESC(dev_perio_tx_fifo_size_8,
++01052                  "Number of words in the periodic Tx FIFO 4-768");
++01053 module_param_named(dev_perio_tx_fifo_size_9,
++01054                    dwc_otg_module_params.dev_perio_tx_fifo_size[8], int, 0444);
++01055 MODULE_PARM_DESC(dev_perio_tx_fifo_size_9,
++01056                  "Number of words in the periodic Tx FIFO 4-768");
++01057 module_param_named(dev_perio_tx_fifo_size_10,
++01058                    dwc_otg_module_params.dev_perio_tx_fifo_size[9], int, 0444);
++01059 MODULE_PARM_DESC(dev_perio_tx_fifo_size_10,
++01060                  "Number of words in the periodic Tx FIFO 4-768");
++01061 module_param_named(dev_perio_tx_fifo_size_11,
++01062                    dwc_otg_module_params.dev_perio_tx_fifo_size[10], int, 0444);
++01063 MODULE_PARM_DESC(dev_perio_tx_fifo_size_11,
++01064                  "Number of words in the periodic Tx FIFO 4-768");
++01065 module_param_named(dev_perio_tx_fifo_size_12,
++01066                    dwc_otg_module_params.dev_perio_tx_fifo_size[11], int, 0444);
++01067 MODULE_PARM_DESC(dev_perio_tx_fifo_size_12,
++01068                  "Number of words in the periodic Tx FIFO 4-768");
++01069 module_param_named(dev_perio_tx_fifo_size_13,
++01070                    dwc_otg_module_params.dev_perio_tx_fifo_size[12], int, 0444);
++01071 MODULE_PARM_DESC(dev_perio_tx_fifo_size_13,
++01072                  "Number of words in the periodic Tx FIFO 4-768");
++01073 module_param_named(dev_perio_tx_fifo_size_14,
++01074                    dwc_otg_module_params.dev_perio_tx_fifo_size[13], int, 0444);
++01075 MODULE_PARM_DESC(dev_perio_tx_fifo_size_14,
++01076                  "Number of words in the periodic Tx FIFO 4-768");
++01077 module_param_named(dev_perio_tx_fifo_size_15,
++01078                    dwc_otg_module_params.dev_perio_tx_fifo_size[14], int, 0444);
++01079 MODULE_PARM_DESC(dev_perio_tx_fifo_size_15,
++01080                  "Number of words in the periodic Tx FIFO 4-768");
++01081 module_param_named(host_rx_fifo_size, dwc_otg_module_params.host_rx_fifo_size,
++01082                    int, 0444);
++01083 MODULE_PARM_DESC(host_rx_fifo_size, "Number of words in the Rx FIFO 16-32768");
++01084 module_param_named(host_nperio_tx_fifo_size,
++01085                    dwc_otg_module_params.host_nperio_tx_fifo_size, int, 0444);
++01086 MODULE_PARM_DESC(host_nperio_tx_fifo_size,
++01087                  "Number of words in the non-periodic Tx FIFO 16-32768");
++01088 module_param_named(host_perio_tx_fifo_size,
++01089                    dwc_otg_module_params.host_perio_tx_fifo_size, int, 0444);
++01090 MODULE_PARM_DESC(host_perio_tx_fifo_size,
++01091                  "Number of words in the host periodic Tx FIFO 16-32768");
++01092 module_param_named(max_transfer_size, dwc_otg_module_params.max_transfer_size,
++01093                    int, 0444);
++01095 MODULE_PARM_DESC(max_transfer_size,
++01096                  "The maximum transfer size supported in bytes 2047-65535");
++01097 module_param_named(max_packet_count, dwc_otg_module_params.max_packet_count,
++01098                    int, 0444);
++01099 MODULE_PARM_DESC(max_packet_count,
++01100                  "The maximum number of packets in a transfer 15-511");
++01101 module_param_named(host_channels, dwc_otg_module_params.host_channels, int,
++01102                    0444);
++01103 MODULE_PARM_DESC(host_channels,
++01104                  "The number of host channel registers to use 1-16");
++01105 module_param_named(dev_endpoints, dwc_otg_module_params.dev_endpoints, int,
++01106                    0444);
++01107 MODULE_PARM_DESC(dev_endpoints,
++01108                  "The number of endpoints in addition to EP0 available for device mode 1-15");
++01109 module_param_named(phy_type, dwc_otg_module_params.phy_type, int, 0444);
++01110 MODULE_PARM_DESC(phy_type, "0=Reserved 1=UTMI+ 2=ULPI");
++01111 module_param_named(phy_utmi_width, dwc_otg_module_params.phy_utmi_width, int,
++01112                    0444);
++01113 MODULE_PARM_DESC(phy_utmi_width, "Specifies the UTMI+ Data Width 8 or 16 bits");
++01114 module_param_named(phy_ulpi_ddr, dwc_otg_module_params.phy_ulpi_ddr, int, 0444);
++01115 MODULE_PARM_DESC(phy_ulpi_ddr,
++01116                  "ULPI at double or single data rate 0=Single 1=Double");
++01117 module_param_named(phy_ulpi_ext_vbus, dwc_otg_module_params.phy_ulpi_ext_vbus,
++01118                    int, 0444);
++01119 MODULE_PARM_DESC(phy_ulpi_ext_vbus,
++01120                  "ULPI PHY using internal or external vbus 0=Internal");
++01121 module_param_named(i2c_enable, dwc_otg_module_params.i2c_enable, int, 0444);
++01122 MODULE_PARM_DESC(i2c_enable, "FS PHY Interface");
++01123 module_param_named(ulpi_fs_ls, dwc_otg_module_params.ulpi_fs_ls, int, 0444);
++01124 MODULE_PARM_DESC(ulpi_fs_ls, "ULPI PHY FS/LS mode only");
++01125 module_param_named(ts_dline, dwc_otg_module_params.ts_dline, int, 0444);
++01126 MODULE_PARM_DESC(ts_dline, "Term select Dline pulsing for all PHYs");
++01127 module_param_named(debug, g_dbg_lvl, int, 0444);
++01128 MODULE_PARM_DESC(debug, "");
++01129 
++01130 module_param_named(en_multiple_tx_fifo,
++01131                    dwc_otg_module_params.en_multiple_tx_fifo, int, 0444);
++01132 MODULE_PARM_DESC(en_multiple_tx_fifo,
++01133                  "Dedicated Non Periodic Tx FIFOs 0=disabled 1=enabled");
++01134 module_param_named(dev_tx_fifo_size_1,
++01135                    dwc_otg_module_params.dev_tx_fifo_size[0], int, 0444);
++01136 MODULE_PARM_DESC(dev_tx_fifo_size_1, "Number of words in the Tx FIFO 4-768");
++01137 module_param_named(dev_tx_fifo_size_2,
++01138                    dwc_otg_module_params.dev_tx_fifo_size[1], int, 0444);
++01139 MODULE_PARM_DESC(dev_tx_fifo_size_2, "Number of words in the Tx FIFO 4-768");
++01140 module_param_named(dev_tx_fifo_size_3,
++01141                    dwc_otg_module_params.dev_tx_fifo_size[2], int, 0444);
++01142 MODULE_PARM_DESC(dev_tx_fifo_size_3, "Number of words in the Tx FIFO 4-768");
++01143 module_param_named(dev_tx_fifo_size_4,
++01144                    dwc_otg_module_params.dev_tx_fifo_size[3], int, 0444);
++01145 MODULE_PARM_DESC(dev_tx_fifo_size_4, "Number of words in the Tx FIFO 4-768");
++01146 module_param_named(dev_tx_fifo_size_5,
++01147                    dwc_otg_module_params.dev_tx_fifo_size[4], int, 0444);
++01148 MODULE_PARM_DESC(dev_tx_fifo_size_5, "Number of words in the Tx FIFO 4-768");
++01149 module_param_named(dev_tx_fifo_size_6,
++01150                    dwc_otg_module_params.dev_tx_fifo_size[5], int, 0444);
++01151 MODULE_PARM_DESC(dev_tx_fifo_size_6, "Number of words in the Tx FIFO 4-768");
++01152 module_param_named(dev_tx_fifo_size_7,
++01153                    dwc_otg_module_params.dev_tx_fifo_size[6], int, 0444);
++01154 MODULE_PARM_DESC(dev_tx_fifo_size_7, "Number of words in the Tx FIFO 4-768");
++01155 module_param_named(dev_tx_fifo_size_8,
++01156                    dwc_otg_module_params.dev_tx_fifo_size[7], int, 0444);
++01157 MODULE_PARM_DESC(dev_tx_fifo_size_8, "Number of words in the Tx FIFO 4-768");
++01158 module_param_named(dev_tx_fifo_size_9,
++01159                    dwc_otg_module_params.dev_tx_fifo_size[8], int, 0444);
++01160 MODULE_PARM_DESC(dev_tx_fifo_size_9, "Number of words in the Tx FIFO 4-768");
++01161 module_param_named(dev_tx_fifo_size_10,
++01162                    dwc_otg_module_params.dev_tx_fifo_size[9], int, 0444);
++01163 MODULE_PARM_DESC(dev_tx_fifo_size_10, "Number of words in the Tx FIFO 4-768");
++01164 module_param_named(dev_tx_fifo_size_11,
++01165                    dwc_otg_module_params.dev_tx_fifo_size[10], int, 0444);
++01166 MODULE_PARM_DESC(dev_tx_fifo_size_11, "Number of words in the Tx FIFO 4-768");
++01167 module_param_named(dev_tx_fifo_size_12,
++01168                    dwc_otg_module_params.dev_tx_fifo_size[11], int, 0444);
++01169 MODULE_PARM_DESC(dev_tx_fifo_size_12, "Number of words in the Tx FIFO 4-768");
++01170 module_param_named(dev_tx_fifo_size_13,
++01171                    dwc_otg_module_params.dev_tx_fifo_size[12], int, 0444);
++01172 MODULE_PARM_DESC(dev_tx_fifo_size_13, "Number of words in the Tx FIFO 4-768");
++01173 module_param_named(dev_tx_fifo_size_14,
++01174                    dwc_otg_module_params.dev_tx_fifo_size[13], int, 0444);
++01175 MODULE_PARM_DESC(dev_tx_fifo_size_14, "Number of words in the Tx FIFO 4-768");
++01176 module_param_named(dev_tx_fifo_size_15,
++01177                    dwc_otg_module_params.dev_tx_fifo_size[14], int, 0444);
++01178 MODULE_PARM_DESC(dev_tx_fifo_size_15, "Number of words in the Tx FIFO 4-768");
++01179 
++01180 module_param_named(thr_ctl, dwc_otg_module_params.thr_ctl, int, 0444);
++01181 MODULE_PARM_DESC(thr_ctl,
++01182                  "Thresholding enable flag bit 0 - non ISO Tx thr., 1 - ISO Tx thr., 2 - Rx thr.- bit 0=disabled 1=enabled");
++01183 module_param_named(tx_thr_length, dwc_otg_module_params.tx_thr_length, int,
++01184                    0444);
++01185 MODULE_PARM_DESC(tx_thr_length, "Tx Threshold length in 32 bit DWORDs");
++01186 module_param_named(rx_thr_length, dwc_otg_module_params.rx_thr_length, int,
++01187                    0444);
++01188 MODULE_PARM_DESC(rx_thr_length, "Rx Threshold length in 32 bit DWORDs");
++01189 
++01190 module_param_named(pti_enable, dwc_otg_module_params.pti_enable, int, 0444);
++01191 module_param_named(mpi_enable, dwc_otg_module_params.mpi_enable, int, 0444);
++01192 module_param_named(lpm_enable, dwc_otg_module_params.lpm_enable, int, 0444);
++01193 MODULE_PARM_DESC(lpm_enable, "LPM Enable 0=LPM Disabled 1=LPM Enabled");
++01194 module_param_named(ic_usb_cap, dwc_otg_module_params.ic_usb_cap, int, 0444);
++01195 MODULE_PARM_DESC(ic_usb_cap,
++01196                  "IC_USB Capability 0=IC_USB Disabled 1=IC_USB Enabled");
++01197 module_param_named(ahb_thr_ratio, dwc_otg_module_params.ahb_thr_ratio, int,
++01198                    0444);
++01199 MODULE_PARM_DESC(ahb_thr_ratio, "AHB Threshold Ratio");
++01200 module_param_named(power_down, dwc_otg_module_params.power_down, int, 0444);
++01201 MODULE_PARM_DESC(power_down, "Power Down Mode");
++01202 module_param_named(reload_ctl, dwc_otg_module_params.reload_ctl, int, 0444);
++01203 MODULE_PARM_DESC(reload_ctl, "HFIR Reload Control");
++01204 module_param_named(dev_out_nak, dwc_otg_module_params.dev_out_nak, int, 0444);
++01205 MODULE_PARM_DESC(dev_out_nak, "Enable Device OUT NAK");
++01206 module_param_named(cont_on_bna, dwc_otg_module_params.cont_on_bna, int, 0444);
++01207 MODULE_PARM_DESC(cont_on_bna, "Enable Enable Continue on BNA");
++01208 module_param_named(ahb_single, dwc_otg_module_params.ahb_single, int, 0444);
++01209 MODULE_PARM_DESC(ahb_single, "Enable AHB Single Support");
++01210 module_param_named(adp_enable, dwc_otg_module_params.adp_enable, int, 0444);
++01211 MODULE_PARM_DESC(adp_enable, "ADP Enable 0=ADP Disabled 1=ADP Enabled");
++01212 module_param_named(otg_ver, dwc_otg_module_params.otg_ver, int, 0444);
++01213 MODULE_PARM_DESC(otg_ver, "OTG revision supported 0=OTG 1.3 1=OTG 2.0");
++01214 
++
    Generated on Thu Oct 27 03:56:37 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
    ++doxygen 1.3.9.1
    + + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__driver_8c.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/dwc__otg__driver_8c.html 2013-07-26 19:31:20.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__driver_8c.html 2013-07-26 19:34:40.000000000 +0000 +@@ -2,522 +2,508 @@ + + DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_driver.c File Reference + +- + +- +-
    +-
    +-
    +-
    ++ ++
    Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
    +

    dwc_otg_driver.c File Reference

    The dwc_otg_driver module provides the initialization and cleanup entry points for the DWC_otg driver. More... +

    +-#include <linux/kernel.h>
    +-#include <linux/module.h>
    +-#include <linux/moduleparam.h>
    +-#include <linux/init.h>
    +-#include <linux/device.h>
    +-#include <linux/errno.h>
    +-#include <linux/types.h>
    +-#include <linux/stat.h>
    +-#include <linux/version.h>
    +-#include <linux/interrupt.h>
    +-#include <linux/irq.h>
    +-#include <asm/io.h>
    +-#include "dwc_os.h"
    +-#include "dwc_otg_dbg.h"
    +-#include "dwc_otg_driver.h"
    +-#include "dwc_otg_attr.h"
    +-#include "dwc_otg_core_if.h"
    +-#include "dwc_otg_pcd_if.h"
    +-#include "dwc_otg_hcd_if.h"
    ++#include "dwc_otg_os_dep.h"
    ++#include "dwc_os.h"
    ++#include "dwc_otg_dbg.h"
    ++#include "dwc_otg_driver.h"
    ++#include "dwc_otg_attr.h"
    ++#include "dwc_otg_core_if.h"
    ++#include "dwc_otg_pcd_if.h"
    ++#include "dwc_otg_hcd_if.h"
    + +

    + Go to the source code of this file. + + +- ++ + + +- ++ + +- ++ + + +- ++ + + +- ++ + +- +- ++ ++ + + +- ++ + +- +- ++ ++ ++ ++ ++ + + +- ++ + +- ++ + + +- ++ + + +- ++ + +- ++ + + +- ++ + + +- ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ + +- ++ + +- +- ++ + +- + +- ++ + +- ++ + +- + +- ++ + +- + +- ++ + +- + +- ++ + +- + +- ++ + +- + +- ++ + +- + +- ++ + +- + +- ++ + +- + +- ++ + +- + +- ++ + +- + +- ++ + +- + +- ++ + +- + +- ++ + +- + +- ++ + +- + +- ++ + +- + +- ++ + +- + +- ++ + +- + +- ++ + +- + +- ++ + +- + +- ++ + +- + +- ++ + +- + +- ++ + +- + +- +- +- + +- +- +- + +- +- +- + +- +- +- + +- +- +- + +- +- +- + +- ++ + +- + +- ++ + +- + +- ++ + +- + +- ++ + +- + +- ++ + +- + +- ++ + +- + +- ++ + +- + +- ++ + +- + +- ++ + +- + +- ++ + +- + +- ++ + +- + +- ++ + +- + +- ++ + +- + +- ++ + +- ++ + +- ++ + +- + +- ++ + +- + +- ++ + +- + +- ++ + +- + +- ++ + +- + +- ++ + +- + +- ++ + +- + +- ++ + +- + +- ++ + +- + +- ++ + +- + +- ++ + +- + +- +- +- + +- +- +- + +- +- +- + +- +- +- + +- +- +- + +- +- +- + +- ++ + +- + +- ++ + +- + +- ++ + +- + +- + +- + +- ++ + +- + +- ++ + +- + +- ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ + + +- ++ + +- ++ + +- ++ + + +

    Data Structures

    struct  dwc_otg_driver_module_params
    struct  dwc_otg_driver_module_params

    Defines

    +-#define DWC_DRIVER_VERSION   "2.90a 23-APR-2009"
    ++#define DWC_DRIVER_VERSION   "2.94a 27-OCT-2011"
    +-#define DWC_DRIVER_DESC   "HS OTG USB Controller driver"
    ++#define DWC_DRIVER_DESC   "HS OTG USB Controller driver"

    Functions

    +-int pcd_init ()
    ++int pcd_init ()
     This function initialized the PCD portion of the driver.
    int hcd_init ()
    int hcd_init ()
     Initializes the HCD.
    +-int pcd_remove ()
     Initializes the HCD.
    ++int pcd_remove ()
     Cleanup the PCD.
    void hcd_remove ()
    void hcd_remove ()
     Removes the HCD.
    +-static ssize_t version_show (struct device_driver *dev, char *buf)
     Removes the HCD.
    void dwc_otg_adp_start (dwc_otg_core_if_t *core_if, uint8_t is_host)
     Called right after driver is loaded to perform initial actions for ADP.
    ++ssize_t version_show (struct device_driver *dev, char *buf)
     This function shows the Driver Version.
    +-static DRIVER_ATTR (version, S_IRUGO, version_show, NULL)
    ++ DRIVER_ATTR (version, S_IRUGO, version_show, NULL)
    +-static ssize_t dbg_level_show (struct device_driver *drv, char *buf)
    ++ssize_t dbg_level_show (struct device_driver *drv, char *buf)
     This function shows the driver Debug Level.
    +-static ssize_t dbg_level_store (struct device_driver *drv, const char *buf, size_t count)
    ++ssize_t dbg_level_store (struct device_driver *drv, const char *buf, size_t count)
     This function stores the driver Debug Level.
    +-static DRIVER_ATTR (debuglevel, S_IRUGO|S_IWUSR, dbg_level_show, dbg_level_store)
    ++ DRIVER_ATTR (debuglevel, S_IRUGO|S_IWUSR, dbg_level_show, dbg_level_store)
    +-static int set_parameters (dwc_otg_core_if_t *core_if)
    ++int set_parameters (dwc_otg_core_if_t *core_if)
     This function is called during module intialization to pass module parameters to the DWC_OTG CORE.
    +-static irqreturn_t dwc_otg_common_irq (int irq, void *dev)
    ++irqreturn_t dwc_otg_common_irq (int irq, void *dev)
     This function is the top level interrupt handler for the Common (Device and host modes) interrupts.
    static void dwc_otg_driver_remove ()
    void dwc_otg_driver_remove ()
     This function is called when a lm_device is unregistered with the dwc_otg_driver.
    static int dwc_otg_driver_probe ()
     This function is called when a lm_device is unregistered with the dwc_otg_driver.
    int dwc_otg_driver_probe ()
     This function is called when an lm_device is bound to a dwc_otg_driver.
    static int __init dwc_otg_driver_init (void)
     This function is called when an lm_device is bound to a dwc_otg_driver.
    int __init dwc_otg_driver_init (void)
     This function is called when the dwc_otg_driver is installed with the insmod command.
    ++
     This function is called when the dwc_otg_driver is installed with the insmod command.
    +  module_init (dwc_otg_driver_init)
    static void __exit dwc_otg_driver_cleanup (void)
    void __exit dwc_otg_driver_cleanup (void)
     This function is called when the driver is removed from the kernel with the rmmod command.
    ++
     This function is called when the driver is removed from the kernel with the rmmod command.
    +  module_exit (dwc_otg_driver_cleanup)
    ++
    +  MODULE_DESCRIPTION (DWC_DRIVER_DESC)
    +- MODULE_AUTHOR ("Synopsys Inc.")
    ++ MODULE_AUTHOR ("Synopsys Inc.")
    +- MODULE_LICENSE ("GPL")
    ++ MODULE_LICENSE ("GPL")
    ++
    +  module_param_named (otg_cap, dwc_otg_module_params.otg_cap, int, 0444)
    +- MODULE_PARM_DESC (otg_cap,"OTG Capabilities 0=HNP&SRP 1=SRP Only 2=None")
    ++ MODULE_PARM_DESC (otg_cap,"OTG Capabilities 0=HNP&SRP 1=SRP Only 2=None")
    ++
    +  module_param_named (opt, dwc_otg_module_params.opt, int, 0444)
    +- MODULE_PARM_DESC (opt,"OPT Mode")
    ++ MODULE_PARM_DESC (opt,"OPT Mode")
    ++
    +  module_param_named (dma_enable, dwc_otg_module_params.dma_enable, int, 0444)
    +- MODULE_PARM_DESC (dma_enable,"DMA Mode 0=Slave 1=DMA enabled")
    ++ MODULE_PARM_DESC (dma_enable,"DMA Mode 0=Slave 1=DMA enabled")
    ++
    +  module_param_named (dma_desc_enable, dwc_otg_module_params.dma_desc_enable, int, 0444)
    +- MODULE_PARM_DESC (dma_desc_enable,"DMA Desc Mode 0=Address DMA 1=DMA Descriptor enabled")
    ++ MODULE_PARM_DESC (dma_desc_enable,"DMA Desc Mode 0=Address DMA 1=DMA Descriptor enabled")
    ++
    +  module_param_named (dma_burst_size, dwc_otg_module_params.dma_burst_size, int, 0444)
    +- MODULE_PARM_DESC (dma_burst_size,"DMA Burst Size 1, 4, 8, 16, 32, 64, 128, 256")
    ++ MODULE_PARM_DESC (dma_burst_size,"DMA Burst Size 1, 4, 8, 16, 32, 64, 128, 256")
    ++
    +  module_param_named (speed, dwc_otg_module_params.speed, int, 0444)
    +- MODULE_PARM_DESC (speed,"Speed 0=High Speed 1=Full Speed")
    ++ MODULE_PARM_DESC (speed,"Speed 0=High Speed 1=Full Speed")
    ++
    +  module_param_named (host_support_fs_ls_low_power, dwc_otg_module_params.host_support_fs_ls_low_power, int, 0444)
    +- MODULE_PARM_DESC (host_support_fs_ls_low_power,"Support Low Power w/FS or LS 0=Support 1=Don't Support")
    ++ MODULE_PARM_DESC (host_support_fs_ls_low_power,"Support Low Power w/FS or LS 0=Support 1=Don't Support")
    ++
    +  module_param_named (host_ls_low_power_phy_clk, dwc_otg_module_params.host_ls_low_power_phy_clk, int, 0444)
    +- MODULE_PARM_DESC (host_ls_low_power_phy_clk,"Low Speed Low Power Clock 0=48Mhz 1=6Mhz")
    ++ MODULE_PARM_DESC (host_ls_low_power_phy_clk,"Low Speed Low Power Clock 0=48Mhz 1=6Mhz")
    ++
    +  module_param_named (enable_dynamic_fifo, dwc_otg_module_params.enable_dynamic_fifo, int, 0444)
    +- MODULE_PARM_DESC (enable_dynamic_fifo,"0=cC Setting 1=Allow Dynamic Sizing")
    ++ MODULE_PARM_DESC (enable_dynamic_fifo,"0=cC Setting 1=Allow Dynamic Sizing")
    ++
    +  module_param_named (data_fifo_size, dwc_otg_module_params.data_fifo_size, int, 0444)
    +- MODULE_PARM_DESC (data_fifo_size,"Total number of words in the data FIFO memory 32-32768")
    ++ MODULE_PARM_DESC (data_fifo_size,"Total number of words in the data FIFO memory 32-32768")
    ++
    +  module_param_named (dev_rx_fifo_size, dwc_otg_module_params.dev_rx_fifo_size, int, 0444)
    +- MODULE_PARM_DESC (dev_rx_fifo_size,"Number of words in the Rx FIFO 16-32768")
    ++ MODULE_PARM_DESC (dev_rx_fifo_size,"Number of words in the Rx FIFO 16-32768")
    ++
    +  module_param_named (dev_nperio_tx_fifo_size, dwc_otg_module_params.dev_nperio_tx_fifo_size, int, 0444)
    +- MODULE_PARM_DESC (dev_nperio_tx_fifo_size,"Number of words in the non-periodic Tx FIFO 16-32768")
    ++ MODULE_PARM_DESC (dev_nperio_tx_fifo_size,"Number of words in the non-periodic Tx FIFO 16-32768")
    ++
    +  module_param_named (dev_perio_tx_fifo_size_1, dwc_otg_module_params.dev_perio_tx_fifo_size[0], int, 0444)
    +- MODULE_PARM_DESC (dev_perio_tx_fifo_size_1,"Number of words in the periodic Tx FIFO 4-768")
    ++ MODULE_PARM_DESC (dev_perio_tx_fifo_size_1,"Number of words in the periodic Tx FIFO 4-768")
    ++
    +  module_param_named (dev_perio_tx_fifo_size_2, dwc_otg_module_params.dev_perio_tx_fifo_size[1], int, 0444)
    +- MODULE_PARM_DESC (dev_perio_tx_fifo_size_2,"Number of words in the periodic Tx FIFO 4-768")
    ++ MODULE_PARM_DESC (dev_perio_tx_fifo_size_2,"Number of words in the periodic Tx FIFO 4-768")
    ++
    +  module_param_named (dev_perio_tx_fifo_size_3, dwc_otg_module_params.dev_perio_tx_fifo_size[2], int, 0444)
    +- MODULE_PARM_DESC (dev_perio_tx_fifo_size_3,"Number of words in the periodic Tx FIFO 4-768")
    ++ MODULE_PARM_DESC (dev_perio_tx_fifo_size_3,"Number of words in the periodic Tx FIFO 4-768")
    ++
    +  module_param_named (dev_perio_tx_fifo_size_4, dwc_otg_module_params.dev_perio_tx_fifo_size[3], int, 0444)
    +- MODULE_PARM_DESC (dev_perio_tx_fifo_size_4,"Number of words in the periodic Tx FIFO 4-768")
    ++ MODULE_PARM_DESC (dev_perio_tx_fifo_size_4,"Number of words in the periodic Tx FIFO 4-768")
    ++
    +  module_param_named (dev_perio_tx_fifo_size_5, dwc_otg_module_params.dev_perio_tx_fifo_size[4], int, 0444)
    +- MODULE_PARM_DESC (dev_perio_tx_fifo_size_5,"Number of words in the periodic Tx FIFO 4-768")
    ++ MODULE_PARM_DESC (dev_perio_tx_fifo_size_5,"Number of words in the periodic Tx FIFO 4-768")
    ++
    +  module_param_named (dev_perio_tx_fifo_size_6, dwc_otg_module_params.dev_perio_tx_fifo_size[5], int, 0444)
    +- MODULE_PARM_DESC (dev_perio_tx_fifo_size_6,"Number of words in the periodic Tx FIFO 4-768")
    ++ MODULE_PARM_DESC (dev_perio_tx_fifo_size_6,"Number of words in the periodic Tx FIFO 4-768")
    ++
    +  module_param_named (dev_perio_tx_fifo_size_7, dwc_otg_module_params.dev_perio_tx_fifo_size[6], int, 0444)
    +- MODULE_PARM_DESC (dev_perio_tx_fifo_size_7,"Number of words in the periodic Tx FIFO 4-768")
    ++ MODULE_PARM_DESC (dev_perio_tx_fifo_size_7,"Number of words in the periodic Tx FIFO 4-768")
    ++
    +  module_param_named (dev_perio_tx_fifo_size_8, dwc_otg_module_params.dev_perio_tx_fifo_size[7], int, 0444)
    +- MODULE_PARM_DESC (dev_perio_tx_fifo_size_8,"Number of words in the periodic Tx FIFO 4-768")
    ++ MODULE_PARM_DESC (dev_perio_tx_fifo_size_8,"Number of words in the periodic Tx FIFO 4-768")
    ++
    +  module_param_named (dev_perio_tx_fifo_size_9, dwc_otg_module_params.dev_perio_tx_fifo_size[8], int, 0444)
    +- MODULE_PARM_DESC (dev_perio_tx_fifo_size_9,"Number of words in the periodic Tx FIFO 4-768")
    ++ MODULE_PARM_DESC (dev_perio_tx_fifo_size_9,"Number of words in the periodic Tx FIFO 4-768")
    ++
    +  module_param_named (dev_perio_tx_fifo_size_10, dwc_otg_module_params.dev_perio_tx_fifo_size[9], int, 0444)
    +- MODULE_PARM_DESC (dev_perio_tx_fifo_size_10,"Number of words in the periodic Tx FIFO 4-768")
    ++
    +  module_param_named (dev_perio_tx_fifo_size_11, dwc_otg_module_params.dev_perio_tx_fifo_size[10], int, 0444)
    +- MODULE_PARM_DESC (dev_perio_tx_fifo_size_11,"Number of words in the periodic Tx FIFO 4-768")
    ++
    +  module_param_named (dev_perio_tx_fifo_size_12, dwc_otg_module_params.dev_perio_tx_fifo_size[11], int, 0444)
    +- MODULE_PARM_DESC (dev_perio_tx_fifo_size_12,"Number of words in the periodic Tx FIFO 4-768")
    ++
    +  module_param_named (dev_perio_tx_fifo_size_13, dwc_otg_module_params.dev_perio_tx_fifo_size[12], int, 0444)
    +- MODULE_PARM_DESC (dev_perio_tx_fifo_size_13,"Number of words in the periodic Tx FIFO 4-768")
    ++
    +  module_param_named (dev_perio_tx_fifo_size_14, dwc_otg_module_params.dev_perio_tx_fifo_size[13], int, 0444)
    +- MODULE_PARM_DESC (dev_perio_tx_fifo_size_14,"Number of words in the periodic Tx FIFO 4-768")
    ++
    +  module_param_named (dev_perio_tx_fifo_size_15, dwc_otg_module_params.dev_perio_tx_fifo_size[14], int, 0444)
    +- MODULE_PARM_DESC (dev_perio_tx_fifo_size_15,"Number of words in the periodic Tx FIFO 4-768")
    ++
    +  module_param_named (host_rx_fifo_size, dwc_otg_module_params.host_rx_fifo_size, int, 0444)
    +- MODULE_PARM_DESC (host_rx_fifo_size,"Number of words in the Rx FIFO 16-32768")
    ++ MODULE_PARM_DESC (host_rx_fifo_size,"Number of words in the Rx FIFO 16-32768")
    ++
    +  module_param_named (host_nperio_tx_fifo_size, dwc_otg_module_params.host_nperio_tx_fifo_size, int, 0444)
    +- MODULE_PARM_DESC (host_nperio_tx_fifo_size,"Number of words in the non-periodic Tx FIFO 16-32768")
    ++ MODULE_PARM_DESC (host_nperio_tx_fifo_size,"Number of words in the non-periodic Tx FIFO 16-32768")
    ++
    +  module_param_named (host_perio_tx_fifo_size, dwc_otg_module_params.host_perio_tx_fifo_size, int, 0444)
    +- MODULE_PARM_DESC (host_perio_tx_fifo_size,"Number of words in the host periodic Tx FIFO 16-32768")
    ++ MODULE_PARM_DESC (host_perio_tx_fifo_size,"Number of words in the host periodic Tx FIFO 16-32768")
    ++
    +  module_param_named (max_transfer_size, dwc_otg_module_params.max_transfer_size, int, 0444)
     MODULE_PARM_DESC (max_transfer_size,"The maximum transfer size supported in bytes 2047-65535")
     MODULE_PARM_DESC (max_transfer_size,"The maximum transfer size supported in bytes 2047-65535")
    ++
    +  module_param_named (max_packet_count, dwc_otg_module_params.max_packet_count, int, 0444)
    +- MODULE_PARM_DESC (max_packet_count,"The maximum number of packets in a transfer 15-511")
    ++ MODULE_PARM_DESC (max_packet_count,"The maximum number of packets in a transfer 15-511")
    ++
    +  module_param_named (host_channels, dwc_otg_module_params.host_channels, int, 0444)
    +- MODULE_PARM_DESC (host_channels,"The number of host channel registers to use 1-16")
    ++ MODULE_PARM_DESC (host_channels,"The number of host channel registers to use 1-16")
    ++
    +  module_param_named (dev_endpoints, dwc_otg_module_params.dev_endpoints, int, 0444)
    +- MODULE_PARM_DESC (dev_endpoints,"The number of endpoints in addition to EP0 available for device mode 1-15")
    ++ MODULE_PARM_DESC (dev_endpoints,"The number of endpoints in addition to EP0 available for device mode 1-15")
    ++
    +  module_param_named (phy_type, dwc_otg_module_params.phy_type, int, 0444)
    +- MODULE_PARM_DESC (phy_type,"0=Reserved 1=UTMI+ 2=ULPI")
    ++ MODULE_PARM_DESC (phy_type,"0=Reserved 1=UTMI+ 2=ULPI")
    ++
    +  module_param_named (phy_utmi_width, dwc_otg_module_params.phy_utmi_width, int, 0444)
    +- MODULE_PARM_DESC (phy_utmi_width,"Specifies the UTMI+ Data Width 8 or 16 bits")
    ++ MODULE_PARM_DESC (phy_utmi_width,"Specifies the UTMI+ Data Width 8 or 16 bits")
    ++
    +  module_param_named (phy_ulpi_ddr, dwc_otg_module_params.phy_ulpi_ddr, int, 0444)
    +- MODULE_PARM_DESC (phy_ulpi_ddr,"ULPI at double or single data rate 0=Single 1=Double")
    ++ MODULE_PARM_DESC (phy_ulpi_ddr,"ULPI at double or single data rate 0=Single 1=Double")
    ++
    +  module_param_named (phy_ulpi_ext_vbus, dwc_otg_module_params.phy_ulpi_ext_vbus, int, 0444)
    +- MODULE_PARM_DESC (phy_ulpi_ext_vbus,"ULPI PHY using internal or external vbus 0=Internal")
    ++ MODULE_PARM_DESC (phy_ulpi_ext_vbus,"ULPI PHY using internal or external vbus 0=Internal")
    ++
    +  module_param_named (i2c_enable, dwc_otg_module_params.i2c_enable, int, 0444)
    +- MODULE_PARM_DESC (i2c_enable,"FS PHY Interface")
    ++ MODULE_PARM_DESC (i2c_enable,"FS PHY Interface")
    ++
    +  module_param_named (ulpi_fs_ls, dwc_otg_module_params.ulpi_fs_ls, int, 0444)
    +- MODULE_PARM_DESC (ulpi_fs_ls,"ULPI PHY FS/LS mode only")
    ++ MODULE_PARM_DESC (ulpi_fs_ls,"ULPI PHY FS/LS mode only")
    ++
    +  module_param_named (ts_dline, dwc_otg_module_params.ts_dline, int, 0444)
    +- MODULE_PARM_DESC (ts_dline,"Term select Dline pulsing for all PHYs")
    ++ MODULE_PARM_DESC (ts_dline,"Term select Dline pulsing for all PHYs")
    +- module_param_named (debug, g_dbg_lvl, int, 0444)
    ++ module_param_named (debug, g_dbg_lvl, int, 0444)
    +- MODULE_PARM_DESC (debug,"")
    ++ MODULE_PARM_DESC (debug,"")
    ++
    +  module_param_named (en_multiple_tx_fifo, dwc_otg_module_params.en_multiple_tx_fifo, int, 0444)
    +- MODULE_PARM_DESC (en_multiple_tx_fifo,"Dedicated Non Periodic Tx FIFOs 0=disabled 1=enabled")
    ++ MODULE_PARM_DESC (en_multiple_tx_fifo,"Dedicated Non Periodic Tx FIFOs 0=disabled 1=enabled")
    ++
    +  module_param_named (dev_tx_fifo_size_1, dwc_otg_module_params.dev_tx_fifo_size[0], int, 0444)
    +- MODULE_PARM_DESC (dev_tx_fifo_size_1,"Number of words in the Tx FIFO 4-768")
    ++ MODULE_PARM_DESC (dev_tx_fifo_size_1,"Number of words in the Tx FIFO 4-768")
    ++
    +  module_param_named (dev_tx_fifo_size_2, dwc_otg_module_params.dev_tx_fifo_size[1], int, 0444)
    +- MODULE_PARM_DESC (dev_tx_fifo_size_2,"Number of words in the Tx FIFO 4-768")
    ++ MODULE_PARM_DESC (dev_tx_fifo_size_2,"Number of words in the Tx FIFO 4-768")
    ++
    +  module_param_named (dev_tx_fifo_size_3, dwc_otg_module_params.dev_tx_fifo_size[2], int, 0444)
    +- MODULE_PARM_DESC (dev_tx_fifo_size_3,"Number of words in the Tx FIFO 4-768")
    ++ MODULE_PARM_DESC (dev_tx_fifo_size_3,"Number of words in the Tx FIFO 4-768")
    ++
    +  module_param_named (dev_tx_fifo_size_4, dwc_otg_module_params.dev_tx_fifo_size[3], int, 0444)
    +- MODULE_PARM_DESC (dev_tx_fifo_size_4,"Number of words in the Tx FIFO 4-768")
    ++ MODULE_PARM_DESC (dev_tx_fifo_size_4,"Number of words in the Tx FIFO 4-768")
    ++
    +  module_param_named (dev_tx_fifo_size_5, dwc_otg_module_params.dev_tx_fifo_size[4], int, 0444)
    +- MODULE_PARM_DESC (dev_tx_fifo_size_5,"Number of words in the Tx FIFO 4-768")
    ++ MODULE_PARM_DESC (dev_tx_fifo_size_5,"Number of words in the Tx FIFO 4-768")
    ++
    +  module_param_named (dev_tx_fifo_size_6, dwc_otg_module_params.dev_tx_fifo_size[5], int, 0444)
    +- MODULE_PARM_DESC (dev_tx_fifo_size_6,"Number of words in the Tx FIFO 4-768")
    ++ MODULE_PARM_DESC (dev_tx_fifo_size_6,"Number of words in the Tx FIFO 4-768")
    ++
    +  module_param_named (dev_tx_fifo_size_7, dwc_otg_module_params.dev_tx_fifo_size[6], int, 0444)
    +- MODULE_PARM_DESC (dev_tx_fifo_size_7,"Number of words in the Tx FIFO 4-768")
    ++ MODULE_PARM_DESC (dev_tx_fifo_size_7,"Number of words in the Tx FIFO 4-768")
    ++
    +  module_param_named (dev_tx_fifo_size_8, dwc_otg_module_params.dev_tx_fifo_size[7], int, 0444)
    +- MODULE_PARM_DESC (dev_tx_fifo_size_8,"Number of words in the Tx FIFO 4-768")
    ++ MODULE_PARM_DESC (dev_tx_fifo_size_8,"Number of words in the Tx FIFO 4-768")
    ++
    +  module_param_named (dev_tx_fifo_size_9, dwc_otg_module_params.dev_tx_fifo_size[8], int, 0444)
    +- MODULE_PARM_DESC (dev_tx_fifo_size_9,"Number of words in the Tx FIFO 4-768")
    ++ MODULE_PARM_DESC (dev_tx_fifo_size_9,"Number of words in the Tx FIFO 4-768")
    ++
    +  module_param_named (dev_tx_fifo_size_10, dwc_otg_module_params.dev_tx_fifo_size[9], int, 0444)
    +- MODULE_PARM_DESC (dev_tx_fifo_size_10,"Number of words in the Tx FIFO 4-768")
    ++
    +  module_param_named (dev_tx_fifo_size_11, dwc_otg_module_params.dev_tx_fifo_size[10], int, 0444)
    +- MODULE_PARM_DESC (dev_tx_fifo_size_11,"Number of words in the Tx FIFO 4-768")
    ++
    +  module_param_named (dev_tx_fifo_size_12, dwc_otg_module_params.dev_tx_fifo_size[11], int, 0444)
    +- MODULE_PARM_DESC (dev_tx_fifo_size_12,"Number of words in the Tx FIFO 4-768")
    ++
    +  module_param_named (dev_tx_fifo_size_13, dwc_otg_module_params.dev_tx_fifo_size[12], int, 0444)
    +- MODULE_PARM_DESC (dev_tx_fifo_size_13,"Number of words in the Tx FIFO 4-768")
    ++
    +  module_param_named (dev_tx_fifo_size_14, dwc_otg_module_params.dev_tx_fifo_size[13], int, 0444)
    +- MODULE_PARM_DESC (dev_tx_fifo_size_14,"Number of words in the Tx FIFO 4-768")
    ++
    +  module_param_named (dev_tx_fifo_size_15, dwc_otg_module_params.dev_tx_fifo_size[14], int, 0444)
    +- MODULE_PARM_DESC (dev_tx_fifo_size_15,"Number of words in the Tx FIFO 4-768")
    ++
    +  module_param_named (thr_ctl, dwc_otg_module_params.thr_ctl, int, 0444)
    +- MODULE_PARM_DESC (thr_ctl,"Thresholding enable flag bit 0 - non ISO Tx thr., 1 - ISO Tx thr., 2 - Rx thr.- bit 0=disabled 1=enabled")
    ++ MODULE_PARM_DESC (thr_ctl,"Thresholding enable flag bit 0 - non ISO Tx thr., 1 - ISO Tx thr., 2 - Rx thr.- bit 0=disabled 1=enabled")
    ++
    +  module_param_named (tx_thr_length, dwc_otg_module_params.tx_thr_length, int, 0444)
    +- MODULE_PARM_DESC (tx_thr_length,"Tx Threshold length in 32 bit DWORDs")
    ++ MODULE_PARM_DESC (tx_thr_length,"Tx Threshold length in 32 bit DWORDs")
    ++
    +  module_param_named (rx_thr_length, dwc_otg_module_params.rx_thr_length, int, 0444)
    +- MODULE_PARM_DESC (rx_thr_length,"Rx Threshold length in 32 bit DWORDs")
    ++ MODULE_PARM_DESC (rx_thr_length,"Rx Threshold length in 32 bit DWORDs")
    ++
    +  module_param_named (pti_enable, dwc_otg_module_params.pti_enable, int, 0444)
    ++
    +  module_param_named (mpi_enable, dwc_otg_module_params.mpi_enable, int, 0444)
    ++
    +  module_param_named (lpm_enable, dwc_otg_module_params.lpm_enable, int, 0444)
    +- MODULE_PARM_DESC (lpm_enable,"LPM Enable 0=LPM Disabled 1=LPM Enabled")
    ++ MODULE_PARM_DESC (lpm_enable,"LPM Enable 0=LPM Disabled 1=LPM Enabled")
    ++
    +  module_param_named (ic_usb_cap, dwc_otg_module_params.ic_usb_cap, int, 0444)
    +- MODULE_PARM_DESC (ic_usb_cap,"IC_USB Capability 0=IC_USB Disabled 1=IC_USB Enabled")
    ++ MODULE_PARM_DESC (ic_usb_cap,"IC_USB Capability 0=IC_USB Disabled 1=IC_USB Enabled")
    ++
    +  module_param_named (ahb_thr_ratio, dwc_otg_module_params.ahb_thr_ratio, int, 0444)
    +- MODULE_PARM_DESC (ahb_thr_ratio,"AHB Threshold Ratio")
    ++ MODULE_PARM_DESC (ahb_thr_ratio,"AHB Threshold Ratio")
    ++ module_param_named (power_down, dwc_otg_module_params.power_down, int, 0444)
    ++ MODULE_PARM_DESC (power_down,"Power Down Mode")
    ++ module_param_named (reload_ctl, dwc_otg_module_params.reload_ctl, int, 0444)
    ++ MODULE_PARM_DESC (reload_ctl,"HFIR Reload Control")
    ++ module_param_named (dev_out_nak, dwc_otg_module_params.dev_out_nak, int, 0444)
    ++ MODULE_PARM_DESC (dev_out_nak,"Enable Device OUT NAK")
    ++ module_param_named (cont_on_bna, dwc_otg_module_params.cont_on_bna, int, 0444)
    ++ MODULE_PARM_DESC (cont_on_bna,"Enable Enable Continue on BNA")
    ++ module_param_named (ahb_single, dwc_otg_module_params.ahb_single, int, 0444)
    ++ MODULE_PARM_DESC (ahb_single,"Enable AHB Single Support")
    ++ module_param_named (adp_enable, dwc_otg_module_params.adp_enable, int, 0444)
    ++ MODULE_PARM_DESC (adp_enable,"ADP Enable 0=ADP Disabled 1=ADP Enabled")
    ++ module_param_named (otg_ver, dwc_otg_module_params.otg_ver, int, 0444)
    ++ MODULE_PARM_DESC (otg_ver,"OTG revision supported 0=OTG 1.3 1=OTG 2.0")

    Variables

    +-static const char dwc_driver_name [] = "dwc_otg"
    ++const char dwc_driver_name [] = "dwc_otg"
    +-static struct dwc_otg_driver_module_params dwc_otg_module_params
    ++dwc_otg_driver_module_params dwc_otg_module_params
    +-uint32_t g_dbg_lvl = 0
    ++uint32_t g_dbg_lvl = 0
     The Debug Level bit-mask variable.
    +@@ -525,69 +511,140 @@ + The dwc_otg_driver module provides the initialization and cleanup entry points for the DWC_otg driver. +

    + This module will be dynamically installed after Linux is booted using the insmod command. When the module is installed, the dwc_otg_driver_init function is called. When the module is removed (using rmmod), the dwc_otg_driver_cleanup function is called.

    +-This module also defines a data structure for the dwc_otg_driver, which is used in conjunction with the standard ARM lm_device structure. These structures allow the OTG driver to comply with the standard Linux driver model in which devices and drivers are registered with a bus driver. This has the benefit that Linux can expose attributes of the driver and device in its special sysfs file system. Users can then read or write files in this file system to perform diagnostics on the driver components or the device. ++This module also defines a data structure for the dwc_otg_driver, which is used in conjunction with the standard ARM lm_device structure. These structures allow the OTG driver to comply with the standard Linux driver model in which devices and drivers are registered with a bus driver. This has the benefit that Linux can expose attributes of the driver and device in its special sysfs file system. Users can then read or write files in this file system to perform diagnostics on the driver components or the device. +

    + Definition in file dwc_otg_driver.c.

    Function Documentation

    +- +-
    +-
    +- +- +- +- +- +- +- ++

    ++

    int hcd_init (  ) 
    ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ + +
    int hcd_init (   ) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Initializes the HCD. +

    + This function allocates memory for and initializes the static parts of the usb_hcd and dwc_otg_hcd structures. It also registers the USB bus with the core and calls the hc_driver->start() function. It returns a negative error on failure. +

    +-Definition at line 327 of file dwc_otg_hcd_linux.c. +- +-

    +- +-

    +-
    +- +- +- +- +- +- +- ++Definition at line 339 of file dwc_otg_hcd_linux.c. ++ ++
    void hcd_remove (  ) 
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ + +
    void hcd_remove (   ) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Removes the HCD. +

    + Frees memory and resources associated with the HCD and deregisters the bus. +

    +-Definition at line 417 of file dwc_otg_hcd_linux.c. +- +-

    +- +-

    +-
    +- +- +- +- +- +- +- ++Definition at line 441 of file dwc_otg_hcd_linux.c. ++ ++
    static void dwc_otg_driver_remove (  )  [static]
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
    void dwc_otg_adp_start ( dwc_otg_core_if_t *  core_if,
    uint8_t  is_host
    ) 
    ++
    ++ ++ ++ ++ ++ ++
    ++   ++ ++ ++

    ++Called right after driver is loaded to perform initial actions for ADP. ++

    ++

    Parameters:
    ++ ++ ++ ++
    core_if the pointer to core_if structure.
    is_host - flag for current mode of operation either from GINTSTS or GPWRDN
    ++
    ++ ++

    ++Definition at line 458 of file dwc_otg_adp.c.

    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ + +
    void dwc_otg_driver_remove (   )  [static]
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + This function is called when a lm_device is unregistered with the dwc_otg_driver. +@@ -600,23 +657,31 @@ + + +

    +-Definition at line 525 of file dwc_otg_driver.c. +- +-

    +- +-

    +-
    +- +- +- +- +- +- +- ++Definition at line 561 of file dwc_otg_driver.c. ++ ++
    static int dwc_otg_driver_probe (  )  [static]
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ + +
    int dwc_otg_driver_probe (   )  [static]
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + This function is called when an lm_device is bound to a dwc_otg_driver. +@@ -629,24 +694,32 @@ + + +

    +-Definition at line 608 of file dwc_otg_driver.c. +- +-

    +- +-

    +-
    +- +- +- +- +- +- +- +- ++Definition at line 651 of file dwc_otg_driver.c. ++ ++
    static int __init dwc_otg_driver_init (void   )  [static]
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ + +
    int __init dwc_otg_driver_init ( void   )  [static]
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + This function is called when the dwc_otg_driver is installed with the insmod command. +@@ -655,65 +728,81 @@ +

    Returns:
    + +

    +-Definition at line 866 of file dwc_otg_driver.c. +- +-

    +- +-

    +-
    +- +- +- +- +- +- +- +- ++Definition at line 924 of file dwc_otg_driver.c. ++ ++
    static void __exit dwc_otg_driver_cleanup (void   )  [static]
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ + +
    void __exit dwc_otg_driver_cleanup ( void   )  [static]
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + This function is called when the driver is removed from the kernel with the rmmod command. +

    + The driver unregisters itself with its bus driver. +

    +-Definition at line 899 of file dwc_otg_driver.c. +- +-

    +- +-

    +-
    +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- ++Definition at line 957 of file dwc_otg_driver.c. ++ ++
    MODULE_PARM_DESC (max_transfer_size ,
    "The maximum transfer size supported in bytes 2047-65535"  
    )
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ + +
    MODULE_PARM_DESC ( max_transfer_size ,
    "The maximum transfer size supported in bytes 2047-65535" 
    ) 
    +- +-
    ++
    ++ ++ ++ ++ ++ ++
    ++   ++ + +

    +-

    Todo:
    Set the max to 512K, modify checks
    +- +- +-

    +-

    Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++
    Todo:
    Set the max to 512K, modify checks
    ++
    ++

    Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
    ++doxygen 1.3.9.1 + + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__driver_8h-source.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/dwc__otg__driver_8h-source.html 2013-07-26 19:31:20.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__driver_8h-source.html 2013-07-26 19:34:40.000000000 +0000 +@@ -2,109 +2,83 @@ + + DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_driver.h Source File + +- + +- +-
    +-
    +-
    +-
    +-

    dwc_otg_driver.h

    Go to the documentation of this file.
    00001 /* ==========================================================================
+-00002  * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_driver.h $
+-00003  * $Revision: #16 $
+-00004  * $Date: 2009/04/03 $
+-00005  * $Change: 1225160 $
+-00006  *
+-00007  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
+-00008  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
+-00009  * otherwise expressly agreed to in writing between Synopsys and you.
+-00010  * 
+-00011  * The Software IS NOT an item of Licensed Software or Licensed Product under
+-00012  * any End User Software License Agreement or Agreement for Licensed Product
+-00013  * with Synopsys or any supplement thereto. You are permitted to use and
+-00014  * redistribute this Software in source and binary forms, with or without
+-00015  * modification, provided that redistributions of source code must retain this
+-00016  * notice. You may not view, use, disclose, copy or distribute this file or
+-00017  * any information contained herein except pursuant to this license grant from
+-00018  * Synopsys. If you do not agree with this notice, including the disclaimer
+-00019  * below, then you are not authorized to use the Software.
+-00020  * 
+-00021  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
+-00022  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+-00023  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+-00024  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
+-00025  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+-00026  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+-00027  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+-00028  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+-00029  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+-00030  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+-00031  * DAMAGE.
+-00032  * ========================================================================== */
+-00033 
+-00034 #ifndef __DWC_OTG_DRIVER_H__
+-00035 #define __DWC_OTG_DRIVER_H__
+-00036 
+-00040 #include "dwc_otg_core_if.h"
+-00041 
+-00042 /* Type declarations */
+-00043 struct dwc_otg_pcd;
+-00044 struct dwc_otg_hcd;
+-00045 
+-00046 #ifdef  PCI_INTERFACE
+-00047 #include <linux/pci.h>
+-00048 #endif
+-00049 
+-00050 
+-00051 
+-00056 typedef struct dwc_otg_device {
+-00058         void *base;
+-00059 
+-00060 #ifdef LM_INTERFACE
+-00061         struct lm_device *lmdev;
+-00062 #elif  PCI_INTERFACE
+-00063         int rsrc_start;
+-00064         int rsrc_len;
+-00065 #endif
+-00066 
+-00068         dwc_otg_core_if_t *core_if;
+-00069 
+-00071         uint32_t reg_offset;
+-00072 
+-00074         struct dwc_otg_pcd *pcd;
+-00075 
+-00077         struct dwc_otg_hcd *hcd;
+-00078 
+-00080         uint8_t common_irq_installed;
+-00081 
+-00082 } dwc_otg_device_t;
+-00083 
+-00084 /*We must clear S3C24XX_EINTPEND external interrupt register 
+-00085  * because after clearing in this register trigerred IRQ from 
+-00086  * H/W core in kernel interrupt can be occured again before OTG
+-00087  * handlers clear all IRQ sources of Core registers because of
+-00088  * timing latencies and Low Level IRQ Type.
+-00089  */
+-00090 #ifdef CONFIG_MACH_IPMATE
+-00091 #define  S3C2410X_CLEAR_EINTPEND()   \
+-00092 do { \
+-00093         __raw_writel(1UL << 11,S3C24XX_EINTPEND); \
+-00094 } while (0)
+-00095 #else
+-00096 #define  S3C2410X_CLEAR_EINTPEND()   do { } while (0)
+-00097 #endif
+-00098 
+-00099 #endif
+-
    Generated on Tue May 5 02:22:48 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++
    Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
    ++

    dwc_otg_driver.h

    Go to the documentation of this file.
    00001 /* ==========================================================================
++00002  * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_driver.h $
++00003  * $Revision: #19 $
++00004  * $Date: 2010/11/15 $
++00005  * $Change: 1627671 $
++00006  *
++00007  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
++00008  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
++00009  * otherwise expressly agreed to in writing between Synopsys and you.
++00010  * 
++00011  * The Software IS NOT an item of Licensed Software or Licensed Product under
++00012  * any End User Software License Agreement or Agreement for Licensed Product
++00013  * with Synopsys or any supplement thereto. You are permitted to use and
++00014  * redistribute this Software in source and binary forms, with or without
++00015  * modification, provided that redistributions of source code must retain this
++00016  * notice. You may not view, use, disclose, copy or distribute this file or
++00017  * any information contained herein except pursuant to this license grant from
++00018  * Synopsys. If you do not agree with this notice, including the disclaimer
++00019  * below, then you are not authorized to use the Software.
++00020  * 
++00021  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
++00022  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++00023  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++00024  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
++00025  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++00026  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
++00027  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
++00028  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
++00029  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
++00030  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
++00031  * DAMAGE.
++00032  * ========================================================================== */
++00033 
++00034 #ifndef __DWC_OTG_DRIVER_H__
++00035 #define __DWC_OTG_DRIVER_H__
++00036 
++00040 #include "dwc_otg_os_dep.h"
++00041 #include "dwc_otg_core_if.h"
++00042 
++00043 /* Type declarations */
++00044 struct dwc_otg_pcd;
++00045 struct dwc_otg_hcd;
++00046 
++00051 typedef struct dwc_otg_device {
++00055         struct os_dependent os_dep;
++00056 
++00058         dwc_otg_core_if_t *core_if;
++00059 
++00061         struct dwc_otg_pcd *pcd;
++00062 
++00064         struct dwc_otg_hcd *hcd;
++00065 
++00067         uint8_t common_irq_installed;
++00068 
++00069 } dwc_otg_device_t;
++00070 
++00071 /*We must clear S3C24XX_EINTPEND external interrupt register 
++00072  * because after clearing in this register trigerred IRQ from 
++00073  * H/W core in kernel interrupt can be occured again before OTG
++00074  * handlers clear all IRQ sources of Core registers because of
++00075  * timing latencies and Low Level IRQ Type.
++00076  */
++00077 #ifdef CONFIG_MACH_IPMATE
++00078 #define  S3C2410X_CLEAR_EINTPEND()   \
++00079 do { \
++00080         __raw_writel(1UL << 11,S3C24XX_EINTPEND); \
++00081 } while (0)
++00082 #else
++00083 #define  S3C2410X_CLEAR_EINTPEND()   do { } while (0)
++00084 #endif
++00085 
++00086 #endif
++
    Generated on Thu Oct 27 03:56:37 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
    ++doxygen 1.3.9.1
    + + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__driver_8h.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/dwc__otg__driver_8h.html 2013-07-26 19:31:20.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__driver_8h.html 2013-07-26 19:34:40.000000000 +0000 +@@ -2,24 +2,13 @@ + + DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_driver.h File Reference + +- + +- +-
    +-
    +-
    +-
    ++ ++
    Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
    +

    dwc_otg_driver.h File Reference

    This file contains the interface to the Linux driver. More... +

    +-#include "dwc_otg_core_if.h"
    ++#include "dwc_otg_os_dep.h"
    ++#include "dwc_otg_core_if.h"
    + +

    + Go to the source code of this file. +@@ -29,12 +18,12 @@ + + + +- ++ + + +- ++ + + +
     This structure is a wrapper that encapsulates the driver components used to manage a single DWC_otg controller. More...

    Defines

    +-#define S3C2410X_CLEAR_EINTPEND()   do { } while (0)
    ++#define S3C2410X_CLEAR_EINTPEND()   do { } while (0)

    Typedefs

    +-typedef dwc_otg_device dwc_otg_device_t
    ++typedef dwc_otg_device dwc_otg_device_t
     This structure is a wrapper that encapsulates the driver components used to manage a single DWC_otg controller.
    +@@ -43,8 +32,8 @@ +

    + +

    +-Definition in file dwc_otg_driver.h.

    Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++Definition in file dwc_otg_driver.h.
    Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
    ++doxygen 1.3.9.1
    + + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__hcd_8c-source.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/dwc__otg__hcd_8c-source.html 2013-07-26 19:31:21.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__hcd_8c-source.html 2013-07-26 19:34:41.000000000 +0000 +@@ -2,2945 +2,3215 @@ + + DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_hcd.c Source File + +- + +- +-
    +-
    +-
    +-
    +-

    dwc_otg_hcd.c

    Go to the documentation of this file.
    00001 /* ==========================================================================
+-00002  * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd.c $
+-00003  * $Revision: #87 $
+-00004  * $Date: 2009/04/23 $
+-00005  * $Change: 1239143 $
+-00006  *
+-00007  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
+-00008  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
+-00009  * otherwise expressly agreed to in writing between Synopsys and you.
+-00010  *
+-00011  * The Software IS NOT an item of Licensed Software or Licensed Product under
+-00012  * any End User Software License Agreement or Agreement for Licensed Product
+-00013  * with Synopsys or any supplement thereto. You are permitted to use and
+-00014  * redistribute this Software in source and binary forms, with or without
+-00015  * modification, provided that redistributions of source code must retain this
+-00016  * notice. You may not view, use, disclose, copy or distribute this file or
+-00017  * any information contained herein except pursuant to this license grant from
+-00018  * Synopsys. If you do not agree with this notice, including the disclaimer
+-00019  * below, then you are not authorized to use the Software.
+-00020  *
+-00021  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
+-00022  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+-00023  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+-00024  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
+-00025  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+-00026  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+-00027  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+-00028  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+-00029  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+-00030  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+-00031  * DAMAGE.
+-00032  * ========================================================================== */
+-00033 #ifndef DWC_DEVICE_ONLY
+-00034 
+-00042 #include "dwc_otg_hcd.h"
+-00043 #include "dwc_otg_regs.h"
+-00044                 
+-00045 dwc_otg_hcd_t *dwc_otg_hcd_alloc_hcd(void)
+-00046 {
+-00047         return dwc_alloc(sizeof(dwc_otg_hcd_t));
+-00048 }
+-00049 
+-00054 void dwc_otg_hcd_connect_timeout(void *ptr)
+-00055 {
+-00056         DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, ptr);
+-00057         DWC_PRINTF("Connect Timeout\n");
+-00058         __DWC_ERROR("Device Not Connected/Responding\n");
+-00059 }
+-00060 
+-00061 #ifdef DEBUG
+-00062 static void dump_channel_info(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
+-00063 {
+-00064         if (qh->channel != NULL) {
+-00065                 dwc_hc_t *hc = qh->channel;
+-00066                 dwc_list_link_t *item;
+-00067                 dwc_otg_qh_t *qh_item;
+-00068                 int num_channels = hcd->core_if->core_params->host_channels;
+-00069                 int i;
+-00070 
+-00071                 dwc_otg_hc_regs_t *hc_regs;
+-00072                 hcchar_data_t hcchar;
+-00073                 hcsplt_data_t hcsplt;
+-00074                 hctsiz_data_t hctsiz;
+-00075                 uint32_t hcdma;
+-00076 
+-00077                 hc_regs = hcd->core_if->host_if->hc_regs[hc->hc_num];
+-00078                 hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
+-00079                 hcsplt.d32 = dwc_read_reg32(&hc_regs->hcsplt);
+-00080                 hctsiz.d32 = dwc_read_reg32(&hc_regs->hctsiz);
+-00081                 hcdma = dwc_read_reg32(&hc_regs->hcdma);
+-00082 
+-00083                 DWC_PRINTF("  Assigned to channel %p:\n", hc);
+-00084                 DWC_PRINTF("    hcchar 0x%08x, hcsplt 0x%08x\n", hcchar.d32,
+-00085                            hcsplt.d32);
+-00086                 DWC_PRINTF("    hctsiz 0x%08x, hcdma 0x%08x\n", hctsiz.d32,
+-00087                            hcdma);
+-00088                 DWC_PRINTF("    dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
+-00089                            hc->dev_addr, hc->ep_num, hc->ep_is_in);
+-00090                 DWC_PRINTF("    ep_type: %d\n", hc->ep_type);
+-00091                 DWC_PRINTF("    max_packet: %d\n", hc->max_packet);
+-00092                 DWC_PRINTF("    data_pid_start: %d\n", hc->data_pid_start);
+-00093                 DWC_PRINTF("    xfer_started: %d\n", hc->xfer_started);
+-00094                 DWC_PRINTF("    halt_status: %d\n", hc->halt_status);
+-00095                 DWC_PRINTF("    xfer_buff: %p\n", hc->xfer_buff);
+-00096                 DWC_PRINTF("    xfer_len: %d\n", hc->xfer_len);
+-00097                 DWC_PRINTF("    qh: %p\n", hc->qh);
+-00098                 DWC_PRINTF("  NP inactive sched:\n");
+-00099                 DWC_LIST_FOREACH(item, &hcd->non_periodic_sched_inactive) {
+-00100                         qh_item =
+-00101                             DWC_LIST_ENTRY(item, dwc_otg_qh_t, qh_list_entry);
+-00102                         DWC_PRINTF("    %p\n", qh_item);
+-00103                 }
+-00104                 DWC_PRINTF("  NP active sched:\n");
+-00105                 DWC_LIST_FOREACH(item, &hcd->non_periodic_sched_active) {
+-00106                         qh_item =
+-00107                             DWC_LIST_ENTRY(item, dwc_otg_qh_t, qh_list_entry);
+-00108                         DWC_PRINTF("    %p\n", qh_item);
+-00109                 }
+-00110                 DWC_PRINTF("  Channels: \n");
+-00111                 for (i = 0; i < num_channels; i++) {
+-00112                         dwc_hc_t *hc = hcd->hc_ptr_array[i];
+-00113                         DWC_PRINTF("    %2d: %p\n", i, hc);
+-00114                 }
+-00115         }
+-00116 }
+-00117 #endif                          /* DEBUG */
+-00118 
+-00123 static void hcd_start_func(void *_vp)
+-00124 {
+-00125         dwc_otg_hcd_t *hcd = (dwc_otg_hcd_t *) _vp;
+-00126 
+-00127         DWC_DEBUGPL(DBG_HCDV, "%s() %p\n", __func__, hcd);
+-00128         if (hcd) {
+-00129                 hcd->fops->start(hcd);
+-00130         }
+-00131 }
+-00132 
+-00133 static void del_xfer_timers(dwc_otg_hcd_t * hcd)
+-00134 {
+-00135 #ifdef DEBUG
+-00136         int i;
+-00137         int num_channels = hcd->core_if->core_params->host_channels;
+-00138         for (i = 0; i < num_channels; i++) {
+-00139                 DWC_TIMER_CANCEL(hcd->core_if->hc_xfer_timer[i]);
+-00140         }
+-00141 #endif
+-00142 }
+-00143 
+-00144 static void del_timers(dwc_otg_hcd_t * hcd)
+-00145 {
+-00146         del_xfer_timers(hcd);
+-00147         DWC_TIMER_CANCEL(hcd->conn_timer);
+-00148 }
+-00149 
+-00154 static void kill_urbs_in_qh_list(dwc_otg_hcd_t * hcd, dwc_list_link_t * qh_list)
+-00155 {
+-00156         dwc_list_link_t *qh_item;
+-00157         dwc_otg_qh_t *qh;
+-00158         dwc_otg_qtd_t *qtd, *qtd_tmp;
+-00159 
+-00160         DWC_LIST_FOREACH(qh_item, qh_list) {
+-00161                 qh = DWC_LIST_ENTRY(qh_item, dwc_otg_qh_t, qh_list_entry);
+-00162                 DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp,
+-00163                                          &qh->qtd_list, qtd_list_entry) {
+-00164                         qtd = DWC_CIRCLEQ_FIRST(&qh->qtd_list);
+-00165                         if (qtd->urb != NULL) {
+-00166                                 hcd->fops->complete(hcd, qtd->urb->priv,
+-00167                                                     qtd->urb,
+-00168                                                     -DWC_E_TIMEOUT);
+-00169                                 dwc_otg_hcd_qtd_remove_and_free(hcd, qtd, qh);
+-00170                         }
+-00171 
+-00172                 }
+-00173         }
+-00174 }
+-00175 
+-00182 static void kill_all_urbs(dwc_otg_hcd_t * hcd)
+-00183 {
+-00184         kill_urbs_in_qh_list(hcd, &hcd->non_periodic_sched_inactive);
+-00185         kill_urbs_in_qh_list(hcd, &hcd->non_periodic_sched_active);
+-00186         kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_inactive);
+-00187         kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_ready);
+-00188         kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_assigned);
+-00189         kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_queued);
+-00190 }
+-00191 
+-00198 static void dwc_otg_hcd_start_connect_timer(dwc_otg_hcd_t * hcd)
+-00199 {
+-00200         DWC_TIMER_SCHEDULE(hcd->conn_timer, 10000 /* 10 secs */ );
+-00201 }
+-00202 
+-00208 static int32_t dwc_otg_hcd_session_start_cb(void *p)
+-00209 {
+-00210         dwc_otg_hcd_t *dwc_otg_hcd;
+-00211         DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, p);
+-00212         dwc_otg_hcd = p;
+-00213         dwc_otg_hcd_start_connect_timer(dwc_otg_hcd);
+-00214         return 1;
+-00215 }
+-00216 
+-00223 static int32_t dwc_otg_hcd_start_cb(void *p)
+-00224 {
+-00225         dwc_otg_hcd_t *dwc_otg_hcd = p;
+-00226         dwc_otg_core_if_t *core_if;
+-00227         hprt0_data_t hprt0;
+-00228 
+-00229         core_if = dwc_otg_hcd->core_if;
+-00230 
+-00231         if (core_if->op_state == B_HOST) {
+-00232                 /*
+-00233                  * Reset the port.  During a HNP mode switch the reset
+-00234                  * needs to occur within 1ms and have a duration of at
+-00235                  * least 50ms.
+-00236                  */
+-00237                 hprt0.d32 = dwc_otg_read_hprt0(core_if);
+-00238                 hprt0.b.prtrst = 1;
+-00239                 dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
+-00240         }
+-00241         DWC_WORKQ_SCHEDULE_DELAYED(core_if->wq_otg,
+-00242                                    hcd_start_func, dwc_otg_hcd, 50,
+-00243                                    "start hcd");
+-00244 
+-00245         return 1;
+-00246 }
+-00247 
+-00253 static int32_t dwc_otg_hcd_disconnect_cb(void *p)
+-00254 {
+-00255         gintsts_data_t intr;
+-00256         dwc_otg_hcd_t *dwc_otg_hcd = p;
+-00257 
+-00258         /*
+-00259          * Set status flags for the hub driver.
+-00260          */
+-00261         dwc_otg_hcd->flags.b.port_connect_status_change = 1;
+-00262         dwc_otg_hcd->flags.b.port_connect_status = 0;
+-00263 
+-00264         /*
+-00265          * Shutdown any transfers in process by clearing the Tx FIFO Empty
+-00266          * interrupt mask and status bits and disabling subsequent host
+-00267          * channel interrupts.
+-00268          */
+-00269         intr.d32 = 0;
+-00270         intr.b.nptxfempty = 1;
+-00271         intr.b.ptxfempty = 1;
+-00272         intr.b.hcintr = 1;
+-00273         dwc_modify_reg32(&dwc_otg_hcd->core_if->core_global_regs->gintmsk,
+-00274                          intr.d32, 0);
+-00275         dwc_modify_reg32(&dwc_otg_hcd->core_if->core_global_regs->gintsts,
+-00276                          intr.d32, 0);
+-00277 
+-00278         del_timers(dwc_otg_hcd);
+-00279 
+-00280         /*
+-00281          * Turn off the vbus power only if the core has transitioned to device
+-00282          * mode. If still in host mode, need to keep power on to detect a
+-00283          * reconnection.
+-00284          */
+-00285         if (dwc_otg_is_device_mode(dwc_otg_hcd->core_if)) {
+-00286                 if (dwc_otg_hcd->core_if->op_state != A_SUSPEND) {
+-00287                         hprt0_data_t hprt0 = {.d32 = 0 };
+-00288                         DWC_PRINTF("Disconnect: PortPower off\n");
+-00289                         hprt0.b.prtpwr = 0;
+-00290                         dwc_write_reg32(dwc_otg_hcd->core_if->host_if->hprt0,
+-00291                                         hprt0.d32);
+-00292                 }
+-00293 
+-00294                 dwc_otg_disable_host_interrupts(dwc_otg_hcd->core_if);
+-00295         }
+-00296 
+-00297         /* Respond with an error status to all URBs in the schedule. */
+-00298         kill_all_urbs(dwc_otg_hcd);
+-00299 
+-00300         if (dwc_otg_is_host_mode(dwc_otg_hcd->core_if)) {
+-00301                 /* Clean up any host channels that were in use. */
+-00302                 int num_channels;
+-00303                 int i;
+-00304                 dwc_hc_t *channel;
+-00305                 dwc_otg_hc_regs_t *hc_regs;
+-00306                 hcchar_data_t hcchar;
+-00307 
+-00308                 num_channels = dwc_otg_hcd->core_if->core_params->host_channels;
+-00309 
+-00310                 if (!dwc_otg_hcd->core_if->dma_enable) {
+-00311                         /* Flush out any channel requests in slave mode. */
+-00312                         for (i = 0; i < num_channels; i++) {
+-00313                                 channel = dwc_otg_hcd->hc_ptr_array[i];
+-00314                                 if (DWC_CIRCLEQ_EMPTY_ENTRY
+-00315                                     (channel, hc_list_entry)) {
+-00316                                         hc_regs =
+-00317                                             dwc_otg_hcd->core_if->host_if->
+-00318                                             hc_regs[i];
+-00319                                         hcchar.d32 =
+-00320                                             dwc_read_reg32(&hc_regs->hcchar);
+-00321                                         if (hcchar.b.chen) {
+-00322                                                 hcchar.b.chen = 0;
+-00323                                                 hcchar.b.chdis = 1;
+-00324                                                 hcchar.b.epdir = 0;
+-00325                                                 dwc_write_reg32(&hc_regs->
+-00326                                                                 hcchar,
+-00327                                                                 hcchar.d32);
+-00328                                         }
+-00329                                 }
+-00330                         }
+-00331                 }
+-00332 
+-00333                 for (i = 0; i < num_channels; i++) {
+-00334                         channel = dwc_otg_hcd->hc_ptr_array[i];
+-00335                         if (DWC_CIRCLEQ_EMPTY_ENTRY(channel, hc_list_entry)) {
+-00336                                 hc_regs =
+-00337                                     dwc_otg_hcd->core_if->host_if->hc_regs[i];
+-00338                                 hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
+-00339                                 if (hcchar.b.chen) {
+-00340                                         /* Halt the channel. */
+-00341                                         hcchar.b.chdis = 1;
+-00342                                         dwc_write_reg32(&hc_regs->hcchar,
+-00343                                                         hcchar.d32);
+-00344                                 }
+-00345 
+-00346                                 dwc_otg_hc_cleanup(dwc_otg_hcd->core_if,
+-00347                                                    channel);
+-00348                                 DWC_CIRCLEQ_INSERT_TAIL(&dwc_otg_hcd->
+-00349                                                         free_hc_list, channel,
+-00350                                                         hc_list_entry);
+-00351                                 /* 
+-00352                                  * Added for Descriptor DMA to prevent channel double cleanup 
+-00353                                  * in release_channel_ddma(). Which called from ep_disable
+-00354                                  * when device disconnect.
+-00355                                  */                     
+-00356                                 channel->qh = NULL;                     
+-00357                         }
+-00358                 }
+-00359         }
+-00360 
+-00361         if (dwc_otg_hcd->fops->disconnect) {
+-00362                 dwc_otg_hcd->fops->disconnect(dwc_otg_hcd);
+-00363         }
+-00364 
+-00365         return 1;
+-00366 }
+-00367 
+-00373 static int32_t dwc_otg_hcd_stop_cb(void *p)
+-00374 {
+-00375         dwc_otg_hcd_t *dwc_otg_hcd = p;
+-00376 
+-00377         DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, p);
+-00378         dwc_otg_hcd_stop(dwc_otg_hcd);
+-00379         return 1;
+-00380 }
+-00381 
+-00382 #ifdef CONFIG_USB_DWC_OTG_LPM
+-00383 
+-00388 static int dwc_otg_hcd_sleep_cb(void *p)
+-00389 {
+-00390         dwc_otg_hcd_t *hcd = p;
+-00391 
+-00392         dwc_otg_hcd_free_hc_from_lpm(hcd);
+-00393 
+-00394         return 0;
+-00395 }
+-00396 #endif
+-00397 
+-00403 static int dwc_otg_hcd_rem_wakeup_cb(void *p)
+-00404 {
+-00405         dwc_otg_hcd_t *hcd = p;
+-00406 
+-00407         if (hcd->core_if->lx_state == DWC_OTG_L2) {
+-00408                 hcd->flags.b.port_suspend_change = 1;
+-00409         }
+-00410 #ifdef CONFIG_USB_DWC_OTG_LPM
+-00411         else {
+-00412                 hcd->flags.b.port_l1_change = 1;
+-00413         }
+-00414 #endif
+-00415         return 0;
+-00416 }
+-00417 
+-00422 void dwc_otg_hcd_stop(dwc_otg_hcd_t * hcd)
+-00423 {
+-00424         hprt0_data_t hprt0 = {.d32 = 0 };
+-00425 
+-00426         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD STOP\n");
+-00427 
+-00428         /*
+-00429          * The root hub should be disconnected before this function is called.
+-00430          * The disconnect will clear the QTD lists (via ..._hcd_urb_dequeue)
+-00431          * and the QH lists (via ..._hcd_endpoint_disable).
+-00432          */
+-00433 
+-00434         /* Turn off all host-specific interrupts. */
+-00435         dwc_otg_disable_host_interrupts(hcd->core_if);
+-00436 
+-00437         /* Turn off the vbus power */
+-00438         DWC_PRINTF("PortPower off\n");
+-00439         hprt0.b.prtpwr = 0;
+-00440         dwc_write_reg32(hcd->core_if->host_if->hprt0, hprt0.d32);
+-00441         dwc_mdelay(1);
+-00442 }
+-00443 
+-00444 int dwc_otg_hcd_urb_enqueue(dwc_otg_hcd_t * hcd,
+-00445                             dwc_otg_hcd_urb_t * dwc_otg_urb, void **ep_handle)
+-00446 {
+-00447         uint64_t flags;
+-00448         int retval = 0;
+-00449         dwc_otg_qtd_t *qtd;
+-00450 
+-00451         if (!hcd->flags.b.port_connect_status) {
+-00452                 /* No longer connected. */
+-00453                 return -DWC_E_NO_DEVICE;
+-00454         }
+-00455 
+-00456         qtd = dwc_otg_hcd_qtd_create(dwc_otg_urb);
+-00457         if (qtd == NULL) {
+-00458                 DWC_ERROR("DWC OTG HCD URB Enqueue failed creating QTD\n");
+-00459                 return -DWC_E_NO_MEMORY;
+-00460         }
+-00461 
+-00462         retval =
+-00463             dwc_otg_hcd_qtd_add(qtd, hcd, (dwc_otg_qh_t **) ep_handle);
+-00464         if (retval < 0) {
+-00465                 DWC_ERROR("DWC OTG HCD URB Enqueue failed adding QTD. "
+-00466                           "Error status %d\n", retval);
+-00467                 dwc_otg_hcd_qtd_free(qtd);
+-00468         } else {
+-00469                 qtd->qh = *ep_handle;
+-00470         }
+-00471         
+-00472         if (hcd->core_if->dma_desc_enable && retval == 0) {
+-00473                 dwc_otg_transaction_type_e tr_type;     
+-00474                 if ((qtd->qh->ep_type == UE_BULK) && !(qtd->urb->flags & URB_GIVEBACK_ASAP)) {
+-00475                         /* Do not schedule SG transcations until qtd has URB_GIVEBACK_ASAP set */
+-00476                         return 0;
+-00477                 }
+-00478                 DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
+-00479                 tr_type = dwc_otg_hcd_select_transactions(hcd);
+-00480                 if (tr_type != DWC_OTG_TRANSACTION_NONE) {
+-00481                         dwc_otg_hcd_queue_transactions(hcd, tr_type);
+-00482                 }
+-00483                 DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
+-00484         }
+-00485 
+-00486         return retval;
+-00487 }
+-00488 
+-00489 int dwc_otg_hcd_urb_dequeue(dwc_otg_hcd_t * hcd,
+-00490                             dwc_otg_hcd_urb_t * dwc_otg_urb)
+-00491 {
+-00492         uint64_t flags;
+-00493 
+-00494         dwc_otg_qh_t *qh;
+-00495         dwc_otg_qtd_t *urb_qtd;
+-00496 
+-00497         DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
+-00498         
+-00499         urb_qtd = dwc_otg_urb->qtd;
+-00500         qh = urb_qtd->qh;
+-00501 #ifdef DEBUG
+-00502         if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
+-00503                 if (urb_qtd->in_process) {
+-00504                         dump_channel_info(hcd, qh);
+-00505                 }
+-00506         }
+-00507 #endif
+-00508         if (urb_qtd->in_process && qh->channel) {
+-00509                 /* The QTD is in process (it has been assigned to a channel). */
+-00510                 if (hcd->flags.b.port_connect_status) {
+-00511                         /*
+-00512                          * If still connected (i.e. in host mode), halt the
+-00513                          * channel so it can be used for other transfers. If
+-00514                          * no longer connected, the host registers can't be
+-00515                          * written to halt the channel since the core is in
+-00516                          * device mode.
+-00517                          */
+-00518                         dwc_otg_hc_halt(hcd->core_if, qh->channel,
+-00519                                         DWC_OTG_HC_XFER_URB_DEQUEUE);
+-00520                 }
+-00521         }
+-00522 
+-00523         /*
+-00524          * Free the QTD and clean up the associated QH. Leave the QH in the
+-00525          * schedule if it has any remaining QTDs.
+-00526          */
+-00527          
+-00528         if (!hcd->core_if->dma_desc_enable) {
+-00529                 uint8_t b = urb_qtd->in_process;        
+-00530                 dwc_otg_hcd_qtd_remove_and_free(hcd, urb_qtd, qh);
+-00531                 if (b) {
+-00532                         dwc_otg_hcd_qh_deactivate(hcd, qh, 0);
+-00533                         qh->channel = NULL;
+-00534                 } else if (DWC_CIRCLEQ_EMPTY(&qh->qtd_list)) {
+-00535                         dwc_otg_hcd_qh_remove(hcd, qh);
+-00536                 }
+-00537         }
+-00538         else {
+-00539                 dwc_otg_hcd_qtd_remove_and_free(hcd, urb_qtd, qh);
+-00540         }
+-00541         
+-00542         DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
+-00543 
+-00544         return 0;
+-00545 }
+-00546 
+-00547 int dwc_otg_hcd_endpoint_disable(dwc_otg_hcd_t * hcd, void *ep_handle,
+-00548                                  int retry)
+-00549 {
+-00550         dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle;
+-00551         int retval = 0;
+-00552         uint64_t flags;
+-00553 
+-00554         if (retry < 0) {
+-00555                 retval = -DWC_E_INVALID;
+-00556                 goto done;
+-00557         }
+-00558 
+-00559         if (!qh) {
+-00560                 goto done;
+-00561         }
+-00562 
+-00563         DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
+-00564         
+-00565         while (!DWC_CIRCLEQ_EMPTY(&qh->qtd_list) && retry) {
+-00566                 DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
+-00567                 retry--;
+-00568                 dwc_msleep(5);
+-00569                 DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
+-00570         }
+-00571 
+-00572         dwc_otg_hcd_qh_remove(hcd, qh);
+-00573         
+-00574         DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
+-00575         /* 
+-00576          * Split dwc_otg_hcd_qh_remove_and_free() into qh_remove 
+-00577          * and qh_free to prevent stack dump on dwc_dma_free() with 
+-00578          * irq_disabled (spinlock_irqsave) in dwc_otg_hcd_desc_list_free() 
+-00579          * and dwc_otg_hcd_frame_list_alloc().
+-00580          */
+-00581         dwc_otg_hcd_qh_free(hcd, qh);
+-00582 
+-00583       done:
+-00584         return retval;
+-00585 }
+-00586 
+-00590 static dwc_otg_cil_callbacks_t hcd_cil_callbacks = {
+-00591         .start = dwc_otg_hcd_start_cb,
+-00592         .stop = dwc_otg_hcd_stop_cb,
+-00593         .disconnect = dwc_otg_hcd_disconnect_cb,
+-00594         .session_start = dwc_otg_hcd_session_start_cb,
+-00595         .resume_wakeup = dwc_otg_hcd_rem_wakeup_cb,
+-00596 #ifdef CONFIG_USB_DWC_OTG_LPM
+-00597         .sleep = dwc_otg_hcd_sleep_cb,
+-00598 #endif
+-00599         .p = 0,
+-00600 };
+-00601 
+-00605 static void reset_tasklet_func(void *data)
+-00606 {
+-00607         dwc_otg_hcd_t *dwc_otg_hcd = (dwc_otg_hcd_t *) data;
+-00608         dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;
+-00609         hprt0_data_t hprt0;
+-00610 
+-00611         DWC_DEBUGPL(DBG_HCDV, "USB RESET tasklet called\n");
+-00612 
+-00613         hprt0.d32 = dwc_otg_read_hprt0(core_if);
+-00614         hprt0.b.prtrst = 1;
+-00615         dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
+-00616         dwc_mdelay(60);
+-00617 
+-00618         hprt0.b.prtrst = 0;
+-00619         dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
+-00620         dwc_otg_hcd->flags.b.port_reset_change = 1;
+-00621 }
+-00622 
+-00623 static void qh_list_free(dwc_otg_hcd_t * hcd, dwc_list_link_t * qh_list)
+-00624 {
+-00625         dwc_list_link_t *item;
+-00626         dwc_otg_qh_t *qh;
+-00627 
+-00628         if (!qh_list->next) {
+-00629                 /* The list hasn't been initialized yet. */
+-00630                 return;
+-00631         }
+-00632 
+-00633         /* Ensure there are no QTDs or URBs left. */
+-00634         kill_urbs_in_qh_list(hcd, qh_list);
+-00635 
+-00636         DWC_LIST_FOREACH(item, qh_list) {
+-00637                 qh = DWC_LIST_ENTRY(item, dwc_otg_qh_t, qh_list_entry);
+-00638                 dwc_otg_hcd_qh_remove_and_free(hcd, qh);
+-00639         }
+-00640 }
+-00641 
+-00646 static void dwc_otg_hcd_free(dwc_otg_hcd_t * dwc_otg_hcd)
+-00647 {
+-00648         int i;
+-00649 
+-00650         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD FREE\n");
+-00651 
+-00652         del_timers(dwc_otg_hcd);
+-00653 
+-00654         /* Free memory for QH/QTD lists */
+-00655         qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->non_periodic_sched_inactive);
+-00656         qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->non_periodic_sched_active);
+-00657         qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_inactive);
+-00658         qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_ready);
+-00659         qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_assigned);
+-00660         qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_queued);
+-00661 
+-00662         /* Free memory for the host channels. */
+-00663         for (i = 0; i < MAX_EPS_CHANNELS; i++) {
+-00664                 dwc_hc_t *hc = dwc_otg_hcd->hc_ptr_array[i];
+-00665 
+-00666 #ifdef DEBUG
+-00667                 if (dwc_otg_hcd->core_if->hc_xfer_timer[i]) {
+-00668                         DWC_TIMER_FREE(dwc_otg_hcd->core_if->hc_xfer_timer[i]);
+-00669                 }
+-00670 #endif
+-00671                 if (hc != NULL) {
+-00672                         DWC_DEBUGPL(DBG_HCDV, "HCD Free channel #%i, hc=%p\n",
+-00673                                     i, hc);
+-00674                         dwc_free(hc);
+-00675                 }
+-00676         }
+-00677 
+-00678         if (dwc_otg_hcd->core_if->dma_enable) {
+-00679                 if (dwc_otg_hcd->status_buf_dma) {
+-00680                         dwc_dma_free(DWC_OTG_HCD_STATUS_BUF_SIZE,
+-00681                                      dwc_otg_hcd->status_buf,
+-00682                                      dwc_otg_hcd->status_buf_dma);
+-00683                 }
+-00684         } else if (dwc_otg_hcd->status_buf != NULL) {
+-00685                 dwc_free(dwc_otg_hcd->status_buf);
+-00686         }
+-00687         DWC_SPINLOCK_FREE(dwc_otg_hcd->lock);
+-00688         DWC_TIMER_FREE(dwc_otg_hcd->conn_timer);
+-00689         DWC_TASK_FREE(dwc_otg_hcd->reset_tasklet);
+-00690         dwc_free(dwc_otg_hcd);
+-00691 }
+-00692 
+-00693 int dwc_otg_hcd_init(dwc_otg_hcd_t * hcd, dwc_otg_core_if_t * core_if)
+-00694 {
+-00695         int retval = 0;
+-00696         int num_channels;
+-00697         int i;
+-00698         dwc_hc_t *channel;
+-00699 
+-00700         hcd->lock = DWC_SPINLOCK_ALLOC();
+-00701 
+-00702         hcd->core_if = core_if;
+-00703         /* Register the HCD CIL Callbacks */
+-00704         dwc_otg_cil_register_hcd_callbacks(hcd->core_if,
+-00705                                            &hcd_cil_callbacks, hcd);
+-00706 
+-00707         /* Initialize the non-periodic schedule. */
+-00708         DWC_LIST_INIT(&hcd->non_periodic_sched_inactive);
+-00709         DWC_LIST_INIT(&hcd->non_periodic_sched_active);
+-00710 
+-00711         /* Initialize the periodic schedule. */
+-00712         DWC_LIST_INIT(&hcd->periodic_sched_inactive);
+-00713         DWC_LIST_INIT(&hcd->periodic_sched_ready);
+-00714         DWC_LIST_INIT(&hcd->periodic_sched_assigned);
+-00715         DWC_LIST_INIT(&hcd->periodic_sched_queued);
+-00716 
+-00717         /*
+-00718          * Create a host channel descriptor for each host channel implemented
+-00719          * in the controller. Initialize the channel descriptor array.
+-00720          */
+-00721         DWC_CIRCLEQ_INIT(&hcd->free_hc_list);
+-00722         num_channels = hcd->core_if->core_params->host_channels;
+-00723         DWC_MEMSET(hcd->hc_ptr_array, 0, sizeof(hcd->hc_ptr_array));
+-00724         for (i = 0; i < num_channels; i++) {
+-00725                 channel = dwc_alloc(sizeof(dwc_hc_t));
+-00726                 if (channel == NULL) {
+-00727                         retval = -DWC_E_NO_MEMORY;
+-00728                         DWC_ERROR("%s: host channel allocation failed\n",
+-00729                                   __func__);
+-00730                         dwc_otg_hcd_free(hcd);
+-00731                         goto out;
+-00732                 }
+-00733                 channel->hc_num = i;
+-00734                 hcd->hc_ptr_array[i] = channel;
+-00735 #ifdef DEBUG
+-00736                 hcd->core_if->hc_xfer_timer[i] =
+-00737                     DWC_TIMER_ALLOC("hc timer", hc_xfer_timeout,
+-00738                                     &hcd->core_if->hc_xfer_info[i]);
+-00739 #endif
+-00740                 DWC_DEBUGPL(DBG_HCDV, "HCD Added channel #%d, hc=%p\n", i,
+-00741                             channel);
+-00742         }
+-00743 
+-00744         /* Initialize the Connection timeout timer. */
+-00745         hcd->conn_timer = DWC_TIMER_ALLOC("Connection timer",
+-00746                                           dwc_otg_hcd_connect_timeout, 0);
+-00747 
+-00748         /* Initialize reset tasklet. */
+-00749         hcd->reset_tasklet = DWC_TASK_ALLOC(reset_tasklet_func, hcd);
+-00750 
+-00751         /*
+-00752          * Allocate space for storing data on status transactions. Normally no
+-00753          * data is sent, but this space acts as a bit bucket. This must be
+-00754          * done after usb_add_hcd since that function allocates the DMA buffer
+-00755          * pool.
+-00756          */
+-00757         if (hcd->core_if->dma_enable) {
+-00758                 hcd->status_buf =
+-00759                     dwc_dma_alloc(DWC_OTG_HCD_STATUS_BUF_SIZE,
+-00760                                   &hcd->status_buf_dma);
+-00761         } else {
+-00762                 hcd->status_buf = dwc_alloc(DWC_OTG_HCD_STATUS_BUF_SIZE);
+-00763         }
+-00764         if (!hcd->status_buf) {
+-00765                 retval = -DWC_E_NO_MEMORY;
+-00766                 DWC_ERROR("%s: status_buf allocation failed\n", __func__);
+-00767                 dwc_otg_hcd_free(hcd);
+-00768                 goto out;
+-00769         }
+-00770 
+-00771         hcd->otg_port = 1;
+-00772         hcd->frame_list = NULL;
+-00773         hcd->frame_list_dma = 0;
+-00774 out:
+-00775         return retval;
+-00776 }
+-00777 
+-00778 void dwc_otg_hcd_remove(dwc_otg_hcd_t * hcd)
+-00779 {
+-00780         /* Turn off all host-specific interrupts. */
+-00781         dwc_otg_disable_host_interrupts(hcd->core_if);
+-00782 
+-00783         dwc_otg_hcd_free(hcd);
+-00784 }
+-00785 
+-00789 static void dwc_otg_hcd_reinit(dwc_otg_hcd_t * hcd)
+-00790 {
+-00791         int num_channels;
+-00792         int i;
+-00793         dwc_hc_t *channel;
+-00794         dwc_hc_t *channel_tmp;
+-00795 
+-00796         hcd->flags.d32 = 0;
+-00797 
+-00798         hcd->non_periodic_qh_ptr = &hcd->non_periodic_sched_active;
+-00799         hcd->non_periodic_channels = 0;
+-00800         hcd->periodic_channels = 0;
+-00801 
+-00802         /*
+-00803          * Put all channels in the free channel list and clean up channel
+-00804          * states.
+-00805          */
+-00806         DWC_CIRCLEQ_FOREACH_SAFE(channel, channel_tmp,
+-00807                                  &hcd->free_hc_list, hc_list_entry) {
+-00808                 DWC_CIRCLEQ_REMOVE(&hcd->free_hc_list, channel, hc_list_entry);
+-00809         }
+-00810 
+-00811         num_channels = hcd->core_if->core_params->host_channels;
+-00812         for (i = 0; i < num_channels; i++) {
+-00813                 channel = hcd->hc_ptr_array[i];
+-00814                 DWC_CIRCLEQ_INSERT_TAIL(&hcd->free_hc_list, channel,
+-00815                                         hc_list_entry);
+-00816                 dwc_otg_hc_cleanup(hcd->core_if, channel);
+-00817         }
+-00818 
+-00819         /* Initialize the DWC core for host mode operation. */
+-00820         dwc_otg_core_host_init(hcd->core_if);
+-00821 }
+-00822 
+-00832 static void assign_and_init_hc(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
+-00833 {
+-00834         dwc_hc_t *hc;
+-00835         dwc_otg_qtd_t *qtd;
+-00836         dwc_otg_hcd_urb_t *urb;
+-00837         void* ptr = NULL;
+-00838 
+-00839         DWC_DEBUGPL(DBG_HCDV, "%s(%p,%p)\n", __func__, hcd, qh);
+-00840 
+-00841         hc = DWC_CIRCLEQ_FIRST(&hcd->free_hc_list);
+-00842 
+-00843         /* Remove the host channel from the free list. */
+-00844         DWC_CIRCLEQ_REMOVE_INIT(&hcd->free_hc_list, hc, hc_list_entry);
+-00845 
+-00846         qtd = DWC_CIRCLEQ_FIRST(&qh->qtd_list);
+-00847         
+-00848         urb = qtd->urb;
+-00849         qh->channel = hc;
+-00850         
+-00851         qtd->in_process = 1;
+-00852 
+-00853         /*
+-00854          * Use usb_pipedevice to determine device address. This address is
+-00855          * 0 before the SET_ADDRESS command and the correct address afterward.
+-00856          */
+-00857         hc->dev_addr = dwc_otg_hcd_get_dev_addr(&urb->pipe_info);
+-00858         hc->ep_num = dwc_otg_hcd_get_ep_num(&urb->pipe_info);
+-00859         hc->speed = qh->dev_speed;
+-00860         hc->max_packet = dwc_max_packet(qh->maxp);
+-00861 
+-00862         hc->xfer_started = 0;
+-00863         hc->halt_status = DWC_OTG_HC_XFER_NO_HALT_STATUS;
+-00864         hc->error_state = (qtd->error_count > 0);
+-00865         hc->halt_on_queue = 0;
+-00866         hc->halt_pending = 0;
+-00867         hc->requests = 0;
+-00868 
+-00869         /*
+-00870          * The following values may be modified in the transfer type section
+-00871          * below. The xfer_len value may be reduced when the transfer is
+-00872          * started to accommodate the max widths of the XferSize and PktCnt
+-00873          * fields in the HCTSIZn register.
+-00874          */
+-00875         hc->do_ping = qh->ping_state;
+-00876         hc->ep_is_in = (dwc_otg_hcd_is_pipe_in(&urb->pipe_info) != 0);
+-00877         hc->data_pid_start = qh->data_toggle;
+-00878         hc->multi_count = 1;
+-00879 
+-00880         if (hcd->core_if->dma_enable) {
+-00881                 hc->xfer_buff = (uint8_t *) urb->dma + urb->actual_length;
+-00882         
+-00883                 /* For non-dword aligned case */
+-00884                 if (((uint32_t)hc->xfer_buff & 0x3) && !hcd->core_if->dma_desc_enable) {
+-00885                         ptr = (uint8_t *) urb->buf + urb->actual_length;
+-00886                 }
+-00887         } else {
+-00888                 hc->xfer_buff = (uint8_t *) urb->buf + urb->actual_length;
+-00889         }
+-00890         hc->xfer_len = urb->length - urb->actual_length;
+-00891         hc->xfer_count = 0;
+-00892 
+-00893         /*
+-00894          * Set the split attributes
+-00895          */
+-00896         hc->do_split = 0;
+-00897         if (qh->do_split) {
+-00898                 uint32_t hub_addr, port_addr;
+-00899                 hc->do_split = 1;
+-00900                 hc->xact_pos = qtd->isoc_split_pos;
+-00901                 hc->complete_split = qtd->complete_split;
+-00902                 hcd->fops->hub_info(hcd, urb->priv, &hub_addr, &port_addr);
+-00903                 hc->hub_addr = (uint8_t) hub_addr;
+-00904                 hc->port_addr = (uint8_t) port_addr;
+-00905         }
+-00906 
+-00907         switch (dwc_otg_hcd_get_pipe_type(&urb->pipe_info)) {
+-00908         case UE_CONTROL:
+-00909                 hc->ep_type = DWC_OTG_EP_TYPE_CONTROL;
+-00910                 switch (qtd->control_phase) {
+-00911                 case DWC_OTG_CONTROL_SETUP:
+-00912                         DWC_DEBUGPL(DBG_HCDV, "  Control setup transaction\n");
+-00913                         hc->do_ping = 0;
+-00914                         hc->ep_is_in = 0;
+-00915                         hc->data_pid_start = DWC_OTG_HC_PID_SETUP;
+-00916                         if (hcd->core_if->dma_enable) {
+-00917                                 hc->xfer_buff = (uint8_t *) urb->setup_dma;
+-00918                         } else {
+-00919                                 hc->xfer_buff = (uint8_t *) urb->setup_packet;
+-00920                         }
+-00921                         hc->xfer_len = 8;
+-00922                         ptr = NULL;
+-00923                         break;
+-00924                 case DWC_OTG_CONTROL_DATA:
+-00925                         DWC_DEBUGPL(DBG_HCDV, "  Control data transaction\n");
+-00926                         hc->data_pid_start = qtd->data_toggle;
+-00927                         break;
+-00928                 case DWC_OTG_CONTROL_STATUS:
+-00929                         /*
+-00930                          * Direction is opposite of data direction or IN if no
+-00931                          * data.
+-00932                          */
+-00933                         DWC_DEBUGPL(DBG_HCDV, "  Control status transaction\n");
+-00934                         if (urb->length == 0) {
+-00935                                 hc->ep_is_in = 1;
+-00936                         } else {
+-00937                                 hc->ep_is_in =
+-00938                                     dwc_otg_hcd_is_pipe_out(&urb->pipe_info);
+-00939                         }
+-00940                         if (hc->ep_is_in) {
+-00941                                 hc->do_ping = 0;
+-00942                         }
+-00943                         
+-00944                         hc->data_pid_start = DWC_OTG_HC_PID_DATA1;
+-00945 
+-00946                         hc->xfer_len = 0;
+-00947                         if (hcd->core_if->dma_enable) {
+-00948                                 hc->xfer_buff = (uint8_t *) hcd->status_buf_dma;
+-00949                         } else {
+-00950                                 hc->xfer_buff = (uint8_t *) hcd->status_buf;
+-00951                         }
+-00952                         ptr = NULL;
+-00953                         break;
+-00954                 }
+-00955                 break;
+-00956         case UE_BULK:
+-00957                 hc->ep_type = DWC_OTG_EP_TYPE_BULK;
+-00958                 break;
+-00959         case UE_INTERRUPT:
+-00960                 hc->ep_type = DWC_OTG_EP_TYPE_INTR;
+-00961                 break;
+-00962         case UE_ISOCHRONOUS:
+-00963                 {
+-00964                         struct dwc_otg_hcd_iso_packet_desc *frame_desc;
+-00965                         
+-00966                         hc->ep_type = DWC_OTG_EP_TYPE_ISOC;
+-00967                         
+-00968                         if (hcd->core_if->dma_desc_enable)
+-00969                                 break;
+-00970                                 
+-00971                         frame_desc = &urb->iso_descs[qtd->isoc_frame_index];
+-00972                         
+-00973                         frame_desc->status = 0;
+-00974                         
+-00975                         if (hcd->core_if->dma_enable) {
+-00976                                 hc->xfer_buff = (uint8_t *) urb->dma;
+-00977                         } else {
+-00978                                 hc->xfer_buff = (uint8_t *) urb->buf;
+-00979                         }
+-00980                         hc->xfer_buff +=
+-00981                             frame_desc->offset + qtd->isoc_split_offset;
+-00982                         hc->xfer_len =
+-00983                             frame_desc->length - qtd->isoc_split_offset;
+-00984 
+-00985                         /* For non-dword aligned buffers */
+-00986                         if (((uint32_t)hc->xfer_buff & 0x3) && hcd->core_if->dma_enable) {
+-00987                                 ptr = (uint8_t *) urb->buf + frame_desc->offset + qtd->isoc_split_offset;
+-00988                         }       
+-00989                         else
+-00990                             ptr = NULL;
+-00991                         
+-00992                         if (hc->xact_pos == DWC_HCSPLIT_XACTPOS_ALL) {
+-00993                                 if (hc->xfer_len <= 188) {
+-00994                                         hc->xact_pos = DWC_HCSPLIT_XACTPOS_ALL;
+-00995                                 } else {
+-00996                                         hc->xact_pos =
+-00997                                             DWC_HCSPLIT_XACTPOS_BEGIN;
+-00998                                 }
+-00999                         }
+-01000                 }
+-01001                 break;
+-01002         }
+-01003         /* non DWORD-aligned buffer case */     
+-01004         if (ptr) {
+-01005                 uint32_t buf_size;
+-01006                 if (hc->ep_type != DWC_OTG_EP_TYPE_ISOC) {
+-01007                         buf_size = hcd->core_if->core_params->max_transfer_size;
+-01008                 } else {                                
+-01009                         buf_size = 4096;
+-01010                 }
+-01011                 if (!qh->dw_align_buf) {
+-01012                         qh->dw_align_buf = dwc_dma_alloc(buf_size,
+-01013                                                          &qh->dw_align_buf_dma);
+-01014                         if (!qh->dw_align_buf) {
+-01015                                 DWC_ERROR("%s: Failed to allocate memory to handle "
+-01016                                           "non-dword aligned buffer case\n", __func__);
+-01017                                 return;
+-01018                         }
+-01019                 }
+-01020                 if (!hc->ep_is_in) {
+-01021                         dwc_memcpy(qh->dw_align_buf, ptr, hc->xfer_len);
+-01022                 }
+-01023                 hc->align_buff = qh->dw_align_buf_dma;
+-01024         }
+-01025         else {
+-01026                 hc->align_buff = 0;
+-01027         }
+-01028 
+-01029         if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
+-01030             hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
+-01031                 /*
+-01032                  * This value may be modified when the transfer is started to
+-01033                  * reflect the actual transfer length.
+-01034                  */
+-01035                 hc->multi_count = dwc_hb_mult(qh->maxp);
+-01036         }
+-01037         
+-01038         if (hcd->core_if->dma_desc_enable)
+-01039                 hc->desc_list_addr = qh->desc_list_dma;
+-01040         
+-01041         dwc_otg_hc_init(hcd->core_if, hc);
+-01042         hc->qh = qh;
+-01043 }
+-01044 
+-01045 
+-01055 dwc_otg_transaction_type_e dwc_otg_hcd_select_transactions(dwc_otg_hcd_t * hcd)
+-01056 {
+-01057         dwc_list_link_t *qh_ptr;
+-01058         dwc_otg_qh_t *qh;
+-01059         int num_channels;
+-01060         dwc_otg_transaction_type_e ret_val = DWC_OTG_TRANSACTION_NONE;
+-01061 
+-01062 #ifdef DEBUG_SOF
+-01063         DWC_DEBUGPL(DBG_HCD, "  Select Transactions\n");
+-01064 #endif
+-01065 
+-01066         /* Process entries in the periodic ready list. */
+-01067         qh_ptr = DWC_LIST_FIRST(&hcd->periodic_sched_ready);
+-01068 
+-01069         while (qh_ptr != &hcd->periodic_sched_ready &&
+-01070                !DWC_CIRCLEQ_EMPTY(&hcd->free_hc_list)) {
+-01071 
+-01072                 qh = DWC_LIST_ENTRY(qh_ptr, dwc_otg_qh_t, qh_list_entry);
+-01073                 assign_and_init_hc(hcd, qh);
+-01074 
+-01075                 /*
+-01076                  * Move the QH from the periodic ready schedule to the
+-01077                  * periodic assigned schedule.
+-01078                  */
+-01079                 qh_ptr = DWC_LIST_NEXT(qh_ptr);
+-01080                 DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_assigned,
+-01081                                    &qh->qh_list_entry);
+-01082 
+-01083                 ret_val = DWC_OTG_TRANSACTION_PERIODIC;
+-01084         }
+-01085 
+-01086         /*
+-01087          * Process entries in the inactive portion of the non-periodic
+-01088          * schedule. Some free host channels may not be used if they are
+-01089          * reserved for periodic transfers.
+-01090          */
+-01091         qh_ptr = hcd->non_periodic_sched_inactive.next;
+-01092         num_channels = hcd->core_if->core_params->host_channels;
+-01093         while (qh_ptr != &hcd->non_periodic_sched_inactive &&
+-01094                (hcd->non_periodic_channels <
+-01095                 num_channels - hcd->periodic_channels) &&
+-01096                !DWC_CIRCLEQ_EMPTY(&hcd->free_hc_list)) {
+-01097 
+-01098                 qh = DWC_LIST_ENTRY(qh_ptr, dwc_otg_qh_t, qh_list_entry);
+-01099 
+-01100                 assign_and_init_hc(hcd, qh);
+-01101 
+-01102                 /*
+-01103                  * Move the QH from the non-periodic inactive schedule to the
+-01104                  * non-periodic active schedule.
+-01105                  */
+-01106                 qh_ptr = DWC_LIST_NEXT(qh_ptr);
+-01107                 DWC_LIST_MOVE_HEAD(&hcd->non_periodic_sched_active,
+-01108                                    &qh->qh_list_entry);
+-01109 
+-01110                 if (ret_val == DWC_OTG_TRANSACTION_NONE) {
+-01111                         ret_val = DWC_OTG_TRANSACTION_NON_PERIODIC;
+-01112                 } else {
+-01113                         ret_val = DWC_OTG_TRANSACTION_ALL;
+-01114                 }
+-01115 
+-01116                 hcd->non_periodic_channels++;
+-01117         }
+-01118 
+-01119         return ret_val;
+-01120 }
+-01139 static int queue_transaction(dwc_otg_hcd_t * hcd,
+-01140                              dwc_hc_t * hc, uint16_t fifo_dwords_avail)
+-01141 {
+-01142         int retval;
+-01143 
+-01144         if (hcd->core_if->dma_enable) {
+-01145                 if (hcd->core_if->dma_desc_enable) {
+-01146                         if (!hc->xfer_started || (hc->ep_type == DWC_OTG_EP_TYPE_ISOC)) {       
+-01147                                 dwc_otg_hcd_start_xfer_ddma(hcd, hc->qh);
+-01148                                 hc->qh->ping_state = 0;
+-01149                         }
+-01150                 }
+-01151                 else if (!hc->xfer_started) {
+-01152                         dwc_otg_hc_start_transfer(hcd->core_if, hc);
+-01153                         hc->qh->ping_state = 0;
+-01154                 }
+-01155                 retval = 0;
+-01156         } else if (hc->halt_pending) {
+-01157                 /* Don't queue a request if the channel has been halted. */
+-01158                 retval = 0;
+-01159         } else if (hc->halt_on_queue) {
+-01160                 dwc_otg_hc_halt(hcd->core_if, hc, hc->halt_status);
+-01161                 retval = 0;
+-01162         } else if (hc->do_ping) {
+-01163                 if (!hc->xfer_started) {
+-01164                         dwc_otg_hc_start_transfer(hcd->core_if, hc);
+-01165                 }
+-01166                 retval = 0;
+-01167         } else if (!hc->ep_is_in || hc->data_pid_start == DWC_OTG_HC_PID_SETUP) {
+-01168                 if ((fifo_dwords_avail * 4) >= hc->max_packet) {
+-01169                         if (!hc->xfer_started) {
+-01170                                 dwc_otg_hc_start_transfer(hcd->core_if, hc);
+-01171                                 retval = 1;
+-01172                         } else {
+-01173                                 retval =
+-01174                                     dwc_otg_hc_continue_transfer(hcd->core_if,
+-01175                                                                  hc);
+-01176                         }
+-01177                 } else {
+-01178                         retval = -1;
+-01179                 }
+-01180         } else {
+-01181                 if (!hc->xfer_started) {
+-01182                         dwc_otg_hc_start_transfer(hcd->core_if, hc);
+-01183                         retval = 1;
+-01184                 } else {
+-01185                         retval = dwc_otg_hc_continue_transfer(hcd->core_if, hc);
+-01186                 }
+-01187         }
+-01188 
+-01189         return retval;
+-01190 }
+-01191 
+-01199 static void process_periodic_channels(dwc_otg_hcd_t * hcd)
+-01200 {
+-01201         hptxsts_data_t tx_status;
+-01202         dwc_list_link_t *qh_ptr;
+-01203         dwc_otg_qh_t *qh;
+-01204         int status;
+-01205         int no_queue_space = 0;
+-01206         int no_fifo_space = 0;
+-01207 
+-01208         dwc_otg_host_global_regs_t *host_regs;
+-01209         host_regs = hcd->core_if->host_if->host_global_regs;
+-01210 
+-01211         DWC_DEBUGPL(DBG_HCDV, "Queue periodic transactions\n");
+-01212 #ifdef DEBUG
+-01213         tx_status.d32 = dwc_read_reg32(&host_regs->hptxsts);
+-01214         DWC_DEBUGPL(DBG_HCDV,
+-01215                     "  P Tx Req Queue Space Avail (before queue): %d\n",
+-01216                     tx_status.b.ptxqspcavail);
+-01217         DWC_DEBUGPL(DBG_HCDV, "  P Tx FIFO Space Avail (before queue): %d\n",
+-01218                     tx_status.b.ptxfspcavail);
+-01219 #endif
+-01220 
+-01221         qh_ptr = hcd->periodic_sched_assigned.next;
+-01222         while (qh_ptr != &hcd->periodic_sched_assigned) {
+-01223                 tx_status.d32 = dwc_read_reg32(&host_regs->hptxsts);
+-01224                 if (tx_status.b.ptxqspcavail == 0) {
+-01225                         no_queue_space = 1;
+-01226                         break;
+-01227                 }
+-01228 
+-01229                 qh = DWC_LIST_ENTRY(qh_ptr, dwc_otg_qh_t, qh_list_entry);
+-01230 
+-01231                 /*
+-01232                  * Set a flag if we're queuing high-bandwidth in slave mode.
+-01233                  * The flag prevents any halts to get into the request queue in
+-01234                  * the middle of multiple high-bandwidth packets getting queued.
+-01235                  */
+-01236                 if (!hcd->core_if->dma_enable && qh->channel->multi_count > 1) {
+-01237                         hcd->core_if->queuing_high_bandwidth = 1;
+-01238                 }
+-01239                 status =
+-01240                     queue_transaction(hcd, qh->channel,
+-01241                                       tx_status.b.ptxfspcavail);
+-01242                 if (status < 0) {
+-01243                         no_fifo_space = 1;
+-01244                         break;
+-01245                 }
+-01246 
+-01247                 /*
+-01248                  * In Slave mode, stay on the current transfer until there is
+-01249                  * nothing more to do or the high-bandwidth request count is
+-01250                  * reached. In DMA mode, only need to queue one request. The
+-01251                  * controller automatically handles multiple packets for
+-01252                  * high-bandwidth transfers.
+-01253                  */
+-01254                 if (hcd->core_if->dma_enable || status == 0 ||
+-01255                     qh->channel->requests == qh->channel->multi_count) {
+-01256                         qh_ptr = qh_ptr->next;
+-01257                         /*
+-01258                          * Move the QH from the periodic assigned schedule to
+-01259                          * the periodic queued schedule.
+-01260                          */
+-01261                         DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_queued,
+-01262                                            &qh->qh_list_entry);
+-01263 
+-01264                         /* done queuing high bandwidth */
+-01265                         hcd->core_if->queuing_high_bandwidth = 0;
+-01266                 }
+-01267         }
+-01268 
+-01269         if (!hcd->core_if->dma_enable) {
+-01270                 dwc_otg_core_global_regs_t *global_regs;
+-01271                 gintmsk_data_t intr_mask = {.d32 = 0 };
+-01272 
+-01273                 global_regs = hcd->core_if->core_global_regs;
+-01274                 intr_mask.b.ptxfempty = 1;
+-01275 #ifdef DEBUG
+-01276                 tx_status.d32 = dwc_read_reg32(&host_regs->hptxsts);
+-01277                 DWC_DEBUGPL(DBG_HCDV,
+-01278                             "  P Tx Req Queue Space Avail (after queue): %d\n",
+-01279                             tx_status.b.ptxqspcavail);
+-01280                 DWC_DEBUGPL(DBG_HCDV,
+-01281                             "  P Tx FIFO Space Avail (after queue): %d\n",
+-01282                             tx_status.b.ptxfspcavail);
+-01283 #endif
+-01284                 if (!DWC_LIST_EMPTY(&hcd->periodic_sched_assigned) ||
+-01285                     no_queue_space || no_fifo_space) {
+-01286                         /*
+-01287                          * May need to queue more transactions as the request
+-01288                          * queue or Tx FIFO empties. Enable the periodic Tx
+-01289                          * FIFO empty interrupt. (Always use the half-empty
+-01290                          * level to ensure that new requests are loaded as
+-01291                          * soon as possible.)
+-01292                          */
+-01293                         dwc_modify_reg32(&global_regs->gintmsk, 0,
+-01294                                          intr_mask.d32);
+-01295                 } else {
+-01296                         /*
+-01297                          * Disable the Tx FIFO empty interrupt since there are
+-01298                          * no more transactions that need to be queued right
+-01299                          * now. This function is called from interrupt
+-01300                          * handlers to queue more transactions as transfer
+-01301                          * states change.
+-01302                          */
+-01303                         dwc_modify_reg32(&global_regs->gintmsk, intr_mask.d32,
+-01304                                          0);
+-01305                 }
+-01306         }
+-01307 }
+-01308 
+-01316 static void process_non_periodic_channels(dwc_otg_hcd_t * hcd)
+-01317 {
+-01318         gnptxsts_data_t tx_status;
+-01319         dwc_list_link_t *orig_qh_ptr;
+-01320         dwc_otg_qh_t *qh;
+-01321         int status;
+-01322         int no_queue_space = 0;
+-01323         int no_fifo_space = 0;
+-01324         int more_to_do = 0;
+-01325 
+-01326         dwc_otg_core_global_regs_t *global_regs =
+-01327             hcd->core_if->core_global_regs;
+-01328 
+-01329         DWC_DEBUGPL(DBG_HCDV, "Queue non-periodic transactions\n");
+-01330 #ifdef DEBUG
+-01331         tx_status.d32 = dwc_read_reg32(&global_regs->gnptxsts);
+-01332         DWC_DEBUGPL(DBG_HCDV,
+-01333                     "  NP Tx Req Queue Space Avail (before queue): %d\n",
+-01334                     tx_status.b.nptxqspcavail);
+-01335         DWC_DEBUGPL(DBG_HCDV, "  NP Tx FIFO Space Avail (before queue): %d\n",
+-01336                     tx_status.b.nptxfspcavail);
+-01337 #endif
+-01338         /*
+-01339          * Keep track of the starting point. Skip over the start-of-list
+-01340          * entry.
+-01341          */
+-01342         if (hcd->non_periodic_qh_ptr == &hcd->non_periodic_sched_active) {
+-01343                 hcd->non_periodic_qh_ptr = hcd->non_periodic_qh_ptr->next;
+-01344         }
+-01345         orig_qh_ptr = hcd->non_periodic_qh_ptr;
+-01346 
+-01347         /*
+-01348          * Process once through the active list or until no more space is
+-01349          * available in the request queue or the Tx FIFO.
+-01350          */
+-01351         do {
+-01352                 tx_status.d32 = dwc_read_reg32(&global_regs->gnptxsts);
+-01353                 if (!hcd->core_if->dma_enable && tx_status.b.nptxqspcavail == 0) {
+-01354                         no_queue_space = 1;
+-01355                         break;
+-01356                 }
+-01357 
+-01358                 qh = DWC_LIST_ENTRY(hcd->non_periodic_qh_ptr, dwc_otg_qh_t,
+-01359                                     qh_list_entry);
+-01360                 status =
+-01361                     queue_transaction(hcd, qh->channel,
+-01362                                       tx_status.b.nptxfspcavail);
+-01363 
+-01364                 if (status > 0) {
+-01365                         more_to_do = 1;
+-01366                 } else if (status < 0) {
+-01367                         no_fifo_space = 1;
+-01368                         break;
+-01369                 }
+-01370 
+-01371                 /* Advance to next QH, skipping start-of-list entry. */
+-01372                 hcd->non_periodic_qh_ptr = hcd->non_periodic_qh_ptr->next;
+-01373                 if (hcd->non_periodic_qh_ptr == &hcd->non_periodic_sched_active) {
+-01374                         hcd->non_periodic_qh_ptr =
+-01375                             hcd->non_periodic_qh_ptr->next;
+-01376                 }
+-01377 
+-01378         } while (hcd->non_periodic_qh_ptr != orig_qh_ptr);
+-01379 
+-01380         if (!hcd->core_if->dma_enable) {
+-01381                 gintmsk_data_t intr_mask = {.d32 = 0 };
+-01382                 intr_mask.b.nptxfempty = 1;
+-01383 
+-01384 #ifdef DEBUG
+-01385                 tx_status.d32 = dwc_read_reg32(&global_regs->gnptxsts);
+-01386                 DWC_DEBUGPL(DBG_HCDV,
+-01387                             "  NP Tx Req Queue Space Avail (after queue): %d\n",
+-01388                             tx_status.b.nptxqspcavail);
+-01389                 DWC_DEBUGPL(DBG_HCDV,
+-01390                             "  NP Tx FIFO Space Avail (after queue): %d\n",
+-01391                             tx_status.b.nptxfspcavail);
+-01392 #endif
+-01393                 if (more_to_do || no_queue_space || no_fifo_space) {
+-01394                         /*
+-01395                          * May need to queue more transactions as the request
+-01396                          * queue or Tx FIFO empties. Enable the non-periodic
+-01397                          * Tx FIFO empty interrupt. (Always use the half-empty
+-01398                          * level to ensure that new requests are loaded as
+-01399                          * soon as possible.)
+-01400                          */
+-01401                         dwc_modify_reg32(&global_regs->gintmsk, 0,
+-01402                                          intr_mask.d32);
+-01403                 } else {
+-01404                         /*
+-01405                          * Disable the Tx FIFO empty interrupt since there are
+-01406                          * no more transactions that need to be queued right
+-01407                          * now. This function is called from interrupt
+-01408                          * handlers to queue more transactions as transfer
+-01409                          * states change.
+-01410                          */
+-01411                         dwc_modify_reg32(&global_regs->gintmsk, intr_mask.d32,
+-01412                                          0);
+-01413                 }
+-01414         }
+-01415 }
+-01416 
+-01426 void dwc_otg_hcd_queue_transactions(dwc_otg_hcd_t * hcd,
+-01427                                            dwc_otg_transaction_type_e tr_type)
+-01428 {
+-01429 #ifdef DEBUG_SOF
+-01430         DWC_DEBUGPL(DBG_HCD, "Queue Transactions\n");
+-01431 #endif
+-01432         /* Process host channels associated with periodic transfers. */
+-01433         if ((tr_type == DWC_OTG_TRANSACTION_PERIODIC ||
+-01434              tr_type == DWC_OTG_TRANSACTION_ALL) &&
+-01435             !DWC_LIST_EMPTY(&hcd->periodic_sched_assigned)) {
+-01436 
+-01437                 process_periodic_channels(hcd);
+-01438         }
+-01439 
+-01440         /* Process host channels associated with non-periodic transfers. */
+-01441         if (tr_type == DWC_OTG_TRANSACTION_NON_PERIODIC ||
+-01442             tr_type == DWC_OTG_TRANSACTION_ALL) {
+-01443                 if (!DWC_LIST_EMPTY(&hcd->non_periodic_sched_active)) {
+-01444                         process_non_periodic_channels(hcd);
+-01445                 } else {
+-01446                         /*
+-01447                          * Ensure NP Tx FIFO empty interrupt is disabled when
+-01448                          * there are no non-periodic transfers to process.
+-01449                          */
+-01450                         gintmsk_data_t gintmsk = {.d32 = 0 };
+-01451                         gintmsk.b.nptxfempty = 1;
+-01452                         dwc_modify_reg32(&hcd->core_if->core_global_regs->
+-01453                                          gintmsk, gintmsk.d32, 0);
+-01454                 }
+-01455         }
+-01456 }
+-01457  
+-01458 #ifdef DWC_HS_ELECT_TST
+-01459 /*
+-01460  * Quick and dirty hack to implement the HS Electrical Test
+-01461  * SINGLE_STEP_GET_DEVICE_DESCRIPTOR feature.
+-01462  *
+-01463  * This code was copied from our userspace app "hset". It sends a
+-01464  * Get Device Descriptor control sequence in two parts, first the
+-01465  * Setup packet by itself, followed some time later by the In and
+-01466  * Ack packets. Rather than trying to figure out how to add this
+-01467  * functionality to the normal driver code, we just hijack the
+-01468  * hardware, using these two function to drive the hardware
+-01469  * directly.
+-01470  */
+-01471 
+-01472 static dwc_otg_core_global_regs_t *global_regs;
+-01473 static dwc_otg_host_global_regs_t *hc_global_regs;
+-01474 static dwc_otg_hc_regs_t *hc_regs;
+-01475 static uint32_t *data_fifo;
+-01476 
+-01477 static void do_setup(void)
+-01478 {
+-01479         gintsts_data_t gintsts;
+-01480         hctsiz_data_t hctsiz;
+-01481         hcchar_data_t hcchar;
+-01482         haint_data_t haint;
+-01483         hcint_data_t hcint;
+-01484 
+-01485         /* Enable HAINTs */
+-01486         dwc_write_reg32(&hc_global_regs->haintmsk, 0x0001);
+-01487 
+-01488         /* Enable HCINTs */
+-01489         dwc_write_reg32(&hc_regs->hcintmsk, 0x04a3);
+-01490 
+-01491         /* Read GINTSTS */
+-01492         gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
+-01493 
+-01494         /* Read HAINT */
+-01495         haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
+-01496 
+-01497         /* Read HCINT */
+-01498         hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
+-01499 
+-01500         /* Read HCCHAR */
+-01501         hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
+-01502 
+-01503         /* Clear HCINT */
+-01504         dwc_write_reg32(&hc_regs->hcint, hcint.d32);
+-01505 
+-01506         /* Clear HAINT */
+-01507         dwc_write_reg32(&hc_global_regs->haint, haint.d32);
+-01508 
+-01509         /* Clear GINTSTS */
+-01510         dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
+-01511 
+-01512         /* Read GINTSTS */
+-01513         gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
+-01514 
+-01515         /*
+-01516          * Send Setup packet (Get Device Descriptor)
+-01517          */
+-01518 
+-01519         /* Make sure channel is disabled */
+-01520         hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
+-01521         if (hcchar.b.chen) {
+-01522                 hcchar.b.chdis = 1;
+-01523 //              hcchar.b.chen = 1;
+-01524                 dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
+-01525                 //sleep(1);
+-01526                 dwc_mdelay(1000);
+-01527 
+-01528                 /* Read GINTSTS */
+-01529                 gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
+-01530 
+-01531                 /* Read HAINT */
+-01532                 haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
+-01533 
+-01534                 /* Read HCINT */
+-01535                 hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
+-01536 
+-01537                 /* Read HCCHAR */
+-01538                 hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
+-01539 
+-01540                 /* Clear HCINT */
+-01541                 dwc_write_reg32(&hc_regs->hcint, hcint.d32);
+-01542 
+-01543                 /* Clear HAINT */
+-01544                 dwc_write_reg32(&hc_global_regs->haint, haint.d32);
+-01545 
+-01546                 /* Clear GINTSTS */
+-01547                 dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
+-01548 
+-01549                 hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
+-01550         }
+-01551 
+-01552         /* Set HCTSIZ */
+-01553         hctsiz.d32 = 0;
+-01554         hctsiz.b.xfersize = 8;
+-01555         hctsiz.b.pktcnt = 1;
+-01556         hctsiz.b.pid = DWC_OTG_HC_PID_SETUP;
+-01557         dwc_write_reg32(&hc_regs->hctsiz, hctsiz.d32);
+-01558 
+-01559         /* Set HCCHAR */
+-01560         hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
+-01561         hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
+-01562         hcchar.b.epdir = 0;
+-01563         hcchar.b.epnum = 0;
+-01564         hcchar.b.mps = 8;
+-01565         hcchar.b.chen = 1;
+-01566         dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
+-01567 
+-01568         /* Fill FIFO with Setup data for Get Device Descriptor */
+-01569         data_fifo = (uint32_t *) ((char *)global_regs + 0x1000);
+-01570         dwc_write_reg32(data_fifo++, 0x01000680);
+-01571         dwc_write_reg32(data_fifo++, 0x00080000);
+-01572 
+-01573         gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
+-01574 
+-01575         /* Wait for host channel interrupt */
+-01576         do {
+-01577                 gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
+-01578         } while (gintsts.b.hcintr == 0);
+-01579 
+-01580 
+-01581         /* Disable HCINTs */
+-01582         dwc_write_reg32(&hc_regs->hcintmsk, 0x0000);
+-01583 
+-01584         /* Disable HAINTs */
+-01585         dwc_write_reg32(&hc_global_regs->haintmsk, 0x0000);
+-01586 
+-01587         /* Read HAINT */
+-01588         haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
+-01589 
+-01590         /* Read HCINT */
+-01591         hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
+-01592 
+-01593         /* Read HCCHAR */
+-01594         hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
+-01595 
+-01596         /* Clear HCINT */
+-01597         dwc_write_reg32(&hc_regs->hcint, hcint.d32);
+-01598 
+-01599         /* Clear HAINT */
+-01600         dwc_write_reg32(&hc_global_regs->haint, haint.d32);
+-01601 
+-01602         /* Clear GINTSTS */
+-01603         dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
+-01604 
+-01605         /* Read GINTSTS */
+-01606         gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
+-01607 }
+-01608 
+-01609 static void do_in_ack(void)
+-01610 {
+-01611         gintsts_data_t gintsts;
+-01612         hctsiz_data_t hctsiz;
+-01613         hcchar_data_t hcchar;
+-01614         haint_data_t haint;
+-01615         hcint_data_t hcint;
+-01616         host_grxsts_data_t grxsts;
+-01617 
+-01618         /* Enable HAINTs */
+-01619         dwc_write_reg32(&hc_global_regs->haintmsk, 0x0001);
+-01620 
+-01621         /* Enable HCINTs */
+-01622         dwc_write_reg32(&hc_regs->hcintmsk, 0x04a3);
+-01623 
+-01624         /* Read GINTSTS */
+-01625         gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
+-01626 
+-01627         /* Read HAINT */
+-01628         haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
+-01629 
+-01630         /* Read HCINT */
+-01631         hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
+-01632 
+-01633         /* Read HCCHAR */
+-01634         hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
+-01635 
+-01636         /* Clear HCINT */
+-01637         dwc_write_reg32(&hc_regs->hcint, hcint.d32);
+-01638 
+-01639         /* Clear HAINT */
+-01640         dwc_write_reg32(&hc_global_regs->haint, haint.d32);
+-01641 
+-01642         /* Clear GINTSTS */
+-01643         dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
+-01644 
+-01645         /* Read GINTSTS */
+-01646         gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
+-01647 
+-01648         /*
+-01649          * Receive Control In packet
+-01650          */
+-01651 
+-01652         /* Make sure channel is disabled */
+-01653         hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
+-01654         if (hcchar.b.chen) {
+-01655                 hcchar.b.chdis = 1;
+-01656                 hcchar.b.chen = 1;
+-01657                 dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
+-01658                 //sleep(1);
+-01659                 dwc_mdelay(1000);
+-01660 
+-01661                 /* Read GINTSTS */
+-01662                 gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
+-01663 
+-01664                 /* Read HAINT */
+-01665                 haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
+-01666 
+-01667                 /* Read HCINT */
+-01668                 hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
+-01669 
+-01670                 /* Read HCCHAR */
+-01671                 hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
+-01672 
+-01673                 /* Clear HCINT */
+-01674                 dwc_write_reg32(&hc_regs->hcint, hcint.d32);
+-01675 
+-01676                 /* Clear HAINT */
+-01677                 dwc_write_reg32(&hc_global_regs->haint, haint.d32);
+-01678 
+-01679                 /* Clear GINTSTS */
+-01680                 dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
+-01681 
+-01682                 hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
+-01683         }
+-01684 
+-01685         /* Set HCTSIZ */
+-01686         hctsiz.d32 = 0;
+-01687         hctsiz.b.xfersize = 8;
+-01688         hctsiz.b.pktcnt = 1;
+-01689         hctsiz.b.pid = DWC_OTG_HC_PID_DATA1;
+-01690         dwc_write_reg32(&hc_regs->hctsiz, hctsiz.d32);
+-01691 
+-01692         /* Set HCCHAR */
+-01693         hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
+-01694         hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
+-01695         hcchar.b.epdir = 1;
+-01696         hcchar.b.epnum = 0;
+-01697         hcchar.b.mps = 8;
+-01698         hcchar.b.chen = 1;
+-01699         dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
+-01700 
+-01701         gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
+-01702 
+-01703         /* Wait for receive status queue interrupt */
+-01704         do {
+-01705                 gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
+-01706         } while (gintsts.b.rxstsqlvl == 0);
+-01707 
+-01708 
+-01709         /* Read RXSTS */
+-01710         grxsts.d32 = dwc_read_reg32(&global_regs->grxstsp);
+-01711 
+-01712         /* Clear RXSTSQLVL in GINTSTS */
+-01713         gintsts.d32 = 0;
+-01714         gintsts.b.rxstsqlvl = 1;
+-01715         dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
+-01716 
+-01717         switch (grxsts.b.pktsts) {
+-01718         case DWC_GRXSTS_PKTSTS_IN:
+-01719                 /* Read the data into the host buffer */
+-01720                 if (grxsts.b.bcnt > 0) {
+-01721                         int i;
+-01722                         int word_count = (grxsts.b.bcnt + 3) / 4;
+-01723 
+-01724                         data_fifo = (uint32_t *) ((char *)global_regs + 0x1000);
+-01725 
+-01726                         for (i = 0; i < word_count; i++) {
+-01727                                 (void)dwc_read_reg32(data_fifo++);
+-01728                         }
+-01729                 }
+-01730                 break;
+-01731 
+-01732         default:
+-01733                 break;
+-01734         }
+-01735 
+-01736         gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
+-01737 
+-01738         /* Wait for receive status queue interrupt */
+-01739         do {
+-01740                 gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
+-01741         } while (gintsts.b.rxstsqlvl == 0);
+-01742 
+-01743 
+-01744         /* Read RXSTS */
+-01745         grxsts.d32 = dwc_read_reg32(&global_regs->grxstsp);
+-01746 
+-01747         /* Clear RXSTSQLVL in GINTSTS */
+-01748         gintsts.d32 = 0;
+-01749         gintsts.b.rxstsqlvl = 1;
+-01750         dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
+-01751 
+-01752         switch (grxsts.b.pktsts) {
+-01753         case DWC_GRXSTS_PKTSTS_IN_XFER_COMP:
+-01754                 break;
+-01755 
+-01756         default:
+-01757                 break;
+-01758         }
+-01759 
+-01760         gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
+-01761 
+-01762         /* Wait for host channel interrupt */
+-01763         do {
+-01764                 gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
+-01765         } while (gintsts.b.hcintr == 0);
+-01766 
+-01767 
+-01768         /* Read HAINT */
+-01769         haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
+-01770 
+-01771         /* Read HCINT */
+-01772         hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
+-01773 
+-01774         /* Read HCCHAR */
+-01775         hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
+-01776 
+-01777         /* Clear HCINT */
+-01778         dwc_write_reg32(&hc_regs->hcint, hcint.d32);
+-01779 
+-01780         /* Clear HAINT */
+-01781         dwc_write_reg32(&hc_global_regs->haint, haint.d32);
+-01782 
+-01783         /* Clear GINTSTS */
+-01784         dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
+-01785 
+-01786         /* Read GINTSTS */
+-01787         gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
+-01788 
+-01789 //      usleep(100000);
+-01790 //      mdelay(100);
+-01791         dwc_mdelay(1);
+-01792 
+-01793         /*
+-01794          * Send handshake packet
+-01795          */
+-01796 
+-01797         /* Read HAINT */
+-01798         haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
+-01799 
+-01800         /* Read HCINT */
+-01801         hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
+-01802 
+-01803         /* Read HCCHAR */
+-01804         hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
+-01805 
+-01806         /* Clear HCINT */
+-01807         dwc_write_reg32(&hc_regs->hcint, hcint.d32);
+-01808 
+-01809         /* Clear HAINT */
+-01810         dwc_write_reg32(&hc_global_regs->haint, haint.d32);
+-01811 
+-01812         /* Clear GINTSTS */
+-01813         dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
+-01814 
+-01815         /* Read GINTSTS */
+-01816         gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
+-01817 
+-01818         /* Make sure channel is disabled */
+-01819         hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
+-01820         if (hcchar.b.chen) {
+-01821                 hcchar.b.chdis = 1;
+-01822                 hcchar.b.chen = 1;
+-01823                 dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
+-01824                 //sleep(1);
+-01825                 dwc_mdelay(1000);
+-01826 
+-01827                 /* Read GINTSTS */
+-01828                 gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
+-01829 
+-01830                 /* Read HAINT */
+-01831                 haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
+-01832 
+-01833                 /* Read HCINT */
+-01834                 hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
+-01835 
+-01836                 /* Read HCCHAR */
+-01837                 hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
+-01838 
+-01839                 /* Clear HCINT */
+-01840                 dwc_write_reg32(&hc_regs->hcint, hcint.d32);
+-01841 
+-01842                 /* Clear HAINT */
+-01843                 dwc_write_reg32(&hc_global_regs->haint, haint.d32);
+-01844 
+-01845                 /* Clear GINTSTS */
+-01846                 dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
+-01847 
+-01848                 hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
+-01849         }
+-01850 
+-01851         /* Set HCTSIZ */
+-01852         hctsiz.d32 = 0;
+-01853         hctsiz.b.xfersize = 0;
+-01854         hctsiz.b.pktcnt = 1;
+-01855         hctsiz.b.pid = DWC_OTG_HC_PID_DATA1;
+-01856         dwc_write_reg32(&hc_regs->hctsiz, hctsiz.d32);
+-01857 
+-01858         /* Set HCCHAR */
+-01859         hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
+-01860         hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
+-01861         hcchar.b.epdir = 0;
+-01862         hcchar.b.epnum = 0;
+-01863         hcchar.b.mps = 8;
+-01864         hcchar.b.chen = 1;
+-01865         dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
+-01866 
+-01867         gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
+-01868 
+-01869         /* Wait for host channel interrupt */
+-01870         do {
+-01871                 gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
+-01872         } while (gintsts.b.hcintr == 0);
+-01873 
+-01874 
+-01875         /* Disable HCINTs */
+-01876         dwc_write_reg32(&hc_regs->hcintmsk, 0x0000);
+-01877 
+-01878         /* Disable HAINTs */
+-01879         dwc_write_reg32(&hc_global_regs->haintmsk, 0x0000);
+-01880 
+-01881         /* Read HAINT */
+-01882         haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
+-01883 
+-01884         /* Read HCINT */
+-01885         hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
+-01886 
+-01887         /* Read HCCHAR */
+-01888         hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
+-01889 
+-01890         /* Clear HCINT */
+-01891         dwc_write_reg32(&hc_regs->hcint, hcint.d32);
+-01892 
+-01893         /* Clear HAINT */
+-01894         dwc_write_reg32(&hc_global_regs->haint, haint.d32);
+-01895 
+-01896         /* Clear GINTSTS */
+-01897         dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
+-01898 
+-01899         /* Read GINTSTS */
+-01900         gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
+-01901 }
+-01902 #endif
+-01903 
+-01905 int dwc_otg_hcd_hub_control(dwc_otg_hcd_t * dwc_otg_hcd,
+-01906                             uint16_t typeReq,
+-01907                             uint16_t wValue,
+-01908                             uint16_t wIndex, uint8_t * buf, uint16_t wLength)
+-01909 {
+-01910         int retval = 0;
+-01911 
+-01912         dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;
+-01913         usb_hub_descriptor_t *hub_desc;
+-01914         hprt0_data_t hprt0 = {.d32 = 0 };
+-01915 
+-01916         uint32_t port_status;
+-01917 
+-01918         switch (typeReq) {
+-01919         case UCR_CLEAR_HUB_FEATURE:
+-01920                 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
+-01921                             "ClearHubFeature 0x%x\n", wValue);
+-01922                 switch (wValue) {
+-01923                 case UHF_C_HUB_LOCAL_POWER:
+-01924                 case UHF_C_HUB_OVER_CURRENT:
+-01925                         /* Nothing required here */
+-01926                         break;
+-01927                 default:
+-01928                         retval = -DWC_E_INVALID;
+-01929                         DWC_ERROR("DWC OTG HCD - "
+-01930                                   "ClearHubFeature request %xh unknown\n",
+-01931                                   wValue);
+-01932                 }
+-01933                 break;
+-01934         case UCR_CLEAR_PORT_FEATURE:
+-01935 #ifdef CONFIG_USB_DWC_OTG_LPM
+-01936                 if (wValue != UHF_PORT_L1)
+-01937 #endif
+-01938                         if (!wIndex || wIndex > 1)
+-01939                                 goto error;
+-01940 
+-01941                 switch (wValue) {
+-01942                 case UHF_PORT_ENABLE:
+-01943                         DWC_DEBUGPL(DBG_ANY, "DWC OTG HCD HUB CONTROL - "
+-01944                                     "ClearPortFeature USB_PORT_FEAT_ENABLE\n");
+-01945                         hprt0.d32 = dwc_otg_read_hprt0(core_if);
+-01946                         hprt0.b.prtena = 1;
+-01947                         dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
+-01948                         break;
+-01949                 case UHF_PORT_SUSPEND:
+-01950                         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
+-01951                                     "ClearPortFeature USB_PORT_FEAT_SUSPEND\n");
+-01952 
+-01953                         dwc_write_reg32(core_if->pcgcctl, 0);
+-01954                         dwc_mdelay(5);
+-01955 
+-01956                         hprt0.d32 = dwc_otg_read_hprt0(core_if);
+-01957                         hprt0.b.prtres = 1;
+-01958                         dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
+-01959                         hprt0.b.prtsusp = 0;
+-01960                         /* Clear Resume bit */
+-01961                         dwc_mdelay(100);
+-01962                         hprt0.b.prtres = 0;
+-01963                         dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
+-01964                         break;
+-01965 #ifdef CONFIG_USB_DWC_OTG_LPM
+-01966                 case UHF_PORT_L1:
+-01967                         {
+-01968                                 pcgcctl_data_t pcgcctl = {.d32 = 0 };
+-01969                                 glpmcfg_data_t lpmcfg = {.d32 = 0 };
+-01970 
+-01971                                 lpmcfg.d32 =
+-01972                                     dwc_read_reg32(&core_if->core_global_regs->
+-01973                                                    glpmcfg);
+-01974                                 lpmcfg.b.en_utmi_sleep = 0;
+-01975                                 lpmcfg.b.hird_thres &= (~(1 << 4));
+-01976                                 lpmcfg.b.prt_sleep_sts = 1;
+-01977                                 dwc_write_reg32(&core_if->core_global_regs->
+-01978                                                 glpmcfg, lpmcfg.d32);
+-01979 
+-01980                                 /* Clear Enbl_L1Gating bit. */
+-01981                                 pcgcctl.b.enbl_sleep_gating = 1;
+-01982                                 dwc_modify_reg32(core_if->pcgcctl, pcgcctl.d32,
+-01983                                                  0);
+-01984 
+-01985                                 dwc_mdelay(5);
+-01986 
+-01987                                 hprt0.d32 = dwc_otg_read_hprt0(core_if);
+-01988                                 hprt0.b.prtres = 1;
+-01989                                 dwc_write_reg32(core_if->host_if->hprt0,
+-01990                                                 hprt0.d32);
+-01991                                 /* This bit will be cleared in wakeup interrupt handle */
+-01992                                 break;
+-01993                         }
+-01994 #endif
+-01995                 case UHF_PORT_POWER:
+-01996                         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
+-01997                                     "ClearPortFeature USB_PORT_FEAT_POWER\n");
+-01998                         hprt0.d32 = dwc_otg_read_hprt0(core_if);
+-01999                         hprt0.b.prtpwr = 0;
+-02000                         dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
+-02001                         break;
+-02002                 case UHF_PORT_INDICATOR:
+-02003                         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
+-02004                                     "ClearPortFeature USB_PORT_FEAT_INDICATOR\n");
+-02005                         /* Port inidicator not supported */
+-02006                         break;
+-02007                 case UHF_C_PORT_CONNECTION:
+-02008                         /* Clears drivers internal connect status change
+-02009                          * flag */
+-02010                         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
+-02011                                     "ClearPortFeature USB_PORT_FEAT_C_CONNECTION\n");
+-02012                         dwc_otg_hcd->flags.b.port_connect_status_change = 0;
+-02013                         break;
+-02014                 case UHF_C_PORT_RESET:
+-02015                         /* Clears the driver's internal Port Reset Change
+-02016                          * flag */
+-02017                         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
+-02018                                     "ClearPortFeature USB_PORT_FEAT_C_RESET\n");
+-02019                         dwc_otg_hcd->flags.b.port_reset_change = 0;
+-02020                         break;
+-02021                 case UHF_C_PORT_ENABLE:
+-02022                         /* Clears the driver's internal Port
+-02023                          * Enable/Disable Change flag */
+-02024                         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
+-02025                                     "ClearPortFeature USB_PORT_FEAT_C_ENABLE\n");
+-02026                         dwc_otg_hcd->flags.b.port_enable_change = 0;
+-02027                         break;
+-02028                 case UHF_C_PORT_SUSPEND:
+-02029                         /* Clears the driver's internal Port Suspend
+-02030                          * Change flag, which is set when resume signaling on
+-02031                          * the host port is complete */
+-02032                         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
+-02033                                     "ClearPortFeature USB_PORT_FEAT_C_SUSPEND\n");
+-02034                         dwc_otg_hcd->flags.b.port_suspend_change = 0;
+-02035                         break;
+-02036 #ifdef CONFIG_USB_DWC_OTG_LPM
+-02037                 case UHF_C_PORT_L1:
+-02038                         dwc_otg_hcd->flags.b.port_l1_change = 0;
+-02039                         break;
+-02040 #endif
+-02041                 case UHF_C_PORT_OVER_CURRENT:
+-02042                         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
+-02043                                     "ClearPortFeature USB_PORT_FEAT_C_OVER_CURRENT\n");
+-02044                         dwc_otg_hcd->flags.b.port_over_current_change = 0;
+-02045                         break;
+-02046                 default:
+-02047                         retval = -DWC_E_INVALID;
+-02048                         DWC_ERROR("DWC OTG HCD - "
+-02049                                   "ClearPortFeature request %xh "
+-02050                                   "unknown or unsupported\n", wValue);
+-02051                 }
+-02052                 break;
+-02053         case UCR_GET_HUB_DESCRIPTOR:
+-02054                 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
+-02055                             "GetHubDescriptor\n");
+-02056                 hub_desc = (usb_hub_descriptor_t *) buf;
+-02057                 hub_desc->bDescLength = 9;
+-02058                 hub_desc->bDescriptorType = 0x29;
+-02059                 hub_desc->bNbrPorts = 1;
+-02060                 USETW(hub_desc->wHubCharacteristics, 0x08);
+-02061                 hub_desc->bPwrOn2PwrGood = 1;
+-02062                 hub_desc->bHubContrCurrent = 0;
+-02063                 hub_desc->DeviceRemovable[0] = 0;
+-02064                 hub_desc->DeviceRemovable[1] = 0xff;
+-02065                 break;
+-02066         case UCR_GET_HUB_STATUS:
+-02067                 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
+-02068                             "GetHubStatus\n");
+-02069                 DWC_MEMSET(buf, 0, 4);
+-02070                 break;
+-02071         case UCR_GET_PORT_STATUS:
+-02072                 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
+-02073                             "GetPortStatus\n");
+-02074                 if (!wIndex || wIndex > 1)
+-02075                         goto error;
+-02076 
+-02077                 port_status = 0;
+-02078 
+-02079                 if (dwc_otg_hcd->flags.b.port_connect_status_change)
+-02080                         port_status |= (1 << UHF_C_PORT_CONNECTION);
+-02081 
+-02082                 if (dwc_otg_hcd->flags.b.port_enable_change)
+-02083                         port_status |= (1 << UHF_C_PORT_ENABLE);
+-02084 
+-02085                 if (dwc_otg_hcd->flags.b.port_suspend_change)
+-02086                         port_status |= (1 << UHF_C_PORT_SUSPEND);
+-02087 
+-02088                 if (dwc_otg_hcd->flags.b.port_l1_change)
+-02089                         port_status |= (1 << UHF_C_PORT_L1);
+-02090 
+-02091                 if (dwc_otg_hcd->flags.b.port_reset_change) {
+-02092                         port_status |= (1 << UHF_C_PORT_RESET);
+-02093                 }
+-02094 
+-02095                 if (dwc_otg_hcd->flags.b.port_over_current_change) {
+-02096                         DWC_ERROR("Device Not Supported\n");
+-02097                         port_status |= (1 << UHF_C_PORT_OVER_CURRENT);
+-02098                 }
+-02099 
+-02100                 if (!dwc_otg_hcd->flags.b.port_connect_status) {
+-02101                         /*
+-02102                          * The port is disconnected, which means the core is
+-02103                          * either in device mode or it soon will be. Just
+-02104                          * return 0's for the remainder of the port status
+-02105                          * since the port register can't be read if the core
+-02106                          * is in device mode.
+-02107                          */
+-02108                         *((__le32 *) buf) = dwc_cpu_to_le32(&port_status);
+-02109                         break;
+-02110                 }
+-02111 
+-02112                 hprt0.d32 = dwc_read_reg32(core_if->host_if->hprt0);
+-02113                 DWC_DEBUGPL(DBG_HCDV, "  HPRT0: 0x%08x\n", hprt0.d32);
+-02114 
+-02115                 if (hprt0.b.prtconnsts)
+-02116                         port_status |= (1 << UHF_PORT_CONNECTION);
+-02117 
+-02118                 if (hprt0.b.prtena)
+-02119                         port_status |= (1 << UHF_PORT_ENABLE);
+-02120 
+-02121                 if (hprt0.b.prtsusp)
+-02122                         port_status |= (1 << UHF_PORT_SUSPEND);
+-02123 
+-02124                 if (hprt0.b.prtovrcurract)
+-02125                         port_status |= (1 << UHF_PORT_OVER_CURRENT);
+-02126 
+-02127                 if (hprt0.b.prtrst)
+-02128                         port_status |= (1 << UHF_PORT_RESET);
+-02129 
+-02130                 if (hprt0.b.prtpwr)
+-02131                         port_status |= (1 << UHF_PORT_POWER);
+-02132 
+-02133                 if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_HIGH_SPEED)
+-02134                         port_status |= (1 << UHF_PORT_HIGH_SPEED);
+-02135                 else if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_LOW_SPEED)
+-02136                         port_status |= (1 << UHF_PORT_LOW_SPEED);
+-02137 
+-02138                 if (hprt0.b.prttstctl)
+-02139                         port_status |= (1 << UHF_PORT_TEST);
+-02140                 if (dwc_otg_get_lpm_portsleepstatus(dwc_otg_hcd->core_if)) {
+-02141                         port_status |= (1 << UHF_PORT_L1);
+-02142                 }
+-02143 
+-02144                 /* USB_PORT_FEAT_INDICATOR unsupported always 0 */
+-02145 
+-02146                 *((__le32 *) buf) = dwc_cpu_to_le32(&port_status);
+-02147 
+-02148                 break;
+-02149         case UCR_SET_HUB_FEATURE:
+-02150                 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
+-02151                             "SetHubFeature\n");
+-02152                 /* No HUB features supported */
+-02153                 break;
+-02154         case UCR_SET_PORT_FEATURE:
+-02155                 if (wValue != UHF_PORT_TEST && (!wIndex || wIndex > 1))
+-02156                         goto error;
+-02157 
+-02158                 if (!dwc_otg_hcd->flags.b.port_connect_status) {
+-02159                         /*
+-02160                          * The port is disconnected, which means the core is
+-02161                          * either in device mode or it soon will be. Just
+-02162                          * return without doing anything since the port
+-02163                          * register can't be written if the core is in device
+-02164                          * mode.
+-02165                          */
+-02166                         break;
+-02167                 }
+-02168 
+-02169                 switch (wValue) {
+-02170                 case UHF_PORT_SUSPEND:
+-02171                         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
+-02172                                     "SetPortFeature - USB_PORT_FEAT_SUSPEND\n");
+-02173                         if (dwc_otg_hcd_otg_port(dwc_otg_hcd) == wIndex &&
+-02174                             dwc_otg_hcd->fops->get_b_hnp_enable(dwc_otg_hcd)) {
+-02175                                 gotgctl_data_t gotgctl = {.d32 = 0 };
+-02176                                 gotgctl.b.hstsethnpen = 1;
+-02177                                 dwc_modify_reg32(&core_if->core_global_regs->
+-02178                                                  gotgctl, 0, gotgctl.d32);
+-02179                                 core_if->op_state = A_SUSPEND;
+-02180                         }
+-02181                         hprt0.d32 = dwc_otg_read_hprt0(core_if);
+-02182                         hprt0.b.prtsusp = 1;
+-02183                         dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
+-02184                         {
+-02185                                 uint64_t flags;
+-02186                                 /* Update lx_state */
+-02187                                 DWC_SPINLOCK_IRQSAVE(dwc_otg_hcd->lock, &flags);
+-02188                                 core_if->lx_state = DWC_OTG_L2;
+-02189                                 DWC_SPINUNLOCK_IRQRESTORE(dwc_otg_hcd->lock, flags);
+-02190                         }
+-02191                         /* Suspend the Phy Clock */
+-02192                         {
+-02193                                 pcgcctl_data_t pcgcctl = {.d32 = 0 };
+-02194                                 pcgcctl.b.stoppclk = 1;
+-02195                                 dwc_modify_reg32(core_if->pcgcctl, 0,
+-02196                                                  pcgcctl.d32);
+-02197                         }
+-02198 
+-02199                         /* For HNP the bus must be suspended for at least 200ms. */
+-02200                         if (dwc_otg_hcd->fops->get_b_hnp_enable(dwc_otg_hcd)) {
+-02201                                 dwc_mdelay(200);
+-02202                         }
+-02203                         break;
+-02204                 case UHF_PORT_POWER:
+-02205                         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
+-02206                                     "SetPortFeature - USB_PORT_FEAT_POWER\n");
+-02207                         hprt0.d32 = dwc_otg_read_hprt0(core_if);
+-02208                         hprt0.b.prtpwr = 1;
+-02209                         dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
+-02210                         break;
+-02211                 case UHF_PORT_RESET:
+-02212                         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
+-02213                                     "SetPortFeature - USB_PORT_FEAT_RESET\n");
+-02214                         {
+-02215                                 pcgcctl_data_t pcgcctl = {.d32 = 0 };
+-02216                                 pcgcctl.b.enbl_sleep_gating = 1;
+-02217                                 pcgcctl.b.stoppclk = 1;
+-02218                                 dwc_modify_reg32(core_if->pcgcctl, pcgcctl.d32,
+-02219                                                  0);
+-02220                                 dwc_write_reg32(core_if->pcgcctl, 0);
+-02221                         }
+-02222 #ifdef CONFIG_USB_DWC_OTG_LPM
+-02223                         {
+-02224                                 glpmcfg_data_t lpmcfg;
+-02225                                 lpmcfg.d32 =
+-02226                                     dwc_read_reg32(&core_if->core_global_regs->
+-02227                                                    glpmcfg);
+-02228                                 if (lpmcfg.b.prt_sleep_sts) {
+-02229                                         lpmcfg.b.en_utmi_sleep = 0;
+-02230                                         lpmcfg.b.hird_thres &= (~(1 << 4));
+-02231                                         dwc_write_reg32(&core_if->
+-02232                                                         core_global_regs->
+-02233                                                         glpmcfg, lpmcfg.d32);
+-02234                                         dwc_mdelay(1);
+-02235                                 }
+-02236                         }
+-02237 #endif
+-02238                         hprt0.d32 = dwc_otg_read_hprt0(core_if);
+-02239                         /* When B-Host the Port reset bit is set in
+-02240                          * the Start HCD Callback function, so that
+-02241                          * the reset is started within 1ms of the HNP
+-02242                          * success interrupt. */
+-02243                         if (!dwc_otg_hcd_is_b_host(dwc_otg_hcd)) {
+-02244                                 hprt0.b.prtrst = 1;
+-02245                                 dwc_write_reg32(core_if->host_if->hprt0,
+-02246                                                 hprt0.d32);
+-02247                         }
+-02248                         /* Clear reset bit in 10ms (FS/LS) or 50ms (HS) */
+-02249                         dwc_mdelay(60);
+-02250                         hprt0.b.prtrst = 0;
+-02251                         dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
+-02252                         core_if->lx_state = DWC_OTG_L0; /* Now back to the on state */
+-02253                         break;
+-02254 #ifdef DWC_HS_ELECT_TST
+-02255                 case UHF_PORT_TEST:
+-02256                         {
+-02257                                 uint32_t t;
+-02258                                 gintmsk_data_t gintmsk;
+-02259 
+-02260                                 t = (wIndex >> 8);      /* MSB wIndex USB */
+-02261                                 DWC_DEBUGPL(DBG_HCD,
+-02262                                             "DWC OTG HCD HUB CONTROL - "
+-02263                                             "SetPortFeature - USB_PORT_FEAT_TEST %d\n",
+-02264                                             t);
+-02265                                 DWC_WARN("USB_PORT_FEAT_TEST %d\n", t);
+-02266                                 if (t < 6) {
+-02267                                         hprt0.d32 = dwc_otg_read_hprt0(core_if);
+-02268                                         hprt0.b.prttstctl = t;
+-02269                                         dwc_write_reg32(core_if->host_if->hprt0,
+-02270                                                         hprt0.d32);
+-02271                                 } else {
+-02272                                         /* Setup global vars with reg addresses (quick and
+-02273                                          * dirty hack, should be cleaned up)
+-02274                                          */
+-02275                                         global_regs = core_if->core_global_regs;
+-02276                                         hc_global_regs =
+-02277                                             core_if->host_if->host_global_regs;
+-02278                                         hc_regs =
+-02279                                             (dwc_otg_hc_regs_t *) ((char *)
+-02280                                                                    global_regs +
+-02281                                                                    0x500);
+-02282                                         data_fifo =
+-02283                                             (uint32_t *) ((char *)global_regs +
+-02284                                                           0x1000);
+-02285 
+-02286                                         if (t == 6) {   /* HS_HOST_PORT_SUSPEND_RESUME */
+-02287                                                 /* Save current interrupt mask */
+-02288                                                 gintmsk.d32 =
+-02289                                                     dwc_read_reg32
+-02290                                                     (&global_regs->gintmsk);
+-02291 
+-02292                                                 /* Disable all interrupts while we muck with
+-02293                                                  * the hardware directly
+-02294                                                  */
+-02295                                                 dwc_write_reg32(&global_regs->
+-02296                                                                 gintmsk, 0);
+-02297 
+-02298                                                 /* 15 second delay per the test spec */
+-02299                                                 dwc_mdelay(15000);
+-02300 
+-02301                                                 /* Drive suspend on the root port */
+-02302                                                 hprt0.d32 =
+-02303                                                     dwc_otg_read_hprt0(core_if);
+-02304                                                 hprt0.b.prtsusp = 1;
+-02305                                                 hprt0.b.prtres = 0;
+-02306                                                 dwc_write_reg32(core_if->
+-02307                                                                 host_if->hprt0,
+-02308                                                                 hprt0.d32);
+-02309 
+-02310                                                 /* 15 second delay per the test spec */
+-02311                                                 dwc_mdelay(15000);
+-02312 
+-02313                                                 /* Drive resume on the root port */
+-02314                                                 hprt0.d32 =
+-02315                                                     dwc_otg_read_hprt0(core_if);
+-02316                                                 hprt0.b.prtsusp = 0;
+-02317                                                 hprt0.b.prtres = 1;
+-02318                                                 dwc_write_reg32(core_if->
+-02319                                                                 host_if->hprt0,
+-02320                                                                 hprt0.d32);
+-02321                                                 dwc_mdelay(100);
+-02322 
+-02323                                                 /* Clear the resume bit */
+-02324                                                 hprt0.b.prtres = 0;
+-02325                                                 dwc_write_reg32(core_if->
+-02326                                                                 host_if->hprt0,
+-02327                                                                 hprt0.d32);
+-02328 
+-02329                                                 /* Restore interrupts */
+-02330                                                 dwc_write_reg32(&global_regs->
+-02331                                                                 gintmsk,
+-02332                                                                 gintmsk.d32);
+-02333                                         } else if (t == 7) {    /* SINGLE_STEP_GET_DEVICE_DESCRIPTOR setup */
+-02334                                                 /* Save current interrupt mask */
+-02335                                                 gintmsk.d32 =
+-02336                                                     dwc_read_reg32
+-02337                                                     (&global_regs->gintmsk);
+-02338 
+-02339                                                 /* Disable all interrupts while we muck with
+-02340                                                  * the hardware directly
+-02341                                                  */
+-02342                                                 dwc_write_reg32(&global_regs->
+-02343                                                                 gintmsk, 0);
+-02344 
+-02345                                                 /* 15 second delay per the test spec */
+-02346                                                 dwc_mdelay(15000);
+-02347 
+-02348                                                 /* Send the Setup packet */
+-02349                                                 do_setup();
+-02350 
+-02351                                                 /* 15 second delay so nothing else happens for awhile */
+-02352                                                 dwc_mdelay(15000);
+-02353 
+-02354                                                 /* Restore interrupts */
+-02355                                                 dwc_write_reg32(&global_regs->
+-02356                                                                 gintmsk,
+-02357                                                                 gintmsk.d32);
+-02358                                         } else if (t == 8) {    /* SINGLE_STEP_GET_DEVICE_DESCRIPTOR execute */
+-02359                                                 /* Save current interrupt mask */
+-02360                                                 gintmsk.d32 =
+-02361                                                     dwc_read_reg32
+-02362                                                     (&global_regs->gintmsk);
+-02363 
+-02364                                                 /* Disable all interrupts while we muck with
+-02365                                                  * the hardware directly
+-02366                                                  */
+-02367                                                 dwc_write_reg32(&global_regs->
+-02368                                                                 gintmsk, 0);
+-02369 
+-02370                                                 /* Send the Setup packet */
+-02371                                                 do_setup();
+-02372 
+-02373                                                 /* 15 second delay so nothing else happens for awhile */
+-02374                                                 dwc_mdelay(15000);
+-02375 
+-02376                                                 /* Send the In and Ack packets */
+-02377                                                 do_in_ack();
+-02378 
+-02379                                                 /* 15 second delay so nothing else happens for awhile */
+-02380                                                 dwc_mdelay(15000);
+-02381 
+-02382                                                 /* Restore interrupts */
+-02383                                                 dwc_write_reg32(&global_regs->
+-02384                                                                 gintmsk,
+-02385                                                                 gintmsk.d32);
+-02386                                         }
+-02387                                 }
+-02388                                 break;
+-02389                         }
+-02390 #endif                          /* DWC_HS_ELECT_TST */
+-02391 
+-02392                 case UHF_PORT_INDICATOR:
+-02393                         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
+-02394                                     "SetPortFeature - USB_PORT_FEAT_INDICATOR\n");
+-02395                         /* Not supported */
+-02396                         break;
+-02397                 default:
+-02398                         retval = -DWC_E_INVALID;
+-02399                         DWC_ERROR("DWC OTG HCD - "
+-02400                                   "SetPortFeature request %xh "
+-02401                                   "unknown or unsupported\n", wValue);
+-02402                         break;
+-02403                 }
+-02404                 break;
+-02405 #ifdef CONFIG_USB_DWC_OTG_LPM
+-02406         case UCR_SET_AND_TEST_PORT_FEATURE:
+-02407                 if (wValue != UHF_PORT_L1) {
+-02408                         goto error;
+-02409                 }
+-02410                 {
+-02411                         int portnum, hird, devaddr, remwake;
+-02412                         glpmcfg_data_t lpmcfg;
+-02413                         uint32_t time_usecs;
+-02414                         gintsts_data_t gintsts;
+-02415                         gintmsk_data_t gintmsk;
+-02416 
+-02417                         if (!dwc_otg_get_param_lpm_enable(core_if)) {
+-02418                                 goto error;
+-02419                         }
+-02420                         if (wValue != UHF_PORT_L1 || wLength != 1) {
+-02421                                 goto error;
+-02422                         }
+-02423                         /* Check if the port currently is in SLEEP state */
+-02424                         lpmcfg.d32 =
+-02425                             dwc_read_reg32(&core_if->core_global_regs->glpmcfg);
+-02426                         if (lpmcfg.b.prt_sleep_sts) {
+-02427                                 DWC_INFO("Port is already in sleep mode\n");
+-02428                                 buf[0] = 0;     /* Return success */
+-02429                                 break;
+-02430                         }
+-02431 
+-02432                         portnum = wIndex & 0xf;
+-02433                         hird = (wIndex >> 4) & 0xf;
+-02434                         devaddr = (wIndex >> 8) & 0x7f;
+-02435                         remwake = (wIndex >> 15);
+-02436 
+-02437                         if (portnum != 1) {
+-02438                                 retval = -DWC_E_INVALID;
+-02439                                 DWC_WARN
+-02440                                     ("Wrong port number(%d) in SetandTestPortFeature request\n",
+-02441                                      portnum);
+-02442                                 break;
+-02443                         }
+-02444 
+-02445                         DWC_PRINTF
+-02446                             ("SetandTestPortFeature request: portnum = %d, hird = %d, devaddr = %d, rewake = %d\n",
+-02447                              portnum, hird, devaddr, remwake);
+-02448                         /* Disable LPM interrupt */
+-02449                         gintmsk.d32 = 0;
+-02450                         gintmsk.b.lpmtranrcvd = 1;
+-02451                         dwc_modify_reg32(&core_if->core_global_regs->gintmsk,
+-02452                                          gintmsk.d32, 0);
+-02453 
+-02454                         if (dwc_otg_hcd_send_lpm
+-02455                             (dwc_otg_hcd, devaddr, hird, remwake)) {
+-02456                                 retval = -DWC_E_INVALID;
+-02457                                 break;
+-02458                         }
+-02459 
+-02460                         time_usecs = 10 * (lpmcfg.b.retry_count + 1);
+-02461                         /* We will consider timeout if time_usecs microseconds pass,
+-02462                          * and we don't receive LPM transaction status.
+-02463                          * After receiving non-error responce(ACK/NYET/STALL) from device,
+-02464                          *  core will set lpmtranrcvd bit.
+-02465                          */
+-02466                         do {
+-02467                                 gintsts.d32 =
+-02468                                     dwc_read_reg32(&core_if->core_global_regs->
+-02469                                                    gintsts);
+-02470                                 if (gintsts.b.lpmtranrcvd) {
+-02471                                         break;
+-02472                                 }
+-02473                                 dwc_udelay(1);
+-02474                         } while (--time_usecs);
+-02475                         /* lpm_int bit will be cleared in LPM interrupt handler */
+-02476 
+-02477                         /* Now fill status
+-02478                          * 0x00 - Success
+-02479                          * 0x10 - NYET
+-02480                          * 0x11 - Timeout
+-02481                          */
+-02482                         if (!gintsts.b.lpmtranrcvd) {
+-02483                                 buf[0] = 0x3;   /* Completion code is Timeout */
+-02484                                 dwc_otg_hcd_free_hc_from_lpm(dwc_otg_hcd);
+-02485                         } else {
+-02486                                 lpmcfg.d32 =
+-02487                                     dwc_read_reg32(&core_if->core_global_regs->
+-02488                                                    glpmcfg);
+-02489                                 if (lpmcfg.b.lpm_resp == 0x3) {
+-02490                                         /* ACK responce from the device */
+-02491                                         buf[0] = 0x00;  /* Success */
+-02492                                 } else if (lpmcfg.b.lpm_resp == 0x2) {
+-02493                                         /* NYET responce from the device */
+-02494                                         buf[0] = 0x2;
+-02495                                 } else {
+-02496                                         /* Otherwise responce with Timeout */
+-02497                                         buf[0] = 0x3;
+-02498                                 }
+-02499                         }
+-02500                         DWC_PRINTF("Device responce to LPM trans is %x\n",
+-02501                                    lpmcfg.b.lpm_resp);
+-02502                         dwc_modify_reg32(&core_if->core_global_regs->gintmsk, 0,
+-02503                                          gintmsk.d32);
+-02504 
+-02505                         break;
+-02506                 }
+-02507 #endif                          /* CONFIG_USB_DWC_OTG_LPM */
+-02508         default:
+-02509               error:
+-02510                 retval = -DWC_E_INVALID;
+-02511                 DWC_WARN("DWC OTG HCD - "
+-02512                          "Unknown hub control request type or invalid typeReq: %xh wIndex: %xh wValue: %xh\n",
+-02513                          typeReq, wIndex, wValue);
+-02514                 break;
+-02515         }
+-02516 
+-02517         return retval;
+-02518 }
+-02519 
+-02520 #ifdef CONFIG_USB_DWC_OTG_LPM
+-02521 
+-02522 int dwc_otg_hcd_get_hc_for_lpm_tran(dwc_otg_hcd_t * hcd, uint8_t devaddr)
+-02523 {
+-02524         dwc_otg_core_if_t *core_if = hcd->core_if;
+-02525         dwc_hc_t *hc;
+-02526         hcchar_data_t hcchar;
+-02527         gintmsk_data_t gintmsk = {.d32 = 0 };
+-02528 
+-02529         if (DWC_CIRCLEQ_EMPTY(&hcd->free_hc_list)) {
+-02530                 DWC_PRINTF("No free channel to select for LPM transaction\n");
+-02531                 return -1;
+-02532         }
+-02533 
+-02534         hc = DWC_CIRCLEQ_FIRST(&hcd->free_hc_list);
+-02535 
+-02536         /* Mask host channel interrupts. */
+-02537         gintmsk.b.hcintr = 1;
+-02538         dwc_modify_reg32(&core_if->core_global_regs->gintmsk, gintmsk.d32, 0);
+-02539 
+-02540         /* Fill fields that core needs for LPM transaction */
+-02541         hcchar.b.devaddr = devaddr;
+-02542         hcchar.b.epnum = 0;
+-02543         hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
+-02544         hcchar.b.mps = 64;
+-02545         hcchar.b.lspddev = (hc->speed == DWC_OTG_EP_SPEED_LOW);
+-02546         hcchar.b.epdir = 0;     /* OUT */
+-02547         dwc_write_reg32(&core_if->host_if->hc_regs[hc->hc_num]->hcchar,
+-02548                         hcchar.d32);
+-02549 
+-02550         /* Remove the host channel from the free list. */
+-02551         DWC_CIRCLEQ_REMOVE_INIT(&hcd->free_hc_list, hc, hc_list_entry);
+-02552 
+-02553         DWC_PRINTF("hcnum = %d devaddr = %d\n", hc->hc_num, devaddr);
+-02554 
+-02555         return hc->hc_num;
+-02556 }
+-02557 
+-02559 void dwc_otg_hcd_free_hc_from_lpm(dwc_otg_hcd_t * hcd)
+-02560 {
+-02561         dwc_hc_t *hc;
+-02562         glpmcfg_data_t lpmcfg;
+-02563         uint8_t hc_num;
+-02564 
+-02565         lpmcfg.d32 = dwc_read_reg32(&hcd->core_if->core_global_regs->glpmcfg);
+-02566         hc_num = lpmcfg.b.lpm_chan_index;
+-02567 
+-02568         hc = hcd->hc_ptr_array[hc_num];
+-02569 
+-02570         DWC_PRINTF("Freeing channel %d after LPM\n", hc_num);
+-02571         /* Return host channel to free list */
+-02572         DWC_CIRCLEQ_INSERT_TAIL(&hcd->free_hc_list, hc, hc_list_entry);
+-02573 }
+-02574 
+-02575 int dwc_otg_hcd_send_lpm(dwc_otg_hcd_t * hcd, uint8_t devaddr, uint8_t hird,
+-02576                          uint8_t bRemoteWake)
+-02577 {
+-02578         glpmcfg_data_t lpmcfg;
+-02579         pcgcctl_data_t pcgcctl = {.d32 = 0 };
+-02580         int channel;
+-02581 
+-02582         channel = dwc_otg_hcd_get_hc_for_lpm_tran(hcd, devaddr);
+-02583         if (channel < 0) {
+-02584                 return channel;
+-02585         }
+-02586 
+-02587         pcgcctl.b.enbl_sleep_gating = 1;
+-02588         dwc_modify_reg32(hcd->core_if->pcgcctl, 0, pcgcctl.d32);
+-02589 
+-02590         /* Read LPM config register */
+-02591         lpmcfg.d32 = dwc_read_reg32(&hcd->core_if->core_global_regs->glpmcfg);
+-02592 
+-02593         /* Program LPM transaction fields */
+-02594         lpmcfg.b.rem_wkup_en = bRemoteWake;
+-02595         lpmcfg.b.hird = hird;
+-02596         lpmcfg.b.hird_thres = 0x1c;
+-02597         lpmcfg.b.lpm_chan_index = channel;
+-02598         lpmcfg.b.en_utmi_sleep = 1;
+-02599         /* Program LPM config register */
+-02600         dwc_write_reg32(&hcd->core_if->core_global_regs->glpmcfg, lpmcfg.d32);
+-02601 
+-02602         /* Send LPM transaction */
+-02603         lpmcfg.b.send_lpm = 1;
+-02604         dwc_write_reg32(&hcd->core_if->core_global_regs->glpmcfg, lpmcfg.d32);
+-02605 
+-02606         return 0;
+-02607 }
+-02608 
+-02609 #endif                          /* CONFIG_USB_DWC_OTG_LPM */
+-02610 
+-02611 int dwc_otg_hcd_is_status_changed(dwc_otg_hcd_t * hcd, int port)
+-02612 {
+-02613         int retval;
+-02614 
+-02615         if (port != 1) {
+-02616                 return -DWC_E_INVALID;
+-02617         }
+-02618 
+-02619         retval = (hcd->flags.b.port_connect_status_change ||
+-02620                   hcd->flags.b.port_reset_change ||
+-02621                   hcd->flags.b.port_enable_change ||
+-02622                   hcd->flags.b.port_suspend_change ||
+-02623                   hcd->flags.b.port_over_current_change);
+-02624 #ifdef DEBUG
+-02625         if (retval) {
+-02626                 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB STATUS DATA:"
+-02627                             " Root port status changed\n");
+-02628                 DWC_DEBUGPL(DBG_HCDV, "  port_connect_status_change: %d\n",
+-02629                             hcd->flags.b.port_connect_status_change);
+-02630                 DWC_DEBUGPL(DBG_HCDV, "  port_reset_change: %d\n",
+-02631                             hcd->flags.b.port_reset_change);
+-02632                 DWC_DEBUGPL(DBG_HCDV, "  port_enable_change: %d\n",
+-02633                             hcd->flags.b.port_enable_change);
+-02634                 DWC_DEBUGPL(DBG_HCDV, "  port_suspend_change: %d\n",
+-02635                             hcd->flags.b.port_suspend_change);
+-02636                 DWC_DEBUGPL(DBG_HCDV, "  port_over_current_change: %d\n",
+-02637                             hcd->flags.b.port_over_current_change);
+-02638         }
+-02639 #endif
+-02640         return retval;
+-02641 }
+-02642 
+-02643 int dwc_otg_hcd_get_frame_number(dwc_otg_hcd_t * dwc_otg_hcd)
+-02644 {
+-02645         hfnum_data_t hfnum;
+-02646         hfnum.d32 = dwc_read_reg32(&dwc_otg_hcd->core_if->
+-02647                                    host_if->host_global_regs->hfnum);
+-02648 
+-02649 #ifdef DEBUG_SOF
+-02650         DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD GET FRAME NUMBER %d\n",
+-02651                     hfnum.b.frnum);
+-02652 #endif
+-02653         return hfnum.b.frnum;
+-02654 }
+-02655 
+-02656 int dwc_otg_hcd_start(dwc_otg_hcd_t * hcd,
+-02657                       struct dwc_otg_hcd_function_ops *fops)
+-02658 {
+-02659         int retval = 0;
+-02660 
+-02661         hcd->fops = fops;
+-02662         if (!dwc_otg_is_device_mode(hcd->core_if)) {
+-02663                 dwc_otg_hcd_reinit(hcd);
+-02664         } else {
+-02665                 retval = -DWC_E_NO_DEVICE;
+-02666         }
+-02667 
+-02668         return retval;
+-02669 }
+-02670 
+-02671 void *dwc_otg_hcd_get_priv_data(dwc_otg_hcd_t * hcd)
+-02672 {
+-02673         return hcd->priv;
+-02674 }
+-02675 
+-02676 void dwc_otg_hcd_set_priv_data(dwc_otg_hcd_t * hcd, void *priv_data)
+-02677 {
+-02678         hcd->priv = priv_data;
+-02679 }
+-02680 
+-02681 uint32_t dwc_otg_hcd_otg_port(dwc_otg_hcd_t * hcd)
+-02682 {
+-02683         return hcd->otg_port;
+-02684 }
+-02685 
+-02686 uint32_t dwc_otg_hcd_is_b_host(dwc_otg_hcd_t * hcd)
+-02687 {
+-02688         uint32_t is_b_host;
+-02689         if (hcd->core_if->op_state == B_HOST) {
+-02690                 is_b_host = 1;
+-02691         } else {
+-02692                 is_b_host = 0;
+-02693         }
+-02694 
+-02695         return is_b_host;
+-02696 }
+-02697 
+-02698 dwc_otg_hcd_urb_t *dwc_otg_hcd_urb_alloc(dwc_otg_hcd_t * hcd,
+-02699                                          int iso_desc_count, int atomic_alloc)
+-02700 {
+-02701         dwc_otg_hcd_urb_t *dwc_otg_urb;
+-02702         uint32_t size;
+-02703 
+-02704         size =
+-02705             sizeof(*dwc_otg_urb) +
+-02706             iso_desc_count * sizeof(struct dwc_otg_hcd_iso_packet_desc);
+-02707         if (atomic_alloc) {
+-02708                 dwc_otg_urb = dwc_alloc_atomic(size);
+-02709         } else {
+-02710                 dwc_otg_urb = dwc_alloc(size);
+-02711         }
+-02712         dwc_otg_urb->packet_count = iso_desc_count;
+-02713 
+-02714         return dwc_otg_urb;
+-02715 }
+-02716 
+-02717 void dwc_otg_hcd_urb_set_pipeinfo(dwc_otg_hcd_urb_t * dwc_otg_urb,
+-02718                                   uint8_t dev_addr, uint8_t ep_num,
+-02719                                   uint8_t ep_type, uint8_t ep_dir, uint16_t mps)
+-02720 {
+-02721         dwc_otg_hcd_fill_pipe(&dwc_otg_urb->pipe_info, dev_addr, ep_num,
+-02722                               ep_type, ep_dir, mps);
+-02723 #if 0
+-02724         DWC_PRINTF
+-02725             ("addr = %d, ep_num = %d, ep_dir = 0x%x, ep_type = 0x%x, mps = %d\n",
+-02726              dev_addr, ep_num, ep_dir, ep_type, mps);
+-02727 #endif
+-02728 }
+-02729 
+-02730 void dwc_otg_hcd_urb_set_params(dwc_otg_hcd_urb_t * dwc_otg_urb,
+-02731                                 void *urb_handle, void *buf, dwc_dma_t dma,
+-02732                                 uint32_t buflen, void *setup_packet,
+-02733                                 dwc_dma_t setup_dma, uint32_t flags,
+-02734                                 uint16_t interval)
+-02735 {
+-02736         dwc_otg_urb->priv = urb_handle;
+-02737         dwc_otg_urb->buf = buf;
+-02738         dwc_otg_urb->dma = dma;
+-02739         dwc_otg_urb->length = buflen;
+-02740         dwc_otg_urb->setup_packet = setup_packet;
+-02741         dwc_otg_urb->setup_dma = setup_dma;
+-02742         dwc_otg_urb->flags = flags;
+-02743         dwc_otg_urb->interval = interval;
+-02744         dwc_otg_urb->status = -DWC_E_IN_PROGRESS;
+-02745 }
+-02746 
+-02747 uint32_t dwc_otg_hcd_urb_get_status(dwc_otg_hcd_urb_t * dwc_otg_urb)
+-02748 {
+-02749         return dwc_otg_urb->status;
+-02750 }
+-02751 
+-02752 uint32_t dwc_otg_hcd_urb_get_actual_length(dwc_otg_hcd_urb_t * dwc_otg_urb)
+-02753 {
+-02754         return dwc_otg_urb->actual_length;
+-02755 }
+-02756 
+-02757 uint32_t dwc_otg_hcd_urb_get_error_count(dwc_otg_hcd_urb_t * dwc_otg_urb)
+-02758 {
+-02759         return dwc_otg_urb->error_count;
+-02760 }
+-02761 
+-02762 void dwc_otg_hcd_urb_set_iso_desc_params(dwc_otg_hcd_urb_t * dwc_otg_urb,
+-02763                                          int desc_num, uint32_t offset,
+-02764                                          uint32_t length)
+-02765 {
+-02766         dwc_otg_urb->iso_descs[desc_num].offset = offset;
+-02767         dwc_otg_urb->iso_descs[desc_num].length = length;
+-02768 }
+-02769 
+-02770 uint32_t dwc_otg_hcd_urb_get_iso_desc_status(dwc_otg_hcd_urb_t * dwc_otg_urb,
+-02771                                              int desc_num)
+-02772 {
+-02773         return dwc_otg_urb->iso_descs[desc_num].status;
+-02774 }
+-02775 
+-02776 uint32_t dwc_otg_hcd_urb_get_iso_desc_actual_length(dwc_otg_hcd_urb_t *
+-02777                                                     dwc_otg_urb, int desc_num)
+-02778 {
+-02779         return dwc_otg_urb->iso_descs[desc_num].actual_length;
+-02780 }
+-02781 
+-02782 int dwc_otg_hcd_is_bandwidth_allocated(dwc_otg_hcd_t * hcd, void *ep_handle)
+-02783 {
+-02784         int allocated = 0;
+-02785         dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle;
+-02786 
+-02787         if (qh) {
+-02788                 if (!DWC_LIST_EMPTY(&qh->qh_list_entry)) {
+-02789                         allocated = 1;
+-02790                 }
+-02791         }
+-02792         return allocated;
+-02793 }
+-02794 
+-02795 int dwc_otg_hcd_is_bandwidth_freed(dwc_otg_hcd_t * hcd, void *ep_handle)
+-02796 {
+-02797         dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle;
+-02798         int freed = 0;
+-02799         DWC_ASSERT(qh, "qh is not allocated\n");
+-02800 
+-02801         if (DWC_LIST_EMPTY(&qh->qh_list_entry)) {
+-02802                 freed = 1;
+-02803         }
+-02804 
+-02805         return freed;
+-02806 }
+-02807 
+-02808 uint8_t dwc_otg_hcd_get_ep_bandwidth(dwc_otg_hcd_t * hcd, void *ep_handle)
+-02809 {
+-02810         dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle;
+-02811         DWC_ASSERT(qh, "qh is not allocated\n");
+-02812         return qh->usecs;
+-02813 }
+-02814 
+-02815 void dwc_otg_hcd_dump_state(dwc_otg_hcd_t * hcd)
+-02816 {
+-02817 #ifdef DEBUG
+-02818         int num_channels;
+-02819         int i;
+-02820         gnptxsts_data_t np_tx_status;
+-02821         hptxsts_data_t p_tx_status;
+-02822 
+-02823         num_channels = hcd->core_if->core_params->host_channels;
+-02824         DWC_PRINTF("\n");
+-02825         DWC_PRINTF
+-02826             ("************************************************************\n");
+-02827         DWC_PRINTF("HCD State:\n");
+-02828         DWC_PRINTF("  Num channels: %d\n", num_channels);
+-02829         for (i = 0; i < num_channels; i++) {
+-02830                 dwc_hc_t *hc = hcd->hc_ptr_array[i];
+-02831                 DWC_PRINTF("  Channel %d:\n", i);
+-02832                 DWC_PRINTF("    dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
+-02833                            hc->dev_addr, hc->ep_num, hc->ep_is_in);
+-02834                 DWC_PRINTF("    speed: %d\n", hc->speed);
+-02835                 DWC_PRINTF("    ep_type: %d\n", hc->ep_type);
+-02836                 DWC_PRINTF("    max_packet: %d\n", hc->max_packet);
+-02837                 DWC_PRINTF("    data_pid_start: %d\n", hc->data_pid_start);
+-02838                 DWC_PRINTF("    multi_count: %d\n", hc->multi_count);
+-02839                 DWC_PRINTF("    xfer_started: %d\n", hc->xfer_started);
+-02840                 DWC_PRINTF("    xfer_buff: %p\n", hc->xfer_buff);
+-02841                 DWC_PRINTF("    xfer_len: %d\n", hc->xfer_len);
+-02842                 DWC_PRINTF("    xfer_count: %d\n", hc->xfer_count);
+-02843                 DWC_PRINTF("    halt_on_queue: %d\n", hc->halt_on_queue);
+-02844                 DWC_PRINTF("    halt_pending: %d\n", hc->halt_pending);
+-02845                 DWC_PRINTF("    halt_status: %d\n", hc->halt_status);
+-02846                 DWC_PRINTF("    do_split: %d\n", hc->do_split);
+-02847                 DWC_PRINTF("    complete_split: %d\n", hc->complete_split);
+-02848                 DWC_PRINTF("    hub_addr: %d\n", hc->hub_addr);
+-02849                 DWC_PRINTF("    port_addr: %d\n", hc->port_addr);
+-02850                 DWC_PRINTF("    xact_pos: %d\n", hc->xact_pos);
+-02851                 DWC_PRINTF("    requests: %d\n", hc->requests);
+-02852                 DWC_PRINTF("    qh: %p\n", hc->qh);
+-02853                 if (hc->xfer_started) {
+-02854                         hfnum_data_t hfnum;
+-02855                         hcchar_data_t hcchar;
+-02856                         hctsiz_data_t hctsiz;
+-02857                         hcint_data_t hcint;
+-02858                         hcintmsk_data_t hcintmsk;
+-02859                         hfnum.d32 =
+-02860                             dwc_read_reg32(&hcd->core_if->host_if->
+-02861                                            host_global_regs->hfnum);
+-02862                         hcchar.d32 =
+-02863                             dwc_read_reg32(&hcd->core_if->host_if->hc_regs[i]->
+-02864                                            hcchar);
+-02865                         hctsiz.d32 =
+-02866                             dwc_read_reg32(&hcd->core_if->host_if->hc_regs[i]->
+-02867                                            hctsiz);
+-02868                         hcint.d32 =
+-02869                             dwc_read_reg32(&hcd->core_if->host_if->hc_regs[i]->
+-02870                                            hcint);
+-02871                         hcintmsk.d32 =
+-02872                             dwc_read_reg32(&hcd->core_if->host_if->hc_regs[i]->
+-02873                                            hcintmsk);
+-02874                         DWC_PRINTF("    hfnum: 0x%08x\n", hfnum.d32);
+-02875                         DWC_PRINTF("    hcchar: 0x%08x\n", hcchar.d32);
+-02876                         DWC_PRINTF("    hctsiz: 0x%08x\n", hctsiz.d32);
+-02877                         DWC_PRINTF("    hcint: 0x%08x\n", hcint.d32);
+-02878                         DWC_PRINTF("    hcintmsk: 0x%08x\n", hcintmsk.d32);
+-02879                 }
+-02880                 if (hc->xfer_started && hc->qh) {
+-02881                         dwc_otg_qtd_t *qtd;
+-02882                         dwc_otg_hcd_urb_t *urb;
+-02883                         
+-02884                         DWC_CIRCLEQ_FOREACH(qtd, &hc->qh->qtd_list, qtd_list_entry) {
+-02885                                 if(!qtd->in_process)
+-02886                                         break;
+-02887                                 
+-02888                                 urb = qtd->urb;
+-02889                         DWC_PRINTF("    URB Info:\n");
+-02890                         DWC_PRINTF("      qtd: %p, urb: %p\n", qtd, urb);
+-02891                         if (urb) {
+-02892                                 DWC_PRINTF("      Dev: %d, EP: %d %s\n",
+-02893                                            dwc_otg_hcd_get_dev_addr(&urb->
+-02894                                                                     pipe_info),
+-02895                                            dwc_otg_hcd_get_ep_num(&urb->
+-02896                                                                   pipe_info),
+-02897                                            dwc_otg_hcd_is_pipe_in(&urb->
+-02898                                                                   pipe_info) ?
+-02899                                            "IN" : "OUT");
+-02900                                 DWC_PRINTF("      Max packet size: %d\n",
+-02901                                            dwc_otg_hcd_get_mps(&urb->
+-02902                                                                pipe_info));
+-02903                                 DWC_PRINTF("      transfer_buffer: %p\n",
+-02904                                            urb->buf);
+-02905                                 DWC_PRINTF("      transfer_dma: %p\n",
+-02906                                            (void *)urb->dma);
+-02907                                 DWC_PRINTF("      transfer_buffer_length: %d\n",
+-02908                                            urb->length);
+-02909                                 DWC_PRINTF("      actual_length: %d\n",
+-02910                                            urb->actual_length);
+-02911                         }
+-02912                 }
+-02913         }
+-02914         }
+-02915         DWC_PRINTF("  non_periodic_channels: %d\n", hcd->non_periodic_channels);
+-02916         DWC_PRINTF("  periodic_channels: %d\n", hcd->periodic_channels);
+-02917         DWC_PRINTF("  periodic_usecs: %d\n", hcd->periodic_usecs);
+-02918         np_tx_status.d32 =
+-02919             dwc_read_reg32(&hcd->core_if->core_global_regs->gnptxsts);
+-02920         DWC_PRINTF("  NP Tx Req Queue Space Avail: %d\n",
+-02921                    np_tx_status.b.nptxqspcavail);
+-02922         DWC_PRINTF("  NP Tx FIFO Space Avail: %d\n",
+-02923                    np_tx_status.b.nptxfspcavail);
+-02924         p_tx_status.d32 =
+-02925             dwc_read_reg32(&hcd->core_if->host_if->host_global_regs->hptxsts);
+-02926         DWC_PRINTF("  P Tx Req Queue Space Avail: %d\n",
+-02927                    p_tx_status.b.ptxqspcavail);
+-02928         DWC_PRINTF("  P Tx FIFO Space Avail: %d\n", p_tx_status.b.ptxfspcavail);
+-02929         dwc_otg_hcd_dump_frrem(hcd);
+-02930         dwc_otg_dump_global_registers(hcd->core_if);
+-02931         dwc_otg_dump_host_registers(hcd->core_if);
+-02932         DWC_PRINTF
+-02933             ("************************************************************\n");
+-02934         DWC_PRINTF("\n");
+-02935 #endif
+-02936 }
+-02937 
+-02938 #ifdef DEBUG
+-02939 void dwc_print_setup_data(uint8_t * setup)
+-02940 {
+-02941         int i;
+-02942         if (CHK_DEBUG_LEVEL(DBG_HCD)) {
+-02943                 DWC_PRINTF("Setup Data = MSB ");
+-02944                 for (i = 7; i >= 0; i--)
+-02945                         DWC_PRINTF("%02x ", setup[i]);
+-02946                 DWC_PRINTF("\n");
+-02947                 DWC_PRINTF("  bmRequestType Tranfer = %s\n",
+-02948                            (setup[0] & 0x80) ? "Device-to-Host" :
+-02949                            "Host-to-Device");
+-02950                 DWC_PRINTF("  bmRequestType Type = ");
+-02951                 switch ((setup[0] & 0x60) >> 5) {
+-02952                 case 0:
+-02953                         DWC_PRINTF("Standard\n");
+-02954                         break;
+-02955                 case 1:
+-02956                         DWC_PRINTF("Class\n");
+-02957                         break;
+-02958                 case 2:
+-02959                         DWC_PRINTF("Vendor\n");
+-02960                         break;
+-02961                 case 3:
+-02962                         DWC_PRINTF("Reserved\n");
+-02963                         break;
+-02964                 }
+-02965                 DWC_PRINTF("  bmRequestType Recipient = ");
+-02966                 switch (setup[0] & 0x1f) {
+-02967                 case 0:
+-02968                         DWC_PRINTF("Device\n");
+-02969                         break;
+-02970                 case 1:
+-02971                         DWC_PRINTF("Interface\n");
+-02972                         break;
+-02973                 case 2:
+-02974                         DWC_PRINTF("Endpoint\n");
+-02975                         break;
+-02976                 case 3:
+-02977                         DWC_PRINTF("Other\n");
+-02978                         break;
+-02979                 default:
+-02980                         DWC_PRINTF("Reserved\n");
+-02981                         break;
+-02982                 }
+-02983                 DWC_PRINTF("  bRequest = 0x%0x\n", setup[1]);
+-02984                 DWC_PRINTF("  wValue = 0x%0x\n", *((uint16_t *) & setup[2]));
+-02985                 DWC_PRINTF("  wIndex = 0x%0x\n", *((uint16_t *) & setup[4]));
+-02986                 DWC_PRINTF("  wLength = 0x%0x\n\n", *((uint16_t *) & setup[6]));
+-02987         }
+-02988 }
+-02989 #endif
+-02990 
+-02991 void dwc_otg_hcd_dump_frrem(dwc_otg_hcd_t * hcd)
+-02992 {
+-02993 #if 0
+-02994         DWC_PRINTF("Frame remaining at SOF:\n");
+-02995         DWC_PRINTF("  samples %u, accum %llu, avg %llu\n",
+-02996                    hcd->frrem_samples, hcd->frrem_accum,
+-02997                    (hcd->frrem_samples > 0) ?
+-02998                    hcd->frrem_accum / hcd->frrem_samples : 0);
+-02999 
+-03000         DWC_PRINTF("\n");
+-03001         DWC_PRINTF("Frame remaining at start_transfer (uframe 7):\n");
+-03002         DWC_PRINTF("  samples %u, accum %llu, avg %llu\n",
+-03003                    hcd->core_if->hfnum_7_samples,
+-03004                    hcd->core_if->hfnum_7_frrem_accum,
+-03005                    (hcd->core_if->hfnum_7_samples >
+-03006                     0) ? hcd->core_if->hfnum_7_frrem_accum /
+-03007                    hcd->core_if->hfnum_7_samples : 0);
+-03008         DWC_PRINTF("Frame remaining at start_transfer (uframe 0):\n");
+-03009         DWC_PRINTF("  samples %u, accum %llu, avg %llu\n",
+-03010                    hcd->core_if->hfnum_0_samples,
+-03011                    hcd->core_if->hfnum_0_frrem_accum,
+-03012                    (hcd->core_if->hfnum_0_samples >
+-03013                     0) ? hcd->core_if->hfnum_0_frrem_accum /
+-03014                    hcd->core_if->hfnum_0_samples : 0);
+-03015         DWC_PRINTF("Frame remaining at start_transfer (uframe 1-6):\n");
+-03016         DWC_PRINTF("  samples %u, accum %llu, avg %llu\n",
+-03017                    hcd->core_if->hfnum_other_samples,
+-03018                    hcd->core_if->hfnum_other_frrem_accum,
+-03019                    (hcd->core_if->hfnum_other_samples >
+-03020                     0) ? hcd->core_if->hfnum_other_frrem_accum /
+-03021                    hcd->core_if->hfnum_other_samples : 0);
+-03022 
+-03023         DWC_PRINTF("\n");
+-03024         DWC_PRINTF("Frame remaining at sample point A (uframe 7):\n");
+-03025         DWC_PRINTF("  samples %u, accum %llu, avg %llu\n",
+-03026                    hcd->hfnum_7_samples_a, hcd->hfnum_7_frrem_accum_a,
+-03027                    (hcd->hfnum_7_samples_a > 0) ?
+-03028                    hcd->hfnum_7_frrem_accum_a / hcd->hfnum_7_samples_a : 0);
+-03029         DWC_PRINTF("Frame remaining at sample point A (uframe 0):\n");
+-03030         DWC_PRINTF("  samples %u, accum %llu, avg %llu\n",
+-03031                    hcd->hfnum_0_samples_a, hcd->hfnum_0_frrem_accum_a,
+-03032                    (hcd->hfnum_0_samples_a > 0) ?
+-03033                    hcd->hfnum_0_frrem_accum_a / hcd->hfnum_0_samples_a : 0);
+-03034         DWC_PRINTF("Frame remaining at sample point A (uframe 1-6):\n");
+-03035         DWC_PRINTF("  samples %u, accum %llu, avg %llu\n",
+-03036                    hcd->hfnum_other_samples_a, hcd->hfnum_other_frrem_accum_a,
+-03037                    (hcd->hfnum_other_samples_a > 0) ?
+-03038                    hcd->hfnum_other_frrem_accum_a /
+-03039                    hcd->hfnum_other_samples_a : 0);
+-03040 
+-03041         DWC_PRINTF("\n");
+-03042         DWC_PRINTF("Frame remaining at sample point B (uframe 7):\n");
+-03043         DWC_PRINTF("  samples %u, accum %llu, avg %llu\n",
+-03044                    hcd->hfnum_7_samples_b, hcd->hfnum_7_frrem_accum_b,
+-03045                    (hcd->hfnum_7_samples_b > 0) ?
+-03046                    hcd->hfnum_7_frrem_accum_b / hcd->hfnum_7_samples_b : 0);
+-03047         DWC_PRINTF("Frame remaining at sample point B (uframe 0):\n");
+-03048         DWC_PRINTF("  samples %u, accum %llu, avg %llu\n",
+-03049                    hcd->hfnum_0_samples_b, hcd->hfnum_0_frrem_accum_b,
+-03050                    (hcd->hfnum_0_samples_b > 0) ?
+-03051                    hcd->hfnum_0_frrem_accum_b / hcd->hfnum_0_samples_b : 0);
+-03052         DWC_PRINTF("Frame remaining at sample point B (uframe 1-6):\n");
+-03053         DWC_PRINTF("  samples %u, accum %llu, avg %llu\n",
+-03054                    hcd->hfnum_other_samples_b, hcd->hfnum_other_frrem_accum_b,
+-03055                    (hcd->hfnum_other_samples_b > 0) ?
+-03056                    hcd->hfnum_other_frrem_accum_b /
+-03057                    hcd->hfnum_other_samples_b : 0);
+-03058 #endif
+-03059 }
+-03060 
+-03061 #endif                          /* DWC_DEVICE_ONLY */
+-
    Generated on Tue May 5 02:22:48 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++
    Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
    ++

    dwc_otg_hcd.c

    Go to the documentation of this file.
    00001 /* ==========================================================================
++00002  * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd.c $
++00003  * $Revision: #104 $
++00004  * $Date: 2011/10/24 $
++00005  * $Change: 1871159 $
++00006  *
++00007  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
++00008  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
++00009  * otherwise expressly agreed to in writing between Synopsys and you.
++00010  *
++00011  * The Software IS NOT an item of Licensed Software or Licensed Product under
++00012  * any End User Software License Agreement or Agreement for Licensed Product
++00013  * with Synopsys or any supplement thereto. You are permitted to use and
++00014  * redistribute this Software in source and binary forms, with or without
++00015  * modification, provided that redistributions of source code must retain this
++00016  * notice. You may not view, use, disclose, copy or distribute this file or
++00017  * any information contained herein except pursuant to this license grant from
++00018  * Synopsys. If you do not agree with this notice, including the disclaimer
++00019  * below, then you are not authorized to use the Software.
++00020  *
++00021  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
++00022  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++00023  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++00024  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
++00025  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++00026  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
++00027  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
++00028  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
++00029  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
++00030  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
++00031  * DAMAGE.
++00032  * ========================================================================== */
++00033 #ifndef DWC_DEVICE_ONLY
++00034 
++00042 #include "dwc_otg_hcd.h"
++00043 #include "dwc_otg_regs.h"
++00044 
++00045 dwc_otg_hcd_t *dwc_otg_hcd_alloc_hcd(void)
++00046 {
++00047         return DWC_ALLOC(sizeof(dwc_otg_hcd_t));
++00048 }
++00049 
++00054 void dwc_otg_hcd_connect_timeout(void *ptr)
++00055 {
++00056         DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, ptr);
++00057         DWC_PRINTF("Connect Timeout\n");
++00058         __DWC_ERROR("Device Not Connected/Responding\n");
++00059 }
++00060 
++00061 #ifdef DEBUG
++00062 static void dump_channel_info(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
++00063 {
++00064         if (qh->channel != NULL) {
++00065                 dwc_hc_t *hc = qh->channel;
++00066                 dwc_list_link_t *item;
++00067                 dwc_otg_qh_t *qh_item;
++00068                 int num_channels = hcd->core_if->core_params->host_channels;
++00069                 int i;
++00070 
++00071                 dwc_otg_hc_regs_t *hc_regs;
++00072                 hcchar_data_t hcchar;
++00073                 hcsplt_data_t hcsplt;
++00074                 hctsiz_data_t hctsiz;
++00075                 uint32_t hcdma;
++00076 
++00077                 hc_regs = hcd->core_if->host_if->hc_regs[hc->hc_num];
++00078                 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
++00079                 hcsplt.d32 = DWC_READ_REG32(&hc_regs->hcsplt);
++00080                 hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
++00081                 hcdma = DWC_READ_REG32(&hc_regs->hcdma);
++00082 
++00083                 DWC_PRINTF("  Assigned to channel %p:\n", hc);
++00084                 DWC_PRINTF("    hcchar 0x%08x, hcsplt 0x%08x\n", hcchar.d32,
++00085                            hcsplt.d32);
++00086                 DWC_PRINTF("    hctsiz 0x%08x, hcdma 0x%08x\n", hctsiz.d32,
++00087                            hcdma);
++00088                 DWC_PRINTF("    dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
++00089                            hc->dev_addr, hc->ep_num, hc->ep_is_in);
++00090                 DWC_PRINTF("    ep_type: %d\n", hc->ep_type);
++00091                 DWC_PRINTF("    max_packet: %d\n", hc->max_packet);
++00092                 DWC_PRINTF("    data_pid_start: %d\n", hc->data_pid_start);
++00093                 DWC_PRINTF("    xfer_started: %d\n", hc->xfer_started);
++00094                 DWC_PRINTF("    halt_status: %d\n", hc->halt_status);
++00095                 DWC_PRINTF("    xfer_buff: %p\n", hc->xfer_buff);
++00096                 DWC_PRINTF("    xfer_len: %d\n", hc->xfer_len);
++00097                 DWC_PRINTF("    qh: %p\n", hc->qh);
++00098                 DWC_PRINTF("  NP inactive sched:\n");
++00099                 DWC_LIST_FOREACH(item, &hcd->non_periodic_sched_inactive) {
++00100                         qh_item =
++00101                             DWC_LIST_ENTRY(item, dwc_otg_qh_t, qh_list_entry);
++00102                         DWC_PRINTF("    %p\n", qh_item);
++00103                 }
++00104                 DWC_PRINTF("  NP active sched:\n");
++00105                 DWC_LIST_FOREACH(item, &hcd->non_periodic_sched_active) {
++00106                         qh_item =
++00107                             DWC_LIST_ENTRY(item, dwc_otg_qh_t, qh_list_entry);
++00108                         DWC_PRINTF("    %p\n", qh_item);
++00109                 }
++00110                 DWC_PRINTF("  Channels: \n");
++00111                 for (i = 0; i < num_channels; i++) {
++00112                         dwc_hc_t *hc = hcd->hc_ptr_array[i];
++00113                         DWC_PRINTF("    %2d: %p\n", i, hc);
++00114                 }
++00115         }
++00116 }
++00117 #endif /* DEBUG */
++00118 
++00123 static void hcd_start_func(void *_vp)
++00124 {
++00125         dwc_otg_hcd_t *hcd = (dwc_otg_hcd_t *) _vp;
++00126 
++00127         DWC_DEBUGPL(DBG_HCDV, "%s() %p\n", __func__, hcd);
++00128         if (hcd) {
++00129                 hcd->fops->start(hcd);
++00130         }
++00131 }
++00132 
++00133 static void del_xfer_timers(dwc_otg_hcd_t * hcd)
++00134 {
++00135 #ifdef DEBUG
++00136         int i;
++00137         int num_channels = hcd->core_if->core_params->host_channels;
++00138         for (i = 0; i < num_channels; i++) {
++00139                 DWC_TIMER_CANCEL(hcd->core_if->hc_xfer_timer[i]);
++00140         }
++00141 #endif
++00142 }
++00143 
++00144 static void del_timers(dwc_otg_hcd_t * hcd)
++00145 {
++00146         del_xfer_timers(hcd);
++00147         DWC_TIMER_CANCEL(hcd->conn_timer);
++00148 }
++00149 
++00154 static void kill_urbs_in_qh_list(dwc_otg_hcd_t * hcd, dwc_list_link_t * qh_list)
++00155 {
++00156         dwc_list_link_t *qh_item;
++00157         dwc_otg_qh_t *qh;
++00158         dwc_otg_qtd_t *qtd, *qtd_tmp;
++00159 
++00160         DWC_LIST_FOREACH(qh_item, qh_list) {
++00161                 qh = DWC_LIST_ENTRY(qh_item, dwc_otg_qh_t, qh_list_entry);
++00162                 DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp,
++00163                                          &qh->qtd_list, qtd_list_entry) {
++00164                         qtd = DWC_CIRCLEQ_FIRST(&qh->qtd_list);
++00165                         if (qtd->urb != NULL) {
++00166                                 hcd->fops->complete(hcd, qtd->urb->priv,
++00167                                                     qtd->urb, -DWC_E_TIMEOUT);
++00168                                 dwc_otg_hcd_qtd_remove_and_free(hcd, qtd, qh);
++00169                         }
++00170 
++00171                 }
++00172         }
++00173 }
++00174 
++00181 static void kill_all_urbs(dwc_otg_hcd_t * hcd)
++00182 {
++00183         kill_urbs_in_qh_list(hcd, &hcd->non_periodic_sched_inactive);
++00184         kill_urbs_in_qh_list(hcd, &hcd->non_periodic_sched_active);
++00185         kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_inactive);
++00186         kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_ready);
++00187         kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_assigned);
++00188         kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_queued);
++00189 }
++00190 
++00197 static void dwc_otg_hcd_start_connect_timer(dwc_otg_hcd_t * hcd)
++00198 {
++00199         DWC_TIMER_SCHEDULE(hcd->conn_timer, 10000 /* 10 secs */ );
++00200 }
++00201 
++00207 static int32_t dwc_otg_hcd_session_start_cb(void *p)
++00208 {
++00209         dwc_otg_hcd_t *dwc_otg_hcd;
++00210         DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, p);
++00211         dwc_otg_hcd = p;
++00212         dwc_otg_hcd_start_connect_timer(dwc_otg_hcd);
++00213         return 1;
++00214 }
++00215 
++00222 static int32_t dwc_otg_hcd_start_cb(void *p)
++00223 {
++00224         dwc_otg_hcd_t *dwc_otg_hcd = p;
++00225         dwc_otg_core_if_t *core_if;
++00226         hprt0_data_t hprt0;
++00227 
++00228         core_if = dwc_otg_hcd->core_if;
++00229 
++00230         if (core_if->op_state == B_HOST) {
++00231                 /*
++00232                  * Reset the port.  During a HNP mode switch the reset
++00233                  * needs to occur within 1ms and have a duration of at
++00234                  * least 50ms.
++00235                  */
++00236                 hprt0.d32 = dwc_otg_read_hprt0(core_if);
++00237                 hprt0.b.prtrst = 1;
++00238                 DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
++00239         }
++00240         DWC_WORKQ_SCHEDULE_DELAYED(core_if->wq_otg,
++00241                                    hcd_start_func, dwc_otg_hcd, 50,
++00242                                    "start hcd");
++00243 
++00244         return 1;
++00245 }
++00246 
++00252 static int32_t dwc_otg_hcd_disconnect_cb(void *p)
++00253 {
++00254         gintsts_data_t intr;
++00255         dwc_otg_hcd_t *dwc_otg_hcd = p;
++00256 
++00257         /*
++00258          * Set status flags for the hub driver.
++00259          */
++00260         dwc_otg_hcd->flags.b.port_connect_status_change = 1;
++00261         dwc_otg_hcd->flags.b.port_connect_status = 0;
++00262 
++00263         /*
++00264          * Shutdown any transfers in process by clearing the Tx FIFO Empty
++00265          * interrupt mask and status bits and disabling subsequent host
++00266          * channel interrupts.
++00267          */
++00268         intr.d32 = 0;
++00269         intr.b.nptxfempty = 1;
++00270         intr.b.ptxfempty = 1;
++00271         intr.b.hcintr = 1;
++00272         DWC_MODIFY_REG32(&dwc_otg_hcd->core_if->core_global_regs->gintmsk,
++00273                          intr.d32, 0);
++00274         DWC_MODIFY_REG32(&dwc_otg_hcd->core_if->core_global_regs->gintsts,
++00275                          intr.d32, 0);
++00276 
++00277         del_timers(dwc_otg_hcd);
++00278 
++00279         /*
++00280          * Turn off the vbus power only if the core has transitioned to device
++00281          * mode. If still in host mode, need to keep power on to detect a
++00282          * reconnection.
++00283          */
++00284         if (dwc_otg_is_device_mode(dwc_otg_hcd->core_if)) {
++00285                 if (dwc_otg_hcd->core_if->op_state != A_SUSPEND) {
++00286                         hprt0_data_t hprt0 = {.d32 = 0 };
++00287                         DWC_PRINTF("Disconnect: PortPower off\n");
++00288                         hprt0.b.prtpwr = 0;
++00289                         DWC_WRITE_REG32(dwc_otg_hcd->core_if->host_if->hprt0,
++00290                                         hprt0.d32);
++00291                 }
++00292 
++00293                 dwc_otg_disable_host_interrupts(dwc_otg_hcd->core_if);
++00294         }
++00295 
++00296         /* Respond with an error status to all URBs in the schedule. */
++00297         kill_all_urbs(dwc_otg_hcd);
++00298 
++00299         if (dwc_otg_is_host_mode(dwc_otg_hcd->core_if)) {
++00300                 /* Clean up any host channels that were in use. */
++00301                 int num_channels;
++00302                 int i;
++00303                 dwc_hc_t *channel;
++00304                 dwc_otg_hc_regs_t *hc_regs;
++00305                 hcchar_data_t hcchar;
++00306 
++00307                 num_channels = dwc_otg_hcd->core_if->core_params->host_channels;
++00308 
++00309                 if (!dwc_otg_hcd->core_if->dma_enable) {
++00310                         /* Flush out any channel requests in slave mode. */
++00311                         for (i = 0; i < num_channels; i++) {
++00312                                 channel = dwc_otg_hcd->hc_ptr_array[i];
++00313                                 if (DWC_CIRCLEQ_EMPTY_ENTRY
++00314                                     (channel, hc_list_entry)) {
++00315                                         hc_regs =
++00316                                             dwc_otg_hcd->core_if->
++00317                                             host_if->hc_regs[i];
++00318                                         hcchar.d32 =
++00319                                             DWC_READ_REG32(&hc_regs->hcchar);
++00320                                         if (hcchar.b.chen) {
++00321                                                 hcchar.b.chen = 0;
++00322                                                 hcchar.b.chdis = 1;
++00323                                                 hcchar.b.epdir = 0;
++00324                                                 DWC_WRITE_REG32
++00325                                                     (&hc_regs->hcchar,
++00326                                                      hcchar.d32);
++00327                                         }
++00328                                 }
++00329                         }
++00330                 }
++00331 
++00332                 for (i = 0; i < num_channels; i++) {
++00333                         channel = dwc_otg_hcd->hc_ptr_array[i];
++00334                         if (DWC_CIRCLEQ_EMPTY_ENTRY(channel, hc_list_entry)) {
++00335                                 hc_regs =
++00336                                     dwc_otg_hcd->core_if->host_if->hc_regs[i];
++00337                                 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
++00338                                 if (hcchar.b.chen) {
++00339                                         /* Halt the channel. */
++00340                                         hcchar.b.chdis = 1;
++00341                                         DWC_WRITE_REG32(&hc_regs->hcchar,
++00342                                                         hcchar.d32);
++00343                                 }
++00344 
++00345                                 dwc_otg_hc_cleanup(dwc_otg_hcd->core_if,
++00346                                                    channel);
++00347                                 DWC_CIRCLEQ_INSERT_TAIL
++00348                                     (&dwc_otg_hcd->free_hc_list, channel,
++00349                                      hc_list_entry);
++00350                                 /*
++00351                                  * Added for Descriptor DMA to prevent channel double cleanup
++00352                                  * in release_channel_ddma(). Which called from ep_disable
++00353                                  * when device disconnect.
++00354                                  */
++00355                                 channel->qh = NULL;
++00356                         }
++00357                 }
++00358         }
++00359 
++00360         if (dwc_otg_hcd->fops->disconnect) {
++00361                 dwc_otg_hcd->fops->disconnect(dwc_otg_hcd);
++00362         }
++00363 
++00364         return 1;
++00365 }
++00366 
++00372 static int32_t dwc_otg_hcd_stop_cb(void *p)
++00373 {
++00374         dwc_otg_hcd_t *dwc_otg_hcd = p;
++00375 
++00376         DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, p);
++00377         dwc_otg_hcd_stop(dwc_otg_hcd);
++00378         return 1;
++00379 }
++00380 
++00381 #ifdef CONFIG_USB_DWC_OTG_LPM
++00382 
++00387 static int dwc_otg_hcd_sleep_cb(void *p)
++00388 {
++00389         dwc_otg_hcd_t *hcd = p;
++00390 
++00391         dwc_otg_hcd_free_hc_from_lpm(hcd);
++00392 
++00393         return 0;
++00394 }
++00395 #endif
++00396 
++00402 static int dwc_otg_hcd_rem_wakeup_cb(void *p)
++00403 {
++00404         dwc_otg_hcd_t *hcd = p;
++00405 
++00406         if (hcd->core_if->lx_state == DWC_OTG_L2) {
++00407                 hcd->flags.b.port_suspend_change = 1;
++00408         }
++00409 #ifdef CONFIG_USB_DWC_OTG_LPM
++00410         else {
++00411                 hcd->flags.b.port_l1_change = 1;
++00412         }
++00413 #endif
++00414         return 0;
++00415 }
++00416 
++00421 void dwc_otg_hcd_stop(dwc_otg_hcd_t * hcd)
++00422 {
++00423         hprt0_data_t hprt0 = {.d32 = 0 };
++00424 
++00425         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD STOP\n");
++00426 
++00427         /*
++00428          * The root hub should be disconnected before this function is called.
++00429          * The disconnect will clear the QTD lists (via ..._hcd_urb_dequeue)
++00430          * and the QH lists (via ..._hcd_endpoint_disable).
++00431          */
++00432 
++00433         /* Turn off all host-specific interrupts. */
++00434         dwc_otg_disable_host_interrupts(hcd->core_if);
++00435 
++00436         /* Turn off the vbus power */
++00437         DWC_PRINTF("PortPower off\n");
++00438         hprt0.b.prtpwr = 0;
++00439         DWC_WRITE_REG32(hcd->core_if->host_if->hprt0, hprt0.d32);
++00440         dwc_mdelay(1);
++00441 }
++00442 
++00443 int dwc_otg_hcd_urb_enqueue(dwc_otg_hcd_t * hcd,
++00444                             dwc_otg_hcd_urb_t * dwc_otg_urb, void **ep_handle,
++00445                             int atomic_alloc)
++00446 {
++00447         dwc_irqflags_t flags;
++00448         int retval = 0;
++00449         dwc_otg_qtd_t *qtd;
++00450         gintmsk_data_t intr_mask = {.d32 = 0 };
++00451 
++00452         if (!hcd->flags.b.port_connect_status) {
++00453                 /* No longer connected. */
++00454                 DWC_ERROR("Not connected\n");
++00455                 return -DWC_E_NO_DEVICE;
++00456         }
++00457 
++00458         qtd = dwc_otg_hcd_qtd_create(dwc_otg_urb, atomic_alloc);
++00459         if (qtd == NULL) {
++00460                 DWC_ERROR("DWC OTG HCD URB Enqueue failed creating QTD\n");
++00461                 return -DWC_E_NO_MEMORY;
++00462         }
++00463 
++00464         retval =
++00465             dwc_otg_hcd_qtd_add(qtd, hcd, (dwc_otg_qh_t **) ep_handle, atomic_alloc);
++00466         if (retval < 0) {
++00467                 DWC_ERROR("DWC OTG HCD URB Enqueue failed adding QTD. "
++00468                           "Error status %d\n", retval);
++00469                 dwc_otg_hcd_qtd_free(qtd);
++00470         } else {
++00471                 qtd->qh = *ep_handle;
++00472         }
++00473         intr_mask.d32 = DWC_READ_REG32(&hcd->core_if->core_global_regs->gintmsk);
++00474         if (!intr_mask.b.sofintr && retval == 0) {
++00475                 dwc_otg_transaction_type_e tr_type;
++00476                 if ((qtd->qh->ep_type == UE_BULK)
++00477                     && !(qtd->urb->flags & URB_GIVEBACK_ASAP)) {
++00478                         /* Do not schedule SG transactions until qtd has URB_GIVEBACK_ASAP set */
++00479                         return 0;
++00480                 }
++00481                 DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
++00482                 tr_type = dwc_otg_hcd_select_transactions(hcd);
++00483                 if (tr_type != DWC_OTG_TRANSACTION_NONE) {
++00484                         dwc_otg_hcd_queue_transactions(hcd, tr_type);
++00485                 }
++00486                 DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
++00487         }
++00488 
++00489         return retval;
++00490 }
++00491 
++00492 int dwc_otg_hcd_urb_dequeue(dwc_otg_hcd_t * hcd,
++00493                             dwc_otg_hcd_urb_t * dwc_otg_urb)
++00494 {
++00495         dwc_otg_qh_t *qh;
++00496         dwc_otg_qtd_t *urb_qtd;
++00497 
++00498         urb_qtd = dwc_otg_urb->qtd;
++00499         qh = urb_qtd->qh;
++00500 #ifdef DEBUG
++00501         if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
++00502                 if (urb_qtd->in_process) {
++00503                         dump_channel_info(hcd, qh);
++00504                 }
++00505         }
++00506 #endif
++00507         if (urb_qtd->in_process && qh->channel) {
++00508                 /* The QTD is in process (it has been assigned to a channel). */
++00509                 if (hcd->flags.b.port_connect_status) {
++00510                         /*
++00511                          * If still connected (i.e. in host mode), halt the
++00512                          * channel so it can be used for other transfers. If
++00513                          * no longer connected, the host registers can't be
++00514                          * written to halt the channel since the core is in
++00515                          * device mode.
++00516                          */
++00517                         dwc_otg_hc_halt(hcd->core_if, qh->channel,
++00518                                         DWC_OTG_HC_XFER_URB_DEQUEUE);
++00519                 }
++00520         }
++00521 
++00522         /*
++00523          * Free the QTD and clean up the associated QH. Leave the QH in the
++00524          * schedule if it has any remaining QTDs.
++00525          */
++00526 
++00527         if (!hcd->core_if->dma_desc_enable) {
++00528                 uint8_t b = urb_qtd->in_process;
++00529                 dwc_otg_hcd_qtd_remove_and_free(hcd, urb_qtd, qh);
++00530                 if (b) {
++00531                         dwc_otg_hcd_qh_deactivate(hcd, qh, 0);
++00532                         qh->channel = NULL;
++00533                 } else if (DWC_CIRCLEQ_EMPTY(&qh->qtd_list)) {
++00534                         dwc_otg_hcd_qh_remove(hcd, qh);
++00535                 }
++00536         } else {
++00537                 dwc_otg_hcd_qtd_remove_and_free(hcd, urb_qtd, qh);
++00538         }
++00539         return 0;
++00540 }
++00541 
++00542 int dwc_otg_hcd_endpoint_disable(dwc_otg_hcd_t * hcd, void *ep_handle,
++00543                                  int retry)
++00544 {
++00545         dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle;
++00546         int retval = 0;
++00547         dwc_irqflags_t flags;
++00548 
++00549         if (retry < 0) {
++00550                 retval = -DWC_E_INVALID;
++00551                 goto done;
++00552         }
++00553 
++00554         if (!qh) {
++00555                 retval = -DWC_E_INVALID;
++00556                 goto done;
++00557         }
++00558 
++00559         DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
++00560 
++00561         while (!DWC_CIRCLEQ_EMPTY(&qh->qtd_list) && retry) {
++00562                 DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
++00563                 retry--;
++00564                 dwc_msleep(5);
++00565                 DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
++00566         }
++00567 
++00568         dwc_otg_hcd_qh_remove(hcd, qh);
++00569 
++00570         DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
++00571         /*
++00572          * Split dwc_otg_hcd_qh_remove_and_free() into qh_remove
++00573          * and qh_free to prevent stack dump on DWC_DMA_FREE() with
++00574          * irq_disabled (spinlock_irqsave) in dwc_otg_hcd_desc_list_free()
++00575          * and dwc_otg_hcd_frame_list_alloc().
++00576          */
++00577         dwc_otg_hcd_qh_free(hcd, qh);
++00578 
++00579 done:
++00580         return retval;
++00581 }
++00582 
++00583 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,30)
++00584 int dwc_otg_hcd_endpoint_reset(dwc_otg_hcd_t * hcd, void *ep_handle)
++00585 {
++00586         int retval = 0;
++00587         dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle;
++00588         if (!qh)
++00589                 return -DWC_E_INVALID;
++00590 
++00591         qh->data_toggle = DWC_OTG_HC_PID_DATA0;
++00592         return retval;
++00593 }
++00594 #endif
++00595 
++00599 static dwc_otg_cil_callbacks_t hcd_cil_callbacks = {
++00600         .start = dwc_otg_hcd_start_cb,
++00601         .stop = dwc_otg_hcd_stop_cb,
++00602         .disconnect = dwc_otg_hcd_disconnect_cb,
++00603         .session_start = dwc_otg_hcd_session_start_cb,
++00604         .resume_wakeup = dwc_otg_hcd_rem_wakeup_cb,
++00605 #ifdef CONFIG_USB_DWC_OTG_LPM
++00606         .sleep = dwc_otg_hcd_sleep_cb,
++00607 #endif
++00608         .p = 0,
++00609 };
++00610 
++00614 static void reset_tasklet_func(void *data)
++00615 {
++00616         dwc_otg_hcd_t *dwc_otg_hcd = (dwc_otg_hcd_t *) data;
++00617         dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;
++00618         hprt0_data_t hprt0;
++00619 
++00620         DWC_DEBUGPL(DBG_HCDV, "USB RESET tasklet called\n");
++00621 
++00622         hprt0.d32 = dwc_otg_read_hprt0(core_if);
++00623         hprt0.b.prtrst = 1;
++00624         DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
++00625         dwc_mdelay(60);
++00626 
++00627         hprt0.b.prtrst = 0;
++00628         DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
++00629         dwc_otg_hcd->flags.b.port_reset_change = 1;
++00630 }
++00631 
++00632 static void qh_list_free(dwc_otg_hcd_t * hcd, dwc_list_link_t * qh_list)
++00633 {
++00634         dwc_list_link_t *item;
++00635         dwc_otg_qh_t *qh;
++00636         dwc_irqflags_t flags;
++00637 
++00638         if (!qh_list->next) {
++00639                 /* The list hasn't been initialized yet. */
++00640                 return;
++00641         }
++00642         /*
++00643          * Hold spinlock here. Not needed in that case if bellow 
++00644          * function is being called from ISR 
++00645          */
++00646         DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
++00647         /* Ensure there are no QTDs or URBs left. */
++00648         kill_urbs_in_qh_list(hcd, qh_list);
++00649         DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
++00650 
++00651         DWC_LIST_FOREACH(item, qh_list) {
++00652                 qh = DWC_LIST_ENTRY(item, dwc_otg_qh_t, qh_list_entry);
++00653                 dwc_otg_hcd_qh_remove_and_free(hcd, qh);
++00654         }
++00655 }
++00656 
++00661 void dwc_otg_hcd_power_up(void *ptr)
++00662 {
++00663         gpwrdn_data_t gpwrdn = {.d32 = 0 };
++00664         dwc_otg_core_if_t *core_if = (dwc_otg_core_if_t *) ptr;
++00665 
++00666         DWC_PRINTF("%s called\n", __FUNCTION__);
++00667 
++00668         if (!core_if->hibernation_suspend) {
++00669                 DWC_PRINTF("Already exited from Hibernation\n");
++00670                 return;
++00671         }
++00672 
++00673         /* Switch on the voltage to the core */
++00674         gpwrdn.b.pwrdnswtch = 1;
++00675         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
++00676         dwc_udelay(10);
++00677 
++00678         /* Reset the core */
++00679         gpwrdn.d32 = 0;
++00680         gpwrdn.b.pwrdnrstn = 1;
++00681         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
++00682         dwc_udelay(10);
++00683 
++00684         /* Disable power clamps */
++00685         gpwrdn.d32 = 0;
++00686         gpwrdn.b.pwrdnclmp = 1;
++00687         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
++00688 
++00689         /* Remove reset the core signal */
++00690         gpwrdn.d32 = 0;
++00691         gpwrdn.b.pwrdnrstn = 1;
++00692         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
++00693         dwc_udelay(10);
++00694 
++00695         /* Disable PMU interrupt */
++00696         gpwrdn.d32 = 0;
++00697         gpwrdn.b.pmuintsel = 1;
++00698         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
++00699 
++00700         core_if->hibernation_suspend = 0;
++00701 
++00702         /* Disable PMU */
++00703         gpwrdn.d32 = 0;
++00704         gpwrdn.b.pmuactv = 1;
++00705         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
++00706         dwc_udelay(10);
++00707 
++00708         /* Enable VBUS */
++00709         gpwrdn.d32 = 0;
++00710         gpwrdn.b.dis_vbus = 1;
++00711         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
++00712 
++00713         core_if->op_state = A_HOST;
++00714         dwc_otg_core_init(core_if);
++00715         dwc_otg_enable_global_interrupts(core_if);
++00716         cil_hcd_start(core_if);
++00717 }
++00718 
++00723 static void dwc_otg_hcd_free(dwc_otg_hcd_t * dwc_otg_hcd)
++00724 {
++00725         int i;
++00726 
++00727         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD FREE\n");
++00728 
++00729         del_timers(dwc_otg_hcd);
++00730 
++00731         /* Free memory for QH/QTD lists */
++00732         qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->non_periodic_sched_inactive);
++00733         qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->non_periodic_sched_active);
++00734         qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_inactive);
++00735         qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_ready);
++00736         qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_assigned);
++00737         qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_queued);
++00738 
++00739         /* Free memory for the host channels. */
++00740         for (i = 0; i < MAX_EPS_CHANNELS; i++) {
++00741                 dwc_hc_t *hc = dwc_otg_hcd->hc_ptr_array[i];
++00742 
++00743 #ifdef DEBUG
++00744                 if (dwc_otg_hcd->core_if->hc_xfer_timer[i]) {
++00745                         DWC_TIMER_FREE(dwc_otg_hcd->core_if->hc_xfer_timer[i]);
++00746                 }
++00747 #endif
++00748                 if (hc != NULL) {
++00749                         DWC_DEBUGPL(DBG_HCDV, "HCD Free channel #%i, hc=%p\n",
++00750                                     i, hc);
++00751                         DWC_FREE(hc);
++00752                 }
++00753         }
++00754 
++00755         if (dwc_otg_hcd->core_if->dma_enable) {
++00756                 if (dwc_otg_hcd->status_buf_dma) {
++00757                         DWC_DMA_FREE(DWC_OTG_HCD_STATUS_BUF_SIZE,
++00758                                      dwc_otg_hcd->status_buf,
++00759                                      dwc_otg_hcd->status_buf_dma);
++00760                 }
++00761         } else if (dwc_otg_hcd->status_buf != NULL) {
++00762                 DWC_FREE(dwc_otg_hcd->status_buf);
++00763         }
++00764         DWC_SPINLOCK_FREE(dwc_otg_hcd->lock);
++00765         /* Set core_if's lock pointer to NULL */
++00766         dwc_otg_hcd->core_if->lock = NULL;
++00767 
++00768         DWC_TIMER_FREE(dwc_otg_hcd->conn_timer);
++00769         DWC_TASK_FREE(dwc_otg_hcd->reset_tasklet);
++00770 
++00771 #ifdef DWC_DEV_SRPCAP
++00772         if (dwc_otg_hcd->core_if->power_down == 2 &&
++00773             dwc_otg_hcd->core_if->pwron_timer) {
++00774                 DWC_TIMER_FREE(dwc_otg_hcd->core_if->pwron_timer);
++00775         }
++00776 #endif
++00777         DWC_FREE(dwc_otg_hcd);
++00778 }
++00779 
++00780 int dwc_otg_hcd_init(dwc_otg_hcd_t * hcd, dwc_otg_core_if_t * core_if)
++00781 {
++00782         int retval = 0;
++00783         int num_channels;
++00784         int i;
++00785         dwc_hc_t *channel;
++00786 
++00787         hcd->lock = DWC_SPINLOCK_ALLOC();
++00788         if (!hcd->lock) {
++00789                 DWC_ERROR("Could not allocate lock for pcd");
++00790                 DWC_FREE(hcd);
++00791                 retval = -DWC_E_NO_MEMORY;
++00792                 goto out;
++00793         }
++00794         hcd->core_if = core_if;
++00795 
++00796         /* Register the HCD CIL Callbacks */
++00797         dwc_otg_cil_register_hcd_callbacks(hcd->core_if,
++00798                                            &hcd_cil_callbacks, hcd);
++00799 
++00800         /* Initialize the non-periodic schedule. */
++00801         DWC_LIST_INIT(&hcd->non_periodic_sched_inactive);
++00802         DWC_LIST_INIT(&hcd->non_periodic_sched_active);
++00803 
++00804         /* Initialize the periodic schedule. */
++00805         DWC_LIST_INIT(&hcd->periodic_sched_inactive);
++00806         DWC_LIST_INIT(&hcd->periodic_sched_ready);
++00807         DWC_LIST_INIT(&hcd->periodic_sched_assigned);
++00808         DWC_LIST_INIT(&hcd->periodic_sched_queued);
++00809 
++00810         /*
++00811          * Create a host channel descriptor for each host channel implemented
++00812          * in the controller. Initialize the channel descriptor array.
++00813          */
++00814         DWC_CIRCLEQ_INIT(&hcd->free_hc_list);
++00815         num_channels = hcd->core_if->core_params->host_channels;
++00816         DWC_MEMSET(hcd->hc_ptr_array, 0, sizeof(hcd->hc_ptr_array));
++00817         for (i = 0; i < num_channels; i++) {
++00818                 channel = DWC_ALLOC(sizeof(dwc_hc_t));
++00819                 if (channel == NULL) {
++00820                         retval = -DWC_E_NO_MEMORY;
++00821                         DWC_ERROR("%s: host channel allocation failed\n",
++00822                                   __func__);
++00823                         dwc_otg_hcd_free(hcd);
++00824                         goto out;
++00825                 }
++00826                 channel->hc_num = i;
++00827                 hcd->hc_ptr_array[i] = channel;
++00828 #ifdef DEBUG
++00829                 hcd->core_if->hc_xfer_timer[i] =
++00830                     DWC_TIMER_ALLOC("hc timer", hc_xfer_timeout,
++00831                                     &hcd->core_if->hc_xfer_info[i]);
++00832 #endif
++00833                 DWC_DEBUGPL(DBG_HCDV, "HCD Added channel #%d, hc=%p\n", i,
++00834                             channel);
++00835         }
++00836 
++00837         /* Initialize the Connection timeout timer. */
++00838         hcd->conn_timer = DWC_TIMER_ALLOC("Connection timer",
++00839                                           dwc_otg_hcd_connect_timeout, 0);
++00840 
++00841         /* Initialize reset tasklet. */
++00842         hcd->reset_tasklet = DWC_TASK_ALLOC("reset_tasklet", reset_tasklet_func, hcd);
++00843 #ifdef DWC_DEV_SRPCAP
++00844         if (hcd->core_if->power_down == 2) {
++00845                 /* Initialize Power on timer for Host power up in case hibernation */
++00846                 hcd->core_if->pwron_timer = DWC_TIMER_ALLOC("PWRON TIMER",
++00847                                                                         dwc_otg_hcd_power_up, core_if);
++00848         }
++00849 #endif  
++00850 
++00851         /*
++00852          * Allocate space for storing data on status transactions. Normally no
++00853          * data is sent, but this space acts as a bit bucket. This must be
++00854          * done after usb_add_hcd since that function allocates the DMA buffer
++00855          * pool.
++00856          */
++00857         if (hcd->core_if->dma_enable) {
++00858                 hcd->status_buf =
++00859                     DWC_DMA_ALLOC(DWC_OTG_HCD_STATUS_BUF_SIZE,
++00860                                   &hcd->status_buf_dma);
++00861         } else {
++00862                 hcd->status_buf = DWC_ALLOC(DWC_OTG_HCD_STATUS_BUF_SIZE);
++00863         }
++00864         if (!hcd->status_buf) {
++00865                 retval = -DWC_E_NO_MEMORY;
++00866                 DWC_ERROR("%s: status_buf allocation failed\n", __func__);
++00867                 dwc_otg_hcd_free(hcd);
++00868                 goto out;
++00869         }
++00870 
++00871         hcd->otg_port = 1;
++00872         hcd->frame_list = NULL;
++00873         hcd->frame_list_dma = 0;
++00874         hcd->periodic_qh_count = 0;
++00875 out:
++00876         return retval;
++00877 }
++00878 
++00879 void dwc_otg_hcd_remove(dwc_otg_hcd_t * hcd)
++00880 {
++00881         /* Turn off all host-specific interrupts. */
++00882         dwc_otg_disable_host_interrupts(hcd->core_if);
++00883 
++00884         dwc_otg_hcd_free(hcd);
++00885 }
++00886 
++00890 static void dwc_otg_hcd_reinit(dwc_otg_hcd_t * hcd)
++00891 {
++00892         int num_channels;
++00893         int i;
++00894         dwc_hc_t *channel;
++00895         dwc_hc_t *channel_tmp;
++00896 
++00897         hcd->flags.d32 = 0;
++00898 
++00899         hcd->non_periodic_qh_ptr = &hcd->non_periodic_sched_active;
++00900         hcd->non_periodic_channels = 0;
++00901         hcd->periodic_channels = 0;
++00902 
++00903         /*
++00904          * Put all channels in the free channel list and clean up channel
++00905          * states.
++00906          */
++00907         DWC_CIRCLEQ_FOREACH_SAFE(channel, channel_tmp,
++00908                                  &hcd->free_hc_list, hc_list_entry) {
++00909                 DWC_CIRCLEQ_REMOVE(&hcd->free_hc_list, channel, hc_list_entry);
++00910         }
++00911 
++00912         num_channels = hcd->core_if->core_params->host_channels;
++00913         for (i = 0; i < num_channels; i++) {
++00914                 channel = hcd->hc_ptr_array[i];
++00915                 DWC_CIRCLEQ_INSERT_TAIL(&hcd->free_hc_list, channel,
++00916                                         hc_list_entry);
++00917                 dwc_otg_hc_cleanup(hcd->core_if, channel);
++00918         }
++00919 
++00920         /* Initialize the DWC core for host mode operation. */
++00921         dwc_otg_core_host_init(hcd->core_if);
++00922 
++00923         /* Set core_if's lock pointer to the hcd->lock */
++00924         hcd->core_if->lock = hcd->lock;
++00925 }
++00926 
++00936 static void assign_and_init_hc(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
++00937 {
++00938         dwc_hc_t *hc;
++00939         dwc_otg_qtd_t *qtd;
++00940         dwc_otg_hcd_urb_t *urb;
++00941         void* ptr = NULL;
++00942 
++00943         DWC_DEBUGPL(DBG_HCDV, "%s(%p,%p)\n", __func__, hcd, qh);
++00944 
++00945         hc = DWC_CIRCLEQ_FIRST(&hcd->free_hc_list);
++00946 
++00947         /* Remove the host channel from the free list. */
++00948         DWC_CIRCLEQ_REMOVE_INIT(&hcd->free_hc_list, hc, hc_list_entry);
++00949 
++00950         qtd = DWC_CIRCLEQ_FIRST(&qh->qtd_list);
++00951 
++00952         urb = qtd->urb;
++00953         qh->channel = hc;
++00954 
++00955         qtd->in_process = 1;
++00956 
++00957         /*
++00958          * Use usb_pipedevice to determine device address. This address is
++00959          * 0 before the SET_ADDRESS command and the correct address afterward.
++00960          */
++00961         hc->dev_addr = dwc_otg_hcd_get_dev_addr(&urb->pipe_info);
++00962         hc->ep_num = dwc_otg_hcd_get_ep_num(&urb->pipe_info);
++00963         hc->speed = qh->dev_speed;
++00964         hc->max_packet = dwc_max_packet(qh->maxp);
++00965 
++00966         hc->xfer_started = 0;
++00967         hc->halt_status = DWC_OTG_HC_XFER_NO_HALT_STATUS;
++00968         hc->error_state = (qtd->error_count > 0);
++00969         hc->halt_on_queue = 0;
++00970         hc->halt_pending = 0;
++00971         hc->requests = 0;
++00972 
++00973         /*
++00974          * The following values may be modified in the transfer type section
++00975          * below. The xfer_len value may be reduced when the transfer is
++00976          * started to accommodate the max widths of the XferSize and PktCnt
++00977          * fields in the HCTSIZn register.
++00978          */
++00979 
++00980         hc->ep_is_in = (dwc_otg_hcd_is_pipe_in(&urb->pipe_info) != 0);
++00981         if (hc->ep_is_in) {
++00982                 hc->do_ping = 0;
++00983         } else {
++00984                 hc->do_ping = qh->ping_state;
++00985         }
++00986 
++00987         hc->data_pid_start = qh->data_toggle;
++00988         hc->multi_count = 1;
++00989 
++00990         if (hcd->core_if->dma_enable) {
++00991                 hc->xfer_buff = (uint8_t *) urb->dma + urb->actual_length;
++00992 
++00993                 /* For non-dword aligned case */
++00994                 if (((unsigned long)hc->xfer_buff & 0x3)
++00995                     && !hcd->core_if->dma_desc_enable) {
++00996                         ptr = (uint8_t *) urb->buf + urb->actual_length;
++00997                 }
++00998         } else {
++00999                 hc->xfer_buff = (uint8_t *) urb->buf + urb->actual_length;
++01000         }
++01001         hc->xfer_len = urb->length - urb->actual_length;
++01002         hc->xfer_count = 0;
++01003 
++01004         /*
++01005          * Set the split attributes
++01006          */
++01007         hc->do_split = 0;
++01008         if (qh->do_split) {
++01009                 uint32_t hub_addr, port_addr;
++01010                 hc->do_split = 1;
++01011                 hc->xact_pos = qtd->isoc_split_pos;
++01012                 hc->complete_split = qtd->complete_split;
++01013                 hcd->fops->hub_info(hcd, urb->priv, &hub_addr, &port_addr);
++01014                 hc->hub_addr = (uint8_t) hub_addr;
++01015                 hc->port_addr = (uint8_t) port_addr;
++01016         }
++01017 
++01018         switch (dwc_otg_hcd_get_pipe_type(&urb->pipe_info)) {
++01019         case UE_CONTROL:
++01020                 hc->ep_type = DWC_OTG_EP_TYPE_CONTROL;
++01021                 switch (qtd->control_phase) {
++01022                 case DWC_OTG_CONTROL_SETUP:
++01023                         DWC_DEBUGPL(DBG_HCDV, "  Control setup transaction\n");
++01024                         hc->do_ping = 0;
++01025                         hc->ep_is_in = 0;
++01026                         hc->data_pid_start = DWC_OTG_HC_PID_SETUP;
++01027                         if (hcd->core_if->dma_enable) {
++01028                                 hc->xfer_buff = (uint8_t *) urb->setup_dma;
++01029                         } else {
++01030                                 hc->xfer_buff = (uint8_t *) urb->setup_packet;
++01031                         }
++01032                         hc->xfer_len = 8;
++01033                         ptr = NULL;
++01034                         break;
++01035                 case DWC_OTG_CONTROL_DATA:
++01036                         DWC_DEBUGPL(DBG_HCDV, "  Control data transaction\n");
++01037                         hc->data_pid_start = qtd->data_toggle;
++01038                         break;
++01039                 case DWC_OTG_CONTROL_STATUS:
++01040                         /*
++01041                          * Direction is opposite of data direction or IN if no
++01042                          * data.
++01043                          */
++01044                         DWC_DEBUGPL(DBG_HCDV, "  Control status transaction\n");
++01045                         if (urb->length == 0) {
++01046                                 hc->ep_is_in = 1;
++01047                         } else {
++01048                                 hc->ep_is_in =
++01049                                     dwc_otg_hcd_is_pipe_out(&urb->pipe_info);
++01050                         }
++01051                         if (hc->ep_is_in) {
++01052                                 hc->do_ping = 0;
++01053                         }
++01054 
++01055                         hc->data_pid_start = DWC_OTG_HC_PID_DATA1;
++01056 
++01057                         hc->xfer_len = 0;
++01058                         if (hcd->core_if->dma_enable) {
++01059                                 hc->xfer_buff = (uint8_t *) hcd->status_buf_dma;
++01060                         } else {
++01061                                 hc->xfer_buff = (uint8_t *) hcd->status_buf;
++01062                         }
++01063                         ptr = NULL;
++01064                         break;
++01065                 }
++01066                 break;
++01067         case UE_BULK:
++01068                 hc->ep_type = DWC_OTG_EP_TYPE_BULK;
++01069                 break;
++01070         case UE_INTERRUPT:
++01071                 hc->ep_type = DWC_OTG_EP_TYPE_INTR;
++01072                 break;
++01073         case UE_ISOCHRONOUS:
++01074                 {
++01075                         struct dwc_otg_hcd_iso_packet_desc *frame_desc;
++01076 
++01077                         hc->ep_type = DWC_OTG_EP_TYPE_ISOC;
++01078 
++01079                         if (hcd->core_if->dma_desc_enable)
++01080                                 break;
++01081 
++01082                         frame_desc = &urb->iso_descs[qtd->isoc_frame_index];
++01083 
++01084                         frame_desc->status = 0;
++01085 
++01086                         if (hcd->core_if->dma_enable) {
++01087                                 hc->xfer_buff = (uint8_t *) urb->dma;
++01088                         } else {
++01089                                 hc->xfer_buff = (uint8_t *) urb->buf;
++01090                         }
++01091                         hc->xfer_buff +=
++01092                             frame_desc->offset + qtd->isoc_split_offset;
++01093                         hc->xfer_len =
++01094                             frame_desc->length - qtd->isoc_split_offset;
++01095 
++01096                         /* For non-dword aligned buffers */
++01097                         if (((unsigned long)hc->xfer_buff & 0x3)
++01098                             && hcd->core_if->dma_enable) {
++01099                                 ptr =
++01100                                     (uint8_t *) urb->buf + frame_desc->offset +
++01101                                     qtd->isoc_split_offset;
++01102                         } else
++01103                                 ptr = NULL;
++01104 
++01105                         if (hc->xact_pos == DWC_HCSPLIT_XACTPOS_ALL) {
++01106                                 if (hc->xfer_len <= 188) {
++01107                                         hc->xact_pos = DWC_HCSPLIT_XACTPOS_ALL;
++01108                                 } else {
++01109                                         hc->xact_pos =
++01110                                             DWC_HCSPLIT_XACTPOS_BEGIN;
++01111                                 }
++01112                         }
++01113                 }
++01114                 break;
++01115         }
++01116         /* non DWORD-aligned buffer case */     
++01117         if (ptr) {
++01118                 uint32_t buf_size;
++01119                 if (hc->ep_type != DWC_OTG_EP_TYPE_ISOC) {
++01120                         buf_size = hcd->core_if->core_params->max_transfer_size;
++01121                 } else {                                
++01122                         buf_size = 4096;
++01123                 }
++01124                 if (!qh->dw_align_buf) {
++01125                         qh->dw_align_buf = DWC_DMA_ALLOC_ATOMIC(buf_size,
++01126                                                          &qh->dw_align_buf_dma);
++01127                         if (!qh->dw_align_buf) {
++01128                                 DWC_ERROR
++01129                                     ("%s: Failed to allocate memory to handle "
++01130                                      "non-dword aligned buffer case\n",
++01131                                      __func__);
++01132                                 return;
++01133                         }
++01134                 }
++01135                 if (!hc->ep_is_in) {
++01136                         dwc_memcpy(qh->dw_align_buf, ptr, hc->xfer_len);
++01137                 }
++01138                 hc->align_buff = qh->dw_align_buf_dma;
++01139         } else {
++01140                 hc->align_buff = 0;
++01141         }
++01142 
++01143         if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
++01144             hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
++01145                 /*
++01146                  * This value may be modified when the transfer is started to
++01147                  * reflect the actual transfer length.
++01148                  */
++01149                 hc->multi_count = dwc_hb_mult(qh->maxp);
++01150         }
++01151 
++01152         if (hcd->core_if->dma_desc_enable)
++01153                 hc->desc_list_addr = qh->desc_list_dma;
++01154 
++01155         dwc_otg_hc_init(hcd->core_if, hc);
++01156         hc->qh = qh;
++01157 }
++01158 
++01168 dwc_otg_transaction_type_e dwc_otg_hcd_select_transactions(dwc_otg_hcd_t * hcd)
++01169 {
++01170         dwc_list_link_t *qh_ptr;
++01171         dwc_otg_qh_t *qh;
++01172         int num_channels;
++01173         dwc_otg_transaction_type_e ret_val = DWC_OTG_TRANSACTION_NONE;
++01174 
++01175 #ifdef DEBUG_SOF
++01176         DWC_DEBUGPL(DBG_HCD, "  Select Transactions\n");
++01177 #endif
++01178 
++01179         /* Process entries in the periodic ready list. */
++01180         qh_ptr = DWC_LIST_FIRST(&hcd->periodic_sched_ready);
++01181 
++01182         while (qh_ptr != &hcd->periodic_sched_ready &&
++01183                !DWC_CIRCLEQ_EMPTY(&hcd->free_hc_list)) {
++01184 
++01185                 qh = DWC_LIST_ENTRY(qh_ptr, dwc_otg_qh_t, qh_list_entry);
++01186                 assign_and_init_hc(hcd, qh);
++01187 
++01188                 /*
++01189                  * Move the QH from the periodic ready schedule to the
++01190                  * periodic assigned schedule.
++01191                  */
++01192                 qh_ptr = DWC_LIST_NEXT(qh_ptr);
++01193                 DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_assigned,
++01194                                    &qh->qh_list_entry);
++01195 
++01196                 ret_val = DWC_OTG_TRANSACTION_PERIODIC;
++01197         }
++01198 
++01199         /*
++01200          * Process entries in the inactive portion of the non-periodic
++01201          * schedule. Some free host channels may not be used if they are
++01202          * reserved for periodic transfers.
++01203          */
++01204         qh_ptr = hcd->non_periodic_sched_inactive.next;
++01205         num_channels = hcd->core_if->core_params->host_channels;
++01206         while (qh_ptr != &hcd->non_periodic_sched_inactive &&
++01207                (hcd->non_periodic_channels <
++01208                 num_channels - hcd->periodic_channels) &&
++01209                !DWC_CIRCLEQ_EMPTY(&hcd->free_hc_list)) {
++01210 
++01211                 qh = DWC_LIST_ENTRY(qh_ptr, dwc_otg_qh_t, qh_list_entry);
++01212 
++01213                 assign_and_init_hc(hcd, qh);
++01214 
++01215                 /*
++01216                  * Move the QH from the non-periodic inactive schedule to the
++01217                  * non-periodic active schedule.
++01218                  */
++01219                 qh_ptr = DWC_LIST_NEXT(qh_ptr);
++01220                 DWC_LIST_MOVE_HEAD(&hcd->non_periodic_sched_active,
++01221                                    &qh->qh_list_entry);
++01222 
++01223                 if (ret_val == DWC_OTG_TRANSACTION_NONE) {
++01224                         ret_val = DWC_OTG_TRANSACTION_NON_PERIODIC;
++01225                 } else {
++01226                         ret_val = DWC_OTG_TRANSACTION_ALL;
++01227                 }
++01228 
++01229                 hcd->non_periodic_channels++;
++01230         }
++01231 
++01232         return ret_val;
++01233 }
++01234 
++01253 static int queue_transaction(dwc_otg_hcd_t * hcd,
++01254                              dwc_hc_t * hc, uint16_t fifo_dwords_avail)
++01255 {
++01256         int retval;
++01257 
++01258         if (hcd->core_if->dma_enable) {
++01259                 if (hcd->core_if->dma_desc_enable) {
++01260                         if (!hc->xfer_started
++01261                             || (hc->ep_type == DWC_OTG_EP_TYPE_ISOC)) {
++01262                                 dwc_otg_hcd_start_xfer_ddma(hcd, hc->qh);
++01263                                 hc->qh->ping_state = 0;
++01264                         }
++01265                 } else if (!hc->xfer_started) {
++01266                         dwc_otg_hc_start_transfer(hcd->core_if, hc);
++01267                         hc->qh->ping_state = 0;
++01268                 }
++01269                 retval = 0;
++01270         } else if (hc->halt_pending) {
++01271                 /* Don't queue a request if the channel has been halted. */
++01272                 retval = 0;
++01273         } else if (hc->halt_on_queue) {
++01274                 dwc_otg_hc_halt(hcd->core_if, hc, hc->halt_status);
++01275                 retval = 0;
++01276         } else if (hc->do_ping) {
++01277                 if (!hc->xfer_started) {
++01278                         dwc_otg_hc_start_transfer(hcd->core_if, hc);
++01279                 }
++01280                 retval = 0;
++01281         } else if (!hc->ep_is_in || hc->data_pid_start == DWC_OTG_HC_PID_SETUP) {
++01282                 if ((fifo_dwords_avail * 4) >= hc->max_packet) {
++01283                         if (!hc->xfer_started) {
++01284                                 dwc_otg_hc_start_transfer(hcd->core_if, hc);
++01285                                 retval = 1;
++01286                         } else {
++01287                                 retval =
++01288                                     dwc_otg_hc_continue_transfer(hcd->core_if,
++01289                                                                  hc);
++01290                         }
++01291                 } else {
++01292                         retval = -1;
++01293                 }
++01294         } else {
++01295                 if (!hc->xfer_started) {
++01296                         dwc_otg_hc_start_transfer(hcd->core_if, hc);
++01297                         retval = 1;
++01298                 } else {
++01299                         retval = dwc_otg_hc_continue_transfer(hcd->core_if, hc);
++01300                 }
++01301         }
++01302 
++01303         return retval;
++01304 }
++01305 
++01313 static void process_periodic_channels(dwc_otg_hcd_t * hcd)
++01314 {
++01315         hptxsts_data_t tx_status;
++01316         dwc_list_link_t *qh_ptr;
++01317         dwc_otg_qh_t *qh;
++01318         int status;
++01319         int no_queue_space = 0;
++01320         int no_fifo_space = 0;
++01321 
++01322         dwc_otg_host_global_regs_t *host_regs;
++01323         host_regs = hcd->core_if->host_if->host_global_regs;
++01324 
++01325         DWC_DEBUGPL(DBG_HCDV, "Queue periodic transactions\n");
++01326 #ifdef DEBUG
++01327         tx_status.d32 = DWC_READ_REG32(&host_regs->hptxsts);
++01328         DWC_DEBUGPL(DBG_HCDV,
++01329                     "  P Tx Req Queue Space Avail (before queue): %d\n",
++01330                     tx_status.b.ptxqspcavail);
++01331         DWC_DEBUGPL(DBG_HCDV, "  P Tx FIFO Space Avail (before queue): %d\n",
++01332                     tx_status.b.ptxfspcavail);
++01333 #endif
++01334 
++01335         qh_ptr = hcd->periodic_sched_assigned.next;
++01336         while (qh_ptr != &hcd->periodic_sched_assigned) {
++01337                 tx_status.d32 = DWC_READ_REG32(&host_regs->hptxsts);
++01338                 if (tx_status.b.ptxqspcavail == 0) {
++01339                         no_queue_space = 1;
++01340                         break;
++01341                 }
++01342 
++01343                 qh = DWC_LIST_ENTRY(qh_ptr, dwc_otg_qh_t, qh_list_entry);
++01344 
++01345                 /*
++01346                  * Set a flag if we're queuing high-bandwidth in slave mode.
++01347                  * The flag prevents any halts to get into the request queue in
++01348                  * the middle of multiple high-bandwidth packets getting queued.
++01349                  */
++01350                 if (!hcd->core_if->dma_enable && qh->channel->multi_count > 1) {
++01351                         hcd->core_if->queuing_high_bandwidth = 1;
++01352                 }
++01353                 status =
++01354                     queue_transaction(hcd, qh->channel,
++01355                                       tx_status.b.ptxfspcavail);
++01356                 if (status < 0) {
++01357                         no_fifo_space = 1;
++01358                         break;
++01359                 }
++01360 
++01361                 /*
++01362                  * In Slave mode, stay on the current transfer until there is
++01363                  * nothing more to do or the high-bandwidth request count is
++01364                  * reached. In DMA mode, only need to queue one request. The
++01365                  * controller automatically handles multiple packets for
++01366                  * high-bandwidth transfers.
++01367                  */
++01368                 if (hcd->core_if->dma_enable || status == 0 ||
++01369                     qh->channel->requests == qh->channel->multi_count) {
++01370                         qh_ptr = qh_ptr->next;
++01371                         /*
++01372                          * Move the QH from the periodic assigned schedule to
++01373                          * the periodic queued schedule.
++01374                          */
++01375                         DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_queued,
++01376                                            &qh->qh_list_entry);
++01377 
++01378                         /* done queuing high bandwidth */
++01379                         hcd->core_if->queuing_high_bandwidth = 0;
++01380                 }
++01381         }
++01382 
++01383         if (!hcd->core_if->dma_enable) {
++01384                 dwc_otg_core_global_regs_t *global_regs;
++01385                 gintmsk_data_t intr_mask = {.d32 = 0 };
++01386 
++01387                 global_regs = hcd->core_if->core_global_regs;
++01388                 intr_mask.b.ptxfempty = 1;
++01389 #ifdef DEBUG
++01390                 tx_status.d32 = DWC_READ_REG32(&host_regs->hptxsts);
++01391                 DWC_DEBUGPL(DBG_HCDV,
++01392                             "  P Tx Req Queue Space Avail (after queue): %d\n",
++01393                             tx_status.b.ptxqspcavail);
++01394                 DWC_DEBUGPL(DBG_HCDV,
++01395                             "  P Tx FIFO Space Avail (after queue): %d\n",
++01396                             tx_status.b.ptxfspcavail);
++01397 #endif
++01398                 if (!DWC_LIST_EMPTY(&hcd->periodic_sched_assigned) ||
++01399                     no_queue_space || no_fifo_space) {
++01400                         /*
++01401                          * May need to queue more transactions as the request
++01402                          * queue or Tx FIFO empties. Enable the periodic Tx
++01403                          * FIFO empty interrupt. (Always use the half-empty
++01404                          * level to ensure that new requests are loaded as
++01405                          * soon as possible.)
++01406                          */
++01407                         DWC_MODIFY_REG32(&global_regs->gintmsk, 0,
++01408                                          intr_mask.d32);
++01409                 } else {
++01410                         /*
++01411                          * Disable the Tx FIFO empty interrupt since there are
++01412                          * no more transactions that need to be queued right
++01413                          * now. This function is called from interrupt
++01414                          * handlers to queue more transactions as transfer
++01415                          * states change.
++01416                          */
++01417                         DWC_MODIFY_REG32(&global_regs->gintmsk, intr_mask.d32,
++01418                                          0);
++01419                 }
++01420         }
++01421 }
++01422 
++01430 static void process_non_periodic_channels(dwc_otg_hcd_t * hcd)
++01431 {
++01432         gnptxsts_data_t tx_status;
++01433         dwc_list_link_t *orig_qh_ptr;
++01434         dwc_otg_qh_t *qh;
++01435         int status;
++01436         int no_queue_space = 0;
++01437         int no_fifo_space = 0;
++01438         int more_to_do = 0;
++01439 
++01440         dwc_otg_core_global_regs_t *global_regs =
++01441             hcd->core_if->core_global_regs;
++01442 
++01443         DWC_DEBUGPL(DBG_HCDV, "Queue non-periodic transactions\n");
++01444 #ifdef DEBUG
++01445         tx_status.d32 = DWC_READ_REG32(&global_regs->gnptxsts);
++01446         DWC_DEBUGPL(DBG_HCDV,
++01447                     "  NP Tx Req Queue Space Avail (before queue): %d\n",
++01448                     tx_status.b.nptxqspcavail);
++01449         DWC_DEBUGPL(DBG_HCDV, "  NP Tx FIFO Space Avail (before queue): %d\n",
++01450                     tx_status.b.nptxfspcavail);
++01451 #endif
++01452         /*
++01453          * Keep track of the starting point. Skip over the start-of-list
++01454          * entry.
++01455          */
++01456         if (hcd->non_periodic_qh_ptr == &hcd->non_periodic_sched_active) {
++01457                 hcd->non_periodic_qh_ptr = hcd->non_periodic_qh_ptr->next;
++01458         }
++01459         orig_qh_ptr = hcd->non_periodic_qh_ptr;
++01460 
++01461         /*
++01462          * Process once through the active list or until no more space is
++01463          * available in the request queue or the Tx FIFO.
++01464          */
++01465         do {
++01466                 tx_status.d32 = DWC_READ_REG32(&global_regs->gnptxsts);
++01467                 if (!hcd->core_if->dma_enable && tx_status.b.nptxqspcavail == 0) {
++01468                         no_queue_space = 1;
++01469                         break;
++01470                 }
++01471 
++01472                 qh = DWC_LIST_ENTRY(hcd->non_periodic_qh_ptr, dwc_otg_qh_t,
++01473                                     qh_list_entry);
++01474                 status =
++01475                     queue_transaction(hcd, qh->channel,
++01476                                       tx_status.b.nptxfspcavail);
++01477 
++01478                 if (status > 0) {
++01479                         more_to_do = 1;
++01480                 } else if (status < 0) {
++01481                         no_fifo_space = 1;
++01482                         break;
++01483                 }
++01484 
++01485                 /* Advance to next QH, skipping start-of-list entry. */
++01486                 hcd->non_periodic_qh_ptr = hcd->non_periodic_qh_ptr->next;
++01487                 if (hcd->non_periodic_qh_ptr == &hcd->non_periodic_sched_active) {
++01488                         hcd->non_periodic_qh_ptr =
++01489                             hcd->non_periodic_qh_ptr->next;
++01490                 }
++01491 
++01492         } while (hcd->non_periodic_qh_ptr != orig_qh_ptr);
++01493 
++01494         if (!hcd->core_if->dma_enable) {
++01495                 gintmsk_data_t intr_mask = {.d32 = 0 };
++01496                 intr_mask.b.nptxfempty = 1;
++01497 
++01498 #ifdef DEBUG
++01499                 tx_status.d32 = DWC_READ_REG32(&global_regs->gnptxsts);
++01500                 DWC_DEBUGPL(DBG_HCDV,
++01501                             "  NP Tx Req Queue Space Avail (after queue): %d\n",
++01502                             tx_status.b.nptxqspcavail);
++01503                 DWC_DEBUGPL(DBG_HCDV,
++01504                             "  NP Tx FIFO Space Avail (after queue): %d\n",
++01505                             tx_status.b.nptxfspcavail);
++01506 #endif
++01507                 if (more_to_do || no_queue_space || no_fifo_space) {
++01508                         /*
++01509                          * May need to queue more transactions as the request
++01510                          * queue or Tx FIFO empties. Enable the non-periodic
++01511                          * Tx FIFO empty interrupt. (Always use the half-empty
++01512                          * level to ensure that new requests are loaded as
++01513                          * soon as possible.)
++01514                          */
++01515                         DWC_MODIFY_REG32(&global_regs->gintmsk, 0,
++01516                                          intr_mask.d32);
++01517                 } else {
++01518                         /*
++01519                          * Disable the Tx FIFO empty interrupt since there are
++01520                          * no more transactions that need to be queued right
++01521                          * now. This function is called from interrupt
++01522                          * handlers to queue more transactions as transfer
++01523                          * states change.
++01524                          */
++01525                         DWC_MODIFY_REG32(&global_regs->gintmsk, intr_mask.d32,
++01526                                          0);
++01527                 }
++01528         }
++01529 }
++01530 
++01540 void dwc_otg_hcd_queue_transactions(dwc_otg_hcd_t * hcd,
++01541                                     dwc_otg_transaction_type_e tr_type)
++01542 {
++01543 #ifdef DEBUG_SOF
++01544         DWC_DEBUGPL(DBG_HCD, "Queue Transactions\n");
++01545 #endif
++01546         /* Process host channels associated with periodic transfers. */
++01547         if ((tr_type == DWC_OTG_TRANSACTION_PERIODIC ||
++01548              tr_type == DWC_OTG_TRANSACTION_ALL) &&
++01549             !DWC_LIST_EMPTY(&hcd->periodic_sched_assigned)) {
++01550 
++01551                 process_periodic_channels(hcd);
++01552         }
++01553 
++01554         /* Process host channels associated with non-periodic transfers. */
++01555         if (tr_type == DWC_OTG_TRANSACTION_NON_PERIODIC ||
++01556             tr_type == DWC_OTG_TRANSACTION_ALL) {
++01557                 if (!DWC_LIST_EMPTY(&hcd->non_periodic_sched_active)) {
++01558                         process_non_periodic_channels(hcd);
++01559                 } else {
++01560                         /*
++01561                          * Ensure NP Tx FIFO empty interrupt is disabled when
++01562                          * there are no non-periodic transfers to process.
++01563                          */
++01564                         gintmsk_data_t gintmsk = {.d32 = 0 };
++01565                         gintmsk.b.nptxfempty = 1;
++01566                         DWC_MODIFY_REG32(&hcd->core_if->
++01567                                          core_global_regs->gintmsk, gintmsk.d32,
++01568                                          0);
++01569                 }
++01570         }
++01571 }
++01572 
++01573 #ifdef DWC_HS_ELECT_TST
++01574 /*
++01575  * Quick and dirty hack to implement the HS Electrical Test
++01576  * SINGLE_STEP_GET_DEVICE_DESCRIPTOR feature.
++01577  *
++01578  * This code was copied from our userspace app "hset". It sends a
++01579  * Get Device Descriptor control sequence in two parts, first the
++01580  * Setup packet by itself, followed some time later by the In and
++01581  * Ack packets. Rather than trying to figure out how to add this
++01582  * functionality to the normal driver code, we just hijack the
++01583  * hardware, using these two function to drive the hardware
++01584  * directly.
++01585  */
++01586 
++01587 static dwc_otg_core_global_regs_t *global_regs;
++01588 static dwc_otg_host_global_regs_t *hc_global_regs;
++01589 static dwc_otg_hc_regs_t *hc_regs;
++01590 static uint32_t *data_fifo;
++01591 
++01592 static void do_setup(void)
++01593 {
++01594         gintsts_data_t gintsts;
++01595         hctsiz_data_t hctsiz;
++01596         hcchar_data_t hcchar;
++01597         haint_data_t haint;
++01598         hcint_data_t hcint;
++01599 
++01600         /* Enable HAINTs */
++01601         DWC_WRITE_REG32(&hc_global_regs->haintmsk, 0x0001);
++01602 
++01603         /* Enable HCINTs */
++01604         DWC_WRITE_REG32(&hc_regs->hcintmsk, 0x04a3);
++01605 
++01606         /* Read GINTSTS */
++01607         gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
++01608 
++01609         /* Read HAINT */
++01610         haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
++01611 
++01612         /* Read HCINT */
++01613         hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
++01614 
++01615         /* Read HCCHAR */
++01616         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
++01617 
++01618         /* Clear HCINT */
++01619         DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
++01620 
++01621         /* Clear HAINT */
++01622         DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
++01623 
++01624         /* Clear GINTSTS */
++01625         DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
++01626 
++01627         /* Read GINTSTS */
++01628         gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
++01629 
++01630         /*
++01631          * Send Setup packet (Get Device Descriptor)
++01632          */
++01633 
++01634         /* Make sure channel is disabled */
++01635         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
++01636         if (hcchar.b.chen) {
++01637                 hcchar.b.chdis = 1;
++01638 //              hcchar.b.chen = 1;
++01639                 DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
++01640                 //sleep(1);
++01641                 dwc_mdelay(1000);
++01642 
++01643                 /* Read GINTSTS */
++01644                 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
++01645 
++01646                 /* Read HAINT */
++01647                 haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
++01648 
++01649                 /* Read HCINT */
++01650                 hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
++01651 
++01652                 /* Read HCCHAR */
++01653                 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
++01654 
++01655                 /* Clear HCINT */
++01656                 DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
++01657 
++01658                 /* Clear HAINT */
++01659                 DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
++01660 
++01661                 /* Clear GINTSTS */
++01662                 DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
++01663 
++01664                 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
++01665         }
++01666 
++01667         /* Set HCTSIZ */
++01668         hctsiz.d32 = 0;
++01669         hctsiz.b.xfersize = 8;
++01670         hctsiz.b.pktcnt = 1;
++01671         hctsiz.b.pid = DWC_OTG_HC_PID_SETUP;
++01672         DWC_WRITE_REG32(&hc_regs->hctsiz, hctsiz.d32);
++01673 
++01674         /* Set HCCHAR */
++01675         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
++01676         hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
++01677         hcchar.b.epdir = 0;
++01678         hcchar.b.epnum = 0;
++01679         hcchar.b.mps = 8;
++01680         hcchar.b.chen = 1;
++01681         DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
++01682 
++01683         /* Fill FIFO with Setup data for Get Device Descriptor */
++01684         data_fifo = (uint32_t *) ((char *)global_regs + 0x1000);
++01685         DWC_WRITE_REG32(data_fifo++, 0x01000680);
++01686         DWC_WRITE_REG32(data_fifo++, 0x00080000);
++01687 
++01688         gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
++01689 
++01690         /* Wait for host channel interrupt */
++01691         do {
++01692                 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
++01693         } while (gintsts.b.hcintr == 0);
++01694 
++01695         /* Disable HCINTs */
++01696         DWC_WRITE_REG32(&hc_regs->hcintmsk, 0x0000);
++01697 
++01698         /* Disable HAINTs */
++01699         DWC_WRITE_REG32(&hc_global_regs->haintmsk, 0x0000);
++01700 
++01701         /* Read HAINT */
++01702         haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
++01703 
++01704         /* Read HCINT */
++01705         hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
++01706 
++01707         /* Read HCCHAR */
++01708         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
++01709 
++01710         /* Clear HCINT */
++01711         DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
++01712 
++01713         /* Clear HAINT */
++01714         DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
++01715 
++01716         /* Clear GINTSTS */
++01717         DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
++01718 
++01719         /* Read GINTSTS */
++01720         gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
++01721 }
++01722 
++01723 static void do_in_ack(void)
++01724 {
++01725         gintsts_data_t gintsts;
++01726         hctsiz_data_t hctsiz;
++01727         hcchar_data_t hcchar;
++01728         haint_data_t haint;
++01729         hcint_data_t hcint;
++01730         host_grxsts_data_t grxsts;
++01731 
++01732         /* Enable HAINTs */
++01733         DWC_WRITE_REG32(&hc_global_regs->haintmsk, 0x0001);
++01734 
++01735         /* Enable HCINTs */
++01736         DWC_WRITE_REG32(&hc_regs->hcintmsk, 0x04a3);
++01737 
++01738         /* Read GINTSTS */
++01739         gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
++01740 
++01741         /* Read HAINT */
++01742         haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
++01743 
++01744         /* Read HCINT */
++01745         hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
++01746 
++01747         /* Read HCCHAR */
++01748         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
++01749 
++01750         /* Clear HCINT */
++01751         DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
++01752 
++01753         /* Clear HAINT */
++01754         DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
++01755 
++01756         /* Clear GINTSTS */
++01757         DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
++01758 
++01759         /* Read GINTSTS */
++01760         gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
++01761 
++01762         /*
++01763          * Receive Control In packet
++01764          */
++01765 
++01766         /* Make sure channel is disabled */
++01767         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
++01768         if (hcchar.b.chen) {
++01769                 hcchar.b.chdis = 1;
++01770                 hcchar.b.chen = 1;
++01771                 DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
++01772                 //sleep(1);
++01773                 dwc_mdelay(1000);
++01774 
++01775                 /* Read GINTSTS */
++01776                 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
++01777 
++01778                 /* Read HAINT */
++01779                 haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
++01780 
++01781                 /* Read HCINT */
++01782                 hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
++01783 
++01784                 /* Read HCCHAR */
++01785                 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
++01786 
++01787                 /* Clear HCINT */
++01788                 DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
++01789 
++01790                 /* Clear HAINT */
++01791                 DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
++01792 
++01793                 /* Clear GINTSTS */
++01794                 DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
++01795 
++01796                 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
++01797         }
++01798 
++01799         /* Set HCTSIZ */
++01800         hctsiz.d32 = 0;
++01801         hctsiz.b.xfersize = 8;
++01802         hctsiz.b.pktcnt = 1;
++01803         hctsiz.b.pid = DWC_OTG_HC_PID_DATA1;
++01804         DWC_WRITE_REG32(&hc_regs->hctsiz, hctsiz.d32);
++01805 
++01806         /* Set HCCHAR */
++01807         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
++01808         hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
++01809         hcchar.b.epdir = 1;
++01810         hcchar.b.epnum = 0;
++01811         hcchar.b.mps = 8;
++01812         hcchar.b.chen = 1;
++01813         DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
++01814 
++01815         gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
++01816 
++01817         /* Wait for receive status queue interrupt */
++01818         do {
++01819                 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
++01820         } while (gintsts.b.rxstsqlvl == 0);
++01821 
++01822         /* Read RXSTS */
++01823         grxsts.d32 = DWC_READ_REG32(&global_regs->grxstsp);
++01824 
++01825         /* Clear RXSTSQLVL in GINTSTS */
++01826         gintsts.d32 = 0;
++01827         gintsts.b.rxstsqlvl = 1;
++01828         DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
++01829 
++01830         switch (grxsts.b.pktsts) {
++01831         case DWC_GRXSTS_PKTSTS_IN:
++01832                 /* Read the data into the host buffer */
++01833                 if (grxsts.b.bcnt > 0) {
++01834                         int i;
++01835                         int word_count = (grxsts.b.bcnt + 3) / 4;
++01836 
++01837                         data_fifo = (uint32_t *) ((char *)global_regs + 0x1000);
++01838 
++01839                         for (i = 0; i < word_count; i++) {
++01840                                 (void)DWC_READ_REG32(data_fifo++);
++01841                         }
++01842                 }
++01843                 break;
++01844 
++01845         default:
++01846                 break;
++01847         }
++01848 
++01849         gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
++01850 
++01851         /* Wait for receive status queue interrupt */
++01852         do {
++01853                 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
++01854         } while (gintsts.b.rxstsqlvl == 0);
++01855 
++01856         /* Read RXSTS */
++01857         grxsts.d32 = DWC_READ_REG32(&global_regs->grxstsp);
++01858 
++01859         /* Clear RXSTSQLVL in GINTSTS */
++01860         gintsts.d32 = 0;
++01861         gintsts.b.rxstsqlvl = 1;
++01862         DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
++01863 
++01864         switch (grxsts.b.pktsts) {
++01865         case DWC_GRXSTS_PKTSTS_IN_XFER_COMP:
++01866                 break;
++01867 
++01868         default:
++01869                 break;
++01870         }
++01871 
++01872         gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
++01873 
++01874         /* Wait for host channel interrupt */
++01875         do {
++01876                 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
++01877         } while (gintsts.b.hcintr == 0);
++01878 
++01879         /* Read HAINT */
++01880         haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
++01881 
++01882         /* Read HCINT */
++01883         hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
++01884 
++01885         /* Read HCCHAR */
++01886         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
++01887 
++01888         /* Clear HCINT */
++01889         DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
++01890 
++01891         /* Clear HAINT */
++01892         DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
++01893 
++01894         /* Clear GINTSTS */
++01895         DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
++01896 
++01897         /* Read GINTSTS */
++01898         gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
++01899 
++01900 //      usleep(100000);
++01901 //      mdelay(100);
++01902         dwc_mdelay(1);
++01903 
++01904         /*
++01905          * Send handshake packet
++01906          */
++01907 
++01908         /* Read HAINT */
++01909         haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
++01910 
++01911         /* Read HCINT */
++01912         hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
++01913 
++01914         /* Read HCCHAR */
++01915         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
++01916 
++01917         /* Clear HCINT */
++01918         DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
++01919 
++01920         /* Clear HAINT */
++01921         DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
++01922 
++01923         /* Clear GINTSTS */
++01924         DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
++01925 
++01926         /* Read GINTSTS */
++01927         gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
++01928 
++01929         /* Make sure channel is disabled */
++01930         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
++01931         if (hcchar.b.chen) {
++01932                 hcchar.b.chdis = 1;
++01933                 hcchar.b.chen = 1;
++01934                 DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
++01935                 //sleep(1);
++01936                 dwc_mdelay(1000);
++01937 
++01938                 /* Read GINTSTS */
++01939                 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
++01940 
++01941                 /* Read HAINT */
++01942                 haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
++01943 
++01944                 /* Read HCINT */
++01945                 hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
++01946 
++01947                 /* Read HCCHAR */
++01948                 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
++01949 
++01950                 /* Clear HCINT */
++01951                 DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
++01952 
++01953                 /* Clear HAINT */
++01954                 DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
++01955 
++01956                 /* Clear GINTSTS */
++01957                 DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
++01958 
++01959                 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
++01960         }
++01961 
++01962         /* Set HCTSIZ */
++01963         hctsiz.d32 = 0;
++01964         hctsiz.b.xfersize = 0;
++01965         hctsiz.b.pktcnt = 1;
++01966         hctsiz.b.pid = DWC_OTG_HC_PID_DATA1;
++01967         DWC_WRITE_REG32(&hc_regs->hctsiz, hctsiz.d32);
++01968 
++01969         /* Set HCCHAR */
++01970         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
++01971         hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
++01972         hcchar.b.epdir = 0;
++01973         hcchar.b.epnum = 0;
++01974         hcchar.b.mps = 8;
++01975         hcchar.b.chen = 1;
++01976         DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
++01977 
++01978         gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
++01979 
++01980         /* Wait for host channel interrupt */
++01981         do {
++01982                 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
++01983         } while (gintsts.b.hcintr == 0);
++01984 
++01985         /* Disable HCINTs */
++01986         DWC_WRITE_REG32(&hc_regs->hcintmsk, 0x0000);
++01987 
++01988         /* Disable HAINTs */
++01989         DWC_WRITE_REG32(&hc_global_regs->haintmsk, 0x0000);
++01990 
++01991         /* Read HAINT */
++01992         haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
++01993 
++01994         /* Read HCINT */
++01995         hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
++01996 
++01997         /* Read HCCHAR */
++01998         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
++01999 
++02000         /* Clear HCINT */
++02001         DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
++02002 
++02003         /* Clear HAINT */
++02004         DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
++02005 
++02006         /* Clear GINTSTS */
++02007         DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
++02008 
++02009         /* Read GINTSTS */
++02010         gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
++02011 }
++02012 #endif
++02013 
++02015 int dwc_otg_hcd_hub_control(dwc_otg_hcd_t * dwc_otg_hcd,
++02016                             uint16_t typeReq,
++02017                             uint16_t wValue,
++02018                             uint16_t wIndex, uint8_t * buf, uint16_t wLength)
++02019 {
++02020         int retval = 0;
++02021 
++02022         dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;
++02023         usb_hub_descriptor_t *hub_desc;
++02024         hprt0_data_t hprt0 = {.d32 = 0 };
++02025 
++02026         uint32_t port_status;
++02027 
++02028         switch (typeReq) {
++02029         case UCR_CLEAR_HUB_FEATURE:
++02030                 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
++02031                             "ClearHubFeature 0x%x\n", wValue);
++02032                 switch (wValue) {
++02033                 case UHF_C_HUB_LOCAL_POWER:
++02034                 case UHF_C_HUB_OVER_CURRENT:
++02035                         /* Nothing required here */
++02036                         break;
++02037                 default:
++02038                         retval = -DWC_E_INVALID;
++02039                         DWC_ERROR("DWC OTG HCD - "
++02040                                   "ClearHubFeature request %xh unknown\n",
++02041                                   wValue);
++02042                 }
++02043                 break;
++02044         case UCR_CLEAR_PORT_FEATURE:
++02045 #ifdef CONFIG_USB_DWC_OTG_LPM
++02046                 if (wValue != UHF_PORT_L1)
++02047 #endif
++02048                         if (!wIndex || wIndex > 1)
++02049                                 goto error;
++02050 
++02051                 switch (wValue) {
++02052                 case UHF_PORT_ENABLE:
++02053                         DWC_DEBUGPL(DBG_ANY, "DWC OTG HCD HUB CONTROL - "
++02054                                     "ClearPortFeature USB_PORT_FEAT_ENABLE\n");
++02055                         hprt0.d32 = dwc_otg_read_hprt0(core_if);
++02056                         hprt0.b.prtena = 1;
++02057                         DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
++02058                         break;
++02059                 case UHF_PORT_SUSPEND:
++02060                         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
++02061                                     "ClearPortFeature USB_PORT_FEAT_SUSPEND\n");
++02062 
++02063                         if (core_if->power_down == 2) {
++02064                                 dwc_otg_host_hibernation_restore(core_if, 0, 0);
++02065                         } else {
++02066                                 DWC_WRITE_REG32(core_if->pcgcctl, 0);
++02067                                 dwc_mdelay(5);
++02068 
++02069                                 hprt0.d32 = dwc_otg_read_hprt0(core_if);
++02070                                 hprt0.b.prtres = 1;
++02071                                 DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
++02072                                 hprt0.b.prtsusp = 0;
++02073                                 /* Clear Resume bit */
++02074                                 dwc_mdelay(100);
++02075                                 hprt0.b.prtres = 0;
++02076                                 DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
++02077                         }
++02078                         break;
++02079 #ifdef CONFIG_USB_DWC_OTG_LPM
++02080                 case UHF_PORT_L1:
++02081                         {
++02082                                 pcgcctl_data_t pcgcctl = {.d32 = 0 };
++02083                                 glpmcfg_data_t lpmcfg = {.d32 = 0 };
++02084 
++02085                                 lpmcfg.d32 =
++02086                                     DWC_READ_REG32(&core_if->
++02087                                                    core_global_regs->glpmcfg);
++02088                                 lpmcfg.b.en_utmi_sleep = 0;
++02089                                 lpmcfg.b.hird_thres &= (~(1 << 4));
++02090                                 lpmcfg.b.prt_sleep_sts = 1;
++02091                                 DWC_WRITE_REG32(&core_if->
++02092                                                 core_global_regs->glpmcfg,
++02093                                                 lpmcfg.d32);
++02094 
++02095                                 /* Clear Enbl_L1Gating bit. */
++02096                                 pcgcctl.b.enbl_sleep_gating = 1;
++02097                                 DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32,
++02098                                                  0);
++02099 
++02100                                 dwc_mdelay(5);
++02101 
++02102                                 hprt0.d32 = dwc_otg_read_hprt0(core_if);
++02103                                 hprt0.b.prtres = 1;
++02104                                 DWC_WRITE_REG32(core_if->host_if->hprt0,
++02105                                                 hprt0.d32);
++02106                                 /* This bit will be cleared in wakeup interrupt handle */
++02107                                 break;
++02108                         }
++02109 #endif
++02110                 case UHF_PORT_POWER:
++02111                         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
++02112                                     "ClearPortFeature USB_PORT_FEAT_POWER\n");
++02113                         hprt0.d32 = dwc_otg_read_hprt0(core_if);
++02114                         hprt0.b.prtpwr = 0;
++02115                         DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
++02116                         break;
++02117                 case UHF_PORT_INDICATOR:
++02118                         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
++02119                                     "ClearPortFeature USB_PORT_FEAT_INDICATOR\n");
++02120                         /* Port inidicator not supported */
++02121                         break;
++02122                 case UHF_C_PORT_CONNECTION:
++02123                         /* Clears drivers internal connect status change
++02124                          * flag */
++02125                         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
++02126                                     "ClearPortFeature USB_PORT_FEAT_C_CONNECTION\n");
++02127                         dwc_otg_hcd->flags.b.port_connect_status_change = 0;
++02128                         break;
++02129                 case UHF_C_PORT_RESET:
++02130                         /* Clears the driver's internal Port Reset Change
++02131                          * flag */
++02132                         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
++02133                                     "ClearPortFeature USB_PORT_FEAT_C_RESET\n");
++02134                         dwc_otg_hcd->flags.b.port_reset_change = 0;
++02135                         break;
++02136                 case UHF_C_PORT_ENABLE:
++02137                         /* Clears the driver's internal Port
++02138                          * Enable/Disable Change flag */
++02139                         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
++02140                                     "ClearPortFeature USB_PORT_FEAT_C_ENABLE\n");
++02141                         dwc_otg_hcd->flags.b.port_enable_change = 0;
++02142                         break;
++02143                 case UHF_C_PORT_SUSPEND:
++02144                         /* Clears the driver's internal Port Suspend
++02145                          * Change flag, which is set when resume signaling on
++02146                          * the host port is complete */
++02147                         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
++02148                                     "ClearPortFeature USB_PORT_FEAT_C_SUSPEND\n");
++02149                         dwc_otg_hcd->flags.b.port_suspend_change = 0;
++02150                         break;
++02151 #ifdef CONFIG_USB_DWC_OTG_LPM
++02152                 case UHF_C_PORT_L1:
++02153                         dwc_otg_hcd->flags.b.port_l1_change = 0;
++02154                         break;
++02155 #endif
++02156                 case UHF_C_PORT_OVER_CURRENT:
++02157                         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
++02158                                     "ClearPortFeature USB_PORT_FEAT_C_OVER_CURRENT\n");
++02159                         dwc_otg_hcd->flags.b.port_over_current_change = 0;
++02160                         break;
++02161                 default:
++02162                         retval = -DWC_E_INVALID;
++02163                         DWC_ERROR("DWC OTG HCD - "
++02164                                   "ClearPortFeature request %xh "
++02165                                   "unknown or unsupported\n", wValue);
++02166                 }
++02167                 break;
++02168         case UCR_GET_HUB_DESCRIPTOR:
++02169                 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
++02170                             "GetHubDescriptor\n");
++02171                 hub_desc = (usb_hub_descriptor_t *) buf;
++02172                 hub_desc->bDescLength = 9;
++02173                 hub_desc->bDescriptorType = 0x29;
++02174                 hub_desc->bNbrPorts = 1;
++02175                 USETW(hub_desc->wHubCharacteristics, 0x08);
++02176                 hub_desc->bPwrOn2PwrGood = 1;
++02177                 hub_desc->bHubContrCurrent = 0;
++02178                 hub_desc->DeviceRemovable[0] = 0;
++02179                 hub_desc->DeviceRemovable[1] = 0xff;
++02180                 break;
++02181         case UCR_GET_HUB_STATUS:
++02182                 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
++02183                             "GetHubStatus\n");
++02184                 DWC_MEMSET(buf, 0, 4);
++02185                 break;
++02186         case UCR_GET_PORT_STATUS:
++02187                 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
++02188                             "GetPortStatus wIndex = 0x%04x FLAGS=0x%08x\n",
++02189                             wIndex, dwc_otg_hcd->flags.d32);
++02190                 if (!wIndex || wIndex > 1)
++02191                         goto error;
++02192 
++02193                 port_status = 0;
++02194 
++02195                 if (dwc_otg_hcd->flags.b.port_connect_status_change)
++02196                         port_status |= (1 << UHF_C_PORT_CONNECTION);
++02197 
++02198                 if (dwc_otg_hcd->flags.b.port_enable_change)
++02199                         port_status |= (1 << UHF_C_PORT_ENABLE);
++02200 
++02201                 if (dwc_otg_hcd->flags.b.port_suspend_change)
++02202                         port_status |= (1 << UHF_C_PORT_SUSPEND);
++02203 
++02204                 if (dwc_otg_hcd->flags.b.port_l1_change)
++02205                         port_status |= (1 << UHF_C_PORT_L1);
++02206 
++02207                 if (dwc_otg_hcd->flags.b.port_reset_change) {
++02208                         port_status |= (1 << UHF_C_PORT_RESET);
++02209                 }
++02210 
++02211                 if (dwc_otg_hcd->flags.b.port_over_current_change) {
++02212                         DWC_WARN("Overcurrent change detected\n");
++02213                         port_status |= (1 << UHF_C_PORT_OVER_CURRENT);
++02214                 }
++02215 
++02216                 if (!dwc_otg_hcd->flags.b.port_connect_status) {
++02217                         /*
++02218                          * The port is disconnected, which means the core is
++02219                          * either in device mode or it soon will be. Just
++02220                          * return 0's for the remainder of the port status
++02221                          * since the port register can't be read if the core
++02222                          * is in device mode.
++02223                          */
++02224                         *((__le32 *) buf) = dwc_cpu_to_le32(&port_status);
++02225                         break;
++02226                 }
++02227 
++02228                 hprt0.d32 = DWC_READ_REG32(core_if->host_if->hprt0);
++02229                 DWC_DEBUGPL(DBG_HCDV, "  HPRT0: 0x%08x\n", hprt0.d32);
++02230 
++02231                 if (hprt0.b.prtconnsts)
++02232                         port_status |= (1 << UHF_PORT_CONNECTION);
++02233 
++02234                 if (hprt0.b.prtena)
++02235                         port_status |= (1 << UHF_PORT_ENABLE);
++02236 
++02237                 if (hprt0.b.prtsusp)
++02238                         port_status |= (1 << UHF_PORT_SUSPEND);
++02239 
++02240                 if (hprt0.b.prtovrcurract)
++02241                         port_status |= (1 << UHF_PORT_OVER_CURRENT);
++02242 
++02243                 if (hprt0.b.prtrst)
++02244                         port_status |= (1 << UHF_PORT_RESET);
++02245 
++02246                 if (hprt0.b.prtpwr)
++02247                         port_status |= (1 << UHF_PORT_POWER);
++02248 
++02249                 if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_HIGH_SPEED)
++02250                         port_status |= (1 << UHF_PORT_HIGH_SPEED);
++02251                 else if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_LOW_SPEED)
++02252                         port_status |= (1 << UHF_PORT_LOW_SPEED);
++02253 
++02254                 if (hprt0.b.prttstctl)
++02255                         port_status |= (1 << UHF_PORT_TEST);
++02256                 if (dwc_otg_get_lpm_portsleepstatus(dwc_otg_hcd->core_if)) {
++02257                         port_status |= (1 << UHF_PORT_L1);
++02258                 }
++02259                 /*
++02260                    For Synopsys HW emulation of Power down wkup_control asserts the 
++02261                    hreset_n and prst_n on suspned. This causes the HPRT0 to be zero. 
++02262                    We intentionally tell the software that port is in L2Suspend state. 
++02263                    Only for STE.
++02264                 */
++02265                 if ((core_if->power_down == 2)
++02266                     && (core_if->hibernation_suspend == 1)) {
++02267                         port_status |= (1 << UHF_PORT_SUSPEND);
++02268                 }
++02269                 /* USB_PORT_FEAT_INDICATOR unsupported always 0 */
++02270 
++02271                 *((__le32 *) buf) = dwc_cpu_to_le32(&port_status);
++02272 
++02273                 break;
++02274         case UCR_SET_HUB_FEATURE:
++02275                 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
++02276                             "SetHubFeature\n");
++02277                 /* No HUB features supported */
++02278                 break;
++02279         case UCR_SET_PORT_FEATURE:
++02280                 if (wValue != UHF_PORT_TEST && (!wIndex || wIndex > 1))
++02281                         goto error;
++02282 
++02283                 if (!dwc_otg_hcd->flags.b.port_connect_status) {
++02284                         /*
++02285                          * The port is disconnected, which means the core is
++02286                          * either in device mode or it soon will be. Just
++02287                          * return without doing anything since the port
++02288                          * register can't be written if the core is in device
++02289                          * mode.
++02290                          */
++02291                         break;
++02292                 }
++02293 
++02294                 switch (wValue) {
++02295                 case UHF_PORT_SUSPEND:
++02296                         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
++02297                                     "SetPortFeature - USB_PORT_FEAT_SUSPEND\n");
++02298                         if (dwc_otg_hcd_otg_port(dwc_otg_hcd) != wIndex) {
++02299                                 goto error;
++02300                         }
++02301                         if (core_if->power_down == 2) {
++02302                                 int timeout = 300;
++02303                                 dwc_irqflags_t flags;
++02304                                 pcgcctl_data_t pcgcctl = {.d32 = 0 };
++02305                                 gpwrdn_data_t gpwrdn = {.d32 = 0 };
++02306                                 gusbcfg_data_t gusbcfg = {.d32 = 0 };
++02307 #ifdef DWC_DEV_SRPCAP
++02308                                 int32_t otg_cap_param = core_if->core_params->otg_cap;
++02309 #endif
++02310                                 DWC_PRINTF("Preparing for complete power-off\n");
++02311 
++02312                                 /* Save registers before hibernation */
++02313                                 dwc_otg_save_global_regs(core_if);
++02314                                 dwc_otg_save_host_regs(core_if);
++02315 
++02316                                 hprt0.d32 = dwc_otg_read_hprt0(core_if);
++02317                                 hprt0.b.prtsusp = 1;
++02318                                 hprt0.b.prtena = 0;
++02319                                 DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
++02320                                 /* Spin hprt0.b.prtsusp to became 1 */
++02321                                 do {
++02322                                         hprt0.d32 = dwc_otg_read_hprt0(core_if);
++02323                                         if (hprt0.b.prtsusp) {
++02324                                                 break;
++02325                                         }
++02326                                         dwc_mdelay(1);
++02327                                 } while (--timeout);
++02328                                 if (!timeout) {
++02329                                         DWC_WARN("Suspend wasn't genereted\n");
++02330                                 }
++02331                                 dwc_udelay(10);
++02332 
++02333                                 /*
++02334                                  * We need to disable interrupts to prevent servicing of any IRQ
++02335                                  * during going to hibernation
++02336                                  */
++02337                                 DWC_SPINLOCK_IRQSAVE(dwc_otg_hcd->lock, &flags);
++02338                                 core_if->lx_state = DWC_OTG_L2;
++02339 #ifdef DWC_DEV_SRPCAP
++02340                                 hprt0.d32 = dwc_otg_read_hprt0(core_if);
++02341                                 hprt0.b.prtpwr = 0;
++02342                                 hprt0.b.prtena = 0;
++02343                                 DWC_WRITE_REG32(core_if->host_if->hprt0,
++02344                                                 hprt0.d32);
++02345 #endif
++02346                                 gusbcfg.d32 =
++02347                                     DWC_READ_REG32(&core_if->core_global_regs->
++02348                                                    gusbcfg);
++02349                                 if (gusbcfg.b.ulpi_utmi_sel == 1) {
++02350                                         /* ULPI interface */
++02351                                         /* Suspend the Phy Clock */
++02352                                         pcgcctl.d32 = 0;
++02353                                         pcgcctl.b.stoppclk = 1;
++02354                                         DWC_MODIFY_REG32(core_if->pcgcctl, 0,
++02355                                                          pcgcctl.d32);
++02356                                         dwc_udelay(10);
++02357                                         gpwrdn.b.pmuactv = 1;
++02358                                         DWC_MODIFY_REG32(&core_if->
++02359                                                          core_global_regs->
++02360                                                          gpwrdn, 0, gpwrdn.d32);
++02361                                 } else {
++02362                                         /* UTMI+ Interface */
++02363                                         gpwrdn.b.pmuactv = 1;
++02364                                         DWC_MODIFY_REG32(&core_if->
++02365                                                          core_global_regs->
++02366                                                          gpwrdn, 0, gpwrdn.d32);
++02367                                         dwc_udelay(10);
++02368                                         pcgcctl.b.stoppclk = 1;
++02369                                         DWC_MODIFY_REG32(core_if->pcgcctl, 0, pcgcctl.d32);
++02370                                         dwc_udelay(10);
++02371                                 }
++02372 #ifdef DWC_DEV_SRPCAP                           
++02373                                 gpwrdn.d32 = 0;
++02374                                 gpwrdn.b.dis_vbus = 1;
++02375                                 DWC_MODIFY_REG32(&core_if->core_global_regs->
++02376                                                  gpwrdn, 0, gpwrdn.d32);
++02377 #endif
++02378                                 gpwrdn.d32 = 0;
++02379                                 gpwrdn.b.pmuintsel = 1;
++02380                                 DWC_MODIFY_REG32(&core_if->core_global_regs->
++02381                                                  gpwrdn, 0, gpwrdn.d32);
++02382                                 dwc_udelay(10);
++02383 
++02384                                 gpwrdn.d32 = 0;
++02385 #ifdef DWC_DEV_SRPCAP
++02386                                 gpwrdn.b.srp_det_msk = 1;
++02387 #endif
++02388                                 gpwrdn.b.disconn_det_msk = 1;
++02389                                 gpwrdn.b.lnstchng_msk = 1;
++02390                                 gpwrdn.b.sts_chngint_msk = 1;
++02391                                 DWC_MODIFY_REG32(&core_if->core_global_regs->
++02392                                                  gpwrdn, 0, gpwrdn.d32);
++02393                                 dwc_udelay(10);
++02394 
++02395                                 /* Enable Power Down Clamp and all interrupts in GPWRDN */
++02396                                 gpwrdn.d32 = 0;
++02397                                 gpwrdn.b.pwrdnclmp = 1;
++02398                                 DWC_MODIFY_REG32(&core_if->core_global_regs->
++02399                                                  gpwrdn, 0, gpwrdn.d32);
++02400                                 dwc_udelay(10);
++02401 
++02402                                 /* Switch off VDD */
++02403                                 gpwrdn.d32 = 0;
++02404                                 gpwrdn.b.pwrdnswtch = 1;
++02405                                 DWC_MODIFY_REG32(&core_if->core_global_regs->
++02406                                                  gpwrdn, 0, gpwrdn.d32);
++02407 
++02408 #ifdef DWC_DEV_SRPCAP
++02409                                 if (otg_cap_param == DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE)
++02410                                 {
++02411                                         core_if->pwron_timer_started = 1;
++02412                                         DWC_TIMER_SCHEDULE(core_if->pwron_timer, 6000 /* 6 secs */ );
++02413                                 }
++02414 #endif
++02415                                 /* Save gpwrdn register for further usage if stschng interrupt */
++02416                                 core_if->gr_backup->gpwrdn_local =
++02417                                                 DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
++02418 
++02419                                 /* Set flag to indicate that we are in hibernation */
++02420                                 core_if->hibernation_suspend = 1;
++02421                                 DWC_SPINUNLOCK_IRQRESTORE(dwc_otg_hcd->lock,flags);
++02422 
++02423                                 DWC_PRINTF("Host hibernation completed\n");
++02424                                 // Exit from case statement
++02425                                 break;
++02426 
++02427                         }
++02428                         if (dwc_otg_hcd_otg_port(dwc_otg_hcd) == wIndex &&
++02429                             dwc_otg_hcd->fops->get_b_hnp_enable(dwc_otg_hcd)) {
++02430                                 gotgctl_data_t gotgctl = {.d32 = 0 };
++02431                                 gotgctl.b.hstsethnpen = 1;
++02432                                 DWC_MODIFY_REG32(&core_if->core_global_regs->
++02433                                                  gotgctl, 0, gotgctl.d32);
++02434                                 core_if->op_state = A_SUSPEND;
++02435                         }
++02436                         hprt0.d32 = dwc_otg_read_hprt0(core_if);
++02437                         hprt0.b.prtsusp = 1;
++02438                         DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
++02439                         {
++02440                                 dwc_irqflags_t flags;
++02441                                 /* Update lx_state */
++02442                                 DWC_SPINLOCK_IRQSAVE(dwc_otg_hcd->lock, &flags);
++02443                                 core_if->lx_state = DWC_OTG_L2;
++02444                                 DWC_SPINUNLOCK_IRQRESTORE(dwc_otg_hcd->lock, flags);
++02445                         }
++02446                         /* Suspend the Phy Clock */
++02447                         {
++02448                                 pcgcctl_data_t pcgcctl = {.d32 = 0 };
++02449                                 pcgcctl.b.stoppclk = 1;
++02450                                 DWC_MODIFY_REG32(core_if->pcgcctl, 0,
++02451                                                  pcgcctl.d32);
++02452                                 dwc_udelay(10);
++02453                         }
++02454 
++02455                         /* For HNP the bus must be suspended for at least 200ms. */
++02456                         if (dwc_otg_hcd->fops->get_b_hnp_enable(dwc_otg_hcd)) {
++02457                                 pcgcctl_data_t pcgcctl = {.d32 = 0 };
++02458                                 pcgcctl.b.stoppclk = 1;
++02459                 DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32, 0);
++02460                                 dwc_mdelay(200);
++02461                         }
++02462 
++02464 #if 0 //vahrama !!!!!!!!!!!!!!!!!!
++02465                         if (core_if->adp_enable) {
++02466                                 gotgctl_data_t gotgctl = {.d32 = 0 };
++02467                                 gpwrdn_data_t gpwrdn;
++02468 
++02469                                 while (gotgctl.b.asesvld == 1) {
++02470                                         gotgctl.d32 =
++02471                                             DWC_READ_REG32(&core_if->
++02472                                                            core_global_regs->
++02473                                                            gotgctl);
++02474                                         dwc_mdelay(100);
++02475                                 }
++02476 
++02477                                 /* Enable Power Down Logic */
++02478                                 gpwrdn.d32 = 0;
++02479                                 gpwrdn.b.pmuactv = 1;
++02480                                 DWC_MODIFY_REG32(&core_if->core_global_regs->
++02481                                                  gpwrdn, 0, gpwrdn.d32);
++02482 
++02483                                 /* Unmask SRP detected interrupt from Power Down Logic */
++02484                                 gpwrdn.d32 = 0;
++02485                                 gpwrdn.b.srp_det_msk = 1;
++02486                                 DWC_MODIFY_REG32(&core_if->core_global_regs->
++02487                                                  gpwrdn, 0, gpwrdn.d32);
++02488 
++02489                                 dwc_otg_adp_probe_start(core_if);
++02490                         }
++02491 #endif
++02492                         break;
++02493                 case UHF_PORT_POWER:
++02494                         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
++02495                                     "SetPortFeature - USB_PORT_FEAT_POWER\n");
++02496                         hprt0.d32 = dwc_otg_read_hprt0(core_if);
++02497                         hprt0.b.prtpwr = 1;
++02498                         DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
++02499                         break;
++02500                 case UHF_PORT_RESET:
++02501                         if ((core_if->power_down == 2)
++02502                             && (core_if->hibernation_suspend == 1)) {
++02503                                 /* If we are going to exit from Hibernated
++02504                                  * state via USB RESET.
++02505                                  */
++02506                                 dwc_otg_host_hibernation_restore(core_if, 0, 1);
++02507                         } else {
++02508                                 hprt0.d32 = dwc_otg_read_hprt0(core_if);
++02509 
++02510                                 DWC_DEBUGPL(DBG_HCD,
++02511                                             "DWC OTG HCD HUB CONTROL - "
++02512                                             "SetPortFeature - USB_PORT_FEAT_RESET\n");
++02513                                 {
++02514                                         pcgcctl_data_t pcgcctl = {.d32 = 0 };
++02515                                         pcgcctl.b.enbl_sleep_gating = 1;
++02516                                         pcgcctl.b.stoppclk = 1;
++02517                                         DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32, 0);
++02518                                         DWC_WRITE_REG32(core_if->pcgcctl, 0);
++02519                                 }
++02520 #ifdef CONFIG_USB_DWC_OTG_LPM
++02521                                 {
++02522                                         glpmcfg_data_t lpmcfg;
++02523                                         lpmcfg.d32 =
++02524                                                 DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
++02525                                         if (lpmcfg.b.prt_sleep_sts) {
++02526                                                 lpmcfg.b.en_utmi_sleep = 0;
++02527                                                 lpmcfg.b.hird_thres &= (~(1 << 4));
++02528                                                 DWC_WRITE_REG32
++02529                                                     (&core_if->core_global_regs->glpmcfg,
++02530                                                      lpmcfg.d32);
++02531                                                 dwc_mdelay(1);
++02532                                         }
++02533                                 }
++02534 #endif
++02535                                 hprt0.d32 = dwc_otg_read_hprt0(core_if);
++02536                                 /* Clear suspend bit if resetting from suspended state. */
++02537                                 hprt0.b.prtsusp = 0;
++02538                                 /* When B-Host the Port reset bit is set in
++02539                                  * the Start HCD Callback function, so that
++02540                                  * the reset is started within 1ms of the HNP
++02541                                  * success interrupt. */
++02542                                 if (!dwc_otg_hcd_is_b_host(dwc_otg_hcd)) {
++02543                                         hprt0.b.prtpwr = 1;
++02544                                         hprt0.b.prtrst = 1;
++02545                                         DWC_PRINTF("Indeed it is in host mode hprt0 = %08x\n",hprt0.d32);
++02546                                         DWC_WRITE_REG32(core_if->host_if->hprt0,
++02547                                                         hprt0.d32);
++02548                                 }
++02549                                 /* Clear reset bit in 10ms (FS/LS) or 50ms (HS) */
++02550                                 dwc_mdelay(60);
++02551                                 hprt0.b.prtrst = 0;
++02552                                 DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
++02553                                 core_if->lx_state = DWC_OTG_L0; /* Now back to the on state */
++02554                         }
++02555                         break;
++02556 #ifdef DWC_HS_ELECT_TST
++02557                 case UHF_PORT_TEST:
++02558                         {
++02559                                 uint32_t t;
++02560                                 gintmsk_data_t gintmsk;
++02561 
++02562                                 t = (wIndex >> 8);      /* MSB wIndex USB */
++02563                                 DWC_DEBUGPL(DBG_HCD,
++02564                                             "DWC OTG HCD HUB CONTROL - "
++02565                                             "SetPortFeature - USB_PORT_FEAT_TEST %d\n",
++02566                                             t);
++02567                                 DWC_WARN("USB_PORT_FEAT_TEST %d\n", t);
++02568                                 if (t < 6) {
++02569                                         hprt0.d32 = dwc_otg_read_hprt0(core_if);
++02570                                         hprt0.b.prttstctl = t;
++02571                                         DWC_WRITE_REG32(core_if->host_if->hprt0,
++02572                                                         hprt0.d32);
++02573                                 } else {
++02574                                         /* Setup global vars with reg addresses (quick and
++02575                                          * dirty hack, should be cleaned up)
++02576                                          */
++02577                                         global_regs = core_if->core_global_regs;
++02578                                         hc_global_regs =
++02579                                             core_if->host_if->host_global_regs;
++02580                                         hc_regs =
++02581                                             (dwc_otg_hc_regs_t *) ((char *)
++02582                                                                    global_regs +
++02583                                                                    0x500);
++02584                                         data_fifo =
++02585                                             (uint32_t *) ((char *)global_regs +
++02586                                                           0x1000);
++02587 
++02588                                         if (t == 6) {   /* HS_HOST_PORT_SUSPEND_RESUME */
++02589                                                 /* Save current interrupt mask */
++02590                                                 gintmsk.d32 =
++02591                                                     DWC_READ_REG32
++02592                                                     (&global_regs->gintmsk);
++02593 
++02594                                                 /* Disable all interrupts while we muck with
++02595                                                  * the hardware directly
++02596                                                  */
++02597                                                 DWC_WRITE_REG32(&global_regs->gintmsk, 0);
++02598 
++02599                                                 /* 15 second delay per the test spec */
++02600                                                 dwc_mdelay(15000);
++02601 
++02602                                                 /* Drive suspend on the root port */
++02603                                                 hprt0.d32 =
++02604                                                     dwc_otg_read_hprt0(core_if);
++02605                                                 hprt0.b.prtsusp = 1;
++02606                                                 hprt0.b.prtres = 0;
++02607                                                 DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
++02608 
++02609                                                 /* 15 second delay per the test spec */
++02610                                                 dwc_mdelay(15000);
++02611 
++02612                                                 /* Drive resume on the root port */
++02613                                                 hprt0.d32 =
++02614                                                     dwc_otg_read_hprt0(core_if);
++02615                                                 hprt0.b.prtsusp = 0;
++02616                                                 hprt0.b.prtres = 1;
++02617                                                 DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
++02618                                                 dwc_mdelay(100);
++02619 
++02620                                                 /* Clear the resume bit */
++02621                                                 hprt0.b.prtres = 0;
++02622                                                 DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
++02623 
++02624                                                 /* Restore interrupts */
++02625                                                 DWC_WRITE_REG32(&global_regs->gintmsk, gintmsk.d32);
++02626                                         } else if (t == 7) {    /* SINGLE_STEP_GET_DEVICE_DESCRIPTOR setup */
++02627                                                 /* Save current interrupt mask */
++02628                                                 gintmsk.d32 =
++02629                                                     DWC_READ_REG32
++02630                                                     (&global_regs->gintmsk);
++02631 
++02632                                                 /* Disable all interrupts while we muck with
++02633                                                  * the hardware directly
++02634                                                  */
++02635                                                 DWC_WRITE_REG32(&global_regs->gintmsk, 0);
++02636 
++02637                                                 /* 15 second delay per the test spec */
++02638                                                 dwc_mdelay(15000);
++02639 
++02640                                                 /* Send the Setup packet */
++02641                                                 do_setup();
++02642 
++02643                                                 /* 15 second delay so nothing else happens for awhile */
++02644                                                 dwc_mdelay(15000);
++02645 
++02646                                                 /* Restore interrupts */
++02647                                                 DWC_WRITE_REG32(&global_regs->gintmsk, gintmsk.d32);
++02648                                         } else if (t == 8) {    /* SINGLE_STEP_GET_DEVICE_DESCRIPTOR execute */
++02649                                                 /* Save current interrupt mask */
++02650                                                 gintmsk.d32 =
++02651                                                     DWC_READ_REG32
++02652                                                     (&global_regs->gintmsk);
++02653 
++02654                                                 /* Disable all interrupts while we muck with
++02655                                                  * the hardware directly
++02656                                                  */
++02657                                                 DWC_WRITE_REG32(&global_regs->gintmsk, 0);
++02658 
++02659                                                 /* Send the Setup packet */
++02660                                                 do_setup();
++02661 
++02662                                                 /* 15 second delay so nothing else happens for awhile */
++02663                                                 dwc_mdelay(15000);
++02664 
++02665                                                 /* Send the In and Ack packets */
++02666                                                 do_in_ack();
++02667 
++02668                                                 /* 15 second delay so nothing else happens for awhile */
++02669                                                 dwc_mdelay(15000);
++02670 
++02671                                                 /* Restore interrupts */
++02672                                                 DWC_WRITE_REG32(&global_regs->gintmsk, gintmsk.d32);
++02673                                         }
++02674                                 }
++02675                                 break;
++02676                         }
++02677 #endif /* DWC_HS_ELECT_TST */
++02678 
++02679                 case UHF_PORT_INDICATOR:
++02680                         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
++02681                                     "SetPortFeature - USB_PORT_FEAT_INDICATOR\n");
++02682                         /* Not supported */
++02683                         break;
++02684                 default:
++02685                         retval = -DWC_E_INVALID;
++02686                         DWC_ERROR("DWC OTG HCD - "
++02687                                   "SetPortFeature request %xh "
++02688                                   "unknown or unsupported\n", wValue);
++02689                         break;
++02690                 }
++02691                 break;
++02692 #ifdef CONFIG_USB_DWC_OTG_LPM
++02693         case UCR_SET_AND_TEST_PORT_FEATURE:
++02694                 if (wValue != UHF_PORT_L1) {
++02695                         goto error;
++02696                 }
++02697                 {
++02698                         int portnum, hird, devaddr, remwake;
++02699                         glpmcfg_data_t lpmcfg;
++02700                         uint32_t time_usecs;
++02701                         gintsts_data_t gintsts;
++02702                         gintmsk_data_t gintmsk;
++02703 
++02704                         if (!dwc_otg_get_param_lpm_enable(core_if)) {
++02705                                 goto error;
++02706                         }
++02707                         if (wValue != UHF_PORT_L1 || wLength != 1) {
++02708                                 goto error;
++02709                         }
++02710                         /* Check if the port currently is in SLEEP state */
++02711                         lpmcfg.d32 =
++02712                             DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
++02713                         if (lpmcfg.b.prt_sleep_sts) {
++02714                                 DWC_INFO("Port is already in sleep mode\n");
++02715                                 buf[0] = 0;     /* Return success */
++02716                                 break;
++02717                         }
++02718 
++02719                         portnum = wIndex & 0xf;
++02720                         hird = (wIndex >> 4) & 0xf;
++02721                         devaddr = (wIndex >> 8) & 0x7f;
++02722                         remwake = (wIndex >> 15);
++02723 
++02724                         if (portnum != 1) {
++02725                                 retval = -DWC_E_INVALID;
++02726                                 DWC_WARN
++02727                                     ("Wrong port number(%d) in SetandTestPortFeature request\n",
++02728                                      portnum);
++02729                                 break;
++02730                         }
++02731 
++02732                         DWC_PRINTF
++02733                             ("SetandTestPortFeature request: portnum = %d, hird = %d, devaddr = %d, rewake = %d\n",
++02734                              portnum, hird, devaddr, remwake);
++02735                         /* Disable LPM interrupt */
++02736                         gintmsk.d32 = 0;
++02737                         gintmsk.b.lpmtranrcvd = 1;
++02738                         DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk,
++02739                                          gintmsk.d32, 0);
++02740 
++02741                         if (dwc_otg_hcd_send_lpm
++02742                             (dwc_otg_hcd, devaddr, hird, remwake)) {
++02743                                 retval = -DWC_E_INVALID;
++02744                                 break;
++02745                         }
++02746 
++02747                         time_usecs = 10 * (lpmcfg.b.retry_count + 1);
++02748                         /* We will consider timeout if time_usecs microseconds pass,
++02749                          * and we don't receive LPM transaction status.
++02750                          * After receiving non-error responce(ACK/NYET/STALL) from device,
++02751                          *  core will set lpmtranrcvd bit.
++02752                          */
++02753                         do {
++02754                                 gintsts.d32 =
++02755                                     DWC_READ_REG32(&core_if->core_global_regs->gintsts);
++02756                                 if (gintsts.b.lpmtranrcvd) {
++02757                                         break;
++02758                                 }
++02759                                 dwc_udelay(1);
++02760                         } while (--time_usecs);
++02761                         /* lpm_int bit will be cleared in LPM interrupt handler */
++02762 
++02763                         /* Now fill status
++02764                          * 0x00 - Success
++02765                          * 0x10 - NYET
++02766                          * 0x11 - Timeout
++02767                          */
++02768                         if (!gintsts.b.lpmtranrcvd) {
++02769                                 buf[0] = 0x3;   /* Completion code is Timeout */
++02770                                 dwc_otg_hcd_free_hc_from_lpm(dwc_otg_hcd);
++02771                         } else {
++02772                                 lpmcfg.d32 =
++02773                                     DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
++02774                                 if (lpmcfg.b.lpm_resp == 0x3) {
++02775                                         /* ACK responce from the device */
++02776                                         buf[0] = 0x00;  /* Success */
++02777                                 } else if (lpmcfg.b.lpm_resp == 0x2) {
++02778                                         /* NYET responce from the device */
++02779                                         buf[0] = 0x2;
++02780                                 } else {
++02781                                         /* Otherwise responce with Timeout */
++02782                                         buf[0] = 0x3;
++02783                                 }
++02784                         }
++02785                         DWC_PRINTF("Device responce to LPM trans is %x\n",
++02786                                    lpmcfg.b.lpm_resp);
++02787                         DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, 0,
++02788                                          gintmsk.d32);
++02789 
++02790                         break;
++02791                 }
++02792 #endif /* CONFIG_USB_DWC_OTG_LPM */
++02793         default:
++02794 error:
++02795                 retval = -DWC_E_INVALID;
++02796                 DWC_WARN("DWC OTG HCD - "
++02797                          "Unknown hub control request type or invalid typeReq: %xh wIndex: %xh wValue: %xh\n",
++02798                          typeReq, wIndex, wValue);
++02799                 break;
++02800         }
++02801 
++02802         return retval;
++02803 }
++02804 
++02805 #ifdef CONFIG_USB_DWC_OTG_LPM
++02806 
++02807 int dwc_otg_hcd_get_hc_for_lpm_tran(dwc_otg_hcd_t * hcd, uint8_t devaddr)
++02808 {
++02809         dwc_otg_core_if_t *core_if = hcd->core_if;
++02810         dwc_hc_t *hc;
++02811         hcchar_data_t hcchar;
++02812         gintmsk_data_t gintmsk = {.d32 = 0 };
++02813 
++02814         if (DWC_CIRCLEQ_EMPTY(&hcd->free_hc_list)) {
++02815                 DWC_PRINTF("No free channel to select for LPM transaction\n");
++02816                 return -1;
++02817         }
++02818 
++02819         hc = DWC_CIRCLEQ_FIRST(&hcd->free_hc_list);
++02820 
++02821         /* Mask host channel interrupts. */
++02822         gintmsk.b.hcintr = 1;
++02823         DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, gintmsk.d32, 0);
++02824 
++02825         /* Fill fields that core needs for LPM transaction */
++02826         hcchar.b.devaddr = devaddr;
++02827         hcchar.b.epnum = 0;
++02828         hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
++02829         hcchar.b.mps = 64;
++02830         hcchar.b.lspddev = (hc->speed == DWC_OTG_EP_SPEED_LOW);
++02831         hcchar.b.epdir = 0;     /* OUT */
++02832         DWC_WRITE_REG32(&core_if->host_if->hc_regs[hc->hc_num]->hcchar,
++02833                         hcchar.d32);
++02834 
++02835         /* Remove the host channel from the free list. */
++02836         DWC_CIRCLEQ_REMOVE_INIT(&hcd->free_hc_list, hc, hc_list_entry);
++02837 
++02838         DWC_PRINTF("hcnum = %d devaddr = %d\n", hc->hc_num, devaddr);
++02839 
++02840         return hc->hc_num;
++02841 }
++02842 
++02844 void dwc_otg_hcd_free_hc_from_lpm(dwc_otg_hcd_t * hcd)
++02845 {
++02846         dwc_hc_t *hc;
++02847         glpmcfg_data_t lpmcfg;
++02848         uint8_t hc_num;
++02849 
++02850         lpmcfg.d32 = DWC_READ_REG32(&hcd->core_if->core_global_regs->glpmcfg);
++02851         hc_num = lpmcfg.b.lpm_chan_index;
++02852 
++02853         hc = hcd->hc_ptr_array[hc_num];
++02854 
++02855         DWC_PRINTF("Freeing channel %d after LPM\n", hc_num);
++02856         /* Return host channel to free list */
++02857         DWC_CIRCLEQ_INSERT_TAIL(&hcd->free_hc_list, hc, hc_list_entry);
++02858 }
++02859 
++02860 int dwc_otg_hcd_send_lpm(dwc_otg_hcd_t * hcd, uint8_t devaddr, uint8_t hird,
++02861                          uint8_t bRemoteWake)
++02862 {
++02863         glpmcfg_data_t lpmcfg;
++02864         pcgcctl_data_t pcgcctl = {.d32 = 0 };
++02865         int channel;
++02866 
++02867         channel = dwc_otg_hcd_get_hc_for_lpm_tran(hcd, devaddr);
++02868         if (channel < 0) {
++02869                 return channel;
++02870         }
++02871 
++02872         pcgcctl.b.enbl_sleep_gating = 1;
++02873         DWC_MODIFY_REG32(hcd->core_if->pcgcctl, 0, pcgcctl.d32);
++02874 
++02875         /* Read LPM config register */
++02876         lpmcfg.d32 = DWC_READ_REG32(&hcd->core_if->core_global_regs->glpmcfg);
++02877 
++02878         /* Program LPM transaction fields */
++02879         lpmcfg.b.rem_wkup_en = bRemoteWake;
++02880         lpmcfg.b.hird = hird;
++02881         lpmcfg.b.hird_thres = 0x1c;
++02882         lpmcfg.b.lpm_chan_index = channel;
++02883         lpmcfg.b.en_utmi_sleep = 1;
++02884         /* Program LPM config register */
++02885         DWC_WRITE_REG32(&hcd->core_if->core_global_regs->glpmcfg, lpmcfg.d32);
++02886 
++02887         /* Send LPM transaction */
++02888         lpmcfg.b.send_lpm = 1;
++02889         DWC_WRITE_REG32(&hcd->core_if->core_global_regs->glpmcfg, lpmcfg.d32);
++02890 
++02891         return 0;
++02892 }
++02893 
++02894 #endif /* CONFIG_USB_DWC_OTG_LPM */
++02895 
++02896 int dwc_otg_hcd_is_status_changed(dwc_otg_hcd_t * hcd, int port)
++02897 {
++02898         int retval;
++02899 
++02900         if (port != 1) {
++02901                 return -DWC_E_INVALID;
++02902         }
++02903 
++02904         retval = (hcd->flags.b.port_connect_status_change ||
++02905                   hcd->flags.b.port_reset_change ||
++02906                   hcd->flags.b.port_enable_change ||
++02907                   hcd->flags.b.port_suspend_change ||
++02908                   hcd->flags.b.port_over_current_change);
++02909 #ifdef DEBUG
++02910         if (retval) {
++02911                 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB STATUS DATA:"
++02912                             " Root port status changed\n");
++02913                 DWC_DEBUGPL(DBG_HCDV, "  port_connect_status_change: %d\n",
++02914                             hcd->flags.b.port_connect_status_change);
++02915                 DWC_DEBUGPL(DBG_HCDV, "  port_reset_change: %d\n",
++02916                             hcd->flags.b.port_reset_change);
++02917                 DWC_DEBUGPL(DBG_HCDV, "  port_enable_change: %d\n",
++02918                             hcd->flags.b.port_enable_change);
++02919                 DWC_DEBUGPL(DBG_HCDV, "  port_suspend_change: %d\n",
++02920                             hcd->flags.b.port_suspend_change);
++02921                 DWC_DEBUGPL(DBG_HCDV, "  port_over_current_change: %d\n",
++02922                             hcd->flags.b.port_over_current_change);
++02923         }
++02924 #endif
++02925         return retval;
++02926 }
++02927 
++02928 int dwc_otg_hcd_get_frame_number(dwc_otg_hcd_t * dwc_otg_hcd)
++02929 {
++02930         hfnum_data_t hfnum;
++02931         hfnum.d32 =
++02932             DWC_READ_REG32(&dwc_otg_hcd->core_if->host_if->host_global_regs->
++02933                            hfnum);
++02934 
++02935 #ifdef DEBUG_SOF
++02936         DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD GET FRAME NUMBER %d\n",
++02937                     hfnum.b.frnum);
++02938 #endif
++02939         return hfnum.b.frnum;
++02940 }
++02941 
++02942 int dwc_otg_hcd_start(dwc_otg_hcd_t * hcd,
++02943                       struct dwc_otg_hcd_function_ops *fops)
++02944 {
++02945         int retval = 0;
++02946 
++02947         hcd->fops = fops;
++02948         if (!dwc_otg_is_device_mode(hcd->core_if) && 
++02949                 (!hcd->core_if->adp_enable || hcd->core_if->adp.adp_started)) {
++02950                 dwc_otg_hcd_reinit(hcd);
++02951         } else {
++02952                 retval = -DWC_E_NO_DEVICE;
++02953         }
++02954 
++02955         return retval;
++02956 }
++02957 
++02958 void *dwc_otg_hcd_get_priv_data(dwc_otg_hcd_t * hcd)
++02959 {
++02960         return hcd->priv;
++02961 }
++02962 
++02963 void dwc_otg_hcd_set_priv_data(dwc_otg_hcd_t * hcd, void *priv_data)
++02964 {
++02965         hcd->priv = priv_data;
++02966 }
++02967 
++02968 uint32_t dwc_otg_hcd_otg_port(dwc_otg_hcd_t * hcd)
++02969 {
++02970         return hcd->otg_port;
++02971 }
++02972 
++02973 uint32_t dwc_otg_hcd_is_b_host(dwc_otg_hcd_t * hcd)
++02974 {
++02975         uint32_t is_b_host;
++02976         if (hcd->core_if->op_state == B_HOST) {
++02977                 is_b_host = 1;
++02978         } else {
++02979                 is_b_host = 0;
++02980         }
++02981 
++02982         return is_b_host;
++02983 }
++02984 
++02985 dwc_otg_hcd_urb_t *dwc_otg_hcd_urb_alloc(dwc_otg_hcd_t * hcd,
++02986                                          int iso_desc_count, int atomic_alloc)
++02987 {
++02988         dwc_otg_hcd_urb_t *dwc_otg_urb;
++02989         uint32_t size;
++02990 
++02991         size =
++02992             sizeof(*dwc_otg_urb) +
++02993             iso_desc_count * sizeof(struct dwc_otg_hcd_iso_packet_desc);
++02994         if (atomic_alloc)
++02995                 dwc_otg_urb = DWC_ALLOC_ATOMIC(size);
++02996         else
++02997                 dwc_otg_urb = DWC_ALLOC(size);
++02998 
++02999         dwc_otg_urb->packet_count = iso_desc_count;
++03000 
++03001         return dwc_otg_urb;
++03002 }
++03003 
++03004 void dwc_otg_hcd_urb_set_pipeinfo(dwc_otg_hcd_urb_t * dwc_otg_urb,
++03005                                   uint8_t dev_addr, uint8_t ep_num,
++03006                                   uint8_t ep_type, uint8_t ep_dir, uint16_t mps)
++03007 {
++03008         dwc_otg_hcd_fill_pipe(&dwc_otg_urb->pipe_info, dev_addr, ep_num,
++03009                               ep_type, ep_dir, mps);
++03010 #if 0
++03011         DWC_PRINTF
++03012             ("addr = %d, ep_num = %d, ep_dir = 0x%x, ep_type = 0x%x, mps = %d\n",
++03013              dev_addr, ep_num, ep_dir, ep_type, mps);
++03014 #endif
++03015 }
++03016 
++03017 void dwc_otg_hcd_urb_set_params(dwc_otg_hcd_urb_t * dwc_otg_urb,
++03018                                 void *urb_handle, void *buf, dwc_dma_t dma,
++03019                                 uint32_t buflen, void *setup_packet,
++03020                                 dwc_dma_t setup_dma, uint32_t flags,
++03021                                 uint16_t interval)
++03022 {
++03023         dwc_otg_urb->priv = urb_handle;
++03024         dwc_otg_urb->buf = buf;
++03025         dwc_otg_urb->dma = dma;
++03026         dwc_otg_urb->length = buflen;
++03027         dwc_otg_urb->setup_packet = setup_packet;
++03028         dwc_otg_urb->setup_dma = setup_dma;
++03029         dwc_otg_urb->flags = flags;
++03030         dwc_otg_urb->interval = interval;
++03031         dwc_otg_urb->status = -DWC_E_IN_PROGRESS;
++03032 }
++03033 
++03034 uint32_t dwc_otg_hcd_urb_get_status(dwc_otg_hcd_urb_t * dwc_otg_urb)
++03035 {
++03036         return dwc_otg_urb->status;
++03037 }
++03038 
++03039 uint32_t dwc_otg_hcd_urb_get_actual_length(dwc_otg_hcd_urb_t * dwc_otg_urb)
++03040 {
++03041         return dwc_otg_urb->actual_length;
++03042 }
++03043 
++03044 uint32_t dwc_otg_hcd_urb_get_error_count(dwc_otg_hcd_urb_t * dwc_otg_urb)
++03045 {
++03046         return dwc_otg_urb->error_count;
++03047 }
++03048 
++03049 void dwc_otg_hcd_urb_set_iso_desc_params(dwc_otg_hcd_urb_t * dwc_otg_urb,
++03050                                          int desc_num, uint32_t offset,
++03051                                          uint32_t length)
++03052 {
++03053         dwc_otg_urb->iso_descs[desc_num].offset = offset;
++03054         dwc_otg_urb->iso_descs[desc_num].length = length;
++03055 }
++03056 
++03057 uint32_t dwc_otg_hcd_urb_get_iso_desc_status(dwc_otg_hcd_urb_t * dwc_otg_urb,
++03058                                              int desc_num)
++03059 {
++03060         return dwc_otg_urb->iso_descs[desc_num].status;
++03061 }
++03062 
++03063 uint32_t dwc_otg_hcd_urb_get_iso_desc_actual_length(dwc_otg_hcd_urb_t *
++03064                                                     dwc_otg_urb, int desc_num)
++03065 {
++03066         return dwc_otg_urb->iso_descs[desc_num].actual_length;
++03067 }
++03068 
++03069 int dwc_otg_hcd_is_bandwidth_allocated(dwc_otg_hcd_t * hcd, void *ep_handle)
++03070 {
++03071         int allocated = 0;
++03072         dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle;
++03073 
++03074         if (qh) {
++03075                 if (!DWC_LIST_EMPTY(&qh->qh_list_entry)) {
++03076                         allocated = 1;
++03077                 }
++03078         }
++03079         return allocated;
++03080 }
++03081 
++03082 int dwc_otg_hcd_is_bandwidth_freed(dwc_otg_hcd_t * hcd, void *ep_handle)
++03083 {
++03084         dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle;
++03085         int freed = 0;
++03086         DWC_ASSERT(qh, "qh is not allocated\n");
++03087 
++03088         if (DWC_LIST_EMPTY(&qh->qh_list_entry)) {
++03089                 freed = 1;
++03090         }
++03091 
++03092         return freed;
++03093 }
++03094 
++03095 uint8_t dwc_otg_hcd_get_ep_bandwidth(dwc_otg_hcd_t * hcd, void *ep_handle)
++03096 {
++03097         dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle;
++03098         DWC_ASSERT(qh, "qh is not allocated\n");
++03099         return qh->usecs;
++03100 }
++03101 
++03102 void dwc_otg_hcd_dump_state(dwc_otg_hcd_t * hcd)
++03103 {
++03104 #ifdef DEBUG
++03105         int num_channels;
++03106         int i;
++03107         gnptxsts_data_t np_tx_status;
++03108         hptxsts_data_t p_tx_status;
++03109 
++03110         num_channels = hcd->core_if->core_params->host_channels;
++03111         DWC_PRINTF("\n");
++03112         DWC_PRINTF
++03113             ("************************************************************\n");
++03114         DWC_PRINTF("HCD State:\n");
++03115         DWC_PRINTF("  Num channels: %d\n", num_channels);
++03116         for (i = 0; i < num_channels; i++) {
++03117                 dwc_hc_t *hc = hcd->hc_ptr_array[i];
++03118                 DWC_PRINTF("  Channel %d:\n", i);
++03119                 DWC_PRINTF("    dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
++03120                            hc->dev_addr, hc->ep_num, hc->ep_is_in);
++03121                 DWC_PRINTF("    speed: %d\n", hc->speed);
++03122                 DWC_PRINTF("    ep_type: %d\n", hc->ep_type);
++03123                 DWC_PRINTF("    max_packet: %d\n", hc->max_packet);
++03124                 DWC_PRINTF("    data_pid_start: %d\n", hc->data_pid_start);
++03125                 DWC_PRINTF("    multi_count: %d\n", hc->multi_count);
++03126                 DWC_PRINTF("    xfer_started: %d\n", hc->xfer_started);
++03127                 DWC_PRINTF("    xfer_buff: %p\n", hc->xfer_buff);
++03128                 DWC_PRINTF("    xfer_len: %d\n", hc->xfer_len);
++03129                 DWC_PRINTF("    xfer_count: %d\n", hc->xfer_count);
++03130                 DWC_PRINTF("    halt_on_queue: %d\n", hc->halt_on_queue);
++03131                 DWC_PRINTF("    halt_pending: %d\n", hc->halt_pending);
++03132                 DWC_PRINTF("    halt_status: %d\n", hc->halt_status);
++03133                 DWC_PRINTF("    do_split: %d\n", hc->do_split);
++03134                 DWC_PRINTF("    complete_split: %d\n", hc->complete_split);
++03135                 DWC_PRINTF("    hub_addr: %d\n", hc->hub_addr);
++03136                 DWC_PRINTF("    port_addr: %d\n", hc->port_addr);
++03137                 DWC_PRINTF("    xact_pos: %d\n", hc->xact_pos);
++03138                 DWC_PRINTF("    requests: %d\n", hc->requests);
++03139                 DWC_PRINTF("    qh: %p\n", hc->qh);
++03140                 if (hc->xfer_started) {
++03141                         hfnum_data_t hfnum;
++03142                         hcchar_data_t hcchar;
++03143                         hctsiz_data_t hctsiz;
++03144                         hcint_data_t hcint;
++03145                         hcintmsk_data_t hcintmsk;
++03146                         hfnum.d32 =
++03147                             DWC_READ_REG32(&hcd->core_if->
++03148                                            host_if->host_global_regs->hfnum);
++03149                         hcchar.d32 =
++03150                             DWC_READ_REG32(&hcd->core_if->host_if->
++03151                                            hc_regs[i]->hcchar);
++03152                         hctsiz.d32 =
++03153                             DWC_READ_REG32(&hcd->core_if->host_if->
++03154                                            hc_regs[i]->hctsiz);
++03155                         hcint.d32 =
++03156                             DWC_READ_REG32(&hcd->core_if->host_if->
++03157                                            hc_regs[i]->hcint);
++03158                         hcintmsk.d32 =
++03159                             DWC_READ_REG32(&hcd->core_if->host_if->
++03160                                            hc_regs[i]->hcintmsk);
++03161                         DWC_PRINTF("    hfnum: 0x%08x\n", hfnum.d32);
++03162                         DWC_PRINTF("    hcchar: 0x%08x\n", hcchar.d32);
++03163                         DWC_PRINTF("    hctsiz: 0x%08x\n", hctsiz.d32);
++03164                         DWC_PRINTF("    hcint: 0x%08x\n", hcint.d32);
++03165                         DWC_PRINTF("    hcintmsk: 0x%08x\n", hcintmsk.d32);
++03166                 }
++03167                 if (hc->xfer_started && hc->qh) {
++03168                         dwc_otg_qtd_t *qtd;
++03169                         dwc_otg_hcd_urb_t *urb;
++03170                         
++03171                         DWC_CIRCLEQ_FOREACH(qtd, &hc->qh->qtd_list, qtd_list_entry) {
++03172                                 if (!qtd->in_process)
++03173                                         break;
++03174                                 
++03175                                 urb = qtd->urb;
++03176                         DWC_PRINTF("    URB Info:\n");
++03177                         DWC_PRINTF("      qtd: %p, urb: %p\n", qtd, urb);
++03178                         if (urb) {
++03179                                 DWC_PRINTF("      Dev: %d, EP: %d %s\n",
++03180                                            dwc_otg_hcd_get_dev_addr(&urb->
++03181                                                                     pipe_info),
++03182                                            dwc_otg_hcd_get_ep_num(&urb->
++03183                                                                   pipe_info),
++03184                                            dwc_otg_hcd_is_pipe_in(&urb->
++03185                                                                   pipe_info) ?
++03186                                            "IN" : "OUT");
++03187                                 DWC_PRINTF("      Max packet size: %d\n",
++03188                                            dwc_otg_hcd_get_mps(&urb->
++03189                                                                pipe_info));
++03190                                 DWC_PRINTF("      transfer_buffer: %p\n",
++03191                                            urb->buf);
++03192                                 DWC_PRINTF("      transfer_dma: %p\n",
++03193                                            (void *)urb->dma);
++03194                                 DWC_PRINTF("      transfer_buffer_length: %d\n",
++03195                                            urb->length);
++03196                                         DWC_PRINTF("      actual_length: %d\n",
++03197                                                    urb->actual_length);
++03198                                 }
++03199                         }
++03200                 }
++03201         }
++03202         DWC_PRINTF("  non_periodic_channels: %d\n", hcd->non_periodic_channels);
++03203         DWC_PRINTF("  periodic_channels: %d\n", hcd->periodic_channels);
++03204         DWC_PRINTF("  periodic_usecs: %d\n", hcd->periodic_usecs);
++03205         np_tx_status.d32 =
++03206             DWC_READ_REG32(&hcd->core_if->core_global_regs->gnptxsts);
++03207         DWC_PRINTF("  NP Tx Req Queue Space Avail: %d\n",
++03208                    np_tx_status.b.nptxqspcavail);
++03209         DWC_PRINTF("  NP Tx FIFO Space Avail: %d\n",
++03210                    np_tx_status.b.nptxfspcavail);
++03211         p_tx_status.d32 =
++03212             DWC_READ_REG32(&hcd->core_if->host_if->host_global_regs->hptxsts);
++03213         DWC_PRINTF("  P Tx Req Queue Space Avail: %d\n",
++03214                    p_tx_status.b.ptxqspcavail);
++03215         DWC_PRINTF("  P Tx FIFO Space Avail: %d\n", p_tx_status.b.ptxfspcavail);
++03216         dwc_otg_hcd_dump_frrem(hcd);
++03217         dwc_otg_dump_global_registers(hcd->core_if);
++03218         dwc_otg_dump_host_registers(hcd->core_if);
++03219         DWC_PRINTF
++03220             ("************************************************************\n");
++03221         DWC_PRINTF("\n");
++03222 #endif
++03223 }
++03224 
++03225 #ifdef DEBUG
++03226 void dwc_print_setup_data(uint8_t * setup)
++03227 {
++03228         int i;
++03229         if (CHK_DEBUG_LEVEL(DBG_HCD)) {
++03230                 DWC_PRINTF("Setup Data = MSB ");
++03231                 for (i = 7; i >= 0; i--)
++03232                         DWC_PRINTF("%02x ", setup[i]);
++03233                 DWC_PRINTF("\n");
++03234                 DWC_PRINTF("  bmRequestType Tranfer = %s\n",
++03235                            (setup[0] & 0x80) ? "Device-to-Host" :
++03236                            "Host-to-Device");
++03237                 DWC_PRINTF("  bmRequestType Type = ");
++03238                 switch ((setup[0] & 0x60) >> 5) {
++03239                 case 0:
++03240                         DWC_PRINTF("Standard\n");
++03241                         break;
++03242                 case 1:
++03243                         DWC_PRINTF("Class\n");
++03244                         break;
++03245                 case 2:
++03246                         DWC_PRINTF("Vendor\n");
++03247                         break;
++03248                 case 3:
++03249                         DWC_PRINTF("Reserved\n");
++03250                         break;
++03251                 }
++03252                 DWC_PRINTF("  bmRequestType Recipient = ");
++03253                 switch (setup[0] & 0x1f) {
++03254                 case 0:
++03255                         DWC_PRINTF("Device\n");
++03256                         break;
++03257                 case 1:
++03258                         DWC_PRINTF("Interface\n");
++03259                         break;
++03260                 case 2:
++03261                         DWC_PRINTF("Endpoint\n");
++03262                         break;
++03263                 case 3:
++03264                         DWC_PRINTF("Other\n");
++03265                         break;
++03266                 default:
++03267                         DWC_PRINTF("Reserved\n");
++03268                         break;
++03269                 }
++03270                 DWC_PRINTF("  bRequest = 0x%0x\n", setup[1]);
++03271                 DWC_PRINTF("  wValue = 0x%0x\n", *((uint16_t *) & setup[2]));
++03272                 DWC_PRINTF("  wIndex = 0x%0x\n", *((uint16_t *) & setup[4]));
++03273                 DWC_PRINTF("  wLength = 0x%0x\n\n", *((uint16_t *) & setup[6]));
++03274         }
++03275 }
++03276 #endif
++03277 
++03278 void dwc_otg_hcd_dump_frrem(dwc_otg_hcd_t * hcd)
++03279 {
++03280 #if 0
++03281         DWC_PRINTF("Frame remaining at SOF:\n");
++03282         DWC_PRINTF("  samples %u, accum %llu, avg %llu\n",
++03283                    hcd->frrem_samples, hcd->frrem_accum,
++03284                    (hcd->frrem_samples > 0) ?
++03285                    hcd->frrem_accum / hcd->frrem_samples : 0);
++03286 
++03287         DWC_PRINTF("\n");
++03288         DWC_PRINTF("Frame remaining at start_transfer (uframe 7):\n");
++03289         DWC_PRINTF("  samples %u, accum %llu, avg %llu\n",
++03290                    hcd->core_if->hfnum_7_samples,
++03291                    hcd->core_if->hfnum_7_frrem_accum,
++03292                    (hcd->core_if->hfnum_7_samples >
++03293                     0) ? hcd->core_if->hfnum_7_frrem_accum /
++03294                    hcd->core_if->hfnum_7_samples : 0);
++03295         DWC_PRINTF("Frame remaining at start_transfer (uframe 0):\n");
++03296         DWC_PRINTF("  samples %u, accum %llu, avg %llu\n",
++03297                    hcd->core_if->hfnum_0_samples,
++03298                    hcd->core_if->hfnum_0_frrem_accum,
++03299                    (hcd->core_if->hfnum_0_samples >
++03300                     0) ? hcd->core_if->hfnum_0_frrem_accum /
++03301                    hcd->core_if->hfnum_0_samples : 0);
++03302         DWC_PRINTF("Frame remaining at start_transfer (uframe 1-6):\n");
++03303         DWC_PRINTF("  samples %u, accum %llu, avg %llu\n",
++03304                    hcd->core_if->hfnum_other_samples,
++03305                    hcd->core_if->hfnum_other_frrem_accum,
++03306                    (hcd->core_if->hfnum_other_samples >
++03307                     0) ? hcd->core_if->hfnum_other_frrem_accum /
++03308                    hcd->core_if->hfnum_other_samples : 0);
++03309 
++03310         DWC_PRINTF("\n");
++03311         DWC_PRINTF("Frame remaining at sample point A (uframe 7):\n");
++03312         DWC_PRINTF("  samples %u, accum %llu, avg %llu\n",
++03313                    hcd->hfnum_7_samples_a, hcd->hfnum_7_frrem_accum_a,
++03314                    (hcd->hfnum_7_samples_a > 0) ?
++03315                    hcd->hfnum_7_frrem_accum_a / hcd->hfnum_7_samples_a : 0);
++03316         DWC_PRINTF("Frame remaining at sample point A (uframe 0):\n");
++03317         DWC_PRINTF("  samples %u, accum %llu, avg %llu\n",
++03318                    hcd->hfnum_0_samples_a, hcd->hfnum_0_frrem_accum_a,
++03319                    (hcd->hfnum_0_samples_a > 0) ?
++03320                    hcd->hfnum_0_frrem_accum_a / hcd->hfnum_0_samples_a : 0);
++03321         DWC_PRINTF("Frame remaining at sample point A (uframe 1-6):\n");
++03322         DWC_PRINTF("  samples %u, accum %llu, avg %llu\n",
++03323                    hcd->hfnum_other_samples_a, hcd->hfnum_other_frrem_accum_a,
++03324                    (hcd->hfnum_other_samples_a > 0) ?
++03325                    hcd->hfnum_other_frrem_accum_a /
++03326                    hcd->hfnum_other_samples_a : 0);
++03327 
++03328         DWC_PRINTF("\n");
++03329         DWC_PRINTF("Frame remaining at sample point B (uframe 7):\n");
++03330         DWC_PRINTF("  samples %u, accum %llu, avg %llu\n",
++03331                    hcd->hfnum_7_samples_b, hcd->hfnum_7_frrem_accum_b,
++03332                    (hcd->hfnum_7_samples_b > 0) ?
++03333                    hcd->hfnum_7_frrem_accum_b / hcd->hfnum_7_samples_b : 0);
++03334         DWC_PRINTF("Frame remaining at sample point B (uframe 0):\n");
++03335         DWC_PRINTF("  samples %u, accum %llu, avg %llu\n",
++03336                    hcd->hfnum_0_samples_b, hcd->hfnum_0_frrem_accum_b,
++03337                    (hcd->hfnum_0_samples_b > 0) ?
++03338                    hcd->hfnum_0_frrem_accum_b / hcd->hfnum_0_samples_b : 0);
++03339         DWC_PRINTF("Frame remaining at sample point B (uframe 1-6):\n");
++03340         DWC_PRINTF("  samples %u, accum %llu, avg %llu\n",
++03341                    hcd->hfnum_other_samples_b, hcd->hfnum_other_frrem_accum_b,
++03342                    (hcd->hfnum_other_samples_b > 0) ?
++03343                    hcd->hfnum_other_frrem_accum_b /
++03344                    hcd->hfnum_other_samples_b : 0);
++03345 #endif
++03346 }
++03347 
++03348 #endif /* DWC_DEVICE_ONLY */
++
    Generated on Thu Oct 27 03:56:37 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
    ++doxygen 1.3.9.1
    + + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__hcd_8c.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/dwc__otg__hcd_8c.html 2013-07-26 19:31:21.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__hcd_8c.html 2013-07-26 19:34:41.000000000 +0000 +@@ -2,342 +2,385 @@ + + DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_hcd.c File Reference + +- + +- +-
    +-
    +-
    +-
    ++ ++
    Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
    +

    dwc_otg_hcd.c File Reference

    This file implements HCD Core. More... +

    +-#include "dwc_otg_hcd.h"
    +-#include "dwc_otg_regs.h"
    ++#include "dwc_otg_hcd.h"
    ++#include "dwc_otg_regs.h"
    + +

    + Go to the source code of this file. + + +- ++ + + +- ++ + +- +- ++ ++ + +- +- ++ ++ + +- ++ + +- ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ ++ ++ + + +- ++ ++ ++ + +- ++ ++ + + +- ++ + +- +- ++ ++ + +- +- ++ ++ + + +- ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- ++ + +- ++ + +- ++ +

    Functions

    +-dwc_otg_hcd_t * dwc_otg_hcd_alloc_hcd (void)
    ++dwc_otg_hcd_t * dwc_otg_hcd_alloc_hcd (void)
     This function allocates dwc_otg_hcd structure and returns pointer on it.
    void dwc_otg_hcd_connect_timeout (void *ptr)
    void dwc_otg_hcd_connect_timeout (void *ptr)
     Connection timeout function.
    static void hcd_start_func (void *_vp)
     Connection timeout function.
    void hcd_start_func (void *_vp)
     Work queue function for starting the HCD when A-Cable is connected.
    +-static void del_xfer_timers (dwc_otg_hcd_t *hcd)
     Work queue function for starting the HCD when A-Cable is connected.
    ++void del_xfer_timers (dwc_otg_hcd_t *hcd)
    +-static void del_timers (dwc_otg_hcd_t *hcd)
    ++void del_timers (dwc_otg_hcd_t *hcd)
    static void kill_urbs_in_qh_list (dwc_otg_hcd_t *hcd, dwc_list_link_t *qh_list)
    void kill_urbs_in_qh_list (dwc_otg_hcd_t *hcd, dwc_list_link_t *qh_list)
     Processes all the URBs in a single list of QHs.
    static void kill_all_urbs (dwc_otg_hcd_t *hcd)
     Processes all the URBs in a single list of QHs.
    void kill_all_urbs (dwc_otg_hcd_t *hcd)
     Responds with an error status of ETIMEDOUT to all URBs in the non-periodic and periodic schedules.
    static void dwc_otg_hcd_start_connect_timer (dwc_otg_hcd_t *hcd)
     Responds with an error status of ETIMEDOUT to all URBs in the non-periodic and periodic schedules.
    void dwc_otg_hcd_start_connect_timer (dwc_otg_hcd_t *hcd)
     Start the connection timer.
    static int32_t dwc_otg_hcd_session_start_cb (void *p)
     Start the connection timer.
    int32_t dwc_otg_hcd_session_start_cb (void *p)
     HCD Callback function for disconnect of the HCD.
    static int32_t dwc_otg_hcd_start_cb (void *p)
     HCD Callback function for disconnect of the HCD.
    int32_t dwc_otg_hcd_start_cb (void *p)
     HCD Callback function for starting the HCD when A-Cable is connected.
    static int32_t dwc_otg_hcd_disconnect_cb (void *p)
     HCD Callback function for starting the HCD when A-Cable is connected.
    int32_t dwc_otg_hcd_disconnect_cb (void *p)
     HCD Callback function for disconnect of the HCD.
    static int32_t dwc_otg_hcd_stop_cb (void *p)
     HCD Callback function for disconnect of the HCD.
    int32_t dwc_otg_hcd_stop_cb (void *p)
     HCD Callback function for stopping the HCD.
    static int dwc_otg_hcd_rem_wakeup_cb (void *p)
     HCD Callback function for stopping the HCD.
    int dwc_otg_hcd_rem_wakeup_cb (void *p)
     HCD Callback function for Remote Wakeup.
    void dwc_otg_hcd_stop (dwc_otg_hcd_t *hcd)
     HCD Callback function for Remote Wakeup.
    void dwc_otg_hcd_stop (dwc_otg_hcd_t *hcd)
     Halts the DWC_otg host mode operations in a clean manner.
    int dwc_otg_hcd_urb_enqueue (dwc_otg_hcd_t *hcd, dwc_otg_hcd_urb_t *dwc_otg_urb, void **ep_handle)
     Halts the DWC_otg host mode operations in a clean manner.
    int dwc_otg_hcd_urb_enqueue (dwc_otg_hcd_t *hcd, dwc_otg_hcd_urb_t *dwc_otg_urb, void **ep_handle, int atomic_alloc)
     Queue URB.
    int dwc_otg_hcd_urb_dequeue (dwc_otg_hcd_t *hcd, dwc_otg_hcd_urb_t *dwc_otg_urb)
     Queue URB.
    int dwc_otg_hcd_urb_dequeue (dwc_otg_hcd_t *hcd, dwc_otg_hcd_urb_t *dwc_otg_urb)
     De-queue the specified URB.
    int dwc_otg_hcd_endpoint_disable (dwc_otg_hcd_t *hcd, void *ep_handle, int retry)
     De-queue the specified URB.
    int dwc_otg_hcd_endpoint_disable (dwc_otg_hcd_t *hcd, void *ep_handle, int retry)
     Frees resources in the DWC_otg controller related to a given endpoint.
    +-static void reset_tasklet_func (void *data)
     Frees resources in the DWC_otg controller related to a given endpoint.
    ++int dwc_otg_hcd_endpoint_reset (dwc_otg_hcd_t *hcd, void *ep_handle)
    ++void reset_tasklet_func (void *data)
     Reset tasklet function.
    +-static void qh_list_free (dwc_otg_hcd_t *hcd, dwc_list_link_t *qh_list)
    ++void qh_list_free (dwc_otg_hcd_t *hcd, dwc_list_link_t *qh_list)
    ++void dwc_otg_hcd_power_up (void *ptr)
    +-static void dwc_otg_hcd_free (dwc_otg_hcd_t *dwc_otg_hcd)
     Exit from Hibernation if Host did not detect SRP from connected SRP capable Device during SRP time by host power up.
    ++void dwc_otg_hcd_free (dwc_otg_hcd_t *dwc_otg_hcd)
     Frees secondary storage associated with the dwc_otg_hcd structure contained in the struct usb_hcd field.
    int dwc_otg_hcd_init (dwc_otg_hcd_t *hcd, dwc_otg_core_if_t *core_if)
    int dwc_otg_hcd_init (dwc_otg_hcd_t *hcd, dwc_otg_core_if_t *core_if)
     This function should be called to initiate HCD Core.
    void dwc_otg_hcd_remove (dwc_otg_hcd_t *hcd)
     This function should be called to initiate HCD Core.
    void dwc_otg_hcd_remove (dwc_otg_hcd_t *hcd)
     Frees HCD.
    +-static void dwc_otg_hcd_reinit (dwc_otg_hcd_t *hcd)
     Frees HCD.
    ++void dwc_otg_hcd_reinit (dwc_otg_hcd_t *hcd)
     Initializes dynamic portions of the DWC_otg HCD state.
    static void assign_and_init_hc (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
    void assign_and_init_hc (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
     Assigns transactions from a QTD to a free host channel and initializes the host channel to perform the transactions.
    dwc_otg_transaction_type_e dwc_otg_hcd_select_transactions (dwc_otg_hcd_t *hcd)
     Assigns transactions from a QTD to a free host channel and initializes the host channel to perform the transactions.
    dwc_otg_transaction_type_e dwc_otg_hcd_select_transactions (dwc_otg_hcd_t *hcd)
     This function selects transactions from the HCD transfer schedule and assigns them to available host channels.
    static int queue_transaction (dwc_otg_hcd_t *hcd, dwc_hc_t *hc, uint16_t fifo_dwords_avail)
     This function selects transactions from the HCD transfer schedule and assigns them to available host channels.
    int queue_transaction (dwc_otg_hcd_t *hcd, dwc_hc_t *hc, uint16_t fifo_dwords_avail)
     Attempts to queue a single transaction request for a host channel associated with either a periodic or non-periodic transfer.
    static void process_periodic_channels (dwc_otg_hcd_t *hcd)
     Attempts to queue a single transaction request for a host channel associated with either a periodic or non-periodic transfer.
    void process_periodic_channels (dwc_otg_hcd_t *hcd)
     Processes periodic channels for the next frame and queues transactions for these channels to the DWC_otg controller.
    static void process_non_periodic_channels (dwc_otg_hcd_t *hcd)
     Processes periodic channels for the next frame and queues transactions for these channels to the DWC_otg controller.
    void process_non_periodic_channels (dwc_otg_hcd_t *hcd)
     Processes active non-periodic channels and queues transactions for these channels to the DWC_otg controller.
    void dwc_otg_hcd_queue_transactions (dwc_otg_hcd_t *hcd, dwc_otg_transaction_type_e tr_type)
     Processes active non-periodic channels and queues transactions for these channels to the DWC_otg controller.
    void dwc_otg_hcd_queue_transactions (dwc_otg_hcd_t *hcd, dwc_otg_transaction_type_e tr_type)
     This function processes the currently active host channels and queues transactions for these channels to the DWC_otg controller.
    int dwc_otg_hcd_hub_control (dwc_otg_hcd_t *dwc_otg_hcd, uint16_t typeReq, uint16_t wValue, uint16_t wIndex, uint8_t *buf, uint16_t wLength)
     This function processes the currently active host channels and queues transactions for these channels to the DWC_otg controller.
    int dwc_otg_hcd_hub_control (dwc_otg_hcd_t *dwc_otg_hcd, uint16_t typeReq, uint16_t wValue, uint16_t wIndex, uint8_t *buf, uint16_t wLength)
     Handles hub class-specific requests.
    int dwc_otg_hcd_is_status_changed (dwc_otg_hcd_t *hcd, int port)
     Handles hub class-specific requests.
    int dwc_otg_hcd_is_status_changed (dwc_otg_hcd_t *hcd, int port)
     Returns 1 if status of specified port is changed and 0 otherwise.
    int dwc_otg_hcd_get_frame_number (dwc_otg_hcd_t *dwc_otg_hcd)
     Returns 1 if status of specified port is changed and 0 otherwise.
    int dwc_otg_hcd_get_frame_number (dwc_otg_hcd_t *dwc_otg_hcd)
     Returns current frame number.
    int dwc_otg_hcd_start (dwc_otg_hcd_t *hcd, struct dwc_otg_hcd_function_ops *fops)
     Returns current frame number.
    int dwc_otg_hcd_start (dwc_otg_hcd_t *hcd, struct dwc_otg_hcd_function_ops *fops)
     This function initializes the HCD Core.
    void * dwc_otg_hcd_get_priv_data (dwc_otg_hcd_t *hcd)
     This function initializes the HCD Core.
    void * dwc_otg_hcd_get_priv_data (dwc_otg_hcd_t *hcd)
     Returns private data set by dwc_otg_hcd_set_priv_data function.
    void dwc_otg_hcd_set_priv_data (dwc_otg_hcd_t *hcd, void *priv_data)
     Returns private data set by dwc_otg_hcd_set_priv_data function.
    void dwc_otg_hcd_set_priv_data (dwc_otg_hcd_t *hcd, void *priv_data)
     Set private data.
    uint32_t dwc_otg_hcd_otg_port (dwc_otg_hcd_t *hcd)
     Set private data.
    uint32_t dwc_otg_hcd_otg_port (dwc_otg_hcd_t *hcd)
     Returns otg port number.
    uint32_t dwc_otg_hcd_is_b_host (dwc_otg_hcd_t *hcd)
     Returns otg port number.
    uint32_t dwc_otg_hcd_is_b_host (dwc_otg_hcd_t *hcd)
     Returns 1 if currently core is acting as B host, and 0 otherwise.
    dwc_otg_hcd_urb_t * dwc_otg_hcd_urb_alloc (dwc_otg_hcd_t *hcd, int iso_desc_count, int atomic_alloc)
     Returns 1 if currently core is acting as B host, and 0 otherwise.
    dwc_otg_hcd_urb_t * dwc_otg_hcd_urb_alloc (dwc_otg_hcd_t *hcd, int iso_desc_count, int atomic_alloc)
     Allocates memory for dwc_otg_hcd_urb structure.
    void dwc_otg_hcd_urb_set_pipeinfo (dwc_otg_hcd_urb_t *dwc_otg_urb, uint8_t dev_addr, uint8_t ep_num, uint8_t ep_type, uint8_t ep_dir, uint16_t mps)
     Allocates memory for dwc_otg_hcd_urb structure.
    void dwc_otg_hcd_urb_set_pipeinfo (dwc_otg_hcd_urb_t *dwc_otg_urb, uint8_t dev_addr, uint8_t ep_num, uint8_t ep_type, uint8_t ep_dir, uint16_t mps)
     Set pipe information in URB.
    void dwc_otg_hcd_urb_set_params (dwc_otg_hcd_urb_t *dwc_otg_urb, void *urb_handle, void *buf, dwc_dma_t dma, uint32_t buflen, void *setup_packet, dwc_dma_t setup_dma, uint32_t flags, uint16_t interval)
     Set pipe information in URB.
    void dwc_otg_hcd_urb_set_params (dwc_otg_hcd_urb_t *dwc_otg_urb, void *urb_handle, void *buf, dwc_dma_t dma, uint32_t buflen, void *setup_packet, dwc_dma_t setup_dma, uint32_t flags, uint16_t interval)
     Sets dwc_otg_hcd_urb parameters.
    uint32_t dwc_otg_hcd_urb_get_status (dwc_otg_hcd_urb_t *dwc_otg_urb)
     Sets dwc_otg_hcd_urb parameters.
    uint32_t dwc_otg_hcd_urb_get_status (dwc_otg_hcd_urb_t *dwc_otg_urb)
     Gets status from dwc_otg_hcd_urb.
    uint32_t dwc_otg_hcd_urb_get_actual_length (dwc_otg_hcd_urb_t *dwc_otg_urb)
     Gets status from dwc_otg_hcd_urb.
    uint32_t dwc_otg_hcd_urb_get_actual_length (dwc_otg_hcd_urb_t *dwc_otg_urb)
     Gets actual length from dwc_otg_hcd_urb.
    uint32_t dwc_otg_hcd_urb_get_error_count (dwc_otg_hcd_urb_t *dwc_otg_urb)
     Gets actual length from dwc_otg_hcd_urb.
    uint32_t dwc_otg_hcd_urb_get_error_count (dwc_otg_hcd_urb_t *dwc_otg_urb)
     Gets error count from dwc_otg_hcd_urb.
    void dwc_otg_hcd_urb_set_iso_desc_params (dwc_otg_hcd_urb_t *dwc_otg_urb, int desc_num, uint32_t offset, uint32_t length)
     Gets error count from dwc_otg_hcd_urb.
    void dwc_otg_hcd_urb_set_iso_desc_params (dwc_otg_hcd_urb_t *dwc_otg_urb, int desc_num, uint32_t offset, uint32_t length)
     Set ISOC descriptor offset and length.
    uint32_t dwc_otg_hcd_urb_get_iso_desc_status (dwc_otg_hcd_urb_t *dwc_otg_urb, int desc_num)
     Set ISOC descriptor offset and length.
    uint32_t dwc_otg_hcd_urb_get_iso_desc_status (dwc_otg_hcd_urb_t *dwc_otg_urb, int desc_num)
     Get status of ISOC descriptor, specified by desc_num.
    uint32_t dwc_otg_hcd_urb_get_iso_desc_actual_length (dwc_otg_hcd_urb_t *dwc_otg_urb, int desc_num)
     Get status of ISOC descriptor, specified by desc_num.
    uint32_t dwc_otg_hcd_urb_get_iso_desc_actual_length (dwc_otg_hcd_urb_t *dwc_otg_urb, int desc_num)
     Get actual length of ISOC descriptor, specified by desc_num.
    int dwc_otg_hcd_is_bandwidth_allocated (dwc_otg_hcd_t *hcd, void *ep_handle)
     Get actual length of ISOC descriptor, specified by desc_num.
    int dwc_otg_hcd_is_bandwidth_allocated (dwc_otg_hcd_t *hcd, void *ep_handle)
     Call this function to check if bandwidth was allocated for specified endpoint.
    int dwc_otg_hcd_is_bandwidth_freed (dwc_otg_hcd_t *hcd, void *ep_handle)
     Call this function to check if bandwidth was allocated for specified endpoint.
    int dwc_otg_hcd_is_bandwidth_freed (dwc_otg_hcd_t *hcd, void *ep_handle)
     Call this function to check if bandwidth was freed for specified endpoint.
    uint8_t dwc_otg_hcd_get_ep_bandwidth (dwc_otg_hcd_t *hcd, void *ep_handle)
     Call this function to check if bandwidth was freed for specified endpoint.
    uint8_t dwc_otg_hcd_get_ep_bandwidth (dwc_otg_hcd_t *hcd, void *ep_handle)
     Returns bandwidth allocated for specified endpoint in microseconds.
    void dwc_otg_hcd_dump_state (dwc_otg_hcd_t *hcd)
     Returns bandwidth allocated for specified endpoint in microseconds.
    void dwc_otg_hcd_dump_state (dwc_otg_hcd_t *hcd)
     Dumps hcd state.
    void dwc_otg_hcd_dump_frrem (dwc_otg_hcd_t *hcd)
     Dumps hcd state.
    void dwc_otg_hcd_dump_frrem (dwc_otg_hcd_t *hcd)
     Dump the average frame remaining at SOF.
     Dump the average frame remaining at SOF.

    Variables

    static dwc_otg_cil_callbacks_t hcd_cil_callbacks
    dwc_otg_cil_callbacks_t hcd_cil_callbacks
     HCD Callback structure for handling mode switching.
     HCD Callback structure for handling mode switching.
    +

    Detailed Description

    + This file implements HCD Core. +

    +-All code in this file is portable and don't use any OS specific functions. Interface provided by HCD Core is defined in <hcd_if.h> header file. ++All code in this file is portable and doesn't use any OS specific functions. Interface provided by HCD Core is defined in <hcd_if.h> header file. +

    + Definition in file dwc_otg_hcd.c.

    Function Documentation

    +- +-
    +-
    +- +- +- +- +- +- +- +- ++

    ++

    void dwc_otg_hcd_connect_timeout (void *  ptr  ) 
    ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ + +
    void dwc_otg_hcd_connect_timeout ( void *  ptr  ) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Connection timeout function. +

    + An OTG host is required to display a message if the device does not connect within 10 seconds. +

    +-Definition at line 54 of file dwc_otg_hcd.c. +- +-

    +- +-

    +-
    +- +- +- +- +- +- +- +- ++Definition at line 54 of file dwc_otg_hcd.c. ++ ++
    static void hcd_start_func (void *  _vp  )  [static]
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ + +
    void hcd_start_func ( void *  _vp  )  [static]
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Work queue function for starting the HCD when A-Cable is connected. +

    +-The hcd_start() must be called in a process context. ++The hcd_start() must be called in a process context. +

    +-Definition at line 123 of file dwc_otg_hcd.c. +- +-

    +- +-

    +-
    +- ++Definition at line 123 of file dwc_otg_hcd.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    static void kill_urbs_in_qh_list (dwc_otg_hcd_t *  hcd, void kill_urbs_in_qh_list ( dwc_otg_hcd_t *  hcd,
    dwc_list_link_t *  qh_list dwc_list_link_t *  qh_list
    ) [static])  [static]
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Processes all the URBs in a single list of QHs. +

    + Completes them with -ETIMEDOUT and frees the QTD. +

    +-Definition at line 154 of file dwc_otg_hcd.c. +- +-

    +- +-

    +-
    +- +- +- +- +- +- +- +- ++Definition at line 154 of file dwc_otg_hcd.c. ++ ++
    static void kill_all_urbs (dwc_otg_hcd_t *  hcd  )  [static]
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ + +
    void kill_all_urbs ( dwc_otg_hcd_t *  hcd  )  [static]
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Responds with an error status of ETIMEDOUT to all URBs in the non-periodic and periodic schedules. +

    + The QTD associated with each URB is removed from the schedule and freed. This function may be called when a disconnect is detected or when the HCD is being stopped. +

    +-Definition at line 182 of file dwc_otg_hcd.c. +- +-

    +- +-

    +-
    +- +- +- +- +- +- +- +- ++Definition at line 181 of file dwc_otg_hcd.c. ++ ++
    static void dwc_otg_hcd_start_connect_timer (dwc_otg_hcd_t *  hcd  )  [static]
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ + +
    void dwc_otg_hcd_start_connect_timer ( dwc_otg_hcd_t *  hcd  )  [static]
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Start the connection timer. +

    + An OTG host is required to display a message if the device does not connect within 10 seconds. The timer is deleted if a port connect interrupt occurs before the timer expires. +

    +-Definition at line 198 of file dwc_otg_hcd.c. +- +-

    +- +-

    +-
    +- +- +- +- +- +- +- +- ++Definition at line 197 of file dwc_otg_hcd.c. ++ ++
    static int32_t dwc_otg_hcd_session_start_cb (void *  p  )  [static]
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ + +
    int32_t dwc_otg_hcd_session_start_cb ( void *  p  )  [static]
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + HCD Callback function for disconnect of the HCD. +@@ -349,24 +392,32 @@ + + +

    +-Definition at line 208 of file dwc_otg_hcd.c. +- +-

    +- +-

    +-
    +- +- +- +- +- +- +- +- ++Definition at line 207 of file dwc_otg_hcd.c. ++ ++
    static int32_t dwc_otg_hcd_start_cb (void *  p  )  [static]
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ + +
    int32_t dwc_otg_hcd_start_cb ( void *  p  )  [static]
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + HCD Callback function for starting the HCD when A-Cable is connected. +@@ -378,24 +429,32 @@ + + +

    +-Definition at line 223 of file dwc_otg_hcd.c. +- +-

    +- +-

    +-
    +- +- +- +- +- +- +- +- ++Definition at line 222 of file dwc_otg_hcd.c. ++ ++
    static int32_t dwc_otg_hcd_disconnect_cb (void *  p  )  [static]
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ + +
    int32_t dwc_otg_hcd_disconnect_cb ( void *  p  )  [static]
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + HCD Callback function for disconnect of the HCD. +@@ -407,24 +466,32 @@ + + +

    +-Definition at line 253 of file dwc_otg_hcd.c. +- +-

    +- +-

    +-
    +- +- +- +- +- +- +- +- ++Definition at line 252 of file dwc_otg_hcd.c. ++ ++
    static int32_t dwc_otg_hcd_stop_cb (void *  p  )  [static]
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ + +
    int32_t dwc_otg_hcd_stop_cb ( void *  p  )  [static]
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + HCD Callback function for stopping the HCD. +@@ -436,24 +503,32 @@ + + +

    +-Definition at line 373 of file dwc_otg_hcd.c. +- +-

    +- +-

    +-
    +- +- +- +- +- +- +- +- ++Definition at line 372 of file dwc_otg_hcd.c. ++ ++
    static int dwc_otg_hcd_rem_wakeup_cb (void *  p  )  [static]
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ + +
    int dwc_otg_hcd_rem_wakeup_cb ( void *  p  )  [static]
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + HCD Callback function for Remote Wakeup. +@@ -465,63 +540,85 @@ + + +

    +-Definition at line 403 of file dwc_otg_hcd.c. +- +-

    +- +-

    +-
    +- +- +- +- +- +- +- +- ++Definition at line 402 of file dwc_otg_hcd.c. ++ ++
    void dwc_otg_hcd_stop (dwc_otg_hcd_t *  hcd  ) 
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ + +
    void dwc_otg_hcd_stop ( dwc_otg_hcd_t *  hcd  ) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Halts the DWC_otg host mode operations in a clean manner. +

    + USB transfers are stopped. +

    +-Definition at line 422 of file dwc_otg_hcd.c. +- +-

    +- +-

    +-
    +- ++Definition at line 421 of file dwc_otg_hcd.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    int dwc_otg_hcd_urb_enqueue ( dwc_otg_hcd_t *  dwc_otg_hcd,
    int dwc_otg_hcd_urb_enqueue (dwc_otg_hcd_t *  dwc_otg_hcd, dwc_otg_hcd_urb_t *  dwc_otg_urb,
    dwc_otg_hcd_urb_t *  dwc_otg_urb, void **  ep_handle,
    void **  ep_handle int  atomic_alloc
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Queue URB. +@@ -529,85 +626,102 @@ + After transfer is completes, the complete callback will be called with the URB status

    +

    Parameters:
    + +- ++ + +- ++ ++ +
    dwc_otg_hcd The HCD
    dwc_otg_hcd The HCD
    dwc_otg_urb DWC_OTG URB
    ep_handle Out parameter for returning endpoint handle
    ep_handle Out parameter for returning endpoint handle
    atomic_alloc Flag to do atomic allocation if needed
    +
    + Returns -DWC_E_NO_DEVICE if no device is connected. Returns -DWC_E_NO_MEMORY if there is no enough memory. Returns 0 on success. +

    +-Definition at line 444 of file dwc_otg_hcd.c. +- +-

    +- +-

    +-
    +- ++Definition at line 443 of file dwc_otg_hcd.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    int dwc_otg_hcd_urb_dequeue (dwc_otg_hcd_t *  dwc_otg_hcd, int dwc_otg_hcd_urb_dequeue ( dwc_otg_hcd_t *  dwc_otg_hcd,
    dwc_otg_hcd_urb_t *  dwc_otg_urb dwc_otg_hcd_urb_t *  dwc_otg_urb
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + De-queue the specified URB. +

    +

    Parameters:
    + +- ++ + +
    dwc_otg_hcd The HCD
    dwc_otg_hcd The HCD
    dwc_otg_urb DWC_OTG URB
    +
    + +

    +-Definition at line 489 of file dwc_otg_hcd.c. +- +-

    +- +-

    +-
    +- ++Definition at line 492 of file dwc_otg_hcd.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    int dwc_otg_hcd_endpoint_disable (dwc_otg_hcd_t *  hcd, int dwc_otg_hcd_endpoint_disable ( dwc_otg_hcd_t *  hcd,
    void *  ep_handle, void *  ep_handle,
    int  retry int  retry
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Frees resources in the DWC_otg controller related to a given endpoint. +@@ -622,33 +736,41 @@ + + Returns -DWC_E_INVALID if invalid arguments are passed. Returns 0 on success +

    +-Definition at line 547 of file dwc_otg_hcd.c. +- +-

    +- +-

    +-
    +- ++Definition at line 542 of file dwc_otg_hcd.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    int dwc_otg_hcd_init (dwc_otg_hcd_t *  hcd, int dwc_otg_hcd_init ( dwc_otg_hcd_t *  hcd,
    dwc_otg_core_if_t *  core_if dwc_otg_core_if_t *  core_if
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + This function should be called to initiate HCD Core. +@@ -661,24 +783,32 @@ + + Returns -DWC_E_NO_MEMORY if no enough memory. Returns 0 on success +

    +-Definition at line 693 of file dwc_otg_hcd.c. +- +-

    +- +-

    +-
    +- +- +- +- +- +- +- +- ++Definition at line 780 of file dwc_otg_hcd.c. ++ ++
    void dwc_otg_hcd_remove (dwc_otg_hcd_t *  hcd  ) 
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ + +
    void dwc_otg_hcd_remove ( dwc_otg_hcd_t *  hcd  ) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Frees HCD. +@@ -690,33 +820,41 @@ + + +

    +-Definition at line 778 of file dwc_otg_hcd.c. +- +-

    +- +-

    +-
    +- ++Definition at line 879 of file dwc_otg_hcd.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    static void assign_and_init_hc (dwc_otg_hcd_t *  hcd, void assign_and_init_hc ( dwc_otg_hcd_t *  hcd,
    dwc_otg_qh_t *  qh dwc_otg_qh_t *  qh
    ) [static])  [static]
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Assigns transactions from a QTD to a free host channel and initializes the host channel to perform the transactions. +@@ -730,24 +868,32 @@ + + +

    +-Definition at line 832 of file dwc_otg_hcd.c. +- +-

    +- +-

    +-
    +- +- +- +- +- +- +- +- ++Definition at line 936 of file dwc_otg_hcd.c. ++ ++
    dwc_otg_transaction_type_e dwc_otg_hcd_select_transactions (dwc_otg_hcd_t *  hcd  ) 
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ + +
    dwc_otg_transaction_type_e dwc_otg_hcd_select_transactions ( dwc_otg_hcd_t *  hcd  ) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + This function selects transactions from the HCD transfer schedule and assigns them to available host channels. +@@ -761,39 +907,47 @@ +

    Returns:
    The types of new transactions that were assigned to host channels.
    + +

    +-Definition at line 1055 of file dwc_otg_hcd.c. +- +-

    +- +-

    +-
    +- ++Definition at line 1168 of file dwc_otg_hcd.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    static int queue_transaction (dwc_otg_hcd_t *  hcd, int queue_transaction ( dwc_otg_hcd_t *  hcd,
    dwc_hc_t *  hc, dwc_hc_t *  hc,
    uint16_t  fifo_dwords_avail uint16_t  fifo_dwords_avail
    ) [static])  [static]
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Attempts to queue a single transaction request for a host channel associated with either a periodic or non-periodic transfer. +@@ -809,81 +963,105 @@ +

    Returns:
    1 if a request is queued and more requests may be needed to complete the transfer, 0 if no more requests are required for this transfer, -1 if there is insufficient space in the Tx FIFO.
    + +

    +-Definition at line 1139 of file dwc_otg_hcd.c. +- +-

    +- +-

    +-
    +- +- +- +- +- +- +- +- ++Definition at line 1253 of file dwc_otg_hcd.c. ++ ++
    static void process_periodic_channels (dwc_otg_hcd_t *  hcd  )  [static]
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ + +
    void process_periodic_channels ( dwc_otg_hcd_t *  hcd  )  [static]
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Processes periodic channels for the next frame and queues transactions for these channels to the DWC_otg controller. +

    + After queueing transactions, the Periodic Tx FIFO Empty interrupt is enabled if there are more transactions to queue as Periodic Tx FIFO or request queue space becomes available. Otherwise, the Periodic Tx FIFO Empty interrupt is disabled. +

    +-Definition at line 1199 of file dwc_otg_hcd.c. +- +-

    +- +-

    +-
    +- +- +- +- +- +- +- +- ++Definition at line 1313 of file dwc_otg_hcd.c. ++ ++
    static void process_non_periodic_channels (dwc_otg_hcd_t *  hcd  )  [static]
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ + +
    void process_non_periodic_channels ( dwc_otg_hcd_t *  hcd  )  [static]
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Processes active non-periodic channels and queues transactions for these channels to the DWC_otg controller. +

    + After queueing transactions, the NP Tx FIFO Empty interrupt is enabled if there are more transactions to queue as NP Tx FIFO or request queue space becomes available. Otherwise, the NP Tx FIFO Empty interrupt is disabled. +

    +-Definition at line 1316 of file dwc_otg_hcd.c. +- +-

    +- +-

    +-
    +- ++Definition at line 1430 of file dwc_otg_hcd.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    void dwc_otg_hcd_queue_transactions (dwc_otg_hcd_t *  hcd, void dwc_otg_hcd_queue_transactions ( dwc_otg_hcd_t *  hcd,
    dwc_otg_transaction_type_e  tr_type dwc_otg_transaction_type_e  tr_type
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + This function processes the currently active host channels and queues transactions for these channels to the DWC_otg controller. +@@ -897,100 +1075,109 @@ + + +

    +-Definition at line 1426 of file dwc_otg_hcd.c. +- +-

    +- +-

    +-
    +- ++Definition at line 1540 of file dwc_otg_hcd.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    int dwc_otg_hcd_hub_control (dwc_otg_hcd_t *  dwc_otg_hcd, int dwc_otg_hcd_hub_control ( dwc_otg_hcd_t *  dwc_otg_hcd,
    uint16_t  typeReq, uint16_t  typeReq,
    uint16_t  wValue, uint16_t  wValue,
    uint16_t  wIndex, uint16_t  wIndex,
    uint8_t *  buf, uint8_t *  buf,
    uint16_t  wLength uint16_t  wLength
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Handles hub class-specific requests. +

    +-

    Parameters:
    +- +- +- +- +- +- +- +-
    dwc_otg_hcd The HCD
    typeReq Request Type
    wValue wValue from control request
    wIndex wIndex from control request
    buf data buffer
    wLength data buffer length
    +-
    +-Returns -DWC_E_INVALID if invalid argument is passed Returns 0 on success ++
    Todo:
      ++
    • check how sw can wait for 1 sec to check asesvld???
    ++
    ++ +

    +-Definition at line 1905 of file dwc_otg_hcd.c. +- +-

    +- +-

    +-
    +- ++Definition at line 2015 of file dwc_otg_hcd.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    int dwc_otg_hcd_is_status_changed (dwc_otg_hcd_t *  hcd, int dwc_otg_hcd_is_status_changed ( dwc_otg_hcd_t *  hcd,
    int  port int  port
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Returns 1 if status of specified port is changed and 0 otherwise. +@@ -1003,24 +1190,32 @@ + + +

    +-Definition at line 2611 of file dwc_otg_hcd.c. +- +-

    +- +-

    +-
    +- +- +- +- +- +- +- +- ++Definition at line 2896 of file dwc_otg_hcd.c. ++ ++
    int dwc_otg_hcd_get_frame_number (dwc_otg_hcd_t *  hcd  ) 
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ + +
    int dwc_otg_hcd_get_frame_number ( dwc_otg_hcd_t *  hcd  ) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Returns current frame number. +@@ -1032,33 +1227,41 @@ + + +

    +-Definition at line 2643 of file dwc_otg_hcd.c. +- +-

    +- +-

    +-
    +- ++Definition at line 2928 of file dwc_otg_hcd.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    int dwc_otg_hcd_start (dwc_otg_hcd_t *  hcd, int dwc_otg_hcd_start ( dwc_otg_hcd_t *  hcd,
    struct dwc_otg_hcd_function_ops *  fops struct dwc_otg_hcd_function_ops *  fops
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + This function initializes the HCD Core. +@@ -1071,24 +1274,32 @@ + + Returns -DWC_E_NO_DEVICE if Core is currently is in device mode. Returns 0 on success +

    +-Definition at line 2656 of file dwc_otg_hcd.c. +- +-

    +- +-

    +-
    +- +- +- +- +- +- +- +- ++Definition at line 2942 of file dwc_otg_hcd.c. ++ ++
    void* dwc_otg_hcd_get_priv_data (dwc_otg_hcd_t *  hcd  ) 
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ + +
    void* dwc_otg_hcd_get_priv_data ( dwc_otg_hcd_t *  hcd  ) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Returns private data set by dwc_otg_hcd_set_priv_data function. +@@ -1100,33 +1311,41 @@ + + +

    +-Definition at line 2671 of file dwc_otg_hcd.c. +- +-

    +- +-

    +-
    +- ++Definition at line 2958 of file dwc_otg_hcd.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    void dwc_otg_hcd_set_priv_data (dwc_otg_hcd_t *  hcd, void dwc_otg_hcd_set_priv_data ( dwc_otg_hcd_t *  hcd,
    void *  priv_data void *  priv_data
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Set private data. +@@ -1139,24 +1358,32 @@ + + +

    +-Definition at line 2676 of file dwc_otg_hcd.c. +- +-

    +- +-

    +-
    +- +- +- +- +- +- +- +- ++Definition at line 2963 of file dwc_otg_hcd.c. ++ ++
    uint32_t dwc_otg_hcd_otg_port (dwc_otg_hcd_t *  hcd  ) 
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ + +
    uint32_t dwc_otg_hcd_otg_port ( dwc_otg_hcd_t *  hcd  ) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Returns otg port number. +@@ -1168,24 +1395,32 @@ + + +

    +-Definition at line 2681 of file dwc_otg_hcd.c. +- +-

    +- +-

    +-
    +- +- +- +- +- +- +- +- ++Definition at line 2968 of file dwc_otg_hcd.c. ++ ++
    uint32_t dwc_otg_hcd_is_b_host (dwc_otg_hcd_t *  hcd  ) 
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ + +
    uint32_t dwc_otg_hcd_is_b_host ( dwc_otg_hcd_t *  hcd  ) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Returns 1 if currently core is acting as B host, and 0 otherwise. +@@ -1197,44 +1432,52 @@ + + +

    +-Definition at line 2686 of file dwc_otg_hcd.c. +- +-

    +- +-

    +-
    +- ++Definition at line 2973 of file dwc_otg_hcd.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    dwc_otg_hcd_urb_t* dwc_otg_hcd_urb_alloc (dwc_otg_hcd_t *  hcd, dwc_otg_hcd_urb_t* dwc_otg_hcd_urb_alloc ( dwc_otg_hcd_t *  hcd,
    int  iso_desc_count, int  iso_desc_count,
    int  atomic_alloc int  atomic_alloc
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    +-Allocates memory for dwc_otg_hcd_urb structure. ++Allocates memory for dwc_otg_hcd_urb structure. +

    +-Allocated memory should be freed by call dwc_free function.

    ++Allocated memory should be freed by call of DWC_FREE.

    +

    Parameters:
    + + +@@ -1244,57 +1487,65 @@ + + +

    +-Definition at line 2698 of file dwc_otg_hcd.c. +- +-

    +- +-

    +-
    +-
    hcd The HCD
    ++Definition at line 2985 of file dwc_otg_hcd.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    void dwc_otg_hcd_urb_set_pipeinfo (dwc_otg_hcd_urb_t *  hcd_urb, void dwc_otg_hcd_urb_set_pipeinfo ( dwc_otg_hcd_urb_t *  hcd_urb,
    uint8_t  devaddr, uint8_t  devaddr,
    uint8_t  ep_num, uint8_t  ep_num,
    uint8_t  ep_type, uint8_t  ep_type,
    uint8_t  ep_dir, uint8_t  ep_dir,
    uint16_t  mps uint16_t  mps
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Set pipe information in URB. +@@ -1311,78 +1562,86 @@ + + +

    +-Definition at line 2717 of file dwc_otg_hcd.c. +- +-

    +- +-

    +-
    +- ++Definition at line 3004 of file dwc_otg_hcd.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    void dwc_otg_hcd_urb_set_params (dwc_otg_hcd_urb_t *  urb, void dwc_otg_hcd_urb_set_params ( dwc_otg_hcd_urb_t *  urb,
    void *  urb_handle, void *  urb_handle,
    void *  buf, void *  buf,
    dwc_dma_t  dma, dwc_dma_t  dma,
    uint32_t  buflen, uint32_t  buflen,
    void *  sp, void *  sp,
    dwc_dma_t  sp_dma, dwc_dma_t  sp_dma,
    uint32_t  flags, uint32_t  flags,
    uint16_t  interval uint16_t  interval
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    +-Sets dwc_otg_hcd_urb parameters. ++Sets dwc_otg_hcd_urb parameters. +

    +

    Parameters:
    + +@@ -1399,27 +1658,35 @@ + + +

    +-Definition at line 2730 of file dwc_otg_hcd.c. +- +-

    +- +-

    +-
    +-
    +- +- +- +- +- +- +- ++Definition at line 3017 of file dwc_otg_hcd.c. ++ ++
    uint32_t dwc_otg_hcd_urb_get_status (dwc_otg_hcd_urb_t *  dwc_otg_urb  ) 
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ + +
    uint32_t dwc_otg_hcd_urb_get_status ( dwc_otg_hcd_urb_t *  dwc_otg_urb  ) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    +-Gets status from dwc_otg_hcd_urb. ++Gets status from dwc_otg_hcd_urb. +

    +

    Parameters:
    + +@@ -1428,27 +1695,35 @@ + + +

    +-Definition at line 2747 of file dwc_otg_hcd.c. +- +-

    +- +-

    +-
    +-
    +- +- +- +- +- +- +- ++Definition at line 3034 of file dwc_otg_hcd.c. ++ ++
    uint32_t dwc_otg_hcd_urb_get_actual_length (dwc_otg_hcd_urb_t *  dwc_otg_urb  ) 
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ + +
    uint32_t dwc_otg_hcd_urb_get_actual_length ( dwc_otg_hcd_urb_t *  dwc_otg_urb  ) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    +-Gets actual length from dwc_otg_hcd_urb. ++Gets actual length from dwc_otg_hcd_urb. +

    +

    Parameters:
    + +@@ -1457,27 +1732,35 @@ + + +

    +-Definition at line 2752 of file dwc_otg_hcd.c. +- +-

    +- +-

    +-
    +-
    +- +- +- +- +- +- +- ++Definition at line 3039 of file dwc_otg_hcd.c. ++ ++
    uint32_t dwc_otg_hcd_urb_get_error_count (dwc_otg_hcd_urb_t *  dwc_otg_urb  ) 
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ + +
    uint32_t dwc_otg_hcd_urb_get_error_count ( dwc_otg_hcd_urb_t *  dwc_otg_urb  ) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    +-Gets error count from dwc_otg_hcd_urb. ++Gets error count from dwc_otg_hcd_urb. +

    + Only for ISOC URBs

    +

    Parameters:
    +@@ -1487,45 +1770,53 @@ +
    + +

    +-Definition at line 2757 of file dwc_otg_hcd.c. +- +-

    +- +-

    +-
    +- ++Definition at line 3044 of file dwc_otg_hcd.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    void dwc_otg_hcd_urb_set_iso_desc_params (dwc_otg_hcd_urb_t *  dwc_otg_urb, void dwc_otg_hcd_urb_set_iso_desc_params ( dwc_otg_hcd_urb_t *  dwc_otg_urb,
    int  desc_num, int  desc_num,
    uint32_t  offset, uint32_t  offset,
    uint32_t  length uint32_t  length
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Set ISOC descriptor offset and length. +@@ -1540,33 +1831,41 @@ + + +

    +-Definition at line 2762 of file dwc_otg_hcd.c. +- +-

    +- +-

    +-
    +- ++Definition at line 3049 of file dwc_otg_hcd.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    uint32_t dwc_otg_hcd_urb_get_iso_desc_status (dwc_otg_hcd_urb_t *  dwc_otg_urb, uint32_t dwc_otg_hcd_urb_get_iso_desc_status ( dwc_otg_hcd_urb_t *  dwc_otg_urb,
    int  desc_num int  desc_num
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Get status of ISOC descriptor, specified by desc_num. +@@ -1579,33 +1878,41 @@ + + +

    +-Definition at line 2770 of file dwc_otg_hcd.c. +- +-

    +- +-

    +-
    +- ++Definition at line 3057 of file dwc_otg_hcd.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    uint32_t dwc_otg_hcd_urb_get_iso_desc_actual_length (dwc_otg_hcd_urb_t *  dwc_otg_urb, uint32_t dwc_otg_hcd_urb_get_iso_desc_actual_length ( dwc_otg_hcd_urb_t *  dwc_otg_urb,
    int  desc_num int  desc_num
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Get actual length of ISOC descriptor, specified by desc_num. +@@ -1618,33 +1925,41 @@ + + +

    +-Definition at line 2776 of file dwc_otg_hcd.c. +- +-

    +- +-

    +-
    +- ++Definition at line 3063 of file dwc_otg_hcd.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    int dwc_otg_hcd_is_bandwidth_allocated (dwc_otg_hcd_t *  hcd, int dwc_otg_hcd_is_bandwidth_allocated ( dwc_otg_hcd_t *  hcd,
    void *  ep_handle void *  ep_handle
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Call this function to check if bandwidth was allocated for specified endpoint. +@@ -1658,33 +1973,41 @@ + + +

    +-Definition at line 2782 of file dwc_otg_hcd.c. +- +-

    +- +-

    +-
    +- ++Definition at line 3069 of file dwc_otg_hcd.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    int dwc_otg_hcd_is_bandwidth_freed (dwc_otg_hcd_t *  hcd, int dwc_otg_hcd_is_bandwidth_freed ( dwc_otg_hcd_t *  hcd,
    void *  ep_handle void *  ep_handle
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Call this function to check if bandwidth was freed for specified endpoint. +@@ -1697,33 +2020,41 @@ + + +

    +-Definition at line 2795 of file dwc_otg_hcd.c. +- +-

    +- +-

    +-
    +- ++Definition at line 3082 of file dwc_otg_hcd.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    uint8_t dwc_otg_hcd_get_ep_bandwidth (dwc_otg_hcd_t *  hcd, uint8_t dwc_otg_hcd_get_ep_bandwidth ( dwc_otg_hcd_t *  hcd,
    void *  ep_handle void *  ep_handle
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Returns bandwidth allocated for specified endpoint in microseconds. +@@ -1737,24 +2068,32 @@ + + +

    +-Definition at line 2808 of file dwc_otg_hcd.c. +- +-

    +- +-

    +-
    +- +- +- +- +- +- +- +- ++Definition at line 3095 of file dwc_otg_hcd.c. ++ ++
    void dwc_otg_hcd_dump_state (dwc_otg_hcd_t *  hcd  ) 
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ + +
    void dwc_otg_hcd_dump_state ( dwc_otg_hcd_t *  hcd  ) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Dumps hcd state. +@@ -1766,24 +2105,32 @@ + + +

    +-Definition at line 2815 of file dwc_otg_hcd.c. +- +-

    +- +-

    +-
    +- +- +- +- +- +- +- +- ++Definition at line 3102 of file dwc_otg_hcd.c. ++ ++
    void dwc_otg_hcd_dump_frrem (dwc_otg_hcd_t *  hcd  ) 
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ + +
    void dwc_otg_hcd_dump_frrem ( dwc_otg_hcd_t *  hcd  ) 
    +- +-
    ++
    ++ ++ ++ ++ ++ ++
    ++   ++ + +

    + Dump the average frame remaining at SOF. +@@ -1796,28 +2143,36 @@ + + +

    +-Definition at line 2991 of file dwc_otg_hcd.c. +- +-

    ++Definition at line 3278 of file dwc_otg_hcd.c.

    +

    Variable Documentation

    +- +-
    +-
    +- ++

    ++

    ++ ++ ++ ++
    ++ + +- ++ + +
    dwc_otg_cil_callbacks_t hcd_cil_callbacks [static] dwc_otg_cil_callbacks_t hcd_cil_callbacks [static]
    +- +-
    ++
    ++ ++ ++ ++ ++ ++
    ++   ++ + +

    + Initial value:

     {
+-        .start = dwc_otg_hcd_start_cb,
+-        .stop = dwc_otg_hcd_stop_cb,
+-        .disconnect = dwc_otg_hcd_disconnect_cb,
+-        .session_start = dwc_otg_hcd_session_start_cb,
+-        .resume_wakeup = dwc_otg_hcd_rem_wakeup_cb,
++        .start = dwc_otg_hcd_start_cb,
++        .stop = dwc_otg_hcd_stop_cb,
++        .disconnect = dwc_otg_hcd_disconnect_cb,
++        .session_start = dwc_otg_hcd_session_start_cb,
++        .resume_wakeup = dwc_otg_hcd_rem_wakeup_cb,
+ 
+ 
+ 
+@@ -1827,11 +2182,11 @@
+ 
    
+ 
+ 
    
+-Definition at line 590 of file dwc_otg_hcd.c.
+-
    +-

    +-

    Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++Definition at line 599 of file dwc_otg_hcd.c.
    ++
    Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
    ++doxygen 1.3.9.1 + + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__hcd_8h-source.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/dwc__otg__hcd_8h-source.html 2013-07-26 19:31:21.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__hcd_8h-source.html 2013-07-26 19:34:41.000000000 +0000 +@@ -2,516 +2,515 @@ + + DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_hcd.h Source File + +- + +- +-
    +-
    +-
    +-
    +-

    dwc_otg_hcd.h

    Go to the documentation of this file.
    00001 /* ==========================================================================
+-00002  * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd.h $
+-00003  * $Revision: #52 $
+-00004  * $Date: 2009/04/21 $
+-00005  * $Change: 1237472 $
+-00006  *
+-00007  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
+-00008  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
+-00009  * otherwise expressly agreed to in writing between Synopsys and you.
+-00010  *
+-00011  * The Software IS NOT an item of Licensed Software or Licensed Product under
+-00012  * any End User Software License Agreement or Agreement for Licensed Product
+-00013  * with Synopsys or any supplement thereto. You are permitted to use and
+-00014  * redistribute this Software in source and binary forms, with or without
+-00015  * modification, provided that redistributions of source code must retain this
+-00016  * notice. You may not view, use, disclose, copy or distribute this file or
+-00017  * any information contained herein except pursuant to this license grant from
+-00018  * Synopsys. If you do not agree with this notice, including the disclaimer
+-00019  * below, then you are not authorized to use the Software.
+-00020  *
+-00021  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
+-00022  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+-00023  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+-00024  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
+-00025  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+-00026  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+-00027  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+-00028  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+-00029  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+-00030  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+-00031  * DAMAGE.
+-00032  * ========================================================================== */
+-00033 #ifndef DWC_DEVICE_ONLY
+-00034 #ifndef __DWC_HCD_H__
+-00035 #define __DWC_HCD_H__
+-00036 
+-00037 #include <usb.h>
+-00038 #include "dwc_otg_hcd_if.h"
+-00039 #include "dwc_otg_core_if.h"
+-00040 #include "dwc_list.h"
+-00041 #include "dwc_otg_cil.h"
+-00042 
+-00055 struct dwc_otg_hcd_pipe_info {
+-00056         uint8_t dev_addr;
+-00057         uint8_t ep_num;
+-00058         uint8_t pipe_type;
+-00059         uint8_t pipe_dir;
+-00060         uint16_t mps;
+-00061 };
+-00062 
+-00063 struct dwc_otg_hcd_iso_packet_desc {
+-00064         uint32_t offset;
+-00065         uint32_t length;
+-00066         uint32_t actual_length;
+-00067         uint32_t status;
+-00068 };
+-00069 
+-00070 struct dwc_otg_qtd;
+-00071 
+-00072 struct dwc_otg_hcd_urb {
+-00073         void *priv;
+-00074         struct dwc_otg_qtd *qtd;
+-00075         void *buf;
+-00076         dwc_dma_t dma;
+-00077         void *setup_packet;
+-00078         dwc_dma_t setup_dma;
+-00079         uint32_t length;
+-00080         uint32_t actual_length;
+-00081         uint32_t status;
+-00082         uint32_t error_count;
+-00083         uint32_t packet_count;
+-00084         uint32_t flags;
+-00085         uint16_t interval;
+-00086         struct dwc_otg_hcd_pipe_info pipe_info;
+-00087         struct dwc_otg_hcd_iso_packet_desc iso_descs[0];
+-00088 };
+-00089 
+-00090 static inline uint8_t dwc_otg_hcd_get_ep_num(struct dwc_otg_hcd_pipe_info *pipe)
+-00091 {
+-00092         return pipe->ep_num;
+-00093 }
+-00094 
+-00095 static inline uint8_t dwc_otg_hcd_get_pipe_type(struct dwc_otg_hcd_pipe_info
+-00096                                                 *pipe)
+-00097 {
+-00098         return pipe->pipe_type;
+-00099 }
+-00100 
+-00101 static inline uint16_t dwc_otg_hcd_get_mps(struct dwc_otg_hcd_pipe_info *pipe)
+-00102 {
+-00103         return pipe->mps;
+-00104 }
+-00105 
+-00106 static inline uint8_t dwc_otg_hcd_get_dev_addr(struct dwc_otg_hcd_pipe_info
+-00107                                                *pipe)
+-00108 {
+-00109         return pipe->dev_addr;
+-00110 }
+-00111 
+-00112 static inline uint8_t dwc_otg_hcd_is_pipe_isoc(struct dwc_otg_hcd_pipe_info
+-00113                                                *pipe)
+-00114 {
+-00115         return (pipe->pipe_type == UE_ISOCHRONOUS);
+-00116 }
+-00117 
+-00118 static inline uint8_t dwc_otg_hcd_is_pipe_int(struct dwc_otg_hcd_pipe_info
+-00119                                               *pipe)
+-00120 {
+-00121         return (pipe->pipe_type == UE_INTERRUPT);
+-00122 }
+-00123 
+-00124 static inline uint8_t dwc_otg_hcd_is_pipe_bulk(struct dwc_otg_hcd_pipe_info
+-00125                                                *pipe)
+-00126 {
+-00127         return (pipe->pipe_type == UE_BULK);
+-00128 }
+-00129 
+-00130 static inline uint8_t dwc_otg_hcd_is_pipe_control(struct dwc_otg_hcd_pipe_info
+-00131                                                   *pipe)
+-00132 {
+-00133         return (pipe->pipe_type == UE_CONTROL);
+-00134 }
+-00135 
+-00136 static inline uint8_t dwc_otg_hcd_is_pipe_in(struct dwc_otg_hcd_pipe_info *pipe)
+-00137 {
+-00138         return (pipe->pipe_dir == UE_DIR_IN);
+-00139 }
+-00140 
+-00141 static inline uint8_t dwc_otg_hcd_is_pipe_out(struct dwc_otg_hcd_pipe_info
+-00142                                               *pipe)
+-00143 {
+-00144         return (!dwc_otg_hcd_is_pipe_in(pipe));
+-00145 }
+-00146 
+-00147 static inline void dwc_otg_hcd_fill_pipe(struct dwc_otg_hcd_pipe_info *pipe,
+-00148                                          uint8_t devaddr, uint8_t ep_num,
+-00149                                          uint8_t pipe_type, uint8_t pipe_dir,
+-00150                                          uint16_t mps)
+-00151 {
+-00152         pipe->dev_addr = devaddr;
+-00153         pipe->ep_num = ep_num;
+-00154         pipe->pipe_type = pipe_type;
+-00155         pipe->pipe_dir = pipe_dir;
+-00156         pipe->mps = mps;
+-00157 }
+-00158 
+-00162 typedef enum dwc_otg_control_phase {
+-00163         DWC_OTG_CONTROL_SETUP,
+-00164         DWC_OTG_CONTROL_DATA,
+-00165         DWC_OTG_CONTROL_STATUS
+-00166 } dwc_otg_control_phase_e;
+-00167 
+-00169 typedef enum dwc_otg_transaction_type {
+-00170         DWC_OTG_TRANSACTION_NONE,
+-00171         DWC_OTG_TRANSACTION_PERIODIC,
+-00172         DWC_OTG_TRANSACTION_NON_PERIODIC,
+-00173         DWC_OTG_TRANSACTION_ALL
+-00174 } dwc_otg_transaction_type_e;
+-00175 
+-00176 struct dwc_otg_qh;
+-00177 
+-00191 typedef struct dwc_otg_qtd {
+-00199         uint8_t data_toggle;
+-00200 
+-00202         dwc_otg_control_phase_e control_phase;
+-00203 
+-00206         uint8_t complete_split;
+-00207 
+-00209         uint32_t ssplit_out_xfer_count;
+-00210 
+-00215         uint8_t error_count;
+-00216 
+-00224         uint16_t isoc_frame_index;
+-00225 
+-00227         uint8_t isoc_split_pos;
+-00228 
+-00230         uint16_t isoc_split_offset;
+-00231 
+-00233         struct dwc_otg_hcd_urb *urb;
+-00234 
+-00235         struct dwc_otg_qh *qh;
+-00236 
+-00238          DWC_CIRCLEQ_ENTRY(dwc_otg_qtd) qtd_list_entry;
+-00239 
+-00241         uint8_t in_process;
+-00242 
+-00244         uint8_t n_desc;
+-00245         
+-00250         uint16_t isoc_frame_index_last;
+-00251         
+-00252 } dwc_otg_qtd_t;
+-00253 
+-00254 DWC_CIRCLEQ_HEAD(dwc_otg_qtd_list, dwc_otg_qtd);
+-00255 
+-00261 typedef struct dwc_otg_qh {
+-00270         uint8_t ep_type;
+-00271         uint8_t ep_is_in;
+-00272 
+-00274         uint16_t maxp;
+-00275 
+-00283         uint8_t dev_speed;
+-00284 
+-00292         uint8_t data_toggle;
+-00293 
+-00295         uint8_t ping_state;
+-00296 
+-00300         struct dwc_otg_qtd_list qtd_list;
+-00301 
+-00303         struct dwc_hc *channel;
+-00304 
+-00306         uint8_t do_split;
+-00307 
+-00312         uint16_t usecs;
+-00313 
+-00315         uint16_t interval;
+-00316 
+-00321         uint16_t sched_frame;
+-00322 
+-00324         uint16_t start_split_frame;
+-00325 
+-00332         uint8_t *dw_align_buf;
+-00333         dwc_dma_t dw_align_buf_dma;
+-00334         
+-00336         dwc_list_link_t qh_list_entry;
+-00337         
+-00342         dwc_otg_host_dma_desc_t *desc_list;
+-00343         
+-00345         dwc_dma_t desc_list_dma;
+-00346         
+-00352         uint32_t *n_bytes;
+-00353         
+-00355         uint16_t ntd;
+-00356         
+-00358         uint8_t td_first;
+-00360         uint8_t td_last;
+-00361         
+-00364 } dwc_otg_qh_t;
+-00365 
+-00366 DWC_CIRCLEQ_HEAD(hc_list, dwc_hc);
+-00367 
+-00372 struct dwc_otg_hcd {
+-00374         dwc_otg_core_if_t *core_if;
+-00375 
+-00377         struct dwc_otg_hcd_function_ops *fops;
+-00378 
+-00380         volatile union dwc_otg_hcd_internal_flags {
+-00381                 uint32_t d32;
+-00382                 struct {
+-00383                         unsigned port_connect_status_change:1;
+-00384                         unsigned port_connect_status:1;
+-00385                         unsigned port_reset_change:1;
+-00386                         unsigned port_enable_change:1;
+-00387                         unsigned port_suspend_change:1;
+-00388                         unsigned port_over_current_change:1;
+-00389                         unsigned port_l1_change:1;
+-00390                         unsigned reserved:26;
+-00391                 } b;
+-00392         } flags;
+-00393 
+-00399         dwc_list_link_t non_periodic_sched_inactive;
+-00400 
+-00406         dwc_list_link_t non_periodic_sched_active;
+-00407 
+-00412         dwc_list_link_t *non_periodic_qh_ptr;
+-00413 
+-00428         dwc_list_link_t periodic_sched_inactive;
+-00429 
+-00437         dwc_list_link_t periodic_sched_ready;
+-00438 
+-00446         dwc_list_link_t periodic_sched_assigned;
+-00447 
+-00457         dwc_list_link_t periodic_sched_queued;
+-00458 
+-00464         uint16_t periodic_usecs;
+-00465 
+-00470         uint16_t frame_number;
+-00471 
+-00476         struct hc_list free_hc_list;
+-00483         int periodic_channels;
+-00484 
+-00488         int non_periodic_channels;
+-00489 
+-00495         struct dwc_hc *hc_ptr_array[MAX_EPS_CHANNELS];
+-00496 
+-00502         uint8_t *status_buf;
+-00503 
+-00507         dma_addr_t status_buf_dma;
+-00508 #define DWC_OTG_HCD_STATUS_BUF_SIZE 64
+-00509 
+-00515         dwc_timer_t *conn_timer;
+-00516 
+-00517         /* Tasket to do a reset */
+-00518         dwc_tasklet_t *reset_tasklet;
+-00519 
+-00520         /*  */
+-00521         dwc_spinlock_t *lock;
+-00522 
+-00526         void *priv;
+-00527 
+-00528         uint8_t otg_port;
+-00529 
+-00531         uint32_t *frame_list;
+-00532 
+-00534         dma_addr_t frame_list_dma;
+-00535 
+-00536 #ifdef DEBUG
+-00537         uint32_t frrem_samples;
+-00538         uint64_t frrem_accum;
+-00539 
+-00540         uint32_t hfnum_7_samples_a;
+-00541         uint64_t hfnum_7_frrem_accum_a;
+-00542         uint32_t hfnum_0_samples_a;
+-00543         uint64_t hfnum_0_frrem_accum_a;
+-00544         uint32_t hfnum_other_samples_a;
+-00545         uint64_t hfnum_other_frrem_accum_a;
+-00546 
+-00547         uint32_t hfnum_7_samples_b;
+-00548         uint64_t hfnum_7_frrem_accum_b;
+-00549         uint32_t hfnum_0_samples_b;
+-00550         uint64_t hfnum_0_frrem_accum_b;
+-00551         uint32_t hfnum_other_samples_b;
+-00552         uint64_t hfnum_other_frrem_accum_b;
+-00553 #endif
+-00554 };
+-00555 
+-00558 extern dwc_otg_transaction_type_e dwc_otg_hcd_select_transactions(dwc_otg_hcd_t
+-00559                                                                   * hcd);
+-00560 extern void dwc_otg_hcd_queue_transactions(dwc_otg_hcd_t * hcd,
+-00561                                     dwc_otg_transaction_type_e tr_type);
+-00562 
+-00567 extern int32_t dwc_otg_hcd_handle_intr(dwc_otg_hcd_t * dwc_otg_hcd);
+-00568 extern int32_t dwc_otg_hcd_handle_sof_intr(dwc_otg_hcd_t * dwc_otg_hcd);
+-00569 extern int32_t dwc_otg_hcd_handle_rx_status_q_level_intr(dwc_otg_hcd_t *
+-00570                                                          dwc_otg_hcd);
+-00571 extern int32_t dwc_otg_hcd_handle_np_tx_fifo_empty_intr(dwc_otg_hcd_t *
+-00572                                                         dwc_otg_hcd);
+-00573 extern int32_t dwc_otg_hcd_handle_perio_tx_fifo_empty_intr(dwc_otg_hcd_t *
+-00574                                                            dwc_otg_hcd);
+-00575 extern int32_t dwc_otg_hcd_handle_incomplete_periodic_intr(dwc_otg_hcd_t *
+-00576                                                            dwc_otg_hcd);
+-00577 extern int32_t dwc_otg_hcd_handle_port_intr(dwc_otg_hcd_t * dwc_otg_hcd);
+-00578 extern int32_t dwc_otg_hcd_handle_conn_id_status_change_intr(dwc_otg_hcd_t *
+-00579                                                              dwc_otg_hcd);
+-00580 extern int32_t dwc_otg_hcd_handle_disconnect_intr(dwc_otg_hcd_t * dwc_otg_hcd);
+-00581 extern int32_t dwc_otg_hcd_handle_hc_intr(dwc_otg_hcd_t * dwc_otg_hcd);
+-00582 extern int32_t dwc_otg_hcd_handle_hc_n_intr(dwc_otg_hcd_t * dwc_otg_hcd,
+-00583                                             uint32_t num);
+-00584 extern int32_t dwc_otg_hcd_handle_session_req_intr(dwc_otg_hcd_t * dwc_otg_hcd);
+-00585 extern int32_t dwc_otg_hcd_handle_wakeup_detected_intr(dwc_otg_hcd_t *
+-00586                                                        dwc_otg_hcd);
+-00592 /* Implemented in dwc_otg_hcd_queue.c */
+-00593 extern dwc_otg_qh_t *dwc_otg_hcd_qh_create(dwc_otg_hcd_t * hcd,
+-00594                                            dwc_otg_hcd_urb_t * urb);
+-00595 extern void dwc_otg_hcd_qh_free(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh);
+-00596 extern int dwc_otg_hcd_qh_add(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh);
+-00597 extern void dwc_otg_hcd_qh_remove(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh);
+-00598 extern void dwc_otg_hcd_qh_deactivate(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh,
+-00599                                       int sched_csplit);
+-00600 
+-00602 static inline void dwc_otg_hcd_qh_remove_and_free(dwc_otg_hcd_t * hcd,
+-00603                                                   dwc_otg_qh_t * qh)
+-00604 {
+-00605         dwc_otg_hcd_qh_remove(hcd, qh);
+-00606         dwc_otg_hcd_qh_free(hcd, qh);
+-00607 }
+-00608 
+-00611 static inline dwc_otg_qh_t *dwc_otg_hcd_qh_alloc(void)
+-00612 {
+-00613         return (dwc_otg_qh_t *) dwc_alloc(sizeof(dwc_otg_qh_t));
+-00614 }
+-00615 
+-00616 extern dwc_otg_qtd_t *dwc_otg_hcd_qtd_create(dwc_otg_hcd_urb_t * urb);
+-00617 extern void dwc_otg_hcd_qtd_init(dwc_otg_qtd_t * qtd, dwc_otg_hcd_urb_t * urb);
+-00618 extern int dwc_otg_hcd_qtd_add(dwc_otg_qtd_t * qtd, dwc_otg_hcd_t * dwc_otg_hcd,
+-00619                                dwc_otg_qh_t ** qh);
+-00620 
+-00623 static inline dwc_otg_qtd_t *dwc_otg_hcd_qtd_alloc(void)
+-00624 {
+-00625         return (dwc_otg_qtd_t *) dwc_alloc(sizeof(dwc_otg_qtd_t));
+-00626 }
+-00627 
+-00631 static inline void dwc_otg_hcd_qtd_free(dwc_otg_qtd_t * qtd)
+-00632 {
+-00633         dwc_free(qtd);
+-00634 }
+-00635 
+-00641 static inline void dwc_otg_hcd_qtd_remove(dwc_otg_hcd_t * hcd,
+-00642                                           dwc_otg_qtd_t * qtd,
+-00643                                           dwc_otg_qh_t * qh)
+-00644 {
+-00645         uint64_t flags;
+-00646         DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
+-00647         DWC_CIRCLEQ_REMOVE(&qh->qtd_list, qtd, qtd_list_entry);
+-00648         DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
+-00649 }
+-00650 
+-00652 static inline void dwc_otg_hcd_qtd_remove_and_free(dwc_otg_hcd_t * hcd,
+-00653                                                    dwc_otg_qtd_t * qtd,
+-00654                                                    dwc_otg_qh_t * qh)
+-00655 {
+-00656         dwc_otg_hcd_qtd_remove(hcd, qtd, qh);
+-00657         dwc_otg_hcd_qtd_free(qtd);
+-00658 }
+-00659 
+-00665 extern void dwc_otg_hcd_start_xfer_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh);
+-00666 extern void dwc_otg_hcd_complete_xfer_ddma(dwc_otg_hcd_t * hcd,
+-00667                                            dwc_hc_t * hc,
+-00668                                            dwc_otg_hc_regs_t * hc_regs,
+-00669                                            dwc_otg_halt_status_e halt_status);
+-00670 
+-00671 extern int dwc_otg_hcd_qh_init_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh);
+-00672 extern void dwc_otg_hcd_qh_free_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh);
+-00673 
+-00678 dwc_otg_qh_t *dwc_urb_to_qh(dwc_otg_hcd_urb_t * urb);
+-00681 #ifdef CONFIG_USB_DWC_OTG_LPM
+-00682 extern int dwc_otg_hcd_get_hc_for_lpm_tran(dwc_otg_hcd_t * hcd,
+-00683                                            uint8_t devaddr);
+-00684 extern void dwc_otg_hcd_free_hc_from_lpm(dwc_otg_hcd_t * hcd);
+-00685 #endif
+-00686 
+-00688 #define dwc_list_to_qh(_list_head_ptr_) container_of(_list_head_ptr_, dwc_otg_qh_t, qh_list_entry)
+-00689 
+-00691 #define dwc_list_to_qtd(_list_head_ptr_) container_of(_list_head_ptr_, dwc_otg_qtd_t, qtd_list_entry)
+-00692 
+-00694 #define dwc_qh_is_non_per(_qh_ptr_) ((_qh_ptr_->ep_type == UE_BULK) || \
+-00695                                      (_qh_ptr_->ep_type == UE_CONTROL))
+-00696 
+-00698 #define dwc_hb_mult(wMaxPacketSize) (1 + (((wMaxPacketSize) >> 11) & 0x03))
+-00699 
+-00701 #define dwc_max_packet(wMaxPacketSize) ((wMaxPacketSize) & 0x07ff)
+-00702 
+-00708 static inline int dwc_frame_num_le(uint16_t frame1, uint16_t frame2)
+-00709 {
+-00710         return ((frame2 - frame1) & DWC_HFNUM_MAX_FRNUM) <=
+-00711             (DWC_HFNUM_MAX_FRNUM >> 1);
+-00712 }
+-00713 
+-00719 static inline int dwc_frame_num_gt(uint16_t frame1, uint16_t frame2)
+-00720 {
+-00721         return (frame1 != frame2) &&
+-00722             (((frame1 - frame2) & DWC_HFNUM_MAX_FRNUM) <
+-00723              (DWC_HFNUM_MAX_FRNUM >> 1));
+-00724 }
+-00725 
+-00730 static inline uint16_t dwc_frame_num_inc(uint16_t frame, uint16_t inc)
+-00731 {
+-00732         return (frame + inc) & DWC_HFNUM_MAX_FRNUM;
+-00733 }
+-00734 
+-00735 static inline uint16_t dwc_full_frame_num(uint16_t frame)
+-00736 {
+-00737         return (frame & DWC_HFNUM_MAX_FRNUM) >> 3;
+-00738 }
+-00739 
+-00740 static inline uint16_t dwc_micro_frame_num(uint16_t frame)
+-00741 {
+-00742         return frame & 0x7;
+-00743 }
+-00744 
+-00745 void dwc_otg_hcd_save_data_toggle(dwc_hc_t * hc,
+-00746                                   dwc_otg_hc_regs_t * hc_regs, 
+-00747                                   dwc_otg_qtd_t * qtd);
+-00748 
+-00749 #ifdef DEBUG
+-00750 
+-00759 #define dwc_sample_frrem(_hcd, _qh, _letter) \
+-00760 { \
+-00761         hfnum_data_t hfnum; \
+-00762         dwc_otg_qtd_t *qtd; \
+-00763         qtd = list_entry(_qh->qtd_list.next, dwc_otg_qtd_t, qtd_list_entry); \
+-00764         if (usb_pipeint(qtd->urb->pipe) && _qh->start_split_frame != 0 && !qtd->complete_split) { \
+-00765                 hfnum.d32 = dwc_read_reg32(&_hcd->core_if->host_if->host_global_regs->hfnum); \
+-00766                 switch (hfnum.b.frnum & 0x7) { \
+-00767                 case 7: \
+-00768                         _hcd->hfnum_7_samples_##_letter++; \
+-00769                         _hcd->hfnum_7_frrem_accum_##_letter += hfnum.b.frrem; \
+-00770                         break; \
+-00771                 case 0: \
+-00772                         _hcd->hfnum_0_samples_##_letter++; \
+-00773                         _hcd->hfnum_0_frrem_accum_##_letter += hfnum.b.frrem; \
+-00774                         break; \
+-00775                 default: \
+-00776                         _hcd->hfnum_other_samples_##_letter++; \
+-00777                         _hcd->hfnum_other_frrem_accum_##_letter += hfnum.b.frrem; \
+-00778                         break; \
+-00779                 } \
+-00780         } \
+-00781 }
+-00782 #else
+-00783 #define dwc_sample_frrem(_hcd, _qh, _letter)
+-00784 #endif
+-00785 #endif
+-00786 #endif                          /* DWC_DEVICE_ONLY */
+-
    Generated on Tue May 5 02:22:48 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++
    Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
    ++

    dwc_otg_hcd.h

    Go to the documentation of this file.
    00001 /* ==========================================================================
++00002  * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd.h $
++00003  * $Revision: #58 $
++00004  * $Date: 2011/09/15 $
++00005  * $Change: 1846647 $
++00006  *
++00007  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
++00008  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
++00009  * otherwise expressly agreed to in writing between Synopsys and you.
++00010  *
++00011  * The Software IS NOT an item of Licensed Software or Licensed Product under
++00012  * any End User Software License Agreement or Agreement for Licensed Product
++00013  * with Synopsys or any supplement thereto. You are permitted to use and
++00014  * redistribute this Software in source and binary forms, with or without
++00015  * modification, provided that redistributions of source code must retain this
++00016  * notice. You may not view, use, disclose, copy or distribute this file or
++00017  * any information contained herein except pursuant to this license grant from
++00018  * Synopsys. If you do not agree with this notice, including the disclaimer
++00019  * below, then you are not authorized to use the Software.
++00020  *
++00021  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
++00022  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++00023  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++00024  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
++00025  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++00026  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
++00027  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
++00028  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
++00029  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
++00030  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
++00031  * DAMAGE.
++00032  * ========================================================================== */
++00033 #ifndef DWC_DEVICE_ONLY
++00034 #ifndef __DWC_HCD_H__
++00035 #define __DWC_HCD_H__
++00036 
++00037 #include "dwc_otg_os_dep.h"
++00038 #include "usb.h"
++00039 #include "dwc_otg_hcd_if.h"
++00040 #include "dwc_otg_core_if.h"
++00041 #include "dwc_list.h"
++00042 #include "dwc_otg_cil.h"
++00043 
++00056 struct dwc_otg_hcd_pipe_info {
++00057         uint8_t dev_addr;
++00058         uint8_t ep_num;
++00059         uint8_t pipe_type;
++00060         uint8_t pipe_dir;
++00061         uint16_t mps;
++00062 };
++00063 
++00064 struct dwc_otg_hcd_iso_packet_desc {
++00065         uint32_t offset;
++00066         uint32_t length;
++00067         uint32_t actual_length;
++00068         uint32_t status;
++00069 };
++00070 
++00071 struct dwc_otg_qtd;
++00072 
++00073 struct dwc_otg_hcd_urb {
++00074         void *priv;
++00075         struct dwc_otg_qtd *qtd;
++00076         void *buf;
++00077         dwc_dma_t dma;
++00078         void *setup_packet;
++00079         dwc_dma_t setup_dma;
++00080         uint32_t length;
++00081         uint32_t actual_length;
++00082         uint32_t status;
++00083         uint32_t error_count;
++00084         uint32_t packet_count;
++00085         uint32_t flags;
++00086         uint16_t interval;
++00087         struct dwc_otg_hcd_pipe_info pipe_info;
++00088         struct dwc_otg_hcd_iso_packet_desc iso_descs[0];
++00089 };
++00090 
++00091 static inline uint8_t dwc_otg_hcd_get_ep_num(struct dwc_otg_hcd_pipe_info *pipe)
++00092 {
++00093         return pipe->ep_num;
++00094 }
++00095 
++00096 static inline uint8_t dwc_otg_hcd_get_pipe_type(struct dwc_otg_hcd_pipe_info
++00097                                                 *pipe)
++00098 {
++00099         return pipe->pipe_type;
++00100 }
++00101 
++00102 static inline uint16_t dwc_otg_hcd_get_mps(struct dwc_otg_hcd_pipe_info *pipe)
++00103 {
++00104         return pipe->mps;
++00105 }
++00106 
++00107 static inline uint8_t dwc_otg_hcd_get_dev_addr(struct dwc_otg_hcd_pipe_info
++00108                                                *pipe)
++00109 {
++00110         return pipe->dev_addr;
++00111 }
++00112 
++00113 static inline uint8_t dwc_otg_hcd_is_pipe_isoc(struct dwc_otg_hcd_pipe_info
++00114                                                *pipe)
++00115 {
++00116         return (pipe->pipe_type == UE_ISOCHRONOUS);
++00117 }
++00118 
++00119 static inline uint8_t dwc_otg_hcd_is_pipe_int(struct dwc_otg_hcd_pipe_info
++00120                                               *pipe)
++00121 {
++00122         return (pipe->pipe_type == UE_INTERRUPT);
++00123 }
++00124 
++00125 static inline uint8_t dwc_otg_hcd_is_pipe_bulk(struct dwc_otg_hcd_pipe_info
++00126                                                *pipe)
++00127 {
++00128         return (pipe->pipe_type == UE_BULK);
++00129 }
++00130 
++00131 static inline uint8_t dwc_otg_hcd_is_pipe_control(struct dwc_otg_hcd_pipe_info
++00132                                                   *pipe)
++00133 {
++00134         return (pipe->pipe_type == UE_CONTROL);
++00135 }
++00136 
++00137 static inline uint8_t dwc_otg_hcd_is_pipe_in(struct dwc_otg_hcd_pipe_info *pipe)
++00138 {
++00139         return (pipe->pipe_dir == UE_DIR_IN);
++00140 }
++00141 
++00142 static inline uint8_t dwc_otg_hcd_is_pipe_out(struct dwc_otg_hcd_pipe_info
++00143                                               *pipe)
++00144 {
++00145         return (!dwc_otg_hcd_is_pipe_in(pipe));
++00146 }
++00147 
++00148 static inline void dwc_otg_hcd_fill_pipe(struct dwc_otg_hcd_pipe_info *pipe,
++00149                                          uint8_t devaddr, uint8_t ep_num,
++00150                                          uint8_t pipe_type, uint8_t pipe_dir,
++00151                                          uint16_t mps)
++00152 {
++00153         pipe->dev_addr = devaddr;
++00154         pipe->ep_num = ep_num;
++00155         pipe->pipe_type = pipe_type;
++00156         pipe->pipe_dir = pipe_dir;
++00157         pipe->mps = mps;
++00158 }
++00159 
++00163 typedef enum dwc_otg_control_phase {
++00164         DWC_OTG_CONTROL_SETUP,
++00165         DWC_OTG_CONTROL_DATA,
++00166         DWC_OTG_CONTROL_STATUS
++00167 } dwc_otg_control_phase_e;
++00168 
++00170 typedef enum dwc_otg_transaction_type {
++00171         DWC_OTG_TRANSACTION_NONE,
++00172         DWC_OTG_TRANSACTION_PERIODIC,
++00173         DWC_OTG_TRANSACTION_NON_PERIODIC,
++00174         DWC_OTG_TRANSACTION_ALL
++00175 } dwc_otg_transaction_type_e;
++00176 
++00177 struct dwc_otg_qh;
++00178 
++00192 typedef struct dwc_otg_qtd {
++00200         uint8_t data_toggle;
++00201 
++00203         dwc_otg_control_phase_e control_phase;
++00204 
++00207         uint8_t complete_split;
++00208 
++00210         uint32_t ssplit_out_xfer_count;
++00211 
++00216         uint8_t error_count;
++00217 
++00225         uint16_t isoc_frame_index;
++00226 
++00228         uint8_t isoc_split_pos;
++00229 
++00231         uint16_t isoc_split_offset;
++00232 
++00234         struct dwc_otg_hcd_urb *urb;
++00235 
++00236         struct dwc_otg_qh *qh;
++00237 
++00239          DWC_CIRCLEQ_ENTRY(dwc_otg_qtd) qtd_list_entry;
++00240 
++00242         uint8_t in_process;
++00243 
++00245         uint8_t n_desc;
++00246 
++00251         uint16_t isoc_frame_index_last;
++00252 
++00253 } dwc_otg_qtd_t;
++00254 
++00255 DWC_CIRCLEQ_HEAD(dwc_otg_qtd_list, dwc_otg_qtd);
++00256 
++00262 typedef struct dwc_otg_qh {
++00271         uint8_t ep_type;
++00272         uint8_t ep_is_in;
++00273 
++00275         uint16_t maxp;
++00276 
++00284         uint8_t dev_speed;
++00285 
++00293         uint8_t data_toggle;
++00294 
++00296         uint8_t ping_state;
++00297 
++00301         struct dwc_otg_qtd_list qtd_list;
++00302 
++00304         struct dwc_hc *channel;
++00305 
++00307         uint8_t do_split;
++00308 
++00313         uint16_t usecs;
++00314 
++00316         uint16_t interval;
++00317 
++00322         uint16_t sched_frame;
++00323 
++00325         uint16_t start_split_frame;
++00326 
++00333         uint8_t *dw_align_buf;
++00334         dwc_dma_t dw_align_buf_dma;
++00335 
++00337         dwc_list_link_t qh_list_entry;
++00338 
++00343         dwc_otg_host_dma_desc_t *desc_list;
++00344 
++00346         dwc_dma_t desc_list_dma;
++00347 
++00353         uint32_t *n_bytes;
++00354 
++00356         uint16_t ntd;
++00357 
++00359         uint8_t td_first;
++00361         uint8_t td_last;
++00362 
++00365 } dwc_otg_qh_t;
++00366 
++00367 DWC_CIRCLEQ_HEAD(hc_list, dwc_hc);
++00368 
++00373 struct dwc_otg_hcd {
++00375         struct dwc_otg_device *otg_dev;
++00377         dwc_otg_core_if_t *core_if;
++00378 
++00380         struct dwc_otg_hcd_function_ops *fops;
++00381 
++00383         volatile union dwc_otg_hcd_internal_flags {
++00384                 uint32_t d32;
++00385                 struct {
++00386                         unsigned port_connect_status_change:1;
++00387                         unsigned port_connect_status:1;
++00388                         unsigned port_reset_change:1;
++00389                         unsigned port_enable_change:1;
++00390                         unsigned port_suspend_change:1;
++00391                         unsigned port_over_current_change:1;
++00392                         unsigned port_l1_change:1;
++00393                         unsigned reserved:26;
++00394                 } b;
++00395         } flags;
++00396 
++00402         dwc_list_link_t non_periodic_sched_inactive;
++00403 
++00409         dwc_list_link_t non_periodic_sched_active;
++00410 
++00415         dwc_list_link_t *non_periodic_qh_ptr;
++00416 
++00431         dwc_list_link_t periodic_sched_inactive;
++00432 
++00440         dwc_list_link_t periodic_sched_ready;
++00441 
++00449         dwc_list_link_t periodic_sched_assigned;
++00450 
++00460         dwc_list_link_t periodic_sched_queued;
++00461 
++00467         uint16_t periodic_usecs;
++00468 
++00473         uint16_t frame_number;
++00474 
++00478         uint16_t periodic_qh_count;
++00479 
++00484         struct hc_list free_hc_list;
++00491         int periodic_channels;
++00492 
++00496         int non_periodic_channels;
++00497 
++00503         struct dwc_hc *hc_ptr_array[MAX_EPS_CHANNELS];
++00504 
++00510         uint8_t *status_buf;
++00511 
++00515         dma_addr_t status_buf_dma;
++00516 #define DWC_OTG_HCD_STATUS_BUF_SIZE 64
++00517 
++00523         dwc_timer_t *conn_timer;
++00524 
++00525         /* Tasket to do a reset */
++00526         dwc_tasklet_t *reset_tasklet;
++00527 
++00528         /*  */
++00529         dwc_spinlock_t *lock;
++00530 
++00534         void *priv;
++00535 
++00536         uint8_t otg_port;
++00537 
++00539         uint32_t *frame_list;
++00540 
++00542         dma_addr_t frame_list_dma;
++00543 
++00544 #ifdef DEBUG
++00545         uint32_t frrem_samples;
++00546         uint64_t frrem_accum;
++00547 
++00548         uint32_t hfnum_7_samples_a;
++00549         uint64_t hfnum_7_frrem_accum_a;
++00550         uint32_t hfnum_0_samples_a;
++00551         uint64_t hfnum_0_frrem_accum_a;
++00552         uint32_t hfnum_other_samples_a;
++00553         uint64_t hfnum_other_frrem_accum_a;
++00554 
++00555         uint32_t hfnum_7_samples_b;
++00556         uint64_t hfnum_7_frrem_accum_b;
++00557         uint32_t hfnum_0_samples_b;
++00558         uint64_t hfnum_0_frrem_accum_b;
++00559         uint32_t hfnum_other_samples_b;
++00560         uint64_t hfnum_other_frrem_accum_b;
++00561 #endif
++00562 };
++00563 
++00566 extern dwc_otg_transaction_type_e dwc_otg_hcd_select_transactions(dwc_otg_hcd_t
++00567                                                                   * hcd);
++00568 extern void dwc_otg_hcd_queue_transactions(dwc_otg_hcd_t * hcd,
++00569                                            dwc_otg_transaction_type_e tr_type);
++00570 
++00575 extern int32_t dwc_otg_hcd_handle_intr(dwc_otg_hcd_t * dwc_otg_hcd);
++00576 extern int32_t dwc_otg_hcd_handle_sof_intr(dwc_otg_hcd_t * dwc_otg_hcd);
++00577 extern int32_t dwc_otg_hcd_handle_rx_status_q_level_intr(dwc_otg_hcd_t *
++00578                                                          dwc_otg_hcd);
++00579 extern int32_t dwc_otg_hcd_handle_np_tx_fifo_empty_intr(dwc_otg_hcd_t *
++00580                                                         dwc_otg_hcd);
++00581 extern int32_t dwc_otg_hcd_handle_perio_tx_fifo_empty_intr(dwc_otg_hcd_t *
++00582                                                            dwc_otg_hcd);
++00583 extern int32_t dwc_otg_hcd_handle_incomplete_periodic_intr(dwc_otg_hcd_t *
++00584                                                            dwc_otg_hcd);
++00585 extern int32_t dwc_otg_hcd_handle_port_intr(dwc_otg_hcd_t * dwc_otg_hcd);
++00586 extern int32_t dwc_otg_hcd_handle_conn_id_status_change_intr(dwc_otg_hcd_t *
++00587                                                              dwc_otg_hcd);
++00588 extern int32_t dwc_otg_hcd_handle_disconnect_intr(dwc_otg_hcd_t * dwc_otg_hcd);
++00589 extern int32_t dwc_otg_hcd_handle_hc_intr(dwc_otg_hcd_t * dwc_otg_hcd);
++00590 extern int32_t dwc_otg_hcd_handle_hc_n_intr(dwc_otg_hcd_t * dwc_otg_hcd,
++00591                                             uint32_t num);
++00592 extern int32_t dwc_otg_hcd_handle_session_req_intr(dwc_otg_hcd_t * dwc_otg_hcd);
++00593 extern int32_t dwc_otg_hcd_handle_wakeup_detected_intr(dwc_otg_hcd_t *
++00594                                                        dwc_otg_hcd);
++00600 /* Implemented in dwc_otg_hcd_queue.c */
++00601 extern dwc_otg_qh_t *dwc_otg_hcd_qh_create(dwc_otg_hcd_t * hcd,
++00602                                            dwc_otg_hcd_urb_t * urb, int atomic_alloc);
++00603 extern void dwc_otg_hcd_qh_free(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh);
++00604 extern int dwc_otg_hcd_qh_add(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh);
++00605 extern void dwc_otg_hcd_qh_remove(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh);
++00606 extern void dwc_otg_hcd_qh_deactivate(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh,
++00607                                       int sched_csplit);
++00608 
++00610 static inline void dwc_otg_hcd_qh_remove_and_free(dwc_otg_hcd_t * hcd,
++00611                                                   dwc_otg_qh_t * qh)
++00612 {
++00613         dwc_irqflags_t flags;
++00614         DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
++00615         dwc_otg_hcd_qh_remove(hcd, qh);
++00616         DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
++00617         dwc_otg_hcd_qh_free(hcd, qh);
++00618 }
++00619 
++00622 static inline dwc_otg_qh_t *dwc_otg_hcd_qh_alloc(int atomic_alloc)
++00623 {
++00624         if (atomic_alloc)
++00625                 return (dwc_otg_qh_t *) DWC_ALLOC_ATOMIC(sizeof(dwc_otg_qh_t));
++00626         else
++00627                 return (dwc_otg_qh_t *) DWC_ALLOC(sizeof(dwc_otg_qh_t));
++00628 }
++00629 
++00630 extern dwc_otg_qtd_t *dwc_otg_hcd_qtd_create(dwc_otg_hcd_urb_t * urb,
++00631                                              int atomic_alloc);
++00632 extern void dwc_otg_hcd_qtd_init(dwc_otg_qtd_t * qtd, dwc_otg_hcd_urb_t * urb);
++00633 extern int dwc_otg_hcd_qtd_add(dwc_otg_qtd_t * qtd, dwc_otg_hcd_t * dwc_otg_hcd,
++00634                                dwc_otg_qh_t ** qh, int atomic_alloc);
++00635 
++00638 static inline dwc_otg_qtd_t *dwc_otg_hcd_qtd_alloc(int atomic_alloc)
++00639 {
++00640         if (atomic_alloc)
++00641                 return (dwc_otg_qtd_t *) DWC_ALLOC_ATOMIC(sizeof(dwc_otg_qtd_t));
++00642         else
++00643                 return (dwc_otg_qtd_t *) DWC_ALLOC(sizeof(dwc_otg_qtd_t));
++00644 }
++00645 
++00649 static inline void dwc_otg_hcd_qtd_free(dwc_otg_qtd_t * qtd)
++00650 {
++00651         DWC_FREE(qtd);
++00652 }
++00653 
++00659 static inline void dwc_otg_hcd_qtd_remove(dwc_otg_hcd_t * hcd,
++00660                                           dwc_otg_qtd_t * qtd,
++00661                                           dwc_otg_qh_t * qh)
++00662 {
++00663         DWC_CIRCLEQ_REMOVE(&qh->qtd_list, qtd, qtd_list_entry);
++00664 }
++00665 
++00669 static inline void dwc_otg_hcd_qtd_remove_and_free(dwc_otg_hcd_t * hcd,
++00670                                                    dwc_otg_qtd_t * qtd,
++00671                                                    dwc_otg_qh_t * qh)
++00672 {
++00673         dwc_otg_hcd_qtd_remove(hcd, qtd, qh);
++00674         dwc_otg_hcd_qtd_free(qtd);
++00675 }
++00676 
++00682 extern void dwc_otg_hcd_start_xfer_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh);
++00683 extern void dwc_otg_hcd_complete_xfer_ddma(dwc_otg_hcd_t * hcd,
++00684                                            dwc_hc_t * hc,
++00685                                            dwc_otg_hc_regs_t * hc_regs,
++00686                                            dwc_otg_halt_status_e halt_status);
++00687 
++00688 extern int dwc_otg_hcd_qh_init_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh);
++00689 extern void dwc_otg_hcd_qh_free_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh);
++00690 
++00695 dwc_otg_qh_t *dwc_urb_to_qh(dwc_otg_hcd_urb_t * urb);
++00698 #ifdef CONFIG_USB_DWC_OTG_LPM
++00699 extern int dwc_otg_hcd_get_hc_for_lpm_tran(dwc_otg_hcd_t * hcd,
++00700                                            uint8_t devaddr);
++00701 extern void dwc_otg_hcd_free_hc_from_lpm(dwc_otg_hcd_t * hcd);
++00702 #endif
++00703 
++00705 #define dwc_list_to_qh(_list_head_ptr_) container_of(_list_head_ptr_, dwc_otg_qh_t, qh_list_entry)
++00706 
++00708 #define dwc_list_to_qtd(_list_head_ptr_) container_of(_list_head_ptr_, dwc_otg_qtd_t, qtd_list_entry)
++00709 
++00711 #define dwc_qh_is_non_per(_qh_ptr_) ((_qh_ptr_->ep_type == UE_BULK) || \
++00712                                      (_qh_ptr_->ep_type == UE_CONTROL))
++00713 
++00715 #define dwc_hb_mult(wMaxPacketSize) (1 + (((wMaxPacketSize) >> 11) & 0x03))
++00716 
++00718 #define dwc_max_packet(wMaxPacketSize) ((wMaxPacketSize) & 0x07ff)
++00719 
++00725 static inline int dwc_frame_num_le(uint16_t frame1, uint16_t frame2)
++00726 {
++00727         return ((frame2 - frame1) & DWC_HFNUM_MAX_FRNUM) <=
++00728             (DWC_HFNUM_MAX_FRNUM >> 1);
++00729 }
++00730 
++00736 static inline int dwc_frame_num_gt(uint16_t frame1, uint16_t frame2)
++00737 {
++00738         return (frame1 != frame2) &&
++00739             (((frame1 - frame2) & DWC_HFNUM_MAX_FRNUM) <
++00740              (DWC_HFNUM_MAX_FRNUM >> 1));
++00741 }
++00742 
++00747 static inline uint16_t dwc_frame_num_inc(uint16_t frame, uint16_t inc)
++00748 {
++00749         return (frame + inc) & DWC_HFNUM_MAX_FRNUM;
++00750 }
++00751 
++00752 static inline uint16_t dwc_full_frame_num(uint16_t frame)
++00753 {
++00754         return (frame & DWC_HFNUM_MAX_FRNUM) >> 3;
++00755 }
++00756 
++00757 static inline uint16_t dwc_micro_frame_num(uint16_t frame)
++00758 {
++00759         return frame & 0x7;
++00760 }
++00761 
++00762 void dwc_otg_hcd_save_data_toggle(dwc_hc_t * hc,
++00763                                   dwc_otg_hc_regs_t * hc_regs,
++00764                                   dwc_otg_qtd_t * qtd);
++00765 
++00766 #ifdef DEBUG
++00767 
++00776 #define dwc_sample_frrem(_hcd, _qh, _letter) \
++00777 { \
++00778         hfnum_data_t hfnum; \
++00779         dwc_otg_qtd_t *qtd; \
++00780         qtd = list_entry(_qh->qtd_list.next, dwc_otg_qtd_t, qtd_list_entry); \
++00781         if (usb_pipeint(qtd->urb->pipe) && _qh->start_split_frame != 0 && !qtd->complete_split) { \
++00782                 hfnum.d32 = DWC_READ_REG32(&_hcd->core_if->host_if->host_global_regs->hfnum); \
++00783                 switch (hfnum.b.frnum & 0x7) { \
++00784                 case 7: \
++00785                         _hcd->hfnum_7_samples_##_letter++; \
++00786                         _hcd->hfnum_7_frrem_accum_##_letter += hfnum.b.frrem; \
++00787                         break; \
++00788                 case 0: \
++00789                         _hcd->hfnum_0_samples_##_letter++; \
++00790                         _hcd->hfnum_0_frrem_accum_##_letter += hfnum.b.frrem; \
++00791                         break; \
++00792                 default: \
++00793                         _hcd->hfnum_other_samples_##_letter++; \
++00794                         _hcd->hfnum_other_frrem_accum_##_letter += hfnum.b.frrem; \
++00795                         break; \
++00796                 } \
++00797         } \
++00798 }
++00799 #else
++00800 #define dwc_sample_frrem(_hcd, _qh, _letter)
++00801 #endif
++00802 #endif
++00803 #endif /* DWC_DEVICE_ONLY */
++
    Generated on Thu Oct 27 03:56:37 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
    ++doxygen 1.3.9.1
    + + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__hcd_8h.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/dwc__otg__hcd_8h.html 2013-07-26 19:31:21.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__hcd_8h.html 2013-07-26 19:34:41.000000000 +0000 +@@ -2,38 +2,27 @@ + + DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_hcd.h File Reference + +- + +- +-
    +-
    +-
    +-
    ++ ++
    Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
    +

    dwc_otg_hcd.h File Reference

    This file contains the structures, constants, and interfaces for the Host Contoller Driver (HCD). More... +

    +-#include <usb.h>
    +-#include "dwc_otg_hcd_if.h"
    +-#include "dwc_otg_core_if.h"
    +-#include "dwc_list.h"
    +-#include "dwc_otg_cil.h"
    ++#include "dwc_otg_os_dep.h"
    ++#include "usb.h"
    ++#include "dwc_otg_hcd_if.h"
    ++#include "dwc_otg_core_if.h"
    ++#include "dwc_list.h"
    ++#include "dwc_otg_cil.h"
    + +

    + Go to the source code of this file. + + +- ++ + +- ++ + +- ++ + + + +@@ -48,164 +37,164 @@ + + + +- ++ + +- +- ++ ++ + +- ++ + +- ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ + +- ++ + +- +- ++ + +- + +- ++ + +- +- ++ ++ + + +- + +- + + +- ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + + +- ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- ++ + +- ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- ++ + +- ++ + + +- ++ + +- ++ + + +- ++ + + +- ++ + +- +- ++ ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ + +- +- ++ ++ + +- ++ + +- + + +- + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- + +- + +- ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- ++ + +- ++ + +

    Data Structures

    struct  dwc_otg_hcd_pipe_info
    struct  dwc_otg_hcd_pipe_info
    struct  dwc_otg_hcd_iso_packet_desc
    struct  dwc_otg_hcd_iso_packet_desc
    struct  dwc_otg_hcd_urb
    struct  dwc_otg_hcd_urb
    struct  dwc_otg_qtd
     Internal DWC HCD Flags. More...

    Transaction Execution Functions

    dwc_otg_transaction_type_e dwc_otg_hcd_select_transactions (dwc_otg_hcd_t *hcd)
    dwc_otg_transaction_type_e dwc_otg_hcd_select_transactions (dwc_otg_hcd_t *hcd)
     This function selects transactions from the HCD transfer schedule and assigns them to available host channels.
    void dwc_otg_hcd_queue_transactions (dwc_otg_hcd_t *hcd, dwc_otg_transaction_type_e tr_type)
     This function selects transactions from the HCD transfer schedule and assigns them to available host channels.
    void dwc_otg_hcd_queue_transactions (dwc_otg_hcd_t *hcd, dwc_otg_transaction_type_e tr_type)
     This function processes the currently active host channels and queues transactions for these channels to the DWC_otg controller.
     This function processes the currently active host channels and queues transactions for these channels to the DWC_otg controller.

    Interrupt Handler Functions

    int32_t dwc_otg_hcd_handle_intr (dwc_otg_hcd_t *dwc_otg_hcd)
    int32_t dwc_otg_hcd_handle_intr (dwc_otg_hcd_t *dwc_otg_hcd)
     This function handles interrupts for the HCD.
    int32_t dwc_otg_hcd_handle_sof_intr (dwc_otg_hcd_t *dwc_otg_hcd)
     This function handles interrupts for the HCD.
    int32_t dwc_otg_hcd_handle_sof_intr (dwc_otg_hcd_t *dwc_otg_hcd)
     Handles the start-of-frame interrupt in host mode.
    int32_t dwc_otg_hcd_handle_rx_status_q_level_intr (dwc_otg_hcd_t *dwc_otg_hcd)
     Handles the start-of-frame interrupt in host mode.
    int32_t dwc_otg_hcd_handle_rx_status_q_level_intr (dwc_otg_hcd_t *dwc_otg_hcd)
     Handles the Rx Status Queue Level Interrupt, which indicates that there is at least one packet in the Rx FIFO.
    int32_t dwc_otg_hcd_handle_np_tx_fifo_empty_intr (dwc_otg_hcd_t *dwc_otg_hcd)
     Handles the Rx Status Queue Level Interrupt, which indicates that there is at least one packet in the Rx FIFO.
    int32_t dwc_otg_hcd_handle_np_tx_fifo_empty_intr (dwc_otg_hcd_t *dwc_otg_hcd)
     This interrupt occurs when the non-periodic Tx FIFO is half-empty.
    int32_t dwc_otg_hcd_handle_perio_tx_fifo_empty_intr (dwc_otg_hcd_t *dwc_otg_hcd)
     This interrupt occurs when the non-periodic Tx FIFO is half-empty.
    int32_t dwc_otg_hcd_handle_perio_tx_fifo_empty_intr (dwc_otg_hcd_t *dwc_otg_hcd)
     This interrupt occurs when the periodic Tx FIFO is half-empty.
    ++
     This interrupt occurs when the periodic Tx FIFO is half-empty.
    + int32_t dwc_otg_hcd_handle_incomplete_periodic_intr (dwc_otg_hcd_t *dwc_otg_hcd)
    int32_t dwc_otg_hcd_handle_port_intr (dwc_otg_hcd_t *dwc_otg_hcd)
    int32_t dwc_otg_hcd_handle_port_intr (dwc_otg_hcd_t *dwc_otg_hcd)
     There are multiple conditions that can cause a port interrupt.
    ++
     There are multiple conditions that can cause a port interrupt.
    + int32_t dwc_otg_hcd_handle_conn_id_status_change_intr (dwc_otg_hcd_t *dwc_otg_hcd)
    ++
    + int32_t dwc_otg_hcd_handle_disconnect_intr (dwc_otg_hcd_t *dwc_otg_hcd)
    int32_t dwc_otg_hcd_handle_hc_intr (dwc_otg_hcd_t *dwc_otg_hcd)
    int32_t dwc_otg_hcd_handle_hc_intr (dwc_otg_hcd_t *dwc_otg_hcd)
     This interrupt indicates that one or more host channels has a pending interrupt.
    +-int32_t dwc_otg_hcd_handle_hc_n_intr (dwc_otg_hcd_t *dwc_otg_hcd, uint32_t num)
     This interrupt indicates that one or more host channels has a pending interrupt.
    ++int32_t dwc_otg_hcd_handle_hc_n_intr (dwc_otg_hcd_t *dwc_otg_hcd, uint32_t num)
     Handles interrupt for a specific Host Channel.
    ++
    + int32_t dwc_otg_hcd_handle_session_req_intr (dwc_otg_hcd_t *dwc_otg_hcd)
    ++
    + int32_t dwc_otg_hcd_handle_wakeup_detected_intr (dwc_otg_hcd_t *dwc_otg_hcd)

    Schedule Queue Functions

    dwc_otg_qh_t * dwc_otg_hcd_qh_create (dwc_otg_hcd_t *hcd, dwc_otg_hcd_urb_t *urb)
    dwc_otg_qh_t * dwc_otg_hcd_qh_create (dwc_otg_hcd_t *hcd, dwc_otg_hcd_urb_t *urb, int atomic_alloc)
     This function allocates and initializes a QH.
    void dwc_otg_hcd_qh_free (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
     This function allocates and initializes a QH.
    void dwc_otg_hcd_qh_free (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
     Free each QTD in the QH's QTD-list then free the QH.
    int dwc_otg_hcd_qh_add (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
     Free each QTD in the QH's QTD-list then free the QH.
    int dwc_otg_hcd_qh_add (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
     This function adds a QH to either the non periodic or periodic schedule if it is not already in the schedule.
    void dwc_otg_hcd_qh_remove (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
     This function adds a QH to either the non periodic or periodic schedule if it is not already in the schedule.
    void dwc_otg_hcd_qh_remove (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
     Removes a QH from either the non-periodic or periodic schedule.
    void dwc_otg_hcd_qh_deactivate (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh, int sched_csplit)
     Removes a QH from either the non-periodic or periodic schedule.
    void dwc_otg_hcd_qh_deactivate (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh, int sched_csplit)
     Deactivates a QH.
    +-static void dwc_otg_hcd_qh_remove_and_free (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
     Deactivates a QH.
    ++void dwc_otg_hcd_qh_remove_and_free (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
     Remove and free a QH.
    static dwc_otg_qh_t * dwc_otg_hcd_qh_alloc (void)
    dwc_otg_qh_t * dwc_otg_hcd_qh_alloc (int atomic_alloc)
     Allocates memory for a QH structure.
    dwc_otg_qtd_t * dwc_otg_hcd_qtd_create (dwc_otg_hcd_urb_t *urb)
     Allocates memory for a QH structure.
    dwc_otg_qtd_t * dwc_otg_hcd_qtd_create (dwc_otg_hcd_urb_t *urb, int atomic_alloc)
     This function allocates and initializes a QTD.
    void dwc_otg_hcd_qtd_init (dwc_otg_qtd_t *qtd, dwc_otg_hcd_urb_t *urb)
     This function allocates and initializes a QTD.
    void dwc_otg_hcd_qtd_init (dwc_otg_qtd_t *qtd, dwc_otg_hcd_urb_t *urb)
     Initializes a QTD structure.
    int dwc_otg_hcd_qtd_add (dwc_otg_qtd_t *qtd, dwc_otg_hcd_t *dwc_otg_hcd, dwc_otg_qh_t **qh)
     Initializes a QTD structure.
    int dwc_otg_hcd_qtd_add (dwc_otg_qtd_t *qtd, dwc_otg_hcd_t *dwc_otg_hcd, dwc_otg_qh_t **qh, int atomic_alloc)
     This function adds a QTD to the QTD-list of a QH.
    static dwc_otg_qtd_t * dwc_otg_hcd_qtd_alloc (void)
     This function adds a QTD to the QTD-list of a QH.
    dwc_otg_qtd_t * dwc_otg_hcd_qtd_alloc (int atomic_alloc)
     Allocates memory for a QTD structure.
    static void dwc_otg_hcd_qtd_free (dwc_otg_qtd_t *qtd)
     Allocates memory for a QTD structure.
    void dwc_otg_hcd_qtd_free (dwc_otg_qtd_t *qtd)
     Frees the memory for a QTD structure.
    static void dwc_otg_hcd_qtd_remove (dwc_otg_hcd_t *hcd, dwc_otg_qtd_t *qtd, dwc_otg_qh_t *qh)
     Frees the memory for a QTD structure.
    void dwc_otg_hcd_qtd_remove (dwc_otg_hcd_t *hcd, dwc_otg_qtd_t *qtd, dwc_otg_qh_t *qh)
     Removes a QTD from list.
    +-static void dwc_otg_hcd_qtd_remove_and_free (dwc_otg_hcd_t *hcd, dwc_otg_qtd_t *qtd, dwc_otg_qh_t *qh)
     Removes a QTD from list.
    ++void dwc_otg_hcd_qtd_remove_and_free (dwc_otg_hcd_t *hcd, dwc_otg_qtd_t *qtd, dwc_otg_qh_t *qh)
     Remove and free a QTD.
     Remove and free a QTD Need to disable IRQ and hold hcd lock while calling this function out of interrupt servicing chain.

    Descriptor DMA Supporting Functions

    void dwc_otg_hcd_start_xfer_ddma (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
    void dwc_otg_hcd_start_xfer_ddma (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
     For Control and Bulk endpoints initializes descriptor list and starts the transfer.
    void dwc_otg_hcd_complete_xfer_ddma (dwc_otg_hcd_t *hcd, dwc_hc_t *hc, dwc_otg_hc_regs_t *hc_regs, dwc_otg_halt_status_e halt_status)
     For Control and Bulk endpoints initializes descriptor list and starts the transfer.
    void dwc_otg_hcd_complete_xfer_ddma (dwc_otg_hcd_t *hcd, dwc_hc_t *hc, dwc_otg_hc_regs_t *hc_regs, dwc_otg_halt_status_e halt_status)
     This function is called from interrupt handlers.
    int dwc_otg_hcd_qh_init_ddma (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
     This function is called from interrupt handlers.
    int dwc_otg_hcd_qh_init_ddma (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
     Initializes a QH structure's Descriptor DMA related members.
    void dwc_otg_hcd_qh_free_ddma (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
     Initializes a QH structure's Descriptor DMA related members.
    void dwc_otg_hcd_qh_free_ddma (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
     Frees descriptor list memory associated with the QH.
     Frees descriptor list memory associated with the QH.

    Internal Functions

    +-dwc_otg_qh_t * dwc_urb_to_qh (dwc_otg_hcd_urb_t *urb)
    ++dwc_otg_qh_t * dwc_urb_to_qh (dwc_otg_hcd_urb_t *urb)

    Defines

    +-#define DWC_OTG_HCD_STATUS_BUF_SIZE   64
    ++#define DWC_OTG_HCD_STATUS_BUF_SIZE   64
    +-#define dwc_list_to_qh(_list_head_ptr_)   container_of(_list_head_ptr_, dwc_otg_qh_t, qh_list_entry)
    ++#define dwc_list_to_qh(_list_head_ptr_)   container_of(_list_head_ptr_, dwc_otg_qh_t, qh_list_entry)
     Gets the QH that contains the list_head.
    +-#define dwc_list_to_qtd(_list_head_ptr_)   container_of(_list_head_ptr_, dwc_otg_qtd_t, qtd_list_entry)
    ++#define dwc_list_to_qtd(_list_head_ptr_)   container_of(_list_head_ptr_, dwc_otg_qtd_t, qtd_list_entry)
     Gets the QTD that contains the list_head.
    #define dwc_qh_is_non_per(_qh_ptr_)
    #define dwc_qh_is_non_per(_qh_ptr_)
     Check if QH is non-periodic.
    +-#define dwc_hb_mult(wMaxPacketSize)   (1 + (((wMaxPacketSize) >> 11) & 0x03))
     Check if QH is non-periodic.
    ++#define dwc_hb_mult(wMaxPacketSize)   (1 + (((wMaxPacketSize) >> 11) & 0x03))
     High bandwidth multiplier as encoded in highspeed endpoint descriptors.
    +-#define dwc_max_packet(wMaxPacketSize)   ((wMaxPacketSize) & 0x07ff)
    ++#define dwc_max_packet(wMaxPacketSize)   ((wMaxPacketSize) & 0x07ff)
     Packet size for any kind of endpoint descriptor.
    +-#define dwc_sample_frrem(_hcd, _qh, _letter)
    ++#define dwc_sample_frrem(_hcd, _qh, _letter)

    Typedefs

    +-typedef enum dwc_otg_control_phase dwc_otg_control_phase_e
    ++typedef enum dwc_otg_control_phase dwc_otg_control_phase_e
     Phases for control transfers.
    +-typedef enum dwc_otg_transaction_type dwc_otg_transaction_type_e
    ++typedef enum dwc_otg_transaction_type dwc_otg_transaction_type_e
     Transaction types.
    typedef dwc_otg_qtd dwc_otg_qtd_t
    typedef dwc_otg_qtd dwc_otg_qtd_t
     A Queue Transfer Descriptor (QTD) holds the state of a bulk, control, interrupt, or isochronous transfer.
    typedef dwc_otg_qh dwc_otg_qh_t
     A Queue Transfer Descriptor (QTD) holds the state of a bulk, control, interrupt, or isochronous transfer.
    typedef dwc_otg_qh dwc_otg_qh_t
     A Queue Head (QH) holds the static characteristics of an endpoint and maintains a list of transfers (QTDs) for that endpoint.
     A Queue Head (QH) holds the static characteristics of an endpoint and maintains a list of transfers (QTDs) for that endpoint.

    Enumerations

    enum  dwc_otg_control_phase { DWC_OTG_CONTROL_SETUP, ++
    enum  dwc_otg_control_phase { DWC_OTG_CONTROL_SETUP, + DWC_OTG_CONTROL_DATA, + DWC_OTG_CONTROL_STATUS + }
     Phases for control transfers.
    enum  dwc_otg_transaction_type { DWC_OTG_TRANSACTION_NONE, ++
    enum  dwc_otg_transaction_type { DWC_OTG_TRANSACTION_NONE, + DWC_OTG_TRANSACTION_PERIODIC, + DWC_OTG_TRANSACTION_NON_PERIODIC, + DWC_OTG_TRANSACTION_ALL +@@ -213,85 +202,93 @@ + +
     Transaction types.

    Functions

    +-static uint8_t dwc_otg_hcd_get_ep_num (struct dwc_otg_hcd_pipe_info *pipe)
    ++uint8_t dwc_otg_hcd_get_ep_num (struct dwc_otg_hcd_pipe_info *pipe)
    +-static uint8_t dwc_otg_hcd_get_pipe_type (struct dwc_otg_hcd_pipe_info *pipe)
    ++uint8_t dwc_otg_hcd_get_pipe_type (struct dwc_otg_hcd_pipe_info *pipe)
    +-static uint16_t dwc_otg_hcd_get_mps (struct dwc_otg_hcd_pipe_info *pipe)
    ++uint16_t dwc_otg_hcd_get_mps (struct dwc_otg_hcd_pipe_info *pipe)
    +-static uint8_t dwc_otg_hcd_get_dev_addr (struct dwc_otg_hcd_pipe_info *pipe)
    ++uint8_t dwc_otg_hcd_get_dev_addr (struct dwc_otg_hcd_pipe_info *pipe)
    +-static uint8_t dwc_otg_hcd_is_pipe_isoc (struct dwc_otg_hcd_pipe_info *pipe)
    ++uint8_t dwc_otg_hcd_is_pipe_isoc (struct dwc_otg_hcd_pipe_info *pipe)
    +-static uint8_t dwc_otg_hcd_is_pipe_int (struct dwc_otg_hcd_pipe_info *pipe)
    ++uint8_t dwc_otg_hcd_is_pipe_int (struct dwc_otg_hcd_pipe_info *pipe)
    +-static uint8_t dwc_otg_hcd_is_pipe_bulk (struct dwc_otg_hcd_pipe_info *pipe)
    ++uint8_t dwc_otg_hcd_is_pipe_bulk (struct dwc_otg_hcd_pipe_info *pipe)
    +-static uint8_t dwc_otg_hcd_is_pipe_control (struct dwc_otg_hcd_pipe_info *pipe)
    ++uint8_t dwc_otg_hcd_is_pipe_control (struct dwc_otg_hcd_pipe_info *pipe)
    +-static uint8_t dwc_otg_hcd_is_pipe_in (struct dwc_otg_hcd_pipe_info *pipe)
    ++uint8_t dwc_otg_hcd_is_pipe_in (struct dwc_otg_hcd_pipe_info *pipe)
    +-static uint8_t dwc_otg_hcd_is_pipe_out (struct dwc_otg_hcd_pipe_info *pipe)
    ++uint8_t dwc_otg_hcd_is_pipe_out (struct dwc_otg_hcd_pipe_info *pipe)
    +-static void dwc_otg_hcd_fill_pipe (struct dwc_otg_hcd_pipe_info *pipe, uint8_t devaddr, uint8_t ep_num, uint8_t pipe_type, uint8_t pipe_dir, uint16_t mps)
    ++void dwc_otg_hcd_fill_pipe (struct dwc_otg_hcd_pipe_info *pipe, uint8_t devaddr, uint8_t ep_num, uint8_t pipe_type, uint8_t pipe_dir, uint16_t mps)
    ++
    +  DWC_CIRCLEQ_HEAD (dwc_otg_qtd_list, dwc_otg_qtd)
    ++
    +  DWC_CIRCLEQ_HEAD (hc_list, dwc_hc)
    static int dwc_frame_num_le (uint16_t frame1, uint16_t frame2)
    int dwc_frame_num_le (uint16_t frame1, uint16_t frame2)
     Returns true if _frame1 is less than or equal to _frame2.
    static int dwc_frame_num_gt (uint16_t frame1, uint16_t frame2)
     Returns true if _frame1 is less than or equal to _frame2.
    int dwc_frame_num_gt (uint16_t frame1, uint16_t frame2)
     Returns true if _frame1 is greater than _frame2.
    static uint16_t dwc_frame_num_inc (uint16_t frame, uint16_t inc)
     Returns true if _frame1 is greater than _frame2.
    uint16_t dwc_frame_num_inc (uint16_t frame, uint16_t inc)
     Increments _frame by the amount specified by _inc.
    +-static uint16_t dwc_full_frame_num (uint16_t frame)
     Increments _frame by the amount specified by _inc.
    ++uint16_t dwc_full_frame_num (uint16_t frame)
    +-static uint16_t dwc_micro_frame_num (uint16_t frame)
    ++uint16_t dwc_micro_frame_num (uint16_t frame)
    +-void dwc_otg_hcd_save_data_toggle (dwc_hc_t *hc, dwc_otg_hc_regs_t *hc_regs, dwc_otg_qtd_t *qtd)
    ++void dwc_otg_hcd_save_data_toggle (dwc_hc_t *hc, dwc_otg_hc_regs_t *hc_regs, dwc_otg_qtd_t *qtd)
    +

    Detailed Description

    + This file contains the structures, constants, and interfaces for the Host Contoller Driver (HCD). +

    +-The Host Controller Driver (HCD) is responsible for translating requests from the USB Driver into the appropriate actions on the DWC_otg controller. It isolates the USBD from the specifics of the controller by providing an API to the USBD. ++The Host Controller Driver (HCD) is responsible for translating requests from the USB Driver into the appropriate actions on the DWC_otg controller. It isolates the USBD from the specifics of the controller by providing an API to the USBD. +

    + Definition in file dwc_otg_hcd.h.

    Define Documentation

    +- +-
    +-
    +- +- +- +- +- +- +- +- ++

    ++

    #define dwc_qh_is_non_per (_qh_ptr_   ) 
    ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ + +
    #define dwc_qh_is_non_per ( _qh_ptr_   ) 
    +- +-
    ++
    ++ ++ ++ ++ ++ ++
    ++   ++ + +

    + Value:

    ((_qh_ptr_->ep_type == UE_BULK) || \
+@@ -300,61 +297,85 @@
+ 
    
+ 
+ 
    
+-Definition at line 694 of file dwc_otg_hcd.h.
+-
    +-

    ++Definition at line 711 of file dwc_otg_hcd.h.

    +

    Typedef Documentation

    +- +-
    +-
    +- ++

    ++

    ++ ++ ++ ++
    ++ + +- ++ + +
    typedef struct dwc_otg_qtd dwc_otg_qtd_t typedef struct dwc_otg_qtd dwc_otg_qtd_t
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + A Queue Transfer Descriptor (QTD) holds the state of a bulk, control, interrupt, or isochronous transfer. +

    + A single QTD is created for each URB (of one of these types) submitted to the HCD. The transfer associated with a QTD may require one or multiple transactions.

    +-A QTD is linked to a Queue Head, which is entered in either the non-periodic or periodic schedule for execution. When a QTD is chosen for execution, some or all of its transactions may be executed. After execution, the state of the QTD is updated. The QTD may be retired if all its transactions are complete or if an error occurred. Otherwise, it remains in the schedule so more transactions can be executed later. +- +-

    +- +-

    +-
    +- ++A QTD is linked to a Queue Head, which is entered in either the non-periodic or periodic schedule for execution. When a QTD is chosen for execution, some or all of its transactions may be executed. After execution, the state of the QTD is updated. The QTD may be retired if all its transactions are complete or if an error occurred. Otherwise, it remains in the schedule so more transactions can be executed later. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- ++ + +
    typedef struct dwc_otg_qh dwc_otg_qh_t typedef struct dwc_otg_qh dwc_otg_qh_t
    +- +-
    ++
    ++ ++ ++ ++ ++ ++
    ++   ++ + +

    + A Queue Head (QH) holds the static characteristics of an endpoint and maintains a list of transfers (QTDs) for that endpoint. +

    +-A QH structure may be entered in either the non-periodic or periodic schedule. +- +-

    ++A QH structure may be entered in either the non-periodic or periodic schedule.

    +

    Function Documentation

    +- +-
    +-
    +- +- +- +- +- +- +- +- ++

    ++

    dwc_otg_transaction_type_e dwc_otg_hcd_select_transactions (dwc_otg_hcd_t *  hcd  ) 
    ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ + +
    dwc_otg_transaction_type_e dwc_otg_hcd_select_transactions ( dwc_otg_hcd_t *  hcd  ) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + This function selects transactions from the HCD transfer schedule and assigns them to available host channels. +@@ -368,33 +389,41 @@ +

    Returns:
    The types of new transactions that were assigned to host channels.
    + +

    +-Definition at line 1055 of file dwc_otg_hcd.c. +- +-

    +- +-

    +-
    +- ++Definition at line 1168 of file dwc_otg_hcd.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    void dwc_otg_hcd_queue_transactions (dwc_otg_hcd_t *  hcd, void dwc_otg_hcd_queue_transactions ( dwc_otg_hcd_t *  hcd,
    dwc_otg_transaction_type_e  tr_type dwc_otg_transaction_type_e  tr_type
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + This function processes the currently active host channels and queues transactions for these channels to the DWC_otg controller. +@@ -408,206 +437,277 @@ + + +

    +-Definition at line 1426 of file dwc_otg_hcd.c. +- +-

    +- +-

    +-
    +- +- +- +- +- +- +- +- ++Definition at line 1540 of file dwc_otg_hcd.c. ++ ++
    int32_t dwc_otg_hcd_handle_intr (dwc_otg_hcd_t *  dwc_otg_hcd  ) 
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ + +
    int32_t dwc_otg_hcd_handle_intr ( dwc_otg_hcd_t *  dwc_otg_hcd  ) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + This function handles interrupts for the HCD. +

    ++

    Todo:
    Implement i2cintr handler.
    + +

    +-

    Todo:
    Implement i2cintr handler.
    +- +-

    +-Definition at line 43 of file dwc_otg_hcd_intr.c. +- +-

    +- +-

    +-
    +- +- +- +- +- +- +- +- ++Definition at line 43 of file dwc_otg_hcd_intr.c. ++ ++
    int32_t dwc_otg_hcd_handle_sof_intr (dwc_otg_hcd_t *  hcd  ) 
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ + +
    int32_t dwc_otg_hcd_handle_sof_intr ( dwc_otg_hcd_t *  hcd  ) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Handles the start-of-frame interrupt in host mode. +

    + Non-periodic transactions may be queued to the DWC_otg controller for the current (micro)frame. Periodic transactions may be queued to the controller for the next (micro)frame. +

    +-Definition at line 169 of file dwc_otg_hcd_intr.c. +- +-

    +- +-

    +-
    +- +- +- +- +- +- +- +- ++Definition at line 175 of file dwc_otg_hcd_intr.c. ++ ++
    int32_t dwc_otg_hcd_handle_rx_status_q_level_intr (dwc_otg_hcd_t *  dwc_otg_hcd  ) 
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ + +
    int32_t dwc_otg_hcd_handle_rx_status_q_level_intr ( dwc_otg_hcd_t *  dwc_otg_hcd  ) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Handles the Rx Status Queue Level Interrupt, which indicates that there is at least one packet in the Rx FIFO. +

    + The packets are moved from the FIFO to memory if the DWC_otg controller is operating in Slave mode. +

    +-Definition at line 222 of file dwc_otg_hcd_intr.c. +- +-

    +- +-

    +-
    +- +- +- +- +- +- +- +- ++Definition at line 228 of file dwc_otg_hcd_intr.c. ++ ++
    int32_t dwc_otg_hcd_handle_np_tx_fifo_empty_intr (dwc_otg_hcd_t *  dwc_otg_hcd  ) 
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ + +
    int32_t dwc_otg_hcd_handle_np_tx_fifo_empty_intr ( dwc_otg_hcd_t *  dwc_otg_hcd  ) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + This interrupt occurs when the non-periodic Tx FIFO is half-empty. +

    + More data packets may be written to the FIFO for OUT transfers. More requests may be written to the non-periodic request queue for IN transfers. This interrupt is enabled only in Slave mode. +

    +-Definition at line 271 of file dwc_otg_hcd_intr.c. +- +-

    +- +-

    +-
    +- +- +- +- +- +- +- +- ++Definition at line 281 of file dwc_otg_hcd_intr.c. ++ ++
    int32_t dwc_otg_hcd_handle_perio_tx_fifo_empty_intr (dwc_otg_hcd_t *  dwc_otg_hcd  ) 
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ + +
    int32_t dwc_otg_hcd_handle_perio_tx_fifo_empty_intr ( dwc_otg_hcd_t *  dwc_otg_hcd  ) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + This interrupt occurs when the periodic Tx FIFO is half-empty. +

    + More data packets may be written to the FIFO for OUT transfers. More requests may be written to the periodic request queue for IN transfers. This interrupt is enabled only in Slave mode. +

    +-Definition at line 283 of file dwc_otg_hcd_intr.c. +- +-

    +- +-

    +-
    +- +- +- +- +- +- +- +- ++Definition at line 293 of file dwc_otg_hcd_intr.c. ++ ++
    int32_t dwc_otg_hcd_handle_port_intr (dwc_otg_hcd_t *  dwc_otg_hcd  ) 
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ + +
    int32_t dwc_otg_hcd_handle_port_intr ( dwc_otg_hcd_t *  dwc_otg_hcd  ) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + There are multiple conditions that can cause a port interrupt. +

    +-This function determines which interrupt conditions have occurred and handles them appropriately. ++This function determines which interrupt conditions have occurred and handles them appropriately.

    ++

    Todo:
      ++
    • check if steps performed in 'else' block should be perfromed regardles adp
    ++
    +

    + Overcurrent Change Interrupt +

    +-Definition at line 294 of file dwc_otg_hcd_intr.c. +- +-

    +- +-

    +-
    +- +- +- +- +- +- +- +- ++Definition at line 304 of file dwc_otg_hcd_intr.c. ++ ++
    int32_t dwc_otg_hcd_handle_hc_intr (dwc_otg_hcd_t *  dwc_otg_hcd  ) 
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ + +
    int32_t dwc_otg_hcd_handle_hc_intr ( dwc_otg_hcd_t *  dwc_otg_hcd  ) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + This interrupt indicates that one or more host channels has a pending interrupt. +

    + There are multiple conditions that can cause each host channel interrupt. This function determines which conditions have occurred for each host channel interrupt and handles them appropriately. +

    +-Definition at line 453 of file dwc_otg_hcd_intr.c. +- +-

    +- +-

    +-
    +- ++Definition at line 493 of file dwc_otg_hcd_intr.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ ++ ++ ++ ++ ++ ++ + +
    dwc_otg_qh_t* dwc_otg_hcd_qh_create (dwc_otg_hcd_t *  hcd, dwc_otg_qh_t* dwc_otg_hcd_qh_create ( dwc_otg_hcd_t *  hcd,
    dwc_otg_hcd_urb_t *  urb dwc_otg_hcd_urb_t *  urb,
    )int  atomic_alloc
    ) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + This function allocates and initializes a QH. +@@ -615,42 +715,50 @@ +

    Parameters:
    + + +- ++ ++ +
    hcd The HCD state structure for the DWC OTG controller.
    urb Holds the information about the device/endpoint that we need to initialize the QH.
    urb Holds the information about the device/endpoint that we need to initialize the QH.
    atomic_alloc Flag to do atomic allocation if needed
    +
    +-
    Returns:
    Returns pointer to the newly allocated QH, or NULL on error.
    +- ++
    Returns:
    Returns pointer to the newly allocated QH, or NULL on error.
    +

    +-

    Todo:
    add memflags argument
    ++
    Todo:
    add memflags argument
    + +

    +-Definition at line 296 of file dwc_otg_hcd_queue.c. +- +-

    +- +-

    +-
    +- ++Definition at line 290 of file dwc_otg_hcd_queue.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    void dwc_otg_hcd_qh_free (dwc_otg_hcd_t *  hcd, void dwc_otg_hcd_qh_free ( dwc_otg_hcd_t *  hcd,
    dwc_otg_qh_t *  qh dwc_otg_qh_t *  qh
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Free each QTD in the QH's QTD-list then free the QH. +@@ -664,33 +772,41 @@ + + +

    +-Definition at line 53 of file dwc_otg_hcd_queue.c. +- +-

    +- +-

    +-
    +- ++Definition at line 53 of file dwc_otg_hcd_queue.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    int dwc_otg_hcd_qh_add (dwc_otg_hcd_t *  hcd, int dwc_otg_hcd_qh_add ( dwc_otg_hcd_t *  hcd,
    dwc_otg_qh_t *  qh dwc_otg_qh_t *  qh
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + This function adds a QH to either the non periodic or periodic schedule if it is not already in the schedule. +@@ -699,33 +815,41 @@ +

    Returns:
    0 if successful, negative error code otherwise.
    + +

    +-Definition at line 472 of file dwc_otg_hcd_queue.c. +- +-

    +- +-

    +-
    +- ++Definition at line 468 of file dwc_otg_hcd_queue.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    void dwc_otg_hcd_qh_remove (dwc_otg_hcd_t *  hcd, void dwc_otg_hcd_qh_remove ( dwc_otg_hcd_t *  hcd,
    dwc_otg_qh_t *  qh dwc_otg_qh_t *  qh
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Removes a QH from either the non-periodic or periodic schedule. +@@ -739,39 +863,47 @@ + + +

    +-Definition at line 522 of file dwc_otg_hcd_queue.c. +- +-

    +- +-

    +-
    +- ++Definition at line 519 of file dwc_otg_hcd_queue.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    void dwc_otg_hcd_qh_deactivate (dwc_otg_hcd_t *  hcd, void dwc_otg_hcd_qh_deactivate ( dwc_otg_hcd_t *  hcd,
    dwc_otg_qh_t *  qh, dwc_otg_qh_t *  qh,
    int  sched_next_periodic_split int  sched_next_periodic_split
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Deactivates a QH. +@@ -779,24 +911,32 @@ + For non-periodic QHs, removes the QH from the active non-periodic schedule. The QH is added to the inactive non-periodic schedule if any QTDs are still attached to the QH.

    + For periodic QHs, the QH is removed from the periodic queued schedule. If there are any QTDs still attached to the QH, the QH is added to either the periodic inactive schedule or the periodic ready schedule and its next scheduled frame is calculated. The QH is placed in the ready schedule if the scheduled frame has been reached already. Otherwise it's placed in the inactive schedule. If there are no QTDs attached to the QH, the QH is completely removed from the periodic schedule. +

    +-Definition at line 559 of file dwc_otg_hcd_queue.c. +- +-

    +- +-

    +-
    +- +- +- +- +- +- +- +- ++Definition at line 558 of file dwc_otg_hcd_queue.c. ++ ++
    static dwc_otg_qh_t* dwc_otg_hcd_qh_alloc (void   )  [inline, static]
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ + +
    dwc_otg_qh_t* dwc_otg_hcd_qh_alloc ( int  atomic_alloc  )  [inline, static]
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Allocates memory for a QH structure. +@@ -804,63 +944,89 @@ +

    Returns:
    Returns the memory allocate or NULL on error.
    + +

    +-Definition at line 611 of file dwc_otg_hcd.h. +- +-

    +- +-

    +-
    +- +- +- +- +- +- +- +- ++Definition at line 622 of file dwc_otg_hcd.h. ++ ++
    dwc_otg_qtd_t* dwc_otg_hcd_qtd_create (dwc_otg_hcd_urb_t *  urb  ) 
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ + +
    dwc_otg_qtd_t* dwc_otg_hcd_qtd_create ( dwc_otg_hcd_urb_t *  urb,
    int  atomic_alloc
    ) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + This function allocates and initializes a QTD. +

    +

    Parameters:
    + +- ++ ++ +
    urb The URB to create a QTD from. Each URB-QTD pair will end up pointing to each other so each pair should have a unique correlation.
    urb The URB to create a QTD from. Each URB-QTD pair will end up pointing to each other so each pair should have a unique correlation.
    atomic_alloc Flag to do atomic alloc if needed
    +
    +
    Returns:
    Returns pointer to the newly allocated QTD, or NULL on error.
    + +

    +-Definition at line 643 of file dwc_otg_hcd_queue.c. +- +-

    +- +-

    +-
    +- ++Definition at line 638 of file dwc_otg_hcd_queue.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    void dwc_otg_hcd_qtd_init (dwc_otg_qtd_t *  qtd, void dwc_otg_hcd_qtd_init ( dwc_otg_qtd_t *  qtd,
    dwc_otg_hcd_urb_t *  urb dwc_otg_hcd_urb_t *  urb
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Initializes a QTD structure. +@@ -873,39 +1039,53 @@ + + +

    +-Definition at line 661 of file dwc_otg_hcd_queue.c. +- +-

    +- +-

    +-
    +- ++Definition at line 656 of file dwc_otg_hcd_queue.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ ++ ++ ++ ++ ++ ++ + +
    int dwc_otg_hcd_qtd_add (dwc_otg_qtd_t *  qtd, int dwc_otg_hcd_qtd_add ( dwc_otg_qtd_t *  qtd,
    dwc_otg_hcd_t *  hcd, dwc_otg_hcd_t *  hcd,
    dwc_otg_qh_t **  qh dwc_otg_qh_t **  qh,
    )int  atomic_alloc
    ) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + This function adds a QTD to the QTD-list of a QH. +@@ -915,30 +1095,39 @@ + + + +- ++ ++ +
    [in] qtd The QTD to add
    [in] hcd The DWC HCD structure
    [out] qh out parameter to return queue head
    [out] qh out parameter to return queue head
    atomic_alloc Flag to do atomic alloc if needed
    + +

    Returns:
    0 if successful, negative error code otherwise.
    + +

    +-Definition at line 698 of file dwc_otg_hcd_queue.c. +- +-

    +- +-

    +-
    +- +- +- +- +- +- +- +- ++Definition at line 694 of file dwc_otg_hcd_queue.c. ++ ++
    static dwc_otg_qtd_t* dwc_otg_hcd_qtd_alloc (void   )  [inline, static]
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ + +
    dwc_otg_qtd_t* dwc_otg_hcd_qtd_alloc ( int  atomic_alloc  )  [inline, static]
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Allocates memory for a QTD structure. +@@ -946,24 +1135,32 @@ +

    Returns:
    Returns the memory allocate or NULL on error.
    + +

    +-Definition at line 623 of file dwc_otg_hcd.h. +- +-

    +- +-

    +-
    +- +- +- +- +- +- +- +- ++Definition at line 638 of file dwc_otg_hcd.h. ++ ++
    static void dwc_otg_hcd_qtd_free (dwc_otg_qtd_t *  qtd  )  [inline, static]
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ + +
    void dwc_otg_hcd_qtd_free ( dwc_otg_qtd_t *  qtd  )  [inline, static]
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Frees the memory for a QTD structure. +@@ -975,39 +1172,47 @@ + + +

    +-Definition at line 631 of file dwc_otg_hcd.h. +- +-

    +- +-

    +-
    +- ++Definition at line 649 of file dwc_otg_hcd.h. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    static void dwc_otg_hcd_qtd_remove (dwc_otg_hcd_t *  hcd, void dwc_otg_hcd_qtd_remove ( dwc_otg_hcd_t *  hcd,
    dwc_otg_qtd_t *  qtd, dwc_otg_qtd_t *  qtd,
    dwc_otg_qh_t *  qh dwc_otg_qh_t *  qh
    ) [inline, static])  [inline, static]
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Removes a QTD from list. +@@ -1021,33 +1226,41 @@ + + +

    +-Definition at line 641 of file dwc_otg_hcd.h. +- +-

    +- +-

    +-
    +- ++Definition at line 659 of file dwc_otg_hcd.h. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    void dwc_otg_hcd_start_xfer_ddma (dwc_otg_hcd_t *  hcd, void dwc_otg_hcd_start_xfer_ddma ( dwc_otg_hcd_t *  hcd,
    dwc_otg_qh_t *  qh dwc_otg_qh_t *  qh
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + For Control and Bulk endpoints initializes descriptor list and starts the transfer. +@@ -1062,45 +1275,53 @@ +

    Returns:
    0 if successful, negative error code otherwise.
    + +

    +-Definition at line 675 of file dwc_otg_hcd_ddma.c. +- +-

    +- +-

    +-
    +- ++Definition at line 702 of file dwc_otg_hcd_ddma.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    void dwc_otg_hcd_complete_xfer_ddma (dwc_otg_hcd_t *  hcd, void dwc_otg_hcd_complete_xfer_ddma ( dwc_otg_hcd_t *  hcd,
    dwc_hc_t *  hc, dwc_hc_t *  hc,
    dwc_otg_hc_regs_t *  hc_regs, dwc_otg_hc_regs_t *  hc_regs,
    dwc_otg_halt_status_e  halt_status dwc_otg_halt_status_e  halt_status
    )) 
    +- +-
    ++
    ++ ++ ++ ++ + + +- ++ +
    ++   ++ + +

    + This function is called from interrupt handlers. +@@ -1112,41 +1333,48 @@ +

    hcd The HCD state structure for the DWC OTG controller.
    hc Host channel, the transfer is completed on.
    hc_regs Host channel registers.
    halt_status Reason the channel is being halted, or just XferComplete for isochronous transfer
    halt_status Reason the channel is being halted, or just XferComplete for isochronous transfer
    + +- +

    +-

    Todo:
    Consider the case when period exceeds FrameList size. Frame Rollover interrupt should be used.
    ++
    Todo:
    Consider the case when period exceeds FrameList size. Frame Rollover interrupt should be used.
    + +

    +-Definition at line 1042 of file dwc_otg_hcd_ddma.c. +-

    +-

    +- +-

    +-
    +- ++Definition at line 1062 of file dwc_otg_hcd_ddma.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    int dwc_otg_hcd_qh_init_ddma (dwc_otg_hcd_t *  hcd, int dwc_otg_hcd_qh_init_ddma ( dwc_otg_hcd_t *  hcd,
    dwc_otg_qh_t *  qh dwc_otg_qh_t *  qh
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Initializes a QH structure's Descriptor DMA related members. +@@ -1161,33 +1389,41 @@ +

    Returns:
    0 if successful, negative error code otherwise.
    + +

    +-Definition at line 294 of file dwc_otg_hcd_ddma.c. +- +-

    +- +-

    +-
    +- ++Definition at line 312 of file dwc_otg_hcd_ddma.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    void dwc_otg_hcd_qh_free_ddma (dwc_otg_hcd_t *  hcd, void dwc_otg_hcd_qh_free_ddma ( dwc_otg_hcd_t *  hcd,
    dwc_otg_qh_t *  qh dwc_otg_qh_t *  qh
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Frees descriptor list memory associated with the QH. +@@ -1201,110 +1437,134 @@ + + +

    +-Definition at line 327 of file dwc_otg_hcd_ddma.c. +- +-

    +- +-

    +-
    +- ++Definition at line 346 of file dwc_otg_hcd_ddma.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    static int dwc_frame_num_le (uint16_t  frame1, int dwc_frame_num_le ( uint16_t  frame1,
    uint16_t  frame2 uint16_t  frame2
    ) [inline, static])  [inline, static]
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Returns true if _frame1 is less than or equal to _frame2. +

    + The comparison is done modulo DWC_HFNUM_MAX_FRNUM. This accounts for the rollover of the frame number when the max frame number is reached. +

    +-Definition at line 708 of file dwc_otg_hcd.h. +- +-

    +- +-

    +-
    +- ++Definition at line 725 of file dwc_otg_hcd.h. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    static int dwc_frame_num_gt (uint16_t  frame1, int dwc_frame_num_gt ( uint16_t  frame1,
    uint16_t  frame2 uint16_t  frame2
    ) [inline, static])  [inline, static]
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Returns true if _frame1 is greater than _frame2. +

    + The comparison is done modulo DWC_HFNUM_MAX_FRNUM. This accounts for the rollover of the frame number when the max frame number is reached. +

    +-Definition at line 719 of file dwc_otg_hcd.h. +- +-

    +- +-

    +-
    +- ++Definition at line 736 of file dwc_otg_hcd.h. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    static uint16_t dwc_frame_num_inc (uint16_t  frame, uint16_t dwc_frame_num_inc ( uint16_t  frame,
    uint16_t  inc uint16_t  inc
    ) [inline, static])  [inline, static]
    +- +-
    ++
    ++ ++ ++ ++ ++ ++
    ++   ++ + +

    + Increments _frame by the amount specified by _inc. +

    + The addition is done modulo DWC_HFNUM_MAX_FRNUM. Returns the incremented value. +

    +-Definition at line 730 of file dwc_otg_hcd.h. +- +-

    +-

    Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++Definition at line 747 of file dwc_otg_hcd.h.
    ++

    Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
    ++doxygen 1.3.9.1 + + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__hcd__ddma_8c-source.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/dwc__otg__hcd__ddma_8c-source.html 2013-07-26 19:31:21.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__hcd__ddma_8c-source.html 2013-07-26 19:34:41.000000000 +0000 +@@ -2,1069 +2,1073 @@ + + DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_hcd_ddma.c Source File + +- + +- +-
    +-
    +-
    +-
    +-

    dwc_otg_hcd_ddma.c

    Go to the documentation of this file.
    00001 /*==========================================================================
+-00002  * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd_ddma.c $
+-00003  * $Revision: #2 $
+-00004  * $Date: 2009/04/21 $
+-00005  * $Change: 1237473 $
+-00006  *
+-00007  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
+-00008  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
+-00009  * otherwise expressly agreed to in writing between Synopsys and you.
+-00010  *
+-00011  * The Software IS NOT an item of Licensed Software or Licensed Product under
+-00012  * any End User Software License Agreement or Agreement for Licensed Product
+-00013  * with Synopsys or any supplement thereto. You are permitted to use and
+-00014  * redistribute this Software in source and binary forms, with or without
+-00015  * modification, provided that redistributions of source code must retain this
+-00016  * notice. You may not view, use, disclose, copy or distribute this file or
+-00017  * any information contained herein except pursuant to this license grant from
+-00018  * Synopsys. If you do not agree with this notice, including the disclaimer
+-00019  * below, then you are not authorized to use the Software.
+-00020  *
+-00021  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
+-00022  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+-00023  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+-00024  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
+-00025  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+-00026  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+-00027  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+-00028  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+-00029  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+-00030  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+-00031  * DAMAGE.
+-00032  * ========================================================================== */
+-00033 #ifndef DWC_DEVICE_ONLY
+-00034 
+-00039 #include "dwc_otg_hcd.h"
+-00040 #include "dwc_otg_regs.h"
+-00041                 
+-00042                 
+-00043 static inline uint8_t frame_list_idx(uint16_t frame)
+-00044 {
+-00045         return (frame & (MAX_FRLIST_EN_NUM - 1));
+-00046 }
+-00047 
+-00048 static inline uint16_t desclist_idx_inc(uint16_t idx, uint16_t inc, uint8_t speed)
+-00049 {
+-00050         return (idx + inc) & 
+-00051                 (((speed == DWC_OTG_EP_SPEED_HIGH) ? MAX_DMA_DESC_NUM_HS_ISOC : MAX_DMA_DESC_NUM_GENERIC) - 1);
+-00052 }
+-00053 
+-00054 static inline uint16_t desclist_idx_dec(uint16_t idx, uint16_t inc, uint8_t speed)
+-00055 {
+-00056         return (idx - inc) & 
+-00057                 (((speed == DWC_OTG_EP_SPEED_HIGH) ? MAX_DMA_DESC_NUM_HS_ISOC : MAX_DMA_DESC_NUM_GENERIC) - 1);
+-00058 }
+-00059 
+-00060 static inline uint16_t max_desc_num(dwc_otg_qh_t * qh)
+-00061 {
+-00062         return (((qh->ep_type == UE_ISOCHRONOUS) && (qh->dev_speed == DWC_OTG_EP_SPEED_HIGH)) 
+-00063                                                         ?
+-00064                                                         MAX_DMA_DESC_NUM_HS_ISOC
+-00065                                                         :
+-00066                                                         MAX_DMA_DESC_NUM_GENERIC);
+-00067 }
+-00068 static inline uint16_t frame_incr_val(dwc_otg_qh_t * qh)
+-00069 {
+-00070         return ((qh->dev_speed == DWC_OTG_EP_SPEED_HIGH) 
+-00071                                                 ? ((qh->interval + 8 - 1) / 8)
+-00072                                                 :
+-00073                                                 qh->interval);
+-00074 }
+-00075 
+-00076 static int desc_list_alloc(dwc_otg_qh_t * qh)
+-00077 {
+-00078         int retval = 0;
+-00079         
+-00080         qh->desc_list = (dwc_otg_host_dma_desc_t *) 
+-00081                                 dwc_dma_alloc(sizeof(dwc_otg_host_dma_desc_t) * max_desc_num(qh),
+-00082                                               &qh->desc_list_dma
+-00083                                               );
+-00084         
+-00085         if (!qh->desc_list) {
+-00086                 retval = -DWC_E_NO_MEMORY;
+-00087                 DWC_ERROR("%s: DMA descriptor list allocation failed\n", __func__);
+-00088                 
+-00089         }
+-00090         
+-00091         dwc_memset(qh->desc_list, 0x00, sizeof(dwc_otg_host_dma_desc_t) * max_desc_num(qh));
+-00092          
+-00093 
+-00094         qh->n_bytes = (uint32_t *) dwc_alloc(sizeof(uint32_t) * max_desc_num(qh));
+-00095         
+-00096         if (!qh->n_bytes) {
+-00097                 retval = -DWC_E_NO_MEMORY;
+-00098                 DWC_ERROR("%s: Failed to allocate array for descriptors' size actual values\n",
+-00099                           __func__);
+-00100                 
+-00101         }       
+-00102         return retval;
+-00103 
+-00104 }
+-00105 
+-00106 static void desc_list_free(dwc_otg_qh_t * qh)
+-00107 {
+-00108         if(qh->desc_list) {
+-00109                 dwc_dma_free(max_desc_num(qh), qh->desc_list, qh->desc_list_dma);
+-00110                 qh->desc_list = NULL;
+-00111         }
+-00112         
+-00113         if (qh->n_bytes) {
+-00114                 dwc_free(qh->n_bytes);
+-00115                 qh->n_bytes = NULL;
+-00116         }
+-00117 }
+-00118 
+-00119 static int frame_list_alloc(dwc_otg_hcd_t * hcd)
+-00120 {
+-00121         int retval = 0; 
+-00122         if (hcd->frame_list)
+-00123                 return 0;
+-00124         
+-00125         hcd->frame_list = dwc_dma_alloc(4 * MAX_FRLIST_EN_NUM,
+-00126                                         &hcd->frame_list_dma
+-00127                                         );
+-00128         if (!hcd->frame_list) {
+-00129                 retval = -DWC_E_NO_MEMORY;
+-00130                 DWC_ERROR("%s: Frame List allocation failed\n", __func__);
+-00131         }
+-00132         
+-00133         dwc_memset(hcd->frame_list, 0x00, 4 * MAX_FRLIST_EN_NUM);
+-00134         
+-00135         return retval;
+-00136 }
+-00137 
+-00138 static void frame_list_free(dwc_otg_hcd_t * hcd)
+-00139 {
+-00140         if (!hcd->frame_list)
+-00141                 return;
+-00142         
+-00143         dwc_dma_free(4 * MAX_FRLIST_EN_NUM, hcd->frame_list, hcd->frame_list_dma);
+-00144         hcd->frame_list = NULL;
+-00145 }
+-00146 
+-00147 static void per_sched_enable(dwc_otg_hcd_t * hcd, uint16_t fr_list_en)
+-00148 {
+-00149                 
+-00150         hcfg_data_t hcfg;
+-00151 
+-00152         hcfg.d32 = dwc_read_reg32(&hcd->core_if->host_if->host_global_regs->hcfg);
+-00153 
+-00154         if (hcfg.b.perschedstat) {
+-00155                 /* already enabled*/    
+-00156                 return;
+-00157         }
+-00158         
+-00159         dwc_write_reg32(&hcd->core_if->host_if->host_global_regs->hflbaddr, hcd->frame_list_dma);
+-00160         
+-00161         switch(fr_list_en) {
+-00162         case 64:
+-00163             hcfg.b.frlisten = 3;
+-00164             break;
+-00165         case 32:
+-00166             hcfg.b.frlisten = 2;
+-00167             break;
+-00168         case 16:
+-00169             hcfg.b.frlisten = 1;    
+-00170         case 8:
+-00171             hcfg.b.frlisten = 0;
+-00172         default:
+-00173             break;        
+-00174         }
+-00175         
+-00176         hcfg.b.perschedena = 1;
+-00177 
+-00178         DWC_DEBUGPL(DBG_HCD, "Enabling Periodic schedule\n");
+-00179         dwc_write_reg32(&hcd->core_if->host_if->host_global_regs->hcfg, hcfg.d32);
+-00180 
+-00181 }
+-00182  
+-00183 static void per_sched_disable(dwc_otg_hcd_t * hcd)
+-00184 {
+-00185         hcfg_data_t hcfg;
+-00186 
+-00187         hcfg.d32 = dwc_read_reg32(&hcd->core_if->host_if->host_global_regs->hcfg);
+-00188         
+-00189         if (!hcfg.b.perschedstat) {
+-00190                 /* already disabled */  
+-00191                 return;
+-00192         }
+-00193         hcfg.b.perschedena = 0;
+-00194         
+-00195         DWC_DEBUGPL(DBG_HCD, "Disabling Periodic schedule\n");
+-00196         dwc_write_reg32(&hcd->core_if->host_if->host_global_regs->hcfg, hcfg.d32);
+-00197 }
+-00198 
+-00199 /* 
+-00200  * Activates/Deactivates FrameList entries for the channel 
+-00201  * based on endpoint servicing period.
+-00202  */
+-00203 void update_frame_list(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh, uint8_t enable)
+-00204 {
+-00205         uint16_t i, j, inc;
+-00206         dwc_hc_t *hc = qh->channel;
+-00207         
+-00208         inc = frame_incr_val(qh);
+-00209         
+-00210         if (qh->ep_type == UE_ISOCHRONOUS)
+-00211                 i = frame_list_idx(qh->sched_frame);
+-00212         else
+-00213                 i = 0;
+-00214 
+-00215         j = i;
+-00216         do {
+-00217                 if (enable)
+-00218                         hcd->frame_list[j] |= (1 << hc->hc_num);
+-00219                 else
+-00220                         hcd->frame_list[j] &= ~(1 << hc->hc_num);
+-00221                 j = (j + inc) & (MAX_FRLIST_EN_NUM - 1);
+-00222         }
+-00223         while (j != i);
+-00224         
+-00225         if (!enable)
+-00226                 return;
+-00227         
+-00228         hc->schinfo = 0;
+-00229         if (qh->channel->speed == DWC_OTG_EP_SPEED_HIGH) {
+-00230                 j = 1;
+-00231                 for (i = 0 ; i < 8 / qh->interval; i++) {
+-00232                         hc->schinfo |= j;
+-00233                         j = j << qh->interval;
+-00234                 }
+-00235         }
+-00236         else {
+-00237                 hc->schinfo = 0xff;
+-00238         }       
+-00239 }               
+-00240 #if 1
+-00241 void dump_frame_list(dwc_otg_hcd_t * hcd)
+-00242 {
+-00243         int i = 0;
+-00244         DWC_PRINTF("--FRAME LIST (hex) --\n");          
+-00245         for (i = 0; i < MAX_FRLIST_EN_NUM; i++) {
+-00246                 DWC_PRINTF("%x\t",hcd->frame_list[i]);
+-00247                 if (!(i % 8) && i)    
+-00248                         DWC_PRINTF("\n");
+-00249         }
+-00250         DWC_PRINTF("\n----\n");
+-00251 
+-00252 }
+-00253 #endif
+-00254 
+-00255 static void release_channel_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
+-00256 {
+-00257         dwc_hc_t *hc = qh->channel;
+-00258         if (dwc_qh_is_non_per(qh)) {
+-00259                 hcd->non_periodic_channels--;                   
+-00260         }
+-00261         else {
+-00262                 update_frame_list(hcd, qh, 0);
+-00263         }
+-00264         /* 
+-00265          * The condition is added to prevent double cleanup try in case of device
+-00266          * disconnect. See channel cleanup in dwc_otg_hcd_disconnect_cb().
+-00267          */
+-00268         if (hc->qh) {   
+-00269                 dwc_otg_hc_cleanup(hcd->core_if, hc);
+-00270                 DWC_CIRCLEQ_INSERT_TAIL(&hcd->free_hc_list, hc, hc_list_entry);
+-00271                 hc->qh = NULL;
+-00272         }
+-00273         
+-00274         qh->channel = NULL;
+-00275         qh->ntd = 0;
+-00276         
+-00277         if (qh->desc_list) {
+-00278                 dwc_memset(qh->desc_list, 0x00, 
+-00279                             sizeof(dwc_otg_host_dma_desc_t) * max_desc_num(qh));
+-00280         }
+-00281 }
+-00282 
+-00294 int dwc_otg_hcd_qh_init_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
+-00295 {
+-00296         int retval = 0;
+-00297         
+-00298         if (qh->do_split) {
+-00299                 DWC_ERROR("SPLIT Transfers are not supported in Descriptor DMA.\n");
+-00300                 return -1;
+-00301         }
+-00302 
+-00303         retval = desc_list_alloc(qh);
+-00304         
+-00305         if ((retval == 0) && (qh->ep_type == UE_ISOCHRONOUS || qh->ep_type == UE_INTERRUPT)) {
+-00306                 if(!hcd->frame_list) {
+-00307                         retval = frame_list_alloc(hcd); 
+-00308                         /* Enable periodic schedule on first periodic QH */
+-00309                         if (retval == 0)                
+-00310                                 per_sched_enable(hcd, MAX_FRLIST_EN_NUM);
+-00311                 }
+-00312         }
+-00313         
+-00314         qh->ntd = 0;
+-00315         
+-00316         return retval;
+-00317 }
+-00318 
+-00327 void dwc_otg_hcd_qh_free_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
+-00328 {
+-00329         desc_list_free(qh);
+-00330 
+-00331         /* 
+-00332          * Channel still assigned due to some reasons. 
+-00333          * Seen on Isoc URB dequeue. Channel halted but no subsequent
+-00334          * ChHalted interrupt to release the channel. Afterwards
+-00335          * when it comes here from endpoint disable routine
+-00336          * channel remains assigned.
+-00337          */
+-00338         if (qh->channel)
+-00339                 release_channel_ddma(hcd, qh);
+-00340 
+-00341         if ((qh->ep_type == UE_ISOCHRONOUS || qh->ep_type == UE_INTERRUPT) 
+-00342                         && !hcd->periodic_channels && hcd->frame_list) {
+-00343                 
+-00344                 per_sched_disable(hcd); 
+-00345                 frame_list_free(hcd);   
+-00346         }
+-00347 }       
+-00348 
+-00349 static uint8_t frame_to_desc_idx(dwc_otg_qh_t * qh, uint16_t frame_idx)
+-00350 {
+-00351         if (qh->dev_speed == DWC_OTG_EP_SPEED_HIGH) {
+-00352                 /* 
+-00353                  * Descriptor set(8 descriptors) index
+-00354                  * which is 8-aligned.
+-00355                  */     
+-00356                 return (frame_idx & ((MAX_DMA_DESC_NUM_HS_ISOC / 8) - 1)) * 8;
+-00357         }
+-00358         else {
+-00359                 return (frame_idx & (MAX_DMA_DESC_NUM_GENERIC - 1));
+-00360         }       
+-00361 }
+-00362 
+-00363 /* 
+-00364  * Determine starting frame for Isochronous transfer. 
+-00365  * Few frames skipped to prevent race condition with HC. 
+-00366  */
+-00367 static uint8_t calc_starting_frame(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh, uint8_t* skip_frames)
+-00368 {
+-00369         uint16_t frame = 0;
+-00370         hcd->frame_number = dwc_otg_hcd_get_frame_number(hcd);
+-00371         
+-00372         /* sched_frame is always frame number(not uFrame) both in FS and HS !! */
+-00373         
+-00374         /* 
+-00375          * skip_frames is used to limit activated descriptors number
+-00376          * to avoid the situation when HC services the last activated
+-00377          * descriptor firstly.
+-00378          * Example for FS:
+-00379          * Current frame is 1, scheduled frame is 3. Since HC always fetches the descriptor
+-00380          * corresponding to curr_frame+1, the descriptor corresponding to frame 2
+-00381          * will be fetched. If the number of descriptors is max=64 (or greather) the list will
+-00382          * be fully programmed with Active descriptors and it is possible case(rare) that the latest 
+-00383          * descriptor(considering rollback) corresponding to frame 2 will be serviced first.
+-00384          * HS case is more probable because, in fact, up to 11 uframes(16 in the code)
+-00385          * may be skipped.
+-00386          */
+-00387         if (qh->dev_speed == DWC_OTG_EP_SPEED_HIGH) {
+-00388                 /* 
+-00389                  * Consider uframe counter also, to start xfer asap.
+-00390                  * If half of the frame elapsed skip 2 frames otherwise
+-00391                  * just 1 frame. 
+-00392                  * Starting descriptor index must be 8-aligned, so
+-00393                  * if the current frame is near to complete the next one
+-00394                  * is skipped as well.
+-00395                  */
+-00396                         
+-00397                 if (dwc_micro_frame_num(hcd->frame_number)  >= 5) {
+-00398                         *skip_frames = 2 * 8;
+-00399                         frame = dwc_frame_num_inc(hcd->frame_number, *skip_frames);
+-00400                 }       
+-00401                 else {
+-00402                         *skip_frames = 1 * 8;
+-00403                         frame = dwc_frame_num_inc(hcd->frame_number, *skip_frames);
+-00404                 }       
+-00405                                  
+-00406                 frame = dwc_full_frame_num(frame); 
+-00407         } else {
+-00408                 /* 
+-00409                  * Two frames are skipped for FS - the current and the next.
+-00410                  * But for descriptor programming, 1 frame(descriptor) is enough,
+-00411                  * see example above.
+-00412                  */
+-00413                 *skip_frames = 1;        
+-00414                 frame = dwc_frame_num_inc(hcd->frame_number, 2);
+-00415         }
+-00416         
+-00417         return frame;
+-00418 }
+-00419 /* 
+-00420  * Calculate initial descriptor index for isochronous transfer
+-00421  * based on scheduled frame. 
+-00422  */
+-00423 static uint8_t recalc_initial_desc_idx(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
+-00424 {
+-00425         uint16_t frame = 0, fr_idx, fr_idx_tmp; 
+-00426         uint8_t skip_frames = 0 ;
+-00427         /* 
+-00428          * With current ISOC processing algorithm the channel is being
+-00429          * released when no more QTDs in the list(qh->ntd == 0).
+-00430          * Thus this function is called only when qh->ntd == 0 and qh->channel == 0. 
+-00431          *
+-00432          * So qh->channel != NULL branch is not used and just not removed from the
+-00433          * source file. It is required for another possible approach which is,
+-00434          * do not disable and release the channel when ISOC session completed, 
+-00435          * just move QH to inactive schedule until new QTD arrives. 
+-00436          * On new QTD, the QH moved back to 'ready' schedule,
+-00437          * starting frame and therefore starting desc_index are recalculated.
+-00438          * In this case channel is released only on ep_disable.
+-00439          */
+-00440          
+-00441         /* Calculate starting descriptor index. For INTERRUPT endpoint it is always 0. */
+-00442         if (qh->channel) {
+-00443                 frame = calc_starting_frame(hcd, qh, &skip_frames);     
+-00444                 /* 
+-00445                  * Calculate initial descriptor index based on FrameList current bitmap
+-00446                  * and servicing period.
+-00447                  */
+-00448                 fr_idx_tmp = frame_list_idx(frame);
+-00449                 fr_idx = (MAX_FRLIST_EN_NUM + frame_list_idx(qh->sched_frame) - fr_idx_tmp) 
+-00450                                 % frame_incr_val(qh);
+-00451                 fr_idx = (fr_idx + fr_idx_tmp) % MAX_FRLIST_EN_NUM;
+-00452         }
+-00453         else {
+-00454                 qh->sched_frame = calc_starting_frame(hcd, qh, &skip_frames);   
+-00455                 fr_idx = frame_list_idx(qh->sched_frame);
+-00456         }
+-00457         
+-00458         qh->td_first = qh->td_last =  frame_to_desc_idx(qh, fr_idx);
+-00459         
+-00460         return skip_frames;
+-00461 }
+-00462  
+-00463 #define ISOC_URB_GIVEBACK_ASAP
+-00464  
+-00465 #define MAX_ISOC_XFER_SIZE_FS 1023
+-00466 #define MAX_ISOC_XFER_SIZE_HS 3072
+-00467 #define DESCNUM_THRESHOLD 4
+-00468 
+-00469 static void init_isoc_dma_desc(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh, uint8_t skip_frames)
+-00470 {
+-00471         struct dwc_otg_hcd_iso_packet_desc *frame_desc;
+-00472         dwc_otg_qtd_t *qtd;
+-00473         dwc_otg_host_dma_desc_t *dma_desc;
+-00474         uint16_t idx, inc, n_desc, ntd_max, max_xfer_size;
+-00475         
+-00476         idx = qh->td_last;
+-00477         inc = qh->interval;
+-00478         n_desc = 0;
+-00479         
+-00480         ntd_max = (max_desc_num(qh) + qh->interval - 1) / qh->interval;
+-00481         if (skip_frames && !qh->channel)
+-00482                 ntd_max = ntd_max - skip_frames / qh->interval; 
+-00483         
+-00484         max_xfer_size = (qh->dev_speed == DWC_OTG_EP_SPEED_HIGH) ? MAX_ISOC_XFER_SIZE_HS 
+-00485                                                                  : MAX_ISOC_XFER_SIZE_FS;
+-00486                         
+-00487         DWC_CIRCLEQ_FOREACH(qtd, &qh->qtd_list, qtd_list_entry) {
+-00488                 while ((qh->ntd < ntd_max) && (qtd->isoc_frame_index_last < qtd->urb->packet_count)) {
+-00489                                 
+-00490                         dma_desc = &qh->desc_list[idx];
+-00491                         dwc_memset(dma_desc, 0x00, sizeof(dwc_otg_host_dma_desc_t));
+-00492 
+-00493                         frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index_last];
+-00494                         
+-00495                         if (frame_desc->length > max_xfer_size)
+-00496                                 qh->n_bytes[idx] = max_xfer_size;
+-00497                         else
+-00498                                 qh->n_bytes[idx] = frame_desc->length;
+-00499                         dma_desc->status.b_isoc.n_bytes = qh->n_bytes[idx];
+-00500                         dma_desc->status.b_isoc.a = 1;
+-00501                         
+-00502                         dma_desc->buf = qtd->urb->dma + frame_desc->offset;
+-00503                         
+-00504                         qh->ntd++;
+-00505 
+-00506                         qtd->isoc_frame_index_last++;
+-00507                         
+-00508                 #ifdef  ISOC_URB_GIVEBACK_ASAP
+-00509                         /* 
+-00510                          * Set IOC for each descriptor corresponding to the 
+-00511                          * last frame of the URB.
+-00512                          */     
+-00513                         if (qtd->isoc_frame_index_last == qtd->urb->packet_count)
+-00514                                 dma_desc->status.b_isoc.ioc = 1;
+-00515                         
+-00516                 #endif  
+-00517                         idx = desclist_idx_inc(idx, inc, qh->dev_speed);
+-00518                         n_desc++;
+-00519                         
+-00520                 }
+-00521                 qtd->in_process = 1;
+-00522         }
+-00523         
+-00524         qh->td_last = idx;
+-00525         
+-00526 #ifdef  ISOC_URB_GIVEBACK_ASAP
+-00527         /* Set IOC for the last descriptor if descriptor list is full */        
+-00528         if (qh->ntd == ntd_max) {
+-00529                 idx = desclist_idx_dec(qh->td_last, inc, qh->dev_speed);
+-00530                 qh->desc_list[idx].status.b_isoc.ioc = 1;
+-00531         }
+-00532 #else   
+-00533         /* 
+-00534          * Set IOC bit only for one descriptor. 
+-00535          * Always try to be ahead of HW processing,
+-00536          * i.e. on IOC generation driver activates next descriptors but
+-00537          * core continues to process descriptors followed the one with IOC set.
+-00538          */
+-00539 
+-00540         if (n_desc > DESCNUM_THRESHOLD) {
+-00541                 /* 
+-00542                  * Move IOC "up". Required even if there is only one QTD 
+-00543                  * in the list, cause QTDs migth continue to be queued,
+-00544                  * but during the activation it was only one queued.
+-00545                  * Actually more than one QTD might be in the list if this function called 
+-00546                  * from XferCompletion - QTDs was queued during HW processing of the previous
+-00547                  * descriptor chunk.
+-00548                  */     
+-00549                 idx = dwc_desclist_idx_dec(idx, inc * ((qh->ntd + 1) / 2), qh->dev_speed);
+-00550         }
+-00551         else {
+-00552                 /* 
+-00553                  * Set the IOC for the latest descriptor
+-00554                  * if either number of descriptor is not greather than threshold
+-00555                  * or no more new descriptors activated.
+-00556                  */     
+-00557                 idx = dwc_desclist_idx_dec(qh->td_last, inc, qh->dev_speed);
+-00558         }
+-00559         
+-00560         qh->desc_list[idx].status.b_isoc.ioc = 1;
+-00561 #endif
+-00562 }
+-00563 
+-00564 
+-00565 static void init_non_isoc_dma_desc(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
+-00566 {
+-00567 
+-00568         dwc_hc_t *hc;
+-00569         dwc_otg_host_dma_desc_t *dma_desc;
+-00570         dwc_otg_qtd_t *qtd;
+-00571         int     num_packets, len, n_desc = 0;
+-00572         
+-00573         hc =  qh->channel;
+-00574          
+-00575         /* 
+-00576          * Start with hc->xfer_buff initialized in 
+-00577          * assign_and_init_hc(), then if SG transfer consists of multiple URBs,
+-00578          * this pointer re-assigned to the buffer of the currently processed QTD.
+-00579          * For non-SG request there is always one QTD active.
+-00580          */
+-00581         
+-00582         DWC_CIRCLEQ_FOREACH(qtd, &qh->qtd_list, qtd_list_entry) {
+-00583                         
+-00584                 if (n_desc) {
+-00585                         /* SG request - more than 1 QTDs */
+-00586                         hc->xfer_buff = (uint8_t *)qtd->urb->dma + qtd->urb->actual_length;
+-00587                         hc->xfer_len = qtd->urb->length - qtd->urb->actual_length;
+-00588                 }
+-00589 
+-00590                 qtd->n_desc = 0;
+-00591                 
+-00592                 do {
+-00593                         dma_desc = &qh->desc_list[n_desc];
+-00594                         len = hc->xfer_len;
+-00595                         
+-00596 
+-00597                         if (len > MAX_DMA_DESC_SIZE)
+-00598                                 len = MAX_DMA_DESC_SIZE - hc->max_packet + 1;
+-00599                         
+-00600                         if (hc->ep_is_in) {
+-00601                                 if (len > 0) {
+-00602                                         num_packets = (len + hc->max_packet - 1) / hc->max_packet;
+-00603                                 }
+-00604                                 else {
+-00605                                         /* Need 1 packet for transfer length of 0. */
+-00606                                         num_packets = 1;
+-00607                                 }
+-00608                                 /* Always program an integral # of max packets for IN transfers. */
+-00609                                 len = num_packets * hc->max_packet;     
+-00610                         }                               
+-00611                                 
+-00612                         dma_desc->status.b.n_bytes = len;
+-00613                         
+-00614                         qh->n_bytes[n_desc] = len;
+-00615                         
+-00616 
+-00617                         if ((qh->ep_type == UE_CONTROL) && (qtd->control_phase == DWC_OTG_CONTROL_SETUP))
+-00618                                 dma_desc->status.b.sup = 1; /* Setup Packet */
+-00619                                 
+-00620                         dma_desc->status.b.a = 1; /* Active descriptor */
+-00621                         
+-00622                         dma_desc->buf = (uint32_t) hc->xfer_buff;
+-00623 
+-00624                         /* 
+-00625                          * Last descriptor(or single) of IN transfer 
+-00626                          * with actual size less than MaxPacket.
+-00627                          */
+-00628                         if (len > hc->xfer_len) {
+-00629                                 hc->xfer_len = 0;
+-00630                         }
+-00631                         else {
+-00632                                 hc->xfer_buff += len;
+-00633                                 hc->xfer_len -= len;
+-00634                         }
+-00635                         
+-00636                         qtd->n_desc++;
+-00637                         n_desc++;
+-00638                 }
+-00639                 while ((hc->xfer_len > 0) && (n_desc != MAX_DMA_DESC_NUM_GENERIC));
+-00640                 
+-00641 
+-00642                 qtd->in_process = 1;
+-00643                 
+-00644                 if (n_desc == MAX_DMA_DESC_NUM_GENERIC)
+-00645                         break;
+-00646         }
+-00647 
+-00648         if (n_desc) {
+-00649                 /* Request Transfer Complete interrupt for the last descriptor */
+-00650                 qh->desc_list[n_desc-1].status.b.ioc = 1;
+-00651                 /* End of List indicator */
+-00652                 qh->desc_list[n_desc-1].status.b.eol = 1;
+-00653                 
+-00654                 hc->ntd = n_desc;
+-00655         }
+-00656 }
+-00657 
+-00675 void dwc_otg_hcd_start_xfer_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
+-00676 {
+-00677         /* Channel is already assigned */
+-00678         dwc_hc_t *hc = qh->channel;
+-00679         uint8_t skip_frames = 0;
+-00680         
+-00681         switch (hc->ep_type) {
+-00682         case DWC_OTG_EP_TYPE_CONTROL:
+-00683         case DWC_OTG_EP_TYPE_BULK:
+-00684                 init_non_isoc_dma_desc(hcd, qh);
+-00685                 
+-00686                 dwc_otg_hc_start_transfer_ddma(hcd->core_if, hc);
+-00687                 break;
+-00688         case DWC_OTG_EP_TYPE_INTR:
+-00689                 init_non_isoc_dma_desc(hcd, qh);
+-00690                 
+-00691                 update_frame_list(hcd, qh, 1);
+-00692                 
+-00693                 dwc_otg_hc_start_transfer_ddma(hcd->core_if, hc);
+-00694                 break;
+-00695         case DWC_OTG_EP_TYPE_ISOC:
+-00696                         
+-00697                 if(!qh->ntd)
+-00698                         skip_frames = recalc_initial_desc_idx(hcd, qh);
+-00699                 
+-00700                 init_isoc_dma_desc(hcd, qh, skip_frames);
+-00701 
+-00702                 if (!hc->xfer_started) {
+-00703 
+-00704                         update_frame_list(hcd, qh, 1);
+-00705                 
+-00706                         /* 
+-00707                          * Always set to max, instead of actual size.
+-00708                          * Otherwise ntd will be changed with 
+-00709                          * channel being enabled. Not recommended.
+-00710                          *
+-00711                          */     
+-00712                         hc->ntd = max_desc_num(qh);
+-00713                         /* Enable channel only once for ISOC */ 
+-00714                         dwc_otg_hc_start_transfer_ddma(hcd->core_if, hc);
+-00715                 }
+-00716                 
+-00717                 break;
+-00718         default:
+-00719                 
+-00720                 break;
+-00721         }
+-00722 }
+-00723 
+-00724 static void complete_isoc_xfer_ddma(dwc_otg_hcd_t *hcd,
+-00725                                    dwc_hc_t *hc,
+-00726                                    dwc_otg_hc_regs_t *hc_regs,
+-00727                                    dwc_otg_halt_status_e halt_status)
+-00728 {
+-00729         struct dwc_otg_hcd_iso_packet_desc      *frame_desc;            
+-00730         dwc_otg_qtd_t                           *qtd, *qtd_tmp;
+-00731         dwc_otg_qh_t                            *qh;
+-00732         dwc_otg_host_dma_desc_t                 *dma_desc;
+-00733         uint16_t                                idx, remain;
+-00734         uint8_t                                 urb_compl;      
+-00735         
+-00736         qh = hc->qh;
+-00737         idx = qh->td_first;
+-00738         
+-00739 
+-00740         if (hc->halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE) {
+-00741                 DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp, &hc->qh->qtd_list, qtd_list_entry)
+-00742                         qtd->in_process = 0;
+-00743                 return; 
+-00744         }
+-00745         else if ((halt_status == DWC_OTG_HC_XFER_AHB_ERR) || 
+-00746                         (halt_status == DWC_OTG_HC_XFER_BABBLE_ERR)) {
+-00747                 /* 
+-00748                  * Channel is halted in these error cases.
+-00749                  * Considered as serious issues.
+-00750                  * Complete all URBs marking all frames as failed, 
+-00751                  * irrespective whether some of the descriptors(frames) succeeded or no.
+-00752                  * Pass error code to completion routine as well, to
+-00753                  * update urb->status, some of class drivers might use it to stop
+-00754                  * queing transfer requests.
+-00755                  */     
+-00756                 int err = (halt_status == DWC_OTG_HC_XFER_AHB_ERR) 
+-00757                                                         ? (-DWC_E_IO)
+-00758                                                         : (-DWC_E_OVERFLOW);
+-00759                                                 
+-00760                 DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp, &hc->qh->qtd_list, qtd_list_entry) {
+-00761                         for(idx = 0; idx < qtd->urb->packet_count; idx++) {
+-00762                                 frame_desc = &qtd->urb->iso_descs[idx];
+-00763                                 frame_desc->status = err;
+-00764                         }
+-00765                         hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, err);
+-00766                         dwc_otg_hcd_qtd_remove_and_free(hcd, qtd, qh);
+-00767                 }
+-00768                 return; 
+-00769         }
+-00770         
+-00771         
+-00772         DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp, &hc->qh->qtd_list, qtd_list_entry) {
+-00773                 
+-00774                 if (!qtd->in_process)
+-00775                     break;
+-00776                 
+-00777                 urb_compl = 0;
+-00778                 
+-00779                 do {
+-00780 
+-00781                         dma_desc = &qh->desc_list[idx];
+-00782                         
+-00783                         frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index];
+-00784                         remain = hc->ep_is_in ? dma_desc->status.b_isoc.n_bytes : 0;
+-00785         
+-00786                         if (dma_desc->status.b_isoc.sts == DMA_DESC_STS_PKTERR) {
+-00787                                 /* 
+-00788                                  * XactError or, unable to complete all the transactions 
+-00789                                  * in the scheduled micro-frame/frame, 
+-00790                                  * both indicated by DMA_DESC_STS_PKTERR.
+-00791                                  */     
+-00792                                 qtd->urb->error_count++;
+-00793                                 frame_desc->actual_length = qh->n_bytes[idx] - remain;
+-00794                                 frame_desc->status = -DWC_E_PROTOCOL;
+-00795                         }
+-00796                         else {
+-00797                                 /* Success */   
+-00798                                                                 
+-00799                                 frame_desc->actual_length = qh->n_bytes[idx] - remain;
+-00800                                 frame_desc->status = 0;
+-00801                         }
+-00802                         
+-00803                         if (++qtd->isoc_frame_index == qtd->urb->packet_count) {
+-00804                                 /*
+-00805                                  * urb->status is not used for isoc transfers here.
+-00806                                  * The individual frame_desc status are used instead.
+-00807                                  */
+-00808 
+-00809                                 hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, 0);
+-00810                                 dwc_otg_hcd_qtd_remove_and_free(hcd, qtd, qh);
+-00811                                 
+-00812                                 /* 
+-00813                                  * This check is necessary because urb_dequeue can be called 
+-00814                                  * from urb complete callback(sound driver example).
+-00815                                  * All pending URBs are dequeued there, so no need for
+-00816                                  * further processing.
+-00817                                  */
+-00818                                 if (hc->halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE) {   
+-00819                                         return;
+-00820                                 }
+-00821                                 
+-00822                                 urb_compl = 1;          
+-00823                                 
+-00824                         }
+-00825                         
+-00826                         qh->ntd--;
+-00827                         
+-00828                         /* Stop if IOC requested descriptor reached */
+-00829                         if (dma_desc->status.b_isoc.ioc) {
+-00830                                 idx = desclist_idx_inc(idx, qh->interval, hc->speed);   
+-00831                                 goto stop_scan;
+-00832                         }
+-00833                         
+-00834                         idx = desclist_idx_inc(idx, qh->interval, hc->speed);
+-00835                         
+-00836                         if (urb_compl)
+-00837                                 break;
+-00838                 }
+-00839                 while(idx != qh->td_first);
+-00840         }
+-00841 stop_scan:      
+-00842         qh->td_first = idx;
+-00843 }
+-00844         
+-00845 uint8_t update_non_isoc_urb_state_ddma(dwc_otg_hcd_t * hcd,
+-00846                            dwc_hc_t * hc,
+-00847                            dwc_otg_qtd_t * qtd,
+-00848                            dwc_otg_host_dma_desc_t * dma_desc,
+-00849                            dwc_otg_halt_status_e halt_status,
+-00850                            uint32_t n_bytes,
+-00851                            uint8_t *xfer_done)
+-00852 {
+-00853 
+-00854         uint16_t remain = hc->ep_is_in ? dma_desc->status.b.n_bytes : 0;
+-00855         dwc_otg_hcd_urb_t *urb = qtd->urb;
+-00856         
+-00857         
+-00858         if (halt_status == DWC_OTG_HC_XFER_AHB_ERR) {
+-00859                 urb->status = -DWC_E_IO;
+-00860                 return 1;
+-00861         }
+-00862         if (dma_desc->status.b.sts == DMA_DESC_STS_PKTERR) {
+-00863                 switch (halt_status) {
+-00864                 case DWC_OTG_HC_XFER_STALL:
+-00865                         urb->status = -DWC_E_PIPE;
+-00866                         break;
+-00867                 case DWC_OTG_HC_XFER_BABBLE_ERR:
+-00868                         urb->status = -DWC_E_OVERFLOW;
+-00869                         break;
+-00870                 case DWC_OTG_HC_XFER_XACT_ERR:
+-00871                         urb->status = -DWC_E_PROTOCOL;
+-00872                         break;
+-00873                 default:        
+-00874                         DWC_ERROR("%s: Unhandled descriptor error status (%d)\n", __func__,
+-00875                                   halt_status);
+-00876                         break;
+-00877                 }
+-00878                 return 1;
+-00879         }
+-00880         
+-00881         if (dma_desc->status.b.a == 1) {
+-00882                 DWC_DEBUGPL(DBG_HCDV, "Active descriptor encountered on channel %d\n", hc->hc_num);
+-00883                 return 0;
+-00884         }
+-00885         
+-00886         if (hc->ep_type == DWC_OTG_EP_TYPE_CONTROL) {
+-00887             if (qtd->control_phase == DWC_OTG_CONTROL_DATA) {
+-00888                 urb->actual_length += n_bytes - remain;
+-00889                 if (remain || urb->actual_length == urb->length) {
+-00890                         /* 
+-00891                          * For Control Data stage do not set urb->status=0 to prevent
+-00892                          * URB callback. Set it when Status phase done. See below.
+-00893                          */
+-00894                         *xfer_done = 1;
+-00895                 }               
+-00896             
+-00897             }
+-00898             else if (qtd->control_phase == DWC_OTG_CONTROL_STATUS) {
+-00899                 urb->status = 0;
+-00900                 *xfer_done = 1;
+-00901             }
+-00902             /* No handling for SETUP stage */
+-00903 
+-00904         }
+-00905         else { 
+-00906             /* BULK and INTR */
+-00907             urb->actual_length += n_bytes - remain;
+-00908             if (remain || urb->actual_length == urb->length) {
+-00909                 urb->status = 0;
+-00910                 *xfer_done = 1;
+-00911             }
+-00912         }
+-00913 
+-00914         return 0;
+-00915 }
+-00916 
+-00917 static void complete_non_isoc_xfer_ddma(dwc_otg_hcd_t * hcd,
+-00918                                         dwc_hc_t * hc,
+-00919                                         dwc_otg_hc_regs_t * hc_regs,
+-00920                                         dwc_otg_halt_status_e halt_status)
+-00921 {
+-00922         dwc_otg_hcd_urb_t       *urb = NULL;
+-00923         dwc_otg_qtd_t           *qtd, *qtd_tmp;
+-00924         dwc_otg_qh_t            *qh;
+-00925         dwc_otg_host_dma_desc_t *dma_desc;
+-00926         uint32_t                n_bytes, n_desc, i;
+-00927         uint8_t                 failed = 0, xfer_done;
+-00928         
+-00929         n_desc = 0;
+-00930         
+-00931         qh = hc->qh;
+-00932 
+-00933         
+-00934         if (hc->halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE) {
+-00935                 DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp, &hc->qh->qtd_list, qtd_list_entry) {
+-00936                         qtd->in_process = 0;
+-00937                 }
+-00938                 return;
+-00939         }
+-00940         
+-00941         DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp, &qh->qtd_list, qtd_list_entry) {
+-00942                 
+-00943                 urb = qtd->urb;
+-00944 
+-00945                 n_bytes = 0; 
+-00946                 xfer_done = 0; 
+-00947                 
+-00948                 for (i = 0; i < qtd->n_desc; i++) {
+-00949                         dma_desc = &qh->desc_list[n_desc];
+-00950                 
+-00951                         n_bytes = qh->n_bytes[n_desc];
+-00952                         
+-00953                         
+-00954                         failed = update_non_isoc_urb_state_ddma(hcd, hc, qtd, dma_desc, 
+-00955                                                                 halt_status, n_bytes, &xfer_done);
+-00956                         
+-00957                         if (failed || (xfer_done && (urb->status != -DWC_E_IN_PROGRESS))) {
+-00958                                 
+-00959                                 hcd->fops->complete(hcd, urb->priv, urb, urb->status);
+-00960                                 dwc_otg_hcd_qtd_remove_and_free(hcd, qtd, qh);
+-00961 
+-00962                                 if (failed)
+-00963                                         goto stop_scan;
+-00964                         }
+-00965                         else if (qh->ep_type == UE_CONTROL) {
+-00966                                 if (qtd->control_phase == DWC_OTG_CONTROL_SETUP) {
+-00967                                         if (urb->length > 0) {
+-00968                                                 qtd->control_phase = DWC_OTG_CONTROL_DATA;
+-00969                                         } else {
+-00970                                                 qtd->control_phase = DWC_OTG_CONTROL_STATUS;
+-00971                                         }
+-00972                                         DWC_DEBUGPL(DBG_HCDV, "  Control setup transaction done\n");
+-00973                                 }
+-00974                                 else if(qtd->control_phase == DWC_OTG_CONTROL_DATA) {
+-00975                                         if (xfer_done) {
+-00976                                                 qtd->control_phase = DWC_OTG_CONTROL_STATUS;
+-00977                                                 DWC_DEBUGPL(DBG_HCDV, "  Control data transfer done\n");
+-00978                                         } else if (i+1 == qtd->n_desc){
+-00979                                                 /* 
+-00980                                                  * Last descriptor for Control data stage which is
+-00981                                                  * not completed yet.
+-00982                                                  */     
+-00983                                                 dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
+-00984                                         }
+-00985                                 }
+-00986                         }
+-00987                         
+-00988                         n_desc++;
+-00989                 }
+-00990                 
+-00991         }
+-00992         
+-00993 stop_scan:      
+-00994         
+-00995         if (qh->ep_type != UE_CONTROL) {
+-00996                 /* 
+-00997                  * Resetting the data toggle for bulk
+-00998                  * and interrupt endpoints in case of stall. See handle_hc_stall_intr() 
+-00999                  */     
+-01000                 if (halt_status == DWC_OTG_HC_XFER_STALL) {     
+-01001                         qh->data_toggle = DWC_OTG_HC_PID_DATA0; 
+-01002                 }
+-01003                 else {
+-01004                         dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
+-01005                 }
+-01006         }
+-01007         
+-01008         if (halt_status == DWC_OTG_HC_XFER_COMPLETE) {
+-01009                 hcint_data_t hcint;
+-01010                 hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
+-01011                 if (hcint.b.nyet) {
+-01012                         /*
+-01013                          * Got a NYET on the last transaction of the transfer. It
+-01014                          * means that the endpoint should be in the PING state at the
+-01015                          * beginning of the next transfer.
+-01016                          */
+-01017                         qh->ping_state = 1;
+-01018                         clear_hc_int(hc_regs, nyet);
+-01019                 }
+-01020 
+-01021         }
+-01022 
+-01023 }
+-01024 
+-01042 void dwc_otg_hcd_complete_xfer_ddma(dwc_otg_hcd_t *hcd,
+-01043                             dwc_hc_t *hc,
+-01044                             dwc_otg_hc_regs_t *hc_regs,
+-01045                             dwc_otg_halt_status_e halt_status)
+-01046 {
+-01047         uint8_t continue_isoc_xfer = 0;
+-01048         dwc_otg_transaction_type_e tr_type;
+-01049         dwc_otg_qh_t *qh = hc->qh;
+-01050         
+-01051         if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
+-01052 
+-01053                 complete_isoc_xfer_ddma(hcd, hc, hc_regs, halt_status);
+-01054                 
+-01055                 /* Release the channel if halted or session completed */        
+-01056                 if (halt_status != DWC_OTG_HC_XFER_COMPLETE ||
+-01057                                 DWC_CIRCLEQ_EMPTY(&qh->qtd_list)) {
+-01058 
+-01059                         /* Halt the channel if session completed */     
+-01060                         if (halt_status == DWC_OTG_HC_XFER_COMPLETE) {
+-01061                                 dwc_otg_hc_halt(hcd->core_if, hc, halt_status);
+-01062                         }       
+-01063                         
+-01064                         release_channel_ddma(hcd, qh);
+-01065                         dwc_otg_hcd_qh_remove(hcd, qh);
+-01066                 }
+-01067                 else {
+-01068                         /* Keep in assigned schedule to continue transfer */
+-01069                         DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_assigned,
+-01070                                            &qh->qh_list_entry);
+-01071                         continue_isoc_xfer = 1;
+-01072                                 
+-01073                 }
+-01077         }
+-01078         else {
+-01079                 /* Scan descriptor list to complete the URB(s), then release the channel */     
+-01080                 complete_non_isoc_xfer_ddma(hcd, hc, hc_regs, halt_status);
+-01081                 
+-01082                 release_channel_ddma(hcd, qh);
+-01083                 
+-01084                 dwc_otg_hcd_qh_remove(hcd, qh);
+-01085                 
+-01086                 if (!DWC_CIRCLEQ_EMPTY(&qh->qtd_list)) {
+-01087                         /* Add back to inactive non-periodic schedule on normal completion */
+-01088                         dwc_otg_hcd_qh_add(hcd, qh);
+-01089                 }
+-01090         
+-01091 
+-01092         }
+-01093         tr_type = dwc_otg_hcd_select_transactions(hcd);
+-01094         if (tr_type != DWC_OTG_TRANSACTION_NONE || continue_isoc_xfer) {
+-01095                 if (continue_isoc_xfer) {
+-01096                         if (tr_type == DWC_OTG_TRANSACTION_NONE) {
+-01097                                 tr_type = DWC_OTG_TRANSACTION_PERIODIC;
+-01098                         } else if (tr_type == DWC_OTG_TRANSACTION_NON_PERIODIC) {
+-01099                                 tr_type = DWC_OTG_TRANSACTION_ALL;
+-01100                         }
+-01101                 }
+-01102                 dwc_otg_hcd_queue_transactions(hcd, tr_type);
+-01103         }
+-01104 }
+-01105         
+-01106 #endif  /* DWC_DEVICE_ONLY */
+-
    Generated on Tue May 5 02:22:48 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++
    Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
    ++

    dwc_otg_hcd_ddma.c

    Go to the documentation of this file.
    00001 /*==========================================================================
++00002  * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd_ddma.c $
++00003  * $Revision: #10 $
++00004  * $Date: 2011/10/20 $
++00005  * $Change: 1869464 $
++00006  *
++00007  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
++00008  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
++00009  * otherwise expressly agreed to in writing between Synopsys and you.
++00010  *
++00011  * The Software IS NOT an item of Licensed Software or Licensed Product under
++00012  * any End User Software License Agreement or Agreement for Licensed Product
++00013  * with Synopsys or any supplement thereto. You are permitted to use and
++00014  * redistribute this Software in source and binary forms, with or without
++00015  * modification, provided that redistributions of source code must retain this
++00016  * notice. You may not view, use, disclose, copy or distribute this file or
++00017  * any information contained herein except pursuant to this license grant from
++00018  * Synopsys. If you do not agree with this notice, including the disclaimer
++00019  * below, then you are not authorized to use the Software.
++00020  *
++00021  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
++00022  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++00023  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++00024  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
++00025  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++00026  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
++00027  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
++00028  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
++00029  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
++00030  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
++00031  * DAMAGE.
++00032  * ========================================================================== */
++00033 #ifndef DWC_DEVICE_ONLY
++00034 
++00039 #include "dwc_otg_hcd.h"
++00040 #include "dwc_otg_regs.h"
++00041 
++00042 static inline uint8_t frame_list_idx(uint16_t frame)
++00043 {
++00044         return (frame & (MAX_FRLIST_EN_NUM - 1));
++00045 }
++00046 
++00047 static inline uint16_t desclist_idx_inc(uint16_t idx, uint16_t inc, uint8_t speed)
++00048 {
++00049         return (idx + inc) &
++00050             (((speed ==
++00051                DWC_OTG_EP_SPEED_HIGH) ? MAX_DMA_DESC_NUM_HS_ISOC :
++00052               MAX_DMA_DESC_NUM_GENERIC) - 1);
++00053 }
++00054 
++00055 static inline uint16_t desclist_idx_dec(uint16_t idx, uint16_t inc, uint8_t speed)
++00056 {
++00057         return (idx - inc) &
++00058             (((speed ==
++00059                DWC_OTG_EP_SPEED_HIGH) ? MAX_DMA_DESC_NUM_HS_ISOC :
++00060               MAX_DMA_DESC_NUM_GENERIC) - 1);
++00061 }
++00062 
++00063 static inline uint16_t max_desc_num(dwc_otg_qh_t * qh)
++00064 {
++00065         return (((qh->ep_type == UE_ISOCHRONOUS)
++00066                  && (qh->dev_speed == DWC_OTG_EP_SPEED_HIGH))
++00067                 ? MAX_DMA_DESC_NUM_HS_ISOC : MAX_DMA_DESC_NUM_GENERIC);
++00068 }
++00069 static inline uint16_t frame_incr_val(dwc_otg_qh_t * qh)
++00070 {
++00071         return ((qh->dev_speed == DWC_OTG_EP_SPEED_HIGH)
++00072                 ? ((qh->interval + 8 - 1) / 8)
++00073                 : qh->interval);
++00074 }
++00075 
++00076 static int desc_list_alloc(dwc_otg_qh_t * qh)
++00077 {
++00078         int retval = 0;
++00079 
++00080         qh->desc_list = (dwc_otg_host_dma_desc_t *)
++00081             DWC_DMA_ALLOC(sizeof(dwc_otg_host_dma_desc_t) * max_desc_num(qh),
++00082                           &qh->desc_list_dma);
++00083 
++00084         if (!qh->desc_list) {
++00085                 retval = -DWC_E_NO_MEMORY;
++00086                 DWC_ERROR("%s: DMA descriptor list allocation failed\n", __func__);
++00087                 
++00088         }
++00089 
++00090         dwc_memset(qh->desc_list, 0x00,
++00091                    sizeof(dwc_otg_host_dma_desc_t) * max_desc_num(qh));
++00092 
++00093         qh->n_bytes =
++00094             (uint32_t *) DWC_ALLOC(sizeof(uint32_t) * max_desc_num(qh));
++00095 
++00096         if (!qh->n_bytes) {
++00097                 retval = -DWC_E_NO_MEMORY;
++00098                 DWC_ERROR
++00099                     ("%s: Failed to allocate array for descriptors' size actual values\n",
++00100                      __func__);
++00101 
++00102         }
++00103         return retval;
++00104 
++00105 }
++00106 
++00107 static void desc_list_free(dwc_otg_qh_t * qh)
++00108 {
++00109         if (qh->desc_list) {
++00110                 DWC_DMA_FREE(max_desc_num(qh), qh->desc_list,
++00111                              qh->desc_list_dma);
++00112                 qh->desc_list = NULL;
++00113         }
++00114 
++00115         if (qh->n_bytes) {
++00116                 DWC_FREE(qh->n_bytes);
++00117                 qh->n_bytes = NULL;
++00118         }
++00119 }
++00120 
++00121 static int frame_list_alloc(dwc_otg_hcd_t * hcd)
++00122 {
++00123         int retval = 0;
++00124         if (hcd->frame_list)
++00125                 return 0;
++00126 
++00127         hcd->frame_list = DWC_DMA_ALLOC(4 * MAX_FRLIST_EN_NUM,
++00128                                         &hcd->frame_list_dma);
++00129         if (!hcd->frame_list) {
++00130                 retval = -DWC_E_NO_MEMORY;
++00131                 DWC_ERROR("%s: Frame List allocation failed\n", __func__);
++00132         }
++00133 
++00134         dwc_memset(hcd->frame_list, 0x00, 4 * MAX_FRLIST_EN_NUM);
++00135 
++00136         return retval;
++00137 }
++00138 
++00139 static void frame_list_free(dwc_otg_hcd_t * hcd)
++00140 {
++00141         if (!hcd->frame_list)
++00142                 return;
++00143         
++00144         DWC_DMA_FREE(4 * MAX_FRLIST_EN_NUM, hcd->frame_list, hcd->frame_list_dma);
++00145         hcd->frame_list = NULL;
++00146 }
++00147 
++00148 static void per_sched_enable(dwc_otg_hcd_t * hcd, uint16_t fr_list_en)
++00149 {
++00150 
++00151         hcfg_data_t hcfg;
++00152 
++00153         hcfg.d32 = DWC_READ_REG32(&hcd->core_if->host_if->host_global_regs->hcfg);
++00154 
++00155         if (hcfg.b.perschedena) {
++00156                 /* already enabled */
++00157                 return;
++00158         }
++00159 
++00160         DWC_WRITE_REG32(&hcd->core_if->host_if->host_global_regs->hflbaddr,
++00161                         hcd->frame_list_dma);
++00162 
++00163         switch (fr_list_en) {
++00164         case 64:
++00165                 hcfg.b.frlisten = 3;
++00166                 break;
++00167         case 32:
++00168                 hcfg.b.frlisten = 2;
++00169                 break;
++00170         case 16:
++00171                 hcfg.b.frlisten = 1;
++00172                 break;
++00173         case 8:
++00174                 hcfg.b.frlisten = 0;
++00175                 break;
++00176         default:
++00177                 break;
++00178         }
++00179 
++00180         hcfg.b.perschedena = 1;
++00181 
++00182         DWC_DEBUGPL(DBG_HCD, "Enabling Periodic schedule\n");
++00183         DWC_WRITE_REG32(&hcd->core_if->host_if->host_global_regs->hcfg, hcfg.d32);
++00184 
++00185 }
++00186 
++00187 static void per_sched_disable(dwc_otg_hcd_t * hcd)
++00188 {
++00189         hcfg_data_t hcfg;
++00190 
++00191         hcfg.d32 = DWC_READ_REG32(&hcd->core_if->host_if->host_global_regs->hcfg);
++00192         
++00193         if (!hcfg.b.perschedena) {
++00194                 /* already disabled */
++00195                 return;
++00196         }
++00197         hcfg.b.perschedena = 0;
++00198 
++00199         DWC_DEBUGPL(DBG_HCD, "Disabling Periodic schedule\n");
++00200         DWC_WRITE_REG32(&hcd->core_if->host_if->host_global_regs->hcfg, hcfg.d32);
++00201 }
++00202 
++00203 /* 
++00204  * Activates/Deactivates FrameList entries for the channel 
++00205  * based on endpoint servicing period.
++00206  */
++00207 void update_frame_list(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh, uint8_t enable)
++00208 {
++00209         uint16_t i, j, inc;
++00210         dwc_hc_t *hc = NULL;
++00211 
++00212         if (!qh->channel) {
++00213                 DWC_ERROR("qh->channel = %p", qh->channel);
++00214                 return;
++00215         }
++00216 
++00217         if (!hcd) {
++00218                 DWC_ERROR("------hcd = %p", hcd);
++00219                 return;
++00220         }
++00221 
++00222         if (!hcd->frame_list) {
++00223                 DWC_ERROR("-------hcd->frame_list = %p", hcd->frame_list);
++00224                 return;
++00225         }
++00226 
++00227         hc = qh->channel;
++00228         inc = frame_incr_val(qh);
++00229         if (qh->ep_type == UE_ISOCHRONOUS)
++00230                 i = frame_list_idx(qh->sched_frame);
++00231         else
++00232                 i = 0;
++00233 
++00234         j = i;
++00235         do {
++00236                 if (enable)
++00237                         hcd->frame_list[j] |= (1 << hc->hc_num);
++00238                 else
++00239                         hcd->frame_list[j] &= ~(1 << hc->hc_num);
++00240                 j = (j + inc) & (MAX_FRLIST_EN_NUM - 1);
++00241         }
++00242         while (j != i);
++00243         if (!enable)
++00244                 return;
++00245         hc->schinfo = 0;
++00246         if (qh->channel->speed == DWC_OTG_EP_SPEED_HIGH) {
++00247                 j = 1;
++00248                 /* TODO - check this */
++00249                 inc = (8 + qh->interval - 1) / qh->interval;
++00250                 for (i = 0; i < inc; i++) {
++00251                         hc->schinfo |= j;
++00252                         j = j << qh->interval;
++00253                 }
++00254         } else {
++00255                 hc->schinfo = 0xff;
++00256         }
++00257 }
++00258 
++00259 #if 1
++00260 void dump_frame_list(dwc_otg_hcd_t * hcd)
++00261 {
++00262         int i = 0;
++00263         DWC_PRINTF("--FRAME LIST (hex) --\n");
++00264         for (i = 0; i < MAX_FRLIST_EN_NUM; i++) {
++00265                 DWC_PRINTF("%x\t", hcd->frame_list[i]);
++00266                 if (!(i % 8) && i)
++00267                         DWC_PRINTF("\n");
++00268         }
++00269         DWC_PRINTF("\n----\n");
++00270 
++00271 }
++00272 #endif
++00273 
++00274 static void release_channel_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
++00275 {
++00276         dwc_hc_t *hc = qh->channel;
++00277         if (dwc_qh_is_non_per(qh))
++00278                 hcd->non_periodic_channels--;
++00279         else
++00280                 update_frame_list(hcd, qh, 0);
++00281 
++00282         /* 
++00283          * The condition is added to prevent double cleanup try in case of device
++00284          * disconnect. See channel cleanup in dwc_otg_hcd_disconnect_cb().
++00285          */
++00286         if (hc->qh) {
++00287                 dwc_otg_hc_cleanup(hcd->core_if, hc);
++00288                 DWC_CIRCLEQ_INSERT_TAIL(&hcd->free_hc_list, hc, hc_list_entry);
++00289                 hc->qh = NULL;
++00290         }
++00291 
++00292         qh->channel = NULL;
++00293         qh->ntd = 0;
++00294 
++00295         if (qh->desc_list) {
++00296                 dwc_memset(qh->desc_list, 0x00,
++00297                            sizeof(dwc_otg_host_dma_desc_t) * max_desc_num(qh));
++00298         }
++00299 }
++00300 
++00312 int dwc_otg_hcd_qh_init_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
++00313 {
++00314         int retval = 0;
++00315 
++00316         if (qh->do_split) {
++00317                 DWC_ERROR("SPLIT Transfers are not supported in Descriptor DMA.\n");
++00318                 return -1;
++00319         }
++00320 
++00321         retval = desc_list_alloc(qh);
++00322 
++00323         if ((retval == 0)
++00324             && (qh->ep_type == UE_ISOCHRONOUS || qh->ep_type == UE_INTERRUPT)) {
++00325                 if (!hcd->frame_list) {
++00326                         retval = frame_list_alloc(hcd);
++00327                         /* Enable periodic schedule on first periodic QH */
++00328                         if (retval == 0)
++00329                                 per_sched_enable(hcd, MAX_FRLIST_EN_NUM);
++00330                 }
++00331         }
++00332 
++00333         qh->ntd = 0;
++00334 
++00335         return retval;
++00336 }
++00337 
++00346 void dwc_otg_hcd_qh_free_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
++00347 {
++00348         desc_list_free(qh);
++00349 
++00350         /* 
++00351          * Channel still assigned due to some reasons. 
++00352          * Seen on Isoc URB dequeue. Channel halted but no subsequent
++00353          * ChHalted interrupt to release the channel. Afterwards
++00354          * when it comes here from endpoint disable routine
++00355          * channel remains assigned.
++00356          */
++00357         if (qh->channel)
++00358                 release_channel_ddma(hcd, qh);
++00359 
++00360         if ((qh->ep_type == UE_ISOCHRONOUS || qh->ep_type == UE_INTERRUPT)
++00361             && !hcd->periodic_channels && hcd->frame_list) {
++00362 
++00363                 per_sched_disable(hcd);
++00364                 frame_list_free(hcd);
++00365         }
++00366 }
++00367 
++00368 static uint8_t frame_to_desc_idx(dwc_otg_qh_t * qh, uint16_t frame_idx)
++00369 {
++00370         if (qh->dev_speed == DWC_OTG_EP_SPEED_HIGH) {
++00371                 /* 
++00372                  * Descriptor set(8 descriptors) index
++00373                  * which is 8-aligned.
++00374                  */
++00375                 return (frame_idx & ((MAX_DMA_DESC_NUM_HS_ISOC / 8) - 1)) * 8;
++00376         } else {
++00377                 return (frame_idx & (MAX_DMA_DESC_NUM_GENERIC - 1));
++00378         }
++00379 }
++00380 
++00381 /* 
++00382  * Determine starting frame for Isochronous transfer. 
++00383  * Few frames skipped to prevent race condition with HC. 
++00384  */
++00385 static uint8_t calc_starting_frame(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh,
++00386                                    uint8_t * skip_frames)
++00387 {
++00388         uint16_t frame = 0;
++00389         hcd->frame_number = dwc_otg_hcd_get_frame_number(hcd);
++00390         
++00391         /* sched_frame is always frame number(not uFrame) both in FS and HS !! */
++00392         
++00393         /* 
++00394          * skip_frames is used to limit activated descriptors number
++00395          * to avoid the situation when HC services the last activated
++00396          * descriptor firstly.
++00397          * Example for FS:
++00398          * Current frame is 1, scheduled frame is 3. Since HC always fetches the descriptor
++00399          * corresponding to curr_frame+1, the descriptor corresponding to frame 2
++00400          * will be fetched. If the number of descriptors is max=64 (or greather) the
++00401          * list will be fully programmed with Active descriptors and it is possible
++00402          * case(rare) that the latest descriptor(considering rollback) corresponding
++00403          * to frame 2 will be serviced first. HS case is more probable because, in fact,
++00404          * up to 11 uframes(16 in the code) may be skipped.
++00405          */
++00406         if (qh->dev_speed == DWC_OTG_EP_SPEED_HIGH) {
++00407                 /* 
++00408                  * Consider uframe counter also, to start xfer asap.
++00409                  * If half of the frame elapsed skip 2 frames otherwise
++00410                  * just 1 frame. 
++00411                  * Starting descriptor index must be 8-aligned, so
++00412                  * if the current frame is near to complete the next one
++00413                  * is skipped as well.
++00414                  */
++00415 
++00416                 if (dwc_micro_frame_num(hcd->frame_number) >= 5) {
++00417                         *skip_frames = 2 * 8;
++00418                         frame = dwc_frame_num_inc(hcd->frame_number, *skip_frames);
++00419                 } else {
++00420                         *skip_frames = 1 * 8;
++00421                         frame = dwc_frame_num_inc(hcd->frame_number, *skip_frames);
++00422                 }
++00423 
++00424                 frame = dwc_full_frame_num(frame);
++00425         } else {
++00426                 /* 
++00427                  * Two frames are skipped for FS - the current and the next.
++00428                  * But for descriptor programming, 1 frame(descriptor) is enough,
++00429                  * see example above.
++00430                  */
++00431                 *skip_frames = 1;
++00432                 frame = dwc_frame_num_inc(hcd->frame_number, 2);
++00433         }
++00434 
++00435         return frame;
++00436 }
++00437 
++00438 /* 
++00439  * Calculate initial descriptor index for isochronous transfer
++00440  * based on scheduled frame. 
++00441  */
++00442 static uint8_t recalc_initial_desc_idx(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
++00443 {
++00444         uint16_t frame = 0, fr_idx, fr_idx_tmp;
++00445         uint8_t skip_frames = 0;
++00446         /* 
++00447          * With current ISOC processing algorithm the channel is being
++00448          * released when no more QTDs in the list(qh->ntd == 0).
++00449          * Thus this function is called only when qh->ntd == 0 and qh->channel == 0. 
++00450          *
++00451          * So qh->channel != NULL branch is not used and just not removed from the
++00452          * source file. It is required for another possible approach which is,
++00453          * do not disable and release the channel when ISOC session completed, 
++00454          * just move QH to inactive schedule until new QTD arrives. 
++00455          * On new QTD, the QH moved back to 'ready' schedule,
++00456          * starting frame and therefore starting desc_index are recalculated.
++00457          * In this case channel is released only on ep_disable.
++00458          */
++00459 
++00460         /* Calculate starting descriptor index. For INTERRUPT endpoint it is always 0. */
++00461         if (qh->channel) {
++00462                 frame = calc_starting_frame(hcd, qh, &skip_frames);
++00463                 /* 
++00464                  * Calculate initial descriptor index based on FrameList current bitmap
++00465                  * and servicing period.
++00466                  */
++00467                 fr_idx_tmp = frame_list_idx(frame);
++00468                 fr_idx =
++00469                     (MAX_FRLIST_EN_NUM + frame_list_idx(qh->sched_frame) -
++00470                      fr_idx_tmp)
++00471                     % frame_incr_val(qh);
++00472                 fr_idx = (fr_idx + fr_idx_tmp) % MAX_FRLIST_EN_NUM;
++00473         } else {
++00474                 qh->sched_frame = calc_starting_frame(hcd, qh, &skip_frames);
++00475                 fr_idx = frame_list_idx(qh->sched_frame);
++00476         }
++00477 
++00478         qh->td_first = qh->td_last = frame_to_desc_idx(qh, fr_idx);
++00479 
++00480         return skip_frames;
++00481 }
++00482 
++00483 #define ISOC_URB_GIVEBACK_ASAP
++00484 
++00485 #define MAX_ISOC_XFER_SIZE_FS 1023
++00486 #define MAX_ISOC_XFER_SIZE_HS 3072
++00487 #define DESCNUM_THRESHOLD 4
++00488 
++00489 static void init_isoc_dma_desc(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh,
++00490                                uint8_t skip_frames)
++00491 {
++00492         struct dwc_otg_hcd_iso_packet_desc *frame_desc;
++00493         dwc_otg_qtd_t *qtd;
++00494         dwc_otg_host_dma_desc_t *dma_desc;
++00495         uint16_t idx, inc, n_desc, ntd_max, max_xfer_size;
++00496 
++00497         idx = qh->td_last;
++00498         inc = qh->interval;
++00499         n_desc = 0;
++00500 
++00501         ntd_max = (max_desc_num(qh) + qh->interval - 1) / qh->interval;
++00502         if (skip_frames && !qh->channel)
++00503                 ntd_max = ntd_max - skip_frames / qh->interval;
++00504 
++00505         max_xfer_size =
++00506             (qh->dev_speed ==
++00507              DWC_OTG_EP_SPEED_HIGH) ? MAX_ISOC_XFER_SIZE_HS :
++00508             MAX_ISOC_XFER_SIZE_FS;
++00509 
++00510         DWC_CIRCLEQ_FOREACH(qtd, &qh->qtd_list, qtd_list_entry) {
++00511                 while ((qh->ntd < ntd_max)
++00512                        && (qtd->isoc_frame_index_last <
++00513                            qtd->urb->packet_count)) {
++00514 
++00515                         dma_desc = &qh->desc_list[idx];
++00516                         dwc_memset(dma_desc, 0x00, sizeof(dwc_otg_host_dma_desc_t));
++00517 
++00518                         frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index_last];
++00519 
++00520                         if (frame_desc->length > max_xfer_size)
++00521                                 qh->n_bytes[idx] = max_xfer_size;
++00522                         else
++00523                                 qh->n_bytes[idx] = frame_desc->length;
++00524                         dma_desc->status.b_isoc.n_bytes = qh->n_bytes[idx];
++00525                         dma_desc->status.b_isoc.a = 1;
++00526                         dma_desc->status.b_isoc.sts = 0;
++00527 
++00528                         dma_desc->buf = qtd->urb->dma + frame_desc->offset;
++00529 
++00530                         qh->ntd++;
++00531 
++00532                         qtd->isoc_frame_index_last++;
++00533 
++00534 #ifdef  ISOC_URB_GIVEBACK_ASAP
++00535                         /* 
++00536                          * Set IOC for each descriptor corresponding to the 
++00537                          * last frame of the URB.
++00538                          */
++00539                         if (qtd->isoc_frame_index_last ==
++00540                             qtd->urb->packet_count)
++00541                                 dma_desc->status.b_isoc.ioc = 1;
++00542 
++00543 #endif
++00544                         idx = desclist_idx_inc(idx, inc, qh->dev_speed);
++00545                         n_desc++;
++00546 
++00547                 }
++00548                 qtd->in_process = 1;
++00549         }
++00550 
++00551         qh->td_last = idx;
++00552 
++00553 #ifdef  ISOC_URB_GIVEBACK_ASAP
++00554         /* Set IOC for the last descriptor if descriptor list is full */
++00555         if (qh->ntd == ntd_max) {
++00556                 idx = desclist_idx_dec(qh->td_last, inc, qh->dev_speed);
++00557                 qh->desc_list[idx].status.b_isoc.ioc = 1;
++00558         }
++00559 #else
++00560         /* 
++00561          * Set IOC bit only for one descriptor. 
++00562          * Always try to be ahead of HW processing,
++00563          * i.e. on IOC generation driver activates next descriptors but
++00564          * core continues to process descriptors followed the one with IOC set.
++00565          */
++00566 
++00567         if (n_desc > DESCNUM_THRESHOLD) {
++00568                 /* 
++00569                  * Move IOC "up". Required even if there is only one QTD 
++00570                  * in the list, cause QTDs migth continue to be queued,
++00571                  * but during the activation it was only one queued.
++00572                  * Actually more than one QTD might be in the list if this function called 
++00573                  * from XferCompletion - QTDs was queued during HW processing of the previous
++00574                  * descriptor chunk.
++00575                  */
++00576                 idx = dwc_desclist_idx_dec(idx, inc * ((qh->ntd + 1) / 2), qh->dev_speed);
++00577         } else {
++00578                 /* 
++00579                  * Set the IOC for the latest descriptor
++00580                  * if either number of descriptor is not greather than threshold
++00581                  * or no more new descriptors activated.
++00582                  */
++00583                 idx = dwc_desclist_idx_dec(qh->td_last, inc, qh->dev_speed);
++00584         }
++00585 
++00586         qh->desc_list[idx].status.b_isoc.ioc = 1;
++00587 #endif
++00588 }
++00589 
++00590 static void init_non_isoc_dma_desc(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
++00591 {
++00592 
++00593         dwc_hc_t *hc;
++00594         dwc_otg_host_dma_desc_t *dma_desc;
++00595         dwc_otg_qtd_t *qtd;
++00596         int num_packets, len, n_desc = 0;
++00597 
++00598         hc = qh->channel;
++00599 
++00600         /* 
++00601          * Start with hc->xfer_buff initialized in 
++00602          * assign_and_init_hc(), then if SG transfer consists of multiple URBs,
++00603          * this pointer re-assigned to the buffer of the currently processed QTD.
++00604          * For non-SG request there is always one QTD active.
++00605          */
++00606 
++00607         DWC_CIRCLEQ_FOREACH(qtd, &qh->qtd_list, qtd_list_entry) {
++00608 
++00609                 if (n_desc) {
++00610                         /* SG request - more than 1 QTDs */
++00611                         hc->xfer_buff = (uint8_t *)qtd->urb->dma + qtd->urb->actual_length;
++00612                         hc->xfer_len = qtd->urb->length - qtd->urb->actual_length;
++00613                 }
++00614 
++00615                 qtd->n_desc = 0;
++00616 
++00617                 do {
++00618                         dma_desc = &qh->desc_list[n_desc];
++00619                         len = hc->xfer_len;
++00620 
++00621                         if (len > MAX_DMA_DESC_SIZE)
++00622                                 len = MAX_DMA_DESC_SIZE - hc->max_packet + 1;
++00623 
++00624                         if (hc->ep_is_in) {
++00625                                 if (len > 0) {
++00626                                         num_packets = (len + hc->max_packet - 1) / hc->max_packet;
++00627                                 } else {
++00628                                         /* Need 1 packet for transfer length of 0. */
++00629                                         num_packets = 1;
++00630                                 }
++00631                                 /* Always program an integral # of max packets for IN transfers. */
++00632                                 len = num_packets * hc->max_packet;
++00633                         }
++00634 
++00635                         dma_desc->status.b.n_bytes = len;
++00636 
++00637                         qh->n_bytes[n_desc] = len;
++00638 
++00639                         if ((qh->ep_type == UE_CONTROL)
++00640                             && (qtd->control_phase == DWC_OTG_CONTROL_SETUP))
++00641                                 dma_desc->status.b.sup = 1;     /* Setup Packet */
++00642 
++00643                         dma_desc->status.b.a = 1;       /* Active descriptor */
++00644                         dma_desc->status.b.sts = 0;
++00645 
++00646                         dma_desc->buf =
++00647                             ((unsigned long)hc->xfer_buff & 0xffffffff);
++00648 
++00649                         /* 
++00650                          * Last descriptor(or single) of IN transfer 
++00651                          * with actual size less than MaxPacket.
++00652                          */
++00653                         if (len > hc->xfer_len) {
++00654                                 hc->xfer_len = 0;
++00655                         } else {
++00656                                 hc->xfer_buff += len;
++00657                                 hc->xfer_len -= len;
++00658                         }
++00659 
++00660                         qtd->n_desc++;
++00661                         n_desc++;
++00662                 }
++00663                 while ((hc->xfer_len > 0) && (n_desc != MAX_DMA_DESC_NUM_GENERIC));
++00664                 
++00665 
++00666                 qtd->in_process = 1;
++00667 
++00668                 if (qh->ep_type == UE_CONTROL)
++00669                         break;
++00670 
++00671                 if (n_desc == MAX_DMA_DESC_NUM_GENERIC)
++00672                         break;
++00673         }
++00674 
++00675         if (n_desc) {
++00676                 /* Request Transfer Complete interrupt for the last descriptor */
++00677                 qh->desc_list[n_desc - 1].status.b.ioc = 1;
++00678                 /* End of List indicator */
++00679                 qh->desc_list[n_desc - 1].status.b.eol = 1;
++00680 
++00681                 hc->ntd = n_desc;
++00682         }
++00683 }
++00684 
++00702 void dwc_otg_hcd_start_xfer_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
++00703 {
++00704         /* Channel is already assigned */
++00705         dwc_hc_t *hc = qh->channel;
++00706         uint8_t skip_frames = 0;
++00707 
++00708         switch (hc->ep_type) {
++00709         case DWC_OTG_EP_TYPE_CONTROL:
++00710         case DWC_OTG_EP_TYPE_BULK:
++00711                 init_non_isoc_dma_desc(hcd, qh);
++00712 
++00713                 dwc_otg_hc_start_transfer_ddma(hcd->core_if, hc);
++00714                 break;
++00715         case DWC_OTG_EP_TYPE_INTR:
++00716                 init_non_isoc_dma_desc(hcd, qh);
++00717 
++00718                 update_frame_list(hcd, qh, 1);
++00719 
++00720                 dwc_otg_hc_start_transfer_ddma(hcd->core_if, hc);
++00721                 break;
++00722         case DWC_OTG_EP_TYPE_ISOC:
++00723 
++00724                 if (!qh->ntd)
++00725                         skip_frames = recalc_initial_desc_idx(hcd, qh);
++00726 
++00727                 init_isoc_dma_desc(hcd, qh, skip_frames);
++00728 
++00729                 if (!hc->xfer_started) {
++00730 
++00731                         update_frame_list(hcd, qh, 1);
++00732 
++00733                         /* 
++00734                          * Always set to max, instead of actual size.
++00735                          * Otherwise ntd will be changed with 
++00736                          * channel being enabled. Not recommended.
++00737                          *
++00738                          */
++00739                         hc->ntd = max_desc_num(qh);
++00740                         /* Enable channel only once for ISOC */
++00741                         dwc_otg_hc_start_transfer_ddma(hcd->core_if, hc);
++00742                 }
++00743 
++00744                 break;
++00745         default:
++00746 
++00747                 break;
++00748         }
++00749 }
++00750 
++00751 static void complete_isoc_xfer_ddma(dwc_otg_hcd_t * hcd,
++00752                                     dwc_hc_t * hc,
++00753                                     dwc_otg_hc_regs_t * hc_regs,
++00754                                     dwc_otg_halt_status_e halt_status)
++00755 {
++00756         struct dwc_otg_hcd_iso_packet_desc *frame_desc;
++00757         dwc_otg_qtd_t *qtd, *qtd_tmp;
++00758         dwc_otg_qh_t *qh;
++00759         dwc_otg_host_dma_desc_t *dma_desc;
++00760         uint16_t idx, remain;
++00761         uint8_t urb_compl;
++00762 
++00763         qh = hc->qh;
++00764         idx = qh->td_first;
++00765 
++00766         if (hc->halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE) {
++00767                 DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp, &hc->qh->qtd_list, qtd_list_entry)
++00768                     qtd->in_process = 0;
++00769                 return;
++00770         } else if ((halt_status == DWC_OTG_HC_XFER_AHB_ERR) ||
++00771                    (halt_status == DWC_OTG_HC_XFER_BABBLE_ERR)) {
++00772                 /* 
++00773                  * Channel is halted in these error cases.
++00774                  * Considered as serious issues.
++00775                  * Complete all URBs marking all frames as failed, 
++00776                  * irrespective whether some of the descriptors(frames) succeeded or no.
++00777                  * Pass error code to completion routine as well, to
++00778                  * update urb->status, some of class drivers might use it to stop
++00779                  * queing transfer requests.
++00780                  */
++00781                 int err = (halt_status == DWC_OTG_HC_XFER_AHB_ERR)
++00782                     ? (-DWC_E_IO)
++00783                     : (-DWC_E_OVERFLOW);
++00784                                                 
++00785                 DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp, &hc->qh->qtd_list, qtd_list_entry) {
++00786                         for (idx = 0; idx < qtd->urb->packet_count; idx++) {
++00787                                 frame_desc = &qtd->urb->iso_descs[idx];
++00788                                 frame_desc->status = err;
++00789                         }
++00790                         hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, err);
++00791                         dwc_otg_hcd_qtd_remove_and_free(hcd, qtd, qh);
++00792                 }
++00793                 return;
++00794         }
++00795 
++00796         DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp, &hc->qh->qtd_list, qtd_list_entry) {
++00797 
++00798                 if (!qtd->in_process)
++00799                         break;
++00800 
++00801                 urb_compl = 0;
++00802 
++00803                 do {
++00804 
++00805                         dma_desc = &qh->desc_list[idx];
++00806                         
++00807                         frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index];
++00808                         remain = hc->ep_is_in ? dma_desc->status.b_isoc.n_bytes : 0;
++00809 
++00810                         if (dma_desc->status.b_isoc.sts == DMA_DESC_STS_PKTERR) {
++00811                                 /* 
++00812                                  * XactError or, unable to complete all the transactions 
++00813                                  * in the scheduled micro-frame/frame, 
++00814                                  * both indicated by DMA_DESC_STS_PKTERR.
++00815                                  */
++00816                                 qtd->urb->error_count++;
++00817                                 frame_desc->actual_length = qh->n_bytes[idx] - remain;
++00818                                 frame_desc->status = -DWC_E_PROTOCOL;
++00819                         } else {
++00820                                 /* Success */
++00821                                                                 
++00822                                 frame_desc->actual_length = qh->n_bytes[idx] - remain;
++00823                                 frame_desc->status = 0;
++00824                         }
++00825 
++00826                         if (++qtd->isoc_frame_index == qtd->urb->packet_count) {
++00827                                 /*
++00828                                  * urb->status is not used for isoc transfers here.
++00829                                  * The individual frame_desc status are used instead.
++00830                                  */
++00831 
++00832                                 hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, 0);
++00833                                 dwc_otg_hcd_qtd_remove_and_free(hcd, qtd, qh);
++00834 
++00835                                 /* 
++00836                                  * This check is necessary because urb_dequeue can be called 
++00837                                  * from urb complete callback(sound driver example).
++00838                                  * All pending URBs are dequeued there, so no need for
++00839                                  * further processing.
++00840                                  */
++00841                                 if (hc->halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE) {   
++00842                                         return;
++00843                                 }
++00844 
++00845                                 urb_compl = 1;
++00846 
++00847                         }
++00848 
++00849                         qh->ntd--;
++00850 
++00851                         /* Stop if IOC requested descriptor reached */
++00852                         if (dma_desc->status.b_isoc.ioc) {
++00853                                 idx = desclist_idx_inc(idx, qh->interval, hc->speed);   
++00854                                 goto stop_scan;
++00855                         }
++00856 
++00857                         idx = desclist_idx_inc(idx, qh->interval, hc->speed);
++00858 
++00859                         if (urb_compl)
++00860                                 break;
++00861                 }
++00862                 while (idx != qh->td_first);
++00863         }
++00864 stop_scan:
++00865         qh->td_first = idx;
++00866 }
++00867 
++00868 uint8_t update_non_isoc_urb_state_ddma(dwc_otg_hcd_t * hcd,
++00869                                        dwc_hc_t * hc,
++00870                                        dwc_otg_qtd_t * qtd,
++00871                                        dwc_otg_host_dma_desc_t * dma_desc,
++00872                                        dwc_otg_halt_status_e halt_status,
++00873                                        uint32_t n_bytes, uint8_t * xfer_done)
++00874 {
++00875 
++00876         uint16_t remain = hc->ep_is_in ? dma_desc->status.b.n_bytes : 0;
++00877         dwc_otg_hcd_urb_t *urb = qtd->urb;
++00878 
++00879         if (halt_status == DWC_OTG_HC_XFER_AHB_ERR) {
++00880                 urb->status = -DWC_E_IO;
++00881                 return 1;
++00882         }
++00883         if (dma_desc->status.b.sts == DMA_DESC_STS_PKTERR) {
++00884                 switch (halt_status) {
++00885                 case DWC_OTG_HC_XFER_STALL:
++00886                         urb->status = -DWC_E_PIPE;
++00887                         break;
++00888                 case DWC_OTG_HC_XFER_BABBLE_ERR:
++00889                         urb->status = -DWC_E_OVERFLOW;
++00890                         break;
++00891                 case DWC_OTG_HC_XFER_XACT_ERR:
++00892                         urb->status = -DWC_E_PROTOCOL;
++00893                         break;
++00894                 default:        
++00895                         DWC_ERROR("%s: Unhandled descriptor error status (%d)\n", __func__,
++00896                                   halt_status);
++00897                         break;
++00898                 }
++00899                 return 1;
++00900         }
++00901 
++00902         if (dma_desc->status.b.a == 1) {
++00903                 DWC_DEBUGPL(DBG_HCDV,
++00904                             "Active descriptor encountered on channel %d\n",
++00905                             hc->hc_num);
++00906                 return 0;
++00907         }
++00908 
++00909         if (hc->ep_type == DWC_OTG_EP_TYPE_CONTROL) {
++00910                 if (qtd->control_phase == DWC_OTG_CONTROL_DATA) {
++00911                         urb->actual_length += n_bytes - remain;
++00912                         if (remain || urb->actual_length == urb->length) {
++00913                                 /* 
++00914                                  * For Control Data stage do not set urb->status=0 to prevent
++00915                                  * URB callback. Set it when Status phase done. See below.
++00916                                  */
++00917                                 *xfer_done = 1;
++00918                         }
++00919 
++00920                 } else if (qtd->control_phase == DWC_OTG_CONTROL_STATUS) {
++00921                         urb->status = 0;
++00922                         *xfer_done = 1;
++00923                 }
++00924                 /* No handling for SETUP stage */
++00925         } else {
++00926                 /* BULK and INTR */
++00927                 urb->actual_length += n_bytes - remain;
++00928                 if (remain || urb->actual_length == urb->length) {
++00929                         urb->status = 0;
++00930                         *xfer_done = 1;
++00931                 }
++00932         }
++00933 
++00934         return 0;
++00935 }
++00936 
++00937 static void complete_non_isoc_xfer_ddma(dwc_otg_hcd_t * hcd,
++00938                                         dwc_hc_t * hc,
++00939                                         dwc_otg_hc_regs_t * hc_regs,
++00940                                         dwc_otg_halt_status_e halt_status)
++00941 {
++00942         dwc_otg_hcd_urb_t *urb = NULL;
++00943         dwc_otg_qtd_t *qtd, *qtd_tmp;
++00944         dwc_otg_qh_t *qh;
++00945         dwc_otg_host_dma_desc_t *dma_desc;
++00946         uint32_t n_bytes, n_desc, i;
++00947         uint8_t failed = 0, xfer_done;
++00948 
++00949         n_desc = 0;
++00950 
++00951         qh = hc->qh;
++00952 
++00953         if (hc->halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE) {
++00954                 DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp, &hc->qh->qtd_list, qtd_list_entry) {
++00955                         qtd->in_process = 0;
++00956                 }
++00957                 return;
++00958         }
++00959 
++00960         DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp, &qh->qtd_list, qtd_list_entry) {
++00961 
++00962                 urb = qtd->urb;
++00963 
++00964                 n_bytes = 0;
++00965                 xfer_done = 0;
++00966 
++00967                 for (i = 0; i < qtd->n_desc; i++) {
++00968                         dma_desc = &qh->desc_list[n_desc];
++00969 
++00970                         n_bytes = qh->n_bytes[n_desc];
++00971 
++00972                         failed =
++00973                             update_non_isoc_urb_state_ddma(hcd, hc, qtd,
++00974                                                            dma_desc,
++00975                                                            halt_status, n_bytes,
++00976                                                            &xfer_done);
++00977 
++00978                         if (failed
++00979                             || (xfer_done
++00980                                 && (urb->status != -DWC_E_IN_PROGRESS))) {
++00981 
++00982                                 hcd->fops->complete(hcd, urb->priv, urb,
++00983                                                     urb->status);
++00984                                 dwc_otg_hcd_qtd_remove_and_free(hcd, qtd, qh);
++00985 
++00986                                 if (failed)
++00987                                         goto stop_scan;
++00988                         } else if (qh->ep_type == UE_CONTROL) {
++00989                                 if (qtd->control_phase == DWC_OTG_CONTROL_SETUP) {
++00990                                         if (urb->length > 0) {
++00991                                                 qtd->control_phase = DWC_OTG_CONTROL_DATA;
++00992                                         } else {
++00993                                                 qtd->control_phase = DWC_OTG_CONTROL_STATUS;
++00994                                         }
++00995                                         DWC_DEBUGPL(DBG_HCDV, "  Control setup transaction done\n");
++00996                                 } else if (qtd->control_phase == DWC_OTG_CONTROL_DATA) {
++00997                                         if (xfer_done) {
++00998                                                 qtd->control_phase = DWC_OTG_CONTROL_STATUS;
++00999                                                 DWC_DEBUGPL(DBG_HCDV, "  Control data transfer done\n");
++01000                                         } else if (i + 1 == qtd->n_desc) {
++01001                                                 /* 
++01002                                                  * Last descriptor for Control data stage which is
++01003                                                  * not completed yet.
++01004                                                  */
++01005                                                 dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
++01006                                         }
++01007                                 }
++01008                         }
++01009 
++01010                         n_desc++;
++01011                 }
++01012 
++01013         }
++01014 
++01015 stop_scan:
++01016 
++01017         if (qh->ep_type != UE_CONTROL) {
++01018                 /* 
++01019                  * Resetting the data toggle for bulk
++01020                  * and interrupt endpoints in case of stall. See handle_hc_stall_intr() 
++01021                  */
++01022                 if (halt_status == DWC_OTG_HC_XFER_STALL)
++01023                         qh->data_toggle = DWC_OTG_HC_PID_DATA0;
++01024                 else
++01025                         dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
++01026         }
++01027 
++01028         if (halt_status == DWC_OTG_HC_XFER_COMPLETE) {
++01029                 hcint_data_t hcint;
++01030                 hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
++01031                 if (hcint.b.nyet) {
++01032                         /*
++01033                          * Got a NYET on the last transaction of the transfer. It
++01034                          * means that the endpoint should be in the PING state at the
++01035                          * beginning of the next transfer.
++01036                          */
++01037                         qh->ping_state = 1;
++01038                         clear_hc_int(hc_regs, nyet);
++01039                 }
++01040 
++01041         }
++01042 
++01043 }
++01044 
++01062 void dwc_otg_hcd_complete_xfer_ddma(dwc_otg_hcd_t * hcd,
++01063                                     dwc_hc_t * hc,
++01064                                     dwc_otg_hc_regs_t * hc_regs,
++01065                                     dwc_otg_halt_status_e halt_status)
++01066 {
++01067         uint8_t continue_isoc_xfer = 0;
++01068         dwc_otg_transaction_type_e tr_type;
++01069         dwc_otg_qh_t *qh = hc->qh;
++01070 
++01071         if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
++01072 
++01073                 complete_isoc_xfer_ddma(hcd, hc, hc_regs, halt_status);
++01074 
++01075                 /* Release the channel if halted or session completed */
++01076                 if (halt_status != DWC_OTG_HC_XFER_COMPLETE ||
++01077                     DWC_CIRCLEQ_EMPTY(&qh->qtd_list)) {
++01078 
++01079                         /* Halt the channel if session completed */
++01080                         if (halt_status == DWC_OTG_HC_XFER_COMPLETE) {
++01081                                 dwc_otg_hc_halt(hcd->core_if, hc, halt_status);
++01082                         }
++01083 
++01084                         release_channel_ddma(hcd, qh);
++01085                         dwc_otg_hcd_qh_remove(hcd, qh);
++01086                 } else {
++01087                         /* Keep in assigned schedule to continue transfer */
++01088                         DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_assigned,
++01089                                            &qh->qh_list_entry);
++01090                         continue_isoc_xfer = 1;
++01091 
++01092                 }
++01096         } else {
++01097                 /* Scan descriptor list to complete the URB(s), then release the channel */
++01098                 complete_non_isoc_xfer_ddma(hcd, hc, hc_regs, halt_status);
++01099 
++01100                 release_channel_ddma(hcd, qh);
++01101                 dwc_otg_hcd_qh_remove(hcd, qh);
++01102 
++01103                 if (!DWC_CIRCLEQ_EMPTY(&qh->qtd_list)) {
++01104                         /* Add back to inactive non-periodic schedule on normal completion */
++01105                         dwc_otg_hcd_qh_add(hcd, qh);
++01106                 }
++01107 
++01108         }
++01109         tr_type = dwc_otg_hcd_select_transactions(hcd);
++01110         if (tr_type != DWC_OTG_TRANSACTION_NONE || continue_isoc_xfer) {
++01111                 if (continue_isoc_xfer) {
++01112                         if (tr_type == DWC_OTG_TRANSACTION_NONE) {
++01113                                 tr_type = DWC_OTG_TRANSACTION_PERIODIC;
++01114                         } else if (tr_type == DWC_OTG_TRANSACTION_NON_PERIODIC) {
++01115                                 tr_type = DWC_OTG_TRANSACTION_ALL;
++01116                         }
++01117                 }
++01118                 dwc_otg_hcd_queue_transactions(hcd, tr_type);
++01119         }
++01120 }
++01121 
++01122 #endif /* DWC_DEVICE_ONLY */
++
    Generated on Thu Oct 27 03:56:37 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
    ++doxygen 1.3.9.1
    + + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__hcd__ddma_8c.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/dwc__otg__hcd__ddma_8c.html 2013-07-26 19:31:21.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__hcd__ddma_8c.html 2013-07-26 19:34:41.000000000 +0000 +@@ -2,121 +2,109 @@ + + DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_hcd_ddma.c File Reference + +- + +- +-
    +-
    +-
    +-
    ++ ++
    Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
    +

    dwc_otg_hcd_ddma.c File Reference

    This file contains Descriptor DMA support implementation for host mode. More... +

    +-#include "dwc_otg_hcd.h"
    +-#include "dwc_otg_regs.h"
    ++#include "dwc_otg_hcd.h"
    ++#include "dwc_otg_regs.h"
    + +

    + Go to the source code of this file. + + +- ++ + +- ++ + +- ++ + +- ++ + + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- +- ++ ++ + +- +- ++ ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- +- ++ ++ + +- ++ + +- ++ + +- ++ + +- ++ +

    Defines

    +-#define ISOC_URB_GIVEBACK_ASAP
    ++#define ISOC_URB_GIVEBACK_ASAP
    +-#define MAX_ISOC_XFER_SIZE_FS   1023
    ++#define MAX_ISOC_XFER_SIZE_FS   1023
    +-#define MAX_ISOC_XFER_SIZE_HS   3072
    ++#define MAX_ISOC_XFER_SIZE_HS   3072
    +-#define DESCNUM_THRESHOLD   4
    ++#define DESCNUM_THRESHOLD   4

    Functions

    +-static uint8_t frame_list_idx (uint16_t frame)
    ++uint8_t frame_list_idx (uint16_t frame)
    +-static uint16_t desclist_idx_inc (uint16_t idx, uint16_t inc, uint8_t speed)
    ++uint16_t desclist_idx_inc (uint16_t idx, uint16_t inc, uint8_t speed)
    +-static uint16_t desclist_idx_dec (uint16_t idx, uint16_t inc, uint8_t speed)
    ++uint16_t desclist_idx_dec (uint16_t idx, uint16_t inc, uint8_t speed)
    +-static uint16_t max_desc_num (dwc_otg_qh_t *qh)
    ++uint16_t max_desc_num (dwc_otg_qh_t *qh)
    +-static uint16_t frame_incr_val (dwc_otg_qh_t *qh)
    ++uint16_t frame_incr_val (dwc_otg_qh_t *qh)
    +-static int desc_list_alloc (dwc_otg_qh_t *qh)
    ++int desc_list_alloc (dwc_otg_qh_t *qh)
    +-static void desc_list_free (dwc_otg_qh_t *qh)
    ++void desc_list_free (dwc_otg_qh_t *qh)
    +-static int frame_list_alloc (dwc_otg_hcd_t *hcd)
    ++int frame_list_alloc (dwc_otg_hcd_t *hcd)
    +-static void frame_list_free (dwc_otg_hcd_t *hcd)
    ++void frame_list_free (dwc_otg_hcd_t *hcd)
    +-static void per_sched_enable (dwc_otg_hcd_t *hcd, uint16_t fr_list_en)
    ++void per_sched_enable (dwc_otg_hcd_t *hcd, uint16_t fr_list_en)
    +-static void per_sched_disable (dwc_otg_hcd_t *hcd)
    ++void per_sched_disable (dwc_otg_hcd_t *hcd)
    +-void update_frame_list (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh, uint8_t enable)
    ++void update_frame_list (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh, uint8_t enable)
    +-void dump_frame_list (dwc_otg_hcd_t *hcd)
    ++void dump_frame_list (dwc_otg_hcd_t *hcd)
    +-static void release_channel_ddma (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
    ++void release_channel_ddma (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
    int dwc_otg_hcd_qh_init_ddma (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
    int dwc_otg_hcd_qh_init_ddma (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
     Initializes a QH structure's Descriptor DMA related members.
    void dwc_otg_hcd_qh_free_ddma (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
     Initializes a QH structure's Descriptor DMA related members.
    void dwc_otg_hcd_qh_free_ddma (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
     Frees descriptor list memory associated with the QH.
    +-static uint8_t frame_to_desc_idx (dwc_otg_qh_t *qh, uint16_t frame_idx)
     Frees descriptor list memory associated with the QH.
    ++uint8_t frame_to_desc_idx (dwc_otg_qh_t *qh, uint16_t frame_idx)
    +-static uint8_t calc_starting_frame (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh, uint8_t *skip_frames)
    ++uint8_t calc_starting_frame (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh, uint8_t *skip_frames)
    +-static uint8_t recalc_initial_desc_idx (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
    ++uint8_t recalc_initial_desc_idx (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
    +-static void init_isoc_dma_desc (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh, uint8_t skip_frames)
    ++void init_isoc_dma_desc (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh, uint8_t skip_frames)
    +-static void init_non_isoc_dma_desc (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
    ++void init_non_isoc_dma_desc (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
    void dwc_otg_hcd_start_xfer_ddma (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
    void dwc_otg_hcd_start_xfer_ddma (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
     For Control and Bulk endpoints initializes descriptor list and starts the transfer.
    +-static void complete_isoc_xfer_ddma (dwc_otg_hcd_t *hcd, dwc_hc_t *hc, dwc_otg_hc_regs_t *hc_regs, dwc_otg_halt_status_e halt_status)
     For Control and Bulk endpoints initializes descriptor list and starts the transfer.
    ++void complete_isoc_xfer_ddma (dwc_otg_hcd_t *hcd, dwc_hc_t *hc, dwc_otg_hc_regs_t *hc_regs, dwc_otg_halt_status_e halt_status)
    +-uint8_t update_non_isoc_urb_state_ddma (dwc_otg_hcd_t *hcd, dwc_hc_t *hc, dwc_otg_qtd_t *qtd, dwc_otg_host_dma_desc_t *dma_desc, dwc_otg_halt_status_e halt_status, uint32_t n_bytes, uint8_t *xfer_done)
    ++uint8_t update_non_isoc_urb_state_ddma (dwc_otg_hcd_t *hcd, dwc_hc_t *hc, dwc_otg_qtd_t *qtd, dwc_otg_host_dma_desc_t *dma_desc, dwc_otg_halt_status_e halt_status, uint32_t n_bytes, uint8_t *xfer_done)
    +-static void complete_non_isoc_xfer_ddma (dwc_otg_hcd_t *hcd, dwc_hc_t *hc, dwc_otg_hc_regs_t *hc_regs, dwc_otg_halt_status_e halt_status)
    ++void complete_non_isoc_xfer_ddma (dwc_otg_hcd_t *hcd, dwc_hc_t *hc, dwc_otg_hc_regs_t *hc_regs, dwc_otg_halt_status_e halt_status)
    void dwc_otg_hcd_complete_xfer_ddma (dwc_otg_hcd_t *hcd, dwc_hc_t *hc, dwc_otg_hc_regs_t *hc_regs, dwc_otg_halt_status_e halt_status)
    void dwc_otg_hcd_complete_xfer_ddma (dwc_otg_hcd_t *hcd, dwc_hc_t *hc, dwc_otg_hc_regs_t *hc_regs, dwc_otg_halt_status_e halt_status)
     This function is called from interrupt handlers.
     This function is called from interrupt handlers.
    +

    Detailed Description

    + This file contains Descriptor DMA support implementation for host mode. +@@ -124,30 +112,38 @@ + +

    + Definition in file dwc_otg_hcd_ddma.c.

    Function Documentation

    +- +-
    +-
    +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- ++

    ++

    int dwc_otg_hcd_qh_init_ddma (dwc_otg_hcd_t *  hcd,
    dwc_otg_qh_t *  qh 
    )
    ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ + +
    int dwc_otg_hcd_qh_init_ddma ( dwc_otg_hcd_t *  hcd,
    dwc_otg_qh_t *  qh
    ) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Initializes a QH structure's Descriptor DMA related members. +@@ -162,33 +158,41 @@ +

    Returns:
    0 if successful, negative error code otherwise.
    + +

    +-Definition at line 294 of file dwc_otg_hcd_ddma.c. +- +-

    +- +-

    +-
    +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- ++Definition at line 312 of file dwc_otg_hcd_ddma.c. ++ ++
    void dwc_otg_hcd_qh_free_ddma (dwc_otg_hcd_t *  hcd,
    dwc_otg_qh_t *  qh 
    )
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ + +
    void dwc_otg_hcd_qh_free_ddma ( dwc_otg_hcd_t *  hcd,
    dwc_otg_qh_t *  qh
    ) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Frees descriptor list memory associated with the QH. +@@ -202,33 +206,41 @@ + + +

    +-Definition at line 327 of file dwc_otg_hcd_ddma.c. +- +-

    +- +-

    +-
    +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- ++Definition at line 346 of file dwc_otg_hcd_ddma.c. ++ ++
    void dwc_otg_hcd_start_xfer_ddma (dwc_otg_hcd_t *  hcd,
    dwc_otg_qh_t *  qh 
    )
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ + +
    void dwc_otg_hcd_start_xfer_ddma ( dwc_otg_hcd_t *  hcd,
    dwc_otg_qh_t *  qh
    ) 
    +- +-
    ++
    ++ ++ ++ ++ ++ ++
    ++   ++ + +

    + For Control and Bulk endpoints initializes descriptor list and starts the transfer. +@@ -243,45 +255,53 @@ +

    Returns:
    0 if successful, negative error code otherwise.
    + +

    +-Definition at line 675 of file dwc_otg_hcd_ddma.c. +- +-

    +- +-

    +-
    +- ++Definition at line 702 of file dwc_otg_hcd_ddma.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    void dwc_otg_hcd_complete_xfer_ddma (dwc_otg_hcd_t *  hcd, void dwc_otg_hcd_complete_xfer_ddma ( dwc_otg_hcd_t *  hcd,
    dwc_hc_t *  hc, dwc_hc_t *  hc,
    dwc_otg_hc_regs_t *  hc_regs, dwc_otg_hc_regs_t *  hc_regs,
    dwc_otg_halt_status_e  halt_status dwc_otg_halt_status_e  halt_status
    )) 
    +- +-
    ++
    ++ ++ ++ ++ + + +- ++ +
    ++   ++ + +

    + This function is called from interrupt handlers. +@@ -293,19 +313,18 @@ +

    hcd The HCD state structure for the DWC OTG controller.
    hc Host channel, the transfer is completed on.
    hc_regs Host channel registers.
    halt_status Reason the channel is being halted, or just XferComplete for isochronous transfer
    halt_status Reason the channel is being halted, or just XferComplete for isochronous transfer
    + +- +

    +-

    Todo:
    Consider the case when period exceeds FrameList size. Frame Rollover interrupt should be used.
    ++
    Todo:
    Consider the case when period exceeds FrameList size. Frame Rollover interrupt should be used.
    + +

    +-Definition at line 1042 of file dwc_otg_hcd_ddma.c. +-

    +-

    +-

    Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++Definition at line 1062 of file dwc_otg_hcd_ddma.c.
    ++

    Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
    ++doxygen 1.3.9.1 + + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__hcd__if_8h-source.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/dwc__otg__hcd__if_8h-source.html 2013-07-26 19:31:21.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__hcd__if_8h-source.html 2013-07-26 19:34:41.000000000 +0000 +@@ -2,190 +2,191 @@ + + DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_hcd_if.h Source File + +- + +- +-
    +-
    +-
    +-
    +-

    dwc_otg_hcd_if.h

    Go to the documentation of this file.
    00001 /* ==========================================================================
+-00002  * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd_if.h $
+-00003  * $Revision: #6 $
+-00004  * $Date: 2009/04/21 $
+-00005  * $Change: 1237474 $
+-00006  *
+-00007  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
+-00008  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
+-00009  * otherwise expressly agreed to in writing between Synopsys and you.
+-00010  *
+-00011  * The Software IS NOT an item of Licensed Software or Licensed Product under
+-00012  * any End User Software License Agreement or Agreement for Licensed Product
+-00013  * with Synopsys or any supplement thereto. You are permitted to use and
+-00014  * redistribute this Software in source and binary forms, with or without
+-00015  * modification, provided that redistributions of source code must retain this
+-00016  * notice. You may not view, use, disclose, copy or distribute this file or
+-00017  * any information contained herein except pursuant to this license grant from
+-00018  * Synopsys. If you do not agree with this notice, including the disclaimer
+-00019  * below, then you are not authorized to use the Software.
+-00020  *
+-00021  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
+-00022  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+-00023  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+-00024  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
+-00025  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+-00026  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+-00027  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+-00028  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+-00029  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+-00030  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+-00031  * DAMAGE.
+-00032  * ========================================================================== */
+-00033 #ifndef DWC_DEVICE_ONLY
+-00034 #ifndef __DWC_HCD_IF_H__
+-00035 #define __DWC_HCD_IF_H__
+-00036 
+-00037 #include "dwc_otg_core_if.h"
+-00038 
+-00043 struct dwc_otg_hcd;
+-00044 typedef struct dwc_otg_hcd dwc_otg_hcd_t;
+-00045 
+-00046 struct dwc_otg_hcd_urb;
+-00047 typedef struct dwc_otg_hcd_urb dwc_otg_hcd_urb_t;
+-00048 
+-00053 typedef int (*dwc_otg_hcd_start_cb_t) (dwc_otg_hcd_t * hcd);
+-00054 
+-00056 typedef int (*dwc_otg_hcd_disconnect_cb_t) (dwc_otg_hcd_t * hcd);
+-00057 
+-00059 typedef int (*dwc_otg_hcd_hub_info_from_urb_cb_t) (dwc_otg_hcd_t * hcd,
+-00060                                                    void *urb_handle,
+-00061                                                    uint32_t * hub_addr,
+-00062                                                    uint32_t * port_addr);
+-00064 typedef int (*dwc_otg_hcd_speed_from_urb_cb_t) (dwc_otg_hcd_t * hcd,
+-00065                                                 void *urb_handle);
+-00066 
+-00068 typedef int (*dwc_otg_hcd_complete_urb_cb_t) (dwc_otg_hcd_t * hcd,
+-00069                                               void *urb_handle,
+-00070                                               dwc_otg_hcd_urb_t * dwc_otg_urb,
+-00071                                               int32_t status);
+-00072 
+-00074 typedef int (*dwc_otg_hcd_get_b_hnp_enable) (dwc_otg_hcd_t * hcd);
+-00075 
+-00076 struct dwc_otg_hcd_function_ops {
+-00077         dwc_otg_hcd_start_cb_t start;
+-00078         dwc_otg_hcd_disconnect_cb_t disconnect;
+-00079         dwc_otg_hcd_hub_info_from_urb_cb_t hub_info;
+-00080         dwc_otg_hcd_speed_from_urb_cb_t speed;
+-00081         dwc_otg_hcd_complete_urb_cb_t complete;
+-00082         dwc_otg_hcd_get_b_hnp_enable get_b_hnp_enable;
+-00083 };
+-00089 extern dwc_otg_hcd_t *dwc_otg_hcd_alloc_hcd(void);
+-00090 
+-00099 extern int dwc_otg_hcd_init(dwc_otg_hcd_t * hcd, dwc_otg_core_if_t * core_if);
+-00100 
+-00105 extern void dwc_otg_hcd_remove(dwc_otg_hcd_t * hcd);
+-00106 
+-00114 extern int32_t dwc_otg_hcd_handle_intr(dwc_otg_hcd_t * dwc_otg_hcd);
+-00115 
+-00122 extern void *dwc_otg_hcd_get_priv_data(dwc_otg_hcd_t * hcd);
+-00123 
+-00130 extern void dwc_otg_hcd_set_priv_data(dwc_otg_hcd_t * hcd, void *priv_data);
+-00131 
+-00141 extern int dwc_otg_hcd_start(dwc_otg_hcd_t * hcd,
+-00142                              struct dwc_otg_hcd_function_ops *fops);
+-00143 
+-00150 extern void dwc_otg_hcd_stop(dwc_otg_hcd_t * hcd);
+-00151 
+-00165 extern int dwc_otg_hcd_hub_control(dwc_otg_hcd_t * dwc_otg_hcd,
+-00166                                    uint16_t typeReq, uint16_t wValue,
+-00167                                    uint16_t wIndex, uint8_t * buf,
+-00168                                    uint16_t wLength);
+-00169 
+-00175 extern uint32_t dwc_otg_hcd_otg_port(dwc_otg_hcd_t * hcd);
+-00176 
+-00182 extern uint32_t dwc_otg_hcd_is_b_host(dwc_otg_hcd_t * hcd);
+-00183 
+-00189 extern int dwc_otg_hcd_get_frame_number(dwc_otg_hcd_t * hcd);
+-00190 
+-00196 extern void dwc_otg_hcd_dump_state(dwc_otg_hcd_t * hcd);
+-00197 
+-00206 extern void dwc_otg_hcd_dump_frrem(dwc_otg_hcd_t * hcd);
+-00207 
+-00219 extern int dwc_otg_hcd_send_lpm(dwc_otg_hcd_t * hcd, uint8_t devaddr,
+-00220                                 uint8_t hird, uint8_t bRemoteWake);
+-00221 
+-00222 /* URB interface */
+-00223 
+-00232 extern dwc_otg_hcd_urb_t *dwc_otg_hcd_urb_alloc(dwc_otg_hcd_t * hcd,
+-00233                                                 int iso_desc_count,
+-00234                                                 int atomic_alloc);
+-00235 
+-00246 extern void dwc_otg_hcd_urb_set_pipeinfo(dwc_otg_hcd_urb_t * hcd_urb,
+-00247                                          uint8_t devaddr, uint8_t ep_num,
+-00248                                          uint8_t ep_type, uint8_t ep_dir,
+-00249                                          uint16_t mps);
+-00250 
+-00251 /* Transfer flags */ 
+-00252 #define URB_GIVEBACK_ASAP 0x1
+-00253 #define URB_SEND_ZERO_PACKET 0x2
+-00254 
+-00269 extern void dwc_otg_hcd_urb_set_params(dwc_otg_hcd_urb_t * urb,
+-00270                                        void *urb_handle, void *buf,
+-00271                                        dwc_dma_t dma, uint32_t buflen, void *sp,
+-00272                                        dwc_dma_t sp_dma, uint32_t flags,
+-00273                                        uint16_t interval);
+-00274 
+-00279 extern uint32_t dwc_otg_hcd_urb_get_status(dwc_otg_hcd_urb_t * dwc_otg_urb);
+-00280 
+-00285 extern uint32_t dwc_otg_hcd_urb_get_actual_length(dwc_otg_hcd_urb_t *
+-00286                                                   dwc_otg_urb);
+-00287 
+-00292 extern uint32_t dwc_otg_hcd_urb_get_error_count(dwc_otg_hcd_urb_t *
+-00293                                                 dwc_otg_urb);
+-00294 
+-00302 extern void dwc_otg_hcd_urb_set_iso_desc_params(dwc_otg_hcd_urb_t * dwc_otg_urb,
+-00303                                                 int desc_num, uint32_t offset,
+-00304                                                 uint32_t length);
+-00305 
+-00311 extern uint32_t dwc_otg_hcd_urb_get_iso_desc_status(dwc_otg_hcd_urb_t *
+-00312                                                     dwc_otg_urb, int desc_num);
+-00313 
+-00319 extern uint32_t dwc_otg_hcd_urb_get_iso_desc_actual_length(dwc_otg_hcd_urb_t *
+-00320                                                            dwc_otg_urb,
+-00321                                                            int desc_num);
+-00322 
+-00333 extern int dwc_otg_hcd_urb_enqueue(dwc_otg_hcd_t * dwc_otg_hcd,
+-00334                                    dwc_otg_hcd_urb_t * dwc_otg_urb,
+-00335                                    void **ep_handle);
+-00336 
+-00342 extern int dwc_otg_hcd_urb_dequeue(dwc_otg_hcd_t * dwc_otg_hcd,
+-00343                                    dwc_otg_hcd_urb_t * dwc_otg_urb);
+-00344 
+-00355 extern int dwc_otg_hcd_endpoint_disable(dwc_otg_hcd_t * hcd, void *ep_handle,
+-00356                                         int retry);
+-00357 
+-00363 extern int dwc_otg_hcd_is_status_changed(dwc_otg_hcd_t * hcd, int port);
+-00364 
+-00371 extern int dwc_otg_hcd_is_bandwidth_allocated(dwc_otg_hcd_t * hcd,
+-00372                                               void *ep_handle);
+-00373 
+-00379 extern int dwc_otg_hcd_is_bandwidth_freed(dwc_otg_hcd_t * hcd, void *ep_handle);
+-00380 
+-00387 extern uint8_t dwc_otg_hcd_get_ep_bandwidth(dwc_otg_hcd_t * hcd,
+-00388                                             void *ep_handle);
+-00389 
+-00392 #endif                          /* __DWC_HCD_IF_H__ */
+-00393 #endif                          /* DWC_DEVICE_ONLY */
+-
    Generated on Tue May 5 02:22:48 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++
    Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
    ++

    dwc_otg_hcd_if.h

    Go to the documentation of this file.
    00001 /* ==========================================================================
++00002  * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd_if.h $
++00003  * $Revision: #12 $
++00004  * $Date: 2011/10/26 $
++00005  * $Change: 1873028 $
++00006  *
++00007  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
++00008  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
++00009  * otherwise expressly agreed to in writing between Synopsys and you.
++00010  *
++00011  * The Software IS NOT an item of Licensed Software or Licensed Product under
++00012  * any End User Software License Agreement or Agreement for Licensed Product
++00013  * with Synopsys or any supplement thereto. You are permitted to use and
++00014  * redistribute this Software in source and binary forms, with or without
++00015  * modification, provided that redistributions of source code must retain this
++00016  * notice. You may not view, use, disclose, copy or distribute this file or
++00017  * any information contained herein except pursuant to this license grant from
++00018  * Synopsys. If you do not agree with this notice, including the disclaimer
++00019  * below, then you are not authorized to use the Software.
++00020  *
++00021  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
++00022  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++00023  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++00024  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
++00025  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++00026  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
++00027  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
++00028  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
++00029  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
++00030  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
++00031  * DAMAGE.
++00032  * ========================================================================== */
++00033 #ifndef DWC_DEVICE_ONLY
++00034 #ifndef __DWC_HCD_IF_H__
++00035 #define __DWC_HCD_IF_H__
++00036 
++00037 #include "dwc_otg_core_if.h"
++00038 
++00043 struct dwc_otg_hcd;
++00044 typedef struct dwc_otg_hcd dwc_otg_hcd_t;
++00045 
++00046 struct dwc_otg_hcd_urb;
++00047 typedef struct dwc_otg_hcd_urb dwc_otg_hcd_urb_t;
++00048 
++00053 typedef int (*dwc_otg_hcd_start_cb_t) (dwc_otg_hcd_t * hcd);
++00054 
++00056 typedef int (*dwc_otg_hcd_disconnect_cb_t) (dwc_otg_hcd_t * hcd);
++00057 
++00059 typedef int (*dwc_otg_hcd_hub_info_from_urb_cb_t) (dwc_otg_hcd_t * hcd,
++00060                                                    void *urb_handle,
++00061                                                    uint32_t * hub_addr,
++00062                                                    uint32_t * port_addr);
++00064 typedef int (*dwc_otg_hcd_speed_from_urb_cb_t) (dwc_otg_hcd_t * hcd,
++00065                                                 void *urb_handle);
++00066 
++00068 typedef int (*dwc_otg_hcd_complete_urb_cb_t) (dwc_otg_hcd_t * hcd,
++00069                                               void *urb_handle,
++00070                                               dwc_otg_hcd_urb_t * dwc_otg_urb,
++00071                                               int32_t status);
++00072 
++00074 typedef int (*dwc_otg_hcd_get_b_hnp_enable) (dwc_otg_hcd_t * hcd);
++00075 
++00076 struct dwc_otg_hcd_function_ops {
++00077         dwc_otg_hcd_start_cb_t start;
++00078         dwc_otg_hcd_disconnect_cb_t disconnect;
++00079         dwc_otg_hcd_hub_info_from_urb_cb_t hub_info;
++00080         dwc_otg_hcd_speed_from_urb_cb_t speed;
++00081         dwc_otg_hcd_complete_urb_cb_t complete;
++00082         dwc_otg_hcd_get_b_hnp_enable get_b_hnp_enable;
++00083 };
++00089 extern dwc_otg_hcd_t *dwc_otg_hcd_alloc_hcd(void);
++00090 
++00099 extern int dwc_otg_hcd_init(dwc_otg_hcd_t * hcd, dwc_otg_core_if_t * core_if);
++00100 
++00105 extern void dwc_otg_hcd_remove(dwc_otg_hcd_t * hcd);
++00106 
++00114 extern int32_t dwc_otg_hcd_handle_intr(dwc_otg_hcd_t * dwc_otg_hcd);
++00115 
++00122 extern void *dwc_otg_hcd_get_priv_data(dwc_otg_hcd_t * hcd);
++00123 
++00130 extern void dwc_otg_hcd_set_priv_data(dwc_otg_hcd_t * hcd, void *priv_data);
++00131 
++00141 extern int dwc_otg_hcd_start(dwc_otg_hcd_t * hcd,
++00142                              struct dwc_otg_hcd_function_ops *fops);
++00143 
++00150 extern void dwc_otg_hcd_stop(dwc_otg_hcd_t * hcd);
++00151 
++00165 extern int dwc_otg_hcd_hub_control(dwc_otg_hcd_t * dwc_otg_hcd,
++00166                                    uint16_t typeReq, uint16_t wValue,
++00167                                    uint16_t wIndex, uint8_t * buf,
++00168                                    uint16_t wLength);
++00169 
++00175 extern uint32_t dwc_otg_hcd_otg_port(dwc_otg_hcd_t * hcd);
++00176 
++00182 extern uint16_t dwc_otg_get_otg_version(dwc_otg_core_if_t * core_if);
++00183 
++00189 extern uint32_t dwc_otg_hcd_is_b_host(dwc_otg_hcd_t * hcd);
++00190 
++00196 extern int dwc_otg_hcd_get_frame_number(dwc_otg_hcd_t * hcd);
++00197 
++00203 extern void dwc_otg_hcd_dump_state(dwc_otg_hcd_t * hcd);
++00204 
++00213 extern void dwc_otg_hcd_dump_frrem(dwc_otg_hcd_t * hcd);
++00214 
++00226 extern int dwc_otg_hcd_send_lpm(dwc_otg_hcd_t * hcd, uint8_t devaddr,
++00227                                 uint8_t hird, uint8_t bRemoteWake);
++00228 
++00229 /* URB interface */
++00230 
++00239 extern dwc_otg_hcd_urb_t *dwc_otg_hcd_urb_alloc(dwc_otg_hcd_t * hcd,
++00240                                                 int iso_desc_count,
++00241                                                 int atomic_alloc);
++00242 
++00253 extern void dwc_otg_hcd_urb_set_pipeinfo(dwc_otg_hcd_urb_t * hcd_urb,
++00254                                          uint8_t devaddr, uint8_t ep_num,
++00255                                          uint8_t ep_type, uint8_t ep_dir,
++00256                                          uint16_t mps);
++00257 
++00258 /* Transfer flags */
++00259 #define URB_GIVEBACK_ASAP 0x1
++00260 #define URB_SEND_ZERO_PACKET 0x2
++00261 
++00276 extern void dwc_otg_hcd_urb_set_params(dwc_otg_hcd_urb_t * urb,
++00277                                        void *urb_handle, void *buf,
++00278                                        dwc_dma_t dma, uint32_t buflen, void *sp,
++00279                                        dwc_dma_t sp_dma, uint32_t flags,
++00280                                        uint16_t interval);
++00281 
++00286 extern uint32_t dwc_otg_hcd_urb_get_status(dwc_otg_hcd_urb_t * dwc_otg_urb);
++00287 
++00292 extern uint32_t dwc_otg_hcd_urb_get_actual_length(dwc_otg_hcd_urb_t *
++00293                                                   dwc_otg_urb);
++00294 
++00299 extern uint32_t dwc_otg_hcd_urb_get_error_count(dwc_otg_hcd_urb_t *
++00300                                                 dwc_otg_urb);
++00301 
++00309 extern void dwc_otg_hcd_urb_set_iso_desc_params(dwc_otg_hcd_urb_t * dwc_otg_urb,
++00310                                                 int desc_num, uint32_t offset,
++00311                                                 uint32_t length);
++00312 
++00318 extern uint32_t dwc_otg_hcd_urb_get_iso_desc_status(dwc_otg_hcd_urb_t *
++00319                                                     dwc_otg_urb, int desc_num);
++00320 
++00326 extern uint32_t dwc_otg_hcd_urb_get_iso_desc_actual_length(dwc_otg_hcd_urb_t *
++00327                                                            dwc_otg_urb,
++00328                                                            int desc_num);
++00329 
++00341 extern int dwc_otg_hcd_urb_enqueue(dwc_otg_hcd_t * dwc_otg_hcd,
++00342                                    dwc_otg_hcd_urb_t * dwc_otg_urb,
++00343                                    void **ep_handle, int atomic_alloc);
++00344 
++00350 extern int dwc_otg_hcd_urb_dequeue(dwc_otg_hcd_t * dwc_otg_hcd,
++00351                                    dwc_otg_hcd_urb_t * dwc_otg_urb);
++00352 
++00363 extern int dwc_otg_hcd_endpoint_disable(dwc_otg_hcd_t * hcd, void *ep_handle,
++00364                                         int retry);
++00365 
++00366 /* Resets the data toggle in qh structure. This function can be called from
++00367  * usb_clear_halt routine.
++00368  *
++00369  * @param hcd The HCD
++00370  * @param ep_handle Endpoint handle, returned by dwc_otg_hcd_urb_enqueue function
++00371  *
++00372  * Returns -DWC_E_INVALID if invalid arguments are passed.
++00373  * Returns 0 on success
++00374  */
++00375 extern int dwc_otg_hcd_endpoint_reset(dwc_otg_hcd_t * hcd, void *ep_handle);
++00376 
++00382 extern int dwc_otg_hcd_is_status_changed(dwc_otg_hcd_t * hcd, int port);
++00383 
++00390 extern int dwc_otg_hcd_is_bandwidth_allocated(dwc_otg_hcd_t * hcd,
++00391                                               void *ep_handle);
++00392 
++00398 extern int dwc_otg_hcd_is_bandwidth_freed(dwc_otg_hcd_t * hcd, void *ep_handle);
++00399 
++00406 extern uint8_t dwc_otg_hcd_get_ep_bandwidth(dwc_otg_hcd_t * hcd,
++00407                                             void *ep_handle);
++00408 
++00411 #endif /* __DWC_HCD_IF_H__ */
++00412 #endif /* DWC_DEVICE_ONLY */
++
    Generated on Thu Oct 27 03:56:37 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
    ++doxygen 1.3.9.1
    + + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__hcd__if_8h.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/dwc__otg__hcd__if_8h.html 2013-07-26 19:31:21.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__hcd__if_8h.html 2013-07-26 19:34:41.000000000 +0000 +@@ -2,163 +2,157 @@ + + DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_hcd_if.h File Reference + +- + +- +-
    +-
    +-
    +-
    ++ ++
    Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
    +

    dwc_otg_hcd_if.h File Reference

    This file defines DWC_OTG HCD Core API. More... +

    +-#include "dwc_otg_core_if.h"
    ++#include "dwc_otg_core_if.h"
    + +

    + Go to the source code of this file. + + +- ++ + + +- ++ + +- ++ + +- ++ + + +- ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ + +- +- ++ ++ + +- ++ ++ ++ ++ ++ ++ ++ + +- ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ + + + +- ++ + +- ++ + +

    Data Structures

    struct  dwc_otg_hcd_function_ops
    struct  dwc_otg_hcd_function_ops

    HCD Core API

    +-#define URB_GIVEBACK_ASAP   0x1
    ++#define URB_GIVEBACK_ASAP   0x1
    +-#define URB_SEND_ZERO_PACKET   0x2
    ++#define URB_SEND_ZERO_PACKET   0x2
    +-dwc_otg_hcd_t * dwc_otg_hcd_alloc_hcd (void)
    ++dwc_otg_hcd_t * dwc_otg_hcd_alloc_hcd (void)
     This function allocates dwc_otg_hcd structure and returns pointer on it.
    int dwc_otg_hcd_init (dwc_otg_hcd_t *hcd, dwc_otg_core_if_t *core_if)
    int dwc_otg_hcd_init (dwc_otg_hcd_t *hcd, dwc_otg_core_if_t *core_if)
     This function should be called to initiate HCD Core.
    void dwc_otg_hcd_remove (dwc_otg_hcd_t *hcd)
     This function should be called to initiate HCD Core.
    void dwc_otg_hcd_remove (dwc_otg_hcd_t *hcd)
     Frees HCD.
    int32_t dwc_otg_hcd_handle_intr (dwc_otg_hcd_t *dwc_otg_hcd)
     Frees HCD.
    int32_t dwc_otg_hcd_handle_intr (dwc_otg_hcd_t *dwc_otg_hcd)
     This function should be called on every hardware interrupt.
    void * dwc_otg_hcd_get_priv_data (dwc_otg_hcd_t *hcd)
     This function should be called on every hardware interrupt.
    void * dwc_otg_hcd_get_priv_data (dwc_otg_hcd_t *hcd)
     Returns private data set by dwc_otg_hcd_set_priv_data function.
    void dwc_otg_hcd_set_priv_data (dwc_otg_hcd_t *hcd, void *priv_data)
     Returns private data set by dwc_otg_hcd_set_priv_data function.
    void dwc_otg_hcd_set_priv_data (dwc_otg_hcd_t *hcd, void *priv_data)
     Set private data.
    int dwc_otg_hcd_start (dwc_otg_hcd_t *hcd, struct dwc_otg_hcd_function_ops *fops)
     Set private data.
    int dwc_otg_hcd_start (dwc_otg_hcd_t *hcd, struct dwc_otg_hcd_function_ops *fops)
     This function initializes the HCD Core.
    void dwc_otg_hcd_stop (dwc_otg_hcd_t *hcd)
     This function initializes the HCD Core.
    void dwc_otg_hcd_stop (dwc_otg_hcd_t *hcd)
     Halts the DWC_otg host mode operations in a clean manner.
    int dwc_otg_hcd_hub_control (dwc_otg_hcd_t *dwc_otg_hcd, uint16_t typeReq, uint16_t wValue, uint16_t wIndex, uint8_t *buf, uint16_t wLength)
     Halts the DWC_otg host mode operations in a clean manner.
    int dwc_otg_hcd_hub_control (dwc_otg_hcd_t *dwc_otg_hcd, uint16_t typeReq, uint16_t wValue, uint16_t wIndex, uint8_t *buf, uint16_t wLength)
     Handles hub class-specific requests.
    uint32_t dwc_otg_hcd_otg_port (dwc_otg_hcd_t *hcd)
     Handles hub class-specific requests.
    uint32_t dwc_otg_hcd_otg_port (dwc_otg_hcd_t *hcd)
     Returns otg port number.
    uint32_t dwc_otg_hcd_is_b_host (dwc_otg_hcd_t *hcd)
     Returns otg port number.
    uint16_t dwc_otg_get_otg_version (dwc_otg_core_if_t *core_if)
     Returns 1 if currently core is acting as B host, and 0 otherwise.
    int dwc_otg_hcd_get_frame_number (dwc_otg_hcd_t *hcd)
     Returns OTG version - either 1.3 or 2.0.
    uint32_t dwc_otg_hcd_is_b_host (dwc_otg_hcd_t *hcd)
     Returns current frame number.
    void dwc_otg_hcd_dump_state (dwc_otg_hcd_t *hcd)
     Returns 1 if currently core is acting as B host, and 0 otherwise.
    int dwc_otg_hcd_get_frame_number (dwc_otg_hcd_t *hcd)
     Dumps hcd state.
    void dwc_otg_hcd_dump_frrem (dwc_otg_hcd_t *hcd)
     Returns current frame number.
    void dwc_otg_hcd_dump_state (dwc_otg_hcd_t *hcd)
     Dump the average frame remaining at SOF.
    int dwc_otg_hcd_send_lpm (dwc_otg_hcd_t *hcd, uint8_t devaddr, uint8_t hird, uint8_t bRemoteWake)
     Dumps hcd state.
    void dwc_otg_hcd_dump_frrem (dwc_otg_hcd_t *hcd)
     Sends LPM transaction to the local device.
    dwc_otg_hcd_urb_t * dwc_otg_hcd_urb_alloc (dwc_otg_hcd_t *hcd, int iso_desc_count, int atomic_alloc)
     Dump the average frame remaining at SOF.
    int dwc_otg_hcd_send_lpm (dwc_otg_hcd_t *hcd, uint8_t devaddr, uint8_t hird, uint8_t bRemoteWake)
     Allocates memory for dwc_otg_hcd_urb structure.
    void dwc_otg_hcd_urb_set_pipeinfo (dwc_otg_hcd_urb_t *hcd_urb, uint8_t devaddr, uint8_t ep_num, uint8_t ep_type, uint8_t ep_dir, uint16_t mps)
     Sends LPM transaction to the local device.
    dwc_otg_hcd_urb_t * dwc_otg_hcd_urb_alloc (dwc_otg_hcd_t *hcd, int iso_desc_count, int atomic_alloc)
     Set pipe information in URB.
    void dwc_otg_hcd_urb_set_params (dwc_otg_hcd_urb_t *urb, void *urb_handle, void *buf, dwc_dma_t dma, uint32_t buflen, void *sp, dwc_dma_t sp_dma, uint32_t flags, uint16_t interval)
     Allocates memory for dwc_otg_hcd_urb structure.
    void dwc_otg_hcd_urb_set_pipeinfo (dwc_otg_hcd_urb_t *hcd_urb, uint8_t devaddr, uint8_t ep_num, uint8_t ep_type, uint8_t ep_dir, uint16_t mps)
     Sets dwc_otg_hcd_urb parameters.
    uint32_t dwc_otg_hcd_urb_get_status (dwc_otg_hcd_urb_t *dwc_otg_urb)
     Set pipe information in URB.
    void dwc_otg_hcd_urb_set_params (dwc_otg_hcd_urb_t *urb, void *urb_handle, void *buf, dwc_dma_t dma, uint32_t buflen, void *sp, dwc_dma_t sp_dma, uint32_t flags, uint16_t interval)
     Gets status from dwc_otg_hcd_urb.
    uint32_t dwc_otg_hcd_urb_get_actual_length (dwc_otg_hcd_urb_t *dwc_otg_urb)
     Sets dwc_otg_hcd_urb parameters.
    uint32_t dwc_otg_hcd_urb_get_status (dwc_otg_hcd_urb_t *dwc_otg_urb)
     Gets actual length from dwc_otg_hcd_urb.
    uint32_t dwc_otg_hcd_urb_get_error_count (dwc_otg_hcd_urb_t *dwc_otg_urb)
     Gets status from dwc_otg_hcd_urb.
    uint32_t dwc_otg_hcd_urb_get_actual_length (dwc_otg_hcd_urb_t *dwc_otg_urb)
     Gets error count from dwc_otg_hcd_urb.
    void dwc_otg_hcd_urb_set_iso_desc_params (dwc_otg_hcd_urb_t *dwc_otg_urb, int desc_num, uint32_t offset, uint32_t length)
     Gets actual length from dwc_otg_hcd_urb.
    uint32_t dwc_otg_hcd_urb_get_error_count (dwc_otg_hcd_urb_t *dwc_otg_urb)
     Set ISOC descriptor offset and length.
    uint32_t dwc_otg_hcd_urb_get_iso_desc_status (dwc_otg_hcd_urb_t *dwc_otg_urb, int desc_num)
     Gets error count from dwc_otg_hcd_urb.
    void dwc_otg_hcd_urb_set_iso_desc_params (dwc_otg_hcd_urb_t *dwc_otg_urb, int desc_num, uint32_t offset, uint32_t length)
     Get status of ISOC descriptor, specified by desc_num.
    uint32_t dwc_otg_hcd_urb_get_iso_desc_actual_length (dwc_otg_hcd_urb_t *dwc_otg_urb, int desc_num)
     Set ISOC descriptor offset and length.
    uint32_t dwc_otg_hcd_urb_get_iso_desc_status (dwc_otg_hcd_urb_t *dwc_otg_urb, int desc_num)
     Get actual length of ISOC descriptor, specified by desc_num.
    int dwc_otg_hcd_urb_enqueue (dwc_otg_hcd_t *dwc_otg_hcd, dwc_otg_hcd_urb_t *dwc_otg_urb, void **ep_handle)
     Get status of ISOC descriptor, specified by desc_num.
    uint32_t dwc_otg_hcd_urb_get_iso_desc_actual_length (dwc_otg_hcd_urb_t *dwc_otg_urb, int desc_num)
     Queue URB.
    int dwc_otg_hcd_urb_dequeue (dwc_otg_hcd_t *dwc_otg_hcd, dwc_otg_hcd_urb_t *dwc_otg_urb)
     Get actual length of ISOC descriptor, specified by desc_num.
    int dwc_otg_hcd_urb_enqueue (dwc_otg_hcd_t *dwc_otg_hcd, dwc_otg_hcd_urb_t *dwc_otg_urb, void **ep_handle, int atomic_alloc)
     De-queue the specified URB.
    int dwc_otg_hcd_endpoint_disable (dwc_otg_hcd_t *hcd, void *ep_handle, int retry)
     Queue URB.
    int dwc_otg_hcd_urb_dequeue (dwc_otg_hcd_t *dwc_otg_hcd, dwc_otg_hcd_urb_t *dwc_otg_urb)
     Frees resources in the DWC_otg controller related to a given endpoint.
    int dwc_otg_hcd_is_status_changed (dwc_otg_hcd_t *hcd, int port)
     De-queue the specified URB.
    int dwc_otg_hcd_endpoint_disable (dwc_otg_hcd_t *hcd, void *ep_handle, int retry)
     Returns 1 if status of specified port is changed and 0 otherwise.
    int dwc_otg_hcd_is_bandwidth_allocated (dwc_otg_hcd_t *hcd, void *ep_handle)
     Frees resources in the DWC_otg controller related to a given endpoint.
    ++int dwc_otg_hcd_endpoint_reset (dwc_otg_hcd_t *hcd, void *ep_handle)
     Call this function to check if bandwidth was allocated for specified endpoint.
    int dwc_otg_hcd_is_bandwidth_freed (dwc_otg_hcd_t *hcd, void *ep_handle)
    int dwc_otg_hcd_is_status_changed (dwc_otg_hcd_t *hcd, int port)
     Call this function to check if bandwidth was freed for specified endpoint.
    uint8_t dwc_otg_hcd_get_ep_bandwidth (dwc_otg_hcd_t *hcd, void *ep_handle)
     Returns 1 if status of specified port is changed and 0 otherwise.
    int dwc_otg_hcd_is_bandwidth_allocated (dwc_otg_hcd_t *hcd, void *ep_handle)
     Returns bandwidth allocated for specified endpoint in microseconds.
     Call this function to check if bandwidth was allocated for specified endpoint.
    int dwc_otg_hcd_is_bandwidth_freed (dwc_otg_hcd_t *hcd, void *ep_handle)
     Call this function to check if bandwidth was freed for specified endpoint.
    uint8_t dwc_otg_hcd_get_ep_bandwidth (dwc_otg_hcd_t *hcd, void *ep_handle)
     Returns bandwidth allocated for specified endpoint in microseconds.

    HCD Function Driver Callbacks

    +-typedef int(*) dwc_otg_hcd_start_cb_t (dwc_otg_hcd_t *hcd)
    ++typedef int(* dwc_otg_hcd_start_cb_t )(dwc_otg_hcd_t *hcd)
     This function is called whenever core switches to host mode.
    +-typedef int(*) dwc_otg_hcd_disconnect_cb_t (dwc_otg_hcd_t *hcd)
    ++typedef int(* dwc_otg_hcd_disconnect_cb_t )(dwc_otg_hcd_t *hcd)
     This function is called when device has been disconnected.
    +-typedef int(*) dwc_otg_hcd_hub_info_from_urb_cb_t (dwc_otg_hcd_t *hcd, void *urb_handle, uint32_t *hub_addr, uint32_t *port_addr)
    ++typedef int(* dwc_otg_hcd_hub_info_from_urb_cb_t )(dwc_otg_hcd_t *hcd, void *urb_handle, uint32_t *hub_addr, uint32_t *port_addr)
     Wrapper provides this function to HCD to core, so it can get hub information to which device is connected.
    +-typedef int(*) dwc_otg_hcd_speed_from_urb_cb_t (dwc_otg_hcd_t *hcd, void *urb_handle)
    ++typedef int(* dwc_otg_hcd_speed_from_urb_cb_t )(dwc_otg_hcd_t *hcd, void *urb_handle)
     Via this function HCD core gets device speed.
    +-typedef int(*) dwc_otg_hcd_complete_urb_cb_t (dwc_otg_hcd_t *hcd, void *urb_handle, dwc_otg_hcd_urb_t *dwc_otg_urb, int32_t status)
    ++typedef int(* dwc_otg_hcd_complete_urb_cb_t )(dwc_otg_hcd_t *hcd, void *urb_handle, dwc_otg_hcd_urb_t *dwc_otg_urb, int32_t status)
     This function is called when urb is completed.
    +-typedef int(*) dwc_otg_hcd_get_b_hnp_enable (dwc_otg_hcd_t *hcd)
    ++typedef int(* dwc_otg_hcd_get_b_hnp_enable )(dwc_otg_hcd_t *hcd)
     Via this function HCD core gets b_hnp_enable parameter.

    Typedefs

    +-typedef dwc_otg_hcd dwc_otg_hcd_t
    ++typedef dwc_otg_hcd dwc_otg_hcd_t
    +-typedef dwc_otg_hcd_urb dwc_otg_hcd_urb_t
    ++typedef dwc_otg_hcd_urb dwc_otg_hcd_urb_t
    +

    Detailed Description

    +@@ -167,30 +161,38 @@ + +

    + Definition in file dwc_otg_hcd_if.h.

    Function Documentation

    +- +-
    +-
    +- ++

    ++

    ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    int dwc_otg_hcd_init (dwc_otg_hcd_t *  hcd, int dwc_otg_hcd_init ( dwc_otg_hcd_t *  hcd,
    dwc_otg_core_if_t *  core_if dwc_otg_core_if_t *  core_if
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + This function should be called to initiate HCD Core. +@@ -203,24 +205,32 @@ + + Returns -DWC_E_NO_MEMORY if no enough memory. Returns 0 on success +

    +-Definition at line 693 of file dwc_otg_hcd.c. +- +-

    +- +-

    +-
    +- +- +- +- +- +- +- +- ++Definition at line 780 of file dwc_otg_hcd.c. ++ ++
    void dwc_otg_hcd_remove (dwc_otg_hcd_t *  hcd  ) 
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ + +
    void dwc_otg_hcd_remove ( dwc_otg_hcd_t *  hcd  ) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Frees HCD. +@@ -232,56 +242,65 @@ + + +

    +-Definition at line 778 of file dwc_otg_hcd.c. +- +-

    +- +-

    +-
    +- +- +- +- +- +- +- +- ++Definition at line 879 of file dwc_otg_hcd.c. ++ ++
    int32_t dwc_otg_hcd_handle_intr (dwc_otg_hcd_t *  dwc_otg_hcd  ) 
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ + +
    int32_t dwc_otg_hcd_handle_intr ( dwc_otg_hcd_t *  dwc_otg_hcd  ) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + This function should be called on every hardware interrupt. +

    +-

    Parameters:
    +- +- +-
    dwc_otg_hcd The HCD
    +-
    +-Returns non zero if interrupt is handled Return 0 if interrupt is not handled +-

    +-

    Todo:
    Implement i2cintr handler.
    ++
    Todo:
    Implement i2cintr handler.
    + +

    +-Definition at line 43 of file dwc_otg_hcd_intr.c. +- +-

    +- +-

    +-
    +- +- +- +- +- +- +- +- ++Definition at line 43 of file dwc_otg_hcd_intr.c. ++ ++
    void* dwc_otg_hcd_get_priv_data (dwc_otg_hcd_t *  hcd  ) 
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ + +
    void* dwc_otg_hcd_get_priv_data ( dwc_otg_hcd_t *  hcd  ) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Returns private data set by dwc_otg_hcd_set_priv_data function. +@@ -293,33 +312,41 @@ + + +

    +-Definition at line 2671 of file dwc_otg_hcd.c. +- +-

    +- +-

    +-
    +- ++Definition at line 2958 of file dwc_otg_hcd.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    void dwc_otg_hcd_set_priv_data (dwc_otg_hcd_t *  hcd, void dwc_otg_hcd_set_priv_data ( dwc_otg_hcd_t *  hcd,
    void *  priv_data void *  priv_data
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Set private data. +@@ -332,33 +359,41 @@ + + +

    +-Definition at line 2676 of file dwc_otg_hcd.c. +- +-

    +- +-

    +-
    +- ++Definition at line 2963 of file dwc_otg_hcd.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    int dwc_otg_hcd_start (dwc_otg_hcd_t *  hcd, int dwc_otg_hcd_start ( dwc_otg_hcd_t *  hcd,
    struct dwc_otg_hcd_function_ops *  fops struct dwc_otg_hcd_function_ops *  fops
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + This function initializes the HCD Core. +@@ -371,115 +406,132 @@ + + Returns -DWC_E_NO_DEVICE if Core is currently is in device mode. Returns 0 on success +

    +-Definition at line 2656 of file dwc_otg_hcd.c. +- +-

    +- +-

    +-
    +- +- +- +- +- +- +- +- ++Definition at line 2942 of file dwc_otg_hcd.c. ++ ++
    void dwc_otg_hcd_stop (dwc_otg_hcd_t *  hcd  ) 
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ + +
    void dwc_otg_hcd_stop ( dwc_otg_hcd_t *  hcd  ) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Halts the DWC_otg host mode operations in a clean manner. +

    + USB transfers are stopped. +

    +-Definition at line 422 of file dwc_otg_hcd.c. +- +-

    +- +-

    +-
    +- ++Definition at line 421 of file dwc_otg_hcd.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    int dwc_otg_hcd_hub_control (dwc_otg_hcd_t *  dwc_otg_hcd, int dwc_otg_hcd_hub_control ( dwc_otg_hcd_t *  dwc_otg_hcd,
    uint16_t  typeReq, uint16_t  typeReq,
    uint16_t  wValue, uint16_t  wValue,
    uint16_t  wIndex, uint16_t  wIndex,
    uint8_t *  buf, uint8_t *  buf,
    uint16_t  wLength uint16_t  wLength
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Handles hub class-specific requests. +

    +-

    Parameters:
    +- +- +- +- +- +- +- +-
    dwc_otg_hcd The HCD
    typeReq Request Type
    wValue wValue from control request
    wIndex wIndex from control request
    buf data buffer
    wLength data buffer length
    +-
    +-Returns -DWC_E_INVALID if invalid argument is passed Returns 0 on success +-

    +-Definition at line 1905 of file dwc_otg_hcd.c. +- +-

    +- +-

    +-
    +- +- +- +- +- +- +- +- ++
    Todo:
      ++
    • check how sw can wait for 1 sec to check asesvld???
    ++
    ++ ++

    ++Definition at line 2015 of file dwc_otg_hcd.c. ++

    ++
    uint32_t dwc_otg_hcd_otg_port (dwc_otg_hcd_t *  hcd  ) 
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ + +
    uint32_t dwc_otg_hcd_otg_port ( dwc_otg_hcd_t *  hcd  ) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Returns otg port number. +@@ -491,24 +543,69 @@ + + +

    +-Definition at line 2681 of file dwc_otg_hcd.c. +- +-

    +- +-

    +-
    +- +- +- +- +- +- +- +- ++Definition at line 2968 of file dwc_otg_hcd.c. ++ ++
    uint32_t dwc_otg_hcd_is_b_host (dwc_otg_hcd_t *  hcd  ) 
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
    uint16_t dwc_otg_get_otg_version ( dwc_otg_core_if_t *  core_if  ) 
    ++
    ++ ++ ++ ++ ++ ++
    ++   ++ ++ ++

    ++Returns OTG version - either 1.3 or 2.0. ++

    ++

    Parameters:
    ++ ++ ++
    core_if The core_if structure pointer
    ++
    ++ ++

    ++Definition at line 7012 of file dwc_otg_cil.c.

    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ + +
    uint32_t dwc_otg_hcd_is_b_host ( dwc_otg_hcd_t *  hcd  ) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Returns 1 if currently core is acting as B host, and 0 otherwise. +@@ -520,24 +617,32 @@ + + +

    +-Definition at line 2686 of file dwc_otg_hcd.c. +- +-

    +- +-

    +-
    +- +- +- +- +- +- +- +- ++Definition at line 2973 of file dwc_otg_hcd.c. ++ ++
    int dwc_otg_hcd_get_frame_number (dwc_otg_hcd_t *  hcd  ) 
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ + +
    int dwc_otg_hcd_get_frame_number ( dwc_otg_hcd_t *  hcd  ) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Returns current frame number. +@@ -549,24 +654,32 @@ + + +

    +-Definition at line 2643 of file dwc_otg_hcd.c. +- +-

    +- +-

    +-
    +- +- +- +- +- +- +- +- ++Definition at line 2928 of file dwc_otg_hcd.c. ++ ++
    void dwc_otg_hcd_dump_state (dwc_otg_hcd_t *  hcd  ) 
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ + +
    void dwc_otg_hcd_dump_state ( dwc_otg_hcd_t *  hcd  ) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Dumps hcd state. +@@ -578,24 +691,32 @@ + + +

    +-Definition at line 2815 of file dwc_otg_hcd.c. +- +-

    +- +-

    +-
    +- +- +- +- +- +- +- +- ++Definition at line 3102 of file dwc_otg_hcd.c. ++ ++
    void dwc_otg_hcd_dump_frrem (dwc_otg_hcd_t *  hcd  ) 
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ + +
    void dwc_otg_hcd_dump_frrem ( dwc_otg_hcd_t *  hcd  ) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Dump the average frame remaining at SOF. +@@ -608,45 +729,53 @@ + + +

    +-Definition at line 2991 of file dwc_otg_hcd.c. +- +-

    +- +-

    +-
    +- ++Definition at line 3278 of file dwc_otg_hcd.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    int dwc_otg_hcd_send_lpm (dwc_otg_hcd_t *  hcd, int dwc_otg_hcd_send_lpm ( dwc_otg_hcd_t *  hcd,
    uint8_t  devaddr, uint8_t  devaddr,
    uint8_t  hird, uint8_t  hird,
    uint8_t  bRemoteWake uint8_t  bRemoteWake
    )) 
    +- +-
    ++
    ++ ++ ++ ++ +
    ++   ++ + +

    + Sends LPM transaction to the local device. +@@ -659,44 +788,52 @@ +

    bRemoteWake Value of bRemoteWake field in LPM transaction
    + +-Returns negative value if sending LPM transaction was not succeeded. Returns 0 on success. +-

    +-

    +- +-

    +-
    +- ++Returns negative value if sending LPM transaction was not succeeded. Returns 0 on success. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    dwc_otg_hcd_urb_t* dwc_otg_hcd_urb_alloc (dwc_otg_hcd_t *  hcd, dwc_otg_hcd_urb_t* dwc_otg_hcd_urb_alloc ( dwc_otg_hcd_t *  hcd,
    int  iso_desc_count, int  iso_desc_count,
    int  atomic_alloc int  atomic_alloc
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    +-Allocates memory for dwc_otg_hcd_urb structure. ++Allocates memory for dwc_otg_hcd_urb structure. +

    +-Allocated memory should be freed by call dwc_free function.

    ++Allocated memory should be freed by call of DWC_FREE.

    +

    Parameters:
    + + +@@ -706,57 +843,65 @@ + + +

    +-Definition at line 2698 of file dwc_otg_hcd.c. +- +-

    +- +-

    +-
    +-
    hcd The HCD
    ++Definition at line 2985 of file dwc_otg_hcd.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    void dwc_otg_hcd_urb_set_pipeinfo (dwc_otg_hcd_urb_t *  hcd_urb, void dwc_otg_hcd_urb_set_pipeinfo ( dwc_otg_hcd_urb_t *  hcd_urb,
    uint8_t  devaddr, uint8_t  devaddr,
    uint8_t  ep_num, uint8_t  ep_num,
    uint8_t  ep_type, uint8_t  ep_type,
    uint8_t  ep_dir, uint8_t  ep_dir,
    uint16_t  mps uint16_t  mps
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Set pipe information in URB. +@@ -773,78 +918,86 @@ + + +

    +-Definition at line 2717 of file dwc_otg_hcd.c. +- +-

    +- +-

    +-
    +- ++Definition at line 3004 of file dwc_otg_hcd.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    void dwc_otg_hcd_urb_set_params (dwc_otg_hcd_urb_t *  urb, void dwc_otg_hcd_urb_set_params ( dwc_otg_hcd_urb_t *  urb,
    void *  urb_handle, void *  urb_handle,
    void *  buf, void *  buf,
    dwc_dma_t  dma, dwc_dma_t  dma,
    uint32_t  buflen, uint32_t  buflen,
    void *  sp, void *  sp,
    dwc_dma_t  sp_dma, dwc_dma_t  sp_dma,
    uint32_t  flags, uint32_t  flags,
    uint16_t  interval uint16_t  interval
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    +-Sets dwc_otg_hcd_urb parameters. ++Sets dwc_otg_hcd_urb parameters. +

    +

    Parameters:
    + +@@ -861,27 +1014,35 @@ + + +

    +-Definition at line 2730 of file dwc_otg_hcd.c. +- +-

    +- +-

    +-
    +-
    +- +- +- +- +- +- +- ++Definition at line 3017 of file dwc_otg_hcd.c. ++ ++
    uint32_t dwc_otg_hcd_urb_get_status (dwc_otg_hcd_urb_t *  dwc_otg_urb  ) 
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ + +
    uint32_t dwc_otg_hcd_urb_get_status ( dwc_otg_hcd_urb_t *  dwc_otg_urb  ) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    +-Gets status from dwc_otg_hcd_urb. ++Gets status from dwc_otg_hcd_urb. +

    +

    Parameters:
    + +@@ -890,27 +1051,35 @@ + + +

    +-Definition at line 2747 of file dwc_otg_hcd.c. +- +-

    +- +-

    +-
    +-
    +- +- +- +- +- +- +- ++Definition at line 3034 of file dwc_otg_hcd.c. ++ ++
    uint32_t dwc_otg_hcd_urb_get_actual_length (dwc_otg_hcd_urb_t *  dwc_otg_urb  ) 
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ + +
    uint32_t dwc_otg_hcd_urb_get_actual_length ( dwc_otg_hcd_urb_t *  dwc_otg_urb  ) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    +-Gets actual length from dwc_otg_hcd_urb. ++Gets actual length from dwc_otg_hcd_urb. +

    +

    Parameters:
    + +@@ -919,27 +1088,35 @@ + + +

    +-Definition at line 2752 of file dwc_otg_hcd.c. +- +-

    +- +-

    +-
    +-
    +- +- +- +- +- +- +- ++Definition at line 3039 of file dwc_otg_hcd.c. ++ ++
    uint32_t dwc_otg_hcd_urb_get_error_count (dwc_otg_hcd_urb_t *  dwc_otg_urb  ) 
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ + +
    uint32_t dwc_otg_hcd_urb_get_error_count ( dwc_otg_hcd_urb_t *  dwc_otg_urb  ) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    +-Gets error count from dwc_otg_hcd_urb. ++Gets error count from dwc_otg_hcd_urb. +

    + Only for ISOC URBs

    +

    Parameters:
    +@@ -949,45 +1126,53 @@ +
    + +

    +-Definition at line 2757 of file dwc_otg_hcd.c. +- +-

    +- +-

    +-
    +- ++Definition at line 3044 of file dwc_otg_hcd.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    void dwc_otg_hcd_urb_set_iso_desc_params (dwc_otg_hcd_urb_t *  dwc_otg_urb, void dwc_otg_hcd_urb_set_iso_desc_params ( dwc_otg_hcd_urb_t *  dwc_otg_urb,
    int  desc_num, int  desc_num,
    uint32_t  offset, uint32_t  offset,
    uint32_t  length uint32_t  length
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Set ISOC descriptor offset and length. +@@ -1002,33 +1187,41 @@ + + +

    +-Definition at line 2762 of file dwc_otg_hcd.c. +- +-

    +- +-

    +-
    +- ++Definition at line 3049 of file dwc_otg_hcd.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    uint32_t dwc_otg_hcd_urb_get_iso_desc_status (dwc_otg_hcd_urb_t *  dwc_otg_urb, uint32_t dwc_otg_hcd_urb_get_iso_desc_status ( dwc_otg_hcd_urb_t *  dwc_otg_urb,
    int  desc_num int  desc_num
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Get status of ISOC descriptor, specified by desc_num. +@@ -1041,33 +1234,41 @@ + + +

    +-Definition at line 2770 of file dwc_otg_hcd.c. +- +-

    +- +-

    +-
    +- ++Definition at line 3057 of file dwc_otg_hcd.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    uint32_t dwc_otg_hcd_urb_get_iso_desc_actual_length (dwc_otg_hcd_urb_t *  dwc_otg_urb, uint32_t dwc_otg_hcd_urb_get_iso_desc_actual_length ( dwc_otg_hcd_urb_t *  dwc_otg_urb,
    int  desc_num int  desc_num
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Get actual length of ISOC descriptor, specified by desc_num. +@@ -1080,39 +1281,53 @@ + + +

    +-Definition at line 2776 of file dwc_otg_hcd.c. +- +-

    +- +-

    +-
    +- ++Definition at line 3063 of file dwc_otg_hcd.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ ++ ++ ++ ++ ++ ++ + +
    int dwc_otg_hcd_urb_enqueue (dwc_otg_hcd_t *  dwc_otg_hcd, int dwc_otg_hcd_urb_enqueue ( dwc_otg_hcd_t *  dwc_otg_hcd,
    dwc_otg_hcd_urb_t *  dwc_otg_urb, dwc_otg_hcd_urb_t *  dwc_otg_urb,
    void **  ep_handle void **  ep_handle,
    )int  atomic_alloc
    ) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Queue URB. +@@ -1120,85 +1335,102 @@ + After transfer is completes, the complete callback will be called with the URB status

    +

    Parameters:
    + +- ++ + +- ++ ++ +
    dwc_otg_hcd The HCD
    dwc_otg_hcd The HCD
    dwc_otg_urb DWC_OTG URB
    ep_handle Out parameter for returning endpoint handle
    ep_handle Out parameter for returning endpoint handle
    atomic_alloc Flag to do atomic allocation if needed
    +
    + Returns -DWC_E_NO_DEVICE if no device is connected. Returns -DWC_E_NO_MEMORY if there is no enough memory. Returns 0 on success. +

    +-Definition at line 444 of file dwc_otg_hcd.c. +- +-

    +- +-

    +-
    +- ++Definition at line 443 of file dwc_otg_hcd.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    int dwc_otg_hcd_urb_dequeue (dwc_otg_hcd_t *  dwc_otg_hcd, int dwc_otg_hcd_urb_dequeue ( dwc_otg_hcd_t *  dwc_otg_hcd,
    dwc_otg_hcd_urb_t *  dwc_otg_urb dwc_otg_hcd_urb_t *  dwc_otg_urb
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + De-queue the specified URB. +

    +

    Parameters:
    + +- ++ + +
    dwc_otg_hcd The HCD
    dwc_otg_hcd The HCD
    dwc_otg_urb DWC_OTG URB
    +
    + +

    +-Definition at line 489 of file dwc_otg_hcd.c. +- +-

    +- +-

    +-
    +- ++Definition at line 492 of file dwc_otg_hcd.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    int dwc_otg_hcd_endpoint_disable (dwc_otg_hcd_t *  hcd, int dwc_otg_hcd_endpoint_disable ( dwc_otg_hcd_t *  hcd,
    void *  ep_handle, void *  ep_handle,
    int  retry int  retry
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Frees resources in the DWC_otg controller related to a given endpoint. +@@ -1213,33 +1445,41 @@ + + Returns -DWC_E_INVALID if invalid arguments are passed. Returns 0 on success +

    +-Definition at line 547 of file dwc_otg_hcd.c. +- +-

    +- +-

    +-
    +- ++Definition at line 542 of file dwc_otg_hcd.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    int dwc_otg_hcd_is_status_changed (dwc_otg_hcd_t *  hcd, int dwc_otg_hcd_is_status_changed ( dwc_otg_hcd_t *  hcd,
    int  port int  port
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Returns 1 if status of specified port is changed and 0 otherwise. +@@ -1252,33 +1492,41 @@ + + +

    +-Definition at line 2611 of file dwc_otg_hcd.c. +- +-

    +- +-

    +-
    +- ++Definition at line 2896 of file dwc_otg_hcd.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    int dwc_otg_hcd_is_bandwidth_allocated (dwc_otg_hcd_t *  hcd, int dwc_otg_hcd_is_bandwidth_allocated ( dwc_otg_hcd_t *  hcd,
    void *  ep_handle void *  ep_handle
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Call this function to check if bandwidth was allocated for specified endpoint. +@@ -1292,33 +1540,41 @@ + + +

    +-Definition at line 2782 of file dwc_otg_hcd.c. +- +-

    +- +-

    +-
    +- ++Definition at line 3069 of file dwc_otg_hcd.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    int dwc_otg_hcd_is_bandwidth_freed (dwc_otg_hcd_t *  hcd, int dwc_otg_hcd_is_bandwidth_freed ( dwc_otg_hcd_t *  hcd,
    void *  ep_handle void *  ep_handle
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Call this function to check if bandwidth was freed for specified endpoint. +@@ -1331,33 +1587,41 @@ + + +

    +-Definition at line 2795 of file dwc_otg_hcd.c. +- +-

    +- +-

    +-
    +- ++Definition at line 3082 of file dwc_otg_hcd.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    uint8_t dwc_otg_hcd_get_ep_bandwidth (dwc_otg_hcd_t *  hcd, uint8_t dwc_otg_hcd_get_ep_bandwidth ( dwc_otg_hcd_t *  hcd,
    void *  ep_handle void *  ep_handle
    )) 
    +- +-
    ++
    ++ ++ ++ ++ ++ ++
    ++   ++ + +

    + Returns bandwidth allocated for specified endpoint in microseconds. +@@ -1371,11 +1635,11 @@ + + +

    +-Definition at line 2808 of file dwc_otg_hcd.c. +- +-

    +-

    Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++Definition at line 3095 of file dwc_otg_hcd.c.
    ++

    Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
    ++doxygen 1.3.9.1 + + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__hcd__intr_8c-source.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/dwc__otg__hcd__intr_8c-source.html 2013-07-26 19:31:21.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__hcd__intr_8c-source.html 2013-07-26 19:34:41.000000000 +0000 +@@ -2,1872 +2,1920 @@ + + DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_hcd_intr.c Source File + +- + +- +-
    +-
    +-
    +-
    +-

    dwc_otg_hcd_intr.c

    Go to the documentation of this file.
    00001 /* ==========================================================================
+-00002  * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd_intr.c $
+-00003  * $Revision: #77 $
+-00004  * $Date: 2009/04/21 $
+-00005  * $Change: 1237475 $
+-00006  *
+-00007  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
+-00008  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
+-00009  * otherwise expressly agreed to in writing between Synopsys and you.
+-00010  *
+-00011  * The Software IS NOT an item of Licensed Software or Licensed Product under
+-00012  * any End User Software License Agreement or Agreement for Licensed Product
+-00013  * with Synopsys or any supplement thereto. You are permitted to use and
+-00014  * redistribute this Software in source and binary forms, with or without
+-00015  * modification, provided that redistributions of source code must retain this
+-00016  * notice. You may not view, use, disclose, copy or distribute this file or
+-00017  * any information contained herein except pursuant to this license grant from
+-00018  * Synopsys. If you do not agree with this notice, including the disclaimer
+-00019  * below, then you are not authorized to use the Software.
+-00020  *
+-00021  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
+-00022  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+-00023  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+-00024  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
+-00025  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+-00026  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+-00027  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+-00028  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+-00029  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+-00030  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+-00031  * DAMAGE.
+-00032  * ========================================================================== */
+-00033 #ifndef DWC_DEVICE_ONLY
+-00034 
+-00035 #include "dwc_otg_hcd.h"
+-00036 #include "dwc_otg_regs.h"
+-00037 
+-00043 int32_t dwc_otg_hcd_handle_intr(dwc_otg_hcd_t * dwc_otg_hcd)
+-00044 {
+-00045         int retval = 0;
+-00046 
+-00047         dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;
+-00048         gintsts_data_t gintsts;
+-00049 #ifdef DEBUG
+-00050         dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
+-00051 #endif
+-00052 
+-00053         /* Check if HOST Mode */
+-00054         if (dwc_otg_is_host_mode(core_if)) {
+-00055                 gintsts.d32 = dwc_otg_read_core_intr(core_if);
+-00056                 if (!gintsts.d32) {
+-00057                         return 0;
+-00058                 }
+-00059 #ifdef DEBUG
+-00060                 /* Don't print debug message in the interrupt handler on SOF */
+-00061 #ifndef DEBUG_SOF
+-00062                 if (gintsts.d32 != DWC_SOF_INTR_MASK)
+-00063 #endif
+-00064                         DWC_DEBUGPL(DBG_HCD, "\n");
+-00065 #endif
+-00066 
+-00067 #ifdef DEBUG
+-00068 #ifndef DEBUG_SOF
+-00069                 if (gintsts.d32 != DWC_SOF_INTR_MASK)
+-00070 #endif
+-00071                         DWC_DEBUGPL(DBG_HCD,
+-00072                                     "DWC OTG HCD Interrupt Detected gintsts&gintmsk=0x%08x\n",
+-00073                                     gintsts.d32);
+-00074 #endif
+-00075 
+-00076                 if (gintsts.b.sofintr) {
+-00077                         retval |= dwc_otg_hcd_handle_sof_intr(dwc_otg_hcd);
+-00078                 }
+-00079                 if (gintsts.b.rxstsqlvl) {
+-00080                         retval |=
+-00081                             dwc_otg_hcd_handle_rx_status_q_level_intr
+-00082                             (dwc_otg_hcd);
+-00083                 }
+-00084                 if (gintsts.b.nptxfempty) {
+-00085                         retval |=
+-00086                             dwc_otg_hcd_handle_np_tx_fifo_empty_intr
+-00087                             (dwc_otg_hcd);
+-00088                 }
+-00089                 if (gintsts.b.i2cintr) {
+-00091                 }
+-00092                 if (gintsts.b.portintr) {
+-00093                         retval |= dwc_otg_hcd_handle_port_intr(dwc_otg_hcd);
+-00094                 }
+-00095                 if (gintsts.b.hcintr) {
+-00096                         retval |= dwc_otg_hcd_handle_hc_intr(dwc_otg_hcd);
+-00097                 }
+-00098                 if (gintsts.b.ptxfempty) {
+-00099                         retval |=
+-00100                             dwc_otg_hcd_handle_perio_tx_fifo_empty_intr
+-00101                             (dwc_otg_hcd);
+-00102                 }
+-00103 #ifdef DEBUG
+-00104 #ifndef DEBUG_SOF
+-00105                 if (gintsts.d32 != DWC_SOF_INTR_MASK)
+-00106 #endif
+-00107                 {
+-00108                         DWC_DEBUGPL(DBG_HCD,
+-00109                                     "DWC OTG HCD Finished Servicing Interrupts\n");
+-00110                         DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD gintsts=0x%08x\n",
+-00111                                     dwc_read_reg32(&global_regs->gintsts));
+-00112                         DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD gintmsk=0x%08x\n",
+-00113                                     dwc_read_reg32(&global_regs->gintmsk));
+-00114                 }
+-00115 #endif
+-00116 
+-00117 #ifdef DEBUG
+-00118 #ifndef DEBUG_SOF
+-00119                 if (gintsts.d32 != DWC_SOF_INTR_MASK)
+-00120 #endif
+-00121                         DWC_DEBUGPL(DBG_HCD, "\n");
+-00122 #endif
+-00123 
+-00124         }
+-00125 
+-00126         return retval;
+-00127 }
+-00128 
+-00129 #ifdef DWC_TRACK_MISSED_SOFS
+-00130 #warning Compiling code to track missed SOFs
+-00131 #define FRAME_NUM_ARRAY_SIZE 1000
+-00132 
+-00135 static inline void track_missed_sofs(uint16_t curr_frame_number)
+-00136 {
+-00137         static uint16_t frame_num_array[FRAME_NUM_ARRAY_SIZE];
+-00138         static uint16_t last_frame_num_array[FRAME_NUM_ARRAY_SIZE];
+-00139         static int frame_num_idx = 0;
+-00140         static uint16_t last_frame_num = DWC_HFNUM_MAX_FRNUM;
+-00141         static int dumped_frame_num_array = 0;
+-00142 
+-00143         if (frame_num_idx < FRAME_NUM_ARRAY_SIZE) {
+-00144                 if (((last_frame_num + 1) & DWC_HFNUM_MAX_FRNUM) !=
+-00145                     curr_frame_number) {
+-00146                         frame_num_array[frame_num_idx] = curr_frame_number;
+-00147                         last_frame_num_array[frame_num_idx++] = last_frame_num;
+-00148                 }
+-00149         } else if (!dumped_frame_num_array) {
+-00150                 int i;
+-00151                 DWC_PRINTF("Frame     Last Frame\n");
+-00152                 DWC_PRINTF("-----     ----------\n");
+-00153                 for (i = 0; i < FRAME_NUM_ARRAY_SIZE; i++) {
+-00154                         DWC_PRINTF("0x%04x    0x%04x\n",
+-00155                                    frame_num_array[i], last_frame_num_array[i]);
+-00156                 }
+-00157                 dumped_frame_num_array = 1;
+-00158         }
+-00159         last_frame_num = curr_frame_number;
+-00160 }
+-00161 #endif
+-00162 
+-00169 int32_t dwc_otg_hcd_handle_sof_intr(dwc_otg_hcd_t * hcd)
+-00170 {
+-00171         hfnum_data_t hfnum;
+-00172         dwc_list_link_t *qh_entry;
+-00173         dwc_otg_qh_t *qh;
+-00174         dwc_otg_transaction_type_e tr_type;
+-00175         gintsts_data_t gintsts = {.d32 = 0 };
+-00176 
+-00177         hfnum.d32 =
+-00178             dwc_read_reg32(&hcd->core_if->host_if->host_global_regs->hfnum);
+-00179 
+-00180 #ifdef DEBUG_SOF
+-00181         DWC_DEBUGPL(DBG_HCD, "--Start of Frame Interrupt--\n");
+-00182 #endif
+-00183         hcd->frame_number = hfnum.b.frnum;
+-00184 
+-00185 #ifdef DEBUG
+-00186         hcd->frrem_accum += hfnum.b.frrem;
+-00187         hcd->frrem_samples++;
+-00188 #endif
+-00189 
+-00190 #ifdef DWC_TRACK_MISSED_SOFS
+-00191         track_missed_sofs(hcd->frame_number);
+-00192 #endif
+-00193         /* Determine whether any periodic QHs should be executed. */
+-00194         qh_entry = DWC_LIST_FIRST(&hcd->periodic_sched_inactive);
+-00195         while (qh_entry != &hcd->periodic_sched_inactive) {
+-00196                 qh = DWC_LIST_ENTRY(qh_entry, dwc_otg_qh_t, qh_list_entry);
+-00197                 qh_entry = qh_entry->next;
+-00198                 if (dwc_frame_num_le(qh->sched_frame, hcd->frame_number)) {
+-00199                         /*
+-00200                          * Move QH to the ready list to be executed next
+-00201                          * (micro)frame.
+-00202                          */
+-00203                         DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_ready,
+-00204                                            &qh->qh_list_entry);
+-00205                 }
+-00206         }
+-00207         tr_type = dwc_otg_hcd_select_transactions(hcd);
+-00208         if (tr_type != DWC_OTG_TRANSACTION_NONE) {
+-00209                 dwc_otg_hcd_queue_transactions(hcd, tr_type);
+-00210         }
+-00211 
+-00212         /* Clear interrupt */
+-00213         gintsts.b.sofintr = 1;
+-00214         dwc_write_reg32(&hcd->core_if->core_global_regs->gintsts, gintsts.d32);
+-00215 
+-00216         return 1;
+-00217 }
+-00218 
+-00222 int32_t dwc_otg_hcd_handle_rx_status_q_level_intr(dwc_otg_hcd_t * dwc_otg_hcd)
+-00223 {
+-00224         host_grxsts_data_t grxsts;
+-00225         dwc_hc_t *hc = NULL;
+-00226 
+-00227         DWC_DEBUGPL(DBG_HCD, "--RxStsQ Level Interrupt--\n");
+-00228 
+-00229         grxsts.d32 =
+-00230             dwc_read_reg32(&dwc_otg_hcd->core_if->core_global_regs->grxstsp);
+-00231 
+-00232         hc = dwc_otg_hcd->hc_ptr_array[grxsts.b.chnum];
+-00233 
+-00234         /* Packet Status */
+-00235         DWC_DEBUGPL(DBG_HCDV, "    Ch num = %d\n", grxsts.b.chnum);
+-00236         DWC_DEBUGPL(DBG_HCDV, "    Count = %d\n", grxsts.b.bcnt);
+-00237         DWC_DEBUGPL(DBG_HCDV, "    DPID = %d, hc.dpid = %d\n", grxsts.b.dpid,
+-00238                     hc->data_pid_start);
+-00239         DWC_DEBUGPL(DBG_HCDV, "    PStatus = %d\n", grxsts.b.pktsts);
+-00240 
+-00241         switch (grxsts.b.pktsts) {
+-00242         case DWC_GRXSTS_PKTSTS_IN:
+-00243                 /* Read the data into the host buffer. */
+-00244                 if (grxsts.b.bcnt > 0) {
+-00245                         dwc_otg_read_packet(dwc_otg_hcd->core_if,
+-00246                                             hc->xfer_buff, grxsts.b.bcnt);
+-00247 
+-00248                         /* Update the HC fields for the next packet received. */
+-00249                         hc->xfer_count += grxsts.b.bcnt;
+-00250                         hc->xfer_buff += grxsts.b.bcnt;
+-00251                 }
+-00252 
+-00253         case DWC_GRXSTS_PKTSTS_IN_XFER_COMP:
+-00254         case DWC_GRXSTS_PKTSTS_DATA_TOGGLE_ERR:
+-00255         case DWC_GRXSTS_PKTSTS_CH_HALTED:
+-00256                 /* Handled in interrupt, just ignore data */
+-00257                 break;
+-00258         default:
+-00259                 DWC_ERROR("RX_STS_Q Interrupt: Unknown status %d\n",
+-00260                           grxsts.b.pktsts);
+-00261                 break;
+-00262         }
+-00263 
+-00264         return 1;
+-00265 }
+-00266 
+-00271 int32_t dwc_otg_hcd_handle_np_tx_fifo_empty_intr(dwc_otg_hcd_t * dwc_otg_hcd)
+-00272 {
+-00273         DWC_DEBUGPL(DBG_HCD, "--Non-Periodic TxFIFO Empty Interrupt--\n");
+-00274         dwc_otg_hcd_queue_transactions(dwc_otg_hcd,
+-00275                                        DWC_OTG_TRANSACTION_NON_PERIODIC);
+-00276         return 1;
+-00277 }
+-00278 
+-00283 int32_t dwc_otg_hcd_handle_perio_tx_fifo_empty_intr(dwc_otg_hcd_t * dwc_otg_hcd)
+-00284 {
+-00285         DWC_DEBUGPL(DBG_HCD, "--Periodic TxFIFO Empty Interrupt--\n");
+-00286         dwc_otg_hcd_queue_transactions(dwc_otg_hcd,
+-00287                                        DWC_OTG_TRANSACTION_PERIODIC);
+-00288         return 1;
+-00289 }
+-00290 
+-00294 int32_t dwc_otg_hcd_handle_port_intr(dwc_otg_hcd_t * dwc_otg_hcd)
+-00295 {
+-00296         int retval = 0;
+-00297         hprt0_data_t hprt0;
+-00298         hprt0_data_t hprt0_modify;
+-00299 
+-00300         hprt0.d32 = dwc_read_reg32(dwc_otg_hcd->core_if->host_if->hprt0);
+-00301         hprt0_modify.d32 = dwc_read_reg32(dwc_otg_hcd->core_if->host_if->hprt0);
+-00302 
+-00303         /* Clear appropriate bits in HPRT0 to clear the interrupt bit in
+-00304          * GINTSTS */
+-00305 
+-00306         hprt0_modify.b.prtena = 0;
+-00307         hprt0_modify.b.prtconndet = 0;
+-00308         hprt0_modify.b.prtenchng = 0;
+-00309         hprt0_modify.b.prtovrcurrchng = 0;
+-00310 
+-00311         /* Port Connect Detected
+-00312          * Set flag and clear if detected */
+-00313         if (hprt0.b.prtconndet) {
+-00314                 DWC_DEBUGPL(DBG_HCD, "--Port Interrupt HPRT0=0x%08x "
+-00315                             "Port Connect Detected--\n", hprt0.d32);
+-00316                 dwc_otg_hcd->flags.b.port_connect_status_change = 1;
+-00317                 dwc_otg_hcd->flags.b.port_connect_status = 1;
+-00318                 hprt0_modify.b.prtconndet = 1;
+-00319 
+-00320                 /* B-Device has connected, Delete the connection timer. */
+-00321                 DWC_TIMER_CANCEL(dwc_otg_hcd->conn_timer);
+-00322 
+-00323                 /* The Hub driver asserts a reset when it sees port connect
+-00324                  * status change flag */
+-00325                 retval |= 1;
+-00326         }
+-00327 
+-00328         /* Port Enable Changed
+-00329          * Clear if detected - Set internal flag if disabled */
+-00330         if (hprt0.b.prtenchng) {
+-00331                 DWC_DEBUGPL(DBG_HCD, "  --Port Interrupt HPRT0=0x%08x "
+-00332                             "Port Enable Changed--\n", hprt0.d32);
+-00333                 hprt0_modify.b.prtenchng = 1;
+-00334                 if (hprt0.b.prtena == 1) {
+-00335                         int do_reset = 0;
+-00336                         dwc_otg_core_params_t *params =
+-00337                             dwc_otg_hcd->core_if->core_params;
+-00338                         dwc_otg_core_global_regs_t *global_regs =
+-00339                             dwc_otg_hcd->core_if->core_global_regs;
+-00340                         dwc_otg_host_if_t *host_if =
+-00341                             dwc_otg_hcd->core_if->host_if;
+-00342 
+-00343                         /* Check if we need to adjust the PHY clock speed for
+-00344                          * low power and adjust it */
+-00345                         if (params->host_support_fs_ls_low_power) {
+-00346                                 gusbcfg_data_t usbcfg;
+-00347 
+-00348                                 usbcfg.d32 =
+-00349                                     dwc_read_reg32(&global_regs->gusbcfg);
+-00350 
+-00351                                 if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_LOW_SPEED
+-00352                                     || hprt0.b.prtspd ==
+-00353                                     DWC_HPRT0_PRTSPD_FULL_SPEED) {
+-00354                                         /*
+-00355                                          * Low power
+-00356                                          */
+-00357                                         hcfg_data_t hcfg;
+-00358                                         if (usbcfg.b.phylpwrclksel == 0) {
+-00359                                                 /* Set PHY low power clock select for FS/LS devices */
+-00360                                                 usbcfg.b.phylpwrclksel = 1;
+-00361                                                 dwc_write_reg32(&global_regs->
+-00362                                                                 gusbcfg,
+-00363                                                                 usbcfg.d32);
+-00364                                                 do_reset = 1;
+-00365                                         }
+-00366 
+-00367                                         hcfg.d32 =
+-00368                                             dwc_read_reg32(&host_if->
+-00369                                                            host_global_regs->hcfg);
+-00370 
+-00371                                         if (hprt0.b.prtspd ==
+-00372                                             DWC_HPRT0_PRTSPD_LOW_SPEED
+-00373                                             && params->
+-00374                                             host_ls_low_power_phy_clk ==
+-00375                                             DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ)
+-00376                                         {
+-00377                                                 /* 6 MHZ */
+-00378                                                 DWC_DEBUGPL(DBG_CIL,
+-00379                                                             "FS_PHY programming HCFG to 6 MHz (Low Power)\n");
+-00380                                                 if (hcfg.b.fslspclksel !=
+-00381                                                     DWC_HCFG_6_MHZ) {
+-00382                                                         hcfg.b.fslspclksel =
+-00383                                                             DWC_HCFG_6_MHZ;
+-00384                                                         dwc_write_reg32
+-00385                                                             (&host_if->
+-00386                                                              host_global_regs->
+-00387                                                              hcfg, hcfg.d32);
+-00388                                                         do_reset = 1;
+-00389                                                 }
+-00390                                         } else {
+-00391                                                 /* 48 MHZ */
+-00392                                                 DWC_DEBUGPL(DBG_CIL,
+-00393                                                             "FS_PHY programming HCFG to 48 MHz ()\n");
+-00394                                                 if (hcfg.b.fslspclksel !=
+-00395                                                     DWC_HCFG_48_MHZ) {
+-00396                                                         hcfg.b.fslspclksel =
+-00397                                                             DWC_HCFG_48_MHZ;
+-00398                                                         dwc_write_reg32
+-00399                                                             (&host_if->
+-00400                                                              host_global_regs->
+-00401                                                              hcfg, hcfg.d32);
+-00402                                                         do_reset = 1;
+-00403                                                 }
+-00404                                         }
+-00405                                 } else {
+-00406                                         /*
+-00407                                          * Not low power
+-00408                                          */
+-00409                                         if (usbcfg.b.phylpwrclksel == 1) {
+-00410                                                 usbcfg.b.phylpwrclksel = 0;
+-00411                                                 dwc_write_reg32(&global_regs->
+-00412                                                                 gusbcfg,
+-00413                                                                 usbcfg.d32);
+-00414                                                 do_reset = 1;
+-00415                                         }
+-00416                                 }
+-00417 
+-00418                                 if (do_reset) {
+-00419                                         DWC_TASK_SCHEDULE(dwc_otg_hcd->
+-00420                                                           reset_tasklet);
+-00421                                 }
+-00422                         }
+-00423 
+-00424                         if (!do_reset) {
+-00425                                 /* Port has been enabled set the reset change flag */
+-00426                                 dwc_otg_hcd->flags.b.port_reset_change = 1;
+-00427                         }
+-00428                 } else {
+-00429                         dwc_otg_hcd->flags.b.port_enable_change = 1;
+-00430                 }
+-00431                 retval |= 1;
+-00432         }
+-00433 
+-00435         if (hprt0.b.prtovrcurrchng) {
+-00436                 DWC_DEBUGPL(DBG_HCD, "  --Port Interrupt HPRT0=0x%08x "
+-00437                             "Port Overcurrent Changed--\n", hprt0.d32);
+-00438                 dwc_otg_hcd->flags.b.port_over_current_change = 1;
+-00439                 hprt0_modify.b.prtovrcurrchng = 1;
+-00440                 retval |= 1;
+-00441         }
+-00442 
+-00443         /* Clear Port Interrupts */
+-00444         dwc_write_reg32(dwc_otg_hcd->core_if->host_if->hprt0, hprt0_modify.d32);
+-00445 
+-00446         return retval;
+-00447 }
+-00448 
+-00453 int32_t dwc_otg_hcd_handle_hc_intr(dwc_otg_hcd_t * dwc_otg_hcd)
+-00454 {
+-00455         int i;
+-00456         int retval = 0;
+-00457         haint_data_t haint;
+-00458 
+-00459         /* Clear appropriate bits in HCINTn to clear the interrupt bit in
+-00460          * GINTSTS */
+-00461 
+-00462         haint.d32 = dwc_otg_read_host_all_channels_intr(dwc_otg_hcd->core_if);
+-00463 
+-00464         for (i = 0; i < dwc_otg_hcd->core_if->core_params->host_channels; i++) {
+-00465                 if (haint.b2.chint & (1 << i)) {
+-00466                         retval |= dwc_otg_hcd_handle_hc_n_intr(dwc_otg_hcd, i);
+-00467                 }
+-00468         }
+-00469 
+-00470         return retval;
+-00471 }
+-00472 
+-00473 
+-00474 
+-00485 static uint32_t get_actual_xfer_length(dwc_hc_t * hc,
+-00486                                        dwc_otg_hc_regs_t * hc_regs,
+-00487                                        dwc_otg_qtd_t * qtd,
+-00488                                        dwc_otg_halt_status_e halt_status,
+-00489                                        int *short_read)
+-00490 {
+-00491         hctsiz_data_t hctsiz;
+-00492         uint32_t length;
+-00493 
+-00494         if (short_read != NULL) {
+-00495                 *short_read = 0;
+-00496         }
+-00497         hctsiz.d32 = dwc_read_reg32(&hc_regs->hctsiz);
+-00498 
+-00499         if (halt_status == DWC_OTG_HC_XFER_COMPLETE) {
+-00500                 if (hc->ep_is_in) {
+-00501                         length = hc->xfer_len - hctsiz.b.xfersize;
+-00502                         if (short_read != NULL) {
+-00503                                 *short_read = (hctsiz.b.xfersize != 0);
+-00504                         }
+-00505                 } else if (hc->qh->do_split) {
+-00506                         length = qtd->ssplit_out_xfer_count;
+-00507                 } else {
+-00508                         length = hc->xfer_len;
+-00509                 }
+-00510         } else {
+-00511                 /*
+-00512                  * Must use the hctsiz.pktcnt field to determine how much data
+-00513                  * has been transferred. This field reflects the number of
+-00514                  * packets that have been transferred via the USB. This is
+-00515                  * always an integral number of packets if the transfer was
+-00516                  * halted before its normal completion. (Can't use the
+-00517                  * hctsiz.xfersize field because that reflects the number of
+-00518                  * bytes transferred via the AHB, not the USB).
+-00519                  */
+-00520                 length =
+-00521                     (hc->start_pkt_count - hctsiz.b.pktcnt) * hc->max_packet;
+-00522         }
+-00523 
+-00524         return length;
+-00525 }
+-00526 
+-00536 static int update_urb_state_xfer_comp(dwc_hc_t * hc,
+-00537                                       dwc_otg_hc_regs_t * hc_regs,
+-00538                                       dwc_otg_hcd_urb_t * urb,
+-00539                                       dwc_otg_qtd_t * qtd)
+-00540 {
+-00541         int xfer_done = 0;
+-00542         int short_read = 0;
+-00543 
+-00544         int xfer_length;
+-00545 
+-00546         xfer_length = get_actual_xfer_length(hc, hc_regs, qtd,                                               
+-00547                                                      DWC_OTG_HC_XFER_COMPLETE,
+-00548                                                      &short_read);
+-00549 
+-00550 
+-00551         /* non DWORD-aligned buffer case handling. */
+-00552         if (hc->align_buff && xfer_length && hc->ep_is_in) {
+-00553                 dwc_memcpy(urb->buf + urb->actual_length, hc->qh->dw_align_buf, xfer_length);
+-00554         }
+-00555 
+-00556         urb->actual_length += xfer_length;
+-00557 
+-00558         if(xfer_length && (hc->ep_type == DWC_OTG_EP_TYPE_BULK) &&
+-00559            (urb->flags & URB_SEND_ZERO_PACKET) && (urb->actual_length == urb->length) &&
+-00560            !(urb->length % hc->max_packet)) {
+-00561                 xfer_done = 0;
+-00562         } else if (short_read || urb->actual_length == urb->length) {
+-00563                 xfer_done = 1;
+-00564                 urb->status = 0;
+-00565         }
+-00566         
+-00567 #ifdef DEBUG
+-00568         {
+-00569                 hctsiz_data_t hctsiz;
+-00570                 hctsiz.d32 = dwc_read_reg32(&hc_regs->hctsiz);
+-00571                 DWC_DEBUGPL(DBG_HCDV, "DWC_otg: %s: %s, channel %d\n",
+-00572                             __func__, (hc->ep_is_in ? "IN" : "OUT"),
+-00573                             hc->hc_num);
+-00574                 DWC_DEBUGPL(DBG_HCDV, "  hc->xfer_len %d\n", hc->xfer_len);
+-00575                 DWC_DEBUGPL(DBG_HCDV, "  hctsiz.xfersize %d\n",
+-00576                             hctsiz.b.xfersize);
+-00577                 DWC_DEBUGPL(DBG_HCDV, "  urb->transfer_buffer_length %d\n",
+-00578                             urb->length);
+-00579                 DWC_DEBUGPL(DBG_HCDV, "  urb->actual_length %d\n",
+-00580                             urb->actual_length);
+-00581                 DWC_DEBUGPL(DBG_HCDV, "  short_read %d, xfer_done %d\n",
+-00582                             short_read, xfer_done);
+-00583         }
+-00584 #endif
+-00585 
+-00586         return xfer_done;
+-00587 }
+-00588 
+-00589 /*
+-00590  * Save the starting data toggle for the next transfer. The data toggle is
+-00591  * saved in the QH for non-control transfers and it's saved in the QTD for
+-00592  * control transfers.
+-00593  */
+-00594 void dwc_otg_hcd_save_data_toggle(dwc_hc_t * hc,
+-00595                              dwc_otg_hc_regs_t * hc_regs, dwc_otg_qtd_t * qtd)
+-00596 {
+-00597         hctsiz_data_t hctsiz;
+-00598         hctsiz.d32 = dwc_read_reg32(&hc_regs->hctsiz);
+-00599 
+-00600         if (hc->ep_type != DWC_OTG_EP_TYPE_CONTROL) {
+-00601                 dwc_otg_qh_t *qh = hc->qh;
+-00602                 if (hctsiz.b.pid == DWC_HCTSIZ_DATA0) {
+-00603                         qh->data_toggle = DWC_OTG_HC_PID_DATA0;
+-00604                 } else {
+-00605                         qh->data_toggle = DWC_OTG_HC_PID_DATA1;
+-00606                 }
+-00607         } else {
+-00608                 if (hctsiz.b.pid == DWC_HCTSIZ_DATA0) {
+-00609                         qtd->data_toggle = DWC_OTG_HC_PID_DATA0;
+-00610                 } else {
+-00611                         qtd->data_toggle = DWC_OTG_HC_PID_DATA1;
+-00612                 }
+-00613         }
+-00614 }
+-00615 
+-00625 static dwc_otg_halt_status_e
+-00626 update_isoc_urb_state(dwc_otg_hcd_t * hcd,
+-00627                       dwc_hc_t * hc,
+-00628                       dwc_otg_hc_regs_t * hc_regs,
+-00629                       dwc_otg_qtd_t * qtd, dwc_otg_halt_status_e halt_status)
+-00630 {
+-00631         dwc_otg_hcd_urb_t *urb = qtd->urb;
+-00632         dwc_otg_halt_status_e ret_val = halt_status;
+-00633         struct dwc_otg_hcd_iso_packet_desc *frame_desc;
+-00634 
+-00635         frame_desc = &urb->iso_descs[qtd->isoc_frame_index];
+-00636         switch (halt_status) {
+-00637         case DWC_OTG_HC_XFER_COMPLETE:
+-00638                 frame_desc->status = 0;
+-00639                 frame_desc->actual_length =
+-00640                     get_actual_xfer_length(hc, hc_regs, qtd, halt_status, NULL);
+-00641                     
+-00642                 /* non DWORD-aligned buffer case handling. */
+-00643                 if (hc->align_buff && frame_desc->actual_length && hc->ep_is_in) {
+-00644                         dwc_memcpy(urb->buf + frame_desc->offset + qtd->isoc_split_offset, 
+-00645                                    hc->qh->dw_align_buf, frame_desc->actual_length);
+-00646                 }
+-00647                 
+-00648                 break;
+-00649         case DWC_OTG_HC_XFER_FRAME_OVERRUN:
+-00650                 urb->error_count++;
+-00651                 if (hc->ep_is_in) {
+-00652                         frame_desc->status = -DWC_E_NO_STREAM_RES;
+-00653                 } else {
+-00654                         frame_desc->status = -DWC_E_COMMUNICATION;
+-00655                 }
+-00656                 frame_desc->actual_length = 0;
+-00657                 break;
+-00658         case DWC_OTG_HC_XFER_BABBLE_ERR:
+-00659                 urb->error_count++;
+-00660                 frame_desc->status = -DWC_E_OVERFLOW;
+-00661                 /* Don't need to update actual_length in this case. */
+-00662                 break;
+-00663         case DWC_OTG_HC_XFER_XACT_ERR:
+-00664                 urb->error_count++;
+-00665                 frame_desc->status = -DWC_E_PROTOCOL;
+-00666                 frame_desc->actual_length =
+-00667                     get_actual_xfer_length(hc, hc_regs, qtd, halt_status, NULL);
+-00668                 
+-00669                 /* non DWORD-aligned buffer case handling. */
+-00670                 if (hc->align_buff && frame_desc->actual_length && hc->ep_is_in) {
+-00671                         dwc_memcpy(urb->buf + frame_desc->offset + qtd->isoc_split_offset, 
+-00672                                    hc->qh->dw_align_buf, frame_desc->actual_length);
+-00673                 }
+-00674                 /* Skip whole frame */
+-00675                 if (hc->qh->do_split && (hc->ep_type == DWC_OTG_EP_TYPE_ISOC) && 
+-00676                                 hc->ep_is_in && hcd->core_if->dma_enable) {
+-00677                         qtd->complete_split = 0;
+-00678                         qtd->isoc_split_offset = 0;
+-00679                 }
+-00680                         
+-00681                 break;
+-00682         default:
+-00683                 DWC_ASSERT(1, "Unhandled _halt_status (%d)\n", halt_status);
+-00684                 break;
+-00685         }
+-00686         if (++qtd->isoc_frame_index == urb->packet_count) {
+-00687                 /*
+-00688                  * urb->status is not used for isoc transfers.
+-00689                  * The individual frame_desc statuses are used instead.
+-00690                  */
+-00691                 hcd->fops->complete(hcd, urb->priv, urb, 0);
+-00692                 ret_val = DWC_OTG_HC_XFER_URB_COMPLETE;
+-00693         } else {
+-00694                 ret_val = DWC_OTG_HC_XFER_COMPLETE;
+-00695         }
+-00696         return ret_val;
+-00697 }
+-00698 
+-00706 static void deactivate_qh(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh, int free_qtd)
+-00707 {
+-00708         int continue_split = 0;
+-00709         dwc_otg_qtd_t *qtd;
+-00710 
+-00711         DWC_DEBUGPL(DBG_HCDV, "  %s(%p,%p,%d)\n", __func__, hcd, qh, free_qtd);
+-00712 
+-00713         qtd = DWC_CIRCLEQ_FIRST(&qh->qtd_list);
+-00714 
+-00715         if (qtd->complete_split) {
+-00716                 continue_split = 1;
+-00717         } else if (qtd->isoc_split_pos == DWC_HCSPLIT_XACTPOS_MID ||
+-00718                    qtd->isoc_split_pos == DWC_HCSPLIT_XACTPOS_END) {
+-00719                 continue_split = 1;
+-00720         }
+-00721 
+-00722         if (free_qtd) {
+-00723                 dwc_otg_hcd_qtd_remove_and_free(hcd, qtd, qh);
+-00724                 continue_split = 0;
+-00725         }
+-00726 
+-00727         qh->channel = NULL;
+-00728         dwc_otg_hcd_qh_deactivate(hcd, qh, continue_split);
+-00729 }
+-00730 
+-00742 static void release_channel(dwc_otg_hcd_t * hcd,
+-00743                             dwc_hc_t * hc,
+-00744                             dwc_otg_qtd_t * qtd,
+-00745                             dwc_otg_halt_status_e halt_status)
+-00746 {
+-00747         dwc_otg_transaction_type_e tr_type;
+-00748         int free_qtd;
+-00749 
+-00750         DWC_DEBUGPL(DBG_HCDV, "  %s: channel %d, halt_status %d\n",
+-00751                     __func__, hc->hc_num, halt_status);
+-00752 
+-00753         switch (halt_status) {
+-00754         case DWC_OTG_HC_XFER_URB_COMPLETE:
+-00755                 free_qtd = 1;
+-00756                 break;
+-00757         case DWC_OTG_HC_XFER_AHB_ERR:
+-00758         case DWC_OTG_HC_XFER_STALL:
+-00759         case DWC_OTG_HC_XFER_BABBLE_ERR:
+-00760                 free_qtd = 1;
+-00761                 break;
+-00762         case DWC_OTG_HC_XFER_XACT_ERR:
+-00763                 if (qtd->error_count >= 3) {
+-00764                         DWC_DEBUGPL(DBG_HCDV,
+-00765                                     "  Complete URB with transaction error\n");
+-00766                         free_qtd = 1;
+-00767                         qtd->urb->status = -DWC_E_PROTOCOL;
+-00768                         hcd->fops->complete(hcd, qtd->urb->priv,
+-00769                                             qtd->urb, -DWC_E_PROTOCOL);
+-00770                 } else {
+-00771                         free_qtd = 0;
+-00772                 }
+-00773                 break;
+-00774         case DWC_OTG_HC_XFER_URB_DEQUEUE:
+-00775                 /*
+-00776                  * The QTD has already been removed and the QH has been
+-00777                  * deactivated. Don't want to do anything except release the
+-00778                  * host channel and try to queue more transfers.
+-00779                  */
+-00780                 goto cleanup;
+-00781         case DWC_OTG_HC_XFER_NO_HALT_STATUS:
+-00782                 free_qtd = 0;
+-00783                 break;
+-00784         default:
+-00785                 free_qtd = 0;
+-00786                 break;
+-00787         }
+-00788 
+-00789         deactivate_qh(hcd, hc->qh, free_qtd);
+-00790 
+-00791       cleanup:
+-00792         /*
+-00793          * Release the host channel for use by other transfers. The cleanup
+-00794          * function clears the channel interrupt enables and conditions, so
+-00795          * there's no need to clear the Channel Halted interrupt separately.
+-00796          */
+-00797         dwc_otg_hc_cleanup(hcd->core_if, hc);
+-00798         DWC_CIRCLEQ_INSERT_TAIL(&hcd->free_hc_list, hc, hc_list_entry);
+-00799 
+-00800         switch (hc->ep_type) {
+-00801         case DWC_OTG_EP_TYPE_CONTROL:
+-00802         case DWC_OTG_EP_TYPE_BULK:
+-00803                 hcd->non_periodic_channels--;
+-00804                 break;
+-00805 
+-00806         default:
+-00807                 /*
+-00808                  * Don't release reservations for periodic channels here.
+-00809                  * That's done when a periodic transfer is descheduled (i.e.
+-00810                  * when the QH is removed from the periodic schedule).
+-00811                  */
+-00812                 break;
+-00813         }
+-00814 
+-00815         /* Try to queue more transfers now that there's a free channel. */
+-00816         tr_type = dwc_otg_hcd_select_transactions(hcd);
+-00817         if (tr_type != DWC_OTG_TRANSACTION_NONE) {
+-00818                 dwc_otg_hcd_queue_transactions(hcd, tr_type);
+-00819         }
+-00820 }
+-00821 
+-00822 
+-00833 static void halt_channel(dwc_otg_hcd_t * hcd,
+-00834                          dwc_hc_t * hc,
+-00835                          dwc_otg_qtd_t * qtd, dwc_otg_halt_status_e halt_status)
+-00836 {
+-00837         if (hcd->core_if->dma_enable) {
+-00838                 release_channel(hcd, hc, qtd, halt_status);
+-00839                 return;
+-00840         }
+-00841 
+-00842         /* Slave mode processing... */
+-00843         dwc_otg_hc_halt(hcd->core_if, hc, halt_status);
+-00844 
+-00845         if (hc->halt_on_queue) {
+-00846                 gintmsk_data_t gintmsk = {.d32 = 0 };
+-00847                 dwc_otg_core_global_regs_t *global_regs;
+-00848                 global_regs = hcd->core_if->core_global_regs;
+-00849 
+-00850                 if (hc->ep_type == DWC_OTG_EP_TYPE_CONTROL ||
+-00851                     hc->ep_type == DWC_OTG_EP_TYPE_BULK) {
+-00852                         /*
+-00853                          * Make sure the Non-periodic Tx FIFO empty interrupt
+-00854                          * is enabled so that the non-periodic schedule will
+-00855                          * be processed.
+-00856                          */
+-00857                         gintmsk.b.nptxfempty = 1;
+-00858                         dwc_modify_reg32(&global_regs->gintmsk, 0, gintmsk.d32);
+-00859                 } else {
+-00860                         /*
+-00861                          * Move the QH from the periodic queued schedule to
+-00862                          * the periodic assigned schedule. This allows the
+-00863                          * halt to be queued when the periodic schedule is
+-00864                          * processed.
+-00865                          */
+-00866                         DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_assigned,
+-00867                                            &hc->qh->qh_list_entry);
+-00868 
+-00869                         /*
+-00870                          * Make sure the Periodic Tx FIFO Empty interrupt is
+-00871                          * enabled so that the periodic schedule will be
+-00872                          * processed.
+-00873                          */
+-00874                         gintmsk.b.ptxfempty = 1;
+-00875                         dwc_modify_reg32(&global_regs->gintmsk, 0, gintmsk.d32);
+-00876                 }
+-00877         }
+-00878 }
+-00879 
+-00885 static void complete_non_periodic_xfer(dwc_otg_hcd_t * hcd,
+-00886                                        dwc_hc_t * hc,
+-00887                                        dwc_otg_hc_regs_t * hc_regs,
+-00888                                        dwc_otg_qtd_t * qtd,
+-00889                                        dwc_otg_halt_status_e halt_status)
+-00890 {
+-00891         hcint_data_t hcint;
+-00892 
+-00893         qtd->error_count = 0;
+-00894 
+-00895         hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
+-00896         if (hcint.b.nyet) {
+-00897                 /*
+-00898                  * Got a NYET on the last transaction of the transfer. This
+-00899                  * means that the endpoint should be in the PING state at the
+-00900                  * beginning of the next transfer.
+-00901                  */
+-00902                 hc->qh->ping_state = 1;
+-00903                 clear_hc_int(hc_regs, nyet);
+-00904         }
+-00905 
+-00906         /*
+-00907          * Always halt and release the host channel to make it available for
+-00908          * more transfers. There may still be more phases for a control
+-00909          * transfer or more data packets for a bulk transfer at this point,
+-00910          * but the host channel is still halted. A channel will be reassigned
+-00911          * to the transfer when the non-periodic schedule is processed after
+-00912          * the channel is released. This allows transactions to be queued
+-00913          * properly via dwc_otg_hcd_queue_transactions, which also enables the
+-00914          * Tx FIFO Empty interrupt if necessary.
+-00915          */
+-00916         if (hc->ep_is_in) {
+-00917                 /*
+-00918                  * IN transfers in Slave mode require an explicit disable to
+-00919                  * halt the channel. (In DMA mode, this call simply releases
+-00920                  * the channel.)
+-00921                  */
+-00922                 halt_channel(hcd, hc, qtd, halt_status);
+-00923         } else {
+-00924                 /*
+-00925                  * The channel is automatically disabled by the core for OUT
+-00926                  * transfers in Slave mode.
+-00927                  */
+-00928                 release_channel(hcd, hc, qtd, halt_status);
+-00929         }
+-00930 }
+-00931 
+-00937 static void complete_periodic_xfer(dwc_otg_hcd_t * hcd,
+-00938                                    dwc_hc_t * hc,
+-00939                                    dwc_otg_hc_regs_t * hc_regs,
+-00940                                    dwc_otg_qtd_t * qtd,
+-00941                                    dwc_otg_halt_status_e halt_status)
+-00942 {
+-00943         hctsiz_data_t hctsiz;
+-00944         qtd->error_count = 0;
+-00945 
+-00946         hctsiz.d32 = dwc_read_reg32(&hc_regs->hctsiz);
+-00947         if (!hc->ep_is_in || hctsiz.b.pktcnt == 0) {
+-00948                 /* Core halts channel in these cases. */
+-00949                 release_channel(hcd, hc, qtd, halt_status);
+-00950         } else {
+-00951                 /* Flush any outstanding requests from the Tx queue. */
+-00952                 halt_channel(hcd, hc, qtd, halt_status);
+-00953         }
+-00954 }
+-00955 
+-00956 static int32_t handle_xfercomp_isoc_split_in(dwc_otg_hcd_t * hcd,
+-00957                                              dwc_hc_t * hc,
+-00958                                              dwc_otg_hc_regs_t * hc_regs,
+-00959                                              dwc_otg_qtd_t * qtd)
+-00960 {
+-00961         uint32_t len;   
+-00962         struct dwc_otg_hcd_iso_packet_desc *frame_desc;
+-00963         frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index];
+-00964                                 
+-00965         len = get_actual_xfer_length(hc, hc_regs, qtd,
+-00966                                      DWC_OTG_HC_XFER_COMPLETE,
+-00967                                      NULL);
+-00968                      
+-00969         if (!len) {
+-00970                 qtd->complete_split = 0;
+-00971                 qtd->isoc_split_offset = 0;
+-00972                 return 0;
+-00973         }
+-00974         frame_desc->actual_length += len;
+-00975         
+-00976         if (hc->align_buff && len)
+-00977                 dwc_memcpy(qtd->urb->buf + frame_desc->offset + qtd->isoc_split_offset, 
+-00978                                                                 hc->qh->dw_align_buf, 
+-00979                                                                 len);
+-00980         qtd->isoc_split_offset += len;
+-00981         
+-00982         if (frame_desc->length == frame_desc->actual_length) {
+-00983                 frame_desc->status = 0;
+-00984                 qtd->isoc_frame_index++;
+-00985                 qtd->complete_split = 0;
+-00986                 qtd->isoc_split_offset = 0;
+-00987         }
+-00988                         
+-00989         if (qtd->isoc_frame_index == qtd->urb->packet_count) {
+-00990                 hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, 0);
+-00991                 release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE);
+-00992         } else {
+-00993                 release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NO_HALT_STATUS);
+-00994         }
+-00995         
+-00996         return 1; /* Indicates that channel released */
+-00997 }
+-01002 static int32_t handle_hc_xfercomp_intr(dwc_otg_hcd_t * hcd,
+-01003                                        dwc_hc_t * hc,
+-01004                                        dwc_otg_hc_regs_t * hc_regs,
+-01005                                        dwc_otg_qtd_t * qtd)
+-01006 {
+-01007         int urb_xfer_done;
+-01008         dwc_otg_halt_status_e halt_status = DWC_OTG_HC_XFER_COMPLETE;
+-01009         dwc_otg_hcd_urb_t *urb = qtd->urb;
+-01010         int pipe_type = dwc_otg_hcd_get_pipe_type(&urb->pipe_info);
+-01011 
+-01012         DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
+-01013                     "Transfer Complete--\n", hc->hc_num);
+-01014 
+-01015         if (hcd->core_if->dma_desc_enable) {
+-01016                 dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs, halt_status);
+-01017                 if (pipe_type == UE_ISOCHRONOUS) {
+-01018                         /* Do not disable the interrupt, just clear it */       
+-01019                         clear_hc_int(hc_regs, xfercomp);
+-01020                         return 1;
+-01021                 }
+-01022                 goto handle_xfercomp_done;
+-01023         }
+-01024 
+-01025         /*
+-01026          * Handle xfer complete on CSPLIT.
+-01027          */
+-01028 
+-01029         if (hc->qh->do_split) {
+-01030                 if ((hc->ep_type == DWC_OTG_EP_TYPE_ISOC) && hc->ep_is_in && hcd->core_if->dma_enable) {
+-01031                         if (qtd->complete_split && handle_xfercomp_isoc_split_in(hcd, hc, hc_regs, qtd))
+-01032                                 goto handle_xfercomp_done;
+-01033                 }
+-01034                 else {
+-01035                 qtd->complete_split = 0;
+-01036         }
+-01037         }       
+-01038 
+-01039         /* Update the QTD and URB states. */
+-01040         switch (pipe_type) {
+-01041         case UE_CONTROL:
+-01042                 switch (qtd->control_phase) {
+-01043                 case DWC_OTG_CONTROL_SETUP:
+-01044                         if (urb->length > 0) {
+-01045                                 qtd->control_phase = DWC_OTG_CONTROL_DATA;
+-01046                         } else {
+-01047                                 qtd->control_phase = DWC_OTG_CONTROL_STATUS;
+-01048                         }
+-01049                         DWC_DEBUGPL(DBG_HCDV,
+-01050                                     "  Control setup transaction done\n");
+-01051                         halt_status = DWC_OTG_HC_XFER_COMPLETE;
+-01052                         break;
+-01053                 case DWC_OTG_CONTROL_DATA:{
+-01054                                 urb_xfer_done =
+-01055                                     update_urb_state_xfer_comp(hc, hc_regs, urb,
+-01056                                                                qtd);
+-01057                                 if (urb_xfer_done) {
+-01058                                         qtd->control_phase =
+-01059                                             DWC_OTG_CONTROL_STATUS;
+-01060                                         DWC_DEBUGPL(DBG_HCDV,
+-01061                                                     "  Control data transfer done\n");
+-01062                                 } else {
+-01063                                         dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
+-01064                                 }
+-01065                                 halt_status = DWC_OTG_HC_XFER_COMPLETE;
+-01066                                 break;
+-01067                         }
+-01068                 case DWC_OTG_CONTROL_STATUS:
+-01069                         DWC_DEBUGPL(DBG_HCDV, "  Control transfer complete\n");
+-01070                         if (urb->status == -DWC_E_IN_PROGRESS) {
+-01071                                 urb->status = 0;
+-01072                         }
+-01073                         hcd->fops->complete(hcd, urb->priv, urb, urb->status);
+-01074                         halt_status = DWC_OTG_HC_XFER_URB_COMPLETE;
+-01075                         break;
+-01076                 }
+-01077 
+-01078                 complete_non_periodic_xfer(hcd, hc, hc_regs, qtd, halt_status);
+-01079                 break;
+-01080         case UE_BULK:
+-01081                 DWC_DEBUGPL(DBG_HCDV, "  Bulk transfer complete\n");
+-01082                 urb_xfer_done =
+-01083                     update_urb_state_xfer_comp(hc, hc_regs, urb, qtd);
+-01084                 if (urb_xfer_done) {
+-01085                         hcd->fops->complete(hcd, urb->priv, urb, urb->status);
+-01086                         halt_status = DWC_OTG_HC_XFER_URB_COMPLETE;
+-01087                 } else {
+-01088                         halt_status = DWC_OTG_HC_XFER_COMPLETE;
+-01089                 }
+-01090 
+-01091                 dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
+-01092                 complete_non_periodic_xfer(hcd, hc, hc_regs, qtd, halt_status);
+-01093                 break;
+-01094         case UE_INTERRUPT:
+-01095                 DWC_DEBUGPL(DBG_HCDV, "  Interrupt transfer complete\n");
+-01096                 update_urb_state_xfer_comp(hc, hc_regs, urb, qtd);
+-01097 
+-01098                 /*
+-01099                  * Interrupt URB is done on the first transfer complete
+-01100                  * interrupt.
+-01101                  */
+-01102                 hcd->fops->complete(hcd, urb->priv, urb, urb->status);
+-01103                 dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
+-01104                 complete_periodic_xfer(hcd, hc, hc_regs, qtd,
+-01105                                        DWC_OTG_HC_XFER_URB_COMPLETE);
+-01106                 break;
+-01107         case UE_ISOCHRONOUS:
+-01108                 DWC_DEBUGPL(DBG_HCDV, "  Isochronous transfer complete\n");
+-01109                 if (qtd->isoc_split_pos == DWC_HCSPLIT_XACTPOS_ALL) {
+-01110                         halt_status =
+-01111                             update_isoc_urb_state(hcd, hc, hc_regs, qtd,
+-01112                                                   DWC_OTG_HC_XFER_COMPLETE);
+-01113                 }
+-01114                 complete_periodic_xfer(hcd, hc, hc_regs, qtd, halt_status);
+-01115                 break;
+-01116         }
+-01117 
+-01118 handle_xfercomp_done:
+-01119         disable_hc_int(hc_regs, xfercompl);
+-01120 
+-01121         return 1;
+-01122 }
+-01123 
+-01128 static int32_t handle_hc_stall_intr(dwc_otg_hcd_t * hcd,
+-01129                                     dwc_hc_t * hc,
+-01130                                     dwc_otg_hc_regs_t * hc_regs,
+-01131                                     dwc_otg_qtd_t * qtd)
+-01132 {
+-01133         dwc_otg_hcd_urb_t *urb = qtd->urb;
+-01134         int pipe_type = dwc_otg_hcd_get_pipe_type(&urb->pipe_info);
+-01135 
+-01136         DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
+-01137                     "STALL Received--\n", hc->hc_num);
+-01138 
+-01139         if (hcd->core_if->dma_desc_enable) {
+-01140                 dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs, DWC_OTG_HC_XFER_STALL);
+-01141                 goto handle_stall_done;
+-01142         }
+-01143 
+-01144         if (pipe_type == UE_CONTROL) {
+-01145                 hcd->fops->complete(hcd, urb->priv, urb, -DWC_E_PIPE);
+-01146         }
+-01147 
+-01148         if (pipe_type == UE_BULK || pipe_type == UE_INTERRUPT) {
+-01149                 hcd->fops->complete(hcd, urb->priv, urb, -DWC_E_PIPE);
+-01150                 /*
+-01151                  * USB protocol requires resetting the data toggle for bulk
+-01152                  * and interrupt endpoints when a CLEAR_FEATURE(ENDPOINT_HALT)
+-01153                  * setup command is issued to the endpoint. Anticipate the
+-01154                  * CLEAR_FEATURE command since a STALL has occurred and reset
+-01155                  * the data toggle now.
+-01156                  */
+-01157                 hc->qh->data_toggle = 0;
+-01158         }
+-01159 
+-01160         halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_STALL);
+-01161 
+-01162 handle_stall_done:
+-01163         disable_hc_int(hc_regs, stall);
+-01164 
+-01165         return 1;
+-01166 }
+-01167 
+-01168 /*
+-01169  * Updates the state of the URB when a transfer has been stopped due to an
+-01170  * abnormal condition before the transfer completes. Modifies the
+-01171  * actual_length field of the URB to reflect the number of bytes that have
+-01172  * actually been transferred via the host channel.
+-01173  */
+-01174 static void update_urb_state_xfer_intr(dwc_hc_t * hc,
+-01175                                        dwc_otg_hc_regs_t * hc_regs,
+-01176                                        dwc_otg_hcd_urb_t * urb,
+-01177                                        dwc_otg_qtd_t * qtd,
+-01178                                        dwc_otg_halt_status_e halt_status)
+-01179 {
+-01180         uint32_t bytes_transferred = get_actual_xfer_length(hc, hc_regs, qtd,
+-01181                                                             halt_status, NULL);
+-01182         /* non DWORD-aligned buffer case handling. */
+-01183         if (hc->align_buff && bytes_transferred && hc->ep_is_in) {
+-01184                 dwc_memcpy(urb->buf + urb->actual_length, hc->qh->dw_align_buf, bytes_transferred);
+-01185         }
+-01186         
+-01187         urb->actual_length += bytes_transferred;
+-01188 
+-01189 #ifdef DEBUG
+-01190         {
+-01191                 hctsiz_data_t hctsiz;
+-01192                 hctsiz.d32 = dwc_read_reg32(&hc_regs->hctsiz);
+-01193                 DWC_DEBUGPL(DBG_HCDV, "DWC_otg: %s: %s, channel %d\n",
+-01194                             __func__, (hc->ep_is_in ? "IN" : "OUT"),
+-01195                             hc->hc_num);
+-01196                 DWC_DEBUGPL(DBG_HCDV, "  hc->start_pkt_count %d\n",
+-01197                             hc->start_pkt_count);
+-01198                 DWC_DEBUGPL(DBG_HCDV, "  hctsiz.pktcnt %d\n", hctsiz.b.pktcnt);
+-01199                 DWC_DEBUGPL(DBG_HCDV, "  hc->max_packet %d\n", hc->max_packet);
+-01200                 DWC_DEBUGPL(DBG_HCDV, "  bytes_transferred %d\n",
+-01201                             bytes_transferred);
+-01202                 DWC_DEBUGPL(DBG_HCDV, "  urb->actual_length %d\n",
+-01203                             urb->actual_length);
+-01204                 DWC_DEBUGPL(DBG_HCDV, "  urb->transfer_buffer_length %d\n",
+-01205                             urb->length);
+-01206         }
+-01207 #endif
+-01208 }
+-01209 
+-01214 static int32_t handle_hc_nak_intr(dwc_otg_hcd_t * hcd,
+-01215                                   dwc_hc_t * hc,
+-01216                                   dwc_otg_hc_regs_t * hc_regs,
+-01217                                   dwc_otg_qtd_t * qtd)
+-01218 {
+-01219         DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
+-01220                     "NAK Received--\n", hc->hc_num);
+-01221 
+-01222         /*
+-01223          * Handle NAK for IN/OUT SSPLIT/CSPLIT transfers, bulk, control, and
+-01224          * interrupt.  Re-start the SSPLIT transfer.
+-01225          */
+-01226         if (hc->do_split) {
+-01227                 if (hc->complete_split) {
+-01228                         qtd->error_count = 0;
+-01229                 }
+-01230                 qtd->complete_split = 0;
+-01231                 halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NAK);
+-01232                 goto handle_nak_done;
+-01233         }
+-01234 
+-01235         switch (dwc_otg_hcd_get_pipe_type(&qtd->urb->pipe_info)) {
+-01236         case UE_CONTROL:
+-01237         case UE_BULK:
+-01238                 if (hcd->core_if->dma_enable && hc->ep_is_in) {
+-01239                         /*
+-01240                          * NAK interrupts are enabled on bulk/control IN
+-01241                          * transfers in DMA mode for the sole purpose of
+-01242                          * resetting the error count after a transaction error
+-01243                          * occurs. The core will continue transferring data.
+-01244                          */
+-01245                         qtd->error_count = 0;
+-01246                         goto handle_nak_done;
+-01247                 }
+-01248 
+-01249                 /*
+-01250                  * NAK interrupts normally occur during OUT transfers in DMA
+-01251                  * or Slave mode. For IN transfers, more requests will be
+-01252                  * queued as request queue space is available.
+-01253                  */
+-01254                 qtd->error_count = 0;
+-01255 
+-01256                 if (!hc->qh->ping_state) {
+-01257                         update_urb_state_xfer_intr(hc, hc_regs,
+-01258                                                    qtd->urb, qtd,
+-01259                                                    DWC_OTG_HC_XFER_NAK);
+-01260                         dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
+-01261 
+-01262                         if (hc->speed == DWC_OTG_EP_SPEED_HIGH)
+-01263                                 hc->qh->ping_state = 1;
+-01264                         }
+-01265 
+-01266                 /*
+-01267                  * Halt the channel so the transfer can be re-started from
+-01268                  * the appropriate point or the PING protocol will
+-01269                  * start/continue.
+-01270                  */
+-01271                 halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NAK);
+-01272                 break;
+-01273         case UE_INTERRUPT:
+-01274                 qtd->error_count = 0;
+-01275                 halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NAK);
+-01276                 break;
+-01277         case UE_ISOCHRONOUS:
+-01278                 /* Should never get called for isochronous transfers. */
+-01279                 DWC_ASSERT(1, "NACK interrupt for ISOC transfer\n");
+-01280                 break;
+-01281         }
+-01282 
+-01283       handle_nak_done:
+-01284         disable_hc_int(hc_regs, nak);
+-01285 
+-01286         return 1;
+-01287 }
+-01288 
+-01294 static int32_t handle_hc_ack_intr(dwc_otg_hcd_t * hcd,
+-01295                                   dwc_hc_t * hc,
+-01296                                   dwc_otg_hc_regs_t * hc_regs,
+-01297                                   dwc_otg_qtd_t * qtd)
+-01298 {
+-01299         DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
+-01300                     "ACK Received--\n", hc->hc_num);
+-01301 
+-01302         if (hc->do_split) {
+-01303                 /*
+-01304                  * Handle ACK on SSPLIT.
+-01305                  * ACK should not occur in CSPLIT.
+-01306                  */
+-01307                 if (!hc->ep_is_in && hc->data_pid_start != DWC_OTG_HC_PID_SETUP) {
+-01308                         qtd->ssplit_out_xfer_count = hc->xfer_len;
+-01309                 }
+-01310                 if (!(hc->ep_type == DWC_OTG_EP_TYPE_ISOC && !hc->ep_is_in)) {
+-01311                         /* Don't need complete for isochronous out transfers. */
+-01312                         qtd->complete_split = 1;
+-01313                 }
+-01314 
+-01315                 /* ISOC OUT */
+-01316                 if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC && !hc->ep_is_in) {
+-01317                         switch (hc->xact_pos) {
+-01318                         case DWC_HCSPLIT_XACTPOS_ALL:
+-01319                                 break;
+-01320                         case DWC_HCSPLIT_XACTPOS_END:
+-01321                                 qtd->isoc_split_pos = DWC_HCSPLIT_XACTPOS_ALL;
+-01322                                 qtd->isoc_split_offset = 0;
+-01323                                 break;
+-01324                         case DWC_HCSPLIT_XACTPOS_BEGIN:
+-01325                         case DWC_HCSPLIT_XACTPOS_MID:
+-01326                                 /*
+-01327                                  * For BEGIN or MID, calculate the length for
+-01328                                  * the next microframe to determine the correct
+-01329                                  * SSPLIT token, either MID or END.
+-01330                                  */
+-01331                                 {
+-01332                                         struct dwc_otg_hcd_iso_packet_desc
+-01333                                             *frame_desc;
+-01334 
+-01335                                         frame_desc =
+-01336                                             &qtd->urb->iso_descs[qtd->
+-01337                                                                          isoc_frame_index];
+-01338                                         qtd->isoc_split_offset += 188;
+-01339 
+-01340                                         if ((frame_desc->length -
+-01341                                              qtd->isoc_split_offset) <= 188) {
+-01342                                                 qtd->isoc_split_pos =
+-01343                                                     DWC_HCSPLIT_XACTPOS_END;
+-01344                                         } else {
+-01345                                                 qtd->isoc_split_pos =
+-01346                                                     DWC_HCSPLIT_XACTPOS_MID;
+-01347                                         }
+-01348 
+-01349                                 }
+-01350                                 break;
+-01351                         }
+-01352                 } else {
+-01353                         halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_ACK);
+-01354                 }
+-01355         } else {
+-01356                 qtd->error_count = 0;
+-01357 
+-01358                 if (hc->qh->ping_state) {
+-01359                         hc->qh->ping_state = 0;
+-01360                         /*
+-01361                          * Halt the channel so the transfer can be re-started
+-01362                          * from the appropriate point. This only happens in
+-01363                          * Slave mode. In DMA mode, the ping_state is cleared
+-01364                          * when the transfer is started because the core
+-01365                          * automatically executes the PING, then the transfer.
+-01366                          */
+-01367                         halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_ACK);
+-01368                 }
+-01369         }
+-01370 
+-01371         /*
+-01372          * If the ACK occurred when _not_ in the PING state, let the channel
+-01373          * continue transferring data after clearing the error count.
+-01374          */
+-01375 
+-01376         disable_hc_int(hc_regs, ack);
+-01377 
+-01378         return 1;
+-01379 }
+-01380 
+-01388 static int32_t handle_hc_nyet_intr(dwc_otg_hcd_t * hcd,
+-01389                                    dwc_hc_t * hc,
+-01390                                    dwc_otg_hc_regs_t * hc_regs,
+-01391                                    dwc_otg_qtd_t * qtd)
+-01392 {
+-01393         DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
+-01394                     "NYET Received--\n", hc->hc_num);
+-01395 
+-01396         /*
+-01397          * NYET on CSPLIT
+-01398          * re-do the CSPLIT immediately on non-periodic
+-01399          */
+-01400         if (hc->do_split && hc->complete_split) {
+-01401                 if (hc->ep_is_in && (hc->ep_type == DWC_OTG_EP_TYPE_ISOC) && hcd->core_if->dma_enable) {        
+-01402                         qtd->complete_split = 0;
+-01403                         qtd->isoc_split_offset = 0;
+-01404                         if (++qtd->isoc_frame_index == qtd->urb->packet_count) {
+-01405                                 hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, 0);
+-01406                                 release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE);    
+-01407                         }
+-01408                         else
+-01409                                 release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NO_HALT_STATUS);  
+-01410                         goto handle_nyet_done;
+-01411                 }
+-01412                 
+-01413                 if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
+-01414                     hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
+-01415                         int frnum = dwc_otg_hcd_get_frame_number(hcd);
+-01416 
+-01417                         if (dwc_full_frame_num(frnum) !=
+-01418                             dwc_full_frame_num(hc->qh->sched_frame)) {
+-01419                                 /*
+-01420                                  * No longer in the same full speed frame.
+-01421                                  * Treat this as a transaction error.
+-01422                                  */
+-01423 #if 0
+-01424 
+-01430                                 qtd->error_count++;
+-01431 #endif
+-01432                                 qtd->complete_split = 0;
+-01433                                 halt_channel(hcd, hc, qtd,
+-01434                                              DWC_OTG_HC_XFER_XACT_ERR);
+-01436                                 goto handle_nyet_done;
+-01437                         }
+-01438                 }
+-01439 
+-01440                 halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NYET);
+-01441                 goto handle_nyet_done;
+-01442         }
+-01443 
+-01444         hc->qh->ping_state = 1;
+-01445         qtd->error_count = 0;
+-01446 
+-01447         update_urb_state_xfer_intr(hc, hc_regs, qtd->urb, qtd,
+-01448                                    DWC_OTG_HC_XFER_NYET);
+-01449         dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
+-01450 
+-01451         /*
+-01452          * Halt the channel and re-start the transfer so the PING
+-01453          * protocol will start.
+-01454          */
+-01455         halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NYET);
+-01456 
+-01457       handle_nyet_done:
+-01458         disable_hc_int(hc_regs, nyet);
+-01459         return 1;
+-01460 }
+-01461 
+-01466 static int32_t handle_hc_babble_intr(dwc_otg_hcd_t * hcd,
+-01467                                      dwc_hc_t * hc,
+-01468                                      dwc_otg_hc_regs_t * hc_regs,
+-01469                                      dwc_otg_qtd_t * qtd)
+-01470 {
+-01471         DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
+-01472                     "Babble Error--\n", hc->hc_num);
+-01473         
+-01474         if (hcd->core_if->dma_desc_enable) {
+-01475                 dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs, DWC_OTG_HC_XFER_BABBLE_ERR);
+-01476                 goto handle_babble_done;
+-01477         }
+-01478 
+-01479         if (hc->ep_type != DWC_OTG_EP_TYPE_ISOC) {
+-01480                 hcd->fops->complete(hcd, qtd->urb->priv,
+-01481                                     qtd->urb, -DWC_E_OVERFLOW);
+-01482                 halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_BABBLE_ERR);
+-01483         } else {
+-01484                 dwc_otg_halt_status_e halt_status;
+-01485                 halt_status = update_isoc_urb_state(hcd, hc, hc_regs, qtd,
+-01486                                                     DWC_OTG_HC_XFER_BABBLE_ERR);
+-01487                 halt_channel(hcd, hc, qtd, halt_status);
+-01488         }
+-01489         
+-01490 handle_babble_done:
+-01491         disable_hc_int(hc_regs, bblerr);
+-01492         return 1;
+-01493 }
+-01494 
+-01499 static int32_t handle_hc_ahberr_intr(dwc_otg_hcd_t * hcd,
+-01500                                      dwc_hc_t * hc,
+-01501                                      dwc_otg_hc_regs_t * hc_regs,
+-01502                                      dwc_otg_qtd_t * qtd)
+-01503 {
+-01504         hcchar_data_t hcchar;
+-01505         hcsplt_data_t hcsplt;
+-01506         hctsiz_data_t hctsiz;
+-01507         uint32_t hcdma;
+-01508         char *pipetype, *speed;
+-01509 
+-01510         dwc_otg_hcd_urb_t *urb = qtd->urb;
+-01511 
+-01512         DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
+-01513                     "AHB Error--\n", hc->hc_num);
+-01514 
+-01515         hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
+-01516         hcsplt.d32 = dwc_read_reg32(&hc_regs->hcsplt);
+-01517         hctsiz.d32 = dwc_read_reg32(&hc_regs->hctsiz);
+-01518         hcdma = dwc_read_reg32(&hc_regs->hcdma);
+-01519 
+-01520         DWC_ERROR("AHB ERROR, Channel %d\n", hc->hc_num);
+-01521         DWC_ERROR("  hcchar 0x%08x, hcsplt 0x%08x\n", hcchar.d32, hcsplt.d32);
+-01522         DWC_ERROR("  hctsiz 0x%08x, hcdma 0x%08x\n", hctsiz.d32, hcdma);
+-01523         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD URB Enqueue\n");
+-01524         DWC_ERROR("  Device address: %d\n",
+-01525                   dwc_otg_hcd_get_dev_addr(&urb->pipe_info));
+-01526         DWC_ERROR("  Endpoint: %d, %s\n",
+-01527                   dwc_otg_hcd_get_ep_num(&urb->pipe_info),
+-01528                   (dwc_otg_hcd_is_pipe_in(&urb->pipe_info) ? "IN" : "OUT"));
+-01529         
+-01530 
+-01531         switch (dwc_otg_hcd_get_pipe_type(&urb->pipe_info)) {
+-01532 case UE_CONTROL:
+-01533                 pipetype = "CONTROL"; 
+-01534                 break; 
+-01535         case UE_BULK:
+-01536                 pipetype = "BULK"; 
+-01537                 break; 
+-01538         case UE_INTERRUPT:
+-01539                 pipetype = "INTERRUPT"; 
+-01540                 break; 
+-01541         case UE_ISOCHRONOUS:
+-01542                 pipetype = "ISOCHRONOUS"; 
+-01543                 break; 
+-01544         default:
+-01545                 pipetype = "UNKNOWN"; 
+-01546                 break;
+-01547         }
+-01548         
+-01549         DWC_ERROR("  Endpoint type: %s\n", pipetype);
+-01550 
+-01551         switch (hc->speed) {
+-01552         case DWC_OTG_EP_SPEED_HIGH:
+-01553                 speed = "HIGH"; 
+-01554                 break; 
+-01555         case DWC_OTG_EP_SPEED_FULL:
+-01556                 speed = "FULL"; 
+-01557                 break; 
+-01558         case DWC_OTG_EP_SPEED_LOW:
+-01559                 speed = "LOW"; 
+-01560                 break; 
+-01561         default:
+-01562                 speed = "UNKNOWN"; 
+-01563                 break;
+-01564         };      
+-01565 
+-01566         DWC_ERROR("  Speed: %s\n", speed);
+-01567         
+-01568         DWC_ERROR("  Max packet size: %d\n",
+-01569                   dwc_otg_hcd_get_mps(&urb->pipe_info));
+-01570         DWC_ERROR("  Data buffer length: %d\n", urb->length);
+-01571         DWC_ERROR("  Transfer buffer: %p, Transfer DMA: %p\n",
+-01572                   urb->buf, (void *)urb->dma);
+-01573         DWC_ERROR("  Setup buffer: %p, Setup DMA: %p\n",
+-01574                   urb->setup_packet, (void *)urb->setup_dma);
+-01575         DWC_ERROR("  Interval: %d\n", urb->interval);
+-01576 
+-01577         /* Core haltes the channel for Descriptor DMA mode */
+-01578         if (hcd->core_if->dma_desc_enable) {
+-01579                 dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs, DWC_OTG_HC_XFER_AHB_ERR);
+-01580                 goto handle_ahberr_done;
+-01581         }
+-01582 
+-01583         hcd->fops->complete(hcd, urb->priv, urb, -DWC_E_IO);
+-01584 
+-01585         /*
+-01586          * Force a channel halt. Don't call halt_channel because that won't
+-01587          * write to the HCCHARn register in DMA mode to force the halt.
+-01588          */
+-01589         dwc_otg_hc_halt(hcd->core_if, hc, DWC_OTG_HC_XFER_AHB_ERR);
+-01590 handle_ahberr_done:
+-01591         disable_hc_int(hc_regs, ahberr);
+-01592         return 1;
+-01593 }
+-01594 
+-01599 static int32_t handle_hc_xacterr_intr(dwc_otg_hcd_t * hcd,
+-01600                                       dwc_hc_t * hc,
+-01601                                       dwc_otg_hc_regs_t * hc_regs,
+-01602                                       dwc_otg_qtd_t * qtd)
+-01603 {
+-01604         DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
+-01605                     "Transaction Error--\n", hc->hc_num);
+-01606 
+-01607         if (hcd->core_if->dma_desc_enable) {
+-01608                 dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs, DWC_OTG_HC_XFER_XACT_ERR);
+-01609                 goto handle_xacterr_done;
+-01610         }
+-01611 
+-01612         switch (dwc_otg_hcd_get_pipe_type(&qtd->urb->pipe_info)) {
+-01613         case UE_CONTROL:
+-01614         case UE_BULK:
+-01615                 qtd->error_count++;
+-01616                 if (!hc->qh->ping_state) {
+-01617 
+-01618                         update_urb_state_xfer_intr(hc, hc_regs,
+-01619                                                    qtd->urb, qtd,
+-01620                                                    DWC_OTG_HC_XFER_XACT_ERR);
+-01621                         dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
+-01622                         if (!hc->ep_is_in && hc->speed == DWC_OTG_EP_SPEED_HIGH) {
+-01623                                 hc->qh->ping_state = 1;
+-01624                         }
+-01625                 }
+-01626 
+-01627                 /*
+-01628                  * Halt the channel so the transfer can be re-started from
+-01629                  * the appropriate point or the PING protocol will start.
+-01630                  */
+-01631                 halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_XACT_ERR);
+-01632                 break;
+-01633         case UE_INTERRUPT:
+-01634                 qtd->error_count++;
+-01635                 if (hc->do_split && hc->complete_split) {
+-01636                         qtd->complete_split = 0;
+-01637                 }
+-01638                 halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_XACT_ERR);
+-01639                 break;
+-01640         case UE_ISOCHRONOUS:
+-01641                 {
+-01642                         dwc_otg_halt_status_e halt_status;
+-01643                         halt_status =
+-01644                             update_isoc_urb_state(hcd, hc, hc_regs, qtd,
+-01645                                                   DWC_OTG_HC_XFER_XACT_ERR);
+-01646 
+-01647                         halt_channel(hcd, hc, qtd, halt_status);
+-01648                 }
+-01649                 break;
+-01650         }
+-01651 handle_xacterr_done:
+-01652         disable_hc_int(hc_regs, xacterr);
+-01653 
+-01654         return 1;
+-01655 }
+-01656 
+-01661 static int32_t handle_hc_frmovrun_intr(dwc_otg_hcd_t * hcd,
+-01662                                        dwc_hc_t * hc,
+-01663                                        dwc_otg_hc_regs_t * hc_regs,
+-01664                                        dwc_otg_qtd_t * qtd)
+-01665 {
+-01666         DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
+-01667                     "Frame Overrun--\n", hc->hc_num);
+-01668 
+-01669         switch (dwc_otg_hcd_get_pipe_type(&qtd->urb->pipe_info)) {
+-01670         case UE_CONTROL:
+-01671         case UE_BULK:
+-01672                 break;
+-01673         case UE_INTERRUPT:
+-01674                 halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_FRAME_OVERRUN);
+-01675                 break;
+-01676         case UE_ISOCHRONOUS:
+-01677                 {
+-01678                         dwc_otg_halt_status_e halt_status;
+-01679                         halt_status =
+-01680                             update_isoc_urb_state(hcd, hc, hc_regs, qtd,
+-01681                                                   DWC_OTG_HC_XFER_FRAME_OVERRUN);
+-01682 
+-01683                         halt_channel(hcd, hc, qtd, halt_status);
+-01684                 }
+-01685                 break;
+-01686         }
+-01687 
+-01688         disable_hc_int(hc_regs, frmovrun);
+-01689 
+-01690         return 1;
+-01691 }
+-01692 
+-01697 static int32_t handle_hc_datatglerr_intr(dwc_otg_hcd_t * hcd,
+-01698                                          dwc_hc_t * hc,
+-01699                                          dwc_otg_hc_regs_t * hc_regs,
+-01700                                          dwc_otg_qtd_t * qtd)
+-01701 {
+-01702         DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
+-01703                     "Data Toggle Error--\n", hc->hc_num);
+-01704 
+-01705         if (hc->ep_is_in) {
+-01706                 qtd->error_count = 0;
+-01707         } else {
+-01708                 DWC_ERROR("Data Toggle Error on OUT transfer,"
+-01709                           "channel %d\n", hc->hc_num);
+-01710         }
+-01711 
+-01712         disable_hc_int(hc_regs, datatglerr);
+-01713 
+-01714         return 1;
+-01715 }
+-01716 
+-01717 #ifdef DEBUG
+-01718 
+-01724 static inline int halt_status_ok(dwc_otg_hcd_t * hcd,
+-01725                                  dwc_hc_t * hc,
+-01726                                  dwc_otg_hc_regs_t * hc_regs,
+-01727                                  dwc_otg_qtd_t * qtd)
+-01728 {
+-01729         hcchar_data_t hcchar;
+-01730         hctsiz_data_t hctsiz;
+-01731         hcint_data_t hcint;
+-01732         hcintmsk_data_t hcintmsk;
+-01733         hcsplt_data_t hcsplt;
+-01734 
+-01735         if (hc->halt_status == DWC_OTG_HC_XFER_NO_HALT_STATUS) {
+-01736                 /*
+-01737                  * This code is here only as a check. This condition should
+-01738                  * never happen. Ignore the halt if it does occur.
+-01739                  */
+-01740                 hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
+-01741                 hctsiz.d32 = dwc_read_reg32(&hc_regs->hctsiz);
+-01742                 hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
+-01743                 hcintmsk.d32 = dwc_read_reg32(&hc_regs->hcintmsk);
+-01744                 hcsplt.d32 = dwc_read_reg32(&hc_regs->hcsplt);
+-01745                 DWC_WARN
+-01746                     ("%s: hc->halt_status == DWC_OTG_HC_XFER_NO_HALT_STATUS, "
+-01747                      "channel %d, hcchar 0x%08x, hctsiz 0x%08x, "
+-01748                      "hcint 0x%08x, hcintmsk 0x%08x, "
+-01749                      "hcsplt 0x%08x, qtd->complete_split %d\n", __func__,
+-01750                      hc->hc_num, hcchar.d32, hctsiz.d32, hcint.d32,
+-01751                      hcintmsk.d32, hcsplt.d32, qtd->complete_split);
+-01752 
+-01753                 DWC_WARN("%s: no halt status, channel %d, ignoring interrupt\n",
+-01754                          __func__, hc->hc_num);
+-01755                 DWC_WARN("\n");
+-01756                 clear_hc_int(hc_regs, chhltd);
+-01757                 return 0;
+-01758         }
+-01759 
+-01760         /*
+-01761          * This code is here only as a check. hcchar.chdis should
+-01762          * never be set when the halt interrupt occurs. Halt the
+-01763          * channel again if it does occur.
+-01764          */
+-01765         hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
+-01766         if (hcchar.b.chdis) {
+-01767                 DWC_WARN("%s: hcchar.chdis set unexpectedly, "
+-01768                          "hcchar 0x%08x, trying to halt again\n",
+-01769                          __func__, hcchar.d32);
+-01770                 clear_hc_int(hc_regs, chhltd);
+-01771                 hc->halt_pending = 0;
+-01772                 halt_channel(hcd, hc, qtd, hc->halt_status);
+-01773                 return 0;
+-01774         }
+-01775 
+-01776         return 1;
+-01777 }
+-01778 #endif
+-01779 
+-01784 static void handle_hc_chhltd_intr_dma(dwc_otg_hcd_t * hcd,
+-01785                                       dwc_hc_t * hc,
+-01786                                       dwc_otg_hc_regs_t * hc_regs,
+-01787                                       dwc_otg_qtd_t * qtd)
+-01788 {
+-01789         hcint_data_t hcint;
+-01790         hcintmsk_data_t hcintmsk;
+-01791         int out_nak_enh = 0;
+-01792 
+-01793         /* For core with OUT NAK enhancement, the flow for high-
+-01794          * speed CONTROL/BULK OUT is handled a little differently.
+-01795          */
+-01796         if (hcd->core_if->snpsid >= OTG_CORE_REV_2_71a) {
+-01797                 if (hc->speed == DWC_OTG_EP_SPEED_HIGH && !hc->ep_is_in &&
+-01798                     (hc->ep_type == DWC_OTG_EP_TYPE_CONTROL ||
+-01799                      hc->ep_type == DWC_OTG_EP_TYPE_BULK)) {
+-01800                         out_nak_enh = 1;
+-01801                 }
+-01802         }
+-01803 
+-01804         if (hc->halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE ||
+-01805             (hc->halt_status == DWC_OTG_HC_XFER_AHB_ERR && !hcd->core_if->dma_desc_enable)) {
+-01806                 /*
+-01807                  * Just release the channel. A dequeue can happen on a
+-01808                  * transfer timeout. In the case of an AHB Error, the channel
+-01809                  * was forced to halt because there's no way to gracefully
+-01810                  * recover.
+-01811                  */
+-01812                 if (hcd->core_if->dma_desc_enable)
+-01813                         dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs, hc->halt_status);
+-01814                 else
+-01815                         release_channel(hcd, hc, qtd, hc->halt_status);
+-01816                 return;
+-01817         }
+-01818 
+-01819         /* Read the HCINTn register to determine the cause for the halt. */
+-01820         hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
+-01821         hcintmsk.d32 = dwc_read_reg32(&hc_regs->hcintmsk);
+-01822 
+-01823         if (hcint.b.xfercomp) {
+-01830                 if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC && !hc->ep_is_in) {
+-01831                         handle_hc_ack_intr(hcd, hc, hc_regs, qtd);
+-01832                 }
+-01833                 handle_hc_xfercomp_intr(hcd, hc, hc_regs, qtd);
+-01834         } else if (hcint.b.stall) {
+-01835                 handle_hc_stall_intr(hcd, hc, hc_regs, qtd);
+-01836         } else if (hcint.b.xacterr && !hcd->core_if->dma_desc_enable) {
+-01837                 if (out_nak_enh) {
+-01838                         if (hcint.b.nyet || hcint.b.nak || hcint.b.ack) {
+-01839                                 DWC_DEBUG("XactErr with NYET/NAK/ACK\n");
+-01840                                 qtd->error_count = 0;
+-01841                         } else {
+-01842                                 DWC_DEBUG("XactErr without NYET/NAK/ACK\n");
+-01843                         }
+-01844                 }
+-01845 
+-01846                 /*
+-01847                  * Must handle xacterr before nak or ack. Could get a xacterr
+-01848                  * at the same time as either of these on a BULK/CONTROL OUT
+-01849                  * that started with a PING. The xacterr takes precedence.
+-01850                  */
+-01851                 handle_hc_xacterr_intr(hcd, hc, hc_regs, qtd);
+-01852         } else if (hcint.b.xcs_xact && hcd->core_if->dma_desc_enable) {
+-01853                 handle_hc_xacterr_intr(hcd, hc, hc_regs, qtd);
+-01854         } else if (hcint.b.ahberr && hcd->core_if->dma_desc_enable) {    
+-01855                 handle_hc_ahberr_intr(hcd, hc, hc_regs, qtd);
+-01856         } else if (hcint.b.bblerr) {
+-01857                 handle_hc_babble_intr(hcd, hc, hc_regs, qtd);
+-01858         } else if (hcint.b.frmovrun) {
+-01859                 handle_hc_frmovrun_intr(hcd, hc, hc_regs, qtd);
+-01860         } else if (!out_nak_enh) {
+-01861                 if (hcint.b.nyet) {
+-01862                         /*
+-01863                          * Must handle nyet before nak or ack. Could get a nyet at the
+-01864                          * same time as either of those on a BULK/CONTROL OUT that
+-01865                          * started with a PING. The nyet takes precedence.
+-01866                          */
+-01867                         handle_hc_nyet_intr(hcd, hc, hc_regs, qtd);
+-01868                 } else if (hcint.b.nak && !hcintmsk.b.nak) {
+-01869                         /*
+-01870                          * If nak is not masked, it's because a non-split IN transfer
+-01871                          * is in an error state. In that case, the nak is handled by
+-01872                          * the nak interrupt handler, not here. Handle nak here for
+-01873                          * BULK/CONTROL OUT transfers, which halt on a NAK to allow
+-01874                          * rewinding the buffer pointer.
+-01875                          */
+-01876                         handle_hc_nak_intr(hcd, hc, hc_regs, qtd);
+-01877                 } else if (hcint.b.ack && !hcintmsk.b.ack) {
+-01878                         /*
+-01879                          * If ack is not masked, it's because a non-split IN transfer
+-01880                          * is in an error state. In that case, the ack is handled by
+-01881                          * the ack interrupt handler, not here. Handle ack here for
+-01882                          * split transfers. Start splits halt on ACK.
+-01883                          */
+-01884                         handle_hc_ack_intr(hcd, hc, hc_regs, qtd);
+-01885                 } else {
+-01886                         if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
+-01887                             hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
+-01888                                 /*
+-01889                                  * A periodic transfer halted with no other channel
+-01890                                  * interrupts set. Assume it was halted by the core
+-01891                                  * because it could not be completed in its scheduled
+-01892                                  * (micro)frame.
+-01893                                  */
+-01894 #ifdef DEBUG
+-01895                                 DWC_PRINTF
+-01896                                     ("%s: Halt channel %d (assume incomplete periodic transfer)\n",
+-01897                                      __func__, hc->hc_num);
+-01898 #endif
+-01899                                 halt_channel(hcd, hc, qtd,
+-01900                                              DWC_OTG_HC_XFER_PERIODIC_INCOMPLETE);
+-01901                         } else {
+-01902                                 DWC_ERROR
+-01903                                     ("%s: Channel %d, DMA Mode -- ChHltd set, but reason "
+-01904                                      "for halting is unknown, hcint 0x%08x, intsts 0x%08x\n",
+-01905                                      __func__, hc->hc_num, hcint.d32,
+-01906                                      dwc_read_reg32(&hcd->core_if->
+-01907                                                     core_global_regs->gintsts));
+-01908                         }
+-01909         
+-01910                 }
+-01911         } else {
+-01912                 DWC_PRINTF("NYET/NAK/ACK/other in non-error case, 0x%08x\n",
+-01913                            hcint.d32);
+-01914         }
+-01915 }
+-01916 
+-01928 static int32_t handle_hc_chhltd_intr(dwc_otg_hcd_t * hcd,
+-01929                                      dwc_hc_t * hc,
+-01930                                      dwc_otg_hc_regs_t * hc_regs,
+-01931                                      dwc_otg_qtd_t * qtd)
+-01932 {
+-01933         DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
+-01934                     "Channel Halted--\n", hc->hc_num);
+-01935 
+-01936         if (hcd->core_if->dma_enable) {
+-01937                 handle_hc_chhltd_intr_dma(hcd, hc, hc_regs, qtd);
+-01938         } else {
+-01939 #ifdef DEBUG
+-01940                 if (!halt_status_ok(hcd, hc, hc_regs, qtd)) {
+-01941                         return 1;
+-01942                 }
+-01943 #endif
+-01944                 release_channel(hcd, hc, qtd, hc->halt_status);
+-01945         }
+-01946 
+-01947         return 1;
+-01948 }
+-01949 
+-01951 int32_t dwc_otg_hcd_handle_hc_n_intr(dwc_otg_hcd_t * dwc_otg_hcd, uint32_t num)
+-01952 {
+-01953         int retval = 0;
+-01954         hcint_data_t hcint;
+-01955         hcintmsk_data_t hcintmsk;
+-01956         dwc_hc_t *hc;
+-01957         dwc_otg_hc_regs_t *hc_regs;
+-01958         dwc_otg_qtd_t *qtd;
+-01959 
+-01960         DWC_DEBUGPL(DBG_HCDV, "--Host Channel Interrupt--, Channel %d\n", num);
+-01961 
+-01962         hc = dwc_otg_hcd->hc_ptr_array[num];
+-01963         hc_regs = dwc_otg_hcd->core_if->host_if->hc_regs[num];
+-01964         qtd = DWC_CIRCLEQ_FIRST(&hc->qh->qtd_list);
+-01965 
+-01966         hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
+-01967         hcintmsk.d32 = dwc_read_reg32(&hc_regs->hcintmsk);
+-01968         DWC_DEBUGPL(DBG_HCDV,
+-01969                     "  hcint 0x%08x, hcintmsk 0x%08x, hcint&hcintmsk 0x%08x\n",
+-01970                     hcint.d32, hcintmsk.d32, (hcint.d32 & hcintmsk.d32));
+-01971         hcint.d32 = hcint.d32 & hcintmsk.d32;
+-01972 
+-01973         if (!dwc_otg_hcd->core_if->dma_enable) {
+-01974                 if (hcint.b.chhltd && hcint.d32 != 0x2) {
+-01975                         hcint.b.chhltd = 0;
+-01976                 }
+-01977         }
+-01978 
+-01979         if (hcint.b.xfercomp) {
+-01980                 retval |=
+-01981                     handle_hc_xfercomp_intr(dwc_otg_hcd, hc, hc_regs, qtd);
+-01982                 /*
+-01983                  * If NYET occurred at same time as Xfer Complete, the NYET is
+-01984                  * handled by the Xfer Complete interrupt handler. Don't want
+-01985                  * to call the NYET interrupt handler in this case.
+-01986                  */
+-01987                 hcint.b.nyet = 0;
+-01988         }
+-01989         if (hcint.b.chhltd) {
+-01990                 retval |= handle_hc_chhltd_intr(dwc_otg_hcd, hc, hc_regs, qtd);
+-01991         }
+-01992         if (hcint.b.ahberr) {
+-01993                 retval |= handle_hc_ahberr_intr(dwc_otg_hcd, hc, hc_regs, qtd);
+-01994         }
+-01995         if (hcint.b.stall) {
+-01996                 retval |= handle_hc_stall_intr(dwc_otg_hcd, hc, hc_regs, qtd);
+-01997         }
+-01998         if (hcint.b.nak) {
+-01999                 retval |= handle_hc_nak_intr(dwc_otg_hcd, hc, hc_regs, qtd);
+-02000         }
+-02001         if (hcint.b.ack) {
+-02002                 retval |= handle_hc_ack_intr(dwc_otg_hcd, hc, hc_regs, qtd);
+-02003         }
+-02004         if (hcint.b.nyet) {
+-02005                 retval |= handle_hc_nyet_intr(dwc_otg_hcd, hc, hc_regs, qtd);
+-02006         }
+-02007         if (hcint.b.xacterr) {
+-02008                 retval |= handle_hc_xacterr_intr(dwc_otg_hcd, hc, hc_regs, qtd);
+-02009         }
+-02010         if (hcint.b.bblerr) {
+-02011                 retval |= handle_hc_babble_intr(dwc_otg_hcd, hc, hc_regs, qtd);
+-02012         }
+-02013         if (hcint.b.frmovrun) {
+-02014                 retval |=
+-02015                     handle_hc_frmovrun_intr(dwc_otg_hcd, hc, hc_regs, qtd);
+-02016         }
+-02017         if (hcint.b.datatglerr) {
+-02018                 retval |=
+-02019                     handle_hc_datatglerr_intr(dwc_otg_hcd, hc, hc_regs, qtd);
+-02020         }
+-02021 
+-02022         return retval;
+-02023 }
+-02024 
+-02025 #endif                          /* DWC_DEVICE_ONLY */
+-
    Generated on Tue May 5 02:22:48 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++
    Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
    ++

    dwc_otg_hcd_intr.c

    Go to the documentation of this file.
    00001 /* ==========================================================================
++00002  * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd_intr.c $
++00003  * $Revision: #89 $
++00004  * $Date: 2011/10/20 $
++00005  * $Change: 1869487 $
++00006  *
++00007  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
++00008  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
++00009  * otherwise expressly agreed to in writing between Synopsys and you.
++00010  *
++00011  * The Software IS NOT an item of Licensed Software or Licensed Product under
++00012  * any End User Software License Agreement or Agreement for Licensed Product
++00013  * with Synopsys or any supplement thereto. You are permitted to use and
++00014  * redistribute this Software in source and binary forms, with or without
++00015  * modification, provided that redistributions of source code must retain this
++00016  * notice. You may not view, use, disclose, copy or distribute this file or
++00017  * any information contained herein except pursuant to this license grant from
++00018  * Synopsys. If you do not agree with this notice, including the disclaimer
++00019  * below, then you are not authorized to use the Software.
++00020  *
++00021  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
++00022  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++00023  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++00024  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
++00025  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++00026  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
++00027  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
++00028  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
++00029  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
++00030  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
++00031  * DAMAGE.
++00032  * ========================================================================== */
++00033 #ifndef DWC_DEVICE_ONLY
++00034 
++00035 #include "dwc_otg_hcd.h"
++00036 #include "dwc_otg_regs.h"
++00037 
++00043 int32_t dwc_otg_hcd_handle_intr(dwc_otg_hcd_t * dwc_otg_hcd)
++00044 {
++00045         int retval = 0;
++00046 
++00047         dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;
++00048         gintsts_data_t gintsts;
++00049 #ifdef DEBUG
++00050         dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
++00051 #endif
++00052 
++00053         /* Exit from ISR if core is hibernated */
++00054         if (core_if->hibernation_suspend == 1) {
++00055                 return retval;
++00056         }
++00057         DWC_SPINLOCK(dwc_otg_hcd->lock);
++00058         /* Check if HOST Mode */
++00059         if (dwc_otg_is_host_mode(core_if)) {
++00060                 gintsts.d32 = dwc_otg_read_core_intr(core_if);
++00061                 if (!gintsts.d32) {
++00062                         DWC_SPINUNLOCK(dwc_otg_hcd->lock);
++00063                         return 0;
++00064                 }
++00065 #ifdef DEBUG
++00066                 /* Don't print debug message in the interrupt handler on SOF */
++00067 #ifndef DEBUG_SOF
++00068                 if (gintsts.d32 != DWC_SOF_INTR_MASK)
++00069 #endif
++00070                         DWC_DEBUGPL(DBG_HCD, "\n");
++00071 #endif
++00072 
++00073 #ifdef DEBUG
++00074 #ifndef DEBUG_SOF
++00075                 if (gintsts.d32 != DWC_SOF_INTR_MASK)
++00076 #endif
++00077                         DWC_DEBUGPL(DBG_HCD,
++00078                                     "DWC OTG HCD Interrupt Detected gintsts&gintmsk=0x%08x\n",
++00079                                     gintsts.d32);
++00080 #endif
++00081 
++00082                 if (gintsts.b.sofintr) {
++00083                         retval |= dwc_otg_hcd_handle_sof_intr(dwc_otg_hcd);
++00084                 }
++00085                 if (gintsts.b.rxstsqlvl) {
++00086                         retval |=
++00087                             dwc_otg_hcd_handle_rx_status_q_level_intr
++00088                             (dwc_otg_hcd);
++00089                 }
++00090                 if (gintsts.b.nptxfempty) {
++00091                         retval |=
++00092                             dwc_otg_hcd_handle_np_tx_fifo_empty_intr
++00093                             (dwc_otg_hcd);
++00094                 }
++00095                 if (gintsts.b.i2cintr) {
++00097                 }
++00098                 if (gintsts.b.portintr) {
++00099                         retval |= dwc_otg_hcd_handle_port_intr(dwc_otg_hcd);
++00100                 }
++00101                 if (gintsts.b.hcintr) {
++00102                         retval |= dwc_otg_hcd_handle_hc_intr(dwc_otg_hcd);
++00103                 }
++00104                 if (gintsts.b.ptxfempty) {
++00105                         retval |=
++00106                             dwc_otg_hcd_handle_perio_tx_fifo_empty_intr
++00107                             (dwc_otg_hcd);
++00108                 }
++00109 #ifdef DEBUG
++00110 #ifndef DEBUG_SOF
++00111                 if (gintsts.d32 != DWC_SOF_INTR_MASK)
++00112 #endif
++00113                 {
++00114                         DWC_DEBUGPL(DBG_HCD,
++00115                                     "DWC OTG HCD Finished Servicing Interrupts\n");
++00116                         DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD gintsts=0x%08x\n",
++00117                                     DWC_READ_REG32(&global_regs->gintsts));
++00118                         DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD gintmsk=0x%08x\n",
++00119                                     DWC_READ_REG32(&global_regs->gintmsk));
++00120                 }
++00121 #endif
++00122 
++00123 #ifdef DEBUG
++00124 #ifndef DEBUG_SOF
++00125                 if (gintsts.d32 != DWC_SOF_INTR_MASK)
++00126 #endif
++00127                         DWC_DEBUGPL(DBG_HCD, "\n");
++00128 #endif
++00129 
++00130         }
++00131         DWC_SPINUNLOCK(dwc_otg_hcd->lock);
++00132         return retval;
++00133 }
++00134 
++00135 #ifdef DWC_TRACK_MISSED_SOFS
++00136 #warning Compiling code to track missed SOFs
++00137 #define FRAME_NUM_ARRAY_SIZE 1000
++00138 
++00141 static inline void track_missed_sofs(uint16_t curr_frame_number)
++00142 {
++00143         static uint16_t frame_num_array[FRAME_NUM_ARRAY_SIZE];
++00144         static uint16_t last_frame_num_array[FRAME_NUM_ARRAY_SIZE];
++00145         static int frame_num_idx = 0;
++00146         static uint16_t last_frame_num = DWC_HFNUM_MAX_FRNUM;
++00147         static int dumped_frame_num_array = 0;
++00148 
++00149         if (frame_num_idx < FRAME_NUM_ARRAY_SIZE) {
++00150                 if (((last_frame_num + 1) & DWC_HFNUM_MAX_FRNUM) !=
++00151                     curr_frame_number) {
++00152                         frame_num_array[frame_num_idx] = curr_frame_number;
++00153                         last_frame_num_array[frame_num_idx++] = last_frame_num;
++00154                 }
++00155         } else if (!dumped_frame_num_array) {
++00156                 int i;
++00157                 DWC_PRINTF("Frame     Last Frame\n");
++00158                 DWC_PRINTF("-----     ----------\n");
++00159                 for (i = 0; i < FRAME_NUM_ARRAY_SIZE; i++) {
++00160                         DWC_PRINTF("0x%04x    0x%04x\n",
++00161                                    frame_num_array[i], last_frame_num_array[i]);
++00162                 }
++00163                 dumped_frame_num_array = 1;
++00164         }
++00165         last_frame_num = curr_frame_number;
++00166 }
++00167 #endif
++00168 
++00175 int32_t dwc_otg_hcd_handle_sof_intr(dwc_otg_hcd_t * hcd)
++00176 {
++00177         hfnum_data_t hfnum;
++00178         dwc_list_link_t *qh_entry;
++00179         dwc_otg_qh_t *qh;
++00180         dwc_otg_transaction_type_e tr_type;
++00181         gintsts_data_t gintsts = {.d32 = 0 };
++00182 
++00183         hfnum.d32 =
++00184             DWC_READ_REG32(&hcd->core_if->host_if->host_global_regs->hfnum);
++00185 
++00186 #ifdef DEBUG_SOF
++00187         DWC_DEBUGPL(DBG_HCD, "--Start of Frame Interrupt--\n");
++00188 #endif
++00189         hcd->frame_number = hfnum.b.frnum;
++00190 
++00191 #ifdef DEBUG
++00192         hcd->frrem_accum += hfnum.b.frrem;
++00193         hcd->frrem_samples++;
++00194 #endif
++00195 
++00196 #ifdef DWC_TRACK_MISSED_SOFS
++00197         track_missed_sofs(hcd->frame_number);
++00198 #endif
++00199         /* Determine whether any periodic QHs should be executed. */
++00200         qh_entry = DWC_LIST_FIRST(&hcd->periodic_sched_inactive);
++00201         while (qh_entry != &hcd->periodic_sched_inactive) {
++00202                 qh = DWC_LIST_ENTRY(qh_entry, dwc_otg_qh_t, qh_list_entry);
++00203                 qh_entry = qh_entry->next;
++00204                 if (dwc_frame_num_le(qh->sched_frame, hcd->frame_number)) {
++00205                         /*
++00206                          * Move QH to the ready list to be executed next
++00207                          * (micro)frame.
++00208                          */
++00209                         DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_ready,
++00210                                            &qh->qh_list_entry);
++00211                 }
++00212         }
++00213         tr_type = dwc_otg_hcd_select_transactions(hcd);
++00214         if (tr_type != DWC_OTG_TRANSACTION_NONE) {
++00215                 dwc_otg_hcd_queue_transactions(hcd, tr_type);
++00216         }
++00217 
++00218         /* Clear interrupt */
++00219         gintsts.b.sofintr = 1;
++00220         DWC_WRITE_REG32(&hcd->core_if->core_global_regs->gintsts, gintsts.d32);
++00221 
++00222         return 1;
++00223 }
++00224 
++00228 int32_t dwc_otg_hcd_handle_rx_status_q_level_intr(dwc_otg_hcd_t * dwc_otg_hcd)
++00229 {
++00230         host_grxsts_data_t grxsts;
++00231         dwc_hc_t *hc = NULL;
++00232 
++00233         DWC_DEBUGPL(DBG_HCD, "--RxStsQ Level Interrupt--\n");
++00234 
++00235         grxsts.d32 =
++00236             DWC_READ_REG32(&dwc_otg_hcd->core_if->core_global_regs->grxstsp);
++00237 
++00238         hc = dwc_otg_hcd->hc_ptr_array[grxsts.b.chnum];
++00239         if (!hc) {
++00240                 DWC_ERROR("Unable to get corresponding channel\n");
++00241                 return 0;
++00242         }
++00243 
++00244         /* Packet Status */
++00245         DWC_DEBUGPL(DBG_HCDV, "    Ch num = %d\n", grxsts.b.chnum);
++00246         DWC_DEBUGPL(DBG_HCDV, "    Count = %d\n", grxsts.b.bcnt);
++00247         DWC_DEBUGPL(DBG_HCDV, "    DPID = %d, hc.dpid = %d\n", grxsts.b.dpid,
++00248                     hc->data_pid_start);
++00249         DWC_DEBUGPL(DBG_HCDV, "    PStatus = %d\n", grxsts.b.pktsts);
++00250 
++00251         switch (grxsts.b.pktsts) {
++00252         case DWC_GRXSTS_PKTSTS_IN:
++00253                 /* Read the data into the host buffer. */
++00254                 if (grxsts.b.bcnt > 0) {
++00255                         dwc_otg_read_packet(dwc_otg_hcd->core_if,
++00256                                             hc->xfer_buff, grxsts.b.bcnt);
++00257 
++00258                         /* Update the HC fields for the next packet received. */
++00259                         hc->xfer_count += grxsts.b.bcnt;
++00260                         hc->xfer_buff += grxsts.b.bcnt;
++00261                 }
++00262 
++00263         case DWC_GRXSTS_PKTSTS_IN_XFER_COMP:
++00264         case DWC_GRXSTS_PKTSTS_DATA_TOGGLE_ERR:
++00265         case DWC_GRXSTS_PKTSTS_CH_HALTED:
++00266                 /* Handled in interrupt, just ignore data */
++00267                 break;
++00268         default:
++00269                 DWC_ERROR("RX_STS_Q Interrupt: Unknown status %d\n",
++00270                           grxsts.b.pktsts);
++00271                 break;
++00272         }
++00273 
++00274         return 1;
++00275 }
++00276 
++00281 int32_t dwc_otg_hcd_handle_np_tx_fifo_empty_intr(dwc_otg_hcd_t * dwc_otg_hcd)
++00282 {
++00283         DWC_DEBUGPL(DBG_HCD, "--Non-Periodic TxFIFO Empty Interrupt--\n");
++00284         dwc_otg_hcd_queue_transactions(dwc_otg_hcd,
++00285                                        DWC_OTG_TRANSACTION_NON_PERIODIC);
++00286         return 1;
++00287 }
++00288 
++00293 int32_t dwc_otg_hcd_handle_perio_tx_fifo_empty_intr(dwc_otg_hcd_t * dwc_otg_hcd)
++00294 {
++00295         DWC_DEBUGPL(DBG_HCD, "--Periodic TxFIFO Empty Interrupt--\n");
++00296         dwc_otg_hcd_queue_transactions(dwc_otg_hcd,
++00297                                        DWC_OTG_TRANSACTION_PERIODIC);
++00298         return 1;
++00299 }
++00300 
++00304 int32_t dwc_otg_hcd_handle_port_intr(dwc_otg_hcd_t * dwc_otg_hcd)
++00305 {
++00306         int retval = 0;
++00307         hprt0_data_t hprt0;
++00308         hprt0_data_t hprt0_modify;
++00309 
++00310         hprt0.d32 = DWC_READ_REG32(dwc_otg_hcd->core_if->host_if->hprt0);
++00311         hprt0_modify.d32 = DWC_READ_REG32(dwc_otg_hcd->core_if->host_if->hprt0);
++00312 
++00313         /* Clear appropriate bits in HPRT0 to clear the interrupt bit in
++00314          * GINTSTS */
++00315 
++00316         hprt0_modify.b.prtena = 0;
++00317         hprt0_modify.b.prtconndet = 0;
++00318         hprt0_modify.b.prtenchng = 0;
++00319         hprt0_modify.b.prtovrcurrchng = 0;
++00320 
++00321         /* Port Connect Detected
++00322          * Set flag and clear if detected */
++00323         if (dwc_otg_hcd->core_if->hibernation_suspend == 1) {
++00324                 // Dont modify port status if we are in hibernation state
++00325                 hprt0_modify.b.prtconndet = 1;
++00326                 hprt0_modify.b.prtenchng = 1;
++00327                 DWC_WRITE_REG32(dwc_otg_hcd->core_if->host_if->hprt0, hprt0_modify.d32);
++00328                 hprt0.d32 = DWC_READ_REG32(dwc_otg_hcd->core_if->host_if->hprt0);
++00329                 return retval;
++00330         }
++00331 
++00332         if (hprt0.b.prtconndet) {
++00334                 if (dwc_otg_hcd->core_if->adp_enable &&         
++00335                                 dwc_otg_hcd->core_if->adp.vbuson_timer_started == 1) {
++00336                         DWC_PRINTF("PORT CONNECT DETECTED ----------------\n");
++00337                         DWC_TIMER_CANCEL(dwc_otg_hcd->core_if->adp.vbuson_timer);
++00338                         dwc_otg_hcd->core_if->adp.vbuson_timer_started = 0;
++00339                         /* TODO - check if this is required, as
++00340                          * host initialization was already performed
++00341                          * after initial ADP probing
++00342                          */
++00343                         /*dwc_otg_hcd->core_if->adp.vbuson_timer_started = 0;
++00344                         dwc_otg_core_init(dwc_otg_hcd->core_if);
++00345                         dwc_otg_enable_global_interrupts(dwc_otg_hcd->core_if);
++00346                         cil_hcd_start(dwc_otg_hcd->core_if);*/
++00347                 } else {
++00348                 
++00349                         DWC_DEBUGPL(DBG_HCD, "--Port Interrupt HPRT0=0x%08x "
++00350                                     "Port Connect Detected--\n", hprt0.d32);
++00351                         dwc_otg_hcd->flags.b.port_connect_status_change = 1;
++00352                         dwc_otg_hcd->flags.b.port_connect_status = 1;
++00353                         hprt0_modify.b.prtconndet = 1;
++00354         
++00355                         /* B-Device has connected, Delete the connection timer. */
++00356                         DWC_TIMER_CANCEL(dwc_otg_hcd->conn_timer);
++00357                 }
++00358                 /* The Hub driver asserts a reset when it sees port connect
++00359                  * status change flag */
++00360                 retval |= 1;
++00361         }
++00362 
++00363         /* Port Enable Changed
++00364          * Clear if detected - Set internal flag if disabled */
++00365         if (hprt0.b.prtenchng) {
++00366                 DWC_DEBUGPL(DBG_HCD, "  --Port Interrupt HPRT0=0x%08x "
++00367                             "Port Enable Changed--\n", hprt0.d32);
++00368                 hprt0_modify.b.prtenchng = 1;
++00369                 if (hprt0.b.prtena == 1) {
++00370                         hfir_data_t hfir;
++00371                         int do_reset = 0;
++00372                         dwc_otg_core_params_t *params =
++00373                             dwc_otg_hcd->core_if->core_params;
++00374                         dwc_otg_core_global_regs_t *global_regs =
++00375                             dwc_otg_hcd->core_if->core_global_regs;
++00376                         dwc_otg_host_if_t *host_if =
++00377                             dwc_otg_hcd->core_if->host_if;
++00378                             
++00379                         /* Every time when port enables calculate
++00380                          * HFIR.FrInterval
++00381                          */
++00382                         hfir.d32 = DWC_READ_REG32(&host_if->host_global_regs->hfir);
++00383                         hfir.b.frint = calc_frame_interval(dwc_otg_hcd->core_if);
++00384                         DWC_WRITE_REG32(&host_if->host_global_regs->hfir, hfir.d32);
++00385 
++00386                         /* Check if we need to adjust the PHY clock speed for
++00387                          * low power and adjust it */
++00388                         if (params->host_support_fs_ls_low_power) {
++00389                                 gusbcfg_data_t usbcfg;
++00390 
++00391                                 usbcfg.d32 =
++00392                                     DWC_READ_REG32(&global_regs->gusbcfg);
++00393 
++00394                                 if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_LOW_SPEED
++00395                                     || hprt0.b.prtspd ==
++00396                                     DWC_HPRT0_PRTSPD_FULL_SPEED) {
++00397                                         /*
++00398                                          * Low power
++00399                                          */
++00400                                         hcfg_data_t hcfg;
++00401                                         if (usbcfg.b.phylpwrclksel == 0) {
++00402                                                 /* Set PHY low power clock select for FS/LS devices */
++00403                                                 usbcfg.b.phylpwrclksel = 1;
++00404                                                 DWC_WRITE_REG32
++00405                                                     (&global_regs->gusbcfg,
++00406                                                      usbcfg.d32);
++00407                                                 do_reset = 1;
++00408                                         }
++00409 
++00410                                         hcfg.d32 =
++00411                                             DWC_READ_REG32
++00412                                             (&host_if->host_global_regs->hcfg);
++00413 
++00414                                         if (hprt0.b.prtspd ==
++00415                                             DWC_HPRT0_PRTSPD_LOW_SPEED
++00416                                             && params->host_ls_low_power_phy_clk
++00417                                             ==
++00418                                             DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ)
++00419                                         {
++00420                                                 /* 6 MHZ */
++00421                                                 DWC_DEBUGPL(DBG_CIL,
++00422                                                             "FS_PHY programming HCFG to 6 MHz (Low Power)\n");
++00423                                                 if (hcfg.b.fslspclksel !=
++00424                                                     DWC_HCFG_6_MHZ) {
++00425                                                         hcfg.b.fslspclksel =
++00426                                                             DWC_HCFG_6_MHZ;
++00427                                                         DWC_WRITE_REG32
++00428                                                             (&host_if->host_global_regs->hcfg,
++00429                                                              hcfg.d32);
++00430                                                         do_reset = 1;
++00431                                                 }
++00432                                         } else {
++00433                                                 /* 48 MHZ */
++00434                                                 DWC_DEBUGPL(DBG_CIL,
++00435                                                             "FS_PHY programming HCFG to 48 MHz ()\n");
++00436                                                 if (hcfg.b.fslspclksel !=
++00437                                                     DWC_HCFG_48_MHZ) {
++00438                                                         hcfg.b.fslspclksel =
++00439                                                             DWC_HCFG_48_MHZ;
++00440                                                         DWC_WRITE_REG32
++00441                                                             (&host_if->host_global_regs->hcfg,
++00442                                                              hcfg.d32);
++00443                                                         do_reset = 1;
++00444                                                 }
++00445                                         }
++00446                                 } else {
++00447                                         /*
++00448                                          * Not low power
++00449                                          */
++00450                                         if (usbcfg.b.phylpwrclksel == 1) {
++00451                                                 usbcfg.b.phylpwrclksel = 0;
++00452                                                 DWC_WRITE_REG32
++00453                                                     (&global_regs->gusbcfg,
++00454                                                      usbcfg.d32);
++00455                                                 do_reset = 1;
++00456                                         }
++00457                                 }
++00458 
++00459                                 if (do_reset) {
++00460                                         DWC_TASK_SCHEDULE(dwc_otg_hcd->reset_tasklet);
++00461                                 }
++00462                         }
++00463 
++00464                         if (!do_reset) {
++00465                                 /* Port has been enabled set the reset change flag */
++00466                                 dwc_otg_hcd->flags.b.port_reset_change = 1;
++00467                         }
++00468                 } else {
++00469                         dwc_otg_hcd->flags.b.port_enable_change = 1;
++00470                 }
++00471                 retval |= 1;
++00472         }
++00473 
++00475         if (hprt0.b.prtovrcurrchng) {
++00476                 DWC_DEBUGPL(DBG_HCD, "  --Port Interrupt HPRT0=0x%08x "
++00477                             "Port Overcurrent Changed--\n", hprt0.d32);
++00478                 dwc_otg_hcd->flags.b.port_over_current_change = 1;
++00479                 hprt0_modify.b.prtovrcurrchng = 1;
++00480                 retval |= 1;
++00481         }
++00482 
++00483         /* Clear Port Interrupts */
++00484         DWC_WRITE_REG32(dwc_otg_hcd->core_if->host_if->hprt0, hprt0_modify.d32);
++00485 
++00486         return retval;
++00487 }
++00488 
++00493 int32_t dwc_otg_hcd_handle_hc_intr(dwc_otg_hcd_t * dwc_otg_hcd)
++00494 {
++00495         int i;
++00496         int retval = 0;
++00497         haint_data_t haint;
++00498 
++00499         /* Clear appropriate bits in HCINTn to clear the interrupt bit in
++00500          * GINTSTS */
++00501 
++00502         haint.d32 = dwc_otg_read_host_all_channels_intr(dwc_otg_hcd->core_if);
++00503 
++00504         for (i = 0; i < dwc_otg_hcd->core_if->core_params->host_channels; i++) {
++00505                 if (haint.b2.chint & (1 << i)) {
++00506                         retval |= dwc_otg_hcd_handle_hc_n_intr(dwc_otg_hcd, i);
++00507                 }
++00508         }
++00509 
++00510         return retval;
++00511 }
++00512 
++00523 static uint32_t get_actual_xfer_length(dwc_hc_t * hc,
++00524                                        dwc_otg_hc_regs_t * hc_regs,
++00525                                        dwc_otg_qtd_t * qtd,
++00526                                        dwc_otg_halt_status_e halt_status,
++00527                                        int *short_read)
++00528 {
++00529         hctsiz_data_t hctsiz;
++00530         uint32_t length;
++00531 
++00532         if (short_read != NULL) {
++00533                 *short_read = 0;
++00534         }
++00535         hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
++00536 
++00537         if (halt_status == DWC_OTG_HC_XFER_COMPLETE) {
++00538                 if (hc->ep_is_in) {
++00539                         length = hc->xfer_len - hctsiz.b.xfersize;
++00540                         if (short_read != NULL) {
++00541                                 *short_read = (hctsiz.b.xfersize != 0);
++00542                         }
++00543                 } else if (hc->qh->do_split) {
++00544                         length = qtd->ssplit_out_xfer_count;
++00545                 } else {
++00546                         length = hc->xfer_len;
++00547                 }
++00548         } else {
++00549                 /*
++00550                  * Must use the hctsiz.pktcnt field to determine how much data
++00551                  * has been transferred. This field reflects the number of
++00552                  * packets that have been transferred via the USB. This is
++00553                  * always an integral number of packets if the transfer was
++00554                  * halted before its normal completion. (Can't use the
++00555                  * hctsiz.xfersize field because that reflects the number of
++00556                  * bytes transferred via the AHB, not the USB).
++00557                  */
++00558                 length =
++00559                     (hc->start_pkt_count - hctsiz.b.pktcnt) * hc->max_packet;
++00560         }
++00561 
++00562         return length;
++00563 }
++00564 
++00574 static int update_urb_state_xfer_comp(dwc_hc_t * hc,
++00575                                       dwc_otg_hc_regs_t * hc_regs,
++00576                                       dwc_otg_hcd_urb_t * urb,
++00577                                       dwc_otg_qtd_t * qtd)
++00578 {
++00579         int xfer_done = 0;
++00580         int short_read = 0;
++00581 
++00582         int xfer_length;
++00583 
++00584         xfer_length = get_actual_xfer_length(hc, hc_regs, qtd,
++00585                                              DWC_OTG_HC_XFER_COMPLETE,
++00586                                              &short_read);
++00587 
++00588 
++00589         /* non DWORD-aligned buffer case handling. */
++00590         if (hc->align_buff && xfer_length && hc->ep_is_in) {
++00591                 dwc_memcpy(urb->buf + urb->actual_length, hc->qh->dw_align_buf,
++00592                            xfer_length);
++00593         }
++00594 
++00595         urb->actual_length += xfer_length;
++00596 
++00597         if (xfer_length && (hc->ep_type == DWC_OTG_EP_TYPE_BULK) &&
++00598             (urb->flags & URB_SEND_ZERO_PACKET)
++00599             && (urb->actual_length == urb->length)
++00600             && !(urb->length % hc->max_packet)) {
++00601                 xfer_done = 0;
++00602         } else if (short_read || urb->actual_length == urb->length) {
++00603                 xfer_done = 1;
++00604                 urb->status = 0;
++00605         }
++00606         
++00607 #ifdef DEBUG
++00608         {
++00609                 hctsiz_data_t hctsiz;
++00610                 hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
++00611                 DWC_DEBUGPL(DBG_HCDV, "DWC_otg: %s: %s, channel %d\n",
++00612                             __func__, (hc->ep_is_in ? "IN" : "OUT"),
++00613                             hc->hc_num);
++00614                 DWC_DEBUGPL(DBG_HCDV, "  hc->xfer_len %d\n", hc->xfer_len);
++00615                 DWC_DEBUGPL(DBG_HCDV, "  hctsiz.xfersize %d\n",
++00616                             hctsiz.b.xfersize);
++00617                 DWC_DEBUGPL(DBG_HCDV, "  urb->transfer_buffer_length %d\n",
++00618                             urb->length);
++00619                 DWC_DEBUGPL(DBG_HCDV, "  urb->actual_length %d\n",
++00620                             urb->actual_length);
++00621                 DWC_DEBUGPL(DBG_HCDV, "  short_read %d, xfer_done %d\n",
++00622                             short_read, xfer_done);
++00623         }
++00624 #endif
++00625 
++00626         return xfer_done;
++00627 }
++00628 
++00629 /*
++00630  * Save the starting data toggle for the next transfer. The data toggle is
++00631  * saved in the QH for non-control transfers and it's saved in the QTD for
++00632  * control transfers.
++00633  */
++00634 void dwc_otg_hcd_save_data_toggle(dwc_hc_t * hc,
++00635                              dwc_otg_hc_regs_t * hc_regs, dwc_otg_qtd_t * qtd)
++00636 {
++00637         hctsiz_data_t hctsiz;
++00638         hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
++00639 
++00640         if (hc->ep_type != DWC_OTG_EP_TYPE_CONTROL) {
++00641                 dwc_otg_qh_t *qh = hc->qh;
++00642                 if (hctsiz.b.pid == DWC_HCTSIZ_DATA0) {
++00643                         qh->data_toggle = DWC_OTG_HC_PID_DATA0;
++00644                 } else {
++00645                         qh->data_toggle = DWC_OTG_HC_PID_DATA1;
++00646                 }
++00647         } else {
++00648                 if (hctsiz.b.pid == DWC_HCTSIZ_DATA0) {
++00649                         qtd->data_toggle = DWC_OTG_HC_PID_DATA0;
++00650                 } else {
++00651                         qtd->data_toggle = DWC_OTG_HC_PID_DATA1;
++00652                 }
++00653         }
++00654 }
++00655 
++00665 static dwc_otg_halt_status_e
++00666 update_isoc_urb_state(dwc_otg_hcd_t * hcd,
++00667                       dwc_hc_t * hc,
++00668                       dwc_otg_hc_regs_t * hc_regs,
++00669                       dwc_otg_qtd_t * qtd, dwc_otg_halt_status_e halt_status)
++00670 {
++00671         dwc_otg_hcd_urb_t *urb = qtd->urb;
++00672         dwc_otg_halt_status_e ret_val = halt_status;
++00673         struct dwc_otg_hcd_iso_packet_desc *frame_desc;
++00674 
++00675         frame_desc = &urb->iso_descs[qtd->isoc_frame_index];
++00676         switch (halt_status) {
++00677         case DWC_OTG_HC_XFER_COMPLETE:
++00678                 frame_desc->status = 0;
++00679                 frame_desc->actual_length =
++00680                     get_actual_xfer_length(hc, hc_regs, qtd, halt_status, NULL);
++00681 
++00682                 /* non DWORD-aligned buffer case handling. */
++00683                 if (hc->align_buff && frame_desc->actual_length && hc->ep_is_in) {
++00684                         dwc_memcpy(urb->buf + frame_desc->offset + qtd->isoc_split_offset,
++00685                                    hc->qh->dw_align_buf, frame_desc->actual_length);
++00686                 }
++00687                 
++00688                 break;
++00689         case DWC_OTG_HC_XFER_FRAME_OVERRUN:
++00690                 urb->error_count++;
++00691                 if (hc->ep_is_in) {
++00692                         frame_desc->status = -DWC_E_NO_STREAM_RES;
++00693                 } else {
++00694                         frame_desc->status = -DWC_E_COMMUNICATION;
++00695                 }
++00696                 frame_desc->actual_length = 0;
++00697                 break;
++00698         case DWC_OTG_HC_XFER_BABBLE_ERR:
++00699                 urb->error_count++;
++00700                 frame_desc->status = -DWC_E_OVERFLOW;
++00701                 /* Don't need to update actual_length in this case. */
++00702                 break;
++00703         case DWC_OTG_HC_XFER_XACT_ERR:
++00704                 urb->error_count++;
++00705                 frame_desc->status = -DWC_E_PROTOCOL;
++00706                 frame_desc->actual_length =
++00707                     get_actual_xfer_length(hc, hc_regs, qtd, halt_status, NULL);
++00708 
++00709                 /* non DWORD-aligned buffer case handling. */
++00710                 if (hc->align_buff && frame_desc->actual_length && hc->ep_is_in) {
++00711                         dwc_memcpy(urb->buf + frame_desc->offset + qtd->isoc_split_offset,
++00712                                    hc->qh->dw_align_buf, frame_desc->actual_length);
++00713                 }
++00714                 /* Skip whole frame */
++00715                 if (hc->qh->do_split && (hc->ep_type == DWC_OTG_EP_TYPE_ISOC) &&
++00716                     hc->ep_is_in && hcd->core_if->dma_enable) {
++00717                         qtd->complete_split = 0;
++00718                         qtd->isoc_split_offset = 0;
++00719                 }
++00720 
++00721                 break;
++00722         default:
++00723                 DWC_ASSERT(1, "Unhandled _halt_status (%d)\n", halt_status);
++00724                 break;
++00725         }
++00726         if (++qtd->isoc_frame_index == urb->packet_count) {
++00727                 /*
++00728                  * urb->status is not used for isoc transfers.
++00729                  * The individual frame_desc statuses are used instead.
++00730                  */
++00731                 hcd->fops->complete(hcd, urb->priv, urb, 0);
++00732                 ret_val = DWC_OTG_HC_XFER_URB_COMPLETE;
++00733         } else {
++00734                 ret_val = DWC_OTG_HC_XFER_COMPLETE;
++00735         }
++00736         return ret_val;
++00737 }
++00738 
++00746 static void deactivate_qh(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh, int free_qtd)
++00747 {
++00748         int continue_split = 0;
++00749         dwc_otg_qtd_t *qtd;
++00750 
++00751         DWC_DEBUGPL(DBG_HCDV, "  %s(%p,%p,%d)\n", __func__, hcd, qh, free_qtd);
++00752 
++00753         qtd = DWC_CIRCLEQ_FIRST(&qh->qtd_list);
++00754 
++00755         if (qtd->complete_split) {
++00756                 continue_split = 1;
++00757         } else if (qtd->isoc_split_pos == DWC_HCSPLIT_XACTPOS_MID ||
++00758                    qtd->isoc_split_pos == DWC_HCSPLIT_XACTPOS_END) {
++00759                 continue_split = 1;
++00760         }
++00761 
++00762         if (free_qtd) {
++00763                 dwc_otg_hcd_qtd_remove_and_free(hcd, qtd, qh);
++00764                 continue_split = 0;
++00765         }
++00766 
++00767         qh->channel = NULL;
++00768         dwc_otg_hcd_qh_deactivate(hcd, qh, continue_split);
++00769 }
++00770 
++00782 static void release_channel(dwc_otg_hcd_t * hcd,
++00783                             dwc_hc_t * hc,
++00784                             dwc_otg_qtd_t * qtd,
++00785                             dwc_otg_halt_status_e halt_status)
++00786 {
++00787         dwc_otg_transaction_type_e tr_type;
++00788         int free_qtd;
++00789 
++00790         DWC_DEBUGPL(DBG_HCDV, "  %s: channel %d, halt_status %d\n",
++00791                     __func__, hc->hc_num, halt_status);
++00792 
++00793         switch (halt_status) {
++00794         case DWC_OTG_HC_XFER_URB_COMPLETE:
++00795                 free_qtd = 1;
++00796                 break;
++00797         case DWC_OTG_HC_XFER_AHB_ERR:
++00798         case DWC_OTG_HC_XFER_STALL:
++00799         case DWC_OTG_HC_XFER_BABBLE_ERR:
++00800                 free_qtd = 1;
++00801                 break;
++00802         case DWC_OTG_HC_XFER_XACT_ERR:
++00803                 if (qtd->error_count >= 3) {
++00804                         DWC_DEBUGPL(DBG_HCDV,
++00805                                     "  Complete URB with transaction error\n");
++00806                         free_qtd = 1;
++00807                         qtd->urb->status = -DWC_E_PROTOCOL;
++00808                         hcd->fops->complete(hcd, qtd->urb->priv,
++00809                                             qtd->urb, -DWC_E_PROTOCOL);
++00810                 } else {
++00811                         free_qtd = 0;
++00812                 }
++00813                 break;
++00814         case DWC_OTG_HC_XFER_URB_DEQUEUE:
++00815                 /*
++00816                  * The QTD has already been removed and the QH has been
++00817                  * deactivated. Don't want to do anything except release the
++00818                  * host channel and try to queue more transfers.
++00819                  */
++00820                 goto cleanup;
++00821         case DWC_OTG_HC_XFER_NO_HALT_STATUS:
++00822                 free_qtd = 0;
++00823                 break;
++00824         case DWC_OTG_HC_XFER_PERIODIC_INCOMPLETE:
++00825                 DWC_DEBUGPL(DBG_HCDV,
++00826                         "  Complete URB with I/O error\n");
++00827                 free_qtd = 1;
++00828                 qtd->urb->status = -DWC_E_IO;
++00829                 hcd->fops->complete(hcd, qtd->urb->priv,
++00830                         qtd->urb, -DWC_E_IO);
++00831                 break;
++00832         default:
++00833                 free_qtd = 0;
++00834                 break;
++00835         }
++00836 
++00837         deactivate_qh(hcd, hc->qh, free_qtd);
++00838 
++00839 cleanup:
++00840         /*
++00841          * Release the host channel for use by other transfers. The cleanup
++00842          * function clears the channel interrupt enables and conditions, so
++00843          * there's no need to clear the Channel Halted interrupt separately.
++00844          */
++00845         dwc_otg_hc_cleanup(hcd->core_if, hc);
++00846         DWC_CIRCLEQ_INSERT_TAIL(&hcd->free_hc_list, hc, hc_list_entry);
++00847 
++00848         switch (hc->ep_type) {
++00849         case DWC_OTG_EP_TYPE_CONTROL:
++00850         case DWC_OTG_EP_TYPE_BULK:
++00851                 hcd->non_periodic_channels--;
++00852                 break;
++00853 
++00854         default:
++00855                 /*
++00856                  * Don't release reservations for periodic channels here.
++00857                  * That's done when a periodic transfer is descheduled (i.e.
++00858                  * when the QH is removed from the periodic schedule).
++00859                  */
++00860                 break;
++00861         }
++00862 
++00863         /* Try to queue more transfers now that there's a free channel. */
++00864         tr_type = dwc_otg_hcd_select_transactions(hcd);
++00865         if (tr_type != DWC_OTG_TRANSACTION_NONE) {
++00866                 dwc_otg_hcd_queue_transactions(hcd, tr_type);
++00867         }
++00868 }
++00869 
++00880 static void halt_channel(dwc_otg_hcd_t * hcd,
++00881                          dwc_hc_t * hc,
++00882                          dwc_otg_qtd_t * qtd, dwc_otg_halt_status_e halt_status)
++00883 {
++00884         if (hcd->core_if->dma_enable) {
++00885                 release_channel(hcd, hc, qtd, halt_status);
++00886                 return;
++00887         }
++00888 
++00889         /* Slave mode processing... */
++00890         dwc_otg_hc_halt(hcd->core_if, hc, halt_status);
++00891 
++00892         if (hc->halt_on_queue) {
++00893                 gintmsk_data_t gintmsk = {.d32 = 0 };
++00894                 dwc_otg_core_global_regs_t *global_regs;
++00895                 global_regs = hcd->core_if->core_global_regs;
++00896 
++00897                 if (hc->ep_type == DWC_OTG_EP_TYPE_CONTROL ||
++00898                     hc->ep_type == DWC_OTG_EP_TYPE_BULK) {
++00899                         /*
++00900                          * Make sure the Non-periodic Tx FIFO empty interrupt
++00901                          * is enabled so that the non-periodic schedule will
++00902                          * be processed.
++00903                          */
++00904                         gintmsk.b.nptxfempty = 1;
++00905                         DWC_MODIFY_REG32(&global_regs->gintmsk, 0, gintmsk.d32);
++00906                 } else {
++00907                         /*
++00908                          * Move the QH from the periodic queued schedule to
++00909                          * the periodic assigned schedule. This allows the
++00910                          * halt to be queued when the periodic schedule is
++00911                          * processed.
++00912                          */
++00913                         DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_assigned,
++00914                                            &hc->qh->qh_list_entry);
++00915 
++00916                         /*
++00917                          * Make sure the Periodic Tx FIFO Empty interrupt is
++00918                          * enabled so that the periodic schedule will be
++00919                          * processed.
++00920                          */
++00921                         gintmsk.b.ptxfempty = 1;
++00922                         DWC_MODIFY_REG32(&global_regs->gintmsk, 0, gintmsk.d32);
++00923                 }
++00924         }
++00925 }
++00926 
++00932 static void complete_non_periodic_xfer(dwc_otg_hcd_t * hcd,
++00933                                        dwc_hc_t * hc,
++00934                                        dwc_otg_hc_regs_t * hc_regs,
++00935                                        dwc_otg_qtd_t * qtd,
++00936                                        dwc_otg_halt_status_e halt_status)
++00937 {
++00938         hcint_data_t hcint;
++00939 
++00940         qtd->error_count = 0;
++00941 
++00942         hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
++00943         if (hcint.b.nyet) {
++00944                 /*
++00945                  * Got a NYET on the last transaction of the transfer. This
++00946                  * means that the endpoint should be in the PING state at the
++00947                  * beginning of the next transfer.
++00948                  */
++00949                 hc->qh->ping_state = 1;
++00950                 clear_hc_int(hc_regs, nyet);
++00951         }
++00952 
++00953         /*
++00954          * Always halt and release the host channel to make it available for
++00955          * more transfers. There may still be more phases for a control
++00956          * transfer or more data packets for a bulk transfer at this point,
++00957          * but the host channel is still halted. A channel will be reassigned
++00958          * to the transfer when the non-periodic schedule is processed after
++00959          * the channel is released. This allows transactions to be queued
++00960          * properly via dwc_otg_hcd_queue_transactions, which also enables the
++00961          * Tx FIFO Empty interrupt if necessary.
++00962          */
++00963         if (hc->ep_is_in) {
++00964                 /*
++00965                  * IN transfers in Slave mode require an explicit disable to
++00966                  * halt the channel. (In DMA mode, this call simply releases
++00967                  * the channel.)
++00968                  */
++00969                 halt_channel(hcd, hc, qtd, halt_status);
++00970         } else {
++00971                 /*
++00972                  * The channel is automatically disabled by the core for OUT
++00973                  * transfers in Slave mode.
++00974                  */
++00975                 release_channel(hcd, hc, qtd, halt_status);
++00976         }
++00977 }
++00978 
++00984 static void complete_periodic_xfer(dwc_otg_hcd_t * hcd,
++00985                                    dwc_hc_t * hc,
++00986                                    dwc_otg_hc_regs_t * hc_regs,
++00987                                    dwc_otg_qtd_t * qtd,
++00988                                    dwc_otg_halt_status_e halt_status)
++00989 {
++00990         hctsiz_data_t hctsiz;
++00991         qtd->error_count = 0;
++00992 
++00993         hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
++00994         if (!hc->ep_is_in || hctsiz.b.pktcnt == 0) {
++00995                 /* Core halts channel in these cases. */
++00996                 release_channel(hcd, hc, qtd, halt_status);
++00997         } else {
++00998                 /* Flush any outstanding requests from the Tx queue. */
++00999                 halt_channel(hcd, hc, qtd, halt_status);
++01000         }
++01001 }
++01002 
++01003 static int32_t handle_xfercomp_isoc_split_in(dwc_otg_hcd_t * hcd,
++01004                                              dwc_hc_t * hc,
++01005                                              dwc_otg_hc_regs_t * hc_regs,
++01006                                              dwc_otg_qtd_t * qtd)
++01007 {
++01008         uint32_t len;
++01009         struct dwc_otg_hcd_iso_packet_desc *frame_desc;
++01010         frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index];
++01011 
++01012         len = get_actual_xfer_length(hc, hc_regs, qtd,
++01013                                      DWC_OTG_HC_XFER_COMPLETE, NULL);
++01014 
++01015         if (!len) {
++01016                 qtd->complete_split = 0;
++01017                 qtd->isoc_split_offset = 0;
++01018                 return 0;
++01019         }
++01020         frame_desc->actual_length += len;
++01021 
++01022         if (hc->align_buff && len)
++01023                 dwc_memcpy(qtd->urb->buf + frame_desc->offset +
++01024                            qtd->isoc_split_offset, hc->qh->dw_align_buf, len);
++01025         qtd->isoc_split_offset += len;
++01026 
++01027         if (frame_desc->length == frame_desc->actual_length) {
++01028                 frame_desc->status = 0;
++01029                 qtd->isoc_frame_index++;
++01030                 qtd->complete_split = 0;
++01031                 qtd->isoc_split_offset = 0;
++01032         }
++01033 
++01034         if (qtd->isoc_frame_index == qtd->urb->packet_count) {
++01035                 hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, 0);
++01036                 release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE);
++01037         } else {
++01038                 release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NO_HALT_STATUS);
++01039         }
++01040 
++01041         return 1;               /* Indicates that channel released */
++01042 }
++01043 
++01048 static int32_t handle_hc_xfercomp_intr(dwc_otg_hcd_t * hcd,
++01049                                        dwc_hc_t * hc,
++01050                                        dwc_otg_hc_regs_t * hc_regs,
++01051                                        dwc_otg_qtd_t * qtd)
++01052 {
++01053         int urb_xfer_done;
++01054         dwc_otg_halt_status_e halt_status = DWC_OTG_HC_XFER_COMPLETE;
++01055         dwc_otg_hcd_urb_t *urb = qtd->urb;
++01056         int pipe_type = dwc_otg_hcd_get_pipe_type(&urb->pipe_info);
++01057 
++01058         DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
++01059                     "Transfer Complete--\n", hc->hc_num);
++01060 
++01061         if (hcd->core_if->dma_desc_enable) {
++01062                 dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs, halt_status);
++01063                 if (pipe_type == UE_ISOCHRONOUS) {
++01064                         /* Do not disable the interrupt, just clear it */
++01065                         clear_hc_int(hc_regs, xfercomp);
++01066                         return 1;
++01067                 }
++01068                 goto handle_xfercomp_done;
++01069         }
++01070 
++01071         /*
++01072          * Handle xfer complete on CSPLIT.
++01073          */
++01074 
++01075         if (hc->qh->do_split) {
++01076                 if ((hc->ep_type == DWC_OTG_EP_TYPE_ISOC) && hc->ep_is_in
++01077                     && hcd->core_if->dma_enable) {
++01078                         if (qtd->complete_split
++01079                             && handle_xfercomp_isoc_split_in(hcd, hc, hc_regs,
++01080                                                              qtd))
++01081                                 goto handle_xfercomp_done;
++01082                 } else {
++01083                         qtd->complete_split = 0;
++01084                 }
++01085         }
++01086 
++01087         /* Update the QTD and URB states. */
++01088         switch (pipe_type) {
++01089         case UE_CONTROL:
++01090                 switch (qtd->control_phase) {
++01091                 case DWC_OTG_CONTROL_SETUP:
++01092                         if (urb->length > 0) {
++01093                                 qtd->control_phase = DWC_OTG_CONTROL_DATA;
++01094                         } else {
++01095                                 qtd->control_phase = DWC_OTG_CONTROL_STATUS;
++01096                         }
++01097                         DWC_DEBUGPL(DBG_HCDV,
++01098                                     "  Control setup transaction done\n");
++01099                         halt_status = DWC_OTG_HC_XFER_COMPLETE;
++01100                         break;
++01101                 case DWC_OTG_CONTROL_DATA:{
++01102                                 urb_xfer_done =
++01103                                     update_urb_state_xfer_comp(hc, hc_regs, urb,
++01104                                                                qtd);
++01105                                 if (urb_xfer_done) {
++01106                                         qtd->control_phase =
++01107                                             DWC_OTG_CONTROL_STATUS;
++01108                                         DWC_DEBUGPL(DBG_HCDV,
++01109                                                     "  Control data transfer done\n");
++01110                                 } else {
++01111                                         dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
++01112                                 }
++01113                                 halt_status = DWC_OTG_HC_XFER_COMPLETE;
++01114                                 break;
++01115                         }
++01116                 case DWC_OTG_CONTROL_STATUS:
++01117                         DWC_DEBUGPL(DBG_HCDV, "  Control transfer complete\n");
++01118                         if (urb->status == -DWC_E_IN_PROGRESS) {
++01119                                 urb->status = 0;
++01120                         }
++01121                         hcd->fops->complete(hcd, urb->priv, urb, urb->status);
++01122                         halt_status = DWC_OTG_HC_XFER_URB_COMPLETE;
++01123                         break;
++01124                 }
++01125 
++01126                 complete_non_periodic_xfer(hcd, hc, hc_regs, qtd, halt_status);
++01127                 break;
++01128         case UE_BULK:
++01129                 DWC_DEBUGPL(DBG_HCDV, "  Bulk transfer complete\n");
++01130                 urb_xfer_done =
++01131                     update_urb_state_xfer_comp(hc, hc_regs, urb, qtd);
++01132                 if (urb_xfer_done) {
++01133                         hcd->fops->complete(hcd, urb->priv, urb, urb->status);
++01134                         halt_status = DWC_OTG_HC_XFER_URB_COMPLETE;
++01135                 } else {
++01136                         halt_status = DWC_OTG_HC_XFER_COMPLETE;
++01137                 }
++01138 
++01139                 dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
++01140                 complete_non_periodic_xfer(hcd, hc, hc_regs, qtd, halt_status);
++01141                 break;
++01142         case UE_INTERRUPT:
++01143                 DWC_DEBUGPL(DBG_HCDV, "  Interrupt transfer complete\n");
++01144                 urb_xfer_done =
++01145                         update_urb_state_xfer_comp(hc, hc_regs, urb, qtd);
++01146 
++01147                 /*
++01148                  * Interrupt URB is done on the first transfer complete
++01149                  * interrupt.
++01150                  */
++01151                 if (urb_xfer_done) {
++01152                                 hcd->fops->complete(hcd, urb->priv, urb, urb->status);
++01153                                 halt_status = DWC_OTG_HC_XFER_URB_COMPLETE;
++01154                 } else {
++01155                                 halt_status = DWC_OTG_HC_XFER_COMPLETE;
++01156                 }
++01157 
++01158                 dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
++01159                 complete_periodic_xfer(hcd, hc, hc_regs, qtd, halt_status);
++01160                 break;
++01161         case UE_ISOCHRONOUS:
++01162                 DWC_DEBUGPL(DBG_HCDV, "  Isochronous transfer complete\n");
++01163                 if (qtd->isoc_split_pos == DWC_HCSPLIT_XACTPOS_ALL) {
++01164                         halt_status =
++01165                             update_isoc_urb_state(hcd, hc, hc_regs, qtd,
++01166                                                   DWC_OTG_HC_XFER_COMPLETE);
++01167                 }
++01168                 complete_periodic_xfer(hcd, hc, hc_regs, qtd, halt_status);
++01169                 break;
++01170         }
++01171 
++01172 handle_xfercomp_done:
++01173         disable_hc_int(hc_regs, xfercompl);
++01174 
++01175         return 1;
++01176 }
++01177 
++01182 static int32_t handle_hc_stall_intr(dwc_otg_hcd_t * hcd,
++01183                                     dwc_hc_t * hc,
++01184                                     dwc_otg_hc_regs_t * hc_regs,
++01185                                     dwc_otg_qtd_t * qtd)
++01186 {
++01187         dwc_otg_hcd_urb_t *urb = qtd->urb;
++01188         int pipe_type = dwc_otg_hcd_get_pipe_type(&urb->pipe_info);
++01189 
++01190         DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
++01191                     "STALL Received--\n", hc->hc_num);
++01192 
++01193         if (hcd->core_if->dma_desc_enable) {
++01194                 dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs, DWC_OTG_HC_XFER_STALL);
++01195                 goto handle_stall_done;
++01196         }
++01197 
++01198         if (pipe_type == UE_CONTROL) {
++01199                 hcd->fops->complete(hcd, urb->priv, urb, -DWC_E_PIPE);
++01200         }
++01201 
++01202         if (pipe_type == UE_BULK || pipe_type == UE_INTERRUPT) {
++01203                 hcd->fops->complete(hcd, urb->priv, urb, -DWC_E_PIPE);
++01204                 /*
++01205                  * USB protocol requires resetting the data toggle for bulk
++01206                  * and interrupt endpoints when a CLEAR_FEATURE(ENDPOINT_HALT)
++01207                  * setup command is issued to the endpoint. Anticipate the
++01208                  * CLEAR_FEATURE command since a STALL has occurred and reset
++01209                  * the data toggle now.
++01210                  */
++01211                 hc->qh->data_toggle = 0;
++01212         }
++01213 
++01214         halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_STALL);
++01215 
++01216 handle_stall_done:
++01217         disable_hc_int(hc_regs, stall);
++01218 
++01219         return 1;
++01220 }
++01221 
++01222 /*
++01223  * Updates the state of the URB when a transfer has been stopped due to an
++01224  * abnormal condition before the transfer completes. Modifies the
++01225  * actual_length field of the URB to reflect the number of bytes that have
++01226  * actually been transferred via the host channel.
++01227  */
++01228 static void update_urb_state_xfer_intr(dwc_hc_t * hc,
++01229                                        dwc_otg_hc_regs_t * hc_regs,
++01230                                        dwc_otg_hcd_urb_t * urb,
++01231                                        dwc_otg_qtd_t * qtd,
++01232                                        dwc_otg_halt_status_e halt_status)
++01233 {
++01234         uint32_t bytes_transferred = get_actual_xfer_length(hc, hc_regs, qtd,
++01235                                                             halt_status, NULL);
++01236         /* non DWORD-aligned buffer case handling. */
++01237         if (hc->align_buff && bytes_transferred && hc->ep_is_in) {
++01238                 dwc_memcpy(urb->buf + urb->actual_length, hc->qh->dw_align_buf,
++01239                            bytes_transferred);
++01240         }
++01241 
++01242         urb->actual_length += bytes_transferred;
++01243 
++01244 #ifdef DEBUG
++01245         {
++01246                 hctsiz_data_t hctsiz;
++01247                 hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
++01248                 DWC_DEBUGPL(DBG_HCDV, "DWC_otg: %s: %s, channel %d\n",
++01249                             __func__, (hc->ep_is_in ? "IN" : "OUT"),
++01250                             hc->hc_num);
++01251                 DWC_DEBUGPL(DBG_HCDV, "  hc->start_pkt_count %d\n",
++01252                             hc->start_pkt_count);
++01253                 DWC_DEBUGPL(DBG_HCDV, "  hctsiz.pktcnt %d\n", hctsiz.b.pktcnt);
++01254                 DWC_DEBUGPL(DBG_HCDV, "  hc->max_packet %d\n", hc->max_packet);
++01255                 DWC_DEBUGPL(DBG_HCDV, "  bytes_transferred %d\n",
++01256                             bytes_transferred);
++01257                 DWC_DEBUGPL(DBG_HCDV, "  urb->actual_length %d\n",
++01258                             urb->actual_length);
++01259                 DWC_DEBUGPL(DBG_HCDV, "  urb->transfer_buffer_length %d\n",
++01260                             urb->length);
++01261         }
++01262 #endif
++01263 }
++01264 
++01269 static int32_t handle_hc_nak_intr(dwc_otg_hcd_t * hcd,
++01270                                   dwc_hc_t * hc,
++01271                                   dwc_otg_hc_regs_t * hc_regs,
++01272                                   dwc_otg_qtd_t * qtd)
++01273 {
++01274         DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
++01275                     "NAK Received--\n", hc->hc_num);
++01276 
++01277         /*
++01278          * Handle NAK for IN/OUT SSPLIT/CSPLIT transfers, bulk, control, and
++01279          * interrupt.  Re-start the SSPLIT transfer.
++01280          */
++01281         if (hc->do_split) {
++01282                 if (hc->complete_split) {
++01283                         qtd->error_count = 0;
++01284                 }
++01285                 qtd->complete_split = 0;
++01286                 halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NAK);
++01287                 goto handle_nak_done;
++01288         }
++01289 
++01290         switch (dwc_otg_hcd_get_pipe_type(&qtd->urb->pipe_info)) {
++01291         case UE_CONTROL:
++01292         case UE_BULK:
++01293                 if (hcd->core_if->dma_enable && hc->ep_is_in) {
++01294                         /*
++01295                          * NAK interrupts are enabled on bulk/control IN
++01296                          * transfers in DMA mode for the sole purpose of
++01297                          * resetting the error count after a transaction error
++01298                          * occurs. The core will continue transferring data.
++01299                          */
++01300                         qtd->error_count = 0;
++01301                         goto handle_nak_done;
++01302                 }
++01303 
++01304                 /*
++01305                  * NAK interrupts normally occur during OUT transfers in DMA
++01306                  * or Slave mode. For IN transfers, more requests will be
++01307                  * queued as request queue space is available.
++01308                  */
++01309                 qtd->error_count = 0;
++01310 
++01311                 if (!hc->qh->ping_state) {
++01312                         update_urb_state_xfer_intr(hc, hc_regs,
++01313                                                    qtd->urb, qtd,
++01314                                                    DWC_OTG_HC_XFER_NAK);
++01315                         dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
++01316 
++01317                         if (hc->speed == DWC_OTG_EP_SPEED_HIGH)
++01318                                 hc->qh->ping_state = 1;
++01319                 }
++01320 
++01321                 /*
++01322                  * Halt the channel so the transfer can be re-started from
++01323                  * the appropriate point or the PING protocol will
++01324                  * start/continue.
++01325                  */
++01326                 halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NAK);
++01327                 break;
++01328         case UE_INTERRUPT:
++01329                 qtd->error_count = 0;
++01330                 halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NAK);
++01331                 break;
++01332         case UE_ISOCHRONOUS:
++01333                 /* Should never get called for isochronous transfers. */
++01334                 DWC_ASSERT(1, "NACK interrupt for ISOC transfer\n");
++01335                 break;
++01336         }
++01337 
++01338 handle_nak_done:
++01339         disable_hc_int(hc_regs, nak);
++01340 
++01341         return 1;
++01342 }
++01343 
++01349 static int32_t handle_hc_ack_intr(dwc_otg_hcd_t * hcd,
++01350                                   dwc_hc_t * hc,
++01351                                   dwc_otg_hc_regs_t * hc_regs,
++01352                                   dwc_otg_qtd_t * qtd)
++01353 {
++01354         DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
++01355                     "ACK Received--\n", hc->hc_num);
++01356 
++01357         if (hc->do_split) {
++01358                 /*
++01359                  * Handle ACK on SSPLIT.
++01360                  * ACK should not occur in CSPLIT.
++01361                  */
++01362                 if (!hc->ep_is_in && hc->data_pid_start != DWC_OTG_HC_PID_SETUP) {
++01363                         qtd->ssplit_out_xfer_count = hc->xfer_len;
++01364                 }
++01365                 if (!(hc->ep_type == DWC_OTG_EP_TYPE_ISOC && !hc->ep_is_in)) {
++01366                         /* Don't need complete for isochronous out transfers. */
++01367                         qtd->complete_split = 1;
++01368                 }
++01369 
++01370                 /* ISOC OUT */
++01371                 if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC && !hc->ep_is_in) {
++01372                         switch (hc->xact_pos) {
++01373                         case DWC_HCSPLIT_XACTPOS_ALL:
++01374                                 break;
++01375                         case DWC_HCSPLIT_XACTPOS_END:
++01376                                 qtd->isoc_split_pos = DWC_HCSPLIT_XACTPOS_ALL;
++01377                                 qtd->isoc_split_offset = 0;
++01378                                 break;
++01379                         case DWC_HCSPLIT_XACTPOS_BEGIN:
++01380                         case DWC_HCSPLIT_XACTPOS_MID:
++01381                                 /*
++01382                                  * For BEGIN or MID, calculate the length for
++01383                                  * the next microframe to determine the correct
++01384                                  * SSPLIT token, either MID or END.
++01385                                  */
++01386                                 {
++01387                                         struct dwc_otg_hcd_iso_packet_desc
++01388                                         *frame_desc;
++01389 
++01390                                         frame_desc =
++01391                                             &qtd->urb->
++01392                                             iso_descs[qtd->isoc_frame_index];
++01393                                         qtd->isoc_split_offset += 188;
++01394 
++01395                                         if ((frame_desc->length -
++01396                                              qtd->isoc_split_offset) <= 188) {
++01397                                                 qtd->isoc_split_pos =
++01398                                                     DWC_HCSPLIT_XACTPOS_END;
++01399                                         } else {
++01400                                                 qtd->isoc_split_pos =
++01401                                                     DWC_HCSPLIT_XACTPOS_MID;
++01402                                         }
++01403 
++01404                                 }
++01405                                 break;
++01406                         }
++01407                 } else {
++01408                         halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_ACK);
++01409                 }
++01410         } else {
++01411                 qtd->error_count = 0;
++01412 
++01413                 if (hc->qh->ping_state) {
++01414                         hc->qh->ping_state = 0;
++01415                         /*
++01416                          * Halt the channel so the transfer can be re-started
++01417                          * from the appropriate point. This only happens in
++01418                          * Slave mode. In DMA mode, the ping_state is cleared
++01419                          * when the transfer is started because the core
++01420                          * automatically executes the PING, then the transfer.
++01421                          */
++01422                         halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_ACK);
++01423                 }
++01424         }
++01425 
++01426         /*
++01427          * If the ACK occurred when _not_ in the PING state, let the channel
++01428          * continue transferring data after clearing the error count.
++01429          */
++01430 
++01431         disable_hc_int(hc_regs, ack);
++01432 
++01433         return 1;
++01434 }
++01435 
++01443 static int32_t handle_hc_nyet_intr(dwc_otg_hcd_t * hcd,
++01444                                    dwc_hc_t * hc,
++01445                                    dwc_otg_hc_regs_t * hc_regs,
++01446                                    dwc_otg_qtd_t * qtd)
++01447 {
++01448         DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
++01449                     "NYET Received--\n", hc->hc_num);
++01450 
++01451         /*
++01452          * NYET on CSPLIT
++01453          * re-do the CSPLIT immediately on non-periodic
++01454          */
++01455         if (hc->do_split && hc->complete_split) {
++01456                 if (hc->ep_is_in && (hc->ep_type == DWC_OTG_EP_TYPE_ISOC)
++01457                     && hcd->core_if->dma_enable) {
++01458                         qtd->complete_split = 0;
++01459                         qtd->isoc_split_offset = 0;
++01460                         if (++qtd->isoc_frame_index == qtd->urb->packet_count) {
++01461                                 hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, 0);
++01462                                 release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE);    
++01463                         }
++01464                         else
++01465                                 release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NO_HALT_STATUS);  
++01466                         goto handle_nyet_done;
++01467                 }
++01468                 
++01469                 if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
++01470                     hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
++01471                         int frnum = dwc_otg_hcd_get_frame_number(hcd);
++01472 
++01473                         if (dwc_full_frame_num(frnum) !=
++01474                             dwc_full_frame_num(hc->qh->sched_frame)) {
++01475                                 /*
++01476                                  * No longer in the same full speed frame.
++01477                                  * Treat this as a transaction error.
++01478                                  */
++01479 #if 0
++01480 
++01486                                 qtd->error_count++;
++01487 #endif
++01488                                 qtd->complete_split = 0;
++01489                                 halt_channel(hcd, hc, qtd,
++01490                                              DWC_OTG_HC_XFER_XACT_ERR);
++01492                                 goto handle_nyet_done;
++01493                         }
++01494                 }
++01495 
++01496                 halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NYET);
++01497                 goto handle_nyet_done;
++01498         }
++01499 
++01500         hc->qh->ping_state = 1;
++01501         qtd->error_count = 0;
++01502 
++01503         update_urb_state_xfer_intr(hc, hc_regs, qtd->urb, qtd,
++01504                                    DWC_OTG_HC_XFER_NYET);
++01505         dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
++01506 
++01507         /*
++01508          * Halt the channel and re-start the transfer so the PING
++01509          * protocol will start.
++01510          */
++01511         halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NYET);
++01512 
++01513 handle_nyet_done:
++01514         disable_hc_int(hc_regs, nyet);
++01515         return 1;
++01516 }
++01517 
++01522 static int32_t handle_hc_babble_intr(dwc_otg_hcd_t * hcd,
++01523                                      dwc_hc_t * hc,
++01524                                      dwc_otg_hc_regs_t * hc_regs,
++01525                                      dwc_otg_qtd_t * qtd)
++01526 {
++01527         DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
++01528                     "Babble Error--\n", hc->hc_num);
++01529 
++01530         if (hcd->core_if->dma_desc_enable) {
++01531                 dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs,
++01532                                                DWC_OTG_HC_XFER_BABBLE_ERR);
++01533                 goto handle_babble_done;
++01534         }
++01535 
++01536         if (hc->ep_type != DWC_OTG_EP_TYPE_ISOC) {
++01537                 hcd->fops->complete(hcd, qtd->urb->priv,
++01538                                     qtd->urb, -DWC_E_OVERFLOW);
++01539                 halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_BABBLE_ERR);
++01540         } else {
++01541                 dwc_otg_halt_status_e halt_status;
++01542                 halt_status = update_isoc_urb_state(hcd, hc, hc_regs, qtd,
++01543                                                     DWC_OTG_HC_XFER_BABBLE_ERR);
++01544                 halt_channel(hcd, hc, qtd, halt_status);
++01545         }
++01546 
++01547 handle_babble_done:
++01548         disable_hc_int(hc_regs, bblerr);
++01549         return 1;
++01550 }
++01551 
++01556 static int32_t handle_hc_ahberr_intr(dwc_otg_hcd_t * hcd,
++01557                                      dwc_hc_t * hc,
++01558                                      dwc_otg_hc_regs_t * hc_regs,
++01559                                      dwc_otg_qtd_t * qtd)
++01560 {
++01561         hcchar_data_t hcchar;
++01562         hcsplt_data_t hcsplt;
++01563         hctsiz_data_t hctsiz;
++01564         uint32_t hcdma;
++01565         char *pipetype, *speed;
++01566 
++01567         dwc_otg_hcd_urb_t *urb = qtd->urb;
++01568 
++01569         DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
++01570                     "AHB Error--\n", hc->hc_num);
++01571 
++01572         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
++01573         hcsplt.d32 = DWC_READ_REG32(&hc_regs->hcsplt);
++01574         hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
++01575         hcdma = DWC_READ_REG32(&hc_regs->hcdma);
++01576 
++01577         DWC_ERROR("AHB ERROR, Channel %d\n", hc->hc_num);
++01578         DWC_ERROR("  hcchar 0x%08x, hcsplt 0x%08x\n", hcchar.d32, hcsplt.d32);
++01579         DWC_ERROR("  hctsiz 0x%08x, hcdma 0x%08x\n", hctsiz.d32, hcdma);
++01580         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD URB Enqueue\n");
++01581         DWC_ERROR("  Device address: %d\n",
++01582                   dwc_otg_hcd_get_dev_addr(&urb->pipe_info));
++01583         DWC_ERROR("  Endpoint: %d, %s\n",
++01584                   dwc_otg_hcd_get_ep_num(&urb->pipe_info),
++01585                   (dwc_otg_hcd_is_pipe_in(&urb->pipe_info) ? "IN" : "OUT"));
++01586 
++01587         switch (dwc_otg_hcd_get_pipe_type(&urb->pipe_info)) {
++01588         case UE_CONTROL:
++01589                 pipetype = "CONTROL";
++01590                 break;
++01591         case UE_BULK:
++01592                 pipetype = "BULK";
++01593                 break;
++01594         case UE_INTERRUPT:
++01595                 pipetype = "INTERRUPT";
++01596                 break;
++01597         case UE_ISOCHRONOUS:
++01598                 pipetype = "ISOCHRONOUS";
++01599                 break;
++01600         default:
++01601                 pipetype = "UNKNOWN";
++01602                 break;
++01603         }
++01604 
++01605         DWC_ERROR("  Endpoint type: %s\n", pipetype);
++01606 
++01607         switch (hc->speed) {
++01608         case DWC_OTG_EP_SPEED_HIGH:
++01609                 speed = "HIGH";
++01610                 break;
++01611         case DWC_OTG_EP_SPEED_FULL:
++01612                 speed = "FULL";
++01613                 break;
++01614         case DWC_OTG_EP_SPEED_LOW:
++01615                 speed = "LOW";
++01616                 break;
++01617         default:
++01618                 speed = "UNKNOWN";
++01619                 break;
++01620         };
++01621 
++01622         DWC_ERROR("  Speed: %s\n", speed);
++01623 
++01624         DWC_ERROR("  Max packet size: %d\n",
++01625                   dwc_otg_hcd_get_mps(&urb->pipe_info));
++01626         DWC_ERROR("  Data buffer length: %d\n", urb->length);
++01627         DWC_ERROR("  Transfer buffer: %p, Transfer DMA: %p\n",
++01628                   urb->buf, (void *)urb->dma);
++01629         DWC_ERROR("  Setup buffer: %p, Setup DMA: %p\n",
++01630                   urb->setup_packet, (void *)urb->setup_dma);
++01631         DWC_ERROR("  Interval: %d\n", urb->interval);
++01632 
++01633         /* Core haltes the channel for Descriptor DMA mode */
++01634         if (hcd->core_if->dma_desc_enable) {
++01635                 dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs,
++01636                                                DWC_OTG_HC_XFER_AHB_ERR);
++01637                 goto handle_ahberr_done;
++01638         }
++01639 
++01640         hcd->fops->complete(hcd, urb->priv, urb, -DWC_E_IO);
++01641 
++01642         /*
++01643          * Force a channel halt. Don't call halt_channel because that won't
++01644          * write to the HCCHARn register in DMA mode to force the halt.
++01645          */
++01646         dwc_otg_hc_halt(hcd->core_if, hc, DWC_OTG_HC_XFER_AHB_ERR);
++01647 handle_ahberr_done:
++01648         disable_hc_int(hc_regs, ahberr);
++01649         return 1;
++01650 }
++01651 
++01656 static int32_t handle_hc_xacterr_intr(dwc_otg_hcd_t * hcd,
++01657                                       dwc_hc_t * hc,
++01658                                       dwc_otg_hc_regs_t * hc_regs,
++01659                                       dwc_otg_qtd_t * qtd)
++01660 {
++01661         DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
++01662                     "Transaction Error--\n", hc->hc_num);
++01663 
++01664         if (hcd->core_if->dma_desc_enable) {
++01665                 dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs,
++01666                                                DWC_OTG_HC_XFER_XACT_ERR);
++01667                 goto handle_xacterr_done;
++01668         }
++01669 
++01670         switch (dwc_otg_hcd_get_pipe_type(&qtd->urb->pipe_info)) {
++01671         case UE_CONTROL:
++01672         case UE_BULK:
++01673                 qtd->error_count++;
++01674                 if (!hc->qh->ping_state) {
++01675 
++01676                         update_urb_state_xfer_intr(hc, hc_regs,
++01677                                                    qtd->urb, qtd,
++01678                                                    DWC_OTG_HC_XFER_XACT_ERR);
++01679                         dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
++01680                         if (!hc->ep_is_in && hc->speed == DWC_OTG_EP_SPEED_HIGH) {
++01681                                 hc->qh->ping_state = 1;
++01682                         }
++01683                 }
++01684 
++01685                 /*
++01686                  * Halt the channel so the transfer can be re-started from
++01687                  * the appropriate point or the PING protocol will start.
++01688                  */
++01689                 halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_XACT_ERR);
++01690                 break;
++01691         case UE_INTERRUPT:
++01692                 qtd->error_count++;
++01693                 if (hc->do_split && hc->complete_split) {
++01694                         qtd->complete_split = 0;
++01695                 }
++01696                 halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_XACT_ERR);
++01697                 break;
++01698         case UE_ISOCHRONOUS:
++01699                 {
++01700                         dwc_otg_halt_status_e halt_status;
++01701                         halt_status =
++01702                             update_isoc_urb_state(hcd, hc, hc_regs, qtd,
++01703                                                   DWC_OTG_HC_XFER_XACT_ERR);
++01704 
++01705                         halt_channel(hcd, hc, qtd, halt_status);
++01706                 }
++01707                 break;
++01708         }
++01709 handle_xacterr_done:
++01710         disable_hc_int(hc_regs, xacterr);
++01711 
++01712         return 1;
++01713 }
++01714 
++01719 static int32_t handle_hc_frmovrun_intr(dwc_otg_hcd_t * hcd,
++01720                                        dwc_hc_t * hc,
++01721                                        dwc_otg_hc_regs_t * hc_regs,
++01722                                        dwc_otg_qtd_t * qtd)
++01723 {
++01724         DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
++01725                     "Frame Overrun--\n", hc->hc_num);
++01726 
++01727         switch (dwc_otg_hcd_get_pipe_type(&qtd->urb->pipe_info)) {
++01728         case UE_CONTROL:
++01729         case UE_BULK:
++01730                 break;
++01731         case UE_INTERRUPT:
++01732                 halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_FRAME_OVERRUN);
++01733                 break;
++01734         case UE_ISOCHRONOUS:
++01735                 {
++01736                         dwc_otg_halt_status_e halt_status;
++01737                         halt_status =
++01738                             update_isoc_urb_state(hcd, hc, hc_regs, qtd,
++01739                                                   DWC_OTG_HC_XFER_FRAME_OVERRUN);
++01740 
++01741                         halt_channel(hcd, hc, qtd, halt_status);
++01742                 }
++01743                 break;
++01744         }
++01745 
++01746         disable_hc_int(hc_regs, frmovrun);
++01747 
++01748         return 1;
++01749 }
++01750 
++01755 static int32_t handle_hc_datatglerr_intr(dwc_otg_hcd_t * hcd,
++01756                                          dwc_hc_t * hc,
++01757                                          dwc_otg_hc_regs_t * hc_regs,
++01758                                          dwc_otg_qtd_t * qtd)
++01759 {
++01760         DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
++01761                     "Data Toggle Error--\n", hc->hc_num);
++01762 
++01763         if (hc->ep_is_in) {
++01764                 qtd->error_count = 0;
++01765         } else {
++01766                 DWC_ERROR("Data Toggle Error on OUT transfer,"
++01767                           "channel %d\n", hc->hc_num);
++01768         }
++01769 
++01770         disable_hc_int(hc_regs, datatglerr);
++01771 
++01772         return 1;
++01773 }
++01774 
++01775 #ifdef DEBUG
++01776 
++01782 static inline int halt_status_ok(dwc_otg_hcd_t * hcd,
++01783                                  dwc_hc_t * hc,
++01784                                  dwc_otg_hc_regs_t * hc_regs,
++01785                                  dwc_otg_qtd_t * qtd)
++01786 {
++01787         hcchar_data_t hcchar;
++01788         hctsiz_data_t hctsiz;
++01789         hcint_data_t hcint;
++01790         hcintmsk_data_t hcintmsk;
++01791         hcsplt_data_t hcsplt;
++01792 
++01793         if (hc->halt_status == DWC_OTG_HC_XFER_NO_HALT_STATUS) {
++01794                 /*
++01795                  * This code is here only as a check. This condition should
++01796                  * never happen. Ignore the halt if it does occur.
++01797                  */
++01798                 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
++01799                 hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
++01800                 hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
++01801                 hcintmsk.d32 = DWC_READ_REG32(&hc_regs->hcintmsk);
++01802                 hcsplt.d32 = DWC_READ_REG32(&hc_regs->hcsplt);
++01803                 DWC_WARN
++01804                     ("%s: hc->halt_status == DWC_OTG_HC_XFER_NO_HALT_STATUS, "
++01805                      "channel %d, hcchar 0x%08x, hctsiz 0x%08x, "
++01806                      "hcint 0x%08x, hcintmsk 0x%08x, "
++01807                      "hcsplt 0x%08x, qtd->complete_split %d\n", __func__,
++01808                      hc->hc_num, hcchar.d32, hctsiz.d32, hcint.d32,
++01809                      hcintmsk.d32, hcsplt.d32, qtd->complete_split);
++01810 
++01811                 DWC_WARN("%s: no halt status, channel %d, ignoring interrupt\n",
++01812                          __func__, hc->hc_num);
++01813                 DWC_WARN("\n");
++01814                 clear_hc_int(hc_regs, chhltd);
++01815                 return 0;
++01816         }
++01817 
++01818         /*
++01819          * This code is here only as a check. hcchar.chdis should
++01820          * never be set when the halt interrupt occurs. Halt the
++01821          * channel again if it does occur.
++01822          */
++01823         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
++01824         if (hcchar.b.chdis) {
++01825                 DWC_WARN("%s: hcchar.chdis set unexpectedly, "
++01826                          "hcchar 0x%08x, trying to halt again\n",
++01827                          __func__, hcchar.d32);
++01828                 clear_hc_int(hc_regs, chhltd);
++01829                 hc->halt_pending = 0;
++01830                 halt_channel(hcd, hc, qtd, hc->halt_status);
++01831                 return 0;
++01832         }
++01833 
++01834         return 1;
++01835 }
++01836 #endif
++01837 
++01842 static void handle_hc_chhltd_intr_dma(dwc_otg_hcd_t * hcd,
++01843                                       dwc_hc_t * hc,
++01844                                       dwc_otg_hc_regs_t * hc_regs,
++01845                                       dwc_otg_qtd_t * qtd)
++01846 {
++01847         hcint_data_t hcint;
++01848         hcintmsk_data_t hcintmsk;
++01849         int out_nak_enh = 0;
++01850 
++01851         /* For core with OUT NAK enhancement, the flow for high-
++01852          * speed CONTROL/BULK OUT is handled a little differently.
++01853          */
++01854         if (hcd->core_if->snpsid >= OTG_CORE_REV_2_71a) {
++01855                 if (hc->speed == DWC_OTG_EP_SPEED_HIGH && !hc->ep_is_in &&
++01856                     (hc->ep_type == DWC_OTG_EP_TYPE_CONTROL ||
++01857                      hc->ep_type == DWC_OTG_EP_TYPE_BULK)) {
++01858                         out_nak_enh = 1;
++01859                 }
++01860         }
++01861 
++01862         if (hc->halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE ||
++01863             (hc->halt_status == DWC_OTG_HC_XFER_AHB_ERR
++01864              && !hcd->core_if->dma_desc_enable)) {
++01865                 /*
++01866                  * Just release the channel. A dequeue can happen on a
++01867                  * transfer timeout. In the case of an AHB Error, the channel
++01868                  * was forced to halt because there's no way to gracefully
++01869                  * recover.
++01870                  */
++01871                 if (hcd->core_if->dma_desc_enable)
++01872                         dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs,
++01873                                                        hc->halt_status);
++01874                 else
++01875                         release_channel(hcd, hc, qtd, hc->halt_status);
++01876                 return;
++01877         }
++01878 
++01879         /* Read the HCINTn register to determine the cause for the halt. */
++01880         hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
++01881         hcintmsk.d32 = DWC_READ_REG32(&hc_regs->hcintmsk);
++01882 
++01883         if (hcint.b.xfercomp) {
++01890                 if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC && !hc->ep_is_in) {
++01891                         handle_hc_ack_intr(hcd, hc, hc_regs, qtd);
++01892                 }
++01893                 handle_hc_xfercomp_intr(hcd, hc, hc_regs, qtd);
++01894         } else if (hcint.b.stall) {
++01895                 handle_hc_stall_intr(hcd, hc, hc_regs, qtd);
++01896         } else if (hcint.b.xacterr && !hcd->core_if->dma_desc_enable) {
++01897                 if (out_nak_enh) {
++01898                         if (hcint.b.nyet || hcint.b.nak || hcint.b.ack) {
++01899                                 DWC_DEBUG("XactErr with NYET/NAK/ACK\n");
++01900                                 qtd->error_count = 0;
++01901                         } else {
++01902                                 DWC_DEBUG("XactErr without NYET/NAK/ACK\n");
++01903                         }
++01904                 }
++01905 
++01906                 /*
++01907                  * Must handle xacterr before nak or ack. Could get a xacterr
++01908                  * at the same time as either of these on a BULK/CONTROL OUT
++01909                  * that started with a PING. The xacterr takes precedence.
++01910                  */
++01911                 handle_hc_xacterr_intr(hcd, hc, hc_regs, qtd);
++01912         } else if (hcint.b.xcs_xact && hcd->core_if->dma_desc_enable) {
++01913                 handle_hc_xacterr_intr(hcd, hc, hc_regs, qtd);
++01914         } else if (hcint.b.ahberr && hcd->core_if->dma_desc_enable) {
++01915                 handle_hc_ahberr_intr(hcd, hc, hc_regs, qtd);
++01916         } else if (hcint.b.bblerr) {
++01917                 handle_hc_babble_intr(hcd, hc, hc_regs, qtd);
++01918         } else if (hcint.b.frmovrun) {
++01919                 handle_hc_frmovrun_intr(hcd, hc, hc_regs, qtd);
++01920         } else if (!out_nak_enh) {
++01921                 if (hcint.b.nyet) {
++01922                         /*
++01923                          * Must handle nyet before nak or ack. Could get a nyet at the
++01924                          * same time as either of those on a BULK/CONTROL OUT that
++01925                          * started with a PING. The nyet takes precedence.
++01926                          */
++01927                         handle_hc_nyet_intr(hcd, hc, hc_regs, qtd);
++01928                 } else if (hcint.b.nak && !hcintmsk.b.nak) {
++01929                         /*
++01930                          * If nak is not masked, it's because a non-split IN transfer
++01931                          * is in an error state. In that case, the nak is handled by
++01932                          * the nak interrupt handler, not here. Handle nak here for
++01933                          * BULK/CONTROL OUT transfers, which halt on a NAK to allow
++01934                          * rewinding the buffer pointer.
++01935                          */
++01936                         handle_hc_nak_intr(hcd, hc, hc_regs, qtd);
++01937                 } else if (hcint.b.ack && !hcintmsk.b.ack) {
++01938                         /*
++01939                          * If ack is not masked, it's because a non-split IN transfer
++01940                          * is in an error state. In that case, the ack is handled by
++01941                          * the ack interrupt handler, not here. Handle ack here for
++01942                          * split transfers. Start splits halt on ACK.
++01943                          */
++01944                         handle_hc_ack_intr(hcd, hc, hc_regs, qtd);
++01945                 } else {
++01946                         if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
++01947                             hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
++01948                                 /*
++01949                                  * A periodic transfer halted with no other channel
++01950                                  * interrupts set. Assume it was halted by the core
++01951                                  * because it could not be completed in its scheduled
++01952                                  * (micro)frame.
++01953                                  */
++01954 #ifdef DEBUG
++01955                                 DWC_PRINTF
++01956                                     ("%s: Halt channel %d (assume incomplete periodic transfer)\n",
++01957                                      __func__, hc->hc_num);
++01958 #endif
++01959                                 halt_channel(hcd, hc, qtd,
++01960                                              DWC_OTG_HC_XFER_PERIODIC_INCOMPLETE);
++01961                         } else {
++01962                                 DWC_ERROR
++01963                                     ("%s: Channel %d, DMA Mode -- ChHltd set, but reason "
++01964                                      "for halting is unknown, hcint 0x%08x, intsts 0x%08x\n",
++01965                                      __func__, hc->hc_num, hcint.d32,
++01966                                      DWC_READ_REG32(&hcd->
++01967                                                     core_if->core_global_regs->
++01968                                                     gintsts));
++01969                         }
++01970 
++01971                 }
++01972         } else {
++01973                 DWC_PRINTF("NYET/NAK/ACK/other in non-error case, 0x%08x\n",
++01974                            hcint.d32);
++01975         }
++01976 }
++01977 
++01989 static int32_t handle_hc_chhltd_intr(dwc_otg_hcd_t * hcd,
++01990                                      dwc_hc_t * hc,
++01991                                      dwc_otg_hc_regs_t * hc_regs,
++01992                                      dwc_otg_qtd_t * qtd)
++01993 {
++01994         DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
++01995                     "Channel Halted--\n", hc->hc_num);
++01996 
++01997         if (hcd->core_if->dma_enable) {
++01998                 handle_hc_chhltd_intr_dma(hcd, hc, hc_regs, qtd);
++01999         } else {
++02000 #ifdef DEBUG
++02001                 if (!halt_status_ok(hcd, hc, hc_regs, qtd)) {
++02002                         return 1;
++02003                 }
++02004 #endif
++02005                 release_channel(hcd, hc, qtd, hc->halt_status);
++02006         }
++02007 
++02008         return 1;
++02009 }
++02010 
++02012 int32_t dwc_otg_hcd_handle_hc_n_intr(dwc_otg_hcd_t * dwc_otg_hcd, uint32_t num)
++02013 {
++02014         int retval = 0;
++02015         hcint_data_t hcint;
++02016         hcintmsk_data_t hcintmsk;
++02017         dwc_hc_t *hc;
++02018         dwc_otg_hc_regs_t *hc_regs;
++02019         dwc_otg_qtd_t *qtd;
++02020 
++02021         DWC_DEBUGPL(DBG_HCDV, "--Host Channel Interrupt--, Channel %d\n", num);
++02022 
++02023         hc = dwc_otg_hcd->hc_ptr_array[num];
++02024         hc_regs = dwc_otg_hcd->core_if->host_if->hc_regs[num];
++02025         qtd = DWC_CIRCLEQ_FIRST(&hc->qh->qtd_list);
++02026 
++02027         hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
++02028         hcintmsk.d32 = DWC_READ_REG32(&hc_regs->hcintmsk);
++02029         DWC_DEBUGPL(DBG_HCDV,
++02030                     "  hcint 0x%08x, hcintmsk 0x%08x, hcint&hcintmsk 0x%08x\n",
++02031                     hcint.d32, hcintmsk.d32, (hcint.d32 & hcintmsk.d32));
++02032         hcint.d32 = hcint.d32 & hcintmsk.d32;
++02033 
++02034         if (!dwc_otg_hcd->core_if->dma_enable) {
++02035                 if (hcint.b.chhltd && hcint.d32 != 0x2) {
++02036                         hcint.b.chhltd = 0;
++02037                 }
++02038         }
++02039 
++02040         if (hcint.b.xfercomp) {
++02041                 retval |=
++02042                     handle_hc_xfercomp_intr(dwc_otg_hcd, hc, hc_regs, qtd);
++02043                 /*
++02044                  * If NYET occurred at same time as Xfer Complete, the NYET is
++02045                  * handled by the Xfer Complete interrupt handler. Don't want
++02046                  * to call the NYET interrupt handler in this case.
++02047                  */
++02048                 hcint.b.nyet = 0;
++02049         }
++02050         if (hcint.b.chhltd) {
++02051                 retval |= handle_hc_chhltd_intr(dwc_otg_hcd, hc, hc_regs, qtd);
++02052         }
++02053         if (hcint.b.ahberr) {
++02054                 retval |= handle_hc_ahberr_intr(dwc_otg_hcd, hc, hc_regs, qtd);
++02055         }
++02056         if (hcint.b.stall) {
++02057                 retval |= handle_hc_stall_intr(dwc_otg_hcd, hc, hc_regs, qtd);
++02058         }
++02059         if (hcint.b.nak) {
++02060                 retval |= handle_hc_nak_intr(dwc_otg_hcd, hc, hc_regs, qtd);
++02061         }
++02062         if (hcint.b.ack) {
++02063                 retval |= handle_hc_ack_intr(dwc_otg_hcd, hc, hc_regs, qtd);
++02064         }
++02065         if (hcint.b.nyet) {
++02066                 retval |= handle_hc_nyet_intr(dwc_otg_hcd, hc, hc_regs, qtd);
++02067         }
++02068         if (hcint.b.xacterr) {
++02069                 retval |= handle_hc_xacterr_intr(dwc_otg_hcd, hc, hc_regs, qtd);
++02070         }
++02071         if (hcint.b.bblerr) {
++02072                 retval |= handle_hc_babble_intr(dwc_otg_hcd, hc, hc_regs, qtd);
++02073         }
++02074         if (hcint.b.frmovrun) {
++02075                 retval |=
++02076                     handle_hc_frmovrun_intr(dwc_otg_hcd, hc, hc_regs, qtd);
++02077         }
++02078         if (hcint.b.datatglerr) {
++02079                 retval |=
++02080                     handle_hc_datatglerr_intr(dwc_otg_hcd, hc, hc_regs, qtd);
++02081         }
++02082 
++02083         return retval;
++02084 }
++02085 
++02086 #endif /* DWC_DEVICE_ONLY */
++
    Generated on Thu Oct 27 03:56:37 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
    ++doxygen 1.3.9.1
    + + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__hcd__intr_8c.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/dwc__otg__hcd__intr_8c.html 2013-07-26 19:31:21.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__hcd__intr_8c.html 2013-07-26 19:34:41.000000000 +0000 +@@ -2,122 +2,110 @@ + + DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_hcd_intr.c File Reference + +- + +- +-
    +-
    +-
    +-
    ++ ++
    Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
    +

    dwc_otg_hcd_intr.c File Reference

    This file contains the implementation of the HCD Interrupt handlers. More... +

    +-#include "dwc_otg_hcd.h"
    +-#include "dwc_otg_regs.h"
    ++#include "dwc_otg_hcd.h"
    ++#include "dwc_otg_regs.h"
    + +

    + Go to the source code of this file. + + +- ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- ++ + +- +- ++ ++ + +- +- ++ ++ + +- ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + + +

    Functions

    int32_t dwc_otg_hcd_handle_intr (dwc_otg_hcd_t *dwc_otg_hcd)
    int32_t dwc_otg_hcd_handle_intr (dwc_otg_hcd_t *dwc_otg_hcd)
     This function should be called on every hardware interrupt.
    int32_t dwc_otg_hcd_handle_sof_intr (dwc_otg_hcd_t *hcd)
     This function should be called on every hardware interrupt.
    int32_t dwc_otg_hcd_handle_sof_intr (dwc_otg_hcd_t *hcd)
     Handles the start-of-frame interrupt in host mode.
    int32_t dwc_otg_hcd_handle_rx_status_q_level_intr (dwc_otg_hcd_t *dwc_otg_hcd)
     Handles the start-of-frame interrupt in host mode.
    int32_t dwc_otg_hcd_handle_rx_status_q_level_intr (dwc_otg_hcd_t *dwc_otg_hcd)
     Handles the Rx Status Queue Level Interrupt, which indicates that there is at least one packet in the Rx FIFO.
    int32_t dwc_otg_hcd_handle_np_tx_fifo_empty_intr (dwc_otg_hcd_t *dwc_otg_hcd)
     Handles the Rx Status Queue Level Interrupt, which indicates that there is at least one packet in the Rx FIFO.
    int32_t dwc_otg_hcd_handle_np_tx_fifo_empty_intr (dwc_otg_hcd_t *dwc_otg_hcd)
     This interrupt occurs when the non-periodic Tx FIFO is half-empty.
    int32_t dwc_otg_hcd_handle_perio_tx_fifo_empty_intr (dwc_otg_hcd_t *dwc_otg_hcd)
     This interrupt occurs when the non-periodic Tx FIFO is half-empty.
    int32_t dwc_otg_hcd_handle_perio_tx_fifo_empty_intr (dwc_otg_hcd_t *dwc_otg_hcd)
     This interrupt occurs when the periodic Tx FIFO is half-empty.
    int32_t dwc_otg_hcd_handle_port_intr (dwc_otg_hcd_t *dwc_otg_hcd)
     This interrupt occurs when the periodic Tx FIFO is half-empty.
    int32_t dwc_otg_hcd_handle_port_intr (dwc_otg_hcd_t *dwc_otg_hcd)
     There are multiple conditions that can cause a port interrupt.
    int32_t dwc_otg_hcd_handle_hc_intr (dwc_otg_hcd_t *dwc_otg_hcd)
     There are multiple conditions that can cause a port interrupt.
    int32_t dwc_otg_hcd_handle_hc_intr (dwc_otg_hcd_t *dwc_otg_hcd)
     This interrupt indicates that one or more host channels has a pending interrupt.
    static uint32_t get_actual_xfer_length (dwc_hc_t *hc, dwc_otg_hc_regs_t *hc_regs, dwc_otg_qtd_t *qtd, dwc_otg_halt_status_e halt_status, int *short_read)
     This interrupt indicates that one or more host channels has a pending interrupt.
    uint32_t get_actual_xfer_length (dwc_hc_t *hc, dwc_otg_hc_regs_t *hc_regs, dwc_otg_qtd_t *qtd, dwc_otg_halt_status_e halt_status, int *short_read)
     Gets the actual length of a transfer after the transfer halts.
    static int update_urb_state_xfer_comp (dwc_hc_t *hc, dwc_otg_hc_regs_t *hc_regs, dwc_otg_hcd_urb_t *urb, dwc_otg_qtd_t *qtd)
     Gets the actual length of a transfer after the transfer halts.
    int update_urb_state_xfer_comp (dwc_hc_t *hc, dwc_otg_hc_regs_t *hc_regs, dwc_otg_hcd_urb_t *urb, dwc_otg_qtd_t *qtd)
     Updates the state of the URB after a Transfer Complete interrupt on the host channel.
    +-void dwc_otg_hcd_save_data_toggle (dwc_hc_t *hc, dwc_otg_hc_regs_t *hc_regs, dwc_otg_qtd_t *qtd)
     Updates the state of the URB after a Transfer Complete interrupt on the host channel.
    ++void dwc_otg_hcd_save_data_toggle (dwc_hc_t *hc, dwc_otg_hc_regs_t *hc_regs, dwc_otg_qtd_t *qtd)
    static dwc_otg_halt_status_e update_isoc_urb_state (dwc_otg_hcd_t *hcd, dwc_hc_t *hc, dwc_otg_hc_regs_t *hc_regs, dwc_otg_qtd_t *qtd, dwc_otg_halt_status_e halt_status)
    dwc_otg_halt_status_e update_isoc_urb_state (dwc_otg_hcd_t *hcd, dwc_hc_t *hc, dwc_otg_hc_regs_t *hc_regs, dwc_otg_qtd_t *qtd, dwc_otg_halt_status_e halt_status)
     Updates the state of an Isochronous URB when the transfer is stopped for any reason.
    static void deactivate_qh (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh, int free_qtd)
     Updates the state of an Isochronous URB when the transfer is stopped for any reason.
    void deactivate_qh (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh, int free_qtd)
     Frees the first QTD in the QH's list if free_qtd is 1.
    static void release_channel (dwc_otg_hcd_t *hcd, dwc_hc_t *hc, dwc_otg_qtd_t *qtd, dwc_otg_halt_status_e halt_status)
     Frees the first QTD in the QH's list if free_qtd is 1.
    void release_channel (dwc_otg_hcd_t *hcd, dwc_hc_t *hc, dwc_otg_qtd_t *qtd, dwc_otg_halt_status_e halt_status)
     Releases a host channel for use by other transfers.
    static void halt_channel (dwc_otg_hcd_t *hcd, dwc_hc_t *hc, dwc_otg_qtd_t *qtd, dwc_otg_halt_status_e halt_status)
     Releases a host channel for use by other transfers.
    void halt_channel (dwc_otg_hcd_t *hcd, dwc_hc_t *hc, dwc_otg_qtd_t *qtd, dwc_otg_halt_status_e halt_status)
     Halts a host channel.
    static void complete_non_periodic_xfer (dwc_otg_hcd_t *hcd, dwc_hc_t *hc, dwc_otg_hc_regs_t *hc_regs, dwc_otg_qtd_t *qtd, dwc_otg_halt_status_e halt_status)
     Halts a host channel.
    void complete_non_periodic_xfer (dwc_otg_hcd_t *hcd, dwc_hc_t *hc, dwc_otg_hc_regs_t *hc_regs, dwc_otg_qtd_t *qtd, dwc_otg_halt_status_e halt_status)
     Performs common cleanup for non-periodic transfers after a Transfer Complete interrupt.
    static void complete_periodic_xfer (dwc_otg_hcd_t *hcd, dwc_hc_t *hc, dwc_otg_hc_regs_t *hc_regs, dwc_otg_qtd_t *qtd, dwc_otg_halt_status_e halt_status)
     Performs common cleanup for non-periodic transfers after a Transfer Complete interrupt.
    void complete_periodic_xfer (dwc_otg_hcd_t *hcd, dwc_hc_t *hc, dwc_otg_hc_regs_t *hc_regs, dwc_otg_qtd_t *qtd, dwc_otg_halt_status_e halt_status)
     Performs common cleanup for periodic transfers after a Transfer Complete interrupt.
    +-static int32_t handle_xfercomp_isoc_split_in (dwc_otg_hcd_t *hcd, dwc_hc_t *hc, dwc_otg_hc_regs_t *hc_regs, dwc_otg_qtd_t *qtd)
     Performs common cleanup for periodic transfers after a Transfer Complete interrupt.
    ++int32_t handle_xfercomp_isoc_split_in (dwc_otg_hcd_t *hcd, dwc_hc_t *hc, dwc_otg_hc_regs_t *hc_regs, dwc_otg_qtd_t *qtd)
    static int32_t handle_hc_xfercomp_intr (dwc_otg_hcd_t *hcd, dwc_hc_t *hc, dwc_otg_hc_regs_t *hc_regs, dwc_otg_qtd_t *qtd)
    int32_t handle_hc_xfercomp_intr (dwc_otg_hcd_t *hcd, dwc_hc_t *hc, dwc_otg_hc_regs_t *hc_regs, dwc_otg_qtd_t *qtd)
     Handles a host channel Transfer Complete interrupt.
    static int32_t handle_hc_stall_intr (dwc_otg_hcd_t *hcd, dwc_hc_t *hc, dwc_otg_hc_regs_t *hc_regs, dwc_otg_qtd_t *qtd)
     Handles a host channel Transfer Complete interrupt.
    int32_t handle_hc_stall_intr (dwc_otg_hcd_t *hcd, dwc_hc_t *hc, dwc_otg_hc_regs_t *hc_regs, dwc_otg_qtd_t *qtd)
     Handles a host channel STALL interrupt.
    +-static void update_urb_state_xfer_intr (dwc_hc_t *hc, dwc_otg_hc_regs_t *hc_regs, dwc_otg_hcd_urb_t *urb, dwc_otg_qtd_t *qtd, dwc_otg_halt_status_e halt_status)
     Handles a host channel STALL interrupt.
    ++void update_urb_state_xfer_intr (dwc_hc_t *hc, dwc_otg_hc_regs_t *hc_regs, dwc_otg_hcd_urb_t *urb, dwc_otg_qtd_t *qtd, dwc_otg_halt_status_e halt_status)
    static int32_t handle_hc_nak_intr (dwc_otg_hcd_t *hcd, dwc_hc_t *hc, dwc_otg_hc_regs_t *hc_regs, dwc_otg_qtd_t *qtd)
    int32_t handle_hc_nak_intr (dwc_otg_hcd_t *hcd, dwc_hc_t *hc, dwc_otg_hc_regs_t *hc_regs, dwc_otg_qtd_t *qtd)
     Handles a host channel NAK interrupt.
    static int32_t handle_hc_ack_intr (dwc_otg_hcd_t *hcd, dwc_hc_t *hc, dwc_otg_hc_regs_t *hc_regs, dwc_otg_qtd_t *qtd)
     Handles a host channel NAK interrupt.
    int32_t handle_hc_ack_intr (dwc_otg_hcd_t *hcd, dwc_hc_t *hc, dwc_otg_hc_regs_t *hc_regs, dwc_otg_qtd_t *qtd)
     Handles a host channel ACK interrupt.
    static int32_t handle_hc_nyet_intr (dwc_otg_hcd_t *hcd, dwc_hc_t *hc, dwc_otg_hc_regs_t *hc_regs, dwc_otg_qtd_t *qtd)
     Handles a host channel ACK interrupt.
    int32_t handle_hc_nyet_intr (dwc_otg_hcd_t *hcd, dwc_hc_t *hc, dwc_otg_hc_regs_t *hc_regs, dwc_otg_qtd_t *qtd)
     Handles a host channel NYET interrupt.
    static int32_t handle_hc_babble_intr (dwc_otg_hcd_t *hcd, dwc_hc_t *hc, dwc_otg_hc_regs_t *hc_regs, dwc_otg_qtd_t *qtd)
     Handles a host channel NYET interrupt.
    int32_t handle_hc_babble_intr (dwc_otg_hcd_t *hcd, dwc_hc_t *hc, dwc_otg_hc_regs_t *hc_regs, dwc_otg_qtd_t *qtd)
     Handles a host channel babble interrupt.
    static int32_t handle_hc_ahberr_intr (dwc_otg_hcd_t *hcd, dwc_hc_t *hc, dwc_otg_hc_regs_t *hc_regs, dwc_otg_qtd_t *qtd)
     Handles a host channel babble interrupt.
    int32_t handle_hc_ahberr_intr (dwc_otg_hcd_t *hcd, dwc_hc_t *hc, dwc_otg_hc_regs_t *hc_regs, dwc_otg_qtd_t *qtd)
     Handles a host channel AHB error interrupt.
    static int32_t handle_hc_xacterr_intr (dwc_otg_hcd_t *hcd, dwc_hc_t *hc, dwc_otg_hc_regs_t *hc_regs, dwc_otg_qtd_t *qtd)
     Handles a host channel AHB error interrupt.
    int32_t handle_hc_xacterr_intr (dwc_otg_hcd_t *hcd, dwc_hc_t *hc, dwc_otg_hc_regs_t *hc_regs, dwc_otg_qtd_t *qtd)
     Handles a host channel transaction error interrupt.
    static int32_t handle_hc_frmovrun_intr (dwc_otg_hcd_t *hcd, dwc_hc_t *hc, dwc_otg_hc_regs_t *hc_regs, dwc_otg_qtd_t *qtd)
     Handles a host channel transaction error interrupt.
    int32_t handle_hc_frmovrun_intr (dwc_otg_hcd_t *hcd, dwc_hc_t *hc, dwc_otg_hc_regs_t *hc_regs, dwc_otg_qtd_t *qtd)
     Handles a host channel frame overrun interrupt.
    static int32_t handle_hc_datatglerr_intr (dwc_otg_hcd_t *hcd, dwc_hc_t *hc, dwc_otg_hc_regs_t *hc_regs, dwc_otg_qtd_t *qtd)
     Handles a host channel frame overrun interrupt.
    int32_t handle_hc_datatglerr_intr (dwc_otg_hcd_t *hcd, dwc_hc_t *hc, dwc_otg_hc_regs_t *hc_regs, dwc_otg_qtd_t *qtd)
     Handles a host channel data toggle error interrupt.
    static void handle_hc_chhltd_intr_dma (dwc_otg_hcd_t *hcd, dwc_hc_t *hc, dwc_otg_hc_regs_t *hc_regs, dwc_otg_qtd_t *qtd)
     Handles a host channel data toggle error interrupt.
    void handle_hc_chhltd_intr_dma (dwc_otg_hcd_t *hcd, dwc_hc_t *hc, dwc_otg_hc_regs_t *hc_regs, dwc_otg_qtd_t *qtd)
     Handles a host Channel Halted interrupt in DMA mode.
    static int32_t handle_hc_chhltd_intr (dwc_otg_hcd_t *hcd, dwc_hc_t *hc, dwc_otg_hc_regs_t *hc_regs, dwc_otg_qtd_t *qtd)
     Handles a host Channel Halted interrupt in DMA mode.
    int32_t handle_hc_chhltd_intr (dwc_otg_hcd_t *hcd, dwc_hc_t *hc, dwc_otg_hc_regs_t *hc_regs, dwc_otg_qtd_t *qtd)
     Handles a host channel Channel Halted interrupt.
    +-int32_t dwc_otg_hcd_handle_hc_n_intr (dwc_otg_hcd_t *dwc_otg_hcd, uint32_t num)
     Handles a host channel Channel Halted interrupt.
    ++int32_t dwc_otg_hcd_handle_hc_n_intr (dwc_otg_hcd_t *dwc_otg_hcd, uint32_t num)
     Handles interrupt for a specific Host Channel.
    +@@ -127,226 +115,286 @@ + +

    + Definition in file dwc_otg_hcd_intr.c.

    Function Documentation

    +- +-
    +-
    +- +- +- +- +- +- +- +- ++

    ++

    int32_t dwc_otg_hcd_handle_intr (dwc_otg_hcd_t *  dwc_otg_hcd  ) 
    ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ + +
    int32_t dwc_otg_hcd_handle_intr ( dwc_otg_hcd_t *  dwc_otg_hcd  ) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + This function should be called on every hardware interrupt. +

    +-

    Parameters:
    +- +- +-
    dwc_otg_hcd The HCD
    +-
    +-Returns non zero if interrupt is handled Return 0 if interrupt is not handled +-

    +-

    Todo:
    Implement i2cintr handler.
    ++
    Todo:
    Implement i2cintr handler.
    + +

    +-Definition at line 43 of file dwc_otg_hcd_intr.c. +- +-

    +- +-

    +-
    +- +- +- +- +- +- +- +- ++Definition at line 43 of file dwc_otg_hcd_intr.c. ++ ++
    int32_t dwc_otg_hcd_handle_sof_intr (dwc_otg_hcd_t *  hcd  ) 
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ + +
    int32_t dwc_otg_hcd_handle_sof_intr ( dwc_otg_hcd_t *  hcd  ) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Handles the start-of-frame interrupt in host mode. +

    + Non-periodic transactions may be queued to the DWC_otg controller for the current (micro)frame. Periodic transactions may be queued to the controller for the next (micro)frame. +

    +-Definition at line 169 of file dwc_otg_hcd_intr.c. +- +-

    +- +-

    +-
    +- +- +- +- +- +- +- +- ++Definition at line 175 of file dwc_otg_hcd_intr.c. ++ ++
    int32_t dwc_otg_hcd_handle_rx_status_q_level_intr (dwc_otg_hcd_t *  dwc_otg_hcd  ) 
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ + +
    int32_t dwc_otg_hcd_handle_rx_status_q_level_intr ( dwc_otg_hcd_t *  dwc_otg_hcd  ) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Handles the Rx Status Queue Level Interrupt, which indicates that there is at least one packet in the Rx FIFO. +

    + The packets are moved from the FIFO to memory if the DWC_otg controller is operating in Slave mode. +

    +-Definition at line 222 of file dwc_otg_hcd_intr.c. +- +-

    +- +-

    +-
    +- +- +- +- +- +- +- +- ++Definition at line 228 of file dwc_otg_hcd_intr.c. ++ ++
    int32_t dwc_otg_hcd_handle_np_tx_fifo_empty_intr (dwc_otg_hcd_t *  dwc_otg_hcd  ) 
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ + +
    int32_t dwc_otg_hcd_handle_np_tx_fifo_empty_intr ( dwc_otg_hcd_t *  dwc_otg_hcd  ) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + This interrupt occurs when the non-periodic Tx FIFO is half-empty. +

    + More data packets may be written to the FIFO for OUT transfers. More requests may be written to the non-periodic request queue for IN transfers. This interrupt is enabled only in Slave mode. +

    +-Definition at line 271 of file dwc_otg_hcd_intr.c. +- +-

    +- +-

    +-
    +- +- +- +- +- +- +- +- ++Definition at line 281 of file dwc_otg_hcd_intr.c. ++ ++
    int32_t dwc_otg_hcd_handle_perio_tx_fifo_empty_intr (dwc_otg_hcd_t *  dwc_otg_hcd  ) 
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ + +
    int32_t dwc_otg_hcd_handle_perio_tx_fifo_empty_intr ( dwc_otg_hcd_t *  dwc_otg_hcd  ) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + This interrupt occurs when the periodic Tx FIFO is half-empty. +

    + More data packets may be written to the FIFO for OUT transfers. More requests may be written to the periodic request queue for IN transfers. This interrupt is enabled only in Slave mode. +

    +-Definition at line 283 of file dwc_otg_hcd_intr.c. +- +-

    +- +-

    +-
    +- +- +- +- +- +- +- +- ++Definition at line 293 of file dwc_otg_hcd_intr.c. ++ ++
    int32_t dwc_otg_hcd_handle_port_intr (dwc_otg_hcd_t *  dwc_otg_hcd  ) 
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ + +
    int32_t dwc_otg_hcd_handle_port_intr ( dwc_otg_hcd_t *  dwc_otg_hcd  ) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + There are multiple conditions that can cause a port interrupt. +

    +-This function determines which interrupt conditions have occurred and handles them appropriately. ++This function determines which interrupt conditions have occurred and handles them appropriately.

    ++

    Todo:
      ++
    • check if steps performed in 'else' block should be perfromed regardles adp
    ++
    +

    + Overcurrent Change Interrupt +

    +-Definition at line 294 of file dwc_otg_hcd_intr.c. +- +-

    +- +-

    +-
    +- +- +- +- +- +- +- +- ++Definition at line 304 of file dwc_otg_hcd_intr.c. ++ ++
    int32_t dwc_otg_hcd_handle_hc_intr (dwc_otg_hcd_t *  dwc_otg_hcd  ) 
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ + +
    int32_t dwc_otg_hcd_handle_hc_intr ( dwc_otg_hcd_t *  dwc_otg_hcd  ) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + This interrupt indicates that one or more host channels has a pending interrupt. +

    + There are multiple conditions that can cause each host channel interrupt. This function determines which conditions have occurred for each host channel interrupt and handles them appropriately. +

    +-Definition at line 453 of file dwc_otg_hcd_intr.c. +- +-

    +- +-

    +-
    +- ++Definition at line 493 of file dwc_otg_hcd_intr.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    static uint32_t get_actual_xfer_length (dwc_hc_t *  hc, uint32_t get_actual_xfer_length ( dwc_hc_t *  hc,
    dwc_otg_hc_regs_t *  hc_regs, dwc_otg_hc_regs_t *  hc_regs,
    dwc_otg_qtd_t *  qtd, dwc_otg_qtd_t *  qtd,
    dwc_otg_halt_status_e  halt_status, dwc_otg_halt_status_e  halt_status,
    int *  short_read int *  short_read
    ) [static])  [static]
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Gets the actual length of a transfer after the transfer halts. +@@ -354,45 +402,53 @@ + _halt_status holds the reason for the halt.

    + For IN transfers where halt_status is DWC_OTG_HC_XFER_COMPLETE, *short_read is set to 1 upon return if less than the requested number of bytes were transferred. Otherwise, *short_read is set to 0 upon return. short_read may also be NULL on entry, in which case it remains unchanged. +

    +-Definition at line 485 of file dwc_otg_hcd_intr.c. +- +-

    +- +-

    +-
    +- ++Definition at line 523 of file dwc_otg_hcd_intr.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    static int update_urb_state_xfer_comp (dwc_hc_t *  hc, int update_urb_state_xfer_comp ( dwc_hc_t *  hc,
    dwc_otg_hc_regs_t *  hc_regs, dwc_otg_hc_regs_t *  hc_regs,
    dwc_otg_hcd_urb_t *  urb, dwc_otg_hcd_urb_t *  urb,
    dwc_otg_qtd_t *  qtd dwc_otg_qtd_t *  qtd
    ) [static])  [static]
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Updates the state of the URB after a Transfer Complete interrupt on the host channel. +@@ -401,51 +457,59 @@ +

    Returns:
    1 if the data transfer specified by the URB is completely finished, 0 otherwise.
    + +

    +-Definition at line 536 of file dwc_otg_hcd_intr.c. +- +-

    +- +-

    +-
    +- ++Definition at line 574 of file dwc_otg_hcd_intr.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    static dwc_otg_halt_status_e update_isoc_urb_state (dwc_otg_hcd_t *  hcd, dwc_otg_halt_status_e update_isoc_urb_state ( dwc_otg_hcd_t *  hcd,
    dwc_hc_t *  hc, dwc_hc_t *  hc,
    dwc_otg_hc_regs_t *  hc_regs, dwc_otg_hc_regs_t *  hc_regs,
    dwc_otg_qtd_t *  qtd, dwc_otg_qtd_t *  qtd,
    dwc_otg_halt_status_e  halt_status dwc_otg_halt_status_e  halt_status
    ) [static])  [static]
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Updates the state of an Isochronous URB when the transfer is stopped for any reason. +@@ -454,84 +518,100 @@ +

    Returns:
    DWC_OTG_HC_XFER_COMPLETE if there are more frames remaining to be transferred in the URB. Otherwise return DWC_OTG_HC_XFER_URB_COMPLETE.
    + +

    +-Definition at line 626 of file dwc_otg_hcd_intr.c. +- +-

    +- +-

    +-
    +- ++Definition at line 666 of file dwc_otg_hcd_intr.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    static void deactivate_qh (dwc_otg_hcd_t *  hcd, void deactivate_qh ( dwc_otg_hcd_t *  hcd,
    dwc_otg_qh_t *  qh, dwc_otg_qh_t *  qh,
    int  free_qtd int  free_qtd
    ) [static])  [static]
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Frees the first QTD in the QH's list if free_qtd is 1. +

    + For non-periodic QHs, removes the QH from the active non-periodic schedule. If any QTDs are still linked to the QH, the QH is added to the end of the inactive non-periodic schedule. For periodic QHs, removes the QH from the periodic schedule if no more QTDs are linked to the QH. +

    +-Definition at line 706 of file dwc_otg_hcd_intr.c. +- +-

    +- +-

    +-
    +- ++Definition at line 746 of file dwc_otg_hcd_intr.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    static void release_channel (dwc_otg_hcd_t *  hcd, void release_channel ( dwc_otg_hcd_t *  hcd,
    dwc_hc_t *  hc, dwc_hc_t *  hc,
    dwc_otg_qtd_t *  qtd, dwc_otg_qtd_t *  qtd,
    dwc_otg_halt_status_e  halt_status dwc_otg_halt_status_e  halt_status
    ) [static])  [static]
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Releases a host channel for use by other transfers. +@@ -547,45 +627,53 @@ + + +

    +-Definition at line 742 of file dwc_otg_hcd_intr.c. +- +-

    +- +-

    +-
    +- ++Definition at line 782 of file dwc_otg_hcd_intr.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    static void halt_channel (dwc_otg_hcd_t *  hcd, void halt_channel ( dwc_otg_hcd_t *  hcd,
    dwc_hc_t *  hc, dwc_hc_t *  hc,
    dwc_otg_qtd_t *  qtd, dwc_otg_qtd_t *  qtd,
    dwc_otg_halt_status_e  halt_status dwc_otg_halt_status_e  halt_status
    ) [static])  [static]
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Halts a host channel. +@@ -593,648 +681,758 @@ + If the channel cannot be halted immediately because the request queue is full, this function ensures that the FIFO empty interrupt for the appropriate queue is enabled so that the halt request can be queued when there is space in the request queue.

    + This function may also be called in DMA mode. In that case, the channel is simply released since the core always halts the channel automatically in DMA mode. +

    +-Definition at line 833 of file dwc_otg_hcd_intr.c. +- +-

    +- +-

    +-
    +- ++Definition at line 880 of file dwc_otg_hcd_intr.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    static void complete_non_periodic_xfer (dwc_otg_hcd_t *  hcd, void complete_non_periodic_xfer ( dwc_otg_hcd_t *  hcd,
    dwc_hc_t *  hc, dwc_hc_t *  hc,
    dwc_otg_hc_regs_t *  hc_regs, dwc_otg_hc_regs_t *  hc_regs,
    dwc_otg_qtd_t *  qtd, dwc_otg_qtd_t *  qtd,
    dwc_otg_halt_status_e  halt_status dwc_otg_halt_status_e  halt_status
    ) [static])  [static]
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Performs common cleanup for non-periodic transfers after a Transfer Complete interrupt. +

    + This function should be called after any endpoint type specific handling is finished to release the host channel. +

    +-Definition at line 885 of file dwc_otg_hcd_intr.c. +- +-

    +- +-

    +-
    +- ++Definition at line 932 of file dwc_otg_hcd_intr.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    static void complete_periodic_xfer (dwc_otg_hcd_t *  hcd, void complete_periodic_xfer ( dwc_otg_hcd_t *  hcd,
    dwc_hc_t *  hc, dwc_hc_t *  hc,
    dwc_otg_hc_regs_t *  hc_regs, dwc_otg_hc_regs_t *  hc_regs,
    dwc_otg_qtd_t *  qtd, dwc_otg_qtd_t *  qtd,
    dwc_otg_halt_status_e  halt_status dwc_otg_halt_status_e  halt_status
    ) [static])  [static]
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Performs common cleanup for periodic transfers after a Transfer Complete interrupt. +

    + This function should be called after any endpoint type specific handling is finished to release the host channel. +

    +-Definition at line 937 of file dwc_otg_hcd_intr.c. +- +-

    +- +-

    +-
    +- ++Definition at line 984 of file dwc_otg_hcd_intr.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    static int32_t handle_hc_xfercomp_intr (dwc_otg_hcd_t *  hcd, int32_t handle_hc_xfercomp_intr ( dwc_otg_hcd_t *  hcd,
    dwc_hc_t *  hc, dwc_hc_t *  hc,
    dwc_otg_hc_regs_t *  hc_regs, dwc_otg_hc_regs_t *  hc_regs,
    dwc_otg_qtd_t *  qtd dwc_otg_qtd_t *  qtd
    ) [static])  [static]
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Handles a host channel Transfer Complete interrupt. +

    + This handler may be called in either DMA mode or Slave mode. +

    +-Definition at line 1002 of file dwc_otg_hcd_intr.c. +- +-

    +- +-

    +-
    +- ++Definition at line 1048 of file dwc_otg_hcd_intr.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    static int32_t handle_hc_stall_intr (dwc_otg_hcd_t *  hcd, int32_t handle_hc_stall_intr ( dwc_otg_hcd_t *  hcd,
    dwc_hc_t *  hc, dwc_hc_t *  hc,
    dwc_otg_hc_regs_t *  hc_regs, dwc_otg_hc_regs_t *  hc_regs,
    dwc_otg_qtd_t *  qtd dwc_otg_qtd_t *  qtd
    ) [static])  [static]
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Handles a host channel STALL interrupt. +

    + This handler may be called in either DMA mode or Slave mode. +

    +-Definition at line 1128 of file dwc_otg_hcd_intr.c. +- +-

    +- +-

    +-
    +- ++Definition at line 1182 of file dwc_otg_hcd_intr.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    static int32_t handle_hc_nak_intr (dwc_otg_hcd_t *  hcd, int32_t handle_hc_nak_intr ( dwc_otg_hcd_t *  hcd,
    dwc_hc_t *  hc, dwc_hc_t *  hc,
    dwc_otg_hc_regs_t *  hc_regs, dwc_otg_hc_regs_t *  hc_regs,
    dwc_otg_qtd_t *  qtd dwc_otg_qtd_t *  qtd
    ) [static])  [static]
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Handles a host channel NAK interrupt. +

    + This handler may be called in either DMA mode or Slave mode. +

    +-Definition at line 1214 of file dwc_otg_hcd_intr.c. +- +-

    +- +-

    +-
    +- ++Definition at line 1269 of file dwc_otg_hcd_intr.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    static int32_t handle_hc_ack_intr (dwc_otg_hcd_t *  hcd, int32_t handle_hc_ack_intr ( dwc_otg_hcd_t *  hcd,
    dwc_hc_t *  hc, dwc_hc_t *  hc,
    dwc_otg_hc_regs_t *  hc_regs, dwc_otg_hc_regs_t *  hc_regs,
    dwc_otg_qtd_t *  qtd dwc_otg_qtd_t *  qtd
    ) [static])  [static]
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Handles a host channel ACK interrupt. +

    + This interrupt is enabled when performing the PING protocol in Slave mode, when errors occur during either Slave mode or DMA mode, and during Start Split transactions. +

    +-Definition at line 1294 of file dwc_otg_hcd_intr.c. +- +-

    +- +-

    +-
    +- ++Definition at line 1349 of file dwc_otg_hcd_intr.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    static int32_t handle_hc_nyet_intr (dwc_otg_hcd_t *  hcd, int32_t handle_hc_nyet_intr ( dwc_otg_hcd_t *  hcd,
    dwc_hc_t *  hc, dwc_hc_t *  hc,
    dwc_otg_hc_regs_t *  hc_regs, dwc_otg_hc_regs_t *  hc_regs,
    dwc_otg_qtd_t *  qtd dwc_otg_qtd_t *  qtd
    ) [static])  [static]
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Handles a host channel NYET interrupt. +

    +-This interrupt should only occur on Bulk and Control OUT endpoints and for complete split transactions. If a NYET occurs at the same time as a Transfer Complete interrupt, it is handled in the xfercomp interrupt handler, not here. This handler may be called in either DMA mode or Slave mode. +-

    +-

    Todo:
    add support for isoc release
    ++This interrupt should only occur on Bulk and Control OUT endpoints and for complete split transactions. If a NYET occurs at the same time as a Transfer Complete interrupt, it is handled in the xfercomp interrupt handler, not here. This handler may be called in either DMA mode or Slave mode.

    ++

    Todo:
    add support for isoc release
    + +

    +-Definition at line 1388 of file dwc_otg_hcd_intr.c. +- +-

    +- +-

    +-
    +- ++Definition at line 1443 of file dwc_otg_hcd_intr.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    static int32_t handle_hc_babble_intr (dwc_otg_hcd_t *  hcd, int32_t handle_hc_babble_intr ( dwc_otg_hcd_t *  hcd,
    dwc_hc_t *  hc, dwc_hc_t *  hc,
    dwc_otg_hc_regs_t *  hc_regs, dwc_otg_hc_regs_t *  hc_regs,
    dwc_otg_qtd_t *  qtd dwc_otg_qtd_t *  qtd
    ) [static])  [static]
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Handles a host channel babble interrupt. +

    + This handler may be called in either DMA mode or Slave mode. +

    +-Definition at line 1466 of file dwc_otg_hcd_intr.c. +- +-

    +- +-

    +-
    +- ++Definition at line 1522 of file dwc_otg_hcd_intr.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    static int32_t handle_hc_ahberr_intr (dwc_otg_hcd_t *  hcd, int32_t handle_hc_ahberr_intr ( dwc_otg_hcd_t *  hcd,
    dwc_hc_t *  hc, dwc_hc_t *  hc,
    dwc_otg_hc_regs_t *  hc_regs, dwc_otg_hc_regs_t *  hc_regs,
    dwc_otg_qtd_t *  qtd dwc_otg_qtd_t *  qtd
    ) [static])  [static]
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Handles a host channel AHB error interrupt. +

    + This handler is only called in DMA mode. +

    +-Definition at line 1499 of file dwc_otg_hcd_intr.c. +- +-

    +- +-

    +-
    +- ++Definition at line 1556 of file dwc_otg_hcd_intr.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    static int32_t handle_hc_xacterr_intr (dwc_otg_hcd_t *  hcd, int32_t handle_hc_xacterr_intr ( dwc_otg_hcd_t *  hcd,
    dwc_hc_t *  hc, dwc_hc_t *  hc,
    dwc_otg_hc_regs_t *  hc_regs, dwc_otg_hc_regs_t *  hc_regs,
    dwc_otg_qtd_t *  qtd dwc_otg_qtd_t *  qtd
    ) [static])  [static]
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Handles a host channel transaction error interrupt. +

    + This handler may be called in either DMA mode or Slave mode. +

    +-Definition at line 1599 of file dwc_otg_hcd_intr.c. +- +-

    +- +-

    +-
    +- ++Definition at line 1656 of file dwc_otg_hcd_intr.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    static int32_t handle_hc_frmovrun_intr (dwc_otg_hcd_t *  hcd, int32_t handle_hc_frmovrun_intr ( dwc_otg_hcd_t *  hcd,
    dwc_hc_t *  hc, dwc_hc_t *  hc,
    dwc_otg_hc_regs_t *  hc_regs, dwc_otg_hc_regs_t *  hc_regs,
    dwc_otg_qtd_t *  qtd dwc_otg_qtd_t *  qtd
    ) [static])  [static]
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Handles a host channel frame overrun interrupt. +

    + This handler may be called in either DMA mode or Slave mode. +

    +-Definition at line 1661 of file dwc_otg_hcd_intr.c. +- +-

    +- +-

    +-
    +- ++Definition at line 1719 of file dwc_otg_hcd_intr.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    static int32_t handle_hc_datatglerr_intr (dwc_otg_hcd_t *  hcd, int32_t handle_hc_datatglerr_intr ( dwc_otg_hcd_t *  hcd,
    dwc_hc_t *  hc, dwc_hc_t *  hc,
    dwc_otg_hc_regs_t *  hc_regs, dwc_otg_hc_regs_t *  hc_regs,
    dwc_otg_qtd_t *  qtd dwc_otg_qtd_t *  qtd
    ) [static])  [static]
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Handles a host channel data toggle error interrupt. +

    + This handler may be called in either DMA mode or Slave mode. +

    +-Definition at line 1697 of file dwc_otg_hcd_intr.c. +- +-

    +- +-

    +-
    +- ++Definition at line 1755 of file dwc_otg_hcd_intr.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    static void handle_hc_chhltd_intr_dma (dwc_otg_hcd_t *  hcd, void handle_hc_chhltd_intr_dma ( dwc_otg_hcd_t *  hcd,
    dwc_hc_t *  hc, dwc_hc_t *  hc,
    dwc_otg_hc_regs_t *  hc_regs, dwc_otg_hc_regs_t *  hc_regs,
    dwc_otg_qtd_t *  qtd dwc_otg_qtd_t *  qtd
    ) [static])  [static]
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Handles a host Channel Halted interrupt in DMA mode. +

    +-This handler determines the reason the channel halted and proceeds accordingly. +-

    ++This handler determines the reason the channel halted and proceeds accordingly.

    +

    Todo:
    This is here because of a possible hardware bug. Spec says that on SPLIT-ISOC OUT transfers in DMA mode that a HALT interrupt w/ACK bit set should occur, but I only see the XFERCOMP bit, even with it masked out. This is a workaround for that behavior. Should fix this when hardware is fixed.
    + +

    +-Definition at line 1784 of file dwc_otg_hcd_intr.c. +- +-

    +- +-

    +-
    +- ++Definition at line 1842 of file dwc_otg_hcd_intr.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    static int32_t handle_hc_chhltd_intr (dwc_otg_hcd_t *  hcd, int32_t handle_hc_chhltd_intr ( dwc_otg_hcd_t *  hcd,
    dwc_hc_t *  hc, dwc_hc_t *  hc,
    dwc_otg_hc_regs_t *  hc_regs, dwc_otg_hc_regs_t *  hc_regs,
    dwc_otg_qtd_t *  qtd dwc_otg_qtd_t *  qtd
    ) [static])  [static]
    +- +-
    ++
    ++ ++ ++ ++ ++ ++
    ++   ++ + +

    + Handles a host channel Channel Halted interrupt. +@@ -1242,11 +1440,11 @@ + In slave mode, this handler is called only when the driver specifically requests a halt. This occurs during handling other host channel interrupts (e.g. nak, xacterr, stall, nyet, etc.).

    + In DMA mode, this is the interrupt that occurs when the core has finished processing a transfer on a channel. Other host channel interrupts (except ahberr) are disabled in DMA mode. +

    +-Definition at line 1928 of file dwc_otg_hcd_intr.c. +- +-

    +-

    Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++Definition at line 1989 of file dwc_otg_hcd_intr.c.
    ++

    Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
    ++doxygen 1.3.9.1 + + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__hcd__linux_8c-source.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/dwc__otg__hcd__linux_8c-source.html 2013-07-26 19:31:21.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__hcd__linux_8c-source.html 2013-07-26 19:34:41.000000000 +0000 +@@ -2,725 +2,790 @@ + + DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_hcd_linux.c Source File + +- + +- +-
    +-
    +-
    +-
    +-

    dwc_otg_hcd_linux.c

    Go to the documentation of this file.
    00001 /* ==========================================================================
+-00002  * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd_linux.c $
+-00003  * $Revision: #11 $
+-00004  * $Date: 2009/04/21 $
+-00005  * $Change: 1237476 $
+-00006  *
+-00007  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
+-00008  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
+-00009  * otherwise expressly agreed to in writing between Synopsys and you.
+-00010  *
+-00011  * The Software IS NOT an item of Licensed Software or Licensed Product under
+-00012  * any End User Software License Agreement or Agreement for Licensed Product
+-00013  * with Synopsys or any supplement thereto. You are permitted to use and
+-00014  * redistribute this Software in source and binary forms, with or without
+-00015  * modification, provided that redistributions of source code must retain this
+-00016  * notice. You may not view, use, disclose, copy or distribute this file or
+-00017  * any information contained herein except pursuant to this license grant from
+-00018  * Synopsys. If you do not agree with this notice, including the disclaimer
+-00019  * below, then you are not authorized to use the Software.
+-00020  *
+-00021  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
+-00022  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+-00023  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+-00024  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
+-00025  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+-00026  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+-00027  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+-00028  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+-00029  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+-00030  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+-00031  * DAMAGE.
+-00032  * ========================================================================== */
+-00033 #ifndef DWC_DEVICE_ONLY
+-00034 
+-00041 #include <linux/kernel.h>
+-00042 #include <linux/module.h>
+-00043 #include <linux/moduleparam.h>
+-00044 #include <linux/init.h>
+-00045 #include <linux/device.h>
+-00046 #include <linux/errno.h>
+-00047 #include <linux/list.h>
+-00048 #include <linux/interrupt.h>
+-00049 #include <linux/string.h>
+-00050 #include <linux/dma-mapping.h>
+-00051 #include <linux/version.h>
+-00052 #include <asm/io.h>
+-00053 
+-00054 #ifdef LM_INTERFACE
+-00055 #include <asm/arch/regs-irq.h>
+-00056 #include <asm/arch/lm.h>
+-00057 #include <asm/arch/irqs.h>
+-00058 #endif
+-00059 
+-00060 #include <linux/usb.h>
+-00061 #include <../drivers/usb/core/hcd.h>
+-00062 
+-00063 #include "dwc_otg_hcd_if.h"
+-00064 #include "dwc_otg_dbg.h"
+-00065 #include "dwc_otg_driver.h"
+-00066 
+-00071 #define dwc_ep_addr_to_endpoint(_bEndpointAddress_) ((_bEndpointAddress_ & USB_ENDPOINT_NUMBER_MASK) | \
+-00072                                                      ((_bEndpointAddress_ & USB_DIR_IN) != 0) << 4)
+-00073 
+-00074 static const char dwc_otg_hcd_name[] = "dwc_otg_hcd";
+-00075 
+-00078 static int urb_enqueue(struct usb_hcd *hcd,
+-00079                        struct usb_host_endpoint *ep,
+-00080                        struct urb *urb, gfp_t mem_flags);
+-00081 
+-00082 static int urb_dequeue(struct usb_hcd *hcd, struct urb *urb);
+-00083 
+-00084 static void endpoint_disable(struct usb_hcd *hcd, struct usb_host_endpoint *ep);
+-00085 
+-00086 static irqreturn_t dwc_otg_hcd_irq(struct usb_hcd *hcd);
+-00087 extern int hcd_start(struct usb_hcd *hcd);
+-00088 extern void hcd_stop(struct usb_hcd *hcd);
+-00089 static int get_frame_number(struct usb_hcd *hcd);
+-00090 extern int hub_status_data(struct usb_hcd *hcd, char *buf);
+-00091 extern int hub_control(struct usb_hcd *hcd,
+-00092                        u16 typeReq,
+-00093                        u16 wValue, u16 wIndex, char *buf, u16 wLength);
+-00094 
+-00095 struct wrapper_priv_data {
+-00096         dwc_otg_hcd_t *dwc_otg_hcd;
+-00097 };
+-00098 
+-00101 static struct hc_driver dwc_otg_hc_driver = {
+-00102 
+-00103         .description = dwc_otg_hcd_name,
+-00104         .product_desc = "DWC OTG Controller",
+-00105         .hcd_priv_size = sizeof(struct wrapper_priv_data),
+-00106 
+-00107         .irq = dwc_otg_hcd_irq,
+-00108 
+-00109         .flags = HCD_MEMORY | HCD_USB2,
+-00110 
+-00111         //.reset =              
+-00112         .start = hcd_start,
+-00113         //.suspend =            
+-00114         //.resume =             
+-00115         .stop = hcd_stop,
+-00116 
+-00117         .urb_enqueue = urb_enqueue,
+-00118         .urb_dequeue = urb_dequeue,
+-00119         .endpoint_disable = endpoint_disable,
+-00120 
+-00121         .get_frame_number = get_frame_number,
+-00122 
+-00123         .hub_status_data = hub_status_data,
+-00124         .hub_control = hub_control,
+-00125         //.bus_suspend =                
+-00126         //.bus_resume =         
+-00127 };
+-00128 
+-00130 static inline dwc_otg_hcd_t *hcd_to_dwc_otg_hcd(struct usb_hcd *hcd)
+-00131 {
+-00132         struct wrapper_priv_data *p;
+-00133         p = (struct wrapper_priv_data *)(hcd->hcd_priv);
+-00134         return p->dwc_otg_hcd;
+-00135 }
+-00136 
+-00138 static inline struct usb_hcd *dwc_otg_hcd_to_hcd(dwc_otg_hcd_t * dwc_otg_hcd)
+-00139 {
+-00140         return dwc_otg_hcd_get_priv_data(dwc_otg_hcd);
+-00141 }
+-00142 
+-00144 inline struct usb_host_endpoint *dwc_urb_to_endpoint(struct urb *urb)
+-00145 {
+-00146         struct usb_device *dev = urb->dev;
+-00147         int ep_num = usb_pipeendpoint(urb->pipe);
+-00148 
+-00149         if (usb_pipein(urb->pipe))
+-00150                 return dev->ep_in[ep_num];
+-00151         else
+-00152                 return dev->ep_out[ep_num];
+-00153 }
+-00154 
+-00155 static int _disconnect(dwc_otg_hcd_t * hcd)
+-00156 {
+-00157         struct usb_hcd *usb_hcd = dwc_otg_hcd_to_hcd(hcd);
+-00158 
+-00159         usb_hcd->self.is_b_host = 0;
+-00160         return 0;
+-00161 }
+-00162 
+-00163 static int _start(dwc_otg_hcd_t * hcd)
+-00164 {
+-00165         struct usb_hcd *usb_hcd = dwc_otg_hcd_to_hcd(hcd);
+-00166 
+-00167         usb_hcd->self.is_b_host = dwc_otg_hcd_is_b_host(hcd);
+-00168         hcd_start(usb_hcd);
+-00169 
+-00170         return 0;
+-00171 }
+-00172 
+-00173 static int _hub_info(dwc_otg_hcd_t * hcd, void *urb_handle, uint32_t * hub_addr,
+-00174                      uint32_t * port_addr)
+-00175 {
+-00176         struct urb *urb = (struct urb *)urb_handle;
+-00177         if (urb->dev->tt) {
+-00178                 *hub_addr = urb->dev->tt->hub->devnum;
+-00179         } else {
+-00180                 *hub_addr = 0;
+-00181         }
+-00182         *port_addr = urb->dev->ttport;
+-00183         return 0;
+-00184 }
+-00185 
+-00186 static int _speed(dwc_otg_hcd_t * hcd, void *urb_handle)
+-00187 {
+-00188         struct urb *urb = (struct urb *)urb_handle;
+-00189         return urb->dev->speed;
+-00190 }
+-00191 
+-00192 static int _get_b_hnp_enable(dwc_otg_hcd_t * hcd)
+-00193 {
+-00194         struct usb_hcd *usb_hcd = dwc_otg_hcd_to_hcd(hcd);
+-00195         return usb_hcd->self.b_hnp_enable;
+-00196 }
+-00197 
+-00198 static void allocate_bus_bandwidth(struct usb_hcd *hcd, uint32_t bw,
+-00199                                    struct urb *urb)
+-00200 {
+-00201         hcd_to_bus(hcd)->bandwidth_allocated += bw / urb->interval;
+-00202         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
+-00203                 hcd_to_bus(hcd)->bandwidth_isoc_reqs++;
+-00204         } else {
+-00205                 hcd_to_bus(hcd)->bandwidth_int_reqs++;
+-00206         }
+-00207 }
+-00208 
+-00209 static void free_bus_bandwidth(struct usb_hcd *hcd, uint32_t bw,
+-00210                                struct urb *urb)
+-00211 {
+-00212         hcd_to_bus(hcd)->bandwidth_allocated -= bw / urb->interval;
+-00213         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
+-00214                 hcd_to_bus(hcd)->bandwidth_isoc_reqs--;
+-00215         } else {
+-00216                 hcd_to_bus(hcd)->bandwidth_int_reqs--;
+-00217         }
+-00218 }
+-00219 
+-00224 static int _complete(dwc_otg_hcd_t * hcd, void *urb_handle,
+-00225                      dwc_otg_hcd_urb_t * dwc_otg_urb, int32_t status)
+-00226 {
+-00227         struct urb *urb = (struct urb *)urb_handle;
+-00228 #ifdef DEBUG
+-00229         if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
+-00230                 DWC_PRINTF("%s: urb %p, device %d, ep %d %s, status=%d\n",
+-00231                            __func__, urb, usb_pipedevice(urb->pipe),
+-00232                            usb_pipeendpoint(urb->pipe),
+-00233                            usb_pipein(urb->pipe) ? "IN" : "OUT", status);
+-00234                 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
+-00235                         int i;
+-00236                         for (i = 0; i < urb->number_of_packets; i++) {
+-00237                                 DWC_PRINTF("  ISO Desc %d status: %d\n",
+-00238                                            i, urb->iso_frame_desc[i].status);
+-00239                         }
+-00240                 }
+-00241         }
+-00242 #endif
+-00243 
+-00244         urb->actual_length = dwc_otg_hcd_urb_get_actual_length(dwc_otg_urb);
+-00245         /* Convert status value. */
+-00246         switch (status) {
+-00247         case -DWC_E_PROTOCOL:
+-00248                 status = -EPROTO;
+-00249                 break;
+-00250         case -DWC_E_IN_PROGRESS:
+-00251                 status = -EINPROGRESS;
+-00252                 break;
+-00253         case -DWC_E_PIPE:
+-00254                 status = -EPIPE;
+-00255                 break;
+-00256         case -DWC_E_IO:
+-00257                 status = -EIO;
+-00258                 break;
+-00259         case -DWC_E_TIMEOUT:
+-00260                 status = -ETIMEDOUT;
+-00261                 break;
+-00262         case -DWC_E_OVERFLOW:
+-00263                 status = -EOVERFLOW;
+-00264                 break;
+-00265         default:
+-00266                 if (status) {
+-00267                         DWC_PRINTF("Uknown urb status %d\n", status);
+-00268 
+-00269                 }
+-00270         }
+-00271 
+-00272         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
+-00273                 int i;
+-00274 
+-00275                 urb->error_count = dwc_otg_hcd_urb_get_error_count(dwc_otg_urb);
+-00276                 for (i = 0; i < urb->number_of_packets; ++i) {
+-00277                         urb->iso_frame_desc[i].actual_length =
+-00278                             dwc_otg_hcd_urb_get_iso_desc_actual_length
+-00279                             (dwc_otg_urb, i);
+-00280                         urb->iso_frame_desc[i].status =
+-00281                             dwc_otg_hcd_urb_get_iso_desc_status
+-00282                             (dwc_otg_urb, i);
+-00283                 }
+-00284         }
+-00285 
+-00286         urb->status = status;
+-00287         urb->hcpriv = NULL;
+-00288         if (!status) {
+-00289                 if ((urb->transfer_flags & URB_SHORT_NOT_OK) &&
+-00290                     (urb->actual_length < urb->transfer_buffer_length)) {
+-00291                         urb->status = -EREMOTEIO;
+-00292                 }
+-00293         }
+-00294 
+-00295         if ((usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) ||
+-00296             (usb_pipetype(urb->pipe) == PIPE_INTERRUPT)) {
+-00297                 struct usb_host_endpoint *ep = dwc_urb_to_endpoint(urb);
+-00298                 if (ep) {
+-00299                         free_bus_bandwidth(dwc_otg_hcd_to_hcd(hcd),
+-00300                                            dwc_otg_hcd_get_ep_bandwidth(hcd,
+-00301                                                                         ep->
+-00302                                                                         hcpriv),
+-00303                                            urb);
+-00304                 }
+-00305         }
+-00306 
+-00307         dwc_free(dwc_otg_urb);
+-00308         usb_hcd_giveback_urb(dwc_otg_hcd_to_hcd(hcd), urb);
+-00309         return 0;
+-00310 }
+-00311 
+-00312 static struct dwc_otg_hcd_function_ops hcd_fops = {
+-00313         .start = _start,
+-00314         .disconnect = _disconnect,
+-00315         .hub_info = _hub_info,
+-00316         .speed = _speed,
+-00317         .complete = _complete,
+-00318         .get_b_hnp_enable = _get_b_hnp_enable,
+-00319 };
+-00320 
+-00327 int hcd_init(
+-00328 #ifdef LM_INTERFACE
+-00329         struct lm_device *_dev
+-00330 #elif  PCI_INTERFACE
+-00331         struct pci_dev *_dev
+-00332 #endif
+-00333         )
+-00334 {
+-00335         struct usb_hcd *hcd = NULL;
+-00336         dwc_otg_hcd_t *dwc_otg_hcd = NULL;
+-00337 #ifdef LM_INTERFACE
+-00338         dwc_otg_device_t *otg_dev = lm_get_drvdata(_dev);
+-00339 #elif  PCI_INTERFACE
+-00340         dwc_otg_device_t *otg_dev = pci_get_drvdata(_dev);
+-00341 #endif
+-00342 
+-00343         int retval = 0;
+-00344 
+-00345         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD INIT\n");
+-00346 
+-00347         /* Set device flags indicating whether the HCD supports DMA. */
+-00348         if (dwc_otg_is_dma_enable(otg_dev->core_if)) {
+-00349 #ifdef LM_INTERFACE
+-00350                 _dev->dev.dma_mask = (void *)~0;
+-00351                 _dev->dev.coherent_dma_mask = ~0;
+-00352 #elif  PCI_INTERFACE
+-00353                 pci_set_dma_mask(_dev,DMA_32BIT_MASK);          
+-00354                 pci_set_consistent_dma_mask(_dev,DMA_32BIT_MASK);
+-00355 #endif
+-00356 
+-00357         } else {
+-00358 #ifdef LM_INTERFACE
+-00359                 _dev->dev.dma_mask = (void *)0;
+-00360                 _dev->dev.coherent_dma_mask = 0;
+-00361 #elif  PCI_INTERFACE
+-00362                 pci_set_dma_mask(_dev,0);               
+-00363                 pci_set_consistent_dma_mask(_dev,0);
+-00364 #endif
+-00365         }
+-00366 
+-00367         /*
+-00368          * Allocate memory for the base HCD plus the DWC OTG HCD.
+-00369          * Initialize the base HCD.
+-00370          */
+-00371         hcd = usb_create_hcd(&dwc_otg_hc_driver, &_dev->dev, _dev->dev.bus_id);
+-00372         if (!hcd) {
+-00373                 retval = -ENOMEM;
+-00374                 goto error1;
+-00375         }
+-00376 
+-00377         hcd->regs = otg_dev->base;
+-00378 
+-00379         /* Initialize the DWC OTG HCD. */
+-00380         dwc_otg_hcd = dwc_otg_hcd_alloc_hcd();
+-00381         if (!dwc_otg_hcd) {
+-00382                 goto error2;
+-00383         }
+-00384         ((struct wrapper_priv_data *)(hcd->hcd_priv))->dwc_otg_hcd =
+-00385             dwc_otg_hcd;
+-00386         otg_dev->hcd = dwc_otg_hcd;
+-00387 
+-00388         if (dwc_otg_hcd_init(dwc_otg_hcd, otg_dev->core_if)) {
+-00389                 goto error2;
+-00390         }
+-00391 
+-00392         hcd->self.otg_port = dwc_otg_hcd_otg_port(dwc_otg_hcd);
+-00393 
+-00394         /*
+-00395          * Finish generic HCD initialization and start the HCD. This function
+-00396          * allocates the DMA buffer pool, registers the USB bus, requests the
+-00397          * IRQ line, and calls hcd_start method.
+-00398          */
+-00399         retval = usb_add_hcd(hcd, _dev->irq, SA_SHIRQ);
+-00400         if (retval < 0) {
+-00401                 goto error2;
+-00402         }
+-00403 
+-00404         dwc_otg_hcd_set_priv_data(dwc_otg_hcd, hcd);
+-00405         return 0;
+-00406 
+-00407       error2:
+-00408         usb_put_hcd(hcd);
+-00409       error1:
+-00410         return retval;
+-00411 }
+-00412 
+-00417 void hcd_remove(
+-00418 #ifdef LM_INTERFACE
+-00419         struct lm_device *_dev
+-00420 #elif  PCI_INTERFACE
+-00421         struct pci_dev *_dev
+-00422 #endif
+-00423         )
+-00424 {
+-00425 #ifdef LM_INTERFACE
+-00426         dwc_otg_device_t *otg_dev = lm_get_drvdata(_dev);
+-00427 #elif  PCI_INTERFACE
+-00428         dwc_otg_device_t *otg_dev = pci_get_drvdata(_dev);
+-00429 #endif
+-00430 
+-00431         dwc_otg_hcd_t *dwc_otg_hcd;
+-00432         struct usb_hcd *hcd;
+-00433 
+-00434         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD REMOVE\n");
+-00435 
+-00436         if (!otg_dev) {
+-00437                 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev NULL!\n", __func__);
+-00438                 return;
+-00439         }
+-00440 
+-00441         dwc_otg_hcd = otg_dev->hcd;
+-00442 
+-00443         if (!dwc_otg_hcd) {
+-00444                 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->hcd NULL!\n", __func__);
+-00445                 return;
+-00446         }
+-00447 
+-00448         hcd = dwc_otg_hcd_to_hcd(dwc_otg_hcd);
+-00449 
+-00450         if (!hcd) {
+-00451                 DWC_DEBUGPL(DBG_ANY,
+-00452                             "%s: dwc_otg_hcd_to_hcd(dwc_otg_hcd) NULL!\n",
+-00453                             __func__);
+-00454                 return;
+-00455         }
+-00456         usb_remove_hcd(hcd);
+-00457         dwc_otg_hcd_set_priv_data(dwc_otg_hcd, NULL);
+-00458         dwc_otg_hcd_remove(dwc_otg_hcd);
+-00459         usb_put_hcd(hcd);
+-00460 }
+-00461 
+-00462 /* =========================================================================
+-00463  *  Linux HC Driver Functions
+-00464  * ========================================================================= */
+-00465 
+-00469 int hcd_start(struct usb_hcd *hcd)
+-00470 {
+-00471         dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
+-00472         struct usb_bus *bus;
+-00473 
+-00474         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD START\n");
+-00475         bus = hcd_to_bus(hcd);
+-00476 
+-00477         hcd->state = HC_STATE_RUNNING;
+-00478         if (dwc_otg_hcd_start(dwc_otg_hcd, &hcd_fops)) {
+-00479                 return 0;
+-00480         }
+-00481 
+-00482         /* Initialize and connect root hub if one is not already attached */
+-00483         if (bus->root_hub) {
+-00484                 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Has Root Hub\n");
+-00485                 /* Inform the HUB driver to resume. */
+-00486                 usb_hcd_resume_root_hub(hcd);
+-00487         }
+-00488 
+-00489         return 0;
+-00490 }
+-00491 
+-00496 void hcd_stop(struct usb_hcd *hcd)
+-00497 {
+-00498         dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
+-00499 
+-00500         dwc_otg_hcd_stop(dwc_otg_hcd);
+-00501 }
+-00502 
+-00504 static int get_frame_number(struct usb_hcd *hcd)
+-00505 {
+-00506         dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
+-00507 
+-00508         return dwc_otg_hcd_get_frame_number(dwc_otg_hcd);
+-00509 }
+-00510 
+-00511 #ifdef DEBUG
+-00512 static void dump_urb_info(struct urb *urb, char *fn_name)
+-00513 {
+-00514         DWC_PRINTF("%s, urb %p\n", fn_name, urb);
+-00515         DWC_PRINTF("  Device address: %d\n", usb_pipedevice(urb->pipe));
+-00516         DWC_PRINTF("  Endpoint: %d, %s\n", usb_pipeendpoint(urb->pipe),
+-00517                    (usb_pipein(urb->pipe) ? "IN" : "OUT"));
+-00518         DWC_PRINTF("  Endpoint type: %s\n", ( {
+-00519                                              char *pipetype;
+-00520                                              switch (usb_pipetype(urb->pipe)) {
+-00521 case PIPE_CONTROL:
+-00522 pipetype = "CONTROL"; break; case PIPE_BULK:
+-00523 pipetype = "BULK"; break; case PIPE_INTERRUPT:
+-00524 pipetype = "INTERRUPT"; break; case PIPE_ISOCHRONOUS:
+-00525 pipetype = "ISOCHRONOUS"; break; default:
+-00526                                              pipetype = "UNKNOWN"; break;};
+-00527                                              pipetype;}
+-00528                    )) ;
+-00529         DWC_PRINTF("  Speed: %s\n", ( {
+-00530                                      char *speed; switch (urb->dev->speed) {
+-00531 case USB_SPEED_HIGH:
+-00532 speed = "HIGH"; break; case USB_SPEED_FULL:
+-00533 speed = "FULL"; break; case USB_SPEED_LOW:
+-00534 speed = "LOW"; break; default:
+-00535                                      speed = "UNKNOWN"; break;};
+-00536                                      speed;}
+-00537                    )) ;
+-00538         DWC_PRINTF("  Max packet size: %d\n",
+-00539                    usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe)));
+-00540         DWC_PRINTF("  Data buffer length: %d\n", urb->transfer_buffer_length);
+-00541         DWC_PRINTF("  Transfer buffer: %p, Transfer DMA: %p\n",
+-00542                    urb->transfer_buffer, (void *)urb->transfer_dma);
+-00543         DWC_PRINTF("  Setup buffer: %p, Setup DMA: %p\n",
+-00544                    urb->setup_packet, (void *)urb->setup_dma);
+-00545         DWC_PRINTF("  Interval: %d\n", urb->interval);
+-00546         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
+-00547                 int i;
+-00548                 for (i = 0; i < urb->number_of_packets; i++) {
+-00549                         DWC_PRINTF("  ISO Desc %d:\n", i);
+-00550                         DWC_PRINTF("    offset: %d, length %d\n",
+-00551                                    urb->iso_frame_desc[i].offset,
+-00552                                    urb->iso_frame_desc[i].length);
+-00553                 }
+-00554         }
+-00555 }
+-00556 
+-00557 #endif
+-00558 
+-00562 static int urb_enqueue(struct usb_hcd *hcd,
+-00563                        struct usb_host_endpoint *ep,
+-00564                        struct urb *urb, gfp_t mem_flags)
+-00565 {
+-00566         int retval = 0;
+-00567         dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
+-00568         dwc_otg_hcd_urb_t *dwc_otg_urb;
+-00569         int i;
+-00570         int alloc_bandwidth = 0;
+-00571         uint8_t ep_type = 0;
+-00572         uint32_t flags = 0;
+-00573         void *buf;
+-00574 
+-00575 #ifdef DEBUG
+-00576         if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
+-00577                 dump_urb_info(urb, "urb_enqueue");
+-00578         }
+-00579 #endif
+-00580 
+-00581         if ((usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
+-00582             || (usb_pipetype(urb->pipe) == PIPE_INTERRUPT)) {
+-00583                 if (!dwc_otg_hcd_is_bandwidth_allocated
+-00584                     (dwc_otg_hcd, &ep->hcpriv)) {
+-00585                         alloc_bandwidth = 1;
+-00586                 }
+-00587         }
+-00588 
+-00589         switch (usb_pipetype(urb->pipe)) {
+-00590         case PIPE_CONTROL:
+-00591                 ep_type = USB_ENDPOINT_XFER_CONTROL;
+-00592                 break;
+-00593         case PIPE_ISOCHRONOUS:
+-00594                 ep_type = USB_ENDPOINT_XFER_ISOC;
+-00595                 break;
+-00596         case PIPE_BULK:
+-00597                 ep_type = USB_ENDPOINT_XFER_BULK;
+-00598                 break;
+-00599         case PIPE_INTERRUPT:
+-00600                 ep_type = USB_ENDPOINT_XFER_INT;
+-00601                 break;
+-00602         default:
+-00603                 DWC_WARN("Wrong ep type\n");
+-00604         }
+-00605 
+-00606         dwc_otg_urb = dwc_otg_hcd_urb_alloc(dwc_otg_hcd,
+-00607                                             urb->number_of_packets,
+-00608                                             mem_flags == GFP_ATOMIC ? 1 : 0);
+-00609 
+-00610         dwc_otg_hcd_urb_set_pipeinfo(dwc_otg_urb, usb_pipedevice(urb->pipe),
+-00611                                      usb_pipeendpoint(urb->pipe), ep_type,
+-00612                                      usb_pipein(urb->pipe),
+-00613                                      usb_maxpacket(urb->dev, urb->pipe,
+-00614                                                    !(usb_pipein(urb->pipe))));
+-00615 
+-00616         buf = urb->transfer_buffer;
+-00617         if (hcd->self.uses_dma) {
+-00618                 /*
+-00619                  * Calculate virtual address from physical address,
+-00620                  * because some class driver may not fill transfer_buffer.
+-00621                  * In Buffer DMA mode virual address is used,
+-00622                  * when handling non DWORD aligned buffers.
+-00623                  */
+-00624                 buf = phys_to_virt(urb->transfer_dma);
+-00625         }
+-00626         
+-00627         if (!(urb->transfer_flags & URB_NO_INTERRUPT))
+-00628                 flags |= URB_GIVEBACK_ASAP;
+-00629         if (urb->transfer_flags & URB_ZERO_PACKET)
+-00630                 flags |= URB_SEND_ZERO_PACKET;
+-00631 
+-00632         dwc_otg_hcd_urb_set_params(dwc_otg_urb, urb, buf,
+-00633                                    urb->transfer_dma,
+-00634                                    urb->transfer_buffer_length,
+-00635                                    urb->setup_packet, 
+-00636                                    urb->setup_dma,
+-00637                                    flags,
+-00638                                    urb->interval);
+-00639 
+-00640         for (i = 0; i < urb->number_of_packets; ++i) {
+-00641                 dwc_otg_hcd_urb_set_iso_desc_params(dwc_otg_urb, i,
+-00642                                                     urb->iso_frame_desc[i].
+-00643                                                     offset,
+-00644                                                     urb->iso_frame_desc[i].
+-00645                                                     length);
+-00646         }
+-00647 
+-00648         urb->hcpriv = dwc_otg_urb;
+-00649         retval = dwc_otg_hcd_urb_enqueue(dwc_otg_hcd, dwc_otg_urb, &ep->hcpriv);
+-00650         if (!retval) {
+-00651                 if (alloc_bandwidth) {
+-00652                         allocate_bus_bandwidth(hcd,
+-00653                                                dwc_otg_hcd_get_ep_bandwidth
+-00654                                                (dwc_otg_hcd, ep->hcpriv), urb);
+-00655                 }
+-00656         } else {
+-00657                 if (retval == -DWC_E_NO_DEVICE) {
+-00658                         retval = -ENODEV;
+-00659                 }
+-00660         }
+-00661 
+-00662         return retval;
+-00663 }
+-00664 
+-00667 static int urb_dequeue(struct usb_hcd *hcd, struct urb *urb)
+-00668 {
+-00669         dwc_otg_hcd_t *dwc_otg_hcd;
+-00670         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD URB Dequeue\n");
+-00671 
+-00672         dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
+-00673 
+-00674 #ifdef DEBUG
+-00675         if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
+-00676                 dump_urb_info(urb, "urb_dequeue");
+-00677         }
+-00678 #endif
+-00679         dwc_otg_hcd_urb_dequeue(dwc_otg_hcd, urb->hcpriv);
+-00680 
+-00681         dwc_free(urb->hcpriv);
+-00682         urb->hcpriv = NULL;
+-00683 
+-00684         /* Higher layer software sets URB status. */
+-00685         usb_hcd_giveback_urb(hcd, urb);
+-00686         if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
+-00687                 DWC_PRINTF("Called usb_hcd_giveback_urb()\n");
+-00688                 DWC_PRINTF("  urb->status = %d\n", urb->status);
+-00689         }
+-00690 
+-00691         return 0;
+-00692 }
+-00693 
+-00694 /* Frees resources in the DWC_otg controller related to a given endpoint. Also
+-00695  * clears state in the HCD related to the endpoint. Any URBs for the endpoint
+-00696  * must already be dequeued. */
+-00697 static void endpoint_disable(struct usb_hcd *hcd, struct usb_host_endpoint *ep)
+-00698 {
+-00699         dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
+-00700 
+-00701         DWC_DEBUGPL(DBG_HCD,
+-00702                     "DWC OTG HCD EP DISABLE: _bEndpointAddress=0x%02x, "
+-00703                     "endpoint=%d\n", ep->desc.bEndpointAddress,
+-00704                     dwc_ep_addr_to_endpoint(ep->desc.bEndpointAddress));
+-00705         dwc_otg_hcd_endpoint_disable(dwc_otg_hcd, ep->hcpriv, 250);
+-00706         ep->hcpriv = NULL;
+-00707 }
+-00708 
+-00714 static irqreturn_t dwc_otg_hcd_irq(struct usb_hcd *hcd)
+-00715 {
+-00716         dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
+-00717         int32_t retval = dwc_otg_hcd_handle_intr(dwc_otg_hcd);
+-00718         if (retval != 0) {
+-00719                 S3C2410X_CLEAR_EINTPEND();
+-00720         }
+-00721         return IRQ_RETVAL(retval);
+-00722 }
+-00723 
+-00728 int hub_status_data(struct usb_hcd *hcd, char *buf)
+-00729 {
+-00730         dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
+-00731 
+-00732         buf[0] = 0;
+-00733         buf[0] |= (dwc_otg_hcd_is_status_changed(dwc_otg_hcd, 1)) << 1;
+-00734 
+-00735         return (buf[0] != 0);
+-00736 }
+-00737 
+-00739 int hub_control(struct usb_hcd *hcd,
+-00740                 u16 typeReq, u16 wValue, u16 wIndex, char *buf, u16 wLength)
+-00741 {
+-00742         int retval;
+-00743 
+-00744         retval = dwc_otg_hcd_hub_control(hcd_to_dwc_otg_hcd(hcd),
+-00745                                          typeReq, wValue, wIndex, buf, wLength);
+-00746 
+-00747         switch (retval) {
+-00748         case -DWC_E_INVALID:
+-00749                 retval = -EINVAL;
+-00750                 break;
+-00751         }
+-00752 
+-00753         return retval;
+-00754 }
+-00755 
+-00756 #endif                          /* DWC_DEVICE_ONLY */
+-
    Generated on Tue May 5 02:22:48 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++
    Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
    ++

    dwc_otg_hcd_linux.c

    Go to the documentation of this file.
    00001 /* ==========================================================================
++00002  * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd_linux.c $
++00003  * $Revision: #20 $
++00004  * $Date: 2011/10/26 $
++00005  * $Change: 1872981 $
++00006  *
++00007  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
++00008  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
++00009  * otherwise expressly agreed to in writing between Synopsys and you.
++00010  *
++00011  * The Software IS NOT an item of Licensed Software or Licensed Product under
++00012  * any End User Software License Agreement or Agreement for Licensed Product
++00013  * with Synopsys or any supplement thereto. You are permitted to use and
++00014  * redistribute this Software in source and binary forms, with or without
++00015  * modification, provided that redistributions of source code must retain this
++00016  * notice. You may not view, use, disclose, copy or distribute this file or
++00017  * any information contained herein except pursuant to this license grant from
++00018  * Synopsys. If you do not agree with this notice, including the disclaimer
++00019  * below, then you are not authorized to use the Software.
++00020  *
++00021  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
++00022  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++00023  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++00024  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
++00025  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++00026  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
++00027  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
++00028  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
++00029  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
++00030  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
++00031  * DAMAGE.
++00032  * ========================================================================== */
++00033 #ifndef DWC_DEVICE_ONLY
++00034 
++00041 #include <linux/kernel.h>
++00042 #include <linux/module.h>
++00043 #include <linux/moduleparam.h>
++00044 #include <linux/init.h>
++00045 #include <linux/device.h>
++00046 #include <linux/errno.h>
++00047 #include <linux/list.h>
++00048 #include <linux/interrupt.h>
++00049 #include <linux/string.h>
++00050 #include <linux/dma-mapping.h>
++00051 #include <linux/version.h>
++00052 #include <asm/io.h>
++00053 #include <linux/usb.h>
++00054 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,35)
++00055 #include <../drivers/usb/core/hcd.h>
++00056 #else
++00057 #include <linux/usb/hcd.h>
++00058 #endif
++00059 
++00060 #include "dwc_otg_hcd_if.h"
++00061 #include "dwc_otg_dbg.h"
++00062 #include "dwc_otg_driver.h"
++00063 #include "dwc_otg_hcd.h"
++00068 #define dwc_ep_addr_to_endpoint(_bEndpointAddress_) ((_bEndpointAddress_ & USB_ENDPOINT_NUMBER_MASK) | \
++00069                                                      ((_bEndpointAddress_ & USB_DIR_IN) != 0) << 4)
++00070 
++00071 static const char dwc_otg_hcd_name[] = "dwc_otg_hcd";
++00072 
++00075 static int urb_enqueue(struct usb_hcd *hcd,
++00076 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28)
++00077                        struct usb_host_endpoint *ep,
++00078 #endif
++00079                        struct urb *urb, gfp_t mem_flags);
++00080 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28)
++00081 static int urb_dequeue(struct usb_hcd *hcd, struct urb *urb);
++00082 #else
++00083 static int urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status);
++00084 #endif
++00085 
++00086 static void endpoint_disable(struct usb_hcd *hcd, struct usb_host_endpoint *ep);
++00087 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,30)
++00088 static void endpoint_reset(struct usb_hcd *hcd, struct usb_host_endpoint *ep);
++00089 #endif
++00090 static irqreturn_t dwc_otg_hcd_irq(struct usb_hcd *hcd);
++00091 extern int hcd_start(struct usb_hcd *hcd);
++00092 extern void hcd_stop(struct usb_hcd *hcd);
++00093 static int get_frame_number(struct usb_hcd *hcd);
++00094 extern int hub_status_data(struct usb_hcd *hcd, char *buf);
++00095 extern int hub_control(struct usb_hcd *hcd,
++00096                        u16 typeReq,
++00097                        u16 wValue, u16 wIndex, char *buf, u16 wLength);
++00098 
++00099 struct wrapper_priv_data {
++00100         dwc_otg_hcd_t *dwc_otg_hcd;
++00101 };
++00102 
++00105 static struct hc_driver dwc_otg_hc_driver = {
++00106 
++00107         .description = dwc_otg_hcd_name,
++00108         .product_desc = "DWC OTG Controller",
++00109         .hcd_priv_size = sizeof(struct wrapper_priv_data),
++00110 
++00111         .irq = dwc_otg_hcd_irq,
++00112 
++00113         .flags = HCD_MEMORY | HCD_USB2,
++00114 
++00115         //.reset =              
++00116         .start = hcd_start,
++00117         //.suspend =            
++00118         //.resume =             
++00119         .stop = hcd_stop,
++00120 
++00121         .urb_enqueue = urb_enqueue,
++00122         .urb_dequeue = urb_dequeue,
++00123         .endpoint_disable = endpoint_disable,
++00124 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,30)
++00125         .endpoint_reset = endpoint_reset,
++00126 #endif
++00127         .get_frame_number = get_frame_number,
++00128 
++00129         .hub_status_data = hub_status_data,
++00130         .hub_control = hub_control,
++00131         //.bus_suspend =                
++00132         //.bus_resume =         
++00133 };
++00134 
++00136 static inline dwc_otg_hcd_t *hcd_to_dwc_otg_hcd(struct usb_hcd *hcd)
++00137 {
++00138         struct wrapper_priv_data *p;
++00139         p = (struct wrapper_priv_data *)(hcd->hcd_priv);
++00140         return p->dwc_otg_hcd;
++00141 }
++00142 
++00144 static inline struct usb_hcd *dwc_otg_hcd_to_hcd(dwc_otg_hcd_t * dwc_otg_hcd)
++00145 {
++00146         return dwc_otg_hcd_get_priv_data(dwc_otg_hcd);
++00147 }
++00148 
++00150 inline struct usb_host_endpoint *dwc_urb_to_endpoint(struct urb *urb)
++00151 {
++00152         struct usb_device *dev = urb->dev;
++00153         int ep_num = usb_pipeendpoint(urb->pipe);
++00154 
++00155         if (usb_pipein(urb->pipe))
++00156                 return dev->ep_in[ep_num];
++00157         else
++00158                 return dev->ep_out[ep_num];
++00159 }
++00160 
++00161 static int _disconnect(dwc_otg_hcd_t * hcd)
++00162 {
++00163         struct usb_hcd *usb_hcd = dwc_otg_hcd_to_hcd(hcd);
++00164 
++00165         usb_hcd->self.is_b_host = 0;
++00166         return 0;
++00167 }
++00168 
++00169 static int _start(dwc_otg_hcd_t * hcd)
++00170 {
++00171         struct usb_hcd *usb_hcd = dwc_otg_hcd_to_hcd(hcd);
++00172 
++00173         usb_hcd->self.is_b_host = dwc_otg_hcd_is_b_host(hcd);
++00174         hcd_start(usb_hcd);
++00175 
++00176         return 0;
++00177 }
++00178 
++00179 static int _hub_info(dwc_otg_hcd_t * hcd, void *urb_handle, uint32_t * hub_addr,
++00180                      uint32_t * port_addr)
++00181 {
++00182         struct urb *urb = (struct urb *)urb_handle;
++00183         if (urb->dev->tt) {
++00184                 *hub_addr = urb->dev->tt->hub->devnum;
++00185         } else {
++00186                 *hub_addr = 0;
++00187         }
++00188         *port_addr = urb->dev->ttport;
++00189         return 0;
++00190 }
++00191 
++00192 static int _speed(dwc_otg_hcd_t * hcd, void *urb_handle)
++00193 {
++00194         struct urb *urb = (struct urb *)urb_handle;
++00195         return urb->dev->speed;
++00196 }
++00197 
++00198 static int _get_b_hnp_enable(dwc_otg_hcd_t * hcd)
++00199 {
++00200         struct usb_hcd *usb_hcd = dwc_otg_hcd_to_hcd(hcd);
++00201         return usb_hcd->self.b_hnp_enable;
++00202 }
++00203 
++00204 static void allocate_bus_bandwidth(struct usb_hcd *hcd, uint32_t bw,
++00205                                    struct urb *urb)
++00206 {
++00207         hcd_to_bus(hcd)->bandwidth_allocated += bw / urb->interval;
++00208         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
++00209                 hcd_to_bus(hcd)->bandwidth_isoc_reqs++;
++00210         } else {
++00211                 hcd_to_bus(hcd)->bandwidth_int_reqs++;
++00212         }
++00213 }
++00214 
++00215 static void free_bus_bandwidth(struct usb_hcd *hcd, uint32_t bw,
++00216                                struct urb *urb)
++00217 {
++00218         hcd_to_bus(hcd)->bandwidth_allocated -= bw / urb->interval;
++00219         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
++00220                 hcd_to_bus(hcd)->bandwidth_isoc_reqs--;
++00221         } else {
++00222                 hcd_to_bus(hcd)->bandwidth_int_reqs--;
++00223         }
++00224 }
++00225 
++00230 static int _complete(dwc_otg_hcd_t * hcd, void *urb_handle,
++00231                      dwc_otg_hcd_urb_t * dwc_otg_urb, int32_t status)
++00232 {
++00233         struct urb *urb = (struct urb *)urb_handle;
++00234 #ifdef DEBUG
++00235         if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
++00236                 DWC_PRINTF("%s: urb %p, device %d, ep %d %s, status=%d\n",
++00237                            __func__, urb, usb_pipedevice(urb->pipe),
++00238                            usb_pipeendpoint(urb->pipe),
++00239                            usb_pipein(urb->pipe) ? "IN" : "OUT", status);
++00240                 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
++00241                         int i;
++00242                         for (i = 0; i < urb->number_of_packets; i++) {
++00243                                 DWC_PRINTF("  ISO Desc %d status: %d\n",
++00244                                            i, urb->iso_frame_desc[i].status);
++00245                         }
++00246                 }
++00247         }
++00248 #endif
++00249 
++00250         urb->actual_length = dwc_otg_hcd_urb_get_actual_length(dwc_otg_urb);
++00251         /* Convert status value. */
++00252         switch (status) {
++00253         case -DWC_E_PROTOCOL:
++00254                 status = -EPROTO;
++00255                 break;
++00256         case -DWC_E_IN_PROGRESS:
++00257                 status = -EINPROGRESS;
++00258                 break;
++00259         case -DWC_E_PIPE:
++00260                 status = -EPIPE;
++00261                 break;
++00262         case -DWC_E_IO:
++00263                 status = -EIO;
++00264                 break;
++00265         case -DWC_E_TIMEOUT:
++00266                 status = -ETIMEDOUT;
++00267                 break;
++00268         case -DWC_E_OVERFLOW:
++00269                 status = -EOVERFLOW;
++00270                 break;
++00271         default:
++00272                 if (status) {
++00273                         DWC_PRINTF("Uknown urb status %d\n", status);
++00274 
++00275                 }
++00276         }
++00277 
++00278         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
++00279                 int i;
++00280 
++00281                 urb->error_count = dwc_otg_hcd_urb_get_error_count(dwc_otg_urb);
++00282                 for (i = 0; i < urb->number_of_packets; ++i) {
++00283                         urb->iso_frame_desc[i].actual_length =
++00284                             dwc_otg_hcd_urb_get_iso_desc_actual_length
++00285                             (dwc_otg_urb, i);
++00286                         urb->iso_frame_desc[i].status =
++00287                             dwc_otg_hcd_urb_get_iso_desc_status(dwc_otg_urb, i);
++00288                 }
++00289         }
++00290 
++00291         urb->status = status;
++00292         urb->hcpriv = NULL;
++00293         if (!status) {
++00294                 if ((urb->transfer_flags & URB_SHORT_NOT_OK) &&
++00295                     (urb->actual_length < urb->transfer_buffer_length)) {
++00296                         urb->status = -EREMOTEIO;
++00297                 }
++00298         }
++00299 
++00300         if ((usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) ||
++00301             (usb_pipetype(urb->pipe) == PIPE_INTERRUPT)) {
++00302                 struct usb_host_endpoint *ep = dwc_urb_to_endpoint(urb);
++00303                 if (ep) {
++00304                         free_bus_bandwidth(dwc_otg_hcd_to_hcd(hcd),
++00305                                            dwc_otg_hcd_get_ep_bandwidth(hcd,
++00306                                                                         ep->hcpriv),
++00307                                            urb);
++00308                 }
++00309         }
++00310 
++00311         DWC_FREE(dwc_otg_urb);
++00312 
++00313         DWC_SPINUNLOCK(hcd->lock);
++00314 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28)
++00315         usb_hcd_giveback_urb(dwc_otg_hcd_to_hcd(hcd), urb);
++00316 #else
++00317         usb_hcd_giveback_urb(dwc_otg_hcd_to_hcd(hcd), urb, status);
++00318 #endif
++00319         DWC_SPINLOCK(hcd->lock);
++00320 
++00321         return 0;
++00322 }
++00323 
++00324 static struct dwc_otg_hcd_function_ops hcd_fops = {
++00325         .start = _start,
++00326         .disconnect = _disconnect,
++00327         .hub_info = _hub_info,
++00328         .speed = _speed,
++00329         .complete = _complete,
++00330         .get_b_hnp_enable = _get_b_hnp_enable,
++00331 };
++00332 
++00339 int hcd_init(
++00340 #ifdef LM_INTERFACE
++00341                     struct lm_device *_dev
++00342 #elif  defined(PCI_INTERFACE)
++00343                     struct pci_dev *_dev
++00344 #endif
++00345     )
++00346 {
++00347         struct usb_hcd *hcd = NULL;
++00348         dwc_otg_hcd_t *dwc_otg_hcd = NULL;
++00349 #ifdef LM_INTERFACE
++00350         dwc_otg_device_t *otg_dev = lm_get_drvdata(_dev);
++00351 #elif  defined(PCI_INTERFACE)
++00352         dwc_otg_device_t *otg_dev = pci_get_drvdata(_dev);
++00353 #endif
++00354 
++00355         int retval = 0;
++00356 
++00357         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD INIT\n");
++00358 
++00359         /* Set device flags indicating whether the HCD supports DMA. */
++00360         if (dwc_otg_is_dma_enable(otg_dev->core_if)) {
++00361 #ifdef LM_INTERFACE
++00362                 _dev->dev.dma_mask = (void *)~0;
++00363                 _dev->dev.coherent_dma_mask = ~0;
++00364 #elif  defined(PCI_INTERFACE)
++00365                 pci_set_dma_mask(_dev, DMA_32BIT_MASK);
++00366                 pci_set_consistent_dma_mask(_dev, DMA_32BIT_MASK);
++00367 #endif
++00368 
++00369         } else {
++00370 #ifdef LM_INTERFACE
++00371                 _dev->dev.dma_mask = (void *)0;
++00372                 _dev->dev.coherent_dma_mask = 0;
++00373 #elif  defined(PCI_INTERFACE)
++00374                 pci_set_dma_mask(_dev, 0);
++00375                 pci_set_consistent_dma_mask(_dev, 0);
++00376 #endif
++00377         }
++00378 
++00379         /*
++00380          * Allocate memory for the base HCD plus the DWC OTG HCD.
++00381          * Initialize the base HCD.
++00382          */
++00383 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30)
++00384         hcd = usb_create_hcd(&dwc_otg_hc_driver, &_dev->dev, _dev->dev.bus_id);
++00385 #else
++00386         hcd = usb_create_hcd(&dwc_otg_hc_driver, &_dev->dev, dev_name(&_dev->dev));
++00387         hcd->has_tt = 1;
++00388 //      hcd->uses_new_polling = 1;
++00389 //      hcd->poll_rh = 0;
++00390 #endif
++00391         if (!hcd) {
++00392                 retval = -ENOMEM;
++00393                 goto error1;
++00394         }
++00395 
++00396         hcd->regs = otg_dev->os_dep.base;
++00397 
++00398         /* Initialize the DWC OTG HCD. */
++00399         dwc_otg_hcd = dwc_otg_hcd_alloc_hcd();
++00400         if (!dwc_otg_hcd) {
++00401                 goto error2;
++00402         }
++00403         ((struct wrapper_priv_data *)(hcd->hcd_priv))->dwc_otg_hcd =
++00404             dwc_otg_hcd;
++00405         otg_dev->hcd = dwc_otg_hcd;
++00406 
++00407         if (dwc_otg_hcd_init(dwc_otg_hcd, otg_dev->core_if)) {
++00408                 goto error2;
++00409         }
++00410 
++00411         otg_dev->hcd->otg_dev = otg_dev;
++00412         hcd->self.otg_port = dwc_otg_hcd_otg_port(dwc_otg_hcd);
++00413 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,33) //don't support for LM(with 2.6.20.1 kernel)
++00414         hcd->self.otg_version = dwc_otg_get_otg_version(otg_dev->core_if);
++00415         /* Don't support SG list at this point */
++00416         hcd->self.sg_tablesize = 0;
++00417 #endif
++00418         /*
++00419          * Finish generic HCD initialization and start the HCD. This function
++00420          * allocates the DMA buffer pool, registers the USB bus, requests the
++00421          * IRQ line, and calls hcd_start method.
++00422          */
++00423         retval = usb_add_hcd(hcd, _dev->irq, IRQF_SHARED | IRQF_DISABLED);
++00424         if (retval < 0) {
++00425                 goto error2;
++00426         }
++00427 
++00428         dwc_otg_hcd_set_priv_data(dwc_otg_hcd, hcd);
++00429         return 0;
++00430 
++00431 error2:
++00432         usb_put_hcd(hcd);
++00433 error1:
++00434         return retval;
++00435 }
++00436 
++00441 void hcd_remove(
++00442 #ifdef LM_INTERFACE
++00443                        struct lm_device *_dev
++00444 #elif  defined(PCI_INTERFACE)
++00445                        struct pci_dev *_dev
++00446 #endif
++00447     )
++00448 {
++00449 #ifdef LM_INTERFACE
++00450         dwc_otg_device_t *otg_dev = lm_get_drvdata(_dev);
++00451 #elif  defined(PCI_INTERFACE)
++00452         dwc_otg_device_t *otg_dev = pci_get_drvdata(_dev);
++00453 #endif
++00454 
++00455         dwc_otg_hcd_t *dwc_otg_hcd;
++00456         struct usb_hcd *hcd;
++00457 
++00458         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD REMOVE\n");
++00459 
++00460         if (!otg_dev) {
++00461                 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev NULL!\n", __func__);
++00462                 return;
++00463         }
++00464 
++00465         dwc_otg_hcd = otg_dev->hcd;
++00466 
++00467         if (!dwc_otg_hcd) {
++00468                 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->hcd NULL!\n", __func__);
++00469                 return;
++00470         }
++00471 
++00472         hcd = dwc_otg_hcd_to_hcd(dwc_otg_hcd);
++00473 
++00474         if (!hcd) {
++00475                 DWC_DEBUGPL(DBG_ANY,
++00476                             "%s: dwc_otg_hcd_to_hcd(dwc_otg_hcd) NULL!\n",
++00477                             __func__);
++00478                 return;
++00479         }
++00480         usb_remove_hcd(hcd);
++00481         dwc_otg_hcd_set_priv_data(dwc_otg_hcd, NULL);
++00482         dwc_otg_hcd_remove(dwc_otg_hcd);
++00483         usb_put_hcd(hcd);
++00484 }
++00485 
++00486 /* =========================================================================
++00487  *  Linux HC Driver Functions
++00488  * ========================================================================= */
++00489 
++00493 int hcd_start(struct usb_hcd *hcd)
++00494 {
++00495         dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
++00496         struct usb_bus *bus;
++00497 
++00498         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD START\n");
++00499         bus = hcd_to_bus(hcd);
++00500 
++00501         hcd->state = HC_STATE_RUNNING;
++00502         if (dwc_otg_hcd_start(dwc_otg_hcd, &hcd_fops)) {
++00503                 return 0;
++00504         }
++00505 
++00506         /* Initialize and connect root hub if one is not already attached */
++00507         if (bus->root_hub) {
++00508                 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Has Root Hub\n");
++00509                 /* Inform the HUB driver to resume. */
++00510                 usb_hcd_resume_root_hub(hcd);
++00511         }
++00512 
++00513         return 0;
++00514 }
++00515 
++00520 void hcd_stop(struct usb_hcd *hcd)
++00521 {
++00522         dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
++00523 
++00524         dwc_otg_hcd_stop(dwc_otg_hcd);
++00525 }
++00526 
++00528 static int get_frame_number(struct usb_hcd *hcd)
++00529 {
++00530         dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
++00531 
++00532         return dwc_otg_hcd_get_frame_number(dwc_otg_hcd);
++00533 }
++00534 
++00535 #ifdef DEBUG
++00536 static void dump_urb_info(struct urb *urb, char *fn_name)
++00537 {
++00538         DWC_PRINTF("%s, urb %p\n", fn_name, urb);
++00539         DWC_PRINTF("  Device address: %d\n", usb_pipedevice(urb->pipe));
++00540         DWC_PRINTF("  Endpoint: %d, %s\n", usb_pipeendpoint(urb->pipe),
++00541                    (usb_pipein(urb->pipe) ? "IN" : "OUT"));
++00542         DWC_PRINTF("  Endpoint type: %s\n", ( {
++00543                                              char *pipetype;
++00544                                              switch (usb_pipetype(urb->pipe)) {
++00545 case PIPE_CONTROL:
++00546 pipetype = "CONTROL"; break; case PIPE_BULK:
++00547 pipetype = "BULK"; break; case PIPE_INTERRUPT:
++00548 pipetype = "INTERRUPT"; break; case PIPE_ISOCHRONOUS:
++00549 pipetype = "ISOCHRONOUS"; break; default:
++00550                                              pipetype = "UNKNOWN"; break;};
++00551                                              pipetype;}
++00552                    )) ;
++00553         DWC_PRINTF("  Speed: %s\n", ( {
++00554                                      char *speed; switch (urb->dev->speed) {
++00555 case USB_SPEED_HIGH:
++00556 speed = "HIGH"; break; case USB_SPEED_FULL:
++00557 speed = "FULL"; break; case USB_SPEED_LOW:
++00558 speed = "LOW"; break; default:
++00559                                      speed = "UNKNOWN"; break;};
++00560                                      speed;}
++00561                    )) ;
++00562         DWC_PRINTF("  Max packet size: %d\n",
++00563                    usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe)));
++00564         DWC_PRINTF("  Data buffer length: %d\n", urb->transfer_buffer_length);
++00565         DWC_PRINTF("  Transfer buffer: %p, Transfer DMA: %p\n",
++00566                    urb->transfer_buffer, (void *)urb->transfer_dma);
++00567         DWC_PRINTF("  Setup buffer: %p, Setup DMA: %p\n",
++00568                    urb->setup_packet, (void *)urb->setup_dma);
++00569         DWC_PRINTF("  Interval: %d\n", urb->interval);
++00570         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
++00571                 int i;
++00572                 for (i = 0; i < urb->number_of_packets; i++) {
++00573                         DWC_PRINTF("  ISO Desc %d:\n", i);
++00574                         DWC_PRINTF("    offset: %d, length %d\n",
++00575                                    urb->iso_frame_desc[i].offset,
++00576                                    urb->iso_frame_desc[i].length);
++00577                 }
++00578         }
++00579 }
++00580 
++00581 #endif
++00582 
++00586 static int urb_enqueue(struct usb_hcd *hcd,
++00587 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28)
++00588                        struct usb_host_endpoint *ep,
++00589 #endif
++00590                        struct urb *urb, gfp_t mem_flags)
++00591 {
++00592         int retval = 0;
++00593 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,28)
++00594         struct usb_host_endpoint *ep = urb->ep;
++00595 #endif
++00596         dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
++00597         dwc_otg_hcd_urb_t *dwc_otg_urb;
++00598         int i;
++00599         int alloc_bandwidth = 0;
++00600         uint8_t ep_type = 0;
++00601         uint32_t flags = 0;
++00602         void *buf;
++00603 
++00604 #ifdef DEBUG
++00605         if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
++00606                 dump_urb_info(urb, "urb_enqueue");
++00607         }
++00608 #endif
++00609 
++00610         if ((usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
++00611             || (usb_pipetype(urb->pipe) == PIPE_INTERRUPT)) {
++00612                 if (!dwc_otg_hcd_is_bandwidth_allocated
++00613                     (dwc_otg_hcd, &ep->hcpriv)) {
++00614                         alloc_bandwidth = 1;
++00615                 }
++00616         }
++00617 
++00618         switch (usb_pipetype(urb->pipe)) {
++00619         case PIPE_CONTROL:
++00620                 ep_type = USB_ENDPOINT_XFER_CONTROL;
++00621                 break;
++00622         case PIPE_ISOCHRONOUS:
++00623                 ep_type = USB_ENDPOINT_XFER_ISOC;
++00624                 break;
++00625         case PIPE_BULK:
++00626                 ep_type = USB_ENDPOINT_XFER_BULK;
++00627                 break;
++00628         case PIPE_INTERRUPT:
++00629                 ep_type = USB_ENDPOINT_XFER_INT;
++00630                 break;
++00631         default:
++00632                 DWC_WARN("Wrong ep type\n");
++00633         }
++00634 
++00635         dwc_otg_urb = dwc_otg_hcd_urb_alloc(dwc_otg_hcd,
++00636                                             urb->number_of_packets,
++00637                                             mem_flags == GFP_ATOMIC ? 1 : 0);
++00638 
++00639         dwc_otg_hcd_urb_set_pipeinfo(dwc_otg_urb, usb_pipedevice(urb->pipe),
++00640                                      usb_pipeendpoint(urb->pipe), ep_type,
++00641                                      usb_pipein(urb->pipe),
++00642                                      usb_maxpacket(urb->dev, urb->pipe,
++00643                                                    !(usb_pipein(urb->pipe))));
++00644 
++00645         buf = urb->transfer_buffer;
++00646         if (hcd->self.uses_dma) {
++00647                 /*
++00648                  * Calculate virtual address from physical address,
++00649                  * because some class driver may not fill transfer_buffer.
++00650                  * In Buffer DMA mode virual address is used,
++00651                  * when handling non DWORD aligned buffers.
++00652                  */
++00653                 buf = phys_to_virt(urb->transfer_dma);
++00654         }
++00655 
++00656         if (!(urb->transfer_flags & URB_NO_INTERRUPT))
++00657                 flags |= URB_GIVEBACK_ASAP;
++00658         if (urb->transfer_flags & URB_ZERO_PACKET)
++00659                 flags |= URB_SEND_ZERO_PACKET;
++00660 
++00661         dwc_otg_hcd_urb_set_params(dwc_otg_urb, urb, buf,
++00662                                    urb->transfer_dma,
++00663                                    urb->transfer_buffer_length,
++00664                                    urb->setup_packet,
++00665                                    urb->setup_dma, flags, urb->interval);
++00666 
++00667         for (i = 0; i < urb->number_of_packets; ++i) {
++00668                 dwc_otg_hcd_urb_set_iso_desc_params(dwc_otg_urb, i,
++00669                                                     urb->
++00670                                                     iso_frame_desc[i].offset,
++00671                                                     urb->
++00672                                                     iso_frame_desc[i].length);
++00673         }
++00674 
++00675         urb->hcpriv = dwc_otg_urb;
++00676         retval = dwc_otg_hcd_urb_enqueue(dwc_otg_hcd, dwc_otg_urb, &ep->hcpriv,
++00677                                          mem_flags == GFP_ATOMIC ? 1 : 0);
++00678         if (!retval) {
++00679                 if (alloc_bandwidth) {
++00680                         allocate_bus_bandwidth(hcd,
++00681                                                dwc_otg_hcd_get_ep_bandwidth
++00682                                                (dwc_otg_hcd, ep->hcpriv), urb);
++00683                 }
++00684         } else {
++00685                 if (retval == -DWC_E_NO_DEVICE) {
++00686                         retval = -ENODEV;
++00687                 }
++00688         }
++00689 
++00690         return retval;
++00691 }
++00692 
++00695 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28)
++00696 static int urb_dequeue(struct usb_hcd *hcd, struct urb *urb)
++00697 #else
++00698 static int urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
++00699 #endif
++00700 {
++00701         dwc_irqflags_t flags;
++00702         dwc_otg_hcd_t *dwc_otg_hcd;
++00703         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD URB Dequeue\n");
++00704 
++00705         dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
++00706 
++00707 #ifdef DEBUG
++00708         if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
++00709                 dump_urb_info(urb, "urb_dequeue");
++00710         }
++00711 #endif
++00712 
++00713         DWC_SPINLOCK_IRQSAVE(dwc_otg_hcd->lock, &flags);
++00714 
++00715         dwc_otg_hcd_urb_dequeue(dwc_otg_hcd, urb->hcpriv);
++00716 
++00717         DWC_FREE(urb->hcpriv);
++00718         urb->hcpriv = NULL;
++00719         DWC_SPINUNLOCK_IRQRESTORE(dwc_otg_hcd->lock, flags);
++00720 
++00721         /* Higher layer software sets URB status. */
++00722 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28)
++00723         usb_hcd_giveback_urb(hcd, urb);
++00724 #else
++00725         usb_hcd_giveback_urb(hcd, urb, status);
++00726 #endif
++00727         if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
++00728                 DWC_PRINTF("Called usb_hcd_giveback_urb()\n");
++00729                 DWC_PRINTF("  urb->status = %d\n", urb->status);
++00730         }
++00731 
++00732         return 0;
++00733 }
++00734 
++00735 /* Frees resources in the DWC_otg controller related to a given endpoint. Also
++00736  * clears state in the HCD related to the endpoint. Any URBs for the endpoint
++00737  * must already be dequeued. */
++00738 static void endpoint_disable(struct usb_hcd *hcd, struct usb_host_endpoint *ep)
++00739 {
++00740         dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
++00741 
++00742         DWC_DEBUGPL(DBG_HCD,
++00743                     "DWC OTG HCD EP DISABLE: _bEndpointAddress=0x%02x, "
++00744                     "endpoint=%d\n", ep->desc.bEndpointAddress,
++00745                     dwc_ep_addr_to_endpoint(ep->desc.bEndpointAddress));
++00746         dwc_otg_hcd_endpoint_disable(dwc_otg_hcd, ep->hcpriv, 250);
++00747         ep->hcpriv = NULL;
++00748 }
++00749 
++00750 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,30)
++00751 /* Resets endpoint specific parameter values, in current version used to reset 
++00752  * the data toggle(as a WA). This function can be called from usb_clear_halt routine */
++00753 static void endpoint_reset(struct usb_hcd *hcd, struct usb_host_endpoint *ep)
++00754 {
++00755         dwc_irqflags_t flags;
++00756         struct usb_device *udev = NULL;
++00757         int epnum = usb_endpoint_num(&ep->desc);
++00758         int is_out = usb_endpoint_dir_out(&ep->desc);
++00759         int is_control = usb_endpoint_xfer_control(&ep->desc);
++00760         dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
++00761 #ifdef LM_INTERFACE
++00762         struct lm_device *_dev = dwc_otg_hcd->otg_dev->os_dep.lmdev;
++00763 #elif defined(PCI_INTERFACE)
++00764         struct pci_dev *_dev = dwc_otg_hcd->otg_dev->os_dep.pcidev;
++00765 #endif
++00766 
++00767         if (_dev)
++00768                 udev = to_usb_device(&_dev->dev);
++00769         else
++00770                 return;
++00771 
++00772         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD EP RESET: Endpoint Num=0x%02d\n", epnum);
++00773 
++00774         DWC_SPINLOCK_IRQSAVE(dwc_otg_hcd->lock, &flags);
++00775         usb_settoggle(udev, epnum, is_out, 0);
++00776         if (is_control)
++00777                 usb_settoggle(udev, epnum, !is_out, 0);
++00778 
++00779         if (ep->hcpriv) {
++00780                 dwc_otg_hcd_endpoint_reset(dwc_otg_hcd, ep->hcpriv);
++00781         }
++00782         DWC_SPINUNLOCK_IRQRESTORE(dwc_otg_hcd->lock, flags);
++00783 }
++00784 #endif
++00785 
++00791 static irqreturn_t dwc_otg_hcd_irq(struct usb_hcd *hcd)
++00792 {
++00793         dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
++00794         int32_t retval = dwc_otg_hcd_handle_intr(dwc_otg_hcd);
++00795         if (retval != 0) {
++00796                 S3C2410X_CLEAR_EINTPEND();
++00797         }
++00798         return IRQ_RETVAL(retval);
++00799 }
++00800 
++00805 int hub_status_data(struct usb_hcd *hcd, char *buf)
++00806 {
++00807         dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
++00808 
++00809         buf[0] = 0;
++00810         buf[0] |= (dwc_otg_hcd_is_status_changed(dwc_otg_hcd, 1)) << 1;
++00811 
++00812         return (buf[0] != 0);
++00813 }
++00814 
++00816 int hub_control(struct usb_hcd *hcd,
++00817                 u16 typeReq, u16 wValue, u16 wIndex, char *buf, u16 wLength)
++00818 {
++00819         int retval;
++00820 
++00821         retval = dwc_otg_hcd_hub_control(hcd_to_dwc_otg_hcd(hcd),
++00822                                          typeReq, wValue, wIndex, buf, wLength);
++00823 
++00824         switch (retval) {
++00825         case -DWC_E_INVALID:
++00826                 retval = -EINVAL;
++00827                 break;
++00828         }
++00829 
++00830         return retval;
++00831 }
++00832 
++00833 #endif /* DWC_DEVICE_ONLY */
++
    Generated on Thu Oct 27 03:56:37 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
    ++doxygen 1.3.9.1
    + + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__hcd__linux_8c.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/dwc__otg__hcd__linux_8c.html 2013-07-26 19:31:21.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__hcd__linux_8c.html 2013-07-26 19:34:41.000000000 +0000 +@@ -2,21 +2,9 @@ + + DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_hcd_linux.c File Reference + +- + +- +-
    +-
    +-
    +-
    ++ ++
    Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
    +

    dwc_otg_hcd_linux.c File Reference

    This file contains the implementation of the HCD. More... +

    + #include <linux/kernel.h>
    +@@ -32,124 +20,136 @@ + #include <linux/version.h>
    + #include <asm/io.h>
    + #include <linux/usb.h>
    +-#include <../drivers/usb/core/hcd.h>
    +-#include "dwc_otg_hcd_if.h"
    +-#include "dwc_otg_dbg.h"
    +-#include "dwc_otg_driver.h"
    ++#include <linux/usb/hcd.h>
    ++#include "dwc_otg_hcd_if.h"
    ++#include "dwc_otg_dbg.h"
    ++#include "dwc_otg_driver.h"
    ++#include "dwc_otg_hcd.h"
    + +

    + Go to the source code of this file. + + +- ++ + + +- ++ + +- +- ++ ++ + +- +- ++ ++ + +- ++ + +- +- ++ + +- +- ++ ++ + +- +- ++ ++ ++ ++ ++ + + +- ++ + +- +- ++ ++ + + + +- ++ + +- ++ + +- ++ + + +- ++ + + +- ++ + + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- +- ++ ++ + +- +- ++ ++ + +- ++ + +- ++ + +- ++ + +- ++ + +

    Data Structures

    struct  wrapper_priv_data
    struct  wrapper_priv_data

    Linux HC Driver API Functions

    static int urb_enqueue (struct usb_hcd *hcd, struct usb_host_endpoint *ep, struct urb *urb, gfp_t mem_flags)
    int urb_enqueue (struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags)
     Starts processing a USB transfer request specified by a USB Request Block (URB).
    static int urb_dequeue (struct usb_hcd *hcd, struct urb *urb)
     Starts processing a USB transfer request specified by a USB Request Block (URB).
    int urb_dequeue (struct usb_hcd *hcd, struct urb *urb, int status)
     Aborts/cancels a USB transfer request.
    +-static void endpoint_disable (struct usb_hcd *hcd, struct usb_host_endpoint *ep)
     Aborts/cancels a USB transfer request.
    ++void endpoint_disable (struct usb_hcd *hcd, struct usb_host_endpoint *ep)
    static irqreturn_t dwc_otg_hcd_irq (struct usb_hcd *hcd)
    ++void endpoint_reset (struct usb_hcd *hcd, struct usb_host_endpoint *ep)
     Handles host mode interrupts for the DWC_otg controller.
    int hcd_start (struct usb_hcd *hcd)
    irqreturn_t dwc_otg_hcd_irq (struct usb_hcd *hcd)
     Initializes the DWC_otg controller and its root hub and prepares it for host mode operation.
    void hcd_stop (struct usb_hcd *hcd)
     Handles host mode interrupts for the DWC_otg controller.
    int hcd_start (struct usb_hcd *hcd)
     Halts the DWC_otg host mode operations in a clean manner.
    +-static int get_frame_number (struct usb_hcd *hcd)
     Initializes the DWC_otg controller and its root hub and prepares it for host mode operation.
    void hcd_stop (struct usb_hcd *hcd)
     Halts the DWC_otg host mode operations in a clean manner.
    ++int get_frame_number (struct usb_hcd *hcd)
     Returns the current frame number.
    int hub_status_data (struct usb_hcd *hcd, char *buf)
    int hub_status_data (struct usb_hcd *hcd, char *buf)
     Creates Status Change bitmap for the root hub and root port.
    +-int hub_control (struct usb_hcd *hcd, u16 typeReq, u16 wValue, u16 wIndex, char *buf, u16 wLength)
     Creates Status Change bitmap for the root hub and root port.
    ++int hub_control (struct usb_hcd *hcd, u16 typeReq, u16 wValue, u16 wIndex, char *buf, u16 wLength)
     Handles hub class-specific requests.

    Defines

    #define dwc_ep_addr_to_endpoint(_bEndpointAddress_)
    #define dwc_ep_addr_to_endpoint(_bEndpointAddress_)
     Gets the endpoint number from a _bEndpointAddress argument.
     Gets the endpoint number from a _bEndpointAddress argument.

    Functions

    +-static dwc_otg_hcd_t * hcd_to_dwc_otg_hcd (struct usb_hcd *hcd)
    ++dwc_otg_hcd_t * hcd_to_dwc_otg_hcd (struct usb_hcd *hcd)
     Gets the dwc_otg_hcd from a struct usb_hcd.
    +-static struct usb_hcd * dwc_otg_hcd_to_hcd (dwc_otg_hcd_t *dwc_otg_hcd)
    ++usb_hcd * dwc_otg_hcd_to_hcd (dwc_otg_hcd_t *dwc_otg_hcd)
     Gets the struct usb_hcd that contains a dwc_otg_hcd_t.
    +-usb_host_endpoint * dwc_urb_to_endpoint (struct urb *urb)
    ++usb_host_endpoint * dwc_urb_to_endpoint (struct urb *urb)
     Gets the usb_host_endpoint associated with an URB.
    +-static int _disconnect (dwc_otg_hcd_t *hcd)
    ++int _disconnect (dwc_otg_hcd_t *hcd)
    +-static int _start (dwc_otg_hcd_t *hcd)
    ++int _start (dwc_otg_hcd_t *hcd)
    +-static int _hub_info (dwc_otg_hcd_t *hcd, void *urb_handle, uint32_t *hub_addr, uint32_t *port_addr)
    ++int _hub_info (dwc_otg_hcd_t *hcd, void *urb_handle, uint32_t *hub_addr, uint32_t *port_addr)
    +-static int _speed (dwc_otg_hcd_t *hcd, void *urb_handle)
    ++int _speed (dwc_otg_hcd_t *hcd, void *urb_handle)
    +-static int _get_b_hnp_enable (dwc_otg_hcd_t *hcd)
    ++int _get_b_hnp_enable (dwc_otg_hcd_t *hcd)
    +-static void allocate_bus_bandwidth (struct usb_hcd *hcd, uint32_t bw, struct urb *urb)
    ++void allocate_bus_bandwidth (struct usb_hcd *hcd, uint32_t bw, struct urb *urb)
    +-static void free_bus_bandwidth (struct usb_hcd *hcd, uint32_t bw, struct urb *urb)
    ++void free_bus_bandwidth (struct usb_hcd *hcd, uint32_t bw, struct urb *urb)
    static int _complete (dwc_otg_hcd_t *hcd, void *urb_handle, dwc_otg_hcd_urb_t *dwc_otg_urb, int32_t status)
    int _complete (dwc_otg_hcd_t *hcd, void *urb_handle, dwc_otg_hcd_urb_t *dwc_otg_urb, int32_t status)
     Sets the final status of an URB and returns it to the device driver.
    int hcd_init ()
     Sets the final status of an URB and returns it to the device driver.
    int hcd_init ()
     Initializes the HCD.
    void hcd_remove ()
     Initializes the HCD.
    void hcd_remove ()
     Removes the HCD.
     Removes the HCD.

    Variables

    +-static const char dwc_otg_hcd_name [] = "dwc_otg_hcd"
    ++const char dwc_otg_hcd_name [] = "dwc_otg_hcd"
    static struct hc_driver dwc_otg_hc_driver
    hc_driver dwc_otg_hc_driver
    static struct dwc_otg_hcd_function_ops hcd_fops
    dwc_otg_hcd_function_ops hcd_fops
    +

    Detailed Description

    + This file contains the implementation of the HCD. +

    +-In Linux, the HCD implements the hc_driver API. ++In Linux, the HCD implements the hc_driver API. +

    + Definition in file dwc_otg_hcd_linux.c.

    Define Documentation

    +- +-
    +-
    +- +- +- +- +- +- +- +- ++

    ++

    #define dwc_ep_addr_to_endpoint (_bEndpointAddress_   ) 
    ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ + +
    #define dwc_ep_addr_to_endpoint ( _bEndpointAddress_   ) 
    +- +-
    ++
    ++ ++ ++ ++ ++ ++
    ++   ++ + +

    + Value:

    ((_bEndpointAddress_ & USB_ENDPOINT_NUMBER_MASK) | \
+@@ -158,103 +158,127 @@
+ 
    
+ The endpoint is qualified with its direction (possible 32 endpoints per device). 
+ 
    
+-Definition at line 71 of file dwc_otg_hcd_linux.c.
+-
    +-

    ++Definition at line 68 of file dwc_otg_hcd_linux.c.

    +

    Function Documentation

    +- +-
    +-
    +- +- +- +- +- +- +- ++

    ++

    static int urb_enqueue (struct usb_hcd *  hcd,
    ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    struct usb_host_endpoint *  ep, int urb_enqueue ( struct usb_hcd *  hcd,
    struct urb *  urb, struct urb *  urb,
    gfp_t  mem_flags gfp_t  mem_flags
    ) [static])  [static]
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Starts processing a USB transfer request specified by a USB Request Block (URB). +

    + mem_flags indicates the type of memory allocation to use while processing this URB. +

    +-Definition at line 562 of file dwc_otg_hcd_linux.c. +- +-

    +- +-

    +-
    +- ++Definition at line 586 of file dwc_otg_hcd_linux.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ ++ ++ ++ ++ ++ ++ + +
    static int urb_dequeue (struct usb_hcd *  hcd, int urb_dequeue ( struct usb_hcd *  hcd,
    struct urb *  urb struct urb *  urb,
    ) [static]int  status
    )  [static]
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Aborts/cancels a USB transfer request. +

    + Always returns 0 to indicate success. +

    +-Definition at line 667 of file dwc_otg_hcd_linux.c. +- +-

    +- +-

    +-
    +- +- +- +- +- +- +- +- ++Definition at line 698 of file dwc_otg_hcd_linux.c. ++ ++
    static irqreturn_t dwc_otg_hcd_irq (struct usb_hcd *  hcd  )  [static]
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ + +
    irqreturn_t dwc_otg_hcd_irq ( struct usb_hcd *  hcd  )  [static]
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Handles host mode interrupts for the DWC_otg controller. +@@ -262,253 +286,319 @@ + Returns IRQ_NONE if there was no interrupt to handle. Returns IRQ_HANDLED if there was a valid interrupt.

    + This function is called by the USB core when an interrupt occurs +

    +-Definition at line 714 of file dwc_otg_hcd_linux.c. +- +-

    +- +-

    +-
    +- +- +- +- +- +- +- +- ++Definition at line 791 of file dwc_otg_hcd_linux.c. ++ ++
    int hcd_start (struct usb_hcd *  hcd  ) 
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ + +
    int hcd_start ( struct usb_hcd *  hcd  ) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Initializes the DWC_otg controller and its root hub and prepares it for host mode operation. +

    + Activates the root port. Returns 0 on success and a negative error code on failure. +

    +-Definition at line 469 of file dwc_otg_hcd_linux.c. +- +-

    +- +-

    +-
    +- +- +- +- +- +- +- +- ++Definition at line 493 of file dwc_otg_hcd_linux.c. ++ ++
    void hcd_stop (struct usb_hcd *  hcd  ) 
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ + +
    void hcd_stop ( struct usb_hcd *  hcd  ) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Halts the DWC_otg host mode operations in a clean manner. +

    + USB transfers are stopped. +

    +-Definition at line 496 of file dwc_otg_hcd_linux.c. +- +-

    +- +-

    +-
    +- ++Definition at line 520 of file dwc_otg_hcd_linux.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    int hub_status_data (struct usb_hcd *  hcd, int hub_status_data ( struct usb_hcd *  hcd,
    char *  buf char *  buf
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Creates Status Change bitmap for the root hub and root port. +

    + The bitmap is returned in buf. Bit 0 is the status change indicator for the root hub. Bit 1 is the status change indicator for the single root port. Returns 1 if either change indicator is 1, otherwise returns 0. +

    +-Definition at line 728 of file dwc_otg_hcd_linux.c. +- +-

    +- +-

    +-
    +- ++Definition at line 805 of file dwc_otg_hcd_linux.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    static int _complete (dwc_otg_hcd_t *  hcd, int _complete ( dwc_otg_hcd_t *  hcd,
    void *  urb_handle, void *  urb_handle,
    dwc_otg_hcd_urb_t *  dwc_otg_urb, dwc_otg_hcd_urb_t *  dwc_otg_urb,
    int32_t  status int32_t  status
    ) [static])  [static]
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Sets the final status of an URB and returns it to the device driver. +

    + Any required cleanup of the URB is performed. +

    +-Definition at line 224 of file dwc_otg_hcd_linux.c. +- +-

    +- +-

    +-
    +- +- +- +- +- +- +- ++Definition at line 230 of file dwc_otg_hcd_linux.c. ++ ++
    int hcd_init (  ) 
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ + +
    int hcd_init (   ) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Initializes the HCD. +

    + This function allocates memory for and initializes the static parts of the usb_hcd and dwc_otg_hcd structures. It also registers the USB bus with the core and calls the hc_driver->start() function. It returns a negative error on failure. +

    +-Definition at line 327 of file dwc_otg_hcd_linux.c. +- +-

    +- +-

    +-
    +- +- +- +- +- +- +- ++Definition at line 339 of file dwc_otg_hcd_linux.c. ++ ++
    void hcd_remove (  ) 
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ + +
    void hcd_remove (   ) 
    +- +-
    ++
    ++ ++ ++ ++ ++ ++
    ++   ++ + +

    + Removes the HCD. +

    + Frees memory and resources associated with the HCD and deregisters the bus. +

    +-Definition at line 417 of file dwc_otg_hcd_linux.c. +- +-

    ++Definition at line 441 of file dwc_otg_hcd_linux.c.

    +

    Variable Documentation

    +- +-
    +-
    +- ++

    ++

    ++ ++ ++ ++
    ++ + +- ++ + +
    struct hc_driver dwc_otg_hc_driver [static] struct hc_driver dwc_otg_hc_driver [static]
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Initial value:

     {
+ 
+-        .description = dwc_otg_hcd_name,
++        .description = dwc_otg_hcd_name,
+         .product_desc = "DWC OTG Controller",
+-        .hcd_priv_size = sizeof(struct wrapper_priv_data),
++        .hcd_priv_size = sizeof(struct wrapper_priv_data),
+ 
+-        .irq = dwc_otg_hcd_irq,
++        .irq = dwc_otg_hcd_irq,
+ 
+         .flags = HCD_MEMORY | HCD_USB2,
+ 
+         
+-        .start = hcd_start,
++        .start = hcd_start,
+         
+         
+-        .stop = hcd_stop,
++        .stop = hcd_stop,
++
++        .urb_enqueue = urb_enqueue,
++        .urb_dequeue = urb_dequeue,
++        .endpoint_disable = endpoint_disable,
+ 
+-        .urb_enqueue = urb_enqueue,
+-        .urb_dequeue = urb_dequeue,
+-        .endpoint_disable = endpoint_disable,
++        .endpoint_reset = endpoint_reset,
+ 
+-        .get_frame_number = get_frame_number,
++        .get_frame_number = get_frame_number,
+ 
+-        .hub_status_data = hub_status_data,
+-        .hub_control = hub_control,
++        .hub_status_data = hub_status_data,
++        .hub_control = hub_control,
+         
+         
+ }
+
    +

    +-Definition at line 101 of file dwc_otg_hcd_linux.c. +- +-

    +- +-

    +-
    +- ++Definition at line 105 of file dwc_otg_hcd_linux.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- ++ + +
    struct dwc_otg_hcd_function_ops hcd_fops [static] struct dwc_otg_hcd_function_ops hcd_fops [static]
    +- +-
    ++
    ++ ++ ++ ++ ++ ++
    ++   ++ + +

    + Initial value:

     {
+-        .start = _start,
+-        .disconnect = _disconnect,
+-        .hub_info = _hub_info,
+-        .speed = _speed,
+-        .complete = _complete,
+-        .get_b_hnp_enable = _get_b_hnp_enable,
++        .start = _start,
++        .disconnect = _disconnect,
++        .hub_info = _hub_info,
++        .speed = _speed,
++        .complete = _complete,
++        .get_b_hnp_enable = _get_b_hnp_enable,
+ }
+
    +

    +-Definition at line 312 of file dwc_otg_hcd_linux.c. +- +-

    +-

    Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++Definition at line 324 of file dwc_otg_hcd_linux.c.
    ++

    Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
    ++doxygen 1.3.9.1 + + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__hcd__queue_8c-source.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/dwc__otg__hcd__queue_8c-source.html 2013-07-26 19:31:21.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__hcd__queue_8c-source.html 2013-07-26 19:34:41.000000000 +0000 +@@ -2,632 +2,611 @@ + + DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_hcd_queue.c Source File + +- + +- +-
    +-
    +-
    +-
    +-

    dwc_otg_hcd_queue.c

    Go to the documentation of this file.
    00001 /* ==========================================================================
+-00002  * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd_queue.c $
+-00003  * $Revision: #39 $
+-00004  * $Date: 2009/04/21 $
+-00005  * $Change: 1237477 $
+-00006  *
+-00007  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
+-00008  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
+-00009  * otherwise expressly agreed to in writing between Synopsys and you.
+-00010  * 
+-00011  * The Software IS NOT an item of Licensed Software or Licensed Product under
+-00012  * any End User Software License Agreement or Agreement for Licensed Product
+-00013  * with Synopsys or any supplement thereto. You are permitted to use and
+-00014  * redistribute this Software in source and binary forms, with or without
+-00015  * modification, provided that redistributions of source code must retain this
+-00016  * notice. You may not view, use, disclose, copy or distribute this file or
+-00017  * any information contained herein except pursuant to this license grant from
+-00018  * Synopsys. If you do not agree with this notice, including the disclaimer
+-00019  * below, then you are not authorized to use the Software.
+-00020  * 
+-00021  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
+-00022  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+-00023  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+-00024  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
+-00025  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+-00026  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+-00027  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+-00028  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+-00029  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+-00030  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+-00031  * DAMAGE.
+-00032  * ========================================================================== */
+-00033 #ifndef DWC_DEVICE_ONLY
+-00034 
+-00042 #include "dwc_otg_hcd.h"
+-00043 #include "dwc_otg_regs.h"
+-00044 
+-00053 void dwc_otg_hcd_qh_free(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
+-00054 {
+-00055         dwc_otg_qtd_t *qtd, *qtd_tmp;
+-00056         uint64_t flags;
+-00057 
+-00058         /* Free each QTD in the QTD list */
+-00059         DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
+-00060         DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp, &qh->qtd_list, qtd_list_entry) {
+-00061                 DWC_CIRCLEQ_REMOVE(&qh->qtd_list, qtd, qtd_list_entry);
+-00062                 dwc_otg_hcd_qtd_free(qtd);
+-00063         }
+-00064         DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
+-00065 
+-00066         if (hcd->core_if->dma_desc_enable) {
+-00067                 dwc_otg_hcd_qh_free_ddma(hcd, qh);
+-00068         }
+-00069         else if (qh->dw_align_buf) {
+-00070                 uint32_t buf_size;
+-00071                 if(qh->ep_type == UE_ISOCHRONOUS) {
+-00072                         buf_size = 4096;
+-00073                 } else {
+-00074                         buf_size = hcd->core_if->core_params->max_transfer_size;
+-00075                 }
+-00076                 dwc_dma_free(buf_size, qh->dw_align_buf, qh->dw_align_buf_dma);
+-00077         }
+-00078         
+-00079         
+-00080         
+-00081         dwc_free(qh);
+-00082         return;
+-00083 }
+-00084 
+-00085 #define BitStuffTime(bytecount)  ((8 * 7* bytecount) / 6)
+-00086 #define HS_HOST_DELAY           5       /* nanoseconds */
+-00087 #define FS_LS_HOST_DELAY        1000    /* nanoseconds */
+-00088 #define HUB_LS_SETUP            333     /* nanoseconds */
+-00089 #define NS_TO_US(ns)            ((ns + 500) / 1000)
+-00090                                 /* convert & round nanoseconds to microseconds */
+-00091 
+-00092 static uint32_t calc_bus_time(int speed, int is_in, int is_isoc,
+-00093                                           int bytecount)
+-00094 {
+-00095         unsigned long retval;
+-00096 
+-00097         switch (speed) {
+-00098         case USB_SPEED_HIGH:
+-00099                 if (is_isoc) {
+-00100                         retval =
+-00101                             ((38 * 8 * 2083) +
+-00102                              (2083 * (3 + BitStuffTime(bytecount)))) / 1000 +
+-00103                             HS_HOST_DELAY;
+-00104                 } else {
+-00105                         retval =
+-00106                             ((55 * 8 * 2083) +
+-00107                              (2083 * (3 + BitStuffTime(bytecount)))) / 1000 +
+-00108                             HS_HOST_DELAY;
+-00109                 }
+-00110                 break;
+-00111         case USB_SPEED_FULL:
+-00112                 if (is_isoc) {
+-00113                         retval =
+-00114                             (8354 * (31 + 10 * BitStuffTime(bytecount))) / 1000;
+-00115                         if (is_in) {
+-00116                                 retval = 7268 + FS_LS_HOST_DELAY + retval;
+-00117                         } else {
+-00118                                 retval = 6265 + FS_LS_HOST_DELAY + retval;
+-00119                         }
+-00120                 } else {
+-00121                         retval =
+-00122                             (8354 * (31 + 10 * BitStuffTime(bytecount))) / 1000;
+-00123                         retval = 9107 + FS_LS_HOST_DELAY + retval;
+-00124                 }
+-00125                 break;
+-00126         case USB_SPEED_LOW:
+-00127                 if (is_in) {
+-00128                         retval =
+-00129                             (67667 * (31 + 10 * BitStuffTime(bytecount))) /
+-00130                             1000;
+-00131                         retval =
+-00132                             64060 + (2 * HUB_LS_SETUP) + FS_LS_HOST_DELAY +
+-00133                             retval;
+-00134                 } else {
+-00135                         retval =
+-00136                             (66700 * (31 + 10 * BitStuffTime(bytecount))) /
+-00137                             1000;
+-00138                         retval =
+-00139                             64107 + (2 * HUB_LS_SETUP) + FS_LS_HOST_DELAY +
+-00140                             retval;
+-00141                 }
+-00142                 break;
+-00143         default:
+-00144                 DWC_WARN("Unknown device speed\n");
+-00145                 retval = -1;
+-00146         }
+-00147         
+-00148         return NS_TO_US(retval);
+-00149 }
+-00150 
+-00159 #define SCHEDULE_SLOP 10
+-00160 void qh_init(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh,
+-00161                          dwc_otg_hcd_urb_t * urb)
+-00162 {
+-00163         char *speed, *type;
+-00164         int dev_speed;
+-00165         uint32_t hub_addr, hub_port;
+-00166 
+-00167         dwc_memset(qh, 0, sizeof(dwc_otg_qh_t));
+-00168         
+-00169         /* Initialize QH */
+-00170         qh->ep_type = dwc_otg_hcd_get_pipe_type(&urb->pipe_info);
+-00171 
+-00172         qh->ep_is_in = dwc_otg_hcd_is_pipe_in(&urb->pipe_info) ? 1 : 0;
+-00173 
+-00174         qh->data_toggle = DWC_OTG_HC_PID_DATA0;
+-00175         qh->maxp = dwc_otg_hcd_get_mps(&urb->pipe_info);
+-00176         DWC_CIRCLEQ_INIT(&qh->qtd_list);
+-00177         DWC_LIST_INIT(&qh->qh_list_entry);
+-00178         qh->channel = NULL;
+-00179 
+-00180         /* FS/LS Enpoint on HS Hub 
+-00181          * NOT virtual root hub */
+-00182         dev_speed = hcd->fops->speed(hcd, urb->priv);
+-00183         hcd->fops->hub_info(hcd, urb->priv, &hub_addr, &hub_port);
+-00184         qh->do_split = 0;
+-00185         if (((dev_speed == USB_SPEED_LOW) ||
+-00186              (dev_speed == USB_SPEED_FULL)) &&
+-00187             (hub_addr != 0 && hub_addr != 1)) {
+-00188                 
+-00189                 DWC_DEBUGPL(DBG_HCD,
+-00190                             "QH init: EP %d: TT found at hub addr %d, for port %d\n",
+-00191                             dwc_otg_hcd_get_ep_num(&urb->pipe_info), hub_addr,
+-00192                             hub_port);
+-00193                 
+-00194                 qh->do_split = 1;
+-00195         }
+-00196 
+-00197         if (qh->ep_type == UE_INTERRUPT || qh->ep_type == UE_ISOCHRONOUS) {
+-00198                 /* Compute scheduling parameters once and save them. */
+-00199                 hprt0_data_t hprt;
+-00200 
+-00202                 int bytecount =
+-00203                     dwc_hb_mult(qh->maxp) * dwc_max_packet(qh->maxp);
+-00204 
+-00205                 qh->usecs = calc_bus_time((qh->do_split ? USB_SPEED_HIGH : dev_speed),
+-00206                                           qh->ep_is_in,
+-00207                                           (qh->ep_type == UE_ISOCHRONOUS),
+-00208                                           bytecount);
+-00209                 /* Start in a slightly future (micro)frame. */
+-00210                 qh->sched_frame = dwc_frame_num_inc(hcd->frame_number,
+-00211                                                     SCHEDULE_SLOP);
+-00212                 qh->interval = urb->interval;
+-00213                 
+-00214 #if 0
+-00215                 /* Increase interrupt polling rate for debugging. */
+-00216                 if (qh->ep_type == UE_INTERRUPT) {
+-00217                         qh->interval = 8;
+-00218                 }
+-00219 #endif
+-00220                 hprt.d32 = dwc_read_reg32(hcd->core_if->host_if->hprt0);
+-00221                 if ((hprt.b.prtspd == DWC_HPRT0_PRTSPD_HIGH_SPEED) &&
+-00222                     ((dev_speed == USB_SPEED_LOW) ||
+-00223                      (dev_speed == USB_SPEED_FULL))) {
+-00224                         qh->interval *= 8;
+-00225                         qh->sched_frame |= 0x7;
+-00226                         qh->start_split_frame = qh->sched_frame;
+-00227                 }
+-00228 
+-00229         }
+-00230 
+-00231         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD QH Initialized\n");
+-00232         DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH  - qh = %p\n", qh);
+-00233         DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH  - Device Address = %d\n",
+-00234                     dwc_otg_hcd_get_dev_addr(&urb->pipe_info));
+-00235         DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH  - Endpoint %d, %s\n",
+-00236                     dwc_otg_hcd_get_ep_num(&urb->pipe_info),
+-00237                     dwc_otg_hcd_is_pipe_in(&urb->pipe_info) ? "IN" : "OUT");
+-00238         switch (dev_speed) {
+-00239         case USB_SPEED_LOW:
+-00240                 qh->dev_speed = DWC_OTG_EP_SPEED_LOW;
+-00241                 speed = "low";
+-00242                 break;
+-00243         case USB_SPEED_FULL:
+-00244                 qh->dev_speed = DWC_OTG_EP_SPEED_FULL;
+-00245                 speed = "full";
+-00246                 break;
+-00247         case USB_SPEED_HIGH:
+-00248                 qh->dev_speed = DWC_OTG_EP_SPEED_HIGH;
+-00249                 speed = "high";
+-00250                 break;
+-00251         default:
+-00252                 speed = "?";
+-00253                 break;
+-00254         }
+-00255         DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH  - Speed = %s\n", speed);
+-00256 
+-00257         switch (qh->ep_type) {
+-00258         case UE_ISOCHRONOUS:
+-00259                 type = "isochronous";
+-00260                 break;
+-00261         case UE_INTERRUPT:
+-00262                 type = "interrupt";
+-00263                 break;
+-00264         case UE_CONTROL:
+-00265                 type = "control";
+-00266                 break;
+-00267         case UE_BULK:
+-00268                 type = "bulk";
+-00269                 break;
+-00270         default:
+-00271                 type = "?";
+-00272                 break;
+-00273         }
+-00274         
+-00275         DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH  - Type = %s\n", type);
+-00276 
+-00277 #ifdef DEBUG
+-00278         if (qh->ep_type == UE_INTERRUPT) {
+-00279                 DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - usecs = %d\n",
+-00280                             qh->usecs);
+-00281                 DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - interval = %d\n",
+-00282                             qh->interval);
+-00283         }
+-00284 #endif
+-00285 
+-00286 }
+-00287 
+-00296 dwc_otg_qh_t *dwc_otg_hcd_qh_create(dwc_otg_hcd_t * hcd,
+-00297                                     dwc_otg_hcd_urb_t * urb)
+-00298 {
+-00299         dwc_otg_qh_t *qh;
+-00300 
+-00301         /* Allocate memory */
+-00303         qh = dwc_otg_hcd_qh_alloc();
+-00304         if (qh == NULL) {
+-00305                 return NULL;
+-00306         }
+-00307 
+-00308         qh_init(hcd, qh, urb);
+-00309         
+-00310         if (hcd->core_if->dma_desc_enable && (dwc_otg_hcd_qh_init_ddma(hcd, qh) < 0)) {
+-00311                 dwc_otg_hcd_qh_free(hcd, qh);   
+-00312                 return NULL;
+-00313         }
+-00314         
+-00315         return qh;
+-00316 }
+-00317 
+-00323 static int periodic_channel_available(dwc_otg_hcd_t * hcd)
+-00324 {
+-00325         /*
+-00326          * Currently assuming that there is a dedicated host channnel for each
+-00327          * periodic transaction plus at least one host channel for
+-00328          * non-periodic transactions.
+-00329          */
+-00330         int status;
+-00331         int num_channels;
+-00332 
+-00333         num_channels = hcd->core_if->core_params->host_channels;
+-00334         if ((hcd->periodic_channels + hcd->non_periodic_channels < num_channels) &&
+-00335             (hcd->periodic_channels < num_channels - 1)) {
+-00336                 status = 0;
+-00337         } else {
+-00338                 DWC_INFO("%s: Total channels: %d, Periodic: %d, Non-periodic: %d\n",
+-00339                         __func__, num_channels, hcd->periodic_channels, hcd->non_periodic_channels);    //NOTICE
+-00340                 status = -DWC_E_NO_SPACE;
+-00341         }
+-00342 
+-00343         return status;
+-00344 }
+-00345 
+-00356 static int check_periodic_bandwidth(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
+-00357 {
+-00358         int status;
+-00359         int16_t max_claimed_usecs;
+-00360 
+-00361         status = 0;
+-00362 
+-00363         if ((qh->dev_speed == DWC_OTG_EP_SPEED_HIGH) || qh->do_split) {
+-00364                 /*
+-00365                  * High speed mode.
+-00366                  * Max periodic usecs is 80% x 125 usec = 100 usec.
+-00367                  */
+-00368 
+-00369                 max_claimed_usecs = 100 - qh->usecs;
+-00370         } else {
+-00371                 /*
+-00372                  * Full speed mode.
+-00373                  * Max periodic usecs is 90% x 1000 usec = 900 usec.
+-00374                  */
+-00375                 max_claimed_usecs = 900 - qh->usecs;
+-00376         }
+-00377 
+-00378         if (hcd->periodic_usecs > max_claimed_usecs) {
+-00379                 DWC_INFO("%s: already claimed usecs %d, required usecs %d\n", __func__, hcd->periodic_usecs, qh->usecs);        //NOTICE
+-00380                 status = -DWC_E_NO_SPACE;
+-00381         }
+-00382 
+-00383         return status;
+-00384 }
+-00385 
+-00396 static int check_max_xfer_size(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
+-00397 {
+-00398         int status;
+-00399         uint32_t max_xfer_size;
+-00400         uint32_t max_channel_xfer_size;
+-00401 
+-00402         status = 0;
+-00403 
+-00404         max_xfer_size = dwc_max_packet(qh->maxp) * dwc_hb_mult(qh->maxp);
+-00405         max_channel_xfer_size = hcd->core_if->core_params->max_transfer_size;
+-00406 
+-00407         if (max_xfer_size > max_channel_xfer_size) {
+-00408                 DWC_INFO("%s: Periodic xfer length %d > " "max xfer length for channel %d\n",
+-00409                                 __func__, max_xfer_size, max_channel_xfer_size);        //NOTICE
+-00410                 status = -DWC_E_NO_SPACE;
+-00411         }
+-00412 
+-00413         return status;
+-00414 }
+-00415 
+-00425 static int schedule_periodic(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
+-00426 {
+-00427         int status = 0;
+-00428 
+-00429         status = periodic_channel_available(hcd);
+-00430         if (status) {
+-00431                 DWC_INFO("%s: No host channel available for periodic " "transfer.\n", __func__);        //NOTICE
+-00432                 return status;
+-00433         }
+-00434 
+-00435         status = check_periodic_bandwidth(hcd, qh);
+-00436         if (status) {
+-00437                 DWC_INFO("%s: Insufficient periodic bandwidth for " "periodic transfer.\n", __func__);  //NOTICE
+-00438                 return status;
+-00439         }
+-00440 
+-00441         status = check_max_xfer_size(hcd, qh);
+-00442         if (status) {
+-00443                 DWC_INFO("%s: Channel max transfer size too small " "for periodic transfer.\n", __func__);      //NOTICE
+-00444                 return status;
+-00445         }
+-00446 
+-00447         if (hcd->core_if->dma_desc_enable) {
+-00448                 /* Don't rely on SOF and start in ready schedule */
+-00449                 DWC_LIST_INSERT_TAIL(&hcd->periodic_sched_ready, &qh->qh_list_entry);
+-00450         }
+-00451         else {
+-00452         /* Always start in the inactive schedule. */
+-00453         DWC_LIST_INSERT_TAIL(&hcd->periodic_sched_inactive, &qh->qh_list_entry);
+-00454         }
+-00455 
+-00456         /* Reserve the periodic channel. */
+-00457         hcd->periodic_channels++;
+-00458 
+-00459         /* Update claimed usecs per (micro)frame. */
+-00460         hcd->periodic_usecs += qh->usecs;
+-00461 
+-00462         return status;
+-00463 }
+-00464 
+-00472 int dwc_otg_hcd_qh_add(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
+-00473 {
+-00474         int status = 0;
+-00475         uint64_t flags;
+-00476 
+-00477         DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
+-00478 
+-00479         if (!DWC_LIST_EMPTY(&qh->qh_list_entry)) {
+-00480                 /* QH already in a schedule. */
+-00481                 goto done;
+-00482         }
+-00483 
+-00484         /* Add the new QH to the appropriate schedule */
+-00485         if (dwc_qh_is_non_per(qh)) {
+-00486                 /* Always start in the inactive schedule. */
+-00487                 DWC_LIST_INSERT_TAIL(&hcd->non_periodic_sched_inactive,
+-00488                                      &qh->qh_list_entry);
+-00489         } else {
+-00490                 status = schedule_periodic(hcd, qh);
+-00491         }
+-00492 
+-00493       done:
+-00494         DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
+-00495 
+-00496         return status;
+-00497 }
+-00498 
+-00505 static void deschedule_periodic(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
+-00506 {
+-00507         DWC_LIST_REMOVE_INIT(&qh->qh_list_entry);
+-00508 
+-00509         /* Release the periodic channel reservation. */
+-00510         hcd->periodic_channels--;
+-00511 
+-00512         /* Update claimed usecs per (micro)frame. */
+-00513         hcd->periodic_usecs -= qh->usecs;
+-00514 }
+-00515 
+-00522 void dwc_otg_hcd_qh_remove(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
+-00523 {
+-00524         uint64_t flags;
+-00525         DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
+-00526 
+-00527         if (DWC_LIST_EMPTY(&qh->qh_list_entry)) {
+-00528                 /* QH is not in a schedule. */
+-00529                 goto done;
+-00530         }
+-00531 
+-00532         if (dwc_qh_is_non_per(qh)) {
+-00533                 if (hcd->non_periodic_qh_ptr == &qh->qh_list_entry) {
+-00534                         hcd->non_periodic_qh_ptr =
+-00535                             hcd->non_periodic_qh_ptr->next;
+-00536                 }
+-00537                 DWC_LIST_REMOVE_INIT(&qh->qh_list_entry);
+-00538         } else {
+-00539                 deschedule_periodic(hcd, qh);
+-00540         }
+-00541 
+-00542       done:
+-00543         DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
+-00544 }
+-00545 
+-00559 void dwc_otg_hcd_qh_deactivate(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh,
+-00560                                int sched_next_periodic_split)
+-00561 {
+-00562         uint64_t flags;
+-00563         DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
+-00564 
+-00565         if (dwc_qh_is_non_per(qh)) {
+-00566                 dwc_otg_hcd_qh_remove(hcd, qh);
+-00567                 if (!DWC_CIRCLEQ_EMPTY(&qh->qtd_list)) {
+-00568                         /* Add back to inactive non-periodic schedule. */
+-00569                         dwc_otg_hcd_qh_add(hcd, qh);
+-00570                 }
+-00571         } else {
+-00572                 uint16_t frame_number = dwc_otg_hcd_get_frame_number(hcd);
+-00573 
+-00574                 if (qh->do_split) {
+-00575                         /* Schedule the next continuing periodic split transfer */
+-00576                         if (sched_next_periodic_split) {
+-00577 
+-00578                                 qh->sched_frame = frame_number;
+-00579                                 if (dwc_frame_num_le(frame_number,
+-00580                                                      dwc_frame_num_inc(qh->
+-00581                                                                        start_split_frame,
+-00582                                                                        1))) {
+-00583                                         /*
+-00584                                          * Allow one frame to elapse after start
+-00585                                          * split microframe before scheduling
+-00586                                          * complete split, but DONT if we are
+-00587                                          * doing the next start split in the
+-00588                                          * same frame for an ISOC out.
+-00589                                          */
+-00590                                         if ((qh->ep_type != UE_ISOCHRONOUS) ||
+-00591                                             (qh->ep_is_in != 0)) {
+-00592                                                 qh->sched_frame =
+-00593                                                     dwc_frame_num_inc(qh->sched_frame, 1);
+-00594                                         }
+-00595                                 }
+-00596                         } else {
+-00597                                 qh->sched_frame =
+-00598                                     dwc_frame_num_inc(qh->start_split_frame,
+-00599                                                       qh->interval);
+-00600                                 if (dwc_frame_num_le
+-00601                                     (qh->sched_frame, frame_number)) {
+-00602                                         qh->sched_frame = frame_number;
+-00603                                 }
+-00604                                 qh->sched_frame |= 0x7;
+-00605                                 qh->start_split_frame = qh->sched_frame;
+-00606                         }
+-00607                 } else {
+-00608                         qh->sched_frame =
+-00609                             dwc_frame_num_inc(qh->sched_frame, qh->interval);
+-00610                         if (dwc_frame_num_le(qh->sched_frame, frame_number)) {
+-00611                                 qh->sched_frame = frame_number;
+-00612                         }
+-00613                 }
+-00614 
+-00615                 if (DWC_CIRCLEQ_EMPTY(&qh->qtd_list)) {
+-00616                         dwc_otg_hcd_qh_remove(hcd, qh);
+-00617                 } else {
+-00618                         /*
+-00619                          * Remove from periodic_sched_queued and move to
+-00620                          * appropriate queue.
+-00621                          */
+-00622                         if (qh->sched_frame == frame_number) {
+-00623                                 DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_ready,
+-00624                                                    &qh->qh_list_entry);
+-00625                         } else {
+-00626                                 DWC_LIST_MOVE_HEAD(&hcd->
+-00627                                                    periodic_sched_inactive,
+-00628                                                    &qh->qh_list_entry);
+-00629                         }
+-00630                 }
+-00631         }
+-00632 
+-00633         DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
+-00634 }
+-00635 
+-00643 dwc_otg_qtd_t *dwc_otg_hcd_qtd_create(dwc_otg_hcd_urb_t * urb)
+-00644 {
+-00645         dwc_otg_qtd_t *qtd;
+-00646 
+-00647         qtd = dwc_otg_hcd_qtd_alloc();
+-00648         if (qtd == NULL) {
+-00649                 return NULL;
+-00650         }
+-00651 
+-00652         dwc_otg_hcd_qtd_init(qtd, urb);
+-00653         return qtd;
+-00654 }
+-00655 
+-00661 void dwc_otg_hcd_qtd_init(dwc_otg_qtd_t * qtd, dwc_otg_hcd_urb_t * urb)
+-00662 {
+-00663         dwc_memset(qtd, 0, sizeof(dwc_otg_qtd_t));
+-00664         qtd->urb = urb;
+-00665         if (dwc_otg_hcd_get_pipe_type(&urb->pipe_info) == UE_CONTROL) {
+-00666                 /*
+-00667                  * The only time the QTD data toggle is used is on the data
+-00668                  * phase of control transfers. This phase always starts with
+-00669                  * DATA1.
+-00670                  */
+-00671                 qtd->data_toggle = DWC_OTG_HC_PID_DATA1;
+-00672                 qtd->control_phase = DWC_OTG_CONTROL_SETUP;
+-00673         }
+-00674 
+-00675         /* start split */
+-00676         qtd->complete_split = 0;
+-00677         qtd->isoc_split_pos = DWC_HCSPLIT_XACTPOS_ALL;
+-00678         qtd->isoc_split_offset = 0;
+-00679         qtd->in_process = 0;
+-00680 
+-00681         /* Store the qtd ptr in the urb to reference what QTD. */
+-00682         urb->qtd = qtd;
+-00683         return;
+-00684 }
+-00685 
+-00698 int dwc_otg_hcd_qtd_add(dwc_otg_qtd_t * qtd,
+-00699                         dwc_otg_hcd_t * hcd, dwc_otg_qh_t ** qh)
+-00700 {
+-00701         int retval = 0;
+-00702         uint64_t flags;
+-00703 
+-00704         dwc_otg_hcd_urb_t *urb = qtd->urb;
+-00705 
+-00706         DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
+-00707 
+-00708         /*
+-00709          * Get the QH which holds the QTD-list to insert to. Create QH if it
+-00710          * doesn't exist.
+-00711          */
+-00712         if (*qh == NULL) {
+-00713                 *qh = dwc_otg_hcd_qh_create(hcd, urb);
+-00714                 if (*qh == NULL) {
+-00715                         retval = -1;
+-00716                         goto done;
+-00717                 }
+-00718         }
+-00719 
+-00720         retval = dwc_otg_hcd_qh_add(hcd, *qh);
+-00721         if (retval == 0) {
+-00722                 DWC_CIRCLEQ_INSERT_TAIL(&((*qh)->qtd_list), qtd,
+-00723                                         qtd_list_entry);
+-00724         }
+-00725 
+-00726       done:
+-00727         DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
+-00728 
+-00729         return retval;
+-00730 }
+-00731 
+-00732 #endif                          /* DWC_DEVICE_ONLY */
+-
    Generated on Tue May 5 02:22:48 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++
    Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
    ++

    dwc_otg_hcd_queue.c

    Go to the documentation of this file.
    00001 /* ==========================================================================
++00002  * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd_queue.c $
++00003  * $Revision: #44 $
++00004  * $Date: 2011/10/26 $
++00005  * $Change: 1873028 $
++00006  *
++00007  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
++00008  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
++00009  * otherwise expressly agreed to in writing between Synopsys and you.
++00010  * 
++00011  * The Software IS NOT an item of Licensed Software or Licensed Product under
++00012  * any End User Software License Agreement or Agreement for Licensed Product
++00013  * with Synopsys or any supplement thereto. You are permitted to use and
++00014  * redistribute this Software in source and binary forms, with or without
++00015  * modification, provided that redistributions of source code must retain this
++00016  * notice. You may not view, use, disclose, copy or distribute this file or
++00017  * any information contained herein except pursuant to this license grant from
++00018  * Synopsys. If you do not agree with this notice, including the disclaimer
++00019  * below, then you are not authorized to use the Software.
++00020  * 
++00021  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
++00022  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++00023  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++00024  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
++00025  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++00026  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
++00027  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
++00028  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
++00029  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
++00030  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
++00031  * DAMAGE.
++00032  * ========================================================================== */
++00033 #ifndef DWC_DEVICE_ONLY
++00034 
++00042 #include "dwc_otg_hcd.h"
++00043 #include "dwc_otg_regs.h"
++00044 
++00053 void dwc_otg_hcd_qh_free(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
++00054 {
++00055         dwc_otg_qtd_t *qtd, *qtd_tmp;
++00056 
++00057         /* Free each QTD in the QTD list */
++00058         DWC_SPINLOCK(hcd->lock);
++00059         DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp, &qh->qtd_list, qtd_list_entry) {
++00060                 DWC_CIRCLEQ_REMOVE(&qh->qtd_list, qtd, qtd_list_entry);
++00061                 dwc_otg_hcd_qtd_free(qtd);
++00062         }
++00063 
++00064         if (hcd->core_if->dma_desc_enable) {
++00065                 dwc_otg_hcd_qh_free_ddma(hcd, qh);
++00066         } else if (qh->dw_align_buf) {
++00067                 uint32_t buf_size;
++00068                 if (qh->ep_type == UE_ISOCHRONOUS) {
++00069                         buf_size = 4096;
++00070                 } else {
++00071                         buf_size = hcd->core_if->core_params->max_transfer_size;
++00072                 }
++00073                 DWC_DMA_FREE(buf_size, qh->dw_align_buf, qh->dw_align_buf_dma);
++00074         }
++00075 
++00076         DWC_FREE(qh);
++00077         DWC_SPINUNLOCK(hcd->lock);
++00078         return;
++00079 }
++00080 
++00081 #define BitStuffTime(bytecount)  ((8 * 7* bytecount) / 6)
++00082 #define HS_HOST_DELAY           5       /* nanoseconds */
++00083 #define FS_LS_HOST_DELAY        1000    /* nanoseconds */
++00084 #define HUB_LS_SETUP            333     /* nanoseconds */
++00085 #define NS_TO_US(ns)            ((ns + 500) / 1000)
++00086                                 /* convert & round nanoseconds to microseconds */
++00087 
++00088 static uint32_t calc_bus_time(int speed, int is_in, int is_isoc, int bytecount)
++00089 {
++00090         unsigned long retval;
++00091 
++00092         switch (speed) {
++00093         case USB_SPEED_HIGH:
++00094                 if (is_isoc) {
++00095                         retval =
++00096                             ((38 * 8 * 2083) +
++00097                              (2083 * (3 + BitStuffTime(bytecount)))) / 1000 +
++00098                             HS_HOST_DELAY;
++00099                 } else {
++00100                         retval =
++00101                             ((55 * 8 * 2083) +
++00102                              (2083 * (3 + BitStuffTime(bytecount)))) / 1000 +
++00103                             HS_HOST_DELAY;
++00104                 }
++00105                 break;
++00106         case USB_SPEED_FULL:
++00107                 if (is_isoc) {
++00108                         retval =
++00109                             (8354 * (31 + 10 * BitStuffTime(bytecount))) / 1000;
++00110                         if (is_in) {
++00111                                 retval = 7268 + FS_LS_HOST_DELAY + retval;
++00112                         } else {
++00113                                 retval = 6265 + FS_LS_HOST_DELAY + retval;
++00114                         }
++00115                 } else {
++00116                         retval =
++00117                             (8354 * (31 + 10 * BitStuffTime(bytecount))) / 1000;
++00118                         retval = 9107 + FS_LS_HOST_DELAY + retval;
++00119                 }
++00120                 break;
++00121         case USB_SPEED_LOW:
++00122                 if (is_in) {
++00123                         retval =
++00124                             (67667 * (31 + 10 * BitStuffTime(bytecount))) /
++00125                             1000;
++00126                         retval =
++00127                             64060 + (2 * HUB_LS_SETUP) + FS_LS_HOST_DELAY +
++00128                             retval;
++00129                 } else {
++00130                         retval =
++00131                             (66700 * (31 + 10 * BitStuffTime(bytecount))) /
++00132                             1000;
++00133                         retval =
++00134                             64107 + (2 * HUB_LS_SETUP) + FS_LS_HOST_DELAY +
++00135                             retval;
++00136                 }
++00137                 break;
++00138         default:
++00139                 DWC_WARN("Unknown device speed\n");
++00140                 retval = -1;
++00141         }
++00142 
++00143         return NS_TO_US(retval);
++00144 }
++00145 
++00154 #define SCHEDULE_SLOP 10
++00155 void qh_init(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh, dwc_otg_hcd_urb_t * urb)
++00156 {
++00157         char *speed, *type;
++00158         int dev_speed;
++00159         uint32_t hub_addr, hub_port;
++00160 
++00161         dwc_memset(qh, 0, sizeof(dwc_otg_qh_t));
++00162 
++00163         /* Initialize QH */
++00164         qh->ep_type = dwc_otg_hcd_get_pipe_type(&urb->pipe_info);
++00165         qh->ep_is_in = dwc_otg_hcd_is_pipe_in(&urb->pipe_info) ? 1 : 0;
++00166 
++00167         qh->data_toggle = DWC_OTG_HC_PID_DATA0;
++00168         qh->maxp = dwc_otg_hcd_get_mps(&urb->pipe_info);
++00169         DWC_CIRCLEQ_INIT(&qh->qtd_list);
++00170         DWC_LIST_INIT(&qh->qh_list_entry);
++00171         qh->channel = NULL;
++00172 
++00173         /* FS/LS Enpoint on HS Hub 
++00174          * NOT virtual root hub */
++00175         dev_speed = hcd->fops->speed(hcd, urb->priv);
++00176 
++00177         hcd->fops->hub_info(hcd, urb->priv, &hub_addr, &hub_port);
++00178         qh->do_split = 0;
++00179 
++00180         if (((dev_speed == USB_SPEED_LOW) ||
++00181              (dev_speed == USB_SPEED_FULL)) &&
++00182             (hub_addr != 0 && hub_addr != 1)) {
++00183                 DWC_DEBUGPL(DBG_HCD,
++00184                             "QH init: EP %d: TT found at hub addr %d, for port %d\n",
++00185                             dwc_otg_hcd_get_ep_num(&urb->pipe_info), hub_addr,
++00186                             hub_port);
++00187                 qh->do_split = 1;
++00188         }
++00189 
++00190         if (qh->ep_type == UE_INTERRUPT || qh->ep_type == UE_ISOCHRONOUS) {
++00191                 /* Compute scheduling parameters once and save them. */
++00192                 hprt0_data_t hprt;
++00193 
++00195                 int bytecount =
++00196                     dwc_hb_mult(qh->maxp) * dwc_max_packet(qh->maxp);
++00197 
++00198                 qh->usecs =
++00199                     calc_bus_time((qh->do_split ? USB_SPEED_HIGH : dev_speed),
++00200                                   qh->ep_is_in, (qh->ep_type == UE_ISOCHRONOUS),
++00201                                   bytecount);
++00202                 /* Start in a slightly future (micro)frame. */
++00203                 qh->sched_frame = dwc_frame_num_inc(hcd->frame_number,
++00204                                                     SCHEDULE_SLOP);
++00205                 qh->interval = urb->interval;
++00206 
++00207 #if 0
++00208                 /* Increase interrupt polling rate for debugging. */
++00209                 if (qh->ep_type == UE_INTERRUPT) {
++00210                         qh->interval = 8;
++00211                 }
++00212 #endif
++00213                 hprt.d32 = DWC_READ_REG32(hcd->core_if->host_if->hprt0);
++00214                 if ((hprt.b.prtspd == DWC_HPRT0_PRTSPD_HIGH_SPEED) &&
++00215                     ((dev_speed == USB_SPEED_LOW) ||
++00216                      (dev_speed == USB_SPEED_FULL))) {
++00217                         qh->interval *= 8;
++00218                         qh->sched_frame |= 0x7;
++00219                         qh->start_split_frame = qh->sched_frame;
++00220                 }
++00221 
++00222         }
++00223 
++00224         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD QH Initialized\n");
++00225         DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH  - qh = %p\n", qh);
++00226         DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH  - Device Address = %d\n",
++00227                     dwc_otg_hcd_get_dev_addr(&urb->pipe_info));
++00228         DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH  - Endpoint %d, %s\n",
++00229                     dwc_otg_hcd_get_ep_num(&urb->pipe_info),
++00230                     dwc_otg_hcd_is_pipe_in(&urb->pipe_info) ? "IN" : "OUT");
++00231         switch (dev_speed) {
++00232         case USB_SPEED_LOW:
++00233                 qh->dev_speed = DWC_OTG_EP_SPEED_LOW;
++00234                 speed = "low";
++00235                 break;
++00236         case USB_SPEED_FULL:
++00237                 qh->dev_speed = DWC_OTG_EP_SPEED_FULL;
++00238                 speed = "full";
++00239                 break;
++00240         case USB_SPEED_HIGH:
++00241                 qh->dev_speed = DWC_OTG_EP_SPEED_HIGH;
++00242                 speed = "high";
++00243                 break;
++00244         default:
++00245                 speed = "?";
++00246                 break;
++00247         }
++00248         DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH  - Speed = %s\n", speed);
++00249 
++00250         switch (qh->ep_type) {
++00251         case UE_ISOCHRONOUS:
++00252                 type = "isochronous";
++00253                 break;
++00254         case UE_INTERRUPT:
++00255                 type = "interrupt";
++00256                 break;
++00257         case UE_CONTROL:
++00258                 type = "control";
++00259                 break;
++00260         case UE_BULK:
++00261                 type = "bulk";
++00262                 break;
++00263         default:
++00264                 type = "?";
++00265                 break;
++00266         }
++00267 
++00268         DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH  - Type = %s\n", type);
++00269 
++00270 #ifdef DEBUG
++00271         if (qh->ep_type == UE_INTERRUPT) {
++00272                 DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - usecs = %d\n",
++00273                             qh->usecs);
++00274                 DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - interval = %d\n",
++00275                             qh->interval);
++00276         }
++00277 #endif
++00278 
++00279 }
++00280 
++00290 dwc_otg_qh_t *dwc_otg_hcd_qh_create(dwc_otg_hcd_t * hcd,
++00291                                     dwc_otg_hcd_urb_t * urb, int atomic_alloc)
++00292 {
++00293         dwc_otg_qh_t *qh;
++00294 
++00295         /* Allocate memory */
++00297         qh = dwc_otg_hcd_qh_alloc(atomic_alloc);
++00298         if (qh == NULL) {
++00299                 DWC_ERROR("qh allocation failed");
++00300                 return NULL;
++00301         }
++00302 
++00303         qh_init(hcd, qh, urb);
++00304 
++00305         if (hcd->core_if->dma_desc_enable
++00306             && (dwc_otg_hcd_qh_init_ddma(hcd, qh) < 0)) {
++00307                 dwc_otg_hcd_qh_free(hcd, qh);
++00308                 return NULL;
++00309         }
++00310 
++00311         return qh;
++00312 }
++00313 
++00319 static int periodic_channel_available(dwc_otg_hcd_t * hcd)
++00320 {
++00321         /*
++00322          * Currently assuming that there is a dedicated host channnel for each
++00323          * periodic transaction plus at least one host channel for
++00324          * non-periodic transactions.
++00325          */
++00326         int status;
++00327         int num_channels;
++00328 
++00329         num_channels = hcd->core_if->core_params->host_channels;
++00330         if ((hcd->periodic_channels + hcd->non_periodic_channels < num_channels)
++00331             && (hcd->periodic_channels < num_channels - 1)) {
++00332                 status = 0;
++00333         } else {
++00334                 DWC_INFO("%s: Total channels: %d, Periodic: %d, Non-periodic: %d\n",
++00335                         __func__, num_channels, hcd->periodic_channels, hcd->non_periodic_channels);    //NOTICE
++00336                 status = -DWC_E_NO_SPACE;
++00337         }
++00338 
++00339         return status;
++00340 }
++00341 
++00352 static int check_periodic_bandwidth(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
++00353 {
++00354         int status;
++00355         int16_t max_claimed_usecs;
++00356 
++00357         status = 0;
++00358 
++00359         if ((qh->dev_speed == DWC_OTG_EP_SPEED_HIGH) || qh->do_split) {
++00360                 /*
++00361                  * High speed mode.
++00362                  * Max periodic usecs is 80% x 125 usec = 100 usec.
++00363                  */
++00364 
++00365                 max_claimed_usecs = 100 - qh->usecs;
++00366         } else {
++00367                 /*
++00368                  * Full speed mode.
++00369                  * Max periodic usecs is 90% x 1000 usec = 900 usec.
++00370                  */
++00371                 max_claimed_usecs = 900 - qh->usecs;
++00372         }
++00373 
++00374         if (hcd->periodic_usecs > max_claimed_usecs) {
++00375                 DWC_INFO("%s: already claimed usecs %d, required usecs %d\n", __func__, hcd->periodic_usecs, qh->usecs);        //NOTICE
++00376                 status = -DWC_E_NO_SPACE;
++00377         }
++00378 
++00379         return status;
++00380 }
++00381 
++00392 static int check_max_xfer_size(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
++00393 {
++00394         int status;
++00395         uint32_t max_xfer_size;
++00396         uint32_t max_channel_xfer_size;
++00397 
++00398         status = 0;
++00399 
++00400         max_xfer_size = dwc_max_packet(qh->maxp) * dwc_hb_mult(qh->maxp);
++00401         max_channel_xfer_size = hcd->core_if->core_params->max_transfer_size;
++00402 
++00403         if (max_xfer_size > max_channel_xfer_size) {
++00404                 DWC_INFO("%s: Periodic xfer length %d > " "max xfer length for channel %d\n",
++00405                                 __func__, max_xfer_size, max_channel_xfer_size);        //NOTICE
++00406                 status = -DWC_E_NO_SPACE;
++00407         }
++00408 
++00409         return status;
++00410 }
++00411 
++00421 static int schedule_periodic(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
++00422 {
++00423         int status = 0;
++00424 
++00425         status = periodic_channel_available(hcd);
++00426         if (status) {
++00427                 DWC_INFO("%s: No host channel available for periodic " "transfer.\n", __func__);        //NOTICE
++00428                 return status;
++00429         }
++00430 
++00431         status = check_periodic_bandwidth(hcd, qh);
++00432         if (status) {
++00433                 DWC_INFO("%s: Insufficient periodic bandwidth for " "periodic transfer.\n", __func__);  //NOTICE
++00434                 return status;
++00435         }
++00436 
++00437         status = check_max_xfer_size(hcd, qh);
++00438         if (status) {
++00439                 DWC_INFO("%s: Channel max transfer size too small " "for periodic transfer.\n", __func__);      //NOTICE
++00440                 return status;
++00441         }
++00442 
++00443         if (hcd->core_if->dma_desc_enable) {
++00444                 /* Don't rely on SOF and start in ready schedule */
++00445                 DWC_LIST_INSERT_TAIL(&hcd->periodic_sched_ready, &qh->qh_list_entry);
++00446         }
++00447         else {
++00448         /* Always start in the inactive schedule. */
++00449         DWC_LIST_INSERT_TAIL(&hcd->periodic_sched_inactive, &qh->qh_list_entry);
++00450         }
++00451 
++00452         /* Reserve the periodic channel. */
++00453         hcd->periodic_channels++;
++00454 
++00455         /* Update claimed usecs per (micro)frame. */
++00456         hcd->periodic_usecs += qh->usecs;
++00457 
++00458         return status;
++00459 }
++00460 
++00468 int dwc_otg_hcd_qh_add(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
++00469 {
++00470         int status = 0;
++00471         gintmsk_data_t intr_mask = {.d32 = 0 };
++00472 
++00473         if (!DWC_LIST_EMPTY(&qh->qh_list_entry)) {
++00474                 /* QH already in a schedule. */
++00475                 return status;
++00476         }
++00477 
++00478         /* Add the new QH to the appropriate schedule */
++00479         if (dwc_qh_is_non_per(qh)) {
++00480                 /* Always start in the inactive schedule. */
++00481                 DWC_LIST_INSERT_TAIL(&hcd->non_periodic_sched_inactive,
++00482                                      &qh->qh_list_entry);
++00483         } else {
++00484                 status = schedule_periodic(hcd, qh);
++00485                 if ( !hcd->periodic_qh_count ) {
++00486                         intr_mask.b.sofintr = 1;
++00487                         DWC_MODIFY_REG32(&hcd->core_if->core_global_regs->gintmsk,
++00488                                                                 intr_mask.d32, intr_mask.d32);
++00489                 }
++00490                 hcd->periodic_qh_count++;
++00491         }
++00492 
++00493         return status;
++00494 }
++00495 
++00502 static void deschedule_periodic(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
++00503 {
++00504         DWC_LIST_REMOVE_INIT(&qh->qh_list_entry);
++00505 
++00506         /* Release the periodic channel reservation. */
++00507         hcd->periodic_channels--;
++00508 
++00509         /* Update claimed usecs per (micro)frame. */
++00510         hcd->periodic_usecs -= qh->usecs;
++00511 }
++00512 
++00519 void dwc_otg_hcd_qh_remove(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
++00520 {
++00521         gintmsk_data_t intr_mask = {.d32 = 0 };
++00522 
++00523         if (DWC_LIST_EMPTY(&qh->qh_list_entry)) {
++00524                 /* QH is not in a schedule. */
++00525                 return;
++00526         }
++00527 
++00528         if (dwc_qh_is_non_per(qh)) {
++00529                 if (hcd->non_periodic_qh_ptr == &qh->qh_list_entry) {
++00530                         hcd->non_periodic_qh_ptr =
++00531                             hcd->non_periodic_qh_ptr->next;
++00532                 }
++00533                 DWC_LIST_REMOVE_INIT(&qh->qh_list_entry);
++00534         } else {
++00535                 deschedule_periodic(hcd, qh);
++00536                 hcd->periodic_qh_count--;
++00537                 if( !hcd->periodic_qh_count ) {
++00538                         intr_mask.b.sofintr = 1;
++00539                                 DWC_MODIFY_REG32(&hcd->core_if->core_global_regs->gintmsk,
++00540                                                                         intr_mask.d32, 0);
++00541                 }
++00542         }
++00543 }
++00544 
++00558 void dwc_otg_hcd_qh_deactivate(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh,
++00559                                int sched_next_periodic_split)
++00560 {       
++00561         if (dwc_qh_is_non_per(qh)) {
++00562                 dwc_otg_hcd_qh_remove(hcd, qh);
++00563                 if (!DWC_CIRCLEQ_EMPTY(&qh->qtd_list)) {
++00564                         /* Add back to inactive non-periodic schedule. */
++00565                         dwc_otg_hcd_qh_add(hcd, qh);
++00566                 }
++00567         } else {
++00568                 uint16_t frame_number = dwc_otg_hcd_get_frame_number(hcd);
++00569 
++00570                 if (qh->do_split) {
++00571                         /* Schedule the next continuing periodic split transfer */
++00572                         if (sched_next_periodic_split) {
++00573 
++00574                                 qh->sched_frame = frame_number;
++00575                                 if (dwc_frame_num_le(frame_number,
++00576                                                      dwc_frame_num_inc
++00577                                                      (qh->start_split_frame,
++00578                                                       1))) {
++00579                                         /*
++00580                                          * Allow one frame to elapse after start
++00581                                          * split microframe before scheduling
++00582                                          * complete split, but DONT if we are
++00583                                          * doing the next start split in the
++00584                                          * same frame for an ISOC out.
++00585                                          */
++00586                                         if ((qh->ep_type != UE_ISOCHRONOUS) ||
++00587                                             (qh->ep_is_in != 0)) {
++00588                                                 qh->sched_frame =
++00589                                                     dwc_frame_num_inc(qh->sched_frame, 1);
++00590                                         }
++00591                                 }
++00592                         } else {
++00593                                 qh->sched_frame =
++00594                                     dwc_frame_num_inc(qh->start_split_frame,
++00595                                                       qh->interval);
++00596                                 if (dwc_frame_num_le
++00597                                     (qh->sched_frame, frame_number)) {
++00598                                         qh->sched_frame = frame_number;
++00599                                 }
++00600                                 qh->sched_frame |= 0x7;
++00601                                 qh->start_split_frame = qh->sched_frame;
++00602                         }
++00603                 } else {
++00604                         qh->sched_frame =
++00605                             dwc_frame_num_inc(qh->sched_frame, qh->interval);
++00606                         if (dwc_frame_num_le(qh->sched_frame, frame_number)) {
++00607                                 qh->sched_frame = frame_number;
++00608                         }
++00609                 }
++00610 
++00611                 if (DWC_CIRCLEQ_EMPTY(&qh->qtd_list)) {
++00612                         dwc_otg_hcd_qh_remove(hcd, qh);
++00613                 } else {
++00614                         /*
++00615                          * Remove from periodic_sched_queued and move to
++00616                          * appropriate queue.
++00617                          */
++00618                         if (qh->sched_frame == frame_number) {
++00619                                 DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_ready,
++00620                                                    &qh->qh_list_entry);
++00621                         } else {
++00622                                 DWC_LIST_MOVE_HEAD
++00623                                     (&hcd->periodic_sched_inactive,
++00624                                      &qh->qh_list_entry);
++00625                         }
++00626                 }
++00627         }
++00628 }
++00629 
++00638 dwc_otg_qtd_t *dwc_otg_hcd_qtd_create(dwc_otg_hcd_urb_t * urb, int atomic_alloc)
++00639 {
++00640         dwc_otg_qtd_t *qtd;
++00641 
++00642         qtd = dwc_otg_hcd_qtd_alloc(atomic_alloc);
++00643         if (qtd == NULL) {
++00644                 return NULL;
++00645         }
++00646 
++00647         dwc_otg_hcd_qtd_init(qtd, urb);
++00648         return qtd;
++00649 }
++00650 
++00656 void dwc_otg_hcd_qtd_init(dwc_otg_qtd_t * qtd, dwc_otg_hcd_urb_t * urb)
++00657 {
++00658         dwc_memset(qtd, 0, sizeof(dwc_otg_qtd_t));
++00659         qtd->urb = urb;
++00660         if (dwc_otg_hcd_get_pipe_type(&urb->pipe_info) == UE_CONTROL) {
++00661                 /*
++00662                  * The only time the QTD data toggle is used is on the data
++00663                  * phase of control transfers. This phase always starts with
++00664                  * DATA1.
++00665                  */
++00666                 qtd->data_toggle = DWC_OTG_HC_PID_DATA1;
++00667                 qtd->control_phase = DWC_OTG_CONTROL_SETUP;
++00668         }
++00669 
++00670         /* start split */
++00671         qtd->complete_split = 0;
++00672         qtd->isoc_split_pos = DWC_HCSPLIT_XACTPOS_ALL;
++00673         qtd->isoc_split_offset = 0;
++00674         qtd->in_process = 0;
++00675 
++00676         /* Store the qtd ptr in the urb to reference what QTD. */
++00677         urb->qtd = qtd;
++00678         return;
++00679 }
++00680 
++00694 int dwc_otg_hcd_qtd_add(dwc_otg_qtd_t * qtd,
++00695                         dwc_otg_hcd_t * hcd, dwc_otg_qh_t ** qh, int atomic_alloc)
++00696 {
++00697         int retval = 0;
++00698         dwc_irqflags_t flags;
++00699 
++00700         dwc_otg_hcd_urb_t *urb = qtd->urb;
++00701 
++00702         /*
++00703          * Get the QH which holds the QTD-list to insert to. Create QH if it
++00704          * doesn't exist.
++00705          */
++00706         if (*qh == NULL) {
++00707                 *qh = dwc_otg_hcd_qh_create(hcd, urb, atomic_alloc);
++00708                 if (*qh == NULL) {
++00709                         retval = -1;
++00710                         goto done;
++00711                 }
++00712         }
++00713         DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
++00714         retval = dwc_otg_hcd_qh_add(hcd, *qh);
++00715         if (retval == 0) {
++00716                 DWC_CIRCLEQ_INSERT_TAIL(&((*qh)->qtd_list), qtd,
++00717                                         qtd_list_entry);
++00718         }
++00719         DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
++00720 
++00721 done:
++00722 
++00723         return retval;
++00724 }
++00725 
++00726 #endif /* DWC_DEVICE_ONLY */
++
    Generated on Thu Oct 27 03:56:37 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
    ++doxygen 1.3.9.1
    + + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__hcd__queue_8c.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/dwc__otg__hcd__queue_8c.html 2013-07-26 19:31:21.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__hcd__queue_8c.html 2013-07-26 19:34:41.000000000 +0000 +@@ -2,93 +2,81 @@ + + DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_hcd_queue.c File Reference + +- + +- +-
    +-
    +-
    +-
    ++ ++
    Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
    +

    dwc_otg_hcd_queue.c File Reference

    This file contains the functions to manage Queue Heads and Queue Transfer Descriptors. More... +

    +-#include "dwc_otg_hcd.h"
    +-#include "dwc_otg_regs.h"
    ++#include "dwc_otg_hcd.h"
    ++#include "dwc_otg_regs.h"
    + +

    + Go to the source code of this file. + + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- +- ++ ++ + +- ++ + +- ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- ++ +

    Defines

    +-#define BitStuffTime(bytecount)   ((8 * 7* bytecount) / 6)
    ++#define BitStuffTime(bytecount)   ((8 * 7* bytecount) / 6)
    +-#define HS_HOST_DELAY   5
    ++#define HS_HOST_DELAY   5
    +-#define FS_LS_HOST_DELAY   1000
    ++#define FS_LS_HOST_DELAY   1000
    +-#define HUB_LS_SETUP   333
    ++#define HUB_LS_SETUP   333
    +-#define NS_TO_US(ns)   ((ns + 500) / 1000)
    ++#define NS_TO_US(ns)   ((ns + 500) / 1000)
    #define SCHEDULE_SLOP   10
    #define SCHEDULE_SLOP   10
     Initializes a QH structure.
     Initializes a QH structure.

    Functions

    void dwc_otg_hcd_qh_free (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
    void dwc_otg_hcd_qh_free (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
     Free each QTD in the QH's QTD-list then free the QH.
    +-static uint32_t calc_bus_time (int speed, int is_in, int is_isoc, int bytecount)
     Free each QTD in the QH's QTD-list then free the QH.
    ++uint32_t calc_bus_time (int speed, int is_in, int is_isoc, int bytecount)
    void qh_init (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh, dwc_otg_hcd_urb_t *urb)
    void qh_init (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh, dwc_otg_hcd_urb_t *urb)
    dwc_otg_qh_t * dwc_otg_hcd_qh_create (dwc_otg_hcd_t *hcd, dwc_otg_hcd_urb_t *urb)
    dwc_otg_qh_t * dwc_otg_hcd_qh_create (dwc_otg_hcd_t *hcd, dwc_otg_hcd_urb_t *urb, int atomic_alloc)
     This function allocates and initializes a QH.
    static int periodic_channel_available (dwc_otg_hcd_t *hcd)
     This function allocates and initializes a QH.
    int periodic_channel_available (dwc_otg_hcd_t *hcd)
     Checks that a channel is available for a periodic transfer.
    static int check_periodic_bandwidth (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
     Checks that a channel is available for a periodic transfer.
    int check_periodic_bandwidth (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
     Checks that there is sufficient bandwidth for the specified QH in the periodic schedule.
    static int check_max_xfer_size (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
     Checks that there is sufficient bandwidth for the specified QH in the periodic schedule.
    int check_max_xfer_size (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
     Checks that the max transfer size allowed in a host channel is large enough to handle the maximum data transfer in a single (micro)frame for a periodic transfer.
    static int schedule_periodic (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
     Checks that the max transfer size allowed in a host channel is large enough to handle the maximum data transfer in a single (micro)frame for a periodic transfer.
    int schedule_periodic (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
     Schedules an interrupt or isochronous transfer in the periodic schedule.
    int dwc_otg_hcd_qh_add (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
     Schedules an interrupt or isochronous transfer in the periodic schedule.
    int dwc_otg_hcd_qh_add (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
     This function adds a QH to either the non periodic or periodic schedule if it is not already in the schedule.
    static void deschedule_periodic (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
     This function adds a QH to either the non periodic or periodic schedule if it is not already in the schedule.
    void deschedule_periodic (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
     Removes an interrupt or isochronous transfer from the periodic schedule.
    void dwc_otg_hcd_qh_remove (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
     Removes an interrupt or isochronous transfer from the periodic schedule.
    void dwc_otg_hcd_qh_remove (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
     Removes a QH from either the non-periodic or periodic schedule.
    void dwc_otg_hcd_qh_deactivate (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh, int sched_next_periodic_split)
     Removes a QH from either the non-periodic or periodic schedule.
    void dwc_otg_hcd_qh_deactivate (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh, int sched_next_periodic_split)
     Deactivates a QH.
    dwc_otg_qtd_t * dwc_otg_hcd_qtd_create (dwc_otg_hcd_urb_t *urb)
     Deactivates a QH.
    dwc_otg_qtd_t * dwc_otg_hcd_qtd_create (dwc_otg_hcd_urb_t *urb, int atomic_alloc)
     This function allocates and initializes a QTD.
    void dwc_otg_hcd_qtd_init (dwc_otg_qtd_t *qtd, dwc_otg_hcd_urb_t *urb)
     This function allocates and initializes a QTD.
    void dwc_otg_hcd_qtd_init (dwc_otg_qtd_t *qtd, dwc_otg_hcd_urb_t *urb)
     Initializes a QTD structure.
    int dwc_otg_hcd_qtd_add (dwc_otg_qtd_t *qtd, dwc_otg_hcd_t *hcd, dwc_otg_qh_t **qh)
     Initializes a QTD structure.
    int dwc_otg_hcd_qtd_add (dwc_otg_qtd_t *qtd, dwc_otg_hcd_t *hcd, dwc_otg_qh_t **qh, int atomic_alloc)
     This function adds a QTD to the QTD-list of a QH.
     This function adds a QTD to the QTD-list of a QH.
    +

    Detailed Description

    + This file contains the functions to manage Queue Heads and Queue Transfer Descriptors. +@@ -96,16 +84,24 @@ + +

    + Definition in file dwc_otg_hcd_queue.c.

    Define Documentation

    +- +-
    +-
    +- ++

    ++

    ++ ++ ++ ++
    ++ + +- ++ + +
    #define SCHEDULE_SLOP   10 #define SCHEDULE_SLOP   10
    +- +-
    ++
    ++ ++ ++ ++ ++ ++
    ++   ++ + +

    + Initializes a QH structure. +@@ -119,34 +115,42 @@ + + +

    +-Definition at line 159 of file dwc_otg_hcd_queue.c. +- +-

    ++Definition at line 154 of file dwc_otg_hcd_queue.c.

    +

    Function Documentation

    +- +-
    +-
    +- ++

    ++

    ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    void dwc_otg_hcd_qh_free (dwc_otg_hcd_t *  hcd, void dwc_otg_hcd_qh_free ( dwc_otg_hcd_t *  hcd,
    dwc_otg_qh_t *  qh dwc_otg_qh_t *  qh
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Free each QTD in the QH's QTD-list then free the QH. +@@ -160,70 +164,93 @@ + + +

    +-Definition at line 53 of file dwc_otg_hcd_queue.c. +- +-

    +- +-

    +-
    +- ++Definition at line 53 of file dwc_otg_hcd_queue.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    void qh_init (dwc_otg_hcd_t *  hcd, void qh_init ( dwc_otg_hcd_t *  hcd,
    dwc_otg_qh_t *  qh, dwc_otg_qh_t *  qh,
    dwc_otg_hcd_urb_t *  urb dwc_otg_hcd_urb_t *  urb
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    ++

    Todo:
    Account for split transfers in the bus time.
    + +

    +-Definition at line 160 of file dwc_otg_hcd_queue.c. +- +-

    +- +-

    +-
    +- ++Definition at line 155 of file dwc_otg_hcd_queue.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ ++ ++ ++ ++ ++ ++ + +
    dwc_otg_qh_t* dwc_otg_hcd_qh_create (dwc_otg_hcd_t *  hcd, dwc_otg_qh_t* dwc_otg_hcd_qh_create ( dwc_otg_hcd_t *  hcd,
    dwc_otg_hcd_urb_t *  urb dwc_otg_hcd_urb_t *  urb,
    )int  atomic_alloc
    ) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + This function allocates and initializes a QH. +@@ -231,33 +258,41 @@ +

    Parameters:
    + + +- ++ ++ +
    hcd The HCD state structure for the DWC OTG controller.
    urb Holds the information about the device/endpoint that we need to initialize the QH.
    urb Holds the information about the device/endpoint that we need to initialize the QH.
    atomic_alloc Flag to do atomic allocation if needed
    +
    +-
    Returns:
    Returns pointer to the newly allocated QH, or NULL on error.
    +- ++
    Returns:
    Returns pointer to the newly allocated QH, or NULL on error.
    +

    +-

    Todo:
    add memflags argument
    ++
    Todo:
    add memflags argument
    + +

    +-Definition at line 296 of file dwc_otg_hcd_queue.c. +- +-

    +- +-

    +-
    +- +- +- +- +- +- +- +- ++Definition at line 290 of file dwc_otg_hcd_queue.c. ++ ++
    static int periodic_channel_available (dwc_otg_hcd_t *  hcd  )  [static]
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ + +
    int periodic_channel_available ( dwc_otg_hcd_t *  hcd  )  [static]
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Checks that a channel is available for a periodic transfer. +@@ -265,33 +300,41 @@ +

    Returns:
    0 if successful, negative error code otherise.
    + +

    +-Definition at line 323 of file dwc_otg_hcd_queue.c. +- +-

    +- +-

    +-
    +- ++Definition at line 319 of file dwc_otg_hcd_queue.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    static int check_periodic_bandwidth (dwc_otg_hcd_t *  hcd, int check_periodic_bandwidth ( dwc_otg_hcd_t *  hcd,
    dwc_otg_qh_t *  qh dwc_otg_qh_t *  qh
    ) [static])  [static]
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Checks that there is sufficient bandwidth for the specified QH in the periodic schedule. +@@ -306,33 +349,41 @@ +

    Returns:
    0 if successful, negative error code otherwise.
    + +

    +-Definition at line 356 of file dwc_otg_hcd_queue.c. +- +-

    +- +-

    +-
    +- ++Definition at line 352 of file dwc_otg_hcd_queue.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    static int check_max_xfer_size (dwc_otg_hcd_t *  hcd, int check_max_xfer_size ( dwc_otg_hcd_t *  hcd,
    dwc_otg_qh_t *  qh dwc_otg_qh_t *  qh
    ) [static])  [static]
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Checks that the max transfer size allowed in a host channel is large enough to handle the maximum data transfer in a single (micro)frame for a periodic transfer. +@@ -346,33 +397,41 @@ +

    Returns:
    0 if successful, negative error code otherwise.
    + +

    +-Definition at line 396 of file dwc_otg_hcd_queue.c. +- +-

    +- +-

    +-
    +- ++Definition at line 392 of file dwc_otg_hcd_queue.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    static int schedule_periodic (dwc_otg_hcd_t *  hcd, int schedule_periodic ( dwc_otg_hcd_t *  hcd,
    dwc_otg_qh_t *  qh dwc_otg_qh_t *  qh
    ) [static])  [static]
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Schedules an interrupt or isochronous transfer in the periodic schedule. +@@ -386,33 +445,41 @@ +

    Returns:
    0 if successful, negative error code otherwise.
    + +

    +-Definition at line 425 of file dwc_otg_hcd_queue.c. +- +-

    +- +-

    +-
    +- ++Definition at line 421 of file dwc_otg_hcd_queue.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    int dwc_otg_hcd_qh_add (dwc_otg_hcd_t *  hcd, int dwc_otg_hcd_qh_add ( dwc_otg_hcd_t *  hcd,
    dwc_otg_qh_t *  qh dwc_otg_qh_t *  qh
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + This function adds a QH to either the non periodic or periodic schedule if it is not already in the schedule. +@@ -421,33 +488,41 @@ +

    Returns:
    0 if successful, negative error code otherwise.
    + +

    +-Definition at line 472 of file dwc_otg_hcd_queue.c. +- +-

    +- +-

    +-
    +- ++Definition at line 468 of file dwc_otg_hcd_queue.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    static void deschedule_periodic (dwc_otg_hcd_t *  hcd, void deschedule_periodic ( dwc_otg_hcd_t *  hcd,
    dwc_otg_qh_t *  qh dwc_otg_qh_t *  qh
    ) [static])  [static]
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Removes an interrupt or isochronous transfer from the periodic schedule. +@@ -460,33 +535,41 @@ + + +

    +-Definition at line 505 of file dwc_otg_hcd_queue.c. +- +-

    +- +-

    +-
    +- ++Definition at line 502 of file dwc_otg_hcd_queue.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    void dwc_otg_hcd_qh_remove (dwc_otg_hcd_t *  hcd, void dwc_otg_hcd_qh_remove ( dwc_otg_hcd_t *  hcd,
    dwc_otg_qh_t *  qh dwc_otg_qh_t *  qh
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Removes a QH from either the non-periodic or periodic schedule. +@@ -500,39 +583,47 @@ + + +

    +-Definition at line 522 of file dwc_otg_hcd_queue.c. +- +-

    +- +-

    +-
    +- ++Definition at line 519 of file dwc_otg_hcd_queue.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    void dwc_otg_hcd_qh_deactivate (dwc_otg_hcd_t *  hcd, void dwc_otg_hcd_qh_deactivate ( dwc_otg_hcd_t *  hcd,
    dwc_otg_qh_t *  qh, dwc_otg_qh_t *  qh,
    int  sched_next_periodic_split int  sched_next_periodic_split
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Deactivates a QH. +@@ -540,63 +631,89 @@ + For non-periodic QHs, removes the QH from the active non-periodic schedule. The QH is added to the inactive non-periodic schedule if any QTDs are still attached to the QH.

    + For periodic QHs, the QH is removed from the periodic queued schedule. If there are any QTDs still attached to the QH, the QH is added to either the periodic inactive schedule or the periodic ready schedule and its next scheduled frame is calculated. The QH is placed in the ready schedule if the scheduled frame has been reached already. Otherwise it's placed in the inactive schedule. If there are no QTDs attached to the QH, the QH is completely removed from the periodic schedule. +

    +-Definition at line 559 of file dwc_otg_hcd_queue.c. +- +-

    +- +-

    +-
    +- +- +- +- +- +- +- +- ++Definition at line 558 of file dwc_otg_hcd_queue.c. ++ ++
    dwc_otg_qtd_t* dwc_otg_hcd_qtd_create (dwc_otg_hcd_urb_t *  urb  ) 
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ + +
    dwc_otg_qtd_t* dwc_otg_hcd_qtd_create ( dwc_otg_hcd_urb_t *  urb,
    int  atomic_alloc
    ) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + This function allocates and initializes a QTD. +

    +

    Parameters:
    + +- ++ ++ +
    urb The URB to create a QTD from. Each URB-QTD pair will end up pointing to each other so each pair should have a unique correlation.
    urb The URB to create a QTD from. Each URB-QTD pair will end up pointing to each other so each pair should have a unique correlation.
    atomic_alloc Flag to do atomic alloc if needed
    +
    +
    Returns:
    Returns pointer to the newly allocated QTD, or NULL on error.
    + +

    +-Definition at line 643 of file dwc_otg_hcd_queue.c. +- +-

    +- +-

    +-
    +- ++Definition at line 638 of file dwc_otg_hcd_queue.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    void dwc_otg_hcd_qtd_init (dwc_otg_qtd_t *  qtd, void dwc_otg_hcd_qtd_init ( dwc_otg_qtd_t *  qtd,
    dwc_otg_hcd_urb_t *  urb dwc_otg_hcd_urb_t *  urb
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Initializes a QTD structure. +@@ -609,39 +726,53 @@ + + +

    +-Definition at line 661 of file dwc_otg_hcd_queue.c. +- +-

    +- +-

    +-
    +- ++Definition at line 656 of file dwc_otg_hcd_queue.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    int dwc_otg_hcd_qtd_add ( dwc_otg_qtd_t *  qtd,
    int dwc_otg_hcd_qtd_add (dwc_otg_qtd_t *  qtd, dwc_otg_hcd_t *  hcd,
    dwc_otg_hcd_t *  hcd, dwc_otg_qh_t **  qh,
    dwc_otg_qh_t **  qh int  atomic_alloc
    )) 
    +- +-
    ++
    ++ ++ ++ ++ ++ ++
    ++   ++ + +

    + This function adds a QTD to the QTD-list of a QH. +@@ -651,17 +782,18 @@ + + + +- ++ ++ +
    [in] qtd The QTD to add
    [in] hcd The DWC HCD structure
    [out] qh out parameter to return queue head
    [out] qh out parameter to return queue head
    atomic_alloc Flag to do atomic alloc if needed
    + +

    Returns:
    0 if successful, negative error code otherwise.
    + +

    +-Definition at line 698 of file dwc_otg_hcd_queue.c. +- +-

    +-

    Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++Definition at line 694 of file dwc_otg_hcd_queue.c.
    ++

    Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
    ++doxygen 1.3.9.1 + + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__os__dep_8h-source.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__os__dep_8h-source.html 2013-07-26 19:34:41.000000000 +0000 +@@ -0,0 +1,102 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_os_dep.h Source File ++ ++ ++ ++
    Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
    ++

    dwc_otg_os_dep.h

    Go to the documentation of this file.
    00001 #ifndef _DWC_OS_DEP_H_
++00002 #define _DWC_OS_DEP_H_
++00003 
++00011 #include <linux/kernel.h>
++00012 #include <linux/module.h>
++00013 #include <linux/moduleparam.h>
++00014 #include <linux/init.h>
++00015 #include <linux/device.h>
++00016 #include <linux/errno.h>
++00017 #include <linux/types.h>
++00018 #include <linux/slab.h>
++00019 #include <linux/list.h>
++00020 #include <linux/interrupt.h>
++00021 #include <linux/ctype.h>
++00022 #include <linux/string.h>
++00023 #include <linux/dma-mapping.h>
++00024 #include <linux/jiffies.h>
++00025 #include <linux/delay.h>
++00026 #include <linux/timer.h>
++00027 #include <linux/workqueue.h>
++00028 #include <linux/stat.h>
++00029 #include <linux/pci.h>
++00030 
++00031 #include <linux/version.h>
++00032 
++00033 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
++00034 # include <linux/irq.h>
++00035 #endif
++00036 
++00037 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,21)
++00038 # include <linux/usb/ch9.h>
++00039 #else
++00040 # include <linux/usb_ch9.h>
++00041 #endif
++00042 
++00043 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,24)
++00044 # include <linux/usb/gadget.h>
++00045 #else
++00046 # include <linux/usb_gadget.h>
++00047 #endif
++00048 
++00049 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)
++00050 # include <asm/irq.h>
++00051 #endif
++00052 
++00053 #ifdef PCI_INTERFACE
++00054 # include <asm/io.h>
++00055 #endif
++00056 
++00057 #ifdef LM_INTERFACE
++00058 # include <asm/unaligned.h>
++00059 # include <asm/sizes.h>
++00060 # include <asm/param.h>
++00061 # include <asm/io.h>
++00062 # include <asm/arch/lm.h>
++00063 # include <asm/arch/irqs.h>
++00064 # include <asm/arch/regs-irq.h>
++00065 #endif
++00066 
++00068 #define DWC_OS_PAGE_SIZE        PAGE_SIZE
++00069 
++00070 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,14)
++00071 typedef int gfp_t;
++00072 #endif
++00073 
++00074 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18)
++00075 # define IRQF_SHARED SA_SHIRQ
++00076 #endif
++00077 
++00078 typedef struct os_dependent {
++00080         void *base;
++00081 
++00083         uint32_t reg_offset;
++00084 
++00085 #ifdef LM_INTERFACE
++00086         struct lm_device *lmdev;
++00087 #elif  defined(PCI_INTERFACE)
++00088         struct pci_dev *pcidev;
++00089 
++00091         resource_size_t rsrc_start;
++00092         
++00094         resource_size_t rsrc_len;
++00095 #endif
++00096 } os_dependent_t;
++00097 
++00098 #ifdef __cplusplus
++00099 }
++00100 #endif
++00101 
++00102 #endif /* _DWC_OS_DEP_H_ */
++
    Generated on Thu Oct 27 03:56:37 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.3.9.1
    ++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__os__dep_8h.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__os__dep_8h.html 2013-07-26 19:34:41.000000000 +0000 +@@ -0,0 +1,59 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_os_dep.h File Reference ++ ++ ++ ++
    Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
    ++

    dwc_otg_os_dep.h File Reference

    This file contains OS dependent structures. More... ++

    ++#include <linux/kernel.h>
    ++#include <linux/module.h>
    ++#include <linux/moduleparam.h>
    ++#include <linux/init.h>
    ++#include <linux/device.h>
    ++#include <linux/errno.h>
    ++#include <linux/types.h>
    ++#include <linux/slab.h>
    ++#include <linux/list.h>
    ++#include <linux/interrupt.h>
    ++#include <linux/ctype.h>
    ++#include <linux/string.h>
    ++#include <linux/dma-mapping.h>
    ++#include <linux/jiffies.h>
    ++#include <linux/delay.h>
    ++#include <linux/timer.h>
    ++#include <linux/workqueue.h>
    ++#include <linux/stat.h>
    ++#include <linux/pci.h>
    ++#include <linux/version.h>
    ++#include <linux/irq.h>
    ++#include <linux/usb/ch9.h>
    ++#include <linux/usb/gadget.h>
    ++ ++

    ++Go to the source code of this file. ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++

    Data Structures

    struct  os_dependent

    Defines

    ++#define DWC_OS_PAGE_SIZE   PAGE_SIZE
     The OS page size.

    Typedefs

    ++typedef os_dependent os_dependent_t
    ++

    Detailed Description

    ++This file contains OS dependent structures. ++

    ++ ++

    ++Definition in file dwc_otg_os_dep.h.

    Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.3.9.1
    ++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__pcd_8c-source.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/dwc__otg__pcd_8c-source.html 2013-07-26 19:31:21.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__pcd_8c-source.html 2013-07-26 19:34:41.000000000 +0000 +@@ -2,1850 +2,2437 @@ + + DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_pcd.c Source File + +- + +- +-
    +-
    +-
    +-
    +-

    dwc_otg_pcd.c

    Go to the documentation of this file.
    00001 /* ==========================================================================
+-00002  * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_pcd.c $
+-00003  * $Revision: #79 $
+-00004  * $Date: 2009/04/10 $
+-00005  * $Change: 1230501 $
+-00006  *
+-00007  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
+-00008  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
+-00009  * otherwise expressly agreed to in writing between Synopsys and you.
+-00010  *
+-00011  * The Software IS NOT an item of Licensed Software or Licensed Product under
+-00012  * any End User Software License Agreement or Agreement for Licensed Product
+-00013  * with Synopsys or any supplement thereto. You are permitted to use and
+-00014  * redistribute this Software in source and binary forms, with or without
+-00015  * modification, provided that redistributions of source code must retain this
+-00016  * notice. You may not view, use, disclose, copy or distribute this file or
+-00017  * any information contained herein except pursuant to this license grant from
+-00018  * Synopsys. If you do not agree with this notice, including the disclaimer
+-00019  * below, then you are not authorized to use the Software.
+-00020  *
+-00021  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
+-00022  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+-00023  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+-00024  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
+-00025  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+-00026  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+-00027  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+-00028  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+-00029  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+-00030  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+-00031  * DAMAGE.
+-00032  * ========================================================================== */
+-00033 #ifndef DWC_HOST_ONLY
+-00034 
+-00051 #include "dwc_otg_pcd.h"
+-00052 
+-00053 #ifdef DWC_UTE_CFI
+-00054 #include "dwc_otg_cfi.h"
+-00055 
+-00056 extern int init_cfi(cfiobject_t * cfiobj);
+-00057 #endif
+-00058 
+-00059 static dwc_otg_pcd_ep_t *get_ep_from_handle(dwc_otg_pcd_t * pcd, void *handle)
+-00060 {
+-00061         int i;
+-00062         if (pcd->ep0.priv == handle) {
+-00063                 return &pcd->ep0;
+-00064         }
+-00065         for (i = 0; i < MAX_EPS_CHANNELS - 1; i++) {
+-00066                 if (pcd->in_ep[i].priv == handle)
+-00067                         return &pcd->in_ep[i];
+-00068                 if (pcd->out_ep[i].priv == handle)
+-00069                         return &pcd->out_ep[i];
+-00070         }
+-00071 
+-00072         return NULL;
+-00073 }
+-00074 
+-00078 void dwc_otg_request_done(dwc_otg_pcd_ep_t * ep, dwc_otg_pcd_request_t * req,
+-00079                           int32_t status)
+-00080 {
+-00081         unsigned stopped = ep->stopped;
+-00082 
+-00083         DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, ep);
+-00084         DWC_CIRCLEQ_REMOVE_INIT(&ep->queue, req, queue_entry);
+-00085 
+-00086         /* don't modify queue heads during completion callback */
+-00087         ep->stopped = 1;
+-00088         DWC_SPINUNLOCK(ep->pcd->lock);
+-00089         ep->pcd->fops->complete(ep->pcd, ep->priv, req->priv, status,
+-00090                                 req->actual);
+-00091         DWC_SPINLOCK(ep->pcd->lock);
+-00092 
+-00093         if (ep->pcd->request_pending > 0) {
+-00094                 --ep->pcd->request_pending;
+-00095         }
+-00096 
+-00097         ep->stopped = stopped;
+-00098         dwc_free(req);
+-00099 }
+-00100 
+-00104 void dwc_otg_request_nuke(dwc_otg_pcd_ep_t * ep)
+-00105 {
+-00106         dwc_otg_pcd_request_t *req;
+-00107 
+-00108         ep->stopped = 1;
+-00109 
+-00110         /* called with irqs blocked?? */
+-00111         while (!DWC_CIRCLEQ_EMPTY(&ep->queue)) {
+-00112                 req = DWC_CIRCLEQ_FIRST(&ep->queue);
+-00113                 dwc_otg_request_done(ep, req, -DWC_E_SHUTDOWN);
+-00114         }
+-00115 }
+-00116 
+-00117 void dwc_otg_pcd_start(dwc_otg_pcd_t * pcd,
+-00118                        const struct dwc_otg_pcd_function_ops *fops)
+-00119 {
+-00120         pcd->fops = fops;
+-00121 }
+-00122 
+-00129 static int32_t dwc_otg_pcd_start_cb(void *p)
+-00130 {
+-00131         dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *) p;
+-00132 
+-00133         /*
+-00134          * Initialized the Core for Device mode.
+-00135          */
+-00136         if (dwc_otg_is_device_mode(GET_CORE_IF(pcd))) {
+-00137                 dwc_otg_core_dev_init(GET_CORE_IF(pcd));
+-00138         }
+-00139         return 1;
+-00140 }
+-00141 
+-00143 #ifdef DWC_UTE_CFI
+-00144 uint8_t *cfiw_ep_alloc_buffer(dwc_otg_pcd_t * pcd, void *pep, dwc_dma_t * addr,
+-00145                               size_t buflen, int flags)
+-00146 {
+-00147         dwc_otg_pcd_ep_t *ep;
+-00148         ep = get_ep_from_handle(pcd, pep);
+-00149         return pcd->cfi->ops.ep_alloc_buf(pcd->cfi, pcd, ep, addr, buflen,
+-00150                                           flags);
+-00151 }
+-00152 #else
+-00153 uint8_t *cfiw_ep_alloc_buffer(dwc_otg_pcd_t * pcd, void *pep, dwc_dma_t * addr,
+-00154                               size_t buflen, int flags);
+-00155 #endif
+-00156 
+-00163 static int32_t dwc_otg_pcd_resume_cb(void *p)
+-00164 {
+-00165         dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *) p;
+-00166 
+-00167         if (pcd->fops->resume) {
+-00168                 pcd->fops->resume(pcd);
+-00169         }
+-00170 
+-00171         /* Stop the SRP timeout timer. */
+-00172         if ((GET_CORE_IF(pcd)->core_params->phy_type != DWC_PHY_TYPE_PARAM_FS)
+-00173             || (!GET_CORE_IF(pcd)->core_params->i2c_enable)) {
+-00174                 if (GET_CORE_IF(pcd)->srp_timer_started) {
+-00175                         GET_CORE_IF(pcd)->srp_timer_started = 0;
+-00176                         DWC_TIMER_CANCEL(pcd->srp_timer);
+-00177                 }
+-00178         }
+-00179         return 1;
+-00180 }
+-00181 
+-00187 static int32_t dwc_otg_pcd_suspend_cb(void *p)
+-00188 {
+-00189         dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *) p;
+-00190 
+-00191         if (pcd->fops->suspend) {
+-00192                 pcd->fops->suspend(pcd);
+-00193         }
+-00194 
+-00195         return 1;
+-00196 }
+-00197 
+-00204 static int32_t dwc_otg_pcd_stop_cb(void *p)
+-00205 {
+-00206         dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *) p;
+-00207         extern void dwc_otg_pcd_stop(dwc_otg_pcd_t * _pcd);
+-00208 
+-00209         dwc_otg_pcd_stop(pcd);
+-00210         return 1;
+-00211 }
+-00212 
+-00216 static dwc_otg_cil_callbacks_t pcd_callbacks = {
+-00217         .start = dwc_otg_pcd_start_cb,
+-00218         .stop = dwc_otg_pcd_stop_cb,
+-00219         .suspend = dwc_otg_pcd_suspend_cb,
+-00220         .resume_wakeup = dwc_otg_pcd_resume_cb,
+-00221         .p = 0,                 /* Set at registration */
+-00222 };
+-00223 
+-00228 dwc_otg_dev_dma_desc_t *dwc_otg_ep_alloc_desc_chain(uint32_t * dma_desc_addr,
+-00229                                                 uint32_t count)
+-00230 {
+-00231 
+-00232         return dwc_dma_alloc(count * sizeof(dwc_otg_dev_dma_desc_t), dma_desc_addr);
+-00233 }
+-00234 
+-00238 void dwc_otg_ep_free_desc_chain(dwc_otg_dev_dma_desc_t * desc_addr,
+-00239                                 uint32_t dma_desc_addr, uint32_t count)
+-00240 {
+-00241         dwc_dma_free(count * sizeof(dwc_otg_dev_dma_desc_t), desc_addr,
+-00242                      dma_desc_addr);
+-00243 }
+-00244 
+-00245 #ifdef DWC_EN_ISOC
+-00246 
+-00254 void dwc_otg_iso_ep_start_ddma_transfer(dwc_otg_core_if_t * core_if,
+-00255                                         dwc_ep_t * dwc_ep)
+-00256 {
+-00257 
+-00258         dsts_data_t dsts = {.d32 = 0 };
+-00259         depctl_data_t depctl = {.d32 = 0 };
+-00260         volatile uint32_t *addr;
+-00261         int i, j;
+-00262 
+-00263         if (dwc_ep->is_in)
+-00264                 dwc_ep->desc_cnt = dwc_ep->buf_proc_intrvl / dwc_ep->bInterval;
+-00265         else
+-00266                 dwc_ep->desc_cnt =
+-00267                     dwc_ep->buf_proc_intrvl * dwc_ep->pkt_per_frm /
+-00268                     dwc_ep->bInterval;
+-00269 
+-00271         dwc_ep->iso_desc_addr =
+-00272             dwc_otg_ep_alloc_desc_chain(&dwc_ep->iso_dma_desc_addr,
+-00273                                         dwc_ep->desc_cnt * 2);
+-00274         if (dwc_ep->desc_addr) {
+-00275                 DWC_WARN("%s, can't allocate DMA descriptor chain\n", __func__);
+-00276                 return;
+-00277         }
+-00278 
+-00279         dsts.d32 = dwc_read_reg32(&core_if->dev_if->dev_global_regs->dsts);
+-00280 
+-00282         if (dwc_ep->is_in == 0) {
+-00283                 dev_dma_desc_sts_t sts = {.d32 = 0 };
+-00284                 dwc_otg_dev_dma_desc_t *dma_desc = dwc_ep->iso_desc_addr;
+-00285                 dma_addr_t dma_ad;
+-00286                 uint32_t data_per_desc;
+-00287                 dwc_otg_dev_out_ep_regs_t *out_regs =
+-00288                     core_if->dev_if->out_ep_regs[dwc_ep->num];
+-00289                 int offset;
+-00290 
+-00291                 addr = &core_if->dev_if->out_ep_regs[dwc_ep->num]->doepctl;
+-00292                 dma_ad = (dma_addr_t) dwc_read_reg32(&(out_regs->doepdma));
+-00293 
+-00295                 dma_ad = dwc_ep->dma_addr0;
+-00296 
+-00297                 sts.b_iso_out.bs = BS_HOST_READY;
+-00298                 sts.b_iso_out.rxsts = 0;
+-00299                 sts.b_iso_out.l = 0;
+-00300                 sts.b_iso_out.sp = 0;
+-00301                 sts.b_iso_out.ioc = 0;
+-00302                 sts.b_iso_out.pid = 0;
+-00303                 sts.b_iso_out.framenum = 0;
+-00304 
+-00305                 offset = 0;
+-00306                 for (i = 0; i < dwc_ep->desc_cnt - dwc_ep->pkt_per_frm;
+-00307                      i += dwc_ep->pkt_per_frm) {
+-00308 
+-00309                         for (j = 0; j < dwc_ep->pkt_per_frm; ++j) {
+-00310                                 data_per_desc =
+-00311                                     ((j + 1) * dwc_ep->maxpacket >
+-00312                                      dwc_ep->data_per_frame) ? dwc_ep->
+-00313                                     data_per_frame -
+-00314                                     j * dwc_ep->maxpacket : dwc_ep->maxpacket;
+-00315 
+-00316                                 data_per_desc +=
+-00317                                     (data_per_desc % 4) ? (4 -
+-00318                                                            data_per_desc %
+-00319                                                            4) : 0;
+-00320                                 sts.b_iso_out.rxbytes = data_per_desc;
+-00321                                 dma_desc->buf = dma_ad;
+-00322                                 dma_desc->status.d32 = sts.d32;
+-00323 
+-00324                                 offset += data_per_desc;
+-00325                                 dma_desc++;
+-00326                                 dma_ad += data_per_desc;
+-00327                         }
+-00328                 }
+-00329 
+-00330                 for (j = 0; j < dwc_ep->pkt_per_frm - 1; ++j) {
+-00331                         data_per_desc =
+-00332                             ((j + 1) * dwc_ep->maxpacket >
+-00333                              dwc_ep->data_per_frame) ? dwc_ep->data_per_frame -
+-00334                             j * dwc_ep->maxpacket : dwc_ep->maxpacket;
+-00335                         data_per_desc +=
+-00336                             (data_per_desc % 4) ? (4 - data_per_desc % 4) : 0;
+-00337                         sts.b_iso_out.rxbytes = data_per_desc;
+-00338                         dma_desc->buf = dma_ad;
+-00339                         dma_desc->status.d32 = sts.d32;
+-00340 
+-00341                         offset += data_per_desc;
+-00342                         dma_desc++;
+-00343                         dma_ad += data_per_desc;
+-00344                 }
+-00345 
+-00346                 sts.b_iso_out.ioc = 1;
+-00347                 data_per_desc =
+-00348                     ((j + 1) * dwc_ep->maxpacket >
+-00349                      dwc_ep->data_per_frame) ? dwc_ep->data_per_frame -
+-00350                     j * dwc_ep->maxpacket : dwc_ep->maxpacket;
+-00351                 data_per_desc +=
+-00352                     (data_per_desc % 4) ? (4 - data_per_desc % 4) : 0;
+-00353                 sts.b_iso_out.rxbytes = data_per_desc;
+-00354 
+-00355                 dma_desc->buf = dma_ad;
+-00356                 dma_desc->status.d32 = sts.d32;
+-00357                 dma_desc++;
+-00358 
+-00360                 sts.b_iso_out.ioc = 0;
+-00361                 dma_ad = dwc_ep->dma_addr1;
+-00362 
+-00363                 offset = 0;
+-00364                 for (i = 0; i < dwc_ep->desc_cnt - dwc_ep->pkt_per_frm;
+-00365                      i += dwc_ep->pkt_per_frm) {
+-00366                         for (j = 0; j < dwc_ep->pkt_per_frm; ++j) {
+-00367                                 data_per_desc =
+-00368                                     ((j + 1) * dwc_ep->maxpacket >
+-00369                                      dwc_ep->data_per_frame) ? dwc_ep->
+-00370                                     data_per_frame -
+-00371                                     j * dwc_ep->maxpacket : dwc_ep->maxpacket;
+-00372                                 data_per_desc +=
+-00373                                     (data_per_desc % 4) ? (4 -
+-00374                                                            data_per_desc %
+-00375                                                            4) : 0;
+-00376                                 sts.b_iso_out.rxbytes = data_per_desc;
+-00377                                 dma_desc->buf = dma_ad;
+-00378                                 dma_desc->status.d32 = sts.d32;
+-00379 
+-00380                                 offset += data_per_desc;
+-00381                                 dma_desc++;
+-00382                                 dma_ad += data_per_desc;
+-00383                         }
+-00384                 }
+-00385                 for (j = 0; j < dwc_ep->pkt_per_frm - 1; ++j) {
+-00386                         data_per_desc =
+-00387                             ((j + 1) * dwc_ep->maxpacket >
+-00388                              dwc_ep->data_per_frame) ? dwc_ep->data_per_frame -
+-00389                             j * dwc_ep->maxpacket : dwc_ep->maxpacket;
+-00390                         data_per_desc +=
+-00391                             (data_per_desc % 4) ? (4 - data_per_desc % 4) : 0;
+-00392                         sts.b_iso_out.rxbytes = data_per_desc;
+-00393                         dma_desc->buf = dma_ad;
+-00394                         dma_desc->status.d32 = sts.d32;
+-00395 
+-00396                         offset += data_per_desc;
+-00397                         dma_desc++;
+-00398                         dma_ad += data_per_desc;
+-00399                 }
+-00400 
+-00401                 sts.b_iso_out.ioc = 1;
+-00402                 sts.b_iso_out.l = 1;
+-00403                 data_per_desc =
+-00404                     ((j + 1) * dwc_ep->maxpacket >
+-00405                      dwc_ep->data_per_frame) ? dwc_ep->data_per_frame -
+-00406                     j * dwc_ep->maxpacket : dwc_ep->maxpacket;
+-00407                 data_per_desc +=
+-00408                     (data_per_desc % 4) ? (4 - data_per_desc % 4) : 0;
+-00409                 sts.b_iso_out.rxbytes = data_per_desc;
+-00410 
+-00411                 dma_desc->buf = dma_ad;
+-00412                 dma_desc->status.d32 = sts.d32;
+-00413 
+-00414                 dwc_ep->next_frame = 0;
+-00415 
+-00417                 dwc_write_reg32(&(out_regs->doepdma),
+-00418                                 (uint32_t) dwc_ep->iso_dma_desc_addr);
+-00419 
+-00420         }
+-00422         else {
+-00423                 dev_dma_desc_sts_t sts = {.d32 = 0 };
+-00424                 dwc_otg_dev_dma_desc_t *dma_desc = dwc_ep->iso_desc_addr;
+-00425                 dma_addr_t dma_ad;
+-00426                 dwc_otg_dev_in_ep_regs_t *in_regs =
+-00427                     core_if->dev_if->in_ep_regs[dwc_ep->num];
+-00428                 unsigned int frmnumber;
+-00429                 fifosize_data_t txfifosize, rxfifosize;
+-00430 
+-00431                 txfifosize.d32 =
+-00432                     dwc_read_reg32(&core_if->dev_if->in_ep_regs[dwc_ep->num]->
+-00433                                    dtxfsts);
+-00434                 rxfifosize.d32 =
+-00435                     dwc_read_reg32(&core_if->core_global_regs->grxfsiz);
+-00436 
+-00437                 addr = &core_if->dev_if->in_ep_regs[dwc_ep->num]->diepctl;
+-00438 
+-00439                 dma_ad = dwc_ep->dma_addr0;
+-00440 
+-00441                 dsts.d32 =
+-00442                     dwc_read_reg32(&core_if->dev_if->dev_global_regs->dsts);
+-00443 
+-00444                 sts.b_iso_in.bs = BS_HOST_READY;
+-00445                 sts.b_iso_in.txsts = 0;
+-00446                 sts.b_iso_in.sp =
+-00447                     (dwc_ep->data_per_frame % dwc_ep->maxpacket) ? 1 : 0;
+-00448                 sts.b_iso_in.ioc = 0;
+-00449                 sts.b_iso_in.pid = dwc_ep->pkt_per_frm;
+-00450 
+-00451                 frmnumber = dwc_ep->next_frame;
+-00452 
+-00453                 sts.b_iso_in.framenum = frmnumber;
+-00454                 sts.b_iso_in.txbytes = dwc_ep->data_per_frame;
+-00455                 sts.b_iso_in.l = 0;
+-00456 
+-00458                 for (i = 0; i < dwc_ep->desc_cnt - 1; i++) {
+-00459                         dma_desc->buf = dma_ad;
+-00460                         dma_desc->status.d32 = sts.d32;
+-00461                         dma_desc++;
+-00462 
+-00463                         dma_ad += dwc_ep->data_per_frame;
+-00464                         sts.b_iso_in.framenum += dwc_ep->bInterval;
+-00465                 }
+-00466 
+-00467                 sts.b_iso_in.ioc = 1;
+-00468                 dma_desc->buf = dma_ad;
+-00469                 dma_desc->status.d32 = sts.d32;
+-00470                 ++dma_desc;
+-00471 
+-00473                 sts.b_iso_in.ioc = 0;
+-00474                 dma_ad = dwc_ep->dma_addr1;
+-00475 
+-00476                 for (i = 0; i < dwc_ep->desc_cnt - dwc_ep->pkt_per_frm;
+-00477                      i += dwc_ep->pkt_per_frm) {
+-00478                         dma_desc->buf = dma_ad;
+-00479                         dma_desc->status.d32 = sts.d32;
+-00480                         dma_desc++;
+-00481 
+-00482                         dma_ad += dwc_ep->data_per_frame;
+-00483                         sts.b_iso_in.framenum += dwc_ep->bInterval;
+-00484 
+-00485                         sts.b_iso_in.ioc = 0;
+-00486                 }
+-00487                 sts.b_iso_in.ioc = 1;
+-00488                 sts.b_iso_in.l = 1;
+-00489 
+-00490                 dma_desc->buf = dma_ad;
+-00491                 dma_desc->status.d32 = sts.d32;
+-00492 
+-00493                 dwc_ep->next_frame = sts.b_iso_in.framenum + dwc_ep->bInterval;
+-00494 
+-00496                 dwc_write_reg32(&(in_regs->diepdma),
+-00497                                 (uint32_t) dwc_ep->iso_dma_desc_addr);
+-00498         }
+-00500         depctl.d32 = 0;
+-00501         depctl.b.epena = 1;
+-00502         depctl.b.usbactep = 1;
+-00503         depctl.b.cnak = 1;
+-00504 
+-00505         dwc_modify_reg32(addr, depctl.d32, depctl.d32);
+-00506         depctl.d32 = dwc_read_reg32(addr);
+-00507 }
+-00508 
+-00517 void dwc_otg_iso_ep_start_buf_transfer(dwc_otg_core_if_t * core_if,
+-00518                                        dwc_ep_t * ep)
+-00519 {
+-00520         depctl_data_t depctl = {.d32 = 0 };
+-00521         volatile uint32_t *addr;
+-00522 
+-00523         if (ep->is_in) {
+-00524                 addr = &core_if->dev_if->in_ep_regs[ep->num]->diepctl;
+-00525         } else {
+-00526                 addr = &core_if->dev_if->out_ep_regs[ep->num]->doepctl;
+-00527         }
+-00528 
+-00529         if (core_if->dma_enable == 0 || core_if->dma_desc_enable != 0) {
+-00530                 return;
+-00531         } else {
+-00532                 deptsiz_data_t deptsiz = {.d32 = 0 };
+-00533 
+-00534                 ep->xfer_len =
+-00535                     ep->data_per_frame * ep->buf_proc_intrvl / ep->bInterval;
+-00536                 ep->pkt_cnt =
+-00537                     (ep->xfer_len - 1 + ep->maxpacket) / ep->maxpacket;
+-00538                 ep->xfer_count = 0;
+-00539                 ep->xfer_buff =
+-00540                     (ep->proc_buf_num) ? ep->xfer_buff1 : ep->xfer_buff0;
+-00541                 ep->dma_addr =
+-00542                     (ep->proc_buf_num) ? ep->dma_addr1 : ep->dma_addr0;
+-00543 
+-00544                 if (ep->is_in) {
+-00545                         /* Program the transfer size and packet count
+-00546                          *      as follows: xfersize = N * maxpacket +
+-00547                          *      short_packet pktcnt = N + (short_packet
+-00548                          *      exist ? 1 : 0)  
+-00549                          */
+-00550                         deptsiz.b.mc = ep->pkt_per_frm;
+-00551                         deptsiz.b.xfersize = ep->xfer_len;
+-00552                         deptsiz.b.pktcnt =
+-00553                             (ep->xfer_len - 1 + ep->maxpacket) / ep->maxpacket;
+-00554                         dwc_write_reg32(&core_if->dev_if->in_ep_regs[ep->num]->
+-00555                                         dieptsiz, deptsiz.d32);
+-00556 
+-00557                         /* Write the DMA register */
+-00558                         dwc_write_reg32(&
+-00559                                         (core_if->dev_if->in_ep_regs[ep->num]->
+-00560                                          diepdma), (uint32_t) ep->dma_addr);
+-00561 
+-00562                 } else {
+-00563                         deptsiz.b.pktcnt =
+-00564                             (ep->xfer_len + (ep->maxpacket - 1)) /
+-00565                             ep->maxpacket;
+-00566                         deptsiz.b.xfersize = deptsiz.b.pktcnt * ep->maxpacket;
+-00567 
+-00568                         dwc_write_reg32(&core_if->dev_if->out_ep_regs[ep->num]->
+-00569                                         doeptsiz, deptsiz.d32);
+-00570 
+-00571                         /* Write the DMA register */
+-00572                         dwc_write_reg32(&
+-00573                                         (core_if->dev_if->out_ep_regs[ep->num]->
+-00574                                          doepdma), (uint32_t) ep->dma_addr);
+-00575 
+-00576                 }
+-00578                 depctl.d32 = 0;
+-00579                 dwc_modify_reg32(addr, depctl.d32, depctl.d32);
+-00580 
+-00581                 depctl.b.epena = 1;
+-00582                 depctl.b.cnak = 1;
+-00583 
+-00584                 dwc_modify_reg32(addr, depctl.d32, depctl.d32);
+-00585         }
+-00586 }
+-00587 
+-00598 static void dwc_otg_iso_ep_start_transfer(dwc_otg_core_if_t * core_if,
+-00599                                           dwc_ep_t * ep)
+-00600 {
+-00601         if (core_if->dma_enable) {
+-00602                 if (core_if->dma_desc_enable) {
+-00603                         if (ep->is_in) {
+-00604                                 ep->desc_cnt = ep->pkt_cnt / ep->pkt_per_frm;
+-00605                         } else {
+-00606                                 ep->desc_cnt = ep->pkt_cnt;
+-00607                         }
+-00608                         dwc_otg_iso_ep_start_ddma_transfer(core_if, ep);
+-00609                 } else {
+-00610                         if (core_if->pti_enh_enable) {
+-00611                                 dwc_otg_iso_ep_start_buf_transfer(core_if, ep);
+-00612                         } else {
+-00613                                 ep->cur_pkt_addr =
+-00614                                     (ep->proc_buf_num) ? ep->xfer_buff1 : ep->
+-00615                                     xfer_buff0;
+-00616                                 ep->cur_pkt_dma_addr =
+-00617                                     (ep->proc_buf_num) ? ep->dma_addr1 : ep->
+-00618                                     dma_addr0;
+-00619                                 dwc_otg_iso_ep_start_frm_transfer(core_if, ep);
+-00620                         }
+-00621                 }
+-00622         } else {
+-00623                 ep->cur_pkt_addr =
+-00624                     (ep->proc_buf_num) ? ep->xfer_buff1 : ep->xfer_buff0;
+-00625                 ep->cur_pkt_dma_addr =
+-00626                     (ep->proc_buf_num) ? ep->dma_addr1 : ep->dma_addr0;
+-00627                 dwc_otg_iso_ep_start_frm_transfer(core_if, ep);
+-00628         }
+-00629 }
+-00630 
+-00641 void dwc_otg_iso_ep_stop_transfer(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
+-00642 {
+-00643         depctl_data_t depctl = {.d32 = 0 };
+-00644         volatile uint32_t *addr;
+-00645 
+-00646         if (ep->is_in == 1) {
+-00647                 addr = &core_if->dev_if->in_ep_regs[ep->num]->diepctl;
+-00648         } else {
+-00649                 addr = &core_if->dev_if->out_ep_regs[ep->num]->doepctl;
+-00650         }
+-00651 
+-00652         /* disable the ep */
+-00653         depctl.d32 = dwc_read_reg32(addr);
+-00654 
+-00655         depctl.b.epdis = 1;
+-00656         depctl.b.snak = 1;
+-00657 
+-00658         dwc_write_reg32(addr, depctl.d32);
+-00659 
+-00660         if (core_if->dma_desc_enable &&
+-00661             ep->iso_desc_addr && ep->iso_dma_desc_addr) {
+-00662                 dwc_otg_ep_free_desc_chain(ep->iso_desc_addr,
+-00663                                            ep->iso_dma_desc_addr,
+-00664                                            ep->desc_cnt * 2);
+-00665         }
+-00666 
+-00667         /* reset varibales */
+-00668         ep->dma_addr0 = 0;
+-00669         ep->dma_addr1 = 0;
+-00670         ep->xfer_buff0 = 0;
+-00671         ep->xfer_buff1 = 0;
+-00672         ep->data_per_frame = 0;
+-00673         ep->data_pattern_frame = 0;
+-00674         ep->sync_frame = 0;
+-00675         ep->buf_proc_intrvl = 0;
+-00676         ep->bInterval = 0;
+-00677         ep->proc_buf_num = 0;
+-00678         ep->pkt_per_frm = 0;
+-00679         ep->pkt_per_frm = 0;
+-00680         ep->desc_cnt = 0;
+-00681         ep->iso_desc_addr = 0;
+-00682         ep->iso_dma_desc_addr = 0;
+-00683 }
+-00684 
+-00685 int dwc_otg_pcd_iso_ep_start(dwc_otg_pcd_t * pcd, void *ep_handle,
+-00686                              uint8_t * buf0, uint8_t * buf1, dwc_dma_t dma0,
+-00687                              dwc_dma_t dma1, int sync_frame, int dp_frame,
+-00688                              int data_per_frame, int start_frame,
+-00689                              int buf_proc_intrvl, void *req_handle,
+-00690                              int atomic_alloc)
+-00691 {
+-00692         dwc_otg_pcd_ep_t *ep;
+-00693         uint64_t flags = 0;
+-00694         dwc_ep_t *dwc_ep;
+-00695         int32_t frm_data;
+-00696         dsts_data_t dsts;
+-00697         dwc_otg_core_if_t *core_if;
+-00698 
+-00699         ep = get_ep_from_handle(pcd, ep_handle);
+-00700 
+-00701         if (!ep->desc || ep->dwc_ep.num == 0) {
+-00702                 DWC_WARN("bad ep\n");
+-00703                 return -DWC_E_INVALID;
+-00704         }
+-00705 
+-00706         DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
+-00707         core_if = GET_CORE_IF(pcd);
+-00708         dwc_ep = &ep->dwc_ep;
+-00709 
+-00710         if (ep->iso_req_handle) {
+-00711                 DWC_WARN("ISO request in progress\n");
+-00712         }
+-00713 
+-00714         dwc_ep->dma_addr0 = dma0;
+-00715         dwc_ep->dma_addr1 = dma1;
+-00716 
+-00717         dwc_ep->xfer_buff0 = buf0;
+-00718         dwc_ep->xfer_buff1 = buf1;
+-00719 
+-00720         dwc_ep->data_per_frame = data_per_frame;
+-00721 
+-00723         dwc_ep->data_pattern_frame = dp_frame;
+-00724         dwc_ep->sync_frame = sync_frame;
+-00725 
+-00726         dwc_ep->buf_proc_intrvl = buf_proc_intrvl;
+-00727 
+-00728         dwc_ep->bInterval = 1 << (ep->desc->bInterval - 1);
+-00729 
+-00730         dwc_ep->proc_buf_num = 0;
+-00731 
+-00732         dwc_ep->pkt_per_frm = 0;
+-00733         frm_data = ep->dwc_ep.data_per_frame;
+-00734         while (frm_data > 0) {
+-00735                 dwc_ep->pkt_per_frm++;
+-00736                 frm_data -= ep->dwc_ep.maxpacket;
+-00737         }
+-00738 
+-00739         dsts.d32 = dwc_read_reg32(&core_if->dev_if->dev_global_regs->dsts);
+-00740 
+-00741         if (start_frame == -1) {
+-00742                 dwc_ep->next_frame = dsts.b.soffn + 1;
+-00743                 if (dwc_ep->bInterval != 1) {
+-00744                         dwc_ep->next_frame =
+-00745                             dwc_ep->next_frame + (dwc_ep->bInterval - 1 -
+-00746                                                   dwc_ep->next_frame %
+-00747                                                   dwc_ep->bInterval);
+-00748                 }
+-00749         } else {
+-00750                 dwc_ep->next_frame = start_frame;
+-00751         }
+-00752 
+-00753         if (!core_if->pti_enh_enable) {
+-00754                 dwc_ep->pkt_cnt =
+-00755                     dwc_ep->buf_proc_intrvl * dwc_ep->pkt_per_frm /
+-00756                     dwc_ep->bInterval;
+-00757         } else {
+-00758                 dwc_ep->pkt_cnt =
+-00759                     (dwc_ep->data_per_frame *
+-00760                      (dwc_ep->buf_proc_intrvl / dwc_ep->bInterval)
+-00761                      - 1 + dwc_ep->maxpacket) / dwc_ep->maxpacket;
+-00762         }
+-00763 
+-00764         if (core_if->dma_desc_enable) {
+-00765                 dwc_ep->desc_cnt =
+-00766                     dwc_ep->buf_proc_intrvl * dwc_ep->pkt_per_frm /
+-00767                     dwc_ep->bInterval;
+-00768         }
+-00769 
+-00770         if (atomic_alloc) {
+-00771                 dwc_ep->pkt_info =
+-00772                     dwc_alloc_atomic(sizeof(iso_pkt_info_t) * dwc_ep->pkt_cnt);
+-00773         } else {
+-00774                 dwc_ep->pkt_info =
+-00775                     dwc_alloc(sizeof(iso_pkt_info_t) * dwc_ep->pkt_cnt);
+-00776         }
+-00777         if (!dwc_ep->pkt_info) {
+-00778                 DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
+-00779                 return -DWC_E_NO_MEMORY;
+-00780         }
+-00781         if (core_if->pti_enh_enable) {
+-00782                 dwc_memset(dwc_ep->pkt_info, 0,
+-00783                            sizeof(iso_pkt_info_t) * dwc_ep->pkt_cnt);
+-00784         }
+-00785 
+-00786         dwc_ep->cur_pkt = 0;
+-00787         ep->iso_req_handle = req_handle;
+-00788 
+-00789         DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
+-00790         dwc_otg_iso_ep_start_transfer(core_if, dwc_ep);
+-00791         return 0;
+-00792 }
+-00793 
+-00794 int dwc_otg_pcd_iso_ep_stop(dwc_otg_pcd_t * pcd, void *ep_handle,
+-00795                             void *req_handle)
+-00796 {
+-00797         uint64_t flags = 0;
+-00798         dwc_otg_pcd_ep_t *ep;
+-00799         dwc_ep_t *dwc_ep;
+-00800 
+-00801         ep = get_ep_from_handle(pcd, ep_handle);
+-00802         if (!ep || !ep->desc || ep->dwc_ep.num == 0) {
+-00803                 DWC_WARN("bad ep\n");
+-00804                 return -DWC_E_INVALID;
+-00805         }
+-00806         dwc_ep = &ep->dwc_ep;
+-00807 
+-00808         dwc_otg_iso_ep_stop_transfer(GET_CORE_IF(pcd), dwc_ep);
+-00809 
+-00810         dwc_free(dwc_ep->pkt_info);
+-00811         DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
+-00812         if (ep->iso_req_handle != req_handle) {
+-00813                 DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
+-00814                 return -DWC_E_INVALID;
+-00815         }
+-00816 
+-00817         DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
+-00818 
+-00819         ep->iso_req_handle = 0;
+-00820         return 0;
+-00821 }
+-00822 
+-00830 void dwc_otg_iso_buffer_done(dwc_otg_pcd_t * pcd, dwc_otg_pcd_ep_t * ep,
+-00831                              void *req_handle)
+-00832 {
+-00833         int i;
+-00834         dwc_ep_t *dwc_ep;
+-00835 
+-00836         dwc_ep = &ep->dwc_ep;
+-00837 
+-00838         DWC_SPINUNLOCK(ep->pcd->lock);
+-00839         pcd->fops->isoc_complete(pcd, ep->priv, ep->iso_req_handle,
+-00840                                  dwc_ep->proc_buf_num ^ 0x1);
+-00841         DWC_SPINLOCK(ep->pcd->lock);
+-00842 
+-00843         for (i = 0; i < dwc_ep->pkt_cnt; ++i) {
+-00844                 dwc_ep->pkt_info[i].status = 0;
+-00845                 dwc_ep->pkt_info[i].offset = 0;
+-00846                 dwc_ep->pkt_info[i].length = 0;
+-00847         }
+-00848 }
+-00849 
+-00850 int dwc_otg_pcd_get_iso_packet_count(dwc_otg_pcd_t * pcd, void *ep_handle,
+-00851                                      void *iso_req_handle)
+-00852 {
+-00853         dwc_otg_pcd_ep_t *ep;
+-00854         dwc_ep_t *dwc_ep;
+-00855 
+-00856         ep = get_ep_from_handle(pcd, ep_handle);
+-00857         dwc_ep = &ep->dwc_ep;
+-00858 
+-00859         return dwc_ep->pkt_cnt;
+-00860 }
+-00861 
+-00862 void dwc_otg_pcd_get_iso_packet_params(dwc_otg_pcd_t * pcd, void *ep_handle,
+-00863                                        void *iso_req_handle, int packet,
+-00864                                        int *status, int *actual, int *offset)
+-00865 {
+-00866         dwc_otg_pcd_ep_t *ep;
+-00867         dwc_ep_t *dwc_ep;
+-00868 
+-00869         ep = get_ep_from_handle(pcd, ep_handle);
+-00870         dwc_ep = &ep->dwc_ep;
+-00871 
+-00872         *status = dwc_ep->pkt_info[packet].status;
+-00873         *actual = dwc_ep->pkt_info[packet].length;
+-00874         *offset = dwc_ep->pkt_info[packet].offset;
+-00875 }
+-00876 
+-00877 #endif                          /* DWC_EN_ISOC */
+-00878 
+-00879 static void dwc_otg_pcd_init_ep(dwc_otg_pcd_t * pcd, dwc_otg_pcd_ep_t * pcd_ep,
+-00880                                 uint32_t is_in, uint32_t ep_num)
+-00881 {
+-00882         /* Init EP structure */
+-00883         pcd_ep->desc = 0;
+-00884         pcd_ep->pcd = pcd;
+-00885         pcd_ep->stopped = 1;
+-00886         pcd_ep->queue_sof = 0;
+-00887 
+-00888         /* Init DWC ep structure */
+-00889         pcd_ep->dwc_ep.is_in = is_in;
+-00890         pcd_ep->dwc_ep.num = ep_num;
+-00891         pcd_ep->dwc_ep.active = 0;
+-00892         pcd_ep->dwc_ep.tx_fifo_num = 0;
+-00893         /* Control until ep is actvated */
+-00894         pcd_ep->dwc_ep.type = DWC_OTG_EP_TYPE_CONTROL;
+-00895         pcd_ep->dwc_ep.maxpacket = MAX_PACKET_SIZE;
+-00896         pcd_ep->dwc_ep.dma_addr = 0;
+-00897         pcd_ep->dwc_ep.start_xfer_buff = 0;
+-00898         pcd_ep->dwc_ep.xfer_buff = 0;
+-00899         pcd_ep->dwc_ep.xfer_len = 0;
+-00900         pcd_ep->dwc_ep.xfer_count = 0;
+-00901         pcd_ep->dwc_ep.sent_zlp = 0;
+-00902         pcd_ep->dwc_ep.total_len = 0;
+-00903         pcd_ep->dwc_ep.desc_addr = 0;
+-00904         pcd_ep->dwc_ep.dma_desc_addr = 0;
+-00905         DWC_CIRCLEQ_INIT(&pcd_ep->queue);
+-00906 }
+-00907 
+-00911 static void dwc_otg_pcd_reinit(dwc_otg_pcd_t * pcd)
+-00912 {
+-00913         int i;
+-00914         uint32_t hwcfg1;
+-00915         dwc_otg_pcd_ep_t *ep;
+-00916         int in_ep_cntr, out_ep_cntr;
+-00917         uint32_t num_in_eps = (GET_CORE_IF(pcd))->dev_if->num_in_eps;
+-00918         uint32_t num_out_eps = (GET_CORE_IF(pcd))->dev_if->num_out_eps;
+-00919 
+-00923         ep = &pcd->ep0;
+-00924         dwc_otg_pcd_init_ep(pcd, ep, 0, 0);
+-00925 
+-00926         in_ep_cntr = 0;
+-00927         hwcfg1 = (GET_CORE_IF(pcd))->hwcfg1.d32 >> 3;
+-00928         for (i = 1; in_ep_cntr < num_in_eps; i++) {
+-00929                 if ((hwcfg1 & 0x1) == 0) {
+-00930                         dwc_otg_pcd_ep_t *ep = &pcd->in_ep[in_ep_cntr];
+-00931                         in_ep_cntr++;
+-00937                         dwc_otg_pcd_init_ep(pcd, ep, 1 /* IN */ , i);
+-00938 
+-00939                         DWC_CIRCLEQ_INIT(&ep->queue);
+-00940                 }
+-00941                 hwcfg1 >>= 2;
+-00942         }
+-00943 
+-00944         out_ep_cntr = 0;
+-00945         hwcfg1 = (GET_CORE_IF(pcd))->hwcfg1.d32 >> 2;
+-00946         for (i = 1; out_ep_cntr < num_out_eps; i++) {
+-00947                 if ((hwcfg1 & 0x1) == 0) {
+-00948                         dwc_otg_pcd_ep_t *ep = &pcd->out_ep[out_ep_cntr];
+-00949                         out_ep_cntr++;
+-00955                         dwc_otg_pcd_init_ep(pcd, ep, 0 /* OUT */ , i);
+-00956                         DWC_CIRCLEQ_INIT(&ep->queue);
+-00957                 }
+-00958                 hwcfg1 >>= 2;
+-00959         }
+-00960 
+-00961         pcd->ep0state = EP0_DISCONNECT;
+-00962         pcd->ep0.dwc_ep.maxpacket = MAX_EP0_SIZE;
+-00963         pcd->ep0.dwc_ep.type = DWC_OTG_EP_TYPE_CONTROL;
+-00964 }
+-00965 
+-00970 static void srp_timeout(void *ptr)
+-00971 {
+-00972         gotgctl_data_t gotgctl;
+-00973         dwc_otg_core_if_t *core_if = (dwc_otg_core_if_t *) ptr;
+-00974         volatile uint32_t *addr = &core_if->core_global_regs->gotgctl;
+-00975 
+-00976         gotgctl.d32 = dwc_read_reg32(addr);
+-00977 
+-00978         core_if->srp_timer_started = 0;
+-00979 
+-00980         if ((core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS) &&
+-00981             (core_if->core_params->i2c_enable)) {
+-00982                 DWC_PRINTF("SRP Timeout\n");
+-00983 
+-00984                 if ((core_if->srp_success) && (gotgctl.b.bsesvld)) {
+-00985                         if (core_if->pcd_cb && core_if->pcd_cb->resume_wakeup) {
+-00986                                 core_if->pcd_cb->resume_wakeup(core_if->pcd_cb->
+-00987                                                                p);
+-00988                         }
+-00989 
+-00990                         /* Clear Session Request */
+-00991                         gotgctl.d32 = 0;
+-00992                         gotgctl.b.sesreq = 1;
+-00993                         dwc_modify_reg32(&core_if->core_global_regs->gotgctl,
+-00994                                          gotgctl.d32, 0);
+-00995 
+-00996                         core_if->srp_success = 0;
+-00997                 } else {
+-00998                         __DWC_ERROR("Device not connected/responding\n");
+-00999                         gotgctl.b.sesreq = 0;
+-01000                         dwc_write_reg32(addr, gotgctl.d32);
+-01001                 }
+-01002         } else if (gotgctl.b.sesreq) {
+-01003                 DWC_PRINTF("SRP Timeout\n");
+-01004 
+-01005                 __DWC_ERROR("Device not connected/responding\n");
+-01006                 gotgctl.b.sesreq = 0;
+-01007                 dwc_write_reg32(addr, gotgctl.d32);
+-01008         } else {
+-01009                 DWC_PRINTF(" SRP GOTGCTL=%0x\n", gotgctl.d32);
+-01010         }
+-01011 }
+-01012 
+-01017 extern void start_next_request(dwc_otg_pcd_ep_t * ep);
+-01018 
+-01019 static void start_xfer_tasklet_func(void *data)
+-01020 {
+-01021         dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *) data;
+-01022         dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
+-01023 
+-01024         int i;
+-01025         depctl_data_t diepctl;
+-01026 
+-01027         DWC_DEBUGPL(DBG_PCDV, "Start xfer tasklet\n");
+-01028 
+-01029         diepctl.d32 = dwc_read_reg32(&core_if->dev_if->in_ep_regs[0]->diepctl);
+-01030 
+-01031         if (pcd->ep0.queue_sof) {
+-01032                 pcd->ep0.queue_sof = 0;
+-01033                 start_next_request(&pcd->ep0);
+-01034                 // break;
+-01035         }
+-01036 
+-01037         for (i = 0; i < core_if->dev_if->num_in_eps; i++) {
+-01038                 depctl_data_t diepctl;
+-01039                 diepctl.d32 =
+-01040                     dwc_read_reg32(&core_if->dev_if->in_ep_regs[i]->diepctl);
+-01041 
+-01042                 if (pcd->in_ep[i].queue_sof) {
+-01043                         pcd->in_ep[i].queue_sof = 0;
+-01044                         start_next_request(&pcd->in_ep[i]);
+-01045                         // break;
+-01046                 }
+-01047         }
+-01048 
+-01049         return;
+-01050 }
+-01051 
+-01056 dwc_otg_pcd_t *dwc_otg_pcd_init(dwc_otg_core_if_t * core_if)
+-01057 {
+-01058         dwc_otg_pcd_t *pcd = 0;
+-01059         dwc_otg_dev_if_t *dev_if;
+-01060 
+-01061         /*
+-01062          * Allocate PCD structure
+-01063          */
+-01064         pcd = dwc_alloc(sizeof(dwc_otg_pcd_t));
+-01065 
+-01066         if (pcd == 0) {
+-01067                 return NULL;
+-01068         }
+-01069 
+-01070         pcd->lock = DWC_SPINLOCK_ALLOC();
+-01071         pcd->core_if = core_if;
+-01072         if (!pcd->lock) {
+-01073                 DWC_ERROR("Could not allocate lock for pcd");
+-01074                 dwc_free(pcd);
+-01075                 return NULL;
+-01076         }
+-01077         dev_if = core_if->dev_if;
+-01078 
+-01079         if (core_if->hwcfg4.b.ded_fifo_en) {
+-01080                 DWC_PRINTF("Dedicated Tx FIFOs mode\n");
+-01081         } else {
+-01082                 DWC_PRINTF("Shared Tx FIFO mode\n");
+-01083         }
+-01084 
+-01085         /*
+-01086          * Initialized the Core for Device mode.
+-01087          */
+-01088         if (dwc_otg_is_device_mode(core_if)) {
+-01089                 dwc_otg_core_dev_init(core_if);
+-01090         }
+-01091 
+-01092         /*
+-01093          * Register the PCD Callbacks.
+-01094          */
+-01095         dwc_otg_cil_register_pcd_callbacks(core_if, &pcd_callbacks, pcd);
+-01096 
+-01097         /*
+-01098          * Initialize the DMA buffer for SETUP packets
+-01099          */
+-01100         if (GET_CORE_IF(pcd)->dma_enable) {
+-01101                 pcd->setup_pkt =
+-01102                     dwc_dma_alloc(sizeof(*pcd->setup_pkt) * 5,
+-01103                                   &pcd->setup_pkt_dma_handle);
+-01104                 if (pcd->setup_pkt == 0) {
+-01105                         dwc_free(pcd);
+-01106                         return NULL;
+-01107                 }
+-01108 
+-01109                 pcd->status_buf =
+-01110                     dwc_dma_alloc(sizeof(uint16_t),
+-01111                                   &pcd->status_buf_dma_handle);
+-01112                 if (pcd->status_buf == 0) {
+-01113                         dwc_dma_free(sizeof(*pcd->setup_pkt) * 5,
+-01114                                      pcd->setup_pkt, pcd->setup_pkt_dma_handle);
+-01115                         dwc_free(pcd);
+-01116                         return NULL;
+-01117                 }
+-01118 
+-01119                 if (GET_CORE_IF(pcd)->dma_desc_enable) {
+-01120                         dev_if->setup_desc_addr[0] =
+-01121                             dwc_otg_ep_alloc_desc_chain(&dev_if->
+-01122                                                         dma_setup_desc_addr[0],
+-01123                                                         1);
+-01124                         dev_if->setup_desc_addr[1] =
+-01125                             dwc_otg_ep_alloc_desc_chain(&dev_if->
+-01126                                                         dma_setup_desc_addr[1],
+-01127                                                         1);
+-01128                         dev_if->in_desc_addr =
+-01129                             dwc_otg_ep_alloc_desc_chain(&dev_if->
+-01130                                                         dma_in_desc_addr, 1);
+-01131                         dev_if->out_desc_addr =
+-01132                             dwc_otg_ep_alloc_desc_chain(&dev_if->
+-01133                                                         dma_out_desc_addr, 1);
+-01134 
+-01135                         if (dev_if->setup_desc_addr[0] == 0
+-01136                             || dev_if->setup_desc_addr[1] == 0
+-01137                             || dev_if->in_desc_addr == 0
+-01138                             || dev_if->out_desc_addr == 0) {
+-01139 
+-01140                                 if (dev_if->out_desc_addr)
+-01141                                         dwc_otg_ep_free_desc_chain(dev_if->
+-01142                                                                    out_desc_addr,
+-01143                                                                    dev_if->
+-01144                                                                    dma_out_desc_addr,
+-01145                                                                    1);
+-01146                                 if (dev_if->in_desc_addr)
+-01147                                         dwc_otg_ep_free_desc_chain(dev_if->
+-01148                                                                    in_desc_addr,
+-01149                                                                    dev_if->
+-01150                                                                    dma_in_desc_addr,
+-01151                                                                    1);
+-01152                                 if (dev_if->setup_desc_addr[1])
+-01153                                         dwc_otg_ep_free_desc_chain(dev_if->
+-01154                                                                    setup_desc_addr
+-01155                                                                    [1],
+-01156                                                                    dev_if->
+-01157                                                                    dma_setup_desc_addr
+-01158                                                                    [1], 1);
+-01159                                 if (dev_if->setup_desc_addr[0])
+-01160                                         dwc_otg_ep_free_desc_chain(dev_if->
+-01161                                                                    setup_desc_addr
+-01162                                                                    [0],
+-01163                                                                    dev_if->
+-01164                                                                    dma_setup_desc_addr
+-01165                                                                    [0], 1);
+-01166 
+-01167                                 dwc_dma_free(sizeof(*pcd->setup_pkt) * 5,
+-01168                                              pcd->setup_pkt,
+-01169                                              pcd->setup_pkt_dma_handle);
+-01170                                 dwc_dma_free(sizeof(*pcd->status_buf),
+-01171                                              pcd->status_buf,
+-01172                                              pcd->status_buf_dma_handle);
+-01173 
+-01174                                 dwc_free(pcd);
+-01175 
+-01176                                 return NULL;
+-01177                         }
+-01178                 }
+-01179         } else {
+-01180                 pcd->setup_pkt = dwc_alloc(sizeof(*pcd->setup_pkt) * 5);
+-01181                 if (pcd->setup_pkt == 0) {
+-01182                         dwc_free(pcd);
+-01183                         return NULL;
+-01184                 }
+-01185 
+-01186                 pcd->status_buf = dwc_alloc(sizeof(uint16_t));
+-01187                 if (pcd->status_buf == 0) {
+-01188                         dwc_free(pcd->setup_pkt);
+-01189                         dwc_free(pcd);
+-01190                         return NULL;
+-01191                 }
+-01192         }
+-01193 
+-01194         dwc_otg_pcd_reinit(pcd);
+-01195 
+-01196         /* Allocate the cfi object for the PCD */
+-01197 #ifdef DWC_UTE_CFI
+-01198         pcd->cfi = dwc_alloc(sizeof(cfiobject_t));
+-01199         if (NULL == pcd->cfi)
+-01200                 return NULL;
+-01201         if (init_cfi(pcd->cfi)) {
+-01202                 CFI_INFO("%s: Failed to init the CFI object\n", __func__);
+-01203                 return NULL;
+-01204         }
+-01205 #endif
+-01206 
+-01207         /* Initialize tasklets */
+-01208         pcd->start_xfer_tasklet = DWC_TASK_ALLOC(start_xfer_tasklet_func, pcd);
+-01209         pcd->test_mode_tasklet = DWC_TASK_ALLOC(do_test_mode, pcd);
+-01210         /* Initialize timer */
+-01211         pcd->srp_timer = DWC_TIMER_ALLOC("SRP TIMER", srp_timeout, core_if);
+-01212         return pcd;
+-01213 }
+-01214 
+-01215 void dwc_otg_pcd_remove(dwc_otg_pcd_t * pcd)
+-01216 {
+-01217         dwc_otg_dev_if_t *dev_if = GET_CORE_IF(pcd)->dev_if;
+-01218 
+-01219         if (GET_CORE_IF(pcd)->dma_enable) {
+-01220                 dwc_dma_free(sizeof(*pcd->setup_pkt) * 5, pcd->setup_pkt,
+-01221                              pcd->setup_pkt_dma_handle);
+-01222                 dwc_dma_free(sizeof(uint16_t), pcd->status_buf,
+-01223                              pcd->status_buf_dma_handle);
+-01224                 if (GET_CORE_IF(pcd)->dma_desc_enable) {
+-01225                         dwc_otg_ep_free_desc_chain(dev_if->setup_desc_addr[0],
+-01226                                                    dev_if->
+-01227                                                    dma_setup_desc_addr[0], 1);
+-01228                         dwc_otg_ep_free_desc_chain(dev_if->setup_desc_addr[1],
+-01229                                                    dev_if->
+-01230                                                    dma_setup_desc_addr[1], 1);
+-01231                         dwc_otg_ep_free_desc_chain(dev_if->in_desc_addr,
+-01232                                                    dev_if->dma_in_desc_addr, 1);
+-01233                         dwc_otg_ep_free_desc_chain(dev_if->out_desc_addr,
+-01234                                                    dev_if->dma_out_desc_addr,
+-01235                                                    1);
+-01236                 }
+-01237         } else {
+-01238                 dwc_free(pcd->setup_pkt);
+-01239                 dwc_free(pcd->status_buf);
+-01240         }
+-01241         DWC_SPINLOCK_FREE(pcd->lock);
+-01242         DWC_TASK_FREE(pcd->start_xfer_tasklet);
+-01243         DWC_TASK_FREE(pcd->test_mode_tasklet);
+-01244         DWC_TIMER_FREE(pcd->srp_timer);
+-01245 
+-01246 /* Release the CFI object's dynamic memory */
+-01247 #ifdef DWC_UTE_CFI
+-01248         if (pcd->cfi->ops.release) {
+-01249                 pcd->cfi->ops.release(pcd->cfi);
+-01250         }
+-01251 #endif
+-01252 
+-01253         dwc_free(pcd);
+-01254 }
+-01255 
+-01256 uint32_t dwc_otg_pcd_is_dualspeed(dwc_otg_pcd_t * pcd)
+-01257 {
+-01258         dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
+-01259 
+-01260         if ((core_if->core_params->speed == DWC_SPEED_PARAM_FULL) ||
+-01261             ((core_if->hwcfg2.b.hs_phy_type == 2) &&
+-01262              (core_if->hwcfg2.b.fs_phy_type == 1) &&
+-01263              (core_if->core_params->ulpi_fs_ls))) {
+-01264                 return 0;
+-01265         }
+-01266 
+-01267         return 1;
+-01268 }
+-01269 
+-01270 uint32_t dwc_otg_pcd_is_otg(dwc_otg_pcd_t * pcd)
+-01271 {
+-01272         dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
+-01273         gusbcfg_data_t usbcfg = {.d32 = 0 };
+-01274 
+-01275         usbcfg.d32 = dwc_read_reg32(&core_if->core_global_regs->gusbcfg);
+-01276         if (!usbcfg.b.srpcap || !usbcfg.b.hnpcap) {
+-01277                 return 0;
+-01278         }
+-01279 
+-01280         return 1;
+-01281 }
+-01282 
+-01287 static uint32_t assign_tx_fifo(dwc_otg_core_if_t * core_if)
+-01288 {
+-01289         uint32_t TxMsk = 1;
+-01290         int i;
+-01291 
+-01292         for (i = 0; i < core_if->hwcfg4.b.num_in_eps; ++i) {
+-01293                 if ((TxMsk & core_if->tx_msk) == 0) {
+-01294                         core_if->tx_msk |= TxMsk;
+-01295                         return i + 1;
+-01296                 }
+-01297                 TxMsk <<= 1;
+-01298         }
+-01299         return 0;
+-01300 }
+-01301 
+-01306 static uint32_t assign_perio_tx_fifo(dwc_otg_core_if_t * core_if)
+-01307 {
+-01308         uint32_t PerTxMsk = 1;
+-01309         int i;
+-01310         for (i = 0; i < core_if->hwcfg4.b.num_dev_perio_in_ep; ++i) {
+-01311                 if ((PerTxMsk & core_if->p_tx_msk) == 0) {
+-01312                         core_if->p_tx_msk |= PerTxMsk;
+-01313                         return i + 1;
+-01314                 }
+-01315                 PerTxMsk <<= 1;
+-01316         }
+-01317         return 0;
+-01318 }
+-01319 
+-01324 static void release_perio_tx_fifo(dwc_otg_core_if_t * core_if,
+-01325                                   uint32_t fifo_num)
+-01326 {
+-01327         core_if->p_tx_msk =
+-01328             (core_if->p_tx_msk & (1 << (fifo_num - 1))) ^ core_if->p_tx_msk;
+-01329 }
+-01330 
+-01335 static void release_tx_fifo(dwc_otg_core_if_t * core_if, uint32_t fifo_num)
+-01336 {
+-01337         core_if->tx_msk =
+-01338             (core_if->tx_msk & (1 << (fifo_num - 1))) ^ core_if->tx_msk;
+-01339 }
+-01340 
+-01341 int dwc_otg_pcd_ep_enable(dwc_otg_pcd_t * pcd,
+-01342                           const uint8_t * ep_desc, void *usb_ep)
+-01343 {
+-01344         int num, dir;
+-01345         dwc_otg_pcd_ep_t *ep = 0;
+-01346         const usb_endpoint_descriptor_t *desc;
+-01347         uint64_t flags;
+-01348         int retval = 0;
+-01349 
+-01350         desc = (const usb_endpoint_descriptor_t *)ep_desc;
+-01351 
+-01352         if (!desc) {
+-01353                 pcd->ep0.priv = usb_ep;
+-01354                 ep = &pcd->ep0;
+-01355                 retval = -DWC_E_INVALID;
+-01356                 goto out;
+-01357         }
+-01358 
+-01359         num = UE_GET_ADDR(desc->bEndpointAddress);
+-01360         dir = UE_GET_DIR(desc->bEndpointAddress);
+-01361 
+-01362         if (!desc->wMaxPacketSize) {
+-01363                 DWC_WARN("bad maxpacketsize\n");
+-01364                 retval = -DWC_E_INVALID;
+-01365                 goto out;
+-01366         }
+-01367 
+-01368         if (dir == UE_DIR_IN) {
+-01369                 ep = &pcd->in_ep[num - 1];
+-01370         } else {
+-01371                 ep = &pcd->out_ep[num - 1];
+-01372         }
+-01373 
+-01374         DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
+-01375 
+-01376         ep->desc = desc;
+-01377         ep->priv = usb_ep;
+-01378 
+-01379         /*
+-01380          * Activate the EP
+-01381          */
+-01382         ep->stopped = 0;
+-01383 
+-01384         ep->dwc_ep.is_in = (dir == UE_DIR_IN);
+-01385         ep->dwc_ep.maxpacket = UGETW(desc->wMaxPacketSize);
+-01386 
+-01387         ep->dwc_ep.type = desc->bmAttributes & UE_XFERTYPE;
+-01388 
+-01389         if (ep->dwc_ep.is_in) {
+-01390                 if (!GET_CORE_IF(pcd)->en_multiple_tx_fifo) {
+-01391                         ep->dwc_ep.tx_fifo_num = 0;
+-01392 
+-01393                         if (ep->dwc_ep.type == UE_ISOCHRONOUS) {
+-01394                                 /*
+-01395                                  * if ISOC EP then assign a Periodic Tx FIFO.
+-01396                                  */
+-01397                                 ep->dwc_ep.tx_fifo_num =
+-01398                                     assign_perio_tx_fifo(GET_CORE_IF(pcd));
+-01399                         }
+-01400                 } else {
+-01401                         /*
+-01402                          * if Dedicated FIFOs mode is on then assign a Tx FIFO.
+-01403                          */
+-01404                         ep->dwc_ep.tx_fifo_num =
+-01405                             assign_tx_fifo(GET_CORE_IF(pcd));
+-01406 
+-01407                 }
+-01408         }
+-01409         /* Set initial data PID. */
+-01410         if (ep->dwc_ep.type == UE_BULK) {
+-01411                 ep->dwc_ep.data_pid_start = 0;
+-01412         }
+-01413 
+-01414         /* Alloc DMA Descriptors */
+-01415         if (GET_CORE_IF(pcd)->dma_desc_enable) {
+-01416                 if (ep->dwc_ep.type != UE_ISOCHRONOUS) {
+-01417                         ep->dwc_ep.desc_addr =
+-01418                             dwc_otg_ep_alloc_desc_chain(&ep->dwc_ep.
+-01419                                                         dma_desc_addr,
+-01420                                                         MAX_DMA_DESC_CNT);
+-01421                         if (!ep->dwc_ep.desc_addr) {
+-01422                                 DWC_WARN("%s, can't allocate DMA descriptor\n",
+-01423                                          __func__);
+-01424                                 retval = -DWC_E_SHUTDOWN;
+-01425                                 DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
+-01426                                 goto out;
+-01427                         }
+-01428                 }
+-01429         }
+-01430 
+-01431         DWC_DEBUGPL(DBG_PCD, "Activate %s: type=%d, mps=%d desc=%p\n",
+-01432                     (ep->dwc_ep.is_in ? "IN" : "OUT"),
+-01433                     ep->dwc_ep.type, ep->dwc_ep.maxpacket, ep->desc);
+-01434 
+-01435         dwc_otg_ep_activate(GET_CORE_IF(pcd), &ep->dwc_ep);
+-01436 
+-01437 #ifdef DWC_UTE_CFI
+-01438         if (pcd->cfi->ops.ep_enable) {
+-01439                 pcd->cfi->ops.ep_enable(pcd->cfi, pcd, ep);
+-01440         }
+-01441 #endif
+-01442 
+-01443         DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
+-01444 
+-01445       out:
+-01446         return retval;
+-01447 }
+-01448 
+-01449 int dwc_otg_pcd_ep_disable(dwc_otg_pcd_t * pcd, void *ep_handle)
+-01450 {
+-01451         dwc_otg_pcd_ep_t *ep;
+-01452         uint64_t flags;
+-01453         dwc_otg_dev_dma_desc_t *desc_addr;
+-01454         dwc_dma_t dma_desc_addr;
+-01455 
+-01456         ep = get_ep_from_handle(pcd, ep_handle);
+-01457 
+-01458         if (!ep || !ep->desc) {
+-01459                 DWC_DEBUGPL(DBG_PCD, "%s, %d %s not enabled\n", __func__,
+-01460                             ep->dwc_ep.num, ep->dwc_ep.is_in ? "IN" : "OUT");
+-01461                 return -DWC_E_INVALID;
+-01462         }
+-01463 
+-01464         DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
+-01465 
+-01466         dwc_otg_request_nuke(ep);
+-01467 
+-01468         dwc_otg_ep_deactivate(GET_CORE_IF(pcd), &ep->dwc_ep);
+-01469         ep->desc = 0;
+-01470         ep->stopped = 1;
+-01471 
+-01472         if (ep->dwc_ep.is_in) {
+-01473                 dwc_otg_flush_tx_fifo(GET_CORE_IF(pcd), ep->dwc_ep.tx_fifo_num);
+-01474                 release_perio_tx_fifo(GET_CORE_IF(pcd), ep->dwc_ep.tx_fifo_num);
+-01475                 release_tx_fifo(GET_CORE_IF(pcd), ep->dwc_ep.tx_fifo_num);
+-01476         }
+-01477 
+-01478         /* Free DMA Descriptors */
+-01479         if (GET_CORE_IF(pcd)->dma_desc_enable) {
+-01480                 if (ep->dwc_ep.type != UE_ISOCHRONOUS) {
+-01481                         desc_addr = ep->dwc_ep.desc_addr;
+-01482                         dma_desc_addr = ep->dwc_ep.dma_desc_addr;
+-01483 
+-01484                         /* Cannot call dma_free_coherent() with IRQs disabled */
+-01485                         DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
+-01486                         dwc_otg_ep_free_desc_chain(desc_addr, dma_desc_addr,
+-01487                                                    MAX_DMA_DESC_CNT);
+-01488 
+-01489                         goto out_unlocked;
+-01490                 }
+-01491         }
+-01492 
+-01493         DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
+-01494 
+-01495       out_unlocked:
+-01496         DWC_DEBUGPL(DBG_PCD, "%d %s disabled\n", ep->dwc_ep.num,
+-01497                     ep->dwc_ep.is_in ? "IN" : "OUT");
+-01498         return 0;
+-01499 
+-01500 }
+-01501 
+-01502 int dwc_otg_pcd_ep_queue(dwc_otg_pcd_t * pcd, void *ep_handle,
+-01503                          uint8_t * buf, dwc_dma_t dma_buf, uint32_t buflen,
+-01504                          int zero, void *req_handle, int atomic_alloc)
+-01505 {
+-01506         int prevented = 0;
+-01507         uint64_t flags;
+-01508         dwc_otg_pcd_request_t *req;
+-01509         dwc_otg_pcd_ep_t *ep;
+-01510         uint32_t max_transfer;
+-01511 
+-01512         ep = get_ep_from_handle(pcd, ep_handle);
+-01513         if ((!ep->desc && ep->dwc_ep.num != 0)) {
+-01514                 DWC_WARN("bad ep\n");
+-01515                 return -DWC_E_INVALID;
+-01516         }
+-01517 
+-01518         if (atomic_alloc) {
+-01519                 req = dwc_alloc_atomic(sizeof(*req));
+-01520         } else {
+-01521                 req = dwc_alloc(sizeof(*req));
+-01522         }
+-01523 
+-01524         if (!req) {
+-01525                 return -DWC_E_NO_MEMORY;
+-01526         }
+-01527         DWC_CIRCLEQ_INIT_ENTRY(req, queue_entry);
+-01528         if (!GET_CORE_IF(pcd)->core_params->opt) {
+-01529                 if (ep->dwc_ep.num != 0) {
+-01530                         DWC_ERROR("queue req %p, len %d buf %p\n",
+-01531                                   req_handle, buflen, buf);
+-01532                 }
+-01533         }
+-01534 
+-01535         req->buf = buf;
+-01536         req->dma = dma_buf;
+-01537         req->length = buflen;
+-01538         req->sent_zlp = zero;
+-01539         req->priv = req_handle;
+-01540 
+-01541         DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
+-01542 
+-01543         /*
+-01544          * For EP0 IN without premature status, zlp is required?
+-01545          */
+-01546         if (ep->dwc_ep.num == 0 && ep->dwc_ep.is_in) {
+-01547                 DWC_DEBUGPL(DBG_PCDV, "%d-OUT ZLP\n", ep->dwc_ep.num);
+-01548                 //_req->zero = 1;
+-01549         }
+-01550 
+-01551         /* Start the transfer */
+-01552         if (DWC_CIRCLEQ_EMPTY(&ep->queue) && !ep->stopped) {
+-01553                 /* EP0 Transfer? */
+-01554                 if (ep->dwc_ep.num == 0) {
+-01555                         switch (pcd->ep0state) {
+-01556                         case EP0_IN_DATA_PHASE:
+-01557                                 DWC_DEBUGPL(DBG_PCD,
+-01558                                             "%s ep0: EP0_IN_DATA_PHASE\n",
+-01559                                             __func__);
+-01560                                 break;
+-01561 
+-01562                         case EP0_OUT_DATA_PHASE:
+-01563                                 DWC_DEBUGPL(DBG_PCD,
+-01564                                             "%s ep0: EP0_OUT_DATA_PHASE\n",
+-01565                                             __func__);
+-01566                                 if (pcd->request_config) {
+-01567                                         /* Complete STATUS PHASE */
+-01568                                         ep->dwc_ep.is_in = 1;
+-01569                                         pcd->ep0state = EP0_IN_STATUS_PHASE;
+-01570                                 }
+-01571                                 break;
+-01572 
+-01573                         case EP0_IN_STATUS_PHASE:
+-01574                                 DWC_DEBUGPL(DBG_PCD,
+-01575                                             "%s ep0: EP0_IN_STATUS_PHASE\n",
+-01576                                             __func__);
+-01577                                 break;
+-01578 
+-01579                         default:
+-01580                                 DWC_DEBUGPL(DBG_ANY, "ep0: odd state %d\n",
+-01581                                             pcd->ep0state);
+-01582                                 DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
+-01583                                 return -DWC_E_SHUTDOWN;
+-01584                         }
+-01585 
+-01586                         ep->dwc_ep.dma_addr = dma_buf;
+-01587                         ep->dwc_ep.start_xfer_buff = buf;
+-01588                         ep->dwc_ep.xfer_buff = buf;
+-01589                         ep->dwc_ep.xfer_len = buflen;
+-01590                         ep->dwc_ep.xfer_count = 0;
+-01591                         ep->dwc_ep.sent_zlp = 0;
+-01592                         ep->dwc_ep.total_len = ep->dwc_ep.xfer_len;
+-01593 
+-01594                         if (zero) {
+-01595                                 if ((ep->dwc_ep.xfer_len %
+-01596                                      ep->dwc_ep.maxpacket == 0)
+-01597                                     && (ep->dwc_ep.xfer_len != 0)) {
+-01598                                         ep->dwc_ep.sent_zlp = 1;
+-01599                                 }
+-01600 
+-01601                         }
+-01602 
+-01603                         dwc_otg_ep0_start_transfer(GET_CORE_IF(pcd),
+-01604                                                    &ep->dwc_ep);
+-01605                 }               // non-ep0 endpoints
+-01606                 else {
+-01607 #ifdef DWC_UTE_CFI
+-01608                         if (ep->dwc_ep.buff_mode != BM_STANDARD) {
+-01609                                 /* store the request length */
+-01610                                 ep->dwc_ep.cfi_req_len = buflen;
+-01611                                 pcd->cfi->ops.build_descriptors(pcd->cfi, pcd,
+-01612                                                                 ep, req);
+-01613                 } else {
+-01614 #endif
+-01615                                 max_transfer =
+-01616                                     GET_CORE_IF(ep->pcd)->core_params->
+-01617                                     max_transfer_size;
+-01618 
+-01619                         /* Setup and start the Transfer */
+-01620                         ep->dwc_ep.dma_addr = dma_buf;
+-01621                         ep->dwc_ep.start_xfer_buff = buf;
+-01622                         ep->dwc_ep.xfer_buff = buf;
+-01623                         ep->dwc_ep.xfer_len = 0;
+-01624                         ep->dwc_ep.xfer_count = 0;
+-01625                         ep->dwc_ep.sent_zlp = 0;
+-01626                         ep->dwc_ep.total_len = buflen;
+-01627 
+-01628                         ep->dwc_ep.maxxfer = max_transfer;
+-01629                         if (GET_CORE_IF(pcd)->dma_desc_enable) {
+-01630                                         uint32_t out_max_xfer =
+-01631                                             DDMA_MAX_TRANSFER_SIZE -
+-01632                                             (DDMA_MAX_TRANSFER_SIZE % 4);
+-01633                                 if (ep->dwc_ep.is_in) {
+-01634                                         if (ep->dwc_ep.maxxfer >
+-01635                                             DDMA_MAX_TRANSFER_SIZE) {
+-01636                                                 ep->dwc_ep.maxxfer =
+-01637                                                     DDMA_MAX_TRANSFER_SIZE;
+-01638                                         }
+-01639                                 } else {
+-01640                                                 if (ep->dwc_ep.maxxfer >
+-01641                                                     out_max_xfer) {
+-01642                                                 ep->dwc_ep.maxxfer =
+-01643                                                     out_max_xfer;
+-01644                                         }
+-01645                                 }
+-01646                         }
+-01647                         if (ep->dwc_ep.maxxfer < ep->dwc_ep.total_len) {
+-01648                                 ep->dwc_ep.maxxfer -=
+-01649                                             (ep->dwc_ep.maxxfer %
+-01650                                              ep->dwc_ep.maxpacket);
+-01651                         }
+-01652 
+-01653                         if (zero) {
+-01654                                 if ((ep->dwc_ep.total_len %
+-01655                                              ep->dwc_ep.maxpacket == 0)
+-01656                                             && (ep->dwc_ep.total_len != 0)) {
+-01657                                         ep->dwc_ep.sent_zlp = 1;
+-01658                                 }
+-01659                         }
+-01660 #ifdef DWC_UTE_CFI
+-01661                         }
+-01662 #endif
+-01663                         dwc_otg_ep_start_transfer(GET_CORE_IF(pcd),
+-01664                                                   &ep->dwc_ep);
+-01665                 }
+-01666         }
+-01667 
+-01668         if ((req != 0) || prevented) {
+-01669                 ++pcd->request_pending;
+-01670                 DWC_CIRCLEQ_INSERT_TAIL(&ep->queue, req, queue_entry);
+-01671                 if (ep->dwc_ep.is_in && ep->stopped
+-01672                     && !(GET_CORE_IF(pcd)->dma_enable)) {
+-01674                         diepmsk_data_t diepmsk = {.d32 = 0 };
+-01675                         diepmsk.b.intktxfemp = 1;
+-01676                         if (GET_CORE_IF(pcd)->multiproc_int_enable) {
+-01677                                 dwc_modify_reg32(&GET_CORE_IF(pcd)->dev_if->
+-01678                                                  dev_global_regs->
+-01679                                                  diepeachintmsk[ep->dwc_ep.num],
+-01680                                                  0, diepmsk.d32);
+-01681                         } else {
+-01682                                 dwc_modify_reg32(&GET_CORE_IF(pcd)->dev_if->
+-01683                                                  dev_global_regs->diepmsk, 0,
+-01684                                                  diepmsk.d32);
+-01685                         }
+-01686 
+-01687                 }
+-01688         }
+-01689 
+-01690         DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
+-01691 
+-01692         return 0;
+-01693 }
+-01694 int dwc_otg_pcd_ep_dequeue(dwc_otg_pcd_t * pcd, void *ep_handle,
+-01695                            void *req_handle)
+-01696 {
+-01697         uint64_t flags;
+-01698         dwc_otg_pcd_request_t *req;
+-01699         dwc_otg_pcd_ep_t *ep;
+-01700 
+-01701         ep = get_ep_from_handle(pcd, ep_handle);
+-01702         if (!ep->desc && ep->dwc_ep.num != 0) {
+-01703                 DWC_WARN("bad argument\n");
+-01704                 return -DWC_E_INVALID;
+-01705         }
+-01706 
+-01707         DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
+-01708 
+-01709         /* make sure it's actually queued on this endpoint */
+-01710         DWC_CIRCLEQ_FOREACH(req, &ep->queue, queue_entry) {
+-01711                 if (req->priv == (void *)req_handle) {
+-01712                         break;
+-01713                 }
+-01714         }
+-01715 
+-01716         if (req->priv != (void *)req_handle) {
+-01717                 DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
+-01718                 return -DWC_E_INVALID;
+-01719         }
+-01720 
+-01721         if (!DWC_CIRCLEQ_EMPTY_ENTRY(req, queue_entry)) {
+-01722                 dwc_otg_request_done(ep, req, -DWC_E_RESTART);
+-01723         } else {
+-01724                 req = 0;
+-01725         }
+-01726 
+-01727         DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
+-01728 
+-01729         return req ? 0 : -DWC_E_SHUTDOWN;
+-01730 
+-01731 }
+-01732 
+-01733 int dwc_otg_pcd_ep_halt(dwc_otg_pcd_t * pcd, void *ep_handle, int value)
+-01734 {
+-01735         dwc_otg_pcd_ep_t *ep;
+-01736         uint64_t flags;
+-01737         int retval = 0;
+-01738 
+-01739         ep = get_ep_from_handle(pcd, ep_handle);
+-01740 
+-01741         if ((!ep->desc && ep != &pcd->ep0) ||
+-01742             (ep->desc && (ep->desc->bmAttributes == UE_ISOCHRONOUS))) {
+-01743                 DWC_WARN("%s, bad ep\n", __func__);
+-01744                 return -DWC_E_INVALID;
+-01745         }
+-01746 
+-01747         DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
+-01748         if (!DWC_CIRCLEQ_EMPTY(&ep->queue)) {
+-01749                 DWC_WARN("%d %s XFer In process\n", ep->dwc_ep.num,
+-01750                          ep->dwc_ep.is_in ? "IN" : "OUT");
+-01751                 retval = -DWC_E_AGAIN;
+-01752         } else if (value == 0) {
+-01753                 dwc_otg_ep_clear_stall(GET_CORE_IF(pcd), &ep->dwc_ep);
+-01754         } else if (value == 1) {
+-01755                 if (ep->dwc_ep.is_in == 1 && GET_CORE_IF(pcd)->dma_desc_enable) {
+-01756                         dtxfsts_data_t txstatus;
+-01757                         fifosize_data_t txfifosize;
+-01758 
+-01759                         txfifosize.d32 =
+-01760                             dwc_read_reg32(&GET_CORE_IF(pcd)->core_global_regs->
+-01761                                            dptxfsiz_dieptxf[ep->dwc_ep.
+-01762                                                             tx_fifo_num]);
+-01763                         txstatus.d32 =
+-01764                             dwc_read_reg32(&GET_CORE_IF(pcd)->dev_if->
+-01765                                            in_ep_regs[ep->dwc_ep.num]->dtxfsts);
+-01766 
+-01767                         if (txstatus.b.txfspcavail < txfifosize.b.depth) {
+-01768                                 DWC_WARN("%s() Data In Tx Fifo\n", __func__);
+-01769                                 retval = -DWC_E_AGAIN;
+-01770                         } else {
+-01771                                 if (ep->dwc_ep.num == 0) {
+-01772                                         pcd->ep0state = EP0_STALL;
+-01773                                 }
+-01774 
+-01775                                 ep->stopped = 1;
+-01776                                 dwc_otg_ep_set_stall(GET_CORE_IF(pcd),
+-01777                                                      &ep->dwc_ep);
+-01778                         }
+-01779                 } else {
+-01780                         if (ep->dwc_ep.num == 0) {
+-01781                                 pcd->ep0state = EP0_STALL;
+-01782                         }
+-01783 
+-01784                         ep->stopped = 1;
+-01785                         dwc_otg_ep_set_stall(GET_CORE_IF(pcd), &ep->dwc_ep);
+-01786                 }
+-01787         } else if (value == 2) {
+-01788                 ep->dwc_ep.stall_clear_flag = 0;
+-01789         } else if (value == 3) {
+-01790                 ep->dwc_ep.stall_clear_flag = 1;
+-01791         }
+-01792 
+-01793         DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
+-01794 
+-01795         return retval;
+-01796 }
+-01797 
+-01801 void dwc_otg_pcd_rem_wkup_from_suspend(dwc_otg_pcd_t * pcd, int set)
+-01802 {
+-01803         dctl_data_t dctl = { 0 };
+-01804         dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
+-01805         dsts_data_t dsts;
+-01806 
+-01807         dsts.d32 = dwc_read_reg32(&core_if->dev_if->dev_global_regs->dsts);
+-01808         if (!dsts.b.suspsts) {
+-01809                 DWC_WARN("Remote wakeup while is not in suspend state\n");
+-01810         }
+-01811         /* Check if DEVICE_REMOTE_WAKEUP feature enabled */
+-01812         if (pcd->remote_wakeup_enable) {
+-01813                 if (set) {
+-01814                         dctl.b.rmtwkupsig = 1;
+-01815                         dwc_modify_reg32(&core_if->dev_if->dev_global_regs->
+-01816                                          dctl, 0, dctl.d32);
+-01817                         DWC_DEBUGPL(DBG_PCD, "Set Remote Wakeup\n");
+-01818                         dwc_mdelay(2);
+-01819                         dwc_modify_reg32(&core_if->dev_if->dev_global_regs->
+-01820                                          dctl, dctl.d32, 0);
+-01821                         DWC_DEBUGPL(DBG_PCD, "Clear Remote Wakeup\n");
+-01822                 }
+-01823         } else {
+-01824                 DWC_DEBUGPL(DBG_PCD, "Remote Wakeup is disabled\n");
+-01825         }
+-01826 }
+-01827 
+-01828 #ifdef CONFIG_USB_DWC_OTG_LPM
+-01829 
+-01832 void dwc_otg_pcd_rem_wkup_from_sleep(dwc_otg_pcd_t * pcd, int set)
+-01833 {
+-01834         glpmcfg_data_t lpmcfg;
+-01835         dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
+-01836 
+-01837         lpmcfg.d32 = dwc_read_reg32(&core_if->core_global_regs->glpmcfg);
+-01838 
+-01839         /* Check if we are in L1 state */
+-01840         if (!lpmcfg.b.prt_sleep_sts) {
+-01841                 DWC_DEBUGPL(DBG_PCD, "Device is not in sleep state\n");
+-01842                 return;
+-01843         }
+-01844 
+-01845         /* Check if host allows remote wakeup */
+-01846         if (!lpmcfg.b.rem_wkup_en) {
+-01847                 DWC_DEBUGPL(DBG_PCD, "Host does not allow remote wakeup\n");
+-01848                 return;
+-01849         }
+-01850 
+-01851         /* Check if Resume OK */
+-01852         if (!lpmcfg.b.sleep_state_resumeok) {
+-01853                 DWC_DEBUGPL(DBG_PCD, "Sleep state resume is not OK\n");
+-01854                 return;
+-01855         }
+-01856 
+-01857         lpmcfg.d32 = dwc_read_reg32(&core_if->core_global_regs->glpmcfg);
+-01858         lpmcfg.b.en_utmi_sleep = 0;
+-01859         lpmcfg.b.hird_thres &= (~(1 << 4));
+-01860         dwc_write_reg32(&core_if->core_global_regs->glpmcfg, lpmcfg.d32);
+-01861 
+-01862         if (set) {
+-01863                 dctl_data_t dctl = {.d32 = 0 };
+-01864                 dctl.b.rmtwkupsig = 1;
+-01865                 /* Set RmtWkUpSig bit to start remote wakup signaling.
+-01866                  * Hardware will automatically clear this bit.
+-01867                  */
+-01868                 dwc_modify_reg32(&core_if->dev_if->dev_global_regs->dctl,
+-01869                                  0, dctl.d32);
+-01870                 DWC_DEBUGPL(DBG_PCD, "Set Remote Wakeup\n");
+-01871         }
+-01872 
+-01873 }
+-01874 #endif
+-01875 
+-01879 void dwc_otg_pcd_remote_wakeup(dwc_otg_pcd_t * pcd, int set)
+-01880 {
+-01881         dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
+-01882         if (dwc_otg_is_device_mode(core_if)) {
+-01883 #ifdef CONFIG_USB_DWC_OTG_LPM
+-01884                 if (core_if->lx_state == DWC_OTG_L1) {
+-01885                         dwc_otg_pcd_rem_wkup_from_sleep(pcd, set);
+-01886                 } else {
+-01887 #endif
+-01888                         dwc_otg_pcd_rem_wkup_from_suspend(pcd, set);
+-01889 #ifdef CONFIG_USB_DWC_OTG_LPM
+-01890                 }
+-01891 #endif
+-01892         }
+-01893         return;
+-01894 }
+-01895 
+-01896 int dwc_otg_pcd_wakeup(dwc_otg_pcd_t * pcd)
+-01897 {
+-01898         dsts_data_t dsts;
+-01899         gotgctl_data_t gotgctl;
+-01900         uint64_t flags;
+-01901 
+-01902         DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
+-01903 
+-01904         /*
+-01905          * This function starts the Protocol if no session is in progress. If
+-01906          * a session is already in progress, but the device is suspended,
+-01907          * remote wakeup signaling is started.
+-01908          */
+-01909 
+-01910         /* Check if valid session */
+-01911         gotgctl.d32 =
+-01912             dwc_read_reg32(&(GET_CORE_IF(pcd)->core_global_regs->gotgctl));
+-01913         if (gotgctl.b.bsesvld) {
+-01914                 /* Check if suspend state */
+-01915                 dsts.d32 =
+-01916                     dwc_read_reg32(&
+-01917                                    (GET_CORE_IF(pcd)->dev_if->dev_global_regs->
+-01918                                     dsts));
+-01919                 if (dsts.b.suspsts) {
+-01920                         dwc_otg_pcd_remote_wakeup(pcd, 1);
+-01921                 }
+-01922         } else {
+-01923                 dwc_otg_pcd_initiate_srp(pcd);
+-01924         }
+-01925 
+-01926         DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
+-01927         return 0;
+-01928 
+-01929 }
+-01930 
+-01937 void dwc_otg_pcd_start_srp_timer(dwc_otg_pcd_t * pcd)
+-01938 {
+-01939         GET_CORE_IF(pcd)->srp_timer_started = 1;
+-01940         DWC_TIMER_SCHEDULE(pcd->srp_timer, 6000 /* 6 secs */ );
+-01941 }
+-01942 
+-01943 void dwc_otg_pcd_initiate_srp(dwc_otg_pcd_t * pcd)
+-01944 {
+-01945         uint32_t *addr =
+-01946             (uint32_t *) & (GET_CORE_IF(pcd)->core_global_regs->gotgctl);
+-01947         gotgctl_data_t mem;
+-01948         gotgctl_data_t val;
+-01949 
+-01950         val.d32 = dwc_read_reg32(addr);
+-01951         if (val.b.sesreq) {
+-01952                 DWC_ERROR("Session Request Already active!\n");
+-01953                 return;
+-01954         }
+-01955 
+-01956         DWC_INFO("Session Request Initated\n"); //NOTICE
+-01957         mem.d32 = dwc_read_reg32(addr);
+-01958         mem.b.sesreq = 1;
+-01959         dwc_write_reg32(addr, mem.d32);
+-01960 
+-01961         /* Start the SRP timer */
+-01962         dwc_otg_pcd_start_srp_timer(pcd);
+-01963         return;
+-01964 }
+-01965 
+-01966 int dwc_otg_pcd_get_frame_number(dwc_otg_pcd_t * pcd)
+-01967 {
+-01968         return dwc_otg_get_frame_number(GET_CORE_IF(pcd));
+-01969 }
+-01970 
+-01971 int dwc_otg_pcd_is_lpm_enabled(dwc_otg_pcd_t * pcd)
+-01972 {
+-01973         return GET_CORE_IF(pcd)->core_params->lpm_enable;
+-01974 }
+-01975 
+-01976 uint32_t get_b_hnp_enable(dwc_otg_pcd_t * pcd)
+-01977 {
+-01978         return pcd->b_hnp_enable;
+-01979 }
+-01980 
+-01981 uint32_t get_a_hnp_support(dwc_otg_pcd_t * pcd)
+-01982 {
+-01983         return pcd->a_hnp_support;
+-01984 }
+-01985 
+-01986 uint32_t get_a_alt_hnp_support(dwc_otg_pcd_t * pcd)
+-01987 {
+-01988         return pcd->a_alt_hnp_support;
+-01989 }
+-01990 
+-01991 int dwc_otg_pcd_get_rmwkup_enable(dwc_otg_pcd_t * pcd)
+-01992 {
+-01993         return pcd->remote_wakeup_enable;
+-01994 }
+-01995 
+-01996 #endif                          /* DWC_HOST_ONLY */
+-
    Generated on Tue May 5 02:22:48 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++
    Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
    ++

    dwc_otg_pcd.c

    Go to the documentation of this file.
    00001 /* ==========================================================================
++00002  * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_pcd.c $
++00003  * $Revision: #99 $
++00004  * $Date: 2011/10/24 $
++00005  * $Change: 1871160 $
++00006  *
++00007  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
++00008  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
++00009  * otherwise expressly agreed to in writing between Synopsys and you.
++00010  *
++00011  * The Software IS NOT an item of Licensed Software or Licensed Product under
++00012  * any End User Software License Agreement or Agreement for Licensed Product
++00013  * with Synopsys or any supplement thereto. You are permitted to use and
++00014  * redistribute this Software in source and binary forms, with or without
++00015  * modification, provided that redistributions of source code must retain this
++00016  * notice. You may not view, use, disclose, copy or distribute this file or
++00017  * any information contained herein except pursuant to this license grant from
++00018  * Synopsys. If you do not agree with this notice, including the disclaimer
++00019  * below, then you are not authorized to use the Software.
++00020  *
++00021  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
++00022  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++00023  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++00024  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
++00025  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++00026  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
++00027  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
++00028  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
++00029  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
++00030  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
++00031  * DAMAGE.
++00032  * ========================================================================== */
++00033 #ifndef DWC_HOST_ONLY
++00034 
++00051 #include "dwc_otg_pcd.h"
++00052 
++00053 #ifdef DWC_UTE_CFI
++00054 #include "dwc_otg_cfi.h"
++00055 
++00056 extern int init_cfi(cfiobject_t * cfiobj);
++00057 #endif
++00058 
++00062 static dwc_otg_pcd_ep_t *get_ep_from_handle(dwc_otg_pcd_t * pcd, void *handle)
++00063 {
++00064         int i;
++00065         if (pcd->ep0.priv == handle) {
++00066                 return &pcd->ep0;
++00067         }
++00068         for (i = 0; i < MAX_EPS_CHANNELS - 1; i++) {
++00069                 if (pcd->in_ep[i].priv == handle)
++00070                         return &pcd->in_ep[i];
++00071                 if (pcd->out_ep[i].priv == handle)
++00072                         return &pcd->out_ep[i];
++00073         }
++00074 
++00075         return NULL;
++00076 }
++00077 
++00081 void dwc_otg_request_done(dwc_otg_pcd_ep_t * ep, dwc_otg_pcd_request_t * req,
++00082                           int32_t status)
++00083 {
++00084         unsigned stopped = ep->stopped;
++00085         
++00086         DWC_DEBUGPL(DBG_PCDV, "%s(ep %p req %p)\n", __func__, ep, req);
++00087         DWC_CIRCLEQ_REMOVE_INIT(&ep->queue, req, queue_entry);
++00088 
++00089         /* don't modify queue heads during completion callback */
++00090         ep->stopped = 1;
++00091         /* spin_unlock/spin_lock now done in fops->complete() */
++00092         ep->pcd->fops->complete(ep->pcd, ep->priv, req->priv, status,
++00093                                 req->actual);
++00094 
++00095         if (ep->pcd->request_pending > 0) {
++00096                 --ep->pcd->request_pending;
++00097         }
++00098 
++00099         ep->stopped = stopped;
++00100         DWC_FREE(req);
++00101 }
++00102 
++00106 void dwc_otg_request_nuke(dwc_otg_pcd_ep_t * ep)
++00107 {
++00108         dwc_otg_pcd_request_t *req;
++00109 
++00110         ep->stopped = 1;
++00111 
++00112         /* called with irqs blocked?? */
++00113         while (!DWC_CIRCLEQ_EMPTY(&ep->queue)) {
++00114                 req = DWC_CIRCLEQ_FIRST(&ep->queue);
++00115                 dwc_otg_request_done(ep, req, -DWC_E_SHUTDOWN);
++00116         }
++00117 }
++00118 
++00119 void dwc_otg_pcd_start(dwc_otg_pcd_t * pcd,
++00120                        const struct dwc_otg_pcd_function_ops *fops)
++00121 {
++00122         pcd->fops = fops;
++00123 }
++00124 
++00131 static int32_t dwc_otg_pcd_start_cb(void *p)
++00132 {
++00133         dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *) p;
++00134         dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
++00135 
++00136         /*
++00137          * Initialized the Core for Device mode.
++00138          */
++00139         if (dwc_otg_is_device_mode(core_if)) {
++00140                 dwc_otg_core_dev_init(core_if);
++00141                 /* Set core_if's lock pointer to the pcd->lock */
++00142                 core_if->lock = pcd->lock;
++00143         }
++00144         return 1;
++00145 }
++00146 
++00148 #ifdef DWC_UTE_CFI
++00149 uint8_t *cfiw_ep_alloc_buffer(dwc_otg_pcd_t * pcd, void *pep, dwc_dma_t * addr,
++00150                               size_t buflen, int flags)
++00151 {
++00152         dwc_otg_pcd_ep_t *ep;
++00153         ep = get_ep_from_handle(pcd, pep);
++00154         if (!ep) {
++00155                 DWC_WARN("bad ep\n");
++00156                 return -DWC_E_INVALID;
++00157         }
++00158 
++00159         return pcd->cfi->ops.ep_alloc_buf(pcd->cfi, pcd, ep, addr, buflen,
++00160                                           flags);
++00161 }
++00162 #else
++00163 uint8_t *cfiw_ep_alloc_buffer(dwc_otg_pcd_t * pcd, void *pep, dwc_dma_t * addr,
++00164                               size_t buflen, int flags);
++00165 #endif
++00166 
++00173 static int32_t dwc_otg_pcd_resume_cb(void *p)
++00174 {
++00175         dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *) p;
++00176 
++00177         if (pcd->fops->resume) {
++00178                 pcd->fops->resume(pcd);
++00179         }
++00180 
++00181         /* Stop the SRP timeout timer. */
++00182         if ((GET_CORE_IF(pcd)->core_params->phy_type != DWC_PHY_TYPE_PARAM_FS)
++00183             || (!GET_CORE_IF(pcd)->core_params->i2c_enable)) {
++00184                 if (GET_CORE_IF(pcd)->srp_timer_started) {
++00185                         GET_CORE_IF(pcd)->srp_timer_started = 0;
++00186                         DWC_TIMER_CANCEL(GET_CORE_IF(pcd)->srp_timer);
++00187                 }
++00188         }
++00189         return 1;
++00190 }
++00191 
++00197 static int32_t dwc_otg_pcd_suspend_cb(void *p)
++00198 {
++00199         dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *) p;
++00200 
++00201         if (pcd->fops->suspend) {
++00202                 DWC_SPINUNLOCK(pcd->lock);
++00203                 pcd->fops->suspend(pcd);
++00204                 DWC_SPINLOCK(pcd->lock);
++00205         }
++00206 
++00207         return 1;
++00208 }
++00209 
++00216 static int32_t dwc_otg_pcd_stop_cb(void *p)
++00217 {
++00218         dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *) p;
++00219         extern void dwc_otg_pcd_stop(dwc_otg_pcd_t * _pcd);
++00220 
++00221         dwc_otg_pcd_stop(pcd);
++00222         return 1;
++00223 }
++00224 
++00228 static dwc_otg_cil_callbacks_t pcd_callbacks = {
++00229         .start = dwc_otg_pcd_start_cb,
++00230         .stop = dwc_otg_pcd_stop_cb,
++00231         .suspend = dwc_otg_pcd_suspend_cb,
++00232         .resume_wakeup = dwc_otg_pcd_resume_cb,
++00233         .p = 0,                 /* Set at registration */
++00234 };
++00235 
++00240 dwc_otg_dev_dma_desc_t *dwc_otg_ep_alloc_desc_chain(dwc_dma_t * dma_desc_addr,
++00241                                                     uint32_t count)
++00242 {
++00243         return DWC_DMA_ALLOC_ATOMIC(count * sizeof(dwc_otg_dev_dma_desc_t), 
++00244                                                         dma_desc_addr);
++00245 }
++00246 
++00250 void dwc_otg_ep_free_desc_chain(dwc_otg_dev_dma_desc_t * desc_addr,
++00251                                 uint32_t dma_desc_addr, uint32_t count)
++00252 {
++00253         DWC_DMA_FREE(count * sizeof(dwc_otg_dev_dma_desc_t), desc_addr,
++00254                      dma_desc_addr);
++00255 }
++00256 
++00257 #ifdef DWC_EN_ISOC
++00258 
++00266 void dwc_otg_iso_ep_start_ddma_transfer(dwc_otg_core_if_t * core_if,
++00267                                         dwc_ep_t * dwc_ep)
++00268 {
++00269 
++00270         dsts_data_t dsts = {.d32 = 0 };
++00271         depctl_data_t depctl = {.d32 = 0 };
++00272         volatile uint32_t *addr;
++00273         int i, j;
++00274         uint32_t len;
++00275 
++00276         if (dwc_ep->is_in)
++00277                 dwc_ep->desc_cnt = dwc_ep->buf_proc_intrvl / dwc_ep->bInterval;
++00278         else
++00279                 dwc_ep->desc_cnt =
++00280                     dwc_ep->buf_proc_intrvl * dwc_ep->pkt_per_frm /
++00281                     dwc_ep->bInterval;
++00282 
++00284         dwc_ep->iso_desc_addr =
++00285             dwc_otg_ep_alloc_desc_chain(&dwc_ep->iso_dma_desc_addr,
++00286                                         dwc_ep->desc_cnt * 2);
++00287         if (dwc_ep->desc_addr) {
++00288                 DWC_WARN("%s, can't allocate DMA descriptor chain\n", __func__);
++00289                 return;
++00290         }
++00291 
++00292         dsts.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts);
++00293 
++00295         if (dwc_ep->is_in == 0) {
++00296                 dev_dma_desc_sts_t sts = {.d32 = 0 };
++00297                 dwc_otg_dev_dma_desc_t *dma_desc = dwc_ep->iso_desc_addr;
++00298                 dma_addr_t dma_ad;
++00299                 uint32_t data_per_desc;
++00300                 dwc_otg_dev_out_ep_regs_t *out_regs =
++00301                     core_if->dev_if->out_ep_regs[dwc_ep->num];
++00302                 int offset;
++00303 
++00304                 addr = &core_if->dev_if->out_ep_regs[dwc_ep->num]->doepctl;
++00305                 dma_ad = (dma_addr_t) DWC_READ_REG32(&(out_regs->doepdma));
++00306 
++00308                 dma_ad = dwc_ep->dma_addr0;
++00309 
++00310                 sts.b_iso_out.bs = BS_HOST_READY;
++00311                 sts.b_iso_out.rxsts = 0;
++00312                 sts.b_iso_out.l = 0;
++00313                 sts.b_iso_out.sp = 0;
++00314                 sts.b_iso_out.ioc = 0;
++00315                 sts.b_iso_out.pid = 0;
++00316                 sts.b_iso_out.framenum = 0;
++00317 
++00318                 offset = 0;
++00319                 for (i = 0; i < dwc_ep->desc_cnt - dwc_ep->pkt_per_frm;
++00320                      i += dwc_ep->pkt_per_frm) {
++00321 
++00322                         for (j = 0; j < dwc_ep->pkt_per_frm; ++j) {
++00323                                 uint32_t len = (j + 1) * dwc_ep->maxpacket;
++00324                                 if (len > dwc_ep->data_per_frame)
++00325                                         data_per_desc =
++00326                                             dwc_ep->data_per_frame -
++00327                                             j * dwc_ep->maxpacket;
++00328                                 else
++00329                                         data_per_desc = dwc_ep->maxpacket;
++00330                                 len = data_per_desc % 4;
++00331                                 if (len)
++00332                                         data_per_desc += 4 - len;
++00333 
++00334                                 sts.b_iso_out.rxbytes = data_per_desc;
++00335                                 dma_desc->buf = dma_ad;
++00336                                 dma_desc->status.d32 = sts.d32;
++00337 
++00338                                 offset += data_per_desc;
++00339                                 dma_desc++;
++00340                                 dma_ad += data_per_desc;
++00341                         }
++00342                 }
++00343 
++00344                 for (j = 0; j < dwc_ep->pkt_per_frm - 1; ++j) {
++00345                         uint32_t len = (j + 1) * dwc_ep->maxpacket;
++00346                         if (len > dwc_ep->data_per_frame)
++00347                                 data_per_desc =
++00348                                     dwc_ep->data_per_frame -
++00349                                     j * dwc_ep->maxpacket;
++00350                         else
++00351                                 data_per_desc = dwc_ep->maxpacket;
++00352                         len = data_per_desc % 4;
++00353                         if (len)
++00354                                 data_per_desc += 4 - len;
++00355                         sts.b_iso_out.rxbytes = data_per_desc;
++00356                         dma_desc->buf = dma_ad;
++00357                         dma_desc->status.d32 = sts.d32;
++00358 
++00359                         offset += data_per_desc;
++00360                         dma_desc++;
++00361                         dma_ad += data_per_desc;
++00362                 }
++00363 
++00364                 sts.b_iso_out.ioc = 1;
++00365                 len = (j + 1) * dwc_ep->maxpacket;
++00366                 if (len > dwc_ep->data_per_frame)
++00367                         data_per_desc =
++00368                             dwc_ep->data_per_frame - j * dwc_ep->maxpacket;
++00369                 else
++00370                         data_per_desc = dwc_ep->maxpacket;
++00371                 len = data_per_desc % 4;
++00372                 if (len)
++00373                         data_per_desc += 4 - len;
++00374                 sts.b_iso_out.rxbytes = data_per_desc;
++00375 
++00376                 dma_desc->buf = dma_ad;
++00377                 dma_desc->status.d32 = sts.d32;
++00378                 dma_desc++;
++00379 
++00381                 sts.b_iso_out.ioc = 0;
++00382                 dma_ad = dwc_ep->dma_addr1;
++00383 
++00384                 offset = 0;
++00385                 for (i = 0; i < dwc_ep->desc_cnt - dwc_ep->pkt_per_frm;
++00386                      i += dwc_ep->pkt_per_frm) {
++00387                         for (j = 0; j < dwc_ep->pkt_per_frm; ++j) {
++00388                                 uint32_t len = (j + 1) * dwc_ep->maxpacket;
++00389                                 if (len > dwc_ep->data_per_frame)
++00390                                         data_per_desc =
++00391                                             dwc_ep->data_per_frame -
++00392                                             j * dwc_ep->maxpacket;
++00393                                 else
++00394                                         data_per_desc = dwc_ep->maxpacket;
++00395                                 len = data_per_desc % 4;
++00396                                 if (len)
++00397                                         data_per_desc += 4 - len;
++00398 
++00399                                 data_per_desc =
++00400                                     sts.b_iso_out.rxbytes = data_per_desc;
++00401                                 dma_desc->buf = dma_ad;
++00402                                 dma_desc->status.d32 = sts.d32;
++00403 
++00404                                 offset += data_per_desc;
++00405                                 dma_desc++;
++00406                                 dma_ad += data_per_desc;
++00407                         }
++00408                 }
++00409                 for (j = 0; j < dwc_ep->pkt_per_frm - 1; ++j) {
++00410                         data_per_desc =
++00411                             ((j + 1) * dwc_ep->maxpacket >
++00412                              dwc_ep->data_per_frame) ? dwc_ep->data_per_frame -
++00413                             j * dwc_ep->maxpacket : dwc_ep->maxpacket;
++00414                         data_per_desc +=
++00415                             (data_per_desc % 4) ? (4 - data_per_desc % 4) : 0;
++00416                         sts.b_iso_out.rxbytes = data_per_desc;
++00417                         dma_desc->buf = dma_ad;
++00418                         dma_desc->status.d32 = sts.d32;
++00419 
++00420                         offset += data_per_desc;
++00421                         dma_desc++;
++00422                         dma_ad += data_per_desc;
++00423                 }
++00424 
++00425                 sts.b_iso_out.ioc = 1;
++00426                 sts.b_iso_out.l = 1;
++00427                 data_per_desc =
++00428                     ((j + 1) * dwc_ep->maxpacket >
++00429                      dwc_ep->data_per_frame) ? dwc_ep->data_per_frame -
++00430                     j * dwc_ep->maxpacket : dwc_ep->maxpacket;
++00431                 data_per_desc +=
++00432                     (data_per_desc % 4) ? (4 - data_per_desc % 4) : 0;
++00433                 sts.b_iso_out.rxbytes = data_per_desc;
++00434 
++00435                 dma_desc->buf = dma_ad;
++00436                 dma_desc->status.d32 = sts.d32;
++00437 
++00438                 dwc_ep->next_frame = 0;
++00439 
++00441                 DWC_WRITE_REG32(&(out_regs->doepdma),
++00442                                 (uint32_t) dwc_ep->iso_dma_desc_addr);
++00443 
++00444         }
++00446         else {
++00447                 dev_dma_desc_sts_t sts = {.d32 = 0 };
++00448                 dwc_otg_dev_dma_desc_t *dma_desc = dwc_ep->iso_desc_addr;
++00449                 dma_addr_t dma_ad;
++00450                 dwc_otg_dev_in_ep_regs_t *in_regs =
++00451                     core_if->dev_if->in_ep_regs[dwc_ep->num];
++00452                 unsigned int frmnumber;
++00453                 fifosize_data_t txfifosize, rxfifosize;
++00454 
++00455                 txfifosize.d32 =
++00456                     DWC_READ_REG32(&core_if->dev_if->
++00457                                    in_ep_regs[dwc_ep->num]->dtxfsts);
++00458                 rxfifosize.d32 =
++00459                     DWC_READ_REG32(&core_if->core_global_regs->grxfsiz);
++00460 
++00461                 addr = &core_if->dev_if->in_ep_regs[dwc_ep->num]->diepctl;
++00462 
++00463                 dma_ad = dwc_ep->dma_addr0;
++00464 
++00465                 dsts.d32 =
++00466                     DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts);
++00467 
++00468                 sts.b_iso_in.bs = BS_HOST_READY;
++00469                 sts.b_iso_in.txsts = 0;
++00470                 sts.b_iso_in.sp =
++00471                     (dwc_ep->data_per_frame % dwc_ep->maxpacket) ? 1 : 0;
++00472                 sts.b_iso_in.ioc = 0;
++00473                 sts.b_iso_in.pid = dwc_ep->pkt_per_frm;
++00474 
++00475                 frmnumber = dwc_ep->next_frame;
++00476 
++00477                 sts.b_iso_in.framenum = frmnumber;
++00478                 sts.b_iso_in.txbytes = dwc_ep->data_per_frame;
++00479                 sts.b_iso_in.l = 0;
++00480 
++00482                 for (i = 0; i < dwc_ep->desc_cnt - 1; i++) {
++00483                         dma_desc->buf = dma_ad;
++00484                         dma_desc->status.d32 = sts.d32;
++00485                         dma_desc++;
++00486 
++00487                         dma_ad += dwc_ep->data_per_frame;
++00488                         sts.b_iso_in.framenum += dwc_ep->bInterval;
++00489                 }
++00490 
++00491                 sts.b_iso_in.ioc = 1;
++00492                 dma_desc->buf = dma_ad;
++00493                 dma_desc->status.d32 = sts.d32;
++00494                 ++dma_desc;
++00495 
++00497                 sts.b_iso_in.ioc = 0;
++00498                 dma_ad = dwc_ep->dma_addr1;
++00499 
++00500                 for (i = 0; i < dwc_ep->desc_cnt - dwc_ep->pkt_per_frm;
++00501                      i += dwc_ep->pkt_per_frm) {
++00502                         dma_desc->buf = dma_ad;
++00503                         dma_desc->status.d32 = sts.d32;
++00504                         dma_desc++;
++00505 
++00506                         dma_ad += dwc_ep->data_per_frame;
++00507                         sts.b_iso_in.framenum += dwc_ep->bInterval;
++00508 
++00509                         sts.b_iso_in.ioc = 0;
++00510                 }
++00511                 sts.b_iso_in.ioc = 1;
++00512                 sts.b_iso_in.l = 1;
++00513 
++00514                 dma_desc->buf = dma_ad;
++00515                 dma_desc->status.d32 = sts.d32;
++00516 
++00517                 dwc_ep->next_frame = sts.b_iso_in.framenum + dwc_ep->bInterval;
++00518 
++00520                 DWC_WRITE_REG32(&(in_regs->diepdma),
++00521                                 (uint32_t) dwc_ep->iso_dma_desc_addr);
++00522         }
++00524         depctl.d32 = 0;
++00525         depctl.b.epena = 1;
++00526         depctl.b.usbactep = 1;
++00527         depctl.b.cnak = 1;
++00528 
++00529         DWC_MODIFY_REG32(addr, depctl.d32, depctl.d32);
++00530         depctl.d32 = DWC_READ_REG32(addr);
++00531 }
++00532 
++00540 void dwc_otg_iso_ep_start_buf_transfer(dwc_otg_core_if_t * core_if,
++00541                                        dwc_ep_t * ep)
++00542 {
++00543         depctl_data_t depctl = {.d32 = 0 };
++00544         volatile uint32_t *addr;
++00545 
++00546         if (ep->is_in) {
++00547                 addr = &core_if->dev_if->in_ep_regs[ep->num]->diepctl;
++00548         } else {
++00549                 addr = &core_if->dev_if->out_ep_regs[ep->num]->doepctl;
++00550         }
++00551 
++00552         if (core_if->dma_enable == 0 || core_if->dma_desc_enable != 0) {
++00553                 return;
++00554         } else {
++00555                 deptsiz_data_t deptsiz = {.d32 = 0 };
++00556 
++00557                 ep->xfer_len =
++00558                     ep->data_per_frame * ep->buf_proc_intrvl / ep->bInterval;
++00559                 ep->pkt_cnt =
++00560                     (ep->xfer_len - 1 + ep->maxpacket) / ep->maxpacket;
++00561                 ep->xfer_count = 0;
++00562                 ep->xfer_buff =
++00563                     (ep->proc_buf_num) ? ep->xfer_buff1 : ep->xfer_buff0;
++00564                 ep->dma_addr =
++00565                     (ep->proc_buf_num) ? ep->dma_addr1 : ep->dma_addr0;
++00566 
++00567                 if (ep->is_in) {
++00568                         /* Program the transfer size and packet count
++00569                          *      as follows: xfersize = N * maxpacket +
++00570                          *      short_packet pktcnt = N + (short_packet
++00571                          *      exist ? 1 : 0) 
++00572                          */
++00573                         deptsiz.b.mc = ep->pkt_per_frm;
++00574                         deptsiz.b.xfersize = ep->xfer_len;
++00575                         deptsiz.b.pktcnt =
++00576                             (ep->xfer_len - 1 + ep->maxpacket) / ep->maxpacket;
++00577                         DWC_WRITE_REG32(&core_if->dev_if->
++00578                                         in_ep_regs[ep->num]->dieptsiz,
++00579                                         deptsiz.d32);
++00580 
++00581                         /* Write the DMA register */
++00582                         DWC_WRITE_REG32(&
++00583                                         (core_if->dev_if->
++00584                                          in_ep_regs[ep->num]->diepdma),
++00585                                         (uint32_t) ep->dma_addr);
++00586 
++00587                 } else {
++00588                         deptsiz.b.pktcnt =
++00589                             (ep->xfer_len + (ep->maxpacket - 1)) /
++00590                             ep->maxpacket;
++00591                         deptsiz.b.xfersize = deptsiz.b.pktcnt * ep->maxpacket;
++00592 
++00593                         DWC_WRITE_REG32(&core_if->dev_if->
++00594                                         out_ep_regs[ep->num]->doeptsiz,
++00595                                         deptsiz.d32);
++00596 
++00597                         /* Write the DMA register */
++00598                         DWC_WRITE_REG32(&
++00599                                         (core_if->dev_if->
++00600                                          out_ep_regs[ep->num]->doepdma),
++00601                                         (uint32_t) ep->dma_addr);
++00602 
++00603                 }
++00605                 depctl.d32 = 0;
++00606                 depctl.b.epena = 1;
++00607                 depctl.b.cnak = 1;
++00608 
++00609                 DWC_MODIFY_REG32(addr, depctl.d32, depctl.d32);
++00610         }
++00611 }
++00612 
++00623 static void dwc_otg_iso_ep_start_transfer(dwc_otg_core_if_t * core_if,
++00624                                           dwc_ep_t * ep)
++00625 {
++00626         if (core_if->dma_enable) {
++00627                 if (core_if->dma_desc_enable) {
++00628                         if (ep->is_in) {
++00629                                 ep->desc_cnt = ep->pkt_cnt / ep->pkt_per_frm;
++00630                         } else {
++00631                                 ep->desc_cnt = ep->pkt_cnt;
++00632                         }
++00633                         dwc_otg_iso_ep_start_ddma_transfer(core_if, ep);
++00634                 } else {
++00635                         if (core_if->pti_enh_enable) {
++00636                                 dwc_otg_iso_ep_start_buf_transfer(core_if, ep);
++00637                         } else {
++00638                                 ep->cur_pkt_addr =
++00639                                     (ep->proc_buf_num) ? ep->
++00640                                     xfer_buff1 : ep->xfer_buff0;
++00641                                 ep->cur_pkt_dma_addr =
++00642                                     (ep->proc_buf_num) ? ep->
++00643                                     dma_addr1 : ep->dma_addr0;
++00644                                 dwc_otg_iso_ep_start_frm_transfer(core_if, ep);
++00645                         }
++00646                 }
++00647         } else {
++00648                 ep->cur_pkt_addr =
++00649                     (ep->proc_buf_num) ? ep->xfer_buff1 : ep->xfer_buff0;
++00650                 ep->cur_pkt_dma_addr =
++00651                     (ep->proc_buf_num) ? ep->dma_addr1 : ep->dma_addr0;
++00652                 dwc_otg_iso_ep_start_frm_transfer(core_if, ep);
++00653         }
++00654 }
++00655 
++00664 void dwc_otg_iso_ep_stop_transfer(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
++00665 {
++00666         depctl_data_t depctl = {.d32 = 0 };
++00667         volatile uint32_t *addr;
++00668 
++00669         if (ep->is_in == 1) {
++00670                 addr = &core_if->dev_if->in_ep_regs[ep->num]->diepctl;
++00671         } else {
++00672                 addr = &core_if->dev_if->out_ep_regs[ep->num]->doepctl;
++00673         }
++00674 
++00675         /* disable the ep */
++00676         depctl.d32 = DWC_READ_REG32(addr);
++00677 
++00678         depctl.b.epdis = 1;
++00679         depctl.b.snak = 1;
++00680 
++00681         DWC_WRITE_REG32(addr, depctl.d32);
++00682 
++00683         if (core_if->dma_desc_enable &&
++00684             ep->iso_desc_addr && ep->iso_dma_desc_addr) {
++00685                 dwc_otg_ep_free_desc_chain(ep->iso_desc_addr,
++00686                                            ep->iso_dma_desc_addr,
++00687                                            ep->desc_cnt * 2);
++00688         }
++00689 
++00690         /* reset varibales */
++00691         ep->dma_addr0 = 0;
++00692         ep->dma_addr1 = 0;
++00693         ep->xfer_buff0 = 0;
++00694         ep->xfer_buff1 = 0;
++00695         ep->data_per_frame = 0;
++00696         ep->data_pattern_frame = 0;
++00697         ep->sync_frame = 0;
++00698         ep->buf_proc_intrvl = 0;
++00699         ep->bInterval = 0;
++00700         ep->proc_buf_num = 0;
++00701         ep->pkt_per_frm = 0;
++00702         ep->pkt_per_frm = 0;
++00703         ep->desc_cnt = 0;
++00704         ep->iso_desc_addr = 0;
++00705         ep->iso_dma_desc_addr = 0;
++00706 }
++00707 
++00708 int dwc_otg_pcd_iso_ep_start(dwc_otg_pcd_t * pcd, void *ep_handle,
++00709                              uint8_t * buf0, uint8_t * buf1, dwc_dma_t dma0,
++00710                              dwc_dma_t dma1, int sync_frame, int dp_frame,
++00711                              int data_per_frame, int start_frame,
++00712                              int buf_proc_intrvl, void *req_handle,
++00713                              int atomic_alloc)
++00714 {
++00715         dwc_otg_pcd_ep_t *ep;
++00716         dwc_irqflags_t flags = 0;
++00717         dwc_ep_t *dwc_ep;
++00718         int32_t frm_data;
++00719         dsts_data_t dsts;
++00720         dwc_otg_core_if_t *core_if;
++00721 
++00722         ep = get_ep_from_handle(pcd, ep_handle);
++00723 
++00724         if (!ep || !ep->desc || ep->dwc_ep.num == 0) {
++00725                 DWC_WARN("bad ep\n");
++00726                 return -DWC_E_INVALID;
++00727         }
++00728 
++00729         DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
++00730         core_if = GET_CORE_IF(pcd);
++00731         dwc_ep = &ep->dwc_ep;
++00732 
++00733         if (ep->iso_req_handle) {
++00734                 DWC_WARN("ISO request in progress\n");
++00735         }
++00736 
++00737         dwc_ep->dma_addr0 = dma0;
++00738         dwc_ep->dma_addr1 = dma1;
++00739 
++00740         dwc_ep->xfer_buff0 = buf0;
++00741         dwc_ep->xfer_buff1 = buf1;
++00742 
++00743         dwc_ep->data_per_frame = data_per_frame;
++00744 
++00746         dwc_ep->data_pattern_frame = dp_frame;
++00747         dwc_ep->sync_frame = sync_frame;
++00748 
++00749         dwc_ep->buf_proc_intrvl = buf_proc_intrvl;
++00750 
++00751         dwc_ep->bInterval = 1 << (ep->desc->bInterval - 1);
++00752 
++00753         dwc_ep->proc_buf_num = 0;
++00754 
++00755         dwc_ep->pkt_per_frm = 0;
++00756         frm_data = ep->dwc_ep.data_per_frame;
++00757         while (frm_data > 0) {
++00758                 dwc_ep->pkt_per_frm++;
++00759                 frm_data -= ep->dwc_ep.maxpacket;
++00760         }
++00761 
++00762         dsts.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts);
++00763 
++00764         if (start_frame == -1) {
++00765                 dwc_ep->next_frame = dsts.b.soffn + 1;
++00766                 if (dwc_ep->bInterval != 1) {
++00767                         dwc_ep->next_frame =
++00768                             dwc_ep->next_frame + (dwc_ep->bInterval - 1 -
++00769                                                   dwc_ep->next_frame %
++00770                                                   dwc_ep->bInterval);
++00771                 }
++00772         } else {
++00773                 dwc_ep->next_frame = start_frame;
++00774         }
++00775 
++00776         if (!core_if->pti_enh_enable) {
++00777                 dwc_ep->pkt_cnt =
++00778                     dwc_ep->buf_proc_intrvl * dwc_ep->pkt_per_frm /
++00779                     dwc_ep->bInterval;
++00780         } else {
++00781                 dwc_ep->pkt_cnt =
++00782                     (dwc_ep->data_per_frame *
++00783                      (dwc_ep->buf_proc_intrvl / dwc_ep->bInterval)
++00784                      - 1 + dwc_ep->maxpacket) / dwc_ep->maxpacket;
++00785         }
++00786 
++00787         if (core_if->dma_desc_enable) {
++00788                 dwc_ep->desc_cnt =
++00789                     dwc_ep->buf_proc_intrvl * dwc_ep->pkt_per_frm /
++00790                     dwc_ep->bInterval;
++00791         }
++00792 
++00793         if (atomic_alloc) {
++00794                 dwc_ep->pkt_info =
++00795                     DWC_ALLOC_ATOMIC(sizeof(iso_pkt_info_t) * dwc_ep->pkt_cnt);
++00796         } else {
++00797                 dwc_ep->pkt_info =
++00798                     DWC_ALLOC(sizeof(iso_pkt_info_t) * dwc_ep->pkt_cnt);
++00799         }
++00800         if (!dwc_ep->pkt_info) {
++00801                 DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
++00802                 return -DWC_E_NO_MEMORY;
++00803         }
++00804         if (core_if->pti_enh_enable) {
++00805                 dwc_memset(dwc_ep->pkt_info, 0,
++00806                            sizeof(iso_pkt_info_t) * dwc_ep->pkt_cnt);
++00807         }
++00808 
++00809         dwc_ep->cur_pkt = 0;
++00810         ep->iso_req_handle = req_handle;
++00811 
++00812         DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
++00813         dwc_otg_iso_ep_start_transfer(core_if, dwc_ep);
++00814         return 0;
++00815 }
++00816 
++00817 int dwc_otg_pcd_iso_ep_stop(dwc_otg_pcd_t * pcd, void *ep_handle,
++00818                             void *req_handle)
++00819 {
++00820         dwc_irqflags_t flags = 0;
++00821         dwc_otg_pcd_ep_t *ep;
++00822         dwc_ep_t *dwc_ep;
++00823 
++00824         ep = get_ep_from_handle(pcd, ep_handle);
++00825         if (!ep || !ep->desc || ep->dwc_ep.num == 0) {
++00826                 DWC_WARN("bad ep\n");
++00827                 return -DWC_E_INVALID;
++00828         }
++00829         dwc_ep = &ep->dwc_ep;
++00830 
++00831         dwc_otg_iso_ep_stop_transfer(GET_CORE_IF(pcd), dwc_ep);
++00832 
++00833         DWC_FREE(dwc_ep->pkt_info);
++00834         DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
++00835         if (ep->iso_req_handle != req_handle) {
++00836                 DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
++00837                 return -DWC_E_INVALID;
++00838         }
++00839 
++00840         DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
++00841 
++00842         ep->iso_req_handle = 0;
++00843         return 0;
++00844 }
++00845 
++00853 void dwc_otg_iso_buffer_done(dwc_otg_pcd_t * pcd, dwc_otg_pcd_ep_t * ep,
++00854                              void *req_handle)
++00855 {
++00856         int i;
++00857         dwc_ep_t *dwc_ep;
++00858 
++00859         dwc_ep = &ep->dwc_ep;
++00860 
++00861         DWC_SPINUNLOCK(ep->pcd->lock);
++00862         pcd->fops->isoc_complete(pcd, ep->priv, ep->iso_req_handle,
++00863                                  dwc_ep->proc_buf_num ^ 0x1);
++00864         DWC_SPINLOCK(ep->pcd->lock);
++00865 
++00866         for (i = 0; i < dwc_ep->pkt_cnt; ++i) {
++00867                 dwc_ep->pkt_info[i].status = 0;
++00868                 dwc_ep->pkt_info[i].offset = 0;
++00869                 dwc_ep->pkt_info[i].length = 0;
++00870         }
++00871 }
++00872 
++00873 int dwc_otg_pcd_get_iso_packet_count(dwc_otg_pcd_t * pcd, void *ep_handle,
++00874                                      void *iso_req_handle)
++00875 {
++00876         dwc_otg_pcd_ep_t *ep;
++00877         dwc_ep_t *dwc_ep;
++00878 
++00879         ep = get_ep_from_handle(pcd, ep_handle);
++00880         if (!ep->desc || ep->dwc_ep.num == 0) {
++00881                 DWC_WARN("bad ep\n");
++00882                 return -DWC_E_INVALID;
++00883         }
++00884         dwc_ep = &ep->dwc_ep;
++00885 
++00886         return dwc_ep->pkt_cnt;
++00887 }
++00888 
++00889 void dwc_otg_pcd_get_iso_packet_params(dwc_otg_pcd_t * pcd, void *ep_handle,
++00890                                        void *iso_req_handle, int packet,
++00891                                        int *status, int *actual, int *offset)
++00892 {
++00893         dwc_otg_pcd_ep_t *ep;
++00894         dwc_ep_t *dwc_ep;
++00895 
++00896         ep = get_ep_from_handle(pcd, ep_handle);
++00897         if (!ep)
++00898                 DWC_WARN("bad ep\n");
++00899 
++00900         dwc_ep = &ep->dwc_ep;
++00901 
++00902         *status = dwc_ep->pkt_info[packet].status;
++00903         *actual = dwc_ep->pkt_info[packet].length;
++00904         *offset = dwc_ep->pkt_info[packet].offset;
++00905 }
++00906 
++00907 #endif /* DWC_EN_ISOC */
++00908 
++00909 static void dwc_otg_pcd_init_ep(dwc_otg_pcd_t * pcd, dwc_otg_pcd_ep_t * pcd_ep,
++00910                                 uint32_t is_in, uint32_t ep_num)
++00911 {
++00912         /* Init EP structure */
++00913         pcd_ep->desc = 0;
++00914         pcd_ep->pcd = pcd;
++00915         pcd_ep->stopped = 1;
++00916         pcd_ep->queue_sof = 0;
++00917 
++00918         /* Init DWC ep structure */
++00919         pcd_ep->dwc_ep.is_in = is_in;
++00920         pcd_ep->dwc_ep.num = ep_num;
++00921         pcd_ep->dwc_ep.active = 0;
++00922         pcd_ep->dwc_ep.tx_fifo_num = 0;
++00923         /* Control until ep is actvated */
++00924         pcd_ep->dwc_ep.type = DWC_OTG_EP_TYPE_CONTROL;
++00925         pcd_ep->dwc_ep.maxpacket = MAX_PACKET_SIZE;
++00926         pcd_ep->dwc_ep.dma_addr = 0;
++00927         pcd_ep->dwc_ep.start_xfer_buff = 0;
++00928         pcd_ep->dwc_ep.xfer_buff = 0;
++00929         pcd_ep->dwc_ep.xfer_len = 0;
++00930         pcd_ep->dwc_ep.xfer_count = 0;
++00931         pcd_ep->dwc_ep.sent_zlp = 0;
++00932         pcd_ep->dwc_ep.total_len = 0;
++00933         pcd_ep->dwc_ep.desc_addr = 0;
++00934         pcd_ep->dwc_ep.dma_desc_addr = 0;
++00935         DWC_CIRCLEQ_INIT(&pcd_ep->queue);
++00936 }
++00937 
++00941 static void dwc_otg_pcd_reinit(dwc_otg_pcd_t * pcd)
++00942 {
++00943         int i;
++00944         uint32_t hwcfg1;
++00945         dwc_otg_pcd_ep_t *ep;
++00946         int in_ep_cntr, out_ep_cntr;
++00947         uint32_t num_in_eps = (GET_CORE_IF(pcd))->dev_if->num_in_eps;
++00948         uint32_t num_out_eps = (GET_CORE_IF(pcd))->dev_if->num_out_eps;
++00949 
++00953         ep = &pcd->ep0;
++00954         dwc_otg_pcd_init_ep(pcd, ep, 0, 0);
++00955 
++00956         in_ep_cntr = 0;
++00957         hwcfg1 = (GET_CORE_IF(pcd))->hwcfg1.d32 >> 3;
++00958         for (i = 1; in_ep_cntr < num_in_eps; i++) {
++00959                 if ((hwcfg1 & 0x1) == 0) {
++00960                         dwc_otg_pcd_ep_t *ep = &pcd->in_ep[in_ep_cntr];
++00961                         in_ep_cntr++;
++00967                         dwc_otg_pcd_init_ep(pcd, ep, 1 /* IN */ , i);
++00968 
++00969                         DWC_CIRCLEQ_INIT(&ep->queue);
++00970                 }
++00971                 hwcfg1 >>= 2;
++00972         }
++00973 
++00974         out_ep_cntr = 0;
++00975         hwcfg1 = (GET_CORE_IF(pcd))->hwcfg1.d32 >> 2;
++00976         for (i = 1; out_ep_cntr < num_out_eps; i++) {
++00977                 if ((hwcfg1 & 0x1) == 0) {
++00978                         dwc_otg_pcd_ep_t *ep = &pcd->out_ep[out_ep_cntr];
++00979                         out_ep_cntr++;
++00985                         dwc_otg_pcd_init_ep(pcd, ep, 0 /* OUT */ , i);
++00986                         DWC_CIRCLEQ_INIT(&ep->queue);
++00987                 }
++00988                 hwcfg1 >>= 2;
++00989         }
++00990 
++00991         pcd->ep0state = EP0_DISCONNECT;
++00992         pcd->ep0.dwc_ep.maxpacket = MAX_EP0_SIZE;
++00993         pcd->ep0.dwc_ep.type = DWC_OTG_EP_TYPE_CONTROL;
++00994 }
++00995 
++01000 static void srp_timeout(void *ptr)
++01001 {
++01002         gotgctl_data_t gotgctl;
++01003         dwc_otg_core_if_t *core_if = (dwc_otg_core_if_t *) ptr;
++01004         volatile uint32_t *addr = &core_if->core_global_regs->gotgctl;
++01005 
++01006         gotgctl.d32 = DWC_READ_REG32(addr);
++01007 
++01008         core_if->srp_timer_started = 0;
++01009         
++01010         if (core_if->adp_enable) {
++01011                 if (gotgctl.b.bsesvld == 0) {
++01012                         gpwrdn_data_t gpwrdn = {.d32 = 0 };
++01013                         DWC_PRINTF("SRP Timeout BSESSVLD = 0\n");
++01014                         /* Power off the core */
++01015                         if (core_if->power_down == 2) {
++01016                                 gpwrdn.b.pwrdnswtch = 1;
++01017                                 DWC_MODIFY_REG32(&core_if->core_global_regs->
++01018                                         gpwrdn, gpwrdn.d32, 0);
++01019                         }
++01020 
++01021                         gpwrdn.d32 = 0;
++01022                         gpwrdn.b.pmuintsel = 1;
++01023                         gpwrdn.b.pmuactv = 1;
++01024                         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
++01025                         dwc_otg_adp_probe_start(core_if);
++01026                 } else {
++01027                         DWC_PRINTF("SRP Timeout BSESSVLD = 1\n");
++01028                         core_if->op_state = B_PERIPHERAL;
++01029                         dwc_otg_core_init(core_if);
++01030                         dwc_otg_enable_global_interrupts(core_if);
++01031                         cil_pcd_start(core_if);
++01032                 }
++01033         }
++01034 
++01035         if ((core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS) &&
++01036             (core_if->core_params->i2c_enable)) {
++01037                 DWC_PRINTF("SRP Timeout\n");
++01038 
++01039                 if ((core_if->srp_success) && (gotgctl.b.bsesvld)) {
++01040                         if (core_if->pcd_cb && core_if->pcd_cb->resume_wakeup) {
++01041                                 core_if->pcd_cb->resume_wakeup(core_if->pcd_cb->p);
++01042                         }
++01043 
++01044                         /* Clear Session Request */
++01045                         gotgctl.d32 = 0;
++01046                         gotgctl.b.sesreq = 1;
++01047                         DWC_MODIFY_REG32(&core_if->core_global_regs->gotgctl,
++01048                                          gotgctl.d32, 0);
++01049 
++01050                         core_if->srp_success = 0;
++01051                 } else {
++01052                         __DWC_ERROR("Device not connected/responding\n");
++01053                         gotgctl.b.sesreq = 0;
++01054                         DWC_WRITE_REG32(addr, gotgctl.d32);
++01055                 }
++01056         } else if (gotgctl.b.sesreq) {
++01057                 DWC_PRINTF("SRP Timeout\n");
++01058 
++01059                 __DWC_ERROR("Device not connected/responding\n");
++01060                 gotgctl.b.sesreq = 0;
++01061                 DWC_WRITE_REG32(addr, gotgctl.d32);
++01062         } else {
++01063                 DWC_PRINTF(" SRP GOTGCTL=%0x\n", gotgctl.d32);
++01064         }
++01065 }
++01066 
++01071 extern void start_next_request(dwc_otg_pcd_ep_t * ep);
++01072 
++01073 static void start_xfer_tasklet_func(void *data)
++01074 {
++01075         dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *) data;
++01076         dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
++01077 
++01078         int i;
++01079         depctl_data_t diepctl;
++01080 
++01081         DWC_DEBUGPL(DBG_PCDV, "Start xfer tasklet\n");
++01082 
++01083         diepctl.d32 = DWC_READ_REG32(&core_if->dev_if->in_ep_regs[0]->diepctl);
++01084 
++01085         if (pcd->ep0.queue_sof) {
++01086                 pcd->ep0.queue_sof = 0;
++01087                 start_next_request(&pcd->ep0);
++01088                 // break;
++01089         }
++01090 
++01091         for (i = 0; i < core_if->dev_if->num_in_eps; i++) {
++01092                 depctl_data_t diepctl;
++01093                 diepctl.d32 =
++01094                     DWC_READ_REG32(&core_if->dev_if->in_ep_regs[i]->diepctl);
++01095 
++01096                 if (pcd->in_ep[i].queue_sof) {
++01097                         pcd->in_ep[i].queue_sof = 0;
++01098                         start_next_request(&pcd->in_ep[i]);
++01099                         // break;
++01100                 }
++01101         }
++01102 
++01103         return;
++01104 }
++01105 
++01110 dwc_otg_pcd_t *dwc_otg_pcd_init(dwc_otg_core_if_t * core_if)
++01111 {
++01112         dwc_otg_pcd_t *pcd = NULL;
++01113         dwc_otg_dev_if_t *dev_if;
++01114         int i;
++01115 
++01116         /*
++01117          * Allocate PCD structure
++01118          */
++01119         pcd = DWC_ALLOC(sizeof(dwc_otg_pcd_t));
++01120 
++01121         if (pcd == NULL) {
++01122                 return NULL;
++01123         }
++01124 
++01125         pcd->lock = DWC_SPINLOCK_ALLOC();
++01126         if (!pcd->lock) {
++01127                 DWC_ERROR("Could not allocate lock for pcd");
++01128                 DWC_FREE(pcd);
++01129                 return NULL;
++01130         }
++01131         /* Set core_if's lock pointer to hcd->lock */
++01132         core_if->lock = pcd->lock;
++01133         pcd->core_if = core_if;
++01134 
++01135         dev_if = core_if->dev_if;
++01136         dev_if->isoc_ep = NULL;
++01137 
++01138         if (core_if->hwcfg4.b.ded_fifo_en) {
++01139                 DWC_PRINTF("Dedicated Tx FIFOs mode\n");
++01140         } else {
++01141                 DWC_PRINTF("Shared Tx FIFO mode\n");
++01142         }
++01143 
++01144         /*
++01145          * Initialized the Core for Device mode here if there is nod ADP support. 
++01146          * Otherwise it will be done later in dwc_otg_adp_start routine.
++01147          */                                                                                                                                                              
++01148         if (dwc_otg_is_device_mode(core_if) /*&& !core_if->adp_enable*/) {
++01149                 dwc_otg_core_dev_init(core_if);
++01150         }
++01151 
++01152         /*
++01153          * Register the PCD Callbacks.
++01154          */
++01155         dwc_otg_cil_register_pcd_callbacks(core_if, &pcd_callbacks, pcd);
++01156 
++01157         /*
++01158          * Initialize the DMA buffer for SETUP packets
++01159          */
++01160         if (GET_CORE_IF(pcd)->dma_enable) {
++01161                 pcd->setup_pkt =
++01162                     DWC_DMA_ALLOC(sizeof(*pcd->setup_pkt) * 5,
++01163                                   &pcd->setup_pkt_dma_handle);
++01164                 if (pcd->setup_pkt == NULL) {
++01165                         DWC_FREE(pcd);
++01166                         return NULL;
++01167                 }
++01168 
++01169                 pcd->status_buf =
++01170                     DWC_DMA_ALLOC(sizeof(uint16_t),
++01171                                   &pcd->status_buf_dma_handle);
++01172                 if (pcd->status_buf == NULL) {
++01173                         DWC_DMA_FREE(sizeof(*pcd->setup_pkt) * 5,
++01174                                      pcd->setup_pkt, pcd->setup_pkt_dma_handle);
++01175                         DWC_FREE(pcd);
++01176                         return NULL;
++01177                 }
++01178 
++01179                 if (GET_CORE_IF(pcd)->dma_desc_enable) {
++01180                         dev_if->setup_desc_addr[0] =
++01181                             dwc_otg_ep_alloc_desc_chain(&dev_if->
++01182                                                         dma_setup_desc_addr[0],
++01183                                                         1);
++01184                         dev_if->setup_desc_addr[1] =
++01185                             dwc_otg_ep_alloc_desc_chain(&dev_if->
++01186                                                         dma_setup_desc_addr[1],
++01187                                                         1);
++01188                         dev_if->in_desc_addr =
++01189                             dwc_otg_ep_alloc_desc_chain(&dev_if->
++01190                                                         dma_in_desc_addr, 1);
++01191                         dev_if->out_desc_addr =
++01192                             dwc_otg_ep_alloc_desc_chain(&dev_if->
++01193                                                         dma_out_desc_addr, 1);
++01194 
++01195                         if (dev_if->setup_desc_addr[0] == 0
++01196                             || dev_if->setup_desc_addr[1] == 0
++01197                             || dev_if->in_desc_addr == 0
++01198                             || dev_if->out_desc_addr == 0) {
++01199 
++01200                                 if (dev_if->out_desc_addr)
++01201                                         dwc_otg_ep_free_desc_chain(dev_if->
++01202                                                                    out_desc_addr,
++01203                                                                    dev_if->
++01204                                                                    dma_out_desc_addr,
++01205                                                                    1);
++01206                                 if (dev_if->in_desc_addr)
++01207                                         dwc_otg_ep_free_desc_chain(dev_if->
++01208                                                                    in_desc_addr,
++01209                                                                    dev_if->
++01210                                                                    dma_in_desc_addr,
++01211                                                                    1);
++01212                                 if (dev_if->setup_desc_addr[1])
++01213                                         dwc_otg_ep_free_desc_chain(dev_if->
++01214                                                                    setup_desc_addr
++01215                                                                    [1],
++01216                                                                    dev_if->
++01217                                                                    dma_setup_desc_addr
++01218                                                                    [1], 1);
++01219                                 if (dev_if->setup_desc_addr[0])
++01220                                         dwc_otg_ep_free_desc_chain(dev_if->
++01221                                                                    setup_desc_addr
++01222                                                                    [0],
++01223                                                                    dev_if->
++01224                                                                    dma_setup_desc_addr
++01225                                                                    [0], 1);
++01226 
++01227                                 DWC_DMA_FREE(sizeof(*pcd->setup_pkt) * 5,
++01228                                              pcd->setup_pkt,
++01229                                              pcd->setup_pkt_dma_handle);
++01230                                 DWC_DMA_FREE(sizeof(*pcd->status_buf),
++01231                                              pcd->status_buf,
++01232                                              pcd->status_buf_dma_handle);
++01233 
++01234                                 DWC_FREE(pcd);
++01235 
++01236                                 return NULL;
++01237                         }
++01238                 }
++01239         } else {
++01240                 pcd->setup_pkt = DWC_ALLOC(sizeof(*pcd->setup_pkt) * 5);
++01241                 if (pcd->setup_pkt == NULL) {
++01242                         DWC_FREE(pcd);
++01243                         return NULL;
++01244                 }
++01245 
++01246                 pcd->status_buf = DWC_ALLOC(sizeof(uint16_t));
++01247                 if (pcd->status_buf == NULL) {
++01248                         DWC_FREE(pcd->setup_pkt);
++01249                         DWC_FREE(pcd);
++01250                         return NULL;
++01251                 }
++01252         }
++01253 
++01254         dwc_otg_pcd_reinit(pcd);
++01255 
++01256         /* Allocate the cfi object for the PCD */
++01257 #ifdef DWC_UTE_CFI
++01258         pcd->cfi = DWC_ALLOC(sizeof(cfiobject_t));
++01259         if (NULL == pcd->cfi)
++01260                 goto fail;
++01261         if (init_cfi(pcd->cfi)) {
++01262                 CFI_INFO("%s: Failed to init the CFI object\n", __func__);
++01263                 goto fail;
++01264         }
++01265 #endif
++01266 
++01267         /* Initialize tasklets */
++01268         pcd->start_xfer_tasklet = DWC_TASK_ALLOC("xfer_tasklet",
++01269                                                  start_xfer_tasklet_func, pcd);
++01270         pcd->test_mode_tasklet = DWC_TASK_ALLOC("test_mode_tasklet",
++01271                                                 do_test_mode, pcd);
++01272 
++01273         /* Initialize SRP timer */
++01274         core_if->srp_timer = DWC_TIMER_ALLOC("SRP TIMER", srp_timeout, core_if);
++01275         
++01276         if (core_if->core_params->dev_out_nak) {
++01281                 for(i = 0; i < MAX_EPS_CHANNELS; i++) {
++01282                         pcd->core_if->ep_xfer_timer[i] =
++01283                                 DWC_TIMER_ALLOC("ep timer", ep_xfer_timeout,
++01284                                 &pcd->core_if->ep_xfer_info[i]);
++01285                 }
++01286         }
++01287         
++01288         return pcd;
++01289 #ifdef DWC_UTE_CFI
++01290 fail:
++01291 #endif
++01292         if (pcd->setup_pkt)
++01293                 DWC_FREE(pcd->setup_pkt);
++01294         if (pcd->status_buf)
++01295                 DWC_FREE(pcd->status_buf);
++01296 #ifdef DWC_UTE_CFI
++01297         if (pcd->cfi)
++01298                 DWC_FREE(pcd->cfi);
++01299 #endif
++01300         if (pcd)
++01301                 DWC_FREE(pcd);
++01302         return NULL;
++01303 
++01304 }
++01305 
++01309 void dwc_otg_pcd_remove(dwc_otg_pcd_t * pcd)
++01310 {
++01311         dwc_otg_dev_if_t *dev_if = GET_CORE_IF(pcd)->dev_if;
++01312         int i;
++01313         if (pcd->core_if->core_params->dev_out_nak) {
++01314                 for (i = 0; i < MAX_EPS_CHANNELS; i++) {
++01315                         DWC_TIMER_CANCEL(pcd->core_if->ep_xfer_timer[i]);
++01316                         pcd->core_if->ep_xfer_info[i].state = 0;
++01317                 }
++01318         }
++01319 
++01320         if (GET_CORE_IF(pcd)->dma_enable) {
++01321                 DWC_DMA_FREE(sizeof(*pcd->setup_pkt) * 5, pcd->setup_pkt,
++01322                              pcd->setup_pkt_dma_handle);
++01323                 DWC_DMA_FREE(sizeof(uint16_t), pcd->status_buf,
++01324                              pcd->status_buf_dma_handle);
++01325                 if (GET_CORE_IF(pcd)->dma_desc_enable) {
++01326                         dwc_otg_ep_free_desc_chain(dev_if->setup_desc_addr[0],
++01327                                                    dev_if->dma_setup_desc_addr
++01328                                                    [0], 1);
++01329                         dwc_otg_ep_free_desc_chain(dev_if->setup_desc_addr[1],
++01330                                                    dev_if->dma_setup_desc_addr
++01331                                                    [1], 1);
++01332                         dwc_otg_ep_free_desc_chain(dev_if->in_desc_addr,
++01333                                                    dev_if->dma_in_desc_addr, 1);
++01334                         dwc_otg_ep_free_desc_chain(dev_if->out_desc_addr,
++01335                                                    dev_if->dma_out_desc_addr,
++01336                                                    1);
++01337                 }
++01338         } else {
++01339                 DWC_FREE(pcd->setup_pkt);
++01340                 DWC_FREE(pcd->status_buf);
++01341         }
++01342         DWC_SPINLOCK_FREE(pcd->lock);
++01343         /* Set core_if's lock pointer to NULL */
++01344         pcd->core_if->lock = NULL;
++01345 
++01346         DWC_TASK_FREE(pcd->start_xfer_tasklet);
++01347         DWC_TASK_FREE(pcd->test_mode_tasklet);
++01348         if (pcd->core_if->core_params->dev_out_nak) {
++01349                 for (i = 0; i < MAX_EPS_CHANNELS; i++) {
++01350                         if (pcd->core_if->ep_xfer_timer[i]) {
++01351                                         DWC_TIMER_FREE(pcd->core_if->ep_xfer_timer[i]);
++01352                         }
++01353                 }
++01354         }
++01355 
++01356 /* Release the CFI object's dynamic memory */
++01357 #ifdef DWC_UTE_CFI
++01358         if (pcd->cfi->ops.release) {
++01359                 pcd->cfi->ops.release(pcd->cfi);
++01360         }
++01361 #endif
++01362 
++01363         DWC_FREE(pcd);
++01364 }
++01365 
++01369 uint32_t dwc_otg_pcd_is_dualspeed(dwc_otg_pcd_t * pcd)
++01370 {
++01371         dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
++01372 
++01373         if ((core_if->core_params->speed == DWC_SPEED_PARAM_FULL) ||
++01374             ((core_if->hwcfg2.b.hs_phy_type == 2) &&
++01375              (core_if->hwcfg2.b.fs_phy_type == 1) &&
++01376              (core_if->core_params->ulpi_fs_ls))) {
++01377                 return 0;
++01378         }
++01379 
++01380         return 1;
++01381 }
++01382 
++01386 uint32_t dwc_otg_pcd_is_otg(dwc_otg_pcd_t * pcd)
++01387 {
++01388         dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
++01389         gusbcfg_data_t usbcfg = {.d32 = 0 };
++01390 
++01391         usbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
++01392         if (!usbcfg.b.srpcap || !usbcfg.b.hnpcap) {
++01393                 return 0;
++01394         }
++01395 
++01396         return 1;
++01397 }
++01398 
++01403 static uint32_t assign_tx_fifo(dwc_otg_core_if_t * core_if)
++01404 {
++01405         uint32_t TxMsk = 1;
++01406         int i;
++01407 
++01408         for (i = 0; i < core_if->hwcfg4.b.num_in_eps; ++i) {
++01409                 if ((TxMsk & core_if->tx_msk) == 0) {
++01410                         core_if->tx_msk |= TxMsk;
++01411                         return i + 1;
++01412                 }
++01413                 TxMsk <<= 1;
++01414         }
++01415         return 0;
++01416 }
++01417 
++01422 static uint32_t assign_perio_tx_fifo(dwc_otg_core_if_t * core_if)
++01423 {
++01424         uint32_t PerTxMsk = 1;
++01425         int i;
++01426         for (i = 0; i < core_if->hwcfg4.b.num_dev_perio_in_ep; ++i) {
++01427                 if ((PerTxMsk & core_if->p_tx_msk) == 0) {
++01428                         core_if->p_tx_msk |= PerTxMsk;
++01429                         return i + 1;
++01430                 }
++01431                 PerTxMsk <<= 1;
++01432         }
++01433         return 0;
++01434 }
++01435 
++01440 static void release_perio_tx_fifo(dwc_otg_core_if_t * core_if,
++01441                                   uint32_t fifo_num)
++01442 {
++01443         core_if->p_tx_msk =
++01444             (core_if->p_tx_msk & (1 << (fifo_num - 1))) ^ core_if->p_tx_msk;
++01445 }
++01446 
++01451 static void release_tx_fifo(dwc_otg_core_if_t * core_if, uint32_t fifo_num)
++01452 {
++01453         core_if->tx_msk =
++01454             (core_if->tx_msk & (1 << (fifo_num - 1))) ^ core_if->tx_msk;
++01455 }
++01456 
++01461 int dwc_otg_pcd_ep_enable(dwc_otg_pcd_t * pcd,
++01462                           const uint8_t * ep_desc, void *usb_ep)
++01463 {
++01464         int num, dir;
++01465         dwc_otg_pcd_ep_t *ep = NULL;
++01466         const usb_endpoint_descriptor_t *desc;
++01467         dwc_irqflags_t flags;
++01468         fifosize_data_t dptxfsiz = {.d32 = 0 };
++01469         gdfifocfg_data_t gdfifocfg = {.d32 = 0 };
++01470         gdfifocfg_data_t gdfifocfgbase = {.d32 = 0 };
++01471         int retval = 0;
++01472         int i, epcount;
++01473 
++01474         desc = (const usb_endpoint_descriptor_t *)ep_desc;
++01475 
++01476         if (!desc) {
++01477                 pcd->ep0.priv = usb_ep;
++01478                 ep = &pcd->ep0;
++01479                 retval = -DWC_E_INVALID;
++01480                 goto out;
++01481         }
++01482 
++01483         num = UE_GET_ADDR(desc->bEndpointAddress);
++01484         dir = UE_GET_DIR(desc->bEndpointAddress);
++01485 
++01486         if (!desc->wMaxPacketSize) {
++01487                 DWC_WARN("bad maxpacketsize\n");
++01488                 retval = -DWC_E_INVALID;
++01489                 goto out;
++01490         }
++01491 
++01492         if (dir == UE_DIR_IN) {
++01493                 epcount = pcd->core_if->dev_if->num_in_eps;
++01494                 for (i = 0; i < epcount; i++) {
++01495                         if (num == pcd->in_ep[i].dwc_ep.num) {
++01496                                 ep = &pcd->in_ep[i];
++01497                                 break;
++01498                         }
++01499                 }
++01500         } else {
++01501                 epcount = pcd->core_if->dev_if->num_out_eps;
++01502                 for (i = 0; i < epcount; i++) {
++01503                         if (num == pcd->out_ep[i].dwc_ep.num) {
++01504                                 ep = &pcd->out_ep[i];
++01505                                 break;
++01506                         }
++01507                 }
++01508         }
++01509 
++01510         if (!ep) {
++01511                 DWC_WARN("bad address\n");
++01512                 retval = -DWC_E_INVALID;
++01513                 goto out;
++01514         }
++01515 
++01516         DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
++01517 
++01518         ep->desc = desc;
++01519         ep->priv = usb_ep;
++01520 
++01521         /*
++01522          * Activate the EP
++01523          */
++01524         ep->stopped = 0;
++01525 
++01526         ep->dwc_ep.is_in = (dir == UE_DIR_IN);
++01527         ep->dwc_ep.maxpacket = UGETW(desc->wMaxPacketSize);
++01528 
++01529         ep->dwc_ep.type = desc->bmAttributes & UE_XFERTYPE;
++01530 
++01531         if (ep->dwc_ep.is_in) {
++01532                 if (!GET_CORE_IF(pcd)->en_multiple_tx_fifo) {
++01533                         ep->dwc_ep.tx_fifo_num = 0;
++01534 
++01535                         if (ep->dwc_ep.type == UE_ISOCHRONOUS) {
++01536                                 /*
++01537                                  * if ISOC EP then assign a Periodic Tx FIFO.
++01538                                  */
++01539                                 ep->dwc_ep.tx_fifo_num =
++01540                                     assign_perio_tx_fifo(GET_CORE_IF(pcd));
++01541                         }
++01542                 } else {
++01543                         /*
++01544                          * if Dedicated FIFOs mode is on then assign a Tx FIFO.
++01545                          */
++01546                         ep->dwc_ep.tx_fifo_num =
++01547                             assign_tx_fifo(GET_CORE_IF(pcd));
++01548                 }
++01549 
++01550                 /* Calculating EP info controller base address */
++01551                 if (ep->dwc_ep.tx_fifo_num && GET_CORE_IF(pcd)->en_multiple_tx_fifo) {
++01552                         gdfifocfg.d32 =
++01553                             DWC_READ_REG32(&GET_CORE_IF(pcd)->core_global_regs->
++01554                                            gdfifocfg);
++01555                         gdfifocfgbase.d32 = gdfifocfg.d32 >> 16;
++01556                         dptxfsiz.d32 =
++01557                             (DWC_READ_REG32
++01558                              (&GET_CORE_IF(pcd)->
++01559                               core_global_regs->dtxfsiz[ep->dwc_ep.
++01560                                                         tx_fifo_num-1]) >> 16);
++01561                         gdfifocfg.b.epinfobase =
++01562                             gdfifocfgbase.d32 + dptxfsiz.d32;
++01563                         DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->
++01564                                         gdfifocfg, gdfifocfg.d32);
++01565                 }
++01566         }
++01567         /* Set initial data PID. */
++01568         if (ep->dwc_ep.type == UE_BULK) {
++01569                 ep->dwc_ep.data_pid_start = 0;
++01570         }
++01571 
++01572         /* Alloc DMA Descriptors */
++01573         if (GET_CORE_IF(pcd)->dma_desc_enable) {
++01574 #ifndef DWC_UTE_PER_IO
++01575                 if (ep->dwc_ep.type != UE_ISOCHRONOUS) {
++01576 #endif
++01577                         ep->dwc_ep.desc_addr =
++01578                             dwc_otg_ep_alloc_desc_chain(&ep->
++01579                                                         dwc_ep.dma_desc_addr,
++01580                                                         MAX_DMA_DESC_CNT);
++01581                         if (!ep->dwc_ep.desc_addr) {
++01582                                 DWC_WARN("%s, can't allocate DMA descriptor\n",
++01583                                          __func__);
++01584                                 retval = -DWC_E_SHUTDOWN;
++01585                                 DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
++01586                                 goto out;
++01587                         }
++01588 #ifndef DWC_UTE_PER_IO
++01589                 }
++01590 #endif
++01591         }
++01592 
++01593         DWC_DEBUGPL(DBG_PCD, "Activate %s: type=%d, mps=%d desc=%p\n",
++01594                     (ep->dwc_ep.is_in ? "IN" : "OUT"),
++01595                     ep->dwc_ep.type, ep->dwc_ep.maxpacket, ep->desc);
++01596 #ifdef DWC_UTE_PER_IO
++01597         ep->dwc_ep.xiso_bInterval = 1 << (ep->desc->bInterval - 1);
++01598 #endif
++01599         if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) {
++01600                 ep->dwc_ep.bInterval = 1 << (ep->desc->bInterval - 1);
++01601                 ep->dwc_ep.frame_num = 0xFFFFFFFF;
++01602         }               
++01603 
++01604         dwc_otg_ep_activate(GET_CORE_IF(pcd), &ep->dwc_ep);
++01605 
++01606 #ifdef DWC_UTE_CFI
++01607         if (pcd->cfi->ops.ep_enable) {
++01608                 pcd->cfi->ops.ep_enable(pcd->cfi, pcd, ep);
++01609         }
++01610 #endif
++01611 
++01612         DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
++01613 
++01614 out:
++01615         return retval;
++01616 }
++01617 
++01622 int dwc_otg_pcd_ep_disable(dwc_otg_pcd_t * pcd, void *ep_handle)
++01623 {
++01624         dwc_otg_pcd_ep_t *ep;
++01625         dwc_irqflags_t flags;
++01626         dwc_otg_dev_dma_desc_t *desc_addr;
++01627         dwc_dma_t dma_desc_addr;
++01628         gdfifocfg_data_t gdfifocfgbase = {.d32 = 0 };
++01629         gdfifocfg_data_t gdfifocfg = {.d32 = 0 };
++01630         fifosize_data_t dptxfsiz = {.d32 = 0 };
++01631 
++01632         ep = get_ep_from_handle(pcd, ep_handle);
++01633 
++01634         if (!ep || !ep->desc) {
++01635                 DWC_DEBUGPL(DBG_PCD, "bad ep address\n");
++01636                 return -DWC_E_INVALID;
++01637         }
++01638 
++01639         DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
++01640 
++01641         dwc_otg_request_nuke(ep);
++01642 
++01643         dwc_otg_ep_deactivate(GET_CORE_IF(pcd), &ep->dwc_ep);
++01644         if (pcd->core_if->core_params->dev_out_nak)
++01645         {
++01646                 DWC_TIMER_CANCEL(pcd->core_if->ep_xfer_timer[ep->dwc_ep.num]);
++01647                 pcd->core_if->ep_xfer_info[ep->dwc_ep.num].state = 0;
++01648         }
++01649         ep->desc = NULL;
++01650         ep->stopped = 1;
++01651 
++01652         gdfifocfg.d32 =
++01653             DWC_READ_REG32(&GET_CORE_IF(pcd)->core_global_regs->gdfifocfg);
++01654         gdfifocfgbase.d32 = gdfifocfg.d32 >> 16;
++01655 
++01656         if (ep->dwc_ep.is_in) {
++01657                 if (GET_CORE_IF(pcd)->en_multiple_tx_fifo) {
++01658                         /* Flush the Tx FIFO */
++01659                         dwc_otg_flush_tx_fifo(GET_CORE_IF(pcd), ep->dwc_ep.tx_fifo_num);
++01660                 }
++01661                 release_perio_tx_fifo(GET_CORE_IF(pcd), ep->dwc_ep.tx_fifo_num);
++01662                 release_tx_fifo(GET_CORE_IF(pcd), ep->dwc_ep.tx_fifo_num);
++01663                 if (GET_CORE_IF(pcd)->en_multiple_tx_fifo) {
++01664                         /* Decreasing EPinfo Base Addr */
++01665                         dptxfsiz.d32 =
++01666                             (DWC_READ_REG32
++01667                              (&GET_CORE_IF(pcd)->
++01668                                 core_global_regs->dtxfsiz[ep->dwc_ep.tx_fifo_num-1]) >> 16);
++01669                         gdfifocfg.b.epinfobase = gdfifocfgbase.d32 - dptxfsiz.d32;
++01670                         DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gdfifocfg,
++01671                                         gdfifocfg.d32);
++01672                 }
++01673         }
++01674 
++01675         /* Free DMA Descriptors */
++01676         if (GET_CORE_IF(pcd)->dma_desc_enable) {
++01677                 if (ep->dwc_ep.type != UE_ISOCHRONOUS) {
++01678                         desc_addr = ep->dwc_ep.desc_addr;
++01679                         dma_desc_addr = ep->dwc_ep.dma_desc_addr;
++01680 
++01681                         /* Cannot call dma_free_coherent() with IRQs disabled */
++01682                         DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
++01683                         dwc_otg_ep_free_desc_chain(desc_addr, dma_desc_addr,
++01684                                                    MAX_DMA_DESC_CNT);
++01685 
++01686                         goto out_unlocked;
++01687                 }
++01688         }
++01689         DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
++01690 
++01691 out_unlocked:
++01692         DWC_DEBUGPL(DBG_PCD, "%d %s disabled\n", ep->dwc_ep.num,
++01693                     ep->dwc_ep.is_in ? "IN" : "OUT");
++01694         return 0;
++01695 
++01696 }
++01697 
++01698 /******************************************************************************/
++01699 #ifdef DWC_UTE_PER_IO
++01700 
++01705 void dwc_pcd_xiso_ereq_free(dwc_otg_pcd_ep_t * ep, dwc_otg_pcd_request_t * req)
++01706 {
++01707         DWC_FREE(req->ext_req.per_io_frame_descs);
++01708         DWC_FREE(req);
++01709 }
++01710 
++01715 int dwc_otg_pcd_xiso_start_next_request(dwc_otg_pcd_t * pcd,
++01716                                         dwc_otg_pcd_ep_t * ep)
++01717 {
++01718         int i;
++01719         dwc_otg_pcd_request_t *req = NULL;
++01720         dwc_ep_t *dwcep = NULL;
++01721         struct dwc_iso_xreq_port *ereq = NULL;
++01722         struct dwc_iso_pkt_desc_port *ddesc_iso;
++01723         uint16_t nat;
++01724         depctl_data_t diepctl;
++01725 
++01726         dwcep = &ep->dwc_ep;
++01727 
++01728         if (dwcep->xiso_active_xfers > 0) {
++01729 #if 0   //Disable this to decrease s/w overhead that is crucial for Isoc transfers
++01730                 DWC_WARN("There are currently active transfers for EP%d \
++01731                                 (active=%d; queued=%d)", dwcep->num, dwcep->xiso_active_xfers, 
++01732                                 dwcep->xiso_queued_xfers);
++01733 #endif
++01734                 return 0;
++01735         }
++01736 
++01737         nat = UGETW(ep->desc->wMaxPacketSize);
++01738         nat = (nat >> 11) & 0x03;
++01739 
++01740         if (!DWC_CIRCLEQ_EMPTY(&ep->queue)) {
++01741                 req = DWC_CIRCLEQ_FIRST(&ep->queue);
++01742                 ereq = &req->ext_req;
++01743                 ep->stopped = 0;
++01744 
++01745                 /* Get the frame number */
++01746                 dwcep->xiso_frame_num =
++01747                     dwc_otg_get_frame_number(GET_CORE_IF(pcd));
++01748                 DWC_DEBUG("FRM_NUM=%d", dwcep->xiso_frame_num);
++01749 
++01750                 ddesc_iso = ereq->per_io_frame_descs;
++01751 
++01752                 if (dwcep->is_in) {
++01753                         /* Setup DMA Descriptor chain for IN Isoc request */
++01754                         for (i = 0; i < ereq->pio_pkt_count; i++) {
++01755                                 //if ((i % (nat + 1)) == 0)
++01756                                 if ( i > 0 )
++01757                                         dwcep->xiso_frame_num = (dwcep->xiso_bInterval +
++01758                                                                                 dwcep->xiso_frame_num) & 0x3FFF;
++01759                                 dwcep->desc_addr[i].buf =
++01760                                     req->dma + ddesc_iso[i].offset;
++01761                                 dwcep->desc_addr[i].status.b_iso_in.txbytes =
++01762                                     ddesc_iso[i].length;
++01763                                 dwcep->desc_addr[i].status.b_iso_in.framenum =
++01764                                     dwcep->xiso_frame_num;
++01765                                 dwcep->desc_addr[i].status.b_iso_in.bs =
++01766                                     BS_HOST_READY;
++01767                                 dwcep->desc_addr[i].status.b_iso_in.txsts = 0;
++01768                                 dwcep->desc_addr[i].status.b_iso_in.sp =
++01769                                     (ddesc_iso[i].length %
++01770                                      dwcep->maxpacket) ? 1 : 0;
++01771                                 dwcep->desc_addr[i].status.b_iso_in.ioc = 0;
++01772                                 dwcep->desc_addr[i].status.b_iso_in.pid = nat + 1;
++01773                                 dwcep->desc_addr[i].status.b_iso_in.l = 0;
++01774 
++01775                                 /* Process the last descriptor */
++01776                                 if (i == ereq->pio_pkt_count - 1) {
++01777                                         dwcep->desc_addr[i].status.b_iso_in.ioc = 1;
++01778                                         dwcep->desc_addr[i].status.b_iso_in.l = 1;
++01779                                 }
++01780                         }
++01781 
++01782                         /* Setup and start the transfer for this endpoint */
++01783                         dwcep->xiso_active_xfers++;
++01784                         DWC_WRITE_REG32(&GET_CORE_IF(pcd)->dev_if->
++01785                                         in_ep_regs[dwcep->num]->diepdma,
++01786                                         dwcep->dma_desc_addr);
++01787                         diepctl.d32 = 0;
++01788                         diepctl.b.epena = 1;
++01789                         diepctl.b.cnak = 1;
++01790                         DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->dev_if->
++01791                                          in_ep_regs[dwcep->num]->diepctl, 0,
++01792                                          diepctl.d32);
++01793                 } else {
++01794                         /* Setup DMA Descriptor chain for OUT Isoc request */
++01795                         for (i = 0; i < ereq->pio_pkt_count; i++) {
++01796                                 //if ((i % (nat + 1)) == 0)
++01797                                 dwcep->xiso_frame_num = (dwcep->xiso_bInterval + 
++01798                                                                                 dwcep->xiso_frame_num) & 0x3FFF;
++01799                                 dwcep->desc_addr[i].buf =
++01800                                     req->dma + ddesc_iso[i].offset;
++01801                                 dwcep->desc_addr[i].status.b_iso_out.rxbytes =
++01802                                     ddesc_iso[i].length;
++01803                                 dwcep->desc_addr[i].status.b_iso_out.framenum =
++01804                                     dwcep->xiso_frame_num;
++01805                                 dwcep->desc_addr[i].status.b_iso_out.bs =
++01806                                     BS_HOST_READY;
++01807                                 dwcep->desc_addr[i].status.b_iso_out.rxsts = 0;
++01808                                 dwcep->desc_addr[i].status.b_iso_out.sp =
++01809                                     (ddesc_iso[i].length %
++01810                                      dwcep->maxpacket) ? 1 : 0;
++01811                                 dwcep->desc_addr[i].status.b_iso_out.ioc = 0;
++01812                                 dwcep->desc_addr[i].status.b_iso_out.pid = nat + 1;
++01813                                 dwcep->desc_addr[i].status.b_iso_out.l = 0;
++01814                                 
++01815                                 /* Process the last descriptor */
++01816                                 if (i == ereq->pio_pkt_count - 1) {
++01817                                         dwcep->desc_addr[i].status.b_iso_out.ioc = 1;
++01818                                         dwcep->desc_addr[i].status.b_iso_out.l = 1;
++01819                                 }                       
++01820                         }
++01821                         
++01822                         /* Setup and start the transfer for this endpoint */
++01823                         dwcep->xiso_active_xfers++;
++01824                         DWC_WRITE_REG32(&GET_CORE_IF(pcd)->dev_if->
++01825                                         out_ep_regs[dwcep->num]->doepdma,
++01826                                         dwcep->dma_desc_addr);
++01827                         diepctl.d32 = 0;
++01828                         diepctl.b.epena = 1;
++01829                         diepctl.b.cnak = 1;
++01830                         DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->dev_if->
++01831                                          out_ep_regs[dwcep->num]->doepctl, 0,
++01832                                          diepctl.d32);
++01833                 }
++01834 
++01835         } else {
++01836                 ep->stopped = 1;
++01837         }
++01838 
++01839         return 0;
++01840 }
++01841 
++01845 void complete_xiso_ep(dwc_otg_pcd_ep_t * ep)
++01846 {
++01847         dwc_otg_pcd_request_t *req = NULL;
++01848         struct dwc_iso_xreq_port *ereq = NULL;
++01849         struct dwc_iso_pkt_desc_port *ddesc_iso = NULL;
++01850         dwc_ep_t *dwcep = NULL;
++01851         int i;
++01852 
++01853         //DWC_DEBUG();
++01854         dwcep = &ep->dwc_ep;
++01855 
++01856         /* Get the first pending request from the queue */
++01857         if (!DWC_CIRCLEQ_EMPTY(&ep->queue)) {
++01858                 req = DWC_CIRCLEQ_FIRST(&ep->queue);
++01859                 if (!req) {
++01860                         DWC_PRINTF("complete_ep 0x%p, req = NULL!\n", ep);
++01861                         return;
++01862                 }
++01863                 dwcep->xiso_active_xfers--;
++01864                 dwcep->xiso_queued_xfers--;
++01865                 /* Remove this request from the queue */
++01866                 DWC_CIRCLEQ_REMOVE_INIT(&ep->queue, req, queue_entry);
++01867         } else {
++01868                 DWC_PRINTF("complete_ep 0x%p, ep->queue empty!\n", ep);
++01869                 return;
++01870         }
++01871 
++01872         ep->stopped = 1;
++01873         ereq = &req->ext_req;
++01874         ddesc_iso = ereq->per_io_frame_descs;
++01875 
++01876         if (dwcep->xiso_active_xfers < 0) {
++01877                 DWC_WARN("EP#%d (xiso_active_xfers=%d)", dwcep->num,
++01878                          dwcep->xiso_active_xfers);
++01879         }
++01880 
++01881         /* Fill the Isoc descs of portable extended req from dma descriptors */
++01882         for (i = 0; i < ereq->pio_pkt_count; i++) {
++01883                 if (dwcep->is_in) {     /* IN endpoints */
++01884                         ddesc_iso[i].actual_length = ddesc_iso[i].length -
++01885                             dwcep->desc_addr[i].status.b_iso_in.txbytes;
++01886                         ddesc_iso[i].status =
++01887                             dwcep->desc_addr[i].status.b_iso_in.txsts;
++01888                 } else {        /* OUT endpoints */
++01889                         ddesc_iso[i].actual_length = ddesc_iso[i].length -
++01890                             dwcep->desc_addr[i].status.b_iso_out.rxbytes;
++01891                         ddesc_iso[i].status =
++01892                             dwcep->desc_addr[i].status.b_iso_out.rxsts;
++01893                 }
++01894         }
++01895 
++01896         DWC_SPINUNLOCK(ep->pcd->lock);
++01897 
++01898         /* Call the completion function in the non-portable logic */
++01899         ep->pcd->fops->xisoc_complete(ep->pcd, ep->priv, req->priv, 0,
++01900                                       &req->ext_req);
++01901 
++01902         DWC_SPINLOCK(ep->pcd->lock);
++01903 
++01904         /* Free the request - specific freeing needed for extended request object */
++01905         dwc_pcd_xiso_ereq_free(ep, req);
++01906 
++01907         /* Start the next request */
++01908         dwc_otg_pcd_xiso_start_next_request(ep->pcd, ep);
++01909 
++01910         return;
++01911 }
++01912 
++01917 static int dwc_otg_pcd_xiso_create_pkt_descs(dwc_otg_pcd_request_t * req,
++01918                                              void *ereq_nonport,
++01919                                              int atomic_alloc)
++01920 {
++01921         struct dwc_iso_xreq_port *ereq = NULL;
++01922         struct dwc_iso_xreq_port *req_mapped = NULL;
++01923         struct dwc_iso_pkt_desc_port *ipds = NULL;      /* To be created in this function */
++01924         uint32_t pkt_count;
++01925         int i;
++01926 
++01927         ereq = &req->ext_req;
++01928         req_mapped = (struct dwc_iso_xreq_port *)ereq_nonport;
++01929         pkt_count = req_mapped->pio_pkt_count;
++01930 
++01931         /* Create the isoc descs */
++01932         if (atomic_alloc) {
++01933                 ipds = DWC_ALLOC_ATOMIC(sizeof(*ipds) * pkt_count);
++01934         } else {
++01935                 ipds = DWC_ALLOC(sizeof(*ipds) * pkt_count);
++01936         }
++01937 
++01938         if (!ipds) {
++01939                 DWC_ERROR("Failed to allocate isoc descriptors");
++01940                 return -DWC_E_NO_MEMORY;
++01941         }
++01942 
++01943         /* Initialize the extended request fields */
++01944         ereq->per_io_frame_descs = ipds;
++01945         ereq->error_count = 0;
++01946         ereq->pio_alloc_pkt_count = pkt_count;
++01947         ereq->pio_pkt_count = pkt_count;
++01948         ereq->tr_sub_flags = req_mapped->tr_sub_flags;
++01949 
++01950         /* Init the Isoc descriptors */
++01951         for (i = 0; i < pkt_count; i++) {
++01952                 ipds[i].length = req_mapped->per_io_frame_descs[i].length;
++01953                 ipds[i].offset = req_mapped->per_io_frame_descs[i].offset;
++01954                 ipds[i].status = req_mapped->per_io_frame_descs[i].status;      /* 0 */
++01955                 ipds[i].actual_length =
++01956                     req_mapped->per_io_frame_descs[i].actual_length;
++01957         }
++01958 
++01959         return 0;
++01960 }
++01961 
++01962 static void prn_ext_request(struct dwc_iso_xreq_port *ereq)
++01963 {
++01964         struct dwc_iso_pkt_desc_port *xfd = NULL;
++01965         int i;
++01966 
++01967         DWC_DEBUG("per_io_frame_descs=%p", ereq->per_io_frame_descs);
++01968         DWC_DEBUG("tr_sub_flags=%d", ereq->tr_sub_flags);
++01969         DWC_DEBUG("error_count=%d", ereq->error_count);
++01970         DWC_DEBUG("pio_alloc_pkt_count=%d", ereq->pio_alloc_pkt_count);
++01971         DWC_DEBUG("pio_pkt_count=%d", ereq->pio_pkt_count);
++01972         DWC_DEBUG("res=%d", ereq->res);
++01973 
++01974         for (i = 0; i < ereq->pio_pkt_count; i++) {
++01975                 xfd = &ereq->per_io_frame_descs[0];
++01976                 DWC_DEBUG("FD #%d", i);
++01977 
++01978                 DWC_DEBUG("xfd->actual_length=%d", xfd->actual_length);
++01979                 DWC_DEBUG("xfd->length=%d", xfd->length);
++01980                 DWC_DEBUG("xfd->offset=%d", xfd->offset);
++01981                 DWC_DEBUG("xfd->status=%d", xfd->status);
++01982         }
++01983 }
++01984 
++01988 int dwc_otg_pcd_xiso_ep_queue(dwc_otg_pcd_t * pcd, void *ep_handle,
++01989                               uint8_t * buf, dwc_dma_t dma_buf, uint32_t buflen,
++01990                               int zero, void *req_handle, int atomic_alloc,
++01991                               void *ereq_nonport)
++01992 {
++01993         dwc_otg_pcd_request_t *req = NULL;
++01994         dwc_otg_pcd_ep_t *ep;
++01995         dwc_irqflags_t flags;
++01996         int res;
++01997 
++01998         ep = get_ep_from_handle(pcd, ep_handle);
++01999         if (!ep) {
++02000                 DWC_WARN("bad ep\n");
++02001                 return -DWC_E_INVALID;
++02002         }
++02003 
++02004         /* We support this extension only for DDMA mode */
++02005         if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC)
++02006                 if (!GET_CORE_IF(pcd)->dma_desc_enable)
++02007                         return -DWC_E_INVALID;
++02008 
++02009         /* Create a dwc_otg_pcd_request_t object */
++02010         if (atomic_alloc) {
++02011                 req = DWC_ALLOC_ATOMIC(sizeof(*req));
++02012         } else {
++02013                 req = DWC_ALLOC(sizeof(*req));
++02014         }
++02015 
++02016         if (!req) {
++02017                 return -DWC_E_NO_MEMORY;
++02018         }
++02019 
++02020         /* Create the Isoc descs for this request which shall be the exact match
++02021          * of the structure sent to us from the non-portable logic */
++02022         res =
++02023             dwc_otg_pcd_xiso_create_pkt_descs(req, ereq_nonport, atomic_alloc);
++02024         if (res) {
++02025                 DWC_WARN("Failed to init the Isoc descriptors");
++02026                 DWC_FREE(req);
++02027                 return res;
++02028         }
++02029 
++02030         DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
++02031 
++02032         DWC_CIRCLEQ_INIT_ENTRY(req, queue_entry);
++02033         req->buf = buf;
++02034         req->dma = dma_buf;
++02035         req->length = buflen;
++02036         req->sent_zlp = zero;
++02037         req->priv = req_handle;
++02038 
++02039         //DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
++02040         ep->dwc_ep.dma_addr = dma_buf;
++02041         ep->dwc_ep.start_xfer_buff = buf;
++02042         ep->dwc_ep.xfer_buff = buf;
++02043         ep->dwc_ep.xfer_len = 0;
++02044         ep->dwc_ep.xfer_count = 0;
++02045         ep->dwc_ep.sent_zlp = 0;
++02046         ep->dwc_ep.total_len = buflen;
++02047 
++02048         /* Add this request to the tail */
++02049         DWC_CIRCLEQ_INSERT_TAIL(&ep->queue, req, queue_entry);
++02050         ep->dwc_ep.xiso_queued_xfers++;
++02051 
++02052 //DWC_DEBUG("CP_0");
++02053 //DWC_DEBUG("req->ext_req.tr_sub_flags=%d", req->ext_req.tr_sub_flags);
++02054 //prn_ext_request((struct dwc_iso_xreq_port *) ereq_nonport);
++02055 //prn_ext_request(&req->ext_req);
++02056 
++02057         //DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
++02058 
++02059         /* If the req->status == ASAP  then check if there is any active transfer
++02060          * for this endpoint. If no active transfers, then get the first entry
++02061          * from the queue and start that transfer
++02062          */
++02063         if (req->ext_req.tr_sub_flags == DWC_EREQ_TF_ASAP) {
++02064                 res = dwc_otg_pcd_xiso_start_next_request(pcd, ep);
++02065                 if (res) {
++02066                         DWC_WARN("Failed to start the next Isoc transfer");
++02067                         DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
++02068                         DWC_FREE(req);
++02069                         return res;
++02070                 }
++02071         }
++02072 
++02073         DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
++02074         return 0;
++02075 }
++02076 
++02077 #endif
++02078 /* END ifdef DWC_UTE_PER_IO ***************************************************/
++02079 int dwc_otg_pcd_ep_queue(dwc_otg_pcd_t * pcd, void *ep_handle,
++02080                          uint8_t * buf, dwc_dma_t dma_buf, uint32_t buflen,
++02081                          int zero, void *req_handle, int atomic_alloc)
++02082 {
++02083         dwc_irqflags_t flags;
++02084         dwc_otg_pcd_request_t *req;
++02085         dwc_otg_pcd_ep_t *ep;
++02086         uint32_t max_transfer;
++02087 
++02088         ep = get_ep_from_handle(pcd, ep_handle);
++02089         if (!ep || (!ep->desc && ep->dwc_ep.num != 0)) {
++02090                 DWC_WARN("bad ep\n");
++02091                 return -DWC_E_INVALID;
++02092         }
++02093 
++02094         if (atomic_alloc) {
++02095                 req = DWC_ALLOC_ATOMIC(sizeof(*req));
++02096         } else {
++02097                 req = DWC_ALLOC(sizeof(*req));
++02098         }
++02099 
++02100         if (!req) {
++02101                 return -DWC_E_NO_MEMORY;
++02102         }
++02103         DWC_CIRCLEQ_INIT_ENTRY(req, queue_entry);
++02104         if (!GET_CORE_IF(pcd)->core_params->opt) {
++02105                 if (ep->dwc_ep.num != 0) {
++02106                         DWC_ERROR("queue req %p, len %d buf %p\n",
++02107                                   req_handle, buflen, buf);
++02108                 }
++02109         }
++02110 
++02111         req->buf = buf;
++02112         req->dma = dma_buf;
++02113         req->length = buflen;
++02114         req->sent_zlp = zero;
++02115         req->priv = req_handle;
++02116         req->dw_align_buf = NULL;
++02117         if ((dma_buf & 0x3) && GET_CORE_IF(pcd)->dma_enable
++02118                         && !GET_CORE_IF(pcd)->dma_desc_enable)
++02119                 req->dw_align_buf = DWC_DMA_ALLOC(buflen,
++02120                                  &req->dw_align_buf_dma);
++02121         DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
++02122 
++02123         /*
++02124          * After adding request to the queue for IN ISOC wait for In Token Received
++02125          * when TX FIFO is empty interrupt and for OUT ISOC wait for OUT Token 
++02126          * Received when EP is disabled interrupt to obtain starting microframe
++02127          * (odd/even) start transfer
++02128          */
++02129         if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC)
++02130         {
++02131                 if (req != 0) {
++02132                         depctl_data_t depctl = {.d32 = DWC_READ_REG32(&pcd->core_if->dev_if->in_ep_regs[ep->dwc_ep.num]->diepctl)};
++02133                         ++pcd->request_pending;
++02134 
++02135                         DWC_CIRCLEQ_INSERT_TAIL(&ep->queue, req, queue_entry);
++02136                         if (ep->dwc_ep.is_in)
++02137                         {
++02138                                 depctl.b.cnak = 1;
++02139                                 DWC_WRITE_REG32(&pcd->core_if->dev_if->in_ep_regs[ep->dwc_ep.num]->diepctl, depctl.d32);
++02140                         }
++02141                         
++02142                         DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
++02143                 }
++02144                 return 0;
++02145         }
++02146 
++02147         /*
++02148          * For EP0 IN without premature status, zlp is required?
++02149          */
++02150         if (ep->dwc_ep.num == 0 && ep->dwc_ep.is_in) {
++02151                 DWC_DEBUGPL(DBG_PCDV, "%d-OUT ZLP\n", ep->dwc_ep.num);
++02152                 //_req->zero = 1;
++02153         }
++02154 
++02155         /* Start the transfer */
++02156         if (DWC_CIRCLEQ_EMPTY(&ep->queue) && !ep->stopped) {
++02157                 /* EP0 Transfer? */
++02158                 if (ep->dwc_ep.num == 0) {
++02159                         switch (pcd->ep0state) {
++02160                         case EP0_IN_DATA_PHASE:
++02161                                 DWC_DEBUGPL(DBG_PCD,
++02162                                             "%s ep0: EP0_IN_DATA_PHASE\n",
++02163                                             __func__);
++02164                                 break;
++02165 
++02166                         case EP0_OUT_DATA_PHASE:
++02167                                 DWC_DEBUGPL(DBG_PCD,
++02168                                             "%s ep0: EP0_OUT_DATA_PHASE\n",
++02169                                             __func__);
++02170                                 if (pcd->request_config) {
++02171                                         /* Complete STATUS PHASE */
++02172                                         ep->dwc_ep.is_in = 1;
++02173                                         pcd->ep0state = EP0_IN_STATUS_PHASE;
++02174                                 }
++02175                                 break;
++02176 
++02177                         case EP0_IN_STATUS_PHASE:
++02178                                 DWC_DEBUGPL(DBG_PCD,
++02179                                             "%s ep0: EP0_IN_STATUS_PHASE\n",
++02180                                             __func__);
++02181                                 break;
++02182 
++02183                         default:
++02184                                 DWC_DEBUGPL(DBG_ANY, "ep0: odd state %d\n",
++02185                                             pcd->ep0state);
++02186                                 DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
++02187                                 return -DWC_E_SHUTDOWN;
++02188                         }
++02189 
++02190                         ep->dwc_ep.dma_addr = dma_buf;
++02191                         ep->dwc_ep.start_xfer_buff = buf;
++02192                         ep->dwc_ep.xfer_buff = buf;
++02193                         ep->dwc_ep.xfer_len = buflen;
++02194                         ep->dwc_ep.xfer_count = 0;
++02195                         ep->dwc_ep.sent_zlp = 0;
++02196                         ep->dwc_ep.total_len = ep->dwc_ep.xfer_len;
++02197 
++02198                         if (zero) {
++02199                                 if ((ep->dwc_ep.xfer_len %
++02200                                      ep->dwc_ep.maxpacket == 0)
++02201                                     && (ep->dwc_ep.xfer_len != 0)) {
++02202                                         ep->dwc_ep.sent_zlp = 1;
++02203                                 }
++02204 
++02205                         }
++02206 
++02207                         dwc_otg_ep0_start_transfer(GET_CORE_IF(pcd),
++02208                                                    &ep->dwc_ep);
++02209                 }               // non-ep0 endpoints
++02210                 else {
++02211 #ifdef DWC_UTE_CFI
++02212                         if (ep->dwc_ep.buff_mode != BM_STANDARD) {
++02213                                 /* store the request length */
++02214                                 ep->dwc_ep.cfi_req_len = buflen;
++02215                                 pcd->cfi->ops.build_descriptors(pcd->cfi, pcd,
++02216                                                                 ep, req);
++02217                         } else {
++02218 #endif
++02219                                 max_transfer =
++02220                                     GET_CORE_IF(ep->pcd)->
++02221                                     core_params->max_transfer_size;
++02222 
++02223                                 /* Setup and start the Transfer */
++02224                                 if (req->dw_align_buf){
++02225                                         if (ep->dwc_ep.is_in)
++02226                                                 dwc_memcpy(req->dw_align_buf, buf, buflen);
++02227                                         ep->dwc_ep.dma_addr = req->dw_align_buf_dma;
++02228                                         ep->dwc_ep.start_xfer_buff = req->dw_align_buf;
++02229                                         ep->dwc_ep.xfer_buff = req->dw_align_buf;
++02230                                 } else {
++02231                                         ep->dwc_ep.dma_addr = dma_buf;
++02232                                         ep->dwc_ep.start_xfer_buff = buf;
++02233                                         ep->dwc_ep.xfer_buff = buf;     
++02234                                 }
++02235                                 ep->dwc_ep.xfer_len = 0;
++02236                                 ep->dwc_ep.xfer_count = 0;
++02237                                 ep->dwc_ep.sent_zlp = 0;
++02238                                 ep->dwc_ep.total_len = buflen;
++02239 
++02240                                 ep->dwc_ep.maxxfer = max_transfer;
++02241                                 if (GET_CORE_IF(pcd)->dma_desc_enable) {
++02242                                         uint32_t out_max_xfer =
++02243                                             DDMA_MAX_TRANSFER_SIZE -
++02244                                             (DDMA_MAX_TRANSFER_SIZE % 4);
++02245                                         if (ep->dwc_ep.is_in) {
++02246                                                 if (ep->dwc_ep.maxxfer >
++02247                                                     DDMA_MAX_TRANSFER_SIZE) {
++02248                                                         ep->dwc_ep.maxxfer =
++02249                                                             DDMA_MAX_TRANSFER_SIZE;
++02250                                                 }
++02251                                         } else {
++02252                                                 if (ep->dwc_ep.maxxfer >
++02253                                                     out_max_xfer) {
++02254                                                         ep->dwc_ep.maxxfer =
++02255                                                             out_max_xfer;
++02256                                                 }
++02257                                         }
++02258                                 }
++02259                                 if (ep->dwc_ep.maxxfer < ep->dwc_ep.total_len) {
++02260                                         ep->dwc_ep.maxxfer -=
++02261                                             (ep->dwc_ep.maxxfer %
++02262                                              ep->dwc_ep.maxpacket);
++02263                                 }
++02264 
++02265                                 if (zero) {
++02266                                         if ((ep->dwc_ep.total_len %
++02267                                              ep->dwc_ep.maxpacket == 0)
++02268                                             && (ep->dwc_ep.total_len != 0)) {
++02269                                                 ep->dwc_ep.sent_zlp = 1;
++02270                                         }
++02271                                 }
++02272 #ifdef DWC_UTE_CFI
++02273                         }
++02274 #endif
++02275                         dwc_otg_ep_start_transfer(GET_CORE_IF(pcd),
++02276                                                   &ep->dwc_ep);
++02277                 }
++02278         }
++02279 
++02280         if (req != 0) {
++02281                 ++pcd->request_pending;
++02282                 DWC_CIRCLEQ_INSERT_TAIL(&ep->queue, req, queue_entry);
++02283                 if (ep->dwc_ep.is_in && ep->stopped
++02284                     && !(GET_CORE_IF(pcd)->dma_enable)) {
++02286                         diepmsk_data_t diepmsk = {.d32 = 0 };
++02287                         diepmsk.b.intktxfemp = 1;
++02288                         if (GET_CORE_IF(pcd)->multiproc_int_enable) {
++02289                                 DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->dev_if->
++02290                                                  dev_global_regs->
++02291                                                  diepeachintmsk[ep->dwc_ep.num],
++02292                                                  0, diepmsk.d32);
++02293                         } else {
++02294                                 DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->dev_if->
++02295                                                  dev_global_regs->diepmsk, 0,
++02296                                                  diepmsk.d32);
++02297                         }
++02298 
++02299                 }
++02300         }
++02301         DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
++02302 
++02303         return 0;
++02304 }
++02305 
++02306 int dwc_otg_pcd_ep_dequeue(dwc_otg_pcd_t * pcd, void *ep_handle,
++02307                            void *req_handle)
++02308 {
++02309         dwc_irqflags_t flags;
++02310         dwc_otg_pcd_request_t *req;
++02311         dwc_otg_pcd_ep_t *ep;
++02312 
++02313         ep = get_ep_from_handle(pcd, ep_handle);
++02314         if (!ep || (!ep->desc && ep->dwc_ep.num != 0)) {
++02315                 DWC_WARN("bad argument\n");
++02316                 return -DWC_E_INVALID;
++02317         }
++02318 
++02319         DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
++02320 
++02321         /* make sure it's actually queued on this endpoint */
++02322         DWC_CIRCLEQ_FOREACH(req, &ep->queue, queue_entry) {
++02323                 if (req->priv == (void *)req_handle) {
++02324                         break;
++02325                 }
++02326         }
++02327 
++02328         if (req->priv != (void *)req_handle) {
++02329                 DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
++02330                 return -DWC_E_INVALID;
++02331         }
++02332 
++02333         if (!DWC_CIRCLEQ_EMPTY_ENTRY(req, queue_entry)) {
++02334                 dwc_otg_request_done(ep, req, -DWC_E_RESTART);
++02335         } else {
++02336                 req = NULL;
++02337         }
++02338 
++02339         DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
++02340 
++02341         return req ? 0 : -DWC_E_SHUTDOWN;
++02342 
++02343 }
++02344 
++02345 int dwc_otg_pcd_ep_halt(dwc_otg_pcd_t * pcd, void *ep_handle, int value)
++02346 {
++02347         dwc_otg_pcd_ep_t *ep;
++02348         dwc_irqflags_t flags;
++02349         int retval = 0;
++02350 
++02351         ep = get_ep_from_handle(pcd, ep_handle);
++02352 
++02353         if (!ep || (!ep->desc && ep != &pcd->ep0) ||
++02354             (ep->desc && (ep->desc->bmAttributes == UE_ISOCHRONOUS))) {
++02355                 DWC_WARN("%s, bad ep\n", __func__);
++02356                 return -DWC_E_INVALID;
++02357         }
++02358 
++02359         DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
++02360         if (!DWC_CIRCLEQ_EMPTY(&ep->queue)) {
++02361                 DWC_WARN("%d %s XFer In process\n", ep->dwc_ep.num,
++02362                          ep->dwc_ep.is_in ? "IN" : "OUT");
++02363                 retval = -DWC_E_AGAIN;
++02364         } else if (value == 0) {
++02365                 dwc_otg_ep_clear_stall(GET_CORE_IF(pcd), &ep->dwc_ep);
++02366         } else if (value == 1) {
++02367                 if (ep->dwc_ep.is_in == 1 && GET_CORE_IF(pcd)->dma_desc_enable) {
++02368                         dtxfsts_data_t txstatus;
++02369                         fifosize_data_t txfifosize;
++02370 
++02371                         txfifosize.d32 =
++02372                             DWC_READ_REG32(&GET_CORE_IF(pcd)->core_global_regs->
++02373                                            dtxfsiz[ep->dwc_ep.tx_fifo_num]);
++02374                         txstatus.d32 =
++02375                             DWC_READ_REG32(&GET_CORE_IF(pcd)->dev_if->
++02376                                            in_ep_regs[ep->dwc_ep.num]->dtxfsts);
++02377 
++02378                         if (txstatus.b.txfspcavail < txfifosize.b.depth) {
++02379                                 DWC_WARN("%s() Data In Tx Fifo\n", __func__);
++02380                                 retval = -DWC_E_AGAIN;
++02381                         } else {
++02382                                 if (ep->dwc_ep.num == 0) {
++02383                                         pcd->ep0state = EP0_STALL;
++02384                                 }
++02385 
++02386                                 ep->stopped = 1;
++02387                                 dwc_otg_ep_set_stall(GET_CORE_IF(pcd),
++02388                                                      &ep->dwc_ep);
++02389                         }
++02390                 } else {
++02391                         if (ep->dwc_ep.num == 0) {
++02392                                 pcd->ep0state = EP0_STALL;
++02393                         }
++02394 
++02395                         ep->stopped = 1;
++02396                         dwc_otg_ep_set_stall(GET_CORE_IF(pcd), &ep->dwc_ep);
++02397                 }
++02398         } else if (value == 2) {
++02399                 ep->dwc_ep.stall_clear_flag = 0;
++02400         } else if (value == 3) {
++02401                 ep->dwc_ep.stall_clear_flag = 1;
++02402         }
++02403 
++02404         DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
++02405 
++02406         return retval;
++02407 }
++02408 
++02412 void dwc_otg_pcd_rem_wkup_from_suspend(dwc_otg_pcd_t * pcd, int set)
++02413 {
++02414         dctl_data_t dctl = { 0 };
++02415         dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
++02416         dsts_data_t dsts;
++02417 
++02418         dsts.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts);
++02419         if (!dsts.b.suspsts) {
++02420                 DWC_WARN("Remote wakeup while is not in suspend state\n");
++02421         }
++02422         /* Check if DEVICE_REMOTE_WAKEUP feature enabled */
++02423         if (pcd->remote_wakeup_enable) {
++02424                 if (set) {
++02425 
++02426                         if (core_if->adp_enable) {
++02427                                 gpwrdn_data_t gpwrdn;
++02428 
++02429                                 dwc_otg_adp_probe_stop(core_if);
++02430 
++02431                                 /* Mask SRP detected interrupt from Power Down Logic */
++02432                                 gpwrdn.d32 = 0;
++02433                                 gpwrdn.b.srp_det_msk = 1;
++02434                                 DWC_MODIFY_REG32(&core_if->core_global_regs->
++02435                                                  gpwrdn, gpwrdn.d32, 0);
++02436 
++02437                                 /* Disable Power Down Logic */
++02438                                 gpwrdn.d32 = 0;
++02439                                 gpwrdn.b.pmuactv = 1;
++02440                                 DWC_MODIFY_REG32(&core_if->core_global_regs->
++02441                                                  gpwrdn, gpwrdn.d32, 0);
++02442 
++02443                                 /*
++02444                                  * Initialize the Core for Device mode.
++02445                                  */
++02446                                 core_if->op_state = B_PERIPHERAL;
++02447                                 dwc_otg_core_init(core_if);
++02448                                 dwc_otg_enable_global_interrupts(core_if);
++02449                                 cil_pcd_start(core_if);
++02450 
++02451                                 dwc_otg_initiate_srp(core_if);
++02452                         }
++02453 
++02454                         dctl.b.rmtwkupsig = 1;
++02455                         DWC_MODIFY_REG32(&core_if->dev_if->
++02456                                          dev_global_regs->dctl, 0, dctl.d32);
++02457                         DWC_DEBUGPL(DBG_PCD, "Set Remote Wakeup\n");
++02458 
++02459                         dwc_mdelay(2);
++02460                         DWC_MODIFY_REG32(&core_if->dev_if->
++02461                                          dev_global_regs->dctl, dctl.d32, 0);
++02462                         DWC_DEBUGPL(DBG_PCD, "Clear Remote Wakeup\n");
++02463                 }
++02464         } else {
++02465                 DWC_DEBUGPL(DBG_PCD, "Remote Wakeup is disabled\n");
++02466         }
++02467 }
++02468 
++02469 #ifdef CONFIG_USB_DWC_OTG_LPM
++02470 
++02473 void dwc_otg_pcd_rem_wkup_from_sleep(dwc_otg_pcd_t * pcd, int set)
++02474 {
++02475         glpmcfg_data_t lpmcfg;
++02476         dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
++02477 
++02478         lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
++02479 
++02480         /* Check if we are in L1 state */
++02481         if (!lpmcfg.b.prt_sleep_sts) {
++02482                 DWC_DEBUGPL(DBG_PCD, "Device is not in sleep state\n");
++02483                 return;
++02484         }
++02485 
++02486         /* Check if host allows remote wakeup */
++02487         if (!lpmcfg.b.rem_wkup_en) {
++02488                 DWC_DEBUGPL(DBG_PCD, "Host does not allow remote wakeup\n");
++02489                 return;
++02490         }
++02491 
++02492         /* Check if Resume OK */
++02493         if (!lpmcfg.b.sleep_state_resumeok) {
++02494                 DWC_DEBUGPL(DBG_PCD, "Sleep state resume is not OK\n");
++02495                 return;
++02496         }
++02497 
++02498         lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
++02499         lpmcfg.b.en_utmi_sleep = 0;
++02500         lpmcfg.b.hird_thres &= (~(1 << 4));
++02501         DWC_WRITE_REG32(&core_if->core_global_regs->glpmcfg, lpmcfg.d32);
++02502 
++02503         if (set) {
++02504                 dctl_data_t dctl = {.d32 = 0 };
++02505                 dctl.b.rmtwkupsig = 1;
++02506                 /* Set RmtWkUpSig bit to start remote wakup signaling.
++02507                  * Hardware will automatically clear this bit.
++02508                  */
++02509                 DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl,
++02510                                  0, dctl.d32);
++02511                 DWC_DEBUGPL(DBG_PCD, "Set Remote Wakeup\n");
++02512         }
++02513 
++02514 }
++02515 #endif
++02516 
++02520 void dwc_otg_pcd_remote_wakeup(dwc_otg_pcd_t * pcd, int set)
++02521 {
++02522         dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
++02523         dwc_irqflags_t flags;
++02524         if (dwc_otg_is_device_mode(core_if)) {
++02525                 DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
++02526 #ifdef CONFIG_USB_DWC_OTG_LPM
++02527                 if (core_if->lx_state == DWC_OTG_L1) {
++02528                         dwc_otg_pcd_rem_wkup_from_sleep(pcd, set);
++02529                 } else {
++02530 #endif
++02531                         dwc_otg_pcd_rem_wkup_from_suspend(pcd, set);
++02532 #ifdef CONFIG_USB_DWC_OTG_LPM
++02533                 }
++02534 #endif
++02535                 DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
++02536         }
++02537         return;
++02538 }
++02539 
++02540 void dwc_otg_pcd_disconnect_us(dwc_otg_pcd_t * pcd, int no_of_usecs)
++02541 {
++02542         dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
++02543         dctl_data_t dctl = { 0 };
++02544 
++02545         if (dwc_otg_is_device_mode(core_if)) {
++02546                 dctl.b.sftdiscon = 1;
++02547                 DWC_PRINTF("Soft disconnect for %d useconds\n",no_of_usecs);
++02548                 DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, 0, dctl.d32);
++02549                 dwc_udelay(no_of_usecs);
++02550                 DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32,0);
++02551                 
++02552         } else{
++02553                 DWC_PRINTF("NOT SUPPORTED IN HOST MODE\n");
++02554         }
++02555         return;
++02556 
++02557 }
++02558 
++02559 int dwc_otg_pcd_wakeup(dwc_otg_pcd_t * pcd)
++02560 {
++02561         dsts_data_t dsts;
++02562         gotgctl_data_t gotgctl;
++02563 
++02564         /*
++02565          * This function starts the Protocol if no session is in progress. If
++02566          * a session is already in progress, but the device is suspended,
++02567          * remote wakeup signaling is started.
++02568          */
++02569 
++02570         /* Check if valid session */
++02571         gotgctl.d32 =
++02572             DWC_READ_REG32(&(GET_CORE_IF(pcd)->core_global_regs->gotgctl));
++02573         if (gotgctl.b.bsesvld) {
++02574                 /* Check if suspend state */
++02575                 dsts.d32 =
++02576                     DWC_READ_REG32(&
++02577                                    (GET_CORE_IF(pcd)->dev_if->
++02578                                     dev_global_regs->dsts));
++02579                 if (dsts.b.suspsts) {
++02580                         dwc_otg_pcd_remote_wakeup(pcd, 1);
++02581                 }
++02582         } else {
++02583                 dwc_otg_pcd_initiate_srp(pcd);
++02584         }
++02585 
++02586         return 0;
++02587 
++02588 }
++02589 
++02596 void dwc_otg_pcd_initiate_srp(dwc_otg_pcd_t * pcd)
++02597 {
++02598         dwc_irqflags_t flags;
++02599         DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
++02600         dwc_otg_initiate_srp(GET_CORE_IF(pcd));
++02601         DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
++02602 }
++02603 
++02604 int dwc_otg_pcd_get_frame_number(dwc_otg_pcd_t * pcd)
++02605 {
++02606         return dwc_otg_get_frame_number(GET_CORE_IF(pcd));
++02607 }
++02608 
++02609 int dwc_otg_pcd_is_lpm_enabled(dwc_otg_pcd_t * pcd)
++02610 {
++02611         return GET_CORE_IF(pcd)->core_params->lpm_enable;
++02612 }
++02613 
++02614 uint32_t get_b_hnp_enable(dwc_otg_pcd_t * pcd)
++02615 {
++02616         return pcd->b_hnp_enable;
++02617 }
++02618 
++02619 uint32_t get_a_hnp_support(dwc_otg_pcd_t * pcd)
++02620 {
++02621         return pcd->a_hnp_support;
++02622 }
++02623 
++02624 uint32_t get_a_alt_hnp_support(dwc_otg_pcd_t * pcd)
++02625 {
++02626         return pcd->a_alt_hnp_support;
++02627 }
++02628 
++02629 int dwc_otg_pcd_get_rmwkup_enable(dwc_otg_pcd_t * pcd)
++02630 {
++02631         return pcd->remote_wakeup_enable;
++02632 }
++02633 
++02634 #endif /* DWC_HOST_ONLY */
++
    Generated on Thu Oct 27 03:56:37 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
    ++doxygen 1.3.9.1
    + + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__pcd_8c.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/dwc__otg__pcd_8c.html 2013-07-26 19:31:21.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__pcd_8c.html 2013-07-26 19:34:42.000000000 +0000 +@@ -2,272 +2,277 @@ + + DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_pcd.c File Reference + +- + +- +-
    +-
    +-
    +-
    ++ ++
    Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
    +

    dwc_otg_pcd.c File Reference

    This file implements PCD Core. More... +

    +-#include "dwc_otg_pcd.h"
    ++#include "dwc_otg_pcd.h"
    + +

    + Go to the source code of this file. + + +- ++ + +- ++ ++ + +- +- ++ ++ + + +- ++ + +- +- ++ ++ + +- +- ++ ++ + + +- ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + + +- ++ + + +- ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- ++ + +- +- ++ ++ + +- +- ++ ++ + + +- ++ + +- ++ + +- +- ++ ++ + +- +- ++ ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + + +- ++ + + +- ++ + +- +- ++ ++ + +- +- +- +- +- ++ ++ ++ ++ ++ + + +- ++ + + +- ++ + + +- ++ + +- ++ + +- ++ + + + +- ++ + +- ++ +

    Functions

    +-static dwc_otg_pcd_ep_t * get_ep_from_handle (dwc_otg_pcd_t *pcd, void *handle)
    ++dwc_otg_pcd_ep_t * get_ep_from_handle (dwc_otg_pcd_t *pcd, void *handle)
    void dwc_otg_request_done (dwc_otg_pcd_ep_t *ep, dwc_otg_pcd_request_t *req, int32_t status)
     Choose endpoint from ep arrays using usb_ep structure.
    void dwc_otg_request_done (dwc_otg_pcd_ep_t *ep, dwc_otg_pcd_request_t *req, int32_t status)
     This function completes a request.
    +-void dwc_otg_request_nuke (dwc_otg_pcd_ep_t *ep)
     This function completes a request.
    ++void dwc_otg_request_nuke (dwc_otg_pcd_ep_t *ep)
     This function terminates all the requsts in the EP request queue.
    void dwc_otg_pcd_start (dwc_otg_pcd_t *pcd, const struct dwc_otg_pcd_function_ops *fops)
    void dwc_otg_pcd_start (dwc_otg_pcd_t *pcd, const struct dwc_otg_pcd_function_ops *fops)
     Call this to bind the function driver to the PCD Core.
    static int32_t dwc_otg_pcd_start_cb (void *p)
     Call this to bind the function driver to the PCD Core.
    int32_t dwc_otg_pcd_start_cb (void *p)
     PCD Callback function for initializing the PCD when switching to device mode.
    +-uint8_t * cfiw_ep_alloc_buffer (dwc_otg_pcd_t *pcd, void *pep, dwc_dma_t *addr, size_t buflen, int flags)
     PCD Callback function for initializing the PCD when switching to device mode.
    ++uint8_t * cfiw_ep_alloc_buffer (dwc_otg_pcd_t *pcd, void *pep, dwc_dma_t *addr, size_t buflen, int flags)
     CFI-specific buffer allocation function for EP.
    static int32_t dwc_otg_pcd_resume_cb (void *p)
    int32_t dwc_otg_pcd_resume_cb (void *p)
     PCD Callback function for notifying the PCD when resuming from suspend.
    static int32_t dwc_otg_pcd_suspend_cb (void *p)
     PCD Callback function for notifying the PCD when resuming from suspend.
    int32_t dwc_otg_pcd_suspend_cb (void *p)
     PCD Callback function for notifying the PCD device is suspended.
    static int32_t dwc_otg_pcd_stop_cb (void *p)
     PCD Callback function for notifying the PCD device is suspended.
    int32_t dwc_otg_pcd_stop_cb (void *p)
     PCD Callback function for stopping the PCD when switching to Host mode.
    +-dwc_otg_dev_dma_desc_t * dwc_otg_ep_alloc_desc_chain (uint32_t *dma_desc_addr, uint32_t count)
     PCD Callback function for stopping the PCD when switching to Host mode.
    ++dwc_otg_dev_dma_desc_t * dwc_otg_ep_alloc_desc_chain (dwc_dma_t *dma_desc_addr, uint32_t count)
     This function allocates a DMA Descriptor chain for the Endpoint buffer to be used for a transfer to/from the specified endpoint.
    +-void dwc_otg_ep_free_desc_chain (dwc_otg_dev_dma_desc_t *desc_addr, uint32_t dma_desc_addr, uint32_t count)
    ++void dwc_otg_ep_free_desc_chain (dwc_otg_dev_dma_desc_t *desc_addr, uint32_t dma_desc_addr, uint32_t count)
     This function frees a DMA Descriptor chain that was allocated by ep_alloc_desc.
    void dwc_otg_iso_ep_start_ddma_transfer (dwc_otg_core_if_t *core_if, dwc_ep_t *dwc_ep)
    void dwc_otg_iso_ep_start_ddma_transfer (dwc_otg_core_if_t *core_if, dwc_ep_t *dwc_ep)
     This function initializes a descriptor chain for Isochronous transfer.
    void dwc_otg_iso_ep_start_buf_transfer (dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
     This function initializes a descriptor chain for Isochronous transfer.
    void dwc_otg_iso_ep_start_buf_transfer (dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
     This function initializes a descriptor chain for Isochronous transfer.
    static void dwc_otg_iso_ep_start_transfer (dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
     This function initializes a descriptor chain for Isochronous transfer.
    void dwc_otg_iso_ep_start_transfer (dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
     This function does the setup for a data transfer for an EP and starts the transfer.
    void dwc_otg_iso_ep_stop_transfer (dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
     This function does the setup for a data transfer for an EP and starts the transfer.
    void dwc_otg_iso_ep_stop_transfer (dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
     This function does the setup for a data transfer for an EP and starts the transfer.
    int dwc_otg_pcd_iso_ep_start (dwc_otg_pcd_t *pcd, void *ep_handle, uint8_t *buf0, uint8_t *buf1, dwc_dma_t dma0, dwc_dma_t dma1, int sync_frame, int dp_frame, int data_per_frame, int start_frame, int buf_proc_intrvl, void *req_handle, int atomic_alloc)
     This function stops transfer for an EP and resets the ep's variables.
    int dwc_otg_pcd_iso_ep_start (dwc_otg_pcd_t *pcd, void *ep_handle, uint8_t *buf0, uint8_t *buf1, dwc_dma_t dma0, dwc_dma_t dma1, int sync_frame, int dp_frame, int data_per_frame, int start_frame, int buf_proc_intrvl, void *req_handle, int atomic_alloc)
     Start isochronous transfers on the endpoint referenced by ep_handle.
    int dwc_otg_pcd_iso_ep_stop (dwc_otg_pcd_t *pcd, void *ep_handle, void *req_handle)
     Start isochronous transfers on the endpoint referenced by ep_handle.
    int dwc_otg_pcd_iso_ep_stop (dwc_otg_pcd_t *pcd, void *ep_handle, void *req_handle)
     Stop ISOC transfers on endpoint referenced by ep_handle.
    void dwc_otg_iso_buffer_done (dwc_otg_pcd_t *pcd, dwc_otg_pcd_ep_t *ep, void *req_handle)
     Stop ISOC transfers on endpoint referenced by ep_handle.
    void dwc_otg_iso_buffer_done (dwc_otg_pcd_t *pcd, dwc_otg_pcd_ep_t *ep, void *req_handle)
     This function is used for perodical data exchnage between PCD and gadget drivers.
    int dwc_otg_pcd_get_iso_packet_count (dwc_otg_pcd_t *pcd, void *ep_handle, void *iso_req_handle)
     This function is used for perodical data exchnage between PCD and gadget drivers.
    int dwc_otg_pcd_get_iso_packet_count (dwc_otg_pcd_t *pcd, void *ep_handle, void *iso_req_handle)
     Get ISOC packet count.
    void dwc_otg_pcd_get_iso_packet_params (dwc_otg_pcd_t *pcd, void *ep_handle, void *iso_req_handle, int packet, int *status, int *actual, int *offset)
     Get ISOC packet count.
    void dwc_otg_pcd_get_iso_packet_params (dwc_otg_pcd_t *pcd, void *ep_handle, void *iso_req_handle, int packet, int *status, int *actual, int *offset)
     Get ISOC packet status.
    +-static void dwc_otg_pcd_init_ep (dwc_otg_pcd_t *pcd, dwc_otg_pcd_ep_t *pcd_ep, uint32_t is_in, uint32_t ep_num)
     Get ISOC packet status.
    ++void dwc_otg_pcd_init_ep (dwc_otg_pcd_t *pcd, dwc_otg_pcd_ep_t *pcd_ep, uint32_t is_in, uint32_t ep_num)
    static void dwc_otg_pcd_reinit (dwc_otg_pcd_t *pcd)
    void dwc_otg_pcd_reinit (dwc_otg_pcd_t *pcd)
     Initialise ep's.
    static void srp_timeout (void *ptr)
     Initialize ep's.
    void srp_timeout (void *ptr)
     This function is called when the SRP timer expires.
    +-void start_next_request (dwc_otg_pcd_ep_t *ep)
     This function is called when the SRP timer expires.
    ++void start_next_request (dwc_otg_pcd_ep_t *ep)
     Tasklet.
    +-static void start_xfer_tasklet_func (void *data)
    ++void start_xfer_tasklet_func (void *data)
    dwc_otg_pcd_t * dwc_otg_pcd_init (dwc_otg_core_if_t *core_if)
    dwc_otg_pcd_t * dwc_otg_pcd_init (dwc_otg_core_if_t *core_if)
     Call this function to get pointer on dwc_otg_pcd_t, this pointer will be used for all PCD API functions.
    void dwc_otg_pcd_remove (dwc_otg_pcd_t *pcd)
     Call this function to get pointer on dwc_otg_pcd_t, this pointer will be used for all PCD API functions.
    void dwc_otg_pcd_remove (dwc_otg_pcd_t *pcd)
     Frees PCD allocated by dwc_otg_pcd_init.
    +-uint32_t dwc_otg_pcd_is_dualspeed (dwc_otg_pcd_t *pcd)
     Frees PCD allocated by dwc_otg_pcd_init.
    ++uint32_t dwc_otg_pcd_is_dualspeed (dwc_otg_pcd_t *pcd)
     This function returns whether device is dualspeed.
    +-uint32_t dwc_otg_pcd_is_otg (dwc_otg_pcd_t *pcd)
    ++uint32_t dwc_otg_pcd_is_otg (dwc_otg_pcd_t *pcd)
     This function returns whether device is otg.
    +-static uint32_t assign_tx_fifo (dwc_otg_core_if_t *core_if)
    ++uint32_t assign_tx_fifo (dwc_otg_core_if_t *core_if)
     This function assigns periodic Tx FIFO to an periodic EP in shared Tx FIFO mode.
    +-static uint32_t assign_perio_tx_fifo (dwc_otg_core_if_t *core_if)
    ++uint32_t assign_perio_tx_fifo (dwc_otg_core_if_t *core_if)
     This function assigns periodic Tx FIFO to an periodic EP in shared Tx FIFO mode.
    +-static void release_perio_tx_fifo (dwc_otg_core_if_t *core_if, uint32_t fifo_num)
    ++void release_perio_tx_fifo (dwc_otg_core_if_t *core_if, uint32_t fifo_num)
     This function releases periodic Tx FIFO in shared Tx FIFO mode.
    +-static void release_tx_fifo (dwc_otg_core_if_t *core_if, uint32_t fifo_num)
    ++void release_tx_fifo (dwc_otg_core_if_t *core_if, uint32_t fifo_num)
     This function releases periodic Tx FIFO in shared Tx FIFO mode.
    int dwc_otg_pcd_ep_enable (dwc_otg_pcd_t *pcd, const uint8_t *ep_desc, void *usb_ep)
    int dwc_otg_pcd_ep_enable (dwc_otg_pcd_t *pcd, const uint8_t *ep_desc, void *usb_ep)
     Enables an endpoint for use.
    int dwc_otg_pcd_ep_disable (dwc_otg_pcd_t *pcd, void *ep_handle)
     Enables an endpoint for use.
    int dwc_otg_pcd_ep_disable (dwc_otg_pcd_t *pcd, void *ep_handle)
     Disable the endpoint referenced by ep_handle.
    int dwc_otg_pcd_ep_queue (dwc_otg_pcd_t *pcd, void *ep_handle, uint8_t *buf, dwc_dma_t dma_buf, uint32_t buflen, int zero, void *req_handle, int atomic_alloc)
     Disable the endpoint referenced by ep_handle.
    int dwc_otg_pcd_ep_queue (dwc_otg_pcd_t *pcd, void *ep_handle, uint8_t *buf, dwc_dma_t dma_buf, uint32_t buflen, int zero, void *req_handle, int atomic_alloc)
     Queue a data transfer request on the endpoint referenced by ep_handle.
    int dwc_otg_pcd_ep_dequeue (dwc_otg_pcd_t *pcd, void *ep_handle, void *req_handle)
     Queue a data transfer request on the endpoint referenced by ep_handle.
    int dwc_otg_pcd_ep_dequeue (dwc_otg_pcd_t *pcd, void *ep_handle, void *req_handle)
     De-queue the specified data transfer that has not yet completed.
    int dwc_otg_pcd_ep_halt (dwc_otg_pcd_t *pcd, void *ep_handle, int value)
     De-queue the specified data transfer that has not yet completed.
    int dwc_otg_pcd_ep_halt (dwc_otg_pcd_t *pcd, void *ep_handle, int value)
     Halt (STALL) an endpoint or clear it.
    +-void dwc_otg_pcd_rem_wkup_from_suspend (dwc_otg_pcd_t *pcd, int set)
     Halt (STALL) an endpoint or clear it.
    ++void dwc_otg_pcd_rem_wkup_from_suspend (dwc_otg_pcd_t *pcd, int set)
     This function initiates remote wakeup of the host from suspend state.
    +-void dwc_otg_pcd_remote_wakeup (dwc_otg_pcd_t *pcd, int set)
    ++void dwc_otg_pcd_remote_wakeup (dwc_otg_pcd_t *pcd, int set)
     Starts remote wakeup signaling.
    int dwc_otg_pcd_wakeup (dwc_otg_pcd_t *pcd)
    ++void dwc_otg_pcd_disconnect_us (dwc_otg_pcd_t *pcd, int no_of_usecs)
     This function starts the SRP Protocol if no session is in progress.
    void dwc_otg_pcd_start_srp_timer (dwc_otg_pcd_t *pcd)
     Starts micorsecond soft disconnect.
    int dwc_otg_pcd_wakeup (dwc_otg_pcd_t *pcd)
     Start the SRP timer to detect when the SRP does not complete within 6 seconds.
    +-void dwc_otg_pcd_initiate_srp (dwc_otg_pcd_t *pcd)
     Initiate SRP.
    +-int dwc_otg_pcd_get_frame_number (dwc_otg_pcd_t *pcd)
     This function starts the SRP Protocol if no session is in progress.
    void dwc_otg_pcd_initiate_srp (dwc_otg_pcd_t *pcd)
     Initiate SRP.
    ++int dwc_otg_pcd_get_frame_number (dwc_otg_pcd_t *pcd)
     This function returns current frame number.
    +-int dwc_otg_pcd_is_lpm_enabled (dwc_otg_pcd_t *pcd)
    ++int dwc_otg_pcd_is_lpm_enabled (dwc_otg_pcd_t *pcd)
     This function returns 1 if LPM support is enabled, and 0 otherwise.
    +-uint32_t get_b_hnp_enable (dwc_otg_pcd_t *pcd)
    ++uint32_t get_b_hnp_enable (dwc_otg_pcd_t *pcd)
     These functions allow to get hnp parameters.
    +-uint32_t get_a_hnp_support (dwc_otg_pcd_t *pcd)
    ++uint32_t get_a_hnp_support (dwc_otg_pcd_t *pcd)
    +-uint32_t get_a_alt_hnp_support (dwc_otg_pcd_t *pcd)
    ++uint32_t get_a_alt_hnp_support (dwc_otg_pcd_t *pcd)
    +-int dwc_otg_pcd_get_rmwkup_enable (dwc_otg_pcd_t *pcd)
    ++int dwc_otg_pcd_get_rmwkup_enable (dwc_otg_pcd_t *pcd)
     This function returns 1 if remote wakeup is allowed and 0, otherwise.

    Variables

    static dwc_otg_cil_callbacks_t pcd_callbacks
    dwc_otg_cil_callbacks_t pcd_callbacks
     PCD Callback structure for handling mode switching.
     PCD Callback structure for handling mode switching.
    +

    Detailed Description

    + This file implements PCD Core. +

    +-All code in this file is portable and don't use any OS specific functions. PCD Core provides Interface, defined in <dwc_otg_pcd_if.h> header file, which can be used to implement OS specific PCD interface.

    ++All code in this file is portable and doesn't use any OS specific functions. PCD Core provides Interface, defined in <dwc_otg_pcd_if.h> header file, which can be used to implement OS specific PCD interface.

    + An important function of the PCD is managing interrupts generated by the DWC_otg controller. The implementation of the DWC_otg device mode interrupt service routines is in dwc_otg_pcd_intr.c.

    +

    Todo:
    Add Device Mode test modes (Test J mode, Test K mode, etc).

    +-Does it work when the request size is greater than DEPTSIZ transfer size

    ++Does it work when the request size is greater than DEPTSIZ transfer size + +

    + Definition in file dwc_otg_pcd.c.

    Function Documentation

    +- +-
    +-
    +- ++

    ++

    ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    void dwc_otg_request_done (dwc_otg_pcd_ep_t *  ep, void dwc_otg_request_done ( dwc_otg_pcd_ep_t *  ep,
    dwc_otg_pcd_request_t *  req, dwc_otg_pcd_request_t *  req,
    int32_t  status int32_t  status
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + This function completes a request. +

    + It call's the request call back. +

    +-Definition at line 78 of file dwc_otg_pcd.c. +- +-

    +- +-

    +-
    +- ++Definition at line 81 of file dwc_otg_pcd.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    void dwc_otg_pcd_start (dwc_otg_pcd_t *  pcd, void dwc_otg_pcd_start ( dwc_otg_pcd_t *  pcd,
    const struct dwc_otg_pcd_function_ops *  fops const struct dwc_otg_pcd_function_ops *  fops
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Call this to bind the function driver to the PCD Core. +@@ -280,24 +285,32 @@ + + +

    +-Definition at line 117 of file dwc_otg_pcd.c. +- +-

    +- +-

    +-
    +- +- +- +- +- +- +- +- ++Definition at line 119 of file dwc_otg_pcd.c. ++ ++
    static int32_t dwc_otg_pcd_start_cb (void *  p  )  [static]
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ + +
    int32_t dwc_otg_pcd_start_cb ( void *  p  )  [static]
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + PCD Callback function for initializing the PCD when switching to device mode. +@@ -309,24 +322,32 @@ + + +

    +-Definition at line 129 of file dwc_otg_pcd.c. +- +-

    +- +-

    +-
    +- +- +- +- +- +- +- +- ++Definition at line 131 of file dwc_otg_pcd.c. ++ ++
    static int32_t dwc_otg_pcd_resume_cb (void *  p  )  [static]
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ + +
    int32_t dwc_otg_pcd_resume_cb ( void *  p  )  [static]
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + PCD Callback function for notifying the PCD when resuming from suspend. +@@ -338,24 +359,32 @@ + + +

    +-Definition at line 163 of file dwc_otg_pcd.c. +- +-

    +- +-

    +-
    +- +- +- +- +- +- +- +- ++Definition at line 173 of file dwc_otg_pcd.c. ++ ++
    static int32_t dwc_otg_pcd_suspend_cb (void *  p  )  [static]
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ + +
    int32_t dwc_otg_pcd_suspend_cb ( void *  p  )  [static]
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + PCD Callback function for notifying the PCD device is suspended. +@@ -367,24 +396,32 @@ + + +

    +-Definition at line 187 of file dwc_otg_pcd.c. +- +-

    +- +-

    +-
    +- +- +- +- +- +- +- +- ++Definition at line 197 of file dwc_otg_pcd.c. ++ ++
    static int32_t dwc_otg_pcd_stop_cb (void *  p  )  [static]
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ + +
    int32_t dwc_otg_pcd_stop_cb ( void *  p  )  [static]
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + PCD Callback function for stopping the PCD when switching to Host mode. +@@ -396,33 +433,41 @@ + + +

    +-Definition at line 204 of file dwc_otg_pcd.c. +- +-

    +- +-

    +-
    +- ++Definition at line 216 of file dwc_otg_pcd.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    void dwc_otg_iso_ep_start_ddma_transfer (dwc_otg_core_if_t *  core_if, void dwc_otg_iso_ep_start_ddma_transfer ( dwc_otg_core_if_t *  core_if,
    dwc_ep_t *  dwc_ep dwc_ep_t *  dwc_ep
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + This function initializes a descriptor chain for Isochronous transfer. +@@ -430,49 +475,56 @@ +

    Parameters:
    + + +- ++ +
    core_if Programming view of DWC_otg controller.
    dwc_ep The EP to start the transfer on.
    dwc_ep The EP to start the transfer on.
    +
    +- +

    +-Allocate descriptors for double buffering

    +-ISO OUT EP

    +-Buffer 0 descriptors setup

    +-Buffer 1 descriptors setup

    +-Write dma_ad into DOEPDMA register

    +-ISO IN EP

    +-Buffer 0 descriptors setup

    +-Buffer 1 descriptors setup

    +-Write dma_ad into diepdma register

    ++Allocate descriptors for double buffering

    ++ISO OUT EP

    ++Buffer 0 descriptors setup

    ++Buffer 1 descriptors setup

    ++Write dma_ad into DOEPDMA register

    ++ISO IN EP

    ++Buffer 0 descriptors setup

    ++Buffer 1 descriptors setup

    ++Write dma_ad into diepdma register

    + Enable endpoint, clear nak +

    +-Definition at line 254 of file dwc_otg_pcd.c. +- +-

    +- +-

    +-
    +- ++Definition at line 266 of file dwc_otg_pcd.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    void dwc_otg_iso_ep_start_buf_transfer (dwc_otg_core_if_t *  core_if, void dwc_otg_iso_ep_start_buf_transfer ( dwc_otg_core_if_t *  core_if,
    dwc_ep_t *  ep dwc_ep_t *  ep
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + This function initializes a descriptor chain for Isochronous transfer. +@@ -480,45 +532,52 @@ +

    Parameters:
    + + +- ++ +
    core_if Programming view of DWC_otg controller.
    ep The EP to start the transfer on.
    ep The EP to start the transfer on.
    +
    +- +

    + Enable endpoint, clear nak +

    +-Definition at line 517 of file dwc_otg_pcd.c. +- +-

    +- +-

    +-
    +- ++Definition at line 540 of file dwc_otg_pcd.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    static void dwc_otg_iso_ep_start_transfer (dwc_otg_core_if_t *  core_if, void dwc_otg_iso_ep_start_transfer ( dwc_otg_core_if_t *  core_if,
    dwc_ep_t *  ep dwc_ep_t *  ep
    ) [static])  [static]
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + This function does the setup for a data transfer for an EP and starts the transfer. +

    +-For an IN transfer, the packets will be loaded into the appropriate Tx FIFO in the ISR. For OUT transfers, the packets are unloaded from the Rx FIFO in the ISR. the ISR.

    ++For an IN transfer, the packets will be loaded into the appropriate Tx FIFO in the ISR. For OUT transfers, the packets are unloaded from the Rx FIFO in the ISR.

    +

    Parameters:
    + + +@@ -527,38 +586,45 @@ + + +

    +-Definition at line 598 of file dwc_otg_pcd.c. +- +-

    +- +-

    +-
    +-
    core_if Programming view of DWC_otg controller.
    ++Definition at line 623 of file dwc_otg_pcd.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    void dwc_otg_iso_ep_stop_transfer (dwc_otg_core_if_t *  core_if, void dwc_otg_iso_ep_stop_transfer ( dwc_otg_core_if_t *  core_if,
    dwc_ep_t *  ep dwc_ep_t *  ep
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    +-This function does the setup for a data transfer for an EP and starts the transfer. ++This function stops transfer for an EP and resets the ep's variables. +

    +-For an IN transfer, the packets will be loaded into the appropriate Tx FIFO in the ISR. For OUT transfers, the packets are unloaded from the Rx FIFO in the ISR. the ISR.

    +

    Parameters:
    + + +@@ -567,161 +633,157 @@ + + +

    +-Definition at line 641 of file dwc_otg_pcd.c. +- +-

    +- +-

    +-
    +-
    core_if Programming view of DWC_otg controller.
    ++Definition at line 664 of file dwc_otg_pcd.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    int dwc_otg_pcd_iso_ep_start (dwc_otg_pcd_t *  pcd, int dwc_otg_pcd_iso_ep_start ( dwc_otg_pcd_t *  pcd,
    void *  ep_handle, void *  ep_handle,
    uint8_t *  buf0, uint8_t *  buf0,
    uint8_t *  buf1, uint8_t *  buf1,
    dwc_dma_t  dma0, dwc_dma_t  dma0,
    dwc_dma_t  dma1, dwc_dma_t  dma1,
    int  sync_frame, int  sync_frame,
    int  dp_frame, int  dp_frame,
    int  data_per_frame, int  data_per_frame,
    int  start_frame, int  start_frame,
    int  buf_proc_intrvl, int  buf_proc_intrvl,
    void *  req_handle, void *  req_handle,
    int  atomic_alloc int  atomic_alloc
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Start isochronous transfers on the endpoint referenced by ep_handle. +

    +-For isochronous transfers duble buffering is used. After processing each of buffers comlete callback will be called with status for each transaction.

    +-

    Parameters:
    +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
    pcd The PCD
    ep_handle The handle of the endpoint
    buf0 The virtual address of first data buffer
    buf1 The virtual address of second data buffer
    dma0 The DMA address of first data buffer
    dma1 The DMA address of second data buffer
    sync_frame Data pattern frame number
    dp_frame Data size for pattern frame
    data_per_frame Data size for regular frame
    start_frame Frame number to start transfers, if -1 then start transfers ASAP.
    buf_proc_intrvl Interval of ISOC Buffer processing
    req_handle Handle of ISOC request
    atomic_alloc Specefies whether to perform atomic allocation for internal data structures.
    +-
    +-Returns -DWC_E_NO_MEMORY if there is no enough memory. Returns -DWC_E_INVALID if incorrect arguments are passed to the function. Returns -DW_E_SHUTDOWN for any other error. Returns 0 on success +-

    +

    Todo:
      +-
    • pattern data support is to be implemented in the future
    ++
  • pattern data support is to be implemented in the future
    • +
    + +

    +-Definition at line 685 of file dwc_otg_pcd.c. +- +-

    +- +-

    +-
    +- ++Definition at line 708 of file dwc_otg_pcd.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    int dwc_otg_pcd_iso_ep_stop (dwc_otg_pcd_t *  pcd, int dwc_otg_pcd_iso_ep_stop ( dwc_otg_pcd_t *  pcd,
    void *  ep_handle, void *  ep_handle,
    void *  req_handle void *  req_handle
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Stop ISOC transfers on endpoint referenced by ep_handle. +@@ -735,39 +797,47 @@ + + Returns -DWC_E_INVALID if incorrect arguments are passed to the function Returns 0 on success +

    +-Definition at line 794 of file dwc_otg_pcd.c. +- +-

    +- +-

    +-
    +- ++Definition at line 817 of file dwc_otg_pcd.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    void dwc_otg_iso_buffer_done (dwc_otg_pcd_t *  pcd, void dwc_otg_iso_buffer_done ( dwc_otg_pcd_t *  pcd,
    dwc_otg_pcd_ep_t *  ep, dwc_otg_pcd_ep_t *  ep,
    void *  req_handle void *  req_handle
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + This function is used for perodical data exchnage between PCD and gadget drivers. +@@ -777,39 +847,47 @@ +

  • Every time a sync period completes this function is called to perform data exchange between PCD and gadget
    • + +

    +-Definition at line 830 of file dwc_otg_pcd.c. +- +-

    +- +-

    +-
    +- ++Definition at line 853 of file dwc_otg_pcd.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    int dwc_otg_pcd_get_iso_packet_count (dwc_otg_pcd_t *  pcd, int dwc_otg_pcd_get_iso_packet_count ( dwc_otg_pcd_t *  pcd,
    void *  ep_handle, void *  ep_handle,
    void *  iso_req_handle void *  iso_req_handle
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Get ISOC packet count. +@@ -823,63 +901,71 @@ + + +

    +-Definition at line 850 of file dwc_otg_pcd.c. +- +-

    +- +-

    +-
    +- ++Definition at line 873 of file dwc_otg_pcd.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    void dwc_otg_pcd_get_iso_packet_params (dwc_otg_pcd_t *  pcd, void dwc_otg_pcd_get_iso_packet_params ( dwc_otg_pcd_t *  pcd,
    void *  ep_handle, void *  ep_handle,
    void *  iso_req_handle, void *  iso_req_handle,
    int  packet, int  packet,
    int *  status, int *  status,
    int *  actual, int *  actual,
    int *  offset int *  offset
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Get ISOC packet status. +@@ -897,107 +983,131 @@ + + +

    +-Definition at line 862 of file dwc_otg_pcd.c. +- +-

    +- +-

    +-
    +- +- +- +- +- +- +- +- ++Definition at line 889 of file dwc_otg_pcd.c. ++ ++
    static void dwc_otg_pcd_reinit (dwc_otg_pcd_t *  pcd  )  [static]
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ + +
    void dwc_otg_pcd_reinit ( dwc_otg_pcd_t *  pcd  )  [static]
    +- +-
    +- +-

    +-Initialise ep's. +-

    ++

    ++ ++ ++ ++
    ++   ++ + +

    +-Initialize the EP0 structure.

    +-

    Todo:
    NGS: Add direction to EP, based on contents of HWCFG1. Need a copy of HWCFG1 in pcd structure? sprintf(";r
    ++Initialize ep's. +

    +-

    Todo:
    NGS: Add direction to EP, based on contents of HWCFG1. Need a copy of HWCFG1 in pcd structure? sprintf(";r
    ++Initialize the EP0 structure.

    ++

    Todo:
    NGS: Add direction to EP, based on contents of HWCFG1. Need a copy of HWCFG1 in pcd structure? sprintf(";r

    ++NGS: Add direction to EP, based on contents of HWCFG1. Need a copy of HWCFG1 in pcd structure? sprintf(";r

    + +

    +-Definition at line 911 of file dwc_otg_pcd.c. +- +-

    +- +-

    +-
    +- +- +- +- +- +- +- +- ++Definition at line 941 of file dwc_otg_pcd.c. ++ ++
    static void srp_timeout (void *  ptr  )  [static]
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ + +
    void srp_timeout ( void *  ptr  )  [static]
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + This function is called when the SRP timer expires. +

    + The SRP should complete within 6 seconds. +

    +-Definition at line 970 of file dwc_otg_pcd.c. +- +-

    +- +-

    +-
    +- +- +- +- +- +- +- +- ++Definition at line 1000 of file dwc_otg_pcd.c. ++ ++
    dwc_otg_pcd_t* dwc_otg_pcd_init (dwc_otg_core_if_t *  core_if  ) 
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ + +
    dwc_otg_pcd_t* dwc_otg_pcd_init ( dwc_otg_core_if_t *  core_if  ) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Call this function to get pointer on dwc_otg_pcd_t, this pointer will be used for all PCD API functions. +

    +-

    Parameters:
    +- +- +-
    core_if The DWC_OTG Core
    +-
    +- ++Initialize xfer timeout timer. Implemented for 2.93a feature "Device DDMA OUT NAK Enhancement" +

    +-Definition at line 1056 of file dwc_otg_pcd.c. +- +-

    +- +-

    +-
    +- +- +- +- +- +- +- +- ++Definition at line 1110 of file dwc_otg_pcd.c. ++ ++
    void dwc_otg_pcd_remove (dwc_otg_pcd_t *  pcd  ) 
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ + +
    void dwc_otg_pcd_remove ( dwc_otg_pcd_t *  pcd  ) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Frees PCD allocated by dwc_otg_pcd_init. +@@ -1009,39 +1119,47 @@ + + +

    +-Definition at line 1215 of file dwc_otg_pcd.c. +- +-

    +- +-

    +-
    +- ++Definition at line 1309 of file dwc_otg_pcd.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    int dwc_otg_pcd_ep_enable (dwc_otg_pcd_t *  pcd, int dwc_otg_pcd_ep_enable ( dwc_otg_pcd_t *  pcd,
    const uint8_t *  ep_desc, const uint8_t *  ep_desc,
    void *  ep_handle void *  usb_ep
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Enables an endpoint for use. +@@ -1052,252 +1170,285 @@ + + + +- ++ +
    pcd The PCD
    ep_desc Endpoint descriptor
    ep_handle Handle on endpoint, that will be used to identify endpoint.
    usb_ep Handle on endpoint, that will be used to identify endpoint.
    + + +

    +-Definition at line 1341 of file dwc_otg_pcd.c. +- +-

    +- +-

    +-
    +- ++Definition at line 1461 of file dwc_otg_pcd.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    int dwc_otg_pcd_ep_disable (dwc_otg_pcd_t *  pcd, int dwc_otg_pcd_ep_disable ( dwc_otg_pcd_t *  pcd,
    void *  ep_handle void *  ep_handle
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Disable the endpoint referenced by ep_handle. +

    +-Returns -DWC_E_INVALID if invalid parameters were passed. Returns -DWC_E_SHUTDOWN if any other error ocurred. Returns 0 on success. ++Returns -DWC_E_INVALID if invalid parameters were passed. Returns -DWC_E_SHUTDOWN if any other error occurred. Returns 0 on success. +

    +-Definition at line 1449 of file dwc_otg_pcd.c. +- +-

    +- +-

    +-
    +- ++Definition at line 1622 of file dwc_otg_pcd.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    int dwc_otg_pcd_ep_queue (dwc_otg_pcd_t *  pcd, int dwc_otg_pcd_ep_queue ( dwc_otg_pcd_t *  pcd,
    void *  ep_handle, void *  ep_handle,
    uint8_t *  buf, uint8_t *  buf,
    dwc_dma_t  dma_buf, dwc_dma_t  dma_buf,
    uint32_t  buflen, uint32_t  buflen,
    int  zero, int  zero,
    void *  req_handle, void *  req_handle,
    int  atomic_alloc int  atomic_alloc
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Queue a data transfer request on the endpoint referenced by ep_handle. +

    +-After the transfer is completes, the complete callback will be called with the request status.

    +-

    Parameters:
    +- +- +- +- +- +- +- +- +- +-
    pcd The PCD
    ep_handle The handle of the endpoint
    buf The buffer for the data
    dma_buf The DMA buffer for the data
    buflen The length of the data transfer
    zero Specifies whether to send zero length last packet.
    req_handle Set this handle to any value to use to reference this request in the ep_dequeue function or from the complete callback
    atomic_alloc If driver need to perform atomic allocations for internal data structures.
    +-
    +-Returns -DWC_E_INVALID if invalid parameters were passed. Returns -DWC_E_SHUTDOWN if any other error ocurred. Returns 0 on success. +-

    +-

    Todo:
    NGS Create a function for this.
    ++
    Todo:
    NGS Create a function for this.
    + +

    +-Definition at line 1502 of file dwc_otg_pcd.c. +- +-

    +- +-

    +-
    +- ++Definition at line 2079 of file dwc_otg_pcd.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    int dwc_otg_pcd_ep_dequeue (dwc_otg_pcd_t *  pcd, int dwc_otg_pcd_ep_dequeue ( dwc_otg_pcd_t *  pcd,
    void *  ep_handle, void *  ep_handle,
    void *  req_handle void *  req_handle
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + De-queue the specified data transfer that has not yet completed. +

    + Returns -DWC_E_INVALID if invalid parameters were passed. Returns -DWC_E_SHUTDOWN if any other error ocurred. Returns 0 on success. +

    +-Definition at line 1694 of file dwc_otg_pcd.c. +- +-

    +- +-

    +-
    +- ++Definition at line 2306 of file dwc_otg_pcd.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    int dwc_otg_pcd_ep_halt (dwc_otg_pcd_t *  pcd, int dwc_otg_pcd_ep_halt ( dwc_otg_pcd_t *  pcd,
    void *  ep_handle, void *  ep_handle,
    int  value int  value
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Halt (STALL) an endpoint or clear it. +

    + Returns -DWC_E_INVALID if invalid parameters were passed. Returns -DWC_E_SHUTDOWN if any other error ocurred. Returns -DWC_E_AGAIN if the STALL cannot be sent and must be tried again later Returns 0 on success. +

    +-Definition at line 1733 of file dwc_otg_pcd.c. +- +-

    +- +-

    +-
    +- +- +- +- +- +- +- +- ++Definition at line 2345 of file dwc_otg_pcd.c. ++ ++
    int dwc_otg_pcd_wakeup (dwc_otg_pcd_t *  pcd  ) 
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ + +
    int dwc_otg_pcd_wakeup ( dwc_otg_pcd_t *  pcd  ) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + This function starts the SRP Protocol if no session is in progress. +

    + If a session is already in progress, but the device is suspended, remote wakeup signaling is started. +

    +-Definition at line 1896 of file dwc_otg_pcd.c. +- +-

    +- +-

    +-
    +- +- +- +- +- +- +- +- ++Definition at line 2559 of file dwc_otg_pcd.c. ++ ++
    void dwc_otg_pcd_start_srp_timer (dwc_otg_pcd_t *  pcd  ) 
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ + +
    void dwc_otg_pcd_initiate_srp ( dwc_otg_pcd_t *  pcd  ) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    +-Start the SRP timer to detect when the SRP does not complete within 6 seconds. ++Initiate SRP. +

    +

    Parameters:
    + +@@ -1306,38 +1457,46 @@ + + +

    +-Definition at line 1937 of file dwc_otg_pcd.c. +- +-

    ++Definition at line 2596 of file dwc_otg_pcd.c. ++ ++

    +

    Variable Documentation

    +- +-
    +-
    +- ++

    ++

    ++ ++ ++ ++
    ++ + +- ++ + +
    dwc_otg_cil_callbacks_t pcd_callbacks [static] dwc_otg_cil_callbacks_t pcd_callbacks [static]
    +- +-
    ++
    ++ ++ ++ ++ ++ ++
    ++   ++ + +

    + Initial value:

     {
+-        .start = dwc_otg_pcd_start_cb,
+-        .stop = dwc_otg_pcd_stop_cb,
+-        .suspend = dwc_otg_pcd_suspend_cb,
+-        .resume_wakeup = dwc_otg_pcd_resume_cb,
++        .start = dwc_otg_pcd_start_cb,
++        .stop = dwc_otg_pcd_stop_cb,
++        .suspend = dwc_otg_pcd_suspend_cb,
++        .resume_wakeup = dwc_otg_pcd_resume_cb,
+         .p = 0,                 
+ }
+
    PCD Callback structure for handling mode switching. +

    + +

    +-Definition at line 216 of file dwc_otg_pcd.c. +- +-

    +-

    Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++Definition at line 228 of file dwc_otg_pcd.c.
    ++
    Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
    ++doxygen 1.3.9.1 + + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__pcd_8h-source.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/dwc__otg__pcd_8h-source.html 2013-07-26 19:31:21.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__pcd_8h-source.html 2013-07-26 19:34:42.000000000 +0000 +@@ -2,170 +2,188 @@ + + DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_pcd.h Source File + +- + +- +-
    +-
    +-
    +-
    +-

    dwc_otg_pcd.h

    Go to the documentation of this file.
    00001 /* ==========================================================================
+-00002  * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_pcd.h $
+-00003  * $Revision: #39 $
+-00004  * $Date: 2008/12/16 $
+-00005  * $Change: 1153731 $
+-00006  *
+-00007  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
+-00008  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
+-00009  * otherwise expressly agreed to in writing between Synopsys and you.
+-00010  *
+-00011  * The Software IS NOT an item of Licensed Software or Licensed Product under
+-00012  * any End User Software License Agreement or Agreement for Licensed Product
+-00013  * with Synopsys or any supplement thereto. You are permitted to use and
+-00014  * redistribute this Software in source and binary forms, with or without
+-00015  * modification, provided that redistributions of source code must retain this
+-00016  * notice. You may not view, use, disclose, copy or distribute this file or
+-00017  * any information contained herein except pursuant to this license grant from
+-00018  * Synopsys. If you do not agree with this notice, including the disclaimer
+-00019  * below, then you are not authorized to use the Software.
+-00020  *
+-00021  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
+-00022  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+-00023  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+-00024  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
+-00025  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+-00026  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+-00027  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+-00028  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+-00029  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+-00030  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+-00031  * DAMAGE.
+-00032  * ========================================================================== */
+-00033 #ifndef DWC_HOST_ONLY
+-00034 #if !defined(__DWC_PCD_H__)
+-00035 #define __DWC_PCD_H__
+-00036 
+-00037 #include "usb.h"
+-00038 #include "dwc_otg_cil.h"
+-00039 #include "dwc_otg_pcd_if.h"
+-00040 struct cfiobject;
+-00041 
+-00058 #define DDMA_MAX_TRANSFER_SIZE 65535
+-00059 
+-00061 #define MAX_DMA_DESC_CNT 64
+-00062 
+-00066 #define GET_CORE_IF( _pcd ) (_pcd->core_if)
+-00067 
+-00071 typedef enum ep0_state {
+-00072         EP0_DISCONNECT,         /* no host */
+-00073         EP0_IDLE,
+-00074         EP0_IN_DATA_PHASE,
+-00075         EP0_OUT_DATA_PHASE,
+-00076         EP0_IN_STATUS_PHASE,
+-00077         EP0_OUT_STATUS_PHASE,
+-00078         EP0_STALL,
+-00079 } ep0state_e;
+-00080 
+-00082 struct dwc_otg_pcd;
+-00083 
+-00087 typedef struct usb_iso_request dwc_otg_pcd_iso_request_t;
+-00088 
+-00092 typedef struct dwc_otg_pcd_request {
+-00093         void *priv;
+-00094         void *buf;
+-00095         dwc_dma_t dma;
+-00096         uint32_t length;
+-00097         uint32_t actual;
+-00098         unsigned sent_zlp:1;
+-00099 
+-00100          DWC_CIRCLEQ_ENTRY(dwc_otg_pcd_request) queue_entry;
+-00101 } dwc_otg_pcd_request_t;
+-00102 
+-00103 DWC_CIRCLEQ_HEAD(req_list, dwc_otg_pcd_request);
+-00104 
+-00109 typedef struct dwc_otg_pcd_ep {
+-00111         const usb_endpoint_descriptor_t *desc;
+-00112 
+-00114         struct req_list queue;
+-00115         unsigned stopped:1;
+-00116         unsigned disabling:1;
+-00117         unsigned dma:1;
+-00118         unsigned queue_sof:1;
+-00119 
+-00120 #ifdef DWC_EN_ISOC
+-00121 
+-00122         void *iso_req_handle;
+-00123 #endif                          //_EN_ISOC_
+-00124 
+-00126         dwc_ep_t dwc_ep;
+-00127 
+-00129         struct dwc_otg_pcd *pcd;
+-00130 
+-00131         void *priv;
+-00132 } dwc_otg_pcd_ep_t;
+-00133 
+-00137 struct dwc_otg_pcd {
+-00138         const struct dwc_otg_pcd_function_ops *fops;
+-00140         dwc_otg_core_if_t *core_if;
+-00142         ep0state_e ep0state;
+-00144         unsigned ep0_pending:1;
+-00146         unsigned request_config:1;
+-00148         unsigned remote_wakeup_enable:1;
+-00150         unsigned b_hnp_enable:1;
+-00152         unsigned a_hnp_support:1;
+-00154         unsigned a_alt_hnp_support:1;
+-00156         unsigned request_pending;
+-00157 
+-00162         union {
+-00163                 usb_device_request_t req;
+-00164                 uint32_t d32[2];
+-00165         } *setup_pkt;
+-00166 
+-00167         dwc_dma_t setup_pkt_dma_handle;
+-00168 
+-00170         uint16_t *status_buf;
+-00171         dwc_dma_t status_buf_dma_handle;
+-00172 
+-00174         dwc_otg_pcd_ep_t ep0;
+-00175 
+-00177         dwc_otg_pcd_ep_t in_ep[MAX_EPS_CHANNELS - 1];
+-00179         dwc_otg_pcd_ep_t out_ep[MAX_EPS_CHANNELS - 1];
+-00181 //        unsigned      num_eps : 4;
+-00182         dwc_spinlock_t *lock;
+-00185         dwc_timer_t *srp_timer;
+-00186 
+-00190         dwc_tasklet_t *test_mode_tasklet;
+-00191 
+-00193         dwc_tasklet_t *start_xfer_tasklet;
+-00194 
+-00196         unsigned test_mode;
+-00200 #ifdef DWC_UTE_CFI
+-00201         struct cfiobject *cfi;
+-00202 #endif
+-00203 
+-00204 };
+-00205 
+-00206 //FIXME this functions should be static, and this prototypes should be removed
+-00207 extern void dwc_otg_request_nuke(dwc_otg_pcd_ep_t * ep);
+-00208 extern void dwc_otg_request_done(dwc_otg_pcd_ep_t * ep,
+-00209                                  dwc_otg_pcd_request_t * req, int32_t status);
+-00210 
+-00211 void dwc_otg_iso_buffer_done(dwc_otg_pcd_t * pcd, dwc_otg_pcd_ep_t * ep,
+-00212                              void *req_handle);
+-00213 
+-00214 extern void do_test_mode(void *data);
+-00215 #endif
+-00216 #endif                          /* DWC_HOST_ONLY */
+-
    Generated on Tue May 5 02:22:48 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++
    Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
    ++

    dwc_otg_pcd.h

    Go to the documentation of this file.
    00001 /* ==========================================================================
++00002  * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_pcd.h $
++00003  * $Revision: #46 $
++00004  * $Date: 2011/10/20 $
++00005  * $Change: 1870124 $
++00006  *
++00007  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
++00008  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
++00009  * otherwise expressly agreed to in writing between Synopsys and you.
++00010  *
++00011  * The Software IS NOT an item of Licensed Software or Licensed Product under
++00012  * any End User Software License Agreement or Agreement for Licensed Product
++00013  * with Synopsys or any supplement thereto. You are permitted to use and
++00014  * redistribute this Software in source and binary forms, with or without
++00015  * modification, provided that redistributions of source code must retain this
++00016  * notice. You may not view, use, disclose, copy or distribute this file or
++00017  * any information contained herein except pursuant to this license grant from
++00018  * Synopsys. If you do not agree with this notice, including the disclaimer
++00019  * below, then you are not authorized to use the Software.
++00020  *
++00021  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
++00022  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++00023  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++00024  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
++00025  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++00026  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
++00027  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
++00028  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
++00029  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
++00030  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
++00031  * DAMAGE.
++00032  * ========================================================================== */
++00033 #ifndef DWC_HOST_ONLY
++00034 #if !defined(__DWC_PCD_H__)
++00035 #define __DWC_PCD_H__
++00036 
++00037 #include "dwc_otg_os_dep.h"
++00038 #include "usb.h"
++00039 #include "dwc_otg_cil.h"
++00040 #include "dwc_otg_pcd_if.h"
++00041 struct cfiobject;
++00042 
++00059 #define DWC_DMA_ADDR_INVALID    (~(dwc_dma_t)0)
++00060 
++00062 #define DDMA_MAX_TRANSFER_SIZE 65535
++00063 
++00067 #define GET_CORE_IF( _pcd ) (_pcd->core_if)
++00068 
++00072 typedef enum ep0_state {
++00073         EP0_DISCONNECT,         /* no host */
++00074         EP0_IDLE,
++00075         EP0_IN_DATA_PHASE,
++00076         EP0_OUT_DATA_PHASE,
++00077         EP0_IN_STATUS_PHASE,
++00078         EP0_OUT_STATUS_PHASE,
++00079         EP0_STALL,
++00080 } ep0state_e;
++00081 
++00083 struct dwc_otg_pcd;
++00084 
++00088 typedef struct usb_iso_request dwc_otg_pcd_iso_request_t;
++00089 
++00090 #ifdef DWC_UTE_PER_IO
++00091 
++00096 struct dwc_iso_pkt_desc_port {
++00097         uint32_t offset;
++00098         uint32_t length;        /* expected length */
++00099         uint32_t actual_length;
++00100         uint32_t status;
++00101 };
++00102 
++00103 struct dwc_iso_xreq_port {
++00105         uint32_t tr_sub_flags;
++00107 #define DWC_EREQ_TF_ASAP                0x00000002
++00108 
++00109 #define DWC_EREQ_TF_ENQUEUE             0x00000004
++00110 
++00115         uint32_t pio_pkt_count;
++00117         uint32_t pio_alloc_pkt_count;
++00119         uint32_t error_count;
++00121         uint32_t res;
++00123         struct dwc_iso_pkt_desc_port *per_io_frame_descs;
++00124 };
++00125 #endif
++00126 
++00129 typedef struct dwc_otg_pcd_request {
++00130         void *priv;
++00131         void *buf;
++00132         dwc_dma_t dma;
++00133         uint32_t length;
++00134         uint32_t actual;
++00135         unsigned sent_zlp:1;
++00140      uint8_t *dw_align_buf;
++00141      dwc_dma_t dw_align_buf_dma;
++00142 
++00143          DWC_CIRCLEQ_ENTRY(dwc_otg_pcd_request) queue_entry;
++00144 #ifdef DWC_UTE_PER_IO
++00145         struct dwc_iso_xreq_port ext_req;
++00146         //void *priv_ereq_nport; /*  */
++00147 #endif
++00148 } dwc_otg_pcd_request_t;
++00149 
++00150 DWC_CIRCLEQ_HEAD(req_list, dwc_otg_pcd_request);
++00151 
++00156 typedef struct dwc_otg_pcd_ep {
++00158         const usb_endpoint_descriptor_t *desc;
++00159 
++00161         struct req_list queue;
++00162         unsigned stopped:1;
++00163         unsigned disabling:1;
++00164         unsigned dma:1;
++00165         unsigned queue_sof:1;
++00166 
++00167 #ifdef DWC_EN_ISOC
++00168 
++00169         void *iso_req_handle;
++00170 #endif                          //_EN_ISOC_
++00171 
++00173         dwc_ep_t dwc_ep;
++00174 
++00176         struct dwc_otg_pcd *pcd;
++00177 
++00178         void *priv;
++00179 } dwc_otg_pcd_ep_t;
++00180 
++00184 struct dwc_otg_pcd {
++00185         const struct dwc_otg_pcd_function_ops *fops;
++00187         struct dwc_otg_device *otg_dev;
++00189         dwc_otg_core_if_t *core_if;
++00191         ep0state_e ep0state;
++00193         unsigned ep0_pending:1;
++00195         unsigned request_config:1;
++00197         unsigned remote_wakeup_enable:1;
++00199         unsigned b_hnp_enable:1;
++00201         unsigned a_hnp_support:1;
++00203         unsigned a_alt_hnp_support:1;
++00205         unsigned request_pending;
++00206 
++00211         union {
++00212                 usb_device_request_t req;
++00213                 uint32_t d32[2];
++00214         } *setup_pkt;
++00215 
++00216         dwc_dma_t setup_pkt_dma_handle;
++00217 
++00219         uint16_t *status_buf;
++00220         dwc_dma_t status_buf_dma_handle;
++00221 
++00223         dwc_otg_pcd_ep_t ep0;
++00224 
++00226         dwc_otg_pcd_ep_t in_ep[MAX_EPS_CHANNELS - 1];
++00228         dwc_otg_pcd_ep_t out_ep[MAX_EPS_CHANNELS - 1];
++00230 //        unsigned      num_eps : 4;
++00231         dwc_spinlock_t *lock;
++00232 
++00236         dwc_tasklet_t *test_mode_tasklet;
++00237 
++00239         dwc_tasklet_t *start_xfer_tasklet;
++00240 
++00242         unsigned test_mode;
++00246 #ifdef DWC_UTE_CFI
++00247         struct cfiobject *cfi;
++00248 #endif
++00249 
++00250 };
++00251 
++00252 //FIXME this functions should be static, and this prototypes should be removed
++00253 extern void dwc_otg_request_nuke(dwc_otg_pcd_ep_t * ep);
++00254 extern void dwc_otg_request_done(dwc_otg_pcd_ep_t * ep,
++00255                                  dwc_otg_pcd_request_t * req, int32_t status);
++00256 
++00257 void dwc_otg_iso_buffer_done(dwc_otg_pcd_t * pcd, dwc_otg_pcd_ep_t * ep,
++00258                              void *req_handle);
++00259 
++00260 extern void do_test_mode(void *data);
++00261 #endif
++00262 #endif /* DWC_HOST_ONLY */
++
    Generated on Thu Oct 27 03:56:37 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
    ++doxygen 1.3.9.1
    + + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__pcd_8h.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/dwc__otg__pcd_8h.html 2013-07-26 19:31:21.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__pcd_8h.html 2013-07-26 19:34:42.000000000 +0000 +@@ -2,26 +2,15 @@ + + DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_pcd.h File Reference + +- + +- +-
    +-
    +-
    +-
    ++ ++
    Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
    +

    dwc_otg_pcd.h File Reference

    This file contains the structures, constants, and interfaces for the Perpherial Contoller Driver (PCD). More... +

    +-#include "usb.h"
    +-#include "dwc_otg_cil.h"
    +-#include "dwc_otg_pcd_if.h"
    ++#include "dwc_otg_os_dep.h"
    ++#include "usb.h"
    ++#include "dwc_otg_cil.h"
    ++#include "dwc_otg_pcd_if.h"
    + +

    + Go to the source code of this file. +@@ -37,38 +26,38 @@ + + + +- ++ + +- ++ + +- +- ++ ++ + +- +- ++ ++ + + + +- ++ + + +- ++ + + +- ++ + +- +- ++ ++ + +- ++ + +- + +- + +- ++ + + +- ++ + +- +- ++ ++ + +- +- ++ ++ + +- ++ +
     DWC_otg PCD Structure. More...

    Defines

    +-#define __DWC_PCD_H__
    ++#define __DWC_PCD_H__
    +-#define DDMA_MAX_TRANSFER_SIZE   65535
    ++#define DWC_DMA_ADDR_INVALID   (~(dwc_dma_t)0)
     Max Transfer size for any EP.
    +-#define MAX_DMA_DESC_CNT   64
     Invalid DMA Address.
    ++#define DDMA_MAX_TRANSFER_SIZE   65535
     Max DMA Descriptor count for any EP.
    +-#define GET_CORE_IF(_pcd)   (_pcd->core_if)
     Max Transfer size for any EP.
    ++#define GET_CORE_IF(_pcd)   (_pcd->core_if)
     Get the pointer to the core_if from the pcd pointer.

    Typedefs

    +-typedef enum ep0_state ep0state_e
    ++typedef enum ep0_state ep0state_e
     States of EP0.
    +-typedef usb_iso_request dwc_otg_pcd_iso_request_t
    ++typedef usb_iso_request dwc_otg_pcd_iso_request_t
     DWC_otg iso request structure.
    typedef dwc_otg_pcd_request dwc_otg_pcd_request_t
    typedef dwc_otg_pcd_request dwc_otg_pcd_request_t
     DWC_otg request structure.
    typedef dwc_otg_pcd_ep dwc_otg_pcd_ep_t
     DWC_otg request structure.
    typedef dwc_otg_pcd_ep dwc_otg_pcd_ep_t
     PCD EP structure.
     PCD EP structure.

    Enumerations

    enum  ep0_state {
    ++
    enum  ep0_state {
    +   EP0_DISCONNECT, + EP0_IDLE, + EP0_IN_DATA_PHASE, +@@ -82,133 +71,165 @@ + +
     States of EP0.

    Functions

    ++
    +  DWC_CIRCLEQ_HEAD (req_list, dwc_otg_pcd_request)
    +-void dwc_otg_request_nuke (dwc_otg_pcd_ep_t *ep)
    ++void dwc_otg_request_nuke (dwc_otg_pcd_ep_t *ep)
     This function terminates all the requsts in the EP request queue.
    void dwc_otg_request_done (dwc_otg_pcd_ep_t *ep, dwc_otg_pcd_request_t *req, int32_t status)
    void dwc_otg_request_done (dwc_otg_pcd_ep_t *ep, dwc_otg_pcd_request_t *req, int32_t status)
     This function completes a request.
    void dwc_otg_iso_buffer_done (dwc_otg_pcd_t *pcd, dwc_otg_pcd_ep_t *ep, void *req_handle)
     This function completes a request.
    void dwc_otg_iso_buffer_done (dwc_otg_pcd_t *pcd, dwc_otg_pcd_ep_t *ep, void *req_handle)
     This function is used for perodical data exchnage between PCD and gadget drivers.
    void do_test_mode (void *data)
     This function is used for perodical data exchnage between PCD and gadget drivers.
    void do_test_mode (void *data)
     This function is called when the SET_FEATURE TEST_MODE Setup packet is sent from the host.
     This function is called when the SET_FEATURE TEST_MODE Setup packet is sent from the host.
    +

    Detailed Description

    + This file contains the structures, constants, and interfaces for the Perpherial Contoller Driver (PCD). +

    +-The Peripheral Controller Driver (PCD) for Linux will implement the Gadget API, so that the existing Gadget drivers can be used. For the Mass Storage Function driver the File-backed USB Storage Gadget (FBS) driver will be used. The FBS driver supports the Control-Bulk (CB), Control-Bulk-Interrupt (CBI), and Bulk-Only transports. ++The Peripheral Controller Driver (PCD) for Linux will implement the Gadget API, so that the existing Gadget drivers can be used. For the Mass Storage Function driver the File-backed USB Storage Gadget (FBS) driver will be used. The FBS driver supports the Control-Bulk (CB), Control-Bulk-Interrupt (CBI), and Bulk-Only transports. +

    + Definition in file dwc_otg_pcd.h.

    Typedef Documentation

    +- +-
    +-
    +- ++

    ++

    ++ ++ ++ ++
    ++ + +- ++ + +
    typedef struct dwc_otg_pcd_request dwc_otg_pcd_request_t typedef struct dwc_otg_pcd_request dwc_otg_pcd_request_t
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + DWC_otg request structure. +

    +-This structure is a list of requests. +- +-

    +- +-

    +-
    +- ++This structure is a list of requests. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- ++ + +
    typedef struct dwc_otg_pcd_ep dwc_otg_pcd_ep_t typedef struct dwc_otg_pcd_ep dwc_otg_pcd_ep_t
    +- +-
    ++
    ++ ++ ++ ++ ++ ++
    ++   ++ + +

    + PCD EP structure. +

    +-This structure describes an EP, there is an array of EPs in the PCD structure. +- +-

    ++This structure describes an EP, there is an array of EPs in the PCD structure.

    +

    Function Documentation

    +- +-
    +-
    +- ++

    ++

    ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    void dwc_otg_request_done (dwc_otg_pcd_ep_t *  ep, void dwc_otg_request_done ( dwc_otg_pcd_ep_t *  ep,
    dwc_otg_pcd_request_t *  req, dwc_otg_pcd_request_t *  req,
    int32_t  status int32_t  status
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + This function completes a request. +

    + It call's the request call back. +

    +-Definition at line 78 of file dwc_otg_pcd.c. +- +-

    +- +-

    +-
    +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- ++Definition at line 81 of file dwc_otg_pcd.c. ++ ++
    void dwc_otg_iso_buffer_done (dwc_otg_pcd_t *  pcd,
    dwc_otg_pcd_ep_t *  ep,
    void *  req_handle 
    )
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ + +
    void dwc_otg_iso_buffer_done ( dwc_otg_pcd_t *  pcd,
    dwc_otg_pcd_ep_t *  ep,
    void *  req_handle
    ) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + This function is used for perodical data exchnage between PCD and gadget drivers. +@@ -218,37 +239,45 @@ +

  • Every time a sync period completes this function is called to perform data exchange between PCD and gadget
    • + +

    +-Definition at line 830 of file dwc_otg_pcd.c. +- +-

    +- +-

    +-
    +- +- +- +- +- +- +- +- ++Definition at line 853 of file dwc_otg_pcd.c. ++ ++
    void do_test_mode (void *  data  ) 
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ + +
    void do_test_mode ( void *  data  ) 
    +- +-
    ++
    ++ ++ ++ ++ ++ ++
    ++   ++ + +

    + This function is called when the SET_FEATURE TEST_MODE Setup packet is sent from the host. +

    + The Device Control register is written with the Test Mode bits set to the specified Test Mode. This is done as a tasklet so that the "Status" phase of the control transfer completes before transmitting the TEST packets.

    +-

    Todo:
    This has not been tested since the tasklet struct was put into the PCD struct!
    ++
    Todo:
    This has not been tested since the tasklet struct was put into the PCD struct!
    + +

    +-Definition at line 1284 of file dwc_otg_pcd_intr.c. +- +-

    +-

    Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++Definition at line 1423 of file dwc_otg_pcd_intr.c.
    ++

    Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
    ++doxygen 1.3.9.1 + + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__pcd__if_8h-source.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/dwc__otg__pcd__if_8h-source.html 2013-07-26 19:31:21.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__pcd__if_8h-source.html 2013-07-26 19:34:42.000000000 +0000 +@@ -2,173 +2,177 @@ + + DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_pcd_if.h Source File + +- + +- +-
    +-
    +-
    +-
    +-

    dwc_otg_pcd_if.h

    Go to the documentation of this file.
    00001 /* ==========================================================================
+-00002  * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_pcd_if.h $
+-00003  * $Revision: #6 $
+-00004  * $Date: 2009/04/03 $
+-00005  * $Change: 1225059 $
+-00006  *
+-00007  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
+-00008  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
+-00009  * otherwise expressly agreed to in writing between Synopsys and you.
+-00010  *
+-00011  * The Software IS NOT an item of Licensed Software or Licensed Product under
+-00012  * any End User Software License Agreement or Agreement for Licensed Product
+-00013  * with Synopsys or any supplement thereto. You are permitted to use and
+-00014  * redistribute this Software in source and binary forms, with or without
+-00015  * modification, provided that redistributions of source code must retain this
+-00016  * notice. You may not view, use, disclose, copy or distribute this file or
+-00017  * any information contained herein except pursuant to this license grant from
+-00018  * Synopsys. If you do not agree with this notice, including the disclaimer
+-00019  * below, then you are not authorized to use the Software.
+-00020  *
+-00021  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
+-00022  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+-00023  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+-00024  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
+-00025  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+-00026  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+-00027  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+-00028  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+-00029  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+-00030  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+-00031  * DAMAGE.
+-00032  * ========================================================================== */
+-00033 #ifndef DWC_HOST_ONLY
+-00034 
+-00035 #if !defined(__DWC_PCD_IF_H__)
+-00036 #define __DWC_PCD_IF_H__
+-00037 
+-00038 #include "dwc_os.h"
+-00039 #include "dwc_otg_core_if.h"
+-00040 
+-00045 struct dwc_otg_pcd;
+-00046 typedef struct dwc_otg_pcd dwc_otg_pcd_t;
+-00047 
+-00049 #define MAX_EP0_SIZE    64
+-00050 
+-00051 #define MAX_PACKET_SIZE 1024
+-00052 
+-00061 typedef int (*dwc_completion_cb_t) (dwc_otg_pcd_t * pcd, void *ep_handle,
+-00062                                     void *req_handle, int32_t status,
+-00063                                     uint32_t actual);
+-00071 typedef int (*dwc_isoc_completion_cb_t) (dwc_otg_pcd_t * pcd, void *ep_handle,
+-00072                                          void *req_handle, int proc_buf_num);
+-00081 typedef int (*dwc_setup_cb_t) (dwc_otg_pcd_t * pcd, uint8_t * bytes);
+-00086 typedef int (*dwc_disconnect_cb_t) (dwc_otg_pcd_t * pcd);
+-00088 typedef int (*dwc_connect_cb_t) (dwc_otg_pcd_t * pcd, int speed);
+-00090 typedef int (*dwc_suspend_cb_t) (dwc_otg_pcd_t * pcd);
+-00093 typedef int (*dwc_sleep_cb_t) (dwc_otg_pcd_t * pcd);
+-00096 typedef int (*dwc_resume_cb_t) (dwc_otg_pcd_t * pcd);
+-00100 typedef int (*dwc_hnp_params_changed_cb_t) (dwc_otg_pcd_t * pcd);
+-00102 typedef int (*dwc_reset_cb_t) (dwc_otg_pcd_t * pcd);
+-00103 
+-00104 typedef int (*cfi_setup_cb_t) (dwc_otg_pcd_t * pcd, void *ctrl_req_bytes);
+-00105 
+-00107 struct dwc_otg_pcd_function_ops {
+-00108         dwc_connect_cb_t connect;
+-00109         dwc_disconnect_cb_t disconnect;
+-00110         dwc_setup_cb_t setup;
+-00111         dwc_completion_cb_t complete;
+-00112         dwc_isoc_completion_cb_t isoc_complete;
+-00113         dwc_suspend_cb_t suspend;
+-00114         dwc_sleep_cb_t sleep;
+-00115         dwc_resume_cb_t resume;
+-00116         dwc_reset_cb_t reset;
+-00117         dwc_hnp_params_changed_cb_t hnp_changed;
+-00118         cfi_setup_cb_t cfi_setup;
+-00119 };
+-00130 extern dwc_otg_pcd_t *dwc_otg_pcd_init(dwc_otg_core_if_t * core_if);
+-00131 
+-00136 extern void dwc_otg_pcd_remove(dwc_otg_pcd_t * pcd);
+-00137 
+-00143 extern void dwc_otg_pcd_start(dwc_otg_pcd_t * pcd,
+-00144                               const struct dwc_otg_pcd_function_ops *fops);
+-00145 
+-00161 extern int dwc_otg_pcd_ep_enable(dwc_otg_pcd_t * pcd,
+-00162                                  const uint8_t * ep_desc, void *ep_handle);
+-00163 
+-00169 extern int dwc_otg_pcd_ep_disable(dwc_otg_pcd_t * pcd, void *ep_handle);
+-00170 
+-00189 extern int dwc_otg_pcd_ep_queue(dwc_otg_pcd_t * pcd, void *ep_handle,
+-00190                                 uint8_t * buf, dwc_dma_t dma_buf,
+-00191                                 uint32_t buflen, int zero, void *req_handle,
+-00192                                 int atomic_alloc);
+-00193 
+-00199 extern int dwc_otg_pcd_ep_dequeue(dwc_otg_pcd_t * pcd, void *ep_handle,
+-00200                                   void *req_handle);
+-00201 
+-00208 extern int dwc_otg_pcd_ep_halt(dwc_otg_pcd_t * pcd, void *ep_handle, int value);
+-00209 
+-00211 extern int32_t dwc_otg_pcd_handle_intr(dwc_otg_pcd_t * pcd);
+-00212 
+-00214 extern int dwc_otg_pcd_get_frame_number(dwc_otg_pcd_t * pcd);
+-00215 
+-00242 extern int dwc_otg_pcd_iso_ep_start(dwc_otg_pcd_t * pcd, void *ep_handle,
+-00243                                     uint8_t * buf0, uint8_t * buf1,
+-00244                                     dwc_dma_t dma0, dwc_dma_t dma1,
+-00245                                     int sync_frame, int dp_frame,
+-00246                                     int data_per_frame, int start_frame,
+-00247                                     int buf_proc_intrvl, void *req_handle,
+-00248                                     int atomic_alloc);
+-00249 
+-00259 int dwc_otg_pcd_iso_ep_stop(dwc_otg_pcd_t * pcd, void *ep_handle,
+-00260                             void *req_handle);
+-00261 
+-00273 extern void dwc_otg_pcd_get_iso_packet_params(dwc_otg_pcd_t * pcd,
+-00274                                               void *ep_handle,
+-00275                                               void *iso_req_handle, int packet,
+-00276                                               int *status, int *actual,
+-00277                                               int *offset);
+-00278 
+-00285 extern int dwc_otg_pcd_get_iso_packet_count(dwc_otg_pcd_t * pcd,
+-00286                                             void *ep_handle,
+-00287                                             void *iso_req_handle);
+-00288 
+-00293 extern int dwc_otg_pcd_wakeup(dwc_otg_pcd_t * pcd);
+-00294 
+-00296 extern int dwc_otg_pcd_is_lpm_enabled(dwc_otg_pcd_t * pcd);
+-00297 
+-00299 extern int dwc_otg_pcd_get_rmwkup_enable(dwc_otg_pcd_t * pcd);
+-00300 
+-00302 extern void dwc_otg_pcd_initiate_srp(dwc_otg_pcd_t * pcd);
+-00303 
+-00305 extern void dwc_otg_pcd_remote_wakeup(dwc_otg_pcd_t * pcd, int set);
+-00306 
+-00308 extern uint32_t dwc_otg_pcd_is_dualspeed(dwc_otg_pcd_t * pcd);
+-00309 
+-00311 extern uint32_t dwc_otg_pcd_is_otg(dwc_otg_pcd_t * pcd);
+-00312 
+-00314 extern uint32_t get_b_hnp_enable(dwc_otg_pcd_t * pcd);
+-00315 extern uint32_t get_a_hnp_support(dwc_otg_pcd_t * pcd);
+-00316 extern uint32_t get_a_alt_hnp_support(dwc_otg_pcd_t * pcd);
+-00317 
+-00320 extern uint8_t *cfiw_ep_alloc_buffer(dwc_otg_pcd_t * pcd, void *pep,
+-00321                                      dwc_dma_t * addr, size_t buflen,
+-00322                                      int flags);
+-00323 
+-00324 /******************************************************************************/
+-00325 
+-00328 #endif                          /* __DWC_PCD_IF_H__ */
+-00329 
+-00330 #endif                          /* DWC_HOST_ONLY */
+-
    Generated on Tue May 5 02:22:48 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++
    Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
    ++

    dwc_otg_pcd_if.h

    Go to the documentation of this file.
    00001 /* ==========================================================================
++00002  * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_pcd_if.h $
++00003  * $Revision: #11 $
++00004  * $Date: 2011/10/26 $
++00005  * $Change: 1873028 $
++00006  *
++00007  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
++00008  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
++00009  * otherwise expressly agreed to in writing between Synopsys and you.
++00010  *
++00011  * The Software IS NOT an item of Licensed Software or Licensed Product under
++00012  * any End User Software License Agreement or Agreement for Licensed Product
++00013  * with Synopsys or any supplement thereto. You are permitted to use and
++00014  * redistribute this Software in source and binary forms, with or without
++00015  * modification, provided that redistributions of source code must retain this
++00016  * notice. You may not view, use, disclose, copy or distribute this file or
++00017  * any information contained herein except pursuant to this license grant from
++00018  * Synopsys. If you do not agree with this notice, including the disclaimer
++00019  * below, then you are not authorized to use the Software.
++00020  *
++00021  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
++00022  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++00023  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++00024  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
++00025  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++00026  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
++00027  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
++00028  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
++00029  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
++00030  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
++00031  * DAMAGE.
++00032  * ========================================================================== */
++00033 #ifndef DWC_HOST_ONLY
++00034 
++00035 #if !defined(__DWC_PCD_IF_H__)
++00036 #define __DWC_PCD_IF_H__
++00037 
++00038 //#include "dwc_os.h"
++00039 #include "dwc_otg_core_if.h"
++00040 
++00045 struct dwc_otg_pcd;
++00046 typedef struct dwc_otg_pcd dwc_otg_pcd_t;
++00047 
++00049 #define MAX_EP0_SIZE    64
++00050 
++00051 #define MAX_PACKET_SIZE 1024
++00052 
++00061 typedef int (*dwc_completion_cb_t) (dwc_otg_pcd_t * pcd, void *ep_handle,
++00062                                     void *req_handle, int32_t status,
++00063                                     uint32_t actual);
++00071 typedef int (*dwc_isoc_completion_cb_t) (dwc_otg_pcd_t * pcd, void *ep_handle,
++00072                                          void *req_handle, int proc_buf_num);
++00081 typedef int (*dwc_setup_cb_t) (dwc_otg_pcd_t * pcd, uint8_t * bytes);
++00086 typedef int (*dwc_disconnect_cb_t) (dwc_otg_pcd_t * pcd);
++00088 typedef int (*dwc_connect_cb_t) (dwc_otg_pcd_t * pcd, int speed);
++00090 typedef int (*dwc_suspend_cb_t) (dwc_otg_pcd_t * pcd);
++00093 typedef int (*dwc_sleep_cb_t) (dwc_otg_pcd_t * pcd);
++00096 typedef int (*dwc_resume_cb_t) (dwc_otg_pcd_t * pcd);
++00100 typedef int (*dwc_hnp_params_changed_cb_t) (dwc_otg_pcd_t * pcd);
++00102 typedef int (*dwc_reset_cb_t) (dwc_otg_pcd_t * pcd);
++00103 
++00104 typedef int (*cfi_setup_cb_t) (dwc_otg_pcd_t * pcd, void *ctrl_req_bytes);
++00105 
++00112 typedef int (*xiso_completion_cb_t) (dwc_otg_pcd_t * pcd, void *ep_handle,
++00113                                      void *req_handle, int32_t status,
++00114                                      void *ereq_port);
++00116 struct dwc_otg_pcd_function_ops {
++00117         dwc_connect_cb_t connect;
++00118         dwc_disconnect_cb_t disconnect;
++00119         dwc_setup_cb_t setup;
++00120         dwc_completion_cb_t complete;
++00121         dwc_isoc_completion_cb_t isoc_complete;
++00122         dwc_suspend_cb_t suspend;
++00123         dwc_sleep_cb_t sleep;
++00124         dwc_resume_cb_t resume;
++00125         dwc_reset_cb_t reset;
++00126         dwc_hnp_params_changed_cb_t hnp_changed;
++00127         cfi_setup_cb_t cfi_setup;
++00128 #ifdef DWC_UTE_PER_IO
++00129         xiso_completion_cb_t xisoc_complete;
++00130 #endif
++00131 };
++00142 extern dwc_otg_pcd_t *dwc_otg_pcd_init(dwc_otg_core_if_t * core_if);
++00143 
++00148 extern void dwc_otg_pcd_remove(dwc_otg_pcd_t * pcd);
++00149 
++00155 extern void dwc_otg_pcd_start(dwc_otg_pcd_t * pcd,
++00156                               const struct dwc_otg_pcd_function_ops *fops);
++00157 
++00173 extern int dwc_otg_pcd_ep_enable(dwc_otg_pcd_t * pcd,
++00174                                  const uint8_t * ep_desc, void *usb_ep);
++00175 
++00181 extern int dwc_otg_pcd_ep_disable(dwc_otg_pcd_t * pcd, void *ep_handle);
++00182 
++00201 extern int dwc_otg_pcd_ep_queue(dwc_otg_pcd_t * pcd, void *ep_handle,
++00202                                 uint8_t * buf, dwc_dma_t dma_buf,
++00203                                 uint32_t buflen, int zero, void *req_handle,
++00204                                 int atomic_alloc);
++00205 #ifdef DWC_UTE_PER_IO
++00206 
++00211 extern int dwc_otg_pcd_xiso_ep_queue(dwc_otg_pcd_t * pcd, void *ep_handle,
++00212                                      uint8_t * buf, dwc_dma_t dma_buf,
++00213                                      uint32_t buflen, int zero,
++00214                                      void *req_handle, int atomic_alloc,
++00215                                      void *ereq_nonport);
++00216 
++00217 #endif
++00218 
++00224 extern int dwc_otg_pcd_ep_dequeue(dwc_otg_pcd_t * pcd, void *ep_handle,
++00225                                   void *req_handle);
++00226 
++00233 extern int dwc_otg_pcd_ep_halt(dwc_otg_pcd_t * pcd, void *ep_handle, int value);
++00234 
++00236 extern int32_t dwc_otg_pcd_handle_intr(dwc_otg_pcd_t * pcd);
++00237 
++00239 extern int dwc_otg_pcd_get_frame_number(dwc_otg_pcd_t * pcd);
++00240 
++00267 extern int dwc_otg_pcd_iso_ep_start(dwc_otg_pcd_t * pcd, void *ep_handle,
++00268                                     uint8_t * buf0, uint8_t * buf1,
++00269                                     dwc_dma_t dma0, dwc_dma_t dma1,
++00270                                     int sync_frame, int dp_frame,
++00271                                     int data_per_frame, int start_frame,
++00272                                     int buf_proc_intrvl, void *req_handle,
++00273                                     int atomic_alloc);
++00274 
++00284 int dwc_otg_pcd_iso_ep_stop(dwc_otg_pcd_t * pcd, void *ep_handle,
++00285                             void *req_handle);
++00286 
++00298 extern void dwc_otg_pcd_get_iso_packet_params(dwc_otg_pcd_t * pcd,
++00299                                               void *ep_handle,
++00300                                               void *iso_req_handle, int packet,
++00301                                               int *status, int *actual,
++00302                                               int *offset);
++00303 
++00310 extern int dwc_otg_pcd_get_iso_packet_count(dwc_otg_pcd_t * pcd,
++00311                                             void *ep_handle,
++00312                                             void *iso_req_handle);
++00313 
++00318 extern int dwc_otg_pcd_wakeup(dwc_otg_pcd_t * pcd);
++00319 
++00321 extern int dwc_otg_pcd_is_lpm_enabled(dwc_otg_pcd_t * pcd);
++00322 
++00324 extern int dwc_otg_pcd_get_rmwkup_enable(dwc_otg_pcd_t * pcd);
++00325 
++00327 extern void dwc_otg_pcd_initiate_srp(dwc_otg_pcd_t * pcd);
++00328 
++00330 extern void dwc_otg_pcd_remote_wakeup(dwc_otg_pcd_t * pcd, int set);
++00331 
++00333 extern void dwc_otg_pcd_disconnect_us(dwc_otg_pcd_t * pcd, int no_of_usecs);
++00335 extern uint32_t dwc_otg_pcd_is_dualspeed(dwc_otg_pcd_t * pcd);
++00336 
++00338 extern uint32_t dwc_otg_pcd_is_otg(dwc_otg_pcd_t * pcd);
++00339 
++00341 extern uint32_t get_b_hnp_enable(dwc_otg_pcd_t * pcd);
++00342 extern uint32_t get_a_hnp_support(dwc_otg_pcd_t * pcd);
++00343 extern uint32_t get_a_alt_hnp_support(dwc_otg_pcd_t * pcd);
++00344 
++00347 extern uint8_t *cfiw_ep_alloc_buffer(dwc_otg_pcd_t * pcd, void *pep,
++00348                                      dwc_dma_t * addr, size_t buflen,
++00349                                      int flags);
++00350 
++00351 /******************************************************************************/
++00352 
++00355 #endif                          /* __DWC_PCD_IF_H__ */
++00356 
++00357 #endif                          /* DWC_HOST_ONLY */
++
    Generated on Thu Oct 27 03:56:37 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
    ++doxygen 1.3.9.1
    + + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__pcd__if_8h.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/dwc__otg__pcd__if_8h.html 2013-07-26 19:31:21.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__pcd__if_8h.html 2013-07-26 19:34:42.000000000 +0000 +@@ -2,25 +2,12 @@ + + DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_pcd_if.h File Reference + +- + +- +-
    +-
    +-
    +-
    ++ ++
    Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
    +

    dwc_otg_pcd_if.h File Reference

    This file defines DWC_OTG PCD Core API. More... +

    +-#include "dwc_os.h"
    +-#include "dwc_otg_core_if.h"
    ++#include "dwc_otg_core_if.h"
    + +

    + Go to the source code of this file. +@@ -30,143 +17,148 @@ + + + +- ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + + +- ++ + + +- ++ + +- +- ++ ++ + + +- ++ + +- +- ++ ++ + + +- ++ ++ ++ + + +- ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + + +- ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + + +- ++ + + +- ++ + +- +- ++ ++ + + +- ++ ++ ++ ++ + + +- ++ + + +- ++ + + +- ++ + +- ++ + +- ++ + + + +- ++ + +- ++ + + +- ++ + + + +- ++ + +
     Function Driver Ops Data Structure. More...

    Function Driver Callbacks

    typedef int(*) dwc_completion_cb_t (dwc_otg_pcd_t *pcd, void *ep_handle, void *req_handle, int32_t status, uint32_t actual)
    typedef int(* dwc_completion_cb_t )(dwc_otg_pcd_t *pcd, void *ep_handle, void *req_handle, int32_t status, uint32_t actual)
     This function will be called whenever a previously queued request has completed.
    typedef int(*) dwc_isoc_completion_cb_t (dwc_otg_pcd_t *pcd, void *ep_handle, void *req_handle, int proc_buf_num)
     This function will be called whenever a previously queued request has completed.
    typedef int(* dwc_isoc_completion_cb_t )(dwc_otg_pcd_t *pcd, void *ep_handle, void *req_handle, int proc_buf_num)
     This function will be called whenever a previousle queued ISOC request has completed.
    typedef int(*) dwc_setup_cb_t (dwc_otg_pcd_t *pcd, uint8_t *bytes)
     This function will be called whenever a previousle queued ISOC request has completed.
    typedef int(* dwc_setup_cb_t )(dwc_otg_pcd_t *pcd, uint8_t *bytes)
     This function should handle any SETUP request that cannot be handled by the PCD Core.
    typedef int(*) dwc_disconnect_cb_t (dwc_otg_pcd_t *pcd)
     This function should handle any SETUP request that cannot be handled by the PCD Core.
    typedef int(* dwc_disconnect_cb_t )(dwc_otg_pcd_t *pcd)
     This is called whenever the device has been disconnected.
    +-typedef int(*) dwc_connect_cb_t (dwc_otg_pcd_t *pcd, int speed)
     This is called whenever the device has been disconnected.
    ++typedef int(* dwc_connect_cb_t )(dwc_otg_pcd_t *pcd, int speed)
     This function is called when device has been connected.
    +-typedef int(*) dwc_suspend_cb_t (dwc_otg_pcd_t *pcd)
    ++typedef int(* dwc_suspend_cb_t )(dwc_otg_pcd_t *pcd)
     This function is called when device has been suspended.
    typedef int(*) dwc_sleep_cb_t (dwc_otg_pcd_t *pcd)
    typedef int(* dwc_sleep_cb_t )(dwc_otg_pcd_t *pcd)
     This function is called when device has received LPM tokens, i.e.
    +-typedef int(*) dwc_resume_cb_t (dwc_otg_pcd_t *pcd)
     This function is called when device has received LPM tokens, i.e.
    ++typedef int(* dwc_resume_cb_t )(dwc_otg_pcd_t *pcd)
     This function is called when device has been resumed from suspend(L2) or L1 sleep state.
    typedef int(*) dwc_hnp_params_changed_cb_t (dwc_otg_pcd_t *pcd)
    typedef int(* dwc_hnp_params_changed_cb_t )(dwc_otg_pcd_t *pcd)
     This function is called whenever hnp params has been changed.
    +-typedef int(*) dwc_reset_cb_t (dwc_otg_pcd_t *pcd)
     This function is called whenever hnp params has been changed.
    ++typedef int(* dwc_reset_cb_t )(dwc_otg_pcd_t *pcd)
     This function is called whenever USB RESET is detected.
    +-typedef int(*) cfi_setup_cb_t (dwc_otg_pcd_t *pcd, void *ctrl_req_bytes)
    ++typedef int(* cfi_setup_cb_t )(dwc_otg_pcd_t *pcd, void *ctrl_req_bytes)
    typedef int(* xiso_completion_cb_t )(dwc_otg_pcd_t *pcd, void *ep_handle, void *req_handle, int32_t status, void *ereq_port)

    Function Driver Functions

    dwc_otg_pcd_t * dwc_otg_pcd_init (dwc_otg_core_if_t *core_if)
    dwc_otg_pcd_t * dwc_otg_pcd_init (dwc_otg_core_if_t *core_if)
     Call this function to get pointer on dwc_otg_pcd_t, this pointer will be used for all PCD API functions.
    void dwc_otg_pcd_remove (dwc_otg_pcd_t *pcd)
     Call this function to get pointer on dwc_otg_pcd_t, this pointer will be used for all PCD API functions.
    void dwc_otg_pcd_remove (dwc_otg_pcd_t *pcd)
     Frees PCD allocated by dwc_otg_pcd_init.
    void dwc_otg_pcd_start (dwc_otg_pcd_t *pcd, const struct dwc_otg_pcd_function_ops *fops)
     Frees PCD allocated by dwc_otg_pcd_init.
    void dwc_otg_pcd_start (dwc_otg_pcd_t *pcd, const struct dwc_otg_pcd_function_ops *fops)
     Call this to bind the function driver to the PCD Core.
    int dwc_otg_pcd_ep_enable (dwc_otg_pcd_t *pcd, const uint8_t *ep_desc, void *ep_handle)
     Call this to bind the function driver to the PCD Core.
    int dwc_otg_pcd_ep_enable (dwc_otg_pcd_t *pcd, const uint8_t *ep_desc, void *usb_ep)
     Enables an endpoint for use.
    int dwc_otg_pcd_ep_disable (dwc_otg_pcd_t *pcd, void *ep_handle)
     Enables an endpoint for use.
    int dwc_otg_pcd_ep_disable (dwc_otg_pcd_t *pcd, void *ep_handle)
     Disable the endpoint referenced by ep_handle.
    int dwc_otg_pcd_ep_queue (dwc_otg_pcd_t *pcd, void *ep_handle, uint8_t *buf, dwc_dma_t dma_buf, uint32_t buflen, int zero, void *req_handle, int atomic_alloc)
     Disable the endpoint referenced by ep_handle.
    int dwc_otg_pcd_ep_queue (dwc_otg_pcd_t *pcd, void *ep_handle, uint8_t *buf, dwc_dma_t dma_buf, uint32_t buflen, int zero, void *req_handle, int atomic_alloc)
     Queue a data transfer request on the endpoint referenced by ep_handle.
    int dwc_otg_pcd_ep_dequeue (dwc_otg_pcd_t *pcd, void *ep_handle, void *req_handle)
     Queue a data transfer request on the endpoint referenced by ep_handle.
    int dwc_otg_pcd_ep_dequeue (dwc_otg_pcd_t *pcd, void *ep_handle, void *req_handle)
     De-queue the specified data transfer that has not yet completed.
    int dwc_otg_pcd_ep_halt (dwc_otg_pcd_t *pcd, void *ep_handle, int value)
     De-queue the specified data transfer that has not yet completed.
    int dwc_otg_pcd_ep_halt (dwc_otg_pcd_t *pcd, void *ep_handle, int value)
     Halt (STALL) an endpoint or clear it.
    int32_t dwc_otg_pcd_handle_intr (dwc_otg_pcd_t *pcd)
     Halt (STALL) an endpoint or clear it.
    int32_t dwc_otg_pcd_handle_intr (dwc_otg_pcd_t *pcd)
     This function should be called on every hardware interrupt.
    +-int dwc_otg_pcd_get_frame_number (dwc_otg_pcd_t *pcd)
     This function should be called on every hardware interrupt.
    ++int dwc_otg_pcd_get_frame_number (dwc_otg_pcd_t *pcd)
     This function returns current frame number.
    int dwc_otg_pcd_iso_ep_start (dwc_otg_pcd_t *pcd, void *ep_handle, uint8_t *buf0, uint8_t *buf1, dwc_dma_t dma0, dwc_dma_t dma1, int sync_frame, int dp_frame, int data_per_frame, int start_frame, int buf_proc_intrvl, void *req_handle, int atomic_alloc)
    int dwc_otg_pcd_iso_ep_start (dwc_otg_pcd_t *pcd, void *ep_handle, uint8_t *buf0, uint8_t *buf1, dwc_dma_t dma0, dwc_dma_t dma1, int sync_frame, int dp_frame, int data_per_frame, int start_frame, int buf_proc_intrvl, void *req_handle, int atomic_alloc)
     Start isochronous transfers on the endpoint referenced by ep_handle.
    int dwc_otg_pcd_iso_ep_stop (dwc_otg_pcd_t *pcd, void *ep_handle, void *req_handle)
     Start isochronous transfers on the endpoint referenced by ep_handle.
    int dwc_otg_pcd_iso_ep_stop (dwc_otg_pcd_t *pcd, void *ep_handle, void *req_handle)
     Stop ISOC transfers on endpoint referenced by ep_handle.
    void dwc_otg_pcd_get_iso_packet_params (dwc_otg_pcd_t *pcd, void *ep_handle, void *iso_req_handle, int packet, int *status, int *actual, int *offset)
     Stop ISOC transfers on endpoint referenced by ep_handle.
    void dwc_otg_pcd_get_iso_packet_params (dwc_otg_pcd_t *pcd, void *ep_handle, void *iso_req_handle, int packet, int *status, int *actual, int *offset)
     Get ISOC packet status.
    int dwc_otg_pcd_get_iso_packet_count (dwc_otg_pcd_t *pcd, void *ep_handle, void *iso_req_handle)
     Get ISOC packet status.
    int dwc_otg_pcd_get_iso_packet_count (dwc_otg_pcd_t *pcd, void *ep_handle, void *iso_req_handle)
     Get ISOC packet count.
    int dwc_otg_pcd_wakeup (dwc_otg_pcd_t *pcd)
     Get ISOC packet count.
    int dwc_otg_pcd_wakeup (dwc_otg_pcd_t *pcd)
     This function starts the SRP Protocol if no session is in progress.
    +-int dwc_otg_pcd_is_lpm_enabled (dwc_otg_pcd_t *pcd)
     This function starts the SRP Protocol if no session is in progress.
    ++int dwc_otg_pcd_is_lpm_enabled (dwc_otg_pcd_t *pcd)
     This function returns 1 if LPM support is enabled, and 0 otherwise.
    +-int dwc_otg_pcd_get_rmwkup_enable (dwc_otg_pcd_t *pcd)
    ++int dwc_otg_pcd_get_rmwkup_enable (dwc_otg_pcd_t *pcd)
     This function returns 1 if remote wakeup is allowed and 0, otherwise.
    +-void dwc_otg_pcd_initiate_srp (dwc_otg_pcd_t *pcd)
    void dwc_otg_pcd_initiate_srp (dwc_otg_pcd_t *pcd)
     Initiate SRP.
    +-void dwc_otg_pcd_remote_wakeup (dwc_otg_pcd_t *pcd, int set)
     Initiate SRP.
    ++void dwc_otg_pcd_remote_wakeup (dwc_otg_pcd_t *pcd, int set)
     Starts remote wakeup signaling.
    +-uint32_t dwc_otg_pcd_is_dualspeed (dwc_otg_pcd_t *pcd)
    ++void dwc_otg_pcd_disconnect_us (dwc_otg_pcd_t *pcd, int no_of_usecs)
     Starts micorsecond soft disconnect.
    ++uint32_t dwc_otg_pcd_is_dualspeed (dwc_otg_pcd_t *pcd)
     This function returns whether device is dualspeed.
    +-uint32_t dwc_otg_pcd_is_otg (dwc_otg_pcd_t *pcd)
    ++uint32_t dwc_otg_pcd_is_otg (dwc_otg_pcd_t *pcd)
     This function returns whether device is otg.
    +-uint32_t get_b_hnp_enable (dwc_otg_pcd_t *pcd)
    ++uint32_t get_b_hnp_enable (dwc_otg_pcd_t *pcd)
     These functions allow to get hnp parameters.
    +-uint32_t get_a_hnp_support (dwc_otg_pcd_t *pcd)
    ++uint32_t get_a_hnp_support (dwc_otg_pcd_t *pcd)
    +-uint32_t get_a_alt_hnp_support (dwc_otg_pcd_t *pcd)
    ++uint32_t get_a_alt_hnp_support (dwc_otg_pcd_t *pcd)
    +-uint8_t * cfiw_ep_alloc_buffer (dwc_otg_pcd_t *pcd, void *pep, dwc_dma_t *addr, size_t buflen, int flags)
    ++uint8_t * cfiw_ep_alloc_buffer (dwc_otg_pcd_t *pcd, void *pep, dwc_dma_t *addr, size_t buflen, int flags)
     Allocate a cfi buffer.

    Defines

    +-#define __DWC_PCD_IF_H__
    ++#define __DWC_PCD_IF_H__
    +-#define MAX_EP0_SIZE   64
    ++#define MAX_EP0_SIZE   64
     Maxpacket size for EP0.
    +-#define MAX_PACKET_SIZE   1024
    ++#define MAX_PACKET_SIZE   1024
     Maxpacket size for any EP.

    Typedefs

    +-typedef dwc_otg_pcd dwc_otg_pcd_t
    ++typedef dwc_otg_pcd dwc_otg_pcd_t
    +

    Detailed Description

    +@@ -175,54 +167,78 @@ + +

    + Definition in file dwc_otg_pcd_if.h.

    Typedef Documentation

    +- +-
    +-
    +- ++

    ++

    ++ ++ ++ ++
    ++ + +- ++ + +
    typedef int(*) dwc_completion_cb_t(dwc_otg_pcd_t *pcd, void *ep_handle, void *req_handle, int32_t status, uint32_t actual) typedef int(* dwc_completion_cb_t)(dwc_otg_pcd_t *pcd, void *ep_handle, void *req_handle, int32_t status, uint32_t actual)
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + This function will be called whenever a previously queued request has completed. +

    + The status value will be set to -DWC_E_SHUTDOWN to indicated a failed or aborted transfer, or -DWC_E_RESTART to indicate the device was reset, or -DWC_E_TIMEOUT to indicate it timed out, or -DWC_E_INVALID to indicate invalid parameters. +

    +-Definition at line 61 of file dwc_otg_pcd_if.h. +- +-

    +- +-

    +-
    +- ++Definition at line 61 of file dwc_otg_pcd_if.h. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- ++ + +
    typedef int(*) dwc_isoc_completion_cb_t(dwc_otg_pcd_t *pcd, void *ep_handle, void *req_handle, int proc_buf_num) typedef int(* dwc_isoc_completion_cb_t)(dwc_otg_pcd_t *pcd, void *ep_handle, void *req_handle, int proc_buf_num)
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + This function will be called whenever a previousle queued ISOC request has completed. +

    + Count of ISOC packets could be read using dwc_otg_pcd_get_iso_packet_count function. The status of each ISOC packet could be read using dwc_otg_pcd_get_iso_packet_* functions. +

    +-Definition at line 71 of file dwc_otg_pcd_if.h. +- +-

    +- +-

    +-
    +- ++Definition at line 71 of file dwc_otg_pcd_if.h. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- ++ + +
    typedef int(*) dwc_setup_cb_t(dwc_otg_pcd_t *pcd, uint8_t *bytes) typedef int(* dwc_setup_cb_t)(dwc_otg_pcd_t *pcd, uint8_t *bytes)
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + This function should handle any SETUP request that cannot be handled by the PCD Core. +@@ -230,111 +246,177 @@ + This includes most GET_DESCRIPTORs, SET_CONFIGS, Any class-specific requests, etc. The function must non-blocking.

    + Returns 0 on success. Returns -DWC_E_NOT_SUPPORTED if the request is not supported. Returns -DWC_E_INVALID if the setup request had invalid parameters or bytes. Returns -DWC_E_SHUTDOWN on any other error. +

    +-Definition at line 81 of file dwc_otg_pcd_if.h. +- +-

    +- +-

    +-
    +- ++Definition at line 81 of file dwc_otg_pcd_if.h. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- ++ + +
    typedef int(*) dwc_disconnect_cb_t(dwc_otg_pcd_t *pcd) typedef int(* dwc_disconnect_cb_t)(dwc_otg_pcd_t *pcd)
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + This is called whenever the device has been disconnected. +

    + The function driver should take appropriate action to clean up all pending requests in the PCD Core, remove all endpoints (except ep0), and initialize back to reset state. +

    +-Definition at line 86 of file dwc_otg_pcd_if.h. +- +-

    +- +-

    +-
    +- ++Definition at line 86 of file dwc_otg_pcd_if.h. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- ++ + +
    typedef int(*) dwc_sleep_cb_t(dwc_otg_pcd_t *pcd) typedef int(* dwc_sleep_cb_t)(dwc_otg_pcd_t *pcd)
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + This function is called when device has received LPM tokens, i.e. +

    + device has been sent to sleep state. +

    +-Definition at line 93 of file dwc_otg_pcd_if.h. +- +-

    +- +-

    +-
    +- ++Definition at line 93 of file dwc_otg_pcd_if.h. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- ++ + +
    typedef int(*) dwc_hnp_params_changed_cb_t(dwc_otg_pcd_t *pcd) typedef int(* dwc_hnp_params_changed_cb_t)(dwc_otg_pcd_t *pcd)
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + This function is called whenever hnp params has been changed. +

    + User can call get_b_hnp_enable, get_a_hnp_support, get_a_alt_hnp_support functions to get hnp parameters. +

    +-Definition at line 100 of file dwc_otg_pcd_if.h. +- +-

    +-

    Function Documentation

    +- +-
    +-
    +- +- +- +- +- +- +- +- ++Definition at line 100 of file dwc_otg_pcd_if.h. ++ ++
    dwc_otg_pcd_t* dwc_otg_pcd_init (dwc_otg_core_if_t *  core_if  ) 
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ + +
    typedef int(* xiso_completion_cb_t)(dwc_otg_pcd_t *pcd, void *ep_handle, void *req_handle, int32_t status, void *ereq_port)
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    +-Call this function to get pointer on dwc_otg_pcd_t, this pointer will be used for all PCD API functions. +-

    +

    Parameters:
    + +- ++ ++ +
    core_if The DWC_OTG Core
    ep_handle Void pointer to the usb_ep structure
    ereq_port Pointer to the extended request structure created in the portable part.
    +
    + +

    +-Definition at line 1056 of file dwc_otg_pcd.c. +- +-

    +- +-

    +-
    +- +- +- +- +- +- +- +- ++Definition at line 112 of file dwc_otg_pcd_if.h. ++ ++
    void dwc_otg_pcd_remove (dwc_otg_pcd_t *  pcd  ) 
    ++

    Function Documentation

    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
    dwc_otg_pcd_t* dwc_otg_pcd_init ( dwc_otg_core_if_t *  core_if  ) 
    ++
    ++ ++ ++ ++ ++ ++
    ++   ++ ++ ++

    ++Call this function to get pointer on dwc_otg_pcd_t, this pointer will be used for all PCD API functions. ++

    ++Initialize xfer timeout timer. Implemented for 2.93a feature "Device DDMA OUT NAK Enhancement" ++

    ++Definition at line 1110 of file dwc_otg_pcd.c.

    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ + +
    void dwc_otg_pcd_remove ( dwc_otg_pcd_t *  pcd  ) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Frees PCD allocated by dwc_otg_pcd_init. +@@ -346,33 +428,41 @@ + + +

    +-Definition at line 1215 of file dwc_otg_pcd.c. +- +-

    +- +-

    +-
    +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- ++Definition at line 1309 of file dwc_otg_pcd.c. ++ ++
    void dwc_otg_pcd_start (dwc_otg_pcd_t *  pcd,
    const struct dwc_otg_pcd_function_ops *  fops 
    )
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ + +
    void dwc_otg_pcd_start ( dwc_otg_pcd_t *  pcd,
    const struct dwc_otg_pcd_function_ops *  fops
    ) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Call this to bind the function driver to the PCD Core. +@@ -385,39 +475,47 @@ + + +

    +-Definition at line 117 of file dwc_otg_pcd.c. +- +-

    +- +-

    +-
    +- ++Definition at line 119 of file dwc_otg_pcd.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    int dwc_otg_pcd_ep_enable (dwc_otg_pcd_t *  pcd, int dwc_otg_pcd_ep_enable ( dwc_otg_pcd_t *  pcd,
    const uint8_t *  ep_desc, const uint8_t *  ep_desc,
    void *  ep_handle void *  usb_ep
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Enables an endpoint for use. +@@ -428,225 +526,250 @@ + + + +- ++ +
    pcd The PCD
    ep_desc Endpoint descriptor
    ep_handle Handle on endpoint, that will be used to identify endpoint.
    usb_ep Handle on endpoint, that will be used to identify endpoint.
    + + +

    +-Definition at line 1341 of file dwc_otg_pcd.c. +- +-

    +- +-

    +-
    +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- ++Definition at line 1461 of file dwc_otg_pcd.c. ++ ++
    int dwc_otg_pcd_ep_disable (dwc_otg_pcd_t *  pcd,
    void *  ep_handle 
    )
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ + +
    int dwc_otg_pcd_ep_disable ( dwc_otg_pcd_t *  pcd,
    void *  ep_handle
    ) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Disable the endpoint referenced by ep_handle. +

    +-Returns -DWC_E_INVALID if invalid parameters were passed. Returns -DWC_E_SHUTDOWN if any other error ocurred. Returns 0 on success. ++Returns -DWC_E_INVALID if invalid parameters were passed. Returns -DWC_E_SHUTDOWN if any other error occurred. Returns 0 on success. +

    +-Definition at line 1449 of file dwc_otg_pcd.c. +- +-

    +- +-

    +-
    +- ++Definition at line 1622 of file dwc_otg_pcd.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    int dwc_otg_pcd_ep_queue (dwc_otg_pcd_t *  pcd, int dwc_otg_pcd_ep_queue ( dwc_otg_pcd_t *  pcd,
    void *  ep_handle, void *  ep_handle,
    uint8_t *  buf, uint8_t *  buf,
    dwc_dma_t  dma_buf, dwc_dma_t  dma_buf,
    uint32_t  buflen, uint32_t  buflen,
    int  zero, int  zero,
    void *  req_handle, void *  req_handle,
    int  atomic_alloc int  atomic_alloc
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Queue a data transfer request on the endpoint referenced by ep_handle. +

    +-After the transfer is completes, the complete callback will be called with the request status.

    +-

    Parameters:
    +- +- +- +- +- +- +- +- +- +-
    pcd The PCD
    ep_handle The handle of the endpoint
    buf The buffer for the data
    dma_buf The DMA buffer for the data
    buflen The length of the data transfer
    zero Specifies whether to send zero length last packet.
    req_handle Set this handle to any value to use to reference this request in the ep_dequeue function or from the complete callback
    atomic_alloc If driver need to perform atomic allocations for internal data structures.
    +-
    +-Returns -DWC_E_INVALID if invalid parameters were passed. Returns -DWC_E_SHUTDOWN if any other error ocurred. Returns 0 on success. +-

    +-

    Todo:
    NGS Create a function for this.
    ++
    Todo:
    NGS Create a function for this.
    + +

    +-Definition at line 1502 of file dwc_otg_pcd.c. +- +-

    +- +-

    +-
    +- ++Definition at line 2079 of file dwc_otg_pcd.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    int dwc_otg_pcd_ep_dequeue (dwc_otg_pcd_t *  pcd, int dwc_otg_pcd_ep_dequeue ( dwc_otg_pcd_t *  pcd,
    void *  ep_handle, void *  ep_handle,
    void *  req_handle void *  req_handle
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + De-queue the specified data transfer that has not yet completed. +

    + Returns -DWC_E_INVALID if invalid parameters were passed. Returns -DWC_E_SHUTDOWN if any other error ocurred. Returns 0 on success. +

    +-Definition at line 1694 of file dwc_otg_pcd.c. +- +-

    +- +-

    +-
    +- ++Definition at line 2306 of file dwc_otg_pcd.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    int dwc_otg_pcd_ep_halt (dwc_otg_pcd_t *  pcd, int dwc_otg_pcd_ep_halt ( dwc_otg_pcd_t *  pcd,
    void *  ep_handle, void *  ep_handle,
    int  value int  value
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Halt (STALL) an endpoint or clear it. +

    + Returns -DWC_E_INVALID if invalid parameters were passed. Returns -DWC_E_SHUTDOWN if any other error ocurred. Returns -DWC_E_AGAIN if the STALL cannot be sent and must be tried again later Returns 0 on success. +

    +-Definition at line 1733 of file dwc_otg_pcd.c. +- +-

    +- +-

    +-
    +- +- +- +- +- +- +- +- ++Definition at line 2345 of file dwc_otg_pcd.c. ++ ++
    int32_t dwc_otg_pcd_handle_intr (dwc_otg_pcd_t *  pcd  ) 
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ + +
    int32_t dwc_otg_pcd_handle_intr ( dwc_otg_pcd_t *  pcd  ) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + This function should be called on every hardware interrupt. +@@ -654,161 +777,157 @@ + The PCD handles the device interrupts. Many conditions can cause a device interrupt. When an interrupt occurs, the device interrupt service routine determines the cause of the interrupt and dispatches handling to the appropriate function. These interrupt handling functions are described below.

    + All interrupt registers are processed from LSB to MSB. +

    +-Definition at line 3971 of file dwc_otg_pcd_intr.c. +- +-

    +- +-

    +-
    +- ++Definition at line 4702 of file dwc_otg_pcd_intr.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    int dwc_otg_pcd_iso_ep_start (dwc_otg_pcd_t *  pcd, int dwc_otg_pcd_iso_ep_start ( dwc_otg_pcd_t *  pcd,
    void *  ep_handle, void *  ep_handle,
    uint8_t *  buf0, uint8_t *  buf0,
    uint8_t *  buf1, uint8_t *  buf1,
    dwc_dma_t  dma0, dwc_dma_t  dma0,
    dwc_dma_t  dma1, dwc_dma_t  dma1,
    int  sync_frame, int  sync_frame,
    int  dp_frame, int  dp_frame,
    int  data_per_frame, int  data_per_frame,
    int  start_frame, int  start_frame,
    int  buf_proc_intrvl, int  buf_proc_intrvl,
    void *  req_handle, void *  req_handle,
    int  atomic_alloc int  atomic_alloc
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Start isochronous transfers on the endpoint referenced by ep_handle. +

    +-For isochronous transfers duble buffering is used. After processing each of buffers comlete callback will be called with status for each transaction.

    +-

    Parameters:
    +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
    pcd The PCD
    ep_handle The handle of the endpoint
    buf0 The virtual address of first data buffer
    buf1 The virtual address of second data buffer
    dma0 The DMA address of first data buffer
    dma1 The DMA address of second data buffer
    sync_frame Data pattern frame number
    dp_frame Data size for pattern frame
    data_per_frame Data size for regular frame
    start_frame Frame number to start transfers, if -1 then start transfers ASAP.
    buf_proc_intrvl Interval of ISOC Buffer processing
    req_handle Handle of ISOC request
    atomic_alloc Specefies whether to perform atomic allocation for internal data structures.
    +-
    +-Returns -DWC_E_NO_MEMORY if there is no enough memory. Returns -DWC_E_INVALID if incorrect arguments are passed to the function. Returns -DW_E_SHUTDOWN for any other error. Returns 0 on success +-

    +

    Todo:
      +-
    • pattern data support is to be implemented in the future
    ++
  • pattern data support is to be implemented in the future
    • +
    + +

    +-Definition at line 685 of file dwc_otg_pcd.c. +- +-

    +- +-

    +-
    +- ++Definition at line 708 of file dwc_otg_pcd.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    int dwc_otg_pcd_iso_ep_stop (dwc_otg_pcd_t *  pcd, int dwc_otg_pcd_iso_ep_stop ( dwc_otg_pcd_t *  pcd,
    void *  ep_handle, void *  ep_handle,
    void *  req_handle void *  req_handle
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Stop ISOC transfers on endpoint referenced by ep_handle. +@@ -822,63 +941,71 @@ + + Returns -DWC_E_INVALID if incorrect arguments are passed to the function Returns 0 on success +

    +-Definition at line 794 of file dwc_otg_pcd.c. +- +-

    +- +-

    +-
    +- ++Definition at line 817 of file dwc_otg_pcd.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    void dwc_otg_pcd_get_iso_packet_params (dwc_otg_pcd_t *  pcd, void dwc_otg_pcd_get_iso_packet_params ( dwc_otg_pcd_t *  pcd,
    void *  ep_handle, void *  ep_handle,
    void *  iso_req_handle, void *  iso_req_handle,
    int  packet, int  packet,
    int *  status, int *  status,
    int *  actual, int *  actual,
    int *  offset int *  offset
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Get ISOC packet status. +@@ -896,39 +1023,47 @@ + + +

    +-Definition at line 862 of file dwc_otg_pcd.c. +- +-

    +- +-

    +-
    +- ++Definition at line 889 of file dwc_otg_pcd.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    int dwc_otg_pcd_get_iso_packet_count (dwc_otg_pcd_t *  pcd, int dwc_otg_pcd_get_iso_packet_count ( dwc_otg_pcd_t *  pcd,
    void *  ep_handle, void *  ep_handle,
    void *  iso_req_handle void *  iso_req_handle
    )) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Get ISOC packet count. +@@ -942,35 +1077,80 @@ + + +

    +-Definition at line 850 of file dwc_otg_pcd.c. +- +-

    +- +-

    +-
    +- +- +- +- +- +- +- +- ++Definition at line 873 of file dwc_otg_pcd.c. ++ ++
    int dwc_otg_pcd_wakeup (dwc_otg_pcd_t *  pcd  ) 
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ + +
    int dwc_otg_pcd_wakeup ( dwc_otg_pcd_t *  pcd  ) 
    +- +-
    ++
    ++ ++ ++ ++ ++ ++
    ++   ++ + +

    + This function starts the SRP Protocol if no session is in progress. +

    + If a session is already in progress, but the device is suspended, remote wakeup signaling is started. +

    +-Definition at line 1896 of file dwc_otg_pcd.c. +- +-

    +-

    Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++Definition at line 2559 of file dwc_otg_pcd.c.
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
    void dwc_otg_pcd_initiate_srp ( dwc_otg_pcd_t *  pcd  ) 
    ++
    ++ ++ ++ ++ ++ ++
    ++   ++ ++ ++

    ++Initiate SRP. ++

    ++

    Parameters:
    ++ ++ ++
    pcd the pcd structure.
    ++
    ++ ++

    ++Definition at line 2596 of file dwc_otg_pcd.c.

    ++

    Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
    ++doxygen 1.3.9.1 + + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__pcd__intr_8c-source.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/dwc__otg__pcd__intr_8c-source.html 2013-07-26 19:31:21.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__pcd__intr_8c-source.html 2013-07-26 19:34:42.000000000 +0000 +@@ -2,3628 +2,4337 @@ + + DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_pcd_intr.c Source File + +- + +- +-
    +-
    +-
    +-
    +-

    dwc_otg_pcd_intr.c

    Go to the documentation of this file.
    00001 /* ==========================================================================
+-00002  * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_pcd_intr.c $
+-00003  * $Revision: #93 $
+-00004  * $Date: 2009/04/02 $
+-00005  * $Change: 1224216 $
+-00006  *
+-00007  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
+-00008  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
+-00009  * otherwise expressly agreed to in writing between Synopsys and you.
+-00010  *
+-00011  * The Software IS NOT an item of Licensed Software or Licensed Product under
+-00012  * any End User Software License Agreement or Agreement for Licensed Product
+-00013  * with Synopsys or any supplement thereto. You are permitted to use and
+-00014  * redistribute this Software in source and binary forms, with or without
+-00015  * modification, provided that redistributions of source code must retain this
+-00016  * notice. You may not view, use, disclose, copy or distribute this file or
+-00017  * any information contained herein except pursuant to this license grant from
+-00018  * Synopsys. If you do not agree with this notice, including the disclaimer
+-00019  * below, then you are not authorized to use the Software.
+-00020  *
+-00021  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
+-00022  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+-00023  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+-00024  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
+-00025  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+-00026  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+-00027  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+-00028  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+-00029  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+-00030  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+-00031  * DAMAGE.
+-00032  * ========================================================================== */
+-00033 #ifndef DWC_HOST_ONLY
+-00034 
+-00035 #include "dwc_otg_pcd.h"
+-00036 
+-00037 #ifdef DWC_UTE_CFI
+-00038 #include "dwc_otg_cfi.h"
+-00039 #endif
+-00040 
+-00041 //#define PRINT_CFI_DMA_DESCS
+-00042 
+-00043 #define DEBUG_EP0
+-00044 
+-00048 static void dwc_otg_pcd_update_otg(dwc_otg_pcd_t * pcd, const unsigned reset)
+-00049 {
+-00050 
+-00051         if (reset) {
+-00052                 pcd->b_hnp_enable = 0;
+-00053                 pcd->a_hnp_support = 0;
+-00054                 pcd->a_alt_hnp_support = 0;
+-00055         }
+-00056 
+-00057         if (pcd->fops->hnp_changed) {
+-00058                 pcd->fops->hnp_changed(pcd);
+-00059         }
+-00060 }
+-00061 
+-00076 static inline void print_ep0_state(dwc_otg_pcd_t * pcd)
+-00077 {
+-00078 #ifdef DEBUG
+-00079         char str[40];
+-00080 
+-00081         switch (pcd->ep0state) {
+-00082         case EP0_DISCONNECT:
+-00083                 dwc_strcpy(str, "EP0_DISCONNECT");
+-00084                 break;
+-00085         case EP0_IDLE:
+-00086                 dwc_strcpy(str, "EP0_IDLE");
+-00087                 break;
+-00088         case EP0_IN_DATA_PHASE:
+-00089                 dwc_strcpy(str, "EP0_IN_DATA_PHASE");
+-00090                 break;
+-00091         case EP0_OUT_DATA_PHASE:
+-00092                 dwc_strcpy(str, "EP0_OUT_DATA_PHASE");
+-00093                 break;
+-00094         case EP0_IN_STATUS_PHASE:
+-00095                 dwc_strcpy(str, "EP0_IN_STATUS_PHASE");
+-00096                 break;
+-00097         case EP0_OUT_STATUS_PHASE:
+-00098                 dwc_strcpy(str, "EP0_OUT_STATUS_PHASE");
+-00099                 break;
+-00100         case EP0_STALL:
+-00101                 dwc_strcpy(str, "EP0_STALL");
+-00102                 break;
+-00103         default:
+-00104                 dwc_strcpy(str, "EP0_INVALID");
+-00105         }
+-00106 
+-00107         DWC_DEBUGPL(DBG_ANY, "%s(%d)\n", str, pcd->ep0state);
+-00108 #endif
+-00109 }
+-00110 
+-00111 #ifdef DWC_UTE_CFI
+-00112 static inline void print_desc(struct dwc_otg_dma_desc *ddesc,
+-00113                               const uint8_t * epname, int descnum)
+-00114 {
+-00115         CFI_INFO
+-00116             ("%s DMA_DESC(%d) buf=0x%08x bytes=0x%04x; sp=0x%x; l=0x%x; sts=0x%02x; bs=0x%02x\n",
+-00117              epname, descnum, ddesc->buf, ddesc->status.b.bytes,
+-00118              ddesc->status.b.sp, ddesc->status.b.l, ddesc->status.b.sts,
+-00119              ddesc->status.b.bs);
+-00120 }
+-00121 #endif
+-00122 
+-00126 static inline dwc_otg_pcd_ep_t *get_in_ep(dwc_otg_pcd_t * pcd, uint32_t ep_num)
+-00127 {
+-00128         int i;
+-00129         int num_in_eps = GET_CORE_IF(pcd)->dev_if->num_in_eps;
+-00130         if (ep_num == 0) {
+-00131                 return &pcd->ep0;
+-00132         } else {
+-00133                 for (i = 0; i < num_in_eps; ++i) {
+-00134                         if (pcd->in_ep[i].dwc_ep.num == ep_num)
+-00135                                 return &pcd->in_ep[i];
+-00136                 }
+-00137                 return 0;
+-00138         }
+-00139 }
+-00140 
+-00144 static inline dwc_otg_pcd_ep_t *get_out_ep(dwc_otg_pcd_t * pcd, uint32_t ep_num)
+-00145 {
+-00146         int i;
+-00147         int num_out_eps = GET_CORE_IF(pcd)->dev_if->num_out_eps;
+-00148         if (ep_num == 0) {
+-00149                 return &pcd->ep0;
+-00150         } else {
+-00151                 for (i = 0; i < num_out_eps; ++i) {
+-00152                         if (pcd->out_ep[i].dwc_ep.num == ep_num)
+-00153                                 return &pcd->out_ep[i];
+-00154                 }
+-00155                 return 0;
+-00156         }
+-00157 }
+-00158 
+-00163 dwc_otg_pcd_ep_t *get_ep_by_addr(dwc_otg_pcd_t * pcd, u16 wIndex)
+-00164 {
+-00165         dwc_otg_pcd_ep_t *ep;
+-00166         uint32_t ep_num = UE_GET_ADDR(wIndex);
+-00167 
+-00168         if (ep_num == 0) {
+-00169                 ep = &pcd->ep0;
+-00170         } else if (UE_GET_DIR(wIndex) == UE_DIR_IN) {   /* in ep */
+-00171                 ep = &pcd->in_ep[ep_num - 1];
+-00172         } else {
+-00173                 ep = &pcd->out_ep[ep_num - 1];
+-00174         }
+-00175 
+-00176         return ep;
+-00177 }
+-00178 
+-00183 void start_next_request(dwc_otg_pcd_ep_t * ep)
+-00184 {
+-00185         dwc_otg_pcd_request_t *req = 0;
+-00186         uint32_t max_transfer =
+-00187             GET_CORE_IF(ep->pcd)->core_params->max_transfer_size;
+-00188 
+-00189 #ifdef DWC_UTE_CFI
+-00190         struct dwc_otg_pcd *pcd;
+-00191         pcd = ep->pcd;
+-00192 #endif
+-00193 
+-00194         if (!DWC_CIRCLEQ_EMPTY(&ep->queue)) {
+-00195                 req = DWC_CIRCLEQ_FIRST(&ep->queue);
+-00196 
+-00197 #ifdef DWC_UTE_CFI
+-00198                 if (ep->dwc_ep.buff_mode != BM_STANDARD) {
+-00199                         ep->dwc_ep.cfi_req_len = req->length;
+-00200                         pcd->cfi->ops.build_descriptors(pcd->cfi, pcd, ep, req);
+-00201                 } else {
+-00202 #endif
+-00203                 /* Setup and start the Transfer */
+-00204                 ep->dwc_ep.dma_addr = req->dma;
+-00205                 ep->dwc_ep.start_xfer_buff = req->buf;
+-00206                 ep->dwc_ep.xfer_buff = req->buf;
+-00207                 ep->dwc_ep.sent_zlp = 0;
+-00208                 ep->dwc_ep.total_len = req->length;
+-00209                 ep->dwc_ep.xfer_len = 0;
+-00210                 ep->dwc_ep.xfer_count = 0;
+-00211 
+-00212                 ep->dwc_ep.maxxfer = max_transfer;
+-00213                 if (GET_CORE_IF(ep->pcd)->dma_desc_enable) {
+-00214                         uint32_t out_max_xfer = DDMA_MAX_TRANSFER_SIZE
+-00215                             - (DDMA_MAX_TRANSFER_SIZE % 4);
+-00216                         if (ep->dwc_ep.is_in) {
+-00217                                         if (ep->dwc_ep.maxxfer >
+-00218                                             DDMA_MAX_TRANSFER_SIZE) {
+-00219                                         ep->dwc_ep.maxxfer =
+-00220                                             DDMA_MAX_TRANSFER_SIZE;
+-00221                                 }
+-00222                         } else {
+-00223                                 if (ep->dwc_ep.maxxfer > out_max_xfer) {
+-00224                                                 ep->dwc_ep.maxxfer =
+-00225                                                     out_max_xfer;
+-00226                                 }
+-00227                         }
+-00228                 }
+-00229                 if (ep->dwc_ep.maxxfer < ep->dwc_ep.total_len) {
+-00230                         ep->dwc_ep.maxxfer -=
+-00231                             (ep->dwc_ep.maxxfer % ep->dwc_ep.maxpacket);
+-00232                 }
+-00233                 if (req->sent_zlp) {
+-00234                                 if ((ep->dwc_ep.total_len %
+-00235                                      ep->dwc_ep.maxpacket == 0)
+-00236                                     && (ep->dwc_ep.total_len != 0)) {
+-00237                                 ep->dwc_ep.sent_zlp = 1;
+-00238                         }
+-00239 
+-00240                 }
+-00241 #ifdef DWC_UTE_CFI
+-00242                 }
+-00243 #endif
+-00244                 dwc_otg_ep_start_transfer(GET_CORE_IF(ep->pcd), &ep->dwc_ep);
+-00245         }
+-00246 }
+-00247 
+-00252 int32_t dwc_otg_pcd_handle_sof_intr(dwc_otg_pcd_t * pcd)
+-00253 {
+-00254         dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
+-00255 
+-00256         gintsts_data_t gintsts;
+-00257 
+-00258         DWC_DEBUGPL(DBG_PCD, "SOF\n");
+-00259 
+-00260         /* Clear interrupt */
+-00261         gintsts.d32 = 0;
+-00262         gintsts.b.sofintr = 1;
+-00263         dwc_write_reg32(&core_if->core_global_regs->gintsts, gintsts.d32);
+-00264 
+-00265         return 1;
+-00266 }
+-00267 
+-00285 int32_t dwc_otg_pcd_handle_rx_status_q_level_intr(dwc_otg_pcd_t * pcd)
+-00286 {
+-00287         dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
+-00288         dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
+-00289         gintmsk_data_t gintmask = {.d32 = 0 };
+-00290         device_grxsts_data_t status;
+-00291         dwc_otg_pcd_ep_t *ep;
+-00292         gintsts_data_t gintsts;
+-00293 #ifdef DEBUG
+-00294         static char *dpid_str[] = { "D0", "D2", "D1", "MDATA" };
+-00295 #endif
+-00296 
+-00297         //DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, _pcd);
+-00298         /* Disable the Rx Status Queue Level interrupt */
+-00299         gintmask.b.rxstsqlvl = 1;
+-00300         dwc_modify_reg32(&global_regs->gintmsk, gintmask.d32, 0);
+-00301 
+-00302         /* Get the Status from the top of the FIFO */
+-00303         status.d32 = dwc_read_reg32(&global_regs->grxstsp);
+-00304 
+-00305         DWC_DEBUGPL(DBG_PCD, "EP:%d BCnt:%d DPID:%s "
+-00306                     "pktsts:%x Frame:%d(0x%0x)\n",
+-00307                     status.b.epnum, status.b.bcnt,
+-00308                     dpid_str[status.b.dpid],
+-00309                     status.b.pktsts, status.b.fn, status.b.fn);
+-00310         /* Get pointer to EP structure */
+-00311         ep = get_out_ep(pcd, status.b.epnum);
+-00312 
+-00313         switch (status.b.pktsts) {
+-00314         case DWC_DSTS_GOUT_NAK:
+-00315                 DWC_DEBUGPL(DBG_PCDV, "Global OUT NAK\n");
+-00316                 break;
+-00317         case DWC_STS_DATA_UPDT:
+-00318                 DWC_DEBUGPL(DBG_PCDV, "OUT Data Packet\n");
+-00319                 if (status.b.bcnt && ep->dwc_ep.xfer_buff) {
+-00321                         dwc_otg_read_packet(core_if,
+-00322                                             ep->dwc_ep.xfer_buff,
+-00323                                             status.b.bcnt);
+-00324                         ep->dwc_ep.xfer_count += status.b.bcnt;
+-00325                         ep->dwc_ep.xfer_buff += status.b.bcnt;
+-00326                 }
+-00327                 break;
+-00328         case DWC_STS_XFER_COMP:
+-00329                 DWC_DEBUGPL(DBG_PCDV, "OUT Complete\n");
+-00330                 break;
+-00331         case DWC_DSTS_SETUP_COMP:
+-00332 #ifdef DEBUG_EP0
+-00333                 DWC_DEBUGPL(DBG_PCDV, "Setup Complete\n");
+-00334 #endif
+-00335                 break;
+-00336         case DWC_DSTS_SETUP_UPDT:
+-00337                 dwc_otg_read_setup_packet(core_if, pcd->setup_pkt->d32);
+-00338 #ifdef DEBUG_EP0
+-00339                 DWC_DEBUGPL(DBG_PCD,
+-00340                             "SETUP PKT: %02x.%02x v%04x i%04x l%04x\n",
+-00341                             pcd->setup_pkt->req.bmRequestType,
+-00342                             pcd->setup_pkt->req.bRequest,
+-00343                             UGETW(pcd->setup_pkt->req.wValue),
+-00344                             UGETW(pcd->setup_pkt->req.wIndex),
+-00345                             UGETW(pcd->setup_pkt->req.wLength));
+-00346 #endif
+-00347                 ep->dwc_ep.xfer_count += status.b.bcnt;
+-00348                 break;
+-00349         default:
+-00350                 DWC_DEBUGPL(DBG_PCDV, "Invalid Packet Status (0x%0x)\n",
+-00351                             status.b.pktsts);
+-00352                 break;
+-00353         }
+-00354 
+-00355         /* Enable the Rx Status Queue Level interrupt */
+-00356         dwc_modify_reg32(&global_regs->gintmsk, 0, gintmask.d32);
+-00357         /* Clear interrupt */
+-00358         gintsts.d32 = 0;
+-00359         gintsts.b.rxstsqlvl = 1;
+-00360         dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
+-00361 
+-00362         //DWC_DEBUGPL(DBG_PCDV, "EXIT: %s\n", __func__);
+-00363         return 1;
+-00364 }
+-00365 
+-00378 static inline int get_ep_of_last_in_token(dwc_otg_core_if_t * core_if)
+-00379 {
+-00380         dwc_otg_device_global_regs_t *dev_global_regs =
+-00381             core_if->dev_if->dev_global_regs;
+-00382         const uint32_t TOKEN_Q_DEPTH = core_if->hwcfg2.b.dev_token_q_depth;
+-00383         /* Number of Token Queue Registers */
+-00384         const int DTKNQ_REG_CNT = (TOKEN_Q_DEPTH + 7) / 8;
+-00385         dtknq1_data_t dtknqr1;
+-00386         uint32_t in_tkn_epnums[4];
+-00387         int ndx = 0;
+-00388         int i = 0;
+-00389         volatile uint32_t *addr = &dev_global_regs->dtknqr1;
+-00390         int epnum = 0;
+-00391 
+-00392         //DWC_DEBUGPL(DBG_PCD,"dev_token_q_depth=%d\n",TOKEN_Q_DEPTH);
+-00393 
+-00394         /* Read the DTKNQ Registers */
+-00395         for (i = 0; i < DTKNQ_REG_CNT; i++) {
+-00396                 in_tkn_epnums[i] = dwc_read_reg32(addr);
+-00397                 DWC_DEBUGPL(DBG_PCDV, "DTKNQR%d=0x%08x\n", i + 1,
+-00398                             in_tkn_epnums[i]);
+-00399                 if (addr == &dev_global_regs->dvbusdis) {
+-00400                         addr = &dev_global_regs->dtknqr3_dthrctl;
+-00401                 } else {
+-00402                         ++addr;
+-00403                 }
+-00404 
+-00405         }
+-00406 
+-00407         /* Copy the DTKNQR1 data to the bit field. */
+-00408         dtknqr1.d32 = in_tkn_epnums[0];
+-00409         /* Get the EP numbers */
+-00410         in_tkn_epnums[0] = dtknqr1.b.epnums0_5;
+-00411         ndx = dtknqr1.b.intknwptr - 1;
+-00412 
+-00413         //DWC_DEBUGPL(DBG_PCDV,"ndx=%d\n",ndx);
+-00414         if (ndx == -1) {
+-00417                 int cnt = TOKEN_Q_DEPTH;
+-00418                 if (TOKEN_Q_DEPTH <= 6) {
+-00419                         cnt = TOKEN_Q_DEPTH - 1;
+-00420                 } else if (TOKEN_Q_DEPTH <= 14) {
+-00421                         cnt = TOKEN_Q_DEPTH - 7;
+-00422                 } else if (TOKEN_Q_DEPTH <= 22) {
+-00423                         cnt = TOKEN_Q_DEPTH - 15;
+-00424                 } else {
+-00425                         cnt = TOKEN_Q_DEPTH - 23;
+-00426                 }
+-00427                 epnum = (in_tkn_epnums[DTKNQ_REG_CNT - 1] >> (cnt * 4)) & 0xF;
+-00428         } else {
+-00429                 if (ndx <= 5) {
+-00430                         epnum = (in_tkn_epnums[0] >> (ndx * 4)) & 0xF;
+-00431                 } else if (ndx <= 13) {
+-00432                         ndx -= 6;
+-00433                         epnum = (in_tkn_epnums[1] >> (ndx * 4)) & 0xF;
+-00434                 } else if (ndx <= 21) {
+-00435                         ndx -= 14;
+-00436                         epnum = (in_tkn_epnums[2] >> (ndx * 4)) & 0xF;
+-00437                 } else if (ndx <= 29) {
+-00438                         ndx -= 22;
+-00439                         epnum = (in_tkn_epnums[3] >> (ndx * 4)) & 0xF;
+-00440                 }
+-00441         }
+-00442         //DWC_DEBUGPL(DBG_PCD,"epnum=%d\n",epnum);
+-00443         return epnum;
+-00444 }
+-00445 
+-00451 int32_t dwc_otg_pcd_handle_np_tx_fifo_empty_intr(dwc_otg_pcd_t * pcd)
+-00452 {
+-00453         dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
+-00454         dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
+-00455         dwc_otg_dev_in_ep_regs_t *ep_regs;
+-00456         gnptxsts_data_t txstatus = {.d32 = 0 };
+-00457         gintsts_data_t gintsts;
+-00458 
+-00459         int epnum = 0;
+-00460         dwc_otg_pcd_ep_t *ep = 0;
+-00461         uint32_t len = 0;
+-00462         int dwords;
+-00463 
+-00464         /* Get the epnum from the IN Token Learning Queue. */
+-00465         epnum = get_ep_of_last_in_token(core_if);
+-00466         ep = get_in_ep(pcd, epnum);
+-00467 
+-00468         DWC_DEBUGPL(DBG_PCD, "NP TxFifo Empty: %d \n", epnum);
+-00469 
+-00470         ep_regs = core_if->dev_if->in_ep_regs[epnum];
+-00471 
+-00472         len = ep->dwc_ep.xfer_len - ep->dwc_ep.xfer_count;
+-00473         if (len > ep->dwc_ep.maxpacket) {
+-00474                 len = ep->dwc_ep.maxpacket;
+-00475         }
+-00476         dwords = (len + 3) / 4;
+-00477 
+-00478         /* While there is space in the queue and space in the FIFO and
+-00479          * More data to tranfer, Write packets to the Tx FIFO */
+-00480         txstatus.d32 = dwc_read_reg32(&global_regs->gnptxsts);
+-00481         DWC_DEBUGPL(DBG_PCDV, "b4 GNPTXSTS=0x%08x\n", txstatus.d32);
+-00482 
+-00483         while (txstatus.b.nptxqspcavail > 0 &&
+-00484                txstatus.b.nptxfspcavail > dwords &&
+-00485                ep->dwc_ep.xfer_count < ep->dwc_ep.xfer_len) {
+-00486                 /* Write the FIFO */
+-00487                 dwc_otg_ep_write_packet(core_if, &ep->dwc_ep, 0);
+-00488                 len = ep->dwc_ep.xfer_len - ep->dwc_ep.xfer_count;
+-00489 
+-00490                 if (len > ep->dwc_ep.maxpacket) {
+-00491                         len = ep->dwc_ep.maxpacket;
+-00492                 }
+-00493 
+-00494                 dwords = (len + 3) / 4;
+-00495                 txstatus.d32 = dwc_read_reg32(&global_regs->gnptxsts);
+-00496                 DWC_DEBUGPL(DBG_PCDV, "GNPTXSTS=0x%08x\n", txstatus.d32);
+-00497         }
+-00498 
+-00499         DWC_DEBUGPL(DBG_PCDV, "GNPTXSTS=0x%08x\n",
+-00500                     dwc_read_reg32(&global_regs->gnptxsts));
+-00501 
+-00502         /* Clear interrupt */
+-00503         gintsts.d32 = 0;
+-00504         gintsts.b.nptxfempty = 1;
+-00505         dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
+-00506 
+-00507         return 1;
+-00508 }
+-00509 
+-00515 static int32_t write_empty_tx_fifo(dwc_otg_pcd_t * pcd, uint32_t epnum)
+-00516 {
+-00517         dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
+-00518         dwc_otg_dev_if_t *dev_if = core_if->dev_if;
+-00519         dwc_otg_dev_in_ep_regs_t *ep_regs;
+-00520         dtxfsts_data_t txstatus = {.d32 = 0 };
+-00521         dwc_otg_pcd_ep_t *ep = 0;
+-00522         uint32_t len = 0;
+-00523         int dwords;
+-00524 
+-00525         ep = get_in_ep(pcd, epnum);
+-00526 
+-00527         DWC_DEBUGPL(DBG_PCD, "Dedicated TxFifo Empty: %d \n", epnum);
+-00528 
+-00529         ep_regs = core_if->dev_if->in_ep_regs[epnum];
+-00530 
+-00531         len = ep->dwc_ep.xfer_len - ep->dwc_ep.xfer_count;
+-00532 
+-00533         if (len > ep->dwc_ep.maxpacket) {
+-00534                 len = ep->dwc_ep.maxpacket;
+-00535         }
+-00536 
+-00537         dwords = (len + 3) / 4;
+-00538 
+-00539         /* While there is space in the queue and space in the FIFO and
+-00540          * More data to tranfer, Write packets to the Tx FIFO */
+-00541         txstatus.d32 = dwc_read_reg32(&dev_if->in_ep_regs[epnum]->dtxfsts);
+-00542         DWC_DEBUGPL(DBG_PCDV, "b4 dtxfsts[%d]=0x%08x\n", epnum, txstatus.d32);
+-00543 
+-00544         while (txstatus.b.txfspcavail > dwords &&
+-00545                ep->dwc_ep.xfer_count < ep->dwc_ep.xfer_len &&
+-00546                ep->dwc_ep.xfer_len != 0) {
+-00547                 /* Write the FIFO */
+-00548                 dwc_otg_ep_write_packet(core_if, &ep->dwc_ep, 0);
+-00549 
+-00550                 len = ep->dwc_ep.xfer_len - ep->dwc_ep.xfer_count;
+-00551                 if (len > ep->dwc_ep.maxpacket) {
+-00552                         len = ep->dwc_ep.maxpacket;
+-00553                 }
+-00554 
+-00555                 dwords = (len + 3) / 4;
+-00556                 txstatus.d32 =
+-00557                     dwc_read_reg32(&dev_if->in_ep_regs[epnum]->dtxfsts);
+-00558                 DWC_DEBUGPL(DBG_PCDV, "dtxfsts[%d]=0x%08x\n", epnum,
+-00559                             txstatus.d32);
+-00560         }
+-00561 
+-00562         DWC_DEBUGPL(DBG_PCDV, "b4 dtxfsts[%d]=0x%08x\n", epnum,
+-00563                     dwc_read_reg32(&dev_if->in_ep_regs[epnum]->dtxfsts));
+-00564 
+-00565         return 1;
+-00566 }
+-00567 
+-00573 void dwc_otg_pcd_stop(dwc_otg_pcd_t * pcd)
+-00574 {
+-00575         int i, num_in_eps, num_out_eps;
+-00576         dwc_otg_pcd_ep_t *ep;
+-00577 
+-00578         gintmsk_data_t intr_mask = {.d32 = 0 };
+-00579 
+-00580         DWC_SPINLOCK(pcd->lock);
+-00581 
+-00582         num_in_eps = GET_CORE_IF(pcd)->dev_if->num_in_eps;
+-00583         num_out_eps = GET_CORE_IF(pcd)->dev_if->num_out_eps;
+-00584 
+-00585         DWC_DEBUGPL(DBG_PCDV, "%s() \n", __func__);
+-00586         /* don't disconnect drivers more than once */
+-00587         if (pcd->ep0state == EP0_DISCONNECT) {
+-00588                 DWC_DEBUGPL(DBG_ANY, "%s() Already Disconnected\n", __func__);
+-00589                 return;
+-00590         }
+-00591         pcd->ep0state = EP0_DISCONNECT;
+-00592 
+-00593         /* Reset the OTG state. */
+-00594         dwc_otg_pcd_update_otg(pcd, 1);
+-00595 
+-00596         /* Disable the NP Tx Fifo Empty Interrupt. */
+-00597         intr_mask.b.nptxfempty = 1;
+-00598         dwc_modify_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk,
+-00599                          intr_mask.d32, 0);
+-00600 
+-00601         /* Flush the FIFOs */
+-00603         dwc_otg_flush_tx_fifo(GET_CORE_IF(pcd), 0x10);
+-00604         dwc_otg_flush_rx_fifo(GET_CORE_IF(pcd));
+-00605 
+-00606         /* prevent new request submissions, kill any outstanding requests  */
+-00607         ep = &pcd->ep0;
+-00608         dwc_otg_request_nuke(ep);
+-00609         /* prevent new request submissions, kill any outstanding requests  */
+-00610         for (i = 0; i < num_in_eps; i++) {
+-00611                 dwc_otg_pcd_ep_t *ep = &pcd->in_ep[i];
+-00612                 dwc_otg_request_nuke(ep);
+-00613         }
+-00614         /* prevent new request submissions, kill any outstanding requests  */
+-00615         for (i = 0; i < num_out_eps; i++) {
+-00616                 dwc_otg_pcd_ep_t *ep = &pcd->out_ep[i];
+-00617                 dwc_otg_request_nuke(ep);
+-00618         }
+-00619 
+-00620         /* report disconnect; the driver is already quiesced */
+-00621         if (pcd->fops->disconnect) {
+-00622                 DWC_SPINUNLOCK(pcd->lock);
+-00623                 pcd->fops->disconnect(pcd);
+-00624                 DWC_SPINLOCK(pcd->lock);
+-00625         }
+-00626         DWC_SPINUNLOCK(pcd->lock);
+-00627 }
+-00628 
+-00632 int32_t dwc_otg_pcd_handle_i2c_intr(dwc_otg_pcd_t * pcd)
+-00633 {
+-00634         gintmsk_data_t intr_mask = {.d32 = 0 };
+-00635         gintsts_data_t gintsts;
+-00636 
+-00637         DWC_PRINTF("INTERRUPT Handler not implemented for %s\n", "i2cintr");
+-00638         intr_mask.b.i2cintr = 1;
+-00639         dwc_modify_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk,
+-00640                          intr_mask.d32, 0);
+-00641 
+-00642         /* Clear interrupt */
+-00643         gintsts.d32 = 0;
+-00644         gintsts.b.i2cintr = 1;
+-00645         dwc_write_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
+-00646                         gintsts.d32);
+-00647         return 1;
+-00648 }
+-00649 
+-00653 int32_t dwc_otg_pcd_handle_early_suspend_intr(dwc_otg_pcd_t * pcd)
+-00654 {
+-00655         gintsts_data_t gintsts;
+-00656 #if defined(VERBOSE)
+-00657         DWC_PRINTF("Early Suspend Detected\n");
+-00658 #endif
+-00659         /* Clear interrupt */
+-00660         gintsts.d32 = 0;
+-00661         gintsts.b.erlysuspend = 1;
+-00662         dwc_write_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
+-00663                         gintsts.d32);
+-00664         return 1;
+-00665 }
+-00666 
+-00684 static inline void ep0_out_start(dwc_otg_core_if_t * core_if,
+-00685                                  dwc_otg_pcd_t * pcd)
+-00686 {
+-00687         dwc_otg_dev_if_t *dev_if = core_if->dev_if;
+-00688         deptsiz0_data_t doeptsize0 = {.d32 = 0 };
+-00689         dwc_otg_dev_dma_desc_t *dma_desc;
+-00690         depctl_data_t doepctl = {.d32 = 0 };
+-00691 
+-00692 #ifdef VERBOSE
+-00693         DWC_DEBUGPL(DBG_PCDV, "%s() doepctl0=%0x\n", __func__,
+-00694                     dwc_read_reg32(&dev_if->out_ep_regs[0]->doepctl));
+-00695 #endif
+-00696 
+-00697         doeptsize0.b.supcnt = 3;
+-00698         doeptsize0.b.pktcnt = 1;
+-00699         doeptsize0.b.xfersize = 8 * 3;
+-00700 
+-00701         if (core_if->dma_enable) {
+-00702                 if (!core_if->dma_desc_enable) {
+-00704                         dwc_write_reg32(&dev_if->out_ep_regs[0]->doeptsiz,
+-00705                                         doeptsize0.d32);
+-00706 
+-00708                         dwc_write_reg32(&dev_if->out_ep_regs[0]->doepdma,
+-00709                                         pcd->setup_pkt_dma_handle);
+-00710                 } else {
+-00711                         dev_if->setup_desc_index =
+-00712                             (dev_if->setup_desc_index + 1) & 1;
+-00713                         dma_desc =
+-00714                             dev_if->setup_desc_addr[dev_if->setup_desc_index];
+-00715 
+-00717                         dma_desc->status.b.bs = BS_HOST_BUSY;
+-00718                         dma_desc->status.b.l = 1;
+-00719                         dma_desc->status.b.ioc = 1;
+-00720                         dma_desc->status.b.bytes = pcd->ep0.dwc_ep.maxpacket;
+-00721                         dma_desc->buf = pcd->setup_pkt_dma_handle;
+-00722                         dma_desc->status.b.bs = BS_HOST_READY;
+-00723 
+-00725                         dwc_write_reg32(&dev_if->out_ep_regs[0]->doepdma,
+-00726                                         dev_if->dma_setup_desc_addr[dev_if->
+-00727                                                                     setup_desc_index]);
+-00728                 }
+-00729 
+-00730         } else {
+-00732                 dwc_write_reg32(&dev_if->out_ep_regs[0]->doeptsiz,
+-00733                                 doeptsize0.d32);
+-00734         }
+-00735 
+-00737         doepctl.b.epena = 1;
+-00738         doepctl.b.cnak = 1;
+-00739         dwc_write_reg32(&dev_if->out_ep_regs[0]->doepctl, doepctl.d32);
+-00740 
+-00741 #ifdef VERBOSE
+-00742         DWC_DEBUGPL(DBG_PCDV, "doepctl0=%0x\n",
+-00743                     dwc_read_reg32(&dev_if->out_ep_regs[0]->doepctl));
+-00744         DWC_DEBUGPL(DBG_PCDV, "diepctl0=%0x\n",
+-00745                     dwc_read_reg32(&dev_if->in_ep_regs[0]->diepctl));
+-00746 #endif
+-00747 }
+-00748 
+-00772 int32_t dwc_otg_pcd_handle_usb_reset_intr(dwc_otg_pcd_t * pcd)
+-00773 {
+-00774         dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
+-00775         dwc_otg_dev_if_t *dev_if = core_if->dev_if;
+-00776         depctl_data_t doepctl = {.d32 = 0 };
+-00777         daint_data_t daintmsk = {.d32 = 0 };
+-00778         doepmsk_data_t doepmsk = {.d32 = 0 };
+-00779         diepmsk_data_t diepmsk = {.d32 = 0 };
+-00780         dcfg_data_t dcfg = {.d32 = 0 };
+-00781         grstctl_t resetctl = {.d32 = 0 };
+-00782         dctl_data_t dctl = {.d32 = 0 };
+-00783         int i = 0;
+-00784         gintsts_data_t gintsts;
+-00785         pcgcctl_data_t power = {.d32 = 0 };
+-00786 
+-00787         power.d32 = dwc_read_reg32(core_if->pcgcctl);
+-00788         if (power.b.stoppclk) {
+-00789                 power.d32 = 0;
+-00790                 power.b.stoppclk = 1;
+-00791                 dwc_modify_reg32(core_if->pcgcctl, power.d32, 0);
+-00792 
+-00793                 power.b.pwrclmp = 1;
+-00794                 dwc_modify_reg32(core_if->pcgcctl, power.d32, 0);
+-00795 
+-00796                 power.b.rstpdwnmodule = 1;
+-00797                 dwc_modify_reg32(core_if->pcgcctl, power.d32, 0);
+-00798         }
+-00799 
+-00800         core_if->lx_state = DWC_OTG_L0;
+-00801 
+-00802         DWC_PRINTF("USB RESET\n");
+-00803 #ifdef DWC_EN_ISOC
+-00804         for (i = 1; i < 16; ++i) {
+-00805                 dwc_otg_pcd_ep_t *ep;
+-00806                 dwc_ep_t *dwc_ep;
+-00807                 ep = get_in_ep(pcd, i);
+-00808                 if (ep != 0) {
+-00809                         dwc_ep = &ep->dwc_ep;
+-00810                         dwc_ep->next_frame = 0xffffffff;
+-00811                 }
+-00812         }
+-00813 #endif                          /* DWC_EN_ISOC */
+-00814 
+-00815         /* reset the HNP settings */
+-00816         dwc_otg_pcd_update_otg(pcd, 1);
+-00817 
+-00818         /* Clear the Remote Wakeup Signalling */
+-00819         dctl.b.rmtwkupsig = 1;
+-00820         dwc_modify_reg32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32, 0);
+-00821 
+-00822         /* Set NAK for all OUT EPs */
+-00823         doepctl.b.snak = 1;
+-00824         for (i = 0; i <= dev_if->num_out_eps; i++) {
+-00825                 dwc_write_reg32(&dev_if->out_ep_regs[i]->doepctl, doepctl.d32);
+-00826         }
+-00827 
+-00828         /* Flush the NP Tx FIFO */
+-00829         dwc_otg_flush_tx_fifo(core_if, 0x10);
+-00830         /* Flush the Learning Queue */
+-00831         resetctl.b.intknqflsh = 1;
+-00832         dwc_write_reg32(&core_if->core_global_regs->grstctl, resetctl.d32);
+-00833 
+-00834         if (core_if->multiproc_int_enable) {
+-00835                 daintmsk.b.inep0 = 1;
+-00836                 daintmsk.b.outep0 = 1;
+-00837                 dwc_write_reg32(&dev_if->dev_global_regs->deachintmsk,
+-00838                                 daintmsk.d32);
+-00839 
+-00840                 doepmsk.b.setup = 1;
+-00841                 doepmsk.b.xfercompl = 1;
+-00842                 doepmsk.b.ahberr = 1;
+-00843                 doepmsk.b.epdisabled = 1;
+-00844 
+-00845                 if (core_if->dma_desc_enable) {
+-00846                         doepmsk.b.stsphsercvd = 1;
+-00847                         doepmsk.b.bna = 1;
+-00848                 }
+-00849 /*              
+-00850                 doepmsk.b.babble = 1;
+-00851                 doepmsk.b.nyet = 1;
+-00852                 
+-00853                 if(core_if->dma_enable) {
+-00854                         doepmsk.b.nak = 1;
+-00855                 }
+-00856 */
+-00857                 dwc_write_reg32(&dev_if->dev_global_regs->doepeachintmsk[0],
+-00858                                 doepmsk.d32);
+-00859 
+-00860                 diepmsk.b.xfercompl = 1;
+-00861                 diepmsk.b.timeout = 1;
+-00862                 diepmsk.b.epdisabled = 1;
+-00863                 diepmsk.b.ahberr = 1;
+-00864                 diepmsk.b.intknepmis = 1;
+-00865 
+-00866                 if (core_if->dma_desc_enable) {
+-00867                         diepmsk.b.bna = 1;
+-00868                 }
+-00869 /*              
+-00870                 if(core_if->dma_enable) {
+-00871                         diepmsk.b.nak = 1;
+-00872                 }
+-00873 */
+-00874                 dwc_write_reg32(&dev_if->dev_global_regs->diepeachintmsk[0],
+-00875                                 diepmsk.d32);
+-00876         } else {
+-00877                 daintmsk.b.inep0 = 1;
+-00878                 daintmsk.b.outep0 = 1;
+-00879                 dwc_write_reg32(&dev_if->dev_global_regs->daintmsk,
+-00880                                 daintmsk.d32);
+-00881 
+-00882                 doepmsk.b.setup = 1;
+-00883                 doepmsk.b.xfercompl = 1;
+-00884                 doepmsk.b.ahberr = 1;
+-00885                 doepmsk.b.epdisabled = 1;
+-00886 
+-00887                 if (core_if->dma_desc_enable) {
+-00888                         doepmsk.b.stsphsercvd = 1;
+-00889                         doepmsk.b.bna = 1;
+-00890                 }
+-00891                 dwc_write_reg32(&dev_if->dev_global_regs->doepmsk, doepmsk.d32);
+-00892 
+-00893                 diepmsk.b.xfercompl = 1;
+-00894                 diepmsk.b.timeout = 1;
+-00895                 diepmsk.b.epdisabled = 1;
+-00896                 diepmsk.b.ahberr = 1;
+-00897                 diepmsk.b.intknepmis = 1;
+-00898 
+-00899                 if (core_if->dma_desc_enable) {
+-00900                         diepmsk.b.bna = 1;
+-00901                 }
+-00902 
+-00903                 dwc_write_reg32(&dev_if->dev_global_regs->diepmsk, diepmsk.d32);
+-00904         }
+-00905 
+-00906         /* Reset Device Address */
+-00907         dcfg.d32 = dwc_read_reg32(&dev_if->dev_global_regs->dcfg);
+-00908         dcfg.b.devaddr = 0;
+-00909         dwc_write_reg32(&dev_if->dev_global_regs->dcfg, dcfg.d32);
+-00910 
+-00911         /* setup EP0 to receive SETUP packets */
+-00912         ep0_out_start(core_if, pcd);
+-00913 
+-00914         /* Clear interrupt */
+-00915         gintsts.d32 = 0;
+-00916         gintsts.b.usbreset = 1;
+-00917         dwc_write_reg32(&core_if->core_global_regs->gintsts, gintsts.d32);
+-00918 
+-00919         return 1;
+-00920 }
+-00921 
+-00928 static int get_device_speed(dwc_otg_core_if_t * core_if)
+-00929 {
+-00930         dsts_data_t dsts;
+-00931         int speed = 0;
+-00932         dsts.d32 = dwc_read_reg32(&core_if->dev_if->dev_global_regs->dsts);
+-00933 
+-00934         switch (dsts.b.enumspd) {
+-00935         case DWC_DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ:
+-00936                 speed = USB_SPEED_HIGH;
+-00937                 break;
+-00938         case DWC_DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ:
+-00939         case DWC_DSTS_ENUMSPD_FS_PHY_48MHZ:
+-00940                 speed = USB_SPEED_FULL;
+-00941                 break;
+-00942 
+-00943         case DWC_DSTS_ENUMSPD_LS_PHY_6MHZ:
+-00944                 speed = USB_SPEED_LOW;
+-00945                 break;
+-00946         }
+-00947 
+-00948         return speed;
+-00949 }
+-00950 
+-00956 int32_t dwc_otg_pcd_handle_enum_done_intr(dwc_otg_pcd_t * pcd)
+-00957 {
+-00958         dwc_otg_pcd_ep_t *ep0 = &pcd->ep0;
+-00959         gintsts_data_t gintsts;
+-00960         gusbcfg_data_t gusbcfg;
+-00961         dwc_otg_core_global_regs_t *global_regs =
+-00962             GET_CORE_IF(pcd)->core_global_regs;
+-00963         uint8_t utmi16b, utmi8b;
+-00964         int speed;
+-00965         DWC_DEBUGPL(DBG_PCD, "SPEED ENUM\n");
+-00966 
+-00967         if (GET_CORE_IF(pcd)->snpsid >= OTG_CORE_REV_2_60a) {
+-00968                 utmi16b = 6;
+-00969                 utmi8b = 9;
+-00970         } else {
+-00971                 utmi16b = 4;
+-00972                 utmi8b = 8;
+-00973         }
+-00974         dwc_otg_ep0_activate(GET_CORE_IF(pcd), &ep0->dwc_ep);
+-00975 
+-00976 #ifdef DEBUG_EP0
+-00977         print_ep0_state(pcd);
+-00978 #endif
+-00979 
+-00980         if (pcd->ep0state == EP0_DISCONNECT) {
+-00981                 pcd->ep0state = EP0_IDLE;
+-00982         } else if (pcd->ep0state == EP0_STALL) {
+-00983                 pcd->ep0state = EP0_IDLE;
+-00984         }
+-00985 
+-00986         pcd->ep0state = EP0_IDLE;
+-00987 
+-00988         ep0->stopped = 0;
+-00989 
+-00990         speed = get_device_speed(GET_CORE_IF(pcd));
+-00991         pcd->fops->connect(pcd, speed);
+-00992 
+-00993         /* Set USB turnaround time based on device speed and PHY interface. */
+-00994         gusbcfg.d32 = dwc_read_reg32(&global_regs->gusbcfg);
+-00995         if (speed == USB_SPEED_HIGH) {
+-00996                 if (GET_CORE_IF(pcd)->hwcfg2.b.hs_phy_type ==
+-00997                     DWC_HWCFG2_HS_PHY_TYPE_ULPI) {
+-00998                         /* ULPI interface */
+-00999                         gusbcfg.b.usbtrdtim = 9;
+-01000                 }
+-01001                 if (GET_CORE_IF(pcd)->hwcfg2.b.hs_phy_type ==
+-01002                     DWC_HWCFG2_HS_PHY_TYPE_UTMI) {
+-01003                         /* UTMI+ interface */
+-01004                         if (GET_CORE_IF(pcd)->hwcfg4.b.utmi_phy_data_width == 0) {
+-01005                                 gusbcfg.b.usbtrdtim = utmi8b;
+-01006                         } else if (GET_CORE_IF(pcd)->hwcfg4.b.
+-01007                                    utmi_phy_data_width == 1) {
+-01008                                 gusbcfg.b.usbtrdtim = utmi16b;
+-01009                         } else if (GET_CORE_IF(pcd)->core_params->
+-01010                                    phy_utmi_width == 8) {
+-01011                                 gusbcfg.b.usbtrdtim = utmi8b;
+-01012                         } else {
+-01013                                 gusbcfg.b.usbtrdtim = utmi16b;
+-01014                         }
+-01015                 }
+-01016                 if (GET_CORE_IF(pcd)->hwcfg2.b.hs_phy_type ==
+-01017                     DWC_HWCFG2_HS_PHY_TYPE_UTMI_ULPI) {
+-01018                         /* UTMI+  OR  ULPI interface */
+-01019                         if (gusbcfg.b.ulpi_utmi_sel == 1) {
+-01020                                 /* ULPI interface */
+-01021                                 gusbcfg.b.usbtrdtim = 9;
+-01022                         } else {
+-01023                                 /* UTMI+ interface */
+-01024                                 if (GET_CORE_IF(pcd)->core_params->
+-01025                                     phy_utmi_width == 16) {
+-01026                                         gusbcfg.b.usbtrdtim = utmi16b;
+-01027                                 } else {
+-01028                                         gusbcfg.b.usbtrdtim = utmi8b;
+-01029                                 }
+-01030                         }
+-01031                 }
+-01032         } else {
+-01033                 /* Full or low speed */
+-01034                 gusbcfg.b.usbtrdtim = 9;
+-01035         }
+-01036         dwc_write_reg32(&global_regs->gusbcfg, gusbcfg.d32);
+-01037 
+-01038         /* Clear interrupt */
+-01039         gintsts.d32 = 0;
+-01040         gintsts.b.enumdone = 1;
+-01041         dwc_write_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
+-01042                         gintsts.d32);
+-01043         return 1;
+-01044 }
+-01045 
+-01051 int32_t dwc_otg_pcd_handle_isoc_out_packet_dropped_intr(dwc_otg_pcd_t * pcd)
+-01052 {
+-01053         gintmsk_data_t intr_mask = {.d32 = 0 };
+-01054         gintsts_data_t gintsts;
+-01055 
+-01056         DWC_PRINTF("INTERRUPT Handler not implemented for %s\n",
+-01057                    "ISOC Out Dropped");
+-01058 
+-01059         intr_mask.b.isooutdrop = 1;
+-01060         dwc_modify_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk,
+-01061                          intr_mask.d32, 0);
+-01062 
+-01063         /* Clear interrupt */
+-01064         gintsts.d32 = 0;
+-01065         gintsts.b.isooutdrop = 1;
+-01066         dwc_write_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
+-01067                         gintsts.d32);
+-01068 
+-01069         return 1;
+-01070 }
+-01071 
+-01077 int32_t dwc_otg_pcd_handle_end_periodic_frame_intr(dwc_otg_pcd_t * pcd)
+-01078 {
+-01079         gintmsk_data_t intr_mask = {.d32 = 0 };
+-01080         gintsts_data_t gintsts;
+-01081         DWC_PRINTF("INTERRUPT Handler not implemented for %s\n", "EOP");
+-01082 
+-01083         intr_mask.b.eopframe = 1;
+-01084         dwc_modify_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk,
+-01085                          intr_mask.d32, 0);
+-01086 
+-01087         /* Clear interrupt */
+-01088         gintsts.d32 = 0;
+-01089         gintsts.b.eopframe = 1;
+-01090         dwc_write_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
+-01091                         gintsts.d32);
+-01092 
+-01093         return 1;
+-01094 }
+-01095 
+-01105 int32_t dwc_otg_pcd_handle_ep_mismatch_intr(dwc_otg_core_if_t * core_if)
+-01106 {
+-01107         gintsts_data_t gintsts;
+-01108         DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, core_if);
+-01109 
+-01110         /* Clear interrupt */
+-01111         gintsts.d32 = 0;
+-01112         gintsts.b.epmismatch = 1;
+-01113         dwc_write_reg32(&core_if->core_global_regs->gintsts, gintsts.d32);
+-01114 
+-01115         return 1;
+-01116 }
+-01117 
+-01121 static inline void ep0_do_stall(dwc_otg_pcd_t * pcd, const int err_val)
+-01122 {
+-01123         dwc_otg_pcd_ep_t *ep0 = &pcd->ep0;
+-01124         usb_device_request_t *ctrl = &pcd->setup_pkt->req;
+-01125         DWC_WARN("req %02x.%02x protocol STALL; err %d\n",
+-01126                  ctrl->bmRequestType, ctrl->bRequest, err_val);
+-01127 
+-01128         ep0->dwc_ep.is_in = 1;
+-01129         dwc_otg_ep_set_stall(GET_CORE_IF(pcd), &ep0->dwc_ep);
+-01130         pcd->ep0.stopped = 1;
+-01131         pcd->ep0state = EP0_IDLE;
+-01132         ep0_out_start(GET_CORE_IF(pcd), pcd);
+-01133 }
+-01134 
+-01138 static inline void do_gadget_setup(dwc_otg_pcd_t * pcd,
+-01139                                    usb_device_request_t * ctrl)
+-01140 {
+-01141         int ret = 0;
+-01142         DWC_SPINUNLOCK(pcd->lock);
+-01143         ret = pcd->fops->setup(pcd, (uint8_t *) ctrl);
+-01144         DWC_SPINLOCK(pcd->lock);
+-01145         if (ret < 0) {
+-01146                 ep0_do_stall(pcd, ret);
+-01147         }
+-01148 
+-01161         if (ret == 256 + 999) {
+-01162                 pcd->request_config = 1;
+-01163         }
+-01164 }
+-01165 
+-01166 #ifdef DWC_UTE_CFI
+-01167 
+-01171 static inline int cfi_gadget_setup(dwc_otg_pcd_t * pcd,
+-01172                                    struct cfi_usb_ctrlrequest *ctrl_req)
+-01173 {
+-01174         int ret = 0;
+-01175 
+-01176         if (pcd->fops && pcd->fops->cfi_setup) {
+-01177                 DWC_SPINUNLOCK(pcd->lock);
+-01178                 ret = pcd->fops->cfi_setup(pcd, ctrl_req);
+-01179                 DWC_SPINLOCK(pcd->lock);
+-01180                 if (ret < 0) {
+-01181                         ep0_do_stall(pcd, ret);
+-01182                         return ret;
+-01183                 }
+-01184         }
+-01185 
+-01186         return ret;
+-01187 }
+-01188 #endif
+-01189 
+-01194 static inline void do_setup_in_status_phase(dwc_otg_pcd_t * pcd)
+-01195 {
+-01196         dwc_otg_pcd_ep_t *ep0 = &pcd->ep0;
+-01197         if (pcd->ep0state == EP0_STALL) {
+-01198                 return;
+-01199         }
+-01200 
+-01201         pcd->ep0state = EP0_IN_STATUS_PHASE;
+-01202 
+-01203         /* Prepare for more SETUP Packets */
+-01204         DWC_DEBUGPL(DBG_PCD, "EP0 IN ZLP\n");
+-01205         ep0->dwc_ep.xfer_len = 0;
+-01206         ep0->dwc_ep.xfer_count = 0;
+-01207         ep0->dwc_ep.is_in = 1;
+-01208         ep0->dwc_ep.dma_addr = pcd->setup_pkt_dma_handle;
+-01209         dwc_otg_ep0_start_transfer(GET_CORE_IF(pcd), &ep0->dwc_ep);
+-01210 
+-01211         /* Prepare for more SETUP Packets */
+-01212         //ep0_out_start(GET_CORE_IF(pcd), pcd);
+-01213 }
+-01214 
+-01219 static inline void do_setup_out_status_phase(dwc_otg_pcd_t * pcd)
+-01220 {
+-01221         dwc_otg_pcd_ep_t *ep0 = &pcd->ep0;
+-01222         if (pcd->ep0state == EP0_STALL) {
+-01223                 DWC_DEBUGPL(DBG_PCD, "EP0 STALLED\n");
+-01224                 return;
+-01225         }
+-01226         pcd->ep0state = EP0_OUT_STATUS_PHASE;
+-01227 
+-01228         DWC_DEBUGPL(DBG_PCD, "EP0 OUT ZLP\n");
+-01229         ep0->dwc_ep.xfer_len = 0;
+-01230         ep0->dwc_ep.xfer_count = 0;
+-01231         ep0->dwc_ep.is_in = 0;
+-01232         ep0->dwc_ep.dma_addr = pcd->setup_pkt_dma_handle;
+-01233         dwc_otg_ep0_start_transfer(GET_CORE_IF(pcd), &ep0->dwc_ep);
+-01234 
+-01235         /* Prepare for more SETUP Packets */
+-01236         if (GET_CORE_IF(pcd)->dma_enable == 0) {
+-01237                 ep0_out_start(GET_CORE_IF(pcd), pcd);
+-01238         }
+-01239 }
+-01240 
+-01245 static inline void pcd_clear_halt(dwc_otg_pcd_t * pcd, dwc_otg_pcd_ep_t * ep)
+-01246 {
+-01247         if (ep->dwc_ep.stall_clear_flag == 0)
+-01248                 dwc_otg_ep_clear_stall(GET_CORE_IF(pcd), &ep->dwc_ep);
+-01249 
+-01250         /* Reactive the EP */
+-01251         dwc_otg_ep_activate(GET_CORE_IF(pcd), &ep->dwc_ep);
+-01252         if (ep->stopped) {
+-01253                 ep->stopped = 0;
+-01254                 /* If there is a request in the EP queue start it */
+-01255 
+-01259                 /*
+-01260                  * Above fixme is solved by implmenting a tasklet to call the
+-01261                  * start_next_request(), outside of interrupt context at some
+-01262                  * time after the current time, after a clear-halt setup packet.
+-01263                  * Still need to implement ep mismatch in the future if a gadget
+-01264                  * ever uses more than one endpoint at once
+-01265                  */
+-01266                 ep->queue_sof = 1;
+-01267                 DWC_TASK_SCHEDULE(pcd->start_xfer_tasklet);
+-01268         }
+-01269         /* Start Control Status Phase */
+-01270         do_setup_in_status_phase(pcd);
+-01271 }
+-01272 
+-01284 void do_test_mode(void *data)
+-01285 {
+-01286         dctl_data_t dctl;
+-01287         dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *) data;
+-01288         dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
+-01289         int test_mode = pcd->test_mode;
+-01290 
+-01291 //        DWC_WARN("%s() has not been tested since being rewritten!\n", __func__);
+-01292 
+-01293         dctl.d32 = dwc_read_reg32(&core_if->dev_if->dev_global_regs->dctl);
+-01294         switch (test_mode) {
+-01295         case 1:         // TEST_J
+-01296                 dctl.b.tstctl = 1;
+-01297                 break;
+-01298 
+-01299         case 2:         // TEST_K
+-01300                 dctl.b.tstctl = 2;
+-01301                 break;
+-01302 
+-01303         case 3:         // TEST_SE0_NAK
+-01304                 dctl.b.tstctl = 3;
+-01305                 break;
+-01306 
+-01307         case 4:         // TEST_PACKET
+-01308                 dctl.b.tstctl = 4;
+-01309                 break;
+-01310 
+-01311         case 5:         // TEST_FORCE_ENABLE
+-01312                 dctl.b.tstctl = 5;
+-01313                 break;
+-01314         }
+-01315         dwc_write_reg32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32);
+-01316 }
+-01317 
+-01321 static inline void do_get_status(dwc_otg_pcd_t * pcd)
+-01322 {
+-01323         usb_device_request_t ctrl = pcd->setup_pkt->req;
+-01324         dwc_otg_pcd_ep_t *ep;
+-01325         dwc_otg_pcd_ep_t *ep0 = &pcd->ep0;
+-01326         uint16_t *status = pcd->status_buf;
+-01327 
+-01328 #ifdef DEBUG_EP0
+-01329         DWC_DEBUGPL(DBG_PCD,
+-01330                     "GET_STATUS %02x.%02x v%04x i%04x l%04x\n",
+-01331                     ctrl.bmRequestType, ctrl.bRequest,
+-01332                     UGETW(ctrl.wValue), UGETW(ctrl.wIndex),
+-01333                     UGETW(ctrl.wLength));
+-01334 #endif
+-01335 
+-01336         switch (UT_GET_RECIPIENT(ctrl.bmRequestType)) {
+-01337         case UT_DEVICE:
+-01338                 *status = 0x1;  /* Self powered */
+-01339                 *status |= pcd->remote_wakeup_enable << 1;
+-01340                 break;
+-01341 
+-01342         case UT_INTERFACE:
+-01343                 *status = 0;
+-01344                 break;
+-01345 
+-01346         case UT_ENDPOINT:
+-01347                 ep = get_ep_by_addr(pcd, UGETW(ctrl.wIndex));
+-01348                 if (ep == 0 || UGETW(ctrl.wLength) > 2) {
+-01349                         ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED);
+-01350                         return;
+-01351                 }
+-01353                 *status = ep->stopped;
+-01354                 break;
+-01355         }
+-01356         pcd->ep0_pending = 1;
+-01357         ep0->dwc_ep.start_xfer_buff = (uint8_t *) status;
+-01358         ep0->dwc_ep.xfer_buff = (uint8_t *) status;
+-01359         ep0->dwc_ep.dma_addr = pcd->status_buf_dma_handle;
+-01360         ep0->dwc_ep.xfer_len = 2;
+-01361         ep0->dwc_ep.xfer_count = 0;
+-01362         ep0->dwc_ep.total_len = ep0->dwc_ep.xfer_len;
+-01363         dwc_otg_ep0_start_transfer(GET_CORE_IF(pcd), &ep0->dwc_ep);
+-01364 }
+-01365 
+-01369 static inline void do_set_feature(dwc_otg_pcd_t * pcd)
+-01370 {
+-01371         dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
+-01372         dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
+-01373         usb_device_request_t ctrl = pcd->setup_pkt->req;
+-01374         dwc_otg_pcd_ep_t *ep = 0;
+-01375         int32_t otg_cap_param = core_if->core_params->otg_cap;
+-01376         gotgctl_data_t gotgctl = {.d32 = 0 };
+-01377 
+-01378         DWC_DEBUGPL(DBG_PCD, "SET_FEATURE:%02x.%02x v%04x i%04x l%04x\n",
+-01379                     ctrl.bmRequestType, ctrl.bRequest,
+-01380                     UGETW(ctrl.wValue), UGETW(ctrl.wIndex),
+-01381                     UGETW(ctrl.wLength));
+-01382         DWC_DEBUGPL(DBG_PCD, "otg_cap=%d\n", otg_cap_param);
+-01383 
+-01384         switch (UT_GET_RECIPIENT(ctrl.bmRequestType)) {
+-01385         case UT_DEVICE:
+-01386                 switch (UGETW(ctrl.wValue)) {
+-01387                 case UF_DEVICE_REMOTE_WAKEUP:
+-01388                         pcd->remote_wakeup_enable = 1;
+-01389                         break;
+-01390 
+-01391                 case UF_TEST_MODE:
+-01392                         /* Setup the Test Mode tasklet to do the Test
+-01393                          * Packet generation after the SETUP Status
+-01394                          * phase has completed. */
+-01395 
+-01399                         pcd->test_mode = UGETW(ctrl.wIndex) >> 8;
+-01400                         DWC_TASK_SCHEDULE(pcd->test_mode_tasklet);
+-01401                         break;
+-01402 
+-01403                 case UF_DEVICE_B_HNP_ENABLE:
+-01404                         DWC_DEBUGPL(DBG_PCDV,
+-01405                                     "SET_FEATURE: USB_DEVICE_B_HNP_ENABLE\n");
+-01406 
+-01407                         /* dev may initiate HNP */
+-01408                         if (otg_cap_param == DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE) {
+-01409                                 pcd->b_hnp_enable = 1;
+-01410                                 dwc_otg_pcd_update_otg(pcd, 0);
+-01411                                 DWC_DEBUGPL(DBG_PCD, "Request B HNP\n");
+-01414                                 gotgctl.b.devhnpen = 1;
+-01415                                 gotgctl.b.hnpreq = 1;
+-01416                                 dwc_write_reg32(&global_regs->gotgctl,
+-01417                                                 gotgctl.d32);
+-01418                         } else {
+-01419                                 ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED);
+-01420                         }
+-01421                         break;
+-01422 
+-01423                 case UF_DEVICE_A_HNP_SUPPORT:
+-01424                         /* RH port supports HNP */
+-01425                         DWC_DEBUGPL(DBG_PCDV,
+-01426                                     "SET_FEATURE: USB_DEVICE_A_HNP_SUPPORT\n");
+-01427                         if (otg_cap_param == DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE) {
+-01428                                 pcd->a_hnp_support = 1;
+-01429                                 dwc_otg_pcd_update_otg(pcd, 0);
+-01430                         } else {
+-01431                                 ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED);
+-01432                         }
+-01433                         break;
+-01434 
+-01435                 case UF_DEVICE_A_ALT_HNP_SUPPORT:
+-01436                         /* other RH port does */
+-01437                         DWC_DEBUGPL(DBG_PCDV,
+-01438                                     "SET_FEATURE: USB_DEVICE_A_ALT_HNP_SUPPORT\n");
+-01439                         if (otg_cap_param == DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE) {
+-01440                                 pcd->a_alt_hnp_support = 1;
+-01441                                 dwc_otg_pcd_update_otg(pcd, 0);
+-01442                         } else {
+-01443                                 ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED);
+-01444                         }
+-01445                         break;
+-01446                 }
+-01447                 do_setup_in_status_phase(pcd);
+-01448                 break;
+-01449 
+-01450         case UT_INTERFACE:
+-01451                 do_gadget_setup(pcd, &ctrl);
+-01452                 break;
+-01453 
+-01454         case UT_ENDPOINT:
+-01455                 if (UGETW(ctrl.wValue) == UF_ENDPOINT_HALT) {
+-01456                         ep = get_ep_by_addr(pcd, UGETW(ctrl.wIndex));
+-01457                         if (ep == 0) {
+-01458                                 ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED);
+-01459                                 return;
+-01460                         }
+-01461                         ep->stopped = 1;
+-01462                         dwc_otg_ep_set_stall(core_if, &ep->dwc_ep);
+-01463                 }
+-01464                 do_setup_in_status_phase(pcd);
+-01465                 break;
+-01466         }
+-01467 }
+-01468 
+-01472 static inline void do_clear_feature(dwc_otg_pcd_t * pcd)
+-01473 {
+-01474         usb_device_request_t ctrl = pcd->setup_pkt->req;
+-01475         dwc_otg_pcd_ep_t *ep = 0;
+-01476 
+-01477         DWC_DEBUGPL(DBG_PCD,
+-01478                     "CLEAR_FEATURE:%02x.%02x v%04x i%04x l%04x\n",
+-01479                     ctrl.bmRequestType, ctrl.bRequest,
+-01480                     UGETW(ctrl.wValue), UGETW(ctrl.wIndex),
+-01481                     UGETW(ctrl.wLength));
+-01482 
+-01483         switch (UT_GET_RECIPIENT(ctrl.bmRequestType)) {
+-01484         case UT_DEVICE:
+-01485                 switch (UGETW(ctrl.wValue)) {
+-01486                 case UF_DEVICE_REMOTE_WAKEUP:
+-01487                         pcd->remote_wakeup_enable = 0;
+-01488                         break;
+-01489 
+-01490                 case UF_TEST_MODE:
+-01492                         break;
+-01493                 }
+-01494                 do_setup_in_status_phase(pcd);
+-01495                 break;
+-01496 
+-01497         case UT_ENDPOINT:
+-01498                 ep = get_ep_by_addr(pcd, UGETW(ctrl.wIndex));
+-01499                 if (ep == 0) {
+-01500                         ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED);
+-01501                         return;
+-01502                 }
+-01503 
+-01504                 pcd_clear_halt(pcd, ep);
+-01505 
+-01506                 break;
+-01507         }
+-01508 }
+-01509 
+-01513 static inline void do_set_address(dwc_otg_pcd_t * pcd)
+-01514 {
+-01515         dwc_otg_dev_if_t *dev_if = GET_CORE_IF(pcd)->dev_if;
+-01516         usb_device_request_t ctrl = pcd->setup_pkt->req;
+-01517 
+-01518         if (ctrl.bmRequestType == UT_DEVICE) {
+-01519                 dcfg_data_t dcfg = {.d32 = 0 };
+-01520 
+-01521 #ifdef DEBUG_EP0
+-01522 //                      DWC_DEBUGPL(DBG_PCDV, "SET_ADDRESS:%d\n", ctrl.wValue);
+-01523 #endif
+-01524                 dcfg.b.devaddr = UGETW(ctrl.wValue);
+-01525                 dwc_modify_reg32(&dev_if->dev_global_regs->dcfg, 0, dcfg.d32);
+-01526                 do_setup_in_status_phase(pcd);
+-01527         }
+-01528 }
+-01529 
+-01580 static inline void pcd_setup(dwc_otg_pcd_t * pcd)
+-01581 {
+-01582         dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
+-01583         dwc_otg_dev_if_t *dev_if = core_if->dev_if;
+-01584         usb_device_request_t ctrl = pcd->setup_pkt->req;
+-01585         dwc_otg_pcd_ep_t *ep0 = &pcd->ep0;
+-01586 
+-01587         deptsiz0_data_t doeptsize0 = {.d32 = 0 };
+-01588 
+-01589 #ifdef DWC_UTE_CFI
+-01590         int retval = 0;
+-01591         struct cfi_usb_ctrlrequest cfi_req;
+-01592 #endif
+-01593 
+-01594 #ifdef DEBUG_EP0
+-01595         DWC_DEBUGPL(DBG_PCD, "SETUP %02x.%02x v%04x i%04x l%04x\n",
+-01596                     ctrl.bmRequestType, ctrl.bRequest,
+-01597                     UGETW(ctrl.wValue), UGETW(ctrl.wIndex),
+-01598                     UGETW(ctrl.wLength));
+-01599 #endif
+-01600 
+-01601         doeptsize0.d32 = dwc_read_reg32(&dev_if->out_ep_regs[0]->doeptsiz);
+-01602 
+-01605         if (core_if->dma_enable && core_if->dma_desc_enable == 0
+-01606             && (doeptsize0.b.supcnt < 2)) {
+-01607                 DWC_ERROR
+-01608                     ("\n\n-----------    CANNOT handle > 1 setup packet in DMA mode\n\n");
+-01609         }
+-01610 
+-01611         /* Clean up the request queue */
+-01612         dwc_otg_request_nuke(ep0);
+-01613         ep0->stopped = 0;
+-01614 
+-01615         if (ctrl.bmRequestType & UE_DIR_IN) {
+-01616                 ep0->dwc_ep.is_in = 1;
+-01617                 pcd->ep0state = EP0_IN_DATA_PHASE;
+-01618         } else {
+-01619                 ep0->dwc_ep.is_in = 0;
+-01620                 pcd->ep0state = EP0_OUT_DATA_PHASE;
+-01621         }
+-01622 
+-01623         if (UGETW(ctrl.wLength) == 0) {
+-01624                 ep0->dwc_ep.is_in = 1;
+-01625                 pcd->ep0state = EP0_IN_STATUS_PHASE;
+-01626         }
+-01627 
+-01628         if (UT_GET_TYPE(ctrl.bmRequestType) != UT_STANDARD) {
+-01629 
+-01630 #ifdef DWC_UTE_CFI
+-01631                 DWC_MEMCPY(&cfi_req, &ctrl, sizeof(usb_device_request_t));
+-01632 
+-01633                 //printk(KERN_ALERT "CFI: req_type=0x%02x; req=0x%02x\n", ctrl.bRequestType, ctrl.bRequest);
+-01634                 if (UT_GET_TYPE(cfi_req.bRequestType) == UT_VENDOR) {
+-01635                         if (cfi_req.bRequest > 0xB0 && cfi_req.bRequest < 0xBF) {
+-01636                                 retval = cfi_setup(pcd, &cfi_req);
+-01637                                 if (retval < 0) {
+-01638                                         ep0_do_stall(pcd, retval);
+-01639                                         pcd->ep0_pending = 0;
+-01640                                         return;
+-01641                                 }
+-01642 
+-01643                                 /* if need gadget setup then call it and check the retval */
+-01644                                 if (pcd->cfi->need_gadget_att) {
+-01645                                         retval =
+-01646                                             cfi_gadget_setup(pcd,
+-01647                                                              &pcd->cfi->
+-01648                                                              ctrl_req);
+-01649                                         if (retval < 0) {
+-01650                                                 pcd->ep0_pending = 0;
+-01651                                                 return;
+-01652                                         }
+-01653                                 }
+-01654 
+-01655                                 if (pcd->cfi->need_status_in_complete) {
+-01656                                         do_setup_in_status_phase(pcd);
+-01657                                 }
+-01658                                 return;
+-01659                         }
+-01660                 }
+-01661 #endif
+-01662 
+-01663                 /* handle non-standard (class/vendor) requests in the gadget driver */
+-01664                 do_gadget_setup(pcd, &ctrl);
+-01665                 return;
+-01666         }
+-01667 
+-01670 
+-01671 
+-01672 
+-01673         switch (ctrl.bRequest) {
+-01674         case UR_GET_STATUS:
+-01675                 do_get_status(pcd);
+-01676                 break;
+-01677 
+-01678         case UR_CLEAR_FEATURE:
+-01679                 do_clear_feature(pcd);
+-01680                 break;
+-01681 
+-01682         case UR_SET_FEATURE:
+-01683                 do_set_feature(pcd);
+-01684                 break;
+-01685 
+-01686         case UR_SET_ADDRESS:
+-01687                 do_set_address(pcd);
+-01688                 break;
+-01689 
+-01690         case UR_SET_INTERFACE:
+-01691         case UR_SET_CONFIG:
+-01692 //              _pcd->request_config = 1;       /* Configuration changed */
+-01693                 do_gadget_setup(pcd, &ctrl);
+-01694                 break;
+-01695 
+-01696         case UR_SYNCH_FRAME:
+-01697                 do_gadget_setup(pcd, &ctrl);
+-01698                 break;
+-01699 
+-01700         default:
+-01701                 /* Call the Gadget Driver's setup functions */
+-01702                 do_gadget_setup(pcd, &ctrl);
+-01703                 break;
+-01704         }
+-01705 }
+-01706 
+-01710 static int32_t ep0_complete_request(dwc_otg_pcd_ep_t * ep)
+-01711 {
+-01712         dwc_otg_core_if_t *core_if = GET_CORE_IF(ep->pcd);
+-01713         dwc_otg_dev_if_t *dev_if = core_if->dev_if;
+-01714         dwc_otg_dev_in_ep_regs_t *in_ep_regs =
+-01715             dev_if->in_ep_regs[ep->dwc_ep.num];
+-01716 #ifdef DEBUG_EP0
+-01717         dwc_otg_dev_out_ep_regs_t *out_ep_regs =
+-01718             dev_if->out_ep_regs[ep->dwc_ep.num];
+-01719 #endif
+-01720         deptsiz0_data_t deptsiz;
+-01721         dev_dma_desc_sts_t desc_sts;
+-01722         dwc_otg_pcd_request_t *req;
+-01723         int is_last = 0;
+-01724         dwc_otg_pcd_t *pcd = ep->pcd;
+-01725 
+-01726 #ifdef DWC_UTE_CFI
+-01727         struct cfi_usb_ctrlrequest *ctrlreq;
+-01728         int retval = -DWC_E_NOT_SUPPORTED;
+-01729 #endif
+-01730 
+-01731         if (pcd->ep0_pending && DWC_CIRCLEQ_EMPTY(&ep->queue)) {
+-01732                 if (ep->dwc_ep.is_in) {
+-01733 #ifdef DEBUG_EP0
+-01734                         DWC_DEBUGPL(DBG_PCDV, "Do setup OUT status phase\n");
+-01735 #endif
+-01736                         do_setup_out_status_phase(pcd);
+-01737                 } else {
+-01738 #ifdef DEBUG_EP0
+-01739                         DWC_DEBUGPL(DBG_PCDV, "Do setup IN status phase\n");
+-01740 #endif
+-01741 
+-01742 #ifdef DWC_UTE_CFI
+-01743                         ctrlreq = &pcd->cfi->ctrl_req;
+-01744 
+-01745                         if (UT_GET_TYPE(ctrlreq->bRequestType) == UT_VENDOR) {
+-01746                                 if (ctrlreq->bRequest > 0xB0
+-01747                                     && ctrlreq->bRequest < 0xBF) {
+-01748 
+-01749                                         /* Return if the PCD failed to handle the request */
+-01750                                         if ((retval =
+-01751                                              pcd->cfi->ops.
+-01752                                              ctrl_write_complete(pcd->cfi,
+-01753                                                                  pcd)) < 0) {
+-01754                                                 CFI_INFO
+-01755                                                     ("ERROR setting a new value in the PCD(%d)\n",
+-01756                                                      retval);
+-01757                                                 ep0_do_stall(pcd, retval);
+-01758                                                 pcd->ep0_pending = 0;
+-01759                                                 return 0;
+-01760                                         }
+-01761 
+-01762                                         /* If the gadget needs to be notified on the request */
+-01763                                         if (pcd->cfi->need_gadget_att == 1) {
+-01764                                                 //retval = do_gadget_setup(pcd, &pcd->cfi->ctrl_req);
+-01765                                                 retval =
+-01766                                                     cfi_gadget_setup(pcd,
+-01767                                                                      &pcd->cfi->
+-01768                                                                      ctrl_req);
+-01769 
+-01770                                                 /* Return from the function if the gadget failed to process
+-01771                                                  * the request properly - this should never happen !!!
+-01772                                                  */
+-01773                                                 if (retval < 0) {
+-01774                                                         CFI_INFO
+-01775                                                             ("ERROR setting a new value in the gadget(%d)\n",
+-01776                                                              retval);
+-01777                                                         pcd->ep0_pending = 0;
+-01778                                                         return 0;
+-01779                                                 }
+-01780                                         }
+-01781 
+-01782                                         CFI_INFO("%s: RETVAL=%d\n", __func__,
+-01783                                                  retval);
+-01784                                         /* If we hit here then the PCD and the gadget has properly
+-01785                                          * handled the request - so send the ZLP IN to the host.
+-01786                                          */
+-01787                                         /* @todo: MAS - decide whether we need to start the setup
+-01788                                          * stage based on the need_setup value of the cfi object
+-01789                                          */
+-01790                                         do_setup_in_status_phase(pcd);
+-01791                                         pcd->ep0_pending = 0;
+-01792                                         return 1;
+-01793                                 }
+-01794                         }
+-01795 #endif
+-01796 
+-01797                         do_setup_in_status_phase(pcd);
+-01798                 }
+-01799                 pcd->ep0_pending = 0;
+-01800                 return 1;
+-01801         }
+-01802 
+-01803         if (DWC_CIRCLEQ_EMPTY(&ep->queue)) {
+-01804                 return 0;
+-01805         }
+-01806         req = DWC_CIRCLEQ_FIRST(&ep->queue);
+-01807 
+-01808         if (pcd->ep0state == EP0_OUT_STATUS_PHASE
+-01809             || pcd->ep0state == EP0_IN_STATUS_PHASE) {
+-01810                 is_last = 1;
+-01811         } else if (ep->dwc_ep.is_in) {
+-01812                 deptsiz.d32 = dwc_read_reg32(&in_ep_regs->dieptsiz);
+-01813                 if (core_if->dma_desc_enable != 0)
+-01814                         desc_sts = dev_if->in_desc_addr->status;
+-01815 #ifdef DEBUG_EP0
+-01816                 DWC_DEBUGPL(DBG_PCDV, "%d len=%d  xfersize=%d pktcnt=%d\n",
+-01817                             ep->dwc_ep.num, ep->dwc_ep.xfer_len,
+-01818                             deptsiz.b.xfersize, deptsiz.b.pktcnt);
+-01819 #endif
+-01820 
+-01821                 if (((core_if->dma_desc_enable == 0)
+-01822                      && (deptsiz.b.xfersize == 0))
+-01823                     || ((core_if->dma_desc_enable != 0)
+-01824                         && (desc_sts.b.bytes == 0))) {
+-01825                         req->actual = ep->dwc_ep.xfer_count;
+-01826                         /* Is a Zero Len Packet needed? */
+-01827                         if (req->sent_zlp) {
+-01828 #ifdef DEBUG_EP0
+-01829                                 DWC_DEBUGPL(DBG_PCD, "Setup Rx ZLP\n");
+-01830 #endif
+-01831                                 req->sent_zlp = 0;
+-01832                         }
+-01833                         do_setup_out_status_phase(pcd);
+-01834                 }
+-01835         } else {
+-01836                 /* ep0-OUT */
+-01837 #ifdef DEBUG_EP0
+-01838                 deptsiz.d32 = dwc_read_reg32(&out_ep_regs->doeptsiz);
+-01839                 DWC_DEBUGPL(DBG_PCDV, "%d len=%d xsize=%d pktcnt=%d\n",
+-01840                             ep->dwc_ep.num, ep->dwc_ep.xfer_len,
+-01841                             deptsiz.b.xfersize, deptsiz.b.pktcnt);
+-01842 #endif
+-01843                 req->actual = ep->dwc_ep.xfer_count;
+-01844 
+-01845                 /* Is a Zero Len Packet needed? */
+-01846                 if (req->sent_zlp) {
+-01847 #ifdef DEBUG_EP0
+-01848                         DWC_DEBUGPL(DBG_PCDV, "Setup Tx ZLP\n");
+-01849 #endif
+-01850                         req->sent_zlp = 0;
+-01851                 }
+-01852                 if (core_if->dma_desc_enable == 0)
+-01853                         do_setup_in_status_phase(pcd);
+-01854         }
+-01855 
+-01856         /* Complete the request */
+-01857         if (is_last) {
+-01858                 dwc_otg_request_done(ep, req, 0);
+-01859                 ep->dwc_ep.start_xfer_buff = 0;
+-01860                 ep->dwc_ep.xfer_buff = 0;
+-01861                 ep->dwc_ep.xfer_len = 0;
+-01862                 return 1;
+-01863         }
+-01864         return 0;
+-01865 }
+-01866 
+-01867 #ifdef DWC_UTE_CFI
+-01868 
+-01874 static inline int cfi_calc_desc_residue(dwc_otg_pcd_ep_t * ep)
+-01875 {
+-01876         int32_t ret = 0;
+-01877         int i;
+-01878         struct dwc_otg_dma_desc *ddesc = NULL;
+-01879         struct cfi_ep *cfiep;
+-01880 
+-01881         /* See if the pcd_ep has its respective cfi_ep mapped */
+-01882         cfiep = get_cfi_ep_by_pcd_ep(ep->pcd->cfi, ep);
+-01883         if (!cfiep) {
+-01884                 CFI_INFO("%s: Failed to find ep\n", __func__);
+-01885                 return -1;
+-01886         }
+-01887 
+-01888         ddesc = ep->dwc_ep.descs;
+-01889 
+-01890         for (i = 0; (i < cfiep->desc_count) && (i < MAX_DMA_DESCS_PER_EP); i++) {
+-01891 
+-01892 #if defined(PRINT_CFI_DMA_DESCS)
+-01893                 print_desc(ddesc, ep->ep.name, i);
+-01894 #endif
+-01895                 ret += ddesc->status.b.bytes;
+-01896                 ddesc++;
+-01897         }
+-01898 
+-01899         if (ret)
+-01900                 CFI_INFO("!!!!!!!!!! WARNING (%s) - residue=%d\n", __func__,
+-01901                          ret);
+-01902 
+-01903         return ret;
+-01904 }
+-01905 #endif
+-01906 
+-01911 static void complete_ep(dwc_otg_pcd_ep_t * ep)
+-01912 {
+-01913         dwc_otg_core_if_t *core_if = GET_CORE_IF(ep->pcd);
+-01914         dwc_otg_dev_if_t *dev_if = core_if->dev_if;
+-01915         dwc_otg_dev_in_ep_regs_t *in_ep_regs =
+-01916             dev_if->in_ep_regs[ep->dwc_ep.num];
+-01917         deptsiz_data_t deptsiz;
+-01918         dev_dma_desc_sts_t desc_sts;
+-01919         dwc_otg_pcd_request_t *req = 0;
+-01920         dwc_otg_dev_dma_desc_t *dma_desc;
+-01921         uint32_t byte_count = 0;
+-01922         int is_last = 0;
+-01923         int i;
+-01924 
+-01925         DWC_DEBUGPL(DBG_PCDV, "%s() %d-%s\n", __func__, ep->dwc_ep.num,
+-01926                     (ep->dwc_ep.is_in ? "IN" : "OUT"));
+-01927 
+-01928         /* Get any pending requests */
+-01929         if (!DWC_CIRCLEQ_EMPTY(&ep->queue)) {
+-01930                 req = DWC_CIRCLEQ_FIRST(&ep->queue);
+-01931                 if (!req) {
+-01932                         DWC_PRINTF("complete_ep 0x%p, req = NULL!\n", ep);
+-01933                         return;
+-01934                 }
+-01935         } else {
+-01936                 DWC_PRINTF("complete_ep 0x%p, ep->queue empty!\n", ep);
+-01937                 return;
+-01938         }
+-01939 
+-01940         DWC_DEBUGPL(DBG_PCD, "Requests %d\n", ep->pcd->request_pending);
+-01941 
+-01942         if (ep->dwc_ep.is_in) {
+-01943                 deptsiz.d32 = dwc_read_reg32(&in_ep_regs->dieptsiz);
+-01944 
+-01945                 if (core_if->dma_enable) {
+-01946                         if (core_if->dma_desc_enable == 0) {
+-01947                                 if (deptsiz.b.xfersize == 0
+-01948                                     && deptsiz.b.pktcnt == 0) {
+-01949                                         byte_count =
+-01950                                             ep->dwc_ep.xfer_len -
+-01951                                             ep->dwc_ep.xfer_count;
+-01952 
+-01953                                         ep->dwc_ep.xfer_buff += byte_count;
+-01954                                         ep->dwc_ep.dma_addr += byte_count;
+-01955                                         ep->dwc_ep.xfer_count += byte_count;
+-01956 
+-01957                                         DWC_DEBUGPL(DBG_PCDV,
+-01958                                                     "%d-%s len=%d  xfersize=%d pktcnt=%d\n",
+-01959                                                     ep->dwc_ep.num,
+-01960                                                     (ep->dwc_ep.
+-01961                                                      is_in ? "IN" : "OUT"),
+-01962                                                     ep->dwc_ep.xfer_len,
+-01963                                                     deptsiz.b.xfersize,
+-01964                                                     deptsiz.b.pktcnt);
+-01965 
+-01966                                         if (ep->dwc_ep.xfer_len <
+-01967                                             ep->dwc_ep.total_len) {
+-01968                                                 dwc_otg_ep_start_transfer
+-01969                                                     (core_if, &ep->dwc_ep);
+-01970                                         } else if (ep->dwc_ep.sent_zlp) {
+-01971                                                 /*      
+-01972                                                  * This fragment of code should initiate 0 
+-01973                                                  * length trasfer in case if it is queued
+-01974                                                  * a trasfer with size divisible to EPs max 
+-01975                                                  * packet size and with usb_request zero field 
+-01976                                                  * is set, which means that after data is transfered, 
+-01977                                                  * it is also should be transfered 
+-01978                                                  * a 0 length packet at the end. For Slave and 
+-01979                                                  * Buffer DMA modes in this case SW has 
+-01980                                                  * to initiate 2 transfers one with transfer size, 
+-01981                                                  * and the second with 0 size. For Desriptor 
+-01982                                                  * DMA mode SW is able to initiate a transfer, 
+-01983                                                  * which will handle all the packets including 
+-01984                                                  * the last  0 legth.
+-01985                                                  */
+-01986                                                 ep->dwc_ep.sent_zlp = 0;
+-01987                                                 dwc_otg_ep_start_zl_transfer
+-01988                                                     (core_if, &ep->dwc_ep);
+-01989                                         } else {
+-01990                                                 is_last = 1;
+-01991                                         }
+-01992                                 } else {
+-01993                                         DWC_WARN
+-01994                                             ("Incomplete transfer (%d - %s [siz=%d pkt=%d])\n",
+-01995                                              ep->dwc_ep.num,
+-01996                                              (ep->dwc_ep.is_in ? "IN" : "OUT"),
+-01997                                              deptsiz.b.xfersize,
+-01998                                              deptsiz.b.pktcnt);
+-01999                                 }
+-02000                         } else {
+-02001                                 dma_desc = ep->dwc_ep.desc_addr;
+-02002                                 byte_count = 0;
+-02003                                 ep->dwc_ep.sent_zlp = 0;
+-02004 
+-02005 #ifdef DWC_UTE_CFI
+-02006                                 CFI_INFO("%s: BUFFER_MODE=%d\n", __func__,
+-02007                                          ep->dwc_ep.buff_mode);
+-02008                                 if (ep->dwc_ep.buff_mode != BM_STANDARD) {
+-02009                                         int residue;
+-02010 
+-02011                                         residue = cfi_calc_desc_residue(ep);
+-02012                                         if (residue < 0)
+-02013                                                 return;
+-02014 
+-02015                                         byte_count = residue;
+-02016                                 } else {
+-02017 #endif
+-02018                                         for (i = 0; i < ep->dwc_ep.desc_cnt;
+-02019                                              ++i) {
+-02020                                         desc_sts = dma_desc->status;
+-02021                                         byte_count += desc_sts.b.bytes;
+-02022                                         dma_desc++;
+-02023                                 }
+-02024 #ifdef DWC_UTE_CFI
+-02025                                 }
+-02026 #endif
+-02027                                 if (byte_count == 0) {
+-02028                                         ep->dwc_ep.xfer_count =
+-02029                                             ep->dwc_ep.total_len;
+-02030                                         is_last = 1;
+-02031                                 } else {
+-02032                                         DWC_WARN("Incomplete transfer\n");
+-02033                                 }
+-02034                         }
+-02035                 } else {
+-02036                         if (deptsiz.b.xfersize == 0 && deptsiz.b.pktcnt == 0) {
+-02037                                 DWC_DEBUGPL(DBG_PCDV,
+-02038                                             "%d-%s len=%d  xfersize=%d pktcnt=%d\n",
+-02039                                             ep->dwc_ep.num,
+-02040                                             ep->dwc_ep.is_in ? "IN" : "OUT",
+-02041                                             ep->dwc_ep.xfer_len,
+-02042                                             deptsiz.b.xfersize,
+-02043                                             deptsiz.b.pktcnt);
+-02044 
+-02045                                 /*      Check if the whole transfer was completed,  
+-02046                                  *      if no, setup transfer for next portion of data
+-02047                                  */
+-02048                                 if (ep->dwc_ep.xfer_len < ep->dwc_ep.total_len) {
+-02049                                         dwc_otg_ep_start_transfer(core_if,
+-02050                                                                   &ep->dwc_ep);
+-02051                                 } else if (ep->dwc_ep.sent_zlp) {
+-02052                                         /*      
+-02053                                          * This fragment of code should initiate 0 
+-02054                                          * length trasfer in case if it is queued
+-02055                                          * a trasfer with size divisible to EPs max 
+-02056                                          * packet size and with usb_request zero field 
+-02057                                          * is set, which means that after data is transfered, 
+-02058                                          * it is also should be transfered 
+-02059                                          * a 0 length packet at the end. For Slave and 
+-02060                                          * Buffer DMA modes in this case SW has 
+-02061                                          * to initiate 2 transfers one with transfer size, 
+-02062                                          * and the second with 0 size. For Desriptor 
+-02063                                          * DMA mode SW is able to initiate a transfer, 
+-02064                                          * which will handle all the packets including 
+-02065                                          * the last  0 legth.
+-02066                                          */
+-02067                                         ep->dwc_ep.sent_zlp = 0;
+-02068                                         dwc_otg_ep_start_zl_transfer(core_if,
+-02069                                                                      &ep->
+-02070                                                                      dwc_ep);
+-02071                                 } else {
+-02072                                         is_last = 1;
+-02073                                 }
+-02074                         } else {
+-02075                                 DWC_WARN
+-02076                                     ("Incomplete transfer (%d-%s [siz=%d pkt=%d])\n",
+-02077                                      ep->dwc_ep.num,
+-02078                                      (ep->dwc_ep.is_in ? "IN" : "OUT"),
+-02079                                      deptsiz.b.xfersize, deptsiz.b.pktcnt);
+-02080                         }
+-02081                 }
+-02082         } else {
+-02083                 dwc_otg_dev_out_ep_regs_t *out_ep_regs =
+-02084                     dev_if->out_ep_regs[ep->dwc_ep.num];
+-02085                 desc_sts.d32 = 0;
+-02086                 if (core_if->dma_enable) {
+-02087                         if (core_if->dma_desc_enable) {
+-02088                                 dma_desc = ep->dwc_ep.desc_addr;
+-02089                                 byte_count = 0;
+-02090                                 ep->dwc_ep.sent_zlp = 0;
+-02091 
+-02092 #ifdef DWC_UTE_CFI
+-02093                                 CFI_INFO("%s: BUFFER_MODE=%d\n", __func__,
+-02094                                          ep->dwc_ep.buff_mode);
+-02095                                 if (ep->dwc_ep.buff_mode != BM_STANDARD) {
+-02096                                         int residue;
+-02097                                         residue = cfi_calc_desc_residue(ep);
+-02098                                         if (residue < 0)
+-02099                                                 return;
+-02100                                         byte_count = residue;
+-02101                                 } else {
+-02102 #endif
+-02103 
+-02104                                         for (i = 0; i < ep->dwc_ep.desc_cnt;
+-02105                                              ++i) {
+-02106                                         desc_sts = dma_desc->status;
+-02107                                         byte_count += desc_sts.b.bytes;
+-02108                                         dma_desc++;
+-02109                                 }
+-02110 
+-02111 #ifdef DWC_UTE_CFI
+-02112                                 }
+-02113 #endif
+-02114                                 ep->dwc_ep.xfer_count = ep->dwc_ep.total_len
+-02115                                     - byte_count +
+-02116                                     ((4 - (ep->dwc_ep.total_len & 0x3)) & 0x3);
+-02117                                 is_last = 1;
+-02118                         } else {
+-02119                                 deptsiz.d32 = 0;
+-02120                                 deptsiz.d32 =
+-02121                                     dwc_read_reg32(&out_ep_regs->doeptsiz);
+-02122 
+-02123                                 byte_count = (ep->dwc_ep.xfer_len -
+-02124                                               ep->dwc_ep.xfer_count -
+-02125                                               deptsiz.b.xfersize);
+-02126                                 ep->dwc_ep.xfer_buff += byte_count;
+-02127                                 ep->dwc_ep.dma_addr += byte_count;
+-02128                                 ep->dwc_ep.xfer_count += byte_count;
+-02129 
+-02130                                 /*      Check if the whole transfer was completed,  
+-02131                                  *      if no, setup transfer for next portion of data
+-02132                                  */
+-02133                                 if (ep->dwc_ep.xfer_len < ep->dwc_ep.total_len) {
+-02134                                         dwc_otg_ep_start_transfer(core_if,
+-02135                                                                   &ep->dwc_ep);
+-02136                                 } else if (ep->dwc_ep.sent_zlp) {
+-02137                                         /*      
+-02138                                          * This fragment of code should initiate 0 
+-02139                                          * length trasfer in case if it is queued
+-02140                                          * a trasfer with size divisible to EPs max 
+-02141                                          * packet size and with usb_request zero field 
+-02142                                          * is set, which means that after data is transfered, 
+-02143                                          * it is also should be transfered 
+-02144                                          * a 0 length packet at the end. For Slave and 
+-02145                                          * Buffer DMA modes in this case SW has 
+-02146                                          * to initiate 2 transfers one with transfer size, 
+-02147                                          * and the second with 0 size. For Desriptor 
+-02148                                          * DMA mode SW is able to initiate a transfer, 
+-02149                                          * which will handle all the packets including 
+-02150                                          * the last  0 legth.
+-02151                                          */
+-02152                                         ep->dwc_ep.sent_zlp = 0;
+-02153                                         dwc_otg_ep_start_zl_transfer(core_if,
+-02154                                                                      &ep->
+-02155                                                                      dwc_ep);
+-02156                                 } else {
+-02157                                         is_last = 1;
+-02158                                 }
+-02159                         }
+-02160                 } else {
+-02161                         /*      Check if the whole transfer was completed,  
+-02162                          *      if no, setup transfer for next portion of data
+-02163                          */
+-02164                         if (ep->dwc_ep.xfer_len < ep->dwc_ep.total_len) {
+-02165                                 dwc_otg_ep_start_transfer(core_if, &ep->dwc_ep);
+-02166                         } else if (ep->dwc_ep.sent_zlp) {
+-02167                                 /*      
+-02168                                  * This fragment of code should initiate 0 
+-02169                                  * length trasfer in case if it is queued
+-02170                                  * a trasfer with size divisible to EPs max 
+-02171                                  * packet size and with usb_request zero field 
+-02172                                  * is set, which means that after data is transfered, 
+-02173                                  * it is also should be transfered 
+-02174                                  * a 0 length packet at the end. For Slave and 
+-02175                                  * Buffer DMA modes in this case SW has 
+-02176                                  * to initiate 2 transfers one with transfer size, 
+-02177                                  * and the second with 0 size. For Desriptor 
+-02178                                  * DMA mode SW is able to initiate a transfer, 
+-02179                                  * which will handle all the packets including 
+-02180                                  * the last  0 legth.
+-02181                                  */
+-02182                                 ep->dwc_ep.sent_zlp = 0;
+-02183                                 dwc_otg_ep_start_zl_transfer(core_if,
+-02184                                                              &ep->dwc_ep);
+-02185                         } else {
+-02186                                 is_last = 1;
+-02187                         }
+-02188                 }
+-02189 
+-02190                 DWC_DEBUGPL(DBG_PCDV,
+-02191                             "addr %p,    %d-%s len=%d cnt=%d xsize=%d pktcnt=%d\n",
+-02192                             &out_ep_regs->doeptsiz, ep->dwc_ep.num,
+-02193                             ep->dwc_ep.is_in ? "IN" : "OUT",
+-02194                             ep->dwc_ep.xfer_len, ep->dwc_ep.xfer_count,
+-02195                             deptsiz.b.xfersize, deptsiz.b.pktcnt);
+-02196         }
+-02197 
+-02198         /* Complete the request */
+-02199         if (is_last) {
+-02200 #ifdef DWC_UTE_CFI
+-02201                 if (ep->dwc_ep.buff_mode != BM_STANDARD) {
+-02202                         req->actual = ep->dwc_ep.cfi_req_len - byte_count;
+-02203                 } else {
+-02204 #endif
+-02205                 req->actual = ep->dwc_ep.xfer_count;
+-02206 #ifdef DWC_UTE_CFI
+-02207                 }
+-02208 #endif
+-02209 
+-02210                 dwc_otg_request_done(ep, req, 0);
+-02211 
+-02212                 ep->dwc_ep.start_xfer_buff = 0;
+-02213                 ep->dwc_ep.xfer_buff = 0;
+-02214                 ep->dwc_ep.xfer_len = 0;
+-02215 
+-02216                 /* If there is a request in the queue start it. */
+-02217                 start_next_request(ep);
+-02218         }
+-02219 }
+-02220 
+-02221 #ifdef DWC_EN_ISOC
+-02222 
+-02227 static void dwc_otg_pcd_handle_iso_bna(dwc_otg_pcd_ep_t * ep)
+-02228 {
+-02229         dwc_ep_t *dwc_ep = &ep->dwc_ep;
+-02230         volatile uint32_t *addr;
+-02231         depctl_data_t depctl = {.d32 = 0 };
+-02232         dwc_otg_pcd_t *pcd = ep->pcd;
+-02233         dwc_otg_dev_dma_desc_t *dma_desc;
+-02234         int i;
+-02235 
+-02236         dma_desc =
+-02237             dwc_ep->iso_desc_addr + dwc_ep->desc_cnt * (dwc_ep->proc_buf_num);
+-02238 
+-02239         if (dwc_ep->is_in) {
+-02240                 dev_dma_desc_sts_t sts = {.d32 = 0 };
+-02241                 for (i = 0; i < dwc_ep->desc_cnt; ++i, ++dma_desc) {
+-02242                         sts.d32 = dma_desc->status.d32;
+-02243                         sts.b_iso_in.bs = BS_HOST_READY;
+-02244                         dma_desc->status.d32 = sts.d32;
+-02245                 }
+-02246         } else {
+-02247                 dev_dma_desc_sts_t sts = {.d32 = 0 };
+-02248                 for (i = 0; i < dwc_ep->desc_cnt; ++i, ++dma_desc) {
+-02249                         sts.d32 = dma_desc->status.d32;
+-02250                         sts.b_iso_out.bs = BS_HOST_READY;
+-02251                         dma_desc->status.d32 = sts.d32;
+-02252                 }
+-02253         }
+-02254 
+-02255         if (dwc_ep->is_in == 0) {
+-02256                 addr =
+-02257                     &GET_CORE_IF(pcd)->dev_if->out_ep_regs[dwc_ep->num]->
+-02258                     doepctl;
+-02259         } else {
+-02260                 addr =
+-02261                     &GET_CORE_IF(pcd)->dev_if->in_ep_regs[dwc_ep->num]->diepctl;
+-02262         }
+-02263         depctl.b.epena = 1;
+-02264         dwc_modify_reg32(addr, depctl.d32, depctl.d32);
+-02265 }
+-02266 
+-02274 void set_current_pkt_info(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
+-02275 {
+-02276         deptsiz_data_t deptsiz = {.d32 = 0 };
+-02277         dma_addr_t dma_addr;
+-02278         uint32_t offset;
+-02279 
+-02280         if (ep->proc_buf_num)
+-02281                 dma_addr = ep->dma_addr1;
+-02282         else
+-02283                 dma_addr = ep->dma_addr0;
+-02284 
+-02285         if (ep->is_in) {
+-02286                 deptsiz.d32 =
+-02287                     dwc_read_reg32(&core_if->dev_if->in_ep_regs[ep->num]->
+-02288                                    dieptsiz);
+-02289                 offset = ep->data_per_frame;
+-02290         } else {
+-02291                 deptsiz.d32 =
+-02292                     dwc_read_reg32(&core_if->dev_if->out_ep_regs[ep->num]->
+-02293                                    doeptsiz);
+-02294                 offset =
+-02295                     ep->data_per_frame +
+-02296                     (0x4 & (0x4 - (ep->data_per_frame & 0x3)));
+-02297         }
+-02298 
+-02299         if (!deptsiz.b.xfersize) {
+-02300                 ep->pkt_info[ep->cur_pkt].length = ep->data_per_frame;
+-02301                 ep->pkt_info[ep->cur_pkt].offset =
+-02302                     ep->cur_pkt_dma_addr - dma_addr;
+-02303                 ep->pkt_info[ep->cur_pkt].status = 0;
+-02304         } else {
+-02305                 ep->pkt_info[ep->cur_pkt].length = ep->data_per_frame;
+-02306                 ep->pkt_info[ep->cur_pkt].offset =
+-02307                     ep->cur_pkt_dma_addr - dma_addr;
+-02308                 ep->pkt_info[ep->cur_pkt].status = -DWC_E_NO_DATA;
+-02309         }
+-02310         ep->cur_pkt_addr += offset;
+-02311         ep->cur_pkt_dma_addr += offset;
+-02312         ep->cur_pkt++;
+-02313 }
+-02314 
+-02322 static void set_ddma_iso_pkts_info(dwc_otg_core_if_t * core_if,
+-02323                                    dwc_ep_t * dwc_ep)
+-02324 {
+-02325         dwc_otg_dev_dma_desc_t *dma_desc;
+-02326         dev_dma_desc_sts_t sts = {.d32 = 0 };
+-02327         iso_pkt_info_t *iso_packet;
+-02328         uint32_t data_per_desc;
+-02329         uint32_t offset;
+-02330         int i, j;
+-02331 
+-02332         iso_packet = dwc_ep->pkt_info;
+-02333 
+-02336         if (dwc_ep->is_in == 0) {
+-02337                 dma_desc =
+-02338                     dwc_ep->iso_desc_addr +
+-02339                     dwc_ep->desc_cnt * dwc_ep->proc_buf_num;
+-02340                 offset = 0;
+-02341 
+-02342                 for (i = 0; i < dwc_ep->desc_cnt - dwc_ep->pkt_per_frm;
+-02343                      i += dwc_ep->pkt_per_frm) {
+-02344                         for (j = 0; j < dwc_ep->pkt_per_frm; ++j) {
+-02345                                 data_per_desc =
+-02346                                     ((j + 1) * dwc_ep->maxpacket >
+-02347                                      dwc_ep->data_per_frame) ? dwc_ep->
+-02348                                     data_per_frame -
+-02349                                     j * dwc_ep->maxpacket : dwc_ep->maxpacket;
+-02350                                 data_per_desc +=
+-02351                                     (data_per_desc % 4) ? (4 -
+-02352                                                            data_per_desc %
+-02353                                                            4) : 0;
+-02354 
+-02355                                 sts.d32 = dma_desc->status.d32;
+-02356 
+-02357                                 /* Write status in iso_packet_decsriptor  */
+-02358                                 iso_packet->status =
+-02359                                     sts.b_iso_out.rxsts +
+-02360                                     (sts.b_iso_out.bs ^ BS_DMA_DONE);
+-02361                                 if (iso_packet->status) {
+-02362                                         iso_packet->status = -DWC_E_NO_DATA;
+-02363                                 }
+-02364 
+-02365                                 /* Received data length */
+-02366                                 if (!sts.b_iso_out.rxbytes) {
+-02367                                         iso_packet->length =
+-02368                                             data_per_desc -
+-02369                                             sts.b_iso_out.rxbytes;
+-02370                                 } else {
+-02371                                         iso_packet->length =
+-02372                                             data_per_desc -
+-02373                                             sts.b_iso_out.rxbytes + (4 -
+-02374                                                                      dwc_ep->
+-02375                                                                      data_per_frame
+-02376                                                                      % 4);
+-02377                                 }
+-02378 
+-02379                                 iso_packet->offset = offset;
+-02380 
+-02381                                 offset += data_per_desc;
+-02382                                 dma_desc++;
+-02383                                 iso_packet++;
+-02384                         }
+-02385                 }
+-02386 
+-02387                 for (j = 0; j < dwc_ep->pkt_per_frm - 1; ++j) {
+-02388                         data_per_desc =
+-02389                             ((j + 1) * dwc_ep->maxpacket >
+-02390                              dwc_ep->data_per_frame) ? dwc_ep->data_per_frame -
+-02391                             j * dwc_ep->maxpacket : dwc_ep->maxpacket;
+-02392                         data_per_desc +=
+-02393                             (data_per_desc % 4) ? (4 - data_per_desc % 4) : 0;
+-02394 
+-02395                         sts.d32 = dma_desc->status.d32;
+-02396 
+-02397                         /* Write status in iso_packet_decsriptor  */
+-02398                         iso_packet->status =
+-02399                             sts.b_iso_out.rxsts +
+-02400                             (sts.b_iso_out.bs ^ BS_DMA_DONE);
+-02401                         if (iso_packet->status) {
+-02402                                 iso_packet->status = -DWC_E_NO_DATA;
+-02403                         }
+-02404 
+-02405                         /* Received data length */
+-02406                         iso_packet->length =
+-02407                             dwc_ep->data_per_frame - sts.b_iso_out.rxbytes;
+-02408 
+-02409                         iso_packet->offset = offset;
+-02410 
+-02411                         offset += data_per_desc;
+-02412                         iso_packet++;
+-02413                         dma_desc++;
+-02414                 }
+-02415 
+-02416                 sts.d32 = dma_desc->status.d32;
+-02417 
+-02418                 /* Write status in iso_packet_decsriptor  */
+-02419                 iso_packet->status =
+-02420                     sts.b_iso_out.rxsts + (sts.b_iso_out.bs ^ BS_DMA_DONE);
+-02421                 if (iso_packet->status) {
+-02422                         iso_packet->status = -DWC_E_NO_DATA;
+-02423                 }
+-02424                 /* Received data length */
+-02425                 if (!sts.b_iso_out.rxbytes) {
+-02426                         iso_packet->length =
+-02427                             dwc_ep->data_per_frame - sts.b_iso_out.rxbytes;
+-02428                 } else {
+-02429                         iso_packet->length =
+-02430                             dwc_ep->data_per_frame - sts.b_iso_out.rxbytes +
+-02431                             (4 - dwc_ep->data_per_frame % 4);
+-02432                 }
+-02433 
+-02434                 iso_packet->offset = offset;
+-02435         } else {
+-02438                 dma_desc =
+-02439                     dwc_ep->iso_desc_addr +
+-02440                     dwc_ep->desc_cnt * dwc_ep->proc_buf_num;
+-02441 
+-02442                 for (i = 0; i < dwc_ep->desc_cnt - 1; i++) {
+-02443                         sts.d32 = dma_desc->status.d32;
+-02444 
+-02445                         /* Write status in iso packet descriptor */
+-02446                         iso_packet->status =
+-02447                             sts.b_iso_in.txsts +
+-02448                             (sts.b_iso_in.bs ^ BS_DMA_DONE);
+-02449                         if (iso_packet->status != 0) {
+-02450                                 iso_packet->status = -DWC_E_NO_DATA;
+-02451 
+-02452                         }
+-02453                         /* Bytes has been transfered */
+-02454                         iso_packet->length =
+-02455                             dwc_ep->data_per_frame - sts.b_iso_in.txbytes;
+-02456 
+-02457                         dma_desc++;
+-02458                         iso_packet++;
+-02459                 }
+-02460 
+-02461                 sts.d32 = dma_desc->status.d32;
+-02462                 while (sts.b_iso_in.bs == BS_DMA_BUSY) {
+-02463                         sts.d32 = dma_desc->status.d32;
+-02464                 }
+-02465 
+-02466                 /* Write status in iso packet descriptor ??? do be done with ERROR codes */
+-02467                 iso_packet->status =
+-02468                     sts.b_iso_in.txsts + (sts.b_iso_in.bs ^ BS_DMA_DONE);
+-02469                 if (iso_packet->status != 0) {
+-02470                         iso_packet->status = -DWC_E_NO_DATA;
+-02471                 }
+-02472 
+-02473                 /* Bytes has been transfered */
+-02474                 iso_packet->length =
+-02475                     dwc_ep->data_per_frame - sts.b_iso_in.txbytes;
+-02476         }
+-02477 }
+-02478 
+-02486 static void reinit_ddma_iso_xfer(dwc_otg_core_if_t * core_if, dwc_ep_t * dwc_ep)
+-02487 {
+-02488         int i, j;
+-02489         dwc_otg_dev_dma_desc_t *dma_desc;
+-02490         dma_addr_t dma_ad;
+-02491         volatile uint32_t *addr;
+-02492         dev_dma_desc_sts_t sts = {.d32 = 0 };
+-02493         uint32_t data_per_desc;
+-02494 
+-02495         if (dwc_ep->is_in == 0) {
+-02496                 addr = &core_if->dev_if->out_ep_regs[dwc_ep->num]->doepctl;
+-02497         } else {
+-02498                 addr = &core_if->dev_if->in_ep_regs[dwc_ep->num]->diepctl;
+-02499         }
+-02500 
+-02501         if (dwc_ep->proc_buf_num == 0) {
+-02503                 dma_ad = dwc_ep->dma_addr0;
+-02504         } else {
+-02506                 dma_ad = dwc_ep->dma_addr1;
+-02507         }
+-02508 
+-02511         if (dwc_ep->is_in == 0) {
+-02512                 dma_desc =
+-02513                     dwc_ep->iso_desc_addr +
+-02514                     dwc_ep->desc_cnt * dwc_ep->proc_buf_num;
+-02515 
+-02516                 sts.b_iso_out.bs = BS_HOST_READY;
+-02517                 sts.b_iso_out.rxsts = 0;
+-02518                 sts.b_iso_out.l = 0;
+-02519                 sts.b_iso_out.sp = 0;
+-02520                 sts.b_iso_out.ioc = 0;
+-02521                 sts.b_iso_out.pid = 0;
+-02522                 sts.b_iso_out.framenum = 0;
+-02523 
+-02524                 for (i = 0; i < dwc_ep->desc_cnt - dwc_ep->pkt_per_frm;
+-02525                      i += dwc_ep->pkt_per_frm) {
+-02526                         for (j = 0; j < dwc_ep->pkt_per_frm; ++j) {
+-02527                                 data_per_desc =
+-02528                                     ((j + 1) * dwc_ep->maxpacket >
+-02529                                      dwc_ep->data_per_frame) ? dwc_ep->
+-02530                                     data_per_frame -
+-02531                                     j * dwc_ep->maxpacket : dwc_ep->maxpacket;
+-02532                                 data_per_desc +=
+-02533                                     (data_per_desc % 4) ? (4 -
+-02534                                                            data_per_desc %
+-02535                                                            4) : 0;
+-02536                                 sts.b_iso_out.rxbytes = data_per_desc;
+-02537                                 dma_desc->buf = dma_ad;
+-02538                                 dma_desc->status.d32 = sts.d32;
+-02539 
+-02540                                 dma_ad += data_per_desc;
+-02541                                 dma_desc++;
+-02542                         }
+-02543                 }
+-02544 
+-02545                 for (j = 0; j < dwc_ep->pkt_per_frm - 1; ++j) {
+-02546 
+-02547                         data_per_desc =
+-02548                             ((j + 1) * dwc_ep->maxpacket >
+-02549                              dwc_ep->data_per_frame) ? dwc_ep->data_per_frame -
+-02550                             j * dwc_ep->maxpacket : dwc_ep->maxpacket;
+-02551                         data_per_desc +=
+-02552                             (data_per_desc % 4) ? (4 - data_per_desc % 4) : 0;
+-02553                         sts.b_iso_out.rxbytes = data_per_desc;
+-02554 
+-02555                         dma_desc->buf = dma_ad;
+-02556                         dma_desc->status.d32 = sts.d32;
+-02557 
+-02558                         dma_desc++;
+-02559                         dma_ad += data_per_desc;
+-02560                 }
+-02561 
+-02562                 sts.b_iso_out.ioc = 1;
+-02563                 sts.b_iso_out.l = dwc_ep->proc_buf_num;
+-02564 
+-02565                 data_per_desc =
+-02566                     ((j + 1) * dwc_ep->maxpacket >
+-02567                      dwc_ep->data_per_frame) ? dwc_ep->data_per_frame -
+-02568                     j * dwc_ep->maxpacket : dwc_ep->maxpacket;
+-02569                 data_per_desc +=
+-02570                     (data_per_desc % 4) ? (4 - data_per_desc % 4) : 0;
+-02571                 sts.b_iso_out.rxbytes = data_per_desc;
+-02572 
+-02573                 dma_desc->buf = dma_ad;
+-02574                 dma_desc->status.d32 = sts.d32;
+-02575         } else {
+-02578                 dma_desc =
+-02579                     dwc_ep->iso_desc_addr +
+-02580                     dwc_ep->desc_cnt * dwc_ep->proc_buf_num;
+-02581 
+-02582                 sts.b_iso_in.bs = BS_HOST_READY;
+-02583                 sts.b_iso_in.txsts = 0;
+-02584                 sts.b_iso_in.sp = 0;
+-02585                 sts.b_iso_in.ioc = 0;
+-02586                 sts.b_iso_in.pid = dwc_ep->pkt_per_frm;
+-02587                 sts.b_iso_in.framenum = dwc_ep->next_frame;
+-02588                 sts.b_iso_in.txbytes = dwc_ep->data_per_frame;
+-02589                 sts.b_iso_in.l = 0;
+-02590 
+-02591                 for (i = 0; i < dwc_ep->desc_cnt - 1; i++) {
+-02592                         dma_desc->buf = dma_ad;
+-02593                         dma_desc->status.d32 = sts.d32;
+-02594 
+-02595                         sts.b_iso_in.framenum += dwc_ep->bInterval;
+-02596                         dma_ad += dwc_ep->data_per_frame;
+-02597                         dma_desc++;
+-02598                 }
+-02599 
+-02600                 sts.b_iso_in.ioc = 1;
+-02601                 sts.b_iso_in.l = dwc_ep->proc_buf_num;
+-02602 
+-02603                 dma_desc->buf = dma_ad;
+-02604                 dma_desc->status.d32 = sts.d32;
+-02605 
+-02606                 dwc_ep->next_frame =
+-02607                     sts.b_iso_in.framenum + dwc_ep->bInterval * 1;
+-02608         }
+-02609         dwc_ep->proc_buf_num = (dwc_ep->proc_buf_num ^ 1) & 0x1;
+-02610 }
+-02611 
+-02620 static uint32_t handle_iso_out_pkt_dropped(dwc_otg_core_if_t * core_if,
+-02621                                            dwc_ep_t * dwc_ep)
+-02622 {
+-02623         uint32_t dma_addr;
+-02624         uint32_t drp_pkt;
+-02625         uint32_t drp_pkt_cnt;
+-02626         deptsiz_data_t deptsiz = {.d32 = 0 };
+-02627         depctl_data_t depctl = {.d32 = 0 };
+-02628         int i;
+-02629 
+-02630         deptsiz.d32 =
+-02631             dwc_read_reg32(&core_if->dev_if->out_ep_regs[dwc_ep->num]->
+-02632                            doeptsiz);
+-02633 
+-02634         drp_pkt = dwc_ep->pkt_cnt - deptsiz.b.pktcnt;
+-02635         drp_pkt_cnt = dwc_ep->pkt_per_frm - (drp_pkt % dwc_ep->pkt_per_frm);
+-02636 
+-02637         /* Setting dropped packets status */
+-02638         for (i = 0; i < drp_pkt_cnt; ++i) {
+-02639                 dwc_ep->pkt_info[drp_pkt].status = -DWC_E_NO_DATA;
+-02640                 drp_pkt++;
+-02641                 deptsiz.b.pktcnt--;
+-02642         }
+-02643 
+-02644         if (deptsiz.b.pktcnt > 0) {
+-02645                 deptsiz.b.xfersize =
+-02646                     dwc_ep->xfer_len - (dwc_ep->pkt_cnt -
+-02647                                         deptsiz.b.pktcnt) * dwc_ep->maxpacket;
+-02648         } else {
+-02649                 deptsiz.b.xfersize = 0;
+-02650                 deptsiz.b.pktcnt = 0;
+-02651         }
+-02652 
+-02653         dwc_write_reg32(&core_if->dev_if->out_ep_regs[dwc_ep->num]->doeptsiz,
+-02654                         deptsiz.d32);
+-02655 
+-02656         if (deptsiz.b.pktcnt > 0) {
+-02657                 if (dwc_ep->proc_buf_num) {
+-02658                         dma_addr =
+-02659                             dwc_ep->dma_addr1 + dwc_ep->xfer_len -
+-02660                             deptsiz.b.xfersize;
+-02661                 } else {
+-02662                         dma_addr =
+-02663                             dwc_ep->dma_addr0 + dwc_ep->xfer_len -
+-02664                             deptsiz.b.xfersize;;
+-02665                 }
+-02666 
+-02667                 dwc_write_reg32(&core_if->dev_if->out_ep_regs[dwc_ep->num]->
+-02668                                 doepdma, dma_addr);
+-02669 
+-02671                 depctl.d32 = 0;
+-02672                 depctl.b.epena = 1;
+-02673                 depctl.b.cnak = 1;
+-02674 
+-02675                 dwc_modify_reg32(&core_if->dev_if->out_ep_regs[dwc_ep->num]->
+-02676                                  doepctl, depctl.d32, depctl.d32);
+-02677                 return 0;
+-02678         } else {
+-02679                 return 1;
+-02680         }
+-02681 }
+-02682 
+-02690 static uint32_t set_iso_pkts_info(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
+-02691 {
+-02692         int i, j;
+-02693         dma_addr_t dma_ad;
+-02694         iso_pkt_info_t *packet_info = ep->pkt_info;
+-02695         uint32_t offset;
+-02696         uint32_t frame_data;
+-02697         deptsiz_data_t deptsiz;
+-02698 
+-02699         if (ep->proc_buf_num == 0) {
+-02701                 dma_ad = ep->dma_addr0;
+-02702         } else {
+-02704                 dma_ad = ep->dma_addr1;
+-02705         }
+-02706 
+-02707         if (ep->is_in) {
+-02708                 deptsiz.d32 =
+-02709                     dwc_read_reg32(&core_if->dev_if->in_ep_regs[ep->num]->
+-02710                                    dieptsiz);
+-02711         } else {
+-02712                 deptsiz.d32 =
+-02713                     dwc_read_reg32(&core_if->dev_if->out_ep_regs[ep->num]->
+-02714                                    doeptsiz);
+-02715         }
+-02716 
+-02717         if (!deptsiz.b.xfersize) {
+-02718                 offset = 0;
+-02719                 for (i = 0; i < ep->pkt_cnt; i += ep->pkt_per_frm) {
+-02720                         frame_data = ep->data_per_frame;
+-02721                         for (j = 0; j < ep->pkt_per_frm; ++j) {
+-02722 
+-02723                                 /* Packet status - is not set as initially 
+-02724                                  * it is set to 0 and if packet was sent 
+-02725                                  successfully, status field will remain 0*/
+-02726 
+-02727                                 /* Bytes has been transfered */
+-02728                                 packet_info->length =
+-02729                                     (ep->maxpacket <
+-02730                                      frame_data) ? ep->maxpacket : frame_data;
+-02731 
+-02732                                 /* Received packet offset */
+-02733                                 packet_info->offset = offset;
+-02734                                 offset += packet_info->length;
+-02735                                 frame_data -= packet_info->length;
+-02736 
+-02737                                 packet_info++;
+-02738                         }
+-02739                 }
+-02740                 return 1;
+-02741         } else {
+-02742                 /* This is a workaround for in case of Transfer Complete with 
+-02743                  * PktDrpSts interrupts merging - in this case Transfer complete 
+-02744                  * interrupt for Isoc Out Endpoint is asserted without PktDrpSts 
+-02745                  * set and with DOEPTSIZ register non zero. Investigations showed,
+-02746                  * that this happens when Out packet is dropped, but because of 
+-02747                  * interrupts merging during first interrupt handling PktDrpSts
+-02748                  * bit is cleared and for next merged interrupts it is not reset.
+-02749                  * In this case SW hadles the interrupt as if PktDrpSts bit is set.
+-02750                  */
+-02751                 if (ep->is_in) {
+-02752                         return 1;
+-02753                 } else {
+-02754                         return handle_iso_out_pkt_dropped(core_if, ep);
+-02755                 }
+-02756         }
+-02757 }
+-02758 
+-02766 static void complete_iso_ep(dwc_otg_pcd_t * pcd, dwc_otg_pcd_ep_t * ep)
+-02767 {
+-02768         dwc_otg_core_if_t *core_if = GET_CORE_IF(ep->pcd);
+-02769         dwc_ep_t *dwc_ep = &ep->dwc_ep;
+-02770         uint8_t is_last = 0;
+-02771 
+-02772         if(ep->dwc_ep.next_frame == 0xffffffff) {
+-02773                 DWC_WARN("Next frame is not set!\n");
+-02774                 return;
+-02775         }
+-02776 
+-02777         if (core_if->dma_enable) {
+-02778                 if (core_if->dma_desc_enable) {
+-02779                         set_ddma_iso_pkts_info(core_if, dwc_ep);
+-02780                         reinit_ddma_iso_xfer(core_if, dwc_ep);
+-02781                         is_last = 1;
+-02782                 } else {
+-02783                         if (core_if->pti_enh_enable) {
+-02784                                 if (set_iso_pkts_info(core_if, dwc_ep)) {
+-02785                                         dwc_ep->proc_buf_num =
+-02786                                             (dwc_ep->proc_buf_num ^ 1) & 0x1;
+-02787                                         dwc_otg_iso_ep_start_buf_transfer
+-02788                                             (core_if, dwc_ep);
+-02789                                         is_last = 1;
+-02790                                 }
+-02791                         } else {
+-02792                                 set_current_pkt_info(core_if, dwc_ep);
+-02793                                 if (dwc_ep->cur_pkt >= dwc_ep->pkt_cnt) {
+-02794                                         is_last = 1;
+-02795                                         dwc_ep->cur_pkt = 0;
+-02796                                         dwc_ep->proc_buf_num =
+-02797                                             (dwc_ep->proc_buf_num ^ 1) & 0x1;
+-02798                                         if (dwc_ep->proc_buf_num) {
+-02799                                                 dwc_ep->cur_pkt_addr =
+-02800                                                     dwc_ep->xfer_buff1;
+-02801                                                 dwc_ep->cur_pkt_dma_addr =
+-02802                                                     dwc_ep->dma_addr1;
+-02803                                         } else {
+-02804                                                 dwc_ep->cur_pkt_addr =
+-02805                                                     dwc_ep->xfer_buff0;
+-02806                                                 dwc_ep->cur_pkt_dma_addr =
+-02807                                                     dwc_ep->dma_addr0;
+-02808                                         }
+-02809 
+-02810                                 }
+-02811                                 dwc_otg_iso_ep_start_frm_transfer(core_if,
+-02812                                                                   dwc_ep);
+-02813                         }
+-02814                 }
+-02815         } else {
+-02816                 set_current_pkt_info(core_if, dwc_ep);
+-02817                 if (dwc_ep->cur_pkt >= dwc_ep->pkt_cnt) {
+-02818                         is_last = 1;
+-02819                         dwc_ep->cur_pkt = 0;
+-02820                         dwc_ep->proc_buf_num = (dwc_ep->proc_buf_num ^ 1) & 0x1;
+-02821                         if (dwc_ep->proc_buf_num) {
+-02822                                 dwc_ep->cur_pkt_addr = dwc_ep->xfer_buff1;
+-02823                                 dwc_ep->cur_pkt_dma_addr = dwc_ep->dma_addr1;
+-02824                         } else {
+-02825                                 dwc_ep->cur_pkt_addr = dwc_ep->xfer_buff0;
+-02826                                 dwc_ep->cur_pkt_dma_addr = dwc_ep->dma_addr0;
+-02827                         }
+-02828 
+-02829                 }
+-02830                 dwc_otg_iso_ep_start_frm_transfer(core_if, dwc_ep);
+-02831         }
+-02832         if (is_last)
+-02833                 dwc_otg_iso_buffer_done(pcd, ep, ep->iso_req_handle);
+-02834 }
+-02835 #endif                          /* DWC_EN_ISOC */
+-02836 
+-02843 static void handle_ep0(dwc_otg_pcd_t * pcd)
+-02844 {
+-02845         dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
+-02846         dwc_otg_pcd_ep_t *ep0 = &pcd->ep0;
+-02847         dev_dma_desc_sts_t desc_sts;
+-02848         deptsiz0_data_t deptsiz;
+-02849         uint32_t byte_count;
+-02850 
+-02851 #ifdef DEBUG_EP0
+-02852         DWC_DEBUGPL(DBG_PCDV, "%s()\n", __func__);
+-02853         print_ep0_state(pcd);
+-02854 #endif
+-02855 
+-02856 //      DWC_PRINTF("HANDLE EP0\n");
+-02857 
+-02858         switch (pcd->ep0state) {
+-02859         case EP0_DISCONNECT:
+-02860                 break;
+-02861 
+-02862         case EP0_IDLE:
+-02863                 pcd->request_config = 0;
+-02864 
+-02865                 pcd_setup(pcd);
+-02866                 break;
+-02867 
+-02868         case EP0_IN_DATA_PHASE:
+-02869 #ifdef DEBUG_EP0
+-02870                 DWC_DEBUGPL(DBG_PCD, "DATA_IN EP%d-%s: type=%d, mps=%d\n",
+-02871                             ep0->dwc_ep.num, (ep0->dwc_ep.is_in ? "IN" : "OUT"),
+-02872                             ep0->dwc_ep.type, ep0->dwc_ep.maxpacket);
+-02873 #endif
+-02874 
+-02875                 if (core_if->dma_enable != 0) {
+-02876                         /*
+-02877                          * For EP0 we can only program 1 packet at a time so we
+-02878                          * need to do the make calculations after each complete.
+-02879                          * Call write_packet to make the calculations, as in
+-02880                          * slave mode, and use those values to determine if we
+-02881                          * can complete.
+-02882                          */
+-02883                         if (core_if->dma_desc_enable == 0) {
+-02884                                 deptsiz.d32 =
+-02885                                     dwc_read_reg32(&core_if->dev_if->
+-02886                                                    in_ep_regs[0]->dieptsiz);
+-02887                                 byte_count =
+-02888                                     ep0->dwc_ep.xfer_len - deptsiz.b.xfersize;
+-02889                         } else {
+-02890                                 desc_sts =
+-02891                                     core_if->dev_if->in_desc_addr->status;
+-02892                                 byte_count =
+-02893                                     ep0->dwc_ep.xfer_len - desc_sts.b.bytes;
+-02894                         }
+-02895                         ep0->dwc_ep.xfer_count += byte_count;
+-02896                         ep0->dwc_ep.xfer_buff += byte_count;
+-02897                         ep0->dwc_ep.dma_addr += byte_count;
+-02898                 }
+-02899                 if (ep0->dwc_ep.xfer_count < ep0->dwc_ep.total_len) {
+-02900                         dwc_otg_ep0_continue_transfer(GET_CORE_IF(pcd),
+-02901                                                       &ep0->dwc_ep);
+-02902                         DWC_DEBUGPL(DBG_PCD, "CONTINUE TRANSFER\n");
+-02903                 } else if (ep0->dwc_ep.sent_zlp) {
+-02904                         dwc_otg_ep0_continue_transfer(GET_CORE_IF(pcd),
+-02905                                                       &ep0->dwc_ep);
+-02906                         ep0->dwc_ep.sent_zlp = 0;
+-02907                         DWC_DEBUGPL(DBG_PCD, "CONTINUE TRANSFER\n");
+-02908                 } else {
+-02909                         ep0_complete_request(ep0);
+-02910                         DWC_DEBUGPL(DBG_PCD, "COMPLETE TRANSFER\n");
+-02911                 }
+-02912                 break;
+-02913         case EP0_OUT_DATA_PHASE:
+-02914 #ifdef DEBUG_EP0
+-02915                 DWC_DEBUGPL(DBG_PCD, "DATA_OUT EP%d-%s: type=%d, mps=%d\n",
+-02916                             ep0->dwc_ep.num, (ep0->dwc_ep.is_in ? "IN" : "OUT"),
+-02917                             ep0->dwc_ep.type, ep0->dwc_ep.maxpacket);
+-02918 #endif
+-02919                 if (core_if->dma_enable != 0) {
+-02920                         if (core_if->dma_desc_enable == 0) {
+-02921                                 deptsiz.d32 =
+-02922                                     dwc_read_reg32(&core_if->dev_if->
+-02923                                                    out_ep_regs[0]->doeptsiz);
+-02924                                 byte_count =
+-02925                                     ep0->dwc_ep.maxpacket - deptsiz.b.xfersize;
+-02926                         } else {
+-02927                                 desc_sts =
+-02928                                     core_if->dev_if->out_desc_addr->status;
+-02929                                 byte_count =
+-02930                                     ep0->dwc_ep.maxpacket - desc_sts.b.bytes;
+-02931                         }
+-02932                         ep0->dwc_ep.xfer_count += byte_count;
+-02933                         ep0->dwc_ep.xfer_buff += byte_count;
+-02934                         ep0->dwc_ep.dma_addr += byte_count;
+-02935                 }
+-02936                 if (ep0->dwc_ep.xfer_count < ep0->dwc_ep.total_len) {
+-02937                         dwc_otg_ep0_continue_transfer(GET_CORE_IF(pcd),
+-02938                                                       &ep0->dwc_ep);
+-02939                         DWC_DEBUGPL(DBG_PCD, "CONTINUE TRANSFER\n");
+-02940                 } else if (ep0->dwc_ep.sent_zlp) {
+-02941                         dwc_otg_ep0_continue_transfer(GET_CORE_IF(pcd),
+-02942                                                       &ep0->dwc_ep);
+-02943                         ep0->dwc_ep.sent_zlp = 0;
+-02944                         DWC_DEBUGPL(DBG_PCD, "CONTINUE TRANSFER\n");
+-02945                 } else {
+-02946                         ep0_complete_request(ep0);
+-02947                         DWC_DEBUGPL(DBG_PCD, "COMPLETE TRANSFER\n");
+-02948                 }
+-02949                 break;
+-02950 
+-02951         case EP0_IN_STATUS_PHASE:
+-02952         case EP0_OUT_STATUS_PHASE:
+-02953                 DWC_DEBUGPL(DBG_PCD, "CASE: EP0_STATUS\n");
+-02954                 ep0_complete_request(ep0);
+-02955                 pcd->ep0state = EP0_IDLE;
+-02956                 ep0->stopped = 1;
+-02957                 ep0->dwc_ep.is_in = 0;  /* OUT for next SETUP */
+-02958 
+-02959                 /* Prepare for more SETUP Packets */
+-02960                 if (core_if->dma_enable) {
+-02961                         ep0_out_start(core_if, pcd);
+-02962                 }
+-02963                 break;
+-02964 
+-02965         case EP0_STALL:
+-02966                 DWC_ERROR("EP0 STALLed, should not get here pcd_setup()\n");
+-02967                 break;
+-02968         }
+-02969 #ifdef DEBUG_EP0
+-02970         print_ep0_state(pcd);
+-02971 #endif
+-02972 }
+-02973 
+-02977 static void restart_transfer(dwc_otg_pcd_t * pcd, const uint32_t epnum)
+-02978 {
+-02979         dwc_otg_core_if_t *core_if;
+-02980         dwc_otg_dev_if_t *dev_if;
+-02981         deptsiz_data_t dieptsiz = {.d32 = 0 };
+-02982         dwc_otg_pcd_ep_t *ep;
+-02983 
+-02984         ep = get_in_ep(pcd, epnum);
+-02985 
+-02986 #ifdef DWC_EN_ISOC
+-02987         if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) {
+-02988                 return;
+-02989         }
+-02990 #endif                          /* DWC_EN_ISOC  */
+-02991 
+-02992         core_if = GET_CORE_IF(pcd);
+-02993         dev_if = core_if->dev_if;
+-02994 
+-02995         dieptsiz.d32 = dwc_read_reg32(&dev_if->in_ep_regs[epnum]->dieptsiz);
+-02996 
+-02997         DWC_DEBUGPL(DBG_PCD, "xfer_buff=%p xfer_count=%0x xfer_len=%0x"
+-02998                     " stopped=%d\n", ep->dwc_ep.xfer_buff,
+-02999                     ep->dwc_ep.xfer_count, ep->dwc_ep.xfer_len, ep->stopped);
+-03000         /*
+-03001          * If xfersize is 0 and pktcnt in not 0, resend the last packet.
+-03002          */
+-03003         if (dieptsiz.b.pktcnt && dieptsiz.b.xfersize == 0 &&
+-03004             ep->dwc_ep.start_xfer_buff != 0) {
+-03005                 if (ep->dwc_ep.total_len <= ep->dwc_ep.maxpacket) {
+-03006                         ep->dwc_ep.xfer_count = 0;
+-03007                         ep->dwc_ep.xfer_buff = ep->dwc_ep.start_xfer_buff;
+-03008                         ep->dwc_ep.xfer_len = ep->dwc_ep.xfer_count;
+-03009                 } else {
+-03010                         ep->dwc_ep.xfer_count -= ep->dwc_ep.maxpacket;
+-03011                         /* convert packet size to dwords. */
+-03012                         ep->dwc_ep.xfer_buff -= ep->dwc_ep.maxpacket;
+-03013                         ep->dwc_ep.xfer_len = ep->dwc_ep.xfer_count;
+-03014                 }
+-03015                 ep->stopped = 0;
+-03016                 DWC_DEBUGPL(DBG_PCD, "xfer_buff=%p xfer_count=%0x "
+-03017                             "xfer_len=%0x stopped=%d\n",
+-03018                             ep->dwc_ep.xfer_buff,
+-03019                             ep->dwc_ep.xfer_count, ep->dwc_ep.xfer_len,
+-03020                             ep->stopped);
+-03021                 if (epnum == 0) {
+-03022                         dwc_otg_ep0_start_transfer(core_if, &ep->dwc_ep);
+-03023                 } else {
+-03024                         dwc_otg_ep_start_transfer(core_if, &ep->dwc_ep);
+-03025                 }
+-03026         }
+-03027 }
+-03028 
+-03032 static inline void handle_in_ep_disable_intr(dwc_otg_pcd_t * pcd,
+-03033                                              const uint32_t epnum)
+-03034 {
+-03035         dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
+-03036         dwc_otg_dev_if_t *dev_if = core_if->dev_if;
+-03037         deptsiz_data_t dieptsiz = {.d32 = 0 };
+-03038         dctl_data_t dctl = {.d32 = 0 };
+-03039         dwc_otg_pcd_ep_t *ep;
+-03040         dwc_ep_t *dwc_ep;
+-03041 
+-03042         ep = get_in_ep(pcd, epnum);
+-03043         dwc_ep = &ep->dwc_ep;
+-03044 
+-03045         if (dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) {
+-03046                 dwc_otg_flush_tx_fifo(core_if, dwc_ep->tx_fifo_num);
+-03047                 return;
+-03048         }
+-03049 
+-03050         DWC_DEBUGPL(DBG_PCD, "diepctl%d=%0x\n", epnum,
+-03051                     dwc_read_reg32(&dev_if->in_ep_regs[epnum]->diepctl));
+-03052         dieptsiz.d32 = dwc_read_reg32(&dev_if->in_ep_regs[epnum]->dieptsiz);
+-03053 
+-03054         DWC_DEBUGPL(DBG_ANY, "pktcnt=%d size=%d\n",
+-03055                     dieptsiz.b.pktcnt, dieptsiz.b.xfersize);
+-03056 
+-03057         if (ep->stopped) {
+-03058                 /* Flush the Tx FIFO */
+-03059                 dwc_otg_flush_tx_fifo(core_if, dwc_ep->tx_fifo_num);
+-03060                 /* Clear the Global IN NP NAK */
+-03061                 dctl.d32 = 0;
+-03062                 dctl.b.cgnpinnak = 1;
+-03063                 dwc_modify_reg32(&dev_if->dev_global_regs->dctl, dctl.d32, 0);
+-03064                 /* Restart the transaction */
+-03065                 if (dieptsiz.b.pktcnt != 0 || dieptsiz.b.xfersize != 0) {
+-03066                         restart_transfer(pcd, epnum);
+-03067                 }
+-03068         } else {
+-03069                 /* Restart the transaction */
+-03070                 if (dieptsiz.b.pktcnt != 0 || dieptsiz.b.xfersize != 0) {
+-03071                         restart_transfer(pcd, epnum);
+-03072                 }
+-03073                 DWC_DEBUGPL(DBG_ANY, "STOPPED!!!\n");
+-03074         }
+-03075 }
+-03076 
+-03080 static inline void handle_in_ep_timeout_intr(dwc_otg_pcd_t * pcd,
+-03081                                              const uint32_t epnum)
+-03082 {
+-03083         dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
+-03084         dwc_otg_dev_if_t *dev_if = core_if->dev_if;
+-03085 
+-03086 #ifdef DEBUG
+-03087         deptsiz_data_t dieptsiz = {.d32 = 0 };
+-03088         uint32_t num = 0;
+-03089 #endif
+-03090         dctl_data_t dctl = {.d32 = 0 };
+-03091         dwc_otg_pcd_ep_t *ep;
+-03092 
+-03093         gintmsk_data_t intr_mask = {.d32 = 0 };
+-03094 
+-03095         ep = get_in_ep(pcd, epnum);
+-03096 
+-03097         /* Disable the NP Tx Fifo Empty Interrrupt */
+-03098         if (!core_if->dma_enable) {
+-03099                 intr_mask.b.nptxfempty = 1;
+-03100                 dwc_modify_reg32(&core_if->core_global_regs->gintmsk,
+-03101                                  intr_mask.d32, 0);
+-03102         }
+-03105         /*
+-03106          * Non-periodic EP
+-03107          */
+-03108         /* Enable the Global IN NAK Effective Interrupt */
+-03109         intr_mask.b.ginnakeff = 1;
+-03110         dwc_modify_reg32(&core_if->core_global_regs->gintmsk, 0, intr_mask.d32);
+-03111 
+-03112         /* Set Global IN NAK */
+-03113         dctl.b.sgnpinnak = 1;
+-03114         dwc_modify_reg32(&dev_if->dev_global_regs->dctl, dctl.d32, dctl.d32);
+-03115 
+-03116         ep->stopped = 1;
+-03117 
+-03118 #ifdef DEBUG
+-03119         dieptsiz.d32 = dwc_read_reg32(&dev_if->in_ep_regs[num]->dieptsiz);
+-03120         DWC_DEBUGPL(DBG_ANY, "pktcnt=%d size=%d\n",
+-03121                     dieptsiz.b.pktcnt, dieptsiz.b.xfersize);
+-03122 #endif
+-03123 
+-03124 #ifdef DISABLE_PERIODIC_EP
+-03125         /*
+-03126          * Set the NAK bit for this EP to
+-03127          * start the disable process.
+-03128          */
+-03129         diepctl.d32 = 0;
+-03130         diepctl.b.snak = 1;
+-03131         dwc_modify_reg32(&dev_if->in_ep_regs[num]->diepctl, diepctl.d32,
+-03132                          diepctl.d32);
+-03133         ep->disabling = 1;
+-03134         ep->stopped = 1;
+-03135 #endif
+-03136 }
+-03137 
+-03141 static inline int32_t handle_in_ep_nak_intr(dwc_otg_pcd_t * pcd,
+-03142                                             const uint32_t epnum)
+-03143 {
+-03145         dwc_otg_core_if_t *core_if;
+-03146         diepmsk_data_t intr_mask = {.d32 = 0 };
+-03147 
+-03148         DWC_PRINTF("INTERRUPT Handler not implemented for %s\n", "IN EP NAK");
+-03149         core_if = GET_CORE_IF(pcd);
+-03150         intr_mask.b.nak = 1;
+-03151 
+-03152         if (core_if->multiproc_int_enable) {
+-03153                 dwc_modify_reg32(&core_if->dev_if->dev_global_regs->
+-03154                                  diepeachintmsk[epnum], intr_mask.d32, 0);
+-03155         } else {
+-03156                 dwc_modify_reg32(&core_if->dev_if->dev_global_regs->diepmsk,
+-03157                                  intr_mask.d32, 0);
+-03158         }
+-03159 
+-03160         return 1;
+-03161 }
+-03162 
+-03166 static inline int32_t handle_out_ep_babble_intr(dwc_otg_pcd_t * pcd,
+-03167                                                 const uint32_t epnum)
+-03168 {
+-03170         dwc_otg_core_if_t *core_if;
+-03171         doepmsk_data_t intr_mask = {.d32 = 0 };
+-03172 
+-03173         DWC_PRINTF("INTERRUPT Handler not implemented for %s\n",
+-03174                    "OUT EP Babble");
+-03175         core_if = GET_CORE_IF(pcd);
+-03176         intr_mask.b.babble = 1;
+-03177 
+-03178         if (core_if->multiproc_int_enable) {
+-03179                 dwc_modify_reg32(&core_if->dev_if->dev_global_regs->
+-03180                                  doepeachintmsk[epnum], intr_mask.d32, 0);
+-03181         } else {
+-03182                 dwc_modify_reg32(&core_if->dev_if->dev_global_regs->doepmsk,
+-03183                                  intr_mask.d32, 0);
+-03184         }
+-03185 
+-03186         return 1;
+-03187 }
+-03188 
+-03192 static inline int32_t handle_out_ep_nak_intr(dwc_otg_pcd_t * pcd,
+-03193                                              const uint32_t epnum)
+-03194 {
+-03196         dwc_otg_core_if_t *core_if;
+-03197         doepmsk_data_t intr_mask = {.d32 = 0 };
+-03198 
+-03199         DWC_PRINTF("INTERRUPT Handler not implemented for %s\n", "OUT EP NAK");
+-03200         core_if = GET_CORE_IF(pcd);
+-03201         intr_mask.b.nak = 1;
+-03202 
+-03203         if (core_if->multiproc_int_enable) {
+-03204                 dwc_modify_reg32(&core_if->dev_if->dev_global_regs->
+-03205                                  doepeachintmsk[epnum], intr_mask.d32, 0);
+-03206         } else {
+-03207                 dwc_modify_reg32(&core_if->dev_if->dev_global_regs->doepmsk,
+-03208                                  intr_mask.d32, 0);
+-03209         }
+-03210 
+-03211         return 1;
+-03212 }
+-03213 
+-03217 static inline int32_t handle_out_ep_nyet_intr(dwc_otg_pcd_t * pcd,
+-03218                                               const uint32_t epnum)
+-03219 {
+-03221         dwc_otg_core_if_t *core_if;
+-03222         doepmsk_data_t intr_mask = {.d32 = 0 };
+-03223 
+-03224         DWC_PRINTF("INTERRUPT Handler not implemented for %s\n", "OUT EP NYET");
+-03225         core_if = GET_CORE_IF(pcd);
+-03226         intr_mask.b.nyet = 1;
+-03227 
+-03228         if (core_if->multiproc_int_enable) {
+-03229                 dwc_modify_reg32(&core_if->dev_if->dev_global_regs->
+-03230                                  doepeachintmsk[epnum], intr_mask.d32, 0);
+-03231         } else {
+-03232                 dwc_modify_reg32(&core_if->dev_if->dev_global_regs->doepmsk,
+-03233                                  intr_mask.d32, 0);
+-03234         }
+-03235 
+-03236         return 1;
+-03237 }
+-03238 
+-03255 static int32_t dwc_otg_pcd_handle_in_ep_intr(dwc_otg_pcd_t * pcd)
+-03256 {
+-03257 #define CLEAR_IN_EP_INTR(__core_if,__epnum,__intr) \
+-03258 do { \
+-03259                 diepint_data_t diepint = {.d32=0}; \
+-03260                 diepint.b.__intr = 1; \
+-03261                 dwc_write_reg32(&__core_if->dev_if->in_ep_regs[__epnum]->diepint, \
+-03262                 diepint.d32); \
+-03263 } while (0)
+-03264 
+-03265         dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
+-03266         dwc_otg_dev_if_t *dev_if = core_if->dev_if;
+-03267         diepint_data_t diepint = {.d32 = 0 };
+-03268         dctl_data_t dctl = {.d32 = 0 };
+-03269         depctl_data_t depctl = {.d32 = 0 };
+-03270         uint32_t ep_intr;
+-03271         uint32_t epnum = 0;
+-03272         dwc_otg_pcd_ep_t *ep;
+-03273         dwc_ep_t *dwc_ep;
+-03274         gintmsk_data_t intr_mask = {.d32 = 0 };
+-03275 
+-03276         DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, pcd);
+-03277 
+-03278         /* Read in the device interrupt bits */
+-03279         ep_intr = dwc_otg_read_dev_all_in_ep_intr(core_if);
+-03280 
+-03281         /* Service the Device IN interrupts for each endpoint */
+-03282         while (ep_intr) {
+-03283                 if (ep_intr & 0x1) {
+-03284                         uint32_t empty_msk;
+-03285                         /* Get EP pointer */
+-03286                         ep = get_in_ep(pcd, epnum);
+-03287                         dwc_ep = &ep->dwc_ep;
+-03288 
+-03289                         depctl.d32 =
+-03290                             dwc_read_reg32(&dev_if->in_ep_regs[epnum]->diepctl);
+-03291                         empty_msk =
+-03292                             dwc_read_reg32(&dev_if->dev_global_regs->
+-03293                                            dtknqr4_fifoemptymsk);
+-03294 
+-03295                         DWC_DEBUGPL(DBG_PCDV,
+-03296                                     "IN EP INTERRUPT - %d\nepmty_msk - %8x  diepctl - %8x\n",
+-03297                                     epnum, empty_msk, depctl.d32);
+-03298 
+-03299                         DWC_DEBUGPL(DBG_PCD,
+-03300                                     "EP%d-%s: type=%d, mps=%d\n",
+-03301                                     dwc_ep->num, (dwc_ep->is_in ? "IN" : "OUT"),
+-03302                                     dwc_ep->type, dwc_ep->maxpacket);
+-03303 
+-03304                         diepint.d32 =
+-03305                             dwc_otg_read_dev_in_ep_intr(core_if, dwc_ep);
+-03306 
+-03307                         DWC_DEBUGPL(DBG_PCDV,
+-03308                                     "EP %d Interrupt Register - 0x%x\n", epnum,
+-03309                                     diepint.d32);
+-03310                         /* Transfer complete */
+-03311                         if (diepint.b.xfercompl) {
+-03312                                 /* Disable the NP Tx FIFO Empty
+-03313                                  * Interrrupt */
+-03314                                 if (core_if->en_multiple_tx_fifo == 0) {
+-03315                                         intr_mask.b.nptxfempty = 1;
+-03316                                         dwc_modify_reg32(&core_if->
+-03317                                                          core_global_regs->
+-03318                                                          gintmsk, intr_mask.d32,
+-03319                                                          0);
+-03320                                 } else {
+-03321                                         /* Disable the Tx FIFO Empty Interrupt for this EP */
+-03322                                         uint32_t fifoemptymsk =
+-03323                                             0x1 << dwc_ep->num;
+-03324                                         dwc_modify_reg32(&core_if->dev_if->
+-03325                                                          dev_global_regs->
+-03326                                                          dtknqr4_fifoemptymsk,
+-03327                                                          fifoemptymsk, 0);
+-03328                                 }
+-03329                                 /* Clear the bit in DIEPINTn for this interrupt */
+-03330                                 CLEAR_IN_EP_INTR(core_if, epnum, xfercompl);
+-03331 
+-03332                                 /* Complete the transfer */
+-03333                                 if (epnum == 0) {
+-03334                                         handle_ep0(pcd);
+-03335                                 }
+-03336 #ifdef DWC_EN_ISOC
+-03337                                 else if (dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) {
+-03338                                         if (!ep->stopped)
+-03339                                                 complete_iso_ep(pcd, ep);
+-03340                                 }
+-03341 #endif                          /* DWC_EN_ISOC */
+-03342                                 else {
+-03343 
+-03344                                         complete_ep(ep);
+-03345                                 }
+-03346                         }
+-03347                         /* Endpoint disable      */
+-03348                         if (diepint.b.epdisabled) {
+-03349                                 DWC_DEBUGPL(DBG_ANY, "EP%d IN disabled\n",
+-03350                                             epnum);
+-03351                                 handle_in_ep_disable_intr(pcd, epnum);
+-03352 
+-03353                                 /* Clear the bit in DIEPINTn for this interrupt */
+-03354                                 CLEAR_IN_EP_INTR(core_if, epnum, epdisabled);
+-03355                         }
+-03356                         /* AHB Error */
+-03357                         if (diepint.b.ahberr) {
+-03358                                 DWC_DEBUGPL(DBG_ANY, "EP%d IN AHB Error\n",
+-03359                                             epnum);
+-03360                                 /* Clear the bit in DIEPINTn for this interrupt */
+-03361                                 CLEAR_IN_EP_INTR(core_if, epnum, ahberr);
+-03362                         }
+-03363                         /* TimeOUT Handshake (non-ISOC IN EPs) */
+-03364                         if (diepint.b.timeout) {
+-03365                                 DWC_DEBUGPL(DBG_ANY, "EP%d IN Time-out\n",
+-03366                                             epnum);
+-03367                                 handle_in_ep_timeout_intr(pcd, epnum);
+-03368 
+-03369                                 CLEAR_IN_EP_INTR(core_if, epnum, timeout);
+-03370                         }
+-03372                         if (diepint.b.intktxfemp) {
+-03373                                 DWC_DEBUGPL(DBG_ANY,
+-03374                                             "EP%d IN TKN TxFifo Empty\n",
+-03375                                             epnum);
+-03376                                 if (!ep->stopped && epnum != 0) {
+-03377 
+-03378                                         diepmsk_data_t diepmsk = {.d32 = 0 };
+-03379                                         diepmsk.b.intktxfemp = 1;
+-03380 
+-03381                                         if (core_if->multiproc_int_enable) {
+-03382                                                 dwc_modify_reg32(&dev_if->
+-03383                                                                  dev_global_regs->
+-03384                                                                  diepeachintmsk
+-03385                                                                  [epnum],
+-03386                                                                  diepmsk.d32,
+-03387                                                                  0);
+-03388                                         } else {
+-03389                                                 dwc_modify_reg32(&dev_if->
+-03390                                                                  dev_global_regs->
+-03391                                                                  diepmsk,
+-03392                                                                  diepmsk.d32,
+-03393                                                                  0);
+-03394                                         }
+-03395                                 } else if (core_if->dma_desc_enable
+-03396                                            && epnum == 0
+-03397                                            && pcd->ep0state ==
+-03398                                            EP0_OUT_STATUS_PHASE) {
+-03399                                         // EP0 IN set STALL
+-03400                                         depctl.d32 =
+-03401                                             dwc_read_reg32(&dev_if->
+-03402                                                            in_ep_regs[epnum]->
+-03403                                                            diepctl);
+-03404 
+-03405                                         /* set the disable and stall bits */
+-03406                                         if (depctl.b.epena) {
+-03407                                                 depctl.b.epdis = 1;
+-03408                                         }
+-03409                                         depctl.b.stall = 1;
+-03410                                         dwc_write_reg32(&dev_if->
+-03411                                                         in_ep_regs[epnum]->
+-03412                                                         diepctl, depctl.d32);
+-03413                                 }
+-03414                                 CLEAR_IN_EP_INTR(core_if, epnum, intktxfemp);
+-03415                         }
+-03417                         if (diepint.b.intknepmis) {
+-03418                                 DWC_DEBUGPL(DBG_ANY,
+-03419                                             "EP%d IN TKN EP Mismatch\n", epnum);
+-03420                                 CLEAR_IN_EP_INTR(core_if, epnum, intknepmis);
+-03421                         }
+-03423                         if (diepint.b.inepnakeff) {
+-03424                                 DWC_DEBUGPL(DBG_ANY,
+-03425                                             "EP%d IN EP NAK Effective\n",
+-03426                                             epnum);
+-03427                                 /* Periodic EP */
+-03428                                 if (ep->disabling) {
+-03429                                         depctl.d32 = 0;
+-03430                                         depctl.b.snak = 1;
+-03431                                         depctl.b.epdis = 1;
+-03432                                         dwc_modify_reg32(&dev_if->
+-03433                                                          in_ep_regs[epnum]->
+-03434                                                          diepctl, depctl.d32,
+-03435                                                          depctl.d32);
+-03436                                 }
+-03437                                 CLEAR_IN_EP_INTR(core_if, epnum, inepnakeff);
+-03438 
+-03439                         }
+-03440 
+-03442                         if (diepint.b.emptyintr) {
+-03443                                 DWC_DEBUGPL(DBG_ANY,
+-03444                                             "EP%d Tx FIFO Empty Intr \n",
+-03445                                             epnum);
+-03446                                 write_empty_tx_fifo(pcd, epnum);
+-03447 
+-03448                                 CLEAR_IN_EP_INTR(core_if, epnum, emptyintr);
+-03449 
+-03450                         }
+-03451 
+-03453                         if (diepint.b.bna) {
+-03454                                 CLEAR_IN_EP_INTR(core_if, epnum, bna);
+-03455                                 if (core_if->dma_desc_enable) {
+-03456 #ifdef DWC_EN_ISOC
+-03457                                         if (dwc_ep->type ==
+-03458                                             DWC_OTG_EP_TYPE_ISOC) {
+-03459                                                 /*
+-03460                                                  * This checking is performed to prevent first "false" BNA 
+-03461                                                  * handling occuring right after reconnect 
+-03462                                                  */
+-03463                                                 if (dwc_ep->next_frame !=
+-03464                                                     0xffffffff)
+-03465                                                         dwc_otg_pcd_handle_iso_bna
+-03466                                                             (ep);
+-03467                                         } else
+-03468 #endif                          /* DWC_EN_ISOC */
+-03469                                         {
+-03470                                                 dctl.d32 =
+-03471                                                     dwc_read_reg32(&dev_if->
+-03472                                                                    dev_global_regs->
+-03473                                                                    dctl);
+-03474 
+-03475                                                 /* If Global Continue on BNA is disabled - disable EP */
+-03476                                                 if (!dctl.b.gcontbna) {
+-03477                                                         depctl.d32 = 0;
+-03478                                                         depctl.b.snak = 1;
+-03479                                                         depctl.b.epdis = 1;
+-03480                                                         dwc_modify_reg32
+-03481                                                             (&dev_if->
+-03482                                                              in_ep_regs[epnum]->
+-03483                                                              diepctl,
+-03484                                                              depctl.d32,
+-03485                                                              depctl.d32);
+-03486                                                 } else {
+-03487                                                         start_next_request(ep);
+-03488                                                 }
+-03489                                         }
+-03490                                 }
+-03491                         }
+-03492                         /* NAK Interrutp */
+-03493                         if (diepint.b.nak) {
+-03494                                 DWC_DEBUGPL(DBG_ANY, "EP%d IN NAK Interrupt\n",
+-03495                                             epnum);
+-03496                                 handle_in_ep_nak_intr(pcd, epnum);
+-03497 
+-03498                                 CLEAR_IN_EP_INTR(core_if, epnum, nak);
+-03499                         }
+-03500                 }
+-03501                 epnum++;
+-03502                 ep_intr >>= 1;
+-03503         }
+-03504 
+-03505         return 1;
+-03506 #undef CLEAR_IN_EP_INTR
+-03507 }
+-03508 
+-03522 static int32_t dwc_otg_pcd_handle_out_ep_intr(dwc_otg_pcd_t * pcd)
+-03523 {
+-03524 #define CLEAR_OUT_EP_INTR(__core_if,__epnum,__intr) \
+-03525 do { \
+-03526                 doepint_data_t doepint = {.d32=0}; \
+-03527                 doepint.b.__intr = 1; \
+-03528                 dwc_write_reg32(&__core_if->dev_if->out_ep_regs[__epnum]->doepint, \
+-03529                 doepint.d32); \
+-03530 } while (0)
+-03531 
+-03532         dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
+-03533         dwc_otg_dev_if_t *dev_if = core_if->dev_if;
+-03534         uint32_t ep_intr;
+-03535         doepint_data_t doepint = {.d32 = 0 };
+-03536         dctl_data_t dctl = {.d32 = 0 };
+-03537         depctl_data_t doepctl = {.d32 = 0 };
+-03538         uint32_t epnum = 0;
+-03539         dwc_otg_pcd_ep_t *ep;
+-03540         dwc_ep_t *dwc_ep;
+-03541 
+-03542         DWC_DEBUGPL(DBG_PCDV, "%s()\n", __func__);
+-03543 
+-03544         /* Read in the device interrupt bits */
+-03545         ep_intr = dwc_otg_read_dev_all_out_ep_intr(core_if);
+-03546 
+-03547         while (ep_intr) {
+-03548                 if (ep_intr & 0x1) {
+-03549                         /* Get EP pointer */
+-03550                         ep = get_out_ep(pcd, epnum);
+-03551                         dwc_ep = &ep->dwc_ep;
+-03552 
+-03553 #ifdef VERBOSE
+-03554                         DWC_DEBUGPL(DBG_PCDV,
+-03555                                     "EP%d-%s: type=%d, mps=%d\n",
+-03556                                     dwc_ep->num, (dwc_ep->is_in ? "IN" : "OUT"),
+-03557                                     dwc_ep->type, dwc_ep->maxpacket);
+-03558 #endif
+-03559                         doepint.d32 =
+-03560                             dwc_otg_read_dev_out_ep_intr(core_if, dwc_ep);
+-03561 
+-03562                         /* Transfer complete */
+-03563                         if (doepint.b.xfercompl) {
+-03564 
+-03565                                 if (epnum == 0) {
+-03566                                         /* Clear the bit in DOEPINTn for this interrupt */
+-03567                                         CLEAR_OUT_EP_INTR(core_if, epnum,
+-03568                                                           xfercompl);
+-03569                                         if (core_if->dma_desc_enable == 0
+-03570                                             || pcd->ep0state != EP0_IDLE)
+-03571                                                 handle_ep0(pcd);
+-03572 #ifdef DWC_EN_ISOC
+-03573                                 } else if (dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) {
+-03574                                         if (doepint.b.pktdrpsts == 0) {
+-03575                                                 /* Clear the bit in DOEPINTn for this interrupt */
+-03576                                                 CLEAR_OUT_EP_INTR(core_if,
+-03577                                                                   epnum,
+-03578                                                                   xfercompl);
+-03579                                                 complete_iso_ep(pcd, ep);
+-03580                                         } else {
+-03581 
+-03582                                                 doepint_data_t doepint = {.d32 =
+-03583                                                             0 };
+-03584                                                 doepint.b.xfercompl = 1;
+-03585                                                 doepint.b.pktdrpsts = 1;
+-03586                                                 dwc_write_reg32(&core_if->
+-03587                                                                 dev_if->
+-03588                                                                 out_ep_regs
+-03589                                                                 [epnum]->
+-03590                                                                 doepint,
+-03591                                                                 doepint.d32);
+-03592                                                 if (handle_iso_out_pkt_dropped
+-03593                                                     (core_if, dwc_ep)) {
+-03594                                                         complete_iso_ep(pcd,
+-03595                                                                         ep);
+-03596                                                 }
+-03597                                         }
+-03598 #endif                          /* DWC_EN_ISOC */
+-03599                                 } else {
+-03600                                         /* Clear the bit in DOEPINTn for this interrupt */
+-03601                                         CLEAR_OUT_EP_INTR(core_if, epnum,
+-03602                                                           xfercompl);
+-03603                                         complete_ep(ep);
+-03604                                 }
+-03605 
+-03606                         }
+-03607 
+-03608                         /* Endpoint disable      */
+-03609                         if (doepint.b.epdisabled) {
+-03610 
+-03611                                 /* Clear the bit in DOEPINTn for this interrupt */
+-03612                                 CLEAR_OUT_EP_INTR(core_if, epnum, epdisabled);
+-03613                         }
+-03614                         /* AHB Error */
+-03615                         if (doepint.b.ahberr) {
+-03616                                 DWC_DEBUGPL(DBG_PCD, "EP%d OUT AHB Error\n",
+-03617                                             epnum);
+-03618                                 DWC_DEBUGPL(DBG_PCD, "EP DMA REG         %d \n",
+-03619                                             core_if->dev_if->
+-03620                                             out_ep_regs[epnum]->doepdma);
+-03621                                 CLEAR_OUT_EP_INTR(core_if, epnum, ahberr);
+-03622                         }
+-03623                         /* Setup Phase Done (contorl EPs) */
+-03624                         if (doepint.b.setup) {
+-03625 #ifdef DEBUG_EP0
+-03626                                 DWC_DEBUGPL(DBG_PCD, "EP%d SETUP Done\n",
+-03627                                             epnum);
+-03628 #endif
+-03629                                 CLEAR_OUT_EP_INTR(core_if, epnum, setup);
+-03630 
+-03631                                 handle_ep0(pcd);
+-03632                         }
+-03633 
+-03635                         if (doepint.b.bna) {
+-03636                                 CLEAR_OUT_EP_INTR(core_if, epnum, bna);
+-03637                                 if (core_if->dma_desc_enable) {
+-03638 #ifdef DWC_EN_ISOC
+-03639                                         if (dwc_ep->type ==
+-03640                                             DWC_OTG_EP_TYPE_ISOC) {
+-03641                                                 /*
+-03642                                                  * This checking is performed to prevent first "false" BNA 
+-03643                                                  * handling occuring right after reconnect 
+-03644                                                  */
+-03645                                                 if (dwc_ep->next_frame !=
+-03646                                                     0xffffffff)
+-03647                                                         dwc_otg_pcd_handle_iso_bna
+-03648                                                             (ep);
+-03649                                         } else
+-03650 #endif                          /* DWC_EN_ISOC */
+-03651                                         {
+-03652                                                 dctl.d32 =
+-03653                                                     dwc_read_reg32(&dev_if->
+-03654                                                                    dev_global_regs->
+-03655                                                                    dctl);
+-03656 
+-03657                                                 /* If Global Continue on BNA is disabled - disable EP */
+-03658                                                 if (!dctl.b.gcontbna) {
+-03659                                                         doepctl.d32 = 0;
+-03660                                                         doepctl.b.snak = 1;
+-03661                                                         doepctl.b.epdis = 1;
+-03662                                                         dwc_modify_reg32
+-03663                                                             (&dev_if->
+-03664                                                              out_ep_regs
+-03665                                                              [epnum]->doepctl,
+-03666                                                              doepctl.d32,
+-03667                                                              doepctl.d32);
+-03668                                                 } else {
+-03669                                                         start_next_request(ep);
+-03670                                                 }
+-03671                                         }
+-03672                                 }
+-03673                         }
+-03674                         if (doepint.b.stsphsercvd) {
+-03675                                 CLEAR_OUT_EP_INTR(core_if, epnum, stsphsercvd);
+-03676                                 if (core_if->dma_desc_enable) {
+-03677                                         do_setup_in_status_phase(pcd);
+-03678                                 }
+-03679                         }
+-03680                         /* Babble Interrutp */
+-03681                         if (doepint.b.babble) {
+-03682                                 DWC_DEBUGPL(DBG_ANY, "EP%d OUT Babble\n",
+-03683                                             epnum);
+-03684                                 handle_out_ep_babble_intr(pcd, epnum);
+-03685 
+-03686                                 CLEAR_OUT_EP_INTR(core_if, epnum, babble);
+-03687                         }
+-03688                         /* NAK Interrutp */
+-03689                         if (doepint.b.nak) {
+-03690                                 DWC_DEBUGPL(DBG_ANY, "EP%d OUT NAK\n", epnum);
+-03691                                 handle_out_ep_nak_intr(pcd, epnum);
+-03692 
+-03693                                 CLEAR_OUT_EP_INTR(core_if, epnum, nak);
+-03694                         }
+-03695                         /* NYET Interrutp */
+-03696                         if (doepint.b.nyet) {
+-03697                                 DWC_DEBUGPL(DBG_ANY, "EP%d OUT NYET\n", epnum);
+-03698                                 handle_out_ep_nyet_intr(pcd, epnum);
+-03699 
+-03700                                 CLEAR_OUT_EP_INTR(core_if, epnum, nyet);
+-03701                         }
+-03702                 }
+-03703 
+-03704                 epnum++;
+-03705                 ep_intr >>= 1;
+-03706         }
+-03707 
+-03708         return 1;
+-03709 
+-03710 #undef CLEAR_OUT_EP_INTR
+-03711 }
+-03712 
+-03725 int32_t dwc_otg_pcd_handle_incomplete_isoc_in_intr(dwc_otg_pcd_t * pcd)
+-03726 {
+-03727         gintsts_data_t gintsts;
+-03728 
+-03729 #ifdef DWC_EN_ISOC
+-03730         dwc_otg_dev_if_t *dev_if;
+-03731         deptsiz_data_t deptsiz = {.d32 = 0 };
+-03732         depctl_data_t depctl = {.d32 = 0 };
+-03733         dsts_data_t dsts = {.d32 = 0 };
+-03734         dwc_ep_t *dwc_ep;
+-03735         int i;
+-03736 
+-03737         dev_if = GET_CORE_IF(pcd)->dev_if;
+-03738 
+-03739         for (i = 1; i <= dev_if->num_in_eps; ++i) {
+-03740                 dwc_ep = &pcd->in_ep[i].dwc_ep;
+-03741                 if (dwc_ep->active && dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) {
+-03742                         deptsiz.d32 =
+-03743                             dwc_read_reg32(&dev_if->in_ep_regs[i]->dieptsiz);
+-03744                         depctl.d32 =
+-03745                             dwc_read_reg32(&dev_if->in_ep_regs[i]->diepctl);
+-03746 
+-03747                         if (depctl.b.epdis && deptsiz.d32) {
+-03748                                 set_current_pkt_info(GET_CORE_IF(pcd), dwc_ep);
+-03749                                 if (dwc_ep->cur_pkt >= dwc_ep->pkt_cnt) {
+-03750                                         dwc_ep->cur_pkt = 0;
+-03751                                         dwc_ep->proc_buf_num =
+-03752                                             (dwc_ep->proc_buf_num ^ 1) & 0x1;
+-03753 
+-03754                                         if (dwc_ep->proc_buf_num) {
+-03755                                                 dwc_ep->cur_pkt_addr =
+-03756                                                     dwc_ep->xfer_buff1;
+-03757                                                 dwc_ep->cur_pkt_dma_addr =
+-03758                                                     dwc_ep->dma_addr1;
+-03759                                         } else {
+-03760                                                 dwc_ep->cur_pkt_addr =
+-03761                                                     dwc_ep->xfer_buff0;
+-03762                                                 dwc_ep->cur_pkt_dma_addr =
+-03763                                                     dwc_ep->dma_addr0;
+-03764                                         }
+-03765 
+-03766                                 }
+-03767 
+-03768                                 dsts.d32 =
+-03769                                     dwc_read_reg32(&GET_CORE_IF(pcd)->dev_if->
+-03770                                                    dev_global_regs->dsts);
+-03771                                 dwc_ep->next_frame = dsts.b.soffn;
+-03772 
+-03773                                 dwc_otg_iso_ep_start_frm_transfer(GET_CORE_IF
+-03774                                                                   (pcd),
+-03775                                                                   dwc_ep);
+-03776                         }
+-03777                 }
+-03778         }
+-03779 
+-03780 #else
+-03781         gintmsk_data_t intr_mask = {.d32 = 0 };
+-03782         DWC_PRINTF("INTERRUPT Handler not implemented for %s\n",
+-03783                    "IN ISOC Incomplete");
+-03784 
+-03785         intr_mask.b.incomplisoin = 1;
+-03786         dwc_modify_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk,
+-03787                          intr_mask.d32, 0);
+-03788 #endif                          //DWC_EN_ISOC
+-03789 
+-03790         /* Clear interrupt */
+-03791         gintsts.d32 = 0;
+-03792         gintsts.b.incomplisoin = 1;
+-03793         dwc_write_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
+-03794                         gintsts.d32);
+-03795 
+-03796         return 1;
+-03797 }
+-03798 
+-03814 int32_t dwc_otg_pcd_handle_incomplete_isoc_out_intr(dwc_otg_pcd_t * pcd)
+-03815 {
+-03816 
+-03817         gintsts_data_t gintsts;
+-03818 
+-03819 #ifdef DWC_EN_ISOC
+-03820         dwc_otg_dev_if_t *dev_if;
+-03821         deptsiz_data_t deptsiz = {.d32 = 0 };
+-03822         depctl_data_t depctl = {.d32 = 0 };
+-03823         dsts_data_t dsts = {.d32 = 0 };
+-03824         dwc_ep_t *dwc_ep;
+-03825         int i;
+-03826 
+-03827         dev_if = GET_CORE_IF(pcd)->dev_if;
+-03828 
+-03829         for (i = 1; i <= dev_if->num_out_eps; ++i) {
+-03830                 dwc_ep = &pcd->in_ep[i].dwc_ep;
+-03831                 if (pcd->out_ep[i].dwc_ep.active &&
+-03832                     pcd->out_ep[i].dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) {
+-03833                         deptsiz.d32 =
+-03834                             dwc_read_reg32(&dev_if->out_ep_regs[i]->doeptsiz);
+-03835                         depctl.d32 =
+-03836                             dwc_read_reg32(&dev_if->out_ep_regs[i]->doepctl);
+-03837 
+-03838                         if (depctl.b.epdis && deptsiz.d32) {
+-03839                                 set_current_pkt_info(GET_CORE_IF(pcd),
+-03840                                                      &pcd->out_ep[i].dwc_ep);
+-03841                                 if (dwc_ep->cur_pkt >= dwc_ep->pkt_cnt) {
+-03842                                         dwc_ep->cur_pkt = 0;
+-03843                                         dwc_ep->proc_buf_num =
+-03844                                             (dwc_ep->proc_buf_num ^ 1) & 0x1;
+-03845 
+-03846                                         if (dwc_ep->proc_buf_num) {
+-03847                                                 dwc_ep->cur_pkt_addr =
+-03848                                                     dwc_ep->xfer_buff1;
+-03849                                                 dwc_ep->cur_pkt_dma_addr =
+-03850                                                     dwc_ep->dma_addr1;
+-03851                                         } else {
+-03852                                                 dwc_ep->cur_pkt_addr =
+-03853                                                     dwc_ep->xfer_buff0;
+-03854                                                 dwc_ep->cur_pkt_dma_addr =
+-03855                                                     dwc_ep->dma_addr0;
+-03856                                         }
+-03857 
+-03858                                 }
+-03859 
+-03860                                 dsts.d32 =
+-03861                                     dwc_read_reg32(&GET_CORE_IF(pcd)->dev_if->
+-03862                                                    dev_global_regs->dsts);
+-03863                                 dwc_ep->next_frame = dsts.b.soffn;
+-03864 
+-03865                                 dwc_otg_iso_ep_start_frm_transfer(GET_CORE_IF
+-03866                                                                   (pcd),
+-03867                                                                   dwc_ep);
+-03868                         }
+-03869                 }
+-03870         }
+-03871 #else
+-03872 
+-03873         gintmsk_data_t intr_mask = {.d32 = 0 };
+-03874 
+-03875         DWC_PRINTF("INTERRUPT Handler not implemented for %s\n",
+-03876                    "OUT ISOC Incomplete");
+-03877 
+-03878         intr_mask.b.incomplisoout = 1;
+-03879         dwc_modify_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk,
+-03880                          intr_mask.d32, 0);
+-03881 
+-03882 #endif                          /* DWC_EN_ISOC */
+-03883 
+-03884         /* Clear interrupt */
+-03885         gintsts.d32 = 0;
+-03886         gintsts.b.incomplisoout = 1;
+-03887         dwc_write_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
+-03888                         gintsts.d32);
+-03889 
+-03890         return 1;
+-03891 }
+-03892 
+-03897 int32_t dwc_otg_pcd_handle_in_nak_effective(dwc_otg_pcd_t * pcd)
+-03898 {
+-03899         dwc_otg_dev_if_t *dev_if = GET_CORE_IF(pcd)->dev_if;
+-03900         depctl_data_t diepctl = {.d32 = 0 };
+-03901         depctl_data_t diepctl_rd = {.d32 = 0 };
+-03902         gintmsk_data_t intr_mask = {.d32 = 0 };
+-03903         gintsts_data_t gintsts;
+-03904         int i;
+-03905 
+-03906         DWC_DEBUGPL(DBG_PCD, "Global IN NAK Effective\n");
+-03907 
+-03908         /* Disable all active IN EPs */
+-03909         diepctl.b.epdis = 1;
+-03910         diepctl.b.snak = 1;
+-03911 
+-03912         for (i = 0; i <= dev_if->num_in_eps; i++) {
+-03913                 diepctl_rd.d32 =
+-03914                     dwc_read_reg32(&dev_if->in_ep_regs[i]->diepctl);
+-03915                 if (diepctl_rd.b.epena) {
+-03916                         dwc_write_reg32(&dev_if->in_ep_regs[i]->diepctl,
+-03917                                         diepctl.d32);
+-03918                 }
+-03919         }
+-03920         /* Disable the Global IN NAK Effective Interrupt */
+-03921         intr_mask.b.ginnakeff = 1;
+-03922         dwc_modify_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk,
+-03923                          intr_mask.d32, 0);
+-03924 
+-03925         /* Clear interrupt */
+-03926         gintsts.d32 = 0;
+-03927         gintsts.b.ginnakeff = 1;
+-03928         dwc_write_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
+-03929                         gintsts.d32);
+-03930 
+-03931         return 1;
+-03932 }
+-03933 
+-03938 int32_t dwc_otg_pcd_handle_out_nak_effective(dwc_otg_pcd_t * pcd)
+-03939 {
+-03940         gintmsk_data_t intr_mask = {.d32 = 0 };
+-03941         gintsts_data_t gintsts;
+-03942 
+-03943         DWC_PRINTF("INTERRUPT Handler not implemented for %s\n",
+-03944                    "Global IN NAK Effective\n");
+-03945         /* Disable the Global IN NAK Effective Interrupt */
+-03946         intr_mask.b.goutnakeff = 1;
+-03947         dwc_modify_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk,
+-03948                          intr_mask.d32, 0);
+-03949 
+-03950         /* Clear interrupt */
+-03951         gintsts.d32 = 0;
+-03952         gintsts.b.goutnakeff = 1;
+-03953         dwc_write_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
+-03954                         gintsts.d32);
+-03955 
+-03956         return 1;
+-03957 }
+-03958 
+-03971 int32_t dwc_otg_pcd_handle_intr(dwc_otg_pcd_t * pcd)
+-03972 {
+-03973         dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
+-03974 #ifdef VERBOSE
+-03975         dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
+-03976 #endif
+-03977         gintsts_data_t gintr_status;
+-03978         int32_t retval = 0;
+-03979 
+-03980 #ifdef VERBOSE
+-03981         DWC_DEBUGPL(DBG_ANY, "%s() gintsts=%08x  gintmsk=%08x\n",
+-03982                     __func__,
+-03983                     dwc_read_reg32(&global_regs->gintsts),
+-03984                     dwc_read_reg32(&global_regs->gintmsk));
+-03985 #endif
+-03986 
+-03987         if (dwc_otg_is_device_mode(core_if)) {
+-03988                 DWC_SPINLOCK(pcd->lock);
+-03989 #ifdef VERBOSE
+-03990                 DWC_DEBUGPL(DBG_PCDV, "%s() gintsts=%08x  gintmsk=%08x\n",
+-03991                             __func__,
+-03992                             dwc_read_reg32(&global_regs->gintsts),
+-03993                             dwc_read_reg32(&global_regs->gintmsk));
+-03994 #endif
+-03995 
+-03996                 gintr_status.d32 = dwc_otg_read_core_intr(core_if);
+-03997 
+-03998                 DWC_DEBUGPL(DBG_PCDV, "%s: gintsts&gintmsk=%08x\n",
+-03999                             __func__, gintr_status.d32);
+-04000 
+-04001                 if (gintr_status.b.sofintr) {
+-04002                         retval |= dwc_otg_pcd_handle_sof_intr(pcd);
+-04003                 }
+-04004                 if (gintr_status.b.rxstsqlvl) {
+-04005                         retval |=
+-04006                             dwc_otg_pcd_handle_rx_status_q_level_intr(pcd);
+-04007                 }
+-04008                 if (gintr_status.b.nptxfempty) {
+-04009                         retval |= dwc_otg_pcd_handle_np_tx_fifo_empty_intr(pcd);
+-04010                 }
+-04011                 if (gintr_status.b.ginnakeff) {
+-04012                         retval |= dwc_otg_pcd_handle_in_nak_effective(pcd);
+-04013                 }
+-04014                 if (gintr_status.b.goutnakeff) {
+-04015                         retval |= dwc_otg_pcd_handle_out_nak_effective(pcd);
+-04016                 }
+-04017                 if (gintr_status.b.i2cintr) {
+-04018                         retval |= dwc_otg_pcd_handle_i2c_intr(pcd);
+-04019                 }
+-04020                 if (gintr_status.b.erlysuspend) {
+-04021                         retval |= dwc_otg_pcd_handle_early_suspend_intr(pcd);
+-04022                 }
+-04023                 if (gintr_status.b.usbreset) {
+-04024                         retval |= dwc_otg_pcd_handle_usb_reset_intr(pcd);
+-04025                 }
+-04026                 if (gintr_status.b.enumdone) {
+-04027                         retval |= dwc_otg_pcd_handle_enum_done_intr(pcd);
+-04028                 }
+-04029                 if (gintr_status.b.isooutdrop) {
+-04030                         retval |=
+-04031                             dwc_otg_pcd_handle_isoc_out_packet_dropped_intr
+-04032                             (pcd);
+-04033                 }
+-04034                 if (gintr_status.b.eopframe) {
+-04035                         retval |=
+-04036                             dwc_otg_pcd_handle_end_periodic_frame_intr(pcd);
+-04037                 }
+-04038                 if (gintr_status.b.epmismatch) {
+-04039                         retval |= dwc_otg_pcd_handle_ep_mismatch_intr(core_if);
+-04040                 }
+-04041                 if (gintr_status.b.inepint) {
+-04042                         if (!core_if->multiproc_int_enable) {
+-04043                                 retval |= dwc_otg_pcd_handle_in_ep_intr(pcd);
+-04044                         }
+-04045                 }
+-04046                 if (gintr_status.b.outepintr) {
+-04047                         if (!core_if->multiproc_int_enable) {
+-04048                                 retval |= dwc_otg_pcd_handle_out_ep_intr(pcd);
+-04049                         }
+-04050                 }
+-04051                 if (gintr_status.b.incomplisoin) {
+-04052                         retval |=
+-04053                             dwc_otg_pcd_handle_incomplete_isoc_in_intr(pcd);
+-04054                 }
+-04055                 if (gintr_status.b.incomplisoout) {
+-04056                         retval |=
+-04057                             dwc_otg_pcd_handle_incomplete_isoc_out_intr(pcd);
+-04058                 }
+-04059 
+-04060                 /* In MPI mode De vice Endpoints intterrupts are asserted 
+-04061                  * without setting outepintr and inepint bits set, so these
+-04062                  * Interrupt handlers are called without checking these bit-fields
+-04063                  */
+-04064                 if (core_if->multiproc_int_enable) {
+-04065                         retval |= dwc_otg_pcd_handle_in_ep_intr(pcd);
+-04066                         retval |= dwc_otg_pcd_handle_out_ep_intr(pcd);
+-04067                 }
+-04068 #ifdef VERBOSE
+-04069                 DWC_DEBUGPL(DBG_PCDV, "%s() gintsts=%0x\n", __func__,
+-04070                             dwc_read_reg32(&global_regs->gintsts));
+-04071 #endif
+-04072                 DWC_SPINUNLOCK(pcd->lock);
+-04073         }
+-04074         return retval;
+-04075 }
+-04076 
+-04077 #endif                          /* DWC_HOST_ONLY */
+-
    Generated on Tue May 5 02:22:48 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++
    Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
    ++

    dwc_otg_pcd_intr.c

    Go to the documentation of this file.
    00001 /* ==========================================================================
++00002  * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_pcd_intr.c $
++00003  * $Revision: #113 $
++00004  * $Date: 2011/10/24 $
++00005  * $Change: 1871160 $
++00006  *
++00007  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
++00008  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
++00009  * otherwise expressly agreed to in writing between Synopsys and you.
++00010  *
++00011  * The Software IS NOT an item of Licensed Software or Licensed Product under
++00012  * any End User Software License Agreement or Agreement for Licensed Product
++00013  * with Synopsys or any supplement thereto. You are permitted to use and
++00014  * redistribute this Software in source and binary forms, with or without
++00015  * modification, provided that redistributions of source code must retain this
++00016  * notice. You may not view, use, disclose, copy or distribute this file or
++00017  * any information contained herein except pursuant to this license grant from
++00018  * Synopsys. If you do not agree with this notice, including the disclaimer
++00019  * below, then you are not authorized to use the Software.
++00020  *
++00021  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
++00022  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++00023  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++00024  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
++00025  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++00026  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
++00027  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
++00028  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
++00029  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
++00030  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
++00031  * DAMAGE.
++00032  * ========================================================================== */
++00033 #ifndef DWC_HOST_ONLY
++00034 
++00035 #include "dwc_otg_pcd.h"
++00036 
++00037 #ifdef DWC_UTE_CFI
++00038 #include "dwc_otg_cfi.h"
++00039 #endif
++00040 
++00041 #ifdef DWC_UTE_PER_IO
++00042 extern void complete_xiso_ep(dwc_otg_pcd_ep_t * ep);
++00043 #endif
++00044 //#define PRINT_CFI_DMA_DESCS
++00045 
++00046 #define DEBUG_EP0
++00047 
++00051 static void dwc_otg_pcd_update_otg(dwc_otg_pcd_t * pcd, const unsigned reset)
++00052 {
++00053 
++00054         if (reset) {
++00055                 pcd->b_hnp_enable = 0;
++00056                 pcd->a_hnp_support = 0;
++00057                 pcd->a_alt_hnp_support = 0;
++00058         }
++00059 
++00060         if (pcd->fops->hnp_changed) {
++00061                 pcd->fops->hnp_changed(pcd);
++00062         }
++00063 }
++00064 
++00079 static inline void print_ep0_state(dwc_otg_pcd_t * pcd)
++00080 {
++00081 #ifdef DEBUG
++00082         char str[40];
++00083 
++00084         switch (pcd->ep0state) {
++00085         case EP0_DISCONNECT:
++00086                 dwc_strcpy(str, "EP0_DISCONNECT");
++00087                 break;
++00088         case EP0_IDLE:
++00089                 dwc_strcpy(str, "EP0_IDLE");
++00090                 break;
++00091         case EP0_IN_DATA_PHASE:
++00092                 dwc_strcpy(str, "EP0_IN_DATA_PHASE");
++00093                 break;
++00094         case EP0_OUT_DATA_PHASE:
++00095                 dwc_strcpy(str, "EP0_OUT_DATA_PHASE");
++00096                 break;
++00097         case EP0_IN_STATUS_PHASE:
++00098                 dwc_strcpy(str, "EP0_IN_STATUS_PHASE");
++00099                 break;
++00100         case EP0_OUT_STATUS_PHASE:
++00101                 dwc_strcpy(str, "EP0_OUT_STATUS_PHASE");
++00102                 break;
++00103         case EP0_STALL:
++00104                 dwc_strcpy(str, "EP0_STALL");
++00105                 break;
++00106         default:
++00107                 dwc_strcpy(str, "EP0_INVALID");
++00108         }
++00109 
++00110         DWC_DEBUGPL(DBG_ANY, "%s(%d)\n", str, pcd->ep0state);
++00111 #endif
++00112 }
++00113 
++00119 static inline void print_memory_payload(dwc_otg_pcd_t * pcd,  dwc_ep_t * ep)
++00120 {
++00121 #ifdef DEBUG
++00122         deptsiz_data_t deptsiz_init = {.d32 = 0 };
++00123         deptsiz_data_t deptsiz_updt = {.d32 = 0 };
++00124         int pack_num;
++00125         unsigned payload;
++00126         
++00127         deptsiz_init.d32 = pcd->core_if->start_doeptsiz_val[ep->num];
++00128         deptsiz_updt.d32 =
++00129                 DWC_READ_REG32(&pcd->core_if->dev_if->
++00130                                                 out_ep_regs[ep->num]->doeptsiz);
++00131         /* Payload will be */
++00132         payload = deptsiz_init.b.xfersize - deptsiz_updt.b.xfersize;
++00133         /* Packet count is decremented every time a packet
++00134          * is written to the RxFIFO not in to the external memory
++00135          * So, if payload == 0, then it means no packet was sent to ext memory*/
++00136         pack_num = (!payload) ? 0 : (deptsiz_init.b.pktcnt - deptsiz_updt.b.pktcnt);
++00137         DWC_DEBUGPL(DBG_PCDV,
++00138                 "Payload for EP%d-%s\n",
++00139                 ep->num, (ep->is_in ? "IN" : "OUT"));
++00140         DWC_DEBUGPL(DBG_PCDV,
++00141                 "Number of transfered bytes = 0x%08x\n", payload);
++00142         DWC_DEBUGPL(DBG_PCDV,
++00143                 "Number of transfered packets = %d\n", pack_num);       
++00144 #endif  
++00145 }
++00146 
++00147 
++00148 #ifdef DWC_UTE_CFI
++00149 static inline void print_desc(struct dwc_otg_dma_desc *ddesc,
++00150                               const uint8_t * epname, int descnum)
++00151 {
++00152         CFI_INFO
++00153             ("%s DMA_DESC(%d) buf=0x%08x bytes=0x%04x; sp=0x%x; l=0x%x; sts=0x%02x; bs=0x%02x\n",
++00154              epname, descnum, ddesc->buf, ddesc->status.b.bytes,
++00155              ddesc->status.b.sp, ddesc->status.b.l, ddesc->status.b.sts,
++00156              ddesc->status.b.bs);
++00157 }
++00158 #endif
++00159 
++00163 static inline dwc_otg_pcd_ep_t *get_in_ep(dwc_otg_pcd_t * pcd, uint32_t ep_num)
++00164 {
++00165         int i;
++00166         int num_in_eps = GET_CORE_IF(pcd)->dev_if->num_in_eps;
++00167         if (ep_num == 0) {
++00168                 return &pcd->ep0;
++00169         } else {
++00170                 for (i = 0; i < num_in_eps; ++i) {
++00171                         if (pcd->in_ep[i].dwc_ep.num == ep_num)
++00172                                 return &pcd->in_ep[i];
++00173                 }
++00174                 return 0;
++00175         }
++00176 }
++00177 
++00181 static inline dwc_otg_pcd_ep_t *get_out_ep(dwc_otg_pcd_t * pcd, uint32_t ep_num)
++00182 {
++00183         int i;
++00184         int num_out_eps = GET_CORE_IF(pcd)->dev_if->num_out_eps;
++00185         if (ep_num == 0) {
++00186                 return &pcd->ep0;
++00187         } else {
++00188                 for (i = 0; i < num_out_eps; ++i) {
++00189                         if (pcd->out_ep[i].dwc_ep.num == ep_num)
++00190                                 return &pcd->out_ep[i];
++00191                 }
++00192                 return 0;
++00193         }
++00194 }
++00195 
++00200 dwc_otg_pcd_ep_t *get_ep_by_addr(dwc_otg_pcd_t * pcd, u16 wIndex)
++00201 {
++00202         dwc_otg_pcd_ep_t *ep;
++00203         uint32_t ep_num = UE_GET_ADDR(wIndex);
++00204 
++00205         if (ep_num == 0) {
++00206                 ep = &pcd->ep0;
++00207         } else if (UE_GET_DIR(wIndex) == UE_DIR_IN) {   /* in ep */
++00208                 ep = &pcd->in_ep[ep_num - 1];
++00209         } else {
++00210                 ep = &pcd->out_ep[ep_num - 1];
++00211         }
++00212 
++00213         return ep;
++00214 }
++00215 
++00220 void start_next_request(dwc_otg_pcd_ep_t * ep)
++00221 {
++00222         dwc_otg_pcd_request_t *req = 0;
++00223         uint32_t max_transfer =
++00224             GET_CORE_IF(ep->pcd)->core_params->max_transfer_size;
++00225 
++00226 #ifdef DWC_UTE_CFI
++00227         struct dwc_otg_pcd *pcd;
++00228         pcd = ep->pcd;
++00229 #endif
++00230 
++00231         if (!DWC_CIRCLEQ_EMPTY(&ep->queue)) {
++00232                 req = DWC_CIRCLEQ_FIRST(&ep->queue);
++00233 
++00234 #ifdef DWC_UTE_CFI
++00235                 if (ep->dwc_ep.buff_mode != BM_STANDARD) {
++00236                         ep->dwc_ep.cfi_req_len = req->length;
++00237                         pcd->cfi->ops.build_descriptors(pcd->cfi, pcd, ep, req);
++00238                 } else {
++00239 #endif
++00240                         /* Setup and start the Transfer */
++00241                         if (req->dw_align_buf) {
++00242                                 ep->dwc_ep.dma_addr = req->dw_align_buf_dma;
++00243                                 ep->dwc_ep.start_xfer_buff = req->dw_align_buf;
++00244                                 ep->dwc_ep.xfer_buff = req->dw_align_buf;
++00245                         } else {
++00246                                 ep->dwc_ep.dma_addr = req->dma;
++00247                                 ep->dwc_ep.start_xfer_buff = req->buf;
++00248                                 ep->dwc_ep.xfer_buff = req->buf;
++00249                         }
++00250                         ep->dwc_ep.sent_zlp = 0;
++00251                         ep->dwc_ep.total_len = req->length;
++00252                         ep->dwc_ep.xfer_len = 0;
++00253                         ep->dwc_ep.xfer_count = 0;
++00254 
++00255                         ep->dwc_ep.maxxfer = max_transfer;
++00256                         if (GET_CORE_IF(ep->pcd)->dma_desc_enable) {
++00257                                 uint32_t out_max_xfer = DDMA_MAX_TRANSFER_SIZE
++00258                                     - (DDMA_MAX_TRANSFER_SIZE % 4);
++00259                                 if (ep->dwc_ep.is_in) {
++00260                                         if (ep->dwc_ep.maxxfer >
++00261                                             DDMA_MAX_TRANSFER_SIZE) {
++00262                                                 ep->dwc_ep.maxxfer =
++00263                                                     DDMA_MAX_TRANSFER_SIZE;
++00264                                         }
++00265                                 } else {
++00266                                         if (ep->dwc_ep.maxxfer > out_max_xfer) {
++00267                                                 ep->dwc_ep.maxxfer =
++00268                                                     out_max_xfer;
++00269                                         }
++00270                                 }
++00271                         }
++00272                         if (ep->dwc_ep.maxxfer < ep->dwc_ep.total_len) {
++00273                                 ep->dwc_ep.maxxfer -=
++00274                                     (ep->dwc_ep.maxxfer % ep->dwc_ep.maxpacket);
++00275                         }
++00276                         if (req->sent_zlp) {
++00277                                 if ((ep->dwc_ep.total_len %
++00278                                      ep->dwc_ep.maxpacket == 0)
++00279                                     && (ep->dwc_ep.total_len != 0)) {
++00280                                         ep->dwc_ep.sent_zlp = 1;
++00281                                 }
++00282 
++00283                         }
++00284 #ifdef DWC_UTE_CFI
++00285                 }
++00286 #endif
++00287                 dwc_otg_ep_start_transfer(GET_CORE_IF(ep->pcd), &ep->dwc_ep);
++00288         } else if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) {
++00289                 DWC_PRINTF("There are no more ISOC requests \n");
++00290                 ep->dwc_ep.frame_num = 0xFFFFFFFF;
++00291         }
++00292 }
++00293 
++00298 int32_t dwc_otg_pcd_handle_sof_intr(dwc_otg_pcd_t * pcd)
++00299 {
++00300         dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
++00301 
++00302         gintsts_data_t gintsts;
++00303 
++00304         DWC_DEBUGPL(DBG_PCD, "SOF\n");
++00305 
++00306         /* Clear interrupt */
++00307         gintsts.d32 = 0;
++00308         gintsts.b.sofintr = 1;
++00309         DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
++00310 
++00311         return 1;
++00312 }
++00313 
++00331 int32_t dwc_otg_pcd_handle_rx_status_q_level_intr(dwc_otg_pcd_t * pcd)
++00332 {
++00333         dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
++00334         dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
++00335         gintmsk_data_t gintmask = {.d32 = 0 };
++00336         device_grxsts_data_t status;
++00337         dwc_otg_pcd_ep_t *ep;
++00338         gintsts_data_t gintsts;
++00339 #ifdef DEBUG
++00340         static char *dpid_str[] = { "D0", "D2", "D1", "MDATA" };
++00341 #endif
++00342 
++00343         //DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, _pcd);
++00344         /* Disable the Rx Status Queue Level interrupt */
++00345         gintmask.b.rxstsqlvl = 1;
++00346         DWC_MODIFY_REG32(&global_regs->gintmsk, gintmask.d32, 0);
++00347 
++00348         /* Get the Status from the top of the FIFO */
++00349         status.d32 = DWC_READ_REG32(&global_regs->grxstsp);
++00350 
++00351         DWC_DEBUGPL(DBG_PCD, "EP:%d BCnt:%d DPID:%s "
++00352                     "pktsts:%x Frame:%d(0x%0x)\n",
++00353                     status.b.epnum, status.b.bcnt,
++00354                     dpid_str[status.b.dpid],
++00355                     status.b.pktsts, status.b.fn, status.b.fn);
++00356         /* Get pointer to EP structure */
++00357         ep = get_out_ep(pcd, status.b.epnum);
++00358 
++00359         switch (status.b.pktsts) {
++00360         case DWC_DSTS_GOUT_NAK:
++00361                 DWC_DEBUGPL(DBG_PCDV, "Global OUT NAK\n");
++00362                 break;
++00363         case DWC_STS_DATA_UPDT:
++00364                 DWC_DEBUGPL(DBG_PCDV, "OUT Data Packet\n");
++00365                 if (status.b.bcnt && ep->dwc_ep.xfer_buff) {
++00367                         dwc_otg_read_packet(core_if,
++00368                                             ep->dwc_ep.xfer_buff,
++00369                                             status.b.bcnt);
++00370                         ep->dwc_ep.xfer_count += status.b.bcnt;
++00371                         ep->dwc_ep.xfer_buff += status.b.bcnt;
++00372                 }
++00373                 break;
++00374         case DWC_STS_XFER_COMP:
++00375                 DWC_DEBUGPL(DBG_PCDV, "OUT Complete\n");
++00376                 break;
++00377         case DWC_DSTS_SETUP_COMP:
++00378 #ifdef DEBUG_EP0
++00379                 DWC_DEBUGPL(DBG_PCDV, "Setup Complete\n");
++00380 #endif
++00381                 break;
++00382         case DWC_DSTS_SETUP_UPDT:
++00383                 dwc_otg_read_setup_packet(core_if, pcd->setup_pkt->d32);
++00384 #ifdef DEBUG_EP0
++00385                 DWC_DEBUGPL(DBG_PCD,
++00386                             "SETUP PKT: %02x.%02x v%04x i%04x l%04x\n",
++00387                             pcd->setup_pkt->req.bmRequestType,
++00388                             pcd->setup_pkt->req.bRequest,
++00389                             UGETW(pcd->setup_pkt->req.wValue),
++00390                             UGETW(pcd->setup_pkt->req.wIndex),
++00391                             UGETW(pcd->setup_pkt->req.wLength));
++00392 #endif
++00393                 ep->dwc_ep.xfer_count += status.b.bcnt;
++00394                 break;
++00395         default:
++00396                 DWC_DEBUGPL(DBG_PCDV, "Invalid Packet Status (0x%0x)\n",
++00397                             status.b.pktsts);
++00398                 break;
++00399         }
++00400 
++00401         /* Enable the Rx Status Queue Level interrupt */
++00402         DWC_MODIFY_REG32(&global_regs->gintmsk, 0, gintmask.d32);
++00403         /* Clear interrupt */
++00404         gintsts.d32 = 0;
++00405         gintsts.b.rxstsqlvl = 1;
++00406         DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
++00407 
++00408         //DWC_DEBUGPL(DBG_PCDV, "EXIT: %s\n", __func__);
++00409         return 1;
++00410 }
++00411 
++00424 static inline int get_ep_of_last_in_token(dwc_otg_core_if_t * core_if)
++00425 {
++00426         dwc_otg_device_global_regs_t *dev_global_regs =
++00427             core_if->dev_if->dev_global_regs;
++00428         const uint32_t TOKEN_Q_DEPTH = core_if->hwcfg2.b.dev_token_q_depth;
++00429         /* Number of Token Queue Registers */
++00430         const int DTKNQ_REG_CNT = (TOKEN_Q_DEPTH + 7) / 8;
++00431         dtknq1_data_t dtknqr1;
++00432         uint32_t in_tkn_epnums[4];
++00433         int ndx = 0;
++00434         int i = 0;
++00435         volatile uint32_t *addr = &dev_global_regs->dtknqr1;
++00436         int epnum = 0;
++00437 
++00438         //DWC_DEBUGPL(DBG_PCD,"dev_token_q_depth=%d\n",TOKEN_Q_DEPTH);
++00439 
++00440         /* Read the DTKNQ Registers */
++00441         for (i = 0; i < DTKNQ_REG_CNT; i++) {
++00442                 in_tkn_epnums[i] = DWC_READ_REG32(addr);
++00443                 DWC_DEBUGPL(DBG_PCDV, "DTKNQR%d=0x%08x\n", i + 1,
++00444                             in_tkn_epnums[i]);
++00445                 if (addr == &dev_global_regs->dvbusdis) {
++00446                         addr = &dev_global_regs->dtknqr3_dthrctl;
++00447                 } else {
++00448                         ++addr;
++00449                 }
++00450 
++00451         }
++00452 
++00453         /* Copy the DTKNQR1 data to the bit field. */
++00454         dtknqr1.d32 = in_tkn_epnums[0];
++00455         /* Get the EP numbers */
++00456         in_tkn_epnums[0] = dtknqr1.b.epnums0_5;
++00457         ndx = dtknqr1.b.intknwptr - 1;
++00458 
++00459         //DWC_DEBUGPL(DBG_PCDV,"ndx=%d\n",ndx);
++00460         if (ndx == -1) {
++00463                 int cnt = TOKEN_Q_DEPTH;
++00464                 if (TOKEN_Q_DEPTH <= 6) {
++00465                         cnt = TOKEN_Q_DEPTH - 1;
++00466                 } else if (TOKEN_Q_DEPTH <= 14) {
++00467                         cnt = TOKEN_Q_DEPTH - 7;
++00468                 } else if (TOKEN_Q_DEPTH <= 22) {
++00469                         cnt = TOKEN_Q_DEPTH - 15;
++00470                 } else {
++00471                         cnt = TOKEN_Q_DEPTH - 23;
++00472                 }
++00473                 epnum = (in_tkn_epnums[DTKNQ_REG_CNT - 1] >> (cnt * 4)) & 0xF;
++00474         } else {
++00475                 if (ndx <= 5) {
++00476                         epnum = (in_tkn_epnums[0] >> (ndx * 4)) & 0xF;
++00477                 } else if (ndx <= 13) {
++00478                         ndx -= 6;
++00479                         epnum = (in_tkn_epnums[1] >> (ndx * 4)) & 0xF;
++00480                 } else if (ndx <= 21) {
++00481                         ndx -= 14;
++00482                         epnum = (in_tkn_epnums[2] >> (ndx * 4)) & 0xF;
++00483                 } else if (ndx <= 29) {
++00484                         ndx -= 22;
++00485                         epnum = (in_tkn_epnums[3] >> (ndx * 4)) & 0xF;
++00486                 }
++00487         }
++00488         //DWC_DEBUGPL(DBG_PCD,"epnum=%d\n",epnum);
++00489         return epnum;
++00490 }
++00491 
++00497 int32_t dwc_otg_pcd_handle_np_tx_fifo_empty_intr(dwc_otg_pcd_t * pcd)
++00498 {
++00499         dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
++00500         dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
++00501         dwc_otg_dev_in_ep_regs_t *ep_regs;
++00502         gnptxsts_data_t txstatus = {.d32 = 0 };
++00503         gintsts_data_t gintsts;
++00504 
++00505         int epnum = 0;
++00506         dwc_otg_pcd_ep_t *ep = 0;
++00507         uint32_t len = 0;
++00508         int dwords;
++00509 
++00510         /* Get the epnum from the IN Token Learning Queue. */
++00511         epnum = get_ep_of_last_in_token(core_if);
++00512         ep = get_in_ep(pcd, epnum);
++00513 
++00514         DWC_DEBUGPL(DBG_PCD, "NP TxFifo Empty: %d \n", epnum);
++00515 
++00516         ep_regs = core_if->dev_if->in_ep_regs[epnum];
++00517 
++00518         len = ep->dwc_ep.xfer_len - ep->dwc_ep.xfer_count;
++00519         if (len > ep->dwc_ep.maxpacket) {
++00520                 len = ep->dwc_ep.maxpacket;
++00521         }
++00522         dwords = (len + 3) / 4;
++00523 
++00524         /* While there is space in the queue and space in the FIFO and
++00525          * More data to tranfer, Write packets to the Tx FIFO */
++00526         txstatus.d32 = DWC_READ_REG32(&global_regs->gnptxsts);
++00527         DWC_DEBUGPL(DBG_PCDV, "b4 GNPTXSTS=0x%08x\n", txstatus.d32);
++00528 
++00529         while (txstatus.b.nptxqspcavail > 0 &&
++00530                txstatus.b.nptxfspcavail > dwords &&
++00531                ep->dwc_ep.xfer_count < ep->dwc_ep.xfer_len) {
++00532                 /* Write the FIFO */
++00533                 dwc_otg_ep_write_packet(core_if, &ep->dwc_ep, 0);
++00534                 len = ep->dwc_ep.xfer_len - ep->dwc_ep.xfer_count;
++00535 
++00536                 if (len > ep->dwc_ep.maxpacket) {
++00537                         len = ep->dwc_ep.maxpacket;
++00538                 }
++00539 
++00540                 dwords = (len + 3) / 4;
++00541                 txstatus.d32 = DWC_READ_REG32(&global_regs->gnptxsts);
++00542                 DWC_DEBUGPL(DBG_PCDV, "GNPTXSTS=0x%08x\n", txstatus.d32);
++00543         }
++00544 
++00545         DWC_DEBUGPL(DBG_PCDV, "GNPTXSTS=0x%08x\n",
++00546                     DWC_READ_REG32(&global_regs->gnptxsts));
++00547 
++00548         /* Clear interrupt */
++00549         gintsts.d32 = 0;
++00550         gintsts.b.nptxfempty = 1;
++00551         DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
++00552 
++00553         return 1;
++00554 }
++00555 
++00561 static int32_t write_empty_tx_fifo(dwc_otg_pcd_t * pcd, uint32_t epnum)
++00562 {
++00563         dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
++00564         dwc_otg_dev_if_t *dev_if = core_if->dev_if;
++00565         dwc_otg_dev_in_ep_regs_t *ep_regs;
++00566         dtxfsts_data_t txstatus = {.d32 = 0 };
++00567         dwc_otg_pcd_ep_t *ep = 0;
++00568         uint32_t len = 0;
++00569         int dwords;
++00570 
++00571         ep = get_in_ep(pcd, epnum);
++00572 
++00573         DWC_DEBUGPL(DBG_PCD, "Dedicated TxFifo Empty: %d \n", epnum);
++00574 
++00575         ep_regs = core_if->dev_if->in_ep_regs[epnum];
++00576 
++00577         len = ep->dwc_ep.xfer_len - ep->dwc_ep.xfer_count;
++00578 
++00579         if (len > ep->dwc_ep.maxpacket) {
++00580                 len = ep->dwc_ep.maxpacket;
++00581         }
++00582 
++00583         dwords = (len + 3) / 4;
++00584 
++00585         /* While there is space in the queue and space in the FIFO and
++00586          * More data to tranfer, Write packets to the Tx FIFO */
++00587         txstatus.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->dtxfsts);
++00588         DWC_DEBUGPL(DBG_PCDV, "b4 dtxfsts[%d]=0x%08x\n", epnum, txstatus.d32);
++00589 
++00590         while (txstatus.b.txfspcavail > dwords &&
++00591                ep->dwc_ep.xfer_count < ep->dwc_ep.xfer_len &&
++00592                ep->dwc_ep.xfer_len != 0) {
++00593                 /* Write the FIFO */
++00594                 dwc_otg_ep_write_packet(core_if, &ep->dwc_ep, 0);
++00595 
++00596                 len = ep->dwc_ep.xfer_len - ep->dwc_ep.xfer_count;
++00597                 if (len > ep->dwc_ep.maxpacket) {
++00598                         len = ep->dwc_ep.maxpacket;
++00599                 }
++00600 
++00601                 dwords = (len + 3) / 4;
++00602                 txstatus.d32 =
++00603                     DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->dtxfsts);
++00604                 DWC_DEBUGPL(DBG_PCDV, "dtxfsts[%d]=0x%08x\n", epnum,
++00605                             txstatus.d32);
++00606         }
++00607 
++00608         DWC_DEBUGPL(DBG_PCDV, "b4 dtxfsts[%d]=0x%08x\n", epnum,
++00609                     DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->dtxfsts));
++00610 
++00611         return 1;
++00612 }
++00613 
++00619 void dwc_otg_pcd_stop(dwc_otg_pcd_t * pcd)
++00620 {
++00621         int i, num_in_eps, num_out_eps;
++00622         dwc_otg_pcd_ep_t *ep;
++00623 
++00624         gintmsk_data_t intr_mask = {.d32 = 0 };
++00625 
++00626         DWC_SPINLOCK(pcd->lock);
++00627 
++00628         num_in_eps = GET_CORE_IF(pcd)->dev_if->num_in_eps;
++00629         num_out_eps = GET_CORE_IF(pcd)->dev_if->num_out_eps;
++00630 
++00631         DWC_DEBUGPL(DBG_PCDV, "%s() \n", __func__);
++00632         /* don't disconnect drivers more than once */
++00633         if (pcd->ep0state == EP0_DISCONNECT) {
++00634                 DWC_DEBUGPL(DBG_ANY, "%s() Already Disconnected\n", __func__);
++00635                 DWC_SPINUNLOCK(pcd->lock);
++00636                 return;
++00637         }
++00638         pcd->ep0state = EP0_DISCONNECT;
++00639 
++00640         /* Reset the OTG state. */
++00641         dwc_otg_pcd_update_otg(pcd, 1);
++00642 
++00643         /* Disable the NP Tx Fifo Empty Interrupt. */
++00644         intr_mask.b.nptxfempty = 1;
++00645         DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk,
++00646                          intr_mask.d32, 0);
++00647 
++00648         /* Flush the FIFOs */
++00650         dwc_otg_flush_tx_fifo(GET_CORE_IF(pcd), 0x10);
++00651         dwc_otg_flush_rx_fifo(GET_CORE_IF(pcd));
++00652 
++00653         /* prevent new request submissions, kill any outstanding requests  */
++00654         ep = &pcd->ep0;
++00655         dwc_otg_request_nuke(ep);
++00656         /* prevent new request submissions, kill any outstanding requests  */
++00657         for (i = 0; i < num_in_eps; i++) {
++00658                 dwc_otg_pcd_ep_t *ep = &pcd->in_ep[i];
++00659                 dwc_otg_request_nuke(ep);
++00660         }
++00661         /* prevent new request submissions, kill any outstanding requests  */
++00662         for (i = 0; i < num_out_eps; i++) {
++00663                 dwc_otg_pcd_ep_t *ep = &pcd->out_ep[i];
++00664                 dwc_otg_request_nuke(ep);
++00665         }
++00666 
++00667         /* report disconnect; the driver is already quiesced */
++00668         if (pcd->fops->disconnect) {
++00669                 DWC_SPINUNLOCK(pcd->lock);
++00670                 pcd->fops->disconnect(pcd);
++00671                 DWC_SPINLOCK(pcd->lock);
++00672         }
++00673         DWC_SPINUNLOCK(pcd->lock);
++00674 }
++00675 
++00679 int32_t dwc_otg_pcd_handle_i2c_intr(dwc_otg_pcd_t * pcd)
++00680 {
++00681         gintmsk_data_t intr_mask = {.d32 = 0 };
++00682         gintsts_data_t gintsts;
++00683 
++00684         DWC_PRINTF("INTERRUPT Handler not implemented for %s\n", "i2cintr");
++00685         intr_mask.b.i2cintr = 1;
++00686         DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk,
++00687                          intr_mask.d32, 0);
++00688 
++00689         /* Clear interrupt */
++00690         gintsts.d32 = 0;
++00691         gintsts.b.i2cintr = 1;
++00692         DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
++00693                         gintsts.d32);
++00694         return 1;
++00695 }
++00696 
++00700 int32_t dwc_otg_pcd_handle_early_suspend_intr(dwc_otg_pcd_t * pcd)
++00701 {
++00702         gintsts_data_t gintsts;
++00703 #if defined(VERBOSE)
++00704         DWC_PRINTF("Early Suspend Detected\n");
++00705 #endif
++00706 
++00707         /* Clear interrupt */
++00708         gintsts.d32 = 0;
++00709         gintsts.b.erlysuspend = 1;
++00710         DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
++00711                         gintsts.d32);
++00712         return 1;
++00713 }
++00714 
++00732 static inline void ep0_out_start(dwc_otg_core_if_t * core_if,
++00733                                  dwc_otg_pcd_t * pcd)
++00734 {
++00735         dwc_otg_dev_if_t *dev_if = core_if->dev_if;
++00736         deptsiz0_data_t doeptsize0 = {.d32 = 0 };
++00737         dwc_otg_dev_dma_desc_t *dma_desc;
++00738         depctl_data_t doepctl = {.d32 = 0 };
++00739 
++00740 #ifdef VERBOSE
++00741         DWC_DEBUGPL(DBG_PCDV, "%s() doepctl0=%0x\n", __func__,
++00742                     DWC_READ_REG32(&dev_if->out_ep_regs[0]->doepctl));
++00743 #endif
++00744 
++00745         doeptsize0.b.supcnt = 3;
++00746         doeptsize0.b.pktcnt = 1;
++00747         doeptsize0.b.xfersize = 8 * 3;
++00748 
++00749         if (core_if->dma_enable) {
++00750                 if (!core_if->dma_desc_enable) {
++00752                         DWC_WRITE_REG32(&dev_if->out_ep_regs[0]->doeptsiz,
++00753                                         doeptsize0.d32);
++00754 
++00756                         DWC_WRITE_REG32(&dev_if->out_ep_regs[0]->doepdma,
++00757                                         pcd->setup_pkt_dma_handle);
++00758                 } else {
++00759                         dev_if->setup_desc_index =
++00760                             (dev_if->setup_desc_index + 1) & 1;
++00761                         dma_desc =
++00762                             dev_if->setup_desc_addr[dev_if->setup_desc_index];
++00763 
++00765                         dma_desc->status.b.bs = BS_HOST_BUSY;
++00766                         dma_desc->status.b.l = 1;
++00767                         dma_desc->status.b.ioc = 1;
++00768                         dma_desc->status.b.bytes = pcd->ep0.dwc_ep.maxpacket;
++00769                         dma_desc->buf = pcd->setup_pkt_dma_handle;
++00770                         dma_desc->status.b.sts = 0;
++00771                         dma_desc->status.b.bs = BS_HOST_READY;
++00772 
++00774                         DWC_WRITE_REG32(&dev_if->out_ep_regs[0]->doepdma,
++00775                                         dev_if->
++00776                                         dma_setup_desc_addr
++00777                                         [dev_if->setup_desc_index]);
++00778                 }
++00779 
++00780         } else {
++00782                 DWC_WRITE_REG32(&dev_if->out_ep_regs[0]->doeptsiz,
++00783                                 doeptsize0.d32);
++00784         }
++00785 
++00787         doepctl.b.epena = 1;
++00788         doepctl.b.cnak = 1;
++00789         DWC_WRITE_REG32(&dev_if->out_ep_regs[0]->doepctl, doepctl.d32);
++00790 
++00791 #ifdef VERBOSE
++00792         DWC_DEBUGPL(DBG_PCDV, "doepctl0=%0x\n",
++00793                     DWC_READ_REG32(&dev_if->out_ep_regs[0]->doepctl));
++00794         DWC_DEBUGPL(DBG_PCDV, "diepctl0=%0x\n",
++00795                     DWC_READ_REG32(&dev_if->in_ep_regs[0]->diepctl));
++00796 #endif
++00797 }
++00798 
++00822 int32_t dwc_otg_pcd_handle_usb_reset_intr(dwc_otg_pcd_t * pcd)
++00823 {
++00824         dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
++00825         dwc_otg_dev_if_t *dev_if = core_if->dev_if;
++00826         depctl_data_t doepctl = {.d32 = 0 };
++00827         depctl_data_t diepctl = {.d32 = 0 };
++00828         daint_data_t daintmsk = {.d32 = 0 };
++00829         doepmsk_data_t doepmsk = {.d32 = 0 };
++00830         diepmsk_data_t diepmsk = {.d32 = 0 };
++00831         dcfg_data_t dcfg = {.d32 = 0 };
++00832         grstctl_t resetctl = {.d32 = 0 };
++00833         dctl_data_t dctl = {.d32 = 0 };
++00834         int i = 0;
++00835         gintsts_data_t gintsts;
++00836         pcgcctl_data_t power = {.d32 = 0 };
++00837 
++00838         power.d32 = DWC_READ_REG32(core_if->pcgcctl);
++00839         if (power.b.stoppclk) {
++00840                 power.d32 = 0;
++00841                 power.b.stoppclk = 1;
++00842                 DWC_MODIFY_REG32(core_if->pcgcctl, power.d32, 0);
++00843 
++00844                 power.b.pwrclmp = 1;
++00845                 DWC_MODIFY_REG32(core_if->pcgcctl, power.d32, 0);
++00846 
++00847                 power.b.rstpdwnmodule = 1;
++00848                 DWC_MODIFY_REG32(core_if->pcgcctl, power.d32, 0);
++00849         }
++00850 
++00851         core_if->lx_state = DWC_OTG_L0;
++00852 
++00853         DWC_PRINTF("USB RESET\n");
++00854 #ifdef DWC_EN_ISOC
++00855         for (i = 1; i < 16; ++i) {
++00856                 dwc_otg_pcd_ep_t *ep;
++00857                 dwc_ep_t *dwc_ep;
++00858                 ep = get_in_ep(pcd, i);
++00859                 if (ep != 0) {
++00860                         dwc_ep = &ep->dwc_ep;
++00861                         dwc_ep->next_frame = 0xffffffff;
++00862                 }
++00863         }
++00864 #endif /* DWC_EN_ISOC */
++00865 
++00866         /* reset the HNP settings */
++00867         dwc_otg_pcd_update_otg(pcd, 1);
++00868 
++00869         /* Clear the Remote Wakeup Signalling */
++00870         dctl.b.rmtwkupsig = 1;
++00871         DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32, 0);
++00872 
++00873         /* Set NAK for all OUT EPs */
++00874         doepctl.b.snak = 1;
++00875         for (i = 0; i <= dev_if->num_out_eps; i++) {
++00876                 DWC_WRITE_REG32(&dev_if->out_ep_regs[i]->doepctl, doepctl.d32);
++00877         }
++00878 
++00879         /* Flush the NP Tx FIFO */
++00880         dwc_otg_flush_tx_fifo(core_if, 0x10);
++00881         /* Flush the Learning Queue */
++00882         resetctl.b.intknqflsh = 1;
++00883         DWC_WRITE_REG32(&core_if->core_global_regs->grstctl, resetctl.d32);
++00884 
++00885         if (!core_if->core_params->en_multiple_tx_fifo && core_if->dma_enable) {
++00886                 core_if->start_predict = 0;
++00887                 for (i = 0; i<= core_if->dev_if->num_in_eps; ++i) {
++00888                         core_if->nextep_seq[i] = 0xff;  // 0xff - EP not active
++00889                 }
++00890                 core_if->nextep_seq[0] = 0;     
++00891                 core_if->first_in_nextep_seq = 0;
++00892                 diepctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[0]->diepctl);
++00893                 diepctl.b.nextep = 0;
++00894                 DWC_WRITE_REG32(&dev_if->in_ep_regs[0]->diepctl, diepctl.d32);
++00895                 
++00896                 /* Update IN Endpoint Mismatch Count by active IN NP EP count + 1 */
++00897                 dcfg.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->dcfg);
++00898                 dcfg.b.epmscnt = 2;
++00899                 DWC_WRITE_REG32(&dev_if->dev_global_regs->dcfg, dcfg.d32);
++00900 
++00901                 DWC_DEBUGPL(DBG_PCDV,"%s first_in_nextep_seq= %2d; nextep_seq[]:\n", 
++00902                         __func__, core_if->first_in_nextep_seq);
++00903                 for (i=0; i <= core_if->dev_if->num_in_eps; i++) {
++00904                         DWC_DEBUGPL(DBG_PCDV, "%2d\n", core_if->nextep_seq[i]);
++00905                 }
++00906         }
++00907 
++00908         if (core_if->multiproc_int_enable) {
++00909                 daintmsk.b.inep0 = 1;
++00910                 daintmsk.b.outep0 = 1;
++00911                 DWC_WRITE_REG32(&dev_if->dev_global_regs->deachintmsk,
++00912                                 daintmsk.d32);
++00913 
++00914                 doepmsk.b.setup = 1;
++00915                 doepmsk.b.xfercompl = 1;
++00916                 doepmsk.b.ahberr = 1;
++00917                 doepmsk.b.epdisabled = 1;
++00918 
++00919                 if (core_if->dma_desc_enable) {
++00920                         doepmsk.b.stsphsercvd = 1;
++00921                         doepmsk.b.bna = 1;
++00922                 }
++00923 /*              
++00924                 doepmsk.b.babble = 1;
++00925                 doepmsk.b.nyet = 1;
++00926                 
++00927                 if (core_if->dma_enable) {
++00928                         doepmsk.b.nak = 1;
++00929                 }
++00930 */
++00931                 DWC_WRITE_REG32(&dev_if->dev_global_regs->doepeachintmsk[0],
++00932                                 doepmsk.d32);
++00933 
++00934                 diepmsk.b.xfercompl = 1;
++00935                 diepmsk.b.timeout = 1;
++00936                 diepmsk.b.epdisabled = 1;
++00937                 diepmsk.b.ahberr = 1;
++00938                 diepmsk.b.intknepmis = 1; 
++00939                 if (!core_if->en_multiple_tx_fifo && core_if->dma_enable)
++00940                         diepmsk.b.intknepmis = 0; 
++00941 
++00942 /*              if (core_if->dma_desc_enable) {
++00943                         diepmsk.b.bna = 1;
++00944                 }
++00945 */
++00946 /*              
++00947                 if (core_if->dma_enable) {
++00948                         diepmsk.b.nak = 1;
++00949                 }
++00950 */
++00951                 DWC_WRITE_REG32(&dev_if->dev_global_regs->diepeachintmsk[0],
++00952                                 diepmsk.d32);
++00953         } else {
++00954                 daintmsk.b.inep0 = 1;
++00955                 daintmsk.b.outep0 = 1;
++00956                 DWC_WRITE_REG32(&dev_if->dev_global_regs->daintmsk,
++00957                                 daintmsk.d32);
++00958 
++00959                 doepmsk.b.setup = 1;
++00960                 doepmsk.b.xfercompl = 1;
++00961                 doepmsk.b.ahberr = 1;
++00962                 doepmsk.b.epdisabled = 1;
++00963 
++00964                 if (core_if->dma_desc_enable) {
++00965                         doepmsk.b.stsphsercvd = 1;
++00966                         doepmsk.b.bna = 1;
++00967                 }
++00968                 DWC_WRITE_REG32(&dev_if->dev_global_regs->doepmsk, doepmsk.d32);
++00969 
++00970                 diepmsk.b.xfercompl = 1;
++00971                 diepmsk.b.timeout = 1;
++00972                 diepmsk.b.epdisabled = 1;
++00973                 diepmsk.b.ahberr = 1;
++00974                 if (!core_if->en_multiple_tx_fifo && core_if->dma_enable)
++00975                         diepmsk.b.intknepmis = 0; 
++00976 /*
++00977                 if (core_if->dma_desc_enable) {
++00978                         diepmsk.b.bna = 1;
++00979                 }
++00980 */
++00981 
++00982                 DWC_WRITE_REG32(&dev_if->dev_global_regs->diepmsk, diepmsk.d32);
++00983         }
++00984 
++00985         /* Reset Device Address */
++00986         dcfg.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->dcfg);
++00987         dcfg.b.devaddr = 0;
++00988         DWC_WRITE_REG32(&dev_if->dev_global_regs->dcfg, dcfg.d32);
++00989 
++00990         /* setup EP0 to receive SETUP packets */
++00991         ep0_out_start(core_if, pcd);
++00992 
++00993         /* Clear interrupt */
++00994         gintsts.d32 = 0;
++00995         gintsts.b.usbreset = 1;
++00996         DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
++00997 
++00998         return 1;
++00999 }
++01000 
++01007 static int get_device_speed(dwc_otg_core_if_t * core_if)
++01008 {
++01009         dsts_data_t dsts;
++01010         int speed = 0;
++01011         dsts.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts);
++01012 
++01013         switch (dsts.b.enumspd) {
++01014         case DWC_DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ:
++01015                 speed = USB_SPEED_HIGH;
++01016                 break;
++01017         case DWC_DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ:
++01018         case DWC_DSTS_ENUMSPD_FS_PHY_48MHZ:
++01019                 speed = USB_SPEED_FULL;
++01020                 break;
++01021 
++01022         case DWC_DSTS_ENUMSPD_LS_PHY_6MHZ:
++01023                 speed = USB_SPEED_LOW;
++01024                 break;
++01025         }
++01026 
++01027         return speed;
++01028 }
++01029 
++01035 int32_t dwc_otg_pcd_handle_enum_done_intr(dwc_otg_pcd_t * pcd)
++01036 {
++01037         dwc_otg_pcd_ep_t *ep0 = &pcd->ep0;
++01038         gintsts_data_t gintsts;
++01039         gusbcfg_data_t gusbcfg;
++01040         dwc_otg_core_global_regs_t *global_regs =
++01041             GET_CORE_IF(pcd)->core_global_regs;
++01042         uint8_t utmi16b, utmi8b;
++01043         int speed;
++01044         DWC_DEBUGPL(DBG_PCD, "SPEED ENUM\n");
++01045 
++01046         if (GET_CORE_IF(pcd)->snpsid >= OTG_CORE_REV_2_60a) {
++01047                 utmi16b = 6;    //vahrama old value was 6;
++01048                 utmi8b = 9;
++01049         } else {
++01050                 utmi16b = 4;
++01051                 utmi8b = 8;
++01052         }
++01053         dwc_otg_ep0_activate(GET_CORE_IF(pcd), &ep0->dwc_ep);
++01054 
++01055 #ifdef DEBUG_EP0
++01056         print_ep0_state(pcd);
++01057 #endif
++01058 
++01059         if (pcd->ep0state == EP0_DISCONNECT) {
++01060                 pcd->ep0state = EP0_IDLE;
++01061         } else if (pcd->ep0state == EP0_STALL) {
++01062                 pcd->ep0state = EP0_IDLE;
++01063         }
++01064 
++01065         pcd->ep0state = EP0_IDLE;
++01066 
++01067         ep0->stopped = 0;
++01068 
++01069         speed = get_device_speed(GET_CORE_IF(pcd));
++01070         pcd->fops->connect(pcd, speed);
++01071 
++01072         /* Set USB turnaround time based on device speed and PHY interface. */
++01073         gusbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg);
++01074         if (speed == USB_SPEED_HIGH) {
++01075                 if (GET_CORE_IF(pcd)->hwcfg2.b.hs_phy_type ==
++01076                     DWC_HWCFG2_HS_PHY_TYPE_ULPI) {
++01077                         /* ULPI interface */
++01078                         gusbcfg.b.usbtrdtim = 9;
++01079                 }
++01080                 if (GET_CORE_IF(pcd)->hwcfg2.b.hs_phy_type ==
++01081                     DWC_HWCFG2_HS_PHY_TYPE_UTMI) {
++01082                         /* UTMI+ interface */
++01083                         if (GET_CORE_IF(pcd)->hwcfg4.b.utmi_phy_data_width == 0) {
++01084                                 gusbcfg.b.usbtrdtim = utmi8b;
++01085                         } else if (GET_CORE_IF(pcd)->hwcfg4.
++01086                                    b.utmi_phy_data_width == 1) {
++01087                                 gusbcfg.b.usbtrdtim = utmi16b;
++01088                         } else if (GET_CORE_IF(pcd)->
++01089                                    core_params->phy_utmi_width == 8) {
++01090                                 gusbcfg.b.usbtrdtim = utmi8b;
++01091                         } else {
++01092                                 gusbcfg.b.usbtrdtim = utmi16b;
++01093                         }
++01094                 }
++01095                 if (GET_CORE_IF(pcd)->hwcfg2.b.hs_phy_type ==
++01096                     DWC_HWCFG2_HS_PHY_TYPE_UTMI_ULPI) {
++01097                         /* UTMI+  OR  ULPI interface */
++01098                         if (gusbcfg.b.ulpi_utmi_sel == 1) {
++01099                                 /* ULPI interface */
++01100                                 gusbcfg.b.usbtrdtim = 9;
++01101                         } else {
++01102                                 /* UTMI+ interface */
++01103                                 if (GET_CORE_IF(pcd)->
++01104                                     core_params->phy_utmi_width == 16) {
++01105                                         gusbcfg.b.usbtrdtim = utmi16b;
++01106                                 } else {
++01107                                         gusbcfg.b.usbtrdtim = utmi8b;
++01108                                 }
++01109                         }
++01110                 }
++01111         } else {
++01112                 /* Full or low speed */
++01113                 gusbcfg.b.usbtrdtim = 9;
++01114         }
++01115         DWC_WRITE_REG32(&global_regs->gusbcfg, gusbcfg.d32);
++01116 
++01117         /* Clear interrupt */
++01118         gintsts.d32 = 0;
++01119         gintsts.b.enumdone = 1;
++01120         DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
++01121                         gintsts.d32);
++01122         return 1;
++01123 }
++01124 
++01130 int32_t dwc_otg_pcd_handle_isoc_out_packet_dropped_intr(dwc_otg_pcd_t * pcd)
++01131 {
++01132         gintmsk_data_t intr_mask = {.d32 = 0 };
++01133         gintsts_data_t gintsts;
++01134 
++01135         DWC_WARN("INTERRUPT Handler not implemented for %s\n",
++01136                  "ISOC Out Dropped");
++01137 
++01138         intr_mask.b.isooutdrop = 1;
++01139         DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk,
++01140                          intr_mask.d32, 0);
++01141 
++01142         /* Clear interrupt */
++01143         gintsts.d32 = 0;
++01144         gintsts.b.isooutdrop = 1;
++01145         DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
++01146                         gintsts.d32);
++01147 
++01148         return 1;
++01149 }
++01150 
++01156 int32_t dwc_otg_pcd_handle_end_periodic_frame_intr(dwc_otg_pcd_t * pcd)
++01157 {
++01158         gintmsk_data_t intr_mask = {.d32 = 0 };
++01159         gintsts_data_t gintsts;
++01160         DWC_PRINTF("INTERRUPT Handler not implemented for %s\n", "EOP");
++01161 
++01162         intr_mask.b.eopframe = 1;
++01163         DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk,
++01164                          intr_mask.d32, 0);
++01165 
++01166         /* Clear interrupt */
++01167         gintsts.d32 = 0;
++01168         gintsts.b.eopframe = 1;
++01169         DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
++01170                         gintsts.d32);
++01171 
++01172         return 1;
++01173 }
++01174 
++01184 int32_t dwc_otg_pcd_handle_ep_mismatch_intr(dwc_otg_pcd_t * pcd)
++01185 {
++01186         gintsts_data_t gintsts;
++01187         dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
++01188         dctl_data_t dctl;
++01189         gintmsk_data_t intr_mask = {.d32 = 0 };
++01190 
++01191         if (!core_if->en_multiple_tx_fifo && core_if->dma_enable) {
++01192                 core_if->start_predict = 1;
++01193         
++01194                 DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, core_if);
++01195         
++01196                 gintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts);
++01197                 if (!gintsts.b.ginnakeff) {
++01198                         /* Disable EP Mismatch interrupt */
++01199                         intr_mask.d32 = 0;
++01200                         intr_mask.b.epmismatch = 1;
++01201                         DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, intr_mask.d32, 0);
++01202                         /* Enable the Global IN NAK Effective Interrupt */
++01203                         intr_mask.d32 = 0;
++01204                         intr_mask.b.ginnakeff = 1;
++01205                         DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, 0, intr_mask.d32);
++01206                         /* Set the global non-periodic IN NAK handshake */
++01207                         dctl.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dctl);
++01208                         dctl.b.sgnpinnak = 1;
++01209                         DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32);
++01210                 } else {
++01211                         DWC_PRINTF("gintsts.b.ginnakeff = 1! dctl.b.sgnpinnak not set\n");
++01212                 }
++01213                 /* Disabling of all EP's will be done in dwc_otg_pcd_handle_in_nak_effective()
++01214                  * handler after Global IN NAK Effective interrupt will be asserted */
++01215         }
++01216         /* Clear interrupt */
++01217         gintsts.d32 = 0;
++01218         gintsts.b.epmismatch = 1;
++01219         DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
++01220 
++01221         return 1;
++01222 }
++01223 
++01232 int32_t dwc_otg_pcd_handle_ep_fetsusp_intr(dwc_otg_pcd_t * pcd)
++01233 {
++01234         gintsts_data_t gintsts;
++01235         gintmsk_data_t gintmsk_data;
++01236         dctl_data_t dctl;
++01237         dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
++01238         DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, core_if);
++01239         
++01240         /* Clear the global non-periodic IN NAK handshake */
++01241         dctl.d32 = 0;
++01242         dctl.b.cgnpinnak = 1;
++01243         DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32, dctl.d32); 
++01244         
++01245         /* Mask GINTSTS.FETSUSP interrupt */
++01246         gintmsk_data.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintmsk);
++01247         gintmsk_data.b.fetsusp = 0;
++01248         DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, gintmsk_data.d32);
++01249 
++01250         /* Clear interrupt */
++01251         gintsts.d32 = 0;
++01252         gintsts.b.fetsusp = 1;
++01253         DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
++01254 
++01255         return 1;
++01256 }
++01260 static inline void ep0_do_stall(dwc_otg_pcd_t * pcd, const int err_val)
++01261 {
++01262         dwc_otg_pcd_ep_t *ep0 = &pcd->ep0;
++01263         usb_device_request_t *ctrl = &pcd->setup_pkt->req;
++01264         DWC_WARN("req %02x.%02x protocol STALL; err %d\n",
++01265                  ctrl->bmRequestType, ctrl->bRequest, err_val);
++01266 
++01267         ep0->dwc_ep.is_in = 1;
++01268         dwc_otg_ep_set_stall(GET_CORE_IF(pcd), &ep0->dwc_ep);
++01269         pcd->ep0.stopped = 1;
++01270         pcd->ep0state = EP0_IDLE;
++01271         ep0_out_start(GET_CORE_IF(pcd), pcd);
++01272 }
++01273 
++01277 static inline void do_gadget_setup(dwc_otg_pcd_t * pcd,
++01278                                    usb_device_request_t * ctrl)
++01279 {
++01280         int ret = 0;
++01281         DWC_SPINUNLOCK(pcd->lock);
++01282         ret = pcd->fops->setup(pcd, (uint8_t *) ctrl);
++01283         DWC_SPINLOCK(pcd->lock);
++01284         if (ret < 0) {
++01285                 ep0_do_stall(pcd, ret);
++01286         }
++01287 
++01300         if (ret == 256 + 999) {
++01301                 pcd->request_config = 1;
++01302         }
++01303 }
++01304 
++01305 #ifdef DWC_UTE_CFI
++01306 
++01310 static inline int cfi_gadget_setup(dwc_otg_pcd_t * pcd,
++01311                                    struct cfi_usb_ctrlrequest *ctrl_req)
++01312 {
++01313         int ret = 0;
++01314 
++01315         if (pcd->fops && pcd->fops->cfi_setup) {
++01316                 DWC_SPINUNLOCK(pcd->lock);
++01317                 ret = pcd->fops->cfi_setup(pcd, ctrl_req);
++01318                 DWC_SPINLOCK(pcd->lock);
++01319                 if (ret < 0) {
++01320                         ep0_do_stall(pcd, ret);
++01321                         return ret;
++01322                 }
++01323         }
++01324 
++01325         return ret;
++01326 }
++01327 #endif
++01328 
++01333 static inline void do_setup_in_status_phase(dwc_otg_pcd_t * pcd)
++01334 {
++01335         dwc_otg_pcd_ep_t *ep0 = &pcd->ep0;
++01336         if (pcd->ep0state == EP0_STALL) {
++01337                 return;
++01338         }
++01339 
++01340         pcd->ep0state = EP0_IN_STATUS_PHASE;
++01341 
++01342         /* Prepare for more SETUP Packets */
++01343         DWC_DEBUGPL(DBG_PCD, "EP0 IN ZLP\n");
++01344         ep0->dwc_ep.xfer_len = 0;
++01345         ep0->dwc_ep.xfer_count = 0;
++01346         ep0->dwc_ep.is_in = 1;
++01347         ep0->dwc_ep.dma_addr = pcd->setup_pkt_dma_handle;
++01348         dwc_otg_ep0_start_transfer(GET_CORE_IF(pcd), &ep0->dwc_ep);
++01349 
++01350         /* Prepare for more SETUP Packets */
++01351         //ep0_out_start(GET_CORE_IF(pcd), pcd);
++01352 }
++01353 
++01358 static inline void do_setup_out_status_phase(dwc_otg_pcd_t * pcd)
++01359 {
++01360         dwc_otg_pcd_ep_t *ep0 = &pcd->ep0;
++01361         if (pcd->ep0state == EP0_STALL) {
++01362                 DWC_DEBUGPL(DBG_PCD, "EP0 STALLED\n");
++01363                 return;
++01364         }
++01365         pcd->ep0state = EP0_OUT_STATUS_PHASE;
++01366 
++01367         DWC_DEBUGPL(DBG_PCD, "EP0 OUT ZLP\n");
++01368         ep0->dwc_ep.xfer_len = 0;
++01369         ep0->dwc_ep.xfer_count = 0;
++01370         ep0->dwc_ep.is_in = 0;
++01371         ep0->dwc_ep.dma_addr = pcd->setup_pkt_dma_handle;
++01372         dwc_otg_ep0_start_transfer(GET_CORE_IF(pcd), &ep0->dwc_ep);
++01373 
++01374         /* Prepare for more SETUP Packets */
++01375         if (GET_CORE_IF(pcd)->dma_enable == 0) {
++01376                 ep0_out_start(GET_CORE_IF(pcd), pcd);
++01377         }
++01378 }
++01379 
++01384 static inline void pcd_clear_halt(dwc_otg_pcd_t * pcd, dwc_otg_pcd_ep_t * ep)
++01385 {
++01386         if (ep->dwc_ep.stall_clear_flag == 0)
++01387                 dwc_otg_ep_clear_stall(GET_CORE_IF(pcd), &ep->dwc_ep);
++01388 
++01389         /* Reactive the EP */
++01390         dwc_otg_ep_activate(GET_CORE_IF(pcd), &ep->dwc_ep);
++01391         if (ep->stopped) {
++01392                 ep->stopped = 0;
++01393                 /* If there is a request in the EP queue start it */
++01394 
++01398                 /*
++01399                  * Above fixme is solved by implmenting a tasklet to call the
++01400                  * start_next_request(), outside of interrupt context at some
++01401                  * time after the current time, after a clear-halt setup packet.
++01402                  * Still need to implement ep mismatch in the future if a gadget
++01403                  * ever uses more than one endpoint at once
++01404                  */
++01405                 ep->queue_sof = 1;
++01406                 DWC_TASK_SCHEDULE(pcd->start_xfer_tasklet);
++01407         }
++01408         /* Start Control Status Phase */
++01409         do_setup_in_status_phase(pcd);
++01410 }
++01411 
++01423 void do_test_mode(void *data)
++01424 {
++01425         dctl_data_t dctl;
++01426         dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *) data;
++01427         dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
++01428         int test_mode = pcd->test_mode;
++01429 
++01430 //        DWC_WARN("%s() has not been tested since being rewritten!\n", __func__);
++01431 
++01432         dctl.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dctl);
++01433         switch (test_mode) {
++01434         case 1:         // TEST_J
++01435                 dctl.b.tstctl = 1;
++01436                 break;
++01437 
++01438         case 2:         // TEST_K
++01439                 dctl.b.tstctl = 2;
++01440                 break;
++01441 
++01442         case 3:         // TEST_SE0_NAK
++01443                 dctl.b.tstctl = 3;
++01444                 break;
++01445 
++01446         case 4:         // TEST_PACKET
++01447                 dctl.b.tstctl = 4;
++01448                 break;
++01449 
++01450         case 5:         // TEST_FORCE_ENABLE
++01451                 dctl.b.tstctl = 5;
++01452                 break;
++01453         }
++01454         DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32);
++01455 }
++01456 
++01460 static inline void do_get_status(dwc_otg_pcd_t * pcd)
++01461 {
++01462         usb_device_request_t ctrl = pcd->setup_pkt->req;
++01463         dwc_otg_pcd_ep_t *ep;
++01464         dwc_otg_pcd_ep_t *ep0 = &pcd->ep0;
++01465         uint16_t *status = pcd->status_buf;
++01466         dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
++01467 
++01468 #ifdef DEBUG_EP0
++01469         DWC_DEBUGPL(DBG_PCD,
++01470                     "GET_STATUS %02x.%02x v%04x i%04x l%04x\n",
++01471                     ctrl.bmRequestType, ctrl.bRequest,
++01472                     UGETW(ctrl.wValue), UGETW(ctrl.wIndex),
++01473                     UGETW(ctrl.wLength));
++01474 #endif
++01475 
++01476         switch (UT_GET_RECIPIENT(ctrl.bmRequestType)) {
++01477         case UT_DEVICE:
++01478                 if(UGETW(ctrl.wIndex) == 0xF000) { /* OTG Status selector */
++01479                         DWC_PRINTF("wIndex - %d\n", UGETW(ctrl.wIndex));
++01480                         DWC_PRINTF("OTG VERSION - %d\n", core_if->otg_ver);
++01481                         DWC_PRINTF("OTG CAP - %d, %d\n", core_if->core_params->otg_cap,
++01482                                                 DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE);
++01483                         if(core_if->otg_ver == 1 && 
++01484                         core_if->core_params->otg_cap == DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE) {
++01485                                 uint8_t *otgsts = (uint8_t*)pcd->status_buf;
++01486                                 *otgsts = (core_if->otg_sts & 0x1);
++01487                                 pcd->ep0_pending = 1;
++01488                                 ep0->dwc_ep.start_xfer_buff = (uint8_t *) otgsts;
++01489                                 ep0->dwc_ep.xfer_buff = (uint8_t *) otgsts;
++01490                                 ep0->dwc_ep.dma_addr = pcd->status_buf_dma_handle;
++01491                                 ep0->dwc_ep.xfer_len = 1;
++01492                                 ep0->dwc_ep.xfer_count = 0;
++01493                                 ep0->dwc_ep.total_len = ep0->dwc_ep.xfer_len;
++01494                                 dwc_otg_ep0_start_transfer(GET_CORE_IF(pcd), &ep0->dwc_ep);
++01495                                 return;
++01496                         } else {
++01497                                 ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED);
++01498                                 return;
++01499                         }
++01500                         break;
++01501                 } else {
++01502                         *status = 0x1;  /* Self powered */
++01503                         *status |= pcd->remote_wakeup_enable << 1;
++01504                         break;
++01505                 }
++01506         case UT_INTERFACE:
++01507                 *status = 0;
++01508                 break;
++01509 
++01510         case UT_ENDPOINT:
++01511                 ep = get_ep_by_addr(pcd, UGETW(ctrl.wIndex));
++01512                 if (ep == 0 || UGETW(ctrl.wLength) > 2) {
++01513                         ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED);
++01514                         return;
++01515                 }
++01517                 *status = ep->stopped;
++01518                 break;
++01519         }
++01520         pcd->ep0_pending = 1;
++01521         ep0->dwc_ep.start_xfer_buff = (uint8_t *) status;
++01522         ep0->dwc_ep.xfer_buff = (uint8_t *) status;
++01523         ep0->dwc_ep.dma_addr = pcd->status_buf_dma_handle;
++01524         ep0->dwc_ep.xfer_len = 2;
++01525         ep0->dwc_ep.xfer_count = 0;
++01526         ep0->dwc_ep.total_len = ep0->dwc_ep.xfer_len;
++01527         dwc_otg_ep0_start_transfer(GET_CORE_IF(pcd), &ep0->dwc_ep);
++01528 }
++01529 
++01533 static inline void do_set_feature(dwc_otg_pcd_t * pcd)
++01534 {
++01535         dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
++01536         dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
++01537         usb_device_request_t ctrl = pcd->setup_pkt->req;
++01538         dwc_otg_pcd_ep_t *ep = 0;
++01539         int32_t otg_cap_param = core_if->core_params->otg_cap;
++01540         gotgctl_data_t gotgctl = {.d32 = 0 };
++01541 
++01542         DWC_DEBUGPL(DBG_PCD, "SET_FEATURE:%02x.%02x v%04x i%04x l%04x\n",
++01543                     ctrl.bmRequestType, ctrl.bRequest,
++01544                     UGETW(ctrl.wValue), UGETW(ctrl.wIndex),
++01545                     UGETW(ctrl.wLength));
++01546         DWC_DEBUGPL(DBG_PCD, "otg_cap=%d\n", otg_cap_param);
++01547 
++01548         switch (UT_GET_RECIPIENT(ctrl.bmRequestType)) {
++01549         case UT_DEVICE:
++01550                 switch (UGETW(ctrl.wValue)) {
++01551                 case UF_DEVICE_REMOTE_WAKEUP:
++01552                         pcd->remote_wakeup_enable = 1;
++01553                         break;
++01554 
++01555                 case UF_TEST_MODE:
++01556                         /* Setup the Test Mode tasklet to do the Test
++01557                          * Packet generation after the SETUP Status
++01558                          * phase has completed. */
++01559 
++01563                         pcd->test_mode = UGETW(ctrl.wIndex) >> 8;
++01564                         DWC_TASK_SCHEDULE(pcd->test_mode_tasklet);
++01565                         break;
++01566 
++01567                 case UF_DEVICE_B_HNP_ENABLE:
++01568                         DWC_DEBUGPL(DBG_PCDV,
++01569                                     "SET_FEATURE: USB_DEVICE_B_HNP_ENABLE\n");
++01570 
++01571                         /* dev may initiate HNP */
++01572                         if (otg_cap_param == DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE) {
++01573                                 pcd->b_hnp_enable = 1;
++01574                                 dwc_otg_pcd_update_otg(pcd, 0);
++01575                                 DWC_DEBUGPL(DBG_PCD, "Request B HNP\n");
++01578                                 gotgctl.b.devhnpen = 1;
++01579                                 gotgctl.b.hnpreq = 1;
++01580                                 DWC_WRITE_REG32(&global_regs->gotgctl,
++01581                                                 gotgctl.d32);
++01582                         } else {
++01583                                 ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED);
++01584                                 return;
++01585                         }
++01586                         break;
++01587 
++01588                 case UF_DEVICE_A_HNP_SUPPORT:
++01589                         /* RH port supports HNP */
++01590                         DWC_DEBUGPL(DBG_PCDV,
++01591                                     "SET_FEATURE: USB_DEVICE_A_HNP_SUPPORT\n");
++01592                         if (otg_cap_param == DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE) {
++01593                                 pcd->a_hnp_support = 1;
++01594                                 dwc_otg_pcd_update_otg(pcd, 0);
++01595                         } else {
++01596                                 ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED);
++01597                                 return;
++01598                         }
++01599                         break;
++01600 
++01601                 case UF_DEVICE_A_ALT_HNP_SUPPORT:
++01602                         /* other RH port does */
++01603                         DWC_DEBUGPL(DBG_PCDV,
++01604                                     "SET_FEATURE: USB_DEVICE_A_ALT_HNP_SUPPORT\n");
++01605                         if (otg_cap_param == DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE) {
++01606                                 pcd->a_alt_hnp_support = 1;
++01607                                 dwc_otg_pcd_update_otg(pcd, 0);
++01608                         } else {
++01609                                 ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED);
++01610                                 return;
++01611                         }
++01612                         break;
++01613 
++01614                 default:
++01615                         ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED);
++01616                         return;
++01617 
++01618                 }
++01619                 do_setup_in_status_phase(pcd);
++01620                 break;
++01621 
++01622         case UT_INTERFACE:
++01623                 do_gadget_setup(pcd, &ctrl);
++01624                 break;
++01625 
++01626         case UT_ENDPOINT:
++01627                 if (UGETW(ctrl.wValue) == UF_ENDPOINT_HALT) {
++01628                         ep = get_ep_by_addr(pcd, UGETW(ctrl.wIndex));
++01629                         if (ep == 0) {
++01630                                 ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED);
++01631                                 return;
++01632                         }
++01633                         ep->stopped = 1;
++01634                         dwc_otg_ep_set_stall(core_if, &ep->dwc_ep);
++01635                 }
++01636                 do_setup_in_status_phase(pcd);
++01637                 break;
++01638         }
++01639 }
++01640 
++01644 static inline void do_clear_feature(dwc_otg_pcd_t * pcd)
++01645 {
++01646         usb_device_request_t ctrl = pcd->setup_pkt->req;
++01647         dwc_otg_pcd_ep_t *ep = 0;
++01648 
++01649         DWC_DEBUGPL(DBG_PCD,
++01650                     "CLEAR_FEATURE:%02x.%02x v%04x i%04x l%04x\n",
++01651                     ctrl.bmRequestType, ctrl.bRequest,
++01652                     UGETW(ctrl.wValue), UGETW(ctrl.wIndex),
++01653                     UGETW(ctrl.wLength));
++01654 
++01655         switch (UT_GET_RECIPIENT(ctrl.bmRequestType)) {
++01656         case UT_DEVICE:
++01657                 switch (UGETW(ctrl.wValue)) {
++01658                 case UF_DEVICE_REMOTE_WAKEUP:
++01659                         pcd->remote_wakeup_enable = 0;
++01660                         break;
++01661 
++01662                 case UF_TEST_MODE:
++01664                         break;
++01665 
++01666                 default:
++01667                         ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED);
++01668                         return;
++01669                 }
++01670                 do_setup_in_status_phase(pcd);
++01671                 break;
++01672 
++01673         case UT_ENDPOINT:
++01674                 ep = get_ep_by_addr(pcd, UGETW(ctrl.wIndex));
++01675                 if (ep == 0) {
++01676                         ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED);
++01677                         return;
++01678                 }
++01679 
++01680                 pcd_clear_halt(pcd, ep);
++01681 
++01682                 break;
++01683         }
++01684 }
++01685 
++01689 static inline void do_set_address(dwc_otg_pcd_t * pcd)
++01690 {
++01691         dwc_otg_dev_if_t *dev_if = GET_CORE_IF(pcd)->dev_if;
++01692         usb_device_request_t ctrl = pcd->setup_pkt->req;
++01693 
++01694         if (ctrl.bmRequestType == UT_DEVICE) {
++01695                 dcfg_data_t dcfg = {.d32 = 0 };
++01696 
++01697 #ifdef DEBUG_EP0
++01698 //                      DWC_DEBUGPL(DBG_PCDV, "SET_ADDRESS:%d\n", ctrl.wValue);
++01699 #endif
++01700                 dcfg.b.devaddr = UGETW(ctrl.wValue);
++01701                 DWC_MODIFY_REG32(&dev_if->dev_global_regs->dcfg, 0, dcfg.d32);
++01702                 do_setup_in_status_phase(pcd);
++01703         }
++01704 }
++01705 
++01756 static inline void pcd_setup(dwc_otg_pcd_t * pcd)
++01757 {
++01758         dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
++01759         dwc_otg_dev_if_t *dev_if = core_if->dev_if;
++01760         usb_device_request_t ctrl = pcd->setup_pkt->req;
++01761         dwc_otg_pcd_ep_t *ep0 = &pcd->ep0;
++01762 
++01763         deptsiz0_data_t doeptsize0 = {.d32 = 0 };
++01764 
++01765 #ifdef DWC_UTE_CFI
++01766         int retval = 0;
++01767         struct cfi_usb_ctrlrequest cfi_req;
++01768 #endif
++01769 
++01770 #ifdef DEBUG_EP0
++01771         DWC_DEBUGPL(DBG_PCD, "SETUP %02x.%02x v%04x i%04x l%04x\n",
++01772                     ctrl.bmRequestType, ctrl.bRequest,
++01773                     UGETW(ctrl.wValue), UGETW(ctrl.wIndex),
++01774                     UGETW(ctrl.wLength));
++01775 #endif
++01776 
++01777         doeptsize0.d32 = DWC_READ_REG32(&dev_if->out_ep_regs[0]->doeptsiz);
++01778 
++01781         if (core_if->dma_enable && core_if->dma_desc_enable == 0
++01782             && (doeptsize0.b.supcnt < 2)) {
++01783                 DWC_ERROR
++01784                     ("\n\n-----------    CANNOT handle > 1 setup packet in DMA mode\n\n");
++01785         }
++01786 
++01787         /* Clean up the request queue */
++01788         dwc_otg_request_nuke(ep0);
++01789         ep0->stopped = 0;
++01790 
++01791         if (ctrl.bmRequestType & UE_DIR_IN) {
++01792                 ep0->dwc_ep.is_in = 1;
++01793                 pcd->ep0state = EP0_IN_DATA_PHASE;
++01794         } else {
++01795                 ep0->dwc_ep.is_in = 0;
++01796                 pcd->ep0state = EP0_OUT_DATA_PHASE;
++01797         }
++01798 
++01799         if (UGETW(ctrl.wLength) == 0) {
++01800                 ep0->dwc_ep.is_in = 1;
++01801                 pcd->ep0state = EP0_IN_STATUS_PHASE;
++01802         }
++01803 
++01804         if (UT_GET_TYPE(ctrl.bmRequestType) != UT_STANDARD) {
++01805 
++01806 #ifdef DWC_UTE_CFI
++01807                 DWC_MEMCPY(&cfi_req, &ctrl, sizeof(usb_device_request_t));
++01808 
++01809                 //printk(KERN_ALERT "CFI: req_type=0x%02x; req=0x%02x\n", 
++01810                                 ctrl.bRequestType, ctrl.bRequest);
++01811                 if (UT_GET_TYPE(cfi_req.bRequestType) == UT_VENDOR) {
++01812                         if (cfi_req.bRequest > 0xB0 && cfi_req.bRequest < 0xBF) {
++01813                                 retval = cfi_setup(pcd, &cfi_req);
++01814                                 if (retval < 0) {
++01815                                         ep0_do_stall(pcd, retval);
++01816                                         pcd->ep0_pending = 0;
++01817                                         return;
++01818                                 }
++01819 
++01820                                 /* if need gadget setup then call it and check the retval */
++01821                                 if (pcd->cfi->need_gadget_att) {
++01822                                         retval =
++01823                                             cfi_gadget_setup(pcd,
++01824                                                              &pcd->
++01825                                                              cfi->ctrl_req);
++01826                                         if (retval < 0) {
++01827                                                 pcd->ep0_pending = 0;
++01828                                                 return;
++01829                                         }
++01830                                 }
++01831 
++01832                                 if (pcd->cfi->need_status_in_complete) {
++01833                                         do_setup_in_status_phase(pcd);
++01834                                 }
++01835                                 return;
++01836                         }
++01837                 }
++01838 #endif
++01839 
++01840                 /* handle non-standard (class/vendor) requests in the gadget driver */
++01841                 do_gadget_setup(pcd, &ctrl);
++01842                 return;
++01843         }
++01844 
++01847 
++01848 
++01849 
++01850         switch (ctrl.bRequest) {
++01851         case UR_GET_STATUS:
++01852                 do_get_status(pcd);
++01853                 break;
++01854 
++01855         case UR_CLEAR_FEATURE:
++01856                 do_clear_feature(pcd);
++01857                 break;
++01858 
++01859         case UR_SET_FEATURE:
++01860                 do_set_feature(pcd);
++01861                 break;
++01862 
++01863         case UR_SET_ADDRESS:
++01864                 do_set_address(pcd);
++01865                 break;
++01866 
++01867         case UR_SET_INTERFACE:
++01868         case UR_SET_CONFIG:
++01869 //              _pcd->request_config = 1;       /* Configuration changed */
++01870                 do_gadget_setup(pcd, &ctrl);
++01871                 break;
++01872 
++01873         case UR_SYNCH_FRAME:
++01874                 do_gadget_setup(pcd, &ctrl);
++01875                 break;
++01876 
++01877         default:
++01878                 /* Call the Gadget Driver's setup functions */
++01879                 do_gadget_setup(pcd, &ctrl);
++01880                 break;
++01881         }
++01882 }
++01883 
++01887 static int32_t ep0_complete_request(dwc_otg_pcd_ep_t * ep)
++01888 {
++01889         dwc_otg_core_if_t *core_if = GET_CORE_IF(ep->pcd);
++01890         dwc_otg_dev_if_t *dev_if = core_if->dev_if;
++01891         dwc_otg_dev_in_ep_regs_t *in_ep_regs =
++01892             dev_if->in_ep_regs[ep->dwc_ep.num];
++01893 #ifdef DEBUG_EP0
++01894         dwc_otg_dev_out_ep_regs_t *out_ep_regs =
++01895             dev_if->out_ep_regs[ep->dwc_ep.num];
++01896 #endif
++01897         deptsiz0_data_t deptsiz;
++01898         dev_dma_desc_sts_t desc_sts;
++01899         dwc_otg_pcd_request_t *req;
++01900         int is_last = 0;
++01901         dwc_otg_pcd_t *pcd = ep->pcd;
++01902 
++01903 #ifdef DWC_UTE_CFI
++01904         struct cfi_usb_ctrlrequest *ctrlreq;
++01905         int retval = -DWC_E_NOT_SUPPORTED;
++01906 #endif
++01907 
++01908         if (pcd->ep0_pending && DWC_CIRCLEQ_EMPTY(&ep->queue)) {
++01909                 if (ep->dwc_ep.is_in) {
++01910 #ifdef DEBUG_EP0
++01911                         DWC_DEBUGPL(DBG_PCDV, "Do setup OUT status phase\n");
++01912 #endif
++01913                         do_setup_out_status_phase(pcd);
++01914                 } else {
++01915 #ifdef DEBUG_EP0
++01916                         DWC_DEBUGPL(DBG_PCDV, "Do setup IN status phase\n");
++01917 #endif
++01918 
++01919 #ifdef DWC_UTE_CFI
++01920                         ctrlreq = &pcd->cfi->ctrl_req;
++01921 
++01922                         if (UT_GET_TYPE(ctrlreq->bRequestType) == UT_VENDOR) {
++01923                                 if (ctrlreq->bRequest > 0xB0
++01924                                     && ctrlreq->bRequest < 0xBF) {
++01925 
++01926                                         /* Return if the PCD failed to handle the request */
++01927                                         if ((retval =
++01928                                              pcd->cfi->ops.
++01929                                              ctrl_write_complete(pcd->cfi,
++01930                                                                  pcd)) < 0) {
++01931                                                 CFI_INFO
++01932                                                     ("ERROR setting a new value in the PCD(%d)\n",
++01933                                                      retval);
++01934                                                 ep0_do_stall(pcd, retval);
++01935                                                 pcd->ep0_pending = 0;
++01936                                                 return 0;
++01937                                         }
++01938 
++01939                                         /* If the gadget needs to be notified on the request */
++01940                                         if (pcd->cfi->need_gadget_att == 1) {
++01941                                                 //retval = do_gadget_setup(pcd, &pcd->cfi->ctrl_req);
++01942                                                 retval =
++01943                                                     cfi_gadget_setup(pcd,
++01944                                                                      &pcd->cfi->
++01945                                                                      ctrl_req);
++01946 
++01947                                                 /* Return from the function if the gadget failed to process
++01948                                                  * the request properly - this should never happen !!!
++01949                                                  */
++01950                                                 if (retval < 0) {
++01951                                                         CFI_INFO
++01952                                                             ("ERROR setting a new value in the gadget(%d)\n",
++01953                                                              retval);
++01954                                                         pcd->ep0_pending = 0;
++01955                                                         return 0;
++01956                                                 }
++01957                                         }
++01958 
++01959                                         CFI_INFO("%s: RETVAL=%d\n", __func__,
++01960                                                  retval);
++01961                                         /* If we hit here then the PCD and the gadget has properly
++01962                                          * handled the request - so send the ZLP IN to the host.
++01963                                          */
++01964                                         /* @todo: MAS - decide whether we need to start the setup
++01965                                          * stage based on the need_setup value of the cfi object
++01966                                          */
++01967                                         do_setup_in_status_phase(pcd);
++01968                                         pcd->ep0_pending = 0;
++01969                                         return 1;
++01970                                 }
++01971                         }
++01972 #endif
++01973 
++01974                         do_setup_in_status_phase(pcd);
++01975                 }
++01976                 pcd->ep0_pending = 0;
++01977                 return 1;
++01978         }
++01979 
++01980         if (DWC_CIRCLEQ_EMPTY(&ep->queue)) {
++01981                 return 0;
++01982         }
++01983         req = DWC_CIRCLEQ_FIRST(&ep->queue);
++01984 
++01985         if (pcd->ep0state == EP0_OUT_STATUS_PHASE
++01986             || pcd->ep0state == EP0_IN_STATUS_PHASE) {
++01987                 is_last = 1;
++01988         } else if (ep->dwc_ep.is_in) {
++01989                 deptsiz.d32 = DWC_READ_REG32(&in_ep_regs->dieptsiz);
++01990                 if (core_if->dma_desc_enable != 0)
++01991                         desc_sts = dev_if->in_desc_addr->status;
++01992 #ifdef DEBUG_EP0
++01993                 DWC_DEBUGPL(DBG_PCDV, "%d len=%d  xfersize=%d pktcnt=%d\n",
++01994                             ep->dwc_ep.num, ep->dwc_ep.xfer_len,
++01995                             deptsiz.b.xfersize, deptsiz.b.pktcnt);
++01996 #endif
++01997 
++01998                 if (((core_if->dma_desc_enable == 0)
++01999                      && (deptsiz.b.xfersize == 0))
++02000                     || ((core_if->dma_desc_enable != 0)
++02001                         && (desc_sts.b.bytes == 0))) {
++02002                         req->actual = ep->dwc_ep.xfer_count;
++02003                         /* Is a Zero Len Packet needed? */
++02004                         if (req->sent_zlp) {
++02005 #ifdef DEBUG_EP0
++02006                                 DWC_DEBUGPL(DBG_PCD, "Setup Rx ZLP\n");
++02007 #endif
++02008                                 req->sent_zlp = 0;
++02009                         }
++02010                         do_setup_out_status_phase(pcd);
++02011                 }
++02012         } else {
++02013                 /* ep0-OUT */
++02014 #ifdef DEBUG_EP0
++02015                 deptsiz.d32 = DWC_READ_REG32(&out_ep_regs->doeptsiz);
++02016                 DWC_DEBUGPL(DBG_PCDV, "%d len=%d xsize=%d pktcnt=%d\n",
++02017                             ep->dwc_ep.num, ep->dwc_ep.xfer_len,
++02018                             deptsiz.b.xfersize, deptsiz.b.pktcnt);
++02019 #endif
++02020                 req->actual = ep->dwc_ep.xfer_count;
++02021 
++02022                 /* Is a Zero Len Packet needed? */
++02023                 if (req->sent_zlp) {
++02024 #ifdef DEBUG_EP0
++02025                         DWC_DEBUGPL(DBG_PCDV, "Setup Tx ZLP\n");
++02026 #endif
++02027                         req->sent_zlp = 0;
++02028                 }
++02029                 if (core_if->dma_desc_enable == 0)
++02030                         do_setup_in_status_phase(pcd);
++02031         }
++02032 
++02033         /* Complete the request */
++02034         if (is_last) {
++02035                 dwc_otg_request_done(ep, req, 0);
++02036                 ep->dwc_ep.start_xfer_buff = 0;
++02037                 ep->dwc_ep.xfer_buff = 0;
++02038                 ep->dwc_ep.xfer_len = 0;
++02039                 return 1;
++02040         }
++02041         return 0;
++02042 }
++02043 
++02044 #ifdef DWC_UTE_CFI
++02045 
++02051 static inline int cfi_calc_desc_residue(dwc_otg_pcd_ep_t * ep)
++02052 {
++02053         int32_t ret = 0;
++02054         int i;
++02055         struct dwc_otg_dma_desc *ddesc = NULL;
++02056         struct cfi_ep *cfiep;
++02057 
++02058         /* See if the pcd_ep has its respective cfi_ep mapped */
++02059         cfiep = get_cfi_ep_by_pcd_ep(ep->pcd->cfi, ep);
++02060         if (!cfiep) {
++02061                 CFI_INFO("%s: Failed to find ep\n", __func__);
++02062                 return -1;
++02063         }
++02064 
++02065         ddesc = ep->dwc_ep.descs;
++02066 
++02067         for (i = 0; (i < cfiep->desc_count) && (i < MAX_DMA_DESCS_PER_EP); i++) {
++02068 
++02069 #if defined(PRINT_CFI_DMA_DESCS)
++02070                 print_desc(ddesc, ep->ep.name, i);
++02071 #endif
++02072                 ret += ddesc->status.b.bytes;
++02073                 ddesc++;
++02074         }
++02075 
++02076         if (ret)
++02077                 CFI_INFO("!!!!!!!!!! WARNING (%s) - residue=%d\n", __func__,
++02078                          ret);
++02079 
++02080         return ret;
++02081 }
++02082 #endif
++02083 
++02088 static void complete_ep(dwc_otg_pcd_ep_t * ep)
++02089 {
++02090         dwc_otg_core_if_t *core_if = GET_CORE_IF(ep->pcd);
++02091         dwc_otg_dev_if_t *dev_if = core_if->dev_if;
++02092         dwc_otg_dev_in_ep_regs_t *in_ep_regs =
++02093             dev_if->in_ep_regs[ep->dwc_ep.num];
++02094         deptsiz_data_t deptsiz;
++02095         dev_dma_desc_sts_t desc_sts;
++02096         dwc_otg_pcd_request_t *req = 0;
++02097         dwc_otg_dev_dma_desc_t *dma_desc;
++02098         uint32_t byte_count = 0;
++02099         int is_last = 0;
++02100         int i;
++02101 
++02102         DWC_DEBUGPL(DBG_PCDV, "%s() %d-%s\n", __func__, ep->dwc_ep.num,
++02103                     (ep->dwc_ep.is_in ? "IN" : "OUT"));
++02104 
++02105         /* Get any pending requests */
++02106         if (!DWC_CIRCLEQ_EMPTY(&ep->queue)) {
++02107                 req = DWC_CIRCLEQ_FIRST(&ep->queue);
++02108                 if (!req) {
++02109                         DWC_PRINTF("complete_ep 0x%p, req = NULL!\n", ep);
++02110                         return;
++02111                 }
++02112         } else {
++02113                 DWC_PRINTF("complete_ep 0x%p, ep->queue empty!\n", ep);
++02114                 return;
++02115         }
++02116 
++02117         DWC_DEBUGPL(DBG_PCD, "Requests %d\n", ep->pcd->request_pending);
++02118 
++02119         if (ep->dwc_ep.is_in) {
++02120                 deptsiz.d32 = DWC_READ_REG32(&in_ep_regs->dieptsiz);
++02121 
++02122                 if (core_if->dma_enable) {
++02123                         if (core_if->dma_desc_enable == 0) {
++02124                                 if (deptsiz.b.xfersize == 0
++02125                                     && deptsiz.b.pktcnt == 0) {
++02126                                         byte_count =
++02127                                             ep->dwc_ep.xfer_len -
++02128                                             ep->dwc_ep.xfer_count;
++02129 
++02130                                         ep->dwc_ep.xfer_buff += byte_count;
++02131                                         ep->dwc_ep.dma_addr += byte_count;
++02132                                         ep->dwc_ep.xfer_count += byte_count;
++02133 
++02134                                         DWC_DEBUGPL(DBG_PCDV,
++02135                                                     "%d-%s len=%d  xfersize=%d pktcnt=%d\n",
++02136                                                     ep->dwc_ep.num,
++02137                                                     (ep->dwc_ep.
++02138                                                      is_in ? "IN" : "OUT"),
++02139                                                     ep->dwc_ep.xfer_len,
++02140                                                     deptsiz.b.xfersize,
++02141                                                     deptsiz.b.pktcnt);
++02142 
++02143                                         if (ep->dwc_ep.xfer_len <
++02144                                             ep->dwc_ep.total_len) {
++02145                                                 dwc_otg_ep_start_transfer
++02146                                                     (core_if, &ep->dwc_ep);
++02147                                         } else if (ep->dwc_ep.sent_zlp) {
++02148                                                 /*     
++02149                                                  * This fragment of code should initiate 0
++02150                                                  * length transfer in case if it is queued
++02151                                                  * a transfer with size divisible to EPs max
++02152                                                  * packet size and with usb_request zero field
++02153                                                  * is set, which means that after data is transfered,
++02154                                                  * it is also should be transfered
++02155                                                  * a 0 length packet at the end. For Slave and
++02156                                                  * Buffer DMA modes in this case SW has
++02157                                                  * to initiate 2 transfers one with transfer size,
++02158                                                  * and the second with 0 size. For Descriptor
++02159                                                  * DMA mode SW is able to initiate a transfer,
++02160                                                  * which will handle all the packets including
++02161                                                  * the last  0 length.
++02162                                                  */
++02163                                                 ep->dwc_ep.sent_zlp = 0;
++02164                                                 dwc_otg_ep_start_zl_transfer
++02165                                                     (core_if, &ep->dwc_ep);
++02166                                         } else {
++02167                                                 is_last = 1;
++02168                                         }
++02169                                 } else {
++02170                                         if(ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC)
++02171                                         {
++02172                                                 req->actual = 0;
++02173                                                 dwc_otg_request_done(ep, req, 0);
++02174 
++02175                                                 ep->dwc_ep.start_xfer_buff = 0;
++02176                                                 ep->dwc_ep.xfer_buff = 0;
++02177                                                 ep->dwc_ep.xfer_len = 0;
++02178 
++02179                                                 /* If there is a request in the queue start it. */
++02180                                                 start_next_request(ep);
++02181                                         } else
++02182                                                 DWC_WARN
++02183                                                 ("Incomplete transfer (%d - %s [siz=%d pkt=%d])\n",
++02184                                                 ep->dwc_ep.num,
++02185                                                 (ep->dwc_ep.is_in ? "IN" : "OUT"),
++02186                                                 deptsiz.b.xfersize,
++02187                                                 deptsiz.b.pktcnt);
++02188                                 }
++02189                         } else {
++02190                                 dma_desc = ep->dwc_ep.desc_addr;
++02191                                 byte_count = 0;
++02192                                 ep->dwc_ep.sent_zlp = 0;
++02193 
++02194 #ifdef DWC_UTE_CFI
++02195                                 CFI_INFO("%s: BUFFER_MODE=%d\n", __func__,
++02196                                          ep->dwc_ep.buff_mode);
++02197                                 if (ep->dwc_ep.buff_mode != BM_STANDARD) {
++02198                                         int residue;
++02199 
++02200                                         residue = cfi_calc_desc_residue(ep);
++02201                                         if (residue < 0)
++02202                                                 return;
++02203 
++02204                                         byte_count = residue;
++02205                                 } else {
++02206 #endif
++02207                                         for (i = 0; i < ep->dwc_ep.desc_cnt;
++02208                                              ++i) {
++02209                                         desc_sts = dma_desc->status;
++02210                                         byte_count += desc_sts.b.bytes;
++02211                                         dma_desc++;
++02212                                 }
++02213 #ifdef DWC_UTE_CFI
++02214                                 }
++02215 #endif
++02216                                 if (byte_count == 0) {
++02217                                         ep->dwc_ep.xfer_count =
++02218                                             ep->dwc_ep.total_len;
++02219                                         is_last = 1;
++02220                                 } else {
++02221                                         DWC_WARN("Incomplete transfer\n");
++02222                                 }
++02223                         }
++02224                 } else {
++02225                         if (deptsiz.b.xfersize == 0 && deptsiz.b.pktcnt == 0) {
++02226                                 DWC_DEBUGPL(DBG_PCDV,
++02227                                             "%d-%s len=%d  xfersize=%d pktcnt=%d\n",
++02228                                             ep->dwc_ep.num,
++02229                                             ep->dwc_ep.is_in ? "IN" : "OUT",
++02230                                             ep->dwc_ep.xfer_len,
++02231                                             deptsiz.b.xfersize,
++02232                                             deptsiz.b.pktcnt);
++02233 
++02234                                 /*      Check if the whole transfer was completed, 
++02235                                  *      if no, setup transfer for next portion of data
++02236                                  */
++02237                                 if (ep->dwc_ep.xfer_len < ep->dwc_ep.total_len) {
++02238                                         dwc_otg_ep_start_transfer(core_if,
++02239                                                                   &ep->dwc_ep);
++02240                                 } else if (ep->dwc_ep.sent_zlp) {
++02241                                         /*     
++02242                                          * This fragment of code should initiate 0
++02243                                          * length trasfer in case if it is queued
++02244                                          * a trasfer with size divisible to EPs max
++02245                                          * packet size and with usb_request zero field
++02246                                          * is set, which means that after data is transfered,
++02247                                          * it is also should be transfered
++02248                                          * a 0 length packet at the end. For Slave and
++02249                                          * Buffer DMA modes in this case SW has
++02250                                          * to initiate 2 transfers one with transfer size,
++02251                                          * and the second with 0 size. For Desriptor
++02252                                          * DMA mode SW is able to initiate a transfer,
++02253                                          * which will handle all the packets including
++02254                                          * the last  0 legth.
++02255                                          */
++02256                                         ep->dwc_ep.sent_zlp = 0;
++02257                                         dwc_otg_ep_start_zl_transfer(core_if,
++02258                                                                      &ep->dwc_ep);
++02259                                 } else {
++02260                                         is_last = 1;
++02261                                 }
++02262                         } else {
++02263                                 DWC_WARN
++02264                                     ("Incomplete transfer (%d-%s [siz=%d pkt=%d])\n",
++02265                                      ep->dwc_ep.num,
++02266                                      (ep->dwc_ep.is_in ? "IN" : "OUT"),
++02267                                      deptsiz.b.xfersize, deptsiz.b.pktcnt);
++02268                         }
++02269                 }
++02270         } else {
++02271                 dwc_otg_dev_out_ep_regs_t *out_ep_regs =
++02272                     dev_if->out_ep_regs[ep->dwc_ep.num];
++02273                 desc_sts.d32 = 0;
++02274                 if (core_if->dma_enable) {
++02275                         if (core_if->dma_desc_enable) {
++02276                                 dma_desc = ep->dwc_ep.desc_addr;
++02277                                 byte_count = 0;
++02278                                 ep->dwc_ep.sent_zlp = 0;
++02279 
++02280 #ifdef DWC_UTE_CFI
++02281                                 CFI_INFO("%s: BUFFER_MODE=%d\n", __func__,
++02282                                          ep->dwc_ep.buff_mode);
++02283                                 if (ep->dwc_ep.buff_mode != BM_STANDARD) {
++02284                                         int residue;
++02285                                         residue = cfi_calc_desc_residue(ep);
++02286                                         if (residue < 0)
++02287                                                 return;
++02288                                         byte_count = residue;
++02289                                 } else {
++02290 #endif
++02291 
++02292                                         for (i = 0; i < ep->dwc_ep.desc_cnt;
++02293                                              ++i) {
++02294                                                 desc_sts = dma_desc->status;
++02295                                                 byte_count += desc_sts.b.bytes;
++02296                                                 dma_desc++;
++02297                                         }
++02298 
++02299 #ifdef DWC_UTE_CFI
++02300                                 }
++02301 #endif
++02302                                 /* Checking for interrupt Out transfers with not 
++02303                                  * dword aligned mps sizes 
++02304                                  */
++02305                                 if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_INTR &&
++02306                                                         (ep->dwc_ep.maxpacket%4)) {
++02307                                         ep->dwc_ep.xfer_count = ep->dwc_ep.total_len - byte_count;
++02308                                         if ((ep->dwc_ep.xfer_len % ep->dwc_ep.maxpacket) &&
++02309                                                 (ep->dwc_ep.xfer_len/ep->dwc_ep.maxpacket < MAX_DMA_DESC_CNT))
++02310                                                 ep->dwc_ep.xfer_len -=
++02311                                                         (ep->dwc_ep.desc_cnt - 1) * ep->dwc_ep.maxpacket +
++02312                                                                         ep->dwc_ep.xfer_len % ep->dwc_ep.maxpacket;
++02313                                         else                                            
++02314                                                 ep->dwc_ep.xfer_len -=
++02315                                                                         ep->dwc_ep.desc_cnt * ep->dwc_ep.maxpacket;
++02316                                         if (ep->dwc_ep.xfer_len > 0) {
++02317                                                 dwc_otg_ep_start_transfer(core_if,
++02318                                                                   &ep->dwc_ep);
++02319                                         } else {
++02320                                                 is_last = 1;
++02321                                         }
++02322                                 } else {
++02323                                         ep->dwc_ep.xfer_count = ep->dwc_ep.total_len
++02324                                                 - byte_count +
++02325                                                 ((4 - (ep->dwc_ep.total_len & 0x3)) & 0x3);
++02326                                         is_last = 1;
++02327                                 }       
++02328                         } else {
++02329                                 deptsiz.d32 = 0;
++02330                                 deptsiz.d32 =
++02331                                     DWC_READ_REG32(&out_ep_regs->doeptsiz);
++02332 
++02333                                 byte_count = (ep->dwc_ep.xfer_len -
++02334                                               ep->dwc_ep.xfer_count -
++02335                                               deptsiz.b.xfersize);
++02336                                 ep->dwc_ep.xfer_buff += byte_count;
++02337                                 ep->dwc_ep.dma_addr += byte_count;
++02338                                 ep->dwc_ep.xfer_count += byte_count;
++02339 
++02340                                 /*      Check if the whole transfer was completed, 
++02341                                  *      if no, setup transfer for next portion of data
++02342                                  */
++02343                                 if (ep->dwc_ep.xfer_len < ep->dwc_ep.total_len) {
++02344                                         dwc_otg_ep_start_transfer(core_if,
++02345                                                                   &ep->dwc_ep);
++02346                                 } else if (ep->dwc_ep.sent_zlp) {
++02347                                         /*     
++02348                                          * This fragment of code should initiate 0
++02349                                          * length trasfer in case if it is queued
++02350                                          * a trasfer with size divisible to EPs max
++02351                                          * packet size and with usb_request zero field
++02352                                          * is set, which means that after data is transfered,
++02353                                          * it is also should be transfered
++02354                                          * a 0 length packet at the end. For Slave and
++02355                                          * Buffer DMA modes in this case SW has
++02356                                          * to initiate 2 transfers one with transfer size,
++02357                                          * and the second with 0 size. For Desriptor
++02358                                          * DMA mode SW is able to initiate a transfer,
++02359                                          * which will handle all the packets including
++02360                                          * the last  0 legth.
++02361                                          */
++02362                                         ep->dwc_ep.sent_zlp = 0;
++02363                                         dwc_otg_ep_start_zl_transfer(core_if,
++02364                                                                      &ep->dwc_ep);
++02365                                 } else {
++02366                                         is_last = 1;
++02367                                 }
++02368                         }
++02369                 } else {
++02370                         /*      Check if the whole transfer was completed, 
++02371                          *      if no, setup transfer for next portion of data
++02372                          */
++02373                         if (ep->dwc_ep.xfer_len < ep->dwc_ep.total_len) {
++02374                                 dwc_otg_ep_start_transfer(core_if, &ep->dwc_ep);
++02375                         } else if (ep->dwc_ep.sent_zlp) {
++02376                                 /*     
++02377                                  * This fragment of code should initiate 0
++02378                                  * length transfer in case if it is queued
++02379                                  * a transfer with size divisible to EPs max
++02380                                  * packet size and with usb_request zero field
++02381                                  * is set, which means that after data is transfered,
++02382                                  * it is also should be transfered
++02383                                  * a 0 length packet at the end. For Slave and
++02384                                  * Buffer DMA modes in this case SW has
++02385                                  * to initiate 2 transfers one with transfer size,
++02386                                  * and the second with 0 size. For Descriptor
++02387                                  * DMA mode SW is able to initiate a transfer,
++02388                                  * which will handle all the packets including
++02389                                  * the last  0 length.
++02390                                  */
++02391                                 ep->dwc_ep.sent_zlp = 0;
++02392                                 dwc_otg_ep_start_zl_transfer(core_if,
++02393                                                              &ep->dwc_ep);
++02394                         } else {
++02395                                 is_last = 1;
++02396                         }
++02397                 }
++02398 
++02399                 DWC_DEBUGPL(DBG_PCDV,
++02400                             "addr %p,    %d-%s len=%d cnt=%d xsize=%d pktcnt=%d\n",
++02401                             &out_ep_regs->doeptsiz, ep->dwc_ep.num,
++02402                             ep->dwc_ep.is_in ? "IN" : "OUT",
++02403                             ep->dwc_ep.xfer_len, ep->dwc_ep.xfer_count,
++02404                             deptsiz.b.xfersize, deptsiz.b.pktcnt);
++02405         }
++02406 
++02407         /* Complete the request */
++02408         if (is_last) {
++02409 #ifdef DWC_UTE_CFI
++02410                 if (ep->dwc_ep.buff_mode != BM_STANDARD) {
++02411                         req->actual = ep->dwc_ep.cfi_req_len - byte_count;
++02412                 } else {
++02413 #endif
++02414                         req->actual = ep->dwc_ep.xfer_count;
++02415 #ifdef DWC_UTE_CFI
++02416                 }
++02417 #endif
++02418                 if (req->dw_align_buf) {
++02419                         if (!ep->dwc_ep.is_in) {
++02420                                 dwc_memcpy(req->buf, req->dw_align_buf, req->length); 
++02421                         }
++02422                         DWC_DMA_FREE(req->length, req->dw_align_buf,
++02423                                      req->dw_align_buf_dma);
++02424                 }
++02425 
++02426                 dwc_otg_request_done(ep, req, 0);
++02427 
++02428                 ep->dwc_ep.start_xfer_buff = 0;
++02429                 ep->dwc_ep.xfer_buff = 0;
++02430                 ep->dwc_ep.xfer_len = 0;
++02431 
++02432                 /* If there is a request in the queue start it. */
++02433                 start_next_request(ep);
++02434         }
++02435 }
++02436 
++02437 #ifdef DWC_EN_ISOC
++02438 
++02443 static void dwc_otg_pcd_handle_iso_bna(dwc_otg_pcd_ep_t * ep)
++02444 {
++02445         dwc_ep_t *dwc_ep = &ep->dwc_ep;
++02446         volatile uint32_t *addr;
++02447         depctl_data_t depctl = {.d32 = 0 };
++02448         dwc_otg_pcd_t *pcd = ep->pcd;
++02449         dwc_otg_dev_dma_desc_t *dma_desc;
++02450         int i;
++02451 
++02452         dma_desc =
++02453             dwc_ep->iso_desc_addr + dwc_ep->desc_cnt * (dwc_ep->proc_buf_num);
++02454 
++02455         if (dwc_ep->is_in) {
++02456                 dev_dma_desc_sts_t sts = {.d32 = 0 };
++02457                 for (i = 0; i < dwc_ep->desc_cnt; ++i, ++dma_desc) {
++02458                         sts.d32 = dma_desc->status.d32;
++02459                         sts.b_iso_in.bs = BS_HOST_READY;
++02460                         dma_desc->status.d32 = sts.d32;
++02461                 }
++02462         } else {
++02463                 dev_dma_desc_sts_t sts = {.d32 = 0 };
++02464                 for (i = 0; i < dwc_ep->desc_cnt; ++i, ++dma_desc) {
++02465                         sts.d32 = dma_desc->status.d32;
++02466                         sts.b_iso_out.bs = BS_HOST_READY;
++02467                         dma_desc->status.d32 = sts.d32;
++02468                 }
++02469         }
++02470 
++02471         if (dwc_ep->is_in == 0) {
++02472                 addr =
++02473                     &GET_CORE_IF(pcd)->dev_if->out_ep_regs[dwc_ep->
++02474                                                            num]->doepctl;
++02475         } else {
++02476                 addr =
++02477                     &GET_CORE_IF(pcd)->dev_if->in_ep_regs[dwc_ep->num]->diepctl;
++02478         }
++02479         depctl.b.epena = 1;
++02480         DWC_MODIFY_REG32(addr, depctl.d32, depctl.d32);
++02481 }
++02482 
++02490 void set_current_pkt_info(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
++02491 {
++02492         deptsiz_data_t deptsiz = {.d32 = 0 };
++02493         dma_addr_t dma_addr;
++02494         uint32_t offset;
++02495 
++02496         if (ep->proc_buf_num)
++02497                 dma_addr = ep->dma_addr1;
++02498         else
++02499                 dma_addr = ep->dma_addr0;
++02500 
++02501         if (ep->is_in) {
++02502                 deptsiz.d32 =
++02503                     DWC_READ_REG32(&core_if->dev_if->
++02504                                    in_ep_regs[ep->num]->dieptsiz);
++02505                 offset = ep->data_per_frame;
++02506         } else {
++02507                 deptsiz.d32 =
++02508                     DWC_READ_REG32(&core_if->dev_if->
++02509                                    out_ep_regs[ep->num]->doeptsiz);
++02510                 offset =
++02511                     ep->data_per_frame +
++02512                     (0x4 & (0x4 - (ep->data_per_frame & 0x3)));
++02513         }
++02514 
++02515         if (!deptsiz.b.xfersize) {
++02516                 ep->pkt_info[ep->cur_pkt].length = ep->data_per_frame;
++02517                 ep->pkt_info[ep->cur_pkt].offset =
++02518                     ep->cur_pkt_dma_addr - dma_addr;
++02519                 ep->pkt_info[ep->cur_pkt].status = 0;
++02520         } else {
++02521                 ep->pkt_info[ep->cur_pkt].length = ep->data_per_frame;
++02522                 ep->pkt_info[ep->cur_pkt].offset =
++02523                     ep->cur_pkt_dma_addr - dma_addr;
++02524                 ep->pkt_info[ep->cur_pkt].status = -DWC_E_NO_DATA;
++02525         }
++02526         ep->cur_pkt_addr += offset;
++02527         ep->cur_pkt_dma_addr += offset;
++02528         ep->cur_pkt++;
++02529 }
++02530 
++02538 static void set_ddma_iso_pkts_info(dwc_otg_core_if_t * core_if,
++02539                                    dwc_ep_t * dwc_ep)
++02540 {
++02541         dwc_otg_dev_dma_desc_t *dma_desc;
++02542         dev_dma_desc_sts_t sts = {.d32 = 0 };
++02543         iso_pkt_info_t *iso_packet;
++02544         uint32_t data_per_desc;
++02545         uint32_t offset;
++02546         int i, j;
++02547 
++02548         iso_packet = dwc_ep->pkt_info;
++02549 
++02552         if (dwc_ep->is_in == 0) {
++02553                 dma_desc =
++02554                     dwc_ep->iso_desc_addr +
++02555                     dwc_ep->desc_cnt * dwc_ep->proc_buf_num;
++02556                 offset = 0;
++02557 
++02558                 for (i = 0; i < dwc_ep->desc_cnt - dwc_ep->pkt_per_frm;
++02559                      i += dwc_ep->pkt_per_frm) {
++02560                         for (j = 0; j < dwc_ep->pkt_per_frm; ++j) {
++02561                                 data_per_desc =
++02562                                     ((j + 1) * dwc_ep->maxpacket >
++02563                                      dwc_ep->
++02564                                      data_per_frame) ? dwc_ep->data_per_frame -
++02565                                     j * dwc_ep->maxpacket : dwc_ep->maxpacket;
++02566                                 data_per_desc +=
++02567                                     (data_per_desc % 4) ? (4 -
++02568                                                            data_per_desc %
++02569                                                            4) : 0;
++02570 
++02571                                 sts.d32 = dma_desc->status.d32;
++02572 
++02573                                 /* Write status in iso_packet_decsriptor  */
++02574                                 iso_packet->status =
++02575                                     sts.b_iso_out.rxsts +
++02576                                     (sts.b_iso_out.bs ^ BS_DMA_DONE);
++02577                                 if (iso_packet->status) {
++02578                                         iso_packet->status = -DWC_E_NO_DATA;
++02579                                 }
++02580 
++02581                                 /* Received data length */
++02582                                 if (!sts.b_iso_out.rxbytes) {
++02583                                         iso_packet->length =
++02584                                             data_per_desc -
++02585                                             sts.b_iso_out.rxbytes;
++02586                                 } else {
++02587                                         iso_packet->length =
++02588                                             data_per_desc -
++02589                                             sts.b_iso_out.rxbytes + (4 -
++02590                                                                      dwc_ep->data_per_frame
++02591                                                                      % 4);
++02592                                 }
++02593 
++02594                                 iso_packet->offset = offset;
++02595 
++02596                                 offset += data_per_desc;
++02597                                 dma_desc++;
++02598                                 iso_packet++;
++02599                         }
++02600                 }
++02601 
++02602                 for (j = 0; j < dwc_ep->pkt_per_frm - 1; ++j) {
++02603                         data_per_desc =
++02604                             ((j + 1) * dwc_ep->maxpacket >
++02605                              dwc_ep->data_per_frame) ? dwc_ep->data_per_frame -
++02606                             j * dwc_ep->maxpacket : dwc_ep->maxpacket;
++02607                         data_per_desc +=
++02608                             (data_per_desc % 4) ? (4 - data_per_desc % 4) : 0;
++02609 
++02610                         sts.d32 = dma_desc->status.d32;
++02611 
++02612                         /* Write status in iso_packet_decsriptor  */
++02613                         iso_packet->status =
++02614                             sts.b_iso_out.rxsts +
++02615                             (sts.b_iso_out.bs ^ BS_DMA_DONE);
++02616                         if (iso_packet->status) {
++02617                                 iso_packet->status = -DWC_E_NO_DATA;
++02618                         }
++02619 
++02620                         /* Received data length */
++02621                         iso_packet->length =
++02622                             dwc_ep->data_per_frame - sts.b_iso_out.rxbytes;
++02623 
++02624                         iso_packet->offset = offset;
++02625 
++02626                         offset += data_per_desc;
++02627                         iso_packet++;
++02628                         dma_desc++;
++02629                 }
++02630 
++02631                 sts.d32 = dma_desc->status.d32;
++02632 
++02633                 /* Write status in iso_packet_decsriptor  */
++02634                 iso_packet->status =
++02635                     sts.b_iso_out.rxsts + (sts.b_iso_out.bs ^ BS_DMA_DONE);
++02636                 if (iso_packet->status) {
++02637                         iso_packet->status = -DWC_E_NO_DATA;
++02638                 }
++02639                 /* Received data length */
++02640                 if (!sts.b_iso_out.rxbytes) {
++02641                         iso_packet->length =
++02642                             dwc_ep->data_per_frame - sts.b_iso_out.rxbytes;
++02643                 } else {
++02644                         iso_packet->length =
++02645                             dwc_ep->data_per_frame - sts.b_iso_out.rxbytes +
++02646                             (4 - dwc_ep->data_per_frame % 4);
++02647                 }
++02648 
++02649                 iso_packet->offset = offset;
++02650         } else {
++02653                 dma_desc =
++02654                     dwc_ep->iso_desc_addr +
++02655                     dwc_ep->desc_cnt * dwc_ep->proc_buf_num;
++02656 
++02657                 for (i = 0; i < dwc_ep->desc_cnt - 1; i++) {
++02658                         sts.d32 = dma_desc->status.d32;
++02659 
++02660                         /* Write status in iso packet descriptor */
++02661                         iso_packet->status =
++02662                             sts.b_iso_in.txsts +
++02663                             (sts.b_iso_in.bs ^ BS_DMA_DONE);
++02664                         if (iso_packet->status != 0) {
++02665                                 iso_packet->status = -DWC_E_NO_DATA;
++02666 
++02667                         }
++02668                         /* Bytes has been transfered */
++02669                         iso_packet->length =
++02670                             dwc_ep->data_per_frame - sts.b_iso_in.txbytes;
++02671 
++02672                         dma_desc++;
++02673                         iso_packet++;
++02674                 }
++02675 
++02676                 sts.d32 = dma_desc->status.d32;
++02677                 while (sts.b_iso_in.bs == BS_DMA_BUSY) {
++02678                         sts.d32 = dma_desc->status.d32;
++02679                 }
++02680 
++02681                 /* Write status in iso packet descriptor ??? do be done with ERROR codes */
++02682                 iso_packet->status =
++02683                     sts.b_iso_in.txsts + (sts.b_iso_in.bs ^ BS_DMA_DONE);
++02684                 if (iso_packet->status != 0) {
++02685                         iso_packet->status = -DWC_E_NO_DATA;
++02686                 }
++02687 
++02688                 /* Bytes has been transfered */
++02689                 iso_packet->length =
++02690                     dwc_ep->data_per_frame - sts.b_iso_in.txbytes;
++02691         }
++02692 }
++02693 
++02701 static void reinit_ddma_iso_xfer(dwc_otg_core_if_t * core_if, dwc_ep_t * dwc_ep)
++02702 {
++02703         int i, j;
++02704         dwc_otg_dev_dma_desc_t *dma_desc;
++02705         dma_addr_t dma_ad;
++02706         volatile uint32_t *addr;
++02707         dev_dma_desc_sts_t sts = {.d32 = 0 };
++02708         uint32_t data_per_desc;
++02709 
++02710         if (dwc_ep->is_in == 0) {
++02711                 addr = &core_if->dev_if->out_ep_regs[dwc_ep->num]->doepctl;
++02712         } else {
++02713                 addr = &core_if->dev_if->in_ep_regs[dwc_ep->num]->diepctl;
++02714         }
++02715 
++02716         if (dwc_ep->proc_buf_num == 0) {
++02718                 dma_ad = dwc_ep->dma_addr0;
++02719         } else {
++02721                 dma_ad = dwc_ep->dma_addr1;
++02722         }
++02723 
++02726         if (dwc_ep->is_in == 0) {
++02727                 dma_desc =
++02728                     dwc_ep->iso_desc_addr +
++02729                     dwc_ep->desc_cnt * dwc_ep->proc_buf_num;
++02730 
++02731                 sts.b_iso_out.bs = BS_HOST_READY;
++02732                 sts.b_iso_out.rxsts = 0;
++02733                 sts.b_iso_out.l = 0;
++02734                 sts.b_iso_out.sp = 0;
++02735                 sts.b_iso_out.ioc = 0;
++02736                 sts.b_iso_out.pid = 0;
++02737                 sts.b_iso_out.framenum = 0;
++02738 
++02739                 for (i = 0; i < dwc_ep->desc_cnt - dwc_ep->pkt_per_frm;
++02740                      i += dwc_ep->pkt_per_frm) {
++02741                         for (j = 0; j < dwc_ep->pkt_per_frm; ++j) {
++02742                                 data_per_desc =
++02743                                     ((j + 1) * dwc_ep->maxpacket >
++02744                                      dwc_ep->
++02745                                      data_per_frame) ? dwc_ep->data_per_frame -
++02746                                     j * dwc_ep->maxpacket : dwc_ep->maxpacket;
++02747                                 data_per_desc +=
++02748                                     (data_per_desc % 4) ? (4 -
++02749                                                            data_per_desc %
++02750                                                            4) : 0;
++02751                                 sts.b_iso_out.rxbytes = data_per_desc;
++02752                                 dma_desc->buf = dma_ad;
++02753                                 dma_desc->status.d32 = sts.d32;
++02754 
++02755                                 dma_ad += data_per_desc;
++02756                                 dma_desc++;
++02757                         }
++02758                 }
++02759 
++02760                 for (j = 0; j < dwc_ep->pkt_per_frm - 1; ++j) {
++02761 
++02762                         data_per_desc =
++02763                             ((j + 1) * dwc_ep->maxpacket >
++02764                              dwc_ep->data_per_frame) ? dwc_ep->data_per_frame -
++02765                             j * dwc_ep->maxpacket : dwc_ep->maxpacket;
++02766                         data_per_desc +=
++02767                             (data_per_desc % 4) ? (4 - data_per_desc % 4) : 0;
++02768                         sts.b_iso_out.rxbytes = data_per_desc;
++02769 
++02770                         dma_desc->buf = dma_ad;
++02771                         dma_desc->status.d32 = sts.d32;
++02772 
++02773                         dma_desc++;
++02774                         dma_ad += data_per_desc;
++02775                 }
++02776 
++02777                 sts.b_iso_out.ioc = 1;
++02778                 sts.b_iso_out.l = dwc_ep->proc_buf_num;
++02779 
++02780                 data_per_desc =
++02781                     ((j + 1) * dwc_ep->maxpacket >
++02782                      dwc_ep->data_per_frame) ? dwc_ep->data_per_frame -
++02783                     j * dwc_ep->maxpacket : dwc_ep->maxpacket;
++02784                 data_per_desc +=
++02785                     (data_per_desc % 4) ? (4 - data_per_desc % 4) : 0;
++02786                 sts.b_iso_out.rxbytes = data_per_desc;
++02787 
++02788                 dma_desc->buf = dma_ad;
++02789                 dma_desc->status.d32 = sts.d32;
++02790         } else {
++02793                 dma_desc =
++02794                     dwc_ep->iso_desc_addr +
++02795                     dwc_ep->desc_cnt * dwc_ep->proc_buf_num;
++02796 
++02797                 sts.b_iso_in.bs = BS_HOST_READY;
++02798                 sts.b_iso_in.txsts = 0;
++02799                 sts.b_iso_in.sp = 0;
++02800                 sts.b_iso_in.ioc = 0;
++02801                 sts.b_iso_in.pid = dwc_ep->pkt_per_frm;
++02802                 sts.b_iso_in.framenum = dwc_ep->next_frame;
++02803                 sts.b_iso_in.txbytes = dwc_ep->data_per_frame;
++02804                 sts.b_iso_in.l = 0;
++02805 
++02806                 for (i = 0; i < dwc_ep->desc_cnt - 1; i++) {
++02807                         dma_desc->buf = dma_ad;
++02808                         dma_desc->status.d32 = sts.d32;
++02809 
++02810                         sts.b_iso_in.framenum += dwc_ep->bInterval;
++02811                         dma_ad += dwc_ep->data_per_frame;
++02812                         dma_desc++;
++02813                 }
++02814 
++02815                 sts.b_iso_in.ioc = 1;
++02816                 sts.b_iso_in.l = dwc_ep->proc_buf_num;
++02817 
++02818                 dma_desc->buf = dma_ad;
++02819                 dma_desc->status.d32 = sts.d32;
++02820 
++02821                 dwc_ep->next_frame =
++02822                     sts.b_iso_in.framenum + dwc_ep->bInterval * 1;
++02823         }
++02824         dwc_ep->proc_buf_num = (dwc_ep->proc_buf_num ^ 1) & 0x1;
++02825 }
++02826 
++02835 static uint32_t handle_iso_out_pkt_dropped(dwc_otg_core_if_t * core_if,
++02836                                            dwc_ep_t * dwc_ep)
++02837 {
++02838         uint32_t dma_addr;
++02839         uint32_t drp_pkt;
++02840         uint32_t drp_pkt_cnt;
++02841         deptsiz_data_t deptsiz = {.d32 = 0 };
++02842         depctl_data_t depctl = {.d32 = 0 };
++02843         int i;
++02844 
++02845         deptsiz.d32 =
++02846             DWC_READ_REG32(&core_if->dev_if->
++02847                            out_ep_regs[dwc_ep->num]->doeptsiz);
++02848 
++02849         drp_pkt = dwc_ep->pkt_cnt - deptsiz.b.pktcnt;
++02850         drp_pkt_cnt = dwc_ep->pkt_per_frm - (drp_pkt % dwc_ep->pkt_per_frm);
++02851 
++02852         /* Setting dropped packets status */
++02853         for (i = 0; i < drp_pkt_cnt; ++i) {
++02854                 dwc_ep->pkt_info[drp_pkt].status = -DWC_E_NO_DATA;
++02855                 drp_pkt++;
++02856                 deptsiz.b.pktcnt--;
++02857         }
++02858 
++02859         if (deptsiz.b.pktcnt > 0) {
++02860                 deptsiz.b.xfersize =
++02861                     dwc_ep->xfer_len - (dwc_ep->pkt_cnt -
++02862                                         deptsiz.b.pktcnt) * dwc_ep->maxpacket;
++02863         } else {
++02864                 deptsiz.b.xfersize = 0;
++02865                 deptsiz.b.pktcnt = 0;
++02866         }
++02867 
++02868         DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[dwc_ep->num]->doeptsiz,
++02869                         deptsiz.d32);
++02870 
++02871         if (deptsiz.b.pktcnt > 0) {
++02872                 if (dwc_ep->proc_buf_num) {
++02873                         dma_addr =
++02874                             dwc_ep->dma_addr1 + dwc_ep->xfer_len -
++02875                             deptsiz.b.xfersize;
++02876                 } else {
++02877                         dma_addr =
++02878                             dwc_ep->dma_addr0 + dwc_ep->xfer_len -
++02879                             deptsiz.b.xfersize;;
++02880                 }
++02881 
++02882                 DWC_WRITE_REG32(&core_if->dev_if->
++02883                                 out_ep_regs[dwc_ep->num]->doepdma, dma_addr);
++02884 
++02886                 depctl.d32 = 0;
++02887                 depctl.b.epena = 1;
++02888                 depctl.b.cnak = 1;
++02889 
++02890                 DWC_MODIFY_REG32(&core_if->dev_if->
++02891                                  out_ep_regs[dwc_ep->num]->doepctl, depctl.d32,
++02892                                  depctl.d32);
++02893                 return 0;
++02894         } else {
++02895                 return 1;
++02896         }
++02897 }
++02898 
++02906 static uint32_t set_iso_pkts_info(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
++02907 {
++02908         int i, j;
++02909         dma_addr_t dma_ad;
++02910         iso_pkt_info_t *packet_info = ep->pkt_info;
++02911         uint32_t offset;
++02912         uint32_t frame_data;
++02913         deptsiz_data_t deptsiz;
++02914 
++02915         if (ep->proc_buf_num == 0) {
++02917                 dma_ad = ep->dma_addr0;
++02918         } else {
++02920                 dma_ad = ep->dma_addr1;
++02921         }
++02922 
++02923         if (ep->is_in) {
++02924                 deptsiz.d32 =
++02925                     DWC_READ_REG32(&core_if->dev_if->
++02926                                    in_ep_regs[ep->num]->dieptsiz);
++02927         } else {
++02928                 deptsiz.d32 =
++02929                     DWC_READ_REG32(&core_if->dev_if->
++02930                                    out_ep_regs[ep->num]->doeptsiz);
++02931         }
++02932 
++02933         if (!deptsiz.b.xfersize) {
++02934                 offset = 0;
++02935                 for (i = 0; i < ep->pkt_cnt; i += ep->pkt_per_frm) {
++02936                         frame_data = ep->data_per_frame;
++02937                         for (j = 0; j < ep->pkt_per_frm; ++j) {
++02938 
++02939                                 /* Packet status - is not set as initially
++02940                                  * it is set to 0 and if packet was sent
++02941                                  successfully, status field will remain 0*/
++02942 
++02943                                 /* Bytes has been transfered */
++02944                                 packet_info->length =
++02945                                     (ep->maxpacket <
++02946                                      frame_data) ? ep->maxpacket : frame_data;
++02947 
++02948                                 /* Received packet offset */
++02949                                 packet_info->offset = offset;
++02950                                 offset += packet_info->length;
++02951                                 frame_data -= packet_info->length;
++02952 
++02953                                 packet_info++;
++02954                         }
++02955                 }
++02956                 return 1;
++02957         } else {
++02958                 /* This is a workaround for in case of Transfer Complete with
++02959                  * PktDrpSts interrupts merging - in this case Transfer complete
++02960                  * interrupt for Isoc Out Endpoint is asserted without PktDrpSts
++02961                  * set and with DOEPTSIZ register non zero. Investigations showed,
++02962                  * that this happens when Out packet is dropped, but because of
++02963                  * interrupts merging during first interrupt handling PktDrpSts
++02964                  * bit is cleared and for next merged interrupts it is not reset.
++02965                  * In this case SW hadles the interrupt as if PktDrpSts bit is set.
++02966                  */
++02967                 if (ep->is_in) {
++02968                         return 1;
++02969                 } else {
++02970                         return handle_iso_out_pkt_dropped(core_if, ep);
++02971                 }
++02972         }
++02973 }
++02974 
++02982 static void complete_iso_ep(dwc_otg_pcd_t * pcd, dwc_otg_pcd_ep_t * ep)
++02983 {
++02984         dwc_otg_core_if_t *core_if = GET_CORE_IF(ep->pcd);
++02985         dwc_ep_t *dwc_ep = &ep->dwc_ep;
++02986         uint8_t is_last = 0;
++02987 
++02988         if (ep->dwc_ep.next_frame == 0xffffffff) {
++02989                 DWC_WARN("Next frame is not set!\n");
++02990                 return;
++02991         }
++02992 
++02993         if (core_if->dma_enable) {
++02994                 if (core_if->dma_desc_enable) {
++02995                         set_ddma_iso_pkts_info(core_if, dwc_ep);
++02996                         reinit_ddma_iso_xfer(core_if, dwc_ep);
++02997                         is_last = 1;
++02998                 } else {
++02999                         if (core_if->pti_enh_enable) {
++03000                                 if (set_iso_pkts_info(core_if, dwc_ep)) {
++03001                                         dwc_ep->proc_buf_num =
++03002                                             (dwc_ep->proc_buf_num ^ 1) & 0x1;
++03003                                         dwc_otg_iso_ep_start_buf_transfer
++03004                                             (core_if, dwc_ep);
++03005                                         is_last = 1;
++03006                                 }
++03007                         } else {
++03008                                 set_current_pkt_info(core_if, dwc_ep);
++03009                                 if (dwc_ep->cur_pkt >= dwc_ep->pkt_cnt) {
++03010                                         is_last = 1;
++03011                                         dwc_ep->cur_pkt = 0;
++03012                                         dwc_ep->proc_buf_num =
++03013                                             (dwc_ep->proc_buf_num ^ 1) & 0x1;
++03014                                         if (dwc_ep->proc_buf_num) {
++03015                                                 dwc_ep->cur_pkt_addr =
++03016                                                     dwc_ep->xfer_buff1;
++03017                                                 dwc_ep->cur_pkt_dma_addr =
++03018                                                     dwc_ep->dma_addr1;
++03019                                         } else {
++03020                                                 dwc_ep->cur_pkt_addr =
++03021                                                     dwc_ep->xfer_buff0;
++03022                                                 dwc_ep->cur_pkt_dma_addr =
++03023                                                     dwc_ep->dma_addr0;
++03024                                         }
++03025 
++03026                                 }
++03027                                 dwc_otg_iso_ep_start_frm_transfer(core_if,
++03028                                                                   dwc_ep);
++03029                         }
++03030                 }
++03031         } else {
++03032                 set_current_pkt_info(core_if, dwc_ep);
++03033                 if (dwc_ep->cur_pkt >= dwc_ep->pkt_cnt) {
++03034                         is_last = 1;
++03035                         dwc_ep->cur_pkt = 0;
++03036                         dwc_ep->proc_buf_num = (dwc_ep->proc_buf_num ^ 1) & 0x1;
++03037                         if (dwc_ep->proc_buf_num) {
++03038                                 dwc_ep->cur_pkt_addr = dwc_ep->xfer_buff1;
++03039                                 dwc_ep->cur_pkt_dma_addr = dwc_ep->dma_addr1;
++03040                         } else {
++03041                                 dwc_ep->cur_pkt_addr = dwc_ep->xfer_buff0;
++03042                                 dwc_ep->cur_pkt_dma_addr = dwc_ep->dma_addr0;
++03043                         }
++03044 
++03045                 }
++03046                 dwc_otg_iso_ep_start_frm_transfer(core_if, dwc_ep);
++03047         }
++03048         if (is_last)
++03049                 dwc_otg_iso_buffer_done(pcd, ep, ep->iso_req_handle);
++03050 }
++03051 #endif /* DWC_EN_ISOC */
++03052 
++03057 static void dwc_otg_pcd_handle_noniso_bna(dwc_otg_pcd_ep_t * ep)
++03058 {
++03059         dwc_ep_t *dwc_ep = &ep->dwc_ep;
++03060         volatile uint32_t *addr;
++03061         depctl_data_t depctl = {.d32 = 0 };
++03062         dwc_otg_pcd_t *pcd = ep->pcd;
++03063         dwc_otg_dev_dma_desc_t *dma_desc;
++03064         dev_dma_desc_sts_t sts = {.d32 = 0 };
++03065         dwc_otg_core_if_t *core_if = ep->pcd->core_if;
++03066         int i, start;
++03067 
++03068         if (!dwc_ep->desc_cnt)
++03069                 DWC_WARN("Descriptor count = %d\n", dwc_ep->desc_cnt);
++03070 
++03071         if (core_if->core_params->cont_on_bna && !dwc_ep->is_in
++03072                                                         && dwc_ep->type != DWC_OTG_EP_TYPE_CONTROL) {
++03073                 uint32_t doepdma;
++03074                 dwc_otg_dev_out_ep_regs_t *out_regs =
++03075                         core_if->dev_if->out_ep_regs[dwc_ep->num];
++03076                 doepdma = DWC_READ_REG32(&(out_regs->doepdma));
++03077                 start = (doepdma - dwc_ep->dma_desc_addr)/sizeof(dwc_otg_dev_dma_desc_t);
++03078                 dma_desc = &(dwc_ep->desc_addr[start]);
++03079         } else {
++03080                 start = 0;
++03081                 dma_desc = dwc_ep->desc_addr;
++03082         }
++03083         
++03084 
++03085         for (i = start; i < dwc_ep->desc_cnt; ++i, ++dma_desc) {
++03086                 sts.d32 = dma_desc->status.d32;
++03087                 sts.b.bs = BS_HOST_READY;
++03088                 dma_desc->status.d32 = sts.d32;
++03089         }
++03090 
++03091         if (dwc_ep->is_in == 0) {
++03092                 addr =
++03093                     &GET_CORE_IF(pcd)->dev_if->out_ep_regs[dwc_ep->
++03094                                                            num]->doepctl;
++03095         } else {
++03096                 addr =
++03097                     &GET_CORE_IF(pcd)->dev_if->in_ep_regs[dwc_ep->num]->diepctl;
++03098         }
++03099         depctl.b.epena = 1;
++03100         depctl.b.cnak = 1;
++03101         DWC_MODIFY_REG32(addr, 0, depctl.d32);
++03102 }
++03103 
++03110 static void handle_ep0(dwc_otg_pcd_t * pcd)
++03111 {
++03112         dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
++03113         dwc_otg_pcd_ep_t *ep0 = &pcd->ep0;
++03114         dev_dma_desc_sts_t desc_sts;
++03115         deptsiz0_data_t deptsiz;
++03116         uint32_t byte_count;
++03117 
++03118 #ifdef DEBUG_EP0
++03119         DWC_DEBUGPL(DBG_PCDV, "%s()\n", __func__);
++03120         print_ep0_state(pcd);
++03121 #endif
++03122 
++03123 //      DWC_PRINTF("HANDLE EP0\n");
++03124 
++03125         switch (pcd->ep0state) {
++03126         case EP0_DISCONNECT:
++03127                 break;
++03128 
++03129         case EP0_IDLE:
++03130                 pcd->request_config = 0;
++03131 
++03132                 pcd_setup(pcd);
++03133                 break;
++03134 
++03135         case EP0_IN_DATA_PHASE:
++03136 #ifdef DEBUG_EP0
++03137                 DWC_DEBUGPL(DBG_PCD, "DATA_IN EP%d-%s: type=%d, mps=%d\n",
++03138                             ep0->dwc_ep.num, (ep0->dwc_ep.is_in ? "IN" : "OUT"),
++03139                             ep0->dwc_ep.type, ep0->dwc_ep.maxpacket);
++03140 #endif
++03141 
++03142                 if (core_if->dma_enable != 0) {
++03143                         /*
++03144                          * For EP0 we can only program 1 packet at a time so we
++03145                          * need to do the make calculations after each complete.
++03146                          * Call write_packet to make the calculations, as in
++03147                          * slave mode, and use those values to determine if we
++03148                          * can complete.
++03149                          */
++03150                         if (core_if->dma_desc_enable == 0) {
++03151                                 deptsiz.d32 =
++03152                                     DWC_READ_REG32(&core_if->
++03153                                                    dev_if->in_ep_regs[0]->
++03154                                                    dieptsiz);
++03155                                 byte_count =
++03156                                     ep0->dwc_ep.xfer_len - deptsiz.b.xfersize;
++03157                         } else {
++03158                                 desc_sts =
++03159                                     core_if->dev_if->in_desc_addr->status;
++03160                                 byte_count =
++03161                                     ep0->dwc_ep.xfer_len - desc_sts.b.bytes;
++03162                         }
++03163                         ep0->dwc_ep.xfer_count += byte_count;
++03164                         ep0->dwc_ep.xfer_buff += byte_count;
++03165                         ep0->dwc_ep.dma_addr += byte_count;
++03166                 }
++03167                 if (ep0->dwc_ep.xfer_count < ep0->dwc_ep.total_len) {
++03168                         dwc_otg_ep0_continue_transfer(GET_CORE_IF(pcd),
++03169                                                       &ep0->dwc_ep);
++03170                         DWC_DEBUGPL(DBG_PCD, "CONTINUE TRANSFER\n");
++03171                 } else if (ep0->dwc_ep.sent_zlp) {
++03172                         dwc_otg_ep0_continue_transfer(GET_CORE_IF(pcd),
++03173                                                       &ep0->dwc_ep);
++03174                         ep0->dwc_ep.sent_zlp = 0;
++03175                         DWC_DEBUGPL(DBG_PCD, "CONTINUE TRANSFER\n");
++03176                 } else {
++03177                         ep0_complete_request(ep0);
++03178                         DWC_DEBUGPL(DBG_PCD, "COMPLETE TRANSFER\n");
++03179                 }
++03180                 break;
++03181         case EP0_OUT_DATA_PHASE:
++03182 #ifdef DEBUG_EP0
++03183                 DWC_DEBUGPL(DBG_PCD, "DATA_OUT EP%d-%s: type=%d, mps=%d\n",
++03184                             ep0->dwc_ep.num, (ep0->dwc_ep.is_in ? "IN" : "OUT"),
++03185                             ep0->dwc_ep.type, ep0->dwc_ep.maxpacket);
++03186 #endif
++03187                 if (core_if->dma_enable != 0) {
++03188                         if (core_if->dma_desc_enable == 0) {
++03189                                 deptsiz.d32 =
++03190                                     DWC_READ_REG32(&core_if->
++03191                                                    dev_if->out_ep_regs[0]->
++03192                                                    doeptsiz);
++03193                                 byte_count =
++03194                                     ep0->dwc_ep.maxpacket - deptsiz.b.xfersize;
++03195                         } else {
++03196                                 desc_sts =
++03197                                     core_if->dev_if->out_desc_addr->status;
++03198                                 byte_count =
++03199                                     ep0->dwc_ep.maxpacket - desc_sts.b.bytes;
++03200                         }
++03201                         ep0->dwc_ep.xfer_count += byte_count;
++03202                         ep0->dwc_ep.xfer_buff += byte_count;
++03203                         ep0->dwc_ep.dma_addr += byte_count;
++03204                 }
++03205                 if (ep0->dwc_ep.xfer_count < ep0->dwc_ep.total_len) {
++03206                         dwc_otg_ep0_continue_transfer(GET_CORE_IF(pcd),
++03207                                                       &ep0->dwc_ep);
++03208                         DWC_DEBUGPL(DBG_PCD, "CONTINUE TRANSFER\n");
++03209                 } else if (ep0->dwc_ep.sent_zlp) {
++03210                         dwc_otg_ep0_continue_transfer(GET_CORE_IF(pcd),
++03211                                                       &ep0->dwc_ep);
++03212                         ep0->dwc_ep.sent_zlp = 0;
++03213                         DWC_DEBUGPL(DBG_PCD, "CONTINUE TRANSFER\n");
++03214                 } else {
++03215                         ep0_complete_request(ep0);
++03216                         DWC_DEBUGPL(DBG_PCD, "COMPLETE TRANSFER\n");
++03217                 }
++03218                 break;
++03219 
++03220         case EP0_IN_STATUS_PHASE:
++03221         case EP0_OUT_STATUS_PHASE:
++03222                 DWC_DEBUGPL(DBG_PCD, "CASE: EP0_STATUS\n");
++03223                 ep0_complete_request(ep0);
++03224                 pcd->ep0state = EP0_IDLE;
++03225                 ep0->stopped = 1;
++03226                 ep0->dwc_ep.is_in = 0;  /* OUT for next SETUP */
++03227 
++03228                 /* Prepare for more SETUP Packets */
++03229                 if (core_if->dma_enable) {
++03230                         ep0_out_start(core_if, pcd);
++03231                 }
++03232                 break;
++03233 
++03234         case EP0_STALL:
++03235                 DWC_ERROR("EP0 STALLed, should not get here pcd_setup()\n");
++03236                 break;
++03237         }
++03238 #ifdef DEBUG_EP0
++03239         print_ep0_state(pcd);
++03240 #endif
++03241 }
++03242 
++03246 static void restart_transfer(dwc_otg_pcd_t * pcd, const uint32_t epnum)
++03247 {
++03248         dwc_otg_core_if_t *core_if;
++03249         dwc_otg_dev_if_t *dev_if;
++03250         deptsiz_data_t dieptsiz = {.d32 = 0 };
++03251         dwc_otg_pcd_ep_t *ep;
++03252 
++03253         ep = get_in_ep(pcd, epnum);
++03254 
++03255 #ifdef DWC_EN_ISOC
++03256         if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) {
++03257                 return;
++03258         }
++03259 #endif /* DWC_EN_ISOC  */
++03260 
++03261         core_if = GET_CORE_IF(pcd);
++03262         dev_if = core_if->dev_if;
++03263 
++03264         dieptsiz.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->dieptsiz);
++03265 
++03266         DWC_DEBUGPL(DBG_PCD, "xfer_buff=%p xfer_count=%0x xfer_len=%0x"
++03267                     " stopped=%d\n", ep->dwc_ep.xfer_buff,
++03268                     ep->dwc_ep.xfer_count, ep->dwc_ep.xfer_len, ep->stopped);
++03269         /*
++03270          * If xfersize is 0 and pktcnt in not 0, resend the last packet.
++03271          */
++03272         if (dieptsiz.b.pktcnt && dieptsiz.b.xfersize == 0 &&
++03273             ep->dwc_ep.start_xfer_buff != 0) {
++03274                 if (ep->dwc_ep.total_len <= ep->dwc_ep.maxpacket) {
++03275                         ep->dwc_ep.xfer_count = 0;
++03276                         ep->dwc_ep.xfer_buff = ep->dwc_ep.start_xfer_buff;
++03277                         ep->dwc_ep.xfer_len = ep->dwc_ep.xfer_count;
++03278                 } else {
++03279                         ep->dwc_ep.xfer_count -= ep->dwc_ep.maxpacket;
++03280                         /* convert packet size to dwords. */
++03281                         ep->dwc_ep.xfer_buff -= ep->dwc_ep.maxpacket;
++03282                         ep->dwc_ep.xfer_len = ep->dwc_ep.xfer_count;
++03283                 }
++03284                 ep->stopped = 0;
++03285                 DWC_DEBUGPL(DBG_PCD, "xfer_buff=%p xfer_count=%0x "
++03286                             "xfer_len=%0x stopped=%d\n",
++03287                             ep->dwc_ep.xfer_buff,
++03288                             ep->dwc_ep.xfer_count, ep->dwc_ep.xfer_len,
++03289                             ep->stopped);
++03290                 if (epnum == 0) {
++03291                         dwc_otg_ep0_start_transfer(core_if, &ep->dwc_ep);
++03292                 } else {
++03293                         dwc_otg_ep_start_transfer(core_if, &ep->dwc_ep);
++03294                 }
++03295         }
++03296 }
++03297 
++03298 /*
++03299  * This function create new nextep sequnce based on Learn Queue.
++03300  *
++03301  * @param core_if Programming view of DWC_otg controller
++03302  */
++03303 void predict_nextep_seq( dwc_otg_core_if_t * core_if)
++03304 {
++03305         dwc_otg_device_global_regs_t *dev_global_regs =
++03306             core_if->dev_if->dev_global_regs;
++03307         const uint32_t TOKEN_Q_DEPTH = core_if->hwcfg2.b.dev_token_q_depth;
++03308         /* Number of Token Queue Registers */
++03309         const int DTKNQ_REG_CNT = (TOKEN_Q_DEPTH + 7) / 8;
++03310         dtknq1_data_t dtknqr1;
++03311         uint32_t in_tkn_epnums[4];
++03312         uint8_t seqnum[MAX_EPS_CHANNELS];
++03313         uint8_t intkn_seq[TOKEN_Q_DEPTH];
++03314         grstctl_t resetctl = {.d32 = 0 };
++03315         uint8_t temp;
++03316         int ndx = 0;
++03317         int start = 0;
++03318         int end = 0;
++03319         int sort_done = 0;
++03320         int i = 0;
++03321         volatile uint32_t *addr = &dev_global_regs->dtknqr1;
++03322 
++03323 
++03324         DWC_DEBUGPL(DBG_PCD,"dev_token_q_depth=%d\n",TOKEN_Q_DEPTH);
++03325 
++03326         /* Read the DTKNQ Registers */
++03327         for (i = 0; i < DTKNQ_REG_CNT; i++) {
++03328                 in_tkn_epnums[i] = DWC_READ_REG32(addr);
++03329                 DWC_DEBUGPL(DBG_PCDV, "DTKNQR%d=0x%08x\n", i + 1,
++03330                             in_tkn_epnums[i]);
++03331                 if (addr == &dev_global_regs->dvbusdis) {
++03332                         addr = &dev_global_regs->dtknqr3_dthrctl;
++03333                 } else {
++03334                         ++addr;
++03335                 }
++03336 
++03337         }
++03338 
++03339         /* Copy the DTKNQR1 data to the bit field. */
++03340         dtknqr1.d32 = in_tkn_epnums[0];
++03341         if (dtknqr1.b.wrap_bit) {
++03342                 ndx = dtknqr1.b.intknwptr;
++03343                 end = ndx -1;
++03344                 if (end < 0) 
++03345                         end = TOKEN_Q_DEPTH -1;
++03346         } else {
++03347                 ndx = 0;
++03348                 end = dtknqr1.b.intknwptr -1;
++03349                 if (end < 0) 
++03350                         end = 0;
++03351         }
++03352         start = ndx;
++03353         
++03354         /* Fill seqnum[] by initial values: EP number + 31 */
++03355         for (i=0; i <= core_if->dev_if->num_in_eps; i++) {
++03356                 seqnum[i] = i +31;
++03357         }
++03358         
++03359         /* Fill intkn_seq[] from in_tkn_epnums[0] */
++03360         for (i=0; i < 6; i++) 
++03361                 intkn_seq[i] = (in_tkn_epnums[0] >> ((7-i) * 4)) & 0xf;
++03362         
++03363         if (TOKEN_Q_DEPTH > 6) {
++03364                 /* Fill intkn_seq[] from in_tkn_epnums[1] */
++03365                 for (i=6; i < 14; i++) 
++03366                         intkn_seq[i] = (in_tkn_epnums[1] >> ((7-(i-6)) * 4)) & 0xf;
++03367         }
++03368         
++03369         if (TOKEN_Q_DEPTH > 14) {
++03370                 /* Fill intkn_seq[] from in_tkn_epnums[1] */
++03371                 for (i=14; i < 22; i++) 
++03372                         intkn_seq[i] = (in_tkn_epnums[2] >> ((7-(i-14)) * 4)) & 0xf;
++03373         }
++03374 
++03375         if (TOKEN_Q_DEPTH > 22) {
++03376                 /* Fill intkn_seq[] from in_tkn_epnums[1] */
++03377                 for (i=22; i < 30; i++) 
++03378                         intkn_seq[i] = (in_tkn_epnums[3] >> ((7-(i-22)) * 4)) & 0xf;
++03379         }
++03380 
++03381         DWC_DEBUGPL(DBG_PCDV,"%s start=%d end=%d intkn_seq[]:\n", __func__, start, end);
++03382         for (i=0; i<TOKEN_Q_DEPTH; i++) 
++03383                 DWC_DEBUGPL(DBG_PCDV,"%d\n", intkn_seq[i]);
++03384 
++03385         /* Update seqnum based on intkn_seq[] */
++03386         i = 0;
++03387         do {
++03388                 seqnum[intkn_seq[ndx]] = i;
++03389                 ndx++;
++03390                 i++;
++03391                 if (ndx == TOKEN_Q_DEPTH) 
++03392                         ndx = 0;
++03393         } while ( i < TOKEN_Q_DEPTH );
++03394         
++03395         /* Mark non active EP's in seqnum[] by 0xff */
++03396         for (i=0; i<=core_if->dev_if->num_in_eps; i++) {
++03397                 if (core_if->nextep_seq[i] == 0xff )
++03398                         seqnum[i] = 0xff;
++03399         }
++03400         
++03401         /* Sort seqnum[] */
++03402         sort_done = 0;
++03403         while (!sort_done) {
++03404                 sort_done = 1;
++03405                 for (i=0; i<core_if->dev_if->num_in_eps; i++) {
++03406                         if (seqnum[i] > seqnum[i+1]) {
++03407                                 temp = seqnum[i];
++03408                                 seqnum[i] = seqnum[i+1];
++03409                                 seqnum[i+1] = temp;
++03410                                 sort_done = 0;
++03411                         }
++03412                 }
++03413         }
++03414 
++03415         ndx = start + seqnum[0];
++03416         if (ndx >= TOKEN_Q_DEPTH) 
++03417                 ndx = ndx % TOKEN_Q_DEPTH;
++03418         core_if->first_in_nextep_seq = intkn_seq[ndx];
++03419         
++03420         /* Update seqnum[] by EP numbers  */
++03421         for (i=0; i<=core_if->dev_if->num_in_eps; i++) {
++03422                 ndx = start + i;
++03423                 if (seqnum[i] < 31) {
++03424                         ndx = start + seqnum[i];
++03425                         if (ndx >= TOKEN_Q_DEPTH) 
++03426                                 ndx = ndx % TOKEN_Q_DEPTH;
++03427                         seqnum[i] = intkn_seq[ndx];
++03428                 } else {
++03429                         if (seqnum[i] < 0xff) {
++03430                                 seqnum[i] = seqnum[i] - 31;
++03431                         } else {
++03432                                 break;
++03433                         }
++03434                 }
++03435         }
++03436 
++03437         /* Update nextep_seq[] based on seqnum[] */
++03438         for (i=0; i<core_if->dev_if->num_in_eps; i++) {
++03439                 if (seqnum[i] != 0xff) {
++03440                         if (seqnum[i+1] != 0xff) {
++03441                                 core_if->nextep_seq[seqnum[i]] = seqnum[i+1];
++03442                         } else {
++03443                                 core_if->nextep_seq[seqnum[i]] = core_if->first_in_nextep_seq;
++03444                                 break;
++03445                         }
++03446                 } else {
++03447                         break;
++03448                 }
++03449         }
++03450         
++03451         DWC_DEBUGPL(DBG_PCDV, "%s first_in_nextep_seq= %2d; nextep_seq[]:\n", 
++03452                 __func__, core_if->first_in_nextep_seq);
++03453         for (i=0; i <= core_if->dev_if->num_in_eps; i++) {
++03454                 DWC_DEBUGPL(DBG_PCDV,"%2d\n", core_if->nextep_seq[i]);
++03455         }
++03456 
++03457         /* Flush the Learning Queue */
++03458         resetctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->grstctl);
++03459         resetctl.b.intknqflsh = 1;
++03460         DWC_WRITE_REG32(&core_if->core_global_regs->grstctl, resetctl.d32);
++03461         
++03462 
++03463 }
++03464 
++03468 static inline void handle_in_ep_disable_intr(dwc_otg_pcd_t * pcd,
++03469                                              const uint32_t epnum)
++03470 {
++03471         dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
++03472         dwc_otg_dev_if_t *dev_if = core_if->dev_if;
++03473         deptsiz_data_t dieptsiz = {.d32 = 0 };
++03474         dctl_data_t dctl = {.d32 = 0 };
++03475         dwc_otg_pcd_ep_t *ep;
++03476         dwc_ep_t *dwc_ep;
++03477         gintmsk_data_t gintmsk_data;
++03478         depctl_data_t depctl;
++03479         uint32_t diepdma;
++03480         uint32_t remain_to_transfer = 0;
++03481         uint8_t i;
++03482         uint32_t xfer_size;
++03483         
++03484         ep = get_in_ep(pcd, epnum);
++03485         dwc_ep = &ep->dwc_ep;
++03486 
++03487         if (dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) {
++03488                 dwc_otg_flush_tx_fifo(core_if, dwc_ep->tx_fifo_num);
++03489                 complete_ep(ep);
++03490                 return;
++03491         }
++03492 
++03493         DWC_DEBUGPL(DBG_PCD, "diepctl%d=%0x\n", epnum,
++03494                     DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->diepctl));
++03495         dieptsiz.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->dieptsiz);
++03496         depctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->diepctl);
++03497 
++03498         DWC_DEBUGPL(DBG_ANY, "pktcnt=%d size=%d\n",
++03499                     dieptsiz.b.pktcnt, dieptsiz.b.xfersize);
++03500         
++03501         if ((core_if->start_predict == 0) || (depctl.b.eptype & 1)) { 
++03502                 if (ep->stopped) {
++03503                         if (core_if->en_multiple_tx_fifo)
++03504                                 /* Flush the Tx FIFO */
++03505                                 dwc_otg_flush_tx_fifo(core_if, dwc_ep->tx_fifo_num);
++03506                         /* Clear the Global IN NP NAK */
++03507                         dctl.d32 = 0;
++03508                         dctl.b.cgnpinnak = 1;
++03509                         DWC_MODIFY_REG32(&dev_if->dev_global_regs->dctl, dctl.d32, dctl.d32); 
++03510                         /* Restart the transaction */
++03511                         if (dieptsiz.b.pktcnt != 0 || dieptsiz.b.xfersize != 0) {
++03512                                 restart_transfer(pcd, epnum);
++03513                         }
++03514                 } else {
++03515                         /* Restart the transaction */
++03516                         if (dieptsiz.b.pktcnt != 0 || dieptsiz.b.xfersize != 0) {
++03517                                 restart_transfer(pcd, epnum);
++03518                         }
++03519                         DWC_DEBUGPL(DBG_ANY, "STOPPED!!!\n");
++03520                 }
++03521                 return;
++03522         }
++03523 
++03524         if (core_if->start_predict > 2) {       // NP IN EP
++03525                 core_if->start_predict--;
++03526                 return;
++03527         }
++03528 
++03529         core_if->start_predict--;
++03530         
++03531         if (core_if->start_predict == 1) {      // All NP IN Ep's disabled now
++03532 
++03533                 predict_nextep_seq(core_if);
++03534                         
++03535                 /* Update all active IN EP's NextEP field based of nextep_seq[] */
++03536                 for ( i = 0; i <= core_if->dev_if->num_in_eps; i++) {
++03537                         depctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl);
++03538                         if (core_if->nextep_seq[i] != 0xff) {   // Active NP IN EP
++03539                                 depctl.b.nextep = core_if->nextep_seq[i];
++03540                                 DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->diepctl, depctl.d32);
++03541                         }
++03542                 }
++03543                 /* Flush Shared NP TxFIFO */
++03544                 dwc_otg_flush_tx_fifo(core_if, 0);
++03545                 /* Rewind buffers */
++03546                 if (!core_if->dma_desc_enable) {                
++03547                         i = core_if->first_in_nextep_seq;
++03548                         do {
++03549                                 ep = get_in_ep(pcd, i);
++03550                                 dieptsiz.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[i]->dieptsiz);
++03551                                 xfer_size = ep->dwc_ep.total_len - ep->dwc_ep.xfer_count;
++03552                                 if (xfer_size > ep->dwc_ep.maxxfer) 
++03553                                         xfer_size = ep->dwc_ep.maxxfer;
++03554                                 depctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl);
++03555                                 if (dieptsiz.b.pktcnt != 0) {
++03556                                         if (xfer_size == 0) {
++03557                                                 remain_to_transfer = 0;
++03558                                         } else {
++03559                                                 if ((xfer_size % ep->dwc_ep.maxpacket) == 0) {
++03560                                                         remain_to_transfer = 
++03561                                                                 dieptsiz.b.pktcnt * ep->dwc_ep.maxpacket;
++03562                                                 } else {
++03563                                                         remain_to_transfer = ((dieptsiz.b.pktcnt -1) * ep->dwc_ep.maxpacket) 
++03564                                                                 + (xfer_size % ep->dwc_ep.maxpacket);
++03565                                                 }
++03566                                         }
++03567                                         diepdma = DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepdma);
++03568                                         dieptsiz.b.xfersize = remain_to_transfer;
++03569                                         DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->dieptsiz, dieptsiz.d32);
++03570                                         diepdma = ep->dwc_ep.dma_addr + (xfer_size - remain_to_transfer);
++03571                                         DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->diepdma, diepdma);
++03572                                 }
++03573                                 i = core_if->nextep_seq[i];
++03574                         } while (i != core_if->first_in_nextep_seq);
++03575                 } else { // dma_desc_enable
++03576                                 DWC_PRINTF("%s Learning Queue not supported in DDMA\n", __func__);
++03577                 }
++03578                                 
++03579                 /* Restart transfers in predicted sequences */
++03580                 i = core_if->first_in_nextep_seq;
++03581                 do {
++03582                         dieptsiz.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[i]->dieptsiz);
++03583                         depctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl);
++03584                         if (dieptsiz.b.pktcnt != 0) {
++03585                                 depctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl);
++03586                                 depctl.b.epena = 1;
++03587                                 depctl.b.cnak = 1;
++03588                                 DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->diepctl, depctl.d32);
++03589                         }
++03590                         i = core_if->nextep_seq[i];
++03591                 } while (i != core_if->first_in_nextep_seq);
++03592 
++03593                 /* Clear the global non-periodic IN NAK handshake */
++03594                 dctl.d32 = 0;
++03595                 dctl.b.cgnpinnak = 1;
++03596                 DWC_MODIFY_REG32(&dev_if->dev_global_regs->dctl, dctl.d32, dctl.d32); 
++03597                         
++03598                 /* Unmask EP Mismatch interrupt */
++03599                 gintmsk_data.d32 = 0;
++03600                 gintmsk_data.b.epmismatch = 1;
++03601                 DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, 0, gintmsk_data.d32);
++03602                 
++03603                 core_if->start_predict = 0;
++03604 
++03605         } 
++03606 }
++03607 
++03611 static inline void handle_in_ep_timeout_intr(dwc_otg_pcd_t * pcd,
++03612                                              const uint32_t epnum)
++03613 {
++03614         dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
++03615         dwc_otg_dev_if_t *dev_if = core_if->dev_if;
++03616 
++03617 #ifdef DEBUG
++03618         deptsiz_data_t dieptsiz = {.d32 = 0 };
++03619         uint32_t num = 0;
++03620 #endif
++03621         dctl_data_t dctl = {.d32 = 0 };
++03622         dwc_otg_pcd_ep_t *ep;
++03623 
++03624         gintmsk_data_t intr_mask = {.d32 = 0 };
++03625 
++03626         ep = get_in_ep(pcd, epnum);
++03627 
++03628         /* Disable the NP Tx Fifo Empty Interrrupt */
++03629         if (!core_if->dma_enable) {
++03630                 intr_mask.b.nptxfempty = 1;
++03631                 DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk,
++03632                                  intr_mask.d32, 0);
++03633         }
++03636         /*
++03637          * Non-periodic EP
++03638          */
++03639         /* Enable the Global IN NAK Effective Interrupt */
++03640         intr_mask.b.ginnakeff = 1;
++03641         DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, 0, intr_mask.d32);
++03642 
++03643         /* Set Global IN NAK */
++03644         dctl.b.sgnpinnak = 1;
++03645         DWC_MODIFY_REG32(&dev_if->dev_global_regs->dctl, dctl.d32, dctl.d32);
++03646 
++03647         ep->stopped = 1;
++03648 
++03649 #ifdef DEBUG
++03650         dieptsiz.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[num]->dieptsiz);
++03651         DWC_DEBUGPL(DBG_ANY, "pktcnt=%d size=%d\n",
++03652                     dieptsiz.b.pktcnt, dieptsiz.b.xfersize);
++03653 #endif
++03654 
++03655 #ifdef DISABLE_PERIODIC_EP
++03656         /*
++03657          * Set the NAK bit for this EP to
++03658          * start the disable process.
++03659          */
++03660         diepctl.d32 = 0;
++03661         diepctl.b.snak = 1;
++03662         DWC_MODIFY_REG32(&dev_if->in_ep_regs[num]->diepctl, diepctl.d32,
++03663                          diepctl.d32);
++03664         ep->disabling = 1;
++03665         ep->stopped = 1;
++03666 #endif
++03667 }
++03668 
++03672 static inline int32_t handle_in_ep_nak_intr(dwc_otg_pcd_t * pcd,
++03673                                             const uint32_t epnum)
++03674 {
++03676         dwc_otg_core_if_t *core_if;
++03677         diepmsk_data_t intr_mask = {.d32 = 0 };
++03678 
++03679         DWC_PRINTF("INTERRUPT Handler not implemented for %s\n", "IN EP NAK");
++03680         core_if = GET_CORE_IF(pcd);
++03681         intr_mask.b.nak = 1;
++03682 
++03683         if (core_if->multiproc_int_enable) {
++03684                 DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->
++03685                                  diepeachintmsk[epnum], intr_mask.d32, 0);
++03686         } else {
++03687                 DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->diepmsk,
++03688                                  intr_mask.d32, 0);
++03689         }
++03690 
++03691         return 1;
++03692 }
++03693 
++03697 static inline int32_t handle_out_ep_babble_intr(dwc_otg_pcd_t * pcd,
++03698                                                 const uint32_t epnum)
++03699 {
++03701         dwc_otg_core_if_t *core_if;
++03702         doepmsk_data_t intr_mask = {.d32 = 0 };
++03703 
++03704         DWC_PRINTF("INTERRUPT Handler not implemented for %s\n",
++03705                    "OUT EP Babble");
++03706         core_if = GET_CORE_IF(pcd);
++03707         intr_mask.b.babble = 1;
++03708 
++03709         if (core_if->multiproc_int_enable) {
++03710                 DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->
++03711                                  doepeachintmsk[epnum], intr_mask.d32, 0);
++03712         } else {
++03713                 DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->doepmsk,
++03714                                  intr_mask.d32, 0);
++03715         }
++03716 
++03717         return 1;
++03718 }
++03719 
++03723 static inline int32_t handle_out_ep_nak_intr(dwc_otg_pcd_t * pcd,
++03724                                              const uint32_t epnum)
++03725 {
++03727         dwc_otg_core_if_t *core_if;
++03728         doepmsk_data_t intr_mask = {.d32 = 0 };
++03729 
++03730         DWC_PRINTF("INTERRUPT Handler not implemented for %s\n", "OUT EP NAK");
++03731         core_if = GET_CORE_IF(pcd);
++03732         intr_mask.b.nak = 1;
++03733 
++03734         if (core_if->multiproc_int_enable) {
++03735                 DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->
++03736                                  doepeachintmsk[epnum], intr_mask.d32, 0);
++03737         } else {
++03738                 DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->doepmsk,
++03739                                  intr_mask.d32, 0);
++03740         }
++03741 
++03742         return 1;
++03743 }
++03744 
++03748 static inline int32_t handle_out_ep_nyet_intr(dwc_otg_pcd_t * pcd,
++03749                                               const uint32_t epnum)
++03750 {
++03752         dwc_otg_core_if_t *core_if;
++03753         doepmsk_data_t intr_mask = {.d32 = 0 };
++03754 
++03755         DWC_PRINTF("INTERRUPT Handler not implemented for %s\n", "OUT EP NYET");
++03756         core_if = GET_CORE_IF(pcd);
++03757         intr_mask.b.nyet = 1;
++03758 
++03759         if (core_if->multiproc_int_enable) {
++03760                 DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->
++03761                                  doepeachintmsk[epnum], intr_mask.d32, 0);
++03762         } else {
++03763                 DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->doepmsk,
++03764                                  intr_mask.d32, 0);
++03765         }
++03766 
++03767         return 1;
++03768 }
++03769 
++03786 static int32_t dwc_otg_pcd_handle_in_ep_intr(dwc_otg_pcd_t * pcd)
++03787 {
++03788 #define CLEAR_IN_EP_INTR(__core_if,__epnum,__intr) \
++03789 do { \
++03790                 diepint_data_t diepint = {.d32=0}; \
++03791                 diepint.b.__intr = 1; \
++03792                 DWC_WRITE_REG32(&__core_if->dev_if->in_ep_regs[__epnum]->diepint, \
++03793                 diepint.d32); \
++03794 } while (0)
++03795 
++03796         dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
++03797         dwc_otg_dev_if_t *dev_if = core_if->dev_if;
++03798         diepint_data_t diepint = {.d32 = 0 };
++03799         depctl_data_t depctl = {.d32 = 0 };
++03800         uint32_t ep_intr;
++03801         uint32_t epnum = 0;
++03802         dwc_otg_pcd_ep_t *ep;
++03803         dwc_ep_t *dwc_ep;
++03804         gintmsk_data_t intr_mask = {.d32 = 0 };
++03805 
++03806         DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, pcd);
++03807 
++03808         /* Read in the device interrupt bits */
++03809         ep_intr = dwc_otg_read_dev_all_in_ep_intr(core_if);
++03810 
++03811         /* Service the Device IN interrupts for each endpoint */
++03812         while (ep_intr) {
++03813                 if (ep_intr & 0x1) {
++03814                         uint32_t empty_msk;
++03815                         /* Get EP pointer */
++03816                         ep = get_in_ep(pcd, epnum);
++03817                         dwc_ep = &ep->dwc_ep;
++03818 
++03819                         depctl.d32 =
++03820                             DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->diepctl);
++03821                         empty_msk =
++03822                             DWC_READ_REG32(&dev_if->
++03823                                            dev_global_regs->dtknqr4_fifoemptymsk);
++03824 
++03825                         DWC_DEBUGPL(DBG_PCDV,
++03826                                     "IN EP INTERRUPT - %d\nepmty_msk - %8x  diepctl - %8x\n",
++03827                                     epnum, empty_msk, depctl.d32);
++03828 
++03829                         DWC_DEBUGPL(DBG_PCD,
++03830                                     "EP%d-%s: type=%d, mps=%d\n",
++03831                                     dwc_ep->num, (dwc_ep->is_in ? "IN" : "OUT"),
++03832                                     dwc_ep->type, dwc_ep->maxpacket);
++03833 
++03834                         diepint.d32 =
++03835                             dwc_otg_read_dev_in_ep_intr(core_if, dwc_ep);
++03836 
++03837                         DWC_DEBUGPL(DBG_PCDV,
++03838                                     "EP %d Interrupt Register - 0x%x\n", epnum,
++03839                                     diepint.d32);
++03840                         /* Transfer complete */
++03841                         if (diepint.b.xfercompl) {
++03842                                 /* Disable the NP Tx FIFO Empty
++03843                                  * Interrrupt */
++03844                                 if (core_if->en_multiple_tx_fifo == 0) {
++03845                                         intr_mask.b.nptxfempty = 1;
++03846                                         DWC_MODIFY_REG32
++03847                                             (&core_if->core_global_regs->gintmsk,
++03848                                              intr_mask.d32, 0);
++03849                                 } else {
++03850                                         /* Disable the Tx FIFO Empty Interrupt for this EP */
++03851                                         uint32_t fifoemptymsk =
++03852                                             0x1 << dwc_ep->num;
++03853                                         DWC_MODIFY_REG32(&core_if->
++03854                                                          dev_if->dev_global_regs->dtknqr4_fifoemptymsk,
++03855                                                          fifoemptymsk, 0);
++03856                                 }
++03857                                 /* Clear the bit in DIEPINTn for this interrupt */
++03858                                 CLEAR_IN_EP_INTR(core_if, epnum, xfercompl);
++03859 
++03860                                 /* Complete the transfer */
++03861                                 if (epnum == 0) {
++03862                                         handle_ep0(pcd);
++03863                                 }
++03864 #ifdef DWC_EN_ISOC
++03865                                 else if (dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) {
++03866                                         if (!ep->stopped)
++03867                                                 complete_iso_ep(pcd, ep);
++03868                                 }
++03869 #endif /* DWC_EN_ISOC */
++03870 #ifdef DWC_UTE_PER_IO
++03871                                 else if (dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) {
++03872                                         if (!ep->stopped)
++03873                                                 complete_xiso_ep(ep);
++03874                                 }
++03875 #endif /* DWC_UTE_PER_IO */
++03876                                 else {
++03877                                         if (dwc_ep->type == DWC_OTG_EP_TYPE_ISOC && 
++03878                                                         dwc_ep->bInterval > 1) {
++03879                                                 dwc_ep->frame_num += dwc_ep->bInterval;
++03880                                                 if (dwc_ep->frame_num > 0x3FFF)
++03881                                                 {
++03882                                                         dwc_ep->frm_overrun = 1;
++03883                                                         dwc_ep->frame_num &= 0x3FFF;
++03884                                                 } else 
++03885                                                         dwc_ep->frm_overrun = 0;
++03886                                         }
++03887                                         complete_ep(ep);
++03888                                         if(diepint.b.nak)
++03889                                                 CLEAR_IN_EP_INTR(core_if, epnum, nak);
++03890                                 }
++03891                         }
++03892                         /* Endpoint disable      */
++03893                         if (diepint.b.epdisabled) {
++03894                                 DWC_DEBUGPL(DBG_ANY, "EP%d IN disabled\n",
++03895                                             epnum);
++03896                                 handle_in_ep_disable_intr(pcd, epnum);
++03897 
++03898                                 /* Clear the bit in DIEPINTn for this interrupt */
++03899                                 CLEAR_IN_EP_INTR(core_if, epnum, epdisabled);
++03900                         }
++03901                         /* AHB Error */
++03902                         if (diepint.b.ahberr) {
++03903                                 DWC_ERROR("EP%d IN AHB Error\n", epnum);
++03904                                 /* Clear the bit in DIEPINTn for this interrupt */
++03905                                 CLEAR_IN_EP_INTR(core_if, epnum, ahberr);
++03906                         }
++03907                         /* TimeOUT Handshake (non-ISOC IN EPs) */
++03908                         if (diepint.b.timeout) {
++03909                                 DWC_ERROR("EP%d IN Time-out\n", epnum);
++03910                                 handle_in_ep_timeout_intr(pcd, epnum);
++03911 
++03912                                 CLEAR_IN_EP_INTR(core_if, epnum, timeout);
++03913                         }
++03915                         if (diepint.b.intktxfemp) {
++03916                                 DWC_DEBUGPL(DBG_ANY,
++03917                                             "EP%d IN TKN TxFifo Empty\n",
++03918                                             epnum);
++03919                                 if (!ep->stopped && epnum != 0) {
++03920 
++03921                                         diepmsk_data_t diepmsk = {.d32 = 0 };
++03922                                         diepmsk.b.intktxfemp = 1;
++03923 
++03924                                         if (core_if->multiproc_int_enable) {
++03925                                                 DWC_MODIFY_REG32
++03926                                                     (&dev_if->dev_global_regs->diepeachintmsk
++03927                                                      [epnum], diepmsk.d32, 0);
++03928                                         } else {
++03929                                                 DWC_MODIFY_REG32
++03930                                                     (&dev_if->dev_global_regs->diepmsk,
++03931                                                      diepmsk.d32, 0);
++03932                                         }
++03933                                 } else if (core_if->dma_desc_enable
++03934                                            && epnum == 0
++03935                                            && pcd->ep0state ==
++03936                                            EP0_OUT_STATUS_PHASE) {
++03937                                         // EP0 IN set STALL
++03938                                         depctl.d32 =
++03939                                             DWC_READ_REG32(&dev_if->in_ep_regs
++03940                                                            [epnum]->diepctl);
++03941 
++03942                                         /* set the disable and stall bits */
++03943                                         if (depctl.b.epena) {
++03944                                                 depctl.b.epdis = 1;
++03945                                         }
++03946                                         depctl.b.stall = 1;
++03947                                         DWC_WRITE_REG32(&dev_if->in_ep_regs
++03948                                                         [epnum]->diepctl,
++03949                                                         depctl.d32);
++03950                                 }
++03951                                 CLEAR_IN_EP_INTR(core_if, epnum, intktxfemp);
++03952                         }
++03954                         if (diepint.b.intknepmis) {
++03955                                 DWC_DEBUGPL(DBG_ANY,
++03956                                             "EP%d IN TKN EP Mismatch\n", epnum);
++03957                                 CLEAR_IN_EP_INTR(core_if, epnum, intknepmis);                           
++03958                         }
++03960                         if (diepint.b.inepnakeff) {
++03961                                 DWC_DEBUGPL(DBG_ANY,
++03962                                             "EP%d IN EP NAK Effective\n",
++03963                                             epnum);
++03964                                 /* Periodic EP */
++03965                                 if (ep->disabling) {
++03966                                         depctl.d32 = 0;
++03967                                         depctl.b.snak = 1;
++03968                                         depctl.b.epdis = 1;
++03969                                         DWC_MODIFY_REG32(&dev_if->in_ep_regs
++03970                                                          [epnum]->diepctl,
++03971                                                          depctl.d32,
++03972                                                          depctl.d32);
++03973                                 }
++03974                                 CLEAR_IN_EP_INTR(core_if, epnum, inepnakeff);
++03975 
++03976                         }
++03977 
++03979                         if (diepint.b.emptyintr) {
++03980                                 DWC_DEBUGPL(DBG_ANY,
++03981                                             "EP%d Tx FIFO Empty Intr \n",
++03982                                             epnum);
++03983                                 write_empty_tx_fifo(pcd, epnum);
++03984 
++03985                                 CLEAR_IN_EP_INTR(core_if, epnum, emptyintr);
++03986 
++03987                         }
++03988 
++03990                         if (diepint.b.bna) {
++03991                                 CLEAR_IN_EP_INTR(core_if, epnum, bna);
++03992                                 if (core_if->dma_desc_enable) {
++03993 #ifdef DWC_EN_ISOC
++03994                                         if (dwc_ep->type ==
++03995                                             DWC_OTG_EP_TYPE_ISOC) {
++03996                                                 /*
++03997                                                  * This checking is performed to prevent first "false" BNA
++03998                                                  * handling occuring right after reconnect
++03999                                                  */
++04000                                                 if (dwc_ep->next_frame !=
++04001                                                     0xffffffff)
++04002                                                         dwc_otg_pcd_handle_iso_bna(ep);
++04003                                         } else
++04004 #endif                          /* DWC_EN_ISOC */
++04005                                         {
++04006                                                 dwc_otg_pcd_handle_noniso_bna(ep);
++04007                                         }
++04008                                 }
++04009                         }
++04010                         /* NAK Interrutp */
++04011                         if (diepint.b.nak) {
++04012                                 DWC_DEBUGPL(DBG_ANY, "EP%d IN NAK Interrupt\n",
++04013                                             epnum);
++04014                                 if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC)
++04015                                 {
++04016                                         depctl_data_t depctl;
++04017                                         if (ep->dwc_ep.frame_num == 0xFFFFFFFF) 
++04018                                         {
++04019                                                 ep->dwc_ep.frame_num = core_if->frame_num;
++04020                                                 if (ep->dwc_ep.bInterval > 1) 
++04021                                                 {
++04022                                                         depctl.d32 = 0;
++04023                                                         depctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->diepctl);
++04024                                                         if (ep->dwc_ep.frame_num & 0x1) {
++04025                                                                 depctl.b.setd1pid = 1;
++04026                                                                 depctl.b.setd0pid = 0;
++04027                                                         } else {
++04028                                                                 depctl.b.setd0pid = 1;
++04029                                                                 depctl.b.setd1pid = 0;
++04030                                                         }
++04031                                                         DWC_WRITE_REG32(&dev_if->in_ep_regs[epnum]->diepctl, depctl.d32);
++04032                                                 }
++04033                                                 start_next_request(ep);
++04034                                         }
++04035                                         ep->dwc_ep.frame_num += ep->dwc_ep.bInterval;
++04036                                         if (dwc_ep->frame_num > 0x3FFF)
++04037                                         {
++04038                                                 dwc_ep->frm_overrun = 1;
++04039                                                 dwc_ep->frame_num &= 0x3FFF;
++04040                                         } else 
++04041                                                 dwc_ep->frm_overrun = 0;
++04042                                 }
++04043 
++04044                                 CLEAR_IN_EP_INTR(core_if, epnum, nak);
++04045                         }
++04046                 }
++04047                 epnum++;
++04048                 ep_intr >>= 1;
++04049         }
++04050 
++04051         return 1;
++04052 #undef CLEAR_IN_EP_INTR
++04053 }
++04054 
++04068 static int32_t dwc_otg_pcd_handle_out_ep_intr(dwc_otg_pcd_t * pcd)
++04069 {
++04070 #define CLEAR_OUT_EP_INTR(__core_if,__epnum,__intr) \
++04071 do { \
++04072                 doepint_data_t doepint = {.d32=0}; \
++04073                 doepint.b.__intr = 1; \
++04074                 DWC_WRITE_REG32(&__core_if->dev_if->out_ep_regs[__epnum]->doepint, \
++04075                 doepint.d32); \
++04076 } while (0)
++04077 
++04078         dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
++04079         uint32_t ep_intr;
++04080         doepint_data_t doepint = {.d32 = 0 };
++04081         uint32_t epnum = 0;
++04082         dwc_otg_pcd_ep_t *ep;
++04083         dwc_ep_t *dwc_ep;
++04084         dctl_data_t dctl = {.d32 = 0 };
++04085         gintmsk_data_t gintmsk = {.d32 = 0 };
++04086 
++04087 
++04088         DWC_DEBUGPL(DBG_PCDV, "%s()\n", __func__);
++04089 
++04090         /* Read in the device interrupt bits */
++04091         ep_intr = dwc_otg_read_dev_all_out_ep_intr(core_if);
++04092 
++04093         while (ep_intr) {
++04094                 if (ep_intr & 0x1) {
++04095                         /* Get EP pointer */
++04096                         ep = get_out_ep(pcd, epnum);
++04097                         dwc_ep = &ep->dwc_ep;
++04098 
++04099 #ifdef VERBOSE
++04100                         DWC_DEBUGPL(DBG_PCDV,
++04101                                     "EP%d-%s: type=%d, mps=%d\n",
++04102                                     dwc_ep->num, (dwc_ep->is_in ? "IN" : "OUT"),
++04103                                     dwc_ep->type, dwc_ep->maxpacket);
++04104 #endif
++04105                         doepint.d32 =
++04106                             dwc_otg_read_dev_out_ep_intr(core_if, dwc_ep);
++04107 
++04108                         /* Transfer complete */
++04109                         if (doepint.b.xfercompl) {
++04110 
++04111                                 if (epnum == 0) {
++04112                                         /* Clear the bit in DOEPINTn for this interrupt */
++04113                                         CLEAR_OUT_EP_INTR(core_if, epnum,
++04114                                                           xfercompl);
++04115                                         if (core_if->dma_desc_enable == 0
++04116                                             || pcd->ep0state != EP0_IDLE)
++04117                                                 handle_ep0(pcd);
++04118 #ifdef DWC_EN_ISOC
++04119                                 } else if (dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) {
++04120                                         if (doepint.b.pktdrpsts == 0) {
++04121                                                 /* Clear the bit in DOEPINTn for this interrupt */
++04122                                                 CLEAR_OUT_EP_INTR(core_if,
++04123                                                                   epnum,
++04124                                                                   xfercompl);
++04125                                                 complete_iso_ep(pcd, ep);
++04126                                         } else {
++04127 
++04128                                                 doepint_data_t doepint = {.d32 = 0 };
++04129                                                 doepint.b.xfercompl = 1;
++04130                                                 doepint.b.pktdrpsts = 1;
++04131                                                 DWC_WRITE_REG32
++04132                                                     (&core_if->dev_if->out_ep_regs
++04133                                                      [epnum]->doepint,
++04134                                                      doepint.d32);
++04135                                                 if (handle_iso_out_pkt_dropped
++04136                                                     (core_if, dwc_ep)) {
++04137                                                         complete_iso_ep(pcd,
++04138                                                                         ep);
++04139                                                 }
++04140                                         }
++04141 #endif /* DWC_EN_ISOC */
++04142 #ifdef DWC_UTE_PER_IO
++04143                                 } else if (dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) {
++04144                                         CLEAR_OUT_EP_INTR(core_if, epnum, xfercompl);
++04145                                         if (!ep->stopped)
++04146                                                 complete_xiso_ep(ep);
++04147 #endif /* DWC_UTE_PER_IO */
++04148                                 } else {
++04149                                         /* Clear the bit in DOEPINTn for this interrupt */
++04150                                         CLEAR_OUT_EP_INTR(core_if, epnum,
++04151                                                           xfercompl);
++04152 
++04153                                         if (core_if->core_params->dev_out_nak) {
++04154                                                 DWC_TIMER_CANCEL(pcd->core_if->ep_xfer_timer[epnum]);
++04155                                                 pcd->core_if->ep_xfer_info[epnum].state = 0;
++04156 #ifdef DEBUG
++04157                                                 print_memory_payload(pcd, dwc_ep);
++04158 #endif
++04159                                         }
++04160                                         complete_ep(ep);                                                
++04161                                 }
++04162 
++04163                         }
++04164 
++04165                         /* Endpoint disable      */
++04166                         if (doepint.b.epdisabled) {
++04167 
++04168                                 /* Clear the bit in DOEPINTn for this interrupt */
++04169                                 CLEAR_OUT_EP_INTR(core_if, epnum, epdisabled);
++04170                                 if (core_if->core_params->dev_out_nak) {
++04171 #ifdef DEBUG
++04172                                         print_memory_payload(pcd, dwc_ep);
++04173 #endif
++04174                                         /* In case of timeout condition */
++04175                                         if (core_if->ep_xfer_info[epnum].state == 2) {
++04176                                                 dctl.d32 = DWC_READ_REG32(&core_if->dev_if->
++04177                                                                                 dev_global_regs->dctl);
++04178                                                 dctl.b.cgoutnak = 1;
++04179                                                 DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl,
++04180                                                                                                                                 dctl.d32);
++04181                                                 /* Unmask goutnakeff interrupt which was masked
++04182                                                  * during handle nak out interrupt */
++04183                                                 gintmsk.b.goutnakeff = 1;
++04184                                                 DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk,
++04185                                                                                                                                 0, gintmsk.d32);
++04186                                         
++04187                                                 complete_ep(ep);
++04188                                         }
++04189                                 }
++04190                                 if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC)
++04191                                 {
++04192                                         dctl_data_t dctl;
++04193                                         gintmsk_data_t intr_mask = {.d32 = 0};
++04194                                         dwc_otg_pcd_request_t *req = 0;
++04195 
++04196                                         dctl.d32 = DWC_READ_REG32(&core_if->dev_if->
++04197                                                 dev_global_regs->dctl);
++04198                                         dctl.b.cgoutnak = 1;
++04199                                         DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl,
++04200                                                 dctl.d32);
++04201 
++04202                                         intr_mask.d32 = 0;
++04203                                         intr_mask.b.incomplisoout = 1;     
++04204 
++04205                                         /* Get any pending requests */
++04206                                         if (!DWC_CIRCLEQ_EMPTY(&ep->queue)) {
++04207                                                 req = DWC_CIRCLEQ_FIRST(&ep->queue);
++04208                                                 if (!req) {
++04209                                                         DWC_PRINTF("complete_ep 0x%p, req = NULL!\n", ep);
++04210                                                 } else {
++04211                                                         dwc_otg_request_done(ep, req, 0);
++04212                                                         start_next_request(ep);
++04213                                                 }
++04214                                         } else {
++04215                                                 DWC_PRINTF("complete_ep 0x%p, ep->queue empty!\n", ep);
++04216                                         }
++04217                                 }
++04218                         }
++04219                         /* AHB Error */
++04220                         if (doepint.b.ahberr) {
++04221                                 DWC_ERROR("EP%d OUT AHB Error\n", epnum);
++04222                                 DWC_ERROR("EP%d DEPDMA=0x%08x \n",
++04223                                           epnum, core_if->dev_if->out_ep_regs[epnum]->doepdma);
++04224                                 CLEAR_OUT_EP_INTR(core_if, epnum, ahberr);
++04225                         }
++04226                         /* Setup Phase Done (contorl EPs) */
++04227                         if (doepint.b.setup) {
++04228 #ifdef DEBUG_EP0
++04229                                 DWC_DEBUGPL(DBG_PCD, "EP%d SETUP Done\n",
++04230                                             epnum);
++04231 #endif
++04232                                 CLEAR_OUT_EP_INTR(core_if, epnum, setup);
++04233 
++04234                                 handle_ep0(pcd);
++04235                         }
++04236 
++04238                         if (doepint.b.bna) {
++04239                                 CLEAR_OUT_EP_INTR(core_if, epnum, bna);
++04240                                 if (core_if->dma_desc_enable) {
++04241 #ifdef DWC_EN_ISOC
++04242                                         if (dwc_ep->type ==
++04243                                             DWC_OTG_EP_TYPE_ISOC) {
++04244                                                 /*
++04245                                                  * This checking is performed to prevent first "false" BNA
++04246                                                  * handling occuring right after reconnect
++04247                                                  */
++04248                                                 if (dwc_ep->next_frame !=
++04249                                                     0xffffffff)
++04250                                                         dwc_otg_pcd_handle_iso_bna(ep);
++04251                                         } else
++04252 #endif                          /* DWC_EN_ISOC */
++04253                                         {
++04254                                                 dwc_otg_pcd_handle_noniso_bna(ep);
++04255                                         }
++04256                                 }
++04257                         }
++04258                         if (doepint.b.stsphsercvd) {
++04259                                 CLEAR_OUT_EP_INTR(core_if, epnum, stsphsercvd);
++04260                                 if (core_if->dma_desc_enable) {
++04261                                         do_setup_in_status_phase(pcd);
++04262                                 }
++04263                         }
++04264                         /* Babble Interrutp */
++04265                         if (doepint.b.babble) {
++04266                                 DWC_DEBUGPL(DBG_ANY, "EP%d OUT Babble\n",
++04267                                             epnum);
++04268                                 handle_out_ep_babble_intr(pcd, epnum);
++04269 
++04270                                 CLEAR_OUT_EP_INTR(core_if, epnum, babble);
++04271                         }
++04272                         if (doepint.b.outtknepdis)
++04273                         {
++04274                                 DWC_DEBUGPL(DBG_ANY, "EP%d OUT Token received when EP is \
++04275                                         disabled\n",epnum);
++04276                                 if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC)
++04277                                 {
++04278                                         doepmsk_data_t doepmsk = {.d32 = 0};
++04279                                         ep->dwc_ep.frame_num = core_if->frame_num;
++04280                                         if (ep->dwc_ep.bInterval > 1) 
++04281                                         {
++04282                                                 depctl_data_t depctl;
++04283                                                 depctl.d32 = DWC_READ_REG32(&core_if->dev_if->
++04284                                                                                                         out_ep_regs[epnum]->doepctl);
++04285                                                 if (ep->dwc_ep.frame_num & 0x1) {
++04286                                                         depctl.b.setd1pid = 1;
++04287                                                         depctl.b.setd0pid = 0;
++04288                                                 } else {
++04289                                                         depctl.b.setd0pid = 1;
++04290                                                         depctl.b.setd1pid = 0;
++04291                                                 }
++04292                                                 DWC_WRITE_REG32(&core_if->dev_if->
++04293                                                                                 out_ep_regs[epnum]->doepctl, depctl.d32);
++04294                                         }
++04295                                         start_next_request(ep);
++04296                                         doepmsk.b.outtknepdis = 1;
++04297                                         DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->doepmsk, 
++04298                                                                  doepmsk.d32, 0);
++04299                                 }
++04300                                 CLEAR_OUT_EP_INTR(core_if, epnum, outtknepdis);
++04301                         }
++04302                         
++04303                         /* NAK Interrutp */
++04304                         if (doepint.b.nak) {
++04305                                 DWC_DEBUGPL(DBG_ANY, "EP%d OUT NAK\n", epnum);
++04306                                 handle_out_ep_nak_intr(pcd, epnum);
++04307 
++04308                                 CLEAR_OUT_EP_INTR(core_if, epnum, nak);
++04309                         }
++04310                         /* NYET Interrutp */
++04311                         if (doepint.b.nyet) {
++04312                                 DWC_DEBUGPL(DBG_ANY, "EP%d OUT NYET\n", epnum);
++04313                                 handle_out_ep_nyet_intr(pcd, epnum);
++04314 
++04315                                 CLEAR_OUT_EP_INTR(core_if, epnum, nyet);
++04316                         }
++04317                 }
++04318 
++04319                 epnum++;
++04320                 ep_intr >>= 1;
++04321         }
++04322 
++04323         return 1;
++04324 
++04325 #undef CLEAR_OUT_EP_INTR
++04326 }
++04327 static int drop_transfer(uint32_t trgt_fr, uint32_t curr_fr, uint8_t frm_overrun)
++04328 {
++04329         int retval = 0;
++04330         if(!frm_overrun && curr_fr >= trgt_fr) 
++04331                 retval = 1;
++04332         else if (frm_overrun && (curr_fr >= trgt_fr && ((curr_fr - trgt_fr) < 0x3FFF/2)))
++04333                 retval = 1;
++04334         return retval;
++04335 }
++04348 int32_t dwc_otg_pcd_handle_incomplete_isoc_in_intr(dwc_otg_pcd_t * pcd)
++04349 {
++04350         gintsts_data_t gintsts;
++04351 
++04352 #ifdef DWC_EN_ISOC
++04353         dwc_otg_dev_if_t *dev_if;
++04354         deptsiz_data_t deptsiz = {.d32 = 0 };
++04355         depctl_data_t depctl = {.d32 = 0 };
++04356         dsts_data_t dsts = {.d32 = 0 };
++04357         dwc_ep_t *dwc_ep;
++04358         int i;
++04359 
++04360         dev_if = GET_CORE_IF(pcd)->dev_if;
++04361 
++04362         for (i = 1; i <= dev_if->num_in_eps; ++i) {
++04363                 dwc_ep = &pcd->in_ep[i].dwc_ep;
++04364                 if (dwc_ep->active && dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) {
++04365                         deptsiz.d32 =
++04366                             DWC_READ_REG32(&dev_if->in_ep_regs[i]->dieptsiz);
++04367                         depctl.d32 =
++04368                             DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl);
++04369 
++04370                         if (depctl.b.epdis && deptsiz.d32) {
++04371                                 set_current_pkt_info(GET_CORE_IF(pcd), dwc_ep);
++04372                                 if (dwc_ep->cur_pkt >= dwc_ep->pkt_cnt) {
++04373                                         dwc_ep->cur_pkt = 0;
++04374                                         dwc_ep->proc_buf_num =
++04375                                             (dwc_ep->proc_buf_num ^ 1) & 0x1;
++04376 
++04377                                         if (dwc_ep->proc_buf_num) {
++04378                                                 dwc_ep->cur_pkt_addr =
++04379                                                     dwc_ep->xfer_buff1;
++04380                                                 dwc_ep->cur_pkt_dma_addr =
++04381                                                     dwc_ep->dma_addr1;
++04382                                         } else {
++04383                                                 dwc_ep->cur_pkt_addr =
++04384                                                     dwc_ep->xfer_buff0;
++04385                                                 dwc_ep->cur_pkt_dma_addr =
++04386                                                     dwc_ep->dma_addr0;
++04387                                         }
++04388 
++04389                                 }
++04390 
++04391                                 dsts.d32 =
++04392                                     DWC_READ_REG32(&GET_CORE_IF(pcd)->dev_if->
++04393                                                    dev_global_regs->dsts);
++04394                                 dwc_ep->next_frame = dsts.b.soffn;
++04395 
++04396                                 dwc_otg_iso_ep_start_frm_transfer(GET_CORE_IF
++04397                                                                   (pcd),
++04398                                                                   dwc_ep);
++04399                         }
++04400                 }
++04401         }
++04402 
++04403 #else
++04404         depctl_data_t depctl = {.d32 = 0 };
++04405         dwc_ep_t *dwc_ep;
++04406         dwc_otg_dev_if_t *dev_if;
++04407         int i;
++04408         dev_if = GET_CORE_IF(pcd)->dev_if;
++04409 
++04410         DWC_DEBUGPL(DBG_PCD,"Incomplete ISO IN \n");
++04411         
++04412         for (i = 1; i <= dev_if->num_in_eps; ++i) {
++04413                 dwc_ep = &pcd->in_ep[i-1].dwc_ep;
++04414                 depctl.d32 =
++04415                         DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl);
++04416                 if (depctl.b.epena && dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) {
++04417                         if (drop_transfer(dwc_ep->frame_num, GET_CORE_IF(pcd)->frame_num, 
++04418                                                         dwc_ep->frm_overrun))
++04419                         {
++04420                                 depctl.d32 =
++04421                                         DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl);
++04422                                 depctl.b.snak = 1;
++04423                                 depctl.b.epdis = 1;
++04424                                 DWC_MODIFY_REG32(&dev_if->in_ep_regs[i]->diepctl, depctl.d32, depctl.d32);
++04425                         }
++04426                 }
++04427         }
++04428 
++04429         /*intr_mask.b.incomplisoin = 1;
++04430         DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk,
++04431                          intr_mask.d32, 0);      */
++04432 #endif                          //DWC_EN_ISOC
++04433 
++04434         /* Clear interrupt */
++04435         gintsts.d32 = 0;
++04436         gintsts.b.incomplisoin = 1;
++04437         DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
++04438                         gintsts.d32);
++04439 
++04440         return 1;
++04441 }
++04442 
++04458 int32_t dwc_otg_pcd_handle_incomplete_isoc_out_intr(dwc_otg_pcd_t * pcd)
++04459 {
++04460 
++04461         gintsts_data_t gintsts;
++04462 
++04463 #ifdef DWC_EN_ISOC
++04464         dwc_otg_dev_if_t *dev_if;
++04465         deptsiz_data_t deptsiz = {.d32 = 0 };
++04466         depctl_data_t depctl = {.d32 = 0 };
++04467         dsts_data_t dsts = {.d32 = 0 };
++04468         dwc_ep_t *dwc_ep;
++04469         int i;
++04470 
++04471         dev_if = GET_CORE_IF(pcd)->dev_if;
++04472 
++04473         for (i = 1; i <= dev_if->num_out_eps; ++i) {
++04474                 dwc_ep = &pcd->in_ep[i].dwc_ep;
++04475                 if (pcd->out_ep[i].dwc_ep.active &&
++04476                     pcd->out_ep[i].dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) {
++04477                         deptsiz.d32 =
++04478                             DWC_READ_REG32(&dev_if->out_ep_regs[i]->doeptsiz);
++04479                         depctl.d32 =
++04480                             DWC_READ_REG32(&dev_if->out_ep_regs[i]->doepctl);
++04481 
++04482                         if (depctl.b.epdis && deptsiz.d32) {
++04483                                 set_current_pkt_info(GET_CORE_IF(pcd),
++04484                                                      &pcd->out_ep[i].dwc_ep);
++04485                                 if (dwc_ep->cur_pkt >= dwc_ep->pkt_cnt) {
++04486                                         dwc_ep->cur_pkt = 0;
++04487                                         dwc_ep->proc_buf_num =
++04488                                             (dwc_ep->proc_buf_num ^ 1) & 0x1;
++04489 
++04490                                         if (dwc_ep->proc_buf_num) {
++04491                                                 dwc_ep->cur_pkt_addr =
++04492                                                     dwc_ep->xfer_buff1;
++04493                                                 dwc_ep->cur_pkt_dma_addr =
++04494                                                     dwc_ep->dma_addr1;
++04495                                         } else {
++04496                                                 dwc_ep->cur_pkt_addr =
++04497                                                     dwc_ep->xfer_buff0;
++04498                                                 dwc_ep->cur_pkt_dma_addr =
++04499                                                     dwc_ep->dma_addr0;
++04500                                         }
++04501 
++04502                                 }
++04503 
++04504                                 dsts.d32 =
++04505                                     DWC_READ_REG32(&GET_CORE_IF(pcd)->dev_if->
++04506                                                    dev_global_regs->dsts);
++04507                                 dwc_ep->next_frame = dsts.b.soffn;
++04508 
++04509                                 dwc_otg_iso_ep_start_frm_transfer(GET_CORE_IF
++04510                                                                   (pcd),
++04511                                                                   dwc_ep);
++04512                         }
++04513                 }
++04514         }
++04515 #else
++04516 
++04517         gintmsk_data_t intr_mask = {.d32 = 0 };
++04518         dwc_otg_core_if_t *core_if;
++04519         deptsiz_data_t deptsiz = {.d32 = 0 };
++04520         depctl_data_t depctl = {.d32 = 0 };
++04521         dctl_data_t dctl = {.d32 = 0 };
++04522         dwc_ep_t *dwc_ep = NULL;
++04523         int i;
++04524         core_if = GET_CORE_IF(pcd);
++04525 
++04526         for (i = 0; i < core_if->dev_if->num_out_eps; ++i) {
++04527                 dwc_ep = &pcd->out_ep[i].dwc_ep;
++04528                 depctl.d32 =
++04529                         DWC_READ_REG32(&core_if->dev_if->out_ep_regs[dwc_ep->num]->doepctl);
++04530                 if (depctl.b.epena && depctl.b.dpid == (core_if->frame_num & 0x1)) {
++04531                         core_if->dev_if->isoc_ep = dwc_ep;      
++04532                         deptsiz.d32 =
++04533                                         DWC_READ_REG32(&core_if->dev_if->out_ep_regs[dwc_ep->num]->doeptsiz);
++04534                                 break;
++04535                 }
++04536         }
++04537         dctl.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dctl);
++04538         gintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts);
++04539         intr_mask.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintmsk);
++04540 
++04541         if (!intr_mask.b.goutnakeff) {
++04542                 /* Unmask it */
++04543                 intr_mask.b.goutnakeff = 1;
++04544                 DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, intr_mask.d32);
++04545         }
++04546         if (!gintsts.b.goutnakeff) {
++04547                 dctl.b.sgoutnak = 1;
++04548         }
++04549         DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32);
++04550 
++04551         depctl.d32 = DWC_READ_REG32(&core_if->dev_if->out_ep_regs[dwc_ep->num]->doepctl);
++04552         if (depctl.b.epena) {
++04553                 depctl.b.epdis = 1;
++04554                 depctl.b.snak = 1;
++04555         }
++04556         DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[dwc_ep->num]->doepctl, depctl.d32);
++04557 
++04558         intr_mask.d32 = 0;
++04559         intr_mask.b.incomplisoout = 1;
++04560                 
++04561 #endif /* DWC_EN_ISOC */
++04562 
++04563         /* Clear interrupt */
++04564         gintsts.d32 = 0;
++04565         gintsts.b.incomplisoout = 1;
++04566         DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
++04567                         gintsts.d32);
++04568 
++04569         return 1;
++04570 }
++04571 
++04576 int32_t dwc_otg_pcd_handle_in_nak_effective(dwc_otg_pcd_t * pcd)
++04577 {
++04578         dwc_otg_dev_if_t *dev_if = GET_CORE_IF(pcd)->dev_if;
++04579         depctl_data_t diepctl = {.d32 = 0 };
++04580         gintmsk_data_t intr_mask = {.d32 = 0 };
++04581         gintsts_data_t gintsts;
++04582         dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
++04583         int i;
++04584 
++04585         DWC_DEBUGPL(DBG_PCD, "Global IN NAK Effective\n");
++04586 
++04587         /* Disable all active IN EPs */
++04588         for (i = 0; i <= dev_if->num_in_eps; i++) {
++04589                 diepctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl);
++04590                 if (!(diepctl.b.eptype & 1) && diepctl.b.epena) {
++04591                         if (core_if->start_predict > 0)
++04592                                 core_if->start_predict++;
++04593                         diepctl.b.epdis = 1;
++04594                         diepctl.b.snak = 1;
++04595                         DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->diepctl, diepctl.d32);
++04596                 }                                               
++04597         }
++04598         
++04599 
++04600         /* Disable the Global IN NAK Effective Interrupt */
++04601         intr_mask.b.ginnakeff = 1;
++04602         DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk,
++04603                          intr_mask.d32, 0);
++04604 
++04605         /* Clear interrupt */
++04606         gintsts.d32 = 0;
++04607         gintsts.b.ginnakeff = 1;
++04608         DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
++04609                         gintsts.d32);
++04610 
++04611         return 1;
++04612 }
++04613 
++04618 int32_t dwc_otg_pcd_handle_out_nak_effective(dwc_otg_pcd_t * pcd)
++04619 {
++04620         dwc_otg_dev_if_t *dev_if = GET_CORE_IF(pcd)->dev_if;
++04621         gintmsk_data_t intr_mask = {.d32 = 0 };
++04622         gintsts_data_t gintsts;
++04623         depctl_data_t doepctl;
++04624         int i;
++04625 
++04626         /* Disable the Global OUT NAK Effective Interrupt */
++04627         intr_mask.b.goutnakeff = 1;
++04628         DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk,
++04629                 intr_mask.d32, 0);
++04630         
++04631         /* If DEV OUT NAK enabled*/
++04632         if (pcd->core_if->core_params->dev_out_nak) {
++04633                 /* Run over all out endpoints to determine the ep number on
++04634                  * which the timeout has happened 
++04635                  */
++04636                 for (i = 0; i <= dev_if->num_out_eps; i++) {
++04637                         if ( pcd->core_if->ep_xfer_info[i].state == 2 )
++04638                                 break;
++04639                 }
++04640                 if (i > dev_if->num_out_eps) {
++04641                         dctl_data_t dctl;
++04642                         dctl.d32 = DWC_READ_REG32(&dev_if->
++04643                                 dev_global_regs->dctl);
++04644                         dctl.b.cgoutnak = 1;
++04645                         DWC_WRITE_REG32(&dev_if->dev_global_regs->dctl,
++04646                                 dctl.d32);
++04647                         goto out;
++04648                 }
++04649 
++04650                 /* Disable the endpoint */
++04651                 doepctl.d32 = DWC_READ_REG32(&dev_if->
++04652                                                                                 out_ep_regs[i]->doepctl);
++04653                 if (doepctl.b.epena) {
++04654                         doepctl.b.epdis = 1;
++04655                         doepctl.b.snak = 1;
++04656                 }
++04657                 DWC_WRITE_REG32(&dev_if->out_ep_regs[i]->doepctl, doepctl.d32);
++04658                 return 1;
++04659         }
++04660         /* We come here from Incomplete ISO OUT handler */
++04661         if(dev_if->isoc_ep)
++04662         {
++04663                 dwc_ep_t *dwc_ep = (dwc_ep_t *)dev_if->isoc_ep;
++04664                 uint32_t epnum = dwc_ep->num;
++04665                 doepint_data_t doepint;
++04666                 doepint.d32 = DWC_READ_REG32(&dev_if->out_ep_regs[dwc_ep->num]->doepint);
++04667                 dev_if->isoc_ep = NULL;
++04668                 doepctl.d32 = DWC_READ_REG32(&dev_if->out_ep_regs[epnum]->doepctl);
++04669                 DWC_PRINTF("Before disable DOEPCTL = %08x\n", doepctl.d32);
++04670                 if (doepctl.b.epena) {
++04671                         doepctl.b.epdis = 1;
++04672                         doepctl.b.snak = 1;
++04673                 }
++04674                 DWC_WRITE_REG32(&dev_if->out_ep_regs[epnum]->doepctl, doepctl.d32);
++04675                 return 1;
++04676         } else
++04677                 DWC_PRINTF("INTERRUPT Handler not implemented for %s\n",
++04678                            "Global OUT NAK Effective\n");
++04679         
++04680 out:
++04681         /* Clear interrupt */
++04682         gintsts.d32 = 0;
++04683         gintsts.b.goutnakeff = 1;
++04684         DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
++04685                         gintsts.d32);
++04686 
++04687         return 1;
++04688 }
++04689 
++04702 int32_t dwc_otg_pcd_handle_intr(dwc_otg_pcd_t * pcd)
++04703 {
++04704         dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
++04705 #ifdef VERBOSE
++04706         dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
++04707 #endif
++04708         gintsts_data_t gintr_status;
++04709         int32_t retval = 0;
++04710 
++04711         /* Exit from ISR if core is hibernated */
++04712         if (core_if->hibernation_suspend == 1) {
++04713                 return retval;
++04714         }
++04715 #ifdef VERBOSE
++04716         DWC_DEBUGPL(DBG_ANY, "%s() gintsts=%08x  gintmsk=%08x\n",
++04717                     __func__,
++04718                     DWC_READ_REG32(&global_regs->gintsts),
++04719                     DWC_READ_REG32(&global_regs->gintmsk));
++04720 #endif
++04721 
++04722         if (dwc_otg_is_device_mode(core_if)) {
++04723                 DWC_SPINLOCK(pcd->lock);
++04724 #ifdef VERBOSE
++04725                 DWC_DEBUGPL(DBG_PCDV, "%s() gintsts=%08x  gintmsk=%08x\n",
++04726                             __func__,
++04727                             DWC_READ_REG32(&global_regs->gintsts),
++04728                             DWC_READ_REG32(&global_regs->gintmsk));
++04729 #endif
++04730 
++04731                 gintr_status.d32 = dwc_otg_read_core_intr(core_if);
++04732 
++04733                 DWC_DEBUGPL(DBG_PCDV, "%s: gintsts&gintmsk=%08x\n",
++04734                             __func__, gintr_status.d32);
++04735 
++04736                 if (gintr_status.b.sofintr) {
++04737                         retval |= dwc_otg_pcd_handle_sof_intr(pcd);
++04738                 }
++04739                 if (gintr_status.b.rxstsqlvl) {
++04740                         retval |=
++04741                             dwc_otg_pcd_handle_rx_status_q_level_intr(pcd);
++04742                 }
++04743                 if (gintr_status.b.nptxfempty) {
++04744                         retval |= dwc_otg_pcd_handle_np_tx_fifo_empty_intr(pcd);
++04745                 }
++04746                 if (gintr_status.b.goutnakeff) {
++04747                         retval |= dwc_otg_pcd_handle_out_nak_effective(pcd);
++04748                 }
++04749                 if (gintr_status.b.i2cintr) {
++04750                         retval |= dwc_otg_pcd_handle_i2c_intr(pcd);
++04751                 }
++04752                 if (gintr_status.b.erlysuspend) {
++04753                         retval |= dwc_otg_pcd_handle_early_suspend_intr(pcd);
++04754                 }
++04755                 if (gintr_status.b.usbreset) {
++04756                         retval |= dwc_otg_pcd_handle_usb_reset_intr(pcd);
++04757                 }
++04758                 if (gintr_status.b.enumdone) {
++04759                         retval |= dwc_otg_pcd_handle_enum_done_intr(pcd);
++04760                 }
++04761                 if (gintr_status.b.isooutdrop) {
++04762                         retval |=
++04763                             dwc_otg_pcd_handle_isoc_out_packet_dropped_intr
++04764                             (pcd);
++04765                 }
++04766                 if (gintr_status.b.eopframe) {
++04767                         retval |=
++04768                             dwc_otg_pcd_handle_end_periodic_frame_intr(pcd);
++04769                 }
++04770                 if (gintr_status.b.inepint) {
++04771                         if (!core_if->multiproc_int_enable) {
++04772                                 retval |= dwc_otg_pcd_handle_in_ep_intr(pcd);
++04773                         }
++04774                 }
++04775                 if (gintr_status.b.outepintr) {
++04776                         if (!core_if->multiproc_int_enable) {
++04777                                 retval |= dwc_otg_pcd_handle_out_ep_intr(pcd);
++04778                         }
++04779                 }
++04780                 if (gintr_status.b.epmismatch) {
++04781                         retval |= dwc_otg_pcd_handle_ep_mismatch_intr(pcd);
++04782                 }
++04783                 if (gintr_status.b.fetsusp) {
++04784                         retval |= dwc_otg_pcd_handle_ep_fetsusp_intr(pcd);
++04785                 }
++04786                 if (gintr_status.b.ginnakeff) {
++04787                         retval |= dwc_otg_pcd_handle_in_nak_effective(pcd);
++04788                 }
++04789                 if (gintr_status.b.incomplisoin) {
++04790                         retval |=
++04791                             dwc_otg_pcd_handle_incomplete_isoc_in_intr(pcd);
++04792                 }
++04793                 if (gintr_status.b.incomplisoout) {
++04794                         retval |=
++04795                             dwc_otg_pcd_handle_incomplete_isoc_out_intr(pcd);
++04796                 }
++04797 
++04798                 /* In MPI mode Device Endpoints interrupts are asserted
++04799                  * without setting outepintr and inepint bits set, so these
++04800                  * Interrupt handlers are called without checking these bit-fields
++04801                  */
++04802                 if (core_if->multiproc_int_enable) {
++04803                         retval |= dwc_otg_pcd_handle_in_ep_intr(pcd);
++04804                         retval |= dwc_otg_pcd_handle_out_ep_intr(pcd);
++04805                 }
++04806 #ifdef VERBOSE
++04807                 DWC_DEBUGPL(DBG_PCDV, "%s() gintsts=%0x\n", __func__,
++04808                             DWC_READ_REG32(&global_regs->gintsts));
++04809 #endif
++04810                 DWC_SPINUNLOCK(pcd->lock);
++04811         }
++04812         return retval;
++04813 }
++04814 
++04815 #endif /* DWC_HOST_ONLY */
++
    Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
    ++doxygen 1.3.9.1
    + + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__pcd__intr_8c.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/dwc__otg__pcd__intr_8c.html 2013-07-26 19:31:21.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__pcd__intr_8c.html 2013-07-26 19:34:42.000000000 +0000 +@@ -2,362 +2,408 @@ + + DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_pcd_intr.c File Reference + +- + +- +-
    +-
    +-
    +-
    ++ ++
    Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
    +

    dwc_otg_pcd_intr.c File Reference

    This file contains the implementation of the PCD Interrupt handlers. More... +

    +-#include "dwc_otg_pcd.h"
    ++#include "dwc_otg_pcd.h"
    + +

    + Go to the source code of this file. + + +- ++ + + + + + + +- ++ + + +- ++ + + +- ++ ++ ++ ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ ++ ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + + +- ++ + +- +- ++ ++ + + +- ++ + + +- ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + + +- ++ + +- +- ++ ++ + + +- ++ + +- +- ++ ++ + + +- ++ ++ ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + + +- ++ ++ ++ + + +- ++ ++ ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ + +- +- ++ ++ + +- +- ++ ++ + + +- ++ + + +- ++ + +- ++ +

    Defines

    +-#define DEBUG_EP0
    ++#define DEBUG_EP0
    #define CLEAR_IN_EP_INTR(__core_if, __epnum, __intr)
    #define CLEAR_OUT_EP_INTR(__core_if, __epnum, __intr)

    Functions

    +-static void dwc_otg_pcd_update_otg (dwc_otg_pcd_t *pcd, const unsigned reset)
    ++void dwc_otg_pcd_update_otg (dwc_otg_pcd_t *pcd, const unsigned reset)
     This function updates OTG.
    +-static void print_ep0_state (dwc_otg_pcd_t *pcd)
    ++void print_ep0_state (dwc_otg_pcd_t *pcd)
     This function prints the ep0 state for debug purposes.
    +-static dwc_otg_pcd_ep_t * get_in_ep (dwc_otg_pcd_t *pcd, uint32_t ep_num)
    ++void print_memory_payload (dwc_otg_pcd_t *pcd, dwc_ep_t *ep)
     This function calculate the size of the payload in the memory for out endpoints and prints size for debug purposes(used in 2.93a DevOutNak feature).
    ++dwc_otg_pcd_ep_t * get_in_ep (dwc_otg_pcd_t *pcd, uint32_t ep_num)
     This function returns pointer to in ep struct with number ep_num.
    +-static dwc_otg_pcd_ep_t * get_out_ep (dwc_otg_pcd_t *pcd, uint32_t ep_num)
    ++dwc_otg_pcd_ep_t * get_out_ep (dwc_otg_pcd_t *pcd, uint32_t ep_num)
     This function returns pointer to out ep struct with number ep_num.
    +-dwc_otg_pcd_ep_t * get_ep_by_addr (dwc_otg_pcd_t *pcd, u16 wIndex)
    ++dwc_otg_pcd_ep_t * get_ep_by_addr (dwc_otg_pcd_t *pcd, u16 wIndex)
     This functions gets a pointer to an EP from the wIndex address value of the control request.
    +-void start_next_request (dwc_otg_pcd_ep_t *ep)
    ++void start_next_request (dwc_otg_pcd_ep_t *ep)
     Tasklet.
    int32_t dwc_otg_pcd_handle_sof_intr (dwc_otg_pcd_t *pcd)
    int32_t dwc_otg_pcd_handle_sof_intr (dwc_otg_pcd_t *pcd)
     This function handles the SOF Interrupts.
    int32_t dwc_otg_pcd_handle_rx_status_q_level_intr (dwc_otg_pcd_t *pcd)
     This function handles the SOF Interrupts.
    int32_t dwc_otg_pcd_handle_rx_status_q_level_intr (dwc_otg_pcd_t *pcd)
     This function handles the Rx Status Queue Level Interrupt, which indicates that there is a least one packet in the Rx FIFO.
    int get_ep_of_last_in_token (dwc_otg_core_if_t *core_if)
     This function handles the Rx Status Queue Level Interrupt, which indicates that there is a least one packet in the Rx FIFO.
    static int get_ep_of_last_in_token (dwc_otg_core_if_t *core_if)
     This function examines the Device IN Token Learning Queue to determine the EP number of the last IN token received.
    int32_t dwc_otg_pcd_handle_np_tx_fifo_empty_intr (dwc_otg_pcd_t *pcd)
     This function examines the Device IN Token Learning Queue to determine the EP number of the last IN token received.
    int32_t dwc_otg_pcd_handle_np_tx_fifo_empty_intr (dwc_otg_pcd_t *pcd)
     This interrupt occurs when the non-periodic Tx FIFO is half-empty.
    int32_t write_empty_tx_fifo (dwc_otg_pcd_t *pcd, uint32_t epnum)
     This interrupt occurs when the non-periodic Tx FIFO is half-empty.
    static int32_t write_empty_tx_fifo (dwc_otg_pcd_t *pcd, uint32_t epnum)
     This function is called when dedicated Tx FIFO Empty interrupt occurs.
    void dwc_otg_pcd_stop (dwc_otg_pcd_t *pcd)
     This function is called when dedicated Tx FIFO Empty interrupt occurs.
    void dwc_otg_pcd_stop (dwc_otg_pcd_t *pcd)
     This function is called when the Device is disconnected.
    ++int32_t dwc_otg_pcd_handle_i2c_intr (dwc_otg_pcd_t *pcd)
     This function is called when the Device is disconnected.
    int32_t dwc_otg_pcd_handle_i2c_intr (dwc_otg_pcd_t *pcd)
     This interrupt indicates that ...
    ++int32_t dwc_otg_pcd_handle_early_suspend_intr (dwc_otg_pcd_t *pcd)
     This interrupt indicates that .
    int32_t dwc_otg_pcd_handle_early_suspend_intr (dwc_otg_pcd_t *pcd)
     This interrupt indicates that ...
    void ep0_out_start (dwc_otg_core_if_t *core_if, dwc_otg_pcd_t *pcd)
     This interrupt indicates that .
    static void ep0_out_start (dwc_otg_core_if_t *core_if, dwc_otg_pcd_t *pcd)
     This function configures EPO to receive SETUP packets.
    int32_t dwc_otg_pcd_handle_usb_reset_intr (dwc_otg_pcd_t *pcd)
     This function configures EPO to receive SETUP packets.
    int32_t dwc_otg_pcd_handle_usb_reset_intr (dwc_otg_pcd_t *pcd)
     This interrupt occurs when a USB Reset is detected.
    int get_device_speed (dwc_otg_core_if_t *core_if)
     This interrupt occurs when a USB Reset is detected.
    static int get_device_speed (dwc_otg_core_if_t *core_if)
     Get the device speed from the device status register and convert it to USB speed constant.
    int32_t dwc_otg_pcd_handle_enum_done_intr (dwc_otg_pcd_t *pcd)
     Get the device speed from the device status register and convert it to USB speed constant.
    int32_t dwc_otg_pcd_handle_enum_done_intr (dwc_otg_pcd_t *pcd)
     Read the device status register and set the device speed in the data structure.
    int32_t dwc_otg_pcd_handle_isoc_out_packet_dropped_intr (dwc_otg_pcd_t *pcd)
     Read the device status register and set the device speed in the data structure.
    int32_t dwc_otg_pcd_handle_isoc_out_packet_dropped_intr (dwc_otg_pcd_t *pcd)
     This interrupt indicates that the ISO OUT Packet was dropped due to Rx FIFO full or Rx Status Queue Full.
    int32_t dwc_otg_pcd_handle_end_periodic_frame_intr (dwc_otg_pcd_t *pcd)
     This interrupt indicates that the ISO OUT Packet was dropped due to Rx FIFO full or Rx Status Queue Full.
    int32_t dwc_otg_pcd_handle_end_periodic_frame_intr (dwc_otg_pcd_t *pcd)
     This interrupt indicates the end of the portion of the micro-frame for periodic transactions.
    int32_t dwc_otg_pcd_handle_ep_mismatch_intr (dwc_otg_pcd_t *pcd)
     This interrupt indicates the end of the portion of the micro-frame for periodic transactions.
    int32_t dwc_otg_pcd_handle_ep_mismatch_intr (dwc_otg_core_if_t *core_if)
     This interrupt indicates that EP of the packet on the top of the non-periodic Tx FIFO does not match EP of the IN Token received.
    int32_t dwc_otg_pcd_handle_ep_fetsusp_intr (dwc_otg_pcd_t *pcd)
     This interrupt indicates that EP of the packet on the top of the non-periodic Tx FIFO does not match EP of the IN Token received.
    +-static void ep0_do_stall (dwc_otg_pcd_t *pcd, const int err_val)
     This interrupt is valid only in DMA mode.
    ++void ep0_do_stall (dwc_otg_pcd_t *pcd, const int err_val)
     This funcion stalls EP0.
    static void do_gadget_setup (dwc_otg_pcd_t *pcd, usb_device_request_t *ctrl)
    void do_gadget_setup (dwc_otg_pcd_t *pcd, usb_device_request_t *ctrl)
     This functions delegates the setup command to the gadget driver.
    +-static void do_setup_in_status_phase (dwc_otg_pcd_t *pcd)
     This functions delegates the setup command to the gadget driver.
    ++void do_setup_in_status_phase (dwc_otg_pcd_t *pcd)
     This function starts the Zero-Length Packet for the IN status phase of a 2 stage control transfer.
    +-static void do_setup_out_status_phase (dwc_otg_pcd_t *pcd)
    ++void do_setup_out_status_phase (dwc_otg_pcd_t *pcd)
     This function starts the Zero-Length Packet for the OUT status phase of a 2 stage control transfer.
    static void pcd_clear_halt (dwc_otg_pcd_t *pcd, dwc_otg_pcd_ep_t *ep)
    void pcd_clear_halt (dwc_otg_pcd_t *pcd, dwc_otg_pcd_ep_t *ep)
     Clear the EP halt (STALL) and if pending requests start the transfer.
    void do_test_mode (void *data)
     Clear the EP halt (STALL) and if pending requests start the transfer.
    void do_test_mode (void *data)
     This function is called when the SET_FEATURE TEST_MODE Setup packet is sent from the host.
    static void do_get_status (dwc_otg_pcd_t *pcd)
     This function is called when the SET_FEATURE TEST_MODE Setup packet is sent from the host.
    void do_get_status (dwc_otg_pcd_t *pcd)
     This function process the GET_STATUS Setup Commands.
    static void do_set_feature (dwc_otg_pcd_t *pcd)
     This function process the GET_STATUS Setup Commands.
    void do_set_feature (dwc_otg_pcd_t *pcd)
     This function process the SET_FEATURE Setup Commands.
    static void do_clear_feature (dwc_otg_pcd_t *pcd)
     This function process the SET_FEATURE Setup Commands.
    void do_clear_feature (dwc_otg_pcd_t *pcd)
     This function process the CLEAR_FEATURE Setup Commands.
    +-static void do_set_address (dwc_otg_pcd_t *pcd)
     This function process the CLEAR_FEATURE Setup Commands.
    ++void do_set_address (dwc_otg_pcd_t *pcd)
     This function process the SET_ADDRESS Setup Commands.
    static void pcd_setup (dwc_otg_pcd_t *pcd)
    void pcd_setup (dwc_otg_pcd_t *pcd)
     This function processes SETUP commands.
    +-static int32_t ep0_complete_request (dwc_otg_pcd_ep_t *ep)
     This function processes SETUP commands.
    ++int32_t ep0_complete_request (dwc_otg_pcd_ep_t *ep)
     This function completes the ep0 control transfer.
    static void complete_ep (dwc_otg_pcd_ep_t *ep)
    void complete_ep (dwc_otg_pcd_ep_t *ep)
     This function completes the request for the EP.
    +-static void dwc_otg_pcd_handle_iso_bna (dwc_otg_pcd_ep_t *ep)
     This function completes the request for the EP.
    ++void dwc_otg_pcd_handle_iso_bna (dwc_otg_pcd_ep_t *ep)
     This function BNA interrupt for Isochronous EPs.
    void set_current_pkt_info (dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
    void set_current_pkt_info (dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
     This function sets latest iso packet information(non-PTI mode).
    void set_ddma_iso_pkts_info (dwc_otg_core_if_t *core_if, dwc_ep_t *dwc_ep)
     This function sets latest iso packet information(non-PTI mode).
    static void set_ddma_iso_pkts_info (dwc_otg_core_if_t *core_if, dwc_ep_t *dwc_ep)
     This function sets latest iso packet information(DDMA mode).
    void reinit_ddma_iso_xfer (dwc_otg_core_if_t *core_if, dwc_ep_t *dwc_ep)
     This function sets latest iso packet information(DDMA mode).
    static void reinit_ddma_iso_xfer (dwc_otg_core_if_t *core_if, dwc_ep_t *dwc_ep)
     This function reinitialize DMA Descriptors for Isochronous transfer.
    uint32_t handle_iso_out_pkt_dropped (dwc_otg_core_if_t *core_if, dwc_ep_t *dwc_ep)
     This function reinitialize DMA Descriptors for Isochronous transfer.
    static uint32_t handle_iso_out_pkt_dropped (dwc_otg_core_if_t *core_if, dwc_ep_t *dwc_ep)
     This function is to handle Iso EP transfer complete interrupt in case Iso out packet was dropped.
    uint32_t set_iso_pkts_info (dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
     This function is to handle Iso EP transfer complete interrupt in case Iso out packet was dropped.
    static uint32_t set_iso_pkts_info (dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
     This function sets iso packets information(PTI mode).
    void complete_iso_ep (dwc_otg_pcd_t *pcd, dwc_otg_pcd_ep_t *ep)
     This function sets iso packets information(PTI mode).
    static void complete_iso_ep (dwc_otg_pcd_t *pcd, dwc_otg_pcd_ep_t *ep)
     This function is to handle Iso EP transfer complete interrupt.
    ++void dwc_otg_pcd_handle_noniso_bna (dwc_otg_pcd_ep_t *ep)
     This function is to handle Iso EP transfer complete interrupt.
    static void handle_ep0 (dwc_otg_pcd_t *pcd)
     This function handle BNA interrupt for Non Isochronous EPs.
    void handle_ep0 (dwc_otg_pcd_t *pcd)
     This function handles EP0 Control transfers.
    +-static void restart_transfer (dwc_otg_pcd_t *pcd, const uint32_t epnum)
     This function handles EP0 Control transfers.
    ++void restart_transfer (dwc_otg_pcd_t *pcd, const uint32_t epnum)
     Restart transfer.
    +-static void handle_in_ep_disable_intr (dwc_otg_pcd_t *pcd, const uint32_t epnum)
    ++void predict_nextep_seq (dwc_otg_core_if_t *core_if)
    ++void handle_in_ep_disable_intr (dwc_otg_pcd_t *pcd, const uint32_t epnum)
     handle the IN EP disable interrupt.
    static void handle_in_ep_timeout_intr (dwc_otg_pcd_t *pcd, const uint32_t epnum)
    void handle_in_ep_timeout_intr (dwc_otg_pcd_t *pcd, const uint32_t epnum)
     Handler for the IN EP timeout handshake interrupt.
    int32_t handle_in_ep_nak_intr (dwc_otg_pcd_t *pcd, const uint32_t epnum)
     Handler for the IN EP timeout handshake interrupt.
    static int32_t handle_in_ep_nak_intr (dwc_otg_pcd_t *pcd, const uint32_t epnum)
     Handler for the IN EP NAK interrupt.
    int32_t handle_out_ep_babble_intr (dwc_otg_pcd_t *pcd, const uint32_t epnum)
     Handler for the IN EP NAK interrupt.
    static int32_t handle_out_ep_babble_intr (dwc_otg_pcd_t *pcd, const uint32_t epnum)
     Handler for the OUT EP Babble interrupt.
    int32_t handle_out_ep_nak_intr (dwc_otg_pcd_t *pcd, const uint32_t epnum)
     Handler for the OUT EP Babble interrupt.
    static int32_t handle_out_ep_nak_intr (dwc_otg_pcd_t *pcd, const uint32_t epnum)
     Handler for the OUT EP NAK interrupt.
    int32_t handle_out_ep_nyet_intr (dwc_otg_pcd_t *pcd, const uint32_t epnum)
     Handler for the OUT EP NAK interrupt.
    static int32_t handle_out_ep_nyet_intr (dwc_otg_pcd_t *pcd, const uint32_t epnum)
     Handler for the OUT EP NYET interrupt.
    int32_t dwc_otg_pcd_handle_in_ep_intr (dwc_otg_pcd_t *pcd)
     Handler for the OUT EP NYET interrupt.
    static int32_t dwc_otg_pcd_handle_in_ep_intr (dwc_otg_pcd_t *pcd)
     This interrupt indicates that an IN EP has a pending Interrupt.
    int32_t dwc_otg_pcd_handle_out_ep_intr (dwc_otg_pcd_t *pcd)
     This interrupt indicates that an IN EP has a pending Interrupt.
    static int32_t dwc_otg_pcd_handle_out_ep_intr (dwc_otg_pcd_t *pcd)
     This interrupt indicates that an OUT EP has a pending Interrupt.
    ++int drop_transfer (uint32_t trgt_fr, uint32_t curr_fr, uint8_t frm_overrun)
     This interrupt indicates that an OUT EP has a pending Interrupt.
    int32_t dwc_otg_pcd_handle_incomplete_isoc_in_intr (dwc_otg_pcd_t *pcd)
    int32_t dwc_otg_pcd_handle_incomplete_isoc_in_intr (dwc_otg_pcd_t *pcd)
     Incomplete ISO IN Transfer Interrupt.
    int32_t dwc_otg_pcd_handle_incomplete_isoc_out_intr (dwc_otg_pcd_t *pcd)
     Incomplete ISO IN Transfer Interrupt.
    int32_t dwc_otg_pcd_handle_incomplete_isoc_out_intr (dwc_otg_pcd_t *pcd)
     Incomplete ISO OUT Transfer Interrupt.
    +-int32_t dwc_otg_pcd_handle_in_nak_effective (dwc_otg_pcd_t *pcd)
     Incomplete ISO OUT Transfer Interrupt.
    ++int32_t dwc_otg_pcd_handle_in_nak_effective (dwc_otg_pcd_t *pcd)
     This function handles the Global IN NAK Effective interrupt.
    +-int32_t dwc_otg_pcd_handle_out_nak_effective (dwc_otg_pcd_t *pcd)
    ++int32_t dwc_otg_pcd_handle_out_nak_effective (dwc_otg_pcd_t *pcd)
     OUT NAK Effective.
    int32_t dwc_otg_pcd_handle_intr (dwc_otg_pcd_t *pcd)
    int32_t dwc_otg_pcd_handle_intr (dwc_otg_pcd_t *pcd)
     This function should be called on every hardware interrupt.
     This function should be called on every hardware interrupt.
    +

    Detailed Description

    + This file contains the implementation of the PCD Interrupt handlers. +

    +-The PCD handles the device interrupts. Many conditions can cause a device interrupt. When an interrupt occurs, the device interrupt service routine determines the cause of the interrupt and dispatches handling to the appropriate function. These interrupt handling functions are described below. All interrupt registers are processed from LSB to MSB. ++The PCD handles the device interrupts. Many conditions can cause a device interrupt. When an interrupt occurs, the device interrupt service routine determines the cause of the interrupt and dispatches handling to the appropriate function. These interrupt handling functions are described below. All interrupt registers are processed from LSB to MSB. +

    + Definition in file dwc_otg_pcd_intr.c.

    Define Documentation

    +- +-
    +-
    +- +- +- +- +- +- +- +- +- +- +- +- +- +- ++

    ++

    #define CLEAR_IN_EP_INTR (__core_if,
    __epnum,
    __intr   ) 
    ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ + +
    #define CLEAR_IN_EP_INTR ( __core_if,
    __epnum,
    __intr   ) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + Value:

    do { \
+                 diepint_data_t diepint = {.d32=0}; \
+-                diepint.b.__intr = 1; \
+-                dwc_write_reg32(&__core_if->dev_if->in_ep_regs[__epnum]->diepint, \
+-                diepint.d32); \
++                diepint.b.__intr = 1; \
++                DWC_WRITE_REG32(&__core_if->dev_if->in_ep_regs[__epnum]->diepint, \
++                diepint.d32); \
+ } while (0)
+-
    +- +-

    +- +-

    +-
    +- +- +- +- +- +- +- +- +- +- +- +- +- +- ++ ++ ++
    #define CLEAR_OUT_EP_INTR (__core_if,
    __epnum,
    __intr   ) 
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ + +
    #define CLEAR_OUT_EP_INTR ( __core_if,
    __epnum,
    __intr   ) 
    +- +-
    ++
    ++ ++ ++ ++ ++ ++
    ++   ++ + +

    + Value:

    do { \
+                 doepint_data_t doepint = {.d32=0}; \
+-                doepint.b.__intr = 1; \
+-                dwc_write_reg32(&__core_if->dev_if->out_ep_regs[__epnum]->doepint, \
+-                doepint.d32); \
++                doepint.b.__intr = 1; \
++                DWC_WRITE_REG32(&__core_if->dev_if->out_ep_regs[__epnum]->doepint, \
++                doepint.d32); \
+ } while (0)
+-
    +- +-

    ++

    +

    Function Documentation

    +- +-
    +-
    +- +- +- +- +- +- +- +- ++

    ++

    int32_t dwc_otg_pcd_handle_sof_intr (dwc_otg_pcd_t *  pcd  ) 
    ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ + +
    int32_t dwc_otg_pcd_handle_sof_intr ( dwc_otg_pcd_t *  pcd  ) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + This function handles the SOF Interrupts. +

    + At this time the SOF Interrupt is disabled. +

    +-Definition at line 252 of file dwc_otg_pcd_intr.c. +- +-

    +- +-

    +-
    +- +- +- +- +- +- +- +- ++Definition at line 298 of file dwc_otg_pcd_intr.c. ++ ++
    int32_t dwc_otg_pcd_handle_rx_status_q_level_intr (dwc_otg_pcd_t *  pcd  ) 
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ + +
    int32_t dwc_otg_pcd_handle_rx_status_q_level_intr ( dwc_otg_pcd_t *  pcd  ) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + This function handles the Rx Status Queue Level Interrupt, which indicates that there is a least one packet in the Rx FIFO. +

    + The packets are moved from the FIFO to memory, where they will be processed when the Endpoint Interrupt Register indicates Transfer Complete or SETUP Phase Done.

    + Repeat the following until the Rx Status Queue is empty:

      +-
    1. Read the Receive Status Pop Register (GRXSTSP) to get Packet info
    2. If Receive FIFO is empty then skip to step Clear the interrupt and exit
    3. If SETUP Packet call dwc_otg_read_setup_packet to copy the SETUP data to the buffer
    4. If OUT Data Packet call dwc_otg_read_packet to copy the data to the destination buffer
    +- ++
  • Read the Receive Status Pop Register (GRXSTSP) to get Packet info
  • If Receive FIFO is empty then skip to step Clear the interrupt and exit
  • If SETUP Packet call dwc_otg_read_setup_packet to copy the SETUP data to the buffer
  • If OUT Data Packet call dwc_otg_read_packet to copy the data to the destination buffer
    • +

    +-

    Todo:
    NGS Check for buffer overflow?
    ++
    Todo:
    NGS Check for buffer overflow?
    + +

    +-Definition at line 285 of file dwc_otg_pcd_intr.c. +- +-

    +- +-

    +-
    +- +- +- +- +- +- +- +- ++Definition at line 331 of file dwc_otg_pcd_intr.c. ++ ++
    static int get_ep_of_last_in_token (dwc_otg_core_if_t *  core_if  )  [inline, static]
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ + +
    int get_ep_of_last_in_token ( dwc_otg_core_if_t *  core_if  )  [inline, static]
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + This function examines the Device IN Token Learning Queue to determine the EP number of the last IN token received. +@@ -366,178 +412,160 @@ + The EP numbers for the first six IN Tokens are in DTKNQR1 and there are 8 EP Numbers in each of the other possible DTKNQ Registers.

    +

    Parameters:
    + +- ++ +
    core_if Programming view of DWC_otg controller.
    core_if Programming view of DWC_otg controller.
    +
    +- +

    +-

    Todo:
    Find a simpler way to calculate the max queue position.
    ++
    Todo:
    Find a simpler way to calculate the max queue position.
    + +

    +-Definition at line 378 of file dwc_otg_pcd_intr.c. +- +-

    +- +-

    +-
    +- +- +- +- +- +- +- +- ++Definition at line 424 of file dwc_otg_pcd_intr.c. ++ ++
    int32_t dwc_otg_pcd_handle_np_tx_fifo_empty_intr (dwc_otg_pcd_t *  pcd  ) 
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ + +
    int32_t dwc_otg_pcd_handle_np_tx_fifo_empty_intr ( dwc_otg_pcd_t *  pcd  ) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + This interrupt occurs when the non-periodic Tx FIFO is half-empty. +

    + The active request is checked for the next packet to be loaded into the non-periodic Tx FIFO. +

    +-Definition at line 451 of file dwc_otg_pcd_intr.c. +- +-

    +- +-

    +-
    +- ++Definition at line 497 of file dwc_otg_pcd_intr.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    static int32_t write_empty_tx_fifo (dwc_otg_pcd_t *  pcd, int32_t write_empty_tx_fifo ( dwc_otg_pcd_t *  pcd,
    uint32_t  epnum uint32_t  epnum
    ) [static])  [static]
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + This function is called when dedicated Tx FIFO Empty interrupt occurs. +

    + The active request is checked for the next packet to be loaded into apropriate Tx FIFO. +

    +-Definition at line 515 of file dwc_otg_pcd_intr.c. +- +-

    +- +-

    +-
    +- +- +- +- +- +- +- +- ++Definition at line 561 of file dwc_otg_pcd_intr.c. ++ ++
    void dwc_otg_pcd_stop (dwc_otg_pcd_t *  pcd  ) 
    ++

    ++ ++ ++ ++ ++
    ++ ++ ++ ++ ++ ++ ++ ++ + +
    void dwc_otg_pcd_stop ( dwc_otg_pcd_t *  pcd  ) 
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + This function is called when the Device is disconnected. +

    +-It stops any active requests and informs the Gadget driver of the disconnect. +-

    +-

    Todo:
    NGS Flush Periodic FIFOs
    ++It stops any active requests and informs the Gadget driver of the disconnect.

    ++

    Todo:
    NGS Flush Periodic FIFOs
    + +

    +-Definition at line 573 of file dwc_otg_pcd_intr.c. +- +-

    +- +-

    +-
    +- +- +- +- +- +- +- +- +- +-
    int32_t dwc_otg_pcd_handle_i2c_intr (dwc_otg_pcd_t *  pcd  ) 
    +-
    +-
    +- +-

    +-This interrupt indicates that . +-

    +-.. +-

    +-Definition at line 632 of file dwc_otg_pcd_intr.c. +-

    +-

    +- +-

    +-
    +- +- +- +- +- +- +- +- +- +-
    int32_t dwc_otg_pcd_handle_early_suspend_intr (dwc_otg_pcd_t *  pcd  ) 
    +-
    +-
    +- +-

    +-This interrupt indicates that . +-

    +-.. +-

    +-Definition at line 653 of file dwc_otg_pcd_intr.c. +-

    +-

    +- +-

    +-
    +- ++Definition at line 619 of file dwc_otg_pcd_intr.c. ++ ++
    ++

    ++ ++ ++ ++ ++
    ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
    static void ep0_out_start (dwc_otg_core_if_t *  core_if, void ep0_out_start ( dwc_otg_core_if_t *  core_if,
    dwc_otg_pcd_t *  pcd dwc_otg_pcd_t *  pcd
    ) [inline, static])  [inline, static]
    +- +-
    ++
    ++ ++ ++ ++
    ++   ++ + +

    + This function configures EPO to receive SETUP packets. +

    +-

    Todo:
    NGS: Update the comments from the HW FS.
    ++
    Todo:
    NGS: Update the comments from the HW FS.
    +
      +
    1. Program the following fields in the endpoint specific registers for Control OUT EP 0, in order to receive a setup packet
    +
      +@@ -548,37 +576,44 @@ +
      Parameters:
      + + +- ++ +
      core_if Programming view of DWC_otg controller.
      pcd Programming view of the PCD.
      pcd Programming view of the PCD.
      +
      +- +

      +-put here as for Hermes mode deptisz register should not be written

      +-

      Todo:
      dma needs to handle multiple setup packets (up to 3)
      ++put here as for Hermes mode deptisz register should not be written

      ++

      Todo:
      dma needs to handle multiple setup packets (up to 3)
      +

      +-DMA Descriptor Setup

      +-DOEPDMA0 Register write

      +-put here as for Hermes mode deptisz register should not be written

      ++DMA Descriptor Setup

      ++DOEPDMA0 Register write

      ++put here as for Hermes mode deptisz register should not be written

      + DOEPCTL0 Register write +

      +-Definition at line 684 of file dwc_otg_pcd_intr.c. +- +-

      +- +-

      +-
      +- +- +- +- +- +- +- +- ++Definition at line 732 of file dwc_otg_pcd_intr.c. ++ ++
      int32_t dwc_otg_pcd_handle_usb_reset_intr (dwc_otg_pcd_t *  pcd  ) 
      ++

      ++ ++ ++ ++ ++
      ++ ++ ++ ++ ++ ++ ++ ++ + +
      int32_t dwc_otg_pcd_handle_usb_reset_intr ( dwc_otg_pcd_t *  pcd  ) 
      +- +-
      ++
      ++ ++ ++ ++
      ++   ++ + +

      + This interrupt occurs when a USB Reset is detected. +@@ -597,24 +632,32 @@ + + +

      +-Definition at line 772 of file dwc_otg_pcd_intr.c. +- +-

      +- +-

      +-
      +- +- +- +- +- +- +- +- ++Definition at line 822 of file dwc_otg_pcd_intr.c. ++ ++
      static int get_device_speed (dwc_otg_core_if_t *  core_if  )  [static]
      ++

      ++ ++ ++ ++ ++
      ++ ++ ++ ++ ++ ++ ++ ++ + +
      int get_device_speed ( dwc_otg_core_if_t *  core_if  )  [static]
      +- +-
      ++
      ++ ++ ++ ++
      ++   ++ + +

      + Get the device speed from the device status register and convert it to USB speed constant. +@@ -626,301 +669,416 @@ + + +

      +-Definition at line 928 of file dwc_otg_pcd_intr.c. +- +-

      +- +-

      +-
      +- +- +- +- +- +- +- +- ++Definition at line 1007 of file dwc_otg_pcd_intr.c. ++ ++
      int32_t dwc_otg_pcd_handle_enum_done_intr (dwc_otg_pcd_t *  pcd  ) 
      ++

      ++ ++ ++ ++ ++
      ++ ++ ++ ++ ++ ++ ++ ++ + +
      int32_t dwc_otg_pcd_handle_enum_done_intr ( dwc_otg_pcd_t *  pcd  ) 
      +- +-
      ++
      ++ ++ ++ ++
      ++   ++ + +

      + Read the device status register and set the device speed in the data structure. +

      + Set up EP0 to receive SETUP packets by calling dwc_ep0_activate. +

      +-Definition at line 956 of file dwc_otg_pcd_intr.c. +- +-

      +- +-

      +-
      +- +- +- +- +- +- +- +- ++Definition at line 1035 of file dwc_otg_pcd_intr.c. ++ ++
      int32_t dwc_otg_pcd_handle_isoc_out_packet_dropped_intr (dwc_otg_pcd_t *  pcd  ) 
      ++

      ++ ++ ++ ++ ++
      ++ ++ ++ ++ ++ ++ ++ ++ + +
      int32_t dwc_otg_pcd_handle_isoc_out_packet_dropped_intr ( dwc_otg_pcd_t *  pcd  ) 
      +- +-
      ++
      ++ ++ ++ ++
      ++   ++ + +

      + This interrupt indicates that the ISO OUT Packet was dropped due to Rx FIFO full or Rx Status Queue Full. +

      + If this interrupt occurs read all the data from the Rx FIFO. +

      +-Definition at line 1051 of file dwc_otg_pcd_intr.c. +- +-

      +- +-

      +-
      +- +- +- +- +- +- +- +- ++Definition at line 1130 of file dwc_otg_pcd_intr.c. ++ ++
      int32_t dwc_otg_pcd_handle_end_periodic_frame_intr (dwc_otg_pcd_t *  pcd  ) 
      ++

      ++ ++ ++ ++ ++
      ++ ++ ++ ++ ++ ++ ++ ++ + +
      int32_t dwc_otg_pcd_handle_end_periodic_frame_intr ( dwc_otg_pcd_t *  pcd  ) 
      +- +-
      ++
      ++ ++ ++ ++
      ++   ++ + +

      + This interrupt indicates the end of the portion of the micro-frame for periodic transactions. +

      + If there is a periodic transaction for the next frame, load the packets into the EP periodic Tx FIFO. +

      +-Definition at line 1077 of file dwc_otg_pcd_intr.c. +- +-

      +- +-

      +-
      +- +- +- +- +- +- +- +- ++Definition at line 1156 of file dwc_otg_pcd_intr.c. ++ ++
      int32_t dwc_otg_pcd_handle_ep_mismatch_intr (dwc_otg_core_if_t *  core_if  ) 
      ++

      ++ ++ ++ ++ ++
      ++ ++ ++ ++ ++ ++ ++ ++ + +
      int32_t dwc_otg_pcd_handle_ep_mismatch_intr ( dwc_otg_pcd_t *  pcd  ) 
      +- +-
      ++
      ++ ++ ++ ++
      ++   ++ + +

      + This interrupt indicates that EP of the packet on the top of the non-periodic Tx FIFO does not match EP of the IN Token received. +

      + The "Device IN Token Queue" Registers are read to determine the order the IN Tokens have been received. The non-periodic Tx FIFO is flushed, so it can be reloaded in the order seen in the IN Token Queue. +

      +-Definition at line 1105 of file dwc_otg_pcd_intr.c. +- +-

      +- +-

      +-
      +- ++Definition at line 1184 of file dwc_otg_pcd_intr.c. ++ ++
      ++

      ++ ++ ++ ++ ++
      ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
      int32_t dwc_otg_pcd_handle_ep_fetsusp_intr ( dwc_otg_pcd_t *  pcd  ) 
      ++
      ++ ++ ++ ++ ++ ++
      ++   ++ ++ ++

      ++This interrupt is valid only in DMA mode. ++

      ++This interrupt indicates that the core has stopped fetching data for IN endpoints due to the unavailability of TxFIFO space or Request Queue space. This interrupt is used by the application for an endpoint mismatch algorithm.

      ++

      Parameters:
      ++ ++ ++
      pcd The PCD
      ++
      ++ ++

      ++Definition at line 1232 of file dwc_otg_pcd_intr.c.

      ++

      ++ ++ ++ ++ ++
      ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
      static void do_gadget_setup (dwc_otg_pcd_t *  pcd, void do_gadget_setup ( dwc_otg_pcd_t *  pcd,
      usb_device_request_t *  ctrl usb_device_request_t *  ctrl
      ) [inline, static])  [inline, static]
      +- +-
      ++
      ++ ++ ++ ++
      ++   ++ + +

      + This functions delegates the setup command to the gadget driver. +

      ++

      Todo:
      This is a g_file_storage gadget driver specific workaround: a DELAYED_STATUS result from the fsg_setup routine will result in the gadget queueing a EP0 IN status phase for a two-stage control transfer. Exactly the same as a SET_CONFIGURATION/SET_INTERFACE except that this is a class specific request. Need a generic way to know when the gadget driver will queue the status phase. Can we assume when we call the gadget driver setup() function that it will always queue and require the following flag? Need to look into this.
      + +

      +-

      Todo:
      This is a g_file_storage gadget driver specific workaround: a DELAYED_STATUS result from the fsg_setup routine will result in the gadget queueing a EP0 IN status phase for a two-stage control transfer. Exactly the same as a SET_CONFIGURATION/SET_INTERFACE except that this is a class specific request. Need a generic way to know when the gadget driver will queue the status phase. Can we assume when we call the gadget driver setup() function that it will always queue and require the following flag? Need to look into this.
      +- +-

      +-Definition at line 1138 of file dwc_otg_pcd_intr.c. +- +-

      +- +-

      +-
      +- ++Definition at line 1277 of file dwc_otg_pcd_intr.c. ++ ++
      ++

      ++ ++ ++ ++ ++
      ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
      static void pcd_clear_halt (dwc_otg_pcd_t *  pcd, void pcd_clear_halt ( dwc_otg_pcd_t *  pcd,
      dwc_otg_pcd_ep_t *  ep dwc_otg_pcd_ep_t *  ep
      ) [inline, static])  [inline, static]
      +- +-
      ++
      ++ ++ ++ ++
      ++   ++ + +

      + Clear the EP halt (STALL) and if pending requests start the transfer. +

      ++

      Todo:
      FIXME: this causes an EP mismatch in DMA mode. epmismatch not yet implemented.
      + +

      +-

      Todo:
      FIXME: this causes an EP mismatch in DMA mode. epmismatch not yet implemented.
      +- +-

      +-Definition at line 1245 of file dwc_otg_pcd_intr.c. +- +-

      +- +-

      +-
      +- +- +- +- +- +- +- +- ++Definition at line 1384 of file dwc_otg_pcd_intr.c. ++ ++
      void do_test_mode (void *  data  ) 
      ++

      ++ ++ ++ ++ ++
      ++ ++ ++ ++ ++ ++ ++ ++ + +
      void do_test_mode ( void *  data  ) 
      +- +-
      ++
      ++ ++ ++ ++
      ++   ++ + +

      + This function is called when the SET_FEATURE TEST_MODE Setup packet is sent from the host. +

      + The Device Control register is written with the Test Mode bits set to the specified Test Mode. This is done as a tasklet so that the "Status" phase of the control transfer completes before transmitting the TEST packets.

      +-

      Todo:
      This has not been tested since the tasklet struct was put into the PCD struct!
      ++
      Todo:
      This has not been tested since the tasklet struct was put into the PCD struct!
      + +

      +-Definition at line 1284 of file dwc_otg_pcd_intr.c. +- +-

      +- +-

      +-
      +- +- +- +- +- +- +- +- ++Definition at line 1423 of file dwc_otg_pcd_intr.c. ++ ++
      static void do_get_status (dwc_otg_pcd_t *  pcd  )  [inline, static]
      ++

      ++ ++ ++ ++ ++
      ++ ++ ++ ++ ++ ++ ++ ++ + +
      void do_get_status ( dwc_otg_pcd_t *  pcd  )  [inline, static]
      +- +-
      ++
      ++ ++ ++ ++
      ++   ++ + +

      + This function process the GET_STATUS Setup Commands. +

      ++

      Todo:
      check for EP stall
      + +

      +-

      Todo:
      check for EP stall
      +- +-

      +-Definition at line 1321 of file dwc_otg_pcd_intr.c. +- +-

      +- +-

      +-
      +- +- +- +- +- +- +- +- ++Definition at line 1460 of file dwc_otg_pcd_intr.c. ++ ++
      static void do_set_feature (dwc_otg_pcd_t *  pcd  )  [inline, static]
      ++

      ++ ++ ++ ++ ++
      ++ ++ ++ ++ ++ ++ ++ ++ + +
      void do_set_feature ( dwc_otg_pcd_t *  pcd  )  [inline, static]
      +- +-
      ++
      ++ ++ ++ ++
      ++   ++ + +

      + This function process the SET_FEATURE Setup Commands. +

      ++

      Todo:
      This has not been tested since the tasklet struct was put into the PCD struct!

      ++Is the gotgctl.devhnpen cleared by a USB Reset?

      + +

      +-

      Todo:
      This has not been tested since the tasklet struct was put into the PCD struct!
      +-

      +-

      Todo:
      Is the gotgctl.devhnpen cleared by a USB Reset?
      +- +-

      +-Definition at line 1369 of file dwc_otg_pcd_intr.c. +- +-

      +- +-

      +-
      +- +- +- +- +- +- +- +- ++Definition at line 1533 of file dwc_otg_pcd_intr.c. ++ ++
      static void do_clear_feature (dwc_otg_pcd_t *  pcd  )  [inline, static]
      ++

      ++ ++ ++ ++ ++
      ++ ++ ++ ++ ++ ++ ++ ++ + +
      void do_clear_feature ( dwc_otg_pcd_t *  pcd  )  [inline, static]
      +- +-
      ++
      ++ ++ ++ ++
      ++   ++ + +

      + This function process the CLEAR_FEATURE Setup Commands. +

      ++

      Todo:
      Add CLEAR_FEATURE for TEST modes.
      + +

      +-

      Todo:
      Add CLEAR_FEATURE for TEST modes.
      +- +-

      +-Definition at line 1472 of file dwc_otg_pcd_intr.c. +- +-

      +- +-

      +-
      +- +- +- +- +- +- +- +- ++Definition at line 1644 of file dwc_otg_pcd_intr.c. ++ ++
      static void pcd_setup (dwc_otg_pcd_t *  pcd  )  [inline, static]
      ++

      ++ ++ ++ ++ ++
      ++ ++ ++ ++ ++ ++ ++ ++ + +
      void pcd_setup ( dwc_otg_pcd_t *  pcd  )  [inline, static]
      +- +-
      ++
      ++ ++ ++ ++ +
      ++   ++ + +

      + This function processes SETUP commands. +@@ -964,64 +1122,78 @@ +

      		SYNC_FRAME PCD Display debug message.
      +

      +-When the SETUP Phase Done interrupt occurs, the PCD SETUP commands are processed by pcd_setup. Calling the Function Driver's setup function from pcd_setup processes the gadget SETUP commands. +-

      +-

      Todo:
      handle > 1 setup packet , assert error for now
      +-

      +-

      Todo:
      NGS: Handle bad setup packet?
      ++When the SETUP Phase Done interrupt occurs, the PCD SETUP commands are processed by pcd_setup. Calling the Function Driver's setup function from pcd_setup processes the gadget SETUP commands.

      ++

      Todo:
      handle > 1 setup packet , assert error for now

      ++NGS: Handle bad setup packet?

      + +

      +-Definition at line 1580 of file dwc_otg_pcd_intr.c. +-

      +-

      +- +-

      +-
      +- +- +- +- +- +- +- +- ++Definition at line 1756 of file dwc_otg_pcd_intr.c. ++ ++
      static void complete_ep (dwc_otg_pcd_ep_t *  ep  )  [static]
      ++

      ++ ++ ++ ++ ++
      ++ ++ ++ ++ ++ ++ ++ ++ + +
      void complete_ep ( dwc_otg_pcd_ep_t *  ep  )  [static]
      +- +-
      ++
      ++ ++ ++ ++
      ++   ++ + +

      + This function completes the request for the EP. +

      + If there are additional requests for the EP in the queue they will be started. +

      +-Definition at line 1911 of file dwc_otg_pcd_intr.c. +- +-

      +- +-

      +-
      +- ++Definition at line 2088 of file dwc_otg_pcd_intr.c. ++ ++
      ++

      ++ ++ ++ ++ ++
      ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
      void set_current_pkt_info (dwc_otg_core_if_t *  core_if, void set_current_pkt_info ( dwc_otg_core_if_t *  core_if,
      dwc_ep_t *  ep dwc_ep_t *  ep
      )) 
      +- +-
      ++
      ++ ++ ++ ++
      ++   ++ + +

      + This function sets latest iso packet information(non-PTI mode). +@@ -1034,33 +1206,41 @@ + + +

      +-Definition at line 2274 of file dwc_otg_pcd_intr.c. +- +-

      +- +-

      +-
      +- ++Definition at line 2490 of file dwc_otg_pcd_intr.c. ++ ++
      ++

      ++ ++ ++ ++ ++
      ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
      static void set_ddma_iso_pkts_info (dwc_otg_core_if_t *  core_if, void set_ddma_iso_pkts_info ( dwc_otg_core_if_t *  core_if,
      dwc_ep_t *  dwc_ep dwc_ep_t *  dwc_ep
      ) [static])  [static]
      +- +-
      ++
      ++ ++ ++ ++
      ++   ++ + +

      + This function sets latest iso packet information(DDMA mode). +@@ -1068,42 +1248,49 @@ +

      Parameters:
      + + +- ++ +
      core_if Programming view of DWC_otg controller.
      dwc_ep The EP to start the transfer on.
      dwc_ep The EP to start the transfer on.
      +
      +- +

      + Reinit closed DMA Descriptors

      +-ISO OUT EP

      ++ISO OUT EP

      + ISO IN EP +

      +-Definition at line 2322 of file dwc_otg_pcd_intr.c. +- +-

      +- +-

      +-
      +- ++Definition at line 2538 of file dwc_otg_pcd_intr.c. ++ ++
      ++

      ++ ++ ++ ++ ++
      ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
      static void reinit_ddma_iso_xfer (dwc_otg_core_if_t *  core_if, void reinit_ddma_iso_xfer ( dwc_otg_core_if_t *  core_if,
      dwc_ep_t *  dwc_ep dwc_ep_t *  dwc_ep
      ) [static])  [static]
      +- +-
      ++
      ++ ++ ++ ++
      ++   ++ + +

      + This function reinitialize DMA Descriptors for Isochronous transfer. +@@ -1111,44 +1298,51 @@ +

      Parameters:
      + + +- ++ +
      core_if Programming view of DWC_otg controller.
      dwc_ep The EP to start the transfer on.
      dwc_ep The EP to start the transfer on.
      +
      +- +

      +-Buffer 0 descriptors setup

      +-Buffer 1 descriptors setup

      ++Buffer 0 descriptors setup

      ++Buffer 1 descriptors setup

      + Reinit closed DMA Descriptors

      +-ISO OUT EP

      ++ISO OUT EP

      + ISO IN EP +

      +-Definition at line 2486 of file dwc_otg_pcd_intr.c. +- +-

      +- +-

      +-
      +- ++Definition at line 2701 of file dwc_otg_pcd_intr.c. ++ ++
      ++

      ++ ++ ++ ++ ++
      ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
      static uint32_t handle_iso_out_pkt_dropped (dwc_otg_core_if_t *  core_if, uint32_t handle_iso_out_pkt_dropped ( dwc_otg_core_if_t *  core_if,
      dwc_ep_t *  dwc_ep dwc_ep_t *  dwc_ep
      ) [static])  [static]
      +- +-
      ++
      ++ ++ ++ ++
      ++   ++ + +

      + This function is to handle Iso EP transfer complete interrupt in case Iso out packet was dropped. +@@ -1156,40 +1350,47 @@ +

      Parameters:
      + + +- ++ +
      core_if Programming view of DWC_otg controller.
      dwc_ep The EP for wihich transfer complete was asserted
      dwc_ep The EP for wihich transfer complete was asserted
      +
      +- +

      + Re-enable endpoint, clear nak +

      +-Definition at line 2620 of file dwc_otg_pcd_intr.c. +- +-

      +- +-

      +-
      +- ++Definition at line 2835 of file dwc_otg_pcd_intr.c. ++ ++
      ++

      ++ ++ ++ ++ ++
      ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
      static uint32_t set_iso_pkts_info (dwc_otg_core_if_t *  core_if, uint32_t set_iso_pkts_info ( dwc_otg_core_if_t *  core_if,
      dwc_ep_t *  ep dwc_ep_t *  ep
      ) [static])  [static]
      +- +-
      ++
      ++ ++ ++ ++
      ++   ++ + +

      + This function sets iso packets information(PTI mode). +@@ -1197,41 +1398,48 @@ +

      Parameters:
      + + +- ++ +
      core_if Programming view of DWC_otg controller.
      ep The EP to start the transfer on.
      ep The EP to start the transfer on.
      +
      +- +

      +-Buffer 0 descriptors setup

      ++Buffer 0 descriptors setup

      + Buffer 1 descriptors setup +

      +-Definition at line 2690 of file dwc_otg_pcd_intr.c. +- +-

      +- +-

      +-
      +- ++Definition at line 2906 of file dwc_otg_pcd_intr.c. ++ ++
      ++

      ++ ++ ++ ++ ++
      ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
      static void complete_iso_ep (dwc_otg_pcd_t *  pcd, void complete_iso_ep ( dwc_otg_pcd_t *  pcd,
      dwc_otg_pcd_ep_t *  ep dwc_otg_pcd_ep_t *  ep
      ) [static])  [static]
      +- +-
      ++
      ++ ++ ++ ++
      ++   ++ + +

      + This function is to handle Iso EP transfer complete interrupt. +@@ -1244,288 +1452,348 @@ + + +

      +-Definition at line 2766 of file dwc_otg_pcd_intr.c. +- +-

      +- +-

      +-
      +- +- +- +- +- +- +- +- ++Definition at line 2982 of file dwc_otg_pcd_intr.c. ++ ++
      static void handle_ep0 (dwc_otg_pcd_t *  pcd  )  [static]
      ++

      ++ ++ ++ ++ ++
      ++ ++ ++ ++ ++ ++ ++ ++ + +
      void handle_ep0 ( dwc_otg_pcd_t *  pcd  )  [static]
      +- +-
      ++
      ++ ++ ++ ++
      ++   ++ + +

      + This function handles EP0 Control transfers. +

      + The state of the control tranfers are tracked in ep0state. +

      +-Definition at line 2843 of file dwc_otg_pcd_intr.c. +- +-

      +- +-

      +-
      +- ++Definition at line 3110 of file dwc_otg_pcd_intr.c. ++ ++
      ++

      ++ ++ ++ ++ ++
      ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
      static void handle_in_ep_timeout_intr (dwc_otg_pcd_t *  pcd, void handle_in_ep_timeout_intr ( dwc_otg_pcd_t *  pcd,
      const uint32_t  epnum const uint32_t  epnum
      ) [inline, static])  [inline, static]
      +- +-
      ++
      ++ ++ ++ ++
      ++   ++ + +

      + Handler for the IN EP timeout handshake interrupt. +

      ++

      Todo:
      NGS Check EP type. Implement for Periodic EPs
      + +

      +-

      Todo:
      NGS Check EP type. Implement for Periodic EPs
      +- +-

      +-Definition at line 3080 of file dwc_otg_pcd_intr.c. +- +-

      +- +-

      +-
      +- ++Definition at line 3611 of file dwc_otg_pcd_intr.c. ++ ++
      ++

      ++ ++ ++ ++ ++
      ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
      static int32_t handle_in_ep_nak_intr (dwc_otg_pcd_t *  pcd, int32_t handle_in_ep_nak_intr ( dwc_otg_pcd_t *  pcd,
      const uint32_t  epnum const uint32_t  epnum
      ) [inline, static])  [inline, static]
      +- +-
      ++
      ++ ++ ++ ++
      ++   ++ + +

      + Handler for the IN EP NAK interrupt. +

      ++

      Todo:
      implement ISR
      + +

      +-

      Todo:
      implement ISR
      +- +-

      +-Definition at line 3141 of file dwc_otg_pcd_intr.c. +- +-

      +- +-

      +-
      +- ++Definition at line 3672 of file dwc_otg_pcd_intr.c. ++ ++
      ++

      ++ ++ ++ ++ ++
      ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
      static int32_t handle_out_ep_babble_intr (dwc_otg_pcd_t *  pcd, int32_t handle_out_ep_babble_intr ( dwc_otg_pcd_t *  pcd,
      const uint32_t  epnum const uint32_t  epnum
      ) [inline, static])  [inline, static]
      +- +-
      ++
      ++ ++ ++ ++
      ++   ++ + +

      + Handler for the OUT EP Babble interrupt. +

      ++

      Todo:
      implement ISR
      + +

      +-

      Todo:
      implement ISR
      +- +-

      +-Definition at line 3166 of file dwc_otg_pcd_intr.c. +- +-

      +- +-

      +-
      +- ++Definition at line 3697 of file dwc_otg_pcd_intr.c. ++ ++
      ++

      ++ ++ ++ ++ ++
      ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
      static int32_t handle_out_ep_nak_intr (dwc_otg_pcd_t *  pcd, int32_t handle_out_ep_nak_intr ( dwc_otg_pcd_t *  pcd,
      const uint32_t  epnum const uint32_t  epnum
      ) [inline, static])  [inline, static]
      +- +-
      ++
      ++ ++ ++ ++
      ++   ++ + +

      + Handler for the OUT EP NAK interrupt. +

      ++

      Todo:
      implement ISR
      + +

      +-

      Todo:
      implement ISR
      +- +-

      +-Definition at line 3192 of file dwc_otg_pcd_intr.c. +- +-

      +- +-

      +-
      +- ++Definition at line 3723 of file dwc_otg_pcd_intr.c. ++ ++
      ++

      ++ ++ ++ ++ ++
      ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
      static int32_t handle_out_ep_nyet_intr (dwc_otg_pcd_t *  pcd, int32_t handle_out_ep_nyet_intr ( dwc_otg_pcd_t *  pcd,
      const uint32_t  epnum const uint32_t  epnum
      ) [inline, static])  [inline, static]
      +- +-
      ++
      ++ ++ ++ ++
      ++   ++ + +

      + Handler for the OUT EP NYET interrupt. +

      ++

      Todo:
      implement ISR
      + +

      +-

      Todo:
      implement ISR
      +- +-

      +-Definition at line 3217 of file dwc_otg_pcd_intr.c. +- +-

      +- +-

      +-
      +- +- +- +- +- +- +- +- ++Definition at line 3748 of file dwc_otg_pcd_intr.c. ++ ++
      static int32_t dwc_otg_pcd_handle_in_ep_intr (dwc_otg_pcd_t *  pcd  )  [static]
      ++

      ++ ++ ++ ++ ++
      ++ ++ ++ ++ ++ ++ ++ ++ + +
      int32_t dwc_otg_pcd_handle_in_ep_intr ( dwc_otg_pcd_t *  pcd  )  [static]
      +- +-
      ++
      ++ ++ ++ ++
      ++   ++ + +

      + This interrupt indicates that an IN EP has a pending Interrupt. +

      + The sequence for handling the IN EP interrupt is shown below:

        +-
      1. Read the Device All Endpoint Interrupt register
      2. Repeat the following for each IN EP interrupt bit set (from LSB to MSB).
      3. Read the Device Endpoint Interrupt (DIEPINTn) register
      4. If "Transfer Complete" call the request complete function
      5. If "Endpoint Disabled" complete the EP disable procedure.
      6. If "AHB Error Interrupt" log error
      7. If "Time-out Handshake" log error
      8. If "IN Token Received when TxFIFO Empty" write packet to Tx FIFO.
      9. If "IN Token EP Mismatch" (disable, this is handled by EP Mismatch Interrupt)
      +- ++
    • Read the Device All Endpoint Interrupt register
    • Repeat the following for each IN EP interrupt bit set (from LSB to MSB).
    • Read the Device Endpoint Interrupt (DIEPINTn) register
    • If "Transfer Complete" call the request complete function
    • If "Endpoint Disabled" complete the EP disable procedure.
    • If "AHB Error Interrupt" log error
    • If "Time-out Handshake" log error
    • If "IN Token Received when TxFIFO Empty" write packet to Tx FIFO.
    • If "IN Token EP Mismatch" (disable, this is handled by EP Mismatch Interrupt)
      • +

      +-IN Token received with TxF Empty

      +-IN Token Received with EP mismatch

      +-IN Endpoint NAK Effective

      +-IN EP Tx FIFO Empty Intr

      ++IN Token received with TxF Empty

      ++IN Token Received with EP mismatch

      ++IN Endpoint NAK Effective

      ++IN EP Tx FIFO Empty Intr

      + IN EP BNA Intr +

      +-Definition at line 3255 of file dwc_otg_pcd_intr.c. +- +-

      +- +-

      +-
      +- +- +- +- +- +- +- +- ++Definition at line 3786 of file dwc_otg_pcd_intr.c. ++ ++
      static int32_t dwc_otg_pcd_handle_out_ep_intr (dwc_otg_pcd_t *  pcd  )  [static]
      ++

      ++ ++ ++ ++ ++
      ++ ++ ++ ++ ++ ++ ++ ++ + +
      int32_t dwc_otg_pcd_handle_out_ep_intr ( dwc_otg_pcd_t *  pcd  )  [static]
      +- +-
      ++
      ++ ++ ++ ++
      ++   ++ + +

      + This interrupt indicates that an OUT EP has a pending Interrupt. +

      + The sequence for handling the OUT EP interrupt is shown below:

        +-
      1. Read the Device All Endpoint Interrupt register
      2. Repeat the following for each OUT EP interrupt bit set (from LSB to MSB).
      3. Read the Device Endpoint Interrupt (DOEPINTn) register
      4. If "Transfer Complete" call the request complete function
      5. If "Endpoint Disabled" complete the EP disable procedure.
      6. If "AHB Error Interrupt" log error
      7. If "Setup Phase Done" process Setup Packet (See Standard USB Command Processing)
      +- ++
    • Read the Device All Endpoint Interrupt register
    • Repeat the following for each OUT EP interrupt bit set (from LSB to MSB).
    • Read the Device Endpoint Interrupt (DOEPINTn) register
    • If "Transfer Complete" call the request complete function
    • If "Endpoint Disabled" complete the EP disable procedure.
    • If "AHB Error Interrupt" log error
    • If "Setup Phase Done" process Setup Packet (See Standard USB Command Processing)
      • +

      + OUT EP BNA Intr +

      +-Definition at line 3522 of file dwc_otg_pcd_intr.c. +- +-

      +- +-

      +-
      +- +- +- +- +- +- +- +- ++Definition at line 4068 of file dwc_otg_pcd_intr.c. ++ ++
      int32_t dwc_otg_pcd_handle_incomplete_isoc_in_intr (dwc_otg_pcd_t *  pcd  ) 
      ++

      ++ ++ ++ ++ ++
      ++ ++ ++ ++ ++ ++ ++ ++ + +
      int32_t dwc_otg_pcd_handle_incomplete_isoc_in_intr ( dwc_otg_pcd_t *  pcd  ) 
      +- +-
      ++
      ++ ++ ++ ++
      ++   ++ + +

      + Incomplete ISO IN Transfer Interrupt. +@@ -1536,52 +1804,68 @@ + + +

      +-Definition at line 3725 of file dwc_otg_pcd_intr.c. +- +-

      +- +-

      +-
      +- +- +- +- +- +- +- +- ++Definition at line 4348 of file dwc_otg_pcd_intr.c. ++ ++
      int32_t dwc_otg_pcd_handle_incomplete_isoc_out_intr (dwc_otg_pcd_t *  pcd  ) 
      ++

      ++ ++ ++ ++ ++
      ++ ++ ++ ++ ++ ++ ++ ++ + +
      int32_t dwc_otg_pcd_handle_incomplete_isoc_out_intr ( dwc_otg_pcd_t *  pcd  ) 
      +- +-
      ++
      ++ ++ ++ ++
      ++   ++ + +

      + Incomplete ISO OUT Transfer Interrupt. +

      + This interrupt indicates that the core has dropped an ISO OUT packet. The following conditions can be the cause:

        +
      • FIFO Full, the entire packet would not fit in the FIFO.
      • CRC Error
      • Corrupted Token The follow actions will be taken:
          +-
        1. Determine the EP
        2. Set incomplete flag in dwc_ep structure
        3. Read any data from the FIFO
        4. Disable EP. when "Endpoint Disabled" interrupt is received re-enable EP.
        ++
      • Determine the EP
      • Set incomplete flag in dwc_ep structure
      • Read any data from the FIFO
      • Disable EP. When "Endpoint Disabled" interrupt is received re-enable EP.
        • +
      + +

      +-Definition at line 3814 of file dwc_otg_pcd_intr.c. +- +-

      +- +-

      +-
      +- +- +- +- +- +- +- +- ++Definition at line 4458 of file dwc_otg_pcd_intr.c. ++ ++
      int32_t dwc_otg_pcd_handle_intr (dwc_otg_pcd_t *  pcd  ) 
      ++

      ++ ++ ++ ++ ++
      ++ ++ ++ ++ ++ ++ ++ ++ + +
      int32_t dwc_otg_pcd_handle_intr ( dwc_otg_pcd_t *  pcd  ) 
      +- +-
      ++
      ++ ++ ++ ++ ++ ++
      ++   ++ + +

      + This function should be called on every hardware interrupt. +@@ -1589,11 +1873,11 @@ + The PCD handles the device interrupts. Many conditions can cause a device interrupt. When an interrupt occurs, the device interrupt service routine determines the cause of the interrupt and dispatches handling to the appropriate function. These interrupt handling functions are described below.

      + All interrupt registers are processed from LSB to MSB. +

      +-Definition at line 3971 of file dwc_otg_pcd_intr.c. +- +-

      +-

      Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++Definition at line 4702 of file dwc_otg_pcd_intr.c.
      ++

      Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
      ++doxygen 1.3.9.1 + + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__pcd__linux_8c-source.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/dwc__otg__pcd__linux_8c-source.html 2013-07-26 19:31:22.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__pcd__linux_8c-source.html 2013-07-26 19:34:42.000000000 +0000 +@@ -2,996 +2,1121 @@ + + DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_pcd_linux.c Source File + +- + +- +-
      +-
      +-
      +-
      +-

      dwc_otg_pcd_linux.c

      Go to the documentation of this file.
      00001  /* ==========================================================================
+-00002   * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_pcd_linux.c $
+-00003   * $Revision: #7 $
+-00004   * $Date: 2009/04/03 $
+-00005   * $Change: 1225160 $
+-00006   *
+-00007   * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
+-00008   * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
+-00009   * otherwise expressly agreed to in writing between Synopsys and you.
+-00010   *
+-00011   * The Software IS NOT an item of Licensed Software or Licensed Product under
+-00012   * any End User Software License Agreement or Agreement for Licensed Product
+-00013   * with Synopsys or any supplement thereto. You are permitted to use and
+-00014   * redistribute this Software in source and binary forms, with or without
+-00015   * modification, provided that redistributions of source code must retain this
+-00016   * notice. You may not view, use, disclose, copy or distribute this file or
+-00017   * any information contained herein except pursuant to this license grant from
+-00018   * Synopsys. If you do not agree with this notice, including the disclaimer
+-00019   * below, then you are not authorized to use the Software.
+-00020   *
+-00021   * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
+-00022   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+-00023   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+-00024   * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
+-00025   * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+-00026   * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+-00027   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+-00028   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+-00029   * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+-00030   * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+-00031   * DAMAGE.
+-00032   * ========================================================================== */
+-00033 #ifndef DWC_HOST_ONLY
+-00034 
+-00056 #include <linux/kernel.h>
+-00057 #include <linux/module.h>
+-00058 #include <linux/moduleparam.h>
+-00059 #include <linux/init.h>
+-00060 #include <linux/device.h>
+-00061 #include <linux/errno.h>
+-00062 #include <linux/list.h>
+-00063 #include <linux/interrupt.h>
+-00064 #include <linux/string.h>
+-00065 #include <linux/dma-mapping.h>
+-00066 #include <linux/version.h>
+-00067 
+-00068 #ifdef LM_INTERFACE
+-00069 # include <asm/arch/regs-irq.h>
+-00070 # include <asm/arch/lm.h>
+-00071 # include <asm/arch/irqs.h>
+-00072 #endif
+-00073 
+-00074 #include <asm/io.h>
+-00075 # include <linux/usb_ch9.h>
+-00076 #include <linux/usb_gadget.h>
+-00077 
+-00078 #include "dwc_otg_pcd_if.h"
+-00079 #include "dwc_otg_driver.h"
+-00080 #include "dwc_otg_dbg.h"
+-00081 
+-00082 static struct gadget_wrapper {
+-00083         dwc_otg_pcd_t *pcd;
+-00084 
+-00085         struct usb_gadget gadget;
+-00086         struct usb_gadget_driver *driver;
+-00087 
+-00088         struct usb_ep ep0;
+-00089         struct usb_ep in_ep[16];
+-00090         struct usb_ep out_ep[16];
+-00091 
+-00092 } *gadget_wrapper;
+-00093 
+-00094 /* Display the contents of the buffer */
+-00095 extern void dump_msg(const u8 * buf, unsigned int length);
+-00096 
+-00097 /* USB Endpoint Operations */
+-00098 /*
+-00099  * The following sections briefly describe the behavior of the Gadget
+-00100  * API endpoint operations implemented in the DWC_otg driver
+-00101  * software. Detailed descriptions of the generic behavior of each of
+-00102  * these functions can be found in the Linux header file
+-00103  * include/linux/usb_gadget.h.
+-00104  *
+-00105  * The Gadget API provides wrapper functions for each of the function
+-00106  * pointers defined in usb_ep_ops. The Gadget Driver calls the wrapper
+-00107  * function, which then calls the underlying PCD function. The
+-00108  * following sections are named according to the wrapper
+-00109  * functions. Within each section, the corresponding DWC_otg PCD
+-00110  * function name is specified.
+-00111  *
+-00112  */
+-00113 
+-00121 static int ep_enable(struct usb_ep *usb_ep,
+-00122                      const struct usb_endpoint_descriptor *ep_desc)
+-00123 {
+-00124         int retval;
+-00125 
+-00126         DWC_DEBUGPL(DBG_PCDV, "%s(%p,%p)\n", __func__, usb_ep, ep_desc);
+-00127 
+-00128         if (!usb_ep || !ep_desc || ep_desc->bDescriptorType != USB_DT_ENDPOINT) {
+-00129                 DWC_WARN("%s, bad ep or descriptor\n", __func__);
+-00130                 return -EINVAL;
+-00131         }
+-00132         if (usb_ep == &gadget_wrapper->ep0) {
+-00133                 DWC_WARN("%s, bad ep(0)\n", __func__);
+-00134                 return -EINVAL;
+-00135         }
+-00136 
+-00137         /* Check FIFO size? */
+-00138         if (!ep_desc->wMaxPacketSize) {
+-00139                 DWC_WARN("%s, bad %s maxpacket\n", __func__, usb_ep->name);
+-00140                 return -ERANGE;
+-00141         }
+-00142 
+-00143         if (!gadget_wrapper->driver ||
+-00144             gadget_wrapper->gadget.speed == USB_SPEED_UNKNOWN) {
+-00145                 DWC_WARN("%s, bogus device state\n", __func__);
+-00146                 return -ESHUTDOWN;
+-00147         }
+-00148 
+-00149         retval = dwc_otg_pcd_ep_enable(gadget_wrapper->pcd,
+-00150                                        (const uint8_t *)ep_desc,
+-00151                                        (void *)usb_ep);
+-00152         if (retval) {
+-00153                 DWC_WARN("dwc_otg_pcd_ep_enable failed\n");
+-00154                 return -EINVAL;
+-00155         }
+-00156 
+-00157         usb_ep->maxpacket = le16_to_cpu(ep_desc->wMaxPacketSize);
+-00158 
+-00159         return 0;
+-00160 }
+-00161 
+-00170 static int ep_disable(struct usb_ep *usb_ep)
+-00171 {
+-00172         int retval;
+-00173 
+-00174         DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, usb_ep);
+-00175         if (!usb_ep) {
+-00176                 DWC_DEBUGPL(DBG_PCD, "%s, %s not enabled\n", __func__,
+-00177                             usb_ep ? usb_ep->name : NULL);
+-00178                 return -EINVAL;
+-00179         }
+-00180 
+-00181         retval = dwc_otg_pcd_ep_disable(gadget_wrapper->pcd, usb_ep);
+-00182         if (retval) {
+-00183                 retval = -EINVAL;
+-00184         }
+-00185 
+-00186         return retval;
+-00187 }
+-00188 
+-00196 static struct usb_request *dwc_otg_pcd_alloc_request(struct usb_ep *ep,
+-00197                                                      gfp_t gfp_flags)
+-00198 {
+-00199         struct usb_request *usb_req;
+-00200 
+-00201         DWC_DEBUGPL(DBG_PCDV, "%s(%p,%d)\n", __func__, ep, gfp_flags);
+-00202         if (0 == ep) {
+-00203                 DWC_WARN("%s() %s\n", __func__, "Invalid EP!\n");
+-00204                 return 0;
+-00205         }
+-00206         usb_req = kmalloc(sizeof(*usb_req), gfp_flags);
+-00207         if (0 == usb_req) {
+-00208                 DWC_WARN("%s() %s\n", __func__, "request allocation failed!\n");
+-00209                 return 0;
+-00210         }
+-00211         memset(usb_req, 0, sizeof(*usb_req));
+-00212         usb_req->dma = DWC_INVALID_DMA_ADDR;
+-00213 
+-00214         return usb_req;
+-00215 }
+-00216 
+-00223 static void dwc_otg_pcd_free_request(struct usb_ep *ep, struct usb_request *req)
+-00224 {
+-00225         DWC_DEBUGPL(DBG_PCDV, "%s(%p,%p)\n", __func__, ep, req);
+-00226 
+-00227         if (0 == ep || 0 == req) {
+-00228                 DWC_WARN("%s() %s\n", __func__,
+-00229                          "Invalid ep or req argument!\n");
+-00230                 return;
+-00231         }
+-00232 
+-00233         kfree(req);
+-00234 }
+-00235 
+-00246 static void *dwc_otg_pcd_alloc_buffer(struct usb_ep *usb_ep, unsigned bytes,
+-00247                                       dma_addr_t * dma, gfp_t gfp_flags)
+-00248 {
+-00249         void *buf;
+-00250         dwc_otg_pcd_t *pcd = 0;
+-00251 
+-00252         pcd = gadget_wrapper->pcd;
+-00253 
+-00254         DWC_DEBUGPL(DBG_PCDV, "%s(%p,%d,%p,%0x)\n", __func__, usb_ep, bytes,
+-00255                     dma, gfp_flags);
+-00256 
+-00257         /* Check dword alignment */
+-00258         if ((bytes & 0x3UL) != 0) {
+-00259                 DWC_WARN("%s() Buffer size is not a multiple of"
+-00260                          "DWORD size (%d)", __func__, bytes);
+-00261         }
+-00262 
+-00263         buf = dma_alloc_coherent(NULL, bytes, dma, gfp_flags);
+-00264 
+-00265         /* Check dword alignment */
+-00266         if (((int)buf & 0x3UL) != 0) {
+-00267                 DWC_WARN("%s() Buffer is not DWORD aligned (%p)",
+-00268                          __func__, buf);
+-00269         }
+-00270 
+-00271         return buf;
+-00272 }
+-00273 
+-00282 static void dwc_otg_pcd_free_buffer(struct usb_ep *usb_ep, void *buf,
+-00283                                     dma_addr_t dma, unsigned bytes)
+-00284 {
+-00285         dwc_otg_pcd_t *pcd = 0;
+-00286 
+-00287         pcd = gadget_wrapper->pcd;
+-00288 
+-00289         DWC_DEBUGPL(DBG_PCDV, "%s(%p,%0x,%d)\n", __func__, buf, dma, bytes);
+-00290 
+-00291         dma_free_coherent(NULL, bytes, buf, dma);
+-00292 }
+-00293 
+-00308 static int ep_queue(struct usb_ep *usb_ep, struct usb_request *usb_req,
+-00309                     gfp_t gfp_flags)
+-00310 {
+-00311         dwc_otg_pcd_t *pcd;
+-00312         int retval;
+-00313 
+-00314         DWC_DEBUGPL(DBG_PCDV, "%s(%p,%p,%d)\n",
+-00315                     __func__, usb_ep, usb_req, gfp_flags);
+-00316 
+-00317         if (!usb_req || !usb_req->complete || !usb_req->buf) {
+-00318                 DWC_WARN("bad params\n");
+-00319                 return -EINVAL;
+-00320         }
+-00321 
+-00322         if (!usb_ep) {
+-00323                 DWC_WARN("bad ep\n");
+-00324                 return -EINVAL;
+-00325         }
+-00326 
+-00327         pcd = gadget_wrapper->pcd;
+-00328         if (!gadget_wrapper->driver ||
+-00329             gadget_wrapper->gadget.speed == USB_SPEED_UNKNOWN) {
+-00330                 DWC_DEBUGPL(DBG_PCDV, "gadget.speed=%d\n",
+-00331                             gadget_wrapper->gadget.speed);
+-00332                 DWC_WARN("bogus device state\n");
+-00333                 return -ESHUTDOWN;
+-00334         }
+-00335 
+-00336         DWC_DEBUGPL(DBG_PCD, "%s queue req %p, len %d buf %p\n",
+-00337                     usb_ep->name, usb_req, usb_req->length, usb_req->buf);
+-00338 
+-00339         usb_req->status = -EINPROGRESS;
+-00340         usb_req->actual = 0;
+-00341 
+-00342         retval = dwc_otg_pcd_ep_queue(pcd, usb_ep, usb_req->buf, usb_req->dma,
+-00343                                       usb_req->length, usb_req->zero, usb_req,
+-00344                                       gfp_flags == GFP_ATOMIC ? 1 : 0);
+-00345         if (retval) {
+-00346                 return -EINVAL;
+-00347         }
+-00348 
+-00349         return 0;
+-00350 }
+-00351 
+-00355 static int ep_dequeue(struct usb_ep *usb_ep, struct usb_request *usb_req)
+-00356 {
+-00357         DWC_DEBUGPL(DBG_PCDV, "%s(%p,%p)\n", __func__, usb_ep, usb_req);
+-00358 
+-00359         if (!usb_ep || !usb_req) {
+-00360                 DWC_WARN("bad argument\n");
+-00361                 return -EINVAL;
+-00362         }
+-00363         if (!gadget_wrapper->driver ||
+-00364             gadget_wrapper->gadget.speed == USB_SPEED_UNKNOWN) {
+-00365                 DWC_WARN("bogus device state\n");
+-00366                 return -ESHUTDOWN;
+-00367         }
+-00368         if (dwc_otg_pcd_ep_dequeue(gadget_wrapper->pcd, usb_ep, usb_req)) {
+-00369                 return -EINVAL;
+-00370         }
+-00371 
+-00372         return 0;
+-00373 }
+-00374 
+-00391 static int ep_halt(struct usb_ep *usb_ep, int value)
+-00392 {
+-00393         int retval = 0;
+-00394 
+-00395         DWC_DEBUGPL(DBG_PCD, "HALT %s %d\n", usb_ep->name, value);
+-00396 
+-00397         if (!usb_ep) {
+-00398                 DWC_WARN("bad ep\n");
+-00399                 return -EINVAL;
+-00400         }
+-00401 
+-00402         retval = dwc_otg_pcd_ep_halt(gadget_wrapper->pcd, usb_ep, value);
+-00403         if (retval == -DWC_E_AGAIN) {
+-00404                 return -EAGAIN;
+-00405         } else if (retval) {
+-00406                 retval = -EINVAL;
+-00407         }
+-00408 
+-00409         return retval;
+-00410 }
+-00411 
+-00412 #ifdef DWC_EN_ISOC
+-00413 
+-00422 static int iso_ep_start(struct usb_ep *usb_ep, struct usb_iso_request *req,
+-00423                         gfp_t gfp_flags)
+-00424 {
+-00425         int retval = 0;
+-00426 
+-00427         if (!req || !req->process_buffer || !req->buf0 || !req->buf1) {
+-00428                 DWC_WARN("bad params\n");
+-00429                 return -EINVAL;
+-00430         }
+-00431 
+-00432         if (!usb_ep) {
+-00433                 DWC_PRINTF("bad params\n");
+-00434                 return -EINVAL;
+-00435         }
+-00436 
+-00437         req->status = -EINPROGRESS;
+-00438 
+-00439         retval =
+-00440             dwc_otg_pcd_iso_ep_start(gadget_wrapper->pcd, usb_ep, req->buf0,
+-00441                                      req->buf1, req->dma0, req->dma1,
+-00442                                      req->sync_frame, req->data_pattern_frame,
+-00443                                      req->data_per_frame,
+-00444                                      req->flags & USB_REQ_ISO_ASAP ? -1 : req->
+-00445                                      start_frame, req->buf_proc_intrvl, req,
+-00446                                      gfp_flags == GFP_ATOMIC ? 1 : 0);
+-00447 
+-00448         if (retval) {
+-00449                 return -EINVAL;
+-00450         }
+-00451 
+-00452         return retval;
+-00453 }
+-00454 
+-00458 static int iso_ep_stop(struct usb_ep *usb_ep, struct usb_iso_request *req)
+-00459 {
+-00460         int retval = 0;
+-00461         if (!usb_ep) {
+-00462                 DWC_WARN("bad ep\n");
+-00463         }
+-00464 
+-00465         if (!gadget_wrapper->driver ||
+-00466             gadget_wrapper->gadget.speed == USB_SPEED_UNKNOWN) {
+-00467                 DWC_DEBUGPL(DBG_PCDV, "gadget.speed=%d\n",
+-00468                             gadget_wrapper->gadget.speed);
+-00469                 DWC_WARN("bogus device state\n");
+-00470         }
+-00471 
+-00472         dwc_otg_pcd_iso_ep_stop(gadget_wrapper->pcd, usb_ep, req);
+-00473         if (retval) {
+-00474                 retval = -EINVAL;
+-00475         }
+-00476 
+-00477         return retval;
+-00478 }
+-00479 
+-00480 static struct usb_iso_request *alloc_iso_request(struct usb_ep *ep,
+-00481                                                  int packets, gfp_t gfp_flags)
+-00482 {
+-00483         struct usb_iso_request *pReq = NULL;
+-00484         uint32_t req_size;
+-00485 
+-00486         req_size = sizeof(struct usb_iso_request);
+-00487         req_size +=
+-00488             (2 * packets * (sizeof(struct usb_gadget_iso_packet_descriptor)));
+-00489 
+-00490         pReq = kmalloc(req_size, gfp_flags);
+-00491         if (!pReq) {
+-00492                 DWC_WARN("Can't allocate Iso Request\n");
+-00493                 return 0;
+-00494         }
+-00495         pReq->iso_packet_desc0 = (void *)(pReq + 1);
+-00496 
+-00497         pReq->iso_packet_desc1 = pReq->iso_packet_desc0 + packets;
+-00498 
+-00499         return pReq;
+-00500 }
+-00501 
+-00502 static void free_iso_request(struct usb_ep *ep, struct usb_iso_request *req)
+-00503 {
+-00504         kfree(req);
+-00505 }
+-00506 
+-00507 static struct usb_isoc_ep_ops dwc_otg_pcd_ep_ops = {
+-00508         .ep_ops = {
+-00509                    .enable = ep_enable,
+-00510                    .disable = ep_disable,
+-00511 
+-00512                    .alloc_request = dwc_otg_pcd_alloc_request,
+-00513                    .free_request = dwc_otg_pcd_free_request,
+-00514 
+-00515                    .alloc_buffer = dwc_otg_pcd_alloc_buffer,
+-00516                    .free_buffer = dwc_otg_pcd_free_buffer,
+-00517 
+-00518                    .queue = ep_queue,
+-00519                    .dequeue = ep_dequeue,
+-00520 
+-00521                    .set_halt = ep_halt,
+-00522                    .fifo_status = 0,
+-00523                    .fifo_flush = 0,
+-00524                    },
+-00525         .iso_ep_start = iso_ep_start,
+-00526         .iso_ep_stop = iso_ep_stop,
+-00527         .alloc_iso_request = alloc_iso_request,
+-00528         .free_iso_request = free_iso_request,
+-00529 };
+-00530 
+-00531 #else
+-00532 
+-00533 static struct usb_ep_ops dwc_otg_pcd_ep_ops = {
+-00534         .enable = ep_enable,
+-00535         .disable = ep_disable,
+-00536 
+-00537         .alloc_request = dwc_otg_pcd_alloc_request,
+-00538         .free_request = dwc_otg_pcd_free_request,
+-00539 
+-00540         .alloc_buffer = dwc_otg_pcd_alloc_buffer,
+-00541         .free_buffer = dwc_otg_pcd_free_buffer,
+-00542 
+-00543         .queue = ep_queue,
+-00544         .dequeue = ep_dequeue,
+-00545 
+-00546         .set_halt = ep_halt,
+-00547         .fifo_status = 0,
+-00548         .fifo_flush = 0,
+-00549 
+-00550 };
+-00551 
+-00552 #endif                          /* _EN_ISOC_ */
+-00553 /*      Gadget Operations */
+-00572 static int get_frame_number(struct usb_gadget *gadget)
+-00573 {
+-00574         struct gadget_wrapper *d;
+-00575 
+-00576         DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, gadget);
+-00577 
+-00578         if (gadget == 0) {
+-00579                 return -ENODEV;
+-00580         }
+-00581 
+-00582         d = container_of(gadget, struct gadget_wrapper, gadget);
+-00583         return dwc_otg_pcd_get_frame_number(d->pcd);
+-00584 }
+-00585 
+-00586 #ifdef CONFIG_USB_DWC_OTG_LPM
+-00587 static int test_lpm_enabled(struct usb_gadget *gadget)
+-00588 {
+-00589         struct gadget_wrapper *d;
+-00590 
+-00591         d = container_of(gadget, struct gadget_wrapper, gadget);
+-00592 
+-00593         return dwc_otg_pcd_is_lpm_enabled(d->pcd);
+-00594 }
+-00595 #endif
+-00596 
+-00603 static int wakeup(struct usb_gadget *gadget)
+-00604 {
+-00605         struct gadget_wrapper *d;
+-00606 
+-00607         DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, gadget);
+-00608 
+-00609         if (gadget == 0) {
+-00610                 return -ENODEV;
+-00611         } else {
+-00612                 d = container_of(gadget, struct gadget_wrapper, gadget);
+-00613         }
+-00614         dwc_otg_pcd_wakeup(d->pcd);
+-00615         return 0;
+-00616 }
+-00617 
+-00618 static const struct usb_gadget_ops dwc_otg_pcd_ops = {
+-00619         .get_frame = get_frame_number,
+-00620         .wakeup = wakeup,
+-00621 #ifdef CONFIG_USB_DWC_OTG_LPM
+-00622         .lpm_support = test_lpm_enabled,
+-00623 #endif
+-00624         // current versions must always be self-powered
+-00625 };
+-00626 
+-00627 static int _setup(dwc_otg_pcd_t * pcd, uint8_t * bytes)
+-00628 {
+-00629         int retval = -DWC_E_NOT_SUPPORTED;
+-00630         if (gadget_wrapper->driver && gadget_wrapper->driver->setup) {
+-00631                 retval = gadget_wrapper->driver->setup(&gadget_wrapper->gadget,
+-00632                                                        (struct usb_ctrlrequest
+-00633                                                         *)bytes);
+-00634         }
+-00635 
+-00636         if (retval == -ENOTSUPP) {
+-00637                 retval = -DWC_E_NOT_SUPPORTED;
+-00638         } else if (retval < 0) {
+-00639                 retval = -DWC_E_INVALID;
+-00640         }
+-00641 
+-00642         return retval;
+-00643 }
+-00644 
+-00645 #ifdef DWC_EN_ISOC
+-00646 static int _isoc_complete(dwc_otg_pcd_t * pcd, void *ep_handle,
+-00647                           void *req_handle, int proc_buf_num)
+-00648 {
+-00649         int i, packet_count;
+-00650         struct usb_gadget_iso_packet_descriptor *iso_packet = 0;
+-00651         struct usb_iso_request *iso_req = req_handle;
+-00652 
+-00653         if (proc_buf_num) {
+-00654                 iso_packet = iso_req->iso_packet_desc1;
+-00655         } else {
+-00656                 iso_packet = iso_req->iso_packet_desc0;
+-00657         }
+-00658         packet_count =
+-00659             dwc_otg_pcd_get_iso_packet_count(pcd, ep_handle, req_handle);
+-00660         for (i = 0; i < packet_count; ++i) {
+-00661                 int status;
+-00662                 int actual;
+-00663                 int offset;
+-00664                 dwc_otg_pcd_get_iso_packet_params(pcd, ep_handle, req_handle,
+-00665                                                   i, &status, &actual, &offset);
+-00666                 switch (status) {
+-00667                 case -DWC_E_NO_DATA:
+-00668                         status = -ENODATA;
+-00669                         break;
+-00670                 default:
+-00671                         if (status) {
+-00672                                 DWC_PRINTF("unknown status in isoc packet\n");
+-00673                         }
+-00674 
+-00675                 }
+-00676                 iso_packet[i].status = status;
+-00677                 iso_packet[i].offset = offset;
+-00678                 iso_packet[i].actual_length = actual;
+-00679         }
+-00680 
+-00681         iso_req->status = 0;
+-00682         iso_req->process_buffer(ep_handle, iso_req);
+-00683 
+-00684         return 0;
+-00685 }
+-00686 #endif                          /* DWC_EN_ISOC */
+-00687 
+-00688 static int _complete(dwc_otg_pcd_t * pcd, void *ep_handle,
+-00689                      void *req_handle, int32_t status, uint32_t actual)
+-00690 {
+-00691         struct usb_request *req = (struct usb_request *)req_handle;
+-00692 
+-00693         if (req && req->complete) {
+-00694                 switch (status) {
+-00695                 case -DWC_E_SHUTDOWN:
+-00696                         req->status = -ESHUTDOWN;
+-00697                         break;
+-00698                 case -DWC_E_RESTART:
+-00699                         req->status = -ECONNRESET;
+-00700                         break;
+-00701                 case -DWC_E_INVALID:
+-00702                         req->status = -EINVAL;
+-00703                         break;
+-00704                 case -DWC_E_TIMEOUT:
+-00705                         req->status = -ETIMEDOUT;
+-00706                         break;
+-00707                 default:
+-00708                         req->status = status;
+-00709 
+-00710                 }
+-00711                 req->actual = actual;
+-00712                 req->complete(ep_handle, req);
+-00713         }
+-00714 
+-00715         return 0;
+-00716 }
+-00717 
+-00718 static int _connect(dwc_otg_pcd_t * pcd, int speed)
+-00719 {
+-00720         gadget_wrapper->gadget.speed = speed;
+-00721         return 0;
+-00722 }
+-00723 
+-00724 static int _disconnect(dwc_otg_pcd_t * pcd)
+-00725 {
+-00726         if (gadget_wrapper->driver && gadget_wrapper->driver->disconnect) {
+-00727                 gadget_wrapper->driver->disconnect(&gadget_wrapper->gadget);
+-00728         }
+-00729         return 0;
+-00730 }
+-00731 
+-00732 static int _resume(dwc_otg_pcd_t * pcd)
+-00733 {
+-00734         if (gadget_wrapper->driver && gadget_wrapper->driver->resume) {
+-00735                 gadget_wrapper->driver->resume(&gadget_wrapper->gadget);
+-00736         }
+-00737 
+-00738         return 0;
+-00739 }
+-00740 
+-00741 static int _suspend(dwc_otg_pcd_t * pcd)
+-00742 {
+-00743         if (gadget_wrapper->driver && gadget_wrapper->driver->suspend) {
+-00744                 gadget_wrapper->driver->suspend(&gadget_wrapper->gadget);
+-00745         }
+-00746         return 0;
+-00747 }
+-00748 
+-00752 static int _hnp_changed(dwc_otg_pcd_t * pcd)
+-00753 {
+-00754 
+-00755         if (!gadget_wrapper->gadget.is_otg)
+-00756                 return 0;
+-00757 
+-00758         gadget_wrapper->gadget.b_hnp_enable = get_b_hnp_enable(pcd);
+-00759         gadget_wrapper->gadget.a_hnp_support = get_a_hnp_support(pcd);
+-00760         gadget_wrapper->gadget.a_alt_hnp_support = get_a_alt_hnp_support(pcd);
+-00761         return 0;
+-00762 }
+-00763 
+-00764 static int _reset(dwc_otg_pcd_t * pcd)
+-00765 {
+-00766         return 0;
+-00767 }
+-00768 
+-00769 #ifdef DWC_UTE_CFI
+-00770 static int _cfi_setup(dwc_otg_pcd_t * pcd, void *cfi_req)
+-00771 {
+-00772         int retval = -DWC_E_INVALID;
+-00773         if (gadget_wrapper->driver->cfi_feature_setup) {
+-00774                 retval =
+-00775                     gadget_wrapper->driver->cfi_feature_setup(&gadget_wrapper->
+-00776                                                               gadget,
+-00777                                                               (struct
+-00778                                                                cfi_usb_ctrlrequest
+-00779                                                                *)cfi_req);
+-00780         }
+-00781 
+-00782         return retval;
+-00783 }
+-00784 #endif
+-00785 
+-00786 static const struct dwc_otg_pcd_function_ops fops = {
+-00787         .complete = _complete,
+-00788 #ifdef DWC_EN_ISOC
+-00789         .isoc_complete = _isoc_complete,
+-00790 #endif
+-00791         .setup = _setup,
+-00792         .disconnect = _disconnect,
+-00793         .connect = _connect,
+-00794         .resume = _resume,
+-00795         .suspend = _suspend,
+-00796         .hnp_changed = _hnp_changed,
+-00797         .reset = _reset,
+-00798 #ifdef DWC_UTE_CFI
+-00799         .cfi_setup = _cfi_setup,
+-00800 #endif
+-00801 };
+-00802 
+-00806 static irqreturn_t dwc_otg_pcd_irq(int irq, void *dev)
+-00807 {
+-00808         dwc_otg_pcd_t *pcd = dev;
+-00809         int32_t retval = IRQ_NONE;
+-00810 
+-00811         retval = dwc_otg_pcd_handle_intr(pcd);
+-00812         if (retval != 0) {
+-00813                 S3C2410X_CLEAR_EINTPEND();
+-00814         }
+-00815         return IRQ_RETVAL(retval);
+-00816 }
+-00817 
+-00824 void gadget_add_eps(struct gadget_wrapper *d)
+-00825 {
+-00826         static const char *names[] = {
+-00827 
+-00828                 "ep0",
+-00829                 "ep1in",
+-00830                 "ep2in",
+-00831                 "ep3in",
+-00832                 "ep4in",
+-00833                 "ep5in",
+-00834                 "ep6in",
+-00835                 "ep7in",
+-00836                 "ep8in",
+-00837                 "ep9in",
+-00838                 "ep10in",
+-00839                 "ep11in",
+-00840                 "ep12in",
+-00841                 "ep13in",
+-00842                 "ep14in",
+-00843                 "ep15in",
+-00844                 "ep1out",
+-00845                 "ep2out",
+-00846                 "ep3out",
+-00847                 "ep4out",
+-00848                 "ep5out",
+-00849                 "ep6out",
+-00850                 "ep7out",
+-00851                 "ep8out",
+-00852                 "ep9out",
+-00853                 "ep10out",
+-00854                 "ep11out",
+-00855                 "ep12out",
+-00856                 "ep13out",
+-00857                 "ep14out",
+-00858                 "ep15out"
+-00859         };
+-00860 
+-00861         int i;
+-00862         struct usb_ep *ep;
+-00863 
+-00864         DWC_DEBUGPL(DBG_PCDV, "%s\n", __func__);
+-00865 
+-00866         INIT_LIST_HEAD(&d->gadget.ep_list);
+-00867         d->gadget.ep0 = &d->ep0;
+-00868         d->gadget.speed = USB_SPEED_UNKNOWN;
+-00869 
+-00870         INIT_LIST_HEAD(&d->gadget.ep0->ep_list);
+-00871 
+-00875         ep = &d->ep0;
+-00876 
+-00877         /* Init the usb_ep structure. */
+-00878         ep->name = names[0];
+-00879         ep->ops = (struct usb_ep_ops *)&dwc_otg_pcd_ep_ops;
+-00880 
+-00885         ep->maxpacket = MAX_PACKET_SIZE;
+-00886         dwc_otg_pcd_ep_enable(d->pcd, NULL, ep);
+-00887 
+-00888         list_add_tail(&ep->ep_list, &d->gadget.ep_list);
+-00889 
+-00894         for (i = 0; i < 15; i++) {
+-00895                 ep = &d->in_ep[i];
+-00896 
+-00897                 /* Init the usb_ep structure. */
+-00898                 ep->name = names[i + 1];
+-00899                 ep->ops = (struct usb_ep_ops *)&dwc_otg_pcd_ep_ops;
+-00900 
+-00905                 ep->maxpacket = MAX_PACKET_SIZE;
+-00906                 list_add_tail(&ep->ep_list, &d->gadget.ep_list);
+-00907         }
+-00908 
+-00909         for (i = 0; i < 15; i++) {
+-00910                 ep = &d->out_ep[i];
+-00911 
+-00912                 /* Init the usb_ep structure. */
+-00913                 ep->name = names[15 + i + 1];
+-00914                 ep->ops = (struct usb_ep_ops *)&dwc_otg_pcd_ep_ops;
+-00915 
+-00920                 ep->maxpacket = MAX_PACKET_SIZE;
+-00921 
+-00922                 list_add_tail(&ep->ep_list, &d->gadget.ep_list);
+-00923         }
+-00924 
+-00925         /* remove ep0 from the list.  There is a ep0 pointer. */
+-00926         list_del_init(&d->ep0.ep_list);
+-00927 
+-00928         d->ep0.maxpacket = MAX_EP0_SIZE;
+-00929 }
+-00930 
+-00937 static void dwc_otg_pcd_gadget_release(struct device *dev)
+-00938 {
+-00939         DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, dev);
+-00940 }
+-00941 
+-00942 static struct gadget_wrapper *alloc_wrapper(
+-00943 #ifdef LM_INTERFACE
+-00944         struct lm_device *_dev
+-00945 #elif  PCI_INTERFACE
+-00946         struct pci_dev *_dev
+-00947 #endif
+-00948         )
+-00949 {
+-00950         static char pcd_name[] = "dwc_otg_pcd";
+-00951 #ifdef LM_INTERFACE
+-00952         dwc_otg_device_t *otg_dev = lm_get_drvdata(_dev);
+-00953 #elif PCI_INTERFACE
+-00954         dwc_otg_device_t *otg_dev = pci_get_drvdata(_dev);
+-00955 #endif
+-00956 
+-00957         struct gadget_wrapper *d;
+-00958         int retval;
+-00959 
+-00960         d = dwc_alloc(sizeof(*d));
+-00961         if (d == NULL) {
+-00962                 return NULL;
+-00963         }
+-00964 
+-00965         memset(d, 0, sizeof(*d));
+-00966 
+-00967         d->gadget.name = pcd_name;
+-00968         d->pcd = otg_dev->pcd;
+-00969         strcpy(d->gadget.dev.bus_id, "gadget");
+-00970 
+-00971         d->gadget.dev.parent = &_dev->dev;
+-00972         d->gadget.dev.release = dwc_otg_pcd_gadget_release;
+-00973         d->gadget.ops = &dwc_otg_pcd_ops;
+-00974         d->gadget.is_dualspeed = dwc_otg_pcd_is_dualspeed(otg_dev->pcd);
+-00975         d->gadget.is_otg = dwc_otg_pcd_is_otg(otg_dev->pcd);
+-00976 
+-00977         d->driver = 0;
+-00978         /* Register the gadget device */
+-00979         retval = device_register(&d->gadget.dev);
+-00980         if (retval != 0) {
+-00981                 DWC_ERROR("device_register failed\n");
+-00982                 dwc_free(d);
+-00983                 return NULL;
+-00984         }
+-00985 
+-00986         return d;
+-00987 }
+-00988 
+-00989 static void free_wrapper(struct gadget_wrapper *d)
+-00990 {
+-00991         if (d->driver) {
+-00992                 /* should have been done already by driver model core */
+-00993                 DWC_WARN("driver '%s' is still registered\n",
+-00994                          d->driver->driver.name);
+-00995                 usb_gadget_unregister_driver(d->driver);
+-00996         }
+-00997 
+-00998         device_unregister(&d->gadget.dev);
+-00999         dwc_free(d);
+-01000 }
+-01001 
+-01006 int pcd_init(
+-01007 #ifdef LM_INTERFACE
+-01008         struct lm_device *_dev
+-01009 #elif  PCI_INTERFACE
+-01010         struct pci_dev *_dev
+-01011 #endif
+-01012         )
+-01013 
+-01014 {
+-01015 #ifdef LM_INTERFACE
+-01016         dwc_otg_device_t *otg_dev = lm_get_drvdata(_dev);
+-01017 #elif  PCI_INTERFACE
+-01018         dwc_otg_device_t *otg_dev = pci_get_drvdata(_dev);
+-01019 #endif
+-01020 
+-01021         int retval = 0;
+-01022 
+-01023         DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, _dev);
+-01024 
+-01025         otg_dev->pcd = dwc_otg_pcd_init(otg_dev->core_if);
+-01026 
+-01027         if (!otg_dev->pcd) {
+-01028                 DWC_ERROR("dwc_otg_pcd_init failed\n");
+-01029                 return -ENOMEM;
+-01030         }
+-01031 
+-01032         gadget_wrapper = alloc_wrapper(_dev);
+-01033 
+-01034         /*
+-01035          * Initialize EP structures
+-01036          */
+-01037         gadget_add_eps(gadget_wrapper);
+-01038 
+-01039         /*
+-01040          * Setup interupt handler
+-01041          */
+-01042         DWC_DEBUGPL(DBG_ANY, "registering handler for irq%d\n", _dev->irq);
+-01043         retval = request_irq(_dev->irq, dwc_otg_pcd_irq,
+-01044                              SA_SHIRQ, gadget_wrapper->gadget.name,
+-01045                              otg_dev->pcd);
+-01046         if (retval != 0) {
+-01047                 DWC_ERROR("request of irq%d failed\n", _dev->irq);
+-01048                 free_wrapper(gadget_wrapper);
+-01049                 return -EBUSY;
+-01050         }
+-01051 
+-01052         dwc_otg_pcd_start(gadget_wrapper->pcd, &fops);
+-01053 
+-01054         return retval;
+-01055 }
+-01056 
+-01060 void pcd_remove(
+-01061 #ifdef LM_INTERFACE
+-01062         struct lm_device *_dev
+-01063 #elif  PCI_INTERFACE
+-01064         struct pci_dev *_dev
+-01065 #endif
+-01066         )
+-01067 {
+-01068 #ifdef LM_INTERFACE
+-01069         dwc_otg_device_t *otg_dev = lm_get_drvdata(_dev);
+-01070 #elif  PCI_INTERFACE
+-01071         dwc_otg_device_t *otg_dev = pci_get_drvdata(_dev);
+-01072 #endif
+-01073         dwc_otg_pcd_t *pcd = otg_dev->pcd;
+-01074 
+-01075         DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, _dev);
+-01076 
+-01077         /*
+-01078          * Free the IRQ
+-01079          */
+-01080         free_irq(_dev->irq, pcd);
+-01081         dwc_otg_pcd_remove(otg_dev->pcd);
+-01082         free_wrapper(gadget_wrapper);
+-01083         otg_dev->pcd = 0;
+-01084 }
+-01085 
+-01096 int usb_gadget_register_driver(struct usb_gadget_driver *driver)
+-01097 {
+-01098         int retval;
+-01099 
+-01100         DWC_DEBUGPL(DBG_PCD, "registering gadget driver '%s'\n",
+-01101                     driver->driver.name);
+-01102 
+-01103         if (!driver || driver->speed == USB_SPEED_UNKNOWN ||
+-01104             !driver->bind ||
+-01105             !driver->unbind || !driver->disconnect || !driver->setup) {
+-01106                 DWC_DEBUGPL(DBG_PCDV, "EINVAL\n");
+-01107                 return -EINVAL;
+-01108         }
+-01109         if (gadget_wrapper == 0) {
+-01110                 DWC_DEBUGPL(DBG_PCDV, "ENODEV\n");
+-01111                 return -ENODEV;
+-01112         }
+-01113         if (gadget_wrapper->driver != 0) {
+-01114                 DWC_DEBUGPL(DBG_PCDV, "EBUSY (%p)\n", gadget_wrapper->driver);
+-01115                 return -EBUSY;
+-01116         }
+-01117 
+-01118         /* hook up the driver */
+-01119         gadget_wrapper->driver = driver;
+-01120         gadget_wrapper->gadget.dev.driver = &driver->driver;
+-01121 
+-01122         DWC_DEBUGPL(DBG_PCD, "bind to driver %s\n", driver->driver.name);
+-01123         retval = driver->bind(&gadget_wrapper->gadget);
+-01124         if (retval) {
+-01125                 DWC_ERROR("bind to driver %s --> error %d\n",
+-01126                           driver->driver.name, retval);
+-01127                 gadget_wrapper->driver = 0;
+-01128                 gadget_wrapper->gadget.dev.driver = 0;
+-01129                 return retval;
+-01130         }
+-01131         DWC_DEBUGPL(DBG_ANY, "registered gadget driver '%s'\n",
+-01132                     driver->driver.name);
+-01133         return 0;
+-01134 }
+-01135 
+-01136 EXPORT_SYMBOL(usb_gadget_register_driver);
+-01137 
+-01143 int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
+-01144 {
+-01145         //DWC_DEBUGPL(DBG_PCDV,"%s(%p)\n", __func__, _driver);
+-01146 
+-01147         if (gadget_wrapper == 0) {
+-01148                 DWC_DEBUGPL(DBG_ANY, "%s Return(%d): s_pcd==0\n", __func__,
+-01149                             -ENODEV);
+-01150                 return -ENODEV;
+-01151         }
+-01152         if (driver == 0 || driver != gadget_wrapper->driver) {
+-01153                 DWC_DEBUGPL(DBG_ANY, "%s Return(%d): driver?\n", __func__,
+-01154                             -EINVAL);
+-01155                 return -EINVAL;
+-01156         }
+-01157 
+-01158         driver->unbind(&gadget_wrapper->gadget);
+-01159         gadget_wrapper->driver = 0;
+-01160 
+-01161         DWC_DEBUGPL(DBG_ANY, "unregistered driver '%s'\n", driver->driver.name);
+-01162         return 0;
+-01163 }
+-01164 
+-01165 EXPORT_SYMBOL(usb_gadget_unregister_driver);
+-01166 
+-01167 #endif                          /* DWC_HOST_ONLY */
+-
      Generated on Tue May 5 02:22:48 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++
      Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
      ++

      dwc_otg_pcd_linux.c

      Go to the documentation of this file.
      00001  /* ==========================================================================
++00002   * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_pcd_linux.c $
++00003   * $Revision: #19 $
++00004   * $Date: 2011/10/26 $
++00005   * $Change: 1873028 $
++00006   *
++00007   * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
++00008   * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
++00009   * otherwise expressly agreed to in writing between Synopsys and you.
++00010   *
++00011   * The Software IS NOT an item of Licensed Software or Licensed Product under
++00012   * any End User Software License Agreement or Agreement for Licensed Product
++00013   * with Synopsys or any supplement thereto. You are permitted to use and
++00014   * redistribute this Software in source and binary forms, with or without
++00015   * modification, provided that redistributions of source code must retain this
++00016   * notice. You may not view, use, disclose, copy or distribute this file or
++00017   * any information contained herein except pursuant to this license grant from
++00018   * Synopsys. If you do not agree with this notice, including the disclaimer
++00019   * below, then you are not authorized to use the Software.
++00020   *
++00021   * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
++00022   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++00023   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++00024   * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
++00025   * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++00026   * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
++00027   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
++00028   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
++00029   * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
++00030   * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
++00031   * DAMAGE.
++00032   * ========================================================================== */
++00033 #ifndef DWC_HOST_ONLY
++00034 
++00056 #include "dwc_otg_os_dep.h"
++00057 #include "dwc_otg_pcd_if.h"
++00058 #include "dwc_otg_pcd.h"
++00059 #include "dwc_otg_driver.h"
++00060 #include "dwc_otg_dbg.h"
++00061 
++00062 static struct gadget_wrapper {
++00063         dwc_otg_pcd_t *pcd;
++00064 
++00065         struct usb_gadget gadget;
++00066         struct usb_gadget_driver *driver;
++00067 
++00068         struct usb_ep ep0;
++00069         struct usb_ep in_ep[16];
++00070         struct usb_ep out_ep[16];
++00071 
++00072 } *gadget_wrapper;
++00073 
++00074 /* Display the contents of the buffer */
++00075 extern void dump_msg(const u8 * buf, unsigned int length);
++00080 static struct dwc_otg_pcd_ep *ep_from_handle(dwc_otg_pcd_t * pcd, void *handle)
++00081 {
++00082         int i;
++00083         if (pcd->ep0.priv == handle) {
++00084                 return &pcd->ep0;
++00085         }
++00086 
++00087         for (i = 0; i < MAX_EPS_CHANNELS - 1; i++) {
++00088                 if (pcd->in_ep[i].priv == handle)
++00089                         return &pcd->in_ep[i];
++00090                 if (pcd->out_ep[i].priv == handle)
++00091                         return &pcd->out_ep[i];
++00092         }
++00093 
++00094         return NULL;
++00095 }
++00096 
++00097 /* USB Endpoint Operations */
++00098 /*
++00099  * The following sections briefly describe the behavior of the Gadget
++00100  * API endpoint operations implemented in the DWC_otg driver
++00101  * software. Detailed descriptions of the generic behavior of each of
++00102  * these functions can be found in the Linux header file
++00103  * include/linux/usb_gadget.h.
++00104  *
++00105  * The Gadget API provides wrapper functions for each of the function
++00106  * pointers defined in usb_ep_ops. The Gadget Driver calls the wrapper
++00107  * function, which then calls the underlying PCD function. The
++00108  * following sections are named according to the wrapper
++00109  * functions. Within each section, the corresponding DWC_otg PCD
++00110  * function name is specified.
++00111  *
++00112  */
++00113 
++00121 static int ep_enable(struct usb_ep *usb_ep,
++00122                      const struct usb_endpoint_descriptor *ep_desc)
++00123 {
++00124         int retval;
++00125 
++00126         DWC_DEBUGPL(DBG_PCDV, "%s(%p,%p)\n", __func__, usb_ep, ep_desc);
++00127 
++00128         if (!usb_ep || !ep_desc || ep_desc->bDescriptorType != USB_DT_ENDPOINT) {
++00129                 DWC_WARN("%s, bad ep or descriptor\n", __func__);
++00130                 return -EINVAL;
++00131         }
++00132         if (usb_ep == &gadget_wrapper->ep0) {
++00133                 DWC_WARN("%s, bad ep(0)\n", __func__);
++00134                 return -EINVAL;
++00135         }
++00136 
++00137         /* Check FIFO size? */
++00138         if (!ep_desc->wMaxPacketSize) {
++00139                 DWC_WARN("%s, bad %s maxpacket\n", __func__, usb_ep->name);
++00140                 return -ERANGE;
++00141         }
++00142 
++00143         if (!gadget_wrapper->driver ||
++00144             gadget_wrapper->gadget.speed == USB_SPEED_UNKNOWN) {
++00145                 DWC_WARN("%s, bogus device state\n", __func__);
++00146                 return -ESHUTDOWN;
++00147         }
++00148 
++00149         /* Delete after check - MAS */
++00150 #if 0
++00151         nat = (uint32_t) ep_desc->wMaxPacketSize;
++00152         printk(KERN_ALERT "%s: nat (before) =%d\n", __func__, nat);
++00153         nat = (nat >> 11) & 0x03;
++00154         printk(KERN_ALERT "%s: nat (after) =%d\n", __func__, nat);
++00155 #endif
++00156         retval = dwc_otg_pcd_ep_enable(gadget_wrapper->pcd,
++00157                                        (const uint8_t *)ep_desc,
++00158                                        (void *)usb_ep);
++00159         if (retval) {
++00160                 DWC_WARN("dwc_otg_pcd_ep_enable failed\n");
++00161                 return -EINVAL;
++00162         }
++00163 
++00164         usb_ep->maxpacket = le16_to_cpu(ep_desc->wMaxPacketSize);
++00165 
++00166         return 0;
++00167 }
++00168 
++00177 static int ep_disable(struct usb_ep *usb_ep)
++00178 {
++00179         int retval;
++00180 
++00181         DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, usb_ep);
++00182         if (!usb_ep) {
++00183                 DWC_DEBUGPL(DBG_PCD, "%s, %s not enabled\n", __func__,
++00184                             usb_ep ? usb_ep->name : NULL);
++00185                 return -EINVAL;
++00186         }
++00187 
++00188         retval = dwc_otg_pcd_ep_disable(gadget_wrapper->pcd, usb_ep);
++00189         if (retval) {
++00190                 retval = -EINVAL;
++00191         }
++00192 
++00193         return retval;
++00194 }
++00195 
++00203 static struct usb_request *dwc_otg_pcd_alloc_request(struct usb_ep *ep,
++00204                                                      gfp_t gfp_flags)
++00205 {
++00206         struct usb_request *usb_req;
++00207 
++00208         DWC_DEBUGPL(DBG_PCDV, "%s(%p,%d)\n", __func__, ep, gfp_flags);
++00209         if (0 == ep) {
++00210                 DWC_WARN("%s() %s\n", __func__, "Invalid EP!\n");
++00211                 return 0;
++00212         }
++00213         usb_req = kmalloc(sizeof(*usb_req), gfp_flags);
++00214         if (0 == usb_req) {
++00215                 DWC_WARN("%s() %s\n", __func__, "request allocation failed!\n");
++00216                 return 0;
++00217         }
++00218         memset(usb_req, 0, sizeof(*usb_req));
++00219         usb_req->dma = DWC_DMA_ADDR_INVALID;
++00220 
++00221         return usb_req;
++00222 }
++00223 
++00230 static void dwc_otg_pcd_free_request(struct usb_ep *ep, struct usb_request *req)
++00231 {
++00232         DWC_DEBUGPL(DBG_PCDV, "%s(%p,%p)\n", __func__, ep, req);
++00233 
++00234         if (0 == ep || 0 == req) {
++00235                 DWC_WARN("%s() %s\n", __func__,
++00236                          "Invalid ep or req argument!\n");
++00237                 return;
++00238         }
++00239 
++00240         kfree(req);
++00241 }
++00242 
++00243 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28)
++00244 
++00254 static void *dwc_otg_pcd_alloc_buffer(struct usb_ep *usb_ep, unsigned bytes,
++00255                                       dma_addr_t * dma, gfp_t gfp_flags)
++00256 {
++00257         void *buf;
++00258         dwc_otg_pcd_t *pcd = 0;
++00259 
++00260         pcd = gadget_wrapper->pcd;
++00261 
++00262         DWC_DEBUGPL(DBG_PCDV, "%s(%p,%d,%p,%0x)\n", __func__, usb_ep, bytes,
++00263                     dma, gfp_flags);
++00264 
++00265         /* Check dword alignment */
++00266         if ((bytes & 0x3UL) != 0) {
++00267                 DWC_WARN("%s() Buffer size is not a multiple of"
++00268                          "DWORD size (%d)", __func__, bytes);
++00269         }
++00270 
++00271         buf = dma_alloc_coherent(NULL, bytes, dma, gfp_flags);
++00272 
++00273         /* Check dword alignment */
++00274         if (((int)buf & 0x3UL) != 0) {
++00275                 DWC_WARN("%s() Buffer is not DWORD aligned (%p)",
++00276                          __func__, buf);
++00277         }
++00278 
++00279         return buf;
++00280 }
++00281 
++00290 static void dwc_otg_pcd_free_buffer(struct usb_ep *usb_ep, void *buf,
++00291                                     dma_addr_t dma, unsigned bytes)
++00292 {
++00293         dwc_otg_pcd_t *pcd = 0;
++00294 
++00295         pcd = gadget_wrapper->pcd;
++00296 
++00297         DWC_DEBUGPL(DBG_PCDV, "%s(%p,%0x,%d)\n", __func__, buf, dma, bytes);
++00298 
++00299         dma_free_coherent(NULL, bytes, buf, dma);
++00300 }
++00301 #endif
++00302 
++00317 static int ep_queue(struct usb_ep *usb_ep, struct usb_request *usb_req,
++00318                     gfp_t gfp_flags)
++00319 {
++00320         dwc_otg_pcd_t *pcd;
++00321         struct dwc_otg_pcd_ep *ep = NULL;
++00322         int retval = 0, is_isoc_ep = 0;
++00323         dma_addr_t dma_addr = DWC_DMA_ADDR_INVALID;
++00324 
++00325         DWC_DEBUGPL(DBG_PCDV, "%s(%p,%p,%d)\n",
++00326                     __func__, usb_ep, usb_req, gfp_flags);
++00327 
++00328         if (!usb_req || !usb_req->complete || !usb_req->buf) {
++00329                 DWC_WARN("bad params\n");
++00330                 return -EINVAL;
++00331         }
++00332 
++00333         if (!usb_ep) {
++00334                 DWC_WARN("bad ep\n");
++00335                 return -EINVAL;
++00336         }
++00337 
++00338         pcd = gadget_wrapper->pcd;
++00339         if (!gadget_wrapper->driver ||
++00340             gadget_wrapper->gadget.speed == USB_SPEED_UNKNOWN) {
++00341                 DWC_DEBUGPL(DBG_PCDV, "gadget.speed=%d\n",
++00342                             gadget_wrapper->gadget.speed);
++00343                 DWC_WARN("bogus device state\n");
++00344                 return -ESHUTDOWN;
++00345         }
++00346 
++00347         DWC_DEBUGPL(DBG_PCD, "%s queue req %p, len %d buf %p\n",
++00348                     usb_ep->name, usb_req, usb_req->length, usb_req->buf);
++00349 
++00350         usb_req->status = -EINPROGRESS;
++00351         usb_req->actual = 0;
++00352 
++00353         ep = ep_from_handle(pcd, usb_ep);
++00354         if (ep == NULL)
++00355                 is_isoc_ep = 0;
++00356         else
++00357                 is_isoc_ep = (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) ? 1 : 0;
++00358 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28)
++00359         dma_addr = usb_req->dma;
++00360 #else
++00361         if (GET_CORE_IF(pcd)->dma_enable) {
++00362                 struct pci_dev *dev = gadget_wrapper->pcd->otg_dev->os_dep.pcidev;
++00363                 if (usb_req->length != 0 && usb_req->dma == DWC_DMA_ADDR_INVALID) {
++00364                         dma_addr = pci_map_single(dev, usb_req->buf, usb_req->length, 
++00365                                         ep->dwc_ep.is_in ? PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
++00366                 }
++00367         }
++00368 #endif
++00369 
++00370 #ifdef DWC_UTE_PER_IO
++00371         if (is_isoc_ep == 1) {
++00372                 retval = dwc_otg_pcd_xiso_ep_queue(pcd, usb_ep, usb_req->buf, dma_addr,
++00373                         usb_req->length, usb_req->zero, usb_req,
++00374                         gfp_flags == GFP_ATOMIC ? 1 : 0, &usb_req->ext_req);
++00375                 if (retval)
++00376                         return -EINVAL;
++00377 
++00378                 return 0;
++00379         }
++00380 #endif
++00381         retval = dwc_otg_pcd_ep_queue(pcd, usb_ep, usb_req->buf, dma_addr,
++00382                                       usb_req->length, usb_req->zero, usb_req,
++00383                                       gfp_flags == GFP_ATOMIC ? 1 : 0);
++00384         if (retval) {
++00385                 return -EINVAL;
++00386         }
++00387 
++00388         return 0;
++00389 }
++00390 
++00394 static int ep_dequeue(struct usb_ep *usb_ep, struct usb_request *usb_req)
++00395 {
++00396         DWC_DEBUGPL(DBG_PCDV, "%s(%p,%p)\n", __func__, usb_ep, usb_req);
++00397 
++00398         if (!usb_ep || !usb_req) {
++00399                 DWC_WARN("bad argument\n");
++00400                 return -EINVAL;
++00401         }
++00402         if (!gadget_wrapper->driver ||
++00403             gadget_wrapper->gadget.speed == USB_SPEED_UNKNOWN) {
++00404                 DWC_WARN("bogus device state\n");
++00405                 return -ESHUTDOWN;
++00406         }
++00407         if (dwc_otg_pcd_ep_dequeue(gadget_wrapper->pcd, usb_ep, usb_req)) {
++00408                 return -EINVAL;
++00409         }
++00410 
++00411         return 0;
++00412 }
++00413 
++00430 static int ep_halt(struct usb_ep *usb_ep, int value)
++00431 {
++00432         int retval = 0;
++00433 
++00434         DWC_DEBUGPL(DBG_PCD, "HALT %s %d\n", usb_ep->name, value);
++00435 
++00436         if (!usb_ep) {
++00437                 DWC_WARN("bad ep\n");
++00438                 return -EINVAL;
++00439         }
++00440 
++00441         retval = dwc_otg_pcd_ep_halt(gadget_wrapper->pcd, usb_ep, value);
++00442         if (retval == -DWC_E_AGAIN) {
++00443                 return -EAGAIN;
++00444         } else if (retval) {
++00445                 retval = -EINVAL;
++00446         }
++00447 
++00448         return retval;
++00449 }
++00450 
++00451 #ifdef DWC_EN_ISOC
++00452 
++00461 static int iso_ep_start(struct usb_ep *usb_ep, struct usb_iso_request *req,
++00462                         gfp_t gfp_flags)
++00463 {
++00464         int retval = 0;
++00465 
++00466         if (!req || !req->process_buffer || !req->buf0 || !req->buf1) {
++00467                 DWC_WARN("bad params\n");
++00468                 return -EINVAL;
++00469         }
++00470 
++00471         if (!usb_ep) {
++00472                 DWC_PRINTF("bad params\n");
++00473                 return -EINVAL;
++00474         }
++00475 
++00476         req->status = -EINPROGRESS;
++00477 
++00478         retval =
++00479             dwc_otg_pcd_iso_ep_start(gadget_wrapper->pcd, usb_ep, req->buf0,
++00480                                      req->buf1, req->dma0, req->dma1,
++00481                                      req->sync_frame, req->data_pattern_frame,
++00482                                      req->data_per_frame,
++00483                                      req->flags & USB_REQ_ISO_ASAP ? -1 : req->
++00484                                      start_frame, req->buf_proc_intrvl, req,
++00485                                      gfp_flags == GFP_ATOMIC ? 1 : 0);
++00486 
++00487         if (retval) {
++00488                 return -EINVAL;
++00489         }
++00490 
++00491         return retval;
++00492 }
++00493 
++00497 static int iso_ep_stop(struct usb_ep *usb_ep, struct usb_iso_request *req)
++00498 {
++00499         int retval = 0;
++00500         if (!usb_ep) {
++00501                 DWC_WARN("bad ep\n");
++00502         }
++00503 
++00504         if (!gadget_wrapper->driver ||
++00505             gadget_wrapper->gadget.speed == USB_SPEED_UNKNOWN) {
++00506                 DWC_DEBUGPL(DBG_PCDV, "gadget.speed=%d\n",
++00507                             gadget_wrapper->gadget.speed);
++00508                 DWC_WARN("bogus device state\n");
++00509         }
++00510 
++00511         dwc_otg_pcd_iso_ep_stop(gadget_wrapper->pcd, usb_ep, req);
++00512         if (retval) {
++00513                 retval = -EINVAL;
++00514         }
++00515 
++00516         return retval;
++00517 }
++00518 
++00519 static struct usb_iso_request *alloc_iso_request(struct usb_ep *ep,
++00520                                                  int packets, gfp_t gfp_flags)
++00521 {
++00522         struct usb_iso_request *pReq = NULL;
++00523         uint32_t req_size;
++00524 
++00525         req_size = sizeof(struct usb_iso_request);
++00526         req_size +=
++00527             (2 * packets * (sizeof(struct usb_gadget_iso_packet_descriptor)));
++00528 
++00529         pReq = kmalloc(req_size, gfp_flags);
++00530         if (!pReq) {
++00531                 DWC_WARN("Can't allocate Iso Request\n");
++00532                 return 0;
++00533         }
++00534         pReq->iso_packet_desc0 = (void *)(pReq + 1);
++00535 
++00536         pReq->iso_packet_desc1 = pReq->iso_packet_desc0 + packets;
++00537 
++00538         return pReq;
++00539 }
++00540 
++00541 static void free_iso_request(struct usb_ep *ep, struct usb_iso_request *req)
++00542 {
++00543         kfree(req);
++00544 }
++00545 
++00546 static struct usb_isoc_ep_ops dwc_otg_pcd_ep_ops = {
++00547         .ep_ops = {
++00548                    .enable = ep_enable,
++00549                    .disable = ep_disable,
++00550 
++00551                    .alloc_request = dwc_otg_pcd_alloc_request,
++00552                    .free_request = dwc_otg_pcd_free_request,
++00553 
++00554 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28)
++00555                    .alloc_buffer = dwc_otg_pcd_alloc_buffer,
++00556                    .free_buffer = dwc_otg_pcd_free_buffer,
++00557 #endif
++00558 
++00559                    .queue = ep_queue,
++00560                    .dequeue = ep_dequeue,
++00561 
++00562                    .set_halt = ep_halt,
++00563                    .fifo_status = 0,
++00564                    .fifo_flush = 0,
++00565                    },
++00566         .iso_ep_start = iso_ep_start,
++00567         .iso_ep_stop = iso_ep_stop,
++00568         .alloc_iso_request = alloc_iso_request,
++00569         .free_iso_request = free_iso_request,
++00570 };
++00571 
++00572 #else
++00573 
++00574 static struct usb_ep_ops dwc_otg_pcd_ep_ops = {
++00575         .enable = ep_enable,
++00576         .disable = ep_disable,
++00577 
++00578         .alloc_request = dwc_otg_pcd_alloc_request,
++00579         .free_request = dwc_otg_pcd_free_request,
++00580 
++00581 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28)
++00582         .alloc_buffer = dwc_otg_pcd_alloc_buffer,
++00583         .free_buffer = dwc_otg_pcd_free_buffer,
++00584 #endif
++00585 
++00586         .queue = ep_queue,
++00587         .dequeue = ep_dequeue,
++00588 
++00589         .set_halt = ep_halt,
++00590         .fifo_status = 0,
++00591         .fifo_flush = 0,
++00592 
++00593 };
++00594 
++00595 #endif /* _EN_ISOC_ */
++00596 /*      Gadget Operations */
++00615 static int get_frame_number(struct usb_gadget *gadget)
++00616 {
++00617         struct gadget_wrapper *d;
++00618 
++00619         DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, gadget);
++00620 
++00621         if (gadget == 0) {
++00622                 return -ENODEV;
++00623         }
++00624 
++00625         d = container_of(gadget, struct gadget_wrapper, gadget);
++00626         return dwc_otg_pcd_get_frame_number(d->pcd);
++00627 }
++00628 
++00629 #ifdef CONFIG_USB_DWC_OTG_LPM
++00630 static int test_lpm_enabled(struct usb_gadget *gadget)
++00631 {
++00632         struct gadget_wrapper *d;
++00633 
++00634         d = container_of(gadget, struct gadget_wrapper, gadget);
++00635 
++00636         return dwc_otg_pcd_is_lpm_enabled(d->pcd);
++00637 }
++00638 #endif
++00639 
++00646 static int wakeup(struct usb_gadget *gadget)
++00647 {
++00648         struct gadget_wrapper *d;
++00649 
++00650         DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, gadget);
++00651 
++00652         if (gadget == 0) {
++00653                 return -ENODEV;
++00654         } else {
++00655                 d = container_of(gadget, struct gadget_wrapper, gadget);
++00656         }
++00657         dwc_otg_pcd_wakeup(d->pcd);
++00658         return 0;
++00659 }
++00660 
++00661 static const struct usb_gadget_ops dwc_otg_pcd_ops = {
++00662         .get_frame = get_frame_number,
++00663         .wakeup = wakeup,
++00664 #ifdef CONFIG_USB_DWC_OTG_LPM
++00665         .lpm_support = test_lpm_enabled,
++00666 #endif
++00667         // current versions must always be self-powered
++00668 };
++00669 
++00670 static int _setup(dwc_otg_pcd_t * pcd, uint8_t * bytes)
++00671 {
++00672         int retval = -DWC_E_NOT_SUPPORTED;
++00673         if (gadget_wrapper->driver && gadget_wrapper->driver->setup) {
++00674                 retval = gadget_wrapper->driver->setup(&gadget_wrapper->gadget,
++00675                                                        (struct usb_ctrlrequest
++00676                                                         *)bytes);
++00677         }
++00678 
++00679         if (retval == -ENOTSUPP) {
++00680                 retval = -DWC_E_NOT_SUPPORTED;
++00681         } else if (retval < 0) {
++00682                 retval = -DWC_E_INVALID;
++00683         }
++00684 
++00685         return retval;
++00686 }
++00687 
++00688 #ifdef DWC_EN_ISOC
++00689 static int _isoc_complete(dwc_otg_pcd_t * pcd, void *ep_handle,
++00690                           void *req_handle, int proc_buf_num)
++00691 {
++00692         int i, packet_count;
++00693         struct usb_gadget_iso_packet_descriptor *iso_packet = 0;
++00694         struct usb_iso_request *iso_req = req_handle;
++00695 
++00696         if (proc_buf_num) {
++00697                 iso_packet = iso_req->iso_packet_desc1;
++00698         } else {
++00699                 iso_packet = iso_req->iso_packet_desc0;
++00700         }
++00701         packet_count =
++00702             dwc_otg_pcd_get_iso_packet_count(pcd, ep_handle, req_handle);
++00703         for (i = 0; i < packet_count; ++i) {
++00704                 int status;
++00705                 int actual;
++00706                 int offset;
++00707                 dwc_otg_pcd_get_iso_packet_params(pcd, ep_handle, req_handle,
++00708                                                   i, &status, &actual, &offset);
++00709                 switch (status) {
++00710                 case -DWC_E_NO_DATA:
++00711                         status = -ENODATA;
++00712                         break;
++00713                 default:
++00714                         if (status) {
++00715                                 DWC_PRINTF("unknown status in isoc packet\n");
++00716                         }
++00717 
++00718                 }
++00719                 iso_packet[i].status = status;
++00720                 iso_packet[i].offset = offset;
++00721                 iso_packet[i].actual_length = actual;
++00722         }
++00723 
++00724         iso_req->status = 0;
++00725         iso_req->process_buffer(ep_handle, iso_req);
++00726 
++00727         return 0;
++00728 }
++00729 #endif /* DWC_EN_ISOC */
++00730 
++00731 #ifdef DWC_UTE_PER_IO
++00732 
++00744 static int _xisoc_complete(dwc_otg_pcd_t * pcd, void *ep_handle,
++00745                            void *req_handle, int32_t status, void *ereq_port)
++00746 {
++00747         struct dwc_ute_iso_req_ext *ereqorg = NULL;
++00748         struct dwc_iso_xreq_port *ereqport = NULL;
++00749         struct dwc_ute_iso_packet_descriptor *desc_org = NULL;
++00750         int i;
++00751         struct usb_request *req;
++00752         //struct dwc_ute_iso_packet_descriptor *
++00753         //int status = 0;
++00754 
++00755         req = (struct usb_request *)req_handle;
++00756         ereqorg = &req->ext_req;
++00757         ereqport = (struct dwc_iso_xreq_port *)ereq_port;
++00758         desc_org = ereqorg->per_io_frame_descs;
++00759 
++00760         if (req && req->complete) {
++00761                 /* Copy the request data from the portable logic to our request */
++00762                 for (i = 0; i < ereqport->pio_pkt_count; i++) {
++00763                         desc_org[i].actual_length =
++00764                             ereqport->per_io_frame_descs[i].actual_length;
++00765                         desc_org[i].status =
++00766                             ereqport->per_io_frame_descs[i].status;
++00767                 }
++00768 
++00769                 switch (status) {
++00770                 case -DWC_E_SHUTDOWN:
++00771                         req->status = -ESHUTDOWN;
++00772                         break;
++00773                 case -DWC_E_RESTART:
++00774                         req->status = -ECONNRESET;
++00775                         break;
++00776                 case -DWC_E_INVALID:
++00777                         req->status = -EINVAL;
++00778                         break;
++00779                 case -DWC_E_TIMEOUT:
++00780                         req->status = -ETIMEDOUT;
++00781                         break;
++00782                 default:
++00783                         req->status = status;
++00784                 }
++00785 
++00786                 /* And call the gadget's completion */
++00787                 req->complete(ep_handle, req);
++00788         }
++00789 
++00790         return 0;
++00791 }
++00792 #endif /* DWC_UTE_PER_IO */
++00793 static int _complete(dwc_otg_pcd_t * pcd, void *ep_handle,
++00794                      void *req_handle, int32_t status, uint32_t actual)
++00795 {
++00796         struct usb_request *req = (struct usb_request *)req_handle;
++00797 #if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,27)
++00798         struct dwc_otg_pcd_ep *ep = NULL;
++00799 #endif
++00800 #ifdef PCI_INTERFACE
++00801         struct pci_dev *dev = NULL;
++00802 #endif
++00803 
++00804         if (req && req->complete) {
++00805                 switch (status) {
++00806                 case -DWC_E_SHUTDOWN:
++00807                         req->status = -ESHUTDOWN;
++00808                         break;
++00809                 case -DWC_E_RESTART:
++00810                         req->status = -ECONNRESET;
++00811                         break;
++00812                 case -DWC_E_INVALID:
++00813                         req->status = -EINVAL;
++00814                         break;
++00815                 case -DWC_E_TIMEOUT:
++00816                         req->status = -ETIMEDOUT;
++00817                         break;
++00818                 default:
++00819                         req->status = status;
++00820 
++00821                 }
++00822 
++00823                 req->actual = actual;
++00824                 DWC_SPINUNLOCK(pcd->lock);
++00825                 req->complete(ep_handle, req);
++00826                 DWC_SPINLOCK(pcd->lock);
++00827         }
++00828 #ifdef PCI_INTERFACE
++00829         dev = gadget_wrapper->pcd->otg_dev->os_dep.pcidev;
++00830         ep = ep_from_handle(pcd, ep_handle);
++00831         if (GET_CORE_IF(pcd)->dma_enable) {
++00832                 if (req->length != 0)
++00833                         pci_unmap_single(dev, req->dma, req->length,
++00834                                          ep->dwc_ep.
++00835                                          is_in ? PCI_DMA_TODEVICE :
++00836                                          PCI_DMA_FROMDEVICE);
++00837         }
++00838 #endif
++00839 
++00840         return 0;
++00841 }
++00842 
++00843 static int _connect(dwc_otg_pcd_t * pcd, int speed)
++00844 {
++00845         gadget_wrapper->gadget.speed = speed;
++00846         return 0;
++00847 }
++00848 
++00849 static int _disconnect(dwc_otg_pcd_t * pcd)
++00850 {
++00851         if (gadget_wrapper->driver && gadget_wrapper->driver->disconnect) {
++00852                 gadget_wrapper->driver->disconnect(&gadget_wrapper->gadget);
++00853         }
++00854         return 0;
++00855 }
++00856 
++00857 static int _resume(dwc_otg_pcd_t * pcd)
++00858 {
++00859         if (gadget_wrapper->driver && gadget_wrapper->driver->resume) {
++00860                 gadget_wrapper->driver->resume(&gadget_wrapper->gadget);
++00861         }
++00862 
++00863         return 0;
++00864 }
++00865 
++00866 static int _suspend(dwc_otg_pcd_t * pcd)
++00867 {
++00868         if (gadget_wrapper->driver && gadget_wrapper->driver->suspend) {
++00869                 gadget_wrapper->driver->suspend(&gadget_wrapper->gadget);
++00870         }
++00871         return 0;
++00872 }
++00873 
++00877 static int _hnp_changed(dwc_otg_pcd_t * pcd)
++00878 {
++00879 
++00880         if (!gadget_wrapper->gadget.is_otg)
++00881                 return 0;
++00882 
++00883         gadget_wrapper->gadget.b_hnp_enable = get_b_hnp_enable(pcd);
++00884         gadget_wrapper->gadget.a_hnp_support = get_a_hnp_support(pcd);
++00885         gadget_wrapper->gadget.a_alt_hnp_support = get_a_alt_hnp_support(pcd);
++00886         return 0;
++00887 }
++00888 
++00889 static int _reset(dwc_otg_pcd_t * pcd)
++00890 {
++00891         return 0;
++00892 }
++00893 
++00894 #ifdef DWC_UTE_CFI
++00895 static int _cfi_setup(dwc_otg_pcd_t * pcd, void *cfi_req)
++00896 {
++00897         int retval = -DWC_E_INVALID;
++00898         if (gadget_wrapper->driver->cfi_feature_setup) {
++00899                 retval =
++00900                     gadget_wrapper->driver->
++00901                     cfi_feature_setup(&gadget_wrapper->gadget,
++00902                                       (struct cfi_usb_ctrlrequest *)cfi_req);
++00903         }
++00904 
++00905         return retval;
++00906 }
++00907 #endif
++00908 
++00909 static const struct dwc_otg_pcd_function_ops fops = {
++00910         .complete = _complete,
++00911 #ifdef DWC_EN_ISOC
++00912         .isoc_complete = _isoc_complete,
++00913 #endif
++00914         .setup = _setup,
++00915         .disconnect = _disconnect,
++00916         .connect = _connect,
++00917         .resume = _resume,
++00918         .suspend = _suspend,
++00919         .hnp_changed = _hnp_changed,
++00920         .reset = _reset,
++00921 #ifdef DWC_UTE_CFI
++00922         .cfi_setup = _cfi_setup,
++00923 #endif
++00924 #ifdef DWC_UTE_PER_IO
++00925         .xisoc_complete = _xisoc_complete,
++00926 #endif
++00927 };
++00928 
++00932 static irqreturn_t dwc_otg_pcd_irq(int irq, void *dev)
++00933 {
++00934         dwc_otg_pcd_t *pcd = dev;
++00935         int32_t retval = IRQ_NONE;
++00936 
++00937         retval = dwc_otg_pcd_handle_intr(pcd);
++00938         if (retval != 0) {
++00939                 S3C2410X_CLEAR_EINTPEND();
++00940         }
++00941         return IRQ_RETVAL(retval);
++00942 }
++00943 
++00950 void gadget_add_eps(struct gadget_wrapper *d)
++00951 {
++00952         static const char *names[] = {
++00953 
++00954                 "ep0",
++00955                 "ep1in",
++00956                 "ep2in",
++00957                 "ep3in",
++00958                 "ep4in",
++00959                 "ep5in",
++00960                 "ep6in",
++00961                 "ep7in",
++00962                 "ep8in",
++00963                 "ep9in",
++00964                 "ep10in",
++00965                 "ep11in",
++00966                 "ep12in",
++00967                 "ep13in",
++00968                 "ep14in",
++00969                 "ep15in",
++00970                 "ep1out",
++00971                 "ep2out",
++00972                 "ep3out",
++00973                 "ep4out",
++00974                 "ep5out",
++00975                 "ep6out",
++00976                 "ep7out",
++00977                 "ep8out",
++00978                 "ep9out",
++00979                 "ep10out",
++00980                 "ep11out",
++00981                 "ep12out",
++00982                 "ep13out",
++00983                 "ep14out",
++00984                 "ep15out"
++00985         };
++00986 
++00987         int i;
++00988         struct usb_ep *ep;
++00989         int8_t dev_endpoints;
++00990 
++00991         DWC_DEBUGPL(DBG_PCDV, "%s\n", __func__);
++00992 
++00993         INIT_LIST_HEAD(&d->gadget.ep_list);
++00994         d->gadget.ep0 = &d->ep0;
++00995         d->gadget.speed = USB_SPEED_UNKNOWN;
++00996 
++00997         INIT_LIST_HEAD(&d->gadget.ep0->ep_list);
++00998 
++01002         ep = &d->ep0;
++01003 
++01004         /* Init the usb_ep structure. */
++01005         ep->name = names[0];
++01006         ep->ops = (struct usb_ep_ops *)&dwc_otg_pcd_ep_ops;
++01007 
++01012         ep->maxpacket = MAX_PACKET_SIZE;
++01013         dwc_otg_pcd_ep_enable(d->pcd, NULL, ep);
++01014 
++01015         list_add_tail(&ep->ep_list, &d->gadget.ep_list);
++01016 
++01020         dev_endpoints = d->pcd->core_if->dev_if->num_in_eps;
++01021 
++01022         for (i = 0; i < dev_endpoints; i++) {
++01023                 ep = &d->in_ep[i];
++01024 
++01025                 /* Init the usb_ep structure. */
++01026                 ep->name = names[d->pcd->in_ep[i].dwc_ep.num];
++01027                 ep->ops = (struct usb_ep_ops *)&dwc_otg_pcd_ep_ops;
++01028 
++01033                 ep->maxpacket = MAX_PACKET_SIZE;
++01034                 list_add_tail(&ep->ep_list, &d->gadget.ep_list);
++01035         }
++01036 
++01037         dev_endpoints = d->pcd->core_if->dev_if->num_out_eps;
++01038 
++01039         for (i = 0; i < dev_endpoints; i++) {
++01040                 ep = &d->out_ep[i];
++01041 
++01042                 /* Init the usb_ep structure. */
++01043                 ep->name = names[15 + d->pcd->out_ep[i].dwc_ep.num];
++01044                 ep->ops = (struct usb_ep_ops *)&dwc_otg_pcd_ep_ops;
++01045 
++01050                 ep->maxpacket = MAX_PACKET_SIZE;
++01051 
++01052                 list_add_tail(&ep->ep_list, &d->gadget.ep_list);
++01053         }
++01054 
++01055         /* remove ep0 from the list.  There is a ep0 pointer. */
++01056         list_del_init(&d->ep0.ep_list);
++01057 
++01058         d->ep0.maxpacket = MAX_EP0_SIZE;
++01059 }
++01060 
++01067 static void dwc_otg_pcd_gadget_release(struct device *dev)
++01068 {
++01069         DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, dev);
++01070 }
++01071 
++01072 static struct gadget_wrapper *alloc_wrapper(
++01073 #ifdef LM_INTERFACE
++01074         struct lm_device *_dev
++01075 #elif  defined(PCI_INTERFACE)
++01076         struct pci_dev *_dev
++01077 #endif
++01078     )
++01079 {
++01080         static char pcd_name[] = "dwc_otg_pcd";
++01081 #ifdef LM_INTERFACE
++01082         dwc_otg_device_t *otg_dev = lm_get_drvdata(_dev);
++01083 #elif defined(PCI_INTERFACE)
++01084         dwc_otg_device_t *otg_dev = pci_get_drvdata(_dev);
++01085 #endif
++01086 
++01087         struct gadget_wrapper *d;
++01088         int retval;
++01089 
++01090         d = DWC_ALLOC(sizeof(*d));
++01091         if (d == NULL) {
++01092                 return NULL;
++01093         }
++01094 
++01095         memset(d, 0, sizeof(*d));
++01096 
++01097         d->gadget.name = pcd_name;
++01098         d->pcd = otg_dev->pcd;
++01099 
++01100 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30)
++01101         strcpy(d->gadget.dev.bus_id, "gadget");
++01102 #else
++01103         dev_set_name(&d->gadget.dev, "%s", "gadget");
++01104 #endif
++01105 
++01106         d->gadget.dev.parent = &_dev->dev;
++01107         d->gadget.dev.release = dwc_otg_pcd_gadget_release;
++01108         d->gadget.ops = &dwc_otg_pcd_ops;
++01109         d->gadget.is_dualspeed = dwc_otg_pcd_is_dualspeed(otg_dev->pcd);
++01110         d->gadget.is_otg = dwc_otg_pcd_is_otg(otg_dev->pcd);
++01111 
++01112         d->driver = 0;
++01113         /* Register the gadget device */
++01114         retval = device_register(&d->gadget.dev);
++01115         if (retval != 0) {
++01116                 DWC_ERROR("device_register failed\n");
++01117                 DWC_FREE(d);
++01118                 return NULL;
++01119         }
++01120 
++01121         return d;
++01122 }
++01123 
++01124 static void free_wrapper(struct gadget_wrapper *d)
++01125 {
++01126         if (d->driver) {
++01127                 /* should have been done already by driver model core */
++01128                 DWC_WARN("driver '%s' is still registered\n",
++01129                          d->driver->driver.name);
++01130                 usb_gadget_unregister_driver(d->driver);
++01131         }
++01132 
++01133         device_unregister(&d->gadget.dev);
++01134         DWC_FREE(d);
++01135 }
++01136 
++01141 int pcd_init(
++01142 #ifdef LM_INTERFACE
++01143         struct lm_device *_dev
++01144 #elif  defined(PCI_INTERFACE)
++01145         struct pci_dev *_dev
++01146 #endif
++01147     )
++01148 {
++01149 #ifdef LM_INTERFACE
++01150         dwc_otg_device_t *otg_dev = lm_get_drvdata(_dev);
++01151 #elif  defined(PCI_INTERFACE)
++01152         dwc_otg_device_t *otg_dev = pci_get_drvdata(_dev);
++01153 #endif
++01154 
++01155         int retval = 0;
++01156 
++01157         DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, _dev);
++01158 
++01159         otg_dev->pcd = dwc_otg_pcd_init(otg_dev->core_if);
++01160 
++01161         if (!otg_dev->pcd) {
++01162                 DWC_ERROR("dwc_otg_pcd_init failed\n");
++01163                 return -ENOMEM;
++01164         }
++01165 
++01166         otg_dev->pcd->otg_dev = otg_dev;
++01167         gadget_wrapper = alloc_wrapper(_dev);
++01168 
++01169         /*
++01170          * Initialize EP structures
++01171          */
++01172         gadget_add_eps(gadget_wrapper);
++01173         /*
++01174          * Setup interupt handler
++01175          */
++01176         DWC_DEBUGPL(DBG_ANY, "registering handler for irq%d\n", _dev->irq);
++01177         retval = request_irq(_dev->irq, dwc_otg_pcd_irq,
++01178                              IRQF_SHARED | IRQF_DISABLED,
++01179                              gadget_wrapper->gadget.name, otg_dev->pcd);
++01180         if (retval != 0) {
++01181                 DWC_ERROR("request of irq%d failed\n", _dev->irq);
++01182                 free_wrapper(gadget_wrapper);
++01183                 return -EBUSY;
++01184         }
++01185 
++01186         dwc_otg_pcd_start(gadget_wrapper->pcd, &fops);
++01187 
++01188         return retval;
++01189 }
++01190 
++01194 void pcd_remove(
++01195 #ifdef LM_INTERFACE
++01196         struct lm_device *_dev
++01197 #elif  defined(PCI_INTERFACE)
++01198         struct pci_dev *_dev
++01199 #endif
++01200     )
++01201 {
++01202 #ifdef LM_INTERFACE
++01203         dwc_otg_device_t *otg_dev = lm_get_drvdata(_dev);
++01204 #elif  defined(PCI_INTERFACE)
++01205         dwc_otg_device_t *otg_dev = pci_get_drvdata(_dev);
++01206 #endif
++01207         dwc_otg_pcd_t *pcd = otg_dev->pcd;
++01208 
++01209         DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, _dev);
++01210 
++01211         /*
++01212          * Free the IRQ
++01213          */
++01214         free_irq(_dev->irq, pcd);
++01215         dwc_otg_pcd_remove(otg_dev->pcd);
++01216         free_wrapper(gadget_wrapper);
++01217         otg_dev->pcd = 0;
++01218 }
++01219 
++01231 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,37)
++01232 int usb_gadget_register_driver(struct usb_gadget_driver *driver)
++01233 #else
++01234 int usb_gadget_probe_driver(struct usb_gadget_driver *driver,
++01235                 int (*bind)(struct usb_gadget *))
++01236 #endif
++01237 {
++01238         int retval;
++01239 
++01240         DWC_DEBUGPL(DBG_PCD, "registering gadget driver '%s'\n",
++01241                     driver->driver.name);
++01242 
++01243         if (!driver || driver->speed == USB_SPEED_UNKNOWN ||
++01244 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,37)
++01245             !driver->bind ||
++01246 #else
++01247                 !bind ||
++01248 #endif
++01249             !driver->unbind || !driver->disconnect || !driver->setup) {
++01250                 DWC_DEBUGPL(DBG_PCDV, "EINVAL\n");
++01251                 return -EINVAL;
++01252         }
++01253         if (gadget_wrapper == 0) {
++01254                 DWC_DEBUGPL(DBG_PCDV, "ENODEV\n");
++01255                 return -ENODEV;
++01256         }
++01257         if (gadget_wrapper->driver != 0) {
++01258                 DWC_DEBUGPL(DBG_PCDV, "EBUSY (%p)\n", gadget_wrapper->driver);
++01259                 return -EBUSY;
++01260         }
++01261 
++01262         /* hook up the driver */
++01263         gadget_wrapper->driver = driver;
++01264         gadget_wrapper->gadget.dev.driver = &driver->driver;
++01265 
++01266         DWC_DEBUGPL(DBG_PCD, "bind to driver %s\n", driver->driver.name);
++01267 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,37)
++01268         retval = driver->bind(&gadget_wrapper->gadget);
++01269 #else
++01270         retval = bind(&gadget_wrapper->gadget);
++01271 #endif
++01272         if (retval) {
++01273                 DWC_ERROR("bind to driver %s --> error %d\n",
++01274                           driver->driver.name, retval);
++01275                 gadget_wrapper->driver = 0;
++01276                 gadget_wrapper->gadget.dev.driver = 0;
++01277                 return retval;
++01278         }
++01279         DWC_DEBUGPL(DBG_ANY, "registered gadget driver '%s'\n",
++01280                     driver->driver.name);
++01281         return 0;
++01282 }
++01283 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,37)
++01284 EXPORT_SYMBOL(usb_gadget_register_driver);
++01285 #else
++01286 EXPORT_SYMBOL(usb_gadget_probe_driver);
++01287 #endif
++01288 
++01294 int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
++01295 {
++01296         //DWC_DEBUGPL(DBG_PCDV,"%s(%p)\n", __func__, _driver);
++01297 
++01298         if (gadget_wrapper == 0) {
++01299                 DWC_DEBUGPL(DBG_ANY, "%s Return(%d): s_pcd==0\n", __func__,
++01300                             -ENODEV);
++01301                 return -ENODEV;
++01302         }
++01303         if (driver == 0 || driver != gadget_wrapper->driver) {
++01304                 DWC_DEBUGPL(DBG_ANY, "%s Return(%d): driver?\n", __func__,
++01305                             -EINVAL);
++01306                 return -EINVAL;
++01307         }
++01308 
++01309         driver->unbind(&gadget_wrapper->gadget);
++01310         gadget_wrapper->driver = 0;
++01311 
++01312         DWC_DEBUGPL(DBG_ANY, "unregistered driver '%s'\n", driver->driver.name);
++01313         return 0;
++01314 }
++01315 
++01316 EXPORT_SYMBOL(usb_gadget_unregister_driver);
++01317 
++01318 #endif /* DWC_HOST_ONLY */
++
      Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
      ++doxygen 1.3.9.1
      + + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__pcd__linux_8c.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/dwc__otg__pcd__linux_8c.html 2013-07-26 19:31:22.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__pcd__linux_8c.html 2013-07-26 19:34:42.000000000 +0000 +@@ -2,169 +2,146 @@ + + DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_pcd_linux.c File Reference + +- + +- +-
      +-
      +-
      +-
      ++ ++
      Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
      +

      dwc_otg_pcd_linux.c File Reference

      This file implements the Peripheral Controller Driver. More... +

      +-#include <linux/kernel.h>
      +-#include <linux/module.h>
      +-#include <linux/moduleparam.h>
      +-#include <linux/init.h>
      +-#include <linux/device.h>
      +-#include <linux/errno.h>
      +-#include <linux/list.h>
      +-#include <linux/interrupt.h>
      +-#include <linux/string.h>
      +-#include <linux/dma-mapping.h>
      +-#include <linux/version.h>
      +-#include <asm/io.h>
      +-#include <linux/usb_ch9.h>
      +-#include <linux/usb_gadget.h>
      +-#include "dwc_otg_pcd_if.h"
      +-#include "dwc_otg_driver.h"
      +-#include "dwc_otg_dbg.h"
      ++#include "dwc_otg_os_dep.h"
      ++#include "dwc_otg_pcd_if.h"
      ++#include "dwc_otg_pcd.h"
      ++#include "dwc_otg_driver.h"
      ++#include "dwc_otg_dbg.h"
      + +

      + Go to the source code of this file. + + +- ++ + + +- + +- ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- +- +- +- ++ ++ + + +- ++ + +- +- ++ ++ + +- +- ++ ++ + + +- ++ + +- ++ + +- ++ + + +- ++ + +- +- ++ ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + + +- ++ + +- ++ + + +- ++ + +- +- ++ ++ + +- +- ++ ++ + +- ++ + +- ++ + + +- ++ + + +- ++ + +- +- ++ ++ + +- ++ + +- +- ++ + + +- ++ ++ ++ + +- ++ + +- ++ + +

      Data Structures

      struct  gadget_wrapper
      struct  gadget_wrapper

      Functions

      ++
      + void dump_msg (const u8 *buf, unsigned int length)
      static int ep_enable (struct usb_ep *usb_ep, const struct usb_endpoint_descriptor *ep_desc)
      ++dwc_otg_pcd_ep * ep_from_handle (dwc_otg_pcd_t *pcd, void *handle)
       This function is called by the Gadget Driver for each EP to be configured for the current configuration (SET_CONFIGURATION).
      static int ep_disable (struct usb_ep *usb_ep)
       Get the dwc_otg_pcd_ep_t* from usb_ep* pointer - NULL in case if the endpoint is not found.
      int ep_enable (struct usb_ep *usb_ep, const struct usb_endpoint_descriptor *ep_desc)
       This function is called when an EP is disabled due to disconnect or change in configuration.
      static struct usb_request * dwc_otg_pcd_alloc_request (struct usb_ep *ep, gfp_t gfp_flags)
       This function is called by the Gadget Driver for each EP to be configured for the current configuration (SET_CONFIGURATION).
      int ep_disable (struct usb_ep *usb_ep)
       This function allocates a request object to use with the specified endpoint.
      static void dwc_otg_pcd_free_request (struct usb_ep *ep, struct usb_request *req)
       This function is called when an EP is disabled due to disconnect or change in configuration.
      usb_request * dwc_otg_pcd_alloc_request (struct usb_ep *ep, gfp_t gfp_flags)
       This function frees a request object.
      static void * dwc_otg_pcd_alloc_buffer (struct usb_ep *usb_ep, unsigned bytes, dma_addr_t *dma, gfp_t gfp_flags)
       This function allocates a request object to use with the specified endpoint.
      void dwc_otg_pcd_free_request (struct usb_ep *ep, struct usb_request *req)
       This function allocates an I/O buffer to be used for a transfer to/from the specified endpoint.
      static void dwc_otg_pcd_free_buffer (struct usb_ep *usb_ep, void *buf, dma_addr_t dma, unsigned bytes)
       This function frees a request object.
      int ep_queue (struct usb_ep *usb_ep, struct usb_request *usb_req, gfp_t gfp_flags)
       This function frees an I/O buffer that was allocated by alloc_buffer.
      static int ep_queue (struct usb_ep *usb_ep, struct usb_request *usb_req, gfp_t gfp_flags)
       This function is used to submit an I/O Request to an EP.
      +-static int ep_dequeue (struct usb_ep *usb_ep, struct usb_request *usb_req)
       This function is used to submit an I/O Request to an EP.
      ++int ep_dequeue (struct usb_ep *usb_ep, struct usb_request *usb_req)
       This function cancels an I/O request from an EP.
      static int ep_halt (struct usb_ep *usb_ep, int value)
      int ep_halt (struct usb_ep *usb_ep, int value)
       usb_ep_set_halt stalls an endpoint.
      static int iso_ep_start (struct usb_ep *usb_ep, struct usb_iso_request *req, gfp_t gfp_flags)
       usb_ep_set_halt stalls an endpoint.
      int iso_ep_start (struct usb_ep *usb_ep, struct usb_iso_request *req, gfp_t gfp_flags)
       This function is used to submit an ISOC Transfer Request to an EP.
      +-static int iso_ep_stop (struct usb_ep *usb_ep, struct usb_iso_request *req)
       This function is used to submit an ISOC Transfer Request to an EP.
      ++int iso_ep_stop (struct usb_ep *usb_ep, struct usb_iso_request *req)
       This function stops ISO EP Periodic Data Transfer.
      +-static struct usb_iso_request * alloc_iso_request (struct usb_ep *ep, int packets, gfp_t gfp_flags)
      ++usb_iso_request * alloc_iso_request (struct usb_ep *ep, int packets, gfp_t gfp_flags)
      +-static void free_iso_request (struct usb_ep *ep, struct usb_iso_request *req)
      ++void free_iso_request (struct usb_ep *ep, struct usb_iso_request *req)
      +-static int get_frame_number (struct usb_gadget *gadget)
      ++int get_frame_number (struct usb_gadget *gadget)
       Gets the USB Frame number of the last SOF.
      static int wakeup (struct usb_gadget *gadget)
      int wakeup (struct usb_gadget *gadget)
       Initiates Session Request Protocol (SRP) to wakeup the host if no session is in progress.
      +-static int _setup (dwc_otg_pcd_t *pcd, uint8_t *bytes)
       Initiates Session Request Protocol (SRP) to wakeup the host if no session is in progress.
      ++int _setup (dwc_otg_pcd_t *pcd, uint8_t *bytes)
      +-static int _isoc_complete (dwc_otg_pcd_t *pcd, void *ep_handle, void *req_handle, int proc_buf_num)
      ++int _isoc_complete (dwc_otg_pcd_t *pcd, void *ep_handle, void *req_handle, int proc_buf_num)
      +-static int _complete (dwc_otg_pcd_t *pcd, void *ep_handle, void *req_handle, int32_t status, uint32_t actual)
      ++int _complete (dwc_otg_pcd_t *pcd, void *ep_handle, void *req_handle, int32_t status, uint32_t actual)
      +-static int _connect (dwc_otg_pcd_t *pcd, int speed)
      ++int _connect (dwc_otg_pcd_t *pcd, int speed)
      +-static int _disconnect (dwc_otg_pcd_t *pcd)
      ++int _disconnect (dwc_otg_pcd_t *pcd)
      +-static int _resume (dwc_otg_pcd_t *pcd)
      ++int _resume (dwc_otg_pcd_t *pcd)
      +-static int _suspend (dwc_otg_pcd_t *pcd)
      ++int _suspend (dwc_otg_pcd_t *pcd)
      +-static int _hnp_changed (dwc_otg_pcd_t *pcd)
      ++int _hnp_changed (dwc_otg_pcd_t *pcd)
       This function updates the otg values in the gadget structure.
      +-static int _reset (dwc_otg_pcd_t *pcd)
      ++int _reset (dwc_otg_pcd_t *pcd)
      +-static irqreturn_t dwc_otg_pcd_irq (int irq, void *dev)
      ++irqreturn_t dwc_otg_pcd_irq (int irq, void *dev)
       This function is the top level PCD interrupt handler.
      void gadget_add_eps (struct gadget_wrapper *d)
      void gadget_add_eps (struct gadget_wrapper *d)
       This function initialized the usb_ep structures to there default state.
      static void dwc_otg_pcd_gadget_release (struct device *dev)
       This function initialized the usb_ep structures to there default state.
      void dwc_otg_pcd_gadget_release (struct device *dev)
       This function releases the Gadget device.
      +-static struct gadget_wrapper * alloc_wrapper ()
       This function releases the Gadget device.
      ++gadget_wrapper * alloc_wrapper ()
      +-static void free_wrapper (struct gadget_wrapper *d)
      ++void free_wrapper (struct gadget_wrapper *d)
      +-int pcd_init ()
      ++int pcd_init ()
       This function initialized the PCD portion of the driver.
      +-void pcd_remove ()
      ++void pcd_remove ()
       Cleanup the PCD.
      int usb_gadget_register_driver (struct usb_gadget_driver *driver)
      int usb_gadget_probe_driver (struct usb_gadget_driver *driver, int(*bind)(struct usb_gadget *))
       This function registers a gadget driver with the PCD.
      +- EXPORT_SYMBOL (usb_gadget_register_driver)
       This function registers a gadget driver with the PCD.
      ++ EXPORT_SYMBOL (usb_gadget_probe_driver)
      int usb_gadget_unregister_driver (struct usb_gadget_driver *driver)
      int usb_gadget_unregister_driver (struct usb_gadget_driver *driver)
       This function unregisters a gadget driver.
      ++
       This function unregisters a gadget driver.
      +  EXPORT_SYMBOL (usb_gadget_unregister_driver)

      Variables

      static struct usb_isoc_ep_ops dwc_otg_pcd_ep_ops
      ++gadget_wrapper * gadget_wrapper
      usb_isoc_ep_ops dwc_otg_pcd_ep_ops
      static struct usb_gadget_ops dwc_otg_pcd_ops
      const struct usb_gadget_ops dwc_otg_pcd_ops
      static struct dwc_otg_pcd_function_ops fops
      const struct dwc_otg_pcd_function_ops fops
      +

      Detailed Description

      +@@ -172,57 +149,73 @@ +

      + The Peripheral Controller Driver (PCD) is responsible for translating requests from the Function Driver into the appropriate actions on the DWC_otg controller. It isolates the Function Driver from the specifics of the controller by providing an API to the Function Driver.

      + The Peripheral Controller Driver for Linux will implement the Gadget API, so that the existing Gadget drivers can be used. (Gadget Driver is the Linux terminology for a Function Driver.)

      +-The Linux Gadget API is defined in the header file <linux/usb_gadget.h>. The USB EP operations API is defined in the structure usb_ep_ops and the USB Controller API is defined in the structure usb_gadget_ops. ++The Linux Gadget API is defined in the header file <linux/usb_gadget.h>. The USB EP operations API is defined in the structure usb_ep_ops and the USB Controller API is defined in the structure usb_gadget_ops. +

      + Definition in file dwc_otg_pcd_linux.c.

      Function Documentation

      +- +-
      +-
      +- ++

      ++

      ++ ++ ++ ++
      ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
      static int ep_enable (struct usb_ep *  usb_ep, int ep_enable ( struct usb_ep *  usb_ep,
      const struct usb_endpoint_descriptor *  ep_desc const struct usb_endpoint_descriptor *  ep_desc
      ) [static])  [static]
      +- +-
      ++
      ++ ++ ++ ++
      ++   ++ + +

      + This function is called by the Gadget Driver for each EP to be configured for the current configuration (SET_CONFIGURATION). +

      + This function initializes the dwc_otg_ep_t data structure, and then calls dwc_otg_ep_activate. +

      +-Definition at line 121 of file dwc_otg_pcd_linux.c. +- +-

      +- +-

      +-
      +- +- +- +- +- +- +- +- ++Definition at line 121 of file dwc_otg_pcd_linux.c. ++ ++
      static int ep_disable (struct usb_ep *  usb_ep  )  [static]
      ++

      ++ ++ ++ ++ ++
      ++ ++ ++ ++ ++ ++ ++ ++ + +
      int ep_disable ( struct usb_ep *  usb_ep  )  [static]
      +- +-
      ++
      ++ ++ ++ ++
      ++   ++ + +

      + This function is called when an EP is disabled due to disconnect or change in configuration. +@@ -230,33 +223,41 @@ + Any pending requests will terminate with a status of -ESHUTDOWN.

      + This function modifies the dwc_otg_ep_t data structure for this EP, and then calls dwc_otg_ep_deactivate. +

      +-Definition at line 170 of file dwc_otg_pcd_linux.c. +- +-

      +- +-

      +-
      +- ++Definition at line 177 of file dwc_otg_pcd_linux.c. ++ ++
      ++

      ++ ++ ++ ++ ++
      ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
      static struct usb_request* dwc_otg_pcd_alloc_request (struct usb_ep *  ep, struct usb_request* dwc_otg_pcd_alloc_request ( struct usb_ep *  ep,
      gfp_t  gfp_flags gfp_t  gfp_flags
      ) [static])  [static]
      +- +-
      ++
      ++ ++ ++ ++
      ++   ++ + +

      + This function allocates a request object to use with the specified endpoint. +@@ -269,33 +270,41 @@ + + +

      +-Definition at line 196 of file dwc_otg_pcd_linux.c. +- +-

      +- +-

      +-
      +- ++Definition at line 203 of file dwc_otg_pcd_linux.c. ++ ++
      ++

      ++ ++ ++ ++ ++
      ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
      static void dwc_otg_pcd_free_request (struct usb_ep *  ep, void dwc_otg_pcd_free_request ( struct usb_ep *  ep,
      struct usb_request *  req struct usb_request *  req
      ) [static])  [static]
      +- +-
      ++
      ++ ++ ++ ++
      ++   ++ + +

      + This function frees a request object. +@@ -308,146 +317,47 @@ + + +

      +-Definition at line 223 of file dwc_otg_pcd_linux.c. +- +-

      +- +-

      +-
      +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
      static void* dwc_otg_pcd_alloc_buffer (struct usb_ep *  usb_ep,
      unsigned  bytes,
      dma_addr_t *  dma,
      gfp_t  gfp_flags 
      ) [static]
      +-
      +-
      +- +-

      +-This function allocates an I/O buffer to be used for a transfer to/from the specified endpoint. +-

      +-

      Parameters:
      +- +- +- +- +- +-
      usb_ep The endpoint to be used with with the request
      bytes The desired number of bytes for the buffer
      dma Pointer to the buffer's DMA address; must be valid
      gfp_flags the GFP_* flags to use.
      +-
      +-
      Returns:
      address of a new buffer or null is buffer could not be allocated.
      +- +-

      +-Definition at line 246 of file dwc_otg_pcd_linux.c. +-

      +-

      +- +-

      +-
      +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
      static void dwc_otg_pcd_free_buffer (struct usb_ep *  usb_ep,
      void *  buf,
      dma_addr_t  dma,
      unsigned  bytes 
      ) [static]
      +-
      +-
      +- +-

      +-This function frees an I/O buffer that was allocated by alloc_buffer. +-

      +-

      Parameters:
      +- +- +- +- +- +-
      usb_ep the endpoint associated with the buffer
      buf address of the buffer
      dma The buffer's DMA address
      bytes The number of bytes of the buffer
      +-
      +- +-

      +-Definition at line 282 of file dwc_otg_pcd_linux.c. +-

      +-

      +- +-

      +-
      +- ++Definition at line 230 of file dwc_otg_pcd_linux.c. ++ ++
      ++

      ++ ++ ++ ++ ++
      ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
      static int ep_queue (struct usb_ep *  usb_ep, int ep_queue ( struct usb_ep *  usb_ep,
      struct usb_request *  usb_req, struct usb_request *  usb_req,
      gfp_t  gfp_flags gfp_t  gfp_flags
      ) [static])  [static]
      +- +-
      ++
      ++ ++ ++ ++
      ++   ++ + +

      + This function is used to submit an I/O Request to an EP. +@@ -456,33 +366,41 @@ +

    • When the request completes the request's completion callback is called to return the request to the driver.
    • An EP, except control EPs, may have multiple requests pending.
    • Once submitted the request cannot be examined or modified.
    • Each request is turned into one or more packets.
    • A BULK EP can queue any amount of data; the transfer is packetized.
    • Zero length Packets are specified with the request 'zero' flag.
      • + +

      +-Definition at line 308 of file dwc_otg_pcd_linux.c. +- +-

      +- +-

      +-
      +- ++Definition at line 317 of file dwc_otg_pcd_linux.c. ++ ++
      ++

      ++ ++ ++ ++ ++
      ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
      static int ep_halt (struct usb_ep *  usb_ep, int ep_halt ( struct usb_ep *  usb_ep,
      int  value int  value
      ) [static])  [static]
      +- +-
      ++
      ++ ++ ++ ++
      ++   ++ + +

      + usb_ep_set_halt stalls an endpoint. +@@ -499,39 +417,47 @@ + + +

      +-Definition at line 391 of file dwc_otg_pcd_linux.c. +- +-

      +- +-

      +-
      +- ++Definition at line 430 of file dwc_otg_pcd_linux.c. ++ ++
      ++

      ++ ++ ++ ++ ++
      ++ + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- +- ++ ++ ++ ++ + + +- +- +- ++ ++ ++ + +
      static int iso_ep_start (struct usb_ep *  usb_ep, int iso_ep_start ( struct usb_ep *  usb_ep,
      struct usb_iso_request *  req, struct usb_iso_request *  req,
      gfp_t  gfp_flags gfp_t  gfp_flags
      ) [static])  [static]
      +- +-
      ++
      ++ ++ ++ ++
      ++   ++ + +

      + This function is used to submit an ISOC Transfer Request to an EP. +@@ -540,112 +466,150 @@ +

    • Every time a sync period completes the request's completion callback is called to provide data to the gadget driver.
    • Once submitted the request cannot be modified.
    • Each request is turned into periodic data packets untill ISO Transfer is stopped..
      • + +

      +-Definition at line 422 of file dwc_otg_pcd_linux.c. +- +-

      +- +-

      +-
      +- +- +- +- +- +- +- +- ++Definition at line 461 of file dwc_otg_pcd_linux.c. ++ ++
      static int wakeup (struct usb_gadget *  gadget  )  [static]
      ++

      ++ ++ ++ ++ ++
      ++ ++ ++ ++ ++ ++ ++ ++ + +
      int wakeup ( struct usb_gadget *  gadget  )  [static]
      +- +-
      ++
      ++ ++ ++ ++
      ++   ++ + +

      + Initiates Session Request Protocol (SRP) to wakeup the host if no session is in progress. +

      + If a session is already in progress, but the device is suspended, remote wakeup signaling is started. +

      +-Definition at line 603 of file dwc_otg_pcd_linux.c. +- +-

      +- +-

      +-
      +- +- +- +- +- +- +- +- ++Definition at line 646 of file dwc_otg_pcd_linux.c. ++ ++
      void gadget_add_eps (struct gadget_wrapper *  d  ) 
      ++

      ++ ++ ++ ++ ++
      ++ ++ ++ ++ ++ ++ ++ ++ + +
      void gadget_add_eps ( struct gadget_wrapper *  d  ) 
      +- +-
      ++
      ++ ++ ++ ++
      ++   ++ + +

      + This function initialized the usb_ep structures to there default state. +

      +

      Parameters:
      + +- ++ +
      d Pointer on gadget_wrapper.
      d Pointer on gadget_wrapper.
      +
      +- +

      +-Initialize the EP0 structure.

      +-

      Todo:
      NGS: What should the max packet size be set to here? Before EP type is set?
      ++Initialize the EP0 structure.

      ++

      Todo:
      NGS: What should the max packet size be set to here? Before EP type is set?

      ++NGS: What should the max packet size be set to here? Before EP type is set?

      ++NGS: What should the max packet size be set to here? Before EP type is set?

      +

      +-Initialize the EP structures.

      +-

      Todo:
      NGS: What should the max packet size be set to here? Before EP type is set?
      ++Initialize the EP structures. +

      +-

      Todo:
      NGS: What should the max packet size be set to here? Before EP type is set?
      +- +-

      +-Definition at line 824 of file dwc_otg_pcd_linux.c. +- +-

      +- +-

      +-
      +- +- +- +- +- +- +- +- ++Definition at line 950 of file dwc_otg_pcd_linux.c. ++ ++
      static void dwc_otg_pcd_gadget_release (struct device *  dev  )  [static]
      ++

      ++ ++ ++ ++ ++
      ++ ++ ++ ++ ++ ++ ++ ++ + +
      void dwc_otg_pcd_gadget_release ( struct device *  dev  )  [static]
      +- +-
      ++
      ++ ++ ++ ++
      ++   ++ + +

      + This function releases the Gadget device. +

      + required by device_unregister().

      +-

      Todo:
      Should this do something? Should it free the PCD?
      ++
      Todo:
      Should this do something? Should it free the PCD?
      + +

      +-Definition at line 937 of file dwc_otg_pcd_linux.c. +- +-

      +- +-

      +-
      +- +- +- +- +- +- +- +- ++Definition at line 1067 of file dwc_otg_pcd_linux.c. ++ ++
      int usb_gadget_register_driver (struct usb_gadget_driver *  driver  ) 
      ++

      ++ ++ ++ ++ ++
      ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ + +
      int usb_gadget_probe_driver ( struct usb_gadget_driver *  driver,
      int(*)(struct usb_gadget *)  bind
      ) 
      +- +-
      ++
      ++ ++ ++ ++
      ++   ++ + +

      + This function registers a gadget driver with the PCD. +@@ -654,28 +618,37 @@ +

      Parameters:
      + + ++ +
      driver The driver being registered
      bind The bind function of gadget driver
      +
      + +

      +-Definition at line 1096 of file dwc_otg_pcd_linux.c. +- +-

      +- +-

      +-
      +- +- +- +- +- +- +- +- ++Definition at line 1234 of file dwc_otg_pcd_linux.c. ++ ++
      int usb_gadget_unregister_driver (struct usb_gadget_driver *  driver  ) 
      ++

      ++ ++ ++ ++ ++
      ++ ++ ++ ++ ++ ++ ++ ++ + +
      int usb_gadget_unregister_driver ( struct usb_gadget_driver *  driver  ) 
      +- +-
      ++
      ++ ++ ++ ++ ++ ++
      ++   ++ + +

      + This function unregisters a gadget driver. +@@ -687,65 +660,83 @@ + + +

      +-Definition at line 1143 of file dwc_otg_pcd_linux.c. +- +-

      ++Definition at line 1294 of file dwc_otg_pcd_linux.c.

      +

      Variable Documentation

      +- +-
      +-
      +- ++

      ++

      ++ ++ ++ ++
      ++ + +- ++ + +
      struct usb_isoc_ep_ops dwc_otg_pcd_ep_ops [static] struct usb_isoc_ep_ops dwc_otg_pcd_ep_ops [static]
      +- +-
      ++
      ++ ++ ++ ++
      ++   ++ + +

      + Initial value:

       {
+         .ep_ops = {
+-                   .enable = ep_enable,
+-                   .disable = ep_disable,
++                   .enable = ep_enable,
++                   .disable = ep_disable,
++
++                   .alloc_request = dwc_otg_pcd_alloc_request,
++                   .free_request = dwc_otg_pcd_free_request,
+ 
+-                   .alloc_request = dwc_otg_pcd_alloc_request,
+-                   .free_request = dwc_otg_pcd_free_request,
+ 
+-                   .alloc_buffer = dwc_otg_pcd_alloc_buffer,
+-                   .free_buffer = dwc_otg_pcd_free_buffer,
+ 
+-                   .queue = ep_queue,
+-                   .dequeue = ep_dequeue,
+ 
+-                   .set_halt = ep_halt,
++
++
++                   .queue = ep_queue,
++                   .dequeue = ep_dequeue,
++
++                   .set_halt = ep_halt,
+                    .fifo_status = 0,
+                    .fifo_flush = 0,
+                    },
+-        .iso_ep_start = iso_ep_start,
+-        .iso_ep_stop = iso_ep_stop,
+-        .alloc_iso_request = alloc_iso_request,
+-        .free_iso_request = free_iso_request,
++        .iso_ep_start = iso_ep_start,
++        .iso_ep_stop = iso_ep_stop,
++        .alloc_iso_request = alloc_iso_request,
++        .free_iso_request = free_iso_request,
+ }
+
      +

      +-Definition at line 507 of file dwc_otg_pcd_linux.c. +- +-

      +- +-

      +-
      +- ++Definition at line 546 of file dwc_otg_pcd_linux.c. ++ ++
      ++

      ++ ++ ++ ++ ++
      ++ + +- ++ + +
      struct usb_gadget_ops dwc_otg_pcd_ops [static] const struct usb_gadget_ops dwc_otg_pcd_ops [static]
      +- +-
      ++
      ++ ++ ++ ++
      ++   ++ + +

      + Initial value:

       {
+-        .get_frame = get_frame_number,
+-        .wakeup = wakeup,
++        .get_frame = get_frame_number,
++        .wakeup = wakeup,
+ 
+ 
+ 
+@@ -753,44 +744,55 @@
+ }
+
      +

      +-Definition at line 618 of file dwc_otg_pcd_linux.c. +- +-

      +- +-

      +-
      +- ++Definition at line 661 of file dwc_otg_pcd_linux.c. ++ ++
      ++

      ++ ++ ++ ++ ++
      ++ + +- ++ + +
      struct dwc_otg_pcd_function_ops fops [static] const struct dwc_otg_pcd_function_ops fops [static]
      +- +-
      ++
      ++ ++ ++ ++ ++ ++
      ++   ++ + +

      + Initial value:

       {
+-        .complete = _complete,
++        .complete = _complete,
++
++        .isoc_complete = _isoc_complete,
++
++        .setup = _setup,
++        .disconnect = _disconnect,
++        .connect = _connect,
++        .resume = _resume,
++        .suspend = _suspend,
++        .hnp_changed = _hnp_changed,
++        .reset = _reset,
++
+ 
+-        .isoc_complete = _isoc_complete,
+ 
+-        .setup = _setup,
+-        .disconnect = _disconnect,
+-        .connect = _connect,
+-        .resume = _resume,
+-        .suspend = _suspend,
+-        .hnp_changed = _hnp_changed,
+-        .reset = _reset,
+ 
+ 
+ 
+ }
+
      +

      +-Definition at line 786 of file dwc_otg_pcd_linux.c. +- +-

      +-

      Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++Definition at line 909 of file dwc_otg_pcd_linux.c.
      ++

      Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
      ++doxygen 1.3.9.1 + + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__regs_8h-source.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/dwc__otg__regs_8h-source.html 2013-07-26 19:31:22.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__regs_8h-source.html 2013-07-26 19:34:42.000000000 +0000 +@@ -2,1259 +2,1381 @@ + + DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_regs.h Source File + +- + +- +-
      +-
      +-
      +-
      +-

      dwc_otg_regs.h

      Go to the documentation of this file.
      00001 /* ==========================================================================
+-00002  * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_regs.h $
+-00003  * $Revision: #76 $
+-00004  * $Date: 2009/04/02 $
+-00005  * $Change: 1224216 $
+-00006  *
+-00007  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
+-00008  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
+-00009  * otherwise expressly agreed to in writing between Synopsys and you.
+-00010  * 
+-00011  * The Software IS NOT an item of Licensed Software or Licensed Product under
+-00012  * any End User Software License Agreement or Agreement for Licensed Product
+-00013  * with Synopsys or any supplement thereto. You are permitted to use and
+-00014  * redistribute this Software in source and binary forms, with or without
+-00015  * modification, provided that redistributions of source code must retain this
+-00016  * notice. You may not view, use, disclose, copy or distribute this file or
+-00017  * any information contained herein except pursuant to this license grant from
+-00018  * Synopsys. If you do not agree with this notice, including the disclaimer
+-00019  * below, then you are not authorized to use the Software.
+-00020  * 
+-00021  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
+-00022  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+-00023  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+-00024  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
+-00025  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+-00026  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+-00027  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+-00028  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+-00029  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+-00030  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+-00031  * DAMAGE.
+-00032  * ========================================================================== */
+-00033 
+-00034 #ifndef __DWC_OTG_REGS_H__
+-00035 #define __DWC_OTG_REGS_H__
+-00036 
+-00037 #include "dwc_otg_core_if.h"
+-00038 
+-00066 /****************************************************************************/
++
++
      Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
      
++
      dwc_otg_regs.h
      Go to the documentation of this file.
      00001 /* ==========================================================================
++00002  * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_regs.h $
++00003  * $Revision: #97 $
++00004  * $Date: 2011/10/24 $
++00005  * $Change: 1871160 $
++00006  *
++00007  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
++00008  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
++00009  * otherwise expressly agreed to in writing between Synopsys and you.
++00010  *
++00011  * The Software IS NOT an item of Licensed Software or Licensed Product under
++00012  * any End User Software License Agreement or Agreement for Licensed Product
++00013  * with Synopsys or any supplement thereto. You are permitted to use and
++00014  * redistribute this Software in source and binary forms, with or without
++00015  * modification, provided that redistributions of source code must retain this
++00016  * notice. You may not view, use, disclose, copy or distribute this file or
++00017  * any information contained herein except pursuant to this license grant from
++00018  * Synopsys. If you do not agree with this notice, including the disclaimer
++00019  * below, then you are not authorized to use the Software.
++00020  *
++00021  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
++00022  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++00023  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++00024  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
++00025  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++00026  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
++00027  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
++00028  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
++00029  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
++00030  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
++00031  * DAMAGE.
++00032  * ========================================================================== */
++00033 
++00034 #ifndef __DWC_OTG_REGS_H__
++00035 #define __DWC_OTG_REGS_H__
++00036 
++00037 #include "dwc_otg_core_if.h"
++00038 
++00066 /****************************************************************************/
+ 00071 typedef struct dwc_otg_core_global_regs {
+-00073         volatile uint32_t gotgctl;
+-00075         volatile uint32_t gotgint;
+-00077         volatile uint32_t gahbcfg;
+-00078 
+-00079 #define DWC_GLBINTRMASK         0x0001
+-00080 #define DWC_DMAENABLE           0x0020
+-00081 #define DWC_NPTXEMPTYLVL_EMPTY  0x0080
+-00082 #define DWC_NPTXEMPTYLVL_HALFEMPTY      0x0000
+-00083 #define DWC_PTXEMPTYLVL_EMPTY   0x0100
+-00084 #define DWC_PTXEMPTYLVL_HALFEMPTY       0x0000
+-00085 
+-00087         volatile uint32_t gusbcfg;
+-00089         volatile uint32_t grstctl;
+-00091         volatile uint32_t gintsts;
+-00093         volatile uint32_t gintmsk;
+-00095         volatile uint32_t grxstsr;
+-00097         volatile uint32_t grxstsp;
+-00099         volatile uint32_t grxfsiz;
+-00101         volatile uint32_t gnptxfsiz;
+-00104         volatile uint32_t gnptxsts;
+-00106         volatile uint32_t gi2cctl;
+-00108         volatile uint32_t gpvndctl;
+-00110         volatile uint32_t ggpio;
+-00112         volatile uint32_t guid;
+-00114         volatile uint32_t gsnpsid;
+-00116         volatile uint32_t ghwcfg1;
+-00118         volatile uint32_t ghwcfg2;
+-00119 #define DWC_SLAVE_ONLY_ARCH 0
+-00120 #define DWC_EXT_DMA_ARCH 1
+-00121 #define DWC_INT_DMA_ARCH 2
+-00122 
+-00123 #define DWC_MODE_HNP_SRP_CAPABLE        0
+-00124 #define DWC_MODE_SRP_ONLY_CAPABLE       1
+-00125 #define DWC_MODE_NO_HNP_SRP_CAPABLE             2
+-00126 #define DWC_MODE_SRP_CAPABLE_DEVICE             3
+-00127 #define DWC_MODE_NO_SRP_CAPABLE_DEVICE  4
+-00128 #define DWC_MODE_SRP_CAPABLE_HOST       5
+-00129 #define DWC_MODE_NO_SRP_CAPABLE_HOST    6
+-00130 
+-00132         volatile uint32_t ghwcfg3;
+-00134         volatile uint32_t ghwcfg4;
+-00136         volatile uint32_t glpmcfg;
+-00138         volatile uint32_t reserved[42];
+-00140         volatile uint32_t hptxfsiz;
+-00144         volatile uint32_t dptxfsiz_dieptxf[15];
+-00145 } dwc_otg_core_global_regs_t;
+-00146 
+-00152 typedef union gotgctl_data {
+-00154         uint32_t d32;
+-00156         struct {
+-00157                 unsigned sesreqscs:1;
+-00158                 unsigned sesreq:1;
+-00159                 unsigned reserved2_7:6;
+-00160                 unsigned hstnegscs:1;
+-00161                 unsigned hnpreq:1;
+-00162                 unsigned hstsethnpen:1;
+-00163                 unsigned devhnpen:1;
+-00164                 unsigned reserved12_15:4;
+-00165                 unsigned conidsts:1;
+-00166                 unsigned reserved17:1;
+-00167                 unsigned asesvld:1;
+-00168                 unsigned bsesvld:1;
+-00169                 unsigned currmod:1;
+-00170                 unsigned reserved21_31:11;
+-00171         } b;
+-00172 } gotgctl_data_t;
+-00173 
+-00179 typedef union gotgint_data {
+-00181         uint32_t d32;
+-00183         struct {
+-00185                 unsigned reserved0_1:2;
+-00186 
+-00188                 unsigned sesenddet:1;
+-00189 
+-00190                 unsigned reserved3_7:5;
+-00191 
+-00193                 unsigned sesreqsucstschng:1;
+-00195                 unsigned hstnegsucstschng:1;
+-00196 
+-00197                 unsigned reserver10_16:7;
+-00198 
+-00200                 unsigned hstnegdet:1;
+-00202                 unsigned adevtoutchng:1;
+-00204                 unsigned debdone:1;
+-00205 
+-00206                 unsigned reserved31_20:12;
+-00207 
+-00208         } b;
+-00209 } gotgint_data_t;
+-00210 
+-00216 typedef union gahbcfg_data {
+-00218         uint32_t d32;
+-00220         struct {
+-00221                 unsigned glblintrmsk:1;
+-00222 #define DWC_GAHBCFG_GLBINT_ENABLE               1
+-00223 
+-00224                 unsigned hburstlen:4;
+-00225 #define DWC_GAHBCFG_INT_DMA_BURST_SINGLE        0
+-00226 #define DWC_GAHBCFG_INT_DMA_BURST_INCR          1
+-00227 #define DWC_GAHBCFG_INT_DMA_BURST_INCR4         3
+-00228 #define DWC_GAHBCFG_INT_DMA_BURST_INCR8         5
+-00229 #define DWC_GAHBCFG_INT_DMA_BURST_INCR16        7
+-00230 
+-00231                 unsigned dmaenable:1;
+-00232 #define DWC_GAHBCFG_DMAENABLE                   1
+-00233                 unsigned reserved:1;
+-00234                 unsigned nptxfemplvl_txfemplvl:1;
+-00235                 unsigned ptxfemplvl:1;
+-00236 #define DWC_GAHBCFG_TXFEMPTYLVL_EMPTY           1
+-00237 #define DWC_GAHBCFG_TXFEMPTYLVL_HALFEMPTY       0
+-00238                 unsigned reserved9_31:23;
+-00239         } b;
+-00240 } gahbcfg_data_t;
+-00241 
+-00247 typedef union gusbcfg_data {
+-00249         uint32_t d32;
+-00251         struct {
+-00252                 unsigned toutcal:3;
+-00253                 unsigned phyif:1;
+-00254                 unsigned ulpi_utmi_sel:1;
+-00255                 unsigned fsintf:1;
+-00256                 unsigned physel:1;
+-00257                 unsigned ddrsel:1;
+-00258                 unsigned srpcap:1;
+-00259                 unsigned hnpcap:1;
+-00260                 unsigned usbtrdtim:4;
+-00261                 unsigned nptxfrwnden:1;
+-00262                 unsigned phylpwrclksel:1;
+-00263                 unsigned otgutmifssel:1;
+-00264                 unsigned ulpi_fsls:1;
+-00265                 unsigned ulpi_auto_res:1;
+-00266                 unsigned ulpi_clk_sus_m:1;
+-00267                 unsigned ulpi_ext_vbus_drv:1;
+-00268                 unsigned ulpi_int_vbus_indicator:1;
+-00269                 unsigned term_sel_dl_pulse:1;
+-00270                 unsigned reserved23_25:3;
+-00271                 unsigned ic_usb_cap:1;
+-00272                 unsigned ic_traffic_pull_remove:1;
+-00273                 unsigned tx_end_delay:1;
+-00274                 unsigned reserved29_31:3;
+-00275         } b;
+-00276 } gusbcfg_data_t;
+-00277 
+-00283 typedef union glpmctl_data {
+-00285         uint32_t d32;
+-00287         struct {
+-00292                 unsigned lpm_cap_en:1;
+-00297                 unsigned appl_resp:1;
+-00306                 unsigned hird:4;
+-00315                 unsigned rem_wkup_en:1;
+-00320                 unsigned en_utmi_sleep:1;
+-00323                 unsigned hird_thres:5;
+-00334                 unsigned lpm_resp:2;
+-00339                 unsigned prt_sleep_sts:1;
+-00344                 unsigned sleep_state_resumeok:1;
+-00350                 unsigned lpm_chan_index:4;
+-00355                 unsigned retry_count:3;
+-00361                 unsigned send_lpm:1;
+-00366                 unsigned retry_count_sts:3;
+-00367                 unsigned reserved28_29:2;
+-00375                 unsigned hsic_connect:1;
+-00379                 unsigned inv_sel_hsic:1;
+-00380         } b;
+-00381 } glpmcfg_data_t;
+-00382 
+-00388 typedef union grstctl_data {
+-00390         uint32_t d32;
+-00392         struct {
+-00428                 unsigned csftrst:1;
+-00435                 unsigned hsftrst:1;
+-00444                 unsigned hstfrm:1;
+-00448                 unsigned intknqflsh:1;
+-00463                 unsigned rxfflsh:1;
+-00478                 unsigned txfflsh:1;
+-00479 
+-00495                 unsigned txfnum:5;
+-00497                 unsigned reserved11_29:19;
+-00500                 unsigned dmareq:1;
+-00503                 unsigned ahbidle:1;
+-00504         } b;
+-00505 } grstctl_t;
+-00506 
+-00512 typedef union gintmsk_data {
+-00514         uint32_t d32;
+-00516         struct {
+-00517                 unsigned reserved0:1;
+-00518                 unsigned modemismatch:1;
+-00519                 unsigned otgintr:1;
+-00520                 unsigned sofintr:1;
+-00521                 unsigned rxstsqlvl:1;
+-00522                 unsigned nptxfempty:1;
+-00523                 unsigned ginnakeff:1;
+-00524                 unsigned goutnakeff:1;
+-00525                 unsigned reserved8:1;
+-00526                 unsigned i2cintr:1;
+-00527                 unsigned erlysuspend:1;
+-00528                 unsigned usbsuspend:1;
+-00529                 unsigned usbreset:1;
+-00530                 unsigned enumdone:1;
+-00531                 unsigned isooutdrop:1;
+-00532                 unsigned eopframe:1;
+-00533                 unsigned reserved16:1;
+-00534                 unsigned epmismatch:1;
+-00535                 unsigned inepintr:1;
+-00536                 unsigned outepintr:1;
+-00537                 unsigned incomplisoin:1;
+-00538                 unsigned incomplisoout:1;
+-00539                 unsigned reserved22_23:2;
+-00540                 unsigned portintr:1;
+-00541                 unsigned hcintr:1;
+-00542                 unsigned ptxfempty:1;
+-00543                 unsigned lpmtranrcvd:1;
+-00544                 unsigned conidstschng:1;
+-00545                 unsigned disconnect:1;
+-00546                 unsigned sessreqintr:1;
+-00547                 unsigned wkupintr:1;
+-00548         } b;
+-00549 } gintmsk_data_t;
+-00555 typedef union gintsts_data {
+-00557         uint32_t d32;
+-00558 #define DWC_SOF_INTR_MASK 0x0008
+-00559 
+-00560         struct {
+-00561 #define DWC_HOST_MODE 1
+-00562                 unsigned curmode:1;
+-00563                 unsigned modemismatch:1;
+-00564                 unsigned otgintr:1;
+-00565                 unsigned sofintr:1;
+-00566                 unsigned rxstsqlvl:1;
+-00567                 unsigned nptxfempty:1;
+-00568                 unsigned ginnakeff:1;
+-00569                 unsigned goutnakeff:1;
+-00570                 unsigned reserved8:1;
+-00571                 unsigned i2cintr:1;
+-00572                 unsigned erlysuspend:1;
+-00573                 unsigned usbsuspend:1;
+-00574                 unsigned usbreset:1;
+-00575                 unsigned enumdone:1;
+-00576                 unsigned isooutdrop:1;
+-00577                 unsigned eopframe:1;
+-00578                 unsigned intokenrx:1;
+-00579                 unsigned epmismatch:1;
+-00580                 unsigned inepint:1;
+-00581                 unsigned outepintr:1;
+-00582                 unsigned incomplisoin:1;
+-00583                 unsigned incomplisoout:1;
+-00584                 unsigned reserved22_23:2;
+-00585                 unsigned portintr:1;
+-00586                 unsigned hcintr:1;
+-00587                 unsigned ptxfempty:1;
+-00588                 unsigned lpmtranrcvd:1;
+-00589                 unsigned conidstschng:1;
+-00590                 unsigned disconnect:1;
+-00591                 unsigned sessreqintr:1;
+-00592                 unsigned wkupintr:1;
+-00593         } b;
+-00594 } gintsts_data_t;
+-00595 
+-00601 typedef union device_grxsts_data {
+-00603         uint32_t d32;
+-00605         struct {
+-00606                 unsigned epnum:4;
+-00607                 unsigned bcnt:11;
+-00608                 unsigned dpid:2;
+-00609 
+-00610 #define DWC_STS_DATA_UPDT               0x2     // OUT Data Packet
+-00611 #define DWC_STS_XFER_COMP               0x3     // OUT Data Transfer Complete
+-00612 
+-00613 #define DWC_DSTS_GOUT_NAK               0x1     // Global OUT NAK
+-00614 #define DWC_DSTS_SETUP_COMP             0x4     // Setup Phase Complete
+-00615 #define DWC_DSTS_SETUP_UPDT 0x6 // SETUP Packet
+-00616                 unsigned pktsts:4;
+-00617                 unsigned fn:4;
+-00618                 unsigned reserved:7;
+-00619         } b;
+-00620 } device_grxsts_data_t;
+-00621 
+-00627 typedef union host_grxsts_data {
+-00629         uint32_t d32;
+-00631         struct {
+-00632                 unsigned chnum:4;
+-00633                 unsigned bcnt:11;
+-00634                 unsigned dpid:2;
+-00635 
+-00636                 unsigned pktsts:4;
+-00637 #define DWC_GRXSTS_PKTSTS_IN                      0x2
+-00638 #define DWC_GRXSTS_PKTSTS_IN_XFER_COMP    0x3
+-00639 #define DWC_GRXSTS_PKTSTS_DATA_TOGGLE_ERR 0x5
+-00640 #define DWC_GRXSTS_PKTSTS_CH_HALTED               0x7
+-00641 
+-00642                 unsigned reserved:11;
+-00643         } b;
+-00644 } host_grxsts_data_t;
+-00645 
+-00651 typedef union fifosize_data {
+-00653         uint32_t d32;
+-00655         struct {
+-00656                 unsigned startaddr:16;
+-00657                 unsigned depth:16;
+-00658         } b;
+-00659 } fifosize_data_t;
+-00660 
+-00667 typedef union gnptxsts_data {
+-00669         uint32_t d32;
+-00671         struct {
+-00672                 unsigned nptxfspcavail:16;
+-00673                 unsigned nptxqspcavail:8;
+-00684                 unsigned nptxqtop_terminate:1;
+-00685                 unsigned nptxqtop_token:2;
+-00686                 unsigned nptxqtop_chnep:4;
+-00687                 unsigned reserved:1;
+-00688         } b;
+-00689 } gnptxsts_data_t;
+-00690 
+-00697 typedef union dtxfsts_data {
+-00699         uint32_t d32;
+-00701         struct {
+-00702                 unsigned txfspcavail:16;
+-00703                 unsigned reserved:16;
+-00704         } b;
+-00705 } dtxfsts_data_t;
+-00706 
+-00712 typedef union gi2cctl_data {
+-00714         uint32_t d32;
+-00716         struct {
+-00717                 unsigned rwdata:8;
+-00718                 unsigned regaddr:8;
+-00719                 unsigned addr:7;
+-00720                 unsigned i2cen:1;
+-00721                 unsigned ack:1;
+-00722                 unsigned i2csuspctl:1;
+-00723                 unsigned i2cdevaddr:2;
+-00724                 unsigned reserved:2;
+-00725                 unsigned rw:1;
+-00726                 unsigned bsydne:1;
+-00727         } b;
+-00728 } gi2cctl_data_t;
+-00729 
+-00735 typedef union hwcfg1_data {
+-00737         uint32_t d32;
+-00739         struct {
+-00740                 unsigned ep_dir0:2;
+-00741                 unsigned ep_dir1:2;
+-00742                 unsigned ep_dir2:2;
+-00743                 unsigned ep_dir3:2;
+-00744                 unsigned ep_dir4:2;
+-00745                 unsigned ep_dir5:2;
+-00746                 unsigned ep_dir6:2;
+-00747                 unsigned ep_dir7:2;
+-00748                 unsigned ep_dir8:2;
+-00749                 unsigned ep_dir9:2;
+-00750                 unsigned ep_dir10:2;
+-00751                 unsigned ep_dir11:2;
+-00752                 unsigned ep_dir12:2;
+-00753                 unsigned ep_dir13:2;
+-00754                 unsigned ep_dir14:2;
+-00755                 unsigned ep_dir15:2;
+-00756         } b;
+-00757 } hwcfg1_data_t;
+-00758 
+-00764 typedef union hwcfg2_data {
+-00766         uint32_t d32;
+-00768         struct {
+-00769                 /* GHWCFG2 */
+-00770                 unsigned op_mode:3;
+-00771 #define DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG 0
+-00772 #define DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG 1
+-00773 #define DWC_HWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE_OTG 2
+-00774 #define DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE 3
+-00775 #define DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE 4
+-00776 #define DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST 5
+-00777 #define DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST 6
+-00778 
+-00779                 unsigned architecture:2;
+-00780                 unsigned point2point:1;
+-00781                 unsigned hs_phy_type:2;
+-00782 #define DWC_HWCFG2_HS_PHY_TYPE_NOT_SUPPORTED 0
+-00783 #define DWC_HWCFG2_HS_PHY_TYPE_UTMI 1
+-00784 #define DWC_HWCFG2_HS_PHY_TYPE_ULPI 2
+-00785 #define DWC_HWCFG2_HS_PHY_TYPE_UTMI_ULPI 3
+-00786 
+-00787                 unsigned fs_phy_type:2;
+-00788                 unsigned num_dev_ep:4;
+-00789                 unsigned num_host_chan:4;
+-00790                 unsigned perio_ep_supported:1;
+-00791                 unsigned dynamic_fifo:1;
+-00792                 unsigned multi_proc_int:1;
+-00793                 unsigned reserved21:1;
+-00794                 unsigned nonperio_tx_q_depth:2;
+-00795                 unsigned host_perio_tx_q_depth:2;
+-00796                 unsigned dev_token_q_depth:5;
+-00797                 unsigned reserved31:1;
+-00798         } b;
+-00799 } hwcfg2_data_t;
+-00800 
+-00806 typedef union hwcfg3_data {
+-00808         uint32_t d32;
+-00810         struct {
+-00811                 /* GHWCFG3 */
+-00812                 unsigned xfer_size_cntr_width:4;
+-00813                 unsigned packet_size_cntr_width:3;
+-00814                 unsigned otg_func:1;
+-00815                 unsigned i2c:1;
+-00816                 unsigned vendor_ctrl_if:1;
+-00817                 unsigned optional_features:1;
+-00818                 unsigned synch_reset_type:1;
+-00819                 unsigned otg_enable_ic_usb:1;
+-00820                 unsigned otg_enable_hsic:1;
+-00821                 unsigned reserved14:1;
+-00822                 unsigned otg_lpm_en:1;
+-00823                 unsigned dfifo_depth:16;
+-00824         } b;
+-00825 } hwcfg3_data_t;
+-00826 
+-00832 typedef union hwcfg4_data {
+-00834         uint32_t d32;
+-00836         struct {
+-00837                 unsigned num_dev_perio_in_ep:4;
+-00838                 unsigned power_optimiz:1;
+-00839                 unsigned min_ahb_freq:9;
+-00840                 unsigned utmi_phy_data_width:2;
+-00841                 unsigned num_dev_mode_ctrl_ep:4;
+-00842                 unsigned iddig_filt_en:1;
+-00843                 unsigned vbus_valid_filt_en:1;
+-00844                 unsigned a_valid_filt_en:1;
+-00845                 unsigned b_valid_filt_en:1;
+-00846                 unsigned session_end_filt_en:1;
+-00847                 unsigned ded_fifo_en:1;
+-00848                 unsigned num_in_eps:4;
+-00849                 unsigned desc_dma:1;
+-00850                 unsigned desc_dma_dyn:1;
+-00851         } b;
+-00852 } hwcfg4_data_t;
+-00853 
+-00855 // Device Registers
+-00865 typedef struct dwc_otg_dev_global_regs {
+-00867         volatile uint32_t dcfg;
+-00869         volatile uint32_t dctl;
+-00871         volatile uint32_t dsts;
+-00873         uint32_t unused;
+-00876         volatile uint32_t diepmsk;
+-00879         volatile uint32_t doepmsk;
+-00881         volatile uint32_t daint;
+-00884         volatile uint32_t daintmsk;
+-00887         volatile uint32_t dtknqr1;
+-00890         volatile uint32_t dtknqr2;
+-00892         volatile uint32_t dvbusdis;
+-00894         volatile uint32_t dvbuspulse;
+-00898         volatile uint32_t dtknqr3_dthrctl;
+-00902         volatile uint32_t dtknqr4_fifoemptymsk;
+-00905         volatile uint32_t deachint;
+-00908         volatile uint32_t deachintmsk;
+-00911         volatile uint32_t diepeachintmsk[MAX_EPS_CHANNELS];
+-00914         volatile uint32_t doepeachintmsk[MAX_EPS_CHANNELS];
+-00915 } dwc_otg_device_global_regs_t;
+-00916 
+-00923 typedef union dcfg_data {
+-00925         uint32_t d32;
+-00927         struct {
+-00929                 unsigned devspd:2;
+-00931                 unsigned nzstsouthshk:1;
+-00932 #define DWC_DCFG_SEND_STALL 1
+-00933 
+-00934                 unsigned reserved3:1;
+-00936                 unsigned devaddr:7;
+-00938                 unsigned perfrint:2;
+-00939 #define DWC_DCFG_FRAME_INTERVAL_80 0
+-00940 #define DWC_DCFG_FRAME_INTERVAL_85 1
+-00941 #define DWC_DCFG_FRAME_INTERVAL_90 2
+-00942 #define DWC_DCFG_FRAME_INTERVAL_95 3
+-00943 
+-00944                 unsigned reserved13_17:5;
+-00946                 unsigned epmscnt:5;
+-00948                 unsigned descdma:1;
+-00949         } b;
+-00950 } dcfg_data_t;
+-00951 
+-00957 typedef union dctl_data {
+-00959         uint32_t d32;
+-00961         struct {
+-00963                 unsigned rmtwkupsig:1;
+-00965                 unsigned sftdiscon:1;
+-00967                 unsigned gnpinnaksts:1;
+-00969                 unsigned goutnaksts:1;
+-00971                 unsigned tstctl:3;
+-00973                 unsigned sgnpinnak:1;
+-00975                 unsigned cgnpinnak:1;
+-00977                 unsigned sgoutnak:1;
+-00979                 unsigned cgoutnak:1;
+-00980 
+-00982                 unsigned pwronprgdone:1;
+-00984                 unsigned gcontbna:1;
+-00986                 unsigned gmc:2;
+-00988                 unsigned ifrmnum:1;
+-00990                 unsigned nakonbble:1;
+-00991 
+-00992                 unsigned reserved17_31:15;
+-00993         } b;
+-00994 } dctl_data_t;
+-00995 
+-01001 typedef union dsts_data {
+-01003         uint32_t d32;
+-01005         struct {
+-01007                 unsigned suspsts:1;
+-01009                 unsigned enumspd:2;
+-01010 #define DWC_DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ 0
+-01011 #define DWC_DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ 1
+-01012 #define DWC_DSTS_ENUMSPD_LS_PHY_6MHZ               2
+-01013 #define DWC_DSTS_ENUMSPD_FS_PHY_48MHZ              3
+-01014 
+-01015                 unsigned errticerr:1;
+-01016                 unsigned reserved4_7:4;
+-01018                 unsigned soffn:14;
+-01019                 unsigned reserved22_31:10;
+-01020         } b;
+-01021 } dsts_data_t;
+-01022 
+-01030 typedef union diepint_data {
+-01032         uint32_t d32;
+-01034         struct {
+-01036                 unsigned xfercompl:1;
+-01038                 unsigned epdisabled:1;
+-01040                 unsigned ahberr:1;
+-01042                 unsigned timeout:1;
+-01044                 unsigned intktxfemp:1;
+-01046                 unsigned intknepmis:1;
+-01048                 unsigned inepnakeff:1;
+-01050                 unsigned emptyintr:1;
+-01051 
+-01052                 unsigned txfifoundrn:1;
+-01053 
+-01055                 unsigned bna:1;
+-01056 
+-01057                 unsigned reserved10_12:3;
+-01059                 unsigned nak:1;
+-01060 
+-01061                 unsigned reserved14_31:18;
+-01062         } b;
+-01063 } diepint_data_t;
+-01064 
+-01069 typedef union diepint_data diepmsk_data_t;
+-01070 
+-01078 typedef union doepint_data {
+-01080         uint32_t d32;
+-01082         struct {
+-01084                 unsigned xfercompl:1;
+-01086                 unsigned epdisabled:1;
+-01088                 unsigned ahberr:1;
+-01090                 unsigned setup:1;
+-01092                 unsigned outtknepdis:1;
+-01093 
+-01094                 unsigned stsphsercvd:1;
+-01096                 unsigned back2backsetup:1;
+-01097 
+-01098                 unsigned reserved7:1;
+-01100                 unsigned outpkterr:1;
+-01102                 unsigned bna:1;
+-01103 
+-01104                 unsigned reserved10:1;
+-01106                 unsigned pktdrpsts:1;
+-01108                 unsigned babble:1;
+-01110                 unsigned nak:1;
+-01112                 unsigned nyet:1;
+-01113 
+-01114                 unsigned reserved15_31:17;
+-01115         } b;
+-01116 } doepint_data_t;
+-01117 
+-01122 typedef union doepint_data doepmsk_data_t;
+-01123 
+-01130 typedef union daint_data {
+-01132         uint32_t d32;
+-01134         struct {
+-01136                 unsigned in:16;
+-01138                 unsigned out:16;
+-01139         } ep;
+-01140         struct {
+-01142                 unsigned inep0:1;
+-01143                 unsigned inep1:1;
+-01144                 unsigned inep2:1;
+-01145                 unsigned inep3:1;
+-01146                 unsigned inep4:1;
+-01147                 unsigned inep5:1;
+-01148                 unsigned inep6:1;
+-01149                 unsigned inep7:1;
+-01150                 unsigned inep8:1;
+-01151                 unsigned inep9:1;
+-01152                 unsigned inep10:1;
+-01153                 unsigned inep11:1;
+-01154                 unsigned inep12:1;
+-01155                 unsigned inep13:1;
+-01156                 unsigned inep14:1;
+-01157                 unsigned inep15:1;
+-01159                 unsigned outep0:1;
+-01160                 unsigned outep1:1;
+-01161                 unsigned outep2:1;
+-01162                 unsigned outep3:1;
+-01163                 unsigned outep4:1;
+-01164                 unsigned outep5:1;
+-01165                 unsigned outep6:1;
+-01166                 unsigned outep7:1;
+-01167                 unsigned outep8:1;
+-01168                 unsigned outep9:1;
+-01169                 unsigned outep10:1;
+-01170                 unsigned outep11:1;
+-01171                 unsigned outep12:1;
+-01172                 unsigned outep13:1;
+-01173                 unsigned outep14:1;
+-01174                 unsigned outep15:1;
+-01175         } b;
+-01176 } daint_data_t;
+-01177 
+-01184 typedef union dtknq1_data {
+-01186         uint32_t d32;
+-01188         struct {
+-01190                 unsigned intknwptr:5;
+-01192                 unsigned reserved05_06:2;
+-01194                 unsigned wrap_bit:1;
+-01196                 unsigned epnums0_5:24;
+-01197         } b;
+-01198 } dtknq1_data_t;
+-01199 
+-01205 typedef union dthrctl_data {
+-01207         uint32_t d32;
+-01209         struct {
+-01211                 unsigned non_iso_thr_en:1;
+-01213                 unsigned iso_thr_en:1;
+-01215                 unsigned tx_thr_len:9;
+-01217                 unsigned ahb_thr_ratio:2;
+-01219                 unsigned reserved13_15:3;
+-01221                 unsigned rx_thr_en:1;
+-01223                 unsigned rx_thr_len:9;
+-01225                 unsigned reserved26_31:6;
+-01226         } b;
+-01227 } dthrctl_data_t;
+-01228 
+-01239 typedef struct dwc_otg_dev_in_ep_regs {
+-01242         volatile uint32_t diepctl;
+-01244         uint32_t reserved04;
+-01247         volatile uint32_t diepint;
+-01249         uint32_t reserved0C;
+-01252         volatile uint32_t dieptsiz;
+-01255         volatile uint32_t diepdma;
+-01258         volatile uint32_t dtxfsts;
+-01261         volatile uint32_t diepdmab;
+-01262 } dwc_otg_dev_in_ep_regs_t;
+-01263 
+-01274 typedef struct dwc_otg_dev_out_ep_regs {
+-01277         volatile uint32_t doepctl;
+-01280         volatile uint32_t doepfn;
+-01283         volatile uint32_t doepint;
+-01285         uint32_t reserved0C;
+-01288         volatile uint32_t doeptsiz;
+-01291         volatile uint32_t doepdma;
+-01293         uint32_t unused;
+-01296         uint32_t doepdmab;
+-01297 } dwc_otg_dev_out_ep_regs_t;
+-01298 
+-01304 typedef union depctl_data {
+-01306         uint32_t d32;
+-01308         struct {
+-01316                 unsigned mps:11;
+-01317 #define DWC_DEP0CTL_MPS_64       0
+-01318 #define DWC_DEP0CTL_MPS_32       1
+-01319 #define DWC_DEP0CTL_MPS_16       2
+-01320 #define DWC_DEP0CTL_MPS_8        3
+-01321 
+-01325                 unsigned nextep:4;
+-01326 
+-01328                 unsigned usbactep:1;
+-01329 
+-01344                 unsigned dpid:1;
+-01345 
+-01347                 unsigned naksts:1;
+-01348 
+-01354                 unsigned eptype:2;
+-01355 
+-01359                 unsigned snp:1;
+-01360 
+-01362                 unsigned stall:1;
+-01363 
+-01367                 unsigned txfnum:4;
+-01368 
+-01370                 unsigned cnak:1;
+-01372                 unsigned snak:1;
+-01381                 unsigned setd0pid:1;
+-01389                 unsigned setd1pid:1;
+-01390 
+-01392                 unsigned epdis:1;
+-01394                 unsigned epena:1;
+-01395         } b;
+-01396 } depctl_data_t;
+-01397 
+-01403 typedef union deptsiz_data {
+-01405         uint32_t d32;
+-01407         struct {
+-01409                 unsigned xfersize:19;
+-01411                 unsigned pktcnt:10;
+-01413                 unsigned mc:2;
+-01414                 unsigned reserved:1;
+-01415         } b;
+-01416 } deptsiz_data_t;
+-01417 
+-01423 typedef union deptsiz0_data {
+-01425         uint32_t d32;
+-01427         struct {
+-01429                 unsigned xfersize:7;
+-01431                 unsigned reserved7_18:12;
+-01433                 unsigned pktcnt:1;
+-01435                 unsigned reserved20_28:9;
+-01437                 unsigned supcnt:2;
+-01438                 unsigned reserved31;
+-01439         } b;
+-01440 } deptsiz0_data_t;
+-01441 
+-01443 // DMA Descriptor Specific Structures
+-01444 //
+-01445 
+-01448 #define BS_HOST_READY   0x0
+-01449 #define BS_DMA_BUSY             0x1
+-01450 #define BS_DMA_DONE             0x2
+-01451 #define BS_HOST_BUSY    0x3
+-01452 
+-01455 #define RTS_SUCCESS             0x0
+-01456 #define RTS_BUFFLUSH    0x1
+-01457 #define RTS_RESERVED    0x2
+-01458 #define RTS_BUFERR              0x3
+-01459 
+-01466 typedef union dev_dma_desc_sts {
+-01468         uint32_t d32;
+-01470         struct {
+-01472                 unsigned bytes:16;
+-01473 
+-01474                 unsigned reserved16_22:7;
+-01476                 unsigned mtrf:1;
+-01478                 unsigned sr:1;
+-01480                 unsigned ioc:1;
+-01482                 unsigned sp:1;
+-01484                 unsigned l:1;
+-01486                 unsigned sts:2;
+-01488                 unsigned bs:2;
+-01489         } b;
+-01490 
+-01491 #ifdef DWC_EN_ISOC
+-01492 
+-01493         struct {
+-01495                 unsigned rxbytes:11;
+-01496 
+-01497                 unsigned reserved11:1;
+-01499                 unsigned framenum:11;
+-01501                 unsigned pid:2;
+-01503                 unsigned ioc:1;
+-01505                 unsigned sp:1;
+-01507                 unsigned l:1;
+-01509                 unsigned rxsts:2;
+-01511                 unsigned bs:2;
+-01512         } b_iso_out;
+-01513 
+-01515         struct {
+-01517                 unsigned txbytes:12;
+-01519                 unsigned framenum:11;
+-01521                 unsigned pid:2;
+-01523                 unsigned ioc:1;
+-01525                 unsigned sp:1;
+-01527                 unsigned l:1;
+-01529                 unsigned txsts:2;
+-01531                 unsigned bs:2;
+-01532         } b_iso_in;
+-01533 #endif                          /* DWC_EN_ISOC */
+-01534 } dev_dma_desc_sts_t;
+-01535 
+-01542 typedef struct dwc_otg_dev_dma_desc {
+-01544         dev_dma_desc_sts_t status;
+-01546         uint32_t buf;
+-01547 } dwc_otg_dev_dma_desc_t;
+-01548 
+-01554 typedef struct dwc_otg_dev_if {
+-01558         dwc_otg_device_global_regs_t *dev_global_regs;
+-01559 #define DWC_DEV_GLOBAL_REG_OFFSET 0x800
+-01560 
+-01564         dwc_otg_dev_in_ep_regs_t *in_ep_regs[MAX_EPS_CHANNELS];
+-01565 #define DWC_DEV_IN_EP_REG_OFFSET 0x900
+-01566 #define DWC_EP_REG_OFFSET 0x20
+-01567 
+-01569         dwc_otg_dev_out_ep_regs_t *out_ep_regs[MAX_EPS_CHANNELS];
+-01570 #define DWC_DEV_OUT_EP_REG_OFFSET 0xB00
+-01571 
+-01572         /* Device configuration information */
+-01573         uint8_t speed;                           
+-01574         uint8_t num_in_eps;              
+-01575         uint8_t num_out_eps;             
+-01578         uint16_t perio_tx_fifo_size[MAX_PERIO_FIFOS];
+-01579 
+-01581         uint16_t tx_fifo_size[MAX_TX_FIFOS];
+-01582 
+-01584         uint16_t rx_thr_en;
+-01585         uint16_t iso_tx_thr_en;
+-01586         uint16_t non_iso_tx_thr_en;
+-01587 
+-01588         uint16_t rx_thr_length;
+-01589         uint16_t tx_thr_length;
+-01590 
+-01597         dwc_dma_t dma_setup_desc_addr[2];
+-01598         dwc_otg_dev_dma_desc_t *setup_desc_addr[2];
+-01599 
+-01601         dwc_otg_dev_dma_desc_t *psetup;
+-01602 
+-01604         uint32_t setup_desc_index;
+-01605 
+-01607         dwc_dma_t dma_in_desc_addr;
+-01608         dwc_otg_dev_dma_desc_t *in_desc_addr;
+-01609 
+-01611         dwc_dma_t dma_out_desc_addr;
+-01612         dwc_otg_dev_dma_desc_t *out_desc_addr;
+-01613 
+-01615         uint32_t spd;
+-01616 
+-01617 } dwc_otg_dev_if_t;
+-01618 
+-01620 // Host Mode Register Structures
+-01621 //
+-01627 typedef struct dwc_otg_host_global_regs {
+-01629         volatile uint32_t hcfg;
+-01631         volatile uint32_t hfir;
+-01633         volatile uint32_t hfnum;
+-01635         uint32_t reserved40C;
+-01637         volatile uint32_t hptxsts;
+-01639         volatile uint32_t haint;
+-01641         volatile uint32_t haintmsk;
+-01643         volatile uint32_t hflbaddr;
+-01644 } dwc_otg_host_global_regs_t;
+-01645 
+-01646 
+-01652 typedef union hcfg_data
+-01653 {
+-01655         uint32_t d32;
+-01656 
+-01658         struct 
+-01659         {
+-01661                 unsigned fslspclksel:2;
+-01662 #define DWC_HCFG_30_60_MHZ 0
+-01663 #define DWC_HCFG_48_MHZ    1
+-01664 #define DWC_HCFG_6_MHZ     2
+-01665 
+-01667                 unsigned fslssupp:1;
+-01668                 unsigned reserved3_22 : 20;
+-01670                 unsigned descdma : 1;
+-01672                 unsigned frlisten: 2;
+-01674                 unsigned perschedena: 1;
+-01676                 unsigned perschedstat: 1;
+-01677         } b;
+-01678 } hcfg_data_t;
+-01679 
+-01684 typedef union hfir_data {
+-01686         uint32_t d32;
+-01687 
+-01689         struct {
+-01690                 unsigned frint:16;
+-01691                 unsigned reserved:16;
+-01692         } b;
+-01693 } hfir_data_t;
+-01694 
+-01699 typedef union hfnum_data {
+-01701         uint32_t d32;
+-01702 
+-01704         struct {
+-01705                 unsigned frnum:16;
+-01706 #define DWC_HFNUM_MAX_FRNUM 0x3FFF
+-01707                 unsigned frrem:16;
+-01708         } b;
+-01709 } hfnum_data_t;
+-01710 
+-01711 typedef union hptxsts_data {
+-01713         uint32_t d32;
+-01714 
+-01716         struct {
+-01717                 unsigned ptxfspcavail:16;
+-01718                 unsigned ptxqspcavail:8;
+-01728                 unsigned ptxqtop_terminate:1;
+-01729                 unsigned ptxqtop_token:2;
+-01730                 unsigned ptxqtop_chnum:4;
+-01731                 unsigned ptxqtop_odd:1;
+-01732         } b;
+-01733 } hptxsts_data_t;
+-01734 
+-01741 typedef union hprt0_data {
+-01743         uint32_t d32;
+-01745         struct {
+-01746                 unsigned prtconnsts:1;
+-01747                 unsigned prtconndet:1;
+-01748                 unsigned prtena:1;
+-01749                 unsigned prtenchng:1;
+-01750                 unsigned prtovrcurract:1;
+-01751                 unsigned prtovrcurrchng:1;
+-01752                 unsigned prtres:1;
+-01753                 unsigned prtsusp:1;
+-01754                 unsigned prtrst:1;
+-01755                 unsigned reserved9:1;
+-01756                 unsigned prtlnsts:2;
+-01757                 unsigned prtpwr:1;
+-01758                 unsigned prttstctl:4;
+-01759                 unsigned prtspd:2;
+-01760 #define DWC_HPRT0_PRTSPD_HIGH_SPEED 0
+-01761 #define DWC_HPRT0_PRTSPD_FULL_SPEED 1
+-01762 #define DWC_HPRT0_PRTSPD_LOW_SPEED      2
+-01763                 unsigned reserved19_31:13;
+-01764         } b;
+-01765 } hprt0_data_t;
+-01766 
+-01771 typedef union haint_data {
+-01773         uint32_t d32;
+-01775         struct {
+-01776                 unsigned ch0:1;
+-01777                 unsigned ch1:1;
+-01778                 unsigned ch2:1;
+-01779                 unsigned ch3:1;
+-01780                 unsigned ch4:1;
+-01781                 unsigned ch5:1;
+-01782                 unsigned ch6:1;
+-01783                 unsigned ch7:1;
+-01784                 unsigned ch8:1;
+-01785                 unsigned ch9:1;
+-01786                 unsigned ch10:1;
+-01787                 unsigned ch11:1;
+-01788                 unsigned ch12:1;
+-01789                 unsigned ch13:1;
+-01790                 unsigned ch14:1;
+-01791                 unsigned ch15:1;
+-01792                 unsigned reserved:16;
+-01793         } b;
+-01794 
+-01795         struct {
+-01796                 unsigned chint:16;
+-01797                 unsigned reserved:16;
+-01798         } b2;
+-01799 } haint_data_t;
+-01800 
+-01805 typedef union haintmsk_data {
+-01807         uint32_t d32;
+-01809         struct {
+-01810                 unsigned ch0:1;
+-01811                 unsigned ch1:1;
+-01812                 unsigned ch2:1;
+-01813                 unsigned ch3:1;
+-01814                 unsigned ch4:1;
+-01815                 unsigned ch5:1;
+-01816                 unsigned ch6:1;
+-01817                 unsigned ch7:1;
+-01818                 unsigned ch8:1;
+-01819                 unsigned ch9:1;
+-01820                 unsigned ch10:1;
+-01821                 unsigned ch11:1;
+-01822                 unsigned ch12:1;
+-01823                 unsigned ch13:1;
+-01824                 unsigned ch14:1;
+-01825                 unsigned ch15:1;
+-01826                 unsigned reserved:16;
+-01827         } b;
+-01828 
+-01829         struct {
+-01830                 unsigned chint:16;
+-01831                 unsigned reserved:16;
+-01832         } b2;
+-01833 } haintmsk_data_t;
+-01834 
+-01838 typedef struct dwc_otg_hc_regs 
+-01839 {
+-01841         volatile uint32_t hcchar;
+-01843         volatile uint32_t hcsplt;
+-01845         volatile uint32_t hcint;
+-01847         volatile uint32_t hcintmsk;
+-01849         volatile uint32_t hctsiz;
+-01851         volatile uint32_t hcdma;
+-01852         volatile uint32_t reserved;
+-01854         volatile uint32_t hcdmab;
+-01855 } dwc_otg_hc_regs_t;
+-01856 
+-01863 typedef union hcchar_data {
+-01865         uint32_t d32;
+-01866 
+-01868         struct {
+-01870                 unsigned mps:11;
+-01871 
+-01873                 unsigned epnum:4;
+-01874 
+-01876                 unsigned epdir:1;
+-01877 
+-01878                 unsigned reserved:1;
+-01879 
+-01881                 unsigned lspddev:1;
+-01882 
+-01884                 unsigned eptype:2;
+-01885 
+-01887                 unsigned multicnt:2;
+-01888 
+-01890                 unsigned devaddr:7;
+-01891 
+-01896                 unsigned oddfrm:1;
+-01897 
+-01899                 unsigned chdis:1;
+-01900 
+-01902                 unsigned chen:1;
+-01903         } b;
+-01904 } hcchar_data_t;
+-01905 
+-01906 typedef union hcsplt_data {
+-01908         uint32_t d32;
+-01909 
+-01911         struct {
+-01913                 unsigned prtaddr:7;
+-01914 
+-01916                 unsigned hubaddr:7;
+-01917 
+-01919                 unsigned xactpos:2;
+-01920 #define DWC_HCSPLIT_XACTPOS_MID 0
+-01921 #define DWC_HCSPLIT_XACTPOS_END 1
+-01922 #define DWC_HCSPLIT_XACTPOS_BEGIN 2
+-01923 #define DWC_HCSPLIT_XACTPOS_ALL 3
+-01924 
+-01926                 unsigned compsplt:1;
+-01927 
+-01929                 unsigned reserved:14;
+-01930 
+-01932                 unsigned spltena:1;
+-01933         } b;
+-01934 } hcsplt_data_t;
+-01935 
+-01940 typedef union hcint_data
+-01941 {
+-01943         uint32_t d32;
+-01945         struct 
+-01946         {
+-01948                 unsigned xfercomp:1;
+-01950                 unsigned chhltd:1;
+-01952                 unsigned ahberr:1;
+-01954                 unsigned stall:1;
+-01956                 unsigned nak:1;
+-01958                 unsigned ack:1;
+-01960                 unsigned nyet:1;
+-01962                 unsigned xacterr:1;
+-01964                 unsigned bblerr:1;
+-01966                 unsigned frmovrun:1;
+-01968                 unsigned datatglerr:1;
+-01970                 unsigned bna : 1;
+-01972                 unsigned xcs_xact : 1;
+-01974                 unsigned frm_list_roll : 1;
+-01976                 unsigned reserved14_31 : 18;
+-01977         } b;
+-01978 } hcint_data_t;
+-01979 
+-01986 typedef union hcintmsk_data
+-01987 {
+-01989         uint32_t d32;
+-01990 
+-01992         struct 
+-01993         {
+-01994                 unsigned xfercompl : 1;
+-01995                 unsigned chhltd : 1;
+-01996                 unsigned ahberr : 1;
+-01997                 unsigned stall : 1;
+-01998                 unsigned nak : 1;
+-01999                 unsigned ack : 1;
+-02000                 unsigned nyet : 1;
+-02001                 unsigned xacterr : 1;
+-02002                 unsigned bblerr : 1;
+-02003                 unsigned frmovrun : 1;
+-02004                 unsigned datatglerr : 1;
+-02005                 unsigned bna : 1;
+-02006                 unsigned xcs_xact : 1;
+-02007                 unsigned frm_list_roll : 1;
+-02008                 unsigned reserved14_31 : 18;
+-02009         } b;
+-02010 } hcintmsk_data_t;
+-02011 
+-02019 typedef union hctsiz_data
+-02020 {
+-02022         uint32_t d32;
+-02023 
+-02025         struct 
+-02026         {
+-02028                 unsigned xfersize:19;
+-02029 
+-02031                 unsigned pktcnt:10;
+-02032 
+-02040                 unsigned pid:2;
+-02041 #define DWC_HCTSIZ_DATA0 0
+-02042 #define DWC_HCTSIZ_DATA1 2
+-02043 #define DWC_HCTSIZ_DATA2 1
+-02044 #define DWC_HCTSIZ_MDATA 3
+-02045 #define DWC_HCTSIZ_SETUP 3
+-02046 
+-02048                 unsigned dopng:1;
+-02049         } b;
+-02050         
+-02052         struct 
+-02053         {
+-02055                 unsigned schinfo : 8;
+-02056                 
+-02062                 unsigned ntd : 8;
+-02063 
+-02065                 unsigned reserved16_28 : 13;
+-02066 
+-02074                 unsigned pid : 2;
+-02075 
+-02077                 unsigned dopng : 1;
+-02078         } b_ddma;
+-02079 } hctsiz_data_t;
+-02080 
+-02081 
+-02086 typedef union hcdma_data
+-02087 {
+-02089         uint32_t d32;
+-02091         struct 
+-02092         {
+-02093                 unsigned reserved0_2 : 3;
+-02095                 unsigned ctd : 8;
+-02097                 unsigned dma_addr : 21;
+-02098         } b;
+-02099 } hcdma_data_t;
+-02100 
+-02106 typedef union host_dma_desc_sts
+-02107 {
+-02109         uint32_t d32;
+-02112         /* for non-isochronous  */
+-02113         struct {
+-02115                 unsigned n_bytes : 17;
+-02117                 unsigned qtd_offset : 6;
+-02122                 unsigned a_qtd : 1;
+-02127                 unsigned sup : 1;
+-02129                 unsigned ioc : 1;
+-02131                 unsigned eol : 1;
+-02132                 unsigned reserved27 : 1;
+-02134                 unsigned sts : 2;
+-02135         #define DMA_DESC_STS_PKTERR     1
+-02136                 unsigned reserved30 : 1;
+-02138                 unsigned a : 1;
+-02139         } b;
+-02140         /* for isochronous */
+-02141         struct {
+-02143                 unsigned n_bytes : 12;
+-02144                 unsigned reserved12_24 : 13;
+-02146                 unsigned ioc : 1;
+-02147                 unsigned reserved26_27 : 2;
+-02149                 unsigned sts : 2;
+-02150                 unsigned reserved30 : 1;
+-02152                 unsigned a : 1;
+-02153         } b_isoc;
+-02154 } host_dma_desc_sts_t;
+-02155 
+-02156 #define MAX_DMA_DESC_SIZE               131071
+-02157 #define MAX_DMA_DESC_NUM_GENERIC        64
+-02158 #define MAX_DMA_DESC_NUM_HS_ISOC        256
+-02159 #define MAX_FRLIST_EN_NUM               64
+-02160 
+-02166 typedef struct dwc_otg_host_dma_desc
+-02167 {
+-02169         host_dma_desc_sts_t     status;
+-02171         uint32_t        buf;
+-02172 } dwc_otg_host_dma_desc_t;
+-02173 
+-02181 typedef struct dwc_otg_host_if {
+-02183         dwc_otg_host_global_regs_t *host_global_regs;
+-02184 #define DWC_OTG_HOST_GLOBAL_REG_OFFSET 0x400
+-02185 
+-02187         volatile uint32_t *hprt0;
+-02188 #define DWC_OTG_HOST_PORT_REGS_OFFSET 0x440
+-02189 
+-02191         dwc_otg_hc_regs_t *hc_regs[MAX_EPS_CHANNELS];
+-02192 #define DWC_OTG_HOST_CHAN_REGS_OFFSET 0x500
+-02193 #define DWC_OTG_CHAN_REGS_OFFSET 0x20
+-02194 
+-02195         /* Host configuration information */
+-02197         uint8_t num_host_channels;
+-02199         uint8_t perio_eps_supported;
+-02201         uint16_t perio_tx_fifo_size;
+-02202 
+-02203 } dwc_otg_host_if_t;
+-02204 
+-02210 typedef union pcgcctl_data {
+-02212         uint32_t d32;
+-02213 
+-02215         struct {
+-02217                 unsigned stoppclk:1;
+-02219                 unsigned gatehclk:1;
+-02221                 unsigned pwrclmp:1;
+-02223                 unsigned rstpdwnmodule:1;
+-02225                 unsigned physuspended:1;
+-02227                 unsigned enbl_sleep_gating:1;
+-02229                 unsigned phy_in_sleep:1;
+-02231                 unsigned deep_sleep:1;
+-02232 
+-02233                 unsigned reserved31_8:24;
+-02234         } b;
+-02235 } pcgcctl_data_t;
+-02236 
+-02237 #endif
+-
      Generated on Tue May 5 02:22:48 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by 
++00073         volatile uint32_t gotgctl;
++00075         volatile uint32_t gotgint;
++00077         volatile uint32_t gahbcfg;
++00078 
++00079 #define DWC_GLBINTRMASK         0x0001
++00080 #define DWC_DMAENABLE           0x0020
++00081 #define DWC_NPTXEMPTYLVL_EMPTY  0x0080
++00082 #define DWC_NPTXEMPTYLVL_HALFEMPTY      0x0000
++00083 #define DWC_PTXEMPTYLVL_EMPTY   0x0100
++00084 #define DWC_PTXEMPTYLVL_HALFEMPTY       0x0000
++00085 
++00087         volatile uint32_t gusbcfg;
++00089         volatile uint32_t grstctl;
++00091         volatile uint32_t gintsts;
++00093         volatile uint32_t gintmsk;
++00095         volatile uint32_t grxstsr;
++00097         volatile uint32_t grxstsp;
++00099         volatile uint32_t grxfsiz;
++00101         volatile uint32_t gnptxfsiz;
++00104         volatile uint32_t gnptxsts;
++00106         volatile uint32_t gi2cctl;
++00108         volatile uint32_t gpvndctl;
++00110         volatile uint32_t ggpio;
++00112         volatile uint32_t guid;
++00114         volatile uint32_t gsnpsid;
++00116         volatile uint32_t ghwcfg1;
++00118         volatile uint32_t ghwcfg2;
++00119 #define DWC_SLAVE_ONLY_ARCH 0
++00120 #define DWC_EXT_DMA_ARCH 1
++00121 #define DWC_INT_DMA_ARCH 2
++00122 
++00123 #define DWC_MODE_HNP_SRP_CAPABLE        0
++00124 #define DWC_MODE_SRP_ONLY_CAPABLE       1
++00125 #define DWC_MODE_NO_HNP_SRP_CAPABLE             2
++00126 #define DWC_MODE_SRP_CAPABLE_DEVICE             3
++00127 #define DWC_MODE_NO_SRP_CAPABLE_DEVICE  4
++00128 #define DWC_MODE_SRP_CAPABLE_HOST       5
++00129 #define DWC_MODE_NO_SRP_CAPABLE_HOST    6
++00130 
++00132         volatile uint32_t ghwcfg3;
++00134         volatile uint32_t ghwcfg4;
++00136         volatile uint32_t glpmcfg;
++00138         volatile uint32_t gpwrdn;
++00140         volatile uint32_t gdfifocfg;
++00142         volatile uint32_t adpctl;
++00144         volatile uint32_t reserved39[39];
++00146         volatile uint32_t hptxfsiz;
++00150         volatile uint32_t dtxfsiz[15];
++00151 } dwc_otg_core_global_regs_t;
++00152 
++00158 typedef union gotgctl_data {
++00160         uint32_t d32;
++00162         struct {
++00163                 unsigned sesreqscs:1;
++00164                 unsigned sesreq:1;
++00165                 unsigned vbvalidoven:1;
++00166                 unsigned vbvalidovval:1;
++00167                 unsigned avalidoven:1;
++00168                 unsigned avalidovval:1;
++00169                 unsigned bvalidoven:1;
++00170                 unsigned bvalidovval:1;
++00171                 unsigned hstnegscs:1;
++00172                 unsigned hnpreq:1;
++00173                 unsigned hstsethnpen:1;
++00174                 unsigned devhnpen:1;
++00175                 unsigned reserved12_15:4;
++00176                 unsigned conidsts:1;
++00177                 unsigned dbnctime:1;
++00178                 unsigned asesvld:1;
++00179                 unsigned bsesvld:1;
++00180                 unsigned otgver:1;
++00181                 unsigned reserved1:1;
++00182                 unsigned multvalidbc:5;
++00183                 unsigned chirpen:1;
++00184                 unsigned reserved28_31:4;
++00185         } b;
++00186 } gotgctl_data_t;
++00187 
++00193 typedef union gotgint_data {
++00195         uint32_t d32;
++00197         struct {
++00199                 unsigned reserved0_1:2;
++00200 
++00202                 unsigned sesenddet:1;
++00203 
++00204                 unsigned reserved3_7:5;
++00205 
++00207                 unsigned sesreqsucstschng:1;
++00209                 unsigned hstnegsucstschng:1;
++00210 
++00211                 unsigned reserved10_16:7;
++00212 
++00214                 unsigned hstnegdet:1;
++00216                 unsigned adevtoutchng:1;
++00218                 unsigned debdone:1;
++00220                 unsigned mvic:1;
++00221 
++00222                 unsigned reserved31_21:11;
++00223 
++00224         } b;
++00225 } gotgint_data_t;
++00226 
++00232 typedef union gahbcfg_data {
++00234         uint32_t d32;
++00236         struct {
++00237                 unsigned glblintrmsk:1;
++00238 #define DWC_GAHBCFG_GLBINT_ENABLE               1
++00239 
++00240                 unsigned hburstlen:4;
++00241 #define DWC_GAHBCFG_INT_DMA_BURST_SINGLE        0
++00242 #define DWC_GAHBCFG_INT_DMA_BURST_INCR          1
++00243 #define DWC_GAHBCFG_INT_DMA_BURST_INCR4         3
++00244 #define DWC_GAHBCFG_INT_DMA_BURST_INCR8         5
++00245 #define DWC_GAHBCFG_INT_DMA_BURST_INCR16        7
++00246 
++00247                 unsigned dmaenable:1;
++00248 #define DWC_GAHBCFG_DMAENABLE                   1
++00249                 unsigned reserved:1;
++00250                 unsigned nptxfemplvl_txfemplvl:1;
++00251                 unsigned ptxfemplvl:1;
++00252 #define DWC_GAHBCFG_TXFEMPTYLVL_EMPTY           1
++00253 #define DWC_GAHBCFG_TXFEMPTYLVL_HALFEMPTY       0
++00254                 unsigned reserved9_20:12;
++00255                 unsigned remmemsupp:1;
++00256                 unsigned notialldmawrit:1;
++00257                 unsigned ahbsingle:1;
++00258                 unsigned reserved24_31:8;
++00259         } b;
++00260 } gahbcfg_data_t;
++00261 
++00267 typedef union gusbcfg_data {
++00269         uint32_t d32;
++00271         struct {
++00272                 unsigned toutcal:3;
++00273                 unsigned phyif:1;
++00274                 unsigned ulpi_utmi_sel:1;
++00275                 unsigned fsintf:1;
++00276                 unsigned physel:1;
++00277                 unsigned ddrsel:1;
++00278                 unsigned srpcap:1;
++00279                 unsigned hnpcap:1;
++00280                 unsigned usbtrdtim:4;
++00281                 unsigned reserved1:1;
++00282                 unsigned phylpwrclksel:1;
++00283                 unsigned otgutmifssel:1;
++00284                 unsigned ulpi_fsls:1;
++00285                 unsigned ulpi_auto_res:1;
++00286                 unsigned ulpi_clk_sus_m:1;
++00287                 unsigned ulpi_ext_vbus_drv:1;
++00288                 unsigned ulpi_int_vbus_indicator:1;
++00289                 unsigned term_sel_dl_pulse:1;
++00290                 unsigned indicator_complement:1;
++00291                 unsigned indicator_pass_through:1;
++00292                 unsigned ulpi_int_prot_dis:1;
++00293                 unsigned ic_usb_cap:1;
++00294                 unsigned ic_traffic_pull_remove:1;
++00295                 unsigned tx_end_delay:1;
++00296                 unsigned force_host_mode:1;
++00297                 unsigned force_dev_mode:1;
++00298                 unsigned reserved31:1;
++00299         } b;
++00300 } gusbcfg_data_t;
++00301 
++00307 typedef union grstctl_data {
++00309         uint32_t d32;
++00311         struct {
++00347                 unsigned csftrst:1;
++00354                 unsigned hsftrst:1;
++00363                 unsigned hstfrm:1;
++00367                 unsigned intknqflsh:1;
++00382                 unsigned rxfflsh:1;
++00397                 unsigned txfflsh:1;
++00398 
++00414                 unsigned txfnum:5;
++00416                 unsigned reserved11_29:19;
++00419                 unsigned dmareq:1;
++00422                 unsigned ahbidle:1;
++00423         } b;
++00424 } grstctl_t;
++00425 
++00431 typedef union gintmsk_data {
++00433         uint32_t d32;
++00435         struct {
++00436                 unsigned reserved0:1;
++00437                 unsigned modemismatch:1;
++00438                 unsigned otgintr:1;
++00439                 unsigned sofintr:1;
++00440                 unsigned rxstsqlvl:1;
++00441                 unsigned nptxfempty:1;
++00442                 unsigned ginnakeff:1;
++00443                 unsigned goutnakeff:1;
++00444                 unsigned ulpickint:1;
++00445                 unsigned i2cintr:1;
++00446                 unsigned erlysuspend:1;
++00447                 unsigned usbsuspend:1;
++00448                 unsigned usbreset:1;
++00449                 unsigned enumdone:1;
++00450                 unsigned isooutdrop:1;
++00451                 unsigned eopframe:1;
++00452                 unsigned restoredone:1;
++00453                 unsigned epmismatch:1;
++00454                 unsigned inepintr:1;
++00455                 unsigned outepintr:1;
++00456                 unsigned incomplisoin:1;
++00457                 unsigned incomplisoout:1;
++00458                 unsigned fetsusp:1;
++00459                 unsigned resetdet:1;
++00460                 unsigned portintr:1;
++00461                 unsigned hcintr:1;
++00462                 unsigned ptxfempty:1;
++00463                 unsigned lpmtranrcvd:1;
++00464                 unsigned conidstschng:1;
++00465                 unsigned disconnect:1;
++00466                 unsigned sessreqintr:1;
++00467                 unsigned wkupintr:1;
++00468         } b;
++00469 } gintmsk_data_t;
++00475 typedef union gintsts_data {
++00477         uint32_t d32;
++00478 #define DWC_SOF_INTR_MASK 0x0008
++00479 
++00480         struct {
++00481 #define DWC_HOST_MODE 1
++00482                 unsigned curmode:1;
++00483                 unsigned modemismatch:1;
++00484                 unsigned otgintr:1;
++00485                 unsigned sofintr:1;
++00486                 unsigned rxstsqlvl:1;
++00487                 unsigned nptxfempty:1;
++00488                 unsigned ginnakeff:1;
++00489                 unsigned goutnakeff:1;
++00490                 unsigned ulpickint:1;
++00491                 unsigned i2cintr:1;
++00492                 unsigned erlysuspend:1;
++00493                 unsigned usbsuspend:1;
++00494                 unsigned usbreset:1;
++00495                 unsigned enumdone:1;
++00496                 unsigned isooutdrop:1;
++00497                 unsigned eopframe:1;
++00498                 unsigned restoredone:1;
++00499                 unsigned epmismatch:1;
++00500                 unsigned inepint:1;
++00501                 unsigned outepintr:1;
++00502                 unsigned incomplisoin:1;
++00503                 unsigned incomplisoout:1;
++00504                 unsigned fetsusp:1;
++00505                 unsigned resetdet:1;
++00506                 unsigned portintr:1;
++00507                 unsigned hcintr:1;
++00508                 unsigned ptxfempty:1;
++00509                 unsigned lpmtranrcvd:1;
++00510                 unsigned conidstschng:1;
++00511                 unsigned disconnect:1;
++00512                 unsigned sessreqintr:1;
++00513                 unsigned wkupintr:1;
++00514         } b;
++00515 } gintsts_data_t;
++00516 
++00522 typedef union device_grxsts_data {
++00524         uint32_t d32;
++00526         struct {
++00527                 unsigned epnum:4;
++00528                 unsigned bcnt:11;
++00529                 unsigned dpid:2;
++00530 
++00531 #define DWC_STS_DATA_UPDT               0x2     // OUT Data Packet
++00532 #define DWC_STS_XFER_COMP               0x3     // OUT Data Transfer Complete
++00533 
++00534 #define DWC_DSTS_GOUT_NAK               0x1     // Global OUT NAK
++00535 #define DWC_DSTS_SETUP_COMP             0x4     // Setup Phase Complete
++00536 #define DWC_DSTS_SETUP_UPDT 0x6 // SETUP Packet
++00537                 unsigned pktsts:4;
++00538                 unsigned fn:4;
++00539                 unsigned reserved25_31:7;
++00540         } b;
++00541 } device_grxsts_data_t;
++00542 
++00548 typedef union host_grxsts_data {
++00550         uint32_t d32;
++00552         struct {
++00553                 unsigned chnum:4;
++00554                 unsigned bcnt:11;
++00555                 unsigned dpid:2;
++00556 
++00557                 unsigned pktsts:4;
++00558 #define DWC_GRXSTS_PKTSTS_IN                      0x2
++00559 #define DWC_GRXSTS_PKTSTS_IN_XFER_COMP    0x3
++00560 #define DWC_GRXSTS_PKTSTS_DATA_TOGGLE_ERR 0x5
++00561 #define DWC_GRXSTS_PKTSTS_CH_HALTED               0x7
++00562 
++00563                 unsigned reserved21_31:11;
++00564         } b;
++00565 } host_grxsts_data_t;
++00566 
++00572 typedef union fifosize_data {
++00574         uint32_t d32;
++00576         struct {
++00577                 unsigned startaddr:16;
++00578                 unsigned depth:16;
++00579         } b;
++00580 } fifosize_data_t;
++00581 
++00588 typedef union gnptxsts_data {
++00590         uint32_t d32;
++00592         struct {
++00593                 unsigned nptxfspcavail:16;
++00594                 unsigned nptxqspcavail:8;
++00605                 unsigned nptxqtop_terminate:1;
++00606                 unsigned nptxqtop_token:2;
++00607                 unsigned nptxqtop_chnep:4;
++00608                 unsigned reserved:1;
++00609         } b;
++00610 } gnptxsts_data_t;
++00611 
++00618 typedef union dtxfsts_data {
++00620         uint32_t d32;
++00622         struct {
++00623                 unsigned txfspcavail:16;
++00624                 unsigned reserved:16;
++00625         } b;
++00626 } dtxfsts_data_t;
++00627 
++00633 typedef union gi2cctl_data {
++00635         uint32_t d32;
++00637         struct {
++00638                 unsigned rwdata:8;
++00639                 unsigned regaddr:8;
++00640                 unsigned addr:7;
++00641                 unsigned i2cen:1;
++00642                 unsigned ack:1;
++00643                 unsigned i2csuspctl:1;
++00644                 unsigned i2cdevaddr:2;
++00645                 unsigned i2cdatse0:1;
++00646                 unsigned reserved:1;
++00647                 unsigned rw:1;
++00648                 unsigned bsydne:1;
++00649         } b;
++00650 } gi2cctl_data_t;
++00651 
++00657 typedef union gpvndctl_data {
++00659         uint32_t d32;
++00661         struct {
++00662                 unsigned regdata:8;
++00663                 unsigned vctrl:8;
++00664                 unsigned regaddr16_21:6;
++00665                 unsigned regwr:1;
++00666                 unsigned reserved23_24:2;
++00667                 unsigned newregreq:1;
++00668                 unsigned vstsbsy:1;
++00669                 unsigned vstsdone:1;
++00670                 unsigned reserved28_30:3;
++00671                 unsigned disulpidrvr:1;
++00672         } b;
++00673 } gpvndctl_data_t;
++00674 
++00681 typedef union ggpio_data {
++00683         uint32_t d32;
++00685         struct {
++00686                 unsigned gpi:16;
++00687                 unsigned gpo:16;
++00688         } b;
++00689 } ggpio_data_t;
++00690 
++00696 typedef union guid_data {
++00698         uint32_t d32;
++00700         struct {
++00701                 unsigned rwdata:32;
++00702         } b;
++00703 } guid_data_t;
++00704 
++00710 typedef union gsnpsid_data {
++00712         uint32_t d32;
++00714         struct {
++00715                 unsigned rwdata:32;
++00716         } b;
++00717 } gsnpsid_data_t;
++00718 
++00724 typedef union hwcfg1_data {
++00726         uint32_t d32;
++00728         struct {
++00729                 unsigned ep_dir0:2;
++00730                 unsigned ep_dir1:2;
++00731                 unsigned ep_dir2:2;
++00732                 unsigned ep_dir3:2;
++00733                 unsigned ep_dir4:2;
++00734                 unsigned ep_dir5:2;
++00735                 unsigned ep_dir6:2;
++00736                 unsigned ep_dir7:2;
++00737                 unsigned ep_dir8:2;
++00738                 unsigned ep_dir9:2;
++00739                 unsigned ep_dir10:2;
++00740                 unsigned ep_dir11:2;
++00741                 unsigned ep_dir12:2;
++00742                 unsigned ep_dir13:2;
++00743                 unsigned ep_dir14:2;
++00744                 unsigned ep_dir15:2;
++00745         } b;
++00746 } hwcfg1_data_t;
++00747 
++00753 typedef union hwcfg2_data {
++00755         uint32_t d32;
++00757         struct {
++00758                 /* GHWCFG2 */
++00759                 unsigned op_mode:3;
++00760 #define DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG 0
++00761 #define DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG 1
++00762 #define DWC_HWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE_OTG 2
++00763 #define DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE 3
++00764 #define DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE 4
++00765 #define DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST 5
++00766 #define DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST 6
++00767 
++00768                 unsigned architecture:2;
++00769                 unsigned point2point:1;
++00770                 unsigned hs_phy_type:2;
++00771 #define DWC_HWCFG2_HS_PHY_TYPE_NOT_SUPPORTED 0
++00772 #define DWC_HWCFG2_HS_PHY_TYPE_UTMI 1
++00773 #define DWC_HWCFG2_HS_PHY_TYPE_ULPI 2
++00774 #define DWC_HWCFG2_HS_PHY_TYPE_UTMI_ULPI 3
++00775 
++00776                 unsigned fs_phy_type:2;
++00777                 unsigned num_dev_ep:4;
++00778                 unsigned num_host_chan:4;
++00779                 unsigned perio_ep_supported:1;
++00780                 unsigned dynamic_fifo:1;
++00781                 unsigned multi_proc_int:1;
++00782                 unsigned reserved21:1;
++00783                 unsigned nonperio_tx_q_depth:2;
++00784                 unsigned host_perio_tx_q_depth:2;
++00785                 unsigned dev_token_q_depth:5;
++00786                 unsigned otg_enable_ic_usb:1;
++00787         } b;
++00788 } hwcfg2_data_t;
++00789 
++00795 typedef union hwcfg3_data {
++00797         uint32_t d32;
++00799         struct {
++00800                 /* GHWCFG3 */
++00801                 unsigned xfer_size_cntr_width:4;
++00802                 unsigned packet_size_cntr_width:3;
++00803                 unsigned otg_func:1;
++00804                 unsigned i2c:1;
++00805                 unsigned vendor_ctrl_if:1;
++00806                 unsigned optional_features:1;
++00807                 unsigned synch_reset_type:1;
++00808                 unsigned adp_supp:1;
++00809                 unsigned otg_enable_hsic:1;
++00810                 unsigned bc_support:1;
++00811                 unsigned otg_lpm_en:1;
++00812                 unsigned dfifo_depth:16;
++00813         } b;
++00814 } hwcfg3_data_t;
++00815 
++00821 typedef union hwcfg4_data {
++00823         uint32_t d32;
++00825         struct {
++00826                 unsigned num_dev_perio_in_ep:4;
++00827                 unsigned power_optimiz:1;
++00828                 unsigned min_ahb_freq:1;
++00829                 unsigned part_power_down:1;
++00830                 unsigned reserved:7;
++00831                 unsigned utmi_phy_data_width:2;
++00832                 unsigned num_dev_mode_ctrl_ep:4;
++00833                 unsigned iddig_filt_en:1;
++00834                 unsigned vbus_valid_filt_en:1;
++00835                 unsigned a_valid_filt_en:1;
++00836                 unsigned b_valid_filt_en:1;
++00837                 unsigned session_end_filt_en:1;
++00838                 unsigned ded_fifo_en:1;
++00839                 unsigned num_in_eps:4;
++00840                 unsigned desc_dma:1;
++00841                 unsigned desc_dma_dyn:1;
++00842         } b;
++00843 } hwcfg4_data_t;
++00844 
++00850 typedef union glpmctl_data {
++00852         uint32_t d32;
++00854         struct {
++00859                 unsigned lpm_cap_en:1;
++00864                 unsigned appl_resp:1;
++00873                 unsigned hird:4;
++00882                 unsigned rem_wkup_en:1;
++00887                 unsigned en_utmi_sleep:1;
++00890                 unsigned hird_thres:5;
++00901                 unsigned lpm_resp:2;
++00906                 unsigned prt_sleep_sts:1;
++00911                 unsigned sleep_state_resumeok:1;
++00917                 unsigned lpm_chan_index:4;
++00922                 unsigned retry_count:3;
++00928                 unsigned send_lpm:1;
++00933                 unsigned retry_count_sts:3;
++00934                 unsigned reserved28_29:2;
++00942                 unsigned hsic_connect:1;
++00946                 unsigned inv_sel_hsic:1;
++00947         } b;
++00948 } glpmcfg_data_t;
++00949 
++00955 typedef union adpctl_data {
++00957         uint32_t d32;
++00959         struct {
++00968                 unsigned prb_dschg:2;
++00979                 unsigned prb_delta:2;
++00987                 unsigned prb_per:2;
++00997                 unsigned rtim:11;
++01002                 unsigned enaprb:1;
++01007                 unsigned enasns:1;
++01012                 unsigned adpres:1;
++01018                 unsigned adpen:1;
++01024                 unsigned adp_prb_int:1;
++01031                 unsigned adp_sns_int:1;
++01040                 unsigned adp_tmout_int:1;
++01045                 unsigned adp_prb_int_msk:1;
++01050                 unsigned adp_sns_int_msk:1;
++01055                 unsigned adp_tmout_int_msk:1;
++01062                 unsigned ar:2;
++01064                 unsigned reserved29_31:3;
++01065         } b;
++01066 } adpctl_data_t;
++01067 
++01069 // Device Registers
++01079 typedef struct dwc_otg_dev_global_regs {
++01081         volatile uint32_t dcfg;
++01083         volatile uint32_t dctl;
++01085         volatile uint32_t dsts;
++01087         uint32_t unused;
++01090         volatile uint32_t diepmsk;
++01093         volatile uint32_t doepmsk;
++01095         volatile uint32_t daint;
++01098         volatile uint32_t daintmsk;
++01101         volatile uint32_t dtknqr1;
++01104         volatile uint32_t dtknqr2;
++01106         volatile uint32_t dvbusdis;
++01108         volatile uint32_t dvbuspulse;
++01112         volatile uint32_t dtknqr3_dthrctl;
++01116         volatile uint32_t dtknqr4_fifoemptymsk;
++01119         volatile uint32_t deachint;
++01122         volatile uint32_t deachintmsk;
++01125         volatile uint32_t diepeachintmsk[MAX_EPS_CHANNELS];
++01128         volatile uint32_t doepeachintmsk[MAX_EPS_CHANNELS];
++01129 } dwc_otg_device_global_regs_t;
++01130 
++01137 typedef union dcfg_data {
++01139         uint32_t d32;
++01141         struct {
++01143                 unsigned devspd:2;
++01145                 unsigned nzstsouthshk:1;
++01146 #define DWC_DCFG_SEND_STALL 1
++01147 
++01148                 unsigned ena32khzs:1;
++01150                 unsigned devaddr:7;
++01152                 unsigned perfrint:2;
++01153 #define DWC_DCFG_FRAME_INTERVAL_80 0
++01154 #define DWC_DCFG_FRAME_INTERVAL_85 1
++01155 #define DWC_DCFG_FRAME_INTERVAL_90 2
++01156 #define DWC_DCFG_FRAME_INTERVAL_95 3
++01157                 
++01159                 unsigned endevoutnak:1;
++01160 
++01161                 unsigned reserved14_17:4;
++01163                 unsigned epmscnt:5;
++01165                 unsigned descdma:1;
++01166                 unsigned perschintvl:2;
++01167                 unsigned resvalid:6;
++01168         } b;
++01169 } dcfg_data_t;
++01170 
++01176 typedef union dctl_data {
++01178         uint32_t d32;
++01180         struct {
++01182                 unsigned rmtwkupsig:1;
++01184                 unsigned sftdiscon:1;
++01186                 unsigned gnpinnaksts:1;
++01188                 unsigned goutnaksts:1;
++01190                 unsigned tstctl:3;
++01192                 unsigned sgnpinnak:1;
++01194                 unsigned cgnpinnak:1;
++01196                 unsigned sgoutnak:1;
++01198                 unsigned cgoutnak:1;
++01200                 unsigned pwronprgdone:1;
++01202                 unsigned reserved:1;
++01204                 unsigned gmc:2;
++01206                 unsigned ifrmnum:1;
++01208                 unsigned nakonbble:1;
++01210                 unsigned encontonbna:1;
++01211 
++01212                 unsigned reserved18_31:14;
++01213         } b;
++01214 } dctl_data_t;
++01215 
++01221 typedef union dsts_data {
++01223         uint32_t d32;
++01225         struct {
++01227                 unsigned suspsts:1;
++01229                 unsigned enumspd:2;
++01230 #define DWC_DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ 0
++01231 #define DWC_DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ 1
++01232 #define DWC_DSTS_ENUMSPD_LS_PHY_6MHZ               2
++01233 #define DWC_DSTS_ENUMSPD_FS_PHY_48MHZ              3
++01234 
++01235                 unsigned errticerr:1;
++01236                 unsigned reserved4_7:4;
++01238                 unsigned soffn:14;
++01239                 unsigned reserved22_31:10;
++01240         } b;
++01241 } dsts_data_t;
++01242 
++01250 typedef union diepint_data {
++01252         uint32_t d32;
++01254         struct {
++01256                 unsigned xfercompl:1;
++01258                 unsigned epdisabled:1;
++01260                 unsigned ahberr:1;
++01262                 unsigned timeout:1;
++01264                 unsigned intktxfemp:1;
++01266                 unsigned intknepmis:1;
++01268                 unsigned inepnakeff:1;
++01270                 unsigned emptyintr:1;
++01271 
++01272                 unsigned txfifoundrn:1;
++01273 
++01275                 unsigned bna:1;
++01276 
++01277                 unsigned reserved10_12:3;
++01279                 unsigned nak:1;
++01280 
++01281                 unsigned reserved14_31:18;
++01282         } b;
++01283 } diepint_data_t;
++01284 
++01289 typedef union diepint_data diepmsk_data_t;
++01290 
++01298 typedef union doepint_data {
++01300         uint32_t d32;
++01302         struct {
++01304                 unsigned xfercompl:1;
++01306                 unsigned epdisabled:1;
++01308                 unsigned ahberr:1;
++01310                 unsigned setup:1;
++01312                 unsigned outtknepdis:1;
++01313 
++01314                 unsigned stsphsercvd:1;
++01316                 unsigned back2backsetup:1;
++01317 
++01318                 unsigned reserved7:1;
++01320                 unsigned outpkterr:1;
++01322                 unsigned bna:1;
++01323 
++01324                 unsigned reserved10:1;
++01326                 unsigned pktdrpsts:1;
++01328                 unsigned babble:1;
++01330                 unsigned nak:1;
++01332                 unsigned nyet:1;
++01333 
++01334                 unsigned reserved15_31:17;
++01335         } b;
++01336 } doepint_data_t;
++01337 
++01342 typedef union doepint_data doepmsk_data_t;
++01343 
++01350 typedef union daint_data {
++01352         uint32_t d32;
++01354         struct {
++01356                 unsigned in:16;
++01358                 unsigned out:16;
++01359         } ep;
++01360         struct {
++01362                 unsigned inep0:1;
++01363                 unsigned inep1:1;
++01364                 unsigned inep2:1;
++01365                 unsigned inep3:1;
++01366                 unsigned inep4:1;
++01367                 unsigned inep5:1;
++01368                 unsigned inep6:1;
++01369                 unsigned inep7:1;
++01370                 unsigned inep8:1;
++01371                 unsigned inep9:1;
++01372                 unsigned inep10:1;
++01373                 unsigned inep11:1;
++01374                 unsigned inep12:1;
++01375                 unsigned inep13:1;
++01376                 unsigned inep14:1;
++01377                 unsigned inep15:1;
++01379                 unsigned outep0:1;
++01380                 unsigned outep1:1;
++01381                 unsigned outep2:1;
++01382                 unsigned outep3:1;
++01383                 unsigned outep4:1;
++01384                 unsigned outep5:1;
++01385                 unsigned outep6:1;
++01386                 unsigned outep7:1;
++01387                 unsigned outep8:1;
++01388                 unsigned outep9:1;
++01389                 unsigned outep10:1;
++01390                 unsigned outep11:1;
++01391                 unsigned outep12:1;
++01392                 unsigned outep13:1;
++01393                 unsigned outep14:1;
++01394                 unsigned outep15:1;
++01395         } b;
++01396 } daint_data_t;
++01397 
++01404 typedef union dtknq1_data {
++01406         uint32_t d32;
++01408         struct {
++01410                 unsigned intknwptr:5;
++01412                 unsigned reserved05_06:2;
++01414                 unsigned wrap_bit:1;
++01416                 unsigned epnums0_5:24;
++01417         } b;
++01418 } dtknq1_data_t;
++01419 
++01425 typedef union dthrctl_data {
++01427         uint32_t d32;
++01429         struct {
++01431                 unsigned non_iso_thr_en:1;
++01433                 unsigned iso_thr_en:1;
++01435                 unsigned tx_thr_len:9;
++01437                 unsigned ahb_thr_ratio:2;
++01439                 unsigned reserved13_15:3;
++01441                 unsigned rx_thr_en:1;
++01443                 unsigned rx_thr_len:9;
++01444                 unsigned reserved26:1;
++01446                 unsigned arbprken:1;
++01448                 unsigned reserved28_31:4;
++01449         } b;
++01450 } dthrctl_data_t;
++01451 
++01462 typedef struct dwc_otg_dev_in_ep_regs {
++01465         volatile uint32_t diepctl;
++01467         uint32_t reserved04;
++01470         volatile uint32_t diepint;
++01472         uint32_t reserved0C;
++01475         volatile uint32_t dieptsiz;
++01478         volatile uint32_t diepdma;
++01481         volatile uint32_t dtxfsts;
++01484         volatile uint32_t diepdmab;
++01485 } dwc_otg_dev_in_ep_regs_t;
++01486 
++01497 typedef struct dwc_otg_dev_out_ep_regs {
++01500         volatile uint32_t doepctl;
++01502         uint32_t reserved04;
++01505         volatile uint32_t doepint;
++01507         uint32_t reserved0C;
++01510         volatile uint32_t doeptsiz;
++01513         volatile uint32_t doepdma;
++01515         uint32_t unused;
++01518         uint32_t doepdmab;
++01519 } dwc_otg_dev_out_ep_regs_t;
++01520 
++01526 typedef union depctl_data {
++01528         uint32_t d32;
++01530         struct {
++01538                 unsigned mps:11;
++01539 #define DWC_DEP0CTL_MPS_64       0
++01540 #define DWC_DEP0CTL_MPS_32       1
++01541 #define DWC_DEP0CTL_MPS_16       2
++01542 #define DWC_DEP0CTL_MPS_8        3
++01543 
++01547                 unsigned nextep:4;
++01548 
++01550                 unsigned usbactep:1;
++01551 
++01566                 unsigned dpid:1;
++01567 
++01569                 unsigned naksts:1;
++01570 
++01576                 unsigned eptype:2;
++01577 
++01581                 unsigned snp:1;
++01582 
++01584                 unsigned stall:1;
++01585 
++01589                 unsigned txfnum:4;
++01590 
++01592                 unsigned cnak:1;
++01594                 unsigned snak:1;
++01603                 unsigned setd0pid:1;
++01611                 unsigned setd1pid:1;
++01612 
++01614                 unsigned epdis:1;
++01616                 unsigned epena:1;
++01617         } b;
++01618 } depctl_data_t;
++01619 
++01625 typedef union deptsiz_data {
++01627         uint32_t d32;
++01629         struct {
++01631                 unsigned xfersize:19;
++01633 #define MAX_PKT_CNT 1023
++01634 
++01635                 unsigned pktcnt:10;
++01637                 unsigned mc:2;
++01638                 unsigned reserved:1;
++01639         } b;
++01640 } deptsiz_data_t;
++01641 
++01647 typedef union deptsiz0_data {
++01649         uint32_t d32;
++01651         struct {
++01653                 unsigned xfersize:7;
++01655                 unsigned reserved7_18:12;
++01657                 unsigned pktcnt:2;
++01659                 unsigned reserved21_28:8;
++01661                 unsigned supcnt:2;
++01662                 unsigned reserved31;
++01663         } b;
++01664 } deptsiz0_data_t;
++01665 
++01667 // DMA Descriptor Specific Structures
++01668 //
++01669 
++01672 #define BS_HOST_READY   0x0
++01673 #define BS_DMA_BUSY             0x1
++01674 #define BS_DMA_DONE             0x2
++01675 #define BS_HOST_BUSY    0x3
++01676 
++01679 #define RTS_SUCCESS             0x0
++01680 #define RTS_BUFFLUSH    0x1
++01681 #define RTS_RESERVED    0x2
++01682 #define RTS_BUFERR              0x3
++01683 
++01690 typedef union dev_dma_desc_sts {
++01692         uint32_t d32;
++01694         struct {
++01696                 unsigned bytes:16;
++01698                 unsigned nak:1;
++01699                 unsigned reserved17_22:6;
++01701                 unsigned mtrf:1;
++01703                 unsigned sr:1;
++01705                 unsigned ioc:1;
++01707                 unsigned sp:1;
++01709                 unsigned l:1;
++01711                 unsigned sts:2;
++01713                 unsigned bs:2;
++01714         } b;
++01715 
++01716 //#ifdef DWC_EN_ISOC
++01718         struct {
++01720                 unsigned rxbytes:11;
++01721 
++01722                 unsigned reserved11:1;
++01724                 unsigned framenum:11;
++01726                 unsigned pid:2;
++01728                 unsigned ioc:1;
++01730                 unsigned sp:1;
++01732                 unsigned l:1;
++01734                 unsigned rxsts:2;
++01736                 unsigned bs:2;
++01737         } b_iso_out;
++01738 
++01740         struct {
++01742                 unsigned txbytes:12;
++01744                 unsigned framenum:11;
++01746                 unsigned pid:2;
++01748                 unsigned ioc:1;
++01750                 unsigned sp:1;
++01752                 unsigned l:1;
++01754                 unsigned txsts:2;
++01756                 unsigned bs:2;
++01757         } b_iso_in;
++01758 //#endif                                /* DWC_EN_ISOC */
++01759 } dev_dma_desc_sts_t;
++01760 
++01767 typedef struct dwc_otg_dev_dma_desc {
++01769         dev_dma_desc_sts_t status;
++01771         uint32_t buf;
++01772 } dwc_otg_dev_dma_desc_t;
++01773 
++01779 typedef struct dwc_otg_dev_if {
++01783         dwc_otg_device_global_regs_t *dev_global_regs;
++01784 #define DWC_DEV_GLOBAL_REG_OFFSET 0x800
++01785 
++01789         dwc_otg_dev_in_ep_regs_t *in_ep_regs[MAX_EPS_CHANNELS];
++01790 #define DWC_DEV_IN_EP_REG_OFFSET 0x900
++01791 #define DWC_EP_REG_OFFSET 0x20
++01792 
++01794         dwc_otg_dev_out_ep_regs_t *out_ep_regs[MAX_EPS_CHANNELS];
++01795 #define DWC_DEV_OUT_EP_REG_OFFSET 0xB00
++01796 
++01797         /* Device configuration information */
++01798         uint8_t speed;                           
++01799         uint8_t num_in_eps;              
++01800         uint8_t num_out_eps;             
++01803         uint16_t perio_tx_fifo_size[MAX_PERIO_FIFOS];
++01804 
++01806         uint16_t tx_fifo_size[MAX_TX_FIFOS];
++01807 
++01809         uint16_t rx_thr_en;
++01810         uint16_t iso_tx_thr_en;
++01811         uint16_t non_iso_tx_thr_en;
++01812 
++01813         uint16_t rx_thr_length;
++01814         uint16_t tx_thr_length;
++01815 
++01822         dwc_dma_t dma_setup_desc_addr[2];
++01823         dwc_otg_dev_dma_desc_t *setup_desc_addr[2];
++01824 
++01826         dwc_otg_dev_dma_desc_t *psetup;
++01827 
++01829         uint32_t setup_desc_index;
++01830 
++01832         dwc_dma_t dma_in_desc_addr;
++01833         dwc_otg_dev_dma_desc_t *in_desc_addr;
++01834 
++01836         dwc_dma_t dma_out_desc_addr;
++01837         dwc_otg_dev_dma_desc_t *out_desc_addr;
++01838 
++01840         uint32_t spd;
++01842         void *isoc_ep;
++01843 
++01844 } dwc_otg_dev_if_t;
++01845 
++01847 // Host Mode Register Structures
++01848 //
++01854 typedef struct dwc_otg_host_global_regs {
++01856         volatile uint32_t hcfg;
++01858         volatile uint32_t hfir;
++01860         volatile uint32_t hfnum;
++01862         uint32_t reserved40C;
++01864         volatile uint32_t hptxsts;
++01866         volatile uint32_t haint;
++01868         volatile uint32_t haintmsk;
++01870         volatile uint32_t hflbaddr;
++01871 } dwc_otg_host_global_regs_t;
++01872 
++01878 typedef union hcfg_data {
++01880         uint32_t d32;
++01881 
++01883         struct {
++01885                 unsigned fslspclksel:2;
++01886 #define DWC_HCFG_30_60_MHZ 0
++01887 #define DWC_HCFG_48_MHZ    1
++01888 #define DWC_HCFG_6_MHZ     2
++01889 
++01891                 unsigned fslssupp:1;
++01892                 unsigned reserved3_6:4;
++01894                 unsigned ena32khzs:1;
++01896                 unsigned resvalid:8;
++01897                 unsigned reserved16_22:7;
++01899                 unsigned descdma:1;
++01901                 unsigned frlisten:2;
++01903                 unsigned perschedena:1;
++01904                 unsigned reserved27_30:4;
++01905                 unsigned modechtimen:1;
++01906         } b;
++01907 } hcfg_data_t;
++01908 
++01913 typedef union hfir_data {
++01915         uint32_t d32;
++01916 
++01918         struct {
++01919                 unsigned frint:16;
++01920                 unsigned hfirrldctrl:1;
++01921                 unsigned reserved:15;
++01922         } b;
++01923 } hfir_data_t;
++01924 
++01929 typedef union hfnum_data {
++01931         uint32_t d32;
++01932 
++01934         struct {
++01935                 unsigned frnum:16;
++01936 #define DWC_HFNUM_MAX_FRNUM 0x3FFF
++01937                 unsigned frrem:16;
++01938         } b;
++01939 } hfnum_data_t;
++01940 
++01941 typedef union hptxsts_data {
++01943         uint32_t d32;
++01944 
++01946         struct {
++01947                 unsigned ptxfspcavail:16;
++01948                 unsigned ptxqspcavail:8;
++01958                 unsigned ptxqtop_terminate:1;
++01959                 unsigned ptxqtop_token:2;
++01960                 unsigned ptxqtop_chnum:4;
++01961                 unsigned ptxqtop_odd:1;
++01962         } b;
++01963 } hptxsts_data_t;
++01964 
++01971 typedef union hprt0_data {
++01973         uint32_t d32;
++01975         struct {
++01976                 unsigned prtconnsts:1;
++01977                 unsigned prtconndet:1;
++01978                 unsigned prtena:1;
++01979                 unsigned prtenchng:1;
++01980                 unsigned prtovrcurract:1;
++01981                 unsigned prtovrcurrchng:1;
++01982                 unsigned prtres:1;
++01983                 unsigned prtsusp:1;
++01984                 unsigned prtrst:1;
++01985                 unsigned reserved9:1;
++01986                 unsigned prtlnsts:2;
++01987                 unsigned prtpwr:1;
++01988                 unsigned prttstctl:4;
++01989                 unsigned prtspd:2;
++01990 #define DWC_HPRT0_PRTSPD_HIGH_SPEED 0
++01991 #define DWC_HPRT0_PRTSPD_FULL_SPEED 1
++01992 #define DWC_HPRT0_PRTSPD_LOW_SPEED      2
++01993                 unsigned reserved19_31:13;
++01994         } b;
++01995 } hprt0_data_t;
++01996 
++02001 typedef union haint_data {
++02003         uint32_t d32;
++02005         struct {
++02006                 unsigned ch0:1;
++02007                 unsigned ch1:1;
++02008                 unsigned ch2:1;
++02009                 unsigned ch3:1;
++02010                 unsigned ch4:1;
++02011                 unsigned ch5:1;
++02012                 unsigned ch6:1;
++02013                 unsigned ch7:1;
++02014                 unsigned ch8:1;
++02015                 unsigned ch9:1;
++02016                 unsigned ch10:1;
++02017                 unsigned ch11:1;
++02018                 unsigned ch12:1;
++02019                 unsigned ch13:1;
++02020                 unsigned ch14:1;
++02021                 unsigned ch15:1;
++02022                 unsigned reserved:16;
++02023         } b;
++02024 
++02025         struct {
++02026                 unsigned chint:16;
++02027                 unsigned reserved:16;
++02028         } b2;
++02029 } haint_data_t;
++02030 
++02035 typedef union haintmsk_data {
++02037         uint32_t d32;
++02039         struct {
++02040                 unsigned ch0:1;
++02041                 unsigned ch1:1;
++02042                 unsigned ch2:1;
++02043                 unsigned ch3:1;
++02044                 unsigned ch4:1;
++02045                 unsigned ch5:1;
++02046                 unsigned ch6:1;
++02047                 unsigned ch7:1;
++02048                 unsigned ch8:1;
++02049                 unsigned ch9:1;
++02050                 unsigned ch10:1;
++02051                 unsigned ch11:1;
++02052                 unsigned ch12:1;
++02053                 unsigned ch13:1;
++02054                 unsigned ch14:1;
++02055                 unsigned ch15:1;
++02056                 unsigned reserved:16;
++02057         } b;
++02058 
++02059         struct {
++02060                 unsigned chint:16;
++02061                 unsigned reserved:16;
++02062         } b2;
++02063 } haintmsk_data_t;
++02064 
++02068 typedef struct dwc_otg_hc_regs {
++02070         volatile uint32_t hcchar;
++02072         volatile uint32_t hcsplt;
++02074         volatile uint32_t hcint;
++02076         volatile uint32_t hcintmsk;
++02078         volatile uint32_t hctsiz;
++02080         volatile uint32_t hcdma;
++02081         volatile uint32_t reserved;
++02083         volatile uint32_t hcdmab;
++02084 } dwc_otg_hc_regs_t;
++02085 
++02092 typedef union hcchar_data {
++02094         uint32_t d32;
++02095 
++02097         struct {
++02099                 unsigned mps:11;
++02100 
++02102                 unsigned epnum:4;
++02103 
++02105                 unsigned epdir:1;
++02106 
++02107                 unsigned reserved:1;
++02108 
++02110                 unsigned lspddev:1;
++02111 
++02113                 unsigned eptype:2;
++02114 
++02116                 unsigned multicnt:2;
++02117 
++02119                 unsigned devaddr:7;
++02120 
++02125                 unsigned oddfrm:1;
++02126 
++02128                 unsigned chdis:1;
++02129 
++02131                 unsigned chen:1;
++02132         } b;
++02133 } hcchar_data_t;
++02134 
++02135 typedef union hcsplt_data {
++02137         uint32_t d32;
++02138 
++02140         struct {
++02142                 unsigned prtaddr:7;
++02143 
++02145                 unsigned hubaddr:7;
++02146 
++02148                 unsigned xactpos:2;
++02149 #define DWC_HCSPLIT_XACTPOS_MID 0
++02150 #define DWC_HCSPLIT_XACTPOS_END 1
++02151 #define DWC_HCSPLIT_XACTPOS_BEGIN 2
++02152 #define DWC_HCSPLIT_XACTPOS_ALL 3
++02153 
++02155                 unsigned compsplt:1;
++02156 
++02158                 unsigned reserved:14;
++02159 
++02161                 unsigned spltena:1;
++02162         } b;
++02163 } hcsplt_data_t;
++02164 
++02169 typedef union hcint_data {
++02171         uint32_t d32;
++02173         struct {
++02175                 unsigned xfercomp:1;
++02177                 unsigned chhltd:1;
++02179                 unsigned ahberr:1;
++02181                 unsigned stall:1;
++02183                 unsigned nak:1;
++02185                 unsigned ack:1;
++02187                 unsigned nyet:1;
++02189                 unsigned xacterr:1;
++02191                 unsigned bblerr:1;
++02193                 unsigned frmovrun:1;
++02195                 unsigned datatglerr:1;
++02197                 unsigned bna:1;
++02199                 unsigned xcs_xact:1;
++02201                 unsigned frm_list_roll:1;
++02203                 unsigned reserved14_31:18;
++02204         } b;
++02205 } hcint_data_t;
++02206 
++02213 typedef union hcintmsk_data {
++02215         uint32_t d32;
++02216 
++02218         struct {
++02219                 unsigned xfercompl:1;
++02220                 unsigned chhltd:1;
++02221                 unsigned ahberr:1;
++02222                 unsigned stall:1;
++02223                 unsigned nak:1;
++02224                 unsigned ack:1;
++02225                 unsigned nyet:1;
++02226                 unsigned xacterr:1;
++02227                 unsigned bblerr:1;
++02228                 unsigned frmovrun:1;
++02229                 unsigned datatglerr:1;
++02230                 unsigned bna:1;
++02231                 unsigned xcs_xact:1;
++02232                 unsigned frm_list_roll:1;
++02233                 unsigned reserved14_31:18;
++02234         } b;
++02235 } hcintmsk_data_t;
++02236 
++02244 typedef union hctsiz_data {
++02246         uint32_t d32;
++02247 
++02249         struct {
++02251                 unsigned xfersize:19;
++02252 
++02254                 unsigned pktcnt:10;
++02255 
++02263                 unsigned pid:2;
++02264 #define DWC_HCTSIZ_DATA0 0
++02265 #define DWC_HCTSIZ_DATA1 2
++02266 #define DWC_HCTSIZ_DATA2 1
++02267 #define DWC_HCTSIZ_MDATA 3
++02268 #define DWC_HCTSIZ_SETUP 3
++02269 
++02271                 unsigned dopng:1;
++02272         } b;
++02273 
++02275         struct {
++02277                 unsigned schinfo:8;
++02278 
++02284                 unsigned ntd:8;
++02285 
++02287                 unsigned reserved16_28:13;
++02288 
++02296                 unsigned pid:2;
++02297 
++02299                 unsigned dopng:1;
++02300         } b_ddma;
++02301 } hctsiz_data_t;
++02302 
++02307 typedef union hcdma_data {
++02309         uint32_t d32;
++02311         struct {
++02312                 unsigned reserved0_2:3;
++02314                 unsigned ctd:8;
++02316                 unsigned dma_addr:21;
++02317         } b;
++02318 } hcdma_data_t;
++02319 
++02325 typedef union host_dma_desc_sts {
++02327         uint32_t d32;
++02330         /* for non-isochronous  */
++02331         struct {
++02333                 unsigned n_bytes:17;
++02335                 unsigned qtd_offset:6;
++02340                 unsigned a_qtd:1;
++02345                 unsigned sup:1;
++02347                 unsigned ioc:1;
++02349                 unsigned eol:1;
++02350                 unsigned reserved27:1;
++02352                 unsigned sts:2;
++02353 #define DMA_DESC_STS_PKTERR     1
++02354                 unsigned reserved30:1;
++02356                 unsigned a:1;
++02357         } b;
++02358         /* for isochronous */
++02359         struct {
++02361                 unsigned n_bytes:12;
++02362                 unsigned reserved12_24:13;
++02364                 unsigned ioc:1;
++02365                 unsigned reserved26_27:2;
++02367                 unsigned sts:2;
++02368                 unsigned reserved30:1;
++02370                 unsigned a:1;
++02371         } b_isoc;
++02372 } host_dma_desc_sts_t;
++02373 
++02374 #define MAX_DMA_DESC_SIZE               131071
++02375 #define MAX_DMA_DESC_NUM_GENERIC        64
++02376 #define MAX_DMA_DESC_NUM_HS_ISOC        256
++02377 #define MAX_FRLIST_EN_NUM               64
++02378 
++02384 typedef struct dwc_otg_host_dma_desc {
++02386         host_dma_desc_sts_t status;
++02388         uint32_t buf;
++02389 } dwc_otg_host_dma_desc_t;
++02390 
++02398 typedef struct dwc_otg_host_if {
++02400         dwc_otg_host_global_regs_t *host_global_regs;
++02401 #define DWC_OTG_HOST_GLOBAL_REG_OFFSET 0x400
++02402 
++02404         volatile uint32_t *hprt0;
++02405 #define DWC_OTG_HOST_PORT_REGS_OFFSET 0x440
++02406 
++02408         dwc_otg_hc_regs_t *hc_regs[MAX_EPS_CHANNELS];
++02409 #define DWC_OTG_HOST_CHAN_REGS_OFFSET 0x500
++02410 #define DWC_OTG_CHAN_REGS_OFFSET 0x20
++02411 
++02412         /* Host configuration information */
++02414         uint8_t num_host_channels;
++02416         uint8_t perio_eps_supported;
++02418         uint16_t perio_tx_fifo_size;
++02419 
++02420 } dwc_otg_host_if_t;
++02421 
++02427 typedef union pcgcctl_data {
++02429         uint32_t d32;
++02430 
++02432         struct {
++02434                 unsigned stoppclk:1;
++02436                 unsigned gatehclk:1;
++02438                 unsigned pwrclmp:1;
++02440                 unsigned rstpdwnmodule:1;
++02442                 unsigned reserved:1;
++02444                 unsigned enbl_sleep_gating:1;
++02446                 unsigned phy_in_sleep:1;
++02448                 unsigned deep_sleep:1;
++02449                 unsigned resetaftsusp:1;
++02450                 unsigned restoremode:1;
++02451                 unsigned reserved10_12:3;
++02452                 unsigned ess_reg_restored:1;
++02453                 unsigned prt_clk_sel:2;
++02454                 unsigned port_power:1;
++02455                 unsigned max_xcvrselect:2;
++02456                 unsigned max_termsel:1;
++02457                 unsigned mac_dev_addr:7;
++02458                 unsigned p2hd_dev_enum_spd:2;
++02459                 unsigned p2hd_prt_spd:2;
++02460                 unsigned if_dev_mode:1;
++02461         } b;
++02462 } pcgcctl_data_t;
++02463 
++02469 typedef union gdfifocfg_data {
++02470         /* raw register data */
++02471         uint32_t d32;
++02473         struct {
++02475                 unsigned gdfifocfg:16;
++02477                 unsigned epinfobase:16;
++02478         } b;
++02479 } gdfifocfg_data_t;
++02480 
++02486 typedef union gpwrdn_data {
++02487         /* raw register data */
++02488         uint32_t d32;
++02489 
++02491         struct {
++02493                 unsigned pmuintsel:1;
++02495                 unsigned pmuactv:1;
++02497                 unsigned restore:1;
++02499                 unsigned pwrdnclmp:1;
++02501                 unsigned pwrdnrstn:1;
++02503                 unsigned pwrdnswtch:1;
++02505                 unsigned dis_vbus:1;
++02507                 unsigned lnstschng:1;
++02509                 unsigned lnstchng_msk:1;
++02511                 unsigned rst_det:1;
++02513                 unsigned rst_det_msk:1;
++02515                 unsigned disconn_det:1;
++02517                 unsigned disconn_det_msk:1;
++02519                 unsigned connect_det:1;
++02521                 unsigned connect_det_msk:1;
++02523                 unsigned srp_det:1;
++02525                 unsigned srp_det_msk:1;
++02527                 unsigned sts_chngint:1;
++02529                 unsigned sts_chngint_msk:1;
++02531                 unsigned linestate:2;
++02533                 unsigned idsts:1;
++02535                 unsigned bsessvld:1;
++02537                 unsigned adp_int:1;
++02539                 unsigned mult_val_id_bc:5;
++02541                 unsigned reserved29_31:3;
++02542         } b;
++02543 } gpwrdn_data_t;
++02544 
++02545 #endif
++
      Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
      ++doxygen 1.3.9.1 + + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__regs_8h.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/dwc__otg__regs_8h.html 2013-07-26 19:31:22.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__regs_8h.html 2013-07-26 19:34:42.000000000 +0000 +@@ -2,24 +2,12 @@ + + DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_regs.h File Reference + +- + +- +-
      +-
      +-
      +-
      ++ ++
      Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
      +

      dwc_otg_regs.h File Reference

      This file contains the data structures for accessing the DWC_otg core registers. More... +

      +-#include "dwc_otg_core_if.h"
      ++#include "dwc_otg_core_if.h"
      + +

      + Go to the source code of this file. +@@ -40,9 +28,6 @@ + + + +- +- +- + + + +@@ -70,6 +55,18 @@ + + + ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ + + + +@@ -82,6 +79,12 @@ + + + ++ ++ ++ ++ ++ ++ + + + +@@ -108,9 +111,7 @@ + + + +- ++ + + + +@@ -134,7 +135,7 @@ + + + +- ++ + + + +@@ -147,7 +148,7 @@ + + + +- ++ + + + +@@ -164,7 +165,7 @@ + + + +- ++ + + + +@@ -190,484 +191,513 @@ + + + ++ ++ ++ ++ ++ ++ + +- ++ ++ ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ ++ + + +- ++ + +- ++ + +- ++ + +- ++ + + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + + +- +- +- +- ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + + +- ++ + + +- ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ + + +- ++ + +- +- ++ ++ + + +- ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + + +- ++ + + +- ++ + +- ++ + +- +- ++ ++ + + +- ++ + + +- ++ + +- +- ++ ++ + +- +- ++ ++ + +- ++ + + +- ++ + +- +- ++ ++ + +- +- ++ ++ + + +- ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- ++ ++ ++ ++ ++ ++ ++ +
      union  gusbcfg_data
       This union represents the bit fields of the Core USB Configuration Register (GUSBCFG). More...
      union  glpmctl_data
       This union represents the bit fields of the Core LPM Configuration Register (GLPMCFG). More...
      union  grstctl_data
       This union represents the bit fields of the Core Reset Register (GRSTCTL). More...
      union  gi2cctl_data
       This union represents the bit fields in the I2C Control Register (I2CCTL). More...
      union  gpvndctl_data
       This union represents the bit fields in the PHY Vendor Control Register (GPVNDCTL). More...
      union  ggpio_data
       This union represents the bit fields in the General Purpose Input/Output Register (GGPIO). More...
      union  guid_data
       This union represents the bit fields in the User ID Register (GUID). More...
      union  gsnpsid_data
       This union represents the bit fields in the Synopsys ID Register (GSNPSID). More...
      union  hwcfg1_data
       This union represents the bit fields in the User HW Config1 Register. More...
      union  hwcfg4_data
       This union represents the bit fields in the User HW Config4 Register. More...
      union  glpmctl_data
       This union represents the bit fields of the Core LPM Configuration Register (GLPMCFG). More...
      union  adpctl_data
       This union represents the bit fields of the Core ADP Timer, Control and Status Register (ADPTIMCTLSTS). More...
      struct  dwc_otg_dev_global_regs
       Device Global Registers. More...
       This union represents the bit fields in the Device IN Token Queue Read Registers. More...
      union  dthrctl_data
       This union represents Threshold control Register
        +-
      • Read and write the register into the d32 member.
      +- More...
       This union represents Threshold control Register Read and write the register into the d32 member. More...
      struct  dwc_otg_dev_in_ep_regs
       Device Logical IN Endpoint-Specific Registers. More...
       DMA Descriptor structure. More...
      struct  dwc_otg_dev_if
       The dwc_otg_dev_if structure contains information needed to manage the DWC_otg controller acting in device mode. More...
       The dwc_otg_dev_if structure contains information needed to manage the DWC_otg controller acting in device mode. More...
      struct  dwc_otg_host_global_regs
       The Host Global Registers structure defines the size and relative field offsets for the Host Mode Global Registers. More...
      union  hfnum_data
       This union represents the bit fields in the Host Frame Remaing/Number Register. More...
      union  hptxsts_data
      union  hptxsts_data
      union  hprt0_data
      union  hcchar_data
       This union represents the bit fields in the Host Channel Characteristics Register. More...
      union  hcsplt_data
      union  hcsplt_data
      union  hcint_data
      union  pcgcctl_data
       This union represents the bit fields in the Power and Clock Gating Control Register. More...
      union  gdfifocfg_data
       This union represents the bit fields in the Global Data FIFO Software Configuration Register. More...
      union  gpwrdn_data
       This union represents the bit fields in the Global Power Down Register Register. More...

      Defines

      +-#define DWC_GLBINTRMASK   0x0001
      ++#define DWC_GLBINTRMASK   0x0001
      ++#define DWC_DMAENABLE   0x0020
      +-#define DWC_DMAENABLE   0x0020
      ++#define DWC_NPTXEMPTYLVL_EMPTY   0x0080
      +-#define DWC_NPTXEMPTYLVL_EMPTY   0x0080
      ++#define DWC_NPTXEMPTYLVL_HALFEMPTY   0x0000
      +-#define DWC_NPTXEMPTYLVL_HALFEMPTY   0x0000
      ++#define DWC_PTXEMPTYLVL_EMPTY   0x0100
      +-#define DWC_PTXEMPTYLVL_EMPTY   0x0100
      ++#define DWC_PTXEMPTYLVL_HALFEMPTY   0x0000
      +-#define DWC_PTXEMPTYLVL_HALFEMPTY   0x0000
      ++#define DWC_SLAVE_ONLY_ARCH   0
      +-#define DWC_SLAVE_ONLY_ARCH   0
      ++#define DWC_EXT_DMA_ARCH   1
      +-#define DWC_EXT_DMA_ARCH   1
      ++#define DWC_INT_DMA_ARCH   2
      +-#define DWC_INT_DMA_ARCH   2
      ++#define DWC_MODE_HNP_SRP_CAPABLE   0
      +-#define DWC_MODE_HNP_SRP_CAPABLE   0
      ++#define DWC_MODE_SRP_ONLY_CAPABLE   1
      +-#define DWC_MODE_SRP_ONLY_CAPABLE   1
      ++#define DWC_MODE_NO_HNP_SRP_CAPABLE   2
      +-#define DWC_MODE_NO_HNP_SRP_CAPABLE   2
      ++#define DWC_MODE_SRP_CAPABLE_DEVICE   3
      +-#define DWC_MODE_SRP_CAPABLE_DEVICE   3
      ++#define DWC_MODE_NO_SRP_CAPABLE_DEVICE   4
      +-#define DWC_MODE_NO_SRP_CAPABLE_DEVICE   4
      ++#define DWC_MODE_SRP_CAPABLE_HOST   5
      +-#define DWC_MODE_SRP_CAPABLE_HOST   5
      ++#define DWC_MODE_NO_SRP_CAPABLE_HOST   6
      +-#define DWC_MODE_NO_SRP_CAPABLE_HOST   6
      ++#define DWC_GAHBCFG_GLBINT_ENABLE   1
      +-#define DWC_GAHBCFG_GLBINT_ENABLE   1
      ++#define DWC_GAHBCFG_INT_DMA_BURST_SINGLE   0
      +-#define DWC_GAHBCFG_INT_DMA_BURST_SINGLE   0
      ++#define DWC_GAHBCFG_INT_DMA_BURST_INCR   1
      +-#define DWC_GAHBCFG_INT_DMA_BURST_INCR   1
      ++#define DWC_GAHBCFG_INT_DMA_BURST_INCR4   3
      +-#define DWC_GAHBCFG_INT_DMA_BURST_INCR4   3
      ++#define DWC_GAHBCFG_INT_DMA_BURST_INCR8   5
      +-#define DWC_GAHBCFG_INT_DMA_BURST_INCR8   5
      ++#define DWC_GAHBCFG_INT_DMA_BURST_INCR16   7
      +-#define DWC_GAHBCFG_INT_DMA_BURST_INCR16   7
      ++#define DWC_GAHBCFG_DMAENABLE   1
      +-#define DWC_GAHBCFG_DMAENABLE   1
      ++#define DWC_GAHBCFG_TXFEMPTYLVL_EMPTY   1
      +-#define DWC_GAHBCFG_TXFEMPTYLVL_EMPTY   1
      ++#define DWC_GAHBCFG_TXFEMPTYLVL_HALFEMPTY   0
      +-#define DWC_GAHBCFG_TXFEMPTYLVL_HALFEMPTY   0
      ++#define DWC_SOF_INTR_MASK   0x0008
      +-#define DWC_SOF_INTR_MASK   0x0008
      ++#define DWC_HOST_MODE   1
      +-#define DWC_HOST_MODE   1
      ++#define DWC_STS_DATA_UPDT   0x2
      +-#define DWC_STS_DATA_UPDT   0x2
      ++#define DWC_STS_XFER_COMP   0x3
      +-#define DWC_STS_XFER_COMP   0x3
      ++#define DWC_DSTS_GOUT_NAK   0x1
      +-#define DWC_DSTS_GOUT_NAK   0x1
      ++#define DWC_DSTS_SETUP_COMP   0x4
      +-#define DWC_DSTS_SETUP_COMP   0x4
      ++#define DWC_DSTS_SETUP_UPDT   0x6
      +-#define DWC_DSTS_SETUP_UPDT   0x6
      ++#define DWC_GRXSTS_PKTSTS_IN   0x2
      +-#define DWC_GRXSTS_PKTSTS_IN   0x2
      ++#define DWC_GRXSTS_PKTSTS_IN_XFER_COMP   0x3
      +-#define DWC_GRXSTS_PKTSTS_IN_XFER_COMP   0x3
      ++#define DWC_GRXSTS_PKTSTS_DATA_TOGGLE_ERR   0x5
      +-#define DWC_GRXSTS_PKTSTS_DATA_TOGGLE_ERR   0x5
      ++#define DWC_GRXSTS_PKTSTS_CH_HALTED   0x7
      +-#define DWC_GRXSTS_PKTSTS_CH_HALTED   0x7
      ++#define DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG   0
      +-#define DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG   0
      ++#define DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG   1
      +-#define DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG   1
      ++#define DWC_HWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE_OTG   2
      +-#define DWC_HWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE_OTG   2
      ++#define DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE   3
      +-#define DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE   3
      ++#define DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE   4
      +-#define DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE   4
      ++#define DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST   5
      +-#define DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST   5
      ++#define DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST   6
      +-#define DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST   6
      ++#define DWC_HWCFG2_HS_PHY_TYPE_NOT_SUPPORTED   0
      +-#define DWC_HWCFG2_HS_PHY_TYPE_NOT_SUPPORTED   0
      ++#define DWC_HWCFG2_HS_PHY_TYPE_UTMI   1
      +-#define DWC_HWCFG2_HS_PHY_TYPE_UTMI   1
      ++#define DWC_HWCFG2_HS_PHY_TYPE_ULPI   2
      +-#define DWC_HWCFG2_HS_PHY_TYPE_ULPI   2
      ++#define DWC_HWCFG2_HS_PHY_TYPE_UTMI_ULPI   3
      +-#define DWC_HWCFG2_HS_PHY_TYPE_UTMI_ULPI   3
      ++#define DWC_DCFG_SEND_STALL   1
      +-#define DWC_DCFG_SEND_STALL   1
      ++#define DWC_DCFG_FRAME_INTERVAL_80   0
      +-#define DWC_DCFG_FRAME_INTERVAL_80   0
      ++#define DWC_DCFG_FRAME_INTERVAL_85   1
      +-#define DWC_DCFG_FRAME_INTERVAL_85   1
      ++#define DWC_DCFG_FRAME_INTERVAL_90   2
      +-#define DWC_DCFG_FRAME_INTERVAL_90   2
      ++#define DWC_DCFG_FRAME_INTERVAL_95   3
      +-#define DWC_DCFG_FRAME_INTERVAL_95   3
      ++#define DWC_DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ   0
      +-#define DWC_DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ   0
      ++#define DWC_DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ   1
      +-#define DWC_DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ   1
      ++#define DWC_DSTS_ENUMSPD_LS_PHY_6MHZ   2
      +-#define DWC_DSTS_ENUMSPD_LS_PHY_6MHZ   2
      ++#define DWC_DSTS_ENUMSPD_FS_PHY_48MHZ   3
      +-#define DWC_DSTS_ENUMSPD_FS_PHY_48MHZ   3
      ++#define DWC_DEP0CTL_MPS_64   0
      +-#define DWC_DEP0CTL_MPS_64   0
      ++#define DWC_DEP0CTL_MPS_32   1
      +-#define DWC_DEP0CTL_MPS_32   1
      ++#define DWC_DEP0CTL_MPS_16   2
      +-#define DWC_DEP0CTL_MPS_16   2
      ++#define DWC_DEP0CTL_MPS_8   3
      +-#define DWC_DEP0CTL_MPS_8   3
      ++#define MAX_PKT_CNT   1023
      +-#define BS_HOST_READY   0x0
       Max packet count for EP (pow(2,10)-1).
      ++#define BS_HOST_READY   0x0
       Buffer status definitions.
      +-#define BS_DMA_BUSY   0x1
      ++#define BS_DMA_BUSY   0x1
      +-#define BS_DMA_DONE   0x2
      ++#define BS_DMA_DONE   0x2
      +-#define BS_HOST_BUSY   0x3
      ++#define BS_HOST_BUSY   0x3
      +-#define RTS_SUCCESS   0x0
      ++#define RTS_SUCCESS   0x0
       Receive/Transmit status definitions.
      +-#define RTS_BUFFLUSH   0x1
      ++#define RTS_BUFFLUSH   0x1
      +-#define RTS_RESERVED   0x2
      ++#define RTS_RESERVED   0x2
      +-#define RTS_BUFERR   0x3
      ++#define RTS_BUFERR   0x3
      +-#define DWC_DEV_GLOBAL_REG_OFFSET   0x800
      ++#define DWC_DEV_GLOBAL_REG_OFFSET   0x800
      +-#define DWC_DEV_IN_EP_REG_OFFSET   0x900
      ++#define DWC_DEV_IN_EP_REG_OFFSET   0x900
      +-#define DWC_EP_REG_OFFSET   0x20
      ++#define DWC_EP_REG_OFFSET   0x20
      +-#define DWC_DEV_OUT_EP_REG_OFFSET   0xB00
      ++#define DWC_DEV_OUT_EP_REG_OFFSET   0xB00
      +-#define DWC_HCFG_30_60_MHZ   0
      ++#define DWC_HCFG_30_60_MHZ   0
      +-#define DWC_HCFG_48_MHZ   1
      ++#define DWC_HCFG_48_MHZ   1
      +-#define DWC_HCFG_6_MHZ   2
      ++#define DWC_HCFG_6_MHZ   2
      +-#define DWC_HFNUM_MAX_FRNUM   0x3FFF
      ++#define DWC_HFNUM_MAX_FRNUM   0x3FFF
      +-#define DWC_HPRT0_PRTSPD_HIGH_SPEED   0
      ++#define DWC_HPRT0_PRTSPD_HIGH_SPEED   0
      +-#define DWC_HPRT0_PRTSPD_FULL_SPEED   1
      ++#define DWC_HPRT0_PRTSPD_FULL_SPEED   1
      +-#define DWC_HPRT0_PRTSPD_LOW_SPEED   2
      ++#define DWC_HPRT0_PRTSPD_LOW_SPEED   2
      +-#define DWC_HCSPLIT_XACTPOS_MID   0
      ++#define DWC_HCSPLIT_XACTPOS_MID   0
      +-#define DWC_HCSPLIT_XACTPOS_END   1
      ++#define DWC_HCSPLIT_XACTPOS_END   1
      +-#define DWC_HCSPLIT_XACTPOS_BEGIN   2
      ++#define DWC_HCSPLIT_XACTPOS_BEGIN   2
      +-#define DWC_HCSPLIT_XACTPOS_ALL   3
      ++#define DWC_HCSPLIT_XACTPOS_ALL   3
      +-#define DWC_HCTSIZ_DATA0   0
      ++#define DWC_HCTSIZ_DATA0   0
      +-#define DWC_HCTSIZ_DATA1   2
      ++#define DWC_HCTSIZ_DATA1   2
      +-#define DWC_HCTSIZ_DATA2   1
      ++#define DWC_HCTSIZ_DATA2   1
      +-#define DWC_HCTSIZ_MDATA   3
      ++#define DWC_HCTSIZ_MDATA   3
      +-#define DWC_HCTSIZ_SETUP   3
      ++#define DWC_HCTSIZ_SETUP   3
      +-#define DMA_DESC_STS_PKTERR   1
      ++#define DMA_DESC_STS_PKTERR   1
      +-#define MAX_DMA_DESC_SIZE   131071
      ++#define MAX_DMA_DESC_SIZE   131071
      +-#define MAX_DMA_DESC_NUM_GENERIC   64
      ++#define MAX_DMA_DESC_NUM_GENERIC   64
      +-#define MAX_DMA_DESC_NUM_HS_ISOC   256
      ++#define MAX_DMA_DESC_NUM_HS_ISOC   256
      +-#define MAX_FRLIST_EN_NUM   64
      ++#define MAX_FRLIST_EN_NUM   64
      +-#define DWC_OTG_HOST_GLOBAL_REG_OFFSET   0x400
      ++#define DWC_OTG_HOST_GLOBAL_REG_OFFSET   0x400
      +-#define DWC_OTG_HOST_PORT_REGS_OFFSET   0x440
      ++#define DWC_OTG_HOST_PORT_REGS_OFFSET   0x440
      +-#define DWC_OTG_HOST_CHAN_REGS_OFFSET   0x500
      ++#define DWC_OTG_HOST_CHAN_REGS_OFFSET   0x500
      +-#define DWC_OTG_CHAN_REGS_OFFSET   0x20
      ++#define DWC_OTG_CHAN_REGS_OFFSET   0x20

      Typedefs

      typedef dwc_otg_core_global_regs dwc_otg_core_global_regs_t
       DWC_otg Core registers .
      typedef gotgctl_data gotgctl_data_t
      typedef dwc_otg_core_global_regs dwc_otg_core_global_regs_t
       This union represents the bit fields of the Core OTG Control and Status Register (GOTGCTL).
      typedef gotgint_data gotgint_data_t
       DWC_otg Core registers .
      typedef gotgctl_data gotgctl_data_t
       This union represents the bit fields of the Core OTG Interrupt Register (GOTGINT).
      typedef gahbcfg_data gahbcfg_data_t
       This union represents the bit fields of the Core OTG Control and Status Register (GOTGCTL).
      typedef gotgint_data gotgint_data_t
       This union represents the bit fields of the Core AHB Configuration Register (GAHBCFG).
      typedef gusbcfg_data gusbcfg_data_t
       This union represents the bit fields of the Core OTG Interrupt Register (GOTGINT).
      typedef gahbcfg_data gahbcfg_data_t
       This union represents the bit fields of the Core USB Configuration Register (GUSBCFG).
      typedef glpmctl_data glpmcfg_data_t
       This union represents the bit fields of the Core AHB Configuration Register (GAHBCFG).
      typedef gusbcfg_data gusbcfg_data_t
       This union represents the bit fields of the Core LPM Configuration Register (GLPMCFG).
      typedef grstctl_data grstctl_t
       This union represents the bit fields of the Core USB Configuration Register (GUSBCFG).
      typedef grstctl_data grstctl_t
       This union represents the bit fields of the Core Reset Register (GRSTCTL).
      typedef gintmsk_data gintmsk_data_t
       This union represents the bit fields of the Core Reset Register (GRSTCTL).
      typedef gintmsk_data gintmsk_data_t
       This union represents the bit fields of the Core Interrupt Mask Register (GINTMSK).
      typedef gintsts_data gintsts_data_t
       This union represents the bit fields of the Core Interrupt Mask Register (GINTMSK).
      typedef gintsts_data gintsts_data_t
       This union represents the bit fields of the Core Interrupt Register (GINTSTS).
      +-typedef device_grxsts_data device_grxsts_data_t
       This union represents the bit fields of the Core Interrupt Register (GINTSTS).
      ++typedef device_grxsts_data device_grxsts_data_t
       This union represents the bit fields in the Device Receive Status Read and Pop Registers (GRXSTSR, GRXSTSP) Read the register into the d32 element then read out the bits using the bit elements.
      +-typedef host_grxsts_data host_grxsts_data_t
      ++typedef host_grxsts_data host_grxsts_data_t
       This union represents the bit fields in the Host Receive Status Read and Pop Registers (GRXSTSR, GRXSTSP) Read the register into the d32 element then read out the bits using the bit elements.
      typedef fifosize_data fifosize_data_t
      typedef fifosize_data fifosize_data_t
       This union represents the bit fields in the FIFO Size Registers (HPTXFSIZ, GNPTXFSIZ, DPTXFSIZn, DIEPTXFn).
      typedef gnptxsts_data gnptxsts_data_t
       This union represents the bit fields in the Non-Periodic Transmit FIFO/Queue Status Register (GNPTXSTS).
      typedef dtxfsts_data dtxfsts_data_t
       This union represents the bit fields in the Transmit FIFO Status Register (DTXFSTS).
      typedef gi2cctl_data gi2cctl_data_t
       This union represents the bit fields in the FIFO Size Registers (HPTXFSIZ, GNPTXFSIZ, DPTXFSIZn, DIEPTXFn).
      typedef gnptxsts_data gnptxsts_data_t
       This union represents the bit fields in the I2C Control Register (I2CCTL).
      typedef gpvndctl_data gpvndctl_data_t
       This union represents the bit fields in the Non-Periodic Transmit FIFO/Queue Status Register (GNPTXSTS).
      typedef dtxfsts_data dtxfsts_data_t
       This union represents the bit fields in the PHY Vendor Control Register (GPVNDCTL).
      typedef ggpio_data ggpio_data_t
       This union represents the bit fields in the Transmit FIFO Status Register (DTXFSTS).
      typedef gi2cctl_data gi2cctl_data_t
       This union represents the bit fields in the General Purpose Input/Output Register (GGPIO).
      typedef guid_data guid_data_t
       This union represents the bit fields in the I2C Control Register (I2CCTL).
      typedef hwcfg1_data hwcfg1_data_t
       This union represents the bit fields in the User ID Register (GUID).
      typedef gsnpsid_data gsnpsid_data_t
       This union represents the bit fields in the User HW Config1 Register.
      typedef hwcfg2_data hwcfg2_data_t
       This union represents the bit fields in the Synopsys ID Register (GSNPSID).
      typedef hwcfg1_data hwcfg1_data_t
       This union represents the bit fields in the User HW Config2 Register.
      typedef hwcfg3_data hwcfg3_data_t
       This union represents the bit fields in the User HW Config1 Register.
      typedef hwcfg2_data hwcfg2_data_t
       This union represents the bit fields in the User HW Config3 Register.
      typedef hwcfg4_data hwcfg4_data_t
       This union represents the bit fields in the User HW Config2 Register.
      typedef hwcfg3_data hwcfg3_data_t
       This union represents the bit fields in the User HW Config4 Register.
      typedef dwc_otg_dev_global_regs dwc_otg_device_global_regs_t
       This union represents the bit fields in the User HW Config3 Register.
      typedef hwcfg4_data hwcfg4_data_t
       Device Global Registers.
      typedef dcfg_data dcfg_data_t
       This union represents the bit fields in the User HW Config4 Register.
      typedef glpmctl_data glpmcfg_data_t
       This union represents the bit fields in the Device Configuration Register.
      typedef dctl_data dctl_data_t
       This union represents the bit fields of the Core LPM Configuration Register (GLPMCFG).
      typedef adpctl_data adpctl_data_t
       This union represents the bit fields in the Device Control Register.
      typedef dsts_data dsts_data_t
       This union represents the bit fields of the Core ADP Timer, Control and Status Register (ADPTIMCTLSTS).
      typedef dwc_otg_dev_global_regs dwc_otg_device_global_regs_t
       This union represents the bit fields in the Device Status Register.
      typedef diepint_data diepint_data_t
       Device Global Registers.
      typedef dcfg_data dcfg_data_t
       This union represents the bit fields in the Device IN EP Interrupt Register and the Device IN EP Common Mask Register.
      +-typedef diepint_data diepmsk_data_t
       This union represents the bit fields in the Device Configuration Register.
      typedef dctl_data dctl_data_t
       This union represents the bit fields in the Device Control Register.
      typedef dsts_data dsts_data_t
       This union represents the bit fields in the Device Status Register.
      typedef diepint_data diepint_data_t
       This union represents the bit fields in the Device IN EP Interrupt Register and the Device IN EP Common Mask Register.
      ++typedef diepint_data diepmsk_data_t
       This union represents the bit fields in the Device IN EP Common/Dedicated Interrupt Mask Register.
      typedef doepint_data doepint_data_t
      typedef doepint_data doepint_data_t
       This union represents the bit fields in the Device OUT EP Interrupt Registerand Device OUT EP Common Interrupt Mask Register.
      +-typedef doepint_data doepmsk_data_t
       This union represents the bit fields in the Device OUT EP Interrupt Registerand Device OUT EP Common Interrupt Mask Register.
      ++typedef doepint_data doepmsk_data_t
       This union represents the bit fields in the Device OUT EP Common/Dedicated Interrupt Mask Register.
      typedef daint_data daint_data_t
      typedef daint_data daint_data_t
       This union represents the bit fields in the Device All EP Interrupt and Mask Registers.
      typedef dtknq1_data dtknq1_data_t
       This union represents the bit fields in the Device All EP Interrupt and Mask Registers.
      typedef dtknq1_data dtknq1_data_t
       This union represents the bit fields in the Device IN Token Queue Read Registers.
      typedef dthrctl_data dthrctl_data_t
       This union represents the bit fields in the Device IN Token Queue Read Registers.
      typedef dthrctl_data dthrctl_data_t
       This union represents Threshold control Register
        +-
      • Read and write the register into the d32 member.
      +-
      typedef dwc_otg_dev_in_ep_regs dwc_otg_dev_in_ep_regs_t
       This union represents Threshold control Register Read and write the register into the d32 member.
      typedef dwc_otg_dev_in_ep_regs dwc_otg_dev_in_ep_regs_t
       Device Logical IN Endpoint-Specific Registers.
      typedef dwc_otg_dev_out_ep_regs dwc_otg_dev_out_ep_regs_t
       Device Logical IN Endpoint-Specific Registers.
      typedef dwc_otg_dev_out_ep_regs dwc_otg_dev_out_ep_regs_t
       Device Logical OUT Endpoint-Specific Registers.
      typedef depctl_data depctl_data_t
       Device Logical OUT Endpoint-Specific Registers.
      typedef depctl_data depctl_data_t
       This union represents the bit fields in the Device EP Control Register.
      typedef deptsiz_data deptsiz_data_t
       This union represents the bit fields in the Device EP Control Register.
      typedef deptsiz_data deptsiz_data_t
       This union represents the bit fields in the Device EP Transfer Size Register.
      typedef deptsiz0_data deptsiz0_data_t
       This union represents the bit fields in the Device EP Transfer Size Register.
      typedef deptsiz0_data deptsiz0_data_t
       This union represents the bit fields in the Device EP 0 Transfer Size Register.
      typedef dev_dma_desc_sts dev_dma_desc_sts_t
       This union represents the bit fields in the Device EP 0 Transfer Size Register.
      typedef dev_dma_desc_sts dev_dma_desc_sts_t
       This union represents the bit fields in the DMA Descriptor status quadlet.
      typedef dwc_otg_dev_dma_desc dwc_otg_dev_dma_desc_t
       This union represents the bit fields in the DMA Descriptor status quadlet.
      typedef dwc_otg_dev_dma_desc dwc_otg_dev_dma_desc_t
       DMA Descriptor structure.
      typedef dwc_otg_dev_if dwc_otg_dev_if_t
       DMA Descriptor structure.
      typedef dwc_otg_dev_if dwc_otg_dev_if_t
       The dwc_otg_dev_if structure contains information needed to manage the DWC_otg controller acting in device mode.
      typedef dwc_otg_host_global_regs dwc_otg_host_global_regs_t
       The dwc_otg_dev_if structure contains information needed to manage the DWC_otg controller acting in device mode.
      typedef dwc_otg_host_global_regs dwc_otg_host_global_regs_t
       The Host Global Registers structure defines the size and relative field offsets for the Host Mode Global Registers.
      typedef hcfg_data hcfg_data_t
       The Host Global Registers structure defines the size and relative field offsets for the Host Mode Global Registers.
      typedef hcfg_data hcfg_data_t
       This union represents the bit fields in the Host Configuration Register.
      +-typedef hfir_data hfir_data_t
       This union represents the bit fields in the Host Configuration Register.
      ++typedef hfir_data hfir_data_t
       This union represents the bit fields in the Host Frame Remaing/Number Register.
      +-typedef hfnum_data hfnum_data_t
      ++typedef hfnum_data hfnum_data_t
       This union represents the bit fields in the Host Frame Remaing/Number Register.
      +-typedef hptxsts_data hptxsts_data_t
      ++typedef hptxsts_data hptxsts_data_t
      typedef hprt0_data hprt0_data_t
      typedef hprt0_data hprt0_data_t
       This union represents the bit fields in the Host Port Control and Status Register.
      +-typedef haint_data haint_data_t
       This union represents the bit fields in the Host Port Control and Status Register.
      ++typedef haint_data haint_data_t
       This union represents the bit fields in the Host All Interrupt Register.
      +-typedef haintmsk_data haintmsk_data_t
      ++typedef haintmsk_data haintmsk_data_t
       This union represents the bit fields in the Host All Interrupt Register.
      typedef dwc_otg_hc_regs dwc_otg_hc_regs_t
      typedef dwc_otg_hc_regs dwc_otg_hc_regs_t
       Host Channel Specific Registers.
      typedef hcchar_data hcchar_data_t
       Host Channel Specific Registers.
      typedef hcchar_data hcchar_data_t
       This union represents the bit fields in the Host Channel Characteristics Register.
      +-typedef hcsplt_data hcsplt_data_t
       This union represents the bit fields in the Host Channel Characteristics Register.
      ++typedef hcsplt_data hcsplt_data_t
      +-typedef hcint_data hcint_data_t
      ++typedef hcint_data hcint_data_t
       This union represents the bit fields in the Host All Interrupt Register.
      typedef hcintmsk_data hcintmsk_data_t
      typedef hcintmsk_data hcintmsk_data_t
       This union represents the bit fields in the Host Channel Interrupt Mask Register.
      typedef hctsiz_data hctsiz_data_t
       This union represents the bit fields in the Host Channel Interrupt Mask Register.
      typedef hctsiz_data hctsiz_data_t
       This union represents the bit fields in the Host Channel Transfer Size Register.
      +-typedef hcdma_data hcdma_data_t
       This union represents the bit fields in the Host Channel Transfer Size Register.
      ++typedef hcdma_data hcdma_data_t
       This union represents the bit fields in the Host DMA Address Register used in Descriptor DMA mode.
      typedef host_dma_desc_sts host_dma_desc_sts_t
      typedef host_dma_desc_sts host_dma_desc_sts_t
       This union represents the bit fields in the DMA Descriptor status quadlet for host mode.
      typedef dwc_otg_host_dma_desc dwc_otg_host_dma_desc_t
       This union represents the bit fields in the DMA Descriptor status quadlet for host mode.
      typedef dwc_otg_host_dma_desc dwc_otg_host_dma_desc_t
       Host-mode DMA Descriptor structure.
      typedef dwc_otg_host_if dwc_otg_host_if_t
       Host-mode DMA Descriptor structure.
      typedef dwc_otg_host_if dwc_otg_host_if_t
       OTG Host Interface Structure.
      typedef pcgcctl_data pcgcctl_data_t
       OTG Host Interface Structure.
      typedef pcgcctl_data pcgcctl_data_t
       This union represents the bit fields in the Power and Clock Gating Control Register.
       This union represents the bit fields in the Power and Clock Gating Control Register.
      typedef gdfifocfg_data gdfifocfg_data_t
       This union represents the bit fields in the Global Data FIFO Software Configuration Register.
      typedef gpwrdn_data gpwrdn_data_t
       This union represents the bit fields in the Global Power Down Register Register.
      +

      Detailed Description

      + This file contains the data structures for accessing the DWC_otg core registers. +@@ -675,794 +705,1327 @@ + The application interfaces with the HS OTG core by reading from and writing to the Control and Status Register (CSR) space through the AHB Slave interface. These registers are 32 bits wide, and the addresses are 32-bit-block aligned. CSRs are classified as follows:
        +
      • Core Global Registers
      • Device Mode Registers
      • Device Global Registers
      • Device Endpoint Specific Registers
      • Host Mode Registers
      • Host Global Registers
      • Host Port CSRs
      • Host Channel Specific Registers
      +

      +-Only the Core Global registers can be accessed in both Device and Host modes. When the HS OTG core is operating in one mode, either Device or Host, the application must not access registers from the other mode. When the core switches from one mode to another, the registers in the new mode of operation must be reprogrammed as they would be after a power-on reset. ++Only the Core Global registers can be accessed in both Device and Host modes. When the HS OTG core is operating in one mode, either Device or Host, the application must not access registers from the other mode. When the core switches from one mode to another, the registers in the new mode of operation must be reprogrammed as they would be after a power-on reset. +

      + Definition in file dwc_otg_regs.h.

      Typedef Documentation

      +- +-
      +-
      +- ++

      ++

      ++ ++ ++ ++
      ++ + +- ++ + +
      typedef struct dwc_otg_core_global_regs dwc_otg_core_global_regs_t typedef struct dwc_otg_core_global_regs dwc_otg_core_global_regs_t
      +- +-
      ++
      ++ ++ ++ ++
      ++   ++ + +

      + DWC_otg Core registers . +

      +-The dwc_otg_core_global_regs structure defines the size and relative field offsets for the Core Global registers. +- +-

      +- +-

      +-
      +- ++The dwc_otg_core_global_regs structure defines the size and relative field offsets for the Core Global registers. ++ ++
      ++

      ++ ++ ++ ++ ++
      ++ + +- ++ + +
      typedef union gotgctl_data gotgctl_data_t typedef union gotgctl_data gotgctl_data_t
      +- +-
      ++
      ++ ++ ++ ++
      ++   ++ + +

      + This union represents the bit fields of the Core OTG Control and Status Register (GOTGCTL). +

      +-Set the bits using the bit fields then write the d32 value to the register. +- +-

      +- +-

      +-
      +- ++Set the bits using the bit fields then write the d32 value to the register. ++ ++
      ++

      ++ ++ ++ ++ ++
      ++ + +- ++ + +
      typedef union gotgint_data gotgint_data_t typedef union gotgint_data gotgint_data_t
      +- +-
      ++
      ++ ++ ++ ++
      ++   ++ + +

      + This union represents the bit fields of the Core OTG Interrupt Register (GOTGINT). +

      +-Set/clear the bits using the bit fields then write the d32 value to the register. +- +-

      +- +-

      +-
      +- ++Set/clear the bits using the bit fields then write the d32 value to the register. ++ ++
      ++

      ++ ++ ++ ++ ++
      ++ + +- ++ + +
      typedef union gahbcfg_data gahbcfg_data_t typedef union gahbcfg_data gahbcfg_data_t
      +- +-
      ++
      ++ ++ ++ ++
      ++   ++ + +

      + This union represents the bit fields of the Core AHB Configuration Register (GAHBCFG). +

      +-Set/clear the bits using the bit fields then write the d32 value to the register. +- +-

      +- +-

      +-
      +- ++Set/clear the bits using the bit fields then write the d32 value to the register. ++ ++
      ++

      ++ ++ ++ ++ ++
      ++ + +- ++ + +
      typedef union gusbcfg_data gusbcfg_data_t typedef union gusbcfg_data gusbcfg_data_t
      +- +-
      ++
      ++ ++ ++ ++
      ++   ++ + +

      + This union represents the bit fields of the Core USB Configuration Register (GUSBCFG). +

      +-Set the bits using the bit fields then write the d32 value to the register. +- +-

      +- +-

      +-
      +- +- +- +- +-
      typedef union glpmctl_data glpmcfg_data_t
      +-
      +-
      +- +-

      +-This union represents the bit fields of the Core LPM Configuration Register (GLPMCFG). +-

      +-Set the bits using bit fields then write the d32 value to the register. +-

      +-

      +- +-

      +-
      +- ++Set the bits using the bit fields then write the d32 value to the register. ++ ++
      ++

      ++ ++ ++ ++ ++
      ++ + +- ++ + +
      typedef union grstctl_data grstctl_t typedef union grstctl_data grstctl_t
      +- +-
      ++
      ++ ++ ++ ++
      ++   ++ + +

      + This union represents the bit fields of the Core Reset Register (GRSTCTL). +

      +-Set/clear the bits using the bit fields then write the d32 value to the register. +- +-

      +- +-

      +-
      +- ++Set/clear the bits using the bit fields then write the d32 value to the register. ++ ++
      ++

      ++ ++ ++ ++ ++
      ++ + +- ++ + +
      typedef union gintmsk_data gintmsk_data_t typedef union gintmsk_data gintmsk_data_t
      +- +-
      ++
      ++ ++ ++ ++
      ++   ++ + +

      + This union represents the bit fields of the Core Interrupt Mask Register (GINTMSK). +

      +-Set/clear the bits using the bit fields then write the d32 value to the register. +- +-

      +- +-

      +-
      +- ++Set/clear the bits using the bit fields then write the d32 value to the register. ++ ++
      ++

      ++ ++ ++ ++ ++
      ++ + +- ++ + +
      typedef union gintsts_data gintsts_data_t typedef union gintsts_data gintsts_data_t
      +- +-
      ++
      ++ ++ ++ ++
      ++   ++ + +

      + This union represents the bit fields of the Core Interrupt Register (GINTSTS). +

      +-Set/clear the bits using the bit fields then write the d32 value to the register. +- +-

      +- +-

      +-
      +- ++Set/clear the bits using the bit fields then write the d32 value to the register. ++ ++
      ++

      ++ ++ ++ ++ ++
      ++ + +- ++ + +
      typedef union fifosize_data fifosize_data_t typedef union fifosize_data fifosize_data_t
      +- +-
      ++
      ++ ++ ++ ++
      ++   ++ + +

      + This union represents the bit fields in the FIFO Size Registers (HPTXFSIZ, GNPTXFSIZ, DPTXFSIZn, DIEPTXFn). +

      +-Read the register into the d32 element then read out the bits using the bit elements. +- +-

      +- +-

      +-
      +- ++Read the register into the d32 element then read out the bits using the bit elements. ++ ++
      ++

      ++ ++ ++ ++ ++
      ++ + +- ++ + +
      typedef union gnptxsts_data gnptxsts_data_t typedef union gnptxsts_data gnptxsts_data_t
      +- +-
      ++
      ++ ++ ++ ++
      ++   ++ + +

      + This union represents the bit fields in the Non-Periodic Transmit FIFO/Queue Status Register (GNPTXSTS). +

      +-Read the register into the d32 element then read out the bits using the bit elements. +- +-

      +- +-

      +-
      +- ++Read the register into the d32 element then read out the bits using the bit elements. ++ ++
      ++

      ++ ++ ++ ++ ++
      ++ + +- ++ + +
      typedef union dtxfsts_data dtxfsts_data_t typedef union dtxfsts_data dtxfsts_data_t
      +- +-
      ++
      ++ ++ ++ ++
      ++   ++ + +

      + This union represents the bit fields in the Transmit FIFO Status Register (DTXFSTS). +

      +-Read the register into the d32 element then read out the bits using the bit elements. +- +-

      +- +-

      +-
      +- ++Read the register into the d32 element then read out the bits using the bit elements. ++ ++
      ++

      ++ ++ ++ ++ ++
      ++ + +- ++ + +
      typedef union gi2cctl_data gi2cctl_data_t typedef union gi2cctl_data gi2cctl_data_t
      +- +-
      ++
      ++ ++ ++ ++
      ++   ++ + +

      + This union represents the bit fields in the I2C Control Register (I2CCTL). +

      +-Read the register into the d32 element then read out the bits using the bit elements. +- +-

      +- +-

      +-
      +- ++Read the register into the d32 element then read out the bits using the bit elements. ++ ++
      ++

      ++ ++ ++ ++ ++
      ++ ++ ++ ++ ++
      typedef union gpvndctl_data gpvndctl_data_t
      ++
      ++ ++ ++ ++ ++ ++
      ++   ++ ++ ++

      ++This union represents the bit fields in the PHY Vendor Control Register (GPVNDCTL). ++

      ++Read the register into the d32 element then read out the bits using the bit elements.

      ++

      ++ ++ ++ ++ ++
      ++ ++ ++ ++ ++
      typedef union ggpio_data ggpio_data_t
      ++
      ++ ++ ++ ++ ++ ++
      ++   ++ ++ ++

      ++This union represents the bit fields in the General Purpose Input/Output Register (GGPIO). ++

      ++Read the register into the d32 element then read out the bits using the bit elements.

      ++

      ++ ++ ++ ++ ++
      ++ + +- ++ + +
      typedef union hwcfg1_data hwcfg1_data_t typedef union guid_data guid_data_t
      +- +-
      ++
      ++ ++ ++ ++ ++ ++
      ++   ++ ++ ++

      ++This union represents the bit fields in the User ID Register (GUID). ++

      ++Read the register into the d32 element then read out the bits using the bit elements.

      ++

      ++ ++ ++ ++ ++
      ++ ++ ++ ++ ++
      typedef union gsnpsid_data gsnpsid_data_t
      ++
      ++ ++ ++ ++ ++ ++
      ++   ++ ++ ++

      ++This union represents the bit fields in the Synopsys ID Register (GSNPSID). ++

      ++Read the register into the d32 element then read out the bits using the bit elements.

      ++

      ++ ++ ++ ++ ++
      ++ ++ ++ ++ ++
      typedef union hwcfg1_data hwcfg1_data_t
      ++
      ++ ++ ++ ++
      ++   ++ + +

      + This union represents the bit fields in the User HW Config1 Register. +

      +-Read the register into the d32 element then read out the bits using the bit elements. +- +-

      +- +-

      +-
      +- ++Read the register into the d32 element then read out the bits using the bit elements. ++ ++
      ++

      ++ ++ ++ ++ ++
      ++ + +- ++ + +
      typedef union hwcfg2_data hwcfg2_data_t typedef union hwcfg2_data hwcfg2_data_t
      +- +-
      ++
      ++ ++ ++ ++
      ++   ++ + +

      + This union represents the bit fields in the User HW Config2 Register. +

      +-Read the register into the d32 element then read out the bits using the bit elements. +- +-

      +- +-

      +-
      +- ++Read the register into the d32 element then read out the bits using the bit elements. ++ ++
      ++

      ++ ++ ++ ++ ++
      ++ + +- ++ + +
      typedef union hwcfg3_data hwcfg3_data_t typedef union hwcfg3_data hwcfg3_data_t
      +- +-
      ++
      ++ ++ ++ ++
      ++   ++ + +

      + This union represents the bit fields in the User HW Config3 Register. +

      +-Read the register into the d32 element then read out the bits using the bit elements. +- +-

      +- +-

      +-
      +- ++Read the register into the d32 element then read out the bits using the bit elements. ++ ++
      ++

      ++ ++ ++ ++ ++
      ++ + +- ++ + +
      typedef union hwcfg4_data hwcfg4_data_t typedef union hwcfg4_data hwcfg4_data_t
      +- +-
      ++
      ++ ++ ++ ++
      ++   ++ + +

      + This union represents the bit fields in the User HW Config4 Register. +

      +-Read the register into the d32 element then read out the bits using the bit elements. +- +-

      +- +-

      +-
      +- ++Read the register into the d32 element then read out the bits using the bit elements. ++ ++
      ++

      ++ ++ ++ ++ ++
      ++ + +- ++ + +
      typedef struct dwc_otg_dev_global_regs dwc_otg_device_global_regs_t typedef union glpmctl_data glpmcfg_data_t
      +- +-
      ++
      ++ ++ ++ ++ ++ ++
      ++   ++ ++ ++

      ++This union represents the bit fields of the Core LPM Configuration Register (GLPMCFG). ++

      ++Set the bits using bit fields then write the d32 value to the register.

      ++

      ++ ++ ++ ++ ++
      ++ ++ ++ ++ ++
      typedef union adpctl_data adpctl_data_t
      ++
      ++ ++ ++ ++ ++ ++
      ++   ++ ++ ++

      ++This union represents the bit fields of the Core ADP Timer, Control and Status Register (ADPTIMCTLSTS). ++

      ++Set the bits using bit fields then write the d32 value to the register.

      ++

      ++ ++ ++ ++ ++
      ++ ++ ++ ++ ++
      typedef struct dwc_otg_dev_global_regs dwc_otg_device_global_regs_t
      ++
      ++ ++ ++ ++
      ++   ++ + +

      + Device Global Registers. +

      + Offsets 800h-BFFh

      + The following structures define the size and relative field offsets for the Device Mode Registers.

      +-These registers are visible only in Device mode and must not be accessed in Host mode, as the results are unknown. +- +-

      +- +-

      +-
      +- ++These registers are visible only in Device mode and must not be accessed in Host mode, as the results are unknown. ++ ++
      ++

      ++ ++ ++ ++ ++
      ++ + +- ++ + +
      typedef union dcfg_data dcfg_data_t typedef union dcfg_data dcfg_data_t
      +- +-
      ++
      ++ ++ ++ ++
      ++   ++ + +

      + This union represents the bit fields in the Device Configuration Register. +

      +-Read the register into the d32 member then set/clear the bits using the bit elements. Write the d32 member to the dcfg register. +- +-

      +- +-

      +-
      +- ++Read the register into the d32 member then set/clear the bits using the bit elements. Write the d32 member to the dcfg register. ++ ++
      ++

      ++ ++ ++ ++ ++
      ++ + +- ++ + +
      typedef union dctl_data dctl_data_t typedef union dctl_data dctl_data_t
      +- +-
      ++
      ++ ++ ++ ++
      ++   ++ + +

      + This union represents the bit fields in the Device Control Register. +

      +-Read the register into the d32 member then set/clear the bits using the bit elements. +- +-

      +- +-

      +-
      +- ++Read the register into the d32 member then set/clear the bits using the bit elements. ++ ++
      ++

      ++ ++ ++ ++ ++
      ++ + +- ++ + +
      typedef union dsts_data dsts_data_t typedef union dsts_data dsts_data_t
      +- +-
      ++
      ++ ++ ++ ++
      ++   ++ + +

      + This union represents the bit fields in the Device Status Register. +

      +-Read the register into the d32 member then set/clear the bits using the bit elements. +- +-

      +- +-

      +-
      +- ++Read the register into the d32 member then set/clear the bits using the bit elements. ++ ++
      ++

      ++ ++ ++ ++ ++
      ++ + +- ++ + +
      typedef union diepint_data diepint_data_t typedef union diepint_data diepint_data_t
      +- +-
      ++
      ++ ++ ++ ++
      ++   ++ + +

      + This union represents the bit fields in the Device IN EP Interrupt Register and the Device IN EP Common Mask Register. +

      +

        +
      • Read the register into the d32 member then set/clear the bits using the bit elements.
      +- +- +-

      +- +-

      +-
      +- ++ ++ ++
      ++

      ++ ++ ++ ++ ++
      ++ + +- ++ + +
      typedef union doepint_data doepint_data_t typedef union doepint_data doepint_data_t
      +- +-
      ++
      ++ ++ ++ ++
      ++   ++ + +

      + This union represents the bit fields in the Device OUT EP Interrupt Registerand Device OUT EP Common Interrupt Mask Register. +

      +

        +
      • Read the register into the d32 member then set/clear the bits using the bit elements.
      +- +- +-

      +- +-

      +-
      +- ++ ++ ++
      ++

      ++ ++ ++ ++ ++
      ++ + +- ++ + +
      typedef union daint_data daint_data_t typedef union daint_data daint_data_t
      +- +-
      ++
      ++ ++ ++ ++
      ++   ++ + +

      + This union represents the bit fields in the Device All EP Interrupt and Mask Registers. +

      +

        +
      • Read the register into the d32 member then set/clear the bits using the bit elements.
      +- +- +-

      +- +-

      +-
      +- ++ ++ ++
      ++

      ++ ++ ++ ++ ++
      ++ + +- ++ + +
      typedef union dtknq1_data dtknq1_data_t typedef union dtknq1_data dtknq1_data_t
      +- +-
      ++
      ++ ++ ++ ++
      ++   ++ + +

      + This union represents the bit fields in the Device IN Token Queue Read Registers. +

      +

        +
      • Read the register into the d32 member.
      • READ-ONLY Register
      +- +- +-

      +- +-

      +-
      +- ++ ++ ++
      ++

      ++ ++ ++ ++ ++
      ++ + +- ++ + +
      typedef union dthrctl_data dthrctl_data_t typedef union dthrctl_data dthrctl_data_t
      +- +-
      ++
      ++ ++ ++ ++
      ++   ++ + +

      +-This union represents Threshold control Register

        +-
      • Read and write the register into the d32 member.
      +- ++This union represents Threshold control Register Read and write the register into the d32 member. +

      +

        +-
      • READ-WRITABLE Register
      +- +- +-

      +- +-

      +-
      +- ++
    • * - READ-WRITABLE Register
      • ++ ++ ++
      ++

      ++ ++ ++ ++ ++
      ++ + +- ++ + +
      typedef struct dwc_otg_dev_in_ep_regs dwc_otg_dev_in_ep_regs_t typedef struct dwc_otg_dev_in_ep_regs dwc_otg_dev_in_ep_regs_t
      +- +-
      ++
      ++ ++ ++ ++
      ++   ++ + +

      + Device Logical IN Endpoint-Specific Registers. +

      + Offsets 900h-AFCh

      + There will be one set of endpoint registers per logical endpoint implemented.

      +-These registers are visible only in Device mode and must not be accessed in Host mode, as the results are unknown. +- +-

      +- +-

      +-
      +- ++These registers are visible only in Device mode and must not be accessed in Host mode, as the results are unknown. ++ ++
      ++

      ++ ++ ++ ++ ++
      ++ + +- ++ + +
      typedef struct dwc_otg_dev_out_ep_regs dwc_otg_dev_out_ep_regs_t typedef struct dwc_otg_dev_out_ep_regs dwc_otg_dev_out_ep_regs_t
      +- +-
      ++
      ++ ++ ++ ++
      ++   ++ + +

      + Device Logical OUT Endpoint-Specific Registers. +

      + Offsets: B00h-CFCh

      + There will be one set of endpoint registers per logical endpoint implemented.

      +-These registers are visible only in Device mode and must not be accessed in Host mode, as the results are unknown. +- +-

      +- +-

      +-
      +- ++These registers are visible only in Device mode and must not be accessed in Host mode, as the results are unknown. ++ ++
      ++

      ++ ++ ++ ++ ++
      ++ + +- ++ + +
      typedef union depctl_data depctl_data_t typedef union depctl_data depctl_data_t
      +- +-
      ++
      ++ ++ ++ ++
      ++   ++ + +

      + This union represents the bit fields in the Device EP Control Register. +

      +-Read the register into the d32 member then set/clear the bits using the bit elements. +- +-

      +- +-

      +-
      +- ++Read the register into the d32 member then set/clear the bits using the bit elements. ++ ++
      ++

      ++ ++ ++ ++ ++
      ++ + +- ++ + +
      typedef union deptsiz_data deptsiz_data_t typedef union deptsiz_data deptsiz_data_t
      +- +-
      ++
      ++ ++ ++ ++
      ++   ++ + +

      + This union represents the bit fields in the Device EP Transfer Size Register. +

      +-Read the register into the d32 member then set/clear the bits using the bit elements. +- +-

      +- +-

      +-
      +- ++Read the register into the d32 member then set/clear the bits using the bit elements. ++ ++
      ++

      ++ ++ ++ ++ ++
      ++ + +- ++ + +
      typedef union deptsiz0_data deptsiz0_data_t typedef union deptsiz0_data deptsiz0_data_t
      +- +-
      ++
      ++ ++ ++ ++
      ++   ++ + +

      + This union represents the bit fields in the Device EP 0 Transfer Size Register. +

      +-Read the register into the d32 member then set/clear the bits using the bit elements. +- +-

      +- +-

      +-
      +- ++Read the register into the d32 member then set/clear the bits using the bit elements. ++ ++
      ++

      ++ ++ ++ ++ ++
      ++ + +- ++ + +
      typedef union dev_dma_desc_sts dev_dma_desc_sts_t typedef union dev_dma_desc_sts dev_dma_desc_sts_t
      +- +-
      ++
      ++ ++ ++ ++
      ++   ++ + +

      + This union represents the bit fields in the DMA Descriptor status quadlet. +

      +-Read the quadlet into the d32 member then set/clear the bits using the bit, b_iso_out and b_iso_in elements. +- +-

      +- +-

      +-
      +- ++Read the quadlet into the d32 member then set/clear the bits using the bit, b_iso_out and b_iso_in elements. ++ ++
      ++

      ++ ++ ++ ++ ++
      ++ + +- ++ + +
      typedef struct dwc_otg_dev_dma_desc dwc_otg_dev_dma_desc_t typedef struct dwc_otg_dev_dma_desc dwc_otg_dev_dma_desc_t
      +- +-
      ++
      ++ ++ ++ ++
      ++   ++ + +

      + DMA Descriptor structure. +

      +-DMA Descriptor structure contains two quadlets: Status quadlet and Data buffer pointer. +- +-

      +- +-

      +-
      +- ++DMA Descriptor structure contains two quadlets: Status quadlet and Data buffer pointer. ++ ++
      ++

      ++ ++ ++ ++ ++
      ++ + +- ++ + +
      typedef struct dwc_otg_dev_if dwc_otg_dev_if_t typedef struct dwc_otg_dev_if dwc_otg_dev_if_t
      +- +-
      ++
      ++ ++ ++ ++
      ++   ++ + +

      + The dwc_otg_dev_if structure contains information needed to manage the DWC_otg controller acting in device mode. +

      +-It represents the programming view of the device-specific aspects of the controller. +- +-

      +- +-

      +-
      +- ++It represents the programming view of the device-specific aspects of the controller. ++ ++
      ++

      ++ ++ ++ ++ ++
      ++ + +- ++ + +
      typedef struct dwc_otg_host_global_regs dwc_otg_host_global_regs_t typedef struct dwc_otg_host_global_regs dwc_otg_host_global_regs_t
      +- +-
      ++
      ++ ++ ++ ++
      ++   ++ + +

      + The Host Global Registers structure defines the size and relative field offsets for the Host Mode Global Registers. +

      +-Host Global Registers offsets 400h-7FFh. +- +-

      +- +-

      +-
      +- ++Host Global Registers offsets 400h-7FFh. ++ ++
      ++

      ++ ++ ++ ++ ++
      ++ + +- ++ + +
      typedef union hcfg_data hcfg_data_t typedef union hcfg_data hcfg_data_t
      +- +-
      ++
      ++ ++ ++ ++
      ++   ++ + +

      + This union represents the bit fields in the Host Configuration Register. +

      +-Read the register into the d32 member then set/clear the bits using the bit elements. Write the d32 member to the hcfg register. +- +-

      +- +-

      +-
      +- ++Read the register into the d32 member then set/clear the bits using the bit elements. Write the d32 member to the hcfg register. ++ ++
      ++

      ++ ++ ++ ++ ++
      ++ + +- ++ + +
      typedef union hprt0_data hprt0_data_t typedef union hprt0_data hprt0_data_t
      +- +-
      ++
      ++ ++ ++ ++
      ++   ++ + +

      + This union represents the bit fields in the Host Port Control and Status Register. +

      +-Read the register into the d32 member then set/clear the bits using the bit elements. Write the d32 member to the hprt0 register. +- +-

      +- +-

      +-
      +- ++Read the register into the d32 member then set/clear the bits using the bit elements. Write the d32 member to the hprt0 register. ++ ++
      ++

      ++ ++ ++ ++ ++
      ++ + +- ++ + +
      typedef struct dwc_otg_hc_regs dwc_otg_hc_regs_t typedef struct dwc_otg_hc_regs dwc_otg_hc_regs_t
      +- +-
      ++
      ++ ++ ++ ++
      ++   ++ + +

      + Host Channel Specific Registers. +

      +-500h-5FCh +- +-

      +- +-

      +-
      +- ++500h-5FCh ++ ++
      ++

      ++ ++ ++ ++ ++
      ++ + +- ++ + +
      typedef union hcchar_data hcchar_data_t typedef union hcchar_data hcchar_data_t
      +- +-
      ++
      ++ ++ ++ ++
      ++   ++ + +

      + This union represents the bit fields in the Host Channel Characteristics Register. +

      +-Read the register into the d32 member then set/clear the bits using the bit elements. Write the d32 member to the hcchar register. +- +-

      +- +-

      +-
      +- ++Read the register into the d32 member then set/clear the bits using the bit elements. Write the d32 member to the hcchar register. ++ ++
      ++

      ++ ++ ++ ++ ++
      ++ + +- ++ + +
      typedef union hcintmsk_data hcintmsk_data_t typedef union hcintmsk_data hcintmsk_data_t
      +- +-
      ++
      ++ ++ ++ ++
      ++   ++ + +

      + This union represents the bit fields in the Host Channel Interrupt Mask Register. +

      +-Read the register into the d32 member then set/clear the bits using the bit elements. Write the d32 member to the hcintmsk register. +- +-

      +- +-

      +-
      +- ++Read the register into the d32 member then set/clear the bits using the bit elements. Write the d32 member to the hcintmsk register. ++ ++
      ++

      ++ ++ ++ ++ ++
      ++ + +- ++ + +
      typedef union hctsiz_data hctsiz_data_t typedef union hctsiz_data hctsiz_data_t
      +- +-
      ++
      ++ ++ ++ ++
      ++   ++ + +

      + This union represents the bit fields in the Host Channel Transfer Size Register. +

      +-Read the register into the d32 member then set/clear the bits using the bit elements. Write the d32 member to the hcchar register. +- +-

      +- +-

      +-
      +- ++Read the register into the d32 member then set/clear the bits using the bit elements. Write the d32 member to the hcchar register. ++ ++
      ++

      ++ ++ ++ ++ ++
      ++ + +- ++ + +
      typedef union host_dma_desc_sts host_dma_desc_sts_t typedef union host_dma_desc_sts host_dma_desc_sts_t
      +- +-
      ++
      ++ ++ ++ ++
      ++   ++ + +

      + This union represents the bit fields in the DMA Descriptor status quadlet for host mode. +

      +-Read the quadlet into the d32 member then set/clear the bits using the bit elements. +- +-

      +- +-

      +-
      +- ++Read the quadlet into the d32 member then set/clear the bits using the bit elements. ++ ++
      ++

      ++ ++ ++ ++ ++
      ++ + +- ++ + +
      typedef struct dwc_otg_host_dma_desc dwc_otg_host_dma_desc_t typedef struct dwc_otg_host_dma_desc dwc_otg_host_dma_desc_t
      +- +-
      ++
      ++ ++ ++ ++
      ++   ++ + +

      + Host-mode DMA Descriptor structure. +

      +-DMA Descriptor structure contains two quadlets: Status quadlet and Data buffer pointer. +- +-

      +- +-

      +-
      +- ++DMA Descriptor structure contains two quadlets: Status quadlet and Data buffer pointer. ++ ++
      ++

      ++ ++ ++ ++ ++
      ++ + +- ++ + +
      typedef struct dwc_otg_host_if dwc_otg_host_if_t typedef struct dwc_otg_host_if dwc_otg_host_if_t
      +- +-
      ++
      ++ ++ ++ ++
      ++   ++ + +

      + OTG Host Interface Structure. +

      +-The OTG Host Interface Structure structure contains information needed to manage the DWC_otg controller acting in host mode. It represents the programming view of the host-specific aspects of the controller. +- +-

      +- +-

      +-
      +- ++The OTG Host Interface Structure structure contains information needed to manage the DWC_otg controller acting in host mode. It represents the programming view of the host-specific aspects of the controller. ++ ++
      ++

      ++ ++ ++ ++ ++
      ++ + +- ++ + +
      typedef union pcgcctl_data pcgcctl_data_t typedef union pcgcctl_data pcgcctl_data_t
      +- +-
      ++
      ++ ++ ++ ++ ++ ++
      ++   ++ + +

      + This union represents the bit fields in the Power and Clock Gating Control Register. +

      +-Read the register into the d32 member then set/clear the bits using the bit elements. +- +-

      +-

      Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++Read the register into the d32 member then set/clear the bits using the bit elements.
      ++

      ++ ++ ++ ++ ++
      ++ ++ ++ ++ ++
      typedef union gdfifocfg_data gdfifocfg_data_t
      ++
      ++ ++ ++ ++ ++ ++
      ++   ++ ++ ++

      ++This union represents the bit fields in the Global Data FIFO Software Configuration Register. ++

      ++Read the register into the d32 member then set/clear the bits using the bit elements.

      ++

      ++ ++ ++ ++ ++
      ++ ++ ++ ++ ++
      typedef union gpwrdn_data gpwrdn_data_t
      ++
      ++ ++ ++ ++ ++ ++
      ++   ++ ++ ++

      ++This union represents the bit fields in the Global Power Down Register Register. ++

      ++Read the register into the d32 member then set/clear the bits using the bit elements.

      ++

      Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
      ++doxygen 1.3.9.1 + + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/files.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/files.html 2013-07-26 19:31:22.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/files.html 2013-07-26 19:34:42.000000000 +0000 +@@ -2,28 +2,17 @@ + + DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: File Index + +- + +- +-
      +-
      +-
      +-
      ++ ++
      Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
      +

      DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver File List

      Here is a list of all documented files with brief descriptions: +- + ++ ++ + + +- +- ++ ++ + + + +@@ -38,6 +27,7 @@ + + + ++ + + + +@@ -45,8 +35,8 @@ + + +
      dummy_audio.c [code]
      dwc_cfi_common.h [code]This file contains the CFI specific common constants, interfaces (functions and macros) and structures for Linux
      dwc_otg_adp.c [code]This file contains the most of the Attach Detect Protocol implementation for the driver to support OTG Rev2.0
      dwc_otg_adp.h [code]This file contains the Attach Detect Protocol interfaces and defines (functions) and structures for Linux
      dwc_otg_attr.c [code]The diagnostic interface will provide access to the controller for bringing up the hardware and testing
      dwc_otg_attr.h [code]This file contains the interface to the Linux device attributes
      dwc_otg_cfi.c [code]This file contains the most of the CFI implementation for the OTG
      dwc_otg_cfi.h [code]This file contains the CFI related OTG PCD specific common constants, interfaces (functions and macros) and data structures
      dwc_otg_cfi.c [code]This file contains the most of the CFI(Core Feature Interface) implementation for the OTG
      dwc_otg_cfi.h [code]This file contains the CFI related OTG PCD specific common constants, interfaces(functions and macros) and data structures.The CFI Protocol is an optional interface for internal testing purposes that a DUT may implement to support testing of configurable features
      dwc_otg_cil.c [code]The Core Interface Layer provides basic services for accessing and managing the DWC_otg hardware
      dwc_otg_cil.h [code]This file contains the interface to the Core Interface Layer
      dwc_otg_cil_intr.c [code]The Core Interface Layer provides basic services for accessing and managing the DWC_otg hardware
      dwc_otg_hcd_intr.c [code]This file contains the implementation of the HCD Interrupt handlers
      dwc_otg_hcd_linux.c [code]This file contains the implementation of the HCD
      dwc_otg_hcd_queue.c [code]This file contains the functions to manage Queue Heads and Queue Transfer Descriptors
      dwc_otg_os_dep.h [code]This file contains OS dependent structures
      dwc_otg_pcd.c [code]This file implements PCD Core
      dwc_otg_pcd.h [code]This file contains the structures, constants, and interfaces for the Perpherial Contoller Driver (PCD)
      dwc_otg_pcd_if.h [code]This file defines DWC_OTG PCD Core API
      dwc_otg_pcd_linux.c [code]This file implements the Peripheral Controller Driver
      dwc_otg_regs.h [code]This file contains the data structures for accessing the DWC_otg core registers
      +-
      Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++
      Generated on Thu Oct 27 03:56:37 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
      ++doxygen 1.3.9.1
      + + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/functions.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/functions.html 2013-07-26 19:31:22.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/functions.html 2013-07-26 19:34:42.000000000 +0000 +@@ -2,81 +2,594 @@ + + DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields + +- + +- +-
      +-
      +-
      +-
      +-
      +- +-
      +-
      +-
        +-
      • a
        • +-
      • b
        • +-
      • c
        • +-
      • d
        • +-
      • e
        • +-
      • f
        • +-
      • g
        • +-
      • h
        • +-
      • i
        • +-
      • l
        • +-
      • m
        • +-
      • n
        • +-
      • o
        • +-
      • p
        • +-
      • q
        • +-
      • r
        • +-
      • s
        • +-
      • t
        • +-
      • u
        • +-
      • v
        • +-
      • w
        • +-
      • x
        • +-
      +-
      ++ ++
      Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
      ++
      All | Functions | Variables
      ++
      a | b | c | d | e | f | g | h | i | l | m | n | o | p | q | r | s | t | u | w | x
      + +

      +-Here is a list of all documented struct and union fields with links to the struct/union documentation for each field: ++ +

      +-

      - a -

      ++

      - b -

      ++

      - c -

      ++

      - d -

      ++

      - e -

      ++

      - f -

      ++

      - g -

      ++

      - h -

      ++

      - i -

      ++

      - l -

      ++

      - m -

      ++

      - n -

      ++

      - o -

      ++

      - p -

      ++

      - q -

      ++

      - r -

      ++

      - s -

      ++

      - t -

      ++

      - u -

      ++

      - w -

      ++

      - x -

      ++
      Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
      ++doxygen 1.3.9.1       + + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/functions_0x62.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/functions_0x62.html 2013-07-26 19:31:22.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,99 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields +- +- +- +- +-
      +-
      +-
      +-
      +-
      +- +-
      +-
      +-
        +-
      • a
        • +-
      • b
        • +-
      • c
        • +-
      • d
        • +-
      • e
        • +-
      • f
        • +-
      • g
        • +-
      • h
        • +-
      • i
        • +-
      • l
        • +-
      • m
        • +-
      • n
        • +-
      • o
        • +-
      • p
        • +-
      • q
        • +-
      • r
        • +-
      • s
        • +-
      • t
        • +-
      • u
        • +-
      • v
        • +-
      • w
        • +-
      • x
        • +-
      +-
      +- +-

      +-Here is a list of all documented struct and union fields with links to the struct/union documentation for each field: +-

      +-

      - b -

      +-
      Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.4.7
      +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/functions_0x63.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/functions_0x63.html 2013-07-26 19:31:22.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,110 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields +- +- +- +- +-
      +-
      +-
      +-
      +-
      +- +-
      +-
      +-
        +-
      • a
        • +-
      • b
        • +-
      • c
        • +-
      • d
        • +-
      • e
        • +-
      • f
        • +-
      • g
        • +-
      • h
        • +-
      • i
        • +-
      • l
        • +-
      • m
        • +-
      • n
        • +-
      • o
        • +-
      • p
        • +-
      • q
        • +-
      • r
        • +-
      • s
        • +-
      • t
        • +-
      • u
        • +-
      • v
        • +-
      • w
        • +-
      • x
        • +-
      +-
      +- +-

      +-Here is a list of all documented struct and union fields with links to the struct/union documentation for each field: +-

      +-

      - c -

      +-
      Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.4.7
      +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/functions_0x64.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/functions_0x64.html 2013-07-26 19:31:22.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,158 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields +- +- +- +- +-
      +-
      +-
      +-
      +-
      +- +-
      +-
      +-
        +-
      • a
        • +-
      • b
        • +-
      • c
        • +-
      • d
        • +-
      • e
        • +-
      • f
        • +-
      • g
        • +-
      • h
        • +-
      • i
        • +-
      • l
        • +-
      • m
        • +-
      • n
        • +-
      • o
        • +-
      • p
        • +-
      • q
        • +-
      • r
        • +-
      • s
        • +-
      • t
        • +-
      • u
        • +-
      • v
        • +-
      • w
        • +-
      • x
        • +-
      +-
      +- +-

      +-Here is a list of all documented struct and union fields with links to the struct/union documentation for each field: +-

      +-

      - d -

      +-
      Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.4.7
      +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/functions_0x65.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/functions_0x65.html 2013-07-26 19:31:22.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,109 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields +- +- +- +- +-
      +-
      +-
      +-
      +-
      +- +-
      +-
      +-
        +-
      • a
        • +-
      • b
        • +-
      • c
        • +-
      • d
        • +-
      • e
        • +-
      • f
        • +-
      • g
        • +-
      • h
        • +-
      • i
        • +-
      • l
        • +-
      • m
        • +-
      • n
        • +-
      • o
        • +-
      • p
        • +-
      • q
        • +-
      • r
        • +-
      • s
        • +-
      • t
        • +-
      • u
        • +-
      • v
        • +-
      • w
        • +-
      • x
        • +-
      +-
      +- +-

      +-Here is a list of all documented struct and union fields with links to the struct/union documentation for each field: +-

      +-

      - e -

      +-
      Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.4.7
      +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/functions_0x66.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/functions_0x66.html 2013-07-26 19:31:22.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,81 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields +- +- +- +- +-
      +-
      +-
      +-
      +-
      +- +-
      +-
      +-
        +-
      • a
        • +-
      • b
        • +-
      • c
        • +-
      • d
        • +-
      • e
        • +-
      • f
        • +-
      • g
        • +-
      • h
        • +-
      • i
        • +-
      • l
        • +-
      • m
        • +-
      • n
        • +-
      • o
        • +-
      • p
        • +-
      • q
        • +-
      • r
        • +-
      • s
        • +-
      • t
        • +-
      • u
        • +-
      • v
        • +-
      • w
        • +-
      • x
        • +-
      +-
      +- +-

      +-Here is a list of all documented struct and union fields with links to the struct/union documentation for each field: +-

      +-

      - f -

      +-
      Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.4.7
      +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/functions_0x67.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/functions_0x67.html 2013-07-26 19:31:22.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,95 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields +- +- +- +- +-
      +-
      +-
      +-
      +-
      +- +-
      +-
      +-
        +-
      • a
        • +-
      • b
        • +-
      • c
        • +-
      • d
        • +-
      • e
        • +-
      • f
        • +-
      • g
        • +-
      • h
        • +-
      • i
        • +-
      • l
        • +-
      • m
        • +-
      • n
        • +-
      • o
        • +-
      • p
        • +-
      • q
        • +-
      • r
        • +-
      • s
        • +-
      • t
        • +-
      • u
        • +-
      • v
        • +-
      • w
        • +-
      • x
        • +-
      +-
      +- +-

      +-Here is a list of all documented struct and union fields with links to the struct/union documentation for each field: +-

      +-

      - g -

      +-
      Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.4.7
      +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/functions_0x68.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/functions_0x68.html 2013-07-26 19:31:22.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,119 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields +- +- +- +- +-
      +-
      +-
      +-
      +-
      +- +-
      +-
      +-
        +-
      • a
        • +-
      • b
        • +-
      • c
        • +-
      • d
        • +-
      • e
        • +-
      • f
        • +-
      • g
        • +-
      • h
        • +-
      • i
        • +-
      • l
        • +-
      • m
        • +-
      • n
        • +-
      • o
        • +-
      • p
        • +-
      • q
        • +-
      • r
        • +-
      • s
        • +-
      • t
        • +-
      • u
        • +-
      • v
        • +-
      • w
        • +-
      • x
        • +-
      +-
      +- +-

      +-Here is a list of all documented struct and union fields with links to the struct/union documentation for each field: +-

      +-

      - h -

      +-
      Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.4.7
      +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/functions_0x69.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/functions_0x69.html 2013-07-26 19:31:22.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,121 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields +- +- +- +- +-
      +-
      +-
      +-
      +-
      +- +-
      +-
      +-
        +-
      • a
        • +-
      • b
        • +-
      • c
        • +-
      • d
        • +-
      • e
        • +-
      • f
        • +-
      • g
        • +-
      • h
        • +-
      • i
        • +-
      • l
        • +-
      • m
        • +-
      • n
        • +-
      • o
        • +-
      • p
        • +-
      • q
        • +-
      • r
        • +-
      • s
        • +-
      • t
        • +-
      • u
        • +-
      • v
        • +-
      • w
        • +-
      • x
        • +-
      +-
      +- +-

      +-Here is a list of all documented struct and union fields with links to the struct/union documentation for each field: +-

      +-

      - i -

      +-
      Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.4.7
      +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/functions_0x6c.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/functions_0x6c.html 2013-07-26 19:31:22.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,74 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields +- +- +- +- +-
      +-
      +-
      +-
      +-
      +- +-
      +-
      +-
        +-
      • a
        • +-
      • b
        • +-
      • c
        • +-
      • d
        • +-
      • e
        • +-
      • f
        • +-
      • g
        • +-
      • h
        • +-
      • i
        • +-
      • l
        • +-
      • m
        • +-
      • n
        • +-
      • o
        • +-
      • p
        • +-
      • q
        • +-
      • r
        • +-
      • s
        • +-
      • t
        • +-
      • u
        • +-
      • v
        • +-
      • w
        • +-
      • x
        • +-
      +-
      +- +-

      +-Here is a list of all documented struct and union fields with links to the struct/union documentation for each field: +-

      +-

      - l -

      +-
      Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.4.7
      +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/functions_0x6d.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/functions_0x6d.html 2013-07-26 19:31:22.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,79 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields +- +- +- +- +-
      +-
      +-
      +-
      +-
      +- +-
      +-
      +-
        +-
      • a
        • +-
      • b
        • +-
      • c
        • +-
      • d
        • +-
      • e
        • +-
      • f
        • +-
      • g
        • +-
      • h
        • +-
      • i
        • +-
      • l
        • +-
      • m
        • +-
      • n
        • +-
      • o
        • +-
      • p
        • +-
      • q
        • +-
      • r
        • +-
      • s
        • +-
      • t
        • +-
      • u
        • +-
      • v
        • +-
      • w
        • +-
      • x
        • +-
      +-
      +- +-

      +-Here is a list of all documented struct and union fields with links to the struct/union documentation for each field: +-

      +-

      - m -

      +-
      Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.4.7
      +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/functions_0x6e.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/functions_0x6e.html 2013-07-26 19:31:22.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,99 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields +- +- +- +- +-
      +-
      +-
      +-
      +-
      +- +-
      +-
      +-
        +-
      • a
        • +-
      • b
        • +-
      • c
        • +-
      • d
        • +-
      • e
        • +-
      • f
        • +-
      • g
        • +-
      • h
        • +-
      • i
        • +-
      • l
        • +-
      • m
        • +-
      • n
        • +-
      • o
        • +-
      • p
        • +-
      • q
        • +-
      • r
        • +-
      • s
        • +-
      • t
        • +-
      • u
        • +-
      • v
        • +-
      • w
        • +-
      • x
        • +-
      +-
      +- +-

      +-Here is a list of all documented struct and union fields with links to the struct/union documentation for each field: +-

      +-

      - n -

      +-
      Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.4.7
      +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/functions_0x6f.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/functions_0x6f.html 2013-07-26 19:31:22.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,101 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields +- +- +- +- +-
      +-
      +-
      +-
      +-
      +- +-
      +-
      +-
        +-
      • a
        • +-
      • b
        • +-
      • c
        • +-
      • d
        • +-
      • e
        • +-
      • f
        • +-
      • g
        • +-
      • h
        • +-
      • i
        • +-
      • l
        • +-
      • m
        • +-
      • n
        • +-
      • o
        • +-
      • p
        • +-
      • q
        • +-
      • r
        • +-
      • s
        • +-
      • t
        • +-
      • u
        • +-
      • v
        • +-
      • w
        • +-
      • x
        • +-
      +-
      +- +-

      +-Here is a list of all documented struct and union fields with links to the struct/union documentation for each field: +-

      +-

      - o -

      +-
      Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.4.7
      +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/functions_0x70.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/functions_0x70.html 2013-07-26 19:31:22.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,144 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields +- +- +- +- +-
      +-
      +-
      +-
      +-
      +- +-
      +-
      +-
        +-
      • a
        • +-
      • b
        • +-
      • c
        • +-
      • d
        • +-
      • e
        • +-
      • f
        • +-
      • g
        • +-
      • h
        • +-
      • i
        • +-
      • l
        • +-
      • m
        • +-
      • n
        • +-
      • o
        • +-
      • p
        • +-
      • q
        • +-
      • r
        • +-
      • s
        • +-
      • t
        • +-
      • u
        • +-
      • v
        • +-
      • w
        • +-
      • x
        • +-
      +-
      +- +-

      +-Here is a list of all documented struct and union fields with links to the struct/union documentation for each field: +-

      +-

      - p -

      +-
      Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.4.7
      +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/functions_0x71.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/functions_0x71.html 2013-07-26 19:31:22.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,71 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields +- +- +- +- +-
      +-
      +-
      +-
      +-
      +- +-
      +-
      +-
        +-
      • a
        • +-
      • b
        • +-
      • c
        • +-
      • d
        • +-
      • e
        • +-
      • f
        • +-
      • g
        • +-
      • h
        • +-
      • i
        • +-
      • l
        • +-
      • m
        • +-
      • n
        • +-
      • o
        • +-
      • p
        • +-
      • q
        • +-
      • r
        • +-
      • s
        • +-
      • t
        • +-
      • u
        • +-
      • v
        • +-
      • w
        • +-
      • x
        • +-
      +-
      +- +-

      +-Here is a list of all documented struct and union fields with links to the struct/union documentation for each field: +-

      +-

      - q -

      +-
      Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.4.7
      +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/functions_0x72.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/functions_0x72.html 2013-07-26 19:31:22.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,141 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields +- +- +- +- +-
      +-
      +-
      +-
      +-
      +- +-
      +-
      +-
        +-
      • a
        • +-
      • b
        • +-
      • c
        • +-
      • d
        • +-
      • e
        • +-
      • f
        • +-
      • g
        • +-
      • h
        • +-
      • i
        • +-
      • l
        • +-
      • m
        • +-
      • n
        • +-
      • o
        • +-
      • p
        • +-
      • q
        • +-
      • r
        • +-
      • s
        • +-
      • t
        • +-
      • u
        • +-
      • v
        • +-
      • w
        • +-
      • x
        • +-
      +-
      +- +-

      +-Here is a list of all documented struct and union fields with links to the struct/union documentation for each field: +-

      +-

      - r -

      +-
      Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.4.7
      +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/functions_0x73.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/functions_0x73.html 2013-07-26 19:31:22.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,128 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields +- +- +- +- +-
      +-
      +-
      +-
      +-
      +- +-
      +-
      +-
        +-
      • a
        • +-
      • b
        • +-
      • c
        • +-
      • d
        • +-
      • e
        • +-
      • f
        • +-
      • g
        • +-
      • h
        • +-
      • i
        • +-
      • l
        • +-
      • m
        • +-
      • n
        • +-
      • o
        • +-
      • p
        • +-
      • q
        • +-
      • r
        • +-
      • s
        • +-
      • t
        • +-
      • u
        • +-
      • v
        • +-
      • w
        • +-
      • x
        • +-
      +-
      +- +-

      +-Here is a list of all documented struct and union fields with links to the struct/union documentation for each field: +-

      +-

      - s -

      +-
      Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.4.7
      +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/functions_0x74.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/functions_0x74.html 2013-07-26 19:31:22.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,88 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields +- +- +- +- +-
      +-
      +-
      +-
      +-
      +- +-
      +-
      +-
        +-
      • a
        • +-
      • b
        • +-
      • c
        • +-
      • d
        • +-
      • e
        • +-
      • f
        • +-
      • g
        • +-
      • h
        • +-
      • i
        • +-
      • l
        • +-
      • m
        • +-
      • n
        • +-
      • o
        • +-
      • p
        • +-
      • q
        • +-
      • r
        • +-
      • s
        • +-
      • t
        • +-
      • u
        • +-
      • v
        • +-
      • w
        • +-
      • x
        • +-
      +-
      +- +-

      +-Here is a list of all documented struct and union fields with links to the struct/union documentation for each field: +-

      +-

      - t -

      +-
      Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.4.7
      +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/functions_0x75.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/functions_0x75.html 2013-07-26 19:31:22.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,78 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields +- +- +- +- +-
      +-
      +-
      +-
      +-
      +- +-
      +-
      +-
        +-
      • a
        • +-
      • b
        • +-
      • c
        • +-
      • d
        • +-
      • e
        • +-
      • f
        • +-
      • g
        • +-
      • h
        • +-
      • i
        • +-
      • l
        • +-
      • m
        • +-
      • n
        • +-
      • o
        • +-
      • p
        • +-
      • q
        • +-
      • r
        • +-
      • s
        • +-
      • t
        • +-
      • u
        • +-
      • v
        • +-
      • w
        • +-
      • x
        • +-
      +-
      +- +-

      +-Here is a list of all documented struct and union fields with links to the struct/union documentation for each field: +-

      +-

      - u -

      +-
      Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.4.7
      +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/functions_0x76.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/functions_0x76.html 2013-07-26 19:31:22.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,65 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields +- +- +- +- +-
      +-
      +-
      +-
      +-
      +- +-
      +-
      +-
        +-
      • a
        • +-
      • b
        • +-
      • c
        • +-
      • d
        • +-
      • e
        • +-
      • f
        • +-
      • g
        • +-
      • h
        • +-
      • i
        • +-
      • l
        • +-
      • m
        • +-
      • n
        • +-
      • o
        • +-
      • p
        • +-
      • q
        • +-
      • r
        • +-
      • s
        • +-
      • t
        • +-
      • u
        • +-
      • v
        • +-
      • w
        • +-
      • x
        • +-
      +-
      +- +-

      +-Here is a list of all documented struct and union fields with links to the struct/union documentation for each field: +-

      +-

      - v -

      +-
      Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.4.7
      +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/functions_0x77.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/functions_0x77.html 2013-07-26 19:31:22.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,79 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields +- +- +- +- +-
      +-
      +-
      +-
      +-
      +- +-
      +-
      +-
        +-
      • a
        • +-
      • b
        • +-
      • c
        • +-
      • d
        • +-
      • e
        • +-
      • f
        • +-
      • g
        • +-
      • h
        • +-
      • i
        • +-
      • l
        • +-
      • m
        • +-
      • n
        • +-
      • o
        • +-
      • p
        • +-
      • q
        • +-
      • r
        • +-
      • s
        • +-
      • t
        • +-
      • u
        • +-
      • v
        • +-
      • w
        • +-
      • x
        • +-
      +-
      +- +-

      +-Here is a list of all documented struct and union fields with links to the struct/union documentation for each field: +-

      +-

      - w -

      +-
      Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.4.7
      +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/functions_0x78.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/functions_0x78.html 2013-07-26 19:31:22.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,77 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields +- +- +- +- +-
      +-
      +-
      +-
      +-
      +- +-
      +-
      +-
        +-
      • a
        • +-
      • b
        • +-
      • c
        • +-
      • d
        • +-
      • e
        • +-
      • f
        • +-
      • g
        • +-
      • h
        • +-
      • i
        • +-
      • l
        • +-
      • m
        • +-
      • n
        • +-
      • o
        • +-
      • p
        • +-
      • q
        • +-
      • r
        • +-
      • s
        • +-
      • t
        • +-
      • u
        • +-
      • v
        • +-
      • w
        • +-
      • x
        • +-
      +-
      +- +-

      +-Here is a list of all documented struct and union fields with links to the struct/union documentation for each field: +-

      +-

      - x -

      +-
      Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.4.7
      +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/functions_func.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/functions_func.html 2013-07-26 19:31:22.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/functions_func.html 2013-07-26 19:34:42.000000000 +0000 +@@ -2,35 +2,17 @@ + + DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields - Functions + +- + +- +-
      +-
      +-
      +-
      +-
      +- +-
      +-  ++ ++
      Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
      ++
      All | Functions | Variables
      ++ +

      +

      +-
      Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++: dwc_otg_qtd, dwc_hc ++
      Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
      ++doxygen 1.3.9.1
      + + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/functions_vars.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/functions_vars.html 2013-07-26 19:31:22.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/functions_vars.html 2013-07-26 19:34:42.000000000 +0000 +@@ -2,81 +2,593 @@ + + DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields - Variables + +- + +- +-
      +-
      +-
      +-
      +-
      +- +-
      +-
      +-
        +-
      • a
        • +-
      • b
        • +-
      • c
        • +-
      • d
        • +-
      • e
        • +-
      • f
        • +-
      • g
        • +-
      • h
        • +-
      • i
        • +-
      • l
        • +-
      • m
        • +-
      • n
        • +-
      • o
        • +-
      • p
        • +-
      • q
        • +-
      • r
        • +-
      • s
        • +-
      • t
        • +-
      • u
        • +-
      • v
        • +-
      • w
        • +-
      • x
        • +-
      +-
      ++ ++
      Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
      ++
      All | Functions | Variables
      ++
      a | b | c | d | e | f | g | h | i | l | m | n | o | p | q | r | s | t | u | w | x
      + +

      +-  ++ +

      +

      - a -

      +-
      Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++: host_dma_desc_sts
    • a_alt_hnp_support ++: dwc_otg_pcd
    • a_hnp_support ++: dwc_otg_pcd
    • a_qtd ++: host_dma_desc_sts
    • ack ++: hcint_data
    • active ++: dwc_ep
    • adevtoutchng ++: gotgint_data
    • adp ++: dwc_otg_core_if
    • adp_enable ++: dwc_otg_core_if
    • adp_int ++: gpwrdn_data
    • adp_prb_int ++: adpctl_data
    • adp_prb_int_msk ++: adpctl_data
    • adp_sns_int ++: adpctl_data
    • adp_sns_int_msk ++: adpctl_data
    • adp_supp_enable ++: dwc_otg_core_params
    • adp_tmout_int ++: adpctl_data
    • adp_tmout_int_msk ++: adpctl_data
    • adpctl ++: dwc_otg_core_global_regs
    • adpen ++: adpctl_data
    • adpres ++: adpctl_data
    • ahb_single ++: dwc_otg_core_params
    • ahb_thr_ratio ++: dthrctl_data, dwc_otg_core_params
    • ahberr ++: hcint_data, doepint_data, diepint_data
    • ahbidle ++: grstctl_data
    • align_buff ++: dwc_hc
    • appl_resp ++: glpmctl_data
    • ar ++: adpctl_data
    • arbprken ++: dthrctl_data ++

      - b -

      ++

      - c -

      ++

      - d -

      ++

      - e -

      ++

      - f -

      ++

      - g -

      ++

      - h -

      ++

      - i -

      ++

      - l -

      ++

      - m -

      ++

      - n -

      ++

      - o -

      ++

      - p -

      ++

      - q -

      ++

      - r -

      ++

      - s -

      ++

      - t -

      ++

      - u -

      ++

      - w -

      ++

      - x -

      ++
      Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
      ++doxygen 1.3.9.1
      • + + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x62.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x62.html 2013-07-26 19:31:22.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,99 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields - Variables +- +- +- +- +-
      +-
      +-
      +-
      +-
      +- +-
      +-
      +-
        +-
      • a
        • +-
      • b
        • +-
      • c
        • +-
      • d
        • +-
      • e
        • +-
      • f
        • +-
      • g
        • +-
      • h
        • +-
      • i
        • +-
      • l
        • +-
      • m
        • +-
      • n
        • +-
      • o
        • +-
      • p
        • +-
      • q
        • +-
      • r
        • +-
      • s
        • +-
      • t
        • +-
      • u
        • +-
      • v
        • +-
      • w
        • +-
      • x
        • +-
      +-
      +- +-

      +-  +-

      +-

      - b -

      +-
      Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.4.7
      +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x63.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x63.html 2013-07-26 19:31:22.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,110 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields - Variables +- +- +- +- +-
      +-
      +-
      +-
      +-
      +- +-
      +-
      +-
        +-
      • a
        • +-
      • b
        • +-
      • c
        • +-
      • d
        • +-
      • e
        • +-
      • f
        • +-
      • g
        • +-
      • h
        • +-
      • i
        • +-
      • l
        • +-
      • m
        • +-
      • n
        • +-
      • o
        • +-
      • p
        • +-
      • q
        • +-
      • r
        • +-
      • s
        • +-
      • t
        • +-
      • u
        • +-
      • v
        • +-
      • w
        • +-
      • x
        • +-
      +-
      +- +-

      +-  +-

      +-

      - c -

      +-
      Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.4.7
      +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x64.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x64.html 2013-07-26 19:31:22.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,157 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields - Variables +- +- +- +- +-
      +-
      +-
      +-
      +-
      +- +-
      +-
      +-
        +-
      • a
        • +-
      • b
        • +-
      • c
        • +-
      • d
        • +-
      • e
        • +-
      • f
        • +-
      • g
        • +-
      • h
        • +-
      • i
        • +-
      • l
        • +-
      • m
        • +-
      • n
        • +-
      • o
        • +-
      • p
        • +-
      • q
        • +-
      • r
        • +-
      • s
        • +-
      • t
        • +-
      • u
        • +-
      • v
        • +-
      • w
        • +-
      • x
        • +-
      +-
      +- +-

      +-  +-

      +-

      - d -

      +-
      Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.4.7
      +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x65.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x65.html 2013-07-26 19:31:22.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,109 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields - Variables +- +- +- +- +-
      +-
      +-
      +-
      +-
      +- +-
      +-
      +-
        +-
      • a
        • +-
      • b
        • +-
      • c
        • +-
      • d
        • +-
      • e
        • +-
      • f
        • +-
      • g
        • +-
      • h
        • +-
      • i
        • +-
      • l
        • +-
      • m
        • +-
      • n
        • +-
      • o
        • +-
      • p
        • +-
      • q
        • +-
      • r
        • +-
      • s
        • +-
      • t
        • +-
      • u
        • +-
      • v
        • +-
      • w
        • +-
      • x
        • +-
      +-
      +- +-

      +-  +-

      +-

      - e -

      +-
      Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.4.7
      +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x66.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x66.html 2013-07-26 19:31:22.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,81 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields - Variables +- +- +- +- +-
      +-
      +-
      +-
      +-
      +- +-
      +-
      +-
        +-
      • a
        • +-
      • b
        • +-
      • c
        • +-
      • d
        • +-
      • e
        • +-
      • f
        • +-
      • g
        • +-
      • h
        • +-
      • i
        • +-
      • l
        • +-
      • m
        • +-
      • n
        • +-
      • o
        • +-
      • p
        • +-
      • q
        • +-
      • r
        • +-
      • s
        • +-
      • t
        • +-
      • u
        • +-
      • v
        • +-
      • w
        • +-
      • x
        • +-
      +-
      +- +-

      +-  +-

      +-

      - f -

      +-
      Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.4.7
      +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x67.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x67.html 2013-07-26 19:31:22.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,95 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields - Variables +- +- +- +- +-
      +-
      +-
      +-
      +-
      +- +-
      +-
      +-
        +-
      • a
        • +-
      • b
        • +-
      • c
        • +-
      • d
        • +-
      • e
        • +-
      • f
        • +-
      • g
        • +-
      • h
        • +-
      • i
        • +-
      • l
        • +-
      • m
        • +-
      • n
        • +-
      • o
        • +-
      • p
        • +-
      • q
        • +-
      • r
        • +-
      • s
        • +-
      • t
        • +-
      • u
        • +-
      • v
        • +-
      • w
        • +-
      • x
        • +-
      +-
      +- +-

      +-  +-

      +-

      - g -

      +-
      Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.4.7
      +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x68.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x68.html 2013-07-26 19:31:22.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,119 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields - Variables +- +- +- +- +-
      +-
      +-
      +-
      +-
      +- +-
      +-
      +-
        +-
      • a
        • +-
      • b
        • +-
      • c
        • +-
      • d
        • +-
      • e
        • +-
      • f
        • +-
      • g
        • +-
      • h
        • +-
      • i
        • +-
      • l
        • +-
      • m
        • +-
      • n
        • +-
      • o
        • +-
      • p
        • +-
      • q
        • +-
      • r
        • +-
      • s
        • +-
      • t
        • +-
      • u
        • +-
      • v
        • +-
      • w
        • +-
      • x
        • +-
      +-
      +- +-

      +-  +-

      +-

      - h -

      +-
      Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.4.7
      +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x69.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x69.html 2013-07-26 19:31:22.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,121 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields - Variables +- +- +- +- +-
      +-
      +-
      +-
      +-
      +- +-
      +-
      +-
        +-
      • a
        • +-
      • b
        • +-
      • c
        • +-
      • d
        • +-
      • e
        • +-
      • f
        • +-
      • g
        • +-
      • h
        • +-
      • i
        • +-
      • l
        • +-
      • m
        • +-
      • n
        • +-
      • o
        • +-
      • p
        • +-
      • q
        • +-
      • r
        • +-
      • s
        • +-
      • t
        • +-
      • u
        • +-
      • v
        • +-
      • w
        • +-
      • x
        • +-
      +-
      +- +-

      +-  +-

      +-

      - i -

      +-
      Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.4.7
      +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x6c.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x6c.html 2013-07-26 19:31:22.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,74 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields - Variables +- +- +- +- +-
      +-
      +-
      +-
      +-
      +- +-
      +-
      +-
        +-
      • a
        • +-
      • b
        • +-
      • c
        • +-
      • d
        • +-
      • e
        • +-
      • f
        • +-
      • g
        • +-
      • h
        • +-
      • i
        • +-
      • l
        • +-
      • m
        • +-
      • n
        • +-
      • o
        • +-
      • p
        • +-
      • q
        • +-
      • r
        • +-
      • s
        • +-
      • t
        • +-
      • u
        • +-
      • v
        • +-
      • w
        • +-
      • x
        • +-
      +-
      +- +-

      +-  +-

      +-

      - l -

      +-
      Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.4.7
      +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x6d.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x6d.html 2013-07-26 19:31:22.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,79 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields - Variables +- +- +- +- +-
      +-
      +-
      +-
      +-
      +- +-
      +-
      +-
        +-
      • a
        • +-
      • b
        • +-
      • c
        • +-
      • d
        • +-
      • e
        • +-
      • f
        • +-
      • g
        • +-
      • h
        • +-
      • i
        • +-
      • l
        • +-
      • m
        • +-
      • n
        • +-
      • o
        • +-
      • p
        • +-
      • q
        • +-
      • r
        • +-
      • s
        • +-
      • t
        • +-
      • u
        • +-
      • v
        • +-
      • w
        • +-
      • x
        • +-
      +-
      +- +-

      +-  +-

      +-

      - m -

      +-
      Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.4.7
      +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x6e.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x6e.html 2013-07-26 19:31:22.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,99 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields - Variables +- +- +- +- +-
      +-
      +-
      +-
      +-
      +- +-
      +-
      +-
        +-
      • a
        • +-
      • b
        • +-
      • c
        • +-
      • d
        • +-
      • e
        • +-
      • f
        • +-
      • g
        • +-
      • h
        • +-
      • i
        • +-
      • l
        • +-
      • m
        • +-
      • n
        • +-
      • o
        • +-
      • p
        • +-
      • q
        • +-
      • r
        • +-
      • s
        • +-
      • t
        • +-
      • u
        • +-
      • v
        • +-
      • w
        • +-
      • x
        • +-
      +-
      +- +-

      +-  +-

      +-

      - n -

      +-
      Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.4.7
      +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x6f.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x6f.html 2013-07-26 19:31:22.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,101 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields - Variables +- +- +- +- +-
      +-
      +-
      +-
      +-
      +- +-
      +-
      +-
        +-
      • a
        • +-
      • b
        • +-
      • c
        • +-
      • d
        • +-
      • e
        • +-
      • f
        • +-
      • g
        • +-
      • h
        • +-
      • i
        • +-
      • l
        • +-
      • m
        • +-
      • n
        • +-
      • o
        • +-
      • p
        • +-
      • q
        • +-
      • r
        • +-
      • s
        • +-
      • t
        • +-
      • u
        • +-
      • v
        • +-
      • w
        • +-
      • x
        • +-
      +-
      +- +-

      +-  +-

      +-

      - o -

      +-
      Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.4.7
      +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x70.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x70.html 2013-07-26 19:31:22.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,144 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields - Variables +- +- +- +- +-
      +-
      +-
      +-
      +-
      +- +-
      +-
      +-
        +-
      • a
        • +-
      • b
        • +-
      • c
        • +-
      • d
        • +-
      • e
        • +-
      • f
        • +-
      • g
        • +-
      • h
        • +-
      • i
        • +-
      • l
        • +-
      • m
        • +-
      • n
        • +-
      • o
        • +-
      • p
        • +-
      • q
        • +-
      • r
        • +-
      • s
        • +-
      • t
        • +-
      • u
        • +-
      • v
        • +-
      • w
        • +-
      • x
        • +-
      +-
      +- +-

      +-  +-

      +-

      - p -

      +-
      Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.4.7
      +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x71.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x71.html 2013-07-26 19:31:22.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,71 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields - Variables +- +- +- +- +-
      +-
      +-
      +-
      +-
      +- +-
      +-
      +-
        +-
      • a
        • +-
      • b
        • +-
      • c
        • +-
      • d
        • +-
      • e
        • +-
      • f
        • +-
      • g
        • +-
      • h
        • +-
      • i
        • +-
      • l
        • +-
      • m
        • +-
      • n
        • +-
      • o
        • +-
      • p
        • +-
      • q
        • +-
      • r
        • +-
      • s
        • +-
      • t
        • +-
      • u
        • +-
      • v
        • +-
      • w
        • +-
      • x
        • +-
      +-
      +- +-

      +-  +-

      +-

      - q -

      +-
      Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.4.7
      +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x72.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x72.html 2013-07-26 19:31:22.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,141 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields - Variables +- +- +- +- +-
      +-
      +-
      +-
      +-
      +- +-
      +-
      +-
        +-
      • a
        • +-
      • b
        • +-
      • c
        • +-
      • d
        • +-
      • e
        • +-
      • f
        • +-
      • g
        • +-
      • h
        • +-
      • i
        • +-
      • l
        • +-
      • m
        • +-
      • n
        • +-
      • o
        • +-
      • p
        • +-
      • q
        • +-
      • r
        • +-
      • s
        • +-
      • t
        • +-
      • u
        • +-
      • v
        • +-
      • w
        • +-
      • x
        • +-
      +-
      +- +-

      +-  +-

      +-

      - r -

      +-
      Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.4.7
      +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x73.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x73.html 2013-07-26 19:31:22.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,128 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields - Variables +- +- +- +- +-
      +-
      +-
      +-
      +-
      +- +-
      +-
      +-
        +-
      • a
        • +-
      • b
        • +-
      • c
        • +-
      • d
        • +-
      • e
        • +-
      • f
        • +-
      • g
        • +-
      • h
        • +-
      • i
        • +-
      • l
        • +-
      • m
        • +-
      • n
        • +-
      • o
        • +-
      • p
        • +-
      • q
        • +-
      • r
        • +-
      • s
        • +-
      • t
        • +-
      • u
        • +-
      • v
        • +-
      • w
        • +-
      • x
        • +-
      +-
      +- +-

      +-  +-

      +-

      - s -

      +-
      Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.4.7
      +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x74.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x74.html 2013-07-26 19:31:22.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,88 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields - Variables +- +- +- +- +-
      +-
      +-
      +-
      +-
      +- +-
      +-
      +-
        +-
      • a
        • +-
      • b
        • +-
      • c
        • +-
      • d
        • +-
      • e
        • +-
      • f
        • +-
      • g
        • +-
      • h
        • +-
      • i
        • +-
      • l
        • +-
      • m
        • +-
      • n
        • +-
      • o
        • +-
      • p
        • +-
      • q
        • +-
      • r
        • +-
      • s
        • +-
      • t
        • +-
      • u
        • +-
      • v
        • +-
      • w
        • +-
      • x
        • +-
      +-
      +- +-

      +-  +-

      +-

      - t -

      +-
      Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.4.7
      +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x75.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x75.html 2013-07-26 19:31:22.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,78 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields - Variables +- +- +- +- +-
      +-
      +-
      +-
      +-
      +- +-
      +-
      +-
        +-
      • a
        • +-
      • b
        • +-
      • c
        • +-
      • d
        • +-
      • e
        • +-
      • f
        • +-
      • g
        • +-
      • h
        • +-
      • i
        • +-
      • l
        • +-
      • m
        • +-
      • n
        • +-
      • o
        • +-
      • p
        • +-
      • q
        • +-
      • r
        • +-
      • s
        • +-
      • t
        • +-
      • u
        • +-
      • v
        • +-
      • w
        • +-
      • x
        • +-
      +-
      +- +-

      +-  +-

      +-

      - u -

      +-
      Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.4.7
      +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x76.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x76.html 2013-07-26 19:31:22.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,65 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields - Variables +- +- +- +- +-
      +-
      +-
      +-
      +-
      +- +-
      +-
      +-
        +-
      • a
        • +-
      • b
        • +-
      • c
        • +-
      • d
        • +-
      • e
        • +-
      • f
        • +-
      • g
        • +-
      • h
        • +-
      • i
        • +-
      • l
        • +-
      • m
        • +-
      • n
        • +-
      • o
        • +-
      • p
        • +-
      • q
        • +-
      • r
        • +-
      • s
        • +-
      • t
        • +-
      • u
        • +-
      • v
        • +-
      • w
        • +-
      • x
        • +-
      +-
      +- +-

      +-  +-

      +-

      - v -

      +-
      Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.4.7
      +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x77.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x77.html 2013-07-26 19:31:22.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,79 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields - Variables +- +- +- +- +-
      +-
      +-
      +-
      +-
      +- +-
      +-
      +-
        +-
      • a
        • +-
      • b
        • +-
      • c
        • +-
      • d
        • +-
      • e
        • +-
      • f
        • +-
      • g
        • +-
      • h
        • +-
      • i
        • +-
      • l
        • +-
      • m
        • +-
      • n
        • +-
      • o
        • +-
      • p
        • +-
      • q
        • +-
      • r
        • +-
      • s
        • +-
      • t
        • +-
      • u
        • +-
      • v
        • +-
      • w
        • +-
      • x
        • +-
      +-
      +- +-

      +-  +-

      +-

      - w -

      +-
      Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.4.7
      +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x78.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/functions_vars_0x78.html 2013-07-26 19:31:22.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,77 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields - Variables +- +- +- +- +-
      +-
      +-
      +-
      +-
      +- +-
      +-
      +-
        +-
      • a
        • +-
      • b
        • +-
      • c
        • +-
      • d
        • +-
      • e
        • +-
      • f
        • +-
      • g
        • +-
      • h
        • +-
      • i
        • +-
      • l
        • +-
      • m
        • +-
      • n
        • +-
      • o
        • +-
      • p
        • +-
      • q
        • +-
      • r
        • +-
      • s
        • +-
      • t
        • +-
      • u
        • +-
      • v
        • +-
      • w
        • +-
      • x
        • +-
      +-
      +- +-

      +-  +-

      +-

      - x -

      +-
      Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.4.7
      +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/globals.html 2013-07-26 19:31:22.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals.html 2013-07-26 19:34:43.000000000 +0000 +@@ -1,87 +1,680 @@ + + +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Globals + +- + +- +-
      +-
      +-
      +-
      +-
      +- +-
      +-
      +-
        +-
      • _
        • +-
      • a
        • +-
      • b
        • +-
      • c
        • +-
      • d
        • +-
      • e
        • +-
      • f
        • +-
      • g
        • +-
      • h
        • +-
      • i
        • +-
      • k
        • +-
      • m
        • +-
      • n
        • +-
      • o
        • +-
      • p
        • +-
      • q
        • +-
      • r
        • +-
      • s
        • +-
      • t
        • +-
      • u
        • +-
      • v
        • +-
      • w
        • +-
      +-
      ++ ++
      Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
      ++
      All | Functions | Variables | Typedefs | Enumerations | Enumeration values | Defines
      ++
      _ | a | b | c | d | e | f | g | h | i | k | m | o | p | q | r | s | u | v | w | x
      + +

      +-Here is a list of all documented functions, variables, defines, enums, and typedefs with links to the documentation: ++ +

      +-

      - _ -

      +-
      Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++Here is a list of all documented functions, variables, defines, enums, and typedefs with links to the documentation:

      - _ -

      ++

      - a -

      ++

      - b -

      ++

      - c -

      ++

      - d -

      ++

      - e -

      ++

      - f -

      ++

      - g -

      ++

      - h -

      ++

      - i -

      ++

      - k -

      ++

      - m -

      ++

      - o -

      ++

      - p -

      ++

      - q -

      ++

      - r -

      ++

      - s -

      ++

      - u -

      ++

      - v -

      ++

      - w -

      ++

      - x -

      ++
      Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
      ++doxygen 1.3.9.1
      + + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_0x61.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/globals_0x61.html 2013-07-26 19:31:22.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,76 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields +- +- +- +- +-
      +-
      +-
      +-
      +-
      +- +-
      +-
      +-
        +-
      • _
        • +-
      • a
        • +-
      • b
        • +-
      • c
        • +-
      • d
        • +-
      • e
        • +-
      • f
        • +-
      • g
        • +-
      • h
        • +-
      • i
        • +-
      • k
        • +-
      • m
        • +-
      • n
        • +-
      • o
        • +-
      • p
        • +-
      • q
        • +-
      • r
        • +-
      • s
        • +-
      • t
        • +-
      • u
        • +-
      • v
        • +-
      • w
        • +-
      +-
      +- +-

      +-Here is a list of all documented functions, variables, defines, enums, and typedefs with links to the documentation: +-

      +-

      - a -

      +-
      Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.4.7
      +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_0x62.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/globals_0x62.html 2013-07-26 19:31:22.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,83 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields +- +- +- +- +-
      +-
      +-
      +-
      +-
      +- +-
      +-
      +-
        +-
      • _
        • +-
      • a
        • +-
      • b
        • +-
      • c
        • +-
      • d
        • +-
      • e
        • +-
      • f
        • +-
      • g
        • +-
      • h
        • +-
      • i
        • +-
      • k
        • +-
      • m
        • +-
      • n
        • +-
      • o
        • +-
      • p
        • +-
      • q
        • +-
      • r
        • +-
      • s
        • +-
      • t
        • +-
      • u
        • +-
      • v
        • +-
      • w
        • +-
      +-
      +- +-

      +-Here is a list of all documented functions, variables, defines, enums, and typedefs with links to the documentation: +-

      +-

      - b -

      +-
      Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.4.7
      +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_0x63.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/globals_0x63.html 2013-07-26 19:31:22.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,100 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields +- +- +- +- +-
      +-
      +-
      +-
      +-
      +- +-
      +-
      +-
        +-
      • _
        • +-
      • a
        • +-
      • b
        • +-
      • c
        • +-
      • d
        • +-
      • e
        • +-
      • f
        • +-
      • g
        • +-
      • h
        • +-
      • i
        • +-
      • k
        • +-
      • m
        • +-
      • n
        • +-
      • o
        • +-
      • p
        • +-
      • q
        • +-
      • r
        • +-
      • s
        • +-
      • t
        • +-
      • u
        • +-
      • v
        • +-
      • w
        • +-
      +-
      +- +-

      +-Here is a list of all documented functions, variables, defines, enums, and typedefs with links to the documentation: +-

      +-

      - c -

      +-
      Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.4.7
      +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_0x64.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/globals_0x64.html 2013-07-26 19:31:22.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,686 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields +- +- +- +- +-
      +-
      +-
      +-
      +-
      +- +-
      +-
      +-
        +-
      • _
        • +-
      • a
        • +-
      • b
        • +-
      • c
        • +-
      • d
        • +-
      • e
        • +-
      • f
        • +-
      • g
        • +-
      • h
        • +-
      • i
        • +-
      • k
        • +-
      • m
        • +-
      • n
        • +-
      • o
        • +-
      • p
        • +-
      • q
        • +-
      • r
        • +-
      • s
        • +-
      • t
        • +-
      • u
        • +-
      • v
        • +-
      • w
        • +-
      +-
      +- +-

      +-Here is a list of all documented functions, variables, defines, enums, and typedefs with links to the documentation: +-

      +-

      - d -

      +-
      Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.4.7
      +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_0x65.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/globals_0x65.html 2013-07-26 19:31:22.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,78 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields +- +- +- +- +-
      +-
      +-
      +-
      +-
      +- +-
      +-
      +-
        +-
      • _
        • +-
      • a
        • +-
      • b
        • +-
      • c
        • +-
      • d
        • +-
      • e
        • +-
      • f
        • +-
      • g
        • +-
      • h
        • +-
      • i
        • +-
      • k
        • +-
      • m
        • +-
      • n
        • +-
      • o
        • +-
      • p
        • +-
      • q
        • +-
      • r
        • +-
      • s
        • +-
      • t
        • +-
      • u
        • +-
      • v
        • +-
      • w
        • +-
      +-
      +- +-

      +-Here is a list of all documented functions, variables, defines, enums, and typedefs with links to the documentation: +-

      +-

      - e -

      +-
      Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.4.7
      +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_0x66.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/globals_0x66.html 2013-07-26 19:31:22.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,87 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields +- +- +- +- +-
      +-
      +-
      +-
      +-
      +- +-
      +-
      +-
        +-
      • _
        • +-
      • a
        • +-
      • b
        • +-
      • c
        • +-
      • d
        • +-
      • e
        • +-
      • f
        • +-
      • g
        • +-
      • h
        • +-
      • i
        • +-
      • k
        • +-
      • m
        • +-
      • n
        • +-
      • o
        • +-
      • p
        • +-
      • q
        • +-
      • r
        • +-
      • s
        • +-
      • t
        • +-
      • u
        • +-
      • v
        • +-
      • w
        • +-
      +-
      +- +-

      +-Here is a list of all documented functions, variables, defines, enums, and typedefs with links to the documentation: +-

      +-

      - f -

      +-
      Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.4.7
      +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_0x67.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/globals_0x67.html 2013-07-26 19:31:22.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,93 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields +- +- +- +- +-
      +-
      +-
      +-
      +-
      +- +-
      +-
      +-
        +-
      • _
        • +-
      • a
        • +-
      • b
        • +-
      • c
        • +-
      • d
        • +-
      • e
        • +-
      • f
        • +-
      • g
        • +-
      • h
        • +-
      • i
        • +-
      • k
        • +-
      • m
        • +-
      • n
        • +-
      • o
        • +-
      • p
        • +-
      • q
        • +-
      • r
        • +-
      • s
        • +-
      • t
        • +-
      • u
        • +-
      • v
        • +-
      • w
        • +-
      +-
      +- +-

      +-Here is a list of all documented functions, variables, defines, enums, and typedefs with links to the documentation: +-

      +-

      - g -

      +-
      Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.4.7
      +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_0x68.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/globals_0x68.html 2013-07-26 19:31:22.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,129 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields +- +- +- +- +-
      +-
      +-
      +-
      +-
      +- +-
      +-
      +-
        +-
      • _
        • +-
      • a
        • +-
      • b
        • +-
      • c
        • +-
      • d
        • +-
      • e
        • +-
      • f
        • +-
      • g
        • +-
      • h
        • +-
      • i
        • +-
      • k
        • +-
      • m
        • +-
      • n
        • +-
      • o
        • +-
      • p
        • +-
      • q
        • +-
      • r
        • +-
      • s
        • +-
      • t
        • +-
      • u
        • +-
      • v
        • +-
      • w
        • +-
      +-
      +- +-

      +-Here is a list of all documented functions, variables, defines, enums, and typedefs with links to the documentation: +-

      +-

      - h -

      +-
      Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.4.7
      +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_0x69.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/globals_0x69.html 2013-07-26 19:31:22.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,76 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields +- +- +- +- +-
      +-
      +-
      +-
      +-
      +- +-
      +-
      +-
        +-
      • _
        • +-
      • a
        • +-
      • b
        • +-
      • c
        • +-
      • d
        • +-
      • e
        • +-
      • f
        • +-
      • g
        • +-
      • h
        • +-
      • i
        • +-
      • k
        • +-
      • m
        • +-
      • n
        • +-
      • o
        • +-
      • p
        • +-
      • q
        • +-
      • r
        • +-
      • s
        • +-
      • t
        • +-
      • u
        • +-
      • v
        • +-
      • w
        • +-
      +-
      +- +-

      +-Here is a list of all documented functions, variables, defines, enums, and typedefs with links to the documentation: +-

      +-

      - i -

      +-
      Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.4.7
      +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_0x6b.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/globals_0x6b.html 2013-07-26 19:31:22.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,69 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields +- +- +- +- +-
      +-
      +-
      +-
      +-
      +- +-
      +-
      +-
        +-
      • _
        • +-
      • a
        • +-
      • b
        • +-
      • c
        • +-
      • d
        • +-
      • e
        • +-
      • f
        • +-
      • g
        • +-
      • h
        • +-
      • i
        • +-
      • k
        • +-
      • m
        • +-
      • n
        • +-
      • o
        • +-
      • p
        • +-
      • q
        • +-
      • r
        • +-
      • s
        • +-
      • t
        • +-
      • u
        • +-
      • v
        • +-
      • w
        • +-
      +-
      +- +-

      +-Here is a list of all documented functions, variables, defines, enums, and typedefs with links to the documentation: +-

      +-

      - k -

      +-
      Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.4.7
      +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_0x6d.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/globals_0x6d.html 2013-07-26 19:31:22.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,84 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields +- +- +- +- +-
      +-
      +-
      +-
      +-
      +- +-
      +-
      +-
        +-
      • _
        • +-
      • a
        • +-
      • b
        • +-
      • c
        • +-
      • d
        • +-
      • e
        • +-
      • f
        • +-
      • g
        • +-
      • h
        • +-
      • i
        • +-
      • k
        • +-
      • m
        • +-
      • n
        • +-
      • o
        • +-
      • p
        • +-
      • q
        • +-
      • r
        • +-
      • s
        • +-
      • t
        • +-
      • u
        • +-
      • v
        • +-
      • w
        • +-
      +-
      +- +-

      +-Here is a list of all documented functions, variables, defines, enums, and typedefs with links to the documentation: +-

      +-

      - m -

      +-
      Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.4.7
      +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_0x6e.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/globals_0x6e.html 2013-07-26 19:31:22.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,68 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields +- +- +- +- +-
      +-
      +-
      +-
      +-
      +- +-
      +-
      +-
        +-
      • _
        • +-
      • a
        • +-
      • b
        • +-
      • c
        • +-
      • d
        • +-
      • e
        • +-
      • f
        • +-
      • g
        • +-
      • h
        • +-
      • i
        • +-
      • k
        • +-
      • m
        • +-
      • n
        • +-
      • o
        • +-
      • p
        • +-
      • q
        • +-
      • r
        • +-
      • s
        • +-
      • t
        • +-
      • u
        • +-
      • v
        • +-
      • w
        • +-
      +-
      +- +-

      +-Here is a list of all documented functions, variables, defines, enums, and typedefs with links to the documentation: +-

      +-

      - n -

      +-
      Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.4.7
      +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_0x6f.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/globals_0x6f.html 2013-07-26 19:31:22.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,73 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields +- +- +- +- +-
      +-
      +-
      +-
      +-
      +- +-
      +-
      +-
        +-
      • _
        • +-
      • a
        • +-
      • b
        • +-
      • c
        • +-
      • d
        • +-
      • e
        • +-
      • f
        • +-
      • g
        • +-
      • h
        • +-
      • i
        • +-
      • k
        • +-
      • m
        • +-
      • n
        • +-
      • o
        • +-
      • p
        • +-
      • q
        • +-
      • r
        • +-
      • s
        • +-
      • t
        • +-
      • u
        • +-
      • v
        • +-
      • w
        • +-
      +-
      +- +-

      +-Here is a list of all documented functions, variables, defines, enums, and typedefs with links to the documentation: +-

      +-

      - o -

      +-
      Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.4.7
      +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_0x70.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/globals_0x70.html 2013-07-26 19:31:22.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,84 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields +- +- +- +- +-
      +-
      +-
      +-
      +-
      +- +-
      +-
      +-
        +-
      • _
        • +-
      • a
        • +-
      • b
        • +-
      • c
        • +-
      • d
        • +-
      • e
        • +-
      • f
        • +-
      • g
        • +-
      • h
        • +-
      • i
        • +-
      • k
        • +-
      • m
        • +-
      • n
        • +-
      • o
        • +-
      • p
        • +-
      • q
        • +-
      • r
        • +-
      • s
        • +-
      • t
        • +-
      • u
        • +-
      • v
        • +-
      • w
        • +-
      +-
      +- +-

      +-Here is a list of all documented functions, variables, defines, enums, and typedefs with links to the documentation: +-

      +-

      - p -

      +-
      Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.4.7
      +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_0x71.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/globals_0x71.html 2013-07-26 19:31:22.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,70 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields +- +- +- +- +-
      +-
      +-
      +-
      +-
      +- +-
      +-
      +-
        +-
      • _
        • +-
      • a
        • +-
      • b
        • +-
      • c
        • +-
      • d
        • +-
      • e
        • +-
      • f
        • +-
      • g
        • +-
      • h
        • +-
      • i
        • +-
      • k
        • +-
      • m
        • +-
      • n
        • +-
      • o
        • +-
      • p
        • +-
      • q
        • +-
      • r
        • +-
      • s
        • +-
      • t
        • +-
      • u
        • +-
      • v
        • +-
      • w
        • +-
      +-
      +- +-

      +-Here is a list of all documented functions, variables, defines, enums, and typedefs with links to the documentation: +-

      +-

      - q -

      +-
      Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.4.7
      +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_0x72.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/globals_0x72.html 2013-07-26 19:31:22.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,94 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields +- +- +- +- +-
      +-
      +-
      +-
      +-
      +- +-
      +-
      +-
        +-
      • _
        • +-
      • a
        • +-
      • b
        • +-
      • c
        • +-
      • d
        • +-
      • e
        • +-
      • f
        • +-
      • g
        • +-
      • h
        • +-
      • i
        • +-
      • k
        • +-
      • m
        • +-
      • n
        • +-
      • o
        • +-
      • p
        • +-
      • q
        • +-
      • r
        • +-
      • s
        • +-
      • t
        • +-
      • u
        • +-
      • v
        • +-
      • w
        • +-
      +-
      +- +-

      +-Here is a list of all documented functions, variables, defines, enums, and typedefs with links to the documentation: +-

      +-

      - r -

      +-
      Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.4.7
      +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_0x73.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/globals_0x73.html 2013-07-26 19:31:22.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,85 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields +- +- +- +- +-
      +-
      +-
      +-
      +-
      +- +-
      +-
      +-
        +-
      • _
        • +-
      • a
        • +-
      • b
        • +-
      • c
        • +-
      • d
        • +-
      • e
        • +-
      • f
        • +-
      • g
        • +-
      • h
        • +-
      • i
        • +-
      • k
        • +-
      • m
        • +-
      • n
        • +-
      • o
        • +-
      • p
        • +-
      • q
        • +-
      • r
        • +-
      • s
        • +-
      • t
        • +-
      • u
        • +-
      • v
        • +-
      • w
        • +-
      +-
      +- +-

      +-Here is a list of all documented functions, variables, defines, enums, and typedefs with links to the documentation: +-

      +-

      - s -

      +-
      Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.4.7
      +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_0x74.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/globals_0x74.html 2013-07-26 19:31:22.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,68 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields +- +- +- +- +-
      +-
      +-
      +-
      +-
      +- +-
      +-
      +-
        +-
      • _
        • +-
      • a
        • +-
      • b
        • +-
      • c
        • +-
      • d
        • +-
      • e
        • +-
      • f
        • +-
      • g
        • +-
      • h
        • +-
      • i
        • +-
      • k
        • +-
      • m
        • +-
      • n
        • +-
      • o
        • +-
      • p
        • +-
      • q
        • +-
      • r
        • +-
      • s
        • +-
      • t
        • +-
      • u
        • +-
      • v
        • +-
      • w
        • +-
      +-
      +- +-

      +-Here is a list of all documented functions, variables, defines, enums, and typedefs with links to the documentation: +-

      +-

      - t -

      +-
      Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.4.7
      +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_0x75.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/globals_0x75.html 2013-07-26 19:31:22.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,80 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields +- +- +- +- +-
      +-
      +-
      +-
      +-
      +- +-
      +-
      +-
        +-
      • _
        • +-
      • a
        • +-
      • b
        • +-
      • c
        • +-
      • d
        • +-
      • e
        • +-
      • f
        • +-
      • g
        • +-
      • h
        • +-
      • i
        • +-
      • k
        • +-
      • m
        • +-
      • n
        • +-
      • o
        • +-
      • p
        • +-
      • q
        • +-
      • r
        • +-
      • s
        • +-
      • t
        • +-
      • u
        • +-
      • v
        • +-
      • w
        • +-
      +-
      +- +-

      +-Here is a list of all documented functions, variables, defines, enums, and typedefs with links to the documentation: +-

      +-

      - u -

      +-
      Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.4.7
      +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_0x76.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/globals_0x76.html 2013-07-26 19:31:22.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,75 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields +- +- +- +- +-
      +-
      +-
      +-
      +-
      +- +-
      +-
      +-
        +-
      • _
        • +-
      • a
        • +-
      • b
        • +-
      • c
        • +-
      • d
        • +-
      • e
        • +-
      • f
        • +-
      • g
        • +-
      • h
        • +-
      • i
        • +-
      • k
        • +-
      • m
        • +-
      • n
        • +-
      • o
        • +-
      • p
        • +-
      • q
        • +-
      • r
        • +-
      • s
        • +-
      • t
        • +-
      • u
        • +-
      • v
        • +-
      • w
        • +-
      +-
      +- +-

      +-Here is a list of all documented functions, variables, defines, enums, and typedefs with links to the documentation: +-

      +-

      - v -

      +-
      Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.4.7
      +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_0x77.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/globals_0x77.html 2013-07-26 19:31:22.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,74 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields +- +- +- +- +-
      +-
      +-
      +-
      +-
      +- +-
      +-
      +-
        +-
      • _
        • +-
      • a
        • +-
      • b
        • +-
      • c
        • +-
      • d
        • +-
      • e
        • +-
      • f
        • +-
      • g
        • +-
      • h
        • +-
      • i
        • +-
      • k
        • +-
      • m
        • +-
      • n
        • +-
      • o
        • +-
      • p
        • +-
      • q
        • +-
      • r
        • +-
      • s
        • +-
      • t
        • +-
      • u
        • +-
      • v
        • +-
      • w
        • +-
      +-
      +- +-

      +-Here is a list of all documented functions, variables, defines, enums, and typedefs with links to the documentation: +-

      +-

      - w -

      +-
      Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.4.7
      +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_defs.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/globals_defs.html 2013-07-26 19:31:22.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_defs.html 2013-07-26 19:34:43.000000000 +0000 +@@ -1,68 +1,89 @@ + + +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Globals - Defines + +- + +- +-
      +-
      +-
      +-
      +-
      +- +-
      +-
      +-
        +-
      • _
        • +-
      • a
        • +-
      • b
        • +-
      • c
        • +-
      • d
        • +-
      • f
        • +-
      • g
        • +-
      • h
        • +-
      • i
        • +-
      • m
        • +-
      • n
        • +-
      • o
        • +-
      • r
        • +-
      • s
        • +-
      • u
        • +-
      • v
        • +-
      +-
      ++ ++
      Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
      ++
      All | Functions | Variables | Typedefs | Enumerations | Enumeration values | Defines
      ++
      a | b | c | d | f | g | m | o | r | s | u | v
      + +

      +-  ++ +

      +-

      - _ -

      +-
      Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++

      - a -

      ++

      - b -

      ++

      - c -

      ++

      - d -

      ++

      - f -

      ++

      - g -

      ++

      - m -

      ++

      - o -

      ++

      - r -

      ++

      - s -

      ++

      - u -

      ++

      - v -

      ++
      Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
      ++doxygen 1.3.9.1
      + + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_defs_0x61.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/globals_defs_0x61.html 2013-07-26 19:31:22.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,64 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields +- +- +- +- +-
      +-
      +-
      +-
      +-
      +- +-
      +-
      +-
        +-
      • _
        • +-
      • a
        • +-
      • b
        • +-
      • c
        • +-
      • d
        • +-
      • f
        • +-
      • g
        • +-
      • h
        • +-
      • i
        • +-
      • m
        • +-
      • n
        • +-
      • o
        • +-
      • r
        • +-
      • s
        • +-
      • u
        • +-
      • v
        • +-
      +-
      +- +-

      +-  +-

      +-

      - a -

      +-
      Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.4.7
      +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_defs_0x62.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/globals_defs_0x62.html 2013-07-26 19:31:22.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,71 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields +- +- +- +- +-
      +-
      +-
      +-
      +-
      +- +-
      +-
      +-
        +-
      • _
        • +-
      • a
        • +-
      • b
        • +-
      • c
        • +-
      • d
        • +-
      • f
        • +-
      • g
        • +-
      • h
        • +-
      • i
        • +-
      • m
        • +-
      • n
        • +-
      • o
        • +-
      • r
        • +-
      • s
        • +-
      • u
        • +-
      • v
        • +-
      +-
      +- +-

      +-  +-

      +-

      - b -

      +-
      Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.4.7
      +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_defs_0x63.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/globals_defs_0x63.html 2013-07-26 19:31:22.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,74 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields +- +- +- +- +-
      +-
      +-
      +-
      +-
      +- +-
      +-
      +-
        +-
      • _
        • +-
      • a
        • +-
      • b
        • +-
      • c
        • +-
      • d
        • +-
      • f
        • +-
      • g
        • +-
      • h
        • +-
      • i
        • +-
      • m
        • +-
      • n
        • +-
      • o
        • +-
      • r
        • +-
      • s
        • +-
      • u
        • +-
      • v
        • +-
      +-
      +- +-

      +-  +-

      +-

      - c -

      +-
      Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.4.7
      +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_defs_0x64.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/globals_defs_0x64.html 2013-07-26 19:31:22.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,241 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields +- +- +- +- +-
      +-
      +-
      +-
      +-
      +- +-
      +-
      +-
        +-
      • _
        • +-
      • a
        • +-
      • b
        • +-
      • c
        • +-
      • d
        • +-
      • f
        • +-
      • g
        • +-
      • h
        • +-
      • i
        • +-
      • m
        • +-
      • n
        • +-
      • o
        • +-
      • r
        • +-
      • s
        • +-
      • u
        • +-
      • v
        • +-
      +-
      +- +-

      +-  +-

      +-

      - d -

      +-
      Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.4.7
      +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_defs_0x66.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/globals_defs_0x66.html 2013-07-26 19:31:22.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,71 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields +- +- +- +- +-
      +-
      +-
      +-
      +-
      +- +-
      +-
      +-
        +-
      • _
        • +-
      • a
        • +-
      • b
        • +-
      • c
        • +-
      • d
        • +-
      • f
        • +-
      • g
        • +-
      • h
        • +-
      • i
        • +-
      • m
        • +-
      • n
        • +-
      • o
        • +-
      • r
        • +-
      • s
        • +-
      • u
        • +-
      • v
        • +-
      +-
      +- +-

      +-  +-

      +-

      - f -

      +-
      Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.4.7
      +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_defs_0x67.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/globals_defs_0x67.html 2013-07-26 19:31:22.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,62 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields +- +- +- +- +-
      +-
      +-
      +-
      +-
      +- +-
      +-
      +-
        +-
      • _
        • +-
      • a
        • +-
      • b
        • +-
      • c
        • +-
      • d
        • +-
      • f
        • +-
      • g
        • +-
      • h
        • +-
      • i
        • +-
      • m
        • +-
      • n
        • +-
      • o
        • +-
      • r
        • +-
      • s
        • +-
      • u
        • +-
      • v
        • +-
      +-
      +- +-

      +-  +-

      +-

      - g -

      +-
      Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.4.7
      +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_defs_0x68.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/globals_defs_0x68.html 2013-07-26 19:31:22.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,63 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields +- +- +- +- +-
      +-
      +-
      +-
      +-
      +- +-
      +-
      +-
        +-
      • _
        • +-
      • a
        • +-
      • b
        • +-
      • c
        • +-
      • d
        • +-
      • f
        • +-
      • g
        • +-
      • h
        • +-
      • i
        • +-
      • m
        • +-
      • n
        • +-
      • o
        • +-
      • r
        • +-
      • s
        • +-
      • u
        • +-
      • v
        • +-
      +-
      +- +-

      +-  +-

      +-

      - h -

      +-
      Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.4.7
      +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_defs_0x69.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/globals_defs_0x69.html 2013-07-26 19:31:22.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,62 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields +- +- +- +- +-
      +-
      +-
      +-
      +-
      +- +-
      +-
      +-
        +-
      • _
        • +-
      • a
        • +-
      • b
        • +-
      • c
        • +-
      • d
        • +-
      • f
        • +-
      • g
        • +-
      • h
        • +-
      • i
        • +-
      • m
        • +-
      • n
        • +-
      • o
        • +-
      • r
        • +-
      • s
        • +-
      • u
        • +-
      • v
        • +-
      +-
      +- +-

      +-  +-

      +-

      - i -

      +-
      Generated on Tue May 5 02:22:50 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.4.7
      +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_defs_0x6d.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/globals_defs_0x6d.html 2013-07-26 19:31:22.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,76 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields +- +- +- +- +-
      +-
      +-
      +-
      +-
      +- +-
      +-
      +-
        +-
      • _
        • +-
      • a
        • +-
      • b
        • +-
      • c
        • +-
      • d
        • +-
      • f
        • +-
      • g
        • +-
      • h
        • +-
      • i
        • +-
      • m
        • +-
      • n
        • +-
      • o
        • +-
      • r
        • +-
      • s
        • +-
      • u
        • +-
      • v
        • +-
      +-
      +- +-

      +-  +-

      +-

      - m -

      +-
      Generated on Tue May 5 02:22:50 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.4.7
      +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_defs_0x6e.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/globals_defs_0x6e.html 2013-07-26 19:31:22.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,62 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields +- +- +- +- +-
      +-
      +-
      +-
      +-
      +- +-
      +-
      +-
        +-
      • _
        • +-
      • a
        • +-
      • b
        • +-
      • c
        • +-
      • d
        • +-
      • f
        • +-
      • g
        • +-
      • h
        • +-
      • i
        • +-
      • m
        • +-
      • n
        • +-
      • o
        • +-
      • r
        • +-
      • s
        • +-
      • u
        • +-
      • v
        • +-
      +-
      +- +-

      +-  +-

      +-

      - n -

      +-
      Generated on Tue May 5 02:22:50 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.4.7
      +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_defs_0x6f.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/globals_defs_0x6f.html 2013-07-26 19:31:22.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,67 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields +- +- +- +- +-
      +-
      +-
      +-
      +-
      +- +-
      +-
      +-
        +-
      • _
        • +-
      • a
        • +-
      • b
        • +-
      • c
        • +-
      • d
        • +-
      • f
        • +-
      • g
        • +-
      • h
        • +-
      • i
        • +-
      • m
        • +-
      • n
        • +-
      • o
        • +-
      • r
        • +-
      • s
        • +-
      • u
        • +-
      • v
        • +-
      +-
      +- +-

      +-  +-

      +-

      - o -

      +-
      Generated on Tue May 5 02:22:50 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.4.7
      +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_defs_0x72.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/globals_defs_0x72.html 2013-07-26 19:31:22.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,66 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields +- +- +- +- +-
      +-
      +-
      +-
      +-
      +- +-
      +-
      +-
        +-
      • _
        • +-
      • a
        • +-
      • b
        • +-
      • c
        • +-
      • d
        • +-
      • f
        • +-
      • g
        • +-
      • h
        • +-
      • i
        • +-
      • m
        • +-
      • n
        • +-
      • o
        • +-
      • r
        • +-
      • s
        • +-
      • u
        • +-
      • v
        • +-
      +-
      +- +-

      +-  +-

      +-

      - r -

      +-
      Generated on Tue May 5 02:22:50 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.4.7
      +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_defs_0x73.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/globals_defs_0x73.html 2013-07-26 19:31:22.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,63 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields +- +- +- +- +-
      +-
      +-
      +-
      +-
      +- +-
      +-
      +-
        +-
      • _
        • +-
      • a
        • +-
      • b
        • +-
      • c
        • +-
      • d
        • +-
      • f
        • +-
      • g
        • +-
      • h
        • +-
      • i
        • +-
      • m
        • +-
      • n
        • +-
      • o
        • +-
      • r
        • +-
      • s
        • +-
      • u
        • +-
      • v
        • +-
      +-
      +- +-

      +-  +-

      +-

      - s -

      +-
      Generated on Tue May 5 02:22:50 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.4.7
      +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_defs_0x75.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/globals_defs_0x75.html 2013-07-26 19:31:22.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,64 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields +- +- +- +- +-
      +-
      +-
      +-
      +-
      +- +-
      +-
      +-
        +-
      • _
        • +-
      • a
        • +-
      • b
        • +-
      • c
        • +-
      • d
        • +-
      • f
        • +-
      • g
        • +-
      • h
        • +-
      • i
        • +-
      • m
        • +-
      • n
        • +-
      • o
        • +-
      • r
        • +-
      • s
        • +-
      • u
        • +-
      • v
        • +-
      +-
      +- +-

      +-  +-

      +-

      - u -

      +-
      Generated on Tue May 5 02:22:50 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.4.7
      +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_defs_0x76.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/globals_defs_0x76.html 2013-07-26 19:31:22.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,68 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields +- +- +- +- +-
      +-
      +-
      +-
      +-
      +- +-
      +-
      +-
        +-
      • _
        • +-
      • a
        • +-
      • b
        • +-
      • c
        • +-
      • d
        • +-
      • f
        • +-
      • g
        • +-
      • h
        • +-
      • i
        • +-
      • m
        • +-
      • n
        • +-
      • o
        • +-
      • r
        • +-
      • s
        • +-
      • u
        • +-
      • v
        • +-
      +-
      +- +-

      +-  +-

      +-

      - v -

      +-
      Generated on Tue May 5 02:22:50 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.4.7
      +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_enum.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/globals_enum.html 2013-07-26 19:31:22.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_enum.html 2013-07-26 19:34:43.000000000 +0000 +@@ -1,44 +1,21 @@ + + +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Globals - Enumerations + +- + +- +-
      +-
      +-
      +-
      +-
      +- +-
      +-  ++ ++
      Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
      ++
      All | Functions | Variables | Typedefs | Enumerations | Enumeration values | Defines
      ++ +

      +

      +-
      Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++: dwc_otg_hcd.h
    • dwc_otg_lx_state ++: dwc_otg_cil.h
    • dwc_otg_transaction_type ++: dwc_otg_hcd.h
    • ep0_state ++: dwc_otg_pcd.h ++
      Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
      ++doxygen 1.3.9.1
      • + + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_eval.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/globals_eval.html 2013-07-26 19:31:22.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_eval.html 2013-07-26 19:34:43.000000000 +0000 +@@ -1,43 +1,21 @@ + + +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Globals - Enumeration values + +- + +- +-
      +-
      +-
      +-
      +-
      +- +-
      +-  ++ ++
      Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
      ++
      All | Functions | Variables | Typedefs | Enumerations | Enumeration values | Defines
      ++ +

      +

      +-
      Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++: dwc_otg_cil.h
    • DWC_OTG_L1 ++: dwc_otg_cil.h
    • DWC_OTG_L2 ++: dwc_otg_cil.h
    • DWC_OTG_L3 ++: dwc_otg_cil.h ++
      Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
      ++doxygen 1.3.9.1
      • + + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_func.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/globals_func.html 2013-07-26 19:31:22.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_func.html 2013-07-26 19:34:43.000000000 +0000 +@@ -1,77 +1,522 @@ + + +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Globals - Functions + +- + +- +-
      +-
      +-
      +-
      +-
      +- +-
      +-
      +-
        +-
      • _
        • +-
      • a
        • +-
      • b
        • +-
      • c
        • +-
      • d
        • +-
      • e
        • +-
      • f
        • +-
      • g
        • +-
      • h
        • +-
      • i
        • +-
      • k
        • +-
      • m
        • +-
      • p
        • +-
      • q
        • +-
      • r
        • +-
      • s
        • +-
      • u
        • +-
      • v
        • +-
      • w
        • +-
      +-
      ++ ++
      Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
      ++
      All | Functions | Variables | Typedefs | Enumerations | Enumeration values | Defines
      ++
      _ | a | b | c | d | e | f | g | h | i | k | m | p | q | r | s | u | v | w
      + +

      +-  ++ +

      +

      - _ -

      +-
      Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++: dwc_otg_hcd_linux.c
    • _hnp_changed() ++: dwc_otg_pcd_linux.c ++

      - a -

      ++

      - b -

      ++

      - c -

      ++

      - d -

      ++

      - e -

      ++

      - f -

      ++

      - g -

      ++

      - h -

      ++

      - i -

      ++

      - k -

      ++

      - m -

      ++

      - p -

      ++

      - q -

      ++

      - r -

      ++

      - s -

      ++

      - u -

      ++

      - v -

      ++

      - w -

      ++
      Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
      ++doxygen 1.3.9.1
      • + + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_func_0x61.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/globals_func_0x61.html 2013-07-26 19:31:22.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,70 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields +- +- +- +- +-
      +-
      +-
      +-
      +-
      +- +-
      +-
      +-
        +-
      • _
        • +-
      • a
        • +-
      • b
        • +-
      • c
        • +-
      • d
        • +-
      • e
        • +-
      • f
        • +-
      • g
        • +-
      • h
        • +-
      • i
        • +-
      • k
        • +-
      • m
        • +-
      • p
        • +-
      • q
        • +-
      • r
        • +-
      • s
        • +-
      • u
        • +-
      • v
        • +-
      • w
        • +-
      +-
      +- +-

      +-  +-

      +-

      - a -

      +-
      Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.4.7
      +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_func_0x62.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/globals_func_0x62.html 2013-07-26 19:31:22.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,68 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields +- +- +- +- +-
      +-
      +-
      +-
      +-
      +- +-
      +-
      +-
        +-
      • _
        • +-
      • a
        • +-
      • b
        • +-
      • c
        • +-
      • d
        • +-
      • e
        • +-
      • f
        • +-
      • g
        • +-
      • h
        • +-
      • i
        • +-
      • k
        • +-
      • m
        • +-
      • p
        • +-
      • q
        • +-
      • r
        • +-
      • s
        • +-
      • u
        • +-
      • v
        • +-
      • w
        • +-
      +-
      +- +-

      +-  +-

      +-

      - b -

      +-
      Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.4.7
      +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_func_0x63.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/globals_func_0x63.html 2013-07-26 19:31:22.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,77 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields +- +- +- +- +-
      +-
      +-
      +-
      +-
      +- +-
      +-
      +-
        +-
      • _
        • +-
      • a
        • +-
      • b
        • +-
      • c
        • +-
      • d
        • +-
      • e
        • +-
      • f
        • +-
      • g
        • +-
      • h
        • +-
      • i
        • +-
      • k
        • +-
      • m
        • +-
      • p
        • +-
      • q
        • +-
      • r
        • +-
      • s
        • +-
      • u
        • +-
      • v
        • +-
      • w
        • +-
      +-
      +- +-

      +-  +-

      +-

      - c -

      +-
      Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.4.7
      +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_func_0x64.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/globals_func_0x64.html 2013-07-26 19:31:22.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,427 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields +- +- +- +- +-
      +-
      +-
      +-
      +-
      +- +-
      +-
      +-
        +-
      • _
        • +-
      • a
        • +-
      • b
        • +-
      • c
        • +-
      • d
        • +-
      • e
        • +-
      • f
        • +-
      • g
        • +-
      • h
        • +-
      • i
        • +-
      • k
        • +-
      • m
        • +-
      • p
        • +-
      • q
        • +-
      • r
        • +-
      • s
        • +-
      • u
        • +-
      • v
        • +-
      • w
        • +-
      +-
      +- +-

      +-  +-

      +-

      - d -

      +-
      Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.4.7
      +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_func_0x65.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/globals_func_0x65.html 2013-07-26 19:31:22.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,73 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields +- +- +- +- +-
      +-
      +-
      +-
      +-
      +- +-
      +-
      +-
        +-
      • _
        • +-
      • a
        • +-
      • b
        • +-
      • c
        • +-
      • d
        • +-
      • e
        • +-
      • f
        • +-
      • g
        • +-
      • h
        • +-
      • i
        • +-
      • k
        • +-
      • m
        • +-
      • p
        • +-
      • q
        • +-
      • r
        • +-
      • s
        • +-
      • u
        • +-
      • v
        • +-
      • w
        • +-
      +-
      +- +-

      +-  +-

      +-

      - e -

      +-
      Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.4.7
      +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_func_0x66.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/globals_func_0x66.html 2013-07-26 19:31:22.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,72 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields +- +- +- +- +-
      +-
      +-
      +-
      +-
      +- +-
      +-
      +-
        +-
      • _
        • +-
      • a
        • +-
      • b
        • +-
      • c
        • +-
      • d
        • +-
      • e
        • +-
      • f
        • +-
      • g
        • +-
      • h
        • +-
      • i
        • +-
      • k
        • +-
      • m
        • +-
      • p
        • +-
      • q
        • +-
      • r
        • +-
      • s
        • +-
      • u
        • +-
      • v
        • +-
      • w
        • +-
      +-
      +- +-

      +-  +-

      +-

      - f -

      +-
      Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.4.7
      +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_func_0x67.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/globals_func_0x67.html 2013-07-26 19:31:22.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,78 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields +- +- +- +- +-
      +-
      +-
      +-
      +-
      +- +-
      +-
      +-
        +-
      • _
        • +-
      • a
        • +-
      • b
        • +-
      • c
        • +-
      • d
        • +-
      • e
        • +-
      • f
        • +-
      • g
        • +-
      • h
        • +-
      • i
        • +-
      • k
        • +-
      • m
        • +-
      • p
        • +-
      • q
        • +-
      • r
        • +-
      • s
        • +-
      • u
        • +-
      • v
        • +-
      • w
        • +-
      +-
      +- +-

      +-  +-

      +-

      - g -

      +-
      Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.4.7
      +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_func_0x68.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/globals_func_0x68.html 2013-07-26 19:31:22.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,101 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields +- +- +- +- +-
      +-
      +-
      +-
      +-
      +- +-
      +-
      +-
        +-
      • _
        • +-
      • a
        • +-
      • b
        • +-
      • c
        • +-
      • d
        • +-
      • e
        • +-
      • f
        • +-
      • g
        • +-
      • h
        • +-
      • i
        • +-
      • k
        • +-
      • m
        • +-
      • p
        • +-
      • q
        • +-
      • r
        • +-
      • s
        • +-
      • u
        • +-
      • v
        • +-
      • w
        • +-
      +-
      +- +-

      +-  +-

      +-

      - h -

      +-
      Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.4.7
      +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_func_0x69.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/globals_func_0x69.html 2013-07-26 19:31:22.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,71 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields +- +- +- +- +-
      +-
      +-
      +-
      +-
      +- +-
      +-
      +-
        +-
      • _
        • +-
      • a
        • +-
      • b
        • +-
      • c
        • +-
      • d
        • +-
      • e
        • +-
      • f
        • +-
      • g
        • +-
      • h
        • +-
      • i
        • +-
      • k
        • +-
      • m
        • +-
      • p
        • +-
      • q
        • +-
      • r
        • +-
      • s
        • +-
      • u
        • +-
      • v
        • +-
      • w
        • +-
      +-
      +- +-

      +-  +-

      +-

      - i -

      +-
      Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.4.7
      +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_func_0x6b.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/globals_func_0x6b.html 2013-07-26 19:31:22.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,66 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields +- +- +- +- +-
      +-
      +-
      +-
      +-
      +- +-
      +-
      +-
        +-
      • _
        • +-
      • a
        • +-
      • b
        • +-
      • c
        • +-
      • d
        • +-
      • e
        • +-
      • f
        • +-
      • g
        • +-
      • h
        • +-
      • i
        • +-
      • k
        • +-
      • m
        • +-
      • p
        • +-
      • q
        • +-
      • r
        • +-
      • s
        • +-
      • u
        • +-
      • v
        • +-
      • w
        • +-
      +-
      +- +-

      +-  +-

      +-

      - k -

      +-
      Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.4.7
      +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_func_0x6d.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/globals_func_0x6d.html 2013-07-26 19:31:22.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,66 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields +- +- +- +- +-
      +-
      +-
      +-
      +-
      +- +-
      +-
      +-
        +-
      • _
        • +-
      • a
        • +-
      • b
        • +-
      • c
        • +-
      • d
        • +-
      • e
        • +-
      • f
        • +-
      • g
        • +-
      • h
        • +-
      • i
        • +-
      • k
        • +-
      • m
        • +-
      • p
        • +-
      • q
        • +-
      • r
        • +-
      • s
        • +-
      • u
        • +-
      • v
        • +-
      • w
        • +-
      +-
      +- +-

      +-  +-

      +-

      - m -

      +-
      Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.4.7
      +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_func_0x70.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/globals_func_0x70.html 2013-07-26 19:31:22.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,78 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields +- +- +- +- +-
      +-
      +-
      +-
      +-
      +- +-
      +-
      +-
        +-
      • _
        • +-
      • a
        • +-
      • b
        • +-
      • c
        • +-
      • d
        • +-
      • e
        • +-
      • f
        • +-
      • g
        • +-
      • h
        • +-
      • i
        • +-
      • k
        • +-
      • m
        • +-
      • p
        • +-
      • q
        • +-
      • r
        • +-
      • s
        • +-
      • u
        • +-
      • v
        • +-
      • w
        • +-
      +-
      +- +-

      +-  +-

      +-

      - p -

      +-
      Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.4.7
      +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_func_0x71.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/globals_func_0x71.html 2013-07-26 19:31:22.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,67 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields +- +- +- +- +-
      +-
      +-
      +-
      +-
      +- +-
      +-
      +-
        +-
      • _
        • +-
      • a
        • +-
      • b
        • +-
      • c
        • +-
      • d
        • +-
      • e
        • +-
      • f
        • +-
      • g
        • +-
      • h
        • +-
      • i
        • +-
      • k
        • +-
      • m
        • +-
      • p
        • +-
      • q
        • +-
      • r
        • +-
      • s
        • +-
      • u
        • +-
      • v
        • +-
      • w
        • +-
      +-
      +- +-

      +-  +-

      +-

      - q -

      +-
      Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.4.7
      +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_func_0x72.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/globals_func_0x72.html 2013-07-26 19:31:22.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,80 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields +- +- +- +- +-
      +-
      +-
      +-
      +-
      +- +-
      +-
      +-
        +-
      • _
        • +-
      • a
        • +-
      • b
        • +-
      • c
        • +-
      • d
        • +-
      • e
        • +-
      • f
        • +-
      • g
        • +-
      • h
        • +-
      • i
        • +-
      • k
        • +-
      • m
        • +-
      • p
        • +-
      • q
        • +-
      • r
        • +-
      • s
        • +-
      • u
        • +-
      • v
        • +-
      • w
        • +-
      +-
      +- +-

      +-  +-

      +-

      - r -

      +-
      Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.4.7
      +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_func_0x73.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/globals_func_0x73.html 2013-07-26 19:31:22.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,77 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields +- +- +- +- +-
      +-
      +-
      +-
      +-
      +- +-
      +-
      +-
        +-
      • _
        • +-
      • a
        • +-
      • b
        • +-
      • c
        • +-
      • d
        • +-
      • e
        • +-
      • f
        • +-
      • g
        • +-
      • h
        • +-
      • i
        • +-
      • k
        • +-
      • m
        • +-
      • p
        • +-
      • q
        • +-
      • r
        • +-
      • s
        • +-
      • u
        • +-
      • v
        • +-
      • w
        • +-
      +-
      +- +-

      +-  +-

      +-

      - s -

      +-
      Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.4.7
      +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_func_0x75.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/globals_func_0x75.html 2013-07-26 19:31:22.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,73 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields +- +- +- +- +-
      +-
      +-
      +-
      +-
      +- +-
      +-
      +-
        +-
      • _
        • +-
      • a
        • +-
      • b
        • +-
      • c
        • +-
      • d
        • +-
      • e
        • +-
      • f
        • +-
      • g
        • +-
      • h
        • +-
      • i
        • +-
      • k
        • +-
      • m
        • +-
      • p
        • +-
      • q
        • +-
      • r
        • +-
      • s
        • +-
      • u
        • +-
      • v
        • +-
      • w
        • +-
      +-
      +- +-

      +-  +-

      +-

      - u -

      +-
      Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.4.7
      +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_func_0x76.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/globals_func_0x76.html 2013-07-26 19:31:22.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,65 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields +- +- +- +- +-
      +-
      +-
      +-
      +-
      +- +-
      +-
      +-
        +-
      • _
        • +-
      • a
        • +-
      • b
        • +-
      • c
        • +-
      • d
        • +-
      • e
        • +-
      • f
        • +-
      • g
        • +-
      • h
        • +-
      • i
        • +-
      • k
        • +-
      • m
        • +-
      • p
        • +-
      • q
        • +-
      • r
        • +-
      • s
        • +-
      • u
        • +-
      • v
        • +-
      • w
        • +-
      +-
      +- +-

      +-  +-

      +-

      - v -

      +-
      Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.4.7
      +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_func_0x77.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/globals_func_0x77.html 2013-07-26 19:31:22.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,70 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields +- +- +- +- +-
      +-
      +-
      +-
      +-
      +- +-
      +-
      +-
        +-
      • _
        • +-
      • a
        • +-
      • b
        • +-
      • c
        • +-
      • d
        • +-
      • e
        • +-
      • f
        • +-
      • g
        • +-
      • h
        • +-
      • i
        • +-
      • k
        • +-
      • m
        • +-
      • p
        • +-
      • q
        • +-
      • r
        • +-
      • s
        • +-
      • u
        • +-
      • v
        • +-
      • w
        • +-
      +-
      +- +-

      +-  +-

      +-

      - w -

      +-
      Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.4.7
      +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_type.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/globals_type.html 2013-07-26 19:31:22.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_type.html 2013-07-26 19:34:43.000000000 +0000 +@@ -1,175 +1,132 @@ + + +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Globals - Typedefs + +- + +- +-
      +-
      +-
      +-
      +-
      +- +-
      +-
      +-
        +-
      • c
        • +-
      • d
        • +-
      • e
        • +-
      • f
        • +-
      • g
        • +-
      • h
        • +-
      • i
        • +-
      • p
        • +-
      • r
        • +-
      • t
        • +-
      +-
      ++ ++
      Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
      ++
      All | Functions | Variables | Typedefs | Enumerations | Enumeration values | Defines
      ++
      a | c | d | e | f | g | h | i | p | x
      + +

      +-  ++ +

      ++

      - a -

      +

      - c -

      ++
    • cfi_ops_t ++: dwc_otg_cfi.h +

      - d -

      ++: dwc_otg_regs.h
    • dcfg_data_t ++: dwc_otg_regs.h
    • dctl_data_t ++: dwc_otg_regs.h
    • depctl_data_t ++: dwc_otg_regs.h
    • deptsiz0_data_t ++: dwc_otg_regs.h
    • deptsiz_data_t ++: dwc_otg_regs.h
    • dev_dma_desc_sts_t ++: dwc_otg_regs.h
    • device_grxsts_data_t ++: dwc_otg_regs.h
    • diepint_data_t ++: dwc_otg_regs.h
    • diepmsk_data_t ++: dwc_otg_regs.h
    • doepint_data_t ++: dwc_otg_regs.h
    • doepmsk_data_t ++: dwc_otg_regs.h
    • dsts_data_t ++: dwc_otg_regs.h
    • dthrctl_data_t ++: dwc_otg_regs.h
    • dtknq1_data_t ++: dwc_otg_regs.h
    • dtxfsts_data_t ++: dwc_otg_regs.h
    • dwc_completion_cb_t ++: dwc_otg_pcd_if.h
    • dwc_connect_cb_t ++: dwc_otg_pcd_if.h
    • dwc_disconnect_cb_t ++: dwc_otg_pcd_if.h
    • dwc_ep_t ++: dwc_otg_cil.h
    • dwc_hc_t ++: dwc_otg_cil.h
    • dwc_hnp_params_changed_cb_t ++: dwc_otg_pcd_if.h
    • dwc_isoc_completion_cb_t ++: dwc_otg_pcd_if.h
    • dwc_otg_cil_callbacks_t ++: dwc_otg_cil.h
    • dwc_otg_control_phase_e ++: dwc_otg_hcd.h
    • dwc_otg_core_global_regs_t ++: dwc_otg_regs.h
    • dwc_otg_core_params_t ++: dwc_otg_cil.h
    • dwc_otg_dev_dma_desc_t ++: dwc_otg_regs.h
    • dwc_otg_dev_if_t ++: dwc_otg_regs.h
    • dwc_otg_dev_in_ep_regs_t ++: dwc_otg_regs.h
    • dwc_otg_dev_out_ep_regs_t ++: dwc_otg_regs.h
    • dwc_otg_device_global_regs_t ++: dwc_otg_regs.h
    • dwc_otg_device_t ++: dwc_otg_driver.h
    • dwc_otg_hc_regs_t ++: dwc_otg_regs.h
    • dwc_otg_hcd_complete_urb_cb_t ++: dwc_otg_hcd_if.h
    • dwc_otg_hcd_disconnect_cb_t ++: dwc_otg_hcd_if.h
    • dwc_otg_hcd_get_b_hnp_enable ++: dwc_otg_hcd_if.h
    • dwc_otg_hcd_hub_info_from_urb_cb_t ++: dwc_otg_hcd_if.h
    • dwc_otg_hcd_speed_from_urb_cb_t ++: dwc_otg_hcd_if.h
    • dwc_otg_hcd_start_cb_t ++: dwc_otg_hcd_if.h
    • dwc_otg_host_dma_desc_t ++: dwc_otg_regs.h
    • dwc_otg_host_global_regs_t ++: dwc_otg_regs.h
    • dwc_otg_host_if_t ++: dwc_otg_regs.h
    • dwc_otg_pcd_ep_t ++: dwc_otg_pcd.h
    • dwc_otg_pcd_iso_request_t ++: dwc_otg_pcd.h
    • dwc_otg_pcd_request_t ++: dwc_otg_pcd.h
    • dwc_otg_qh_t ++: dwc_otg_hcd.h
    • dwc_otg_qtd_t ++: dwc_otg_hcd.h
    • dwc_otg_transaction_type_e ++: dwc_otg_hcd.h
    • dwc_reset_cb_t ++: dwc_otg_pcd_if.h
    • dwc_resume_cb_t ++: dwc_otg_pcd_if.h
    • dwc_setup_cb_t ++: dwc_otg_pcd_if.h
    • dwc_sleep_cb_t ++: dwc_otg_pcd_if.h
    • dwc_suspend_cb_t ++: dwc_otg_pcd_if.h +

      - e -

      ++: dwc_otg_pcd.h +

      - f -

      ++: dwc_otg_regs.h +

      - g -

      ++: dwc_otg_regs.h
    • gdfifocfg_data_t ++: dwc_otg_regs.h
    • ggpio_data_t ++: dwc_otg_regs.h
    • gi2cctl_data_t ++: dwc_otg_regs.h
    • gintmsk_data_t ++: dwc_otg_regs.h
    • gintsts_data_t ++: dwc_otg_regs.h
    • glpmcfg_data_t ++: dwc_otg_regs.h
    • gnptxsts_data_t ++: dwc_otg_regs.h
    • gotgctl_data_t ++: dwc_otg_regs.h
    • gotgint_data_t ++: dwc_otg_regs.h
    • gpvndctl_data_t ++: dwc_otg_regs.h
    • gpwrdn_data_t ++: dwc_otg_regs.h
    • grstctl_t ++: dwc_otg_regs.h
    • gsnpsid_data_t ++: dwc_otg_regs.h
    • guid_data_t ++: dwc_otg_regs.h
    • gusbcfg_data_t ++: dwc_otg_regs.h +

      - h -

      ++: dwc_otg_regs.h
    • haintmsk_data_t ++: dwc_otg_regs.h
    • hcchar_data_t ++: dwc_otg_regs.h
    • hcdma_data_t ++: dwc_otg_regs.h
    • hcfg_data_t ++: dwc_otg_regs.h
    • hcint_data_t ++: dwc_otg_regs.h
    • hcintmsk_data_t ++: dwc_otg_regs.h
    • hctsiz_data_t ++: dwc_otg_regs.h
    • hfir_data_t ++: dwc_otg_regs.h
    • hfnum_data_t ++: dwc_otg_regs.h
    • host_dma_desc_sts_t ++: dwc_otg_regs.h
    • host_grxsts_data_t ++: dwc_otg_regs.h
    • hprt0_data_t ++: dwc_otg_regs.h
    • hwcfg1_data_t ++: dwc_otg_regs.h
    • hwcfg2_data_t ++: dwc_otg_regs.h
    • hwcfg3_data_t ++: dwc_otg_regs.h
    • hwcfg4_data_t ++: dwc_otg_regs.h +

      - i -

      ++: dwc_otg_cil.h +

      - p -

      +-

      - r -

      +-

      - t -

      +-
      Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++: dwc_otg_regs.h ++

      - x -

      ++
      Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
      ++doxygen 1.3.9.1
      + + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_vars.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/globals_vars.html 2013-07-26 19:31:22.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_vars.html 2013-07-26 19:34:43.000000000 +0000 +@@ -1,120 +1,22 @@ + + +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Globals - Variables + +- + +- +-
      +-
      +-
      +-
      +-
      +- +-
      +-
      +-
        +-
      • b
        • +-
      • d
        • +-
      • f
        • +-
      • g
        • +-
      • h
        • +-
      • p
        • +-
      • r
        • +-
      • s
        • +-
      • u
        • +-
      • w
        • +-
      +-
      ++ ++
      Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
      ++
      All | Functions | Variables | Typedefs | Enumerations | Enumeration values | Defines
      + +

      +-  +-

      +-

      - b -

      +-

      - d -

      +-

      - f -

      +-

      - g -

      ++
      Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
      ++doxygen 1.3.9.1       + + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/linux module attributes.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/linux module attributes.html 2013-07-26 19:31:22.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/linux module attributes.html 2013-07-26 19:34:43.000000000 +0000 +@@ -2,18 +2,10 @@ + + DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: + +- + +- +-
      +-
      +-The Linux module attributes feature is used to provide the Linux Diagnostic Interface.

      +-These attributes are accessed through sysfs. The diagnostic interface will provide access to the controller for bringing up the hardware and testing.

      ++ ++

      Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
      ++The Linux module attributes feature is used to provide the Linux Diagnostic Interface. These attributes are accessed through sysfs. The diagnostic interface will provide access to the controller for bringing up the hardware and testing.

      + The following table shows the attributes. + + + ++ ++ ++ ++ ++ ++ ++ ++ + + +@@ -115,16 +119,13 @@ + + +- +- + +
      Name Description Access

      +@@ -94,6 +86,18 @@ +

      		remote_wakeup On read, shows the status of Remote Wakeup. On write, initiates a remote wakeup of the host. When bit 0 is 1 and Remote Wakeup is enabled, the Remote Wakeup signalling bit in the Device Control Register is set for 1 milli-second. Read/Write

      +

      rem_wakeup_pwrdn On read, shows the status core - hibernated or not. On write, initiates a remote wakeup of the device from Hibernation. Read/Write

      ++

      mode_ch_tim_en This bit is used to enable or disable the host core to wait for 200 PHY clock cycles at the end of Resume to change the opmode signal to the PHY to 00 after Suspend or LPM. Read/Write

      ++

      fr_interval On read, shows the value of HFIR Frame Interval. On write, dynamically reload HFIR register during runtime. The application can write a value to this register only after the Port Enable bit of the Host Port Control and Status register (HPRT.PrtEnaPort) has been set Read/Write

      ++

      disconnect_us On read, shows the status of disconnect_device_us. On write, sets disconnect_us which causes soft disconnect for 100us. Applicable only for device mode of operation. Read/Write

      ++

      regdump Dumps the contents of core registers. Read

      +

      lpm_response Gets or sets lpm_response mode. Applicable only in device mode. Write

      +

      sleep_local_dev Generetates sleep signaling. Applicable only in host mode. Write

      +-

      sleep_status Shows sleep status of device. Read

      +

      +

      + Example usage: To get the current mode: cat /sys/devices/lm0/mode

      +-To power down the USB: echo 0 > /sys/devices/lm0/buspower

      Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++To power down the USB: echo 0 > /sys/devices/lm0/buspower
      Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
      ++doxygen 1.3.9.1
      + + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/main.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/main.html 2013-07-26 19:31:22.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/main.html 2013-07-26 19:34:43.000000000 +0000 +@@ -2,20 +2,13 @@ + + DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Main Page + +- + +- +-
      +-
      ++ ++
      Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
      +

      DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver Documentation

      +

      +-

      v2.90a

      Generated on Tue May 5 02:22:48 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++

      v2.94a

      Generated on Thu Oct 27 03:56:37 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
      ++doxygen 1.3.9.1
      + + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/module parameters.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/module parameters.html 2013-07-26 19:31:22.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/module parameters.html 2013-07-26 19:34:43.000000000 +0000 +@@ -2,18 +2,10 @@ + + DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: + +- + +- +-
      +-
      +-The following parameters may be specified when starting the module.

      +-These parameters define how the DWC_otg controller should be configured. Parameter values are passed to the CIL initialization function dwc_otg_cil_init

      ++ ++

      Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
      ++The following parameters may be specified when starting the module. These parameters define how the DWC_otg controller should be configured. Parameter values are passed to the CIL initialization function dwc_otg_cil_init

      + Example: modprobe dwc_otg speed=1 otg_cap=1

      + + +@@ -133,7 +125,17 @@ +

      +

      + +- ++ ++ ++ ++ +@@ -178,12 +180,52 @@ +

      + +

      ++ ++ + ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ +
      otg_en_multiple_tx_fifo Specifies whether dedicatedto tx fifos are enabled for non periodic IN EPs. The driver will automatically detect the value for this parameter if none is specified.
        ++
      		ulpi_fs_ls Specifies whether to use ULPI FS/LS mode only.
        ++
      • 0: Disabled (default)
      • 1: Enabled
      ++

      ++

      ts_dline Specifies whether term select D-Line pulsing for all PHYs is enabled.
        ++
      • 0: Disabled (default)
      • 1: Enabled
      ++

      ++

      en_multiple_tx_fifo Specifies whether dedicatedto tx fifos are enabled for non periodic IN EPs. The driver will automatically detect the value for this parameter if none is specified.
        +
      • 0: Disabled
      • 1: Enabled (default, if available)
      +

      +

      ic_usb_cap Specifies whether to enable IC_USB capability. The driver will automatically detect the value for this parameter if none is specified.
        ++
      • 0: IC_USB disabled (default, if available)
      • 1: IC_USB enable
      ++

      ++

      ahb_thr_ratio Specifies AHB Threshold ratio.
        +-
      • Values: 0 to 3 (default 0)
      ++
    • Values: 0 to 3 (default 0)
      • ++

      ++

      power_down Specifies Power Down(Hibernation) Mode. The driver will automatically detect the value for this parameter if none is specified.
        ++
      • 0: Power Down disabled (default)
      • 2: Power Down enabled
      ++

      ++

      reload_ctl Specifies whether dynamic reloading of the HFIR register is allowed during run time. The driver will automatically detect the value for this parameter if none is specified. In case the HFIR value is reloaded when HFIR.RldCtrl == 1'b0 the core might misbehave.
        ++
      • 0: Reload Control disabled (default)
      • 1: Reload Control enabled
      ++

      ++

      dev_out_nak Specifies whether Device OUT NAK enhancement enabled or no. The driver will automatically detect the value for this parameter if none is specified. This parameter is valid only when OTG_EN_DESC_DMA == 1’b1.
        ++
      • 0: The core does not set NAK after Bulk OUT transfer complete (default)
      • 1: The core sets NAK after Bulk OUT transfer complete
      ++

      ++

      cont_on_bna Specifies whether Enable Continue on BNA enabled or no. After receiving BNA interrupt the core disables the endpoint,when the endpoint is re-enabled by the application the
        ++
      • 0: Core starts processing from the DOEPDMA descriptor (default)
      • 1: Core starts processing from the descriptor which received the BNA. This parameter is valid only when OTG_EN_DESC_DMA == 1’b1.
      ++

      ++

      ahb_single This bit when programmed supports SINGLE transfers for remainder data in a transfer for DMA mode of operation.
        ++
      • 0: The remainder data will be sent using INCR burst size (default)
      • 1: The remainder data will be sent using SINGLE burst size.
      ++

      ++

      adp_enable Specifies whether ADP feature is enabled. The driver will automatically detect the value for this parameter if none is specified.
        ++
      • 0: ADP feature disabled (default)
      • 1: ADP feature enabled
      ++

      ++

      otg_ver Specifies whether OTG is performing as USB OTG Revision 2.0 or Revision 1.3 USB OTG device.
        ++
      • 0: OTG 2.0 support disabled (default)
      • 1: OTG 2.0 support enabled
      +
      +-

      Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++
      Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
      ++doxygen 1.3.9.1
      + + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/pages.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/pages.html 2013-07-26 19:31:22.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/pages.html 2013-07-26 19:34:43.000000000 +0000 +@@ -2,16 +2,9 @@ + + DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Page Index + +- + +- +-
      +-
      ++ ++
      Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
      +

      DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver Related Pages

      Here is a list of all related documentation pages: +-
      Generated on Tue May 5 02:22:50 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++
      Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
      ++doxygen 1.3.9.1
      + + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/struct__ddma__align__buffer__setup.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/struct__ddma__align__buffer__setup.html 2013-07-26 19:31:22.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/struct__ddma__align__buffer__setup.html 2013-07-26 19:34:43.000000000 +0000 +@@ -2,22 +2,10 @@ + + DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: _ddma_align_buffer_setup Struct Reference + +- + +- +-
      +-
      +-
      +-
      +-

      _ddma_align_buffer_setup Struct Reference

      Descriptor DMA Alignment Buffer setup structure. ++ ++
      Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
      ++

      _ddma_align_buffer_setup Struct Reference

      Descriptor DMA Alignment Buffer setup structure. + More... +

      + #include <dwc_otg_cfi.h> +@@ -25,11 +13,11 @@ + + + +- ++ + +- ++ + +

      Data Fields

      +-uint8_t bEndpointAddress
      ++uint8_t bEndpointAddress
      +-uint8_t bAlign
      ++uint8_t bAlign
      +

      Detailed Description

      +@@ -37,10 +25,10 @@ +

      + +

      +-Definition at line 115 of file dwc_otg_cfi.h.

      The documentation for this struct was generated from the following file:
        ++Definition at line 116 of file dwc_otg_cfi.h.
        The documentation for this struct was generated from the following file: +-
        Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++
        Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
        ++doxygen 1.3.9.1
        + + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/struct__ddma__concat__buffer__setup.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/struct__ddma__concat__buffer__setup.html 2013-07-26 19:31:22.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/struct__ddma__concat__buffer__setup.html 2013-07-26 19:34:43.000000000 +0000 +@@ -2,22 +2,10 @@ + + DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: _ddma_concat_buffer_setup Struct Reference + +- + +- +-
        +-
        +-
        +-
        +-

        _ddma_concat_buffer_setup Struct Reference

        Descriptor DMA Concatenation Buffer setup structure. ++ ++
        Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
        ++

        _ddma_concat_buffer_setup Struct Reference

        Descriptor DMA Concatenation Buffer setup structure. + More... +

        + #include <dwc_otg_cfi.h> +@@ -25,11 +13,11 @@ + + + +- ++ + +- ++ + +

        Data Fields

        +-ddma_concat_buffer_setup_hdr_t hdr
        ++ddma_concat_buffer_setup_hdr_t hdr
        +-uint16_t * wTxBytes
        ++uint16_t * wTxBytes
        +

        Detailed Description

        +@@ -37,10 +25,10 @@ +

        + +

        +-Definition at line 105 of file dwc_otg_cfi.h.

        The documentation for this struct was generated from the following file:
          ++Definition at line 106 of file dwc_otg_cfi.h.
          The documentation for this struct was generated from the following file: +-
          Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++
          Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
          ++doxygen 1.3.9.1
          + + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/struct__ddma__concat__buffer__setup__hdr.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/struct__ddma__concat__buffer__setup__hdr.html 2013-07-26 19:31:22.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/struct__ddma__concat__buffer__setup__hdr.html 2013-07-26 19:34:43.000000000 +0000 +@@ -2,22 +2,10 @@ + + DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: _ddma_concat_buffer_setup_hdr Struct Reference + +- + +- +-
          +-
          +-
          +-
          +-

          _ddma_concat_buffer_setup_hdr Struct Reference

          Descriptor DMA Concatenation Buffer setup structure. ++ ++
          Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
          ++

          _ddma_concat_buffer_setup_hdr Struct Reference

          Descriptor DMA Concatenation Buffer setup structure. + More... +

          + #include <dwc_otg_cfi.h> +@@ -25,14 +13,14 @@ + + + +- ++ + +- ++ + +- ++ + +

          Data Fields

          +-uint8_t bEndpointAddress
          ++uint8_t bEndpointAddress
          +-uint8_t bDescCount
          ++uint8_t bDescCount
          +-uint16_t wSize
          ++uint16_t wSize
          +

          Detailed Description

          +@@ -40,10 +28,10 @@ +

          + +

          +-Definition at line 93 of file dwc_otg_cfi.h.

          The documentation for this struct was generated from the following file:
            ++Definition at line 94 of file dwc_otg_cfi.h.
            The documentation for this struct was generated from the following file: +-
            Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++
            Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
            ++doxygen 1.3.9.1
            + + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/struct__ddma__sg__buffer__setup.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/struct__ddma__sg__buffer__setup.html 2013-07-26 19:31:22.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/struct__ddma__sg__buffer__setup.html 2013-07-26 19:34:43.000000000 +0000 +@@ -2,22 +2,10 @@ + + DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: _ddma_sg_buffer_setup Struct Reference + +- + +- +-
            +-
            +-
            +-
            +-

            _ddma_sg_buffer_setup Struct Reference

            Descriptor DMA SG Buffer setup structure (SG buffer). ++ ++
            Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
            ++

            _ddma_sg_buffer_setup Struct Reference

            Descriptor DMA SG Buffer setup structure (SG buffer). + More... +

            + #include <dwc_otg_cfi.h> +@@ -25,20 +13,20 @@ + + + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +

            Data Fields

            +-uint8_t bOutEndpointAddress
            ++uint8_t bOutEndpointAddress
            +-uint8_t bInEndpointAddress
            ++uint8_t bInEndpointAddress
            +-uint8_t bOffset
            ++uint8_t bOffset
            +-uint8_t bCount
            ++uint8_t bCount
            +-uint16_t wSize
            ++uint16_t wSize
            +

            Detailed Description

            +@@ -48,10 +36,10 @@ +

            + +

            +-Definition at line 77 of file dwc_otg_cfi.h.

            The documentation for this struct was generated from the following file:
              ++Definition at line 78 of file dwc_otg_cfi.h.
              The documentation for this struct was generated from the following file: +-
              Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++
              Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
              ++doxygen 1.3.9.1
              + + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/struct__rx__fifo__size__setup.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/struct__rx__fifo__size__setup.html 2013-07-26 19:31:22.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/struct__rx__fifo__size__setup.html 2013-07-26 19:34:43.000000000 +0000 +@@ -2,22 +2,10 @@ + + DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: _rx_fifo_size_setup Struct Reference + +- + +- +-
              +-
              +-
              +-
              +-

              _rx_fifo_size_setup Struct Reference

              Transmit FIFO Size setup structure. ++ ++
              Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
              ++

              _rx_fifo_size_setup Struct Reference

              Transmit FIFO Size setup structure. + More... +

              + #include <dwc_otg_cfi.h> +@@ -25,8 +13,8 @@ + + + +- ++ + +

              Data Fields

              +-uint16_t wDepth
              ++uint16_t wDepth
              +

              Detailed Description

              +@@ -34,10 +22,10 @@ +

              + +

              +-Definition at line 130 of file dwc_otg_cfi.h.

              The documentation for this struct was generated from the following file:
                ++Definition at line 131 of file dwc_otg_cfi.h.
                The documentation for this struct was generated from the following file: +-
                Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++
                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
                ++doxygen 1.3.9.1
                + + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/struct__tx__fifo__size__setup.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/struct__tx__fifo__size__setup.html 2013-07-26 19:31:22.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/struct__tx__fifo__size__setup.html 2013-07-26 19:34:43.000000000 +0000 +@@ -2,22 +2,10 @@ + + DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: _tx_fifo_size_setup Struct Reference + +- + +- +-
                +-
                +-
                +-
                +-

                _tx_fifo_size_setup Struct Reference

                Transmit FIFO Size setup structure. ++ ++
                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                ++

                _tx_fifo_size_setup Struct Reference

                Transmit FIFO Size setup structure. + More... +

                + #include <dwc_otg_cfi.h> +@@ -25,11 +13,11 @@ + + + +- ++ + +- ++ + +

                Data Fields

                +-uint8_t bEndpointAddress
                ++uint8_t bEndpointAddress
                +-uint16_t wDepth
                ++uint16_t wDepth
                +

                Detailed Description

                +@@ -37,10 +25,10 @@ +

                + +

                +-Definition at line 123 of file dwc_otg_cfi.h.

                The documentation for this struct was generated from the following file:
                  ++Definition at line 124 of file dwc_otg_cfi.h.
                  The documentation for this struct was generated from the following file: +-
                  Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++
                  Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
                  ++doxygen 1.3.9.1
                  + + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structcfi__all__features__header.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/structcfi__all__features__header.html 2013-07-26 19:31:22.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structcfi__all__features__header.html 2013-07-26 19:34:43.000000000 +0000 +@@ -2,22 +2,10 @@ + + DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: cfi_all_features_header Struct Reference + +- + +- +-
                  +-
                  +-
                  +-
                  +-

                  cfi_all_features_header Struct Reference

                  This structure is the header of the Core Features dataset returned to the Host. ++ ++
                  Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                  ++

                  cfi_all_features_header Struct Reference

                  This structure is the header of the Core Features dataset returned to the Host. + More... +

                  + #include <dwc_cfi_common.h> +@@ -25,19 +13,19 @@ + + + +- ++ + + +- ++ + +- +- ++ ++ + + +- ++ + + +

                  Data Fields

                  +-uint16_t wTotalLen
                  ++uint16_t wTotalLen
                   The total length of the features dataset returned to the Host.
                  uint16_t wVersion
                  uint16_t wVersion
                   CFI version number inBinary-Coded Decimal (i.e., 1.00 is 100H).
                  +-uint16_t wCoreID
                   CFI version number inBinary-Coded Decimal (i.e., 1.00 is 100H).
                  ++uint16_t wCoreID
                   The ID of the Core.
                  +-uint16_t wNumFeatures
                  ++uint16_t wNumFeatures
                   Number of features returned by VEN_CORE_GET_FEATURES request.
                  +@@ -47,29 +35,37 @@ + +

                  + Definition at line 69 of file dwc_cfi_common.h.

                  Field Documentation

                  +- +-
                  +-
                  +- ++

                  ++

                  ++ ++ ++ ++
                  ++ + +- ++ + +
                  uint16_t cfi_all_features_header::wVersion uint16_t cfi_all_features_header::wVersion
                  +- +-
                  ++
                  ++ ++ ++ ++ ++ ++
                  ++   ++ + +

                  + CFI version number inBinary-Coded Decimal (i.e., 1.00 is 100H). +

                  +-This field identifies the version of the CFI Specification with which the device is compliant. ++This field identifies the version of the CFI Specification with which the device is compliant. +

                  +-Definition at line 82 of file dwc_cfi_common.h. +- +-

                  ++Definition at line 82 of file dwc_cfi_common.h.

                  +
                  The documentation for this struct was generated from the following file: +-
                  Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++
                  Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
                  ++doxygen 1.3.9.1
                  + + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structcfi__dma__buff.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/structcfi__dma__buff.html 2013-07-26 19:31:22.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,41 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: cfi_dma_buff Struct Reference +- +- +- +- +-
                  +-
                  +-
                  +-
                  +-

                  cfi_dma_buff Struct Reference

                  +- +- +- +- +- +- +-

                  Data Fields

                  +-dma_addr_t addr
                  +-uint8_t * buf
                  +-

                  Detailed Description

                  +- +-

                  +- +-

                  +-Definition at line 182 of file dwc_otg_cfi.h.

                  The documentation for this struct was generated from the following file: +-
                  Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.4.7
                  +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structcfi__ep.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/structcfi__ep.html 2013-07-26 19:31:22.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structcfi__ep.html 2013-07-26 19:34:43.000000000 +0000 +@@ -2,22 +2,10 @@ + + DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: cfi_ep Struct Reference + +- + +- +-
                  +-
                  +-
                  +-
                  +-

                  cfi_ep Struct Reference

                  The CFI wrapper of the enabled and activated dwc_otg_pcd_ep structures. ++ ++
                  Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                  ++

                  cfi_ep Struct Reference

                  The CFI wrapper of the enabled and activated dwc_otg_pcd_ep structures. + More... +

                  + #include <dwc_otg_cfi.h> +@@ -25,32 +13,32 @@ + + + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +

                  Data Fields

                  +-dwc_list_link_t lh
                  ++dwc_list_link_t lh
                  +-dwc_otg_pcd_ep * ep
                  ++dwc_otg_pcd_ep * ep
                  +-dwc_otg_dma_desc * dma_desc_last
                  ++dwc_otg_dma_desc * dma_desc_last
                  +-ddma_sg_buffer_setup_t * bm_sg
                  ++ddma_sg_buffer_setup_t * bm_sg
                  +-ddma_sg_buffer_setup_t * bm_circ
                  ++ddma_sg_buffer_setup_t * bm_circ
                  +-ddma_concat_buffer_setup_t * bm_concat
                  ++ddma_concat_buffer_setup_t * bm_concat
                  +-ddma_align_buffer_setup_t * bm_align
                  ++ddma_align_buffer_setup_t * bm_align
                  +-uint32_t xfer_len
                  ++uint32_t xfer_len
                  +-uint32_t desc_count
                  ++uint32_t desc_count
                  +

                  Detailed Description

                  +@@ -60,10 +48,10 @@ +

                  + +

                  +-Definition at line 156 of file dwc_otg_cfi.h.

                  The documentation for this struct was generated from the following file:
                    ++Definition at line 157 of file dwc_otg_cfi.h.
                    The documentation for this struct was generated from the following file: +-
                    Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++
                    Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
                    ++doxygen 1.3.9.1
                    + + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structcfi__feature__desc__header.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/structcfi__feature__desc__header.html 2013-07-26 19:31:22.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structcfi__feature__desc__header.html 2013-07-26 19:34:43.000000000 +0000 +@@ -2,22 +2,10 @@ + + DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: cfi_feature_desc_header Struct Reference + +- + +- +-
                    +-
                    +-
                    +-
                    +-

                    cfi_feature_desc_header Struct Reference

                    This structure is a header of the Core Feature descriptor dataset returned to the Host after the VEN_CORE_GET_FEATURES request. ++ ++
                    Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                    ++

                    cfi_feature_desc_header Struct Reference

                    This structure is a header of the Core Feature descriptor dataset returned to the Host after the VEN_CORE_GET_FEATURES request. + More... +

                    + #include <dwc_cfi_common.h> +@@ -25,24 +13,24 @@ + + + +- ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ + + +

                    Data Fields

                    +-uint16_t wFeatureID
                    ++uint16_t wFeatureID
                     The feature ID.
                    +-uint16_t wLength
                    ++uint16_t wLength
                     Length of this feature descriptor in bytes - including the length of the feature name string.
                    +-uint16_t wDataLength
                    ++uint16_t wDataLength
                     The data length of this feature in bytes.
                    +-uint8_t bmAttributes
                    ++uint8_t bmAttributes
                     Attributes of this features D0: Access rights 0 - Read/Write 1 - Read only.
                    +-uint8_t bNameLen
                    ++uint8_t bNameLen
                     Length of the feature name in bytes.
                    +@@ -53,8 +41,8 @@ +

                    + Definition at line 99 of file dwc_cfi_common.h.

                    The documentation for this struct was generated from the following file: +-
                    Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++
                    Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
                    ++doxygen 1.3.9.1
                    + + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structcfi__ops.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/structcfi__ops.html 2013-07-26 19:31:22.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structcfi__ops.html 2013-07-26 19:34:43.000000000 +0000 +@@ -2,22 +2,10 @@ + + DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: cfi_ops Struct Reference + +- + +- +-
                    +-
                    +-
                    +-
                    +-

                    cfi_ops Struct Reference

                    This is the interface for the CFI operations. ++ ++
                    Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                    ++

                    cfi_ops Struct Reference

                    This is the interface for the CFI operations. + More... +

                    + #include <dwc_otg_cfi.h> +@@ -25,20 +13,20 @@ + + + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +

                    Data Fields

                    +-int(* ep_enable )(struct cfiobject *cfi, struct dwc_otg_pcd *pcd, struct dwc_otg_pcd_ep *ep)
                    ++int(* ep_enable )(struct cfiobject *cfi, struct dwc_otg_pcd *pcd, struct dwc_otg_pcd_ep *ep)
                    +-void *(* ep_alloc_buf )(struct cfiobject *cfi, struct dwc_otg_pcd *pcd, struct dwc_otg_pcd_ep *ep, dma_addr_t *dma, unsigned size, gfp_t flags)
                    ++void *(* ep_alloc_buf )(struct cfiobject *cfi, struct dwc_otg_pcd *pcd, struct dwc_otg_pcd_ep *ep, dma_addr_t *dma, unsigned size, gfp_t flags)
                    +-void(* release )(struct cfiobject *cfi)
                    ++void(* release )(struct cfiobject *cfi)
                    +-int(* ctrl_write_complete )(struct cfiobject *cfi, struct dwc_otg_pcd *pcd)
                    ++int(* ctrl_write_complete )(struct cfiobject *cfi, struct dwc_otg_pcd *pcd)
                    +-void(* build_descriptors )(struct cfiobject *cfi, struct dwc_otg_pcd *pcd, struct dwc_otg_pcd_ep *ep, dwc_otg_pcd_request_t *req)
                    ++void(* build_descriptors )(struct cfiobject *cfi, struct dwc_otg_pcd *pcd, struct dwc_otg_pcd_ep *ep, dwc_otg_pcd_request_t *req)
                    +

                    Detailed Description

                    +@@ -55,10 +43,10 @@ +

                    + +

                    +-Definition at line 199 of file dwc_otg_cfi.h.

                    The documentation for this struct was generated from the following file:
                      ++Definition at line 200 of file dwc_otg_cfi.h.
                      The documentation for this struct was generated from the following file: +-
                      Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++
                      Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
                      ++doxygen 1.3.9.1
                      + + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structcfi__string.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/structcfi__string.html 2013-07-26 19:31:22.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structcfi__string.html 2013-07-26 19:34:43.000000000 +0000 +@@ -2,22 +2,10 @@ + + DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: cfi_string Struct Reference + +- + +- +-
                      +-
                      +-
                      +-
                      +-

                      cfi_string Struct Reference

                      This structure describes a NULL terminated string referenced by its id field. ++ ++
                      Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                      ++

                      cfi_string Struct Reference

                      This structure describes a NULL terminated string referenced by its id field. + More... +

                      + #include <dwc_cfi_common.h> +@@ -25,11 +13,11 @@ + + + +- ++ + +- ++ + +

                      Data Fields

                      +-uint16_t id
                      ++uint16_t id
                      +-const uint8_t * s
                      ++const uint8_t * s
                      +

                      Detailed Description

                      +@@ -41,8 +29,8 @@ +

                      + Definition at line 136 of file dwc_cfi_common.h.

                      The documentation for this struct was generated from the following file: +-
                      Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++
                      Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
                      ++doxygen 1.3.9.1
                      + + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structcfi__usb__ctrlrequest.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/structcfi__usb__ctrlrequest.html 2013-07-26 19:31:22.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structcfi__usb__ctrlrequest.html 2013-07-26 19:34:43.000000000 +0000 +@@ -2,22 +2,10 @@ + + DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: cfi_usb_ctrlrequest Struct Reference + +- + +- +-
                      +-
                      +-
                      +-
                      +-

                      cfi_usb_ctrlrequest Struct Reference

                      struct cfi_usb_ctrlrequest - the CFI implementation of the struct usb_ctrlrequest This structure encapsulates the standard usb_ctrlrequest and adds a pointer to the data returned in the data stage of a 3-stage Control Write requests. ++ ++
                      Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                      ++

                      cfi_usb_ctrlrequest Struct Reference

                      struct cfi_usb_ctrlrequest - the CFI implementation of the struct usb_ctrlrequest This structure encapsulates the standard usb_ctrlrequest and adds a pointer to the data returned in the data stage of a 3-stage Control Write requests. + More... +

                      + #include <dwc_otg_cfi.h> +@@ -25,34 +13,34 @@ + + + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +

                      Data Fields

                      +-uint8_t bRequestType
                      ++uint8_t bRequestType
                      +-uint8_t bRequest
                      ++uint8_t bRequest
                      +-uint16_t wValue
                      ++uint16_t wValue
                      +-uint16_t wIndex
                      ++uint16_t wIndex
                      +-uint16_t wLength
                      ++uint16_t wLength
                      +-uint8_t * data
                      ++uint8_t * data
                      +

                      Detailed Description

                      +-struct cfi_usb_ctrlrequest - the CFI implementation of the struct usb_ctrlrequest This structure encapsulates the standard usb_ctrlrequest and adds a pointer to the data returned in the data stage of a 3-stage Control Write requests. ++struct cfi_usb_ctrlrequest - the CFI implementation of the struct usb_ctrlrequest This structure encapsulates the standard usb_ctrlrequest and adds a pointer to the data returned in the data stage of a 3-stage Control Write requests. +

                      + +

                      +-Definition at line 140 of file dwc_otg_cfi.h.

                      The documentation for this struct was generated from the following file:
                        ++Definition at line 141 of file dwc_otg_cfi.h.
                        The documentation for this struct was generated from the following file: +-
                        Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++
                        Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
                        ++doxygen 1.3.9.1
                        + + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structcfiobject.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/structcfiobject.html 2013-07-26 19:31:22.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,62 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: cfiobject Struct Reference +- +- +- +- +-
                        +-
                        +-
                        +-
                        +-

                        cfiobject Struct Reference

                        +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-

                        Data Fields

                        +-cfi_ops_t ops
                        +-dwc_otg_pcd * pcd
                        +-usb_gadget * gadget
                        +-cfi_dma_buff_t buf_in
                        +-cfi_dma_buff_t buf_out
                        +-cfi_usb_ctrlrequest ctrl_req
                        +-dwc_list_link_t active_eps
                        +-uint8_t need_gadget_att
                        +-uint8_t need_status_in_complete
                        +-

                        Detailed Description

                        +- +-

                        +- +-

                        +-Definition at line 214 of file dwc_otg_cfi.h.

                        The documentation for this struct was generated from the following file: +-
                        Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.4.7
                        +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structdwc__ep.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/structdwc__ep.html 2013-07-26 19:31:22.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structdwc__ep.html 2013-07-26 19:34:43.000000000 +0000 +@@ -2,22 +2,10 @@ + + DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_ep Struct Reference + +- + +- +-
                        +-
                        +-
                        +-
                        +-

                        dwc_ep Struct Reference

                        The dwc_ep structure represents the state of a single endpoint when acting in device mode. ++ ++
                        Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                        ++

                        dwc_ep Struct Reference

                        The dwc_ep structure represents the state of a single endpoint when acting in device mode. + More... +

                        + #include <dwc_otg_cil.h> +@@ -25,168 +13,229 @@ + + + +- ++ + + +- ++ + + +- ++ + + +- ++ + +- +- ++ ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ + + + +- ++ + +- +- ++ ++ + +- ++ + +- ++ + +- ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ + + +- ++ + +- ++ + +- ++ + +- ++ + + +- ++ + +- ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ + + +- +- +- +- ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ + + +

                        Data Fields

                        +-uint8_t num
                        ++uint8_t num
                         EP number used for register address lookup.
                        +-unsigned is_in:1
                        ++unsigned is_in:1
                         EP direction 0 = OUT.
                        +-unsigned active:1
                        ++unsigned active:1
                         EP active.
                        +-unsigned tx_fifo_num:4
                        unsigned tx_fifo_num:4
                         Periodic Tx FIFO # for IN EPs For INTR EP set to 0 to use non-periodic Tx FIFO If dedicated Tx FIFOs are enabled for all IN Eps - Tx FIFO # FOR IN EPs.
                        +-unsigned type:2
                         Periodic Tx FIFO # for IN EPs For INTR EP set to 0 to use non-periodic Tx FIFO.
                        ++unsigned type:2
                         EP type: 0 - Control, 1 - ISOC, 2 - BULK, 3 - INTR.
                        +-unsigned data_pid_start:1
                        ++unsigned data_pid_start:1
                         DATA start PID for INTR and BULK EP.
                        +-unsigned even_odd_frame:1
                        ++unsigned even_odd_frame:1
                         Frame (even/odd) for ISOC EP.
                        +-unsigned maxpacket:11
                        ++unsigned maxpacket:11
                         Max Packet bytes.
                        +-uint32_t maxxfer
                        ++uint32_t maxxfer
                         Max Transfer size.
                        Transfer state
                        +-dwc_dma_t dma_addr
                        dwc_dma_t dma_addr
                         Pointer to the beginning of the transfer buffer -- do not modify during transfer.
                        +-dwc_dma_t dma_desc_addr
                         Pointer to the beginning of the transfer buffer -- do not modify during transfer.
                        ++dwc_dma_t dma_desc_addr
                        +-dwc_otg_dev_dma_desc_t * desc_addr
                        ++dwc_otg_dev_dma_desc_t * desc_addr
                        +-uint8_t * start_xfer_buff
                        ++uint8_t * start_xfer_buff
                        +-uint8_t * xfer_buff
                        ++uint8_t * xfer_buff
                         pointer to the transfer buffer
                        +-unsigned xfer_len:19
                        ++unsigned xfer_len:19
                         Number of bytes to transfer.
                        +-unsigned xfer_count:19
                        ++unsigned xfer_count:19
                         Number of bytes transferred.
                        +-unsigned sent_zlp:1
                        ++unsigned sent_zlp:1
                         Sent ZLP.
                        +-unsigned total_len:19
                        ++unsigned total_len:19
                         Total len for control transfer.
                        +-unsigned stall_clear_flag:1
                        ++unsigned stall_clear_flag:1
                         stall clear flag
                        +-uint32_t desc_cnt
                        ++uint32_t desc_cnt
                         Allocated DMA Desc count.
                        +-dwc_dma_t dma_addr0
                        ++uint32_t bInterval
                         bInterval
                        ++uint32_t frame_num
                         Next frame num to setup next ISOC transfer.
                        ++uint8_t frm_overrun
                         Indicates SOF number overrun in DSTS.
                        ++dwc_dma_t dma_addr0
                         DMA addresses of ISOC buffers.
                        +-dwc_dma_t dma_addr1
                        ++dwc_dma_t dma_addr1
                        +-dwc_dma_t iso_dma_desc_addr
                        ++dwc_dma_t iso_dma_desc_addr
                        +-dwc_otg_dev_dma_desc_t * iso_desc_addr
                        ++dwc_otg_dev_dma_desc_t * iso_desc_addr
                        +-uint8_t * xfer_buff0
                        ++uint8_t * xfer_buff0
                         pointer to the transfer buffers
                        +-uint8_t * xfer_buff1
                        ++uint8_t * xfer_buff1
                        +-uint32_t proc_buf_num
                        ++uint32_t proc_buf_num
                         number of ISOC Buffer is processing
                        +-uint32_t buf_proc_intrvl
                        ++uint32_t buf_proc_intrvl
                         Interval of ISOC Buffer processing.
                        +-uint32_t data_per_frame
                        ++uint32_t data_per_frame
                         Data size for regular frame.
                        +-uint32_t data_pattern_frame
                        ++uint32_t data_pattern_frame
                         Data size for pattern frame.
                        +-uint32_t sync_frame
                        ++uint32_t sync_frame
                         Frame number of pattern data.
                        +-uint32_t bInterval
                         bInterval
                        +-uint32_t pkt_per_frm
                        ++uint32_t pkt_per_frm
                         ISO Packet number per frame.
                        +-uint32_t next_frame
                        ++uint32_t next_frame
                         Next frame num for which will be setup DMA Desc.
                        +-uint32_t pkt_cnt
                        ++uint32_t pkt_cnt
                         Number of packets per buffer processing.
                        +-iso_pkt_info_t * pkt_info
                        ++iso_pkt_info_t * pkt_info
                         Info for all isoc packets.
                        +-uint32_t cur_pkt
                        ++uint32_t cur_pkt
                         current pkt number
                        +-uint8_t * cur_pkt_addr
                        ++uint8_t * cur_pkt_addr
                         current pkt number
                        +-uint32_t cur_pkt_dma_addr
                        ++uint32_t cur_pkt_dma_addr
                         current pkt number
                        +

                        Detailed Description

                        +-The dwc_ep structure represents the state of a single endpoint when acting in device mode. ++The dwc_ep structure represents the state of a single endpoint when acting in device mode. +

                        + It contains the data items needed for an endpoint to be activated and transfer packets. +

                        + +

                        +-Definition at line 88 of file dwc_otg_cil.h.

                        The documentation for this struct was generated from the following file:
                          ++Definition at line 92 of file dwc_otg_cil.h.

                          Field Documentation

                          ++

                          ++ ++ ++ ++ ++
                          ++ ++ ++ ++ ++
                          unsigned dwc_ep::tx_fifo_num
                          ++
                          ++ ++ ++ ++ ++ ++
                          ++   ++ ++ ++

                          ++Periodic Tx FIFO # for IN EPs For INTR EP set to 0 to use non-periodic Tx FIFO. ++

                          ++If dedicated Tx FIFOs are enabled Tx FIFO # FOR IN EPs ++

                          ++Definition at line 103 of file dwc_otg_cil.h.

                          ++

                          ++ ++ ++ ++ ++
                          ++ ++ ++ ++ ++
                          dwc_dma_t dwc_ep::dma_addr
                          ++
                          ++ ++ ++ ++ ++ ++
                          ++   ++ ++ ++

                          ++Pointer to the beginning of the transfer buffer -- do not modify during transfer. ++

                          ++ ++

                          ++Definition at line 129 of file dwc_otg_cil.h.

                          ++

                          The documentation for this struct was generated from the following file: +-
                          Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++
                          Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
                          ++doxygen 1.3.9.1
                          + + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structdwc__hc.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/structdwc__hc.html 2013-07-26 19:31:22.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structdwc__hc.html 2013-07-26 19:34:43.000000000 +0000 +@@ -2,22 +2,10 @@ + + DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_hc Struct Reference + +- + +- +-
                          +-
                          +-
                          +-
                          +-

                          dwc_hc Struct Reference

                          Host channel descriptor. ++ ++
                          Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                          ++

                          dwc_hc Struct Reference

                          Host channel descriptor. + More... +

                          + #include <dwc_otg_cil.h> +@@ -25,128 +13,121 @@ + + + +- ++ + + + +- ++ + + +- ++ + + +- ++ + + +- ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + + +- ++ + +- +- ++ ++ + + + +- ++ + + +- ++ + +- +- ++ ++ + + +- ++ + + +- ++ + + +- ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ + +- +- ++ ++ + + +- ++ + +- +- ++ ++ + +- ++ + +- ++ + + +- ++ + + +- ++ + + +

                          Public Member Functions

                          +- DWC_CIRCLEQ_ENTRY (dwc_hc) hc_list_entry
                          ++ DWC_CIRCLEQ_ENTRY (dwc_hc) hc_list_entry
                           Entry in list of host channels.

                          Data Fields

                          +-uint8_t hc_num
                          ++uint8_t hc_num
                           Host channel number used for register address lookup.
                          +-unsigned dev_addr:7
                          ++unsigned dev_addr:7
                           Device to access.
                          +-unsigned ep_num:4
                          ++unsigned ep_num:4
                           EP to access.
                          unsigned ep_is_in:1
                          unsigned ep_is_in:1
                           EP direction.
                          unsigned speed:2
                           EP direction.
                          unsigned speed:2
                           EP speed.
                          unsigned ep_type:2
                           EP speed.
                          unsigned ep_type:2
                           Endpoint type.
                          +-unsigned max_packet:11
                           Endpoint type.
                          ++unsigned max_packet:11
                           Max packet size in bytes.
                          unsigned data_pid_start:2
                          unsigned data_pid_start:2
                           PID for initial transaction.
                          +-unsigned multi_count:2
                           PID for initial transaction.
                          ++unsigned multi_count:2
                           Number of periodic transactions per (micro)frame.
                          Transfer State
                          +-uint8_t * xfer_buff
                          ++uint8_t * xfer_buff
                           Pointer to the current transfer buffer position.
                          +-dwc_dma_t align_buff
                          dwc_dma_t align_buff
                           In Buffer DMA mode this buffer will be used if xfer_buff is not DWORD aligned.
                          +-uint32_t xfer_len
                           In Buffer DMA mode this buffer will be used if xfer_buff is not DWORD aligned.
                          ++uint32_t xfer_len
                           Total number of bytes to transfer.
                          +-uint32_t xfer_count
                          ++uint32_t xfer_count
                           Number of bytes transferred so far.
                          +-uint16_t start_pkt_count
                          ++uint16_t start_pkt_count
                           Packet count at start of transfer.
                          uint8_t xfer_started
                          uint8_t xfer_started
                           Flag to indicate whether the transfer has been started.
                          uint8_t do_ping
                           Flag to indicate whether the transfer has been started.
                          uint8_t do_ping
                           Set to 1 to indicate that a PING request should be issued on this channel.
                          uint8_t error_state
                           Set to 1 to indicate that a PING request should be issued on this channel.
                          uint8_t error_state
                           Set to 1 to indicate that the error count for this transaction is non-zero.
                          uint8_t halt_on_queue
                           Set to 1 to indicate that the error count for this transaction is non-zero.
                          uint8_t halt_on_queue
                           Set to 1 to indicate that this channel should be halted the next time a request is queued for the channel.
                          uint8_t halt_pending
                           Set to 1 to indicate that this channel should be halted the next time a request is queued for the channel.
                          uint8_t halt_pending
                           Set to 1 if the host channel has been halted, but the core is not finished flushing queued requests.
                          +-dwc_otg_halt_status_e halt_status
                           Set to 1 if the host channel has been halted, but the core is not finished flushing queued requests.
                          dwc_otg_halt_status_e halt_status
                           Reason for halting the host channel.
                          +-uint8_t do_split
                           Reason for halting the host channel.
                          ++uint8_t do_split
                           Enable split for the channel.
                          +-uint8_t complete_split
                          ++uint8_t complete_split
                           Enable complete split.
                          +-uint8_t hub_addr
                          ++uint8_t hub_addr
                           Address of high speed hub.
                          +-uint8_t port_addr
                          ++uint8_t port_addr
                           Port of the low/full speed device.
                          +-uint8_t xact_pos
                          uint8_t xact_pos
                           Split transaction position One of the following values:
                            +-
                          • DWC_HCSPLIT_XACTPOS_MID
                          • DWC_HCSPLIT_XACTPOS_BEGIN
                          • DWC_HCSPLIT_XACTPOS_END
                          • DWC_HCSPLIT_XACTPOS_ALL.
                          +-
                          +-uint8_t short_read
                           Split transaction position One of the following values: DWC_HCSPLIT_XACTPOS_MID DWC_HCSPLIT_XACTPOS_BEGIN DWC_HCSPLIT_XACTPOS_END DWC_HCSPLIT_XACTPOS_ALL.
                          ++uint8_t short_read
                           Set when the host channel does a short read.
                          +-uint8_t requests
                          uint8_t requests
                           Number of requests issued for this channel since it was assigned to the current transfer (not counting PINGs).
                          +-dwc_otg_qh * qh
                           Number of requests issued for this channel since it was assigned to the current transfer (not counting PINGs).
                          dwc_otg_qh * qh
                           Queue Head for the transfer being processed by this channel.
                           Queue Head for the transfer being processed by this channel.
                          Descriptor DMA support
                          +-uint16_t ntd
                          ++uint16_t ntd
                           Number of Transfer Descriptors.
                          +-dwc_dma_t desc_list_addr
                          ++dwc_dma_t desc_list_addr
                           Descriptor List DMA address.
                          +-uint8_t schinfo
                          ++uint8_t schinfo
                           Scheduling micro-frame bitmap.
                          +@@ -157,78 +138,110 @@ +

                          + +

                          +-Definition at line 237 of file dwc_otg_cil.h.

                          Field Documentation

                          +- +-
                          +-
                          +- ++Definition at line 260 of file dwc_otg_cil.h.

                          Field Documentation

                          ++

                          ++

                          ++ ++ ++ ++
                          ++ + +- ++ + +
                          unsigned dwc_hc::ep_is_in unsigned dwc_hc::ep_is_in
                          +- +-
                          ++
                          ++ ++ ++ ++
                          ++   ++ + +

                          + EP direction. +

                          + 0: OUT, 1: IN +

                          +-Definition at line 248 of file dwc_otg_cil.h. +- +-

                          +- +-

                          +-
                          +- ++Definition at line 271 of file dwc_otg_cil.h. ++ ++
                          ++

                          ++ ++ ++ ++ ++
                          ++ + +- ++ + +
                          unsigned dwc_hc::speed unsigned dwc_hc::speed
                          +- +-
                          ++
                          ++ ++ ++ ++
                          ++   ++ + +

                          + EP speed. +

                          + One of the following values:

                            +-
                          • DWC_OTG_EP_SPEED_LOW
                          • DWC_OTG_EP_SPEED_FULL
                          • DWC_OTG_EP_SPEED_HIGH
                          ++
                        • DWC_OTG_EP_SPEED_LOW
                        • DWC_OTG_EP_SPEED_FULL
                        • DWC_OTG_EP_SPEED_HIGH
                          • + +

                          +-Definition at line 257 of file dwc_otg_cil.h. +- +-

                          +- +-

                          +-
                          +- ++Definition at line 280 of file dwc_otg_cil.h. ++ ++
                          ++

                          ++ ++ ++ ++ ++
                          ++ + +- ++ + +
                          unsigned dwc_hc::ep_type unsigned dwc_hc::ep_type
                          +- +-
                          ++
                          ++ ++ ++ ++
                          ++   ++ + +

                          + Endpoint type. +

                          + One of the following values:

                            +-
                          • DWC_OTG_EP_TYPE_CONTROL: 0
                          • DWC_OTG_EP_TYPE_ISOC: 1
                          • DWC_OTG_EP_TYPE_BULK: 2
                          • DWC_OTG_EP_TYPE_INTR: 3
                          ++
                        • DWC_OTG_EP_TYPE_CONTROL: 0
                        • DWC_OTG_EP_TYPE_ISOC: 1
                        • DWC_OTG_EP_TYPE_BULK: 2
                        • DWC_OTG_EP_TYPE_INTR: 3
                          • + +

                          +-Definition at line 270 of file dwc_otg_cil.h. +- +-

                          +- +-

                          +-
                          +- ++Definition at line 293 of file dwc_otg_cil.h. ++ ++
                          ++

                          ++ ++ ++ ++ ++
                          ++ + +- ++ + +
                          unsigned dwc_hc::data_pid_start unsigned dwc_hc::data_pid_start
                          +- +-
                          ++
                          ++ ++ ++ ++ ++ ++
                          ++   ++ + +

                          + PID for initial transaction. +@@ -236,110 +249,287 @@ + 0: DATA0,
                          + 1: DATA2,
                          + 2: DATA1,
                          +- 3: MDATA (non-Control EP), SETUP (Control EP) ++ 3: MDATA (non-Control EP), SETUP (Control EP) ++

                          ++Definition at line 306 of file dwc_otg_cil.h.

                          ++

                          ++ ++ ++ ++ ++
                          ++ ++ ++ ++ ++
                          dwc_dma_t dwc_hc::align_buff
                          ++
                          ++ ++ ++ ++
                          ++   ++ ++ ++

                          ++In Buffer DMA mode this buffer will be used if xfer_buff is not DWORD aligned. ++

                          ++ +

                          +-Definition at line 283 of file dwc_otg_cil.h. +- +-

                          +- +-

                          +-
                          +- ++Definition at line 325 of file dwc_otg_cil.h. ++ ++
                          ++

                          ++ ++ ++ ++ ++
                          ++ + +- ++ + +
                          uint8_t dwc_hc::xfer_started uint8_t dwc_hc::xfer_started
                          +- +-
                          ++
                          ++ ++ ++ ++
                          ++   ++ + +

                          + Flag to indicate whether the transfer has been started. +

                          +-Set to 1 if it has been started, 0 otherwise. ++Set to 1 if it has been started, 0 otherwise. +

                          +-Definition at line 314 of file dwc_otg_cil.h. +- +-

                          +- +-

                          +-
                          +- ++Definition at line 337 of file dwc_otg_cil.h. ++ ++
                          ++

                          ++ ++ ++ ++ ++
                          ++ + +- ++ + +
                          uint8_t dwc_hc::do_ping uint8_t dwc_hc::do_ping
                          +- +-
                          ++
                          ++ ++ ++ ++
                          ++   ++ + +

                          + Set to 1 to indicate that a PING request should be issued on this channel. +

                          +-If 0, process normally. ++If 0, process normally. +

                          +-Definition at line 320 of file dwc_otg_cil.h. +- +-

                          +- +-

                          +-
                          +- ++Definition at line 343 of file dwc_otg_cil.h. ++ ++
                          ++

                          ++ ++ ++ ++ ++
                          ++ + +- ++ + +
                          uint8_t dwc_hc::error_state uint8_t dwc_hc::error_state
                          +- +-
                          ++
                          ++ ++ ++ ++
                          ++   ++ + +

                          + Set to 1 to indicate that the error count for this transaction is non-zero. +

                          +-Set to 0 if the error count is 0. ++Set to 0 if the error count is 0. +

                          +-Definition at line 326 of file dwc_otg_cil.h. +- +-

                          +- +-

                          +-
                          +- ++Definition at line 349 of file dwc_otg_cil.h. ++ ++
                          ++

                          ++ ++ ++ ++ ++
                          ++ + +- ++ + +
                          uint8_t dwc_hc::halt_on_queue uint8_t dwc_hc::halt_on_queue
                          +- +-
                          ++
                          ++ ++ ++ ++
                          ++   ++ + +

                          + Set to 1 to indicate that this channel should be halted the next time a request is queued for the channel. +

                          +-This is necessary in slave mode if no request queue space is available when an attempt is made to halt the channel. ++This is necessary in slave mode if no request queue space is available when an attempt is made to halt the channel. +

                          +-Definition at line 334 of file dwc_otg_cil.h. +- +-

                          +- +-

                          +-
                          +- ++Definition at line 357 of file dwc_otg_cil.h. ++ ++
                          ++

                          ++ ++ ++ ++ ++
                          ++ + +- ++ + +
                          uint8_t dwc_hc::halt_pending uint8_t dwc_hc::halt_pending
                          +- +-
                          ++
                          ++ ++ ++ ++ ++ ++
                          ++   ++ + +

                          + Set to 1 if the host channel has been halted, but the core is not finished flushing queued requests. +

                          +-Otherwise 0. ++Otherwise 0. ++

                          ++Definition at line 363 of file dwc_otg_cil.h.

                          ++

                          ++ ++ ++ ++ ++
                          ++ ++ ++ ++ ++
                          dwc_otg_halt_status_e dwc_hc::halt_status
                          ++
                          ++ ++ ++ ++ ++ ++
                          ++   ++ ++ ++

                          ++Reason for halting the host channel. ++

                          ++ ++

                          ++Definition at line 368 of file dwc_otg_cil.h.

                          ++

                          ++ ++ ++ ++ ++
                          ++ ++ ++ ++ ++
                          uint8_t dwc_hc::xact_pos
                          ++
                          ++ ++ ++ ++ ++ ++
                          ++   ++ ++ ++

                          ++Split transaction position One of the following values: DWC_HCSPLIT_XACTPOS_MID DWC_HCSPLIT_XACTPOS_BEGIN DWC_HCSPLIT_XACTPOS_END DWC_HCSPLIT_XACTPOS_ALL. ++

                          ++

                            ++
                          • * - * - * -
                          ++ ++

                          ++Definition at line 384 of file dwc_otg_cil.h.

                          ++

                          ++ ++ ++ ++ ++
                          ++ ++ ++ ++ ++
                          uint8_t dwc_hc::requests
                          ++
                          ++ ++ ++ ++ ++ ++
                          ++   ++ ++ ++

                          ++Number of requests issued for this channel since it was assigned to the current transfer (not counting PINGs). +

                          +-Definition at line 340 of file dwc_otg_cil.h. +- +-

                          ++ ++

                          ++Definition at line 393 of file dwc_otg_cil.h.

                          ++

                          ++ ++ ++ ++ ++
                          ++ ++ ++ ++ ++
                          struct dwc_otg_qh* dwc_hc::qh
                          ++
                          ++ ++ ++ ++ ++ ++
                          ++   ++ ++ ++

                          ++Queue Head for the transfer being processed by this channel. ++

                          ++ ++

                          ++Definition at line 398 of file dwc_otg_cil.h.

                          +

                          The documentation for this struct was generated from the following file: +-
                          Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++
                          Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
                          ++doxygen 1.3.9.1
                          + + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__cil__callbacks.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__cil__callbacks.html 2013-07-26 19:31:22.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__cil__callbacks.html 2013-07-26 19:34:43.000000000 +0000 +@@ -2,22 +2,10 @@ + + DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_cil_callbacks Struct Reference + +- + +- +-
                          +-
                          +-
                          +-
                          +-

                          dwc_otg_cil_callbacks Struct Reference

                          DWC_otg CIL callback structure. ++ ++
                          Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                          ++

                          dwc_otg_cil_callbacks Struct Reference

                          DWC_otg CIL callback structure. + More... +

                          + #include <dwc_otg_cil.h> +@@ -25,34 +13,34 @@ + + + +- ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ + +- ++ +

                          Data Fields

                          +-int(* start )(void *_p)
                          ++int(* start )(void *_p)
                           Start function for role change.
                          +-int(* stop )(void *_p)
                          ++int(* stop )(void *_p)
                           Stop Function for role change.
                          +-int(* disconnect )(void *_p)
                          ++int(* disconnect )(void *_p)
                           Disconnect Function for role change.
                          +-int(* resume_wakeup )(void *_p)
                          ++int(* resume_wakeup )(void *_p)
                           Resume/Remote wakeup Function.
                          +-int(* suspend )(void *_p)
                          ++int(* suspend )(void *_p)
                           Suspend function.
                          +-int(* session_start )(void *_p)
                          ++int(* session_start )(void *_p)
                           Session Start (SRP).
                          +-void * p
                          ++void * p
                           Pointer passed to start() and stop().
                           Pointer passed to start() and stop().
                          +

                          Detailed Description

                          + DWC_otg CIL callback structure. +@@ -61,10 +49,10 @@ +

                          + +

                          +-Definition at line 1109 of file dwc_otg_cil.h.

                          The documentation for this struct was generated from the following file:
                            ++Definition at line 1307 of file dwc_otg_cil.h.
                            The documentation for this struct was generated from the following file: +-
                            Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++
                            Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
                            ++doxygen 1.3.9.1
                            + + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__core__global__regs.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__core__global__regs.html 2013-07-26 19:31:22.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__core__global__regs.html 2013-07-26 19:34:43.000000000 +0000 +@@ -2,22 +2,10 @@ + + DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_core_global_regs Struct Reference + +- + +- +-
                            +-
                            +-
                            +-
                            +-

                            dwc_otg_core_global_regs Struct Reference

                            DWC_otg Core registers . ++ ++
                            Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                            ++

                            dwc_otg_core_global_regs Struct Reference

                            DWC_otg Core registers . + More... +

                            + #include <dwc_otg_regs.h> +@@ -25,533 +13,729 @@ + + + +- ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ +

                            Data Fields

                            volatile uint32_t gotgctl
                            volatile uint32_t gotgctl
                             OTG Control and Status Register.
                            volatile uint32_t gotgint
                             OTG Control and Status Register.
                            volatile uint32_t gotgint
                             OTG Interrupt Register.
                            volatile uint32_t gahbcfg
                             OTG Interrupt Register.
                            volatile uint32_t gahbcfg
                             Core AHB Configuration Register.
                            volatile uint32_t gusbcfg
                             Core AHB Configuration Register.
                            volatile uint32_t gusbcfg
                             Core USB Configuration Register.
                            volatile uint32_t grstctl
                             Core USB Configuration Register.
                            volatile uint32_t grstctl
                             Core Reset Register.
                            volatile uint32_t gintsts
                             Core Reset Register.
                            volatile uint32_t gintsts
                             Core Interrupt Register.
                            volatile uint32_t gintmsk
                             Core Interrupt Register.
                            volatile uint32_t gintmsk
                             Core Interrupt Mask Register.
                            volatile uint32_t grxstsr
                             Core Interrupt Mask Register.
                            volatile uint32_t grxstsr
                             Receive Status Queue Read Register (Read Only).
                            volatile uint32_t grxstsp
                             Receive Status Queue Read Register (Read Only).
                            volatile uint32_t grxstsp
                             Receive Status Queue Read & POP Register (Read Only).
                            volatile uint32_t grxfsiz
                             Receive Status Queue Read & POP Register (Read Only).
                            volatile uint32_t grxfsiz
                             Receive FIFO Size Register.
                            volatile uint32_t gnptxfsiz
                             Receive FIFO Size Register.
                            volatile uint32_t gnptxfsiz
                             Non Periodic Transmit FIFO Size Register.
                            volatile uint32_t gnptxsts
                             Non Periodic Transmit FIFO Size Register.
                            volatile uint32_t gnptxsts
                             Non Periodic Transmit FIFO/Queue Status Register (Read Only).
                            volatile uint32_t gi2cctl
                             Non Periodic Transmit FIFO/Queue Status Register (Read Only).
                            volatile uint32_t gi2cctl
                             I2C Access Register.
                            volatile uint32_t gpvndctl
                             I2C Access Register.
                            volatile uint32_t gpvndctl
                             PHY Vendor Control Register.
                            volatile uint32_t ggpio
                             PHY Vendor Control Register.
                            volatile uint32_t ggpio
                             General Purpose Input/Output Register.
                            volatile uint32_t guid
                             General Purpose Input/Output Register.
                            volatile uint32_t guid
                             User ID Register.
                            volatile uint32_t gsnpsid
                             User ID Register.
                            volatile uint32_t gsnpsid
                             Synopsys ID Register (Read Only).
                            volatile uint32_t ghwcfg1
                             Synopsys ID Register (Read Only).
                            volatile uint32_t ghwcfg1
                             User HW Config1 Register (Read Only).
                            volatile uint32_t ghwcfg2
                             User HW Config1 Register (Read Only).
                            volatile uint32_t ghwcfg2
                             User HW Config2 Register (Read Only).
                            volatile uint32_t ghwcfg3
                             User HW Config2 Register (Read Only).
                            volatile uint32_t ghwcfg3
                             User HW Config3 Register (Read Only).
                            volatile uint32_t ghwcfg4
                             User HW Config3 Register (Read Only).
                            volatile uint32_t ghwcfg4
                             User HW Config4 Register (Read Only).
                            +-volatile uint32_t glpmcfg
                             User HW Config4 Register (Read Only).
                            ++volatile uint32_t glpmcfg
                             Core LPM Configuration register.
                            +-volatile uint32_t reserved [42]
                             Core LPM Configuration register Offset: 054h.
                            ++volatile uint32_t gpwrdn
                             Reserved Offset: 058h-0FFh.
                            volatile uint32_t hptxfsiz
                             Global PowerDn Register Offset: 058h.
                            ++volatile uint32_t gdfifocfg
                             Host Periodic Transmit FIFO Size Register.
                            volatile uint32_t dptxfsiz_dieptxf [15]
                             Global DFIFO SW Config Register Offset: 05Ch.
                            ++volatile uint32_t adpctl
                             Device Periodic Transmit FIFO::n Register if dedicated fifos are disabled, otherwise Device Transmit FIFO::n Register.
                             ADP Control Register Offset: 060h.
                            ++volatile uint32_t reserved39 [39]
                             Reserved Offset: 064h-0FFh.
                            volatile uint32_t hptxfsiz
                             Host Periodic Transmit FIFO Size Register.
                            volatile uint32_t dtxfsiz [15]
                             Device Periodic Transmit FIFO#n Register if dedicated fifos are disabled, otherwise Device Transmit FIFO#n Register.
                            +

                            Detailed Description

                            + DWC_otg Core registers . +

                            +-The dwc_otg_core_global_regs structure defines the size and relative field offsets for the Core Global registers. ++The dwc_otg_core_global_regs structure defines the size and relative field offsets for the Core Global registers. +

                            + +

                            + Definition at line 71 of file dwc_otg_regs.h.

                            Field Documentation

                            +- +-
                            +-
                            +- ++

                            ++

                            ++ ++ ++ ++
                            ++ + +- ++ + +
                            volatile uint32_t dwc_otg_core_global_regs::gotgctl volatile uint32_t dwc_otg_core_global_regs::gotgctl
                            +- +-
                            ++
                            ++ ++ ++ ++
                            ++   ++ + +

                            + OTG Control and Status Register. +

                            + Offset: 000h +

                            +-Definition at line 73 of file dwc_otg_regs.h. +- +-

                            +- +-

                            +-
                            +- ++Definition at line 73 of file dwc_otg_regs.h. ++ ++
                            ++

                            ++ ++ ++ ++ ++
                            ++ + +- ++ + +
                            volatile uint32_t dwc_otg_core_global_regs::gotgint volatile uint32_t dwc_otg_core_global_regs::gotgint
                            +- +-
                            ++
                            ++ ++ ++ ++
                            ++   ++ + +

                            + OTG Interrupt Register. +

                            + Offset: 004h +

                            +-Definition at line 75 of file dwc_otg_regs.h. +- +-

                            +- +-

                            +-
                            +- ++Definition at line 75 of file dwc_otg_regs.h. ++ ++
                            ++

                            ++ ++ ++ ++ ++
                            ++ + +- ++ + +
                            volatile uint32_t dwc_otg_core_global_regs::gahbcfg volatile uint32_t dwc_otg_core_global_regs::gahbcfg
                            +- +-
                            ++
                            ++ ++ ++ ++
                            ++   ++ + +

                            + Core AHB Configuration Register. +

                            + Offset: 008h +

                            +-Definition at line 77 of file dwc_otg_regs.h. +- +-

                            +- +-

                            +-
                            +- ++Definition at line 77 of file dwc_otg_regs.h. ++ ++
                            ++

                            ++ ++ ++ ++ ++
                            ++ + +- ++ + +
                            volatile uint32_t dwc_otg_core_global_regs::gusbcfg volatile uint32_t dwc_otg_core_global_regs::gusbcfg
                            +- +-
                            ++
                            ++ ++ ++ ++
                            ++   ++ + +

                            + Core USB Configuration Register. +

                            + Offset: 00Ch +

                            +-Definition at line 87 of file dwc_otg_regs.h. +- +-

                            +- +-

                            +-
                            +- ++Definition at line 87 of file dwc_otg_regs.h. ++ ++
                            ++

                            ++ ++ ++ ++ ++
                            ++ + +- ++ + +
                            volatile uint32_t dwc_otg_core_global_regs::grstctl volatile uint32_t dwc_otg_core_global_regs::grstctl
                            +- +-
                            ++
                            ++ ++ ++ ++
                            ++   ++ + +

                            + Core Reset Register. +

                            + Offset: 010h +

                            +-Definition at line 89 of file dwc_otg_regs.h. +- +-

                            +- +-

                            +-
                            +- ++Definition at line 89 of file dwc_otg_regs.h. ++ ++
                            ++

                            ++ ++ ++ ++ ++
                            ++ + +- ++ + +
                            volatile uint32_t dwc_otg_core_global_regs::gintsts volatile uint32_t dwc_otg_core_global_regs::gintsts
                            +- +-
                            ++
                            ++ ++ ++ ++
                            ++   ++ + +

                            + Core Interrupt Register. +

                            + Offset: 014h +

                            +-Definition at line 91 of file dwc_otg_regs.h. +- +-

                            +- +-

                            +-
                            +- ++Definition at line 91 of file dwc_otg_regs.h. ++ ++
                            ++

                            ++ ++ ++ ++ ++
                            ++ + +- ++ + +
                            volatile uint32_t dwc_otg_core_global_regs::gintmsk volatile uint32_t dwc_otg_core_global_regs::gintmsk
                            +- +-
                            ++
                            ++ ++ ++ ++
                            ++   ++ + +

                            + Core Interrupt Mask Register. +

                            + Offset: 018h +

                            +-Definition at line 93 of file dwc_otg_regs.h. +- +-

                            +- +-

                            +-
                            +- ++Definition at line 93 of file dwc_otg_regs.h. ++ ++
                            ++

                            ++ ++ ++ ++ ++
                            ++ + +- ++ + +
                            volatile uint32_t dwc_otg_core_global_regs::grxstsr volatile uint32_t dwc_otg_core_global_regs::grxstsr
                            +- +-
                            ++
                            ++ ++ ++ ++
                            ++   ++ + +

                            + Receive Status Queue Read Register (Read Only). +

                            + Offset: 01Ch +

                            +-Definition at line 95 of file dwc_otg_regs.h. +- +-

                            +- +-

                            +-
                            +- ++Definition at line 95 of file dwc_otg_regs.h. ++ ++
                            ++

                            ++ ++ ++ ++ ++
                            ++ + +- ++ + +
                            volatile uint32_t dwc_otg_core_global_regs::grxstsp volatile uint32_t dwc_otg_core_global_regs::grxstsp
                            +- +-
                            ++
                            ++ ++ ++ ++
                            ++   ++ + +

                            + Receive Status Queue Read & POP Register (Read Only). +

                            + Offset: 020h +

                            +-Definition at line 97 of file dwc_otg_regs.h. +- +-

                            +- +-

                            +-
                            +- ++Definition at line 97 of file dwc_otg_regs.h. ++ ++
                            ++

                            ++ ++ ++ ++ ++
                            ++ + +- ++ + +
                            volatile uint32_t dwc_otg_core_global_regs::grxfsiz volatile uint32_t dwc_otg_core_global_regs::grxfsiz
                            +- +-
                            ++
                            ++ ++ ++ ++
                            ++   ++ + +

                            + Receive FIFO Size Register. +

                            + Offset: 024h +

                            +-Definition at line 99 of file dwc_otg_regs.h. +- +-

                            +- +-

                            +-
                            +- ++Definition at line 99 of file dwc_otg_regs.h. ++ ++
                            ++

                            ++ ++ ++ ++ ++
                            ++ + +- ++ + +
                            volatile uint32_t dwc_otg_core_global_regs::gnptxfsiz volatile uint32_t dwc_otg_core_global_regs::gnptxfsiz
                            +- +-
                            ++
                            ++ ++ ++ ++
                            ++   ++ + +

                            + Non Periodic Transmit FIFO Size Register. +

                            + Offset: 028h +

                            +-Definition at line 101 of file dwc_otg_regs.h. +- +-

                            +- +-

                            +-
                            +- ++Definition at line 101 of file dwc_otg_regs.h. ++ ++
                            ++

                            ++ ++ ++ ++ ++
                            ++ + +- ++ + +
                            volatile uint32_t dwc_otg_core_global_regs::gnptxsts volatile uint32_t dwc_otg_core_global_regs::gnptxsts
                            +- +-
                            ++
                            ++ ++ ++ ++
                            ++   ++ + +

                            + Non Periodic Transmit FIFO/Queue Status Register (Read Only). +

                            + Offset: 02Ch +

                            +-Definition at line 104 of file dwc_otg_regs.h. +- +-

                            +- +-

                            +-
                            +- ++Definition at line 104 of file dwc_otg_regs.h. ++ ++
                            ++

                            ++ ++ ++ ++ ++
                            ++ + +- ++ + +
                            volatile uint32_t dwc_otg_core_global_regs::gi2cctl volatile uint32_t dwc_otg_core_global_regs::gi2cctl
                            +- +-
                            ++
                            ++ ++ ++ ++
                            ++   ++ + +

                            + I2C Access Register. +

                            + Offset: 030h +

                            +-Definition at line 106 of file dwc_otg_regs.h. +- +-

                            +- +-

                            +-
                            +- ++Definition at line 106 of file dwc_otg_regs.h. ++ ++
                            ++

                            ++ ++ ++ ++ ++
                            ++ + +- ++ + +
                            volatile uint32_t dwc_otg_core_global_regs::gpvndctl volatile uint32_t dwc_otg_core_global_regs::gpvndctl
                            +- +-
                            ++
                            ++ ++ ++ ++
                            ++   ++ + +

                            + PHY Vendor Control Register. +

                            + Offset: 034h +

                            +-Definition at line 108 of file dwc_otg_regs.h. +- +-

                            +- +-

                            +-
                            +- ++Definition at line 108 of file dwc_otg_regs.h. ++ ++
                            ++

                            ++ ++ ++ ++ ++
                            ++ + +- ++ + +
                            volatile uint32_t dwc_otg_core_global_regs::ggpio volatile uint32_t dwc_otg_core_global_regs::ggpio
                            +- +-
                            ++
                            ++ ++ ++ ++
                            ++   ++ + +

                            + General Purpose Input/Output Register. +

                            + Offset: 038h +

                            +-Definition at line 110 of file dwc_otg_regs.h. +- +-

                            +- +-

                            +-
                            +- ++Definition at line 110 of file dwc_otg_regs.h. ++ ++
                            ++

                            ++ ++ ++ ++ ++
                            ++ + +- ++ + +
                            volatile uint32_t dwc_otg_core_global_regs::guid volatile uint32_t dwc_otg_core_global_regs::guid
                            +- +-
                            ++
                            ++ ++ ++ ++
                            ++   ++ + +

                            + User ID Register. +

                            + Offset: 03Ch +

                            +-Definition at line 112 of file dwc_otg_regs.h. +- +-

                            +- +-

                            +-
                            +- ++Definition at line 112 of file dwc_otg_regs.h. ++ ++
                            ++

                            ++ ++ ++ ++ ++
                            ++ + +- ++ + +
                            volatile uint32_t dwc_otg_core_global_regs::gsnpsid volatile uint32_t dwc_otg_core_global_regs::gsnpsid
                            +- +-
                            ++
                            ++ ++ ++ ++
                            ++   ++ + +

                            + Synopsys ID Register (Read Only). +

                            + Offset: 040h +

                            +-Definition at line 114 of file dwc_otg_regs.h. +- +-

                            +- +-

                            +-
                            +- ++Definition at line 114 of file dwc_otg_regs.h. ++ ++
                            ++

                            ++ ++ ++ ++ ++
                            ++ + +- ++ + +
                            volatile uint32_t dwc_otg_core_global_regs::ghwcfg1 volatile uint32_t dwc_otg_core_global_regs::ghwcfg1
                            +- +-
                            ++
                            ++ ++ ++ ++
                            ++   ++ + +

                            + User HW Config1 Register (Read Only). +

                            + Offset: 044h +

                            +-Definition at line 116 of file dwc_otg_regs.h. +- +-

                            +- +-

                            +-
                            +- ++Definition at line 116 of file dwc_otg_regs.h. ++ ++
                            ++

                            ++ ++ ++ ++ ++
                            ++ + +- ++ + +
                            volatile uint32_t dwc_otg_core_global_regs::ghwcfg2 volatile uint32_t dwc_otg_core_global_regs::ghwcfg2
                            +- +-
                            ++
                            ++ ++ ++ ++
                            ++   ++ + +

                            + User HW Config2 Register (Read Only). +

                            + Offset: 048h +

                            +-Definition at line 118 of file dwc_otg_regs.h. +- +-

                            +- +-

                            +-
                            +- ++Definition at line 118 of file dwc_otg_regs.h. ++ ++
                            ++

                            ++ ++ ++ ++ ++
                            ++ + +- ++ + +
                            volatile uint32_t dwc_otg_core_global_regs::ghwcfg3 volatile uint32_t dwc_otg_core_global_regs::ghwcfg3
                            +- +-
                            ++
                            ++ ++ ++ ++
                            ++   ++ + +

                            + User HW Config3 Register (Read Only). +

                            + Offset: 04Ch +

                            +-Definition at line 132 of file dwc_otg_regs.h. +- +-

                            +- +-

                            +-
                            +- ++Definition at line 132 of file dwc_otg_regs.h. ++ ++
                            ++

                            ++ ++ ++ ++ ++
                            ++ + +- ++ + +
                            volatile uint32_t dwc_otg_core_global_regs::ghwcfg4 volatile uint32_t dwc_otg_core_global_regs::ghwcfg4
                            +- +-
                            ++
                            ++ ++ ++ ++
                            ++   ++ + +

                            + User HW Config4 Register (Read Only). +

                            + Offset: 050h +

                            +-Definition at line 134 of file dwc_otg_regs.h. +- +-

                            +- +-

                            +-
                            +- ++Definition at line 134 of file dwc_otg_regs.h. ++ ++
                            ++

                            ++ ++ ++ ++ ++
                            ++ + +- ++ + +
                            volatile uint32_t dwc_otg_core_global_regs::hptxfsiz volatile uint32_t dwc_otg_core_global_regs::hptxfsiz
                            +- +-
                            ++
                            ++ ++ ++ ++
                            ++   ++ + +

                            + Host Periodic Transmit FIFO Size Register. +

                            + Offset: 100h +

                            +-Definition at line 140 of file dwc_otg_regs.h. +- +-

                            +- +-

                            +-
                            +- ++Definition at line 146 of file dwc_otg_regs.h. ++ ++
                            ++

                            ++ ++ ++ ++ ++
                            ++ + +- ++ + +
                            volatile uint32_t dwc_otg_core_global_regs::dptxfsiz_dieptxf[15] volatile uint32_t dwc_otg_core_global_regs::dtxfsiz[15]
                            +- +-
                            ++
                            ++ ++ ++ ++ ++ ++
                            ++   ++ + +

                            +-Device Periodic Transmit FIFO::n Register if dedicated fifos are disabled, otherwise Device Transmit FIFO::n Register. ++Device Periodic Transmit FIFO#n Register if dedicated fifos are disabled, otherwise Device Transmit FIFO#n Register. +

                            + Offset: 104h + (FIFO_Number-1)*04h, 1 <= FIFO Number <= 15 (1<=n<=15). +

                            +-Definition at line 144 of file dwc_otg_regs.h. +- +-

                            ++Definition at line 150 of file dwc_otg_regs.h.

                            +

                            The documentation for this struct was generated from the following file: +-
                            Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++
                            Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
                            ++doxygen 1.3.9.1
                            + + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__core__if.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__core__if.html 2013-07-26 19:31:22.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__core__if.html 2013-07-26 19:34:43.000000000 +0000 +@@ -2,22 +2,10 @@ + + DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_core_if Struct Reference + +- + +- +-
                            +-
                            +-
                            +-
                            +-

                            dwc_otg_core_if Struct Reference

                            The dwc_otg_core_if structure contains information needed to manage the DWC_otg controller acting in either host or device mode. ++ ++
                            Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                            ++

                            dwc_otg_core_if Struct Reference

                            The dwc_otg_core_if structure contains information needed to manage the DWC_otg controller acting in either host or device mode. + More... +

                            + #include <dwc_otg_cil.h> +@@ -25,166 +13,299 @@ + + + +- ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ + +- ++ + +- ++ + +- ++ ++ ++ ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ ++ ++ + +- ++ + +- ++ + +- ++ + + +- ++ + +- ++ + +- +- ++ ++ + +- +- ++ ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ ++ ++ ++ ++ ++ ++ ++ + + ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ +

                            Data Fields

                            +-dwc_otg_core_params_t * core_params
                            ++dwc_otg_core_params_t * core_params
                             Parameters that define how the core should be configured.
                            +-dwc_otg_core_global_regs_t * core_global_regs
                            ++dwc_otg_core_global_regs_t * core_global_regs
                             Core Global registers starting at offset 000h.
                            +-dwc_otg_dev_if_t * dev_if
                            ++dwc_otg_dev_if_t * dev_if
                             Device-specific information.
                            +-dwc_otg_host_if_t * host_if
                            ++dwc_otg_host_if_t * host_if
                             Host-specific information.
                            +-uint32_t snpsid
                            ++uint32_t snpsid
                             Value from SNPSID register.
                            +-uint8_t phy_init_done
                            ++uint8_t phy_init_done
                            +-uint8_t srp_success
                            ++uint8_t srp_success
                            +-uint8_t srp_timer_started
                            ++uint8_t srp_timer_started
                            +-volatile uint32_t * pcgcctl
                            dwc_timer_t * srp_timer
                             Timer for SRP.
                            ++volatile uint32_t * pcgcctl
                             Power and Clock Gating Control Register.
                            +-uint32_t * data_fifo [MAX_EPS_CHANNELS]
                            ++uint32_t * data_fifo [MAX_EPS_CHANNELS]
                             Push/pop addresses for endpoints or host channels.
                            +-uint16_t total_fifo_size
                            ++uint16_t total_fifo_size
                             Total RAM for FIFOs (Bytes).
                            +-uint16_t rx_fifo_size
                            ++uint16_t rx_fifo_size
                             Size of Rx FIFO (Bytes).
                            +-uint16_t nperio_tx_fifo_size
                            ++uint16_t nperio_tx_fifo_size
                             Size of Non-periodic Tx FIFO (Bytes).
                            +-uint8_t dma_enable
                            ++uint8_t dma_enable
                             1 if DMA is enabled, 0 otherwise.
                            +-uint8_t dma_desc_enable
                            ++uint8_t dma_desc_enable
                             1 if DMA descriptor is enabled, 0 otherwise.
                            +-uint8_t pti_enh_enable
                            ++uint8_t pti_enh_enable
                             1 if PTI Enhancement mode is enabled, 0 otherwise.
                            +-uint8_t multiproc_int_enable
                            ++uint8_t multiproc_int_enable
                             1 if MPI Enhancement mode is enabled, 0 otherwise.
                            +-uint8_t en_multiple_tx_fifo
                            ++uint8_t en_multiple_tx_fifo
                             1 if dedicated Tx FIFOs are enabled, 0 otherwise.
                            +-uint8_t queuing_high_bandwidth
                            ++uint8_t queuing_high_bandwidth
                             Set to 1 if multiple packets of a high-bandwidth transfer is in process of being queued.
                            +-hwcfg1_data_t hwcfg1
                            ++hwcfg1_data_t hwcfg1
                             Hardware Configuration -- stored here for convenience.
                            +-hwcfg2_data_t hwcfg2
                            ++hwcfg2_data_t hwcfg2
                            ++hwcfg3_data_t hwcfg3
                            +-hwcfg3_data_t hwcfg3
                            ++hwcfg4_data_t hwcfg4
                            +-hwcfg4_data_t hwcfg4
                            ++fifosize_data_t hptxfsiz
                            +-hcfg_data_t hcfg
                            ++hcfg_data_t hcfg
                             Host and Device Configuration -- stored here for convenience.
                            +-dcfg_data_t dcfg
                            ++dcfg_data_t dcfg
                            +-uint8_t op_state
                            uint8_t op_state
                             The operational State, during transations (a_host>>a_peripherial and b_device=>b_host) this may not match the core but allows the software to determine transitions.
                            uint8_t restart_hcd_on_session_req
                             The operational State, during transations (a_host>>a_peripherial and b_device=>b_host) this may not match the core but allows the software to determine transitions.
                            uint8_t restart_hcd_on_session_req
                             Set to 1 if the HCD needs to be restarted on a session request interrupt.
                            +-dwc_otg_cil_callbacks * hcd_cb
                             Set to 1 if the HCD needs to be restarted on a session request interrupt.
                            ++dwc_otg_cil_callbacks * hcd_cb
                             HCD callbacks.
                            +-dwc_otg_cil_callbacks * pcd_cb
                            ++dwc_otg_cil_callbacks * pcd_cb
                             PCD callbacks.
                            +-uint32_t p_tx_msk
                            ++uint32_t p_tx_msk
                             Device mode Periodic Tx FIFO Mask.
                            +-uint32_t tx_msk
                            ++uint32_t tx_msk
                             Device mode Periodic Tx FIFO Mask.
                            +-dwc_workq_t * wq_otg
                            ++dwc_workq_t * wq_otg
                             Workqueue object used for handling several interrupts.
                            +-dwc_timer_t * wkp_timer
                            ++dwc_timer_t * wkp_timer
                             Timer object used for handling "Wakeup Detected" Interrupt.
                            +-dwc_otg_lx_state_e lx_state
                            ++uint32_t start_doeptsiz_val [MAX_EPS_CHANNELS]
                             This arrays used for debug purposes for DEV OUT NAK enhancement.
                            ++ep_xfer_info_t ep_xfer_info [MAX_EPS_CHANNELS]
                            ++dwc_timer_t * ep_xfer_timer [MAX_EPS_CHANNELS]
                            ++dwc_otg_lx_state_e lx_state
                             Lx state of device.
                            ++dwc_otg_global_regs_backup * gr_backup
                             Saved Core Global registers.
                            ++dwc_otg_host_regs_backup * hr_backup
                             Saved Host registers.
                            ++dwc_otg_dev_regs_backup * dr_backup
                             Saved Device registers.
                            ++uint32_t power_down
                             Power Down Enable.
                            ++uint32_t adp_enable
                             ADP support Enable.
                            ++dwc_otg_adp_t adp
                             ADP structure object.
                            ++int hibernation_suspend
                             hibernation/suspend flag
                            ++uint32_t otg_ver
                             OTG revision supported.
                            ++uint8_t otg_sts
                             OTG status flag used for HNP polling.
                            ++dwc_spinlock_t * lock
                             Pointer to either hcd->lock or pcd->lock.
                            ++uint8_t start_predict
                             Start predict NextEP based on Learning Queue if equal 1, also used as counter of disabled NP IN EP's.
                            ++uint8_t nextep_seq [MAX_EPS_CHANNELS]
                             NextEp sequence, including EP0: nextep_seq[] = EP if non-periodic and active, 0xff otherwise.
                            ++uint8_t first_in_nextep_seq
                             Index of fisrt EP in nextep_seq array which should be re-enabled *.
                            ++uint32_t frame_num
                             Frame number while entering to ISR - needed for ISOCs *.
                            +

                            Detailed Description

                            +-The dwc_otg_core_if structure contains information needed to manage the DWC_otg controller acting in either host or device mode. ++The dwc_otg_core_if structure contains information needed to manage the DWC_otg controller acting in either host or device mode. +

                            + It represents the programming view of the controller as a whole. +

                            + +

                            +-Definition at line 680 of file dwc_otg_cil.h.

                            Field Documentation

                            +- +-
                            +-
                            +- ++Definition at line 792 of file dwc_otg_cil.h.

                            Field Documentation

                            ++

                            ++

                            ++ ++ ++ ++
                            ++ ++ ++ ++ ++
                            dwc_timer_t* dwc_otg_core_if::srp_timer
                            ++
                            ++ ++ ++ ++ ++ ++
                            ++   ++ ++ ++

                            ++Timer for SRP. ++

                            ++If it expires before SRP is successful clear the SRP. ++

                            ++Definition at line 820 of file dwc_otg_cil.h.

                            ++

                            ++ ++ ++ ++ ++
                            ++ ++ ++ ++ ++
                            uint8_t dwc_otg_core_if::op_state
                            ++
                            ++ ++ ++ ++ ++ ++
                            ++   ++ ++ ++

                            ++The operational State, during transations (a_host>>a_peripherial and b_device=>b_host) this may not match the core but allows the software to determine transitions. ++

                            ++ ++

                            ++Definition at line 881 of file dwc_otg_cil.h.

                            ++

                            ++ ++ ++ ++ ++
                            ++ + +- ++ + +
                            uint8_t dwc_otg_core_if::restart_hcd_on_session_req uint8_t dwc_otg_core_if::restart_hcd_on_session_req
                            +- +-
                            ++
                            ++ ++ ++ ++ ++ ++
                            ++   ++ + +

                            + Set to 1 if the HCD needs to be restarted on a session request interrupt. +

                            +-This is required if no connector ID status change has occurred since the HCD was last disconnected. ++This is required if no connector ID status change has occurred since the HCD was last disconnected. +

                            +-Definition at line 765 of file dwc_otg_cil.h. +- +-

                            ++Definition at line 888 of file dwc_otg_cil.h.

                            +

                            The documentation for this struct was generated from the following file: +-
                            Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++
                            Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
                            ++doxygen 1.3.9.1
                            + + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__core__params.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__core__params.html 2013-07-26 19:31:22.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__core__params.html 2013-07-26 19:34:43.000000000 +0000 +@@ -2,22 +2,10 @@ + + DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_core_params Struct Reference + +- + +- +-
                            +-
                            +-
                            +-
                            +-

                            dwc_otg_core_params Struct Reference

                            The following parameters may be specified when starting the module. ++ ++
                            Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                            ++

                            dwc_otg_core_params Struct Reference

                            The following parameters may be specified when starting the module. + More... +

                            + #include <dwc_otg_cil.h> +@@ -25,128 +13,151 @@ + + + +- ++ + +- ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + + +- ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- ++ + +- ++ + + +- ++ + +- +- ++ ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ + + ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ +

                            Data Fields

                            +-int32_t opt
                            ++int32_t opt
                            int32_t otg_cap
                            int32_t otg_cap
                             Specifies the OTG capabilities.
                            int32_t dma_enable
                             Specifies the OTG capabilities.
                            int32_t dma_enable
                             Specifies whether to use slave or DMA mode for accessing the data FIFOs.
                            int32_t dma_desc_enable
                             Specifies whether to use slave or DMA mode for accessing the data FIFOs.
                            int32_t dma_desc_enable
                             When DMA mode is enabled specifies whether to use address DMA or DMA Descritor mode for accessing the data FIFOs in device mode.
                            int32_t dma_burst_size
                             When DMA mode is enabled specifies whether to use address DMA or DMA Descriptor mode for accessing the data FIFOs in device mode.
                            int32_t dma_burst_size
                             The DMA Burst size (applicable only for External DMA Mode).
                            int32_t speed
                             The DMA Burst size (applicable only for External DMA Mode).
                            int32_t speed
                             Specifies the maximum speed of operation in host and device mode.
                            int32_t host_support_fs_ls_low_power
                             Specifies the maximum speed of operation in host and device mode.
                            int32_t host_support_fs_ls_low_power
                             Specifies whether low power mode is supported when attached to a Full Speed or Low Speed device in host mode.
                            int32_t host_ls_low_power_phy_clk
                             Specifies whether low power mode is supported when attached to a Full Speed or Low Speed device in host mode.
                            int32_t host_ls_low_power_phy_clk
                             Specifies the PHY clock rate in low power mode when connected to a Low Speed device in host mode.
                            +-int32_t enable_dynamic_fifo
                             Specifies the PHY clock rate in low power mode when connected to a Low Speed device in host mode.
                            ++int32_t enable_dynamic_fifo
                             0 - Use cC FIFO size parameters 1 - Allow dynamic FIFO sizing (default)
                            int32_t data_fifo_size
                            int32_t data_fifo_size
                             Total number of 4-byte words in the data FIFO memory.
                            int32_t dev_rx_fifo_size
                             Total number of 4-byte words in the data FIFO memory.
                            int32_t dev_rx_fifo_size
                             Number of 4-byte words in the Rx FIFO in device mode when dynamic FIFO sizing is enabled.
                            int32_t dev_nperio_tx_fifo_size
                             Number of 4-byte words in the Rx FIFO in device mode when dynamic FIFO sizing is enabled.
                            int32_t dev_nperio_tx_fifo_size
                             Number of 4-byte words in the non-periodic Tx FIFO in device mode when dynamic FIFO sizing is enabled.
                            uint32_t dev_perio_tx_fifo_size [MAX_PERIO_FIFOS]
                             Number of 4-byte words in the non-periodic Tx FIFO in device mode when dynamic FIFO sizing is enabled.
                            uint32_t dev_perio_tx_fifo_size [MAX_PERIO_FIFOS]
                             Number of 4-byte words in each of the periodic Tx FIFOs in device mode when dynamic FIFO sizing is enabled.
                            int32_t host_rx_fifo_size
                             Number of 4-byte words in each of the periodic Tx FIFOs in device mode when dynamic FIFO sizing is enabled.
                            int32_t host_rx_fifo_size
                             Number of 4-byte words in the Rx FIFO in host mode when dynamic FIFO sizing is enabled.
                            int32_t host_nperio_tx_fifo_size
                             Number of 4-byte words in the Rx FIFO in host mode when dynamic FIFO sizing is enabled.
                            int32_t host_nperio_tx_fifo_size
                             Number of 4-byte words in the non-periodic Tx FIFO in host mode when Dynamic FIFO sizing is enabled in the core.
                            int32_t host_perio_tx_fifo_size
                             Number of 4-byte words in the non-periodic Tx FIFO in host mode when Dynamic FIFO sizing is enabled in the core.
                            int32_t host_perio_tx_fifo_size
                             Number of 4-byte words in the host periodic Tx FIFO when dynamic FIFO sizing is enabled.
                            int32_t max_transfer_size
                             Number of 4-byte words in the host periodic Tx FIFO when dynamic FIFO sizing is enabled.
                            int32_t max_transfer_size
                             The maximum transfer size supported in bytes.
                            int32_t max_packet_count
                             The maximum transfer size supported in bytes.
                            int32_t max_packet_count
                             The maximum number of packets in a transfer.
                            int32_t host_channels
                             The maximum number of packets in a transfer.
                            int32_t host_channels
                             The number of host channel registers to use.
                            int32_t dev_endpoints
                             The number of host channel registers to use.
                            int32_t dev_endpoints
                             The number of endpoints in addition to EP0 available for device mode operations.
                            int32_t phy_type
                             The number of endpoints in addition to EP0 available for device mode operations.
                            int32_t phy_type
                             Specifies the type of PHY interface to use.
                            int32_t phy_utmi_width
                             Specifies the type of PHY interface to use.
                            int32_t phy_utmi_width
                             Specifies the UTMI+ Data Width.
                            int32_t phy_ulpi_ddr
                             Specifies the UTMI+ Data Width.
                            int32_t phy_ulpi_ddr
                             Specifies whether the ULPI operates at double or single data rate.
                            +-int32_t phy_ulpi_ext_vbus
                             Specifies whether the ULPI operates at double or single data rate.
                            int32_t phy_ulpi_ext_vbus
                             Specifies whether to use the internal or external supply to drive the vbus with a ULPI phy.
                            int32_t i2c_enable
                             Specifies whether to use the internal or external supply to drive the vbus with a ULPI phy.
                            int32_t i2c_enable
                             Specifies whether to use the I2Cinterface for full speed PHY.
                            +-int32_t ulpi_fs_ls
                             Specifies whether to use the I2Cinterface for full speed PHY.
                            ++int32_t ulpi_fs_ls
                            +-int32_t ts_dline
                            ++int32_t ts_dline
                            +-int32_t en_multiple_tx_fifo
                            ++int32_t en_multiple_tx_fifo
                             Specifies whether dedicated transmit FIFOs are enabled for non periodic IN endpoints in device mode 0 - No 1 - Yes.
                            uint32_t dev_tx_fifo_size [MAX_TX_FIFOS]
                            uint32_t dev_tx_fifo_size [MAX_TX_FIFOS]
                             Number of 4-byte words in each of the Tx FIFOs in device mode when dynamic FIFO sizing is enabled.
                            +-uint32_t thr_ctl
                             Number of 4-byte words in each of the Tx FIFOs in device mode when dynamic FIFO sizing is enabled.
                            ++uint32_t thr_ctl
                             Thresholding enable flag- bit 0 - enable non-ISO Tx thresholding bit 1 - enable ISO Tx thresholding bit 2 - enable Rx thresholding.
                            +-uint32_t tx_thr_length
                            ++uint32_t tx_thr_length
                             Thresholding length for Tx FIFOs in 32 bit DWORDs.
                            +-uint32_t rx_thr_length
                            ++uint32_t rx_thr_length
                             Thresholding length for Rx FIFOs in 32 bit DWORDs.
                            +-int32_t lpm_enable
                            ++int32_t lpm_enable
                             Specifies whether LPM (Link Power Management) support is enabled.
                            +-int32_t pti_enable
                            ++int32_t pti_enable
                             Per Transfer Interrupt mode enable flag 1 - Enabled 0 - Disabled.
                            +-int32_t mpi_enable
                            ++int32_t mpi_enable
                             Multi Processor Interrupt mode enable flag 1 - Enabled 0 - Disabled.
                            +-int32_t ic_usb_cap
                            ++int32_t ic_usb_cap
                             IS_USB Capability 1 - Enabled 0 - Disabled.
                            +-int32_t ahb_thr_ratio
                            ++int32_t ahb_thr_ratio
                             AHB Threshold Ratio 2'b00 AHB Threshold = MAC Threshold 2'b01 AHB Threshold = 1/2 MAC Threshold 2'b10 AHB Threshold = 1/4 MAC Threshold 2'b11 AHB Threshold = 1/8 MAC Threshold.
                            ++int32_t adp_supp_enable
                             ADP Support 1 - Enabled 0 - Disabled.
                            int32_t reload_ctl
                             HFIR Reload Control 0 - The HFIR cannot be reloaded dynamically.
                            int32_t dev_out_nak
                             DCFG: Enable device Out NAK 0 - The core does not set NAK after Bulk Out transfer complete.
                            int32_t cont_on_bna
                             DCFG: Enable Continue on BNA After receiving BNA interrupt the core disables the endpoint,when the endpoint is re-enabled by the application the core starts processing 0 - from the DOEPDMA descriptor 1 - from the descriptor which received the BNA.
                            int32_t ahb_single
                             GAHBCFG: AHB Single Support This bit when programmed supports SINGLE transfers for remainder data in a transfer for DMA mode of operation.
                            ++int32_t power_down
                             Core Power down mode 0 - No Power Down is enabled 1 - Reserved 2 - Complete Power Down (Hibernation).
                            ++int32_t otg_ver
                             OTG revision supported 0 - OTG 1.3 revision 1 - OTG 2.0 revision.
                            +

                            Detailed Description

                            + The following parameters may be specified when starting the module. +@@ -155,452 +166,771 @@ +

                            + +

                            +-Definition at line 401 of file dwc_otg_cil.h.

                            Field Documentation

                            +- +-
                            +-
                            +- ++Definition at line 424 of file dwc_otg_cil.h.

                            Field Documentation

                            ++

                            ++

                            ++ ++ ++ ++
                            ++ + +- ++ + +
                            int32_t dwc_otg_core_params::otg_cap int32_t dwc_otg_core_params::otg_cap
                            +- +-
                            ++
                            ++ ++ ++ ++
                            ++   ++ + +

                            + Specifies the OTG capabilities. +

                            +-The driver will automatically detect the value for this parameter if none is specified. 0 - HNP and SRP capable (default) 1 - SRP Only capable 2 - No HNP/SRP capable ++The driver will automatically detect the value for this parameter if none is specified. 0 - HNP and SRP capable (default) 1 - SRP Only capable 2 - No HNP/SRP capable +

                            +-Definition at line 411 of file dwc_otg_cil.h. +- +-

                            +- +-

                            +-
                            +- ++Definition at line 434 of file dwc_otg_cil.h. ++ ++
                            ++

                            ++ ++ ++ ++ ++
                            ++ + +- ++ + +
                            int32_t dwc_otg_core_params::dma_enable int32_t dwc_otg_core_params::dma_enable
                            +- +-
                            ++
                            ++ ++ ++ ++
                            ++   ++ + +

                            + Specifies whether to use slave or DMA mode for accessing the data FIFOs. +

                            +-The driver will automatically detect the value for this parameter if none is specified. 0 - Slave 1 - DMA (default, if available) ++The driver will automatically detect the value for this parameter if none is specified. 0 - Slave 1 - DMA (default, if available) +

                            +-Definition at line 420 of file dwc_otg_cil.h. +- +-

                            +- +-

                            +-
                            +- ++Definition at line 443 of file dwc_otg_cil.h. ++ ++
                            ++

                            ++ ++ ++ ++ ++
                            ++ + +- ++ + +
                            int32_t dwc_otg_core_params::dma_desc_enable int32_t dwc_otg_core_params::dma_desc_enable
                            +- +-
                            ++
                            ++ ++ ++ ++
                            ++   ++ + +

                            +-When DMA mode is enabled specifies whether to use address DMA or DMA Descritor mode for accessing the data FIFOs in device mode. ++When DMA mode is enabled specifies whether to use address DMA or DMA Descriptor mode for accessing the data FIFOs in device mode. +

                            +-The driver will automatically detect the value for this parameter if none is specified. 0 - address DMA 1 - DMA Descriptor(default, if available) ++The driver will automatically detect the value for this if none is specified. 0 - address DMA 1 - DMA Descriptor(default, if available) +

                            +-Definition at line 429 of file dwc_otg_cil.h. +- +-

                            +- +-

                            +-
                            +- ++Definition at line 452 of file dwc_otg_cil.h. ++ ++
                            ++

                            ++ ++ ++ ++ ++
                            ++ + +- ++ + +
                            int32_t dwc_otg_core_params::dma_burst_size int32_t dwc_otg_core_params::dma_burst_size
                            +- +-
                            ++
                            ++ ++ ++ ++
                            ++   ++ + +

                            + The DMA Burst size (applicable only for External DMA Mode). +

                            +-1, 4, 8 16, 32, 64, 128, 256 (default 32) ++1, 4, 8 16, 32, 64, 128, 256 (default 32) +

                            +-Definition at line 433 of file dwc_otg_cil.h. +- +-

                            +- +-

                            +-
                            +- ++Definition at line 456 of file dwc_otg_cil.h. ++ ++
                            ++

                            ++ ++ ++ ++ ++
                            ++ + +- ++ + +
                            int32_t dwc_otg_core_params::speed int32_t dwc_otg_core_params::speed
                            +- +-
                            ++
                            ++ ++ ++ ++
                            ++   ++ + +

                            + Specifies the maximum speed of operation in host and device mode. +

                            +-The actual speed depends on the speed of the attached device and the value of phy_type. The actual speed depends on the speed of the attached device. 0 - High Speed (default) 1 - Full Speed ++The actual speed depends on the speed of the attached device and the value of phy_type. The actual speed depends on the speed of the attached device. 0 - High Speed (default) 1 - Full Speed +

                            +-Definition at line 443 of file dwc_otg_cil.h. +- +-

                            +- +-

                            +-
                            +- ++Definition at line 466 of file dwc_otg_cil.h. ++ ++
                            ++

                            ++ ++ ++ ++ ++
                            ++ + +- ++ + +
                            int32_t dwc_otg_core_params::host_support_fs_ls_low_power int32_t dwc_otg_core_params::host_support_fs_ls_low_power
                            +- +-
                            ++
                            ++ ++ ++ ++
                            ++   ++ + +

                            + Specifies whether low power mode is supported when attached to a Full Speed or Low Speed device in host mode. +

                            +-0 - Don't support low power mode (default) 1 - Support low power mode ++0 - Don't support low power mode (default) 1 - Support low power mode +

                            +-Definition at line 449 of file dwc_otg_cil.h. +- +-

                            +- +-

                            +-
                            +- ++Definition at line 472 of file dwc_otg_cil.h. ++ ++
                            ++

                            ++ ++ ++ ++ ++
                            ++ + +- ++ + +
                            int32_t dwc_otg_core_params::host_ls_low_power_phy_clk int32_t dwc_otg_core_params::host_ls_low_power_phy_clk
                            +- +-
                            ++
                            ++ ++ ++ ++
                            ++   ++ + +

                            + Specifies the PHY clock rate in low power mode when connected to a Low Speed device in host mode. +

                            + This parameter is applicable only if HOST_SUPPORT_FS_LS_LOW_POWER is enabled. If PHY_TYPE is set to FS then defaults to 6 MHZ otherwise 48 MHZ.

                            +-0 - 48 MHz 1 - 6 MHz ++0 - 48 MHz 1 - 6 MHz +

                            +-Definition at line 459 of file dwc_otg_cil.h. +- +-

                            +- +-

                            +-
                            +- ++Definition at line 482 of file dwc_otg_cil.h. ++ ++
                            ++

                            ++ ++ ++ ++ ++
                            ++ + +- ++ + +
                            int32_t dwc_otg_core_params::data_fifo_size int32_t dwc_otg_core_params::data_fifo_size
                            +- +-
                            ++
                            ++ ++ ++ ++
                            ++   ++ + +

                            + Total number of 4-byte words in the data FIFO memory. +

                            +-This memory includes the Rx FIFO, non-periodic Tx FIFO, and periodic Tx FIFOs. 32 to 32768 (default 8192) Note: The total FIFO memory depth in the FPGA configuration is 8192. ++This memory includes the Rx FIFO, non-periodic Tx FIFO, and periodic Tx FIFOs. 32 to 32768 (default 8192) Note: The total FIFO memory depth in the FPGA configuration is 8192. +

                            +-Definition at line 473 of file dwc_otg_cil.h. +- +-

                            +- +-

                            +-
                            +- ++Definition at line 496 of file dwc_otg_cil.h. ++ ++
                            ++

                            ++ ++ ++ ++ ++
                            ++ + +- ++ + +
                            int32_t dwc_otg_core_params::dev_rx_fifo_size int32_t dwc_otg_core_params::dev_rx_fifo_size
                            +- +-
                            ++
                            ++ ++ ++ ++
                            ++   ++ + +

                            + Number of 4-byte words in the Rx FIFO in device mode when dynamic FIFO sizing is enabled. +

                            +-16 to 32768 (default 1064) ++16 to 32768 (default 1064) +

                            +-Definition at line 479 of file dwc_otg_cil.h. +- +-

                            +- +-

                            +-
                            +- ++Definition at line 502 of file dwc_otg_cil.h. ++ ++
                            ++

                            ++ ++ ++ ++ ++
                            ++ + +- ++ + +
                            int32_t dwc_otg_core_params::dev_nperio_tx_fifo_size int32_t dwc_otg_core_params::dev_nperio_tx_fifo_size
                            +- +-
                            ++
                            ++ ++ ++ ++
                            ++   ++ + +

                            + Number of 4-byte words in the non-periodic Tx FIFO in device mode when dynamic FIFO sizing is enabled. +

                            +-16 to 32768 (default 1024) ++16 to 32768 (default 1024) +

                            +-Definition at line 485 of file dwc_otg_cil.h. +- +-

                            +- +-

                            +-
                            +- ++Definition at line 508 of file dwc_otg_cil.h. ++ ++
                            ++

                            ++ ++ ++ ++ ++
                            ++ + +- ++ + +
                            uint32_t dwc_otg_core_params::dev_perio_tx_fifo_size[MAX_PERIO_FIFOS] uint32_t dwc_otg_core_params::dev_perio_tx_fifo_size[MAX_PERIO_FIFOS]
                            +- +-
                            ++
                            ++ ++ ++ ++
                            ++   ++ + +

                            + Number of 4-byte words in each of the periodic Tx FIFOs in device mode when dynamic FIFO sizing is enabled. +

                            +-4 to 768 (default 256) ++4 to 768 (default 256) +

                            +-Definition at line 491 of file dwc_otg_cil.h. +- +-

                            +- +-

                            +-
                            +- ++Definition at line 514 of file dwc_otg_cil.h. ++ ++
                            ++

                            ++ ++ ++ ++ ++
                            ++ + +- ++ + +
                            int32_t dwc_otg_core_params::host_rx_fifo_size int32_t dwc_otg_core_params::host_rx_fifo_size
                            +- +-
                            ++
                            ++ ++ ++ ++
                            ++   ++ + +

                            + Number of 4-byte words in the Rx FIFO in host mode when dynamic FIFO sizing is enabled. +

                            +-16 to 32768 (default 1024) ++16 to 32768 (default 1024) +

                            +-Definition at line 497 of file dwc_otg_cil.h. +- +-

                            +- +-

                            +-
                            +- ++Definition at line 520 of file dwc_otg_cil.h. ++ ++
                            ++

                            ++ ++ ++ ++ ++
                            ++ + +- ++ + +
                            int32_t dwc_otg_core_params::host_nperio_tx_fifo_size int32_t dwc_otg_core_params::host_nperio_tx_fifo_size
                            +- +-
                            ++
                            ++ ++ ++ ++
                            ++   ++ + +

                            + Number of 4-byte words in the non-periodic Tx FIFO in host mode when Dynamic FIFO sizing is enabled in the core. +

                            +-16 to 32768 (default 1024) ++16 to 32768 (default 1024) +

                            +-Definition at line 503 of file dwc_otg_cil.h. +- +-

                            +- +-

                            +-
                            +- ++Definition at line 526 of file dwc_otg_cil.h. ++ ++
                            ++

                            ++ ++ ++ ++ ++
                            ++ + +- ++ + +
                            int32_t dwc_otg_core_params::host_perio_tx_fifo_size int32_t dwc_otg_core_params::host_perio_tx_fifo_size
                            +- +-
                            ++
                            ++ ++ ++ ++
                            ++   ++ + +

                            + Number of 4-byte words in the host periodic Tx FIFO when dynamic FIFO sizing is enabled. +

                            +-16 to 32768 (default 1024) ++16 to 32768 (default 1024) +

                            +-Definition at line 509 of file dwc_otg_cil.h. +- +-

                            +- +-

                            +-
                            +- ++Definition at line 532 of file dwc_otg_cil.h. ++ ++
                            ++

                            ++ ++ ++ ++ ++
                            ++ + +- ++ + +
                            int32_t dwc_otg_core_params::max_transfer_size int32_t dwc_otg_core_params::max_transfer_size
                            +- +-
                            ++
                            ++ ++ ++ ++
                            ++   ++ + +

                            + The maximum transfer size supported in bytes. +

                            +-2047 to 65,535 (default 65,535) ++2047 to 65,535 (default 65,535) +

                            +-Definition at line 514 of file dwc_otg_cil.h. +- +-

                            +- +-

                            +-
                            +- ++Definition at line 537 of file dwc_otg_cil.h. ++ ++
                            ++

                            ++ ++ ++ ++ ++
                            ++ + +- ++ + +
                            int32_t dwc_otg_core_params::max_packet_count int32_t dwc_otg_core_params::max_packet_count
                            +- +-
                            ++
                            ++ ++ ++ ++
                            ++   ++ + +

                            + The maximum number of packets in a transfer. +

                            +-15 to 511 (default 511) ++15 to 511 (default 511) +

                            +-Definition at line 519 of file dwc_otg_cil.h. +- +-

                            +- +-

                            +-
                            +- ++Definition at line 542 of file dwc_otg_cil.h. ++ ++
                            ++

                            ++ ++ ++ ++ ++
                            ++ + +- ++ + +
                            int32_t dwc_otg_core_params::host_channels int32_t dwc_otg_core_params::host_channels
                            +- +-
                            ++
                            ++ ++ ++ ++
                            ++   ++ + +

                            + The number of host channel registers to use. +

                            +-1 to 16 (default 12) Note: The FPGA configuration supports a maximum of 12 host channels. ++1 to 16 (default 12) Note: The FPGA configuration supports a maximum of 12 host channels. +

                            +-Definition at line 525 of file dwc_otg_cil.h. +- +-

                            +- +-

                            +-
                            +- ++Definition at line 548 of file dwc_otg_cil.h. ++ ++
                            ++

                            ++ ++ ++ ++ ++
                            ++ + +- ++ + +
                            int32_t dwc_otg_core_params::dev_endpoints int32_t dwc_otg_core_params::dev_endpoints
                            +- +-
                            ++
                            ++ ++ ++ ++
                            ++   ++ + +

                            + The number of endpoints in addition to EP0 available for device mode operations. +

                            +-1 to 15 (default 6 IN and OUT) Note: The FPGA configuration supports a maximum of 6 IN and OUT endpoints in addition to EP0. ++1 to 15 (default 6 IN and OUT) Note: The FPGA configuration supports a maximum of 6 IN and OUT endpoints in addition to EP0. +

                            +-Definition at line 533 of file dwc_otg_cil.h. +- +-

                            +- +-

                            +-
                            +- ++Definition at line 556 of file dwc_otg_cil.h. ++ ++
                            ++

                            ++ ++ ++ ++ ++
                            ++ + +- ++ + +
                            int32_t dwc_otg_core_params::phy_type int32_t dwc_otg_core_params::phy_type
                            +- +-
                            ++
                            ++ ++ ++ ++
                            ++   ++ + +

                            + Specifies the type of PHY interface to use. +

                            + By default, the driver will automatically detect the phy_type.

                            +-0 - Full Speed PHY 1 - UTMI+ (default) 2 - ULPI ++0 - Full Speed PHY 1 - UTMI+ (default) 2 - ULPI +

                            +-Definition at line 543 of file dwc_otg_cil.h. +- +-

                            +- +-

                            +-
                            +- ++Definition at line 566 of file dwc_otg_cil.h. ++ ++
                            ++

                            ++ ++ ++ ++ ++
                            ++ + +- ++ + +
                            int32_t dwc_otg_core_params::phy_utmi_width int32_t dwc_otg_core_params::phy_utmi_width
                            +- +-
                            ++
                            ++ ++ ++ ++
                            ++   ++ + +

                            + Specifies the UTMI+ Data Width. +

                            + This parameter is applicable for a PHY_TYPE of UTMI+ or ULPI. (For a ULPI PHY_TYPE, this parameter indicates the data width between the MAC and the ULPI Wrapper.) Also, this parameter is applicable only if the OTG_HSPHY_WIDTH cC parameter was set to "8 and 16 bits", meaning that the core has been configured to work at either data path width.

                            +-8 or 16 bits (default 16) ++8 or 16 bits (default 16) +

                            +-Definition at line 556 of file dwc_otg_cil.h. +- +-

                            +- +-

                            +-
                            +- ++Definition at line 579 of file dwc_otg_cil.h. ++ ++
                            ++

                            ++ ++ ++ ++ ++
                            ++ + +- ++ + +
                            int32_t dwc_otg_core_params::phy_ulpi_ddr int32_t dwc_otg_core_params::phy_ulpi_ddr
                            +- +-
                            ++
                            ++ ++ ++ ++ ++ ++
                            ++   ++ + +

                            + Specifies whether the ULPI operates at double or single data rate. +

                            + This parameter is only applicable if PHY_TYPE is ULPI.

                            +-0 - single data rate ULPI interface with 8 bit wide data bus (default) 1 - double data rate ULPI interface with 4 bit wide data bus ++0 - single data rate ULPI interface with 8 bit wide data bus (default) 1 - double data rate ULPI interface with 4 bit wide data bus ++

                            ++Definition at line 591 of file dwc_otg_cil.h.

                            ++

                            ++ ++ ++ ++ ++
                            ++ ++ ++ ++ ++
                            int32_t dwc_otg_core_params::phy_ulpi_ext_vbus
                            ++
                            ++ ++ ++ ++
                            ++   ++ ++ ++

                            ++Specifies whether to use the internal or external supply to drive the vbus with a ULPI phy. +

                            +-Definition at line 568 of file dwc_otg_cil.h. +- +-

                            +- +-

                            +-
                            +- ++ ++

                            ++Definition at line 597 of file dwc_otg_cil.h. ++ ++

                            ++

                            ++ ++ ++ ++ ++
                            ++ + +- ++ + +
                            int32_t dwc_otg_core_params::i2c_enable int32_t dwc_otg_core_params::i2c_enable
                            +- +-
                            ++
                            ++ ++ ++ ++
                            ++   ++ + +

                            + Specifies whether to use the I2Cinterface for full speed PHY. +

                            +-This parameter is only applicable if PHY_TYPE is FS. 0 - No (default) 1 - Yes ++This parameter is only applicable if PHY_TYPE is FS. 0 - No (default) 1 - Yes +

                            +-Definition at line 582 of file dwc_otg_cil.h. +- +-

                            +- +-

                            +-
                            +- ++Definition at line 605 of file dwc_otg_cil.h. ++ ++
                            ++

                            ++ ++ ++ ++ ++
                            ++ + +- ++ + +
                            uint32_t dwc_otg_core_params::dev_tx_fifo_size[MAX_TX_FIFOS] uint32_t dwc_otg_core_params::dev_tx_fifo_size[MAX_TX_FIFOS]
                            +- +-
                            ++
                            ++ ++ ++ ++ ++ ++
                            ++   ++ + +

                            + Number of 4-byte words in each of the Tx FIFOs in device mode when dynamic FIFO sizing is enabled. +

                            +-4 to 768 (default 256) ++4 to 768 (default 256) ++

                            ++Definition at line 623 of file dwc_otg_cil.h.

                            ++

                            ++ ++ ++ ++ ++
                            ++ ++ ++ ++ ++
                            int32_t dwc_otg_core_params::reload_ctl
                            ++
                            ++ ++ ++ ++ ++ ++
                            ++   ++ ++ ++

                            ++HFIR Reload Control 0 - The HFIR cannot be reloaded dynamically. ++

                            ++1 - Allow dynamic reloading of the HFIR register during runtime. ++

                            ++Definition at line 685 of file dwc_otg_cil.h.

                            ++

                            ++ ++ ++ ++ ++
                            ++ ++ ++ ++ ++
                            int32_t dwc_otg_core_params::dev_out_nak
                            ++
                            ++ ++ ++ ++ ++ ++
                            ++   ++ ++ ++

                            ++DCFG: Enable device Out NAK 0 - The core does not set NAK after Bulk Out transfer complete. ++

                            ++1 - The core sets NAK after Bulk OUT transfer complete. ++

                            ++Definition at line 691 of file dwc_otg_cil.h.

                            ++

                            ++ ++ ++ ++ ++
                            ++ ++ ++ ++ ++
                            int32_t dwc_otg_core_params::cont_on_bna
                            ++
                            ++ ++ ++ ++ ++ ++
                            ++   ++ ++ ++

                            ++DCFG: Enable Continue on BNA After receiving BNA interrupt the core disables the endpoint,when the endpoint is re-enabled by the application the core starts processing 0 - from the DOEPDMA descriptor 1 - from the descriptor which received the BNA. +

                            +-Definition at line 600 of file dwc_otg_cil.h. +- +-

                            ++ ++

                            ++Definition at line 699 of file dwc_otg_cil.h.

                            ++

                            ++ ++ ++ ++ ++
                            ++ ++ ++ ++ ++
                            int32_t dwc_otg_core_params::ahb_single
                            ++
                            ++ ++ ++ ++ ++ ++
                            ++   ++ ++ ++

                            ++GAHBCFG: AHB Single Support This bit when programmed supports SINGLE transfers for remainder data in a transfer for DMA mode of operation. ++

                            ++0 - in this case the remainder data will be sent using INCR burst size. 1 - in this case the remainder data will be sent using SINGLE burst size. ++

                            ++Definition at line 707 of file dwc_otg_cil.h.

                            +

                            The documentation for this struct was generated from the following file: +-
                            Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++
                            Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
                            ++doxygen 1.3.9.1
                            + + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__dev__dma__desc.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__dev__dma__desc.html 2013-07-26 19:31:22.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__dev__dma__desc.html 2013-07-26 19:34:43.000000000 +0000 +@@ -2,22 +2,10 @@ + + DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_dev_dma_desc Struct Reference + +- + +- +-
                            +-
                            +-
                            +-
                            +-

                            dwc_otg_dev_dma_desc Struct Reference

                            DMA Descriptor structure. ++ ++
                            Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                            ++

                            dwc_otg_dev_dma_desc Struct Reference

                            DMA Descriptor structure. + More... +

                            + #include <dwc_otg_regs.h> +@@ -25,12 +13,12 @@ + + + +- ++ + + +- ++ + + +

                            Data Fields

                            +-dev_dma_desc_sts_t status
                            ++dev_dma_desc_sts_t status
                             DMA Descriptor status quadlet.
                            +-uint32_t buf
                            ++uint32_t buf
                             DMA Descriptor data buffer pointer.
                            +@@ -41,10 +29,10 @@ +

                            + +

                            +-Definition at line 1542 of file dwc_otg_regs.h.

                            The documentation for this struct was generated from the following file:
                              ++Definition at line 1767 of file dwc_otg_regs.h.
                              The documentation for this struct was generated from the following file: +-
                              Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++
                              Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
                              ++doxygen 1.3.9.1
                              + + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__dev__global__regs.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__dev__global__regs.html 2013-07-26 19:31:22.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__dev__global__regs.html 2013-07-26 19:34:43.000000000 +0000 +@@ -2,22 +2,10 @@ + + DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_dev_global_regs Struct Reference + +- + +- +-
                              +-
                              +-
                              +-
                              +-

                              dwc_otg_dev_global_regs Struct Reference

                              Device Global Registers. ++ ++
                              Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                              ++

                              dwc_otg_dev_global_regs Struct Reference

                              Device Global Registers. + More... +

                              + #include <dwc_otg_regs.h> +@@ -25,60 +13,60 @@ + + + +- ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- ++ +

                              Data Fields

                              volatile uint32_t dcfg
                              volatile uint32_t dcfg
                               Device Configuration Register.
                              volatile uint32_t dctl
                               Device Configuration Register.
                              volatile uint32_t dctl
                               Device Control Register.
                              volatile uint32_t dsts
                               Device Control Register.
                              volatile uint32_t dsts
                               Device Status Register (Read Only).
                              uint32_t unused
                               Device Status Register (Read Only).
                              uint32_t unused
                               Reserved.
                              volatile uint32_t diepmsk
                               Reserved.
                              volatile uint32_t diepmsk
                               Device IN Endpoint Common Interrupt Mask Register.
                              volatile uint32_t doepmsk
                               Device IN Endpoint Common Interrupt Mask Register.
                              volatile uint32_t doepmsk
                               Device OUT Endpoint Common Interrupt Mask Register.
                              volatile uint32_t daint
                               Device OUT Endpoint Common Interrupt Mask Register.
                              volatile uint32_t daint
                               Device All Endpoints Interrupt Register.
                              volatile uint32_t daintmsk
                               Device All Endpoints Interrupt Register.
                              volatile uint32_t daintmsk
                               Device All Endpoints Interrupt Mask Register.
                              volatile uint32_t dtknqr1
                               Device All Endpoints Interrupt Mask Register.
                              volatile uint32_t dtknqr1
                               Device IN Token Queue Read Register-1 (Read Only).
                              volatile uint32_t dtknqr2
                               Device IN Token Queue Read Register-1 (Read Only).
                              volatile uint32_t dtknqr2
                               Device IN Token Queue Read Register-2 (Read Only).
                              volatile uint32_t dvbusdis
                               Device IN Token Queue Read Register-2 (Read Only).
                              volatile uint32_t dvbusdis
                               Device VBUS discharge Register.
                              volatile uint32_t dvbuspulse
                               Device VBUS discharge Register.
                              volatile uint32_t dvbuspulse
                               Device VBUS Pulse Register.
                              volatile uint32_t dtknqr3_dthrctl
                               Device VBUS Pulse Register.
                              volatile uint32_t dtknqr3_dthrctl
                               Device IN Token Queue Read Register-3 (Read Only).
                              volatile uint32_t dtknqr4_fifoemptymsk
                               Device IN Token Queue Read Register-3 (Read Only).
                              volatile uint32_t dtknqr4_fifoemptymsk
                               Device IN Token Queue Read Register-4 (Read Only).
                              volatile uint32_t deachint
                               Device IN Token Queue Read Register-4 (Read Only).
                              volatile uint32_t deachint
                               Device Each Endpoint Interrupt Register (Read Only).
                              volatile uint32_t deachintmsk
                               Device Each Endpoint Interrupt Register (Read Only).
                              volatile uint32_t deachintmsk
                               Device Each Endpoint Interrupt mask Register (Read/Write).
                              volatile uint32_t diepeachintmsk [MAX_EPS_CHANNELS]
                               Device Each Endpoint Interrupt mask Register (Read/Write).
                              volatile uint32_t diepeachintmsk [MAX_EPS_CHANNELS]
                               Device Each In Endpoint Interrupt mask Register (Read/Write).
                              volatile uint32_t doepeachintmsk [MAX_EPS_CHANNELS]
                               Device Each In Endpoint Interrupt mask Register (Read/Write).
                              volatile uint32_t doepeachintmsk [MAX_EPS_CHANNELS]
                               Device Each Out Endpoint Interrupt mask Register (Read/Write).
                               Device Each Out Endpoint Interrupt mask Register (Read/Write).
                              +

                              Detailed Description

                              + Device Global Registers. +@@ -89,353 +77,497 @@ +

                              + +

                              +-Definition at line 865 of file dwc_otg_regs.h.

                              Field Documentation

                              +- +-
                              +-
                              +- ++Definition at line 1079 of file dwc_otg_regs.h.

                              Field Documentation

                              ++

                              ++

                              ++ ++ ++ ++
                              ++ + +- ++ + +
                              volatile uint32_t dwc_otg_dev_global_regs::dcfg volatile uint32_t dwc_otg_dev_global_regs::dcfg
                              +- +-
                              ++
                              ++ ++ ++ ++
                              ++   ++ + +

                              + Device Configuration Register. +

                              + Offset 800h +

                              +-Definition at line 867 of file dwc_otg_regs.h. +- +-

                              +- +-

                              +-
                              +- ++Definition at line 1081 of file dwc_otg_regs.h. ++ ++
                              ++

                              ++ ++ ++ ++ ++
                              ++ + +- ++ + +
                              volatile uint32_t dwc_otg_dev_global_regs::dctl volatile uint32_t dwc_otg_dev_global_regs::dctl
                              +- +-
                              ++
                              ++ ++ ++ ++
                              ++   ++ + +

                              + Device Control Register. +

                              + Offset: 804h +

                              +-Definition at line 869 of file dwc_otg_regs.h. +- +-

                              +- +-

                              +-
                              +- ++Definition at line 1083 of file dwc_otg_regs.h. ++ ++
                              ++

                              ++ ++ ++ ++ ++
                              ++ + +- ++ + +
                              volatile uint32_t dwc_otg_dev_global_regs::dsts volatile uint32_t dwc_otg_dev_global_regs::dsts
                              +- +-
                              ++
                              ++ ++ ++ ++
                              ++   ++ + +

                              + Device Status Register (Read Only). +

                              + Offset: 808h +

                              +-Definition at line 871 of file dwc_otg_regs.h. +- +-

                              +- +-

                              +-
                              +- ++Definition at line 1085 of file dwc_otg_regs.h. ++ ++
                              ++

                              ++ ++ ++ ++ ++
                              ++ + +- ++ + +
                              uint32_t dwc_otg_dev_global_regs::unused uint32_t dwc_otg_dev_global_regs::unused
                              +- +-
                              ++
                              ++ ++ ++ ++
                              ++   ++ + +

                              + Reserved. +

                              + Offset: 80Ch +

                              +-Definition at line 873 of file dwc_otg_regs.h. +- +-

                              +- +-

                              +-
                              +- ++Definition at line 1087 of file dwc_otg_regs.h. ++ ++
                              ++

                              ++ ++ ++ ++ ++
                              ++ + +- ++ + +
                              volatile uint32_t dwc_otg_dev_global_regs::diepmsk volatile uint32_t dwc_otg_dev_global_regs::diepmsk
                              +- +-
                              ++
                              ++ ++ ++ ++
                              ++   ++ + +

                              + Device IN Endpoint Common Interrupt Mask Register. +

                              + Offset: 810h +

                              +-Definition at line 876 of file dwc_otg_regs.h. +- +-

                              +- +-

                              +-
                              +- ++Definition at line 1090 of file dwc_otg_regs.h. ++ ++
                              ++

                              ++ ++ ++ ++ ++
                              ++ + +- ++ + +
                              volatile uint32_t dwc_otg_dev_global_regs::doepmsk volatile uint32_t dwc_otg_dev_global_regs::doepmsk
                              +- +-
                              ++
                              ++ ++ ++ ++
                              ++   ++ + +

                              + Device OUT Endpoint Common Interrupt Mask Register. +

                              + Offset: 814h +

                              +-Definition at line 879 of file dwc_otg_regs.h. +- +-

                              +- +-

                              +-
                              +- ++Definition at line 1093 of file dwc_otg_regs.h. ++ ++
                              ++

                              ++ ++ ++ ++ ++
                              ++ + +- ++ + +
                              volatile uint32_t dwc_otg_dev_global_regs::daint volatile uint32_t dwc_otg_dev_global_regs::daint
                              +- +-
                              ++
                              ++ ++ ++ ++
                              ++   ++ + +

                              + Device All Endpoints Interrupt Register. +

                              + Offset: 818h +

                              +-Definition at line 881 of file dwc_otg_regs.h. +- +-

                              +- +-

                              +-
                              +- ++Definition at line 1095 of file dwc_otg_regs.h. ++ ++
                              ++

                              ++ ++ ++ ++ ++
                              ++ + +- ++ + +
                              volatile uint32_t dwc_otg_dev_global_regs::daintmsk volatile uint32_t dwc_otg_dev_global_regs::daintmsk
                              +- +-
                              ++
                              ++ ++ ++ ++
                              ++   ++ + +

                              + Device All Endpoints Interrupt Mask Register. +

                              + Offset: 81Ch +

                              +-Definition at line 884 of file dwc_otg_regs.h. +- +-

                              +- +-

                              +-
                              +- ++Definition at line 1098 of file dwc_otg_regs.h. ++ ++
                              ++

                              ++ ++ ++ ++ ++
                              ++ + +- ++ + +
                              volatile uint32_t dwc_otg_dev_global_regs::dtknqr1 volatile uint32_t dwc_otg_dev_global_regs::dtknqr1
                              +- +-
                              ++
                              ++ ++ ++ ++
                              ++   ++ + +

                              + Device IN Token Queue Read Register-1 (Read Only). +

                              + Offset: 820h +

                              +-Definition at line 887 of file dwc_otg_regs.h. +- +-

                              +- +-

                              +-
                              +- ++Definition at line 1101 of file dwc_otg_regs.h. ++ ++
                              ++

                              ++ ++ ++ ++ ++
                              ++ + +- ++ + +
                              volatile uint32_t dwc_otg_dev_global_regs::dtknqr2 volatile uint32_t dwc_otg_dev_global_regs::dtknqr2
                              +- +-
                              ++
                              ++ ++ ++ ++
                              ++   ++ + +

                              + Device IN Token Queue Read Register-2 (Read Only). +

                              + Offset: 824h +

                              +-Definition at line 890 of file dwc_otg_regs.h. +- +-

                              +- +-

                              +-
                              +- ++Definition at line 1104 of file dwc_otg_regs.h. ++ ++
                              ++

                              ++ ++ ++ ++ ++
                              ++ + +- ++ + +
                              volatile uint32_t dwc_otg_dev_global_regs::dvbusdis volatile uint32_t dwc_otg_dev_global_regs::dvbusdis
                              +- +-
                              ++
                              ++ ++ ++ ++
                              ++   ++ + +

                              + Device VBUS discharge Register. +

                              + Offset: 828h +

                              +-Definition at line 892 of file dwc_otg_regs.h. +- +-

                              +- +-

                              +-
                              +- ++Definition at line 1106 of file dwc_otg_regs.h. ++ ++
                              ++

                              ++ ++ ++ ++ ++
                              ++ + +- ++ + +
                              volatile uint32_t dwc_otg_dev_global_regs::dvbuspulse volatile uint32_t dwc_otg_dev_global_regs::dvbuspulse
                              +- +-
                              ++
                              ++ ++ ++ ++
                              ++   ++ + +

                              + Device VBUS Pulse Register. +

                              + Offset: 82Ch +

                              +-Definition at line 894 of file dwc_otg_regs.h. +- +-

                              +- +-

                              +-
                              +- ++Definition at line 1108 of file dwc_otg_regs.h. ++ ++
                              ++

                              ++ ++ ++ ++ ++
                              ++ + +- ++ + +
                              volatile uint32_t dwc_otg_dev_global_regs::dtknqr3_dthrctl volatile uint32_t dwc_otg_dev_global_regs::dtknqr3_dthrctl
                              +- +-
                              ++
                              ++ ++ ++ ++
                              ++   ++ + +

                              + Device IN Token Queue Read Register-3 (Read Only). +

                              + / Device Thresholding control register (Read/Write) Offset: 830h +

                              +-Definition at line 898 of file dwc_otg_regs.h. +- +-

                              +- +-

                              +-
                              +- ++Definition at line 1112 of file dwc_otg_regs.h. ++ ++
                              ++

                              ++ ++ ++ ++ ++
                              ++ + +- ++ + +
                              volatile uint32_t dwc_otg_dev_global_regs::dtknqr4_fifoemptymsk volatile uint32_t dwc_otg_dev_global_regs::dtknqr4_fifoemptymsk
                              +- +-
                              ++
                              ++ ++ ++ ++
                              ++   ++ + +

                              + Device IN Token Queue Read Register-4 (Read Only). +

                              + / Device IN EPs empty Inr. Mask Register (Read/Write) Offset: 834h +

                              +-Definition at line 902 of file dwc_otg_regs.h. +- +-

                              +- +-

                              +-
                              +- ++Definition at line 1116 of file dwc_otg_regs.h. ++ ++
                              ++

                              ++ ++ ++ ++ ++
                              ++ + +- ++ + +
                              volatile uint32_t dwc_otg_dev_global_regs::deachint volatile uint32_t dwc_otg_dev_global_regs::deachint
                              +- +-
                              ++
                              ++ ++ ++ ++
                              ++   ++ + +

                              + Device Each Endpoint Interrupt Register (Read Only). +

                              + / Offset: 838h +

                              +-Definition at line 905 of file dwc_otg_regs.h. +- +-

                              +- +-

                              +-
                              +- ++Definition at line 1119 of file dwc_otg_regs.h. ++ ++
                              ++

                              ++ ++ ++ ++ ++
                              ++ + +- ++ + +
                              volatile uint32_t dwc_otg_dev_global_regs::deachintmsk volatile uint32_t dwc_otg_dev_global_regs::deachintmsk
                              +- +-
                              ++
                              ++ ++ ++ ++
                              ++   ++ + +

                              + Device Each Endpoint Interrupt mask Register (Read/Write). +

                              + / Offset: 83Ch +

                              +-Definition at line 908 of file dwc_otg_regs.h. +- +-

                              +- +-

                              +-
                              +- ++Definition at line 1122 of file dwc_otg_regs.h. ++ ++
                              ++

                              ++ ++ ++ ++ ++
                              ++ + +- ++ + +
                              volatile uint32_t dwc_otg_dev_global_regs::diepeachintmsk[MAX_EPS_CHANNELS] volatile uint32_t dwc_otg_dev_global_regs::diepeachintmsk[MAX_EPS_CHANNELS]
                              +- +-
                              ++
                              ++ ++ ++ ++
                              ++   ++ + +

                              + Device Each In Endpoint Interrupt mask Register (Read/Write). +

                              + / Offset: 840h +

                              +-Definition at line 911 of file dwc_otg_regs.h. +- +-

                              +- +-

                              +-
                              +- ++Definition at line 1125 of file dwc_otg_regs.h. ++ ++
                              ++

                              ++ ++ ++ ++ ++
                              ++ + +- ++ + +
                              volatile uint32_t dwc_otg_dev_global_regs::doepeachintmsk[MAX_EPS_CHANNELS] volatile uint32_t dwc_otg_dev_global_regs::doepeachintmsk[MAX_EPS_CHANNELS]
                              +- +-
                              ++
                              ++ ++ ++ ++ ++ ++
                              ++   ++ + +

                              + Device Each Out Endpoint Interrupt mask Register (Read/Write). +

                              + / Offset: 880h +

                              +-Definition at line 914 of file dwc_otg_regs.h. +- +-

                              ++Definition at line 1128 of file dwc_otg_regs.h.

                              +

                              The documentation for this struct was generated from the following file: +-
                              Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++
                              Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
                              ++doxygen 1.3.9.1
                              + + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__dev__if.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__dev__if.html 2013-07-26 19:31:22.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__dev__if.html 2013-07-26 19:34:43.000000000 +0000 +@@ -2,22 +2,10 @@ + + DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_dev_if Struct Reference + +- + +- +-
                              +-
                              +-
                              +-
                              +-

                              dwc_otg_dev_if Struct Reference

                              The dwc_otg_dev_if structure contains information needed to manage the DWC_otg controller acting in device mode. ++ ++
                              Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                              ++

                              dwc_otg_dev_if Struct Reference

                              The dwc_otg_dev_if structure contains information needed to manage the DWC_otg controller acting in device mode. + More... +

                              + #include <dwc_otg_regs.h> +@@ -25,118 +13,130 @@ + + + +- ++ + +- +- ++ ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ + +- +- ++ ++ + +- ++ + +- ++ + +- ++ + +- ++ + + +- ++ + +- ++ + + +- ++ + + +- ++ + + +- ++ + +- ++ + + +- ++ + +- ++ + + ++ ++ ++ +

                              Data Fields

                              dwc_otg_device_global_regs_t * dev_global_regs
                              dwc_otg_device_global_regs_t * dev_global_regs
                               Pointer to device Global registers.
                              +-dwc_otg_dev_in_ep_regs_t * in_ep_regs [MAX_EPS_CHANNELS]
                               Pointer to device Global registers.
                              ++dwc_otg_dev_in_ep_regs_t * in_ep_regs [MAX_EPS_CHANNELS]
                               Device Logical IN Endpoint-Specific Registers 900h-AFCh.
                              +-dwc_otg_dev_out_ep_regs_t * out_ep_regs [MAX_EPS_CHANNELS]
                              ++dwc_otg_dev_out_ep_regs_t * out_ep_regs [MAX_EPS_CHANNELS]
                               Device Logical OUT Endpoint-Specific Registers B00h-CFCh.
                              +-uint8_t speed
                              ++uint8_t speed
                               Device Speed 0: Unknown, 1: LS, 2:FS, 3: HS.
                              +-uint8_t num_in_eps
                              ++uint8_t num_in_eps
                               Number # of Tx EP range: 0-15 exept ep0.
                              +-uint8_t num_out_eps
                              ++uint8_t num_out_eps
                               Number # of Rx EP range: 0-15 exept ep 0.
                              +-uint16_t perio_tx_fifo_size [MAX_PERIO_FIFOS]
                              ++uint16_t perio_tx_fifo_size [MAX_PERIO_FIFOS]
                               Size of periodic FIFOs (Bytes).
                              +-uint16_t tx_fifo_size [MAX_TX_FIFOS]
                              ++uint16_t tx_fifo_size [MAX_TX_FIFOS]
                               Size of Tx FIFOs (Bytes).
                              +-uint16_t rx_thr_en
                              ++uint16_t rx_thr_en
                               Thresholding enable flags and length varaiables.
                              +-uint16_t iso_tx_thr_en
                               Thresholding enable flags and length varaiables *.
                              ++uint16_t iso_tx_thr_en
                              +-uint16_t non_iso_tx_thr_en
                              ++uint16_t non_iso_tx_thr_en
                              +-uint16_t rx_thr_length
                              ++uint16_t rx_thr_length
                              +-uint16_t tx_thr_length
                              ++uint16_t tx_thr_length
                              +-dwc_dma_t dma_setup_desc_addr [2]
                              ++dwc_dma_t dma_setup_desc_addr [2]
                               2 descriptors for SETUP packets
                              +-dwc_otg_dev_dma_desc_t * setup_desc_addr [2]
                              ++dwc_otg_dev_dma_desc_t * setup_desc_addr [2]
                              +-dwc_otg_dev_dma_desc_t * psetup
                              ++dwc_otg_dev_dma_desc_t * psetup
                               Pointer to Descriptor with latest SETUP packet.
                              +-uint32_t setup_desc_index
                              ++uint32_t setup_desc_index
                               Index of current SETUP handler descriptor.
                              +-dwc_dma_t dma_in_desc_addr
                              ++dwc_dma_t dma_in_desc_addr
                               Descriptor for Data In or Status In phases.
                              +-dwc_otg_dev_dma_desc_t * in_desc_addr
                              ++dwc_otg_dev_dma_desc_t * in_desc_addr
                              +-dwc_dma_t dma_out_desc_addr
                              ++dwc_dma_t dma_out_desc_addr
                               Descriptor for Data Out or Status Out phases.
                              +-dwc_otg_dev_dma_desc_t * out_desc_addr
                              ++dwc_otg_dev_dma_desc_t * out_desc_addr
                              +-uint32_t spd
                              ++uint32_t spd
                               Setup Packet Detected - if set clear NAK when queueing.
                              ++void * isoc_ep
                               Isoc ep pointer on which incomplete happens.
                              +

                              Detailed Description

                              +-The dwc_otg_dev_if structure contains information needed to manage the DWC_otg controller acting in device mode. ++The dwc_otg_dev_if structure contains information needed to manage the DWC_otg controller acting in device mode. +

                              + It represents the programming view of the device-specific aspects of the controller. +

                              + +

                              +-Definition at line 1554 of file dwc_otg_regs.h.

                              Field Documentation

                              +- +-
                              +-
                              +- ++Definition at line 1779 of file dwc_otg_regs.h.

                              Field Documentation

                              ++

                              ++

                              ++ ++ ++ ++
                              ++ + +- ++ + +
                              dwc_otg_device_global_regs_t* dwc_otg_dev_if::dev_global_regs dwc_otg_device_global_regs_t* dwc_otg_dev_if::dev_global_regs
                              +- +-
                              ++
                              ++ ++ ++ ++ ++ ++
                              ++   ++ + +

                              + Pointer to device Global registers. +

                              +-Device Global Registers starting at offset 800h ++Device Global Registers starting at offset 800h +

                              +-Definition at line 1558 of file dwc_otg_regs.h. +- +-

                              ++Definition at line 1783 of file dwc_otg_regs.h.

                              +
                              The documentation for this struct was generated from the following file: +-
                              Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++
                              Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
                              ++doxygen 1.3.9.1
                              + + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__dev__in__ep__regs.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__dev__in__ep__regs.html 2013-07-26 19:31:22.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__dev__in__ep__regs.html 2013-07-26 19:34:43.000000000 +0000 +@@ -2,22 +2,10 @@ + + DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_dev_in_ep_regs Struct Reference + +- + +- +-
                              +-
                              +-
                              +-
                              +-

                              dwc_otg_dev_in_ep_regs Struct Reference

                              Device Logical IN Endpoint-Specific Registers. ++ ++
                              Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                              ++

                              dwc_otg_dev_in_ep_regs Struct Reference

                              Device Logical IN Endpoint-Specific Registers. + More... +

                              + #include <dwc_otg_regs.h> +@@ -25,30 +13,30 @@ + + + +- ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- ++ +

                              Data Fields

                              volatile uint32_t diepctl
                              volatile uint32_t diepctl
                               Device IN Endpoint Control Register.
                              uint32_t reserved04
                               Device IN Endpoint Control Register.
                              uint32_t reserved04
                               Reserved.
                              volatile uint32_t diepint
                               Reserved.
                              volatile uint32_t diepint
                               Device IN Endpoint Interrupt Register.
                              uint32_t reserved0C
                               Device IN Endpoint Interrupt Register.
                              uint32_t reserved0C
                               Reserved.
                              volatile uint32_t dieptsiz
                               Reserved.
                              volatile uint32_t dieptsiz
                               Device IN Endpoint Transfer Size Register.
                              volatile uint32_t diepdma
                               Device IN Endpoint Transfer Size Register.
                              volatile uint32_t diepdma
                               Device IN Endpoint DMA Address Register.
                              volatile uint32_t dtxfsts
                               Device IN Endpoint DMA Address Register.
                              volatile uint32_t dtxfsts
                               Device IN Endpoint Transmit FIFO Status Register.
                              volatile uint32_t diepdmab
                               Device IN Endpoint Transmit FIFO Status Register.
                              volatile uint32_t diepdmab
                               Device IN Endpoint DMA Buffer Register.
                               Device IN Endpoint DMA Buffer Register.
                              +

                              Detailed Description

                              + Device Logical IN Endpoint-Specific Registers. +@@ -59,163 +47,227 @@ +

                              + +

                              +-Definition at line 1239 of file dwc_otg_regs.h.

                              Field Documentation

                              +- +-
                              +-
                              +- ++Definition at line 1462 of file dwc_otg_regs.h.

                              Field Documentation

                              ++

                              ++

                              ++ ++ ++ ++
                              ++ + +- ++ + +
                              volatile uint32_t dwc_otg_dev_in_ep_regs::diepctl volatile uint32_t dwc_otg_dev_in_ep_regs::diepctl
                              +- +-
                              ++
                              ++ ++ ++ ++
                              ++   ++ + +

                              + Device IN Endpoint Control Register. +

                              + Offset:900h + (ep_num * 20h) + 00h +

                              +-Definition at line 1242 of file dwc_otg_regs.h. +- +-

                              +- +-

                              +-
                              +- ++Definition at line 1465 of file dwc_otg_regs.h. ++ ++
                              ++

                              ++ ++ ++ ++ ++
                              ++ + +- ++ + +
                              uint32_t dwc_otg_dev_in_ep_regs::reserved04 uint32_t dwc_otg_dev_in_ep_regs::reserved04
                              +- +-
                              ++
                              ++ ++ ++ ++
                              ++   ++ + +

                              + Reserved. +

                              + Offset:900h + (ep_num * 20h) + 04h +

                              +-Definition at line 1244 of file dwc_otg_regs.h. +- +-

                              +- +-

                              +-
                              +- ++Definition at line 1467 of file dwc_otg_regs.h. ++ ++
                              ++

                              ++ ++ ++ ++ ++
                              ++ + +- ++ + +
                              volatile uint32_t dwc_otg_dev_in_ep_regs::diepint volatile uint32_t dwc_otg_dev_in_ep_regs::diepint
                              +- +-
                              ++
                              ++ ++ ++ ++
                              ++   ++ + +

                              + Device IN Endpoint Interrupt Register. +

                              + Offset:900h + (ep_num * 20h) + 08h +

                              +-Definition at line 1247 of file dwc_otg_regs.h. +- +-

                              +- +-

                              +-
                              +- ++Definition at line 1470 of file dwc_otg_regs.h. ++ ++
                              ++

                              ++ ++ ++ ++ ++
                              ++ + +- ++ + +
                              uint32_t dwc_otg_dev_in_ep_regs::reserved0C uint32_t dwc_otg_dev_in_ep_regs::reserved0C
                              +- +-
                              ++
                              ++ ++ ++ ++
                              ++   ++ + +

                              + Reserved. +

                              + Offset:900h + (ep_num * 20h) + 0Ch +

                              +-Definition at line 1249 of file dwc_otg_regs.h. +- +-

                              +- +-

                              +-
                              +- ++Definition at line 1472 of file dwc_otg_regs.h. ++ ++
                              ++

                              ++ ++ ++ ++ ++
                              ++ + +- ++ + +
                              volatile uint32_t dwc_otg_dev_in_ep_regs::dieptsiz volatile uint32_t dwc_otg_dev_in_ep_regs::dieptsiz
                              +- +-
                              ++
                              ++ ++ ++ ++
                              ++   ++ + +

                              + Device IN Endpoint Transfer Size Register. +

                              + Offset:900h + (ep_num * 20h) + 10h +

                              +-Definition at line 1252 of file dwc_otg_regs.h. +- +-

                              +- +-

                              +-
                              +- ++Definition at line 1475 of file dwc_otg_regs.h. ++ ++
                              ++

                              ++ ++ ++ ++ ++
                              ++ + +- ++ + +
                              volatile uint32_t dwc_otg_dev_in_ep_regs::diepdma volatile uint32_t dwc_otg_dev_in_ep_regs::diepdma
                              +- +-
                              ++
                              ++ ++ ++ ++
                              ++   ++ + +

                              + Device IN Endpoint DMA Address Register. +

                              + Offset:900h + (ep_num * 20h) + 14h +

                              +-Definition at line 1255 of file dwc_otg_regs.h. +- +-

                              +- +-

                              +-
                              +- ++Definition at line 1478 of file dwc_otg_regs.h. ++ ++
                              ++

                              ++ ++ ++ ++ ++
                              ++ + +- ++ + +
                              volatile uint32_t dwc_otg_dev_in_ep_regs::dtxfsts volatile uint32_t dwc_otg_dev_in_ep_regs::dtxfsts
                              +- +-
                              ++
                              ++ ++ ++ ++
                              ++   ++ + +

                              + Device IN Endpoint Transmit FIFO Status Register. +

                              + Offset:900h + (ep_num * 20h) + 18h +

                              +-Definition at line 1258 of file dwc_otg_regs.h. +- +-

                              +- +-

                              +-
                              +- ++Definition at line 1481 of file dwc_otg_regs.h. ++ ++
                              ++

                              ++ ++ ++ ++ ++
                              ++ + +- ++ + +
                              volatile uint32_t dwc_otg_dev_in_ep_regs::diepdmab volatile uint32_t dwc_otg_dev_in_ep_regs::diepdmab
                              +- +-
                              ++
                              ++ ++ ++ ++ ++ ++
                              ++   ++ + +

                              + Device IN Endpoint DMA Buffer Register. +

                              + Offset:900h + (ep_num * 20h) + 1Ch +

                              +-Definition at line 1261 of file dwc_otg_regs.h. +- +-

                              ++Definition at line 1484 of file dwc_otg_regs.h.

                              +

                              The documentation for this struct was generated from the following file: +-
                              Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++
                              Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
                              ++doxygen 1.3.9.1
                              + + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__dev__out__ep__regs.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__dev__out__ep__regs.html 2013-07-26 19:31:22.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__dev__out__ep__regs.html 2013-07-26 19:34:43.000000000 +0000 +@@ -2,22 +2,10 @@ + + DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_dev_out_ep_regs Struct Reference + +- + +- +-
                              +-
                              +-
                              +-
                              +-

                              dwc_otg_dev_out_ep_regs Struct Reference

                              Device Logical OUT Endpoint-Specific Registers. ++ ++
                              Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                              ++

                              dwc_otg_dev_out_ep_regs Struct Reference

                              Device Logical OUT Endpoint-Specific Registers. + More... +

                              + #include <dwc_otg_regs.h> +@@ -25,30 +13,30 @@ + + + +- ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- ++ +

                              Data Fields

                              volatile uint32_t doepctl
                              volatile uint32_t doepctl
                               Device OUT Endpoint Control Register.
                              volatile uint32_t doepfn
                               Device OUT Endpoint Control Register.
                              uint32_t reserved04
                               Device OUT Endpoint Frame number Register.
                              volatile uint32_t doepint
                               Reserved.
                              volatile uint32_t doepint
                               Device OUT Endpoint Interrupt Register.
                              uint32_t reserved0C
                               Device OUT Endpoint Interrupt Register.
                              uint32_t reserved0C
                               Reserved.
                              volatile uint32_t doeptsiz
                               Reserved.
                              volatile uint32_t doeptsiz
                               Device OUT Endpoint Transfer Size Register.
                              volatile uint32_t doepdma
                               Device OUT Endpoint Transfer Size Register.
                              volatile uint32_t doepdma
                               Device OUT Endpoint DMA Address Register.
                              uint32_t unused
                               Device OUT Endpoint DMA Address Register.
                              uint32_t unused
                               Reserved.
                              uint32_t doepdmab
                               Reserved.
                              uint32_t doepdmab
                               Device OUT Endpoint DMA Buffer Register.
                               Device OUT Endpoint DMA Buffer Register.
                              +

                              Detailed Description

                              + Device Logical OUT Endpoint-Specific Registers. +@@ -59,163 +47,227 @@ +

                              + +

                              +-Definition at line 1274 of file dwc_otg_regs.h.

                              Field Documentation

                              +- +-
                              +-
                              +- ++Definition at line 1497 of file dwc_otg_regs.h.

                              Field Documentation

                              ++

                              ++

                              ++ ++ ++ ++
                              ++ + +- ++ + +
                              volatile uint32_t dwc_otg_dev_out_ep_regs::doepctl volatile uint32_t dwc_otg_dev_out_ep_regs::doepctl
                              +- +-
                              ++
                              ++ ++ ++ ++
                              ++   ++ + +

                              + Device OUT Endpoint Control Register. +

                              + Offset:B00h + (ep_num * 20h) + 00h +

                              +-Definition at line 1277 of file dwc_otg_regs.h. +- +-

                              +- +-

                              +-
                              +- ++Definition at line 1500 of file dwc_otg_regs.h. ++ ++
                              ++

                              ++ ++ ++ ++ ++
                              ++ + +- ++ + +
                              volatile uint32_t dwc_otg_dev_out_ep_regs::doepfn uint32_t dwc_otg_dev_out_ep_regs::reserved04
                              +- +-
                              ++
                              ++ ++ ++ ++
                              ++   ++ + +

                              +-Device OUT Endpoint Frame number Register. ++Reserved. +

                              +-Offset: B00h + (ep_num * 20h) + 04h ++Offset:B00h + (ep_num * 20h) + 04h +

                              +-Definition at line 1280 of file dwc_otg_regs.h. +- +-

                              +- +-

                              +-
                              +- ++Definition at line 1502 of file dwc_otg_regs.h. ++ ++
                              ++

                              ++ ++ ++ ++ ++
                              ++ + +- ++ + +
                              volatile uint32_t dwc_otg_dev_out_ep_regs::doepint volatile uint32_t dwc_otg_dev_out_ep_regs::doepint
                              +- +-
                              ++
                              ++ ++ ++ ++
                              ++   ++ + +

                              + Device OUT Endpoint Interrupt Register. +

                              + Offset:B00h + (ep_num * 20h) + 08h +

                              +-Definition at line 1283 of file dwc_otg_regs.h. +- +-

                              +- +-

                              +-
                              +- ++Definition at line 1505 of file dwc_otg_regs.h. ++ ++
                              ++

                              ++ ++ ++ ++ ++
                              ++ + +- ++ + +
                              uint32_t dwc_otg_dev_out_ep_regs::reserved0C uint32_t dwc_otg_dev_out_ep_regs::reserved0C
                              +- +-
                              ++
                              ++ ++ ++ ++
                              ++   ++ + +

                              + Reserved. +

                              + Offset:B00h + (ep_num * 20h) + 0Ch +

                              +-Definition at line 1285 of file dwc_otg_regs.h. +- +-

                              +- +-

                              +-
                              +- ++Definition at line 1507 of file dwc_otg_regs.h. ++ ++
                              ++

                              ++ ++ ++ ++ ++
                              ++ + +- ++ + +
                              volatile uint32_t dwc_otg_dev_out_ep_regs::doeptsiz volatile uint32_t dwc_otg_dev_out_ep_regs::doeptsiz
                              +- +-
                              ++
                              ++ ++ ++ ++
                              ++   ++ + +

                              + Device OUT Endpoint Transfer Size Register. +

                              + Offset: B00h + (ep_num * 20h) + 10h +

                              +-Definition at line 1288 of file dwc_otg_regs.h. +- +-

                              +- +-

                              +-
                              +- ++Definition at line 1510 of file dwc_otg_regs.h. ++ ++
                              ++

                              ++ ++ ++ ++ ++
                              ++ + +- ++ + +
                              volatile uint32_t dwc_otg_dev_out_ep_regs::doepdma volatile uint32_t dwc_otg_dev_out_ep_regs::doepdma
                              +- +-
                              ++
                              ++ ++ ++ ++
                              ++   ++ + +

                              + Device OUT Endpoint DMA Address Register. +

                              + Offset:B00h + (ep_num * 20h) + 14h +

                              +-Definition at line 1291 of file dwc_otg_regs.h. +- +-

                              +- +-

                              +-
                              +- ++Definition at line 1513 of file dwc_otg_regs.h. ++ ++
                              ++

                              ++ ++ ++ ++ ++
                              ++ + +- ++ + +
                              uint32_t dwc_otg_dev_out_ep_regs::unused uint32_t dwc_otg_dev_out_ep_regs::unused
                              +- +-
                              ++
                              ++ ++ ++ ++
                              ++   ++ + +

                              + Reserved. +

                              + Offset:B00h + * (ep_num * 20h) + 18h +

                              +-Definition at line 1293 of file dwc_otg_regs.h. +- +-

                              +- +-

                              +-
                              +- ++Definition at line 1515 of file dwc_otg_regs.h. ++ ++
                              ++

                              ++ ++ ++ ++ ++
                              ++ + +- ++ + +
                              uint32_t dwc_otg_dev_out_ep_regs::doepdmab uint32_t dwc_otg_dev_out_ep_regs::doepdmab
                              +- +-
                              ++
                              ++ ++ ++ ++ ++ ++
                              ++   ++ + +

                              + Device OUT Endpoint DMA Buffer Register. +

                              + Offset:B00h + (ep_num * 20h) + 1Ch +

                              +-Definition at line 1296 of file dwc_otg_regs.h. +- +-

                              ++Definition at line 1518 of file dwc_otg_regs.h.

                              +

                              The documentation for this struct was generated from the following file: +-
                              Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++
                              Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
                              ++doxygen 1.3.9.1
                              + + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__device.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__device.html 2013-07-26 19:31:22.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__device.html 2013-07-26 19:34:43.000000000 +0000 +@@ -2,22 +2,10 @@ + + DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_device Struct Reference + +- + +- +-
                              +-
                              +-
                              +-
                              +-

                              dwc_otg_device Struct Reference

                              This structure is a wrapper that encapsulates the driver components used to manage a single DWC_otg controller. ++ ++
                              Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                              ++

                              dwc_otg_device Struct Reference

                              This structure is a wrapper that encapsulates the driver components used to manage a single DWC_otg controller. + More... +

                              + #include <dwc_otg_driver.h> +@@ -25,28 +13,23 @@ + + + +- ++ + +- +- ++ ++ + + +- +- +- +- ++ + + +- ++ + + +- ++ + + +

                              Data Fields

                              +-void * base
                              os_dependent os_dep
                               Base address returned from ioremap().
                              +-dwc_otg_core_if_t * core_if
                               Structure containing OS-dependent stuff.
                              ++dwc_otg_core_if_t * core_if
                               Pointer to the core interface structure.
                              +-uint32_t reg_offset
                               Register offset for Diagnostic API.
                              +-dwc_otg_pcd * pcd
                              ++dwc_otg_pcd * pcd
                               Pointer to the PCD structure.
                              +-dwc_otg_hcd * hcd
                              ++dwc_otg_hcd * hcd
                               Pointer to the HCD structure.
                              +-uint8_t common_irq_installed
                              ++uint8_t common_irq_installed
                               Flag to indicate whether the common IRQ handler is installed.
                              +@@ -55,10 +38,38 @@ +

                              + +

                              +-Definition at line 56 of file dwc_otg_driver.h.

                              The documentation for this struct was generated from the following file:
                                ++Definition at line 51 of file dwc_otg_driver.h.

                                Field Documentation

                                ++

                                ++ ++ ++ ++ ++
                                ++ ++ ++ ++ ++
                                struct os_dependent dwc_otg_device::os_dep
                                ++
                                ++ ++ ++ ++ ++ ++
                                ++   ++ ++ ++

                                ++Structure containing OS-dependent stuff. ++

                                ++KEEP THIS STRUCT AT THE VERY BEGINNING OF THE DEVICE STRUCT. OSes such as FreeBSD and NetBSD require this. ++

                                ++Definition at line 55 of file dwc_otg_driver.h.

                                ++

                                The documentation for this struct was generated from the following file: +-
                                Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++
                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
                                ++doxygen 1.3.9.1
                                + + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__driver__module__params.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__driver__module__params.html 2013-07-26 19:31:22.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,146 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_driver_module_params Struct Reference +- +- +- +- +-
                                +-
                                +-
                                +-
                                +-

                                dwc_otg_driver_module_params Struct Reference

                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-

                                Data Fields

                                +-int32_t opt
                                +-int32_t otg_cap
                                +-int32_t dma_enable
                                +-int32_t dma_desc_enable
                                +-int32_t dma_burst_size
                                +-int32_t speed
                                +-int32_t host_support_fs_ls_low_power
                                +-int32_t host_ls_low_power_phy_clk
                                +-int32_t enable_dynamic_fifo
                                +-int32_t data_fifo_size
                                +-int32_t dev_rx_fifo_size
                                +-int32_t dev_nperio_tx_fifo_size
                                +-uint32_t dev_perio_tx_fifo_size [MAX_PERIO_FIFOS]
                                +-int32_t host_rx_fifo_size
                                +-int32_t host_nperio_tx_fifo_size
                                +-int32_t host_perio_tx_fifo_size
                                +-int32_t max_transfer_size
                                +-int32_t max_packet_count
                                +-int32_t host_channels
                                +-int32_t dev_endpoints
                                +-int32_t phy_type
                                +-int32_t phy_utmi_width
                                +-int32_t phy_ulpi_ddr
                                +-int32_t phy_ulpi_ext_vbus
                                +-int32_t i2c_enable
                                +-int32_t ulpi_fs_ls
                                +-int32_t ts_dline
                                +-int32_t en_multiple_tx_fifo
                                +-uint32_t dev_tx_fifo_size [MAX_TX_FIFOS]
                                +-uint32_t thr_ctl
                                +-uint32_t tx_thr_length
                                +-uint32_t rx_thr_length
                                +-int32_t pti_enable
                                +-int32_t mpi_enable
                                +-int32_t lpm_enable
                                +-int32_t ic_usb_cap
                                +-int32_t ahb_thr_ratio
                                +-

                                Detailed Description

                                +- +-

                                +- +-

                                +-Definition at line 120 of file dwc_otg_driver.c.

                                The documentation for this struct was generated from the following file: +-
                                Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.4.7
                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__hc__regs.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__hc__regs.html 2013-07-26 19:31:22.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__hc__regs.html 2013-07-26 19:34:43.000000000 +0000 +@@ -2,22 +2,10 @@ + + DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_hc_regs Struct Reference + +- + +- +-
                                +-
                                +-
                                +-
                                +-

                                dwc_otg_hc_regs Struct Reference

                                Host Channel Specific Registers. ++ ++
                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                ++

                                dwc_otg_hc_regs Struct Reference

                                Host Channel Specific Registers. + More... +

                                + #include <dwc_otg_regs.h> +@@ -25,30 +13,30 @@ + + + +- ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- ++ + +- ++ +

                                Data Fields

                                volatile uint32_t hcchar
                                volatile uint32_t hcchar
                                 Host Channel 0 Characteristic Register.
                                volatile uint32_t hcsplt
                                 Host Channel 0 Characteristic Register.
                                volatile uint32_t hcsplt
                                 Host Channel 0 Split Control Register.
                                volatile uint32_t hcint
                                 Host Channel 0 Split Control Register.
                                volatile uint32_t hcint
                                 Host Channel 0 Interrupt Register.
                                volatile uint32_t hcintmsk
                                 Host Channel 0 Interrupt Register.
                                volatile uint32_t hcintmsk
                                 Host Channel 0 Interrupt Mask Register.
                                volatile uint32_t hctsiz
                                 Host Channel 0 Interrupt Mask Register.
                                volatile uint32_t hctsiz
                                 Host Channel 0 Transfer Size Register.
                                volatile uint32_t hcdma
                                 Host Channel 0 Transfer Size Register.
                                volatile uint32_t hcdma
                                 Host Channel 0 DMA Address Register.
                                +-volatile uint32_t reserved
                                 Host Channel 0 DMA Address Register.
                                ++volatile uint32_t reserved
                                volatile uint32_t hcdmab
                                volatile uint32_t hcdmab
                                 Host Channel 0 DMA Buffer Address Register.
                                 Host Channel 0 DMA Buffer Address Register.
                                +

                                Detailed Description

                                + Host Channel Specific Registers. +@@ -57,144 +45,200 @@ +

                                + +

                                +-Definition at line 1838 of file dwc_otg_regs.h.

                                Field Documentation

                                +- +-
                                +-
                                +- ++Definition at line 2068 of file dwc_otg_regs.h.

                                Field Documentation

                                ++

                                ++

                                ++ ++ ++ ++
                                ++ + +- ++ + +
                                volatile uint32_t dwc_otg_hc_regs::hcchar volatile uint32_t dwc_otg_hc_regs::hcchar
                                +- +-
                                ++
                                ++ ++ ++ ++
                                ++   ++ + +

                                + Host Channel 0 Characteristic Register. +

                                + Offset: 500h + (chan_num * 20h) + 00h +

                                +-Definition at line 1841 of file dwc_otg_regs.h. +- +-

                                +- +-

                                +-
                                +- ++Definition at line 2070 of file dwc_otg_regs.h. ++ ++
                                ++

                                ++ ++ ++ ++ ++
                                ++ + +- ++ + +
                                volatile uint32_t dwc_otg_hc_regs::hcsplt volatile uint32_t dwc_otg_hc_regs::hcsplt
                                +- +-
                                ++
                                ++ ++ ++ ++
                                ++   ++ + +

                                + Host Channel 0 Split Control Register. +

                                + Offset: 500h + (chan_num * 20h) + 04h +

                                +-Definition at line 1843 of file dwc_otg_regs.h. +- +-

                                +- +-

                                +-
                                +- ++Definition at line 2072 of file dwc_otg_regs.h. ++ ++
                                ++

                                ++ ++ ++ ++ ++
                                ++ + +- ++ + +
                                volatile uint32_t dwc_otg_hc_regs::hcint volatile uint32_t dwc_otg_hc_regs::hcint
                                +- +-
                                ++
                                ++ ++ ++ ++
                                ++   ++ + +

                                + Host Channel 0 Interrupt Register. +

                                + Offset: 500h + (chan_num * 20h) + 08h +

                                +-Definition at line 1845 of file dwc_otg_regs.h. +- +-

                                +- +-

                                +-
                                +- ++Definition at line 2074 of file dwc_otg_regs.h. ++ ++
                                ++

                                ++ ++ ++ ++ ++
                                ++ + +- ++ + +
                                volatile uint32_t dwc_otg_hc_regs::hcintmsk volatile uint32_t dwc_otg_hc_regs::hcintmsk
                                +- +-
                                ++
                                ++ ++ ++ ++
                                ++   ++ + +

                                + Host Channel 0 Interrupt Mask Register. +

                                + Offset: 500h + (chan_num * 20h) + 0Ch +

                                +-Definition at line 1847 of file dwc_otg_regs.h. +- +-

                                +- +-

                                +-
                                +- ++Definition at line 2076 of file dwc_otg_regs.h. ++ ++
                                ++

                                ++ ++ ++ ++ ++
                                ++ + +- ++ + +
                                volatile uint32_t dwc_otg_hc_regs::hctsiz volatile uint32_t dwc_otg_hc_regs::hctsiz
                                +- +-
                                ++
                                ++ ++ ++ ++
                                ++   ++ + +

                                + Host Channel 0 Transfer Size Register. +

                                + Offset: 500h + (chan_num * 20h) + 10h +

                                +-Definition at line 1849 of file dwc_otg_regs.h. +- +-

                                +- +-

                                +-
                                +- ++Definition at line 2078 of file dwc_otg_regs.h. ++ ++
                                ++

                                ++ ++ ++ ++ ++
                                ++ + +- ++ + +
                                volatile uint32_t dwc_otg_hc_regs::hcdma volatile uint32_t dwc_otg_hc_regs::hcdma
                                +- +-
                                ++
                                ++ ++ ++ ++
                                ++   ++ + +

                                + Host Channel 0 DMA Address Register. +

                                + Offset: 500h + (chan_num * 20h) + 14h +

                                +-Definition at line 1851 of file dwc_otg_regs.h. +- +-

                                +- +-

                                +-
                                +- ++Definition at line 2080 of file dwc_otg_regs.h. ++ ++
                                ++

                                ++ ++ ++ ++ ++
                                ++ + +- ++ + +
                                volatile uint32_t dwc_otg_hc_regs::hcdmab volatile uint32_t dwc_otg_hc_regs::hcdmab
                                +- +-
                                ++
                                ++ ++ ++ ++ ++ ++
                                ++   ++ + +

                                + Host Channel 0 DMA Buffer Address Register. +

                                + Offset: 500h + (chan_num * 20h) + 1Ch +

                                +-Definition at line 1854 of file dwc_otg_regs.h. +- +-

                                ++Definition at line 2083 of file dwc_otg_regs.h.

                                +

                                The documentation for this struct was generated from the following file: +-
                                Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++
                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
                                ++doxygen 1.3.9.1
                                + + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__hcd.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__hcd.html 2013-07-26 19:31:22.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__hcd.html 2013-07-26 19:34:43.000000000 +0000 +@@ -2,22 +2,10 @@ + + DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_hcd Struct Reference + +- + +- +-
                                +-
                                +-
                                +-
                                +-

                                dwc_otg_hcd Struct Reference

                                This structure holds the state of the HCD, including the non-periodic and periodic schedules. ++ ++
                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                ++

                                dwc_otg_hcd Struct Reference

                                This structure holds the state of the HCD, including the non-periodic and periodic schedules. + More... +

                                + #include <dwc_otg_hcd.h> +@@ -25,353 +13,591 @@ + + + +- ++ ++ ++ ++ + + +- ++ + + +- ++ + + +- ++ ++ ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- ++ + +- ++ + +- +- ++ ++ + +- ++ + + +- ++ + + +- +- +- +- +

                                Data Fields

                                +-dwc_otg_core_if_t * core_if
                                ++dwc_otg_device * otg_dev
                                 The DWC otg device pointer.
                                ++dwc_otg_core_if_t * core_if
                                 DWC OTG Core Interface Layer.
                                +-dwc_otg_hcd_function_ops * fops
                                ++dwc_otg_hcd_function_ops * fops
                                 Function HCD driver callbacks.
                                +-dwc_otg_hcd::dwc_otg_hcd_internal_flags flags
                                ++dwc_otg_hcd::dwc_otg_hcd_internal_flags flags
                                 Internal DWC HCD Flags.
                                dwc_list_link_t non_periodic_sched_inactive
                                dwc_list_link_t non_periodic_sched_inactive
                                 Inactive items in the non-periodic schedule.
                                dwc_list_link_t non_periodic_sched_active
                                 Inactive items in the non-periodic schedule.
                                dwc_list_link_t non_periodic_sched_active
                                 Active items in the non-periodic schedule.
                                dwc_list_link_t * non_periodic_qh_ptr
                                 Active items in the non-periodic schedule.
                                +-dwc_list_link_t * non_periodic_qh_ptr
                                 Pointer to the next Queue Head to process in the active non-periodic schedule.
                                dwc_list_link_t periodic_sched_inactive
                                 Pointer to the next Queue Head to process in the active non-periodic schedule.
                                dwc_list_link_t periodic_sched_inactive
                                 Inactive items in the periodic schedule.
                                dwc_list_link_t periodic_sched_ready
                                 Inactive items in the periodic schedule.
                                dwc_list_link_t periodic_sched_ready
                                 List of periodic QHs that are ready for execution in the next frame, but have not yet been assigned to host channels.
                                dwc_list_link_t periodic_sched_assigned
                                 List of periodic QHs that are ready for execution in the next frame, but have not yet been assigned to host channels.
                                dwc_list_link_t periodic_sched_assigned
                                 List of periodic QHs to be executed in the next frame that are assigned to host channels.
                                dwc_list_link_t periodic_sched_queued
                                 List of periodic QHs to be executed in the next frame that are assigned to host channels.
                                dwc_list_link_t periodic_sched_queued
                                 List of periodic QHs that have been queued for execution.
                                uint16_t periodic_usecs
                                 List of periodic QHs that have been queued for execution.
                                uint16_t periodic_usecs
                                 Total bandwidth claimed so far for periodic transfers.
                                uint16_t frame_number
                                 Total bandwidth claimed so far for periodic transfers.
                                uint16_t frame_number
                                 Frame number read from the core at SOF.
                                uint16_t periodic_qh_count
                                 Frame number read from the core at SOF.
                                hc_list free_hc_list
                                 Count of periodic QHs, if using several eps.
                                hc_list free_hc_list
                                 Free host channels in the controller.
                                int periodic_channels
                                 Free host channels in the controller.
                                int periodic_channels
                                 Number of host channels assigned to periodic transfers.
                                +-int non_periodic_channels
                                 Number of host channels assigned to periodic transfers.
                                int non_periodic_channels
                                 Number of host channels assigned to non-periodic transfers.
                                dwc_hc * hc_ptr_array [MAX_EPS_CHANNELS]
                                 Number of host channels assigned to non-periodic transfers.
                                dwc_hc * hc_ptr_array [MAX_EPS_CHANNELS]
                                 Array of pointers to the host channel descriptors.
                                uint8_t * status_buf
                                 Array of pointers to the host channel descriptors.
                                uint8_t * status_buf
                                 Buffer to use for any data received during the status phase of a control transfer.
                                +-dma_addr_t status_buf_dma
                                 Buffer to use for any data received during the status phase of a control transfer.
                                dma_addr_t status_buf_dma
                                 DMA address for status_buf.
                                dwc_timer_t * conn_timer
                                 DMA address for status_buf.
                                dwc_timer_t * conn_timer
                                 Connection timer.
                                +-dwc_tasklet_t * reset_tasklet
                                 Connection timer.
                                ++dwc_tasklet_t * reset_tasklet
                                +-dwc_spinlock_t * lock
                                ++dwc_spinlock_t * lock
                                +-void * priv
                                void * priv
                                 Private data that could be used by OS wrapper.
                                +-uint8_t otg_port
                                 Private data that could be used by OS wrapper.
                                ++uint8_t otg_port
                                +-uint32_t * frame_list
                                ++uint32_t * frame_list
                                 Frame List.
                                +-dma_addr_t frame_list_dma
                                ++dma_addr_t frame_list_dma
                                 Frame List DMA address.

                                Data Structures

                                union  dwc_otg_hcd_internal_flags
                                 Internal DWC HCD Flags. More...
                                +

                                Detailed Description

                                + This structure holds the state of the HCD, including the non-periodic and periodic schedules. +

                                + +

                                +-Definition at line 372 of file dwc_otg_hcd.h.

                                Field Documentation

                                +- +-
                                +-
                                +- ++Definition at line 373 of file dwc_otg_hcd.h.

                                Field Documentation

                                ++

                                ++

                                ++ ++ ++ ++
                                ++ + +- ++ + +
                                dwc_list_link_t dwc_otg_hcd::non_periodic_sched_inactive dwc_list_link_t dwc_otg_hcd::non_periodic_sched_inactive
                                +- +-
                                ++
                                ++ ++ ++ ++
                                ++   ++ + +

                                + Inactive items in the non-periodic schedule. +

                                +-This is a list of Queue Heads. Transfers associated with these Queue Heads are not currently assigned to a host channel. ++This is a list of Queue Heads. Transfers associated with these Queue Heads are not currently assigned to a host channel. +

                                +-Definition at line 399 of file dwc_otg_hcd.h. +- +-

                                +- +-

                                +-
                                +- ++Definition at line 402 of file dwc_otg_hcd.h. ++ ++
                                ++

                                ++ ++ ++ ++ ++
                                ++ + +- ++ + +
                                dwc_list_link_t dwc_otg_hcd::non_periodic_sched_active dwc_list_link_t dwc_otg_hcd::non_periodic_sched_active
                                +- +-
                                ++
                                ++ ++ ++ ++ ++ ++
                                ++   ++ + +

                                + Active items in the non-periodic schedule. +

                                +-This is a list of Queue Heads. Transfers associated with these Queue Heads are currently assigned to a host channel. ++This is a list of Queue Heads. Transfers associated with these Queue Heads are currently assigned to a host channel. ++

                                ++Definition at line 409 of file dwc_otg_hcd.h.

                                ++

                                ++ ++ ++ ++ ++
                                ++ ++ ++ ++ ++
                                dwc_list_link_t* dwc_otg_hcd::non_periodic_qh_ptr
                                ++
                                ++ ++ ++ ++
                                ++   ++ ++ ++

                                ++Pointer to the next Queue Head to process in the active non-periodic schedule. ++

                                ++ +

                                +-Definition at line 406 of file dwc_otg_hcd.h. +- +-

                                +- +-

                                +-
                                +- ++Definition at line 415 of file dwc_otg_hcd.h. ++ ++
                                ++

                                ++ ++ ++ ++ ++
                                ++ + +- ++ + +
                                dwc_list_link_t dwc_otg_hcd::periodic_sched_inactive dwc_list_link_t dwc_otg_hcd::periodic_sched_inactive
                                +- +-
                                ++
                                ++ ++ ++ ++
                                ++   ++ + +

                                + Inactive items in the periodic schedule. +

                                + This is a list of QHs for periodic transfers that are _not_ scheduled for the next frame. Each QH in the list has an interval counter that determines when it needs to be scheduled for execution. This scheduling mechanism allows only a simple calculation for periodic bandwidth used (i.e. must assume that all periodic transfers may need to execute in the same frame). However, it greatly simplifies scheduling and should be sufficient for the vast majority of OTG hosts, which need to connect to a small number of peripherals at one time.

                                +-Items move from this list to periodic_sched_ready when the QH interval counter is 0 at SOF. ++Items move from this list to periodic_sched_ready when the QH interval counter is 0 at SOF. +

                                +-Definition at line 428 of file dwc_otg_hcd.h. +- +-

                                +- +-

                                +-
                                +- ++Definition at line 431 of file dwc_otg_hcd.h. ++ ++
                                ++

                                ++ ++ ++ ++ ++
                                ++ + +- ++ + +
                                dwc_list_link_t dwc_otg_hcd::periodic_sched_ready dwc_list_link_t dwc_otg_hcd::periodic_sched_ready
                                +- +-
                                ++
                                ++ ++ ++ ++
                                ++   ++ + +

                                + List of periodic QHs that are ready for execution in the next frame, but have not yet been assigned to host channels. +

                                +-Items move from this list to periodic_sched_assigned as host channels become available during the current frame. ++Items move from this list to periodic_sched_assigned as host channels become available during the current frame. +

                                +-Definition at line 437 of file dwc_otg_hcd.h. +- +-

                                +- +-

                                +-
                                +- ++Definition at line 440 of file dwc_otg_hcd.h. ++ ++
                                ++

                                ++ ++ ++ ++ ++
                                ++ + +- ++ + +
                                dwc_list_link_t dwc_otg_hcd::periodic_sched_assigned dwc_list_link_t dwc_otg_hcd::periodic_sched_assigned
                                +- +-
                                ++
                                ++ ++ ++ ++
                                ++   ++ + +

                                + List of periodic QHs to be executed in the next frame that are assigned to host channels. +

                                +-Items move from this list to periodic_sched_queued as the transactions for the QH are queued to the DWC_otg controller. ++Items move from this list to periodic_sched_queued as the transactions for the QH are queued to the DWC_otg controller. +

                                +-Definition at line 446 of file dwc_otg_hcd.h. +- +-

                                +- +-

                                +-
                                +- ++Definition at line 449 of file dwc_otg_hcd.h. ++ ++
                                ++

                                ++ ++ ++ ++ ++
                                ++ + +- ++ + +
                                dwc_list_link_t dwc_otg_hcd::periodic_sched_queued dwc_list_link_t dwc_otg_hcd::periodic_sched_queued
                                +- +-
                                ++
                                ++ ++ ++ ++
                                ++   ++ + +

                                + List of periodic QHs that have been queued for execution. +

                                +-Items move from this list to either periodic_sched_inactive or periodic_sched_ready when the channel associated with the transfer is released. If the interval for the QH is 1, the item moves to periodic_sched_ready because it must be rescheduled for the next frame. Otherwise, the item moves to periodic_sched_inactive. ++Items move from this list to either periodic_sched_inactive or periodic_sched_ready when the channel associated with the transfer is released. If the interval for the QH is 1, the item moves to periodic_sched_ready because it must be rescheduled for the next frame. Otherwise, the item moves to periodic_sched_inactive. +

                                +-Definition at line 457 of file dwc_otg_hcd.h. +- +-

                                +- +-

                                +-
                                +- ++Definition at line 460 of file dwc_otg_hcd.h. ++ ++
                                ++

                                ++ ++ ++ ++ ++
                                ++ + +- ++ + +
                                uint16_t dwc_otg_hcd::periodic_usecs uint16_t dwc_otg_hcd::periodic_usecs
                                +- +-
                                ++
                                ++ ++ ++ ++
                                ++   ++ + +

                                + Total bandwidth claimed so far for periodic transfers. +

                                +-This value is in microseconds per (micro)frame. The assumption is that all periodic transfers may occur in the same (micro)frame. ++This value is in microseconds per (micro)frame. The assumption is that all periodic transfers may occur in the same (micro)frame. +

                                +-Definition at line 464 of file dwc_otg_hcd.h. +- +-

                                +- +-

                                +-
                                +- ++Definition at line 467 of file dwc_otg_hcd.h. ++ ++
                                ++

                                ++ ++ ++ ++ ++
                                ++ + +- ++ + +
                                uint16_t dwc_otg_hcd::frame_number uint16_t dwc_otg_hcd::frame_number
                                +- +-
                                ++
                                ++ ++ ++ ++
                                ++   ++ + +

                                + Frame number read from the core at SOF. +

                                +-The value ranges from 0 to DWC_HFNUM_MAX_FRNUM. ++The value ranges from 0 to DWC_HFNUM_MAX_FRNUM. +

                                +-Definition at line 470 of file dwc_otg_hcd.h. +- +-

                                +- +-

                                +-
                                +- ++Definition at line 473 of file dwc_otg_hcd.h. ++ ++
                                ++

                                ++ ++ ++ ++ ++
                                ++ + +- ++ + +
                                struct hc_list dwc_otg_hcd::free_hc_list uint16_t dwc_otg_hcd::periodic_qh_count
                                +- +-
                                ++
                                ++ ++ ++ ++ ++ ++
                                ++   ++ ++ ++

                                ++Count of periodic QHs, if using several eps. ++

                                ++For SOF enable/disable. ++

                                ++Definition at line 478 of file dwc_otg_hcd.h.

                                ++

                                ++ ++ ++ ++ ++
                                ++ ++ ++ ++ ++
                                struct hc_list dwc_otg_hcd::free_hc_list
                                ++
                                ++ ++ ++ ++
                                ++   ++ + +

                                + Free host channels in the controller. +

                                +-This is a list of dwc_hc_t items. ++This is a list of dwc_hc_t items. +

                                +-Definition at line 476 of file dwc_otg_hcd.h. +- +-

                                +- +-

                                +-
                                +- ++Definition at line 484 of file dwc_otg_hcd.h. ++ ++
                                ++

                                ++ ++ ++ ++ ++
                                ++ + +- ++ + +
                                int dwc_otg_hcd::periodic_channels int dwc_otg_hcd::periodic_channels
                                +- +-
                                ++
                                ++ ++ ++ ++ ++ ++
                                ++   ++ + +

                                + Number of host channels assigned to periodic transfers. +

                                +-Currently assuming that there is a dedicated host channel for each periodic transaction and at least one host channel available for non-periodic transactions. ++Currently assuming that there is a dedicated host channel for each periodic transaction and at least one host channel available for non-periodic transactions. ++

                                ++Definition at line 491 of file dwc_otg_hcd.h.

                                ++

                                ++ ++ ++ ++ ++
                                ++ ++ ++ ++ ++
                                int dwc_otg_hcd::non_periodic_channels
                                ++
                                ++ ++ ++ ++
                                ++   ++ ++ ++

                                ++Number of host channels assigned to non-periodic transfers. +

                                +-Definition at line 483 of file dwc_otg_hcd.h. +- +-

                                +- +-

                                +-
                                +- ++ ++

                                ++Definition at line 496 of file dwc_otg_hcd.h. ++ ++

                                ++

                                ++ ++ ++ ++ ++
                                ++ + +- ++ + +
                                struct dwc_hc* dwc_otg_hcd::hc_ptr_array[MAX_EPS_CHANNELS] struct dwc_hc* dwc_otg_hcd::hc_ptr_array[MAX_EPS_CHANNELS]
                                +- +-
                                ++
                                ++ ++ ++ ++
                                ++   ++ + +

                                + Array of pointers to the host channel descriptors. +

                                +-Allows accessing a host channel descriptor given the host channel number. This is useful in interrupt handlers. ++Allows accessing a host channel descriptor given the host channel number. This is useful in interrupt handlers. +

                                +-Definition at line 495 of file dwc_otg_hcd.h. +- +-

                                +- +-

                                +-
                                +- ++Definition at line 503 of file dwc_otg_hcd.h. ++ ++
                                ++

                                ++ ++ ++ ++ ++
                                ++ + +- ++ + +
                                uint8_t* dwc_otg_hcd::status_buf uint8_t* dwc_otg_hcd::status_buf
                                +- +-
                                ++
                                ++ ++ ++ ++
                                ++   ++ + +

                                + Buffer to use for any data received during the status phase of a control transfer. +

                                +-Normally no data is transferred during the status phase. This buffer is used as a bit bucket. ++Normally no data is transferred during the status phase. This buffer is used as a bit bucket. +

                                +-Definition at line 502 of file dwc_otg_hcd.h. +- +-

                                +- +-

                                +-
                                +- ++Definition at line 510 of file dwc_otg_hcd.h. ++ ++
                                ++

                                ++ ++ ++ ++ ++
                                ++ + +- ++ + +
                                dwc_timer_t* dwc_otg_hcd::conn_timer dma_addr_t dwc_otg_hcd::status_buf_dma
                                +- +-
                                ++
                                ++ ++ ++ ++ ++ ++
                                ++   ++ ++ ++

                                ++DMA address for status_buf. ++

                                ++ ++

                                ++Definition at line 515 of file dwc_otg_hcd.h.

                                ++

                                ++ ++ ++ ++ ++
                                ++ ++ ++ ++ ++
                                dwc_timer_t* dwc_otg_hcd::conn_timer
                                ++
                                ++ ++ ++ ++ ++ ++
                                ++   ++ + +

                                + Connection timer. +

                                +-An OTG host must display a message if the device does not connect. Started when the VBus power is turned on via sysfs attribute "buspower". ++An OTG host must display a message if the device does not connect. Started when the VBus power is turned on via sysfs attribute "buspower". +

                                +-Definition at line 515 of file dwc_otg_hcd.h. +- +-

                                ++Definition at line 523 of file dwc_otg_hcd.h.

                                ++

                                ++ ++ ++ ++ ++
                                ++ ++ ++ ++ ++
                                void* dwc_otg_hcd::priv
                                ++
                                ++ ++ ++ ++ ++ ++
                                ++   ++ ++ ++

                                ++Private data that could be used by OS wrapper. ++

                                ++ ++

                                ++Definition at line 534 of file dwc_otg_hcd.h.

                                +

                                The documentation for this struct was generated from the following file: +-
                                Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++
                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
                                ++doxygen 1.3.9.1
                                + + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__hcd__function__ops.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__hcd__function__ops.html 2013-07-26 19:31:22.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,53 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_hcd_function_ops Struct Reference +- +- +- +- +-
                                +-
                                +-
                                +-
                                +-

                                dwc_otg_hcd_function_ops Struct Reference

                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-

                                Data Fields

                                +-dwc_otg_hcd_start_cb_t start
                                +-dwc_otg_hcd_disconnect_cb_t disconnect
                                +-dwc_otg_hcd_hub_info_from_urb_cb_t hub_info
                                +-dwc_otg_hcd_speed_from_urb_cb_t speed
                                +-dwc_otg_hcd_complete_urb_cb_t complete
                                +-dwc_otg_hcd_get_b_hnp_enable get_b_hnp_enable
                                +-

                                Detailed Description

                                +- +-

                                +- +-

                                +-Definition at line 76 of file dwc_otg_hcd_if.h.

                                The documentation for this struct was generated from the following file: +-
                                Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.4.7
                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__hcd__iso__packet__desc.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__hcd__iso__packet__desc.html 2013-07-26 19:31:22.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,47 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_hcd_iso_packet_desc Struct Reference +- +- +- +- +-
                                +-
                                +-
                                +-
                                +-

                                dwc_otg_hcd_iso_packet_desc Struct Reference

                                +- +- +- +- +- +- +- +- +- +- +-

                                Data Fields

                                +-uint32_t offset
                                +-uint32_t length
                                +-uint32_t actual_length
                                +-uint32_t status
                                +-

                                Detailed Description

                                +- +-

                                +- +-

                                +-Definition at line 63 of file dwc_otg_hcd.h.

                                The documentation for this struct was generated from the following file: +-
                                Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.4.7
                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__hcd__pipe__info.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__hcd__pipe__info.html 2013-07-26 19:31:22.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,50 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_hcd_pipe_info Struct Reference +- +- +- +- +-
                                +-
                                +-
                                +-
                                +-

                                dwc_otg_hcd_pipe_info Struct Reference

                                +- +- +- +- +- +- +- +- +- +- +- +- +-

                                Data Fields

                                +-uint8_t dev_addr
                                +-uint8_t ep_num
                                +-uint8_t pipe_type
                                +-uint8_t pipe_dir
                                +-uint16_t mps
                                +-

                                Detailed Description

                                +- +-

                                +- +-

                                +-Definition at line 55 of file dwc_otg_hcd.h.

                                The documentation for this struct was generated from the following file: +-
                                Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.4.7
                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__hcd__urb.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__hcd__urb.html 2013-07-26 19:31:22.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,80 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_hcd_urb Struct Reference +- +- +- +- +-
                                +-
                                +-
                                +-
                                +-

                                dwc_otg_hcd_urb Struct Reference

                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-

                                Data Fields

                                +-void * priv
                                +-dwc_otg_qtd * qtd
                                +-void * buf
                                +-dwc_dma_t dma
                                +-void * setup_packet
                                +-dwc_dma_t setup_dma
                                +-uint32_t length
                                +-uint32_t actual_length
                                +-uint32_t status
                                +-uint32_t error_count
                                +-uint32_t packet_count
                                +-uint32_t flags
                                +-uint16_t interval
                                +-dwc_otg_hcd_pipe_info pipe_info
                                +-dwc_otg_hcd_iso_packet_desc iso_descs [0]
                                +-

                                Detailed Description

                                +- +-

                                +- +-

                                +-Definition at line 72 of file dwc_otg_hcd.h.

                                The documentation for this struct was generated from the following file: +-
                                Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.4.7
                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__host__dma__desc.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__host__dma__desc.html 2013-07-26 19:31:22.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__host__dma__desc.html 2013-07-26 19:34:43.000000000 +0000 +@@ -2,22 +2,10 @@ + + DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_host_dma_desc Struct Reference + +- + +- +-
                                +-
                                +-
                                +-
                                +-

                                dwc_otg_host_dma_desc Struct Reference

                                Host-mode DMA Descriptor structure. ++ ++
                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                ++

                                dwc_otg_host_dma_desc Struct Reference

                                Host-mode DMA Descriptor structure. + More... +

                                + #include <dwc_otg_regs.h> +@@ -25,12 +13,12 @@ + + + +- ++ + + +- ++ + + +

                                Data Fields

                                +-host_dma_desc_sts_t status
                                ++host_dma_desc_sts_t status
                                 DMA Descriptor status quadlet.
                                +-uint32_t buf
                                ++uint32_t buf
                                 DMA Descriptor data buffer pointer.
                                +@@ -41,10 +29,10 @@ +

                                + +

                                +-Definition at line 2166 of file dwc_otg_regs.h.

                                The documentation for this struct was generated from the following file:
                                  ++Definition at line 2384 of file dwc_otg_regs.h.
                                  The documentation for this struct was generated from the following file: +-
                                  Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++
                                  Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
                                  ++doxygen 1.3.9.1
                                  + + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__host__global__regs.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__host__global__regs.html 2013-07-26 19:31:22.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__host__global__regs.html 2013-07-26 19:34:43.000000000 +0000 +@@ -2,22 +2,10 @@ + + DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_host_global_regs Struct Reference + +- + +- +-
                                  +-
                                  +-
                                  +-
                                  +-

                                  dwc_otg_host_global_regs Struct Reference

                                  The Host Global Registers structure defines the size and relative field offsets for the Host Mode Global Registers. ++ ++
                                  Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                  ++

                                  dwc_otg_host_global_regs Struct Reference

                                  The Host Global Registers structure defines the size and relative field offsets for the Host Mode Global Registers. + More... +

                                  + #include <dwc_otg_regs.h> +@@ -25,30 +13,30 @@ + + + +- ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- ++ +

                                  Data Fields

                                  volatile uint32_t hcfg
                                  volatile uint32_t hcfg
                                   Host Configuration Register.
                                  volatile uint32_t hfir
                                   Host Configuration Register.
                                  volatile uint32_t hfir
                                   Host Frame Interval Register.
                                  volatile uint32_t hfnum
                                   Host Frame Interval Register.
                                  volatile uint32_t hfnum
                                   Host Frame Number / Frame Remaining Register.
                                  uint32_t reserved40C
                                   Host Frame Number / Frame Remaining Register.
                                  uint32_t reserved40C
                                   Reserved.
                                  volatile uint32_t hptxsts
                                   Reserved.
                                  volatile uint32_t hptxsts
                                   Host Periodic Transmit FIFO/ Queue Status Register.
                                  volatile uint32_t haint
                                   Host Periodic Transmit FIFO/ Queue Status Register.
                                  volatile uint32_t haint
                                   Host All Channels Interrupt Register.
                                  volatile uint32_t haintmsk
                                   Host All Channels Interrupt Register.
                                  volatile uint32_t haintmsk
                                   Host All Channels Interrupt Mask Register.
                                  volatile uint32_t hflbaddr
                                   Host All Channels Interrupt Mask Register.
                                  volatile uint32_t hflbaddr
                                   Host Frame List Base Address Register .
                                   Host Frame List Base Address Register .
                                  +

                                  Detailed Description

                                  + The Host Global Registers structure defines the size and relative field offsets for the Host Mode Global Registers. +@@ -57,163 +45,227 @@ +

                                  + +

                                  +-Definition at line 1627 of file dwc_otg_regs.h.

                                  Field Documentation

                                  +- +-
                                  +-
                                  +- ++Definition at line 1854 of file dwc_otg_regs.h.

                                  Field Documentation

                                  ++

                                  ++

                                  ++ ++ ++ ++
                                  ++ + +- ++ + +
                                  volatile uint32_t dwc_otg_host_global_regs::hcfg volatile uint32_t dwc_otg_host_global_regs::hcfg
                                  +- +-
                                  ++
                                  ++ ++ ++ ++
                                  ++   ++ + +

                                  + Host Configuration Register. +

                                  + Offset: 400h +

                                  +-Definition at line 1629 of file dwc_otg_regs.h. +- +-

                                  +- +-

                                  +-
                                  +- ++Definition at line 1856 of file dwc_otg_regs.h. ++ ++
                                  ++

                                  ++ ++ ++ ++ ++
                                  ++ + +- ++ + +
                                  volatile uint32_t dwc_otg_host_global_regs::hfir volatile uint32_t dwc_otg_host_global_regs::hfir
                                  +- +-
                                  ++
                                  ++ ++ ++ ++
                                  ++   ++ + +

                                  + Host Frame Interval Register. +

                                  + Offset: 404h +

                                  +-Definition at line 1631 of file dwc_otg_regs.h. +- +-

                                  +- +-

                                  +-
                                  +- ++Definition at line 1858 of file dwc_otg_regs.h. ++ ++
                                  ++

                                  ++ ++ ++ ++ ++
                                  ++ + +- ++ + +
                                  volatile uint32_t dwc_otg_host_global_regs::hfnum volatile uint32_t dwc_otg_host_global_regs::hfnum
                                  +- +-
                                  ++
                                  ++ ++ ++ ++
                                  ++   ++ + +

                                  + Host Frame Number / Frame Remaining Register. +

                                  + Offset: 408h +

                                  +-Definition at line 1633 of file dwc_otg_regs.h. +- +-

                                  +- +-

                                  +-
                                  +- ++Definition at line 1860 of file dwc_otg_regs.h. ++ ++
                                  ++

                                  ++ ++ ++ ++ ++
                                  ++ + +- ++ + +
                                  uint32_t dwc_otg_host_global_regs::reserved40C uint32_t dwc_otg_host_global_regs::reserved40C
                                  +- +-
                                  ++
                                  ++ ++ ++ ++
                                  ++   ++ + +

                                  + Reserved. +

                                  + Offset: 40Ch +

                                  +-Definition at line 1635 of file dwc_otg_regs.h. +- +-

                                  +- +-

                                  +-
                                  +- ++Definition at line 1862 of file dwc_otg_regs.h. ++ ++
                                  ++

                                  ++ ++ ++ ++ ++
                                  ++ + +- ++ + +
                                  volatile uint32_t dwc_otg_host_global_regs::hptxsts volatile uint32_t dwc_otg_host_global_regs::hptxsts
                                  +- +-
                                  ++
                                  ++ ++ ++ ++
                                  ++   ++ + +

                                  + Host Periodic Transmit FIFO/ Queue Status Register. +

                                  + Offset: 410h +

                                  +-Definition at line 1637 of file dwc_otg_regs.h. +- +-

                                  +- +-

                                  +-
                                  +- ++Definition at line 1864 of file dwc_otg_regs.h. ++ ++
                                  ++

                                  ++ ++ ++ ++ ++
                                  ++ + +- ++ + +
                                  volatile uint32_t dwc_otg_host_global_regs::haint volatile uint32_t dwc_otg_host_global_regs::haint
                                  +- +-
                                  ++
                                  ++ ++ ++ ++
                                  ++   ++ + +

                                  + Host All Channels Interrupt Register. +

                                  + Offset: 414h +

                                  +-Definition at line 1639 of file dwc_otg_regs.h. +- +-

                                  +- +-

                                  +-
                                  +- ++Definition at line 1866 of file dwc_otg_regs.h. ++ ++
                                  ++

                                  ++ ++ ++ ++ ++
                                  ++ + +- ++ + +
                                  volatile uint32_t dwc_otg_host_global_regs::haintmsk volatile uint32_t dwc_otg_host_global_regs::haintmsk
                                  +- +-
                                  ++
                                  ++ ++ ++ ++
                                  ++   ++ + +

                                  + Host All Channels Interrupt Mask Register. +

                                  + Offset: 418h +

                                  +-Definition at line 1641 of file dwc_otg_regs.h. +- +-

                                  +- +-

                                  +-
                                  +- ++Definition at line 1868 of file dwc_otg_regs.h. ++ ++
                                  ++

                                  ++ ++ ++ ++ ++
                                  ++ + +- ++ + +
                                  volatile uint32_t dwc_otg_host_global_regs::hflbaddr volatile uint32_t dwc_otg_host_global_regs::hflbaddr
                                  +- +-
                                  ++
                                  ++ ++ ++ ++ ++ ++
                                  ++   ++ + +

                                  + Host Frame List Base Address Register . +

                                  + Offset: 41Ch +

                                  +-Definition at line 1643 of file dwc_otg_regs.h. +- +-

                                  ++Definition at line 1870 of file dwc_otg_regs.h.

                                  +

                                  The documentation for this struct was generated from the following file: +-
                                  Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++
                                  Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
                                  ++doxygen 1.3.9.1
                                  + + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__host__if.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__host__if.html 2013-07-26 19:31:22.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__host__if.html 2013-07-26 19:34:43.000000000 +0000 +@@ -2,22 +2,10 @@ + + DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_host_if Struct Reference + +- + +- +-
                                  +-
                                  +-
                                  +-
                                  +-

                                  dwc_otg_host_if Struct Reference

                                  OTG Host Interface Structure. ++ ++
                                  Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                  ++

                                  dwc_otg_host_if Struct Reference

                                  OTG Host Interface Structure. + More... +

                                  + #include <dwc_otg_regs.h> +@@ -25,28 +13,28 @@ + + + +- ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ + + +

                                  Data Fields

                                  +-dwc_otg_host_global_regs_t * host_global_regs
                                  ++dwc_otg_host_global_regs_t * host_global_regs
                                   Host Global Registers starting at offset 400h.
                                  +-volatile uint32_t * hprt0
                                  ++volatile uint32_t * hprt0
                                   Host Port 0 Control and Status Register.
                                  +-dwc_otg_hc_regs_t * hc_regs [MAX_EPS_CHANNELS]
                                  ++dwc_otg_hc_regs_t * hc_regs [MAX_EPS_CHANNELS]
                                   Host Channel Specific Registers at offsets 500h-5FCh.
                                  +-uint8_t num_host_channels
                                  ++uint8_t num_host_channels
                                   Number of Host Channels (range: 1-16).
                                  +-uint8_t perio_eps_supported
                                  ++uint8_t perio_eps_supported
                                   Periodic EPs supported (0: no, 1: yes).
                                  +-uint16_t perio_tx_fifo_size
                                  ++uint16_t perio_tx_fifo_size
                                   Periodic Tx FIFO Size (Only 1 host periodic Tx FIFO).
                                  +@@ -57,10 +45,10 @@ +

                                  + +

                                  +-Definition at line 2181 of file dwc_otg_regs.h.

                                  The documentation for this struct was generated from the following file:
                                    ++Definition at line 2398 of file dwc_otg_regs.h.
                                    The documentation for this struct was generated from the following file: +-
                                    Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++
                                    Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
                                    ++doxygen 1.3.9.1
                                    + + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__pcd.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__pcd.html 2013-07-26 19:31:22.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__pcd.html 2013-07-26 19:34:43.000000000 +0000 +@@ -2,22 +2,10 @@ + + DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_pcd Struct Reference + +- + +- +-
                                    +-
                                    +-
                                    +-
                                    +-

                                    dwc_otg_pcd Struct Reference

                                    DWC_otg PCD Structure. ++ ++
                                    Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                    ++

                                    dwc_otg_pcd Struct Reference

                                    DWC_otg PCD Structure. + More... +

                                    + #include <dwc_otg_pcd.h> +@@ -25,94 +13,93 @@ + + + +- ++ + +- ++ ++ ++ ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ + +- ++ + +- ++ + +- ++ + +- +- ++ ++ + +- ++ + + +- ++ + +- ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ + +- +- +- +- +- ++ ++ + + +- ++ + + +

                                    Data Fields

                                    +-dwc_otg_pcd_function_ops * fops
                                    ++const struct dwc_otg_pcd_function_ops * fops
                                    +-dwc_otg_core_if_t * core_if
                                    ++dwc_otg_device * otg_dev
                                     The DWC otg device pointer.
                                    ++dwc_otg_core_if_t * core_if
                                     Core Interface.
                                    +-ep0state_e ep0state
                                    ++ep0state_e ep0state
                                     State of EP0.
                                    +-unsigned ep0_pending:1
                                    ++unsigned ep0_pending:1
                                     EP0 Request is pending.
                                    +-unsigned request_config:1
                                    ++unsigned request_config:1
                                     Indicates when SET CONFIGURATION Request is in process.
                                    +-unsigned remote_wakeup_enable:1
                                    ++unsigned remote_wakeup_enable:1
                                     The state of the Remote Wakeup Enable.
                                    +-unsigned b_hnp_enable:1
                                    ++unsigned b_hnp_enable:1
                                     The state of the B-Device HNP Enable.
                                    +-unsigned a_hnp_support:1
                                    ++unsigned a_hnp_support:1
                                     The state of A-Device HNP Support.
                                    +-unsigned a_alt_hnp_support:1
                                    ++unsigned a_alt_hnp_support:1
                                     The state of the A-Device Alt HNP support.
                                    +-unsigned request_pending
                                    ++unsigned request_pending
                                     Count of pending Requests.
                                    +-union {
                                    union {
                                       usb_device_request_t   req
                                       usb_device_request_t   req
                                       uint32_t   d32 [2]
                                       uint32_t   d32 [2]
                                    } setup_pkt
                                    } setup_pkt
                                     SETUP packet for EP0 This structure is allocated as a DMA buffer on PCD initialization with enough space for up to 3 setup packets.
                                    +-dwc_dma_t setup_pkt_dma_handle
                                     SETUP packet for EP0 This structure is allocated as a DMA buffer on PCD initialization with enough space for up to 3 setup packets.
                                    ++dwc_dma_t setup_pkt_dma_handle
                                    +-uint16_t * status_buf
                                    ++uint16_t * status_buf
                                     2-byte dma buffer used to return status from GET_STATUS
                                    +-dwc_dma_t status_buf_dma_handle
                                    ++dwc_dma_t status_buf_dma_handle
                                    +-dwc_otg_pcd_ep_t ep0
                                    ++dwc_otg_pcd_ep_t ep0
                                     EP0.
                                    +-dwc_otg_pcd_ep_t in_ep [MAX_EPS_CHANNELS-1]
                                    ++dwc_otg_pcd_ep_t in_ep [MAX_EPS_CHANNELS-1]
                                     Array of IN EPs.
                                    +-dwc_otg_pcd_ep_t out_ep [MAX_EPS_CHANNELS-1]
                                    ++dwc_otg_pcd_ep_t out_ep [MAX_EPS_CHANNELS-1]
                                     Array of OUT EPs.
                                    +-dwc_spinlock_t * lock
                                    ++dwc_spinlock_t * lock
                                     number of valid EPs in the above array.
                                    dwc_timer_t * srp_timer
                                    dwc_tasklet_t * test_mode_tasklet
                                     Timer for SRP.
                                    +-dwc_tasklet_t * test_mode_tasklet
                                     Tasklet to defer starting of TEST mode transmissions until Status Phase has been completed.
                                    +-dwc_tasklet_t * start_xfer_tasklet
                                     Tasklet to defer starting of TEST mode transmissions until Status Phase has been completed.
                                    ++dwc_tasklet_t * start_xfer_tasklet
                                     Tasklet to delay starting of xfer in DMA mode.
                                    +-unsigned test_mode
                                    ++unsigned test_mode
                                     The test mode to enter when the tasklet is executed.
                                    +@@ -123,30 +110,63 @@ +

                                    + +

                                    +-Definition at line 137 of file dwc_otg_pcd.h.

                                    Field Documentation

                                    +- +-
                                    +-
                                    +- ++Definition at line 184 of file dwc_otg_pcd.h.

                                    Field Documentation

                                    ++

                                    ++

                                    ++ ++ ++ ++
                                    ++ ++ ++ ++ ++
                                    union { ... } * dwc_otg_pcd::setup_pkt
                                    ++
                                    ++ ++ ++ ++ ++ ++
                                    ++   ++ ++ ++

                                    ++SETUP packet for EP0 This structure is allocated as a DMA buffer on PCD initialization with enough space for up to 3 setup packets. ++

                                    ++

                                    ++

                                    ++ ++ ++ ++ ++
                                    ++ + +- ++ + +
                                    dwc_timer_t* dwc_otg_pcd::srp_timer dwc_tasklet_t* dwc_otg_pcd::test_mode_tasklet
                                    +- +-
                                    ++
                                    ++ ++ ++ ++ ++ ++
                                    ++   ++ + +

                                    +-Timer for SRP. ++Tasklet to defer starting of TEST mode transmissions until Status Phase has been completed. +

                                    +-If it expires before SRP is successful clear the SRP. ++ +

                                    +-Definition at line 185 of file dwc_otg_pcd.h. +- +-

                                    ++Definition at line 236 of file dwc_otg_pcd.h.

                                    +

                                    The documentation for this struct was generated from the following file: +-
                                    Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++
                                    Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
                                    ++doxygen 1.3.9.1
                                    + + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__pcd__ep.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__pcd__ep.html 2013-07-26 19:31:22.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__pcd__ep.html 2013-07-26 19:34:43.000000000 +0000 +@@ -2,22 +2,10 @@ + + DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_pcd_ep Struct Reference + +- + +- +-
                                    +-
                                    +-
                                    +-
                                    +-

                                    dwc_otg_pcd_ep Struct Reference

                                    PCD EP structure. ++ ++
                                    Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                    ++

                                    dwc_otg_pcd_ep Struct Reference

                                    PCD EP structure. + More... +

                                    + #include <dwc_otg_pcd.h> +@@ -25,40 +13,40 @@ + + + +- ++ + + +- ++ + + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + + +- ++ + + +- ++ + + +- ++ + +

                                    Data Fields

                                    +-const usb_endpoint_descriptor_t * desc
                                    ++const usb_endpoint_descriptor_t * desc
                                     USB EP Descriptor.
                                    +-req_list queue
                                    ++req_list queue
                                     queue of dwc_otg_pcd_requests.
                                    +-unsigned stopped:1
                                    ++unsigned stopped:1
                                    +-unsigned disabling:1
                                    ++unsigned disabling:1
                                    +-unsigned dma:1
                                    ++unsigned dma:1
                                    +-unsigned queue_sof:1
                                    ++unsigned queue_sof:1
                                    +-void * iso_req_handle
                                    ++void * iso_req_handle
                                     ISOC req handle passed.
                                    +-dwc_ep_t dwc_ep
                                    ++dwc_ep_t dwc_ep
                                     DWC_otg ep data.
                                    +-dwc_otg_pcd * pcd
                                    ++dwc_otg_pcd * pcd
                                     Pointer to PCD.
                                    +-void * priv
                                    ++void * priv
                                    +

                                    Detailed Description

                                    +@@ -68,10 +56,10 @@ +

                                    + +

                                    +-Definition at line 109 of file dwc_otg_pcd.h.

                                    The documentation for this struct was generated from the following file:
                                      ++Definition at line 156 of file dwc_otg_pcd.h.
                                      The documentation for this struct was generated from the following file: +-
                                      Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++
                                      Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
                                      ++doxygen 1.3.9.1
                                      + + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__pcd__function__ops.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__pcd__function__ops.html 2013-07-26 19:31:22.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__pcd__function__ops.html 2013-07-26 19:34:43.000000000 +0000 +@@ -2,22 +2,10 @@ + + DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_pcd_function_ops Struct Reference + +- + +- +-
                                      +-
                                      +-
                                      +-
                                      +-

                                      dwc_otg_pcd_function_ops Struct Reference

                                      Function Driver Ops Data Structure. ++ ++
                                      Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                      ++

                                      dwc_otg_pcd_function_ops Struct Reference

                                      Function Driver Ops Data Structure. + More... +

                                      + #include <dwc_otg_pcd_if.h> +@@ -25,38 +13,38 @@ + + + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +

                                      Data Fields

                                      +-dwc_connect_cb_t connect
                                      ++dwc_connect_cb_t connect
                                      +-dwc_disconnect_cb_t disconnect
                                      ++dwc_disconnect_cb_t disconnect
                                      +-dwc_setup_cb_t setup
                                      ++dwc_setup_cb_t setup
                                      +-dwc_completion_cb_t complete
                                      ++dwc_completion_cb_t complete
                                      +-dwc_isoc_completion_cb_t isoc_complete
                                      ++dwc_isoc_completion_cb_t isoc_complete
                                      +-dwc_suspend_cb_t suspend
                                      ++dwc_suspend_cb_t suspend
                                      +-dwc_sleep_cb_t sleep
                                      ++dwc_sleep_cb_t sleep
                                      +-dwc_resume_cb_t resume
                                      ++dwc_resume_cb_t resume
                                      +-dwc_reset_cb_t reset
                                      ++dwc_reset_cb_t reset
                                      +-dwc_hnp_params_changed_cb_t hnp_changed
                                      ++dwc_hnp_params_changed_cb_t hnp_changed
                                      +-cfi_setup_cb_t cfi_setup
                                      ++cfi_setup_cb_t cfi_setup
                                      +

                                      Detailed Description

                                      +@@ -64,10 +52,10 @@ +

                                      + +

                                      +-Definition at line 107 of file dwc_otg_pcd_if.h.

                                      The documentation for this struct was generated from the following file:
                                        ++Definition at line 116 of file dwc_otg_pcd_if.h.
                                        The documentation for this struct was generated from the following file: +-
                                        Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++
                                        Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
                                        ++doxygen 1.3.9.1
                                        + + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__pcd__request.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__pcd__request.html 2013-07-26 19:31:22.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__pcd__request.html 2013-07-26 19:34:43.000000000 +0000 +@@ -2,22 +2,10 @@ + + DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_pcd_request Struct Reference + +- + +- +-
                                        +-
                                        +-
                                        +-
                                        +-

                                        dwc_otg_pcd_request Struct Reference

                                        DWC_otg request structure. ++ ++
                                        Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                        ++

                                        dwc_otg_pcd_request Struct Reference

                                        DWC_otg request structure. + More... +

                                        + #include <dwc_otg_pcd.h> +@@ -25,27 +13,34 @@ + + + +- + + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ ++ ++ ++ ++ ++ + +

                                        Public Member Functions

                                        ++
                                        +  DWC_CIRCLEQ_ENTRY (dwc_otg_pcd_request) queue_entry

                                        Data Fields

                                        +-void * priv
                                        ++void * priv
                                        +-void * buf
                                        ++void * buf
                                        +-dwc_dma_t dma
                                        ++dwc_dma_t dma
                                        +-uint32_t length
                                        ++uint32_t length
                                        +-uint32_t actual
                                        ++uint32_t actual
                                        +-unsigned sent_zlp:1
                                        ++unsigned sent_zlp:1
                                        ++uint8_t * dw_align_buf
                                         Used instead of original buffer if it(physical address) is not dword-aligned.
                                        ++dwc_dma_t dw_align_buf_dma
                                        +

                                        Detailed Description

                                        +@@ -55,10 +50,10 @@ +

                                        + +

                                        +-Definition at line 92 of file dwc_otg_pcd.h.

                                        The documentation for this struct was generated from the following file:
                                          ++Definition at line 129 of file dwc_otg_pcd.h.
                                          The documentation for this struct was generated from the following file: +-
                                          Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++
                                          Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
                                          ++doxygen 1.3.9.1
                                          + + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__qh.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__qh.html 2013-07-26 19:31:22.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__qh.html 2013-07-26 19:34:43.000000000 +0000 +@@ -2,22 +2,10 @@ + + DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_qh Struct Reference + +- + +- +-
                                          +-
                                          +-
                                          +-
                                          +-

                                          dwc_otg_qh Struct Reference

                                          A Queue Head (QH) holds the static characteristics of an endpoint and maintains a list of transfers (QTDs) for that endpoint. ++ ++
                                          Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                          ++

                                          dwc_otg_qh Struct Reference

                                          A Queue Head (QH) holds the static characteristics of an endpoint and maintains a list of transfers (QTDs) for that endpoint. + More... +

                                          + #include <dwc_otg_hcd.h> +@@ -25,87 +13,85 @@ + + + +- ++ + +- +- ++ ++ + +- ++ + + +- ++ + +- +- ++ ++ + +- +- ++ ++ + + +- ++ + +- +- ++ ++ + + +- ++ + + +- ++ + +- +- ++ ++ + +- ++ + + + +- ++ + + +- ++ + + +- ++ + +- +- ++ ++ + + + +- ++ + + +- ++ + + +- ++ + +- +- ++ ++ + + +- ++ + + +- ++ + + +

                                          Data Fields

                                          uint8_t ep_type
                                          uint8_t ep_type
                                           Endpoint type.
                                          +-uint8_t ep_is_in
                                           Endpoint type.
                                          ++uint8_t ep_is_in
                                          +-uint16_t maxp
                                          ++uint16_t maxp
                                           wMaxPacketSize Field of Endpoint Descriptor.
                                          uint8_t dev_speed
                                          uint8_t dev_speed
                                           Device speed.
                                          uint8_t data_toggle
                                           Device speed.
                                          uint8_t data_toggle
                                           Determines the PID of the next data packet for non-control transfers.
                                          +-uint8_t ping_state
                                           Determines the PID of the next data packet for non-control transfers.
                                          ++uint8_t ping_state
                                           Ping state if 1.
                                          +-dwc_otg_qtd_list qtd_list
                                          dwc_otg_qtd_list qtd_list
                                           List of QTDs for this QH.
                                          +-dwc_hc * channel
                                           List of QTDs for this QH.
                                          ++dwc_hc * channel
                                           Host channel currently processing transfers for this QH.
                                          +-uint8_t do_split
                                          ++uint8_t do_split
                                           Full/low speed endpoint on high-speed hub requires split.
                                          +-uint8_t * dw_align_buf
                                          uint8_t * dw_align_buf
                                           Used instead of original buffer if it(physical address) is not dword-aligned.
                                          +-dwc_dma_t dw_align_buf_dma
                                           Used instead of original buffer if it(physical address) is not dword-aligned.
                                          ++dwc_dma_t dw_align_buf_dma
                                          +-dwc_list_link_t qh_list_entry
                                          ++dwc_list_link_t qh_list_entry
                                           Entry for QH in either the periodic or non-periodic schedule.
                                          Periodic schedule information
                                          +-uint16_t usecs
                                          ++uint16_t usecs
                                           Bandwidth in microseconds per (micro)frame.
                                          +-uint16_t interval
                                          ++uint16_t interval
                                           Interval between transfers in (micro)frames.
                                          uint16_t sched_frame
                                          uint16_t sched_frame
                                           (micro)frame to initialize a periodic transfer.
                                          +-uint16_t start_split_frame
                                           (micro)frame to initialize a periodic transfer.
                                          ++uint16_t start_split_frame
                                           (micro)frame at which last start split was initialized.
                                          Descriptor DMA support
                                          +-dwc_otg_host_dma_desc_t * desc_list
                                          ++dwc_otg_host_dma_desc_t * desc_list
                                           Descriptor List.
                                          +-dwc_dma_t desc_list_dma
                                          ++dwc_dma_t desc_list_dma
                                           Descriptor List physical address.
                                          uint32_t * n_bytes
                                          uint32_t * n_bytes
                                           Xfer Bytes array.
                                          +-uint16_t ntd
                                           Xfer Bytes array.
                                          ++uint16_t ntd
                                           Actual number of transfer descriptors in a list.
                                          +-uint8_t td_first
                                          ++uint8_t td_first
                                           First activated isochronous transfer descriptor index.
                                          +-uint8_t td_last
                                          ++uint8_t td_last
                                           Last activated isochronous transfer descriptor index.
                                          +@@ -116,113 +102,207 @@ +

                                          + +

                                          +-Definition at line 261 of file dwc_otg_hcd.h.

                                          Field Documentation

                                          +- +-
                                          +-
                                          +- ++Definition at line 262 of file dwc_otg_hcd.h.

                                          Field Documentation

                                          ++

                                          ++

                                          ++ ++ ++ ++
                                          ++ + +- ++ + +
                                          uint8_t dwc_otg_qh::ep_type uint8_t dwc_otg_qh::ep_type
                                          +- +-
                                          ++
                                          ++ ++ ++ ++
                                          ++   ++ + +

                                          + Endpoint type. +

                                          + One of the following values:

                                            +-
                                          • UE_CONTROL
                                          • UE_BULK
                                          • UE_INTERRUPT
                                          • UE_ISOCHRONOUS
                                          ++
                                        • UE_CONTROL
                                        • UE_BULK
                                        • UE_INTERRUPT
                                        • UE_ISOCHRONOUS
                                          • + +

                                          +-Definition at line 270 of file dwc_otg_hcd.h. +- +-

                                          +- +-

                                          +-
                                          +- ++Definition at line 271 of file dwc_otg_hcd.h. ++ ++
                                          ++

                                          ++ ++ ++ ++ ++
                                          ++ + +- ++ + +
                                          uint8_t dwc_otg_qh::dev_speed uint8_t dwc_otg_qh::dev_speed
                                          +- +-
                                          ++
                                          ++ ++ ++ ++
                                          ++   ++ + +

                                          + Device speed. +

                                          + One of the following values:

                                            +-
                                          • DWC_OTG_EP_SPEED_LOW
                                          • DWC_OTG_EP_SPEED_FULL
                                          • DWC_OTG_EP_SPEED_HIGH
                                          ++
                                        • DWC_OTG_EP_SPEED_LOW
                                        • DWC_OTG_EP_SPEED_FULL
                                        • DWC_OTG_EP_SPEED_HIGH
                                          • + +

                                          +-Definition at line 283 of file dwc_otg_hcd.h. +- +-

                                          +- +-

                                          +-
                                          +- ++Definition at line 284 of file dwc_otg_hcd.h. ++ ++
                                          ++

                                          ++ ++ ++ ++ ++
                                          ++ + +- ++ + +
                                          uint8_t dwc_otg_qh::data_toggle uint8_t dwc_otg_qh::data_toggle
                                          +- +-
                                          ++
                                          ++ ++ ++ ++ ++ ++
                                          ++   ++ + +

                                          + Determines the PID of the next data packet for non-control transfers. +

                                          + Ignored for control transfers.
                                          + One of the following values:

                                            +-
                                          • DWC_OTG_HC_PID_DATA0
                                          • DWC_OTG_HC_PID_DATA1
                                          ++
                                        • DWC_OTG_HC_PID_DATA0
                                        • DWC_OTG_HC_PID_DATA1
                                          • ++ ++

                                          ++Definition at line 293 of file dwc_otg_hcd.h.

                                          ++

                                          ++ ++ ++ ++ ++
                                          ++ ++ ++ ++ ++
                                          struct dwc_otg_qtd_list dwc_otg_qh::qtd_list
                                          ++
                                          ++ ++ ++ ++
                                          ++   ++ ++ ++

                                          ++List of QTDs for this QH. ++

                                          + +

                                          +-Definition at line 292 of file dwc_otg_hcd.h. +- +-

                                          +- +-

                                          +-
                                          +- ++Definition at line 301 of file dwc_otg_hcd.h. ++ ++
                                          ++

                                          ++ ++ ++ ++ ++
                                          ++ + +- ++ + +
                                          uint16_t dwc_otg_qh::sched_frame uint16_t dwc_otg_qh::sched_frame
                                          +- +-
                                          ++
                                          ++ ++ ++ ++
                                          ++   ++ + +

                                          + (micro)frame to initialize a periodic transfer. +

                                          +-The transfer executes in the following (micro)frame. ++The transfer executes in the following (micro)frame. +

                                          +-Definition at line 321 of file dwc_otg_hcd.h. +- +-

                                          +- +-

                                          +-
                                          +- ++Definition at line 322 of file dwc_otg_hcd.h. ++ ++
                                          ++

                                          ++ ++ ++ ++ ++
                                          ++ + +- ++ + +
                                          uint32_t* dwc_otg_qh::n_bytes uint8_t* dwc_otg_qh::dw_align_buf
                                          +- +-
                                          ++
                                          ++ ++ ++ ++ ++ ++
                                          ++   ++ ++ ++

                                          ++Used instead of original buffer if it(physical address) is not dword-aligned. ++

                                          ++ ++

                                          ++Definition at line 333 of file dwc_otg_hcd.h.

                                          ++

                                          ++ ++ ++ ++ ++
                                          ++ ++ ++ ++ ++
                                          uint32_t* dwc_otg_qh::n_bytes
                                          ++
                                          ++ ++ ++ ++ ++ ++
                                          ++   ++ + +

                                          + Xfer Bytes array. +

                                          +-Each element corresponds to a descriptor and indicates original XferSize size value for the descriptor. ++Each element corresponds to a descriptor and indicates original XferSize size value for the descriptor. +

                                          +-Definition at line 352 of file dwc_otg_hcd.h. +- +-

                                          ++Definition at line 353 of file dwc_otg_hcd.h.

                                          +

                                          The documentation for this struct was generated from the following file: +-
                                          Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++
                                          Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
                                          ++doxygen 1.3.9.1
                                          + + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__qtd.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__qtd.html 2013-07-26 19:31:22.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__qtd.html 2013-07-26 19:34:43.000000000 +0000 +@@ -2,22 +2,10 @@ + + DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_qtd Struct Reference + +- + +- +-
                                          +-
                                          +-
                                          +-
                                          +-

                                          dwc_otg_qtd Struct Reference

                                          A Queue Transfer Descriptor (QTD) holds the state of a bulk, control, interrupt, or isochronous transfer. ++ ++
                                          Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                          ++

                                          dwc_otg_qtd Struct Reference

                                          A Queue Transfer Descriptor (QTD) holds the state of a bulk, control, interrupt, or isochronous transfer. + More... +

                                          + #include <dwc_otg_hcd.h> +@@ -25,59 +13,58 @@ + + + +- ++ + + + +- ++ + +- +- ++ ++ + + +- ++ + + +- ++ + + +- ++ + +- +- ++ ++ + +- +- ++ ++ + + +- ++ + + +- ++ + + +- ++ + +- ++ + + +- ++ + + +- ++ + +- ++ +

                                          Public Member Functions

                                          +- DWC_CIRCLEQ_ENTRY (dwc_otg_qtd) qtd_list_entry
                                          ++ DWC_CIRCLEQ_ENTRY (dwc_otg_qtd) qtd_list_entry
                                           This list of QTDs.

                                          Data Fields

                                          uint8_t data_toggle
                                          uint8_t data_toggle
                                           Determines the PID of the next data packet for the data phase of control transfers.
                                          +-dwc_otg_control_phase_e control_phase
                                           Determines the PID of the next data packet for the data phase of control transfers.
                                          ++dwc_otg_control_phase_e control_phase
                                           Current phase for control transfers (Setup, Data, or Status).
                                          +-uint8_t complete_split
                                          ++uint8_t complete_split
                                           Keep track of the current split type for FS/LS endpoints on a HS Hub.
                                          +-uint32_t ssplit_out_xfer_count
                                          ++uint32_t ssplit_out_xfer_count
                                           How many bytes transferred during SSPLIT OUT.
                                          +-uint8_t error_count
                                          uint8_t error_count
                                           Holds the number of bus errors that have occurred for a transaction within this transfer.
                                          uint16_t isoc_frame_index
                                           Holds the number of bus errors that have occurred for a transaction within this transfer.
                                          uint16_t isoc_frame_index
                                           Index of the next frame descriptor for an isochronous transfer.
                                          +-uint8_t isoc_split_pos
                                           Index of the next frame descriptor for an isochronous transfer.
                                          ++uint8_t isoc_split_pos
                                           Position of the ISOC split on full/low speed.
                                          +-uint16_t isoc_split_offset
                                          ++uint16_t isoc_split_offset
                                           Position of the ISOC split in the buffer for the current frame.
                                          +-dwc_otg_hcd_urb * urb
                                          ++dwc_otg_hcd_urb * urb
                                           URB for this transfer.
                                          +-dwc_otg_qh * qh
                                          ++dwc_otg_qh * qh
                                          +-uint8_t in_process
                                          ++uint8_t in_process
                                           Indicates if this QTD is currently processed by HW.
                                          +-uint8_t n_desc
                                          ++uint8_t n_desc
                                           Number of DMA descriptors for this QTD.
                                          uint16_t isoc_frame_index_last
                                          uint16_t isoc_frame_index_last
                                           Last activated frame(packet) index.
                                           Last activated frame(packet) index.
                                          +

                                          Detailed Description

                                          + A Queue Transfer Descriptor (QTD) holds the state of a bulk, control, interrupt, or isochronous transfer. +@@ -87,71 +74,122 @@ +

                                          + +

                                          +-Definition at line 191 of file dwc_otg_hcd.h.

                                          Field Documentation

                                          +- +-
                                          +-
                                          +- ++Definition at line 192 of file dwc_otg_hcd.h.

                                          Field Documentation

                                          ++

                                          ++

                                          ++ ++ ++ ++
                                          ++ + +- ++ + +
                                          uint8_t dwc_otg_qtd::data_toggle uint8_t dwc_otg_qtd::data_toggle
                                          +- +-
                                          ++
                                          ++ ++ ++ ++ ++ ++
                                          ++   ++ + +

                                          + Determines the PID of the next data packet for the data phase of control transfers. +

                                          + Ignored for other transfer types.
                                          + One of the following values:

                                            +-
                                          • DWC_OTG_HC_PID_DATA0
                                          • DWC_OTG_HC_PID_DATA1
                                          ++
                                        • DWC_OTG_HC_PID_DATA0
                                        • DWC_OTG_HC_PID_DATA1
                                          • ++ ++

                                          ++Definition at line 200 of file dwc_otg_hcd.h.

                                          ++

                                          ++ ++ ++ ++ ++
                                          ++ ++ ++ ++ ++
                                          uint8_t dwc_otg_qtd::error_count
                                          ++
                                          ++ ++ ++ ++
                                          ++   ++ + +

                                          +-Definition at line 199 of file dwc_otg_hcd.h. +- +-

                                          +- +-

                                          +-
                                          +- ++Holds the number of bus errors that have occurred for a transaction within this transfer. ++

                                          ++ ++

                                          ++Definition at line 216 of file dwc_otg_hcd.h. ++ ++

                                          ++

                                          ++ ++ ++ ++ ++
                                          ++ + +- ++ + +
                                          uint16_t dwc_otg_qtd::isoc_frame_index uint16_t dwc_otg_qtd::isoc_frame_index
                                          +- +-
                                          ++
                                          ++ ++ ++ ++
                                          ++   ++ + +

                                          + Index of the next frame descriptor for an isochronous transfer. +

                                          +-A frame descriptor describes the buffer position and length of the data to be transferred in the next scheduled (micro)frame of an isochronous transfer. It also holds status for that transaction. The frame index starts at 0. ++A frame descriptor describes the buffer position and length of the data to be transferred in the next scheduled (micro)frame of an isochronous transfer. It also holds status for that transaction. The frame index starts at 0. +

                                          +-Definition at line 224 of file dwc_otg_hcd.h. +- +-

                                          +- +-

                                          +-
                                          +- ++Definition at line 225 of file dwc_otg_hcd.h. ++ ++
                                          ++

                                          ++ ++ ++ ++ ++
                                          ++ + +- ++ + +
                                          uint16_t dwc_otg_qtd::isoc_frame_index_last uint16_t dwc_otg_qtd::isoc_frame_index_last
                                          +- +-
                                          ++
                                          ++ ++ ++ ++ ++ ++
                                          ++   ++ + +

                                          + Last activated frame(packet) index. +

                                          +-Used in Descriptor DMA mode only. ++Used in Descriptor DMA mode only. +

                                          +-Definition at line 250 of file dwc_otg_hcd.h. +- +-

                                          ++Definition at line 251 of file dwc_otg_hcd.h.

                                          +

                                          The documentation for this struct was generated from the following file: +-
                                          Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++
                                          Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
                                          ++doxygen 1.3.9.1
                                          + + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structgadget__wrapper.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/structgadget__wrapper.html 2013-07-26 19:31:22.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,53 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: gadget_wrapper Struct Reference +- +- +- +- +-
                                          +-
                                          +-
                                          +-
                                          +-

                                          gadget_wrapper Struct Reference

                                          +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-

                                          Data Fields

                                          +-dwc_otg_pcd_t * pcd
                                          +-usb_gadget gadget
                                          +-usb_gadget_driver * driver
                                          +-usb_ep ep0
                                          +-usb_ep in_ep [16]
                                          +-usb_ep out_ep [16]
                                          +-

                                          Detailed Description

                                          +- +-

                                          +- +-

                                          +-Definition at line 82 of file dwc_otg_pcd_linux.c.

                                          The documentation for this struct was generated from the following file: +-
                                          Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.4.7
                                          +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structiso__pkt__info.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/structiso__pkt__info.html 2013-07-26 19:31:22.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structiso__pkt__info.html 2013-07-26 19:34:43.000000000 +0000 +@@ -2,22 +2,10 @@ + + DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: iso_pkt_info Struct Reference + +- + +- +-
                                          +-
                                          +-
                                          +-
                                          +-

                                          iso_pkt_info Struct Reference

                                          Information for each ISOC packet. ++ ++
                                          Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                          ++

                                          iso_pkt_info Struct Reference

                                          Information for each ISOC packet. + More... +

                                          + #include <dwc_otg_cil.h> +@@ -25,14 +13,14 @@ + + + +- ++ + +- ++ + +- ++ + +

                                          Data Fields

                                          +-uint32_t offset
                                          ++uint32_t offset
                                          +-uint32_t length
                                          ++uint32_t length
                                          +-int32_t status
                                          ++int32_t status
                                          +

                                          Detailed Description

                                          +@@ -40,10 +28,10 @@ +

                                          + +

                                          +-Definition at line 77 of file dwc_otg_cil.h.

                                          The documentation for this struct was generated from the following file:
                                            ++Definition at line 81 of file dwc_otg_cil.h.
                                            The documentation for this struct was generated from the following file: +-
                                            Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++
                                            Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
                                            ++doxygen 1.3.9.1
                                            + + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structwrapper__priv__data.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/structwrapper__priv__data.html 2013-07-26 19:31:22.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,38 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: wrapper_priv_data Struct Reference +- +- +- +- +-
                                            +-
                                            +-
                                            +-
                                            +-

                                            wrapper_priv_data Struct Reference

                                            +- +- +- +- +-

                                            Data Fields

                                            +-dwc_otg_hcd_t * dwc_otg_hcd
                                            +-

                                            Detailed Description

                                            +- +-

                                            +- +-

                                            +-Definition at line 95 of file dwc_otg_hcd_linux.c.

                                            The documentation for this struct was generated from the following file: +-
                                            Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.4.7
                                            +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structzero__dev.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/structzero__dev.html 2013-07-26 19:31:22.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,56 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: zero_dev Struct Reference +- +- +- +- +-
                                            +-
                                            +-
                                            +-
                                            +-

                                            zero_dev Struct Reference

                                            +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-

                                            Data Fields

                                            +-spinlock_t lock
                                            +-usb_gadget * gadget
                                            +-usb_request * req
                                            +-u8 config
                                            +-usb_ep * in_ep
                                            +-usb_ep * out_ep
                                            +-timer_list resume
                                            +-

                                            Detailed Description

                                            +- +-

                                            +- +-

                                            +-Definition at line 342 of file dummy_audio.c.

                                            The documentation for this struct was generated from the following file: +-
                                            Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.4.7
                                            +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/tabs.css +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/tabs.css 2013-07-26 19:31:22.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,102 +0,0 @@ +-/* tabs styles, based on http://www.alistapart.com/articles/slidingdoors */ +- +-DIV.tabs +-{ +- float : left; +- width : 100%; +- background : url("tab_b.gif") repeat-x bottom; +- margin-bottom : 4px; +-} +- +-DIV.tabs UL +-{ +- margin : 0px; +- padding-left : 10px; +- list-style : none; +-} +- +-DIV.tabs LI, DIV.tabs FORM +-{ +- display : inline; +- margin : 0px; +- padding : 0px; +-} +- +-DIV.tabs FORM +-{ +- float : right; +-} +- +-DIV.tabs A +-{ +- float : left; +- background : url("tab_r.gif") no-repeat right top; +- border-bottom : 1px solid #84B0C7; +- font-size : x-small; +- font-weight : bold; +- text-decoration : none; +-} +- +-DIV.tabs A:hover +-{ +- background-position: 100% -150px; +-} +- +-DIV.tabs A:link, DIV.tabs A:visited, +-DIV.tabs A:active, DIV.tabs A:hover +-{ +- color: #1A419D; +-} +- +-DIV.tabs SPAN +-{ +- float : left; +- display : block; +- background : url("tab_l.gif") no-repeat left top; +- padding : 5px 9px; +- white-space : nowrap; +-} +- +-DIV.tabs INPUT +-{ +- float : right; +- display : inline; +- font-size : 1em; +-} +- +-DIV.tabs TD +-{ +- font-size : x-small; +- font-weight : bold; +- text-decoration : none; +-} +- +- +- +-/* Commented Backslash Hack hides rule from IE5-Mac \*/ +-DIV.tabs SPAN {float : none;} +-/* End IE5-Mac hack */ +- +-DIV.tabs A:hover SPAN +-{ +- background-position: 0% -150px; +-} +- +-DIV.tabs LI#current A +-{ +- background-position: 100% -150px; +- border-width : 0px; +-} +- +-DIV.tabs LI#current SPAN +-{ +- background-position: 0% -150px; +- padding-bottom : 6px; +-} +- +-DIV.nav +-{ +- background : none; +- border : none; +- border-bottom : 1px solid #84B0C7; +-} +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/todo.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/todo.html 2013-07-26 19:31:22.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/todo.html 2013-07-26 19:34:43.000000000 +0000 +@@ -2,261 +2,228 @@ + + DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Todo List + +- + +- +-
                                            +-
                                            +-

                                            Todo List

                                            +-
                                            Global DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW
                                            +-
                                            Add code to initiate the HNP.
                                            +-
                                            +-

                                            +-

                                            +-
                                            Global srp_show
                                            ++ ++
                                            Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                            ++

                                            Todo List

                                            ++
                                            Global srp_show (struct device *_dev, struct device_attribute *attr, char *buf)
                                            +
                                            Add code to initiate the SRP.
                                            +
                                            +

                                            +

                                            +-
                                            Global buspower_show
                                            ++
                                            Global buspower_show (struct device *_dev, struct device_attribute *attr, char *buf)
                                            +
                                            Need to do more for power on/off?
                                            +
                                            +

                                            +

                                            +-
                                            Global bussuspend_show
                                            ++
                                            Global bussuspend_show (struct device *_dev, struct device_attribute *attr, char *buf)
                                            +
                                            Need to do more for suspend?
                                            +
                                            +

                                            +

                                            +-
                                            Global dwc_otg_enable_device_interrupts
                                            +-
                                            NGS: Should this be a module parameter?
                                            ++
                                            Global dwc_otg_enable_device_interrupts (dwc_otg_core_if_t *core_if)
                                            ++
                                            NGS: Should this be a module parameter?
                                            +
                                            +

                                            +

                                            +-
                                            Global dwc_otg_core_dev_init
                                            +-
                                            NGS: Fix Periodic FIFO Sizing!
                                            ++
                                            Global dwc_otg_core_dev_init (dwc_otg_core_if_t *core_if)
                                            ++
                                            NGS: Fix Periodic FIFO Sizing!

                                            ++Finish debug of this

                                            ++- if the condition needed to be checked or in any case all pending interrutps should be cleared?

                                            +
                                            +

                                            +-

                                            +-
                                            Global dwc_otg_core_dev_init
                                            +-
                                            Finish debug of this
                                            ++
                                            ++
                                            Global dwc_otg_ep0_continue_transfer (dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
                                            ++
                                            Should there be check for room in the Tx Status Queue. If not remove the code above this comment.
                                            +
                                            +

                                            +-

                                            +-
                                            Global dwc_otg_core_dev_init
                                            +-
                                            - if the condition needed to be checked or in any case all pending interrutps should be cleared?
                                            ++
                                            ++
                                            Global dwc_otg_ep_write_packet (dwc_otg_core_if_t *core_if, dwc_ep_t *ep, int dma)
                                            ++
                                            NGS Where are the Periodic Tx FIFO addresses intialized? What should this be?
                                            +
                                            +

                                            +

                                            +-
                                            Global dwc_otg_ep0_continue_transfer
                                            +-
                                            Should there be check for room in the Tx Status Queue. If not remove the code above this comment.
                                            ++
                                            Global dwc_otg_read_packet (dwc_otg_core_if_t *core_if, uint8_t *dest, uint16_t bytes)
                                            ++
                                            Account for the case where _dest is not dword aligned. This requires reading data from the FIFO into a uint32_t temp buffer, then moving it into the data buffer.
                                            +
                                            +

                                            +

                                            +-
                                            Global dwc_otg_ep_write_packet
                                            +-
                                            NGS Where are the Periodic Tx FIFO addresses intialized? What should this be?
                                            ++
                                            Global dwc_otg_handle_disconnect_intr (dwc_otg_core_if_t *core_if)
                                            ++
                                            Consolidate this if statement.
                                            +
                                            +

                                            +

                                            +-
                                            Global dwc_otg_read_packet
                                            +-
                                            Account for the case where _dest is not dword aligned. This requires reading data from the FIFO into a uint32_t temp buffer, then moving it into the data buffer.
                                            ++
                                            Global dwc_otg_read_common_intr (dwc_otg_core_if_t *core_if)
                                            ++
                                            : The port interrupt occurs while in device mode. Added code to CIL to clear the interrupt for now!
                                            +
                                            +

                                            +

                                            +-
                                            Global dwc_otg_handle_disconnect_intr
                                            +-
                                            Consolidate this if statement.
                                            ++
                                            Global MODULE_PARM_DESC (max_transfer_size,"The maximum transfer size supported in bytes 2047-65535")
                                            ++
                                            Set the max to 512K, modify checks
                                            +
                                            +

                                            +

                                            +-
                                            Global dwc_otg_read_common_intr
                                            +-
                                            : The port interrupt occurs while in device mode. Added code to CIL to clear the interrupt for now!
                                            ++
                                            Global dwc_otg_hcd_hub_control (dwc_otg_hcd_t *dwc_otg_hcd, uint16_t typeReq, uint16_t wValue, uint16_t wIndex, uint8_t *buf, uint16_t wLength)
                                            ++
                                            - check how sw can wait for 1 sec to check asesvld???
                                            +
                                            +

                                            +-

                                            +-
                                            Global MODULE_PARM_DESC
                                            +-
                                            Set the max to 512K, modify checks
                                            ++
                                            ++
                                            Global dwc_otg_hcd_handle_intr (dwc_otg_hcd_t *dwc_otg_hcd)
                                            ++
                                            Implement i2cintr handler.
                                            +
                                            +

                                            +

                                            +-
                                            Global dwc_otg_hcd_handle_intr
                                            +-
                                            Implement i2cintr handler.
                                            ++
                                            Global dwc_otg_hcd_handle_port_intr (dwc_otg_hcd_t *dwc_otg_hcd)
                                            ++
                                            - check if steps performed in 'else' block should be perfromed regardles adp
                                            +
                                            +

                                            +

                                            +-
                                            Global dwc_otg_hcd_qh_create
                                            +-
                                            add memflags argument
                                            ++
                                            Global dwc_otg_hcd_qh_create (dwc_otg_hcd_t *hcd, dwc_otg_hcd_urb_t *urb, int atomic_alloc)
                                            ++
                                            add memflags argument
                                            +
                                            +

                                            +-

                                            +-
                                            Global dwc_otg_hcd_complete_xfer_ddma
                                            ++
                                            ++
                                            Global dwc_otg_hcd_complete_xfer_ddma (dwc_otg_hcd_t *hcd, dwc_hc_t *hc, dwc_otg_hc_regs_t *hc_regs, dwc_otg_halt_status_e halt_status)
                                            +
                                            Consider the case when period exceeds FrameList size. Frame Rollover interrupt should be used.
                                            +
                                            +

                                            +

                                            +-
                                            Global handle_hc_nyet_intr
                                            +-
                                            add support for isoc release
                                            ++
                                            Global handle_hc_nyet_intr (dwc_otg_hcd_t *hcd, dwc_hc_t *hc, dwc_otg_hc_regs_t *hc_regs, dwc_otg_qtd_t *qtd)
                                            ++
                                            add support for isoc release
                                            +
                                            +

                                            +

                                            +-
                                            Global handle_hc_chhltd_intr_dma
                                            ++
                                            Global handle_hc_chhltd_intr_dma (dwc_otg_hcd_t *hcd, dwc_hc_t *hc, dwc_otg_hc_regs_t *hc_regs, dwc_otg_qtd_t *qtd)
                                            +
                                            This is here because of a possible hardware bug. Spec says that on SPLIT-ISOC OUT transfers in DMA mode that a HALT interrupt w/ACK bit set should occur, but I only see the XFERCOMP bit, even with it masked out. This is a workaround for that behavior. Should fix this when hardware is fixed.
                                            +
                                            +

                                            +

                                            +-
                                            Global qh_init
                                            +-
                                            Account for split transfers in the bus time.
                                            ++
                                            Global qh_init (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh, dwc_otg_hcd_urb_t *urb)
                                            ++
                                            Account for split transfers in the bus time.
                                            +
                                            +

                                            +

                                            +
                                            File dwc_otg_pcd.c
                                            +
                                            Add Device Mode test modes (Test J mode, Test K mode, etc).

                                            +-Does it work when the request size is greater than DEPTSIZ transfer size

                                            +-

                                            ++Does it work when the request size is greater than DEPTSIZ transfer size +
                                            +

                                            +

                                            +-
                                            Global dwc_otg_pcd_iso_ep_start
                                            +-
                                            - pattern data support is to be implemented in the future
                                            ++
                                            Global dwc_otg_pcd_iso_ep_start (dwc_otg_pcd_t *pcd, void *ep_handle, uint8_t *buf0, uint8_t *buf1, dwc_dma_t dma0, dwc_dma_t dma1, int sync_frame, int dp_frame, int data_per_frame, int start_frame, int buf_proc_intrvl, void *req_handle, int atomic_alloc)
                                            ++
                                            - pattern data support is to be implemented in the future
                                            +
                                            +

                                            +

                                            +-
                                            Global dwc_otg_pcd_reinit
                                            +-
                                            NGS: Add direction to EP, based on contents of HWCFG1. Need a copy of HWCFG1 in pcd structure? sprintf(";r
                                            ++
                                            Global dwc_otg_pcd_reinit (dwc_otg_pcd_t *pcd)
                                            ++
                                            NGS: Add direction to EP, based on contents of HWCFG1. Need a copy of HWCFG1 in pcd structure? sprintf(";r

                                            ++NGS: Add direction to EP, based on contents of HWCFG1. Need a copy of HWCFG1 in pcd structure? sprintf(";r

                                            +
                                            +

                                            +-

                                            +-
                                            Global dwc_otg_pcd_reinit
                                            +-
                                            NGS: Add direction to EP, based on contents of HWCFG1. Need a copy of HWCFG1 in pcd structure? sprintf(";r
                                            ++
                                            ++
                                            Global dwc_otg_pcd_ep_queue (dwc_otg_pcd_t *pcd, void *ep_handle, uint8_t *buf, dwc_dma_t dma_buf, uint32_t buflen, int zero, void *req_handle, int atomic_alloc)
                                            ++
                                            NGS Create a function for this.
                                            +
                                            +

                                            +-

                                            +-
                                            Global dwc_otg_pcd_ep_queue
                                            +-
                                            NGS Create a function for this.
                                            ++
                                            ++
                                            Global do_test_mode (void *data)
                                            ++
                                            This has not been tested since the tasklet struct was put into the PCD struct!
                                            +
                                            +

                                            +-

                                            +-
                                            Global do_test_mode
                                            +-
                                            This has not been tested since the tasklet struct was put into the PCD struct!

                                            +-

                                            ++
                                            ++
                                            Global dwc_otg_pcd_handle_rx_status_q_level_intr (dwc_otg_pcd_t *pcd)
                                            ++
                                            NGS Check for buffer overflow?
                                            +
                                            +

                                            +

                                            +-
                                            Global dwc_otg_pcd_handle_rx_status_q_level_intr
                                            +-
                                            NGS Check for buffer overflow?
                                            ++
                                            Global get_ep_of_last_in_token (dwc_otg_core_if_t *core_if)
                                            ++
                                            Find a simpler way to calculate the max queue position.
                                            +
                                            +

                                            +

                                            +-
                                            Global get_ep_of_last_in_token
                                            +-
                                            Find a simpler way to calculate the max queue position.
                                            ++
                                            Global dwc_otg_pcd_stop (dwc_otg_pcd_t *pcd)
                                            ++
                                            NGS Flush Periodic FIFOs
                                            +
                                            +

                                            +

                                            +-
                                            Global dwc_otg_pcd_stop
                                            +-
                                            NGS Flush Periodic FIFOs
                                            ++
                                            Global ep0_out_start (dwc_otg_core_if_t *core_if, dwc_otg_pcd_t *pcd)
                                            ++
                                            NGS: Update the comments from the HW FS.
                                            +
                                            +

                                            +

                                            +-
                                            Global ep0_out_start
                                            +-
                                            NGS: Update the comments from the HW FS.

                                            +-

                                            ++
                                            Global ep0_out_start (dwc_otg_core_if_t *core_if, dwc_otg_pcd_t *pcd)
                                            ++
                                            dma needs to handle multiple setup packets (up to 3)
                                            +
                                            +

                                            +-

                                            +-
                                            Global ep0_out_start
                                            +-
                                            dma needs to handle multiple setup packets (up to 3)
                                            ++
                                            ++
                                            Global do_gadget_setup (dwc_otg_pcd_t *pcd, usb_device_request_t *ctrl)
                                            ++
                                            This is a g_file_storage gadget driver specific workaround: a DELAYED_STATUS result from the fsg_setup routine will result in the gadget queueing a EP0 IN status phase for a two-stage control transfer. Exactly the same as a SET_CONFIGURATION/SET_INTERFACE except that this is a class specific request. Need a generic way to know when the gadget driver will queue the status phase. Can we assume when we call the gadget driver setup() function that it will always queue and require the following flag? Need to look into this.
                                            +
                                            +

                                            +

                                            +-
                                            Global do_gadget_setup
                                            +-
                                            This is a g_file_storage gadget driver specific workaround: a DELAYED_STATUS result from the fsg_setup routine will result in the gadget queueing a EP0 IN status phase for a two-stage control transfer. Exactly the same as a SET_CONFIGURATION/SET_INTERFACE except that this is a class specific request. Need a generic way to know when the gadget driver will queue the status phase. Can we assume when we call the gadget driver setup() function that it will always queue and require the following flag? Need to look into this.
                                            ++
                                            Global pcd_clear_halt (dwc_otg_pcd_t *pcd, dwc_otg_pcd_ep_t *ep)
                                            ++
                                            FIXME: this causes an EP mismatch in DMA mode. epmismatch not yet implemented.
                                            +
                                            +

                                            +-

                                            +-
                                            Global pcd_clear_halt
                                            +-
                                            FIXME: this causes an EP mismatch in DMA mode. epmismatch not yet implemented.
                                            ++
                                            ++
                                            Global do_get_status (dwc_otg_pcd_t *pcd)
                                            ++
                                            check for EP stall
                                            +
                                            +

                                            +

                                            +-
                                            Global do_get_status
                                            +-
                                            check for EP stall
                                            ++
                                            Global do_set_feature (dwc_otg_pcd_t *pcd)
                                            ++
                                            This has not been tested since the tasklet struct was put into the PCD struct!

                                            ++Is the gotgctl.devhnpen cleared by a USB Reset?

                                            +
                                            +

                                            +

                                            +-
                                            Global do_set_feature
                                            +-
                                            This has not been tested since the tasklet struct was put into the PCD struct!
                                            ++
                                            Global do_clear_feature (dwc_otg_pcd_t *pcd)
                                            ++
                                            Add CLEAR_FEATURE for TEST modes.
                                            +
                                            +

                                            +-

                                            +-
                                            Global do_set_feature
                                            +-
                                            Is the gotgctl.devhnpen cleared by a USB Reset?
                                            ++
                                            ++
                                            Global pcd_setup (dwc_otg_pcd_t *pcd)
                                            ++
                                            handle > 1 setup packet , assert error for now

                                            ++NGS: Handle bad setup packet?

                                            +
                                            +

                                            +

                                            +-
                                            Global do_clear_feature
                                            +-
                                            Add CLEAR_FEATURE for TEST modes.
                                            ++
                                            Global handle_in_ep_timeout_intr (dwc_otg_pcd_t *pcd, const uint32_t epnum)
                                            ++
                                            NGS Check EP type. Implement for Periodic EPs
                                            +
                                            +

                                            +

                                            +-
                                            Global pcd_setup
                                            +-
                                            handle > 1 setup packet , assert error for now
                                            ++
                                            Global handle_in_ep_nak_intr (dwc_otg_pcd_t *pcd, const uint32_t epnum)
                                            ++
                                            implement ISR
                                            +
                                            +

                                            +-

                                            +-
                                            Global pcd_setup
                                            +-
                                            NGS: Handle bad setup packet?
                                            ++
                                            ++
                                            Global handle_out_ep_babble_intr (dwc_otg_pcd_t *pcd, const uint32_t epnum)
                                            ++
                                            implement ISR
                                            +
                                            +

                                            +

                                            +-
                                            Global handle_in_ep_timeout_intr
                                            +-
                                            NGS Check EP type. Implement for Periodic EPs
                                            ++
                                            Global handle_out_ep_nak_intr (dwc_otg_pcd_t *pcd, const uint32_t epnum)
                                            ++
                                            implement ISR
                                            +
                                            +

                                            +

                                            +-
                                            Global handle_in_ep_nak_intr
                                            +-
                                            implement ISR
                                            ++
                                            Global handle_out_ep_nyet_intr (dwc_otg_pcd_t *pcd, const uint32_t epnum)
                                            ++
                                            implement ISR
                                            +
                                            +

                                            +

                                            +-
                                            Global handle_out_ep_babble_intr
                                            +-
                                            implement ISR
                                            ++
                                            Global gadget_add_eps (struct gadget_wrapper *d)
                                            ++
                                            NGS: What should the max packet size be set to here? Before EP type is set?

                                            ++NGS: What should the max packet size be set to here? Before EP type is set?

                                            ++NGS: What should the max packet size be set to here? Before EP type is set?

                                            +
                                            +

                                            +

                                            +-
                                            Global handle_out_ep_nak_intr
                                            +-
                                            implement ISR
                                            +-
                                            +-

                                            +-

                                            +-
                                            Global handle_out_ep_nyet_intr
                                            +-
                                            implement ISR
                                            +-
                                            +-

                                            +-

                                            +-
                                            Global gadget_add_eps
                                            +-
                                            NGS: What should the max packet size be set to here? Before EP type is set?
                                            +-
                                            +-

                                            +-

                                            +-
                                            Global gadget_add_eps
                                            +-
                                            NGS: What should the max packet size be set to here? Before EP type is set?
                                            +-
                                            +-

                                            +-

                                            +-
                                            Global gadget_add_eps
                                            +-
                                            NGS: What should the max packet size be set to here? Before EP type is set?
                                            +-
                                            +-

                                            +-

                                            +-
                                            Global dwc_otg_pcd_gadget_release
                                            ++
                                            Global dwc_otg_pcd_gadget_release (struct device *dev)
                                            +
                                            Should this do something? Should it free the PCD?
                                            +
                                            +-
                                            Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++
                                            Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
                                            ++doxygen 1.3.9.1
                                            + + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/tree.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/tree.html 2013-07-26 19:31:22.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/tree.html 2013-07-26 19:34:43.000000000 +0000 +@@ -1,30 +1,70 @@ + + +- ++ + + + + TreeView ++ + + + +- ++ +
                                            +

                                            DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver

                                            +
                                            +-

                                            o+Data Structures

                                            ++

                                            o*Main Page

                                            ++

                                            o+File List

                                            + ++

                                            o+Data Structures

                                            ++ +

                                            o*Data Fields

                                            +-

                                            o+File List

                                            +- +

                                            o*Globals

                                            +

                                            \+Related Pages

                                            +
                                            +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/unionadpctl__data.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/unionadpctl__data.html 2013-07-26 19:34:43.000000000 +0000 +@@ -0,0 +1,440 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: adpctl_data Union Reference ++ ++ ++ ++
                                            Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                            ++

                                            adpctl_data Union Reference

                                            This union represents the bit fields of the Core ADP Timer, Control and Status Register (ADPTIMCTLSTS). ++More... ++

                                            ++#include <dwc_otg_regs.h> ++

                                            ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++

                                            Data Fields

                                            ++uint32_t d32
                                             raw register data
                                            ++struct {
                                               unsigned   prb_dschg:2
                                             Probe Discharge (PRB_DSCHG) These bits set the times for TADP_DSCHG.
                                               unsigned   prb_delta:2
                                             Probe Delta (PRB_DELTA) These bits set the resolution for RTIM value.
                                               unsigned   prb_per:2
                                             Probe Period (PRB_PER) These bits sets the TADP_PRD as shown in Figure 4 as follows: 2'b00 - 0.625 to 0.925 sec (typical 0.775 sec) 2'b01 - 1.25 to 1.85 sec (typical 1.55 sec) 2'b10 - 1.9 to 2.6 sec (typical 2.275 sec) 2'b11 - Reserved.
                                               unsigned   rtim:11
                                             These bits capture the latest time it took for VBUS to ramp from VADP_SINK to VADP_PRB.
                                               unsigned   enaprb:1
                                             Enable Probe (EnaPrb) When programmed to 1'b1, the core performs a probe operation.
                                               unsigned   enasns:1
                                             Enable Sense (EnaSns) When programmed to 1'b1, the core performs a Sense operation.
                                               unsigned   adpres:1
                                             ADP Reset (ADPRes) When set, ADP controller is reset.
                                               unsigned   adpen:1
                                             ADP Enable (ADPEn) When set, the core performs either ADP probing or sensing based on EnaPrb or EnaSns.
                                               unsigned   adp_prb_int:1
                                             ADP Probe Interrupt (ADP_PRB_INT) When this bit is set, it means that the VBUS voltage is greater than VADP_PRB or VADP_PRB is reached.
                                               unsigned   adp_sns_int:1
                                             ADP Sense Interrupt (ADP_SNS_INT) When this bit is set, it means that the VBUS voltage is greater than VADP_SNS value or VADP_SNS is reached.
                                               unsigned   adp_tmout_int:1
                                             ADP Tomeout Interrupt (ADP_TMOUT_INT) This bit is relevant only for an ADP probe.
                                               unsigned   adp_prb_int_msk:1
                                             ADP Probe Interrupt Mask (ADP_PRB_INT_MSK) When this bit is set, it unmasks the interrupt due to ADP_PRB_INT.
                                               unsigned   adp_sns_int_msk:1
                                             ADP Sense Interrupt Mask (ADP_SNS_INT_MSK) When this bit is set, it unmasks the interrupt due to ADP_SNS_INT.
                                               unsigned   adp_tmout_int_msk:1
                                             ADP Timoeout Interrupt Mask (ADP_TMOUT_MSK) When this bit is set, it unmasks the interrupt due to ADP_TMOUT_INT.
                                               unsigned   ar:2
                                             Access Request 2'b00 - Read/Write Valid (updated by the core) 2'b01 - Read 2'b00 - Write 2'b00 - Reserved.
                                               unsigned   reserved29_31:3
                                             Reserved.
                                            } b
                                             register bits
                                            ++

                                            Detailed Description

                                            ++This union represents the bit fields of the Core ADP Timer, Control and Status Register (ADPTIMCTLSTS). ++

                                            ++Set the bits using bit fields then write the d32 value to the register. ++

                                            ++ ++

                                            ++Definition at line 955 of file dwc_otg_regs.h.

                                            Field Documentation

                                            ++

                                            ++ ++ ++ ++ ++
                                            ++ ++ ++ ++ ++
                                            unsigned adpctl_data::prb_dschg
                                            ++
                                            ++ ++ ++ ++ ++ ++
                                            ++   ++ ++ ++

                                            ++Probe Discharge (PRB_DSCHG) These bits set the times for TADP_DSCHG. ++

                                            ++These bits are defined as follows: 2'b00 - 4 msec 2'b01 - 8 msec 2'b10 - 16 msec 2'b11 - 32 msec ++

                                            ++Definition at line 968 of file dwc_otg_regs.h.

                                            ++

                                            ++ ++ ++ ++ ++
                                            ++ ++ ++ ++ ++
                                            unsigned adpctl_data::prb_delta
                                            ++
                                            ++ ++ ++ ++ ++ ++
                                            ++   ++ ++ ++

                                            ++Probe Delta (PRB_DELTA) These bits set the resolution for RTIM value. ++

                                            ++The bits are defined in units of 32 kHz clock cycles as follows: 2'b00 - 1 cycles 2'b01 - 2 cycles 2'b10 - 3 cycles 2'b11 - 4 cycles For example if this value is chosen to 2'b01, it means that RTIM increments for every 3(three) 32Khz clock cycles. ++

                                            ++Definition at line 979 of file dwc_otg_regs.h.

                                            ++

                                            ++ ++ ++ ++ ++
                                            ++ ++ ++ ++ ++
                                            unsigned adpctl_data::rtim
                                            ++
                                            ++ ++ ++ ++ ++ ++
                                            ++   ++ ++ ++

                                            ++These bits capture the latest time it took for VBUS to ramp from VADP_SINK to VADP_PRB. ++

                                            ++0x000 - 1 cycles 0x001 - 2 cycles 0x002 - 3 cycles etc 0x7FF - 2048 cycles A time of 1024 cycles at 32 kHz corresponds to a time of 32 msec. ++

                                            ++Definition at line 997 of file dwc_otg_regs.h.

                                            ++

                                            ++ ++ ++ ++ ++
                                            ++ ++ ++ ++ ++
                                            unsigned adpctl_data::enaprb
                                            ++
                                            ++ ++ ++ ++ ++ ++
                                            ++   ++ ++ ++

                                            ++Enable Probe (EnaPrb) When programmed to 1'b1, the core performs a probe operation. ++

                                            ++This bit is valid only if OTG_Ver = 1'b1. ++

                                            ++Definition at line 1002 of file dwc_otg_regs.h.

                                            ++

                                            ++ ++ ++ ++ ++
                                            ++ ++ ++ ++ ++
                                            unsigned adpctl_data::enasns
                                            ++
                                            ++ ++ ++ ++ ++ ++
                                            ++   ++ ++ ++

                                            ++Enable Sense (EnaSns) When programmed to 1'b1, the core performs a Sense operation. ++

                                            ++This bit is valid only if OTG_Ver = 1'b1. ++

                                            ++Definition at line 1007 of file dwc_otg_regs.h.

                                            ++

                                            ++ ++ ++ ++ ++
                                            ++ ++ ++ ++ ++
                                            unsigned adpctl_data::adpres
                                            ++
                                            ++ ++ ++ ++ ++ ++
                                            ++   ++ ++ ++

                                            ++ADP Reset (ADPRes) When set, ADP controller is reset. ++

                                            ++This bit is valid only if OTG_Ver = 1'b1. ++

                                            ++Definition at line 1012 of file dwc_otg_regs.h.

                                            ++

                                            ++ ++ ++ ++ ++
                                            ++ ++ ++ ++ ++
                                            unsigned adpctl_data::adpen
                                            ++
                                            ++ ++ ++ ++ ++ ++
                                            ++   ++ ++ ++

                                            ++ADP Enable (ADPEn) When set, the core performs either ADP probing or sensing based on EnaPrb or EnaSns. ++

                                            ++This bit is valid only if OTG_Ver = 1'b1. ++

                                            ++Definition at line 1018 of file dwc_otg_regs.h.

                                            ++

                                            ++ ++ ++ ++ ++
                                            ++ ++ ++ ++ ++
                                            unsigned adpctl_data::adp_prb_int
                                            ++
                                            ++ ++ ++ ++ ++ ++
                                            ++   ++ ++ ++

                                            ++ADP Probe Interrupt (ADP_PRB_INT) When this bit is set, it means that the VBUS voltage is greater than VADP_PRB or VADP_PRB is reached. ++

                                            ++This bit is valid only if OTG_Ver = 1'b1. ++

                                            ++Definition at line 1024 of file dwc_otg_regs.h.

                                            ++

                                            ++ ++ ++ ++ ++
                                            ++ ++ ++ ++ ++
                                            unsigned adpctl_data::adp_sns_int
                                            ++
                                            ++ ++ ++ ++ ++ ++
                                            ++   ++ ++ ++

                                            ++ADP Sense Interrupt (ADP_SNS_INT) When this bit is set, it means that the VBUS voltage is greater than VADP_SNS value or VADP_SNS is reached. ++

                                            ++This bit is valid only if OTG_Ver = 1'b1. ++

                                            ++Definition at line 1031 of file dwc_otg_regs.h.

                                            ++

                                            ++ ++ ++ ++ ++
                                            ++ ++ ++ ++ ++
                                            unsigned adpctl_data::adp_tmout_int
                                            ++
                                            ++ ++ ++ ++ ++ ++
                                            ++   ++ ++ ++

                                            ++ADP Tomeout Interrupt (ADP_TMOUT_INT) This bit is relevant only for an ADP probe. ++

                                            ++When this bit is set, it means that the ramp time has completed ie ADPCTL.RTIM has reached its terminal value of 0x7FF. This is a debug feature that allows software to read the ramp time after each cycle. This bit is valid only if OTG_Ver = 1'b1. ++

                                            ++Definition at line 1040 of file dwc_otg_regs.h.

                                            ++

                                            ++ ++ ++ ++ ++
                                            ++ ++ ++ ++ ++
                                            unsigned adpctl_data::adp_prb_int_msk
                                            ++
                                            ++ ++ ++ ++ ++ ++
                                            ++   ++ ++ ++

                                            ++ADP Probe Interrupt Mask (ADP_PRB_INT_MSK) When this bit is set, it unmasks the interrupt due to ADP_PRB_INT. ++

                                            ++This bit is valid only if OTG_Ver = 1'b1. ++

                                            ++Definition at line 1045 of file dwc_otg_regs.h.

                                            ++

                                            ++ ++ ++ ++ ++
                                            ++ ++ ++ ++ ++
                                            unsigned adpctl_data::adp_sns_int_msk
                                            ++
                                            ++ ++ ++ ++ ++ ++
                                            ++   ++ ++ ++

                                            ++ADP Sense Interrupt Mask (ADP_SNS_INT_MSK) When this bit is set, it unmasks the interrupt due to ADP_SNS_INT. ++

                                            ++This bit is valid only if OTG_Ver = 1'b1. ++

                                            ++Definition at line 1050 of file dwc_otg_regs.h.

                                            ++

                                            ++ ++ ++ ++ ++
                                            ++ ++ ++ ++ ++
                                            unsigned adpctl_data::adp_tmout_int_msk
                                            ++
                                            ++ ++ ++ ++ ++ ++
                                            ++   ++ ++ ++

                                            ++ADP Timoeout Interrupt Mask (ADP_TMOUT_MSK) When this bit is set, it unmasks the interrupt due to ADP_TMOUT_INT. ++

                                            ++This bit is valid only if OTG_Ver = 1'b1. ++

                                            ++Definition at line 1055 of file dwc_otg_regs.h.

                                            ++

                                            The documentation for this union was generated from the following file: ++
                                            Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.3.9.1
                                            ++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/uniondaint__data.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/uniondaint__data.html 2013-07-26 19:31:22.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/uniondaint__data.html 2013-07-26 19:34:43.000000000 +0000 +@@ -2,22 +2,10 @@ + + DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: daint_data Union Reference + +- + +- +-
                                            +-
                                            +-
                                            +-
                                            +-

                                            daint_data Union Reference

                                            This union represents the bit fields in the Device All EP Interrupt and Mask Registers. ++ ++
                                            Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                            ++

                                            daint_data Union Reference

                                            This union represents the bit fields in the Device All EP Interrupt and Mask Registers. + More... +

                                            + #include <dwc_otg_regs.h> +@@ -25,90 +13,90 @@ + + + +- ++ + + +- + +- ++ + + +- ++ + + +- ++ + + +- + +- ++ + + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + + + +@@ -122,10 +110,10 @@ +

                                            + +

                                            +-Definition at line 1130 of file dwc_otg_regs.h.

                                            The documentation for this union was generated from the following file:
                                              ++Definition at line 1350 of file dwc_otg_regs.h.
                                              The documentation for this union was generated from the following file: +-
                                              Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++
                                              Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
                                              ++doxygen 1.3.9.1
                                              + + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/uniondcfg__data.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/uniondcfg__data.html 2013-07-26 19:31:22.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/uniondcfg__data.html 2013-07-26 19:34:43.000000000 +0000 +@@ -2,22 +2,10 @@ + + DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dcfg_data Union Reference + +- + +- +-
                                              +-
                                              +-
                                              +-
                                              +-

                                              dcfg_data Union Reference

                                              This union represents the bit fields in the Device Configuration Register. ++ ++
                                              Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                              ++

                                              dcfg_data Union Reference

                                              This union represents the bit fields in the Device Configuration Register. + More... +

                                              + #include <dwc_otg_regs.h> +@@ -25,36 +13,43 @@ +


                                            Data Fields

                                            +-uint32_t d32
                                            ++uint32_t d32
                                             raw register data
                                            ++
                                            + struct {
                                               unsigned   in:16
                                               unsigned   in:16
                                             IN Endpoint bits.
                                               unsigned   out:16
                                               unsigned   out:16
                                             OUT Endpoint bits.
                                            } ep
                                            } ep
                                             register bits
                                            ++
                                            + struct {
                                               unsigned   inep0:1
                                               unsigned   inep0:1
                                             IN Endpoint bits.
                                               unsigned   inep1:1
                                               unsigned   inep1:1
                                               unsigned   inep2:1
                                               unsigned   inep2:1
                                               unsigned   inep3:1
                                               unsigned   inep3:1
                                               unsigned   inep4:1
                                               unsigned   inep4:1
                                               unsigned   inep5:1
                                               unsigned   inep5:1
                                               unsigned   inep6:1
                                               unsigned   inep6:1
                                               unsigned   inep7:1
                                               unsigned   inep7:1
                                               unsigned   inep8:1
                                               unsigned   inep8:1
                                               unsigned   inep9:1
                                               unsigned   inep9:1
                                               unsigned   inep10:1
                                               unsigned   inep10:1
                                               unsigned   inep11:1
                                               unsigned   inep11:1
                                               unsigned   inep12:1
                                               unsigned   inep12:1
                                               unsigned   inep13:1
                                               unsigned   inep13:1
                                               unsigned   inep14:1
                                               unsigned   inep14:1
                                               unsigned   inep15:1
                                               unsigned   inep15:1
                                               unsigned   outep0:1
                                               unsigned   outep0:1
                                             OUT Endpoint bits.
                                               unsigned   outep1:1
                                               unsigned   outep1:1
                                               unsigned   outep2:1
                                               unsigned   outep2:1
                                               unsigned   outep3:1
                                               unsigned   outep3:1
                                               unsigned   outep4:1
                                               unsigned   outep4:1
                                               unsigned   outep5:1
                                               unsigned   outep5:1
                                               unsigned   outep6:1
                                               unsigned   outep6:1
                                               unsigned   outep7:1
                                               unsigned   outep7:1
                                               unsigned   outep8:1
                                               unsigned   outep8:1
                                               unsigned   outep9:1
                                               unsigned   outep9:1
                                               unsigned   outep10:1
                                               unsigned   outep10:1
                                               unsigned   outep11:1
                                               unsigned   outep11:1
                                               unsigned   outep12:1
                                               unsigned   outep12:1
                                               unsigned   outep13:1
                                               unsigned   outep13:1
                                               unsigned   outep14:1
                                               unsigned   outep14:1
                                               unsigned   outep15:1
                                               unsigned   outep15:1
                                            } b
                                            + + +- ++ + + +- + +- ++ + + +- ++ + + +- ++ + +- ++ + + +- ++ + + +- ++ + +- ++ ++ ++ ++ + + +- ++ + + +- ++ ++ ++ ++ ++ + + +

                                            Data Fields

                                            +-uint32_t d32
                                            ++uint32_t d32
                                             raw register data
                                            ++
                                            + struct {
                                               unsigned   devspd:2
                                               unsigned   devspd:2
                                             Device Speed.
                                               unsigned   nzstsouthshk:1
                                               unsigned   nzstsouthshk:1
                                             Non Zero Length Status OUT Handshake.
                                               unsigned   reserved3:1
                                               unsigned   ena32khzs:1
                                               unsigned   devaddr:7
                                               unsigned   devaddr:7
                                             Device Addresses.
                                               unsigned   perfrint:2
                                               unsigned   perfrint:2
                                             Periodic Frame Interval.
                                               unsigned   reserved13_17:5
                                               unsigned   endevoutnak:1
                                               unsigned   epmscnt:5
                                             Enable Device OUT NAK for bulk in DDMA mode.
                                               unsigned   reserved14_17:4
                                               unsigned   epmscnt:5
                                             In Endpoint Mis-match count.
                                               unsigned   descdma:1
                                               unsigned   descdma:1
                                             Enable Descriptor DMA in Device mode.
                                            } b
                                               unsigned   perschintvl:2
                                               unsigned   resvalid:6
                                            } b
                                             register bits
                                            +@@ -65,10 +60,10 @@ +

                                            + +

                                            +-Definition at line 923 of file dwc_otg_regs.h.

                                            The documentation for this union was generated from the following file:
                                              ++Definition at line 1137 of file dwc_otg_regs.h.
                                              The documentation for this union was generated from the following file: +-
                                              Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++
                                              Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
                                              ++doxygen 1.3.9.1
                                              + + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/uniondctl__data.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/uniondctl__data.html 2013-07-26 19:31:22.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/uniondctl__data.html 2013-07-26 19:34:43.000000000 +0000 +@@ -2,22 +2,10 @@ + + DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dctl_data Union Reference + +- + +- +-
                                              +-
                                              +-
                                              +-
                                              +-

                                              dctl_data Union Reference

                                              This union represents the bit fields in the Device Control Register. ++ ++
                                              Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                              ++

                                              dctl_data Union Reference

                                              This union represents the bit fields in the Device Control Register. + More... +

                                              + #include <dwc_otg_regs.h> +@@ -25,58 +13,61 @@ + + + +- ++ + + +- + +- ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ + +- +- ++ ++ + + +- ++ + + +- ++ + + +- ++ + +- ++ ++ ++ ++ + + +

                                              Data Fields

                                              +-uint32_t d32
                                              ++uint32_t d32
                                               raw register data
                                              ++
                                              + struct {
                                                 unsigned   rmtwkupsig:1
                                                 unsigned   rmtwkupsig:1
                                               Remote Wakeup.
                                                 unsigned   sftdiscon:1
                                                 unsigned   sftdiscon:1
                                               Soft Disconnect.
                                                 unsigned   gnpinnaksts:1
                                                 unsigned   gnpinnaksts:1
                                               Global Non-Periodic IN NAK Status.
                                                 unsigned   goutnaksts:1
                                                 unsigned   goutnaksts:1
                                               Global OUT NAK Status.
                                                 unsigned   tstctl:3
                                                 unsigned   tstctl:3
                                               Test Control.
                                                 unsigned   sgnpinnak:1
                                                 unsigned   sgnpinnak:1
                                               Set Global Non-Periodic IN NAK.
                                                 unsigned   cgnpinnak:1
                                                 unsigned   cgnpinnak:1
                                               Clear Global Non-Periodic IN NAK.
                                                 unsigned   sgoutnak:1
                                                 unsigned   sgoutnak:1
                                               Set Global OUT NAK.
                                                 unsigned   cgoutnak:1
                                                 unsigned   cgoutnak:1
                                               Clear Global OUT NAK.
                                                 unsigned   pwronprgdone:1
                                                 unsigned   pwronprgdone:1
                                               Power-On Programming Done.
                                                 unsigned   gcontbna:1
                                                 unsigned   reserved:1
                                               Global Continue on BNA.
                                                 unsigned   gmc:2
                                               Reserved.
                                                 unsigned   gmc:2
                                               Global Multi Count.
                                                 unsigned   ifrmnum:1
                                                 unsigned   ifrmnum:1
                                               Ignore Frame Number for ISOC EPs.
                                                 unsigned   nakonbble:1
                                                 unsigned   nakonbble:1
                                               NAK on Babble.
                                                 unsigned   reserved17_31:15
                                                 unsigned   encontonbna:1
                                              } b
                                               Enable Continue on BNA.
                                                 unsigned   reserved18_31:14
                                              } b
                                               register bits
                                              +@@ -87,10 +78,10 @@ +

                                              + +

                                              +-Definition at line 957 of file dwc_otg_regs.h.

                                              The documentation for this union was generated from the following file:
                                                ++Definition at line 1176 of file dwc_otg_regs.h.
                                                The documentation for this union was generated from the following file: +-
                                                Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++
                                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
                                                ++doxygen 1.3.9.1
                                                + + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/uniondepctl__data.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/uniondepctl__data.html 2013-07-26 19:31:22.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/uniondepctl__data.html 2013-07-26 19:34:43.000000000 +0000 +@@ -2,22 +2,10 @@ + + DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: depctl_data Union Reference + +- + +- +-
                                                +-
                                                +-
                                                +-
                                                +-

                                                depctl_data Union Reference

                                                This union represents the bit fields in the Device EP Control Register. ++ ++
                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                ++

                                                depctl_data Union Reference

                                                This union represents the bit fields in the Device EP Control Register. + More... +

                                                + #include <dwc_otg_regs.h> +@@ -25,59 +13,59 @@ + + + +- ++ + + +- + +- ++ + + +- ++ + + +- ++ + + +- ++ + +- +- ++ ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ + +- +- ++ ++ + +- +- ++ ++ + + +- ++ + + +- ++ + + +

                                                Data Fields

                                                +-uint32_t d32
                                                ++uint32_t d32
                                                 raw register data
                                                ++
                                                + struct {
                                                   unsigned   mps:11
                                                   unsigned   mps:11
                                                 Maximum Packet Size IN/OUT EPn IN/OUT EP0 - 2 bits 2'b00: 64 Bytes 2'b01: 32 2'b10: 16 2'b11: 8.
                                                   unsigned   nextep:4
                                                   unsigned   nextep:4
                                                 Next Endpoint IN EPn/IN EP0 OUT EPn/OUT EP0 - reserved.
                                                   unsigned   usbactep:1
                                                   unsigned   usbactep:1
                                                 USB Active Endpoint.
                                                   unsigned   dpid:1
                                                   unsigned   dpid:1
                                                 Endpoint DPID (INTR/Bulk IN and OUT endpoints) This field contains the PID of the packet going to be received or transmitted on this endpoint.
                                                   unsigned   naksts:1
                                                 Endpoint DPID (INTR/Bulk IN and OUT endpoints) This field contains the PID of the packet going to be received or transmitted on this endpoint.
                                                   unsigned   naksts:1
                                                 NAK Status.
                                                   unsigned   eptype:2
                                                   unsigned   eptype:2
                                                 Endpoint Type 2'b00: Control 2'b01: Isochronous 2'b10: Bulk 2'b11: Interrupt.
                                                   unsigned   snp:1
                                                   unsigned   snp:1
                                                 Snoop Mode OUT EPn/OUT EP0 IN EPn/IN EP0 - reserved.
                                                   unsigned   stall:1
                                                   unsigned   stall:1
                                                 Stall Handshake.
                                                   unsigned   txfnum:4
                                                   unsigned   txfnum:4
                                                 Tx Fifo Number IN EPn/IN EP0 OUT EPn/OUT EP0 - reserved.
                                                   unsigned   cnak:1
                                                   unsigned   cnak:1
                                                 Clear NAK.
                                                   unsigned   snak:1
                                                   unsigned   snak:1
                                                 Set NAK.
                                                   unsigned   setd0pid:1
                                                   unsigned   setd0pid:1
                                                 Set DATA0 PID (INTR/Bulk IN and OUT endpoints) Writing to this field sets the Endpoint DPID (DPID) field in this register to DATA0.
                                                   unsigned   setd1pid:1
                                                 Set DATA0 PID (INTR/Bulk IN and OUT endpoints) Writing to this field sets the Endpoint DPID (DPID) field in this register to DATA0.
                                                   unsigned   setd1pid:1
                                                 Set DATA1 PID (INTR/Bulk IN and OUT endpoints) Writing to this field sets the Endpoint DPID (DPID) field in this register to DATA1 Set Odd (micro)frame (SetOddFr) (ISO IN and OUT Endpoints) Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to odd (micro) frame.
                                                   unsigned   epdis:1
                                                 Set DATA1 PID (INTR/Bulk IN and OUT endpoints) Writing to this field sets the Endpoint DPID (DPID) field in this register to DATA1 Set Odd (micro)frame (SetOddFr) (ISO IN and OUT Endpoints) Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to odd (micro) frame.
                                                   unsigned   epdis:1
                                                 Endpoint Disable.
                                                   unsigned   epena:1
                                                   unsigned   epena:1
                                                 Endpoint Enable.
                                                } b
                                                } b
                                                 register bits
                                                +@@ -88,52 +76,95 @@ +

                                                + +

                                                +-Definition at line 1304 of file dwc_otg_regs.h.

                                                Field Documentation

                                                +- +-
                                                +-
                                                +- ++Definition at line 1526 of file dwc_otg_regs.h.

                                                Field Documentation

                                                ++

                                                ++

                                                ++ ++ ++ ++
                                                ++ + +- ++ + +
                                                unsigned depctl_data::dpid unsigned depctl_data::dpid
                                                +- +-
                                                ++
                                                ++ ++ ++ ++
                                                ++   ++ + +

                                                + Endpoint DPID (INTR/Bulk IN and OUT endpoints) This field contains the PID of the packet going to be received or transmitted on this endpoint. +

                                                + The application should program the PID of the first packet going to be received or transmitted on this endpoint , after the endpoint is activated. Application use the SetD1PID and SetD0PID fields of this register to program either D0 or D1 PID.

                                                + The encoding for this field is

                                                  +-
                                                • 0: D0
                                                • 1: D1
                                                ++
                                              • 0: D0
                                              • 1: D1
                                                • + +

                                                +-Definition at line 1344 of file dwc_otg_regs.h. +- +-

                                                +- +-

                                                +-
                                                +- ++Definition at line 1566 of file dwc_otg_regs.h. ++ ++
                                                ++

                                                ++ ++ ++ ++ ++
                                                ++ + +- ++ + +
                                                unsigned depctl_data::setd0pid unsigned depctl_data::setd0pid
                                                +- +-
                                                ++
                                                ++ ++ ++ ++ ++ ++
                                                ++   ++ + +

                                                + Set DATA0 PID (INTR/Bulk IN and OUT endpoints) Writing to this field sets the Endpoint DPID (DPID) field in this register to DATA0. +

                                                +-Set Even (micro)frame (SetEvenFr) (ISO IN and OUT Endpoints) Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to even (micro) frame. ++Set Even (micro)frame (SetEvenFr) (ISO IN and OUT Endpoints) Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to even (micro) frame. ++

                                                ++Definition at line 1603 of file dwc_otg_regs.h.

                                                ++

                                                ++ ++ ++ ++ ++
                                                ++ ++ ++ ++ ++
                                                unsigned depctl_data::setd1pid
                                                ++
                                                ++ ++ ++ ++ ++ ++
                                                ++   ++ ++ ++

                                                ++Set DATA1 PID (INTR/Bulk IN and OUT endpoints) Writing to this field sets the Endpoint DPID (DPID) field in this register to DATA1 Set Odd (micro)frame (SetOddFr) (ISO IN and OUT Endpoints) Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to odd (micro) frame. +

                                                +-Definition at line 1381 of file dwc_otg_regs.h. +- +-

                                                ++ ++

                                                ++Definition at line 1611 of file dwc_otg_regs.h.

                                                +

                                                The documentation for this union was generated from the following file: +-
                                                Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++
                                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
                                                ++doxygen 1.3.9.1
                                                + + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/uniondeptsiz0__data.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/uniondeptsiz0__data.html 2013-07-26 19:31:22.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/uniondeptsiz0__data.html 2013-07-26 19:34:43.000000000 +0000 +@@ -2,22 +2,10 @@ + + DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: deptsiz0_data Union Reference + +- + +- +-
                                                +-
                                                +-
                                                +-
                                                +-

                                                deptsiz0_data Union Reference

                                                This union represents the bit fields in the Device EP 0 Transfer Size Register. ++ ++
                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                ++

                                                deptsiz0_data Union Reference

                                                This union represents the bit fields in the Device EP 0 Transfer Size Register. + More... +

                                                + #include <dwc_otg_regs.h> +@@ -25,31 +13,31 @@ + + + +- ++ + + +- + +- ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ + +- ++ + + +

                                                Data Fields

                                                +-uint32_t d32
                                                ++uint32_t d32
                                                 raw register data
                                                ++
                                                + struct {
                                                   unsigned   xfersize:7
                                                   unsigned   xfersize:7
                                                 Transfer size.
                                                   unsigned   reserved7_18:12
                                                   unsigned   reserved7_18:12
                                                 Reserved.
                                                   unsigned   pktcnt:1
                                                   unsigned   pktcnt:2
                                                 Packet Count.
                                                   unsigned   reserved20_28:9
                                                   unsigned   reserved21_28:8
                                                 Reserved.
                                                   unsigned   supcnt:2
                                                   unsigned   supcnt:2
                                                 Setup Packet Count (DOEPTSIZ0 Only).
                                                   unsigned   reserved31
                                                   unsigned   reserved31
                                                } b
                                                } b
                                                 register bits
                                                +@@ -60,10 +48,10 @@ +

                                                + +

                                                +-Definition at line 1423 of file dwc_otg_regs.h.

                                                The documentation for this union was generated from the following file:
                                                  ++Definition at line 1647 of file dwc_otg_regs.h.
                                                  The documentation for this union was generated from the following file: +-
                                                  Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++
                                                  Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
                                                  ++doxygen 1.3.9.1
                                                  + + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/uniondeptsiz__data.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/uniondeptsiz__data.html 2013-07-26 19:31:22.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/uniondeptsiz__data.html 2013-07-26 19:34:43.000000000 +0000 +@@ -2,22 +2,10 @@ + + DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: deptsiz_data Union Reference + +- + +- +-
                                                  +-
                                                  +-
                                                  +-
                                                  +-

                                                  deptsiz_data Union Reference

                                                  This union represents the bit fields in the Device EP Transfer Size Register. ++ ++
                                                  Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                  ++

                                                  deptsiz_data Union Reference

                                                  This union represents the bit fields in the Device EP Transfer Size Register. + More... +

                                                  + #include <dwc_otg_regs.h> +@@ -25,25 +13,25 @@ + + + +- ++ + + +- + +- ++ + + +- ++ + + +- ++ + + +- ++ + +- ++ + + +

                                                  Data Fields

                                                  +-uint32_t d32
                                                  ++uint32_t d32
                                                   raw register data
                                                  ++
                                                  + struct {
                                                     unsigned   xfersize:19
                                                     unsigned   xfersize:19
                                                   Transfer size.
                                                     unsigned   pktcnt:10
                                                     unsigned   pktcnt:10
                                                   Packet Count.
                                                     unsigned   mc:2
                                                     unsigned   mc:2
                                                   Multi Count - Periodic IN endpoints.
                                                     unsigned   reserved:1
                                                     unsigned   reserved:1
                                                  } b
                                                  } b
                                                   register bits
                                                  +@@ -54,10 +42,10 @@ +

                                                  + +

                                                  +-Definition at line 1403 of file dwc_otg_regs.h.

                                                  The documentation for this union was generated from the following file:
                                                    ++Definition at line 1625 of file dwc_otg_regs.h.
                                                    The documentation for this union was generated from the following file: +-
                                                    Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++
                                                    Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
                                                    ++doxygen 1.3.9.1
                                                    + + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/uniondev__dma__desc__sts.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/uniondev__dma__desc__sts.html 2013-07-26 19:31:22.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/uniondev__dma__desc__sts.html 2013-07-26 19:34:43.000000000 +0000 +@@ -2,22 +2,10 @@ + + DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dev_dma_desc_sts Union Reference + +- + +- +-
                                                    +-
                                                    +-
                                                    +-
                                                    +-

                                                    dev_dma_desc_sts Union Reference

                                                    This union represents the bit fields in the DMA Descriptor status quadlet. ++ ++
                                                    Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                    ++

                                                    dev_dma_desc_sts Union Reference

                                                    This union represents the bit fields in the DMA Descriptor status quadlet. + More... +

                                                    + #include <dwc_otg_regs.h> +@@ -25,102 +13,105 @@ + + + +- ++ + + +- + +- ++ + + +- ++ + +- ++ ++ ++ ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ + + +- + +- ++ + + +- ++ + +- ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ + + +- + +- ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ + + +

                                                    Data Fields

                                                    +-uint32_t d32
                                                    ++uint32_t d32
                                                     raw register data
                                                    ++
                                                    + struct {
                                                       unsigned   bytes:16
                                                       unsigned   bytes:16
                                                     Received number of bytes.
                                                       unsigned   reserved16_22:7
                                                       unsigned   nak:1
                                                       unsigned   mtrf:1
                                                     NAK bit - only for OUT EPs.
                                                       unsigned   reserved17_22:6
                                                       unsigned   mtrf:1
                                                     Multiple Transfer - only for OUT EPs.
                                                       unsigned   sr:1
                                                       unsigned   sr:1
                                                     Setup Packet received - only for OUT EPs.
                                                       unsigned   ioc:1
                                                       unsigned   ioc:1
                                                     Interrupt On Complete.
                                                       unsigned   sp:1
                                                       unsigned   sp:1
                                                     Short Packet.
                                                       unsigned   l:1
                                                       unsigned   l:1
                                                     Last.
                                                       unsigned   sts:2
                                                       unsigned   sts:2
                                                     Receive Status.
                                                       unsigned   bs:2
                                                       unsigned   bs:2
                                                     Buffer Status.
                                                    } b
                                                    } b
                                                     quadlet bits
                                                    ++
                                                    + struct {
                                                       unsigned   rxbytes:11
                                                       unsigned   rxbytes:11
                                                     Received number of bytes.
                                                       unsigned   reserved11:1
                                                       unsigned   reserved11:1
                                                       unsigned   framenum:11
                                                       unsigned   framenum:11
                                                     Frame Number.
                                                       unsigned   pid:2
                                                       unsigned   pid:2
                                                     Received ISO Data PID.
                                                       unsigned   ioc:1
                                                       unsigned   ioc:1
                                                     Interrupt On Complete.
                                                       unsigned   sp:1
                                                       unsigned   sp:1
                                                     Short Packet.
                                                       unsigned   l:1
                                                       unsigned   l:1
                                                     Last.
                                                       unsigned   rxsts:2
                                                       unsigned   rxsts:2
                                                     Receive Status.
                                                       unsigned   bs:2
                                                       unsigned   bs:2
                                                     Buffer Status.
                                                    } b_iso_out
                                                    } b_iso_out
                                                     iso out quadlet bits
                                                    ++
                                                    + struct {
                                                       unsigned   txbytes:12
                                                       unsigned   txbytes:12
                                                     Transmited number of bytes.
                                                       unsigned   framenum:11
                                                       unsigned   framenum:11
                                                     Frame Number.
                                                       unsigned   pid:2
                                                       unsigned   pid:2
                                                     Transmited ISO Data PID.
                                                       unsigned   ioc:1
                                                       unsigned   ioc:1
                                                     Interrupt On Complete.
                                                       unsigned   sp:1
                                                       unsigned   sp:1
                                                     Short Packet.
                                                       unsigned   l:1
                                                       unsigned   l:1
                                                     Last.
                                                       unsigned   txsts:2
                                                       unsigned   txsts:2
                                                     Transmit Status.
                                                       unsigned   bs:2
                                                       unsigned   bs:2
                                                     Buffer Status.
                                                    } b_iso_in
                                                    } b_iso_in
                                                     iso in quadlet bits
                                                    +@@ -131,10 +122,10 @@ +

                                                    + +

                                                    +-Definition at line 1466 of file dwc_otg_regs.h.

                                                    The documentation for this union was generated from the following file:
                                                      ++Definition at line 1690 of file dwc_otg_regs.h.
                                                      The documentation for this union was generated from the following file: +-
                                                      Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++
                                                      Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
                                                      ++doxygen 1.3.9.1
                                                      + + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/uniondevice__grxsts__data.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/uniondevice__grxsts__data.html 2013-07-26 19:31:22.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/uniondevice__grxsts__data.html 2013-07-26 19:34:43.000000000 +0000 +@@ -2,22 +2,10 @@ + + DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: device_grxsts_data Union Reference + +- + +- +-
                                                      +-
                                                      +-
                                                      +-
                                                      +-

                                                      device_grxsts_data Union Reference

                                                      This union represents the bit fields in the Device Receive Status Read and Pop Registers (GRXSTSR, GRXSTSP) Read the register into the d32 element then read out the bits using the bit elements. ++ ++
                                                      Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                      ++

                                                      device_grxsts_data Union Reference

                                                      This union represents the bit fields in the Device Receive Status Read and Pop Registers (GRXSTSR, GRXSTSP) Read the register into the d32 element then read out the bits using the bit elements. + More... +

                                                      + #include <dwc_otg_regs.h> +@@ -25,26 +13,26 @@ + + + +- ++ + + +- + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + + +

                                                      Data Fields

                                                      +-uint32_t d32
                                                      ++uint32_t d32
                                                       raw register data
                                                      ++
                                                      + struct {
                                                         unsigned   epnum:4
                                                         unsigned   epnum:4
                                                         unsigned   bcnt:11
                                                         unsigned   bcnt:11
                                                         unsigned   dpid:2
                                                         unsigned   dpid:2
                                                         unsigned   pktsts:4
                                                         unsigned   pktsts:4
                                                         unsigned   fn:4
                                                         unsigned   fn:4
                                                         unsigned   reserved:7
                                                         unsigned   reserved25_31:7
                                                      } b
                                                      } b
                                                       register bits
                                                      +@@ -53,10 +41,10 @@ +

                                                      + +

                                                      +-Definition at line 601 of file dwc_otg_regs.h.

                                                      The documentation for this union was generated from the following file:
                                                        ++Definition at line 522 of file dwc_otg_regs.h.
                                                        The documentation for this union was generated from the following file: +-
                                                        Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++
                                                        Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
                                                        ++doxygen 1.3.9.1
                                                        + + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/uniondiepint__data.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/uniondiepint__data.html 2013-07-26 19:31:22.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/uniondiepint__data.html 2013-07-26 19:34:43.000000000 +0000 +@@ -2,22 +2,10 @@ + + DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: diepint_data Union Reference + +- + +- +-
                                                        +-
                                                        +-
                                                        +-
                                                        +-

                                                        diepint_data Union Reference

                                                        This union represents the bit fields in the Device IN EP Interrupt Register and the Device IN EP Common Mask Register. ++ ++
                                                        Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                        ++

                                                        diepint_data Union Reference

                                                        This union represents the bit fields in the Device IN EP Interrupt Register and the Device IN EP Common Mask Register. + More... +

                                                        + #include <dwc_otg_regs.h> +@@ -25,50 +13,50 @@ + + + +- ++ + + +- + +- ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ + +- +- ++ ++ + +- +- ++ ++ + +- ++ + + +- ++ + +- ++ + + +- ++ + +- ++ + + +

                                                        Data Fields

                                                        +-uint32_t d32
                                                        ++uint32_t d32
                                                         raw register data
                                                        ++
                                                        + struct {
                                                           unsigned   xfercompl:1
                                                           unsigned   xfercompl:1
                                                         Transfer complete mask.
                                                           unsigned   epdisabled:1
                                                           unsigned   epdisabled:1
                                                         Endpoint disable mask.
                                                           unsigned   ahberr:1
                                                           unsigned   ahberr:1
                                                         AHB Error mask.
                                                           unsigned   timeout:1
                                                           unsigned   timeout:1
                                                         TimeOUT Handshake mask (non-ISOC EPs).
                                                           unsigned   intktxfemp:1
                                                           unsigned   intktxfemp:1
                                                         IN Token received with TxF Empty mask.
                                                           unsigned   intknepmis:1
                                                           unsigned   intknepmis:1
                                                         IN Token Received with EP mismatch mask.
                                                           unsigned   inepnakeff:1
                                                           unsigned   inepnakeff:1
                                                         IN Endpoint HAK Effective mask.
                                                           unsigned   emptyintr:1
                                                         IN Endpoint NAK Effective mask.
                                                           unsigned   emptyintr:1
                                                         IN Endpoint HAK Effective mask.
                                                           unsigned   txfifoundrn:1
                                                         Reserved.
                                                           unsigned   txfifoundrn:1
                                                           unsigned   bna:1
                                                           unsigned   bna:1
                                                         BNA Interrupt mask.
                                                           unsigned   reserved10_12:3
                                                           unsigned   reserved10_12:3
                                                           unsigned   nak:1
                                                           unsigned   nak:1
                                                         BNA Interrupt mask.
                                                           unsigned   reserved14_31:18
                                                           unsigned   reserved14_31:18
                                                        } b
                                                        } b
                                                         register bits
                                                        +@@ -81,10 +69,10 @@ +

                                                        + +

                                                        +-Definition at line 1030 of file dwc_otg_regs.h.

                                                        The documentation for this union was generated from the following file:
                                                          ++Definition at line 1250 of file dwc_otg_regs.h.
                                                          The documentation for this union was generated from the following file: +-
                                                          Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++
                                                          Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
                                                          ++doxygen 1.3.9.1
                                                          + + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/uniondoepint__data.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/uniondoepint__data.html 2013-07-26 19:31:22.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/uniondoepint__data.html 2013-07-26 19:34:43.000000000 +0000 +@@ -2,22 +2,10 @@ + + DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: doepint_data Union Reference + +- + +- +-
                                                          +-
                                                          +-
                                                          +-
                                                          +-

                                                          doepint_data Union Reference

                                                          This union represents the bit fields in the Device OUT EP Interrupt Registerand Device OUT EP Common Interrupt Mask Register. ++ ++
                                                          Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                          ++

                                                          doepint_data Union Reference

                                                          This union represents the bit fields in the Device OUT EP Interrupt Registerand Device OUT EP Common Interrupt Mask Register. + More... +

                                                          + #include <dwc_otg_regs.h> +@@ -25,58 +13,58 @@ + + + +- ++ + + +- + +- ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ + +- ++ + + +- ++ + +- ++ + + +- ++ + + +- ++ + +- ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ + +- ++ + + +

                                                          Data Fields

                                                          +-uint32_t d32
                                                          ++uint32_t d32
                                                           raw register data
                                                          ++
                                                          + struct {
                                                             unsigned   xfercompl:1
                                                             unsigned   xfercompl:1
                                                           Transfer complete.
                                                             unsigned   epdisabled:1
                                                             unsigned   epdisabled:1
                                                           Endpoint disable.
                                                             unsigned   ahberr:1
                                                             unsigned   ahberr:1
                                                           AHB Error.
                                                             unsigned   setup:1
                                                             unsigned   setup:1
                                                           Setup Phase Done (contorl EPs).
                                                             unsigned   outtknepdis:1
                                                             unsigned   outtknepdis:1
                                                           OUT Token Received when Endpoint Disabled.
                                                             unsigned   stsphsercvd:1
                                                             unsigned   stsphsercvd:1
                                                             unsigned   back2backsetup:1
                                                             unsigned   back2backsetup:1
                                                           Back-to-Back SETUP Packets Received.
                                                             unsigned   reserved7:1
                                                             unsigned   reserved7:1
                                                             unsigned   outpkterr:1
                                                             unsigned   outpkterr:1
                                                           OUT packet Error.
                                                             unsigned   bna:1
                                                             unsigned   bna:1
                                                           BNA Interrupt.
                                                             unsigned   reserved10:1
                                                             unsigned   reserved10:1
                                                             unsigned   pktdrpsts:1
                                                             unsigned   pktdrpsts:1
                                                           Packet Drop Status.
                                                             unsigned   babble:1
                                                             unsigned   babble:1
                                                           Babble Interrupt.
                                                             unsigned   nak:1
                                                             unsigned   nak:1
                                                           NAK Interrupt.
                                                             unsigned   nyet:1
                                                             unsigned   nyet:1
                                                           NYET Interrupt.
                                                             unsigned   reserved15_31:17
                                                             unsigned   reserved15_31:17
                                                          } b
                                                          } b
                                                           register bits
                                                          +@@ -89,10 +77,10 @@ +

                                                          + +

                                                          +-Definition at line 1078 of file dwc_otg_regs.h.

                                                          The documentation for this union was generated from the following file:
                                                            ++Definition at line 1298 of file dwc_otg_regs.h.
                                                            The documentation for this union was generated from the following file: +-
                                                            Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++
                                                            Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
                                                            ++doxygen 1.3.9.1
                                                            + + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/uniondsts__data.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/uniondsts__data.html 2013-07-26 19:31:22.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/uniondsts__data.html 2013-07-26 19:34:43.000000000 +0000 +@@ -2,22 +2,10 @@ + + DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dsts_data Union Reference + +- + +- +-
                                                            +-
                                                            +-
                                                            +-
                                                            +-

                                                            dsts_data Union Reference

                                                            This union represents the bit fields in the Device Status Register. ++ ++
                                                            Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                            ++

                                                            dsts_data Union Reference

                                                            This union represents the bit fields in the Device Status Register. + More... +

                                                            + #include <dwc_otg_regs.h> +@@ -25,30 +13,30 @@ + + + +- ++ + + +- + +- ++ + + +- ++ + + +- ++ + + +- ++ + +- ++ + + +- ++ + +- ++ + + +

                                                            Data Fields

                                                            +-uint32_t d32
                                                            ++uint32_t d32
                                                             raw register data
                                                            ++
                                                            + struct {
                                                               unsigned   suspsts:1
                                                               unsigned   suspsts:1
                                                             Suspend Status.
                                                               unsigned   enumspd:2
                                                               unsigned   enumspd:2
                                                             Enumerated Speed.
                                                               unsigned   errticerr:1
                                                               unsigned   errticerr:1
                                                             Erratic Error.
                                                               unsigned   reserved4_7:4
                                                               unsigned   reserved4_7:4
                                                               unsigned   soffn:14
                                                               unsigned   soffn:14
                                                             Frame or Microframe Number of the received SOF.
                                                               unsigned   reserved22_31:10
                                                               unsigned   reserved22_31:10
                                                            } b
                                                            } b
                                                             register bits
                                                            +@@ -59,10 +47,10 @@ +

                                                            + +

                                                            +-Definition at line 1001 of file dwc_otg_regs.h.

                                                            The documentation for this union was generated from the following file:
                                                              ++Definition at line 1221 of file dwc_otg_regs.h.
                                                              The documentation for this union was generated from the following file: +-
                                                              Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++
                                                              Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
                                                              ++doxygen 1.3.9.1
                                                              + + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/uniondthrctl__data.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/uniondthrctl__data.html 2013-07-26 19:31:22.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/uniondthrctl__data.html 2013-07-26 19:34:43.000000000 +0000 +@@ -2,24 +2,10 @@ + + DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dthrctl_data Union Reference + +- + +- +-
                                                              +-
                                                              +-
                                                              +-
                                                              +-

                                                              dthrctl_data Union Reference

                                                              This union represents Threshold control Register
                                                                +-
                                                              • Read and write the register into the d32 member.
                                                              +- ++ ++
                                                              Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                              ++

                                                              dthrctl_data Union Reference

                                                              This union represents Threshold control Register Read and write the register into the d32 member. + More... +

                                                              + #include <dwc_otg_regs.h> +@@ -27,152 +13,195 @@ + + + +- ++ + + +- + +- ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + + +- ++ + + +- ++ + +- +- ++ ++ + +- +- ++ ++ ++ ++ ++ ++ ++ + + +- ++ + + +

                                                              Data Fields

                                                              +-uint32_t d32
                                                              ++uint32_t d32
                                                               raw register data
                                                              ++
                                                              + struct {
                                                                 unsigned   non_iso_thr_en:1
                                                                 unsigned   non_iso_thr_en:1
                                                               non ISO Tx Thr.
                                                                 unsigned   iso_thr_en:1
                                                               non ISO Tx Thr.
                                                                 unsigned   iso_thr_en:1
                                                               ISO Tx Thr.
                                                                 unsigned   tx_thr_len:9
                                                               ISO Tx Thr.
                                                                 unsigned   tx_thr_len:9
                                                               Tx Thr.
                                                                 unsigned   ahb_thr_ratio:2
                                                               Tx Thr.
                                                                 unsigned   ahb_thr_ratio:2
                                                               AHB Threshold ratio.
                                                                 unsigned   reserved13_15:3
                                                                 unsigned   reserved13_15:3
                                                               Reserved.
                                                                 unsigned   rx_thr_en:1
                                                                 unsigned   rx_thr_en:1
                                                               Rx Thr.
                                                                 unsigned   rx_thr_len:9
                                                               Rx Thr.
                                                                 unsigned   rx_thr_len:9
                                                               Rx Thr.
                                                                 unsigned   reserved26_31:6
                                                               Rx Thr.
                                                                 unsigned   reserved26:1
                                                                 unsigned   arbprken:1
                                                               Arbiter Parking Enable.
                                                                 unsigned   reserved28_31:4
                                                               Reserved.
                                                              } b
                                                              } b
                                                               register bits
                                                              +

                                                              Detailed Description

                                                              +-This union represents Threshold control Register
                                                                +-
                                                              • Read and write the register into the d32 member.
                                                              +- ++This union represents Threshold control Register Read and write the register into the d32 member. +

                                                              +

                                                                +-
                                                              • READ-WRITABLE Register
                                                              ++
                                                            • * - READ-WRITABLE Register
                                                            + +

                                                            + +

                                                            +-Definition at line 1205 of file dwc_otg_regs.h.

                                                            Field Documentation

                                                            +- +-
                                                            +-
                                                            +- ++Definition at line 1425 of file dwc_otg_regs.h.

                                                            Field Documentation

                                                            ++

                                                            ++

                                                            ++ ++ ++ ++
                                                            ++ + +- ++ + +
                                                            unsigned dthrctl_data::non_iso_thr_en unsigned dthrctl_data::non_iso_thr_en
                                                            +- +-
                                                            ++
                                                            ++ ++ ++ ++
                                                            ++   ++ + +

                                                            + non ISO Tx Thr. +

                                                            + Enable +

                                                            +-Definition at line 1211 of file dwc_otg_regs.h. +- +-

                                                            +- +-

                                                            +-
                                                            +- ++Definition at line 1431 of file dwc_otg_regs.h. ++ ++
                                                            ++

                                                            ++ ++ ++ ++ ++
                                                            ++ + +- ++ + +
                                                            unsigned dthrctl_data::iso_thr_en unsigned dthrctl_data::iso_thr_en
                                                            +- +-
                                                            ++
                                                            ++ ++ ++ ++
                                                            ++   ++ + +

                                                            + ISO Tx Thr. +

                                                            + Enable +

                                                            +-Definition at line 1213 of file dwc_otg_regs.h. +- +-

                                                            +- +-

                                                            +-
                                                            +- ++Definition at line 1433 of file dwc_otg_regs.h. ++ ++
                                                            ++

                                                            ++ ++ ++ ++ ++
                                                            ++ + +- ++ + +
                                                            unsigned dthrctl_data::tx_thr_len unsigned dthrctl_data::tx_thr_len
                                                            +- +-
                                                            ++
                                                            ++ ++ ++ ++
                                                            ++   ++ + +

                                                            + Tx Thr. +

                                                            + Length +

                                                            +-Definition at line 1215 of file dwc_otg_regs.h. +- +-

                                                            +- +-

                                                            +-
                                                            +- ++Definition at line 1435 of file dwc_otg_regs.h. ++ ++
                                                            ++

                                                            ++ ++ ++ ++ ++
                                                            ++ + +- ++ + +
                                                            unsigned dthrctl_data::rx_thr_en unsigned dthrctl_data::rx_thr_en
                                                            +- +-
                                                            ++
                                                            ++ ++ ++ ++
                                                            ++   ++ + +

                                                            + Rx Thr. +

                                                            + Enable +

                                                            +-Definition at line 1221 of file dwc_otg_regs.h. +- +-

                                                            +- +-

                                                            +-
                                                            +- ++Definition at line 1441 of file dwc_otg_regs.h. ++ ++
                                                            ++

                                                            ++ ++ ++ ++ ++
                                                            ++ + +- ++ + +
                                                            unsigned dthrctl_data::rx_thr_len unsigned dthrctl_data::rx_thr_len
                                                            +- +-
                                                            ++
                                                            ++ ++ ++ ++ ++ ++
                                                            ++   ++ + +

                                                            + Rx Thr. +

                                                            + Length +

                                                            +-Definition at line 1223 of file dwc_otg_regs.h. +- +-

                                                            ++Definition at line 1443 of file dwc_otg_regs.h.

                                                            +

                                                            The documentation for this union was generated from the following file: +-
                                                            Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++
                                                            Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
                                                            ++doxygen 1.3.9.1
                                                            + + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/uniondtknq1__data.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/uniondtknq1__data.html 2013-07-26 19:31:22.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/uniondtknq1__data.html 2013-07-26 19:34:43.000000000 +0000 +@@ -2,22 +2,10 @@ + + DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dtknq1_data Union Reference + +- + +- +-
                                                            +-
                                                            +-
                                                            +-
                                                            +-

                                                            dtknq1_data Union Reference

                                                            This union represents the bit fields in the Device IN Token Queue Read Registers. ++ ++
                                                            Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                            ++

                                                            dtknq1_data Union Reference

                                                            This union represents the bit fields in the Device IN Token Queue Read Registers. + More... +

                                                            + #include <dwc_otg_regs.h> +@@ -25,26 +13,26 @@ + + + +- ++ + + +- + +- ++ + + +- ++ + + +- ++ + + +- ++ + +- +- ++ ++ + + +

                                                            Data Fields

                                                            +-uint32_t d32
                                                            ++uint32_t d32
                                                             raw register data
                                                            ++
                                                            + struct {
                                                               unsigned   intknwptr:5
                                                               unsigned   intknwptr:5
                                                             In Token Queue Write Pointer.
                                                               unsigned   reserved05_06:2
                                                               unsigned   reserved05_06:2
                                                             Reserved.
                                                               unsigned   wrap_bit:1
                                                               unsigned   wrap_bit:1
                                                             write pointer has wrapped.
                                                               unsigned   epnums0_5:24
                                                               unsigned   epnums0_5:24
                                                             EP Numbers of IN Tokens 0 .
                                                            } b
                                                             EP Numbers of IN Tokens 0 ...
                                                            } b
                                                             register bits
                                                            +@@ -57,30 +45,38 @@ +

                                                            + +

                                                            +-Definition at line 1184 of file dwc_otg_regs.h.

                                                            Field Documentation

                                                            +- +-
                                                            +-
                                                            +- ++Definition at line 1404 of file dwc_otg_regs.h.

                                                            Field Documentation

                                                            ++

                                                            ++

                                                            ++ ++ ++ ++
                                                            ++ + +- ++ + +
                                                            unsigned dtknq1_data::epnums0_5 unsigned dtknq1_data::epnums0_5
                                                            +- +-
                                                            ++
                                                            ++ ++ ++ ++ ++ ++
                                                            ++   ++ + +

                                                            +-EP Numbers of IN Tokens 0 . ++EP Numbers of IN Tokens 0 ... +

                                                            +-.. 4 ++4 +

                                                            +-Definition at line 1196 of file dwc_otg_regs.h. +- +-

                                                            ++Definition at line 1416 of file dwc_otg_regs.h.

                                                            +
                                                            The documentation for this union was generated from the following file: +-
                                                            Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++
                                                            Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
                                                            ++doxygen 1.3.9.1
                                                            + + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/uniondtxfsts__data.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/uniondtxfsts__data.html 2013-07-26 19:31:22.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/uniondtxfsts__data.html 2013-07-26 19:34:43.000000000 +0000 +@@ -2,22 +2,10 @@ + + DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dtxfsts_data Union Reference + +- + +- +-
                                                            +-
                                                            +-
                                                            +-
                                                            +-

                                                            dtxfsts_data Union Reference

                                                            This union represents the bit fields in the Transmit FIFO Status Register (DTXFSTS). ++ ++
                                                            Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                            ++

                                                            dtxfsts_data Union Reference

                                                            This union represents the bit fields in the Transmit FIFO Status Register (DTXFSTS). + More... +

                                                            + #include <dwc_otg_regs.h> +@@ -25,18 +13,18 @@ + + + +- ++ + + +- + +- ++ + +- ++ + +- ++ + + +

                                                            Data Fields

                                                            +-uint32_t d32
                                                            ++uint32_t d32
                                                             raw register data
                                                            ++
                                                            + struct {
                                                               unsigned   txfspcavail:16
                                                               unsigned   txfspcavail:16
                                                               unsigned   reserved:16
                                                               unsigned   reserved:16
                                                            } b
                                                            } b
                                                             register bits
                                                            +@@ -47,10 +35,10 @@ +

                                                            + +

                                                            +-Definition at line 697 of file dwc_otg_regs.h.

                                                            The documentation for this union was generated from the following file:
                                                              ++Definition at line 618 of file dwc_otg_regs.h.
                                                              The documentation for this union was generated from the following file: +-
                                                              Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++
                                                              Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
                                                              ++doxygen 1.3.9.1
                                                              + + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/uniondwc__otg__hcd_1_1dwc__otg__hcd__internal__flags.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/uniondwc__otg__hcd_1_1dwc__otg__hcd__internal__flags.html 2013-07-26 19:31:22.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/uniondwc__otg__hcd_1_1dwc__otg__hcd__internal__flags.html 2013-07-26 19:34:43.000000000 +0000 +@@ -2,24 +2,10 @@ + + DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_hcd::dwc_otg_hcd_internal_flags Union Reference + +- + +- +-
                                                              +-
                                                              +-
                                                              +-
                                                              +-
                                                              +-dwc_otg_hcd::dwc_otg_hcd_internal_flags
                                                              +-

                                                              dwc_otg_hcd::dwc_otg_hcd_internal_flags Union Reference

                                                              Internal DWC HCD Flags. ++ ++
                                                              Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                              ++

                                                              dwc_otg_hcd::dwc_otg_hcd_internal_flags Union Reference

                                                              Internal DWC HCD Flags. + More... +

                                                              + #include <dwc_otg_hcd.h> +@@ -27,27 +13,27 @@ + + + +- ++ + +- + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + + + +@@ -57,10 +43,10 @@ +

                                                              + +

                                                              +-Definition at line 380 of file dwc_otg_hcd.h.

                                                              The documentation for this union was generated from the following file:
                                                                ++Definition at line 383 of file dwc_otg_hcd.h.
                                                                The documentation for this union was generated from the following file: +-
                                                                Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++
                                                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
                                                                ++doxygen 1.3.9.1
                                                                + + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/unionfifosize__data.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/unionfifosize__data.html 2013-07-26 19:31:22.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/unionfifosize__data.html 2013-07-26 19:34:43.000000000 +0000 +@@ -2,22 +2,10 @@ + + DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: fifosize_data Union Reference + +- + +- +-
                                                                +-
                                                                +-
                                                                +-
                                                                +-

                                                                fifosize_data Union Reference

                                                                This union represents the bit fields in the FIFO Size Registers (HPTXFSIZ, GNPTXFSIZ, DPTXFSIZn, DIEPTXFn). ++ ++
                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                ++

                                                                fifosize_data Union Reference

                                                                This union represents the bit fields in the FIFO Size Registers (HPTXFSIZ, GNPTXFSIZ, DPTXFSIZn, DIEPTXFn). + More... +

                                                                + #include <dwc_otg_regs.h> +@@ -25,18 +13,18 @@ +


                                                              Data Fields

                                                              +-uint32_t d32
                                                              ++uint32_t d32
                                                              ++
                                                              + struct {
                                                                 unsigned   port_connect_status_change:1
                                                                 unsigned   port_connect_status_change:1
                                                                 unsigned   port_connect_status:1
                                                                 unsigned   port_connect_status:1
                                                                 unsigned   port_reset_change:1
                                                                 unsigned   port_reset_change:1
                                                                 unsigned   port_enable_change:1
                                                                 unsigned   port_enable_change:1
                                                                 unsigned   port_suspend_change:1
                                                                 unsigned   port_suspend_change:1
                                                                 unsigned   port_over_current_change:1
                                                                 unsigned   port_over_current_change:1
                                                                 unsigned   port_l1_change:1
                                                                 unsigned   port_l1_change:1
                                                                 unsigned   reserved:26
                                                                 unsigned   reserved:26
                                                              } b
                                                              + + +- ++ + + +- + +- ++ + +- ++ + +- ++ + + +

                                                              Data Fields

                                                              +-uint32_t d32
                                                              ++uint32_t d32
                                                               raw register data
                                                              ++
                                                              + struct {
                                                                 unsigned   startaddr:16
                                                                 unsigned   startaddr:16
                                                                 unsigned   depth:16
                                                                 unsigned   depth:16
                                                              } b
                                                              } b
                                                               register bits
                                                              +@@ -47,10 +35,10 @@ +

                                                              + +

                                                              +-Definition at line 651 of file dwc_otg_regs.h.

                                                              The documentation for this union was generated from the following file:
                                                                ++Definition at line 572 of file dwc_otg_regs.h.
                                                                The documentation for this union was generated from the following file: +-
                                                                Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++
                                                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
                                                                ++doxygen 1.3.9.1
                                                                + + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/uniongahbcfg__data.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/uniongahbcfg__data.html 2013-07-26 19:31:22.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/uniongahbcfg__data.html 2013-07-26 19:34:43.000000000 +0000 +@@ -2,22 +2,10 @@ + + DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: gahbcfg_data Union Reference + +- + +- +-
                                                                +-
                                                                +-
                                                                +-
                                                                +-

                                                                gahbcfg_data Union Reference

                                                                This union represents the bit fields of the Core AHB Configuration Register (GAHBCFG). ++ ++
                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                ++

                                                                gahbcfg_data Union Reference

                                                                This union represents the bit fields of the Core AHB Configuration Register (GAHBCFG). + More... +

                                                                + #include <dwc_otg_regs.h> +@@ -25,28 +13,36 @@ + + + +- ++ + + +- + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ ++ ++ ++ ++ ++ ++ ++ ++ + + +

                                                                Data Fields

                                                                +-uint32_t d32
                                                                ++uint32_t d32
                                                                 raw register data
                                                                ++
                                                                + struct {
                                                                   unsigned   glblintrmsk:1
                                                                   unsigned   glblintrmsk:1
                                                                   unsigned   hburstlen:4
                                                                   unsigned   hburstlen:4
                                                                   unsigned   dmaenable:1
                                                                   unsigned   dmaenable:1
                                                                   unsigned   reserved:1
                                                                   unsigned   reserved:1
                                                                   unsigned   nptxfemplvl_txfemplvl:1
                                                                   unsigned   nptxfemplvl_txfemplvl:1
                                                                   unsigned   ptxfemplvl:1
                                                                   unsigned   ptxfemplvl:1
                                                                   unsigned   reserved9_31:23
                                                                   unsigned   reserved9_20:12
                                                                } b
                                                                   unsigned   remmemsupp:1
                                                                   unsigned   notialldmawrit:1
                                                                   unsigned   ahbsingle:1
                                                                   unsigned   reserved24_31:8
                                                                } b
                                                                 register bits
                                                                +@@ -57,10 +53,10 @@ +

                                                                + +

                                                                +-Definition at line 216 of file dwc_otg_regs.h.

                                                                The documentation for this union was generated from the following file:
                                                                  ++Definition at line 232 of file dwc_otg_regs.h.
                                                                  The documentation for this union was generated from the following file: +-
                                                                  Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++
                                                                  Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
                                                                  ++doxygen 1.3.9.1
                                                                  + + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/uniongdfifocfg__data.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/uniongdfifocfg__data.html 2013-07-26 19:34:43.000000000 +0000 +@@ -0,0 +1,45 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: gdfifocfg_data Union Reference ++ ++ ++ ++
                                                                  Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                  ++

                                                                  gdfifocfg_data Union Reference

                                                                  This union represents the bit fields in the Global Data FIFO Software Configuration Register. ++More... ++

                                                                  ++#include <dwc_otg_regs.h> ++

                                                                  ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++

                                                                  Data Fields

                                                                  ++uint32_t d32
                                                                  ++struct {
                                                                     unsigned   gdfifocfg:16
                                                                   OTG Data FIFO depth.
                                                                     unsigned   epinfobase:16
                                                                   Start address of EP info controller.
                                                                  } b
                                                                   register bits
                                                                  ++

                                                                  Detailed Description

                                                                  ++This union represents the bit fields in the Global Data FIFO Software Configuration Register. ++

                                                                  ++Read the register into the d32 member then set/clear the bits using the bit elements. ++

                                                                  ++ ++

                                                                  ++Definition at line 2469 of file dwc_otg_regs.h.

                                                                  The documentation for this union was generated from the following file: ++
                                                                  Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.3.9.1
                                                                  ++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/unionggpio__data.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/unionggpio__data.html 2013-07-26 19:34:43.000000000 +0000 +@@ -0,0 +1,44 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: ggpio_data Union Reference ++ ++ ++ ++
                                                                  Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                  ++

                                                                  ggpio_data Union Reference

                                                                  This union represents the bit fields in the General Purpose Input/Output Register (GGPIO). ++More... ++

                                                                  ++#include <dwc_otg_regs.h> ++

                                                                  ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++

                                                                  Data Fields

                                                                  ++uint32_t d32
                                                                   raw register data
                                                                  ++struct {
                                                                     unsigned   gpi:16
                                                                     unsigned   gpo:16
                                                                  } b
                                                                   register bits
                                                                  ++

                                                                  Detailed Description

                                                                  ++This union represents the bit fields in the General Purpose Input/Output Register (GGPIO). ++

                                                                  ++Read the register into the d32 element then read out the bits using the bit elements. ++

                                                                  ++ ++

                                                                  ++Definition at line 681 of file dwc_otg_regs.h.

                                                                  The documentation for this union was generated from the following file: ++
                                                                  Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.3.9.1
                                                                  ++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/uniongi2cctl__data.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/uniongi2cctl__data.html 2013-07-26 19:31:22.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/uniongi2cctl__data.html 2013-07-26 19:34:43.000000000 +0000 +@@ -2,22 +2,10 @@ + + DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: gi2cctl_data Union Reference + +- + +- +-
                                                                  +-
                                                                  +-
                                                                  +-
                                                                  +-

                                                                  gi2cctl_data Union Reference

                                                                  This union represents the bit fields in the I2C Control Register (I2CCTL). ++ ++
                                                                  Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                  ++

                                                                  gi2cctl_data Union Reference

                                                                  This union represents the bit fields in the I2C Control Register (I2CCTL). + More... +

                                                                  + #include <dwc_otg_regs.h> +@@ -25,34 +13,36 @@ + + + +- ++ + + +- + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ ++ ++ + + +

                                                                  Data Fields

                                                                  +-uint32_t d32
                                                                  ++uint32_t d32
                                                                   raw register data
                                                                  ++
                                                                  + struct {
                                                                     unsigned   rwdata:8
                                                                     unsigned   rwdata:8
                                                                     unsigned   regaddr:8
                                                                     unsigned   regaddr:8
                                                                     unsigned   addr:7
                                                                     unsigned   addr:7
                                                                     unsigned   i2cen:1
                                                                     unsigned   i2cen:1
                                                                     unsigned   ack:1
                                                                     unsigned   ack:1
                                                                     unsigned   i2csuspctl:1
                                                                     unsigned   i2csuspctl:1
                                                                     unsigned   i2cdevaddr:2
                                                                     unsigned   i2cdevaddr:2
                                                                     unsigned   reserved:2
                                                                     unsigned   i2cdatse0:1
                                                                     unsigned   rw:1
                                                                     unsigned   reserved:1
                                                                     unsigned   bsydne:1
                                                                     unsigned   rw:1
                                                                  } b
                                                                     unsigned   bsydne:1
                                                                  } b
                                                                   register bits
                                                                  +@@ -63,10 +53,10 @@ +

                                                                  + +

                                                                  +-Definition at line 712 of file dwc_otg_regs.h.

                                                                  The documentation for this union was generated from the following file:
                                                                    ++Definition at line 633 of file dwc_otg_regs.h.
                                                                    The documentation for this union was generated from the following file: +-
                                                                    Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++
                                                                    Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
                                                                    ++doxygen 1.3.9.1
                                                                    + + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/uniongintmsk__data.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/uniongintmsk__data.html 2013-07-26 19:31:22.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/uniongintmsk__data.html 2013-07-26 19:34:43.000000000 +0000 +@@ -2,22 +2,10 @@ + + DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: gintmsk_data Union Reference + +- + +- +-
                                                                    +-
                                                                    +-
                                                                    +-
                                                                    +-

                                                                    gintmsk_data Union Reference

                                                                    This union represents the bit fields of the Core Interrupt Mask Register (GINTMSK). ++ ++
                                                                    Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                    ++

                                                                    gintmsk_data Union Reference

                                                                    This union represents the bit fields of the Core Interrupt Mask Register (GINTMSK). + More... +

                                                                    + #include <dwc_otg_regs.h> +@@ -25,76 +13,78 @@ + + + +- ++ + + +- + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ ++ ++ + + +

                                                                    Data Fields

                                                                    +-uint32_t d32
                                                                    ++uint32_t d32
                                                                     raw register data
                                                                    ++
                                                                    + struct {
                                                                       unsigned   reserved0:1
                                                                       unsigned   reserved0:1
                                                                       unsigned   modemismatch:1
                                                                       unsigned   modemismatch:1
                                                                       unsigned   otgintr:1
                                                                       unsigned   otgintr:1
                                                                       unsigned   sofintr:1
                                                                       unsigned   sofintr:1
                                                                       unsigned   rxstsqlvl:1
                                                                       unsigned   rxstsqlvl:1
                                                                       unsigned   nptxfempty:1
                                                                       unsigned   nptxfempty:1
                                                                       unsigned   ginnakeff:1
                                                                       unsigned   ginnakeff:1
                                                                       unsigned   goutnakeff:1
                                                                       unsigned   goutnakeff:1
                                                                       unsigned   reserved8:1
                                                                       unsigned   ulpickint:1
                                                                       unsigned   i2cintr:1
                                                                       unsigned   i2cintr:1
                                                                       unsigned   erlysuspend:1
                                                                       unsigned   erlysuspend:1
                                                                       unsigned   usbsuspend:1
                                                                       unsigned   usbsuspend:1
                                                                       unsigned   usbreset:1
                                                                       unsigned   usbreset:1
                                                                       unsigned   enumdone:1
                                                                       unsigned   enumdone:1
                                                                       unsigned   isooutdrop:1
                                                                       unsigned   isooutdrop:1
                                                                       unsigned   eopframe:1
                                                                       unsigned   eopframe:1
                                                                       unsigned   reserved16:1
                                                                       unsigned   restoredone:1
                                                                       unsigned   epmismatch:1
                                                                       unsigned   epmismatch:1
                                                                       unsigned   inepintr:1
                                                                       unsigned   inepintr:1
                                                                       unsigned   outepintr:1
                                                                       unsigned   outepintr:1
                                                                       unsigned   incomplisoin:1
                                                                       unsigned   incomplisoin:1
                                                                       unsigned   incomplisoout:1
                                                                       unsigned   incomplisoout:1
                                                                       unsigned   reserved22_23:2
                                                                       unsigned   fetsusp:1
                                                                       unsigned   portintr:1
                                                                       unsigned   resetdet:1
                                                                       unsigned   hcintr:1
                                                                       unsigned   portintr:1
                                                                       unsigned   ptxfempty:1
                                                                       unsigned   hcintr:1
                                                                       unsigned   lpmtranrcvd:1
                                                                       unsigned   ptxfempty:1
                                                                       unsigned   conidstschng:1
                                                                       unsigned   lpmtranrcvd:1
                                                                       unsigned   disconnect:1
                                                                       unsigned   conidstschng:1
                                                                       unsigned   sessreqintr:1
                                                                       unsigned   disconnect:1
                                                                       unsigned   wkupintr:1
                                                                       unsigned   sessreqintr:1
                                                                    } b
                                                                       unsigned   wkupintr:1
                                                                    } b
                                                                     register bits
                                                                    +@@ -105,10 +95,10 @@ +

                                                                    + +

                                                                    +-Definition at line 512 of file dwc_otg_regs.h.

                                                                    The documentation for this union was generated from the following file:
                                                                      ++Definition at line 431 of file dwc_otg_regs.h.
                                                                      The documentation for this union was generated from the following file: +-
                                                                      Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++
                                                                      Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
                                                                      ++doxygen 1.3.9.1
                                                                      + + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/uniongintsts__data.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/uniongintsts__data.html 2013-07-26 19:31:22.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/uniongintsts__data.html 2013-07-26 19:34:43.000000000 +0000 +@@ -2,22 +2,10 @@ + + DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: gintsts_data Union Reference + +- + +- +-
                                                                      +-
                                                                      +-
                                                                      +-
                                                                      +-

                                                                      gintsts_data Union Reference

                                                                      This union represents the bit fields of the Core Interrupt Register (GINTSTS). ++ ++
                                                                      Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                      ++

                                                                      gintsts_data Union Reference

                                                                      This union represents the bit fields of the Core Interrupt Register (GINTSTS). + More... +

                                                                      + #include <dwc_otg_regs.h> +@@ -25,76 +13,78 @@ + + + +- ++ + + +- + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ ++ ++ + + +

                                                                      Data Fields

                                                                      +-uint32_t d32
                                                                      ++uint32_t d32
                                                                       raw register data
                                                                      ++
                                                                      + struct {
                                                                         unsigned   curmode:1
                                                                         unsigned   curmode:1
                                                                         unsigned   modemismatch:1
                                                                         unsigned   modemismatch:1
                                                                         unsigned   otgintr:1
                                                                         unsigned   otgintr:1
                                                                         unsigned   sofintr:1
                                                                         unsigned   sofintr:1
                                                                         unsigned   rxstsqlvl:1
                                                                         unsigned   rxstsqlvl:1
                                                                         unsigned   nptxfempty:1
                                                                         unsigned   nptxfempty:1
                                                                         unsigned   ginnakeff:1
                                                                         unsigned   ginnakeff:1
                                                                         unsigned   goutnakeff:1
                                                                         unsigned   goutnakeff:1
                                                                         unsigned   reserved8:1
                                                                         unsigned   ulpickint:1
                                                                         unsigned   i2cintr:1
                                                                         unsigned   i2cintr:1
                                                                         unsigned   erlysuspend:1
                                                                         unsigned   erlysuspend:1
                                                                         unsigned   usbsuspend:1
                                                                         unsigned   usbsuspend:1
                                                                         unsigned   usbreset:1
                                                                         unsigned   usbreset:1
                                                                         unsigned   enumdone:1
                                                                         unsigned   enumdone:1
                                                                         unsigned   isooutdrop:1
                                                                         unsigned   isooutdrop:1
                                                                         unsigned   eopframe:1
                                                                         unsigned   eopframe:1
                                                                         unsigned   intokenrx:1
                                                                         unsigned   restoredone:1
                                                                         unsigned   epmismatch:1
                                                                         unsigned   epmismatch:1
                                                                         unsigned   inepint:1
                                                                         unsigned   inepint:1
                                                                         unsigned   outepintr:1
                                                                         unsigned   outepintr:1
                                                                         unsigned   incomplisoin:1
                                                                         unsigned   incomplisoin:1
                                                                         unsigned   incomplisoout:1
                                                                         unsigned   incomplisoout:1
                                                                         unsigned   reserved22_23:2
                                                                         unsigned   fetsusp:1
                                                                         unsigned   portintr:1
                                                                         unsigned   resetdet:1
                                                                         unsigned   hcintr:1
                                                                         unsigned   portintr:1
                                                                         unsigned   ptxfempty:1
                                                                         unsigned   hcintr:1
                                                                         unsigned   lpmtranrcvd:1
                                                                         unsigned   ptxfempty:1
                                                                         unsigned   conidstschng:1
                                                                         unsigned   lpmtranrcvd:1
                                                                         unsigned   disconnect:1
                                                                         unsigned   conidstschng:1
                                                                         unsigned   sessreqintr:1
                                                                         unsigned   disconnect:1
                                                                         unsigned   wkupintr:1
                                                                         unsigned   sessreqintr:1
                                                                      } b
                                                                         unsigned   wkupintr:1
                                                                      } b
                                                                       register bits
                                                                      +@@ -105,10 +95,10 @@ +

                                                                      + +

                                                                      +-Definition at line 555 of file dwc_otg_regs.h.

                                                                      The documentation for this union was generated from the following file:
                                                                        ++Definition at line 475 of file dwc_otg_regs.h.
                                                                        The documentation for this union was generated from the following file: +-
                                                                        Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++
                                                                        Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
                                                                        ++doxygen 1.3.9.1
                                                                        + + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/unionglpmctl__data.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/unionglpmctl__data.html 2013-07-26 19:31:22.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/unionglpmctl__data.html 2013-07-26 19:34:43.000000000 +0000 +@@ -2,22 +2,10 @@ + + DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: glpmctl_data Union Reference + +- + +- +-
                                                                        +-
                                                                        +-
                                                                        +-
                                                                        +-

                                                                        glpmctl_data Union Reference

                                                                        This union represents the bit fields of the Core LPM Configuration Register (GLPMCFG). ++ ++
                                                                        Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                        ++

                                                                        glpmctl_data Union Reference

                                                                        This union represents the bit fields of the Core LPM Configuration Register (GLPMCFG). + More... +

                                                                        + #include <dwc_otg_regs.h> +@@ -25,61 +13,61 @@ + + + +- ++ + + +- + +- ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + + +- ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + + +- ++ + +- ++ + +- +- ++ ++ + +- +- ++ ++ + + +

                                                                        Data Fields

                                                                        +-uint32_t d32
                                                                        ++uint32_t d32
                                                                         raw register data
                                                                        ++
                                                                        + struct {
                                                                           unsigned   lpm_cap_en:1
                                                                           unsigned   lpm_cap_en:1
                                                                         LPM-Capable (LPMCap) (Device and Host) The application uses this bit to control the DWC_otg core LPM capabilities.
                                                                           unsigned   appl_resp:1
                                                                         LPM-Capable (LPMCap) (Device and Host) The application uses this bit to control the DWC_otg core LPM capabilities.
                                                                           unsigned   appl_resp:1
                                                                         LPM response programmed by application (AppL1Res) (Device) Handshake response to LPM token pre-programmed by device application software.
                                                                           unsigned   hird:4
                                                                         LPM response programmed by application (AppL1Res) (Device) Handshake response to LPM token pre-programmed by device application software.
                                                                           unsigned   hird:4
                                                                         Host Initiated Resume Duration (HIRD) (Device and Host) In Host mode this field indicates the value of HIRD to be sent in an LPM transaction.
                                                                           unsigned   rem_wkup_en:1
                                                                         Host Initiated Resume Duration (HIRD) (Device and Host) In Host mode this field indicates the value of HIRD to be sent in an LPM transaction.
                                                                           unsigned   rem_wkup_en:1
                                                                         RemoteWakeEnable (bRemoteWake) (Device and Host) In Host mode this bit indicates the value of remote wake up to be sent in wIndex field of LPM transaction.
                                                                           unsigned   en_utmi_sleep:1
                                                                         RemoteWakeEnable (bRemoteWake) (Device and Host) In Host mode this bit indicates the value of remote wake up to be sent in wIndex field of LPM transaction.
                                                                           unsigned   en_utmi_sleep:1
                                                                         Enable utmi_sleep_n (EnblSlpM) (Device and Host) The application uses this bit to control the utmi_sleep_n assertion to the PHY when in L1 state.
                                                                           unsigned   hird_thres:5
                                                                         Enable utmi_sleep_n (EnblSlpM) (Device and Host) The application uses this bit to control the utmi_sleep_n assertion to the PHY when in L1 state.
                                                                           unsigned   hird_thres:5
                                                                         HIRD Threshold (HIRD_Thres) (Device and Host).
                                                                           unsigned   lpm_resp:2
                                                                           unsigned   lpm_resp:2
                                                                         LPM Response (CoreL1Res) (Device and Host) In Host mode this bit contains handsake response to LPM transaction.
                                                                           unsigned   prt_sleep_sts:1
                                                                         LPM Response (CoreL1Res) (Device and Host) In Host mode this bit contains handsake response to LPM transaction.
                                                                           unsigned   prt_sleep_sts:1
                                                                         Port Sleep Status (SlpSts) (Device and Host) This bit is set as long as a Sleep condition is present on the USB bus.
                                                                           unsigned   sleep_state_resumeok:1
                                                                         Port Sleep Status (SlpSts) (Device and Host) This bit is set as long as a Sleep condition is present on the USB bus.
                                                                           unsigned   sleep_state_resumeok:1
                                                                         Sleep State Resume OK (L1ResumeOK) (Device and Host) Indicates that the application or host can start resume from Sleep state.
                                                                           unsigned   lpm_chan_index:4
                                                                         Sleep State Resume OK (L1ResumeOK) (Device and Host) Indicates that the application or host can start resume from Sleep state.
                                                                           unsigned   lpm_chan_index:4
                                                                         LPM channel Index (LPM_Chnl_Indx) (Host) The channel number on which the LPM transaction has to be applied while sending an LPM transaction to the local device.
                                                                           unsigned   retry_count:3
                                                                         LPM channel Index (LPM_Chnl_Indx) (Host) The channel number on which the LPM transaction has to be applied while sending an LPM transaction to the local device.
                                                                           unsigned   retry_count:3
                                                                         LPM Retry Count (LPM_Retry_Cnt) (Host) Number host retries that would be performed if the device response was not valid response.
                                                                           unsigned   send_lpm:1
                                                                         LPM Retry Count (LPM_Retry_Cnt) (Host) Number host retries that would be performed if the device response was not valid response.
                                                                           unsigned   send_lpm:1
                                                                         Send LPM Transaction (SndLPM) (Host) When set by application software, an LPM transaction containing two tokens is sent.
                                                                           unsigned   retry_count_sts:3
                                                                         Send LPM Transaction (SndLPM) (Host) When set by application software, an LPM transaction containing two tokens is sent.
                                                                           unsigned   retry_count_sts:3
                                                                         LPM Retry status (LPM_RetryCnt_Sts) (Host) Number of LPM Host Retries still remaining to be transmitted for the current LPM sequence.
                                                                           unsigned   reserved28_29:2
                                                                           unsigned   reserved28_29:2
                                                                           unsigned   hsic_connect:1
                                                                           unsigned   hsic_connect:1
                                                                         In host mode once this bit is set, the host configures to drive the HSIC Idle state on the bus.
                                                                           unsigned   inv_sel_hsic:1
                                                                         In host mode once this bit is set, the host configures to drive the HSIC Idle state on the bus.
                                                                           unsigned   inv_sel_hsic:1
                                                                         This bit overrides and functionally inverts the if_select_hsic input port signal.
                                                                        } b
                                                                         This bit overrides and functionally inverts the if_select_hsic input port signal.
                                                                        } b
                                                                         register bits
                                                                        +@@ -90,89 +78,364 @@ +

                                                                        + +

                                                                        +-Definition at line 283 of file dwc_otg_regs.h.

                                                                        Field Documentation

                                                                        +- +-
                                                                        +-
                                                                        +- ++Definition at line 850 of file dwc_otg_regs.h.

                                                                        Field Documentation

                                                                        ++

                                                                        ++

                                                                        ++ ++ ++ ++
                                                                        ++ + +- ++ + +
                                                                        unsigned glpmctl_data::hird unsigned glpmctl_data::lpm_cap_en
                                                                        +- +-
                                                                        ++
                                                                        ++ ++ ++ ++ ++ ++
                                                                        ++   ++ ++ ++

                                                                        ++LPM-Capable (LPMCap) (Device and Host) The application uses this bit to control the DWC_otg core LPM capabilities. ++

                                                                        ++ ++

                                                                        ++Definition at line 859 of file dwc_otg_regs.h.

                                                                        ++

                                                                        ++ ++ ++ ++ ++
                                                                        ++ ++ ++ ++ ++
                                                                        unsigned glpmctl_data::appl_resp
                                                                        ++
                                                                        ++ ++ ++ ++ ++ ++
                                                                        ++   ++ ++ ++

                                                                        ++LPM response programmed by application (AppL1Res) (Device) Handshake response to LPM token pre-programmed by device application software. ++

                                                                        ++ ++

                                                                        ++Definition at line 864 of file dwc_otg_regs.h.

                                                                        ++

                                                                        ++ ++ ++ ++ ++
                                                                        ++ ++ ++ ++ ++
                                                                        unsigned glpmctl_data::hird
                                                                        ++
                                                                        ++ ++ ++ ++
                                                                        ++   ++ + +

                                                                        + Host Initiated Resume Duration (HIRD) (Device and Host) In Host mode this field indicates the value of HIRD to be sent in an LPM transaction. +

                                                                        +-In Device mode this field is updated with the Received LPM Token HIRD bmAttribute when an ACK/NYET/STALL response is sent to an LPM transaction. ++In Device mode this field is updated with the Received LPM Token HIRD bmAttribute when an ACK/NYET/STALL response is sent to an LPM transaction. +

                                                                        +-Definition at line 306 of file dwc_otg_regs.h. +- +-

                                                                        +- +-

                                                                        +-
                                                                        +- ++Definition at line 873 of file dwc_otg_regs.h. ++ ++
                                                                        ++

                                                                        ++ ++ ++ ++ ++
                                                                        ++ + +- ++ + +
                                                                        unsigned glpmctl_data::rem_wkup_en unsigned glpmctl_data::rem_wkup_en
                                                                        +- +-
                                                                        ++
                                                                        ++ ++ ++ ++
                                                                        ++   ++ + +

                                                                        + RemoteWakeEnable (bRemoteWake) (Device and Host) In Host mode this bit indicates the value of remote wake up to be sent in wIndex field of LPM transaction. +

                                                                        +-In Device mode this field is updated with the Received LPM Token bRemoteWake bmAttribute when an ACK/NYET/STALL response is sent to an LPM transaction. ++In Device mode this field is updated with the Received LPM Token bRemoteWake bmAttribute when an ACK/NYET/STALL response is sent to an LPM transaction. +

                                                                        +-Definition at line 315 of file dwc_otg_regs.h. +- +-

                                                                        +- +-

                                                                        +-
                                                                        +- ++Definition at line 882 of file dwc_otg_regs.h. ++ ++
                                                                        ++

                                                                        ++ ++ ++ ++ ++
                                                                        ++ + +- ++ + +
                                                                        unsigned glpmctl_data::lpm_resp unsigned glpmctl_data::en_utmi_sleep
                                                                        +- +-
                                                                        ++
                                                                        ++ ++ ++ ++ ++ ++
                                                                        ++   ++ ++ ++

                                                                        ++Enable utmi_sleep_n (EnblSlpM) (Device and Host) The application uses this bit to control the utmi_sleep_n assertion to the PHY when in L1 state. ++

                                                                        ++ ++

                                                                        ++Definition at line 887 of file dwc_otg_regs.h.

                                                                        ++

                                                                        ++ ++ ++ ++ ++
                                                                        ++ ++ ++ ++ ++
                                                                        unsigned glpmctl_data::lpm_resp
                                                                        ++
                                                                        ++ ++ ++ ++ ++ ++
                                                                        ++   ++ + +

                                                                        + LPM Response (CoreL1Res) (Device and Host) In Host mode this bit contains handsake response to LPM transaction. +

                                                                        + In Device mode the response of the core to LPM transaction received is reflected in these two bits.

                                                                          +-
                                                                        • 0x0 : ERROR (No handshake response)
                                                                        • 0x1 : STALL
                                                                        • 0x2 : NYET
                                                                        • 0x3 : ACK
                                                                        ++
                                                                      • 0x0 : ERROR (No handshake response)
                                                                      • 0x1 : STALL
                                                                      • 0x2 : NYET
                                                                      • 0x3 : ACK
                                                                        • ++ ++

                                                                        ++Definition at line 901 of file dwc_otg_regs.h.

                                                                        ++

                                                                        ++ ++ ++ ++ ++
                                                                        ++ ++ ++ ++ ++
                                                                        unsigned glpmctl_data::prt_sleep_sts
                                                                        ++
                                                                        ++ ++ ++ ++ ++ ++
                                                                        ++   ++ ++ ++

                                                                        ++Port Sleep Status (SlpSts) (Device and Host) This bit is set as long as a Sleep condition is present on the USB bus. ++

                                                                        ++ ++

                                                                        ++Definition at line 906 of file dwc_otg_regs.h.

                                                                        ++

                                                                        ++ ++ ++ ++ ++
                                                                        ++ ++ ++ ++ ++
                                                                        unsigned glpmctl_data::sleep_state_resumeok
                                                                        ++
                                                                        ++ ++ ++ ++
                                                                        ++   ++ + +

                                                                        +-Definition at line 334 of file dwc_otg_regs.h. +- +-

                                                                        +- +-

                                                                        +-
                                                                        +- ++Sleep State Resume OK (L1ResumeOK) (Device and Host) Indicates that the application or host can start resume from Sleep state. ++

                                                                        ++ ++

                                                                        ++Definition at line 911 of file dwc_otg_regs.h. ++ ++

                                                                        ++

                                                                        ++ ++ ++ ++ ++
                                                                        ++ + +- ++ + +
                                                                        unsigned glpmctl_data::hsic_connect unsigned glpmctl_data::lpm_chan_index
                                                                        +- +-
                                                                        ++
                                                                        ++ ++ ++ ++ ++ ++
                                                                        ++   ++ ++ ++

                                                                        ++LPM channel Index (LPM_Chnl_Indx) (Host) The channel number on which the LPM transaction has to be applied while sending an LPM transaction to the local device. ++

                                                                        ++ ++

                                                                        ++Definition at line 917 of file dwc_otg_regs.h.

                                                                        ++

                                                                        ++ ++ ++ ++ ++
                                                                        ++ ++ ++ ++ ++
                                                                        unsigned glpmctl_data::retry_count
                                                                        ++
                                                                        ++ ++ ++ ++ ++ ++
                                                                        ++   ++ ++ ++

                                                                        ++LPM Retry Count (LPM_Retry_Cnt) (Host) Number host retries that would be performed if the device response was not valid response. ++

                                                                        ++ ++

                                                                        ++Definition at line 922 of file dwc_otg_regs.h.

                                                                        ++

                                                                        ++ ++ ++ ++ ++
                                                                        ++ ++ ++ ++ ++
                                                                        unsigned glpmctl_data::send_lpm
                                                                        ++
                                                                        ++ ++ ++ ++ ++ ++
                                                                        ++   ++ ++ ++

                                                                        ++Send LPM Transaction (SndLPM) (Host) When set by application software, an LPM transaction containing two tokens is sent. ++

                                                                        ++ ++

                                                                        ++Definition at line 928 of file dwc_otg_regs.h.

                                                                        ++

                                                                        ++ ++ ++ ++ ++
                                                                        ++ ++ ++ ++ ++
                                                                        unsigned glpmctl_data::hsic_connect
                                                                        ++
                                                                        ++ ++ ++ ++ ++ ++
                                                                        ++   ++ + +

                                                                        + In host mode once this bit is set, the host configures to drive the HSIC Idle state on the bus. +

                                                                        +-It then waits for the device to initiate the Connect sequence. In device mode once this bit is set, the device waits for the HSIC Idle line state on the bus. Upon receving the Idle line state, it initiates the HSIC Connect sequence. ++It then waits for the device to initiate the Connect sequence. In device mode once this bit is set, the device waits for the HSIC Idle line state on the bus. Upon receving the Idle line state, it initiates the HSIC Connect sequence. ++

                                                                        ++Definition at line 942 of file dwc_otg_regs.h.

                                                                        ++

                                                                        ++ ++ ++ ++ ++
                                                                        ++ ++ ++ ++ ++
                                                                        unsigned glpmctl_data::inv_sel_hsic
                                                                        ++
                                                                        ++ ++ ++ ++ ++ ++
                                                                        ++   ++ ++ ++

                                                                        ++This bit overrides and functionally inverts the if_select_hsic input port signal. +

                                                                        +-Definition at line 375 of file dwc_otg_regs.h. +- +-

                                                                        ++ ++

                                                                        ++Definition at line 946 of file dwc_otg_regs.h.

                                                                        +

                                                                        The documentation for this union was generated from the following file: +-
                                                                        Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++
                                                                        Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
                                                                        ++doxygen 1.3.9.1
                                                                        + + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/uniongnptxsts__data.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/uniongnptxsts__data.html 2013-07-26 19:31:22.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/uniongnptxsts__data.html 2013-07-26 19:34:43.000000000 +0000 +@@ -2,22 +2,10 @@ + + DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: gnptxsts_data Union Reference + +- + +- +-
                                                                        +-
                                                                        +-
                                                                        +-
                                                                        +-

                                                                        gnptxsts_data Union Reference

                                                                        This union represents the bit fields in the Non-Periodic Transmit FIFO/Queue Status Register (GNPTXSTS). ++ ++
                                                                        Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                        ++

                                                                        gnptxsts_data Union Reference

                                                                        This union represents the bit fields in the Non-Periodic Transmit FIFO/Queue Status Register (GNPTXSTS). + More... +

                                                                        + #include <dwc_otg_regs.h> +@@ -25,31 +13,27 @@ + + + +- ++ + + +- + +- ++ + +- ++ + +- ++ + +- +- ++ ++ + +- ++ + +- ++ + +- ++ + + +

                                                                        Data Fields

                                                                        +-uint32_t d32
                                                                        ++uint32_t d32
                                                                         raw register data
                                                                        ++
                                                                        + struct {
                                                                           unsigned   nptxfspcavail:16
                                                                           unsigned   nptxfspcavail:16
                                                                           unsigned   nptxqspcavail:8
                                                                           unsigned   nptxqspcavail:8
                                                                           unsigned   nptxqtop_terminate:1
                                                                           unsigned   nptxqtop_terminate:1
                                                                         Top of the Non-Periodic Transmit Request Queue
                                                                          +-
                                                                        • bit 24 - Terminate (Last entry for the selected channel/EP)
                                                                        • bits 26:25 - Token Type
                                                                            +-
                                                                          • 2'b00 - IN/OUT
                                                                          • 2'b01 - Zero Length OUT
                                                                          • 2'b10 - PING/Complete Split
                                                                          • 2'b11 - Channel Halt
                                                                          +-
                                                                        • bits 30:27 - Channel/EP Number.
                                                                        +-
                                                                           unsigned   nptxqtop_token:2
                                                                         Top of the Non-Periodic Transmit Request Queue bit 24 - Terminate (Last entry for the selected channel/EP) bits 26:25 - Token Type 2'b00 - IN/OUT 2'b01 - Zero Length OUT 2'b10 - PING/Complete Split 2'b11 - Channel Halt bits 30:27 - Channel/EP Number.
                                                                           unsigned   nptxqtop_token:2
                                                                           unsigned   nptxqtop_chnep:4
                                                                           unsigned   nptxqtop_chnep:4
                                                                           unsigned   reserved:1
                                                                           unsigned   reserved:1
                                                                        } b
                                                                        } b
                                                                         register bits
                                                                        +@@ -60,10 +44,40 @@ +

                                                                        + +

                                                                        +-Definition at line 667 of file dwc_otg_regs.h.

                                                                        The documentation for this union was generated from the following file:
                                                                          ++Definition at line 588 of file dwc_otg_regs.h.

                                                                          Field Documentation

                                                                          ++

                                                                          ++ ++ ++ ++ ++
                                                                          ++ ++ ++ ++ ++
                                                                          unsigned gnptxsts_data::nptxqtop_terminate
                                                                          ++
                                                                          ++ ++ ++ ++ ++ ++
                                                                          ++   ++ ++ ++

                                                                          ++Top of the Non-Periodic Transmit Request Queue bit 24 - Terminate (Last entry for the selected channel/EP) bits 26:25 - Token Type 2'b00 - IN/OUT 2'b01 - Zero Length OUT 2'b10 - PING/Complete Split 2'b11 - Channel Halt bits 30:27 - Channel/EP Number. ++

                                                                          ++

                                                                            ++
                                                                          • * - * - * - * - * - * -
                                                                          ++ ++

                                                                          ++Definition at line 605 of file dwc_otg_regs.h.

                                                                          ++

                                                                          The documentation for this union was generated from the following file: +-
                                                                          Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++
                                                                          Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
                                                                          ++doxygen 1.3.9.1
                                                                          + + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/uniongotgctl__data.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/uniongotgctl__data.html 2013-07-26 19:31:22.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/uniongotgctl__data.html 2013-07-26 19:34:43.000000000 +0000 +@@ -2,22 +2,10 @@ + + DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: gotgctl_data Union Reference + +- + +- +-
                                                                          +-
                                                                          +-
                                                                          +-
                                                                          +-

                                                                          gotgctl_data Union Reference

                                                                          This union represents the bit fields of the Core OTG Control and Status Register (GOTGCTL). ++ ++
                                                                          Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                          ++

                                                                          gotgctl_data Union Reference

                                                                          This union represents the bit fields of the Core OTG Control and Status Register (GOTGCTL). + More... +

                                                                          + #include <dwc_otg_regs.h> +@@ -25,42 +13,58 @@ + + + +- ++ + + +- + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ + + +

                                                                          Data Fields

                                                                          +-uint32_t d32
                                                                          ++uint32_t d32
                                                                           raw register data
                                                                          ++
                                                                          + struct {
                                                                             unsigned   sesreqscs:1
                                                                             unsigned   sesreqscs:1
                                                                             unsigned   sesreq:1
                                                                             unsigned   sesreq:1
                                                                             unsigned   reserved2_7:6
                                                                             unsigned   vbvalidoven:1
                                                                             unsigned   hstnegscs:1
                                                                             unsigned   vbvalidovval:1
                                                                             unsigned   hnpreq:1
                                                                             unsigned   avalidoven:1
                                                                             unsigned   hstsethnpen:1
                                                                             unsigned   avalidovval:1
                                                                             unsigned   devhnpen:1
                                                                             unsigned   bvalidoven:1
                                                                             unsigned   reserved12_15:4
                                                                             unsigned   bvalidovval:1
                                                                             unsigned   conidsts:1
                                                                             unsigned   hstnegscs:1
                                                                             unsigned   reserved17:1
                                                                             unsigned   hnpreq:1
                                                                             unsigned   asesvld:1
                                                                             unsigned   hstsethnpen:1
                                                                             unsigned   bsesvld:1
                                                                             unsigned   devhnpen:1
                                                                             unsigned   currmod:1
                                                                             unsigned   reserved12_15:4
                                                                             unsigned   reserved21_31:11
                                                                             unsigned   conidsts:1
                                                                          } b
                                                                             unsigned   dbnctime:1
                                                                             unsigned   asesvld:1
                                                                             unsigned   bsesvld:1
                                                                             unsigned   otgver:1
                                                                             unsigned   reserved1:1
                                                                             unsigned   multvalidbc:5
                                                                             unsigned   chirpen:1
                                                                             unsigned   reserved28_31:4
                                                                          } b
                                                                           register bits
                                                                          +@@ -71,10 +75,10 @@ +

                                                                          + +

                                                                          +-Definition at line 152 of file dwc_otg_regs.h.

                                                                          The documentation for this union was generated from the following file:
                                                                            ++Definition at line 158 of file dwc_otg_regs.h.
                                                                            The documentation for this union was generated from the following file: +-
                                                                            Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++
                                                                            Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
                                                                            ++doxygen 1.3.9.1
                                                                            + + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/uniongotgint__data.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/uniongotgint__data.html 2013-07-26 19:31:22.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/uniongotgint__data.html 2013-07-26 19:34:43.000000000 +0000 +@@ -2,22 +2,10 @@ + + DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: gotgint_data Union Reference + +- + +- +-
                                                                            +-
                                                                            +-
                                                                            +-
                                                                            +-

                                                                            gotgint_data Union Reference

                                                                            This union represents the bit fields of the Core OTG Interrupt Register (GOTGINT). ++ ++
                                                                            Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                            ++

                                                                            gotgint_data Union Reference

                                                                            This union represents the bit fields of the Core OTG Interrupt Register (GOTGINT). + More... +

                                                                            + #include <dwc_otg_regs.h> +@@ -25,41 +13,44 @@ + + + +- ++ + + +- + +- ++ + + +- ++ + + +- ++ + +- ++ + + +- ++ + + +- ++ + +- ++ + + +- ++ + + +- ++ + + +- ++ + +- ++ ++ ++ ++ + + +

                                                                            Data Fields

                                                                            +-uint32_t d32
                                                                            ++uint32_t d32
                                                                             raw register data
                                                                            ++
                                                                            + struct {
                                                                               unsigned   reserved0_1:2
                                                                               unsigned   reserved0_1:2
                                                                             Current Mode.
                                                                               unsigned   sesenddet:1
                                                                               unsigned   sesenddet:1
                                                                             Session End Detected.
                                                                               unsigned   reserved3_7:5
                                                                               unsigned   reserved3_7:5
                                                                               unsigned   sesreqsucstschng:1
                                                                               unsigned   sesreqsucstschng:1
                                                                             Session Request Success Status Change.
                                                                               unsigned   hstnegsucstschng:1
                                                                               unsigned   hstnegsucstschng:1
                                                                             Host Negotiation Success Status Change.
                                                                               unsigned   reserver10_16:7
                                                                               unsigned   reserved10_16:7
                                                                               unsigned   hstnegdet:1
                                                                               unsigned   hstnegdet:1
                                                                             Host Negotiation Detected.
                                                                               unsigned   adevtoutchng:1
                                                                               unsigned   adevtoutchng:1
                                                                             A-Device Timeout Change.
                                                                               unsigned   debdone:1
                                                                               unsigned   debdone:1
                                                                             Debounce Done.
                                                                               unsigned   reserved31_20:12
                                                                               unsigned   mvic:1
                                                                            } b
                                                                             Multi-Valued input changed.
                                                                               unsigned   reserved31_21:11
                                                                            } b
                                                                             register bits
                                                                            +@@ -70,10 +61,10 @@ +

                                                                            + +

                                                                            +-Definition at line 179 of file dwc_otg_regs.h.

                                                                            The documentation for this union was generated from the following file:
                                                                              ++Definition at line 193 of file dwc_otg_regs.h.
                                                                              The documentation for this union was generated from the following file: +-
                                                                              Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++
                                                                              Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
                                                                              ++doxygen 1.3.9.1
                                                                              + + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/uniongpvndctl__data.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/uniongpvndctl__data.html 2013-07-26 19:34:43.000000000 +0000 +@@ -0,0 +1,60 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: gpvndctl_data Union Reference ++ ++ ++ ++
                                                                              Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                              ++

                                                                              gpvndctl_data Union Reference

                                                                              This union represents the bit fields in the PHY Vendor Control Register (GPVNDCTL). ++More... ++

                                                                              ++#include <dwc_otg_regs.h> ++

                                                                              ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++

                                                                              Data Fields

                                                                              ++uint32_t d32
                                                                               raw register data
                                                                              ++struct {
                                                                                 unsigned   regdata:8
                                                                                 unsigned   vctrl:8
                                                                                 unsigned   regaddr16_21:6
                                                                                 unsigned   regwr:1
                                                                                 unsigned   reserved23_24:2
                                                                                 unsigned   newregreq:1
                                                                                 unsigned   vstsbsy:1
                                                                                 unsigned   vstsdone:1
                                                                                 unsigned   reserved28_30:3
                                                                                 unsigned   disulpidrvr:1
                                                                              } b
                                                                               register bits
                                                                              ++

                                                                              Detailed Description

                                                                              ++This union represents the bit fields in the PHY Vendor Control Register (GPVNDCTL). ++

                                                                              ++Read the register into the d32 element then read out the bits using the bit elements. ++

                                                                              ++ ++

                                                                              ++Definition at line 657 of file dwc_otg_regs.h.

                                                                              The documentation for this union was generated from the following file: ++
                                                                              Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.3.9.1
                                                                              ++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/uniongpwrdn__data.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/uniongpwrdn__data.html 2013-07-26 19:34:43.000000000 +0000 +@@ -0,0 +1,114 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: gpwrdn_data Union Reference ++ ++ ++ ++
                                                                              Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                              ++

                                                                              gpwrdn_data Union Reference

                                                                              This union represents the bit fields in the Global Power Down Register Register. ++More... ++

                                                                              ++#include <dwc_otg_regs.h> ++

                                                                              ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++

                                                                              Data Fields

                                                                              ++uint32_t d32
                                                                              ++struct {
                                                                                 unsigned   pmuintsel:1
                                                                               PMU Interrupt Select.
                                                                                 unsigned   pmuactv:1
                                                                               PMU Active.
                                                                                 unsigned   restore:1
                                                                               Restore.
                                                                                 unsigned   pwrdnclmp:1
                                                                               Power Down Clamp.
                                                                                 unsigned   pwrdnrstn:1
                                                                               Power Down Reset.
                                                                                 unsigned   pwrdnswtch:1
                                                                               Power Down Switch.
                                                                                 unsigned   dis_vbus:1
                                                                               Disable VBUS.
                                                                                 unsigned   lnstschng:1
                                                                               Line State Change.
                                                                                 unsigned   lnstchng_msk:1
                                                                               Line state change mask.
                                                                                 unsigned   rst_det:1
                                                                               Reset Detected.
                                                                                 unsigned   rst_det_msk:1
                                                                               Reset Detect mask.
                                                                                 unsigned   disconn_det:1
                                                                               Disconnect Detected.
                                                                                 unsigned   disconn_det_msk:1
                                                                               Disconnect Detect mask.
                                                                                 unsigned   connect_det:1
                                                                               Connect Detected.
                                                                                 unsigned   connect_det_msk:1
                                                                               Connect Detected Mask.
                                                                                 unsigned   srp_det:1
                                                                               SRP Detected.
                                                                                 unsigned   srp_det_msk:1
                                                                               SRP Detect mask.
                                                                                 unsigned   sts_chngint:1
                                                                               Status Change Interrupt.
                                                                                 unsigned   sts_chngint_msk:1
                                                                               Status Change Interrupt Mask.
                                                                                 unsigned   linestate:2
                                                                               Line State.
                                                                                 unsigned   idsts:1
                                                                               Indicates current mode(status of IDDIG signal).
                                                                                 unsigned   bsessvld:1
                                                                               B Session Valid signal status.
                                                                                 unsigned   adp_int:1
                                                                               ADP Event Detected.
                                                                                 unsigned   mult_val_id_bc:5
                                                                               Multi Valued ID pin.
                                                                                 unsigned   reserved29_31:3
                                                                               Reserved 24_31.
                                                                              } b
                                                                               register bits
                                                                              ++

                                                                              Detailed Description

                                                                              ++This union represents the bit fields in the Global Power Down Register Register. ++

                                                                              ++Read the register into the d32 member then set/clear the bits using the bit elements. ++

                                                                              ++ ++

                                                                              ++Definition at line 2486 of file dwc_otg_regs.h.

                                                                              The documentation for this union was generated from the following file: ++
                                                                              Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.3.9.1
                                                                              ++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/uniongrstctl__data.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/uniongrstctl__data.html 2013-07-26 19:31:22.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/uniongrstctl__data.html 2013-07-26 19:34:43.000000000 +0000 +@@ -2,22 +2,10 @@ + + DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: grstctl_data Union Reference + +- + +- +-
                                                                              +-
                                                                              +-
                                                                              +-
                                                                              +-

                                                                              grstctl_data Union Reference

                                                                              This union represents the bit fields of the Core Reset Register (GRSTCTL). ++ ++
                                                                              Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                              ++

                                                                              grstctl_data Union Reference

                                                                              This union represents the bit fields of the Core Reset Register (GRSTCTL). + More... +

                                                                              + #include <dwc_otg_regs.h> +@@ -25,45 +13,45 @@ + + + +- ++ + + +- + +- ++ + +- +- ++ ++ + +- +- ++ ++ + + +- ++.
                                                                              ++ + + +- ++ + +- +- ++ ++ + +- +- ++ ++ + +- +- ++ ++ + + +- ++ + +- +- ++ ++ + +- +- ++ ++ + + +

                                                                              Data Fields

                                                                              +-uint32_t d32
                                                                              ++uint32_t d32
                                                                               raw register data
                                                                              ++
                                                                              + struct {
                                                                                 unsigned   csftrst:1
                                                                                 unsigned   csftrst:1
                                                                               Core Soft Reset (CSftRst) (Device and Host).
                                                                                 unsigned   hsftrst:1
                                                                               Core Soft Reset (CSftRst) (Device and Host).
                                                                                 unsigned   hsftrst:1
                                                                               Hclk Soft Reset.
                                                                                 unsigned   hstfrm:1
                                                                               Hclk Soft Reset.
                                                                                 unsigned   hstfrm:1
                                                                               Host Frame Counter Reset (Host Only)
                                                                              +-.
                                                                                 unsigned   intknqflsh:1
                                                                                 unsigned   intknqflsh:1
                                                                               In Token Sequence Learning Queue Flush (INTknQFlsh) (Device Only).
                                                                                 unsigned   rxfflsh:1
                                                                                 unsigned   rxfflsh:1
                                                                               RxFIFO Flush (RxFFlsh) (Device and Host).
                                                                                 unsigned   txfflsh:1
                                                                               RxFIFO Flush (RxFFlsh) (Device and Host).
                                                                                 unsigned   txfflsh:1
                                                                               TxFIFO Flush (TxFFlsh) (Device and Host).
                                                                                 unsigned   txfnum:5
                                                                               TxFIFO Flush (TxFFlsh) (Device and Host).
                                                                                 unsigned   txfnum:5
                                                                               TxFIFO Number (TxFNum) (Device and Host).
                                                                                 unsigned   reserved11_29:19
                                                                               TxFIFO Number (TxFNum) (Device and Host).
                                                                                 unsigned   reserved11_29:19
                                                                               Reserved.
                                                                                 unsigned   dmareq:1
                                                                                 unsigned   dmareq:1
                                                                               DMA Request Signal.
                                                                                 unsigned   ahbidle:1
                                                                               DMA Request Signal.
                                                                                 unsigned   ahbidle:1
                                                                               AHB Master Idle.
                                                                              } b
                                                                               AHB Master Idle.
                                                                              } b
                                                                               register bits
                                                                              +@@ -74,17 +62,25 @@ +

                                                                              + +

                                                                              +-Definition at line 388 of file dwc_otg_regs.h.

                                                                              Field Documentation

                                                                              +- +-
                                                                              +-
                                                                              +- ++Definition at line 307 of file dwc_otg_regs.h.

                                                                              Field Documentation

                                                                              ++

                                                                              ++

                                                                              ++ ++ ++ ++
                                                                              ++ + +- ++ + +
                                                                              unsigned grstctl_data::csftrst unsigned grstctl_data::csftrst
                                                                              +- +-
                                                                              ++
                                                                              ++ ++ ++ ++
                                                                              ++   ++ + +

                                                                              + Core Soft Reset (CSftRst) (Device and Host). +@@ -94,156 +90,207 @@ + The status mask bits that control the generation of the interrupt, are cleared, to clear the interrupt. The interrupt status bits are not cleared, so the application can get the status of any events that occurred in the core after it has set this bit.

                                                                              + Any transactions on the AHB are terminated as soon as possible following the protocol. Any transactions on the USB are terminated immediately.

                                                                              + The configuration settings in the CSRs are unchanged, so the software doesn't have to reprogram these registers (Device Configuration/Host Configuration/Core System Configuration/Core PHY Configuration).

                                                                              +-The application can write to this bit, any time it wants to reset the core. This is a self clearing bit and the core clears this bit after all the necessary logic is reset in the core, which may take several clocks, depending on the current state of the core. ++The application can write to this bit, any time it wants to reset the core. This is a self clearing bit and the core clears this bit after all the necessary logic is reset in the core, which may take several clocks, depending on the current state of the core. +

                                                                              +-Definition at line 428 of file dwc_otg_regs.h. +- +-

                                                                              +- +-

                                                                              +-
                                                                              +- ++Definition at line 347 of file dwc_otg_regs.h. ++ ++
                                                                              ++

                                                                              ++ ++ ++ ++ ++
                                                                              ++ + +- ++ + +
                                                                              unsigned grstctl_data::hsftrst unsigned grstctl_data::hsftrst
                                                                              +- +-
                                                                              ++
                                                                              ++ ++ ++ ++
                                                                              ++   ++ + +

                                                                              + Hclk Soft Reset. +

                                                                              +-The application uses this bit to reset the control logic in the AHB clock domain. Only AHB clock domain pipelines are reset. ++The application uses this bit to reset the control logic in the AHB clock domain. Only AHB clock domain pipelines are reset. +

                                                                              +-Definition at line 435 of file dwc_otg_regs.h. +- +-

                                                                              +- +-

                                                                              +-
                                                                              +- ++Definition at line 354 of file dwc_otg_regs.h. ++ ++
                                                                              ++

                                                                              ++ ++ ++ ++ ++
                                                                              ++ + +- ++ + +
                                                                              unsigned grstctl_data::hstfrm unsigned grstctl_data::hstfrm
                                                                              +- +-
                                                                              ++
                                                                              ++ ++ ++ ++
                                                                              ++   ++ + +

                                                                              + Host Frame Counter Reset (Host Only)
                                                                              + . +

                                                                              +-The application can reset the (micro)frame number counter inside the core, using this bit. When the (micro)frame counter is reset, the subsequent SOF sent out by the core, will have a (micro)frame number of 0. ++The application can reset the (micro)frame number counter inside the core, using this bit. When the (micro)frame counter is reset, the subsequent SOF sent out by the core, will have a (micro)frame number of 0. +

                                                                              +-Definition at line 444 of file dwc_otg_regs.h. +- +-

                                                                              +- +-

                                                                              +-
                                                                              +- ++Definition at line 363 of file dwc_otg_regs.h. ++ ++
                                                                              ++

                                                                              ++ ++ ++ ++ ++
                                                                              ++ + +- ++ + +
                                                                              unsigned grstctl_data::rxfflsh unsigned grstctl_data::rxfflsh
                                                                              +- +-
                                                                              ++
                                                                              ++ ++ ++ ++
                                                                              ++   ++ + +

                                                                              + RxFIFO Flush (RxFFlsh) (Device and Host). +

                                                                              +-The application can flush the entire Receive FIFO using this bit.

                                                                              +-The application must first ensure that the core is not in the middle of a transaction.

                                                                              +-The application should write into this bit, only after making sure that neither the DMA engine is reading from the RxFIFO nor the MAC is writing the data in to the FIFO.

                                                                              +-The application should wait until the bit is cleared before performing any other operations. This bit will takes 8 clocks (slowest of PHY or AHB clock) to clear. +-

                                                                              +-Definition at line 463 of file dwc_otg_regs.h. +- +-

                                                                              +- +-

                                                                              +-
                                                                              +- ++The application can flush the entire Receive FIFO using this bit. The application must first ensure that the core is not in the middle of a transaction. The application should write into this bit, only after making sure that neither the DMA engine is reading from the RxFIFO nor the MAC is writing the data in to the FIFO. The application should wait until the bit is cleared before performing any other operations. This bit will takes 8 clocks (slowest of PHY or AHB clock) to clear. ++

                                                                              ++Definition at line 382 of file dwc_otg_regs.h. ++ ++

                                                                              ++

                                                                              ++ ++ ++ ++ ++
                                                                              ++ + +- ++ + +
                                                                              unsigned grstctl_data::txfflsh unsigned grstctl_data::txfflsh
                                                                              +- +-
                                                                              ++
                                                                              ++ ++ ++ ++
                                                                              ++   ++ + +

                                                                              + TxFIFO Flush (TxFFlsh) (Device and Host). +

                                                                              +-This bit is used to selectively flush a single or all transmit FIFOs. The application must first ensure that the core is not in the middle of a transaction.

                                                                              +-The application should write into this bit, only after making sure that neither the DMA engine is writing into the TxFIFO nor the MAC is reading the data out of the FIFO.

                                                                              +-The application should wait until the core clears this bit, before performing any operations. This bit will takes 8 clocks (slowest of PHY or AHB clock) to clear. +-

                                                                              +-Definition at line 478 of file dwc_otg_regs.h. +- +-

                                                                              +- +-

                                                                              +-
                                                                              +- ++This bit is used to selectively flush a single or all transmit FIFOs. The application must first ensure that the core is not in the middle of a transaction. The application should write into this bit, only after making sure that neither the DMA engine is writing into the TxFIFO nor the MAC is reading the data out of the FIFO. The application should wait until the core clears this bit, before performing any operations. This bit will takes 8 clocks (slowest of PHY or AHB clock) to clear. ++

                                                                              ++Definition at line 397 of file dwc_otg_regs.h. ++ ++

                                                                              ++

                                                                              ++ ++ ++ ++ ++
                                                                              ++ + +- ++ + +
                                                                              unsigned grstctl_data::txfnum unsigned grstctl_data::txfnum
                                                                              +- +-
                                                                              ++
                                                                              ++ ++ ++ ++
                                                                              ++   ++ + +

                                                                              + TxFIFO Number (TxFNum) (Device and Host). +

                                                                              + This is the FIFO number which needs to be flushed, using the TxFIFO Flush bit. This field should not be changed until the TxFIFO Flush bit is cleared by the core.

                                                                                +-
                                                                              • 0x0 : Non Periodic TxFIFO Flush
                                                                              • 0x1 : Periodic TxFIFO #1 Flush in device mode or Periodic TxFIFO in host mode
                                                                              • 0x2 : Periodic TxFIFO #2 Flush in device mode.
                                                                              • ...
                                                                              • 0xF : Periodic TxFIFO #15 Flush in device mode
                                                                              • 0x10: Flush all the Transmit NonPeriodic and Transmit Periodic FIFOs in the core
                                                                              ++
                                                                            • 0x0 : Non Periodic TxFIFO Flush
                                                                            • 0x1 : Periodic TxFIFO #1 Flush in device mode or Periodic TxFIFO in host mode
                                                                            • 0x2 : Periodic TxFIFO #2 Flush in device mode.
                                                                            • ...
                                                                            • 0xF : Periodic TxFIFO #15 Flush in device mode
                                                                            • 0x10: Flush all the Transmit NonPeriodic and Transmit Periodic FIFOs in the core
                                                                              • + +

                                                                              +-Definition at line 495 of file dwc_otg_regs.h. +- +-

                                                                              +- +-

                                                                              +-
                                                                              +- ++Definition at line 414 of file dwc_otg_regs.h. ++ ++
                                                                              ++

                                                                              ++ ++ ++ ++ ++
                                                                              ++ + +- ++ + +
                                                                              unsigned grstctl_data::dmareq unsigned grstctl_data::dmareq
                                                                              +- +-
                                                                              ++
                                                                              ++ ++ ++ ++
                                                                              ++   ++ + +

                                                                              + DMA Request Signal. +

                                                                              + Indicated DMA request is in probress. Used for debug purpose. +

                                                                              +-Definition at line 500 of file dwc_otg_regs.h. +- +-

                                                                              +- +-

                                                                              +-
                                                                              +- ++Definition at line 419 of file dwc_otg_regs.h. ++ ++
                                                                              ++

                                                                              ++ ++ ++ ++ ++
                                                                              ++ + +- ++ + +
                                                                              unsigned grstctl_data::ahbidle unsigned grstctl_data::ahbidle
                                                                              +- +-
                                                                              ++
                                                                              ++ ++ ++ ++ ++ ++
                                                                              ++   ++ + +

                                                                              + AHB Master Idle. +

                                                                              + Indicates the AHB Master State Machine is in IDLE condition. +

                                                                              +-Definition at line 503 of file dwc_otg_regs.h. +- +-

                                                                              ++Definition at line 422 of file dwc_otg_regs.h.

                                                                              +

                                                                              The documentation for this union was generated from the following file: +-
                                                                              Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++
                                                                              Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
                                                                              ++doxygen 1.3.9.1
                                                                              + + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/uniongsnpsid__data.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/uniongsnpsid__data.html 2013-07-26 19:34:43.000000000 +0000 +@@ -0,0 +1,42 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: gsnpsid_data Union Reference ++ ++ ++ ++
                                                                              Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                              ++

                                                                              gsnpsid_data Union Reference

                                                                              This union represents the bit fields in the Synopsys ID Register (GSNPSID). ++More... ++

                                                                              ++#include <dwc_otg_regs.h> ++

                                                                              ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++

                                                                              Data Fields

                                                                              ++uint32_t d32
                                                                               raw register data
                                                                              ++struct {
                                                                                 unsigned   rwdata:32
                                                                              } b
                                                                               register bits
                                                                              ++

                                                                              Detailed Description

                                                                              ++This union represents the bit fields in the Synopsys ID Register (GSNPSID). ++

                                                                              ++Read the register into the d32 element then read out the bits using the bit elements. ++

                                                                              ++ ++

                                                                              ++Definition at line 710 of file dwc_otg_regs.h.

                                                                              The documentation for this union was generated from the following file: ++
                                                                              Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.3.9.1
                                                                              ++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/unionguid__data.html +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/unionguid__data.html 2013-07-26 19:34:43.000000000 +0000 +@@ -0,0 +1,42 @@ ++ ++ ++DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: guid_data Union Reference ++ ++ ++ ++
                                                                              Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                              ++

                                                                              guid_data Union Reference

                                                                              This union represents the bit fields in the User ID Register (GUID). ++More... ++

                                                                              ++#include <dwc_otg_regs.h> ++

                                                                              ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++

                                                                              Data Fields

                                                                              ++uint32_t d32
                                                                               raw register data
                                                                              ++struct {
                                                                                 unsigned   rwdata:32
                                                                              } b
                                                                               register bits
                                                                              ++

                                                                              Detailed Description

                                                                              ++This union represents the bit fields in the User ID Register (GUID). ++

                                                                              ++Read the register into the d32 element then read out the bits using the bit elements. ++

                                                                              ++ ++

                                                                              ++Definition at line 696 of file dwc_otg_regs.h.

                                                                              The documentation for this union was generated from the following file: ++
                                                                              Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++ ++doxygen 1.3.9.1
                                                                              ++ ++ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/uniongusbcfg__data.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/uniongusbcfg__data.html 2013-07-26 19:31:22.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/uniongusbcfg__data.html 2013-07-26 19:34:43.000000000 +0000 +@@ -2,22 +2,10 @@ + + DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: gusbcfg_data Union Reference + +- + +- +-
                                                                              +-
                                                                              +-
                                                                              +-
                                                                              +-

                                                                              gusbcfg_data Union Reference

                                                                              This union represents the bit fields of the Core USB Configuration Register (GUSBCFG). ++ ++
                                                                              Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                              ++

                                                                              gusbcfg_data Union Reference

                                                                              This union represents the bit fields of the Core USB Configuration Register (GUSBCFG). + More... +

                                                                              + #include <dwc_otg_regs.h> +@@ -25,60 +13,68 @@ + + + +- ++ + + +- + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ ++ ++ ++ ++ ++ ++ ++ ++ + + +

                                                                              Data Fields

                                                                              +-uint32_t d32
                                                                              ++uint32_t d32
                                                                               raw register data
                                                                              ++
                                                                              + struct {
                                                                                 unsigned   toutcal:3
                                                                                 unsigned   toutcal:3
                                                                                 unsigned   phyif:1
                                                                                 unsigned   phyif:1
                                                                                 unsigned   ulpi_utmi_sel:1
                                                                                 unsigned   ulpi_utmi_sel:1
                                                                                 unsigned   fsintf:1
                                                                                 unsigned   fsintf:1
                                                                                 unsigned   physel:1
                                                                                 unsigned   physel:1
                                                                                 unsigned   ddrsel:1
                                                                                 unsigned   ddrsel:1
                                                                                 unsigned   srpcap:1
                                                                                 unsigned   srpcap:1
                                                                                 unsigned   hnpcap:1
                                                                                 unsigned   hnpcap:1
                                                                                 unsigned   usbtrdtim:4
                                                                                 unsigned   usbtrdtim:4
                                                                                 unsigned   nptxfrwnden:1
                                                                                 unsigned   reserved1:1
                                                                                 unsigned   phylpwrclksel:1
                                                                                 unsigned   phylpwrclksel:1
                                                                                 unsigned   otgutmifssel:1
                                                                                 unsigned   otgutmifssel:1
                                                                                 unsigned   ulpi_fsls:1
                                                                                 unsigned   ulpi_fsls:1
                                                                                 unsigned   ulpi_auto_res:1
                                                                                 unsigned   ulpi_auto_res:1
                                                                                 unsigned   ulpi_clk_sus_m:1
                                                                                 unsigned   ulpi_clk_sus_m:1
                                                                                 unsigned   ulpi_ext_vbus_drv:1
                                                                                 unsigned   ulpi_ext_vbus_drv:1
                                                                                 unsigned   ulpi_int_vbus_indicator:1
                                                                                 unsigned   ulpi_int_vbus_indicator:1
                                                                                 unsigned   term_sel_dl_pulse:1
                                                                                 unsigned   term_sel_dl_pulse:1
                                                                                 unsigned   reserved23_25:3
                                                                                 unsigned   indicator_complement:1
                                                                                 unsigned   ic_usb_cap:1
                                                                                 unsigned   indicator_pass_through:1
                                                                                 unsigned   ic_traffic_pull_remove:1
                                                                                 unsigned   ulpi_int_prot_dis:1
                                                                                 unsigned   tx_end_delay:1
                                                                                 unsigned   ic_usb_cap:1
                                                                                 unsigned   reserved29_31:3
                                                                                 unsigned   ic_traffic_pull_remove:1
                                                                              } b
                                                                                 unsigned   tx_end_delay:1
                                                                                 unsigned   force_host_mode:1
                                                                                 unsigned   force_dev_mode:1
                                                                                 unsigned   reserved31:1
                                                                              } b
                                                                               register bits
                                                                              +@@ -89,10 +85,10 @@ +

                                                                              + +

                                                                              +-Definition at line 247 of file dwc_otg_regs.h.

                                                                              The documentation for this union was generated from the following file:
                                                                                ++Definition at line 267 of file dwc_otg_regs.h.
                                                                                The documentation for this union was generated from the following file: +-
                                                                                Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++
                                                                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
                                                                                ++doxygen 1.3.9.1
                                                                                + + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/unionhaint__data.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/unionhaint__data.html 2013-07-26 19:31:22.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/unionhaint__data.html 2013-07-26 19:34:43.000000000 +0000 +@@ -2,22 +2,10 @@ + + DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: haint_data Union Reference + +- + +- +-
                                                                                +-
                                                                                +-
                                                                                +-
                                                                                +-

                                                                                haint_data Union Reference

                                                                                This union represents the bit fields in the Host All Interrupt Register. ++ ++
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                ++

                                                                                haint_data Union Reference

                                                                                This union represents the bit fields in the Host All Interrupt Register. + More... +

                                                                                + #include <dwc_otg_regs.h> +@@ -25,56 +13,56 @@ + + + +- ++ + + +- + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + + +- + +- ++ + +- ++ + + + +@@ -84,10 +72,10 @@ +

                                                                                + +

                                                                                +-Definition at line 1771 of file dwc_otg_regs.h.

                                                                                The documentation for this union was generated from the following file:
                                                                                  ++Definition at line 2001 of file dwc_otg_regs.h.
                                                                                  The documentation for this union was generated from the following file: +-
                                                                                  Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++
                                                                                  Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
                                                                                  ++doxygen 1.3.9.1
                                                                                  + + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/unionhaintmsk__data.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/unionhaintmsk__data.html 2013-07-26 19:31:22.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/unionhaintmsk__data.html 2013-07-26 19:34:43.000000000 +0000 +@@ -2,22 +2,10 @@ + + DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: haintmsk_data Union Reference + +- + +- +-
                                                                                  +-
                                                                                  +-
                                                                                  +-
                                                                                  +-

                                                                                  haintmsk_data Union Reference

                                                                                  This union represents the bit fields in the Host All Interrupt Register. ++ ++
                                                                                  Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                  ++

                                                                                  haintmsk_data Union Reference

                                                                                  This union represents the bit fields in the Host All Interrupt Register. + More... +

                                                                                  + #include <dwc_otg_regs.h> +@@ -25,56 +13,56 @@ +


                                                                                Data Fields

                                                                                +-uint32_t d32
                                                                                ++uint32_t d32
                                                                                 raw register data
                                                                                ++
                                                                                + struct {
                                                                                   unsigned   ch0:1
                                                                                   unsigned   ch0:1
                                                                                   unsigned   ch1:1
                                                                                   unsigned   ch1:1
                                                                                   unsigned   ch2:1
                                                                                   unsigned   ch2:1
                                                                                   unsigned   ch3:1
                                                                                   unsigned   ch3:1
                                                                                   unsigned   ch4:1
                                                                                   unsigned   ch4:1
                                                                                   unsigned   ch5:1
                                                                                   unsigned   ch5:1
                                                                                   unsigned   ch6:1
                                                                                   unsigned   ch6:1
                                                                                   unsigned   ch7:1
                                                                                   unsigned   ch7:1
                                                                                   unsigned   ch8:1
                                                                                   unsigned   ch8:1
                                                                                   unsigned   ch9:1
                                                                                   unsigned   ch9:1
                                                                                   unsigned   ch10:1
                                                                                   unsigned   ch10:1
                                                                                   unsigned   ch11:1
                                                                                   unsigned   ch11:1
                                                                                   unsigned   ch12:1
                                                                                   unsigned   ch12:1
                                                                                   unsigned   ch13:1
                                                                                   unsigned   ch13:1
                                                                                   unsigned   ch14:1
                                                                                   unsigned   ch14:1
                                                                                   unsigned   ch15:1
                                                                                   unsigned   ch15:1
                                                                                   unsigned   reserved:16
                                                                                   unsigned   reserved:16
                                                                                } b
                                                                                } b
                                                                                 register bits
                                                                                ++
                                                                                + struct {
                                                                                   unsigned   chint:16
                                                                                   unsigned   chint:16
                                                                                   unsigned   reserved:16
                                                                                   unsigned   reserved:16
                                                                                } b2
                                                                                + + +- ++ + + +- + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + + +- + +- ++ + +- ++ + + + +@@ -84,10 +72,10 @@ +

                                                                                + +

                                                                                +-Definition at line 1805 of file dwc_otg_regs.h.

                                                                                The documentation for this union was generated from the following file:
                                                                                  ++Definition at line 2035 of file dwc_otg_regs.h.
                                                                                  The documentation for this union was generated from the following file: +-
                                                                                  Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++
                                                                                  Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
                                                                                  ++doxygen 1.3.9.1
                                                                                  + + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/unionhcchar__data.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/unionhcchar__data.html 2013-07-26 19:31:22.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/unionhcchar__data.html 2013-07-26 19:34:43.000000000 +0000 +@@ -2,22 +2,10 @@ + + DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: hcchar_data Union Reference + +- + +- +-
                                                                                  +-
                                                                                  +-
                                                                                  +-
                                                                                  +-

                                                                                  hcchar_data Union Reference

                                                                                  This union represents the bit fields in the Host Channel Characteristics Register. ++ ++
                                                                                  Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                  ++

                                                                                  hcchar_data Union Reference

                                                                                  This union represents the bit fields in the Host Channel Characteristics Register. + More... +

                                                                                  + #include <dwc_otg_regs.h> +@@ -25,46 +13,46 @@ +


                                                                                Data Fields

                                                                                +-uint32_t d32
                                                                                ++uint32_t d32
                                                                                 raw register data
                                                                                ++
                                                                                + struct {
                                                                                   unsigned   ch0:1
                                                                                   unsigned   ch0:1
                                                                                   unsigned   ch1:1
                                                                                   unsigned   ch1:1
                                                                                   unsigned   ch2:1
                                                                                   unsigned   ch2:1
                                                                                   unsigned   ch3:1
                                                                                   unsigned   ch3:1
                                                                                   unsigned   ch4:1
                                                                                   unsigned   ch4:1
                                                                                   unsigned   ch5:1
                                                                                   unsigned   ch5:1
                                                                                   unsigned   ch6:1
                                                                                   unsigned   ch6:1
                                                                                   unsigned   ch7:1
                                                                                   unsigned   ch7:1
                                                                                   unsigned   ch8:1
                                                                                   unsigned   ch8:1
                                                                                   unsigned   ch9:1
                                                                                   unsigned   ch9:1
                                                                                   unsigned   ch10:1
                                                                                   unsigned   ch10:1
                                                                                   unsigned   ch11:1
                                                                                   unsigned   ch11:1
                                                                                   unsigned   ch12:1
                                                                                   unsigned   ch12:1
                                                                                   unsigned   ch13:1
                                                                                   unsigned   ch13:1
                                                                                   unsigned   ch14:1
                                                                                   unsigned   ch14:1
                                                                                   unsigned   ch15:1
                                                                                   unsigned   ch15:1
                                                                                   unsigned   reserved:16
                                                                                   unsigned   reserved:16
                                                                                } b
                                                                                } b
                                                                                 register bits
                                                                                ++
                                                                                + struct {
                                                                                   unsigned   chint:16
                                                                                   unsigned   chint:16
                                                                                   unsigned   reserved:16
                                                                                   unsigned   reserved:16
                                                                                } b2
                                                                                + + +- ++ + + +- + +- ++ + + +- ++ + + +- ++ + + +- ++ + +- ++ + + +- ++ + + +- ++ + +- +- ++ ++ + + +- ++ + +- +- ++ ++ + + +- ++ + + +- ++ + + +

                                                                                Data Fields

                                                                                +-uint32_t d32
                                                                                ++uint32_t d32
                                                                                 raw register data
                                                                                ++
                                                                                + struct {
                                                                                   unsigned   mps:11
                                                                                   unsigned   mps:11
                                                                                 Maximum packet size in bytes.
                                                                                   unsigned   epnum:4
                                                                                   unsigned   epnum:4
                                                                                 Endpoint number.
                                                                                   unsigned   epdir:1
                                                                                   unsigned   epdir:1
                                                                                 0: OUT, 1: IN
                                                                                   unsigned   reserved:1
                                                                                   unsigned   reserved:1
                                                                                   unsigned   lspddev:1
                                                                                   unsigned   lspddev:1
                                                                                 0: Full/high speed device, 1: Low speed device
                                                                                   unsigned   eptype:2
                                                                                   unsigned   eptype:2
                                                                                 0: Control, 1: Isoc, 2: Bulk, 3: Intr
                                                                                   unsigned   multicnt:2
                                                                                   unsigned   multicnt:2
                                                                                 Packets per frame for periodic transfers.
                                                                                   unsigned   devaddr:7
                                                                                 Packets per frame for periodic transfers.
                                                                                   unsigned   devaddr:7
                                                                                 Device address.
                                                                                   unsigned   oddfrm:1
                                                                                   unsigned   oddfrm:1
                                                                                 Frame to transmit periodic transaction.
                                                                                   unsigned   chdis:1
                                                                                 Frame to transmit periodic transaction.
                                                                                   unsigned   chdis:1
                                                                                 Channel disable.
                                                                                   unsigned   chen:1
                                                                                   unsigned   chen:1
                                                                                 Channel enable.
                                                                                } b
                                                                                } b
                                                                                 register bits
                                                                                +@@ -75,49 +63,65 @@ +

                                                                                + +

                                                                                +-Definition at line 1863 of file dwc_otg_regs.h.

                                                                                Field Documentation

                                                                                +- +-
                                                                                +-
                                                                                +- ++Definition at line 2092 of file dwc_otg_regs.h.

                                                                                Field Documentation

                                                                                ++

                                                                                ++

                                                                                ++ ++ ++ ++
                                                                                ++ + +- ++ + +
                                                                                unsigned hcchar_data::multicnt unsigned hcchar_data::multicnt
                                                                                +- +-
                                                                                ++
                                                                                ++ ++ ++ ++ + + ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ + + + +@@ -262,12 +293,6 @@ + + + +- +- +- +- +- + + +@@ -283,36 +308,7 @@ + echo 0 > /sys/devices/lm0/buspower + */ + +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include /* permission constants */ +-#include +-#include +-#include +-#include +- +- +-#ifdef LM_INTERFACE +-#include +-#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30)) +-#include +-#else +-/* in 2.6.31, at least, we seem to have lost the generic LM infrastructure - +- here we use definitions stolen from arm-integrator headers +-*/ +-#include +-#endif +-#elif defined(PLATFORM_INTERFACE) +-#include +-#endif +- +-#include +- ++#include "dwc_otg_os_dep.h" + #include "dwc_os.h" + #include "dwc_otg_driver.h" + #include "dwc_otg_attr.h" +@@ -481,24 +477,24 @@ + /**@{*/ + + /** ++ * Helper function returning the otg_device structure of the given device ++ */ ++static dwc_otg_device_t *dwc_otg_drvdev(struct device *_dev) ++{ ++ dwc_otg_device_t *otg_dev; ++ DWC_OTG_GETDRVDEV(otg_dev, _dev); ++ return otg_dev; ++} ++ ++/** + * Show the register offset of the Register Access. + */ + static ssize_t regoffset_show(struct device *_dev, + struct device_attribute *attr, char *buf) + { +-#ifdef LM_INTERFACE +- struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev); +- dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev); +-#elif defined(PCI_INTERFACE) +- dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); +-#elif defined(PLATFORM_INTERFACE) +- struct platform_device *platform_dev = container_of(_dev, +- struct platform_device, dev); +- dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev); +-#endif +- ++ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev); + return snprintf(buf, sizeof("0xFFFFFFFF\n") + 1, "0x%08x\n", +- otg_dev->reg_offset); ++ otg_dev->os_dep.reg_offset); + } + + /** +@@ -508,20 +504,14 @@ + struct device_attribute *attr, + const char *buf, size_t count) + { +-#ifdef LM_INTERFACE +- struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev); +- dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev); +-#elif defined(PCI_INTERFACE) +- dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); +-#elif defined(PLATFORM_INTERFACE) +- struct platform_device *platform_dev = container_of(_dev, +- struct platform_device, dev); +- dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev); +-#endif +- ++ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev); + uint32_t offset = simple_strtoul(buf, NULL, 16); +- if (offset < SZ_256K) { +- otg_dev->reg_offset = offset; ++#if defined(LM_INTERFACE) || defined(PLATFORM_INTERFACE) ++ if (offset < SZ_256K) { ++#elif defined(PCI_INTERFACE) ++ if (offset < 0x00040000) { ++#endif ++ otg_dev->os_dep.reg_offset = offset; + } else { + dev_err(_dev, "invalid offset\n"); + } +@@ -538,31 +528,21 @@ + static ssize_t regvalue_show(struct device *_dev, + struct device_attribute *attr, char *buf) + { +-#ifdef LM_INTERFACE +- struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev); +- dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev); +-#elif defined(PCI_INTERFACE) +- dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); +-#elif defined(PLATFORM_INTERFACE) +- struct platform_device *platform_dev = +- container_of(_dev, struct platform_device, dev); +- dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev); +-#endif +- ++ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev); + uint32_t val; + volatile uint32_t *addr; + +- if (otg_dev->reg_offset != 0xFFFFFFFF && 0 != otg_dev->base) { ++ if (otg_dev->os_dep.reg_offset != 0xFFFFFFFF && 0 != otg_dev->os_dep.base) { + /* Calculate the address */ +- addr = (uint32_t *) (otg_dev->reg_offset + +- (uint8_t *) otg_dev->base); +- val = dwc_read_reg32(addr); ++ addr = (uint32_t *) (otg_dev->os_dep.reg_offset + ++ (uint8_t *) otg_dev->os_dep.base); ++ val = DWC_READ_REG32(addr); + return snprintf(buf, + sizeof("Reg@0xFFFFFFFF = 0xFFFFFFFF\n") + 1, +- "Reg@0x%06x = 0x%08x\n", otg_dev->reg_offset, ++ "Reg@0x%06x = 0x%08x\n", otg_dev->os_dep.reg_offset, + val); + } else { +- dev_err(_dev, "Invalid offset (0x%0x)\n", otg_dev->reg_offset); ++ dev_err(_dev, "Invalid offset (0x%0x)\n", otg_dev->os_dep.reg_offset); + return sprintf(buf, "invalid offset\n"); + } + } +@@ -576,28 +556,18 @@ + struct device_attribute *attr, + const char *buf, size_t count) + { +-#ifdef LM_INTERFACE +- struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev); +- dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev); +-#elif defined(PCI_INTERFACE) +- dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); +-#elif defined(PLATFORM_INTERFACE) +- struct platform_device *platform_dev = +- container_of(_dev, struct platform_device, dev); +- dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev); +-#endif +- ++ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev); + volatile uint32_t *addr; + uint32_t val = simple_strtoul(buf, NULL, 16); + //dev_dbg(_dev, "Offset=0x%08x Val=0x%08x\n", otg_dev->reg_offset, val); +- if (otg_dev->reg_offset != 0xFFFFFFFF && 0 != otg_dev->base) { ++ if (otg_dev->os_dep.reg_offset != 0xFFFFFFFF && 0 != otg_dev->os_dep.base) { + /* Calculate the address */ +- addr = (uint32_t *) (otg_dev->reg_offset + +- (uint8_t *) otg_dev->base); +- dwc_write_reg32(addr, val); ++ addr = (uint32_t *) (otg_dev->os_dep.reg_offset + ++ (uint8_t *) otg_dev->os_dep.base); ++ DWC_WRITE_REG32(addr, val); + } else { + dev_err(_dev, "Invalid Register Offset (0x%08x)\n", +- otg_dev->reg_offset); ++ otg_dev->os_dep.reg_offset); + } + return count; + } +@@ -609,7 +579,7 @@ + */ + DWC_OTG_DEVICE_ATTR_BITFIELD_RO(mode, "Mode"); + DWC_OTG_DEVICE_ATTR_BITFIELD_RW(hnpcapable, "HNPCapable"); +-DWC_OTG_DEVICE_ATTR_BITFIELD_RW(srpcapable, "Mode"); ++DWC_OTG_DEVICE_ATTR_BITFIELD_RW(srpcapable, "SRPCapable"); + DWC_OTG_DEVICE_ATTR_BITFIELD_RW(hsic_connect, "HSIC Connect"); + DWC_OTG_DEVICE_ATTR_BITFIELD_RW(inv_sel_hsic, "Invert Select HSIC"); + +@@ -655,16 +625,7 @@ + static ssize_t hnp_show(struct device *_dev, + struct device_attribute *attr, char *buf) + { +-#ifdef LM_INTERFACE +- struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev); +- dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev); +-#elif defined(PCI_INTERFACE) +- dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); +-#elif defined(PLATFORM_INTERFACE) +- struct platform_device *platform_dev = +- container_of(_dev, struct platform_device, dev); +- dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev); +-#endif ++ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev); + return sprintf(buf, "HstNegScs = 0x%x\n", + dwc_otg_get_hnpstatus(otg_dev->core_if)); + } +@@ -676,16 +637,7 @@ + struct device_attribute *attr, + const char *buf, size_t count) + { +-#ifdef LM_INTERFACE +- struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev); +- dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev); +-#elif defined(PCI_INTERFACE) +- dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); +-#elif defined(PLATFORM_INTERFACE) +- struct platform_device *platform_dev = +- container_of(_dev, struct platform_device, dev); +- dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev); +-#endif ++ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev); + uint32_t in = simple_strtoul(buf, NULL, 16); + dwc_otg_set_hnpreq(otg_dev->core_if, in); + return count; +@@ -703,16 +655,7 @@ + struct device_attribute *attr, char *buf) + { + #ifndef DWC_HOST_ONLY +-#ifdef LM_INTERFACE +- struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev); +- dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev); +-#elif defined(PCI_INTERFACE) +- dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); +-#elif defined(PLATFORM_INTERFACE) +- struct platform_device *platform_dev = +- container_of(_dev, struct platform_device, dev); +- dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev); +-#endif ++ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev); + return sprintf(buf, "SesReqScs = 0x%x\n", + dwc_otg_get_srpstatus(otg_dev->core_if)); + #else +@@ -728,16 +671,7 @@ + const char *buf, size_t count) + { + #ifndef DWC_HOST_ONLY +-#ifdef LM_INTERFACE +- struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev); +- dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev); +-#elif defined(PCI_INTERFACE) +- dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); +-#elif defined(PLATFORM_INTERFACE) +- struct platform_device *platform_dev = +- container_of(_dev, struct platform_device, dev); +- dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev); +-#endif ++ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev); + dwc_otg_pcd_initiate_srp(otg_dev->pcd); + #endif + return count; +@@ -754,16 +688,7 @@ + static ssize_t buspower_show(struct device *_dev, + struct device_attribute *attr, char *buf) + { +-#ifdef LM_INTERFACE +- struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev); +- dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev); +-#elif defined(PCI_INTERFACE) +- dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); +-#elif defined(PLATFORM_INTERFACE) +- struct platform_device *platform_dev = +- container_of(_dev, struct platform_device, dev); +- dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev); +-#endif ++ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev); + return sprintf(buf, "Bus Power = 0x%x\n", + dwc_otg_get_prtpower(otg_dev->core_if)); + } +@@ -775,16 +700,7 @@ + struct device_attribute *attr, + const char *buf, size_t count) + { +-#ifdef LM_INTERFACE +- struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev); +- dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev); +-#elif defined(PCI_INTERFACE) +- dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); +-#elif defined(PLATFORM_INTERFACE) +- struct platform_device *platform_dev = +- container_of(_dev, struct platform_device, dev); +- dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev); +-#endif ++ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev); + uint32_t on = simple_strtoul(buf, NULL, 16); + dwc_otg_set_prtpower(otg_dev->core_if, on); + return count; +@@ -801,17 +717,7 @@ + static ssize_t bussuspend_show(struct device *_dev, + struct device_attribute *attr, char *buf) + { +-#ifdef LM_INTERFACE +- struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev); +- dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev); +-#elif defined(PCI_INTERFACE) +- dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); +-#elif defined(PLATFORM_INTERFACE) +- struct platform_device *platform_dev = +- container_of(_dev, struct platform_device, dev); +- dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev); +-#endif +- ++ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev); + return sprintf(buf, "Bus Suspend = 0x%x\n", + dwc_otg_get_prtsuspend(otg_dev->core_if)); + } +@@ -823,17 +729,7 @@ + struct device_attribute *attr, + const char *buf, size_t count) + { +-#ifdef LM_INTERFACE +- struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev); +- dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev); +-#elif defined(PCI_INTERFACE) +- dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); +-#elif defined(PLATFORM_INTERFACE) +- struct platform_device *platform_dev = +- container_of(_dev, struct platform_device, dev); +- dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev); +-#endif +- ++ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev); + uint32_t in = simple_strtoul(buf, NULL, 16); + dwc_otg_set_prtsuspend(otg_dev->core_if, in); + return count; +@@ -842,22 +738,65 @@ + DEVICE_ATTR(bussuspend, 0644, bussuspend_show, bussuspend_store); + + /** ++ * Show the Mode Change Ready Timer status ++ */ ++static ssize_t mode_ch_tim_en_show(struct device *_dev, ++ struct device_attribute *attr, char *buf) ++{ ++ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev); ++ return sprintf(buf, "Mode Change Ready Timer Enable = 0x%x\n", ++ dwc_otg_get_mode_ch_tim(otg_dev->core_if)); ++} ++ ++/** ++ * Set the Mode Change Ready Timer status ++ */ ++static ssize_t mode_ch_tim_en_store(struct device *_dev, ++ struct device_attribute *attr, ++ const char *buf, size_t count) ++{ ++ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev); ++ uint32_t in = simple_strtoul(buf, NULL, 16); ++ dwc_otg_set_mode_ch_tim(otg_dev->core_if, in); ++ return count; ++} ++ ++DEVICE_ATTR(mode_ch_tim_en, 0644, mode_ch_tim_en_show, mode_ch_tim_en_store); ++ ++/** ++ * Show the value of HFIR Frame Interval bitfield ++ */ ++static ssize_t fr_interval_show(struct device *_dev, ++ struct device_attribute *attr, char *buf) ++{ ++ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev); ++ return sprintf(buf, "Frame Interval = 0x%x\n", ++ dwc_otg_get_fr_interval(otg_dev->core_if)); ++} ++ ++/** ++ * Set the HFIR Frame Interval value ++ */ ++static ssize_t fr_interval_store(struct device *_dev, ++ struct device_attribute *attr, ++ const char *buf, size_t count) ++{ ++ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev); ++ uint32_t in = simple_strtoul(buf, NULL, 10); ++ dwc_otg_set_fr_interval(otg_dev->core_if, in); ++ return count; ++} ++ ++DEVICE_ATTR(fr_interval, 0644, fr_interval_show, fr_interval_store); ++ ++/** + * Show the status of Remote Wakeup. + */ + static ssize_t remote_wakeup_show(struct device *_dev, + struct device_attribute *attr, char *buf) + { + #ifndef DWC_HOST_ONLY +-#ifdef LM_INTERFACE +- struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev); +- dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev); +-#elif defined(PCI_INTERFACE) +- dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); +-#elif defined(PLATFORM_INTERFACE) +- struct platform_device *platform_dev = +- container_of(_dev, struct platform_device, dev); +- dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev); +-#endif ++ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev); + + return sprintf(buf, + "Remote Wakeup Sig = %d Enabled = %d LPM Remote Wakeup = %d\n", +@@ -880,17 +819,7 @@ + const char *buf, size_t count) + { + #ifndef DWC_HOST_ONLY +-#ifdef LM_INTERFACE +- struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev); +- dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev); +-#elif defined(PCI_INTERFACE) +- dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); +-#elif defined(PLATFORM_INTERFACE) +- struct platform_device *platform_dev = +- container_of(_dev, struct platform_device, dev); +- dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev); +-#endif +- ++ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev); + uint32_t val = simple_strtoul(buf, NULL, 16); + + if (val & 1) { +@@ -906,22 +835,69 @@ + remote_wakeup_store); + + /** ++ * Show the whether core is hibernated or not. ++ */ ++static ssize_t rem_wakeup_pwrdn_show(struct device *_dev, ++ struct device_attribute *attr, char *buf) ++{ ++#ifndef DWC_HOST_ONLY ++ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev); ++ ++ if (dwc_otg_get_core_state(otg_dev->core_if)) { ++ DWC_PRINTF("Core is in hibernation\n"); ++ } else { ++ DWC_PRINTF("Core is not in hibernation\n"); ++ } ++#endif /* DWC_HOST_ONLY */ ++ return 0; ++} ++ ++extern int dwc_otg_device_hibernation_restore(dwc_otg_core_if_t * core_if, ++ int rem_wakeup, int reset); ++ ++/** ++ * Initiate a remote wakeup of the device to exit from hibernation. ++ */ ++static ssize_t rem_wakeup_pwrdn_store(struct device *_dev, ++ struct device_attribute *attr, ++ const char *buf, size_t count) ++{ ++#ifndef DWC_HOST_ONLY ++ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev); ++ dwc_otg_device_hibernation_restore(otg_dev->core_if, 1, 0); ++#endif ++ return count; ++} ++ ++DEVICE_ATTR(rem_wakeup_pwrdn, S_IRUGO | S_IWUSR, rem_wakeup_pwrdn_show, ++ rem_wakeup_pwrdn_store); ++ ++static ssize_t disconnect_us(struct device *_dev, ++ struct device_attribute *attr, ++ const char *buf, size_t count) ++{ ++ ++#ifndef DWC_HOST_ONLY ++ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev); ++ uint32_t val = simple_strtoul(buf, NULL, 16); ++ DWC_PRINTF("The Passed value is %04x\n", val); ++ ++ dwc_otg_pcd_disconnect_us(otg_dev->pcd, 50); ++ ++#endif /* DWC_HOST_ONLY */ ++ return count; ++} ++ ++DEVICE_ATTR(disconnect_us, S_IWUSR, 0, disconnect_us); ++ ++/** + * Dump global registers and either host or device registers (depending on the + * current mode of the core). + */ + static ssize_t regdump_show(struct device *_dev, + struct device_attribute *attr, char *buf) + { +-#ifdef LM_INTERFACE +- struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev); +- dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev); +-#elif defined(PCI_INTERFACE) +- dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); +-#elif defined(PLATFORM_INTERFACE) +- struct platform_device *platform_dev = +- container_of(_dev, struct platform_device, dev); +- dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev); +-#endif ++ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev); + + dwc_otg_dump_global_registers(otg_dev->core_if); + if (dwc_otg_is_host_mode(otg_dev->core_if)) { +@@ -942,16 +918,7 @@ + static ssize_t spramdump_show(struct device *_dev, + struct device_attribute *attr, char *buf) + { +-#ifdef LM_INTERFACE +- struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev); +- dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev); +-#elif defined(PCI_INTERFACE) +- dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); +-#elif defined(PLATFORM_INTERFACE) +- struct platform_device *platform_dev = +- container_of(_dev, struct platform_device, dev); +- dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev); +-#endif ++ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev); + + dwc_otg_dump_spram(otg_dev->core_if); + +@@ -967,17 +934,7 @@ + struct device_attribute *attr, char *buf) + { + #ifndef DWC_DEVICE_ONLY +-#ifdef LM_INTERFACE +- struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev); +- dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev); +-#elif defined(PCI_INTERFACE) +- dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); +-#elif defined(PLATFORM_INTERFACE) +- struct platform_device *platform_dev = +- container_of(_dev, struct platform_device, dev); +- dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev); +-#endif +- ++ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev); + dwc_otg_hcd_dump_state(otg_dev->hcd); + #endif /* DWC_DEVICE_ONLY */ + return sprintf(buf, "HCD Dump\n"); +@@ -994,16 +951,7 @@ + struct device_attribute *attr, char *buf) + { + #ifndef DWC_DEVICE_ONLY +-#ifdef LM_INTERFACE +- struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev); +- dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev); +-#elif defined(PCI_INTERFACE) +- dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); +-#elif defined(PLATFORM_INTERFACE) +- struct platform_device *platform_dev = +- container_of(_dev, struct platform_device, dev); +- dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev); +-#endif ++ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev); + + dwc_otg_hcd_dump_frrem(otg_dev->hcd); + #endif /* DWC_DEVICE_ONLY */ +@@ -1021,17 +969,7 @@ + static ssize_t rd_reg_test_show(struct device *_dev, + struct device_attribute *attr, char *buf) + { +-#ifdef LM_INTERFACE +- struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev); +- dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev); +-#elif defined(PCI_INTERFACE) +- dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); +-#elif defined(PLATFORM_INTERFACE) +- struct platform_device *platform_dev = +- container_of(_dev, struct platform_device, dev); +- dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev); +-#endif +- ++ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev); + int i; + int time; + int start_jiffies; +@@ -1057,17 +995,7 @@ + static ssize_t wr_reg_test_show(struct device *_dev, + struct device_attribute *attr, char *buf) + { +-#ifdef LM_INTERFACE +- struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev); +- dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev); +-#elif defined(PCI_INTERFACE) +- dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); +-#elif defined(PLATFORM_INTERFACE) +- struct platform_device *platform_dev = +- container_of(_dev, struct platform_device, dev); +- dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev); +-#endif +- ++ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev); + uint32_t reg_val; + int i; + int time; +@@ -1096,16 +1024,7 @@ + static ssize_t lpmresp_show(struct device *_dev, + struct device_attribute *attr, char *buf) + { +-#ifdef LM_INTERFACE +- struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev); +- dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev); +-#elif defined(PCI_INTERFACE) +- dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); +-#elif defined(PLATFORM_INTERFACE) +- struct platform_device *platform_dev = +- container_of(_dev, struct platform_device, dev); +- dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev); +-#endif ++ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev); + + if (!dwc_otg_get_param_lpm_enable(otg_dev->core_if)) + return sprintf(buf, "** LPM is DISABLED **\n"); +@@ -1124,17 +1043,7 @@ + struct device_attribute *attr, + const char *buf, size_t count) + { +-#ifdef LM_INTERFACE +- struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev); +- dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev); +-#elif defined(PCI_INTERFACE) +- dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); +-#elif defined(PLATFORM_INTERFACE) +- struct platform_device *platform_dev = +- container_of(_dev, struct platform_device, dev); +- dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev); +-#endif +- ++ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev); + uint32_t val = simple_strtoul(buf, NULL, 16); + + if (!dwc_otg_get_param_lpm_enable(otg_dev->core_if)) { +@@ -1157,18 +1066,7 @@ + static ssize_t sleepstatus_show(struct device *_dev, + struct device_attribute *attr, char *buf) + { +-#ifdef LM_INTERFACE +- struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev); +- dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev); +-#elif defined(PCI_INTERFACE) +- dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); +-#elif defined(PLATFORM_INTERFACE) +- struct platform_device *platform_dev = +- container_of(_dev, struct platform_device, dev); +- dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev); +-#endif +- +- ++ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev); + return sprintf(buf, "Sleep Status = %d\n", + dwc_otg_get_lpm_portsleepstatus(otg_dev->core_if)); + } +@@ -1180,17 +1078,7 @@ + struct device_attribute *attr, + const char *buf, size_t count) + { +-#ifdef LM_INTERFACE +- struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev); +- dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev); +-#elif defined(PCI_INTERFACE) +- dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); +-#elif defined(PLATFORM_INTERFACE) +- struct platform_device *platform_dev = +- container_of(_dev, struct platform_device, dev); +- dwc_otg_device_t *otg_dev = platform_get_drvdata(platform_dev); +-#endif +- ++ dwc_otg_device_t *otg_dev = dwc_otg_drvdev(_dev); + dwc_otg_core_if_t *core_if = otg_dev->core_if; + + if (dwc_otg_get_lpm_portsleepstatus(otg_dev->core_if)) { +@@ -1207,23 +1095,22 @@ + DEVICE_ATTR(sleep_status, S_IRUGO | S_IWUSR, sleepstatus_show, + sleepstatus_store); + +-#endif /* CONFIG_USB_DWC_OTG_LPM_ENABLE */ ++#endif /* CONFIG_USB_DWC_OTG_LPM_ENABLE */ + + /**@}*/ + + /** + * Create the device files + */ +-void dwc_otg_attr_create ( ++void dwc_otg_attr_create( + #ifdef LM_INTERFACE + struct lm_device *dev + #elif defined(PCI_INTERFACE) + struct pci_dev *dev + #elif defined(PLATFORM_INTERFACE) +- struct platform_device *dev ++ struct platform_device *dev + #endif +- ) +- ++ ) + { + int error; + +@@ -1238,6 +1125,8 @@ + error = device_create_file(&dev->dev, &dev_attr_srp); + error = device_create_file(&dev->dev, &dev_attr_buspower); + error = device_create_file(&dev->dev, &dev_attr_bussuspend); ++ error = device_create_file(&dev->dev, &dev_attr_mode_ch_tim_en); ++ error = device_create_file(&dev->dev, &dev_attr_fr_interval); + error = device_create_file(&dev->dev, &dev_attr_busconnected); + error = device_create_file(&dev->dev, &dev_attr_gotgctl); + error = device_create_file(&dev->dev, &dev_attr_gusbcfg); +@@ -1252,6 +1141,8 @@ + error = device_create_file(&dev->dev, &dev_attr_hptxfsiz); + error = device_create_file(&dev->dev, &dev_attr_hprt0); + error = device_create_file(&dev->dev, &dev_attr_remote_wakeup); ++ error = device_create_file(&dev->dev, &dev_attr_rem_wakeup_pwrdn); ++ error = device_create_file(&dev->dev, &dev_attr_disconnect_us); + error = device_create_file(&dev->dev, &dev_attr_regdump); + error = device_create_file(&dev->dev, &dev_attr_spramdump); + error = device_create_file(&dev->dev, &dev_attr_hcddump); +@@ -1267,7 +1158,7 @@ + /** + * Remove the device files + */ +-void dwc_otg_attr_remove ( ++void dwc_otg_attr_remove( + #ifdef LM_INTERFACE + struct lm_device *dev + #elif defined(PCI_INTERFACE) +@@ -1275,8 +1166,7 @@ + #elif defined(PLATFORM_INTERFACE) + struct platform_device *dev + #endif +- ) +- ++ ) + { + device_remove_file(&dev->dev, &dev_attr_regoffset); + device_remove_file(&dev->dev, &dev_attr_regvalue); +@@ -1289,6 +1179,8 @@ + device_remove_file(&dev->dev, &dev_attr_srp); + device_remove_file(&dev->dev, &dev_attr_buspower); + device_remove_file(&dev->dev, &dev_attr_bussuspend); ++ device_remove_file(&dev->dev, &dev_attr_mode_ch_tim_en); ++ device_remove_file(&dev->dev, &dev_attr_fr_interval); + device_remove_file(&dev->dev, &dev_attr_busconnected); + device_remove_file(&dev->dev, &dev_attr_gotgctl); + device_remove_file(&dev->dev, &dev_attr_gusbcfg); +@@ -1303,6 +1195,8 @@ + device_remove_file(&dev->dev, &dev_attr_hptxfsiz); + device_remove_file(&dev->dev, &dev_attr_hprt0); + device_remove_file(&dev->dev, &dev_attr_remote_wakeup); ++ device_remove_file(&dev->dev, &dev_attr_rem_wakeup_pwrdn); ++ device_remove_file(&dev->dev, &dev_attr_disconnect_us); + device_remove_file(&dev->dev, &dev_attr_regdump); + device_remove_file(&dev->dev, &dev_attr_spramdump); + device_remove_file(&dev->dev, &dev_attr_hcddump); +Index: linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_attr.h +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/dwc_otg_attr.h 2013-07-26 19:31:23.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_attr.h 2013-07-26 19:34:44.000000000 +0000 +@@ -1,8 +1,8 @@ + /* ========================================================================== + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_attr.h $ +- * $Revision: #11 $ +- * $Date: 2009/04/03 $ +- * $Change: 1225160 $ ++ * $Revision: #13 $ ++ * $Date: 2010/06/21 $ ++ * $Change: 1532021 $ + * + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless +@@ -47,6 +47,8 @@ + extern struct device_attribute dev_attr_srp; + extern struct device_attribute dev_attr_buspower; + extern struct device_attribute dev_attr_bussuspend; ++extern struct device_attribute dev_attr_mode_ch_tim_en; ++extern struct device_attribute dev_attr_fr_interval; + extern struct device_attribute dev_attr_busconnected; + extern struct device_attribute dev_attr_gotgctl; + extern struct device_attribute dev_attr_gusbcfg; +@@ -62,27 +64,26 @@ + extern struct device_attribute dev_attr_hprt0; + #ifdef CONFIG_USB_DWC_OTG_LPM + extern struct device_attribute dev_attr_lpm_response; +-extern struct device_attribute dev_attr_sleep_local_dev; + extern struct device_attribute devi_attr_sleep_status; + #endif + +-void dwc_otg_attr_create ( ++void dwc_otg_attr_create( + #ifdef LM_INTERFACE +- struct lm_device *dev ++ struct lm_device *dev + #elif defined(PCI_INTERFACE) +- struct pci_dev *dev ++ struct pci_dev *dev + #elif defined(PLATFORM_INTERFACE) + struct platform_device *dev + #endif +- ); ++ ); + +-void dwc_otg_attr_remove ( ++void dwc_otg_attr_remove( + #ifdef LM_INTERFACE +- struct lm_device *dev ++ struct lm_device *dev + #elif defined(PCI_INTERFACE) +- struct pci_dev *dev ++ struct pci_dev *dev + #elif defined(PLATFORM_INTERFACE) + struct platform_device *dev + #endif +- ); ++ ); + #endif +Index: linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_cfi.c +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/dwc_otg_cfi.c 2013-07-26 19:31:23.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_cfi.c 2013-07-26 19:34:44.000000000 +0000 +@@ -28,7 +28,8 @@ + + /** @file + * +- * This file contains the most of the CFI implementation for the OTG. ++ * This file contains the most of the CFI(Core Feature Interface) ++ * implementation for the OTG. + */ + + #ifdef DWC_UTE_CFI +@@ -285,7 +286,7 @@ + if (wValue == 0) { + /* @TODO - MAS - fix the access to the base field */ + regaddr = 0; +- //regaddr = (uint32_t) pcd->otg_dev->base; ++ //regaddr = (uint32_t) pcd->otg_dev->os_dep.base; + //GET_CORE_IF(pcd)->co + regaddr |= wIndex; + } else { +@@ -293,7 +294,7 @@ + } + + /* Read a 32-bit value of the memory at the regaddr */ +- regval = dwc_read_reg32((uint32_t *) regaddr); ++ regval = DWC_READ_REG32((uint32_t *) regaddr); + + ep = &pcd->ep0; + dwc_memcpy(cfi->buf_in.buf, ®val, sizeof(uint32_t)); +@@ -406,13 +407,13 @@ + CFI_INFO("%s\n", __func__); + + if (cfiobj->buf_in.buf) { +- dwc_dma_free(CFI_IN_BUF_LEN, cfiobj->buf_in.buf, ++ DWC_DMA_FREE(CFI_IN_BUF_LEN, cfiobj->buf_in.buf, + cfiobj->buf_in.addr); + cfiobj->buf_in.buf = NULL; + } + + if (cfiobj->buf_out.buf) { +- dwc_dma_free(CFI_OUT_BUF_LEN, cfiobj->buf_out.buf, ++ DWC_DMA_FREE(CFI_OUT_BUF_LEN, cfiobj->buf_out.buf, + cfiobj->buf_out.addr); + cfiobj->buf_out.buf = NULL; + } +@@ -431,21 +432,21 @@ + static void cfi_free_ep_bs_dyn_data(cfi_ep_t * cfiep) + { + if (cfiep->bm_sg) { +- dwc_free(cfiep->bm_sg); ++ DWC_FREE(cfiep->bm_sg); + cfiep->bm_sg = NULL; + } + + if (cfiep->bm_align) { +- dwc_free(cfiep->bm_align); ++ DWC_FREE(cfiep->bm_align); + cfiep->bm_align = NULL; + } + + if (cfiep->bm_concat) { + if (NULL != cfiep->bm_concat->wTxBytes) { +- dwc_free(cfiep->bm_concat->wTxBytes); ++ DWC_FREE(cfiep->bm_concat->wTxBytes); + cfiep->bm_concat->wTxBytes = NULL; + } +- dwc_free(cfiep->bm_concat); ++ DWC_FREE(cfiep->bm_concat); + cfiep->bm_concat = NULL; + } + } +@@ -459,7 +460,7 @@ + { + int retval = 0; + +- cfiep->bm_sg = dwc_alloc(sizeof(ddma_sg_buffer_setup_t)); ++ cfiep->bm_sg = DWC_ALLOC(sizeof(ddma_sg_buffer_setup_t)); + if (NULL == cfiep->bm_sg) { + CFI_INFO("Failed to allocate memory for SG feature value\n"); + return -DWC_E_NO_MEMORY; +@@ -470,21 +471,21 @@ + * memory for the wTxBytes field - it will be done in the set_feature_value + * request handler. + */ +- cfiep->bm_concat = dwc_alloc(sizeof(ddma_concat_buffer_setup_t)); ++ cfiep->bm_concat = DWC_ALLOC(sizeof(ddma_concat_buffer_setup_t)); + if (NULL == cfiep->bm_concat) { + CFI_INFO + ("Failed to allocate memory for CONCATENATION feature value\n"); +- dwc_free(cfiep->bm_sg); ++ DWC_FREE(cfiep->bm_sg); + return -DWC_E_NO_MEMORY; + } + dwc_memset(cfiep->bm_concat, 0, sizeof(ddma_concat_buffer_setup_t)); + +- cfiep->bm_align = dwc_alloc(sizeof(ddma_align_buffer_setup_t)); ++ cfiep->bm_align = DWC_ALLOC(sizeof(ddma_align_buffer_setup_t)); + if (NULL == cfiep->bm_align) { + CFI_INFO + ("Failed to allocate memory for Alignment feature value\n"); +- dwc_free(cfiep->bm_sg); +- dwc_free(cfiep->bm_concat); ++ DWC_FREE(cfiep->bm_sg); ++ DWC_FREE(cfiep->bm_concat); + return -DWC_E_NO_MEMORY; + } + dwc_memset(cfiep->bm_align, 0, sizeof(ddma_align_buffer_setup_t)); +@@ -516,7 +517,7 @@ + + if (NULL == cfiep) { + /* Allocate a cfi_ep_t object */ +- cfiep = dwc_alloc(sizeof(cfi_ep_t)); ++ cfiep = DWC_ALLOC(sizeof(cfi_ep_t)); + if (NULL == cfiep) { + CFI_INFO + ("Unable to allocate memory for in function %s\n", +@@ -530,12 +531,12 @@ + + /* Allocate the DMA Descriptors chain of MAX_DMA_DESCS_PER_EP count */ + ep->dwc_ep.descs = +- dwc_dma_alloc(MAX_DMA_DESCS_PER_EP * ++ DWC_DMA_ALLOC(MAX_DMA_DESCS_PER_EP * + sizeof(dwc_otg_dma_desc_t), + &ep->dwc_ep.descs_dma_addr); + + if (NULL == ep->dwc_ep.descs) { +- dwc_free(cfiep); ++ DWC_FREE(cfiep); + return -DWC_E_NO_MEMORY; + } + +@@ -596,7 +597,7 @@ + reg_value = *((uint32_t *) buf); + if (wValue == 0) { + addr = 0; +- //addr = (uint32_t) pcd->otg_dev->base; ++ //addr = (uint32_t) pcd->otg_dev->os_dep.base; + addr += wIndex; + } else { + addr = (wValue << 16) | wIndex; +@@ -791,7 +792,7 @@ + struct dwc_otg_pcd_ep *ep, dma_addr_t * dma, + unsigned size, gfp_t flags) + { +- return dwc_dma_alloc(size, dma); ++ return DWC_DMA_ALLOC(size, dma); + } + + /** +@@ -803,7 +804,7 @@ + + /* Allocate a buffer for IN XFERs */ + cfiobj->buf_in.buf = +- dwc_dma_alloc(CFI_IN_BUF_LEN, &cfiobj->buf_in.addr); ++ DWC_DMA_ALLOC(CFI_IN_BUF_LEN, &cfiobj->buf_in.addr); + if (NULL == cfiobj->buf_in.buf) { + CFI_INFO("Unable to allocate buffer for INs\n"); + return -DWC_E_NO_MEMORY; +@@ -811,7 +812,7 @@ + + /* Allocate a buffer for OUT XFERs */ + cfiobj->buf_out.buf = +- dwc_dma_alloc(CFI_OUT_BUF_LEN, &cfiobj->buf_out.addr); ++ DWC_DMA_ALLOC(CFI_OUT_BUF_LEN, &cfiobj->buf_out.addr); + if (NULL == cfiobj->buf_out.buf) { + CFI_INFO("Unable to allocate buffer for OUT\n"); + return -DWC_E_NO_MEMORY; +@@ -925,7 +926,7 @@ + { + /* First we need to free the wTxBytes field */ + if (cfiep->bm_concat->wTxBytes) { +- dwc_free(cfiep->bm_concat->wTxBytes); ++ DWC_FREE(cfiep->bm_concat->wTxBytes); + cfiep->bm_concat->wTxBytes = NULL; + } + +@@ -984,8 +985,9 @@ + params->dev_tx_fifo_size[ep->dwc_ep.tx_fifo_num - + 1]; + params->dev_tx_fifo_size[ep->dwc_ep.tx_fifo_num - 1] = +- GET_CORE_IF(pcd)->init_txfsiz[ep->dwc_ep. +- tx_fifo_num - 1]; ++ GET_CORE_IF(pcd)->init_txfsiz[ep-> ++ dwc_ep.tx_fifo_num - ++ 1]; + } + } + +@@ -1004,13 +1006,14 @@ + int i; + for (i = 0; i < core_if->hwcfg4.b.num_in_eps; + i++) { +- core_if->core_params-> +- dev_tx_fifo_size[i] = tx_siz[i]; ++ core_if-> ++ core_params->dev_tx_fifo_size[i] = ++ tx_siz[i]; + } + } else { +- params->dev_tx_fifo_size[ep->dwc_ep. +- tx_fifo_num - 1] = +- tx_siz[0]; ++ params->dev_tx_fifo_size[ep-> ++ dwc_ep.tx_fifo_num - ++ 1] = tx_siz[0]; + } + } + retval = -DWC_E_INVALID; +@@ -1349,12 +1352,12 @@ + + /* Free the previously allocated storage for the wTxBytes */ + if (ep->bm_concat->wTxBytes) { +- dwc_free(ep->bm_concat->wTxBytes); ++ DWC_FREE(ep->bm_concat->wTxBytes); + } + + /* Allocate a new storage for the wTxBytes field */ + ep->bm_concat->wTxBytes = +- dwc_alloc(sizeof(uint16_t) * pConcatValHdr->bDescCount); ++ DWC_ALLOC(sizeof(uint16_t) * pConcatValHdr->bDescCount); + if (NULL == ep->bm_concat->wTxBytes) { + CFI_INFO("%s: Unable to allocate memory\n", __func__); + return -DWC_E_NO_MEMORY; +@@ -1446,16 +1449,15 @@ + + switch (wValue >> 8) { + case 0: +- return (GET_CORE_IF(pcd)-> +- pwron_txfsiz[ep->dwc_ep.tx_fifo_num - 1] < +- 768) ? GET_CORE_IF(pcd)->pwron_txfsiz[ep->dwc_ep. +- tx_fifo_num - +- 1] : 32768; ++ return (GET_CORE_IF(pcd)->pwron_txfsiz ++ [ep->dwc_ep.tx_fifo_num - 1] < ++ 768) ? GET_CORE_IF(pcd)->pwron_txfsiz[ep-> ++ dwc_ep.tx_fifo_num ++ - 1] : 32768; + break; + case 1: +- return GET_CORE_IF(pcd)->core_params->dev_tx_fifo_size[ep-> +- dwc_ep. +- num - 1]; ++ return GET_CORE_IF(pcd)->core_params-> ++ dev_tx_fifo_size[ep->dwc_ep.num - 1]; + break; + default: + return -DWC_E_INVALID; +@@ -1552,65 +1554,63 @@ + + /* Configure data FIFO sizes */ + if (core_if->hwcfg2.b.dynamic_fifo && params->enable_dynamic_fifo) { +- rx_fsz_bak = dwc_read_reg32(&global_regs->grxfsiz); ++ rx_fsz_bak = DWC_READ_REG32(&global_regs->grxfsiz); + rx_fifo_size = params->dev_rx_fifo_size; +- dwc_write_reg32(&global_regs->grxfsiz, rx_fifo_size); ++ DWC_WRITE_REG32(&global_regs->grxfsiz, rx_fifo_size); + + /* + * Tx FIFOs These FIFOs are numbered from 1 to 15. + * Indexes of the FIFO size module parameters in the + * dev_tx_fifo_size array and the FIFO size registers in +- * the dptxfsiz_dieptxf array run from 0 to 14. ++ * the dtxfsiz array run from 0 to 14. + */ + + /* Non-periodic Tx FIFO */ +- nptxfsz_bak = dwc_read_reg32(&global_regs->gnptxfsiz); ++ nptxfsz_bak = DWC_READ_REG32(&global_regs->gnptxfsiz); + nptxfifosize.b.depth = params->dev_nperio_tx_fifo_size; + start_address = params->dev_rx_fifo_size; + nptxfifosize.b.startaddr = start_address; + +- dwc_write_reg32(&global_regs->gnptxfsiz, nptxfifosize.d32); ++ DWC_WRITE_REG32(&global_regs->gnptxfsiz, nptxfifosize.d32); + + start_address += nptxfifosize.b.depth; + + for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) { +- txfsz_bak[i] = +- dwc_read_reg32(&global_regs->dptxfsiz_dieptxf[i]); ++ txfsz_bak[i] = DWC_READ_REG32(&global_regs->dtxfsiz[i]); + + txfifosize[i].b.depth = params->dev_tx_fifo_size[i]; + txfifosize[i].b.startaddr = start_address; +- dwc_write_reg32(&global_regs->dptxfsiz_dieptxf[i], ++ DWC_WRITE_REG32(&global_regs->dtxfsiz[i], + txfifosize[i].d32); + + start_address += txfifosize[i].b.depth; + } + + /** Check if register values are set correctly */ +- if (rx_fifo_size != dwc_read_reg32(&global_regs->grxfsiz)) { ++ if (rx_fifo_size != DWC_READ_REG32(&global_regs->grxfsiz)) { + retval = 0; + } + +- if (nptxfifosize.d32 != dwc_read_reg32(&global_regs->gnptxfsiz)) { ++ if (nptxfifosize.d32 != DWC_READ_REG32(&global_regs->gnptxfsiz)) { + retval = 0; + } + + for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) { + if (txfifosize[i].d32 != +- dwc_read_reg32(&global_regs->dptxfsiz_dieptxf[i])) { ++ DWC_READ_REG32(&global_regs->dtxfsiz[i])) { + retval = 0; + } + } + + /** If register values are not set correctly, reset old values */ + if (retval == 0) { +- dwc_write_reg32(&global_regs->grxfsiz, rx_fsz_bak); ++ DWC_WRITE_REG32(&global_regs->grxfsiz, rx_fsz_bak); + + /* Non-periodic Tx FIFO */ +- dwc_write_reg32(&global_regs->gnptxfsiz, nptxfsz_bak); ++ DWC_WRITE_REG32(&global_regs->gnptxfsiz, nptxfsz_bak); + + for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) { +- dwc_write_reg32(&global_regs-> +- dptxfsiz_dieptxf[i], ++ DWC_WRITE_REG32(&global_regs->dtxfsiz[i], + txfsz_bak[i]); + } + } +@@ -1873,4 +1873,4 @@ + return retval; + } + +-#endif //DWC_UTE_CFI ++#endif //DWC_UTE_CFI +Index: linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_cfi.h +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/dwc_otg_cfi.h 2013-07-26 19:31:23.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_cfi.h 2013-07-26 19:34:44.000000000 +0000 +@@ -2,7 +2,7 @@ + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless + * otherwise expressly agreed to in writing between Synopsys and you. +- * ++ * + * The Software IS NOT an item of Licensed Software or Licensed Product under + * any End User Software License Agreement or Agreement for Licensed Product + * with Synopsys or any supplement thereto. You are permitted to use and +@@ -12,7 +12,7 @@ + * any information contained herein except pursuant to this license grant from + * Synopsys. If you do not agree with this notice, including the disclaimer + * below, then you are not authorized to use the Software. +- * ++ * + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +@@ -33,10 +33,11 @@ + #include "dwc_cfi_common.h" + + /** +- * @file +- * +- * This file contains the CFI related OTG PCD specific common constants, interfaces +- * (functions and macros) and data structures. ++ * @file ++ * This file contains the CFI related OTG PCD specific common constants, ++ * interfaces(functions and macros) and data structures.The CFI Protocol is an ++ * optional interface for internal testing purposes that a DUT may implement to ++ * support testing of configurable features. + * + */ + +@@ -70,7 +71,7 @@ + #define max(x,y) ({ \ + x > y ? x : y; }) + +-/** ++/** + * Descriptor DMA SG Buffer setup structure (SG buffer). This structure is + * also used for setting up a buffer for Circular DDMA. + */ +@@ -134,7 +135,7 @@ + + /** + * struct cfi_usb_ctrlrequest - the CFI implementation of the struct usb_ctrlrequest +- * This structure encapsulates the standard usb_ctrlrequest and adds a pointer ++ * This structure encapsulates the standard usb_ctrlrequest and adds a pointer + * to the data returned in the data stage of a 3-stage Control Write requests. + */ + struct cfi_usb_ctrlrequest { +@@ -150,7 +151,7 @@ + + /** + * The CFI wrapper of the enabled and activated dwc_otg_pcd_ep structures. +- * This structure is used to store the buffer setup data for any ++ * This structure is used to store the buffer setup data for any + * enabled endpoint in the PCD. + */ + struct cfi_ep { +@@ -170,7 +171,7 @@ + ddma_align_buffer_setup_t *bm_align; + /* XFER length */ + uint32_t xfer_len; +- /* ++ /* + * Count of DMA descriptors currently used. + * The total should not exceed the MAX_DMA_DESCS_PER_EP value + * defined in the dwc_otg_cil.h +@@ -190,7 +191,7 @@ + + /** + * This is the interface for the CFI operations. +- * ++ * + * @param ep_enable Called when any endpoint is enabled and activated. + * @param release Called when the CFI object is released and it needs to correctly + * deallocate the dynamic memory +@@ -229,12 +230,12 @@ + /* This flag shall control the propagation of a specific request + * to the gadget's processing routines. + * 0 - no gadget handling +- * 1 - the gadget needs to know about this request (w/o completing a status ++ * 1 - the gadget needs to know about this request (w/o completing a status + * phase - just return a 0 to the _setup callback) + */ + uint8_t need_gadget_att; + +- /* Flag indicating whether the status IN phase needs to be ++ /* Flag indicating whether the status IN phase needs to be + * completed by the PCD + */ + uint8_t need_status_in_complete; +@@ -316,4 +317,4 @@ + + int cfi_setup(struct dwc_otg_pcd *pcd, struct cfi_usb_ctrlrequest *ctrl); + +-#endif /* (__DWC_OTG_CFI_H__) */ ++#endif /* (__DWC_OTG_CFI_H__) */ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_cil.c +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/dwc_otg_cil.c 2013-07-26 19:31:23.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_cil.c 2013-07-26 19:34:44.000000000 +0000 +@@ -1,13 +1,13 @@ + /* ========================================================================== + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_cil.c $ +- * $Revision: #159 $ +- * $Date: 2009/04/21 $ +- * $Change: 1237465 $ ++ * $Revision: #189 $ ++ * $Date: 2011/10/24 $ ++ * $Change: 1871160 $ + * + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless + * otherwise expressly agreed to in writing between Synopsys and you. +- * ++ * + * The Software IS NOT an item of Licensed Software or Licensed Product under + * any End User Software License Agreement or Agreement for Licensed Product + * with Synopsys or any supplement thereto. You are permitted to use and +@@ -17,7 +17,7 @@ + * any information contained herein except pursuant to this license grant from + * Synopsys. If you do not agree with this notice, including the disclaimer + * below, then you are not authorized to use the Software. +- * ++ * + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +@@ -31,7 +31,7 @@ + * DAMAGE. + * ========================================================================== */ + +-/** @file ++/** @file + * + * The Core Interface Layer provides basic services for accessing and + * managing the DWC_otg hardware. These services are used by both the +@@ -51,7 +51,7 @@ + * + * The Core Interface Layer has the following requirements: + * - Provides basic controller operations. +- * - Minimal use of OS services. ++ * - Minimal use of OS services. + * - The OS services used will be abstracted by using inline functions + * or macros. + * +@@ -63,12 +63,12 @@ + + static int dwc_otg_setup_params(dwc_otg_core_if_t * core_if); + +-/** ++/** + * This function is called to initialize the DWC_otg CSR data +- * structures. The register addresses in the device and host ++ * structures. The register addresses in the device and host + * structures are initialized from the base address supplied by the +- * caller. The calling function must make the OS calls to get the +- * base address of the DWC_otg controller registers. The core_params ++ * caller. The calling function must make the OS calls to get the ++ * base address of the DWC_otg controller registers. The core_params + * argument holds the parameters that specify how the core should be + * configured. + * +@@ -85,9 +85,9 @@ + + DWC_DEBUGPL(DBG_CILV, "%s(%p)\n", __func__, reg_base_addr); + +- core_if = dwc_alloc(sizeof(dwc_otg_core_if_t)); ++ core_if = DWC_ALLOC(sizeof(dwc_otg_core_if_t)); + +- if (core_if == 0) { ++ if (core_if == NULL) { + DWC_DEBUGPL(DBG_CIL, + "Allocation of dwc_otg_core_if_t failed\n"); + return 0; +@@ -97,11 +97,11 @@ + /* + * Allocate the Device Mode structures. + */ +- dev_if = dwc_alloc(sizeof(dwc_otg_dev_if_t)); ++ dev_if = DWC_ALLOC(sizeof(dwc_otg_dev_if_t)); + +- if (dev_if == 0) { ++ if (dev_if == NULL) { + DWC_DEBUGPL(DBG_CIL, "Allocation of dwc_otg_dev_if_t failed\n"); +- dwc_free(core_if); ++ DWC_FREE(core_if); + return 0; + } + +@@ -130,13 +130,13 @@ + /* + * Allocate the Host Mode structures. + */ +- host_if = dwc_alloc(sizeof(dwc_otg_host_if_t)); ++ host_if = DWC_ALLOC(sizeof(dwc_otg_host_if_t)); + +- if (host_if == 0) { ++ if (host_if == NULL) { + DWC_DEBUGPL(DBG_CIL, + "Allocation of dwc_otg_host_if_t failed\n"); +- dwc_free(dev_if); +- dwc_free(core_if); ++ DWC_FREE(dev_if); ++ DWC_FREE(core_if); + return 0; + } + +@@ -161,8 +161,8 @@ + core_if->data_fifo[i] = + (uint32_t *) (reg_base + DWC_OTG_DATA_FIFO_OFFSET + + (i * DWC_OTG_DATA_FIFO_SIZE)); +- DWC_DEBUGPL(DBG_CILV, "data_fifo[%d]=0x%08x\n", +- i, (unsigned)core_if->data_fifo[i]); ++ DWC_DEBUGPL(DBG_CILV, "data_fifo[%d]=0x%08lx\n", ++ i, (unsigned long)core_if->data_fifo[i]); + } + + core_if->pcgcctl = (uint32_t *) (reg_base + DWC_OTG_PCGCCTL_OFFSET); +@@ -174,13 +174,28 @@ + * easy access later. + */ + core_if->hwcfg1.d32 = +- dwc_read_reg32(&core_if->core_global_regs->ghwcfg1); ++ DWC_READ_REG32(&core_if->core_global_regs->ghwcfg1); + core_if->hwcfg2.d32 = +- dwc_read_reg32(&core_if->core_global_regs->ghwcfg2); ++ DWC_READ_REG32(&core_if->core_global_regs->ghwcfg2); + core_if->hwcfg3.d32 = +- dwc_read_reg32(&core_if->core_global_regs->ghwcfg3); ++ DWC_READ_REG32(&core_if->core_global_regs->ghwcfg3); + core_if->hwcfg4.d32 = +- dwc_read_reg32(&core_if->core_global_regs->ghwcfg4); ++ DWC_READ_REG32(&core_if->core_global_regs->ghwcfg4); ++ ++ /* Force host mode to get HPTXFSIZ exact power on value */ ++ { ++ gusbcfg_data_t gusbcfg = {.d32 = 0 }; ++ gusbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg); ++ gusbcfg.b.force_host_mode = 1; ++ DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, gusbcfg.d32); ++ dwc_mdelay(100); ++ core_if->hptxfsiz.d32 = ++ DWC_READ_REG32(&core_if->core_global_regs->hptxfsiz); ++ gusbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg); ++ gusbcfg.b.force_host_mode = 0; ++ DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, gusbcfg.d32); ++ dwc_mdelay(100); ++ } + + DWC_DEBUGPL(DBG_CILV, "hwcfg1=%08x\n", core_if->hwcfg1.d32); + DWC_DEBUGPL(DBG_CILV, "hwcfg2=%08x\n", core_if->hwcfg2.d32); +@@ -188,9 +203,9 @@ + DWC_DEBUGPL(DBG_CILV, "hwcfg4=%08x\n", core_if->hwcfg4.d32); + + core_if->hcfg.d32 = +- dwc_read_reg32(&core_if->host_if->host_global_regs->hcfg); ++ DWC_READ_REG32(&core_if->host_if->host_global_regs->hcfg); + core_if->dcfg.d32 = +- dwc_read_reg32(&core_if->dev_if->dev_global_regs->dcfg); ++ DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg); + + DWC_DEBUGPL(DBG_CILV, "hcfg=%08x\n", core_if->hcfg.d32); + DWC_DEBUGPL(DBG_CILV, "dcfg=%08x\n", core_if->dcfg.d32); +@@ -224,13 +239,13 @@ + core_if->wq_otg = DWC_WORKQ_ALLOC("dwc_otg"); + if (core_if->wq_otg == 0) { + DWC_WARN("DWC_WORKQ_ALLOC failed\n"); +- dwc_free(host_if); +- dwc_free(dev_if); +- dwc_free(core_if); ++ DWC_FREE(host_if); ++ DWC_FREE(dev_if); ++ DWC_FREE(core_if); + return 0; + } + +- core_if->snpsid = dwc_read_reg32(&core_if->core_global_regs->gsnpsid); ++ core_if->snpsid = DWC_READ_REG32(&core_if->core_global_regs->gsnpsid); + + DWC_PRINTF("Core Release: %x.%x%x%x\n", + (core_if->snpsid >> 12 & 0xF), +@@ -241,10 +256,10 @@ + w_wakeup_detected, core_if); + if (core_if->wkp_timer == 0) { + DWC_WARN("DWC_TIMER_ALLOC failed\n"); +- dwc_free(host_if); +- dwc_free(dev_if); ++ DWC_FREE(host_if); ++ DWC_FREE(dev_if); + DWC_WORKQ_FREE(core_if->wq_otg); +- dwc_free(core_if); ++ DWC_FREE(core_if); + return 0; + } + +@@ -252,12 +267,17 @@ + DWC_WARN("Error while setting core params\n"); + } + ++ core_if->hibernation_suspend = 0; ++ ++ /** ADP initialization */ ++ dwc_otg_adp_init(core_if); ++ + return core_if; + } + + /** + * This function frees the structures allocated by dwc_otg_cil_init(). +- * ++ * + * @param core_if The core interface pointer returned from + * dwc_otg_cil_init(). + * +@@ -267,22 +287,32 @@ + DWC_DEBUGPL(DBG_CILV, "%s(%p)\n", __func__, core_if); + + /* Disable all interrupts */ +- dwc_modify_reg32(&core_if->core_global_regs->gahbcfg, 1, 0); +- dwc_write_reg32(&core_if->core_global_regs->gintmsk, 0); ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gahbcfg, 1, 0); ++ DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, 0); + + if (core_if->wq_otg) { + DWC_WORKQ_WAIT_WORK_DONE(core_if->wq_otg, 500); + DWC_WORKQ_FREE(core_if->wq_otg); + } + if (core_if->dev_if) { +- dwc_free(core_if->dev_if); ++ DWC_FREE(core_if->dev_if); + } + if (core_if->host_if) { +- dwc_free(core_if->host_if); ++ DWC_FREE(core_if->host_if); ++ } ++ ++ /** Remove ADP Stuff */ ++ dwc_otg_adp_remove(core_if); ++ if (core_if->core_params) { ++ DWC_FREE(core_if->core_params); ++ } ++ if (core_if->wkp_timer) { ++ DWC_TIMER_FREE(core_if->wkp_timer); + } +- dwc_free(core_if); +- DWC_TIMER_FREE(core_if->wkp_timer); +- DWC_FREE(core_if->core_params); ++ if (core_if->srp_timer) { ++ DWC_TIMER_FREE(core_if->srp_timer); ++ } ++ DWC_FREE(core_if); + } + + /** +@@ -295,7 +325,7 @@ + { + gahbcfg_data_t ahbcfg = {.d32 = 0 }; + ahbcfg.b.glblintrmsk = 1; /* Enable interrupts */ +- dwc_modify_reg32(&core_if->core_global_regs->gahbcfg, 0, ahbcfg.d32); ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gahbcfg, 0, ahbcfg.d32); + } + + /** +@@ -307,9 +337,8 @@ + void dwc_otg_disable_global_interrupts(dwc_otg_core_if_t * core_if) + { + gahbcfg_data_t ahbcfg = {.d32 = 0 }; +- ahbcfg.b.glblintrmsk = 1; /* Enable interrupts */ +- DWC_PRINTF("%x -> %x\n", (unsigned int)&core_if->core_global_regs->gahbcfg, ahbcfg.d32); +- dwc_modify_reg32(&core_if->core_global_regs->gahbcfg, ahbcfg.d32, 0); ++ ahbcfg.b.glblintrmsk = 1; /* Disable interrupts */ ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gahbcfg, ahbcfg.d32, 0); + } + + /** +@@ -325,13 +354,13 @@ + gintmsk_data_t intr_mask = {.d32 = 0 }; + + /* Clear any pending OTG Interrupts */ +- dwc_write_reg32(&global_regs->gotgint, 0xFFFFFFFF); ++ DWC_WRITE_REG32(&global_regs->gotgint, 0xFFFFFFFF); + + /* Clear any pending interrupts */ +- dwc_write_reg32(&global_regs->gintsts, 0xFFFFFFFF); ++ DWC_WRITE_REG32(&global_regs->gintsts, 0xFFFFFFFF); + +- /* +- * Enable the interrupts in the GINTMSK. ++ /* ++ * Enable the interrupts in the GINTMSK. + */ + intr_mask.b.modemismatch = 1; + intr_mask.b.otgintr = 1; +@@ -342,7 +371,7 @@ + + intr_mask.b.conidstschng = 1; + intr_mask.b.wkupintr = 1; +- intr_mask.b.disconnect = 1; ++ intr_mask.b.disconnect = 0; + intr_mask.b.usbsuspend = 1; + intr_mask.b.sessreqintr = 1; + #ifdef CONFIG_USB_DWC_OTG_LPM +@@ -350,7 +379,709 @@ + intr_mask.b.lpmtranrcvd = 1; + } + #endif +- dwc_write_reg32(&global_regs->gintmsk, intr_mask.d32); ++ DWC_WRITE_REG32(&global_regs->gintmsk, intr_mask.d32); ++} ++ ++/* ++ * The restore operation is modified to support Synopsys Emulated Powerdown and ++ * Hibernation. This function is for exiting from Device mode hibernation by ++ * Host Initiated Resume/Reset and Device Initiated Remote-Wakeup. ++ * @param core_if Programming view of DWC_otg controller. ++ * @param rem_wakeup - indicates whether resume is initiated by Device or Host. ++ * @param reset - indicates whether resume is initiated by Reset. ++ */ ++int dwc_otg_device_hibernation_restore(dwc_otg_core_if_t * core_if, ++ int rem_wakeup, int reset) ++{ ++ gpwrdn_data_t gpwrdn = {.d32 = 0 }; ++ pcgcctl_data_t pcgcctl = {.d32 = 0 }; ++ dctl_data_t dctl = {.d32 = 0 }; ++ ++ int timeout = 2000; ++ ++ if (!core_if->hibernation_suspend) { ++ DWC_PRINTF("Already exited from Hibernation\n"); ++ return 1; ++ } ++ ++ DWC_DEBUGPL(DBG_PCD, "%s called\n", __FUNCTION__); ++ /* Switch-on voltage to the core */ ++ gpwrdn.b.pwrdnswtch = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ dwc_udelay(10); ++ ++ /* Reset core */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pwrdnrstn = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ dwc_udelay(10); ++ ++ /* Assert Restore signal */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.restore = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32); ++ dwc_udelay(10); ++ ++ /* Disable power clamps */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pwrdnclmp = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ ++ if (rem_wakeup) { ++ dwc_udelay(70); ++ } ++ ++ /* Deassert Reset core */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pwrdnrstn = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32); ++ dwc_udelay(10); ++ ++ /* Disable PMU interrupt */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pmuintsel = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ ++ /* Mask interrupts from gpwrdn */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.connect_det_msk = 1; ++ gpwrdn.b.srp_det_msk = 1; ++ gpwrdn.b.disconn_det_msk = 1; ++ gpwrdn.b.rst_det_msk = 1; ++ gpwrdn.b.lnstchng_msk = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ ++ /* Indicates that we are going out from hibernation */ ++ core_if->hibernation_suspend = 0; ++ ++ /* ++ * Set Restore Essential Regs bit in PCGCCTL register, restore_mode = 1 ++ * indicates restore from remote_wakeup ++ */ ++ restore_essential_regs(core_if, rem_wakeup, 0); ++ ++ /* ++ * Wait a little for seeing new value of variable hibernation_suspend if ++ * Restore done interrupt received before polling ++ */ ++ dwc_udelay(10); ++ ++ if (core_if->hibernation_suspend == 0) { ++ /* ++ * Wait For Restore_done Interrupt. This mechanism of polling the ++ * interrupt is introduced to avoid any possible race conditions ++ */ ++ do { ++ gintsts_data_t gintsts; ++ gintsts.d32 = ++ DWC_READ_REG32(&core_if->core_global_regs->gintsts); ++ if (gintsts.b.restoredone) { ++ gintsts.d32 = 0; ++ gintsts.b.restoredone = 1; ++ DWC_WRITE_REG32(&core_if->core_global_regs-> ++ gintsts, gintsts.d32); ++ DWC_PRINTF("Restore Done Interrupt seen\n"); ++ break; ++ } ++ dwc_udelay(10); ++ } while (--timeout); ++ if (!timeout) { ++ DWC_PRINTF("Restore Done interrupt wasn't generated here\n"); ++ } ++ } ++ /* Clear all pending interupts */ ++ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF); ++ ++ /* De-assert Restore */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.restore = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ dwc_udelay(10); ++ ++ if (!rem_wakeup) { ++ pcgcctl.d32 = 0; ++ pcgcctl.b.rstpdwnmodule = 1; ++ DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32, 0); ++ } ++ ++ /* Restore GUSBCFG and DCFG */ ++ DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, ++ core_if->gr_backup->gusbcfg_local); ++ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dcfg, ++ core_if->dr_backup->dcfg); ++ ++ /* De-assert Wakeup Logic */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pmuactv = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ dwc_udelay(10); ++ ++ if (!rem_wakeup) { ++ /* Set Device programming done bit */ ++ dctl.b.pwronprgdone = 1; ++ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, 0, dctl.d32); ++ } else { ++ /* Start Remote Wakeup Signaling */ ++ dctl.d32 = core_if->dr_backup->dctl; ++ dctl.b.rmtwkupsig = 1; ++ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32); ++ } ++ ++ dwc_mdelay(2); ++ /* Clear all pending interupts */ ++ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF); ++ ++ /* Restore global registers */ ++ dwc_otg_restore_global_regs(core_if); ++ /* Restore device global registers */ ++ dwc_otg_restore_dev_regs(core_if, rem_wakeup); ++ ++ if (rem_wakeup) { ++ dwc_mdelay(7); ++ dctl.d32 = 0; ++ dctl.b.rmtwkupsig = 1; ++ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32, 0); ++ } ++ ++ core_if->hibernation_suspend = 0; ++ /* The core will be in ON STATE */ ++ core_if->lx_state = DWC_OTG_L0; ++ DWC_PRINTF("Hibernation recovery completes here\n"); ++ ++ return 1; ++} ++ ++/* ++ * The restore operation is modified to support Synopsys Emulated Powerdown and ++ * Hibernation. This function is for exiting from Host mode hibernation by ++ * Host Initiated Resume/Reset and Device Initiated Remote-Wakeup. ++ * @param core_if Programming view of DWC_otg controller. ++ * @param rem_wakeup - indicates whether resume is initiated by Device or Host. ++ * @param reset - indicates whether resume is initiated by Reset. ++ */ ++int dwc_otg_host_hibernation_restore(dwc_otg_core_if_t * core_if, ++ int rem_wakeup, int reset) ++{ ++ gpwrdn_data_t gpwrdn = {.d32 = 0 }; ++ hprt0_data_t hprt0 = {.d32 = 0 }; ++ ++ int timeout = 2000; ++ ++ DWC_DEBUGPL(DBG_HCD, "%s called\n", __FUNCTION__); ++ /* Switch-on voltage to the core */ ++ gpwrdn.b.pwrdnswtch = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ dwc_udelay(10); ++ ++ /* Reset core */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pwrdnrstn = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ dwc_udelay(10); ++ ++ /* Assert Restore signal */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.restore = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32); ++ dwc_udelay(10); ++ ++ /* Disable power clamps */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pwrdnclmp = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ ++ if (!rem_wakeup) { ++ dwc_udelay(50); ++ } ++ ++ /* Deassert Reset core */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pwrdnrstn = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32); ++ dwc_udelay(10); ++ ++ /* Disable PMU interrupt */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pmuintsel = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.connect_det_msk = 1; ++ gpwrdn.b.srp_det_msk = 1; ++ gpwrdn.b.disconn_det_msk = 1; ++ gpwrdn.b.rst_det_msk = 1; ++ gpwrdn.b.lnstchng_msk = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ ++ /* Indicates that we are going out from hibernation */ ++ core_if->hibernation_suspend = 0; ++ ++ /* Set Restore Essential Regs bit in PCGCCTL register */ ++ restore_essential_regs(core_if, rem_wakeup, 1); ++ ++ /* Wait a little for seeing new value of variable hibernation_suspend if ++ * Restore done interrupt received before polling */ ++ dwc_udelay(10); ++ ++ if (core_if->hibernation_suspend == 0) { ++ /* Wait For Restore_done Interrupt. This mechanism of polling the ++ * interrupt is introduced to avoid any possible race conditions ++ */ ++ do { ++ gintsts_data_t gintsts; ++ gintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts); ++ if (gintsts.b.restoredone) { ++ gintsts.d32 = 0; ++ gintsts.b.restoredone = 1; ++ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32); ++ DWC_DEBUGPL(DBG_HCD,"Restore Done Interrupt seen\n"); ++ break; ++ } ++ dwc_udelay(10); ++ } while (--timeout); ++ if (!timeout) { ++ DWC_WARN("Restore Done interrupt wasn't generated\n"); ++ } ++ } ++ ++ /* Set the flag's value to 0 again after receiving restore done interrupt */ ++ core_if->hibernation_suspend = 0; ++ ++ /* This step is not described in functional spec but if not wait for this ++ * delay, mismatch interrupts occurred because just after restore core is ++ * in Device mode(gintsts.curmode == 0) */ ++ dwc_mdelay(100); ++ ++ /* Clear all pending interrupts */ ++ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF); ++ ++ /* De-assert Restore */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.restore = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ dwc_udelay(10); ++ ++ /* Restore GUSBCFG and HCFG */ ++ DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, ++ core_if->gr_backup->gusbcfg_local); ++ DWC_WRITE_REG32(&core_if->host_if->host_global_regs->hcfg, ++ core_if->hr_backup->hcfg_local); ++ ++ /* De-assert Wakeup Logic */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pmuactv = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ dwc_udelay(10); ++ ++ /* Start the Resume operation by programming HPRT0 */ ++ hprt0.d32 = core_if->hr_backup->hprt0_local; ++ hprt0.b.prtpwr = 1; ++ hprt0.b.prtena = 0; ++ hprt0.b.prtsusp = 0; ++ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32); ++ ++ DWC_PRINTF("Resume Starts Now\n"); ++ if (!reset) { // Indicates it is Resume Operation ++ hprt0.d32 = core_if->hr_backup->hprt0_local; ++ hprt0.b.prtres = 1; ++ hprt0.b.prtpwr = 1; ++ hprt0.b.prtena = 0; ++ hprt0.b.prtsusp = 0; ++ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32); ++ ++ if (!rem_wakeup) ++ hprt0.b.prtres = 0; ++ /* Wait for Resume time and then program HPRT again */ ++ dwc_mdelay(100); ++ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32); ++ ++ } else { // Indicates it is Reset Operation ++ hprt0.d32 = core_if->hr_backup->hprt0_local; ++ hprt0.b.prtrst = 1; ++ hprt0.b.prtpwr = 1; ++ hprt0.b.prtena = 0; ++ hprt0.b.prtsusp = 0; ++ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32); ++ /* Wait for Reset time and then program HPRT again */ ++ dwc_mdelay(60); ++ hprt0.b.prtrst = 0; ++ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32); ++ } ++ /* Clear all interrupt status */ ++ hprt0.d32 = dwc_otg_read_hprt0(core_if); ++ hprt0.b.prtconndet = 1; ++ hprt0.b.prtenchng = 1; ++ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32); ++ ++ /* Clear all pending interupts */ ++ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF); ++ ++ /* Restore global registers */ ++ dwc_otg_restore_global_regs(core_if); ++ /* Restore host global registers */ ++ dwc_otg_restore_host_regs(core_if, reset); ++ ++ /* The core will be in ON STATE */ ++ core_if->lx_state = DWC_OTG_L0; ++ DWC_PRINTF("Hibernation recovery is complete here\n"); ++ return 0; ++} ++ ++/** Saves some register values into system memory. */ ++int dwc_otg_save_global_regs(dwc_otg_core_if_t * core_if) ++{ ++ struct dwc_otg_global_regs_backup *gr; ++ int i; ++ ++ gr = core_if->gr_backup; ++ if (!gr) { ++ gr = DWC_ALLOC(sizeof(*gr)); ++ if (!gr) { ++ return -DWC_E_NO_MEMORY; ++ } ++ core_if->gr_backup = gr; ++ } ++ ++ gr->gotgctl_local = DWC_READ_REG32(&core_if->core_global_regs->gotgctl); ++ gr->gintmsk_local = DWC_READ_REG32(&core_if->core_global_regs->gintmsk); ++ gr->gahbcfg_local = DWC_READ_REG32(&core_if->core_global_regs->gahbcfg); ++ gr->gusbcfg_local = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg); ++ gr->grxfsiz_local = DWC_READ_REG32(&core_if->core_global_regs->grxfsiz); ++ gr->gnptxfsiz_local = DWC_READ_REG32(&core_if->core_global_regs->gnptxfsiz); ++ gr->hptxfsiz_local = DWC_READ_REG32(&core_if->core_global_regs->hptxfsiz); ++#ifdef CONFIG_USB_DWC_OTG_LPM ++ gr->glpmcfg_local = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg); ++#endif ++ gr->gi2cctl_local = DWC_READ_REG32(&core_if->core_global_regs->gi2cctl); ++ gr->pcgcctl_local = DWC_READ_REG32(core_if->pcgcctl); ++ gr->gdfifocfg_local = ++ DWC_READ_REG32(&core_if->core_global_regs->gdfifocfg); ++ for (i = 0; i < MAX_EPS_CHANNELS; i++) { ++ gr->dtxfsiz_local[i] = ++ DWC_READ_REG32(&(core_if->core_global_regs->dtxfsiz[i])); ++ } ++ ++ DWC_DEBUGPL(DBG_ANY, "===========Backing Global registers==========\n"); ++ DWC_DEBUGPL(DBG_ANY, "Backed up gotgctl = %08x\n", gr->gotgctl_local); ++ DWC_DEBUGPL(DBG_ANY, "Backed up gintmsk = %08x\n", gr->gintmsk_local); ++ DWC_DEBUGPL(DBG_ANY, "Backed up gahbcfg = %08x\n", gr->gahbcfg_local); ++ DWC_DEBUGPL(DBG_ANY, "Backed up gusbcfg = %08x\n", gr->gusbcfg_local); ++ DWC_DEBUGPL(DBG_ANY, "Backed up grxfsiz = %08x\n", gr->grxfsiz_local); ++ DWC_DEBUGPL(DBG_ANY, "Backed up gnptxfsiz = %08x\n", ++ gr->gnptxfsiz_local); ++ DWC_DEBUGPL(DBG_ANY, "Backed up hptxfsiz = %08x\n", ++ gr->hptxfsiz_local); ++#ifdef CONFIG_USB_DWC_OTG_LPM ++ DWC_DEBUGPL(DBG_ANY, "Backed up glpmcfg = %08x\n", gr->glpmcfg_local); ++#endif ++ DWC_DEBUGPL(DBG_ANY, "Backed up gi2cctl = %08x\n", gr->gi2cctl_local); ++ DWC_DEBUGPL(DBG_ANY, "Backed up pcgcctl = %08x\n", gr->pcgcctl_local); ++ DWC_DEBUGPL(DBG_ANY,"Backed up gdfifocfg = %08x\n",gr->gdfifocfg_local); ++ ++ return 0; ++} ++ ++/** Saves GINTMSK register before setting the msk bits. */ ++int dwc_otg_save_gintmsk_reg(dwc_otg_core_if_t * core_if) ++{ ++ struct dwc_otg_global_regs_backup *gr; ++ ++ gr = core_if->gr_backup; ++ if (!gr) { ++ gr = DWC_ALLOC(sizeof(*gr)); ++ if (!gr) { ++ return -DWC_E_NO_MEMORY; ++ } ++ core_if->gr_backup = gr; ++ } ++ ++ gr->gintmsk_local = DWC_READ_REG32(&core_if->core_global_regs->gintmsk); ++ ++ DWC_DEBUGPL(DBG_ANY,"=============Backing GINTMSK registers============\n"); ++ DWC_DEBUGPL(DBG_ANY, "Backed up gintmsk = %08x\n", gr->gintmsk_local); ++ ++ return 0; ++} ++ ++int dwc_otg_save_dev_regs(dwc_otg_core_if_t * core_if) ++{ ++ struct dwc_otg_dev_regs_backup *dr; ++ int i; ++ ++ dr = core_if->dr_backup; ++ if (!dr) { ++ dr = DWC_ALLOC(sizeof(*dr)); ++ if (!dr) { ++ return -DWC_E_NO_MEMORY; ++ } ++ core_if->dr_backup = dr; ++ } ++ ++ dr->dcfg = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg); ++ dr->dctl = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dctl); ++ dr->daintmsk = ++ DWC_READ_REG32(&core_if->dev_if->dev_global_regs->daintmsk); ++ dr->diepmsk = ++ DWC_READ_REG32(&core_if->dev_if->dev_global_regs->diepmsk); ++ dr->doepmsk = ++ DWC_READ_REG32(&core_if->dev_if->dev_global_regs->doepmsk); ++ ++ for (i = 0; i < core_if->dev_if->num_in_eps; ++i) { ++ dr->diepctl[i] = ++ DWC_READ_REG32(&core_if->dev_if->in_ep_regs[i]->diepctl); ++ dr->dieptsiz[i] = ++ DWC_READ_REG32(&core_if->dev_if->in_ep_regs[i]->dieptsiz); ++ dr->diepdma[i] = ++ DWC_READ_REG32(&core_if->dev_if->in_ep_regs[i]->diepdma); ++ } ++ ++ DWC_DEBUGPL(DBG_ANY, ++ "=============Backing Host registers==============\n"); ++ DWC_DEBUGPL(DBG_ANY, "Backed up dcfg = %08x\n", dr->dcfg); ++ DWC_DEBUGPL(DBG_ANY, "Backed up dctl = %08x\n", dr->dctl); ++ DWC_DEBUGPL(DBG_ANY, "Backed up daintmsk = %08x\n", ++ dr->daintmsk); ++ DWC_DEBUGPL(DBG_ANY, "Backed up diepmsk = %08x\n", dr->diepmsk); ++ DWC_DEBUGPL(DBG_ANY, "Backed up doepmsk = %08x\n", dr->doepmsk); ++ for (i = 0; i < core_if->dev_if->num_in_eps; ++i) { ++ DWC_DEBUGPL(DBG_ANY, "Backed up diepctl[%d] = %08x\n", i, ++ dr->diepctl[i]); ++ DWC_DEBUGPL(DBG_ANY, "Backed up dieptsiz[%d] = %08x\n", ++ i, dr->dieptsiz[i]); ++ DWC_DEBUGPL(DBG_ANY, "Backed up diepdma[%d] = %08x\n", i, ++ dr->diepdma[i]); ++ } ++ ++ return 0; ++} ++ ++int dwc_otg_save_host_regs(dwc_otg_core_if_t * core_if) ++{ ++ struct dwc_otg_host_regs_backup *hr; ++ int i; ++ ++ hr = core_if->hr_backup; ++ if (!hr) { ++ hr = DWC_ALLOC(sizeof(*hr)); ++ if (!hr) { ++ return -DWC_E_NO_MEMORY; ++ } ++ core_if->hr_backup = hr; ++ } ++ ++ hr->hcfg_local = ++ DWC_READ_REG32(&core_if->host_if->host_global_regs->hcfg); ++ hr->haintmsk_local = ++ DWC_READ_REG32(&core_if->host_if->host_global_regs->haintmsk); ++ for (i = 0; i < dwc_otg_get_param_host_channels(core_if); ++i) { ++ hr->hcintmsk_local[i] = ++ DWC_READ_REG32(&core_if->host_if->hc_regs[i]->hcintmsk); ++ } ++ hr->hprt0_local = DWC_READ_REG32(core_if->host_if->hprt0); ++ hr->hfir_local = ++ DWC_READ_REG32(&core_if->host_if->host_global_regs->hfir); ++ ++ DWC_DEBUGPL(DBG_ANY, ++ "=============Backing Host registers===============\n"); ++ DWC_DEBUGPL(DBG_ANY, "Backed up hcfg = %08x\n", ++ hr->hcfg_local); ++ DWC_DEBUGPL(DBG_ANY, "Backed up haintmsk = %08x\n", hr->haintmsk_local); ++ for (i = 0; i < dwc_otg_get_param_host_channels(core_if); ++i) { ++ DWC_DEBUGPL(DBG_ANY, "Backed up hcintmsk[%02d]=%08x\n", i, ++ hr->hcintmsk_local[i]); ++ } ++ DWC_DEBUGPL(DBG_ANY, "Backed up hprt0 = %08x\n", ++ hr->hprt0_local); ++ DWC_DEBUGPL(DBG_ANY, "Backed up hfir = %08x\n", ++ hr->hfir_local); ++ ++ return 0; ++} ++ ++int dwc_otg_restore_global_regs(dwc_otg_core_if_t *core_if) ++{ ++ struct dwc_otg_global_regs_backup *gr; ++ int i; ++ ++ gr = core_if->gr_backup; ++ if (!gr) { ++ return -DWC_E_INVALID; ++ } ++ ++ DWC_WRITE_REG32(&core_if->core_global_regs->gotgctl, gr->gotgctl_local); ++ DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, gr->gintmsk_local); ++ DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, gr->gusbcfg_local); ++ DWC_WRITE_REG32(&core_if->core_global_regs->gahbcfg, gr->gahbcfg_local); ++ DWC_WRITE_REG32(&core_if->core_global_regs->grxfsiz, gr->grxfsiz_local); ++ DWC_WRITE_REG32(&core_if->core_global_regs->gnptxfsiz, ++ gr->gnptxfsiz_local); ++ DWC_WRITE_REG32(&core_if->core_global_regs->hptxfsiz, ++ gr->hptxfsiz_local); ++ DWC_WRITE_REG32(&core_if->core_global_regs->gdfifocfg, ++ gr->gdfifocfg_local); ++ for (i = 0; i < MAX_EPS_CHANNELS; i++) { ++ DWC_WRITE_REG32(&core_if->core_global_regs->dtxfsiz[i], ++ gr->dtxfsiz_local[i]); ++ } ++ ++ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF); ++ DWC_WRITE_REG32(core_if->host_if->hprt0, 0x0000100A); ++ DWC_WRITE_REG32(&core_if->core_global_regs->gahbcfg, ++ (gr->gahbcfg_local)); ++ return 0; ++} ++ ++int dwc_otg_restore_dev_regs(dwc_otg_core_if_t * core_if, int rem_wakeup) ++{ ++ struct dwc_otg_dev_regs_backup *dr; ++ int i; ++ ++ dr = core_if->dr_backup; ++ ++ if (!dr) { ++ return -DWC_E_INVALID; ++ } ++ ++ if (!rem_wakeup) ++ { ++ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl, dr->dctl); ++ } ++ ++ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->daintmsk, dr->daintmsk); ++ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->diepmsk, dr->diepmsk); ++ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->doepmsk, dr->doepmsk); ++ ++ for (i = 0; i < core_if->dev_if->num_in_eps; ++i) { ++ DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[i]->diepctl, dr->diepctl[i]); ++ DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[i]->dieptsiz, dr->dieptsiz[i]); ++ DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[i]->diepdma, dr->diepdma[i]); ++ } ++ ++ return 0; ++} ++ ++int dwc_otg_restore_host_regs(dwc_otg_core_if_t * core_if, int reset) ++{ ++ struct dwc_otg_host_regs_backup *hr; ++ int i; ++ hr = core_if->hr_backup; ++ ++ if (!hr) { ++ return -DWC_E_INVALID; ++ } ++ ++ DWC_WRITE_REG32(&core_if->host_if->host_global_regs->hcfg, hr->hcfg_local); ++ //if (!reset) ++ //{ ++ // DWC_WRITE_REG32(&core_if->host_if->host_global_regs->hfir, hr->hfir_local); ++ //} ++ ++ DWC_WRITE_REG32(&core_if->host_if->host_global_regs->haintmsk, ++ hr->haintmsk_local); ++ for (i = 0; i < dwc_otg_get_param_host_channels(core_if); ++i) { ++ DWC_WRITE_REG32(&core_if->host_if->hc_regs[i]->hcintmsk, ++ hr->hcintmsk_local[i]); ++ } ++ ++ return 0; ++} ++ ++int restore_lpm_i2c_regs(dwc_otg_core_if_t * core_if) ++{ ++ struct dwc_otg_global_regs_backup *gr; ++ ++ gr = core_if->gr_backup; ++ ++ /* Restore values for LPM and I2C */ ++#ifdef CONFIG_USB_DWC_OTG_LPM ++ DWC_WRITE_REG32(&core_if->core_global_regs->glpmcfg, gr->glpmcfg_local); ++#endif ++ DWC_WRITE_REG32(&core_if->core_global_regs->gi2cctl, gr->gi2cctl_local); ++ ++ return 0; ++} ++ ++int restore_essential_regs(dwc_otg_core_if_t * core_if, int rmode, int is_host) ++{ ++ struct dwc_otg_global_regs_backup *gr; ++ pcgcctl_data_t pcgcctl = {.d32 = 0 }; ++ gahbcfg_data_t gahbcfg = {.d32 = 0 }; ++ gusbcfg_data_t gusbcfg = {.d32 = 0 }; ++ gintmsk_data_t gintmsk = {.d32 = 0 }; ++ ++ /* Restore LPM and I2C registers */ ++ restore_lpm_i2c_regs(core_if); ++ ++ /* Set PCGCCTL to 0 */ ++ DWC_WRITE_REG32(core_if->pcgcctl, 0x00000000); ++ ++ gr = core_if->gr_backup; ++ /* Load restore values for [31:14] bits */ ++ DWC_WRITE_REG32(core_if->pcgcctl, ++ ((gr->pcgcctl_local & 0xffffc000) | 0x00020000)); ++ ++ /* Umnask global Interrupt in GAHBCFG and restore it */ ++ gahbcfg.d32 = gr->gahbcfg_local; ++ gahbcfg.b.glblintrmsk = 1; ++ DWC_WRITE_REG32(&core_if->core_global_regs->gahbcfg, gahbcfg.d32); ++ ++ /* Clear all pending interupts */ ++ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF); ++ ++ /* Unmask restore done interrupt */ ++ gintmsk.b.restoredone = 1; ++ DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, gintmsk.d32); ++ ++ /* Restore GUSBCFG and HCFG/DCFG */ ++ gusbcfg.d32 = core_if->gr_backup->gusbcfg_local; ++ DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, gusbcfg.d32); ++ ++ if (is_host) { ++ hcfg_data_t hcfg = {.d32 = 0 }; ++ hcfg.d32 = core_if->hr_backup->hcfg_local; ++ DWC_WRITE_REG32(&core_if->host_if->host_global_regs->hcfg, ++ hcfg.d32); ++ ++ /* Load restore values for [31:14] bits */ ++ pcgcctl.d32 = gr->pcgcctl_local & 0xffffc000; ++ pcgcctl.d32 = gr->pcgcctl_local | 0x00020000; ++ ++ if (rmode) ++ pcgcctl.b.restoremode = 1; ++ DWC_WRITE_REG32(core_if->pcgcctl, pcgcctl.d32); ++ dwc_udelay(10); ++ ++ /* Load restore values for [31:14] bits and set EssRegRestored bit */ ++ pcgcctl.d32 = gr->pcgcctl_local | 0xffffc000; ++ pcgcctl.d32 = gr->pcgcctl_local & 0xffffc000; ++ pcgcctl.b.ess_reg_restored = 1; ++ if (rmode) ++ pcgcctl.b.restoremode = 1; ++ DWC_WRITE_REG32(core_if->pcgcctl, pcgcctl.d32); ++ } else { ++ dcfg_data_t dcfg = {.d32 = 0 }; ++ dcfg.d32 = core_if->dr_backup->dcfg; ++ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dcfg, dcfg.d32); ++ ++ /* Load restore values for [31:14] bits */ ++ pcgcctl.d32 = gr->pcgcctl_local & 0xffffc000; ++ pcgcctl.d32 = gr->pcgcctl_local | 0x00020000; ++ if (!rmode) { ++ pcgcctl.d32 |= 0x208; ++ } ++ DWC_WRITE_REG32(core_if->pcgcctl, pcgcctl.d32); ++ dwc_udelay(10); ++ ++ /* Load restore values for [31:14] bits */ ++ pcgcctl.d32 = gr->pcgcctl_local & 0xffffc000; ++ pcgcctl.d32 = gr->pcgcctl_local | 0x00020000; ++ pcgcctl.b.ess_reg_restored = 1; ++ if (!rmode) ++ pcgcctl.d32 |= 0x208; ++ DWC_WRITE_REG32(core_if->pcgcctl, pcgcctl.d32); ++ } ++ ++ return 0; + } + + /** +@@ -374,9 +1105,9 @@ + } + + DWC_DEBUGPL(DBG_CIL, "Initializing HCFG.FSLSPClkSel to 0x%1x\n", val); +- hcfg.d32 = dwc_read_reg32(&core_if->host_if->host_global_regs->hcfg); ++ hcfg.d32 = DWC_READ_REG32(&core_if->host_if->host_global_regs->hcfg); + hcfg.b.fslspclksel = val; +- dwc_write_reg32(&core_if->host_if->host_global_regs->hcfg, hcfg.d32); ++ DWC_WRITE_REG32(&core_if->host_if->host_global_regs->hcfg, hcfg.d32); + } + + /** +@@ -404,14 +1135,14 @@ + + DWC_DEBUGPL(DBG_CIL, "Initializing DCFG.DevSpd to 0x%1x\n", val); + +- dcfg.d32 = dwc_read_reg32(&core_if->dev_if->dev_global_regs->dcfg); ++ dcfg.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg); + dcfg.b.devspd = val; +- dwc_write_reg32(&core_if->dev_if->dev_global_regs->dcfg, dcfg.d32); ++ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dcfg, dcfg.d32); + } + + /** + * This function calculates the number of IN EPS +- * using GHWCFG1 and GHWCFG2 registers values ++ * using GHWCFG1 and GHWCFG2 registers values + * + * @param core_if Programming view of the DWC_otg controller + */ +@@ -440,7 +1171,7 @@ + + /** + * This function calculates the number of OUT EPS +- * using GHWCFG1 and GHWCFG2 registers values ++ * using GHWCFG1 and GHWCFG2 registers values + * + * @param core_if Programming view of the DWC_otg controller + */ +@@ -480,8 +1211,7 @@ + core_if, global_regs); + + /* Common Initialization */ +- +- usbcfg.d32 = dwc_read_reg32(&global_regs->gusbcfg); ++ usbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg); + + /* Program the ULPI External VBUS bit if needed */ + usbcfg.b.ulpi_ext_vbus_drv = +@@ -491,11 +1221,15 @@ + /* Set external TS Dline pulsing */ + usbcfg.b.term_sel_dl_pulse = + (core_if->core_params->ts_dline == 1) ? 1 : 0; +- dwc_write_reg32(&global_regs->gusbcfg, usbcfg.d32); ++ DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32); + + /* Reset the Controller */ + dwc_otg_core_reset(core_if); + ++ core_if->adp_enable = core_if->core_params->adp_supp_enable; ++ core_if->power_down = core_if->core_params->power_down; ++ core_if->otg_sts = 0; ++ + /* Initialize parameters from Hardware configuration registers. */ + dev_if->num_in_eps = calc_num_in_eps(core_if); + dev_if->num_out_eps = calc_num_out_eps(core_if); +@@ -505,22 +1239,22 @@ + + for (i = 0; i < core_if->hwcfg4.b.num_dev_perio_in_ep; i++) { + dev_if->perio_tx_fifo_size[i] = +- dwc_read_reg32(&global_regs->dptxfsiz_dieptxf[i]) >> 16; ++ DWC_READ_REG32(&global_regs->dtxfsiz[i]) >> 16; + DWC_DEBUGPL(DBG_CIL, "Periodic Tx FIFO SZ #%d=0x%0x\n", + i, dev_if->perio_tx_fifo_size[i]); + } + + for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) { + dev_if->tx_fifo_size[i] = +- dwc_read_reg32(&global_regs->dptxfsiz_dieptxf[i]) >> 16; ++ DWC_READ_REG32(&global_regs->dtxfsiz[i]) >> 16; + DWC_DEBUGPL(DBG_CIL, "Tx FIFO SZ #%d=0x%0x\n", +- i, dev_if->perio_tx_fifo_size[i]); ++ i, dev_if->tx_fifo_size[i]); + } + + core_if->total_fifo_size = core_if->hwcfg3.b.dfifo_depth; +- core_if->rx_fifo_size = dwc_read_reg32(&global_regs->grxfsiz); ++ core_if->rx_fifo_size = DWC_READ_REG32(&global_regs->grxfsiz); + core_if->nperio_tx_fifo_size = +- dwc_read_reg32(&global_regs->gnptxfsiz) >> 16; ++ DWC_READ_REG32(&global_regs->gnptxfsiz) >> 16; + + DWC_DEBUGPL(DBG_CIL, "Total FIFO SZ=%d\n", core_if->total_fifo_size); + DWC_DEBUGPL(DBG_CIL, "Rx FIFO SZ=%d\n", core_if->rx_fifo_size); +@@ -538,9 +1272,9 @@ + if (!core_if->phy_init_done) { + core_if->phy_init_done = 1; + DWC_DEBUGPL(DBG_CIL, "FS_PHY detected\n"); +- usbcfg.d32 = dwc_read_reg32(&global_regs->gusbcfg); ++ usbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg); + usbcfg.b.physel = 1; +- dwc_write_reg32(&global_regs->gusbcfg, usbcfg.d32); ++ DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32); + + /* Reset after a PHY select */ + dwc_otg_core_reset(core_if); +@@ -558,17 +1292,17 @@ + if (core_if->core_params->i2c_enable) { + DWC_DEBUGPL(DBG_CIL, "FS_PHY Enabling I2c\n"); + /* Program GUSBCFG.OtgUtmifsSel to I2C */ +- usbcfg.d32 = dwc_read_reg32(&global_regs->gusbcfg); ++ usbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg); + usbcfg.b.otgutmifssel = 1; +- dwc_write_reg32(&global_regs->gusbcfg, usbcfg.d32); ++ DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32); + + /* Program GI2CCTL.I2CEn */ +- i2cctl.d32 = dwc_read_reg32(&global_regs->gi2cctl); ++ i2cctl.d32 = DWC_READ_REG32(&global_regs->gi2cctl); + i2cctl.b.i2cdevaddr = 1; + i2cctl.b.i2cen = 0; +- dwc_write_reg32(&global_regs->gi2cctl, i2cctl.d32); ++ DWC_WRITE_REG32(&global_regs->gi2cctl, i2cctl.d32); + i2cctl.b.i2cen = 1; +- dwc_write_reg32(&global_regs->gi2cctl, i2cctl.d32); ++ DWC_WRITE_REG32(&global_regs->gi2cctl, i2cctl.d32); + } + + } /* endif speed == DWC_SPEED_PARAM_FULL */ +@@ -579,24 +1313,26 @@ + /* HS PHY parameters. These parameters are preserved + * during soft reset so only program the first time. Do + * a soft reset immediately after setting phyif. */ +- usbcfg.b.ulpi_utmi_sel = core_if->core_params->phy_type; +- if (usbcfg.b.ulpi_utmi_sel == 1) { ++ ++ if (core_if->core_params->phy_type == 2) { + /* ULPI interface */ ++ usbcfg.b.ulpi_utmi_sel = 1; + usbcfg.b.phyif = 0; + usbcfg.b.ddrsel = + core_if->core_params->phy_ulpi_ddr; +- } else { ++ } else if (core_if->core_params->phy_type == 1) { + /* UTMI+ interface */ ++ usbcfg.b.ulpi_utmi_sel = 0; + if (core_if->core_params->phy_utmi_width == 16) { + usbcfg.b.phyif = 1; + + } else { + usbcfg.b.phyif = 0; + } +- ++ } else { ++ DWC_ERROR("FS PHY TYPE\n"); + } +- +- dwc_write_reg32(&global_regs->gusbcfg, usbcfg.d32); ++ DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32); + /* Reset after setting the PHY parameters */ + dwc_otg_core_reset(core_if); + } +@@ -606,15 +1342,15 @@ + (core_if->hwcfg2.b.fs_phy_type == 1) && + (core_if->core_params->ulpi_fs_ls)) { + DWC_DEBUGPL(DBG_CIL, "Setting ULPI FSLS\n"); +- usbcfg.d32 = dwc_read_reg32(&global_regs->gusbcfg); ++ usbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg); + usbcfg.b.ulpi_fsls = 1; + usbcfg.b.ulpi_clk_sus_m = 1; +- dwc_write_reg32(&global_regs->gusbcfg, usbcfg.d32); ++ DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32); + } else { +- usbcfg.d32 = dwc_read_reg32(&global_regs->gusbcfg); ++ usbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg); + usbcfg.b.ulpi_fsls = 0; + usbcfg.b.ulpi_clk_sus_m = 0; +- dwc_write_reg32(&global_regs->gusbcfg, usbcfg.d32); ++ DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32); + } + + /* Program the GAHBCFG Register. */ +@@ -646,8 +1382,10 @@ + + case DWC_INT_DMA_ARCH: + DWC_DEBUGPL(DBG_CIL, "Internal DMA Mode\n"); +- /*ahbcfg.b.hburstlen = DWC_GAHBCFG_INT_DMA_BURST_INCR; */ +- ahbcfg.b.hburstlen = (1<<3)|(0<<0); /* WRESP=1, max 4 beats */ ++ /* Old value was DWC_GAHBCFG_INT_DMA_BURST_INCR - done for ++ Host mode ISOC in issue fix - vahrama */ ++ /* Broadcom had altered to (1<<3)|(0<<0) - WRESP=1, max 4 beats */ ++ ahbcfg.b.hburstlen = (1<<3)|(0<<0);//DWC_GAHBCFG_INT_DMA_BURST_INCR4; + core_if->dma_enable = (core_if->core_params->dma_enable != 0); + core_if->dma_desc_enable = + (core_if->core_params->dma_desc_enable != 0); +@@ -665,9 +1403,13 @@ + DWC_PRINTF("Using Slave mode\n"); + core_if->dma_desc_enable = 0; + } ++ ++ if (core_if->core_params->ahb_single) { ++ ahbcfg.b.ahbsingle = 1; ++ } + + ahbcfg.b.dmaenable = core_if->dma_enable; +- dwc_write_reg32(&global_regs->gahbcfg, ahbcfg.d32); ++ DWC_WRITE_REG32(&global_regs->gahbcfg, ahbcfg.d32); + + core_if->en_multiple_tx_fifo = core_if->hwcfg4.b.ded_fifo_en; + +@@ -678,10 +1420,10 @@ + DWC_PRINTF("Multiprocessor Interrupt Enhancement - %s\n", + ((core_if->multiproc_int_enable) ? "enabled" : "disabled")); + +- /* +- * Program the GUSBCFG register. ++ /* ++ * Program the GUSBCFG register. + */ +- usbcfg.d32 = dwc_read_reg32(&global_regs->gusbcfg); ++ usbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg); + + switch (core_if->hwcfg2.b.op_mode) { + case DWC_MODE_HNP_SRP_CAPABLE: +@@ -725,7 +1467,7 @@ + break; + } + +- dwc_write_reg32(&global_regs->gusbcfg, usbcfg.d32); ++ DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32); + + #ifdef CONFIG_USB_DWC_OTG_LPM + if (core_if->core_params->lpm_enable) { +@@ -740,7 +1482,7 @@ + /* Retry 3 times */ + lpmcfg.b.retry_count = 3; + +- dwc_modify_reg32(&core_if->core_global_regs->glpmcfg, ++ DWC_MODIFY_REG32(&core_if->core_global_regs->glpmcfg, + 0, lpmcfg.d32); + + } +@@ -748,9 +1490,20 @@ + if (core_if->core_params->ic_usb_cap) { + gusbcfg_data_t gusbcfg = {.d32 = 0 }; + gusbcfg.b.ic_usb_cap = 1; +- dwc_modify_reg32(&core_if->core_global_regs->gusbcfg, ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gusbcfg, + 0, gusbcfg.d32); + } ++ { ++ gotgctl_data_t gotgctl = {.d32 = 0 }; ++ gotgctl.b.otgver = core_if->core_params->otg_ver; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gotgctl, 0, ++ gotgctl.d32); ++ /* Set OTG version supported */ ++ core_if->otg_ver = core_if->core_params->otg_ver; ++ DWC_PRINTF("OTG VER PARAM: %d, OTG VER FLAG: %d\n", ++ core_if->core_params->otg_ver, core_if->otg_ver); ++ } ++ + + /* Enable common interrupts */ + dwc_otg_enable_common_interrupts(core_if); +@@ -769,7 +1522,7 @@ + } + } + +-/** ++/** + * This function enables the Device mode interrupts. + * + * @param core_if Programming view of DWC_otg controller +@@ -782,10 +1535,10 @@ + DWC_DEBUGPL(DBG_CIL, "%s()\n", __func__); + + /* Disable all interrupts. */ +- dwc_write_reg32(&global_regs->gintmsk, 0); ++ DWC_WRITE_REG32(&global_regs->gintmsk, 0); + + /* Clear any pending interrupts */ +- dwc_write_reg32(&global_regs->gintsts, 0xFFFFFFFF); ++ DWC_WRITE_REG32(&global_regs->gintsts, 0xFFFFFFFF); + + /* Enable the common interrupts */ + dwc_otg_enable_common_interrupts(core_if); +@@ -793,6 +1546,8 @@ + /* Enable interrupts */ + intr_mask.b.usbreset = 1; + intr_mask.b.enumdone = 1; ++ /* Disable Disconnect interrupt in Device mode */ ++ intr_mask.b.disconnect = 0; + + if (!core_if->multiproc_int_enable) { + intr_mask.b.inepintr = 1; +@@ -804,15 +1559,36 @@ + if (core_if->en_multiple_tx_fifo == 0) { + intr_mask.b.epmismatch = 1; + } ++ ++ //intr_mask.b.incomplisoout = 1; ++ intr_mask.b.incomplisoin = 1; ++ ++/* Enable the ignore frame number for ISOC xfers - MAS */ ++/* Disable to support high bandwith ISOC transfers - manukz */ ++#if 0 ++#ifdef DWC_UTE_PER_IO ++ if (core_if->dma_enable) { ++ if (core_if->dma_desc_enable) { ++ dctl_data_t dctl1 = {.d32 = 0 }; ++ dctl1.b.ifrmnum = 1; ++ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs-> ++ dctl, 0, dctl1.d32); ++ DWC_DEBUG("----Enabled Ignore frame number (0x%08x)", ++ DWC_READ_REG32(&core_if->dev_if-> ++ dev_global_regs->dctl)); ++ } ++ } ++#endif ++#endif + #ifdef DWC_EN_ISOC + if (core_if->dma_enable) { + if (core_if->dma_desc_enable == 0) { + if (core_if->pti_enh_enable) { + dctl_data_t dctl = {.d32 = 0 }; + dctl.b.ifrmnum = 1; +- dwc_modify_reg32(&core_if->dev_if-> +- dev_global_regs->dctl, 0, +- dctl.d32); ++ DWC_MODIFY_REG32(&core_if-> ++ dev_if->dev_global_regs->dctl, ++ 0, dctl.d32); + } else { + intr_mask.b.incomplisoin = 1; + intr_mask.b.incomplisoout = 1; +@@ -822,7 +1598,7 @@ + intr_mask.b.incomplisoin = 1; + intr_mask.b.incomplisoout = 1; + } +-#endif /* DWC_EN_ISOC */ ++#endif /* DWC_EN_ISOC */ + + /** @todo NGS: Should this be a module parameter? */ + #ifdef USE_PERIODIC_EP +@@ -832,16 +1608,16 @@ + intr_mask.b.incomplisoout = 1; + #endif + +- dwc_modify_reg32(&global_regs->gintmsk, intr_mask.d32, intr_mask.d32); ++ DWC_MODIFY_REG32(&global_regs->gintmsk, intr_mask.d32, intr_mask.d32); + + DWC_DEBUGPL(DBG_CIL, "%s() gintmsk=%0x\n", __func__, +- dwc_read_reg32(&global_regs->gintmsk)); ++ DWC_READ_REG32(&global_regs->gintmsk)); + } + + /** + * This function initializes the DWC_otg controller registers for + * device mode. +- * ++ * + * @param core_if Programming view of DWC_otg controller + * + */ +@@ -852,23 +1628,38 @@ + dwc_otg_dev_if_t *dev_if = core_if->dev_if; + dwc_otg_core_params_t *params = core_if->core_params; + dcfg_data_t dcfg = {.d32 = 0 }; ++ depctl_data_t diepctl = {.d32 = 0 }; + grstctl_t resetctl = {.d32 = 0 }; + uint32_t rx_fifo_size; + fifosize_data_t nptxfifosize; + fifosize_data_t txfifosize; + dthrctl_data_t dthrctl; + fifosize_data_t ptxfifosize; ++ uint16_t rxfsiz, nptxfsiz; ++ gdfifocfg_data_t gdfifocfg = {.d32 = 0 }; ++ hwcfg3_data_t hwcfg3 = {.d32 = 0 }; + + /* Restart the Phy Clock */ +- dwc_write_reg32(core_if->pcgcctl, 0); ++ DWC_WRITE_REG32(core_if->pcgcctl, 0); + + /* Device configuration register */ + init_devspd(core_if); +- dcfg.d32 = dwc_read_reg32(&dev_if->dev_global_regs->dcfg); ++ dcfg.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->dcfg); + dcfg.b.descdma = (core_if->dma_desc_enable) ? 1 : 0; + dcfg.b.perfrint = DWC_DCFG_FRAME_INTERVAL_80; ++ /* Enable Device OUT NAK in case of DDMA mode*/ ++ if (core_if->core_params->dev_out_nak) { ++ dcfg.b.endevoutnak = 1; ++ } ++ ++ if (core_if->core_params->cont_on_bna) { ++ dctl_data_t dctl = {.d32 = 0 }; ++ dctl.b.encontonbna = 1; ++ DWC_MODIFY_REG32(&dev_if->dev_global_regs->dctl, 0, dctl.d32); ++ } ++ + +- dwc_write_reg32(&dev_if->dev_global_regs->dcfg, dcfg.d32); ++ DWC_WRITE_REG32(&dev_if->dev_global_regs->dcfg, dcfg.d32); + + /* Configure data FIFO sizes */ + if (core_if->hwcfg2.b.dynamic_fifo && params->enable_dynamic_fifo) { +@@ -881,17 +1672,17 @@ + + /* Rx FIFO */ + DWC_DEBUGPL(DBG_CIL, "initial grxfsiz=%08x\n", +- dwc_read_reg32(&global_regs->grxfsiz)); ++ DWC_READ_REG32(&global_regs->grxfsiz)); + + #ifdef DWC_UTE_CFI +- core_if->pwron_rxfsiz = dwc_read_reg32(&global_regs->grxfsiz); ++ core_if->pwron_rxfsiz = DWC_READ_REG32(&global_regs->grxfsiz); + core_if->init_rxfsiz = params->dev_rx_fifo_size; + #endif + rx_fifo_size = params->dev_rx_fifo_size; +- dwc_write_reg32(&global_regs->grxfsiz, rx_fifo_size); ++ DWC_WRITE_REG32(&global_regs->grxfsiz, rx_fifo_size); + + DWC_DEBUGPL(DBG_CIL, "new grxfsiz=%08x\n", +- dwc_read_reg32(&global_regs->grxfsiz)); ++ DWC_READ_REG32(&global_regs->grxfsiz)); + + /** Set Periodic Tx FIFO Mask all bits 0 */ + core_if->p_tx_msk = 0; +@@ -902,16 +1693,16 @@ + if (core_if->en_multiple_tx_fifo == 0) { + /* Non-periodic Tx FIFO */ + DWC_DEBUGPL(DBG_CIL, "initial gnptxfsiz=%08x\n", +- dwc_read_reg32(&global_regs->gnptxfsiz)); ++ DWC_READ_REG32(&global_regs->gnptxfsiz)); + + nptxfifosize.b.depth = params->dev_nperio_tx_fifo_size; + nptxfifosize.b.startaddr = params->dev_rx_fifo_size; + +- dwc_write_reg32(&global_regs->gnptxfsiz, ++ DWC_WRITE_REG32(&global_regs->gnptxfsiz, + nptxfifosize.d32); + + DWC_DEBUGPL(DBG_CIL, "new gnptxfsiz=%08x\n", +- dwc_read_reg32(&global_regs->gnptxfsiz)); ++ DWC_READ_REG32(&global_regs->gnptxfsiz)); + + /**@todo NGS: Fix Periodic FIFO Sizing! */ + /* +@@ -923,24 +1714,18 @@ + /** @todo Finish debug of this */ + ptxfifosize.b.startaddr = + nptxfifosize.b.startaddr + nptxfifosize.b.depth; +- for (i = 0; i < core_if->hwcfg4.b.num_dev_perio_in_ep; +- i++) { ++ for (i = 0; i < core_if->hwcfg4.b.num_dev_perio_in_ep; i++) { + ptxfifosize.b.depth = + params->dev_perio_tx_fifo_size[i]; + DWC_DEBUGPL(DBG_CIL, +- "initial dptxfsiz_dieptxf[%d]=%08x\n", +- i, +- dwc_read_reg32(&global_regs-> +- dptxfsiz_dieptxf ++ "initial dtxfsiz[%d]=%08x\n", i, ++ DWC_READ_REG32(&global_regs->dtxfsiz + [i])); +- dwc_write_reg32(&global_regs-> +- dptxfsiz_dieptxf[i], ++ DWC_WRITE_REG32(&global_regs->dtxfsiz[i], + ptxfifosize.d32); +- DWC_DEBUGPL(DBG_CIL, +- "new dptxfsiz_dieptxf[%d]=%08x\n", ++ DWC_DEBUGPL(DBG_CIL, "new dtxfsiz[%d]=%08x\n", + i, +- dwc_read_reg32(&global_regs-> +- dptxfsiz_dieptxf ++ DWC_READ_REG32(&global_regs->dtxfsiz + [i])); + ptxfifosize.b.startaddr += ptxfifosize.b.depth; + } +@@ -949,27 +1734,27 @@ + * Tx FIFOs These FIFOs are numbered from 1 to 15. + * Indexes of the FIFO size module parameters in the + * dev_tx_fifo_size array and the FIFO size registers in +- * the dptxfsiz_dieptxf array run from 0 to 14. ++ * the dtxfsiz array run from 0 to 14. + */ + + /* Non-periodic Tx FIFO */ + DWC_DEBUGPL(DBG_CIL, "initial gnptxfsiz=%08x\n", +- dwc_read_reg32(&global_regs->gnptxfsiz)); ++ DWC_READ_REG32(&global_regs->gnptxfsiz)); + + #ifdef DWC_UTE_CFI + core_if->pwron_gnptxfsiz = +- (dwc_read_reg32(&global_regs->gnptxfsiz) >> 16); ++ (DWC_READ_REG32(&global_regs->gnptxfsiz) >> 16); + core_if->init_gnptxfsiz = + params->dev_nperio_tx_fifo_size; + #endif + nptxfifosize.b.depth = params->dev_nperio_tx_fifo_size; + nptxfifosize.b.startaddr = params->dev_rx_fifo_size; + +- dwc_write_reg32(&global_regs->gnptxfsiz, ++ DWC_WRITE_REG32(&global_regs->gnptxfsiz, + nptxfifosize.d32); + + DWC_DEBUGPL(DBG_CIL, "new gnptxfsiz=%08x\n", +- dwc_read_reg32(&global_regs->gnptxfsiz)); ++ DWC_READ_REG32(&global_regs->gnptxfsiz)); + + txfifosize.b.startaddr = + nptxfifosize.b.startaddr + nptxfifosize.b.depth; +@@ -980,69 +1765,100 @@ + params->dev_tx_fifo_size[i]; + + DWC_DEBUGPL(DBG_CIL, +- "initial dptxfsiz_dieptxf[%d]=%08x\n", ++ "initial dtxfsiz[%d]=%08x\n", + i, +- dwc_read_reg32(&global_regs-> +- dptxfsiz_dieptxf ++ DWC_READ_REG32(&global_regs->dtxfsiz + [i])); + + #ifdef DWC_UTE_CFI + core_if->pwron_txfsiz[i] = +- (dwc_read_reg32 +- (&global_regs->dptxfsiz_dieptxf[i]) >> 16); ++ (DWC_READ_REG32 ++ (&global_regs->dtxfsiz[i]) >> 16); + core_if->init_txfsiz[i] = + params->dev_tx_fifo_size[i]; + #endif +- dwc_write_reg32(&global_regs-> +- dptxfsiz_dieptxf[i], ++ DWC_WRITE_REG32(&global_regs->dtxfsiz[i], + txfifosize.d32); + + DWC_DEBUGPL(DBG_CIL, +- "new dptxfsiz_dieptxf[%d]=%08x\n", ++ "new dtxfsiz[%d]=%08x\n", + i, +- dwc_read_reg32(&global_regs-> +- dptxfsiz_dieptxf ++ DWC_READ_REG32(&global_regs->dtxfsiz + [i])); + + txfifosize.b.startaddr += txfifosize.b.depth; + } ++ /* Calculating DFIFOCFG for Device mode to include RxFIFO and NPTXFIFO */ ++ gdfifocfg.d32 = DWC_READ_REG32(&global_regs->gdfifocfg); ++ hwcfg3.d32 = DWC_READ_REG32(&global_regs->ghwcfg3); ++ gdfifocfg.b.gdfifocfg = (DWC_READ_REG32(&global_regs->ghwcfg3) >> 16); ++ DWC_WRITE_REG32(&global_regs->gdfifocfg, gdfifocfg.d32); ++ rxfsiz = (DWC_READ_REG32(&global_regs->grxfsiz) & 0x0000ffff); ++ nptxfsiz = (DWC_READ_REG32(&global_regs->gnptxfsiz) >> 16); ++ gdfifocfg.b.epinfobase = rxfsiz + nptxfsiz; ++ DWC_WRITE_REG32(&global_regs->gdfifocfg, gdfifocfg.d32); + } + } ++ + /* Flush the FIFOs */ + dwc_otg_flush_tx_fifo(core_if, 0x10); /* all Tx FIFOs */ + dwc_otg_flush_rx_fifo(core_if); + + /* Flush the Learning Queue. */ + resetctl.b.intknqflsh = 1; +- dwc_write_reg32(&core_if->core_global_regs->grstctl, resetctl.d32); ++ DWC_WRITE_REG32(&core_if->core_global_regs->grstctl, resetctl.d32); + ++ if (!core_if->core_params->en_multiple_tx_fifo && core_if->dma_enable) { ++ core_if->start_predict = 0; ++ for (i = 0; i<= core_if->dev_if->num_in_eps; ++i) { ++ core_if->nextep_seq[i] = 0xff; // 0xff - EP not active ++ } ++ core_if->nextep_seq[0] = 0; ++ core_if->first_in_nextep_seq = 0; ++ diepctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[0]->diepctl); ++ diepctl.b.nextep = 0; ++ DWC_WRITE_REG32(&dev_if->in_ep_regs[0]->diepctl, diepctl.d32); ++ ++ /* Update IN Endpoint Mismatch Count by active IN NP EP count + 1 */ ++ dcfg.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->dcfg); ++ dcfg.b.epmscnt = 2; ++ DWC_WRITE_REG32(&dev_if->dev_global_regs->dcfg, dcfg.d32); ++ ++ DWC_DEBUGPL(DBG_CILV,"%s first_in_nextep_seq= %2d; nextep_seq[]:\n", ++ __func__, core_if->first_in_nextep_seq); ++ for (i=0; i <= core_if->dev_if->num_in_eps; i++) { ++ DWC_DEBUGPL(DBG_CILV, "%2d ", core_if->nextep_seq[i]); ++ } ++ DWC_DEBUGPL(DBG_CILV,"\n"); ++ } ++ + /* Clear all pending Device Interrupts */ +- /** @todo - if the condition needed to be checked +- * or in any case all pending interrutps should be cleared? +- */ ++ /** @todo - if the condition needed to be checked ++ * or in any case all pending interrutps should be cleared? ++ */ + if (core_if->multiproc_int_enable) { + for (i = 0; i < core_if->dev_if->num_in_eps; ++i) { +- dwc_write_reg32(&dev_if->dev_global_regs-> +- diepeachintmsk[i], 0); ++ DWC_WRITE_REG32(&dev_if-> ++ dev_global_regs->diepeachintmsk[i], 0); + } + + for (i = 0; i < core_if->dev_if->num_out_eps; ++i) { +- dwc_write_reg32(&dev_if->dev_global_regs-> +- doepeachintmsk[i], 0); ++ DWC_WRITE_REG32(&dev_if-> ++ dev_global_regs->doepeachintmsk[i], 0); + } + +- dwc_write_reg32(&dev_if->dev_global_regs->deachint, 0xFFFFFFFF); +- dwc_write_reg32(&dev_if->dev_global_regs->deachintmsk, 0); ++ DWC_WRITE_REG32(&dev_if->dev_global_regs->deachint, 0xFFFFFFFF); ++ DWC_WRITE_REG32(&dev_if->dev_global_regs->deachintmsk, 0); + } else { +- dwc_write_reg32(&dev_if->dev_global_regs->diepmsk, 0); +- dwc_write_reg32(&dev_if->dev_global_regs->doepmsk, 0); +- dwc_write_reg32(&dev_if->dev_global_regs->daint, 0xFFFFFFFF); +- dwc_write_reg32(&dev_if->dev_global_regs->daintmsk, 0); ++ DWC_WRITE_REG32(&dev_if->dev_global_regs->diepmsk, 0); ++ DWC_WRITE_REG32(&dev_if->dev_global_regs->doepmsk, 0); ++ DWC_WRITE_REG32(&dev_if->dev_global_regs->daint, 0xFFFFFFFF); ++ DWC_WRITE_REG32(&dev_if->dev_global_regs->daintmsk, 0); + } + + for (i = 0; i <= dev_if->num_in_eps; i++) { + depctl_data_t depctl; +- depctl.d32 = dwc_read_reg32(&dev_if->in_ep_regs[i]->diepctl); ++ depctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl); + if (depctl.b.epena) { + depctl.d32 = 0; + depctl.b.epdis = 1; +@@ -1051,16 +1867,16 @@ + depctl.d32 = 0; + } + +- dwc_write_reg32(&dev_if->in_ep_regs[i]->diepctl, depctl.d32); ++ DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->diepctl, depctl.d32); + +- dwc_write_reg32(&dev_if->in_ep_regs[i]->dieptsiz, 0); +- dwc_write_reg32(&dev_if->in_ep_regs[i]->diepdma, 0); +- dwc_write_reg32(&dev_if->in_ep_regs[i]->diepint, 0xFF); ++ DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->dieptsiz, 0); ++ DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->diepdma, 0); ++ DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->diepint, 0xFF); + } + + for (i = 0; i <= dev_if->num_out_eps; i++) { + depctl_data_t depctl; +- depctl.d32 = dwc_read_reg32(&dev_if->out_ep_regs[i]->doepctl); ++ depctl.d32 = DWC_READ_REG32(&dev_if->out_ep_regs[i]->doepctl); + if (depctl.b.epena) { + depctl.d32 = 0; + depctl.b.epdis = 1; +@@ -1069,11 +1885,11 @@ + depctl.d32 = 0; + } + +- dwc_write_reg32(&dev_if->out_ep_regs[i]->doepctl, depctl.d32); ++ DWC_WRITE_REG32(&dev_if->out_ep_regs[i]->doepctl, depctl.d32); + +- dwc_write_reg32(&dev_if->out_ep_regs[i]->doeptsiz, 0); +- dwc_write_reg32(&dev_if->out_ep_regs[i]->doepdma, 0); +- dwc_write_reg32(&dev_if->out_ep_regs[i]->doepint, 0xFF); ++ DWC_WRITE_REG32(&dev_if->out_ep_regs[i]->doeptsiz, 0); ++ DWC_WRITE_REG32(&dev_if->out_ep_regs[i]->doepdma, 0); ++ DWC_WRITE_REG32(&dev_if->out_ep_regs[i]->doepint, 0xFF); + } + + if (core_if->en_multiple_tx_fifo && core_if->dma_enable) { +@@ -1094,7 +1910,7 @@ + dthrctl.b.rx_thr_len = dev_if->rx_thr_length; + dthrctl.b.ahb_thr_ratio = params->ahb_thr_ratio; + +- dwc_write_reg32(&dev_if->dev_global_regs->dtknqr3_dthrctl, ++ DWC_WRITE_REG32(&dev_if->dev_global_regs->dtknqr3_dthrctl, + dthrctl.d32); + + DWC_DEBUGPL(DBG_CIL, +@@ -1111,10 +1927,11 @@ + diepmsk_data_t msk = {.d32 = 0 }; + msk.b.txfifoundrn = 1; + if (core_if->multiproc_int_enable) { +- dwc_modify_reg32(&dev_if->dev_global_regs-> +- diepeachintmsk[0], msk.d32, msk.d32); ++ DWC_MODIFY_REG32(&dev_if-> ++ dev_global_regs->diepeachintmsk[0], ++ msk.d32, msk.d32); + } else { +- dwc_modify_reg32(&dev_if->dev_global_regs->diepmsk, ++ DWC_MODIFY_REG32(&dev_if->dev_global_regs->diepmsk, + msk.d32, msk.d32); + } + } +@@ -1123,11 +1940,18 @@ + /* Set NAK on Babble */ + dctl_data_t dctl = {.d32 = 0 }; + dctl.b.nakonbble = 1; +- dwc_modify_reg32(&dev_if->dev_global_regs->dctl, 0, dctl.d32); ++ DWC_MODIFY_REG32(&dev_if->dev_global_regs->dctl, 0, dctl.d32); ++ } ++ ++ if (core_if->snpsid >= OTG_CORE_REV_2_94a) { ++ dctl_data_t dctl = {.d32 = 0 }; ++ dctl.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->dctl); ++ dctl.b.sftdiscon = 0; ++ DWC_WRITE_REG32(&dev_if->dev_global_regs->dctl, dctl.d32); + } + } + +-/** ++/** + * This function enables the Host mode interrupts. + * + * @param core_if Programming view of DWC_otg controller +@@ -1140,10 +1964,10 @@ + DWC_DEBUGPL(DBG_CIL, "%s(%p)\n", __func__, core_if); + + /* Disable all interrupts. */ +- dwc_write_reg32(&global_regs->gintmsk, 0); ++ DWC_WRITE_REG32(&global_regs->gintmsk, 0); + + /* Clear any pending interrupts. */ +- dwc_write_reg32(&global_regs->gintsts, 0xFFFFFFFF); ++ DWC_WRITE_REG32(&global_regs->gintsts, 0xFFFFFFFF); + + /* Enable the common interrupts */ + dwc_otg_enable_common_interrupts(core_if); +@@ -1152,17 +1976,15 @@ + * Enable host mode interrupts without disturbing common + * interrupts. + */ +- +- /* Do not need sof interrupt for Descriptor DMA*/ +- if (!core_if->dma_desc_enable) +- intr_mask.b.sofintr = 1; ++ ++ intr_mask.b.disconnect = 1; + intr_mask.b.portintr = 1; + intr_mask.b.hcintr = 1; + +- dwc_modify_reg32(&global_regs->gintmsk, intr_mask.d32, intr_mask.d32); ++ DWC_MODIFY_REG32(&global_regs->gintmsk, intr_mask.d32, intr_mask.d32); + } + +-/** ++/** + * This function disables the Host Mode interrupts. + * + * @param core_if Programming view of DWC_otg controller +@@ -1184,7 +2006,7 @@ + intr_mask.b.ptxfempty = 1; + intr_mask.b.nptxfempty = 1; + +- dwc_modify_reg32(&global_regs->gintmsk, intr_mask.d32, 0); ++ DWC_MODIFY_REG32(&global_regs->gintmsk, intr_mask.d32, 0); + } + + /** +@@ -1206,9 +2028,12 @@ + hprt0_data_t hprt0 = {.d32 = 0 }; + fifosize_data_t nptxfifosize; + fifosize_data_t ptxfifosize; ++ uint16_t rxfsiz, nptxfsiz, hptxfsiz; ++ gdfifocfg_data_t gdfifocfg = {.d32 = 0 }; + int i; + hcchar_data_t hcchar; + hcfg_data_t hcfg; ++ hfir_data_t hfir; + dwc_otg_hc_regs_t *hc_regs; + int num_channels; + gotgctl_data_t gotgctl = {.d32 = 0 }; +@@ -1216,38 +2041,52 @@ + DWC_DEBUGPL(DBG_CILV, "%s(%p)\n", __func__, core_if); + + /* Restart the Phy Clock */ +- dwc_write_reg32(core_if->pcgcctl, 0); ++ DWC_WRITE_REG32(core_if->pcgcctl, 0); + + /* Initialize Host Configuration Register */ + init_fslspclksel(core_if); + if (core_if->core_params->speed == DWC_SPEED_PARAM_FULL) { +- hcfg.d32 = dwc_read_reg32(&host_if->host_global_regs->hcfg); ++ hcfg.d32 = DWC_READ_REG32(&host_if->host_global_regs->hcfg); + hcfg.b.fslssupp = 1; +- dwc_write_reg32(&host_if->host_global_regs->hcfg, hcfg.d32); +- ++ DWC_WRITE_REG32(&host_if->host_global_regs->hcfg, hcfg.d32); ++ ++ } ++ ++ /* This bit allows dynamic reloading of the HFIR register ++ * during runtime. This bit needs to be programmed during ++ * initial configuration and its value must not be changed ++ * during runtime.*/ ++ if (core_if->core_params->reload_ctl == 1) { ++ hfir.d32 = DWC_READ_REG32(&host_if->host_global_regs->hfir); ++ hfir.b.hfirrldctrl = 1; ++ DWC_WRITE_REG32(&host_if->host_global_regs->hfir, hfir.d32); + } + + if (core_if->core_params->dma_desc_enable) { +- uint8_t op_mode = core_if->hwcfg2.b.op_mode; +- if (!(core_if->hwcfg4.b.desc_dma && (core_if->snpsid >= OTG_CORE_REV_2_90a) && +- ((op_mode == DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG) || +- (op_mode == DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG) || +- (op_mode == DWC_HWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE_OTG) || +- (op_mode == DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST) || +- (op_mode == DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST)))) { +- +- DWC_ERROR("Host can't operate in Descriptor DMA mode.\n" +- "Either core version is below 2.90a or " +- "GHWCFG2, GHWCFG4 registers' values do not allow Descriptor DMA in host mode.\n" +- "To run the driver in Buffer DMA host mode set dma_desc_enable " +- "module parameter to 0.\n"); +- return; +- } +- hcfg.d32 = dwc_read_reg32(&host_if->host_global_regs->hcfg); ++ uint8_t op_mode = core_if->hwcfg2.b.op_mode; ++ if (! ++ (core_if->hwcfg4.b.desc_dma ++ && (core_if->snpsid >= OTG_CORE_REV_2_90a) ++ && ((op_mode == DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG) ++ || (op_mode == DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG) ++ || (op_mode == ++ DWC_HWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE_OTG) ++ || (op_mode == DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST) ++ || (op_mode == ++ DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST)))) { ++ ++ DWC_ERROR("Host can't operate in Descriptor DMA mode.\n" ++ "Either core version is below 2.90a or " ++ "GHWCFG2, GHWCFG4 registers' values do not allow Descriptor DMA in host mode.\n" ++ "To run the driver in Buffer DMA host mode set dma_desc_enable " ++ "module parameter to 0.\n"); ++ return; ++ } ++ hcfg.d32 = DWC_READ_REG32(&host_if->host_global_regs->hcfg); + hcfg.b.descdma = 1; +- dwc_write_reg32(&host_if->host_global_regs->hcfg, hcfg.d32); ++ DWC_WRITE_REG32(&host_if->host_global_regs->hcfg, hcfg.d32); + } +- ++ + /* Configure data FIFO sizes */ + if (core_if->hwcfg2.b.dynamic_fifo && params->enable_dynamic_fifo) { + DWC_DEBUGPL(DBG_CIL, "Total FIFO Size=%d\n", +@@ -1261,65 +2100,79 @@ + + /* Rx FIFO */ + DWC_DEBUGPL(DBG_CIL, "initial grxfsiz=%08x\n", +- dwc_read_reg32(&global_regs->grxfsiz)); +- dwc_write_reg32(&global_regs->grxfsiz, ++ DWC_READ_REG32(&global_regs->grxfsiz)); ++ DWC_WRITE_REG32(&global_regs->grxfsiz, + params->host_rx_fifo_size); + DWC_DEBUGPL(DBG_CIL, "new grxfsiz=%08x\n", +- dwc_read_reg32(&global_regs->grxfsiz)); ++ DWC_READ_REG32(&global_regs->grxfsiz)); + + /* Non-periodic Tx FIFO */ + DWC_DEBUGPL(DBG_CIL, "initial gnptxfsiz=%08x\n", +- dwc_read_reg32(&global_regs->gnptxfsiz)); ++ DWC_READ_REG32(&global_regs->gnptxfsiz)); + nptxfifosize.b.depth = params->host_nperio_tx_fifo_size; + nptxfifosize.b.startaddr = params->host_rx_fifo_size; +- dwc_write_reg32(&global_regs->gnptxfsiz, nptxfifosize.d32); ++ DWC_WRITE_REG32(&global_regs->gnptxfsiz, nptxfifosize.d32); + DWC_DEBUGPL(DBG_CIL, "new gnptxfsiz=%08x\n", +- dwc_read_reg32(&global_regs->gnptxfsiz)); ++ DWC_READ_REG32(&global_regs->gnptxfsiz)); + + /* Periodic Tx FIFO */ + DWC_DEBUGPL(DBG_CIL, "initial hptxfsiz=%08x\n", +- dwc_read_reg32(&global_regs->hptxfsiz)); ++ DWC_READ_REG32(&global_regs->hptxfsiz)); + ptxfifosize.b.depth = params->host_perio_tx_fifo_size; + ptxfifosize.b.startaddr = + nptxfifosize.b.startaddr + nptxfifosize.b.depth; +- dwc_write_reg32(&global_regs->hptxfsiz, ptxfifosize.d32); ++ DWC_WRITE_REG32(&global_regs->hptxfsiz, ptxfifosize.d32); + DWC_DEBUGPL(DBG_CIL, "new hptxfsiz=%08x\n", +- dwc_read_reg32(&global_regs->hptxfsiz)); ++ DWC_READ_REG32(&global_regs->hptxfsiz)); ++ ++ if (core_if->en_multiple_tx_fifo) { ++ /* Global DFIFOCFG calculation for Host mode - include RxFIFO, NPTXFIFO and HPTXFIFO */ ++ gdfifocfg.d32 = DWC_READ_REG32(&global_regs->gdfifocfg); ++ rxfsiz = (DWC_READ_REG32(&global_regs->grxfsiz) & 0x0000ffff); ++ nptxfsiz = (DWC_READ_REG32(&global_regs->gnptxfsiz) >> 16); ++ hptxfsiz = (DWC_READ_REG32(&global_regs->hptxfsiz) >> 16); ++ gdfifocfg.b.epinfobase = rxfsiz + nptxfsiz + hptxfsiz; ++ DWC_WRITE_REG32(&global_regs->gdfifocfg, gdfifocfg.d32); ++ } + } + ++ /* TODO - check this */ + /* Clear Host Set HNP Enable in the OTG Control Register */ + gotgctl.b.hstsethnpen = 1; +- dwc_modify_reg32(&global_regs->gotgctl, gotgctl.d32, 0); +- ++ DWC_MODIFY_REG32(&global_regs->gotgctl, gotgctl.d32, 0); + /* Make sure the FIFOs are flushed. */ +- dwc_otg_flush_tx_fifo(core_if, 0x10 /* all Tx FIFOs */ ); ++ dwc_otg_flush_tx_fifo(core_if, 0x10 /* all TX FIFOs */ ); + dwc_otg_flush_rx_fifo(core_if); + +- if(!core_if->core_params->dma_desc_enable) { ++ /* Clear Host Set HNP Enable in the OTG Control Register */ ++ gotgctl.b.hstsethnpen = 1; ++ DWC_MODIFY_REG32(&global_regs->gotgctl, gotgctl.d32, 0); ++ ++ if (!core_if->core_params->dma_desc_enable) { + /* Flush out any leftover queued requests. */ + num_channels = core_if->core_params->host_channels; +- ++ + for (i = 0; i < num_channels; i++) { + hc_regs = core_if->host_if->hc_regs[i]; +- hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); ++ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar); + hcchar.b.chen = 0; + hcchar.b.chdis = 1; + hcchar.b.epdir = 0; +- dwc_write_reg32(&hc_regs->hcchar, hcchar.d32); ++ DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32); + } + + /* Halt all channels to put them into a known state. */ + for (i = 0; i < num_channels; i++) { + int count = 0; + hc_regs = core_if->host_if->hc_regs[i]; +- hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); ++ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar); + hcchar.b.chen = 1; + hcchar.b.chdis = 1; + hcchar.b.epdir = 0; +- dwc_write_reg32(&hc_regs->hcchar, hcchar.d32); ++ DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32); + DWC_DEBUGPL(DBG_HCDV, "%s: Halt channel %d regs %p\n", __func__, i, hc_regs); + do { +- hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); ++ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar); + if (++count > 1000) { + DWC_ERROR + ("%s: Unable to clear halt on channel %d (timeout HCCHAR 0x%X @%p)\n", +@@ -1330,7 +2183,7 @@ + } while (hcchar.b.chen); + } + } +- ++ + /* Turn on the vbus power. */ + DWC_PRINTF("Init: Port Power? op_state=%d\n", core_if->op_state); + if (core_if->op_state == A_HOST) { +@@ -1338,7 +2191,7 @@ + DWC_PRINTF("Init: Power Port (%d)\n", hprt0.b.prtpwr); + if (hprt0.b.prtpwr == 0) { + hprt0.b.prtpwr = 1; +- dwc_write_reg32(host_if->hprt0, hprt0.d32); ++ DWC_WRITE_REG32(host_if->hprt0, hprt0.d32); + } + } + +@@ -1369,7 +2222,7 @@ + /* Clear old interrupt conditions for this host channel. */ + hc_intr_mask.d32 = 0xFFFFFFFF; + hc_intr_mask.b.reserved14_31 = 0; +- dwc_write_reg32(&hc_regs->hcint, hc_intr_mask.d32); ++ DWC_WRITE_REG32(&hc_regs->hcint, hc_intr_mask.d32); + + /* Enable channel interrupts required for this transfer. */ + hc_intr_mask.d32 = 0; +@@ -1379,10 +2232,10 @@ + if (!core_if->dma_desc_enable) + hc_intr_mask.b.ahberr = 1; + else { +- if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC) ++ if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC) + hc_intr_mask.b.xfercompl = 1; + } +- ++ + if (hc->error_state && !hc->do_split && + hc->ep_type != DWC_OTG_EP_TYPE_ISOC) { + hc_intr_mask.b.ack = 1; +@@ -1458,15 +2311,15 @@ + break; + } + } +- dwc_write_reg32(&hc_regs->hcintmsk, hc_intr_mask.d32); ++ DWC_WRITE_REG32(&hc_regs->hcintmsk, hc_intr_mask.d32); + + /* Enable the top level host channel interrupt. */ + intr_enable = (1 << hc_num); +- dwc_modify_reg32(&host_if->host_global_regs->haintmsk, 0, intr_enable); ++ DWC_MODIFY_REG32(&host_if->host_global_regs->haintmsk, 0, intr_enable); + + /* Make sure host channel interrupts are enabled. */ + gintmsk.b.hcintr = 1; +- dwc_modify_reg32(&core_if->core_global_regs->gintmsk, 0, gintmsk.d32); ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, 0, gintmsk.d32); + + /* + * Program the HCCHARn register with the endpoint characteristics for +@@ -1480,16 +2333,14 @@ + hcchar.b.eptype = hc->ep_type; + hcchar.b.mps = hc->max_packet; + +- dwc_write_reg32(&host_if->hc_regs[hc_num]->hcchar, hcchar.d32); ++ DWC_WRITE_REG32(&host_if->hc_regs[hc_num]->hcchar, hcchar.d32); + +- DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num); +- DWC_DEBUGPL(DBG_HCDV, " Dev Addr: %d\n", hcchar.b.devaddr); +- DWC_DEBUGPL(DBG_HCDV, " Ep Num: %d\n", hcchar.b.epnum); +- DWC_DEBUGPL(DBG_HCDV, " Is In: %d\n", hcchar.b.epdir); +- DWC_DEBUGPL(DBG_HCDV, " Is Low Speed: %d\n", hcchar.b.lspddev); +- DWC_DEBUGPL(DBG_HCDV, " Ep Type: %d\n", hcchar.b.eptype); +- DWC_DEBUGPL(DBG_HCDV, " Max Pkt: %d\n", hcchar.b.mps); +- DWC_DEBUGPL(DBG_HCDV, " Multi Cnt: %d\n", hcchar.b.multicnt); ++ DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d, Dev Addr %d, EP #%d\n", ++ __func__, hc->hc_num, hcchar.b.devaddr, hcchar.b.epnum); ++ DWC_DEBUGPL(DBG_HCDV, " Is In %d, Is Low Speed %d, EP Type %d, " ++ "Max Pkt %d, Multi Cnt %d\n", ++ hcchar.b.epdir, hcchar.b.lspddev, hcchar.b.eptype, ++ hcchar.b.mps, hcchar.b.multicnt); + + /* + * Program the HCSPLIT register for SPLITs +@@ -1503,15 +2354,15 @@ + hcsplt.b.xactpos = hc->xact_pos; + hcsplt.b.hubaddr = hc->hub_addr; + hcsplt.b.prtaddr = hc->port_addr; +- DWC_DEBUGPL(DBG_HCDV, " comp split %d\n", hc->complete_split); +- DWC_DEBUGPL(DBG_HCDV, " xact pos %d\n", hc->xact_pos); +- DWC_DEBUGPL(DBG_HCDV, " hub addr %d\n", hc->hub_addr); +- DWC_DEBUGPL(DBG_HCDV, " port addr %d\n", hc->port_addr); +- DWC_DEBUGPL(DBG_HCDV, " is_in %d\n", hc->ep_is_in); +- DWC_DEBUGPL(DBG_HCDV, " Max Pkt: %d\n", hcchar.b.mps); +- DWC_DEBUGPL(DBG_HCDV, " xferlen: %d\n", hc->xfer_len); ++ DWC_DEBUGPL(DBG_HCDV, "\t comp split %d\n", hc->complete_split); ++ DWC_DEBUGPL(DBG_HCDV, "\t xact pos %d\n", hc->xact_pos); ++ DWC_DEBUGPL(DBG_HCDV, "\t hub addr %d\n", hc->hub_addr); ++ DWC_DEBUGPL(DBG_HCDV, "\t port addr %d\n", hc->port_addr); ++ DWC_DEBUGPL(DBG_HCDV, "\t is_in %d\n", hc->ep_is_in); ++ DWC_DEBUGPL(DBG_HCDV, "\t Max Pkt: %d\n", hcchar.b.mps); ++ DWC_DEBUGPL(DBG_HCDV, "\t xferlen: %d\n", hc->xfer_len); + } +- dwc_write_reg32(&host_if->hc_regs[hc_num]->hcsplt, hcsplt.d32); ++ DWC_WRITE_REG32(&host_if->hc_regs[hc_num]->hcsplt, hcsplt.d32); + + } + +@@ -1571,14 +2422,14 @@ + hcintmsk_data_t hcintmsk; + hcintmsk.d32 = 0; + hcintmsk.b.chhltd = 1; +- dwc_write_reg32(&hc_regs->hcintmsk, hcintmsk.d32); ++ DWC_WRITE_REG32(&hc_regs->hcintmsk, hcintmsk.d32); + + /* + * Make sure no other interrupts besides halt are currently + * pending. Handling another interrupt could cause a crash due + * to the QTD and QH state. + */ +- dwc_write_reg32(&hc_regs->hcint, ~hcintmsk.d32); ++ DWC_WRITE_REG32(&hc_regs->hcint, ~hcintmsk.d32); + + /* + * Make sure the halt status is set to URB_DEQUEUE or AHB_ERR +@@ -1587,7 +2438,7 @@ + */ + hc->halt_status = halt_status; + +- hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); ++ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar); + if (hcchar.b.chen == 0) { + /* + * The channel is either already halted or it hasn't +@@ -1618,32 +2469,32 @@ + return; + } + +- hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); +- ++ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar); ++ + /* No need to set the bit in DDMA for disabling the channel */ +- //TODO check it everywhere channel is disabled +- if(!core_if->core_params->dma_desc_enable) ++ //TODO check it everywhere channel is disabled ++ if (!core_if->core_params->dma_desc_enable) + hcchar.b.chen = 1; + hcchar.b.chdis = 1; +- ++ + if (!core_if->dma_enable) { + /* Check for space in the request queue to issue the halt. */ + if (hc->ep_type == DWC_OTG_EP_TYPE_CONTROL || + hc->ep_type == DWC_OTG_EP_TYPE_BULK) { +- nptxsts.d32 = dwc_read_reg32(&global_regs->gnptxsts); ++ nptxsts.d32 = DWC_READ_REG32(&global_regs->gnptxsts); + if (nptxsts.b.nptxqspcavail == 0) { + hcchar.b.chen = 0; + } + } else { + hptxsts.d32 = +- dwc_read_reg32(&host_global_regs->hptxsts); ++ DWC_READ_REG32(&host_global_regs->hptxsts); + if ((hptxsts.b.ptxqspcavail == 0) + || (core_if->queuing_high_bandwidth)) { + hcchar.b.chen = 0; + } + } + } +- dwc_write_reg32(&hc_regs->hcchar, hcchar.d32); ++ DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32); + + hc->halt_status = halt_status; + +@@ -1681,8 +2532,8 @@ + * conditions. + */ + hc_regs = core_if->host_if->hc_regs[hc->hc_num]; +- dwc_write_reg32(&hc_regs->hcintmsk, 0); +- dwc_write_reg32(&hc_regs->hcint, 0xFFFFFFFF); ++ DWC_WRITE_REG32(&hc_regs->hcintmsk, 0); ++ DWC_WRITE_REG32(&hc_regs->hcint, 0xFFFFFFFF); + #ifdef DEBUG + DWC_TIMER_CANCEL(core_if->hc_xfer_timer[hc->hc_num]); + #endif +@@ -1705,7 +2556,7 @@ + hc->ep_type == DWC_OTG_EP_TYPE_ISOC) { + hfnum_data_t hfnum; + hfnum.d32 = +- dwc_read_reg32(&core_if->host_if->host_global_regs->hfnum); ++ DWC_READ_REG32(&core_if->host_if->host_global_regs->hfnum); + + /* 1 if _next_ frame is odd, 0 if it's even */ + hcchar->b.oddfrm = (hfnum.b.frnum & 0x1) ? 0 : 1; +@@ -1735,36 +2586,85 @@ + #ifdef DEBUG + void hc_xfer_timeout(void *ptr) + { +- hc_xfer_info_t *xfer_info = (hc_xfer_info_t *) ptr; +- int hc_num = xfer_info->hc->hc_num; ++ hc_xfer_info_t *xfer_info = NULL; ++ int hc_num = 0; ++ ++ if (ptr) ++ xfer_info = (hc_xfer_info_t *) ptr; ++ ++ if (!xfer_info->hc) { ++ DWC_ERROR("xfer_info->hc = %p\n", xfer_info->hc); ++ return; ++ } ++ ++ hc_num = xfer_info->hc->hc_num; + DWC_WARN("%s: timeout on channel %d\n", __func__, hc_num); + DWC_WARN(" start_hcchar_val 0x%08x\n", + xfer_info->core_if->start_hcchar_val[hc_num]); + } + #endif + ++void ep_xfer_timeout(void *ptr) ++{ ++ ep_xfer_info_t *xfer_info = NULL; ++ int ep_num = 0; ++ dctl_data_t dctl = {.d32 = 0 }; ++ gintsts_data_t gintsts = {.d32 = 0 }; ++ gintmsk_data_t gintmsk = {.d32 = 0 }; ++ ++ if (ptr) ++ xfer_info = (ep_xfer_info_t *) ptr; ++ ++ if (!xfer_info->ep) { ++ DWC_ERROR("xfer_info->ep = %p\n", xfer_info->ep); ++ return; ++ } ++ ++ ep_num = xfer_info->ep->num; ++ DWC_WARN("%s: timeout on endpoit %d\n", __func__, ep_num); ++ /* Put the sate to 2 as it was time outed */ ++ xfer_info->state = 2; ++ ++ dctl.d32 = DWC_READ_REG32(&xfer_info->core_if-> ++ dev_if->dev_global_regs->dctl); ++ gintsts.d32 = DWC_READ_REG32(&xfer_info->core_if-> ++ core_global_regs->gintsts); ++ gintmsk.d32 = DWC_READ_REG32(&xfer_info->core_if-> ++ core_global_regs->gintmsk); ++ ++ if (!gintmsk.b.goutnakeff) { ++ /* Unmask it */ ++ gintmsk.b.goutnakeff = 1; ++ DWC_WRITE_REG32(&xfer_info->core_if-> ++ core_global_regs->gintmsk, gintmsk.d32); ++ ++ } ++ ++ if (!gintsts.b.goutnakeff) { ++ dctl.b.sgoutnak = 1; ++ } ++ DWC_WRITE_REG32(&xfer_info->core_if->dev_if-> ++ dev_global_regs->dctl, dctl.d32); ++ ++} ++ + void set_pid_isoc(dwc_hc_t * hc) + { + /* Set up the initial PID for the transfer. */ + if (hc->speed == DWC_OTG_EP_SPEED_HIGH) { + if (hc->ep_is_in) { + if (hc->multi_count == 1) { +- hc->data_pid_start = +- DWC_OTG_HC_PID_DATA0; ++ hc->data_pid_start = DWC_OTG_HC_PID_DATA0; + } else if (hc->multi_count == 2) { +- hc->data_pid_start = +- DWC_OTG_HC_PID_DATA1; ++ hc->data_pid_start = DWC_OTG_HC_PID_DATA1; + } else { +- hc->data_pid_start = +- DWC_OTG_HC_PID_DATA2; ++ hc->data_pid_start = DWC_OTG_HC_PID_DATA2; + } + } else { + if (hc->multi_count == 1) { +- hc->data_pid_start = +- DWC_OTG_HC_PID_DATA0; ++ hc->data_pid_start = DWC_OTG_HC_PID_DATA0; + } else { +- hc->data_pid_start = +- DWC_OTG_HC_PID_MDATA; ++ hc->data_pid_start = DWC_OTG_HC_PID_MDATA; + } + } + } else { +@@ -1899,7 +2799,7 @@ + hc->start_pkt_count = num_packets; + hctsiz.b.pktcnt = num_packets; + hctsiz.b.pid = hc->data_pid_start; +- dwc_write_reg32(&hc_regs->hctsiz, hctsiz.d32); ++ DWC_WRITE_REG32(&hc_regs->hctsiz, hctsiz.d32); + + DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num); + DWC_DEBUGPL(DBG_HCDV, " Xfer Size: %d\n", hctsiz.b.xfersize); +@@ -1911,20 +2811,20 @@ + if (hc->align_buff) { + dma_addr = hc->align_buff; + } else { +- dma_addr = (uint32_t)hc->xfer_buff; ++ dma_addr = ((unsigned long)hc->xfer_buff & 0xffffffff); + } +- dwc_write_reg32(&hc_regs->hcdma, dma_addr); ++ DWC_WRITE_REG32(&hc_regs->hcdma, dma_addr); + } + + /* Start the split */ + if (hc->do_split) { + hcsplt_data_t hcsplt; +- hcsplt.d32 = dwc_read_reg32(&hc_regs->hcsplt); ++ hcsplt.d32 = DWC_READ_REG32(&hc_regs->hcsplt); + hcsplt.b.spltena = 1; +- dwc_write_reg32(&hc_regs->hcsplt, hcsplt.d32); ++ DWC_WRITE_REG32(&hc_regs->hcsplt, hcsplt.d32); + } + +- hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); ++ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar); + hcchar.b.multicnt = hc->multi_count; + hc_set_even_odd_frame(core_if, hc, &hcchar); + #ifdef DEBUG +@@ -1938,7 +2838,7 @@ + /* Set host channel enable after all other setup is complete. */ + hcchar.b.chen = 1; + hcchar.b.chdis = 0; +- dwc_write_reg32(&hc_regs->hcchar, hcchar.d32); ++ DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32); + + hc->xfer_started = 1; + hc->requests++; +@@ -1953,6 +2853,7 @@ + hc->hc_num, core_if);//GRAYG + core_if->hc_xfer_info[hc->hc_num].core_if = core_if; + core_if->hc_xfer_info[hc->hc_num].hc = hc; ++ + /* Start a timer for this transfer. */ + DWC_TIMER_SCHEDULE(core_if->hc_xfer_timer[hc->hc_num], 10000); + } +@@ -1960,7 +2861,7 @@ + } + + /** +- * This function does the setup for a data transfer for a host channel ++ * This function does the setup for a data transfer for a host channel + * and starts the transfer in Descriptor DMA mode. + * + * Initializes HCTSIZ register. For a PING transfer the Do Ping bit is set. +@@ -1975,40 +2876,40 @@ + */ + void dwc_otg_hc_start_transfer_ddma(dwc_otg_core_if_t * core_if, dwc_hc_t * hc) + { +- dwc_otg_hc_regs_t *hc_regs = core_if->host_if->hc_regs[hc->hc_num]; ++ dwc_otg_hc_regs_t *hc_regs = core_if->host_if->hc_regs[hc->hc_num]; + hcchar_data_t hcchar; + hctsiz_data_t hctsiz; +- hcdma_data_t hcdma; +- ++ hcdma_data_t hcdma; ++ + hctsiz.d32 = 0; + +- if (hc->do_ping && !hc->ep_is_in) ++ if (hc->do_ping) + hctsiz.b_ddma.dopng = 1; + + if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC) + set_pid_isoc(hc); +- ++ + /* Packet Count and Xfer Size are not used in Descriptor DMA mode */ + hctsiz.b_ddma.pid = hc->data_pid_start; +- hctsiz.b_ddma.ntd = hc->ntd - 1; /* 0 - 1 descriptor, 1 - 2 descriptors, etc. */ +- hctsiz.b_ddma.schinfo = hc->schinfo; /* Non-zero only for high-speed interrupt endpoints */ +- ++ hctsiz.b_ddma.ntd = hc->ntd - 1; /* 0 - 1 descriptor, 1 - 2 descriptors, etc. */ ++ hctsiz.b_ddma.schinfo = hc->schinfo; /* Non-zero only for high-speed interrupt endpoints */ ++ + DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num); + DWC_DEBUGPL(DBG_HCDV, " Start PID: %d\n", hctsiz.b.pid); +- DWC_DEBUGPL(DBG_HCDV, " NTD: %d\n", hctsiz.b_ddma.ntd); ++ DWC_DEBUGPL(DBG_HCDV, " NTD: %d\n", hctsiz.b_ddma.ntd); + +- dwc_write_reg32(&hc_regs->hctsiz, hctsiz.d32); ++ DWC_WRITE_REG32(&hc_regs->hctsiz, hctsiz.d32); + + hcdma.d32 = 0; +- hcdma.b.dma_addr = ((uint32_t)hc->desc_list_addr) >> 11; +- ++ hcdma.b.dma_addr = ((uint32_t) hc->desc_list_addr) >> 11; ++ + /* Always start from first descriptor. */ + hcdma.b.ctd = 0; +- dwc_write_reg32(&hc_regs->hcdma, hcdma.d32); ++ DWC_WRITE_REG32(&hc_regs->hcdma, hcdma.d32); + +- hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); ++ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar); + hcchar.b.multicnt = hc->multi_count; +- ++ + #ifdef DEBUG + core_if->start_hcchar_val[hc->hc_num] = hcchar.d32; + if (hcchar.b.chdis) { +@@ -2020,14 +2921,15 @@ + /* Set host channel enable after all other setup is complete. */ + hcchar.b.chen = 1; + hcchar.b.chdis = 0; +- +- dwc_write_reg32(&hc_regs->hcchar, hcchar.d32); ++ ++ DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32); + + hc->xfer_started = 1; + hc->requests++; +- ++ + #ifdef DEBUG +- if ((hc->ep_type != DWC_OTG_EP_TYPE_INTR) && (hc->ep_type != DWC_OTG_EP_TYPE_ISOC)) { ++ if ((hc->ep_type != DWC_OTG_EP_TYPE_INTR) ++ && (hc->ep_type != DWC_OTG_EP_TYPE_ISOC)) { + DWC_DEBUGPL(DBG_HCDV, "DMA transfer %d from core_if %p\n", + hc->hc_num, core_if);//GRAYG + core_if->hc_xfer_info[hc->hc_num].core_if = core_if; +@@ -2035,11 +2937,10 @@ + /* Start a timer for this transfer. */ + DWC_TIMER_SCHEDULE(core_if->hc_xfer_timer[hc->hc_num], 10000); + } +- + #endif +- ++ + } +- ++ + /** + * This function continues a data transfer that was started by previous call + * to dwc_otg_hc_start_transfer. The caller must ensure there is +@@ -2082,13 +2983,13 @@ + dwc_otg_hc_regs_t *hc_regs = + core_if->host_if->hc_regs[hc->hc_num]; + +- hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); ++ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar); + hc_set_even_odd_frame(core_if, hc, &hcchar); + hcchar.b.chen = 1; + hcchar.b.chdis = 0; + DWC_DEBUGPL(DBG_HCDV, " IN xfer: hcchar = 0x%08x\n", + hcchar.d32); +- dwc_write_reg32(&hc_regs->hcchar, hcchar.d32); ++ DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32); + hc->requests++; + return 1; + } else { +@@ -2099,7 +3000,7 @@ + hcchar_data_t hcchar; + dwc_otg_hc_regs_t *hc_regs; + hc_regs = core_if->host_if->hc_regs[hc->hc_num]; +- hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); ++ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar); + hc_set_even_odd_frame(core_if, hc, &hcchar); + } + +@@ -2128,12 +3029,12 @@ + hctsiz.d32 = 0; + hctsiz.b.dopng = 1; + hctsiz.b.pktcnt = 1; +- dwc_write_reg32(&hc_regs->hctsiz, hctsiz.d32); ++ DWC_WRITE_REG32(&hc_regs->hctsiz, hctsiz.d32); + +- hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); ++ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar); + hcchar.b.chen = 1; + hcchar.b.chdis = 0; +- dwc_write_reg32(&hc_regs->hcchar, hcchar.d32); ++ DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32); + } + + /* +@@ -2168,7 +3069,7 @@ + if ((((unsigned long)data_buff) & 0x3) == 0) { + /* xfer_buff is DWORD aligned. */ + for (i = 0; i < dword_count; i++, data_buff++) { +- dwc_write_reg32(data_fifo, *data_buff); ++ DWC_WRITE_REG32(data_fifo, *data_buff); + } + } else { + /* xfer_buff is not DWORD aligned. */ +@@ -2177,7 +3078,7 @@ + data = + (data_buff[0] | data_buff[1] << 8 | data_buff[2] << + 16 | data_buff[3] << 24); +- dwc_write_reg32(data_fifo, data); ++ DWC_WRITE_REG32(data_fifo, data); + } + } + +@@ -2186,21 +3087,62 @@ + } + + /** +- * Gets the current USB frame number. This is the frame number from the last +- * SOF packet. ++ * Gets the current USB frame number. This is the frame number from the last ++ * SOF packet. + */ + uint32_t dwc_otg_get_frame_number(dwc_otg_core_if_t * core_if) + { + dsts_data_t dsts; +- dsts.d32 = dwc_read_reg32(&core_if->dev_if->dev_global_regs->dsts); ++ dsts.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts); + + /* read current frame/microframe number from DSTS register */ + return dsts.b.soffn; + } + + /** +- * This function reads a setup packet from the Rx FIFO into the destination +- * buffer. This function is called from the Rx Status Queue Level (RxStsQLvl) ++ * Calculates and gets the frame Interval value of HFIR register according PHY ++ * type and speed.The application can modify a value of HFIR register only after ++ * the Port Enable bit of the Host Port Control and Status register ++ * (HPRT.PrtEnaPort) has been set. ++*/ ++ ++uint32_t calc_frame_interval(dwc_otg_core_if_t * core_if) ++{ ++ gusbcfg_data_t usbcfg; ++ hwcfg2_data_t hwcfg2; ++ hprt0_data_t hprt0; ++ int clock = 60; // default value ++ usbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg); ++ hwcfg2.d32 = DWC_READ_REG32(&core_if->core_global_regs->ghwcfg2); ++ hprt0.d32 = DWC_READ_REG32(core_if->host_if->hprt0); ++ if (!usbcfg.b.physel && usbcfg.b.ulpi_utmi_sel && !usbcfg.b.phyif) ++ clock = 60; ++ if (usbcfg.b.physel && hwcfg2.b.fs_phy_type == 3) ++ clock = 48; ++ if (!usbcfg.b.phylpwrclksel && !usbcfg.b.physel && ++ !usbcfg.b.ulpi_utmi_sel && usbcfg.b.phyif) ++ clock = 30; ++ if (!usbcfg.b.phylpwrclksel && !usbcfg.b.physel && ++ !usbcfg.b.ulpi_utmi_sel && !usbcfg.b.phyif) ++ clock = 60; ++ if (usbcfg.b.phylpwrclksel && !usbcfg.b.physel && ++ !usbcfg.b.ulpi_utmi_sel && usbcfg.b.phyif) ++ clock = 48; ++ if (usbcfg.b.physel && !usbcfg.b.phyif && hwcfg2.b.fs_phy_type == 2) ++ clock = 48; ++ if (usbcfg.b.physel && hwcfg2.b.fs_phy_type == 1) ++ clock = 48; ++ if (hprt0.b.prtspd == 0) ++ /* High speed case */ ++ return 125 * clock; ++ else ++ /* FS/LS case */ ++ return 1000 * clock; ++} ++ ++/** ++ * This function reads a setup packet from the Rx FIFO into the destination ++ * buffer. This function is called from the Rx Status Queue Level (RxStsQLvl) + * Interrupt routine when a SETUP packet has been received in Slave mode. + * + * @param core_if Programming view of DWC_otg controller. +@@ -2211,13 +3153,13 @@ + /* Get the 8 bytes of a setup transaction data */ + + /* Pop 2 DWORDS off the receive data FIFO into memory */ +- dest[0] = dwc_read_reg32(core_if->data_fifo[0]); +- dest[1] = dwc_read_reg32(core_if->data_fifo[0]); ++ dest[0] = DWC_READ_REG32(core_if->data_fifo[0]); ++ dest[1] = DWC_READ_REG32(core_if->data_fifo[0]); + } + + /** +- * This function enables EP0 OUT to receive SETUP packets and configures EP0 +- * IN for transmitting packets. It is normally called when the ++ * This function enables EP0 OUT to receive SETUP packets and configures EP0 ++ * IN for transmitting packets. It is normally called when the + * "Enumeration Done" interrupt occurs. + * + * @param core_if Programming view of DWC_otg controller. +@@ -2232,9 +3174,9 @@ + dctl_data_t dctl = {.d32 = 0 }; + + /* Read the Device Status and Endpoint 0 Control registers */ +- dsts.d32 = dwc_read_reg32(&dev_if->dev_global_regs->dsts); +- diepctl.d32 = dwc_read_reg32(&dev_if->in_ep_regs[0]->diepctl); +- doepctl.d32 = dwc_read_reg32(&dev_if->out_ep_regs[0]->doepctl); ++ dsts.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->dsts); ++ diepctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[0]->diepctl); ++ doepctl.d32 = DWC_READ_REG32(&dev_if->out_ep_regs[0]->doepctl); + + /* Set the MPS of the IN EP based on the enumeration speed */ + switch (dsts.b.enumspd) { +@@ -2248,28 +3190,29 @@ + break; + } + +- dwc_write_reg32(&dev_if->in_ep_regs[0]->diepctl, diepctl.d32); ++ DWC_WRITE_REG32(&dev_if->in_ep_regs[0]->diepctl, diepctl.d32); + + /* Enable OUT EP for receive */ + doepctl.b.epena = 1; +- dwc_write_reg32(&dev_if->out_ep_regs[0]->doepctl, doepctl.d32); ++ DWC_WRITE_REG32(&dev_if->out_ep_regs[0]->doepctl, doepctl.d32); + + #ifdef VERBOSE + DWC_DEBUGPL(DBG_PCDV, "doepctl0=%0x\n", +- dwc_read_reg32(&dev_if->out_ep_regs[0]->doepctl)); ++ DWC_READ_REG32(&dev_if->out_ep_regs[0]->doepctl)); + DWC_DEBUGPL(DBG_PCDV, "diepctl0=%0x\n", +- dwc_read_reg32(&dev_if->in_ep_regs[0]->diepctl)); ++ DWC_READ_REG32(&dev_if->in_ep_regs[0]->diepctl)); + #endif + dctl.b.cgnpinnak = 1; + +- dwc_modify_reg32(&dev_if->dev_global_regs->dctl, dctl.d32, dctl.d32); ++ DWC_MODIFY_REG32(&dev_if->dev_global_regs->dctl, dctl.d32, dctl.d32); + DWC_DEBUGPL(DBG_PCDV, "dctl=%0x\n", +- dwc_read_reg32(&dev_if->dev_global_regs->dctl)); ++ DWC_READ_REG32(&dev_if->dev_global_regs->dctl)); ++ + } + + /** + * This function activates an EP. The Device EP control register for +- * the EP is configured as defined in the ep structure. Note: This ++ * the EP is configured as defined in the ep structure. Note: This + * function is not used for EP0. + * + * @param core_if Programming view of DWC_otg controller. +@@ -2281,10 +3224,17 @@ + depctl_data_t depctl; + volatile uint32_t *addr; + daint_data_t daintmsk = {.d32 = 0 }; ++ dcfg_data_t dcfg; ++ uint8_t i; + + DWC_DEBUGPL(DBG_PCDV, "%s() EP%d-%s\n", __func__, ep->num, + (ep->is_in ? "IN" : "OUT")); + ++#ifdef DWC_UTE_PER_IO ++ ep->xiso_frame_num = 0xFFFFFFFF; ++ ep->xiso_active_xfers = 0; ++ ep->xiso_queued_xfers = 0; ++#endif + /* Read DEPCTLn register */ + if (ep->is_in == 1) { + addr = &dev_if->in_ep_regs[ep->num]->diepctl; +@@ -2296,21 +3246,43 @@ + + /* If the EP is already active don't change the EP Control + * register. */ +- depctl.d32 = dwc_read_reg32(addr); ++ depctl.d32 = DWC_READ_REG32(addr); + if (!depctl.b.usbactep) { + depctl.b.mps = ep->maxpacket; + depctl.b.eptype = ep->type; + depctl.b.txfnum = ep->tx_fifo_num; + + if (ep->type == DWC_OTG_EP_TYPE_ISOC) { +- depctl.b.setd0pid = 1; // ??? ++ depctl.b.setd0pid = 1; // ??? + } else { + depctl.b.setd0pid = 1; + } + depctl.b.usbactep = 1; + +- dwc_write_reg32(addr, depctl.d32); +- DWC_DEBUGPL(DBG_PCDV, "DEPCTL=%08x\n", dwc_read_reg32(addr)); ++ /* Update nextep_seq array and EPMSCNT in DCFG*/ ++ if (!(depctl.b.eptype & 1) && (ep->is_in == 1)) { // NP IN EP ++ for (i = 0; i <= core_if->dev_if->num_in_eps; i++) { ++ if (core_if->nextep_seq[i] == core_if->first_in_nextep_seq) ++ break; ++ } ++ core_if->nextep_seq[i] = ep->num; ++ core_if->nextep_seq[ep->num] = core_if->first_in_nextep_seq; ++ depctl.b.nextep = core_if->nextep_seq[ep->num]; ++ dcfg.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->dcfg); ++ dcfg.b.epmscnt++; ++ DWC_WRITE_REG32(&dev_if->dev_global_regs->dcfg, dcfg.d32); ++ ++ DWC_DEBUGPL(DBG_PCDV,"%s first_in_nextep_seq= %2d; nextep_seq[]:\n", ++ __func__, core_if->first_in_nextep_seq); ++ for (i=0; i <= core_if->dev_if->num_in_eps; i++) { ++ DWC_DEBUGPL(DBG_PCDV, "%2d\n", core_if->nextep_seq[i]); ++ } ++ ++ } ++ ++ ++ DWC_WRITE_REG32(addr, depctl.d32); ++ DWC_DEBUGPL(DBG_PCDV, "DEPCTL=%08x\n", DWC_READ_REG32(addr)); + } + + /* Enable the Interrupt for this EP */ +@@ -2322,17 +3294,26 @@ + diepmsk.b.epdisabled = 1; + diepmsk.b.ahberr = 1; + diepmsk.b.intknepmis = 1; ++ if (!core_if->en_multiple_tx_fifo && core_if->dma_enable) ++ diepmsk.b.intknepmis = 0; + diepmsk.b.txfifoundrn = 1; //????? ++ if (ep->type == DWC_OTG_EP_TYPE_ISOC) { ++ diepmsk.b.nak = 1; ++ } + ++ ++ ++/* + if (core_if->dma_desc_enable) { + diepmsk.b.bna = 1; + } ++*/ + /* +- if(core_if->dma_enable) { ++ if (core_if->dma_enable) { + doepmsk.b.nak = 1; + } + */ +- dwc_write_reg32(&dev_if->dev_global_regs-> ++ DWC_WRITE_REG32(&dev_if->dev_global_regs-> + diepeachintmsk[ep->num], diepmsk.d32); + + } else { +@@ -2340,35 +3321,53 @@ + doepmsk.b.xfercompl = 1; + doepmsk.b.ahberr = 1; + doepmsk.b.epdisabled = 1; ++ if (ep->type == DWC_OTG_EP_TYPE_ISOC) ++ doepmsk.b.outtknepdis = 1; ++ ++/* + + if (core_if->dma_desc_enable) { + doepmsk.b.bna = 1; + } ++*/ + /* + doepmsk.b.babble = 1; + doepmsk.b.nyet = 1; + doepmsk.b.nak = 1; + */ +- dwc_write_reg32(&dev_if->dev_global_regs-> ++ DWC_WRITE_REG32(&dev_if->dev_global_regs-> + doepeachintmsk[ep->num], doepmsk.d32); + } +- dwc_modify_reg32(&dev_if->dev_global_regs->deachintmsk, ++ DWC_MODIFY_REG32(&dev_if->dev_global_regs->deachintmsk, + 0, daintmsk.d32); + } else { +- dwc_modify_reg32(&dev_if->dev_global_regs->daintmsk, ++ if (ep->type == DWC_OTG_EP_TYPE_ISOC) { ++ if (ep->is_in) ++ { ++ diepmsk_data_t diepmsk = {.d32 = 0 }; ++ diepmsk.b.nak = 1; ++ DWC_MODIFY_REG32(&dev_if->dev_global_regs->diepmsk, 0, diepmsk.d32); ++ } else { ++ doepmsk_data_t doepmsk = {.d32 = 0 }; ++ doepmsk.b.outtknepdis = 1; ++ DWC_MODIFY_REG32(&dev_if->dev_global_regs->doepmsk, 0, doepmsk.d32); ++ } ++ } ++ DWC_MODIFY_REG32(&dev_if->dev_global_regs->daintmsk, + 0, daintmsk.d32); + } + + DWC_DEBUGPL(DBG_PCDV, "DAINTMSK=%0x\n", +- dwc_read_reg32(&dev_if->dev_global_regs->daintmsk)); ++ DWC_READ_REG32(&dev_if->dev_global_regs->daintmsk)); + + ep->stall_clear_flag = 0; ++ + return; + } + + /** +- * This function deactivates an EP. This is done by clearing the USB Active +- * EP bit in the Device EP control register. Note: This function is not used ++ * This function deactivates an EP. This is done by clearing the USB Active ++ * EP bit in the Device EP control register. Note: This function is not used + * for EP0. EP0 cannot be deactivated. + * + * @param core_if Programming view of DWC_otg controller. +@@ -2379,6 +3378,14 @@ + depctl_data_t depctl = {.d32 = 0 }; + volatile uint32_t *addr; + daint_data_t daintmsk = {.d32 = 0 }; ++ dcfg_data_t dcfg; ++ uint8_t i = 0; ++ ++#ifdef DWC_UTE_PER_IO ++ ep->xiso_frame_num = 0xFFFFFFFF; ++ ep->xiso_active_xfers = 0; ++ ep->xiso_queued_xfers = 0; ++#endif + + /* Read DEPCTLn register */ + if (ep->is_in == 1) { +@@ -2389,31 +3396,121 @@ + daintmsk.ep.out = 1 << ep->num; + } + +- depctl.d32 = dwc_read_reg32(addr); ++ depctl.d32 = DWC_READ_REG32(addr); + + depctl.b.usbactep = 0; ++ ++ /* Update nextep_seq array and EPMSCNT in DCFG*/ ++ if (!(depctl.b.eptype & 1) && ep->is_in == 1) { // NP EP IN ++ for (i = 0; i <= core_if->dev_if->num_in_eps; i++) { ++ if (core_if->nextep_seq[i] == ep->num) ++ break; ++ } ++ core_if->nextep_seq[i] = core_if->nextep_seq[ep->num]; ++ if (core_if->first_in_nextep_seq == ep->num) ++ core_if->first_in_nextep_seq = i; ++ core_if->nextep_seq[ep->num] = 0xff; ++ depctl.b.nextep = 0; ++ dcfg.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg); ++ dcfg.b.epmscnt--; ++ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dcfg, dcfg.d32); ++ ++ DWC_DEBUGPL(DBG_PCDV,"%s first_in_nextep_seq= %2d; nextep_seq[]:\n", ++ __func__, core_if->first_in_nextep_seq); ++ for (i=0; i <= core_if->dev_if->num_in_eps; i++) { ++ DWC_DEBUGPL(DBG_PCDV, "%2d\n", core_if->nextep_seq[i]); ++ } ++ } ++ ++ if (ep->is_in == 1) ++ depctl.b.txfnum = 0; + + if (core_if->dma_desc_enable) + depctl.b.epdis = 1; + +- dwc_write_reg32(addr, depctl.d32); ++ DWC_WRITE_REG32(addr, depctl.d32); ++ depctl.d32 = DWC_READ_REG32(addr); ++ if (core_if->dma_enable && ep->type == DWC_OTG_EP_TYPE_ISOC && depctl.b.epena) ++ { ++ depctl_data_t depctl = {.d32 = 0}; ++ if (ep->is_in) ++ { ++ diepint_data_t diepint = {.d32 = 0}; ++ ++ depctl.b.snak = 1; ++ DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[ep->num]->diepctl, depctl.d32); ++ do ++ { ++ dwc_udelay(10); ++ diepint.d32 = DWC_READ_REG32(&core_if->dev_if-> ++ in_ep_regs[ep->num]->diepint); ++ } while (!diepint.b.inepnakeff); ++ diepint.b.inepnakeff = 1; ++ DWC_WRITE_REG32(&core_if->dev_if-> ++ in_ep_regs[ep->num]->diepint, diepint.d32); ++ depctl.d32 = 0; ++ depctl.b.epdis = 1; ++ DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[ep->num]->diepctl, depctl.d32); ++ do ++ { ++ dwc_udelay(10); ++ diepint.d32 = DWC_READ_REG32(&core_if->dev_if-> ++ in_ep_regs[ep->num]->diepint); ++ } while (!diepint.b.epdisabled); ++ diepint.b.epdisabled = 1; ++ DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[ep->num]->diepint, diepint.d32); ++ } else { ++ dctl_data_t dctl = {.d32 = 0}; ++ gintmsk_data_t gintsts = {.d32 = 0}; ++ doepint_data_t doepint = {.d32 = 0}; ++ dctl.b.sgoutnak = 1; ++ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, 0, dctl.d32); ++ do ++ { ++ dwc_udelay(10); ++ gintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts); ++ } while (!gintsts.b.goutnakeff); ++ gintsts.d32 = 0; ++ gintsts.b.goutnakeff = 1; ++ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32); ++ ++ depctl.d32 = 0; ++ depctl.b.epdis = 1; ++ depctl.b.snak = 1; ++ DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[ep->num]->doepctl, depctl.d32); ++ do ++ { ++ dwc_udelay(10); ++ doepint.d32 = DWC_READ_REG32(&core_if->dev_if-> ++ out_ep_regs[ep->num]->doepint); ++ } while (!doepint.b.epdisabled); ++ ++ doepint.b.epdisabled = 1; ++ DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[ep->num]->doepint, doepint.d32); ++ ++ dctl.d32 = 0; ++ dctl.b.cgoutnak = 1; ++ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, 0, dctl.d32); ++ } ++ } + + /* Disable the Interrupt for this EP */ + if (core_if->multiproc_int_enable) { +- dwc_modify_reg32(&core_if->dev_if->dev_global_regs->deachintmsk, ++ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->deachintmsk, + daintmsk.d32, 0); + + if (ep->is_in == 1) { +- dwc_write_reg32(&core_if->dev_if->dev_global_regs-> ++ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs-> + diepeachintmsk[ep->num], 0); + } else { +- dwc_write_reg32(&core_if->dev_if->dev_global_regs-> ++ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs-> + doepeachintmsk[ep->num], 0); + } + } else { +- dwc_modify_reg32(&core_if->dev_if->dev_global_regs->daintmsk, ++ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->daintmsk, + daintmsk.d32, 0); + } ++ + } + + /** +@@ -2428,28 +3525,52 @@ + uint32_t offset; + uint32_t xfer_est; + int i; ++ unsigned maxxfer_local, total_len; ++ ++ if (!ep->is_in && ep->type == DWC_OTG_EP_TYPE_INTR && ++ (ep->maxpacket%4)) { ++ maxxfer_local = ep->maxpacket; ++ total_len = ep->xfer_len; ++ } else { ++ maxxfer_local = ep->maxxfer; ++ total_len = ep->total_len; ++ } ++ ++ ep->desc_cnt = (total_len / maxxfer_local) + ++ ((total_len % maxxfer_local) ? 1 : 0); + +- ep->desc_cnt = (ep->total_len / ep->maxxfer) + +- ((ep->total_len % ep->maxxfer) ? 1 : 0); + if (!ep->desc_cnt) + ep->desc_cnt = 1; + ++ if (ep->desc_cnt > MAX_DMA_DESC_CNT) ++ ep->desc_cnt = MAX_DMA_DESC_CNT; ++ + dma_desc = ep->desc_addr; +- xfer_est = ep->total_len; ++ if (maxxfer_local == ep->maxpacket) { ++ if ((total_len % maxxfer_local) && ++ (total_len/maxxfer_local < MAX_DMA_DESC_CNT)) { ++ xfer_est = (ep->desc_cnt - 1) * maxxfer_local + ++ (total_len % maxxfer_local); ++ } else ++ xfer_est = ep->desc_cnt * maxxfer_local; ++ } ++ else ++ xfer_est = total_len; + offset = 0; + for (i = 0; i < ep->desc_cnt; ++i) { + /** DMA Descriptor Setup */ +- if (xfer_est > ep->maxxfer) { ++ if (xfer_est > maxxfer_local) { + dma_desc->status.b.bs = BS_HOST_BUSY; + dma_desc->status.b.l = 0; + dma_desc->status.b.ioc = 0; + dma_desc->status.b.sp = 0; +- dma_desc->status.b.bytes = ep->maxxfer; ++ dma_desc->status.b.bytes = maxxfer_local; + dma_desc->buf = ep->dma_addr + offset; ++ dma_desc->status.b.sts = 0; + dma_desc->status.b.bs = BS_HOST_READY; + +- xfer_est -= ep->maxxfer; +- offset += ep->maxxfer; ++ xfer_est -= maxxfer_local; ++ offset += maxxfer_local; + } else { + dma_desc->status.b.bs = BS_HOST_BUSY; + dma_desc->status.b.l = 1; +@@ -2461,20 +3582,76 @@ + sent_zlp) ? 1 : 0); + dma_desc->status.b.bytes = xfer_est; + } else { +- dma_desc->status.b.bytes = +- xfer_est + ((4 - (xfer_est & 0x3)) & 0x3); ++ if (maxxfer_local == ep->maxpacket) ++ dma_desc->status.b.bytes = xfer_est; ++ else ++ dma_desc->status.b.bytes = ++ xfer_est + ((4 - (xfer_est & 0x3)) & 0x3); + } + + dma_desc->buf = ep->dma_addr + offset; ++ dma_desc->status.b.sts = 0; + dma_desc->status.b.bs = BS_HOST_READY; + } + dma_desc++; + } + } ++/** ++ * This function is called when to write ISOC data into appropriate dedicated ++ * periodic FIFO. ++ */ ++static int32_t write_isoc_tx_fifo(dwc_otg_core_if_t * core_if, dwc_ep_t * dwc_ep) ++{ ++ dwc_otg_dev_if_t *dev_if = core_if->dev_if; ++ dwc_otg_dev_in_ep_regs_t *ep_regs; ++ dtxfsts_data_t txstatus = {.d32 = 0 }; ++ uint32_t len = 0; ++ int epnum = dwc_ep->num; ++ int dwords; ++ ++ DWC_DEBUGPL(DBG_PCD, "Dedicated TxFifo Empty: %d \n", epnum); ++ ++ ep_regs = core_if->dev_if->in_ep_regs[epnum]; ++ ++ len = dwc_ep->xfer_len - dwc_ep->xfer_count; ++ ++ if (len > dwc_ep->maxpacket) { ++ len = dwc_ep->maxpacket; ++ } + ++ dwords = (len + 3) / 4; ++ ++ /* While there is space in the queue and space in the FIFO and ++ * More data to tranfer, Write packets to the Tx FIFO */ ++ txstatus.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->dtxfsts); ++ DWC_DEBUGPL(DBG_PCDV, "b4 dtxfsts[%d]=0x%08x\n", epnum, txstatus.d32); ++ ++ while (txstatus.b.txfspcavail > dwords && ++ dwc_ep->xfer_count < dwc_ep->xfer_len && ++ dwc_ep->xfer_len != 0) { ++ /* Write the FIFO */ ++ dwc_otg_ep_write_packet(core_if, dwc_ep, 0); ++ ++ len = dwc_ep->xfer_len - dwc_ep->xfer_count; ++ if (len > dwc_ep->maxpacket) { ++ len = dwc_ep->maxpacket; ++ } ++ ++ dwords = (len + 3) / 4; ++ txstatus.d32 = ++ DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->dtxfsts); ++ DWC_DEBUGPL(DBG_PCDV, "dtxfsts[%d]=0x%08x\n", epnum, ++ txstatus.d32); ++ } ++ ++ DWC_DEBUGPL(DBG_PCDV, "b4 dtxfsts[%d]=0x%08x\n", epnum, ++ DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->dtxfsts)); ++ ++ return 1; ++} + /** + * This function does the setup for a data transfer for an EP and +- * starts the transfer. For an IN transfer, the packets will be ++ * starts the transfer. For an IN transfer, the packets will be + * loaded into the appropriate Tx FIFO in the ISR. For OUT transfers, + * the packets are unloaded from the Rx FIFO in the ISR. the ISR. + * +@@ -2502,21 +3679,27 @@ + gnptxsts_data_t gtxstatus; + + gtxstatus.d32 = +- dwc_read_reg32(&core_if->core_global_regs->gnptxsts); ++ DWC_READ_REG32(&core_if->core_global_regs->gnptxsts); + + if (core_if->en_multiple_tx_fifo == 0 +- && gtxstatus.b.nptxqspcavail == 0) { ++ && gtxstatus.b.nptxqspcavail == 0 ++ && !core_if->dma_enable) { + #ifdef DEBUG + DWC_PRINTF("TX Queue Full (0x%0x)\n", gtxstatus.d32); + #endif + return; + } + +- depctl.d32 = dwc_read_reg32(&(in_regs->diepctl)); +- deptsiz.d32 = dwc_read_reg32(&(in_regs->dieptsiz)); ++ depctl.d32 = DWC_READ_REG32(&(in_regs->diepctl)); ++ deptsiz.d32 = DWC_READ_REG32(&(in_regs->dieptsiz)); ++ ++ if (ep->maxpacket > ep->maxxfer / MAX_PKT_CNT) ++ ep->xfer_len += (ep->maxxfer < (ep->total_len - ep->xfer_len)) ? ++ ep->maxxfer : (ep->total_len - ep->xfer_len); ++ else ++ ep->xfer_len += (MAX_PKT_CNT * ep->maxpacket < (ep->total_len - ep->xfer_len)) ? ++ MAX_PKT_CNT * ep->maxpacket : (ep->total_len - ep->xfer_len); + +- ep->xfer_len += (ep->maxxfer < (ep->total_len - ep->xfer_len)) ? +- ep->maxxfer : (ep->total_len - ep->xfer_len); + + /* Zero Length Packet? */ + if ((ep->xfer_len - ep->xfer_count) == 0) { +@@ -2526,93 +3709,121 @@ + /* Program the transfer size and packet count + * as follows: xfersize = N * maxpacket + + * short_packet pktcnt = N + (short_packet +- * exist ? 1 : 0) ++ * exist ? 1 : 0) + */ + deptsiz.b.xfersize = ep->xfer_len - ep->xfer_count; + deptsiz.b.pktcnt = + (ep->xfer_len - ep->xfer_count - 1 + + ep->maxpacket) / ep->maxpacket; ++ if (deptsiz.b.pktcnt > MAX_PKT_CNT) { ++ deptsiz.b.pktcnt = MAX_PKT_CNT; ++ deptsiz.b.xfersize = deptsiz.b.pktcnt * ep->maxpacket; ++ } ++ if (ep->type == DWC_OTG_EP_TYPE_ISOC) ++ deptsiz.b.mc = deptsiz.b.pktcnt; + } + + /* Write the DMA register */ + if (core_if->dma_enable) { + if (core_if->dma_desc_enable == 0) { +- dwc_write_reg32(&in_regs->dieptsiz, ++ if (ep->type != DWC_OTG_EP_TYPE_ISOC) ++ deptsiz.b.mc = 1; ++ DWC_WRITE_REG32(&in_regs->dieptsiz, + deptsiz.d32); +- dwc_write_reg32(&(in_regs->diepdma), ++ DWC_WRITE_REG32(&(in_regs->diepdma), + (uint32_t) ep->dma_addr); + } else { + #ifdef DWC_UTE_CFI + /* The descriptor chain should be already initialized by now */ + if (ep->buff_mode != BM_STANDARD) { +- dwc_write_reg32(&in_regs->diepdma, ++ DWC_WRITE_REG32(&in_regs->diepdma, + ep->descs_dma_addr); + } else { + #endif +- init_dma_desc_chain(core_if, ep); ++ init_dma_desc_chain(core_if, ep); + /** DIEPDMAn Register write */ +- dwc_write_reg32(&in_regs->diepdma, +- ep->dma_desc_addr); ++ DWC_WRITE_REG32(&in_regs->diepdma, ++ ep->dma_desc_addr); + #ifdef DWC_UTE_CFI +- } ++ } + #endif + } + } else { +- dwc_write_reg32(&in_regs->dieptsiz, deptsiz.d32); ++ DWC_WRITE_REG32(&in_regs->dieptsiz, deptsiz.d32); + if (ep->type != DWC_OTG_EP_TYPE_ISOC) { +- /** ++ /** + * Enable the Non-Periodic Tx FIFO empty interrupt, + * or the Tx FIFO epmty interrupt in dedicated Tx FIFO mode, + * the data will be written into the fifo by the ISR. + */ + if (core_if->en_multiple_tx_fifo == 0) { + intr_mask.b.nptxfempty = 1; +- dwc_modify_reg32(&core_if-> +- core_global_regs-> +- gintmsk, intr_mask.d32, +- intr_mask.d32); ++ DWC_MODIFY_REG32 ++ (&core_if->core_global_regs->gintmsk, ++ intr_mask.d32, intr_mask.d32); + } else { + /* Enable the Tx FIFO Empty Interrupt for this EP */ + if (ep->xfer_len > 0) { + uint32_t fifoemptymsk = 0; + fifoemptymsk = 1 << ep->num; +- dwc_modify_reg32(&core_if-> +- dev_if-> +- dev_global_regs-> +- dtknqr4_fifoemptymsk, +- 0, +- fifoemptymsk); ++ DWC_MODIFY_REG32 ++ (&core_if->dev_if->dev_global_regs->dtknqr4_fifoemptymsk, ++ 0, fifoemptymsk); + + } + } ++ } else { ++ write_isoc_tx_fifo(core_if, ep); ++ } ++ } ++ if (!core_if->core_params->en_multiple_tx_fifo && core_if->dma_enable) ++ depctl.b.nextep = core_if->nextep_seq[ep->num]; ++ ++ if (ep->type == DWC_OTG_EP_TYPE_ISOC) ++ { ++ dsts_data_t dsts = {.d32 = 0}; ++ if (ep->bInterval == 1) { ++ dsts.d32 = ++ DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts); ++ ep->frame_num = dsts.b.soffn + ep->bInterval; ++ if (ep->frame_num > 0x3FFF) ++ { ++ ep->frm_overrun = 1; ++ ep->frame_num &= 0x3FFF; ++ } else ++ ep->frm_overrun = 0; ++ if (ep->frame_num & 0x1) { ++ depctl.b.setd1pid = 1; ++ } else { ++ depctl.b.setd0pid = 1; ++ } + } + } +- + /* EP enable, IN data in FIFO */ + depctl.b.cnak = 1; + depctl.b.epena = 1; +- dwc_write_reg32(&in_regs->diepctl, depctl.d32); +- +- depctl.d32 = +- dwc_read_reg32(&core_if->dev_if->in_ep_regs[0]->diepctl); +- depctl.b.nextep = ep->num; +- dwc_write_reg32(&core_if->dev_if->in_ep_regs[0]->diepctl, +- depctl.d32); ++ DWC_WRITE_REG32(&in_regs->diepctl, depctl.d32); + + } else { + /* OUT endpoint */ + dwc_otg_dev_out_ep_regs_t *out_regs = + core_if->dev_if->out_ep_regs[ep->num]; + +- depctl.d32 = dwc_read_reg32(&(out_regs->doepctl)); +- deptsiz.d32 = dwc_read_reg32(&(out_regs->doeptsiz)); ++ depctl.d32 = DWC_READ_REG32(&(out_regs->doepctl)); ++ deptsiz.d32 = DWC_READ_REG32(&(out_regs->doeptsiz)); + +- ep->xfer_len += (ep->maxxfer < (ep->total_len - ep->xfer_len)) ? +- ep->maxxfer : (ep->total_len - ep->xfer_len); ++ if (!core_if->dma_desc_enable) { ++ if (ep->maxpacket > ep->maxxfer / MAX_PKT_CNT) ++ ep->xfer_len += (ep->maxxfer < (ep->total_len - ep->xfer_len)) ? ++ ep->maxxfer : (ep->total_len - ep->xfer_len); ++ else ++ ep->xfer_len += (MAX_PKT_CNT * ep->maxpacket < (ep->total_len ++ - ep->xfer_len)) ? MAX_PKT_CNT * ep->maxpacket : (ep->total_len - ep->xfer_len); ++ } + + /* Program the transfer size and packet count as follows: +- * +- * pktcnt = N ++ * ++ * pktcnt = N + * xfersize = N * maxpacket + */ + if ((ep->xfer_len - ep->xfer_count) == 0) { +@@ -2623,8 +3834,13 @@ + deptsiz.b.pktcnt = + (ep->xfer_len - ep->xfer_count + + (ep->maxpacket - 1)) / ep->maxpacket; +- ep->xfer_len = +- deptsiz.b.pktcnt * ep->maxpacket + ep->xfer_count; ++ if (deptsiz.b.pktcnt > MAX_PKT_CNT) { ++ deptsiz.b.pktcnt = MAX_PKT_CNT; ++ } ++ if (!core_if->dma_desc_enable) { ++ ep->xfer_len = ++ deptsiz.b.pktcnt * ep->maxpacket + ep->xfer_count; ++ } + deptsiz.b.xfersize = ep->xfer_len - ep->xfer_count; + } + +@@ -2633,47 +3849,98 @@ + + if (core_if->dma_enable) { + if (!core_if->dma_desc_enable) { +- dwc_write_reg32(&out_regs->doeptsiz, ++ DWC_WRITE_REG32(&out_regs->doeptsiz, + deptsiz.d32); + +- dwc_write_reg32(&(out_regs->doepdma), ++ DWC_WRITE_REG32(&(out_regs->doepdma), + (uint32_t) ep->dma_addr); + } else { + #ifdef DWC_UTE_CFI + /* The descriptor chain should be already initialized by now */ + if (ep->buff_mode != BM_STANDARD) { +- dwc_write_reg32(&out_regs->doepdma, ++ DWC_WRITE_REG32(&out_regs->doepdma, + ep->descs_dma_addr); + } else { + #endif +- +- init_dma_desc_chain(core_if, ep); +- ++ /** This is used for interrupt out transfers*/ ++ if (!ep->xfer_len) ++ ep->xfer_len = ep->total_len; ++ init_dma_desc_chain(core_if, ep); ++ ++ if (core_if->core_params->dev_out_nak) { ++ if (ep->type == DWC_OTG_EP_TYPE_BULK) { ++ deptsiz.b.pktcnt = (ep->total_len + ++ (ep->maxpacket - 1)) / ep->maxpacket; ++ deptsiz.b.xfersize = ep->total_len; ++ /* Remember initial value of doeptsiz */ ++ core_if->start_doeptsiz_val[ep->num] = deptsiz.d32; ++ DWC_WRITE_REG32(&out_regs->doeptsiz, ++ deptsiz.d32); ++ } ++ } + /** DOEPDMAn Register write */ +- dwc_write_reg32(&out_regs->doepdma, +- ep->dma_desc_addr); ++ DWC_WRITE_REG32(&out_regs->doepdma, ++ ep->dma_desc_addr); + #ifdef DWC_UTE_CFI + } + #endif + } + } else { +- dwc_write_reg32(&out_regs->doeptsiz, deptsiz.d32); ++ DWC_WRITE_REG32(&out_regs->doeptsiz, deptsiz.d32); ++ } ++ ++ if (ep->type == DWC_OTG_EP_TYPE_ISOC) ++ { ++ dsts_data_t dsts = {.d32 = 0}; ++ if (ep->bInterval == 1) { ++ dsts.d32 = ++ DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts); ++ ep->frame_num = dsts.b.soffn + ep->bInterval; ++ if (ep->frame_num > 0x3FFF) ++ { ++ ep->frm_overrun = 1; ++ ep->frame_num &= 0x3FFF; ++ } else ++ ep->frm_overrun = 0; ++ ++ if (ep->frame_num & 0x1) { ++ depctl.b.setd1pid = 1; ++ } else { ++ depctl.b.setd0pid = 1; ++ } ++ } + } + + /* EP enable */ + depctl.b.cnak = 1; + depctl.b.epena = 1; + +- dwc_write_reg32(&out_regs->doepctl, depctl.d32); ++ DWC_WRITE_REG32(&out_regs->doepctl, depctl.d32); ++ ++ DWC_DEBUGPL(DBG_PCD, "DOEPCTL=%08x DOEPTSIZ=%08x\n", ++ DWC_READ_REG32(&out_regs->doepctl), ++ DWC_READ_REG32(&out_regs->doeptsiz)); ++ DWC_DEBUGPL(DBG_PCD, "DAINTMSK=%08x GINTMSK=%08x\n", ++ DWC_READ_REG32(&core_if->dev_if-> ++ dev_global_regs->daintmsk), ++ DWC_READ_REG32(&core_if-> ++ core_global_regs->gintmsk)); ++ ++ ++ /* Timer is scheduling only for out bulk transfers for ++ * "Device DDMA OUT NAK Enhancement" feature to inform user ++ * about received data payload in case of timeout ++ */ ++ if (core_if->core_params->dev_out_nak) { ++ if (ep->type == DWC_OTG_EP_TYPE_BULK) { ++ core_if->ep_xfer_info[ep->num].core_if = core_if; ++ core_if->ep_xfer_info[ep->num].ep = ep; ++ core_if->ep_xfer_info[ep->num].state = 1; + +- DWC_DEBUGPL(DBG_PCD, "DOEPCTL=%08x DOEPTSIZ=%08x\n", +- dwc_read_reg32(&out_regs->doepctl), +- dwc_read_reg32(&out_regs->doeptsiz)); +- DWC_DEBUGPL(DBG_PCD, "DAINTMSK=%08x GINTMSK=%08x\n", +- dwc_read_reg32(&core_if->dev_if->dev_global_regs-> +- daintmsk), +- dwc_read_reg32(&core_if->core_global_regs-> +- gintmsk)); ++ /* Start a timer for this transfer. */ ++ DWC_TIMER_SCHEDULE(core_if->ep_xfer_timer[ep->num], 10000); ++ } ++ } + } + } + +@@ -2700,8 +3967,8 @@ + dwc_otg_dev_in_ep_regs_t *in_regs = + core_if->dev_if->in_ep_regs[ep->num]; + +- depctl.d32 = dwc_read_reg32(&(in_regs->diepctl)); +- deptsiz.d32 = dwc_read_reg32(&(in_regs->dieptsiz)); ++ depctl.d32 = DWC_READ_REG32(&(in_regs->diepctl)); ++ deptsiz.d32 = DWC_READ_REG32(&(in_regs->dieptsiz)); + + deptsiz.b.xfersize = 0; + deptsiz.b.pktcnt = 1; +@@ -2709,54 +3976,50 @@ + /* Write the DMA register */ + if (core_if->dma_enable) { + if (core_if->dma_desc_enable == 0) { +- dwc_write_reg32(&in_regs->dieptsiz, ++ deptsiz.b.mc = 1; ++ DWC_WRITE_REG32(&in_regs->dieptsiz, + deptsiz.d32); +- dwc_write_reg32(&(in_regs->diepdma), ++ DWC_WRITE_REG32(&(in_regs->diepdma), + (uint32_t) ep->dma_addr); + } + } else { +- dwc_write_reg32(&in_regs->dieptsiz, deptsiz.d32); +- /** ++ DWC_WRITE_REG32(&in_regs->dieptsiz, deptsiz.d32); ++ /** + * Enable the Non-Periodic Tx FIFO empty interrupt, + * or the Tx FIFO epmty interrupt in dedicated Tx FIFO mode, + * the data will be written into the fifo by the ISR. + */ + if (core_if->en_multiple_tx_fifo == 0) { + intr_mask.b.nptxfempty = 1; +- dwc_modify_reg32(&core_if->core_global_regs-> +- gintmsk, intr_mask.d32, +- intr_mask.d32); ++ DWC_MODIFY_REG32(&core_if-> ++ core_global_regs->gintmsk, ++ intr_mask.d32, intr_mask.d32); + } else { + /* Enable the Tx FIFO Empty Interrupt for this EP */ + if (ep->xfer_len > 0) { + uint32_t fifoemptymsk = 0; + fifoemptymsk = 1 << ep->num; +- dwc_modify_reg32(&core_if->dev_if-> +- dev_global_regs-> +- dtknqr4_fifoemptymsk, ++ DWC_MODIFY_REG32(&core_if-> ++ dev_if->dev_global_regs->dtknqr4_fifoemptymsk, + 0, fifoemptymsk); + } + } + } + ++ if (!core_if->core_params->en_multiple_tx_fifo && core_if->dma_enable) ++ depctl.b.nextep = core_if->nextep_seq[ep->num]; + /* EP enable, IN data in FIFO */ + depctl.b.cnak = 1; + depctl.b.epena = 1; +- dwc_write_reg32(&in_regs->diepctl, depctl.d32); +- +- depctl.d32 = +- dwc_read_reg32(&core_if->dev_if->in_ep_regs[0]->diepctl); +- depctl.b.nextep = ep->num; +- dwc_write_reg32(&core_if->dev_if->in_ep_regs[0]->diepctl, +- depctl.d32); ++ DWC_WRITE_REG32(&in_regs->diepctl, depctl.d32); + + } else { + /* OUT endpoint */ + dwc_otg_dev_out_ep_regs_t *out_regs = + core_if->dev_if->out_ep_regs[ep->num]; + +- depctl.d32 = dwc_read_reg32(&(out_regs->doepctl)); +- deptsiz.d32 = dwc_read_reg32(&(out_regs->doeptsiz)); ++ depctl.d32 = DWC_READ_REG32(&(out_regs->doepctl)); ++ deptsiz.d32 = DWC_READ_REG32(&(out_regs->doeptsiz)); + + /* Zero Length Packet */ + deptsiz.b.xfersize = ep->maxpacket; +@@ -2764,21 +4027,21 @@ + + if (core_if->dma_enable) { + if (!core_if->dma_desc_enable) { +- dwc_write_reg32(&out_regs->doeptsiz, ++ DWC_WRITE_REG32(&out_regs->doeptsiz, + deptsiz.d32); + +- dwc_write_reg32(&(out_regs->doepdma), ++ DWC_WRITE_REG32(&(out_regs->doepdma), + (uint32_t) ep->dma_addr); + } + } else { +- dwc_write_reg32(&out_regs->doeptsiz, deptsiz.d32); ++ DWC_WRITE_REG32(&out_regs->doeptsiz, deptsiz.d32); + } + + /* EP enable */ + depctl.b.cnak = 1; + depctl.b.epena = 1; + +- dwc_write_reg32(&out_regs->doepctl, depctl.d32); ++ DWC_WRITE_REG32(&out_regs->doepctl, depctl.d32); + + } + } +@@ -2814,14 +4077,15 @@ + gnptxsts_data_t gtxstatus; + + gtxstatus.d32 = +- dwc_read_reg32(&core_if->core_global_regs->gnptxsts); ++ DWC_READ_REG32(&core_if->core_global_regs->gnptxsts); + + if (core_if->en_multiple_tx_fifo == 0 +- && gtxstatus.b.nptxqspcavail == 0) { ++ && gtxstatus.b.nptxqspcavail == 0 ++ && !core_if->dma_enable) { + #ifdef DEBUG +- deptsiz.d32 = dwc_read_reg32(&in_regs->dieptsiz); ++ deptsiz.d32 = DWC_READ_REG32(&in_regs->dieptsiz); + DWC_DEBUGPL(DBG_PCD, "DIEPCTL0=%0x\n", +- dwc_read_reg32(&in_regs->diepctl)); ++ DWC_READ_REG32(&in_regs->diepctl)); + DWC_DEBUGPL(DBG_PCD, "DIEPTSIZ0=%0x (sz=%d, pcnt=%d)\n", + deptsiz.d32, + deptsiz.b.xfersize, deptsiz.b.pktcnt); +@@ -2831,8 +4095,8 @@ + return; + } + +- depctl.d32 = dwc_read_reg32(&in_regs->diepctl); +- deptsiz.d32 = dwc_read_reg32(&in_regs->dieptsiz); ++ depctl.d32 = DWC_READ_REG32(&in_regs->diepctl); ++ deptsiz.d32 = DWC_READ_REG32(&in_regs->dieptsiz); + + /* Zero Length Packet? */ + if (ep->xfer_len == 0) { +@@ -2842,7 +4106,7 @@ + /* Program the transfer size and packet count + * as follows: xfersize = N * maxpacket + + * short_packet pktcnt = N + (short_packet +- * exist ? 1 : 0) ++ * exist ? 1 : 0) + */ + if (ep->xfer_len > ep->maxpacket) { + ep->xfer_len = ep->maxpacket; +@@ -2861,10 +4125,10 @@ + /* Write the DMA register */ + if (core_if->dma_enable) { + if (core_if->dma_desc_enable == 0) { +- dwc_write_reg32(&in_regs->dieptsiz, ++ DWC_WRITE_REG32(&in_regs->dieptsiz, + deptsiz.d32); + +- dwc_write_reg32(&(in_regs->diepdma), ++ DWC_WRITE_REG32(&(in_regs->diepdma), + (uint32_t) ep->dma_addr); + } else { + dma_desc = core_if->dev_if->in_desc_addr; +@@ -2877,40 +4141,42 @@ + (ep->xfer_len == ep->maxpacket) ? 0 : 1; + dma_desc->status.b.bytes = ep->xfer_len; + dma_desc->buf = ep->dma_addr; ++ dma_desc->status.b.sts = 0; + dma_desc->status.b.bs = BS_HOST_READY; + + /** DIEPDMA0 Register write */ +- dwc_write_reg32(&in_regs->diepdma, +- core_if->dev_if-> +- dma_in_desc_addr); ++ DWC_WRITE_REG32(&in_regs->diepdma, ++ core_if-> ++ dev_if->dma_in_desc_addr); + } + } else { +- dwc_write_reg32(&in_regs->dieptsiz, deptsiz.d32); ++ DWC_WRITE_REG32(&in_regs->dieptsiz, deptsiz.d32); + } + ++ if (!core_if->core_params->en_multiple_tx_fifo && core_if->dma_enable) ++ depctl.b.nextep = core_if->nextep_seq[ep->num]; + /* EP enable, IN data in FIFO */ + depctl.b.cnak = 1; + depctl.b.epena = 1; +- dwc_write_reg32(&in_regs->diepctl, depctl.d32); ++ DWC_WRITE_REG32(&in_regs->diepctl, depctl.d32); + +- /** ++ /** + * Enable the Non-Periodic Tx FIFO empty interrupt, the + * data will be written into the fifo by the ISR. + */ + if (!core_if->dma_enable) { + if (core_if->en_multiple_tx_fifo == 0) { + intr_mask.b.nptxfempty = 1; +- dwc_modify_reg32(&core_if->core_global_regs-> +- gintmsk, intr_mask.d32, +- intr_mask.d32); ++ DWC_MODIFY_REG32(&core_if-> ++ core_global_regs->gintmsk, ++ intr_mask.d32, intr_mask.d32); + } else { + /* Enable the Tx FIFO Empty Interrupt for this EP */ + if (ep->xfer_len > 0) { + uint32_t fifoemptymsk = 0; + fifoemptymsk |= 1 << ep->num; +- dwc_modify_reg32(&core_if->dev_if-> +- dev_global_regs-> +- dtknqr4_fifoemptymsk, ++ DWC_MODIFY_REG32(&core_if-> ++ dev_if->dev_global_regs->dtknqr4_fifoemptymsk, + 0, fifoemptymsk); + } + } +@@ -2920,8 +4186,8 @@ + dwc_otg_dev_out_ep_regs_t *out_regs = + core_if->dev_if->out_ep_regs[0]; + +- depctl.d32 = dwc_read_reg32(&out_regs->doepctl); +- deptsiz.d32 = dwc_read_reg32(&out_regs->doeptsiz); ++ depctl.d32 = DWC_READ_REG32(&out_regs->doepctl); ++ deptsiz.d32 = DWC_READ_REG32(&out_regs->doeptsiz); + + /* Program the transfer size and packet count as follows: + * xfersize = N * (maxpacket + 4 - (maxpacket % 4)) +@@ -2935,10 +4201,10 @@ + + if (core_if->dma_enable) { + if (!core_if->dma_desc_enable) { +- dwc_write_reg32(&out_regs->doeptsiz, ++ DWC_WRITE_REG32(&out_regs->doeptsiz, + deptsiz.d32); + +- dwc_write_reg32(&(out_regs->doepdma), ++ DWC_WRITE_REG32(&(out_regs->doepdma), + (uint32_t) ep->dma_addr); + } else { + dma_desc = core_if->dev_if->out_desc_addr; +@@ -2949,21 +4215,22 @@ + dma_desc->status.b.ioc = 1; + dma_desc->status.b.bytes = ep->maxpacket; + dma_desc->buf = ep->dma_addr; ++ dma_desc->status.b.sts = 0; + dma_desc->status.b.bs = BS_HOST_READY; + + /** DOEPDMA0 Register write */ +- dwc_write_reg32(&out_regs->doepdma, +- core_if->dev_if-> +- dma_out_desc_addr); ++ DWC_WRITE_REG32(&out_regs->doepdma, ++ core_if-> ++ dev_if->dma_out_desc_addr); + } + } else { +- dwc_write_reg32(&out_regs->doeptsiz, deptsiz.d32); ++ DWC_WRITE_REG32(&out_regs->doeptsiz, deptsiz.d32); + } + + /* EP enable */ + depctl.b.cnak = 1; + depctl.b.epena = 1; +- dwc_write_reg32(&(out_regs->doepctl), depctl.d32); ++ DWC_WRITE_REG32(&(out_regs->doepctl), depctl.d32); + } + } + +@@ -2989,17 +4256,17 @@ + gnptxsts_data_t tx_status = {.d32 = 0 }; + + tx_status.d32 = +- dwc_read_reg32(&core_if->core_global_regs->gnptxsts); ++ DWC_READ_REG32(&core_if->core_global_regs->gnptxsts); + /** @todo Should there be check for room in the Tx + * Status Queue. If not remove the code above this comment. */ + +- depctl.d32 = dwc_read_reg32(&in_regs->diepctl); +- deptsiz.d32 = dwc_read_reg32(&in_regs->dieptsiz); ++ depctl.d32 = DWC_READ_REG32(&in_regs->diepctl); ++ deptsiz.d32 = DWC_READ_REG32(&in_regs->dieptsiz); + + /* Program the transfer size and packet count + * as follows: xfersize = N * maxpacket + + * short_packet pktcnt = N + (short_packet +- * exist ? 1 : 0) ++ * exist ? 1 : 0) + */ + + if (core_if->dma_desc_enable == 0) { +@@ -3013,7 +4280,7 @@ + } else { + ep->xfer_len = deptsiz.b.xfersize; + } +- dwc_write_reg32(&in_regs->dieptsiz, deptsiz.d32); ++ DWC_WRITE_REG32(&in_regs->dieptsiz, deptsiz.d32); + } else { + ep->xfer_len = + (ep->total_len - ep->xfer_count) > +@@ -3030,10 +4297,11 @@ + (ep->xfer_len == ep->maxpacket) ? 0 : 1; + dma_desc->status.b.bytes = ep->xfer_len; + dma_desc->buf = ep->dma_addr; ++ dma_desc->status.b.sts = 0; + dma_desc->status.b.bs = BS_HOST_READY; + + /** DIEPDMA0 Register write */ +- dwc_write_reg32(&in_regs->diepdma, ++ DWC_WRITE_REG32(&in_regs->diepdma, + core_if->dev_if->dma_in_desc_addr); + } + +@@ -3045,16 +4313,17 @@ + /* Write the DMA register */ + if (core_if->hwcfg2.b.architecture == DWC_INT_DMA_ARCH) { + if (core_if->dma_desc_enable == 0) +- dwc_write_reg32(&(in_regs->diepdma), ++ DWC_WRITE_REG32(&(in_regs->diepdma), + (uint32_t) ep->dma_addr); + } +- ++ if (!core_if->core_params->en_multiple_tx_fifo && core_if->dma_enable) ++ depctl.b.nextep = core_if->nextep_seq[ep->num]; + /* EP enable, IN data in FIFO */ + depctl.b.cnak = 1; + depctl.b.epena = 1; +- dwc_write_reg32(&in_regs->diepctl, depctl.d32); ++ DWC_WRITE_REG32(&in_regs->diepctl, depctl.d32); + +- /** ++ /** + * Enable the Non-Periodic Tx FIFO empty interrupt, the + * data will be written into the fifo by the ISR. + */ +@@ -3062,18 +4331,17 @@ + if (core_if->en_multiple_tx_fifo == 0) { + /* First clear it from GINTSTS */ + intr_mask.b.nptxfempty = 1; +- dwc_modify_reg32(&core_if->core_global_regs-> +- gintmsk, intr_mask.d32, +- intr_mask.d32); ++ DWC_MODIFY_REG32(&core_if-> ++ core_global_regs->gintmsk, ++ intr_mask.d32, intr_mask.d32); + + } else { + /* Enable the Tx FIFO Empty Interrupt for this EP */ + if (ep->xfer_len > 0) { + uint32_t fifoemptymsk = 0; + fifoemptymsk |= 1 << ep->num; +- dwc_modify_reg32(&core_if->dev_if-> +- dev_global_regs-> +- dtknqr4_fifoemptymsk, ++ DWC_MODIFY_REG32(&core_if-> ++ dev_if->dev_global_regs->dtknqr4_fifoemptymsk, + 0, fifoemptymsk); + } + } +@@ -3082,19 +4350,19 @@ + dwc_otg_dev_out_ep_regs_t *out_regs = + core_if->dev_if->out_ep_regs[0]; + +- depctl.d32 = dwc_read_reg32(&out_regs->doepctl); +- deptsiz.d32 = dwc_read_reg32(&out_regs->doeptsiz); ++ depctl.d32 = DWC_READ_REG32(&out_regs->doepctl); ++ deptsiz.d32 = DWC_READ_REG32(&out_regs->doeptsiz); + + /* Program the transfer size and packet count + * as follows: xfersize = N * maxpacket + + * short_packet pktcnt = N + (short_packet +- * exist ? 1 : 0) ++ * exist ? 1 : 0) + */ + deptsiz.b.xfersize = ep->maxpacket; + deptsiz.b.pktcnt = 1; + + if (core_if->dma_desc_enable == 0) { +- dwc_write_reg32(&out_regs->doeptsiz, deptsiz.d32); ++ DWC_WRITE_REG32(&out_regs->doeptsiz, deptsiz.d32); + } else { + dma_desc = core_if->dev_if->out_desc_addr; + +@@ -3104,10 +4372,11 @@ + dma_desc->status.b.ioc = 1; + dma_desc->status.b.bytes = ep->maxpacket; + dma_desc->buf = ep->dma_addr; ++ dma_desc->status.b.sts = 0; + dma_desc->status.b.bs = BS_HOST_READY; + + /** DOEPDMA0 Register write */ +- dwc_write_reg32(&out_regs->doepdma, ++ DWC_WRITE_REG32(&out_regs->doepdma, + core_if->dev_if->dma_out_desc_addr); + } + +@@ -3119,14 +4388,15 @@ + /* Write the DMA register */ + if (core_if->hwcfg2.b.architecture == DWC_INT_DMA_ARCH) { + if (core_if->dma_desc_enable == 0) +- dwc_write_reg32(&(out_regs->doepdma), ++ DWC_WRITE_REG32(&(out_regs->doepdma), + (uint32_t) ep->dma_addr); ++ + } + + /* EP enable, IN data in FIFO */ + depctl.b.cnak = 1; + depctl.b.epena = 1; +- dwc_write_reg32(&out_regs->doepctl, depctl.d32); ++ DWC_WRITE_REG32(&out_regs->doepctl, depctl.d32); + + } + } +@@ -3164,7 +4434,7 @@ + + /** + * This function writes a packet into the Tx FIFO associated with the +- * EP. For non-periodic EPs the non-periodic Tx FIFO is written. For ++ * EP. For non-periodic EPs the non-periodic Tx FIFO is written. For + * periodic EPs the periodic Tx FIFO associated with the EP is written + * with all packets for the next micro-frame. + * +@@ -3177,15 +4447,15 @@ + { + /** + * The buffer is padded to DWORD on a per packet basis in +- * slave/dma mode if the MPS is not DWORD aligned. The last ++ * slave/dma mode if the MPS is not DWORD aligned. The last + * packet, if short, is also padded to a multiple of DWORD. + * +- * ep->xfer_buff always starts DWORD aligned in memory and is a ++ * ep->xfer_buff always starts DWORD aligned in memory and is a + * multiple of DWORD in length + * + * ep->xfer_len can be any number of bytes + * +- * ep->xfer_count is a multiple of ep->maxpacket until the last ++ * ep->xfer_count is a multiple of ep->maxpacket until the last + * packet + * + * FIFO access is DWORD */ +@@ -3228,7 +4498,7 @@ + + if (!dma) { + for (i = 0; i < dword_count; i++, data_buff++) { +- dwc_write_reg32(fifo, *data_buff); ++ DWC_WRITE_REG32(fifo, *data_buff); + } + } + +@@ -3237,7 +4507,7 @@ + ep->dma_addr += byte_count; + } + +-/** ++/** + * Set the EP STALL. + * + * @param core_if Programming view of DWC_otg controller. +@@ -3253,29 +4523,29 @@ + + if (ep->is_in == 1) { + depctl_addr = &(core_if->dev_if->in_ep_regs[ep->num]->diepctl); +- depctl.d32 = dwc_read_reg32(depctl_addr); ++ depctl.d32 = DWC_READ_REG32(depctl_addr); + + /* set the disable and stall bits */ + if (depctl.b.epena) { + depctl.b.epdis = 1; + } + depctl.b.stall = 1; +- dwc_write_reg32(depctl_addr, depctl.d32); ++ DWC_WRITE_REG32(depctl_addr, depctl.d32); + } else { + depctl_addr = &(core_if->dev_if->out_ep_regs[ep->num]->doepctl); +- depctl.d32 = dwc_read_reg32(depctl_addr); ++ depctl.d32 = DWC_READ_REG32(depctl_addr); + + /* set the stall bit */ + depctl.b.stall = 1; +- dwc_write_reg32(depctl_addr, depctl.d32); ++ DWC_WRITE_REG32(depctl_addr, depctl.d32); + } + +- DWC_DEBUGPL(DBG_PCD, "DEPCTL=%0x\n", dwc_read_reg32(depctl_addr)); ++ DWC_DEBUGPL(DBG_PCD, "DEPCTL=%0x\n", DWC_READ_REG32(depctl_addr)); + + return; + } + +-/** ++/** + * Clear the EP STALL. + * + * @param core_if Programming view of DWC_otg controller. +@@ -3295,12 +4565,12 @@ + depctl_addr = &(core_if->dev_if->out_ep_regs[ep->num]->doepctl); + } + +- depctl.d32 = dwc_read_reg32(depctl_addr); ++ depctl.d32 = DWC_READ_REG32(depctl_addr); + + /* clear the stall bits */ + depctl.b.stall = 0; + +- /* ++ /* + * USB Spec 9.4.5: For endpoints using data toggle, regardless + * of whether an endpoint has the Halt feature set, a + * ClearFeature(ENDPOINT_HALT) request always results in the +@@ -3311,14 +4581,14 @@ + depctl.b.setd0pid = 1; /* DATA0 */ + } + +- dwc_write_reg32(depctl_addr, depctl.d32); +- DWC_DEBUGPL(DBG_PCD, "DEPCTL=%0x\n", dwc_read_reg32(depctl_addr)); ++ DWC_WRITE_REG32(depctl_addr, depctl.d32); ++ DWC_DEBUGPL(DBG_PCD, "DEPCTL=%0x\n", DWC_READ_REG32(depctl_addr)); + return; + } + +-/** ++/** + * This function reads a packet from the Rx FIFO into the destination +- * buffer. To read SETUP data use dwc_otg_read_setup_packet. ++ * buffer. To read SETUP data use dwc_otg_read_setup_packet. + * + * @param core_if Programming view of DWC_otg controller. + * @param dest Destination buffer for the packet. +@@ -3343,7 +4613,7 @@ + core_if, dest, bytes); + + for (i = 0; i < word_count; i++, data_buff++) { +- *data_buff = dwc_read_reg32(fifo); ++ *data_buff = DWC_READ_REG32(fifo); + } + + return; +@@ -3361,119 +4631,125 @@ + + DWC_PRINTF("Device Global Registers\n"); + addr = &core_if->dev_if->dev_global_regs->dcfg; +- DWC_PRINTF("DCFG @0x%08X : 0x%08X\n", (uint32_t) addr, +- dwc_read_reg32(addr)); ++ DWC_PRINTF("DCFG @0x%08lX : 0x%08X\n", (unsigned long) addr, ++ DWC_READ_REG32(addr)); + addr = &core_if->dev_if->dev_global_regs->dctl; +- DWC_PRINTF("DCTL @0x%08X : 0x%08X\n", (uint32_t) addr, +- dwc_read_reg32(addr)); ++ DWC_PRINTF("DCTL @0x%08lX : 0x%08X\n", (unsigned long) addr, ++ DWC_READ_REG32(addr)); + addr = &core_if->dev_if->dev_global_regs->dsts; +- DWC_PRINTF("DSTS @0x%08X : 0x%08X\n", (uint32_t) addr, +- dwc_read_reg32(addr)); ++ DWC_PRINTF("DSTS @0x%08lX : 0x%08X\n", (unsigned long) addr, ++ DWC_READ_REG32(addr)); + addr = &core_if->dev_if->dev_global_regs->diepmsk; +- DWC_PRINTF("DIEPMSK @0x%08X : 0x%08X\n", (uint32_t) addr, +- dwc_read_reg32(addr)); ++ DWC_PRINTF("DIEPMSK @0x%08lX : 0x%08X\n", (unsigned long)addr, ++ DWC_READ_REG32(addr)); + addr = &core_if->dev_if->dev_global_regs->doepmsk; +- DWC_PRINTF("DOEPMSK @0x%08X : 0x%08X\n", (uint32_t) addr, +- dwc_read_reg32(addr)); ++ DWC_PRINTF("DOEPMSK @0x%08lX : 0x%08X\n", (unsigned long)addr, ++ DWC_READ_REG32(addr)); + addr = &core_if->dev_if->dev_global_regs->daint; +- DWC_PRINTF("DAINT @0x%08X : 0x%08X\n", (uint32_t) addr, +- dwc_read_reg32(addr)); ++ DWC_PRINTF("DAINT @0x%08lX : 0x%08X\n", (unsigned long)addr, ++ DWC_READ_REG32(addr)); + addr = &core_if->dev_if->dev_global_regs->daintmsk; +- DWC_PRINTF("DAINTMSK @0x%08X : 0x%08X\n", (uint32_t) addr, +- dwc_read_reg32(addr)); ++ DWC_PRINTF("DAINTMSK @0x%08lX : 0x%08X\n", (unsigned long)addr, ++ DWC_READ_REG32(addr)); + addr = &core_if->dev_if->dev_global_regs->dtknqr1; +- DWC_PRINTF("DTKNQR1 @0x%08X : 0x%08X\n", (uint32_t) addr, +- dwc_read_reg32(addr)); ++ DWC_PRINTF("DTKNQR1 @0x%08lX : 0x%08X\n", (unsigned long)addr, ++ DWC_READ_REG32(addr)); + if (core_if->hwcfg2.b.dev_token_q_depth > 6) { + addr = &core_if->dev_if->dev_global_regs->dtknqr2; +- DWC_PRINTF("DTKNQR2 @0x%08X : 0x%08X\n", +- (uint32_t) addr, dwc_read_reg32(addr)); ++ DWC_PRINTF("DTKNQR2 @0x%08lX : 0x%08X\n", ++ (unsigned long)addr, DWC_READ_REG32(addr)); + } + + addr = &core_if->dev_if->dev_global_regs->dvbusdis; +- DWC_PRINTF("DVBUSID @0x%08X : 0x%08X\n", (uint32_t) addr, +- dwc_read_reg32(addr)); ++ DWC_PRINTF("DVBUSID @0x%08lX : 0x%08X\n", (unsigned long)addr, ++ DWC_READ_REG32(addr)); + + addr = &core_if->dev_if->dev_global_regs->dvbuspulse; +- DWC_PRINTF("DVBUSPULSE @0x%08X : 0x%08X\n", +- (uint32_t) addr, dwc_read_reg32(addr)); ++ DWC_PRINTF("DVBUSPULSE @0x%08lX : 0x%08X\n", ++ (unsigned long)addr, DWC_READ_REG32(addr)); + +- addr = &core_if->dev_if->dev_global_regs->dtknqr3_dthrctl; +- DWC_PRINTF("DTKNQR3_DTHRCTL @0x%08X : 0x%08X\n", +- (uint32_t) addr, dwc_read_reg32(addr)); ++ addr = &core_if->dev_if->dev_global_regs->dtknqr3_dthrctl; ++ DWC_PRINTF("DTKNQR3_DTHRCTL @0x%08lX : 0x%08X\n", ++ (unsigned long)addr, DWC_READ_REG32(addr)); + + if (core_if->hwcfg2.b.dev_token_q_depth > 22) { + addr = &core_if->dev_if->dev_global_regs->dtknqr4_fifoemptymsk; +- DWC_PRINTF("DTKNQR4 @0x%08X : 0x%08X\n", +- (uint32_t) addr, dwc_read_reg32(addr)); ++ DWC_PRINTF("DTKNQR4 @0x%08lX : 0x%08X\n", ++ (unsigned long)addr, DWC_READ_REG32(addr)); + } + + addr = &core_if->dev_if->dev_global_regs->dtknqr4_fifoemptymsk; +- DWC_PRINTF("FIFOEMPMSK @0x%08X : 0x%08X\n", (uint32_t) addr, +- dwc_read_reg32(addr)); +- +- addr = &core_if->dev_if->dev_global_regs->deachint; +- DWC_PRINTF("DEACHINT @0x%08X : 0x%08X\n", (uint32_t) addr, +- dwc_read_reg32(addr)); +- addr = &core_if->dev_if->dev_global_regs->deachintmsk; +- DWC_PRINTF("DEACHINTMSK @0x%08X : 0x%08X\n", (uint32_t) addr, +- dwc_read_reg32(addr)); ++ DWC_PRINTF("FIFOEMPMSK @0x%08lX : 0x%08X\n", (unsigned long)addr, ++ DWC_READ_REG32(addr)); + +- for (i = 0; i <= core_if->dev_if->num_in_eps; i++) { +- addr = &core_if->dev_if->dev_global_regs->diepeachintmsk[i]; +- DWC_PRINTF("DIEPEACHINTMSK[%d] @0x%08X : 0x%08X\n", i, +- (uint32_t) addr, dwc_read_reg32(addr)); +- } ++ if (core_if->hwcfg2.b.multi_proc_int) { + +- for (i = 0; i <= core_if->dev_if->num_out_eps; i++) { +- addr = &core_if->dev_if->dev_global_regs->doepeachintmsk[i]; +- DWC_PRINTF("DOEPEACHINTMSK[%d] @0x%08X : 0x%08X\n", i, +- (uint32_t) addr, dwc_read_reg32(addr)); ++ addr = &core_if->dev_if->dev_global_regs->deachint; ++ DWC_PRINTF("DEACHINT @0x%08lX : 0x%08X\n", ++ (unsigned long)addr, DWC_READ_REG32(addr)); ++ addr = &core_if->dev_if->dev_global_regs->deachintmsk; ++ DWC_PRINTF("DEACHINTMSK @0x%08lX : 0x%08X\n", ++ (unsigned long)addr, DWC_READ_REG32(addr)); ++ ++ for (i = 0; i <= core_if->dev_if->num_in_eps; i++) { ++ addr = ++ &core_if->dev_if->dev_global_regs-> ++ diepeachintmsk[i]; ++ DWC_PRINTF("DIEPEACHINTMSK[%d] @0x%08lX : 0x%08X\n", ++ i, (unsigned long)addr, ++ DWC_READ_REG32(addr)); ++ } ++ ++ for (i = 0; i <= core_if->dev_if->num_out_eps; i++) { ++ addr = ++ &core_if->dev_if->dev_global_regs-> ++ doepeachintmsk[i]; ++ DWC_PRINTF("DOEPEACHINTMSK[%d] @0x%08lX : 0x%08X\n", ++ i, (unsigned long)addr, ++ DWC_READ_REG32(addr)); ++ } + } + + for (i = 0; i <= core_if->dev_if->num_in_eps; i++) { + DWC_PRINTF("Device IN EP %d Registers\n", i); + addr = &core_if->dev_if->in_ep_regs[i]->diepctl; +- DWC_PRINTF("DIEPCTL @0x%08X : 0x%08X\n", (uint32_t) addr, +- dwc_read_reg32(addr)); ++ DWC_PRINTF("DIEPCTL @0x%08lX : 0x%08X\n", ++ (unsigned long)addr, DWC_READ_REG32(addr)); + addr = &core_if->dev_if->in_ep_regs[i]->diepint; +- DWC_PRINTF("DIEPINT @0x%08X : 0x%08X\n", (uint32_t) addr, +- dwc_read_reg32(addr)); ++ DWC_PRINTF("DIEPINT @0x%08lX : 0x%08X\n", ++ (unsigned long)addr, DWC_READ_REG32(addr)); + addr = &core_if->dev_if->in_ep_regs[i]->dieptsiz; +- DWC_PRINTF("DIETSIZ @0x%08X : 0x%08X\n", (uint32_t) addr, +- dwc_read_reg32(addr)); ++ DWC_PRINTF("DIETSIZ @0x%08lX : 0x%08X\n", ++ (unsigned long)addr, DWC_READ_REG32(addr)); + addr = &core_if->dev_if->in_ep_regs[i]->diepdma; +- DWC_PRINTF("DIEPDMA @0x%08X : 0x%08X\n", (uint32_t) addr, +- dwc_read_reg32(addr)); ++ DWC_PRINTF("DIEPDMA @0x%08lX : 0x%08X\n", ++ (unsigned long)addr, DWC_READ_REG32(addr)); + addr = &core_if->dev_if->in_ep_regs[i]->dtxfsts; +- DWC_PRINTF("DTXFSTS @0x%08X : 0x%08X\n", (uint32_t) addr, +- dwc_read_reg32(addr)); ++ DWC_PRINTF("DTXFSTS @0x%08lX : 0x%08X\n", ++ (unsigned long)addr, DWC_READ_REG32(addr)); + addr = &core_if->dev_if->in_ep_regs[i]->diepdmab; +- DWC_PRINTF("DIEPDMAB @0x%08X : 0x%08X\n", (uint32_t) addr, +- 0 /*dwc_read_reg32(addr) */ ); ++ DWC_PRINTF("DIEPDMAB @0x%08lX : 0x%08X\n", ++ (unsigned long)addr, 0 /*DWC_READ_REG32(addr) */ ); + } + + for (i = 0; i <= core_if->dev_if->num_out_eps; i++) { + DWC_PRINTF("Device OUT EP %d Registers\n", i); + addr = &core_if->dev_if->out_ep_regs[i]->doepctl; +- DWC_PRINTF("DOEPCTL @0x%08X : 0x%08X\n", (uint32_t) addr, +- dwc_read_reg32(addr)); +- addr = &core_if->dev_if->out_ep_regs[i]->doepfn; +- DWC_PRINTF("DOEPFN @0x%08X : 0x%08X\n", (uint32_t) addr, +- dwc_read_reg32(addr)); ++ DWC_PRINTF("DOEPCTL @0x%08lX : 0x%08X\n", ++ (unsigned long)addr, DWC_READ_REG32(addr)); + addr = &core_if->dev_if->out_ep_regs[i]->doepint; +- DWC_PRINTF("DOEPINT @0x%08X : 0x%08X\n", (uint32_t) addr, +- dwc_read_reg32(addr)); ++ DWC_PRINTF("DOEPINT @0x%08lX : 0x%08X\n", ++ (unsigned long)addr, DWC_READ_REG32(addr)); + addr = &core_if->dev_if->out_ep_regs[i]->doeptsiz; +- DWC_PRINTF("DOETSIZ @0x%08X : 0x%08X\n", (uint32_t) addr, +- dwc_read_reg32(addr)); ++ DWC_PRINTF("DOETSIZ @0x%08lX : 0x%08X\n", ++ (unsigned long)addr, DWC_READ_REG32(addr)); + addr = &core_if->dev_if->out_ep_regs[i]->doepdma; +- DWC_PRINTF("DOEPDMA @0x%08X : 0x%08X\n", (uint32_t) addr, +- dwc_read_reg32(addr)); ++ DWC_PRINTF("DOEPDMA @0x%08lX : 0x%08X\n", ++ (unsigned long)addr, DWC_READ_REG32(addr)); + if (core_if->dma_enable) { /* Don't access this register in SLAVE mode */ + addr = &core_if->dev_if->out_ep_regs[i]->doepdmab; +- DWC_PRINTF("DOEPDMAB @0x%08X : 0x%08X\n", +- (uint32_t) addr, dwc_read_reg32(addr)); ++ DWC_PRINTF("DOEPDMAB @0x%08lX : 0x%08X\n", ++ (unsigned long)addr, DWC_READ_REG32(addr)); + } + + } +@@ -3490,15 +4766,15 @@ + + DWC_PRINTF("SPRAM Data:\n"); + start_addr = (void *)core_if->core_global_regs; +- DWC_PRINTF("Base Address: 0x%8X\n", (uint32_t) start_addr); ++ DWC_PRINTF("Base Address: 0x%8lX\n", (unsigned long)start_addr); + start_addr += 0x00028000; + end_addr = (void *)core_if->core_global_regs; + end_addr += 0x000280e0; + + for (addr = start_addr; addr < end_addr; addr += 16) { + DWC_PRINTF +- ("0x%8X:\t%2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X\n", +- (uint32_t) addr, addr[0], addr[1], addr[2], addr[3], ++ ("0x%8lX:\t%2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X\n", ++ (unsigned long)addr, addr[0], addr[1], addr[2], addr[3], + addr[4], addr[5], addr[6], addr[7], addr[8], addr[9], + addr[10], addr[11], addr[12], addr[13], addr[14], addr[15] + ); +@@ -3519,57 +4795,58 @@ + + DWC_PRINTF("Host Global Registers\n"); + addr = &core_if->host_if->host_global_regs->hcfg; +- DWC_PRINTF("HCFG @0x%08X : 0x%08X\n", (uint32_t) addr, +- dwc_read_reg32(addr)); ++ DWC_PRINTF("HCFG @0x%08lX : 0x%08X\n", ++ (unsigned long)addr, DWC_READ_REG32(addr)); + addr = &core_if->host_if->host_global_regs->hfir; +- DWC_PRINTF("HFIR @0x%08X : 0x%08X\n", (uint32_t) addr, +- dwc_read_reg32(addr)); ++ DWC_PRINTF("HFIR @0x%08lX : 0x%08X\n", ++ (unsigned long)addr, DWC_READ_REG32(addr)); + addr = &core_if->host_if->host_global_regs->hfnum; +- DWC_PRINTF("HFNUM @0x%08X : 0x%08X\n", (uint32_t) addr, +- dwc_read_reg32(addr)); ++ DWC_PRINTF("HFNUM @0x%08lX : 0x%08X\n", (unsigned long)addr, ++ DWC_READ_REG32(addr)); + addr = &core_if->host_if->host_global_regs->hptxsts; +- DWC_PRINTF("HPTXSTS @0x%08X : 0x%08X\n", (uint32_t) addr, +- dwc_read_reg32(addr)); ++ DWC_PRINTF("HPTXSTS @0x%08lX : 0x%08X\n", (unsigned long)addr, ++ DWC_READ_REG32(addr)); + addr = &core_if->host_if->host_global_regs->haint; +- DWC_PRINTF("HAINT @0x%08X : 0x%08X\n", (uint32_t) addr, +- dwc_read_reg32(addr)); ++ DWC_PRINTF("HAINT @0x%08lX : 0x%08X\n", (unsigned long)addr, ++ DWC_READ_REG32(addr)); + addr = &core_if->host_if->host_global_regs->haintmsk; +- DWC_PRINTF("HAINTMSK @0x%08X : 0x%08X\n", (uint32_t) addr, +- dwc_read_reg32(addr)); ++ DWC_PRINTF("HAINTMSK @0x%08lX : 0x%08X\n", (unsigned long)addr, ++ DWC_READ_REG32(addr)); + if (core_if->dma_desc_enable) { + addr = &core_if->host_if->host_global_regs->hflbaddr; +- DWC_PRINTF("HFLBADDR @0x%08X : 0x%08X\n",(uint32_t) addr, +- dwc_read_reg32(addr)); ++ DWC_PRINTF("HFLBADDR @0x%08lX : 0x%08X\n", ++ (unsigned long)addr, DWC_READ_REG32(addr)); + } +- ++ + addr = core_if->host_if->hprt0; +- DWC_PRINTF("HPRT0 @0x%08X : 0x%08X\n", (uint32_t) addr, +- dwc_read_reg32(addr)); ++ DWC_PRINTF("HPRT0 @0x%08lX : 0x%08X\n", (unsigned long)addr, ++ DWC_READ_REG32(addr)); + + for (i = 0; i < core_if->core_params->host_channels; i++) { + DWC_PRINTF("Host Channel %d Specific Registers\n", i); + addr = &core_if->host_if->hc_regs[i]->hcchar; +- DWC_PRINTF("HCCHAR @0x%08X : 0x%08X\n", (uint32_t) addr, +- dwc_read_reg32(addr)); ++ DWC_PRINTF("HCCHAR @0x%08lX : 0x%08X\n", ++ (unsigned long)addr, DWC_READ_REG32(addr)); + addr = &core_if->host_if->hc_regs[i]->hcsplt; +- DWC_PRINTF("HCSPLT @0x%08X : 0x%08X\n", (uint32_t) addr, +- dwc_read_reg32(addr)); ++ DWC_PRINTF("HCSPLT @0x%08lX : 0x%08X\n", ++ (unsigned long)addr, DWC_READ_REG32(addr)); + addr = &core_if->host_if->hc_regs[i]->hcint; +- DWC_PRINTF("HCINT @0x%08X : 0x%08X\n", (uint32_t) addr, +- dwc_read_reg32(addr)); ++ DWC_PRINTF("HCINT @0x%08lX : 0x%08X\n", ++ (unsigned long)addr, DWC_READ_REG32(addr)); + addr = &core_if->host_if->hc_regs[i]->hcintmsk; +- DWC_PRINTF("HCINTMSK @0x%08X : 0x%08X\n", (uint32_t) addr, +- dwc_read_reg32(addr)); ++ DWC_PRINTF("HCINTMSK @0x%08lX : 0x%08X\n", ++ (unsigned long)addr, DWC_READ_REG32(addr)); + addr = &core_if->host_if->hc_regs[i]->hctsiz; +- DWC_PRINTF("HCTSIZ @0x%08X : 0x%08X\n", (uint32_t) addr, +- dwc_read_reg32(addr)); ++ DWC_PRINTF("HCTSIZ @0x%08lX : 0x%08X\n", ++ (unsigned long)addr, DWC_READ_REG32(addr)); + addr = &core_if->host_if->hc_regs[i]->hcdma; +- DWC_PRINTF("HCDMA @0x%08X : 0x%08X\n", (uint32_t) addr, +- dwc_read_reg32(addr)); ++ DWC_PRINTF("HCDMA @0x%08lX : 0x%08X\n", ++ (unsigned long)addr, DWC_READ_REG32(addr)); + if (core_if->dma_desc_enable) { +- addr=&core_if->host_if->hc_regs[i]->hcdmab; +- DWC_PRINTF("HCDMAB @0x%08X : 0x%08X\n",(uint32_t) addr, dwc_read_reg32(addr)); +- } ++ addr = &core_if->host_if->hc_regs[i]->hcdmab; ++ DWC_PRINTF("HCDMAB @0x%08lX : 0x%08X\n", ++ (unsigned long)addr, DWC_READ_REG32(addr)); ++ } + + } + return; +@@ -3582,85 +4859,102 @@ + */ + void dwc_otg_dump_global_registers(dwc_otg_core_if_t * core_if) + { +- int i; ++ int i, ep_num; + volatile uint32_t *addr; ++ char *txfsiz; + + DWC_PRINTF("Core Global Registers\n"); + addr = &core_if->core_global_regs->gotgctl; +- DWC_PRINTF("GOTGCTL @0x%08X : 0x%08X\n", (uint32_t) addr, +- dwc_read_reg32(addr)); ++ DWC_PRINTF("GOTGCTL @0x%08lX : 0x%08X\n", (unsigned long)addr, ++ DWC_READ_REG32(addr)); + addr = &core_if->core_global_regs->gotgint; +- DWC_PRINTF("GOTGINT @0x%08X : 0x%08X\n", (uint32_t) addr, +- dwc_read_reg32(addr)); ++ DWC_PRINTF("GOTGINT @0x%08lX : 0x%08X\n", (unsigned long)addr, ++ DWC_READ_REG32(addr)); + addr = &core_if->core_global_regs->gahbcfg; +- DWC_PRINTF("GAHBCFG @0x%08X : 0x%08X\n", (uint32_t) addr, +- dwc_read_reg32(addr)); ++ DWC_PRINTF("GAHBCFG @0x%08lX : 0x%08X\n", (unsigned long)addr, ++ DWC_READ_REG32(addr)); + addr = &core_if->core_global_regs->gusbcfg; +- DWC_PRINTF("GUSBCFG @0x%08X : 0x%08X\n", (uint32_t) addr, +- dwc_read_reg32(addr)); ++ DWC_PRINTF("GUSBCFG @0x%08lX : 0x%08X\n", (unsigned long)addr, ++ DWC_READ_REG32(addr)); + addr = &core_if->core_global_regs->grstctl; +- DWC_PRINTF("GRSTCTL @0x%08X : 0x%08X\n", (uint32_t) addr, +- dwc_read_reg32(addr)); ++ DWC_PRINTF("GRSTCTL @0x%08lX : 0x%08X\n", (unsigned long)addr, ++ DWC_READ_REG32(addr)); + addr = &core_if->core_global_regs->gintsts; +- DWC_PRINTF("GINTSTS @0x%08X : 0x%08X\n", (uint32_t) addr, +- dwc_read_reg32(addr)); ++ DWC_PRINTF("GINTSTS @0x%08lX : 0x%08X\n", (unsigned long)addr, ++ DWC_READ_REG32(addr)); + addr = &core_if->core_global_regs->gintmsk; +- DWC_PRINTF("GINTMSK @0x%08X : 0x%08X\n", (uint32_t) addr, +- dwc_read_reg32(addr)); ++ DWC_PRINTF("GINTMSK @0x%08lX : 0x%08X\n", (unsigned long)addr, ++ DWC_READ_REG32(addr)); + addr = &core_if->core_global_regs->grxstsr; +- DWC_PRINTF("GRXSTSR @0x%08X : 0x%08X\n", (uint32_t) addr, +- dwc_read_reg32(addr)); ++ DWC_PRINTF("GRXSTSR @0x%08lX : 0x%08X\n", (unsigned long)addr, ++ DWC_READ_REG32(addr)); + addr = &core_if->core_global_regs->grxfsiz; +- DWC_PRINTF("GRXFSIZ @0x%08X : 0x%08X\n", (uint32_t) addr, +- dwc_read_reg32(addr)); ++ DWC_PRINTF("GRXFSIZ @0x%08lX : 0x%08X\n", (unsigned long)addr, ++ DWC_READ_REG32(addr)); + addr = &core_if->core_global_regs->gnptxfsiz; +- DWC_PRINTF("GNPTXFSIZ @0x%08X : 0x%08X\n", (uint32_t) addr, +- dwc_read_reg32(addr)); ++ DWC_PRINTF("GNPTXFSIZ @0x%08lX : 0x%08X\n", (unsigned long)addr, ++ DWC_READ_REG32(addr)); + addr = &core_if->core_global_regs->gnptxsts; +- DWC_PRINTF("GNPTXSTS @0x%08X : 0x%08X\n", (uint32_t) addr, +- dwc_read_reg32(addr)); ++ DWC_PRINTF("GNPTXSTS @0x%08lX : 0x%08X\n", (unsigned long)addr, ++ DWC_READ_REG32(addr)); + addr = &core_if->core_global_regs->gi2cctl; +- DWC_PRINTF("GI2CCTL @0x%08X : 0x%08X\n", (uint32_t) addr, +- dwc_read_reg32(addr)); ++ DWC_PRINTF("GI2CCTL @0x%08lX : 0x%08X\n", (unsigned long)addr, ++ DWC_READ_REG32(addr)); + addr = &core_if->core_global_regs->gpvndctl; +- DWC_PRINTF("GPVNDCTL @0x%08X : 0x%08X\n", (uint32_t) addr, +- dwc_read_reg32(addr)); ++ DWC_PRINTF("GPVNDCTL @0x%08lX : 0x%08X\n", (unsigned long)addr, ++ DWC_READ_REG32(addr)); + addr = &core_if->core_global_regs->ggpio; +- DWC_PRINTF("GGPIO @0x%08X : 0x%08X\n", (uint32_t) addr, +- dwc_read_reg32(addr)); ++ DWC_PRINTF("GGPIO @0x%08lX : 0x%08X\n", (unsigned long)addr, ++ DWC_READ_REG32(addr)); + addr = &core_if->core_global_regs->guid; +- DWC_PRINTF("GUID @0x%08X : 0x%08X\n", (uint32_t) addr, +- dwc_read_reg32(addr)); ++ DWC_PRINTF("GUID @0x%08lX : 0x%08X\n", ++ (unsigned long)addr, DWC_READ_REG32(addr)); + addr = &core_if->core_global_regs->gsnpsid; +- DWC_PRINTF("GSNPSID @0x%08X : 0x%08X\n", (uint32_t) addr, +- dwc_read_reg32(addr)); ++ DWC_PRINTF("GSNPSID @0x%08lX : 0x%08X\n", (unsigned long)addr, ++ DWC_READ_REG32(addr)); + addr = &core_if->core_global_regs->ghwcfg1; +- DWC_PRINTF("GHWCFG1 @0x%08X : 0x%08X\n", (uint32_t) addr, +- dwc_read_reg32(addr)); ++ DWC_PRINTF("GHWCFG1 @0x%08lX : 0x%08X\n", (unsigned long)addr, ++ DWC_READ_REG32(addr)); + addr = &core_if->core_global_regs->ghwcfg2; +- DWC_PRINTF("GHWCFG2 @0x%08X : 0x%08X\n", (uint32_t) addr, +- dwc_read_reg32(addr)); ++ DWC_PRINTF("GHWCFG2 @0x%08lX : 0x%08X\n", (unsigned long)addr, ++ DWC_READ_REG32(addr)); + addr = &core_if->core_global_regs->ghwcfg3; +- DWC_PRINTF("GHWCFG3 @0x%08X : 0x%08X\n", (uint32_t) addr, +- dwc_read_reg32(addr)); ++ DWC_PRINTF("GHWCFG3 @0x%08lX : 0x%08X\n", (unsigned long)addr, ++ DWC_READ_REG32(addr)); + addr = &core_if->core_global_regs->ghwcfg4; +- DWC_PRINTF("GHWCFG4 @0x%08X : 0x%08X\n", (uint32_t) addr, +- dwc_read_reg32(addr)); ++ DWC_PRINTF("GHWCFG4 @0x%08lX : 0x%08X\n", (unsigned long)addr, ++ DWC_READ_REG32(addr)); + addr = &core_if->core_global_regs->glpmcfg; +- DWC_PRINTF("GLPMCFG @0x%08X : 0x%08X\n", (uint32_t) addr, +- dwc_read_reg32(addr)); ++ DWC_PRINTF("GLPMCFG @0x%08lX : 0x%08X\n", (unsigned long)addr, ++ DWC_READ_REG32(addr)); ++ addr = &core_if->core_global_regs->gpwrdn; ++ DWC_PRINTF("GPWRDN @0x%08lX : 0x%08X\n", (unsigned long)addr, ++ DWC_READ_REG32(addr)); ++ addr = &core_if->core_global_regs->gdfifocfg; ++ DWC_PRINTF("GDFIFOCFG @0x%08lX : 0x%08X\n", (unsigned long)addr, ++ DWC_READ_REG32(addr)); ++ addr = &core_if->core_global_regs->adpctl; ++ DWC_PRINTF("ADPCTL @0x%08lX : 0x%08X\n", (unsigned long)addr, ++ dwc_otg_adp_read_reg(core_if)); + addr = &core_if->core_global_regs->hptxfsiz; +- DWC_PRINTF("HPTXFSIZ @0x%08X : 0x%08X\n", (uint32_t) addr, +- dwc_read_reg32(addr)); ++ DWC_PRINTF("HPTXFSIZ @0x%08lX : 0x%08X\n", (unsigned long)addr, ++ DWC_READ_REG32(addr)); + +- for (i = 0; i < core_if->hwcfg4.b.num_dev_perio_in_ep; i++) { +- addr = &core_if->core_global_regs->dptxfsiz_dieptxf[i]; +- DWC_PRINTF("DPTXFSIZ[%d] @0x%08X : 0x%08X\n", i, +- (uint32_t) addr, dwc_read_reg32(addr)); ++ if (core_if->en_multiple_tx_fifo == 0) { ++ ep_num = core_if->hwcfg4.b.num_dev_perio_in_ep; ++ txfsiz = "DPTXFSIZ"; ++ } else { ++ ep_num = core_if->hwcfg4.b.num_in_eps; ++ txfsiz = "DIENPTXF"; ++ } ++ for (i = 0; i < ep_num; i++) { ++ addr = &core_if->core_global_regs->dtxfsiz[i]; ++ DWC_PRINTF("%s[%d] @0x%08lX : 0x%08X\n", txfsiz, i + 1, ++ (unsigned long)addr, DWC_READ_REG32(addr)); + } + addr = core_if->pcgcctl; +- DWC_PRINTF("PCGCCTL @0x%08X : 0x%08X\n", (uint32_t) addr, +- dwc_read_reg32(addr)); ++ DWC_PRINTF("PCGCCTL @0x%08lX : 0x%08X\n", (unsigned long)addr, ++ DWC_READ_REG32(addr)); + } + + /** +@@ -3679,14 +4973,14 @@ + + greset.b.txfflsh = 1; + greset.b.txfnum = num; +- dwc_write_reg32(&global_regs->grstctl, greset.d32); ++ DWC_WRITE_REG32(&global_regs->grstctl, greset.d32); + + do { +- greset.d32 = dwc_read_reg32(&global_regs->grstctl); ++ greset.d32 = DWC_READ_REG32(&global_regs->grstctl); + if (++count > 10000) { + DWC_WARN("%s() HANG! GRSTCTL=%0x GNPTXSTS=0x%08x\n", + __func__, greset.d32, +- dwc_read_reg32(&global_regs->gnptxsts)); ++ DWC_READ_REG32(&global_regs->gnptxsts)); + break; + } + dwc_udelay(1); +@@ -3709,13 +5003,13 @@ + + DWC_DEBUGPL((DBG_CIL | DBG_PCDV), "%s\n", __func__); + /* +- * ++ * + */ + greset.b.rxfflsh = 1; +- dwc_write_reg32(&global_regs->grstctl, greset.d32); ++ DWC_WRITE_REG32(&global_regs->grstctl, greset.d32); + + do { +- greset.d32 = dwc_read_reg32(&global_regs->grstctl); ++ greset.d32 = DWC_READ_REG32(&global_regs->grstctl); + if (++count > 10000) { + DWC_WARN("%s() HANG! GRSTCTL=%0x\n", __func__, + greset.d32); +@@ -3742,7 +5036,7 @@ + /* Wait for AHB master IDLE state. */ + do { + dwc_udelay(10); +- greset.d32 = dwc_read_reg32(&global_regs->grstctl); ++ greset.d32 = DWC_READ_REG32(&global_regs->grstctl); + if (++count > 100000) { + DWC_WARN("%s() HANG! AHB Idle GRSTCTL=%0x\n", __func__, + greset.d32); +@@ -3754,9 +5048,9 @@ + /* Core Soft Reset */ + count = 0; + greset.b.csftrst = 1; +- dwc_write_reg32(&global_regs->grstctl, greset.d32); ++ DWC_WRITE_REG32(&global_regs->grstctl, greset.d32); + do { +- greset.d32 = dwc_read_reg32(&global_regs->grstctl); ++ greset.d32 = DWC_READ_REG32(&global_regs->grstctl); + if (++count > 10000) { + DWC_WARN("%s() HANG! Soft Reset GRSTCTL=%0x\n", + __func__, greset.d32); +@@ -3781,7 +5075,7 @@ + } + + /** +- * Register HCD callbacks. The callbacks are used to start and stop ++ * Register HCD callbacks. The callbacks are used to start and stop + * the HCD for interrupt processing. + * + * @param core_if Programming view of DWC_otg controller. +@@ -3796,7 +5090,7 @@ + } + + /** +- * Register PCD callbacks. The callbacks are used to start and stop ++ * Register PCD callbacks. The callbacks are used to start and stop + * the PCD for interrupt processing. + * + * @param core_if Programming view of DWC_otg controller. +@@ -3842,7 +5136,7 @@ + /* While there is space in the queue and space in the FIFO and + * More data to tranfer, Write packets to the Tx FIFO */ + txstatus.d32 = +- dwc_read_reg32(&core_if->dev_if->in_ep_regs[ep->num]->dtxfsts); ++ DWC_READ_REG32(&core_if->dev_if->in_ep_regs[ep->num]->dtxfsts); + DWC_DEBUGPL(DBG_PCDV, "b4 dtxfsts[%d]=0x%08x\n", ep->num, txstatus.d32); + + while (txstatus.b.txfspcavail > dwords && +@@ -3857,8 +5151,8 @@ + + dwords = (len + 3) / 4; + txstatus.d32 = +- dwc_read_reg32(&core_if->dev_if->in_ep_regs[ep->num]-> +- dtxfsts); ++ DWC_READ_REG32(&core_if->dev_if-> ++ in_ep_regs[ep->num]->dtxfsts); + DWC_DEBUGPL(DBG_PCDV, "dtxfsts[%d]=0x%08x\n", ep->num, + txstatus.d32); + } +@@ -3894,18 +5188,18 @@ + /* Program the transfer size and packet count + * as follows: xfersize = N * maxpacket + + * short_packet pktcnt = N + (short_packet +- * exist ? 1 : 0) ++ * exist ? 1 : 0) + */ + deptsiz.b.xfersize = ep->xfer_len; + deptsiz.b.pktcnt = + (ep->xfer_len - 1 + ep->maxpacket) / ep->maxpacket; + deptsiz.b.mc = deptsiz.b.pktcnt; +- dwc_write_reg32(&core_if->dev_if->in_ep_regs[ep->num]->dieptsiz, ++ DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[ep->num]->dieptsiz, + deptsiz.d32); + + /* Write the DMA register */ + if (core_if->dma_enable) { +- dwc_write_reg32(& ++ DWC_WRITE_REG32(& + (core_if->dev_if->in_ep_regs[ep->num]-> + diepdma), (uint32_t) ep->dma_addr); + } +@@ -3914,11 +5208,11 @@ + (ep->xfer_len + (ep->maxpacket - 1)) / ep->maxpacket; + deptsiz.b.xfersize = deptsiz.b.pktcnt * ep->maxpacket; + +- dwc_write_reg32(&core_if->dev_if->out_ep_regs[ep->num]-> ++ DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[ep->num]-> + doeptsiz, deptsiz.d32); + + if (core_if->dma_enable) { +- dwc_write_reg32(& ++ DWC_WRITE_REG32(& + (core_if->dev_if->out_ep_regs[ep->num]-> + doepdma), (uint32_t) ep->dma_addr); + } +@@ -3929,7 +5223,7 @@ + depctl.d32 = 0; + if (ep->bInterval == 1) { + dsts.d32 = +- dwc_read_reg32(&core_if->dev_if->dev_global_regs->dsts); ++ DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts); + ep->next_frame = dsts.b.soffn + ep->bInterval; + + if (ep->next_frame & 0x1) { +@@ -3949,15 +5243,15 @@ + depctl.b.epena = 1; + depctl.b.cnak = 1; + +- dwc_modify_reg32(addr, 0, depctl.d32); +- depctl.d32 = dwc_read_reg32(addr); ++ DWC_MODIFY_REG32(addr, 0, depctl.d32); ++ depctl.d32 = DWC_READ_REG32(addr); + + if (ep->is_in && core_if->dma_enable == 0) { + write_isoc_frame_data(core_if, ep); + } + + } +-#endif /* DWC_EN_ISOC */ ++#endif /* DWC_EN_ISOC */ + + static void dwc_otg_set_uninitialized(int32_t * p, int size) + { +@@ -4048,8 +5342,17 @@ + dwc_param_tx_thr_length_default); + dwc_otg_set_param_rx_thr_length(core_if, + dwc_param_rx_thr_length_default); +- dwc_otg_set_param_ahb_thr_ratio(core_if, dwc_param_ahb_thr_ratio_default); ++ dwc_otg_set_param_ahb_thr_ratio(core_if, ++ dwc_param_ahb_thr_ratio_default); ++ dwc_otg_set_param_power_down(core_if, dwc_param_power_down_default); ++ dwc_otg_set_param_reload_ctl(core_if, dwc_param_reload_ctl_default); ++ dwc_otg_set_param_dev_out_nak(core_if, dwc_param_dev_out_nak_default); ++ dwc_otg_set_param_cont_on_bna(core_if, dwc_param_cont_on_bna_default); ++ dwc_otg_set_param_ahb_single(core_if, dwc_param_ahb_single_default); ++ dwc_otg_set_param_otg_ver(core_if, dwc_param_otg_ver_default); ++ dwc_otg_set_param_adp_enable(core_if, dwc_param_adp_enable_default); + DWC_PRINTF("Finished setting default values for core params\n"); ++ + return 0; + } + +@@ -4090,7 +5393,7 @@ + && (core_if->hwcfg2.b.op_mode != + DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE) + && (core_if->hwcfg2.b.op_mode != +- DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST)) { ++ DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST)) { + valid = 0; + } + break; +@@ -4119,7 +5422,7 @@ + } + + core_if->core_params->otg_cap = val; +- out: ++out: + return retval; + } + +@@ -4288,11 +5591,11 @@ + return -DWC_E_INVALID; + } + +- if (val > dwc_read_reg32(&core_if->core_global_regs->grxfsiz)) { +- if(dwc_otg_param_initialized(core_if->core_params->dev_rx_fifo_size)) { ++ if (val > DWC_READ_REG32(&core_if->core_global_regs->grxfsiz)) { ++ if (dwc_otg_param_initialized(core_if->core_params->dev_rx_fifo_size)) { + DWC_WARN("%d invalid for dev_rx_fifo_size parameter\n", val); + } +- val = dwc_read_reg32(&core_if->core_global_regs->grxfsiz); ++ val = DWC_READ_REG32(&core_if->core_global_regs->grxfsiz); + retval = -DWC_E_INVALID; + } + +@@ -4316,7 +5619,7 @@ + return -DWC_E_INVALID; + } + +- if (val > (dwc_read_reg32(&core_if->core_global_regs->gnptxfsiz) >> 16)) { ++ if (val > (DWC_READ_REG32(&core_if->core_global_regs->gnptxfsiz) >> 16)) { + if (dwc_otg_param_initialized + (core_if->core_params->dev_nperio_tx_fifo_size)) { + DWC_ERROR +@@ -4324,7 +5627,7 @@ + val); + } + val = +- (dwc_read_reg32(&core_if->core_global_regs->gnptxfsiz) >> ++ (DWC_READ_REG32(&core_if->core_global_regs->gnptxfsiz) >> + 16); + retval = -DWC_E_INVALID; + } +@@ -4349,14 +5652,14 @@ + return -DWC_E_INVALID; + } + +- if (val > dwc_read_reg32(&core_if->core_global_regs->grxfsiz)) { ++ if (val > DWC_READ_REG32(&core_if->core_global_regs->grxfsiz)) { + if (dwc_otg_param_initialized + (core_if->core_params->host_rx_fifo_size)) { + DWC_ERROR + ("%d invalid for host_rx_fifo_size. Check HW configuration.\n", + val); + } +- val = dwc_read_reg32(&core_if->core_global_regs->grxfsiz); ++ val = DWC_READ_REG32(&core_if->core_global_regs->grxfsiz); + retval = -DWC_E_INVALID; + } + +@@ -4381,7 +5684,7 @@ + return -DWC_E_INVALID; + } + +- if (val > (dwc_read_reg32(&core_if->core_global_regs->gnptxfsiz) >> 16)) { ++ if (val > (DWC_READ_REG32(&core_if->core_global_regs->gnptxfsiz) >> 16)) { + if (dwc_otg_param_initialized + (core_if->core_params->host_nperio_tx_fifo_size)) { + DWC_ERROR +@@ -4389,7 +5692,7 @@ + val); + } + val = +- (dwc_read_reg32(&core_if->core_global_regs->gnptxfsiz) >> ++ (DWC_READ_REG32(&core_if->core_global_regs->gnptxfsiz) >> + 16); + retval = -DWC_E_INVALID; + } +@@ -4414,16 +5717,14 @@ + } + + if (val > +- ((dwc_read_reg32(&core_if->core_global_regs->hptxfsiz) >> 16))) { ++ ((core_if->hptxfsiz.d32)>> 16)) { + if (dwc_otg_param_initialized + (core_if->core_params->host_perio_tx_fifo_size)) { + DWC_ERROR + ("%d invalid for host_perio_tx_fifo_size. Check HW configuration.\n", + val); + } +- val = +- (dwc_read_reg32(&core_if->core_global_regs->hptxfsiz) >> +- 16); ++ val = (core_if->hptxfsiz.d32) >> 16; + retval = -DWC_E_INVALID; + } + +@@ -4652,9 +5953,11 @@ + + if ((val == DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ) + && (dwc_otg_get_param_phy_type(core_if) == DWC_PHY_TYPE_PARAM_FS)) { +- if(dwc_otg_param_initialized(core_if->core_params->host_ls_low_power_phy_clk)) { +- DWC_ERROR("%d invalid for host_ls_low_power_phy_clk. Check HW configuration.\n", +- val); ++ if (dwc_otg_param_initialized ++ (core_if->core_params->host_ls_low_power_phy_clk)) { ++ DWC_ERROR ++ ("%d invalid for host_ls_low_power_phy_clk. Check HW configuration.\n", ++ val); + } + val = + (dwc_otg_get_param_phy_type(core_if) == +@@ -4769,9 +6072,10 @@ + } + #ifndef NO_FS_PHY_HW_CHECK + if (val == 1 && core_if->hwcfg3.b.i2c == 0) { +- if(dwc_otg_param_initialized(core_if->core_params->i2c_enable)) { +- DWC_ERROR("%d invalid for i2c_enable. Check HW configuration.\n", +- val); ++ if (dwc_otg_param_initialized(core_if->core_params->i2c_enable)) { ++ DWC_ERROR ++ ("%d invalid for i2c_enable. Check HW configuration.\n", ++ val); + } + val = 0; + retval = -DWC_E_INVALID; +@@ -4798,12 +6102,15 @@ + return -DWC_E_INVALID; + } + +- if (val > (dwc_read_reg32(&core_if->core_global_regs->dptxfsiz_dieptxf[fifo_num]))) { +- if(dwc_otg_param_initialized(core_if->core_params->dev_perio_tx_fifo_size[fifo_num])) { +- DWC_ERROR("`%d' invalid for parameter `dev_perio_fifo_size_%d'. Check HW configuration.\n", +- val, fifo_num); ++ if (val > ++ (DWC_READ_REG32(&core_if->core_global_regs->dtxfsiz[fifo_num]))) { ++ if (dwc_otg_param_initialized ++ (core_if->core_params->dev_perio_tx_fifo_size[fifo_num])) { ++ DWC_ERROR ++ ("`%d' invalid for parameter `dev_perio_fifo_size_%d'. Check HW configuration.\n", ++ val, fifo_num); + } +- val = (dwc_read_reg32(&core_if->core_global_regs->dptxfsiz_dieptxf[fifo_num])); ++ val = (DWC_READ_REG32(&core_if->core_global_regs->dtxfsiz[fifo_num])); + retval = -DWC_E_INVALID; + } + +@@ -4828,9 +6135,11 @@ + } + + if (val == 1 && core_if->hwcfg4.b.ded_fifo_en == 0) { +- if(dwc_otg_param_initialized(core_if->core_params->en_multiple_tx_fifo)) { +- DWC_ERROR("%d invalid for parameter en_multiple_tx_fifo. Check HW configuration.\n", +- val); ++ if (dwc_otg_param_initialized ++ (core_if->core_params->en_multiple_tx_fifo)) { ++ DWC_ERROR ++ ("%d invalid for parameter en_multiple_tx_fifo. Check HW configuration.\n", ++ val); + } + val = 0; + retval = -DWC_E_INVALID; +@@ -4856,12 +6165,15 @@ + return -DWC_E_INVALID; + } + +- if (val > (dwc_read_reg32(&core_if->core_global_regs->dptxfsiz_dieptxf[fifo_num]))) { +- if(dwc_otg_param_initialized(core_if->core_params->dev_tx_fifo_size[fifo_num])) { +- DWC_ERROR("`%d' invalid for parameter `dev_tx_fifo_size_%d'. Check HW configuration.\n", +- val, fifo_num); ++ if (val > ++ (DWC_READ_REG32(&core_if->core_global_regs->dtxfsiz[fifo_num]))) { ++ if (dwc_otg_param_initialized ++ (core_if->core_params->dev_tx_fifo_size[fifo_num])) { ++ DWC_ERROR ++ ("`%d' invalid for parameter `dev_tx_fifo_size_%d'. Check HW configuration.\n", ++ val, fifo_num); + } +- val = (dwc_read_reg32(&core_if->core_global_regs->dptxfsiz_dieptxf[fifo_num])); ++ val = (DWC_READ_REG32(&core_if->core_global_regs->dtxfsiz[fifo_num])); + retval = -DWC_E_INVALID; + } + +@@ -4888,9 +6200,10 @@ + if ((val != 0) && + (!dwc_otg_get_param_dma_enable(core_if) || + !core_if->hwcfg4.b.ded_fifo_en)) { +- if(dwc_otg_param_initialized(core_if->core_params->thr_ctl)) { +- DWC_ERROR("%d invalid for parameter thr_ctl. Check HW configuration.\n", +- val); ++ if (dwc_otg_param_initialized(core_if->core_params->thr_ctl)) { ++ DWC_ERROR ++ ("%d invalid for parameter thr_ctl. Check HW configuration.\n", ++ val); + } + val = 0; + retval = -DWC_E_INVALID; +@@ -4916,9 +6229,10 @@ + } + + if (val && !core_if->hwcfg3.b.otg_lpm_en) { +- if(dwc_otg_param_initialized(core_if->core_params->lpm_enable)) { +- DWC_ERROR("%d invalid for parameter lpm_enable. Check HW configuration.\n", +- val); ++ if (dwc_otg_param_initialized(core_if->core_params->lpm_enable)) { ++ DWC_ERROR ++ ("%d invalid for parameter lpm_enable. Check HW configuration.\n", ++ val); + } + val = 0; + retval = -DWC_E_INVALID; +@@ -4998,7 +6312,8 @@ + } + if (val && (core_if->snpsid < OTG_CORE_REV_2_72a)) { + if (dwc_otg_param_initialized(core_if->core_params->pti_enable)) { +- DWC_ERROR("%d invalid for parameter pti_enable. Check HW configuration.\n", ++ DWC_ERROR ++ ("%d invalid for parameter pti_enable. Check HW configuration.\n", + val); + } + retval = -DWC_E_INVALID; +@@ -5022,7 +6337,8 @@ + } + if (val && (core_if->hwcfg2.b.multi_proc_int == 0)) { + if (dwc_otg_param_initialized(core_if->core_params->mpi_enable)) { +- DWC_ERROR("%d invalid for parameter mpi_enable. Check HW configuration.\n", ++ DWC_ERROR ++ ("%d invalid for parameter mpi_enable. Check HW configuration.\n", + val); + } + retval = -DWC_E_INVALID; +@@ -5037,8 +6353,37 @@ + return core_if->core_params->mpi_enable; + } + +-int dwc_otg_set_param_ic_usb_cap(dwc_otg_core_if_t * core_if, +- int32_t val) ++int dwc_otg_set_param_adp_enable(dwc_otg_core_if_t * core_if, int32_t val) ++{ ++ int retval = 0; ++ if (DWC_OTG_PARAM_TEST(val, 0, 1)) { ++ DWC_WARN("`%d' invalid for parameter `adp_enable'\n", val); ++ return -DWC_E_INVALID; ++ } ++ if (val && (core_if->hwcfg3.b.adp_supp == 0)) { ++ if (dwc_otg_param_initialized ++ (core_if->core_params->adp_supp_enable)) { ++ DWC_ERROR ++ ("%d invalid for parameter adp_enable. Check HW configuration.\n", ++ val); ++ } ++ retval = -DWC_E_INVALID; ++ val = 0; ++ } ++ core_if->core_params->adp_supp_enable = val; ++ /*Set OTG version 2.0 in case of enabling ADP*/ ++ if (val) ++ dwc_otg_set_param_otg_ver(core_if, 1); ++ ++ return retval; ++} ++ ++int32_t dwc_otg_get_param_adp_enable(dwc_otg_core_if_t * core_if) ++{ ++ return core_if->core_params->adp_supp_enable; ++} ++ ++int dwc_otg_set_param_ic_usb_cap(dwc_otg_core_if_t * core_if, int32_t val) + { + int retval = 0; + if (DWC_OTG_PARAM_TEST(val, 0, 1)) { +@@ -5047,9 +6392,10 @@ + return -DWC_E_INVALID; + } + +- if (val && (core_if->hwcfg3.b.otg_enable_ic_usb == 0)) { ++ if (val && (core_if->hwcfg2.b.otg_enable_ic_usb == 0)) { + if (dwc_otg_param_initialized(core_if->core_params->ic_usb_cap)) { +- DWC_ERROR("%d invalid for parameter ic_usb_cap. Check HW configuration.\n", ++ DWC_ERROR ++ ("%d invalid for parameter ic_usb_cap. Check HW configuration.\n", + val); + } + retval = -DWC_E_INVALID; +@@ -5058,6 +6404,7 @@ + core_if->core_params->ic_usb_cap = val; + return retval; + } ++ + int32_t dwc_otg_get_param_ic_usb_cap(dwc_otg_core_if_t * core_if) + { + return core_if->core_params->ic_usb_cap; +@@ -5068,20 +6415,27 @@ + int retval = 0; + int valid = 1; + +- if(DWC_OTG_PARAM_TEST(val, 0, 3)) { ++ if (DWC_OTG_PARAM_TEST(val, 0, 3)) { + DWC_WARN("`%d' invalid for parameter `ahb_thr_ratio'\n", val); + DWC_WARN("ahb_thr_ratio must be 0 - 3\n"); + return -DWC_E_INVALID; + } + +- if(val && (core_if->snpsid < OTG_CORE_REV_2_81a || !dwc_otg_get_param_thr_ctl(core_if))) { ++ if (val ++ && (core_if->snpsid < OTG_CORE_REV_2_81a ++ || !dwc_otg_get_param_thr_ctl(core_if))) { + valid = 0; +- } else if(val && ((dwc_otg_get_param_tx_thr_length(core_if) / (1 << val)) < 4)) { ++ } else if (val ++ && ((dwc_otg_get_param_tx_thr_length(core_if) / (1 << val)) < ++ 4)) { + valid = 0; + } +- if(valid == 0) { +- if(dwc_otg_param_initialized(core_if->core_params->ahb_thr_ratio)) { +- DWC_ERROR("%d invalid for parameter ahb_thr_ratio. Chack HW configuration.\n", val); ++ if (valid == 0) { ++ if (dwc_otg_param_initialized ++ (core_if->core_params->ahb_thr_ratio)) { ++ DWC_ERROR ++ ("%d invalid for parameter ahb_thr_ratio. Check HW configuration.\n", ++ val); + } + retval = -DWC_E_INVALID; + val = 0; +@@ -5090,32 +6444,214 @@ + core_if->core_params->ahb_thr_ratio = val; + return retval; + } ++ + int32_t dwc_otg_get_param_ahb_thr_ratio(dwc_otg_core_if_t * core_if) + { + return core_if->core_params->ahb_thr_ratio; + } + ++int dwc_otg_set_param_power_down(dwc_otg_core_if_t * core_if, int32_t val) ++{ ++ int retval = 0; ++ int valid = 1; ++ ++ if (DWC_OTG_PARAM_TEST(val, 0, 2)) { ++ DWC_WARN("`%d' invalid for parameter `power_down'\n", val); ++ DWC_WARN("power_down must be 0 - 2\n"); ++ return -DWC_E_INVALID; ++ } ++ ++ if ((val == 2) && (core_if->snpsid < OTG_CORE_REV_2_91a)) { ++ valid = 0; ++ } ++ if (valid == 0) { ++ if (dwc_otg_param_initialized(core_if->core_params->power_down)) { ++ DWC_ERROR ++ ("%d invalid for parameter power_down. Check HW configuration.\n", ++ val); ++ } ++ retval = -DWC_E_INVALID; ++ val = 0; ++ } ++ core_if->core_params->power_down = val; ++ return retval; ++} ++ ++int32_t dwc_otg_get_param_power_down(dwc_otg_core_if_t * core_if) ++{ ++ return core_if->core_params->power_down; ++} ++ ++int dwc_otg_set_param_reload_ctl(dwc_otg_core_if_t * core_if, int32_t val) ++{ ++ int retval = 0; ++ int valid = 1; ++ ++ if (DWC_OTG_PARAM_TEST(val, 0, 1)) { ++ DWC_WARN("`%d' invalid for parameter `reload_ctl'\n", val); ++ DWC_WARN("reload_ctl must be 0 or 1\n"); ++ return -DWC_E_INVALID; ++ } ++ ++ if ((val == 1) && (core_if->snpsid < OTG_CORE_REV_2_92a)) { ++ valid = 0; ++ } ++ if (valid == 0) { ++ if (dwc_otg_param_initialized(core_if->core_params->reload_ctl)) { ++ DWC_ERROR("%d invalid for parameter reload_ctl." ++ "Check HW configuration.\n", val); ++ } ++ retval = -DWC_E_INVALID; ++ val = 0; ++ } ++ core_if->core_params->reload_ctl = val; ++ return retval; ++} ++ ++int32_t dwc_otg_get_param_reload_ctl(dwc_otg_core_if_t * core_if) ++{ ++ return core_if->core_params->reload_ctl; ++} ++ ++int dwc_otg_set_param_dev_out_nak(dwc_otg_core_if_t * core_if, int32_t val) ++{ ++ int retval = 0; ++ int valid = 1; ++ ++ if (DWC_OTG_PARAM_TEST(val, 0, 1)) { ++ DWC_WARN("`%d' invalid for parameter `dev_out_nak'\n", val); ++ DWC_WARN("dev_out_nak must be 0 or 1\n"); ++ return -DWC_E_INVALID; ++ } ++ ++ if ((val == 1) && ((core_if->snpsid < OTG_CORE_REV_2_93a) || ++ !(core_if->core_params->dma_desc_enable))) { ++ valid = 0; ++ } ++ if (valid == 0) { ++ if (dwc_otg_param_initialized(core_if->core_params->dev_out_nak)) { ++ DWC_ERROR("%d invalid for parameter dev_out_nak." ++ "Check HW configuration.\n", val); ++ } ++ retval = -DWC_E_INVALID; ++ val = 0; ++ } ++ core_if->core_params->dev_out_nak = val; ++ return retval; ++} ++ ++int32_t dwc_otg_get_param_dev_out_nak(dwc_otg_core_if_t * core_if) ++{ ++ return core_if->core_params->dev_out_nak; ++} ++ ++int dwc_otg_set_param_cont_on_bna(dwc_otg_core_if_t * core_if, int32_t val) ++{ ++ int retval = 0; ++ int valid = 1; ++ ++ if (DWC_OTG_PARAM_TEST(val, 0, 1)) { ++ DWC_WARN("`%d' invalid for parameter `cont_on_bna'\n", val); ++ DWC_WARN("cont_on_bna must be 0 or 1\n"); ++ return -DWC_E_INVALID; ++ } ++ ++ if ((val == 1) && ((core_if->snpsid < OTG_CORE_REV_2_94a) || ++ !(core_if->core_params->dma_desc_enable))) { ++ valid = 0; ++ } ++ if (valid == 0) { ++ if (dwc_otg_param_initialized(core_if->core_params->cont_on_bna)) { ++ DWC_ERROR("%d invalid for parameter cont_on_bna." ++ "Check HW configuration.\n", val); ++ } ++ retval = -DWC_E_INVALID; ++ val = 0; ++ } ++ core_if->core_params->cont_on_bna = val; ++ return retval; ++} ++ ++int32_t dwc_otg_get_param_cont_on_bna(dwc_otg_core_if_t * core_if) ++{ ++ return core_if->core_params->cont_on_bna; ++} ++ ++int dwc_otg_set_param_ahb_single(dwc_otg_core_if_t * core_if, int32_t val) ++{ ++ int retval = 0; ++ int valid = 1; ++ ++ if (DWC_OTG_PARAM_TEST(val, 0, 1)) { ++ DWC_WARN("`%d' invalid for parameter `ahb_single'\n", val); ++ DWC_WARN("ahb_single must be 0 or 1\n"); ++ return -DWC_E_INVALID; ++ } ++ ++ if ((val == 1) && (core_if->snpsid < OTG_CORE_REV_2_94a)) { ++ valid = 0; ++ } ++ if (valid == 0) { ++ if (dwc_otg_param_initialized(core_if->core_params->ahb_single)) { ++ DWC_ERROR("%d invalid for parameter ahb_single." ++ "Check HW configuration.\n", val); ++ } ++ retval = -DWC_E_INVALID; ++ val = 0; ++ } ++ core_if->core_params->ahb_single = val; ++ return retval; ++} ++ ++int32_t dwc_otg_get_param_ahb_single(dwc_otg_core_if_t * core_if) ++{ ++ return core_if->core_params->ahb_single; ++} ++ ++int dwc_otg_set_param_otg_ver(dwc_otg_core_if_t * core_if, int32_t val) ++{ ++ int retval = 0; ++ ++ if (DWC_OTG_PARAM_TEST(val, 0, 1)) { ++ DWC_WARN("`%d' invalid for parameter `otg_ver'\n", val); ++ DWC_WARN ++ ("otg_ver must be 0(for OTG 1.3 support) or 1(for OTG 2.0 support)\n"); ++ return -DWC_E_INVALID; ++ } ++ ++ core_if->core_params->otg_ver = val; ++ return retval; ++} ++ ++int32_t dwc_otg_get_param_otg_ver(dwc_otg_core_if_t * core_if) ++{ ++ return core_if->core_params->otg_ver; ++} + + uint32_t dwc_otg_get_hnpstatus(dwc_otg_core_if_t * core_if) + { + gotgctl_data_t otgctl; +- otgctl.d32 = dwc_read_reg32(&core_if->core_global_regs->gotgctl); ++ otgctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->gotgctl); + return otgctl.b.hstnegscs; + } + + uint32_t dwc_otg_get_srpstatus(dwc_otg_core_if_t * core_if) + { + gotgctl_data_t otgctl; +- otgctl.d32 = dwc_read_reg32(&core_if->core_global_regs->gotgctl); ++ otgctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->gotgctl); + return otgctl.b.sesreqscs; + } + + void dwc_otg_set_hnpreq(dwc_otg_core_if_t * core_if, uint32_t val) + { +- gotgctl_data_t otgctl; +- otgctl.d32 = dwc_read_reg32(&core_if->core_global_regs->gotgctl); +- otgctl.b.hnpreq = val; +- dwc_write_reg32(&core_if->core_global_regs->gotgctl, otgctl.d32); ++ if(core_if->otg_ver == 0) { ++ gotgctl_data_t otgctl; ++ otgctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->gotgctl); ++ otgctl.b.hnpreq = val; ++ DWC_WRITE_REG32(&core_if->core_global_regs->gotgctl, otgctl.d32); ++ } else { ++ core_if->otg_sts = val; ++ } + } + + uint32_t dwc_otg_get_gsnpsid(dwc_otg_core_if_t * core_if) +@@ -5125,45 +6661,47 @@ + + uint32_t dwc_otg_get_mode(dwc_otg_core_if_t * core_if) + { +- gotgctl_data_t otgctl; +- otgctl.d32 = dwc_read_reg32(&core_if->core_global_regs->gotgctl); +- return otgctl.b.currmod; ++ gintsts_data_t gintsts; ++ gintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts); ++ return gintsts.b.curmode; + } + + uint32_t dwc_otg_get_hnpcapable(dwc_otg_core_if_t * core_if) + { + gusbcfg_data_t usbcfg; +- usbcfg.d32 = dwc_read_reg32(&core_if->core_global_regs->gusbcfg); ++ usbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg); + return usbcfg.b.hnpcap; + } + + void dwc_otg_set_hnpcapable(dwc_otg_core_if_t * core_if, uint32_t val) + { + gusbcfg_data_t usbcfg; +- usbcfg.d32 = dwc_read_reg32(&core_if->core_global_regs->gusbcfg); ++ usbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg); + usbcfg.b.hnpcap = val; +- dwc_write_reg32(&core_if->core_global_regs->gusbcfg, usbcfg.d32); ++ DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, usbcfg.d32); + } + + uint32_t dwc_otg_get_srpcapable(dwc_otg_core_if_t * core_if) + { + gusbcfg_data_t usbcfg; +- usbcfg.d32 = dwc_read_reg32(&core_if->core_global_regs->gusbcfg); ++ usbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg); + return usbcfg.b.srpcap; + } + + void dwc_otg_set_srpcapable(dwc_otg_core_if_t * core_if, uint32_t val) + { + gusbcfg_data_t usbcfg; +- usbcfg.d32 = dwc_read_reg32(&core_if->core_global_regs->gusbcfg); ++ usbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg); + usbcfg.b.srpcap = val; +- dwc_write_reg32(&core_if->core_global_regs->gusbcfg, usbcfg.d32); ++ DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, usbcfg.d32); + } + + uint32_t dwc_otg_get_devspeed(dwc_otg_core_if_t * core_if) + { + dcfg_data_t dcfg; +- dcfg.d32 = -1; //GRAYG ++ /* originally: dcfg.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg); */ ++ ++ dcfg.d32 = -1; //GRAYG + DWC_DEBUGPL(DBG_CILV, "%s - core_if(%p)\n", __func__, core_if); + if (NULL == core_if) + DWC_ERROR("reg request with NULL core_if\n"); +@@ -5183,7 +6721,7 @@ + core_if, core_if->dev_if, + core_if->dev_if->dev_global_regs, + &core_if->dev_if->dev_global_regs->dcfg); +- dcfg.d32 = dwc_read_reg32(&core_if->dev_if->dev_global_regs->dcfg); ++ dcfg.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg); + } + return dcfg.b.devspd; + } +@@ -5191,45 +6729,50 @@ + void dwc_otg_set_devspeed(dwc_otg_core_if_t * core_if, uint32_t val) + { + dcfg_data_t dcfg; +- dcfg.d32 = dwc_read_reg32(&core_if->dev_if->dev_global_regs->dcfg); ++ dcfg.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg); + dcfg.b.devspd = val; +- dwc_write_reg32(&core_if->dev_if->dev_global_regs->dcfg, dcfg.d32); ++ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dcfg, dcfg.d32); + } + + uint32_t dwc_otg_get_busconnected(dwc_otg_core_if_t * core_if) + { + hprt0_data_t hprt0; +- hprt0.d32 = dwc_read_reg32(core_if->host_if->hprt0); ++ hprt0.d32 = DWC_READ_REG32(core_if->host_if->hprt0); + return hprt0.b.prtconnsts; + } + + uint32_t dwc_otg_get_enumspeed(dwc_otg_core_if_t * core_if) + { + dsts_data_t dsts; +- dsts.d32 = dwc_read_reg32(&core_if->dev_if->dev_global_regs->dsts); ++ dsts.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts); + return dsts.b.enumspd; + } + + uint32_t dwc_otg_get_prtpower(dwc_otg_core_if_t * core_if) + { + hprt0_data_t hprt0; +- hprt0.d32 = dwc_read_reg32(core_if->host_if->hprt0); ++ hprt0.d32 = DWC_READ_REG32(core_if->host_if->hprt0); + return hprt0.b.prtpwr; + + } + ++uint32_t dwc_otg_get_core_state(dwc_otg_core_if_t * core_if) ++{ ++ return core_if->hibernation_suspend; ++} ++ + void dwc_otg_set_prtpower(dwc_otg_core_if_t * core_if, uint32_t val) + { + hprt0_data_t hprt0; +- hprt0.d32 = dwc_read_reg32(core_if->host_if->hprt0); ++ hprt0.d32 = dwc_otg_read_hprt0(core_if); + hprt0.b.prtpwr = val; +- dwc_write_reg32(core_if->host_if->hprt0, val); ++ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32); + } + + uint32_t dwc_otg_get_prtsuspend(dwc_otg_core_if_t * core_if) + { + hprt0_data_t hprt0; +- hprt0.d32 = dwc_read_reg32(core_if->host_if->hprt0); ++ hprt0.d32 = DWC_READ_REG32(core_if->host_if->hprt0); + return hprt0.b.prtsusp; + + } +@@ -5237,30 +6780,119 @@ + void dwc_otg_set_prtsuspend(dwc_otg_core_if_t * core_if, uint32_t val) + { + hprt0_data_t hprt0; +- hprt0.d32 = dwc_read_reg32(core_if->host_if->hprt0); ++ hprt0.d32 = dwc_otg_read_hprt0(core_if); + hprt0.b.prtsusp = val; +- dwc_write_reg32(core_if->host_if->hprt0, val); ++ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32); ++} ++ ++uint32_t dwc_otg_get_fr_interval(dwc_otg_core_if_t * core_if) ++{ ++ hfir_data_t hfir; ++ hfir.d32 = DWC_READ_REG32(&core_if->host_if->host_global_regs->hfir); ++ return hfir.b.frint; ++ ++} ++ ++void dwc_otg_set_fr_interval(dwc_otg_core_if_t * core_if, uint32_t val) ++{ ++ hfir_data_t hfir; ++ uint32_t fram_int; ++ fram_int = calc_frame_interval(core_if); ++ hfir.d32 = DWC_READ_REG32(&core_if->host_if->host_global_regs->hfir); ++ if (!core_if->core_params->reload_ctl) { ++ DWC_WARN("\nCannot reload HFIR register.HFIR.HFIRRldCtrl bit is" ++ "not set to 1.\nShould load driver with reload_ctl=1" ++ " module parameter\n"); ++ return; ++ } ++ switch (fram_int) { ++ case 3750: ++ if ((val < 3350) || (val > 4150)) { ++ DWC_WARN("HFIR interval for HS core and 30 MHz" ++ "clock freq should be from 3350 to 4150\n"); ++ return; ++ } ++ break; ++ case 30000: ++ if ((val < 26820) || (val > 33180)) { ++ DWC_WARN("HFIR interval for FS/LS core and 30 MHz" ++ "clock freq should be from 26820 to 33180\n"); ++ return; ++ } ++ break; ++ case 6000: ++ if ((val < 5360) || (val > 6640)) { ++ DWC_WARN("HFIR interval for HS core and 48 MHz" ++ "clock freq should be from 5360 to 6640\n"); ++ return; ++ } ++ break; ++ case 48000: ++ if ((val < 42912) || (val > 53088)) { ++ DWC_WARN("HFIR interval for FS/LS core and 48 MHz" ++ "clock freq should be from 42912 to 53088\n"); ++ return; ++ } ++ break; ++ case 7500: ++ if ((val < 6700) || (val > 8300)) { ++ DWC_WARN("HFIR interval for HS core and 60 MHz" ++ "clock freq should be from 6700 to 8300\n"); ++ return; ++ } ++ break; ++ case 60000: ++ if ((val < 53640) || (val > 65536)) { ++ DWC_WARN("HFIR interval for FS/LS core and 60 MHz" ++ "clock freq should be from 53640 to 65536\n"); ++ return; ++ } ++ break; ++ default: ++ DWC_WARN("Unknown frame interval\n"); ++ return; ++ break; ++ ++ } ++ hfir.b.frint = val; ++ DWC_WRITE_REG32(&core_if->host_if->host_global_regs->hfir, hfir.d32); ++} ++ ++uint32_t dwc_otg_get_mode_ch_tim(dwc_otg_core_if_t * core_if) ++{ ++ hcfg_data_t hcfg; ++ hcfg.d32 = DWC_READ_REG32(&core_if->host_if->host_global_regs->hcfg); ++ return hcfg.b.modechtimen; ++ ++} ++ ++void dwc_otg_set_mode_ch_tim(dwc_otg_core_if_t * core_if, uint32_t val) ++{ ++ hcfg_data_t hcfg; ++ hcfg.d32 = DWC_READ_REG32(&core_if->host_if->host_global_regs->hcfg); ++ hcfg.b.modechtimen = val; ++ DWC_WRITE_REG32(&core_if->host_if->host_global_regs->hcfg, hcfg.d32); + } + + void dwc_otg_set_prtresume(dwc_otg_core_if_t * core_if, uint32_t val) + { + hprt0_data_t hprt0; +- hprt0.d32 = dwc_read_reg32(core_if->host_if->hprt0); ++ hprt0.d32 = dwc_otg_read_hprt0(core_if); + hprt0.b.prtres = val; +- dwc_write_reg32(core_if->host_if->hprt0, val); ++ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32); + } + + uint32_t dwc_otg_get_remotewakesig(dwc_otg_core_if_t * core_if) + { + dctl_data_t dctl; +- dctl.d32 = dwc_read_reg32(&core_if->dev_if->dev_global_regs->dctl); ++ dctl.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dctl); + return dctl.b.rmtwkupsig; + } + + uint32_t dwc_otg_get_lpm_portsleepstatus(dwc_otg_core_if_t * core_if) + { + glpmcfg_data_t lpmcfg; +- lpmcfg.d32 = dwc_read_reg32(&core_if->core_global_regs->glpmcfg); ++ lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg); + + DWC_ASSERT(! + ((core_if->lx_state == DWC_OTG_L1) ^ lpmcfg.b.prt_sleep_sts), +@@ -5273,44 +6905,44 @@ + uint32_t dwc_otg_get_lpm_remotewakeenabled(dwc_otg_core_if_t * core_if) + { + glpmcfg_data_t lpmcfg; +- lpmcfg.d32 = dwc_read_reg32(&core_if->core_global_regs->glpmcfg); ++ lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg); + return lpmcfg.b.rem_wkup_en; + } + + uint32_t dwc_otg_get_lpmresponse(dwc_otg_core_if_t * core_if) + { + glpmcfg_data_t lpmcfg; +- lpmcfg.d32 = dwc_read_reg32(&core_if->core_global_regs->glpmcfg); ++ lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg); + return lpmcfg.b.appl_resp; + } + + void dwc_otg_set_lpmresponse(dwc_otg_core_if_t * core_if, uint32_t val) + { + glpmcfg_data_t lpmcfg; +- lpmcfg.d32 = dwc_read_reg32(&core_if->core_global_regs->glpmcfg); ++ lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg); + lpmcfg.b.appl_resp = val; +- dwc_write_reg32(&core_if->core_global_regs->glpmcfg, lpmcfg.d32); ++ DWC_WRITE_REG32(&core_if->core_global_regs->glpmcfg, lpmcfg.d32); + } + + uint32_t dwc_otg_get_hsic_connect(dwc_otg_core_if_t * core_if) + { + glpmcfg_data_t lpmcfg; +- lpmcfg.d32 = dwc_read_reg32(&core_if->core_global_regs->glpmcfg); ++ lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg); + return lpmcfg.b.hsic_connect; + } + + void dwc_otg_set_hsic_connect(dwc_otg_core_if_t * core_if, uint32_t val) + { + glpmcfg_data_t lpmcfg; +- lpmcfg.d32 = dwc_read_reg32(&core_if->core_global_regs->glpmcfg); ++ lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg); + lpmcfg.b.hsic_connect = val; +- dwc_write_reg32(&core_if->core_global_regs->glpmcfg, lpmcfg.d32); ++ DWC_WRITE_REG32(&core_if->core_global_regs->glpmcfg, lpmcfg.d32); + } + + uint32_t dwc_otg_get_inv_sel_hsic(dwc_otg_core_if_t * core_if) + { + glpmcfg_data_t lpmcfg; +- lpmcfg.d32 = dwc_read_reg32(&core_if->core_global_regs->glpmcfg); ++ lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg); + return lpmcfg.b.inv_sel_hsic; + + } +@@ -5318,93 +6950,132 @@ + void dwc_otg_set_inv_sel_hsic(dwc_otg_core_if_t * core_if, uint32_t val) + { + glpmcfg_data_t lpmcfg; +- lpmcfg.d32 = dwc_read_reg32(&core_if->core_global_regs->glpmcfg); ++ lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg); + lpmcfg.b.inv_sel_hsic = val; +- dwc_write_reg32(&core_if->core_global_regs->glpmcfg, lpmcfg.d32); ++ DWC_WRITE_REG32(&core_if->core_global_regs->glpmcfg, lpmcfg.d32); + } + + uint32_t dwc_otg_get_gotgctl(dwc_otg_core_if_t * core_if) + { +- return dwc_read_reg32(&core_if->core_global_regs->gotgctl); ++ return DWC_READ_REG32(&core_if->core_global_regs->gotgctl); + } + + void dwc_otg_set_gotgctl(dwc_otg_core_if_t * core_if, uint32_t val) + { +- dwc_write_reg32(&core_if->core_global_regs->gotgctl, val); ++ DWC_WRITE_REG32(&core_if->core_global_regs->gotgctl, val); + } + + uint32_t dwc_otg_get_gusbcfg(dwc_otg_core_if_t * core_if) + { +- return dwc_read_reg32(&core_if->core_global_regs->gusbcfg); ++ return DWC_READ_REG32(&core_if->core_global_regs->gusbcfg); + } + + void dwc_otg_set_gusbcfg(dwc_otg_core_if_t * core_if, uint32_t val) + { +- dwc_write_reg32(&core_if->core_global_regs->gusbcfg, val); ++ DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, val); + } + + uint32_t dwc_otg_get_grxfsiz(dwc_otg_core_if_t * core_if) + { +- return dwc_read_reg32(&core_if->core_global_regs->grxfsiz); ++ return DWC_READ_REG32(&core_if->core_global_regs->grxfsiz); + } + + void dwc_otg_set_grxfsiz(dwc_otg_core_if_t * core_if, uint32_t val) + { +- dwc_write_reg32(&core_if->core_global_regs->grxfsiz, val); ++ DWC_WRITE_REG32(&core_if->core_global_regs->grxfsiz, val); + } + + uint32_t dwc_otg_get_gnptxfsiz(dwc_otg_core_if_t * core_if) + { +- return dwc_read_reg32(&core_if->core_global_regs->gnptxfsiz); ++ return DWC_READ_REG32(&core_if->core_global_regs->gnptxfsiz); + } + + void dwc_otg_set_gnptxfsiz(dwc_otg_core_if_t * core_if, uint32_t val) + { +- dwc_write_reg32(&core_if->core_global_regs->gnptxfsiz, val); ++ DWC_WRITE_REG32(&core_if->core_global_regs->gnptxfsiz, val); + } + + uint32_t dwc_otg_get_gpvndctl(dwc_otg_core_if_t * core_if) + { +- return dwc_read_reg32(&core_if->core_global_regs->gpvndctl); ++ return DWC_READ_REG32(&core_if->core_global_regs->gpvndctl); + } + + void dwc_otg_set_gpvndctl(dwc_otg_core_if_t * core_if, uint32_t val) + { +- dwc_write_reg32(&core_if->core_global_regs->gpvndctl, val); ++ DWC_WRITE_REG32(&core_if->core_global_regs->gpvndctl, val); + } + + uint32_t dwc_otg_get_ggpio(dwc_otg_core_if_t * core_if) + { +- return dwc_read_reg32(&core_if->core_global_regs->ggpio); ++ return DWC_READ_REG32(&core_if->core_global_regs->ggpio); + } + + void dwc_otg_set_ggpio(dwc_otg_core_if_t * core_if, uint32_t val) + { +- dwc_write_reg32(&core_if->core_global_regs->ggpio, val); ++ DWC_WRITE_REG32(&core_if->core_global_regs->ggpio, val); + } + + uint32_t dwc_otg_get_hprt0(dwc_otg_core_if_t * core_if) + { +- return dwc_read_reg32(core_if->host_if->hprt0); ++ return DWC_READ_REG32(core_if->host_if->hprt0); + + } + + void dwc_otg_set_hprt0(dwc_otg_core_if_t * core_if, uint32_t val) + { +- dwc_write_reg32(core_if->host_if->hprt0, val); ++ DWC_WRITE_REG32(core_if->host_if->hprt0, val); + } + + uint32_t dwc_otg_get_guid(dwc_otg_core_if_t * core_if) + { +- return dwc_read_reg32(&core_if->core_global_regs->guid); ++ return DWC_READ_REG32(&core_if->core_global_regs->guid); + } + + void dwc_otg_set_guid(dwc_otg_core_if_t * core_if, uint32_t val) + { +- dwc_write_reg32(&core_if->core_global_regs->guid, val); ++ DWC_WRITE_REG32(&core_if->core_global_regs->guid, val); + } + + uint32_t dwc_otg_get_hptxfsiz(dwc_otg_core_if_t * core_if) + { +- return dwc_read_reg32(&core_if->core_global_regs->hptxfsiz); ++ return DWC_READ_REG32(&core_if->core_global_regs->hptxfsiz); ++} ++ ++uint16_t dwc_otg_get_otg_version(dwc_otg_core_if_t * core_if) ++{ ++ return ((core_if->otg_ver == 1) ? (uint16_t)0x0200 : (uint16_t)0x0103); ++} ++ ++/** ++ * Start the SRP timer to detect when the SRP does not complete within ++ * 6 seconds. ++ * ++ * @param core_if the pointer to core_if strucure. ++ */ ++void dwc_otg_pcd_start_srp_timer(dwc_otg_core_if_t * core_if) ++{ ++ core_if->srp_timer_started = 1; ++ DWC_TIMER_SCHEDULE(core_if->srp_timer, 6000 /* 6 secs */ ); ++} ++ ++void dwc_otg_initiate_srp(dwc_otg_core_if_t * core_if) ++{ ++ uint32_t *addr = (uint32_t *) & (core_if->core_global_regs->gotgctl); ++ gotgctl_data_t mem; ++ gotgctl_data_t val; ++ ++ val.d32 = DWC_READ_REG32(addr); ++ if (val.b.sesreq) { ++ DWC_ERROR("Session Request Already active!\n"); ++ return; ++ } ++ ++ DWC_INFO("Session Request Initated\n"); //NOTICE ++ mem.d32 = DWC_READ_REG32(addr); ++ mem.b.sesreq = 1; ++ DWC_WRITE_REG32(addr, mem.d32); ++ ++ /* Start the SRP timer */ ++ dwc_otg_pcd_start_srp_timer(core_if); ++ return; + } +Index: linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_cil.h +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/dwc_otg_cil.h 2013-07-26 19:31:23.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_cil.h 2013-07-26 19:34:44.000000000 +0000 +@@ -1,13 +1,13 @@ + /* ========================================================================== + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_cil.h $ +- * $Revision: #99 $ +- * $Date: 2009/04/21 $ +- * $Change: 1237466 $ ++ * $Revision: #122 $ ++ * $Date: 2011/10/24 $ ++ * $Change: 1871160 $ + * + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless + * otherwise expressly agreed to in writing between Synopsys and you. +- * ++ * + * The Software IS NOT an item of Licensed Software or Licensed Product under + * any End User Software License Agreement or Agreement for Licensed Product + * with Synopsys or any supplement thereto. You are permitted to use and +@@ -17,7 +17,7 @@ + * any information contained herein except pursuant to this license grant from + * Synopsys. If you do not agree with this notice, including the disclaimer + * below, then you are not authorized to use the Software. +- * ++ * + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +@@ -34,15 +34,14 @@ + #if !defined(__DWC_CIL_H__) + #define __DWC_CIL_H__ + +-//#define HW2937_WORKAROUND + #define DBG_HW2937 0x400 + +-#include "dwc_os.h" + #include "dwc_list.h" + #include "dwc_otg_dbg.h" + #include "dwc_otg_regs.h" + + #include "dwc_otg_core_if.h" ++#include "dwc_otg_adp.h" + + /** + * @file +@@ -63,16 +62,20 @@ + BM_CIRCULAR = 3, /* data buffer uses the circular DMA mode */ + BM_ALIGN = 4 /* data buffer is in buffer alignment mode */ + } data_buffer_mode_e; +-#endif //DWC_UTE_CFI ++#endif //DWC_UTE_CFI + +-/** Macros defined for DWC OTG HW Release verison */ ++/** Macros defined for DWC OTG HW Release version */ + + #define OTG_CORE_REV_2_60a 0x4F54260A + #define OTG_CORE_REV_2_71a 0x4F54271A + #define OTG_CORE_REV_2_72a 0x4F54272A + #define OTG_CORE_REV_2_80a 0x4F54280A + #define OTG_CORE_REV_2_81a 0x4F54281A +-#define OTG_CORE_REV_2_90a 0x4F54290A ++#define OTG_CORE_REV_2_90a 0x4F54290A ++#define OTG_CORE_REV_2_91a 0x4F54291A ++#define OTG_CORE_REV_2_92a 0x4F54292A ++#define OTG_CORE_REV_2_93a 0x4F54293A ++#define OTG_CORE_REV_2_94a 0x4F54294A + + /** + * Information for each ISOC packet. +@@ -96,8 +99,9 @@ + /** EP active. */ + unsigned active:1; + +- /** Periodic Tx FIFO # for IN EPs For INTR EP set to 0 to use non-periodic Tx FIFO +- If dedicated Tx FIFOs are enabled for all IN Eps - Tx FIFO # FOR IN EPs*/ ++ /** ++ * Periodic Tx FIFO # for IN EPs For INTR EP set to 0 to use non-periodic ++ * Tx FIFO. If dedicated Tx FIFOs are enabled Tx FIFO # FOR IN EPs*/ + unsigned tx_fifo_num:4; + /** EP type: 0 - Control, 1 - ISOC, 2 - BULK, 3 - INTR */ + unsigned type:2; +@@ -159,9 +163,27 @@ + uint32_t cfi_req_len; + #endif //DWC_UTE_CFI + ++/** Max DMA Descriptor count for any EP */ ++#define MAX_DMA_DESC_CNT 256 + /** Allocated DMA Desc count */ + uint32_t desc_cnt; ++ ++ /** bInterval */ ++ uint32_t bInterval; ++ /** Next frame num to setup next ISOC transfer */ ++ uint32_t frame_num; ++ /** Indicates SOF number overrun in DSTS */ ++ uint8_t frm_overrun; + ++#ifdef DWC_UTE_PER_IO ++ /** Next frame num for which will be setup DMA Desc */ ++ uint32_t xiso_frame_num; ++ /** bInterval */ ++ uint32_t xiso_bInterval; ++ /** Count of currently active transfers - shall be either 0 or 1 */ ++ int xiso_active_xfers; ++ int xiso_queued_xfers; ++#endif + #ifdef DWC_EN_ISOC + /** + * Variables specific for ISOC EPs +@@ -230,9 +252,6 @@ + DWC_OTG_HC_XFER_AHB_ERR, + DWC_OTG_HC_XFER_PERIODIC_INCOMPLETE, + DWC_OTG_HC_XFER_URB_DEQUEUE +-#ifdef HW2937_WORKAROUND +- , DWC_OTG_HC_XFER_PAUSE_IN +-#endif + } dwc_otg_halt_status_e; + + /** +@@ -301,7 +320,7 @@ + + /** Pointer to the current transfer buffer position. */ + uint8_t *xfer_buff; +- /** ++ /** + * In Buffer DMA mode this buffer will be used + * if xfer_buff is not DWORD aligned. + */ +@@ -358,9 +377,9 @@ + uint8_t hub_addr; /**< Address of high speed hub */ + + uint8_t port_addr; /**< Port of the low/full speed device */ +- /** Split transaction position ++ /** Split transaction position + * One of the following values: +- * - DWC_HCSPLIT_XACTPOS_MID ++ * - DWC_HCSPLIT_XACTPOS_MID + * - DWC_HCSPLIT_XACTPOS_BEGIN + * - DWC_HCSPLIT_XACTPOS_END + * - DWC_HCSPLIT_XACTPOS_ALL */ +@@ -384,19 +403,19 @@ + + /** Entry in list of host channels. */ + DWC_CIRCLEQ_ENTRY(dwc_hc) hc_list_entry; +- ++ + /** @name Descriptor DMA support */ + /** @{ */ +- ++ + /** Number of Transfer Descriptors */ + uint16_t ntd; +- ++ + /** Descriptor List DMA address */ + dwc_dma_t desc_list_addr; +- ++ + /** Scheduling micro-frame bitmap. */ + uint8_t schinfo; +- ++ + /** @} */ + } dwc_hc_t; + +@@ -426,9 +445,9 @@ + int32_t dma_enable; + + /** +- * When DMA mode is enabled specifies whether to use address DMA or DMA Descritor mode for accessing the data +- * FIFOs in device mode. The driver will automatically detect the value for this +- * parameter if none is specified. ++ * When DMA mode is enabled specifies whether to use address DMA or DMA ++ * Descriptor mode for accessing the data FIFOs in device mode. The driver ++ * will automatically detect the value for this if none is specified. + * 0 - address DMA + * 1 - DMA Descriptor(default, if available) + */ +@@ -447,7 +466,7 @@ + * 1 - Full Speed + */ + int32_t speed; +- /** Specifies whether low power mode is supported when attached ++ /** Specifies whether low power mode is supported when attached + * to a Full Speed or Low Speed device in host mode. + * 0 - Don't support low power mode (default) + * 1 - Support low power mode +@@ -456,7 +475,7 @@ + + /** Specifies the PHY clock rate in low power mode when connected to a + * Low Speed device in host mode. This parameter is applicable only if +- * HOST_SUPPORT_FS_LS_LOW_POWER is enabled. If PHY_TYPE is set to FS ++ * HOST_SUPPORT_FS_LS_LOW_POWER is enabled. If PHY_TYPE is set to FS + * then defaults to 6 MHZ otherwise 48 MHZ. + * + * 0 - 48 MHz +@@ -470,21 +489,21 @@ + */ + int32_t enable_dynamic_fifo; + +- /** Total number of 4-byte words in the data FIFO memory. This +- * memory includes the Rx FIFO, non-periodic Tx FIFO, and periodic ++ /** Total number of 4-byte words in the data FIFO memory. This ++ * memory includes the Rx FIFO, non-periodic Tx FIFO, and periodic + * Tx FIFOs. + * 32 to 32768 (default 8192) + * Note: The total FIFO memory depth in the FPGA configuration is 8192. + */ + int32_t data_fifo_size; + +- /** Number of 4-byte words in the Rx FIFO in device mode when dynamic ++ /** Number of 4-byte words in the Rx FIFO in device mode when dynamic + * FIFO sizing is enabled. + * 16 to 32768 (default 1064) + */ + int32_t dev_rx_fifo_size; + +- /** Number of 4-byte words in the non-periodic Tx FIFO in device mode ++ /** Number of 4-byte words in the non-periodic Tx FIFO in device mode + * when dynamic FIFO sizing is enabled. + * 16 to 32768 (default 1024) + */ +@@ -496,52 +515,52 @@ + */ + uint32_t dev_perio_tx_fifo_size[MAX_PERIO_FIFOS]; + +- /** Number of 4-byte words in the Rx FIFO in host mode when dynamic ++ /** Number of 4-byte words in the Rx FIFO in host mode when dynamic + * FIFO sizing is enabled. +- * 16 to 32768 (default 1024) ++ * 16 to 32768 (default 1024) + */ + int32_t host_rx_fifo_size; + +- /** Number of 4-byte words in the non-periodic Tx FIFO in host mode +- * when Dynamic FIFO sizing is enabled in the core. ++ /** Number of 4-byte words in the non-periodic Tx FIFO in host mode ++ * when Dynamic FIFO sizing is enabled in the core. + * 16 to 32768 (default 1024) + */ + int32_t host_nperio_tx_fifo_size; + +- /** Number of 4-byte words in the host periodic Tx FIFO when dynamic +- * FIFO sizing is enabled. ++ /** Number of 4-byte words in the host periodic Tx FIFO when dynamic ++ * FIFO sizing is enabled. + * 16 to 32768 (default 1024) + */ + int32_t host_perio_tx_fifo_size; + +- /** The maximum transfer size supported in bytes. ++ /** The maximum transfer size supported in bytes. + * 2047 to 65,535 (default 65,535) + */ + int32_t max_transfer_size; + +- /** The maximum number of packets in a transfer. ++ /** The maximum number of packets in a transfer. + * 15 to 511 (default 511) + */ + int32_t max_packet_count; + +- /** The number of host channel registers to use. +- * 1 to 16 (default 12) ++ /** The number of host channel registers to use. ++ * 1 to 16 (default 12) + * Note: The FPGA configuration supports a maximum of 12 host channels. + */ + int32_t host_channels; + +- /** The number of endpoints in addition to EP0 available for device +- * mode operations. +- * 1 to 15 (default 6 IN and OUT) +- * Note: The FPGA configuration supports a maximum of 6 IN and OUT ++ /** The number of endpoints in addition to EP0 available for device ++ * mode operations. ++ * 1 to 15 (default 6 IN and OUT) ++ * Note: The FPGA configuration supports a maximum of 6 IN and OUT + * endpoints in addition to EP0. + */ + int32_t dev_endpoints; + +- /** ++ /** + * Specifies the type of PHY interface to use. By default, the driver + * will automatically detect the phy_type. +- * ++ * + * 0 - Full Speed PHY + * 1 - UTMI+ (default) + * 2 - ULPI +@@ -549,13 +568,13 @@ + int32_t phy_type; + + /** +- * Specifies the UTMI+ Data Width. This parameter is ++ * Specifies the UTMI+ Data Width. This parameter is + * applicable for a PHY_TYPE of UTMI+ or ULPI. (For a ULPI + * PHY_TYPE, this parameter indicates the data width between + * the MAC and the ULPI Wrapper.) Also, this parameter is + * applicable only if the OTG_HSPHY_WIDTH cC parameter was set + * to "8 and 16 bits", meaning that the core has been +- * configured to work at either data path width. ++ * configured to work at either data path width. + * + * 8 or 16 bits (default 16) + */ +@@ -565,7 +584,7 @@ + * Specifies whether the ULPI operates at double or single + * data rate. This parameter is only applicable if PHY_TYPE is + * ULPI. +- * ++ * + * 0 - single data rate ULPI interface with 8 bit wide data + * bus (default) + * 1 - double data rate ULPI interface with 4 bit wide data +@@ -574,7 +593,7 @@ + int32_t phy_ulpi_ddr; + + /** +- * Specifies whether to use the internal or external supply to ++ * Specifies whether to use the internal or external supply to + * drive the vbus with a ULPI phy. + */ + int32_t phy_ulpi_ext_vbus; +@@ -592,9 +611,9 @@ + int32_t ts_dline; + + /** +- * Specifies whether dedicated transmit FIFOs are ++ * Specifies whether dedicated transmit FIFOs are + * enabled for non periodic IN endpoints in device mode +- * 0 - No ++ * 0 - No + * 1 - Yes + */ + int32_t en_multiple_tx_fifo; +@@ -605,19 +624,19 @@ + */ + uint32_t dev_tx_fifo_size[MAX_TX_FIFOS]; + +- /** Thresholding enable flag- ++ /** Thresholding enable flag- + * bit 0 - enable non-ISO Tx thresholding + * bit 1 - enable ISO Tx thresholding + * bit 2 - enable Rx thresholding + */ + uint32_t thr_ctl; + +- /** Thresholding length for Tx ++ /** Thresholding length for Tx + * FIFOs in 32 bit DWORDs + */ + uint32_t tx_thr_length; + +- /** Thresholding length for Rx ++ /** Thresholding length for Rx + * FIFOs in 32 bit DWORDs + */ + uint32_t rx_thr_length; +@@ -627,14 +646,14 @@ + */ + int32_t lpm_enable; + +- /** Per Transfer Interrupt ++ /** Per Transfer Interrupt + * mode enable flag + * 1 - Enabled + * 0 - Disabled + */ + int32_t pti_enable; + +- /** Multi Processor Interrupt ++ /** Multi Processor Interrupt + * mode enable flag + * 1 - Enabled + * 0 - Disabled +@@ -655,6 +674,53 @@ + */ + int32_t ahb_thr_ratio; + ++ /** ADP Support ++ * 1 - Enabled ++ * 0 - Disabled ++ */ ++ int32_t adp_supp_enable; ++ ++ /** HFIR Reload Control ++ * 0 - The HFIR cannot be reloaded dynamically. ++ * 1 - Allow dynamic reloading of the HFIR register during runtime. ++ */ ++ int32_t reload_ctl; ++ ++ /** DCFG: Enable device Out NAK ++ * 0 - The core does not set NAK after Bulk Out transfer complete. ++ * 1 - The core sets NAK after Bulk OUT transfer complete. ++ */ ++ int32_t dev_out_nak; ++ ++ /** DCFG: Enable Continue on BNA ++ * After receiving BNA interrupt the core disables the endpoint,when the ++ * endpoint is re-enabled by the application the core starts processing ++ * 0 - from the DOEPDMA descriptor ++ * 1 - from the descriptor which received the BNA. ++ */ ++ int32_t cont_on_bna; ++ ++ /** GAHBCFG: AHB Single Support ++ * This bit when programmed supports SINGLE transfers for remainder ++ * data in a transfer for DMA mode of operation. ++ * 0 - in this case the remainder data will be sent using INCR burst size. ++ * 1 - in this case the remainder data will be sent using SINGLE burst size. ++ */ ++ int32_t ahb_single; ++ ++ /** Core Power down mode ++ * 0 - No Power Down is enabled ++ * 1 - Reserved ++ * 2 - Complete Power Down (Hibernation) ++ */ ++ int32_t power_down; ++ ++ /** OTG revision supported ++ * 0 - OTG 1.3 revision ++ * 1 - OTG 2.0 revision ++ */ ++ int32_t otg_ver; ++ + } dwc_otg_core_params_t; + + #ifdef DEBUG +@@ -664,6 +730,12 @@ + dwc_hc_t *hc; + } hc_xfer_info_t; + #endif ++ ++typedef struct ep_xfer_info { ++ struct dwc_otg_core_if *core_if; ++ dwc_ep_t *ep; ++ uint8_t state; ++} ep_xfer_info_t; + /* + * Device States + */ +@@ -678,6 +750,42 @@ + DWC_OTG_L3 + } dwc_otg_lx_state_e; + ++struct dwc_otg_global_regs_backup { ++ uint32_t gotgctl_local; ++ uint32_t gintmsk_local; ++ uint32_t gahbcfg_local; ++ uint32_t gusbcfg_local; ++ uint32_t grxfsiz_local; ++ uint32_t gnptxfsiz_local; ++#ifdef CONFIG_USB_DWC_OTG_LPM ++ uint32_t glpmcfg_local; ++#endif ++ uint32_t gi2cctl_local; ++ uint32_t hptxfsiz_local; ++ uint32_t pcgcctl_local; ++ uint32_t gdfifocfg_local; ++ uint32_t dtxfsiz_local[MAX_EPS_CHANNELS]; ++ uint32_t gpwrdn_local; ++}; ++ ++struct dwc_otg_host_regs_backup { ++ uint32_t hcfg_local; ++ uint32_t haintmsk_local; ++ uint32_t hcintmsk_local[MAX_EPS_CHANNELS]; ++ uint32_t hprt0_local; ++ uint32_t hfir_local; ++}; ++ ++struct dwc_otg_dev_regs_backup { ++ uint32_t dcfg; ++ uint32_t dctl; ++ uint32_t daintmsk; ++ uint32_t diepmsk; ++ uint32_t doepmsk; ++ uint32_t diepctl[MAX_EPS_CHANNELS]; ++ uint32_t dieptsiz[MAX_EPS_CHANNELS]; ++ uint32_t diepdma[MAX_EPS_CHANNELS]; ++}; + /** + * The dwc_otg_core_if structure contains information needed to manage + * the DWC_otg controller acting in either host or device mode. It +@@ -709,7 +817,17 @@ + */ + uint8_t srp_success; + uint8_t srp_timer_started; +- ++ /** Timer for SRP. If it expires before SRP is successful ++ * clear the SRP. */ ++ dwc_timer_t *srp_timer; ++ ++#ifdef DWC_DEV_SRPCAP ++ /* This timer is needed to power on the hibernated host core if SRP is not ++ * initiated on connected SRP capable device for limited period of time ++ */ ++ uint8_t pwron_timer_started; ++ dwc_timer_t *pwron_timer; ++#endif + /* Common configuration information */ + /** Power and Clock Gating Control Register */ + volatile uint32_t *pcgcctl; +@@ -751,6 +869,7 @@ + hwcfg2_data_t hwcfg2; + hwcfg3_data_t hwcfg3; + hwcfg4_data_t hwcfg4; ++ fifosize_data_t hptxfsiz; + + /** Host and Device Configuration -- stored here for convenience.*/ + hcfg_data_t hcfg; +@@ -797,7 +916,10 @@ + + /** Timer object used for handling "Wakeup Detected" Interrupt */ + dwc_timer_t *wkp_timer; +- ++ /** This arrays used for debug purposes for DEV OUT NAK enhancement */ ++ uint32_t start_doeptsiz_val[MAX_EPS_CHANNELS]; ++ ep_xfer_info_t ep_xfer_info[MAX_EPS_CHANNELS]; ++ dwc_timer_t *ep_xfer_timer[MAX_EPS_CHANNELS]; + #ifdef DEBUG + uint32_t start_hcchar_val[MAX_EPS_CHANNELS]; + +@@ -825,6 +947,48 @@ + /** Lx state of device */ + dwc_otg_lx_state_e lx_state; + ++ /** Saved Core Global registers */ ++ struct dwc_otg_global_regs_backup *gr_backup; ++ /** Saved Host registers */ ++ struct dwc_otg_host_regs_backup *hr_backup; ++ /** Saved Device registers */ ++ struct dwc_otg_dev_regs_backup *dr_backup; ++ ++ /** Power Down Enable */ ++ uint32_t power_down; ++ ++ /** ADP support Enable */ ++ uint32_t adp_enable; ++ ++ /** ADP structure object */ ++ dwc_otg_adp_t adp; ++ ++ /** hibernation/suspend flag */ ++ int hibernation_suspend; ++ ++ /** OTG revision supported */ ++ uint32_t otg_ver; ++ ++ /** OTG status flag used for HNP polling */ ++ uint8_t otg_sts; ++ ++ /** Pointer to either hcd->lock or pcd->lock */ ++ dwc_spinlock_t *lock; ++ ++ /** Start predict NextEP based on Learning Queue if equal 1, ++ * also used as counter of disabled NP IN EP's */ ++ uint8_t start_predict; ++ ++ /** NextEp sequence, including EP0: nextep_seq[] = EP if non-periodic and ++ * active, 0xff otherwise */ ++ uint8_t nextep_seq[MAX_EPS_CHANNELS]; ++ ++ /** Index of fisrt EP in nextep_seq array which should be re-enabled **/ ++ uint8_t first_in_nextep_seq; ++ ++ /** Frame number while entering to ISR - needed for ISOCs **/ ++ uint32_t frame_num; ++ + }; + + #ifdef DEBUG +@@ -835,13 +999,40 @@ + #endif + + /* +- * The following functions are functions for works ++ * This function is called when transfer is timed out on endpoint. ++ */ ++extern void ep_xfer_timeout(void *ptr); ++ ++/* ++ * The following functions are functions for works + * using during handling some interrupts + */ + extern void w_conn_id_status_change(void *p); + + extern void w_wakeup_detected(void *p); + ++/** Saves global register values into system memory. */ ++extern int dwc_otg_save_global_regs(dwc_otg_core_if_t * core_if); ++/** Saves device register values into system memory. */ ++extern int dwc_otg_save_dev_regs(dwc_otg_core_if_t * core_if); ++/** Saves host register values into system memory. */ ++extern int dwc_otg_save_host_regs(dwc_otg_core_if_t * core_if); ++/** Restore global register values. */ ++extern int dwc_otg_restore_global_regs(dwc_otg_core_if_t * core_if); ++/** Restore host register values. */ ++extern int dwc_otg_restore_host_regs(dwc_otg_core_if_t * core_if, int reset); ++/** Restore device register values. */ ++extern int dwc_otg_restore_dev_regs(dwc_otg_core_if_t * core_if, ++ int rem_wakeup); ++extern int restore_lpm_i2c_regs(dwc_otg_core_if_t * core_if); ++extern int restore_essential_regs(dwc_otg_core_if_t * core_if, int rmode, ++ int is_host); ++ ++extern int dwc_otg_host_hibernation_restore(dwc_otg_core_if_t * core_if, ++ int restore_mode, int reset); ++extern int dwc_otg_device_hibernation_restore(dwc_otg_core_if_t * core_if, ++ int rem_wakeup, int reset); ++ + /* + * The following functions support initialization of the CIL driver component + * and the DWC_otg controller. +@@ -881,7 +1072,7 @@ + dwc_ep_t * ep); + extern void dwc_otg_iso_ep_start_buf_transfer(dwc_otg_core_if_t * core_if, + dwc_ep_t * ep); +-#endif /* DWC_EN_ISOC */ ++#endif /* DWC_EN_ISOC */ + /**@}*/ + + /** @name Host CIL Functions +@@ -903,14 +1094,17 @@ + extern void dwc_otg_enable_host_interrupts(dwc_otg_core_if_t * _core_if); + extern void dwc_otg_disable_host_interrupts(dwc_otg_core_if_t * _core_if); + +-extern void dwc_otg_hc_start_transfer_ddma(dwc_otg_core_if_t * core_if, dwc_hc_t * hc); ++extern void dwc_otg_hc_start_transfer_ddma(dwc_otg_core_if_t * core_if, ++ dwc_hc_t * hc); ++ ++extern uint32_t calc_frame_interval(dwc_otg_core_if_t * core_if); + + /* Macro used to clear one channel interrupt */ + #define clear_hc_int(_hc_regs_, _intr_) \ + do { \ + hcint_data_t hcint_clear = {.d32 = 0}; \ + hcint_clear.b._intr_ = 1; \ +- dwc_write_reg32(&(_hc_regs_)->hcint, hcint_clear.d32); \ ++ DWC_WRITE_REG32(&(_hc_regs_)->hcint, hcint_clear.d32); \ + } while (0) + + /* +@@ -924,18 +1118,18 @@ + do { \ + hcintmsk_data_t hcintmsk = {.d32 = 0}; \ + hcintmsk.b._intr_ = 1; \ +- dwc_modify_reg32(&(_hc_regs_)->hcintmsk, hcintmsk.d32, 0); \ ++ DWC_MODIFY_REG32(&(_hc_regs_)->hcintmsk, hcintmsk.d32, 0); \ + } while (0) +- ++ + /** +- * This function Reads HPRT0 in preparation to modify. It keeps the ++ * This function Reads HPRT0 in preparation to modify. It keeps the + * WC bits 0 so that if they are read as 1, they won't clear when you +- * write it back ++ * write it back + */ + static inline uint32_t dwc_otg_read_hprt0(dwc_otg_core_if_t * _core_if) + { + hprt0_data_t hprt0; +- hprt0.d32 = dwc_read_reg32(_core_if->host_if->hprt0); ++ hprt0.d32 = DWC_READ_REG32(_core_if->host_if->hprt0); + hprt0.b.prtena = 0; + hprt0.b.prtconndet = 0; + hprt0.b.prtenchng = 0; +@@ -963,8 +1157,8 @@ + */ + static inline uint32_t dwc_otg_read_core_intr(dwc_otg_core_if_t * core_if) + { +- return (dwc_read_reg32(&core_if->core_global_regs->gintsts) & +- dwc_read_reg32(&core_if->core_global_regs->gintmsk)); ++ return (DWC_READ_REG32(&core_if->core_global_regs->gintsts) & ++ DWC_READ_REG32(&core_if->core_global_regs->gintmsk)); + } + + /** +@@ -972,7 +1166,7 @@ + */ + static inline uint32_t dwc_otg_read_otg_intr(dwc_otg_core_if_t * core_if) + { +- return (dwc_read_reg32(&core_if->core_global_regs->gotgint)); ++ return (DWC_READ_REG32(&core_if->core_global_regs->gotgint)); + } + + /** +@@ -986,13 +1180,13 @@ + uint32_t v; + + if (core_if->multiproc_int_enable) { +- v = dwc_read_reg32(&core_if->dev_if->dev_global_regs-> +- deachint) & dwc_read_reg32(&core_if->dev_if-> +- dev_global_regs-> +- deachintmsk); ++ v = DWC_READ_REG32(&core_if->dev_if-> ++ dev_global_regs->deachint) & ++ DWC_READ_REG32(&core_if-> ++ dev_if->dev_global_regs->deachintmsk); + } else { +- v = dwc_read_reg32(&core_if->dev_if->dev_global_regs->daint) & +- dwc_read_reg32(&core_if->dev_if->dev_global_regs->daintmsk); ++ v = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->daint) & ++ DWC_READ_REG32(&core_if->dev_if->dev_global_regs->daintmsk); + } + return (v & 0xffff); + } +@@ -1007,13 +1201,13 @@ + uint32_t v; + + if (core_if->multiproc_int_enable) { +- v = dwc_read_reg32(&core_if->dev_if->dev_global_regs-> +- deachint) & dwc_read_reg32(&core_if->dev_if-> +- dev_global_regs-> +- deachintmsk); ++ v = DWC_READ_REG32(&core_if->dev_if-> ++ dev_global_regs->deachint) & ++ DWC_READ_REG32(&core_if-> ++ dev_if->dev_global_regs->deachintmsk); + } else { +- v = dwc_read_reg32(&core_if->dev_if->dev_global_regs->daint) & +- dwc_read_reg32(&core_if->dev_if->dev_global_regs->daintmsk); ++ v = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->daint) & ++ DWC_READ_REG32(&core_if->dev_if->dev_global_regs->daintmsk); + } + + return ((v & 0xffff0000) >> 16); +@@ -1030,20 +1224,20 @@ + + if (core_if->multiproc_int_enable) { + msk = +- dwc_read_reg32(&dev_if->dev_global_regs-> +- diepeachintmsk[ep->num]); ++ DWC_READ_REG32(&dev_if-> ++ dev_global_regs->diepeachintmsk[ep->num]); + emp = +- dwc_read_reg32(&dev_if->dev_global_regs-> +- dtknqr4_fifoemptymsk); ++ DWC_READ_REG32(&dev_if-> ++ dev_global_regs->dtknqr4_fifoemptymsk); + msk |= ((emp >> ep->num) & 0x1) << 7; +- v = dwc_read_reg32(&dev_if->in_ep_regs[ep->num]->diepint) & msk; ++ v = DWC_READ_REG32(&dev_if->in_ep_regs[ep->num]->diepint) & msk; + } else { +- msk = dwc_read_reg32(&dev_if->dev_global_regs->diepmsk); ++ msk = DWC_READ_REG32(&dev_if->dev_global_regs->diepmsk); + emp = +- dwc_read_reg32(&dev_if->dev_global_regs-> +- dtknqr4_fifoemptymsk); ++ DWC_READ_REG32(&dev_if-> ++ dev_global_regs->dtknqr4_fifoemptymsk); + msk |= ((emp >> ep->num) & 0x1) << 7; +- v = dwc_read_reg32(&dev_if->in_ep_regs[ep->num]->diepint) & msk; ++ v = DWC_READ_REG32(&dev_if->in_ep_regs[ep->num]->diepint) & msk; + } + + return v; +@@ -1061,20 +1255,20 @@ + + if (_core_if->multiproc_int_enable) { + msk.d32 = +- dwc_read_reg32(&dev_if->dev_global_regs-> +- doepeachintmsk[_ep->num]); ++ DWC_READ_REG32(&dev_if-> ++ dev_global_regs->doepeachintmsk[_ep->num]); + if (_core_if->pti_enh_enable) { + msk.b.pktdrpsts = 1; + } +- v = dwc_read_reg32(&dev_if->out_ep_regs[_ep->num]-> +- doepint) & msk.d32; ++ v = DWC_READ_REG32(&dev_if-> ++ out_ep_regs[_ep->num]->doepint) & msk.d32; + } else { +- msk.d32 = dwc_read_reg32(&dev_if->dev_global_regs->doepmsk); ++ msk.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->doepmsk); + if (_core_if->pti_enh_enable) { + msk.b.pktdrpsts = 1; + } +- v = dwc_read_reg32(&dev_if->out_ep_regs[_ep->num]-> +- doepint) & msk.d32; ++ v = DWC_READ_REG32(&dev_if-> ++ out_ep_regs[_ep->num]->doepint) & msk.d32; + } + return v; + } +@@ -1085,30 +1279,30 @@ + static inline uint32_t dwc_otg_read_host_all_channels_intr(dwc_otg_core_if_t * + _core_if) + { +- return (dwc_read_reg32(&_core_if->host_if->host_global_regs->haint)); ++ return (DWC_READ_REG32(&_core_if->host_if->host_global_regs->haint)); + } + + static inline uint32_t dwc_otg_read_host_channel_intr(dwc_otg_core_if_t * + _core_if, dwc_hc_t * _hc) + { +- return (dwc_read_reg32 ++ return (DWC_READ_REG32 + (&_core_if->host_if->hc_regs[_hc->hc_num]->hcint)); + } + + /** + * This function returns the mode of the operation, host or device. + * +- * @return 0 - Device Mode, 1 - Host Mode ++ * @return 0 - Device Mode, 1 - Host Mode + */ + static inline uint32_t dwc_otg_mode(dwc_otg_core_if_t * _core_if) + { +- return (dwc_read_reg32(&_core_if->core_global_regs->gintsts) & 0x1); ++ return (DWC_READ_REG32(&_core_if->core_global_regs->gintsts) & 0x1); + } + + /**@}*/ + + /** +- * DWC_otg CIL callback structure. This structure allows the HCD and ++ * DWC_otg CIL callback structure. This structure allows the HCD and + * PCD to register functions used for starting and stopping the PCD + * and HCD for role change on for a DRD. + */ +@@ -1140,4 +1334,124 @@ + dwc_otg_cil_callbacks_t * _cb, + void *_p); + ++void dwc_otg_initiate_srp(dwc_otg_core_if_t * core_if); ++ ++////////////////////////////////////////////////////////////////////// ++/** Start the HCD. Helper function for using the HCD callbacks. ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ */ ++static inline void cil_hcd_start(dwc_otg_core_if_t * core_if) ++{ ++ if (core_if->hcd_cb && core_if->hcd_cb->start) { ++ core_if->hcd_cb->start(core_if->hcd_cb->p); ++ } ++} ++ ++/** Stop the HCD. Helper function for using the HCD callbacks. ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ */ ++static inline void cil_hcd_stop(dwc_otg_core_if_t * core_if) ++{ ++ if (core_if->hcd_cb && core_if->hcd_cb->stop) { ++ core_if->hcd_cb->stop(core_if->hcd_cb->p); ++ } ++} ++ ++/** Disconnect the HCD. Helper function for using the HCD callbacks. ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ */ ++static inline void cil_hcd_disconnect(dwc_otg_core_if_t * core_if) ++{ ++ if (core_if->hcd_cb && core_if->hcd_cb->disconnect) { ++ core_if->hcd_cb->disconnect(core_if->hcd_cb->p); ++ } ++} ++ ++/** Inform the HCD the a New Session has begun. Helper function for ++ * using the HCD callbacks. ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ */ ++static inline void cil_hcd_session_start(dwc_otg_core_if_t * core_if) ++{ ++ if (core_if->hcd_cb && core_if->hcd_cb->session_start) { ++ core_if->hcd_cb->session_start(core_if->hcd_cb->p); ++ } ++} ++ ++#ifdef CONFIG_USB_DWC_OTG_LPM ++/** ++ * Inform the HCD about LPM sleep. ++ * Helper function for using the HCD callbacks. ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ */ ++static inline void cil_hcd_sleep(dwc_otg_core_if_t * core_if) ++{ ++ if (core_if->hcd_cb && core_if->hcd_cb->sleep) { ++ core_if->hcd_cb->sleep(core_if->hcd_cb->p); ++ } ++} ++#endif ++ ++/** Resume the HCD. Helper function for using the HCD callbacks. ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ */ ++static inline void cil_hcd_resume(dwc_otg_core_if_t * core_if) ++{ ++ if (core_if->hcd_cb && core_if->hcd_cb->resume_wakeup) { ++ core_if->hcd_cb->resume_wakeup(core_if->hcd_cb->p); ++ } ++} ++ ++/** Start the PCD. Helper function for using the PCD callbacks. ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ */ ++static inline void cil_pcd_start(dwc_otg_core_if_t * core_if) ++{ ++ if (core_if->pcd_cb && core_if->pcd_cb->start) { ++ core_if->pcd_cb->start(core_if->pcd_cb->p); ++ } ++} ++ ++/** Stop the PCD. Helper function for using the PCD callbacks. ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ */ ++static inline void cil_pcd_stop(dwc_otg_core_if_t * core_if) ++{ ++ if (core_if->pcd_cb && core_if->pcd_cb->stop) { ++ core_if->pcd_cb->stop(core_if->pcd_cb->p); ++ } ++} ++ ++/** Suspend the PCD. Helper function for using the PCD callbacks. ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ */ ++static inline void cil_pcd_suspend(dwc_otg_core_if_t * core_if) ++{ ++ if (core_if->pcd_cb && core_if->pcd_cb->suspend) { ++ core_if->pcd_cb->suspend(core_if->pcd_cb->p); ++ } ++} ++ ++/** Resume the PCD. Helper function for using the PCD callbacks. ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ */ ++static inline void cil_pcd_resume(dwc_otg_core_if_t * core_if) ++{ ++ if (core_if->pcd_cb && core_if->pcd_cb->resume_wakeup) { ++ core_if->pcd_cb->resume_wakeup(core_if->pcd_cb->p); ++ } ++} ++ ++////////////////////////////////////////////////////////////////////// ++ + #endif +Index: linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_cil_intr.c +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/dwc_otg_cil_intr.c 2013-07-26 19:31:23.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_cil_intr.c 2013-07-26 19:34:44.000000000 +0000 +@@ -1,8 +1,8 @@ + /* ========================================================================== + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_cil_intr.c $ +- * $Revision: #15 $ +- * $Date: 2009/04/15 $ +- * $Change: 1234129 $ ++ * $Revision: #31 $ ++ * $Date: 2011/10/24 $ ++ * $Change: 1871286 $ + * + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless +@@ -42,6 +42,9 @@ + #include "dwc_os.h" + #include "dwc_otg_regs.h" + #include "dwc_otg_cil.h" ++#include "dwc_otg_driver.h" ++#include "dwc_otg_pcd.h" ++#include "dwc_otg_hcd.h" + + #ifdef DEBUG + inline const char *op_state_str(dwc_otg_core_if_t * core_if) +@@ -67,125 +70,10 @@ + /* Clear interrupt */ + gintsts.d32 = 0; + gintsts.b.modemismatch = 1; +- dwc_write_reg32(&core_if->core_global_regs->gintsts, gintsts.d32); ++ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32); + return 1; + } + +-/** Start the HCD. Helper function for using the HCD callbacks. +- * +- * @param core_if Programming view of DWC_otg controller. +- */ +-static inline void hcd_start(dwc_otg_core_if_t * core_if) +-{ +- if (core_if->hcd_cb && core_if->hcd_cb->start) { +- core_if->hcd_cb->start(core_if->hcd_cb->p); +- } +-} +- +-/** Stop the HCD. Helper function for using the HCD callbacks. +- * +- * @param core_if Programming view of DWC_otg controller. +- */ +-static inline void hcd_stop(dwc_otg_core_if_t * core_if) +-{ +- if (core_if->hcd_cb && core_if->hcd_cb->stop) { +- core_if->hcd_cb->stop(core_if->hcd_cb->p); +- } +-} +- +-/** Disconnect the HCD. Helper function for using the HCD callbacks. +- * +- * @param core_if Programming view of DWC_otg controller. +- */ +-static inline void hcd_disconnect(dwc_otg_core_if_t * core_if) +-{ +- if (core_if->hcd_cb && core_if->hcd_cb->disconnect) { +- core_if->hcd_cb->disconnect(core_if->hcd_cb->p); +- } +-} +- +-/** Inform the HCD the a New Session has begun. Helper function for +- * using the HCD callbacks. +- * +- * @param core_if Programming view of DWC_otg controller. +- */ +-static inline void hcd_session_start(dwc_otg_core_if_t * core_if) +-{ +- if (core_if->hcd_cb && core_if->hcd_cb->session_start) { +- core_if->hcd_cb->session_start(core_if->hcd_cb->p); +- } +-} +- +-#ifdef CONFIG_USB_DWC_OTG_LPM +-/** +- * Inform the HCD about LPM sleep. +- * Helper function for using the HCD callbacks. +- * +- * @param core_if Programming view of DWC_otg controller. +- */ +-static inline void hcd_sleep(dwc_otg_core_if_t * core_if) +-{ +- if (core_if->hcd_cb && core_if->hcd_cb->sleep) { +- core_if->hcd_cb->sleep(core_if->hcd_cb->p); +- } +-} +-#endif +- +-/** Resume the HCD. Helper function for using the HCD callbacks. +- * +- * @param core_if Programming view of DWC_otg controller. +- */ +-static inline void hcd_resume(dwc_otg_core_if_t * core_if) +-{ +- if (core_if->hcd_cb && core_if->hcd_cb->resume_wakeup) { +- core_if->hcd_cb->resume_wakeup(core_if->hcd_cb->p); +- } +-} +- +-/** Start the PCD. Helper function for using the PCD callbacks. +- * +- * @param core_if Programming view of DWC_otg controller. +- */ +-static inline void pcd_start(dwc_otg_core_if_t * core_if) +-{ +- if (core_if->pcd_cb && core_if->pcd_cb->start) { +- core_if->pcd_cb->start(core_if->pcd_cb->p); +- } +-} +- +-/** Stop the PCD. Helper function for using the PCD callbacks. +- * +- * @param core_if Programming view of DWC_otg controller. +- */ +-static inline void pcd_stop(dwc_otg_core_if_t * core_if) +-{ +- if (core_if->pcd_cb && core_if->pcd_cb->stop) { +- core_if->pcd_cb->stop(core_if->pcd_cb->p); +- } +-} +- +-/** Suspend the PCD. Helper function for using the PCD callbacks. +- * +- * @param core_if Programming view of DWC_otg controller. +- */ +-static inline void pcd_suspend(dwc_otg_core_if_t * core_if) +-{ +- if (core_if->pcd_cb && core_if->pcd_cb->suspend) { +- core_if->pcd_cb->suspend(core_if->pcd_cb->p); +- } +-} +- +-/** Resume the PCD. Helper function for using the PCD callbacks. +- * +- * @param core_if Programming view of DWC_otg controller. +- */ +-static inline void pcd_resume(dwc_otg_core_if_t * core_if) +-{ +- if (core_if->pcd_cb && core_if->pcd_cb->resume_wakeup) { +- core_if->pcd_cb->resume_wakeup(core_if->pcd_cb->p); +- } +-} +- + /** + * This function handles the OTG Interrupts. It reads the OTG + * Interrupt Register (GOTGINT) to determine what interrupt has +@@ -199,9 +87,10 @@ + gotgint_data_t gotgint; + gotgctl_data_t gotgctl; + gintmsk_data_t gintmsk; ++ gpwrdn_data_t gpwrdn; + +- gotgint.d32 = dwc_read_reg32(&global_regs->gotgint); +- gotgctl.d32 = dwc_read_reg32(&global_regs->gotgctl); ++ gotgint.d32 = DWC_READ_REG32(&global_regs->gotgint); ++ gotgctl.d32 = DWC_READ_REG32(&global_regs->gotgctl); + DWC_DEBUGPL(DBG_CIL, "++OTG Interrupt gotgint=%0x [%s]\n", gotgint.d32, + op_state_str(core_if)); + +@@ -209,10 +98,10 @@ + DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: " + "Session End Detected++ (%s)\n", + op_state_str(core_if)); +- gotgctl.d32 = dwc_read_reg32(&global_regs->gotgctl); ++ gotgctl.d32 = DWC_READ_REG32(&global_regs->gotgctl); + + if (core_if->op_state == B_HOST) { +- pcd_start(core_if); ++ cil_pcd_start(core_if); + core_if->op_state = B_PERIPHERAL; + } else { + /* If not B_HOST and Device HNP still set. HNP +@@ -227,26 +116,50 @@ + /* Reset PCD and Gadget driver to a + * clean state. */ + core_if->lx_state = DWC_OTG_L0; +- pcd_stop(core_if); ++ DWC_SPINUNLOCK(core_if->lock); ++ cil_pcd_stop(core_if); ++ DWC_SPINLOCK(core_if->lock); ++ ++ if (core_if->adp_enable) { ++ if (core_if->power_down == 2) { ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pwrdnswtch = 1; ++ DWC_MODIFY_REG32(&core_if-> ++ core_global_regs-> ++ gpwrdn, gpwrdn.d32, 0); ++ } ++ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pmuintsel = 1; ++ gpwrdn.b.pmuactv = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs-> ++ gpwrdn, 0, gpwrdn.d32); ++ ++ dwc_otg_adp_sense_start(core_if); ++ } + } ++ + gotgctl.d32 = 0; + gotgctl.b.devhnpen = 1; +- dwc_modify_reg32(&global_regs->gotgctl, gotgctl.d32, 0); ++ DWC_MODIFY_REG32(&global_regs->gotgctl, gotgctl.d32, 0); + } + if (gotgint.b.sesreqsucstschng) { + DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: " + "Session Reqeust Success Status Change++\n"); +- gotgctl.d32 = dwc_read_reg32(&global_regs->gotgctl); ++ gotgctl.d32 = DWC_READ_REG32(&global_regs->gotgctl); + if (gotgctl.b.sesreqscs) { ++ + if ((core_if->core_params->phy_type == + DWC_PHY_TYPE_PARAM_FS) && (core_if->core_params->i2c_enable)) { + core_if->srp_success = 1; + } else { +- pcd_resume(core_if); ++ DWC_SPINUNLOCK(core_if->lock); ++ cil_pcd_resume(core_if); ++ DWC_SPINLOCK(core_if->lock); + /* Clear Session Request */ + gotgctl.d32 = 0; + gotgctl.b.sesreq = 1; +- dwc_modify_reg32(&global_regs->gotgctl, ++ DWC_MODIFY_REG32(&global_regs->gotgctl, + gotgctl.d32, 0); + } + } +@@ -254,7 +167,7 @@ + if (gotgint.b.hstnegsucstschng) { + /* Print statements during the HNP interrupt handling + * can cause it to fail.*/ +- gotgctl.d32 = dwc_read_reg32(&global_regs->gotgctl); ++ gotgctl.d32 = DWC_READ_REG32(&global_regs->gotgctl); + if (gotgctl.b.hstnegscs) { + if (dwc_otg_is_host_mode(core_if)) { + core_if->op_state = B_HOST; +@@ -270,20 +183,23 @@ + */ + gintmsk.d32 = 0; + gintmsk.b.sofintr = 1; +- dwc_modify_reg32(&global_regs->gintmsk, ++ DWC_MODIFY_REG32(&global_regs->gintmsk, + gintmsk.d32, 0); +- pcd_stop(core_if); ++ /* Call callback function with spin lock released */ ++ DWC_SPINUNLOCK(core_if->lock); ++ cil_pcd_stop(core_if); + /* + * Initialize the Core for Host mode. + */ +- hcd_start(core_if); ++ cil_hcd_start(core_if); ++ DWC_SPINLOCK(core_if->lock); + core_if->op_state = B_HOST; + } + } else { + gotgctl.d32 = 0; + gotgctl.b.hnpreq = 1; + gotgctl.b.devhnpen = 1; +- dwc_modify_reg32(&global_regs->gotgctl, gotgctl.d32, 0); ++ DWC_MODIFY_REG32(&global_regs->gotgctl, gotgctl.d32, 0); + DWC_DEBUGPL(DBG_ANY, "HNP Failed\n"); + __DWC_ERROR("Device Not Connected/Responding\n"); + } +@@ -301,8 +217,10 @@ + if (dwc_otg_is_device_mode(core_if)) { + DWC_DEBUGPL(DBG_ANY, "a_suspend->a_peripheral (%d)\n", + core_if->op_state); +- hcd_disconnect(core_if); +- pcd_start(core_if); ++ DWC_SPINUNLOCK(core_if->lock); ++ cil_hcd_disconnect(core_if); ++ cil_pcd_start(core_if); ++ DWC_SPINLOCK(core_if->lock); + core_if->op_state = A_PERIPHERAL; + } else { + /* +@@ -316,9 +234,11 @@ + */ + gintmsk.d32 = 0; + gintmsk.b.sofintr = 1; +- dwc_modify_reg32(&global_regs->gintmsk, gintmsk.d32, 0); +- pcd_stop(core_if); +- hcd_start(core_if); ++ DWC_MODIFY_REG32(&global_regs->gintmsk, gintmsk.d32, 0); ++ DWC_SPINUNLOCK(core_if->lock); ++ cil_pcd_stop(core_if); ++ cil_hcd_start(core_if); ++ DWC_SPINLOCK(core_if->lock); + core_if->op_state = A_HOST; + } + } +@@ -331,7 +251,7 @@ + } + + /* Clear GOTGINT */ +- dwc_write_reg32(&core_if->core_global_regs->gotgint, gotgint.d32); ++ DWC_WRITE_REG32(&core_if->core_global_regs->gotgint, gotgint.d32); + + return 1; + } +@@ -342,7 +262,7 @@ + uint32_t count = 0; + gotgctl_data_t gotgctl = {.d32 = 0 }; + +- gotgctl.d32 = dwc_read_reg32(&core_if->core_global_regs->gotgctl); ++ gotgctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->gotgctl); + DWC_DEBUGPL(DBG_CIL, "gotgctl=%0x\n", gotgctl.d32); + DWC_DEBUGPL(DBG_CIL, "gotgctl.b.conidsts=%d\n", gotgctl.b.conidsts); + +@@ -362,7 +282,7 @@ + core_if->op_state = B_PERIPHERAL; + dwc_otg_core_init(core_if); + dwc_otg_enable_global_interrupts(core_if); +- pcd_start(core_if); ++ cil_pcd_start(core_if); + } else { + /* A-Device connector (Host Mode) */ + while (!dwc_otg_is_host_mode(core_if)) { +@@ -381,7 +301,7 @@ + */ + dwc_otg_core_init(core_if); + dwc_otg_enable_global_interrupts(core_if); +- hcd_start(core_if); ++ cil_hcd_start(core_if); + } + } + +@@ -389,7 +309,7 @@ + * This function handles the Connector ID Status Change Interrupt. It + * reads the OTG Interrupt Register (GOTCTL) to determine whether this + * is a Device to Host Mode transition or a Host Mode to Device +- * Transition. ++ * Transition. + * + * This only occurs when the cable is connected/removed from the PHY + * connector. +@@ -410,21 +330,26 @@ + gintsts_data_t gintsts = {.d32 = 0 }; + + gintmsk.b.sofintr = 1; +- dwc_modify_reg32(&core_if->core_global_regs->gintmsk, gintmsk.d32, 0); ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, gintmsk.d32, 0); + + DWC_DEBUGPL(DBG_CIL, + " ++Connector ID Status Change Interrupt++ (%s)\n", + (dwc_otg_is_host_mode(core_if) ? "Host" : "Device")); ++ ++ DWC_SPINUNLOCK(core_if->lock); + + /* + * Need to schedule a work, as there are possible DELAY function calls ++ * Release lock before scheduling workq as it holds spinlock during scheduling + */ ++ + DWC_WORKQ_SCHEDULE(core_if->wq_otg, w_conn_id_status_change, + core_if, "connection id status change"); ++ DWC_SPINLOCK(core_if->lock); + + /* Set flag and clear interrupt */ + gintsts.b.conidstschng = 1; +- dwc_write_reg32(&core_if->core_global_regs->gintsts, gintsts.d32); ++ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32); + + return 1; + } +@@ -440,7 +365,6 @@ + */ + int32_t dwc_otg_handle_session_req_intr(dwc_otg_core_if_t * core_if) + { +- hprt0_data_t hprt0; + gintsts_data_t gintsts; + + #ifndef DWC_HOST_ONLY +@@ -449,23 +373,24 @@ + if (dwc_otg_is_device_mode(core_if)) { + DWC_PRINTF("SRP: Device mode\n"); + } else { ++ hprt0_data_t hprt0; + DWC_PRINTF("SRP: Host mode\n"); + + /* Turn on the port power bit. */ + hprt0.d32 = dwc_otg_read_hprt0(core_if); + hprt0.b.prtpwr = 1; +- dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32); ++ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32); + + /* Start the Connection timer. So a message can be displayed + * if connect does not occur within 10 seconds. */ +- hcd_session_start(core_if); ++ cil_hcd_session_start(core_if); + } + #endif + + /* Clear interrupt */ + gintsts.d32 = 0; + gintsts.b.sessreqintr = 1; +- dwc_write_reg32(&core_if->core_global_regs->gintsts, gintsts.d32); ++ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32); + + return 1; + } +@@ -482,22 +407,21 @@ + pcgcctl_data_t pcgcctl = {.d32 = 0 }; + /* Restart the Phy Clock */ + pcgcctl.b.stoppclk = 1; +- dwc_modify_reg32(core_if->pcgcctl, pcgcctl.d32, 0); ++ DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32, 0); + dwc_udelay(10); +-#endif //0 ++#endif //0 + hprt0.d32 = dwc_otg_read_hprt0(core_if); + DWC_DEBUGPL(DBG_ANY, "Resume: HPRT0=%0x\n", hprt0.d32); + // dwc_mdelay(70); + hprt0.b.prtres = 0; /* Resume */ +- dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32); ++ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32); + DWC_DEBUGPL(DBG_ANY, "Clear Resume: HPRT0=%0x\n", +- dwc_read_reg32(core_if->host_if->hprt0)); ++ DWC_READ_REG32(core_if->host_if->hprt0)); + +- hcd_resume(core_if); ++ cil_hcd_resume(core_if); + + /** Change to L0 state*/ + core_if->lx_state = DWC_OTG_L0; +- + } + + /** +@@ -519,42 +443,43 @@ + if (dwc_otg_is_device_mode(core_if)) { + dctl_data_t dctl = {.d32 = 0 }; + DWC_DEBUGPL(DBG_PCD, "DSTS=0x%0x\n", +- dwc_read_reg32(&core_if->dev_if->dev_global_regs-> +- dsts)); ++ DWC_READ_REG32(&core_if->dev_if-> ++ dev_global_regs->dsts)); + if (core_if->lx_state == DWC_OTG_L2) { + #ifdef PARTIAL_POWER_DOWN + if (core_if->hwcfg4.b.power_optimiz) { + pcgcctl_data_t power = {.d32 = 0 }; + +- power.d32 = dwc_read_reg32(core_if->pcgcctl); ++ power.d32 = DWC_READ_REG32(core_if->pcgcctl); + DWC_DEBUGPL(DBG_CIL, "PCGCCTL=%0x\n", + power.d32); + + power.b.stoppclk = 0; +- dwc_write_reg32(core_if->pcgcctl, power.d32); ++ DWC_WRITE_REG32(core_if->pcgcctl, power.d32); + + power.b.pwrclmp = 0; +- dwc_write_reg32(core_if->pcgcctl, power.d32); ++ DWC_WRITE_REG32(core_if->pcgcctl, power.d32); + + power.b.rstpdwnmodule = 0; +- dwc_write_reg32(core_if->pcgcctl, power.d32); ++ DWC_WRITE_REG32(core_if->pcgcctl, power.d32); + } + #endif +- /* Clear the Remote Wakeup Signalling */ ++ /* Clear the Remote Wakeup Signaling */ + dctl.b.rmtwkupsig = 1; +- dwc_modify_reg32(&core_if->dev_if->dev_global_regs-> +- dctl, dctl.d32, 0); ++ DWC_MODIFY_REG32(&core_if->dev_if-> ++ dev_global_regs->dctl, dctl.d32, 0); + ++ DWC_SPINUNLOCK(core_if->lock); + if (core_if->pcd_cb && core_if->pcd_cb->resume_wakeup) { +- core_if->pcd_cb->resume_wakeup(core_if->pcd_cb-> +- p); ++ core_if->pcd_cb->resume_wakeup(core_if->pcd_cb->p); + } ++ DWC_SPINLOCK(core_if->lock); + } else { + glpmcfg_data_t lpmcfg; + lpmcfg.d32 = +- dwc_read_reg32(&core_if->core_global_regs->glpmcfg); ++ DWC_READ_REG32(&core_if->core_global_regs->glpmcfg); + lpmcfg.b.hird_thres &= (~(1 << 4)); +- dwc_write_reg32(&core_if->core_global_regs->glpmcfg, ++ DWC_WRITE_REG32(&core_if->core_global_regs->glpmcfg, + lpmcfg.d32); + } + /** Change to L0 state*/ +@@ -565,8 +490,7 @@ + + /* Restart the Phy Clock */ + pcgcctl.b.stoppclk = 1; +- dwc_modify_reg32(core_if->pcgcctl, pcgcctl.d32, 0); +- ++ DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32, 0); + DWC_TIMER_SCHEDULE(core_if->wkp_timer, 71); + } else { + /** Change to L0 state*/ +@@ -577,14 +501,434 @@ + /* Clear interrupt */ + gintsts.d32 = 0; + gintsts.b.wkupintr = 1; +- dwc_write_reg32(&core_if->core_global_regs->gintsts, gintsts.d32); ++ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32); ++ ++ return 1; ++} ++ ++/** ++ * This interrupt indicates that the Wakeup Logic has detected a ++ * Device disconnect. ++ */ ++static int32_t dwc_otg_handle_pwrdn_disconnect_intr(dwc_otg_core_if_t *core_if) ++{ ++ gpwrdn_data_t gpwrdn = { .d32 = 0 }; ++ gpwrdn_data_t gpwrdn_temp = { .d32 = 0 }; ++ gpwrdn_temp.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn); ++ ++ DWC_PRINTF("%s called\n", __FUNCTION__); ++ ++ if (!core_if->hibernation_suspend) { ++ DWC_PRINTF("Already exited from Hibernation\n"); ++ return 1; ++ } ++ ++ /* Switch on the voltage to the core */ ++ gpwrdn.b.pwrdnswtch = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ dwc_udelay(10); ++ ++ /* Reset the core */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pwrdnrstn = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ dwc_udelay(10); ++ ++ /* Disable power clamps*/ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pwrdnclmp = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ ++ /* Remove reset the core signal */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pwrdnrstn = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32); ++ dwc_udelay(10); ++ ++ /* Disable PMU interrupt */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pmuintsel = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ ++ core_if->hibernation_suspend = 0; ++ ++ /* Disable PMU */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pmuactv = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ dwc_udelay(10); ++ ++ if (gpwrdn_temp.b.idsts) { ++ core_if->op_state = B_PERIPHERAL; ++ dwc_otg_core_init(core_if); ++ dwc_otg_enable_global_interrupts(core_if); ++ cil_pcd_start(core_if); ++ } else { ++ core_if->op_state = A_HOST; ++ dwc_otg_core_init(core_if); ++ dwc_otg_enable_global_interrupts(core_if); ++ cil_hcd_start(core_if); ++ } ++ ++ return 1; ++} + ++/** ++ * This interrupt indicates that the Wakeup Logic has detected a ++ * remote wakeup sequence. ++ */ ++static int32_t dwc_otg_handle_pwrdn_wakeup_detected_intr(dwc_otg_core_if_t * core_if) ++{ ++ gpwrdn_data_t gpwrdn = {.d32 = 0 }; ++ DWC_DEBUGPL(DBG_ANY, ++ "++Powerdown Remote Wakeup Detected Interrupt++\n"); ++ ++ if (!core_if->hibernation_suspend) { ++ DWC_PRINTF("Already exited from Hibernation\n"); ++ return 1; ++ } ++ ++ gpwrdn.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn); ++ if (gpwrdn.b.idsts) { // Device Mode ++ if ((core_if->power_down == 2) ++ && (core_if->hibernation_suspend == 1)) { ++ dwc_otg_device_hibernation_restore(core_if, 0, 0); ++ } ++ } else { ++ if ((core_if->power_down == 2) ++ && (core_if->hibernation_suspend == 1)) { ++ dwc_otg_host_hibernation_restore(core_if, 1, 0); ++ } ++ } + return 1; + } + +-/** ++static int32_t dwc_otg_handle_pwrdn_idsts_change(dwc_otg_device_t *otg_dev) ++{ ++ gpwrdn_data_t gpwrdn = {.d32 = 0 }; ++ gpwrdn_data_t gpwrdn_temp = {.d32 = 0 }; ++ dwc_otg_core_if_t *core_if = otg_dev->core_if; ++ ++ DWC_DEBUGPL(DBG_ANY, "%s called\n", __FUNCTION__); ++ gpwrdn_temp.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn); ++ if (core_if->power_down == 2) ++ { ++ if (!core_if->hibernation_suspend) { ++ DWC_PRINTF("Already exited from Hibernation\n"); ++ return 1; ++ } ++ DWC_DEBUGPL(DBG_ANY, "Exit from hibernation on ID sts change\n"); ++ /* Switch on the voltage to the core */ ++ gpwrdn.b.pwrdnswtch = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ dwc_udelay(10); ++ ++ /* Reset the core */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pwrdnrstn = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ dwc_udelay(10); ++ ++ /* Disable power clamps */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pwrdnclmp = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ ++ /* Remove reset the core signal */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pwrdnrstn = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32); ++ dwc_udelay(10); ++ ++ /* Disable PMU interrupt */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pmuintsel = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ ++ /*Indicates that we are exiting from hibernation */ ++ core_if->hibernation_suspend = 0; ++ ++ /* Disable PMU */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pmuactv = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ dwc_udelay(10); ++ ++ gpwrdn.d32 = core_if->gr_backup->gpwrdn_local; ++ if (gpwrdn.b.dis_vbus == 1) { ++ gpwrdn.d32 = 0; ++ gpwrdn.b.dis_vbus = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ } ++ ++ if (gpwrdn_temp.b.idsts) { ++ core_if->op_state = B_PERIPHERAL; ++ dwc_otg_core_init(core_if); ++ dwc_otg_enable_global_interrupts(core_if); ++ cil_pcd_start(core_if); ++ } else { ++ core_if->op_state = A_HOST; ++ dwc_otg_core_init(core_if); ++ dwc_otg_enable_global_interrupts(core_if); ++ cil_hcd_start(core_if); ++ } ++ } ++ ++ if (core_if->adp_enable) ++ { ++ uint8_t is_host = 0; ++ DWC_SPINUNLOCK(core_if->lock); ++ /* Change the core_if's lock to hcd/pcd lock depend on mode? */ ++#ifndef DWC_HOST_ONLY ++ if (gpwrdn_temp.b.idsts) ++ core_if->lock = otg_dev->pcd->lock; ++#endif ++#ifndef DWC_DEVICE_ONLY ++ if (!gpwrdn_temp.b.idsts) { ++ core_if->lock = otg_dev->hcd->lock; ++ is_host = 1; ++ } ++#endif ++ DWC_PRINTF("RESTART ADP\n"); ++ if (core_if->adp.probe_enabled) ++ dwc_otg_adp_probe_stop(core_if); ++ if (core_if->adp.sense_enabled) ++ dwc_otg_adp_sense_stop(core_if); ++ if (core_if->adp.sense_timer_started) ++ DWC_TIMER_CANCEL(core_if->adp.sense_timer); ++ if (core_if->adp.vbuson_timer_started) ++ DWC_TIMER_CANCEL(core_if->adp.vbuson_timer); ++ core_if->adp.probe_timer_values[0] = -1; ++ core_if->adp.probe_timer_values[1] = -1; ++ core_if->adp.sense_timer_started = 0; ++ core_if->adp.vbuson_timer_started = 0; ++ core_if->adp.probe_counter = 0; ++ core_if->adp.gpwrdn = 0; ++ ++ /* Disable PMU and restart ADP */ ++ gpwrdn_temp.d32 = 0; ++ gpwrdn_temp.b.pmuactv = 1; ++ gpwrdn_temp.b.pmuintsel = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ DWC_PRINTF("Check point 1\n"); ++ dwc_mdelay(110); ++ dwc_otg_adp_start(core_if, is_host); ++ DWC_SPINLOCK(core_if->lock); ++ } ++ ++ ++ return 1; ++} ++ ++static int32_t dwc_otg_handle_pwrdn_session_change(dwc_otg_core_if_t * core_if) ++{ ++ gpwrdn_data_t gpwrdn = {.d32 = 0 }; ++ int32_t otg_cap_param = core_if->core_params->otg_cap; ++ DWC_DEBUGPL(DBG_ANY, "%s called\n", __FUNCTION__); ++ ++ gpwrdn.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn); ++ if (core_if->power_down == 2) { ++ if (!core_if->hibernation_suspend) { ++ DWC_PRINTF("Already exited from Hibernation\n"); ++ return 1; ++ } ++ ++ if ((otg_cap_param != DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE || ++ otg_cap_param != DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE) && ++ gpwrdn.b.bsessvld == 0) { ++ /* Save gpwrdn register for further usage if stschng interrupt */ ++ core_if->gr_backup->gpwrdn_local = ++ DWC_READ_REG32(&core_if->core_global_regs->gpwrdn); ++ /*Exit from ISR and wait for stschng interrupt with bsessvld = 1 */ ++ return 1; ++ } ++ ++ /* Switch on the voltage to the core */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pwrdnswtch = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ dwc_udelay(10); ++ ++ /* Reset the core */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pwrdnrstn = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ dwc_udelay(10); ++ ++ /* Disable power clamps */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pwrdnclmp = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ ++ /* Remove reset the core signal */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pwrdnrstn = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32); ++ dwc_udelay(10); ++ ++ /* Disable PMU interrupt */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pmuintsel = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ dwc_udelay(10); ++ ++ /*Indicates that we are exiting from hibernation */ ++ core_if->hibernation_suspend = 0; ++ ++ /* Disable PMU */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pmuactv = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ dwc_udelay(10); ++ ++ core_if->op_state = B_PERIPHERAL; ++ dwc_otg_core_init(core_if); ++ dwc_otg_enable_global_interrupts(core_if); ++ cil_pcd_start(core_if); ++ ++ if (otg_cap_param == DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE || ++ otg_cap_param == DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE) { ++ /* ++ * Initiate SRP after initial ADP probe. ++ */ ++ dwc_otg_initiate_srp(core_if); ++ } ++ } ++ ++ return 1; ++} ++/** ++ * This interrupt indicates that the Wakeup Logic has detected a ++ * status change either on IDDIG or BSessVld. ++ */ ++static uint32_t dwc_otg_handle_pwrdn_stschng_intr(dwc_otg_device_t *otg_dev) ++{ ++ int retval; ++ gpwrdn_data_t gpwrdn = {.d32 = 0 }; ++ gpwrdn_data_t gpwrdn_temp = {.d32 = 0 }; ++ dwc_otg_core_if_t *core_if = otg_dev->core_if; ++ ++ DWC_PRINTF("%s called\n", __FUNCTION__); ++ ++ if (core_if->power_down == 2) { ++ if (core_if->hibernation_suspend <= 0) { ++ DWC_PRINTF("Already exited from Hibernation\n"); ++ return 1; ++ } else ++ gpwrdn_temp.d32 = core_if->gr_backup->gpwrdn_local; ++ ++ } else { ++ gpwrdn_temp.d32 = core_if->adp.gpwrdn; ++ } ++ ++ gpwrdn.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn); ++ ++ if (gpwrdn.b.idsts ^ gpwrdn_temp.b.idsts) { ++ retval = dwc_otg_handle_pwrdn_idsts_change(otg_dev); ++ } else if (gpwrdn.b.bsessvld ^ gpwrdn_temp.b.bsessvld) { ++ retval = dwc_otg_handle_pwrdn_session_change(core_if); ++ } ++ ++ return retval; ++} ++ ++/** ++ * This interrupt indicates that the Wakeup Logic has detected a ++ * SRP. ++ */ ++static int32_t dwc_otg_handle_pwrdn_srp_intr(dwc_otg_core_if_t * core_if) ++{ ++ gpwrdn_data_t gpwrdn = {.d32 = 0 }; ++ ++ DWC_PRINTF("%s called\n", __FUNCTION__); ++ ++ if (!core_if->hibernation_suspend) { ++ DWC_PRINTF("Already exited from Hibernation\n"); ++ return 1; ++ } ++#ifdef DWC_DEV_SRPCAP ++ if (core_if->pwron_timer_started) { ++ core_if->pwron_timer_started = 0; ++ DWC_TIMER_CANCEL(core_if->pwron_timer); ++ } ++#endif ++ ++ /* Switch on the voltage to the core */ ++ gpwrdn.b.pwrdnswtch = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ dwc_udelay(10); ++ ++ /* Reset the core */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pwrdnrstn = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ dwc_udelay(10); ++ ++ /* Disable power clamps */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pwrdnclmp = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ ++ /* Remove reset the core signal */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pwrdnrstn = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32); ++ dwc_udelay(10); ++ ++ /* Disable PMU interrupt */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pmuintsel = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ ++ /* Indicates that we are exiting from hibernation */ ++ core_if->hibernation_suspend = 0; ++ ++ /* Disable PMU */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pmuactv = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ dwc_udelay(10); ++ ++ /* Programm Disable VBUS to 0 */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.dis_vbus = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ ++ /*Initialize the core as Host */ ++ core_if->op_state = A_HOST; ++ dwc_otg_core_init(core_if); ++ dwc_otg_enable_global_interrupts(core_if); ++ cil_hcd_start(core_if); ++ ++ return 1; ++} ++ ++/** This interrupt indicates that restore command after Hibernation ++ * was completed by the core. */ ++int32_t dwc_otg_handle_restore_done_intr(dwc_otg_core_if_t * core_if) ++{ ++ pcgcctl_data_t pcgcctl; ++ DWC_DEBUGPL(DBG_ANY, "++Restore Done Interrupt++\n"); ++ ++ //TODO De-assert restore signal. 8.a ++ pcgcctl.d32 = DWC_READ_REG32(core_if->pcgcctl); ++ if (pcgcctl.b.restoremode == 1) { ++ gintmsk_data_t gintmsk = {.d32 = 0 }; ++ /* ++ * If restore mode is Remote Wakeup, ++ * unmask Remote Wakeup interrupt. ++ */ ++ gintmsk.b.wkupintr = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, ++ 0, gintmsk.d32); ++ } ++ ++ return 1; ++} ++ ++/** + * This interrupt indicates that a device has been disconnected from +- * the root port. ++ * the root port. + */ + int32_t dwc_otg_handle_disconnect_intr(dwc_otg_core_if_t * core_if) + { +@@ -599,13 +943,15 @@ + if (core_if->op_state == B_HOST) { + /* If in device mode Disconnect and stop the HCD, then + * start the PCD. */ +- hcd_disconnect(core_if); +- pcd_start(core_if); ++ DWC_SPINUNLOCK(core_if->lock); ++ cil_hcd_disconnect(core_if); ++ cil_pcd_start(core_if); ++ DWC_SPINLOCK(core_if->lock); + core_if->op_state = B_PERIPHERAL; + } else if (dwc_otg_is_device_mode(core_if)) { + gotgctl_data_t gotgctl = {.d32 = 0 }; + gotgctl.d32 = +- dwc_read_reg32(&core_if->core_global_regs->gotgctl); ++ DWC_READ_REG32(&core_if->core_global_regs->gotgctl); + if (gotgctl.b.hstsethnpen == 1) { + /* Do nothing, if HNP in process the OTG + * interrupt "Host Negotiation Detected" +@@ -614,8 +960,10 @@ + } else if (gotgctl.b.devhnpen == 0) { + /* If in device mode Disconnect and stop the HCD, then + * start the PCD. */ +- hcd_disconnect(core_if); +- pcd_start(core_if); ++ DWC_SPINUNLOCK(core_if->lock); ++ cil_hcd_disconnect(core_if); ++ cil_pcd_start(core_if); ++ DWC_SPINLOCK(core_if->lock); + core_if->op_state = B_PERIPHERAL; + } else { + DWC_DEBUGPL(DBG_ANY, "!a_peripheral && !devhnpen\n"); +@@ -623,7 +971,25 @@ + } else { + if (core_if->op_state == A_HOST) { + /* A-Cable still connected but device disconnected. */ +- hcd_disconnect(core_if); ++ cil_hcd_disconnect(core_if); ++ if (core_if->adp_enable) { ++ gpwrdn_data_t gpwrdn = { .d32 = 0 }; ++ cil_hcd_stop(core_if); ++ /* Enable Power Down Logic */ ++ gpwrdn.b.pmuintsel = 1; ++ gpwrdn.b.pmuactv = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32); ++ dwc_otg_adp_probe_start(core_if); ++ ++ /* Power off the core */ ++ if (core_if->power_down == 2) { ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pwrdnswtch = 1; ++ DWC_MODIFY_REG32(&core_if-> ++ core_global_regs-> ++ gpwrdn, gpwrdn.d32, 0); ++ } ++ } + } + } + #endif +@@ -632,14 +998,14 @@ + + gintsts.d32 = 0; + gintsts.b.disconnect = 1; +- dwc_write_reg32(&core_if->core_global_regs->gintsts, gintsts.d32); ++ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32); + return 1; + } + + /** + * This interrupt indicates that SUSPEND state has been detected on + * the USB. +- * ++ * + * For HNP the USB Suspend interrupt signals the change from + * "a_peripheral" to "a_host". + * +@@ -650,6 +1016,7 @@ + { + dsts_data_t dsts; + gintsts_data_t gintsts; ++ dcfg_data_t dcfg; + + DWC_DEBUGPL(DBG_ANY, "USB SUSPEND\n"); + +@@ -657,7 +1024,7 @@ + /* Check the Device status register to determine if the Suspend + * state is active. */ + dsts.d32 = +- dwc_read_reg32(&core_if->dev_if->dev_global_regs->dsts); ++ DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts); + DWC_DEBUGPL(DBG_PCD, "DSTS=0x%0x\n", dsts.d32); + DWC_DEBUGPL(DBG_PCD, "DSTS.Suspend Status=%d " + "HWCFG4.power Optimize=%d\n", +@@ -671,26 +1038,118 @@ + DWC_DEBUGPL(DBG_CIL, "suspend\n"); + + power.b.pwrclmp = 1; +- dwc_write_reg32(core_if->pcgcctl, power.d32); ++ DWC_WRITE_REG32(core_if->pcgcctl, power.d32); + + power.b.rstpdwnmodule = 1; +- dwc_modify_reg32(core_if->pcgcctl, 0, power.d32); ++ DWC_MODIFY_REG32(core_if->pcgcctl, 0, power.d32); + + power.b.stoppclk = 1; +- dwc_modify_reg32(core_if->pcgcctl, 0, power.d32); ++ DWC_MODIFY_REG32(core_if->pcgcctl, 0, power.d32); + + } else { + DWC_DEBUGPL(DBG_ANY, "disconnect?\n"); + } + #endif +- /* PCD callback for suspend. */ +- pcd_suspend(core_if); ++ /* PCD callback for suspend. Release the lock inside of callback function */ ++ cil_pcd_suspend(core_if); ++ if (core_if->power_down == 2) ++ { ++ dcfg.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg); ++ DWC_DEBUGPL(DBG_ANY,"lx_state = %08x\n",core_if->lx_state); ++ DWC_DEBUGPL(DBG_ANY," device address = %08d\n",dcfg.b.devaddr); ++ ++ if (core_if->lx_state != DWC_OTG_L3 && dcfg.b.devaddr) { ++ pcgcctl_data_t pcgcctl = {.d32 = 0 }; ++ gpwrdn_data_t gpwrdn = {.d32 = 0 }; ++ gusbcfg_data_t gusbcfg = {.d32 = 0 }; ++ ++ /* Change to L2(suspend) state */ ++ core_if->lx_state = DWC_OTG_L2; ++ ++ /* Clear interrupt in gintsts */ ++ gintsts.d32 = 0; ++ gintsts.b.usbsuspend = 1; ++ DWC_WRITE_REG32(&core_if->core_global_regs-> ++ gintsts, gintsts.d32); ++ DWC_PRINTF("Start of hibernation completed\n"); ++ dwc_otg_save_global_regs(core_if); ++ dwc_otg_save_dev_regs(core_if); ++ ++ gusbcfg.d32 = ++ DWC_READ_REG32(&core_if->core_global_regs-> ++ gusbcfg); ++ if (gusbcfg.b.ulpi_utmi_sel == 1) { ++ /* ULPI interface */ ++ /* Suspend the Phy Clock */ ++ pcgcctl.d32 = 0; ++ pcgcctl.b.stoppclk = 1; ++ DWC_MODIFY_REG32(core_if->pcgcctl, 0, ++ pcgcctl.d32); ++ dwc_udelay(10); ++ gpwrdn.b.pmuactv = 1; ++ DWC_MODIFY_REG32(&core_if-> ++ core_global_regs-> ++ gpwrdn, 0, gpwrdn.d32); ++ } else { ++ /* UTMI+ Interface */ ++ gpwrdn.b.pmuactv = 1; ++ DWC_MODIFY_REG32(&core_if-> ++ core_global_regs-> ++ gpwrdn, 0, gpwrdn.d32); ++ dwc_udelay(10); ++ pcgcctl.b.stoppclk = 1; ++ DWC_MODIFY_REG32(core_if->pcgcctl, 0, ++ pcgcctl.d32); ++ dwc_udelay(10); ++ } ++ ++ /* Set flag to indicate that we are in hibernation */ ++ core_if->hibernation_suspend = 1; ++ /* Enable interrupts from wake up logic */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pmuintsel = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs-> ++ gpwrdn, 0, gpwrdn.d32); ++ dwc_udelay(10); ++ ++ /* Unmask device mode interrupts in GPWRDN */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.rst_det_msk = 1; ++ gpwrdn.b.lnstchng_msk = 1; ++ gpwrdn.b.sts_chngint_msk = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs-> ++ gpwrdn, 0, gpwrdn.d32); ++ dwc_udelay(10); ++ ++ /* Enable Power Down Clamp */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pwrdnclmp = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs-> ++ gpwrdn, 0, gpwrdn.d32); ++ dwc_udelay(10); ++ ++ /* Switch off VDD */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pwrdnswtch = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs-> ++ gpwrdn, 0, gpwrdn.d32); ++ ++ /* Save gpwrdn register for further usage if stschng interrupt */ ++ core_if->gr_backup->gpwrdn_local = ++ DWC_READ_REG32(&core_if->core_global_regs->gpwrdn); ++ DWC_PRINTF("Hibernation completed\n"); ++ ++ return 1; ++ } ++ } + } else { + if (core_if->op_state == A_PERIPHERAL) { + DWC_DEBUGPL(DBG_ANY, "a_peripheral->a_host\n"); + /* Clear the a_peripheral flag, back to a_host. */ +- pcd_stop(core_if); +- hcd_start(core_if); ++ DWC_SPINUNLOCK(core_if->lock); ++ cil_pcd_stop(core_if); ++ cil_hcd_start(core_if); ++ DWC_SPINLOCK(core_if->lock); + core_if->op_state = A_HOST; + } + } +@@ -701,7 +1160,7 @@ + /* Clear interrupt */ + gintsts.d32 = 0; + gintsts.b.usbsuspend = 1; +- dwc_write_reg32(&core_if->core_global_regs->gintsts, gintsts.d32); ++ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32); + + return 1; + } +@@ -719,20 +1178,20 @@ + DWC_PRINTF("Unexpected LPM interrupt\n"); + } + +- lpmcfg.d32 = dwc_read_reg32(&core_if->core_global_regs->glpmcfg); ++ lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg); + DWC_PRINTF("LPM config register = 0x%08x\n", lpmcfg.d32); + + if (dwc_otg_is_host_mode(core_if)) { +- hcd_sleep(core_if); ++ cil_hcd_sleep(core_if); + } else { + lpmcfg.b.hird_thres |= (1 << 4); +- dwc_write_reg32(&core_if->core_global_regs->glpmcfg, ++ DWC_WRITE_REG32(&core_if->core_global_regs->glpmcfg, + lpmcfg.d32); + } + +- /* Examine prt_sleep_sts after TL1TokenTetry period max (10 us) */ ++ /* Examine prt_sleep_sts after TL1TokenTetry period max (10 us) */ + dwc_udelay(10); +- lpmcfg.d32 = dwc_read_reg32(&core_if->core_global_regs->glpmcfg); ++ lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg); + if (lpmcfg.b.prt_sleep_sts) { + /* Save the current state */ + core_if->lx_state = DWC_OTG_L1; +@@ -741,16 +1200,17 @@ + /* Clear interrupt */ + gintsts.d32 = 0; + gintsts.b.lpmtranrcvd = 1; +- dwc_write_reg32(&core_if->core_global_regs->gintsts, gintsts.d32); ++ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32); + return 1; + } +-#endif /* CONFIG_USB_DWC_OTG_LPM */ ++#endif /* CONFIG_USB_DWC_OTG_LPM */ + + /** + * This function returns the Core Interrupt register. + */ + static inline uint32_t dwc_otg_read_common_intr(dwc_otg_core_if_t * core_if) + { ++ gahbcfg_data_t gahbcfg = {.d32 = 0 }; + gintsts_data_t gintsts; + gintmsk_data_t gintmsk; + gintmsk_data_t gintmsk_common = {.d32 = 0 }; +@@ -764,13 +1224,16 @@ + #ifdef CONFIG_USB_DWC_OTG_LPM + gintmsk_common.b.lpmtranrcvd = 1; + #endif +- /** @todo: The port interrupt occurs while in device +- * mode. Added code to CIL to clear the interrupt for now! ++ gintmsk_common.b.restoredone = 1; ++ /** @todo: The port interrupt occurs while in device ++ * mode. Added code to CIL to clear the interrupt for now! + */ + gintmsk_common.b.portintr = 1; + +- gintsts.d32 = dwc_read_reg32(&core_if->core_global_regs->gintsts); +- gintmsk.d32 = dwc_read_reg32(&core_if->core_global_regs->gintmsk); ++ gintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts); ++ gintmsk.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintmsk); ++ gahbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gahbcfg); ++ + #ifdef DEBUG + /* if any common interrupts set */ + if (gintsts.d32 & gintmsk_common.d32) { +@@ -778,15 +1241,26 @@ + gintsts.d32, gintmsk.d32); + } + #endif +- +- return ((gintsts.d32 & gintmsk.d32) & gintmsk_common.d32); ++ if (gahbcfg.b.glblintrmsk) ++ return ((gintsts.d32 & gintmsk.d32) & gintmsk_common.d32); ++ else ++ return 0; + + } + ++/* MACRO for clearing interupt bits in GPWRDN register */ ++#define CLEAR_GPWRDN_INTR(__core_if,__intr) \ ++do { \ ++ gpwrdn_data_t gpwrdn = {.d32=0}; \ ++ gpwrdn.b.__intr = 1; \ ++ DWC_MODIFY_REG32(&__core_if->core_global_regs->gpwrdn, \ ++ 0, gpwrdn.d32); \ ++} while (0) ++ + /** + * Common interrupt handler. + * +- * The common interrupts are those that occur in both Host and Device mode. ++ * The common interrupts are those that occur in both Host and Device mode. + * This handler handles the following interrupts: + * - Mode Mismatch Interrupt + * - Disconnect Interrupt +@@ -794,53 +1268,124 @@ + * - Connector ID Status Change Interrupt + * - Session Request Interrupt. + * - Resume / Remote Wakeup Detected Interrupt. +- * - LPM Transaction Received Interrutp +- * ++ * - LPM Transaction Received Interrupt ++ * - ADP Transaction Received Interrupt ++ * + */ +-int32_t dwc_otg_handle_common_intr(dwc_otg_core_if_t * core_if) ++int32_t dwc_otg_handle_common_intr(void *dev) + { + int retval = 0; + gintsts_data_t gintsts; ++ gpwrdn_data_t gpwrdn = {.d32 = 0 }; ++ dwc_otg_device_t *otg_dev = dev; ++ dwc_otg_core_if_t *core_if = otg_dev->core_if; ++ gpwrdn.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn); ++ if (dwc_otg_is_device_mode(core_if)) ++ core_if->frame_num = dwc_otg_get_frame_number(core_if); ++ ++ if (core_if->lock) ++ DWC_SPINLOCK(core_if->lock); + +- gintsts.d32 = dwc_otg_read_common_intr(core_if); ++ if (core_if->hibernation_suspend <= 0) { ++ gintsts.d32 = dwc_otg_read_common_intr(core_if); + +- if (gintsts.b.modemismatch) { +- retval |= dwc_otg_handle_mode_mismatch_intr(core_if); +- } +- if (gintsts.b.otgintr) { +- retval |= dwc_otg_handle_otg_intr(core_if); +- } +- if (gintsts.b.conidstschng) { +- retval |= dwc_otg_handle_conn_id_status_change_intr(core_if); +- } +- if (gintsts.b.disconnect) { +- retval |= dwc_otg_handle_disconnect_intr(core_if); +- } +- if (gintsts.b.sessreqintr) { +- retval |= dwc_otg_handle_session_req_intr(core_if); +- } +- if (gintsts.b.wkupintr) { +- retval |= dwc_otg_handle_wakeup_detected_intr(core_if); +- } +- if (gintsts.b.usbsuspend) { +- retval |= dwc_otg_handle_usb_suspend_intr(core_if); +- } ++ if (gintsts.b.modemismatch) { ++ retval |= dwc_otg_handle_mode_mismatch_intr(core_if); ++ } ++ if (gintsts.b.otgintr) { ++ retval |= dwc_otg_handle_otg_intr(core_if); ++ } ++ if (gintsts.b.conidstschng) { ++ retval |= dwc_otg_handle_conn_id_status_change_intr(core_if); ++ } ++ if (gintsts.b.disconnect) { ++ retval |= dwc_otg_handle_disconnect_intr(core_if); ++ } ++ if (gintsts.b.sessreqintr) { ++ retval |= dwc_otg_handle_session_req_intr(core_if); ++ } ++ if (gintsts.b.wkupintr) { ++ retval |= dwc_otg_handle_wakeup_detected_intr(core_if); ++ } ++ if (gintsts.b.usbsuspend) { ++ retval |= dwc_otg_handle_usb_suspend_intr(core_if); ++ } + #ifdef CONFIG_USB_DWC_OTG_LPM +- if (gintsts.b.lpmtranrcvd) { +- retval |= dwc_otg_handle_lpm_intr(core_if); +- } ++ if (gintsts.b.lpmtranrcvd) { ++ retval |= dwc_otg_handle_lpm_intr(core_if); ++ } + #endif ++ if (gintsts.b.restoredone) { ++ gintsts.d32 = 0; ++ if (core_if->power_down == 2) ++ core_if->hibernation_suspend = -1; ++ gintsts.b.restoredone = 1; ++ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts,gintsts.d32); ++ DWC_PRINTF(" --Restore done interrupt received-- \n"); ++ retval |= 1; ++ } ++ if (gintsts.b.portintr && dwc_otg_is_device_mode(core_if)) { ++ /* The port interrupt occurs while in device mode with HPRT0 ++ * Port Enable/Disable. ++ */ ++ gintsts.d32 = 0; ++ gintsts.b.portintr = 1; ++ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts,gintsts.d32); ++ retval |= 1; + +- if (gintsts.b.portintr && dwc_otg_is_device_mode(core_if)) { +- /* The port interrupt occurs while in device mode with HPRT0 +- * Port Enable/Disable. +- */ +- gintsts.d32 = 0; +- gintsts.b.portintr = 1; +- dwc_write_reg32(&core_if->core_global_regs->gintsts, +- gintsts.d32); ++ } ++ } else { ++ DWC_DEBUGPL(DBG_ANY, "gpwrdn=%08x\n", gpwrdn.d32); ++ ++ if (gpwrdn.b.disconn_det && gpwrdn.b.disconn_det_msk) { ++ CLEAR_GPWRDN_INTR(core_if, disconn_det); ++ if (gpwrdn.b.linestate == 0) { ++ dwc_otg_handle_pwrdn_disconnect_intr(core_if); ++ } else { ++ DWC_PRINTF("Disconnect detected while linestate is not 0\n"); ++ } ++ ++ retval |= 1; ++ } ++ if (gpwrdn.b.lnstschng && gpwrdn.b.lnstchng_msk) { ++ CLEAR_GPWRDN_INTR(core_if, lnstschng); ++ /* remote wakeup from hibernation */ ++ if (gpwrdn.b.linestate == 2 || gpwrdn.b.linestate == 1) { ++ dwc_otg_handle_pwrdn_wakeup_detected_intr(core_if); ++ } else { ++ DWC_PRINTF("gpwrdn.linestate = %d\n", gpwrdn.b.linestate); ++ } ++ retval |= 1; ++ } ++ if (gpwrdn.b.rst_det && gpwrdn.b.rst_det_msk) { ++ CLEAR_GPWRDN_INTR(core_if, rst_det); ++ if (gpwrdn.b.linestate == 0) { ++ DWC_PRINTF("Reset detected\n"); ++ retval |= dwc_otg_device_hibernation_restore(core_if, 0, 1); ++ } ++ } ++ if (gpwrdn.b.srp_det && gpwrdn.b.srp_det_msk) { ++ CLEAR_GPWRDN_INTR(core_if, srp_det); ++ dwc_otg_handle_pwrdn_srp_intr(core_if); ++ retval |= 1; ++ } ++ } ++ /* Handle ADP interrupt here */ ++ if (gpwrdn.b.adp_int) { ++ DWC_PRINTF("ADP interrupt\n"); ++ CLEAR_GPWRDN_INTR(core_if, adp_int); ++ dwc_otg_adp_handle_intr(core_if); + retval |= 1; ++ } ++ if (gpwrdn.b.sts_chngint && gpwrdn.b.sts_chngint_msk) { ++ DWC_PRINTF("STS CHNG interrupt asserted\n"); ++ CLEAR_GPWRDN_INTR(core_if, sts_chngint); ++ dwc_otg_handle_pwrdn_stschng_intr(otg_dev); + ++ retval |= 1; + } ++ if (core_if->lock) ++ DWC_SPINUNLOCK(core_if->lock); ++ + return retval; + } +Index: linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_core_if.h +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/dwc_otg_core_if.h 2013-07-26 19:33:34.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_core_if.h 2013-07-26 19:34:44.000000000 +0000 +@@ -1,8 +1,8 @@ + /* ========================================================================== + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_core_if.h $ +- * $Revision: #4 $ +- * $Date: 2008/12/18 $ +- * $Change: 1155299 $ ++ * $Revision: #12 $ ++ * $Date: 2011/10/24 $ ++ * $Change: 1871159 $ + * + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless +@@ -63,7 +63,7 @@ + extern uint8_t dwc_otg_is_dma_enable(dwc_otg_core_if_t * core_if); + + /** This function should be called on every hardware interrupt. */ +-extern int32_t dwc_otg_handle_common_intr(dwc_otg_core_if_t * _core_if); ++extern int32_t dwc_otg_handle_common_intr(void *otg_dev); + + /** @name OTG Core Parameters */ + /** @{ */ +@@ -268,7 +268,7 @@ + int32_t val); + extern int32_t dwc_otg_get_param_host_channels(dwc_otg_core_if_t * core_if); + //#define dwc_param_host_channels_default 12 +-#define dwc_param_host_channels_default 8// Broadcom BCM2708 ++#define dwc_param_host_channels_default 8 // Broadcom BCM2708 + + /** The number of endpoints in addition to EP0 available for device + * mode operations. +@@ -297,7 +297,7 @@ + #define dwc_param_phy_type_default DWC_PHY_TYPE_PARAM_UTMI + + /** +- * Specifies the UTMI+ Data Width. This parameter is ++ * Specifies the UTMI+ Data Width. This parameter is + * applicable for a PHY_TYPE of UTMI+ or ULPI. (For a ULPI + * PHY_TYPE, this parameter indicates the data width between + * the MAC and the ULPI Wrapper.) Also, this parameter is +@@ -379,7 +379,7 @@ + int fifo_num, int32_t val); + extern int32_t dwc_otg_get_param_dev_tx_fifo_size(dwc_otg_core_if_t * core_if, + int fifo_num); +-#define dwc_param_dev_tx_fifo_size_default 256 ++#define dwc_param_dev_tx_fifo_size_default 768 + + /** Thresholding enable flag- + * bit 0 - enable non-ISO Tx thresholding +@@ -431,17 +431,56 @@ + #define dwc_param_mpi_enable_default 0 + + /** ++ * Specifies whether ADP capability is enabled ++ */ ++extern int dwc_otg_set_param_adp_enable(dwc_otg_core_if_t * core_if, ++ int32_t val); ++extern int32_t dwc_otg_get_param_adp_enable(dwc_otg_core_if_t * core_if); ++#define dwc_param_adp_enable_default 0 ++ ++/** + * Specifies whether IC_USB capability is enabled + */ ++ + extern int dwc_otg_set_param_ic_usb_cap(dwc_otg_core_if_t * core_if, + int32_t val); + extern int32_t dwc_otg_get_param_ic_usb_cap(dwc_otg_core_if_t * core_if); + #define dwc_param_ic_usb_cap_default 0 + +-extern int dwc_otg_set_param_ahb_thr_ratio(dwc_otg_core_if_t * core_if, int32_t val); ++extern int dwc_otg_set_param_ahb_thr_ratio(dwc_otg_core_if_t * core_if, ++ int32_t val); + extern int32_t dwc_otg_get_param_ahb_thr_ratio(dwc_otg_core_if_t * core_if); + #define dwc_param_ahb_thr_ratio_default 0 + ++extern int dwc_otg_set_param_power_down(dwc_otg_core_if_t * core_if, ++ int32_t val); ++extern int32_t dwc_otg_get_param_power_down(dwc_otg_core_if_t * core_if); ++#define dwc_param_power_down_default 0 ++ ++extern int dwc_otg_set_param_reload_ctl(dwc_otg_core_if_t * core_if, ++ int32_t val); ++extern int32_t dwc_otg_get_param_reload_ctl(dwc_otg_core_if_t * core_if); ++#define dwc_param_reload_ctl_default 0 ++ ++extern int dwc_otg_set_param_dev_out_nak(dwc_otg_core_if_t * core_if, ++ int32_t val); ++extern int32_t dwc_otg_get_param_dev_out_nak(dwc_otg_core_if_t * core_if); ++#define dwc_param_dev_out_nak_default 0 ++ ++extern int dwc_otg_set_param_cont_on_bna(dwc_otg_core_if_t * core_if, ++ int32_t val); ++extern int32_t dwc_otg_get_param_cont_on_bna(dwc_otg_core_if_t * core_if); ++#define dwc_param_cont_on_bna_default 0 ++ ++extern int dwc_otg_set_param_ahb_single(dwc_otg_core_if_t * core_if, ++ int32_t val); ++extern int32_t dwc_otg_get_param_ahb_single(dwc_otg_core_if_t * core_if); ++#define dwc_param_ahb_single_default 0 ++ ++extern int dwc_otg_set_param_otg_ver(dwc_otg_core_if_t * core_if, int32_t val); ++extern int32_t dwc_otg_get_param_otg_ver(dwc_otg_core_if_t * core_if); ++#define dwc_param_otg_ver_default 0 ++ + /** @} */ + + /** @name Access to registers and bit-fields */ +@@ -521,6 +560,12 @@ + * Get value of prtpwr field from the HPRT0 register + */ + extern uint32_t dwc_otg_get_prtpower(dwc_otg_core_if_t * core_if); ++ ++/** ++ * Get value of flag indicating core state - hibernated or not ++ */ ++extern uint32_t dwc_otg_get_core_state(dwc_otg_core_if_t * core_if); ++ + /** + * Set value of prtpwr field from the HPRT0 register + */ +@@ -536,6 +581,24 @@ + extern void dwc_otg_set_prtsuspend(dwc_otg_core_if_t * core_if, uint32_t val); + + /** ++ * Get value of ModeChTimEn field from the HCFG regsiter ++ */ ++extern uint32_t dwc_otg_get_mode_ch_tim(dwc_otg_core_if_t * core_if); ++/** ++ * Set value of ModeChTimEn field from the HCFG regsiter ++ */ ++extern void dwc_otg_set_mode_ch_tim(dwc_otg_core_if_t * core_if, uint32_t val); ++ ++/** ++ * Get value of Fram Interval field from the HFIR regsiter ++ */ ++extern uint32_t dwc_otg_get_fr_interval(dwc_otg_core_if_t * core_if); ++/** ++ * Set value of Frame Interval field from the HFIR regsiter ++ */ ++extern void dwc_otg_set_fr_interval(dwc_otg_core_if_t * core_if, uint32_t val); ++ ++/** + * Set value of prtres field from the HPRT0 register + *FIXME Remove? + */ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_dbg.h +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/dwc_otg_dbg.h 2013-07-26 19:31:23.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_dbg.h 2013-07-26 19:34:44.000000000 +0000 +@@ -68,6 +68,9 @@ + /** When debug level has the DBG_HCD_URB bit set, display enqueued URBs in host + * mode. */ + #define DBG_HCD_URB (0x800) ++/** When debug level has the DBG_HCDI bit set, display host interrupt ++ * messages. */ ++#define DBG_HCDI (0x1000) + + /** When debug level has any bit set, display debug messages */ + #define DBG_ANY (0xFF) +Index: linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_driver.c +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/dwc_otg_driver.c 2013-07-26 19:34:36.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_driver.c 2013-07-26 19:34:44.000000000 +0000 +@@ -1,8 +1,8 @@ + /* ========================================================================== + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_driver.c $ +- * $Revision: #76 $ +- * $Date: 2009/05/03 $ +- * $Change: 1245589 $ ++ * $Revision: #91 $ ++ * $Date: 2011/10/24 $ ++ * $Change: 1871159 $ + * + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless +@@ -48,43 +48,7 @@ + * device. + */ + +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include /* permission constants */ +-#include +-#include +- +-#ifdef LM_INTERFACE +-#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30)) +-#include +-#include +-#else +-/* in 2.6.31, at least, we seem to have lost the generic LM infrastructure - +- here we use definitions stolen from arm-integrator headers +-*/ +-#include +-#include +-#endif +-#include +-#include +- +-#elif defined(PLATFORM_INTERFACE) +- +-#include +-#include +- +-#endif +- +-# include +- +-#include +- +- ++#include "dwc_otg_os_dep.h" + #include "dwc_os.h" + #include "dwc_otg_dbg.h" + #include "dwc_otg_driver.h" +@@ -93,49 +57,51 @@ + #include "dwc_otg_pcd_if.h" + #include "dwc_otg_hcd_if.h" + +-#define DWC_DRIVER_VERSION "2.90b 6-MAY-2010" ++#define DWC_DRIVER_VERSION "2.94b 27-OCT-2011 (rev 01-DEC-2011)" + #define DWC_DRIVER_DESC "HS OTG USB Controller driver" + + static const char dwc_driver_name[] = "dwc_otg"; + + extern int pcd_init( + #ifdef LM_INTERFACE +- struct lm_device *_dev ++ struct lm_device *_dev + #elif defined(PCI_INTERFACE) +- struct pci_dev *_dev ++ struct pci_dev *_dev + #elif defined(PLATFORM_INTERFACE) + struct platform_device *dev + #endif +- ); ++ ); + extern int hcd_init( + #ifdef LM_INTERFACE +- struct lm_device *_dev ++ struct lm_device *_dev + #elif defined(PCI_INTERFACE) +- struct pci_dev *_dev ++ struct pci_dev *_dev + #elif defined(PLATFORM_INTERFACE) + struct platform_device *dev + #endif +- ); ++ ); + + extern int pcd_remove( + #ifdef LM_INTERFACE +- struct lm_device *_dev ++ struct lm_device *_dev + #elif defined(PCI_INTERFACE) +- struct pci_dev *_dev ++ struct pci_dev *_dev + #elif defined(PLATFORM_INTERFACE) + struct platform_device *_dev + #endif +- ); ++ ); + + extern void hcd_remove( + #ifdef LM_INTERFACE +- struct lm_device *_dev ++ struct lm_device *_dev + #elif defined(PCI_INTERFACE) +- struct pci_dev *_dev ++ struct pci_dev *_dev + #elif defined(PLATFORM_INTERFACE) + struct platform_device *_dev + #endif +- ); ++ ); ++ ++extern void dwc_otg_adp_start(dwc_otg_core_if_t * core_if, uint8_t is_host); + + /*-------------------------------------------------------------------------*/ + /* Encapsulate the module parameter settings */ +@@ -178,6 +144,13 @@ + int32_t lpm_enable; + int32_t ic_usb_cap; + int32_t ahb_thr_ratio; ++ int32_t power_down; ++ int32_t reload_ctl; ++ int32_t dev_out_nak; ++ int32_t cont_on_bna; ++ int32_t ahb_single; ++ int32_t otg_ver; ++ int32_t adp_enable; + }; + + static struct dwc_otg_driver_module_params dwc_otg_module_params = { +@@ -254,6 +227,13 @@ + .lpm_enable = -1, + .ic_usb_cap = -1, + .ahb_thr_ratio = -1, ++ .power_down = -1, ++ .reload_ctl = -1, ++ .dev_out_nak = -1, ++ .cont_on_bna = -1, ++ .ahb_single = -1, ++ .otg_ver = -1, ++ .adp_enable = -1, + }; + + /** +@@ -436,7 +416,8 @@ + } + if (dwc_otg_module_params.ulpi_fs_ls != -1) { + retval += +- dwc_otg_set_param_ulpi_fs_ls(core_if, dwc_otg_module_params.ulpi_fs_ls); ++ dwc_otg_set_param_ulpi_fs_ls(core_if, ++ dwc_otg_module_params.ulpi_fs_ls); + } + if (dwc_otg_module_params.ts_dline != -1) { + retval += +@@ -513,9 +494,50 @@ + dwc_otg_module_params. + rx_thr_length); + } +- if(dwc_otg_module_params.ahb_thr_ratio != -1) { ++ if (dwc_otg_module_params.ahb_thr_ratio != -1) { ++ retval += ++ dwc_otg_set_param_ahb_thr_ratio(core_if, ++ dwc_otg_module_params.ahb_thr_ratio); ++ } ++ if (dwc_otg_module_params.power_down != -1) { ++ retval += ++ dwc_otg_set_param_power_down(core_if, ++ dwc_otg_module_params.power_down); ++ } ++ if (dwc_otg_module_params.reload_ctl != -1) { ++ retval += ++ dwc_otg_set_param_reload_ctl(core_if, ++ dwc_otg_module_params.reload_ctl); ++ } ++ ++ if (dwc_otg_module_params.dev_out_nak != -1) { ++ retval += ++ dwc_otg_set_param_dev_out_nak(core_if, ++ dwc_otg_module_params.dev_out_nak); ++ } ++ ++ if (dwc_otg_module_params.cont_on_bna != -1) { ++ retval += ++ dwc_otg_set_param_cont_on_bna(core_if, ++ dwc_otg_module_params.cont_on_bna); ++ } ++ ++ if (dwc_otg_module_params.ahb_single != -1) { ++ retval += ++ dwc_otg_set_param_ahb_single(core_if, ++ dwc_otg_module_params.ahb_single); ++ } ++ ++ if (dwc_otg_module_params.otg_ver != -1) { ++ retval += ++ dwc_otg_set_param_otg_ver(core_if, ++ dwc_otg_module_params.otg_ver); ++ } ++ if (dwc_otg_module_params.adp_enable != -1) { + retval += +- dwc_otg_set_param_ahb_thr_ratio(core_if, dwc_otg_module_params.ahb_thr_ratio); ++ dwc_otg_set_param_adp_enable(core_if, ++ dwc_otg_module_params. ++ adp_enable); + } + return retval; + } +@@ -526,10 +548,9 @@ + */ + static irqreturn_t dwc_otg_common_irq(int irq, void *dev) + { +- dwc_otg_device_t *otg_dev = dev; + int32_t retval = IRQ_NONE; + +- retval = dwc_otg_handle_common_intr(otg_dev->core_if); ++ retval = dwc_otg_handle_common_intr(dev); + if (retval != 0) { + S3C2410X_CLEAR_EINTPEND(); + } +@@ -546,54 +567,41 @@ + * @param _dev + */ + #ifdef LM_INTERFACE +-static void dwc_otg_driver_remove( +- struct lm_device *_dev ++#define REM_RETVAL(n) ++static void dwc_otg_driver_remove( struct lm_device *_dev ) ++{ dwc_otg_device_t *otg_dev = lm_get_drvdata(_dev); + #elif defined(PCI_INTERFACE) +-static void dwc_otg_driver_remove( +- struct pci_dev *_dev ++#define REM_RETVAL(n) ++static void dwc_otg_driver_remove( struct pci_dev *_dev ) ++{ dwc_otg_device_t *otg_dev = pci_get_drvdata(_dev); + #elif defined(PLATFORM_INTERFACE) +-static int dwc_otg_driver_remove( +- struct platform_device *_dev ++#define REM_RETVAL(n) n ++static int dwc_otg_driver_remove( struct platform_device *_dev ) ++{ dwc_otg_device_t *otg_dev = platform_get_drvdata(_dev); + #endif +-) +- +-{ +-#ifdef LM_INTERFACE +- dwc_otg_device_t *otg_dev = lm_get_drvdata(_dev); +-#elif defined(PCI_INTERFACE) +- dwc_otg_device_t *otg_dev = pci_get_drvdata(_dev); +-#elif defined(PLATFORM_INTERFACE) +- dwc_otg_device_t *otg_dev = platform_get_drvdata(_dev); +-#endif +- + + DWC_DEBUGPL(DBG_ANY, "%s(%p) otg_dev %p\n", __func__, _dev, otg_dev); + + if (!otg_dev) { + /* Memory allocation for the dwc_otg_device failed. */ + DWC_DEBUGPL(DBG_ANY, "%s: otg_dev NULL!\n", __func__); +-#ifdef PLATFORM_INTERFACE +- return -ENOMEM; +-#else +- return; +-#endif ++ return REM_RETVAL(-ENOMEM); + } + #ifndef DWC_DEVICE_ONLY + if (otg_dev->hcd) { + hcd_remove(_dev); + } else { + DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->hcd NULL!\n", __func__); +-#ifdef PLATFORM_INTERFACE +- return -EINVAL; +-#else +- return; +-#endif ++ return REM_RETVAL(-EINVAL); + } + #endif + + #ifndef DWC_HOST_ONLY + if (otg_dev->pcd) { + pcd_remove(_dev); ++ } else { ++ DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->pcd NULL!\n", __func__); ++ return REM_RETVAL(-EINVAL); + } + #endif + /* +@@ -605,10 +613,16 @@ + #else + free_irq(_dev->irq, otg_dev); + #endif +- } ++ } else { ++ DWC_DEBUGPL(DBG_ANY, "%s: There is no installed irq!\n", __func__); ++ return REM_RETVAL(-ENXIO); ++ } + + if (otg_dev->core_if) { + dwc_otg_cil_remove(otg_dev->core_if); ++ } else { ++ DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->core_if NULL!\n", __func__); ++ return REM_RETVAL(-ENXIO); + } + + /* +@@ -619,23 +633,24 @@ + /* + * Return the memory. + */ +- if (otg_dev->base) { +- iounmap(otg_dev->base); ++ if (otg_dev->os_dep.base) { ++ iounmap(otg_dev->os_dep.base); + } +- dwc_free(otg_dev); ++ DWC_FREE(otg_dev); + + /* + * Clear the drvdata pointer. + */ + #ifdef LM_INTERFACE + lm_set_drvdata(_dev, 0); +-#elif defined(PCI_INTERFACE) +- release_mem_region(otg_dev->rsrc_start, otg_dev->rsrc_len); +- pci_set_drvdata(_dev, 0); ++#elif defined(PCI_INTERFACE) ++ release_mem_region(otg_dev->os_dep.rsrc_start, ++ otg_dev->os_dep.rsrc_len); ++ pci_set_drvdata(_dev, 0); + #elif defined(PLATFORM_INTERFACE) + platform_set_drvdata(_dev, 0); +- return 0; + #endif ++ return REM_RETVAL(0); + } + + /** +@@ -651,13 +666,14 @@ + */ + static int dwc_otg_driver_probe( + #ifdef LM_INTERFACE +-struct lm_device *_dev +-#elif defined(PCI_INTERFACE) +-struct pci_dev *_dev, const struct pci_device_id *id ++ struct lm_device *_dev ++#elif defined(PCI_INTERFACE) ++ struct pci_dev *_dev, ++ const struct pci_device_id *id + #elif defined(PLATFORM_INTERFACE) +-struct platform_device *_dev ++ struct platform_device *_dev + #endif +-) ++ ) + { + int retval = 0; + dwc_otg_device_t *dwc_otg_device; +@@ -666,9 +682,9 @@ + dev_dbg(&_dev->dev, "dwc_otg_driver_probe(%p)\n", _dev); + #ifdef LM_INTERFACE + dev_dbg(&_dev->dev, "start=0x%08x\n", (unsigned)_dev->resource.start); +-#elif defined(PCI_INTERFACE) ++#elif defined(PCI_INTERFACE) + if (!id) { +- DWC_ERROR("Invalid pci_device_id %p", id); ++ DWC_ERROR("Invalid pci_device_id %p", id); + return -EINVAL; + } + +@@ -685,76 +701,77 @@ + (unsigned)(_dev->resource->end - _dev->resource->start)); + #endif + +- +- dwc_otg_device = dwc_alloc(sizeof(dwc_otg_device_t)); ++ dwc_otg_device = DWC_ALLOC(sizeof(dwc_otg_device_t)); + + if (!dwc_otg_device) { + dev_err(&_dev->dev, "kmalloc of dwc_otg_device failed\n"); +- retval = -ENOMEM; +- goto fail; ++ return -ENOMEM; + } + + memset(dwc_otg_device, 0, sizeof(*dwc_otg_device)); +- dwc_otg_device->reg_offset = 0xFFFFFFFF; ++ dwc_otg_device->os_dep.reg_offset = 0xFFFFFFFF; + + /* + * Map the DWC_otg Core memory into virtual address space. + */ + #ifdef LM_INTERFACE +-#if 1 +- dwc_otg_device->base = ioremap(_dev->resource.start, SZ_256K); +-#else +- struct map_desc desc = { +- .virtual = IO_ADDRESS((unsigned)_dev->resource.start), +- .pfn = __phys_to_pfn((unsigned)_dev->resource.start), +- .length = SZ_128K, +- .type = MT_DEVICE +- }; +- iotable_init(&desc, 1); +- dwc_otg_device->base = (void *)desc.virtual; +-#endif ++ dwc_otg_device->os_dep.base = ioremap(_dev->resource.start, SZ_256K); + +- if (!dwc_otg_device->base) { ++ if (!dwc_otg_device->os_dep.base) { + dev_err(&_dev->dev, "ioremap() failed\n"); +- retval = -ENOMEM; +- goto fail; ++ DWC_FREE(dwc_otg_device); ++ return -ENOMEM; + } +- dev_dbg(&_dev->dev, "base=0x%08x\n", (unsigned)dwc_otg_device->base); +-#elif defined(PCI_INTERFACE) ++ dev_dbg(&_dev->dev, "base=0x%08x\n", ++ (unsigned)dwc_otg_device->os_dep.base); ++#elif defined(PCI_INTERFACE) + _dev->current_state = PCI_D0; + _dev->dev.power.power_state = PMSG_ON; +- ++ + if (!_dev->irq) { +- DWC_ERROR("Found HC with no IRQ. Check BIOS/PCI %s setup!", pci_name(_dev)); +- retval = -ENODEV; +- goto fail; +- } ++ DWC_ERROR("Found HC with no IRQ. Check BIOS/PCI %s setup!", ++ pci_name(_dev)); ++ iounmap(dwc_otg_device->os_dep.base); ++ DWC_FREE(dwc_otg_device); ++ return -ENODEV; ++ } + +- dwc_otg_device->rsrc_start = pci_resource_start(_dev,0); +- dwc_otg_device->rsrc_len = pci_resource_len(_dev,0); +- DWC_DEBUGPL(DBG_ANY,"PCI resource: start=%08x, len=%08x\n", +- dwc_otg_device->rsrc_start, +- dwc_otg_device->rsrc_len); +- if (!request_mem_region(dwc_otg_device->rsrc_start, dwc_otg_device->rsrc_len, "dwc_otg")) { +- dev_dbg(&_dev->dev, "error mapping memory\n"); +- retval = -EFAULT; +- goto fail; +- } ++ dwc_otg_device->os_dep.rsrc_start = pci_resource_start(_dev, 0); ++ dwc_otg_device->os_dep.rsrc_len = pci_resource_len(_dev, 0); ++ DWC_DEBUGPL(DBG_ANY, "PCI resource: start=%08x, len=%08x\n", ++ (unsigned)dwc_otg_device->os_dep.rsrc_start, ++ (unsigned)dwc_otg_device->os_dep.rsrc_len); ++ if (!request_mem_region ++ (dwc_otg_device->os_dep.rsrc_start, dwc_otg_device->os_dep.rsrc_len, ++ "dwc_otg")) { ++ dev_dbg(&_dev->dev, "error requesting memory\n"); ++ iounmap(dwc_otg_device->os_dep.base); ++ DWC_FREE(dwc_otg_device); ++ return -EFAULT; ++ } ++ ++ dwc_otg_device->os_dep.base = ++ ioremap_nocache(dwc_otg_device->os_dep.rsrc_start, ++ dwc_otg_device->os_dep.rsrc_len); ++ if (dwc_otg_device->os_dep.base == NULL) { ++ dev_dbg(&_dev->dev, "error mapping memory\n"); ++ release_mem_region(dwc_otg_device->os_dep.rsrc_start, ++ dwc_otg_device->os_dep.rsrc_len); ++ iounmap(dwc_otg_device->os_dep.base); ++ DWC_FREE(dwc_otg_device); ++ return -EFAULT; ++ } ++ dev_dbg(&_dev->dev, "base=0x%p (before adjust) \n", ++ dwc_otg_device->os_dep.base); ++ dwc_otg_device->os_dep.base = (char *)dwc_otg_device->os_dep.base; ++ dev_dbg(&_dev->dev, "base=0x%p (after adjust) \n", ++ dwc_otg_device->os_dep.base); ++ dev_dbg(&_dev->dev, "%s: mapped PA 0x%x to VA 0x%p\n", __func__, ++ (unsigned)dwc_otg_device->os_dep.rsrc_start, ++ dwc_otg_device->os_dep.base); + +- dwc_otg_device->base = ioremap_nocache(dwc_otg_device->rsrc_start, dwc_otg_device->rsrc_len); +- if (dwc_otg_device->base == NULL) { +- dev_dbg(&_dev->dev, "error mapping memory\n"); +- retval = -EFAULT; +- goto fail; +- } +- dev_dbg(&_dev->dev, "base=0x%p (before adjust) \n", dwc_otg_device->base); +- dwc_otg_device->base = (char *)dwc_otg_device->base; +- dev_dbg(&_dev->dev, "base=0x%p (after adjust) \n", dwc_otg_device->base); +- dev_dbg(&_dev->dev, "%s: mapped PA 0x%x to VA 0x%p\n", __func__, +- (unsigned)dwc_otg_device->rsrc_start, dwc_otg_device->base); +- // +- pci_set_drvdata(_dev, dwc_otg_device); +- pci_set_master(_dev); ++ pci_set_master(_dev); ++ pci_set_drvdata(_dev, dwc_otg_device); + #elif defined(PLATFORM_INTERFACE) + DWC_DEBUGPL(DBG_ANY,"Platform resource: start=%08x, len=%08x\n", + _dev->resource->start, +@@ -768,9 +785,9 @@ + goto fail; + } + +- dwc_otg_device->base = ioremap_nocache(_dev->resource->start, +- _dev->resource->end - +- _dev->resource->start + 1); ++ dwc_otg_device->os_dep.base = ioremap_nocache(_dev->resource->start, ++ _dev->resource->end - ++ _dev->resource->start+1); + #else + { + struct map_desc desc = { +@@ -780,15 +797,16 @@ + .type = MT_DEVICE + }; + iotable_init(&desc, 1); +- dwc_otg_device->base = (void *)desc.virtual; ++ dwc_otg_device->os_dep.base = (void *)desc.virtual; + } + #endif +- if (!dwc_otg_device->base) { ++ if (!dwc_otg_device->os_dep.base) { + dev_err(&_dev->dev, "ioremap() failed\n"); + retval = -ENOMEM; + goto fail; + } +- dev_dbg(&_dev->dev, "base=0x%08x\n", (unsigned)dwc_otg_device->base); ++ dev_dbg(&_dev->dev, "base=0x%08x\n", ++ (unsigned)dwc_otg_device->os_dep.base); + #endif + + /* +@@ -802,7 +820,7 @@ + #endif + dev_dbg(&_dev->dev, "dwc_otg_device=0x%p\n", dwc_otg_device); + +- dwc_otg_device->core_if = dwc_otg_cil_init(dwc_otg_device->base); ++ dwc_otg_device->core_if = dwc_otg_cil_init(dwc_otg_device->os_dep.base); + DWC_DEBUGPL(DBG_HCDV, "probe of device %p given core_if %p\n", + dwc_otg_device, dwc_otg_device->core_if);//GRAYG + +@@ -823,8 +841,6 @@ + 0x4F542000) { + dev_err(&_dev->dev, "Bad value for SNPSID: 0x%08x\n", + dwc_otg_get_gsnpsid(dwc_otg_device->core_if)); +- dwc_otg_cil_remove(dwc_otg_device->core_if); +- dwc_free(dwc_otg_device); + retval = -EINVAL; + goto fail; + } +@@ -834,7 +850,6 @@ + */ + dev_dbg(&_dev->dev, "Calling set_parameters\n"); + if (set_parameters(dwc_otg_device->core_if)) { +- dwc_otg_cil_remove(dwc_otg_device->core_if); + retval = -EINVAL; + goto fail; + } +@@ -856,6 +871,7 @@ + * Install the interrupt handler for the common interrupts before + * enabling common interrupts in core_init below. + */ ++ + #if defined(PLATFORM_INTERFACE) + devirq = platform_get_irq(_dev, 0); + #else +@@ -887,13 +903,13 @@ + ); + #endif + #endif /*IRQF_TRIGGER_LOW*/ +- ++ + /* + * Initialize the DWC_otg core. + */ + dev_dbg(&_dev->dev, "Calling dwc_otg_core_init\n"); + dwc_otg_core_init(dwc_otg_device->core_if); +- ++ + #ifndef DWC_HOST_ONLY + /* + * Initialize the PCD +@@ -904,7 +920,7 @@ + DWC_ERROR("pcd_init failed\n"); + dwc_otg_device->pcd = NULL; + goto fail; +- } ++ } + #endif + #ifndef DWC_DEVICE_ONLY + /* +@@ -925,19 +941,25 @@ + platform_set_drvdata(_dev, dwc_otg_device); + #elif defined(PCI_INTERFACE) + pci_set_drvdata(_dev, dwc_otg_device); ++ dwc_otg_device->os_dep.pcidev = _dev; + #endif + + /* + * Enable the global interrupt after all the interrupt +- * handlers are installed. ++ * handlers are installed if there is no ADP support else ++ * perform initial actions required for Internal ADP logic. + */ +- dev_dbg(&_dev->dev, "Calling enable_global_interrupts\n"); +- dwc_otg_enable_global_interrupts(dwc_otg_device->core_if); +- dev_dbg(&_dev->dev, "Done\n"); ++ if (!dwc_otg_get_param_adp_enable(dwc_otg_device->core_if)) { ++ dev_dbg(&_dev->dev, "Calling enable_global_interrupts\n"); ++ dwc_otg_enable_global_interrupts(dwc_otg_device->core_if); ++ dev_dbg(&_dev->dev, "Done\n"); ++ } else ++ dwc_otg_adp_start(dwc_otg_device->core_if, ++ dwc_otg_is_host_mode(dwc_otg_device->core_if)); + + return 0; + +- fail: ++fail: + dwc_otg_driver_remove(_dev); + return retval; + } +@@ -955,32 +977,32 @@ + */ + #ifdef LM_INTERFACE + static struct lm_driver dwc_otg_driver = { +- .drv = { +- .name = (char *)dwc_driver_name, +- }, ++ .drv = {.name = (char *)dwc_driver_name,}, + .probe = dwc_otg_driver_probe, + .remove = dwc_otg_driver_remove, + // 'suspend' and 'resume' absent + }; + #elif defined(PCI_INTERFACE) + static const struct pci_device_id pci_ids[] = { { +- PCI_DEVICE(0x16c3, 0xabcd), +- .driver_data = (unsigned long) 0xdeadbeef, +- }, { /* end: all zeroes */ } ++ PCI_DEVICE(0x16c3, 0xabcd), ++ .driver_data = ++ (unsigned long)0xdeadbeef, ++ }, { /* end: all zeroes */ } + }; ++ + MODULE_DEVICE_TABLE(pci, pci_ids); + + /* pci driver glue; this is a "new style" PCI driver module */ + static struct pci_driver dwc_otg_driver = { +- .name = "dwc_otg", +- .id_table = pci_ids, ++ .name = "dwc_otg", ++ .id_table = pci_ids, + +- .probe = dwc_otg_driver_probe, +- .remove = dwc_otg_driver_remove, ++ .probe = dwc_otg_driver_probe, ++ .remove = dwc_otg_driver_remove, + +- .driver = { +- .name = (char*)dwc_driver_name, +- }, ++ .driver = { ++ .name = (char *)dwc_driver_name, ++ }, + }; + #elif defined(PLATFORM_INTERFACE) + static struct platform_device_id platform_ids[] = { +@@ -1004,7 +1026,6 @@ + }; + #endif + +- + /** + * This function is called when the dwc_otg_driver is installed with the + * insmod command. It registers the dwc_otg_driver structure with the +@@ -1019,35 +1040,30 @@ + { + int retval = 0; + int error; ++ struct device_driver *drv; + printk(KERN_INFO "%s: version %s (%s bus)\n", dwc_driver_name, + DWC_DRIVER_VERSION, + #ifdef LM_INTERFACE + "logicmodule"); + retval = lm_driver_register(&dwc_otg_driver); ++ drv = &dwc_otg_driver.drv; + #elif defined(PCI_INTERFACE) + "pci"); + retval = pci_register_driver(&dwc_otg_driver); ++ drv = &dwc_otg_driver.driver; + #elif defined(PLATFORM_INTERFACE) + "platform"); + retval = platform_driver_register(&dwc_otg_driver); ++ drv = &dwc_otg_driver.driver; + #endif + if (retval < 0) { + printk(KERN_ERR "%s retval=%d\n", __func__, retval); + return retval; + } +-#ifdef LM_INTERFACE +- error = driver_create_file(&dwc_otg_driver.drv, &driver_attr_version); +- error = driver_create_file(&dwc_otg_driver.drv, &driver_attr_debuglevel); +-#elif defined(PCI_INTERFACE) +- error = driver_create_file(&dwc_otg_driver.driver, +- &driver_attr_version); +- error = driver_create_file(&dwc_otg_driver.driver, +- &driver_attr_debuglevel); +-#elif defined(PLATFORM_INTERFACE) +- error = driver_create_file(&dwc_otg_driver.driver, +- &driver_attr_version); +- error = driver_create_file(&dwc_otg_driver.driver, +- &driver_attr_debuglevel); ++ ++ error = driver_create_file(drv, &driver_attr_version); ++#ifdef DEBUG ++ error = driver_create_file(drv, &driver_attr_debuglevel); + #endif + return retval; + } +@@ -1080,6 +1096,7 @@ + + printk(KERN_INFO "%s module removed\n", dwc_driver_name); + } ++ + module_exit(dwc_otg_driver_cleanup); + + MODULE_DESCRIPTION(DWC_DRIVER_DESC); +@@ -1303,8 +1320,23 @@ + module_param_named(ic_usb_cap, dwc_otg_module_params.ic_usb_cap, int, 0444); + MODULE_PARM_DESC(ic_usb_cap, + "IC_USB Capability 0=IC_USB Disabled 1=IC_USB Enabled"); +-module_param_named(ahb_thr_ratio, dwc_otg_module_params.ahb_thr_ratio, int, 0444); ++module_param_named(ahb_thr_ratio, dwc_otg_module_params.ahb_thr_ratio, int, ++ 0444); + MODULE_PARM_DESC(ahb_thr_ratio, "AHB Threshold Ratio"); ++module_param_named(power_down, dwc_otg_module_params.power_down, int, 0444); ++MODULE_PARM_DESC(power_down, "Power Down Mode"); ++module_param_named(reload_ctl, dwc_otg_module_params.reload_ctl, int, 0444); ++MODULE_PARM_DESC(reload_ctl, "HFIR Reload Control"); ++module_param_named(dev_out_nak, dwc_otg_module_params.dev_out_nak, int, 0444); ++MODULE_PARM_DESC(dev_out_nak, "Enable Device OUT NAK"); ++module_param_named(cont_on_bna, dwc_otg_module_params.cont_on_bna, int, 0444); ++MODULE_PARM_DESC(cont_on_bna, "Enable Enable Continue on BNA"); ++module_param_named(ahb_single, dwc_otg_module_params.ahb_single, int, 0444); ++MODULE_PARM_DESC(ahb_single, "Enable AHB Single Support"); ++module_param_named(adp_enable, dwc_otg_module_params.adp_enable, int, 0444); ++MODULE_PARM_DESC(adp_enable, "ADP Enable 0=ADP Disabled 1=ADP Enabled"); ++module_param_named(otg_ver, dwc_otg_module_params.otg_ver, int, 0444); ++MODULE_PARM_DESC(otg_ver, "OTG revision supported 0=OTG 1.3 1=OTG 2.0"); + + /** @page "Module Parameters" + * +@@ -1492,7 +1524,21 @@ + + + +- ++ ++ ++ ++ ++ ++ ++ ++ ++ + + +- + + +@@ -1556,7 +1602,7 @@ + The driver will automatically detect the value for this parameter if none is + specified. + - 0: PTI disabled (default) +- - 1: PTI enable ++ - 1: PTI enable + + + +@@ -1568,10 +1614,82 @@ + - 1: LPM enable (default, if available) + + +- ++ ++ ++ ++ ++ + + + ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ + */ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_driver.h +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/dwc_otg_driver.h 2013-07-26 19:31:23.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_driver.h 2013-07-26 19:34:44.000000000 +0000 +@@ -1,8 +1,8 @@ + /* ========================================================================== + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_driver.h $ +- * $Revision: #16 $ +- * $Date: 2009/04/03 $ +- * $Change: 1225160 $ ++ * $Revision: #19 $ ++ * $Date: 2010/11/15 $ ++ * $Change: 1627671 $ + * + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless +@@ -37,41 +37,26 @@ + /** @file + * This file contains the interface to the Linux driver. + */ ++#include "dwc_otg_os_dep.h" + #include "dwc_otg_core_if.h" + + /* Type declarations */ + struct dwc_otg_pcd; + struct dwc_otg_hcd; + +-#ifdef PCI_INTERFACE +-#include +-#endif +- +- +- + /** + * This structure is a wrapper that encapsulates the driver components used to + * manage a single DWC_otg controller. + */ + typedef struct dwc_otg_device { +- /** Base address returned from ioremap() */ +- void *base; +- +-#ifdef LM_INTERFACE +- struct lm_device *lmdev; +-#elif defined(PCI_INTERFACE) +- int rsrc_start; +- int rsrc_len; +-#elif defined(PLATFORM_INTERFACE) +- struct platform_device *platformdev; +-#endif ++ /** Structure containing OS-dependent stuff. KEEP THIS STRUCT AT THE ++ * VERY BEGINNING OF THE DEVICE STRUCT. OSes such as FreeBSD and NetBSD ++ * require this. */ ++ struct os_dependent os_dep; + + /** Pointer to the core interface structure. */ + dwc_otg_core_if_t *core_if; + +- /** Register offset for Diagnostic API. */ +- uint32_t reg_offset; +- + /** Pointer to the PCD structure. */ + struct dwc_otg_pcd *pcd; + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_hcd.c +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/dwc_otg_hcd.c 2013-07-26 19:34:36.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_hcd.c 2013-07-26 19:34:44.000000000 +0000 +@@ -1,9 +1,9 @@ + + /* ========================================================================== + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd.c $ +- * $Revision: #87 $ +- * $Date: 2009/04/23 $ +- * $Change: 1239143 $ ++ * $Revision: #104 $ ++ * $Date: 2011/10/24 $ ++ * $Change: 1871159 $ + * + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless +@@ -34,7 +34,7 @@ + #ifndef DWC_DEVICE_ONLY + + /** @file +- * This file implements HCD Core. All code in this file is portable and don't ++ * This file implements HCD Core. All code in this file is portable and doesn't + * use any OS specific functions. + * Interface provided by HCD Core is defined in + * header file. +@@ -43,14 +43,9 @@ + #include "dwc_otg_hcd.h" + #include "dwc_otg_regs.h" + +-#ifdef HW2937_WORKAROUND +-//#include +-#include +-#endif +- + dwc_otg_hcd_t *dwc_otg_hcd_alloc_hcd(void) + { +- return dwc_alloc(sizeof(dwc_otg_hcd_t)); ++ return DWC_ALLOC(sizeof(dwc_otg_hcd_t)); + } + + /** +@@ -64,7 +59,7 @@ + __DWC_ERROR("Device Not Connected/Responding\n"); + } + +-#ifdef DEBUG ++#if defined(DEBUG) + static void dump_channel_info(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh) + { + if (qh->channel != NULL) { +@@ -81,10 +76,10 @@ + uint32_t hcdma; + + hc_regs = hcd->core_if->host_if->hc_regs[hc->hc_num]; +- hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); +- hcsplt.d32 = dwc_read_reg32(&hc_regs->hcsplt); +- hctsiz.d32 = dwc_read_reg32(&hc_regs->hctsiz); +- hcdma = dwc_read_reg32(&hc_regs->hcdma); ++ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar); ++ hcsplt.d32 = DWC_READ_REG32(&hc_regs->hcsplt); ++ hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz); ++ hcdma = DWC_READ_REG32(&hc_regs->hcdma); + + DWC_PRINTF(" Assigned to channel %p:\n", hc); + DWC_PRINTF(" hcchar 0x%08x, hcsplt 0x%08x\n", hcchar.d32, +@@ -120,7 +115,9 @@ + } + } + } +-#endif /* DEBUG */ ++#else ++#define dump_channel_info(hcd, qh) ++#endif /* DEBUG */ + + /** + * Work queue function for starting the HCD when A-Cable is connected. +@@ -170,8 +167,7 @@ + qtd = DWC_CIRCLEQ_FIRST(&qh->qtd_list); + if (qtd->urb != NULL) { + hcd->fops->complete(hcd, qtd->urb->priv, +- qtd->urb, +- -DWC_E_TIMEOUT); ++ qtd->urb, -DWC_E_TIMEOUT); + dwc_otg_hcd_qtd_remove_and_free(hcd, qtd, qh); + } + +@@ -242,7 +238,7 @@ + */ + hprt0.d32 = dwc_otg_read_hprt0(core_if); + hprt0.b.prtrst = 1; +- dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32); ++ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32); + } + DWC_WORKQ_SCHEDULE_DELAYED(core_if->wq_otg, + hcd_start_func, dwc_otg_hcd, 50, +@@ -276,9 +272,9 @@ + intr.b.nptxfempty = 1; + intr.b.ptxfempty = 1; + intr.b.hcintr = 1; +- dwc_modify_reg32(&dwc_otg_hcd->core_if->core_global_regs->gintmsk, ++ DWC_MODIFY_REG32(&dwc_otg_hcd->core_if->core_global_regs->gintmsk, + intr.d32, 0); +- dwc_modify_reg32(&dwc_otg_hcd->core_if->core_global_regs->gintsts, ++ DWC_MODIFY_REG32(&dwc_otg_hcd->core_if->core_global_regs->gintsts, + intr.d32, 0); + + del_timers(dwc_otg_hcd); +@@ -293,7 +289,7 @@ + hprt0_data_t hprt0 = {.d32 = 0 }; + DWC_PRINTF("Disconnect: PortPower off\n"); + hprt0.b.prtpwr = 0; +- dwc_write_reg32(dwc_otg_hcd->core_if->host_if->hprt0, ++ DWC_WRITE_REG32(dwc_otg_hcd->core_if->host_if->hprt0, + hprt0.d32); + } + +@@ -320,17 +316,17 @@ + if (DWC_CIRCLEQ_EMPTY_ENTRY + (channel, hc_list_entry)) { + hc_regs = +- dwc_otg_hcd->core_if->host_if-> +- hc_regs[i]; ++ dwc_otg_hcd->core_if-> ++ host_if->hc_regs[i]; + hcchar.d32 = +- dwc_read_reg32(&hc_regs->hcchar); ++ DWC_READ_REG32(&hc_regs->hcchar); + if (hcchar.b.chen) { + hcchar.b.chen = 0; + hcchar.b.chdis = 1; + hcchar.b.epdir = 0; +- dwc_write_reg32(&hc_regs-> +- hcchar, +- hcchar.d32); ++ DWC_WRITE_REG32 ++ (&hc_regs->hcchar, ++ hcchar.d32); + } + } + } +@@ -341,25 +337,25 @@ + if (DWC_CIRCLEQ_EMPTY_ENTRY(channel, hc_list_entry)) { + hc_regs = + dwc_otg_hcd->core_if->host_if->hc_regs[i]; +- hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); ++ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar); + if (hcchar.b.chen) { + /* Halt the channel. */ + hcchar.b.chdis = 1; +- dwc_write_reg32(&hc_regs->hcchar, ++ DWC_WRITE_REG32(&hc_regs->hcchar, + hcchar.d32); + } + + dwc_otg_hc_cleanup(dwc_otg_hcd->core_if, + channel); +- DWC_CIRCLEQ_INSERT_TAIL(&dwc_otg_hcd-> +- free_hc_list, channel, +- hc_list_entry); +- /* +- * Added for Descriptor DMA to prevent channel double cleanup ++ DWC_CIRCLEQ_INSERT_TAIL ++ (&dwc_otg_hcd->free_hc_list, channel, ++ hc_list_entry); ++ /* ++ * Added for Descriptor DMA to prevent channel double cleanup + * in release_channel_ddma(). Which called from ep_disable + * when device disconnect. +- */ +- channel->qh = NULL; ++ */ ++ channel->qh = NULL; + } + } + } +@@ -386,7 +382,7 @@ + } + + #ifdef CONFIG_USB_DWC_OTG_LPM +-/** ++/** + * HCD Callback function for sleep of HCD. + * + * @param p void pointer to the struct usb_hcd +@@ -443,44 +439,49 @@ + /* Turn off the vbus power */ + DWC_PRINTF("PortPower off\n"); + hprt0.b.prtpwr = 0; +- dwc_write_reg32(hcd->core_if->host_if->hprt0, hprt0.d32); ++ DWC_WRITE_REG32(hcd->core_if->host_if->hprt0, hprt0.d32); + dwc_mdelay(1); + } + + int dwc_otg_hcd_urb_enqueue(dwc_otg_hcd_t * hcd, +- dwc_otg_hcd_urb_t * dwc_otg_urb, void **ep_handle) ++ dwc_otg_hcd_urb_t * dwc_otg_urb, void **ep_handle, ++ int atomic_alloc) + { +- uint64_t flags; ++ dwc_irqflags_t flags; + int retval = 0; + dwc_otg_qtd_t *qtd; ++ gintmsk_data_t intr_mask = {.d32 = 0 }; + +- if (NULL == hcd->core_if) { //GRAYG ++#ifdef DEBUG /* integrity checks (Broadcom) */ ++ if (NULL == hcd->core_if) { + DWC_ERROR("**** DWC OTG HCD URB Enqueue - HCD has NULL core_if\n"); + /* No longer connected. */ + return -DWC_E_INVALID; + } +- ++#endif + if (!hcd->flags.b.port_connect_status) { + /* No longer connected. */ ++ DWC_ERROR("Not connected\n"); + return -DWC_E_NO_DEVICE; + } + +- qtd = dwc_otg_hcd_qtd_create(dwc_otg_urb); ++ qtd = dwc_otg_hcd_qtd_create(dwc_otg_urb, atomic_alloc); + if (qtd == NULL) { + DWC_ERROR("DWC OTG HCD URB Enqueue failed creating QTD\n"); + return -DWC_E_NO_MEMORY; + } +- if (qtd->urb == NULL) { //GRAYG ++#ifdef DEBUG /* integrity checks (Broadcom) */ ++ if (qtd->urb == NULL) { + DWC_ERROR("**** DWC OTG HCD URB Enqueue created QTD with no URBs\n"); + return -DWC_E_NO_MEMORY; + } +- if (qtd->urb->priv == NULL) { //GRAYG ++ if (qtd->urb->priv == NULL) { + DWC_ERROR("**** DWC OTG HCD URB Enqueue created QTD URB with no URB handle\n"); + return -DWC_E_NO_MEMORY; + } +- ++#endif + retval = +- dwc_otg_hcd_qtd_add(qtd, hcd, (dwc_otg_qh_t **) ep_handle); ++ dwc_otg_hcd_qtd_add(qtd, hcd, (dwc_otg_qh_t **) ep_handle, atomic_alloc); + // creates a new queue in ep_handle if it doesn't exist already + if (retval < 0) { + DWC_ERROR("DWC OTG HCD URB Enqueue failed adding QTD. " +@@ -489,11 +490,12 @@ + } else { + qtd->qh = *ep_handle; + } +- +- if (hcd->core_if->dma_desc_enable && retval == 0) { +- dwc_otg_transaction_type_e tr_type; +- if ((qtd->qh->ep_type == UE_BULK) && !(qtd->urb->flags & URB_GIVEBACK_ASAP)) { +- /* Do not schedule SG transcations until qtd has URB_GIVEBACK_ASAP set */ ++ intr_mask.d32 = DWC_READ_REG32(&hcd->core_if->core_global_regs->gintmsk); ++ if (!intr_mask.b.sofintr && retval == 0) { ++ dwc_otg_transaction_type_e tr_type; ++ if ((qtd->qh->ep_type == UE_BULK) ++ && !(qtd->urb->flags & URB_GIVEBACK_ASAP)) { ++ /* Do not schedule SG transactions until qtd has URB_GIVEBACK_ASAP set */ + return 0; + } + DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags); +@@ -510,42 +512,43 @@ + int dwc_otg_hcd_urb_dequeue(dwc_otg_hcd_t * hcd, + dwc_otg_hcd_urb_t * dwc_otg_urb) + { +- uint64_t flags; +- + dwc_otg_qh_t *qh; + dwc_otg_qtd_t *urb_qtd; + +- DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags); +- +- if (hcd == NULL) { //GRAYG ++#ifdef DEBUG /* integrity checks (Broadcom) */ ++ ++ if (hcd == NULL) { + DWC_ERROR("**** DWC OTG HCD URB Dequeue has NULL HCD\n"); + return -DWC_E_INVALID; + } +- if (dwc_otg_urb == NULL) { //GRAYG ++ if (dwc_otg_urb == NULL) { + DWC_ERROR("**** DWC OTG HCD URB Dequeue has NULL URB\n"); + return -DWC_E_INVALID; + } +- if (dwc_otg_urb->qtd == NULL) { //GRAYG ++ if (dwc_otg_urb->qtd == NULL) { + DWC_ERROR("**** DWC OTG HCD URB Dequeue with NULL QTD\n"); + return -DWC_E_INVALID; + } + urb_qtd = dwc_otg_urb->qtd; +- if (urb_qtd->qh == NULL) { //GRAYG ++ if (urb_qtd->qh == NULL) { + DWC_ERROR("**** DWC OTG HCD URB Dequeue with QTD with NULL Q handler\n"); + return -DWC_E_INVALID; + } ++#else ++ urb_qtd = dwc_otg_urb->qtd; ++#endif + qh = urb_qtd->qh; +-#ifdef DEBUG + if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) { + if (urb_qtd->in_process) { + dump_channel_info(hcd, qh); + } + } +-#endif +- if (hcd->core_if == NULL) { //GRAYG ++#ifdef DEBUG /* integrity checks (Broadcom) */ ++ if (hcd->core_if == NULL) { + DWC_ERROR("**** DWC OTG HCD URB Dequeue HCD has NULL core_if\n"); + return -DWC_E_INVALID; + } ++#endif + if (urb_qtd->in_process && qh->channel) { + /* The QTD is in process (it has been assigned to a channel). */ + if (hcd->flags.b.port_connect_status) { +@@ -565,12 +568,12 @@ + * Free the QTD and clean up the associated QH. Leave the QH in the + * schedule if it has any remaining QTDs. + */ +- ++ + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD URB Dequeue - " + "delete %sQueue handler\n", +- hcd->core_if->dma_desc_enable?"DMA ":""); //GRAYG ++ hcd->core_if->dma_desc_enable?"DMA ":""); + if (!hcd->core_if->dma_desc_enable) { +- uint8_t b = urb_qtd->in_process; ++ uint8_t b = urb_qtd->in_process; + dwc_otg_hcd_qtd_remove_and_free(hcd, urb_qtd, qh); + if (b) { + dwc_otg_hcd_qh_deactivate(hcd, qh, 0); +@@ -578,13 +581,9 @@ + } else if (DWC_CIRCLEQ_EMPTY(&qh->qtd_list)) { + dwc_otg_hcd_qh_remove(hcd, qh); + } +- } +- else { ++ } else { + dwc_otg_hcd_qtd_remove_and_free(hcd, urb_qtd, qh); + } +- +- DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags); +- + return 0; + } + +@@ -593,7 +592,7 @@ + { + dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle; + int retval = 0; +- uint64_t flags; ++ dwc_irqflags_t flags; + + if (retry < 0) { + retval = -DWC_E_INVALID; +@@ -601,11 +600,12 @@ + } + + if (!qh) { ++ retval = -DWC_E_INVALID; + goto done; + } + + DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags); +- ++ + while (!DWC_CIRCLEQ_EMPTY(&qh->qtd_list) && retry) { + DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags); + retry--; +@@ -614,20 +614,33 @@ + } + + dwc_otg_hcd_qh_remove(hcd, qh); +- ++ + DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags); +- /* +- * Split dwc_otg_hcd_qh_remove_and_free() into qh_remove +- * and qh_free to prevent stack dump on dwc_dma_free() with +- * irq_disabled (spinlock_irqsave) in dwc_otg_hcd_desc_list_free() ++ /* ++ * Split dwc_otg_hcd_qh_remove_and_free() into qh_remove ++ * and qh_free to prevent stack dump on DWC_DMA_FREE() with ++ * irq_disabled (spinlock_irqsave) in dwc_otg_hcd_desc_list_free() + * and dwc_otg_hcd_frame_list_alloc(). + */ + dwc_otg_hcd_qh_free(hcd, qh); + +- done: ++done: + return retval; + } + ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,30) ++int dwc_otg_hcd_endpoint_reset(dwc_otg_hcd_t * hcd, void *ep_handle) ++{ ++ int retval = 0; ++ dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle; ++ if (!qh) ++ return -DWC_E_INVALID; ++ ++ qh->data_toggle = DWC_OTG_HC_PID_DATA0; ++ return retval; ++} ++#endif ++ + /** + * HCD Callback structure for handling mode switching. + */ +@@ -656,11 +669,11 @@ + + hprt0.d32 = dwc_otg_read_hprt0(core_if); + hprt0.b.prtrst = 1; +- dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32); ++ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32); + dwc_mdelay(60); + + hprt0.b.prtrst = 0; +- dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32); ++ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32); + dwc_otg_hcd->flags.b.port_reset_change = 1; + } + +@@ -668,14 +681,20 @@ + { + dwc_list_link_t *item; + dwc_otg_qh_t *qh; ++ dwc_irqflags_t flags; + + if (!qh_list->next) { + /* The list hasn't been initialized yet. */ + return; + } +- ++ /* ++ * Hold spinlock here. Not needed in that case if bellow ++ * function is being called from ISR ++ */ ++ DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags); + /* Ensure there are no QTDs or URBs left. */ + kill_urbs_in_qh_list(hcd, qh_list); ++ DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags); + + DWC_LIST_FOREACH(item, qh_list) { + qh = DWC_LIST_ENTRY(item, dwc_otg_qh_t, qh_list_entry); +@@ -684,6 +703,68 @@ + } + + /** ++ * Exit from Hibernation if Host did not detect SRP from connected SRP capable ++ * Device during SRP time by host power up. ++ */ ++void dwc_otg_hcd_power_up(void *ptr) ++{ ++ gpwrdn_data_t gpwrdn = {.d32 = 0 }; ++ dwc_otg_core_if_t *core_if = (dwc_otg_core_if_t *) ptr; ++ ++ DWC_PRINTF("%s called\n", __FUNCTION__); ++ ++ if (!core_if->hibernation_suspend) { ++ DWC_PRINTF("Already exited from Hibernation\n"); ++ return; ++ } ++ ++ /* Switch on the voltage to the core */ ++ gpwrdn.b.pwrdnswtch = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ dwc_udelay(10); ++ ++ /* Reset the core */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pwrdnrstn = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ dwc_udelay(10); ++ ++ /* Disable power clamps */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pwrdnclmp = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ ++ /* Remove reset the core signal */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pwrdnrstn = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32); ++ dwc_udelay(10); ++ ++ /* Disable PMU interrupt */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pmuintsel = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ ++ core_if->hibernation_suspend = 0; ++ ++ /* Disable PMU */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pmuactv = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ dwc_udelay(10); ++ ++ /* Enable VBUS */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.dis_vbus = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ ++ core_if->op_state = A_HOST; ++ dwc_otg_core_init(core_if); ++ dwc_otg_enable_global_interrupts(core_if); ++ cil_hcd_start(core_if); ++} ++ ++/** + * Frees secondary storage associated with the dwc_otg_hcd structure contained + * in the struct usb_hcd field. + */ +@@ -715,23 +796,33 @@ + if (hc != NULL) { + DWC_DEBUGPL(DBG_HCDV, "HCD Free channel #%i, hc=%p\n", + i, hc); +- dwc_free(hc); ++ DWC_FREE(hc); + } + } + + if (dwc_otg_hcd->core_if->dma_enable) { + if (dwc_otg_hcd->status_buf_dma) { +- dwc_dma_free(DWC_OTG_HCD_STATUS_BUF_SIZE, ++ DWC_DMA_FREE(DWC_OTG_HCD_STATUS_BUF_SIZE, + dwc_otg_hcd->status_buf, + dwc_otg_hcd->status_buf_dma); + } + } else if (dwc_otg_hcd->status_buf != NULL) { +- dwc_free(dwc_otg_hcd->status_buf); ++ DWC_FREE(dwc_otg_hcd->status_buf); + } + DWC_SPINLOCK_FREE(dwc_otg_hcd->lock); ++ /* Set core_if's lock pointer to NULL */ ++ dwc_otg_hcd->core_if->lock = NULL; ++ + DWC_TIMER_FREE(dwc_otg_hcd->conn_timer); + DWC_TASK_FREE(dwc_otg_hcd->reset_tasklet); +- dwc_free(dwc_otg_hcd); ++ ++#ifdef DWC_DEV_SRPCAP ++ if (dwc_otg_hcd->core_if->power_down == 2 && ++ dwc_otg_hcd->core_if->pwron_timer) { ++ DWC_TIMER_FREE(dwc_otg_hcd->core_if->pwron_timer); ++ } ++#endif ++ DWC_FREE(dwc_otg_hcd); + } + + int dwc_otg_hcd_init(dwc_otg_hcd_t * hcd, dwc_otg_core_if_t * core_if) +@@ -742,11 +833,16 @@ + dwc_hc_t *channel; + + hcd->lock = DWC_SPINLOCK_ALLOC(); +- + DWC_DEBUGPL(DBG_HCDV, "init of HCD %p given core_if %p\n", +- hcd, core_if);//GRAYG +- ++ hcd, core_if); ++ if (!hcd->lock) { ++ DWC_ERROR("Could not allocate lock for pcd"); ++ DWC_FREE(hcd); ++ retval = -DWC_E_NO_MEMORY; ++ goto out; ++ } + hcd->core_if = core_if; ++ + /* Register the HCD CIL Callbacks */ + dwc_otg_cil_register_hcd_callbacks(hcd->core_if, + &hcd_cil_callbacks, hcd); +@@ -769,7 +865,7 @@ + num_channels = hcd->core_if->core_params->host_channels; + DWC_MEMSET(hcd->hc_ptr_array, 0, sizeof(hcd->hc_ptr_array)); + for (i = 0; i < num_channels; i++) { +- channel = dwc_alloc(sizeof(dwc_hc_t)); ++ channel = DWC_ALLOC(sizeof(dwc_hc_t)); + if (channel == NULL) { + retval = -DWC_E_NO_MEMORY; + DWC_ERROR("%s: host channel allocation failed\n", +@@ -793,7 +889,14 @@ + dwc_otg_hcd_connect_timeout, 0); + + /* Initialize reset tasklet. */ +- hcd->reset_tasklet = DWC_TASK_ALLOC(reset_tasklet_func, hcd); ++ hcd->reset_tasklet = DWC_TASK_ALLOC("reset_tasklet", reset_tasklet_func, hcd); ++#ifdef DWC_DEV_SRPCAP ++ if (hcd->core_if->power_down == 2) { ++ /* Initialize Power on timer for Host power up in case hibernation */ ++ hcd->core_if->pwron_timer = DWC_TIMER_ALLOC("PWRON TIMER", ++ dwc_otg_hcd_power_up, core_if); ++ } ++#endif + + /* + * Allocate space for storing data on status transactions. Normally no +@@ -803,10 +906,10 @@ + */ + if (hcd->core_if->dma_enable) { + hcd->status_buf = +- dwc_dma_alloc(DWC_OTG_HCD_STATUS_BUF_SIZE, ++ DWC_DMA_ALLOC(DWC_OTG_HCD_STATUS_BUF_SIZE, + &hcd->status_buf_dma); + } else { +- hcd->status_buf = dwc_alloc(DWC_OTG_HCD_STATUS_BUF_SIZE); ++ hcd->status_buf = DWC_ALLOC(DWC_OTG_HCD_STATUS_BUF_SIZE); + } + if (!hcd->status_buf) { + retval = -DWC_E_NO_MEMORY; +@@ -818,12 +921,7 @@ + hcd->otg_port = 1; + hcd->frame_list = NULL; + hcd->frame_list_dma = 0; +- +-#ifdef HW2937_WORKAROUND +- hcd->hw2937_xfer_mode = HW2937_XFER_MODE_IDLE; +- hcd->hw2937_assigned_channels = 0; +-#endif +- ++ hcd->periodic_qh_count = 0; + out: + return retval; + } +@@ -871,6 +969,9 @@ + + /* Initialize the DWC core for host mode operation. */ + dwc_otg_core_host_init(hcd->core_if); ++ ++ /* Set core_if's lock pointer to the hcd->lock */ ++ hcd->core_if->lock = hcd->lock; + } + + /** +@@ -882,19 +983,12 @@ + * @param qh Transactions from the first QTD for this QH are selected and + * assigned to a free host channel. + */ +-#ifdef HW2937_WORKAROUND +-static int assign_and_init_hc(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh) +-#else + static void assign_and_init_hc(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh) +-#endif + { + dwc_hc_t *hc; + dwc_otg_qtd_t *qtd; + dwc_otg_hcd_urb_t *urb; + void* ptr = NULL; +-#ifdef HW2937_WORKAROUND +- int ep_is_in; +-#endif + + qtd = DWC_CIRCLEQ_FIRST(&qh->qtd_list); + +@@ -902,13 +996,6 @@ + + DWC_DEBUGPL(DBG_HCDV, "%s(%p,%p) - urb %x, actual_length %d\n", __func__, hcd, qh, (unsigned int)urb, urb->actual_length); + +-#ifdef HW2937_WORKAROUND +- ep_is_in = (dwc_otg_hcd_is_pipe_in(&urb->pipe_info) != 0); +- if (ep_is_in && ((hcd->hw2937_xfer_mode == HW2937_XFER_MODE_OUT) || +- (hcd->hw2937_xfer_mode == HW2937_XFER_MODE_PAUSEIN))) +- return 0; +-#endif +- + if (((urb->actual_length < 0) || (urb->actual_length > urb->length)) && !dwc_otg_hcd_is_pipe_in(&urb->pipe_info)) + urb->actual_length = urb->length; + +@@ -917,8 +1004,9 @@ + + /* Remove the host channel from the free list. */ + DWC_CIRCLEQ_REMOVE_INIT(&hcd->free_hc_list, hc, hc_list_entry); ++ + qh->channel = hc; +- ++ + qtd->in_process = 1; + + /* +@@ -943,20 +1031,23 @@ + * started to accommodate the max widths of the XferSize and PktCnt + * fields in the HCTSIZn register. + */ +- hc->do_ping = qh->ping_state; +-#ifdef HW2937_WORKAROUND +- hc->ep_is_in = ep_is_in; +-#else ++ + hc->ep_is_in = (dwc_otg_hcd_is_pipe_in(&urb->pipe_info) != 0); +-#endif ++ if (hc->ep_is_in) { ++ hc->do_ping = 0; ++ } else { ++ hc->do_ping = qh->ping_state; ++ } ++ + hc->data_pid_start = qh->data_toggle; + hc->multi_count = 1; + + if (hcd->core_if->dma_enable) { + hc->xfer_buff = (uint8_t *) urb->dma + urb->actual_length; +- ++ + /* For non-dword aligned case */ +- if (((uint32_t)hc->xfer_buff & 0x3) && !hcd->core_if->dma_desc_enable) { ++ if (((unsigned long)hc->xfer_buff & 0x3) ++ && !hcd->core_if->dma_desc_enable) { + ptr = (uint8_t *) urb->buf + urb->actual_length; + } + } else { +@@ -1015,7 +1106,7 @@ + if (hc->ep_is_in) { + hc->do_ping = 0; + } +- ++ + hc->data_pid_start = DWC_OTG_HC_PID_DATA1; + + hc->xfer_len = 0; +@@ -1037,16 +1128,16 @@ + case UE_ISOCHRONOUS: + { + struct dwc_otg_hcd_iso_packet_desc *frame_desc; +- ++ + hc->ep_type = DWC_OTG_EP_TYPE_ISOC; +- ++ + if (hcd->core_if->dma_desc_enable) + break; +- ++ + frame_desc = &urb->iso_descs[qtd->isoc_frame_index]; +- ++ + frame_desc->status = 0; +- ++ + if (hcd->core_if->dma_enable) { + hc->xfer_buff = (uint8_t *) urb->dma; + } else { +@@ -1058,12 +1149,14 @@ + frame_desc->length - qtd->isoc_split_offset; + + /* For non-dword aligned buffers */ +- if (((uint32_t)hc->xfer_buff & 0x3) && hcd->core_if->dma_enable) { +- ptr = (uint8_t *) urb->buf + frame_desc->offset + qtd->isoc_split_offset; +- } +- else +- ptr = NULL; +- ++ if (((unsigned long)hc->xfer_buff & 0x3) ++ && hcd->core_if->dma_enable) { ++ ptr = ++ (uint8_t *) urb->buf + frame_desc->offset + ++ qtd->isoc_split_offset; ++ } else ++ ptr = NULL; ++ + if (hc->xact_pos == DWC_HCSPLIT_XACTPOS_ALL) { + if (hc->xfer_len <= 188) { + hc->xact_pos = DWC_HCSPLIT_XACTPOS_ALL; +@@ -1084,25 +1177,21 @@ + buf_size = 4096; + } + if (!qh->dw_align_buf) { +- qh->dw_align_buf = +- dwc_dma_alloc_atomic(buf_size, +- &qh->dw_align_buf_dma); ++ qh->dw_align_buf = DWC_DMA_ALLOC_ATOMIC(buf_size, ++ &qh->dw_align_buf_dma); + if (!qh->dw_align_buf) { +- DWC_ERROR("%s: Failed to allocate memory to handle " +- "non-dword aligned buffer case\n", __func__); +-#ifdef HW2937_WORKAROUND +- return 0; +-#else ++ DWC_ERROR ++ ("%s: Failed to allocate memory to handle " ++ "non-dword aligned buffer case\n", ++ __func__); + return; +-#endif + } + } + if (!hc->ep_is_in) { + dwc_memcpy(qh->dw_align_buf, ptr, hc->xfer_len); + } + hc->align_buff = qh->dw_align_buf_dma; +- } +- else { ++ } else { + hc->align_buff = 0; + } + +@@ -1114,184 +1203,14 @@ + */ + hc->multi_count = dwc_hb_mult(qh->maxp); + } +- ++ + if (hcd->core_if->dma_desc_enable) + hc->desc_list_addr = qh->desc_list_dma; +- ++ + dwc_otg_hc_init(hcd->core_if, hc); + hc->qh = qh; +-#ifdef HW2937_WORKAROUND +- hcd->hw2937_assigned_channels |= (1 << hc->hc_num); +- DWC_DEBUGPL(DBG_HW2937, " assign %d -> hw2937_ac %x\n", hc->hc_num, hcd->hw2937_assigned_channels); +- return 1; +-#endif + } + +-#ifdef HW2937_WORKAROUND +- +-void debug_halt(void) +-{ +- spinlock_t mr_lock = SPIN_LOCK_UNLOCKED; +- unsigned long flags; +- extern void v6_flush_kern_cache_all(void); +- +- spin_lock_irqsave(&mr_lock, flags); +-#ifdef CONFIG_MACH_BCM2708 +- v6_flush_kern_cache_all(); +-#endif +- while (1) continue; +-} +- +-static +-void dwc_otg_hcd_disable_in_channels(dwc_otg_hcd_t * hcd) +-{ +- int num_channels = hcd->core_if->core_params->host_channels; +- static int stall_count = 0; +- static int max_stall_count = 1; +- static int last_stalled = 0; +- int stalled = 0; +- int i; +- +- DWC_DEBUGPL(DBG_HW2937, " Disable In Channels(%x)\n", hcd->hw2937_assigned_channels); +- +- for (i = 0; i < num_channels; i++) { +- if (hcd->hw2937_assigned_channels & (1 << i)) { +- dwc_hc_t *hc = hcd->hc_ptr_array[i]; +- if (!hc->halt_pending) { +- dwc_otg_hc_regs_t *hc_regs = hcd->core_if->host_if->hc_regs[hc->hc_num]; +- hctsiz_data_t hctsiz; +- hctsiz.d32 = dwc_read_reg32(&hc_regs->hctsiz); +- DWC_DEBUGPL(DBG_HW2937, "pktcnt %d, xfersize %x, xfer_len %x\n", hctsiz.b.pktcnt, hctsiz.b.xfersize, hc->xfer_len); +- if (hctsiz.b.pktcnt == hc->start_pkt_count) +- { +- dwc_otg_hc_halt(hcd->core_if, hc, DWC_OTG_HC_XFER_PAUSE_IN); +- } +- else +- { +- /* Unless a receive is in progress */ +- stalled |= (1< max_stall_count) +- { +- max_stall_count = stall_count; +- DWC_PRINTF( "stall (%x) count -> %d\n", stalled, stall_count); +- if (stall_count == 10) +- { +- debug_halt(); +- } +- } +- } +- else +- { +- stall_count = 0; +- last_stalled = stalled; +- } +-} +- +-static +-int dwc_otg_hcd_update_transaction_mode(dwc_otg_hcd_t * hcd) +-{ +- dwc_list_link_t *qh_ptr; +- dwc_otg_qh_t *qh; +- dwc_otg_qtd_t *qtd; +- dwc_otg_hcd_urb_t *urb; +- int found_in = 0; +- +- /* If there are any existing out transactions, stay in OUT mode */ +- if (hcd->hw2937_xfer_mode == HW2937_XFER_MODE_OUT) +- { +- return 1; +- } +- +- /* Scan entries in the periodic ready list. */ +- qh_ptr = DWC_LIST_FIRST(&hcd->periodic_sched_ready); +- +- while (qh_ptr != &hcd->periodic_sched_ready) { +- qh = DWC_LIST_ENTRY(qh_ptr, dwc_otg_qh_t, qh_list_entry); +- qtd = DWC_CIRCLEQ_FIRST(&qh->qtd_list); +- urb = qtd->urb; +- if (!dwc_otg_hcd_is_pipe_in(&urb->pipe_info)) { +- /* Switch to OUT mode */ +- switch (hcd->hw2937_xfer_mode) +- { +- case HW2937_XFER_MODE_IDLE: +- DWC_DEBUGPL(DBG_HW2937, "utm -> OUT\n"); +- hcd->hw2937_xfer_mode = HW2937_XFER_MODE_OUT; +- /* Drop through... */ +- case HW2937_XFER_MODE_OUT: +- return 1; +- case HW2937_XFER_MODE_IN: +- DWC_DEBUGPL(DBG_HW2937, "utm - halting %x INs\n", hcd->hw2937_assigned_channels); +- /* Disable the channels with outstanding INs */ +- dwc_otg_hcd_disable_in_channels(hcd); +- +- DWC_DEBUGPL(DBG_HW2937, "utm -> PAUSEIN\n"); +- hcd->hw2937_xfer_mode = HW2937_XFER_MODE_PAUSEIN; +- /* Drop through... */ +- case HW2937_XFER_MODE_PAUSEIN: +- /* Delay until the halt completes */ +- return 0; +- } +- } +- found_in = 1; +- qh_ptr = DWC_LIST_NEXT(qh_ptr); +- } +- +- /* +- * Scan entries in the inactive portion of the non-periodic +- * schedule. +- */ +- qh_ptr = hcd->non_periodic_sched_inactive.next; +- while (qh_ptr != &hcd->non_periodic_sched_inactive) { +- qh = DWC_LIST_ENTRY(qh_ptr, dwc_otg_qh_t, qh_list_entry); +- qtd = DWC_CIRCLEQ_FIRST(&qh->qtd_list); +- urb = qtd->urb; +- if (!dwc_otg_hcd_is_pipe_in(&urb->pipe_info)) { +- /* Switch to OUT mode */ +- switch (hcd->hw2937_xfer_mode) +- { +- case HW2937_XFER_MODE_IDLE: +- DWC_DEBUGPL(DBG_HW2937, "utm -> OUT\n"); +- hcd->hw2937_xfer_mode = HW2937_XFER_MODE_OUT; +- /* Drop through... */ +- case HW2937_XFER_MODE_OUT: +- return 1; +- case HW2937_XFER_MODE_IN: +- DWC_DEBUGPL(DBG_HW2937, "utm - halting %x INs\n", hcd->hw2937_assigned_channels); +- /* Disable the channels with outstanding INs */ +- dwc_otg_hcd_disable_in_channels(hcd); +- +- DWC_DEBUGPL(DBG_HW2937, "utm -> PAUSEIN\n"); +- hcd->hw2937_xfer_mode = HW2937_XFER_MODE_PAUSEIN; +- /* Drop through... */ +- case HW2937_XFER_MODE_PAUSEIN: +- /* Delay until the halt completes */ +- return 0; +- } +- } +- found_in = 1; +- qh_ptr = DWC_LIST_NEXT(qh_ptr); +- } +- +- if (found_in && (hcd->hw2937_xfer_mode == HW2937_XFER_MODE_IDLE)) +- { +- DWC_DEBUGPL(DBG_HW2937, "utm -> IN\n"); +- hcd->hw2937_xfer_mode = HW2937_XFER_MODE_IN; +- } +- return 1; +-} +- +-#endif /* HW2937_WORKAROUND */ +- + /** + * This function selects transactions from the HCD transfer schedule and + * assigns them to available host channels. It is called from HCD interrupt +@@ -1312,24 +1231,13 @@ + DWC_DEBUGPL(DBG_HCD, " Select Transactions\n"); + #endif + +-#ifdef HW2937_WORKAROUND +- if (!dwc_otg_hcd_update_transaction_mode(hcd)) +- { +- return ret_val; +- } +-#endif +- + /* Process entries in the periodic ready list. */ + qh_ptr = DWC_LIST_FIRST(&hcd->periodic_sched_ready); + + while (qh_ptr != &hcd->periodic_sched_ready && + !DWC_CIRCLEQ_EMPTY(&hcd->free_hc_list)) { + qh = DWC_LIST_ENTRY(qh_ptr, dwc_otg_qh_t, qh_list_entry); +-#ifdef HW2937_WORKAROUND +- if (assign_and_init_hc(hcd, qh)) { +-#else + assign_and_init_hc(hcd, qh); +-#endif + + /* + * Move the QH from the periodic ready schedule to the +@@ -1340,11 +1248,6 @@ + &qh->qh_list_entry); + + ret_val = DWC_OTG_TRANSACTION_PERIODIC; +-#ifdef HW2937_WORKAROUND +- } else { +- qh_ptr = DWC_LIST_NEXT(qh_ptr); +- } +-#endif + } + + /* +@@ -1361,11 +1264,7 @@ + + qh = DWC_LIST_ENTRY(qh_ptr, dwc_otg_qh_t, qh_list_entry); + +-#ifdef HW2937_WORKAROUND +- if (assign_and_init_hc(hcd, qh)) { +-#else + assign_and_init_hc(hcd, qh); +-#endif + + /* + * Move the QH from the non-periodic inactive schedule to the +@@ -1382,15 +1281,11 @@ + } + + hcd->non_periodic_channels++; +-#ifdef HW2937_WORKAROUND +- } else { +- qh_ptr = DWC_LIST_NEXT(qh_ptr); +- } +-#endif + } + + return ret_val; + } ++ + /** + * Attempts to queue a single transaction request for a host channel + * associated with either a periodic or non-periodic transfer. This function +@@ -1416,12 +1311,12 @@ + + if (hcd->core_if->dma_enable) { + if (hcd->core_if->dma_desc_enable) { +- if (!hc->xfer_started || (hc->ep_type == DWC_OTG_EP_TYPE_ISOC)) { ++ if (!hc->xfer_started ++ || (hc->ep_type == DWC_OTG_EP_TYPE_ISOC)) { + dwc_otg_hcd_start_xfer_ddma(hcd, hc->qh); + hc->qh->ping_state = 0; + } +- } +- else if (!hc->xfer_started) { ++ } else if (!hc->xfer_started) { + dwc_otg_hc_start_transfer(hcd->core_if, hc); + hc->qh->ping_state = 0; + } +@@ -1483,7 +1378,7 @@ + + DWC_DEBUGPL(DBG_HCDV, "Queue periodic transactions\n"); + #ifdef DEBUG +- tx_status.d32 = dwc_read_reg32(&host_regs->hptxsts); ++ tx_status.d32 = DWC_READ_REG32(&host_regs->hptxsts); + DWC_DEBUGPL(DBG_HCDV, + " P Tx Req Queue Space Avail (before queue): %d\n", + tx_status.b.ptxqspcavail); +@@ -1493,7 +1388,7 @@ + + qh_ptr = hcd->periodic_sched_assigned.next; + while (qh_ptr != &hcd->periodic_sched_assigned) { +- tx_status.d32 = dwc_read_reg32(&host_regs->hptxsts); ++ tx_status.d32 = DWC_READ_REG32(&host_regs->hptxsts); + if (tx_status.b.ptxqspcavail == 0) { + no_queue_space = 1; + break; +@@ -1546,7 +1441,7 @@ + global_regs = hcd->core_if->core_global_regs; + intr_mask.b.ptxfempty = 1; + #ifdef DEBUG +- tx_status.d32 = dwc_read_reg32(&host_regs->hptxsts); ++ tx_status.d32 = DWC_READ_REG32(&host_regs->hptxsts); + DWC_DEBUGPL(DBG_HCDV, + " P Tx Req Queue Space Avail (after queue): %d\n", + tx_status.b.ptxqspcavail); +@@ -1563,7 +1458,7 @@ + * level to ensure that new requests are loaded as + * soon as possible.) + */ +- dwc_modify_reg32(&global_regs->gintmsk, 0, ++ DWC_MODIFY_REG32(&global_regs->gintmsk, 0, + intr_mask.d32); + } else { + /* +@@ -1573,7 +1468,7 @@ + * handlers to queue more transactions as transfer + * states change. + */ +- dwc_modify_reg32(&global_regs->gintmsk, intr_mask.d32, ++ DWC_MODIFY_REG32(&global_regs->gintmsk, intr_mask.d32, + 0); + } + } +@@ -1601,7 +1496,7 @@ + + DWC_DEBUGPL(DBG_HCDV, "Queue non-periodic transactions\n"); + #ifdef DEBUG +- tx_status.d32 = dwc_read_reg32(&global_regs->gnptxsts); ++ tx_status.d32 = DWC_READ_REG32(&global_regs->gnptxsts); + DWC_DEBUGPL(DBG_HCDV, + " NP Tx Req Queue Space Avail (before queue): %d\n", + tx_status.b.nptxqspcavail); +@@ -1622,7 +1517,7 @@ + * available in the request queue or the Tx FIFO. + */ + do { +- tx_status.d32 = dwc_read_reg32(&global_regs->gnptxsts); ++ tx_status.d32 = DWC_READ_REG32(&global_regs->gnptxsts); + if (!hcd->core_if->dma_enable && tx_status.b.nptxqspcavail == 0) { + no_queue_space = 1; + break; +@@ -1655,7 +1550,7 @@ + intr_mask.b.nptxfempty = 1; + + #ifdef DEBUG +- tx_status.d32 = dwc_read_reg32(&global_regs->gnptxsts); ++ tx_status.d32 = DWC_READ_REG32(&global_regs->gnptxsts); + DWC_DEBUGPL(DBG_HCDV, + " NP Tx Req Queue Space Avail (after queue): %d\n", + tx_status.b.nptxqspcavail); +@@ -1671,7 +1566,7 @@ + * level to ensure that new requests are loaded as + * soon as possible.) + */ +- dwc_modify_reg32(&global_regs->gintmsk, 0, ++ DWC_MODIFY_REG32(&global_regs->gintmsk, 0, + intr_mask.d32); + } else { + /* +@@ -1681,7 +1576,7 @@ + * handlers to queue more transactions as transfer + * states change. + */ +- dwc_modify_reg32(&global_regs->gintmsk, intr_mask.d32, ++ DWC_MODIFY_REG32(&global_regs->gintmsk, intr_mask.d32, + 0); + } + } +@@ -1697,7 +1592,7 @@ + * periodic, or both). + */ + void dwc_otg_hcd_queue_transactions(dwc_otg_hcd_t * hcd, +- dwc_otg_transaction_type_e tr_type) ++ dwc_otg_transaction_type_e tr_type) + { + #ifdef DEBUG_SOF + DWC_DEBUGPL(DBG_HCD, "Queue Transactions\n"); +@@ -1722,12 +1617,13 @@ + */ + gintmsk_data_t gintmsk = {.d32 = 0 }; + gintmsk.b.nptxfempty = 1; +- dwc_modify_reg32(&hcd->core_if->core_global_regs-> +- gintmsk, gintmsk.d32, 0); ++ DWC_MODIFY_REG32(&hcd->core_if-> ++ core_global_regs->gintmsk, gintmsk.d32, ++ 0); + } + } + } +- ++ + #ifdef DWC_HS_ELECT_TST + /* + * Quick and dirty hack to implement the HS Electrical Test +@@ -1756,70 +1652,70 @@ + hcint_data_t hcint; + + /* Enable HAINTs */ +- dwc_write_reg32(&hc_global_regs->haintmsk, 0x0001); ++ DWC_WRITE_REG32(&hc_global_regs->haintmsk, 0x0001); + + /* Enable HCINTs */ +- dwc_write_reg32(&hc_regs->hcintmsk, 0x04a3); ++ DWC_WRITE_REG32(&hc_regs->hcintmsk, 0x04a3); + + /* Read GINTSTS */ +- gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); ++ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts); + + /* Read HAINT */ +- haint.d32 = dwc_read_reg32(&hc_global_regs->haint); ++ haint.d32 = DWC_READ_REG32(&hc_global_regs->haint); + + /* Read HCINT */ +- hcint.d32 = dwc_read_reg32(&hc_regs->hcint); ++ hcint.d32 = DWC_READ_REG32(&hc_regs->hcint); + + /* Read HCCHAR */ +- hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); ++ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar); + + /* Clear HCINT */ +- dwc_write_reg32(&hc_regs->hcint, hcint.d32); ++ DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32); + + /* Clear HAINT */ +- dwc_write_reg32(&hc_global_regs->haint, haint.d32); ++ DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32); + + /* Clear GINTSTS */ +- dwc_write_reg32(&global_regs->gintsts, gintsts.d32); ++ DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32); + + /* Read GINTSTS */ +- gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); ++ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts); + + /* + * Send Setup packet (Get Device Descriptor) + */ + + /* Make sure channel is disabled */ +- hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); ++ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar); + if (hcchar.b.chen) { + hcchar.b.chdis = 1; + // hcchar.b.chen = 1; +- dwc_write_reg32(&hc_regs->hcchar, hcchar.d32); ++ DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32); + //sleep(1); + dwc_mdelay(1000); + + /* Read GINTSTS */ +- gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); ++ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts); + + /* Read HAINT */ +- haint.d32 = dwc_read_reg32(&hc_global_regs->haint); ++ haint.d32 = DWC_READ_REG32(&hc_global_regs->haint); + + /* Read HCINT */ +- hcint.d32 = dwc_read_reg32(&hc_regs->hcint); ++ hcint.d32 = DWC_READ_REG32(&hc_regs->hcint); + + /* Read HCCHAR */ +- hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); ++ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar); + + /* Clear HCINT */ +- dwc_write_reg32(&hc_regs->hcint, hcint.d32); ++ DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32); + + /* Clear HAINT */ +- dwc_write_reg32(&hc_global_regs->haint, haint.d32); ++ DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32); + + /* Clear GINTSTS */ +- dwc_write_reg32(&global_regs->gintsts, gintsts.d32); ++ DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32); + +- hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); ++ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar); + } + + /* Set HCTSIZ */ +@@ -1827,56 +1723,55 @@ + hctsiz.b.xfersize = 8; + hctsiz.b.pktcnt = 1; + hctsiz.b.pid = DWC_OTG_HC_PID_SETUP; +- dwc_write_reg32(&hc_regs->hctsiz, hctsiz.d32); ++ DWC_WRITE_REG32(&hc_regs->hctsiz, hctsiz.d32); + + /* Set HCCHAR */ +- hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); ++ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar); + hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL; + hcchar.b.epdir = 0; + hcchar.b.epnum = 0; + hcchar.b.mps = 8; + hcchar.b.chen = 1; +- dwc_write_reg32(&hc_regs->hcchar, hcchar.d32); ++ DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32); + + /* Fill FIFO with Setup data for Get Device Descriptor */ + data_fifo = (uint32_t *) ((char *)global_regs + 0x1000); +- dwc_write_reg32(data_fifo++, 0x01000680); +- dwc_write_reg32(data_fifo++, 0x00080000); ++ DWC_WRITE_REG32(data_fifo++, 0x01000680); ++ DWC_WRITE_REG32(data_fifo++, 0x00080000); + +- gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); ++ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts); + + /* Wait for host channel interrupt */ + do { +- gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); ++ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts); + } while (gintsts.b.hcintr == 0); + +- + /* Disable HCINTs */ +- dwc_write_reg32(&hc_regs->hcintmsk, 0x0000); ++ DWC_WRITE_REG32(&hc_regs->hcintmsk, 0x0000); + + /* Disable HAINTs */ +- dwc_write_reg32(&hc_global_regs->haintmsk, 0x0000); ++ DWC_WRITE_REG32(&hc_global_regs->haintmsk, 0x0000); + + /* Read HAINT */ +- haint.d32 = dwc_read_reg32(&hc_global_regs->haint); ++ haint.d32 = DWC_READ_REG32(&hc_global_regs->haint); + + /* Read HCINT */ +- hcint.d32 = dwc_read_reg32(&hc_regs->hcint); ++ hcint.d32 = DWC_READ_REG32(&hc_regs->hcint); + + /* Read HCCHAR */ +- hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); ++ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar); + + /* Clear HCINT */ +- dwc_write_reg32(&hc_regs->hcint, hcint.d32); ++ DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32); + + /* Clear HAINT */ +- dwc_write_reg32(&hc_global_regs->haint, haint.d32); ++ DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32); + + /* Clear GINTSTS */ +- dwc_write_reg32(&global_regs->gintsts, gintsts.d32); ++ DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32); + + /* Read GINTSTS */ +- gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); ++ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts); + } + + static void do_in_ack(void) +@@ -1889,70 +1784,70 @@ + host_grxsts_data_t grxsts; + + /* Enable HAINTs */ +- dwc_write_reg32(&hc_global_regs->haintmsk, 0x0001); ++ DWC_WRITE_REG32(&hc_global_regs->haintmsk, 0x0001); + + /* Enable HCINTs */ +- dwc_write_reg32(&hc_regs->hcintmsk, 0x04a3); ++ DWC_WRITE_REG32(&hc_regs->hcintmsk, 0x04a3); + + /* Read GINTSTS */ +- gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); ++ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts); + + /* Read HAINT */ +- haint.d32 = dwc_read_reg32(&hc_global_regs->haint); ++ haint.d32 = DWC_READ_REG32(&hc_global_regs->haint); + + /* Read HCINT */ +- hcint.d32 = dwc_read_reg32(&hc_regs->hcint); ++ hcint.d32 = DWC_READ_REG32(&hc_regs->hcint); + + /* Read HCCHAR */ +- hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); ++ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar); + + /* Clear HCINT */ +- dwc_write_reg32(&hc_regs->hcint, hcint.d32); ++ DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32); + + /* Clear HAINT */ +- dwc_write_reg32(&hc_global_regs->haint, haint.d32); ++ DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32); + + /* Clear GINTSTS */ +- dwc_write_reg32(&global_regs->gintsts, gintsts.d32); ++ DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32); + + /* Read GINTSTS */ +- gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); ++ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts); + + /* + * Receive Control In packet + */ + + /* Make sure channel is disabled */ +- hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); ++ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar); + if (hcchar.b.chen) { + hcchar.b.chdis = 1; + hcchar.b.chen = 1; +- dwc_write_reg32(&hc_regs->hcchar, hcchar.d32); ++ DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32); + //sleep(1); + dwc_mdelay(1000); + + /* Read GINTSTS */ +- gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); ++ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts); + + /* Read HAINT */ +- haint.d32 = dwc_read_reg32(&hc_global_regs->haint); ++ haint.d32 = DWC_READ_REG32(&hc_global_regs->haint); + + /* Read HCINT */ +- hcint.d32 = dwc_read_reg32(&hc_regs->hcint); ++ hcint.d32 = DWC_READ_REG32(&hc_regs->hcint); + + /* Read HCCHAR */ +- hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); ++ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar); + + /* Clear HCINT */ +- dwc_write_reg32(&hc_regs->hcint, hcint.d32); ++ DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32); + + /* Clear HAINT */ +- dwc_write_reg32(&hc_global_regs->haint, haint.d32); ++ DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32); + + /* Clear GINTSTS */ +- dwc_write_reg32(&global_regs->gintsts, gintsts.d32); ++ DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32); + +- hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); ++ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar); + } + + /* Set HCTSIZ */ +@@ -1960,32 +1855,31 @@ + hctsiz.b.xfersize = 8; + hctsiz.b.pktcnt = 1; + hctsiz.b.pid = DWC_OTG_HC_PID_DATA1; +- dwc_write_reg32(&hc_regs->hctsiz, hctsiz.d32); ++ DWC_WRITE_REG32(&hc_regs->hctsiz, hctsiz.d32); + + /* Set HCCHAR */ +- hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); ++ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar); + hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL; + hcchar.b.epdir = 1; + hcchar.b.epnum = 0; + hcchar.b.mps = 8; + hcchar.b.chen = 1; +- dwc_write_reg32(&hc_regs->hcchar, hcchar.d32); ++ DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32); + +- gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); ++ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts); + + /* Wait for receive status queue interrupt */ + do { +- gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); ++ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts); + } while (gintsts.b.rxstsqlvl == 0); + +- + /* Read RXSTS */ +- grxsts.d32 = dwc_read_reg32(&global_regs->grxstsp); ++ grxsts.d32 = DWC_READ_REG32(&global_regs->grxstsp); + + /* Clear RXSTSQLVL in GINTSTS */ + gintsts.d32 = 0; + gintsts.b.rxstsqlvl = 1; +- dwc_write_reg32(&global_regs->gintsts, gintsts.d32); ++ DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32); + + switch (grxsts.b.pktsts) { + case DWC_GRXSTS_PKTSTS_IN: +@@ -1997,7 +1891,7 @@ + data_fifo = (uint32_t *) ((char *)global_regs + 0x1000); + + for (i = 0; i < word_count; i++) { +- (void)dwc_read_reg32(data_fifo++); ++ (void)DWC_READ_REG32(data_fifo++); + } + } + break; +@@ -2006,21 +1900,20 @@ + break; + } + +- gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); ++ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts); + + /* Wait for receive status queue interrupt */ + do { +- gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); ++ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts); + } while (gintsts.b.rxstsqlvl == 0); + +- + /* Read RXSTS */ +- grxsts.d32 = dwc_read_reg32(&global_regs->grxstsp); ++ grxsts.d32 = DWC_READ_REG32(&global_regs->grxstsp); + + /* Clear RXSTSQLVL in GINTSTS */ + gintsts.d32 = 0; + gintsts.b.rxstsqlvl = 1; +- dwc_write_reg32(&global_regs->gintsts, gintsts.d32); ++ DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32); + + switch (grxsts.b.pktsts) { + case DWC_GRXSTS_PKTSTS_IN_XFER_COMP: +@@ -2030,34 +1923,33 @@ + break; + } + +- gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); ++ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts); + + /* Wait for host channel interrupt */ + do { +- gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); ++ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts); + } while (gintsts.b.hcintr == 0); + +- + /* Read HAINT */ +- haint.d32 = dwc_read_reg32(&hc_global_regs->haint); ++ haint.d32 = DWC_READ_REG32(&hc_global_regs->haint); + + /* Read HCINT */ +- hcint.d32 = dwc_read_reg32(&hc_regs->hcint); ++ hcint.d32 = DWC_READ_REG32(&hc_regs->hcint); + + /* Read HCCHAR */ +- hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); ++ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar); + + /* Clear HCINT */ +- dwc_write_reg32(&hc_regs->hcint, hcint.d32); ++ DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32); + + /* Clear HAINT */ +- dwc_write_reg32(&hc_global_regs->haint, haint.d32); ++ DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32); + + /* Clear GINTSTS */ +- dwc_write_reg32(&global_regs->gintsts, gintsts.d32); ++ DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32); + + /* Read GINTSTS */ +- gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); ++ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts); + + // usleep(100000); + // mdelay(100); +@@ -2068,57 +1960,57 @@ + */ + + /* Read HAINT */ +- haint.d32 = dwc_read_reg32(&hc_global_regs->haint); ++ haint.d32 = DWC_READ_REG32(&hc_global_regs->haint); + + /* Read HCINT */ +- hcint.d32 = dwc_read_reg32(&hc_regs->hcint); ++ hcint.d32 = DWC_READ_REG32(&hc_regs->hcint); + + /* Read HCCHAR */ +- hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); ++ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar); + + /* Clear HCINT */ +- dwc_write_reg32(&hc_regs->hcint, hcint.d32); ++ DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32); + + /* Clear HAINT */ +- dwc_write_reg32(&hc_global_regs->haint, haint.d32); ++ DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32); + + /* Clear GINTSTS */ +- dwc_write_reg32(&global_regs->gintsts, gintsts.d32); ++ DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32); + + /* Read GINTSTS */ +- gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); ++ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts); + + /* Make sure channel is disabled */ +- hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); ++ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar); + if (hcchar.b.chen) { + hcchar.b.chdis = 1; + hcchar.b.chen = 1; +- dwc_write_reg32(&hc_regs->hcchar, hcchar.d32); ++ DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32); + //sleep(1); + dwc_mdelay(1000); + + /* Read GINTSTS */ +- gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); ++ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts); + + /* Read HAINT */ +- haint.d32 = dwc_read_reg32(&hc_global_regs->haint); ++ haint.d32 = DWC_READ_REG32(&hc_global_regs->haint); + + /* Read HCINT */ +- hcint.d32 = dwc_read_reg32(&hc_regs->hcint); ++ hcint.d32 = DWC_READ_REG32(&hc_regs->hcint); + + /* Read HCCHAR */ +- hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); ++ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar); + + /* Clear HCINT */ +- dwc_write_reg32(&hc_regs->hcint, hcint.d32); ++ DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32); + + /* Clear HAINT */ +- dwc_write_reg32(&hc_global_regs->haint, haint.d32); ++ DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32); + + /* Clear GINTSTS */ +- dwc_write_reg32(&global_regs->gintsts, gintsts.d32); ++ DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32); + +- hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); ++ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar); + } + + /* Set HCTSIZ */ +@@ -2126,51 +2018,50 @@ + hctsiz.b.xfersize = 0; + hctsiz.b.pktcnt = 1; + hctsiz.b.pid = DWC_OTG_HC_PID_DATA1; +- dwc_write_reg32(&hc_regs->hctsiz, hctsiz.d32); ++ DWC_WRITE_REG32(&hc_regs->hctsiz, hctsiz.d32); + + /* Set HCCHAR */ +- hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); ++ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar); + hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL; + hcchar.b.epdir = 0; + hcchar.b.epnum = 0; + hcchar.b.mps = 8; + hcchar.b.chen = 1; +- dwc_write_reg32(&hc_regs->hcchar, hcchar.d32); ++ DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32); + +- gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); ++ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts); + + /* Wait for host channel interrupt */ + do { +- gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); ++ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts); + } while (gintsts.b.hcintr == 0); + +- + /* Disable HCINTs */ +- dwc_write_reg32(&hc_regs->hcintmsk, 0x0000); ++ DWC_WRITE_REG32(&hc_regs->hcintmsk, 0x0000); + + /* Disable HAINTs */ +- dwc_write_reg32(&hc_global_regs->haintmsk, 0x0000); ++ DWC_WRITE_REG32(&hc_global_regs->haintmsk, 0x0000); + + /* Read HAINT */ +- haint.d32 = dwc_read_reg32(&hc_global_regs->haint); ++ haint.d32 = DWC_READ_REG32(&hc_global_regs->haint); + + /* Read HCINT */ +- hcint.d32 = dwc_read_reg32(&hc_regs->hcint); ++ hcint.d32 = DWC_READ_REG32(&hc_regs->hcint); + + /* Read HCCHAR */ +- hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); ++ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar); + + /* Clear HCINT */ +- dwc_write_reg32(&hc_regs->hcint, hcint.d32); ++ DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32); + + /* Clear HAINT */ +- dwc_write_reg32(&hc_global_regs->haint, haint.d32); ++ DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32); + + /* Clear GINTSTS */ +- dwc_write_reg32(&global_regs->gintsts, gintsts.d32); ++ DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32); + + /* Read GINTSTS */ +- gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); ++ gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts); + } + #endif + +@@ -2217,23 +2108,27 @@ + "ClearPortFeature USB_PORT_FEAT_ENABLE\n"); + hprt0.d32 = dwc_otg_read_hprt0(core_if); + hprt0.b.prtena = 1; +- dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32); ++ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32); + break; + case UHF_PORT_SUSPEND: + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - " + "ClearPortFeature USB_PORT_FEAT_SUSPEND\n"); + +- dwc_write_reg32(core_if->pcgcctl, 0); +- dwc_mdelay(5); ++ if (core_if->power_down == 2) { ++ dwc_otg_host_hibernation_restore(core_if, 0, 0); ++ } else { ++ DWC_WRITE_REG32(core_if->pcgcctl, 0); ++ dwc_mdelay(5); + +- hprt0.d32 = dwc_otg_read_hprt0(core_if); +- hprt0.b.prtres = 1; +- dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32); +- hprt0.b.prtsusp = 0; +- /* Clear Resume bit */ +- dwc_mdelay(100); +- hprt0.b.prtres = 0; +- dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32); ++ hprt0.d32 = dwc_otg_read_hprt0(core_if); ++ hprt0.b.prtres = 1; ++ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32); ++ hprt0.b.prtsusp = 0; ++ /* Clear Resume bit */ ++ dwc_mdelay(100); ++ hprt0.b.prtres = 0; ++ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32); ++ } + break; + #ifdef CONFIG_USB_DWC_OTG_LPM + case UHF_PORT_L1: +@@ -2242,24 +2137,25 @@ + glpmcfg_data_t lpmcfg = {.d32 = 0 }; + + lpmcfg.d32 = +- dwc_read_reg32(&core_if->core_global_regs-> +- glpmcfg); ++ DWC_READ_REG32(&core_if-> ++ core_global_regs->glpmcfg); + lpmcfg.b.en_utmi_sleep = 0; + lpmcfg.b.hird_thres &= (~(1 << 4)); + lpmcfg.b.prt_sleep_sts = 1; +- dwc_write_reg32(&core_if->core_global_regs-> +- glpmcfg, lpmcfg.d32); ++ DWC_WRITE_REG32(&core_if-> ++ core_global_regs->glpmcfg, ++ lpmcfg.d32); + + /* Clear Enbl_L1Gating bit. */ + pcgcctl.b.enbl_sleep_gating = 1; +- dwc_modify_reg32(core_if->pcgcctl, pcgcctl.d32, ++ DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32, + 0); + + dwc_mdelay(5); + + hprt0.d32 = dwc_otg_read_hprt0(core_if); + hprt0.b.prtres = 1; +- dwc_write_reg32(core_if->host_if->hprt0, ++ DWC_WRITE_REG32(core_if->host_if->hprt0, + hprt0.d32); + /* This bit will be cleared in wakeup interrupt handle */ + break; +@@ -2270,7 +2166,7 @@ + "ClearPortFeature USB_PORT_FEAT_POWER\n"); + hprt0.d32 = dwc_otg_read_hprt0(core_if); + hprt0.b.prtpwr = 0; +- dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32); ++ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32); + break; + case UHF_PORT_INDICATOR: + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - " +@@ -2343,7 +2239,8 @@ + break; + case UCR_GET_PORT_STATUS: + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - " +- "GetPortStatus\n"); ++ "GetPortStatus wIndex = 0x%04x FLAGS=0x%08x\n", ++ wIndex, dwc_otg_hcd->flags.d32); + if (!wIndex || wIndex > 1) + goto error; + +@@ -2366,7 +2263,7 @@ + } + + if (dwc_otg_hcd->flags.b.port_over_current_change) { +- DWC_ERROR("Device Not Supported\n"); ++ DWC_WARN("Overcurrent change detected\n"); + port_status |= (1 << UHF_C_PORT_OVER_CURRENT); + } + +@@ -2382,7 +2279,7 @@ + break; + } + +- hprt0.d32 = dwc_read_reg32(core_if->host_if->hprt0); ++ hprt0.d32 = DWC_READ_REG32(core_if->host_if->hprt0); + DWC_DEBUGPL(DBG_HCDV, " HPRT0: 0x%08x\n", hprt0.d32); + + if (hprt0.b.prtconnsts) +@@ -2413,7 +2310,16 @@ + if (dwc_otg_get_lpm_portsleepstatus(dwc_otg_hcd->core_if)) { + port_status |= (1 << UHF_PORT_L1); + } +- ++ /* ++ For Synopsys HW emulation of Power down wkup_control asserts the ++ hreset_n and prst_n on suspned. This causes the HPRT0 to be zero. ++ We intentionally tell the software that port is in L2Suspend state. ++ Only for STE. ++ */ ++ if ((core_if->power_down == 2) ++ && (core_if->hibernation_suspend == 1)) { ++ port_status |= (1 << UHF_PORT_SUSPEND); ++ } + /* USB_PORT_FEAT_INDICATOR unsupported always 0 */ + + *((__le32 *) buf) = dwc_cpu_to_le32(&port_status); +@@ -2443,19 +2349,149 @@ + case UHF_PORT_SUSPEND: + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - " + "SetPortFeature - USB_PORT_FEAT_SUSPEND\n"); ++ if (dwc_otg_hcd_otg_port(dwc_otg_hcd) != wIndex) { ++ goto error; ++ } ++ if (core_if->power_down == 2) { ++ int timeout = 300; ++ dwc_irqflags_t flags; ++ pcgcctl_data_t pcgcctl = {.d32 = 0 }; ++ gpwrdn_data_t gpwrdn = {.d32 = 0 }; ++ gusbcfg_data_t gusbcfg = {.d32 = 0 }; ++#ifdef DWC_DEV_SRPCAP ++ int32_t otg_cap_param = core_if->core_params->otg_cap; ++#endif ++ DWC_PRINTF("Preparing for complete power-off\n"); ++ ++ /* Save registers before hibernation */ ++ dwc_otg_save_global_regs(core_if); ++ dwc_otg_save_host_regs(core_if); ++ ++ hprt0.d32 = dwc_otg_read_hprt0(core_if); ++ hprt0.b.prtsusp = 1; ++ hprt0.b.prtena = 0; ++ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32); ++ /* Spin hprt0.b.prtsusp to became 1 */ ++ do { ++ hprt0.d32 = dwc_otg_read_hprt0(core_if); ++ if (hprt0.b.prtsusp) { ++ break; ++ } ++ dwc_mdelay(1); ++ } while (--timeout); ++ if (!timeout) { ++ DWC_WARN("Suspend wasn't genereted\n"); ++ } ++ dwc_udelay(10); ++ ++ /* ++ * We need to disable interrupts to prevent servicing of any IRQ ++ * during going to hibernation ++ */ ++ DWC_SPINLOCK_IRQSAVE(dwc_otg_hcd->lock, &flags); ++ core_if->lx_state = DWC_OTG_L2; ++#ifdef DWC_DEV_SRPCAP ++ hprt0.d32 = dwc_otg_read_hprt0(core_if); ++ hprt0.b.prtpwr = 0; ++ hprt0.b.prtena = 0; ++ DWC_WRITE_REG32(core_if->host_if->hprt0, ++ hprt0.d32); ++#endif ++ gusbcfg.d32 = ++ DWC_READ_REG32(&core_if->core_global_regs-> ++ gusbcfg); ++ if (gusbcfg.b.ulpi_utmi_sel == 1) { ++ /* ULPI interface */ ++ /* Suspend the Phy Clock */ ++ pcgcctl.d32 = 0; ++ pcgcctl.b.stoppclk = 1; ++ DWC_MODIFY_REG32(core_if->pcgcctl, 0, ++ pcgcctl.d32); ++ dwc_udelay(10); ++ gpwrdn.b.pmuactv = 1; ++ DWC_MODIFY_REG32(&core_if-> ++ core_global_regs-> ++ gpwrdn, 0, gpwrdn.d32); ++ } else { ++ /* UTMI+ Interface */ ++ gpwrdn.b.pmuactv = 1; ++ DWC_MODIFY_REG32(&core_if-> ++ core_global_regs-> ++ gpwrdn, 0, gpwrdn.d32); ++ dwc_udelay(10); ++ pcgcctl.b.stoppclk = 1; ++ DWC_MODIFY_REG32(core_if->pcgcctl, 0, pcgcctl.d32); ++ dwc_udelay(10); ++ } ++#ifdef DWC_DEV_SRPCAP ++ gpwrdn.d32 = 0; ++ gpwrdn.b.dis_vbus = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs-> ++ gpwrdn, 0, gpwrdn.d32); ++#endif ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pmuintsel = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs-> ++ gpwrdn, 0, gpwrdn.d32); ++ dwc_udelay(10); ++ ++ gpwrdn.d32 = 0; ++#ifdef DWC_DEV_SRPCAP ++ gpwrdn.b.srp_det_msk = 1; ++#endif ++ gpwrdn.b.disconn_det_msk = 1; ++ gpwrdn.b.lnstchng_msk = 1; ++ gpwrdn.b.sts_chngint_msk = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs-> ++ gpwrdn, 0, gpwrdn.d32); ++ dwc_udelay(10); ++ ++ /* Enable Power Down Clamp and all interrupts in GPWRDN */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pwrdnclmp = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs-> ++ gpwrdn, 0, gpwrdn.d32); ++ dwc_udelay(10); ++ ++ /* Switch off VDD */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pwrdnswtch = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs-> ++ gpwrdn, 0, gpwrdn.d32); ++ ++#ifdef DWC_DEV_SRPCAP ++ if (otg_cap_param == DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE) ++ { ++ core_if->pwron_timer_started = 1; ++ DWC_TIMER_SCHEDULE(core_if->pwron_timer, 6000 /* 6 secs */ ); ++ } ++#endif ++ /* Save gpwrdn register for further usage if stschng interrupt */ ++ core_if->gr_backup->gpwrdn_local = ++ DWC_READ_REG32(&core_if->core_global_regs->gpwrdn); ++ ++ /* Set flag to indicate that we are in hibernation */ ++ core_if->hibernation_suspend = 1; ++ DWC_SPINUNLOCK_IRQRESTORE(dwc_otg_hcd->lock,flags); ++ ++ DWC_PRINTF("Host hibernation completed\n"); ++ // Exit from case statement ++ break; ++ ++ } + if (dwc_otg_hcd_otg_port(dwc_otg_hcd) == wIndex && + dwc_otg_hcd->fops->get_b_hnp_enable(dwc_otg_hcd)) { + gotgctl_data_t gotgctl = {.d32 = 0 }; + gotgctl.b.hstsethnpen = 1; +- dwc_modify_reg32(&core_if->core_global_regs-> ++ DWC_MODIFY_REG32(&core_if->core_global_regs-> + gotgctl, 0, gotgctl.d32); + core_if->op_state = A_SUSPEND; + } + hprt0.d32 = dwc_otg_read_hprt0(core_if); + hprt0.b.prtsusp = 1; +- dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32); ++ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32); + { +- uint64_t flags; ++ dwc_irqflags_t flags; + /* Update lx_state */ + DWC_SPINLOCK_IRQSAVE(dwc_otg_hcd->lock, &flags); + core_if->lx_state = DWC_OTG_L2; +@@ -2465,64 +2501,111 @@ + { + pcgcctl_data_t pcgcctl = {.d32 = 0 }; + pcgcctl.b.stoppclk = 1; +- dwc_modify_reg32(core_if->pcgcctl, 0, ++ DWC_MODIFY_REG32(core_if->pcgcctl, 0, + pcgcctl.d32); ++ dwc_udelay(10); + } + + /* For HNP the bus must be suspended for at least 200ms. */ + if (dwc_otg_hcd->fops->get_b_hnp_enable(dwc_otg_hcd)) { ++ pcgcctl_data_t pcgcctl = {.d32 = 0 }; ++ pcgcctl.b.stoppclk = 1; ++ DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32, 0); + dwc_mdelay(200); + } ++ ++ /** @todo - check how sw can wait for 1 sec to check asesvld??? */ ++#if 0 //vahrama !!!!!!!!!!!!!!!!!! ++ if (core_if->adp_enable) { ++ gotgctl_data_t gotgctl = {.d32 = 0 }; ++ gpwrdn_data_t gpwrdn; ++ ++ while (gotgctl.b.asesvld == 1) { ++ gotgctl.d32 = ++ DWC_READ_REG32(&core_if-> ++ core_global_regs-> ++ gotgctl); ++ dwc_mdelay(100); ++ } ++ ++ /* Enable Power Down Logic */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pmuactv = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs-> ++ gpwrdn, 0, gpwrdn.d32); ++ ++ /* Unmask SRP detected interrupt from Power Down Logic */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.srp_det_msk = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs-> ++ gpwrdn, 0, gpwrdn.d32); ++ ++ dwc_otg_adp_probe_start(core_if); ++ } ++#endif + break; + case UHF_PORT_POWER: + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - " + "SetPortFeature - USB_PORT_FEAT_POWER\n"); + hprt0.d32 = dwc_otg_read_hprt0(core_if); + hprt0.b.prtpwr = 1; +- dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32); ++ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32); + break; + case UHF_PORT_RESET: +- DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - " +- "SetPortFeature - USB_PORT_FEAT_RESET\n"); +- { +- pcgcctl_data_t pcgcctl = {.d32 = 0 }; +- pcgcctl.b.enbl_sleep_gating = 1; +- pcgcctl.b.stoppclk = 1; +- dwc_modify_reg32(core_if->pcgcctl, pcgcctl.d32, +- 0); +- dwc_write_reg32(core_if->pcgcctl, 0); +- } ++ if ((core_if->power_down == 2) ++ && (core_if->hibernation_suspend == 1)) { ++ /* If we are going to exit from Hibernated ++ * state via USB RESET. ++ */ ++ dwc_otg_host_hibernation_restore(core_if, 0, 1); ++ } else { ++ hprt0.d32 = dwc_otg_read_hprt0(core_if); ++ ++ DWC_DEBUGPL(DBG_HCD, ++ "DWC OTG HCD HUB CONTROL - " ++ "SetPortFeature - USB_PORT_FEAT_RESET\n"); ++ { ++ pcgcctl_data_t pcgcctl = {.d32 = 0 }; ++ pcgcctl.b.enbl_sleep_gating = 1; ++ pcgcctl.b.stoppclk = 1; ++ DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32, 0); ++ DWC_WRITE_REG32(core_if->pcgcctl, 0); ++ } + #ifdef CONFIG_USB_DWC_OTG_LPM +- { +- glpmcfg_data_t lpmcfg; +- lpmcfg.d32 = +- dwc_read_reg32(&core_if->core_global_regs-> +- glpmcfg); +- if (lpmcfg.b.prt_sleep_sts) { +- lpmcfg.b.en_utmi_sleep = 0; +- lpmcfg.b.hird_thres &= (~(1 << 4)); +- dwc_write_reg32(&core_if-> +- core_global_regs-> +- glpmcfg, lpmcfg.d32); +- dwc_mdelay(1); ++ { ++ glpmcfg_data_t lpmcfg; ++ lpmcfg.d32 = ++ DWC_READ_REG32(&core_if->core_global_regs->glpmcfg); ++ if (lpmcfg.b.prt_sleep_sts) { ++ lpmcfg.b.en_utmi_sleep = 0; ++ lpmcfg.b.hird_thres &= (~(1 << 4)); ++ DWC_WRITE_REG32 ++ (&core_if->core_global_regs->glpmcfg, ++ lpmcfg.d32); ++ dwc_mdelay(1); ++ } + } +- } + #endif +- hprt0.d32 = dwc_otg_read_hprt0(core_if); +- /* When B-Host the Port reset bit is set in +- * the Start HCD Callback function, so that +- * the reset is started within 1ms of the HNP +- * success interrupt. */ +- if (!dwc_otg_hcd_is_b_host(dwc_otg_hcd)) { +- hprt0.b.prtrst = 1; +- dwc_write_reg32(core_if->host_if->hprt0, +- hprt0.d32); ++ hprt0.d32 = dwc_otg_read_hprt0(core_if); ++ /* Clear suspend bit if resetting from suspended state. */ ++ hprt0.b.prtsusp = 0; ++ /* When B-Host the Port reset bit is set in ++ * the Start HCD Callback function, so that ++ * the reset is started within 1ms of the HNP ++ * success interrupt. */ ++ if (!dwc_otg_hcd_is_b_host(dwc_otg_hcd)) { ++ hprt0.b.prtpwr = 1; ++ hprt0.b.prtrst = 1; ++ DWC_PRINTF("Indeed it is in host mode hprt0 = %08x\n",hprt0.d32); ++ DWC_WRITE_REG32(core_if->host_if->hprt0, ++ hprt0.d32); ++ } ++ /* Clear reset bit in 10ms (FS/LS) or 50ms (HS) */ ++ dwc_mdelay(60); ++ hprt0.b.prtrst = 0; ++ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32); ++ core_if->lx_state = DWC_OTG_L0; /* Now back to the on state */ + } +- /* Clear reset bit in 10ms (FS/LS) or 50ms (HS) */ +- dwc_mdelay(60); +- hprt0.b.prtrst = 0; +- dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32); +- core_if->lx_state = DWC_OTG_L0; /* Now back to the on state */ + break; + #ifdef DWC_HS_ELECT_TST + case UHF_PORT_TEST: +@@ -2539,7 +2622,7 @@ + if (t < 6) { + hprt0.d32 = dwc_otg_read_hprt0(core_if); + hprt0.b.prttstctl = t; +- dwc_write_reg32(core_if->host_if->hprt0, ++ DWC_WRITE_REG32(core_if->host_if->hprt0, + hprt0.d32); + } else { + /* Setup global vars with reg addresses (quick and +@@ -2559,14 +2642,13 @@ + if (t == 6) { /* HS_HOST_PORT_SUSPEND_RESUME */ + /* Save current interrupt mask */ + gintmsk.d32 = +- dwc_read_reg32 ++ DWC_READ_REG32 + (&global_regs->gintmsk); + + /* Disable all interrupts while we muck with + * the hardware directly + */ +- dwc_write_reg32(&global_regs-> +- gintmsk, 0); ++ DWC_WRITE_REG32(&global_regs->gintmsk, 0); + + /* 15 second delay per the test spec */ + dwc_mdelay(15000); +@@ -2576,9 +2658,7 @@ + dwc_otg_read_hprt0(core_if); + hprt0.b.prtsusp = 1; + hprt0.b.prtres = 0; +- dwc_write_reg32(core_if-> +- host_if->hprt0, +- hprt0.d32); ++ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32); + + /* 15 second delay per the test spec */ + dwc_mdelay(15000); +@@ -2588,32 +2668,25 @@ + dwc_otg_read_hprt0(core_if); + hprt0.b.prtsusp = 0; + hprt0.b.prtres = 1; +- dwc_write_reg32(core_if-> +- host_if->hprt0, +- hprt0.d32); ++ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32); + dwc_mdelay(100); + + /* Clear the resume bit */ + hprt0.b.prtres = 0; +- dwc_write_reg32(core_if-> +- host_if->hprt0, +- hprt0.d32); ++ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32); + + /* Restore interrupts */ +- dwc_write_reg32(&global_regs-> +- gintmsk, +- gintmsk.d32); ++ DWC_WRITE_REG32(&global_regs->gintmsk, gintmsk.d32); + } else if (t == 7) { /* SINGLE_STEP_GET_DEVICE_DESCRIPTOR setup */ + /* Save current interrupt mask */ + gintmsk.d32 = +- dwc_read_reg32 ++ DWC_READ_REG32 + (&global_regs->gintmsk); + + /* Disable all interrupts while we muck with + * the hardware directly + */ +- dwc_write_reg32(&global_regs-> +- gintmsk, 0); ++ DWC_WRITE_REG32(&global_regs->gintmsk, 0); + + /* 15 second delay per the test spec */ + dwc_mdelay(15000); +@@ -2625,20 +2698,17 @@ + dwc_mdelay(15000); + + /* Restore interrupts */ +- dwc_write_reg32(&global_regs-> +- gintmsk, +- gintmsk.d32); ++ DWC_WRITE_REG32(&global_regs->gintmsk, gintmsk.d32); + } else if (t == 8) { /* SINGLE_STEP_GET_DEVICE_DESCRIPTOR execute */ + /* Save current interrupt mask */ + gintmsk.d32 = +- dwc_read_reg32 ++ DWC_READ_REG32 + (&global_regs->gintmsk); + + /* Disable all interrupts while we muck with + * the hardware directly + */ +- dwc_write_reg32(&global_regs-> +- gintmsk, 0); ++ DWC_WRITE_REG32(&global_regs->gintmsk, 0); + + /* Send the Setup packet */ + do_setup(); +@@ -2653,14 +2723,12 @@ + dwc_mdelay(15000); + + /* Restore interrupts */ +- dwc_write_reg32(&global_regs-> +- gintmsk, +- gintmsk.d32); ++ DWC_WRITE_REG32(&global_regs->gintmsk, gintmsk.d32); + } + } + break; + } +-#endif /* DWC_HS_ELECT_TST */ ++#endif /* DWC_HS_ELECT_TST */ + + case UHF_PORT_INDICATOR: + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - " +@@ -2695,7 +2763,7 @@ + } + /* Check if the port currently is in SLEEP state */ + lpmcfg.d32 = +- dwc_read_reg32(&core_if->core_global_regs->glpmcfg); ++ DWC_READ_REG32(&core_if->core_global_regs->glpmcfg); + if (lpmcfg.b.prt_sleep_sts) { + DWC_INFO("Port is already in sleep mode\n"); + buf[0] = 0; /* Return success */ +@@ -2721,7 +2789,7 @@ + /* Disable LPM interrupt */ + gintmsk.d32 = 0; + gintmsk.b.lpmtranrcvd = 1; +- dwc_modify_reg32(&core_if->core_global_regs->gintmsk, ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, + gintmsk.d32, 0); + + if (dwc_otg_hcd_send_lpm +@@ -2738,8 +2806,7 @@ + */ + do { + gintsts.d32 = +- dwc_read_reg32(&core_if->core_global_regs-> +- gintsts); ++ DWC_READ_REG32(&core_if->core_global_regs->gintsts); + if (gintsts.b.lpmtranrcvd) { + break; + } +@@ -2757,8 +2824,7 @@ + dwc_otg_hcd_free_hc_from_lpm(dwc_otg_hcd); + } else { + lpmcfg.d32 = +- dwc_read_reg32(&core_if->core_global_regs-> +- glpmcfg); ++ DWC_READ_REG32(&core_if->core_global_regs->glpmcfg); + if (lpmcfg.b.lpm_resp == 0x3) { + /* ACK responce from the device */ + buf[0] = 0x00; /* Success */ +@@ -2772,14 +2838,14 @@ + } + DWC_PRINTF("Device responce to LPM trans is %x\n", + lpmcfg.b.lpm_resp); +- dwc_modify_reg32(&core_if->core_global_regs->gintmsk, 0, ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, 0, + gintmsk.d32); + + break; + } +-#endif /* CONFIG_USB_DWC_OTG_LPM */ ++#endif /* CONFIG_USB_DWC_OTG_LPM */ + default: +- error: ++error: + retval = -DWC_E_INVALID; + DWC_WARN("DWC OTG HCD - " + "Unknown hub control request type or invalid typeReq: %xh wIndex: %xh wValue: %xh\n", +@@ -2808,7 +2874,7 @@ + + /* Mask host channel interrupts. */ + gintmsk.b.hcintr = 1; +- dwc_modify_reg32(&core_if->core_global_regs->gintmsk, gintmsk.d32, 0); ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, gintmsk.d32, 0); + + /* Fill fields that core needs for LPM transaction */ + hcchar.b.devaddr = devaddr; +@@ -2817,7 +2883,7 @@ + hcchar.b.mps = 64; + hcchar.b.lspddev = (hc->speed == DWC_OTG_EP_SPEED_LOW); + hcchar.b.epdir = 0; /* OUT */ +- dwc_write_reg32(&core_if->host_if->hc_regs[hc->hc_num]->hcchar, ++ DWC_WRITE_REG32(&core_if->host_if->hc_regs[hc->hc_num]->hcchar, + hcchar.d32); + + /* Remove the host channel from the free list. */ +@@ -2835,7 +2901,7 @@ + glpmcfg_data_t lpmcfg; + uint8_t hc_num; + +- lpmcfg.d32 = dwc_read_reg32(&hcd->core_if->core_global_regs->glpmcfg); ++ lpmcfg.d32 = DWC_READ_REG32(&hcd->core_if->core_global_regs->glpmcfg); + hc_num = lpmcfg.b.lpm_chan_index; + + hc = hcd->hc_ptr_array[hc_num]; +@@ -2858,10 +2924,10 @@ + } + + pcgcctl.b.enbl_sleep_gating = 1; +- dwc_modify_reg32(hcd->core_if->pcgcctl, 0, pcgcctl.d32); ++ DWC_MODIFY_REG32(hcd->core_if->pcgcctl, 0, pcgcctl.d32); + + /* Read LPM config register */ +- lpmcfg.d32 = dwc_read_reg32(&hcd->core_if->core_global_regs->glpmcfg); ++ lpmcfg.d32 = DWC_READ_REG32(&hcd->core_if->core_global_regs->glpmcfg); + + /* Program LPM transaction fields */ + lpmcfg.b.rem_wkup_en = bRemoteWake; +@@ -2870,16 +2936,16 @@ + lpmcfg.b.lpm_chan_index = channel; + lpmcfg.b.en_utmi_sleep = 1; + /* Program LPM config register */ +- dwc_write_reg32(&hcd->core_if->core_global_regs->glpmcfg, lpmcfg.d32); ++ DWC_WRITE_REG32(&hcd->core_if->core_global_regs->glpmcfg, lpmcfg.d32); + + /* Send LPM transaction */ + lpmcfg.b.send_lpm = 1; +- dwc_write_reg32(&hcd->core_if->core_global_regs->glpmcfg, lpmcfg.d32); ++ DWC_WRITE_REG32(&hcd->core_if->core_global_regs->glpmcfg, lpmcfg.d32); + + return 0; + } + +-#endif /* CONFIG_USB_DWC_OTG_LPM */ ++#endif /* CONFIG_USB_DWC_OTG_LPM */ + + int dwc_otg_hcd_is_status_changed(dwc_otg_hcd_t * hcd, int port) + { +@@ -2916,8 +2982,9 @@ + int dwc_otg_hcd_get_frame_number(dwc_otg_hcd_t * dwc_otg_hcd) + { + hfnum_data_t hfnum; +- hfnum.d32 = dwc_read_reg32(&dwc_otg_hcd->core_if-> +- host_if->host_global_regs->hfnum); ++ hfnum.d32 = ++ DWC_READ_REG32(&dwc_otg_hcd->core_if->host_if->host_global_regs-> ++ hfnum); + + #ifdef DEBUG_SOF + DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD GET FRAME NUMBER %d\n", +@@ -2932,7 +2999,8 @@ + int retval = 0; + + hcd->fops = fops; +- if (!dwc_otg_is_device_mode(hcd->core_if)) { ++ if (!dwc_otg_is_device_mode(hcd->core_if) && ++ (!hcd->core_if->adp_enable || hcd->core_if->adp.adp_started)) { + dwc_otg_hcd_reinit(hcd); + } else { + retval = -DWC_E_NO_DEVICE; +@@ -2977,12 +3045,21 @@ + size = + sizeof(*dwc_otg_urb) + + iso_desc_count * sizeof(struct dwc_otg_hcd_iso_packet_desc); +- if (atomic_alloc) { +- dwc_otg_urb = dwc_alloc_atomic(size); +- } else { +- dwc_otg_urb = dwc_alloc(size); +- } +- dwc_otg_urb->packet_count = iso_desc_count; ++ if (atomic_alloc) ++ dwc_otg_urb = DWC_ALLOC_ATOMIC(size); ++ else ++ dwc_otg_urb = DWC_ALLOC(size); ++ ++ if (NULL != dwc_otg_urb) ++ dwc_otg_urb->packet_count = iso_desc_count; ++ else { ++ dwc_otg_urb->packet_count = 0; ++ if (size != 0) { ++ DWC_ERROR("**** DWC OTG HCD URB alloc - " ++ "%salloc of %db failed\n", ++ atomic_alloc?"atomic ":"", size); ++ } ++ } + + return dwc_otg_urb; + } +@@ -3130,20 +3207,20 @@ + hcint_data_t hcint; + hcintmsk_data_t hcintmsk; + hfnum.d32 = +- dwc_read_reg32(&hcd->core_if->host_if-> +- host_global_regs->hfnum); ++ DWC_READ_REG32(&hcd->core_if-> ++ host_if->host_global_regs->hfnum); + hcchar.d32 = +- dwc_read_reg32(&hcd->core_if->host_if->hc_regs[i]-> +- hcchar); ++ DWC_READ_REG32(&hcd->core_if->host_if-> ++ hc_regs[i]->hcchar); + hctsiz.d32 = +- dwc_read_reg32(&hcd->core_if->host_if->hc_regs[i]-> +- hctsiz); ++ DWC_READ_REG32(&hcd->core_if->host_if-> ++ hc_regs[i]->hctsiz); + hcint.d32 = +- dwc_read_reg32(&hcd->core_if->host_if->hc_regs[i]-> +- hcint); ++ DWC_READ_REG32(&hcd->core_if->host_if-> ++ hc_regs[i]->hcint); + hcintmsk.d32 = +- dwc_read_reg32(&hcd->core_if->host_if->hc_regs[i]-> +- hcintmsk); ++ DWC_READ_REG32(&hcd->core_if->host_if-> ++ hc_regs[i]->hcintmsk); + DWC_PRINTF(" hfnum: 0x%08x\n", hfnum.d32); + DWC_PRINTF(" hcchar: 0x%08x\n", hcchar.d32); + DWC_PRINTF(" hctsiz: 0x%08x\n", hctsiz.d32); +@@ -3155,7 +3232,7 @@ + dwc_otg_hcd_urb_t *urb; + + DWC_CIRCLEQ_FOREACH(qtd, &hc->qh->qtd_list, qtd_list_entry) { +- if(!qtd->in_process) ++ if (!qtd->in_process) + break; + + urb = qtd->urb; +@@ -3179,23 +3256,23 @@ + (void *)urb->dma); + DWC_PRINTF(" transfer_buffer_length: %d\n", + urb->length); +- DWC_PRINTF(" actual_length: %d\n", +- urb->actual_length); ++ DWC_PRINTF(" actual_length: %d\n", ++ urb->actual_length); ++ } + } + } + } +- } + DWC_PRINTF(" non_periodic_channels: %d\n", hcd->non_periodic_channels); + DWC_PRINTF(" periodic_channels: %d\n", hcd->periodic_channels); + DWC_PRINTF(" periodic_usecs: %d\n", hcd->periodic_usecs); + np_tx_status.d32 = +- dwc_read_reg32(&hcd->core_if->core_global_regs->gnptxsts); ++ DWC_READ_REG32(&hcd->core_if->core_global_regs->gnptxsts); + DWC_PRINTF(" NP Tx Req Queue Space Avail: %d\n", + np_tx_status.b.nptxqspcavail); + DWC_PRINTF(" NP Tx FIFO Space Avail: %d\n", + np_tx_status.b.nptxfspcavail); + p_tx_status.d32 = +- dwc_read_reg32(&hcd->core_if->host_if->host_global_regs->hptxsts); ++ DWC_READ_REG32(&hcd->core_if->host_if->host_global_regs->hptxsts); + DWC_PRINTF(" P Tx Req Queue Space Avail: %d\n", + p_tx_status.b.ptxqspcavail); + DWC_PRINTF(" P Tx FIFO Space Avail: %d\n", p_tx_status.b.ptxfspcavail); +@@ -3331,4 +3408,4 @@ + #endif + } + +-#endif /* DWC_DEVICE_ONLY */ ++#endif /* DWC_DEVICE_ONLY */ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_hcd.h +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/dwc_otg_hcd.h 2013-07-26 19:34:36.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_hcd.h 2013-07-26 19:34:44.000000000 +0000 +@@ -1,8 +1,8 @@ + /* ========================================================================== + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd.h $ +- * $Revision: #52 $ +- * $Date: 2009/04/21 $ +- * $Change: 1237472 $ ++ * $Revision: #58 $ ++ * $Date: 2011/09/15 $ ++ * $Change: 1846647 $ + * + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless +@@ -34,7 +34,8 @@ + #ifndef __DWC_HCD_H__ + #define __DWC_HCD_H__ + +-#include ++#include "dwc_otg_os_dep.h" ++#include "usb.h" + #include "dwc_otg_hcd_if.h" + #include "dwc_otg_core_if.h" + #include "dwc_list.h" +@@ -238,17 +239,17 @@ + DWC_CIRCLEQ_ENTRY(dwc_otg_qtd) qtd_list_entry; + + /** Indicates if this QTD is currently processed by HW. */ +- uint8_t in_process; ++ uint8_t in_process; + + /** Number of DMA descriptors for this QTD */ +- uint8_t n_desc; +- ++ uint8_t n_desc; ++ + /** + * Last activated frame(packet) index. + * Used in Descriptor DMA mode only. + */ + uint16_t isoc_frame_index_last; +- ++ + } dwc_otg_qtd_t; + + DWC_CIRCLEQ_HEAD(dwc_otg_qtd_list, dwc_otg_qtd); +@@ -331,36 +332,36 @@ + */ + uint8_t *dw_align_buf; + dwc_dma_t dw_align_buf_dma; +- ++ + /** Entry for QH in either the periodic or non-periodic schedule. */ + dwc_list_link_t qh_list_entry; +- ++ + /** @name Descriptor DMA support */ + /** @{ */ +- ++ + /** Descriptor List. */ +- dwc_otg_host_dma_desc_t *desc_list; +- ++ dwc_otg_host_dma_desc_t *desc_list; ++ + /** Descriptor List physical address. */ + dwc_dma_t desc_list_dma; +- ++ + /** + * Xfer Bytes array. + * Each element corresponds to a descriptor and indicates + * original XferSize size value for the descriptor. + */ + uint32_t *n_bytes; +- ++ + /** Actual number of transfer descriptors in a list. */ + uint16_t ntd; +- ++ + /** First activated isochronous transfer descriptor index. */ + uint8_t td_first; + /** Last activated isochronous transfer descriptor index. */ + uint8_t td_last; +- ++ + /** @} */ +- ++ + } dwc_otg_qh_t; + + DWC_CIRCLEQ_HEAD(hc_list, dwc_hc); +@@ -380,6 +381,8 @@ + * periodic schedules. + */ + struct dwc_otg_hcd { ++ /** The DWC otg device pointer */ ++ struct dwc_otg_device *otg_dev; + /** DWC OTG Core Interface Layer */ + dwc_otg_core_if_t *core_if; + +@@ -480,6 +483,11 @@ + uint16_t frame_number; + + /** ++ * Count of periodic QHs, if using several eps. For SOF enable/disable. ++ */ ++ uint16_t periodic_qh_count; ++ ++ /** + * Free host channels in the controller. This is a list of + * dwc_hc_t items. + */ +@@ -576,7 +584,7 @@ + extern dwc_otg_transaction_type_e dwc_otg_hcd_select_transactions(dwc_otg_hcd_t + * hcd); + extern void dwc_otg_hcd_queue_transactions(dwc_otg_hcd_t * hcd, +- dwc_otg_transaction_type_e tr_type); ++ dwc_otg_transaction_type_e tr_type); + + /** @} */ + +@@ -609,7 +617,7 @@ + + /* Implemented in dwc_otg_hcd_queue.c */ + extern dwc_otg_qh_t *dwc_otg_hcd_qh_create(dwc_otg_hcd_t * hcd, +- dwc_otg_hcd_urb_t * urb); ++ dwc_otg_hcd_urb_t * urb, int atomic_alloc); + extern void dwc_otg_hcd_qh_free(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh); + extern int dwc_otg_hcd_qh_add(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh); + extern void dwc_otg_hcd_qh_remove(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh); +@@ -620,27 +628,37 @@ + static inline void dwc_otg_hcd_qh_remove_and_free(dwc_otg_hcd_t * hcd, + dwc_otg_qh_t * qh) + { ++ dwc_irqflags_t flags; ++ DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags); + dwc_otg_hcd_qh_remove(hcd, qh); ++ DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags); + dwc_otg_hcd_qh_free(hcd, qh); + } + + /** Allocates memory for a QH structure. + * @return Returns the memory allocate or NULL on error. */ +-static inline dwc_otg_qh_t *dwc_otg_hcd_qh_alloc(void) ++static inline dwc_otg_qh_t *dwc_otg_hcd_qh_alloc(int atomic_alloc) + { +- return (dwc_otg_qh_t *) dwc_alloc_atomic(sizeof(dwc_otg_qh_t)); ++ if (atomic_alloc) ++ return (dwc_otg_qh_t *) DWC_ALLOC_ATOMIC(sizeof(dwc_otg_qh_t)); ++ else ++ return (dwc_otg_qh_t *) DWC_ALLOC(sizeof(dwc_otg_qh_t)); + } + +-extern dwc_otg_qtd_t *dwc_otg_hcd_qtd_create(dwc_otg_hcd_urb_t * urb); ++extern dwc_otg_qtd_t *dwc_otg_hcd_qtd_create(dwc_otg_hcd_urb_t * urb, ++ int atomic_alloc); + extern void dwc_otg_hcd_qtd_init(dwc_otg_qtd_t * qtd, dwc_otg_hcd_urb_t * urb); + extern int dwc_otg_hcd_qtd_add(dwc_otg_qtd_t * qtd, dwc_otg_hcd_t * dwc_otg_hcd, +- dwc_otg_qh_t ** qh); ++ dwc_otg_qh_t ** qh, int atomic_alloc); + + /** Allocates memory for a QTD structure. + * @return Returns the memory allocate or NULL on error. */ +-static inline dwc_otg_qtd_t *dwc_otg_hcd_qtd_alloc(void) ++static inline dwc_otg_qtd_t *dwc_otg_hcd_qtd_alloc(int atomic_alloc) + { +- return (dwc_otg_qtd_t *) dwc_alloc_atomic(sizeof(dwc_otg_qtd_t)); ++ if (atomic_alloc) ++ return (dwc_otg_qtd_t *) DWC_ALLOC_ATOMIC(sizeof(dwc_otg_qtd_t)); ++ else ++ return (dwc_otg_qtd_t *) DWC_ALLOC(sizeof(dwc_otg_qtd_t)); + } + + /** Frees the memory for a QTD structure. QTD should already be removed from +@@ -648,7 +666,7 @@ + * @param qtd QTD to free.*/ + static inline void dwc_otg_hcd_qtd_free(dwc_otg_qtd_t * qtd) + { +- dwc_free(qtd); ++ DWC_FREE(qtd); + } + + /** Removes a QTD from list. +@@ -660,13 +678,12 @@ + dwc_otg_qtd_t * qtd, + dwc_otg_qh_t * qh) + { +- uint64_t flags; +- DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags); + DWC_CIRCLEQ_REMOVE(&qh->qtd_list, qtd, qtd_list_entry); +- DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags); + } + +-/** Remove and free a QTD */ ++/** Remove and free a QTD ++ * Need to disable IRQ and hold hcd lock while calling this function out of ++ * interrupt servicing chain */ + static inline void dwc_otg_hcd_qtd_remove_and_free(dwc_otg_hcd_t * hcd, + dwc_otg_qtd_t * qtd, + dwc_otg_qh_t * qh) +@@ -682,15 +699,15 @@ + + extern void dwc_otg_hcd_start_xfer_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh); + extern void dwc_otg_hcd_complete_xfer_ddma(dwc_otg_hcd_t * hcd, +- dwc_hc_t * hc, +- dwc_otg_hc_regs_t * hc_regs, +- dwc_otg_halt_status_e halt_status); ++ dwc_hc_t * hc, ++ dwc_otg_hc_regs_t * hc_regs, ++ dwc_otg_halt_status_e halt_status); + + extern int dwc_otg_hcd_qh_init_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh); + extern void dwc_otg_hcd_qh_free_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh); + + /** @} */ +- ++ + /** @name Internal Functions */ + /** @{ */ + dwc_otg_qh_t *dwc_urb_to_qh(dwc_otg_hcd_urb_t * urb); +@@ -761,8 +778,8 @@ + } + + void dwc_otg_hcd_save_data_toggle(dwc_hc_t * hc, +- dwc_otg_hc_regs_t * hc_regs, +- dwc_otg_qtd_t * qtd); ++ dwc_otg_hc_regs_t * hc_regs, ++ dwc_otg_qtd_t * qtd); + + #ifdef DEBUG + /** +@@ -780,7 +797,7 @@ + dwc_otg_qtd_t *qtd; \ + qtd = list_entry(_qh->qtd_list.next, dwc_otg_qtd_t, qtd_list_entry); \ + if (usb_pipeint(qtd->urb->pipe) && _qh->start_split_frame != 0 && !qtd->complete_split) { \ +- hfnum.d32 = dwc_read_reg32(&_hcd->core_if->host_if->host_global_regs->hfnum); \ ++ hfnum.d32 = DWC_READ_REG32(&_hcd->core_if->host_if->host_global_regs->hfnum); \ + switch (hfnum.b.frnum & 0x7) { \ + case 7: \ + _hcd->hfnum_7_samples_##_letter++; \ +@@ -801,4 +818,4 @@ + #define dwc_sample_frrem(_hcd, _qh, _letter) + #endif + #endif +-#endif /* DWC_DEVICE_ONLY */ ++#endif /* DWC_DEVICE_ONLY */ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_hcd_ddma.c +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/dwc_otg_hcd_ddma.c 2013-07-26 19:33:42.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_hcd_ddma.c 2013-07-26 19:34:44.000000000 +0000 +@@ -1,8 +1,8 @@ + /*========================================================================== + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd_ddma.c $ +- * $Revision: #2 $ +- * $Date: 2009/04/21 $ +- * $Change: 1237473 $ ++ * $Revision: #10 $ ++ * $Date: 2011/10/20 $ ++ * $Change: 1869464 $ + * + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless +@@ -35,11 +35,10 @@ + /** @file + * This file contains Descriptor DMA support implementation for host mode. + */ +- ++ + #include "dwc_otg_hcd.h" + #include "dwc_otg_regs.h" +- +- ++ + static inline uint8_t frame_list_idx(uint16_t frame) + { + return (frame & (MAX_FRLIST_EN_NUM - 1)); +@@ -47,91 +46,93 @@ + + static inline uint16_t desclist_idx_inc(uint16_t idx, uint16_t inc, uint8_t speed) + { +- return (idx + inc) & +- (((speed == DWC_OTG_EP_SPEED_HIGH) ? MAX_DMA_DESC_NUM_HS_ISOC : MAX_DMA_DESC_NUM_GENERIC) - 1); ++ return (idx + inc) & ++ (((speed == ++ DWC_OTG_EP_SPEED_HIGH) ? MAX_DMA_DESC_NUM_HS_ISOC : ++ MAX_DMA_DESC_NUM_GENERIC) - 1); + } + + static inline uint16_t desclist_idx_dec(uint16_t idx, uint16_t inc, uint8_t speed) + { +- return (idx - inc) & +- (((speed == DWC_OTG_EP_SPEED_HIGH) ? MAX_DMA_DESC_NUM_HS_ISOC : MAX_DMA_DESC_NUM_GENERIC) - 1); ++ return (idx - inc) & ++ (((speed == ++ DWC_OTG_EP_SPEED_HIGH) ? MAX_DMA_DESC_NUM_HS_ISOC : ++ MAX_DMA_DESC_NUM_GENERIC) - 1); + } + + static inline uint16_t max_desc_num(dwc_otg_qh_t * qh) + { +- return (((qh->ep_type == UE_ISOCHRONOUS) && (qh->dev_speed == DWC_OTG_EP_SPEED_HIGH)) +- ? +- MAX_DMA_DESC_NUM_HS_ISOC +- : +- MAX_DMA_DESC_NUM_GENERIC); ++ return (((qh->ep_type == UE_ISOCHRONOUS) ++ && (qh->dev_speed == DWC_OTG_EP_SPEED_HIGH)) ++ ? MAX_DMA_DESC_NUM_HS_ISOC : MAX_DMA_DESC_NUM_GENERIC); + } + static inline uint16_t frame_incr_val(dwc_otg_qh_t * qh) + { +- return ((qh->dev_speed == DWC_OTG_EP_SPEED_HIGH) +- ? ((qh->interval + 8 - 1) / 8) +- : +- qh->interval); ++ return ((qh->dev_speed == DWC_OTG_EP_SPEED_HIGH) ++ ? ((qh->interval + 8 - 1) / 8) ++ : qh->interval); + } + + static int desc_list_alloc(dwc_otg_qh_t * qh) + { + int retval = 0; +- +- qh->desc_list = (dwc_otg_host_dma_desc_t *) +- dwc_dma_alloc(sizeof(dwc_otg_host_dma_desc_t) * max_desc_num(qh), +- &qh->desc_list_dma +- ); +- ++ ++ qh->desc_list = (dwc_otg_host_dma_desc_t *) ++ DWC_DMA_ALLOC(sizeof(dwc_otg_host_dma_desc_t) * max_desc_num(qh), ++ &qh->desc_list_dma); ++ + if (!qh->desc_list) { + retval = -DWC_E_NO_MEMORY; + DWC_ERROR("%s: DMA descriptor list allocation failed\n", __func__); + + } +- +- dwc_memset(qh->desc_list, 0x00, sizeof(dwc_otg_host_dma_desc_t) * max_desc_num(qh)); +- + +- qh->n_bytes = (uint32_t *) dwc_alloc(sizeof(uint32_t) * max_desc_num(qh)); +- ++ dwc_memset(qh->desc_list, 0x00, ++ sizeof(dwc_otg_host_dma_desc_t) * max_desc_num(qh)); ++ ++ qh->n_bytes = ++ (uint32_t *) DWC_ALLOC(sizeof(uint32_t) * max_desc_num(qh)); ++ + if (!qh->n_bytes) { + retval = -DWC_E_NO_MEMORY; +- DWC_ERROR("%s: Failed to allocate array for descriptors' size actual values\n", +- __func__); +- +- } ++ DWC_ERROR ++ ("%s: Failed to allocate array for descriptors' size actual values\n", ++ __func__); ++ ++ } + return retval; + + } + + static void desc_list_free(dwc_otg_qh_t * qh) + { +- if(qh->desc_list) { +- dwc_dma_free(max_desc_num(qh), qh->desc_list, qh->desc_list_dma); ++ if (qh->desc_list) { ++ DWC_DMA_FREE(max_desc_num(qh), qh->desc_list, ++ qh->desc_list_dma); + qh->desc_list = NULL; + } +- ++ + if (qh->n_bytes) { +- dwc_free(qh->n_bytes); ++ DWC_FREE(qh->n_bytes); + qh->n_bytes = NULL; + } + } + + static int frame_list_alloc(dwc_otg_hcd_t * hcd) + { +- int retval = 0; ++ int retval = 0; + if (hcd->frame_list) + return 0; +- +- hcd->frame_list = dwc_dma_alloc(4 * MAX_FRLIST_EN_NUM, +- &hcd->frame_list_dma +- ); ++ ++ hcd->frame_list = DWC_DMA_ALLOC(4 * MAX_FRLIST_EN_NUM, ++ &hcd->frame_list_dma); + if (!hcd->frame_list) { + retval = -DWC_E_NO_MEMORY; + DWC_ERROR("%s: Frame List allocation failed\n", __func__); + } +- ++ + dwc_memset(hcd->frame_list, 0x00, 4 * MAX_FRLIST_EN_NUM); +- ++ + return retval; + } + +@@ -140,60 +141,63 @@ + if (!hcd->frame_list) + return; + +- dwc_dma_free(4 * MAX_FRLIST_EN_NUM, hcd->frame_list, hcd->frame_list_dma); ++ DWC_DMA_FREE(4 * MAX_FRLIST_EN_NUM, hcd->frame_list, hcd->frame_list_dma); + hcd->frame_list = NULL; + } + + static void per_sched_enable(dwc_otg_hcd_t * hcd, uint16_t fr_list_en) + { +- ++ + hcfg_data_t hcfg; + +- hcfg.d32 = dwc_read_reg32(&hcd->core_if->host_if->host_global_regs->hcfg); ++ hcfg.d32 = DWC_READ_REG32(&hcd->core_if->host_if->host_global_regs->hcfg); + +- if (hcfg.b.perschedstat) { +- /* already enabled*/ ++ if (hcfg.b.perschedena) { ++ /* already enabled */ + return; + } +- +- dwc_write_reg32(&hcd->core_if->host_if->host_global_regs->hflbaddr, hcd->frame_list_dma); +- +- switch(fr_list_en) { ++ ++ DWC_WRITE_REG32(&hcd->core_if->host_if->host_global_regs->hflbaddr, ++ hcd->frame_list_dma); ++ ++ switch (fr_list_en) { + case 64: +- hcfg.b.frlisten = 3; +- break; ++ hcfg.b.frlisten = 3; ++ break; + case 32: +- hcfg.b.frlisten = 2; +- break; ++ hcfg.b.frlisten = 2; ++ break; + case 16: +- hcfg.b.frlisten = 1; +- case 8: +- hcfg.b.frlisten = 0; +- default: +- break; ++ hcfg.b.frlisten = 1; ++ break; ++ case 8: ++ hcfg.b.frlisten = 0; ++ break; ++ default: ++ break; + } +- ++ + hcfg.b.perschedena = 1; + + DWC_DEBUGPL(DBG_HCD, "Enabling Periodic schedule\n"); +- dwc_write_reg32(&hcd->core_if->host_if->host_global_regs->hcfg, hcfg.d32); ++ DWC_WRITE_REG32(&hcd->core_if->host_if->host_global_regs->hcfg, hcfg.d32); + + } +- ++ + static void per_sched_disable(dwc_otg_hcd_t * hcd) + { + hcfg_data_t hcfg; + +- hcfg.d32 = dwc_read_reg32(&hcd->core_if->host_if->host_global_regs->hcfg); ++ hcfg.d32 = DWC_READ_REG32(&hcd->core_if->host_if->host_global_regs->hcfg); + +- if (!hcfg.b.perschedstat) { +- /* already disabled */ ++ if (!hcfg.b.perschedena) { ++ /* already disabled */ + return; + } + hcfg.b.perschedena = 0; +- ++ + DWC_DEBUGPL(DBG_HCD, "Disabling Periodic schedule\n"); +- dwc_write_reg32(&hcd->core_if->host_if->host_global_regs->hcfg, hcfg.d32); ++ DWC_WRITE_REG32(&hcd->core_if->host_if->host_global_regs->hcfg, hcfg.d32); + } + + /* +@@ -203,10 +207,25 @@ + void update_frame_list(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh, uint8_t enable) + { + uint16_t i, j, inc; +- dwc_hc_t *hc = qh->channel; +- ++ dwc_hc_t *hc = NULL; ++ ++ if (!qh->channel) { ++ DWC_ERROR("qh->channel = %p", qh->channel); ++ return; ++ } ++ ++ if (!hcd) { ++ DWC_ERROR("------hcd = %p", hcd); ++ return; ++ } ++ ++ if (!hcd->frame_list) { ++ DWC_ERROR("-------hcd->frame_list = %p", hcd->frame_list); ++ return; ++ } ++ ++ hc = qh->channel; + inc = frame_incr_val(qh); +- + if (qh->ep_type == UE_ISOCHRONOUS) + i = frame_list_idx(qh->sched_frame); + else +@@ -221,30 +240,30 @@ + j = (j + inc) & (MAX_FRLIST_EN_NUM - 1); + } + while (j != i); +- + if (!enable) + return; +- + hc->schinfo = 0; + if (qh->channel->speed == DWC_OTG_EP_SPEED_HIGH) { + j = 1; +- for (i = 0 ; i < 8 / qh->interval; i++) { ++ /* TODO - check this */ ++ inc = (8 + qh->interval - 1) / qh->interval; ++ for (i = 0; i < inc; i++) { + hc->schinfo |= j; + j = j << qh->interval; + } +- } +- else { ++ } else { + hc->schinfo = 0xff; +- } +-} ++ } ++} ++ + #if 1 + void dump_frame_list(dwc_otg_hcd_t * hcd) + { + int i = 0; +- DWC_PRINTF("--FRAME LIST (hex) --\n"); ++ DWC_PRINTF("--FRAME LIST (hex) --\n"); + for (i = 0; i < MAX_FRLIST_EN_NUM; i++) { +- DWC_PRINTF("%x\t",hcd->frame_list[i]); +- if (!(i % 8) && i) ++ DWC_PRINTF("%x\t", hcd->frame_list[i]); ++ if (!(i % 8) && i) + DWC_PRINTF("\n"); + } + DWC_PRINTF("\n----\n"); +@@ -255,28 +274,27 @@ + static void release_channel_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh) + { + dwc_hc_t *hc = qh->channel; +- if (dwc_qh_is_non_per(qh)) { +- hcd->non_periodic_channels--; +- } +- else { ++ if (dwc_qh_is_non_per(qh)) ++ hcd->non_periodic_channels--; ++ else + update_frame_list(hcd, qh, 0); +- } ++ + /* + * The condition is added to prevent double cleanup try in case of device + * disconnect. See channel cleanup in dwc_otg_hcd_disconnect_cb(). + */ +- if (hc->qh) { ++ if (hc->qh) { + dwc_otg_hc_cleanup(hcd->core_if, hc); + DWC_CIRCLEQ_INSERT_TAIL(&hcd->free_hc_list, hc, hc_list_entry); + hc->qh = NULL; + } +- ++ + qh->channel = NULL; + qh->ntd = 0; +- ++ + if (qh->desc_list) { +- dwc_memset(qh->desc_list, 0x00, +- sizeof(dwc_otg_host_dma_desc_t) * max_desc_num(qh)); ++ dwc_memset(qh->desc_list, 0x00, ++ sizeof(dwc_otg_host_dma_desc_t) * max_desc_num(qh)); + } + } + +@@ -290,29 +308,30 @@ + * @param qh The QH to init. + * + * @return 0 if successful, negative error code otherwise. +- */ ++ */ + int dwc_otg_hcd_qh_init_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh) + { + int retval = 0; +- +- if (qh->do_split) { ++ ++ if (qh->do_split) { + DWC_ERROR("SPLIT Transfers are not supported in Descriptor DMA.\n"); + return -1; + } + + retval = desc_list_alloc(qh); +- +- if ((retval == 0) && (qh->ep_type == UE_ISOCHRONOUS || qh->ep_type == UE_INTERRUPT)) { +- if(!hcd->frame_list) { +- retval = frame_list_alloc(hcd); ++ ++ if ((retval == 0) ++ && (qh->ep_type == UE_ISOCHRONOUS || qh->ep_type == UE_INTERRUPT)) { ++ if (!hcd->frame_list) { ++ retval = frame_list_alloc(hcd); + /* Enable periodic schedule on first periodic QH */ +- if (retval == 0) ++ if (retval == 0) + per_sched_enable(hcd, MAX_FRLIST_EN_NUM); + } + } +- ++ + qh->ntd = 0; +- ++ + return retval; + } + +@@ -338,13 +357,13 @@ + if (qh->channel) + release_channel_ddma(hcd, qh); + +- if ((qh->ep_type == UE_ISOCHRONOUS || qh->ep_type == UE_INTERRUPT) +- && !hcd->periodic_channels && hcd->frame_list) { +- +- per_sched_disable(hcd); +- frame_list_free(hcd); ++ if ((qh->ep_type == UE_ISOCHRONOUS || qh->ep_type == UE_INTERRUPT) ++ && !hcd->periodic_channels && hcd->frame_list) { ++ ++ per_sched_disable(hcd); ++ frame_list_free(hcd); + } +-} ++} + + static uint8_t frame_to_desc_idx(dwc_otg_qh_t * qh, uint16_t frame_idx) + { +@@ -352,19 +371,19 @@ + /* + * Descriptor set(8 descriptors) index + * which is 8-aligned. +- */ ++ */ + return (frame_idx & ((MAX_DMA_DESC_NUM_HS_ISOC / 8) - 1)) * 8; +- } +- else { ++ } else { + return (frame_idx & (MAX_DMA_DESC_NUM_GENERIC - 1)); +- } ++ } + } + + /* + * Determine starting frame for Isochronous transfer. + * Few frames skipped to prevent race condition with HC. + */ +-static uint8_t calc_starting_frame(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh, uint8_t* skip_frames) ++static uint8_t calc_starting_frame(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh, ++ uint8_t * skip_frames) + { + uint16_t frame = 0; + hcd->frame_number = dwc_otg_hcd_get_frame_number(hcd); +@@ -378,11 +397,11 @@ + * Example for FS: + * Current frame is 1, scheduled frame is 3. Since HC always fetches the descriptor + * corresponding to curr_frame+1, the descriptor corresponding to frame 2 +- * will be fetched. If the number of descriptors is max=64 (or greather) the list will +- * be fully programmed with Active descriptors and it is possible case(rare) that the latest +- * descriptor(considering rollback) corresponding to frame 2 will be serviced first. +- * HS case is more probable because, in fact, up to 11 uframes(16 in the code) +- * may be skipped. ++ * will be fetched. If the number of descriptors is max=64 (or greather) the ++ * list will be fully programmed with Active descriptors and it is possible ++ * case(rare) that the latest descriptor(considering rollback) corresponding ++ * to frame 2 will be serviced first. HS case is more probable because, in fact, ++ * up to 11 uframes(16 in the code) may be skipped. + */ + if (qh->dev_speed == DWC_OTG_EP_SPEED_HIGH) { + /* +@@ -393,37 +412,37 @@ + * if the current frame is near to complete the next one + * is skipped as well. + */ +- +- if (dwc_micro_frame_num(hcd->frame_number) >= 5) { ++ ++ if (dwc_micro_frame_num(hcd->frame_number) >= 5) { + *skip_frames = 2 * 8; + frame = dwc_frame_num_inc(hcd->frame_number, *skip_frames); +- } +- else { ++ } else { + *skip_frames = 1 * 8; + frame = dwc_frame_num_inc(hcd->frame_number, *skip_frames); +- } +- +- frame = dwc_full_frame_num(frame); ++ } ++ ++ frame = dwc_full_frame_num(frame); + } else { + /* +- * Two frames are skipped for FS - the current and the next. +- * But for descriptor programming, 1 frame(descriptor) is enough, +- * see example above. +- */ +- *skip_frames = 1; ++ * Two frames are skipped for FS - the current and the next. ++ * But for descriptor programming, 1 frame(descriptor) is enough, ++ * see example above. ++ */ ++ *skip_frames = 1; + frame = dwc_frame_num_inc(hcd->frame_number, 2); + } +- ++ + return frame; + } ++ + /* + * Calculate initial descriptor index for isochronous transfer + * based on scheduled frame. + */ + static uint8_t recalc_initial_desc_idx(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh) + { +- uint16_t frame = 0, fr_idx, fr_idx_tmp; +- uint8_t skip_frames = 0 ; ++ uint16_t frame = 0, fr_idx, fr_idx_tmp; ++ uint8_t skip_frames = 0; + /* + * With current ISOC processing algorithm the channel is being + * released when no more QTDs in the list(qh->ntd == 0). +@@ -437,99 +456,107 @@ + * starting frame and therefore starting desc_index are recalculated. + * In this case channel is released only on ep_disable. + */ +- ++ + /* Calculate starting descriptor index. For INTERRUPT endpoint it is always 0. */ + if (qh->channel) { +- frame = calc_starting_frame(hcd, qh, &skip_frames); ++ frame = calc_starting_frame(hcd, qh, &skip_frames); + /* +- * Calculate initial descriptor index based on FrameList current bitmap +- * and servicing period. +- */ ++ * Calculate initial descriptor index based on FrameList current bitmap ++ * and servicing period. ++ */ + fr_idx_tmp = frame_list_idx(frame); +- fr_idx = (MAX_FRLIST_EN_NUM + frame_list_idx(qh->sched_frame) - fr_idx_tmp) +- % frame_incr_val(qh); ++ fr_idx = ++ (MAX_FRLIST_EN_NUM + frame_list_idx(qh->sched_frame) - ++ fr_idx_tmp) ++ % frame_incr_val(qh); + fr_idx = (fr_idx + fr_idx_tmp) % MAX_FRLIST_EN_NUM; +- } +- else { +- qh->sched_frame = calc_starting_frame(hcd, qh, &skip_frames); ++ } else { ++ qh->sched_frame = calc_starting_frame(hcd, qh, &skip_frames); + fr_idx = frame_list_idx(qh->sched_frame); + } +- +- qh->td_first = qh->td_last = frame_to_desc_idx(qh, fr_idx); +- ++ ++ qh->td_first = qh->td_last = frame_to_desc_idx(qh, fr_idx); ++ + return skip_frames; + } +- ++ + #define ISOC_URB_GIVEBACK_ASAP +- ++ + #define MAX_ISOC_XFER_SIZE_FS 1023 + #define MAX_ISOC_XFER_SIZE_HS 3072 + #define DESCNUM_THRESHOLD 4 + +-static void init_isoc_dma_desc(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh, uint8_t skip_frames) ++static void init_isoc_dma_desc(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh, ++ uint8_t skip_frames) + { + struct dwc_otg_hcd_iso_packet_desc *frame_desc; + dwc_otg_qtd_t *qtd; +- dwc_otg_host_dma_desc_t *dma_desc; ++ dwc_otg_host_dma_desc_t *dma_desc; + uint16_t idx, inc, n_desc, ntd_max, max_xfer_size; +- ++ + idx = qh->td_last; + inc = qh->interval; + n_desc = 0; +- ++ + ntd_max = (max_desc_num(qh) + qh->interval - 1) / qh->interval; + if (skip_frames && !qh->channel) +- ntd_max = ntd_max - skip_frames / qh->interval; +- +- max_xfer_size = (qh->dev_speed == DWC_OTG_EP_SPEED_HIGH) ? MAX_ISOC_XFER_SIZE_HS +- : MAX_ISOC_XFER_SIZE_FS; +- ++ ntd_max = ntd_max - skip_frames / qh->interval; ++ ++ max_xfer_size = ++ (qh->dev_speed == ++ DWC_OTG_EP_SPEED_HIGH) ? MAX_ISOC_XFER_SIZE_HS : ++ MAX_ISOC_XFER_SIZE_FS; ++ + DWC_CIRCLEQ_FOREACH(qtd, &qh->qtd_list, qtd_list_entry) { +- while ((qh->ntd < ntd_max) && (qtd->isoc_frame_index_last < qtd->urb->packet_count)) { +- ++ while ((qh->ntd < ntd_max) ++ && (qtd->isoc_frame_index_last < ++ qtd->urb->packet_count)) { ++ + dma_desc = &qh->desc_list[idx]; + dwc_memset(dma_desc, 0x00, sizeof(dwc_otg_host_dma_desc_t)); + + frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index_last]; +- ++ + if (frame_desc->length > max_xfer_size) + qh->n_bytes[idx] = max_xfer_size; + else + qh->n_bytes[idx] = frame_desc->length; + dma_desc->status.b_isoc.n_bytes = qh->n_bytes[idx]; + dma_desc->status.b_isoc.a = 1; +- ++ dma_desc->status.b_isoc.sts = 0; ++ + dma_desc->buf = qtd->urb->dma + frame_desc->offset; +- ++ + qh->ntd++; + + qtd->isoc_frame_index_last++; +- +- #ifdef ISOC_URB_GIVEBACK_ASAP ++ ++#ifdef ISOC_URB_GIVEBACK_ASAP + /* + * Set IOC for each descriptor corresponding to the + * last frame of the URB. +- */ +- if (qtd->isoc_frame_index_last == qtd->urb->packet_count) ++ */ ++ if (qtd->isoc_frame_index_last == ++ qtd->urb->packet_count) + dma_desc->status.b_isoc.ioc = 1; +- +- #endif ++ ++#endif + idx = desclist_idx_inc(idx, inc, qh->dev_speed); + n_desc++; +- ++ + } + qtd->in_process = 1; + } +- ++ + qh->td_last = idx; +- ++ + #ifdef ISOC_URB_GIVEBACK_ASAP +- /* Set IOC for the last descriptor if descriptor list is full */ ++ /* Set IOC for the last descriptor if descriptor list is full */ + if (qh->ntd == ntd_max) { + idx = desclist_idx_dec(qh->td_last, inc, qh->dev_speed); + qh->desc_list[idx].status.b_isoc.ioc = 1; + } +-#else ++#else + /* + * Set IOC bit only for one descriptor. + * Always try to be ahead of HW processing, +@@ -545,81 +572,79 @@ + * Actually more than one QTD might be in the list if this function called + * from XferCompletion - QTDs was queued during HW processing of the previous + * descriptor chunk. +- */ ++ */ + idx = dwc_desclist_idx_dec(idx, inc * ((qh->ntd + 1) / 2), qh->dev_speed); +- } +- else { ++ } else { + /* + * Set the IOC for the latest descriptor + * if either number of descriptor is not greather than threshold + * or no more new descriptors activated. +- */ ++ */ + idx = dwc_desclist_idx_dec(qh->td_last, inc, qh->dev_speed); + } +- ++ + qh->desc_list[idx].status.b_isoc.ioc = 1; + #endif + } + +- + static void init_non_isoc_dma_desc(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh) + { + + dwc_hc_t *hc; +- dwc_otg_host_dma_desc_t *dma_desc; ++ dwc_otg_host_dma_desc_t *dma_desc; + dwc_otg_qtd_t *qtd; +- int num_packets, len, n_desc = 0; +- +- hc = qh->channel; +- ++ int num_packets, len, n_desc = 0; ++ ++ hc = qh->channel; ++ + /* + * Start with hc->xfer_buff initialized in + * assign_and_init_hc(), then if SG transfer consists of multiple URBs, + * this pointer re-assigned to the buffer of the currently processed QTD. + * For non-SG request there is always one QTD active. + */ +- ++ + DWC_CIRCLEQ_FOREACH(qtd, &qh->qtd_list, qtd_list_entry) { +- +- if (n_desc) { +- /* SG request - more than 1 QTDs */ ++ ++ if (n_desc) { ++ /* SG request - more than 1 QTDs */ + hc->xfer_buff = (uint8_t *)qtd->urb->dma + qtd->urb->actual_length; + hc->xfer_len = qtd->urb->length - qtd->urb->actual_length; +- } ++ } + + qtd->n_desc = 0; +- ++ + do { + dma_desc = &qh->desc_list[n_desc]; + len = hc->xfer_len; +- + + if (len > MAX_DMA_DESC_SIZE) + len = MAX_DMA_DESC_SIZE - hc->max_packet + 1; +- ++ + if (hc->ep_is_in) { + if (len > 0) { + num_packets = (len + hc->max_packet - 1) / hc->max_packet; +- } +- else { ++ } else { + /* Need 1 packet for transfer length of 0. */ + num_packets = 1; + } + /* Always program an integral # of max packets for IN transfers. */ +- len = num_packets * hc->max_packet; +- } +- ++ len = num_packets * hc->max_packet; ++ } ++ + dma_desc->status.b.n_bytes = len; +- ++ + qh->n_bytes[n_desc] = len; +- + +- if ((qh->ep_type == UE_CONTROL) && (qtd->control_phase == DWC_OTG_CONTROL_SETUP)) +- dma_desc->status.b.sup = 1; /* Setup Packet */ +- +- dma_desc->status.b.a = 1; /* Active descriptor */ +- +- dma_desc->buf = (uint32_t) hc->xfer_buff; ++ if ((qh->ep_type == UE_CONTROL) ++ && (qtd->control_phase == DWC_OTG_CONTROL_SETUP)) ++ dma_desc->status.b.sup = 1; /* Setup Packet */ ++ ++ dma_desc->status.b.a = 1; /* Active descriptor */ ++ dma_desc->status.b.sts = 0; ++ ++ dma_desc->buf = ++ ((unsigned long)hc->xfer_buff & 0xffffffff); + + /* + * Last descriptor(or single) of IN transfer +@@ -627,12 +652,11 @@ + */ + if (len > hc->xfer_len) { + hc->xfer_len = 0; +- } +- else { ++ } else { + hc->xfer_buff += len; + hc->xfer_len -= len; + } +- ++ + qtd->n_desc++; + n_desc++; + } +@@ -640,17 +664,20 @@ + + + qtd->in_process = 1; +- ++ ++ if (qh->ep_type == UE_CONTROL) ++ break; ++ + if (n_desc == MAX_DMA_DESC_NUM_GENERIC) + break; + } + + if (n_desc) { + /* Request Transfer Complete interrupt for the last descriptor */ +- qh->desc_list[n_desc-1].status.b.ioc = 1; ++ qh->desc_list[n_desc - 1].status.b.ioc = 1; + /* End of List indicator */ +- qh->desc_list[n_desc-1].status.b.eol = 1; +- ++ qh->desc_list[n_desc - 1].status.b.eol = 1; ++ + hc->ntd = n_desc; + } + } +@@ -677,73 +704,71 @@ + /* Channel is already assigned */ + dwc_hc_t *hc = qh->channel; + uint8_t skip_frames = 0; +- ++ + switch (hc->ep_type) { + case DWC_OTG_EP_TYPE_CONTROL: + case DWC_OTG_EP_TYPE_BULK: + init_non_isoc_dma_desc(hcd, qh); +- ++ + dwc_otg_hc_start_transfer_ddma(hcd->core_if, hc); + break; + case DWC_OTG_EP_TYPE_INTR: + init_non_isoc_dma_desc(hcd, qh); +- ++ + update_frame_list(hcd, qh, 1); +- ++ + dwc_otg_hc_start_transfer_ddma(hcd->core_if, hc); + break; + case DWC_OTG_EP_TYPE_ISOC: +- +- if(!qh->ntd) ++ ++ if (!qh->ntd) + skip_frames = recalc_initial_desc_idx(hcd, qh); +- ++ + init_isoc_dma_desc(hcd, qh, skip_frames); + + if (!hc->xfer_started) { + + update_frame_list(hcd, qh, 1); +- ++ + /* + * Always set to max, instead of actual size. + * Otherwise ntd will be changed with + * channel being enabled. Not recommended. + * +- */ ++ */ + hc->ntd = max_desc_num(qh); +- /* Enable channel only once for ISOC */ ++ /* Enable channel only once for ISOC */ + dwc_otg_hc_start_transfer_ddma(hcd->core_if, hc); + } +- ++ + break; + default: +- ++ + break; + } + } + +-static void complete_isoc_xfer_ddma(dwc_otg_hcd_t *hcd, +- dwc_hc_t *hc, +- dwc_otg_hc_regs_t *hc_regs, +- dwc_otg_halt_status_e halt_status) +-{ +- struct dwc_otg_hcd_iso_packet_desc *frame_desc; +- dwc_otg_qtd_t *qtd, *qtd_tmp; +- dwc_otg_qh_t *qh; +- dwc_otg_host_dma_desc_t *dma_desc; +- uint16_t idx, remain; +- uint8_t urb_compl; +- ++static void complete_isoc_xfer_ddma(dwc_otg_hcd_t * hcd, ++ dwc_hc_t * hc, ++ dwc_otg_hc_regs_t * hc_regs, ++ dwc_otg_halt_status_e halt_status) ++{ ++ struct dwc_otg_hcd_iso_packet_desc *frame_desc; ++ dwc_otg_qtd_t *qtd, *qtd_tmp; ++ dwc_otg_qh_t *qh; ++ dwc_otg_host_dma_desc_t *dma_desc; ++ uint16_t idx, remain; ++ uint8_t urb_compl; ++ + qh = hc->qh; + idx = qh->td_first; +- + + if (hc->halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE) { + DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp, &hc->qh->qtd_list, qtd_list_entry) +- qtd->in_process = 0; +- return; +- } +- else if ((halt_status == DWC_OTG_HC_XFER_AHB_ERR) || +- (halt_status == DWC_OTG_HC_XFER_BABBLE_ERR)) { ++ qtd->in_process = 0; ++ return; ++ } else if ((halt_status == DWC_OTG_HC_XFER_AHB_ERR) || ++ (halt_status == DWC_OTG_HC_XFER_BABBLE_ERR)) { + /* + * Channel is halted in these error cases. + * Considered as serious issues. +@@ -752,54 +777,52 @@ + * Pass error code to completion routine as well, to + * update urb->status, some of class drivers might use it to stop + * queing transfer requests. +- */ +- int err = (halt_status == DWC_OTG_HC_XFER_AHB_ERR) +- ? (-DWC_E_IO) +- : (-DWC_E_OVERFLOW); ++ */ ++ int err = (halt_status == DWC_OTG_HC_XFER_AHB_ERR) ++ ? (-DWC_E_IO) ++ : (-DWC_E_OVERFLOW); + + DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp, &hc->qh->qtd_list, qtd_list_entry) { +- for(idx = 0; idx < qtd->urb->packet_count; idx++) { ++ for (idx = 0; idx < qtd->urb->packet_count; idx++) { + frame_desc = &qtd->urb->iso_descs[idx]; + frame_desc->status = err; + } + hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, err); + dwc_otg_hcd_qtd_remove_and_free(hcd, qtd, qh); + } +- return; ++ return; + } +- +- ++ + DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp, &hc->qh->qtd_list, qtd_list_entry) { +- ++ + if (!qtd->in_process) +- break; +- ++ break; ++ + urb_compl = 0; +- ++ + do { + + dma_desc = &qh->desc_list[idx]; + + frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index]; + remain = hc->ep_is_in ? dma_desc->status.b_isoc.n_bytes : 0; +- ++ + if (dma_desc->status.b_isoc.sts == DMA_DESC_STS_PKTERR) { + /* +- * XactError or, unable to complete all the transactions +- * in the scheduled micro-frame/frame, +- * both indicated by DMA_DESC_STS_PKTERR. +- */ ++ * XactError or, unable to complete all the transactions ++ * in the scheduled micro-frame/frame, ++ * both indicated by DMA_DESC_STS_PKTERR. ++ */ + qtd->urb->error_count++; + frame_desc->actual_length = qh->n_bytes[idx] - remain; + frame_desc->status = -DWC_E_PROTOCOL; +- } +- else { +- /* Success */ ++ } else { ++ /* Success */ + + frame_desc->actual_length = qh->n_bytes[idx] - remain; + frame_desc->status = 0; + } +- ++ + if (++qtd->isoc_frame_index == qtd->urb->packet_count) { + /* + * urb->status is not used for isoc transfers here. +@@ -808,53 +831,51 @@ + + hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, 0); + dwc_otg_hcd_qtd_remove_and_free(hcd, qtd, qh); +- ++ + /* + * This check is necessary because urb_dequeue can be called + * from urb complete callback(sound driver example). + * All pending URBs are dequeued there, so no need for + * further processing. +- */ ++ */ + if (hc->halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE) { + return; + } +- +- urb_compl = 1; +- ++ ++ urb_compl = 1; ++ + } +- ++ + qh->ntd--; +- ++ + /* Stop if IOC requested descriptor reached */ + if (dma_desc->status.b_isoc.ioc) { + idx = desclist_idx_inc(idx, qh->interval, hc->speed); + goto stop_scan; + } +- ++ + idx = desclist_idx_inc(idx, qh->interval, hc->speed); +- ++ + if (urb_compl) + break; + } +- while(idx != qh->td_first); ++ while (idx != qh->td_first); + } +-stop_scan: ++stop_scan: + qh->td_first = idx; + } +- ++ + uint8_t update_non_isoc_urb_state_ddma(dwc_otg_hcd_t * hcd, +- dwc_hc_t * hc, +- dwc_otg_qtd_t * qtd, +- dwc_otg_host_dma_desc_t * dma_desc, +- dwc_otg_halt_status_e halt_status, +- uint32_t n_bytes, +- uint8_t *xfer_done) ++ dwc_hc_t * hc, ++ dwc_otg_qtd_t * qtd, ++ dwc_otg_host_dma_desc_t * dma_desc, ++ dwc_otg_halt_status_e halt_status, ++ uint32_t n_bytes, uint8_t * xfer_done) + { + + uint16_t remain = hc->ep_is_in ? dma_desc->status.b.n_bytes : 0; + dwc_otg_hcd_urb_t *urb = qtd->urb; +- +- ++ + if (halt_status == DWC_OTG_HC_XFER_AHB_ERR) { + urb->status = -DWC_E_IO; + return 1; +@@ -877,92 +898,94 @@ + } + return 1; + } +- ++ + if (dma_desc->status.b.a == 1) { +- DWC_DEBUGPL(DBG_HCDV, "Active descriptor encountered on channel %d\n", hc->hc_num); ++ DWC_DEBUGPL(DBG_HCDV, ++ "Active descriptor encountered on channel %d\n", ++ hc->hc_num); + return 0; + } +- ++ + if (hc->ep_type == DWC_OTG_EP_TYPE_CONTROL) { +- if (qtd->control_phase == DWC_OTG_CONTROL_DATA) { ++ if (qtd->control_phase == DWC_OTG_CONTROL_DATA) { ++ urb->actual_length += n_bytes - remain; ++ if (remain || urb->actual_length == urb->length) { ++ /* ++ * For Control Data stage do not set urb->status=0 to prevent ++ * URB callback. Set it when Status phase done. See below. ++ */ ++ *xfer_done = 1; ++ } ++ ++ } else if (qtd->control_phase == DWC_OTG_CONTROL_STATUS) { ++ urb->status = 0; ++ *xfer_done = 1; ++ } ++ /* No handling for SETUP stage */ ++ } else { ++ /* BULK and INTR */ + urb->actual_length += n_bytes - remain; +- if (remain || urb->actual_length >= urb->length) { +- /* +- * For Control Data stage do not set urb->status=0 to prevent +- * URB callback. Set it when Status phase done. See below. +- */ ++ if (remain || urb->actual_length == urb->length) { ++ urb->status = 0; + *xfer_done = 1; +- } +- +- } +- else if (qtd->control_phase == DWC_OTG_CONTROL_STATUS) { +- urb->status = 0; +- *xfer_done = 1; +- } +- /* No handling for SETUP stage */ +- +- } +- else { +- /* BULK and INTR */ +- urb->actual_length += n_bytes - remain; +- if (remain || urb->actual_length >= urb->length) { +- urb->status = 0; +- *xfer_done = 1; +- } ++ } + } + + return 0; + } + + static void complete_non_isoc_xfer_ddma(dwc_otg_hcd_t * hcd, +- dwc_hc_t * hc, +- dwc_otg_hc_regs_t * hc_regs, +- dwc_otg_halt_status_e halt_status) +-{ +- dwc_otg_hcd_urb_t *urb = NULL; +- dwc_otg_qtd_t *qtd, *qtd_tmp; +- dwc_otg_qh_t *qh; +- dwc_otg_host_dma_desc_t *dma_desc; +- uint32_t n_bytes, n_desc, i; +- uint8_t failed = 0, xfer_done; +- ++ dwc_hc_t * hc, ++ dwc_otg_hc_regs_t * hc_regs, ++ dwc_otg_halt_status_e halt_status) ++{ ++ dwc_otg_hcd_urb_t *urb = NULL; ++ dwc_otg_qtd_t *qtd, *qtd_tmp; ++ dwc_otg_qh_t *qh; ++ dwc_otg_host_dma_desc_t *dma_desc; ++ uint32_t n_bytes, n_desc, i; ++ uint8_t failed = 0, xfer_done; ++ + n_desc = 0; +- ++ + qh = hc->qh; + +- + if (hc->halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE) { + DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp, &hc->qh->qtd_list, qtd_list_entry) { + qtd->in_process = 0; + } + return; + } +- ++ + DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp, &qh->qtd_list, qtd_list_entry) { +- ++ + urb = qtd->urb; + +- n_bytes = 0; +- xfer_done = 0; +- ++ n_bytes = 0; ++ xfer_done = 0; ++ + for (i = 0; i < qtd->n_desc; i++) { + dma_desc = &qh->desc_list[n_desc]; +- ++ + n_bytes = qh->n_bytes[n_desc]; +- +- +- failed = update_non_isoc_urb_state_ddma(hcd, hc, qtd, dma_desc, +- halt_status, n_bytes, &xfer_done); +- +- if (failed || (xfer_done && (urb->status != -DWC_E_IN_PROGRESS))) { +- +- hcd->fops->complete(hcd, urb->priv, urb, urb->status); ++ ++ failed = ++ update_non_isoc_urb_state_ddma(hcd, hc, qtd, ++ dma_desc, ++ halt_status, n_bytes, ++ &xfer_done); ++ ++ if (failed ++ || (xfer_done ++ && (urb->status != -DWC_E_IN_PROGRESS))) { ++ ++ hcd->fops->complete(hcd, urb->priv, urb, ++ urb->status); + dwc_otg_hcd_qtd_remove_and_free(hcd, qtd, qh); + + if (failed) + goto stop_scan; +- } +- else if (qh->ep_type == UE_CONTROL) { ++ } else if (qh->ep_type == UE_CONTROL) { + if (qtd->control_phase == DWC_OTG_CONTROL_SETUP) { + if (urb->length > 0) { + qtd->control_phase = DWC_OTG_CONTROL_DATA; +@@ -970,50 +993,47 @@ + qtd->control_phase = DWC_OTG_CONTROL_STATUS; + } + DWC_DEBUGPL(DBG_HCDV, " Control setup transaction done\n"); +- } +- else if(qtd->control_phase == DWC_OTG_CONTROL_DATA) { ++ } else if (qtd->control_phase == DWC_OTG_CONTROL_DATA) { + if (xfer_done) { + qtd->control_phase = DWC_OTG_CONTROL_STATUS; + DWC_DEBUGPL(DBG_HCDV, " Control data transfer done\n"); +- } else if (i+1 == qtd->n_desc){ ++ } else if (i + 1 == qtd->n_desc) { + /* + * Last descriptor for Control data stage which is + * not completed yet. +- */ ++ */ + dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd); + } + } + } +- ++ + n_desc++; + } +- ++ + } +- +-stop_scan: +- ++ ++stop_scan: ++ + if (qh->ep_type != UE_CONTROL) { + /* + * Resetting the data toggle for bulk + * and interrupt endpoints in case of stall. See handle_hc_stall_intr() +- */ +- if (halt_status == DWC_OTG_HC_XFER_STALL) { +- qh->data_toggle = DWC_OTG_HC_PID_DATA0; +- } +- else { ++ */ ++ if (halt_status == DWC_OTG_HC_XFER_STALL) ++ qh->data_toggle = DWC_OTG_HC_PID_DATA0; ++ else + dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd); +- } + } +- ++ + if (halt_status == DWC_OTG_HC_XFER_COMPLETE) { + hcint_data_t hcint; +- hcint.d32 = dwc_read_reg32(&hc_regs->hcint); ++ hcint.d32 = DWC_READ_REG32(&hc_regs->hcint); + if (hcint.b.nyet) { + /* +- * Got a NYET on the last transaction of the transfer. It +- * means that the endpoint should be in the PING state at the +- * beginning of the next transfer. +- */ ++ * Got a NYET on the last transaction of the transfer. It ++ * means that the endpoint should be in the PING state at the ++ * beginning of the next transfer. ++ */ + qh->ping_state = 1; + clear_hc_int(hc_regs, nyet); + } +@@ -1039,55 +1059,51 @@ + * @param halt_status Reason the channel is being halted, + * or just XferComplete for isochronous transfer + */ +-void dwc_otg_hcd_complete_xfer_ddma(dwc_otg_hcd_t *hcd, +- dwc_hc_t *hc, +- dwc_otg_hc_regs_t *hc_regs, +- dwc_otg_halt_status_e halt_status) ++void dwc_otg_hcd_complete_xfer_ddma(dwc_otg_hcd_t * hcd, ++ dwc_hc_t * hc, ++ dwc_otg_hc_regs_t * hc_regs, ++ dwc_otg_halt_status_e halt_status) + { + uint8_t continue_isoc_xfer = 0; + dwc_otg_transaction_type_e tr_type; + dwc_otg_qh_t *qh = hc->qh; +- ++ + if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC) { + + complete_isoc_xfer_ddma(hcd, hc, hc_regs, halt_status); +- +- /* Release the channel if halted or session completed */ ++ ++ /* Release the channel if halted or session completed */ + if (halt_status != DWC_OTG_HC_XFER_COMPLETE || +- DWC_CIRCLEQ_EMPTY(&qh->qtd_list)) { ++ DWC_CIRCLEQ_EMPTY(&qh->qtd_list)) { + +- /* Halt the channel if session completed */ ++ /* Halt the channel if session completed */ + if (halt_status == DWC_OTG_HC_XFER_COMPLETE) { + dwc_otg_hc_halt(hcd->core_if, hc, halt_status); +- } +- ++ } ++ + release_channel_ddma(hcd, qh); + dwc_otg_hcd_qh_remove(hcd, qh); +- } +- else { ++ } else { + /* Keep in assigned schedule to continue transfer */ + DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_assigned, + &qh->qh_list_entry); + continue_isoc_xfer = 1; +- ++ + } + /** @todo Consider the case when period exceeds FrameList size. + * Frame Rollover interrupt should be used. + */ +- } +- else { +- /* Scan descriptor list to complete the URB(s), then release the channel */ ++ } else { ++ /* Scan descriptor list to complete the URB(s), then release the channel */ + complete_non_isoc_xfer_ddma(hcd, hc, hc_regs, halt_status); +- ++ + release_channel_ddma(hcd, qh); +- + dwc_otg_hcd_qh_remove(hcd, qh); +- ++ + if (!DWC_CIRCLEQ_EMPTY(&qh->qtd_list)) { + /* Add back to inactive non-periodic schedule on normal completion */ + dwc_otg_hcd_qh_add(hcd, qh); + } +- + + } + tr_type = dwc_otg_hcd_select_transactions(hcd); +@@ -1102,5 +1118,5 @@ + dwc_otg_hcd_queue_transactions(hcd, tr_type); + } + } +- +-#endif /* DWC_DEVICE_ONLY */ ++ ++#endif /* DWC_DEVICE_ONLY */ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_hcd_if.h +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/dwc_otg_hcd_if.h 2013-07-26 19:31:23.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_hcd_if.h 2013-07-26 19:34:44.000000000 +0000 +@@ -1,8 +1,8 @@ + /* ========================================================================== + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd_if.h $ +- * $Revision: #6 $ +- * $Date: 2009/04/21 $ +- * $Change: 1237474 $ ++ * $Revision: #12 $ ++ * $Date: 2011/10/26 $ ++ * $Change: 1873028 $ + * + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless +@@ -175,6 +175,13 @@ + extern uint32_t dwc_otg_hcd_otg_port(dwc_otg_hcd_t * hcd); + + /** ++ * Returns OTG version - either 1.3 or 2.0. ++ * ++ * @param core_if The core_if structure pointer ++ */ ++extern uint16_t dwc_otg_get_otg_version(dwc_otg_core_if_t * core_if); ++ ++/** + * Returns 1 if currently core is acting as B host, and 0 otherwise. + * + * @param hcd The HCD +@@ -223,7 +230,7 @@ + + /** + * Allocates memory for dwc_otg_hcd_urb structure. +- * Allocated memory should be freed by call dwc_free function. ++ * Allocated memory should be freed by call of DWC_FREE. + * + * @param hcd The HCD + * @param iso_desc_count Count of ISOC descriptors +@@ -248,7 +255,7 @@ + uint8_t ep_type, uint8_t ep_dir, + uint16_t mps); + +-/* Transfer flags */ ++/* Transfer flags */ + #define URB_GIVEBACK_ASAP 0x1 + #define URB_SEND_ZERO_PACKET 0x2 + +@@ -325,6 +332,7 @@ + * @param dwc_otg_hcd The HCD + * @param dwc_otg_urb DWC_OTG URB + * @param ep_handle Out parameter for returning endpoint handle ++ * @param atomic_alloc Flag to do atomic allocation if needed + * + * Returns -DWC_E_NO_DEVICE if no device is connected. + * Returns -DWC_E_NO_MEMORY if there is no enough memory. +@@ -332,7 +340,7 @@ + */ + extern int dwc_otg_hcd_urb_enqueue(dwc_otg_hcd_t * dwc_otg_hcd, + dwc_otg_hcd_urb_t * dwc_otg_urb, +- void **ep_handle); ++ void **ep_handle, int atomic_alloc); + + /** De-queue the specified URB + * +@@ -355,6 +363,17 @@ + extern int dwc_otg_hcd_endpoint_disable(dwc_otg_hcd_t * hcd, void *ep_handle, + int retry); + ++/* Resets the data toggle in qh structure. This function can be called from ++ * usb_clear_halt routine. ++ * ++ * @param hcd The HCD ++ * @param ep_handle Endpoint handle, returned by dwc_otg_hcd_urb_enqueue function ++ * ++ * Returns -DWC_E_INVALID if invalid arguments are passed. ++ * Returns 0 on success ++ */ ++extern int dwc_otg_hcd_endpoint_reset(dwc_otg_hcd_t * hcd, void *ep_handle); ++ + /** Returns 1 if status of specified port is changed and 0 otherwise. + * + * @param hcd The HCD +@@ -389,5 +408,5 @@ + + /** @} */ + +-#endif /* __DWC_HCD_IF_H__ */ +-#endif /* DWC_DEVICE_ONLY */ ++#endif /* __DWC_HCD_IF_H__ */ ++#endif /* DWC_DEVICE_ONLY */ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c 2013-07-26 19:34:36.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c 2013-07-26 19:34:44.000000000 +0000 +@@ -1,8 +1,8 @@ + /* ========================================================================== + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd_intr.c $ +- * $Revision: #77 $ +- * $Date: 2009/04/21 $ +- * $Change: 1237475 $ ++ * $Revision: #89 $ ++ * $Date: 2011/10/20 $ ++ * $Change: 1869487 $ + * + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless +@@ -58,10 +58,16 @@ + } + #endif + ++ /* Exit from ISR if core is hibernated */ ++ if (core_if->hibernation_suspend == 1) { ++ return retval; ++ } ++ DWC_SPINLOCK(dwc_otg_hcd->lock); + /* Check if HOST Mode */ + if (dwc_otg_is_host_mode(core_if)) { + gintsts.d32 = dwc_otg_read_core_intr(core_if); + if (!gintsts.d32) { ++ DWC_SPINUNLOCK(dwc_otg_hcd->lock); + return 0; + } + #ifdef DEBUG +@@ -69,14 +75,14 @@ + #ifndef DEBUG_SOF + if (gintsts.d32 != DWC_SOF_INTR_MASK) + #endif +- DWC_DEBUGPL(DBG_HCD, "\n"); ++ DWC_DEBUGPL(DBG_HCDI, "\n"); + #endif + + #ifdef DEBUG + #ifndef DEBUG_SOF + if (gintsts.d32 != DWC_SOF_INTR_MASK) + #endif +- DWC_DEBUGPL(DBG_HCD, ++ DWC_DEBUGPL(DBG_HCDI, + "DWC OTG HCD Interrupt Detected gintsts&gintmsk=0x%08x core_if=%p\n", + gintsts.d32, core_if); + #endif +@@ -113,12 +119,12 @@ + if (gintsts.d32 != DWC_SOF_INTR_MASK) + #endif + { +- DWC_DEBUGPL(DBG_HCD, ++ DWC_DEBUGPL(DBG_HCDI, + "DWC OTG HCD Finished Servicing Interrupts\n"); + DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD gintsts=0x%08x\n", +- dwc_read_reg32(&global_regs->gintsts)); ++ DWC_READ_REG32(&global_regs->gintsts)); + DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD gintmsk=0x%08x\n", +- dwc_read_reg32(&global_regs->gintmsk)); ++ DWC_READ_REG32(&global_regs->gintmsk)); + } + #endif + +@@ -126,11 +132,11 @@ + #ifndef DEBUG_SOF + if (gintsts.d32 != DWC_SOF_INTR_MASK) + #endif +- DWC_DEBUGPL(DBG_HCD, "\n"); ++ DWC_DEBUGPL(DBG_HCDI, "\n"); + #endif + + } +- ++ DWC_SPINUNLOCK(dwc_otg_hcd->lock); + return retval; + } + +@@ -183,7 +189,7 @@ + gintsts_data_t gintsts = {.d32 = 0 }; + + hfnum.d32 = +- dwc_read_reg32(&hcd->core_if->host_if->host_global_regs->hfnum); ++ DWC_READ_REG32(&hcd->core_if->host_if->host_global_regs->hfnum); + + #ifdef DEBUG_SOF + DWC_DEBUGPL(DBG_HCD, "--Start of Frame Interrupt--\n"); +@@ -219,7 +225,7 @@ + + /* Clear interrupt */ + gintsts.b.sofintr = 1; +- dwc_write_reg32(&hcd->core_if->core_global_regs->gintsts, gintsts.d32); ++ DWC_WRITE_REG32(&hcd->core_if->core_global_regs->gintsts, gintsts.d32); + + return 1; + } +@@ -235,9 +241,13 @@ + DWC_DEBUGPL(DBG_HCD, "--RxStsQ Level Interrupt--\n"); + + grxsts.d32 = +- dwc_read_reg32(&dwc_otg_hcd->core_if->core_global_regs->grxstsp); ++ DWC_READ_REG32(&dwc_otg_hcd->core_if->core_global_regs->grxstsp); + + hc = dwc_otg_hcd->hc_ptr_array[grxsts.b.chnum]; ++ if (!hc) { ++ DWC_ERROR("Unable to get corresponding channel\n"); ++ return 0; ++ } + + /* Packet Status */ + DWC_DEBUGPL(DBG_HCDV, " Ch num = %d\n", grxsts.b.chnum); +@@ -305,8 +315,8 @@ + hprt0_data_t hprt0; + hprt0_data_t hprt0_modify; + +- hprt0.d32 = dwc_read_reg32(dwc_otg_hcd->core_if->host_if->hprt0); +- hprt0_modify.d32 = dwc_read_reg32(dwc_otg_hcd->core_if->host_if->hprt0); ++ hprt0.d32 = DWC_READ_REG32(dwc_otg_hcd->core_if->host_if->hprt0); ++ hprt0_modify.d32 = DWC_READ_REG32(dwc_otg_hcd->core_if->host_if->hprt0); + + /* Clear appropriate bits in HPRT0 to clear the interrupt bit in + * GINTSTS */ +@@ -318,16 +328,41 @@ + + /* Port Connect Detected + * Set flag and clear if detected */ +- if (hprt0.b.prtconndet) { +- DWC_DEBUGPL(DBG_HCD, "--Port Interrupt HPRT0=0x%08x " +- "Port Connect Detected--\n", hprt0.d32); +- dwc_otg_hcd->flags.b.port_connect_status_change = 1; +- dwc_otg_hcd->flags.b.port_connect_status = 1; ++ if (dwc_otg_hcd->core_if->hibernation_suspend == 1) { ++ // Dont modify port status if we are in hibernation state + hprt0_modify.b.prtconndet = 1; ++ hprt0_modify.b.prtenchng = 1; ++ DWC_WRITE_REG32(dwc_otg_hcd->core_if->host_if->hprt0, hprt0_modify.d32); ++ hprt0.d32 = DWC_READ_REG32(dwc_otg_hcd->core_if->host_if->hprt0); ++ return retval; ++ } + +- /* B-Device has connected, Delete the connection timer. */ +- DWC_TIMER_CANCEL(dwc_otg_hcd->conn_timer); +- ++ if (hprt0.b.prtconndet) { ++ /** @todo - check if steps performed in 'else' block should be perfromed regardles adp */ ++ if (dwc_otg_hcd->core_if->adp_enable && ++ dwc_otg_hcd->core_if->adp.vbuson_timer_started == 1) { ++ DWC_PRINTF("PORT CONNECT DETECTED ----------------\n"); ++ DWC_TIMER_CANCEL(dwc_otg_hcd->core_if->adp.vbuson_timer); ++ dwc_otg_hcd->core_if->adp.vbuson_timer_started = 0; ++ /* TODO - check if this is required, as ++ * host initialization was already performed ++ * after initial ADP probing ++ */ ++ /*dwc_otg_hcd->core_if->adp.vbuson_timer_started = 0; ++ dwc_otg_core_init(dwc_otg_hcd->core_if); ++ dwc_otg_enable_global_interrupts(dwc_otg_hcd->core_if); ++ cil_hcd_start(dwc_otg_hcd->core_if);*/ ++ } else { ++ ++ DWC_DEBUGPL(DBG_HCD, "--Port Interrupt HPRT0=0x%08x " ++ "Port Connect Detected--\n", hprt0.d32); ++ dwc_otg_hcd->flags.b.port_connect_status_change = 1; ++ dwc_otg_hcd->flags.b.port_connect_status = 1; ++ hprt0_modify.b.prtconndet = 1; ++ ++ /* B-Device has connected, Delete the connection timer. */ ++ DWC_TIMER_CANCEL(dwc_otg_hcd->conn_timer); ++ } + /* The Hub driver asserts a reset when it sees port connect + * status change flag */ + retval |= 1; +@@ -340,6 +375,7 @@ + "Port Enable Changed--\n", hprt0.d32); + hprt0_modify.b.prtenchng = 1; + if (hprt0.b.prtena == 1) { ++ hfir_data_t hfir; + int do_reset = 0; + dwc_otg_core_params_t *params = + dwc_otg_hcd->core_if->core_params; +@@ -347,6 +383,13 @@ + dwc_otg_hcd->core_if->core_global_regs; + dwc_otg_host_if_t *host_if = + dwc_otg_hcd->core_if->host_if; ++ ++ /* Every time when port enables calculate ++ * HFIR.FrInterval ++ */ ++ hfir.d32 = DWC_READ_REG32(&host_if->host_global_regs->hfir); ++ hfir.b.frint = calc_frame_interval(dwc_otg_hcd->core_if); ++ DWC_WRITE_REG32(&host_if->host_global_regs->hfir, hfir.d32); + + /* Check if we need to adjust the PHY clock speed for + * low power and adjust it */ +@@ -354,7 +397,7 @@ + gusbcfg_data_t usbcfg; + + usbcfg.d32 = +- dwc_read_reg32(&global_regs->gusbcfg); ++ DWC_READ_REG32(&global_regs->gusbcfg); + + if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_LOW_SPEED + || hprt0.b.prtspd == +@@ -366,20 +409,20 @@ + if (usbcfg.b.phylpwrclksel == 0) { + /* Set PHY low power clock select for FS/LS devices */ + usbcfg.b.phylpwrclksel = 1; +- dwc_write_reg32(&global_regs-> +- gusbcfg, +- usbcfg.d32); ++ DWC_WRITE_REG32 ++ (&global_regs->gusbcfg, ++ usbcfg.d32); + do_reset = 1; + } + + hcfg.d32 = +- dwc_read_reg32(&host_if-> +- host_global_regs->hcfg); ++ DWC_READ_REG32 ++ (&host_if->host_global_regs->hcfg); + + if (hprt0.b.prtspd == + DWC_HPRT0_PRTSPD_LOW_SPEED +- && params-> +- host_ls_low_power_phy_clk == ++ && params->host_ls_low_power_phy_clk ++ == + DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ) + { + /* 6 MHZ */ +@@ -389,10 +432,9 @@ + DWC_HCFG_6_MHZ) { + hcfg.b.fslspclksel = + DWC_HCFG_6_MHZ; +- dwc_write_reg32 +- (&host_if-> +- host_global_regs-> +- hcfg, hcfg.d32); ++ DWC_WRITE_REG32 ++ (&host_if->host_global_regs->hcfg, ++ hcfg.d32); + do_reset = 1; + } + } else { +@@ -403,10 +445,9 @@ + DWC_HCFG_48_MHZ) { + hcfg.b.fslspclksel = + DWC_HCFG_48_MHZ; +- dwc_write_reg32 +- (&host_if-> +- host_global_regs-> +- hcfg, hcfg.d32); ++ DWC_WRITE_REG32 ++ (&host_if->host_global_regs->hcfg, ++ hcfg.d32); + do_reset = 1; + } + } +@@ -416,16 +457,15 @@ + */ + if (usbcfg.b.phylpwrclksel == 1) { + usbcfg.b.phylpwrclksel = 0; +- dwc_write_reg32(&global_regs-> +- gusbcfg, +- usbcfg.d32); ++ DWC_WRITE_REG32 ++ (&global_regs->gusbcfg, ++ usbcfg.d32); + do_reset = 1; + } + } + + if (do_reset) { +- DWC_TASK_SCHEDULE(dwc_otg_hcd-> +- reset_tasklet); ++ DWC_TASK_SCHEDULE(dwc_otg_hcd->reset_tasklet); + } + } + +@@ -449,7 +489,7 @@ + } + + /* Clear Port Interrupts */ +- dwc_write_reg32(dwc_otg_hcd->core_if->host_if->hprt0, hprt0_modify.d32); ++ DWC_WRITE_REG32(dwc_otg_hcd->core_if->host_if->hprt0, hprt0_modify.d32); + + return retval; + } +@@ -478,8 +518,6 @@ + return retval; + } + +- +- + /** + * Gets the actual length of a transfer after the transfer halts. _halt_status + * holds the reason for the halt. +@@ -502,7 +540,7 @@ + if (short_read != NULL) { + *short_read = 0; + } +- hctsiz.d32 = dwc_read_reg32(&hc_regs->hctsiz); ++ hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz); + + if (halt_status == DWC_OTG_HC_XFER_COMPLETE) { + if (hc->ep_is_in) { +@@ -551,21 +589,23 @@ + + int xfer_length; + +- xfer_length = get_actual_xfer_length(hc, hc_regs, qtd, +- DWC_OTG_HC_XFER_COMPLETE, +- &short_read); ++ xfer_length = get_actual_xfer_length(hc, hc_regs, qtd, ++ DWC_OTG_HC_XFER_COMPLETE, ++ &short_read); + + + /* non DWORD-aligned buffer case handling. */ + if (hc->align_buff && xfer_length && hc->ep_is_in) { +- dwc_memcpy(urb->buf + urb->actual_length, hc->qh->dw_align_buf, xfer_length); ++ dwc_memcpy(urb->buf + urb->actual_length, hc->qh->dw_align_buf, ++ xfer_length); + } + + urb->actual_length += xfer_length; + +- if(xfer_length && (hc->ep_type == DWC_OTG_EP_TYPE_BULK) && +- (urb->flags & URB_SEND_ZERO_PACKET) && (urb->actual_length == urb->length) && +- !(urb->length % hc->max_packet)) { ++ if (xfer_length && (hc->ep_type == DWC_OTG_EP_TYPE_BULK) && ++ (urb->flags & URB_SEND_ZERO_PACKET) ++ && (urb->actual_length == urb->length) ++ && !(urb->length % hc->max_packet)) { + xfer_done = 0; + } else if (short_read || urb->actual_length >= urb->length) { + xfer_done = 1; +@@ -575,7 +615,7 @@ + #ifdef DEBUG + { + hctsiz_data_t hctsiz; +- hctsiz.d32 = dwc_read_reg32(&hc_regs->hctsiz); ++ hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz); + DWC_DEBUGPL(DBG_HCDV, "DWC_otg: %s: %s, channel %d\n", + __func__, (hc->ep_is_in ? "IN" : "OUT"), + hc->hc_num); +@@ -603,7 +643,7 @@ + dwc_otg_hc_regs_t * hc_regs, dwc_otg_qtd_t * qtd) + { + hctsiz_data_t hctsiz; +- hctsiz.d32 = dwc_read_reg32(&hc_regs->hctsiz); ++ hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz); + + if (hc->ep_type != DWC_OTG_EP_TYPE_CONTROL) { + dwc_otg_qh_t *qh = hc->qh; +@@ -646,10 +686,10 @@ + frame_desc->status = 0; + frame_desc->actual_length = + get_actual_xfer_length(hc, hc_regs, qtd, halt_status, NULL); +- ++ + /* non DWORD-aligned buffer case handling. */ + if (hc->align_buff && frame_desc->actual_length && hc->ep_is_in) { +- dwc_memcpy(urb->buf + frame_desc->offset + qtd->isoc_split_offset, ++ dwc_memcpy(urb->buf + frame_desc->offset + qtd->isoc_split_offset, + hc->qh->dw_align_buf, frame_desc->actual_length); + } + +@@ -673,19 +713,19 @@ + frame_desc->status = -DWC_E_PROTOCOL; + frame_desc->actual_length = + get_actual_xfer_length(hc, hc_regs, qtd, halt_status, NULL); +- ++ + /* non DWORD-aligned buffer case handling. */ + if (hc->align_buff && frame_desc->actual_length && hc->ep_is_in) { +- dwc_memcpy(urb->buf + frame_desc->offset + qtd->isoc_split_offset, ++ dwc_memcpy(urb->buf + frame_desc->offset + qtd->isoc_split_offset, + hc->qh->dw_align_buf, frame_desc->actual_length); + } + /* Skip whole frame */ +- if (hc->qh->do_split && (hc->ep_type == DWC_OTG_EP_TYPE_ISOC) && +- hc->ep_is_in && hcd->core_if->dma_enable) { ++ if (hc->qh->do_split && (hc->ep_type == DWC_OTG_EP_TYPE_ISOC) && ++ hc->ep_is_in && hcd->core_if->dma_enable) { + qtd->complete_split = 0; + qtd->isoc_split_offset = 0; + } +- ++ + break; + default: + DWC_ASSERT(1, "Unhandled _halt_status (%d)\n", halt_status); +@@ -758,19 +798,6 @@ + DWC_DEBUGPL(DBG_HCDV, " %s: channel %d, halt_status %d, xfer_len %d\n", + __func__, hc->hc_num, halt_status, hc->xfer_len); + +-#ifdef HW2937_WORKAROUND +- if (hcd->hw2937_assigned_channels & (1<hc_num)) +- { +- if ((hcd->hw2937_assigned_channels &= ~(1<hc_num)) == 0) +- hcd->hw2937_xfer_mode = HW2937_XFER_MODE_IDLE; +- DWC_DEBUGPL(DBG_HW2937, " release %d, hw2937_ac -> %x\n", hc->hc_num, hcd->hw2937_assigned_channels); +- } +- else +- { +- DWC_DEBUGPL(DBG_ANY, " Unexpected release %d (hw2937_ac = %x)\n", hc->hc_num, hcd->hw2937_assigned_channels); +- } +-#endif +- + switch (halt_status) { + case DWC_OTG_HC_XFER_URB_COMPLETE: + free_qtd = 1; +@@ -802,6 +829,14 @@ + case DWC_OTG_HC_XFER_NO_HALT_STATUS: + free_qtd = 0; + break; ++ case DWC_OTG_HC_XFER_PERIODIC_INCOMPLETE: ++ DWC_DEBUGPL(DBG_HCDV, ++ " Complete URB with I/O error\n"); ++ free_qtd = 1; ++ qtd->urb->status = -DWC_E_IO; ++ hcd->fops->complete(hcd, qtd->urb->priv, ++ qtd->urb, -DWC_E_IO); ++ break; + default: + free_qtd = 0; + break; +@@ -809,7 +844,7 @@ + + deactivate_qh(hcd, hc->qh, free_qtd); + +- cleanup: ++cleanup: + /* + * Release the host channel for use by other transfers. The cleanup + * function clears the channel interrupt enables and conditions, so +@@ -840,7 +875,6 @@ + } + } + +- + /** + * Halts a host channel. If the channel cannot be halted immediately because + * the request queue is full, this function ensures that the FIFO empty +@@ -876,7 +910,7 @@ + * be processed. + */ + gintmsk.b.nptxfempty = 1; +- dwc_modify_reg32(&global_regs->gintmsk, 0, gintmsk.d32); ++ DWC_MODIFY_REG32(&global_regs->gintmsk, 0, gintmsk.d32); + } else { + /* + * Move the QH from the periodic queued schedule to +@@ -893,7 +927,7 @@ + * processed. + */ + gintmsk.b.ptxfempty = 1; +- dwc_modify_reg32(&global_regs->gintmsk, 0, gintmsk.d32); ++ DWC_MODIFY_REG32(&global_regs->gintmsk, 0, gintmsk.d32); + } + } + } +@@ -913,7 +947,7 @@ + + qtd->error_count = 0; + +- hcint.d32 = dwc_read_reg32(&hc_regs->hcint); ++ hcint.d32 = DWC_READ_REG32(&hc_regs->hcint); + if (hcint.b.nyet) { + /* + * Got a NYET on the last transaction of the transfer. This +@@ -964,7 +998,7 @@ + hctsiz_data_t hctsiz; + qtd->error_count = 0; + +- hctsiz.d32 = dwc_read_reg32(&hc_regs->hctsiz); ++ hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz); + if (!hc->ep_is_in || hctsiz.b.pktcnt == 0) { + /* Core halts channel in these cases. */ + release_channel(hcd, hc, qtd, halt_status); +@@ -975,47 +1009,46 @@ + } + + static int32_t handle_xfercomp_isoc_split_in(dwc_otg_hcd_t * hcd, +- dwc_hc_t * hc, +- dwc_otg_hc_regs_t * hc_regs, +- dwc_otg_qtd_t * qtd) ++ dwc_hc_t * hc, ++ dwc_otg_hc_regs_t * hc_regs, ++ dwc_otg_qtd_t * qtd) + { +- uint32_t len; ++ uint32_t len; + struct dwc_otg_hcd_iso_packet_desc *frame_desc; + frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index]; +- ++ + len = get_actual_xfer_length(hc, hc_regs, qtd, +- DWC_OTG_HC_XFER_COMPLETE, +- NULL); +- ++ DWC_OTG_HC_XFER_COMPLETE, NULL); ++ + if (!len) { + qtd->complete_split = 0; + qtd->isoc_split_offset = 0; + return 0; + } + frame_desc->actual_length += len; +- ++ + if (hc->align_buff && len) +- dwc_memcpy(qtd->urb->buf + frame_desc->offset + qtd->isoc_split_offset, +- hc->qh->dw_align_buf, +- len); ++ dwc_memcpy(qtd->urb->buf + frame_desc->offset + ++ qtd->isoc_split_offset, hc->qh->dw_align_buf, len); + qtd->isoc_split_offset += len; +- ++ + if (frame_desc->length == frame_desc->actual_length) { + frame_desc->status = 0; + qtd->isoc_frame_index++; + qtd->complete_split = 0; + qtd->isoc_split_offset = 0; + } +- ++ + if (qtd->isoc_frame_index == qtd->urb->packet_count) { + hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, 0); + release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE); + } else { + release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NO_HALT_STATUS); + } +- +- return 1; /* Indicates that channel released */ ++ ++ return 1; /* Indicates that channel released */ + } ++ + /** + * Handles a host channel Transfer Complete interrupt. This handler may be + * called in either DMA mode or Slave mode. +@@ -1030,13 +1063,13 @@ + dwc_otg_hcd_urb_t *urb = qtd->urb; + int pipe_type = dwc_otg_hcd_get_pipe_type(&urb->pipe_info); + +- DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: " ++ DWC_DEBUGPL(DBG_HCDI, "--Host Channel %d Interrupt: " + "Transfer Complete--\n", hc->hc_num); + + if (hcd->core_if->dma_desc_enable) { + dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs, halt_status); + if (pipe_type == UE_ISOCHRONOUS) { +- /* Do not disable the interrupt, just clear it */ ++ /* Do not disable the interrupt, just clear it */ + clear_hc_int(hc_regs, xfercomp); + return 1; + } +@@ -1048,13 +1081,15 @@ + */ + + if (hc->qh->do_split) { +- if ((hc->ep_type == DWC_OTG_EP_TYPE_ISOC) && hc->ep_is_in && hcd->core_if->dma_enable) { +- if (qtd->complete_split && handle_xfercomp_isoc_split_in(hcd, hc, hc_regs, qtd)) ++ if ((hc->ep_type == DWC_OTG_EP_TYPE_ISOC) && hc->ep_is_in ++ && hcd->core_if->dma_enable) { ++ if (qtd->complete_split ++ && handle_xfercomp_isoc_split_in(hcd, hc, hc_regs, ++ qtd)) + goto handle_xfercomp_done; ++ } else { ++ qtd->complete_split = 0; + } +- else { +- qtd->complete_split = 0; +- } + } + + /* Update the QTD and URB states. */ +@@ -1114,16 +1149,22 @@ + break; + case UE_INTERRUPT: + DWC_DEBUGPL(DBG_HCDV, " Interrupt transfer complete\n"); +- update_urb_state_xfer_comp(hc, hc_regs, urb, qtd); ++ urb_xfer_done = ++ update_urb_state_xfer_comp(hc, hc_regs, urb, qtd); + + /* + * Interrupt URB is done on the first transfer complete + * interrupt. + */ +- hcd->fops->complete(hcd, urb->priv, urb, urb->status); ++ if (urb_xfer_done) { ++ hcd->fops->complete(hcd, urb->priv, urb, urb->status); ++ halt_status = DWC_OTG_HC_XFER_URB_COMPLETE; ++ } else { ++ halt_status = DWC_OTG_HC_XFER_COMPLETE; ++ } ++ + dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd); +- complete_periodic_xfer(hcd, hc, hc_regs, qtd, +- DWC_OTG_HC_XFER_URB_COMPLETE); ++ complete_periodic_xfer(hcd, hc, hc_regs, qtd, halt_status); + break; + case UE_ISOCHRONOUS: + DWC_DEBUGPL(DBG_HCDV, " Isochronous transfer complete\n"); +@@ -1202,15 +1243,16 @@ + halt_status, NULL); + /* non DWORD-aligned buffer case handling. */ + if (hc->align_buff && bytes_transferred && hc->ep_is_in) { +- dwc_memcpy(urb->buf + urb->actual_length, hc->qh->dw_align_buf, bytes_transferred); ++ dwc_memcpy(urb->buf + urb->actual_length, hc->qh->dw_align_buf, ++ bytes_transferred); + } +- ++ + urb->actual_length += bytes_transferred; + + #ifdef DEBUG + { + hctsiz_data_t hctsiz; +- hctsiz.d32 = dwc_read_reg32(&hc_regs->hctsiz); ++ hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz); + DWC_DEBUGPL(DBG_HCDV, "DWC_otg: %s: %s, channel %d\n", + __func__, (hc->ep_is_in ? "IN" : "OUT"), + hc->hc_num); +@@ -1237,7 +1279,7 @@ + dwc_otg_hc_regs_t * hc_regs, + dwc_otg_qtd_t * qtd) + { +- DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: " ++ DWC_DEBUGPL(DBG_HCDI, "--Host Channel %d Interrupt: " + "NAK Received--\n", hc->hc_num); + + /* +@@ -1257,11 +1299,6 @@ + case UE_CONTROL: + case UE_BULK: + if (hcd->core_if->dma_enable && hc->ep_is_in) { +-#ifdef HW2937_WORKAROUND +- if (hc->halt_status == DWC_OTG_HC_XFER_PAUSE_IN) { +- halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NAK); +- } +-#endif + /* + * NAK interrupts are enabled on bulk/control IN + * transfers in DMA mode for the sole purpose of +@@ -1287,7 +1324,7 @@ + + if (hc->speed == DWC_OTG_EP_SPEED_HIGH) + hc->qh->ping_state = 1; +- } ++ } + + /* + * Halt the channel so the transfer can be re-started from +@@ -1301,18 +1338,12 @@ + halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NAK); + break; + case UE_ISOCHRONOUS: +-#ifdef HW2937_WORKAROUND +- if (hc->halt_status == DWC_OTG_HC_XFER_PAUSE_IN) { +- halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NAK); +- break; +- } +-#endif + /* Should never get called for isochronous transfers. */ + DWC_ASSERT(1, "NACK interrupt for ISOC transfer\n"); + break; + } + +- handle_nak_done: ++handle_nak_done: + disable_hc_int(hc_regs, nak); + + return 1; +@@ -1328,7 +1359,7 @@ + dwc_otg_hc_regs_t * hc_regs, + dwc_otg_qtd_t * qtd) + { +- DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: " ++ DWC_DEBUGPL(DBG_HCDI, "--Host Channel %d Interrupt: " + "ACK Received--\n", hc->hc_num); + + if (hc->do_split) { +@@ -1362,11 +1393,11 @@ + */ + { + struct dwc_otg_hcd_iso_packet_desc +- *frame_desc; ++ *frame_desc; + + frame_desc = +- &qtd->urb->iso_descs[qtd-> +- isoc_frame_index]; ++ &qtd->urb-> ++ iso_descs[qtd->isoc_frame_index]; + qtd->isoc_split_offset += 188; + + if ((frame_desc->length - +@@ -1398,14 +1429,6 @@ + */ + halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_ACK); + } +-#ifdef HW2937_WORKAROUND +- else if (hc->halt_status == DWC_OTG_HC_XFER_PAUSE_IN) { +- dwc_otg_hc_regs_t *hc_regs = hcd->core_if->host_if->hc_regs[hc->hc_num]; +- update_urb_state_xfer_intr(hc, hc_regs, qtd->urb, qtd, DWC_OTG_HC_XFER_PAUSE_IN); +- dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd); +- release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_PAUSE_IN); +- } +-#endif + } + + /* +@@ -1430,7 +1453,7 @@ + dwc_otg_hc_regs_t * hc_regs, + dwc_otg_qtd_t * qtd) + { +- DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: " ++ DWC_DEBUGPL(DBG_HCDI, "--Host Channel %d Interrupt: " + "NYET Received--\n", hc->hc_num); + + /* +@@ -1438,7 +1461,8 @@ + * re-do the CSPLIT immediately on non-periodic + */ + if (hc->do_split && hc->complete_split) { +- if (hc->ep_is_in && (hc->ep_type == DWC_OTG_EP_TYPE_ISOC) && hcd->core_if->dma_enable) { ++ if (hc->ep_is_in && (hc->ep_type == DWC_OTG_EP_TYPE_ISOC) ++ && hcd->core_if->dma_enable) { + qtd->complete_split = 0; + qtd->isoc_split_offset = 0; + if (++qtd->isoc_frame_index == qtd->urb->packet_count) { +@@ -1494,7 +1518,7 @@ + */ + halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NYET); + +- handle_nyet_done: ++handle_nyet_done: + disable_hc_int(hc_regs, nyet); + return 1; + } +@@ -1508,11 +1532,12 @@ + dwc_otg_hc_regs_t * hc_regs, + dwc_otg_qtd_t * qtd) + { +- DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: " ++ DWC_DEBUGPL(DBG_HCDI, "--Host Channel %d Interrupt: " + "Babble Error--\n", hc->hc_num); +- ++ + if (hcd->core_if->dma_desc_enable) { +- dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs, DWC_OTG_HC_XFER_BABBLE_ERR); ++ dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs, ++ DWC_OTG_HC_XFER_BABBLE_ERR); + goto handle_babble_done; + } + +@@ -1526,7 +1551,7 @@ + DWC_OTG_HC_XFER_BABBLE_ERR); + halt_channel(hcd, hc, qtd, halt_status); + } +- ++ + handle_babble_done: + disable_hc_int(hc_regs, bblerr); + return 1; +@@ -1549,13 +1574,13 @@ + + dwc_otg_hcd_urb_t *urb = qtd->urb; + +- DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: " ++ DWC_DEBUGPL(DBG_HCDI, "--Host Channel %d Interrupt: " + "AHB Error--\n", hc->hc_num); + +- hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); +- hcsplt.d32 = dwc_read_reg32(&hc_regs->hcsplt); +- hctsiz.d32 = dwc_read_reg32(&hc_regs->hctsiz); +- hcdma = dwc_read_reg32(&hc_regs->hcdma); ++ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar); ++ hcsplt.d32 = DWC_READ_REG32(&hc_regs->hcsplt); ++ hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz); ++ hcdma = DWC_READ_REG32(&hc_regs->hcdma); + + DWC_ERROR("AHB ERROR, Channel %d\n", hc->hc_num); + DWC_ERROR(" hcchar 0x%08x, hcsplt 0x%08x\n", hcchar.d32, hcsplt.d32); +@@ -1566,45 +1591,44 @@ + DWC_ERROR(" Endpoint: %d, %s\n", + dwc_otg_hcd_get_ep_num(&urb->pipe_info), + (dwc_otg_hcd_is_pipe_in(&urb->pipe_info) ? "IN" : "OUT")); +- + + switch (dwc_otg_hcd_get_pipe_type(&urb->pipe_info)) { +-case UE_CONTROL: +- pipetype = "CONTROL"; +- break; ++ case UE_CONTROL: ++ pipetype = "CONTROL"; ++ break; + case UE_BULK: +- pipetype = "BULK"; +- break; ++ pipetype = "BULK"; ++ break; + case UE_INTERRUPT: +- pipetype = "INTERRUPT"; +- break; ++ pipetype = "INTERRUPT"; ++ break; + case UE_ISOCHRONOUS: +- pipetype = "ISOCHRONOUS"; +- break; ++ pipetype = "ISOCHRONOUS"; ++ break; + default: +- pipetype = "UNKNOWN"; ++ pipetype = "UNKNOWN"; + break; + } +- ++ + DWC_ERROR(" Endpoint type: %s\n", pipetype); + + switch (hc->speed) { + case DWC_OTG_EP_SPEED_HIGH: +- speed = "HIGH"; +- break; ++ speed = "HIGH"; ++ break; + case DWC_OTG_EP_SPEED_FULL: +- speed = "FULL"; +- break; ++ speed = "FULL"; ++ break; + case DWC_OTG_EP_SPEED_LOW: +- speed = "LOW"; +- break; ++ speed = "LOW"; ++ break; + default: +- speed = "UNKNOWN"; ++ speed = "UNKNOWN"; + break; +- }; ++ }; + + DWC_ERROR(" Speed: %s\n", speed); +- ++ + DWC_ERROR(" Max packet size: %d\n", + dwc_otg_hcd_get_mps(&urb->pipe_info)); + DWC_ERROR(" Data buffer length: %d\n", urb->length); +@@ -1616,7 +1640,8 @@ + + /* Core haltes the channel for Descriptor DMA mode */ + if (hcd->core_if->dma_desc_enable) { +- dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs, DWC_OTG_HC_XFER_AHB_ERR); ++ dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs, ++ DWC_OTG_HC_XFER_AHB_ERR); + goto handle_ahberr_done; + } + +@@ -1641,11 +1666,12 @@ + dwc_otg_hc_regs_t * hc_regs, + dwc_otg_qtd_t * qtd) + { +- DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: " ++ DWC_DEBUGPL(DBG_HCDI, "--Host Channel %d Interrupt: " + "Transaction Error--\n", hc->hc_num); + + if (hcd->core_if->dma_desc_enable) { +- dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs, DWC_OTG_HC_XFER_XACT_ERR); ++ dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs, ++ DWC_OTG_HC_XFER_XACT_ERR); + goto handle_xacterr_done; + } + +@@ -1703,7 +1729,7 @@ + dwc_otg_hc_regs_t * hc_regs, + dwc_otg_qtd_t * qtd) + { +- DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: " ++ DWC_DEBUGPL(DBG_HCDI, "--Host Channel %d Interrupt: " + "Frame Overrun--\n", hc->hc_num); + + switch (dwc_otg_hcd_get_pipe_type(&qtd->urb->pipe_info)) { +@@ -1739,7 +1765,7 @@ + dwc_otg_hc_regs_t * hc_regs, + dwc_otg_qtd_t * qtd) + { +- DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: " ++ DWC_DEBUGPL(DBG_HCDI, "--Host Channel %d Interrupt: " + "Data Toggle Error--\n", hc->hc_num); + + if (hc->ep_is_in) { +@@ -1777,11 +1803,11 @@ + * This code is here only as a check. This condition should + * never happen. Ignore the halt if it does occur. + */ +- hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); +- hctsiz.d32 = dwc_read_reg32(&hc_regs->hctsiz); +- hcint.d32 = dwc_read_reg32(&hc_regs->hcint); +- hcintmsk.d32 = dwc_read_reg32(&hc_regs->hcintmsk); +- hcsplt.d32 = dwc_read_reg32(&hc_regs->hcsplt); ++ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar); ++ hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz); ++ hcint.d32 = DWC_READ_REG32(&hc_regs->hcint); ++ hcintmsk.d32 = DWC_READ_REG32(&hc_regs->hcintmsk); ++ hcsplt.d32 = DWC_READ_REG32(&hc_regs->hcsplt); + DWC_WARN + ("%s: hc->halt_status == DWC_OTG_HC_XFER_NO_HALT_STATUS, " + "channel %d, hcchar 0x%08x, hctsiz 0x%08x, " +@@ -1802,7 +1828,7 @@ + * never be set when the halt interrupt occurs. Halt the + * channel again if it does occur. + */ +- hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); ++ hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar); + if (hcchar.b.chdis) { + DWC_WARN("%s: hcchar.chdis set unexpectedly, " + "hcchar 0x%08x, trying to halt again\n", +@@ -1842,7 +1868,8 @@ + } + + if (hc->halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE || +- (hc->halt_status == DWC_OTG_HC_XFER_AHB_ERR && !hcd->core_if->dma_desc_enable)) { ++ (hc->halt_status == DWC_OTG_HC_XFER_AHB_ERR ++ && !hcd->core_if->dma_desc_enable)) { + /* + * Just release the channel. A dequeue can happen on a + * transfer timeout. In the case of an AHB Error, the channel +@@ -1850,15 +1877,16 @@ + * recover. + */ + if (hcd->core_if->dma_desc_enable) +- dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs, hc->halt_status); ++ dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs, ++ hc->halt_status); + else + release_channel(hcd, hc, qtd, hc->halt_status); + return; + } + + /* Read the HCINTn register to determine the cause for the halt. */ +- hcint.d32 = dwc_read_reg32(&hc_regs->hcint); +- hcintmsk.d32 = dwc_read_reg32(&hc_regs->hcintmsk); ++ hcint.d32 = DWC_READ_REG32(&hc_regs->hcint); ++ hcintmsk.d32 = DWC_READ_REG32(&hc_regs->hcintmsk); + + if (hcint.b.xfercomp) { + /** @todo This is here because of a possible hardware bug. Spec +@@ -1891,7 +1919,7 @@ + handle_hc_xacterr_intr(hcd, hc, hc_regs, qtd); + } else if (hcint.b.xcs_xact && hcd->core_if->dma_desc_enable) { + handle_hc_xacterr_intr(hcd, hc, hc_regs, qtd); +- } else if (hcint.b.ahberr && hcd->core_if->dma_desc_enable) { ++ } else if (hcint.b.ahberr && hcd->core_if->dma_desc_enable) { + handle_hc_ahberr_intr(hcd, hc, hc_regs, qtd); + } else if (hcint.b.bblerr) { + handle_hc_babble_intr(hcd, hc, hc_regs, qtd); +@@ -1943,10 +1971,11 @@ + ("%s: Channel %d, DMA Mode -- ChHltd set, but reason " + "for halting is unknown, hcint 0x%08x, intsts 0x%08x\n", + __func__, hc->hc_num, hcint.d32, +- dwc_read_reg32(&hcd->core_if-> +- core_global_regs->gintsts)); ++ DWC_READ_REG32(&hcd-> ++ core_if->core_global_regs-> ++ gintsts)); + } +- ++ + } + } else { + DWC_PRINTF("NYET/NAK/ACK/other in non-error case, 0x%08x\n", +@@ -1970,7 +1999,7 @@ + dwc_otg_hc_regs_t * hc_regs, + dwc_otg_qtd_t * qtd) + { +- DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: " ++ DWC_DEBUGPL(DBG_HCDI, "--Host Channel %d Interrupt: " + "Channel Halted--\n", hc->hc_num); + + if (hcd->core_if->dma_enable) { +@@ -2003,8 +2032,8 @@ + hc_regs = dwc_otg_hcd->core_if->host_if->hc_regs[num]; + qtd = DWC_CIRCLEQ_FIRST(&hc->qh->qtd_list); + +- hcint.d32 = dwc_read_reg32(&hc_regs->hcint); +- hcintmsk.d32 = dwc_read_reg32(&hc_regs->hcintmsk); ++ hcint.d32 = DWC_READ_REG32(&hc_regs->hcint); ++ hcintmsk.d32 = DWC_READ_REG32(&hc_regs->hcintmsk); + DWC_DEBUGPL(DBG_HCDV, + " hcint 0x%08x, hcintmsk 0x%08x, hcint&hcintmsk 0x%08x\n", + hcint.d32, hcintmsk.d32, (hcint.d32 & hcintmsk.d32)); +@@ -2062,4 +2091,4 @@ + return retval; + } + +-#endif /* DWC_DEVICE_ONLY */ ++#endif /* DWC_DEVICE_ONLY */ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c 2013-07-26 19:34:36.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c 2013-07-26 19:34:44.000000000 +0000 +@@ -1,8 +1,8 @@ + /* ========================================================================== + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd_linux.c $ +- * $Revision: #11 $ +- * $Date: 2009/04/21 $ +- * $Change: 1237476 $ ++ * $Revision: #20 $ ++ * $Date: 2011/10/26 $ ++ * $Change: 1872981 $ + * + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless +@@ -50,28 +50,23 @@ + #include + #include + #include +- +-#ifdef LM_INTERFACE +-//#include +-#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30)) +-#include +-#include ++#include ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,35) ++#include <../drivers/usb/core/hcd.h> + #else +-#include +-#include +-#endif +-#elif defined(PLATFORM_INTERFACE) +-#include ++#include + #endif + +-#include +-#include ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,30)) ++#define USB_URB_EP_LINKING 1 ++#else ++#define USB_URB_EP_LINKING 0 ++#endif + + #include "dwc_otg_hcd_if.h" + #include "dwc_otg_dbg.h" + #include "dwc_otg_driver.h" + #include "dwc_otg_hcd.h" +- + /** + * Gets the endpoint number from a _bEndpointAddress argument. The endpoint is + * qualified with its direction (possible 32 endpoints per device). +@@ -84,22 +79,25 @@ + /** @name Linux HC Driver API Functions */ + /** @{ */ + /* manage i/o requests, device state */ +-#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30)) +-static int urb_enqueue(struct usb_hcd *hcd, ++static int dwc_otg_urb_enqueue(struct usb_hcd *hcd, ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28) + struct usb_host_endpoint *ep, ++#endif + struct urb *urb, gfp_t mem_flags); + +-static int urb_dequeue(struct usb_hcd *hcd, struct urb *urb); +-#else +-static int urb_enqueue(struct usb_hcd *hcd, +- struct urb *urb, gfp_t mem_flags); +- +-static int urb_dequeue(struct usb_hcd *hcd, +- struct urb *urb, int status); +-#endif ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30) ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28) ++static int dwc_otg_urb_dequeue(struct usb_hcd *hcd, struct urb *urb); ++#endif ++#else /* kernels at or post 2.6.30 */ ++static int dwc_otg_urb_dequeue(struct usb_hcd *hcd, ++ struct urb *urb, int status); ++#endif /* LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30) */ + + static void endpoint_disable(struct usb_hcd *hcd, struct usb_host_endpoint *ep); +- ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,30) ++static void endpoint_reset(struct usb_hcd *hcd, struct usb_host_endpoint *ep); ++#endif + static irqreturn_t dwc_otg_hcd_irq(struct usb_hcd *hcd); + extern int hcd_start(struct usb_hcd *hcd); + extern void hcd_stop(struct usb_hcd *hcd); +@@ -131,10 +129,12 @@ + //.resume = + .stop = hcd_stop, + +- .urb_enqueue = urb_enqueue, +- .urb_dequeue = urb_dequeue, ++ .urb_enqueue = dwc_otg_urb_enqueue, ++ .urb_dequeue = dwc_otg_urb_dequeue, + .endpoint_disable = endpoint_disable, +- ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,30) ++ .endpoint_reset = endpoint_reset, ++#endif + .get_frame_number = get_frame_number, + + .hub_status_data = hub_status_data, +@@ -264,9 +264,8 @@ + static int _complete(dwc_otg_hcd_t * hcd, void *urb_handle, + dwc_otg_hcd_urb_t * dwc_otg_urb, int32_t status) + { +- uint64_t flags; + struct urb *urb = (struct urb *)urb_handle; +-#ifdef DEBUG ++ + if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) { + DWC_PRINTF("%s: urb %p, device %d, ep %d %s, status=%d\n", + __func__, urb, usb_pipedevice(urb->pipe), +@@ -280,7 +279,6 @@ + } + } + } +-#endif + + urb->actual_length = dwc_otg_hcd_urb_get_actual_length(dwc_otg_urb); + /* Convert status value. */ +@@ -319,8 +317,7 @@ + dwc_otg_hcd_urb_get_iso_desc_actual_length + (dwc_otg_urb, i); + urb->iso_frame_desc[i].status = +- dwc_otg_hcd_urb_get_iso_desc_status +- (dwc_otg_urb, i); ++ dwc_otg_hcd_urb_get_iso_desc_status(dwc_otg_urb, i); + } + } + +@@ -339,21 +336,24 @@ + if (ep) { + free_bus_bandwidth(dwc_otg_hcd_to_hcd(hcd), + dwc_otg_hcd_get_ep_bandwidth(hcd, +- ep-> +- hcpriv), ++ ep->hcpriv), + urb); + } + } + +- dwc_free(dwc_otg_urb); +-#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30)) ++ DWC_FREE(dwc_otg_urb); ++ ++#if USB_URB_EP_LINKING ++ usb_hcd_unlink_urb_from_ep(dwc_otg_hcd_to_hcd(hcd), urb); ++#endif ++ DWC_SPINUNLOCK(hcd->lock); ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28) + usb_hcd_giveback_urb(dwc_otg_hcd_to_hcd(hcd), urb); + #else +- DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags); +- usb_hcd_unlink_urb_from_ep(dwc_otg_hcd_to_hcd(hcd), urb); +- DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags); + usb_hcd_giveback_urb(dwc_otg_hcd_to_hcd(hcd), urb, status); + #endif ++ DWC_SPINLOCK(hcd->lock); ++ + return 0; + } + +@@ -372,26 +372,11 @@ + * USB bus with the core and calls the hc_driver->start() function. It returns + * a negative error on failure. + */ +-int hcd_init( +-#ifdef LM_INTERFACE +- struct lm_device *_dev +-#elif defined(PCI_INTERFACE) +- struct pci_dev *_dev +-#elif defined(PLATFORM_INTERFACE) +- struct platform_device *_dev +-#endif +- ) ++int hcd_init(dwc_bus_dev_t *_dev) + { + struct usb_hcd *hcd = NULL; + dwc_otg_hcd_t *dwc_otg_hcd = NULL; +-#ifdef LM_INTERFACE +- dwc_otg_device_t *otg_dev = lm_get_drvdata(_dev); +-#elif defined(PCI_INTERFACE) +- dwc_otg_device_t *otg_dev = pci_get_drvdata(_dev); +-#elif defined(PLATFORM_INTERFACE) +- dwc_otg_device_t *otg_dev = platform_get_drvdata(_dev); +-#endif +- ++ dwc_otg_device_t *otg_dev = DWC_OTG_BUSDRVDATA(_dev); + int retval = 0; + u64 dmamask; + +@@ -415,21 +400,20 @@ + * Allocate memory for the base HCD plus the DWC OTG HCD. + * Initialize the base HCD. + */ +- hcd = usb_create_hcd(&dwc_otg_hc_driver, &_dev->dev, +-#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30)) +- _dev->dev.bus_id); ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30) ++ hcd = usb_create_hcd(&dwc_otg_hc_driver, &_dev->dev, _dev->dev.bus_id); + #else +- dev_name(&_dev->dev)); ++ hcd = usb_create_hcd(&dwc_otg_hc_driver, &_dev->dev, dev_name(&_dev->dev)); ++ hcd->has_tt = 1; ++// hcd->uses_new_polling = 1; ++// hcd->poll_rh = 0; + #endif + if (!hcd) { + retval = -ENOMEM; + goto error1; + } + +- hcd->regs = otg_dev->base; +- +- /* Integrate TT in root hub */ +- hcd->has_tt = 1; ++ hcd->regs = otg_dev->os_dep.base; + + /* Initialize the DWC OTG HCD. */ + dwc_otg_hcd = dwc_otg_hcd_alloc_hcd(); +@@ -444,17 +428,24 @@ + goto error2; + } + ++ otg_dev->hcd->otg_dev = otg_dev; + hcd->self.otg_port = dwc_otg_hcd_otg_port(dwc_otg_hcd); +- ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,33) //don't support for LM(with 2.6.20.1 kernel) ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,35) //version field absent later ++ hcd->self.otg_version = dwc_otg_get_otg_version(otg_dev->core_if); ++#endif ++ /* Don't support SG list at this point */ ++ hcd->self.sg_tablesize = 0; ++#endif + /* + * Finish generic HCD initialization and start the HCD. This function + * allocates the DMA buffer pool, registers the USB bus, requests the + * IRQ line, and calls hcd_start method. + */ + #ifdef PLATFORM_INTERFACE +- retval = usb_add_hcd(hcd, platform_get_irq(_dev, 0), IRQF_SHARED); ++ retval = usb_add_hcd(hcd, platform_get_irq(_dev, 0), IRQF_SHARED | IRQF_DISABLED); + #else +- retval = usb_add_hcd(hcd, _dev->irq, IRQF_SHARED); ++ retval = usb_add_hcd(hcd, _dev->irq, IRQF_SHARED | IRQF_DISABLED); + #endif + if (retval < 0) { + goto error2; +@@ -463,9 +454,9 @@ + dwc_otg_hcd_set_priv_data(dwc_otg_hcd, hcd); + return 0; + +- error2: ++error2: + usb_put_hcd(hcd); +- error1: ++error1: + return retval; + } + +@@ -473,24 +464,9 @@ + * Removes the HCD. + * Frees memory and resources associated with the HCD and deregisters the bus. + */ +-void hcd_remove( +-#ifdef LM_INTERFACE +- struct lm_device *_dev +-#elif defined(PCI_INTERFACE) +- struct pci_dev *_dev +-#elif defined(PLATFORM_INTERFACE) +- struct platform_device *_dev +-#endif +- ) ++void hcd_remove(dwc_bus_dev_t *_dev) + { +-#ifdef LM_INTERFACE +- dwc_otg_device_t *otg_dev = lm_get_drvdata(_dev); +-#elif defined(PCI_INTERFACE) +- dwc_otg_device_t *otg_dev = pci_get_drvdata(_dev); +-#elif defined(PLATFORM_INTERFACE) +- dwc_otg_device_t *otg_dev = platform_get_drvdata(_dev); +-#endif +- ++ dwc_otg_device_t *otg_dev = DWC_OTG_BUSDRVDATA(_dev); + dwc_otg_hcd_t *dwc_otg_hcd; + struct usb_hcd *hcd; + +@@ -616,26 +592,25 @@ + } + } + } +- + #endif + + /** Starts processing a USB transfer request specified by a USB Request Block + * (URB). mem_flags indicates the type of memory allocation to use while + * processing this URB. */ +-#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30)) +-static int urb_enqueue(struct usb_hcd *hcd, ++static int dwc_otg_urb_enqueue(struct usb_hcd *hcd, ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28) + struct usb_host_endpoint *ep, ++#endif + struct urb *urb, gfp_t mem_flags) + { +-#else +-static int urb_enqueue(struct usb_hcd *hcd, +- struct urb *urb, +- gfp_t mem_flags) +-{ +- struct usb_host_endpoint *ep = urb->ep; ++ int retval = 0; ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,28) ++ struct usb_host_endpoint *ep = urb->ep; ++#endif ++#if USB_URB_EP_LINKING ++ dwc_irqflags_t irqflags; + #endif + void **ref_ep_hcpriv = &ep->hcpriv; +- int retval = 0; + dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd); + dwc_otg_hcd_urb_t *dwc_otg_urb; + int i; +@@ -646,7 +621,7 @@ + + #ifdef DEBUG + if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) { +- dump_urb_info(urb, "urb_enqueue"); ++ dump_urb_info(urb, "dwc_otg_urb_enqueue"); + } + #endif + +@@ -675,9 +650,10 @@ + ep_type = USB_ENDPOINT_XFER_INT; + break; + default: +- DWC_WARN("Wrong ep type\n"); ++ DWC_WARN("Wrong EP type - %d\n", usb_pipetype(urb->pipe)); + } + ++ /* # of packets is often 0 - do we really need to call this then? */ + dwc_otg_urb = dwc_otg_hcd_urb_alloc(dwc_otg_hcd, + urb->number_of_packets, + mem_flags == GFP_ATOMIC ? 1 : 0); +@@ -686,6 +662,8 @@ + return -ENOMEM; + + urb->hcpriv = dwc_otg_urb; ++ if (!dwc_otg_urb && urb->number_of_packets) ++ return -ENOMEM; + + dwc_otg_hcd_urb_set_pipeinfo(dwc_otg_urb, usb_pipedevice(urb->pipe), + usb_pipeendpoint(urb->pipe), ep_type, +@@ -705,7 +683,7 @@ + // DMA addresses are bus addresses not physical addresses! + buf = dma_to_virt(&urb->dev->dev, urb->transfer_dma); + } +- ++ + if (!(urb->transfer_flags & URB_NO_INTERRUPT)) + flags |= URB_GIVEBACK_ASAP; + if (urb->transfer_flags & URB_ZERO_PACKET) +@@ -714,27 +692,28 @@ + dwc_otg_hcd_urb_set_params(dwc_otg_urb, urb, buf, + urb->transfer_dma, + urb->transfer_buffer_length, +- urb->setup_packet, +- urb->setup_dma, +- flags, +- urb->interval); ++ urb->setup_packet, ++ urb->setup_dma, flags, urb->interval); + + for (i = 0; i < urb->number_of_packets; ++i) { + dwc_otg_hcd_urb_set_iso_desc_params(dwc_otg_urb, i, +- urb->iso_frame_desc[i]. +- offset, +- urb->iso_frame_desc[i]. +- length); ++ urb-> ++ iso_frame_desc[i].offset, ++ urb-> ++ iso_frame_desc[i].length); + } + +-#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,30)) ++#if USB_URB_EP_LINKING ++ DWC_SPINLOCK_IRQSAVE(dwc_otg_hcd->lock, &irqflags); + retval = usb_hcd_link_urb_to_ep(hcd, urb); ++ DWC_SPINUNLOCK_IRQRESTORE(dwc_otg_hcd->lock, irqflags); + if (0 == retval) + #endif + { + retval = dwc_otg_hcd_urb_enqueue(dwc_otg_hcd, dwc_otg_urb, + /*(dwc_otg_qh_t **)*/ +- ref_ep_hcpriv); ++ ref_ep_hcpriv, ++ mem_flags == GFP_ATOMIC ? 1 : 0); + if (0 == retval) { + if (alloc_bandwidth) { + allocate_bus_bandwidth(hcd, +@@ -743,8 +722,12 @@ + urb); + } + } else { +-#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,30)) ++#if USB_URB_EP_LINKING ++ dwc_irqflags_t irqflags; ++ DWC_DEBUGPL(DBG_HCD, "DWC OTG dwc_otg_hcd_urb_enqueue failed rc %d\n", retval); ++ DWC_SPINLOCK_IRQSAVE(dwc_otg_hcd->lock, &irqflags); + usb_hcd_unlink_urb_from_ep(hcd, urb); ++ DWC_SPINUNLOCK_IRQRESTORE(dwc_otg_hcd->lock, irqflags); + #endif + if (retval == -DWC_E_NO_DEVICE) { + retval = -ENODEV; +@@ -756,54 +739,61 @@ + + /** Aborts/cancels a USB transfer request. Always returns 0 to indicate + * success. */ +-#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30)) +-static int urb_dequeue(struct usb_hcd *hcd, struct urb *urb) ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28) ++static int dwc_otg_urb_dequeue(struct usb_hcd *hcd, struct urb *urb) + #else +-static int urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status) ++static int dwc_otg_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status) + #endif + { +- int rc; +- uint64_t flags; ++ dwc_irqflags_t flags; + dwc_otg_hcd_t *dwc_otg_hcd; ++ int rc; ++ + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD URB Dequeue\n"); + + dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd); + + #ifdef DEBUG + if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) { +- dump_urb_info(urb, "urb_dequeue"); ++ dump_urb_info(urb, "dwc_otg_urb_dequeue"); + } + #endif +- if(urb->hcpriv != NULL) { +- dwc_otg_hcd_urb_dequeue(dwc_otg_hcd, (dwc_otg_hcd_urb_t *)urb->hcpriv); + +- dwc_free(urb->hcpriv); +- urb->hcpriv = NULL; +- } +- +- /* Higher layer software sets URB status. */ +-#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30)) +- usb_hcd_giveback_urb(hcd, urb); +-#else + DWC_SPINLOCK_IRQSAVE(dwc_otg_hcd->lock, &flags); + rc = usb_hcd_check_unlink_urb(hcd, urb, status); +- if(!rc) +- { +- usb_hcd_unlink_urb_from_ep(hcd, urb); +- } ++ if (0 == rc) { ++ if(urb->hcpriv != NULL) { ++ dwc_otg_hcd_urb_dequeue(dwc_otg_hcd, ++ (dwc_otg_hcd_urb_t *)urb->hcpriv); ++ ++ DWC_FREE(urb->hcpriv); ++ urb->hcpriv = NULL; ++ } ++ } + +- DWC_SPINUNLOCK_IRQRESTORE(dwc_otg_hcd->lock, flags); +- if (!rc) +- { +- usb_hcd_giveback_urb(hcd, urb, status); +- } ++ if (0 == rc) { ++ /* Higher layer software sets URB status. */ ++#if USB_URB_EP_LINKING ++ usb_hcd_unlink_urb_from_ep(hcd, urb); ++#endif ++ DWC_SPINUNLOCK_IRQRESTORE(dwc_otg_hcd->lock, flags); ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28) ++ usb_hcd_giveback_urb(hcd, urb); ++#else ++ usb_hcd_giveback_urb(hcd, urb, status); + #endif +- if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) { +- DWC_PRINTF("Called usb_hcd_giveback_urb()\n"); +- DWC_PRINTF(" urb->status = %d\n", urb->status); +- } +- +- return 0; ++ if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) { ++ DWC_PRINTF("Called usb_hcd_giveback_urb() \n"); ++ DWC_PRINTF(" 1urb->status = %d\n", urb->status); ++ } ++ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD URB Dequeue OK\n"); ++ } else { ++ DWC_SPINUNLOCK_IRQRESTORE(dwc_otg_hcd->lock, flags); ++ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD URB Dequeue failed - rc %d\n", ++ rc); ++ } ++ ++ return rc; + } + + /* Frees resources in the DWC_otg controller related to a given endpoint. Also +@@ -821,6 +811,38 @@ + ep->hcpriv = NULL; + } + ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,30) ++/* Resets endpoint specific parameter values, in current version used to reset ++ * the data toggle(as a WA). This function can be called from usb_clear_halt routine */ ++static void endpoint_reset(struct usb_hcd *hcd, struct usb_host_endpoint *ep) ++{ ++ dwc_irqflags_t flags; ++ struct usb_device *udev = NULL; ++ int epnum = usb_endpoint_num(&ep->desc); ++ int is_out = usb_endpoint_dir_out(&ep->desc); ++ int is_control = usb_endpoint_xfer_control(&ep->desc); ++ dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd); ++ struct device *dev = DWC_OTG_OS_GETDEV(dwc_otg_hcd->otg_dev->os_dep); ++ ++ if (dev) ++ udev = to_usb_device(dev); ++ else ++ return; ++ ++ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD EP RESET: Endpoint Num=0x%02d\n", epnum); ++ ++ DWC_SPINLOCK_IRQSAVE(dwc_otg_hcd->lock, &flags); ++ usb_settoggle(udev, epnum, is_out, 0); ++ if (is_control) ++ usb_settoggle(udev, epnum, !is_out, 0); ++ ++ if (ep->hcpriv) { ++ dwc_otg_hcd_endpoint_reset(dwc_otg_hcd, ep->hcpriv); ++ } ++ DWC_SPINUNLOCK_IRQRESTORE(dwc_otg_hcd->lock, flags); ++} ++#endif ++ + /** Handles host mode interrupts for the DWC_otg controller. Returns IRQ_NONE if + * there was no interrupt to handle. Returns IRQ_HANDLED if there was a valid + * interrupt. +@@ -868,4 +890,4 @@ + return retval; + } + +-#endif /* DWC_DEVICE_ONLY */ ++#endif /* DWC_DEVICE_ONLY */ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_hcd_queue.c +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/dwc_otg_hcd_queue.c 2013-07-26 19:31:23.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_hcd_queue.c 2013-07-26 19:34:44.000000000 +0000 +@@ -1,8 +1,8 @@ + /* ========================================================================== + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd_queue.c $ +- * $Revision: #39 $ +- * $Date: 2009/04/21 $ +- * $Change: 1237477 $ ++ * $Revision: #44 $ ++ * $Date: 2011/10/26 $ ++ * $Change: 1873028 $ + * + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless +@@ -52,33 +52,30 @@ + */ + void dwc_otg_hcd_qh_free(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh) + { ++ dwc_irqflags_t flags; + dwc_otg_qtd_t *qtd, *qtd_tmp; +- uint64_t flags; + + /* Free each QTD in the QTD list */ +- DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags); ++ DWC_SPINLOCK_IRQSAVE(hcd->lock,&flags); + DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp, &qh->qtd_list, qtd_list_entry) { + DWC_CIRCLEQ_REMOVE(&qh->qtd_list, qtd, qtd_list_entry); + dwc_otg_hcd_qtd_free(qtd); + } +- DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags); + + if (hcd->core_if->dma_desc_enable) { + dwc_otg_hcd_qh_free_ddma(hcd, qh); +- } +- else if (qh->dw_align_buf) { ++ } else if (qh->dw_align_buf) { + uint32_t buf_size; +- if(qh->ep_type == UE_ISOCHRONOUS) { ++ if (qh->ep_type == UE_ISOCHRONOUS) { + buf_size = 4096; + } else { + buf_size = hcd->core_if->core_params->max_transfer_size; + } +- dwc_dma_free(buf_size, qh->dw_align_buf, qh->dw_align_buf_dma); ++ DWC_DMA_FREE(buf_size, qh->dw_align_buf, qh->dw_align_buf_dma); + } +- +- +- +- dwc_free(qh); ++ ++ DWC_FREE(qh); ++ DWC_SPINUNLOCK_IRQRESTORE(hcd->lock,flags); + return; + } + +@@ -89,8 +86,7 @@ + #define NS_TO_US(ns) ((ns + 500) / 1000) + /* convert & round nanoseconds to microseconds */ + +-static uint32_t calc_bus_time(int speed, int is_in, int is_isoc, +- int bytecount) ++static uint32_t calc_bus_time(int speed, int is_in, int is_isoc, int bytecount) + { + unsigned long retval; + +@@ -144,7 +140,7 @@ + DWC_WARN("Unknown device speed\n"); + retval = -1; + } +- ++ + return NS_TO_US(retval); + } + +@@ -157,18 +153,16 @@ + * to initialize the QH. + */ + #define SCHEDULE_SLOP 10 +-void qh_init(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh, +- dwc_otg_hcd_urb_t * urb) ++void qh_init(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh, dwc_otg_hcd_urb_t * urb) + { + char *speed, *type; + int dev_speed; + uint32_t hub_addr, hub_port; + + dwc_memset(qh, 0, sizeof(dwc_otg_qh_t)); +- ++ + /* Initialize QH */ + qh->ep_type = dwc_otg_hcd_get_pipe_type(&urb->pipe_info); +- + qh->ep_is_in = dwc_otg_hcd_is_pipe_in(&urb->pipe_info) ? 1 : 0; + + qh->data_toggle = DWC_OTG_HC_PID_DATA0; +@@ -180,17 +174,17 @@ + /* FS/LS Enpoint on HS Hub + * NOT virtual root hub */ + dev_speed = hcd->fops->speed(hcd, urb->priv); ++ + hcd->fops->hub_info(hcd, urb->priv, &hub_addr, &hub_port); + qh->do_split = 0; ++ + if (((dev_speed == USB_SPEED_LOW) || + (dev_speed == USB_SPEED_FULL)) && + (hub_addr != 0 && hub_addr != 1)) { +- + DWC_DEBUGPL(DBG_HCD, + "QH init: EP %d: TT found at hub addr %d, for port %d\n", + dwc_otg_hcd_get_ep_num(&urb->pipe_info), hub_addr, + hub_port); +- + qh->do_split = 1; + } + +@@ -202,22 +196,22 @@ + int bytecount = + dwc_hb_mult(qh->maxp) * dwc_max_packet(qh->maxp); + +- qh->usecs = calc_bus_time((qh->do_split ? USB_SPEED_HIGH : dev_speed), +- qh->ep_is_in, +- (qh->ep_type == UE_ISOCHRONOUS), +- bytecount); ++ qh->usecs = ++ calc_bus_time((qh->do_split ? USB_SPEED_HIGH : dev_speed), ++ qh->ep_is_in, (qh->ep_type == UE_ISOCHRONOUS), ++ bytecount); + /* Start in a slightly future (micro)frame. */ + qh->sched_frame = dwc_frame_num_inc(hcd->frame_number, + SCHEDULE_SLOP); + qh->interval = urb->interval; +- ++ + #if 0 + /* Increase interrupt polling rate for debugging. */ + if (qh->ep_type == UE_INTERRUPT) { + qh->interval = 8; + } + #endif +- hprt.d32 = dwc_read_reg32(hcd->core_if->host_if->hprt0); ++ hprt.d32 = DWC_READ_REG32(hcd->core_if->host_if->hprt0); + if ((hprt.b.prtspd == DWC_HPRT0_PRTSPD_HIGH_SPEED) && + ((dev_speed == USB_SPEED_LOW) || + (dev_speed == USB_SPEED_FULL))) { +@@ -271,7 +265,7 @@ + type = "?"; + break; + } +- ++ + DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - Type = %s\n", type); + + #ifdef DEBUG +@@ -291,27 +285,30 @@ + * @param hcd The HCD state structure for the DWC OTG controller. + * @param urb Holds the information about the device/endpoint that we need + * to initialize the QH. ++ * @param atomic_alloc Flag to do atomic allocation if needed + * + * @return Returns pointer to the newly allocated QH, or NULL on error. */ + dwc_otg_qh_t *dwc_otg_hcd_qh_create(dwc_otg_hcd_t * hcd, +- dwc_otg_hcd_urb_t * urb) ++ dwc_otg_hcd_urb_t * urb, int atomic_alloc) + { + dwc_otg_qh_t *qh; + + /* Allocate memory */ + /** @todo add memflags argument */ +- qh = dwc_otg_hcd_qh_alloc(); ++ qh = dwc_otg_hcd_qh_alloc(atomic_alloc); + if (qh == NULL) { ++ DWC_ERROR("qh allocation failed"); + return NULL; + } + + qh_init(hcd, qh, urb); +- +- if (hcd->core_if->dma_desc_enable && (dwc_otg_hcd_qh_init_ddma(hcd, qh) < 0)) { +- dwc_otg_hcd_qh_free(hcd, qh); ++ ++ if (hcd->core_if->dma_desc_enable ++ && (dwc_otg_hcd_qh_init_ddma(hcd, qh) < 0)) { ++ dwc_otg_hcd_qh_free(hcd, qh); + return NULL; + } +- ++ + return qh; + } + +@@ -331,8 +328,8 @@ + int num_channels; + + num_channels = hcd->core_if->core_params->host_channels; +- if ((hcd->periodic_channels + hcd->non_periodic_channels < num_channels) && +- (hcd->periodic_channels < num_channels - 1)) { ++ if ((hcd->periodic_channels + hcd->non_periodic_channels < num_channels) ++ && (hcd->periodic_channels < num_channels - 1)) { + status = 0; + } else { + DWC_INFO("%s: Total channels: %d, Periodic: %d, Non-periodic: %d\n", +@@ -472,13 +469,11 @@ + int dwc_otg_hcd_qh_add(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh) + { + int status = 0; +- uint64_t flags; +- +- DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags); ++ gintmsk_data_t intr_mask = {.d32 = 0 }; + + if (!DWC_LIST_EMPTY(&qh->qh_list_entry)) { + /* QH already in a schedule. */ +- goto done; ++ return status; + } + + /* Add the new QH to the appropriate schedule */ +@@ -488,11 +483,14 @@ + &qh->qh_list_entry); + } else { + status = schedule_periodic(hcd, qh); ++ if ( !hcd->periodic_qh_count ) { ++ intr_mask.b.sofintr = 1; ++ DWC_MODIFY_REG32(&hcd->core_if->core_global_regs->gintmsk, ++ intr_mask.d32, intr_mask.d32); ++ } ++ hcd->periodic_qh_count++; + } + +- done: +- DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags); +- + return status; + } + +@@ -521,12 +519,11 @@ + * @param qh QH to remove from schedule. */ + void dwc_otg_hcd_qh_remove(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh) + { +- uint64_t flags; +- DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags); ++ gintmsk_data_t intr_mask = {.d32 = 0 }; + + if (DWC_LIST_EMPTY(&qh->qh_list_entry)) { + /* QH is not in a schedule. */ +- goto done; ++ return; + } + + if (dwc_qh_is_non_per(qh)) { +@@ -537,10 +534,13 @@ + DWC_LIST_REMOVE_INIT(&qh->qh_list_entry); + } else { + deschedule_periodic(hcd, qh); ++ hcd->periodic_qh_count--; ++ if( !hcd->periodic_qh_count ) { ++ intr_mask.b.sofintr = 1; ++ DWC_MODIFY_REG32(&hcd->core_if->core_global_regs->gintmsk, ++ intr_mask.d32, 0); ++ } + } +- +- done: +- DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags); + } + + /** +@@ -558,10 +558,7 @@ + */ + void dwc_otg_hcd_qh_deactivate(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh, + int sched_next_periodic_split) +-{ +- uint64_t flags; +- DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags); +- ++{ + if (dwc_qh_is_non_per(qh)) { + dwc_otg_hcd_qh_remove(hcd, qh); + if (!DWC_CIRCLEQ_EMPTY(&qh->qtd_list)) { +@@ -577,9 +574,9 @@ + + qh->sched_frame = frame_number; + if (dwc_frame_num_le(frame_number, +- dwc_frame_num_inc(qh-> +- start_split_frame, +- 1))) { ++ dwc_frame_num_inc ++ (qh->start_split_frame, ++ 1))) { + /* + * Allow one frame to elapse after start + * split microframe before scheduling +@@ -623,14 +620,12 @@ + DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_ready, + &qh->qh_list_entry); + } else { +- DWC_LIST_MOVE_HEAD(&hcd-> +- periodic_sched_inactive, +- &qh->qh_list_entry); ++ DWC_LIST_MOVE_HEAD ++ (&hcd->periodic_sched_inactive, ++ &qh->qh_list_entry); + } + } + } +- +- DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags); + } + + /** +@@ -638,13 +633,14 @@ + * + * @param urb The URB to create a QTD from. Each URB-QTD pair will end up + * pointing to each other so each pair should have a unique correlation. ++ * @param atomic_alloc Flag to do atomic alloc if needed + * + * @return Returns pointer to the newly allocated QTD, or NULL on error. */ +-dwc_otg_qtd_t *dwc_otg_hcd_qtd_create(dwc_otg_hcd_urb_t * urb) ++dwc_otg_qtd_t *dwc_otg_hcd_qtd_create(dwc_otg_hcd_urb_t * urb, int atomic_alloc) + { + dwc_otg_qtd_t *qtd; + +- qtd = dwc_otg_hcd_qtd_alloc(); ++ qtd = dwc_otg_hcd_qtd_alloc(atomic_alloc); + if (qtd == NULL) { + return NULL; + } +@@ -692,41 +688,40 @@ + * @param[in] qtd The QTD to add + * @param[in] hcd The DWC HCD structure + * @param[out] qh out parameter to return queue head ++ * @param atomic_alloc Flag to do atomic alloc if needed + * + * @return 0 if successful, negative error code otherwise. + */ + int dwc_otg_hcd_qtd_add(dwc_otg_qtd_t * qtd, +- dwc_otg_hcd_t * hcd, dwc_otg_qh_t ** qh) ++ dwc_otg_hcd_t * hcd, dwc_otg_qh_t ** qh, int atomic_alloc) + { + int retval = 0; +- uint64_t flags; ++ dwc_irqflags_t flags; + + dwc_otg_hcd_urb_t *urb = qtd->urb; + +- DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags); +- + /* + * Get the QH which holds the QTD-list to insert to. Create QH if it + * doesn't exist. + */ + if (*qh == NULL) { +- *qh = dwc_otg_hcd_qh_create(hcd, urb); ++ *qh = dwc_otg_hcd_qh_create(hcd, urb, atomic_alloc); + if (*qh == NULL) { + retval = -1; + goto done; + } + } +- ++ DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags); + retval = dwc_otg_hcd_qh_add(hcd, *qh); + if (retval == 0) { + DWC_CIRCLEQ_INSERT_TAIL(&((*qh)->qtd_list), qtd, + qtd_list_entry); + } +- +- done: + DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags); + ++done: ++ + return retval; + } + +-#endif /* DWC_DEVICE_ONLY */ ++#endif /* DWC_DEVICE_ONLY */ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_os_dep.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_os_dep.h 2013-07-26 19:34:44.000000000 +0000 +@@ -0,0 +1,185 @@ ++#ifndef _DWC_OS_DEP_H_ ++#define _DWC_OS_DEP_H_ ++ ++/** ++ * @file ++ * ++ * This file contains OS dependent structures. ++ * ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20) ++# include ++#endif ++ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,21) ++# include ++#else ++# include ++#endif ++ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,24) ++# include ++#else ++# include ++#endif ++ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) ++# include ++#endif ++ ++#ifdef PCI_INTERFACE ++# include ++#endif ++ ++#ifdef LM_INTERFACE ++# include ++# include ++# include ++# include ++# if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30)) ++# include ++# include ++# include ++# include ++# else ++/* in 2.6.31, at least, we seem to have lost the generic LM infrastructure - ++ here we assume that the machine architecture provides definitions ++ in its own header ++*/ ++# include ++# include ++# endif ++#endif ++ ++#ifdef PLATFORM_INTERFACE ++#include ++#include ++#endif ++ ++/** The OS page size */ ++#define DWC_OS_PAGE_SIZE PAGE_SIZE ++ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,14) ++typedef int gfp_t; ++#endif ++ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18) ++# define IRQF_SHARED SA_SHIRQ ++#endif ++ ++typedef struct os_dependent { ++ /** Base address returned from ioremap() */ ++ void *base; ++ ++ /** Register offset for Diagnostic API */ ++ uint32_t reg_offset; ++ ++#ifdef LM_INTERFACE ++ struct lm_device *lmdev; ++#elif defined(PCI_INTERFACE) ++ struct pci_dev *pcidev; ++ ++ /** Start address of a PCI region */ ++ resource_size_t rsrc_start; ++ ++ /** Length address of a PCI region */ ++ resource_size_t rsrc_len; ++#elif defined(PLATFORM_INTERFACE) ++ struct platform_device *platformdev; ++#endif ++ ++} os_dependent_t; ++ ++#ifdef __cplusplus ++} ++#endif ++ ++ ++ ++/* Type for the our device on the chosen bus */ ++#if defined(LM_INTERFACE) ++typedef struct lm_device dwc_bus_dev_t; ++#elif defined(PCI_INTERFACE) ++typedef struct pci_dev dwc_bus_dev_t; ++#elif defined(PLATFORM_INTERFACE) ++typedef struct platform_device dwc_bus_dev_t; ++#endif ++ ++/* Helper macro to retrieve drvdata from the device on the chosen bus */ ++#if defined(LM_INTERFACE) ++#define DWC_OTG_BUSDRVDATA(_dev) lm_get_drvdata(_dev) ++#elif defined(PCI_INTERFACE) ++#define DWC_OTG_BUSDRVDATA(_dev) pci_get_drvdata(_dev) ++#elif defined(PLATFORM_INTERFACE) ++#define DWC_OTG_BUSDRVDATA(_dev) platform_get_drvdata(_dev) ++#endif ++ ++/** ++ * Helper macro returning the otg_device structure of a given struct device ++ * ++ * c.f. static dwc_otg_device_t *dwc_otg_drvdev(struct device *_dev) ++ */ ++#ifdef LM_INTERFACE ++#define DWC_OTG_GETDRVDEV(_var, _dev) do { \ ++ struct lm_device *lm_dev = \ ++ container_of(_dev, struct lm_device, dev); \ ++ _var = lm_get_drvdata(lm_dev); \ ++ } while (0) ++ ++#elif defined(PCI_INTERFACE) ++#define DWC_OTG_GETDRVDEV(_var, _dev) do { \ ++ _var = dev_get_drvdata(_dev); \ ++ } while (0) ++ ++#elif defined(PLATFORM_INTERFACE) ++#define DWC_OTG_GETDRVDEV(_var, _dev) do { \ ++ struct platform_device *platform_dev = \ ++ container_of(_dev, struct platform_device, dev); \ ++ _var = platform_get_drvdata(platform_dev); \ ++ } while (0) ++#endif ++ ++ ++/** ++ * Helper macro returning the struct dev of the given struct os_dependent ++ * ++ * c.f. static struct device *dwc_otg_getdev(struct os_dependent *osdep) ++ */ ++#ifdef LM_INTERFACE ++#define DWC_OTG_OS_GETDEV(_osdep) \ ++ ((_osdep).lmdev == NULL? NULL: &(_osdep).lmdev->dev) ++#elif defined(PCI_INTERFACE) ++#define DWC_OTG_OS_GETDEV(_osdep) \ ++ ((_osdep).pci_dev == NULL? NULL: &(_osdep).pci_dev->dev) ++#elif defined(PLATFORM_INTERFACE) ++#define DWC_OTG_OS_GETDEV(_osdep) \ ++ ((_osdep).platformdev == NULL? NULL: &(_osdep).platformdev->dev) ++#endif ++ ++ ++ ++ ++#endif /* _DWC_OS_DEP_H_ */ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_pcd.c +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/dwc_otg_pcd.c 2013-07-26 19:31:23.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_pcd.c 2013-07-26 19:34:44.000000000 +0000 +@@ -1,8 +1,8 @@ + /* ========================================================================== + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_pcd.c $ +- * $Revision: #79 $ +- * $Date: 2009/04/10 $ +- * $Change: 1230501 $ ++ * $Revision: #99 $ ++ * $Date: 2011/10/24 $ ++ * $Change: 1871160 $ + * + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless +@@ -33,7 +33,7 @@ + #ifndef DWC_HOST_ONLY + + /** @file +- * This file implements PCD Core. All code in this file is portable and don't ++ * This file implements PCD Core. All code in this file is portable and doesn't + * use any OS specific functions. + * PCD Core provides Interface, defined in + * header file, which can be used to implement OS specific PCD interface. +@@ -56,6 +56,9 @@ + extern int init_cfi(cfiobject_t * cfiobj); + #endif + ++/** ++ * Choose endpoint from ep arrays using usb_ep structure. ++ */ + static dwc_otg_pcd_ep_t *get_ep_from_handle(dwc_otg_pcd_t * pcd, void *handle) + { + int i; +@@ -79,23 +82,22 @@ + int32_t status) + { + unsigned stopped = ep->stopped; +- +- DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, ep); ++ ++ DWC_DEBUGPL(DBG_PCDV, "%s(ep %p req %p)\n", __func__, ep, req); + DWC_CIRCLEQ_REMOVE_INIT(&ep->queue, req, queue_entry); + + /* don't modify queue heads during completion callback */ + ep->stopped = 1; +- DWC_SPINUNLOCK(ep->pcd->lock); ++ /* spin_unlock/spin_lock now done in fops->complete() */ + ep->pcd->fops->complete(ep->pcd, ep->priv, req->priv, status, + req->actual); +- DWC_SPINLOCK(ep->pcd->lock); + + if (ep->pcd->request_pending > 0) { + --ep->pcd->request_pending; + } + + ep->stopped = stopped; +- dwc_free(req); ++ DWC_FREE(req); + } + + /** +@@ -129,12 +131,15 @@ + static int32_t dwc_otg_pcd_start_cb(void *p) + { + dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *) p; ++ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); + + /* + * Initialized the Core for Device mode. + */ +- if (dwc_otg_is_device_mode(GET_CORE_IF(pcd))) { +- dwc_otg_core_dev_init(GET_CORE_IF(pcd)); ++ if (dwc_otg_is_device_mode(core_if)) { ++ dwc_otg_core_dev_init(core_if); ++ /* Set core_if's lock pointer to the pcd->lock */ ++ core_if->lock = pcd->lock; + } + return 1; + } +@@ -146,6 +151,11 @@ + { + dwc_otg_pcd_ep_t *ep; + ep = get_ep_from_handle(pcd, pep); ++ if (!ep) { ++ DWC_WARN("bad ep\n"); ++ return -DWC_E_INVALID; ++ } ++ + return pcd->cfi->ops.ep_alloc_buf(pcd->cfi, pcd, ep, addr, buflen, + flags); + } +@@ -173,7 +183,7 @@ + || (!GET_CORE_IF(pcd)->core_params->i2c_enable)) { + if (GET_CORE_IF(pcd)->srp_timer_started) { + GET_CORE_IF(pcd)->srp_timer_started = 0; +- DWC_TIMER_CANCEL(pcd->srp_timer); ++ DWC_TIMER_CANCEL(GET_CORE_IF(pcd)->srp_timer); + } + } + return 1; +@@ -189,7 +199,9 @@ + dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *) p; + + if (pcd->fops->suspend) { ++ DWC_SPINUNLOCK(pcd->lock); + pcd->fops->suspend(pcd); ++ DWC_SPINLOCK(pcd->lock); + } + + return 1; +@@ -222,14 +234,14 @@ + }; + + /** +- * This function allocates a DMA Descriptor chain for the Endpoint ++ * This function allocates a DMA Descriptor chain for the Endpoint + * buffer to be used for a transfer to/from the specified endpoint. + */ +-dwc_otg_dev_dma_desc_t *dwc_otg_ep_alloc_desc_chain(uint32_t * dma_desc_addr, +- uint32_t count) ++dwc_otg_dev_dma_desc_t *dwc_otg_ep_alloc_desc_chain(dwc_dma_t * dma_desc_addr, ++ uint32_t count) + { +- +- return dwc_dma_alloc(count * sizeof(dwc_otg_dev_dma_desc_t), dma_desc_addr); ++ return DWC_DMA_ALLOC_ATOMIC(count * sizeof(dwc_otg_dev_dma_desc_t), ++ dma_desc_addr); + } + + /** +@@ -238,7 +250,7 @@ + void dwc_otg_ep_free_desc_chain(dwc_otg_dev_dma_desc_t * desc_addr, + uint32_t dma_desc_addr, uint32_t count) + { +- dwc_dma_free(count * sizeof(dwc_otg_dev_dma_desc_t), desc_addr, ++ DWC_DMA_FREE(count * sizeof(dwc_otg_dev_dma_desc_t), desc_addr, + dma_desc_addr); + } + +@@ -259,6 +271,7 @@ + depctl_data_t depctl = {.d32 = 0 }; + volatile uint32_t *addr; + int i, j; ++ uint32_t len; + + if (dwc_ep->is_in) + dwc_ep->desc_cnt = dwc_ep->buf_proc_intrvl / dwc_ep->bInterval; +@@ -276,7 +289,7 @@ + return; + } + +- dsts.d32 = dwc_read_reg32(&core_if->dev_if->dev_global_regs->dsts); ++ dsts.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts); + + /** ISO OUT EP */ + if (dwc_ep->is_in == 0) { +@@ -289,7 +302,7 @@ + int offset; + + addr = &core_if->dev_if->out_ep_regs[dwc_ep->num]->doepctl; +- dma_ad = (dma_addr_t) dwc_read_reg32(&(out_regs->doepdma)); ++ dma_ad = (dma_addr_t) DWC_READ_REG32(&(out_regs->doepdma)); + + /** Buffer 0 descriptors setup */ + dma_ad = dwc_ep->dma_addr0; +@@ -307,16 +320,17 @@ + i += dwc_ep->pkt_per_frm) { + + for (j = 0; j < dwc_ep->pkt_per_frm; ++j) { +- data_per_desc = +- ((j + 1) * dwc_ep->maxpacket > +- dwc_ep->data_per_frame) ? dwc_ep-> +- data_per_frame - +- j * dwc_ep->maxpacket : dwc_ep->maxpacket; +- +- data_per_desc += +- (data_per_desc % 4) ? (4 - +- data_per_desc % +- 4) : 0; ++ uint32_t len = (j + 1) * dwc_ep->maxpacket; ++ if (len > dwc_ep->data_per_frame) ++ data_per_desc = ++ dwc_ep->data_per_frame - ++ j * dwc_ep->maxpacket; ++ else ++ data_per_desc = dwc_ep->maxpacket; ++ len = data_per_desc % 4; ++ if (len) ++ data_per_desc += 4 - len; ++ + sts.b_iso_out.rxbytes = data_per_desc; + dma_desc->buf = dma_ad; + dma_desc->status.d32 = sts.d32; +@@ -328,12 +342,16 @@ + } + + for (j = 0; j < dwc_ep->pkt_per_frm - 1; ++j) { +- data_per_desc = +- ((j + 1) * dwc_ep->maxpacket > +- dwc_ep->data_per_frame) ? dwc_ep->data_per_frame - +- j * dwc_ep->maxpacket : dwc_ep->maxpacket; +- data_per_desc += +- (data_per_desc % 4) ? (4 - data_per_desc % 4) : 0; ++ uint32_t len = (j + 1) * dwc_ep->maxpacket; ++ if (len > dwc_ep->data_per_frame) ++ data_per_desc = ++ dwc_ep->data_per_frame - ++ j * dwc_ep->maxpacket; ++ else ++ data_per_desc = dwc_ep->maxpacket; ++ len = data_per_desc % 4; ++ if (len) ++ data_per_desc += 4 - len; + sts.b_iso_out.rxbytes = data_per_desc; + dma_desc->buf = dma_ad; + dma_desc->status.d32 = sts.d32; +@@ -344,12 +362,15 @@ + } + + sts.b_iso_out.ioc = 1; +- data_per_desc = +- ((j + 1) * dwc_ep->maxpacket > +- dwc_ep->data_per_frame) ? dwc_ep->data_per_frame - +- j * dwc_ep->maxpacket : dwc_ep->maxpacket; +- data_per_desc += +- (data_per_desc % 4) ? (4 - data_per_desc % 4) : 0; ++ len = (j + 1) * dwc_ep->maxpacket; ++ if (len > dwc_ep->data_per_frame) ++ data_per_desc = ++ dwc_ep->data_per_frame - j * dwc_ep->maxpacket; ++ else ++ data_per_desc = dwc_ep->maxpacket; ++ len = data_per_desc % 4; ++ if (len) ++ data_per_desc += 4 - len; + sts.b_iso_out.rxbytes = data_per_desc; + + dma_desc->buf = dma_ad; +@@ -364,16 +385,19 @@ + for (i = 0; i < dwc_ep->desc_cnt - dwc_ep->pkt_per_frm; + i += dwc_ep->pkt_per_frm) { + for (j = 0; j < dwc_ep->pkt_per_frm; ++j) { ++ uint32_t len = (j + 1) * dwc_ep->maxpacket; ++ if (len > dwc_ep->data_per_frame) ++ data_per_desc = ++ dwc_ep->data_per_frame - ++ j * dwc_ep->maxpacket; ++ else ++ data_per_desc = dwc_ep->maxpacket; ++ len = data_per_desc % 4; ++ if (len) ++ data_per_desc += 4 - len; ++ + data_per_desc = +- ((j + 1) * dwc_ep->maxpacket > +- dwc_ep->data_per_frame) ? dwc_ep-> +- data_per_frame - +- j * dwc_ep->maxpacket : dwc_ep->maxpacket; +- data_per_desc += +- (data_per_desc % 4) ? (4 - +- data_per_desc % +- 4) : 0; +- sts.b_iso_out.rxbytes = data_per_desc; ++ sts.b_iso_out.rxbytes = data_per_desc; + dma_desc->buf = dma_ad; + dma_desc->status.d32 = sts.d32; + +@@ -414,7 +438,7 @@ + dwc_ep->next_frame = 0; + + /** Write dma_ad into DOEPDMA register */ +- dwc_write_reg32(&(out_regs->doepdma), ++ DWC_WRITE_REG32(&(out_regs->doepdma), + (uint32_t) dwc_ep->iso_dma_desc_addr); + + } +@@ -429,17 +453,17 @@ + fifosize_data_t txfifosize, rxfifosize; + + txfifosize.d32 = +- dwc_read_reg32(&core_if->dev_if->in_ep_regs[dwc_ep->num]-> +- dtxfsts); ++ DWC_READ_REG32(&core_if->dev_if-> ++ in_ep_regs[dwc_ep->num]->dtxfsts); + rxfifosize.d32 = +- dwc_read_reg32(&core_if->core_global_regs->grxfsiz); ++ DWC_READ_REG32(&core_if->core_global_regs->grxfsiz); + + addr = &core_if->dev_if->in_ep_regs[dwc_ep->num]->diepctl; + + dma_ad = dwc_ep->dma_addr0; + + dsts.d32 = +- dwc_read_reg32(&core_if->dev_if->dev_global_regs->dsts); ++ DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts); + + sts.b_iso_in.bs = BS_HOST_READY; + sts.b_iso_in.txsts = 0; +@@ -493,7 +517,7 @@ + dwc_ep->next_frame = sts.b_iso_in.framenum + dwc_ep->bInterval; + + /** Write dma_ad into diepdma register */ +- dwc_write_reg32(&(in_regs->diepdma), ++ DWC_WRITE_REG32(&(in_regs->diepdma), + (uint32_t) dwc_ep->iso_dma_desc_addr); + } + /** Enable endpoint, clear nak */ +@@ -502,8 +526,8 @@ + depctl.b.usbactep = 1; + depctl.b.cnak = 1; + +- dwc_modify_reg32(addr, depctl.d32, depctl.d32); +- depctl.d32 = dwc_read_reg32(addr); ++ DWC_MODIFY_REG32(addr, depctl.d32, depctl.d32); ++ depctl.d32 = DWC_READ_REG32(addr); + } + + /** +@@ -513,7 +537,6 @@ + * @param ep The EP to start the transfer on. + * + */ +- + void dwc_otg_iso_ep_start_buf_transfer(dwc_otg_core_if_t * core_if, + dwc_ep_t * ep) + { +@@ -545,19 +568,21 @@ + /* Program the transfer size and packet count + * as follows: xfersize = N * maxpacket + + * short_packet pktcnt = N + (short_packet +- * exist ? 1 : 0) ++ * exist ? 1 : 0) + */ + deptsiz.b.mc = ep->pkt_per_frm; + deptsiz.b.xfersize = ep->xfer_len; + deptsiz.b.pktcnt = + (ep->xfer_len - 1 + ep->maxpacket) / ep->maxpacket; +- dwc_write_reg32(&core_if->dev_if->in_ep_regs[ep->num]-> +- dieptsiz, deptsiz.d32); ++ DWC_WRITE_REG32(&core_if->dev_if-> ++ in_ep_regs[ep->num]->dieptsiz, ++ deptsiz.d32); + + /* Write the DMA register */ +- dwc_write_reg32(& +- (core_if->dev_if->in_ep_regs[ep->num]-> +- diepdma), (uint32_t) ep->dma_addr); ++ DWC_WRITE_REG32(& ++ (core_if->dev_if-> ++ in_ep_regs[ep->num]->diepdma), ++ (uint32_t) ep->dma_addr); + + } else { + deptsiz.b.pktcnt = +@@ -565,31 +590,31 @@ + ep->maxpacket; + deptsiz.b.xfersize = deptsiz.b.pktcnt * ep->maxpacket; + +- dwc_write_reg32(&core_if->dev_if->out_ep_regs[ep->num]-> +- doeptsiz, deptsiz.d32); ++ DWC_WRITE_REG32(&core_if->dev_if-> ++ out_ep_regs[ep->num]->doeptsiz, ++ deptsiz.d32); + + /* Write the DMA register */ +- dwc_write_reg32(& +- (core_if->dev_if->out_ep_regs[ep->num]-> +- doepdma), (uint32_t) ep->dma_addr); ++ DWC_WRITE_REG32(& ++ (core_if->dev_if-> ++ out_ep_regs[ep->num]->doepdma), ++ (uint32_t) ep->dma_addr); + + } + /** Enable endpoint, clear nak */ + depctl.d32 = 0; +- dwc_modify_reg32(addr, depctl.d32, depctl.d32); +- + depctl.b.epena = 1; + depctl.b.cnak = 1; + +- dwc_modify_reg32(addr, depctl.d32, depctl.d32); ++ DWC_MODIFY_REG32(addr, depctl.d32, depctl.d32); + } + } + + /** + * This function does the setup for a data transfer for an EP and +- * starts the transfer. For an IN transfer, the packets will be ++ * starts the transfer. For an IN transfer, the packets will be + * loaded into the appropriate Tx FIFO in the ISR. For OUT transfers, +- * the packets are unloaded from the Rx FIFO in the ISR. the ISR. ++ * the packets are unloaded from the Rx FIFO in the ISR. + * + * @param core_if Programming view of DWC_otg controller. + * @param ep The EP to start the transfer on. +@@ -611,11 +636,11 @@ + dwc_otg_iso_ep_start_buf_transfer(core_if, ep); + } else { + ep->cur_pkt_addr = +- (ep->proc_buf_num) ? ep->xfer_buff1 : ep-> +- xfer_buff0; ++ (ep->proc_buf_num) ? ep-> ++ xfer_buff1 : ep->xfer_buff0; + ep->cur_pkt_dma_addr = +- (ep->proc_buf_num) ? ep->dma_addr1 : ep-> +- dma_addr0; ++ (ep->proc_buf_num) ? ep-> ++ dma_addr1 : ep->dma_addr0; + dwc_otg_iso_ep_start_frm_transfer(core_if, ep); + } + } +@@ -629,10 +654,8 @@ + } + + /** +- * This function does the setup for a data transfer for an EP and +- * starts the transfer. For an IN transfer, the packets will be +- * loaded into the appropriate Tx FIFO in the ISR. For OUT transfers, +- * the packets are unloaded from the Rx FIFO in the ISR. the ISR. ++ * This function stops transfer for an EP and ++ * resets the ep's variables. + * + * @param core_if Programming view of DWC_otg controller. + * @param ep The EP to start the transfer on. +@@ -650,12 +673,12 @@ + } + + /* disable the ep */ +- depctl.d32 = dwc_read_reg32(addr); ++ depctl.d32 = DWC_READ_REG32(addr); + + depctl.b.epdis = 1; + depctl.b.snak = 1; + +- dwc_write_reg32(addr, depctl.d32); ++ DWC_WRITE_REG32(addr, depctl.d32); + + if (core_if->dma_desc_enable && + ep->iso_desc_addr && ep->iso_dma_desc_addr) { +@@ -690,7 +713,7 @@ + int atomic_alloc) + { + dwc_otg_pcd_ep_t *ep; +- uint64_t flags = 0; ++ dwc_irqflags_t flags = 0; + dwc_ep_t *dwc_ep; + int32_t frm_data; + dsts_data_t dsts; +@@ -698,7 +721,7 @@ + + ep = get_ep_from_handle(pcd, ep_handle); + +- if (!ep->desc || ep->dwc_ep.num == 0) { ++ if (!ep || !ep->desc || ep->dwc_ep.num == 0) { + DWC_WARN("bad ep\n"); + return -DWC_E_INVALID; + } +@@ -736,7 +759,7 @@ + frm_data -= ep->dwc_ep.maxpacket; + } + +- dsts.d32 = dwc_read_reg32(&core_if->dev_if->dev_global_regs->dsts); ++ dsts.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts); + + if (start_frame == -1) { + dwc_ep->next_frame = dsts.b.soffn + 1; +@@ -769,10 +792,10 @@ + + if (atomic_alloc) { + dwc_ep->pkt_info = +- dwc_alloc_atomic(sizeof(iso_pkt_info_t) * dwc_ep->pkt_cnt); ++ DWC_ALLOC_ATOMIC(sizeof(iso_pkt_info_t) * dwc_ep->pkt_cnt); + } else { + dwc_ep->pkt_info = +- dwc_alloc(sizeof(iso_pkt_info_t) * dwc_ep->pkt_cnt); ++ DWC_ALLOC(sizeof(iso_pkt_info_t) * dwc_ep->pkt_cnt); + } + if (!dwc_ep->pkt_info) { + DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags); +@@ -794,7 +817,7 @@ + int dwc_otg_pcd_iso_ep_stop(dwc_otg_pcd_t * pcd, void *ep_handle, + void *req_handle) + { +- uint64_t flags = 0; ++ dwc_irqflags_t flags = 0; + dwc_otg_pcd_ep_t *ep; + dwc_ep_t *dwc_ep; + +@@ -807,7 +830,7 @@ + + dwc_otg_iso_ep_stop_transfer(GET_CORE_IF(pcd), dwc_ep); + +- dwc_free(dwc_ep->pkt_info); ++ DWC_FREE(dwc_ep->pkt_info); + DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags); + if (ep->iso_req_handle != req_handle) { + DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags); +@@ -824,7 +847,7 @@ + * This function is used for perodical data exchnage between PCD and gadget drivers. + * for Isochronous EPs + * +- * - Every time a sync period completes this function is called to ++ * - Every time a sync period completes this function is called to + * perform data exchange between PCD and gadget + */ + void dwc_otg_iso_buffer_done(dwc_otg_pcd_t * pcd, dwc_otg_pcd_ep_t * ep, +@@ -854,6 +877,10 @@ + dwc_ep_t *dwc_ep; + + ep = get_ep_from_handle(pcd, ep_handle); ++ if (!ep->desc || ep->dwc_ep.num == 0) { ++ DWC_WARN("bad ep\n"); ++ return -DWC_E_INVALID; ++ } + dwc_ep = &ep->dwc_ep; + + return dwc_ep->pkt_cnt; +@@ -867,6 +894,9 @@ + dwc_ep_t *dwc_ep; + + ep = get_ep_from_handle(pcd, ep_handle); ++ if (!ep) ++ DWC_WARN("bad ep\n"); ++ + dwc_ep = &ep->dwc_ep; + + *status = dwc_ep->pkt_info[packet].status; +@@ -874,7 +904,7 @@ + *offset = dwc_ep->pkt_info[packet].offset; + } + +-#endif /* DWC_EN_ISOC */ ++#endif /* DWC_EN_ISOC */ + + static void dwc_otg_pcd_init_ep(dwc_otg_pcd_t * pcd, dwc_otg_pcd_ep_t * pcd_ep, + uint32_t is_in, uint32_t ep_num) +@@ -906,7 +936,7 @@ + } + + /** +- * Initialise ep's ++ * Initialize ep's + */ + static void dwc_otg_pcd_reinit(dwc_otg_pcd_t * pcd) + { +@@ -964,7 +994,7 @@ + } + + /** +- * This function is called when the SRP timer expires. The SRP should ++ * This function is called when the SRP timer expires. The SRP should + * complete within 6 seconds. + */ + static void srp_timeout(void *ptr) +@@ -973,9 +1003,34 @@ + dwc_otg_core_if_t *core_if = (dwc_otg_core_if_t *) ptr; + volatile uint32_t *addr = &core_if->core_global_regs->gotgctl; + +- gotgctl.d32 = dwc_read_reg32(addr); ++ gotgctl.d32 = DWC_READ_REG32(addr); + + core_if->srp_timer_started = 0; ++ ++ if (core_if->adp_enable) { ++ if (gotgctl.b.bsesvld == 0) { ++ gpwrdn_data_t gpwrdn = {.d32 = 0 }; ++ DWC_PRINTF("SRP Timeout BSESSVLD = 0\n"); ++ /* Power off the core */ ++ if (core_if->power_down == 2) { ++ gpwrdn.b.pwrdnswtch = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs-> ++ gpwrdn, gpwrdn.d32, 0); ++ } ++ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pmuintsel = 1; ++ gpwrdn.b.pmuactv = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32); ++ dwc_otg_adp_probe_start(core_if); ++ } else { ++ DWC_PRINTF("SRP Timeout BSESSVLD = 1\n"); ++ core_if->op_state = B_PERIPHERAL; ++ dwc_otg_core_init(core_if); ++ dwc_otg_enable_global_interrupts(core_if); ++ cil_pcd_start(core_if); ++ } ++ } + + if ((core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS) && + (core_if->core_params->i2c_enable)) { +@@ -983,28 +1038,27 @@ + + if ((core_if->srp_success) && (gotgctl.b.bsesvld)) { + if (core_if->pcd_cb && core_if->pcd_cb->resume_wakeup) { +- core_if->pcd_cb->resume_wakeup(core_if->pcd_cb-> +- p); ++ core_if->pcd_cb->resume_wakeup(core_if->pcd_cb->p); + } + + /* Clear Session Request */ + gotgctl.d32 = 0; + gotgctl.b.sesreq = 1; +- dwc_modify_reg32(&core_if->core_global_regs->gotgctl, ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gotgctl, + gotgctl.d32, 0); + + core_if->srp_success = 0; + } else { + __DWC_ERROR("Device not connected/responding\n"); + gotgctl.b.sesreq = 0; +- dwc_write_reg32(addr, gotgctl.d32); ++ DWC_WRITE_REG32(addr, gotgctl.d32); + } + } else if (gotgctl.b.sesreq) { + DWC_PRINTF("SRP Timeout\n"); + + __DWC_ERROR("Device not connected/responding\n"); + gotgctl.b.sesreq = 0; +- dwc_write_reg32(addr, gotgctl.d32); ++ DWC_WRITE_REG32(addr, gotgctl.d32); + } else { + DWC_PRINTF(" SRP GOTGCTL=%0x\n", gotgctl.d32); + } +@@ -1026,7 +1080,7 @@ + + DWC_DEBUGPL(DBG_PCDV, "Start xfer tasklet\n"); + +- diepctl.d32 = dwc_read_reg32(&core_if->dev_if->in_ep_regs[0]->diepctl); ++ diepctl.d32 = DWC_READ_REG32(&core_if->dev_if->in_ep_regs[0]->diepctl); + + if (pcd->ep0.queue_sof) { + pcd->ep0.queue_sof = 0; +@@ -1037,7 +1091,7 @@ + for (i = 0; i < core_if->dev_if->num_in_eps; i++) { + depctl_data_t diepctl; + diepctl.d32 = +- dwc_read_reg32(&core_if->dev_if->in_ep_regs[i]->diepctl); ++ DWC_READ_REG32(&core_if->dev_if->in_ep_regs[i]->diepctl); + + if (pcd->in_ep[i].queue_sof) { + pcd->in_ep[i].queue_sof = 0; +@@ -1055,28 +1109,33 @@ + */ + dwc_otg_pcd_t *dwc_otg_pcd_init(dwc_otg_core_if_t * core_if) + { +- dwc_otg_pcd_t *pcd = 0; ++ dwc_otg_pcd_t *pcd = NULL; + dwc_otg_dev_if_t *dev_if; ++ int i; + + /* + * Allocate PCD structure + */ +- pcd = dwc_alloc(sizeof(dwc_otg_pcd_t)); ++ pcd = DWC_ALLOC(sizeof(dwc_otg_pcd_t)); + +- if (pcd == 0) { ++ if (pcd == NULL) { + return NULL; + } + + pcd->lock = DWC_SPINLOCK_ALLOC(); + DWC_DEBUGPL(DBG_HCDV, "Init of PCD %p given core_if %p\n", + pcd, core_if);//GRAYG +- pcd->core_if = core_if; + if (!pcd->lock) { + DWC_ERROR("Could not allocate lock for pcd"); +- dwc_free(pcd); ++ DWC_FREE(pcd); + return NULL; + } ++ /* Set core_if's lock pointer to hcd->lock */ ++ core_if->lock = pcd->lock; ++ pcd->core_if = core_if; ++ + dev_if = core_if->dev_if; ++ dev_if->isoc_ep = NULL; + + if (core_if->hwcfg4.b.ded_fifo_en) { + DWC_PRINTF("Dedicated Tx FIFOs mode\n"); +@@ -1085,9 +1144,10 @@ + } + + /* +- * Initialized the Core for Device mode. +- */ +- if (dwc_otg_is_device_mode(core_if)) { ++ * Initialized the Core for Device mode here if there is nod ADP support. ++ * Otherwise it will be done later in dwc_otg_adp_start routine. ++ */ ++ if (dwc_otg_is_device_mode(core_if) /*&& !core_if->adp_enable*/) { + dwc_otg_core_dev_init(core_if); + } + +@@ -1101,20 +1161,20 @@ + */ + if (GET_CORE_IF(pcd)->dma_enable) { + pcd->setup_pkt = +- dwc_dma_alloc(sizeof(*pcd->setup_pkt) * 5, ++ DWC_DMA_ALLOC(sizeof(*pcd->setup_pkt) * 5, + &pcd->setup_pkt_dma_handle); +- if (pcd->setup_pkt == 0) { +- dwc_free(pcd); ++ if (pcd->setup_pkt == NULL) { ++ DWC_FREE(pcd); + return NULL; + } + + pcd->status_buf = +- dwc_dma_alloc(sizeof(uint16_t), ++ DWC_DMA_ALLOC(sizeof(uint16_t), + &pcd->status_buf_dma_handle); +- if (pcd->status_buf == 0) { +- dwc_dma_free(sizeof(*pcd->setup_pkt) * 5, ++ if (pcd->status_buf == NULL) { ++ DWC_DMA_FREE(sizeof(*pcd->setup_pkt) * 5, + pcd->setup_pkt, pcd->setup_pkt_dma_handle); +- dwc_free(pcd); ++ DWC_FREE(pcd); + return NULL; + } + +@@ -1166,29 +1226,29 @@ + dma_setup_desc_addr + [0], 1); + +- dwc_dma_free(sizeof(*pcd->setup_pkt) * 5, ++ DWC_DMA_FREE(sizeof(*pcd->setup_pkt) * 5, + pcd->setup_pkt, + pcd->setup_pkt_dma_handle); +- dwc_dma_free(sizeof(*pcd->status_buf), ++ DWC_DMA_FREE(sizeof(*pcd->status_buf), + pcd->status_buf, + pcd->status_buf_dma_handle); + +- dwc_free(pcd); ++ DWC_FREE(pcd); + + return NULL; + } + } + } else { +- pcd->setup_pkt = dwc_alloc(sizeof(*pcd->setup_pkt) * 5); +- if (pcd->setup_pkt == 0) { +- dwc_free(pcd); ++ pcd->setup_pkt = DWC_ALLOC(sizeof(*pcd->setup_pkt) * 5); ++ if (pcd->setup_pkt == NULL) { ++ DWC_FREE(pcd); + return NULL; + } + +- pcd->status_buf = dwc_alloc(sizeof(uint16_t)); +- if (pcd->status_buf == 0) { +- dwc_free(pcd->setup_pkt); +- dwc_free(pcd); ++ pcd->status_buf = DWC_ALLOC(sizeof(uint16_t)); ++ if (pcd->status_buf == NULL) { ++ DWC_FREE(pcd->setup_pkt); ++ DWC_FREE(pcd); + return NULL; + } + } +@@ -1197,39 +1257,80 @@ + + /* Allocate the cfi object for the PCD */ + #ifdef DWC_UTE_CFI +- pcd->cfi = dwc_alloc(sizeof(cfiobject_t)); ++ pcd->cfi = DWC_ALLOC(sizeof(cfiobject_t)); + if (NULL == pcd->cfi) +- return NULL; ++ goto fail; + if (init_cfi(pcd->cfi)) { + CFI_INFO("%s: Failed to init the CFI object\n", __func__); +- return NULL; ++ goto fail; + } + #endif + + /* Initialize tasklets */ +- pcd->start_xfer_tasklet = DWC_TASK_ALLOC(start_xfer_tasklet_func, pcd); +- pcd->test_mode_tasklet = DWC_TASK_ALLOC(do_test_mode, pcd); +- /* Initialize timer */ +- pcd->srp_timer = DWC_TIMER_ALLOC("SRP TIMER", srp_timeout, core_if); ++ pcd->start_xfer_tasklet = DWC_TASK_ALLOC("xfer_tasklet", ++ start_xfer_tasklet_func, pcd); ++ pcd->test_mode_tasklet = DWC_TASK_ALLOC("test_mode_tasklet", ++ do_test_mode, pcd); ++ ++ /* Initialize SRP timer */ ++ core_if->srp_timer = DWC_TIMER_ALLOC("SRP TIMER", srp_timeout, core_if); ++ ++ if (core_if->core_params->dev_out_nak) { ++ /** ++ * Initialize xfer timeout timer. Implemented for ++ * 2.93a feature "Device DDMA OUT NAK Enhancement" ++ */ ++ for(i = 0; i < MAX_EPS_CHANNELS; i++) { ++ pcd->core_if->ep_xfer_timer[i] = ++ DWC_TIMER_ALLOC("ep timer", ep_xfer_timeout, ++ &pcd->core_if->ep_xfer_info[i]); ++ } ++ } ++ + return pcd; ++#ifdef DWC_UTE_CFI ++fail: ++#endif ++ if (pcd->setup_pkt) ++ DWC_FREE(pcd->setup_pkt); ++ if (pcd->status_buf) ++ DWC_FREE(pcd->status_buf); ++#ifdef DWC_UTE_CFI ++ if (pcd->cfi) ++ DWC_FREE(pcd->cfi); ++#endif ++ if (pcd) ++ DWC_FREE(pcd); ++ return NULL; ++ + } + ++/** ++ * Remove PCD specific data ++ */ + void dwc_otg_pcd_remove(dwc_otg_pcd_t * pcd) + { + dwc_otg_dev_if_t *dev_if = GET_CORE_IF(pcd)->dev_if; ++ int i; ++ if (pcd->core_if->core_params->dev_out_nak) { ++ for (i = 0; i < MAX_EPS_CHANNELS; i++) { ++ DWC_TIMER_CANCEL(pcd->core_if->ep_xfer_timer[i]); ++ pcd->core_if->ep_xfer_info[i].state = 0; ++ } ++ } + + if (GET_CORE_IF(pcd)->dma_enable) { +- dwc_dma_free(sizeof(*pcd->setup_pkt) * 5, pcd->setup_pkt, ++ DWC_DMA_FREE(sizeof(*pcd->setup_pkt) * 5, pcd->setup_pkt, + pcd->setup_pkt_dma_handle); +- dwc_dma_free(sizeof(uint16_t), pcd->status_buf, ++ DWC_DMA_FREE(sizeof(uint16_t), pcd->status_buf, + pcd->status_buf_dma_handle); + if (GET_CORE_IF(pcd)->dma_desc_enable) { + dwc_otg_ep_free_desc_chain(dev_if->setup_desc_addr[0], +- dev_if-> +- dma_setup_desc_addr[0], 1); ++ dev_if->dma_setup_desc_addr ++ [0], 1); + dwc_otg_ep_free_desc_chain(dev_if->setup_desc_addr[1], +- dev_if-> +- dma_setup_desc_addr[1], 1); ++ dev_if->dma_setup_desc_addr ++ [1], 1); + dwc_otg_ep_free_desc_chain(dev_if->in_desc_addr, + dev_if->dma_in_desc_addr, 1); + dwc_otg_ep_free_desc_chain(dev_if->out_desc_addr, +@@ -1237,13 +1338,22 @@ + 1); + } + } else { +- dwc_free(pcd->setup_pkt); +- dwc_free(pcd->status_buf); ++ DWC_FREE(pcd->setup_pkt); ++ DWC_FREE(pcd->status_buf); + } + DWC_SPINLOCK_FREE(pcd->lock); ++ /* Set core_if's lock pointer to NULL */ ++ pcd->core_if->lock = NULL; ++ + DWC_TASK_FREE(pcd->start_xfer_tasklet); + DWC_TASK_FREE(pcd->test_mode_tasklet); +- DWC_TIMER_FREE(pcd->srp_timer); ++ if (pcd->core_if->core_params->dev_out_nak) { ++ for (i = 0; i < MAX_EPS_CHANNELS; i++) { ++ if (pcd->core_if->ep_xfer_timer[i]) { ++ DWC_TIMER_FREE(pcd->core_if->ep_xfer_timer[i]); ++ } ++ } ++ } + + /* Release the CFI object's dynamic memory */ + #ifdef DWC_UTE_CFI +@@ -1252,9 +1362,12 @@ + } + #endif + +- dwc_free(pcd); ++ DWC_FREE(pcd); + } + ++/** ++ * Returns whether registered pcd is dual speed or not ++ */ + uint32_t dwc_otg_pcd_is_dualspeed(dwc_otg_pcd_t * pcd) + { + dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); +@@ -1269,12 +1382,15 @@ + return 1; + } + ++/** ++ * Returns whether registered pcd is OTG capable or not ++ */ + uint32_t dwc_otg_pcd_is_otg(dwc_otg_pcd_t * pcd) + { + dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); + gusbcfg_data_t usbcfg = {.d32 = 0 }; + +- usbcfg.d32 = dwc_read_reg32(&core_if->core_global_regs->gusbcfg); ++ usbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg); + if (!usbcfg.b.srpcap || !usbcfg.b.hnpcap) { + return 0; + } +@@ -1340,14 +1456,22 @@ + (core_if->tx_msk & (1 << (fifo_num - 1))) ^ core_if->tx_msk; + } + ++/** ++ * This function is being called from gadget ++ * to enable PCD endpoint. ++ */ + int dwc_otg_pcd_ep_enable(dwc_otg_pcd_t * pcd, + const uint8_t * ep_desc, void *usb_ep) + { + int num, dir; +- dwc_otg_pcd_ep_t *ep = 0; ++ dwc_otg_pcd_ep_t *ep = NULL; + const usb_endpoint_descriptor_t *desc; +- uint64_t flags; ++ dwc_irqflags_t flags; ++ fifosize_data_t dptxfsiz = {.d32 = 0 }; ++ gdfifocfg_data_t gdfifocfg = {.d32 = 0 }; ++ gdfifocfg_data_t gdfifocfgbase = {.d32 = 0 }; + int retval = 0; ++ int i, epcount; + + desc = (const usb_endpoint_descriptor_t *)ep_desc; + +@@ -1368,9 +1492,27 @@ + } + + if (dir == UE_DIR_IN) { +- ep = &pcd->in_ep[num - 1]; ++ epcount = pcd->core_if->dev_if->num_in_eps; ++ for (i = 0; i < epcount; i++) { ++ if (num == pcd->in_ep[i].dwc_ep.num) { ++ ep = &pcd->in_ep[i]; ++ break; ++ } ++ } + } else { +- ep = &pcd->out_ep[num - 1]; ++ epcount = pcd->core_if->dev_if->num_out_eps; ++ for (i = 0; i < epcount; i++) { ++ if (num == pcd->out_ep[i].dwc_ep.num) { ++ ep = &pcd->out_ep[i]; ++ break; ++ } ++ } ++ } ++ ++ if (!ep) { ++ DWC_WARN("bad address\n"); ++ retval = -DWC_E_INVALID; ++ goto out; + } + + DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags); +@@ -1405,7 +1547,23 @@ + */ + ep->dwc_ep.tx_fifo_num = + assign_tx_fifo(GET_CORE_IF(pcd)); ++ } + ++ /* Calculating EP info controller base address */ ++ if (ep->dwc_ep.tx_fifo_num && GET_CORE_IF(pcd)->en_multiple_tx_fifo) { ++ gdfifocfg.d32 = ++ DWC_READ_REG32(&GET_CORE_IF(pcd)->core_global_regs-> ++ gdfifocfg); ++ gdfifocfgbase.d32 = gdfifocfg.d32 >> 16; ++ dptxfsiz.d32 = ++ (DWC_READ_REG32 ++ (&GET_CORE_IF(pcd)-> ++ core_global_regs->dtxfsiz[ep->dwc_ep. ++ tx_fifo_num-1]) >> 16); ++ gdfifocfg.b.epinfobase = ++ gdfifocfgbase.d32 + dptxfsiz.d32; ++ DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs-> ++ gdfifocfg, gdfifocfg.d32); + } + } + /* Set initial data PID. */ +@@ -1415,10 +1573,12 @@ + + /* Alloc DMA Descriptors */ + if (GET_CORE_IF(pcd)->dma_desc_enable) { ++#ifndef DWC_UTE_PER_IO + if (ep->dwc_ep.type != UE_ISOCHRONOUS) { ++#endif + ep->dwc_ep.desc_addr = +- dwc_otg_ep_alloc_desc_chain(&ep->dwc_ep. +- dma_desc_addr, ++ dwc_otg_ep_alloc_desc_chain(&ep-> ++ dwc_ep.dma_desc_addr, + MAX_DMA_DESC_CNT); + if (!ep->dwc_ep.desc_addr) { + DWC_WARN("%s, can't allocate DMA descriptor\n", +@@ -1427,12 +1587,21 @@ + DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags); + goto out; + } ++#ifndef DWC_UTE_PER_IO + } ++#endif + } + + DWC_DEBUGPL(DBG_PCD, "Activate %s: type=%d, mps=%d desc=%p\n", + (ep->dwc_ep.is_in ? "IN" : "OUT"), + ep->dwc_ep.type, ep->dwc_ep.maxpacket, ep->desc); ++#ifdef DWC_UTE_PER_IO ++ ep->dwc_ep.xiso_bInterval = 1 << (ep->desc->bInterval - 1); ++#endif ++ if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) { ++ ep->dwc_ep.bInterval = 1 << (ep->desc->bInterval - 1); ++ ep->dwc_ep.frame_num = 0xFFFFFFFF; ++ } + + dwc_otg_ep_activate(GET_CORE_IF(pcd), &ep->dwc_ep); + +@@ -1444,22 +1613,28 @@ + + DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags); + +- out: ++out: + return retval; + } + ++/** ++ * This function is being called from gadget ++ * to disable PCD endpoint. ++ */ + int dwc_otg_pcd_ep_disable(dwc_otg_pcd_t * pcd, void *ep_handle) + { + dwc_otg_pcd_ep_t *ep; +- uint64_t flags; ++ dwc_irqflags_t flags; + dwc_otg_dev_dma_desc_t *desc_addr; + dwc_dma_t dma_desc_addr; ++ gdfifocfg_data_t gdfifocfgbase = {.d32 = 0 }; ++ gdfifocfg_data_t gdfifocfg = {.d32 = 0 }; ++ fifosize_data_t dptxfsiz = {.d32 = 0 }; + + ep = get_ep_from_handle(pcd, ep_handle); + + if (!ep || !ep->desc) { +- DWC_DEBUGPL(DBG_PCD, "%s, %d %s not enabled\n", __func__, +- ep->dwc_ep.num, ep->dwc_ep.is_in ? "IN" : "OUT"); ++ DWC_DEBUGPL(DBG_PCD, "bad ep address\n"); + return -DWC_E_INVALID; + } + +@@ -1468,13 +1643,35 @@ + dwc_otg_request_nuke(ep); + + dwc_otg_ep_deactivate(GET_CORE_IF(pcd), &ep->dwc_ep); +- ep->desc = 0; ++ if (pcd->core_if->core_params->dev_out_nak) ++ { ++ DWC_TIMER_CANCEL(pcd->core_if->ep_xfer_timer[ep->dwc_ep.num]); ++ pcd->core_if->ep_xfer_info[ep->dwc_ep.num].state = 0; ++ } ++ ep->desc = NULL; + ep->stopped = 1; + ++ gdfifocfg.d32 = ++ DWC_READ_REG32(&GET_CORE_IF(pcd)->core_global_regs->gdfifocfg); ++ gdfifocfgbase.d32 = gdfifocfg.d32 >> 16; ++ + if (ep->dwc_ep.is_in) { +- dwc_otg_flush_tx_fifo(GET_CORE_IF(pcd), ep->dwc_ep.tx_fifo_num); ++ if (GET_CORE_IF(pcd)->en_multiple_tx_fifo) { ++ /* Flush the Tx FIFO */ ++ dwc_otg_flush_tx_fifo(GET_CORE_IF(pcd), ep->dwc_ep.tx_fifo_num); ++ } + release_perio_tx_fifo(GET_CORE_IF(pcd), ep->dwc_ep.tx_fifo_num); + release_tx_fifo(GET_CORE_IF(pcd), ep->dwc_ep.tx_fifo_num); ++ if (GET_CORE_IF(pcd)->en_multiple_tx_fifo) { ++ /* Decreasing EPinfo Base Addr */ ++ dptxfsiz.d32 = ++ (DWC_READ_REG32 ++ (&GET_CORE_IF(pcd)-> ++ core_global_regs->dtxfsiz[ep->dwc_ep.tx_fifo_num-1]) >> 16); ++ gdfifocfg.b.epinfobase = gdfifocfgbase.d32 - dptxfsiz.d32; ++ DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gdfifocfg, ++ gdfifocfg.d32); ++ } + } + + /* Free DMA Descriptors */ +@@ -1491,36 +1688,415 @@ + goto out_unlocked; + } + } +- + DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags); + +- out_unlocked: ++out_unlocked: + DWC_DEBUGPL(DBG_PCD, "%d %s disabled\n", ep->dwc_ep.num, + ep->dwc_ep.is_in ? "IN" : "OUT"); + return 0; + + } + ++/******************************************************************************/ ++#ifdef DWC_UTE_PER_IO ++ ++/** ++ * Free the request and its extended parts ++ * ++ */ ++void dwc_pcd_xiso_ereq_free(dwc_otg_pcd_ep_t * ep, dwc_otg_pcd_request_t * req) ++{ ++ DWC_FREE(req->ext_req.per_io_frame_descs); ++ DWC_FREE(req); ++} ++ ++/** ++ * Start the next request in the endpoint's queue. ++ * ++ */ ++int dwc_otg_pcd_xiso_start_next_request(dwc_otg_pcd_t * pcd, ++ dwc_otg_pcd_ep_t * ep) ++{ ++ int i; ++ dwc_otg_pcd_request_t *req = NULL; ++ dwc_ep_t *dwcep = NULL; ++ struct dwc_iso_xreq_port *ereq = NULL; ++ struct dwc_iso_pkt_desc_port *ddesc_iso; ++ uint16_t nat; ++ depctl_data_t diepctl; ++ ++ dwcep = &ep->dwc_ep; ++ ++ if (dwcep->xiso_active_xfers > 0) { ++#if 0 //Disable this to decrease s/w overhead that is crucial for Isoc transfers ++ DWC_WARN("There are currently active transfers for EP%d \ ++ (active=%d; queued=%d)", dwcep->num, dwcep->xiso_active_xfers, ++ dwcep->xiso_queued_xfers); ++#endif ++ return 0; ++ } ++ ++ nat = UGETW(ep->desc->wMaxPacketSize); ++ nat = (nat >> 11) & 0x03; ++ ++ if (!DWC_CIRCLEQ_EMPTY(&ep->queue)) { ++ req = DWC_CIRCLEQ_FIRST(&ep->queue); ++ ereq = &req->ext_req; ++ ep->stopped = 0; ++ ++ /* Get the frame number */ ++ dwcep->xiso_frame_num = ++ dwc_otg_get_frame_number(GET_CORE_IF(pcd)); ++ DWC_DEBUG("FRM_NUM=%d", dwcep->xiso_frame_num); ++ ++ ddesc_iso = ereq->per_io_frame_descs; ++ ++ if (dwcep->is_in) { ++ /* Setup DMA Descriptor chain for IN Isoc request */ ++ for (i = 0; i < ereq->pio_pkt_count; i++) { ++ //if ((i % (nat + 1)) == 0) ++ if ( i > 0 ) ++ dwcep->xiso_frame_num = (dwcep->xiso_bInterval + ++ dwcep->xiso_frame_num) & 0x3FFF; ++ dwcep->desc_addr[i].buf = ++ req->dma + ddesc_iso[i].offset; ++ dwcep->desc_addr[i].status.b_iso_in.txbytes = ++ ddesc_iso[i].length; ++ dwcep->desc_addr[i].status.b_iso_in.framenum = ++ dwcep->xiso_frame_num; ++ dwcep->desc_addr[i].status.b_iso_in.bs = ++ BS_HOST_READY; ++ dwcep->desc_addr[i].status.b_iso_in.txsts = 0; ++ dwcep->desc_addr[i].status.b_iso_in.sp = ++ (ddesc_iso[i].length % ++ dwcep->maxpacket) ? 1 : 0; ++ dwcep->desc_addr[i].status.b_iso_in.ioc = 0; ++ dwcep->desc_addr[i].status.b_iso_in.pid = nat + 1; ++ dwcep->desc_addr[i].status.b_iso_in.l = 0; ++ ++ /* Process the last descriptor */ ++ if (i == ereq->pio_pkt_count - 1) { ++ dwcep->desc_addr[i].status.b_iso_in.ioc = 1; ++ dwcep->desc_addr[i].status.b_iso_in.l = 1; ++ } ++ } ++ ++ /* Setup and start the transfer for this endpoint */ ++ dwcep->xiso_active_xfers++; ++ DWC_WRITE_REG32(&GET_CORE_IF(pcd)->dev_if-> ++ in_ep_regs[dwcep->num]->diepdma, ++ dwcep->dma_desc_addr); ++ diepctl.d32 = 0; ++ diepctl.b.epena = 1; ++ diepctl.b.cnak = 1; ++ DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->dev_if-> ++ in_ep_regs[dwcep->num]->diepctl, 0, ++ diepctl.d32); ++ } else { ++ /* Setup DMA Descriptor chain for OUT Isoc request */ ++ for (i = 0; i < ereq->pio_pkt_count; i++) { ++ //if ((i % (nat + 1)) == 0) ++ dwcep->xiso_frame_num = (dwcep->xiso_bInterval + ++ dwcep->xiso_frame_num) & 0x3FFF; ++ dwcep->desc_addr[i].buf = ++ req->dma + ddesc_iso[i].offset; ++ dwcep->desc_addr[i].status.b_iso_out.rxbytes = ++ ddesc_iso[i].length; ++ dwcep->desc_addr[i].status.b_iso_out.framenum = ++ dwcep->xiso_frame_num; ++ dwcep->desc_addr[i].status.b_iso_out.bs = ++ BS_HOST_READY; ++ dwcep->desc_addr[i].status.b_iso_out.rxsts = 0; ++ dwcep->desc_addr[i].status.b_iso_out.sp = ++ (ddesc_iso[i].length % ++ dwcep->maxpacket) ? 1 : 0; ++ dwcep->desc_addr[i].status.b_iso_out.ioc = 0; ++ dwcep->desc_addr[i].status.b_iso_out.pid = nat + 1; ++ dwcep->desc_addr[i].status.b_iso_out.l = 0; ++ ++ /* Process the last descriptor */ ++ if (i == ereq->pio_pkt_count - 1) { ++ dwcep->desc_addr[i].status.b_iso_out.ioc = 1; ++ dwcep->desc_addr[i].status.b_iso_out.l = 1; ++ } ++ } ++ ++ /* Setup and start the transfer for this endpoint */ ++ dwcep->xiso_active_xfers++; ++ DWC_WRITE_REG32(&GET_CORE_IF(pcd)->dev_if-> ++ out_ep_regs[dwcep->num]->doepdma, ++ dwcep->dma_desc_addr); ++ diepctl.d32 = 0; ++ diepctl.b.epena = 1; ++ diepctl.b.cnak = 1; ++ DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->dev_if-> ++ out_ep_regs[dwcep->num]->doepctl, 0, ++ diepctl.d32); ++ } ++ ++ } else { ++ ep->stopped = 1; ++ } ++ ++ return 0; ++} ++ ++/** ++ * - Remove the request from the queue ++ */ ++void complete_xiso_ep(dwc_otg_pcd_ep_t * ep) ++{ ++ dwc_otg_pcd_request_t *req = NULL; ++ struct dwc_iso_xreq_port *ereq = NULL; ++ struct dwc_iso_pkt_desc_port *ddesc_iso = NULL; ++ dwc_ep_t *dwcep = NULL; ++ int i; ++ ++ //DWC_DEBUG(); ++ dwcep = &ep->dwc_ep; ++ ++ /* Get the first pending request from the queue */ ++ if (!DWC_CIRCLEQ_EMPTY(&ep->queue)) { ++ req = DWC_CIRCLEQ_FIRST(&ep->queue); ++ if (!req) { ++ DWC_PRINTF("complete_ep 0x%p, req = NULL!\n", ep); ++ return; ++ } ++ dwcep->xiso_active_xfers--; ++ dwcep->xiso_queued_xfers--; ++ /* Remove this request from the queue */ ++ DWC_CIRCLEQ_REMOVE_INIT(&ep->queue, req, queue_entry); ++ } else { ++ DWC_PRINTF("complete_ep 0x%p, ep->queue empty!\n", ep); ++ return; ++ } ++ ++ ep->stopped = 1; ++ ereq = &req->ext_req; ++ ddesc_iso = ereq->per_io_frame_descs; ++ ++ if (dwcep->xiso_active_xfers < 0) { ++ DWC_WARN("EP#%d (xiso_active_xfers=%d)", dwcep->num, ++ dwcep->xiso_active_xfers); ++ } ++ ++ /* Fill the Isoc descs of portable extended req from dma descriptors */ ++ for (i = 0; i < ereq->pio_pkt_count; i++) { ++ if (dwcep->is_in) { /* IN endpoints */ ++ ddesc_iso[i].actual_length = ddesc_iso[i].length - ++ dwcep->desc_addr[i].status.b_iso_in.txbytes; ++ ddesc_iso[i].status = ++ dwcep->desc_addr[i].status.b_iso_in.txsts; ++ } else { /* OUT endpoints */ ++ ddesc_iso[i].actual_length = ddesc_iso[i].length - ++ dwcep->desc_addr[i].status.b_iso_out.rxbytes; ++ ddesc_iso[i].status = ++ dwcep->desc_addr[i].status.b_iso_out.rxsts; ++ } ++ } ++ ++ DWC_SPINUNLOCK(ep->pcd->lock); ++ ++ /* Call the completion function in the non-portable logic */ ++ ep->pcd->fops->xisoc_complete(ep->pcd, ep->priv, req->priv, 0, ++ &req->ext_req); ++ ++ DWC_SPINLOCK(ep->pcd->lock); ++ ++ /* Free the request - specific freeing needed for extended request object */ ++ dwc_pcd_xiso_ereq_free(ep, req); ++ ++ /* Start the next request */ ++ dwc_otg_pcd_xiso_start_next_request(ep->pcd, ep); ++ ++ return; ++} ++ ++/** ++ * Create and initialize the Isoc pkt descriptors of the extended request. ++ * ++ */ ++static int dwc_otg_pcd_xiso_create_pkt_descs(dwc_otg_pcd_request_t * req, ++ void *ereq_nonport, ++ int atomic_alloc) ++{ ++ struct dwc_iso_xreq_port *ereq = NULL; ++ struct dwc_iso_xreq_port *req_mapped = NULL; ++ struct dwc_iso_pkt_desc_port *ipds = NULL; /* To be created in this function */ ++ uint32_t pkt_count; ++ int i; ++ ++ ereq = &req->ext_req; ++ req_mapped = (struct dwc_iso_xreq_port *)ereq_nonport; ++ pkt_count = req_mapped->pio_pkt_count; ++ ++ /* Create the isoc descs */ ++ if (atomic_alloc) { ++ ipds = DWC_ALLOC_ATOMIC(sizeof(*ipds) * pkt_count); ++ } else { ++ ipds = DWC_ALLOC(sizeof(*ipds) * pkt_count); ++ } ++ ++ if (!ipds) { ++ DWC_ERROR("Failed to allocate isoc descriptors"); ++ return -DWC_E_NO_MEMORY; ++ } ++ ++ /* Initialize the extended request fields */ ++ ereq->per_io_frame_descs = ipds; ++ ereq->error_count = 0; ++ ereq->pio_alloc_pkt_count = pkt_count; ++ ereq->pio_pkt_count = pkt_count; ++ ereq->tr_sub_flags = req_mapped->tr_sub_flags; ++ ++ /* Init the Isoc descriptors */ ++ for (i = 0; i < pkt_count; i++) { ++ ipds[i].length = req_mapped->per_io_frame_descs[i].length; ++ ipds[i].offset = req_mapped->per_io_frame_descs[i].offset; ++ ipds[i].status = req_mapped->per_io_frame_descs[i].status; /* 0 */ ++ ipds[i].actual_length = ++ req_mapped->per_io_frame_descs[i].actual_length; ++ } ++ ++ return 0; ++} ++ ++static void prn_ext_request(struct dwc_iso_xreq_port *ereq) ++{ ++ struct dwc_iso_pkt_desc_port *xfd = NULL; ++ int i; ++ ++ DWC_DEBUG("per_io_frame_descs=%p", ereq->per_io_frame_descs); ++ DWC_DEBUG("tr_sub_flags=%d", ereq->tr_sub_flags); ++ DWC_DEBUG("error_count=%d", ereq->error_count); ++ DWC_DEBUG("pio_alloc_pkt_count=%d", ereq->pio_alloc_pkt_count); ++ DWC_DEBUG("pio_pkt_count=%d", ereq->pio_pkt_count); ++ DWC_DEBUG("res=%d", ereq->res); ++ ++ for (i = 0; i < ereq->pio_pkt_count; i++) { ++ xfd = &ereq->per_io_frame_descs[0]; ++ DWC_DEBUG("FD #%d", i); ++ ++ DWC_DEBUG("xfd->actual_length=%d", xfd->actual_length); ++ DWC_DEBUG("xfd->length=%d", xfd->length); ++ DWC_DEBUG("xfd->offset=%d", xfd->offset); ++ DWC_DEBUG("xfd->status=%d", xfd->status); ++ } ++} ++ ++/** ++ * ++ */ ++int dwc_otg_pcd_xiso_ep_queue(dwc_otg_pcd_t * pcd, void *ep_handle, ++ uint8_t * buf, dwc_dma_t dma_buf, uint32_t buflen, ++ int zero, void *req_handle, int atomic_alloc, ++ void *ereq_nonport) ++{ ++ dwc_otg_pcd_request_t *req = NULL; ++ dwc_otg_pcd_ep_t *ep; ++ dwc_irqflags_t flags; ++ int res; ++ ++ ep = get_ep_from_handle(pcd, ep_handle); ++ if (!ep) { ++ DWC_WARN("bad ep\n"); ++ return -DWC_E_INVALID; ++ } ++ ++ /* We support this extension only for DDMA mode */ ++ if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) ++ if (!GET_CORE_IF(pcd)->dma_desc_enable) ++ return -DWC_E_INVALID; ++ ++ /* Create a dwc_otg_pcd_request_t object */ ++ if (atomic_alloc) { ++ req = DWC_ALLOC_ATOMIC(sizeof(*req)); ++ } else { ++ req = DWC_ALLOC(sizeof(*req)); ++ } ++ ++ if (!req) { ++ return -DWC_E_NO_MEMORY; ++ } ++ ++ /* Create the Isoc descs for this request which shall be the exact match ++ * of the structure sent to us from the non-portable logic */ ++ res = ++ dwc_otg_pcd_xiso_create_pkt_descs(req, ereq_nonport, atomic_alloc); ++ if (res) { ++ DWC_WARN("Failed to init the Isoc descriptors"); ++ DWC_FREE(req); ++ return res; ++ } ++ ++ DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags); ++ ++ DWC_CIRCLEQ_INIT_ENTRY(req, queue_entry); ++ req->buf = buf; ++ req->dma = dma_buf; ++ req->length = buflen; ++ req->sent_zlp = zero; ++ req->priv = req_handle; ++ ++ //DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags); ++ ep->dwc_ep.dma_addr = dma_buf; ++ ep->dwc_ep.start_xfer_buff = buf; ++ ep->dwc_ep.xfer_buff = buf; ++ ep->dwc_ep.xfer_len = 0; ++ ep->dwc_ep.xfer_count = 0; ++ ep->dwc_ep.sent_zlp = 0; ++ ep->dwc_ep.total_len = buflen; ++ ++ /* Add this request to the tail */ ++ DWC_CIRCLEQ_INSERT_TAIL(&ep->queue, req, queue_entry); ++ ep->dwc_ep.xiso_queued_xfers++; ++ ++//DWC_DEBUG("CP_0"); ++//DWC_DEBUG("req->ext_req.tr_sub_flags=%d", req->ext_req.tr_sub_flags); ++//prn_ext_request((struct dwc_iso_xreq_port *) ereq_nonport); ++//prn_ext_request(&req->ext_req); ++ ++ //DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags); ++ ++ /* If the req->status == ASAP then check if there is any active transfer ++ * for this endpoint. If no active transfers, then get the first entry ++ * from the queue and start that transfer ++ */ ++ if (req->ext_req.tr_sub_flags == DWC_EREQ_TF_ASAP) { ++ res = dwc_otg_pcd_xiso_start_next_request(pcd, ep); ++ if (res) { ++ DWC_WARN("Failed to start the next Isoc transfer"); ++ DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags); ++ DWC_FREE(req); ++ return res; ++ } ++ } ++ ++ DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags); ++ return 0; ++} ++ ++#endif ++/* END ifdef DWC_UTE_PER_IO ***************************************************/ + int dwc_otg_pcd_ep_queue(dwc_otg_pcd_t * pcd, void *ep_handle, + uint8_t * buf, dwc_dma_t dma_buf, uint32_t buflen, + int zero, void *req_handle, int atomic_alloc) + { +- int prevented = 0; +- uint64_t flags; ++ dwc_irqflags_t flags; + dwc_otg_pcd_request_t *req; + dwc_otg_pcd_ep_t *ep; + uint32_t max_transfer; + + ep = get_ep_from_handle(pcd, ep_handle); +- if ((!ep->desc && ep->dwc_ep.num != 0)) { ++ if (!ep || (!ep->desc && ep->dwc_ep.num != 0)) { + DWC_WARN("bad ep\n"); + return -DWC_E_INVALID; + } + + if (atomic_alloc) { +- req = dwc_alloc_atomic(sizeof(*req)); ++ req = DWC_ALLOC_ATOMIC(sizeof(*req)); + } else { +- req = dwc_alloc(sizeof(*req)); ++ req = DWC_ALLOC(sizeof(*req)); + } + + if (!req) { +@@ -1539,10 +2115,38 @@ + req->length = buflen; + req->sent_zlp = zero; + req->priv = req_handle; +- ++ req->dw_align_buf = NULL; ++ if ((dma_buf & 0x3) && GET_CORE_IF(pcd)->dma_enable ++ && !GET_CORE_IF(pcd)->dma_desc_enable) ++ req->dw_align_buf = DWC_DMA_ALLOC(buflen, ++ &req->dw_align_buf_dma); + DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags); + + /* ++ * After adding request to the queue for IN ISOC wait for In Token Received ++ * when TX FIFO is empty interrupt and for OUT ISOC wait for OUT Token ++ * Received when EP is disabled interrupt to obtain starting microframe ++ * (odd/even) start transfer ++ */ ++ if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) ++ { ++ if (req != 0) { ++ depctl_data_t depctl = {.d32 = DWC_READ_REG32(&pcd->core_if->dev_if->in_ep_regs[ep->dwc_ep.num]->diepctl)}; ++ ++pcd->request_pending; ++ ++ DWC_CIRCLEQ_INSERT_TAIL(&ep->queue, req, queue_entry); ++ if (ep->dwc_ep.is_in) ++ { ++ depctl.b.cnak = 1; ++ DWC_WRITE_REG32(&pcd->core_if->dev_if->in_ep_regs[ep->dwc_ep.num]->diepctl, depctl.d32); ++ } ++ ++ DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags); ++ } ++ return 0; ++ } ++ ++ /* + * For EP0 IN without premature status, zlp is required? + */ + if (ep->dwc_ep.num == 0 && ep->dwc_ep.is_in) { +@@ -1612,53 +2216,61 @@ + ep->dwc_ep.cfi_req_len = buflen; + pcd->cfi->ops.build_descriptors(pcd->cfi, pcd, + ep, req); +- } else { ++ } else { + #endif + max_transfer = +- GET_CORE_IF(ep->pcd)->core_params-> +- max_transfer_size; ++ GET_CORE_IF(ep->pcd)-> ++ core_params->max_transfer_size; + +- /* Setup and start the Transfer */ +- ep->dwc_ep.dma_addr = dma_buf; +- ep->dwc_ep.start_xfer_buff = buf; +- ep->dwc_ep.xfer_buff = buf; +- ep->dwc_ep.xfer_len = 0; +- ep->dwc_ep.xfer_count = 0; +- ep->dwc_ep.sent_zlp = 0; +- ep->dwc_ep.total_len = buflen; ++ /* Setup and start the Transfer */ ++ if (req->dw_align_buf){ ++ if (ep->dwc_ep.is_in) ++ dwc_memcpy(req->dw_align_buf, buf, buflen); ++ ep->dwc_ep.dma_addr = req->dw_align_buf_dma; ++ ep->dwc_ep.start_xfer_buff = req->dw_align_buf; ++ ep->dwc_ep.xfer_buff = req->dw_align_buf; ++ } else { ++ ep->dwc_ep.dma_addr = dma_buf; ++ ep->dwc_ep.start_xfer_buff = buf; ++ ep->dwc_ep.xfer_buff = buf; ++ } ++ ep->dwc_ep.xfer_len = 0; ++ ep->dwc_ep.xfer_count = 0; ++ ep->dwc_ep.sent_zlp = 0; ++ ep->dwc_ep.total_len = buflen; + +- ep->dwc_ep.maxxfer = max_transfer; +- if (GET_CORE_IF(pcd)->dma_desc_enable) { ++ ep->dwc_ep.maxxfer = max_transfer; ++ if (GET_CORE_IF(pcd)->dma_desc_enable) { + uint32_t out_max_xfer = + DDMA_MAX_TRANSFER_SIZE - + (DDMA_MAX_TRANSFER_SIZE % 4); +- if (ep->dwc_ep.is_in) { +- if (ep->dwc_ep.maxxfer > +- DDMA_MAX_TRANSFER_SIZE) { +- ep->dwc_ep.maxxfer = +- DDMA_MAX_TRANSFER_SIZE; +- } +- } else { ++ if (ep->dwc_ep.is_in) { ++ if (ep->dwc_ep.maxxfer > ++ DDMA_MAX_TRANSFER_SIZE) { ++ ep->dwc_ep.maxxfer = ++ DDMA_MAX_TRANSFER_SIZE; ++ } ++ } else { + if (ep->dwc_ep.maxxfer > + out_max_xfer) { +- ep->dwc_ep.maxxfer = +- out_max_xfer; ++ ep->dwc_ep.maxxfer = ++ out_max_xfer; ++ } + } + } +- } +- if (ep->dwc_ep.maxxfer < ep->dwc_ep.total_len) { +- ep->dwc_ep.maxxfer -= ++ if (ep->dwc_ep.maxxfer < ep->dwc_ep.total_len) { ++ ep->dwc_ep.maxxfer -= + (ep->dwc_ep.maxxfer % + ep->dwc_ep.maxpacket); +- } ++ } + +- if (zero) { +- if ((ep->dwc_ep.total_len % ++ if (zero) { ++ if ((ep->dwc_ep.total_len % + ep->dwc_ep.maxpacket == 0) + && (ep->dwc_ep.total_len != 0)) { +- ep->dwc_ep.sent_zlp = 1; ++ ep->dwc_ep.sent_zlp = 1; ++ } + } +- } + #ifdef DWC_UTE_CFI + } + #endif +@@ -1667,7 +2279,7 @@ + } + } + +- if ((req != 0) || prevented) { ++ if (req != 0) { + ++pcd->request_pending; + DWC_CIRCLEQ_INSERT_TAIL(&ep->queue, req, queue_entry); + if (ep->dwc_ep.is_in && ep->stopped +@@ -1676,32 +2288,32 @@ + diepmsk_data_t diepmsk = {.d32 = 0 }; + diepmsk.b.intktxfemp = 1; + if (GET_CORE_IF(pcd)->multiproc_int_enable) { +- dwc_modify_reg32(&GET_CORE_IF(pcd)->dev_if-> ++ DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->dev_if-> + dev_global_regs-> + diepeachintmsk[ep->dwc_ep.num], + 0, diepmsk.d32); + } else { +- dwc_modify_reg32(&GET_CORE_IF(pcd)->dev_if-> ++ DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->dev_if-> + dev_global_regs->diepmsk, 0, + diepmsk.d32); + } + + } + } +- + DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags); + + return 0; + } ++ + int dwc_otg_pcd_ep_dequeue(dwc_otg_pcd_t * pcd, void *ep_handle, + void *req_handle) + { +- uint64_t flags; ++ dwc_irqflags_t flags; + dwc_otg_pcd_request_t *req; + dwc_otg_pcd_ep_t *ep; + + ep = get_ep_from_handle(pcd, ep_handle); +- if (!ep->desc && ep->dwc_ep.num != 0) { ++ if (!ep || (!ep->desc && ep->dwc_ep.num != 0)) { + DWC_WARN("bad argument\n"); + return -DWC_E_INVALID; + } +@@ -1723,7 +2335,7 @@ + if (!DWC_CIRCLEQ_EMPTY_ENTRY(req, queue_entry)) { + dwc_otg_request_done(ep, req, -DWC_E_RESTART); + } else { +- req = 0; ++ req = NULL; + } + + DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags); +@@ -1744,7 +2356,7 @@ + int dwc_otg_pcd_ep_wedge(dwc_otg_pcd_t * pcd, void *ep_handle) + { + dwc_otg_pcd_ep_t *ep; +- uint64_t flags; ++ dwc_irqflags_t flags; + int retval = 0; + + ep = get_ep_from_handle(pcd, ep_handle); +@@ -1767,11 +2379,10 @@ + fifosize_data_t txfifosize; + + txfifosize.d32 = +- dwc_read_reg32(&GET_CORE_IF(pcd)->core_global_regs-> +- dptxfsiz_dieptxf[ep->dwc_ep. +- tx_fifo_num]); ++ DWC_READ_REG32(&GET_CORE_IF(pcd)->core_global_regs-> ++ dtxfsiz[ep->dwc_ep.tx_fifo_num]); + txstatus.d32 = +- dwc_read_reg32(&GET_CORE_IF(pcd)->dev_if-> ++ DWC_READ_REG32(&GET_CORE_IF(pcd)->dev_if-> + in_ep_regs[ep->dwc_ep.num]->dtxfsts); + + if (txstatus.b.txfspcavail < txfifosize.b.depth) { +@@ -1804,12 +2415,12 @@ + int dwc_otg_pcd_ep_halt(dwc_otg_pcd_t * pcd, void *ep_handle, int value) + { + dwc_otg_pcd_ep_t *ep; +- uint64_t flags; ++ dwc_irqflags_t flags; + int retval = 0; + + ep = get_ep_from_handle(pcd, ep_handle); + +- if ((!ep->desc && ep != &pcd->ep0) || ++ if (!ep || (!ep->desc && ep != &pcd->ep0) || + (ep->desc && (ep->desc->bmAttributes == UE_ISOCHRONOUS))) { + DWC_WARN("%s, bad ep\n", __func__); + return -DWC_E_INVALID; +@@ -1828,11 +2439,10 @@ + fifosize_data_t txfifosize; + + txfifosize.d32 = +- dwc_read_reg32(&GET_CORE_IF(pcd)->core_global_regs-> +- dptxfsiz_dieptxf[ep->dwc_ep. +- tx_fifo_num]); ++ DWC_READ_REG32(&GET_CORE_IF(pcd)->core_global_regs-> ++ dtxfsiz[ep->dwc_ep.tx_fifo_num]); + txstatus.d32 = +- dwc_read_reg32(&GET_CORE_IF(pcd)->dev_if-> ++ DWC_READ_REG32(&GET_CORE_IF(pcd)->dev_if-> + in_ep_regs[ep->dwc_ep.num]->dtxfsts); + + if (txstatus.b.txfspcavail < txfifosize.b.depth) { +@@ -1875,20 +2485,50 @@ + dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); + dsts_data_t dsts; + +- dsts.d32 = dwc_read_reg32(&core_if->dev_if->dev_global_regs->dsts); ++ dsts.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts); + if (!dsts.b.suspsts) { + DWC_WARN("Remote wakeup while is not in suspend state\n"); + } + /* Check if DEVICE_REMOTE_WAKEUP feature enabled */ + if (pcd->remote_wakeup_enable) { + if (set) { ++ ++ if (core_if->adp_enable) { ++ gpwrdn_data_t gpwrdn; ++ ++ dwc_otg_adp_probe_stop(core_if); ++ ++ /* Mask SRP detected interrupt from Power Down Logic */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.srp_det_msk = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs-> ++ gpwrdn, gpwrdn.d32, 0); ++ ++ /* Disable Power Down Logic */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pmuactv = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs-> ++ gpwrdn, gpwrdn.d32, 0); ++ ++ /* ++ * Initialize the Core for Device mode. ++ */ ++ core_if->op_state = B_PERIPHERAL; ++ dwc_otg_core_init(core_if); ++ dwc_otg_enable_global_interrupts(core_if); ++ cil_pcd_start(core_if); ++ ++ dwc_otg_initiate_srp(core_if); ++ } ++ + dctl.b.rmtwkupsig = 1; +- dwc_modify_reg32(&core_if->dev_if->dev_global_regs-> +- dctl, 0, dctl.d32); ++ DWC_MODIFY_REG32(&core_if->dev_if-> ++ dev_global_regs->dctl, 0, dctl.d32); + DWC_DEBUGPL(DBG_PCD, "Set Remote Wakeup\n"); ++ + dwc_mdelay(2); +- dwc_modify_reg32(&core_if->dev_if->dev_global_regs-> +- dctl, dctl.d32, 0); ++ DWC_MODIFY_REG32(&core_if->dev_if-> ++ dev_global_regs->dctl, dctl.d32, 0); + DWC_DEBUGPL(DBG_PCD, "Clear Remote Wakeup\n"); + } + } else { +@@ -1905,7 +2545,7 @@ + glpmcfg_data_t lpmcfg; + dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); + +- lpmcfg.d32 = dwc_read_reg32(&core_if->core_global_regs->glpmcfg); ++ lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg); + + /* Check if we are in L1 state */ + if (!lpmcfg.b.prt_sleep_sts) { +@@ -1925,10 +2565,10 @@ + return; + } + +- lpmcfg.d32 = dwc_read_reg32(&core_if->core_global_regs->glpmcfg); ++ lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg); + lpmcfg.b.en_utmi_sleep = 0; + lpmcfg.b.hird_thres &= (~(1 << 4)); +- dwc_write_reg32(&core_if->core_global_regs->glpmcfg, lpmcfg.d32); ++ DWC_WRITE_REG32(&core_if->core_global_regs->glpmcfg, lpmcfg.d32); + + if (set) { + dctl_data_t dctl = {.d32 = 0 }; +@@ -1936,7 +2576,7 @@ + /* Set RmtWkUpSig bit to start remote wakup signaling. + * Hardware will automatically clear this bit. + */ +- dwc_modify_reg32(&core_if->dev_if->dev_global_regs->dctl, ++ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, + 0, dctl.d32); + DWC_DEBUGPL(DBG_PCD, "Set Remote Wakeup\n"); + } +@@ -1950,7 +2590,9 @@ + void dwc_otg_pcd_remote_wakeup(dwc_otg_pcd_t * pcd, int set) + { + dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); ++ dwc_irqflags_t flags; + if (dwc_otg_is_device_mode(core_if)) { ++ DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags); + #ifdef CONFIG_USB_DWC_OTG_LPM + if (core_if->lx_state == DWC_OTG_L1) { + dwc_otg_pcd_rem_wkup_from_sleep(pcd, set); +@@ -1960,17 +2602,34 @@ + #ifdef CONFIG_USB_DWC_OTG_LPM + } + #endif ++ DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags); + } + return; + } + ++void dwc_otg_pcd_disconnect_us(dwc_otg_pcd_t * pcd, int no_of_usecs) ++{ ++ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); ++ dctl_data_t dctl = { 0 }; ++ ++ if (dwc_otg_is_device_mode(core_if)) { ++ dctl.b.sftdiscon = 1; ++ DWC_PRINTF("Soft disconnect for %d useconds\n",no_of_usecs); ++ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, 0, dctl.d32); ++ dwc_udelay(no_of_usecs); ++ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32,0); ++ ++ } else{ ++ DWC_PRINTF("NOT SUPPORTED IN HOST MODE\n"); ++ } ++ return; ++ ++} ++ + int dwc_otg_pcd_wakeup(dwc_otg_pcd_t * pcd) + { + dsts_data_t dsts; + gotgctl_data_t gotgctl; +- uint64_t flags; +- +- DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags); + + /* + * This function starts the Protocol if no session is in progress. If +@@ -1980,13 +2639,13 @@ + + /* Check if valid session */ + gotgctl.d32 = +- dwc_read_reg32(&(GET_CORE_IF(pcd)->core_global_regs->gotgctl)); ++ DWC_READ_REG32(&(GET_CORE_IF(pcd)->core_global_regs->gotgctl)); + if (gotgctl.b.bsesvld) { + /* Check if suspend state */ + dsts.d32 = +- dwc_read_reg32(& +- (GET_CORE_IF(pcd)->dev_if->dev_global_regs-> +- dsts)); ++ DWC_READ_REG32(& ++ (GET_CORE_IF(pcd)->dev_if-> ++ dev_global_regs->dsts)); + if (dsts.b.suspsts) { + dwc_otg_pcd_remote_wakeup(pcd, 1); + } +@@ -1994,7 +2653,6 @@ + dwc_otg_pcd_initiate_srp(pcd); + } + +- DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags); + return 0; + + } +@@ -2005,33 +2663,12 @@ + * + * @param pcd the pcd structure. + */ +-void dwc_otg_pcd_start_srp_timer(dwc_otg_pcd_t * pcd) +-{ +- GET_CORE_IF(pcd)->srp_timer_started = 1; +- DWC_TIMER_SCHEDULE(pcd->srp_timer, 6000 /* 6 secs */ ); +-} +- + void dwc_otg_pcd_initiate_srp(dwc_otg_pcd_t * pcd) + { +- uint32_t *addr = +- (uint32_t *) & (GET_CORE_IF(pcd)->core_global_regs->gotgctl); +- gotgctl_data_t mem; +- gotgctl_data_t val; +- +- val.d32 = dwc_read_reg32(addr); +- if (val.b.sesreq) { +- DWC_ERROR("Session Request Already active!\n"); +- return; +- } +- +- DWC_INFO("Session Request Initated\n"); //NOTICE +- mem.d32 = dwc_read_reg32(addr); +- mem.b.sesreq = 1; +- dwc_write_reg32(addr, mem.d32); +- +- /* Start the SRP timer */ +- dwc_otg_pcd_start_srp_timer(pcd); +- return; ++ dwc_irqflags_t flags; ++ DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags); ++ dwc_otg_initiate_srp(GET_CORE_IF(pcd)); ++ DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags); + } + + int dwc_otg_pcd_get_frame_number(dwc_otg_pcd_t * pcd) +@@ -2064,4 +2701,4 @@ + return pcd->remote_wakeup_enable; + } + +-#endif /* DWC_HOST_ONLY */ ++#endif /* DWC_HOST_ONLY */ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_pcd.h +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/dwc_otg_pcd.h 2013-07-26 19:31:23.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_pcd.h 2013-07-26 19:34:44.000000000 +0000 +@@ -1,8 +1,8 @@ + /* ========================================================================== + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_pcd.h $ +- * $Revision: #39 $ +- * $Date: 2008/12/16 $ +- * $Change: 1153731 $ ++ * $Revision: #46 $ ++ * $Date: 2011/10/20 $ ++ * $Change: 1870124 $ + * + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless +@@ -34,6 +34,7 @@ + #if !defined(__DWC_PCD_H__) + #define __DWC_PCD_H__ + ++#include "dwc_otg_os_dep.h" + #include "usb.h" + #include "dwc_otg_cil.h" + #include "dwc_otg_pcd_if.h" +@@ -46,7 +47,7 @@ + * the Perpherial Contoller Driver (PCD). + * + * The Peripheral Controller Driver (PCD) for Linux will implement the +- * Gadget API, so that the existing Gadget drivers can be used. For ++ * Gadget API, so that the existing Gadget drivers can be used. For + * the Mass Storage Function driver the File-backed USB Storage Gadget + * (FBS) driver will be used. The FBS driver supports the + * Control-Bulk (CB), Control-Bulk-Interrupt (CBI), and Bulk-Only +@@ -54,12 +55,12 @@ + * + */ + ++/** Invalid DMA Address */ ++#define DWC_DMA_ADDR_INVALID (~(dwc_dma_t)0) ++ + /** Max Transfer size for any EP */ + #define DDMA_MAX_TRANSFER_SIZE 65535 + +-/** Max DMA Descriptor count for any EP */ +-#define MAX_DMA_DESC_CNT 64 +- + /** + * Get the pointer to the core_if from the pcd pointer. + */ +@@ -86,6 +87,42 @@ + */ + typedef struct usb_iso_request dwc_otg_pcd_iso_request_t; + ++#ifdef DWC_UTE_PER_IO ++ ++/** ++ * This shall be the exact analogy of the same type structure defined in the ++ * usb_gadget.h. Each descriptor contains ++ */ ++struct dwc_iso_pkt_desc_port { ++ uint32_t offset; ++ uint32_t length; /* expected length */ ++ uint32_t actual_length; ++ uint32_t status; ++}; ++ ++struct dwc_iso_xreq_port { ++ /** transfer/submission flag */ ++ uint32_t tr_sub_flags; ++ /** Start the request ASAP */ ++#define DWC_EREQ_TF_ASAP 0x00000002 ++ /** Just enqueue the request w/o initiating a transfer */ ++#define DWC_EREQ_TF_ENQUEUE 0x00000004 ++ ++ /** ++ * count of ISO packets attached to this request - shall ++ * not exceed the pio_alloc_pkt_count ++ */ ++ uint32_t pio_pkt_count; ++ /** count of ISO packets allocated for this request */ ++ uint32_t pio_alloc_pkt_count; ++ /** number of ISO packet errors */ ++ uint32_t error_count; ++ /** reserved for future extension */ ++ uint32_t res; ++ /** Will be allocated and freed in the UTE gadget and based on the CFC value */ ++ struct dwc_iso_pkt_desc_port *per_io_frame_descs; ++}; ++#endif + /** DWC_otg request structure. + * This structure is a list of requests. + */ +@@ -96,8 +133,18 @@ + uint32_t length; + uint32_t actual; + unsigned sent_zlp:1; ++ /** ++ * Used instead of original buffer if ++ * it(physical address) is not dword-aligned. ++ **/ ++ uint8_t *dw_align_buf; ++ dwc_dma_t dw_align_buf_dma; + + DWC_CIRCLEQ_ENTRY(dwc_otg_pcd_request) queue_entry; ++#ifdef DWC_UTE_PER_IO ++ struct dwc_iso_xreq_port ext_req; ++ //void *priv_ereq_nport; /* */ ++#endif + } dwc_otg_pcd_request_t; + + DWC_CIRCLEQ_HEAD(req_list, dwc_otg_pcd_request); +@@ -136,6 +183,8 @@ + */ + struct dwc_otg_pcd { + const struct dwc_otg_pcd_function_ops *fops; ++ /** The DWC otg device pointer */ ++ struct dwc_otg_device *otg_dev; + /** Core Interface */ + dwc_otg_core_if_t *core_if; + /** State of EP0 */ +@@ -180,9 +229,6 @@ + /** number of valid EPs in the above array. */ + // unsigned num_eps : 4; + dwc_spinlock_t *lock; +- /** Timer for SRP. If it expires before SRP is successful +- * clear the SRP. */ +- dwc_timer_t *srp_timer; + + /** Tasklet to defer starting of TEST mode transmissions until + * Status Phase has been completed. +@@ -195,7 +241,7 @@ + /** The test mode to enter when the tasklet is executed. */ + unsigned test_mode; + /** The cfi_api structure that implements most of the CFI API +- * and OTG specific core configuration functionality ++ * and OTG specific core configuration functionality + */ + #ifdef DWC_UTE_CFI + struct cfiobject *cfi; +@@ -213,4 +259,4 @@ + + extern void do_test_mode(void *data); + #endif +-#endif /* DWC_HOST_ONLY */ ++#endif /* DWC_HOST_ONLY */ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_pcd_if.h +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/dwc_otg_pcd_if.h 2013-07-26 19:31:23.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_pcd_if.h 2013-07-26 19:34:44.000000000 +0000 +@@ -1,8 +1,8 @@ + /* ========================================================================== + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_pcd_if.h $ +- * $Revision: #6 $ +- * $Date: 2009/04/03 $ +- * $Change: 1225059 $ ++ * $Revision: #11 $ ++ * $Date: 2011/10/26 $ ++ * $Change: 1873028 $ + * + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless +@@ -35,10 +35,10 @@ + #if !defined(__DWC_PCD_IF_H__) + #define __DWC_PCD_IF_H__ + +-#include "dwc_os.h" ++//#include "dwc_os.h" + #include "dwc_otg_core_if.h" + +-/** @file ++/** @file + * This file defines DWC_OTG PCD Core API. + */ + +@@ -103,6 +103,15 @@ + + typedef int (*cfi_setup_cb_t) (dwc_otg_pcd_t * pcd, void *ctrl_req_bytes); + ++/** ++ * ++ * @param ep_handle Void pointer to the usb_ep structure ++ * @param ereq_port Pointer to the extended request structure created in the ++ * portable part. ++ */ ++typedef int (*xiso_completion_cb_t) (dwc_otg_pcd_t * pcd, void *ep_handle, ++ void *req_handle, int32_t status, ++ void *ereq_port); + /** Function Driver Ops Data Structure */ + struct dwc_otg_pcd_function_ops { + dwc_connect_cb_t connect; +@@ -116,6 +125,9 @@ + dwc_reset_cb_t reset; + dwc_hnp_params_changed_cb_t hnp_changed; + cfi_setup_cb_t cfi_setup; ++#ifdef DWC_UTE_PER_IO ++ xiso_completion_cb_t xisoc_complete; ++#endif + }; + /** @} */ + +@@ -156,15 +168,15 @@ + * + * @param pcd The PCD + * @param ep_desc Endpoint descriptor +- * @param ep_handle Handle on endpoint, that will be used to identify endpoint. ++ * @param usb_ep Handle on endpoint, that will be used to identify endpoint. + */ + extern int dwc_otg_pcd_ep_enable(dwc_otg_pcd_t * pcd, +- const uint8_t * ep_desc, void *ep_handle); ++ const uint8_t * ep_desc, void *usb_ep); + + /** Disable the endpoint referenced by ep_handle. + * + * Returns -DWC_E_INVALID if invalid parameters were passed. +- * Returns -DWC_E_SHUTDOWN if any other error ocurred. ++ * Returns -DWC_E_SHUTDOWN if any other error occurred. + * Returns 0 on success. */ + extern int dwc_otg_pcd_ep_disable(dwc_otg_pcd_t * pcd, void *ep_handle); + +@@ -190,6 +202,19 @@ + uint8_t * buf, dwc_dma_t dma_buf, + uint32_t buflen, int zero, void *req_handle, + int atomic_alloc); ++#ifdef DWC_UTE_PER_IO ++/** ++ * ++ * @param ereq_nonport Pointer to the extended request part of the ++ * usb_request structure defined in usb_gadget.h file. ++ */ ++extern int dwc_otg_pcd_xiso_ep_queue(dwc_otg_pcd_t * pcd, void *ep_handle, ++ uint8_t * buf, dwc_dma_t dma_buf, ++ uint32_t buflen, int zero, ++ void *req_handle, int atomic_alloc, ++ void *ereq_nonport); ++ ++#endif + + /** De-queue the specified data transfer that has not yet completed. + * +@@ -307,6 +332,8 @@ + /** Starts remote wakeup signaling. */ + extern void dwc_otg_pcd_remote_wakeup(dwc_otg_pcd_t * pcd, int set); + ++/** Starts micorsecond soft disconnect. */ ++extern void dwc_otg_pcd_disconnect_us(dwc_otg_pcd_t * pcd, int no_of_usecs); + /** This function returns whether device is dualspeed.*/ + extern uint32_t dwc_otg_pcd_is_dualspeed(dwc_otg_pcd_t * pcd); + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_pcd_intr.c +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/dwc_otg_pcd_intr.c 2013-07-26 19:31:23.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_pcd_intr.c 2013-07-26 19:34:44.000000000 +0000 +@@ -1,8 +1,8 @@ + /* ========================================================================== + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_pcd_intr.c $ +- * $Revision: #93 $ +- * $Date: 2009/04/02 $ +- * $Change: 1224216 $ ++ * $Revision: #113 $ ++ * $Date: 2011/10/24 $ ++ * $Change: 1871160 $ + * + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless +@@ -38,6 +38,9 @@ + #include "dwc_otg_cfi.h" + #endif + ++#ifdef DWC_UTE_PER_IO ++extern void complete_xiso_ep(dwc_otg_pcd_ep_t * ep); ++#endif + //#define PRINT_CFI_DMA_DESCS + + #define DEBUG_EP0 +@@ -108,6 +111,40 @@ + #endif + } + ++/** ++ * This function calculate the size of the payload in the memory ++ * for out endpoints and prints size for debug purposes(used in ++ * 2.93a DevOutNak feature). ++ */ ++static inline void print_memory_payload(dwc_otg_pcd_t * pcd, dwc_ep_t * ep) ++{ ++#ifdef DEBUG ++ deptsiz_data_t deptsiz_init = {.d32 = 0 }; ++ deptsiz_data_t deptsiz_updt = {.d32 = 0 }; ++ int pack_num; ++ unsigned payload; ++ ++ deptsiz_init.d32 = pcd->core_if->start_doeptsiz_val[ep->num]; ++ deptsiz_updt.d32 = ++ DWC_READ_REG32(&pcd->core_if->dev_if-> ++ out_ep_regs[ep->num]->doeptsiz); ++ /* Payload will be */ ++ payload = deptsiz_init.b.xfersize - deptsiz_updt.b.xfersize; ++ /* Packet count is decremented every time a packet ++ * is written to the RxFIFO not in to the external memory ++ * So, if payload == 0, then it means no packet was sent to ext memory*/ ++ pack_num = (!payload) ? 0 : (deptsiz_init.b.pktcnt - deptsiz_updt.b.pktcnt); ++ DWC_DEBUGPL(DBG_PCDV, ++ "Payload for EP%d-%s\n", ++ ep->num, (ep->is_in ? "IN" : "OUT")); ++ DWC_DEBUGPL(DBG_PCDV, ++ "Number of transfered bytes = 0x%08x\n", payload); ++ DWC_DEBUGPL(DBG_PCDV, ++ "Number of transfered packets = %d\n", pack_num); ++#endif ++} ++ ++ + #ifdef DWC_UTE_CFI + static inline void print_desc(struct dwc_otg_dma_desc *ddesc, + const uint8_t * epname, int descnum) +@@ -200,48 +237,57 @@ + pcd->cfi->ops.build_descriptors(pcd->cfi, pcd, ep, req); + } else { + #endif +- /* Setup and start the Transfer */ +- ep->dwc_ep.dma_addr = req->dma; +- ep->dwc_ep.start_xfer_buff = req->buf; +- ep->dwc_ep.xfer_buff = req->buf; +- ep->dwc_ep.sent_zlp = 0; +- ep->dwc_ep.total_len = req->length; +- ep->dwc_ep.xfer_len = 0; +- ep->dwc_ep.xfer_count = 0; ++ /* Setup and start the Transfer */ ++ if (req->dw_align_buf) { ++ ep->dwc_ep.dma_addr = req->dw_align_buf_dma; ++ ep->dwc_ep.start_xfer_buff = req->dw_align_buf; ++ ep->dwc_ep.xfer_buff = req->dw_align_buf; ++ } else { ++ ep->dwc_ep.dma_addr = req->dma; ++ ep->dwc_ep.start_xfer_buff = req->buf; ++ ep->dwc_ep.xfer_buff = req->buf; ++ } ++ ep->dwc_ep.sent_zlp = 0; ++ ep->dwc_ep.total_len = req->length; ++ ep->dwc_ep.xfer_len = 0; ++ ep->dwc_ep.xfer_count = 0; + +- ep->dwc_ep.maxxfer = max_transfer; +- if (GET_CORE_IF(ep->pcd)->dma_desc_enable) { +- uint32_t out_max_xfer = DDMA_MAX_TRANSFER_SIZE +- - (DDMA_MAX_TRANSFER_SIZE % 4); +- if (ep->dwc_ep.is_in) { ++ ep->dwc_ep.maxxfer = max_transfer; ++ if (GET_CORE_IF(ep->pcd)->dma_desc_enable) { ++ uint32_t out_max_xfer = DDMA_MAX_TRANSFER_SIZE ++ - (DDMA_MAX_TRANSFER_SIZE % 4); ++ if (ep->dwc_ep.is_in) { + if (ep->dwc_ep.maxxfer > + DDMA_MAX_TRANSFER_SIZE) { +- ep->dwc_ep.maxxfer = +- DDMA_MAX_TRANSFER_SIZE; +- } +- } else { +- if (ep->dwc_ep.maxxfer > out_max_xfer) { ++ ep->dwc_ep.maxxfer = ++ DDMA_MAX_TRANSFER_SIZE; ++ } ++ } else { ++ if (ep->dwc_ep.maxxfer > out_max_xfer) { + ep->dwc_ep.maxxfer = + out_max_xfer; ++ } + } + } +- } +- if (ep->dwc_ep.maxxfer < ep->dwc_ep.total_len) { +- ep->dwc_ep.maxxfer -= +- (ep->dwc_ep.maxxfer % ep->dwc_ep.maxpacket); +- } +- if (req->sent_zlp) { ++ if (ep->dwc_ep.maxxfer < ep->dwc_ep.total_len) { ++ ep->dwc_ep.maxxfer -= ++ (ep->dwc_ep.maxxfer % ep->dwc_ep.maxpacket); ++ } ++ if (req->sent_zlp) { + if ((ep->dwc_ep.total_len % + ep->dwc_ep.maxpacket == 0) + && (ep->dwc_ep.total_len != 0)) { +- ep->dwc_ep.sent_zlp = 1; +- } ++ ep->dwc_ep.sent_zlp = 1; ++ } + +- } ++ } + #ifdef DWC_UTE_CFI + } + #endif + dwc_otg_ep_start_transfer(GET_CORE_IF(ep->pcd), &ep->dwc_ep); ++ } else if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) { ++ DWC_PRINTF("There are no more ISOC requests \n"); ++ ep->dwc_ep.frame_num = 0xFFFFFFFF; + } + } + +@@ -260,7 +306,7 @@ + /* Clear interrupt */ + gintsts.d32 = 0; + gintsts.b.sofintr = 1; +- dwc_write_reg32(&core_if->core_global_regs->gintsts, gintsts.d32); ++ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32); + + return 1; + } +@@ -297,10 +343,10 @@ + //DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, _pcd); + /* Disable the Rx Status Queue Level interrupt */ + gintmask.b.rxstsqlvl = 1; +- dwc_modify_reg32(&global_regs->gintmsk, gintmask.d32, 0); ++ DWC_MODIFY_REG32(&global_regs->gintmsk, gintmask.d32, 0); + + /* Get the Status from the top of the FIFO */ +- status.d32 = dwc_read_reg32(&global_regs->grxstsp); ++ status.d32 = DWC_READ_REG32(&global_regs->grxstsp); + + DWC_DEBUGPL(DBG_PCD, "EP:%d BCnt:%d DPID:%s " + "pktsts:%x Frame:%d(0x%0x)\n", +@@ -353,11 +399,11 @@ + } + + /* Enable the Rx Status Queue Level interrupt */ +- dwc_modify_reg32(&global_regs->gintmsk, 0, gintmask.d32); ++ DWC_MODIFY_REG32(&global_regs->gintmsk, 0, gintmask.d32); + /* Clear interrupt */ + gintsts.d32 = 0; + gintsts.b.rxstsqlvl = 1; +- dwc_write_reg32(&global_regs->gintsts, gintsts.d32); ++ DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32); + + //DWC_DEBUGPL(DBG_PCDV, "EXIT: %s\n", __func__); + return 1; +@@ -393,7 +439,7 @@ + + /* Read the DTKNQ Registers */ + for (i = 0; i < DTKNQ_REG_CNT; i++) { +- in_tkn_epnums[i] = dwc_read_reg32(addr); ++ in_tkn_epnums[i] = DWC_READ_REG32(addr); + DWC_DEBUGPL(DBG_PCDV, "DTKNQR%d=0x%08x\n", i + 1, + in_tkn_epnums[i]); + if (addr == &dev_global_regs->dvbusdis) { +@@ -477,7 +523,7 @@ + + /* While there is space in the queue and space in the FIFO and + * More data to tranfer, Write packets to the Tx FIFO */ +- txstatus.d32 = dwc_read_reg32(&global_regs->gnptxsts); ++ txstatus.d32 = DWC_READ_REG32(&global_regs->gnptxsts); + DWC_DEBUGPL(DBG_PCDV, "b4 GNPTXSTS=0x%08x\n", txstatus.d32); + + while (txstatus.b.nptxqspcavail > 0 && +@@ -492,17 +538,17 @@ + } + + dwords = (len + 3) / 4; +- txstatus.d32 = dwc_read_reg32(&global_regs->gnptxsts); ++ txstatus.d32 = DWC_READ_REG32(&global_regs->gnptxsts); + DWC_DEBUGPL(DBG_PCDV, "GNPTXSTS=0x%08x\n", txstatus.d32); + } + + DWC_DEBUGPL(DBG_PCDV, "GNPTXSTS=0x%08x\n", +- dwc_read_reg32(&global_regs->gnptxsts)); ++ DWC_READ_REG32(&global_regs->gnptxsts)); + + /* Clear interrupt */ + gintsts.d32 = 0; + gintsts.b.nptxfempty = 1; +- dwc_write_reg32(&global_regs->gintsts, gintsts.d32); ++ DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32); + + return 1; + } +@@ -538,7 +584,7 @@ + + /* While there is space in the queue and space in the FIFO and + * More data to tranfer, Write packets to the Tx FIFO */ +- txstatus.d32 = dwc_read_reg32(&dev_if->in_ep_regs[epnum]->dtxfsts); ++ txstatus.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->dtxfsts); + DWC_DEBUGPL(DBG_PCDV, "b4 dtxfsts[%d]=0x%08x\n", epnum, txstatus.d32); + + while (txstatus.b.txfspcavail > dwords && +@@ -554,13 +600,13 @@ + + dwords = (len + 3) / 4; + txstatus.d32 = +- dwc_read_reg32(&dev_if->in_ep_regs[epnum]->dtxfsts); ++ DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->dtxfsts); + DWC_DEBUGPL(DBG_PCDV, "dtxfsts[%d]=0x%08x\n", epnum, + txstatus.d32); + } + + DWC_DEBUGPL(DBG_PCDV, "b4 dtxfsts[%d]=0x%08x\n", epnum, +- dwc_read_reg32(&dev_if->in_ep_regs[epnum]->dtxfsts)); ++ DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->dtxfsts)); + + return 1; + } +@@ -586,6 +632,7 @@ + /* don't disconnect drivers more than once */ + if (pcd->ep0state == EP0_DISCONNECT) { + DWC_DEBUGPL(DBG_ANY, "%s() Already Disconnected\n", __func__); ++ DWC_SPINUNLOCK(pcd->lock); + return; + } + pcd->ep0state = EP0_DISCONNECT; +@@ -595,7 +642,7 @@ + + /* Disable the NP Tx Fifo Empty Interrupt. */ + intr_mask.b.nptxfempty = 1; +- dwc_modify_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk, ++ DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk, + intr_mask.d32, 0); + + /* Flush the FIFOs */ +@@ -636,13 +683,13 @@ + + DWC_PRINTF("INTERRUPT Handler not implemented for %s\n", "i2cintr"); + intr_mask.b.i2cintr = 1; +- dwc_modify_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk, ++ DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk, + intr_mask.d32, 0); + + /* Clear interrupt */ + gintsts.d32 = 0; + gintsts.b.i2cintr = 1; +- dwc_write_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintsts, ++ DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts, + gintsts.d32); + return 1; + } +@@ -656,10 +703,11 @@ + #if defined(VERBOSE) + DWC_PRINTF("Early Suspend Detected\n"); + #endif ++ + /* Clear interrupt */ + gintsts.d32 = 0; + gintsts.b.erlysuspend = 1; +- dwc_write_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintsts, ++ DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts, + gintsts.d32); + return 1; + } +@@ -691,7 +739,7 @@ + + #ifdef VERBOSE + DWC_DEBUGPL(DBG_PCDV, "%s() doepctl0=%0x\n", __func__, +- dwc_read_reg32(&dev_if->out_ep_regs[0]->doepctl)); ++ DWC_READ_REG32(&dev_if->out_ep_regs[0]->doepctl)); + #endif + + doeptsize0.b.supcnt = 3; +@@ -701,11 +749,11 @@ + if (core_if->dma_enable) { + if (!core_if->dma_desc_enable) { + /** put here as for Hermes mode deptisz register should not be written */ +- dwc_write_reg32(&dev_if->out_ep_regs[0]->doeptsiz, ++ DWC_WRITE_REG32(&dev_if->out_ep_regs[0]->doeptsiz, + doeptsize0.d32); + + /** @todo dma needs to handle multiple setup packets (up to 3) */ +- dwc_write_reg32(&dev_if->out_ep_regs[0]->doepdma, ++ DWC_WRITE_REG32(&dev_if->out_ep_regs[0]->doepdma, + pcd->setup_pkt_dma_handle); + } else { + dev_if->setup_desc_index = +@@ -719,35 +767,37 @@ + dma_desc->status.b.ioc = 1; + dma_desc->status.b.bytes = pcd->ep0.dwc_ep.maxpacket; + dma_desc->buf = pcd->setup_pkt_dma_handle; ++ dma_desc->status.b.sts = 0; + dma_desc->status.b.bs = BS_HOST_READY; + + /** DOEPDMA0 Register write */ +- dwc_write_reg32(&dev_if->out_ep_regs[0]->doepdma, +- dev_if->dma_setup_desc_addr[dev_if-> +- setup_desc_index]); ++ DWC_WRITE_REG32(&dev_if->out_ep_regs[0]->doepdma, ++ dev_if-> ++ dma_setup_desc_addr ++ [dev_if->setup_desc_index]); + } + + } else { + /** put here as for Hermes mode deptisz register should not be written */ +- dwc_write_reg32(&dev_if->out_ep_regs[0]->doeptsiz, ++ DWC_WRITE_REG32(&dev_if->out_ep_regs[0]->doeptsiz, + doeptsize0.d32); + } + + /** DOEPCTL0 Register write */ + doepctl.b.epena = 1; + doepctl.b.cnak = 1; +- dwc_write_reg32(&dev_if->out_ep_regs[0]->doepctl, doepctl.d32); ++ DWC_WRITE_REG32(&dev_if->out_ep_regs[0]->doepctl, doepctl.d32); + + #ifdef VERBOSE + DWC_DEBUGPL(DBG_PCDV, "doepctl0=%0x\n", +- dwc_read_reg32(&dev_if->out_ep_regs[0]->doepctl)); ++ DWC_READ_REG32(&dev_if->out_ep_regs[0]->doepctl)); + DWC_DEBUGPL(DBG_PCDV, "diepctl0=%0x\n", +- dwc_read_reg32(&dev_if->in_ep_regs[0]->diepctl)); ++ DWC_READ_REG32(&dev_if->in_ep_regs[0]->diepctl)); + #endif + } + + /** +- * This interrupt occurs when a USB Reset is detected. When the USB ++ * This interrupt occurs when a USB Reset is detected. When the USB + * Reset Interrupt occurs the device state is set to DEFAULT and the + * EP0 state is set to IDLE. + * -# Set the NAK bit for all OUT endpoints (DOEPCTLn.SNAK = 1) +@@ -774,6 +824,7 @@ + dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); + dwc_otg_dev_if_t *dev_if = core_if->dev_if; + depctl_data_t doepctl = {.d32 = 0 }; ++ depctl_data_t diepctl = {.d32 = 0 }; + daint_data_t daintmsk = {.d32 = 0 }; + doepmsk_data_t doepmsk = {.d32 = 0 }; + diepmsk_data_t diepmsk = {.d32 = 0 }; +@@ -784,17 +835,17 @@ + gintsts_data_t gintsts; + pcgcctl_data_t power = {.d32 = 0 }; + +- power.d32 = dwc_read_reg32(core_if->pcgcctl); ++ power.d32 = DWC_READ_REG32(core_if->pcgcctl); + if (power.b.stoppclk) { + power.d32 = 0; + power.b.stoppclk = 1; +- dwc_modify_reg32(core_if->pcgcctl, power.d32, 0); ++ DWC_MODIFY_REG32(core_if->pcgcctl, power.d32, 0); + + power.b.pwrclmp = 1; +- dwc_modify_reg32(core_if->pcgcctl, power.d32, 0); ++ DWC_MODIFY_REG32(core_if->pcgcctl, power.d32, 0); + + power.b.rstpdwnmodule = 1; +- dwc_modify_reg32(core_if->pcgcctl, power.d32, 0); ++ DWC_MODIFY_REG32(core_if->pcgcctl, power.d32, 0); + } + + core_if->lx_state = DWC_OTG_L0; +@@ -810,31 +861,54 @@ + dwc_ep->next_frame = 0xffffffff; + } + } +-#endif /* DWC_EN_ISOC */ ++#endif /* DWC_EN_ISOC */ + + /* reset the HNP settings */ + dwc_otg_pcd_update_otg(pcd, 1); + + /* Clear the Remote Wakeup Signalling */ + dctl.b.rmtwkupsig = 1; +- dwc_modify_reg32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32, 0); ++ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32, 0); + + /* Set NAK for all OUT EPs */ + doepctl.b.snak = 1; + for (i = 0; i <= dev_if->num_out_eps; i++) { +- dwc_write_reg32(&dev_if->out_ep_regs[i]->doepctl, doepctl.d32); ++ DWC_WRITE_REG32(&dev_if->out_ep_regs[i]->doepctl, doepctl.d32); + } + + /* Flush the NP Tx FIFO */ + dwc_otg_flush_tx_fifo(core_if, 0x10); + /* Flush the Learning Queue */ + resetctl.b.intknqflsh = 1; +- dwc_write_reg32(&core_if->core_global_regs->grstctl, resetctl.d32); ++ DWC_WRITE_REG32(&core_if->core_global_regs->grstctl, resetctl.d32); ++ ++ if (!core_if->core_params->en_multiple_tx_fifo && core_if->dma_enable) { ++ core_if->start_predict = 0; ++ for (i = 0; i<= core_if->dev_if->num_in_eps; ++i) { ++ core_if->nextep_seq[i] = 0xff; // 0xff - EP not active ++ } ++ core_if->nextep_seq[0] = 0; ++ core_if->first_in_nextep_seq = 0; ++ diepctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[0]->diepctl); ++ diepctl.b.nextep = 0; ++ DWC_WRITE_REG32(&dev_if->in_ep_regs[0]->diepctl, diepctl.d32); ++ ++ /* Update IN Endpoint Mismatch Count by active IN NP EP count + 1 */ ++ dcfg.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->dcfg); ++ dcfg.b.epmscnt = 2; ++ DWC_WRITE_REG32(&dev_if->dev_global_regs->dcfg, dcfg.d32); ++ ++ DWC_DEBUGPL(DBG_PCDV,"%s first_in_nextep_seq= %2d; nextep_seq[]:\n", ++ __func__, core_if->first_in_nextep_seq); ++ for (i=0; i <= core_if->dev_if->num_in_eps; i++) { ++ DWC_DEBUGPL(DBG_PCDV, "%2d\n", core_if->nextep_seq[i]); ++ } ++ } + + if (core_if->multiproc_int_enable) { + daintmsk.b.inep0 = 1; + daintmsk.b.outep0 = 1; +- dwc_write_reg32(&dev_if->dev_global_regs->deachintmsk, ++ DWC_WRITE_REG32(&dev_if->dev_global_regs->deachintmsk, + daintmsk.d32); + + doepmsk.b.setup = 1; +@@ -850,33 +924,36 @@ + doepmsk.b.babble = 1; + doepmsk.b.nyet = 1; + +- if(core_if->dma_enable) { ++ if (core_if->dma_enable) { + doepmsk.b.nak = 1; + } + */ +- dwc_write_reg32(&dev_if->dev_global_regs->doepeachintmsk[0], ++ DWC_WRITE_REG32(&dev_if->dev_global_regs->doepeachintmsk[0], + doepmsk.d32); + + diepmsk.b.xfercompl = 1; + diepmsk.b.timeout = 1; + diepmsk.b.epdisabled = 1; + diepmsk.b.ahberr = 1; +- diepmsk.b.intknepmis = 1; ++ diepmsk.b.intknepmis = 1; ++ if (!core_if->en_multiple_tx_fifo && core_if->dma_enable) ++ diepmsk.b.intknepmis = 0; + +- if (core_if->dma_desc_enable) { ++/* if (core_if->dma_desc_enable) { + diepmsk.b.bna = 1; + } ++*/ + /* +- if(core_if->dma_enable) { ++ if (core_if->dma_enable) { + diepmsk.b.nak = 1; + } + */ +- dwc_write_reg32(&dev_if->dev_global_regs->diepeachintmsk[0], ++ DWC_WRITE_REG32(&dev_if->dev_global_regs->diepeachintmsk[0], + diepmsk.d32); + } else { + daintmsk.b.inep0 = 1; + daintmsk.b.outep0 = 1; +- dwc_write_reg32(&dev_if->dev_global_regs->daintmsk, ++ DWC_WRITE_REG32(&dev_if->dev_global_regs->daintmsk, + daintmsk.d32); + + doepmsk.b.setup = 1; +@@ -888,25 +965,27 @@ + doepmsk.b.stsphsercvd = 1; + doepmsk.b.bna = 1; + } +- dwc_write_reg32(&dev_if->dev_global_regs->doepmsk, doepmsk.d32); ++ DWC_WRITE_REG32(&dev_if->dev_global_regs->doepmsk, doepmsk.d32); + + diepmsk.b.xfercompl = 1; + diepmsk.b.timeout = 1; + diepmsk.b.epdisabled = 1; + diepmsk.b.ahberr = 1; +- diepmsk.b.intknepmis = 1; +- ++ if (!core_if->en_multiple_tx_fifo && core_if->dma_enable) ++ diepmsk.b.intknepmis = 0; ++/* + if (core_if->dma_desc_enable) { + diepmsk.b.bna = 1; + } ++*/ + +- dwc_write_reg32(&dev_if->dev_global_regs->diepmsk, diepmsk.d32); ++ DWC_WRITE_REG32(&dev_if->dev_global_regs->diepmsk, diepmsk.d32); + } + + /* Reset Device Address */ +- dcfg.d32 = dwc_read_reg32(&dev_if->dev_global_regs->dcfg); ++ dcfg.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->dcfg); + dcfg.b.devaddr = 0; +- dwc_write_reg32(&dev_if->dev_global_regs->dcfg, dcfg.d32); ++ DWC_WRITE_REG32(&dev_if->dev_global_regs->dcfg, dcfg.d32); + + /* setup EP0 to receive SETUP packets */ + ep0_out_start(core_if, pcd); +@@ -914,7 +993,7 @@ + /* Clear interrupt */ + gintsts.d32 = 0; + gintsts.b.usbreset = 1; +- dwc_write_reg32(&core_if->core_global_regs->gintsts, gintsts.d32); ++ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32); + + return 1; + } +@@ -929,7 +1008,7 @@ + { + dsts_data_t dsts; + int speed = 0; +- dsts.d32 = dwc_read_reg32(&core_if->dev_if->dev_global_regs->dsts); ++ dsts.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts); + + switch (dsts.b.enumspd) { + case DWC_DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ: +@@ -965,7 +1044,7 @@ + DWC_DEBUGPL(DBG_PCD, "SPEED ENUM\n"); + + if (GET_CORE_IF(pcd)->snpsid >= OTG_CORE_REV_2_60a) { +- utmi16b = 6; ++ utmi16b = 6; //vahrama old value was 6; + utmi8b = 9; + } else { + utmi16b = 4; +@@ -991,7 +1070,7 @@ + pcd->fops->connect(pcd, speed); + + /* Set USB turnaround time based on device speed and PHY interface. */ +- gusbcfg.d32 = dwc_read_reg32(&global_regs->gusbcfg); ++ gusbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg); + if (speed == USB_SPEED_HIGH) { + if (GET_CORE_IF(pcd)->hwcfg2.b.hs_phy_type == + DWC_HWCFG2_HS_PHY_TYPE_ULPI) { +@@ -1003,11 +1082,11 @@ + /* UTMI+ interface */ + if (GET_CORE_IF(pcd)->hwcfg4.b.utmi_phy_data_width == 0) { + gusbcfg.b.usbtrdtim = utmi8b; +- } else if (GET_CORE_IF(pcd)->hwcfg4.b. +- utmi_phy_data_width == 1) { ++ } else if (GET_CORE_IF(pcd)->hwcfg4. ++ b.utmi_phy_data_width == 1) { + gusbcfg.b.usbtrdtim = utmi16b; +- } else if (GET_CORE_IF(pcd)->core_params-> +- phy_utmi_width == 8) { ++ } else if (GET_CORE_IF(pcd)-> ++ core_params->phy_utmi_width == 8) { + gusbcfg.b.usbtrdtim = utmi8b; + } else { + gusbcfg.b.usbtrdtim = utmi16b; +@@ -1021,8 +1100,8 @@ + gusbcfg.b.usbtrdtim = 9; + } else { + /* UTMI+ interface */ +- if (GET_CORE_IF(pcd)->core_params-> +- phy_utmi_width == 16) { ++ if (GET_CORE_IF(pcd)-> ++ core_params->phy_utmi_width == 16) { + gusbcfg.b.usbtrdtim = utmi16b; + } else { + gusbcfg.b.usbtrdtim = utmi8b; +@@ -1033,12 +1112,12 @@ + /* Full or low speed */ + gusbcfg.b.usbtrdtim = 9; + } +- dwc_write_reg32(&global_regs->gusbcfg, gusbcfg.d32); ++ DWC_WRITE_REG32(&global_regs->gusbcfg, gusbcfg.d32); + + /* Clear interrupt */ + gintsts.d32 = 0; + gintsts.b.enumdone = 1; +- dwc_write_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintsts, ++ DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts, + gintsts.d32); + return 1; + } +@@ -1053,17 +1132,17 @@ + gintmsk_data_t intr_mask = {.d32 = 0 }; + gintsts_data_t gintsts; + +- DWC_PRINTF("INTERRUPT Handler not implemented for %s\n", +- "ISOC Out Dropped"); ++ DWC_WARN("INTERRUPT Handler not implemented for %s\n", ++ "ISOC Out Dropped"); + + intr_mask.b.isooutdrop = 1; +- dwc_modify_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk, ++ DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk, + intr_mask.d32, 0); + + /* Clear interrupt */ + gintsts.d32 = 0; + gintsts.b.isooutdrop = 1; +- dwc_write_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintsts, ++ DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts, + gintsts.d32); + + return 1; +@@ -1081,13 +1160,13 @@ + DWC_PRINTF("INTERRUPT Handler not implemented for %s\n", "EOP"); + + intr_mask.b.eopframe = 1; +- dwc_modify_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk, ++ DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk, + intr_mask.d32, 0); + + /* Clear interrupt */ + gintsts.d32 = 0; + gintsts.b.eopframe = 1; +- dwc_write_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintsts, ++ DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts, + gintsts.d32); + + return 1; +@@ -1098,24 +1177,84 @@ + * non-periodic Tx FIFO does not match EP of the IN Token received. + * + * The "Device IN Token Queue" Registers are read to determine the +- * order the IN Tokens have been received. The non-periodic Tx FIFO ++ * order the IN Tokens have been received. The non-periodic Tx FIFO + * is flushed, so it can be reloaded in the order seen in the IN Token + * Queue. + */ +-int32_t dwc_otg_pcd_handle_ep_mismatch_intr(dwc_otg_core_if_t * core_if) ++int32_t dwc_otg_pcd_handle_ep_mismatch_intr(dwc_otg_pcd_t * pcd) + { + gintsts_data_t gintsts; +- DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, core_if); ++ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); ++ dctl_data_t dctl; ++ gintmsk_data_t intr_mask = {.d32 = 0 }; + ++ if (!core_if->en_multiple_tx_fifo && core_if->dma_enable) { ++ core_if->start_predict = 1; ++ ++ DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, core_if); ++ ++ gintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts); ++ if (!gintsts.b.ginnakeff) { ++ /* Disable EP Mismatch interrupt */ ++ intr_mask.d32 = 0; ++ intr_mask.b.epmismatch = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, intr_mask.d32, 0); ++ /* Enable the Global IN NAK Effective Interrupt */ ++ intr_mask.d32 = 0; ++ intr_mask.b.ginnakeff = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, 0, intr_mask.d32); ++ /* Set the global non-periodic IN NAK handshake */ ++ dctl.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dctl); ++ dctl.b.sgnpinnak = 1; ++ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32); ++ } else { ++ DWC_PRINTF("gintsts.b.ginnakeff = 1! dctl.b.sgnpinnak not set\n"); ++ } ++ /* Disabling of all EP's will be done in dwc_otg_pcd_handle_in_nak_effective() ++ * handler after Global IN NAK Effective interrupt will be asserted */ ++ } + /* Clear interrupt */ + gintsts.d32 = 0; + gintsts.b.epmismatch = 1; +- dwc_write_reg32(&core_if->core_global_regs->gintsts, gintsts.d32); ++ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32); + + return 1; + } + + /** ++ * This interrupt is valid only in DMA mode. This interrupt indicates that the ++ * core has stopped fetching data for IN endpoints due to the unavailability of ++ * TxFIFO space or Request Queue space. This interrupt is used by the ++ * application for an endpoint mismatch algorithm. ++ * ++ * @param pcd The PCD ++ */ ++int32_t dwc_otg_pcd_handle_ep_fetsusp_intr(dwc_otg_pcd_t * pcd) ++{ ++ gintsts_data_t gintsts; ++ gintmsk_data_t gintmsk_data; ++ dctl_data_t dctl; ++ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); ++ DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, core_if); ++ ++ /* Clear the global non-periodic IN NAK handshake */ ++ dctl.d32 = 0; ++ dctl.b.cgnpinnak = 1; ++ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32, dctl.d32); ++ ++ /* Mask GINTSTS.FETSUSP interrupt */ ++ gintmsk_data.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintmsk); ++ gintmsk_data.b.fetsusp = 0; ++ DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, gintmsk_data.d32); ++ ++ /* Clear interrupt */ ++ gintsts.d32 = 0; ++ gintsts.b.fetsusp = 1; ++ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32); ++ ++ return 1; ++} ++/** + * This funcion stalls EP0. + */ + static inline void ep0_do_stall(dwc_otg_pcd_t * pcd, const int err_val) +@@ -1149,12 +1288,12 @@ + /** @todo This is a g_file_storage gadget driver specific + * workaround: a DELAYED_STATUS result from the fsg_setup + * routine will result in the gadget queueing a EP0 IN status +- * phase for a two-stage control transfer. Exactly the same as ++ * phase for a two-stage control transfer. Exactly the same as + * a SET_CONFIGURATION/SET_INTERFACE except that this is a class + * specific request. Need a generic way to know when the gadget +- * driver will queue the status phase. Can we assume when we ++ * driver will queue the status phase. Can we assume when we + * call the gadget driver setup() function that it will always +- * queue and require the following flag? Need to look into ++ * queue and require the following flag? Need to look into + * this. + */ + +@@ -1290,7 +1429,7 @@ + + // DWC_WARN("%s() has not been tested since being rewritten!\n", __func__); + +- dctl.d32 = dwc_read_reg32(&core_if->dev_if->dev_global_regs->dctl); ++ dctl.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dctl); + switch (test_mode) { + case 1: // TEST_J + dctl.b.tstctl = 1; +@@ -1312,7 +1451,7 @@ + dctl.b.tstctl = 5; + break; + } +- dwc_write_reg32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32); ++ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32); + } + + /** +@@ -1324,6 +1463,7 @@ + dwc_otg_pcd_ep_t *ep; + dwc_otg_pcd_ep_t *ep0 = &pcd->ep0; + uint16_t *status = pcd->status_buf; ++ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); + + #ifdef DEBUG_EP0 + DWC_DEBUGPL(DBG_PCD, +@@ -1335,10 +1475,34 @@ + + switch (UT_GET_RECIPIENT(ctrl.bmRequestType)) { + case UT_DEVICE: +- *status = 0x1; /* Self powered */ +- *status |= pcd->remote_wakeup_enable << 1; +- break; +- ++ if(UGETW(ctrl.wIndex) == 0xF000) { /* OTG Status selector */ ++ DWC_PRINTF("wIndex - %d\n", UGETW(ctrl.wIndex)); ++ DWC_PRINTF("OTG VERSION - %d\n", core_if->otg_ver); ++ DWC_PRINTF("OTG CAP - %d, %d\n", core_if->core_params->otg_cap, ++ DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE); ++ if(core_if->otg_ver == 1 && ++ core_if->core_params->otg_cap == DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE) { ++ uint8_t *otgsts = (uint8_t*)pcd->status_buf; ++ *otgsts = (core_if->otg_sts & 0x1); ++ pcd->ep0_pending = 1; ++ ep0->dwc_ep.start_xfer_buff = (uint8_t *) otgsts; ++ ep0->dwc_ep.xfer_buff = (uint8_t *) otgsts; ++ ep0->dwc_ep.dma_addr = pcd->status_buf_dma_handle; ++ ep0->dwc_ep.xfer_len = 1; ++ ep0->dwc_ep.xfer_count = 0; ++ ep0->dwc_ep.total_len = ep0->dwc_ep.xfer_len; ++ dwc_otg_ep0_start_transfer(GET_CORE_IF(pcd), &ep0->dwc_ep); ++ return; ++ } else { ++ ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED); ++ return; ++ } ++ break; ++ } else { ++ *status = 0x1; /* Self powered */ ++ *status |= pcd->remote_wakeup_enable << 1; ++ break; ++ } + case UT_INTERFACE: + *status = 0; + break; +@@ -1413,10 +1577,11 @@ + * by a USB Reset? */ + gotgctl.b.devhnpen = 1; + gotgctl.b.hnpreq = 1; +- dwc_write_reg32(&global_regs->gotgctl, ++ DWC_WRITE_REG32(&global_regs->gotgctl, + gotgctl.d32); + } else { + ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED); ++ return; + } + break; + +@@ -1429,6 +1594,7 @@ + dwc_otg_pcd_update_otg(pcd, 0); + } else { + ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED); ++ return; + } + break; + +@@ -1441,8 +1607,14 @@ + dwc_otg_pcd_update_otg(pcd, 0); + } else { + ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED); ++ return; + } + break; ++ ++ default: ++ ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED); ++ return; ++ + } + do_setup_in_status_phase(pcd); + break; +@@ -1490,6 +1662,10 @@ + case UF_TEST_MODE: + /** @todo Add CLEAR_FEATURE for TEST modes. */ + break; ++ ++ default: ++ ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED); ++ return; + } + do_setup_in_status_phase(pcd); + break; +@@ -1522,13 +1698,13 @@ + // DWC_DEBUGPL(DBG_PCDV, "SET_ADDRESS:%d\n", ctrl.wValue); + #endif + dcfg.b.devaddr = UGETW(ctrl.wValue); +- dwc_modify_reg32(&dev_if->dev_global_regs->dcfg, 0, dcfg.d32); ++ DWC_MODIFY_REG32(&dev_if->dev_global_regs->dcfg, 0, dcfg.d32); + do_setup_in_status_phase(pcd); + } + } + + /** +- * This function processes SETUP commands. In Linux, the USB Command ++ * This function processes SETUP commands. In Linux, the USB Command + * processing is done in two places - the first being the PCD and the + * second in the Gadget Driver (for example, the File-Backed Storage + * Gadget Driver). +@@ -1598,7 +1774,7 @@ + UGETW(ctrl.wLength)); + #endif + +- doeptsize0.d32 = dwc_read_reg32(&dev_if->out_ep_regs[0]->doeptsiz); ++ doeptsize0.d32 = DWC_READ_REG32(&dev_if->out_ep_regs[0]->doeptsiz); + + /** @todo handle > 1 setup packet , assert error for now */ + +@@ -1630,7 +1806,8 @@ + #ifdef DWC_UTE_CFI + DWC_MEMCPY(&cfi_req, &ctrl, sizeof(usb_device_request_t)); + +- //printk(KERN_ALERT "CFI: req_type=0x%02x; req=0x%02x\n", ctrl.bRequestType, ctrl.bRequest); ++ //printk(KERN_ALERT "CFI: req_type=0x%02x; req=0x%02x\n", ++ ctrl.bRequestType, ctrl.bRequest); + if (UT_GET_TYPE(cfi_req.bRequestType) == UT_VENDOR) { + if (cfi_req.bRequest > 0xB0 && cfi_req.bRequest < 0xBF) { + retval = cfi_setup(pcd, &cfi_req); +@@ -1644,8 +1821,8 @@ + if (pcd->cfi->need_gadget_att) { + retval = + cfi_gadget_setup(pcd, +- &pcd->cfi-> +- ctrl_req); ++ &pcd-> ++ cfi->ctrl_req); + if (retval < 0) { + pcd->ep0_pending = 0; + return; +@@ -1728,6 +1905,8 @@ + int retval = -DWC_E_NOT_SUPPORTED; + #endif + ++ desc_sts.b.bytes = 0; ++ + if (pcd->ep0_pending && DWC_CIRCLEQ_EMPTY(&ep->queue)) { + if (ep->dwc_ep.is_in) { + #ifdef DEBUG_EP0 +@@ -1809,7 +1988,7 @@ + || pcd->ep0state == EP0_IN_STATUS_PHASE) { + is_last = 1; + } else if (ep->dwc_ep.is_in) { +- deptsiz.d32 = dwc_read_reg32(&in_ep_regs->dieptsiz); ++ deptsiz.d32 = DWC_READ_REG32(&in_ep_regs->dieptsiz); + if (core_if->dma_desc_enable != 0) + desc_sts = dev_if->in_desc_addr->status; + #ifdef DEBUG_EP0 +@@ -1835,7 +2014,7 @@ + } else { + /* ep0-OUT */ + #ifdef DEBUG_EP0 +- deptsiz.d32 = dwc_read_reg32(&out_ep_regs->doeptsiz); ++ deptsiz.d32 = DWC_READ_REG32(&out_ep_regs->doeptsiz); + DWC_DEBUGPL(DBG_PCDV, "%d len=%d xsize=%d pktcnt=%d\n", + ep->dwc_ep.num, ep->dwc_ep.xfer_len, + deptsiz.b.xfersize, deptsiz.b.pktcnt); +@@ -1905,7 +2084,7 @@ + #endif + + /** +- * This function completes the request for the EP. If there are ++ * This function completes the request for the EP. If there are + * additional requests for the EP in the queue they will be started. + */ + static void complete_ep(dwc_otg_pcd_ep_t * ep) +@@ -1940,7 +2119,7 @@ + DWC_DEBUGPL(DBG_PCD, "Requests %d\n", ep->pcd->request_pending); + + if (ep->dwc_ep.is_in) { +- deptsiz.d32 = dwc_read_reg32(&in_ep_regs->dieptsiz); ++ deptsiz.d32 = DWC_READ_REG32(&in_ep_regs->dieptsiz); + + if (core_if->dma_enable) { + if (core_if->dma_desc_enable == 0) { +@@ -1968,20 +2147,20 @@ + dwc_otg_ep_start_transfer + (core_if, &ep->dwc_ep); + } else if (ep->dwc_ep.sent_zlp) { +- /* +- * This fragment of code should initiate 0 +- * length trasfer in case if it is queued +- * a trasfer with size divisible to EPs max +- * packet size and with usb_request zero field +- * is set, which means that after data is transfered, +- * it is also should be transfered +- * a 0 length packet at the end. For Slave and +- * Buffer DMA modes in this case SW has +- * to initiate 2 transfers one with transfer size, +- * and the second with 0 size. For Desriptor +- * DMA mode SW is able to initiate a transfer, +- * which will handle all the packets including +- * the last 0 legth. ++ /* ++ * This fragment of code should initiate 0 ++ * length transfer in case if it is queued ++ * a transfer with size divisible to EPs max ++ * packet size and with usb_request zero field ++ * is set, which means that after data is transfered, ++ * it is also should be transfered ++ * a 0 length packet at the end. For Slave and ++ * Buffer DMA modes in this case SW has ++ * to initiate 2 transfers one with transfer size, ++ * and the second with 0 size. For Descriptor ++ * DMA mode SW is able to initiate a transfer, ++ * which will handle all the packets including ++ * the last 0 length. + */ + ep->dwc_ep.sent_zlp = 0; + dwc_otg_ep_start_zl_transfer +@@ -1990,12 +2169,24 @@ + is_last = 1; + } + } else { +- DWC_WARN +- ("Incomplete transfer (%d - %s [siz=%d pkt=%d])\n", +- ep->dwc_ep.num, +- (ep->dwc_ep.is_in ? "IN" : "OUT"), +- deptsiz.b.xfersize, +- deptsiz.b.pktcnt); ++ if(ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) ++ { ++ req->actual = 0; ++ dwc_otg_request_done(ep, req, 0); ++ ++ ep->dwc_ep.start_xfer_buff = 0; ++ ep->dwc_ep.xfer_buff = 0; ++ ep->dwc_ep.xfer_len = 0; ++ ++ /* If there is a request in the queue start it. */ ++ start_next_request(ep); ++ } else ++ DWC_WARN ++ ("Incomplete transfer (%d - %s [siz=%d pkt=%d])\n", ++ ep->dwc_ep.num, ++ (ep->dwc_ep.is_in ? "IN" : "OUT"), ++ deptsiz.b.xfersize, ++ deptsiz.b.pktcnt); + } + } else { + dma_desc = ep->dwc_ep.desc_addr; +@@ -2042,32 +2233,31 @@ + deptsiz.b.xfersize, + deptsiz.b.pktcnt); + +- /* Check if the whole transfer was completed, ++ /* Check if the whole transfer was completed, + * if no, setup transfer for next portion of data + */ + if (ep->dwc_ep.xfer_len < ep->dwc_ep.total_len) { + dwc_otg_ep_start_transfer(core_if, + &ep->dwc_ep); + } else if (ep->dwc_ep.sent_zlp) { +- /* +- * This fragment of code should initiate 0 ++ /* ++ * This fragment of code should initiate 0 + * length trasfer in case if it is queued +- * a trasfer with size divisible to EPs max +- * packet size and with usb_request zero field +- * is set, which means that after data is transfered, +- * it is also should be transfered +- * a 0 length packet at the end. For Slave and +- * Buffer DMA modes in this case SW has +- * to initiate 2 transfers one with transfer size, +- * and the second with 0 size. For Desriptor +- * DMA mode SW is able to initiate a transfer, +- * which will handle all the packets including ++ * a trasfer with size divisible to EPs max ++ * packet size and with usb_request zero field ++ * is set, which means that after data is transfered, ++ * it is also should be transfered ++ * a 0 length packet at the end. For Slave and ++ * Buffer DMA modes in this case SW has ++ * to initiate 2 transfers one with transfer size, ++ * and the second with 0 size. For Desriptor ++ * DMA mode SW is able to initiate a transfer, ++ * which will handle all the packets including + * the last 0 legth. + */ + ep->dwc_ep.sent_zlp = 0; + dwc_otg_ep_start_zl_transfer(core_if, +- &ep-> +- dwc_ep); ++ &ep->dwc_ep); + } else { + is_last = 1; + } +@@ -2103,22 +2293,44 @@ + + for (i = 0; i < ep->dwc_ep.desc_cnt; + ++i) { +- desc_sts = dma_desc->status; +- byte_count += desc_sts.b.bytes; +- dma_desc++; +- } ++ desc_sts = dma_desc->status; ++ byte_count += desc_sts.b.bytes; ++ dma_desc++; ++ } + + #ifdef DWC_UTE_CFI + } + #endif +- ep->dwc_ep.xfer_count = ep->dwc_ep.total_len +- - byte_count + +- ((4 - (ep->dwc_ep.total_len & 0x3)) & 0x3); +- is_last = 1; ++ /* Checking for interrupt Out transfers with not ++ * dword aligned mps sizes ++ */ ++ if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_INTR && ++ (ep->dwc_ep.maxpacket%4)) { ++ ep->dwc_ep.xfer_count = ep->dwc_ep.total_len - byte_count; ++ if ((ep->dwc_ep.xfer_len % ep->dwc_ep.maxpacket) && ++ (ep->dwc_ep.xfer_len/ep->dwc_ep.maxpacket < MAX_DMA_DESC_CNT)) ++ ep->dwc_ep.xfer_len -= ++ (ep->dwc_ep.desc_cnt - 1) * ep->dwc_ep.maxpacket + ++ ep->dwc_ep.xfer_len % ep->dwc_ep.maxpacket; ++ else ++ ep->dwc_ep.xfer_len -= ++ ep->dwc_ep.desc_cnt * ep->dwc_ep.maxpacket; ++ if (ep->dwc_ep.xfer_len > 0) { ++ dwc_otg_ep_start_transfer(core_if, ++ &ep->dwc_ep); ++ } else { ++ is_last = 1; ++ } ++ } else { ++ ep->dwc_ep.xfer_count = ep->dwc_ep.total_len ++ - byte_count + ++ ((4 - (ep->dwc_ep.total_len & 0x3)) & 0x3); ++ is_last = 1; ++ } + } else { + deptsiz.d32 = 0; + deptsiz.d32 = +- dwc_read_reg32(&out_ep_regs->doeptsiz); ++ DWC_READ_REG32(&out_ep_regs->doeptsiz); + + byte_count = (ep->dwc_ep.xfer_len - + ep->dwc_ep.xfer_count - +@@ -2127,57 +2339,56 @@ + ep->dwc_ep.dma_addr += byte_count; + ep->dwc_ep.xfer_count += byte_count; + +- /* Check if the whole transfer was completed, ++ /* Check if the whole transfer was completed, + * if no, setup transfer for next portion of data + */ + if (ep->dwc_ep.xfer_len < ep->dwc_ep.total_len) { + dwc_otg_ep_start_transfer(core_if, + &ep->dwc_ep); + } else if (ep->dwc_ep.sent_zlp) { +- /* +- * This fragment of code should initiate 0 ++ /* ++ * This fragment of code should initiate 0 + * length trasfer in case if it is queued +- * a trasfer with size divisible to EPs max +- * packet size and with usb_request zero field +- * is set, which means that after data is transfered, +- * it is also should be transfered +- * a 0 length packet at the end. For Slave and +- * Buffer DMA modes in this case SW has +- * to initiate 2 transfers one with transfer size, +- * and the second with 0 size. For Desriptor +- * DMA mode SW is able to initiate a transfer, +- * which will handle all the packets including ++ * a trasfer with size divisible to EPs max ++ * packet size and with usb_request zero field ++ * is set, which means that after data is transfered, ++ * it is also should be transfered ++ * a 0 length packet at the end. For Slave and ++ * Buffer DMA modes in this case SW has ++ * to initiate 2 transfers one with transfer size, ++ * and the second with 0 size. For Desriptor ++ * DMA mode SW is able to initiate a transfer, ++ * which will handle all the packets including + * the last 0 legth. + */ + ep->dwc_ep.sent_zlp = 0; + dwc_otg_ep_start_zl_transfer(core_if, +- &ep-> +- dwc_ep); ++ &ep->dwc_ep); + } else { + is_last = 1; + } + } + } else { +- /* Check if the whole transfer was completed, ++ /* Check if the whole transfer was completed, + * if no, setup transfer for next portion of data + */ + if (ep->dwc_ep.xfer_len < ep->dwc_ep.total_len) { + dwc_otg_ep_start_transfer(core_if, &ep->dwc_ep); + } else if (ep->dwc_ep.sent_zlp) { +- /* +- * This fragment of code should initiate 0 +- * length trasfer in case if it is queued +- * a trasfer with size divisible to EPs max +- * packet size and with usb_request zero field +- * is set, which means that after data is transfered, +- * it is also should be transfered +- * a 0 length packet at the end. For Slave and +- * Buffer DMA modes in this case SW has +- * to initiate 2 transfers one with transfer size, +- * and the second with 0 size. For Desriptor +- * DMA mode SW is able to initiate a transfer, +- * which will handle all the packets including +- * the last 0 legth. ++ /* ++ * This fragment of code should initiate 0 ++ * length transfer in case if it is queued ++ * a transfer with size divisible to EPs max ++ * packet size and with usb_request zero field ++ * is set, which means that after data is transfered, ++ * it is also should be transfered ++ * a 0 length packet at the end. For Slave and ++ * Buffer DMA modes in this case SW has ++ * to initiate 2 transfers one with transfer size, ++ * and the second with 0 size. For Descriptor ++ * DMA mode SW is able to initiate a transfer, ++ * which will handle all the packets including ++ * the last 0 length. + */ + ep->dwc_ep.sent_zlp = 0; + dwc_otg_ep_start_zl_transfer(core_if, +@@ -2202,10 +2413,17 @@ + req->actual = ep->dwc_ep.cfi_req_len - byte_count; + } else { + #endif +- req->actual = ep->dwc_ep.xfer_count; ++ req->actual = ep->dwc_ep.xfer_count; + #ifdef DWC_UTE_CFI + } + #endif ++ if (req->dw_align_buf) { ++ if (!ep->dwc_ep.is_in) { ++ dwc_memcpy(req->buf, req->dw_align_buf, req->length); ++ } ++ DWC_DMA_FREE(req->length, req->dw_align_buf, ++ req->dw_align_buf_dma); ++ } + + dwc_otg_request_done(ep, req, 0); + +@@ -2254,14 +2472,14 @@ + + if (dwc_ep->is_in == 0) { + addr = +- &GET_CORE_IF(pcd)->dev_if->out_ep_regs[dwc_ep->num]-> +- doepctl; ++ &GET_CORE_IF(pcd)->dev_if->out_ep_regs[dwc_ep-> ++ num]->doepctl; + } else { + addr = + &GET_CORE_IF(pcd)->dev_if->in_ep_regs[dwc_ep->num]->diepctl; + } + depctl.b.epena = 1; +- dwc_modify_reg32(addr, depctl.d32, depctl.d32); ++ DWC_MODIFY_REG32(addr, depctl.d32, depctl.d32); + } + + /** +@@ -2284,13 +2502,13 @@ + + if (ep->is_in) { + deptsiz.d32 = +- dwc_read_reg32(&core_if->dev_if->in_ep_regs[ep->num]-> +- dieptsiz); ++ DWC_READ_REG32(&core_if->dev_if-> ++ in_ep_regs[ep->num]->dieptsiz); + offset = ep->data_per_frame; + } else { + deptsiz.d32 = +- dwc_read_reg32(&core_if->dev_if->out_ep_regs[ep->num]-> +- doeptsiz); ++ DWC_READ_REG32(&core_if->dev_if-> ++ out_ep_regs[ep->num]->doeptsiz); + offset = + ep->data_per_frame + + (0x4 & (0x4 - (ep->data_per_frame & 0x3))); +@@ -2344,8 +2562,8 @@ + for (j = 0; j < dwc_ep->pkt_per_frm; ++j) { + data_per_desc = + ((j + 1) * dwc_ep->maxpacket > +- dwc_ep->data_per_frame) ? dwc_ep-> +- data_per_frame - ++ dwc_ep-> ++ data_per_frame) ? dwc_ep->data_per_frame - + j * dwc_ep->maxpacket : dwc_ep->maxpacket; + data_per_desc += + (data_per_desc % 4) ? (4 - +@@ -2371,8 +2589,7 @@ + iso_packet->length = + data_per_desc - + sts.b_iso_out.rxbytes + (4 - +- dwc_ep-> +- data_per_frame ++ dwc_ep->data_per_frame + % 4); + } + +@@ -2526,8 +2743,8 @@ + for (j = 0; j < dwc_ep->pkt_per_frm; ++j) { + data_per_desc = + ((j + 1) * dwc_ep->maxpacket > +- dwc_ep->data_per_frame) ? dwc_ep-> +- data_per_frame - ++ dwc_ep-> ++ data_per_frame) ? dwc_ep->data_per_frame - + j * dwc_ep->maxpacket : dwc_ep->maxpacket; + data_per_desc += + (data_per_desc % 4) ? (4 - +@@ -2628,8 +2845,8 @@ + int i; + + deptsiz.d32 = +- dwc_read_reg32(&core_if->dev_if->out_ep_regs[dwc_ep->num]-> +- doeptsiz); ++ DWC_READ_REG32(&core_if->dev_if-> ++ out_ep_regs[dwc_ep->num]->doeptsiz); + + drp_pkt = dwc_ep->pkt_cnt - deptsiz.b.pktcnt; + drp_pkt_cnt = dwc_ep->pkt_per_frm - (drp_pkt % dwc_ep->pkt_per_frm); +@@ -2650,7 +2867,7 @@ + deptsiz.b.pktcnt = 0; + } + +- dwc_write_reg32(&core_if->dev_if->out_ep_regs[dwc_ep->num]->doeptsiz, ++ DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[dwc_ep->num]->doeptsiz, + deptsiz.d32); + + if (deptsiz.b.pktcnt > 0) { +@@ -2664,16 +2881,17 @@ + deptsiz.b.xfersize;; + } + +- dwc_write_reg32(&core_if->dev_if->out_ep_regs[dwc_ep->num]-> +- doepdma, dma_addr); ++ DWC_WRITE_REG32(&core_if->dev_if-> ++ out_ep_regs[dwc_ep->num]->doepdma, dma_addr); + + /** Re-enable endpoint, clear nak */ + depctl.d32 = 0; + depctl.b.epena = 1; + depctl.b.cnak = 1; + +- dwc_modify_reg32(&core_if->dev_if->out_ep_regs[dwc_ep->num]-> +- doepctl, depctl.d32, depctl.d32); ++ DWC_MODIFY_REG32(&core_if->dev_if-> ++ out_ep_regs[dwc_ep->num]->doepctl, depctl.d32, ++ depctl.d32); + return 0; + } else { + return 1; +@@ -2706,12 +2924,12 @@ + + if (ep->is_in) { + deptsiz.d32 = +- dwc_read_reg32(&core_if->dev_if->in_ep_regs[ep->num]-> +- dieptsiz); ++ DWC_READ_REG32(&core_if->dev_if-> ++ in_ep_regs[ep->num]->dieptsiz); + } else { + deptsiz.d32 = +- dwc_read_reg32(&core_if->dev_if->out_ep_regs[ep->num]-> +- doeptsiz); ++ DWC_READ_REG32(&core_if->dev_if-> ++ out_ep_regs[ep->num]->doeptsiz); + } + + if (!deptsiz.b.xfersize) { +@@ -2720,8 +2938,8 @@ + frame_data = ep->data_per_frame; + for (j = 0; j < ep->pkt_per_frm; ++j) { + +- /* Packet status - is not set as initially +- * it is set to 0 and if packet was sent ++ /* Packet status - is not set as initially ++ * it is set to 0 and if packet was sent + successfully, status field will remain 0*/ + + /* Bytes has been transfered */ +@@ -2739,11 +2957,11 @@ + } + return 1; + } else { +- /* This is a workaround for in case of Transfer Complete with +- * PktDrpSts interrupts merging - in this case Transfer complete +- * interrupt for Isoc Out Endpoint is asserted without PktDrpSts ++ /* This is a workaround for in case of Transfer Complete with ++ * PktDrpSts interrupts merging - in this case Transfer complete ++ * interrupt for Isoc Out Endpoint is asserted without PktDrpSts + * set and with DOEPTSIZ register non zero. Investigations showed, +- * that this happens when Out packet is dropped, but because of ++ * that this happens when Out packet is dropped, but because of + * interrupts merging during first interrupt handling PktDrpSts + * bit is cleared and for next merged interrupts it is not reset. + * In this case SW hadles the interrupt as if PktDrpSts bit is set. +@@ -2769,7 +2987,7 @@ + dwc_ep_t *dwc_ep = &ep->dwc_ep; + uint8_t is_last = 0; + +- if(ep->dwc_ep.next_frame == 0xffffffff) { ++ if (ep->dwc_ep.next_frame == 0xffffffff) { + DWC_WARN("Next frame is not set!\n"); + return; + } +@@ -2832,7 +3050,58 @@ + if (is_last) + dwc_otg_iso_buffer_done(pcd, ep, ep->iso_req_handle); + } +-#endif /* DWC_EN_ISOC */ ++#endif /* DWC_EN_ISOC */ ++ ++/** ++ * This function handle BNA interrupt for Non Isochronous EPs ++ * ++ */ ++static void dwc_otg_pcd_handle_noniso_bna(dwc_otg_pcd_ep_t * ep) ++{ ++ dwc_ep_t *dwc_ep = &ep->dwc_ep; ++ volatile uint32_t *addr; ++ depctl_data_t depctl = {.d32 = 0 }; ++ dwc_otg_pcd_t *pcd = ep->pcd; ++ dwc_otg_dev_dma_desc_t *dma_desc; ++ dev_dma_desc_sts_t sts = {.d32 = 0 }; ++ dwc_otg_core_if_t *core_if = ep->pcd->core_if; ++ int i, start; ++ ++ if (!dwc_ep->desc_cnt) ++ DWC_WARN("Descriptor count = %d\n", dwc_ep->desc_cnt); ++ ++ if (core_if->core_params->cont_on_bna && !dwc_ep->is_in ++ && dwc_ep->type != DWC_OTG_EP_TYPE_CONTROL) { ++ uint32_t doepdma; ++ dwc_otg_dev_out_ep_regs_t *out_regs = ++ core_if->dev_if->out_ep_regs[dwc_ep->num]; ++ doepdma = DWC_READ_REG32(&(out_regs->doepdma)); ++ start = (doepdma - dwc_ep->dma_desc_addr)/sizeof(dwc_otg_dev_dma_desc_t); ++ dma_desc = &(dwc_ep->desc_addr[start]); ++ } else { ++ start = 0; ++ dma_desc = dwc_ep->desc_addr; ++ } ++ ++ ++ for (i = start; i < dwc_ep->desc_cnt; ++i, ++dma_desc) { ++ sts.d32 = dma_desc->status.d32; ++ sts.b.bs = BS_HOST_READY; ++ dma_desc->status.d32 = sts.d32; ++ } ++ ++ if (dwc_ep->is_in == 0) { ++ addr = ++ &GET_CORE_IF(pcd)->dev_if->out_ep_regs[dwc_ep-> ++ num]->doepctl; ++ } else { ++ addr = ++ &GET_CORE_IF(pcd)->dev_if->in_ep_regs[dwc_ep->num]->diepctl; ++ } ++ depctl.b.epena = 1; ++ depctl.b.cnak = 1; ++ DWC_MODIFY_REG32(addr, 0, depctl.d32); ++} + + /** + * This function handles EP0 Control transfers. +@@ -2882,8 +3151,9 @@ + */ + if (core_if->dma_desc_enable == 0) { + deptsiz.d32 = +- dwc_read_reg32(&core_if->dev_if-> +- in_ep_regs[0]->dieptsiz); ++ DWC_READ_REG32(&core_if-> ++ dev_if->in_ep_regs[0]-> ++ dieptsiz); + byte_count = + ep0->dwc_ep.xfer_len - deptsiz.b.xfersize; + } else { +@@ -2919,8 +3189,9 @@ + if (core_if->dma_enable != 0) { + if (core_if->dma_desc_enable == 0) { + deptsiz.d32 = +- dwc_read_reg32(&core_if->dev_if-> +- out_ep_regs[0]->doeptsiz); ++ DWC_READ_REG32(&core_if-> ++ dev_if->out_ep_regs[0]-> ++ doeptsiz); + byte_count = + ep0->dwc_ep.maxpacket - deptsiz.b.xfersize; + } else { +@@ -2987,12 +3258,12 @@ + if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) { + return; + } +-#endif /* DWC_EN_ISOC */ ++#endif /* DWC_EN_ISOC */ + + core_if = GET_CORE_IF(pcd); + dev_if = core_if->dev_if; + +- dieptsiz.d32 = dwc_read_reg32(&dev_if->in_ep_regs[epnum]->dieptsiz); ++ dieptsiz.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->dieptsiz); + + DWC_DEBUGPL(DBG_PCD, "xfer_buff=%p xfer_count=%0x xfer_len=%0x" + " stopped=%d\n", ep->dwc_ep.xfer_buff, +@@ -3026,6 +3297,173 @@ + } + } + ++/* ++ * This function create new nextep sequnce based on Learn Queue. ++ * ++ * @param core_if Programming view of DWC_otg controller ++ */ ++void predict_nextep_seq( dwc_otg_core_if_t * core_if) ++{ ++ dwc_otg_device_global_regs_t *dev_global_regs = ++ core_if->dev_if->dev_global_regs; ++ const uint32_t TOKEN_Q_DEPTH = core_if->hwcfg2.b.dev_token_q_depth; ++ /* Number of Token Queue Registers */ ++ const int DTKNQ_REG_CNT = (TOKEN_Q_DEPTH + 7) / 8; ++ dtknq1_data_t dtknqr1; ++ uint32_t in_tkn_epnums[4]; ++ uint8_t seqnum[MAX_EPS_CHANNELS]; ++ uint8_t intkn_seq[TOKEN_Q_DEPTH]; ++ grstctl_t resetctl = {.d32 = 0 }; ++ uint8_t temp; ++ int ndx = 0; ++ int start = 0; ++ int end = 0; ++ int sort_done = 0; ++ int i = 0; ++ volatile uint32_t *addr = &dev_global_regs->dtknqr1; ++ ++ ++ DWC_DEBUGPL(DBG_PCD,"dev_token_q_depth=%d\n",TOKEN_Q_DEPTH); ++ ++ /* Read the DTKNQ Registers */ ++ for (i = 0; i < DTKNQ_REG_CNT; i++) { ++ in_tkn_epnums[i] = DWC_READ_REG32(addr); ++ DWC_DEBUGPL(DBG_PCDV, "DTKNQR%d=0x%08x\n", i + 1, ++ in_tkn_epnums[i]); ++ if (addr == &dev_global_regs->dvbusdis) { ++ addr = &dev_global_regs->dtknqr3_dthrctl; ++ } else { ++ ++addr; ++ } ++ ++ } ++ ++ /* Copy the DTKNQR1 data to the bit field. */ ++ dtknqr1.d32 = in_tkn_epnums[0]; ++ if (dtknqr1.b.wrap_bit) { ++ ndx = dtknqr1.b.intknwptr; ++ end = ndx -1; ++ if (end < 0) ++ end = TOKEN_Q_DEPTH -1; ++ } else { ++ ndx = 0; ++ end = dtknqr1.b.intknwptr -1; ++ if (end < 0) ++ end = 0; ++ } ++ start = ndx; ++ ++ /* Fill seqnum[] by initial values: EP number + 31 */ ++ for (i=0; i <= core_if->dev_if->num_in_eps; i++) { ++ seqnum[i] = i +31; ++ } ++ ++ /* Fill intkn_seq[] from in_tkn_epnums[0] */ ++ for (i=0; i < 6; i++) ++ intkn_seq[i] = (in_tkn_epnums[0] >> ((7-i) * 4)) & 0xf; ++ ++ if (TOKEN_Q_DEPTH > 6) { ++ /* Fill intkn_seq[] from in_tkn_epnums[1] */ ++ for (i=6; i < 14; i++) ++ intkn_seq[i] = (in_tkn_epnums[1] >> ((7-(i-6)) * 4)) & 0xf; ++ } ++ ++ if (TOKEN_Q_DEPTH > 14) { ++ /* Fill intkn_seq[] from in_tkn_epnums[1] */ ++ for (i=14; i < 22; i++) ++ intkn_seq[i] = (in_tkn_epnums[2] >> ((7-(i-14)) * 4)) & 0xf; ++ } ++ ++ if (TOKEN_Q_DEPTH > 22) { ++ /* Fill intkn_seq[] from in_tkn_epnums[1] */ ++ for (i=22; i < 30; i++) ++ intkn_seq[i] = (in_tkn_epnums[3] >> ((7-(i-22)) * 4)) & 0xf; ++ } ++ ++ DWC_DEBUGPL(DBG_PCDV,"%s start=%d end=%d intkn_seq[]:\n", __func__, start, end); ++ for (i=0; idev_if->num_in_eps; i++) { ++ if (core_if->nextep_seq[i] == 0xff ) ++ seqnum[i] = 0xff; ++ } ++ ++ /* Sort seqnum[] */ ++ sort_done = 0; ++ while (!sort_done) { ++ sort_done = 1; ++ for (i=0; idev_if->num_in_eps; i++) { ++ if (seqnum[i] > seqnum[i+1]) { ++ temp = seqnum[i]; ++ seqnum[i] = seqnum[i+1]; ++ seqnum[i+1] = temp; ++ sort_done = 0; ++ } ++ } ++ } ++ ++ ndx = start + seqnum[0]; ++ if (ndx >= TOKEN_Q_DEPTH) ++ ndx = ndx % TOKEN_Q_DEPTH; ++ core_if->first_in_nextep_seq = intkn_seq[ndx]; ++ ++ /* Update seqnum[] by EP numbers */ ++ for (i=0; i<=core_if->dev_if->num_in_eps; i++) { ++ ndx = start + i; ++ if (seqnum[i] < 31) { ++ ndx = start + seqnum[i]; ++ if (ndx >= TOKEN_Q_DEPTH) ++ ndx = ndx % TOKEN_Q_DEPTH; ++ seqnum[i] = intkn_seq[ndx]; ++ } else { ++ if (seqnum[i] < 0xff) { ++ seqnum[i] = seqnum[i] - 31; ++ } else { ++ break; ++ } ++ } ++ } ++ ++ /* Update nextep_seq[] based on seqnum[] */ ++ for (i=0; idev_if->num_in_eps; i++) { ++ if (seqnum[i] != 0xff) { ++ if (seqnum[i+1] != 0xff) { ++ core_if->nextep_seq[seqnum[i]] = seqnum[i+1]; ++ } else { ++ core_if->nextep_seq[seqnum[i]] = core_if->first_in_nextep_seq; ++ break; ++ } ++ } else { ++ break; ++ } ++ } ++ ++ DWC_DEBUGPL(DBG_PCDV, "%s first_in_nextep_seq= %2d; nextep_seq[]:\n", ++ __func__, core_if->first_in_nextep_seq); ++ for (i=0; i <= core_if->dev_if->num_in_eps; i++) { ++ DWC_DEBUGPL(DBG_PCDV,"%2d\n", core_if->nextep_seq[i]); ++ } ++ ++ /* Flush the Learning Queue */ ++ resetctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->grstctl); ++ resetctl.b.intknqflsh = 1; ++ DWC_WRITE_REG32(&core_if->core_global_regs->grstctl, resetctl.d32); ++ ++ ++} ++ + /** + * handle the IN EP disable interrupt. + */ +@@ -3038,40 +3476,135 @@ + dctl_data_t dctl = {.d32 = 0 }; + dwc_otg_pcd_ep_t *ep; + dwc_ep_t *dwc_ep; +- ++ gintmsk_data_t gintmsk_data; ++ depctl_data_t depctl; ++ uint32_t diepdma; ++ uint32_t remain_to_transfer = 0; ++ uint8_t i; ++ uint32_t xfer_size; ++ + ep = get_in_ep(pcd, epnum); + dwc_ep = &ep->dwc_ep; + + if (dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) { + dwc_otg_flush_tx_fifo(core_if, dwc_ep->tx_fifo_num); ++ complete_ep(ep); + return; + } + + DWC_DEBUGPL(DBG_PCD, "diepctl%d=%0x\n", epnum, +- dwc_read_reg32(&dev_if->in_ep_regs[epnum]->diepctl)); +- dieptsiz.d32 = dwc_read_reg32(&dev_if->in_ep_regs[epnum]->dieptsiz); ++ DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->diepctl)); ++ dieptsiz.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->dieptsiz); ++ depctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->diepctl); + + DWC_DEBUGPL(DBG_ANY, "pktcnt=%d size=%d\n", + dieptsiz.b.pktcnt, dieptsiz.b.xfersize); ++ ++ if ((core_if->start_predict == 0) || (depctl.b.eptype & 1)) { ++ if (ep->stopped) { ++ if (core_if->en_multiple_tx_fifo) ++ /* Flush the Tx FIFO */ ++ dwc_otg_flush_tx_fifo(core_if, dwc_ep->tx_fifo_num); ++ /* Clear the Global IN NP NAK */ ++ dctl.d32 = 0; ++ dctl.b.cgnpinnak = 1; ++ DWC_MODIFY_REG32(&dev_if->dev_global_regs->dctl, dctl.d32, dctl.d32); ++ /* Restart the transaction */ ++ if (dieptsiz.b.pktcnt != 0 || dieptsiz.b.xfersize != 0) { ++ restart_transfer(pcd, epnum); ++ } ++ } else { ++ /* Restart the transaction */ ++ if (dieptsiz.b.pktcnt != 0 || dieptsiz.b.xfersize != 0) { ++ restart_transfer(pcd, epnum); ++ } ++ DWC_DEBUGPL(DBG_ANY, "STOPPED!!!\n"); ++ } ++ return; ++ } + +- if (ep->stopped) { +- /* Flush the Tx FIFO */ +- dwc_otg_flush_tx_fifo(core_if, dwc_ep->tx_fifo_num); +- /* Clear the Global IN NP NAK */ ++ if (core_if->start_predict > 2) { // NP IN EP ++ core_if->start_predict--; ++ return; ++ } ++ ++ core_if->start_predict--; ++ ++ if (core_if->start_predict == 1) { // All NP IN Ep's disabled now ++ ++ predict_nextep_seq(core_if); ++ ++ /* Update all active IN EP's NextEP field based of nextep_seq[] */ ++ for ( i = 0; i <= core_if->dev_if->num_in_eps; i++) { ++ depctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl); ++ if (core_if->nextep_seq[i] != 0xff) { // Active NP IN EP ++ depctl.b.nextep = core_if->nextep_seq[i]; ++ DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->diepctl, depctl.d32); ++ } ++ } ++ /* Flush Shared NP TxFIFO */ ++ dwc_otg_flush_tx_fifo(core_if, 0); ++ /* Rewind buffers */ ++ if (!core_if->dma_desc_enable) { ++ i = core_if->first_in_nextep_seq; ++ do { ++ ep = get_in_ep(pcd, i); ++ dieptsiz.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[i]->dieptsiz); ++ xfer_size = ep->dwc_ep.total_len - ep->dwc_ep.xfer_count; ++ if (xfer_size > ep->dwc_ep.maxxfer) ++ xfer_size = ep->dwc_ep.maxxfer; ++ depctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl); ++ if (dieptsiz.b.pktcnt != 0) { ++ if (xfer_size == 0) { ++ remain_to_transfer = 0; ++ } else { ++ if ((xfer_size % ep->dwc_ep.maxpacket) == 0) { ++ remain_to_transfer = ++ dieptsiz.b.pktcnt * ep->dwc_ep.maxpacket; ++ } else { ++ remain_to_transfer = ((dieptsiz.b.pktcnt -1) * ep->dwc_ep.maxpacket) ++ + (xfer_size % ep->dwc_ep.maxpacket); ++ } ++ } ++ diepdma = DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepdma); ++ dieptsiz.b.xfersize = remain_to_transfer; ++ DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->dieptsiz, dieptsiz.d32); ++ diepdma = ep->dwc_ep.dma_addr + (xfer_size - remain_to_transfer); ++ DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->diepdma, diepdma); ++ } ++ i = core_if->nextep_seq[i]; ++ } while (i != core_if->first_in_nextep_seq); ++ } else { // dma_desc_enable ++ DWC_PRINTF("%s Learning Queue not supported in DDMA\n", __func__); ++ } ++ ++ /* Restart transfers in predicted sequences */ ++ i = core_if->first_in_nextep_seq; ++ do { ++ dieptsiz.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[i]->dieptsiz); ++ depctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl); ++ if (dieptsiz.b.pktcnt != 0) { ++ depctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl); ++ depctl.b.epena = 1; ++ depctl.b.cnak = 1; ++ DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->diepctl, depctl.d32); ++ } ++ i = core_if->nextep_seq[i]; ++ } while (i != core_if->first_in_nextep_seq); ++ ++ /* Clear the global non-periodic IN NAK handshake */ + dctl.d32 = 0; + dctl.b.cgnpinnak = 1; +- dwc_modify_reg32(&dev_if->dev_global_regs->dctl, dctl.d32, 0); +- /* Restart the transaction */ +- if (dieptsiz.b.pktcnt != 0 || dieptsiz.b.xfersize != 0) { +- restart_transfer(pcd, epnum); +- } +- } else { +- /* Restart the transaction */ +- if (dieptsiz.b.pktcnt != 0 || dieptsiz.b.xfersize != 0) { +- restart_transfer(pcd, epnum); +- } +- DWC_DEBUGPL(DBG_ANY, "STOPPED!!!\n"); +- } ++ DWC_MODIFY_REG32(&dev_if->dev_global_regs->dctl, dctl.d32, dctl.d32); ++ ++ /* Unmask EP Mismatch interrupt */ ++ gintmsk_data.d32 = 0; ++ gintmsk_data.b.epmismatch = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, 0, gintmsk_data.d32); ++ ++ core_if->start_predict = 0; ++ ++ } + } + + /** +@@ -3097,7 +3630,7 @@ + /* Disable the NP Tx Fifo Empty Interrrupt */ + if (!core_if->dma_enable) { + intr_mask.b.nptxfempty = 1; +- dwc_modify_reg32(&core_if->core_global_regs->gintmsk, ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, + intr_mask.d32, 0); + } + /** @todo NGS Check EP type. +@@ -3107,16 +3640,16 @@ + */ + /* Enable the Global IN NAK Effective Interrupt */ + intr_mask.b.ginnakeff = 1; +- dwc_modify_reg32(&core_if->core_global_regs->gintmsk, 0, intr_mask.d32); ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, 0, intr_mask.d32); + + /* Set Global IN NAK */ + dctl.b.sgnpinnak = 1; +- dwc_modify_reg32(&dev_if->dev_global_regs->dctl, dctl.d32, dctl.d32); ++ DWC_MODIFY_REG32(&dev_if->dev_global_regs->dctl, dctl.d32, dctl.d32); + + ep->stopped = 1; + + #ifdef DEBUG +- dieptsiz.d32 = dwc_read_reg32(&dev_if->in_ep_regs[num]->dieptsiz); ++ dieptsiz.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[num]->dieptsiz); + DWC_DEBUGPL(DBG_ANY, "pktcnt=%d size=%d\n", + dieptsiz.b.pktcnt, dieptsiz.b.xfersize); + #endif +@@ -3128,7 +3661,7 @@ + */ + diepctl.d32 = 0; + diepctl.b.snak = 1; +- dwc_modify_reg32(&dev_if->in_ep_regs[num]->diepctl, diepctl.d32, ++ DWC_MODIFY_REG32(&dev_if->in_ep_regs[num]->diepctl, diepctl.d32, + diepctl.d32); + ep->disabling = 1; + ep->stopped = 1; +@@ -3136,7 +3669,7 @@ + } + + /** +- * Handler for the IN EP NAK interrupt. ++ * Handler for the IN EP NAK interrupt. + */ + static inline int32_t handle_in_ep_nak_intr(dwc_otg_pcd_t * pcd, + const uint32_t epnum) +@@ -3150,10 +3683,10 @@ + intr_mask.b.nak = 1; + + if (core_if->multiproc_int_enable) { +- dwc_modify_reg32(&core_if->dev_if->dev_global_regs-> ++ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs-> + diepeachintmsk[epnum], intr_mask.d32, 0); + } else { +- dwc_modify_reg32(&core_if->dev_if->dev_global_regs->diepmsk, ++ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->diepmsk, + intr_mask.d32, 0); + } + +@@ -3161,7 +3694,7 @@ + } + + /** +- * Handler for the OUT EP Babble interrupt. ++ * Handler for the OUT EP Babble interrupt. + */ + static inline int32_t handle_out_ep_babble_intr(dwc_otg_pcd_t * pcd, + const uint32_t epnum) +@@ -3176,10 +3709,10 @@ + intr_mask.b.babble = 1; + + if (core_if->multiproc_int_enable) { +- dwc_modify_reg32(&core_if->dev_if->dev_global_regs-> ++ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs-> + doepeachintmsk[epnum], intr_mask.d32, 0); + } else { +- dwc_modify_reg32(&core_if->dev_if->dev_global_regs->doepmsk, ++ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->doepmsk, + intr_mask.d32, 0); + } + +@@ -3187,7 +3720,7 @@ + } + + /** +- * Handler for the OUT EP NAK interrupt. ++ * Handler for the OUT EP NAK interrupt. + */ + static inline int32_t handle_out_ep_nak_intr(dwc_otg_pcd_t * pcd, + const uint32_t epnum) +@@ -3201,10 +3734,10 @@ + intr_mask.b.nak = 1; + + if (core_if->multiproc_int_enable) { +- dwc_modify_reg32(&core_if->dev_if->dev_global_regs-> ++ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs-> + doepeachintmsk[epnum], intr_mask.d32, 0); + } else { +- dwc_modify_reg32(&core_if->dev_if->dev_global_regs->doepmsk, ++ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->doepmsk, + intr_mask.d32, 0); + } + +@@ -3212,7 +3745,7 @@ + } + + /** +- * Handler for the OUT EP NYET interrupt. ++ * Handler for the OUT EP NYET interrupt. + */ + static inline int32_t handle_out_ep_nyet_intr(dwc_otg_pcd_t * pcd, + const uint32_t epnum) +@@ -3226,10 +3759,10 @@ + intr_mask.b.nyet = 1; + + if (core_if->multiproc_int_enable) { +- dwc_modify_reg32(&core_if->dev_if->dev_global_regs-> ++ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs-> + doepeachintmsk[epnum], intr_mask.d32, 0); + } else { +- dwc_modify_reg32(&core_if->dev_if->dev_global_regs->doepmsk, ++ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->doepmsk, + intr_mask.d32, 0); + } + +@@ -3258,14 +3791,13 @@ + do { \ + diepint_data_t diepint = {.d32=0}; \ + diepint.b.__intr = 1; \ +- dwc_write_reg32(&__core_if->dev_if->in_ep_regs[__epnum]->diepint, \ ++ DWC_WRITE_REG32(&__core_if->dev_if->in_ep_regs[__epnum]->diepint, \ + diepint.d32); \ + } while (0) + + dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); + dwc_otg_dev_if_t *dev_if = core_if->dev_if; + diepint_data_t diepint = {.d32 = 0 }; +- dctl_data_t dctl = {.d32 = 0 }; + depctl_data_t depctl = {.d32 = 0 }; + uint32_t ep_intr; + uint32_t epnum = 0; +@@ -3287,10 +3819,10 @@ + dwc_ep = &ep->dwc_ep; + + depctl.d32 = +- dwc_read_reg32(&dev_if->in_ep_regs[epnum]->diepctl); ++ DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->diepctl); + empty_msk = +- dwc_read_reg32(&dev_if->dev_global_regs-> +- dtknqr4_fifoemptymsk); ++ DWC_READ_REG32(&dev_if-> ++ dev_global_regs->dtknqr4_fifoemptymsk); + + DWC_DEBUGPL(DBG_PCDV, + "IN EP INTERRUPT - %d\nepmty_msk - %8x diepctl - %8x\n", +@@ -3313,17 +3845,15 @@ + * Interrrupt */ + if (core_if->en_multiple_tx_fifo == 0) { + intr_mask.b.nptxfempty = 1; +- dwc_modify_reg32(&core_if-> +- core_global_regs-> +- gintmsk, intr_mask.d32, +- 0); ++ DWC_MODIFY_REG32 ++ (&core_if->core_global_regs->gintmsk, ++ intr_mask.d32, 0); + } else { + /* Disable the Tx FIFO Empty Interrupt for this EP */ + uint32_t fifoemptymsk = + 0x1 << dwc_ep->num; +- dwc_modify_reg32(&core_if->dev_if-> +- dev_global_regs-> +- dtknqr4_fifoemptymsk, ++ DWC_MODIFY_REG32(&core_if-> ++ dev_if->dev_global_regs->dtknqr4_fifoemptymsk, + fifoemptymsk, 0); + } + /* Clear the bit in DIEPINTn for this interrupt */ +@@ -3338,10 +3868,27 @@ + if (!ep->stopped) + complete_iso_ep(pcd, ep); + } +-#endif /* DWC_EN_ISOC */ ++#endif /* DWC_EN_ISOC */ ++#ifdef DWC_UTE_PER_IO ++ else if (dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) { ++ if (!ep->stopped) ++ complete_xiso_ep(ep); ++ } ++#endif /* DWC_UTE_PER_IO */ + else { +- ++ if (dwc_ep->type == DWC_OTG_EP_TYPE_ISOC && ++ dwc_ep->bInterval > 1) { ++ dwc_ep->frame_num += dwc_ep->bInterval; ++ if (dwc_ep->frame_num > 0x3FFF) ++ { ++ dwc_ep->frm_overrun = 1; ++ dwc_ep->frame_num &= 0x3FFF; ++ } else ++ dwc_ep->frm_overrun = 0; ++ } + complete_ep(ep); ++ if(diepint.b.nak) ++ CLEAR_IN_EP_INTR(core_if, epnum, nak); + } + } + /* Endpoint disable */ +@@ -3355,15 +3902,13 @@ + } + /* AHB Error */ + if (diepint.b.ahberr) { +- DWC_DEBUGPL(DBG_ANY, "EP%d IN AHB Error\n", +- epnum); ++ DWC_ERROR("EP%d IN AHB Error\n", epnum); + /* Clear the bit in DIEPINTn for this interrupt */ + CLEAR_IN_EP_INTR(core_if, epnum, ahberr); + } + /* TimeOUT Handshake (non-ISOC IN EPs) */ + if (diepint.b.timeout) { +- DWC_DEBUGPL(DBG_ANY, "EP%d IN Time-out\n", +- epnum); ++ DWC_ERROR("EP%d IN Time-out\n", epnum); + handle_in_ep_timeout_intr(pcd, epnum); + + CLEAR_IN_EP_INTR(core_if, epnum, timeout); +@@ -3379,18 +3924,13 @@ + diepmsk.b.intktxfemp = 1; + + if (core_if->multiproc_int_enable) { +- dwc_modify_reg32(&dev_if-> +- dev_global_regs-> +- diepeachintmsk +- [epnum], +- diepmsk.d32, +- 0); ++ DWC_MODIFY_REG32 ++ (&dev_if->dev_global_regs->diepeachintmsk ++ [epnum], diepmsk.d32, 0); + } else { +- dwc_modify_reg32(&dev_if-> +- dev_global_regs-> +- diepmsk, +- diepmsk.d32, +- 0); ++ DWC_MODIFY_REG32 ++ (&dev_if->dev_global_regs->diepmsk, ++ diepmsk.d32, 0); + } + } else if (core_if->dma_desc_enable + && epnum == 0 +@@ -3398,18 +3938,17 @@ + EP0_OUT_STATUS_PHASE) { + // EP0 IN set STALL + depctl.d32 = +- dwc_read_reg32(&dev_if-> +- in_ep_regs[epnum]-> +- diepctl); ++ DWC_READ_REG32(&dev_if->in_ep_regs ++ [epnum]->diepctl); + + /* set the disable and stall bits */ + if (depctl.b.epena) { + depctl.b.epdis = 1; + } + depctl.b.stall = 1; +- dwc_write_reg32(&dev_if-> +- in_ep_regs[epnum]-> +- diepctl, depctl.d32); ++ DWC_WRITE_REG32(&dev_if->in_ep_regs ++ [epnum]->diepctl, ++ depctl.d32); + } + CLEAR_IN_EP_INTR(core_if, epnum, intktxfemp); + } +@@ -3417,7 +3956,7 @@ + if (diepint.b.intknepmis) { + DWC_DEBUGPL(DBG_ANY, + "EP%d IN TKN EP Mismatch\n", epnum); +- CLEAR_IN_EP_INTR(core_if, epnum, intknepmis); ++ CLEAR_IN_EP_INTR(core_if, epnum, intknepmis); + } + /** IN Endpoint NAK Effective */ + if (diepint.b.inepnakeff) { +@@ -3429,9 +3968,9 @@ + depctl.d32 = 0; + depctl.b.snak = 1; + depctl.b.epdis = 1; +- dwc_modify_reg32(&dev_if-> +- in_ep_regs[epnum]-> +- diepctl, depctl.d32, ++ DWC_MODIFY_REG32(&dev_if->in_ep_regs ++ [epnum]->diepctl, ++ depctl.d32, + depctl.d32); + } + CLEAR_IN_EP_INTR(core_if, epnum, inepnakeff); +@@ -3457,35 +3996,16 @@ + if (dwc_ep->type == + DWC_OTG_EP_TYPE_ISOC) { + /* +- * This checking is performed to prevent first "false" BNA +- * handling occuring right after reconnect ++ * This checking is performed to prevent first "false" BNA ++ * handling occuring right after reconnect + */ + if (dwc_ep->next_frame != + 0xffffffff) +- dwc_otg_pcd_handle_iso_bna +- (ep); ++ dwc_otg_pcd_handle_iso_bna(ep); + } else + #endif /* DWC_EN_ISOC */ + { +- dctl.d32 = +- dwc_read_reg32(&dev_if-> +- dev_global_regs-> +- dctl); +- +- /* If Global Continue on BNA is disabled - disable EP */ +- if (!dctl.b.gcontbna) { +- depctl.d32 = 0; +- depctl.b.snak = 1; +- depctl.b.epdis = 1; +- dwc_modify_reg32 +- (&dev_if-> +- in_ep_regs[epnum]-> +- diepctl, +- depctl.d32, +- depctl.d32); +- } else { +- start_next_request(ep); +- } ++ dwc_otg_pcd_handle_noniso_bna(ep); + } + } + } +@@ -3493,7 +4013,35 @@ + if (diepint.b.nak) { + DWC_DEBUGPL(DBG_ANY, "EP%d IN NAK Interrupt\n", + epnum); +- handle_in_ep_nak_intr(pcd, epnum); ++ if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) ++ { ++ depctl_data_t depctl; ++ if (ep->dwc_ep.frame_num == 0xFFFFFFFF) ++ { ++ ep->dwc_ep.frame_num = core_if->frame_num; ++ if (ep->dwc_ep.bInterval > 1) ++ { ++ depctl.d32 = 0; ++ depctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->diepctl); ++ if (ep->dwc_ep.frame_num & 0x1) { ++ depctl.b.setd1pid = 1; ++ depctl.b.setd0pid = 0; ++ } else { ++ depctl.b.setd0pid = 1; ++ depctl.b.setd1pid = 0; ++ } ++ DWC_WRITE_REG32(&dev_if->in_ep_regs[epnum]->diepctl, depctl.d32); ++ } ++ start_next_request(ep); ++ } ++ ep->dwc_ep.frame_num += ep->dwc_ep.bInterval; ++ if (dwc_ep->frame_num > 0x3FFF) ++ { ++ dwc_ep->frm_overrun = 1; ++ dwc_ep->frame_num &= 0x3FFF; ++ } else ++ dwc_ep->frm_overrun = 0; ++ } + + CLEAR_IN_EP_INTR(core_if, epnum, nak); + } +@@ -3525,19 +4073,19 @@ + do { \ + doepint_data_t doepint = {.d32=0}; \ + doepint.b.__intr = 1; \ +- dwc_write_reg32(&__core_if->dev_if->out_ep_regs[__epnum]->doepint, \ ++ DWC_WRITE_REG32(&__core_if->dev_if->out_ep_regs[__epnum]->doepint, \ + doepint.d32); \ + } while (0) + + dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); +- dwc_otg_dev_if_t *dev_if = core_if->dev_if; + uint32_t ep_intr; + doepint_data_t doepint = {.d32 = 0 }; +- dctl_data_t dctl = {.d32 = 0 }; +- depctl_data_t doepctl = {.d32 = 0 }; + uint32_t epnum = 0; + dwc_otg_pcd_ep_t *ep; + dwc_ep_t *dwc_ep; ++ dctl_data_t dctl = {.d32 = 0 }; ++ gintmsk_data_t gintmsk = {.d32 = 0 }; ++ + + DWC_DEBUGPL(DBG_PCDV, "%s()\n", __func__); + +@@ -3579,28 +4127,39 @@ + complete_iso_ep(pcd, ep); + } else { + +- doepint_data_t doepint = {.d32 = +- 0 }; ++ doepint_data_t doepint = {.d32 = 0 }; + doepint.b.xfercompl = 1; + doepint.b.pktdrpsts = 1; +- dwc_write_reg32(&core_if-> +- dev_if-> +- out_ep_regs +- [epnum]-> +- doepint, +- doepint.d32); ++ DWC_WRITE_REG32 ++ (&core_if->dev_if->out_ep_regs ++ [epnum]->doepint, ++ doepint.d32); + if (handle_iso_out_pkt_dropped + (core_if, dwc_ep)) { + complete_iso_ep(pcd, + ep); + } + } +-#endif /* DWC_EN_ISOC */ ++#endif /* DWC_EN_ISOC */ ++#ifdef DWC_UTE_PER_IO ++ } else if (dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) { ++ CLEAR_OUT_EP_INTR(core_if, epnum, xfercompl); ++ if (!ep->stopped) ++ complete_xiso_ep(ep); ++#endif /* DWC_UTE_PER_IO */ + } else { + /* Clear the bit in DOEPINTn for this interrupt */ + CLEAR_OUT_EP_INTR(core_if, epnum, + xfercompl); +- complete_ep(ep); ++ ++ if (core_if->core_params->dev_out_nak) { ++ DWC_TIMER_CANCEL(pcd->core_if->ep_xfer_timer[epnum]); ++ pcd->core_if->ep_xfer_info[epnum].state = 0; ++#ifdef DEBUG ++ print_memory_payload(pcd, dwc_ep); ++#endif ++ } ++ complete_ep(ep); + } + + } +@@ -3610,14 +4169,60 @@ + + /* Clear the bit in DOEPINTn for this interrupt */ + CLEAR_OUT_EP_INTR(core_if, epnum, epdisabled); ++ if (core_if->core_params->dev_out_nak) { ++#ifdef DEBUG ++ print_memory_payload(pcd, dwc_ep); ++#endif ++ /* In case of timeout condition */ ++ if (core_if->ep_xfer_info[epnum].state == 2) { ++ dctl.d32 = DWC_READ_REG32(&core_if->dev_if-> ++ dev_global_regs->dctl); ++ dctl.b.cgoutnak = 1; ++ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl, ++ dctl.d32); ++ /* Unmask goutnakeff interrupt which was masked ++ * during handle nak out interrupt */ ++ gintmsk.b.goutnakeff = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, ++ 0, gintmsk.d32); ++ ++ complete_ep(ep); ++ } ++ } ++ if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) ++ { ++ dctl_data_t dctl; ++ gintmsk_data_t intr_mask = {.d32 = 0}; ++ dwc_otg_pcd_request_t *req = 0; ++ ++ dctl.d32 = DWC_READ_REG32(&core_if->dev_if-> ++ dev_global_regs->dctl); ++ dctl.b.cgoutnak = 1; ++ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl, ++ dctl.d32); ++ ++ intr_mask.d32 = 0; ++ intr_mask.b.incomplisoout = 1; ++ ++ /* Get any pending requests */ ++ if (!DWC_CIRCLEQ_EMPTY(&ep->queue)) { ++ req = DWC_CIRCLEQ_FIRST(&ep->queue); ++ if (!req) { ++ DWC_PRINTF("complete_ep 0x%p, req = NULL!\n", ep); ++ } else { ++ dwc_otg_request_done(ep, req, 0); ++ start_next_request(ep); ++ } ++ } else { ++ DWC_PRINTF("complete_ep 0x%p, ep->queue empty!\n", ep); ++ } ++ } + } + /* AHB Error */ + if (doepint.b.ahberr) { +- DWC_DEBUGPL(DBG_PCD, "EP%d OUT AHB Error\n", +- epnum); +- DWC_DEBUGPL(DBG_PCD, "EP DMA REG %d \n", +- core_if->dev_if-> +- out_ep_regs[epnum]->doepdma); ++ DWC_ERROR("EP%d OUT AHB Error\n", epnum); ++ DWC_ERROR("EP%d DEPDMA=0x%08x \n", ++ epnum, core_if->dev_if->out_ep_regs[epnum]->doepdma); + CLEAR_OUT_EP_INTR(core_if, epnum, ahberr); + } + /* Setup Phase Done (contorl EPs) */ +@@ -3639,35 +4244,16 @@ + if (dwc_ep->type == + DWC_OTG_EP_TYPE_ISOC) { + /* +- * This checking is performed to prevent first "false" BNA +- * handling occuring right after reconnect ++ * This checking is performed to prevent first "false" BNA ++ * handling occuring right after reconnect + */ + if (dwc_ep->next_frame != + 0xffffffff) +- dwc_otg_pcd_handle_iso_bna +- (ep); ++ dwc_otg_pcd_handle_iso_bna(ep); + } else + #endif /* DWC_EN_ISOC */ + { +- dctl.d32 = +- dwc_read_reg32(&dev_if-> +- dev_global_regs-> +- dctl); +- +- /* If Global Continue on BNA is disabled - disable EP */ +- if (!dctl.b.gcontbna) { +- doepctl.d32 = 0; +- doepctl.b.snak = 1; +- doepctl.b.epdis = 1; +- dwc_modify_reg32 +- (&dev_if-> +- out_ep_regs +- [epnum]->doepctl, +- doepctl.d32, +- doepctl.d32); +- } else { +- start_next_request(ep); +- } ++ dwc_otg_pcd_handle_noniso_bna(ep); + } + } + } +@@ -3685,6 +4271,37 @@ + + CLEAR_OUT_EP_INTR(core_if, epnum, babble); + } ++ if (doepint.b.outtknepdis) ++ { ++ DWC_DEBUGPL(DBG_ANY, "EP%d OUT Token received when EP is \ ++ disabled\n",epnum); ++ if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) ++ { ++ doepmsk_data_t doepmsk = {.d32 = 0}; ++ ep->dwc_ep.frame_num = core_if->frame_num; ++ if (ep->dwc_ep.bInterval > 1) ++ { ++ depctl_data_t depctl; ++ depctl.d32 = DWC_READ_REG32(&core_if->dev_if-> ++ out_ep_regs[epnum]->doepctl); ++ if (ep->dwc_ep.frame_num & 0x1) { ++ depctl.b.setd1pid = 1; ++ depctl.b.setd0pid = 0; ++ } else { ++ depctl.b.setd0pid = 1; ++ depctl.b.setd1pid = 0; ++ } ++ DWC_WRITE_REG32(&core_if->dev_if-> ++ out_ep_regs[epnum]->doepctl, depctl.d32); ++ } ++ start_next_request(ep); ++ doepmsk.b.outtknepdis = 1; ++ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->doepmsk, ++ doepmsk.d32, 0); ++ } ++ CLEAR_OUT_EP_INTR(core_if, epnum, outtknepdis); ++ } ++ + /* NAK Interrutp */ + if (doepint.b.nak) { + DWC_DEBUGPL(DBG_ANY, "EP%d OUT NAK\n", epnum); +@@ -3709,7 +4326,15 @@ + + #undef CLEAR_OUT_EP_INTR + } +- ++static int drop_transfer(uint32_t trgt_fr, uint32_t curr_fr, uint8_t frm_overrun) ++{ ++ int retval = 0; ++ if(!frm_overrun && curr_fr >= trgt_fr) ++ retval = 1; ++ else if (frm_overrun && (curr_fr >= trgt_fr && ((curr_fr - trgt_fr) < 0x3FFF/2))) ++ retval = 1; ++ return retval; ++} + /** + * Incomplete ISO IN Transfer Interrupt. + * This interrupt indicates one of the following conditions occurred +@@ -3740,9 +4365,9 @@ + dwc_ep = &pcd->in_ep[i].dwc_ep; + if (dwc_ep->active && dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) { + deptsiz.d32 = +- dwc_read_reg32(&dev_if->in_ep_regs[i]->dieptsiz); ++ DWC_READ_REG32(&dev_if->in_ep_regs[i]->dieptsiz); + depctl.d32 = +- dwc_read_reg32(&dev_if->in_ep_regs[i]->diepctl); ++ DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl); + + if (depctl.b.epdis && deptsiz.d32) { + set_current_pkt_info(GET_CORE_IF(pcd), dwc_ep); +@@ -3766,7 +4391,7 @@ + } + + dsts.d32 = +- dwc_read_reg32(&GET_CORE_IF(pcd)->dev_if-> ++ DWC_READ_REG32(&GET_CORE_IF(pcd)->dev_if-> + dev_global_regs->dsts); + dwc_ep->next_frame = dsts.b.soffn; + +@@ -3778,19 +4403,40 @@ + } + + #else +- gintmsk_data_t intr_mask = {.d32 = 0 }; +- DWC_PRINTF("INTERRUPT Handler not implemented for %s\n", +- "IN ISOC Incomplete"); ++ depctl_data_t depctl = {.d32 = 0 }; ++ dwc_ep_t *dwc_ep; ++ dwc_otg_dev_if_t *dev_if; ++ int i; ++ dev_if = GET_CORE_IF(pcd)->dev_if; + +- intr_mask.b.incomplisoin = 1; +- dwc_modify_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk, +- intr_mask.d32, 0); ++ DWC_DEBUGPL(DBG_PCD,"Incomplete ISO IN \n"); ++ ++ for (i = 1; i <= dev_if->num_in_eps; ++i) { ++ dwc_ep = &pcd->in_ep[i-1].dwc_ep; ++ depctl.d32 = ++ DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl); ++ if (depctl.b.epena && dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) { ++ if (drop_transfer(dwc_ep->frame_num, GET_CORE_IF(pcd)->frame_num, ++ dwc_ep->frm_overrun)) ++ { ++ depctl.d32 = ++ DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl); ++ depctl.b.snak = 1; ++ depctl.b.epdis = 1; ++ DWC_MODIFY_REG32(&dev_if->in_ep_regs[i]->diepctl, depctl.d32, depctl.d32); ++ } ++ } ++ } ++ ++ /*intr_mask.b.incomplisoin = 1; ++ DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk, ++ intr_mask.d32, 0); */ + #endif //DWC_EN_ISOC + + /* Clear interrupt */ + gintsts.d32 = 0; + gintsts.b.incomplisoin = 1; +- dwc_write_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintsts, ++ DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts, + gintsts.d32); + + return 1; +@@ -3800,7 +4446,7 @@ + * Incomplete ISO OUT Transfer Interrupt. + * + * This interrupt indicates that the core has dropped an ISO OUT +- * packet. The following conditions can be the cause: ++ * packet. The following conditions can be the cause: + * - FIFO Full, the entire packet would not fit in the FIFO. + * - CRC Error + * - Corrupted Token +@@ -3808,7 +4454,7 @@ + * -# Determine the EP + * -# Set incomplete flag in dwc_ep structure + * -# Read any data from the FIFO +- * -# Disable EP. when "Endpoint Disabled" interrupt is received ++ * -# Disable EP. When "Endpoint Disabled" interrupt is received + * re-enable EP. + */ + int32_t dwc_otg_pcd_handle_incomplete_isoc_out_intr(dwc_otg_pcd_t * pcd) +@@ -3831,9 +4477,9 @@ + if (pcd->out_ep[i].dwc_ep.active && + pcd->out_ep[i].dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) { + deptsiz.d32 = +- dwc_read_reg32(&dev_if->out_ep_regs[i]->doeptsiz); ++ DWC_READ_REG32(&dev_if->out_ep_regs[i]->doeptsiz); + depctl.d32 = +- dwc_read_reg32(&dev_if->out_ep_regs[i]->doepctl); ++ DWC_READ_REG32(&dev_if->out_ep_regs[i]->doepctl); + + if (depctl.b.epdis && deptsiz.d32) { + set_current_pkt_info(GET_CORE_IF(pcd), +@@ -3858,7 +4504,7 @@ + } + + dsts.d32 = +- dwc_read_reg32(&GET_CORE_IF(pcd)->dev_if-> ++ DWC_READ_REG32(&GET_CORE_IF(pcd)->dev_if-> + dev_global_regs->dsts); + dwc_ep->next_frame = dsts.b.soffn; + +@@ -3871,20 +4517,55 @@ + #else + /** @todo implement ISR */ + gintmsk_data_t intr_mask = {.d32 = 0 }; ++ dwc_otg_core_if_t *core_if; ++ deptsiz_data_t deptsiz = {.d32 = 0 }; ++ depctl_data_t depctl = {.d32 = 0 }; ++ dctl_data_t dctl = {.d32 = 0 }; ++ dwc_ep_t *dwc_ep = NULL; ++ int i; ++ core_if = GET_CORE_IF(pcd); + +- DWC_PRINTF("INTERRUPT Handler not implemented for %s\n", +- "OUT ISOC Incomplete"); ++ for (i = 0; i < core_if->dev_if->num_out_eps; ++i) { ++ dwc_ep = &pcd->out_ep[i].dwc_ep; ++ depctl.d32 = ++ DWC_READ_REG32(&core_if->dev_if->out_ep_regs[dwc_ep->num]->doepctl); ++ if (depctl.b.epena && depctl.b.dpid == (core_if->frame_num & 0x1)) { ++ core_if->dev_if->isoc_ep = dwc_ep; ++ deptsiz.d32 = ++ DWC_READ_REG32(&core_if->dev_if->out_ep_regs[dwc_ep->num]->doeptsiz); ++ break; ++ } ++ } ++ dctl.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dctl); ++ gintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts); ++ intr_mask.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintmsk); + +- intr_mask.b.incomplisoout = 1; +- dwc_modify_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk, +- intr_mask.d32, 0); ++ if (!intr_mask.b.goutnakeff) { ++ /* Unmask it */ ++ intr_mask.b.goutnakeff = 1; ++ DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, intr_mask.d32); ++ } ++ if (!gintsts.b.goutnakeff) { ++ dctl.b.sgoutnak = 1; ++ } ++ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32); + +-#endif /* DWC_EN_ISOC */ ++ depctl.d32 = DWC_READ_REG32(&core_if->dev_if->out_ep_regs[dwc_ep->num]->doepctl); ++ if (depctl.b.epena) { ++ depctl.b.epdis = 1; ++ depctl.b.snak = 1; ++ } ++ DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[dwc_ep->num]->doepctl, depctl.d32); ++ ++ intr_mask.d32 = 0; ++ intr_mask.b.incomplisoout = 1; ++ ++#endif /* DWC_EN_ISOC */ + + /* Clear interrupt */ + gintsts.d32 = 0; + gintsts.b.incomplisoout = 1; +- dwc_write_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintsts, ++ DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts, + gintsts.d32); + + return 1; +@@ -3898,34 +4579,35 @@ + { + dwc_otg_dev_if_t *dev_if = GET_CORE_IF(pcd)->dev_if; + depctl_data_t diepctl = {.d32 = 0 }; +- depctl_data_t diepctl_rd = {.d32 = 0 }; + gintmsk_data_t intr_mask = {.d32 = 0 }; + gintsts_data_t gintsts; ++ dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd); + int i; + + DWC_DEBUGPL(DBG_PCD, "Global IN NAK Effective\n"); + + /* Disable all active IN EPs */ +- diepctl.b.epdis = 1; +- diepctl.b.snak = 1; +- + for (i = 0; i <= dev_if->num_in_eps; i++) { +- diepctl_rd.d32 = +- dwc_read_reg32(&dev_if->in_ep_regs[i]->diepctl); +- if (diepctl_rd.b.epena) { +- dwc_write_reg32(&dev_if->in_ep_regs[i]->diepctl, +- diepctl.d32); +- } ++ diepctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl); ++ if (!(diepctl.b.eptype & 1) && diepctl.b.epena) { ++ if (core_if->start_predict > 0) ++ core_if->start_predict++; ++ diepctl.b.epdis = 1; ++ diepctl.b.snak = 1; ++ DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->diepctl, diepctl.d32); ++ } + } ++ ++ + /* Disable the Global IN NAK Effective Interrupt */ + intr_mask.b.ginnakeff = 1; +- dwc_modify_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk, ++ DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk, + intr_mask.d32, 0); + + /* Clear interrupt */ + gintsts.d32 = 0; + gintsts.b.ginnakeff = 1; +- dwc_write_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintsts, ++ DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts, + gintsts.d32); + + return 1; +@@ -3937,20 +4619,71 @@ + */ + int32_t dwc_otg_pcd_handle_out_nak_effective(dwc_otg_pcd_t * pcd) + { ++ dwc_otg_dev_if_t *dev_if = GET_CORE_IF(pcd)->dev_if; + gintmsk_data_t intr_mask = {.d32 = 0 }; + gintsts_data_t gintsts; ++ depctl_data_t doepctl; ++ int i; + +- DWC_PRINTF("INTERRUPT Handler not implemented for %s\n", +- "Global IN NAK Effective\n"); +- /* Disable the Global IN NAK Effective Interrupt */ ++ /* Disable the Global OUT NAK Effective Interrupt */ + intr_mask.b.goutnakeff = 1; +- dwc_modify_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk, +- intr_mask.d32, 0); +- ++ DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk, ++ intr_mask.d32, 0); ++ ++ /* If DEV OUT NAK enabled*/ ++ if (pcd->core_if->core_params->dev_out_nak) { ++ /* Run over all out endpoints to determine the ep number on ++ * which the timeout has happened ++ */ ++ for (i = 0; i <= dev_if->num_out_eps; i++) { ++ if ( pcd->core_if->ep_xfer_info[i].state == 2 ) ++ break; ++ } ++ if (i > dev_if->num_out_eps) { ++ dctl_data_t dctl; ++ dctl.d32 = DWC_READ_REG32(&dev_if-> ++ dev_global_regs->dctl); ++ dctl.b.cgoutnak = 1; ++ DWC_WRITE_REG32(&dev_if->dev_global_regs->dctl, ++ dctl.d32); ++ goto out; ++ } ++ ++ /* Disable the endpoint */ ++ doepctl.d32 = DWC_READ_REG32(&dev_if-> ++ out_ep_regs[i]->doepctl); ++ if (doepctl.b.epena) { ++ doepctl.b.epdis = 1; ++ doepctl.b.snak = 1; ++ } ++ DWC_WRITE_REG32(&dev_if->out_ep_regs[i]->doepctl, doepctl.d32); ++ return 1; ++ } ++ /* We come here from Incomplete ISO OUT handler */ ++ if(dev_if->isoc_ep) ++ { ++ dwc_ep_t *dwc_ep = (dwc_ep_t *)dev_if->isoc_ep; ++ uint32_t epnum = dwc_ep->num; ++ doepint_data_t doepint; ++ doepint.d32 = DWC_READ_REG32(&dev_if->out_ep_regs[dwc_ep->num]->doepint); ++ dev_if->isoc_ep = NULL; ++ doepctl.d32 = DWC_READ_REG32(&dev_if->out_ep_regs[epnum]->doepctl); ++ DWC_PRINTF("Before disable DOEPCTL = %08x\n", doepctl.d32); ++ if (doepctl.b.epena) { ++ doepctl.b.epdis = 1; ++ doepctl.b.snak = 1; ++ } ++ DWC_WRITE_REG32(&dev_if->out_ep_regs[epnum]->doepctl, doepctl.d32); ++ return 1; ++ } else ++ DWC_PRINTF("INTERRUPT Handler not implemented for %s\n", ++ "Global OUT NAK Effective\n"); ++ ++out: + /* Clear interrupt */ + gintsts.d32 = 0; + gintsts.b.goutnakeff = 1; +- dwc_write_reg32(&GET_CORE_IF(pcd)->core_global_regs->gintsts, ++ DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts, + gintsts.d32); + + return 1; +@@ -3977,11 +4710,15 @@ + gintsts_data_t gintr_status; + int32_t retval = 0; + ++ /* Exit from ISR if core is hibernated */ ++ if (core_if->hibernation_suspend == 1) { ++ return retval; ++ } + #ifdef VERBOSE + DWC_DEBUGPL(DBG_ANY, "%s() gintsts=%08x gintmsk=%08x\n", + __func__, +- dwc_read_reg32(&global_regs->gintsts), +- dwc_read_reg32(&global_regs->gintmsk)); ++ DWC_READ_REG32(&global_regs->gintsts), ++ DWC_READ_REG32(&global_regs->gintmsk)); + #endif + + if (dwc_otg_is_device_mode(core_if)) { +@@ -3989,8 +4726,8 @@ + #ifdef VERBOSE + DWC_DEBUGPL(DBG_PCDV, "%s() gintsts=%08x gintmsk=%08x\n", + __func__, +- dwc_read_reg32(&global_regs->gintsts), +- dwc_read_reg32(&global_regs->gintmsk)); ++ DWC_READ_REG32(&global_regs->gintsts), ++ DWC_READ_REG32(&global_regs->gintmsk)); + #endif + + gintr_status.d32 = dwc_otg_read_core_intr(core_if); +@@ -4008,9 +4745,6 @@ + if (gintr_status.b.nptxfempty) { + retval |= dwc_otg_pcd_handle_np_tx_fifo_empty_intr(pcd); + } +- if (gintr_status.b.ginnakeff) { +- retval |= dwc_otg_pcd_handle_in_nak_effective(pcd); +- } + if (gintr_status.b.goutnakeff) { + retval |= dwc_otg_pcd_handle_out_nak_effective(pcd); + } +@@ -4035,9 +4769,6 @@ + retval |= + dwc_otg_pcd_handle_end_periodic_frame_intr(pcd); + } +- if (gintr_status.b.epmismatch) { +- retval |= dwc_otg_pcd_handle_ep_mismatch_intr(core_if); +- } + if (gintr_status.b.inepint) { + if (!core_if->multiproc_int_enable) { + retval |= dwc_otg_pcd_handle_in_ep_intr(pcd); +@@ -4048,6 +4779,15 @@ + retval |= dwc_otg_pcd_handle_out_ep_intr(pcd); + } + } ++ if (gintr_status.b.epmismatch) { ++ retval |= dwc_otg_pcd_handle_ep_mismatch_intr(pcd); ++ } ++ if (gintr_status.b.fetsusp) { ++ retval |= dwc_otg_pcd_handle_ep_fetsusp_intr(pcd); ++ } ++ if (gintr_status.b.ginnakeff) { ++ retval |= dwc_otg_pcd_handle_in_nak_effective(pcd); ++ } + if (gintr_status.b.incomplisoin) { + retval |= + dwc_otg_pcd_handle_incomplete_isoc_in_intr(pcd); +@@ -4057,7 +4797,7 @@ + dwc_otg_pcd_handle_incomplete_isoc_out_intr(pcd); + } + +- /* In MPI mode De vice Endpoints intterrupts are asserted ++ /* In MPI mode Device Endpoints interrupts are asserted + * without setting outepintr and inepint bits set, so these + * Interrupt handlers are called without checking these bit-fields + */ +@@ -4067,11 +4807,11 @@ + } + #ifdef VERBOSE + DWC_DEBUGPL(DBG_PCDV, "%s() gintsts=%0x\n", __func__, +- dwc_read_reg32(&global_regs->gintsts)); ++ DWC_READ_REG32(&global_regs->gintsts)); + #endif + DWC_SPINUNLOCK(pcd->lock); + } + return retval; + } + +-#endif /* DWC_HOST_ONLY */ ++#endif /* DWC_HOST_ONLY */ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_pcd_linux.c +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/dwc_otg_pcd_linux.c 2013-07-26 19:31:23.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_pcd_linux.c 2013-07-26 19:34:44.000000000 +0000 +@@ -1,8 +1,8 @@ + /* ========================================================================== + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_pcd_linux.c $ +- * $Revision: #7 $ +- * $Date: 2009/04/03 $ +- * $Change: 1225160 $ ++ * $Revision: #19 $ ++ * $Date: 2011/10/26 $ ++ * $Change: 1873028 $ + * + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless +@@ -53,47 +53,9 @@ + * + */ + +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +- +-#if defined(LM_INTERFACE) +-//# include +-#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30)) +-#include +-#else +-/* by 2.6.31, at least, the location of some headers has changed +-*/ +-#include +-#endif +- +-#elif defined(PLATFORM_INTERFACE) +-#include +-#endif +- +-#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30)) +-#include +-#include +-#include +-#else +-/* by 2.6.31, at least, the location of some headers has changed +-*/ +-#include +-#include +-#include +-#endif +- +-#include +- ++#include "dwc_otg_os_dep.h" + #include "dwc_otg_pcd_if.h" ++#include "dwc_otg_pcd.h" + #include "dwc_otg_driver.h" + #include "dwc_otg_dbg.h" + +@@ -111,6 +73,26 @@ + + /* Display the contents of the buffer */ + extern void dump_msg(const u8 * buf, unsigned int length); ++/** ++ * Get the dwc_otg_pcd_ep_t* from usb_ep* pointer - NULL in case ++ * if the endpoint is not found ++ */ ++static struct dwc_otg_pcd_ep *ep_from_handle(dwc_otg_pcd_t * pcd, void *handle) ++{ ++ int i; ++ if (pcd->ep0.priv == handle) { ++ return &pcd->ep0; ++ } ++ ++ for (i = 0; i < MAX_EPS_CHANNELS - 1; i++) { ++ if (pcd->in_ep[i].priv == handle) ++ return &pcd->in_ep[i]; ++ if (pcd->out_ep[i].priv == handle) ++ return &pcd->out_ep[i]; ++ } ++ ++ return NULL; ++} + + /* USB Endpoint Operations */ + /* +@@ -164,6 +146,13 @@ + return -ESHUTDOWN; + } + ++ /* Delete after check - MAS */ ++#if 0 ++ nat = (uint32_t) ep_desc->wMaxPacketSize; ++ printk(KERN_ALERT "%s: nat (before) =%d\n", __func__, nat); ++ nat = (nat >> 11) & 0x03; ++ printk(KERN_ALERT "%s: nat (after) =%d\n", __func__, nat); ++#endif + retval = dwc_otg_pcd_ep_enable(gadget_wrapper->pcd, + (const uint8_t *)ep_desc, + (void *)usb_ep); +@@ -227,7 +216,7 @@ + return 0; + } + memset(usb_req, 0, sizeof(*usb_req)); +- usb_req->dma = DWC_INVALID_DMA_ADDR; ++ usb_req->dma = DWC_DMA_ADDR_INVALID; + + return usb_req; + } +@@ -251,7 +240,7 @@ + kfree(req); + } + +-#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30)) ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28) + /** + * This function allocates an I/O buffer to be used for a transfer + * to/from the specified endpoint. +@@ -329,7 +318,9 @@ + gfp_t gfp_flags) + { + dwc_otg_pcd_t *pcd; +- int retval; ++ struct dwc_otg_pcd_ep *ep = NULL; ++ int retval = 0, is_isoc_ep = 0; ++ dma_addr_t dma_addr = DWC_DMA_ADDR_INVALID; + + DWC_DEBUGPL(DBG_PCDV, "%s(%p,%p,%d)\n", + __func__, usb_ep, usb_req, gfp_flags); +@@ -359,7 +350,44 @@ + usb_req->status = -EINPROGRESS; + usb_req->actual = 0; + +- retval = dwc_otg_pcd_ep_queue(pcd, usb_ep, usb_req->buf, usb_req->dma, ++ ep = ep_from_handle(pcd, usb_ep); ++ if (ep == NULL) ++ is_isoc_ep = 0; ++ else ++ is_isoc_ep = (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) ? 1 : 0; ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28) ++ dma_addr = usb_req->dma; ++#else ++ if (GET_CORE_IF(pcd)->dma_enable) { ++ dwc_otg_device_t *otg_dev = gadget_wrapper->pcd->otg_dev; ++ struct device *dev = NULL; ++ ++ if (otg_dev != NULL) ++ dev = DWC_OTG_OS_GETDEV(otg_dev->os_dep); ++ ++ if (usb_req->length != 0 && ++ usb_req->dma == DWC_DMA_ADDR_INVALID) { ++ dma_addr = dma_map_single(dev, usb_req->buf, ++ usb_req->length, ++ ep->dwc_ep.is_in ? ++ DMA_TO_DEVICE: ++ DMA_FROM_DEVICE); ++ } ++ } ++#endif ++ ++#ifdef DWC_UTE_PER_IO ++ if (is_isoc_ep == 1) { ++ retval = dwc_otg_pcd_xiso_ep_queue(pcd, usb_ep, usb_req->buf, dma_addr, ++ usb_req->length, usb_req->zero, usb_req, ++ gfp_flags == GFP_ATOMIC ? 1 : 0, &usb_req->ext_req); ++ if (retval) ++ return -EINVAL; ++ ++ return 0; ++ } ++#endif ++ retval = dwc_otg_pcd_ep_queue(pcd, usb_ep, usb_req->buf, dma_addr, + usb_req->length, usb_req->zero, usb_req, + gfp_flags == GFP_ATOMIC ? 1 : 0); + if (retval) { +@@ -568,8 +596,10 @@ + .alloc_request = dwc_otg_pcd_alloc_request, + .free_request = dwc_otg_pcd_free_request, + ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28) + .alloc_buffer = dwc_otg_pcd_alloc_buffer, + .free_buffer = dwc_otg_pcd_free_buffer, ++#endif + + .queue = ep_queue, + .dequeue = ep_dequeue, +@@ -610,7 +640,7 @@ + .alloc_request = dwc_otg_pcd_alloc_request, + .free_request = dwc_otg_pcd_free_request, + +-#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30)) ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28) + .alloc_buffer = dwc_otg_pcd_alloc_buffer, + .free_buffer = dwc_otg_pcd_free_buffer, + #else +@@ -627,7 +657,7 @@ + + }; + +-#endif /* _EN_ISOC_ */ ++#endif /* _EN_ISOC_ */ + /* Gadget Operations */ + /** + * The following gadget operations will be implemented in the DWC_otg +@@ -761,12 +791,78 @@ + + return 0; + } +-#endif /* DWC_EN_ISOC */ ++#endif /* DWC_EN_ISOC */ ++ ++#ifdef DWC_UTE_PER_IO ++/** ++ * Copy the contents of the extended request to the Linux usb_request's ++ * extended part and call the gadget's completion. ++ * ++ * @param pcd Pointer to the pcd structure ++ * @param ep_handle Void pointer to the usb_ep structure ++ * @param req_handle Void pointer to the usb_request structure ++ * @param status Request status returned from the portable logic ++ * @param ereq_port Void pointer to the extended request structure ++ * created in the the portable part that contains the ++ * results of the processed iso packets. ++ */ ++static int _xisoc_complete(dwc_otg_pcd_t * pcd, void *ep_handle, ++ void *req_handle, int32_t status, void *ereq_port) ++{ ++ struct dwc_ute_iso_req_ext *ereqorg = NULL; ++ struct dwc_iso_xreq_port *ereqport = NULL; ++ struct dwc_ute_iso_packet_descriptor *desc_org = NULL; ++ int i; ++ struct usb_request *req; ++ //struct dwc_ute_iso_packet_descriptor * ++ //int status = 0; ++ ++ req = (struct usb_request *)req_handle; ++ ereqorg = &req->ext_req; ++ ereqport = (struct dwc_iso_xreq_port *)ereq_port; ++ desc_org = ereqorg->per_io_frame_descs; ++ ++ if (req && req->complete) { ++ /* Copy the request data from the portable logic to our request */ ++ for (i = 0; i < ereqport->pio_pkt_count; i++) { ++ desc_org[i].actual_length = ++ ereqport->per_io_frame_descs[i].actual_length; ++ desc_org[i].status = ++ ereqport->per_io_frame_descs[i].status; ++ } ++ ++ switch (status) { ++ case -DWC_E_SHUTDOWN: ++ req->status = -ESHUTDOWN; ++ break; ++ case -DWC_E_RESTART: ++ req->status = -ECONNRESET; ++ break; ++ case -DWC_E_INVALID: ++ req->status = -EINVAL; ++ break; ++ case -DWC_E_TIMEOUT: ++ req->status = -ETIMEDOUT; ++ break; ++ default: ++ req->status = status; ++ } ++ ++ /* And call the gadget's completion */ ++ req->complete(ep_handle, req); ++ } ++ ++ return 0; ++} ++#endif /* DWC_UTE_PER_IO */ + + static int _complete(dwc_otg_pcd_t * pcd, void *ep_handle, + void *req_handle, int32_t status, uint32_t actual) + { + struct usb_request *req = (struct usb_request *)req_handle; ++#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,27) ++ struct dwc_otg_pcd_ep *ep = NULL; ++#endif + + if (req && req->complete) { + switch (status) { +@@ -786,9 +882,28 @@ + req->status = status; + + } ++ + req->actual = actual; ++ DWC_SPINUNLOCK(pcd->lock); + req->complete(ep_handle, req); ++ DWC_SPINLOCK(pcd->lock); ++ } ++#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,27) ++ ep = ep_from_handle(pcd, ep_handle); ++ if (GET_CORE_IF(pcd)->dma_enable) { ++ if (req->length != 0) { ++ dwc_otg_device_t *otg_dev = gadget_wrapper->pcd->otg_dev; ++ struct device *dev = NULL; ++ ++ if (otg_dev != NULL) ++ dev = DWC_OTG_OS_GETDEV(otg_dev->os_dep); ++ ++ dma_unmap_single(dev, req->dma, req->length, ++ ep->dwc_ep.is_in ? ++ DMA_TO_DEVICE: DMA_FROM_DEVICE); ++ } + } ++#endif + + return 0; + } +@@ -850,11 +965,9 @@ + int retval = -DWC_E_INVALID; + if (gadget_wrapper->driver->cfi_feature_setup) { + retval = +- gadget_wrapper->driver->cfi_feature_setup(&gadget_wrapper-> +- gadget, +- (struct +- cfi_usb_ctrlrequest +- *)cfi_req); ++ gadget_wrapper->driver-> ++ cfi_feature_setup(&gadget_wrapper->gadget, ++ (struct cfi_usb_ctrlrequest *)cfi_req); + } + + return retval; +@@ -876,6 +989,9 @@ + #ifdef DWC_UTE_CFI + .cfi_setup = _cfi_setup, + #endif ++#ifdef DWC_UTE_PER_IO ++ .xisoc_complete = _xisoc_complete, ++#endif + }; + + /** +@@ -938,6 +1054,7 @@ + + int i; + struct usb_ep *ep; ++ int8_t dev_endpoints; + + DWC_DEBUGPL(DBG_PCDV, "%s\n", __func__); + +@@ -968,12 +1085,13 @@ + /** + * Initialize the EP structures. + */ ++ dev_endpoints = d->pcd->core_if->dev_if->num_in_eps; + +- for (i = 0; i < 15; i++) { ++ for (i = 0; i < dev_endpoints; i++) { + ep = &d->in_ep[i]; + + /* Init the usb_ep structure. */ +- ep->name = names[i + 1]; ++ ep->name = names[d->pcd->in_ep[i].dwc_ep.num]; + ep->ops = (struct usb_ep_ops *)&dwc_otg_pcd_ep_ops; + + /** +@@ -984,11 +1102,13 @@ + list_add_tail(&ep->ep_list, &d->gadget.ep_list); + } + +- for (i = 0; i < 15; i++) { ++ dev_endpoints = d->pcd->core_if->dev_if->num_out_eps; ++ ++ for (i = 0; i < dev_endpoints; i++) { + ep = &d->out_ep[i]; + + /* Init the usb_ep structure. */ +- ep->name = names[15 + i + 1]; ++ ep->name = names[15 + d->pcd->out_ep[i].dwc_ep.num]; + ep->ops = (struct usb_ep_ops *)&dwc_otg_pcd_ep_ops; + + /** +@@ -1017,29 +1137,14 @@ + DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, dev); + } + +-static struct gadget_wrapper *alloc_wrapper( +-#ifdef LM_INTERFACE +- struct lm_device *_dev +-#elif defined(PCI_INTERFACE) +- struct pci_dev *_dev +-#elif defined(PLATFORM_INTERFACE) +- struct platform_device *_dev +-#endif +- ) +-{ +-#ifdef LM_INTERFACE +- dwc_otg_device_t *otg_dev = lm_get_drvdata(_dev); +-#elif defined(PCI_INTERFACE) +- dwc_otg_device_t *otg_dev = pci_get_drvdata(_dev); +-#elif defined(PLATFORM_INTERFACE) +- dwc_otg_device_t *otg_dev = platform_get_drvdata(_dev); +-#endif ++static struct gadget_wrapper *alloc_wrapper(dwc_bus_dev_t *_dev) ++{ + static char pcd_name[] = "dwc_otg_pcd"; +- ++ dwc_otg_device_t *otg_dev = DWC_OTG_BUSDRVDATA(_dev); + struct gadget_wrapper *d; + int retval; + +- d = dwc_alloc(sizeof(*d)); ++ d = DWC_ALLOC(sizeof(*d)); + if (d == NULL) { + return NULL; + } +@@ -1048,12 +1153,13 @@ + + d->gadget.name = pcd_name; + d->pcd = otg_dev->pcd; +-#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30)) ++ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30) + strcpy(d->gadget.dev.bus_id, "gadget"); + #else +- /*d->gadget.dev.bus = NULL;*/ +- d->gadget.dev.init_name = "gadget"; ++ dev_set_name(&d->gadget.dev, "%s", "gadget"); + #endif ++ + d->gadget.dev.parent = &_dev->dev; + d->gadget.dev.release = dwc_otg_pcd_gadget_release; + d->gadget.ops = &dwc_otg_pcd_ops; +@@ -1065,7 +1171,7 @@ + retval = device_register(&d->gadget.dev); + if (retval != 0) { + DWC_ERROR("device_register failed\n"); +- dwc_free(d); ++ DWC_FREE(d); + return NULL; + } + +@@ -1082,33 +1188,16 @@ + } + + device_unregister(&d->gadget.dev); +- dwc_free(d); ++ DWC_FREE(d); + } + + /** + * This function initialized the PCD portion of the driver. + * + */ +-int pcd_init( +-#ifdef LM_INTERFACE +- struct lm_device *_dev +-#elif defined(PCI_INTERFACE) +- struct pci_dev *_dev +-#elif defined(PLATFORM_INTERFACE) +- struct platform_device *_dev +-#endif +- ) +- +-{ +-#ifdef LM_INTERFACE +- dwc_otg_device_t *otg_dev = lm_get_drvdata(_dev); +-#elif defined(PCI_INTERFACE) +- dwc_otg_device_t *otg_dev = pci_get_drvdata(_dev); +-#elif defined(PLATFORM_INTERFACE) +- dwc_otg_device_t *otg_dev = platform_get_drvdata(_dev); +-#endif +- int devirq; +- ++int pcd_init(dwc_bus_dev_t *_dev) ++{ ++ dwc_otg_device_t *otg_dev = DWC_OTG_BUSDRVDATA(_dev); + int retval = 0; + + DWC_DEBUGPL(DBG_PCDV, "%s(%p) otg_dev=%p\n", __func__, _dev, otg_dev); +@@ -1120,30 +1209,40 @@ + return -ENOMEM; + } + ++ otg_dev->pcd->otg_dev = otg_dev; + gadget_wrapper = alloc_wrapper(_dev); + + /* + * Initialize EP structures + */ + gadget_add_eps(gadget_wrapper); +- + /* + * Setup interupt handler + */ + #ifdef PLATFORM_INTERFACE +- devirq = platform_get_irq(_dev, 0); +-#else +- devirq = _dev->irq; +-#endif +- DWC_DEBUGPL(DBG_ANY, "registering handler for irq%d\n", devirq); +- retval = request_irq(devirq, dwc_otg_pcd_irq, ++ DWC_DEBUGPL(DBG_ANY, "registering handler for irq%d\n", ++ platform_get_irq(_dev, 0)); ++ retval = request_irq(platform_get_irq(_dev, 0), dwc_otg_pcd_irq, + IRQF_SHARED, gadget_wrapper->gadget.name, + otg_dev->pcd); + if (retval != 0) { +- DWC_ERROR("request of irq%d failed\n", devirq); ++ DWC_ERROR("request of irq%d failed\n", ++ platform_get_irq(_dev, 0)); ++ free_wrapper(gadget_wrapper); ++ return -EBUSY; ++ } ++#else ++ DWC_DEBUGPL(DBG_ANY, "registering handler for irq%d\n", ++ _dev->irq); ++ retval = request_irq(_dev->irq, dwc_otg_pcd_irq, ++ IRQF_SHARED | IRQF_DISABLED, ++ gadget_wrapper->gadget.name, otg_dev->pcd); ++ if (retval != 0) { ++ DWC_ERROR("request of irq%d failed\n", _dev->irq); + free_wrapper(gadget_wrapper); + return -EBUSY; + } ++#endif + + dwc_otg_pcd_start(gadget_wrapper->pcd, &fops); + +@@ -1153,23 +1252,9 @@ + /** + * Cleanup the PCD. + */ +-void pcd_remove( +-#ifdef LM_INTERFACE +- struct lm_device *_dev +-#elif defined(PCI_INTERFACE) +- struct pci_dev *_dev +-#elif defined(PLATFORM_INTERFACE) +- struct platform_device *_dev +-#endif +- ) +-{ +-#ifdef LM_INTERFACE +- dwc_otg_device_t *otg_dev = lm_get_drvdata(_dev); +-#elif defined(PCI_INTERFACE) +- dwc_otg_device_t *otg_dev = pci_get_drvdata(_dev); +-#elif defined(PLATFORM_INTERFACE) +- dwc_otg_device_t *otg_dev = platform_get_drvdata(_dev); +-#endif ++void pcd_remove(dwc_bus_dev_t *_dev) ++{ ++ dwc_otg_device_t *otg_dev = DWC_OTG_BUSDRVDATA(_dev); + dwc_otg_pcd_t *pcd = otg_dev->pcd; + + DWC_DEBUGPL(DBG_PCDV, "%s(%p) otg_dev %p\n", __func__, _dev, otg_dev); +@@ -1196,6 +1281,7 @@ + * then a host may connect again, or the driver might get unbound. + * + * @param driver The driver being registered ++ * @param bind The bind function of gadget driver + */ + #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,37) + int usb_gadget_register_driver(struct usb_gadget_driver *driver) +@@ -1213,7 +1299,7 @@ + #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,37) + !driver->bind || + #else +- !bind || ++ !bind || + #endif + !driver->unbind || !driver->disconnect || !driver->setup) { + DWC_DEBUGPL(DBG_PCDV, "EINVAL\n"); +@@ -1249,7 +1335,6 @@ + driver->driver.name); + return 0; + } +- + #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,37) + EXPORT_SYMBOL(usb_gadget_register_driver); + #else +@@ -1285,4 +1370,4 @@ + + EXPORT_SYMBOL(usb_gadget_unregister_driver); + +-#endif /* DWC_HOST_ONLY */ ++#endif /* DWC_HOST_ONLY */ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_regs.h +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/dwc_otg_regs.h 2013-07-26 19:31:23.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_regs.h 2013-07-26 19:34:44.000000000 +0000 +@@ -1,13 +1,13 @@ + /* ========================================================================== + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_regs.h $ +- * $Revision: #76 $ +- * $Date: 2009/04/02 $ +- * $Change: 1224216 $ ++ * $Revision: #97 $ ++ * $Date: 2011/10/24 $ ++ * $Change: 1871160 $ + * + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless + * otherwise expressly agreed to in writing between Synopsys and you. +- * ++ * + * The Software IS NOT an item of Licensed Software or Licensed Product under + * any End User Software License Agreement or Agreement for Licensed Product + * with Synopsys or any supplement thereto. You are permitted to use and +@@ -17,7 +17,7 @@ + * any information contained herein except pursuant to this license grant from + * Synopsys. If you do not agree with this notice, including the disclaimer + * below, then you are not authorized to use the Software. +- * ++ * + * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +@@ -64,7 +64,7 @@ + */ + + /****************************************************************************/ +-/** DWC_otg Core registers . ++/** DWC_otg Core registers . + * The dwc_otg_core_global_regs structure defines the size + * and relative field offsets for the Core Global registers. + */ +@@ -132,21 +132,27 @@ + volatile uint32_t ghwcfg3; + /**User HW Config4 Register (Read Only). Offset: 050h*/ + volatile uint32_t ghwcfg4; +- /** Core LPM Configuration register */ ++ /** Core LPM Configuration register Offset: 054h*/ + volatile uint32_t glpmcfg; +- /** Reserved Offset: 058h-0FFh */ +- volatile uint32_t reserved[42]; ++ /** Global PowerDn Register Offset: 058h */ ++ volatile uint32_t gpwrdn; ++ /** Global DFIFO SW Config Register Offset: 05Ch */ ++ volatile uint32_t gdfifocfg; ++ /** ADP Control Register Offset: 060h */ ++ volatile uint32_t adpctl; ++ /** Reserved Offset: 064h-0FFh */ ++ volatile uint32_t reserved39[39]; + /** Host Periodic Transmit FIFO Size Register. Offset: 100h */ + volatile uint32_t hptxfsiz; +- /** Device Periodic Transmit FIFO#n Register if dedicated fifos are disabled, +- otherwise Device Transmit FIFO#n Register. ++ /** Device Periodic Transmit FIFO#n Register if dedicated fifos are disabled, ++ otherwise Device Transmit FIFO#n Register. + * Offset: 104h + (FIFO_Number-1)*04h, 1 <= FIFO Number <= 15 (1<=n<=15). */ +- volatile uint32_t dptxfsiz_dieptxf[15]; ++ volatile uint32_t dtxfsiz[15]; + } dwc_otg_core_global_regs_t; + + /** + * This union represents the bit fields of the Core OTG Control +- * and Status Register (GOTGCTL). Set the bits using the bit ++ * and Status Register (GOTGCTL). Set the bits using the bit + * fields then write the d32 value to the register. + */ + typedef union gotgctl_data { +@@ -156,18 +162,26 @@ + struct { + unsigned sesreqscs:1; + unsigned sesreq:1; +- unsigned reserved2_7:6; ++ unsigned vbvalidoven:1; ++ unsigned vbvalidovval:1; ++ unsigned avalidoven:1; ++ unsigned avalidovval:1; ++ unsigned bvalidoven:1; ++ unsigned bvalidovval:1; + unsigned hstnegscs:1; + unsigned hnpreq:1; + unsigned hstsethnpen:1; + unsigned devhnpen:1; + unsigned reserved12_15:4; + unsigned conidsts:1; +- unsigned reserved17:1; ++ unsigned dbnctime:1; + unsigned asesvld:1; + unsigned bsesvld:1; +- unsigned currmod:1; +- unsigned reserved21_31:11; ++ unsigned otgver:1; ++ unsigned reserved1:1; ++ unsigned multvalidbc:5; ++ unsigned chirpen:1; ++ unsigned reserved28_31:4; + } b; + } gotgctl_data_t; + +@@ -194,7 +208,7 @@ + /** Host Negotiation Success Status Change */ + unsigned hstnegsucstschng:1; + +- unsigned reserver10_16:7; ++ unsigned reserved10_16:7; + + /** Host Negotiation Detected */ + unsigned hstnegdet:1; +@@ -202,15 +216,17 @@ + unsigned adevtoutchng:1; + /** Debounce Done */ + unsigned debdone:1; ++ /** Multi-Valued input changed */ ++ unsigned mvic:1; + +- unsigned reserved31_20:12; ++ unsigned reserved31_21:11; + + } b; + } gotgint_data_t; + + /** + * This union represents the bit fields of the Core AHB Configuration +- * Register (GAHBCFG). Set/clear the bits using the bit fields then ++ * Register (GAHBCFG). Set/clear the bits using the bit fields then + * write the d32 value to the register. + */ + typedef union gahbcfg_data { +@@ -235,13 +251,17 @@ + unsigned ptxfemplvl:1; + #define DWC_GAHBCFG_TXFEMPTYLVL_EMPTY 1 + #define DWC_GAHBCFG_TXFEMPTYLVL_HALFEMPTY 0 +- unsigned reserved9_31:23; ++ unsigned reserved9_20:12; ++ unsigned remmemsupp:1; ++ unsigned notialldmawrit:1; ++ unsigned ahbsingle:1; ++ unsigned reserved24_31:8; + } b; + } gahbcfg_data_t; + + /** + * This union represents the bit fields of the Core USB Configuration +- * Register (GUSBCFG). Set the bits using the bit fields then write ++ * Register (GUSBCFG). Set the bits using the bit fields then write + * the d32 value to the register. + */ + typedef union gusbcfg_data { +@@ -258,7 +278,7 @@ + unsigned srpcap:1; + unsigned hnpcap:1; + unsigned usbtrdtim:4; +- unsigned nptxfrwnden:1; ++ unsigned reserved1:1; + unsigned phylpwrclksel:1; + unsigned otgutmifssel:1; + unsigned ulpi_fsls:1; +@@ -267,120 +287,19 @@ + unsigned ulpi_ext_vbus_drv:1; + unsigned ulpi_int_vbus_indicator:1; + unsigned term_sel_dl_pulse:1; +- unsigned reserved23_25:3; ++ unsigned indicator_complement:1; ++ unsigned indicator_pass_through:1; ++ unsigned ulpi_int_prot_dis:1; + unsigned ic_usb_cap:1; + unsigned ic_traffic_pull_remove:1; + unsigned tx_end_delay:1; +- unsigned reserved29_31:3; ++ unsigned force_host_mode:1; ++ unsigned force_dev_mode:1; ++ unsigned reserved31:1; + } b; + } gusbcfg_data_t; + + /** +- * This union represents the bit fields of the Core LPM Configuration +- * Register (GLPMCFG). Set the bits using bit fields then write +- * the d32 value to the register. +- */ +-typedef union glpmctl_data { +- /** raw register data */ +- uint32_t d32; +- /** register bits */ +- struct { +- /** LPM-Capable (LPMCap) (Device and Host) +- * The application uses this bit to control +- * the DWC_otg core LPM capabilities. +- */ +- unsigned lpm_cap_en:1; +- /** LPM response programmed by application (AppL1Res) (Device) +- * Handshake response to LPM token pre-programmed +- * by device application software. +- */ +- unsigned appl_resp:1; +- /** Host Initiated Resume Duration (HIRD) (Device and Host) +- * In Host mode this field indicates the value of HIRD +- * to be sent in an LPM transaction. +- * In Device mode this field is updated with the +- * Received LPM Token HIRD bmAttribute +- * when an ACK/NYET/STALL response is sent +- * to an LPM transaction. +- */ +- unsigned hird:4; +- /** RemoteWakeEnable (bRemoteWake) (Device and Host) +- * In Host mode this bit indicates the value of remote +- * wake up to be sent in wIndex field of LPM transaction. +- * In Device mode this field is updated with the +- * Received LPM Token bRemoteWake bmAttribute +- * when an ACK/NYET/STALL response is sent +- * to an LPM transaction. +- */ +- unsigned rem_wkup_en:1; +- /** Enable utmi_sleep_n (EnblSlpM) (Device and Host) +- * The application uses this bit to control +- * the utmi_sleep_n assertion to the PHY when in L1 state. +- */ +- unsigned en_utmi_sleep:1; +- /** HIRD Threshold (HIRD_Thres) (Device and Host) +- */ +- unsigned hird_thres:5; +- /** LPM Response (CoreL1Res) (Device and Host) +- * In Host mode this bit contains handsake response to +- * LPM transaction. +- * In Device mode the response of the core to +- * LPM transaction received is reflected in these two bits. +- - 0x0 : ERROR (No handshake response) +- - 0x1 : STALL +- - 0x2 : NYET +- - 0x3 : ACK +- */ +- unsigned lpm_resp:2; +- /** Port Sleep Status (SlpSts) (Device and Host) +- * This bit is set as long as a Sleep condition +- * is present on the USB bus. +- */ +- unsigned prt_sleep_sts:1; +- /** Sleep State Resume OK (L1ResumeOK) (Device and Host) +- * Indicates that the application or host +- * can start resume from Sleep state. +- */ +- unsigned sleep_state_resumeok:1; +- /** LPM channel Index (LPM_Chnl_Indx) (Host) +- * The channel number on which the LPM transaction +- * has to be applied while sending +- * an LPM transaction to the local device. +- */ +- unsigned lpm_chan_index:4; +- /** LPM Retry Count (LPM_Retry_Cnt) (Host) +- * Number host retries that would be performed +- * if the device response was not valid response. +- */ +- unsigned retry_count:3; +- /** Send LPM Transaction (SndLPM) (Host) +- * When set by application software, +- * an LPM transaction containing two tokens +- * is sent. +- */ +- unsigned send_lpm:1; +- /** LPM Retry status (LPM_RetryCnt_Sts) (Host) +- * Number of LPM Host Retries still remaining +- * to be transmitted for the current LPM sequence +- */ +- unsigned retry_count_sts:3; +- unsigned reserved28_29:2; +- /** In host mode once this bit is set, the host +- * configures to drive the HSIC Idle state on the bus. +- * It then waits for the device to initiate the Connect sequence. +- * In device mode once this bit is set, the device waits for +- * the HSIC Idle line state on the bus. Upon receving the Idle +- * line state, it initiates the HSIC Connect sequence. +- */ +- unsigned hsic_connect:1; +- /** This bit overrides and functionally inverts +- * the if_select_hsic input port signal. +- */ +- unsigned inv_sel_hsic:1; +- } b; +-} glpmcfg_data_t; +- +-/** + * This union represents the bit fields of the Core Reset Register + * (GRSTCTL). Set/clear the bits using the bit fields then write the + * d32 value to the register. +@@ -434,7 +353,7 @@ + */ + unsigned hsftrst:1; + /** Host Frame Counter Reset (Host Only)
                                                                                +- * ++ * + * The application can reset the (micro)frame number + * counter inside the core, using this bit. When the + * (micro)frame counter is reset, the subsequent SOF +@@ -449,27 +368,27 @@ + /** RxFIFO Flush (RxFFlsh) (Device and Host) + * + * The application can flush the entire Receive FIFO +- * using this bit.

                                                                                The application must first ++ * using this bit. The application must first + * ensure that the core is not in the middle of a +- * transaction.

                                                                                The application should write into ++ * transaction. The application should write into + * this bit, only after making sure that neither the + * DMA engine is reading from the RxFIFO nor the MAC +- * is writing the data in to the FIFO.

                                                                                The ++ * is writing the data in to the FIFO. The + * application should wait until the bit is cleared + * before performing any other operations. This bit + * will takes 8 clocks (slowest of PHY or AHB clock) + * to clear. + */ + unsigned rxfflsh:1; +- /** TxFIFO Flush (TxFFlsh) (Device and Host). ++ /** TxFIFO Flush (TxFFlsh) (Device and Host). + * + * This bit is used to selectively flush a single or +- * all transmit FIFOs. The application must first ++ * all transmit FIFOs. The application must first + * ensure that the core is not in the middle of a +- * transaction.

                                                                                The application should write into ++ * transaction. The application should write into + * this bit, only after making sure that neither the + * DMA engine is writing into the TxFIFO nor the MAC +- * is reading the data out of the FIFO.

                                                                                The ++ * is reading the data out of the FIFO. The + * application should wait until the core clears this + * bit, before performing any operations. This bit + * will takes 8 clocks (slowest of PHY or AHB clock) +@@ -478,7 +397,7 @@ + unsigned txfflsh:1; + + /** TxFIFO Number (TxFNum) (Device and Host). +- * ++ * + * This is the FIFO number which needs to be flushed, + * using the TxFIFO Flush bit. This field should not + * be changed until the TxFIFO Flush bit is cleared by +@@ -496,7 +415,7 @@ + /** Reserved */ + unsigned reserved11_29:19; + /** DMA Request Signal. Indicated DMA request is in +- * probress. Used for debug purpose. */ ++ * probress. Used for debug purpose. */ + unsigned dmareq:1; + /** AHB Master Idle. Indicates the AHB Master State + * Machine is in IDLE condition. */ +@@ -506,7 +425,7 @@ + + /** + * This union represents the bit fields of the Core Interrupt Mask +- * Register (GINTMSK). Set/clear the bits using the bit fields then ++ * Register (GINTMSK). Set/clear the bits using the bit fields then + * write the d32 value to the register. + */ + typedef union gintmsk_data { +@@ -522,7 +441,7 @@ + unsigned nptxfempty:1; + unsigned ginnakeff:1; + unsigned goutnakeff:1; +- unsigned reserved8:1; ++ unsigned ulpickint:1; + unsigned i2cintr:1; + unsigned erlysuspend:1; + unsigned usbsuspend:1; +@@ -530,13 +449,14 @@ + unsigned enumdone:1; + unsigned isooutdrop:1; + unsigned eopframe:1; +- unsigned reserved16:1; ++ unsigned restoredone:1; + unsigned epmismatch:1; + unsigned inepintr:1; + unsigned outepintr:1; + unsigned incomplisoin:1; + unsigned incomplisoout:1; +- unsigned reserved22_23:2; ++ unsigned fetsusp:1; ++ unsigned resetdet:1; + unsigned portintr:1; + unsigned hcintr:1; + unsigned ptxfempty:1; +@@ -567,7 +487,7 @@ + unsigned nptxfempty:1; + unsigned ginnakeff:1; + unsigned goutnakeff:1; +- unsigned reserved8:1; ++ unsigned ulpickint:1; + unsigned i2cintr:1; + unsigned erlysuspend:1; + unsigned usbsuspend:1; +@@ -575,13 +495,14 @@ + unsigned enumdone:1; + unsigned isooutdrop:1; + unsigned eopframe:1; +- unsigned intokenrx:1; ++ unsigned restoredone:1; + unsigned epmismatch:1; + unsigned inepint:1; + unsigned outepintr:1; + unsigned incomplisoin:1; + unsigned incomplisoout:1; +- unsigned reserved22_23:2; ++ unsigned fetsusp:1; ++ unsigned resetdet:1; + unsigned portintr:1; + unsigned hcintr:1; + unsigned ptxfempty:1; +@@ -594,8 +515,8 @@ + } gintsts_data_t; + + /** +- * This union represents the bit fields in the Device Receive Status Read and +- * Pop Registers (GRXSTSR, GRXSTSP) Read the register into the d32 ++ * This union represents the bit fields in the Device Receive Status Read and ++ * Pop Registers (GRXSTSR, GRXSTSP) Read the register into the d32 + * element then read out the bits using the bit elements. + */ + typedef union device_grxsts_data { +@@ -615,13 +536,13 @@ + #define DWC_DSTS_SETUP_UPDT 0x6 // SETUP Packet + unsigned pktsts:4; + unsigned fn:4; +- unsigned reserved:7; ++ unsigned reserved25_31:7; + } b; + } device_grxsts_data_t; + + /** +- * This union represents the bit fields in the Host Receive Status Read and +- * Pop Registers (GRXSTSR, GRXSTSP) Read the register into the d32 ++ * This union represents the bit fields in the Host Receive Status Read and ++ * Pop Registers (GRXSTSR, GRXSTSP) Read the register into the d32 + * element then read out the bits using the bit elements. + */ + typedef union host_grxsts_data { +@@ -639,14 +560,14 @@ + #define DWC_GRXSTS_PKTSTS_DATA_TOGGLE_ERR 0x5 + #define DWC_GRXSTS_PKTSTS_CH_HALTED 0x7 + +- unsigned reserved:11; ++ unsigned reserved21_31:11; + } b; + } host_grxsts_data_t; + + /** + * This union represents the bit fields in the FIFO Size Registers (HPTXFSIZ, +- * GNPTXFSIZ, DPTXFSIZn, DIEPTXFn). Read the register into the d32 element then +- * read out the bits using the bit elements. ++ * GNPTXFSIZ, DPTXFSIZn, DIEPTXFn). Read the register into the d32 element ++ * then read out the bits using the bit elements. + */ + typedef union fifosize_data { + /** raw register data */ +@@ -671,10 +592,10 @@ + struct { + unsigned nptxfspcavail:16; + unsigned nptxqspcavail:8; +- /** Top of the Non-Periodic Transmit Request Queue ++ /** Top of the Non-Periodic Transmit Request Queue + * - bit 24 - Terminate (Last entry for the selected + * channel/EP) +- * - bits 26:25 - Token Type ++ * - bits 26:25 - Token Type + * - 2'b00 - IN/OUT + * - 2'b01 - Zero Length OUT + * - 2'b10 - PING/Complete Split +@@ -721,13 +642,81 @@ + unsigned ack:1; + unsigned i2csuspctl:1; + unsigned i2cdevaddr:2; +- unsigned reserved:2; ++ unsigned i2cdatse0:1; ++ unsigned reserved:1; + unsigned rw:1; + unsigned bsydne:1; + } b; + } gi2cctl_data_t; + + /** ++ * This union represents the bit fields in the PHY Vendor Control Register ++ * (GPVNDCTL). Read the register into the d32 element then read out the ++ * bits using the bit elements. ++ */ ++typedef union gpvndctl_data { ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct { ++ unsigned regdata:8; ++ unsigned vctrl:8; ++ unsigned regaddr16_21:6; ++ unsigned regwr:1; ++ unsigned reserved23_24:2; ++ unsigned newregreq:1; ++ unsigned vstsbsy:1; ++ unsigned vstsdone:1; ++ unsigned reserved28_30:3; ++ unsigned disulpidrvr:1; ++ } b; ++} gpvndctl_data_t; ++ ++/** ++ * This union represents the bit fields in the General Purpose ++ * Input/Output Register (GGPIO). ++ * Read the register into the d32 element then read out the ++ * bits using the bit elements. ++ */ ++typedef union ggpio_data { ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct { ++ unsigned gpi:16; ++ unsigned gpo:16; ++ } b; ++} ggpio_data_t; ++ ++/** ++ * This union represents the bit fields in the User ID Register ++ * (GUID). Read the register into the d32 element then read out the ++ * bits using the bit elements. ++ */ ++typedef union guid_data { ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct { ++ unsigned rwdata:32; ++ } b; ++} guid_data_t; ++ ++/** ++ * This union represents the bit fields in the Synopsys ID Register ++ * (GSNPSID). Read the register into the d32 element then read out the ++ * bits using the bit elements. ++ */ ++typedef union gsnpsid_data { ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct { ++ unsigned rwdata:32; ++ } b; ++} gsnpsid_data_t; ++ ++/** + * This union represents the bit fields in the User HW Config1 + * Register. Read the register into the d32 element then read + * out the bits using the bit elements. +@@ -794,7 +783,7 @@ + unsigned nonperio_tx_q_depth:2; + unsigned host_perio_tx_q_depth:2; + unsigned dev_token_q_depth:5; +- unsigned reserved31:1; ++ unsigned otg_enable_ic_usb:1; + } b; + } hwcfg2_data_t; + +@@ -816,9 +805,9 @@ + unsigned vendor_ctrl_if:1; + unsigned optional_features:1; + unsigned synch_reset_type:1; +- unsigned otg_enable_ic_usb:1; ++ unsigned adp_supp:1; + unsigned otg_enable_hsic:1; +- unsigned reserved14:1; ++ unsigned bc_support:1; + unsigned otg_lpm_en:1; + unsigned dfifo_depth:16; + } b; +@@ -836,7 +825,9 @@ + struct { + unsigned num_dev_perio_in_ep:4; + unsigned power_optimiz:1; +- unsigned min_ahb_freq:9; ++ unsigned min_ahb_freq:1; ++ unsigned part_power_down:1; ++ unsigned reserved:7; + unsigned utmi_phy_data_width:2; + unsigned num_dev_mode_ctrl_ep:4; + unsigned iddig_filt_en:1; +@@ -851,6 +842,229 @@ + } b; + } hwcfg4_data_t; + ++/** ++ * This union represents the bit fields of the Core LPM Configuration ++ * Register (GLPMCFG). Set the bits using bit fields then write ++ * the d32 value to the register. ++ */ ++typedef union glpmctl_data { ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct { ++ /** LPM-Capable (LPMCap) (Device and Host) ++ * The application uses this bit to control ++ * the DWC_otg core LPM capabilities. ++ */ ++ unsigned lpm_cap_en:1; ++ /** LPM response programmed by application (AppL1Res) (Device) ++ * Handshake response to LPM token pre-programmed ++ * by device application software. ++ */ ++ unsigned appl_resp:1; ++ /** Host Initiated Resume Duration (HIRD) (Device and Host) ++ * In Host mode this field indicates the value of HIRD ++ * to be sent in an LPM transaction. ++ * In Device mode this field is updated with the ++ * Received LPM Token HIRD bmAttribute ++ * when an ACK/NYET/STALL response is sent ++ * to an LPM transaction. ++ */ ++ unsigned hird:4; ++ /** RemoteWakeEnable (bRemoteWake) (Device and Host) ++ * In Host mode this bit indicates the value of remote ++ * wake up to be sent in wIndex field of LPM transaction. ++ * In Device mode this field is updated with the ++ * Received LPM Token bRemoteWake bmAttribute ++ * when an ACK/NYET/STALL response is sent ++ * to an LPM transaction. ++ */ ++ unsigned rem_wkup_en:1; ++ /** Enable utmi_sleep_n (EnblSlpM) (Device and Host) ++ * The application uses this bit to control ++ * the utmi_sleep_n assertion to the PHY when in L1 state. ++ */ ++ unsigned en_utmi_sleep:1; ++ /** HIRD Threshold (HIRD_Thres) (Device and Host) ++ */ ++ unsigned hird_thres:5; ++ /** LPM Response (CoreL1Res) (Device and Host) ++ * In Host mode this bit contains handsake response to ++ * LPM transaction. ++ * In Device mode the response of the core to ++ * LPM transaction received is reflected in these two bits. ++ - 0x0 : ERROR (No handshake response) ++ - 0x1 : STALL ++ - 0x2 : NYET ++ - 0x3 : ACK ++ */ ++ unsigned lpm_resp:2; ++ /** Port Sleep Status (SlpSts) (Device and Host) ++ * This bit is set as long as a Sleep condition ++ * is present on the USB bus. ++ */ ++ unsigned prt_sleep_sts:1; ++ /** Sleep State Resume OK (L1ResumeOK) (Device and Host) ++ * Indicates that the application or host ++ * can start resume from Sleep state. ++ */ ++ unsigned sleep_state_resumeok:1; ++ /** LPM channel Index (LPM_Chnl_Indx) (Host) ++ * The channel number on which the LPM transaction ++ * has to be applied while sending ++ * an LPM transaction to the local device. ++ */ ++ unsigned lpm_chan_index:4; ++ /** LPM Retry Count (LPM_Retry_Cnt) (Host) ++ * Number host retries that would be performed ++ * if the device response was not valid response. ++ */ ++ unsigned retry_count:3; ++ /** Send LPM Transaction (SndLPM) (Host) ++ * When set by application software, ++ * an LPM transaction containing two tokens ++ * is sent. ++ */ ++ unsigned send_lpm:1; ++ /** LPM Retry status (LPM_RetryCnt_Sts) (Host) ++ * Number of LPM Host Retries still remaining ++ * to be transmitted for the current LPM sequence ++ */ ++ unsigned retry_count_sts:3; ++ unsigned reserved28_29:2; ++ /** In host mode once this bit is set, the host ++ * configures to drive the HSIC Idle state on the bus. ++ * It then waits for the device to initiate the Connect sequence. ++ * In device mode once this bit is set, the device waits for ++ * the HSIC Idle line state on the bus. Upon receving the Idle ++ * line state, it initiates the HSIC Connect sequence. ++ */ ++ unsigned hsic_connect:1; ++ /** This bit overrides and functionally inverts ++ * the if_select_hsic input port signal. ++ */ ++ unsigned inv_sel_hsic:1; ++ } b; ++} glpmcfg_data_t; ++ ++/** ++ * This union represents the bit fields of the Core ADP Timer, Control and ++ * Status Register (ADPTIMCTLSTS). Set the bits using bit fields then write ++ * the d32 value to the register. ++ */ ++typedef union adpctl_data { ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct { ++ /** Probe Discharge (PRB_DSCHG) ++ * These bits set the times for TADP_DSCHG. ++ * These bits are defined as follows: ++ * 2'b00 - 4 msec ++ * 2'b01 - 8 msec ++ * 2'b10 - 16 msec ++ * 2'b11 - 32 msec ++ */ ++ unsigned prb_dschg:2; ++ /** Probe Delta (PRB_DELTA) ++ * These bits set the resolution for RTIM value. ++ * The bits are defined in units of 32 kHz clock cycles as follows: ++ * 2'b00 - 1 cycles ++ * 2'b01 - 2 cycles ++ * 2'b10 - 3 cycles ++ * 2'b11 - 4 cycles ++ * For example if this value is chosen to 2'b01, it means that RTIM ++ * increments for every 3(three) 32Khz clock cycles. ++ */ ++ unsigned prb_delta:2; ++ /** Probe Period (PRB_PER) ++ * These bits sets the TADP_PRD as shown in Figure 4 as follows: ++ * 2'b00 - 0.625 to 0.925 sec (typical 0.775 sec) ++ * 2'b01 - 1.25 to 1.85 sec (typical 1.55 sec) ++ * 2'b10 - 1.9 to 2.6 sec (typical 2.275 sec) ++ * 2'b11 - Reserved ++ */ ++ unsigned prb_per:2; ++ /** These bits capture the latest time it took for VBUS to ramp from ++ * VADP_SINK to VADP_PRB. ++ * 0x000 - 1 cycles ++ * 0x001 - 2 cycles ++ * 0x002 - 3 cycles ++ * etc ++ * 0x7FF - 2048 cycles ++ * A time of 1024 cycles at 32 kHz corresponds to a time of 32 msec. ++ */ ++ unsigned rtim:11; ++ /** Enable Probe (EnaPrb) ++ * When programmed to 1'b1, the core performs a probe operation. ++ * This bit is valid only if OTG_Ver = 1'b1. ++ */ ++ unsigned enaprb:1; ++ /** Enable Sense (EnaSns) ++ * When programmed to 1'b1, the core performs a Sense operation. ++ * This bit is valid only if OTG_Ver = 1'b1. ++ */ ++ unsigned enasns:1; ++ /** ADP Reset (ADPRes) ++ * When set, ADP controller is reset. ++ * This bit is valid only if OTG_Ver = 1'b1. ++ */ ++ unsigned adpres:1; ++ /** ADP Enable (ADPEn) ++ * When set, the core performs either ADP probing or sensing ++ * based on EnaPrb or EnaSns. ++ * This bit is valid only if OTG_Ver = 1'b1. ++ */ ++ unsigned adpen:1; ++ /** ADP Probe Interrupt (ADP_PRB_INT) ++ * When this bit is set, it means that the VBUS ++ * voltage is greater than VADP_PRB or VADP_PRB is reached. ++ * This bit is valid only if OTG_Ver = 1'b1. ++ */ ++ unsigned adp_prb_int:1; ++ /** ++ * ADP Sense Interrupt (ADP_SNS_INT) ++ * When this bit is set, it means that the VBUS voltage is greater than ++ * VADP_SNS value or VADP_SNS is reached. ++ * This bit is valid only if OTG_Ver = 1'b1. ++ */ ++ unsigned adp_sns_int:1; ++ /** ADP Tomeout Interrupt (ADP_TMOUT_INT) ++ * This bit is relevant only for an ADP probe. ++ * When this bit is set, it means that the ramp time has ++ * completed ie ADPCTL.RTIM has reached its terminal value ++ * of 0x7FF. This is a debug feature that allows software ++ * to read the ramp time after each cycle. ++ * This bit is valid only if OTG_Ver = 1'b1. ++ */ ++ unsigned adp_tmout_int:1; ++ /** ADP Probe Interrupt Mask (ADP_PRB_INT_MSK) ++ * When this bit is set, it unmasks the interrupt due to ADP_PRB_INT. ++ * This bit is valid only if OTG_Ver = 1'b1. ++ */ ++ unsigned adp_prb_int_msk:1; ++ /** ADP Sense Interrupt Mask (ADP_SNS_INT_MSK) ++ * When this bit is set, it unmasks the interrupt due to ADP_SNS_INT. ++ * This bit is valid only if OTG_Ver = 1'b1. ++ */ ++ unsigned adp_sns_int_msk:1; ++ /** ADP Timoeout Interrupt Mask (ADP_TMOUT_MSK) ++ * When this bit is set, it unmasks the interrupt due to ADP_TMOUT_INT. ++ * This bit is valid only if OTG_Ver = 1'b1. ++ */ ++ unsigned adp_tmout_int_msk:1; ++ /** Access Request ++ * 2'b00 - Read/Write Valid (updated by the core) ++ * 2'b01 - Read ++ * 2'b00 - Write ++ * 2'b00 - Reserved ++ */ ++ unsigned ar:2; ++ /** Reserved */ ++ unsigned reserved29_31:3; ++ } b; ++} adpctl_data_t; ++ + //////////////////////////////////////////// + // Device Registers + /** +@@ -931,7 +1145,7 @@ + unsigned nzstsouthshk:1; + #define DWC_DCFG_SEND_STALL 1 + +- unsigned reserved3:1; ++ unsigned ena32khzs:1; + /** Device Addresses */ + unsigned devaddr:7; + /** Periodic Frame Interval */ +@@ -940,12 +1154,17 @@ + #define DWC_DCFG_FRAME_INTERVAL_85 1 + #define DWC_DCFG_FRAME_INTERVAL_90 2 + #define DWC_DCFG_FRAME_INTERVAL_95 3 ++ ++ /** Enable Device OUT NAK for bulk in DDMA mode */ ++ unsigned endevoutnak:1; + +- unsigned reserved13_17:5; ++ unsigned reserved14_17:4; + /** In Endpoint Mis-match count */ + unsigned epmscnt:5; + /** Enable Descriptor DMA in Device mode */ + unsigned descdma:1; ++ unsigned perschintvl:2; ++ unsigned resvalid:6; + } b; + } dcfg_data_t; + +@@ -977,19 +1196,20 @@ + unsigned sgoutnak:1; + /** Clear Global OUT NAK */ + unsigned cgoutnak:1; +- + /** Power-On Programming Done */ + unsigned pwronprgdone:1; +- /** Global Continue on BNA */ +- unsigned gcontbna:1; ++ /** Reserved */ ++ unsigned reserved:1; + /** Global Multi Count */ + unsigned gmc:2; + /** Ignore Frame Number for ISOC EPs */ + unsigned ifrmnum:1; + /** NAK on Babble */ + unsigned nakonbble:1; ++ /** Enable Continue on BNA */ ++ unsigned encontonbna:1; + +- unsigned reserved17_31:15; ++ unsigned reserved18_31:14; + } b; + } dctl_data_t; + +@@ -1044,9 +1264,9 @@ + unsigned intktxfemp:1; + /** IN Token Received with EP mismatch mask */ + unsigned intknepmis:1; +- /** IN Endpoint HAK Effective mask */ ++ /** IN Endpoint NAK Effective mask */ + unsigned inepnakeff:1; +- /** IN Endpoint HAK Effective mask */ ++ /** Reserved */ + unsigned emptyintr:1; + + unsigned txfifoundrn:1; +@@ -1063,7 +1283,7 @@ + } diepint_data_t; + + /** +- * This union represents the bit fields in the Device IN EP ++ * This union represents the bit fields in the Device IN EP + * Common/Dedicated Interrupt Mask Register. + */ + typedef union diepint_data diepmsk_data_t; +@@ -1116,7 +1336,7 @@ + } doepint_data_t; + + /** +- * This union represents the bit fields in the Device OUT EP ++ * This union represents the bit fields in the Device OUT EP + * Common/Dedicated Interrupt Mask Register. + */ + typedef union doepint_data doepmsk_data_t; +@@ -1221,8 +1441,11 @@ + unsigned rx_thr_en:1; + /** Rx Thr. Length */ + unsigned rx_thr_len:9; ++ unsigned reserved26:1; ++ /** Arbiter Parking Enable*/ ++ unsigned arbprken:1; + /** Reserved */ +- unsigned reserved26_31:6; ++ unsigned reserved28_31:4; + } b; + } dthrctl_data_t; + +@@ -1275,9 +1498,8 @@ + /** Device OUT Endpoint Control Register. Offset:B00h + + * (ep_num * 20h) + 00h */ + volatile uint32_t doepctl; +- /** Device OUT Endpoint Frame number Register. Offset: +- * B00h + (ep_num * 20h) + 04h */ +- volatile uint32_t doepfn; ++ /** Reserved. Offset:B00h + (ep_num * 20h) + 04h */ ++ uint32_t reserved04; + /** Device OUT Endpoint Interrupt Register. Offset:B00h + + * (ep_num * 20h) + 08h */ + volatile uint32_t doepint; +@@ -1306,7 +1528,7 @@ + uint32_t d32; + /** register bits */ + struct { +- /** Maximum Packet Size ++ /** Maximum Packet Size + * IN/OUT EPn + * IN/OUT EP0 - 2 bits + * 2'b00: 64 Bytes +@@ -1319,8 +1541,8 @@ + #define DWC_DEP0CTL_MPS_16 2 + #define DWC_DEP0CTL_MPS_8 3 + +- /** Next Endpoint +- * IN EPn/IN EP0 ++ /** Next Endpoint ++ * IN EPn/IN EP0 + * OUT EPn/OUT EP0 - reserved */ + unsigned nextep:4; + +@@ -1336,7 +1558,7 @@ + * activated. Application use the SetD1PID and + * SetD0PID fields of this register to program either + * D0 or D1 PID. +- * ++ * + * The encoding for this field is + * - 0: D0 + * - 1: D1 +@@ -1346,14 +1568,14 @@ + /** NAK Status */ + unsigned naksts:1; + +- /** Endpoint Type ++ /** Endpoint Type + * 2'b00: Control + * 2'b01: Isochronous + * 2'b10: Bulk + * 2'b11: Interrupt */ + unsigned eptype:2; + +- /** Snoop Mode ++ /** Snoop Mode + * OUT EPn/OUT EP0 + * IN EPn/IN EP0 - reserved */ + unsigned snp:1; +@@ -1361,7 +1583,7 @@ + /** Stall Handshake */ + unsigned stall:1; + +- /** Tx Fifo Number ++ /** Tx Fifo Number + * IN EPn/IN EP0 + * OUT EPn/OUT EP0 - reserved */ + unsigned txfnum:4; +@@ -1407,6 +1629,8 @@ + struct { + /** Transfer size */ + unsigned xfersize:19; ++/** Max packet count for EP (pow(2,10)-1) */ ++#define MAX_PKT_CNT 1023 + /** Packet Count */ + unsigned pktcnt:10; + /** Multi Count - Periodic IN endpoints */ +@@ -1430,9 +1654,9 @@ + /** Reserved */ + unsigned reserved7_18:12; + /** Packet Count */ +- unsigned pktcnt:1; ++ unsigned pktcnt:2; + /** Reserved */ +- unsigned reserved20_28:9; ++ unsigned reserved21_28:8; + /**Setup Packet Count (DOEPTSIZ0 Only) */ + unsigned supcnt:2; + unsigned reserved31; +@@ -1460,7 +1684,7 @@ + /** + * This union represents the bit fields in the DMA Descriptor + * status quadlet. Read the quadlet into the d32 member then +- * set/clear the bits using the bit, b_iso_out and ++ * set/clear the bits using the bit, b_iso_out and + * b_iso_in elements. + */ + typedef union dev_dma_desc_sts { +@@ -1470,8 +1694,9 @@ + struct { + /** Received number of bytes */ + unsigned bytes:16; +- +- unsigned reserved16_22:7; ++ /** NAK bit - only for OUT EPs */ ++ unsigned nak:1; ++ unsigned reserved17_22:6; + /** Multiple Transfer - only for OUT EPs */ + unsigned mtrf:1; + /** Setup Packet received - only for OUT EPs */ +@@ -1488,7 +1713,7 @@ + unsigned bs:2; + } b; + +-#ifdef DWC_EN_ISOC ++//#ifdef DWC_EN_ISOC + /** iso out quadlet bits */ + struct { + /** Received number of bytes */ +@@ -1530,11 +1755,11 @@ + /** Buffer Status */ + unsigned bs:2; + } b_iso_in; +-#endif /* DWC_EN_ISOC */ ++//#endif /* DWC_EN_ISOC */ + } dev_dma_desc_sts_t; + +-/** +- * DMA Descriptor structure ++/** ++ * DMA Descriptor structure + * + * DMA Descriptor structure contains two quadlets: + * Status quadlet and Data buffer pointer. +@@ -1558,8 +1783,8 @@ + dwc_otg_device_global_regs_t *dev_global_regs; + #define DWC_DEV_GLOBAL_REG_OFFSET 0x800 + +- /** +- * Device Logical IN Endpoint-Specific Registers 900h-AFCh ++ /** ++ * Device Logical IN Endpoint-Specific Registers 900h-AFCh + */ + dwc_otg_dev_in_ep_regs_t *in_ep_regs[MAX_EPS_CHANNELS]; + #define DWC_DEV_IN_EP_REG_OFFSET 0x900 +@@ -1613,6 +1838,8 @@ + + /** Setup Packet Detected - if set clear NAK when queueing */ + uint32_t spd; ++ /** Isoc ep pointer on which incomplete happens */ ++ void *isoc_ep; + + } dwc_otg_dev_if_t; + +@@ -1643,20 +1870,17 @@ + volatile uint32_t hflbaddr; + } dwc_otg_host_global_regs_t; + +- + /** + * This union represents the bit fields in the Host Configuration Register. + * Read the register into the d32 member then set/clear the bits using + * the bit elements. Write the d32 member to the hcfg register. + */ +-typedef union hcfg_data +-{ ++typedef union hcfg_data { + /** raw register data */ + uint32_t d32; + + /** register bits */ +- struct +- { ++ struct { + /** FS/LS Phy Clock Select */ + unsigned fslspclksel:2; + #define DWC_HCFG_30_60_MHZ 0 +@@ -1665,21 +1889,26 @@ + + /** FS/LS Only Support */ + unsigned fslssupp:1; +- unsigned reserved3_22 : 20; ++ unsigned reserved3_6:4; ++ /** Enable 32-KHz Suspend Mode */ ++ unsigned ena32khzs:1; ++ /** Resume Validation Periiod */ ++ unsigned resvalid:8; ++ unsigned reserved16_22:7; + /** Enable Scatter/gather DMA in Host mode */ +- unsigned descdma : 1; ++ unsigned descdma:1; + /** Frame List Entries */ +- unsigned frlisten: 2; ++ unsigned frlisten:2; + /** Enable Periodic Scheduling */ +- unsigned perschedena: 1; +- /** Periodic Scheduling Enabled Status */ +- unsigned perschedstat: 1; ++ unsigned perschedena:1; ++ unsigned reserved27_30:4; ++ unsigned modechtimen:1; + } b; + } hcfg_data_t; + + /** + * This union represents the bit fields in the Host Frame Remaing/Number +- * Register. ++ * Register. + */ + typedef union hfir_data { + /** raw register data */ +@@ -1688,13 +1917,14 @@ + /** register bits */ + struct { + unsigned frint:16; +- unsigned reserved:16; ++ unsigned hfirrldctrl:1; ++ unsigned reserved:15; + } b; + } hfir_data_t; + + /** + * This union represents the bit fields in the Host Frame Remaing/Number +- * Register. ++ * Register. + */ + typedef union hfnum_data { + /** raw register data */ +@@ -1765,8 +1995,8 @@ + } hprt0_data_t; + + /** +- * This union represents the bit fields in the Host All Interrupt +- * Register. ++ * This union represents the bit fields in the Host All Interrupt ++ * Register. + */ + typedef union haint_data { + /** raw register data */ +@@ -1799,8 +2029,8 @@ + } haint_data_t; + + /** +- * This union represents the bit fields in the Host All Interrupt +- * Register. ++ * This union represents the bit fields in the Host All Interrupt ++ * Register. + */ + typedef union haintmsk_data { + /** raw register data */ +@@ -1832,11 +2062,10 @@ + } b2; + } haintmsk_data_t; + +-/** ++/** + * Host Channel Specific Registers. 500h-5FCh + */ +-typedef struct dwc_otg_hc_regs +-{ ++typedef struct dwc_otg_hc_regs { + /** Host Channel 0 Characteristic Register. Offset: 500h + (chan_num * 20h) + 00h */ + volatile uint32_t hcchar; + /** Host Channel 0 Split Control Register. Offset: 500h + (chan_num * 20h) + 04h */ +@@ -1934,16 +2163,14 @@ + } hcsplt_data_t; + + /** +- * This union represents the bit fields in the Host All Interrupt +- * Register. ++ * This union represents the bit fields in the Host All Interrupt ++ * Register. + */ +-typedef union hcint_data +-{ ++typedef union hcint_data { + /** raw register data */ + uint32_t d32; + /** register bits */ +- struct +- { ++ struct { + /** Transfer Complete */ + unsigned xfercomp:1; + /** Channel Halted */ +@@ -1967,13 +2194,13 @@ + /** Data Toggle Error */ + unsigned datatglerr:1; + /** Buffer Not Available (only for DDMA mode) */ +- unsigned bna : 1; ++ unsigned bna:1; + /** Exessive transaction error (only for DDMA mode) */ +- unsigned xcs_xact : 1; ++ unsigned xcs_xact:1; + /** Frame List Rollover interrupt */ +- unsigned frm_list_roll : 1; ++ unsigned frm_list_roll:1; + /** Reserved */ +- unsigned reserved14_31 : 18; ++ unsigned reserved14_31:18; + } b; + } hcint_data_t; + +@@ -1983,29 +2210,27 @@ + * bits using the bit elements. Write the d32 member to the + * hcintmsk register. + */ +-typedef union hcintmsk_data +-{ ++typedef union hcintmsk_data { + /** raw register data */ + uint32_t d32; + + /** register bits */ +- struct +- { +- unsigned xfercompl : 1; +- unsigned chhltd : 1; +- unsigned ahberr : 1; +- unsigned stall : 1; +- unsigned nak : 1; +- unsigned ack : 1; +- unsigned nyet : 1; +- unsigned xacterr : 1; +- unsigned bblerr : 1; +- unsigned frmovrun : 1; +- unsigned datatglerr : 1; +- unsigned bna : 1; +- unsigned xcs_xact : 1; +- unsigned frm_list_roll : 1; +- unsigned reserved14_31 : 18; ++ struct { ++ unsigned xfercompl:1; ++ unsigned chhltd:1; ++ unsigned ahberr:1; ++ unsigned stall:1; ++ unsigned nak:1; ++ unsigned ack:1; ++ unsigned nyet:1; ++ unsigned xacterr:1; ++ unsigned bblerr:1; ++ unsigned frmovrun:1; ++ unsigned datatglerr:1; ++ unsigned bna:1; ++ unsigned xcs_xact:1; ++ unsigned frm_list_roll:1; ++ unsigned reserved14_31:18; + } b; + } hcintmsk_data_t; + +@@ -2016,14 +2241,12 @@ + * hcchar register. + */ + +-typedef union hctsiz_data +-{ ++typedef union hctsiz_data { + /** raw register data */ + uint32_t d32; + + /** register bits */ +- struct +- { ++ struct { + /** Total transfer size in bytes */ + unsigned xfersize:19; + +@@ -2047,22 +2270,21 @@ + /** Do PING protocol when 1 */ + unsigned dopng:1; + } b; +- ++ + /** register bits */ +- struct +- { ++ struct { + /** Scheduling information */ +- unsigned schinfo : 8; +- +- /** Number of transfer descriptors. ++ unsigned schinfo:8; ++ ++ /** Number of transfer descriptors. + * Max value: +- * 64 in general, ++ * 64 in general, + * 256 only for HS isochronous endpoint. + */ +- unsigned ntd : 8; ++ unsigned ntd:8; + + /** Data packets to transfer */ +- unsigned reserved16_28 : 13; ++ unsigned reserved16_28:13; + + /** + * Packet ID for next data packet +@@ -2071,30 +2293,27 @@ + * 2: DATA1 + * 3: MDATA (non-Control) + */ +- unsigned pid : 2; ++ unsigned pid:2; + + /** Do PING protocol when 1 */ +- unsigned dopng : 1; ++ unsigned dopng:1; + } b_ddma; + } hctsiz_data_t; + +- + /** +- * This union represents the bit fields in the Host DMA Address ++ * This union represents the bit fields in the Host DMA Address + * Register used in Descriptor DMA mode. + */ +-typedef union hcdma_data +-{ ++typedef union hcdma_data { + /** raw register data */ + uint32_t d32; + /** register bits */ +- struct +- { +- unsigned reserved0_2 : 3; ++ struct { ++ unsigned reserved0_2:3; + /** Current Transfer Descriptor. Not used for ISOC */ +- unsigned ctd : 8; ++ unsigned ctd:8; + /** Start Address of Descriptor List */ +- unsigned dma_addr : 21; ++ unsigned dma_addr:21; + } b; + } hcdma_data_t; + +@@ -2103,8 +2322,7 @@ + * status quadlet for host mode. Read the quadlet into the d32 member then + * set/clear the bits using the bit elements. + */ +-typedef union host_dma_desc_sts +-{ ++typedef union host_dma_desc_sts { + /** raw register data */ + uint32_t d32; + /** quadlet bits */ +@@ -2112,44 +2330,44 @@ + /* for non-isochronous */ + struct { + /** Number of bytes */ +- unsigned n_bytes : 17; ++ unsigned n_bytes:17; + /** QTD offset to jump when Short Packet received - only for IN EPs */ +- unsigned qtd_offset : 6; +- /** +- * Set to request the core to jump to alternate QTD if +- * Short Packet received - only for IN EPs ++ unsigned qtd_offset:6; ++ /** ++ * Set to request the core to jump to alternate QTD if ++ * Short Packet received - only for IN EPs + */ +- unsigned a_qtd : 1; +- /** ++ unsigned a_qtd:1; ++ /** + * Setup Packet bit. When set indicates that buffer contains +- * setup packet. ++ * setup packet. + */ +- unsigned sup : 1; ++ unsigned sup:1; + /** Interrupt On Complete */ +- unsigned ioc : 1; ++ unsigned ioc:1; + /** End of List */ +- unsigned eol : 1; +- unsigned reserved27 : 1; ++ unsigned eol:1; ++ unsigned reserved27:1; + /** Rx/Tx Status */ +- unsigned sts : 2; +- #define DMA_DESC_STS_PKTERR 1 +- unsigned reserved30 : 1; ++ unsigned sts:2; ++#define DMA_DESC_STS_PKTERR 1 ++ unsigned reserved30:1; + /** Active Bit */ +- unsigned a : 1; ++ unsigned a:1; + } b; + /* for isochronous */ + struct { + /** Number of bytes */ +- unsigned n_bytes : 12; +- unsigned reserved12_24 : 13; ++ unsigned n_bytes:12; ++ unsigned reserved12_24:13; + /** Interrupt On Complete */ +- unsigned ioc : 1; +- unsigned reserved26_27 : 2; ++ unsigned ioc:1; ++ unsigned reserved26_27:2; + /** Rx/Tx Status */ +- unsigned sts : 2; +- unsigned reserved30 : 1; ++ unsigned sts:2; ++ unsigned reserved30:1; + /** Active Bit */ +- unsigned a : 1; ++ unsigned a:1; + } b_isoc; + } host_dma_desc_sts_t; + +@@ -2157,18 +2375,17 @@ + #define MAX_DMA_DESC_NUM_GENERIC 64 + #define MAX_DMA_DESC_NUM_HS_ISOC 256 + #define MAX_FRLIST_EN_NUM 64 +-/** +- * Host-mode DMA Descriptor structure ++/** ++ * Host-mode DMA Descriptor structure + * + * DMA Descriptor structure contains two quadlets: + * Status quadlet and Data buffer pointer. + */ +-typedef struct dwc_otg_host_dma_desc +-{ ++typedef struct dwc_otg_host_dma_desc { + /** DMA Descriptor status quadlet */ +- host_dma_desc_sts_t status; ++ host_dma_desc_sts_t status; + /** DMA Descriptor data buffer pointer */ +- uint32_t buf; ++ uint32_t buf; + } dwc_otg_host_dma_desc_t; + + /** OTG Host Interface Structure. +@@ -2205,7 +2422,7 @@ + /** + * This union represents the bit fields in the Power and Clock Gating Control + * Register. Read the register into the d32 member then set/clear the +- * bits using the bit elements. ++ * bits using the bit elements. + */ + typedef union pcgcctl_data { + /** raw register data */ +@@ -2221,17 +2438,108 @@ + unsigned pwrclmp:1; + /** Reset Power Down Modules */ + unsigned rstpdwnmodule:1; +- /** PHY Suspended */ +- unsigned physuspended:1; ++ /** Reserved */ ++ unsigned reserved:1; + /** Enable Sleep Clock Gating (Enbl_L1Gating) */ + unsigned enbl_sleep_gating:1; + /** PHY In Sleep (PhySleep) */ + unsigned phy_in_sleep:1; + /** Deep Sleep*/ + unsigned deep_sleep:1; +- +- unsigned reserved31_8:24; ++ unsigned resetaftsusp:1; ++ unsigned restoremode:1; ++ unsigned reserved10_12:3; ++ unsigned ess_reg_restored:1; ++ unsigned prt_clk_sel:2; ++ unsigned port_power:1; ++ unsigned max_xcvrselect:2; ++ unsigned max_termsel:1; ++ unsigned mac_dev_addr:7; ++ unsigned p2hd_dev_enum_spd:2; ++ unsigned p2hd_prt_spd:2; ++ unsigned if_dev_mode:1; + } b; + } pcgcctl_data_t; + ++/** ++ * This union represents the bit fields in the Global Data FIFO Software ++ * Configuration Register. Read the register into the d32 member then ++ * set/clear the bits using the bit elements. ++ */ ++typedef union gdfifocfg_data { ++ /* raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct { ++ /** OTG Data FIFO depth */ ++ unsigned gdfifocfg:16; ++ /** Start address of EP info controller */ ++ unsigned epinfobase:16; ++ } b; ++} gdfifocfg_data_t; ++ ++/** ++ * This union represents the bit fields in the Global Power Down Register ++ * Register. Read the register into the d32 member then set/clear the ++ * bits using the bit elements. ++ */ ++typedef union gpwrdn_data { ++ /* raw register data */ ++ uint32_t d32; ++ ++ /** register bits */ ++ struct { ++ /** PMU Interrupt Select */ ++ unsigned pmuintsel:1; ++ /** PMU Active */ ++ unsigned pmuactv:1; ++ /** Restore */ ++ unsigned restore:1; ++ /** Power Down Clamp */ ++ unsigned pwrdnclmp:1; ++ /** Power Down Reset */ ++ unsigned pwrdnrstn:1; ++ /** Power Down Switch */ ++ unsigned pwrdnswtch:1; ++ /** Disable VBUS */ ++ unsigned dis_vbus:1; ++ /** Line State Change */ ++ unsigned lnstschng:1; ++ /** Line state change mask */ ++ unsigned lnstchng_msk:1; ++ /** Reset Detected */ ++ unsigned rst_det:1; ++ /** Reset Detect mask */ ++ unsigned rst_det_msk:1; ++ /** Disconnect Detected */ ++ unsigned disconn_det:1; ++ /** Disconnect Detect mask */ ++ unsigned disconn_det_msk:1; ++ /** Connect Detected*/ ++ unsigned connect_det:1; ++ /** Connect Detected Mask*/ ++ unsigned connect_det_msk:1; ++ /** SRP Detected */ ++ unsigned srp_det:1; ++ /** SRP Detect mask */ ++ unsigned srp_det_msk:1; ++ /** Status Change Interrupt */ ++ unsigned sts_chngint:1; ++ /** Status Change Interrupt Mask */ ++ unsigned sts_chngint_msk:1; ++ /** Line State */ ++ unsigned linestate:2; ++ /** Indicates current mode(status of IDDIG signal) */ ++ unsigned idsts:1; ++ /** B Session Valid signal status*/ ++ unsigned bsessvld:1; ++ /** ADP Event Detected */ ++ unsigned adp_int:1; ++ /** Multi Valued ID pin */ ++ unsigned mult_val_id_bc:5; ++ /** Reserved 24_31 */ ++ unsigned reserved29_31:3; ++ } b; ++} gpwrdn_data_t; ++ + #endif diff -Nru linux-3.2.46/debian/patches/rpi/rpi_214_5cc98c1e75700e51e4a31d8a05b4a55a7d29648c.patch linux-3.2.46/debian/patches/rpi/rpi_214_5cc98c1e75700e51e4a31d8a05b4a55a7d29648c.patch --- linux-3.2.46/debian/patches/rpi/rpi_214_5cc98c1e75700e51e4a31d8a05b4a55a7d29648c.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_214_5cc98c1e75700e51e4a31d8a05b4a55a7d29648c.patch 2013-07-26 19:35:17.000000000 +0000 @@ -0,0 +1,663 @@ +commit 5cc98c1e75700e51e4a31d8a05b4a55a7d29648c +Author: popcornmix +Date: Sun Aug 19 11:58:01 2012 +0100 + + Merged in microframe scheduler, currently disabled. Enable with dwc_otg.microframe_schedule=1 + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_driver.c +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/dwc_otg_driver.c 2013-07-26 19:34:44.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_driver.c 2013-07-26 19:35:16.000000000 +0000 +@@ -60,6 +60,8 @@ + #define DWC_DRIVER_VERSION "2.94b 27-OCT-2011 (rev 01-DEC-2011)" + #define DWC_DRIVER_DESC "HS OTG USB Controller driver" + ++bool microframe_schedule; ++ + static const char dwc_driver_name[] = "dwc_otg"; + + extern int pcd_init( +@@ -1337,6 +1339,8 @@ + MODULE_PARM_DESC(adp_enable, "ADP Enable 0=ADP Disabled 1=ADP Enabled"); + module_param_named(otg_ver, dwc_otg_module_params.otg_ver, int, 0444); + MODULE_PARM_DESC(otg_ver, "OTG revision supported 0=OTG 1.3 1=OTG 2.0"); ++module_param(microframe_schedule, bool, 0444); ++MODULE_PARM_DESC(microframe_schedule, "Enable the microframe scheduler"); + + /** @page "Module Parameters" + * +Index: linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_hcd.c +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/dwc_otg_hcd.c 2013-07-26 19:34:44.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_hcd.c 2013-07-26 19:35:16.000000000 +0000 +@@ -43,6 +43,16 @@ + #include "dwc_otg_hcd.h" + #include "dwc_otg_regs.h" + ++extern bool microframe_schedule; ++ ++//#define DEBUG_HOST_CHANNELS ++#ifdef DEBUG_HOST_CHANNELS ++static int last_sel_trans_num_per_scheduled = 0; ++static int last_sel_trans_num_nonper_scheduled = 0; ++static int last_sel_trans_num_avail_hc_at_start = 0; ++static int last_sel_trans_num_avail_hc_at_end = 0; ++#endif /* DEBUG_HOST_CHANNELS */ ++ + dwc_otg_hcd_t *dwc_otg_hcd_alloc_hcd(void) + { + return DWC_ALLOC(sizeof(dwc_otg_hcd_t)); +@@ -825,6 +835,8 @@ + DWC_FREE(dwc_otg_hcd); + } + ++int init_hcd_usecs(dwc_otg_hcd_t *_hcd); ++ + int dwc_otg_hcd_init(dwc_otg_hcd_t * hcd, dwc_otg_core_if_t * core_if) + { + int retval = 0; +@@ -888,6 +900,10 @@ + hcd->conn_timer = DWC_TIMER_ALLOC("Connection timer", + dwc_otg_hcd_connect_timeout, 0); + ++ printk(KERN_DEBUG "dwc_otg: Microframe scheduler %s\n", microframe_schedule ? "enabled":"disabled"); ++ if (microframe_schedule) ++ init_hcd_usecs(hcd); ++ + /* Initialize reset tasklet. */ + hcd->reset_tasklet = DWC_TASK_ALLOC("reset_tasklet", reset_tasklet_func, hcd); + #ifdef DWC_DEV_SRPCAP +@@ -947,9 +963,12 @@ + hcd->flags.d32 = 0; + + hcd->non_periodic_qh_ptr = &hcd->non_periodic_sched_active; +- hcd->non_periodic_channels = 0; +- hcd->periodic_channels = 0; +- ++ if (!microframe_schedule) { ++ hcd->non_periodic_channels = 0; ++ hcd->periodic_channels = 0; ++ } else { ++ hcd->available_host_channels = hcd->core_if->core_params->host_channels; ++ } + /* + * Put all channels in the free channel list and clean up channel + * states. +@@ -1225,17 +1244,38 @@ + dwc_list_link_t *qh_ptr; + dwc_otg_qh_t *qh; + int num_channels; ++ dwc_irqflags_t flags; ++ dwc_spinlock_t *channel_lock = DWC_SPINLOCK_ALLOC(); + dwc_otg_transaction_type_e ret_val = DWC_OTG_TRANSACTION_NONE; + + #ifdef DEBUG_SOF + DWC_DEBUGPL(DBG_HCD, " Select Transactions\n"); + #endif + ++#ifdef DEBUG_HOST_CHANNELS ++ last_sel_trans_num_per_scheduled = 0; ++ last_sel_trans_num_nonper_scheduled = 0; ++ last_sel_trans_num_avail_hc_at_start = hcd->available_host_channels; ++#endif /* DEBUG_HOST_CHANNELS */ ++ + /* Process entries in the periodic ready list. */ + qh_ptr = DWC_LIST_FIRST(&hcd->periodic_sched_ready); + + while (qh_ptr != &hcd->periodic_sched_ready && + !DWC_CIRCLEQ_EMPTY(&hcd->free_hc_list)) { ++ if (microframe_schedule) { ++ // Make sure we leave one channel for non periodic transactions. ++ DWC_SPINLOCK_IRQSAVE(channel_lock, &flags); ++ if (hcd->available_host_channels <= 1) { ++ DWC_SPINUNLOCK_IRQRESTORE(channel_lock, flags); ++ break; ++ } ++ hcd->available_host_channels--; ++ DWC_SPINUNLOCK_IRQRESTORE(channel_lock, flags); ++#ifdef DEBUG_HOST_CHANNELS ++ last_sel_trans_num_per_scheduled++; ++#endif /* DEBUG_HOST_CHANNELS */ ++ } + qh = DWC_LIST_ENTRY(qh_ptr, dwc_otg_qh_t, qh_list_entry); + assign_and_init_hc(hcd, qh); + +@@ -1244,8 +1284,10 @@ + * periodic assigned schedule. + */ + qh_ptr = DWC_LIST_NEXT(qh_ptr); ++ DWC_SPINLOCK_IRQSAVE(channel_lock, &flags); + DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_assigned, + &qh->qh_list_entry); ++ DWC_SPINUNLOCK_IRQRESTORE(channel_lock, flags); + + ret_val = DWC_OTG_TRANSACTION_PERIODIC; + } +@@ -1258,10 +1300,22 @@ + qh_ptr = hcd->non_periodic_sched_inactive.next; + num_channels = hcd->core_if->core_params->host_channels; + while (qh_ptr != &hcd->non_periodic_sched_inactive && +- (hcd->non_periodic_channels < ++ (microframe_schedule || hcd->non_periodic_channels < + num_channels - hcd->periodic_channels) && + !DWC_CIRCLEQ_EMPTY(&hcd->free_hc_list)) { + ++ if (microframe_schedule) { ++ DWC_SPINLOCK_IRQSAVE(channel_lock, &flags); ++ if (hcd->available_host_channels < 1) { ++ DWC_SPINUNLOCK_IRQRESTORE(channel_lock, flags); ++ break; ++ } ++ hcd->available_host_channels--; ++ DWC_SPINUNLOCK_IRQRESTORE(channel_lock, flags); ++#ifdef DEBUG_HOST_CHANNELS ++ last_sel_trans_num_nonper_scheduled++; ++#endif /* DEBUG_HOST_CHANNELS */ ++ } + qh = DWC_LIST_ENTRY(qh_ptr, dwc_otg_qh_t, qh_list_entry); + + assign_and_init_hc(hcd, qh); +@@ -1271,8 +1325,10 @@ + * non-periodic active schedule. + */ + qh_ptr = DWC_LIST_NEXT(qh_ptr); ++ DWC_SPINLOCK_IRQSAVE(channel_lock, &flags); + DWC_LIST_MOVE_HEAD(&hcd->non_periodic_sched_active, + &qh->qh_list_entry); ++ DWC_SPINUNLOCK_IRQRESTORE(channel_lock, flags); + + if (ret_val == DWC_OTG_TRANSACTION_NONE) { + ret_val = DWC_OTG_TRANSACTION_NON_PERIODIC; +@@ -1283,6 +1339,11 @@ + hcd->non_periodic_channels++; + } + ++#ifdef DEBUG_HOST_CHANNELS ++ last_sel_trans_num_avail_hc_at_end = hcd->available_host_channels; ++#endif /* DEBUG_HOST_CHANNELS */ ++ ++ DWC_SPINLOCK_FREE(channel_lock); + return ret_val; + } + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_hcd.h +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/dwc_otg_hcd.h 2013-07-26 19:34:44.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_hcd.h 2013-07-26 19:35:16.000000000 +0000 +@@ -362,6 +362,9 @@ + + /** @} */ + ++ ++ uint16_t speed; ++ uint16_t frame_usecs[8]; + } dwc_otg_qh_t; + + DWC_CIRCLEQ_HEAD(hc_list, dwc_hc); +@@ -477,6 +480,19 @@ + uint16_t periodic_usecs; + + /** ++ * Total bandwidth claimed so far for all periodic transfers ++ * in a frame. ++ * This will include a mixture of HS and FS transfers. ++ * Units are microseconds per (micro)frame. ++ * We have a budget per frame and have to schedule ++ * transactions accordingly. ++ * Watch out for the fact that things are actually scheduled for the ++ * "next frame". ++ */ ++ uint16_t frame_usecs[8]; ++ ++ ++ /** + * Frame number read from the core at SOF. The value ranges from 0 to + * DWC_HFNUM_MAX_FRNUM. + */ +@@ -498,12 +514,17 @@ + * transaction and at least one host channel available for + * non-periodic transactions. + */ +- int periodic_channels; ++ int periodic_channels; /* microframe_schedule==0 */ ++ ++ /** ++ * Number of host channels assigned to non-periodic transfers. ++ */ ++ int non_periodic_channels; /* microframe_schedule==0 */ + + /** + * Number of host channels assigned to non-periodic transfers. + */ +- int non_periodic_channels; ++ int available_host_channels; + + /** + * Array of pointers to the host channel descriptors. Allows accessing +Index: linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_hcd_ddma.c +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/dwc_otg_hcd_ddma.c 2013-07-26 19:34:44.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_hcd_ddma.c 2013-07-26 19:35:16.000000000 +0000 +@@ -39,6 +39,8 @@ + #include "dwc_otg_hcd.h" + #include "dwc_otg_regs.h" + ++extern bool microframe_schedule; ++ + static inline uint8_t frame_list_idx(uint16_t frame) + { + return (frame & (MAX_FRLIST_EN_NUM - 1)); +@@ -273,10 +275,18 @@ + + static void release_channel_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh) + { ++ dwc_irqflags_t flags; ++ dwc_spinlock_t *channel_lock = DWC_SPINLOCK_ALLOC(); ++ + dwc_hc_t *hc = qh->channel; +- if (dwc_qh_is_non_per(qh)) +- hcd->non_periodic_channels--; +- else ++ if (dwc_qh_is_non_per(qh)) { ++ DWC_SPINLOCK_IRQSAVE(channel_lock, &flags); ++ if (!microframe_schedule) ++ hcd->non_periodic_channels--; ++ else ++ hcd->available_host_channels++; ++ DWC_SPINUNLOCK_IRQRESTORE(channel_lock, flags); ++ } else + update_frame_list(hcd, qh, 0); + + /* +@@ -296,6 +306,7 @@ + dwc_memset(qh->desc_list, 0x00, + sizeof(dwc_otg_host_dma_desc_t) * max_desc_num(qh)); + } ++ DWC_SPINLOCK_FREE(channel_lock); + } + + /** +@@ -358,7 +369,7 @@ + release_channel_ddma(hcd, qh); + + if ((qh->ep_type == UE_ISOCHRONOUS || qh->ep_type == UE_INTERRUPT) +- && !hcd->periodic_channels && hcd->frame_list) { ++ && (microframe_schedule || !hcd->periodic_channels) && hcd->frame_list) { + + per_sched_disable(hcd); + frame_list_free(hcd); +@@ -665,7 +676,7 @@ + + qtd->in_process = 1; + +- if (qh->ep_type == UE_CONTROL) ++ if (qh->ep_type == UE_CONTROL) + break; + + if (n_desc == MAX_DMA_DESC_NUM_GENERIC) +Index: linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c 2013-07-26 19:34:44.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c 2013-07-26 19:35:16.000000000 +0000 +@@ -35,6 +35,8 @@ + #include "dwc_otg_hcd.h" + #include "dwc_otg_regs.h" + ++extern bool microframe_schedule; ++ + /** @file + * This file contains the implementation of the HCD Interrupt handlers. + */ +@@ -794,6 +796,8 @@ + { + dwc_otg_transaction_type_e tr_type; + int free_qtd; ++ dwc_irqflags_t flags; ++ dwc_spinlock_t *channel_lock = DWC_SPINLOCK_ALLOC(); + + DWC_DEBUGPL(DBG_HCDV, " %s: channel %d, halt_status %d, xfer_len %d\n", + __func__, hc->hc_num, halt_status, hc->xfer_len); +@@ -853,19 +857,26 @@ + dwc_otg_hc_cleanup(hcd->core_if, hc); + DWC_CIRCLEQ_INSERT_TAIL(&hcd->free_hc_list, hc, hc_list_entry); + +- switch (hc->ep_type) { +- case DWC_OTG_EP_TYPE_CONTROL: +- case DWC_OTG_EP_TYPE_BULK: +- hcd->non_periodic_channels--; +- break; ++ if (!microframe_schedule) { ++ switch (hc->ep_type) { ++ case DWC_OTG_EP_TYPE_CONTROL: ++ case DWC_OTG_EP_TYPE_BULK: ++ hcd->non_periodic_channels--; ++ break; + +- default: +- /* +- * Don't release reservations for periodic channels here. +- * That's done when a periodic transfer is descheduled (i.e. +- * when the QH is removed from the periodic schedule). +- */ +- break; ++ default: ++ /* ++ * Don't release reservations for periodic channels here. ++ * That's done when a periodic transfer is descheduled (i.e. ++ * when the QH is removed from the periodic schedule). ++ */ ++ break; ++ } ++ } else { ++ ++ DWC_SPINLOCK_IRQSAVE(channel_lock, &flags); ++ hcd->available_host_channels++; ++ DWC_SPINUNLOCK_IRQRESTORE(channel_lock, flags); + } + + /* Try to queue more transfers now that there's a free channel. */ +@@ -873,6 +884,7 @@ + if (tr_type != DWC_OTG_TRANSACTION_NONE) { + dwc_otg_hcd_queue_transactions(hcd, tr_type); + } ++ DWC_SPINLOCK_FREE(channel_lock); + } + + /** +Index: linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_hcd_queue.c +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/dwc_otg_hcd_queue.c 2013-07-26 19:34:44.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_hcd_queue.c 2013-07-26 19:35:16.000000000 +0000 +@@ -42,6 +42,8 @@ + #include "dwc_otg_hcd.h" + #include "dwc_otg_regs.h" + ++extern bool microframe_schedule; ++ + /** + * Free each QTD in the QH's QTD-list then free the QH. QH should already be + * removed from a list. QTD list should already be empty if called from URB +@@ -177,6 +179,9 @@ + + hcd->fops->hub_info(hcd, urb->priv, &hub_addr, &hub_port); + qh->do_split = 0; ++ if (microframe_schedule) ++ qh->speed = dev_speed; ++ + + if (((dev_speed == USB_SPEED_LOW) || + (dev_speed == USB_SPEED_FULL)) && +@@ -312,6 +317,8 @@ + return qh; + } + ++/* microframe_schedule=0 start */ ++ + /** + * Checks that a channel is available for a periodic transfer. + * +@@ -380,6 +387,162 @@ + return status; + } + ++/* microframe_schedule=0 end */ ++ ++/** ++ * Microframe scheduler ++ * track the total use in hcd->frame_usecs ++ * keep each qh use in qh->frame_usecs ++ * when surrendering the qh then donate the time back ++ */ ++const unsigned short max_uframe_usecs[]={ 100, 100, 100, 100, 100, 100, 30, 0 }; ++ ++/* ++ * called from dwc_otg_hcd.c:dwc_otg_hcd_init ++ */ ++int init_hcd_usecs(dwc_otg_hcd_t *_hcd) ++{ ++ int i; ++ for (i=0; i<8; i++) { ++ _hcd->frame_usecs[i] = max_uframe_usecs[i]; ++ } ++ return 0; ++} ++ ++static int find_single_uframe(dwc_otg_hcd_t * _hcd, dwc_otg_qh_t * _qh) ++{ ++ int i; ++ unsigned short utime; ++ int t_left; ++ int ret; ++ int done; ++ ++ ret = -1; ++ utime = _qh->usecs; ++ t_left = utime; ++ i = 0; ++ done = 0; ++ while (done == 0) { ++ /* At the start _hcd->frame_usecs[i] = max_uframe_usecs[i]; */ ++ if (utime <= _hcd->frame_usecs[i]) { ++ _hcd->frame_usecs[i] -= utime; ++ _qh->frame_usecs[i] += utime; ++ t_left -= utime; ++ ret = i; ++ done = 1; ++ return ret; ++ } else { ++ i++; ++ if (i == 8) { ++ done = 1; ++ ret = -1; ++ } ++ } ++ } ++ return ret; ++ } ++ ++/* ++ * use this for FS apps that can span multiple uframes ++ */ ++static int find_multi_uframe(dwc_otg_hcd_t * _hcd, dwc_otg_qh_t * _qh) ++{ ++ int i; ++ int j; ++ unsigned short utime; ++ int t_left; ++ int ret; ++ int done; ++ unsigned short xtime; ++ ++ ret = -1; ++ utime = _qh->usecs; ++ t_left = utime; ++ i = 0; ++ done = 0; ++loop: ++ while (done == 0) { ++ if(_hcd->frame_usecs[i] <= 0) { ++ i++; ++ if (i == 8) { ++ done = 1; ++ ret = -1; ++ } ++ goto loop; ++ } ++ ++ /* ++ * we need n consecutive slots ++ * so use j as a start slot j plus j+1 must be enough time (for now) ++ */ ++ xtime= _hcd->frame_usecs[i]; ++ for (j = i+1 ; j < 8 ; j++ ) { ++ /* ++ * if we add this frame remaining time to xtime we may ++ * be OK, if not we need to test j for a complete frame ++ */ ++ if ((xtime+_hcd->frame_usecs[j]) < utime) { ++ if (_hcd->frame_usecs[j] < max_uframe_usecs[j]) { ++ j = 8; ++ ret = -1; ++ continue; ++ } ++ } ++ if (xtime >= utime) { ++ ret = i; ++ j = 8; /* stop loop with a good value ret */ ++ continue; ++ } ++ /* add the frame time to x time */ ++ xtime += _hcd->frame_usecs[j]; ++ /* we must have a fully available next frame or break */ ++ if ((xtime < utime) ++ && (_hcd->frame_usecs[j] == max_uframe_usecs[j])) { ++ ret = -1; ++ j = 8; /* stop loop with a bad value ret */ ++ continue; ++ } ++ } ++ if (ret >= 0) { ++ t_left = utime; ++ for (j = i; (t_left>0) && (j < 8); j++ ) { ++ t_left -= _hcd->frame_usecs[j]; ++ if ( t_left <= 0 ) { ++ _qh->frame_usecs[j] += _hcd->frame_usecs[j] + t_left; ++ _hcd->frame_usecs[j]= -t_left; ++ ret = i; ++ done = 1; ++ } else { ++ _qh->frame_usecs[j] += _hcd->frame_usecs[j]; ++ _hcd->frame_usecs[j] = 0; ++ } ++ } ++ } else { ++ i++; ++ if (i == 8) { ++ done = 1; ++ ret = -1; ++ } ++ } ++ } ++ return ret; ++} ++ ++static int find_uframe(dwc_otg_hcd_t * _hcd, dwc_otg_qh_t * _qh) ++{ ++ int ret; ++ ret = -1; ++ ++ if (_qh->speed == USB_SPEED_HIGH) { ++ /* if this is a hs transaction we need a full frame */ ++ ret = find_single_uframe(_hcd, _qh); ++ } else { ++ /* if this is a fs transaction we may need a sequence of frames */ ++ ret = find_multi_uframe(_hcd, _qh); ++ } ++ return ret; ++} ++ + /** + * Checks that the max transfer size allowed in a host channel is large enough + * to handle the maximum data transfer in a single (micro)frame for a periodic +@@ -423,19 +586,41 @@ + { + int status = 0; + +- status = periodic_channel_available(hcd); +- if (status) { +- DWC_INFO("%s: No host channel available for periodic " "transfer.\n", __func__); //NOTICE +- return status; +- } ++ if (microframe_schedule) { ++ int frame; ++ status = find_uframe(hcd, qh); ++ frame = -1; ++ if (status == 0) { ++ frame = 7; ++ } else { ++ if (status > 0 ) ++ frame = status-1; ++ } + +- status = check_periodic_bandwidth(hcd, qh); +- if (status) { +- DWC_INFO("%s: Insufficient periodic bandwidth for " "periodic transfer.\n", __func__); //NOTICE +- return status; +- } ++ /* Set the new frame up */ ++ if (frame > -1) { ++ qh->sched_frame &= ~0x7; ++ qh->sched_frame |= (frame & 7); ++ } ++ ++ if (status != -1) ++ status = 0; ++ } else { ++ status = periodic_channel_available(hcd); ++ if (status) { ++ DWC_INFO("%s: No host channel available for periodic " "transfer.\n", __func__); //NOTICE ++ return status; ++ } ++ ++ status = check_periodic_bandwidth(hcd, qh); ++ ++ if (status) { ++ DWC_INFO("%s: Insufficient periodic bandwidth for " "periodic transfer.\n", __func__); //NOTICE ++ return status; ++ } + +- status = check_max_xfer_size(hcd, qh); ++ status = check_max_xfer_size(hcd, qh); ++ } + if (status) { + DWC_INFO("%s: Channel max transfer size too small " "for periodic transfer.\n", __func__); //NOTICE + return status; +@@ -450,8 +635,10 @@ + DWC_LIST_INSERT_TAIL(&hcd->periodic_sched_inactive, &qh->qh_list_entry); + } + +- /* Reserve the periodic channel. */ +- hcd->periodic_channels++; ++ if (!microframe_schedule) { ++ /* Reserve the periodic channel. */ ++ hcd->periodic_channels++; ++ } + + /* Update claimed usecs per (micro)frame. */ + hcd->periodic_usecs += qh->usecs; +@@ -502,13 +689,21 @@ + */ + static void deschedule_periodic(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh) + { ++ int i; + DWC_LIST_REMOVE_INIT(&qh->qh_list_entry); + +- /* Release the periodic channel reservation. */ +- hcd->periodic_channels--; ++ if (!microframe_schedule) { ++ /* Release the periodic channel reservation. */ ++ hcd->periodic_channels--; + +- /* Update claimed usecs per (micro)frame. */ +- hcd->periodic_usecs -= qh->usecs; ++ /* Update claimed usecs per (micro)frame. */ ++ hcd->periodic_usecs -= qh->usecs; ++ } else { ++ for (i = 0; i < 8; i++) { ++ hcd->frame_usecs[i] += qh->frame_usecs[i]; ++ qh->frame_usecs[i] = 0; ++ } ++ } + } + + /** +@@ -616,7 +811,8 @@ + * Remove from periodic_sched_queued and move to + * appropriate queue. + */ +- if (qh->sched_frame == frame_number) { ++ if ((microframe_schedule && dwc_frame_num_le(qh->sched_frame, frame_number)) || ++ (!microframe_schedule && qh->sched_frame == frame_number)) { + DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_ready, + &qh->qh_list_entry); + } else { diff -Nru linux-3.2.46/debian/patches/rpi/rpi_215_0872b20fbea2377c6286c39cbc60d3bd83a814aa.patch linux-3.2.46/debian/patches/rpi/rpi_215_0872b20fbea2377c6286c39cbc60d3bd83a814aa.patch --- linux-3.2.46/debian/patches/rpi/rpi_215_0872b20fbea2377c6286c39cbc60d3bd83a814aa.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_215_0872b20fbea2377c6286c39cbc60d3bd83a814aa.patch 2013-07-26 19:35:19.000000000 +0000 @@ -0,0 +1,126 @@ +commit 0872b20fbea2377c6286c39cbc60d3bd83a814aa +Author: popcornmix +Date: Sun Aug 19 14:06:11 2012 +0100 + + Make microframe schedule patch a little closer to denx version. Remove vestiges of HW2937_WORKAROUND + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_cil.c +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/dwc_otg_cil.c 2013-07-26 19:34:44.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_cil.c 2013-07-26 19:35:17.000000000 +0000 +@@ -2403,7 +2403,6 @@ + dwc_otg_core_global_regs_t *global_regs; + dwc_otg_host_global_regs_t *host_global_regs; + +- DWC_DEBUGPL(DBG_HW2937, " dwc_otg_hc_halt(%d)\n", hc->hc_num); + hc_regs = core_if->host_if->hc_regs[hc->hc_num]; + global_regs = core_if->core_global_regs; + host_global_regs = core_if->host_if->host_global_regs; +Index: linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_cil.h +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/dwc_otg_cil.h 2013-07-26 19:34:44.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_cil.h 2013-07-26 19:35:17.000000000 +0000 +@@ -34,8 +34,6 @@ + #if !defined(__DWC_CIL_H__) + #define __DWC_CIL_H__ + +-#define DBG_HW2937 0x400 +- + #include "dwc_list.h" + #include "dwc_otg_dbg.h" + #include "dwc_otg_regs.h" +Index: linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_hcd.c +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/dwc_otg_hcd.c 2013-07-26 19:35:16.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_hcd.c 2013-07-26 19:35:17.000000000 +0000 +@@ -1336,7 +1336,8 @@ + ret_val = DWC_OTG_TRANSACTION_ALL; + } + +- hcd->non_periodic_channels++; ++ if (!microframe_schedule) ++ hcd->non_periodic_channels++; + } + + #ifdef DEBUG_HOST_CHANNELS +Index: linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_hcd.h +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/dwc_otg_hcd.h 2013-07-26 19:35:16.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_hcd.h 2013-07-26 19:35:17.000000000 +0000 +@@ -369,16 +369,6 @@ + + DWC_CIRCLEQ_HEAD(hc_list, dwc_hc); + +-#ifdef HW2937_WORKAROUND +- +-typedef enum { +- HW2937_XFER_MODE_IDLE, +- HW2937_XFER_MODE_IN, +- HW2937_XFER_MODE_OUT, +- HW2937_XFER_MODE_PAUSEIN /* Transitioning from IN to IDLE */ +-} hw2937_xfer_mode_t; +-#endif +- + /** + * This structure holds the state of the HCD, including the non-periodic and + * periodic schedules. +@@ -572,14 +562,6 @@ + /** Frame List DMA address */ + dma_addr_t frame_list_dma; + +-#ifdef HW2937_WORKAROUND +- /** Current transfer mode (IN, OUT, or IDLE) */ +- hw2937_xfer_mode_t hw2937_xfer_mode; +- +- /** Mask of channels assigned to the current mode */ +- uint32_t hw2937_assigned_channels; +-#endif +- + #ifdef DEBUG + uint32_t frrem_samples; + uint64_t frrem_accum; +Index: linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_hcd_queue.c +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/dwc_otg_hcd_queue.c 2013-07-26 19:35:16.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_hcd_queue.c 2013-07-26 19:35:17.000000000 +0000 +@@ -613,16 +613,16 @@ + } + + status = check_periodic_bandwidth(hcd, qh); +- +- if (status) { +- DWC_INFO("%s: Insufficient periodic bandwidth for " "periodic transfer.\n", __func__); //NOTICE +- return status; +- } +- +- status = check_max_xfer_size(hcd, qh); + } + if (status) { +- DWC_INFO("%s: Channel max transfer size too small " "for periodic transfer.\n", __func__); //NOTICE ++ DWC_INFO("%s: Insufficient periodic bandwidth for " ++ "periodic transfer.\n", __func__); ++ return status; ++ } ++ status = check_max_xfer_size(hcd, qh); ++ if (status) { ++ DWC_INFO("%s: Channel max transfer size too small " ++ "for periodic transfer.\n", __func__); + return status; + } + +@@ -692,12 +692,12 @@ + int i; + DWC_LIST_REMOVE_INIT(&qh->qh_list_entry); + ++ /* Update claimed usecs per (micro)frame. */ ++ hcd->periodic_usecs -= qh->usecs; ++ + if (!microframe_schedule) { + /* Release the periodic channel reservation. */ + hcd->periodic_channels--; +- +- /* Update claimed usecs per (micro)frame. */ +- hcd->periodic_usecs -= qh->usecs; + } else { + for (i = 0; i < 8; i++) { + hcd->frame_usecs[i] += qh->frame_usecs[i]; diff -Nru linux-3.2.46/debian/patches/rpi/rpi_216_d6911d65886f2db4d0966879102e13c130ec8515.patch linux-3.2.46/debian/patches/rpi/rpi_216_d6911d65886f2db4d0966879102e13c130ec8515.patch --- linux-3.2.46/debian/patches/rpi/rpi_216_d6911d65886f2db4d0966879102e13c130ec8515.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_216_d6911d65886f2db4d0966879102e13c130ec8515.patch 2013-07-26 19:35:33.000000000 +0000 @@ -0,0 +1,77290 @@ +commit d6911d65886f2db4d0966879102e13c130ec8515 +Author: popcornmix +Date: Sun Aug 19 14:07:26 2012 +0100 + + Remove remove documentation from the source tree + There is lots of doxygen-generated bundled source documentation in the + tree. As this is in the source code, remove this redundant copy. + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/annotated.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/annotated.html 2013-07-26 19:34:39.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,101 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Structures +- +- +- +-

                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver Data Structures

                                                                                Here are the data structures with brief descriptions:
                                                                                ++   ++ + +

                                                                                + Packets per frame for periodic transfers. +

                                                                                + 0 is reserved. +

                                                                                +-Definition at line 1887 of file dwc_otg_regs.h. +- +-

                                                                                +- +-

                                                                                +-
                                                                                +- ++Definition at line 2116 of file dwc_otg_regs.h. ++ ++
                                                                                ++

                                                                                ++ ++ ++ ++ ++
                                                                                ++ + +- ++ + +
                                                                                unsigned hcchar_data::oddfrm unsigned hcchar_data::oddfrm
                                                                                +- +-
                                                                                ++
                                                                                ++ ++ ++ ++ ++ ++
                                                                                ++   ++ + +

                                                                                + Frame to transmit periodic transaction. +

                                                                                +-0: even, 1: odd ++0: even, 1: odd +

                                                                                +-Definition at line 1896 of file dwc_otg_regs.h. +- +-

                                                                                ++Definition at line 2125 of file dwc_otg_regs.h.

                                                                                +

                                                                                The documentation for this union was generated from the following file: +-
                                                                                Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++
                                                                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
                                                                                ++doxygen 1.3.9.1
                                                                                + + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/unionhcdma__data.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/unionhcdma__data.html 2013-07-26 19:31:22.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/unionhcdma__data.html 2013-07-26 19:34:43.000000000 +0000 +@@ -2,22 +2,10 @@ + + DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: hcdma_data Union Reference + +- + +- +-
                                                                                +-
                                                                                +-
                                                                                +-
                                                                                +-

                                                                                hcdma_data Union Reference

                                                                                This union represents the bit fields in the Host DMA Address Register used in Descriptor DMA mode. ++ ++
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                ++

                                                                                hcdma_data Union Reference

                                                                                This union represents the bit fields in the Host DMA Address Register used in Descriptor DMA mode. + More... +

                                                                                + #include <dwc_otg_regs.h> +@@ -25,22 +13,22 @@ + + + +- ++ + + +- + +- ++ + +- ++ + +- +- ++ ++ + + +- ++ + + +

                                                                                Data Fields

                                                                                +-uint32_t d32
                                                                                ++uint32_t d32
                                                                                 raw register data
                                                                                ++
                                                                                + struct {
                                                                                   unsigned   reserved0_2: 3
                                                                                   unsigned   reserved0_2:3
                                                                                   unsigned   ctd: 8
                                                                                   unsigned   ctd:8
                                                                                 Current Transfer Descriptor.
                                                                                   unsigned   dma_addr: 21
                                                                                 Current Transfer Descriptor.
                                                                                   unsigned   dma_addr:21
                                                                                 Start Address of Descriptor List.
                                                                                } b
                                                                                } b
                                                                                 register bits
                                                                                +@@ -49,30 +37,38 @@ +

                                                                                + +

                                                                                +-Definition at line 2086 of file dwc_otg_regs.h.

                                                                                Field Documentation

                                                                                +- +-
                                                                                +-
                                                                                +- ++Definition at line 2307 of file dwc_otg_regs.h.

                                                                                Field Documentation

                                                                                ++

                                                                                ++

                                                                                ++ ++ ++ ++
                                                                                ++ + +- ++ + +
                                                                                unsigned hcdma_data::ctd unsigned hcdma_data::ctd
                                                                                +- +-
                                                                                ++
                                                                                ++ ++ ++ ++ ++ ++
                                                                                ++   ++ + +

                                                                                + Current Transfer Descriptor. +

                                                                                + Not used for ISOC +

                                                                                +-Definition at line 2095 of file dwc_otg_regs.h. +- +-

                                                                                ++Definition at line 2314 of file dwc_otg_regs.h.

                                                                                +
                                                                                The documentation for this union was generated from the following file: +-
                                                                                Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++
                                                                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
                                                                                ++doxygen 1.3.9.1
                                                                                + + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/unionhcfg__data.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/unionhcfg__data.html 2013-07-26 19:31:22.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/unionhcfg__data.html 2013-07-26 19:34:43.000000000 +0000 +@@ -2,22 +2,10 @@ + + DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: hcfg_data Union Reference + +- + +- +-
                                                                                +-
                                                                                +-
                                                                                +-
                                                                                +-

                                                                                hcfg_data Union Reference

                                                                                This union represents the bit fields in the Host Configuration Register. ++ ++
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                ++

                                                                                hcfg_data Union Reference

                                                                                This union represents the bit fields in the Host Configuration Register. + More... +

                                                                                + #include <dwc_otg_regs.h> +@@ -25,34 +13,43 @@ + + + +- ++ + + +- + +- ++ + + +- ++ + + +- ++ + +- ++ ++ ++ ++ ++ ++ ++ ++ ++ + + +- ++ + + +- ++ + + +- ++ ++ ++ + +- +- ++ + + +

                                                                                Data Fields

                                                                                +-uint32_t d32
                                                                                ++uint32_t d32
                                                                                 raw register data
                                                                                ++
                                                                                + struct {
                                                                                   unsigned   fslspclksel:2
                                                                                   unsigned   fslspclksel:2
                                                                                 FS/LS Phy Clock Select.
                                                                                   unsigned   fslssupp:1
                                                                                   unsigned   fslssupp:1
                                                                                 FS/LS Only Support.
                                                                                   unsigned   reserved3_22: 20
                                                                                   unsigned   reserved3_6:4
                                                                                   unsigned   descdma: 1
                                                                                   unsigned   ena32khzs:1
                                                                                 Enable 32-KHz Suspend Mode.
                                                                                   unsigned   resvalid:8
                                                                                 Resume Validation Periiod.
                                                                                   unsigned   reserved16_22:7
                                                                                   unsigned   descdma:1
                                                                                 Enable Scatter/gather DMA in Host mode.
                                                                                   unsigned   frlisten: 2
                                                                                   unsigned   frlisten:2
                                                                                 Frame List Entries.
                                                                                   unsigned   perschedena: 1
                                                                                   unsigned   perschedena:1
                                                                                 Enable Periodic Scheduling.
                                                                                   unsigned   perschedstat: 1
                                                                                   unsigned   reserved27_30:4
                                                                                   unsigned   modechtimen:1
                                                                                 Periodic Scheduling Enabled Status.
                                                                                } b
                                                                                } b
                                                                                 register bits
                                                                                +@@ -63,10 +60,10 @@ +

                                                                                + +

                                                                                +-Definition at line 1652 of file dwc_otg_regs.h.

                                                                                The documentation for this union was generated from the following file:
                                                                                  ++Definition at line 1878 of file dwc_otg_regs.h.
                                                                                  The documentation for this union was generated from the following file: +-
                                                                                  Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++
                                                                                  Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
                                                                                  ++doxygen 1.3.9.1
                                                                                  + + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/unionhcint__data.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/unionhcint__data.html 2013-07-26 19:31:22.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/unionhcint__data.html 2013-07-26 19:34:43.000000000 +0000 +@@ -2,22 +2,10 @@ + + DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: hcint_data Union Reference + +- + +- +-
                                                                                  +-
                                                                                  +-
                                                                                  +-
                                                                                  +-

                                                                                  hcint_data Union Reference

                                                                                  This union represents the bit fields in the Host All Interrupt Register. ++ ++
                                                                                  Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                  ++

                                                                                  hcint_data Union Reference

                                                                                  This union represents the bit fields in the Host All Interrupt Register. + More... +

                                                                                  + #include <dwc_otg_regs.h> +@@ -25,59 +13,59 @@ + + + +- ++ + + +- + +- ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ + + +

                                                                                  Data Fields

                                                                                  +-uint32_t d32
                                                                                  ++uint32_t d32
                                                                                   raw register data
                                                                                  ++
                                                                                  + struct {
                                                                                     unsigned   xfercomp:1
                                                                                     unsigned   xfercomp:1
                                                                                   Transfer Complete.
                                                                                     unsigned   chhltd:1
                                                                                     unsigned   chhltd:1
                                                                                   Channel Halted.
                                                                                     unsigned   ahberr:1
                                                                                     unsigned   ahberr:1
                                                                                   AHB Error.
                                                                                     unsigned   stall:1
                                                                                     unsigned   stall:1
                                                                                   STALL Response Received.
                                                                                     unsigned   nak:1
                                                                                     unsigned   nak:1
                                                                                   NAK Response Received.
                                                                                     unsigned   ack:1
                                                                                     unsigned   ack:1
                                                                                   ACK Response Received.
                                                                                     unsigned   nyet:1
                                                                                     unsigned   nyet:1
                                                                                   NYET Response Received.
                                                                                     unsigned   xacterr:1
                                                                                     unsigned   xacterr:1
                                                                                   Transaction Err.
                                                                                     unsigned   bblerr:1
                                                                                     unsigned   bblerr:1
                                                                                   Babble Error.
                                                                                     unsigned   frmovrun:1
                                                                                     unsigned   frmovrun:1
                                                                                   Frame Overrun.
                                                                                     unsigned   datatglerr:1
                                                                                     unsigned   datatglerr:1
                                                                                   Data Toggle Error.
                                                                                     unsigned   bna: 1
                                                                                     unsigned   bna:1
                                                                                   Buffer Not Available (only for DDMA mode).
                                                                                     unsigned   xcs_xact: 1
                                                                                     unsigned   xcs_xact:1
                                                                                   Exessive transaction error (only for DDMA mode).
                                                                                     unsigned   frm_list_roll: 1
                                                                                     unsigned   frm_list_roll:1
                                                                                   Frame List Rollover interrupt.
                                                                                     unsigned   reserved14_31: 18
                                                                                     unsigned   reserved14_31:18
                                                                                   Reserved.
                                                                                  } b
                                                                                  } b
                                                                                   register bits
                                                                                  +@@ -86,10 +74,10 @@ +

                                                                                  + +

                                                                                  +-Definition at line 1940 of file dwc_otg_regs.h.

                                                                                  The documentation for this union was generated from the following file:
                                                                                    ++Definition at line 2169 of file dwc_otg_regs.h.
                                                                                    The documentation for this union was generated from the following file: +-
                                                                                    Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++
                                                                                    Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
                                                                                    ++doxygen 1.3.9.1
                                                                                    + + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/unionhcintmsk__data.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/unionhcintmsk__data.html 2013-07-26 19:31:22.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/unionhcintmsk__data.html 2013-07-26 19:34:43.000000000 +0000 +@@ -2,22 +2,10 @@ + + DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: hcintmsk_data Union Reference + +- + +- +-
                                                                                    +-
                                                                                    +-
                                                                                    +-
                                                                                    +-

                                                                                    hcintmsk_data Union Reference

                                                                                    This union represents the bit fields in the Host Channel Interrupt Mask Register. ++ ++
                                                                                    Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                    ++

                                                                                    hcintmsk_data Union Reference

                                                                                    This union represents the bit fields in the Host Channel Interrupt Mask Register. + More... +

                                                                                    + #include <dwc_otg_regs.h> +@@ -25,44 +13,44 @@ + + + +- ++ + + +- + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + + +

                                                                                    Data Fields

                                                                                    +-uint32_t d32
                                                                                    ++uint32_t d32
                                                                                     raw register data
                                                                                    ++
                                                                                    + struct {
                                                                                       unsigned   xfercompl: 1
                                                                                       unsigned   xfercompl:1
                                                                                       unsigned   chhltd: 1
                                                                                       unsigned   chhltd:1
                                                                                       unsigned   ahberr: 1
                                                                                       unsigned   ahberr:1
                                                                                       unsigned   stall: 1
                                                                                       unsigned   stall:1
                                                                                       unsigned   nak: 1
                                                                                       unsigned   nak:1
                                                                                       unsigned   ack: 1
                                                                                       unsigned   ack:1
                                                                                       unsigned   nyet: 1
                                                                                       unsigned   nyet:1
                                                                                       unsigned   xacterr: 1
                                                                                       unsigned   xacterr:1
                                                                                       unsigned   bblerr: 1
                                                                                       unsigned   bblerr:1
                                                                                       unsigned   frmovrun: 1
                                                                                       unsigned   frmovrun:1
                                                                                       unsigned   datatglerr: 1
                                                                                       unsigned   datatglerr:1
                                                                                       unsigned   bna: 1
                                                                                       unsigned   bna:1
                                                                                       unsigned   xcs_xact: 1
                                                                                       unsigned   xcs_xact:1
                                                                                       unsigned   frm_list_roll: 1
                                                                                       unsigned   frm_list_roll:1
                                                                                       unsigned   reserved14_31: 18
                                                                                       unsigned   reserved14_31:18
                                                                                    } b
                                                                                    } b
                                                                                     register bits
                                                                                    +@@ -73,10 +61,10 @@ +

                                                                                    + +

                                                                                    +-Definition at line 1986 of file dwc_otg_regs.h.

                                                                                    The documentation for this union was generated from the following file:
                                                                                      ++Definition at line 2213 of file dwc_otg_regs.h.
                                                                                      The documentation for this union was generated from the following file: +-
                                                                                      Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++
                                                                                      Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
                                                                                      ++doxygen 1.3.9.1
                                                                                      + + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/unionhcsplt__data.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/unionhcsplt__data.html 2013-07-26 19:31:22.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,63 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: hcsplt_data Union Reference +- +- +- +- +-
                                                                                      +-
                                                                                      +-
                                                                                      +-
                                                                                      +-

                                                                                      hcsplt_data Union Reference

                                                                                      +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-

                                                                                      Data Fields

                                                                                      +-uint32_t d32
                                                                                       raw register data
                                                                                      +-struct {
                                                                                         unsigned   prtaddr:7
                                                                                       Port Address.
                                                                                         unsigned   hubaddr:7
                                                                                       Hub Address.
                                                                                         unsigned   xactpos:2
                                                                                       Transaction Position.
                                                                                         unsigned   compsplt:1
                                                                                       Do Complete Split.
                                                                                         unsigned   reserved:14
                                                                                       Reserved.
                                                                                         unsigned   spltena:1
                                                                                       Split Enble.
                                                                                      } b
                                                                                       register bits
                                                                                      +-

                                                                                      Detailed Description

                                                                                      +- +-

                                                                                      +- +-

                                                                                      +-Definition at line 1906 of file dwc_otg_regs.h.

                                                                                      The documentation for this union was generated from the following file: +-
                                                                                      Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.4.7
                                                                                      +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/unionhctsiz__data.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/unionhctsiz__data.html 2013-07-26 19:31:22.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/unionhctsiz__data.html 2013-07-26 19:34:43.000000000 +0000 +@@ -2,22 +2,10 @@ + + DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: hctsiz_data Union Reference + +- + +- +-
                                                                                      +-
                                                                                      +-
                                                                                      +-
                                                                                      +-

                                                                                      hctsiz_data Union Reference

                                                                                      This union represents the bit fields in the Host Channel Transfer Size Register. ++ ++
                                                                                      Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                      ++

                                                                                      hctsiz_data Union Reference

                                                                                      This union represents the bit fields in the Host Channel Transfer Size Register. + More... +

                                                                                      + #include <dwc_otg_regs.h> +@@ -25,47 +13,47 @@ + + + +- ++ + + +- + +- ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ + + +- + +- ++ + + +- ++ + +- +- ++ ++ + + +- ++ + + +- ++ + + +- ++ + + +

                                                                                      Data Fields

                                                                                      +-uint32_t d32
                                                                                      ++uint32_t d32
                                                                                       raw register data
                                                                                      ++
                                                                                      + struct {
                                                                                         unsigned   xfersize:19
                                                                                         unsigned   xfersize:19
                                                                                       Total transfer size in bytes.
                                                                                         unsigned   pktcnt:10
                                                                                         unsigned   pktcnt:10
                                                                                       Data packets to transfer.
                                                                                         unsigned   pid:2
                                                                                         unsigned   pid:2
                                                                                       Packet ID for next data packet 0: DATA0 1: DATA2 2: DATA1 3: MDATA (non-Control), SETUP (Control).
                                                                                         unsigned   dopng:1
                                                                                         unsigned   dopng:1
                                                                                       Do PING protocol when 1.
                                                                                      } b
                                                                                      } b
                                                                                       register bits
                                                                                      ++
                                                                                      + struct {
                                                                                         unsigned   schinfo: 8
                                                                                         unsigned   schinfo:8
                                                                                       Scheduling information.
                                                                                         unsigned   ntd: 8
                                                                                         unsigned   ntd:8
                                                                                       Number of transfer descriptors.
                                                                                         unsigned   reserved16_28: 13
                                                                                       Number of transfer descriptors.
                                                                                         unsigned   reserved16_28:13
                                                                                       Data packets to transfer.
                                                                                         unsigned   pid: 2
                                                                                         unsigned   pid:2
                                                                                       Packet ID for next data packet 0: DATA0 1: DATA2 2: DATA1 3: MDATA (non-Control).
                                                                                         unsigned   dopng: 1
                                                                                         unsigned   dopng:1
                                                                                       Do PING protocol when 1.
                                                                                      } b_ddma
                                                                                      } b_ddma
                                                                                       register bits
                                                                                      +@@ -76,30 +64,38 @@ +

                                                                                      + +

                                                                                      +-Definition at line 2019 of file dwc_otg_regs.h.

                                                                                      Field Documentation

                                                                                      +- +-
                                                                                      +-
                                                                                      +- ++Definition at line 2244 of file dwc_otg_regs.h.

                                                                                      Field Documentation

                                                                                      ++

                                                                                      ++

                                                                                      ++ ++ ++ ++
                                                                                      ++ + +- ++ + +
                                                                                      unsigned hctsiz_data::ntd unsigned hctsiz_data::ntd
                                                                                      +- +-
                                                                                      ++
                                                                                      ++ ++ ++ ++ ++ ++
                                                                                      ++   ++ + +

                                                                                      + Number of transfer descriptors. +

                                                                                      +-Max value: 64 in general, 256 only for HS isochronous endpoint. ++Max value: 64 in general, 256 only for HS isochronous endpoint. +

                                                                                      +-Definition at line 2062 of file dwc_otg_regs.h. +- +-

                                                                                      ++Definition at line 2284 of file dwc_otg_regs.h.

                                                                                      +
                                                                                      The documentation for this union was generated from the following file: +-
                                                                                      Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++
                                                                                      Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
                                                                                      ++doxygen 1.3.9.1
                                                                                      + + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/unionhfir__data.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/unionhfir__data.html 2013-07-26 19:31:22.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/unionhfir__data.html 2013-07-26 19:34:43.000000000 +0000 +@@ -2,22 +2,10 @@ + + DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: hfir_data Union Reference + +- + +- +-
                                                                                      +-
                                                                                      +-
                                                                                      +-
                                                                                      +-

                                                                                      hfir_data Union Reference

                                                                                      This union represents the bit fields in the Host Frame Remaing/Number Register. ++ ++
                                                                                      Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                      ++

                                                                                      hfir_data Union Reference

                                                                                      This union represents the bit fields in the Host Frame Remaing/Number Register. + More... +

                                                                                      + #include <dwc_otg_regs.h> +@@ -25,18 +13,20 @@ + + + +- ++ + + +- + +- ++ + +- ++ + +- ++ ++ ++ + + +

                                                                                      Data Fields

                                                                                      +-uint32_t d32
                                                                                      ++uint32_t d32
                                                                                       raw register data
                                                                                      ++
                                                                                      + struct {
                                                                                         unsigned   frint:16
                                                                                         unsigned   frint:16
                                                                                         unsigned   reserved:16
                                                                                         unsigned   hfirrldctrl:1
                                                                                      } b
                                                                                         unsigned   reserved:15
                                                                                      } b
                                                                                       register bits
                                                                                      +@@ -45,10 +35,10 @@ +

                                                                                      + +

                                                                                      +-Definition at line 1684 of file dwc_otg_regs.h.

                                                                                      The documentation for this union was generated from the following file:
                                                                                        ++Definition at line 1913 of file dwc_otg_regs.h.
                                                                                        The documentation for this union was generated from the following file: +-
                                                                                        Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++
                                                                                        Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
                                                                                        ++doxygen 1.3.9.1
                                                                                        + + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/unionhfnum__data.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/unionhfnum__data.html 2013-07-26 19:31:22.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/unionhfnum__data.html 2013-07-26 19:34:43.000000000 +0000 +@@ -2,22 +2,10 @@ + + DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: hfnum_data Union Reference + +- + +- +-
                                                                                        +-
                                                                                        +-
                                                                                        +-
                                                                                        +-

                                                                                        hfnum_data Union Reference

                                                                                        This union represents the bit fields in the Host Frame Remaing/Number Register. ++ ++
                                                                                        Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                        ++

                                                                                        hfnum_data Union Reference

                                                                                        This union represents the bit fields in the Host Frame Remaing/Number Register. + More... +

                                                                                        + #include <dwc_otg_regs.h> +@@ -25,18 +13,18 @@ + + + +- ++ + + +- + +- ++ + +- ++ + +- ++ + + +

                                                                                        Data Fields

                                                                                        +-uint32_t d32
                                                                                        ++uint32_t d32
                                                                                         raw register data
                                                                                        ++
                                                                                        + struct {
                                                                                           unsigned   frnum:16
                                                                                           unsigned   frnum:16
                                                                                           unsigned   frrem:16
                                                                                           unsigned   frrem:16
                                                                                        } b
                                                                                        } b
                                                                                         register bits
                                                                                        +@@ -45,10 +33,10 @@ +

                                                                                        + +

                                                                                        +-Definition at line 1699 of file dwc_otg_regs.h.

                                                                                        The documentation for this union was generated from the following file:
                                                                                          ++Definition at line 1929 of file dwc_otg_regs.h.
                                                                                          The documentation for this union was generated from the following file: +-
                                                                                          Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++
                                                                                          Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
                                                                                          ++doxygen 1.3.9.1
                                                                                          + + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/unionhost__dma__desc__sts.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/unionhost__dma__desc__sts.html 2013-07-26 19:31:22.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/unionhost__dma__desc__sts.html 2013-07-26 19:34:43.000000000 +0000 +@@ -2,22 +2,10 @@ + + DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: host_dma_desc_sts Union Reference + +- + +- +-
                                                                                          +-
                                                                                          +-
                                                                                          +-
                                                                                          +-

                                                                                          host_dma_desc_sts Union Reference

                                                                                          This union represents the bit fields in the DMA Descriptor status quadlet for host mode. ++ ++
                                                                                          Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                          ++

                                                                                          host_dma_desc_sts Union Reference

                                                                                          This union represents the bit fields in the DMA Descriptor status quadlet for host mode. + More... +

                                                                                          + #include <dwc_otg_regs.h> +@@ -25,63 +13,63 @@ + + + +- ++ + + +- + +- ++ + + +- ++ + + +- ++ + + +- ++ + +- +- ++ ++ + + +- ++ + + +- ++ + +- ++ + + +- ++ + +- ++ + + +- ++ + + +- + +- ++ + + +- ++ + +- ++ + + +- ++ + +- ++ + + +- ++ + +- ++ + + + +@@ -94,30 +82,38 @@ +

                                                                                          + +

                                                                                          +-Definition at line 2106 of file dwc_otg_regs.h.

                                                                                          Field Documentation

                                                                                          +- +-
                                                                                          +-
                                                                                          +-

                                                                                          Data Fields

                                                                                          +-uint32_t d32
                                                                                          ++uint32_t d32
                                                                                           raw register data
                                                                                          ++
                                                                                          + struct {
                                                                                             unsigned   n_bytes: 17
                                                                                             unsigned   n_bytes:17
                                                                                           Number of bytes.
                                                                                             unsigned   qtd_offset: 6
                                                                                             unsigned   qtd_offset:6
                                                                                           QTD offset to jump when Short Packet received - only for IN EPs.
                                                                                             unsigned   a_qtd: 1
                                                                                             unsigned   a_qtd:1
                                                                                           Set to request the core to jump to alternate QTD if Short Packet received - only for IN EPs.
                                                                                             unsigned   sup: 1
                                                                                             unsigned   sup:1
                                                                                           Setup Packet bit.
                                                                                             unsigned   ioc: 1
                                                                                           Setup Packet bit.
                                                                                             unsigned   ioc:1
                                                                                           Interrupt On Complete.
                                                                                             unsigned   eol: 1
                                                                                             unsigned   eol:1
                                                                                           End of List.
                                                                                             unsigned   reserved27: 1
                                                                                             unsigned   reserved27:1
                                                                                             unsigned   sts: 2
                                                                                             unsigned   sts:2
                                                                                           Rx/Tx Status.
                                                                                             unsigned   reserved30: 1
                                                                                             unsigned   reserved30:1
                                                                                             unsigned   a: 1
                                                                                             unsigned   a:1
                                                                                           Active Bit.
                                                                                          } b
                                                                                          } b
                                                                                           quadlet bits
                                                                                          ++
                                                                                          + struct {
                                                                                             unsigned   n_bytes: 12
                                                                                             unsigned   n_bytes:12
                                                                                           Number of bytes.
                                                                                             unsigned   reserved12_24: 13
                                                                                             unsigned   reserved12_24:13
                                                                                             unsigned   ioc: 1
                                                                                             unsigned   ioc:1
                                                                                           Interrupt On Complete.
                                                                                             unsigned   reserved26_27: 2
                                                                                             unsigned   reserved26_27:2
                                                                                             unsigned   sts: 2
                                                                                             unsigned   sts:2
                                                                                           Rx/Tx Status.
                                                                                             unsigned   reserved30: 1
                                                                                             unsigned   reserved30:1
                                                                                             unsigned   a: 1
                                                                                             unsigned   a:1
                                                                                           Active Bit.
                                                                                          } b_isoc
                                                                                          ++Definition at line 2325 of file dwc_otg_regs.h.

                                                                                          Field Documentation

                                                                                          ++

                                                                                          ++

                                                                                          ++ ++ ++ ++
                                                                                          ++ + +- ++ + +
                                                                                          unsigned host_dma_desc_sts::sup unsigned host_dma_desc_sts::sup
                                                                                          +- +-
                                                                                          ++
                                                                                          ++ ++ ++ ++ ++ ++
                                                                                          ++   ++ + +

                                                                                          + Setup Packet bit. +

                                                                                          +-When set indicates that buffer contains setup packet. ++When set indicates that buffer contains setup packet. +

                                                                                          +-Definition at line 2127 of file dwc_otg_regs.h. +- +-

                                                                                          ++Definition at line 2345 of file dwc_otg_regs.h.

                                                                                          +

                                                                                          The documentation for this union was generated from the following file: +-
                                                                                          Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++
                                                                                          Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
                                                                                          ++doxygen 1.3.9.1
                                                                                          + + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/unionhost__grxsts__data.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/unionhost__grxsts__data.html 2013-07-26 19:31:22.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/unionhost__grxsts__data.html 2013-07-26 19:34:43.000000000 +0000 +@@ -2,22 +2,10 @@ + + DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: host_grxsts_data Union Reference + +- + +- +-
                                                                                          +-
                                                                                          +-
                                                                                          +-
                                                                                          +-

                                                                                          host_grxsts_data Union Reference

                                                                                          This union represents the bit fields in the Host Receive Status Read and Pop Registers (GRXSTSR, GRXSTSP) Read the register into the d32 element then read out the bits using the bit elements. ++ ++
                                                                                          Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                          ++

                                                                                          host_grxsts_data Union Reference

                                                                                          This union represents the bit fields in the Host Receive Status Read and Pop Registers (GRXSTSR, GRXSTSP) Read the register into the d32 element then read out the bits using the bit elements. + More... +

                                                                                          + #include <dwc_otg_regs.h> +@@ -25,24 +13,24 @@ + + + +- ++ + + +- + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + + +

                                                                                          Data Fields

                                                                                          +-uint32_t d32
                                                                                          ++uint32_t d32
                                                                                           raw register data
                                                                                          ++
                                                                                          + struct {
                                                                                             unsigned   chnum:4
                                                                                             unsigned   chnum:4
                                                                                             unsigned   bcnt:11
                                                                                             unsigned   bcnt:11
                                                                                             unsigned   dpid:2
                                                                                             unsigned   dpid:2
                                                                                             unsigned   pktsts:4
                                                                                             unsigned   pktsts:4
                                                                                             unsigned   reserved:11
                                                                                             unsigned   reserved21_31:11
                                                                                          } b
                                                                                          } b
                                                                                           register bits
                                                                                          +@@ -51,10 +39,10 @@ +

                                                                                          + +

                                                                                          +-Definition at line 627 of file dwc_otg_regs.h.

                                                                                          The documentation for this union was generated from the following file:
                                                                                            ++Definition at line 548 of file dwc_otg_regs.h.
                                                                                            The documentation for this union was generated from the following file: +-
                                                                                            Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++
                                                                                            Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
                                                                                            ++doxygen 1.3.9.1
                                                                                            + + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/unionhprt0__data.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/unionhprt0__data.html 2013-07-26 19:31:22.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/unionhprt0__data.html 2013-07-26 19:34:43.000000000 +0000 +@@ -2,22 +2,10 @@ + + DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: hprt0_data Union Reference + +- + +- +-
                                                                                            +-
                                                                                            +-
                                                                                            +-
                                                                                            +-

                                                                                            hprt0_data Union Reference

                                                                                            This union represents the bit fields in the Host Port Control and Status Register. ++ ++
                                                                                            Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                            ++

                                                                                            hprt0_data Union Reference

                                                                                            This union represents the bit fields in the Host Port Control and Status Register. + More... +

                                                                                            + #include <dwc_otg_regs.h> +@@ -25,44 +13,44 @@ + + + +- ++ + + +- + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + + +

                                                                                            Data Fields

                                                                                            +-uint32_t d32
                                                                                            ++uint32_t d32
                                                                                             raw register data
                                                                                            ++
                                                                                            + struct {
                                                                                               unsigned   prtconnsts:1
                                                                                               unsigned   prtconnsts:1
                                                                                               unsigned   prtconndet:1
                                                                                               unsigned   prtconndet:1
                                                                                               unsigned   prtena:1
                                                                                               unsigned   prtena:1
                                                                                               unsigned   prtenchng:1
                                                                                               unsigned   prtenchng:1
                                                                                               unsigned   prtovrcurract:1
                                                                                               unsigned   prtovrcurract:1
                                                                                               unsigned   prtovrcurrchng:1
                                                                                               unsigned   prtovrcurrchng:1
                                                                                               unsigned   prtres:1
                                                                                               unsigned   prtres:1
                                                                                               unsigned   prtsusp:1
                                                                                               unsigned   prtsusp:1
                                                                                               unsigned   prtrst:1
                                                                                               unsigned   prtrst:1
                                                                                               unsigned   reserved9:1
                                                                                               unsigned   reserved9:1
                                                                                               unsigned   prtlnsts:2
                                                                                               unsigned   prtlnsts:2
                                                                                               unsigned   prtpwr:1
                                                                                               unsigned   prtpwr:1
                                                                                               unsigned   prttstctl:4
                                                                                               unsigned   prttstctl:4
                                                                                               unsigned   prtspd:2
                                                                                               unsigned   prtspd:2
                                                                                               unsigned   reserved19_31:13
                                                                                               unsigned   reserved19_31:13
                                                                                            } b
                                                                                            } b
                                                                                             register bits
                                                                                            +@@ -73,10 +61,10 @@ +

                                                                                            + +

                                                                                            +-Definition at line 1741 of file dwc_otg_regs.h.

                                                                                            The documentation for this union was generated from the following file:
                                                                                              ++Definition at line 1971 of file dwc_otg_regs.h.
                                                                                              The documentation for this union was generated from the following file: +-
                                                                                              Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++
                                                                                              Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
                                                                                              ++doxygen 1.3.9.1
                                                                                              + + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/unionhptxsts__data.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/unionhptxsts__data.html 2013-07-26 19:31:22.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,62 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: hptxsts_data Union Reference +- +- +- +- +-
                                                                                              +-
                                                                                              +-
                                                                                              +-
                                                                                              +-

                                                                                              hptxsts_data Union Reference

                                                                                              +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-

                                                                                              Data Fields

                                                                                              +-uint32_t d32
                                                                                               raw register data
                                                                                              +-struct {
                                                                                                 unsigned   ptxfspcavail:16
                                                                                                 unsigned   ptxqspcavail:8
                                                                                                 unsigned   ptxqtop_terminate:1
                                                                                               Top of the Periodic Transmit Request Queue
                                                                                                +-
                                                                                              • bit 24 - Terminate (last entry for the selected channel)
                                                                                              • bits 26:25 - Token Type
                                                                                                  +-
                                                                                                • 2'b00 - Zero length
                                                                                                • 2'b01 - Ping
                                                                                                • 2'b10 - Disable
                                                                                                +-
                                                                                              • bits 30:27 - Channel Number
                                                                                              • bit 31 - Odd/even microframe.
                                                                                              +-
                                                                                                 unsigned   ptxqtop_token:2
                                                                                                 unsigned   ptxqtop_chnum:4
                                                                                                 unsigned   ptxqtop_odd:1
                                                                                              } b
                                                                                               register bits
                                                                                              +-

                                                                                              Detailed Description

                                                                                              +- +-

                                                                                              +- +-

                                                                                              +-Definition at line 1711 of file dwc_otg_regs.h.

                                                                                              The documentation for this union was generated from the following file: +-
                                                                                              Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.4.7
                                                                                              +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/unionhwcfg1__data.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/unionhwcfg1__data.html 2013-07-26 19:31:22.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/unionhwcfg1__data.html 2013-07-26 19:34:43.000000000 +0000 +@@ -2,22 +2,10 @@ + + DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: hwcfg1_data Union Reference + +- + +- +-
                                                                                              +-
                                                                                              +-
                                                                                              +-
                                                                                              +-

                                                                                              hwcfg1_data Union Reference

                                                                                              This union represents the bit fields in the User HW Config1 Register. ++ ++
                                                                                              Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                              ++

                                                                                              hwcfg1_data Union Reference

                                                                                              This union represents the bit fields in the User HW Config1 Register. + More... +

                                                                                              + #include <dwc_otg_regs.h> +@@ -25,46 +13,46 @@ + + + +- ++ + + +- + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + + +

                                                                                              Data Fields

                                                                                              +-uint32_t d32
                                                                                              ++uint32_t d32
                                                                                               raw register data
                                                                                              ++
                                                                                              + struct {
                                                                                                 unsigned   ep_dir0:2
                                                                                                 unsigned   ep_dir0:2
                                                                                                 unsigned   ep_dir1:2
                                                                                                 unsigned   ep_dir1:2
                                                                                                 unsigned   ep_dir2:2
                                                                                                 unsigned   ep_dir2:2
                                                                                                 unsigned   ep_dir3:2
                                                                                                 unsigned   ep_dir3:2
                                                                                                 unsigned   ep_dir4:2
                                                                                                 unsigned   ep_dir4:2
                                                                                                 unsigned   ep_dir5:2
                                                                                                 unsigned   ep_dir5:2
                                                                                                 unsigned   ep_dir6:2
                                                                                                 unsigned   ep_dir6:2
                                                                                                 unsigned   ep_dir7:2
                                                                                                 unsigned   ep_dir7:2
                                                                                                 unsigned   ep_dir8:2
                                                                                                 unsigned   ep_dir8:2
                                                                                                 unsigned   ep_dir9:2
                                                                                                 unsigned   ep_dir9:2
                                                                                                 unsigned   ep_dir10:2
                                                                                                 unsigned   ep_dir10:2
                                                                                                 unsigned   ep_dir11:2
                                                                                                 unsigned   ep_dir11:2
                                                                                                 unsigned   ep_dir12:2
                                                                                                 unsigned   ep_dir12:2
                                                                                                 unsigned   ep_dir13:2
                                                                                                 unsigned   ep_dir13:2
                                                                                                 unsigned   ep_dir14:2
                                                                                                 unsigned   ep_dir14:2
                                                                                                 unsigned   ep_dir15:2
                                                                                                 unsigned   ep_dir15:2
                                                                                              } b
                                                                                              } b
                                                                                               register bits
                                                                                              +@@ -75,10 +63,10 @@ +

                                                                                              + +

                                                                                              +-Definition at line 735 of file dwc_otg_regs.h.

                                                                                              The documentation for this union was generated from the following file:
                                                                                                ++Definition at line 724 of file dwc_otg_regs.h.
                                                                                                The documentation for this union was generated from the following file: +-
                                                                                                Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++
                                                                                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
                                                                                                ++doxygen 1.3.9.1
                                                                                                + + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/unionhwcfg2__data.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/unionhwcfg2__data.html 2013-07-26 19:31:22.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/unionhwcfg2__data.html 2013-07-26 19:34:43.000000000 +0000 +@@ -2,22 +2,10 @@ + + DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: hwcfg2_data Union Reference + +- + +- +-
                                                                                                +-
                                                                                                +-
                                                                                                +-
                                                                                                +-

                                                                                                hwcfg2_data Union Reference

                                                                                                This union represents the bit fields in the User HW Config2 Register. ++ ++
                                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                                ++

                                                                                                hwcfg2_data Union Reference

                                                                                                This union represents the bit fields in the User HW Config2 Register. + More... +

                                                                                                + #include <dwc_otg_regs.h> +@@ -25,44 +13,44 @@ + + + +- ++ + + +- + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + + +

                                                                                                Data Fields

                                                                                                +-uint32_t d32
                                                                                                ++uint32_t d32
                                                                                                 raw register data
                                                                                                ++
                                                                                                + struct {
                                                                                                   unsigned   op_mode:3
                                                                                                   unsigned   op_mode:3
                                                                                                   unsigned   architecture:2
                                                                                                   unsigned   architecture:2
                                                                                                   unsigned   point2point:1
                                                                                                   unsigned   point2point:1
                                                                                                   unsigned   hs_phy_type:2
                                                                                                   unsigned   hs_phy_type:2
                                                                                                   unsigned   fs_phy_type:2
                                                                                                   unsigned   fs_phy_type:2
                                                                                                   unsigned   num_dev_ep:4
                                                                                                   unsigned   num_dev_ep:4
                                                                                                   unsigned   num_host_chan:4
                                                                                                   unsigned   num_host_chan:4
                                                                                                   unsigned   perio_ep_supported:1
                                                                                                   unsigned   perio_ep_supported:1
                                                                                                   unsigned   dynamic_fifo:1
                                                                                                   unsigned   dynamic_fifo:1
                                                                                                   unsigned   multi_proc_int:1
                                                                                                   unsigned   multi_proc_int:1
                                                                                                   unsigned   reserved21:1
                                                                                                   unsigned   reserved21:1
                                                                                                   unsigned   nonperio_tx_q_depth:2
                                                                                                   unsigned   nonperio_tx_q_depth:2
                                                                                                   unsigned   host_perio_tx_q_depth:2
                                                                                                   unsigned   host_perio_tx_q_depth:2
                                                                                                   unsigned   dev_token_q_depth:5
                                                                                                   unsigned   dev_token_q_depth:5
                                                                                                   unsigned   reserved31:1
                                                                                                   unsigned   otg_enable_ic_usb:1
                                                                                                } b
                                                                                                } b
                                                                                                 register bits
                                                                                                +@@ -73,10 +61,10 @@ +

                                                                                                + +

                                                                                                +-Definition at line 764 of file dwc_otg_regs.h.

                                                                                                The documentation for this union was generated from the following file:
                                                                                                  ++Definition at line 753 of file dwc_otg_regs.h.
                                                                                                  The documentation for this union was generated from the following file: +-
                                                                                                  Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++
                                                                                                  Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
                                                                                                  ++doxygen 1.3.9.1
                                                                                                  + + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/unionhwcfg3__data.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/unionhwcfg3__data.html 2013-07-26 19:31:22.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/unionhwcfg3__data.html 2013-07-26 19:34:43.000000000 +0000 +@@ -2,22 +2,10 @@ + + DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: hwcfg3_data Union Reference + +- + +- +-
                                                                                                  +-
                                                                                                  +-
                                                                                                  +-
                                                                                                  +-

                                                                                                  hwcfg3_data Union Reference

                                                                                                  This union represents the bit fields in the User HW Config3 Register. ++ ++
                                                                                                  Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                                  ++

                                                                                                  hwcfg3_data Union Reference

                                                                                                  This union represents the bit fields in the User HW Config3 Register. + More... +

                                                                                                  + #include <dwc_otg_regs.h> +@@ -25,38 +13,38 @@ + + + +- ++ + + +- + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + + +

                                                                                                  Data Fields

                                                                                                  +-uint32_t d32
                                                                                                  ++uint32_t d32
                                                                                                   raw register data
                                                                                                  ++
                                                                                                  + struct {
                                                                                                     unsigned   xfer_size_cntr_width:4
                                                                                                     unsigned   xfer_size_cntr_width:4
                                                                                                     unsigned   packet_size_cntr_width:3
                                                                                                     unsigned   packet_size_cntr_width:3
                                                                                                     unsigned   otg_func:1
                                                                                                     unsigned   otg_func:1
                                                                                                     unsigned   i2c:1
                                                                                                     unsigned   i2c:1
                                                                                                     unsigned   vendor_ctrl_if:1
                                                                                                     unsigned   vendor_ctrl_if:1
                                                                                                     unsigned   optional_features:1
                                                                                                     unsigned   optional_features:1
                                                                                                     unsigned   synch_reset_type:1
                                                                                                     unsigned   synch_reset_type:1
                                                                                                     unsigned   otg_enable_ic_usb:1
                                                                                                     unsigned   adp_supp:1
                                                                                                     unsigned   otg_enable_hsic:1
                                                                                                     unsigned   otg_enable_hsic:1
                                                                                                     unsigned   reserved14:1
                                                                                                     unsigned   bc_support:1
                                                                                                     unsigned   otg_lpm_en:1
                                                                                                     unsigned   otg_lpm_en:1
                                                                                                     unsigned   dfifo_depth:16
                                                                                                     unsigned   dfifo_depth:16
                                                                                                  } b
                                                                                                  } b
                                                                                                   register bits
                                                                                                  +@@ -67,10 +55,10 @@ +

                                                                                                  + +

                                                                                                  +-Definition at line 806 of file dwc_otg_regs.h.

                                                                                                  The documentation for this union was generated from the following file:
                                                                                                    ++Definition at line 795 of file dwc_otg_regs.h.
                                                                                                    The documentation for this union was generated from the following file: +-
                                                                                                    Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++
                                                                                                    Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
                                                                                                    ++doxygen 1.3.9.1
                                                                                                    + + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/unionhwcfg4__data.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/unionhwcfg4__data.html 2013-07-26 19:31:22.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/unionhwcfg4__data.html 2013-07-26 19:34:43.000000000 +0000 +@@ -2,22 +2,10 @@ + + DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: hwcfg4_data Union Reference + +- + +- +-
                                                                                                    +-
                                                                                                    +-
                                                                                                    +-
                                                                                                    +-

                                                                                                    hwcfg4_data Union Reference

                                                                                                    This union represents the bit fields in the User HW Config4 Register. ++ ++
                                                                                                    Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                                    ++

                                                                                                    hwcfg4_data Union Reference

                                                                                                    This union represents the bit fields in the User HW Config4 Register. + More... +

                                                                                                    + #include <dwc_otg_regs.h> +@@ -25,42 +13,46 @@ + + + +- ++ + + +- + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ + +- ++ ++ ++ ++ ++ + + +

                                                                                                    Data Fields

                                                                                                    +-uint32_t d32
                                                                                                    ++uint32_t d32
                                                                                                     raw register data
                                                                                                    ++
                                                                                                    + struct {
                                                                                                       unsigned   num_dev_perio_in_ep:4
                                                                                                       unsigned   num_dev_perio_in_ep:4
                                                                                                       unsigned   power_optimiz:1
                                                                                                       unsigned   power_optimiz:1
                                                                                                       unsigned   min_ahb_freq:9
                                                                                                       unsigned   min_ahb_freq:1
                                                                                                       unsigned   utmi_phy_data_width:2
                                                                                                       unsigned   part_power_down:1
                                                                                                       unsigned   num_dev_mode_ctrl_ep:4
                                                                                                       unsigned   reserved:7
                                                                                                       unsigned   iddig_filt_en:1
                                                                                                       unsigned   utmi_phy_data_width:2
                                                                                                       unsigned   vbus_valid_filt_en:1
                                                                                                       unsigned   num_dev_mode_ctrl_ep:4
                                                                                                       unsigned   a_valid_filt_en:1
                                                                                                       unsigned   iddig_filt_en:1
                                                                                                       unsigned   b_valid_filt_en:1
                                                                                                       unsigned   vbus_valid_filt_en:1
                                                                                                       unsigned   session_end_filt_en:1
                                                                                                       unsigned   a_valid_filt_en:1
                                                                                                       unsigned   ded_fifo_en:1
                                                                                                       unsigned   b_valid_filt_en:1
                                                                                                       unsigned   num_in_eps:4
                                                                                                       unsigned   session_end_filt_en:1
                                                                                                       unsigned   desc_dma:1
                                                                                                       unsigned   ded_fifo_en:1
                                                                                                       unsigned   desc_dma_dyn:1
                                                                                                       unsigned   num_in_eps:4
                                                                                                    } b
                                                                                                       unsigned   desc_dma:1
                                                                                                       unsigned   desc_dma_dyn:1
                                                                                                    } b
                                                                                                     register bits
                                                                                                    +@@ -71,10 +63,10 @@ +

                                                                                                    + +

                                                                                                    +-Definition at line 832 of file dwc_otg_regs.h.

                                                                                                    The documentation for this union was generated from the following file:
                                                                                                      ++Definition at line 821 of file dwc_otg_regs.h.
                                                                                                      The documentation for this union was generated from the following file: +-
                                                                                                      Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++
                                                                                                      Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
                                                                                                      ++doxygen 1.3.9.1
                                                                                                      + + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/unionpcgcctl__data.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/unionpcgcctl__data.html 2013-07-26 19:31:22.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/unionpcgcctl__data.html 2013-07-26 19:34:43.000000000 +0000 +@@ -2,22 +2,10 @@ + + DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: pcgcctl_data Union Reference + +- + +- +-
                                                                                                      +-
                                                                                                      +-
                                                                                                      +-
                                                                                                      +-

                                                                                                      pcgcctl_data Union Reference

                                                                                                      This union represents the bit fields in the Power and Clock Gating Control Register. ++ ++
                                                                                                      Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                                      ++

                                                                                                      pcgcctl_data Union Reference

                                                                                                      This union represents the bit fields in the Power and Clock Gating Control Register. + More... +

                                                                                                      + #include <dwc_otg_regs.h> +@@ -25,40 +13,62 @@ + + + +- ++ + + +- + +- ++ + + +- ++ + + +- ++ + + +- ++ + + +- ++ + +- +- ++ ++ + + +- ++ + + +- ++ + + +- ++ + +- ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ + + +

                                                                                                      Data Fields

                                                                                                      +-uint32_t d32
                                                                                                      ++uint32_t d32
                                                                                                       raw register data
                                                                                                      ++
                                                                                                      + struct {
                                                                                                         unsigned   stoppclk:1
                                                                                                         unsigned   stoppclk:1
                                                                                                       Stop Pclk.
                                                                                                         unsigned   gatehclk:1
                                                                                                         unsigned   gatehclk:1
                                                                                                       Gate Hclk.
                                                                                                         unsigned   pwrclmp:1
                                                                                                         unsigned   pwrclmp:1
                                                                                                       Power Clamp.
                                                                                                         unsigned   rstpdwnmodule:1
                                                                                                         unsigned   rstpdwnmodule:1
                                                                                                       Reset Power Down Modules.
                                                                                                         unsigned   physuspended:1
                                                                                                         unsigned   reserved:1
                                                                                                       PHY Suspended.
                                                                                                         unsigned   enbl_sleep_gating:1
                                                                                                       Reserved.
                                                                                                         unsigned   enbl_sleep_gating:1
                                                                                                       Enable Sleep Clock Gating (Enbl_L1Gating).
                                                                                                         unsigned   phy_in_sleep:1
                                                                                                         unsigned   phy_in_sleep:1
                                                                                                       PHY In Sleep (PhySleep).
                                                                                                         unsigned   deep_sleep:1
                                                                                                         unsigned   deep_sleep:1
                                                                                                       Deep Sleep.
                                                                                                         unsigned   reserved31_8:24
                                                                                                         unsigned   resetaftsusp:1
                                                                                                      } b
                                                                                                         unsigned   restoremode:1
                                                                                                         unsigned   reserved10_12:3
                                                                                                         unsigned   ess_reg_restored:1
                                                                                                         unsigned   prt_clk_sel:2
                                                                                                         unsigned   port_power:1
                                                                                                         unsigned   max_xcvrselect:2
                                                                                                         unsigned   max_termsel:1
                                                                                                         unsigned   mac_dev_addr:7
                                                                                                         unsigned   p2hd_dev_enum_spd:2
                                                                                                         unsigned   p2hd_prt_spd:2
                                                                                                         unsigned   if_dev_mode:1
                                                                                                      } b
                                                                                                       register bits
                                                                                                      +@@ -69,10 +79,10 @@ +

                                                                                                      + +

                                                                                                      +-Definition at line 2210 of file dwc_otg_regs.h.

                                                                                                      The documentation for this union was generated from the following file:
                                                                                                        ++Definition at line 2427 of file dwc_otg_regs.h.
                                                                                                        The documentation for this union was generated from the following file: +-
                                                                                                        Generated on Tue May 5 02:22:49 2009 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  ++
                                                                                                        Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  + +-doxygen 1.4.7
                                                                                                        ++doxygen 1.3.9.1
                                                                                                        + + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_adp.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_adp.c 2013-07-26 19:34:43.000000000 +0000 +@@ -0,0 +1,854 @@ ++/* ========================================================================== ++ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_adp.c $ ++ * $Revision: #12 $ ++ * $Date: 2011/10/26 $ ++ * $Change: 1873028 $ ++ * ++ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, ++ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless ++ * otherwise expressly agreed to in writing between Synopsys and you. ++ * ++ * The Software IS NOT an item of Licensed Software or Licensed Product under ++ * any End User Software License Agreement or Agreement for Licensed Product ++ * with Synopsys or any supplement thereto. You are permitted to use and ++ * redistribute this Software in source and binary forms, with or without ++ * modification, provided that redistributions of source code must retain this ++ * notice. You may not view, use, disclose, copy or distribute this file or ++ * any information contained herein except pursuant to this license grant from ++ * Synopsys. If you do not agree with this notice, including the disclaimer ++ * below, then you are not authorized to use the Software. ++ * ++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, ++ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR ++ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER ++ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY ++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH ++ * DAMAGE. ++ * ========================================================================== */ ++ ++#include "dwc_os.h" ++#include "dwc_otg_regs.h" ++#include "dwc_otg_cil.h" ++#include "dwc_otg_adp.h" ++ ++/** @file ++ * ++ * This file contains the most of the Attach Detect Protocol implementation for ++ * the driver to support OTG Rev2.0. ++ * ++ */ ++ ++void dwc_otg_adp_write_reg(dwc_otg_core_if_t * core_if, uint32_t value) ++{ ++ adpctl_data_t adpctl; ++ ++ adpctl.d32 = value; ++ adpctl.b.ar = 0x2; ++ ++ DWC_WRITE_REG32(&core_if->core_global_regs->adpctl, adpctl.d32); ++ ++ while (adpctl.b.ar) { ++ adpctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->adpctl); ++ } ++ ++} ++ ++/** ++ * Function is called to read ADP registers ++ */ ++uint32_t dwc_otg_adp_read_reg(dwc_otg_core_if_t * core_if) ++{ ++ adpctl_data_t adpctl; ++ ++ adpctl.d32 = 0; ++ adpctl.b.ar = 0x1; ++ ++ DWC_WRITE_REG32(&core_if->core_global_regs->adpctl, adpctl.d32); ++ ++ while (adpctl.b.ar) { ++ adpctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->adpctl); ++ } ++ ++ return adpctl.d32; ++} ++ ++/** ++ * Function is called to read ADPCTL register and filter Write-clear bits ++ */ ++uint32_t dwc_otg_adp_read_reg_filter(dwc_otg_core_if_t * core_if) ++{ ++ adpctl_data_t adpctl; ++ ++ adpctl.d32 = dwc_otg_adp_read_reg(core_if); ++ adpctl.b.adp_tmout_int = 0; ++ adpctl.b.adp_prb_int = 0; ++ adpctl.b.adp_tmout_int = 0; ++ ++ return adpctl.d32; ++} ++ ++/** ++ * Function is called to write ADP registers ++ */ ++void dwc_otg_adp_modify_reg(dwc_otg_core_if_t * core_if, uint32_t clr, ++ uint32_t set) ++{ ++ dwc_otg_adp_write_reg(core_if, ++ (dwc_otg_adp_read_reg(core_if) & (~clr)) | set); ++} ++ ++static void adp_sense_timeout(void *ptr) ++{ ++ dwc_otg_core_if_t *core_if = (dwc_otg_core_if_t *) ptr; ++ core_if->adp.sense_timer_started = 0; ++ DWC_PRINTF("ADP SENSE TIMEOUT\n"); ++ if (core_if->adp_enable) { ++ dwc_otg_adp_sense_stop(core_if); ++ dwc_otg_adp_probe_start(core_if); ++ } ++} ++ ++/** ++ * This function is called when the ADP vbus timer expires. Timeout is 1.1s. ++ */ ++static void adp_vbuson_timeout(void *ptr) ++{ ++ gpwrdn_data_t gpwrdn; ++ dwc_otg_core_if_t *core_if = (dwc_otg_core_if_t *) ptr; ++ hprt0_data_t hprt0 = {.d32 = 0 }; ++ pcgcctl_data_t pcgcctl = {.d32 = 0 }; ++ DWC_PRINTF("%s: 1.1 seconds expire after turning on VBUS\n",__FUNCTION__); ++ if (core_if) { ++ core_if->adp.vbuson_timer_started = 0; ++ /* Turn off vbus */ ++ hprt0.b.prtpwr = 1; ++ DWC_MODIFY_REG32(core_if->host_if->hprt0, hprt0.d32, 0); ++ gpwrdn.d32 = 0; ++ ++ /* Power off the core */ ++ if (core_if->power_down == 2) { ++ /* Enable Wakeup Logic */ ++// gpwrdn.b.wkupactiv = 1; ++ gpwrdn.b.pmuactv = 0; ++ gpwrdn.b.pwrdnrstn = 1; ++ gpwrdn.b.pwrdnclmp = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, ++ gpwrdn.d32); ++ ++ /* Suspend the Phy Clock */ ++ pcgcctl.b.stoppclk = 1; ++ DWC_MODIFY_REG32(core_if->pcgcctl, 0, pcgcctl.d32); ++ ++ /* Switch on VDD */ ++// gpwrdn.b.wkupactiv = 1; ++ gpwrdn.b.pmuactv = 1; ++ gpwrdn.b.pwrdnrstn = 1; ++ gpwrdn.b.pwrdnclmp = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, ++ gpwrdn.d32); ++ } else { ++ /* Enable Power Down Logic */ ++ gpwrdn.b.pmuintsel = 1; ++ gpwrdn.b.pmuactv = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32); ++ } ++ ++ /* Power off the core */ ++ if (core_if->power_down == 2) { ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pwrdnswtch = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, ++ gpwrdn.d32, 0); ++ } ++ ++ /* Unmask SRP detected interrupt from Power Down Logic */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.srp_det_msk = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32); ++ ++ dwc_otg_adp_probe_start(core_if); ++ dwc_otg_dump_global_registers(core_if); ++ dwc_otg_dump_host_registers(core_if); ++ } ++ ++} ++ ++/** ++ * Start the ADP Initial Probe timer to detect if Port Connected interrupt is ++ * not asserted within 1.1 seconds. ++ * ++ * @param core_if the pointer to core_if strucure. ++ */ ++void dwc_otg_adp_vbuson_timer_start(dwc_otg_core_if_t * core_if) ++{ ++ core_if->adp.vbuson_timer_started = 1; ++ if (core_if->adp.vbuson_timer) ++ { ++ DWC_PRINTF("SCHEDULING VBUSON TIMER\n"); ++ /* 1.1 secs + 60ms necessary for cil_hcd_start*/ ++ DWC_TIMER_SCHEDULE(core_if->adp.vbuson_timer, 1160); ++ } else { ++ DWC_WARN("VBUSON_TIMER = %p\n",core_if->adp.vbuson_timer); ++ } ++} ++ ++#if 0 ++/** ++ * Masks all DWC OTG core interrupts ++ * ++ */ ++static void mask_all_interrupts(dwc_otg_core_if_t * core_if) ++{ ++ int i; ++ gahbcfg_data_t ahbcfg = {.d32 = 0 }; ++ ++ /* Mask Host Interrupts */ ++ ++ /* Clear and disable HCINTs */ ++ for (i = 0; i < core_if->core_params->host_channels; i++) { ++ DWC_WRITE_REG32(&core_if->host_if->hc_regs[i]->hcintmsk, 0); ++ DWC_WRITE_REG32(&core_if->host_if->hc_regs[i]->hcint, 0xFFFFFFFF); ++ ++ } ++ ++ /* Clear and disable HAINT */ ++ DWC_WRITE_REG32(&core_if->host_if->host_global_regs->haintmsk, 0x0000); ++ DWC_WRITE_REG32(&core_if->host_if->host_global_regs->haint, 0xFFFFFFFF); ++ ++ /* Mask Device Interrupts */ ++ if (!core_if->multiproc_int_enable) { ++ /* Clear and disable IN Endpoint interrupts */ ++ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->diepmsk, 0); ++ for (i = 0; i <= core_if->dev_if->num_in_eps; i++) { ++ DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[i]-> ++ diepint, 0xFFFFFFFF); ++ } ++ ++ /* Clear and disable OUT Endpoint interrupts */ ++ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->doepmsk, 0); ++ for (i = 0; i <= core_if->dev_if->num_out_eps; i++) { ++ DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[i]-> ++ doepint, 0xFFFFFFFF); ++ } ++ ++ /* Clear and disable DAINT */ ++ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->daint, ++ 0xFFFFFFFF); ++ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->daintmsk, 0); ++ } else { ++ for (i = 0; i < core_if->dev_if->num_in_eps; ++i) { ++ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs-> ++ diepeachintmsk[i], 0); ++ DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[i]-> ++ diepint, 0xFFFFFFFF); ++ } ++ ++ for (i = 0; i < core_if->dev_if->num_out_eps; ++i) { ++ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs-> ++ doepeachintmsk[i], 0); ++ DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[i]-> ++ doepint, 0xFFFFFFFF); ++ } ++ ++ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->deachintmsk, ++ 0); ++ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->deachint, ++ 0xFFFFFFFF); ++ ++ } ++ ++ /* Disable interrupts */ ++ ahbcfg.b.glblintrmsk = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gahbcfg, ahbcfg.d32, 0); ++ ++ /* Disable all interrupts. */ ++ DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, 0); ++ ++ /* Clear any pending interrupts */ ++ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF); ++ ++ /* Clear any pending OTG Interrupts */ ++ DWC_WRITE_REG32(&core_if->core_global_regs->gotgint, 0xFFFFFFFF); ++} ++ ++/** ++ * Unmask Port Connection Detected interrupt ++ * ++ */ ++static void unmask_conn_det_intr(dwc_otg_core_if_t * core_if) ++{ ++ gintmsk_data_t gintmsk = {.d32 = 0,.b.portintr = 1 }; ++ ++ DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, gintmsk.d32); ++} ++#endif ++ ++/** ++ * Starts the ADP Probing ++ * ++ * @param core_if the pointer to core_if structure. ++ */ ++uint32_t dwc_otg_adp_probe_start(dwc_otg_core_if_t * core_if) ++{ ++ ++ adpctl_data_t adpctl = {.d32 = 0}; ++ gpwrdn_data_t gpwrdn; ++#if 0 ++ adpctl_data_t adpctl_int = {.d32 = 0, .b.adp_prb_int = 1, ++ .b.adp_sns_int = 1, b.adp_tmout_int}; ++#endif ++ dwc_otg_disable_global_interrupts(core_if); ++ DWC_PRINTF("ADP Probe Start\n"); ++ core_if->adp.probe_enabled = 1; ++ ++ adpctl.b.adpres = 1; ++ dwc_otg_adp_write_reg(core_if, adpctl.d32); ++ ++ while (adpctl.b.adpres) { ++ adpctl.d32 = dwc_otg_adp_read_reg(core_if); ++ } ++ ++ adpctl.d32 = 0; ++ gpwrdn.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn); ++ ++ /* In Host mode unmask SRP detected interrupt */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.sts_chngint_msk = 1; ++ if (!gpwrdn.b.idsts) { ++ gpwrdn.b.srp_det_msk = 1; ++ } ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32); ++ ++ adpctl.b.adp_tmout_int_msk = 1; ++ adpctl.b.adp_prb_int_msk = 1; ++ adpctl.b.prb_dschg = 1; ++ adpctl.b.prb_delta = 1; ++ adpctl.b.prb_per = 1; ++ adpctl.b.adpen = 1; ++ adpctl.b.enaprb = 1; ++ ++ dwc_otg_adp_write_reg(core_if, adpctl.d32); ++ DWC_PRINTF("ADP Probe Finish\n"); ++ return 0; ++} ++ ++/** ++ * Starts the ADP Sense timer to detect if ADP Sense interrupt is not asserted ++ * within 3 seconds. ++ * ++ * @param core_if the pointer to core_if strucure. ++ */ ++void dwc_otg_adp_sense_timer_start(dwc_otg_core_if_t * core_if) ++{ ++ core_if->adp.sense_timer_started = 1; ++ DWC_TIMER_SCHEDULE(core_if->adp.sense_timer, 3000 /* 3 secs */ ); ++} ++ ++/** ++ * Starts the ADP Sense ++ * ++ * @param core_if the pointer to core_if strucure. ++ */ ++uint32_t dwc_otg_adp_sense_start(dwc_otg_core_if_t * core_if) ++{ ++ adpctl_data_t adpctl; ++ ++ DWC_PRINTF("ADP Sense Start\n"); ++ ++ /* Unmask ADP sense interrupt and mask all other from the core */ ++ adpctl.d32 = dwc_otg_adp_read_reg_filter(core_if); ++ adpctl.b.adp_sns_int_msk = 1; ++ dwc_otg_adp_write_reg(core_if, adpctl.d32); ++ dwc_otg_disable_global_interrupts(core_if); // vahrama ++ ++ /* Set ADP reset bit*/ ++ adpctl.d32 = dwc_otg_adp_read_reg_filter(core_if); ++ adpctl.b.adpres = 1; ++ dwc_otg_adp_write_reg(core_if, adpctl.d32); ++ ++ while (adpctl.b.adpres) { ++ adpctl.d32 = dwc_otg_adp_read_reg(core_if); ++ } ++ ++ adpctl.b.adpres = 0; ++ adpctl.b.adpen = 1; ++ adpctl.b.enasns = 1; ++ dwc_otg_adp_write_reg(core_if, adpctl.d32); ++ ++ dwc_otg_adp_sense_timer_start(core_if); ++ ++ return 0; ++} ++ ++/** ++ * Stops the ADP Probing ++ * ++ * @param core_if the pointer to core_if strucure. ++ */ ++uint32_t dwc_otg_adp_probe_stop(dwc_otg_core_if_t * core_if) ++{ ++ ++ adpctl_data_t adpctl; ++ DWC_PRINTF("Stop ADP probe\n"); ++ core_if->adp.probe_enabled = 0; ++ core_if->adp.probe_counter = 0; ++ adpctl.d32 = dwc_otg_adp_read_reg(core_if); ++ ++ adpctl.b.adpen = 0; ++ adpctl.b.adp_prb_int = 1; ++ adpctl.b.adp_tmout_int = 1; ++ adpctl.b.adp_sns_int = 1; ++ dwc_otg_adp_write_reg(core_if, adpctl.d32); ++ ++ return 0; ++} ++ ++/** ++ * Stops the ADP Sensing ++ * ++ * @param core_if the pointer to core_if strucure. ++ */ ++uint32_t dwc_otg_adp_sense_stop(dwc_otg_core_if_t * core_if) ++{ ++ adpctl_data_t adpctl; ++ ++ core_if->adp.sense_enabled = 0; ++ ++ adpctl.d32 = dwc_otg_adp_read_reg_filter(core_if); ++ adpctl.b.enasns = 0; ++ adpctl.b.adp_sns_int = 1; ++ dwc_otg_adp_write_reg(core_if, adpctl.d32); ++ ++ return 0; ++} ++ ++/** ++ * Called to turn on the VBUS after initial ADP probe in host mode. ++ * If port power was already enabled in cil_hcd_start function then ++ * only schedule a timer. ++ * ++ * @param core_if the pointer to core_if structure. ++ */ ++void dwc_otg_adp_turnon_vbus(dwc_otg_core_if_t * core_if) ++{ ++ hprt0_data_t hprt0 = {.d32 = 0 }; ++ hprt0.d32 = dwc_otg_read_hprt0(core_if); ++ DWC_PRINTF("Turn on VBUS for 1.1s, port power is %d\n", hprt0.b.prtpwr); ++ ++ if (hprt0.b.prtpwr == 0) { ++ hprt0.b.prtpwr = 1; ++ //DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32); ++ } ++ ++ dwc_otg_adp_vbuson_timer_start(core_if); ++} ++ ++/** ++ * Called right after driver is loaded ++ * to perform initial actions for ADP ++ * ++ * @param core_if the pointer to core_if structure. ++ * @param is_host - flag for current mode of operation either from GINTSTS or GPWRDN ++ */ ++void dwc_otg_adp_start(dwc_otg_core_if_t * core_if, uint8_t is_host) ++{ ++ gpwrdn_data_t gpwrdn; ++ ++ DWC_PRINTF("ADP Initial Start\n"); ++ core_if->adp.adp_started = 1; ++ ++ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF); ++ dwc_otg_disable_global_interrupts(core_if); ++ if (is_host) { ++ DWC_PRINTF("HOST MODE\n"); ++ /* Enable Power Down Logic Interrupt*/ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pmuintsel = 1; ++ gpwrdn.b.pmuactv = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32); ++ /* Initialize first ADP probe to obtain Ramp Time value */ ++ core_if->adp.initial_probe = 1; ++ dwc_otg_adp_probe_start(core_if); ++ } else { ++ gotgctl_data_t gotgctl; ++ gotgctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->gotgctl); ++ DWC_PRINTF("DEVICE MODE\n"); ++ if (gotgctl.b.bsesvld == 0) { ++ /* Enable Power Down Logic Interrupt*/ ++ gpwrdn.d32 = 0; ++ DWC_PRINTF("VBUS is not valid - start ADP probe\n"); ++ gpwrdn.b.pmuintsel = 1; ++ gpwrdn.b.pmuactv = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32); ++ core_if->adp.initial_probe = 1; ++ dwc_otg_adp_probe_start(core_if); ++ } else { ++ DWC_PRINTF("VBUS is valid - initialize core as a Device\n"); ++ core_if->op_state = B_PERIPHERAL; ++ dwc_otg_core_init(core_if); ++ dwc_otg_enable_global_interrupts(core_if); ++ cil_pcd_start(core_if); ++ dwc_otg_dump_global_registers(core_if); ++ dwc_otg_dump_dev_registers(core_if); ++ } ++ } ++} ++ ++void dwc_otg_adp_init(dwc_otg_core_if_t * core_if) ++{ ++ core_if->adp.adp_started = 0; ++ core_if->adp.initial_probe = 0; ++ core_if->adp.probe_timer_values[0] = -1; ++ core_if->adp.probe_timer_values[1] = -1; ++ core_if->adp.probe_enabled = 0; ++ core_if->adp.sense_enabled = 0; ++ core_if->adp.sense_timer_started = 0; ++ core_if->adp.vbuson_timer_started = 0; ++ core_if->adp.probe_counter = 0; ++ core_if->adp.gpwrdn = 0; ++ core_if->adp.attached = DWC_OTG_ADP_UNKOWN; ++ /* Initialize timers */ ++ core_if->adp.sense_timer = ++ DWC_TIMER_ALLOC("ADP SENSE TIMER", adp_sense_timeout, core_if); ++ core_if->adp.vbuson_timer = ++ DWC_TIMER_ALLOC("ADP VBUS ON TIMER", adp_vbuson_timeout, core_if); ++ if (!core_if->adp.sense_timer || !core_if->adp.vbuson_timer) ++ { ++ DWC_ERROR("Could not allocate memory for ADP timers\n"); ++ } ++} ++ ++void dwc_otg_adp_remove(dwc_otg_core_if_t * core_if) ++{ ++ gpwrdn_data_t gpwrdn = { .d32 = 0 }; ++ gpwrdn.b.pmuintsel = 1; ++ gpwrdn.b.pmuactv = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ ++ if (core_if->adp.probe_enabled) ++ dwc_otg_adp_probe_stop(core_if); ++ if (core_if->adp.sense_enabled) ++ dwc_otg_adp_sense_stop(core_if); ++ if (core_if->adp.sense_timer_started) ++ DWC_TIMER_CANCEL(core_if->adp.sense_timer); ++ if (core_if->adp.vbuson_timer_started) ++ DWC_TIMER_CANCEL(core_if->adp.vbuson_timer); ++ DWC_TIMER_FREE(core_if->adp.sense_timer); ++ DWC_TIMER_FREE(core_if->adp.vbuson_timer); ++} ++ ++///////////////////////////////////////////////////////////////////// ++////////////// ADP Interrupt Handlers /////////////////////////////// ++///////////////////////////////////////////////////////////////////// ++/** ++ * This function sets Ramp Timer values ++ */ ++static uint32_t set_timer_value(dwc_otg_core_if_t * core_if, uint32_t val) ++{ ++ if (core_if->adp.probe_timer_values[0] == -1) { ++ core_if->adp.probe_timer_values[0] = val; ++ core_if->adp.probe_timer_values[1] = -1; ++ return 1; ++ } else { ++ core_if->adp.probe_timer_values[1] = ++ core_if->adp.probe_timer_values[0]; ++ core_if->adp.probe_timer_values[0] = val; ++ return 0; ++ } ++} ++ ++/** ++ * This function compares Ramp Timer values ++ */ ++static uint32_t compare_timer_values(dwc_otg_core_if_t * core_if) ++{ ++ uint32_t diff; ++ if (core_if->adp.probe_timer_values[0]>=core_if->adp.probe_timer_values[1]) ++ diff = core_if->adp.probe_timer_values[0]-core_if->adp.probe_timer_values[1]; ++ else ++ diff = core_if->adp.probe_timer_values[1]-core_if->adp.probe_timer_values[0]; ++ if(diff < 2) { ++ return 0; ++ } else { ++ return 1; ++ } ++} ++ ++/** ++ * This function handles ADP Probe Interrupts ++ */ ++static int32_t dwc_otg_adp_handle_prb_intr(dwc_otg_core_if_t * core_if, ++ uint32_t val) ++{ ++ adpctl_data_t adpctl = {.d32 = 0 }; ++ gpwrdn_data_t gpwrdn, temp; ++ adpctl.d32 = val; ++ ++ temp.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn); ++ core_if->adp.probe_counter++; ++ core_if->adp.gpwrdn = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn); ++ if (adpctl.b.rtim == 0 && !temp.b.idsts){ ++ DWC_PRINTF("RTIM value is 0\n"); ++ goto exit; ++ } ++ if (set_timer_value(core_if, adpctl.b.rtim) && ++ core_if->adp.initial_probe) { ++ core_if->adp.initial_probe = 0; ++ dwc_otg_adp_probe_stop(core_if); ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pmuactv = 1; ++ gpwrdn.b.pmuintsel = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF); ++ ++ /* check which value is for device mode and which for Host mode */ ++ if (!temp.b.idsts) { /* considered host mode value is 0 */ ++ /* ++ * Turn on VBUS after initial ADP probe. ++ */ ++ core_if->op_state = A_HOST; ++ dwc_otg_enable_global_interrupts(core_if); ++ DWC_SPINUNLOCK(core_if->lock); ++ cil_hcd_start(core_if); ++ dwc_otg_adp_turnon_vbus(core_if); ++ DWC_SPINLOCK(core_if->lock); ++ } else { ++ /* ++ * Initiate SRP after initial ADP probe. ++ */ ++ dwc_otg_enable_global_interrupts(core_if); ++ dwc_otg_initiate_srp(core_if); ++ } ++ } else if (core_if->adp.probe_counter > 2){ ++ gpwrdn.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn); ++ if (compare_timer_values(core_if)) { ++ DWC_PRINTF("Difference in timer values !!! \n"); ++// core_if->adp.attached = DWC_OTG_ADP_ATTACHED; ++ dwc_otg_adp_probe_stop(core_if); ++ ++ /* Power on the core */ ++ if (core_if->power_down == 2) { ++ gpwrdn.b.pwrdnswtch = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs-> ++ gpwrdn, 0, gpwrdn.d32); ++ } ++ ++ /* check which value is for device mode and which for Host mode */ ++ if (!temp.b.idsts) { /* considered host mode value is 0 */ ++ /* Disable Interrupt from Power Down Logic */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pmuintsel = 1; ++ gpwrdn.b.pmuactv = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs-> ++ gpwrdn, gpwrdn.d32, 0); ++ ++ /* ++ * Initialize the Core for Host mode. ++ */ ++ core_if->op_state = A_HOST; ++ dwc_otg_core_init(core_if); ++ dwc_otg_enable_global_interrupts(core_if); ++ cil_hcd_start(core_if); ++ } else { ++ gotgctl_data_t gotgctl; ++ /* Mask SRP detected interrupt from Power Down Logic */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.srp_det_msk = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs-> ++ gpwrdn, gpwrdn.d32, 0); ++ ++ /* Disable Power Down Logic */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pmuintsel = 1; ++ gpwrdn.b.pmuactv = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs-> ++ gpwrdn, gpwrdn.d32, 0); ++ ++ /* ++ * Initialize the Core for Device mode. ++ */ ++ core_if->op_state = B_PERIPHERAL; ++ dwc_otg_core_init(core_if); ++ dwc_otg_enable_global_interrupts(core_if); ++ cil_pcd_start(core_if); ++ ++ gotgctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->gotgctl); ++ if (!gotgctl.b.bsesvld) { ++ dwc_otg_initiate_srp(core_if); ++ } ++ } ++ } ++ if (core_if->power_down == 2) { ++ if (gpwrdn.b.bsessvld) { ++ /* Mask SRP detected interrupt from Power Down Logic */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.srp_det_msk = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ ++ /* Disable Power Down Logic */ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pmuactv = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ ++ /* ++ * Initialize the Core for Device mode. ++ */ ++ core_if->op_state = B_PERIPHERAL; ++ dwc_otg_core_init(core_if); ++ dwc_otg_enable_global_interrupts(core_if); ++ cil_pcd_start(core_if); ++ } ++ } ++ } ++exit: ++ /* Clear interrupt */ ++ adpctl.d32 = dwc_otg_adp_read_reg(core_if); ++ adpctl.b.adp_prb_int = 1; ++ dwc_otg_adp_write_reg(core_if, adpctl.d32); ++ ++ return 0; ++} ++ ++/** ++ * This function hadles ADP Sense Interrupt ++ */ ++static int32_t dwc_otg_adp_handle_sns_intr(dwc_otg_core_if_t * core_if) ++{ ++ adpctl_data_t adpctl; ++ /* Stop ADP Sense timer */ ++ DWC_TIMER_CANCEL(core_if->adp.sense_timer); ++ ++ /* Restart ADP Sense timer */ ++ dwc_otg_adp_sense_timer_start(core_if); ++ ++ /* Clear interrupt */ ++ adpctl.d32 = dwc_otg_adp_read_reg(core_if); ++ adpctl.b.adp_sns_int = 1; ++ dwc_otg_adp_write_reg(core_if, adpctl.d32); ++ ++ return 0; ++} ++ ++/** ++ * This function handles ADP Probe Interrupts ++ */ ++static int32_t dwc_otg_adp_handle_prb_tmout_intr(dwc_otg_core_if_t * core_if, ++ uint32_t val) ++{ ++ adpctl_data_t adpctl = {.d32 = 0 }; ++ adpctl.d32 = val; ++ set_timer_value(core_if, adpctl.b.rtim); ++ ++ /* Clear interrupt */ ++ adpctl.d32 = dwc_otg_adp_read_reg(core_if); ++ adpctl.b.adp_tmout_int = 1; ++ dwc_otg_adp_write_reg(core_if, adpctl.d32); ++ ++ return 0; ++} ++ ++/** ++ * ADP Interrupt handler. ++ * ++ */ ++int32_t dwc_otg_adp_handle_intr(dwc_otg_core_if_t * core_if) ++{ ++ int retval = 0; ++ adpctl_data_t adpctl = {.d32 = 0}; ++ ++ adpctl.d32 = dwc_otg_adp_read_reg(core_if); ++ DWC_PRINTF("ADPCTL = %08x\n",adpctl.d32); ++ ++ if (adpctl.b.adp_sns_int & adpctl.b.adp_sns_int_msk) { ++ DWC_PRINTF("ADP Sense interrupt\n"); ++ retval |= dwc_otg_adp_handle_sns_intr(core_if); ++ } ++ if (adpctl.b.adp_tmout_int & adpctl.b.adp_tmout_int_msk) { ++ DWC_PRINTF("ADP timeout interrupt\n"); ++ retval |= dwc_otg_adp_handle_prb_tmout_intr(core_if, adpctl.d32); ++ } ++ if (adpctl.b.adp_prb_int & adpctl.b.adp_prb_int_msk) { ++ DWC_PRINTF("ADP Probe interrupt\n"); ++ adpctl.b.adp_prb_int = 1; ++ retval |= dwc_otg_adp_handle_prb_intr(core_if, adpctl.d32); ++ } ++ ++// dwc_otg_adp_modify_reg(core_if, adpctl.d32, 0); ++ //dwc_otg_adp_write_reg(core_if, adpctl.d32); ++ DWC_PRINTF("RETURN FROM ADP ISR\n"); ++ ++ return retval; ++} ++ ++/** ++ * ++ * @param core_if Programming view of DWC_otg controller. ++ */ ++int32_t dwc_otg_adp_handle_srp_intr(dwc_otg_core_if_t * core_if) ++{ ++ ++#ifndef DWC_HOST_ONLY ++ hprt0_data_t hprt0; ++ gpwrdn_data_t gpwrdn; ++ DWC_DEBUGPL(DBG_ANY, "++ Power Down Logic Session Request Interrupt++\n"); ++ ++ gpwrdn.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn); ++ /* check which value is for device mode and which for Host mode */ ++ if (!gpwrdn.b.idsts) { /* considered host mode value is 0 */ ++ DWC_PRINTF("SRP: Host mode\n"); ++ ++ if (core_if->adp_enable) { ++ dwc_otg_adp_probe_stop(core_if); ++ ++ /* Power on the core */ ++ if (core_if->power_down == 2) { ++ gpwrdn.b.pwrdnswtch = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs-> ++ gpwrdn, 0, gpwrdn.d32); ++ } ++ ++ core_if->op_state = A_HOST; ++ dwc_otg_core_init(core_if); ++ dwc_otg_enable_global_interrupts(core_if); ++ cil_hcd_start(core_if); ++ } ++ ++ /* Turn on the port power bit. */ ++ hprt0.d32 = dwc_otg_read_hprt0(core_if); ++ hprt0.b.prtpwr = 1; ++ DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32); ++ ++ /* Start the Connection timer. So a message can be displayed ++ * if connect does not occur within 10 seconds. */ ++ cil_hcd_session_start(core_if); ++ } else { ++ DWC_PRINTF("SRP: Device mode %s\n", __FUNCTION__); ++ if (core_if->adp_enable) { ++ dwc_otg_adp_probe_stop(core_if); ++ ++ /* Power on the core */ ++ if (core_if->power_down == 2) { ++ gpwrdn.b.pwrdnswtch = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs-> ++ gpwrdn, 0, gpwrdn.d32); ++ } ++ ++ gpwrdn.d32 = 0; ++ gpwrdn.b.pmuactv = 0; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, ++ gpwrdn.d32); ++ ++ core_if->op_state = B_PERIPHERAL; ++ dwc_otg_core_init(core_if); ++ dwc_otg_enable_global_interrupts(core_if); ++ cil_pcd_start(core_if); ++ } ++ } ++#endif ++ return 1; ++} +Index: linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_adp.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_adp.h 2013-07-26 19:34:43.000000000 +0000 +@@ -0,0 +1,80 @@ ++/* ========================================================================== ++ * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_adp.h $ ++ * $Revision: #7 $ ++ * $Date: 2011/10/24 $ ++ * $Change: 1871159 $ ++ * ++ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, ++ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless ++ * otherwise expressly agreed to in writing between Synopsys and you. ++ * ++ * The Software IS NOT an item of Licensed Software or Licensed Product under ++ * any End User Software License Agreement or Agreement for Licensed Product ++ * with Synopsys or any supplement thereto. You are permitted to use and ++ * redistribute this Software in source and binary forms, with or without ++ * modification, provided that redistributions of source code must retain this ++ * notice. You may not view, use, disclose, copy or distribute this file or ++ * any information contained herein except pursuant to this license grant from ++ * Synopsys. If you do not agree with this notice, including the disclaimer ++ * below, then you are not authorized to use the Software. ++ * ++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, ++ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR ++ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER ++ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY ++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH ++ * DAMAGE. ++ * ========================================================================== */ ++ ++#ifndef __DWC_OTG_ADP_H__ ++#define __DWC_OTG_ADP_H__ ++ ++/** ++ * @file ++ * ++ * This file contains the Attach Detect Protocol interfaces and defines ++ * (functions) and structures for Linux. ++ * ++ */ ++ ++#define DWC_OTG_ADP_UNATTACHED 0 ++#define DWC_OTG_ADP_ATTACHED 1 ++#define DWC_OTG_ADP_UNKOWN 2 ++ ++typedef struct dwc_otg_adp { ++ uint32_t adp_started; ++ uint32_t initial_probe; ++ int32_t probe_timer_values[2]; ++ uint32_t probe_enabled; ++ uint32_t sense_enabled; ++ dwc_timer_t *sense_timer; ++ uint32_t sense_timer_started; ++ dwc_timer_t *vbuson_timer; ++ uint32_t vbuson_timer_started; ++ uint32_t attached; ++ uint32_t probe_counter; ++ uint32_t gpwrdn; ++} dwc_otg_adp_t; ++ ++/** ++ * Attach Detect Protocol functions ++ */ ++ ++extern void dwc_otg_adp_write_reg(dwc_otg_core_if_t * core_if, uint32_t value); ++extern uint32_t dwc_otg_adp_read_reg(dwc_otg_core_if_t * core_if); ++extern uint32_t dwc_otg_adp_probe_start(dwc_otg_core_if_t * core_if); ++extern uint32_t dwc_otg_adp_sense_start(dwc_otg_core_if_t * core_if); ++extern uint32_t dwc_otg_adp_probe_stop(dwc_otg_core_if_t * core_if); ++extern uint32_t dwc_otg_adp_sense_stop(dwc_otg_core_if_t * core_if); ++extern void dwc_otg_adp_start(dwc_otg_core_if_t * core_if, uint8_t is_host); ++extern void dwc_otg_adp_init(dwc_otg_core_if_t * core_if); ++extern void dwc_otg_adp_remove(dwc_otg_core_if_t * core_if); ++extern int32_t dwc_otg_adp_handle_intr(dwc_otg_core_if_t * core_if); ++extern int32_t dwc_otg_adp_handle_srp_intr(dwc_otg_core_if_t * core_if); ++ ++#endif //__DWC_OTG_ADP_H__ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_attr.c +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/dwc_otg_attr.c 2013-07-26 19:31:22.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_attr.c 2013-07-26 19:34:44.000000000 +0000 +@@ -1,8 +1,8 @@ + /* ========================================================================== + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_attr.c $ +- * $Revision: #35 $ +- * $Date: 2009/04/03 $ +- * $Change: 1225160 $ ++ * $Revision: #44 $ ++ * $Date: 2010/11/29 $ ++ * $Change: 1636033 $ + * + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless +@@ -213,6 +213,37 @@ +
                                                                                rem_wakeup_pwrdn On read, shows the status core - hibernated or not. On write, initiates ++ a remote wakeup of the device from Hibernation. Read/Write
                                                                                mode_ch_tim_en This bit is used to enable or disable the host core to wait for 200 PHY ++ clock cycles at the end of Resume to change the opmode signal to the PHY to 00 ++ after Suspend or LPM. Read/Write
                                                                                fr_interval On read, shows the value of HFIR Frame Interval. On write, dynamically ++ reload HFIR register during runtime. The application can write a value to this ++ register only after the Port Enable bit of the Host Port Control and Status ++ register (HPRT.PrtEnaPort) has been set Read/Write
                                                                                disconnect_us On read, shows the status of disconnect_device_us. On write, sets disconnect_us ++ which causes soft disconnect for 100us. Applicable only for device mode of operation. Read/Write
                                                                                regdump Dumps the contents of core registers. Read
                                                                                sleep_local_dev Generetates sleep signaling. Applicable only in host mode. +- Write
                                                                                sleep_status Shows sleep status of device. + Read
                                                                                otg_en_multiple_tx_fifoulpi_fs_lsSpecifies whether to use ULPI FS/LS mode only. ++ - 0: Disabled (default) ++ - 1: Enabled ++
                                                                                ts_dlineSpecifies whether term select D-Line pulsing for all PHYs is enabled. ++ - 0: Disabled (default) ++ - 1: Enabled ++
                                                                                en_multiple_tx_fifoSpecifies whether dedicatedto tx fifos are enabled for non periodic IN EPs. + The driver will automatically detect the value for this parameter if none is + specified. +@@ -1521,9 +1567,9 @@ + +
                                                                                thr_ctlSpecifies whether to enable Thresholding for Device mode. Bits 0, 1, 2 of this +- parmater specifies if thresholding is enabled for non-Iso Tx, Iso Tx and Rx +- transfers accordingly. ++ Specifies whether to enable Thresholding for Device mode. Bits 0, 1, 2 of ++ this parmater specifies if thresholding is enabled for non-Iso Tx, Iso Tx and ++ Rx transfers accordingly. + The driver will automatically detect the value for this parameter if none is + specified. + - Values: 0 to 7 (default 0) +@@ -1547,7 +1593,7 @@ + The driver will automatically detect the value for this parameter if none is + specified. + - 0: MPI disabled (default) +- - 1: MPI enable ++ - 1: MPI enable +
                                                                                ic_usb_capSpecifies whether to enable IC_USB capability. ++ The driver will automatically detect the value for this parameter if none is ++ specified. ++ - 0: IC_USB disabled (default, if available) ++ - 1: IC_USB enable ++
                                                                                ahb_thr_ratioSpecifies AHB Threshold ratio. + - Values: 0 to 3 (default 0) +
                                                                                power_downSpecifies Power Down(Hibernation) Mode. ++ The driver will automatically detect the value for this parameter if none is ++ specified. ++ - 0: Power Down disabled (default) ++ - 2: Power Down enabled ++
                                                                                reload_ctlSpecifies whether dynamic reloading of the HFIR register is allowed during ++ run time. The driver will automatically detect the value for this parameter if ++ none is specified. In case the HFIR value is reloaded when HFIR.RldCtrl == 1'b0 ++ the core might misbehave. ++ - 0: Reload Control disabled (default) ++ - 1: Reload Control enabled ++
                                                                                dev_out_nakSpecifies whether Device OUT NAK enhancement enabled or no. ++ The driver will automatically detect the value for this parameter if ++ none is specified. This parameter is valid only when OTG_EN_DESC_DMA == 1b1. ++ - 0: The core does not set NAK after Bulk OUT transfer complete (default) ++ - 1: The core sets NAK after Bulk OUT transfer complete ++
                                                                                cont_on_bnaSpecifies whether Enable Continue on BNA enabled or no. ++ After receiving BNA interrupt the core disables the endpoint,when the ++ endpoint is re-enabled by the application the ++ - 0: Core starts processing from the DOEPDMA descriptor (default) ++ - 1: Core starts processing from the descriptor which received the BNA. ++ This parameter is valid only when OTG_EN_DESC_DMA == 1b1. ++
                                                                                ahb_singleThis bit when programmed supports SINGLE transfers for remainder data ++ in a transfer for DMA mode of operation. ++ - 0: The remainder data will be sent using INCR burst size (default) ++ - 1: The remainder data will be sent using SINGLE burst size. ++
                                                                                adp_enableSpecifies whether ADP feature is enabled. ++ The driver will automatically detect the value for this parameter if none is ++ specified. ++ - 0: ADP feature disabled (default) ++ - 1: ADP feature enabled ++
                                                                                otg_verSpecifies whether OTG is performing as USB OTG Revision 2.0 or Revision 1.3 ++ USB OTG device. ++ - 0: OTG 2.0 support disabled (default) ++ - 1: OTG 2.0 support enabled ++
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                _ddma_align_buffer_setupDescriptor DMA Alignment Buffer setup structure
                                                                                _ddma_concat_buffer_setupDescriptor DMA Concatenation Buffer setup structure
                                                                                _ddma_concat_buffer_setup_hdrDescriptor DMA Concatenation Buffer setup structure
                                                                                _ddma_sg_buffer_setupDescriptor DMA SG Buffer setup structure (SG buffer)
                                                                                _rx_fifo_size_setupTransmit FIFO Size setup structure
                                                                                _tx_fifo_size_setupTransmit FIFO Size setup structure
                                                                                adpctl_dataThis union represents the bit fields of the Core ADP Timer, Control and Status Register (ADPTIMCTLSTS)
                                                                                cfi_all_features_headerThis structure is the header of the Core Features dataset returned to the Host
                                                                                cfi_epThe CFI wrapper of the enabled and activated dwc_otg_pcd_ep structures
                                                                                cfi_feature_desc_headerThis structure is a header of the Core Feature descriptor dataset returned to the Host after the VEN_CORE_GET_FEATURES request
                                                                                cfi_opsThis is the interface for the CFI operations
                                                                                cfi_stringThis structure describes a NULL terminated string referenced by its id field
                                                                                cfi_usb_ctrlrequestStruct cfi_usb_ctrlrequest - the CFI implementation of the struct usb_ctrlrequest This structure encapsulates the standard usb_ctrlrequest and adds a pointer to the data returned in the data stage of a 3-stage Control Write requests
                                                                                daint_dataThis union represents the bit fields in the Device All EP Interrupt and Mask Registers
                                                                                dcfg_dataThis union represents the bit fields in the Device Configuration Register
                                                                                dctl_dataThis union represents the bit fields in the Device Control Register
                                                                                depctl_dataThis union represents the bit fields in the Device EP Control Register
                                                                                deptsiz0_dataThis union represents the bit fields in the Device EP 0 Transfer Size Register
                                                                                deptsiz_dataThis union represents the bit fields in the Device EP Transfer Size Register
                                                                                dev_dma_desc_stsThis union represents the bit fields in the DMA Descriptor status quadlet
                                                                                device_grxsts_dataThis union represents the bit fields in the Device Receive Status Read and Pop Registers (GRXSTSR, GRXSTSP) Read the register into the d32 element then read out the bits using the bit elements
                                                                                diepint_dataThis union represents the bit fields in the Device IN EP Interrupt Register and the Device IN EP Common Mask Register
                                                                                doepint_dataThis union represents the bit fields in the Device OUT EP Interrupt Registerand Device OUT EP Common Interrupt Mask Register
                                                                                dsts_dataThis union represents the bit fields in the Device Status Register
                                                                                dthrctl_dataThis union represents Threshold control Register Read and write the register into the d32 member
                                                                                dtknq1_dataThis union represents the bit fields in the Device IN Token Queue Read Registers
                                                                                dtxfsts_dataThis union represents the bit fields in the Transmit FIFO Status Register (DTXFSTS)
                                                                                dwc_epThe dwc_ep structure represents the state of a single endpoint when acting in device mode
                                                                                dwc_hcHost channel descriptor
                                                                                dwc_otg_cil_callbacksDWC_otg CIL callback structure
                                                                                dwc_otg_core_global_regsDWC_otg Core registers
                                                                                dwc_otg_core_ifThe dwc_otg_core_if structure contains information needed to manage the DWC_otg controller acting in either host or device mode
                                                                                dwc_otg_core_paramsThe following parameters may be specified when starting the module
                                                                                dwc_otg_dev_dma_descDMA Descriptor structure
                                                                                dwc_otg_dev_global_regsDevice Global Registers
                                                                                dwc_otg_dev_ifThe dwc_otg_dev_if structure contains information needed to manage the DWC_otg controller acting in device mode
                                                                                dwc_otg_dev_in_ep_regsDevice Logical IN Endpoint-Specific Registers
                                                                                dwc_otg_dev_out_ep_regsDevice Logical OUT Endpoint-Specific Registers
                                                                                dwc_otg_deviceThis structure is a wrapper that encapsulates the driver components used to manage a single DWC_otg controller
                                                                                dwc_otg_hc_regsHost Channel Specific Registers
                                                                                dwc_otg_hcdThis structure holds the state of the HCD, including the non-periodic and periodic schedules
                                                                                dwc_otg_hcd::dwc_otg_hcd_internal_flagsInternal DWC HCD Flags
                                                                                dwc_otg_host_dma_descHost-mode DMA Descriptor structure
                                                                                dwc_otg_host_global_regsThe Host Global Registers structure defines the size and relative field offsets for the Host Mode Global Registers
                                                                                dwc_otg_host_ifOTG Host Interface Structure
                                                                                dwc_otg_pcdDWC_otg PCD Structure
                                                                                dwc_otg_pcd_epPCD EP structure
                                                                                dwc_otg_pcd_function_opsFunction Driver Ops Data Structure
                                                                                dwc_otg_pcd_requestDWC_otg request structure
                                                                                dwc_otg_qhA Queue Head (QH) holds the static characteristics of an endpoint and maintains a list of transfers (QTDs) for that endpoint
                                                                                dwc_otg_qtdA Queue Transfer Descriptor (QTD) holds the state of a bulk, control, interrupt, or isochronous transfer
                                                                                fifosize_dataThis union represents the bit fields in the FIFO Size Registers (HPTXFSIZ, GNPTXFSIZ, DPTXFSIZn, DIEPTXFn)
                                                                                gahbcfg_dataThis union represents the bit fields of the Core AHB Configuration Register (GAHBCFG)
                                                                                gdfifocfg_dataThis union represents the bit fields in the Global Data FIFO Software Configuration Register
                                                                                ggpio_dataThis union represents the bit fields in the General Purpose Input/Output Register (GGPIO)
                                                                                gi2cctl_dataThis union represents the bit fields in the I2C Control Register (I2CCTL)
                                                                                gintmsk_dataThis union represents the bit fields of the Core Interrupt Mask Register (GINTMSK)
                                                                                gintsts_dataThis union represents the bit fields of the Core Interrupt Register (GINTSTS)
                                                                                glpmctl_dataThis union represents the bit fields of the Core LPM Configuration Register (GLPMCFG)
                                                                                gnptxsts_dataThis union represents the bit fields in the Non-Periodic Transmit FIFO/Queue Status Register (GNPTXSTS)
                                                                                gotgctl_dataThis union represents the bit fields of the Core OTG Control and Status Register (GOTGCTL)
                                                                                gotgint_dataThis union represents the bit fields of the Core OTG Interrupt Register (GOTGINT)
                                                                                gpvndctl_dataThis union represents the bit fields in the PHY Vendor Control Register (GPVNDCTL)
                                                                                gpwrdn_dataThis union represents the bit fields in the Global Power Down Register Register
                                                                                grstctl_dataThis union represents the bit fields of the Core Reset Register (GRSTCTL)
                                                                                gsnpsid_dataThis union represents the bit fields in the Synopsys ID Register (GSNPSID)
                                                                                guid_dataThis union represents the bit fields in the User ID Register (GUID)
                                                                                gusbcfg_dataThis union represents the bit fields of the Core USB Configuration Register (GUSBCFG)
                                                                                haint_dataThis union represents the bit fields in the Host All Interrupt Register
                                                                                haintmsk_dataThis union represents the bit fields in the Host All Interrupt Register
                                                                                hcchar_dataThis union represents the bit fields in the Host Channel Characteristics Register
                                                                                hcdma_dataThis union represents the bit fields in the Host DMA Address Register used in Descriptor DMA mode
                                                                                hcfg_dataThis union represents the bit fields in the Host Configuration Register
                                                                                hcint_dataThis union represents the bit fields in the Host All Interrupt Register
                                                                                hcintmsk_dataThis union represents the bit fields in the Host Channel Interrupt Mask Register
                                                                                hctsiz_dataThis union represents the bit fields in the Host Channel Transfer Size Register
                                                                                hfir_dataThis union represents the bit fields in the Host Frame Remaing/Number Register
                                                                                hfnum_dataThis union represents the bit fields in the Host Frame Remaing/Number Register
                                                                                host_dma_desc_stsThis union represents the bit fields in the DMA Descriptor status quadlet for host mode
                                                                                host_grxsts_dataThis union represents the bit fields in the Host Receive Status Read and Pop Registers (GRXSTSR, GRXSTSP) Read the register into the d32 element then read out the bits using the bit elements
                                                                                hprt0_dataThis union represents the bit fields in the Host Port Control and Status Register
                                                                                hwcfg1_dataThis union represents the bit fields in the User HW Config1 Register
                                                                                hwcfg2_dataThis union represents the bit fields in the User HW Config2 Register
                                                                                hwcfg3_dataThis union represents the bit fields in the User HW Config3 Register
                                                                                hwcfg4_dataThis union represents the bit fields in the User HW Config4 Register
                                                                                iso_pkt_infoInformation for each ISOC packet
                                                                                pcgcctl_dataThis union represents the bit fields in the Power and Clock Gating Control Register
                                                                                +-
                                                                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/doxygen.css +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/doxygen.css 2013-07-26 19:34:39.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,271 +0,0 @@ +-BODY,H1,H2,H3,H4,H5,H6,P,CENTER,TD,TH,UL,DL,DIV { +- font-family: Geneva, Arial, Helvetica, sans-serif; +-} +-H1 { +- text-align: center; +-} +-CAPTION { font-weight: bold } +-DIV.qindex { +- width: 100%; +- background-color: #eeeeff; +- border: 1px solid #b0b0b0; +- text-align: center; +- margin: 2px; +- padding: 2px; +- line-height: 140%; +-} +-DIV.nav { +- width: 100%; +- background-color: #eeeeff; +- border: 1px solid #b0b0b0; +- text-align: center; +- margin: 2px; +- padding: 2px; +- line-height: 140%; +-} +-A.qindex { +- text-decoration: none; +- font-weight: bold; +- color: #1A419D; +-} +-A.qindex:visited { +- text-decoration: none; +- font-weight: bold; +- color: #1A419D +-} +-A.qindex:hover { +- text-decoration: none; +- background-color: #ddddff; +-} +-A.qindexHL { +- text-decoration: none; +- font-weight: bold; +- background-color: #6666cc; +- color: #ffffff; +- border: 1px double #9295C2; +-} +-A.qindexHL:hover { +- text-decoration: none; +- background-color: #6666cc; +- color: #ffffff; +-} +-A.qindexHL:visited { text-decoration: none; background-color: #6666cc; color: #ffffff } +-A.el { text-decoration: none; font-weight: bold } +-A.elRef { font-weight: bold } +-A.code:link { text-decoration: none; font-weight: normal; color: #0000FF} +-A.code:visited { text-decoration: none; font-weight: normal; color: #0000FF} +-A.codeRef:link { font-weight: normal; color: #0000FF} +-A.codeRef:visited { font-weight: normal; color: #0000FF} +-A:hover { text-decoration: none; background-color: #f2f2ff } +-DL.el { margin-left: -1cm } +-.fragment { +- font-family: monospace +-} +-PRE.fragment { +- border: 1px solid #CCCCCC; +- background-color: #f5f5f5; +- margin-top: 4px; +- margin-bottom: 4px; +- margin-left: 2px; +- margin-right: 8px; +- padding-left: 6px; +- padding-right: 6px; +- padding-top: 4px; +- padding-bottom: 4px; +-} +-DIV.ah { background-color: black; font-weight: bold; color: #ffffff; margin-bottom: 3px; margin-top: 3px } +-TD.md { background-color: #F4F4FB; font-weight: bold; } +-TD.mdname1 { background-color: #F4F4FB; font-weight: bold; color: #602020; } +-TD.mdname { background-color: #F4F4FB; font-weight: bold; color: #602020; width: 600px; } +-DIV.groupHeader { +- margin-left: 16px; +- margin-top: 12px; +- margin-bottom: 6px; +- font-weight: bold; +-} +-DIV.groupText { margin-left: 16px; font-style: italic; font-size: 14px } +-BODY { +- background: white; +- color: black; +- margin-right: 20px; +- margin-left: 20px; +-} +-TD.indexkey { +- background-color: #eeeeff; +- font-weight: bold; +- padding-right : 10px; +- padding-top : 2px; +- padding-left : 10px; +- padding-bottom : 2px; +- margin-left : 0px; +- margin-right : 0px; +- margin-top : 2px; +- margin-bottom : 2px; +- border: 1px solid #CCCCCC; +-} +-TD.indexvalue { +- background-color: #eeeeff; +- font-style: italic; +- padding-right : 10px; +- padding-top : 2px; +- padding-left : 10px; +- padding-bottom : 2px; +- margin-left : 0px; +- margin-right : 0px; +- margin-top : 2px; +- margin-bottom : 2px; +- border: 1px solid #CCCCCC; +-} +-TR.memlist { +- background-color: #f0f0f0; +-} +-P.formulaDsp { text-align: center; } +-IMG.formulaDsp { } +-IMG.formulaInl { vertical-align: middle; } +-SPAN.keyword { color: #008000 } +-SPAN.keywordtype { color: #604020 } +-SPAN.keywordflow { color: #e08000 } +-SPAN.comment { color: #800000 } +-SPAN.preprocessor { color: #806020 } +-SPAN.stringliteral { color: #002080 } +-SPAN.charliteral { color: #008080 } +-.mdTable { +- border: 1px solid #868686; +- background-color: #F4F4FB; +-} +-.mdRow { +- padding: 8px 10px; +-} +-.mdescLeft { +- padding: 0px 8px 4px 8px; +- font-size: 12px; +- font-style: italic; +- background-color: #FAFAFA; +- border-top: 1px none #E0E0E0; +- border-right: 1px none #E0E0E0; +- border-bottom: 1px none #E0E0E0; +- border-left: 1px none #E0E0E0; +- margin: 0px; +-} +-.mdescRight { +- padding: 0px 8px 4px 8px; +- font-size: 12px; +- font-style: italic; +- background-color: #FAFAFA; +- border-top: 1px none #E0E0E0; +- border-right: 1px none #E0E0E0; +- border-bottom: 1px none #E0E0E0; +- border-left: 1px none #E0E0E0; +- margin: 0px; +-} +-.memItemLeft { +- padding: 1px 0px 0px 8px; +- margin: 4px; +- border-top-width: 1px; +- border-right-width: 1px; +- border-bottom-width: 1px; +- border-left-width: 1px; +- border-top-color: #E0E0E0; +- border-right-color: #E0E0E0; +- border-bottom-color: #E0E0E0; +- border-left-color: #E0E0E0; +- border-top-style: solid; +- border-right-style: none; +- border-bottom-style: none; +- border-left-style: none; +- background-color: #FAFAFA; +- font-size: 12px; +-} +-.memItemRight { +- padding: 1px 8px 0px 8px; +- margin: 4px; +- border-top-width: 1px; +- border-right-width: 1px; +- border-bottom-width: 1px; +- border-left-width: 1px; +- border-top-color: #E0E0E0; +- border-right-color: #E0E0E0; +- border-bottom-color: #E0E0E0; +- border-left-color: #E0E0E0; +- border-top-style: solid; +- border-right-style: none; +- border-bottom-style: none; +- border-left-style: none; +- background-color: #FAFAFA; +- font-size: 13px; +-} +-.memTemplItemLeft { +- padding: 1px 0px 0px 8px; +- margin: 4px; +- border-top-width: 1px; +- border-right-width: 1px; +- border-bottom-width: 1px; +- border-left-width: 1px; +- border-top-color: #E0E0E0; +- border-right-color: #E0E0E0; +- border-bottom-color: #E0E0E0; +- border-left-color: #E0E0E0; +- border-top-style: none; +- border-right-style: none; +- border-bottom-style: none; +- border-left-style: none; +- background-color: #FAFAFA; +- font-size: 12px; +-} +-.memTemplItemRight { +- padding: 1px 8px 0px 8px; +- margin: 4px; +- border-top-width: 1px; +- border-right-width: 1px; +- border-bottom-width: 1px; +- border-left-width: 1px; +- border-top-color: #E0E0E0; +- border-right-color: #E0E0E0; +- border-bottom-color: #E0E0E0; +- border-left-color: #E0E0E0; +- border-top-style: none; +- border-right-style: none; +- border-bottom-style: none; +- border-left-style: none; +- background-color: #FAFAFA; +- font-size: 13px; +-} +-.memTemplParams { +- padding: 1px 0px 0px 8px; +- margin: 4px; +- border-top-width: 1px; +- border-right-width: 1px; +- border-bottom-width: 1px; +- border-left-width: 1px; +- border-top-color: #E0E0E0; +- border-right-color: #E0E0E0; +- border-bottom-color: #E0E0E0; +- border-left-color: #E0E0E0; +- border-top-style: solid; +- border-right-style: none; +- border-bottom-style: none; +- border-left-style: none; +- color: #606060; +- background-color: #FAFAFA; +- font-size: 12px; +-} +-.search { color: #003399; +- font-weight: bold; +-} +-FORM.search { +- margin-bottom: 0px; +- margin-top: 0px; +-} +-INPUT.search { font-size: 75%; +- color: #000080; +- font-weight: normal; +- background-color: #eeeeff; +-} +-TD.tiny { font-size: 75%; +-} +-a { +- color: #252E78; +-} +-a:visited { +- color: #3D2185; +-} +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__cfi__common_8h-source.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/dwc__cfi__common_8h-source.html 2013-07-26 19:34:39.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,103 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_cfi_common.h Source File +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                dwc_cfi_common.h

                                                                                Go to the documentation of this file.
                                                                                00001 /* ==========================================================================
+-00002  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
+-00003  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
+-00004  * otherwise expressly agreed to in writing between Synopsys and you.
+-00005  * 
+-00006  * The Software IS NOT an item of Licensed Software or Licensed Product under
+-00007  * any End User Software License Agreement or Agreement for Licensed Product
+-00008  * with Synopsys or any supplement thereto. You are permitted to use and
+-00009  * redistribute this Software in source and binary forms, with or without
+-00010  * modification, provided that redistributions of source code must retain this
+-00011  * notice. You may not view, use, disclose, copy or distribute this file or
+-00012  * any information contained herein except pursuant to this license grant from
+-00013  * Synopsys. If you do not agree with this notice, including the disclaimer
+-00014  * below, then you are not authorized to use the Software.
+-00015  * 
+-00016  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
+-00017  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+-00018  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+-00019  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
+-00020  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+-00021  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+-00022  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+-00023  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+-00024  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+-00025  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+-00026  * DAMAGE.
+-00027  * ========================================================================== */
+-00028 
+-00029 #if !defined(__DWC_CFI_COMMON_H__)
+-00030 #define __DWC_CFI_COMMON_H__
+-00031 
+-00032 //#include <linux/types.h>
+-00033 
+-00044 #define VEN_CORE_GET_FEATURES           0xB1
+-00045 
+-00047 #define VEN_CORE_GET_FEATURE            0xB2
+-00048 
+-00050 #define VEN_CORE_SET_FEATURE            0xB3
+-00051 
+-00055 #define VEN_CORE_RESET_FEATURES         0xB4
+-00056 
+-00058 #define VEN_CORE_ACTIVATE_FEATURES      0xB5
+-00059 
+-00061 #define VEN_CORE_READ_REGISTER          0xB6
+-00062 
+-00064 #define VEN_CORE_WRITE_REGISTER         0xB7
+-00065 
+-00069 struct cfi_all_features_header {
+-00071 #define CFI_ALL_FEATURES_HDR_LEN                8
+-00072 
+-00075         uint16_t wTotalLen;
+-00076 
+-00082         uint16_t wVersion;
+-00083 
+-00085         uint16_t wCoreID;
+-00086 #define CFI_CORE_ID_UDC         1
+-00087 #define CFI_CORE_ID_OTG         2
+-00088 #define CFI_CORE_ID_WUDEV       3
+-00089 
+-00091         uint16_t wNumFeatures;
+-00092 } UPACKED;
+-00093 
+-00094 typedef struct cfi_all_features_header cfi_all_features_header_t;
+-00095 
+-00099 struct cfi_feature_desc_header {
+-00100 #define CFI_FEATURE_DESC_HDR_LEN        8
+-00101 
+-00103         uint16_t wFeatureID;
+-00104 
+-00108         uint16_t wLength;
+-00109 
+-00111         uint16_t wDataLength;
+-00112 
+-00119         uint8_t bmAttributes;
+-00120 #define CFI_FEATURE_ATTR_RO             1
+-00121 #define CFI_FEATURE_ATTR_RW             0
+-00122 
+-00124         uint8_t bNameLen;
+-00125 
+-00127         //uint8_t *name;
+-00128 } UPACKED;
+-00129 
+-00130 typedef struct cfi_feature_desc_header cfi_feature_desc_header_t;
+-00131 
+-00136 struct cfi_string {
+-00137         uint16_t id;
+-00138         const uint8_t *s;
+-00139 };
+-00140 typedef struct cfi_string cfi_string_t;
+-00141 
+-00142 #endif
+-
                                                                                Generated on Thu Oct 27 03:56:37 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__cfi__common_8h.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/dwc__cfi__common_8h.html 2013-07-26 19:34:39.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,103 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_cfi_common.h File Reference +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                dwc_cfi_common.h File Reference

                                                                                This file contains the CFI specific common constants, interfaces (functions and macros) and structures for Linux. More... +-

                                                                                +- +-

                                                                                +-Go to the source code of this file. +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-

                                                                                Data Structures

                                                                                struct  cfi_all_features_header
                                                                                 This structure is the header of the Core Features dataset returned to the Host. More...
                                                                                struct  cfi_feature_desc_header
                                                                                 This structure is a header of the Core Feature descriptor dataset returned to the Host after the VEN_CORE_GET_FEATURES request. More...
                                                                                struct  cfi_string
                                                                                 This structure describes a NULL terminated string referenced by its id field. More...

                                                                                Defines

                                                                                +-#define __DWC_CFI_COMMON_H__
                                                                                +-#define VEN_CORE_GET_FEATURES   0xB1
                                                                                 This is a request for all Core Features.
                                                                                +-#define VEN_CORE_GET_FEATURE   0xB2
                                                                                 This is a request to get the value of a specific Core Feature.
                                                                                +-#define VEN_CORE_SET_FEATURE   0xB3
                                                                                 This command allows the host to set the value of a specific Core Feature.
                                                                                +-#define VEN_CORE_RESET_FEATURES   0xB4
                                                                                 This command allows the host to set the default values of either all or any specific Core Feature.
                                                                                +-#define VEN_CORE_ACTIVATE_FEATURES   0xB5
                                                                                 This command forces the PCD to write the deferred values of a Core Features.
                                                                                +-#define VEN_CORE_READ_REGISTER   0xB6
                                                                                 This request reads a DWORD value from a register at the specified offset.
                                                                                +-#define VEN_CORE_WRITE_REGISTER   0xB7
                                                                                 This request writes a DWORD value into a register at the specified offset.
                                                                                +-#define CFI_ALL_FEATURES_HDR_LEN   8
                                                                                 The features header structure length is.
                                                                                +-#define CFI_CORE_ID_UDC   1
                                                                                +-#define CFI_CORE_ID_OTG   2
                                                                                +-#define CFI_CORE_ID_WUDEV   3
                                                                                +-#define CFI_FEATURE_DESC_HDR_LEN   8
                                                                                +-#define CFI_FEATURE_ATTR_RO   1
                                                                                +-#define CFI_FEATURE_ATTR_RW   0

                                                                                Typedefs

                                                                                +-typedef cfi_all_features_header cfi_all_features_header_t
                                                                                +-typedef cfi_feature_desc_header cfi_feature_desc_header_t
                                                                                +-typedef cfi_string cfi_string_t

                                                                                Variables

                                                                                +-cfi_all_features_header UPACKED
                                                                                 This structure is the header of the Core Features dataset returned to the Host.
                                                                                +-

                                                                                Detailed Description

                                                                                +-This file contains the CFI specific common constants, interfaces (functions and macros) and structures for Linux. +-

                                                                                +-No PCD specific data structure or definition is to be included in this file. +-

                                                                                +-Definition in file dwc_cfi_common.h.

                                                                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__adp_8c-source.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/dwc__otg__adp_8c-source.html 2013-07-26 19:34:39.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,769 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_adp.c Source File +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                dwc_otg_adp.c

                                                                                Go to the documentation of this file.
                                                                                00001 /* ==========================================================================
+-00002  * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_adp.c $
+-00003  * $Revision: #12 $
+-00004  * $Date: 2011/10/26 $
+-00005  * $Change: 1873028 $
+-00006  *
+-00007  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
+-00008  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
+-00009  * otherwise expressly agreed to in writing between Synopsys and you.
+-00010  *
+-00011  * The Software IS NOT an item of Licensed Software or Licensed Product under
+-00012  * any End User Software License Agreement or Agreement for Licensed Product
+-00013  * with Synopsys or any supplement thereto. You are permitted to use and
+-00014  * redistribute this Software in source and binary forms, with or without
+-00015  * modification, provided that redistributions of source code must retain this
+-00016  * notice. You may not view, use, disclose, copy or distribute this file or
+-00017  * any information contained herein except pursuant to this license grant from
+-00018  * Synopsys. If you do not agree with this notice, including the disclaimer
+-00019  * below, then you are not authorized to use the Software.
+-00020  *
+-00021  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
+-00022  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+-00023  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+-00024  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
+-00025  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+-00026  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+-00027  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+-00028  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+-00029  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+-00030  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+-00031  * DAMAGE.
+-00032  * ========================================================================== */
+-00033 
+-00034 #include "dwc_os.h"
+-00035 #include "dwc_otg_regs.h"
+-00036 #include "dwc_otg_cil.h"
+-00037 #include "dwc_otg_adp.h"
+-00038 
+-00046 void dwc_otg_adp_write_reg(dwc_otg_core_if_t * core_if, uint32_t value)
+-00047 {
+-00048         adpctl_data_t adpctl;
+-00049 
+-00050         adpctl.d32 = value;
+-00051         adpctl.b.ar = 0x2;
+-00052 
+-00053         DWC_WRITE_REG32(&core_if->core_global_regs->adpctl, adpctl.d32);
+-00054 
+-00055         while (adpctl.b.ar) {
+-00056                 adpctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->adpctl);
+-00057         }
+-00058 
+-00059 }
+-00060 
+-00064 uint32_t dwc_otg_adp_read_reg(dwc_otg_core_if_t * core_if)
+-00065 {
+-00066         adpctl_data_t adpctl;
+-00067 
+-00068         adpctl.d32 = 0;
+-00069         adpctl.b.ar = 0x1;
+-00070 
+-00071         DWC_WRITE_REG32(&core_if->core_global_regs->adpctl, adpctl.d32);
+-00072 
+-00073         while (adpctl.b.ar) {
+-00074                 adpctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->adpctl);
+-00075         }
+-00076 
+-00077         return adpctl.d32;
+-00078 }
+-00079 
+-00083 uint32_t dwc_otg_adp_read_reg_filter(dwc_otg_core_if_t * core_if)
+-00084 {
+-00085         adpctl_data_t adpctl;
+-00086 
+-00087         adpctl.d32 = dwc_otg_adp_read_reg(core_if);
+-00088         adpctl.b.adp_tmout_int = 0;
+-00089         adpctl.b.adp_prb_int = 0;
+-00090         adpctl.b.adp_tmout_int = 0;
+-00091                 
+-00092         return adpctl.d32;
+-00093 }
+-00094 
+-00098 void dwc_otg_adp_modify_reg(dwc_otg_core_if_t * core_if, uint32_t clr,
+-00099                             uint32_t set)
+-00100 {
+-00101         dwc_otg_adp_write_reg(core_if,
+-00102                               (dwc_otg_adp_read_reg(core_if) & (~clr)) | set);
+-00103 }
+-00104 
+-00105 static void adp_sense_timeout(void *ptr)
+-00106 {
+-00107         dwc_otg_core_if_t *core_if = (dwc_otg_core_if_t *) ptr;
+-00108         core_if->adp.sense_timer_started = 0;
+-00109         DWC_PRINTF("ADP SENSE TIMEOUT\n");
+-00110         if (core_if->adp_enable) {
+-00111                 dwc_otg_adp_sense_stop(core_if);
+-00112                 dwc_otg_adp_probe_start(core_if);
+-00113         }
+-00114 }
+-00115 
+-00119 static void adp_vbuson_timeout(void *ptr)
+-00120 {
+-00121         gpwrdn_data_t gpwrdn;
+-00122         dwc_otg_core_if_t *core_if = (dwc_otg_core_if_t *) ptr;
+-00123         hprt0_data_t hprt0 = {.d32 = 0 };
+-00124         pcgcctl_data_t pcgcctl = {.d32 = 0 };
+-00125         DWC_PRINTF("%s: 1.1 seconds expire after turning on VBUS\n",__FUNCTION__);
+-00126         if (core_if) {
+-00127                 core_if->adp.vbuson_timer_started = 0;
+-00128                 /* Turn off vbus */
+-00129                 hprt0.b.prtpwr = 1;
+-00130                 DWC_MODIFY_REG32(core_if->host_if->hprt0, hprt0.d32, 0);
+-00131                 gpwrdn.d32 = 0;
+-00132 
+-00133                 /* Power off the core */
+-00134                 if (core_if->power_down == 2) {
+-00135                         /* Enable Wakeup Logic */
+-00136 //                      gpwrdn.b.wkupactiv = 1;
+-00137                         gpwrdn.b.pmuactv = 0;
+-00138                         gpwrdn.b.pwrdnrstn = 1;
+-00139                         gpwrdn.b.pwrdnclmp = 1;
+-00140                         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0,
+-00141                                          gpwrdn.d32);
+-00142 
+-00143                         /* Suspend the Phy Clock */
+-00144                         pcgcctl.b.stoppclk = 1;
+-00145                         DWC_MODIFY_REG32(core_if->pcgcctl, 0, pcgcctl.d32);
+-00146 
+-00147                         /* Switch on VDD */
+-00148 //                      gpwrdn.b.wkupactiv = 1;
+-00149                         gpwrdn.b.pmuactv = 1;
+-00150                         gpwrdn.b.pwrdnrstn = 1;
+-00151                         gpwrdn.b.pwrdnclmp = 1;
+-00152                         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0,
+-00153                                          gpwrdn.d32);
+-00154                 } else {
+-00155                         /* Enable Power Down Logic */
+-00156                         gpwrdn.b.pmuintsel = 1;
+-00157                         gpwrdn.b.pmuactv = 1;
+-00158                         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
+-00159                 }
+-00160 
+-00161                 /* Power off the core */
+-00162                 if (core_if->power_down == 2) {
+-00163                         gpwrdn.d32 = 0;
+-00164                         gpwrdn.b.pwrdnswtch = 1;
+-00165                         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn,
+-00166                                          gpwrdn.d32, 0);
+-00167                 }
+-00168 
+-00169                 /* Unmask SRP detected interrupt from Power Down Logic */
+-00170                 gpwrdn.d32 = 0;
+-00171                 gpwrdn.b.srp_det_msk = 1;
+-00172                 DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
+-00173 
+-00174                 dwc_otg_adp_probe_start(core_if);
+-00175                 dwc_otg_dump_global_registers(core_if);
+-00176                 dwc_otg_dump_host_registers(core_if);
+-00177         }
+-00178 
+-00179 }
+-00180 
+-00187 void dwc_otg_adp_vbuson_timer_start(dwc_otg_core_if_t * core_if)
+-00188 {
+-00189         core_if->adp.vbuson_timer_started = 1;
+-00190         if (core_if->adp.vbuson_timer)
+-00191         {
+-00192                 DWC_PRINTF("SCHEDULING VBUSON TIMER\n");
+-00193                 /* 1.1 secs + 60ms necessary for cil_hcd_start*/
+-00194                 DWC_TIMER_SCHEDULE(core_if->adp.vbuson_timer, 1160);
+-00195         } else {
+-00196                 DWC_WARN("VBUSON_TIMER = %p\n",core_if->adp.vbuson_timer);
+-00197         }
+-00198 }
+-00199 
+-00200 #if 0
+-00201 
+-00205 static void mask_all_interrupts(dwc_otg_core_if_t * core_if)
+-00206 {
+-00207         int i;
+-00208         gahbcfg_data_t ahbcfg = {.d32 = 0 };
+-00209 
+-00210         /* Mask Host Interrupts */
+-00211 
+-00212         /* Clear and disable HCINTs */
+-00213         for (i = 0; i < core_if->core_params->host_channels; i++) {
+-00214                 DWC_WRITE_REG32(&core_if->host_if->hc_regs[i]->hcintmsk, 0);
+-00215                 DWC_WRITE_REG32(&core_if->host_if->hc_regs[i]->hcint, 0xFFFFFFFF);
+-00216 
+-00217         }
+-00218 
+-00219         /* Clear and disable HAINT */
+-00220         DWC_WRITE_REG32(&core_if->host_if->host_global_regs->haintmsk, 0x0000);
+-00221         DWC_WRITE_REG32(&core_if->host_if->host_global_regs->haint, 0xFFFFFFFF);
+-00222 
+-00223         /* Mask Device Interrupts */
+-00224         if (!core_if->multiproc_int_enable) {
+-00225                 /* Clear and disable IN Endpoint interrupts */
+-00226                 DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->diepmsk, 0);
+-00227                 for (i = 0; i <= core_if->dev_if->num_in_eps; i++) {
+-00228                         DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[i]->
+-00229                                         diepint, 0xFFFFFFFF);
+-00230                 }
+-00231 
+-00232                 /* Clear and disable OUT Endpoint interrupts */
+-00233                 DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->doepmsk, 0);
+-00234                 for (i = 0; i <= core_if->dev_if->num_out_eps; i++) {
+-00235                         DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[i]->
+-00236                                         doepint, 0xFFFFFFFF);
+-00237                 }
+-00238 
+-00239                 /* Clear and disable DAINT */
+-00240                 DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->daint,
+-00241                                 0xFFFFFFFF);
+-00242                 DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->daintmsk, 0);
+-00243         } else {
+-00244                 for (i = 0; i < core_if->dev_if->num_in_eps; ++i) {
+-00245                         DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->
+-00246                                         diepeachintmsk[i], 0);
+-00247                         DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[i]->
+-00248                                         diepint, 0xFFFFFFFF);
+-00249                 }
+-00250 
+-00251                 for (i = 0; i < core_if->dev_if->num_out_eps; ++i) {
+-00252                         DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->
+-00253                                         doepeachintmsk[i], 0);
+-00254                         DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[i]->
+-00255                                         doepint, 0xFFFFFFFF);
+-00256                 }
+-00257 
+-00258                 DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->deachintmsk,
+-00259                                 0);
+-00260                 DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->deachint,
+-00261                                 0xFFFFFFFF);
+-00262 
+-00263         }
+-00264 
+-00265         /* Disable interrupts */
+-00266         ahbcfg.b.glblintrmsk = 1;
+-00267         DWC_MODIFY_REG32(&core_if->core_global_regs->gahbcfg, ahbcfg.d32, 0);
+-00268 
+-00269         /* Disable all interrupts. */
+-00270         DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, 0);
+-00271 
+-00272         /* Clear any pending interrupts */
+-00273         DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
+-00274 
+-00275         /* Clear any pending OTG Interrupts */
+-00276         DWC_WRITE_REG32(&core_if->core_global_regs->gotgint, 0xFFFFFFFF);
+-00277 }
+-00278 
+-00283 static void unmask_conn_det_intr(dwc_otg_core_if_t * core_if)
+-00284 {
+-00285         gintmsk_data_t gintmsk = {.d32 = 0,.b.portintr = 1 };
+-00286 
+-00287         DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, gintmsk.d32);
+-00288 }
+-00289 #endif
+-00290 
+-00296 uint32_t dwc_otg_adp_probe_start(dwc_otg_core_if_t * core_if)
+-00297 {
+-00298 
+-00299         adpctl_data_t adpctl = {.d32 = 0};
+-00300         gpwrdn_data_t gpwrdn;
+-00301 #if 0
+-00302         adpctl_data_t adpctl_int = {.d32 = 0, .b.adp_prb_int = 1,
+-00303                                                                 .b.adp_sns_int = 1, b.adp_tmout_int};
+-00304 #endif
+-00305         dwc_otg_disable_global_interrupts(core_if);
+-00306         DWC_PRINTF("ADP Probe Start\n");
+-00307         core_if->adp.probe_enabled = 1;
+-00308 
+-00309         adpctl.b.adpres = 1;
+-00310         dwc_otg_adp_write_reg(core_if, adpctl.d32);
+-00311 
+-00312         while (adpctl.b.adpres) {
+-00313                 adpctl.d32 = dwc_otg_adp_read_reg(core_if);
+-00314         }
+-00315 
+-00316         adpctl.d32 = 0;
+-00317         gpwrdn.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
+-00318 
+-00319         /* In Host mode unmask SRP detected interrupt */
+-00320         gpwrdn.d32 = 0;
+-00321         gpwrdn.b.sts_chngint_msk = 1;
+-00322         if (!gpwrdn.b.idsts) {
+-00323                 gpwrdn.b.srp_det_msk = 1;
+-00324         }
+-00325         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
+-00326 
+-00327         adpctl.b.adp_tmout_int_msk = 1;
+-00328         adpctl.b.adp_prb_int_msk = 1;
+-00329         adpctl.b.prb_dschg = 1;
+-00330         adpctl.b.prb_delta = 1;
+-00331         adpctl.b.prb_per = 1;
+-00332         adpctl.b.adpen = 1;
+-00333         adpctl.b.enaprb = 1;
+-00334 
+-00335         dwc_otg_adp_write_reg(core_if, adpctl.d32);
+-00336         DWC_PRINTF("ADP Probe Finish\n");
+-00337         return 0;
+-00338 }
+-00339 
+-00346 void dwc_otg_adp_sense_timer_start(dwc_otg_core_if_t * core_if)
+-00347 {
+-00348         core_if->adp.sense_timer_started = 1;
+-00349         DWC_TIMER_SCHEDULE(core_if->adp.sense_timer, 3000 /* 3 secs */ );
+-00350 }
+-00351 
+-00357 uint32_t dwc_otg_adp_sense_start(dwc_otg_core_if_t * core_if)
+-00358 {
+-00359         adpctl_data_t adpctl;
+-00360 
+-00361         DWC_PRINTF("ADP Sense Start\n");
+-00362 
+-00363         /* Unmask ADP sense interrupt and mask all other from the core */
+-00364         adpctl.d32 = dwc_otg_adp_read_reg_filter(core_if);
+-00365         adpctl.b.adp_sns_int_msk = 1;
+-00366         dwc_otg_adp_write_reg(core_if, adpctl.d32);
+-00367         dwc_otg_disable_global_interrupts(core_if); // vahrama 
+-00368 
+-00369         /* Set ADP reset bit*/
+-00370         adpctl.d32 = dwc_otg_adp_read_reg_filter(core_if);
+-00371         adpctl.b.adpres = 1;
+-00372         dwc_otg_adp_write_reg(core_if, adpctl.d32);
+-00373 
+-00374         while (adpctl.b.adpres) {
+-00375                 adpctl.d32 = dwc_otg_adp_read_reg(core_if);
+-00376         }
+-00377 
+-00378         adpctl.b.adpres = 0;
+-00379         adpctl.b.adpen = 1;
+-00380         adpctl.b.enasns = 1;
+-00381         dwc_otg_adp_write_reg(core_if, adpctl.d32);
+-00382 
+-00383         dwc_otg_adp_sense_timer_start(core_if);
+-00384 
+-00385         return 0;
+-00386 }
+-00387 
+-00393 uint32_t dwc_otg_adp_probe_stop(dwc_otg_core_if_t * core_if)
+-00394 {
+-00395 
+-00396         adpctl_data_t adpctl;
+-00397         DWC_PRINTF("Stop ADP probe\n");
+-00398         core_if->adp.probe_enabled = 0;
+-00399         core_if->adp.probe_counter = 0;
+-00400         adpctl.d32 = dwc_otg_adp_read_reg(core_if);
+-00401 
+-00402         adpctl.b.adpen = 0;
+-00403         adpctl.b.adp_prb_int = 1;
+-00404         adpctl.b.adp_tmout_int = 1;
+-00405         adpctl.b.adp_sns_int = 1;
+-00406         dwc_otg_adp_write_reg(core_if, adpctl.d32);
+-00407 
+-00408         return 0;
+-00409 }
+-00410 
+-00416 uint32_t dwc_otg_adp_sense_stop(dwc_otg_core_if_t * core_if)
+-00417 {
+-00418         adpctl_data_t adpctl;
+-00419 
+-00420         core_if->adp.sense_enabled = 0;
+-00421 
+-00422         adpctl.d32 = dwc_otg_adp_read_reg_filter(core_if);
+-00423         adpctl.b.enasns = 0;
+-00424         adpctl.b.adp_sns_int = 1;
+-00425         dwc_otg_adp_write_reg(core_if, adpctl.d32);
+-00426 
+-00427         return 0;
+-00428 }
+-00429 
+-00437 void dwc_otg_adp_turnon_vbus(dwc_otg_core_if_t * core_if)
+-00438 {
+-00439         hprt0_data_t hprt0 = {.d32 = 0 };
+-00440         hprt0.d32 = dwc_otg_read_hprt0(core_if);
+-00441         DWC_PRINTF("Turn on VBUS for 1.1s, port power is %d\n", hprt0.b.prtpwr);
+-00442 
+-00443         if (hprt0.b.prtpwr == 0) {
+-00444                 hprt0.b.prtpwr = 1;
+-00445                 //DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
+-00446         }
+-00447         
+-00448         dwc_otg_adp_vbuson_timer_start(core_if);
+-00449 }
+-00450 
+-00458 void dwc_otg_adp_start(dwc_otg_core_if_t * core_if, uint8_t is_host)
+-00459 {
+-00460         gpwrdn_data_t gpwrdn;
+-00461 
+-00462         DWC_PRINTF("ADP Initial Start\n");
+-00463         core_if->adp.adp_started = 1;
+-00464 
+-00465         DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
+-00466         dwc_otg_disable_global_interrupts(core_if);
+-00467         if (is_host) {
+-00468                 DWC_PRINTF("HOST MODE\n");
+-00469                 /* Enable Power Down Logic Interrupt*/
+-00470                 gpwrdn.d32 = 0;
+-00471                 gpwrdn.b.pmuintsel = 1;
+-00472                 gpwrdn.b.pmuactv = 1;
+-00473                 DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
+-00474                 /* Initialize first ADP probe to obtain Ramp Time value */
+-00475                 core_if->adp.initial_probe = 1;
+-00476                 dwc_otg_adp_probe_start(core_if);
+-00477         } else {
+-00478                 gotgctl_data_t gotgctl;
+-00479                 gotgctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->gotgctl);
+-00480                 DWC_PRINTF("DEVICE MODE\n");
+-00481                 if (gotgctl.b.bsesvld == 0) {
+-00482                         /* Enable Power Down Logic Interrupt*/
+-00483                         gpwrdn.d32 = 0;
+-00484                         DWC_PRINTF("VBUS is not valid - start ADP probe\n");
+-00485                         gpwrdn.b.pmuintsel = 1;
+-00486                         gpwrdn.b.pmuactv = 1;
+-00487                         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
+-00488                         core_if->adp.initial_probe = 1;
+-00489                         dwc_otg_adp_probe_start(core_if);
+-00490                 } else {
+-00491                         DWC_PRINTF("VBUS is valid - initialize core as a Device\n");
+-00492                         core_if->op_state = B_PERIPHERAL;
+-00493                         dwc_otg_core_init(core_if);
+-00494                         dwc_otg_enable_global_interrupts(core_if);
+-00495                         cil_pcd_start(core_if);
+-00496                         dwc_otg_dump_global_registers(core_if);
+-00497                         dwc_otg_dump_dev_registers(core_if);
+-00498                 }
+-00499         }
+-00500 }
+-00501 
+-00502 void dwc_otg_adp_init(dwc_otg_core_if_t * core_if)
+-00503 {
+-00504         core_if->adp.adp_started = 0;
+-00505         core_if->adp.initial_probe = 0;
+-00506         core_if->adp.probe_timer_values[0] = -1;
+-00507         core_if->adp.probe_timer_values[1] = -1;
+-00508         core_if->adp.probe_enabled = 0;
+-00509         core_if->adp.sense_enabled = 0;
+-00510         core_if->adp.sense_timer_started = 0;
+-00511         core_if->adp.vbuson_timer_started = 0;
+-00512         core_if->adp.probe_counter = 0;
+-00513         core_if->adp.gpwrdn = 0;
+-00514         core_if->adp.attached = DWC_OTG_ADP_UNKOWN;
+-00515         /* Initialize timers */
+-00516         core_if->adp.sense_timer =
+-00517             DWC_TIMER_ALLOC("ADP SENSE TIMER", adp_sense_timeout, core_if);
+-00518         core_if->adp.vbuson_timer =
+-00519             DWC_TIMER_ALLOC("ADP VBUS ON TIMER", adp_vbuson_timeout, core_if);
+-00520         if (!core_if->adp.sense_timer || !core_if->adp.vbuson_timer)
+-00521         {
+-00522                 DWC_ERROR("Could not allocate memory for ADP timers\n");
+-00523         }
+-00524 }
+-00525 
+-00526 void dwc_otg_adp_remove(dwc_otg_core_if_t * core_if)
+-00527 {
+-00528         gpwrdn_data_t gpwrdn = { .d32 = 0 };
+-00529         gpwrdn.b.pmuintsel = 1;
+-00530         gpwrdn.b.pmuactv = 1;
+-00531         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
+-00532 
+-00533         if (core_if->adp.probe_enabled)         
+-00534                 dwc_otg_adp_probe_stop(core_if);
+-00535         if (core_if->adp.sense_enabled)         
+-00536                 dwc_otg_adp_sense_stop(core_if);
+-00537         if (core_if->adp.sense_timer_started)           
+-00538                 DWC_TIMER_CANCEL(core_if->adp.sense_timer);
+-00539         if (core_if->adp.vbuson_timer_started)          
+-00540                 DWC_TIMER_CANCEL(core_if->adp.vbuson_timer);
+-00541         DWC_TIMER_FREE(core_if->adp.sense_timer);
+-00542         DWC_TIMER_FREE(core_if->adp.vbuson_timer);
+-00543 }
+-00544 
+-00548 
+-00551 static uint32_t set_timer_value(dwc_otg_core_if_t * core_if, uint32_t val)
+-00552 {
+-00553         if (core_if->adp.probe_timer_values[0] == -1) {
+-00554                 core_if->adp.probe_timer_values[0] = val;
+-00555                 core_if->adp.probe_timer_values[1] = -1;
+-00556                 return 1;
+-00557         } else {
+-00558                 core_if->adp.probe_timer_values[1] =
+-00559                     core_if->adp.probe_timer_values[0];
+-00560                 core_if->adp.probe_timer_values[0] = val;
+-00561                 return 0;
+-00562         }
+-00563 }
+-00564 
+-00568 static uint32_t compare_timer_values(dwc_otg_core_if_t * core_if)
+-00569 {
+-00570         uint32_t diff;
+-00571         if (core_if->adp.probe_timer_values[0]>=core_if->adp.probe_timer_values[1])
+-00572                         diff = core_if->adp.probe_timer_values[0]-core_if->adp.probe_timer_values[1];
+-00573         else
+-00574                         diff = core_if->adp.probe_timer_values[1]-core_if->adp.probe_timer_values[0];           
+-00575         if(diff < 2) {
+-00576                 return 0;
+-00577         } else {
+-00578                 return 1;
+-00579         }
+-00580 }
+-00581 
+-00585 static int32_t dwc_otg_adp_handle_prb_intr(dwc_otg_core_if_t * core_if,
+-00586                                                  uint32_t val)
+-00587 {
+-00588         adpctl_data_t adpctl = {.d32 = 0 };
+-00589         gpwrdn_data_t gpwrdn, temp;
+-00590         adpctl.d32 = val;
+-00591 
+-00592         temp.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
+-00593         core_if->adp.probe_counter++;
+-00594         core_if->adp.gpwrdn = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
+-00595         if (adpctl.b.rtim == 0 && !temp.b.idsts){
+-00596                 DWC_PRINTF("RTIM value is 0\n");        
+-00597                 goto exit;
+-00598         }
+-00599         if (set_timer_value(core_if, adpctl.b.rtim) &&
+-00600             core_if->adp.initial_probe) {
+-00601                 core_if->adp.initial_probe = 0;
+-00602                 dwc_otg_adp_probe_stop(core_if);
+-00603                 gpwrdn.d32 = 0;
+-00604                 gpwrdn.b.pmuactv = 1;
+-00605                 gpwrdn.b.pmuintsel = 1;
+-00606                 DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
+-00607                 DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
+-00608 
+-00609                 /* check which value is for device mode and which for Host mode */
+-00610                 if (!temp.b.idsts) {    /* considered host mode value is 0 */
+-00611                         /*
+-00612                          * Turn on VBUS after initial ADP probe.
+-00613                          */
+-00614                         core_if->op_state = A_HOST;
+-00615                         dwc_otg_enable_global_interrupts(core_if);
+-00616                         DWC_SPINUNLOCK(core_if->lock);
+-00617                         cil_hcd_start(core_if);
+-00618                         dwc_otg_adp_turnon_vbus(core_if);
+-00619                         DWC_SPINLOCK(core_if->lock);
+-00620                 } else {
+-00621                         /*
+-00622                          * Initiate SRP after initial ADP probe.
+-00623                          */
+-00624                         dwc_otg_enable_global_interrupts(core_if);
+-00625                         dwc_otg_initiate_srp(core_if);
+-00626                 }
+-00627         } else if (core_if->adp.probe_counter > 2){
+-00628                 gpwrdn.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
+-00629                 if (compare_timer_values(core_if)) {
+-00630                         DWC_PRINTF("Difference in timer values !!! \n");
+-00631 //                      core_if->adp.attached = DWC_OTG_ADP_ATTACHED;
+-00632                         dwc_otg_adp_probe_stop(core_if);
+-00633 
+-00634                         /* Power on the core */
+-00635                         if (core_if->power_down == 2) {
+-00636                                 gpwrdn.b.pwrdnswtch = 1;
+-00637                                 DWC_MODIFY_REG32(&core_if->core_global_regs->
+-00638                                                  gpwrdn, 0, gpwrdn.d32);
+-00639                         }
+-00640 
+-00641                         /* check which value is for device mode and which for Host mode */
+-00642                         if (!temp.b.idsts) {    /* considered host mode value is 0 */
+-00643                                 /* Disable Interrupt from Power Down Logic */
+-00644                                 gpwrdn.d32 = 0;
+-00645                                 gpwrdn.b.pmuintsel = 1;
+-00646                                 gpwrdn.b.pmuactv = 1;
+-00647                                 DWC_MODIFY_REG32(&core_if->core_global_regs->
+-00648                                                  gpwrdn, gpwrdn.d32, 0);
+-00649 
+-00650                                 /*
+-00651                                  * Initialize the Core for Host mode.
+-00652                                  */
+-00653                                 core_if->op_state = A_HOST;
+-00654                                 dwc_otg_core_init(core_if);
+-00655                                 dwc_otg_enable_global_interrupts(core_if);
+-00656                                 cil_hcd_start(core_if);
+-00657                         } else {
+-00658                                 gotgctl_data_t gotgctl;
+-00659                                 /* Mask SRP detected interrupt from Power Down Logic */
+-00660                                 gpwrdn.d32 = 0;
+-00661                                 gpwrdn.b.srp_det_msk = 1;
+-00662                                 DWC_MODIFY_REG32(&core_if->core_global_regs->
+-00663                                                  gpwrdn, gpwrdn.d32, 0);
+-00664 
+-00665                                 /* Disable Power Down Logic */
+-00666                                 gpwrdn.d32 = 0;
+-00667                                 gpwrdn.b.pmuintsel = 1;
+-00668                                 gpwrdn.b.pmuactv = 1;
+-00669                                 DWC_MODIFY_REG32(&core_if->core_global_regs->
+-00670                                                  gpwrdn, gpwrdn.d32, 0);
+-00671 
+-00672                                 /*
+-00673                                  * Initialize the Core for Device mode.
+-00674                                  */
+-00675                                 core_if->op_state = B_PERIPHERAL;
+-00676                                 dwc_otg_core_init(core_if);
+-00677                                 dwc_otg_enable_global_interrupts(core_if);
+-00678                                 cil_pcd_start(core_if);
+-00679 
+-00680                                 gotgctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->gotgctl);
+-00681                                 if (!gotgctl.b.bsesvld) {
+-00682                                         dwc_otg_initiate_srp(core_if);
+-00683                                 }
+-00684                         }
+-00685                 }
+-00686                 if (core_if->power_down == 2) {
+-00687                         if (gpwrdn.b.bsessvld) {
+-00688                                 /* Mask SRP detected interrupt from Power Down Logic */
+-00689                                 gpwrdn.d32 = 0;
+-00690                                 gpwrdn.b.srp_det_msk = 1;
+-00691                                 DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
+-00692                                 
+-00693                                 /* Disable Power Down Logic */
+-00694                                 gpwrdn.d32 = 0;
+-00695                                 gpwrdn.b.pmuactv = 1;
+-00696                                 DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
+-00697 
+-00698                                 /*
+-00699                                  * Initialize the Core for Device mode.
+-00700                                  */
+-00701                                 core_if->op_state = B_PERIPHERAL;
+-00702                                 dwc_otg_core_init(core_if);
+-00703                                 dwc_otg_enable_global_interrupts(core_if);
+-00704                                 cil_pcd_start(core_if);
+-00705                         }
+-00706                 }
+-00707         }
+-00708 exit:
+-00709         /* Clear interrupt */
+-00710         adpctl.d32 = dwc_otg_adp_read_reg(core_if);
+-00711         adpctl.b.adp_prb_int = 1;
+-00712         dwc_otg_adp_write_reg(core_if, adpctl.d32);
+-00713 
+-00714         return 0;
+-00715 }
+-00716 
+-00720 static int32_t dwc_otg_adp_handle_sns_intr(dwc_otg_core_if_t * core_if)
+-00721 {
+-00722         adpctl_data_t adpctl;
+-00723         /* Stop ADP Sense timer */
+-00724         DWC_TIMER_CANCEL(core_if->adp.sense_timer);
+-00725 
+-00726         /* Restart ADP Sense timer */
+-00727         dwc_otg_adp_sense_timer_start(core_if);
+-00728         
+-00729         /* Clear interrupt */
+-00730         adpctl.d32 = dwc_otg_adp_read_reg(core_if);
+-00731         adpctl.b.adp_sns_int = 1;
+-00732         dwc_otg_adp_write_reg(core_if, adpctl.d32);
+-00733 
+-00734         return 0;
+-00735 }
+-00736 
+-00740 static int32_t dwc_otg_adp_handle_prb_tmout_intr(dwc_otg_core_if_t * core_if,
+-00741                                                  uint32_t val)
+-00742 {
+-00743         adpctl_data_t adpctl = {.d32 = 0 };
+-00744         adpctl.d32 = val;
+-00745         set_timer_value(core_if, adpctl.b.rtim);
+-00746         
+-00747         /* Clear interrupt */
+-00748         adpctl.d32 = dwc_otg_adp_read_reg(core_if);
+-00749         adpctl.b.adp_tmout_int = 1;
+-00750         dwc_otg_adp_write_reg(core_if, adpctl.d32);
+-00751 
+-00752         return 0;
+-00753 }
+-00754 
+-00759 int32_t dwc_otg_adp_handle_intr(dwc_otg_core_if_t * core_if)
+-00760 {
+-00761         int retval = 0;
+-00762         adpctl_data_t adpctl = {.d32 = 0};
+-00763 
+-00764         adpctl.d32 = dwc_otg_adp_read_reg(core_if);
+-00765         DWC_PRINTF("ADPCTL = %08x\n",adpctl.d32);
+-00766 
+-00767         if (adpctl.b.adp_sns_int & adpctl.b.adp_sns_int_msk) {
+-00768                 DWC_PRINTF("ADP Sense interrupt\n");
+-00769                 retval |= dwc_otg_adp_handle_sns_intr(core_if);
+-00770         }
+-00771         if (adpctl.b.adp_tmout_int & adpctl.b.adp_tmout_int_msk) {
+-00772                 DWC_PRINTF("ADP timeout interrupt\n");
+-00773                 retval |= dwc_otg_adp_handle_prb_tmout_intr(core_if, adpctl.d32);
+-00774         }
+-00775         if (adpctl.b.adp_prb_int & adpctl.b.adp_prb_int_msk) {
+-00776                 DWC_PRINTF("ADP Probe interrupt\n");
+-00777                 adpctl.b.adp_prb_int = 1;       
+-00778                 retval |= dwc_otg_adp_handle_prb_intr(core_if, adpctl.d32);
+-00779         }
+-00780 
+-00781 //      dwc_otg_adp_modify_reg(core_if, adpctl.d32, 0);
+-00782         //dwc_otg_adp_write_reg(core_if, adpctl.d32);
+-00783         DWC_PRINTF("RETURN FROM ADP ISR\n");
+-00784 
+-00785         return retval;
+-00786 }
+-00787 
+-00792 int32_t dwc_otg_adp_handle_srp_intr(dwc_otg_core_if_t * core_if)
+-00793 {
+-00794 
+-00795 #ifndef DWC_HOST_ONLY
+-00796         hprt0_data_t hprt0;
+-00797         gpwrdn_data_t gpwrdn;
+-00798         DWC_DEBUGPL(DBG_ANY, "++ Power Down Logic Session Request Interrupt++\n");
+-00799 
+-00800         gpwrdn.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
+-00801         /* check which value is for device mode and which for Host mode */
+-00802         if (!gpwrdn.b.idsts) {  /* considered host mode value is 0 */
+-00803                 DWC_PRINTF("SRP: Host mode\n");
+-00804 
+-00805                 if (core_if->adp_enable) {
+-00806                         dwc_otg_adp_probe_stop(core_if);
+-00807 
+-00808                         /* Power on the core */
+-00809                         if (core_if->power_down == 2) {
+-00810                                 gpwrdn.b.pwrdnswtch = 1;
+-00811                                 DWC_MODIFY_REG32(&core_if->core_global_regs->
+-00812                                                  gpwrdn, 0, gpwrdn.d32);
+-00813                         }
+-00814 
+-00815                         core_if->op_state = A_HOST;
+-00816                         dwc_otg_core_init(core_if);
+-00817                         dwc_otg_enable_global_interrupts(core_if);
+-00818                         cil_hcd_start(core_if);
+-00819                 }
+-00820 
+-00821                 /* Turn on the port power bit. */
+-00822                 hprt0.d32 = dwc_otg_read_hprt0(core_if);
+-00823                 hprt0.b.prtpwr = 1;
+-00824                 DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
+-00825 
+-00826                 /* Start the Connection timer. So a message can be displayed
+-00827                  * if connect does not occur within 10 seconds. */
+-00828                 cil_hcd_session_start(core_if);
+-00829         } else {
+-00830                 DWC_PRINTF("SRP: Device mode %s\n", __FUNCTION__);
+-00831                 if (core_if->adp_enable) {
+-00832                         dwc_otg_adp_probe_stop(core_if);
+-00833 
+-00834                         /* Power on the core */
+-00835                         if (core_if->power_down == 2) {
+-00836                                 gpwrdn.b.pwrdnswtch = 1;
+-00837                                 DWC_MODIFY_REG32(&core_if->core_global_regs->
+-00838                                                  gpwrdn, 0, gpwrdn.d32);
+-00839                         }
+-00840 
+-00841                         gpwrdn.d32 = 0;
+-00842                         gpwrdn.b.pmuactv = 0;
+-00843                         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0,
+-00844                                          gpwrdn.d32);
+-00845 
+-00846                         core_if->op_state = B_PERIPHERAL;
+-00847                         dwc_otg_core_init(core_if);
+-00848                         dwc_otg_enable_global_interrupts(core_if);
+-00849                         cil_pcd_start(core_if);
+-00850                 }
+-00851         }
+-00852 #endif
+-00853         return 1;
+-00854 }
+-
                                                                                Generated on Thu Oct 27 03:56:37 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__adp_8c.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/dwc__otg__adp_8c.html 2013-07-26 19:34:39.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,482 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_adp.c File Reference +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                dwc_otg_adp.c File Reference

                                                                                This file contains the most of the Attach Detect Protocol implementation for the driver to support OTG Rev2.0. More... +-

                                                                                +-#include "dwc_os.h"
                                                                                +-#include "dwc_otg_regs.h"
                                                                                +-#include "dwc_otg_cil.h"
                                                                                +-#include "dwc_otg_adp.h"
                                                                                +- +-

                                                                                +-Go to the source code of this file. +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-

                                                                                Functions

                                                                                +-void dwc_otg_adp_write_reg (dwc_otg_core_if_t *core_if, uint32_t value)
                                                                                 Attach Detect Protocol functions.
                                                                                +-uint32_t dwc_otg_adp_read_reg (dwc_otg_core_if_t *core_if)
                                                                                 Function is called to read ADP registers.
                                                                                +-uint32_t dwc_otg_adp_read_reg_filter (dwc_otg_core_if_t *core_if)
                                                                                 Function is called to read ADPCTL register and filter Write-clear bits.
                                                                                +-void dwc_otg_adp_modify_reg (dwc_otg_core_if_t *core_if, uint32_t clr, uint32_t set)
                                                                                 Function is called to write ADP registers.
                                                                                +-void adp_sense_timeout (void *ptr)
                                                                                void adp_vbuson_timeout (void *ptr)
                                                                                 This function is called when the ADP vbus timer expires.
                                                                                void dwc_otg_adp_vbuson_timer_start (dwc_otg_core_if_t *core_if)
                                                                                 Start the ADP Initial Probe timer to detect if Port Connected interrupt is not asserted within 1.1 seconds.
                                                                                uint32_t dwc_otg_adp_probe_start (dwc_otg_core_if_t *core_if)
                                                                                 Starts the ADP Probing.
                                                                                void dwc_otg_adp_sense_timer_start (dwc_otg_core_if_t *core_if)
                                                                                 Starts the ADP Sense timer to detect if ADP Sense interrupt is not asserted within 3 seconds.
                                                                                uint32_t dwc_otg_adp_sense_start (dwc_otg_core_if_t *core_if)
                                                                                 Starts the ADP Sense.
                                                                                uint32_t dwc_otg_adp_probe_stop (dwc_otg_core_if_t *core_if)
                                                                                 Stops the ADP Probing.
                                                                                uint32_t dwc_otg_adp_sense_stop (dwc_otg_core_if_t *core_if)
                                                                                 Stops the ADP Sensing.
                                                                                void dwc_otg_adp_turnon_vbus (dwc_otg_core_if_t *core_if)
                                                                                 Called to turn on the VBUS after initial ADP probe in host mode.
                                                                                void dwc_otg_adp_start (dwc_otg_core_if_t *core_if, uint8_t is_host)
                                                                                 Called right after driver is loaded to perform initial actions for ADP.
                                                                                +-void dwc_otg_adp_init (dwc_otg_core_if_t *core_if)
                                                                                +-void dwc_otg_adp_remove (dwc_otg_core_if_t *core_if)
                                                                                +-uint32_t set_timer_value (dwc_otg_core_if_t *core_if, uint32_t val)
                                                                                 This function sets Ramp Timer values.
                                                                                +-uint32_t compare_timer_values (dwc_otg_core_if_t *core_if)
                                                                                 This function compares Ramp Timer values.
                                                                                +-int32_t dwc_otg_adp_handle_prb_intr (dwc_otg_core_if_t *core_if, uint32_t val)
                                                                                 This function handles ADP Probe Interrupts.
                                                                                +-int32_t dwc_otg_adp_handle_sns_intr (dwc_otg_core_if_t *core_if)
                                                                                 This function hadles ADP Sense Interrupt.
                                                                                +-int32_t dwc_otg_adp_handle_prb_tmout_intr (dwc_otg_core_if_t *core_if, uint32_t val)
                                                                                 This function handles ADP Probe Interrupts.
                                                                                +-int32_t dwc_otg_adp_handle_intr (dwc_otg_core_if_t *core_if)
                                                                                 ADP Interrupt handler.
                                                                                int32_t dwc_otg_adp_handle_srp_intr (dwc_otg_core_if_t *core_if)
                                                                                +-

                                                                                Detailed Description

                                                                                +-This file contains the most of the Attach Detect Protocol implementation for the driver to support OTG Rev2.0. +-

                                                                                +- +-

                                                                                +-Definition in file dwc_otg_adp.c.

                                                                                Function Documentation

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                void adp_vbuson_timeout ( void *  ptr  )  [static]
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This function is called when the ADP vbus timer expires. +-

                                                                                +-Timeout is 1.1s. +-

                                                                                +-Definition at line 119 of file dwc_otg_adp.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                void dwc_otg_adp_vbuson_timer_start ( dwc_otg_core_if_t *  core_if  ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Start the ADP Initial Probe timer to detect if Port Connected interrupt is not asserted within 1.1 seconds. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +-
                                                                                core_if the pointer to core_if strucure.
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 187 of file dwc_otg_adp.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                uint32_t dwc_otg_adp_probe_start ( dwc_otg_core_if_t *  core_if  ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Starts the ADP Probing. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +-
                                                                                core_if the pointer to core_if structure.
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 296 of file dwc_otg_adp.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                void dwc_otg_adp_sense_timer_start ( dwc_otg_core_if_t *  core_if  ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Starts the ADP Sense timer to detect if ADP Sense interrupt is not asserted within 3 seconds. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +-
                                                                                core_if the pointer to core_if strucure.
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 346 of file dwc_otg_adp.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                uint32_t dwc_otg_adp_sense_start ( dwc_otg_core_if_t *  core_if  ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Starts the ADP Sense. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +-
                                                                                core_if the pointer to core_if strucure.
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 357 of file dwc_otg_adp.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                uint32_t dwc_otg_adp_probe_stop ( dwc_otg_core_if_t *  core_if  ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Stops the ADP Probing. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +-
                                                                                core_if the pointer to core_if strucure.
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 393 of file dwc_otg_adp.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                uint32_t dwc_otg_adp_sense_stop ( dwc_otg_core_if_t *  core_if  ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Stops the ADP Sensing. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +-
                                                                                core_if the pointer to core_if strucure.
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 416 of file dwc_otg_adp.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                void dwc_otg_adp_turnon_vbus ( dwc_otg_core_if_t *  core_if  ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Called to turn on the VBUS after initial ADP probe in host mode. +-

                                                                                +-If port power was already enabled in cil_hcd_start function then only schedule a timer.

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +-
                                                                                core_if the pointer to core_if structure.
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 437 of file dwc_otg_adp.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                void dwc_otg_adp_start ( dwc_otg_core_if_t *  core_if,
                                                                                uint8_t  is_host
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Called right after driver is loaded to perform initial actions for ADP. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +-
                                                                                core_if the pointer to core_if structure.
                                                                                is_host - flag for current mode of operation either from GINTSTS or GPWRDN
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 458 of file dwc_otg_adp.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                int32_t dwc_otg_adp_handle_srp_intr ( dwc_otg_core_if_t *  core_if  ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +-
                                                                                core_if Programming view of DWC_otg controller.
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 792 of file dwc_otg_adp.c.

                                                                                +-

                                                                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__adp_8h-source.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/dwc__otg__adp_8h-source.html 2013-07-26 19:34:39.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,80 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_adp.h Source File +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                dwc_otg_adp.h

                                                                                Go to the documentation of this file.
                                                                                00001 /* ==========================================================================
+-00002  * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_adp.h $
+-00003  * $Revision: #7 $
+-00004  * $Date: 2011/10/24 $
+-00005  * $Change: 1871159 $
+-00006  *
+-00007  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
+-00008  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
+-00009  * otherwise expressly agreed to in writing between Synopsys and you.
+-00010  *
+-00011  * The Software IS NOT an item of Licensed Software or Licensed Product under
+-00012  * any End User Software License Agreement or Agreement for Licensed Product
+-00013  * with Synopsys or any supplement thereto. You are permitted to use and
+-00014  * redistribute this Software in source and binary forms, with or without
+-00015  * modification, provided that redistributions of source code must retain this
+-00016  * notice. You may not view, use, disclose, copy or distribute this file or
+-00017  * any information contained herein except pursuant to this license grant from
+-00018  * Synopsys. If you do not agree with this notice, including the disclaimer
+-00019  * below, then you are not authorized to use the Software.
+-00020  *
+-00021  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
+-00022  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+-00023  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+-00024  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
+-00025  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+-00026  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+-00027  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+-00028  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+-00029  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+-00030  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+-00031  * DAMAGE.
+-00032  * ========================================================================== */
+-00033 
+-00034 #ifndef __DWC_OTG_ADP_H__
+-00035 #define __DWC_OTG_ADP_H__
+-00036 
+-00045 #define DWC_OTG_ADP_UNATTACHED  0
+-00046 #define DWC_OTG_ADP_ATTACHED    1
+-00047 #define DWC_OTG_ADP_UNKOWN      2
+-00048 
+-00049 typedef struct dwc_otg_adp {
+-00050         uint32_t adp_started;   
+-00051         uint32_t initial_probe;
+-00052         int32_t probe_timer_values[2];
+-00053         uint32_t probe_enabled;
+-00054         uint32_t sense_enabled;
+-00055         dwc_timer_t *sense_timer;
+-00056         uint32_t sense_timer_started;
+-00057         dwc_timer_t *vbuson_timer;
+-00058         uint32_t vbuson_timer_started;
+-00059         uint32_t attached;
+-00060         uint32_t probe_counter;
+-00061         uint32_t gpwrdn;
+-00062 } dwc_otg_adp_t;
+-00063 
+-00068 extern void dwc_otg_adp_write_reg(dwc_otg_core_if_t * core_if, uint32_t value);
+-00069 extern uint32_t dwc_otg_adp_read_reg(dwc_otg_core_if_t * core_if);
+-00070 extern uint32_t dwc_otg_adp_probe_start(dwc_otg_core_if_t * core_if);
+-00071 extern uint32_t dwc_otg_adp_sense_start(dwc_otg_core_if_t * core_if);
+-00072 extern uint32_t dwc_otg_adp_probe_stop(dwc_otg_core_if_t * core_if);
+-00073 extern uint32_t dwc_otg_adp_sense_stop(dwc_otg_core_if_t * core_if);
+-00074 extern void dwc_otg_adp_start(dwc_otg_core_if_t * core_if, uint8_t is_host);
+-00075 extern void dwc_otg_adp_init(dwc_otg_core_if_t * core_if);
+-00076 extern void dwc_otg_adp_remove(dwc_otg_core_if_t * core_if);
+-00077 extern int32_t dwc_otg_adp_handle_intr(dwc_otg_core_if_t * core_if);
+-00078 extern int32_t dwc_otg_adp_handle_srp_intr(dwc_otg_core_if_t * core_if);
+-00079 
+-00080 #endif //__DWC_OTG_ADP_H__
+-
                                                                                Generated on Thu Oct 27 03:56:37 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__adp_8h.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/dwc__otg__adp_8h.html 2013-07-26 19:34:39.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,308 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_adp.h File Reference +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                dwc_otg_adp.h File Reference

                                                                                This file contains the Attach Detect Protocol interfaces and defines (functions) and structures for Linux. More... +-

                                                                                +- +-

                                                                                +-Go to the source code of this file. +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-

                                                                                Data Structures

                                                                                struct  dwc_otg_adp

                                                                                Defines

                                                                                +-#define DWC_OTG_ADP_UNATTACHED   0
                                                                                +-#define DWC_OTG_ADP_ATTACHED   1
                                                                                +-#define DWC_OTG_ADP_UNKOWN   2

                                                                                Typedefs

                                                                                +-typedef dwc_otg_adp dwc_otg_adp_t

                                                                                Functions

                                                                                +-void dwc_otg_adp_write_reg (dwc_otg_core_if_t *core_if, uint32_t value)
                                                                                 Attach Detect Protocol functions.
                                                                                +-uint32_t dwc_otg_adp_read_reg (dwc_otg_core_if_t *core_if)
                                                                                 Function is called to read ADP registers.
                                                                                uint32_t dwc_otg_adp_probe_start (dwc_otg_core_if_t *core_if)
                                                                                 Starts the ADP Probing.
                                                                                uint32_t dwc_otg_adp_sense_start (dwc_otg_core_if_t *core_if)
                                                                                 Starts the ADP Sense.
                                                                                uint32_t dwc_otg_adp_probe_stop (dwc_otg_core_if_t *core_if)
                                                                                 Stops the ADP Probing.
                                                                                uint32_t dwc_otg_adp_sense_stop (dwc_otg_core_if_t *core_if)
                                                                                 Stops the ADP Sensing.
                                                                                void dwc_otg_adp_start (dwc_otg_core_if_t *core_if, uint8_t is_host)
                                                                                 Called right after driver is loaded to perform initial actions for ADP.
                                                                                +-void dwc_otg_adp_init (dwc_otg_core_if_t *core_if)
                                                                                +-void dwc_otg_adp_remove (dwc_otg_core_if_t *core_if)
                                                                                +-int32_t dwc_otg_adp_handle_intr (dwc_otg_core_if_t *core_if)
                                                                                 ADP Interrupt handler.
                                                                                int32_t dwc_otg_adp_handle_srp_intr (dwc_otg_core_if_t *core_if)
                                                                                +-

                                                                                Detailed Description

                                                                                +-This file contains the Attach Detect Protocol interfaces and defines (functions) and structures for Linux. +-

                                                                                +- +-

                                                                                +-Definition in file dwc_otg_adp.h.

                                                                                Function Documentation

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                uint32_t dwc_otg_adp_probe_start ( dwc_otg_core_if_t *  core_if  ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Starts the ADP Probing. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +-
                                                                                core_if the pointer to core_if structure.
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 296 of file dwc_otg_adp.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                uint32_t dwc_otg_adp_sense_start ( dwc_otg_core_if_t *  core_if  ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Starts the ADP Sense. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +-
                                                                                core_if the pointer to core_if strucure.
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 357 of file dwc_otg_adp.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                uint32_t dwc_otg_adp_probe_stop ( dwc_otg_core_if_t *  core_if  ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Stops the ADP Probing. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +-
                                                                                core_if the pointer to core_if strucure.
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 393 of file dwc_otg_adp.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                uint32_t dwc_otg_adp_sense_stop ( dwc_otg_core_if_t *  core_if  ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Stops the ADP Sensing. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +-
                                                                                core_if the pointer to core_if strucure.
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 416 of file dwc_otg_adp.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                void dwc_otg_adp_start ( dwc_otg_core_if_t *  core_if,
                                                                                uint8_t  is_host
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Called right after driver is loaded to perform initial actions for ADP. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +-
                                                                                core_if the pointer to core_if structure.
                                                                                is_host - flag for current mode of operation either from GINTSTS or GPWRDN
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 458 of file dwc_otg_adp.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                int32_t dwc_otg_adp_handle_srp_intr ( dwc_otg_core_if_t *  core_if  ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +-
                                                                                core_if Programming view of DWC_otg controller.
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 792 of file dwc_otg_adp.c.

                                                                                +-

                                                                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__attr_8c-source.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/dwc__otg__attr_8c-source.html 2013-07-26 19:34:39.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,929 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_attr.c Source File +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                dwc_otg_attr.c

                                                                                Go to the documentation of this file.
                                                                                00001 /* ==========================================================================
+-00002  * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_attr.c $
+-00003  * $Revision: #44 $
+-00004  * $Date: 2010/11/29 $
+-00005  * $Change: 1636033 $
+-00006  *
+-00007  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
+-00008  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
+-00009  * otherwise expressly agreed to in writing between Synopsys and you.
+-00010  *
+-00011  * The Software IS NOT an item of Licensed Software or Licensed Product under
+-00012  * any End User Software License Agreement or Agreement for Licensed Product
+-00013  * with Synopsys or any supplement thereto. You are permitted to use and
+-00014  * redistribute this Software in source and binary forms, with or without
+-00015  * modification, provided that redistributions of source code must retain this
+-00016  * notice. You may not view, use, disclose, copy or distribute this file or
+-00017  * any information contained herein except pursuant to this license grant from
+-00018  * Synopsys. If you do not agree with this notice, including the disclaimer
+-00019  * below, then you are not authorized to use the Software.
+-00020  *
+-00021  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
+-00022  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+-00023  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+-00024  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
+-00025  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+-00026  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+-00027  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+-00028  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+-00029  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+-00030  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+-00031  * DAMAGE.
+-00032  * ========================================================================== */
+-00033 
+-00311 #include "dwc_otg_os_dep.h"
+-00312 #include "dwc_os.h"
+-00313 #include "dwc_otg_driver.h"
+-00314 #include "dwc_otg_attr.h"
+-00315 #include "dwc_otg_core_if.h"
+-00316 #include "dwc_otg_pcd_if.h"
+-00317 #include "dwc_otg_hcd_if.h"
+-00318 
+-00319 /*
+-00320  * MACROs for defining sysfs attribute
+-00321  */
+-00322 #ifdef LM_INTERFACE
+-00323 
+-00324 #define DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_string_) \
+-00325 static ssize_t _otg_attr_name_##_show (struct device *_dev, struct device_attribute *attr, char *buf) \
+-00326 { \
+-00327         struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev); \
+-00328         dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);             \
+-00329         uint32_t val; \
+-00330         val = dwc_otg_get_##_otg_attr_name_ (otg_dev->core_if); \
+-00331         return sprintf (buf, "%s = 0x%x\n", _string_, val); \
+-00332 }
+-00333 #define DWC_OTG_DEVICE_ATTR_BITFIELD_STORE(_otg_attr_name_,_string_) \
+-00334 static ssize_t _otg_attr_name_##_store (struct device *_dev, struct device_attribute *attr, \
+-00335                                         const char *buf, size_t count) \
+-00336 { \
+-00337         struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev); \
+-00338         dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev); \
+-00339         uint32_t set = simple_strtoul(buf, NULL, 16); \
+-00340         dwc_otg_set_##_otg_attr_name_(otg_dev->core_if, set);\
+-00341         return count; \
+-00342 }
+-00343 
+-00344 #elif defined(PCI_INTERFACE)
+-00345 
+-00346 #define DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_string_) \
+-00347 static ssize_t _otg_attr_name_##_show (struct device *_dev, struct device_attribute *attr, char *buf) \
+-00348 { \
+-00349         dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);      \
+-00350         uint32_t val; \
+-00351         val = dwc_otg_get_##_otg_attr_name_ (otg_dev->core_if); \
+-00352         return sprintf (buf, "%s = 0x%x\n", _string_, val); \
+-00353 }
+-00354 #define DWC_OTG_DEVICE_ATTR_BITFIELD_STORE(_otg_attr_name_,_string_) \
+-00355 static ssize_t _otg_attr_name_##_store (struct device *_dev, struct device_attribute *attr, \
+-00356                                         const char *buf, size_t count) \
+-00357 { \
+-00358         dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);  \
+-00359         uint32_t set = simple_strtoul(buf, NULL, 16); \
+-00360         dwc_otg_set_##_otg_attr_name_(otg_dev->core_if, set);\
+-00361         return count; \
+-00362 }
+-00363 
+-00364 #endif
+-00365 
+-00366 /*
+-00367  * MACROs for defining sysfs attribute for 32-bit registers
+-00368  */
+-00369 #ifdef LM_INTERFACE
+-00370 #define DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_string_) \
+-00371 static ssize_t _otg_attr_name_##_show (struct device *_dev, struct device_attribute *attr, char *buf) \
+-00372 { \
+-00373         struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev); \
+-00374         dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev); \
+-00375         uint32_t val; \
+-00376         val = dwc_otg_get_##_otg_attr_name_ (otg_dev->core_if); \
+-00377         return sprintf (buf, "%s = 0x%08x\n", _string_, val); \
+-00378 }
+-00379 #define DWC_OTG_DEVICE_ATTR_REG_STORE(_otg_attr_name_,_string_) \
+-00380 static ssize_t _otg_attr_name_##_store (struct device *_dev, struct device_attribute *attr, \
+-00381                                         const char *buf, size_t count) \
+-00382 { \
+-00383         struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev); \
+-00384         dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev); \
+-00385         uint32_t val = simple_strtoul(buf, NULL, 16); \
+-00386         dwc_otg_set_##_otg_attr_name_ (otg_dev->core_if, val); \
+-00387         return count; \
+-00388 }
+-00389 #elif defined(PCI_INTERFACE)
+-00390 #define DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_string_) \
+-00391 static ssize_t _otg_attr_name_##_show (struct device *_dev, struct device_attribute *attr, char *buf) \
+-00392 { \
+-00393         dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);  \
+-00394         uint32_t val; \
+-00395         val = dwc_otg_get_##_otg_attr_name_ (otg_dev->core_if); \
+-00396         return sprintf (buf, "%s = 0x%08x\n", _string_, val); \
+-00397 }
+-00398 #define DWC_OTG_DEVICE_ATTR_REG_STORE(_otg_attr_name_,_string_) \
+-00399 static ssize_t _otg_attr_name_##_store (struct device *_dev, struct device_attribute *attr, \
+-00400                                         const char *buf, size_t count) \
+-00401 { \
+-00402         dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);  \
+-00403         uint32_t val = simple_strtoul(buf, NULL, 16); \
+-00404         dwc_otg_set_##_otg_attr_name_ (otg_dev->core_if, val); \
+-00405         return count; \
+-00406 }
+-00407 
+-00408 #endif
+-00409 
+-00410 #define DWC_OTG_DEVICE_ATTR_BITFIELD_RW(_otg_attr_name_,_string_) \
+-00411 DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_string_) \
+-00412 DWC_OTG_DEVICE_ATTR_BITFIELD_STORE(_otg_attr_name_,_string_) \
+-00413 DEVICE_ATTR(_otg_attr_name_,0644,_otg_attr_name_##_show,_otg_attr_name_##_store);
+-00414 
+-00415 #define DWC_OTG_DEVICE_ATTR_BITFIELD_RO(_otg_attr_name_,_string_) \
+-00416 DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_string_) \
+-00417 DEVICE_ATTR(_otg_attr_name_,0444,_otg_attr_name_##_show,NULL);
+-00418 
+-00419 #define DWC_OTG_DEVICE_ATTR_REG32_RW(_otg_attr_name_,_addr_,_string_) \
+-00420 DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_string_) \
+-00421 DWC_OTG_DEVICE_ATTR_REG_STORE(_otg_attr_name_,_string_) \
+-00422 DEVICE_ATTR(_otg_attr_name_,0644,_otg_attr_name_##_show,_otg_attr_name_##_store);
+-00423 
+-00424 #define DWC_OTG_DEVICE_ATTR_REG32_RO(_otg_attr_name_,_addr_,_string_) \
+-00425 DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_string_) \
+-00426 DEVICE_ATTR(_otg_attr_name_,0444,_otg_attr_name_##_show,NULL);
+-00427 
+-00434 static ssize_t regoffset_show(struct device *_dev,
+-00435                               struct device_attribute *attr, char *buf)
+-00436 {
+-00437 #ifdef LM_INTERFACE
+-00438         struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
+-00439         dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
+-00440 #elif defined(PCI_INTERFACE)
+-00441         dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
+-00442 #endif
+-00443 
+-00444         return snprintf(buf, sizeof("0xFFFFFFFF\n") + 1, "0x%08x\n",
+-00445                         otg_dev->os_dep.reg_offset);
+-00446 }
+-00447 
+-00451 static ssize_t regoffset_store(struct device *_dev,
+-00452                                struct device_attribute *attr,
+-00453                                const char *buf, size_t count)
+-00454 {
+-00455 #ifdef LM_INTERFACE
+-00456         struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
+-00457         dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
+-00458 #elif defined(PCI_INTERFACE)
+-00459         dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
+-00460 #endif
+-00461 
+-00462         uint32_t offset = simple_strtoul(buf, NULL, 16);
+-00463 #ifdef LM_INTERFACE
+-00464         if (offset < SZ_256K) {
+-00465 #elif  defined(PCI_INTERFACE)
+-00466         if (offset < 0x00040000) {
+-00467 #endif
+-00468                 otg_dev->os_dep.reg_offset = offset;
+-00469         } else {
+-00470                 dev_err(_dev, "invalid offset\n");
+-00471         }
+-00472 
+-00473         return count;
+-00474 }
+-00475 
+-00476 DEVICE_ATTR(regoffset, S_IRUGO | S_IWUSR, regoffset_show, regoffset_store);
+-00477 
+-00482 static ssize_t regvalue_show(struct device *_dev,
+-00483                              struct device_attribute *attr, char *buf)
+-00484 {
+-00485 #ifdef LM_INTERFACE
+-00486         struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
+-00487         dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
+-00488 #elif defined(PCI_INTERFACE)
+-00489         dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
+-00490 #endif
+-00491 
+-00492         uint32_t val;
+-00493         volatile uint32_t *addr;
+-00494 
+-00495         if (otg_dev->os_dep.reg_offset != 0xFFFFFFFF && 0 != otg_dev->os_dep.base) {
+-00496                 /* Calculate the address */
+-00497                 addr = (uint32_t *) (otg_dev->os_dep.reg_offset +
+-00498                                      (uint8_t *) otg_dev->os_dep.base);
+-00499                 val = DWC_READ_REG32(addr);
+-00500                 return snprintf(buf,
+-00501                                 sizeof("Reg@0xFFFFFFFF = 0xFFFFFFFF\n") + 1,
+-00502                                 "Reg@0x%06x = 0x%08x\n", otg_dev->os_dep.reg_offset,
+-00503                                 val);
+-00504         } else {
+-00505                 dev_err(_dev, "Invalid offset (0x%0x)\n", otg_dev->os_dep.reg_offset);
+-00506                 return sprintf(buf, "invalid offset\n");
+-00507         }
+-00508 }
+-00509 
+-00515 static ssize_t regvalue_store(struct device *_dev,
+-00516                               struct device_attribute *attr,
+-00517                               const char *buf, size_t count)
+-00518 {
+-00519 #ifdef LM_INTERFACE
+-00520         struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
+-00521         dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
+-00522 #elif defined(PCI_INTERFACE)
+-00523         dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
+-00524 #endif
+-00525 
+-00526         volatile uint32_t *addr;
+-00527         uint32_t val = simple_strtoul(buf, NULL, 16);
+-00528         //dev_dbg(_dev, "Offset=0x%08x Val=0x%08x\n", otg_dev->reg_offset, val);
+-00529         if (otg_dev->os_dep.reg_offset != 0xFFFFFFFF && 0 != otg_dev->os_dep.base) {
+-00530                 /* Calculate the address */
+-00531                 addr = (uint32_t *) (otg_dev->os_dep.reg_offset +
+-00532                                      (uint8_t *) otg_dev->os_dep.base);
+-00533                 DWC_WRITE_REG32(addr, val);
+-00534         } else {
+-00535                 dev_err(_dev, "Invalid Register Offset (0x%08x)\n",
+-00536                         otg_dev->os_dep.reg_offset);
+-00537         }
+-00538         return count;
+-00539 }
+-00540 
+-00541 DEVICE_ATTR(regvalue, S_IRUGO | S_IWUSR, regvalue_show, regvalue_store);
+-00542 
+-00543 /*
+-00544  * Attributes
+-00545  */
+-00546 DWC_OTG_DEVICE_ATTR_BITFIELD_RO(mode, "Mode");
+-00547 DWC_OTG_DEVICE_ATTR_BITFIELD_RW(hnpcapable, "HNPCapable");
+-00548 DWC_OTG_DEVICE_ATTR_BITFIELD_RW(srpcapable, "SRPCapable");
+-00549 DWC_OTG_DEVICE_ATTR_BITFIELD_RW(hsic_connect, "HSIC Connect");
+-00550 DWC_OTG_DEVICE_ATTR_BITFIELD_RW(inv_sel_hsic, "Invert Select HSIC");
+-00551 
+-00552 //DWC_OTG_DEVICE_ATTR_BITFIELD_RW(buspower,&(otg_dev->core_if->core_global_regs->gotgctl),(1<<8),8,"Mode");
+-00553 //DWC_OTG_DEVICE_ATTR_BITFIELD_RW(bussuspend,&(otg_dev->core_if->core_global_regs->gotgctl),(1<<8),8,"Mode");
+-00554 DWC_OTG_DEVICE_ATTR_BITFIELD_RO(busconnected, "Bus Connected");
+-00555 
+-00556 DWC_OTG_DEVICE_ATTR_REG32_RW(gotgctl, 0, "GOTGCTL");
+-00557 DWC_OTG_DEVICE_ATTR_REG32_RW(gusbcfg,
+-00558                              &(otg_dev->core_if->core_global_regs->gusbcfg),
+-00559                              "GUSBCFG");
+-00560 DWC_OTG_DEVICE_ATTR_REG32_RW(grxfsiz,
+-00561                              &(otg_dev->core_if->core_global_regs->grxfsiz),
+-00562                              "GRXFSIZ");
+-00563 DWC_OTG_DEVICE_ATTR_REG32_RW(gnptxfsiz,
+-00564                              &(otg_dev->core_if->core_global_regs->gnptxfsiz),
+-00565                              "GNPTXFSIZ");
+-00566 DWC_OTG_DEVICE_ATTR_REG32_RW(gpvndctl,
+-00567                              &(otg_dev->core_if->core_global_regs->gpvndctl),
+-00568                              "GPVNDCTL");
+-00569 DWC_OTG_DEVICE_ATTR_REG32_RW(ggpio,
+-00570                              &(otg_dev->core_if->core_global_regs->ggpio),
+-00571                              "GGPIO");
+-00572 DWC_OTG_DEVICE_ATTR_REG32_RW(guid, &(otg_dev->core_if->core_global_regs->guid),
+-00573                              "GUID");
+-00574 DWC_OTG_DEVICE_ATTR_REG32_RO(gsnpsid,
+-00575                              &(otg_dev->core_if->core_global_regs->gsnpsid),
+-00576                              "GSNPSID");
+-00577 DWC_OTG_DEVICE_ATTR_BITFIELD_RW(devspeed, "Device Speed");
+-00578 DWC_OTG_DEVICE_ATTR_BITFIELD_RO(enumspeed, "Device Enumeration Speed");
+-00579 
+-00580 DWC_OTG_DEVICE_ATTR_REG32_RO(hptxfsiz,
+-00581                              &(otg_dev->core_if->core_global_regs->hptxfsiz),
+-00582                              "HPTXFSIZ");
+-00583 DWC_OTG_DEVICE_ATTR_REG32_RW(hprt0, otg_dev->core_if->host_if->hprt0, "HPRT0");
+-00584 
+-00591 static ssize_t hnp_show(struct device *_dev,
+-00592                         struct device_attribute *attr, char *buf)
+-00593 {
+-00594 #ifdef LM_INTERFACE
+-00595         struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
+-00596         dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
+-00597 #elif defined(PCI_INTERFACE)
+-00598         dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
+-00599 #endif
+-00600         return sprintf(buf, "HstNegScs = 0x%x\n",
+-00601                        dwc_otg_get_hnpstatus(otg_dev->core_if));
+-00602 }
+-00603 
+-00607 static ssize_t hnp_store(struct device *_dev,
+-00608                          struct device_attribute *attr,
+-00609                          const char *buf, size_t count)
+-00610 {
+-00611 #ifdef LM_INTERFACE
+-00612         struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
+-00613         dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
+-00614 #elif defined(PCI_INTERFACE)
+-00615         dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
+-00616 #endif
+-00617         uint32_t in = simple_strtoul(buf, NULL, 16);
+-00618         dwc_otg_set_hnpreq(otg_dev->core_if, in);
+-00619         return count;
+-00620 }
+-00621 
+-00622 DEVICE_ATTR(hnp, 0644, hnp_show, hnp_store);
+-00623 
+-00630 static ssize_t srp_show(struct device *_dev,
+-00631                         struct device_attribute *attr, char *buf)
+-00632 {
+-00633 #ifndef DWC_HOST_ONLY
+-00634 #ifdef LM_INTERFACE
+-00635         struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
+-00636         dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
+-00637 #elif defined(PCI_INTERFACE)
+-00638         dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
+-00639 #endif
+-00640         return sprintf(buf, "SesReqScs = 0x%x\n",
+-00641                        dwc_otg_get_srpstatus(otg_dev->core_if));
+-00642 #else
+-00643         return sprintf(buf, "Host Only Mode!\n");
+-00644 #endif
+-00645 }
+-00646 
+-00650 static ssize_t srp_store(struct device *_dev,
+-00651                          struct device_attribute *attr,
+-00652                          const char *buf, size_t count)
+-00653 {
+-00654 #ifndef DWC_HOST_ONLY
+-00655 #ifdef LM_INTERFACE
+-00656         struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
+-00657         dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
+-00658 #elif defined(PCI_INTERFACE)
+-00659         dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
+-00660 #endif
+-00661         dwc_otg_pcd_initiate_srp(otg_dev->pcd);
+-00662 #endif
+-00663         return count;
+-00664 }
+-00665 
+-00666 DEVICE_ATTR(srp, 0644, srp_show, srp_store);
+-00667 
+-00674 static ssize_t buspower_show(struct device *_dev,
+-00675                              struct device_attribute *attr, char *buf)
+-00676 {
+-00677 #ifdef LM_INTERFACE
+-00678         struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
+-00679         dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
+-00680 #elif defined(PCI_INTERFACE)
+-00681         dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
+-00682 #endif
+-00683         return sprintf(buf, "Bus Power = 0x%x\n",
+-00684                        dwc_otg_get_prtpower(otg_dev->core_if));
+-00685 }
+-00686 
+-00690 static ssize_t buspower_store(struct device *_dev,
+-00691                               struct device_attribute *attr,
+-00692                               const char *buf, size_t count)
+-00693 {
+-00694 #ifdef LM_INTERFACE
+-00695         struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
+-00696         dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
+-00697 #elif defined(PCI_INTERFACE)
+-00698         dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
+-00699 #endif
+-00700         uint32_t on = simple_strtoul(buf, NULL, 16);
+-00701         dwc_otg_set_prtpower(otg_dev->core_if, on);
+-00702         return count;
+-00703 }
+-00704 
+-00705 DEVICE_ATTR(buspower, 0644, buspower_show, buspower_store);
+-00706 
+-00713 static ssize_t bussuspend_show(struct device *_dev,
+-00714                                struct device_attribute *attr, char *buf)
+-00715 {
+-00716 #ifdef LM_INTERFACE
+-00717         struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
+-00718         dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
+-00719 #elif defined(PCI_INTERFACE)
+-00720         dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
+-00721 #endif
+-00722 
+-00723         return sprintf(buf, "Bus Suspend = 0x%x\n",
+-00724                        dwc_otg_get_prtsuspend(otg_dev->core_if));
+-00725 }
+-00726 
+-00730 static ssize_t bussuspend_store(struct device *_dev,
+-00731                                 struct device_attribute *attr,
+-00732                                 const char *buf, size_t count)
+-00733 {
+-00734 #ifdef LM_INTERFACE
+-00735         struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
+-00736         dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
+-00737 #elif defined(PCI_INTERFACE)
+-00738         dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
+-00739 #endif
+-00740 
+-00741         uint32_t in = simple_strtoul(buf, NULL, 16);
+-00742         dwc_otg_set_prtsuspend(otg_dev->core_if, in);
+-00743         return count;
+-00744 }
+-00745 
+-00746 DEVICE_ATTR(bussuspend, 0644, bussuspend_show, bussuspend_store);
+-00747 
+-00751 static ssize_t mode_ch_tim_en_show(struct device *_dev,
+-00752                                    struct device_attribute *attr, char *buf)
+-00753 {
+-00754 #ifdef LM_INTERFACE
+-00755         struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
+-00756         dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
+-00757 #elif defined(PCI_INTERFACE)
+-00758         dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
+-00759 #endif
+-00760 
+-00761         return sprintf(buf, "Mode Change Ready Timer Enable = 0x%x\n",
+-00762                        dwc_otg_get_mode_ch_tim(otg_dev->core_if));
+-00763 }
+-00764 
+-00768 static ssize_t mode_ch_tim_en_store(struct device *_dev,
+-00769                                     struct device_attribute *attr,
+-00770                                     const char *buf, size_t count)
+-00771 {
+-00772 #ifdef LM_INTERFACE
+-00773         struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
+-00774         dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
+-00775 #elif defined(PCI_INTERFACE)
+-00776         dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
+-00777 #endif
+-00778 
+-00779         uint32_t in = simple_strtoul(buf, NULL, 16);
+-00780         dwc_otg_set_mode_ch_tim(otg_dev->core_if, in);
+-00781         return count;
+-00782 }
+-00783 
+-00784 DEVICE_ATTR(mode_ch_tim_en, 0644, mode_ch_tim_en_show, mode_ch_tim_en_store);
+-00785 
+-00789 static ssize_t fr_interval_show(struct device *_dev,
+-00790                                 struct device_attribute *attr, char *buf)
+-00791 {
+-00792 #ifdef LM_INTERFACE
+-00793         struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
+-00794         dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
+-00795 #elif defined(PCI_INTERFACE)
+-00796         dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
+-00797 #endif
+-00798 
+-00799         return sprintf(buf, "Frame Interval = 0x%x\n",
+-00800                        dwc_otg_get_fr_interval(otg_dev->core_if));
+-00801 }
+-00802 
+-00806 static ssize_t fr_interval_store(struct device *_dev,
+-00807                                  struct device_attribute *attr,
+-00808                                  const char *buf, size_t count)
+-00809 {
+-00810 #ifdef LM_INTERFACE
+-00811         struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
+-00812         dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
+-00813 #elif defined(PCI_INTERFACE)
+-00814         dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
+-00815 #endif
+-00816 
+-00817         uint32_t in = simple_strtoul(buf, NULL, 10);
+-00818         dwc_otg_set_fr_interval(otg_dev->core_if, in);
+-00819         return count;
+-00820 }
+-00821 
+-00822 DEVICE_ATTR(fr_interval, 0644, fr_interval_show, fr_interval_store);
+-00823 
+-00827 static ssize_t remote_wakeup_show(struct device *_dev,
+-00828                                   struct device_attribute *attr, char *buf)
+-00829 {
+-00830 #ifndef DWC_HOST_ONLY
+-00831 #ifdef LM_INTERFACE
+-00832         struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
+-00833         dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
+-00834 #elif defined(PCI_INTERFACE)
+-00835         dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
+-00836 #endif
+-00837 
+-00838         return sprintf(buf,
+-00839                        "Remote Wakeup Sig = %d Enabled = %d LPM Remote Wakeup = %d\n",
+-00840                        dwc_otg_get_remotewakesig(otg_dev->core_if),
+-00841                        dwc_otg_pcd_get_rmwkup_enable(otg_dev->pcd),
+-00842                        dwc_otg_get_lpm_remotewakeenabled(otg_dev->core_if));
+-00843 #else
+-00844         return sprintf(buf, "Host Only Mode!\n");
+-00845 #endif /* DWC_HOST_ONLY */
+-00846 }
+-00847 
+-00854 static ssize_t remote_wakeup_store(struct device *_dev,
+-00855                                    struct device_attribute *attr,
+-00856                                    const char *buf, size_t count)
+-00857 {
+-00858 #ifndef DWC_HOST_ONLY
+-00859 #ifdef LM_INTERFACE
+-00860         struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
+-00861         dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
+-00862 #elif defined(PCI_INTERFACE)
+-00863         dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
+-00864 #endif
+-00865 
+-00866         uint32_t val = simple_strtoul(buf, NULL, 16);
+-00867 
+-00868         if (val & 1) {
+-00869                 dwc_otg_pcd_remote_wakeup(otg_dev->pcd, 1);
+-00870         } else {
+-00871                 dwc_otg_pcd_remote_wakeup(otg_dev->pcd, 0);
+-00872         }
+-00873 #endif /* DWC_HOST_ONLY */
+-00874         return count;
+-00875 }
+-00876 
+-00877 DEVICE_ATTR(remote_wakeup, S_IRUGO | S_IWUSR, remote_wakeup_show,
+-00878             remote_wakeup_store);
+-00879 
+-00883 static ssize_t rem_wakeup_pwrdn_show(struct device *_dev,
+-00884                                      struct device_attribute *attr, char *buf)
+-00885 {
+-00886 #ifndef DWC_HOST_ONLY
+-00887 #ifdef LM_INTERFACE
+-00888         struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
+-00889         dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
+-00890 #elif defined(PCI_INTERFACE)
+-00891         dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
+-00892 #endif
+-00893         if (dwc_otg_get_core_state(otg_dev->core_if)) {
+-00894                 DWC_PRINTF("Core is in hibernation\n");
+-00895         } else {
+-00896                 DWC_PRINTF("Core is not in hibernation\n");
+-00897         }
+-00898 #endif /* DWC_HOST_ONLY */
+-00899         return 0;
+-00900 }
+-00901 
+-00902 extern int dwc_otg_device_hibernation_restore(dwc_otg_core_if_t * core_if,
+-00903                                               int rem_wakeup, int reset);
+-00904 
+-00908 static ssize_t rem_wakeup_pwrdn_store(struct device *_dev,
+-00909                                       struct device_attribute *attr,
+-00910                                       const char *buf, size_t count)
+-00911 {
+-00912 #ifndef DWC_HOST_ONLY
+-00913 #ifdef LM_INTERFACE
+-00914         struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
+-00915         dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
+-00916 #elif defined(PCI_INTERFACE)
+-00917         dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
+-00918 #endif
+-00919         dwc_otg_device_hibernation_restore(otg_dev->core_if, 1, 0);
+-00920 #endif
+-00921         return count;
+-00922 }
+-00923 
+-00924 DEVICE_ATTR(rem_wakeup_pwrdn, S_IRUGO | S_IWUSR, rem_wakeup_pwrdn_show,
+-00925             rem_wakeup_pwrdn_store);
+-00926 
+-00927 static ssize_t disconnect_us(struct device *_dev,
+-00928                              struct device_attribute *attr,
+-00929                              const char *buf, size_t count)
+-00930 {
+-00931 
+-00932 #ifndef DWC_HOST_ONLY
+-00933 #ifdef LM_INTERFACE
+-00934         struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
+-00935         dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
+-00936 #elif defined(PCI_INTERFACE)
+-00937         dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
+-00938 #endif
+-00939         uint32_t val = simple_strtoul(buf, NULL, 16);
+-00940         DWC_PRINTF("The Passed value is %04x\n", val);
+-00941 
+-00942         dwc_otg_pcd_disconnect_us(otg_dev->pcd, 50);
+-00943 
+-00944 #endif /* DWC_HOST_ONLY */
+-00945         return count;
+-00946 }
+-00947 
+-00948 DEVICE_ATTR(disconnect_us, S_IWUSR, 0, disconnect_us);
+-00949 
+-00954 static ssize_t regdump_show(struct device *_dev,
+-00955                             struct device_attribute *attr, char *buf)
+-00956 {
+-00957 #ifdef LM_INTERFACE
+-00958         struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
+-00959         dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
+-00960 #elif defined(PCI_INTERFACE)
+-00961         dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
+-00962 #endif
+-00963 
+-00964         dwc_otg_dump_global_registers(otg_dev->core_if);
+-00965         if (dwc_otg_is_host_mode(otg_dev->core_if)) {
+-00966                 dwc_otg_dump_host_registers(otg_dev->core_if);
+-00967         } else {
+-00968                 dwc_otg_dump_dev_registers(otg_dev->core_if);
+-00969 
+-00970         }
+-00971         return sprintf(buf, "Register Dump\n");
+-00972 }
+-00973 
+-00974 DEVICE_ATTR(regdump, S_IRUGO | S_IWUSR, regdump_show, 0);
+-00975 
+-00980 static ssize_t spramdump_show(struct device *_dev,
+-00981                               struct device_attribute *attr, char *buf)
+-00982 {
+-00983 #ifdef LM_INTERFACE
+-00984         struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
+-00985         dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
+-00986 #elif defined(PCI_INTERFACE)
+-00987         dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
+-00988 #endif
+-00989 
+-00990         dwc_otg_dump_spram(otg_dev->core_if);
+-00991 
+-00992         return sprintf(buf, "SPRAM Dump\n");
+-00993 }
+-00994 
+-00995 DEVICE_ATTR(spramdump, S_IRUGO | S_IWUSR, spramdump_show, 0);
+-00996 
+-01000 static ssize_t hcddump_show(struct device *_dev,
+-01001                             struct device_attribute *attr, char *buf)
+-01002 {
+-01003 #ifndef DWC_DEVICE_ONLY
+-01004 #ifdef LM_INTERFACE
+-01005         struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
+-01006         dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
+-01007 #elif defined(PCI_INTERFACE)
+-01008         dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
+-01009 #endif
+-01010 
+-01011         dwc_otg_hcd_dump_state(otg_dev->hcd);
+-01012 #endif /* DWC_DEVICE_ONLY */
+-01013         return sprintf(buf, "HCD Dump\n");
+-01014 }
+-01015 
+-01016 DEVICE_ATTR(hcddump, S_IRUGO | S_IWUSR, hcddump_show, 0);
+-01017 
+-01023 static ssize_t hcd_frrem_show(struct device *_dev,
+-01024                               struct device_attribute *attr, char *buf)
+-01025 {
+-01026 #ifndef DWC_DEVICE_ONLY
+-01027 #ifdef LM_INTERFACE
+-01028         struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
+-01029         dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
+-01030 #elif defined(PCI_INTERFACE)
+-01031         dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
+-01032 #endif
+-01033 
+-01034         dwc_otg_hcd_dump_frrem(otg_dev->hcd);
+-01035 #endif /* DWC_DEVICE_ONLY */
+-01036         return sprintf(buf, "HCD Dump Frame Remaining\n");
+-01037 }
+-01038 
+-01039 DEVICE_ATTR(hcd_frrem, S_IRUGO | S_IWUSR, hcd_frrem_show, 0);
+-01040 
+-01045 #define RW_REG_COUNT 10000000
+-01046 #define MSEC_PER_JIFFIE 1000/HZ
+-01047 static ssize_t rd_reg_test_show(struct device *_dev,
+-01048                                 struct device_attribute *attr, char *buf)
+-01049 {
+-01050 #ifdef LM_INTERFACE
+-01051         struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
+-01052         dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
+-01053 #elif defined(PCI_INTERFACE)
+-01054         dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
+-01055 #endif
+-01056 
+-01057         int i;
+-01058         int time;
+-01059         int start_jiffies;
+-01060 
+-01061         printk("HZ %d, MSEC_PER_JIFFIE %d, loops_per_jiffy %lu\n",
+-01062                HZ, MSEC_PER_JIFFIE, loops_per_jiffy);
+-01063         start_jiffies = jiffies;
+-01064         for (i = 0; i < RW_REG_COUNT; i++) {
+-01065                 dwc_otg_get_gnptxfsiz(otg_dev->core_if);
+-01066         }
+-01067         time = jiffies - start_jiffies;
+-01068         return sprintf(buf,
+-01069                        "Time to read GNPTXFSIZ reg %d times: %d msecs (%d jiffies)\n",
+-01070                        RW_REG_COUNT, time * MSEC_PER_JIFFIE, time);
+-01071 }
+-01072 
+-01073 DEVICE_ATTR(rd_reg_test, S_IRUGO | S_IWUSR, rd_reg_test_show, 0);
+-01074 
+-01079 static ssize_t wr_reg_test_show(struct device *_dev,
+-01080                                 struct device_attribute *attr, char *buf)
+-01081 {
+-01082 #ifdef LM_INTERFACE
+-01083         struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
+-01084         dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
+-01085 #elif defined(PCI_INTERFACE)
+-01086         dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
+-01087 #endif
+-01088 
+-01089         uint32_t reg_val;
+-01090         int i;
+-01091         int time;
+-01092         int start_jiffies;
+-01093 
+-01094         printk("HZ %d, MSEC_PER_JIFFIE %d, loops_per_jiffy %lu\n",
+-01095                HZ, MSEC_PER_JIFFIE, loops_per_jiffy);
+-01096         reg_val = dwc_otg_get_gnptxfsiz(otg_dev->core_if);
+-01097         start_jiffies = jiffies;
+-01098         for (i = 0; i < RW_REG_COUNT; i++) {
+-01099                 dwc_otg_set_gnptxfsiz(otg_dev->core_if, reg_val);
+-01100         }
+-01101         time = jiffies - start_jiffies;
+-01102         return sprintf(buf,
+-01103                        "Time to write GNPTXFSIZ reg %d times: %d msecs (%d jiffies)\n",
+-01104                        RW_REG_COUNT, time * MSEC_PER_JIFFIE, time);
+-01105 }
+-01106 
+-01107 DEVICE_ATTR(wr_reg_test, S_IRUGO | S_IWUSR, wr_reg_test_show, 0);
+-01108 
+-01109 #ifdef CONFIG_USB_DWC_OTG_LPM
+-01110 
+-01114 static ssize_t lpmresp_show(struct device *_dev,
+-01115                             struct device_attribute *attr, char *buf)
+-01116 {
+-01117 #ifdef LM_INTERFACE
+-01118         struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
+-01119         dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
+-01120 #elif defined(PCI_INTERFACE)
+-01121         dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
+-01122 #endif
+-01123 
+-01124         if (!dwc_otg_get_param_lpm_enable(otg_dev->core_if))
+-01125                 return sprintf(buf, "** LPM is DISABLED **\n");
+-01126 
+-01127         if (!dwc_otg_is_device_mode(otg_dev->core_if)) {
+-01128                 return sprintf(buf, "** Current mode is not device mode\n");
+-01129         }
+-01130         return sprintf(buf, "lpm_response = %d\n",
+-01131                        dwc_otg_get_lpmresponse(otg_dev->core_if));
+-01132 }
+-01133 
+-01137 static ssize_t lpmresp_store(struct device *_dev,
+-01138                              struct device_attribute *attr,
+-01139                              const char *buf, size_t count)
+-01140 {
+-01141 #ifdef LM_INTERFACE
+-01142         struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
+-01143         dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
+-01144 #elif defined(PCI_INTERFACE)
+-01145         dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
+-01146 #endif
+-01147 
+-01148         uint32_t val = simple_strtoul(buf, NULL, 16);
+-01149 
+-01150         if (!dwc_otg_get_param_lpm_enable(otg_dev->core_if)) {
+-01151                 return 0;
+-01152         }
+-01153 
+-01154         if (!dwc_otg_is_device_mode(otg_dev->core_if)) {
+-01155                 return 0;
+-01156         }
+-01157 
+-01158         dwc_otg_set_lpmresponse(otg_dev->core_if, val);
+-01159         return count;
+-01160 }
+-01161 
+-01162 DEVICE_ATTR(lpm_response, S_IRUGO | S_IWUSR, lpmresp_show, lpmresp_store);
+-01163 
+-01167 static ssize_t sleepstatus_show(struct device *_dev,
+-01168                                 struct device_attribute *attr, char *buf)
+-01169 {
+-01170 #ifdef LM_INTERFACE
+-01171         struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
+-01172         dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
+-01173 #elif defined(PCI_INTERFACE)
+-01174         dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
+-01175 #endif
+-01176 
+-01177         return sprintf(buf, "Sleep Status = %d\n",
+-01178                        dwc_otg_get_lpm_portsleepstatus(otg_dev->core_if));
+-01179 }
+-01180 
+-01184 static ssize_t sleepstatus_store(struct device *_dev,
+-01185                                  struct device_attribute *attr,
+-01186                                  const char *buf, size_t count)
+-01187 {
+-01188 #ifdef LM_INTERFACE
+-01189         struct lm_device *lm_dev = container_of(_dev, struct lm_device, dev);
+-01190         dwc_otg_device_t *otg_dev = lm_get_drvdata(lm_dev);
+-01191 #elif defined(PCI_INTERFACE)
+-01192         dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);
+-01193 #endif
+-01194 
+-01195         dwc_otg_core_if_t *core_if = otg_dev->core_if;
+-01196 
+-01197         if (dwc_otg_get_lpm_portsleepstatus(otg_dev->core_if)) {
+-01198                 if (dwc_otg_is_host_mode(core_if)) {
+-01199 
+-01200                         DWC_PRINTF("Host initiated resume\n");
+-01201                         dwc_otg_set_prtresume(otg_dev->core_if, 1);
+-01202                 }
+-01203         }
+-01204 
+-01205         return count;
+-01206 }
+-01207 
+-01208 DEVICE_ATTR(sleep_status, S_IRUGO | S_IWUSR, sleepstatus_show,
+-01209             sleepstatus_store);
+-01210 
+-01211 #endif /* CONFIG_USB_DWC_OTG_LPM_ENABLE */
+-01212 
+-01218 void dwc_otg_attr_create(
+-01219 #ifdef LM_INTERFACE
+-01220                                 struct lm_device *dev
+-01221 #elif  defined(PCI_INTERFACE)
+-01222                                 struct pci_dev *dev
+-01223 #endif
+-01224     )
+-01225 {
+-01226         int error;
+-01227 
+-01228         error = device_create_file(&dev->dev, &dev_attr_regoffset);
+-01229         error = device_create_file(&dev->dev, &dev_attr_regvalue);
+-01230         error = device_create_file(&dev->dev, &dev_attr_mode);
+-01231         error = device_create_file(&dev->dev, &dev_attr_hnpcapable);
+-01232         error = device_create_file(&dev->dev, &dev_attr_srpcapable);
+-01233         error = device_create_file(&dev->dev, &dev_attr_hsic_connect);
+-01234         error = device_create_file(&dev->dev, &dev_attr_inv_sel_hsic);
+-01235         error = device_create_file(&dev->dev, &dev_attr_hnp);
+-01236         error = device_create_file(&dev->dev, &dev_attr_srp);
+-01237         error = device_create_file(&dev->dev, &dev_attr_buspower);
+-01238         error = device_create_file(&dev->dev, &dev_attr_bussuspend);
+-01239         error = device_create_file(&dev->dev, &dev_attr_mode_ch_tim_en);
+-01240         error = device_create_file(&dev->dev, &dev_attr_fr_interval);
+-01241         error = device_create_file(&dev->dev, &dev_attr_busconnected);
+-01242         error = device_create_file(&dev->dev, &dev_attr_gotgctl);
+-01243         error = device_create_file(&dev->dev, &dev_attr_gusbcfg);
+-01244         error = device_create_file(&dev->dev, &dev_attr_grxfsiz);
+-01245         error = device_create_file(&dev->dev, &dev_attr_gnptxfsiz);
+-01246         error = device_create_file(&dev->dev, &dev_attr_gpvndctl);
+-01247         error = device_create_file(&dev->dev, &dev_attr_ggpio);
+-01248         error = device_create_file(&dev->dev, &dev_attr_guid);
+-01249         error = device_create_file(&dev->dev, &dev_attr_gsnpsid);
+-01250         error = device_create_file(&dev->dev, &dev_attr_devspeed);
+-01251         error = device_create_file(&dev->dev, &dev_attr_enumspeed);
+-01252         error = device_create_file(&dev->dev, &dev_attr_hptxfsiz);
+-01253         error = device_create_file(&dev->dev, &dev_attr_hprt0);
+-01254         error = device_create_file(&dev->dev, &dev_attr_remote_wakeup);
+-01255         error = device_create_file(&dev->dev, &dev_attr_rem_wakeup_pwrdn);
+-01256         error = device_create_file(&dev->dev, &dev_attr_disconnect_us);
+-01257         error = device_create_file(&dev->dev, &dev_attr_regdump);
+-01258         error = device_create_file(&dev->dev, &dev_attr_spramdump);
+-01259         error = device_create_file(&dev->dev, &dev_attr_hcddump);
+-01260         error = device_create_file(&dev->dev, &dev_attr_hcd_frrem);
+-01261         error = device_create_file(&dev->dev, &dev_attr_rd_reg_test);
+-01262         error = device_create_file(&dev->dev, &dev_attr_wr_reg_test);
+-01263 #ifdef CONFIG_USB_DWC_OTG_LPM
+-01264         error = device_create_file(&dev->dev, &dev_attr_lpm_response);
+-01265         error = device_create_file(&dev->dev, &dev_attr_sleep_status);
+-01266 #endif
+-01267 }
+-01268 
+-01272 void dwc_otg_attr_remove(
+-01273 #ifdef LM_INTERFACE
+-01274                                 struct lm_device *dev
+-01275 #elif  defined(PCI_INTERFACE)
+-01276                                 struct pci_dev *dev
+-01277 #endif
+-01278     )
+-01279 {
+-01280         device_remove_file(&dev->dev, &dev_attr_regoffset);
+-01281         device_remove_file(&dev->dev, &dev_attr_regvalue);
+-01282         device_remove_file(&dev->dev, &dev_attr_mode);
+-01283         device_remove_file(&dev->dev, &dev_attr_hnpcapable);
+-01284         device_remove_file(&dev->dev, &dev_attr_srpcapable);
+-01285         device_remove_file(&dev->dev, &dev_attr_hsic_connect);
+-01286         device_remove_file(&dev->dev, &dev_attr_inv_sel_hsic);
+-01287         device_remove_file(&dev->dev, &dev_attr_hnp);
+-01288         device_remove_file(&dev->dev, &dev_attr_srp);
+-01289         device_remove_file(&dev->dev, &dev_attr_buspower);
+-01290         device_remove_file(&dev->dev, &dev_attr_bussuspend);
+-01291         device_remove_file(&dev->dev, &dev_attr_mode_ch_tim_en);
+-01292         device_remove_file(&dev->dev, &dev_attr_fr_interval);
+-01293         device_remove_file(&dev->dev, &dev_attr_busconnected);
+-01294         device_remove_file(&dev->dev, &dev_attr_gotgctl);
+-01295         device_remove_file(&dev->dev, &dev_attr_gusbcfg);
+-01296         device_remove_file(&dev->dev, &dev_attr_grxfsiz);
+-01297         device_remove_file(&dev->dev, &dev_attr_gnptxfsiz);
+-01298         device_remove_file(&dev->dev, &dev_attr_gpvndctl);
+-01299         device_remove_file(&dev->dev, &dev_attr_ggpio);
+-01300         device_remove_file(&dev->dev, &dev_attr_guid);
+-01301         device_remove_file(&dev->dev, &dev_attr_gsnpsid);
+-01302         device_remove_file(&dev->dev, &dev_attr_devspeed);
+-01303         device_remove_file(&dev->dev, &dev_attr_enumspeed);
+-01304         device_remove_file(&dev->dev, &dev_attr_hptxfsiz);
+-01305         device_remove_file(&dev->dev, &dev_attr_hprt0);
+-01306         device_remove_file(&dev->dev, &dev_attr_remote_wakeup);
+-01307         device_remove_file(&dev->dev, &dev_attr_rem_wakeup_pwrdn);
+-01308         device_remove_file(&dev->dev, &dev_attr_disconnect_us);
+-01309         device_remove_file(&dev->dev, &dev_attr_regdump);
+-01310         device_remove_file(&dev->dev, &dev_attr_spramdump);
+-01311         device_remove_file(&dev->dev, &dev_attr_hcddump);
+-01312         device_remove_file(&dev->dev, &dev_attr_hcd_frrem);
+-01313         device_remove_file(&dev->dev, &dev_attr_rd_reg_test);
+-01314         device_remove_file(&dev->dev, &dev_attr_wr_reg_test);
+-01315 #ifdef CONFIG_USB_DWC_OTG_LPM
+-01316         device_remove_file(&dev->dev, &dev_attr_lpm_response);
+-01317         device_remove_file(&dev->dev, &dev_attr_sleep_status);
+-01318 #endif
+-01319 }
+-
                                                                                Generated on Thu Oct 27 03:56:37 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__attr_8c.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/dwc__otg__attr_8c.html 2013-07-26 19:34:39.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,591 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_attr.c File Reference +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                dwc_otg_attr.c File Reference

                                                                                The diagnostic interface will provide access to the controller for bringing up the hardware and testing. More... +-

                                                                                +-#include "dwc_otg_os_dep.h"
                                                                                +-#include "dwc_os.h"
                                                                                +-#include "dwc_otg_driver.h"
                                                                                +-#include "dwc_otg_attr.h"
                                                                                +-#include "dwc_otg_core_if.h"
                                                                                +-#include "dwc_otg_pcd_if.h"
                                                                                +-#include "dwc_otg_hcd_if.h"
                                                                                +- +-

                                                                                +-Go to the source code of this file. +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-

                                                                                Functions for Show/Store of Attributes

                                                                                +-#define RW_REG_COUNT   10000000
                                                                                 Displays the time required to read the GNPTXFSIZ register many times (the output shows the number of times the register is read).
                                                                                +-#define MSEC_PER_JIFFIE   1000/HZ
                                                                                +-ssize_t regoffset_show (struct device *_dev, struct device_attribute *attr, char *buf)
                                                                                 Show the register offset of the Register Access.
                                                                                +-ssize_t regoffset_store (struct device *_dev, struct device_attribute *attr, const char *buf, size_t count)
                                                                                 Set the register offset for the next Register Access Read/Write.
                                                                                +-ssize_t regvalue_show (struct device *_dev, struct device_attribute *attr, char *buf)
                                                                                 Show the value of the register at the offset in the reg_offset attribute.
                                                                                +-ssize_t regvalue_store (struct device *_dev, struct device_attribute *attr, const char *buf, size_t count)
                                                                                 Store the value in the register at the offset in the reg_offset attribute.
                                                                                +- DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW (mode,"Mode")
                                                                                +-ssize_t hnp_store (struct device *_dev, struct device_attribute *attr, const char *buf, size_t count)
                                                                                 Set the HNP Request bit.
                                                                                +-ssize_t srp_show (struct device *_dev, struct device_attribute *attr, char *buf)
                                                                                 Show the SRP status bit.
                                                                                +-ssize_t srp_store (struct device *_dev, struct device_attribute *attr, const char *buf, size_t count)
                                                                                 Set the SRP Request bit.
                                                                                +-ssize_t buspower_show (struct device *_dev, struct device_attribute *attr, char *buf)
                                                                                 Show the Bus Power status.
                                                                                +-ssize_t buspower_store (struct device *_dev, struct device_attribute *attr, const char *buf, size_t count)
                                                                                 Set the Bus Power status.
                                                                                +-ssize_t bussuspend_show (struct device *_dev, struct device_attribute *attr, char *buf)
                                                                                 Show the Bus Suspend status.
                                                                                +-ssize_t bussuspend_store (struct device *_dev, struct device_attribute *attr, const char *buf, size_t count)
                                                                                 Set the Bus Suspend status.
                                                                                +-ssize_t mode_ch_tim_en_show (struct device *_dev, struct device_attribute *attr, char *buf)
                                                                                 Show the Mode Change Ready Timer status.
                                                                                +-ssize_t mode_ch_tim_en_store (struct device *_dev, struct device_attribute *attr, const char *buf, size_t count)
                                                                                 Set the Mode Change Ready Timer status.
                                                                                +-ssize_t fr_interval_show (struct device *_dev, struct device_attribute *attr, char *buf)
                                                                                 Show the value of HFIR Frame Interval bitfield.
                                                                                +-ssize_t fr_interval_store (struct device *_dev, struct device_attribute *attr, const char *buf, size_t count)
                                                                                 Set the HFIR Frame Interval value.
                                                                                +-ssize_t remote_wakeup_show (struct device *_dev, struct device_attribute *attr, char *buf)
                                                                                 Show the status of Remote Wakeup.
                                                                                ssize_t remote_wakeup_store (struct device *_dev, struct device_attribute *attr, const char *buf, size_t count)
                                                                                 Initiate a remote wakeup of the host.
                                                                                ssize_t rem_wakeup_pwrdn_show (struct device *_dev, struct device_attribute *attr, char *buf)
                                                                                 Show the whether core is hibernated or not.
                                                                                +-int dwc_otg_device_hibernation_restore (dwc_otg_core_if_t *core_if, int rem_wakeup, int reset)
                                                                                +-ssize_t rem_wakeup_pwrdn_store (struct device *_dev, struct device_attribute *attr, const char *buf, size_t count)
                                                                                 Initiate a remote wakeup of the device to exit from hibernation.
                                                                                +-ssize_t disconnect_us (struct device *_dev, struct device_attribute *attr, const char *buf, size_t count)
                                                                                +-ssize_t regdump_show (struct device *_dev, struct device_attribute *attr, char *buf)
                                                                                 Dump global registers and either host or device registers (depending on the current mode of the core).
                                                                                +-ssize_t spramdump_show (struct device *_dev, struct device_attribute *attr, char *buf)
                                                                                 Dump global registers and either host or device registers (depending on the current mode of the core).
                                                                                +-ssize_t hcddump_show (struct device *_dev, struct device_attribute *attr, char *buf)
                                                                                 Dump the current hcd state.
                                                                                ssize_t hcd_frrem_show (struct device *_dev, struct device_attribute *attr, char *buf)
                                                                                 Dump the average frame remaining at SOF.
                                                                                +-ssize_t rd_reg_test_show (struct device *_dev, struct device_attribute *attr, char *buf)
                                                                                +-ssize_t wr_reg_test_show (struct device *_dev, struct device_attribute *attr, char *buf)
                                                                                 Displays the time required to write the GNPTXFSIZ register many times (the output shows the number of times the register is written).
                                                                                +- regoffset
                                                                                +-S_IRUGO S_IWUSR
                                                                                +-S_IRUGO regoffset_show
                                                                                +-S_IRUGO regoffset_store
                                                                                +- regvalue
                                                                                +-S_IRUGO regvalue_show
                                                                                +-S_IRUGO regvalue_store
                                                                                +- hnp
                                                                                +- hnp_show
                                                                                +- hnp_store
                                                                                +- srp
                                                                                +- srp_show
                                                                                +- srp_store
                                                                                +- buspower
                                                                                +- buspower_show
                                                                                +- buspower_store
                                                                                +- bussuspend
                                                                                +- bussuspend_show
                                                                                +- bussuspend_store
                                                                                +- mode_ch_tim_en
                                                                                +- mode_ch_tim_en_show
                                                                                +- mode_ch_tim_en_store
                                                                                +- fr_interval
                                                                                +- fr_interval_show
                                                                                +- fr_interval_store
                                                                                +- remote_wakeup
                                                                                +-S_IRUGO remote_wakeup_show
                                                                                +-S_IRUGO remote_wakeup_store
                                                                                +- rem_wakeup_pwrdn
                                                                                +-S_IRUGO rem_wakeup_pwrdn_show
                                                                                +-S_IRUGO rem_wakeup_pwrdn_store
                                                                                +- disconnect_us
                                                                                +- regdump
                                                                                +-S_IRUGO regdump_show
                                                                                +- spramdump
                                                                                +-S_IRUGO spramdump_show
                                                                                +- hcddump
                                                                                +-S_IRUGO hcddump_show
                                                                                +- hcd_frrem
                                                                                +-S_IRUGO hcd_frrem_show
                                                                                +- rd_reg_test
                                                                                +-S_IRUGO rd_reg_test_show
                                                                                +- wr_reg_test
                                                                                +-S_IRUGO wr_reg_test_show

                                                                                Defines

                                                                                #define DWC_OTG_DEVICE_ATTR_BITFIELD_RW(_otg_attr_name_, _string_)
                                                                                #define DWC_OTG_DEVICE_ATTR_BITFIELD_RO(_otg_attr_name_, _string_)
                                                                                #define DWC_OTG_DEVICE_ATTR_REG32_RW(_otg_attr_name_, _addr_, _string_)
                                                                                #define DWC_OTG_DEVICE_ATTR_REG32_RO(_otg_attr_name_, _addr_, _string_)

                                                                                Functions

                                                                                +-void dwc_otg_attr_create ()
                                                                                 Create the device files.
                                                                                +-void dwc_otg_attr_remove ()
                                                                                 Remove the device files.
                                                                                +-

                                                                                Detailed Description

                                                                                +-The diagnostic interface will provide access to the controller for bringing up the hardware and testing. +-

                                                                                +-The Linux driver attributes feature will be used to provide the Linux Diagnostic Interface. These attributes are accessed through sysfs. +-

                                                                                +-Definition in file dwc_otg_attr.c.

                                                                                Define Documentation

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                #define DWC_OTG_DEVICE_ATTR_BITFIELD_RW ( _otg_attr_name_,
                                                                                _string_   ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Value:

                                                                                DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_string_) \
+-DWC_OTG_DEVICE_ATTR_BITFIELD_STORE(_otg_attr_name_,_string_) \
+-DEVICE_ATTR(_otg_attr_name_,0644,_otg_attr_name_##_show,_otg_attr_name_##_store);
+-
                                                                                +-

                                                                                +-Definition at line 410 of file dwc_otg_attr.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                #define DWC_OTG_DEVICE_ATTR_BITFIELD_RO ( _otg_attr_name_,
                                                                                _string_   ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Value:

                                                                                DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_string_) \
+-DEVICE_ATTR(_otg_attr_name_,0444,_otg_attr_name_##_show,NULL);
+-
                                                                                +-

                                                                                +-Definition at line 415 of file dwc_otg_attr.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                #define DWC_OTG_DEVICE_ATTR_REG32_RW ( _otg_attr_name_,
                                                                                _addr_,
                                                                                _string_   ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Value:

                                                                                DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_string_) \
+-DWC_OTG_DEVICE_ATTR_REG_STORE(_otg_attr_name_,_string_) \
+-DEVICE_ATTR(_otg_attr_name_,0644,_otg_attr_name_##_show,_otg_attr_name_##_store);
+-
                                                                                +-

                                                                                +-Definition at line 419 of file dwc_otg_attr.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                #define DWC_OTG_DEVICE_ATTR_REG32_RO ( _otg_attr_name_,
                                                                                _addr_,
                                                                                _string_   ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Value:

                                                                                DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_string_) \
+-DEVICE_ATTR(_otg_attr_name_,0444,_otg_attr_name_##_show,NULL);
+-
                                                                                +-

                                                                                +-Definition at line 424 of file dwc_otg_attr.c.

                                                                                +-

                                                                                Function Documentation

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                ssize_t remote_wakeup_store ( struct device *  _dev,
                                                                                struct device_attribute *  attr,
                                                                                const char *  buf,
                                                                                size_t  count
                                                                                )  [static]
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Initiate a remote wakeup of the host. +-

                                                                                +-The Device control register Remote Wakeup Signal bit is written if the PCD Remote wakeup enable flag is set. +-

                                                                                +-Definition at line 854 of file dwc_otg_attr.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                ssize_t rem_wakeup_pwrdn_show ( struct device *  _dev,
                                                                                struct device_attribute *  attr,
                                                                                char *  buf
                                                                                )  [static]
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Show the whether core is hibernated or not. +-

                                                                                +- +-

                                                                                +-Definition at line 883 of file dwc_otg_attr.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                ssize_t hcd_frrem_show ( struct device *  _dev,
                                                                                struct device_attribute *  attr,
                                                                                char *  buf
                                                                                )  [static]
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Dump the average frame remaining at SOF. +-

                                                                                +-This can be used to determine average interrupt latency. Frame remaining is also shown for start transfer and two additional sample points. +-

                                                                                +-Definition at line 1023 of file dwc_otg_attr.c.

                                                                                +-

                                                                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__attr_8h-source.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/dwc__otg__attr_8h-source.html 2013-07-26 19:34:39.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,94 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_attr.h Source File +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                dwc_otg_attr.h

                                                                                Go to the documentation of this file.
                                                                                00001 /* ==========================================================================
+-00002  * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_attr.h $
+-00003  * $Revision: #13 $
+-00004  * $Date: 2010/06/21 $
+-00005  * $Change: 1532021 $
+-00006  *
+-00007  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
+-00008  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
+-00009  * otherwise expressly agreed to in writing between Synopsys and you.
+-00010  * 
+-00011  * The Software IS NOT an item of Licensed Software or Licensed Product under
+-00012  * any End User Software License Agreement or Agreement for Licensed Product
+-00013  * with Synopsys or any supplement thereto. You are permitted to use and
+-00014  * redistribute this Software in source and binary forms, with or without
+-00015  * modification, provided that redistributions of source code must retain this
+-00016  * notice. You may not view, use, disclose, copy or distribute this file or
+-00017  * any information contained herein except pursuant to this license grant from
+-00018  * Synopsys. If you do not agree with this notice, including the disclaimer
+-00019  * below, then you are not authorized to use the Software.
+-00020  * 
+-00021  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
+-00022  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+-00023  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+-00024  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
+-00025  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+-00026  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+-00027  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+-00028  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+-00029  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+-00030  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+-00031  * DAMAGE.
+-00032  * ========================================================================== */
+-00033 
+-00034 #if !defined(__DWC_OTG_ATTR_H__)
+-00035 #define __DWC_OTG_ATTR_H__
+-00036 
+-00040 extern struct device_attribute dev_attr_regoffset;
+-00041 extern struct device_attribute dev_attr_regvalue;
+-00042 
+-00043 extern struct device_attribute dev_attr_mode;
+-00044 extern struct device_attribute dev_attr_hnpcapable;
+-00045 extern struct device_attribute dev_attr_srpcapable;
+-00046 extern struct device_attribute dev_attr_hnp;
+-00047 extern struct device_attribute dev_attr_srp;
+-00048 extern struct device_attribute dev_attr_buspower;
+-00049 extern struct device_attribute dev_attr_bussuspend;
+-00050 extern struct device_attribute dev_attr_mode_ch_tim_en;
+-00051 extern struct device_attribute dev_attr_fr_interval;
+-00052 extern struct device_attribute dev_attr_busconnected;
+-00053 extern struct device_attribute dev_attr_gotgctl;
+-00054 extern struct device_attribute dev_attr_gusbcfg;
+-00055 extern struct device_attribute dev_attr_grxfsiz;
+-00056 extern struct device_attribute dev_attr_gnptxfsiz;
+-00057 extern struct device_attribute dev_attr_gpvndctl;
+-00058 extern struct device_attribute dev_attr_ggpio;
+-00059 extern struct device_attribute dev_attr_guid;
+-00060 extern struct device_attribute dev_attr_gsnpsid;
+-00061 extern struct device_attribute dev_attr_devspeed;
+-00062 extern struct device_attribute dev_attr_enumspeed;
+-00063 extern struct device_attribute dev_attr_hptxfsiz;
+-00064 extern struct device_attribute dev_attr_hprt0;
+-00065 #ifdef CONFIG_USB_DWC_OTG_LPM
+-00066 extern struct device_attribute dev_attr_lpm_response;
+-00067 extern struct device_attribute devi_attr_sleep_status;
+-00068 #endif
+-00069 
+-00070 void dwc_otg_attr_create(
+-00071 #ifdef LM_INTERFACE
+-00072                                 struct lm_device *dev
+-00073 #elif  PCI_INTERFACE
+-00074                                 struct pci_dev *dev
+-00075 #endif
+-00076     );
+-00077 
+-00078 void dwc_otg_attr_remove(
+-00079 #ifdef LM_INTERFACE
+-00080                                 struct lm_device *dev
+-00081 #elif  PCI_INTERFACE
+-00082                                 struct pci_dev *dev
+-00083 #endif
+-00084     );
+-00085 #endif
+-
                                                                                Generated on Thu Oct 27 03:56:37 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__attr_8h.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/dwc__otg__attr_8h.html 2013-07-26 19:34:39.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,106 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_attr.h File Reference +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                dwc_otg_attr.h File Reference

                                                                                This file contains the interface to the Linux device attributes. More... +-

                                                                                +- +-

                                                                                +-Go to the source code of this file. +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-

                                                                                Functions

                                                                                +-void dwc_otg_attr_create ()
                                                                                 Create the device files.
                                                                                +-void dwc_otg_attr_remove ()
                                                                                 Remove the device files.

                                                                                Variables

                                                                                +-device_attribute dev_attr_regoffset
                                                                                +-device_attribute dev_attr_regvalue
                                                                                +-device_attribute dev_attr_mode
                                                                                +-device_attribute dev_attr_hnpcapable
                                                                                +-device_attribute dev_attr_srpcapable
                                                                                +-device_attribute dev_attr_hnp
                                                                                +-device_attribute dev_attr_srp
                                                                                +-device_attribute dev_attr_buspower
                                                                                +-device_attribute dev_attr_bussuspend
                                                                                +-device_attribute dev_attr_mode_ch_tim_en
                                                                                +-device_attribute dev_attr_fr_interval
                                                                                +-device_attribute dev_attr_busconnected
                                                                                +-device_attribute dev_attr_gotgctl
                                                                                +-device_attribute dev_attr_gusbcfg
                                                                                +-device_attribute dev_attr_grxfsiz
                                                                                +-device_attribute dev_attr_gnptxfsiz
                                                                                +-device_attribute dev_attr_gpvndctl
                                                                                +-device_attribute dev_attr_ggpio
                                                                                +-device_attribute dev_attr_guid
                                                                                +-device_attribute dev_attr_gsnpsid
                                                                                +-device_attribute dev_attr_devspeed
                                                                                +-device_attribute dev_attr_enumspeed
                                                                                +-device_attribute dev_attr_hptxfsiz
                                                                                +-device_attribute dev_attr_hprt0
                                                                                +-

                                                                                Detailed Description

                                                                                +-This file contains the interface to the Linux device attributes. +-

                                                                                +- +-

                                                                                +-Definition in file dwc_otg_attr.h.

                                                                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__cfi_8c-source.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/dwc__otg__cfi_8c-source.html 2013-07-26 19:34:39.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,1711 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_cfi.c Source File +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                dwc_otg_cfi.c

                                                                                Go to the documentation of this file.
                                                                                00001 /* ==========================================================================
+-00002  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
+-00003  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
+-00004  * otherwise expressly agreed to in writing between Synopsys and you.
+-00005  * 
+-00006  * The Software IS NOT an item of Licensed Software or Licensed Product under
+-00007  * any End User Software License Agreement or Agreement for Licensed Product
+-00008  * with Synopsys or any supplement thereto. You are permitted to use and
+-00009  * redistribute this Software in source and binary forms, with or without
+-00010  * modification, provided that redistributions of source code must retain this
+-00011  * notice. You may not view, use, disclose, copy or distribute this file or
+-00012  * any information contained herein except pursuant to this license grant from
+-00013  * Synopsys. If you do not agree with this notice, including the disclaimer
+-00014  * below, then you are not authorized to use the Software.
+-00015  * 
+-00016  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
+-00017  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+-00018  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+-00019  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
+-00020  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+-00021  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+-00022  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+-00023  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+-00024  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+-00025  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+-00026  * DAMAGE.
+-00027  * ========================================================================== */
+-00028 
+-00035 #ifdef DWC_UTE_CFI
+-00036 
+-00037 #include "dwc_otg_pcd.h"
+-00038 #include "dwc_otg_cfi.h"
+-00039 
+-00041 #define DWC_CONSTANT_CPU_TO_LE16(x) (x)
+-00042 
+-00043 extern dwc_otg_pcd_ep_t *get_ep_by_addr(dwc_otg_pcd_t * pcd, u16 wIndex);
+-00044 
+-00045 static int cfi_core_features_buf(uint8_t * buf, uint16_t buflen);
+-00046 static int cfi_get_feature_value(uint8_t * buf, uint16_t buflen,
+-00047                                  struct dwc_otg_pcd *pcd,
+-00048                                  struct cfi_usb_ctrlrequest *ctrl_req);
+-00049 static int cfi_set_feature_value(struct dwc_otg_pcd *pcd);
+-00050 static int cfi_ep_get_sg_val(uint8_t * buf, struct dwc_otg_pcd *pcd,
+-00051                              struct cfi_usb_ctrlrequest *req);
+-00052 static int cfi_ep_get_concat_val(uint8_t * buf, struct dwc_otg_pcd *pcd,
+-00053                                  struct cfi_usb_ctrlrequest *req);
+-00054 static int cfi_ep_get_align_val(uint8_t * buf, struct dwc_otg_pcd *pcd,
+-00055                                 struct cfi_usb_ctrlrequest *req);
+-00056 static int cfi_preproc_reset(struct dwc_otg_pcd *pcd,
+-00057                              struct cfi_usb_ctrlrequest *req);
+-00058 static void cfi_free_ep_bs_dyn_data(cfi_ep_t * cfiep);
+-00059 
+-00060 static uint16_t get_dfifo_size(dwc_otg_core_if_t * core_if);
+-00061 static int32_t get_rxfifo_size(dwc_otg_core_if_t * core_if, uint16_t wValue);
+-00062 static int32_t get_txfifo_size(struct dwc_otg_pcd *pcd, uint16_t wValue);
+-00063 
+-00064 static uint8_t resize_fifos(dwc_otg_core_if_t * core_if);
+-00065 
+-00067 static cfi_all_features_header_t all_props_desc_header = {
+-00068         .wVersion = DWC_CONSTANT_CPU_TO_LE16(0x100),
+-00069         .wCoreID = DWC_CONSTANT_CPU_TO_LE16(CFI_CORE_ID_OTG),
+-00070         .wNumFeatures = DWC_CONSTANT_CPU_TO_LE16(9),
+-00071 };
+-00072 
+-00074 static cfi_feature_desc_header_t prop_descs[] = {
+-00075 
+-00076         /* FT_ID_DMA_MODE */
+-00077         {
+-00078          .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_DMA_MODE),
+-00079          .bmAttributes = CFI_FEATURE_ATTR_RW,
+-00080          .wDataLength = DWC_CONSTANT_CPU_TO_LE16(1),
+-00081          },
+-00082 
+-00083         /* FT_ID_DMA_BUFFER_SETUP */
+-00084         {
+-00085          .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_DMA_BUFFER_SETUP),
+-00086          .bmAttributes = CFI_FEATURE_ATTR_RW,
+-00087          .wDataLength = DWC_CONSTANT_CPU_TO_LE16(6),
+-00088          },
+-00089 
+-00090         /* FT_ID_DMA_BUFF_ALIGN */
+-00091         {
+-00092          .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_DMA_BUFF_ALIGN),
+-00093          .bmAttributes = CFI_FEATURE_ATTR_RW,
+-00094          .wDataLength = DWC_CONSTANT_CPU_TO_LE16(2),
+-00095          },
+-00096 
+-00097         /* FT_ID_DMA_CONCAT_SETUP */
+-00098         {
+-00099          .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_DMA_CONCAT_SETUP),
+-00100          .bmAttributes = CFI_FEATURE_ATTR_RW,
+-00101          //.wDataLength  = DWC_CONSTANT_CPU_TO_LE16(6),
+-00102          },
+-00103 
+-00104         /* FT_ID_DMA_CIRCULAR */
+-00105         {
+-00106          .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_DMA_CIRCULAR),
+-00107          .bmAttributes = CFI_FEATURE_ATTR_RW,
+-00108          .wDataLength = DWC_CONSTANT_CPU_TO_LE16(6),
+-00109          },
+-00110 
+-00111         /* FT_ID_THRESHOLD_SETUP */
+-00112         {
+-00113          .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_THRESHOLD_SETUP),
+-00114          .bmAttributes = CFI_FEATURE_ATTR_RW,
+-00115          .wDataLength = DWC_CONSTANT_CPU_TO_LE16(6),
+-00116          },
+-00117 
+-00118         /* FT_ID_DFIFO_DEPTH */
+-00119         {
+-00120          .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_DFIFO_DEPTH),
+-00121          .bmAttributes = CFI_FEATURE_ATTR_RO,
+-00122          .wDataLength = DWC_CONSTANT_CPU_TO_LE16(2),
+-00123          },
+-00124 
+-00125         /* FT_ID_TX_FIFO_DEPTH */
+-00126         {
+-00127          .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_TX_FIFO_DEPTH),
+-00128          .bmAttributes = CFI_FEATURE_ATTR_RW,
+-00129          .wDataLength = DWC_CONSTANT_CPU_TO_LE16(2),
+-00130          },
+-00131 
+-00132         /* FT_ID_RX_FIFO_DEPTH */
+-00133         {
+-00134          .wFeatureID = DWC_CONSTANT_CPU_TO_LE16(FT_ID_RX_FIFO_DEPTH),
+-00135          .bmAttributes = CFI_FEATURE_ATTR_RW,
+-00136          .wDataLength = DWC_CONSTANT_CPU_TO_LE16(2),
+-00137          }
+-00138 };
+-00139 
+-00141 cfi_string_t prop_name_table[] = {
+-00142         {FT_ID_DMA_MODE, "dma_mode"},
+-00143         {FT_ID_DMA_BUFFER_SETUP, "buffer_setup"},
+-00144         {FT_ID_DMA_BUFF_ALIGN, "buffer_align"},
+-00145         {FT_ID_DMA_CONCAT_SETUP, "concat_setup"},
+-00146         {FT_ID_DMA_CIRCULAR, "buffer_circular"},
+-00147         {FT_ID_THRESHOLD_SETUP, "threshold_setup"},
+-00148         {FT_ID_DFIFO_DEPTH, "dfifo_depth"},
+-00149         {FT_ID_TX_FIFO_DEPTH, "txfifo_depth"},
+-00150         {FT_ID_RX_FIFO_DEPTH, "rxfifo_depth"},
+-00151         {}
+-00152 };
+-00153 
+-00154 /************************************************************************/
+-00155 
+-00161 const uint8_t *get_prop_name(uint16_t prop_id, int *len)
+-00162 {
+-00163         cfi_string_t *pstr;
+-00164         *len = 0;
+-00165 
+-00166         for (pstr = prop_name_table; pstr && pstr->s; pstr++) {
+-00167                 if (pstr->id == prop_id) {
+-00168                         *len = DWC_STRLEN(pstr->s);
+-00169                         return pstr->s;
+-00170                 }
+-00171         }
+-00172         return NULL;
+-00173 }
+-00174 
+-00180 int cfi_setup(struct dwc_otg_pcd *pcd, struct cfi_usb_ctrlrequest *ctrl)
+-00181 {
+-00182         int retval = 0;
+-00183         dwc_otg_pcd_ep_t *ep = NULL;
+-00184         cfiobject_t *cfi = pcd->cfi;
+-00185         struct dwc_otg_core_if *coreif = GET_CORE_IF(pcd);
+-00186         uint16_t wLen = DWC_LE16_TO_CPU(&ctrl->wLength);
+-00187         uint16_t wValue = DWC_LE16_TO_CPU(&ctrl->wValue);
+-00188         uint16_t wIndex = DWC_LE16_TO_CPU(&ctrl->wIndex);
+-00189         uint32_t regaddr = 0;
+-00190         uint32_t regval = 0;
+-00191 
+-00192         /* Save this Control Request in the CFI object. 
+-00193          * The data field will be assigned in the data stage completion CB function.
+-00194          */
+-00195         cfi->ctrl_req = *ctrl;
+-00196         cfi->ctrl_req.data = NULL;
+-00197 
+-00198         cfi->need_gadget_att = 0;
+-00199         cfi->need_status_in_complete = 0;
+-00200 
+-00201         switch (ctrl->bRequest) {
+-00202         case VEN_CORE_GET_FEATURES:
+-00203                 retval = cfi_core_features_buf(cfi->buf_in.buf, CFI_IN_BUF_LEN);
+-00204                 if (retval >= 0) {
+-00205                         //dump_msg(cfi->buf_in.buf, retval);
+-00206                         ep = &pcd->ep0;
+-00207 
+-00208                         retval = min((uint16_t) retval, wLen);
+-00209                         /* Transfer this buffer to the host through the EP0-IN EP */
+-00210                         ep->dwc_ep.dma_addr = cfi->buf_in.addr;
+-00211                         ep->dwc_ep.start_xfer_buff = cfi->buf_in.buf;
+-00212                         ep->dwc_ep.xfer_buff = cfi->buf_in.buf;
+-00213                         ep->dwc_ep.xfer_len = retval;
+-00214                         ep->dwc_ep.xfer_count = 0;
+-00215                         ep->dwc_ep.sent_zlp = 0;
+-00216                         ep->dwc_ep.total_len = ep->dwc_ep.xfer_len;
+-00217 
+-00218                         pcd->ep0_pending = 1;
+-00219                         dwc_otg_ep0_start_transfer(coreif, &ep->dwc_ep);
+-00220                 }
+-00221                 retval = 0;
+-00222                 break;
+-00223 
+-00224         case VEN_CORE_GET_FEATURE:
+-00225                 CFI_INFO("VEN_CORE_GET_FEATURE\n");
+-00226                 retval = cfi_get_feature_value(cfi->buf_in.buf, CFI_IN_BUF_LEN,
+-00227                                                pcd, ctrl);
+-00228                 if (retval >= 0) {
+-00229                         ep = &pcd->ep0;
+-00230 
+-00231                         retval = min((uint16_t) retval, wLen);
+-00232                         /* Transfer this buffer to the host through the EP0-IN EP */
+-00233                         ep->dwc_ep.dma_addr = cfi->buf_in.addr;
+-00234                         ep->dwc_ep.start_xfer_buff = cfi->buf_in.buf;
+-00235                         ep->dwc_ep.xfer_buff = cfi->buf_in.buf;
+-00236                         ep->dwc_ep.xfer_len = retval;
+-00237                         ep->dwc_ep.xfer_count = 0;
+-00238                         ep->dwc_ep.sent_zlp = 0;
+-00239                         ep->dwc_ep.total_len = ep->dwc_ep.xfer_len;
+-00240 
+-00241                         pcd->ep0_pending = 1;
+-00242                         dwc_otg_ep0_start_transfer(coreif, &ep->dwc_ep);
+-00243                 }
+-00244                 CFI_INFO("VEN_CORE_GET_FEATURE=%d\n", retval);
+-00245                 dump_msg(cfi->buf_in.buf, retval);
+-00246                 break;
+-00247 
+-00248         case VEN_CORE_SET_FEATURE:
+-00249                 CFI_INFO("VEN_CORE_SET_FEATURE\n");
+-00250                 /* Set up an XFER to get the data stage of the control request,
+-00251                  * which is the new value of the feature to be modified.
+-00252                  */
+-00253                 ep = &pcd->ep0;
+-00254                 ep->dwc_ep.is_in = 0;
+-00255                 ep->dwc_ep.dma_addr = cfi->buf_out.addr;
+-00256                 ep->dwc_ep.start_xfer_buff = cfi->buf_out.buf;
+-00257                 ep->dwc_ep.xfer_buff = cfi->buf_out.buf;
+-00258                 ep->dwc_ep.xfer_len = wLen;
+-00259                 ep->dwc_ep.xfer_count = 0;
+-00260                 ep->dwc_ep.sent_zlp = 0;
+-00261                 ep->dwc_ep.total_len = ep->dwc_ep.xfer_len;
+-00262 
+-00263                 pcd->ep0_pending = 1;
+-00264                 /* Read the control write's data stage */
+-00265                 dwc_otg_ep0_start_transfer(coreif, &ep->dwc_ep);
+-00266                 retval = 0;
+-00267                 break;
+-00268 
+-00269         case VEN_CORE_RESET_FEATURES:
+-00270                 CFI_INFO("VEN_CORE_RESET_FEATURES\n");
+-00271                 cfi->need_gadget_att = 1;
+-00272                 cfi->need_status_in_complete = 1;
+-00273                 retval = cfi_preproc_reset(pcd, ctrl);
+-00274                 CFI_INFO("VEN_CORE_RESET_FEATURES = (%d)\n", retval);
+-00275                 break;
+-00276 
+-00277         case VEN_CORE_ACTIVATE_FEATURES:
+-00278                 CFI_INFO("VEN_CORE_ACTIVATE_FEATURES\n");
+-00279                 break;
+-00280 
+-00281         case VEN_CORE_READ_REGISTER:
+-00282                 CFI_INFO("VEN_CORE_READ_REGISTER\n");
+-00283                 /* wValue optionally contains the HI WORD of the register offset and
+-00284                  * wIndex contains the LOW WORD of the register offset 
+-00285                  */
+-00286                 if (wValue == 0) {
+-00287                         /* @TODO - MAS - fix the access to the base field */
+-00288                         regaddr = 0;
+-00289                         //regaddr = (uint32_t) pcd->otg_dev->os_dep.base;
+-00290                         //GET_CORE_IF(pcd)->co
+-00291                         regaddr |= wIndex;
+-00292                 } else {
+-00293                         regaddr = (wValue << 16) | wIndex;
+-00294                 }
+-00295 
+-00296                 /* Read a 32-bit value of the memory at the regaddr */
+-00297                 regval = DWC_READ_REG32((uint32_t *) regaddr);
+-00298 
+-00299                 ep = &pcd->ep0;
+-00300                 dwc_memcpy(cfi->buf_in.buf, &regval, sizeof(uint32_t));
+-00301                 ep->dwc_ep.is_in = 1;
+-00302                 ep->dwc_ep.dma_addr = cfi->buf_in.addr;
+-00303                 ep->dwc_ep.start_xfer_buff = cfi->buf_in.buf;
+-00304                 ep->dwc_ep.xfer_buff = cfi->buf_in.buf;
+-00305                 ep->dwc_ep.xfer_len = wLen;
+-00306                 ep->dwc_ep.xfer_count = 0;
+-00307                 ep->dwc_ep.sent_zlp = 0;
+-00308                 ep->dwc_ep.total_len = ep->dwc_ep.xfer_len;
+-00309 
+-00310                 pcd->ep0_pending = 1;
+-00311                 dwc_otg_ep0_start_transfer(coreif, &ep->dwc_ep);
+-00312                 cfi->need_gadget_att = 0;
+-00313                 retval = 0;
+-00314                 break;
+-00315 
+-00316         case VEN_CORE_WRITE_REGISTER:
+-00317                 CFI_INFO("VEN_CORE_WRITE_REGISTER\n");
+-00318                 /* Set up an XFER to get the data stage of the control request,
+-00319                  * which is the new value of the register to be modified.
+-00320                  */
+-00321                 ep = &pcd->ep0;
+-00322                 ep->dwc_ep.is_in = 0;
+-00323                 ep->dwc_ep.dma_addr = cfi->buf_out.addr;
+-00324                 ep->dwc_ep.start_xfer_buff = cfi->buf_out.buf;
+-00325                 ep->dwc_ep.xfer_buff = cfi->buf_out.buf;
+-00326                 ep->dwc_ep.xfer_len = wLen;
+-00327                 ep->dwc_ep.xfer_count = 0;
+-00328                 ep->dwc_ep.sent_zlp = 0;
+-00329                 ep->dwc_ep.total_len = ep->dwc_ep.xfer_len;
+-00330 
+-00331                 pcd->ep0_pending = 1;
+-00332                 /* Read the control write's data stage */
+-00333                 dwc_otg_ep0_start_transfer(coreif, &ep->dwc_ep);
+-00334                 retval = 0;
+-00335                 break;
+-00336 
+-00337         default:
+-00338                 retval = -DWC_E_NOT_SUPPORTED;
+-00339                 break;
+-00340         }
+-00341 
+-00342         return retval;
+-00343 }
+-00344 
+-00356 static int cfi_core_features_buf(uint8_t * buf, uint16_t buflen)
+-00357 {
+-00358         cfi_feature_desc_header_t *prop_hdr = prop_descs;
+-00359         cfi_feature_desc_header_t *prop;
+-00360         cfi_all_features_header_t *all_props_hdr = &all_props_desc_header;
+-00361         cfi_all_features_header_t *tmp;
+-00362         uint8_t *tmpbuf = buf;
+-00363         const uint8_t *pname = NULL;
+-00364         int i, j, namelen = 0, totlen;
+-00365 
+-00366         /* Prepare and copy the core features into the buffer */
+-00367         CFI_INFO("%s:\n", __func__);
+-00368 
+-00369         tmp = (cfi_all_features_header_t *) tmpbuf;
+-00370         *tmp = *all_props_hdr;
+-00371         tmpbuf += CFI_ALL_FEATURES_HDR_LEN;
+-00372 
+-00373         j = sizeof(prop_descs) / sizeof(cfi_all_features_header_t);
+-00374         for (i = 0; i < j; i++, prop_hdr++) {
+-00375                 pname = get_prop_name(prop_hdr->wFeatureID, &namelen);
+-00376                 prop = (cfi_feature_desc_header_t *) tmpbuf;
+-00377                 *prop = *prop_hdr;
+-00378 
+-00379                 prop->bNameLen = namelen;
+-00380                 prop->wLength =
+-00381                     DWC_CONSTANT_CPU_TO_LE16(CFI_FEATURE_DESC_HDR_LEN +
+-00382                                              namelen);
+-00383 
+-00384                 tmpbuf += CFI_FEATURE_DESC_HDR_LEN;
+-00385                 dwc_memcpy(tmpbuf, pname, namelen);
+-00386                 tmpbuf += namelen;
+-00387         }
+-00388 
+-00389         totlen = tmpbuf - buf;
+-00390 
+-00391         if (totlen > 0) {
+-00392                 tmp = (cfi_all_features_header_t *) buf;
+-00393                 tmp->wTotalLen = DWC_CONSTANT_CPU_TO_LE16(totlen);
+-00394         }
+-00395 
+-00396         return totlen;
+-00397 }
+-00398 
+-00402 static void cfi_release(cfiobject_t * cfiobj)
+-00403 {
+-00404         cfi_ep_t *cfiep;
+-00405         dwc_list_link_t *tmp;
+-00406 
+-00407         CFI_INFO("%s\n", __func__);
+-00408 
+-00409         if (cfiobj->buf_in.buf) {
+-00410                 DWC_DMA_FREE(CFI_IN_BUF_LEN, cfiobj->buf_in.buf,
+-00411                              cfiobj->buf_in.addr);
+-00412                 cfiobj->buf_in.buf = NULL;
+-00413         }
+-00414 
+-00415         if (cfiobj->buf_out.buf) {
+-00416                 DWC_DMA_FREE(CFI_OUT_BUF_LEN, cfiobj->buf_out.buf,
+-00417                              cfiobj->buf_out.addr);
+-00418                 cfiobj->buf_out.buf = NULL;
+-00419         }
+-00420 
+-00421         /* Free the Buffer Setup values for each EP */
+-00422         //list_for_each_entry(cfiep, &cfiobj->active_eps, lh) {
+-00423         DWC_LIST_FOREACH(tmp, &cfiobj->active_eps) {
+-00424                 cfiep = DWC_LIST_ENTRY(tmp, struct cfi_ep, lh);
+-00425                 cfi_free_ep_bs_dyn_data(cfiep);
+-00426         }
+-00427 }
+-00428 
+-00432 static void cfi_free_ep_bs_dyn_data(cfi_ep_t * cfiep)
+-00433 {
+-00434         if (cfiep->bm_sg) {
+-00435                 DWC_FREE(cfiep->bm_sg);
+-00436                 cfiep->bm_sg = NULL;
+-00437         }
+-00438 
+-00439         if (cfiep->bm_align) {
+-00440                 DWC_FREE(cfiep->bm_align);
+-00441                 cfiep->bm_align = NULL;
+-00442         }
+-00443 
+-00444         if (cfiep->bm_concat) {
+-00445                 if (NULL != cfiep->bm_concat->wTxBytes) {
+-00446                         DWC_FREE(cfiep->bm_concat->wTxBytes);
+-00447                         cfiep->bm_concat->wTxBytes = NULL;
+-00448                 }
+-00449                 DWC_FREE(cfiep->bm_concat);
+-00450                 cfiep->bm_concat = NULL;
+-00451         }
+-00452 }
+-00453 
+-00459 static int cfi_ep_init_defaults(struct dwc_otg_pcd *pcd, cfi_ep_t * cfiep)
+-00460 {
+-00461         int retval = 0;
+-00462 
+-00463         cfiep->bm_sg = DWC_ALLOC(sizeof(ddma_sg_buffer_setup_t));
+-00464         if (NULL == cfiep->bm_sg) {
+-00465                 CFI_INFO("Failed to allocate memory for SG feature value\n");
+-00466                 return -DWC_E_NO_MEMORY;
+-00467         }
+-00468         dwc_memset(cfiep->bm_sg, 0, sizeof(ddma_sg_buffer_setup_t));
+-00469 
+-00470         /* For the Concatenation feature's default value we do not allocate
+-00471          * memory for the wTxBytes field - it will be done in the set_feature_value
+-00472          * request handler.
+-00473          */
+-00474         cfiep->bm_concat = DWC_ALLOC(sizeof(ddma_concat_buffer_setup_t));
+-00475         if (NULL == cfiep->bm_concat) {
+-00476                 CFI_INFO
+-00477                     ("Failed to allocate memory for CONCATENATION feature value\n");
+-00478                 DWC_FREE(cfiep->bm_sg);
+-00479                 return -DWC_E_NO_MEMORY;
+-00480         }
+-00481         dwc_memset(cfiep->bm_concat, 0, sizeof(ddma_concat_buffer_setup_t));
+-00482 
+-00483         cfiep->bm_align = DWC_ALLOC(sizeof(ddma_align_buffer_setup_t));
+-00484         if (NULL == cfiep->bm_align) {
+-00485                 CFI_INFO
+-00486                     ("Failed to allocate memory for Alignment feature value\n");
+-00487                 DWC_FREE(cfiep->bm_sg);
+-00488                 DWC_FREE(cfiep->bm_concat);
+-00489                 return -DWC_E_NO_MEMORY;
+-00490         }
+-00491         dwc_memset(cfiep->bm_align, 0, sizeof(ddma_align_buffer_setup_t));
+-00492 
+-00493         return retval;
+-00494 }
+-00495 
+-00507 static int cfi_ep_enable(struct cfiobject *cfi, struct dwc_otg_pcd *pcd,
+-00508                          struct dwc_otg_pcd_ep *ep)
+-00509 {
+-00510         cfi_ep_t *cfiep;
+-00511         int retval = -DWC_E_NOT_SUPPORTED;
+-00512 
+-00513         CFI_INFO("%s: epname=%s; epnum=0x%02x\n", __func__,
+-00514                  "EP_" /*ep->ep.name */ , ep->desc->bEndpointAddress);
+-00515         /* MAS - Check whether this endpoint already is in the list */
+-00516         cfiep = get_cfi_ep_by_pcd_ep(cfi, ep);
+-00517 
+-00518         if (NULL == cfiep) {
+-00519                 /* Allocate a cfi_ep_t object */
+-00520                 cfiep = DWC_ALLOC(sizeof(cfi_ep_t));
+-00521                 if (NULL == cfiep) {
+-00522                         CFI_INFO
+-00523                             ("Unable to allocate memory for <cfiep> in function %s\n",
+-00524                              __func__);
+-00525                         return -DWC_E_NO_MEMORY;
+-00526                 }
+-00527                 dwc_memset(cfiep, 0, sizeof(cfi_ep_t));
+-00528 
+-00529                 /* Save the dwc_otg_pcd_ep pointer in the cfiep object */
+-00530                 cfiep->ep = ep;
+-00531 
+-00532                 /* Allocate the DMA Descriptors chain of MAX_DMA_DESCS_PER_EP count */
+-00533                 ep->dwc_ep.descs =
+-00534                     DWC_DMA_ALLOC(MAX_DMA_DESCS_PER_EP *
+-00535                                   sizeof(dwc_otg_dma_desc_t),
+-00536                                   &ep->dwc_ep.descs_dma_addr);
+-00537 
+-00538                 if (NULL == ep->dwc_ep.descs) {
+-00539                         DWC_FREE(cfiep);
+-00540                         return -DWC_E_NO_MEMORY;
+-00541                 }
+-00542 
+-00543                 DWC_LIST_INIT(&cfiep->lh);
+-00544 
+-00545                 /* Set the buffer mode to BM_STANDARD. It will be modified 
+-00546                  * when building descriptors for a specific buffer mode */
+-00547                 ep->dwc_ep.buff_mode = BM_STANDARD;
+-00548 
+-00549                 /* Create and initialize the default values for this EP's Buffer modes */
+-00550                 if ((retval = cfi_ep_init_defaults(pcd, cfiep)) < 0)
+-00551                         return retval;
+-00552 
+-00553                 /* Add the cfi_ep_t object to the CFI object's list of active endpoints */
+-00554                 DWC_LIST_INSERT_TAIL(&cfi->active_eps, &cfiep->lh);
+-00555                 retval = 0;
+-00556         } else {                /* The sought EP already is in the list */
+-00557                 CFI_INFO("%s: The sought EP already is in the list\n",
+-00558                          __func__);
+-00559         }
+-00560 
+-00561         return retval;
+-00562 }
+-00563 
+-00569 static int cfi_ctrl_write_complete(struct cfiobject *cfi,
+-00570                                    struct dwc_otg_pcd *pcd)
+-00571 {
+-00572         uint32_t addr, reg_value;
+-00573         uint16_t wIndex, wValue;
+-00574         uint8_t bRequest;
+-00575         uint8_t *buf = cfi->buf_out.buf;
+-00576         //struct usb_ctrlrequest *ctrl_req = &cfi->ctrl_req_saved;
+-00577         struct cfi_usb_ctrlrequest *ctrl_req = &cfi->ctrl_req;
+-00578         int retval = -DWC_E_NOT_SUPPORTED;
+-00579 
+-00580         CFI_INFO("%s\n", __func__);
+-00581 
+-00582         bRequest = ctrl_req->bRequest;
+-00583         wIndex = DWC_CONSTANT_CPU_TO_LE16(ctrl_req->wIndex);
+-00584         wValue = DWC_CONSTANT_CPU_TO_LE16(ctrl_req->wValue);
+-00585 
+-00586         /* 
+-00587          * Save the pointer to the data stage in the ctrl_req's <data> field.
+-00588          * The request should be already saved in the command stage by now.
+-00589          */
+-00590         ctrl_req->data = cfi->buf_out.buf;
+-00591         cfi->need_status_in_complete = 0;
+-00592         cfi->need_gadget_att = 0;
+-00593 
+-00594         switch (bRequest) {
+-00595         case VEN_CORE_WRITE_REGISTER:
+-00596                 /* The buffer contains raw data of the new value for the register */
+-00597                 reg_value = *((uint32_t *) buf);
+-00598                 if (wValue == 0) {
+-00599                         addr = 0;
+-00600                         //addr = (uint32_t) pcd->otg_dev->os_dep.base;
+-00601                         addr += wIndex;
+-00602                 } else {
+-00603                         addr = (wValue << 16) | wIndex;
+-00604                 }
+-00605 
+-00606                 //writel(reg_value, addr);
+-00607 
+-00608                 retval = 0;
+-00609                 cfi->need_status_in_complete = 1;
+-00610                 break;
+-00611 
+-00612         case VEN_CORE_SET_FEATURE:
+-00613                 /* The buffer contains raw data of the new value of the feature */
+-00614                 retval = cfi_set_feature_value(pcd);
+-00615                 if (retval < 0)
+-00616                         return retval;
+-00617 
+-00618                 cfi->need_status_in_complete = 1;
+-00619                 break;
+-00620 
+-00621         default:
+-00622                 break;
+-00623         }
+-00624 
+-00625         return retval;
+-00626 }
+-00627 
+-00631 static void cfi_build_sg_descs(struct cfiobject *cfi, cfi_ep_t * cfiep,
+-00632                                dwc_otg_pcd_request_t * req)
+-00633 {
+-00634         struct dwc_otg_pcd_ep *ep = cfiep->ep;
+-00635         ddma_sg_buffer_setup_t *sgval = cfiep->bm_sg;
+-00636         struct dwc_otg_dma_desc *desc = cfiep->ep->dwc_ep.descs;
+-00637         struct dwc_otg_dma_desc *desc_last = cfiep->ep->dwc_ep.descs;
+-00638         dma_addr_t buff_addr = req->dma;
+-00639         int i;
+-00640         uint32_t txsize, off;
+-00641 
+-00642         txsize = sgval->wSize;
+-00643         off = sgval->bOffset;
+-00644 
+-00645 //      CFI_INFO("%s: %s TXSIZE=0x%08x; OFFSET=0x%08x\n", 
+-00646 //              __func__, cfiep->ep->ep.name, txsize, off);
+-00647 
+-00648         for (i = 0; i < sgval->bCount; i++) {
+-00649                 desc->status.b.bs = BS_HOST_BUSY;
+-00650                 desc->buf = buff_addr;
+-00651                 desc->status.b.l = 0;
+-00652                 desc->status.b.ioc = 0;
+-00653                 desc->status.b.sp = 0;
+-00654                 desc->status.b.bytes = txsize;
+-00655                 desc->status.b.bs = BS_HOST_READY;
+-00656 
+-00657                 /* Set the next address of the buffer */
+-00658                 buff_addr += txsize + off;
+-00659                 desc_last = desc;
+-00660                 desc++;
+-00661         }
+-00662 
+-00663         /* Set the last, ioc and sp bits on the Last DMA Descriptor */
+-00664         desc_last->status.b.l = 1;
+-00665         desc_last->status.b.ioc = 1;
+-00666         desc_last->status.b.sp = ep->dwc_ep.sent_zlp;
+-00667         /* Save the last DMA descriptor pointer */
+-00668         cfiep->dma_desc_last = desc_last;
+-00669         cfiep->desc_count = sgval->bCount;
+-00670 }
+-00671 
+-00675 static void cfi_build_concat_descs(struct cfiobject *cfi, cfi_ep_t * cfiep,
+-00676                                    dwc_otg_pcd_request_t * req)
+-00677 {
+-00678         struct dwc_otg_pcd_ep *ep = cfiep->ep;
+-00679         ddma_concat_buffer_setup_t *concatval = cfiep->bm_concat;
+-00680         struct dwc_otg_dma_desc *desc = cfiep->ep->dwc_ep.descs;
+-00681         struct dwc_otg_dma_desc *desc_last = cfiep->ep->dwc_ep.descs;
+-00682         dma_addr_t buff_addr = req->dma;
+-00683         int i;
+-00684         uint16_t *txsize;
+-00685 
+-00686         txsize = concatval->wTxBytes;
+-00687 
+-00688         for (i = 0; i < concatval->hdr.bDescCount; i++) {
+-00689                 desc->buf = buff_addr;
+-00690                 desc->status.b.bs = BS_HOST_BUSY;
+-00691                 desc->status.b.l = 0;
+-00692                 desc->status.b.ioc = 0;
+-00693                 desc->status.b.sp = 0;
+-00694                 desc->status.b.bytes = *txsize;
+-00695                 desc->status.b.bs = BS_HOST_READY;
+-00696 
+-00697                 txsize++;
+-00698                 /* Set the next address of the buffer */
+-00699                 buff_addr += UGETW(ep->desc->wMaxPacketSize);
+-00700                 desc_last = desc;
+-00701                 desc++;
+-00702         }
+-00703 
+-00704         /* Set the last, ioc and sp bits on the Last DMA Descriptor */
+-00705         desc_last->status.b.l = 1;
+-00706         desc_last->status.b.ioc = 1;
+-00707         desc_last->status.b.sp = ep->dwc_ep.sent_zlp;
+-00708         cfiep->dma_desc_last = desc_last;
+-00709         cfiep->desc_count = concatval->hdr.bDescCount;
+-00710 }
+-00711 
+-00715 static void cfi_build_circ_descs(struct cfiobject *cfi, cfi_ep_t * cfiep,
+-00716                                  dwc_otg_pcd_request_t * req)
+-00717 {
+-00718         /* @todo: MAS - add implementation when this feature needs to be tested */
+-00719 }
+-00720 
+-00724 static void cfi_build_align_descs(struct cfiobject *cfi, cfi_ep_t * cfiep,
+-00725                                   dwc_otg_pcd_request_t * req)
+-00726 {
+-00727         struct dwc_otg_pcd_ep *ep = cfiep->ep;
+-00728         ddma_align_buffer_setup_t *alignval = cfiep->bm_align;
+-00729         struct dwc_otg_dma_desc *desc = cfiep->ep->dwc_ep.descs;
+-00730         dma_addr_t buff_addr = req->dma;
+-00731 
+-00732         desc->status.b.bs = BS_HOST_BUSY;
+-00733         desc->status.b.l = 1;
+-00734         desc->status.b.ioc = 1;
+-00735         desc->status.b.sp = ep->dwc_ep.sent_zlp;
+-00736         desc->status.b.bytes = req->length;
+-00737         /* Adjust the buffer alignment */
+-00738         desc->buf = (buff_addr + alignval->bAlign);
+-00739         desc->status.b.bs = BS_HOST_READY;
+-00740         cfiep->dma_desc_last = desc;
+-00741         cfiep->desc_count = 1;
+-00742 }
+-00743 
+-00748 static void cfi_build_descriptors(struct cfiobject *cfi,
+-00749                                   struct dwc_otg_pcd *pcd,
+-00750                                   struct dwc_otg_pcd_ep *ep,
+-00751                                   dwc_otg_pcd_request_t * req)
+-00752 {
+-00753         cfi_ep_t *cfiep;
+-00754 
+-00755         /* Get the cfiep by the dwc_otg_pcd_ep */
+-00756         cfiep = get_cfi_ep_by_pcd_ep(cfi, ep);
+-00757         if (NULL == cfiep) {
+-00758                 CFI_INFO("%s: Unable to find a matching active endpoint\n",
+-00759                          __func__);
+-00760                 return;
+-00761         }
+-00762 
+-00763         cfiep->xfer_len = req->length;
+-00764 
+-00765         /* Iterate through all the DMA descriptors */
+-00766         switch (cfiep->ep->dwc_ep.buff_mode) {
+-00767         case BM_SG:
+-00768                 cfi_build_sg_descs(cfi, cfiep, req);
+-00769                 break;
+-00770 
+-00771         case BM_CONCAT:
+-00772                 cfi_build_concat_descs(cfi, cfiep, req);
+-00773                 break;
+-00774 
+-00775         case BM_CIRCULAR:
+-00776                 cfi_build_circ_descs(cfi, cfiep, req);
+-00777                 break;
+-00778 
+-00779         case BM_ALIGN:
+-00780                 cfi_build_align_descs(cfi, cfiep, req);
+-00781                 break;
+-00782 
+-00783         default:
+-00784                 break;
+-00785         }
+-00786 }
+-00787 
+-00791 static void *cfi_ep_alloc_buf(struct cfiobject *cfi, struct dwc_otg_pcd *pcd,
+-00792                               struct dwc_otg_pcd_ep *ep, dma_addr_t * dma,
+-00793                               unsigned size, gfp_t flags)
+-00794 {
+-00795         return DWC_DMA_ALLOC(size, dma);
+-00796 }
+-00797 
+-00801 int init_cfi(cfiobject_t * cfiobj)
+-00802 {
+-00803         CFI_INFO("%s\n", __func__);
+-00804 
+-00805         /* Allocate a buffer for IN XFERs */
+-00806         cfiobj->buf_in.buf =
+-00807             DWC_DMA_ALLOC(CFI_IN_BUF_LEN, &cfiobj->buf_in.addr);
+-00808         if (NULL == cfiobj->buf_in.buf) {
+-00809                 CFI_INFO("Unable to allocate buffer for INs\n");
+-00810                 return -DWC_E_NO_MEMORY;
+-00811         }
+-00812 
+-00813         /* Allocate a buffer for OUT XFERs */
+-00814         cfiobj->buf_out.buf =
+-00815             DWC_DMA_ALLOC(CFI_OUT_BUF_LEN, &cfiobj->buf_out.addr);
+-00816         if (NULL == cfiobj->buf_out.buf) {
+-00817                 CFI_INFO("Unable to allocate buffer for OUT\n");
+-00818                 return -DWC_E_NO_MEMORY;
+-00819         }
+-00820 
+-00821         /* Initialize the callback function pointers */
+-00822         cfiobj->ops.release = cfi_release;
+-00823         cfiobj->ops.ep_enable = cfi_ep_enable;
+-00824         cfiobj->ops.ctrl_write_complete = cfi_ctrl_write_complete;
+-00825         cfiobj->ops.build_descriptors = cfi_build_descriptors;
+-00826         cfiobj->ops.ep_alloc_buf = cfi_ep_alloc_buf;
+-00827 
+-00828         /* Initialize the list of active endpoints in the CFI object */
+-00829         DWC_LIST_INIT(&cfiobj->active_eps);
+-00830 
+-00831         return 0;
+-00832 }
+-00833 
+-00839 static int cfi_get_feature_value(uint8_t * buf, uint16_t buflen,
+-00840                                  struct dwc_otg_pcd *pcd,
+-00841                                  struct cfi_usb_ctrlrequest *ctrl_req)
+-00842 {
+-00843         int retval = -DWC_E_NOT_SUPPORTED;
+-00844         struct dwc_otg_core_if *coreif = GET_CORE_IF(pcd);
+-00845         uint16_t dfifo, rxfifo, txfifo;
+-00846 
+-00847         switch (ctrl_req->wIndex) {
+-00848                 /* Whether the DDMA is enabled or not */
+-00849         case FT_ID_DMA_MODE:
+-00850                 *buf = (coreif->dma_enable && coreif->dma_desc_enable) ? 1 : 0;
+-00851                 retval = 1;
+-00852                 break;
+-00853 
+-00854         case FT_ID_DMA_BUFFER_SETUP:
+-00855                 retval = cfi_ep_get_sg_val(buf, pcd, ctrl_req);
+-00856                 break;
+-00857 
+-00858         case FT_ID_DMA_BUFF_ALIGN:
+-00859                 retval = cfi_ep_get_align_val(buf, pcd, ctrl_req);
+-00860                 break;
+-00861 
+-00862         case FT_ID_DMA_CONCAT_SETUP:
+-00863                 retval = cfi_ep_get_concat_val(buf, pcd, ctrl_req);
+-00864                 break;
+-00865 
+-00866         case FT_ID_DMA_CIRCULAR:
+-00867                 CFI_INFO("GetFeature value (FT_ID_DMA_CIRCULAR)\n");
+-00868                 break;
+-00869 
+-00870         case FT_ID_THRESHOLD_SETUP:
+-00871                 CFI_INFO("GetFeature value (FT_ID_THRESHOLD_SETUP)\n");
+-00872                 break;
+-00873 
+-00874         case FT_ID_DFIFO_DEPTH:
+-00875                 dfifo = get_dfifo_size(coreif);
+-00876                 *((uint16_t *) buf) = dfifo;
+-00877                 retval = sizeof(uint16_t);
+-00878                 break;
+-00879 
+-00880         case FT_ID_TX_FIFO_DEPTH:
+-00881                 retval = get_txfifo_size(pcd, ctrl_req->wValue);
+-00882                 if (retval >= 0) {
+-00883                         txfifo = retval;
+-00884                         *((uint16_t *) buf) = txfifo;
+-00885                         retval = sizeof(uint16_t);
+-00886                 }
+-00887                 break;
+-00888 
+-00889         case FT_ID_RX_FIFO_DEPTH:
+-00890                 retval = get_rxfifo_size(coreif, ctrl_req->wValue);
+-00891                 if (retval >= 0) {
+-00892                         rxfifo = retval;
+-00893                         *((uint16_t *) buf) = rxfifo;
+-00894                         retval = sizeof(uint16_t);
+-00895                 }
+-00896                 break;
+-00897         }
+-00898 
+-00899         return retval;
+-00900 }
+-00901 
+-00905 static int cfi_reset_sg_val(cfi_ep_t * cfiep)
+-00906 {
+-00907         dwc_memset(cfiep->bm_sg, 0, sizeof(ddma_sg_buffer_setup_t));
+-00908         return 0;
+-00909 }
+-00910 
+-00914 static int cfi_reset_align_val(cfi_ep_t * cfiep)
+-00915 {
+-00916         dwc_memset(cfiep->bm_sg, 0, sizeof(ddma_sg_buffer_setup_t));
+-00917         return 0;
+-00918 }
+-00919 
+-00925 static int cfi_reset_concat_val(cfi_ep_t * cfiep)
+-00926 {
+-00927         /* First we need to free the wTxBytes field */
+-00928         if (cfiep->bm_concat->wTxBytes) {
+-00929                 DWC_FREE(cfiep->bm_concat->wTxBytes);
+-00930                 cfiep->bm_concat->wTxBytes = NULL;
+-00931         }
+-00932 
+-00933         dwc_memset(cfiep->bm_concat, 0, sizeof(ddma_concat_buffer_setup_t));
+-00934         return 0;
+-00935 }
+-00936 
+-00940 static int cfi_ep_reset_all_setup_vals(cfi_ep_t * cfiep)
+-00941 {
+-00942         cfi_reset_sg_val(cfiep);
+-00943         cfi_reset_align_val(cfiep);
+-00944         cfi_reset_concat_val(cfiep);
+-00945         return 0;
+-00946 }
+-00947 
+-00948 static int cfi_handle_reset_fifo_val(struct dwc_otg_pcd *pcd, uint8_t ep_addr,
+-00949                                      uint8_t rx_rst, uint8_t tx_rst)
+-00950 {
+-00951         int retval = -DWC_E_INVALID;
+-00952         uint16_t tx_siz[15];
+-00953         uint16_t rx_siz = 0;
+-00954         dwc_otg_pcd_ep_t *ep = NULL;
+-00955         dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
+-00956         dwc_otg_core_params_t *params = GET_CORE_IF(pcd)->core_params;
+-00957 
+-00958         if (rx_rst) {
+-00959                 rx_siz = params->dev_rx_fifo_size;
+-00960                 params->dev_rx_fifo_size = GET_CORE_IF(pcd)->init_rxfsiz;
+-00961         }
+-00962 
+-00963         if (tx_rst) {
+-00964                 if (ep_addr == 0) {
+-00965                         int i;
+-00966 
+-00967                         for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {
+-00968                                 tx_siz[i] =
+-00969                                     core_if->core_params->dev_tx_fifo_size[i];
+-00970                                 core_if->core_params->dev_tx_fifo_size[i] =
+-00971                                     core_if->init_txfsiz[i];
+-00972                         }
+-00973                 } else {
+-00974 
+-00975                         ep = get_ep_by_addr(pcd, ep_addr);
+-00976 
+-00977                         if (NULL == ep) {
+-00978                                 CFI_INFO
+-00979                                     ("%s: Unable to get the endpoint addr=0x%02x\n",
+-00980                                      __func__, ep_addr);
+-00981                                 return -DWC_E_INVALID;
+-00982                         }
+-00983 
+-00984                         tx_siz[0] =
+-00985                             params->dev_tx_fifo_size[ep->dwc_ep.tx_fifo_num -
+-00986                                                      1];
+-00987                         params->dev_tx_fifo_size[ep->dwc_ep.tx_fifo_num - 1] =
+-00988                             GET_CORE_IF(pcd)->init_txfsiz[ep->
+-00989                                                           dwc_ep.tx_fifo_num -
+-00990                                                           1];
+-00991                 }
+-00992         }
+-00993 
+-00994         if (resize_fifos(GET_CORE_IF(pcd))) {
+-00995                 retval = 0;
+-00996         } else {
+-00997                 CFI_INFO
+-00998                     ("%s: Error resetting the feature Reset All(FIFO size)\n",
+-00999                      __func__);
+-01000                 if (rx_rst) {
+-01001                         params->dev_rx_fifo_size = rx_siz;
+-01002                 }
+-01003 
+-01004                 if (tx_rst) {
+-01005                         if (ep_addr == 0) {
+-01006                                 int i;
+-01007                                 for (i = 0; i < core_if->hwcfg4.b.num_in_eps;
+-01008                                      i++) {
+-01009                                         core_if->
+-01010                                             core_params->dev_tx_fifo_size[i] =
+-01011                                             tx_siz[i];
+-01012                                 }
+-01013                         } else {
+-01014                                 params->dev_tx_fifo_size[ep->
+-01015                                                          dwc_ep.tx_fifo_num -
+-01016                                                          1] = tx_siz[0];
+-01017                         }
+-01018                 }
+-01019                 retval = -DWC_E_INVALID;
+-01020         }
+-01021         return retval;
+-01022 }
+-01023 
+-01024 static int cfi_handle_reset_all(struct dwc_otg_pcd *pcd, uint8_t addr)
+-01025 {
+-01026         int retval = 0;
+-01027         cfi_ep_t *cfiep;
+-01028         cfiobject_t *cfi = pcd->cfi;
+-01029         dwc_list_link_t *tmp;
+-01030 
+-01031         retval = cfi_handle_reset_fifo_val(pcd, addr, 1, 1);
+-01032         if (retval < 0) {
+-01033                 return retval;
+-01034         }
+-01035 
+-01036         /* If the EP address is known then reset the features for only that EP */
+-01037         if (addr) {
+-01038                 cfiep = get_cfi_ep_by_addr(pcd->cfi, addr);
+-01039                 if (NULL == cfiep) {
+-01040                         CFI_INFO("%s: Error getting the EP address 0x%02x\n",
+-01041                                  __func__, addr);
+-01042                         return -DWC_E_INVALID;
+-01043                 }
+-01044                 retval = cfi_ep_reset_all_setup_vals(cfiep);
+-01045                 cfiep->ep->dwc_ep.buff_mode = BM_STANDARD;
+-01046         }
+-01047         /* Otherwise (wValue == 0), reset all features of all EP's */
+-01048         else {
+-01049                 /* Traverse all the active EP's and reset the feature(s) value(s) */
+-01050                 //list_for_each_entry(cfiep, &cfi->active_eps, lh) {
+-01051                 DWC_LIST_FOREACH(tmp, &cfi->active_eps) {
+-01052                         cfiep = DWC_LIST_ENTRY(tmp, struct cfi_ep, lh);
+-01053                         retval = cfi_ep_reset_all_setup_vals(cfiep);
+-01054                         cfiep->ep->dwc_ep.buff_mode = BM_STANDARD;
+-01055                         if (retval < 0) {
+-01056                                 CFI_INFO
+-01057                                     ("%s: Error resetting the feature Reset All\n",
+-01058                                      __func__);
+-01059                                 return retval;
+-01060                         }
+-01061                 }
+-01062         }
+-01063         return retval;
+-01064 }
+-01065 
+-01066 static int cfi_handle_reset_dma_buff_setup(struct dwc_otg_pcd *pcd,
+-01067                                            uint8_t addr)
+-01068 {
+-01069         int retval = 0;
+-01070         cfi_ep_t *cfiep;
+-01071         cfiobject_t *cfi = pcd->cfi;
+-01072         dwc_list_link_t *tmp;
+-01073 
+-01074         /* If the EP address is known then reset the features for only that EP */
+-01075         if (addr) {
+-01076                 cfiep = get_cfi_ep_by_addr(pcd->cfi, addr);
+-01077                 if (NULL == cfiep) {
+-01078                         CFI_INFO("%s: Error getting the EP address 0x%02x\n",
+-01079                                  __func__, addr);
+-01080                         return -DWC_E_INVALID;
+-01081                 }
+-01082                 retval = cfi_reset_sg_val(cfiep);
+-01083         }
+-01084         /* Otherwise (wValue == 0), reset all features of all EP's */
+-01085         else {
+-01086                 /* Traverse all the active EP's and reset the feature(s) value(s) */
+-01087                 //list_for_each_entry(cfiep, &cfi->active_eps, lh) {
+-01088                 DWC_LIST_FOREACH(tmp, &cfi->active_eps) {
+-01089                         cfiep = DWC_LIST_ENTRY(tmp, struct cfi_ep, lh);
+-01090                         retval = cfi_reset_sg_val(cfiep);
+-01091                         if (retval < 0) {
+-01092                                 CFI_INFO
+-01093                                     ("%s: Error resetting the feature Buffer Setup\n",
+-01094                                      __func__);
+-01095                                 return retval;
+-01096                         }
+-01097                 }
+-01098         }
+-01099         return retval;
+-01100 }
+-01101 
+-01102 static int cfi_handle_reset_concat_val(struct dwc_otg_pcd *pcd, uint8_t addr)
+-01103 {
+-01104         int retval = 0;
+-01105         cfi_ep_t *cfiep;
+-01106         cfiobject_t *cfi = pcd->cfi;
+-01107         dwc_list_link_t *tmp;
+-01108 
+-01109         /* If the EP address is known then reset the features for only that EP */
+-01110         if (addr) {
+-01111                 cfiep = get_cfi_ep_by_addr(pcd->cfi, addr);
+-01112                 if (NULL == cfiep) {
+-01113                         CFI_INFO("%s: Error getting the EP address 0x%02x\n",
+-01114                                  __func__, addr);
+-01115                         return -DWC_E_INVALID;
+-01116                 }
+-01117                 retval = cfi_reset_concat_val(cfiep);
+-01118         }
+-01119         /* Otherwise (wValue == 0), reset all features of all EP's */
+-01120         else {
+-01121                 /* Traverse all the active EP's and reset the feature(s) value(s) */
+-01122                 //list_for_each_entry(cfiep, &cfi->active_eps, lh) {
+-01123                 DWC_LIST_FOREACH(tmp, &cfi->active_eps) {
+-01124                         cfiep = DWC_LIST_ENTRY(tmp, struct cfi_ep, lh);
+-01125                         retval = cfi_reset_concat_val(cfiep);
+-01126                         if (retval < 0) {
+-01127                                 CFI_INFO
+-01128                                     ("%s: Error resetting the feature Concatenation Value\n",
+-01129                                      __func__);
+-01130                                 return retval;
+-01131                         }
+-01132                 }
+-01133         }
+-01134         return retval;
+-01135 }
+-01136 
+-01137 static int cfi_handle_reset_align_val(struct dwc_otg_pcd *pcd, uint8_t addr)
+-01138 {
+-01139         int retval = 0;
+-01140         cfi_ep_t *cfiep;
+-01141         cfiobject_t *cfi = pcd->cfi;
+-01142         dwc_list_link_t *tmp;
+-01143 
+-01144         /* If the EP address is known then reset the features for only that EP */
+-01145         if (addr) {
+-01146                 cfiep = get_cfi_ep_by_addr(pcd->cfi, addr);
+-01147                 if (NULL == cfiep) {
+-01148                         CFI_INFO("%s: Error getting the EP address 0x%02x\n",
+-01149                                  __func__, addr);
+-01150                         return -DWC_E_INVALID;
+-01151                 }
+-01152                 retval = cfi_reset_align_val(cfiep);
+-01153         }
+-01154         /* Otherwise (wValue == 0), reset all features of all EP's */
+-01155         else {
+-01156                 /* Traverse all the active EP's and reset the feature(s) value(s) */
+-01157                 //list_for_each_entry(cfiep, &cfi->active_eps, lh) {
+-01158                 DWC_LIST_FOREACH(tmp, &cfi->active_eps) {
+-01159                         cfiep = DWC_LIST_ENTRY(tmp, struct cfi_ep, lh);
+-01160                         retval = cfi_reset_align_val(cfiep);
+-01161                         if (retval < 0) {
+-01162                                 CFI_INFO
+-01163                                     ("%s: Error resetting the feature Aliignment Value\n",
+-01164                                      __func__);
+-01165                                 return retval;
+-01166                         }
+-01167                 }
+-01168         }
+-01169         return retval;
+-01170 
+-01171 }
+-01172 
+-01173 static int cfi_preproc_reset(struct dwc_otg_pcd *pcd,
+-01174                              struct cfi_usb_ctrlrequest *req)
+-01175 {
+-01176         int retval = 0;
+-01177 
+-01178         switch (req->wIndex) {
+-01179         case 0:
+-01180                 /* Reset all features */
+-01181                 retval = cfi_handle_reset_all(pcd, req->wValue & 0xff);
+-01182                 break;
+-01183 
+-01184         case FT_ID_DMA_BUFFER_SETUP:
+-01185                 /* Reset the SG buffer setup */
+-01186                 retval =
+-01187                     cfi_handle_reset_dma_buff_setup(pcd, req->wValue & 0xff);
+-01188                 break;
+-01189 
+-01190         case FT_ID_DMA_CONCAT_SETUP:
+-01191                 /* Reset the Concatenation buffer setup */
+-01192                 retval = cfi_handle_reset_concat_val(pcd, req->wValue & 0xff);
+-01193                 break;
+-01194 
+-01195         case FT_ID_DMA_BUFF_ALIGN:
+-01196                 /* Reset the Alignment buffer setup */
+-01197                 retval = cfi_handle_reset_align_val(pcd, req->wValue & 0xff);
+-01198                 break;
+-01199 
+-01200         case FT_ID_TX_FIFO_DEPTH:
+-01201                 retval =
+-01202                     cfi_handle_reset_fifo_val(pcd, req->wValue & 0xff, 0, 1);
+-01203                 pcd->cfi->need_gadget_att = 0;
+-01204                 break;
+-01205 
+-01206         case FT_ID_RX_FIFO_DEPTH:
+-01207                 retval = cfi_handle_reset_fifo_val(pcd, 0, 1, 0);
+-01208                 pcd->cfi->need_gadget_att = 0;
+-01209                 break;
+-01210         default:
+-01211                 break;
+-01212         }
+-01213         return retval;
+-01214 }
+-01215 
+-01219 static int cfi_ep_set_sg_val(uint8_t * buf, struct dwc_otg_pcd *pcd)
+-01220 {
+-01221         uint8_t inaddr, outaddr;
+-01222         cfi_ep_t *epin, *epout;
+-01223         ddma_sg_buffer_setup_t *psgval;
+-01224         uint32_t desccount, size;
+-01225 
+-01226         CFI_INFO("%s\n", __func__);
+-01227 
+-01228         psgval = (ddma_sg_buffer_setup_t *) buf;
+-01229         desccount = (uint32_t) psgval->bCount;
+-01230         size = (uint32_t) psgval->wSize;
+-01231 
+-01232         /* Check the DMA descriptor count */
+-01233         if ((desccount > MAX_DMA_DESCS_PER_EP) || (desccount == 0)) {
+-01234                 CFI_INFO
+-01235                     ("%s: The count of DMA Descriptors should be between 1 and %d\n",
+-01236                      __func__, MAX_DMA_DESCS_PER_EP);
+-01237                 return -DWC_E_INVALID;
+-01238         }
+-01239 
+-01240         /* Check the DMA descriptor count */
+-01241 
+-01242         if (size == 0) {
+-01243 
+-01244                 CFI_INFO("%s: The transfer size should be at least 1 byte\n",
+-01245                          __func__);
+-01246 
+-01247                 return -DWC_E_INVALID;
+-01248 
+-01249         }
+-01250 
+-01251         inaddr = psgval->bInEndpointAddress;
+-01252         outaddr = psgval->bOutEndpointAddress;
+-01253 
+-01254         epin = get_cfi_ep_by_addr(pcd->cfi, inaddr);
+-01255         epout = get_cfi_ep_by_addr(pcd->cfi, outaddr);
+-01256 
+-01257         if (NULL == epin || NULL == epout) {
+-01258                 CFI_INFO
+-01259                     ("%s: Unable to get the endpoints inaddr=0x%02x outaddr=0x%02x\n",
+-01260                      __func__, inaddr, outaddr);
+-01261                 return -DWC_E_INVALID;
+-01262         }
+-01263 
+-01264         epin->ep->dwc_ep.buff_mode = BM_SG;
+-01265         dwc_memcpy(epin->bm_sg, psgval, sizeof(ddma_sg_buffer_setup_t));
+-01266 
+-01267         epout->ep->dwc_ep.buff_mode = BM_SG;
+-01268         dwc_memcpy(epout->bm_sg, psgval, sizeof(ddma_sg_buffer_setup_t));
+-01269 
+-01270         return 0;
+-01271 }
+-01272 
+-01276 static int cfi_ep_set_alignment_val(uint8_t * buf, struct dwc_otg_pcd *pcd)
+-01277 {
+-01278         cfi_ep_t *ep;
+-01279         uint8_t addr;
+-01280         ddma_align_buffer_setup_t *palignval;
+-01281 
+-01282         palignval = (ddma_align_buffer_setup_t *) buf;
+-01283         addr = palignval->bEndpointAddress;
+-01284 
+-01285         ep = get_cfi_ep_by_addr(pcd->cfi, addr);
+-01286 
+-01287         if (NULL == ep) {
+-01288                 CFI_INFO("%s: Unable to get the endpoint addr=0x%02x\n",
+-01289                          __func__, addr);
+-01290                 return -DWC_E_INVALID;
+-01291         }
+-01292 
+-01293         ep->ep->dwc_ep.buff_mode = BM_ALIGN;
+-01294         dwc_memcpy(ep->bm_align, palignval, sizeof(ddma_align_buffer_setup_t));
+-01295 
+-01296         return 0;
+-01297 }
+-01298 
+-01302 static int cfi_ep_set_concat_val(uint8_t * buf, struct dwc_otg_pcd *pcd)
+-01303 {
+-01304         uint8_t addr;
+-01305         cfi_ep_t *ep;
+-01306         struct _ddma_concat_buffer_setup_hdr *pConcatValHdr;
+-01307         uint16_t *pVals;
+-01308         uint32_t desccount;
+-01309         int i;
+-01310         uint16_t mps;
+-01311 
+-01312         pConcatValHdr = (struct _ddma_concat_buffer_setup_hdr *)buf;
+-01313         desccount = (uint32_t) pConcatValHdr->bDescCount;
+-01314         pVals = (uint16_t *) (buf + BS_CONCAT_VAL_HDR_LEN);
+-01315 
+-01316         /* Check the DMA descriptor count */
+-01317         if (desccount > MAX_DMA_DESCS_PER_EP) {
+-01318                 CFI_INFO("%s: Maximum DMA Descriptor count should be %d\n",
+-01319                          __func__, MAX_DMA_DESCS_PER_EP);
+-01320                 return -DWC_E_INVALID;
+-01321         }
+-01322 
+-01323         addr = pConcatValHdr->bEndpointAddress;
+-01324         ep = get_cfi_ep_by_addr(pcd->cfi, addr);
+-01325         if (NULL == ep) {
+-01326                 CFI_INFO("%s: Unable to get the endpoint addr=0x%02x\n",
+-01327                          __func__, addr);
+-01328                 return -DWC_E_INVALID;
+-01329         }
+-01330 
+-01331         mps = UGETW(ep->ep->desc->wMaxPacketSize);
+-01332 
+-01333 #if 0
+-01334         for (i = 0; i < desccount; i++) {
+-01335                 CFI_INFO("%s: wTxSize[%d]=0x%04x\n", __func__, i, pVals[i]);
+-01336         }
+-01337         CFI_INFO("%s: epname=%s; mps=%d\n", __func__, ep->ep->ep.name, mps);
+-01338 #endif
+-01339 
+-01340         /* Check the wTxSizes to be less than or equal to the mps */
+-01341         for (i = 0; i < desccount; i++) {
+-01342                 if (pVals[i] > mps) {
+-01343                         CFI_INFO
+-01344                             ("%s: ERROR - the wTxSize[%d] should be <= MPS (wTxSize=%d)\n",
+-01345                              __func__, i, pVals[i]);
+-01346                         return -DWC_E_INVALID;
+-01347                 }
+-01348         }
+-01349 
+-01350         ep->ep->dwc_ep.buff_mode = BM_CONCAT;
+-01351         dwc_memcpy(ep->bm_concat, pConcatValHdr, BS_CONCAT_VAL_HDR_LEN);
+-01352 
+-01353         /* Free the previously allocated storage for the wTxBytes */
+-01354         if (ep->bm_concat->wTxBytes) {
+-01355                 DWC_FREE(ep->bm_concat->wTxBytes);
+-01356         }
+-01357 
+-01358         /* Allocate a new storage for the wTxBytes field */
+-01359         ep->bm_concat->wTxBytes =
+-01360             DWC_ALLOC(sizeof(uint16_t) * pConcatValHdr->bDescCount);
+-01361         if (NULL == ep->bm_concat->wTxBytes) {
+-01362                 CFI_INFO("%s: Unable to allocate memory\n", __func__);
+-01363                 return -DWC_E_NO_MEMORY;
+-01364         }
+-01365 
+-01366         /* Copy the new values into the wTxBytes filed */
+-01367         dwc_memcpy(ep->bm_concat->wTxBytes, buf + BS_CONCAT_VAL_HDR_LEN,
+-01368                    sizeof(uint16_t) * pConcatValHdr->bDescCount);
+-01369 
+-01370         return 0;
+-01371 }
+-01372 
+-01381 static uint16_t get_dfifo_size(dwc_otg_core_if_t * core_if)
+-01382 {
+-01383         dwc_otg_core_params_t *params = core_if->core_params;
+-01384         uint16_t dfifo_total = 0;
+-01385         int i;
+-01386 
+-01387         /* The shared RxFIFO size */
+-01388         dfifo_total =
+-01389             params->dev_rx_fifo_size + params->dev_nperio_tx_fifo_size;
+-01390 
+-01391         /* Add up each TxFIFO size to the total */
+-01392         for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {
+-01393                 dfifo_total += params->dev_tx_fifo_size[i];
+-01394         }
+-01395 
+-01396         return dfifo_total;
+-01397 }
+-01398 
+-01407 static int32_t get_rxfifo_size(dwc_otg_core_if_t * core_if, uint16_t wValue)
+-01408 {
+-01409         switch (wValue >> 8) {
+-01410         case 0:
+-01411                 return (core_if->pwron_rxfsiz <
+-01412                         32768) ? core_if->pwron_rxfsiz : 32768;
+-01413                 break;
+-01414         case 1:
+-01415                 return core_if->core_params->dev_rx_fifo_size;
+-01416                 break;
+-01417         default:
+-01418                 return -DWC_E_INVALID;
+-01419                 break;
+-01420         }
+-01421 }
+-01422 
+-01431 static int32_t get_txfifo_size(struct dwc_otg_pcd *pcd, uint16_t wValue)
+-01432 {
+-01433         dwc_otg_pcd_ep_t *ep;
+-01434 
+-01435         ep = get_ep_by_addr(pcd, wValue & 0xff);
+-01436 
+-01437         if (NULL == ep) {
+-01438                 CFI_INFO("%s: Unable to get the endpoint addr=0x%02x\n",
+-01439                          __func__, wValue & 0xff);
+-01440                 return -DWC_E_INVALID;
+-01441         }
+-01442 
+-01443         if (!ep->dwc_ep.is_in) {
+-01444                 CFI_INFO
+-01445                     ("%s: No Tx FIFO assingned to the Out endpoint addr=0x%02x\n",
+-01446                      __func__, wValue & 0xff);
+-01447                 return -DWC_E_INVALID;
+-01448         }
+-01449 
+-01450         switch (wValue >> 8) {
+-01451         case 0:
+-01452                 return (GET_CORE_IF(pcd)->pwron_txfsiz
+-01453                         [ep->dwc_ep.tx_fifo_num - 1] <
+-01454                         768) ? GET_CORE_IF(pcd)->pwron_txfsiz[ep->
+-01455                                                               dwc_ep.tx_fifo_num
+-01456                                                               - 1] : 32768;
+-01457                 break;
+-01458         case 1:
+-01459                 return GET_CORE_IF(pcd)->core_params->
+-01460                     dev_tx_fifo_size[ep->dwc_ep.num - 1];
+-01461                 break;
+-01462         default:
+-01463                 return -DWC_E_INVALID;
+-01464                 break;
+-01465         }
+-01466 }
+-01467 
+-01477 static uint8_t check_fifo_sizes(dwc_otg_core_if_t * core_if)
+-01478 {
+-01479         uint16_t dfifo_actual = 0;
+-01480         dwc_otg_core_params_t *params = core_if->core_params;
+-01481         uint16_t start_addr = 0;
+-01482         int i;
+-01483 
+-01484         dfifo_actual =
+-01485             params->dev_rx_fifo_size + params->dev_nperio_tx_fifo_size;
+-01486 
+-01487         for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {
+-01488                 dfifo_actual += params->dev_tx_fifo_size[i];
+-01489         }
+-01490 
+-01491         if (dfifo_actual > core_if->total_fifo_size) {
+-01492                 return 0;
+-01493         }
+-01494 
+-01495         if (params->dev_rx_fifo_size > 32768 || params->dev_rx_fifo_size < 16)
+-01496                 return 0;
+-01497 
+-01498         if (params->dev_nperio_tx_fifo_size > 32768
+-01499             || params->dev_nperio_tx_fifo_size < 16)
+-01500                 return 0;
+-01501 
+-01502         for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {
+-01503 
+-01504                 if (params->dev_tx_fifo_size[i] > 768
+-01505                     || params->dev_tx_fifo_size[i] < 4)
+-01506                         return 0;
+-01507         }
+-01508 
+-01509         if (params->dev_rx_fifo_size > core_if->pwron_rxfsiz)
+-01510                 return 0;
+-01511         start_addr = params->dev_rx_fifo_size;
+-01512 
+-01513         if (params->dev_nperio_tx_fifo_size > core_if->pwron_gnptxfsiz)
+-01514                 return 0;
+-01515         start_addr += params->dev_nperio_tx_fifo_size;
+-01516 
+-01517         for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {
+-01518 
+-01519                 if (params->dev_tx_fifo_size[i] > core_if->pwron_txfsiz[i])
+-01520                         return 0;
+-01521                 start_addr += params->dev_tx_fifo_size[i];
+-01522         }
+-01523 
+-01524         return 1;
+-01525 }
+-01526 
+-01535 static uint8_t resize_fifos(dwc_otg_core_if_t * core_if)
+-01536 {
+-01537         int i = 0;
+-01538         dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
+-01539         dwc_otg_core_params_t *params = core_if->core_params;
+-01540         uint32_t rx_fifo_size;
+-01541         fifosize_data_t nptxfifosize;
+-01542         fifosize_data_t txfifosize[15];
+-01543 
+-01544         uint32_t rx_fsz_bak;
+-01545         uint32_t nptxfsz_bak;
+-01546         uint32_t txfsz_bak[15];
+-01547 
+-01548         uint16_t start_address;
+-01549         uint8_t retval = 1;
+-01550 
+-01551         if (!check_fifo_sizes(core_if)) {
+-01552                 return 0;
+-01553         }
+-01554 
+-01555         /* Configure data FIFO sizes */
+-01556         if (core_if->hwcfg2.b.dynamic_fifo && params->enable_dynamic_fifo) {
+-01557                 rx_fsz_bak = DWC_READ_REG32(&global_regs->grxfsiz);
+-01558                 rx_fifo_size = params->dev_rx_fifo_size;
+-01559                 DWC_WRITE_REG32(&global_regs->grxfsiz, rx_fifo_size);
+-01560 
+-01561                 /*
+-01562                  * Tx FIFOs These FIFOs are numbered from 1 to 15.
+-01563                  * Indexes of the FIFO size module parameters in the
+-01564                  * dev_tx_fifo_size array and the FIFO size registers in
+-01565                  * the dtxfsiz array run from 0 to 14.
+-01566                  */
+-01567 
+-01568                 /* Non-periodic Tx FIFO */
+-01569                 nptxfsz_bak = DWC_READ_REG32(&global_regs->gnptxfsiz);
+-01570                 nptxfifosize.b.depth = params->dev_nperio_tx_fifo_size;
+-01571                 start_address = params->dev_rx_fifo_size;
+-01572                 nptxfifosize.b.startaddr = start_address;
+-01573 
+-01574                 DWC_WRITE_REG32(&global_regs->gnptxfsiz, nptxfifosize.d32);
+-01575 
+-01576                 start_address += nptxfifosize.b.depth;
+-01577 
+-01578                 for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {
+-01579                         txfsz_bak[i] = DWC_READ_REG32(&global_regs->dtxfsiz[i]);
+-01580 
+-01581                         txfifosize[i].b.depth = params->dev_tx_fifo_size[i];
+-01582                         txfifosize[i].b.startaddr = start_address;
+-01583                         DWC_WRITE_REG32(&global_regs->dtxfsiz[i],
+-01584                                         txfifosize[i].d32);
+-01585 
+-01586                         start_address += txfifosize[i].b.depth;
+-01587                 }
+-01588 
+-01590                 if (rx_fifo_size != DWC_READ_REG32(&global_regs->grxfsiz)) {
+-01591                         retval = 0;
+-01592                 }
+-01593 
+-01594                 if (nptxfifosize.d32 != DWC_READ_REG32(&global_regs->gnptxfsiz)) {
+-01595                         retval = 0;
+-01596                 }
+-01597 
+-01598                 for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {
+-01599                         if (txfifosize[i].d32 !=
+-01600                             DWC_READ_REG32(&global_regs->dtxfsiz[i])) {
+-01601                                 retval = 0;
+-01602                         }
+-01603                 }
+-01604 
+-01606                 if (retval == 0) {
+-01607                         DWC_WRITE_REG32(&global_regs->grxfsiz, rx_fsz_bak);
+-01608 
+-01609                         /* Non-periodic Tx FIFO */
+-01610                         DWC_WRITE_REG32(&global_regs->gnptxfsiz, nptxfsz_bak);
+-01611 
+-01612                         for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {
+-01613                                 DWC_WRITE_REG32(&global_regs->dtxfsiz[i],
+-01614                                                 txfsz_bak[i]);
+-01615                         }
+-01616                 }
+-01617         } else {
+-01618                 return 0;
+-01619         }
+-01620 
+-01621         /* Flush the FIFOs */
+-01622         dwc_otg_flush_tx_fifo(core_if, 0x10);   /* all Tx FIFOs */
+-01623         dwc_otg_flush_rx_fifo(core_if);
+-01624 
+-01625         return retval;
+-01626 }
+-01627 
+-01631 static int cfi_ep_set_tx_fifo_val(uint8_t * buf, dwc_otg_pcd_t * pcd)
+-01632 {
+-01633         int retval;
+-01634         uint32_t fsiz;
+-01635         uint16_t size;
+-01636         uint16_t ep_addr;
+-01637         dwc_otg_pcd_ep_t *ep;
+-01638         dwc_otg_core_params_t *params = GET_CORE_IF(pcd)->core_params;
+-01639         tx_fifo_size_setup_t *ptxfifoval;
+-01640 
+-01641         ptxfifoval = (tx_fifo_size_setup_t *) buf;
+-01642         ep_addr = ptxfifoval->bEndpointAddress;
+-01643         size = ptxfifoval->wDepth;
+-01644 
+-01645         ep = get_ep_by_addr(pcd, ep_addr);
+-01646 
+-01647         CFI_INFO
+-01648             ("%s: Set Tx FIFO size: endpoint addr=0x%02x, depth=%d, FIFO Num=%d\n",
+-01649              __func__, ep_addr, size, ep->dwc_ep.tx_fifo_num);
+-01650 
+-01651         if (NULL == ep) {
+-01652                 CFI_INFO("%s: Unable to get the endpoint addr=0x%02x\n",
+-01653                          __func__, ep_addr);
+-01654                 return -DWC_E_INVALID;
+-01655         }
+-01656 
+-01657         fsiz = params->dev_tx_fifo_size[ep->dwc_ep.tx_fifo_num - 1];
+-01658         params->dev_tx_fifo_size[ep->dwc_ep.tx_fifo_num - 1] = size;
+-01659 
+-01660         if (resize_fifos(GET_CORE_IF(pcd))) {
+-01661                 retval = 0;
+-01662         } else {
+-01663                 CFI_INFO
+-01664                     ("%s: Error setting the feature Tx FIFO Size for EP%d\n",
+-01665                      __func__, ep_addr);
+-01666                 params->dev_tx_fifo_size[ep->dwc_ep.tx_fifo_num - 1] = fsiz;
+-01667                 retval = -DWC_E_INVALID;
+-01668         }
+-01669 
+-01670         return retval;
+-01671 }
+-01672 
+-01676 static int cfi_set_rx_fifo_val(uint8_t * buf, dwc_otg_pcd_t * pcd)
+-01677 {
+-01678         int retval;
+-01679         uint32_t fsiz;
+-01680         uint16_t size;
+-01681         dwc_otg_core_params_t *params = GET_CORE_IF(pcd)->core_params;
+-01682         rx_fifo_size_setup_t *prxfifoval;
+-01683 
+-01684         prxfifoval = (rx_fifo_size_setup_t *) buf;
+-01685         size = prxfifoval->wDepth;
+-01686 
+-01687         fsiz = params->dev_rx_fifo_size;
+-01688         params->dev_rx_fifo_size = size;
+-01689 
+-01690         if (resize_fifos(GET_CORE_IF(pcd))) {
+-01691                 retval = 0;
+-01692         } else {
+-01693                 CFI_INFO("%s: Error setting the feature Rx FIFO Size\n",
+-01694                          __func__);
+-01695                 params->dev_rx_fifo_size = fsiz;
+-01696                 retval = -DWC_E_INVALID;
+-01697         }
+-01698 
+-01699         return retval;
+-01700 }
+-01701 
+-01705 static int cfi_ep_get_sg_val(uint8_t * buf, struct dwc_otg_pcd *pcd,
+-01706                              struct cfi_usb_ctrlrequest *req)
+-01707 {
+-01708         int retval = -DWC_E_INVALID;
+-01709         uint8_t addr;
+-01710         cfi_ep_t *ep;
+-01711 
+-01712         /* The Low Byte of the wValue contains a non-zero address of the endpoint */
+-01713         addr = req->wValue & 0xFF;
+-01714         if (addr == 0)          /* The address should be non-zero */
+-01715                 return retval;
+-01716 
+-01717         ep = get_cfi_ep_by_addr(pcd->cfi, addr);
+-01718         if (NULL == ep) {
+-01719                 CFI_INFO("%s: Unable to get the endpoint address(0x%02x)\n",
+-01720                          __func__, addr);
+-01721                 return retval;
+-01722         }
+-01723 
+-01724         dwc_memcpy(buf, ep->bm_sg, BS_SG_VAL_DESC_LEN);
+-01725         retval = BS_SG_VAL_DESC_LEN;
+-01726         return retval;
+-01727 }
+-01728 
+-01733 static int cfi_ep_get_concat_val(uint8_t * buf, struct dwc_otg_pcd *pcd,
+-01734                                  struct cfi_usb_ctrlrequest *req)
+-01735 {
+-01736         int retval = -DWC_E_INVALID;
+-01737         uint8_t addr;
+-01738         cfi_ep_t *ep;
+-01739         uint8_t desc_count;
+-01740 
+-01741         /* The Low Byte of the wValue contains a non-zero address of the endpoint */
+-01742         addr = req->wValue & 0xFF;
+-01743         if (addr == 0)          /* The address should be non-zero */
+-01744                 return retval;
+-01745 
+-01746         ep = get_cfi_ep_by_addr(pcd->cfi, addr);
+-01747         if (NULL == ep) {
+-01748                 CFI_INFO("%s: Unable to get the endpoint address(0x%02x)\n",
+-01749                          __func__, addr);
+-01750                 return retval;
+-01751         }
+-01752 
+-01753         /* Copy the header to the buffer */
+-01754         dwc_memcpy(buf, ep->bm_concat, BS_CONCAT_VAL_HDR_LEN);
+-01755         /* Advance the buffer pointer by the header size */
+-01756         buf += BS_CONCAT_VAL_HDR_LEN;
+-01757 
+-01758         desc_count = ep->bm_concat->hdr.bDescCount;
+-01759         /* Copy alll the wTxBytes to the buffer */
+-01760         dwc_memcpy(buf, ep->bm_concat->wTxBytes, sizeof(uid16_t) * desc_count);
+-01761 
+-01762         retval = BS_CONCAT_VAL_HDR_LEN + sizeof(uid16_t) * desc_count;
+-01763         return retval;
+-01764 }
+-01765 
+-01772 static int cfi_ep_get_align_val(uint8_t * buf, struct dwc_otg_pcd *pcd,
+-01773                                 struct cfi_usb_ctrlrequest *req)
+-01774 {
+-01775         int retval = -DWC_E_INVALID;
+-01776         uint8_t addr;
+-01777         cfi_ep_t *ep;
+-01778 
+-01779         /* The Low Byte of the wValue contains a non-zero address of the endpoint */
+-01780         addr = req->wValue & 0xFF;
+-01781         if (addr == 0)          /* The address should be non-zero */
+-01782                 return retval;
+-01783 
+-01784         ep = get_cfi_ep_by_addr(pcd->cfi, addr);
+-01785         if (NULL == ep) {
+-01786                 CFI_INFO("%s: Unable to get the endpoint address(0x%02x)\n",
+-01787                          __func__, addr);
+-01788                 return retval;
+-01789         }
+-01790 
+-01791         dwc_memcpy(buf, ep->bm_align, BS_ALIGN_VAL_HDR_LEN);
+-01792         retval = BS_ALIGN_VAL_HDR_LEN;
+-01793 
+-01794         return retval;
+-01795 }
+-01796 
+-01804 static int cfi_set_feature_value(struct dwc_otg_pcd *pcd)
+-01805 {
+-01806         int retval = -DWC_E_NOT_SUPPORTED;
+-01807         uint16_t wIndex, wValue;
+-01808         uint8_t bRequest;
+-01809         struct dwc_otg_core_if *coreif;
+-01810         cfiobject_t *cfi = pcd->cfi;
+-01811         struct cfi_usb_ctrlrequest *ctrl_req;
+-01812         uint8_t *buf;
+-01813         ctrl_req = &cfi->ctrl_req;
+-01814 
+-01815         buf = pcd->cfi->ctrl_req.data;
+-01816 
+-01817         coreif = GET_CORE_IF(pcd);
+-01818         bRequest = ctrl_req->bRequest;
+-01819         wIndex = DWC_CONSTANT_CPU_TO_LE16(ctrl_req->wIndex);
+-01820         wValue = DWC_CONSTANT_CPU_TO_LE16(ctrl_req->wValue);
+-01821 
+-01822         /* See which feature is to be modified */
+-01823         switch (wIndex) {
+-01824         case FT_ID_DMA_BUFFER_SETUP:
+-01825                 /* Modify the feature */
+-01826                 if ((retval = cfi_ep_set_sg_val(buf, pcd)) < 0)
+-01827                         return retval;
+-01828 
+-01829                 /* And send this request to the gadget */
+-01830                 cfi->need_gadget_att = 1;
+-01831                 break;
+-01832 
+-01833         case FT_ID_DMA_BUFF_ALIGN:
+-01834                 if ((retval = cfi_ep_set_alignment_val(buf, pcd)) < 0)
+-01835                         return retval;
+-01836                 cfi->need_gadget_att = 1;
+-01837                 break;
+-01838 
+-01839         case FT_ID_DMA_CONCAT_SETUP:
+-01840                 /* Modify the feature */
+-01841                 if ((retval = cfi_ep_set_concat_val(buf, pcd)) < 0)
+-01842                         return retval;
+-01843                 cfi->need_gadget_att = 1;
+-01844                 break;
+-01845 
+-01846         case FT_ID_DMA_CIRCULAR:
+-01847                 CFI_INFO("FT_ID_DMA_CIRCULAR\n");
+-01848                 break;
+-01849 
+-01850         case FT_ID_THRESHOLD_SETUP:
+-01851                 CFI_INFO("FT_ID_THRESHOLD_SETUP\n");
+-01852                 break;
+-01853 
+-01854         case FT_ID_DFIFO_DEPTH:
+-01855                 CFI_INFO("FT_ID_DFIFO_DEPTH\n");
+-01856                 break;
+-01857 
+-01858         case FT_ID_TX_FIFO_DEPTH:
+-01859                 CFI_INFO("FT_ID_TX_FIFO_DEPTH\n");
+-01860                 if ((retval = cfi_ep_set_tx_fifo_val(buf, pcd)) < 0)
+-01861                         return retval;
+-01862                 cfi->need_gadget_att = 0;
+-01863                 break;
+-01864 
+-01865         case FT_ID_RX_FIFO_DEPTH:
+-01866                 CFI_INFO("FT_ID_RX_FIFO_DEPTH\n");
+-01867                 if ((retval = cfi_set_rx_fifo_val(buf, pcd)) < 0)
+-01868                         return retval;
+-01869                 cfi->need_gadget_att = 0;
+-01870                 break;
+-01871         }
+-01872 
+-01873         return retval;
+-01874 }
+-01875 
+-01876 #endif //DWC_UTE_CFI
+-
                                                                                Generated on Thu Oct 27 03:56:37 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__cfi_8c.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/dwc__otg__cfi_8c.html 2013-07-26 19:34:39.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,24 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_cfi.c File Reference +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                dwc_otg_cfi.c File Reference

                                                                                This file contains the most of the CFI(Core Feature Interface) implementation for the OTG. More... +-

                                                                                +- +-

                                                                                +-Go to the source code of this file. +- +-
                                                                                +-

                                                                                Detailed Description

                                                                                +-This file contains the most of the CFI(Core Feature Interface) implementation for the OTG. +-

                                                                                +- +-

                                                                                +-Definition in file dwc_otg_cfi.c.

                                                                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__cfi_8h-source.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/dwc__otg__cfi_8h-source.html 2013-07-26 19:34:39.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,287 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_cfi.h Source File +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                dwc_otg_cfi.h

                                                                                Go to the documentation of this file.
                                                                                00001 /* ==========================================================================
+-00002  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
+-00003  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
+-00004  * otherwise expressly agreed to in writing between Synopsys and you.
+-00005  *
+-00006  * The Software IS NOT an item of Licensed Software or Licensed Product under
+-00007  * any End User Software License Agreement or Agreement for Licensed Product
+-00008  * with Synopsys or any supplement thereto. You are permitted to use and
+-00009  * redistribute this Software in source and binary forms, with or without
+-00010  * modification, provided that redistributions of source code must retain this
+-00011  * notice. You may not view, use, disclose, copy or distribute this file or
+-00012  * any information contained herein except pursuant to this license grant from
+-00013  * Synopsys. If you do not agree with this notice, including the disclaimer
+-00014  * below, then you are not authorized to use the Software.
+-00015  *
+-00016  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
+-00017  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+-00018  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+-00019  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
+-00020  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+-00021  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+-00022  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+-00023  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+-00024  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+-00025  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+-00026  * DAMAGE.
+-00027  * ========================================================================== */
+-00028 
+-00029 #if !defined(__DWC_OTG_CFI_H__)
+-00030 #define __DWC_OTG_CFI_H__
+-00031 
+-00032 #include "dwc_otg_pcd.h"
+-00033 #include "dwc_cfi_common.h"
+-00034 
+-00044 struct dwc_otg_pcd;
+-00045 struct dwc_otg_pcd_ep;
+-00046 
+-00049 #define FT_ID_DMA_MODE                                  0x0001
+-00050 #define FT_ID_DMA_BUFFER_SETUP                  0x0002
+-00051 #define FT_ID_DMA_BUFF_ALIGN                    0x0003
+-00052 #define FT_ID_DMA_CONCAT_SETUP                  0x0004
+-00053 #define FT_ID_DMA_CIRCULAR                              0x0005
+-00054 #define FT_ID_THRESHOLD_SETUP                   0x0006
+-00055 #define FT_ID_DFIFO_DEPTH                               0x0007
+-00056 #define FT_ID_TX_FIFO_DEPTH                             0x0008
+-00057 #define FT_ID_RX_FIFO_DEPTH                             0x0009
+-00058 
+-00059 /**********************************************************/
+-00060 #define CFI_INFO_DEF
+-00061 
+-00062 #ifdef CFI_INFO_DEF
+-00063 #define CFI_INFO(fmt...)        DWC_PRINTF("CFI: " fmt);
+-00064 #else
+-00065 #define CFI_INFO(fmt...)
+-00066 #endif
+-00067 
+-00068 #define min(x,y) ({ \
+-00069         x < y ? x : y; })
+-00070 
+-00071 #define max(x,y) ({ \
+-00072         x > y ? x : y; })
+-00073 
+-00078 struct _ddma_sg_buffer_setup {
+-00079 #define BS_SG_VAL_DESC_LEN      6
+-00080         /* The OUT EP address */
+-00081         uint8_t bOutEndpointAddress;
+-00082         /* The IN EP address */
+-00083         uint8_t bInEndpointAddress;
+-00084         /* Number of bytes to put between transfer segments (must be DWORD boundaries) */
+-00085         uint8_t bOffset;
+-00086         /* The number of transfer segments (a DMA descriptors per each segment) */
+-00087         uint8_t bCount;
+-00088         /* Size (in byte) of each transfer segment */
+-00089         uint16_t wSize;
+-00090 } __attribute__ ((packed));
+-00091 typedef struct _ddma_sg_buffer_setup ddma_sg_buffer_setup_t;
+-00092 
+-00094 struct _ddma_concat_buffer_setup_hdr {
+-00095 #define BS_CONCAT_VAL_HDR_LEN   4
+-00096         /* The endpoint for which the buffer is to be set up */
+-00097         uint8_t bEndpointAddress;
+-00098         /* The count of descriptors to be used */
+-00099         uint8_t bDescCount;
+-00100         /* The total size of the transfer */
+-00101         uint16_t wSize;
+-00102 } __attribute__ ((packed));
+-00103 typedef struct _ddma_concat_buffer_setup_hdr ddma_concat_buffer_setup_hdr_t;
+-00104 
+-00106 struct _ddma_concat_buffer_setup {
+-00107         /* The SG header */
+-00108         ddma_concat_buffer_setup_hdr_t hdr;
+-00109 
+-00110         /* The XFER sizes pointer (allocated dynamically) */
+-00111         uint16_t *wTxBytes;
+-00112 } __attribute__ ((packed));
+-00113 typedef struct _ddma_concat_buffer_setup ddma_concat_buffer_setup_t;
+-00114 
+-00116 struct _ddma_align_buffer_setup {
+-00117 #define BS_ALIGN_VAL_HDR_LEN    2
+-00118         uint8_t bEndpointAddress;
+-00119         uint8_t bAlign;
+-00120 } __attribute__ ((packed));
+-00121 typedef struct _ddma_align_buffer_setup ddma_align_buffer_setup_t;
+-00122 
+-00124 struct _tx_fifo_size_setup {
+-00125         uint8_t bEndpointAddress;
+-00126         uint16_t wDepth;
+-00127 } __attribute__ ((packed));
+-00128 typedef struct _tx_fifo_size_setup tx_fifo_size_setup_t;
+-00129 
+-00131 struct _rx_fifo_size_setup {
+-00132         uint16_t wDepth;
+-00133 } __attribute__ ((packed));
+-00134 typedef struct _rx_fifo_size_setup rx_fifo_size_setup_t;
+-00135 
+-00141 struct cfi_usb_ctrlrequest {
+-00142         uint8_t bRequestType;
+-00143         uint8_t bRequest;
+-00144         uint16_t wValue;
+-00145         uint16_t wIndex;
+-00146         uint16_t wLength;
+-00147         uint8_t *data;
+-00148 } UPACKED;
+-00149 
+-00150 /*---------------------------------------------------------------------------*/
+-00151 
+-00157 struct cfi_ep {
+-00158         /* Entry for the list container */
+-00159         dwc_list_link_t lh;
+-00160         /* Pointer to the active PCD endpoint structure */
+-00161         struct dwc_otg_pcd_ep *ep;
+-00162         /* The last descriptor in the chain of DMA descriptors of the endpoint */
+-00163         struct dwc_otg_dma_desc *dma_desc_last;
+-00164         /* The SG feature value */
+-00165         ddma_sg_buffer_setup_t *bm_sg;
+-00166         /* The Circular feature value */
+-00167         ddma_sg_buffer_setup_t *bm_circ;
+-00168         /* The Concatenation feature value */
+-00169         ddma_concat_buffer_setup_t *bm_concat;
+-00170         /* The Alignment feature value */
+-00171         ddma_align_buffer_setup_t *bm_align;
+-00172         /* XFER length */
+-00173         uint32_t xfer_len;
+-00174         /*
+-00175          * Count of DMA descriptors currently used.
+-00176          * The total should not exceed the MAX_DMA_DESCS_PER_EP value
+-00177          * defined in the dwc_otg_cil.h
+-00178          */
+-00179         uint32_t desc_count;
+-00180 };
+-00181 typedef struct cfi_ep cfi_ep_t;
+-00182 
+-00183 typedef struct cfi_dma_buff {
+-00184 #define CFI_IN_BUF_LEN  1024
+-00185 #define CFI_OUT_BUF_LEN 1024
+-00186         dma_addr_t addr;
+-00187         uint8_t *buf;
+-00188 } cfi_dma_buff_t;
+-00189 
+-00190 struct cfiobject;
+-00191 
+-00200 typedef struct cfi_ops {
+-00201         int (*ep_enable) (struct cfiobject * cfi, struct dwc_otg_pcd * pcd,
+-00202                           struct dwc_otg_pcd_ep * ep);
+-00203         void *(*ep_alloc_buf) (struct cfiobject * cfi, struct dwc_otg_pcd * pcd,
+-00204                                struct dwc_otg_pcd_ep * ep, dma_addr_t * dma,
+-00205                                unsigned size, gfp_t flags);
+-00206         void (*release) (struct cfiobject * cfi);
+-00207         int (*ctrl_write_complete) (struct cfiobject * cfi,
+-00208                                     struct dwc_otg_pcd * pcd);
+-00209         void (*build_descriptors) (struct cfiobject * cfi,
+-00210                                    struct dwc_otg_pcd * pcd,
+-00211                                    struct dwc_otg_pcd_ep * ep,
+-00212                                    dwc_otg_pcd_request_t * req);
+-00213 } cfi_ops_t;
+-00214 
+-00215 struct cfiobject {
+-00216         cfi_ops_t ops;
+-00217         struct dwc_otg_pcd *pcd;
+-00218         struct usb_gadget *gadget;
+-00219 
+-00220         /* Buffers used to send/receive CFI-related request data */
+-00221         cfi_dma_buff_t buf_in;
+-00222         cfi_dma_buff_t buf_out;
+-00223 
+-00224         /* CFI specific Control request wrapper */
+-00225         struct cfi_usb_ctrlrequest ctrl_req;
+-00226 
+-00227         /* The list of active EP's in the PCD of type cfi_ep_t */
+-00228         dwc_list_link_t active_eps;
+-00229 
+-00230         /* This flag shall control the propagation of a specific request
+-00231          * to the gadget's processing routines.
+-00232          * 0 - no gadget handling
+-00233          * 1 - the gadget needs to know about this request (w/o completing a status
+-00234          * phase - just return a 0 to the _setup callback)
+-00235          */
+-00236         uint8_t need_gadget_att;
+-00237 
+-00238         /* Flag indicating whether the status IN phase needs to be
+-00239          * completed by the PCD
+-00240          */
+-00241         uint8_t need_status_in_complete;
+-00242 };
+-00243 typedef struct cfiobject cfiobject_t;
+-00244 
+-00245 #define DUMP_MSG
+-00246 
+-00247 #if defined(DUMP_MSG)
+-00248 static inline void dump_msg(const u8 * buf, unsigned int length)
+-00249 {
+-00250         unsigned int start, num, i;
+-00251         char line[52], *p;
+-00252 
+-00253         if (length >= 512)
+-00254                 return;
+-00255 
+-00256         start = 0;
+-00257         while (length > 0) {
+-00258                 num = min(length, 16u);
+-00259                 p = line;
+-00260                 for (i = 0; i < num; ++i) {
+-00261                         if (i == 8)
+-00262                                 *p++ = ' ';
+-00263                         DWC_SPRINTF(p, " %02x", buf[i]);
+-00264                         p += 3;
+-00265                 }
+-00266                 *p = 0;
+-00267                 DWC_DEBUG("%6x: %s\n", start, line);
+-00268                 buf += num;
+-00269                 start += num;
+-00270                 length -= num;
+-00271         }
+-00272 }
+-00273 #else
+-00274 static inline void dump_msg(const u8 * buf, unsigned int length)
+-00275 {
+-00276 }
+-00277 #endif
+-00278 
+-00282 static inline struct cfi_ep *get_cfi_ep_by_addr(struct cfiobject *cfi,
+-00283                                                 uint8_t addr)
+-00284 {
+-00285         struct cfi_ep *pcfiep;
+-00286         dwc_list_link_t *tmp;
+-00287 
+-00288         DWC_LIST_FOREACH(tmp, &cfi->active_eps) {
+-00289                 pcfiep = DWC_LIST_ENTRY(tmp, struct cfi_ep, lh);
+-00290 
+-00291                 if (pcfiep->ep->desc->bEndpointAddress == addr) {
+-00292                         return pcfiep;
+-00293                 }
+-00294         }
+-00295 
+-00296         return NULL;
+-00297 }
+-00298 
+-00303 static inline struct cfi_ep *get_cfi_ep_by_pcd_ep(struct cfiobject *cfi,
+-00304                                                   struct dwc_otg_pcd_ep *ep)
+-00305 {
+-00306         struct cfi_ep *pcfiep = NULL;
+-00307         dwc_list_link_t *tmp;
+-00308 
+-00309         DWC_LIST_FOREACH(tmp, &cfi->active_eps) {
+-00310                 pcfiep = DWC_LIST_ENTRY(tmp, struct cfi_ep, lh);
+-00311                 if (pcfiep->ep == ep) {
+-00312                         return pcfiep;
+-00313                 }
+-00314         }
+-00315         return NULL;
+-00316 }
+-00317 
+-00318 int cfi_setup(struct dwc_otg_pcd *pcd, struct cfi_usb_ctrlrequest *ctrl);
+-00319 
+-00320 #endif /* (__DWC_OTG_CFI_H__) */
+-
                                                                                Generated on Thu Oct 27 03:56:37 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__cfi_8h.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/dwc__otg__cfi_8h.html 2013-07-26 19:34:39.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,302 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_cfi.h File Reference +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                dwc_otg_cfi.h File Reference

                                                                                This file contains the CFI related OTG PCD specific common constants, interfaces(functions and macros) and data structures.The CFI Protocol is an optional interface for internal testing purposes that a DUT may implement to support testing of configurable features. More... +-

                                                                                +-#include "dwc_otg_pcd.h"
                                                                                +-#include "dwc_cfi_common.h"
                                                                                +- +-

                                                                                +-Go to the source code of this file. +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-

                                                                                Data Structures

                                                                                struct  _ddma_sg_buffer_setup
                                                                                 Descriptor DMA SG Buffer setup structure (SG buffer). More...
                                                                                struct  _ddma_concat_buffer_setup_hdr
                                                                                 Descriptor DMA Concatenation Buffer setup structure. More...
                                                                                struct  _ddma_concat_buffer_setup
                                                                                 Descriptor DMA Concatenation Buffer setup structure. More...
                                                                                struct  _ddma_align_buffer_setup
                                                                                 Descriptor DMA Alignment Buffer setup structure. More...
                                                                                struct  _tx_fifo_size_setup
                                                                                 Transmit FIFO Size setup structure. More...
                                                                                struct  _rx_fifo_size_setup
                                                                                 Transmit FIFO Size setup structure. More...
                                                                                struct  cfi_usb_ctrlrequest
                                                                                 struct cfi_usb_ctrlrequest - the CFI implementation of the struct usb_ctrlrequest This structure encapsulates the standard usb_ctrlrequest and adds a pointer to the data returned in the data stage of a 3-stage Control Write requests. More...
                                                                                struct  cfi_ep
                                                                                 The CFI wrapper of the enabled and activated dwc_otg_pcd_ep structures. More...
                                                                                struct  cfi_dma_buff
                                                                                struct  cfi_ops
                                                                                 This is the interface for the CFI operations. More...
                                                                                struct  cfiobject

                                                                                Defines

                                                                                +-#define __DWC_OTG_CFI_H__
                                                                                +-#define FT_ID_DMA_MODE   0x0001
                                                                                 This is a request for all Core Features.
                                                                                +-#define FT_ID_DMA_BUFFER_SETUP   0x0002
                                                                                +-#define FT_ID_DMA_BUFF_ALIGN   0x0003
                                                                                +-#define FT_ID_DMA_CONCAT_SETUP   0x0004
                                                                                +-#define FT_ID_DMA_CIRCULAR   0x0005
                                                                                +-#define FT_ID_THRESHOLD_SETUP   0x0006
                                                                                +-#define FT_ID_DFIFO_DEPTH   0x0007
                                                                                +-#define FT_ID_TX_FIFO_DEPTH   0x0008
                                                                                +-#define FT_ID_RX_FIFO_DEPTH   0x0009
                                                                                +-#define CFI_INFO_DEF
                                                                                +-#define CFI_INFO(fmt...)   DWC_PRINTF("CFI: " fmt);
                                                                                #define min(x, y)
                                                                                #define max(x, y)
                                                                                +-#define BS_SG_VAL_DESC_LEN   6
                                                                                +-#define BS_CONCAT_VAL_HDR_LEN   4
                                                                                +-#define BS_ALIGN_VAL_HDR_LEN   2
                                                                                +-#define CFI_IN_BUF_LEN   1024
                                                                                +-#define CFI_OUT_BUF_LEN   1024
                                                                                +-#define DUMP_MSG

                                                                                Typedefs

                                                                                +-typedef _ddma_sg_buffer_setup ddma_sg_buffer_setup_t
                                                                                +-typedef _ddma_concat_buffer_setup_hdr ddma_concat_buffer_setup_hdr_t
                                                                                +-typedef _ddma_concat_buffer_setup ddma_concat_buffer_setup_t
                                                                                +-typedef _ddma_align_buffer_setup ddma_align_buffer_setup_t
                                                                                +-typedef _tx_fifo_size_setup tx_fifo_size_setup_t
                                                                                +-typedef _rx_fifo_size_setup rx_fifo_size_setup_t
                                                                                +-typedef cfi_ep cfi_ep_t
                                                                                +-typedef cfi_dma_buff cfi_dma_buff_t
                                                                                typedef cfi_ops cfi_ops_t
                                                                                 This is the interface for the CFI operations.
                                                                                +-typedef cfiobject cfiobject_t

                                                                                Functions

                                                                                +-void dump_msg (const u8 *buf, unsigned int length)
                                                                                +-cfi_ep * get_cfi_ep_by_addr (struct cfiobject *cfi, uint8_t addr)
                                                                                 This function returns a pointer to cfi_ep_t object with the addr address.
                                                                                +-cfi_ep * get_cfi_ep_by_pcd_ep (struct cfiobject *cfi, struct dwc_otg_pcd_ep *ep)
                                                                                 This function returns a pointer to cfi_ep_t object that matches the dwc_otg_pcd_ep object.
                                                                                +-int cfi_setup (struct dwc_otg_pcd *pcd, struct cfi_usb_ctrlrequest *ctrl)

                                                                                Variables

                                                                                _ddma_sg_buffer_setup packed
                                                                                 Descriptor DMA SG Buffer setup structure (SG buffer).
                                                                                +-cfi_usb_ctrlrequest UPACKED
                                                                                 struct cfi_usb_ctrlrequest - the CFI implementation of the struct usb_ctrlrequest This structure encapsulates the standard usb_ctrlrequest and adds a pointer to the data returned in the data stage of a 3-stage Control Write requests.
                                                                                +-

                                                                                Detailed Description

                                                                                +-This file contains the CFI related OTG PCD specific common constants, interfaces(functions and macros) and data structures.The CFI Protocol is an optional interface for internal testing purposes that a DUT may implement to support testing of configurable features. +-

                                                                                +- +-

                                                                                +-Definition in file dwc_otg_cfi.h.

                                                                                Define Documentation

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                #define min ( x,
                                                                                y   ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Value:

                                                                                ({ \
+-        x < y ? x : y; })
+-
                                                                                +-

                                                                                +-Definition at line 68 of file dwc_otg_cfi.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                #define max ( x,
                                                                                y   ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Value:

                                                                                ({ \
+-        x > y ? x : y; })
+-
                                                                                +-

                                                                                +-Definition at line 71 of file dwc_otg_cfi.h.

                                                                                +-

                                                                                Typedef Documentation

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                typedef struct cfi_ops cfi_ops_t
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This is the interface for the CFI operations. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +- +-
                                                                                ep_enable Called when any endpoint is enabled and activated.
                                                                                release Called when the CFI object is released and it needs to correctly deallocate the dynamic memory
                                                                                ctrl_write_complete Called when the data stage of the request is complete
                                                                                +-
                                                                                +-
                                                                                +-

                                                                                Variable Documentation

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                struct _rx_fifo_size_setup packed
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Descriptor DMA SG Buffer setup structure (SG buffer). +-

                                                                                +-This structure is also used for setting up a buffer for Circular DDMA.

                                                                                +-

                                                                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__cil_8c-source.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/dwc__otg__cil_8c-source.html 2013-07-26 19:34:40.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,6560 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_cil.c Source File +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                dwc_otg_cil.c

                                                                                Go to the documentation of this file.
                                                                                00001 /* ==========================================================================
+-00002  * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_cil.c $
+-00003  * $Revision: #189 $
+-00004  * $Date: 2011/10/24 $
+-00005  * $Change: 1871160 $
+-00006  *
+-00007  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
+-00008  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
+-00009  * otherwise expressly agreed to in writing between Synopsys and you.
+-00010  *
+-00011  * The Software IS NOT an item of Licensed Software or Licensed Product under
+-00012  * any End User Software License Agreement or Agreement for Licensed Product
+-00013  * with Synopsys or any supplement thereto. You are permitted to use and
+-00014  * redistribute this Software in source and binary forms, with or without
+-00015  * modification, provided that redistributions of source code must retain this
+-00016  * notice. You may not view, use, disclose, copy or distribute this file or
+-00017  * any information contained herein except pursuant to this license grant from
+-00018  * Synopsys. If you do not agree with this notice, including the disclaimer
+-00019  * below, then you are not authorized to use the Software.
+-00020  *
+-00021  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
+-00022  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+-00023  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+-00024  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
+-00025  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+-00026  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+-00027  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+-00028  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+-00029  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+-00030  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+-00031  * DAMAGE.
+-00032  * ========================================================================== */
+-00033 
+-00060 #include "dwc_os.h"
+-00061 #include "dwc_otg_regs.h"
+-00062 #include "dwc_otg_cil.h"
+-00063 
+-00064 static int dwc_otg_setup_params(dwc_otg_core_if_t * core_if);
+-00065 
+-00078 dwc_otg_core_if_t *dwc_otg_cil_init(const uint32_t * reg_base_addr)
+-00079 {
+-00080         dwc_otg_core_if_t *core_if = 0;
+-00081         dwc_otg_dev_if_t *dev_if = 0;
+-00082         dwc_otg_host_if_t *host_if = 0;
+-00083         uint8_t *reg_base = (uint8_t *) reg_base_addr;
+-00084         int i = 0;
+-00085 
+-00086         DWC_DEBUGPL(DBG_CILV, "%s(%p)\n", __func__, reg_base_addr);
+-00087 
+-00088         core_if = DWC_ALLOC(sizeof(dwc_otg_core_if_t));
+-00089 
+-00090         if (core_if == NULL) {
+-00091                 DWC_DEBUGPL(DBG_CIL,
+-00092                             "Allocation of dwc_otg_core_if_t failed\n");
+-00093                 return 0;
+-00094         }
+-00095         core_if->core_global_regs = (dwc_otg_core_global_regs_t *) reg_base;
+-00096 
+-00097         /*
+-00098          * Allocate the Device Mode structures.
+-00099          */
+-00100         dev_if = DWC_ALLOC(sizeof(dwc_otg_dev_if_t));
+-00101 
+-00102         if (dev_if == NULL) {
+-00103                 DWC_DEBUGPL(DBG_CIL, "Allocation of dwc_otg_dev_if_t failed\n");
+-00104                 DWC_FREE(core_if);
+-00105                 return 0;
+-00106         }
+-00107 
+-00108         dev_if->dev_global_regs =
+-00109             (dwc_otg_device_global_regs_t *) (reg_base +
+-00110                                               DWC_DEV_GLOBAL_REG_OFFSET);
+-00111 
+-00112         for (i = 0; i < MAX_EPS_CHANNELS; i++) {
+-00113                 dev_if->in_ep_regs[i] = (dwc_otg_dev_in_ep_regs_t *)
+-00114                     (reg_base + DWC_DEV_IN_EP_REG_OFFSET +
+-00115                      (i * DWC_EP_REG_OFFSET));
+-00116 
+-00117                 dev_if->out_ep_regs[i] = (dwc_otg_dev_out_ep_regs_t *)
+-00118                     (reg_base + DWC_DEV_OUT_EP_REG_OFFSET +
+-00119                      (i * DWC_EP_REG_OFFSET));
+-00120                 DWC_DEBUGPL(DBG_CILV, "in_ep_regs[%d]->diepctl=%p\n",
+-00121                             i, &dev_if->in_ep_regs[i]->diepctl);
+-00122                 DWC_DEBUGPL(DBG_CILV, "out_ep_regs[%d]->doepctl=%p\n",
+-00123                             i, &dev_if->out_ep_regs[i]->doepctl);
+-00124         }
+-00125 
+-00126         dev_if->speed = 0;      // unknown
+-00127 
+-00128         core_if->dev_if = dev_if;
+-00129 
+-00130         /*
+-00131          * Allocate the Host Mode structures.
+-00132          */
+-00133         host_if = DWC_ALLOC(sizeof(dwc_otg_host_if_t));
+-00134 
+-00135         if (host_if == NULL) {
+-00136                 DWC_DEBUGPL(DBG_CIL,
+-00137                             "Allocation of dwc_otg_host_if_t failed\n");
+-00138                 DWC_FREE(dev_if);
+-00139                 DWC_FREE(core_if);
+-00140                 return 0;
+-00141         }
+-00142 
+-00143         host_if->host_global_regs = (dwc_otg_host_global_regs_t *)
+-00144             (reg_base + DWC_OTG_HOST_GLOBAL_REG_OFFSET);
+-00145 
+-00146         host_if->hprt0 =
+-00147             (uint32_t *) (reg_base + DWC_OTG_HOST_PORT_REGS_OFFSET);
+-00148 
+-00149         for (i = 0; i < MAX_EPS_CHANNELS; i++) {
+-00150                 host_if->hc_regs[i] = (dwc_otg_hc_regs_t *)
+-00151                     (reg_base + DWC_OTG_HOST_CHAN_REGS_OFFSET +
+-00152                      (i * DWC_OTG_CHAN_REGS_OFFSET));
+-00153                 DWC_DEBUGPL(DBG_CILV, "hc_reg[%d]->hcchar=%p\n",
+-00154                             i, &host_if->hc_regs[i]->hcchar);
+-00155         }
+-00156 
+-00157         host_if->num_host_channels = MAX_EPS_CHANNELS;
+-00158         core_if->host_if = host_if;
+-00159 
+-00160         for (i = 0; i < MAX_EPS_CHANNELS; i++) {
+-00161                 core_if->data_fifo[i] =
+-00162                     (uint32_t *) (reg_base + DWC_OTG_DATA_FIFO_OFFSET +
+-00163                                   (i * DWC_OTG_DATA_FIFO_SIZE));
+-00164                 DWC_DEBUGPL(DBG_CILV, "data_fifo[%d]=0x%08lx\n",
+-00165                             i, (unsigned long)core_if->data_fifo[i]);
+-00166         }
+-00167 
+-00168         core_if->pcgcctl = (uint32_t *) (reg_base + DWC_OTG_PCGCCTL_OFFSET);
+-00169 
+-00170         /* Initiate lx_state to L3 disconnected state */
+-00171         core_if->lx_state = DWC_OTG_L3;
+-00172         /*
+-00173          * Store the contents of the hardware configuration registers here for
+-00174          * easy access later.
+-00175          */
+-00176         core_if->hwcfg1.d32 =
+-00177             DWC_READ_REG32(&core_if->core_global_regs->ghwcfg1);
+-00178         core_if->hwcfg2.d32 =
+-00179             DWC_READ_REG32(&core_if->core_global_regs->ghwcfg2);
+-00180         core_if->hwcfg3.d32 =
+-00181             DWC_READ_REG32(&core_if->core_global_regs->ghwcfg3);
+-00182         core_if->hwcfg4.d32 =
+-00183             DWC_READ_REG32(&core_if->core_global_regs->ghwcfg4);
+-00184 
+-00185         /* Force host mode to get HPTXFSIZ exact power on value */
+-00186         {
+-00187                 gusbcfg_data_t gusbcfg = {.d32 = 0 };
+-00188                 gusbcfg.d32 =  DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
+-00189                 gusbcfg.b.force_host_mode = 1;
+-00190                 DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, gusbcfg.d32);
+-00191                 dwc_mdelay(100); 
+-00192                 core_if->hptxfsiz.d32 =
+-00193                 DWC_READ_REG32(&core_if->core_global_regs->hptxfsiz);
+-00194                 gusbcfg.d32 =  DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
+-00195                 gusbcfg.b.force_host_mode = 0;
+-00196                 DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, gusbcfg.d32);
+-00197                 dwc_mdelay(100); 
+-00198         }
+-00199 
+-00200         DWC_DEBUGPL(DBG_CILV, "hwcfg1=%08x\n", core_if->hwcfg1.d32);
+-00201         DWC_DEBUGPL(DBG_CILV, "hwcfg2=%08x\n", core_if->hwcfg2.d32);
+-00202         DWC_DEBUGPL(DBG_CILV, "hwcfg3=%08x\n", core_if->hwcfg3.d32);
+-00203         DWC_DEBUGPL(DBG_CILV, "hwcfg4=%08x\n", core_if->hwcfg4.d32);
+-00204 
+-00205         core_if->hcfg.d32 =
+-00206             DWC_READ_REG32(&core_if->host_if->host_global_regs->hcfg);
+-00207         core_if->dcfg.d32 =
+-00208             DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg);
+-00209 
+-00210         DWC_DEBUGPL(DBG_CILV, "hcfg=%08x\n", core_if->hcfg.d32);
+-00211         DWC_DEBUGPL(DBG_CILV, "dcfg=%08x\n", core_if->dcfg.d32);
+-00212 
+-00213         DWC_DEBUGPL(DBG_CILV, "op_mode=%0x\n", core_if->hwcfg2.b.op_mode);
+-00214         DWC_DEBUGPL(DBG_CILV, "arch=%0x\n", core_if->hwcfg2.b.architecture);
+-00215         DWC_DEBUGPL(DBG_CILV, "num_dev_ep=%d\n", core_if->hwcfg2.b.num_dev_ep);
+-00216         DWC_DEBUGPL(DBG_CILV, "num_host_chan=%d\n",
+-00217                     core_if->hwcfg2.b.num_host_chan);
+-00218         DWC_DEBUGPL(DBG_CILV, "nonperio_tx_q_depth=0x%0x\n",
+-00219                     core_if->hwcfg2.b.nonperio_tx_q_depth);
+-00220         DWC_DEBUGPL(DBG_CILV, "host_perio_tx_q_depth=0x%0x\n",
+-00221                     core_if->hwcfg2.b.host_perio_tx_q_depth);
+-00222         DWC_DEBUGPL(DBG_CILV, "dev_token_q_depth=0x%0x\n",
+-00223                     core_if->hwcfg2.b.dev_token_q_depth);
+-00224 
+-00225         DWC_DEBUGPL(DBG_CILV, "Total FIFO SZ=%d\n",
+-00226                     core_if->hwcfg3.b.dfifo_depth);
+-00227         DWC_DEBUGPL(DBG_CILV, "xfer_size_cntr_width=%0x\n",
+-00228                     core_if->hwcfg3.b.xfer_size_cntr_width);
+-00229 
+-00230         /*
+-00231          * Set the SRP sucess bit for FS-I2c
+-00232          */
+-00233         core_if->srp_success = 0;
+-00234         core_if->srp_timer_started = 0;
+-00235 
+-00236         /*
+-00237          * Create new workqueue and init works
+-00238          */
+-00239         core_if->wq_otg = DWC_WORKQ_ALLOC("dwc_otg");
+-00240         if (core_if->wq_otg == 0) {
+-00241                 DWC_WARN("DWC_WORKQ_ALLOC failed\n");
+-00242                 DWC_FREE(host_if);
+-00243                 DWC_FREE(dev_if);
+-00244                 DWC_FREE(core_if);
+-00245                 return 0;
+-00246         }
+-00247 
+-00248         core_if->snpsid = DWC_READ_REG32(&core_if->core_global_regs->gsnpsid);
+-00249 
+-00250         DWC_PRINTF("Core Release: %x.%x%x%x\n",
+-00251                    (core_if->snpsid >> 12 & 0xF),
+-00252                    (core_if->snpsid >> 8 & 0xF),
+-00253                    (core_if->snpsid >> 4 & 0xF), (core_if->snpsid & 0xF));
+-00254 
+-00255         core_if->wkp_timer = DWC_TIMER_ALLOC("Wake Up Timer",
+-00256                                              w_wakeup_detected, core_if);
+-00257         if (core_if->wkp_timer == 0) {
+-00258                 DWC_WARN("DWC_TIMER_ALLOC failed\n");
+-00259                 DWC_FREE(host_if);
+-00260                 DWC_FREE(dev_if);
+-00261                 DWC_WORKQ_FREE(core_if->wq_otg);
+-00262                 DWC_FREE(core_if);
+-00263                 return 0;
+-00264         }
+-00265 
+-00266         if (dwc_otg_setup_params(core_if)) {
+-00267                 DWC_WARN("Error while setting core params\n");
+-00268         }
+-00269 
+-00270         core_if->hibernation_suspend = 0;
+-00271 
+-00273         dwc_otg_adp_init(core_if);
+-00274         
+-00275         return core_if;
+-00276 }
+-00277 
+-00285 void dwc_otg_cil_remove(dwc_otg_core_if_t * core_if)
+-00286 {
+-00287         /* Disable all interrupts */
+-00288         DWC_MODIFY_REG32(&core_if->core_global_regs->gahbcfg, 1, 0);
+-00289         DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, 0);
+-00290 
+-00291         if (core_if->wq_otg) {
+-00292                 DWC_WORKQ_WAIT_WORK_DONE(core_if->wq_otg, 500);
+-00293                 DWC_WORKQ_FREE(core_if->wq_otg);
+-00294         }
+-00295         if (core_if->dev_if) {
+-00296                 DWC_FREE(core_if->dev_if);
+-00297         }
+-00298         if (core_if->host_if) {
+-00299                 DWC_FREE(core_if->host_if);
+-00300         }
+-00301 
+-00303         dwc_otg_adp_remove(core_if);
+-00304         if (core_if->core_params) {
+-00305                 DWC_FREE(core_if->core_params);
+-00306         }
+-00307         if (core_if->wkp_timer) {
+-00308                 DWC_TIMER_FREE(core_if->wkp_timer);
+-00309         }
+-00310         if (core_if->srp_timer) {
+-00311                 DWC_TIMER_FREE(core_if->srp_timer);
+-00312         }
+-00313         DWC_FREE(core_if);
+-00314 }
+-00315 
+-00322 void dwc_otg_enable_global_interrupts(dwc_otg_core_if_t * core_if)
+-00323 {
+-00324         gahbcfg_data_t ahbcfg = {.d32 = 0 };
+-00325         ahbcfg.b.glblintrmsk = 1;       /* Enable interrupts */
+-00326         DWC_MODIFY_REG32(&core_if->core_global_regs->gahbcfg, 0, ahbcfg.d32);
+-00327 }
+-00328 
+-00335 void dwc_otg_disable_global_interrupts(dwc_otg_core_if_t * core_if)
+-00336 {
+-00337         gahbcfg_data_t ahbcfg = {.d32 = 0 };
+-00338         ahbcfg.b.glblintrmsk = 1;       /* Disable interrupts */
+-00339         DWC_MODIFY_REG32(&core_if->core_global_regs->gahbcfg, ahbcfg.d32, 0);
+-00340 }
+-00341 
+-00349 static void dwc_otg_enable_common_interrupts(dwc_otg_core_if_t * core_if)
+-00350 {
+-00351         dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
+-00352         gintmsk_data_t intr_mask = {.d32 = 0 };
+-00353 
+-00354         /* Clear any pending OTG Interrupts */
+-00355         DWC_WRITE_REG32(&global_regs->gotgint, 0xFFFFFFFF);
+-00356 
+-00357         /* Clear any pending interrupts */
+-00358         DWC_WRITE_REG32(&global_regs->gintsts, 0xFFFFFFFF);
+-00359 
+-00360         /*
+-00361          * Enable the interrupts in the GINTMSK.
+-00362          */
+-00363         intr_mask.b.modemismatch = 1;
+-00364         intr_mask.b.otgintr = 1;
+-00365 
+-00366         if (!core_if->dma_enable) {
+-00367                 intr_mask.b.rxstsqlvl = 1;
+-00368         }
+-00369 
+-00370         intr_mask.b.conidstschng = 1;
+-00371         intr_mask.b.wkupintr = 1;
+-00372         intr_mask.b.disconnect = 0;
+-00373         intr_mask.b.usbsuspend = 1;
+-00374         intr_mask.b.sessreqintr = 1;
+-00375 #ifdef CONFIG_USB_DWC_OTG_LPM
+-00376         if (core_if->core_params->lpm_enable) {
+-00377                 intr_mask.b.lpmtranrcvd = 1;
+-00378         }
+-00379 #endif
+-00380         DWC_WRITE_REG32(&global_regs->gintmsk, intr_mask.d32);
+-00381 }
+-00382 
+-00383 /*
+-00384  * The restore operation is modified to support Synopsys Emulated Powerdown and
+-00385  * Hibernation. This function is for exiting from Device mode hibernation by
+-00386  * Host Initiated Resume/Reset and Device Initiated Remote-Wakeup.
+-00387  * @param core_if Programming view of DWC_otg controller.
+-00388  * @param rem_wakeup - indicates whether resume is initiated by Device or Host.
+-00389  * @param reset - indicates whether resume is initiated by Reset.
+-00390  */
+-00391 int dwc_otg_device_hibernation_restore(dwc_otg_core_if_t * core_if,
+-00392                                        int rem_wakeup, int reset)
+-00393 {
+-00394         gpwrdn_data_t gpwrdn = {.d32 = 0 };
+-00395         pcgcctl_data_t pcgcctl = {.d32 = 0 };
+-00396         dctl_data_t dctl = {.d32 = 0 };
+-00397 
+-00398         int timeout = 2000;
+-00399 
+-00400         if (!core_if->hibernation_suspend) {
+-00401                 DWC_PRINTF("Already exited from Hibernation\n");
+-00402                 return 1;
+-00403         }
+-00404 
+-00405         DWC_DEBUGPL(DBG_PCD, "%s called\n", __FUNCTION__);
+-00406         /* Switch-on voltage to the core */
+-00407         gpwrdn.b.pwrdnswtch = 1;
+-00408         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
+-00409         dwc_udelay(10);
+-00410 
+-00411         /* Reset core */
+-00412         gpwrdn.d32 = 0;
+-00413         gpwrdn.b.pwrdnrstn = 1;
+-00414         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
+-00415         dwc_udelay(10);
+-00416 
+-00417         /* Assert Restore signal */
+-00418         gpwrdn.d32 = 0;
+-00419         gpwrdn.b.restore = 1;
+-00420         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
+-00421         dwc_udelay(10);
+-00422 
+-00423         /* Disable power clamps */
+-00424         gpwrdn.d32 = 0;
+-00425         gpwrdn.b.pwrdnclmp = 1;
+-00426         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
+-00427 
+-00428         if (rem_wakeup) {
+-00429                 dwc_udelay(70);
+-00430         }
+-00431 
+-00432         /* Deassert Reset core */
+-00433         gpwrdn.d32 = 0;
+-00434         gpwrdn.b.pwrdnrstn = 1;
+-00435         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
+-00436         dwc_udelay(10);
+-00437 
+-00438         /* Disable PMU interrupt */
+-00439         gpwrdn.d32 = 0;
+-00440         gpwrdn.b.pmuintsel = 1;
+-00441         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
+-00442 
+-00443         /* Mask interrupts from gpwrdn */
+-00444         gpwrdn.d32 = 0;
+-00445         gpwrdn.b.connect_det_msk = 1;
+-00446         gpwrdn.b.srp_det_msk = 1;
+-00447         gpwrdn.b.disconn_det_msk = 1;
+-00448         gpwrdn.b.rst_det_msk = 1;
+-00449         gpwrdn.b.lnstchng_msk = 1;
+-00450         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
+-00451 
+-00452         /* Indicates that we are going out from hibernation */
+-00453         core_if->hibernation_suspend = 0;
+-00454 
+-00455         /*
+-00456          * Set Restore Essential Regs bit in PCGCCTL register, restore_mode = 1
+-00457          * indicates restore from remote_wakeup
+-00458          */
+-00459         restore_essential_regs(core_if, rem_wakeup, 0);
+-00460 
+-00461         /*
+-00462          * Wait a little for seeing new value of variable hibernation_suspend if
+-00463          * Restore done interrupt received before polling
+-00464          */
+-00465         dwc_udelay(10);
+-00466 
+-00467         if (core_if->hibernation_suspend == 0) {
+-00468                 /*
+-00469                  * Wait For Restore_done Interrupt. This mechanism of polling the 
+-00470                  * interrupt is introduced to avoid any possible race conditions
+-00471                  */
+-00472                 do {
+-00473                         gintsts_data_t gintsts;
+-00474                         gintsts.d32 =
+-00475                             DWC_READ_REG32(&core_if->core_global_regs->gintsts);
+-00476                         if (gintsts.b.restoredone) {
+-00477                                 gintsts.d32 = 0;
+-00478                                 gintsts.b.restoredone = 1;
+-00479                                 DWC_WRITE_REG32(&core_if->core_global_regs->
+-00480                                                 gintsts, gintsts.d32);
+-00481                                 DWC_PRINTF("Restore Done Interrupt seen\n");
+-00482                                 break;
+-00483                         }
+-00484                         dwc_udelay(10);
+-00485                 } while (--timeout);
+-00486                 if (!timeout) {
+-00487                         DWC_PRINTF("Restore Done interrupt wasn't generated here\n");
+-00488                 }
+-00489         }
+-00490         /* Clear all pending interupts */
+-00491         DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
+-00492 
+-00493         /* De-assert Restore */
+-00494         gpwrdn.d32 = 0;
+-00495         gpwrdn.b.restore = 1;
+-00496         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
+-00497         dwc_udelay(10);
+-00498 
+-00499         if (!rem_wakeup) {
+-00500                 pcgcctl.d32 = 0;
+-00501                 pcgcctl.b.rstpdwnmodule = 1;
+-00502                 DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32, 0);
+-00503         }
+-00504 
+-00505         /* Restore GUSBCFG and DCFG */
+-00506         DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg,
+-00507                         core_if->gr_backup->gusbcfg_local);
+-00508         DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dcfg,
+-00509                         core_if->dr_backup->dcfg);
+-00510 
+-00511         /* De-assert Wakeup Logic */
+-00512         gpwrdn.d32 = 0;
+-00513         gpwrdn.b.pmuactv = 1;
+-00514         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
+-00515         dwc_udelay(10);
+-00516 
+-00517         if (!rem_wakeup) {
+-00518                 /* Set Device programming done bit */
+-00519                 dctl.b.pwronprgdone = 1;
+-00520                 DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, 0, dctl.d32);
+-00521         } else {
+-00522                 /* Start Remote Wakeup Signaling */
+-00523                 dctl.d32 = core_if->dr_backup->dctl;
+-00524                 dctl.b.rmtwkupsig = 1;
+-00525                 DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32);
+-00526         }
+-00527 
+-00528         dwc_mdelay(2);
+-00529         /* Clear all pending interupts */
+-00530         DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
+-00531 
+-00532         /* Restore global registers */
+-00533         dwc_otg_restore_global_regs(core_if);
+-00534         /* Restore device global registers */
+-00535         dwc_otg_restore_dev_regs(core_if, rem_wakeup);
+-00536 
+-00537         if (rem_wakeup) {
+-00538                 dwc_mdelay(7);
+-00539                 dctl.d32 = 0;
+-00540                 dctl.b.rmtwkupsig = 1;
+-00541                 DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32, 0);
+-00542         }
+-00543 
+-00544         core_if->hibernation_suspend = 0;
+-00545         /* The core will be in ON STATE */
+-00546         core_if->lx_state = DWC_OTG_L0;
+-00547         DWC_PRINTF("Hibernation recovery completes here\n");
+-00548 
+-00549         return 1;
+-00550 }
+-00551 
+-00552 /*
+-00553  * The restore operation is modified to support Synopsys Emulated Powerdown and
+-00554  * Hibernation. This function is for exiting from Host mode hibernation by
+-00555  * Host Initiated Resume/Reset and Device Initiated Remote-Wakeup.
+-00556  * @param core_if Programming view of DWC_otg controller.
+-00557  * @param rem_wakeup - indicates whether resume is initiated by Device or Host.
+-00558  * @param reset - indicates whether resume is initiated by Reset.
+-00559  */
+-00560 int dwc_otg_host_hibernation_restore(dwc_otg_core_if_t * core_if,
+-00561                                      int rem_wakeup, int reset)
+-00562 {
+-00563         gpwrdn_data_t gpwrdn = {.d32 = 0 };
+-00564         hprt0_data_t hprt0 = {.d32 = 0 };
+-00565 
+-00566         int timeout = 2000;
+-00567 
+-00568         DWC_DEBUGPL(DBG_HCD, "%s called\n", __FUNCTION__);
+-00569         /* Switch-on voltage to the core */
+-00570         gpwrdn.b.pwrdnswtch = 1;
+-00571         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
+-00572         dwc_udelay(10);
+-00573 
+-00574         /* Reset core */
+-00575         gpwrdn.d32 = 0;
+-00576         gpwrdn.b.pwrdnrstn = 1;
+-00577         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
+-00578         dwc_udelay(10);
+-00579 
+-00580         /* Assert Restore signal */
+-00581         gpwrdn.d32 = 0;
+-00582         gpwrdn.b.restore = 1;
+-00583         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
+-00584         dwc_udelay(10);
+-00585 
+-00586         /* Disable power clamps */
+-00587         gpwrdn.d32 = 0;
+-00588         gpwrdn.b.pwrdnclmp = 1;
+-00589         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
+-00590 
+-00591         if (!rem_wakeup) {
+-00592                 dwc_udelay(50);
+-00593         }
+-00594 
+-00595         /* Deassert Reset core */
+-00596         gpwrdn.d32 = 0;
+-00597         gpwrdn.b.pwrdnrstn = 1;
+-00598         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
+-00599         dwc_udelay(10);
+-00600 
+-00601         /* Disable PMU interrupt */
+-00602         gpwrdn.d32 = 0;
+-00603         gpwrdn.b.pmuintsel = 1;
+-00604         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
+-00605 
+-00606         gpwrdn.d32 = 0;
+-00607         gpwrdn.b.connect_det_msk = 1;
+-00608         gpwrdn.b.srp_det_msk = 1;
+-00609         gpwrdn.b.disconn_det_msk = 1;
+-00610         gpwrdn.b.rst_det_msk = 1;
+-00611         gpwrdn.b.lnstchng_msk = 1;
+-00612         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
+-00613 
+-00614         /* Indicates that we are going out from hibernation */
+-00615         core_if->hibernation_suspend = 0;
+-00616 
+-00617         /* Set Restore Essential Regs bit in PCGCCTL register */
+-00618         restore_essential_regs(core_if, rem_wakeup, 1);
+-00619 
+-00620         /* Wait a little for seeing new value of variable hibernation_suspend if
+-00621          * Restore done interrupt received before polling */
+-00622         dwc_udelay(10);
+-00623 
+-00624         if (core_if->hibernation_suspend == 0) {
+-00625                 /* Wait For Restore_done Interrupt. This mechanism of polling the
+-00626                  * interrupt is introduced to avoid any possible race conditions
+-00627                  */
+-00628                 do {
+-00629                         gintsts_data_t gintsts;
+-00630                         gintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts);
+-00631                         if (gintsts.b.restoredone) {
+-00632                                 gintsts.d32 = 0;
+-00633                                 gintsts.b.restoredone = 1;
+-00634                         DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
+-00635                                 DWC_DEBUGPL(DBG_HCD,"Restore Done Interrupt seen\n");   
+-00636                                 break;
+-00637                         }
+-00638                         dwc_udelay(10);
+-00639                 } while (--timeout);
+-00640                 if (!timeout) {
+-00641                         DWC_WARN("Restore Done interrupt wasn't generated\n");
+-00642                 }
+-00643         }
+-00644 
+-00645         /* Set the flag's value to 0 again after receiving restore done interrupt */
+-00646         core_if->hibernation_suspend = 0;
+-00647 
+-00648         /* This step is not described in functional spec but if not wait for this
+-00649          * delay, mismatch interrupts occurred because just after restore core is
+-00650          * in Device mode(gintsts.curmode == 0) */
+-00651         dwc_mdelay(100);
+-00652 
+-00653         /* Clear all pending interrupts */
+-00654         DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
+-00655 
+-00656         /* De-assert Restore */
+-00657         gpwrdn.d32 = 0;
+-00658         gpwrdn.b.restore = 1;
+-00659         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
+-00660         dwc_udelay(10);
+-00661 
+-00662         /* Restore GUSBCFG and HCFG */
+-00663         DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg,
+-00664                         core_if->gr_backup->gusbcfg_local);
+-00665         DWC_WRITE_REG32(&core_if->host_if->host_global_regs->hcfg,
+-00666                         core_if->hr_backup->hcfg_local);
+-00667 
+-00668         /* De-assert Wakeup Logic */
+-00669         gpwrdn.d32 = 0;
+-00670         gpwrdn.b.pmuactv = 1;
+-00671         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
+-00672         dwc_udelay(10);
+-00673 
+-00674         /* Start the Resume operation by programming HPRT0 */
+-00675         hprt0.d32 = core_if->hr_backup->hprt0_local;
+-00676         hprt0.b.prtpwr = 1;
+-00677         hprt0.b.prtena = 0;
+-00678         hprt0.b.prtsusp = 0;
+-00679         DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
+-00680 
+-00681         DWC_PRINTF("Resume Starts Now\n");
+-00682         if (!reset) {           // Indicates it is Resume Operation
+-00683                 hprt0.d32 = core_if->hr_backup->hprt0_local;
+-00684                 hprt0.b.prtres = 1;
+-00685                 hprt0.b.prtpwr = 1;
+-00686                 hprt0.b.prtena = 0;
+-00687                 hprt0.b.prtsusp = 0;
+-00688                 DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
+-00689 
+-00690                 if (!rem_wakeup)
+-00691                         hprt0.b.prtres = 0;
+-00692                 /* Wait for Resume time and then program HPRT again */
+-00693                 dwc_mdelay(100);
+-00694                 DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
+-00695 
+-00696         } else {                // Indicates it is Reset Operation
+-00697                 hprt0.d32 = core_if->hr_backup->hprt0_local;
+-00698                 hprt0.b.prtrst = 1;
+-00699                 hprt0.b.prtpwr = 1;
+-00700                 hprt0.b.prtena = 0;
+-00701                 hprt0.b.prtsusp = 0;
+-00702                 DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
+-00703                 /* Wait for Reset time and then program HPRT again */
+-00704                 dwc_mdelay(60);
+-00705                 hprt0.b.prtrst = 0;
+-00706                 DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
+-00707         }
+-00708         /* Clear all interrupt status */
+-00709         hprt0.d32 = dwc_otg_read_hprt0(core_if);
+-00710         hprt0.b.prtconndet = 1;
+-00711         hprt0.b.prtenchng = 1;
+-00712         DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
+-00713 
+-00714         /* Clear all pending interupts */
+-00715         DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
+-00716 
+-00717         /* Restore global registers */
+-00718         dwc_otg_restore_global_regs(core_if);
+-00719         /* Restore host global registers */
+-00720         dwc_otg_restore_host_regs(core_if, reset);
+-00721 
+-00722         /* The core will be in ON STATE */
+-00723         core_if->lx_state = DWC_OTG_L0;
+-00724         DWC_PRINTF("Hibernation recovery is complete here\n");
+-00725         return 0;
+-00726 }
+-00727 
+-00729 int dwc_otg_save_global_regs(dwc_otg_core_if_t * core_if)
+-00730 {
+-00731         struct dwc_otg_global_regs_backup *gr;
+-00732         int i;
+-00733 
+-00734         gr = core_if->gr_backup;
+-00735         if (!gr) {
+-00736                 gr = DWC_ALLOC(sizeof(*gr));
+-00737                 if (!gr) {
+-00738                         return -DWC_E_NO_MEMORY;
+-00739                 }
+-00740                 core_if->gr_backup = gr;
+-00741         }
+-00742 
+-00743         gr->gotgctl_local = DWC_READ_REG32(&core_if->core_global_regs->gotgctl);
+-00744         gr->gintmsk_local = DWC_READ_REG32(&core_if->core_global_regs->gintmsk);
+-00745         gr->gahbcfg_local = DWC_READ_REG32(&core_if->core_global_regs->gahbcfg);
+-00746         gr->gusbcfg_local = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
+-00747         gr->grxfsiz_local = DWC_READ_REG32(&core_if->core_global_regs->grxfsiz);
+-00748         gr->gnptxfsiz_local = DWC_READ_REG32(&core_if->core_global_regs->gnptxfsiz);
+-00749         gr->hptxfsiz_local = DWC_READ_REG32(&core_if->core_global_regs->hptxfsiz);
+-00750 #ifdef CONFIG_USB_DWC_OTG_LPM
+-00751         gr->glpmcfg_local = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
+-00752 #endif
+-00753         gr->gi2cctl_local = DWC_READ_REG32(&core_if->core_global_regs->gi2cctl);
+-00754         gr->pcgcctl_local = DWC_READ_REG32(core_if->pcgcctl);
+-00755         gr->gdfifocfg_local =
+-00756             DWC_READ_REG32(&core_if->core_global_regs->gdfifocfg);
+-00757         for (i = 0; i < MAX_EPS_CHANNELS; i++) {
+-00758                 gr->dtxfsiz_local[i] =
+-00759                     DWC_READ_REG32(&(core_if->core_global_regs->dtxfsiz[i]));
+-00760         }
+-00761 
+-00762         DWC_DEBUGPL(DBG_ANY, "===========Backing Global registers==========\n");
+-00763         DWC_DEBUGPL(DBG_ANY, "Backed up gotgctl   = %08x\n", gr->gotgctl_local);
+-00764         DWC_DEBUGPL(DBG_ANY, "Backed up gintmsk   = %08x\n", gr->gintmsk_local);
+-00765         DWC_DEBUGPL(DBG_ANY, "Backed up gahbcfg   = %08x\n", gr->gahbcfg_local);
+-00766         DWC_DEBUGPL(DBG_ANY, "Backed up gusbcfg   = %08x\n", gr->gusbcfg_local);
+-00767         DWC_DEBUGPL(DBG_ANY, "Backed up grxfsiz   = %08x\n", gr->grxfsiz_local);
+-00768         DWC_DEBUGPL(DBG_ANY, "Backed up gnptxfsiz = %08x\n",
+-00769                     gr->gnptxfsiz_local);
+-00770         DWC_DEBUGPL(DBG_ANY, "Backed up hptxfsiz  = %08x\n",
+-00771                     gr->hptxfsiz_local);
+-00772 #ifdef CONFIG_USB_DWC_OTG_LPM
+-00773         DWC_DEBUGPL(DBG_ANY, "Backed up glpmcfg   = %08x\n", gr->glpmcfg_local);
+-00774 #endif
+-00775         DWC_DEBUGPL(DBG_ANY, "Backed up gi2cctl   = %08x\n", gr->gi2cctl_local);
+-00776         DWC_DEBUGPL(DBG_ANY, "Backed up pcgcctl   = %08x\n", gr->pcgcctl_local);
+-00777         DWC_DEBUGPL(DBG_ANY,"Backed up gdfifocfg   = %08x\n",gr->gdfifocfg_local);
+-00778 
+-00779         return 0;
+-00780 }
+-00781 
+-00783 int dwc_otg_save_gintmsk_reg(dwc_otg_core_if_t * core_if)
+-00784 {
+-00785         struct dwc_otg_global_regs_backup *gr;
+-00786 
+-00787         gr = core_if->gr_backup;
+-00788         if (!gr) {
+-00789                 gr = DWC_ALLOC(sizeof(*gr));
+-00790                 if (!gr) {
+-00791                         return -DWC_E_NO_MEMORY;
+-00792                 }
+-00793                 core_if->gr_backup = gr;
+-00794         }
+-00795 
+-00796         gr->gintmsk_local = DWC_READ_REG32(&core_if->core_global_regs->gintmsk);
+-00797 
+-00798         DWC_DEBUGPL(DBG_ANY,"=============Backing GINTMSK registers============\n");
+-00799         DWC_DEBUGPL(DBG_ANY, "Backed up gintmsk   = %08x\n", gr->gintmsk_local);
+-00800 
+-00801         return 0;
+-00802 }
+-00803 
+-00804 int dwc_otg_save_dev_regs(dwc_otg_core_if_t * core_if)
+-00805 {
+-00806         struct dwc_otg_dev_regs_backup *dr;
+-00807         int i;
+-00808 
+-00809         dr = core_if->dr_backup;
+-00810         if (!dr) {
+-00811                 dr = DWC_ALLOC(sizeof(*dr));
+-00812                 if (!dr) {
+-00813                         return -DWC_E_NO_MEMORY;
+-00814                 }
+-00815                 core_if->dr_backup = dr;
+-00816         }
+-00817 
+-00818         dr->dcfg = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg);
+-00819         dr->dctl = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dctl);
+-00820         dr->daintmsk =
+-00821             DWC_READ_REG32(&core_if->dev_if->dev_global_regs->daintmsk);
+-00822         dr->diepmsk =
+-00823             DWC_READ_REG32(&core_if->dev_if->dev_global_regs->diepmsk);
+-00824         dr->doepmsk =
+-00825             DWC_READ_REG32(&core_if->dev_if->dev_global_regs->doepmsk);
+-00826 
+-00827         for (i = 0; i < core_if->dev_if->num_in_eps; ++i) {
+-00828                 dr->diepctl[i] =
+-00829                     DWC_READ_REG32(&core_if->dev_if->in_ep_regs[i]->diepctl);
+-00830                 dr->dieptsiz[i] =
+-00831                     DWC_READ_REG32(&core_if->dev_if->in_ep_regs[i]->dieptsiz);
+-00832                 dr->diepdma[i] =
+-00833                     DWC_READ_REG32(&core_if->dev_if->in_ep_regs[i]->diepdma);
+-00834         }
+-00835 
+-00836         DWC_DEBUGPL(DBG_ANY,
+-00837                     "=============Backing Host registers==============\n");
+-00838         DWC_DEBUGPL(DBG_ANY, "Backed up dcfg            = %08x\n", dr->dcfg);
+-00839         DWC_DEBUGPL(DBG_ANY, "Backed up dctl        = %08x\n", dr->dctl);
+-00840         DWC_DEBUGPL(DBG_ANY, "Backed up daintmsk            = %08x\n",
+-00841                     dr->daintmsk);
+-00842         DWC_DEBUGPL(DBG_ANY, "Backed up diepmsk        = %08x\n", dr->diepmsk);
+-00843         DWC_DEBUGPL(DBG_ANY, "Backed up doepmsk        = %08x\n", dr->doepmsk);
+-00844         for (i = 0; i < core_if->dev_if->num_in_eps; ++i) {
+-00845                 DWC_DEBUGPL(DBG_ANY, "Backed up diepctl[%d]        = %08x\n", i,
+-00846                             dr->diepctl[i]);
+-00847                 DWC_DEBUGPL(DBG_ANY, "Backed up dieptsiz[%d]        = %08x\n",
+-00848                             i, dr->dieptsiz[i]);
+-00849                 DWC_DEBUGPL(DBG_ANY, "Backed up diepdma[%d]        = %08x\n", i,
+-00850                             dr->diepdma[i]);
+-00851         }
+-00852 
+-00853         return 0;
+-00854 }
+-00855 
+-00856 int dwc_otg_save_host_regs(dwc_otg_core_if_t * core_if)
+-00857 {
+-00858         struct dwc_otg_host_regs_backup *hr;
+-00859         int i;
+-00860 
+-00861         hr = core_if->hr_backup;
+-00862         if (!hr) {
+-00863                 hr = DWC_ALLOC(sizeof(*hr));
+-00864                 if (!hr) {
+-00865                         return -DWC_E_NO_MEMORY;
+-00866                 }
+-00867                 core_if->hr_backup = hr;
+-00868         }
+-00869 
+-00870         hr->hcfg_local =
+-00871             DWC_READ_REG32(&core_if->host_if->host_global_regs->hcfg);
+-00872         hr->haintmsk_local =
+-00873             DWC_READ_REG32(&core_if->host_if->host_global_regs->haintmsk);
+-00874         for (i = 0; i < dwc_otg_get_param_host_channels(core_if); ++i) {
+-00875                 hr->hcintmsk_local[i] =
+-00876                     DWC_READ_REG32(&core_if->host_if->hc_regs[i]->hcintmsk);
+-00877         }
+-00878         hr->hprt0_local = DWC_READ_REG32(core_if->host_if->hprt0);
+-00879         hr->hfir_local =
+-00880             DWC_READ_REG32(&core_if->host_if->host_global_regs->hfir);
+-00881 
+-00882         DWC_DEBUGPL(DBG_ANY,
+-00883                     "=============Backing Host registers===============\n");
+-00884         DWC_DEBUGPL(DBG_ANY, "Backed up hcfg            = %08x\n",
+-00885                     hr->hcfg_local);
+-00886         DWC_DEBUGPL(DBG_ANY, "Backed up haintmsk = %08x\n", hr->haintmsk_local);
+-00887         for (i = 0; i < dwc_otg_get_param_host_channels(core_if); ++i) {
+-00888                 DWC_DEBUGPL(DBG_ANY, "Backed up hcintmsk[%02d]=%08x\n", i,
+-00889                             hr->hcintmsk_local[i]);
+-00890         }
+-00891         DWC_DEBUGPL(DBG_ANY, "Backed up hprt0           = %08x\n",
+-00892                     hr->hprt0_local);
+-00893         DWC_DEBUGPL(DBG_ANY, "Backed up hfir           = %08x\n",
+-00894                     hr->hfir_local);
+-00895 
+-00896         return 0;
+-00897 }
+-00898 
+-00899 int dwc_otg_restore_global_regs(dwc_otg_core_if_t *core_if)
+-00900 {
+-00901         struct dwc_otg_global_regs_backup *gr;
+-00902         int i;
+-00903 
+-00904         gr = core_if->gr_backup;
+-00905         if (!gr) {
+-00906                 return -DWC_E_INVALID;
+-00907         }
+-00908    
+-00909         DWC_WRITE_REG32(&core_if->core_global_regs->gotgctl, gr->gotgctl_local);
+-00910         DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, gr->gintmsk_local);
+-00911         DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, gr->gusbcfg_local);
+-00912         DWC_WRITE_REG32(&core_if->core_global_regs->gahbcfg, gr->gahbcfg_local);
+-00913         DWC_WRITE_REG32(&core_if->core_global_regs->grxfsiz, gr->grxfsiz_local);
+-00914         DWC_WRITE_REG32(&core_if->core_global_regs->gnptxfsiz,
+-00915                         gr->gnptxfsiz_local);
+-00916         DWC_WRITE_REG32(&core_if->core_global_regs->hptxfsiz,
+-00917                         gr->hptxfsiz_local);
+-00918         DWC_WRITE_REG32(&core_if->core_global_regs->gdfifocfg,
+-00919                         gr->gdfifocfg_local);
+-00920         for (i = 0; i < MAX_EPS_CHANNELS; i++) {
+-00921                 DWC_WRITE_REG32(&core_if->core_global_regs->dtxfsiz[i],
+-00922                                 gr->dtxfsiz_local[i]);
+-00923         }
+-00924 
+-00925         DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
+-00926         DWC_WRITE_REG32(core_if->host_if->hprt0, 0x0000100A);
+-00927         DWC_WRITE_REG32(&core_if->core_global_regs->gahbcfg,
+-00928                         (gr->gahbcfg_local));
+-00929         return 0;
+-00930 }
+-00931 
+-00932 int dwc_otg_restore_dev_regs(dwc_otg_core_if_t * core_if, int rem_wakeup)
+-00933 {
+-00934         struct dwc_otg_dev_regs_backup *dr;
+-00935         int i;
+-00936 
+-00937         dr = core_if->dr_backup;
+-00938 
+-00939         if (!dr) {
+-00940                 return -DWC_E_INVALID;
+-00941         }
+-00942 
+-00943         if (!rem_wakeup)
+-00944         {
+-00945                 DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl, dr->dctl);
+-00946         }
+-00947         
+-00948         DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->daintmsk, dr->daintmsk);
+-00949         DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->diepmsk, dr->diepmsk);
+-00950         DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->doepmsk, dr->doepmsk);
+-00951 
+-00952         for (i = 0; i < core_if->dev_if->num_in_eps; ++i) {
+-00953                 DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[i]->diepctl, dr->diepctl[i]);
+-00954                 DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[i]->dieptsiz, dr->dieptsiz[i]);
+-00955                 DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[i]->diepdma, dr->diepdma[i]);
+-00956         }
+-00957         
+-00958         return 0;
+-00959 }
+-00960 
+-00961 int dwc_otg_restore_host_regs(dwc_otg_core_if_t * core_if, int reset)
+-00962 {
+-00963         struct dwc_otg_host_regs_backup *hr;
+-00964         int i;
+-00965         hr = core_if->hr_backup;
+-00966 
+-00967         if (!hr) {
+-00968                 return -DWC_E_INVALID;
+-00969         }
+-00970 
+-00971         DWC_WRITE_REG32(&core_if->host_if->host_global_regs->hcfg, hr->hcfg_local);
+-00972         //if (!reset)
+-00973         //{
+-00974         //      DWC_WRITE_REG32(&core_if->host_if->host_global_regs->hfir, hr->hfir_local);
+-00975         //}
+-00976 
+-00977         DWC_WRITE_REG32(&core_if->host_if->host_global_regs->haintmsk,
+-00978                         hr->haintmsk_local);
+-00979         for (i = 0; i < dwc_otg_get_param_host_channels(core_if); ++i) {
+-00980                 DWC_WRITE_REG32(&core_if->host_if->hc_regs[i]->hcintmsk,
+-00981                                 hr->hcintmsk_local[i]);
+-00982         }
+-00983 
+-00984         return 0;
+-00985 }
+-00986 
+-00987 int restore_lpm_i2c_regs(dwc_otg_core_if_t * core_if)
+-00988 {
+-00989         struct dwc_otg_global_regs_backup *gr;
+-00990 
+-00991         gr = core_if->gr_backup;
+-00992 
+-00993         /* Restore values for LPM and I2C */
+-00994 #ifdef CONFIG_USB_DWC_OTG_LPM
+-00995         DWC_WRITE_REG32(&core_if->core_global_regs->glpmcfg, gr->glpmcfg_local);
+-00996 #endif
+-00997         DWC_WRITE_REG32(&core_if->core_global_regs->gi2cctl, gr->gi2cctl_local);
+-00998 
+-00999         return 0;
+-01000 }
+-01001 
+-01002 int restore_essential_regs(dwc_otg_core_if_t * core_if, int rmode, int is_host)
+-01003 {
+-01004         struct dwc_otg_global_regs_backup *gr;
+-01005         pcgcctl_data_t pcgcctl = {.d32 = 0 };
+-01006         gahbcfg_data_t gahbcfg = {.d32 = 0 };
+-01007         gusbcfg_data_t gusbcfg = {.d32 = 0 };
+-01008         gintmsk_data_t gintmsk = {.d32 = 0 };
+-01009 
+-01010         /* Restore LPM and I2C registers */
+-01011         restore_lpm_i2c_regs(core_if);
+-01012 
+-01013         /* Set PCGCCTL to 0 */
+-01014         DWC_WRITE_REG32(core_if->pcgcctl, 0x00000000);
+-01015 
+-01016         gr = core_if->gr_backup;
+-01017         /* Load restore values for [31:14] bits */
+-01018         DWC_WRITE_REG32(core_if->pcgcctl,
+-01019                         ((gr->pcgcctl_local & 0xffffc000) | 0x00020000));
+-01020 
+-01021         /* Umnask global Interrupt in GAHBCFG and restore it */
+-01022         gahbcfg.d32 = gr->gahbcfg_local;
+-01023         gahbcfg.b.glblintrmsk = 1;
+-01024         DWC_WRITE_REG32(&core_if->core_global_regs->gahbcfg, gahbcfg.d32);
+-01025 
+-01026         /* Clear all pending interupts */
+-01027         DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
+-01028 
+-01029         /* Unmask restore done interrupt */
+-01030         gintmsk.b.restoredone = 1;
+-01031         DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, gintmsk.d32);
+-01032 
+-01033         /* Restore GUSBCFG and HCFG/DCFG */
+-01034         gusbcfg.d32 = core_if->gr_backup->gusbcfg_local;
+-01035         DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, gusbcfg.d32);
+-01036 
+-01037         if (is_host) {
+-01038                 hcfg_data_t hcfg = {.d32 = 0 };
+-01039                 hcfg.d32 = core_if->hr_backup->hcfg_local;
+-01040                 DWC_WRITE_REG32(&core_if->host_if->host_global_regs->hcfg,
+-01041                                 hcfg.d32);
+-01042 
+-01043                 /* Load restore values for [31:14] bits */
+-01044                 pcgcctl.d32 = gr->pcgcctl_local & 0xffffc000;
+-01045                 pcgcctl.d32 = gr->pcgcctl_local | 0x00020000;
+-01046 
+-01047                 if (rmode)
+-01048                         pcgcctl.b.restoremode = 1;
+-01049                 DWC_WRITE_REG32(core_if->pcgcctl, pcgcctl.d32);
+-01050                 dwc_udelay(10);
+-01051 
+-01052                 /* Load restore values for [31:14] bits and set EssRegRestored bit */
+-01053                 pcgcctl.d32 = gr->pcgcctl_local | 0xffffc000;
+-01054                 pcgcctl.d32 = gr->pcgcctl_local & 0xffffc000;
+-01055                 pcgcctl.b.ess_reg_restored = 1;
+-01056                 if (rmode)
+-01057                         pcgcctl.b.restoremode = 1;
+-01058                 DWC_WRITE_REG32(core_if->pcgcctl, pcgcctl.d32);
+-01059         } else {
+-01060                 dcfg_data_t dcfg = {.d32 = 0 };
+-01061                 dcfg.d32 = core_if->dr_backup->dcfg;
+-01062                 DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dcfg, dcfg.d32);
+-01063 
+-01064                 /* Load restore values for [31:14] bits */
+-01065                 pcgcctl.d32 = gr->pcgcctl_local & 0xffffc000;
+-01066                 pcgcctl.d32 = gr->pcgcctl_local | 0x00020000;
+-01067                 if (!rmode) {
+-01068                         pcgcctl.d32 |= 0x208;
+-01069                 }
+-01070                 DWC_WRITE_REG32(core_if->pcgcctl, pcgcctl.d32);
+-01071                 dwc_udelay(10);
+-01072 
+-01073                 /* Load restore values for [31:14] bits */
+-01074                 pcgcctl.d32 = gr->pcgcctl_local & 0xffffc000;
+-01075                 pcgcctl.d32 = gr->pcgcctl_local | 0x00020000;
+-01076                 pcgcctl.b.ess_reg_restored = 1;
+-01077                 if (!rmode)
+-01078                         pcgcctl.d32 |= 0x208;
+-01079                 DWC_WRITE_REG32(core_if->pcgcctl, pcgcctl.d32);
+-01080         }
+-01081 
+-01082         return 0;
+-01083 }
+-01084 
+-01089 static void init_fslspclksel(dwc_otg_core_if_t * core_if)
+-01090 {
+-01091         uint32_t val;
+-01092         hcfg_data_t hcfg;
+-01093 
+-01094         if (((core_if->hwcfg2.b.hs_phy_type == 2) &&
+-01095              (core_if->hwcfg2.b.fs_phy_type == 1) &&
+-01096              (core_if->core_params->ulpi_fs_ls)) ||
+-01097             (core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS)) {
+-01098                 /* Full speed PHY */
+-01099                 val = DWC_HCFG_48_MHZ;
+-01100         } else {
+-01101                 /* High speed PHY running at full speed or high speed */
+-01102                 val = DWC_HCFG_30_60_MHZ;
+-01103         }
+-01104 
+-01105         DWC_DEBUGPL(DBG_CIL, "Initializing HCFG.FSLSPClkSel to 0x%1x\n", val);
+-01106         hcfg.d32 = DWC_READ_REG32(&core_if->host_if->host_global_regs->hcfg);
+-01107         hcfg.b.fslspclksel = val;
+-01108         DWC_WRITE_REG32(&core_if->host_if->host_global_regs->hcfg, hcfg.d32);
+-01109 }
+-01110 
+-01115 static void init_devspd(dwc_otg_core_if_t * core_if)
+-01116 {
+-01117         uint32_t val;
+-01118         dcfg_data_t dcfg;
+-01119 
+-01120         if (((core_if->hwcfg2.b.hs_phy_type == 2) &&
+-01121              (core_if->hwcfg2.b.fs_phy_type == 1) &&
+-01122              (core_if->core_params->ulpi_fs_ls)) ||
+-01123             (core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS)) {
+-01124                 /* Full speed PHY */
+-01125                 val = 0x3;
+-01126         } else if (core_if->core_params->speed == DWC_SPEED_PARAM_FULL) {
+-01127                 /* High speed PHY running at full speed */
+-01128                 val = 0x1;
+-01129         } else {
+-01130                 /* High speed PHY running at high speed */
+-01131                 val = 0x0;
+-01132         }
+-01133 
+-01134         DWC_DEBUGPL(DBG_CIL, "Initializing DCFG.DevSpd to 0x%1x\n", val);
+-01135 
+-01136         dcfg.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg);
+-01137         dcfg.b.devspd = val;
+-01138         DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dcfg, dcfg.d32);
+-01139 }
+-01140 
+-01147 static uint32_t calc_num_in_eps(dwc_otg_core_if_t * core_if)
+-01148 {
+-01149         uint32_t num_in_eps = 0;
+-01150         uint32_t num_eps = core_if->hwcfg2.b.num_dev_ep;
+-01151         uint32_t hwcfg1 = core_if->hwcfg1.d32 >> 3;
+-01152         uint32_t num_tx_fifos = core_if->hwcfg4.b.num_in_eps;
+-01153         int i;
+-01154 
+-01155         for (i = 0; i < num_eps; ++i) {
+-01156                 if (!(hwcfg1 & 0x1))
+-01157                         num_in_eps++;
+-01158 
+-01159                 hwcfg1 >>= 2;
+-01160         }
+-01161 
+-01162         if (core_if->hwcfg4.b.ded_fifo_en) {
+-01163                 num_in_eps =
+-01164                     (num_in_eps > num_tx_fifos) ? num_tx_fifos : num_in_eps;
+-01165         }
+-01166 
+-01167         return num_in_eps;
+-01168 }
+-01169 
+-01176 static uint32_t calc_num_out_eps(dwc_otg_core_if_t * core_if)
+-01177 {
+-01178         uint32_t num_out_eps = 0;
+-01179         uint32_t num_eps = core_if->hwcfg2.b.num_dev_ep;
+-01180         uint32_t hwcfg1 = core_if->hwcfg1.d32 >> 2;
+-01181         int i;
+-01182 
+-01183         for (i = 0; i < num_eps; ++i) {
+-01184                 if (!(hwcfg1 & 0x1))
+-01185                         num_out_eps++;
+-01186 
+-01187                 hwcfg1 >>= 2;
+-01188         }
+-01189         return num_out_eps;
+-01190 }
+-01191 
+-01199 void dwc_otg_core_init(dwc_otg_core_if_t * core_if)
+-01200 {
+-01201         int i = 0;
+-01202         dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
+-01203         dwc_otg_dev_if_t *dev_if = core_if->dev_if;
+-01204         gahbcfg_data_t ahbcfg = {.d32 = 0 };
+-01205         gusbcfg_data_t usbcfg = {.d32 = 0 };
+-01206         gi2cctl_data_t i2cctl = {.d32 = 0 };
+-01207 
+-01208         DWC_DEBUGPL(DBG_CILV, "dwc_otg_core_init(%p)\n", core_if);
+-01209 
+-01210         /* Common Initialization */
+-01211         usbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg);
+-01212 
+-01213         /* Program the ULPI External VBUS bit if needed */
+-01214         usbcfg.b.ulpi_ext_vbus_drv =
+-01215             (core_if->core_params->phy_ulpi_ext_vbus ==
+-01216              DWC_PHY_ULPI_EXTERNAL_VBUS) ? 1 : 0;
+-01217 
+-01218         /* Set external TS Dline pulsing */
+-01219         usbcfg.b.term_sel_dl_pulse =
+-01220             (core_if->core_params->ts_dline == 1) ? 1 : 0;
+-01221         DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32);
+-01222 
+-01223         /* Reset the Controller */
+-01224         dwc_otg_core_reset(core_if);
+-01225 
+-01226         core_if->adp_enable = core_if->core_params->adp_supp_enable;
+-01227         core_if->power_down = core_if->core_params->power_down;
+-01228         core_if->otg_sts = 0;
+-01229 
+-01230         /* Initialize parameters from Hardware configuration registers. */
+-01231         dev_if->num_in_eps = calc_num_in_eps(core_if);
+-01232         dev_if->num_out_eps = calc_num_out_eps(core_if);
+-01233 
+-01234         DWC_DEBUGPL(DBG_CIL, "num_dev_perio_in_ep=%d\n",
+-01235                     core_if->hwcfg4.b.num_dev_perio_in_ep);
+-01236 
+-01237         for (i = 0; i < core_if->hwcfg4.b.num_dev_perio_in_ep; i++) {
+-01238                 dev_if->perio_tx_fifo_size[i] =
+-01239                     DWC_READ_REG32(&global_regs->dtxfsiz[i]) >> 16;
+-01240                 DWC_DEBUGPL(DBG_CIL, "Periodic Tx FIFO SZ #%d=0x%0x\n",
+-01241                             i, dev_if->perio_tx_fifo_size[i]);
+-01242         }
+-01243 
+-01244         for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {
+-01245                 dev_if->tx_fifo_size[i] =
+-01246                     DWC_READ_REG32(&global_regs->dtxfsiz[i]) >> 16;
+-01247                 DWC_DEBUGPL(DBG_CIL, "Tx FIFO SZ #%d=0x%0x\n",
+-01248                             i, dev_if->tx_fifo_size[i]);
+-01249         }
+-01250 
+-01251         core_if->total_fifo_size = core_if->hwcfg3.b.dfifo_depth;
+-01252         core_if->rx_fifo_size = DWC_READ_REG32(&global_regs->grxfsiz);
+-01253         core_if->nperio_tx_fifo_size =
+-01254             DWC_READ_REG32(&global_regs->gnptxfsiz) >> 16;
+-01255 
+-01256         DWC_DEBUGPL(DBG_CIL, "Total FIFO SZ=%d\n", core_if->total_fifo_size);
+-01257         DWC_DEBUGPL(DBG_CIL, "Rx FIFO SZ=%d\n", core_if->rx_fifo_size);
+-01258         DWC_DEBUGPL(DBG_CIL, "NP Tx FIFO SZ=%d\n",
+-01259                     core_if->nperio_tx_fifo_size);
+-01260 
+-01261         /* This programming sequence needs to happen in FS mode before any other
+-01262          * programming occurs */
+-01263         if ((core_if->core_params->speed == DWC_SPEED_PARAM_FULL) &&
+-01264             (core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS)) {
+-01265                 /* If FS mode with FS PHY */
+-01266 
+-01267                 /* core_init() is now called on every switch so only call the
+-01268                  * following for the first time through. */
+-01269                 if (!core_if->phy_init_done) {
+-01270                         core_if->phy_init_done = 1;
+-01271                         DWC_DEBUGPL(DBG_CIL, "FS_PHY detected\n");
+-01272                         usbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg);
+-01273                         usbcfg.b.physel = 1;
+-01274                         DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32);
+-01275 
+-01276                         /* Reset after a PHY select */
+-01277                         dwc_otg_core_reset(core_if);
+-01278                 }
+-01279 
+-01280                 /* Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS.      Also
+-01281                  * do this on HNP Dev/Host mode switches (done in dev_init and
+-01282                  * host_init). */
+-01283                 if (dwc_otg_is_host_mode(core_if)) {
+-01284                         init_fslspclksel(core_if);
+-01285                 } else {
+-01286                         init_devspd(core_if);
+-01287                 }
+-01288 
+-01289                 if (core_if->core_params->i2c_enable) {
+-01290                         DWC_DEBUGPL(DBG_CIL, "FS_PHY Enabling I2c\n");
+-01291                         /* Program GUSBCFG.OtgUtmifsSel to I2C */
+-01292                         usbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg);
+-01293                         usbcfg.b.otgutmifssel = 1;
+-01294                         DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32);
+-01295 
+-01296                         /* Program GI2CCTL.I2CEn */
+-01297                         i2cctl.d32 = DWC_READ_REG32(&global_regs->gi2cctl);
+-01298                         i2cctl.b.i2cdevaddr = 1;
+-01299                         i2cctl.b.i2cen = 0;
+-01300                         DWC_WRITE_REG32(&global_regs->gi2cctl, i2cctl.d32);
+-01301                         i2cctl.b.i2cen = 1;
+-01302                         DWC_WRITE_REG32(&global_regs->gi2cctl, i2cctl.d32);
+-01303                 }
+-01304 
+-01305         } /* endif speed == DWC_SPEED_PARAM_FULL */
+-01306         else {
+-01307                 /* High speed PHY. */
+-01308                 if (!core_if->phy_init_done) {
+-01309                         core_if->phy_init_done = 1;
+-01310                         /* HS PHY parameters.  These parameters are preserved
+-01311                          * during soft reset so only program the first time.  Do
+-01312                          * a soft reset immediately after setting phyif.  */
+-01313 
+-01314                         if (core_if->core_params->phy_type == 2) {
+-01315                                 /* ULPI interface */
+-01316                                 usbcfg.b.ulpi_utmi_sel = 1;
+-01317                                 usbcfg.b.phyif = 0;
+-01318                                 usbcfg.b.ddrsel =
+-01319                                     core_if->core_params->phy_ulpi_ddr;
+-01320                         } else if (core_if->core_params->phy_type == 1) {
+-01321                                 /* UTMI+ interface */
+-01322                                 usbcfg.b.ulpi_utmi_sel = 0;
+-01323                                 if (core_if->core_params->phy_utmi_width == 16) {
+-01324                                         usbcfg.b.phyif = 1;
+-01325 
+-01326                                 } else {
+-01327                                         usbcfg.b.phyif = 0;
+-01328                                 }
+-01329                         } else {
+-01330                                 DWC_ERROR("FS PHY TYPE\n");
+-01331                         }
+-01332                         DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32);
+-01333                         /* Reset after setting the PHY parameters */
+-01334                         dwc_otg_core_reset(core_if);
+-01335                 }
+-01336         }
+-01337 
+-01338         if ((core_if->hwcfg2.b.hs_phy_type == 2) &&
+-01339             (core_if->hwcfg2.b.fs_phy_type == 1) &&
+-01340             (core_if->core_params->ulpi_fs_ls)) {
+-01341                 DWC_DEBUGPL(DBG_CIL, "Setting ULPI FSLS\n");
+-01342                 usbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg);
+-01343                 usbcfg.b.ulpi_fsls = 1;
+-01344                 usbcfg.b.ulpi_clk_sus_m = 1;
+-01345                 DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32);
+-01346         } else {
+-01347                 usbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg);
+-01348                 usbcfg.b.ulpi_fsls = 0;
+-01349                 usbcfg.b.ulpi_clk_sus_m = 0;
+-01350                 DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32);
+-01351         }
+-01352 
+-01353         /* Program the GAHBCFG Register. */
+-01354         switch (core_if->hwcfg2.b.architecture) {
+-01355 
+-01356         case DWC_SLAVE_ONLY_ARCH:
+-01357                 DWC_DEBUGPL(DBG_CIL, "Slave Only Mode\n");
+-01358                 ahbcfg.b.nptxfemplvl_txfemplvl =
+-01359                     DWC_GAHBCFG_TXFEMPTYLVL_HALFEMPTY;
+-01360                 ahbcfg.b.ptxfemplvl = DWC_GAHBCFG_TXFEMPTYLVL_HALFEMPTY;
+-01361                 core_if->dma_enable = 0;
+-01362                 core_if->dma_desc_enable = 0;
+-01363                 break;
+-01364 
+-01365         case DWC_EXT_DMA_ARCH:
+-01366                 DWC_DEBUGPL(DBG_CIL, "External DMA Mode\n");
+-01367                 {
+-01368                         uint8_t brst_sz = core_if->core_params->dma_burst_size;
+-01369                         ahbcfg.b.hburstlen = 0;
+-01370                         while (brst_sz > 1) {
+-01371                                 ahbcfg.b.hburstlen++;
+-01372                                 brst_sz >>= 1;
+-01373                         }
+-01374                 }
+-01375                 core_if->dma_enable = (core_if->core_params->dma_enable != 0);
+-01376                 core_if->dma_desc_enable =
+-01377                     (core_if->core_params->dma_desc_enable != 0);
+-01378                 break;
+-01379 
+-01380         case DWC_INT_DMA_ARCH:
+-01381                 DWC_DEBUGPL(DBG_CIL, "Internal DMA Mode\n");
+-01382                 /* Old value was DWC_GAHBCFG_INT_DMA_BURST_INCR - done for 
+-01383                   Host mode ISOC in issue fix - vahrama */
+-01384                 ahbcfg.b.hburstlen = DWC_GAHBCFG_INT_DMA_BURST_INCR4;
+-01385                 core_if->dma_enable = (core_if->core_params->dma_enable != 0);
+-01386                 core_if->dma_desc_enable =
+-01387                     (core_if->core_params->dma_desc_enable != 0);
+-01388                 break;
+-01389 
+-01390         }
+-01391         if (core_if->dma_enable) {
+-01392                 if (core_if->dma_desc_enable) {
+-01393                         DWC_PRINTF("Using Descriptor DMA mode\n");
+-01394                 } else {
+-01395                         DWC_PRINTF("Using Buffer DMA mode\n");
+-01396 
+-01397                 }
+-01398         } else {
+-01399                 DWC_PRINTF("Using Slave mode\n");
+-01400                 core_if->dma_desc_enable = 0;
+-01401         }
+-01402 
+-01403         if (core_if->core_params->ahb_single) {
+-01404                 ahbcfg.b.ahbsingle = 1;
+-01405         }
+-01406         
+-01407         ahbcfg.b.dmaenable = core_if->dma_enable;
+-01408         DWC_WRITE_REG32(&global_regs->gahbcfg, ahbcfg.d32);
+-01409 
+-01410         core_if->en_multiple_tx_fifo = core_if->hwcfg4.b.ded_fifo_en;
+-01411 
+-01412         core_if->pti_enh_enable = core_if->core_params->pti_enable != 0;
+-01413         core_if->multiproc_int_enable = core_if->core_params->mpi_enable;
+-01414         DWC_PRINTF("Periodic Transfer Interrupt Enhancement - %s\n",
+-01415                    ((core_if->pti_enh_enable) ? "enabled" : "disabled"));
+-01416         DWC_PRINTF("Multiprocessor Interrupt Enhancement - %s\n",
+-01417                    ((core_if->multiproc_int_enable) ? "enabled" : "disabled"));
+-01418 
+-01419         /*
+-01420          * Program the GUSBCFG register.
+-01421          */
+-01422         usbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg);
+-01423 
+-01424         switch (core_if->hwcfg2.b.op_mode) {
+-01425         case DWC_MODE_HNP_SRP_CAPABLE:
+-01426                 usbcfg.b.hnpcap = (core_if->core_params->otg_cap ==
+-01427                                    DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE);
+-01428                 usbcfg.b.srpcap = (core_if->core_params->otg_cap !=
+-01429                                    DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE);
+-01430                 break;
+-01431 
+-01432         case DWC_MODE_SRP_ONLY_CAPABLE:
+-01433                 usbcfg.b.hnpcap = 0;
+-01434                 usbcfg.b.srpcap = (core_if->core_params->otg_cap !=
+-01435                                    DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE);
+-01436                 break;
+-01437 
+-01438         case DWC_MODE_NO_HNP_SRP_CAPABLE:
+-01439                 usbcfg.b.hnpcap = 0;
+-01440                 usbcfg.b.srpcap = 0;
+-01441                 break;
+-01442 
+-01443         case DWC_MODE_SRP_CAPABLE_DEVICE:
+-01444                 usbcfg.b.hnpcap = 0;
+-01445                 usbcfg.b.srpcap = (core_if->core_params->otg_cap !=
+-01446                                    DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE);
+-01447                 break;
+-01448 
+-01449         case DWC_MODE_NO_SRP_CAPABLE_DEVICE:
+-01450                 usbcfg.b.hnpcap = 0;
+-01451                 usbcfg.b.srpcap = 0;
+-01452                 break;
+-01453 
+-01454         case DWC_MODE_SRP_CAPABLE_HOST:
+-01455                 usbcfg.b.hnpcap = 0;
+-01456                 usbcfg.b.srpcap = (core_if->core_params->otg_cap !=
+-01457                                    DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE);
+-01458                 break;
+-01459 
+-01460         case DWC_MODE_NO_SRP_CAPABLE_HOST:
+-01461                 usbcfg.b.hnpcap = 0;
+-01462                 usbcfg.b.srpcap = 0;
+-01463                 break;
+-01464         }
+-01465 
+-01466         DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32);
+-01467 
+-01468 #ifdef CONFIG_USB_DWC_OTG_LPM
+-01469         if (core_if->core_params->lpm_enable) {
+-01470                 glpmcfg_data_t lpmcfg = {.d32 = 0 };
+-01471 
+-01472                 /* To enable LPM support set lpm_cap_en bit */
+-01473                 lpmcfg.b.lpm_cap_en = 1;
+-01474 
+-01475                 /* Make AppL1Res ACK */
+-01476                 lpmcfg.b.appl_resp = 1;
+-01477 
+-01478                 /* Retry 3 times */
+-01479                 lpmcfg.b.retry_count = 3;
+-01480 
+-01481                 DWC_MODIFY_REG32(&core_if->core_global_regs->glpmcfg,
+-01482                                  0, lpmcfg.d32);
+-01483 
+-01484         }
+-01485 #endif
+-01486         if (core_if->core_params->ic_usb_cap) {
+-01487                 gusbcfg_data_t gusbcfg = {.d32 = 0 };
+-01488                 gusbcfg.b.ic_usb_cap = 1;
+-01489                 DWC_MODIFY_REG32(&core_if->core_global_regs->gusbcfg,
+-01490                                  0, gusbcfg.d32);
+-01491         }
+-01492         {
+-01493                 gotgctl_data_t gotgctl = {.d32 = 0 };
+-01494                 gotgctl.b.otgver = core_if->core_params->otg_ver;
+-01495                 DWC_MODIFY_REG32(&core_if->core_global_regs->gotgctl, 0,
+-01496                                  gotgctl.d32);
+-01497                 /* Set OTG version supported */
+-01498                 core_if->otg_ver = core_if->core_params->otg_ver;
+-01499                 DWC_PRINTF("OTG VER PARAM: %d, OTG VER FLAG: %d\n",
+-01500                            core_if->core_params->otg_ver, core_if->otg_ver);
+-01501         }
+-01502         
+-01503 
+-01504         /* Enable common interrupts */
+-01505         dwc_otg_enable_common_interrupts(core_if);
+-01506 
+-01507         /* Do device or host intialization based on mode during PCD
+-01508          * and HCD initialization  */
+-01509         if (dwc_otg_is_host_mode(core_if)) {
+-01510                 DWC_DEBUGPL(DBG_ANY, "Host Mode\n");
+-01511                 core_if->op_state = A_HOST;
+-01512         } else {
+-01513                 DWC_DEBUGPL(DBG_ANY, "Device Mode\n");
+-01514                 core_if->op_state = B_PERIPHERAL;
+-01515 #ifdef DWC_DEVICE_ONLY
+-01516                 dwc_otg_core_dev_init(core_if);
+-01517 #endif
+-01518         }
+-01519 }
+-01520 
+-01526 void dwc_otg_enable_device_interrupts(dwc_otg_core_if_t * core_if)
+-01527 {
+-01528         gintmsk_data_t intr_mask = {.d32 = 0 };
+-01529         dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
+-01530 
+-01531         DWC_DEBUGPL(DBG_CIL, "%s()\n", __func__);
+-01532 
+-01533         /* Disable all interrupts. */
+-01534         DWC_WRITE_REG32(&global_regs->gintmsk, 0);
+-01535 
+-01536         /* Clear any pending interrupts */
+-01537         DWC_WRITE_REG32(&global_regs->gintsts, 0xFFFFFFFF);
+-01538 
+-01539         /* Enable the common interrupts */
+-01540         dwc_otg_enable_common_interrupts(core_if);
+-01541 
+-01542         /* Enable interrupts */
+-01543         intr_mask.b.usbreset = 1;
+-01544         intr_mask.b.enumdone = 1;
+-01545         /* Disable Disconnect interrupt in Device mode */
+-01546         intr_mask.b.disconnect = 0;
+-01547 
+-01548         if (!core_if->multiproc_int_enable) {
+-01549                 intr_mask.b.inepintr = 1;
+-01550                 intr_mask.b.outepintr = 1;
+-01551         }
+-01552 
+-01553         intr_mask.b.erlysuspend = 1;
+-01554 
+-01555         if (core_if->en_multiple_tx_fifo == 0) {
+-01556                 intr_mask.b.epmismatch = 1;
+-01557         }
+-01558 
+-01559         //intr_mask.b.incomplisoout = 1;
+-01560         intr_mask.b.incomplisoin = 1;
+-01561         
+-01562 /* Enable the ignore frame number for ISOC xfers - MAS */
+-01563 /* Disable to support high bandwith ISOC transfers - manukz */
+-01564 #if 0
+-01565 #ifdef DWC_UTE_PER_IO
+-01566         if (core_if->dma_enable) {
+-01567                 if (core_if->dma_desc_enable) {
+-01568                         dctl_data_t dctl1 = {.d32 = 0 };
+-01569                         dctl1.b.ifrmnum = 1;
+-01570                         DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->
+-01571                                          dctl, 0, dctl1.d32);
+-01572                         DWC_DEBUG("----Enabled Ignore frame number (0x%08x)",
+-01573                                   DWC_READ_REG32(&core_if->dev_if->
+-01574                                                  dev_global_regs->dctl));
+-01575                 }
+-01576         }
+-01577 #endif
+-01578 #endif
+-01579 #ifdef DWC_EN_ISOC
+-01580         if (core_if->dma_enable) {
+-01581                 if (core_if->dma_desc_enable == 0) {
+-01582                         if (core_if->pti_enh_enable) {
+-01583                                 dctl_data_t dctl = {.d32 = 0 };
+-01584                                 dctl.b.ifrmnum = 1;
+-01585                                 DWC_MODIFY_REG32(&core_if->
+-01586                                                  dev_if->dev_global_regs->dctl,
+-01587                                                  0, dctl.d32);
+-01588                         } else {
+-01589                                 intr_mask.b.incomplisoin = 1;
+-01590                                 intr_mask.b.incomplisoout = 1;
+-01591                         }
+-01592                 }
+-01593         } else {
+-01594                 intr_mask.b.incomplisoin = 1;
+-01595                 intr_mask.b.incomplisoout = 1;
+-01596         }
+-01597 #endif /* DWC_EN_ISOC */
+-01598 
+-01600 #ifdef USE_PERIODIC_EP
+-01601         intr_mask.b.isooutdrop = 1;
+-01602         intr_mask.b.eopframe = 1;
+-01603         intr_mask.b.incomplisoin = 1;
+-01604         intr_mask.b.incomplisoout = 1;
+-01605 #endif
+-01606 
+-01607         DWC_MODIFY_REG32(&global_regs->gintmsk, intr_mask.d32, intr_mask.d32);
+-01608 
+-01609         DWC_DEBUGPL(DBG_CIL, "%s() gintmsk=%0x\n", __func__,
+-01610                     DWC_READ_REG32(&global_regs->gintmsk));
+-01611 }
+-01612 
+-01620 void dwc_otg_core_dev_init(dwc_otg_core_if_t * core_if)
+-01621 {
+-01622         int i;
+-01623         dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
+-01624         dwc_otg_dev_if_t *dev_if = core_if->dev_if;
+-01625         dwc_otg_core_params_t *params = core_if->core_params;
+-01626         dcfg_data_t dcfg = {.d32 = 0 };
+-01627         depctl_data_t diepctl = {.d32 = 0 };
+-01628         grstctl_t resetctl = {.d32 = 0 };
+-01629         uint32_t rx_fifo_size;
+-01630         fifosize_data_t nptxfifosize;
+-01631         fifosize_data_t txfifosize;
+-01632         dthrctl_data_t dthrctl;
+-01633         fifosize_data_t ptxfifosize;
+-01634         uint16_t rxfsiz, nptxfsiz;
+-01635         gdfifocfg_data_t gdfifocfg = {.d32 = 0 };
+-01636         hwcfg3_data_t hwcfg3 = {.d32 = 0 };
+-01637 
+-01638         /* Restart the Phy Clock */
+-01639         DWC_WRITE_REG32(core_if->pcgcctl, 0);
+-01640 
+-01641         /* Device configuration register */
+-01642         init_devspd(core_if);
+-01643         dcfg.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->dcfg);
+-01644         dcfg.b.descdma = (core_if->dma_desc_enable) ? 1 : 0;
+-01645         dcfg.b.perfrint = DWC_DCFG_FRAME_INTERVAL_80;
+-01646         /* Enable Device OUT NAK in case of DDMA mode*/
+-01647         if (core_if->core_params->dev_out_nak) {
+-01648                 dcfg.b.endevoutnak = 1;         
+-01649         }
+-01650 
+-01651         if (core_if->core_params->cont_on_bna) {
+-01652                 dctl_data_t dctl = {.d32 = 0 };
+-01653                 dctl.b.encontonbna = 1;
+-01654                 DWC_MODIFY_REG32(&dev_if->dev_global_regs->dctl, 0, dctl.d32);
+-01655         }
+-01656         
+-01657 
+-01658         DWC_WRITE_REG32(&dev_if->dev_global_regs->dcfg, dcfg.d32);
+-01659 
+-01660         /* Configure data FIFO sizes */
+-01661         if (core_if->hwcfg2.b.dynamic_fifo && params->enable_dynamic_fifo) {
+-01662                 DWC_DEBUGPL(DBG_CIL, "Total FIFO Size=%d\n",
+-01663                             core_if->total_fifo_size);
+-01664                 DWC_DEBUGPL(DBG_CIL, "Rx FIFO Size=%d\n",
+-01665                             params->dev_rx_fifo_size);
+-01666                 DWC_DEBUGPL(DBG_CIL, "NP Tx FIFO Size=%d\n",
+-01667                             params->dev_nperio_tx_fifo_size);
+-01668 
+-01669                 /* Rx FIFO */
+-01670                 DWC_DEBUGPL(DBG_CIL, "initial grxfsiz=%08x\n",
+-01671                             DWC_READ_REG32(&global_regs->grxfsiz));
+-01672 
+-01673 #ifdef DWC_UTE_CFI
+-01674                 core_if->pwron_rxfsiz = DWC_READ_REG32(&global_regs->grxfsiz);
+-01675                 core_if->init_rxfsiz = params->dev_rx_fifo_size;
+-01676 #endif
+-01677                 rx_fifo_size = params->dev_rx_fifo_size;
+-01678                 DWC_WRITE_REG32(&global_regs->grxfsiz, rx_fifo_size);
+-01679 
+-01680                 DWC_DEBUGPL(DBG_CIL, "new grxfsiz=%08x\n",
+-01681                             DWC_READ_REG32(&global_regs->grxfsiz));
+-01682 
+-01684                 core_if->p_tx_msk = 0;
+-01685 
+-01687                 core_if->tx_msk = 0;
+-01688 
+-01689                 if (core_if->en_multiple_tx_fifo == 0) {
+-01690                         /* Non-periodic Tx FIFO */
+-01691                         DWC_DEBUGPL(DBG_CIL, "initial gnptxfsiz=%08x\n",
+-01692                                     DWC_READ_REG32(&global_regs->gnptxfsiz));
+-01693 
+-01694                         nptxfifosize.b.depth = params->dev_nperio_tx_fifo_size;
+-01695                         nptxfifosize.b.startaddr = params->dev_rx_fifo_size;
+-01696 
+-01697                         DWC_WRITE_REG32(&global_regs->gnptxfsiz,
+-01698                                         nptxfifosize.d32);
+-01699 
+-01700                         DWC_DEBUGPL(DBG_CIL, "new gnptxfsiz=%08x\n",
+-01701                                     DWC_READ_REG32(&global_regs->gnptxfsiz));
+-01702 
+-01704                         /*
+-01705                          * Periodic Tx FIFOs These FIFOs are numbered from 1 to 15.
+-01706                          * Indexes of the FIFO size module parameters in the
+-01707                          * dev_perio_tx_fifo_size array and the FIFO size registers in
+-01708                          * the dptxfsiz array run from 0 to 14.
+-01709                          */
+-01711                         ptxfifosize.b.startaddr =
+-01712                             nptxfifosize.b.startaddr + nptxfifosize.b.depth;
+-01713                         for (i = 0; i < core_if->hwcfg4.b.num_dev_perio_in_ep; i++) {
+-01714                                 ptxfifosize.b.depth =
+-01715                                     params->dev_perio_tx_fifo_size[i];
+-01716                                 DWC_DEBUGPL(DBG_CIL,
+-01717                                             "initial dtxfsiz[%d]=%08x\n", i,
+-01718                                             DWC_READ_REG32(&global_regs->dtxfsiz
+-01719                                                            [i]));
+-01720                                 DWC_WRITE_REG32(&global_regs->dtxfsiz[i],
+-01721                                                 ptxfifosize.d32);
+-01722                                 DWC_DEBUGPL(DBG_CIL, "new dtxfsiz[%d]=%08x\n",
+-01723                                             i,
+-01724                                             DWC_READ_REG32(&global_regs->dtxfsiz
+-01725                                                            [i]));
+-01726                                 ptxfifosize.b.startaddr += ptxfifosize.b.depth;
+-01727                         }
+-01728                 } else {
+-01729                         /*
+-01730                          * Tx FIFOs These FIFOs are numbered from 1 to 15.
+-01731                          * Indexes of the FIFO size module parameters in the
+-01732                          * dev_tx_fifo_size array and the FIFO size registers in
+-01733                          * the dtxfsiz array run from 0 to 14.
+-01734                          */
+-01735 
+-01736                         /* Non-periodic Tx FIFO */
+-01737                         DWC_DEBUGPL(DBG_CIL, "initial gnptxfsiz=%08x\n",
+-01738                                     DWC_READ_REG32(&global_regs->gnptxfsiz));
+-01739 
+-01740 #ifdef DWC_UTE_CFI
+-01741                         core_if->pwron_gnptxfsiz =
+-01742                             (DWC_READ_REG32(&global_regs->gnptxfsiz) >> 16);
+-01743                         core_if->init_gnptxfsiz =
+-01744                             params->dev_nperio_tx_fifo_size;
+-01745 #endif
+-01746                         nptxfifosize.b.depth = params->dev_nperio_tx_fifo_size;
+-01747                         nptxfifosize.b.startaddr = params->dev_rx_fifo_size;
+-01748 
+-01749                         DWC_WRITE_REG32(&global_regs->gnptxfsiz,
+-01750                                         nptxfifosize.d32);
+-01751 
+-01752                         DWC_DEBUGPL(DBG_CIL, "new gnptxfsiz=%08x\n",
+-01753                                     DWC_READ_REG32(&global_regs->gnptxfsiz));
+-01754 
+-01755                         txfifosize.b.startaddr =
+-01756                             nptxfifosize.b.startaddr + nptxfifosize.b.depth;
+-01757 
+-01758                         for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {
+-01759 
+-01760                                 txfifosize.b.depth =
+-01761                                     params->dev_tx_fifo_size[i];
+-01762 
+-01763                                 DWC_DEBUGPL(DBG_CIL,
+-01764                                             "initial dtxfsiz[%d]=%08x\n",
+-01765                                             i,
+-01766                                             DWC_READ_REG32(&global_regs->dtxfsiz
+-01767                                                            [i]));
+-01768 
+-01769 #ifdef DWC_UTE_CFI
+-01770                                 core_if->pwron_txfsiz[i] =
+-01771                                     (DWC_READ_REG32
+-01772                                      (&global_regs->dtxfsiz[i]) >> 16);
+-01773                                 core_if->init_txfsiz[i] =
+-01774                                     params->dev_tx_fifo_size[i];
+-01775 #endif
+-01776                                 DWC_WRITE_REG32(&global_regs->dtxfsiz[i],
+-01777                                                 txfifosize.d32);
+-01778 
+-01779                                 DWC_DEBUGPL(DBG_CIL,
+-01780                                             "new dtxfsiz[%d]=%08x\n",
+-01781                                             i,
+-01782                                             DWC_READ_REG32(&global_regs->dtxfsiz
+-01783                                                            [i]));
+-01784 
+-01785                                 txfifosize.b.startaddr += txfifosize.b.depth;
+-01786                         }
+-01787                         /* Calculating DFIFOCFG for Device mode to include RxFIFO and NPTXFIFO */
+-01788                         gdfifocfg.d32 = DWC_READ_REG32(&global_regs->gdfifocfg);
+-01789                         hwcfg3.d32 = DWC_READ_REG32(&global_regs->ghwcfg3);
+-01790                         gdfifocfg.b.gdfifocfg = (DWC_READ_REG32(&global_regs->ghwcfg3) >> 16);
+-01791                         DWC_WRITE_REG32(&global_regs->gdfifocfg, gdfifocfg.d32);
+-01792                         rxfsiz = (DWC_READ_REG32(&global_regs->grxfsiz) & 0x0000ffff);
+-01793                         nptxfsiz = (DWC_READ_REG32(&global_regs->gnptxfsiz) >> 16);
+-01794                         gdfifocfg.b.epinfobase = rxfsiz + nptxfsiz;
+-01795                         DWC_WRITE_REG32(&global_regs->gdfifocfg, gdfifocfg.d32);
+-01796                 }
+-01797         }
+-01798 
+-01799         /* Flush the FIFOs */
+-01800         dwc_otg_flush_tx_fifo(core_if, 0x10);   /* all Tx FIFOs */
+-01801         dwc_otg_flush_rx_fifo(core_if);
+-01802 
+-01803         /* Flush the Learning Queue. */
+-01804         resetctl.b.intknqflsh = 1;
+-01805         DWC_WRITE_REG32(&core_if->core_global_regs->grstctl, resetctl.d32);
+-01806 
+-01807         if (!core_if->core_params->en_multiple_tx_fifo && core_if->dma_enable) {
+-01808                 core_if->start_predict = 0;
+-01809                 for (i = 0; i<= core_if->dev_if->num_in_eps; ++i) {
+-01810                         core_if->nextep_seq[i] = 0xff;  // 0xff - EP not active
+-01811                 }
+-01812                 core_if->nextep_seq[0] = 0;     
+-01813                 core_if->first_in_nextep_seq = 0;
+-01814                 diepctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[0]->diepctl);
+-01815                 diepctl.b.nextep = 0;
+-01816                 DWC_WRITE_REG32(&dev_if->in_ep_regs[0]->diepctl, diepctl.d32);
+-01817                 
+-01818                 /* Update IN Endpoint Mismatch Count by active IN NP EP count + 1 */
+-01819                 dcfg.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->dcfg);
+-01820                 dcfg.b.epmscnt = 2;
+-01821                 DWC_WRITE_REG32(&dev_if->dev_global_regs->dcfg, dcfg.d32);
+-01822 
+-01823                 DWC_DEBUGPL(DBG_CILV,"%s first_in_nextep_seq= %2d; nextep_seq[]:\n", 
+-01824                         __func__, core_if->first_in_nextep_seq);
+-01825                 for (i=0; i <= core_if->dev_if->num_in_eps; i++) {
+-01826                         DWC_DEBUGPL(DBG_CILV, "%2d ", core_if->nextep_seq[i]);
+-01827                 }
+-01828                 DWC_DEBUGPL(DBG_CILV,"\n");
+-01829         }
+-01830         
+-01831         /* Clear all pending Device Interrupts */
+-01835         if (core_if->multiproc_int_enable) {
+-01836                 for (i = 0; i < core_if->dev_if->num_in_eps; ++i) {
+-01837                         DWC_WRITE_REG32(&dev_if->
+-01838                                         dev_global_regs->diepeachintmsk[i], 0);
+-01839                 }
+-01840 
+-01841                 for (i = 0; i < core_if->dev_if->num_out_eps; ++i) {
+-01842                         DWC_WRITE_REG32(&dev_if->
+-01843                                         dev_global_regs->doepeachintmsk[i], 0);
+-01844                 }
+-01845 
+-01846                 DWC_WRITE_REG32(&dev_if->dev_global_regs->deachint, 0xFFFFFFFF);
+-01847                 DWC_WRITE_REG32(&dev_if->dev_global_regs->deachintmsk, 0);
+-01848         } else {
+-01849                 DWC_WRITE_REG32(&dev_if->dev_global_regs->diepmsk, 0);
+-01850                 DWC_WRITE_REG32(&dev_if->dev_global_regs->doepmsk, 0);
+-01851                 DWC_WRITE_REG32(&dev_if->dev_global_regs->daint, 0xFFFFFFFF);
+-01852                 DWC_WRITE_REG32(&dev_if->dev_global_regs->daintmsk, 0);
+-01853         }
+-01854 
+-01855         for (i = 0; i <= dev_if->num_in_eps; i++) {
+-01856                 depctl_data_t depctl;
+-01857                 depctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl);
+-01858                 if (depctl.b.epena) {
+-01859                         depctl.d32 = 0;
+-01860                         depctl.b.epdis = 1;
+-01861                         depctl.b.snak = 1;
+-01862                 } else {
+-01863                         depctl.d32 = 0;
+-01864                 }
+-01865 
+-01866                 DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->diepctl, depctl.d32);
+-01867 
+-01868                 DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->dieptsiz, 0);
+-01869                 DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->diepdma, 0);
+-01870                 DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->diepint, 0xFF);
+-01871         }
+-01872 
+-01873         for (i = 0; i <= dev_if->num_out_eps; i++) {
+-01874                 depctl_data_t depctl;
+-01875                 depctl.d32 = DWC_READ_REG32(&dev_if->out_ep_regs[i]->doepctl);
+-01876                 if (depctl.b.epena) {
+-01877                         depctl.d32 = 0;
+-01878                         depctl.b.epdis = 1;
+-01879                         depctl.b.snak = 1;
+-01880                 } else {
+-01881                         depctl.d32 = 0;
+-01882                 }
+-01883 
+-01884                 DWC_WRITE_REG32(&dev_if->out_ep_regs[i]->doepctl, depctl.d32);
+-01885 
+-01886                 DWC_WRITE_REG32(&dev_if->out_ep_regs[i]->doeptsiz, 0);
+-01887                 DWC_WRITE_REG32(&dev_if->out_ep_regs[i]->doepdma, 0);
+-01888                 DWC_WRITE_REG32(&dev_if->out_ep_regs[i]->doepint, 0xFF);
+-01889         }
+-01890 
+-01891         if (core_if->en_multiple_tx_fifo && core_if->dma_enable) {
+-01892                 dev_if->non_iso_tx_thr_en = params->thr_ctl & 0x1;
+-01893                 dev_if->iso_tx_thr_en = (params->thr_ctl >> 1) & 0x1;
+-01894                 dev_if->rx_thr_en = (params->thr_ctl >> 2) & 0x1;
+-01895 
+-01896                 dev_if->rx_thr_length = params->rx_thr_length;
+-01897                 dev_if->tx_thr_length = params->tx_thr_length;
+-01898 
+-01899                 dev_if->setup_desc_index = 0;
+-01900 
+-01901                 dthrctl.d32 = 0;
+-01902                 dthrctl.b.non_iso_thr_en = dev_if->non_iso_tx_thr_en;
+-01903                 dthrctl.b.iso_thr_en = dev_if->iso_tx_thr_en;
+-01904                 dthrctl.b.tx_thr_len = dev_if->tx_thr_length;
+-01905                 dthrctl.b.rx_thr_en = dev_if->rx_thr_en;
+-01906                 dthrctl.b.rx_thr_len = dev_if->rx_thr_length;
+-01907                 dthrctl.b.ahb_thr_ratio = params->ahb_thr_ratio;
+-01908 
+-01909                 DWC_WRITE_REG32(&dev_if->dev_global_regs->dtknqr3_dthrctl,
+-01910                                 dthrctl.d32);
+-01911 
+-01912                 DWC_DEBUGPL(DBG_CIL,
+-01913                             "Non ISO Tx Thr - %d\nISO Tx Thr - %d\nRx Thr - %d\nTx Thr Len - %d\nRx Thr Len - %d\n",
+-01914                             dthrctl.b.non_iso_thr_en, dthrctl.b.iso_thr_en,
+-01915                             dthrctl.b.rx_thr_en, dthrctl.b.tx_thr_len,
+-01916                             dthrctl.b.rx_thr_len);
+-01917 
+-01918         }
+-01919 
+-01920         dwc_otg_enable_device_interrupts(core_if);
+-01921 
+-01922         {
+-01923                 diepmsk_data_t msk = {.d32 = 0 };
+-01924                 msk.b.txfifoundrn = 1;
+-01925                 if (core_if->multiproc_int_enable) {
+-01926                         DWC_MODIFY_REG32(&dev_if->
+-01927                                          dev_global_regs->diepeachintmsk[0],
+-01928                                          msk.d32, msk.d32);
+-01929                 } else {
+-01930                         DWC_MODIFY_REG32(&dev_if->dev_global_regs->diepmsk,
+-01931                                          msk.d32, msk.d32);
+-01932                 }
+-01933         }
+-01934 
+-01935         if (core_if->multiproc_int_enable) {
+-01936                 /* Set NAK on Babble */
+-01937                 dctl_data_t dctl = {.d32 = 0 };
+-01938                 dctl.b.nakonbble = 1;
+-01939                 DWC_MODIFY_REG32(&dev_if->dev_global_regs->dctl, 0, dctl.d32);
+-01940         }
+-01941 
+-01942         if (core_if->snpsid >= OTG_CORE_REV_2_94a) {
+-01943                 dctl_data_t dctl = {.d32 = 0 };
+-01944                 dctl.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->dctl);
+-01945                 dctl.b.sftdiscon = 0;
+-01946                 DWC_WRITE_REG32(&dev_if->dev_global_regs->dctl, dctl.d32);
+-01947         }
+-01948 }
+-01949 
+-01955 void dwc_otg_enable_host_interrupts(dwc_otg_core_if_t * core_if)
+-01956 {
+-01957         dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
+-01958         gintmsk_data_t intr_mask = {.d32 = 0 };
+-01959 
+-01960         DWC_DEBUGPL(DBG_CIL, "%s()\n", __func__);
+-01961 
+-01962         /* Disable all interrupts. */
+-01963         DWC_WRITE_REG32(&global_regs->gintmsk, 0);
+-01964 
+-01965         /* Clear any pending interrupts. */
+-01966         DWC_WRITE_REG32(&global_regs->gintsts, 0xFFFFFFFF);
+-01967 
+-01968         /* Enable the common interrupts */
+-01969         dwc_otg_enable_common_interrupts(core_if);
+-01970 
+-01971         /*
+-01972          * Enable host mode interrupts without disturbing common
+-01973          * interrupts.
+-01974          */
+-01975 
+-01976         intr_mask.b.disconnect = 1;
+-01977         intr_mask.b.portintr = 1;
+-01978         intr_mask.b.hcintr = 1;
+-01979 
+-01980         DWC_MODIFY_REG32(&global_regs->gintmsk, intr_mask.d32, intr_mask.d32);
+-01981 }
+-01982 
+-01988 void dwc_otg_disable_host_interrupts(dwc_otg_core_if_t * core_if)
+-01989 {
+-01990         dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
+-01991         gintmsk_data_t intr_mask = {.d32 = 0 };
+-01992 
+-01993         DWC_DEBUGPL(DBG_CILV, "%s()\n", __func__);
+-01994 
+-01995         /*
+-01996          * Disable host mode interrupts without disturbing common
+-01997          * interrupts.
+-01998          */
+-01999         intr_mask.b.sofintr = 1;
+-02000         intr_mask.b.portintr = 1;
+-02001         intr_mask.b.hcintr = 1;
+-02002         intr_mask.b.ptxfempty = 1;
+-02003         intr_mask.b.nptxfempty = 1;
+-02004 
+-02005         DWC_MODIFY_REG32(&global_regs->gintmsk, intr_mask.d32, 0);
+-02006 }
+-02007 
+-02019 void dwc_otg_core_host_init(dwc_otg_core_if_t * core_if)
+-02020 {
+-02021         dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
+-02022         dwc_otg_host_if_t *host_if = core_if->host_if;
+-02023         dwc_otg_core_params_t *params = core_if->core_params;
+-02024         hprt0_data_t hprt0 = {.d32 = 0 };
+-02025         fifosize_data_t nptxfifosize;
+-02026         fifosize_data_t ptxfifosize;
+-02027         uint16_t rxfsiz, nptxfsiz, hptxfsiz;
+-02028         gdfifocfg_data_t gdfifocfg = {.d32 = 0 };
+-02029         int i;
+-02030         hcchar_data_t hcchar;
+-02031         hcfg_data_t hcfg;
+-02032         hfir_data_t hfir;
+-02033         dwc_otg_hc_regs_t *hc_regs;
+-02034         int num_channels;
+-02035         gotgctl_data_t gotgctl = {.d32 = 0 };
+-02036 
+-02037         DWC_DEBUGPL(DBG_CILV, "%s(%p)\n", __func__, core_if);
+-02038 
+-02039         /* Restart the Phy Clock */
+-02040         DWC_WRITE_REG32(core_if->pcgcctl, 0);
+-02041 
+-02042         /* Initialize Host Configuration Register */
+-02043         init_fslspclksel(core_if);
+-02044         if (core_if->core_params->speed == DWC_SPEED_PARAM_FULL) {
+-02045                 hcfg.d32 = DWC_READ_REG32(&host_if->host_global_regs->hcfg);
+-02046                 hcfg.b.fslssupp = 1;
+-02047                 DWC_WRITE_REG32(&host_if->host_global_regs->hcfg, hcfg.d32);
+-02048 
+-02049         }
+-02050 
+-02051         /* This bit allows dynamic reloading of the HFIR register
+-02052          * during runtime. This bit needs to be programmed during 
+-02053          * initial configuration and its value must not be changed
+-02054          * during runtime.*/
+-02055         if (core_if->core_params->reload_ctl == 1) {
+-02056                 hfir.d32 = DWC_READ_REG32(&host_if->host_global_regs->hfir);
+-02057                 hfir.b.hfirrldctrl = 1;
+-02058                 DWC_WRITE_REG32(&host_if->host_global_regs->hfir, hfir.d32);
+-02059         }
+-02060 
+-02061         if (core_if->core_params->dma_desc_enable) {
+-02062                 uint8_t op_mode = core_if->hwcfg2.b.op_mode;
+-02063                 if (!
+-02064                     (core_if->hwcfg4.b.desc_dma
+-02065                      && (core_if->snpsid >= OTG_CORE_REV_2_90a)
+-02066                      && ((op_mode == DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG)
+-02067                          || (op_mode == DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG)
+-02068                          || (op_mode ==
+-02069                              DWC_HWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE_OTG)
+-02070                          || (op_mode == DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST)
+-02071                          || (op_mode ==
+-02072                              DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST)))) {
+-02073 
+-02074                         DWC_ERROR("Host can't operate in Descriptor DMA mode.\n"
+-02075                                   "Either core version is below 2.90a or "
+-02076                                   "GHWCFG2, GHWCFG4 registers' values do not allow Descriptor DMA in host mode.\n"
+-02077                                   "To run the driver in Buffer DMA host mode set dma_desc_enable "
+-02078                                   "module parameter to 0.\n");
+-02079                         return;
+-02080                 }
+-02081                 hcfg.d32 = DWC_READ_REG32(&host_if->host_global_regs->hcfg);
+-02082                 hcfg.b.descdma = 1;
+-02083                 DWC_WRITE_REG32(&host_if->host_global_regs->hcfg, hcfg.d32);
+-02084         }
+-02085 
+-02086         /* Configure data FIFO sizes */
+-02087         if (core_if->hwcfg2.b.dynamic_fifo && params->enable_dynamic_fifo) {
+-02088                 DWC_DEBUGPL(DBG_CIL, "Total FIFO Size=%d\n",
+-02089                             core_if->total_fifo_size);
+-02090                 DWC_DEBUGPL(DBG_CIL, "Rx FIFO Size=%d\n",
+-02091                             params->host_rx_fifo_size);
+-02092                 DWC_DEBUGPL(DBG_CIL, "NP Tx FIFO Size=%d\n",
+-02093                             params->host_nperio_tx_fifo_size);
+-02094                 DWC_DEBUGPL(DBG_CIL, "P Tx FIFO Size=%d\n",
+-02095                             params->host_perio_tx_fifo_size);
+-02096 
+-02097                 /* Rx FIFO */
+-02098                 DWC_DEBUGPL(DBG_CIL, "initial grxfsiz=%08x\n",
+-02099                             DWC_READ_REG32(&global_regs->grxfsiz));
+-02100                 DWC_WRITE_REG32(&global_regs->grxfsiz,
+-02101                                 params->host_rx_fifo_size);
+-02102                 DWC_DEBUGPL(DBG_CIL, "new grxfsiz=%08x\n",
+-02103                             DWC_READ_REG32(&global_regs->grxfsiz));
+-02104 
+-02105                 /* Non-periodic Tx FIFO */
+-02106                 DWC_DEBUGPL(DBG_CIL, "initial gnptxfsiz=%08x\n",
+-02107                             DWC_READ_REG32(&global_regs->gnptxfsiz));
+-02108                 nptxfifosize.b.depth = params->host_nperio_tx_fifo_size;
+-02109                 nptxfifosize.b.startaddr = params->host_rx_fifo_size;
+-02110                 DWC_WRITE_REG32(&global_regs->gnptxfsiz, nptxfifosize.d32);
+-02111                 DWC_DEBUGPL(DBG_CIL, "new gnptxfsiz=%08x\n",
+-02112                             DWC_READ_REG32(&global_regs->gnptxfsiz));
+-02113 
+-02114                 /* Periodic Tx FIFO */
+-02115                 DWC_DEBUGPL(DBG_CIL, "initial hptxfsiz=%08x\n",
+-02116                             DWC_READ_REG32(&global_regs->hptxfsiz));
+-02117                 ptxfifosize.b.depth = params->host_perio_tx_fifo_size;
+-02118                 ptxfifosize.b.startaddr =
+-02119                     nptxfifosize.b.startaddr + nptxfifosize.b.depth;
+-02120                 DWC_WRITE_REG32(&global_regs->hptxfsiz, ptxfifosize.d32);
+-02121                 DWC_DEBUGPL(DBG_CIL, "new hptxfsiz=%08x\n",
+-02122                             DWC_READ_REG32(&global_regs->hptxfsiz));
+-02123                 
+-02124                 if (core_if->en_multiple_tx_fifo) {
+-02125                         /* Global DFIFOCFG calculation for Host mode - include RxFIFO, NPTXFIFO and HPTXFIFO */
+-02126                         gdfifocfg.d32 = DWC_READ_REG32(&global_regs->gdfifocfg);
+-02127                         rxfsiz = (DWC_READ_REG32(&global_regs->grxfsiz) & 0x0000ffff);
+-02128                         nptxfsiz = (DWC_READ_REG32(&global_regs->gnptxfsiz) >> 16);
+-02129                         hptxfsiz = (DWC_READ_REG32(&global_regs->hptxfsiz) >> 16);
+-02130                         gdfifocfg.b.epinfobase = rxfsiz + nptxfsiz + hptxfsiz;
+-02131                         DWC_WRITE_REG32(&global_regs->gdfifocfg, gdfifocfg.d32);
+-02132                 }
+-02133         }
+-02134 
+-02135         /* TODO - check this */
+-02136         /* Clear Host Set HNP Enable in the OTG Control Register */
+-02137         gotgctl.b.hstsethnpen = 1;
+-02138         DWC_MODIFY_REG32(&global_regs->gotgctl, gotgctl.d32, 0);
+-02139         /* Make sure the FIFOs are flushed. */
+-02140         dwc_otg_flush_tx_fifo(core_if, 0x10 /* all TX FIFOs */ );
+-02141         dwc_otg_flush_rx_fifo(core_if);
+-02142 
+-02143         /* Clear Host Set HNP Enable in the OTG Control Register */
+-02144         gotgctl.b.hstsethnpen = 1;
+-02145         DWC_MODIFY_REG32(&global_regs->gotgctl, gotgctl.d32, 0);
+-02146 
+-02147         if (!core_if->core_params->dma_desc_enable) {
+-02148                 /* Flush out any leftover queued requests. */
+-02149                 num_channels = core_if->core_params->host_channels;
+-02150 
+-02151                 for (i = 0; i < num_channels; i++) {
+-02152                         hc_regs = core_if->host_if->hc_regs[i];
+-02153                         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
+-02154                         hcchar.b.chen = 0;
+-02155                         hcchar.b.chdis = 1;
+-02156                         hcchar.b.epdir = 0;
+-02157                         DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
+-02158                 }
+-02159 
+-02160                 /* Halt all channels to put them into a known state. */
+-02161                 for (i = 0; i < num_channels; i++) {
+-02162                         int count = 0;
+-02163                         hc_regs = core_if->host_if->hc_regs[i];
+-02164                         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
+-02165                         hcchar.b.chen = 1;
+-02166                         hcchar.b.chdis = 1;
+-02167                         hcchar.b.epdir = 0;
+-02168                         DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
+-02169                         DWC_DEBUGPL(DBG_HCDV, "%s: Halt channel %d\n", __func__, i);
+-02170                         do {
+-02171                                 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
+-02172                                 if (++count > 1000) {
+-02173                                         DWC_ERROR
+-02174                                             ("%s: Unable to clear halt on channel %d\n",
+-02175                                              __func__, i);
+-02176                                         break;
+-02177                                 }
+-02178                                 dwc_udelay(1);
+-02179                         } while (hcchar.b.chen);
+-02180                 }
+-02181         }
+-02182 
+-02183         /* Turn on the vbus power. */
+-02184         DWC_PRINTF("Init: Port Power? op_state=%d\n", core_if->op_state);
+-02185         if (core_if->op_state == A_HOST) {
+-02186                 hprt0.d32 = dwc_otg_read_hprt0(core_if);
+-02187                 DWC_PRINTF("Init: Power Port (%d)\n", hprt0.b.prtpwr);
+-02188                 if (hprt0.b.prtpwr == 0) {
+-02189                         hprt0.b.prtpwr = 1;
+-02190                         DWC_WRITE_REG32(host_if->hprt0, hprt0.d32);
+-02191                 }
+-02192         }
+-02193 
+-02194         dwc_otg_enable_host_interrupts(core_if);
+-02195 }
+-02196 
+-02206 void dwc_otg_hc_init(dwc_otg_core_if_t * core_if, dwc_hc_t * hc)
+-02207 {
+-02208         uint32_t intr_enable;
+-02209         hcintmsk_data_t hc_intr_mask;
+-02210         gintmsk_data_t gintmsk = {.d32 = 0 };
+-02211         hcchar_data_t hcchar;
+-02212         hcsplt_data_t hcsplt;
+-02213 
+-02214         uint8_t hc_num = hc->hc_num;
+-02215         dwc_otg_host_if_t *host_if = core_if->host_if;
+-02216         dwc_otg_hc_regs_t *hc_regs = host_if->hc_regs[hc_num];
+-02217 
+-02218         /* Clear old interrupt conditions for this host channel. */
+-02219         hc_intr_mask.d32 = 0xFFFFFFFF;
+-02220         hc_intr_mask.b.reserved14_31 = 0;
+-02221         DWC_WRITE_REG32(&hc_regs->hcint, hc_intr_mask.d32);
+-02222 
+-02223         /* Enable channel interrupts required for this transfer. */
+-02224         hc_intr_mask.d32 = 0;
+-02225         hc_intr_mask.b.chhltd = 1;
+-02226         if (core_if->dma_enable) {
+-02227                 /* For Descriptor DMA mode core halts the channel on AHB error. Interrupt is not required */
+-02228                 if (!core_if->dma_desc_enable)
+-02229                         hc_intr_mask.b.ahberr = 1;
+-02230                 else {
+-02231                         if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC)
+-02232                                 hc_intr_mask.b.xfercompl = 1;
+-02233                 }
+-02234 
+-02235                 if (hc->error_state && !hc->do_split &&
+-02236                     hc->ep_type != DWC_OTG_EP_TYPE_ISOC) {
+-02237                         hc_intr_mask.b.ack = 1;
+-02238                         if (hc->ep_is_in) {
+-02239                                 hc_intr_mask.b.datatglerr = 1;
+-02240                                 if (hc->ep_type != DWC_OTG_EP_TYPE_INTR) {
+-02241                                         hc_intr_mask.b.nak = 1;
+-02242                                 }
+-02243                         }
+-02244                 }
+-02245         } else {
+-02246                 switch (hc->ep_type) {
+-02247                 case DWC_OTG_EP_TYPE_CONTROL:
+-02248                 case DWC_OTG_EP_TYPE_BULK:
+-02249                         hc_intr_mask.b.xfercompl = 1;
+-02250                         hc_intr_mask.b.stall = 1;
+-02251                         hc_intr_mask.b.xacterr = 1;
+-02252                         hc_intr_mask.b.datatglerr = 1;
+-02253                         if (hc->ep_is_in) {
+-02254                                 hc_intr_mask.b.bblerr = 1;
+-02255                         } else {
+-02256                                 hc_intr_mask.b.nak = 1;
+-02257                                 hc_intr_mask.b.nyet = 1;
+-02258                                 if (hc->do_ping) {
+-02259                                         hc_intr_mask.b.ack = 1;
+-02260                                 }
+-02261                         }
+-02262 
+-02263                         if (hc->do_split) {
+-02264                                 hc_intr_mask.b.nak = 1;
+-02265                                 if (hc->complete_split) {
+-02266                                         hc_intr_mask.b.nyet = 1;
+-02267                                 } else {
+-02268                                         hc_intr_mask.b.ack = 1;
+-02269                                 }
+-02270                         }
+-02271 
+-02272                         if (hc->error_state) {
+-02273                                 hc_intr_mask.b.ack = 1;
+-02274                         }
+-02275                         break;
+-02276                 case DWC_OTG_EP_TYPE_INTR:
+-02277                         hc_intr_mask.b.xfercompl = 1;
+-02278                         hc_intr_mask.b.nak = 1;
+-02279                         hc_intr_mask.b.stall = 1;
+-02280                         hc_intr_mask.b.xacterr = 1;
+-02281                         hc_intr_mask.b.datatglerr = 1;
+-02282                         hc_intr_mask.b.frmovrun = 1;
+-02283 
+-02284                         if (hc->ep_is_in) {
+-02285                                 hc_intr_mask.b.bblerr = 1;
+-02286                         }
+-02287                         if (hc->error_state) {
+-02288                                 hc_intr_mask.b.ack = 1;
+-02289                         }
+-02290                         if (hc->do_split) {
+-02291                                 if (hc->complete_split) {
+-02292                                         hc_intr_mask.b.nyet = 1;
+-02293                                 } else {
+-02294                                         hc_intr_mask.b.ack = 1;
+-02295                                 }
+-02296                         }
+-02297                         break;
+-02298                 case DWC_OTG_EP_TYPE_ISOC:
+-02299                         hc_intr_mask.b.xfercompl = 1;
+-02300                         hc_intr_mask.b.frmovrun = 1;
+-02301                         hc_intr_mask.b.ack = 1;
+-02302 
+-02303                         if (hc->ep_is_in) {
+-02304                                 hc_intr_mask.b.xacterr = 1;
+-02305                                 hc_intr_mask.b.bblerr = 1;
+-02306                         }
+-02307                         break;
+-02308                 }
+-02309         }
+-02310         DWC_WRITE_REG32(&hc_regs->hcintmsk, hc_intr_mask.d32);
+-02311 
+-02312         /* Enable the top level host channel interrupt. */
+-02313         intr_enable = (1 << hc_num);
+-02314         DWC_MODIFY_REG32(&host_if->host_global_regs->haintmsk, 0, intr_enable);
+-02315 
+-02316         /* Make sure host channel interrupts are enabled. */
+-02317         gintmsk.b.hcintr = 1;
+-02318         DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, 0, gintmsk.d32);
+-02319 
+-02320         /*
+-02321          * Program the HCCHARn register with the endpoint characteristics for
+-02322          * the current transfer.
+-02323          */
+-02324         hcchar.d32 = 0;
+-02325         hcchar.b.devaddr = hc->dev_addr;
+-02326         hcchar.b.epnum = hc->ep_num;
+-02327         hcchar.b.epdir = hc->ep_is_in;
+-02328         hcchar.b.lspddev = (hc->speed == DWC_OTG_EP_SPEED_LOW);
+-02329         hcchar.b.eptype = hc->ep_type;
+-02330         hcchar.b.mps = hc->max_packet;
+-02331 
+-02332         DWC_WRITE_REG32(&host_if->hc_regs[hc_num]->hcchar, hcchar.d32);
+-02333 
+-02334         DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num);
+-02335         DWC_DEBUGPL(DBG_HCDV, "  Dev Addr: %d\n", hcchar.b.devaddr);
+-02336         DWC_DEBUGPL(DBG_HCDV, "  Ep Num: %d\n", hcchar.b.epnum);
+-02337         DWC_DEBUGPL(DBG_HCDV, "  Is In: %d\n", hcchar.b.epdir);
+-02338         DWC_DEBUGPL(DBG_HCDV, "  Is Low Speed: %d\n", hcchar.b.lspddev);
+-02339         DWC_DEBUGPL(DBG_HCDV, "  Ep Type: %d\n", hcchar.b.eptype);
+-02340         DWC_DEBUGPL(DBG_HCDV, "  Max Pkt: %d\n", hcchar.b.mps);
+-02341         DWC_DEBUGPL(DBG_HCDV, "  Multi Cnt: %d\n", hcchar.b.multicnt);
+-02342 
+-02343         /*
+-02344          * Program the HCSPLIT register for SPLITs
+-02345          */
+-02346         hcsplt.d32 = 0;
+-02347         if (hc->do_split) {
+-02348                 DWC_DEBUGPL(DBG_HCDV, "Programming HC %d with split --> %s\n",
+-02349                             hc->hc_num,
+-02350                             hc->complete_split ? "CSPLIT" : "SSPLIT");
+-02351                 hcsplt.b.compsplt = hc->complete_split;
+-02352                 hcsplt.b.xactpos = hc->xact_pos;
+-02353                 hcsplt.b.hubaddr = hc->hub_addr;
+-02354                 hcsplt.b.prtaddr = hc->port_addr;
+-02355                 DWC_DEBUGPL(DBG_HCDV, "   comp split %d\n", hc->complete_split);
+-02356                 DWC_DEBUGPL(DBG_HCDV, "   xact pos %d\n", hc->xact_pos);
+-02357                 DWC_DEBUGPL(DBG_HCDV, "   hub addr %d\n", hc->hub_addr);
+-02358                 DWC_DEBUGPL(DBG_HCDV, "   port addr %d\n", hc->port_addr);
+-02359                 DWC_DEBUGPL(DBG_HCDV, "   is_in %d\n", hc->ep_is_in);
+-02360                 DWC_DEBUGPL(DBG_HCDV, "   Max Pkt: %d\n", hcchar.b.mps);
+-02361                 DWC_DEBUGPL(DBG_HCDV, "   xferlen: %d\n", hc->xfer_len);
+-02362         }
+-02363         DWC_WRITE_REG32(&host_if->hc_regs[hc_num]->hcsplt, hcsplt.d32);
+-02364 
+-02365 }
+-02366 
+-02394 void dwc_otg_hc_halt(dwc_otg_core_if_t * core_if,
+-02395                      dwc_hc_t * hc, dwc_otg_halt_status_e halt_status)
+-02396 {
+-02397         gnptxsts_data_t nptxsts;
+-02398         hptxsts_data_t hptxsts;
+-02399         hcchar_data_t hcchar;
+-02400         dwc_otg_hc_regs_t *hc_regs;
+-02401         dwc_otg_core_global_regs_t *global_regs;
+-02402         dwc_otg_host_global_regs_t *host_global_regs;
+-02403 
+-02404         hc_regs = core_if->host_if->hc_regs[hc->hc_num];
+-02405         global_regs = core_if->core_global_regs;
+-02406         host_global_regs = core_if->host_if->host_global_regs;
+-02407 
+-02408         DWC_ASSERT(!(halt_status == DWC_OTG_HC_XFER_NO_HALT_STATUS),
+-02409                    "halt_status = %d\n", halt_status);
+-02410 
+-02411         if (halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE ||
+-02412             halt_status == DWC_OTG_HC_XFER_AHB_ERR) {
+-02413                 /*
+-02414                  * Disable all channel interrupts except Ch Halted. The QTD
+-02415                  * and QH state associated with this transfer has been cleared
+-02416                  * (in the case of URB_DEQUEUE), so the channel needs to be
+-02417                  * shut down carefully to prevent crashes.
+-02418                  */
+-02419                 hcintmsk_data_t hcintmsk;
+-02420                 hcintmsk.d32 = 0;
+-02421                 hcintmsk.b.chhltd = 1;
+-02422                 DWC_WRITE_REG32(&hc_regs->hcintmsk, hcintmsk.d32);
+-02423 
+-02424                 /*
+-02425                  * Make sure no other interrupts besides halt are currently
+-02426                  * pending. Handling another interrupt could cause a crash due
+-02427                  * to the QTD and QH state.
+-02428                  */
+-02429                 DWC_WRITE_REG32(&hc_regs->hcint, ~hcintmsk.d32);
+-02430 
+-02431                 /*
+-02432                  * Make sure the halt status is set to URB_DEQUEUE or AHB_ERR
+-02433                  * even if the channel was already halted for some other
+-02434                  * reason.
+-02435                  */
+-02436                 hc->halt_status = halt_status;
+-02437 
+-02438                 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
+-02439                 if (hcchar.b.chen == 0) {
+-02440                         /*
+-02441                          * The channel is either already halted or it hasn't
+-02442                          * started yet. In DMA mode, the transfer may halt if
+-02443                          * it finishes normally or a condition occurs that
+-02444                          * requires driver intervention. Don't want to halt
+-02445                          * the channel again. In either Slave or DMA mode,
+-02446                          * it's possible that the transfer has been assigned
+-02447                          * to a channel, but not started yet when an URB is
+-02448                          * dequeued. Don't want to halt a channel that hasn't
+-02449                          * started yet.
+-02450                          */
+-02451                         return;
+-02452                 }
+-02453         }
+-02454         if (hc->halt_pending) {
+-02455                 /*
+-02456                  * A halt has already been issued for this channel. This might
+-02457                  * happen when a transfer is aborted by a higher level in
+-02458                  * the stack.
+-02459                  */
+-02460 #ifdef DEBUG
+-02461                 DWC_PRINTF
+-02462                     ("*** %s: Channel %d, _hc->halt_pending already set ***\n",
+-02463                      __func__, hc->hc_num);
+-02464 
+-02465 #endif
+-02466                 return;
+-02467         }
+-02468 
+-02469         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
+-02470 
+-02471         /* No need to set the bit in DDMA for disabling the channel */
+-02472         //TODO check it everywhere channel is disabled          
+-02473         if (!core_if->core_params->dma_desc_enable)
+-02474                 hcchar.b.chen = 1;
+-02475         hcchar.b.chdis = 1;
+-02476 
+-02477         if (!core_if->dma_enable) {
+-02478                 /* Check for space in the request queue to issue the halt. */
+-02479                 if (hc->ep_type == DWC_OTG_EP_TYPE_CONTROL ||
+-02480                     hc->ep_type == DWC_OTG_EP_TYPE_BULK) {
+-02481                         nptxsts.d32 = DWC_READ_REG32(&global_regs->gnptxsts);
+-02482                         if (nptxsts.b.nptxqspcavail == 0) {
+-02483                                 hcchar.b.chen = 0;
+-02484                         }
+-02485                 } else {
+-02486                         hptxsts.d32 =
+-02487                             DWC_READ_REG32(&host_global_regs->hptxsts);
+-02488                         if ((hptxsts.b.ptxqspcavail == 0)
+-02489                             || (core_if->queuing_high_bandwidth)) {
+-02490                                 hcchar.b.chen = 0;
+-02491                         }
+-02492                 }
+-02493         }
+-02494         DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
+-02495 
+-02496         hc->halt_status = halt_status;
+-02497 
+-02498         if (hcchar.b.chen) {
+-02499                 hc->halt_pending = 1;
+-02500                 hc->halt_on_queue = 0;
+-02501         } else {
+-02502                 hc->halt_on_queue = 1;
+-02503         }
+-02504 
+-02505         DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num);
+-02506         DWC_DEBUGPL(DBG_HCDV, "  hcchar: 0x%08x\n", hcchar.d32);
+-02507         DWC_DEBUGPL(DBG_HCDV, "  halt_pending: %d\n", hc->halt_pending);
+-02508         DWC_DEBUGPL(DBG_HCDV, "  halt_on_queue: %d\n", hc->halt_on_queue);
+-02509         DWC_DEBUGPL(DBG_HCDV, "  halt_status: %d\n", hc->halt_status);
+-02510 
+-02511         return;
+-02512 }
+-02513 
+-02521 void dwc_otg_hc_cleanup(dwc_otg_core_if_t * core_if, dwc_hc_t * hc)
+-02522 {
+-02523         dwc_otg_hc_regs_t *hc_regs;
+-02524 
+-02525         hc->xfer_started = 0;
+-02526 
+-02527         /*
+-02528          * Clear channel interrupt enables and any unhandled channel interrupt
+-02529          * conditions.
+-02530          */
+-02531         hc_regs = core_if->host_if->hc_regs[hc->hc_num];
+-02532         DWC_WRITE_REG32(&hc_regs->hcintmsk, 0);
+-02533         DWC_WRITE_REG32(&hc_regs->hcint, 0xFFFFFFFF);
+-02534 #ifdef DEBUG
+-02535         DWC_TIMER_CANCEL(core_if->hc_xfer_timer[hc->hc_num]);
+-02536 #endif
+-02537 }
+-02538 
+-02549 static inline void hc_set_even_odd_frame(dwc_otg_core_if_t * core_if,
+-02550                                          dwc_hc_t * hc, hcchar_data_t * hcchar)
+-02551 {
+-02552         if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
+-02553             hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
+-02554                 hfnum_data_t hfnum;
+-02555                 hfnum.d32 =
+-02556                     DWC_READ_REG32(&core_if->host_if->host_global_regs->hfnum);
+-02557 
+-02558                 /* 1 if _next_ frame is odd, 0 if it's even */
+-02559                 hcchar->b.oddfrm = (hfnum.b.frnum & 0x1) ? 0 : 1;
+-02560 #ifdef DEBUG
+-02561                 if (hc->ep_type == DWC_OTG_EP_TYPE_INTR && hc->do_split
+-02562                     && !hc->complete_split) {
+-02563                         switch (hfnum.b.frnum & 0x7) {
+-02564                         case 7:
+-02565                                 core_if->hfnum_7_samples++;
+-02566                                 core_if->hfnum_7_frrem_accum += hfnum.b.frrem;
+-02567                                 break;
+-02568                         case 0:
+-02569                                 core_if->hfnum_0_samples++;
+-02570                                 core_if->hfnum_0_frrem_accum += hfnum.b.frrem;
+-02571                                 break;
+-02572                         default:
+-02573                                 core_if->hfnum_other_samples++;
+-02574                                 core_if->hfnum_other_frrem_accum +=
+-02575                                     hfnum.b.frrem;
+-02576                                 break;
+-02577                         }
+-02578                 }
+-02579 #endif
+-02580         }
+-02581 }
+-02582 
+-02583 #ifdef DEBUG
+-02584 void hc_xfer_timeout(void *ptr)
+-02585 {
+-02586         hc_xfer_info_t *xfer_info = NULL;
+-02587         int hc_num = 0;
+-02588 
+-02589         if (ptr)
+-02590                 xfer_info = (hc_xfer_info_t *) ptr;
+-02591 
+-02592         if (!xfer_info->hc) {
+-02593                 DWC_ERROR("xfer_info->hc = %p\n", xfer_info->hc);
+-02594                 return;
+-02595         }
+-02596 
+-02597         hc_num = xfer_info->hc->hc_num;
+-02598         DWC_WARN("%s: timeout on channel %d\n", __func__, hc_num);
+-02599         DWC_WARN("      start_hcchar_val 0x%08x\n",
+-02600                  xfer_info->core_if->start_hcchar_val[hc_num]);
+-02601 }
+-02602 #endif
+-02603 
+-02604 void ep_xfer_timeout(void *ptr)
+-02605 {
+-02606         ep_xfer_info_t *xfer_info = NULL;
+-02607         int ep_num = 0;
+-02608         dctl_data_t dctl = {.d32 = 0 };
+-02609         gintsts_data_t gintsts = {.d32 = 0 };
+-02610         gintmsk_data_t gintmsk = {.d32 = 0 };
+-02611 
+-02612         if (ptr)
+-02613                 xfer_info = (ep_xfer_info_t *) ptr;
+-02614 
+-02615         if (!xfer_info->ep) {
+-02616                 DWC_ERROR("xfer_info->ep = %p\n", xfer_info->ep);
+-02617                 return;
+-02618         }
+-02619 
+-02620         ep_num = xfer_info->ep->num;
+-02621         DWC_WARN("%s: timeout on endpoit %d\n", __func__, ep_num);
+-02622         /* Put the sate to 2 as it was time outed */
+-02623         xfer_info->state = 2;
+-02624 
+-02625         dctl.d32 = DWC_READ_REG32(&xfer_info->core_if->
+-02626                 dev_if->dev_global_regs->dctl);
+-02627         gintsts.d32 = DWC_READ_REG32(&xfer_info->core_if->
+-02628                 core_global_regs->gintsts);
+-02629         gintmsk.d32 = DWC_READ_REG32(&xfer_info->core_if->
+-02630                 core_global_regs->gintmsk);
+-02631 
+-02632         if (!gintmsk.b.goutnakeff) {
+-02633                 /* Unmask it */
+-02634                 gintmsk.b.goutnakeff = 1;
+-02635                 DWC_WRITE_REG32(&xfer_info->core_if->
+-02636                         core_global_regs->gintmsk, gintmsk.d32);
+-02637 
+-02638         }
+-02639 
+-02640         if (!gintsts.b.goutnakeff) {
+-02641                 dctl.b.sgoutnak = 1;
+-02642         }
+-02643         DWC_WRITE_REG32(&xfer_info->core_if->dev_if->
+-02644                 dev_global_regs->dctl, dctl.d32);
+-02645 
+-02646 }
+-02647 
+-02648 void set_pid_isoc(dwc_hc_t * hc)
+-02649 {
+-02650         /* Set up the initial PID for the transfer. */
+-02651         if (hc->speed == DWC_OTG_EP_SPEED_HIGH) {
+-02652                 if (hc->ep_is_in) {
+-02653                         if (hc->multi_count == 1) {
+-02654                                 hc->data_pid_start = DWC_OTG_HC_PID_DATA0;
+-02655                         } else if (hc->multi_count == 2) {
+-02656                                 hc->data_pid_start = DWC_OTG_HC_PID_DATA1;
+-02657                         } else {
+-02658                                 hc->data_pid_start = DWC_OTG_HC_PID_DATA2;
+-02659                         }
+-02660                 } else {
+-02661                         if (hc->multi_count == 1) {
+-02662                                 hc->data_pid_start = DWC_OTG_HC_PID_DATA0;
+-02663                         } else {
+-02664                                 hc->data_pid_start = DWC_OTG_HC_PID_MDATA;
+-02665                         }
+-02666                 }
+-02667         } else {
+-02668                 hc->data_pid_start = DWC_OTG_HC_PID_DATA0;
+-02669         }
+-02670 }
+-02671 
+-02703 void dwc_otg_hc_start_transfer(dwc_otg_core_if_t * core_if, dwc_hc_t * hc)
+-02704 {
+-02705         hcchar_data_t hcchar;
+-02706         hctsiz_data_t hctsiz;
+-02707         uint16_t num_packets;
+-02708         uint32_t max_hc_xfer_size = core_if->core_params->max_transfer_size;
+-02709         uint16_t max_hc_pkt_count = core_if->core_params->max_packet_count;
+-02710         dwc_otg_hc_regs_t *hc_regs = core_if->host_if->hc_regs[hc->hc_num];
+-02711 
+-02712         hctsiz.d32 = 0;
+-02713 
+-02714         if (hc->do_ping) {
+-02715                 if (!core_if->dma_enable) {
+-02716                         dwc_otg_hc_do_ping(core_if, hc);
+-02717                         hc->xfer_started = 1;
+-02718                         return;
+-02719                 } else {
+-02720                         hctsiz.b.dopng = 1;
+-02721                 }
+-02722         }
+-02723 
+-02724         if (hc->do_split) {
+-02725                 num_packets = 1;
+-02726 
+-02727                 if (hc->complete_split && !hc->ep_is_in) {
+-02728                         /* For CSPLIT OUT Transfer, set the size to 0 so the
+-02729                          * core doesn't expect any data written to the FIFO */
+-02730                         hc->xfer_len = 0;
+-02731                 } else if (hc->ep_is_in || (hc->xfer_len > hc->max_packet)) {
+-02732                         hc->xfer_len = hc->max_packet;
+-02733                 } else if (!hc->ep_is_in && (hc->xfer_len > 188)) {
+-02734                         hc->xfer_len = 188;
+-02735                 }
+-02736 
+-02737                 hctsiz.b.xfersize = hc->xfer_len;
+-02738         } else {
+-02739                 /*
+-02740                  * Ensure that the transfer length and packet count will fit
+-02741                  * in the widths allocated for them in the HCTSIZn register.
+-02742                  */
+-02743                 if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
+-02744                     hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
+-02745                         /*
+-02746                          * Make sure the transfer size is no larger than one
+-02747                          * (micro)frame's worth of data. (A check was done
+-02748                          * when the periodic transfer was accepted to ensure
+-02749                          * that a (micro)frame's worth of data can be
+-02750                          * programmed into a channel.)
+-02751                          */
+-02752                         uint32_t max_periodic_len =
+-02753                             hc->multi_count * hc->max_packet;
+-02754                         if (hc->xfer_len > max_periodic_len) {
+-02755                                 hc->xfer_len = max_periodic_len;
+-02756                         } else {
+-02757                         }
+-02758                 } else if (hc->xfer_len > max_hc_xfer_size) {
+-02759                         /* Make sure that xfer_len is a multiple of max packet size. */
+-02760                         hc->xfer_len = max_hc_xfer_size - hc->max_packet + 1;
+-02761                 }
+-02762 
+-02763                 if (hc->xfer_len > 0) {
+-02764                         num_packets =
+-02765                             (hc->xfer_len + hc->max_packet -
+-02766                              1) / hc->max_packet;
+-02767                         if (num_packets > max_hc_pkt_count) {
+-02768                                 num_packets = max_hc_pkt_count;
+-02769                                 hc->xfer_len = num_packets * hc->max_packet;
+-02770                         }
+-02771                 } else {
+-02772                         /* Need 1 packet for transfer length of 0. */
+-02773                         num_packets = 1;
+-02774                 }
+-02775 
+-02776                 if (hc->ep_is_in) {
+-02777                         /* Always program an integral # of max packets for IN transfers. */
+-02778                         hc->xfer_len = num_packets * hc->max_packet;
+-02779                 }
+-02780 
+-02781                 if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
+-02782                     hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
+-02783                         /*
+-02784                          * Make sure that the multi_count field matches the
+-02785                          * actual transfer length.
+-02786                          */
+-02787                         hc->multi_count = num_packets;
+-02788                 }
+-02789 
+-02790                 if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC)
+-02791                         set_pid_isoc(hc);
+-02792 
+-02793                 hctsiz.b.xfersize = hc->xfer_len;
+-02794         }
+-02795 
+-02796         hc->start_pkt_count = num_packets;
+-02797         hctsiz.b.pktcnt = num_packets;
+-02798         hctsiz.b.pid = hc->data_pid_start;
+-02799         DWC_WRITE_REG32(&hc_regs->hctsiz, hctsiz.d32);
+-02800 
+-02801         DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num);
+-02802         DWC_DEBUGPL(DBG_HCDV, "  Xfer Size: %d\n", hctsiz.b.xfersize);
+-02803         DWC_DEBUGPL(DBG_HCDV, "  Num Pkts: %d\n", hctsiz.b.pktcnt);
+-02804         DWC_DEBUGPL(DBG_HCDV, "  Start PID: %d\n", hctsiz.b.pid);
+-02805 
+-02806         if (core_if->dma_enable) {
+-02807                 dwc_dma_t dma_addr;
+-02808                 if (hc->align_buff) {
+-02809                         dma_addr = hc->align_buff;
+-02810                 } else {
+-02811                         dma_addr = ((unsigned long)hc->xfer_buff & 0xffffffff);
+-02812                 }
+-02813                 DWC_WRITE_REG32(&hc_regs->hcdma, dma_addr);
+-02814         }
+-02815 
+-02816         /* Start the split */
+-02817         if (hc->do_split) {
+-02818                 hcsplt_data_t hcsplt;
+-02819                 hcsplt.d32 = DWC_READ_REG32(&hc_regs->hcsplt);
+-02820                 hcsplt.b.spltena = 1;
+-02821                 DWC_WRITE_REG32(&hc_regs->hcsplt, hcsplt.d32);
+-02822         }
+-02823 
+-02824         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
+-02825         hcchar.b.multicnt = hc->multi_count;
+-02826         hc_set_even_odd_frame(core_if, hc, &hcchar);
+-02827 #ifdef DEBUG
+-02828         core_if->start_hcchar_val[hc->hc_num] = hcchar.d32;
+-02829         if (hcchar.b.chdis) {
+-02830                 DWC_WARN("%s: chdis set, channel %d, hcchar 0x%08x\n",
+-02831                          __func__, hc->hc_num, hcchar.d32);
+-02832         }
+-02833 #endif
+-02834 
+-02835         /* Set host channel enable after all other setup is complete. */
+-02836         hcchar.b.chen = 1;
+-02837         hcchar.b.chdis = 0;
+-02838         DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
+-02839 
+-02840         hc->xfer_started = 1;
+-02841         hc->requests++;
+-02842 
+-02843         if (!core_if->dma_enable && !hc->ep_is_in && hc->xfer_len > 0) {
+-02844                 /* Load OUT packet into the appropriate Tx FIFO. */
+-02845                 dwc_otg_hc_write_packet(core_if, hc);
+-02846         }
+-02847 #ifdef DEBUG
+-02848         if (hc->ep_type != DWC_OTG_EP_TYPE_INTR) {
+-02849                 core_if->hc_xfer_info[hc->hc_num].core_if = core_if;
+-02850                 core_if->hc_xfer_info[hc->hc_num].hc = hc;
+-02851 
+-02852                 /* Start a timer for this transfer. */
+-02853                 DWC_TIMER_SCHEDULE(core_if->hc_xfer_timer[hc->hc_num], 10000);
+-02854         }
+-02855 #endif
+-02856 }
+-02857 
+-02872 void dwc_otg_hc_start_transfer_ddma(dwc_otg_core_if_t * core_if, dwc_hc_t * hc)
+-02873 {
+-02874         dwc_otg_hc_regs_t *hc_regs = core_if->host_if->hc_regs[hc->hc_num];
+-02875         hcchar_data_t hcchar;
+-02876         hctsiz_data_t hctsiz;
+-02877         hcdma_data_t hcdma;
+-02878 
+-02879         hctsiz.d32 = 0;
+-02880 
+-02881         if (hc->do_ping)
+-02882                 hctsiz.b_ddma.dopng = 1;
+-02883 
+-02884         if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC)
+-02885                 set_pid_isoc(hc);
+-02886 
+-02887         /* Packet Count and Xfer Size are not used in Descriptor DMA mode */
+-02888         hctsiz.b_ddma.pid = hc->data_pid_start;
+-02889         hctsiz.b_ddma.ntd = hc->ntd - 1;        /* 0 - 1 descriptor, 1 - 2 descriptors, etc. */
+-02890         hctsiz.b_ddma.schinfo = hc->schinfo;    /* Non-zero only for high-speed interrupt endpoints */
+-02891 
+-02892         DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num);
+-02893         DWC_DEBUGPL(DBG_HCDV, "  Start PID: %d\n", hctsiz.b.pid);
+-02894         DWC_DEBUGPL(DBG_HCDV, "  NTD: %d\n", hctsiz.b_ddma.ntd);
+-02895 
+-02896         DWC_WRITE_REG32(&hc_regs->hctsiz, hctsiz.d32);
+-02897 
+-02898         hcdma.d32 = 0;
+-02899         hcdma.b.dma_addr = ((uint32_t) hc->desc_list_addr) >> 11;
+-02900 
+-02901         /* Always start from first descriptor. */
+-02902         hcdma.b.ctd = 0;
+-02903         DWC_WRITE_REG32(&hc_regs->hcdma, hcdma.d32);
+-02904 
+-02905         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
+-02906         hcchar.b.multicnt = hc->multi_count;
+-02907 
+-02908 #ifdef DEBUG
+-02909         core_if->start_hcchar_val[hc->hc_num] = hcchar.d32;
+-02910         if (hcchar.b.chdis) {
+-02911                 DWC_WARN("%s: chdis set, channel %d, hcchar 0x%08x\n",
+-02912                          __func__, hc->hc_num, hcchar.d32);
+-02913         }
+-02914 #endif
+-02915 
+-02916         /* Set host channel enable after all other setup is complete. */
+-02917         hcchar.b.chen = 1;
+-02918         hcchar.b.chdis = 0;
+-02919 
+-02920         DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
+-02921 
+-02922         hc->xfer_started = 1;
+-02923         hc->requests++;
+-02924 
+-02925 #ifdef DEBUG
+-02926         if ((hc->ep_type != DWC_OTG_EP_TYPE_INTR)
+-02927             && (hc->ep_type != DWC_OTG_EP_TYPE_ISOC)) {
+-02928                 core_if->hc_xfer_info[hc->hc_num].core_if = core_if;
+-02929                 core_if->hc_xfer_info[hc->hc_num].hc = hc;
+-02930                 /* Start a timer for this transfer. */
+-02931                 DWC_TIMER_SCHEDULE(core_if->hc_xfer_timer[hc->hc_num], 10000);
+-02932         }
+-02933 #endif
+-02934 
+-02935 }
+-02936 
+-02952 int dwc_otg_hc_continue_transfer(dwc_otg_core_if_t * core_if, dwc_hc_t * hc)
+-02953 {
+-02954         DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num);
+-02955 
+-02956         if (hc->do_split) {
+-02957                 /* SPLITs always queue just once per channel */
+-02958                 return 0;
+-02959         } else if (hc->data_pid_start == DWC_OTG_HC_PID_SETUP) {
+-02960                 /* SETUPs are queued only once since they can't be NAKed. */
+-02961                 return 0;
+-02962         } else if (hc->ep_is_in) {
+-02963                 /*
+-02964                  * Always queue another request for other IN transfers. If
+-02965                  * back-to-back INs are issued and NAKs are received for both,
+-02966                  * the driver may still be processing the first NAK when the
+-02967                  * second NAK is received. When the interrupt handler clears
+-02968                  * the NAK interrupt for the first NAK, the second NAK will
+-02969                  * not be seen. So we can't depend on the NAK interrupt
+-02970                  * handler to requeue a NAKed request. Instead, IN requests
+-02971                  * are issued each time this function is called. When the
+-02972                  * transfer completes, the extra requests for the channel will
+-02973                  * be flushed.
+-02974                  */
+-02975                 hcchar_data_t hcchar;
+-02976                 dwc_otg_hc_regs_t *hc_regs =
+-02977                     core_if->host_if->hc_regs[hc->hc_num];
+-02978 
+-02979                 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
+-02980                 hc_set_even_odd_frame(core_if, hc, &hcchar);
+-02981                 hcchar.b.chen = 1;
+-02982                 hcchar.b.chdis = 0;
+-02983                 DWC_DEBUGPL(DBG_HCDV, "  IN xfer: hcchar = 0x%08x\n",
+-02984                             hcchar.d32);
+-02985                 DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
+-02986                 hc->requests++;
+-02987                 return 1;
+-02988         } else {
+-02989                 /* OUT transfers. */
+-02990                 if (hc->xfer_count < hc->xfer_len) {
+-02991                         if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
+-02992                             hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
+-02993                                 hcchar_data_t hcchar;
+-02994                                 dwc_otg_hc_regs_t *hc_regs;
+-02995                                 hc_regs = core_if->host_if->hc_regs[hc->hc_num];
+-02996                                 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
+-02997                                 hc_set_even_odd_frame(core_if, hc, &hcchar);
+-02998                         }
+-02999 
+-03000                         /* Load OUT packet into the appropriate Tx FIFO. */
+-03001                         dwc_otg_hc_write_packet(core_if, hc);
+-03002                         hc->requests++;
+-03003                         return 1;
+-03004                 } else {
+-03005                         return 0;
+-03006                 }
+-03007         }
+-03008 }
+-03009 
+-03014 void dwc_otg_hc_do_ping(dwc_otg_core_if_t * core_if, dwc_hc_t * hc)
+-03015 {
+-03016         hcchar_data_t hcchar;
+-03017         hctsiz_data_t hctsiz;
+-03018         dwc_otg_hc_regs_t *hc_regs = core_if->host_if->hc_regs[hc->hc_num];
+-03019 
+-03020         DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num);
+-03021 
+-03022         hctsiz.d32 = 0;
+-03023         hctsiz.b.dopng = 1;
+-03024         hctsiz.b.pktcnt = 1;
+-03025         DWC_WRITE_REG32(&hc_regs->hctsiz, hctsiz.d32);
+-03026 
+-03027         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
+-03028         hcchar.b.chen = 1;
+-03029         hcchar.b.chdis = 0;
+-03030         DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
+-03031 }
+-03032 
+-03033 /*
+-03034  * This function writes a packet into the Tx FIFO associated with the Host
+-03035  * Channel. For a channel associated with a non-periodic EP, the non-periodic
+-03036  * Tx FIFO is written. For a channel associated with a periodic EP, the
+-03037  * periodic Tx FIFO is written. This function should only be called in Slave
+-03038  * mode.
+-03039  *
+-03040  * Upon return the xfer_buff and xfer_count fields in _hc are incremented by
+-03041  * then number of bytes written to the Tx FIFO.
+-03042  */
+-03043 void dwc_otg_hc_write_packet(dwc_otg_core_if_t * core_if, dwc_hc_t * hc)
+-03044 {
+-03045         uint32_t i;
+-03046         uint32_t remaining_count;
+-03047         uint32_t byte_count;
+-03048         uint32_t dword_count;
+-03049 
+-03050         uint32_t *data_buff = (uint32_t *) (hc->xfer_buff);
+-03051         uint32_t *data_fifo = core_if->data_fifo[hc->hc_num];
+-03052 
+-03053         remaining_count = hc->xfer_len - hc->xfer_count;
+-03054         if (remaining_count > hc->max_packet) {
+-03055                 byte_count = hc->max_packet;
+-03056         } else {
+-03057                 byte_count = remaining_count;
+-03058         }
+-03059 
+-03060         dword_count = (byte_count + 3) / 4;
+-03061 
+-03062         if ((((unsigned long)data_buff) & 0x3) == 0) {
+-03063                 /* xfer_buff is DWORD aligned. */
+-03064                 for (i = 0; i < dword_count; i++, data_buff++) {
+-03065                         DWC_WRITE_REG32(data_fifo, *data_buff);
+-03066                 }
+-03067         } else {
+-03068                 /* xfer_buff is not DWORD aligned. */
+-03069                 for (i = 0; i < dword_count; i++, data_buff++) {
+-03070                         uint32_t data;
+-03071                         data =
+-03072                             (data_buff[0] | data_buff[1] << 8 | data_buff[2] <<
+-03073                              16 | data_buff[3] << 24);
+-03074                         DWC_WRITE_REG32(data_fifo, data);
+-03075                 }
+-03076         }
+-03077 
+-03078         hc->xfer_count += byte_count;
+-03079         hc->xfer_buff += byte_count;
+-03080 }
+-03081 
+-03086 uint32_t dwc_otg_get_frame_number(dwc_otg_core_if_t * core_if)
+-03087 {
+-03088         dsts_data_t dsts;
+-03089         dsts.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts);
+-03090 
+-03091         /* read current frame/microframe number from DSTS register */
+-03092         return dsts.b.soffn;
+-03093 }
+-03094 
+-03102 uint32_t calc_frame_interval(dwc_otg_core_if_t * core_if)
+-03103 {
+-03104         gusbcfg_data_t usbcfg;
+-03105         hwcfg2_data_t hwcfg2;
+-03106         hprt0_data_t hprt0;
+-03107         int clock = 60;         // default value
+-03108         usbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
+-03109         hwcfg2.d32 = DWC_READ_REG32(&core_if->core_global_regs->ghwcfg2);
+-03110         hprt0.d32 = DWC_READ_REG32(core_if->host_if->hprt0);
+-03111         if (!usbcfg.b.physel && usbcfg.b.ulpi_utmi_sel && !usbcfg.b.phyif)
+-03112                 clock = 60;
+-03113         if (usbcfg.b.physel && hwcfg2.b.fs_phy_type == 3)
+-03114                 clock = 48;
+-03115         if (!usbcfg.b.phylpwrclksel && !usbcfg.b.physel &&
+-03116             !usbcfg.b.ulpi_utmi_sel && usbcfg.b.phyif)
+-03117                 clock = 30;
+-03118         if (!usbcfg.b.phylpwrclksel && !usbcfg.b.physel &&
+-03119             !usbcfg.b.ulpi_utmi_sel && !usbcfg.b.phyif)
+-03120                 clock = 60;
+-03121         if (usbcfg.b.phylpwrclksel && !usbcfg.b.physel &&
+-03122             !usbcfg.b.ulpi_utmi_sel && usbcfg.b.phyif)
+-03123                 clock = 48;
+-03124         if (usbcfg.b.physel && !usbcfg.b.phyif && hwcfg2.b.fs_phy_type == 2)
+-03125                 clock = 48;
+-03126         if (usbcfg.b.physel && hwcfg2.b.fs_phy_type == 1)
+-03127                 clock = 48;
+-03128         if (hprt0.b.prtspd == 0)
+-03129                 /* High speed case */
+-03130                 return 125 * clock;
+-03131         else
+-03132                 /* FS/LS case */
+-03133                 return 1000 * clock;
+-03134 }
+-03135 
+-03144 void dwc_otg_read_setup_packet(dwc_otg_core_if_t * core_if, uint32_t * dest)
+-03145 {
+-03146         /* Get the 8 bytes of a setup transaction data */
+-03147 
+-03148         /* Pop 2 DWORDS off the receive data FIFO into memory */
+-03149         dest[0] = DWC_READ_REG32(core_if->data_fifo[0]);
+-03150         dest[1] = DWC_READ_REG32(core_if->data_fifo[0]);
+-03151 }
+-03152 
+-03161 void dwc_otg_ep0_activate(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
+-03162 {
+-03163         dwc_otg_dev_if_t *dev_if = core_if->dev_if;
+-03164         dsts_data_t dsts;
+-03165         depctl_data_t diepctl;
+-03166         depctl_data_t doepctl;
+-03167         dctl_data_t dctl = {.d32 = 0 };
+-03168 
+-03169         /* Read the Device Status and Endpoint 0 Control registers */
+-03170         dsts.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->dsts);
+-03171         diepctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[0]->diepctl);
+-03172         doepctl.d32 = DWC_READ_REG32(&dev_if->out_ep_regs[0]->doepctl);
+-03173 
+-03174         /* Set the MPS of the IN EP based on the enumeration speed */
+-03175         switch (dsts.b.enumspd) {
+-03176         case DWC_DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ:
+-03177         case DWC_DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ:
+-03178         case DWC_DSTS_ENUMSPD_FS_PHY_48MHZ:
+-03179                 diepctl.b.mps = DWC_DEP0CTL_MPS_64;
+-03180                 break;
+-03181         case DWC_DSTS_ENUMSPD_LS_PHY_6MHZ:
+-03182                 diepctl.b.mps = DWC_DEP0CTL_MPS_8;
+-03183                 break;
+-03184         }
+-03185 
+-03186         DWC_WRITE_REG32(&dev_if->in_ep_regs[0]->diepctl, diepctl.d32);
+-03187 
+-03188         /* Enable OUT EP for receive */
+-03189         doepctl.b.epena = 1;
+-03190         DWC_WRITE_REG32(&dev_if->out_ep_regs[0]->doepctl, doepctl.d32);
+-03191 
+-03192 #ifdef VERBOSE
+-03193         DWC_DEBUGPL(DBG_PCDV, "doepctl0=%0x\n",
+-03194                     DWC_READ_REG32(&dev_if->out_ep_regs[0]->doepctl));
+-03195         DWC_DEBUGPL(DBG_PCDV, "diepctl0=%0x\n",
+-03196                     DWC_READ_REG32(&dev_if->in_ep_regs[0]->diepctl));
+-03197 #endif
+-03198         dctl.b.cgnpinnak = 1;
+-03199 
+-03200         DWC_MODIFY_REG32(&dev_if->dev_global_regs->dctl, dctl.d32, dctl.d32);
+-03201         DWC_DEBUGPL(DBG_PCDV, "dctl=%0x\n",
+-03202                     DWC_READ_REG32(&dev_if->dev_global_regs->dctl));
+-03203 
+-03204 }
+-03205 
+-03214 void dwc_otg_ep_activate(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
+-03215 {
+-03216         dwc_otg_dev_if_t *dev_if = core_if->dev_if;
+-03217         depctl_data_t depctl;
+-03218         volatile uint32_t *addr;
+-03219         daint_data_t daintmsk = {.d32 = 0 };
+-03220         dcfg_data_t dcfg;
+-03221         uint8_t i;
+-03222 
+-03223         DWC_DEBUGPL(DBG_PCDV, "%s() EP%d-%s\n", __func__, ep->num,
+-03224                     (ep->is_in ? "IN" : "OUT"));
+-03225 
+-03226 #ifdef DWC_UTE_PER_IO
+-03227         ep->xiso_frame_num = 0xFFFFFFFF;
+-03228         ep->xiso_active_xfers = 0;
+-03229         ep->xiso_queued_xfers = 0;
+-03230 #endif
+-03231         /* Read DEPCTLn register */
+-03232         if (ep->is_in == 1) {
+-03233                 addr = &dev_if->in_ep_regs[ep->num]->diepctl;
+-03234                 daintmsk.ep.in = 1 << ep->num;
+-03235         } else {
+-03236                 addr = &dev_if->out_ep_regs[ep->num]->doepctl;
+-03237                 daintmsk.ep.out = 1 << ep->num;
+-03238         }
+-03239 
+-03240         /* If the EP is already active don't change the EP Control
+-03241          * register. */
+-03242         depctl.d32 = DWC_READ_REG32(addr);
+-03243         if (!depctl.b.usbactep) {
+-03244                 depctl.b.mps = ep->maxpacket;
+-03245                 depctl.b.eptype = ep->type;
+-03246                 depctl.b.txfnum = ep->tx_fifo_num;
+-03247 
+-03248                 if (ep->type == DWC_OTG_EP_TYPE_ISOC) {
+-03249                         depctl.b.setd0pid = 1;  // ???
+-03250                 } else {
+-03251                         depctl.b.setd0pid = 1;
+-03252                 }
+-03253                 depctl.b.usbactep = 1;
+-03254 
+-03255                 /* Update nextep_seq array and EPMSCNT in DCFG*/
+-03256                 if (!(depctl.b.eptype & 1) && (ep->is_in == 1)) {       // NP IN EP
+-03257                         for (i = 0; i <= core_if->dev_if->num_in_eps; i++) {
+-03258                                 if (core_if->nextep_seq[i] == core_if->first_in_nextep_seq)
+-03259                                 break;
+-03260                         }
+-03261                         core_if->nextep_seq[i] = ep->num;       
+-03262                         core_if->nextep_seq[ep->num] = core_if->first_in_nextep_seq;
+-03263                         depctl.b.nextep = core_if->nextep_seq[ep->num];
+-03264                         dcfg.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->dcfg);
+-03265                         dcfg.b.epmscnt++;
+-03266                         DWC_WRITE_REG32(&dev_if->dev_global_regs->dcfg, dcfg.d32);
+-03267 
+-03268                         DWC_DEBUGPL(DBG_PCDV,"%s first_in_nextep_seq= %2d; nextep_seq[]:\n", 
+-03269                                 __func__, core_if->first_in_nextep_seq);
+-03270                         for (i=0; i <= core_if->dev_if->num_in_eps; i++) {
+-03271                                 DWC_DEBUGPL(DBG_PCDV, "%2d\n", core_if->nextep_seq[i]);
+-03272                         }
+-03273 
+-03274                 }
+-03275 
+-03276 
+-03277                 DWC_WRITE_REG32(addr, depctl.d32);
+-03278                 DWC_DEBUGPL(DBG_PCDV, "DEPCTL=%08x\n", DWC_READ_REG32(addr));
+-03279         }
+-03280 
+-03281         /* Enable the Interrupt for this EP */
+-03282         if (core_if->multiproc_int_enable) {
+-03283                 if (ep->is_in == 1) {
+-03284                         diepmsk_data_t diepmsk = {.d32 = 0 };
+-03285                         diepmsk.b.xfercompl = 1;
+-03286                         diepmsk.b.timeout = 1;
+-03287                         diepmsk.b.epdisabled = 1;
+-03288                         diepmsk.b.ahberr = 1;
+-03289                         diepmsk.b.intknepmis = 1;
+-03290                         if (!core_if->en_multiple_tx_fifo && core_if->dma_enable)
+-03291                                 diepmsk.b.intknepmis = 0; 
+-03292                         diepmsk.b.txfifoundrn = 1;      //?????
+-03293                         if (ep->type == DWC_OTG_EP_TYPE_ISOC) {
+-03294                                 diepmsk.b.nak = 1;
+-03295                         }
+-03296 
+-03297                         
+-03298                         
+-03299 /*
+-03300                         if (core_if->dma_desc_enable) {
+-03301                                 diepmsk.b.bna = 1;
+-03302                         }
+-03303 */
+-03304 /*                      
+-03305                         if (core_if->dma_enable) {
+-03306                                 doepmsk.b.nak = 1;
+-03307                         }
+-03308 */
+-03309                         DWC_WRITE_REG32(&dev_if->dev_global_regs->
+-03310                                         diepeachintmsk[ep->num], diepmsk.d32);
+-03311 
+-03312                 } else {
+-03313                         doepmsk_data_t doepmsk = {.d32 = 0 };
+-03314                         doepmsk.b.xfercompl = 1;
+-03315                         doepmsk.b.ahberr = 1;
+-03316                         doepmsk.b.epdisabled = 1;
+-03317                         if (ep->type == DWC_OTG_EP_TYPE_ISOC)
+-03318                                 doepmsk.b.outtknepdis = 1;
+-03319 
+-03320 /*                      
+-03321 
+-03322                         if (core_if->dma_desc_enable) {
+-03323                                 doepmsk.b.bna = 1;
+-03324                         }
+-03325 */
+-03326 /*                      
+-03327                         doepmsk.b.babble = 1;
+-03328                         doepmsk.b.nyet = 1;
+-03329                         doepmsk.b.nak = 1;
+-03330 */
+-03331                         DWC_WRITE_REG32(&dev_if->dev_global_regs->
+-03332                                         doepeachintmsk[ep->num], doepmsk.d32);
+-03333                 }
+-03334                 DWC_MODIFY_REG32(&dev_if->dev_global_regs->deachintmsk,
+-03335                                  0, daintmsk.d32);
+-03336         } else {
+-03337                 if (ep->type == DWC_OTG_EP_TYPE_ISOC) {
+-03338                         if (ep->is_in)
+-03339                         {
+-03340                                 diepmsk_data_t diepmsk = {.d32 = 0 };
+-03341                                 diepmsk.b.nak = 1;
+-03342                                 DWC_MODIFY_REG32(&dev_if->dev_global_regs->diepmsk, 0, diepmsk.d32);
+-03343                         } else {
+-03344                                 doepmsk_data_t doepmsk = {.d32 = 0 };
+-03345                                 doepmsk.b.outtknepdis = 1;
+-03346                                 DWC_MODIFY_REG32(&dev_if->dev_global_regs->doepmsk, 0, doepmsk.d32);
+-03347                         }
+-03348                 }
+-03349                 DWC_MODIFY_REG32(&dev_if->dev_global_regs->daintmsk,
+-03350                                  0, daintmsk.d32);
+-03351         }
+-03352 
+-03353         DWC_DEBUGPL(DBG_PCDV, "DAINTMSK=%0x\n",
+-03354                     DWC_READ_REG32(&dev_if->dev_global_regs->daintmsk));
+-03355 
+-03356         ep->stall_clear_flag = 0;
+-03357 
+-03358         return;
+-03359 }
+-03360 
+-03369 void dwc_otg_ep_deactivate(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
+-03370 {
+-03371         depctl_data_t depctl = {.d32 = 0 };
+-03372         volatile uint32_t *addr;
+-03373         daint_data_t daintmsk = {.d32 = 0 };
+-03374         dcfg_data_t dcfg;
+-03375         uint8_t i = 0;
+-03376 
+-03377 #ifdef DWC_UTE_PER_IO
+-03378         ep->xiso_frame_num = 0xFFFFFFFF;
+-03379         ep->xiso_active_xfers = 0;
+-03380         ep->xiso_queued_xfers = 0;
+-03381 #endif
+-03382 
+-03383         /* Read DEPCTLn register */
+-03384         if (ep->is_in == 1) {
+-03385                 addr = &core_if->dev_if->in_ep_regs[ep->num]->diepctl;
+-03386                 daintmsk.ep.in = 1 << ep->num;
+-03387         } else {
+-03388                 addr = &core_if->dev_if->out_ep_regs[ep->num]->doepctl;
+-03389                 daintmsk.ep.out = 1 << ep->num;
+-03390         }
+-03391 
+-03392         depctl.d32 = DWC_READ_REG32(addr);
+-03393 
+-03394         depctl.b.usbactep = 0;
+-03395         
+-03396         /* Update nextep_seq array and EPMSCNT in DCFG*/
+-03397         if (!(depctl.b.eptype & 1) && ep->is_in == 1) { // NP EP IN
+-03398                 for (i = 0; i <= core_if->dev_if->num_in_eps; i++) {
+-03399                         if (core_if->nextep_seq[i] == ep->num)
+-03400                         break;
+-03401                 }
+-03402                 core_if->nextep_seq[i] = core_if->nextep_seq[ep->num];  
+-03403                 if (core_if->first_in_nextep_seq == ep->num)
+-03404                         core_if->first_in_nextep_seq = i;
+-03405                 core_if->nextep_seq[ep->num] = 0xff;
+-03406                 depctl.b.nextep = 0;
+-03407                 dcfg.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg);
+-03408                 dcfg.b.epmscnt--;
+-03409                 DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dcfg, dcfg.d32);
+-03410 
+-03411                         DWC_DEBUGPL(DBG_PCDV,"%s first_in_nextep_seq= %2d; nextep_seq[]:\n", 
+-03412                                 __func__, core_if->first_in_nextep_seq);
+-03413                         for (i=0; i <= core_if->dev_if->num_in_eps; i++) {
+-03414                                 DWC_DEBUGPL(DBG_PCDV, "%2d\n", core_if->nextep_seq[i]);
+-03415                         }
+-03416         }
+-03417                 
+-03418         if (ep->is_in == 1)
+-03419                 depctl.b.txfnum = 0;
+-03420 
+-03421         if (core_if->dma_desc_enable)
+-03422                 depctl.b.epdis = 1;
+-03423 
+-03424         DWC_WRITE_REG32(addr, depctl.d32);
+-03425         depctl.d32 = DWC_READ_REG32(addr);
+-03426         if (core_if->dma_enable && ep->type == DWC_OTG_EP_TYPE_ISOC && depctl.b.epena)
+-03427         {
+-03428                 depctl_data_t depctl = {.d32 = 0};
+-03429                 if (ep->is_in)
+-03430                 {
+-03431                         diepint_data_t diepint = {.d32 = 0};
+-03432                         
+-03433                         depctl.b.snak = 1;
+-03434                         DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[ep->num]->diepctl, depctl.d32);
+-03435                         do 
+-03436                         {
+-03437                                 dwc_udelay(10);
+-03438                                 diepint.d32 = DWC_READ_REG32(&core_if->dev_if->
+-03439                                                                                         in_ep_regs[ep->num]->diepint);
+-03440                         } while (!diepint.b.inepnakeff); 
+-03441                         diepint.b.inepnakeff = 1;
+-03442                         DWC_WRITE_REG32(&core_if->dev_if->
+-03443                                                         in_ep_regs[ep->num]->diepint, diepint.d32);
+-03444                         depctl.d32 = 0;
+-03445                         depctl.b.epdis = 1;
+-03446                         DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[ep->num]->diepctl, depctl.d32);
+-03447                         do 
+-03448                         {
+-03449                                 dwc_udelay(10);
+-03450                                 diepint.d32 = DWC_READ_REG32(&core_if->dev_if->
+-03451                                                                                         in_ep_regs[ep->num]->diepint);
+-03452                         } while (!diepint.b.epdisabled); 
+-03453                         diepint.b.epdisabled = 1;
+-03454                         DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[ep->num]->diepint, diepint.d32);
+-03455                 } else {
+-03456                         dctl_data_t dctl = {.d32 = 0};
+-03457                         gintmsk_data_t gintsts = {.d32 = 0};
+-03458                         doepint_data_t doepint = {.d32 = 0};
+-03459                         dctl.b.sgoutnak = 1;
+-03460                         DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, 0, dctl.d32);
+-03461                         do 
+-03462                         {
+-03463                                 dwc_udelay(10);
+-03464                                 gintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts);
+-03465                         } while (!gintsts.b.goutnakeff); 
+-03466                         gintsts.d32 = 0;
+-03467                         gintsts.b.goutnakeff = 1;
+-03468                         DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
+-03469 
+-03470                         depctl.d32 = 0;
+-03471                         depctl.b.epdis = 1;
+-03472                         depctl.b.snak = 1;
+-03473                         DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[ep->num]->doepctl, depctl.d32);
+-03474                         do 
+-03475                         {
+-03476                                 dwc_udelay(10);
+-03477                                 doepint.d32 = DWC_READ_REG32(&core_if->dev_if->
+-03478                                                                                         out_ep_regs[ep->num]->doepint);
+-03479                         } while (!doepint.b.epdisabled); 
+-03480 
+-03481                         doepint.b.epdisabled = 1;
+-03482                         DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[ep->num]->doepint, doepint.d32);
+-03483 
+-03484                         dctl.d32 = 0;
+-03485                         dctl.b.cgoutnak = 1;
+-03486                         DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, 0, dctl.d32);
+-03487                 }               
+-03488         }
+-03489 
+-03490         /* Disable the Interrupt for this EP */
+-03491         if (core_if->multiproc_int_enable) {
+-03492                 DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->deachintmsk,
+-03493                                  daintmsk.d32, 0);
+-03494 
+-03495                 if (ep->is_in == 1) {
+-03496                         DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->
+-03497                                         diepeachintmsk[ep->num], 0);
+-03498                 } else {
+-03499                         DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->
+-03500                                         doepeachintmsk[ep->num], 0);
+-03501                 }
+-03502         } else {
+-03503                 DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->daintmsk,
+-03504                                  daintmsk.d32, 0);
+-03505         }
+-03506 
+-03507 }
+-03508 
+-03515 static void init_dma_desc_chain(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
+-03516 {
+-03517         dwc_otg_dev_dma_desc_t *dma_desc;
+-03518         uint32_t offset;
+-03519         uint32_t xfer_est;
+-03520         int i;
+-03521         unsigned maxxfer_local, total_len;
+-03522         
+-03523         if (!ep->is_in && ep->type == DWC_OTG_EP_TYPE_INTR && 
+-03524                                         (ep->maxpacket%4)) {
+-03525                 maxxfer_local = ep->maxpacket;
+-03526                 total_len = ep->xfer_len;
+-03527         } else {
+-03528                 maxxfer_local = ep->maxxfer;
+-03529                 total_len = ep->total_len;
+-03530         }
+-03531 
+-03532         ep->desc_cnt = (total_len / maxxfer_local) +
+-03533             ((total_len % maxxfer_local) ? 1 : 0);
+-03534 
+-03535         if (!ep->desc_cnt)
+-03536                 ep->desc_cnt = 1;
+-03537 
+-03538         if (ep->desc_cnt > MAX_DMA_DESC_CNT)
+-03539                 ep->desc_cnt = MAX_DMA_DESC_CNT;
+-03540 
+-03541         dma_desc = ep->desc_addr;
+-03542         if (maxxfer_local == ep->maxpacket) {
+-03543                 if ((total_len % maxxfer_local) &&
+-03544                                 (total_len/maxxfer_local < MAX_DMA_DESC_CNT)) {
+-03545                         xfer_est = (ep->desc_cnt - 1) * maxxfer_local +
+-03546                                         (total_len % maxxfer_local);
+-03547                 } else
+-03548                         xfer_est = ep->desc_cnt * maxxfer_local;
+-03549         }
+-03550         else
+-03551                 xfer_est = total_len;
+-03552         offset = 0;
+-03553         for (i = 0; i < ep->desc_cnt; ++i) {
+-03555                 if (xfer_est > maxxfer_local) {
+-03556                         dma_desc->status.b.bs = BS_HOST_BUSY;
+-03557                         dma_desc->status.b.l = 0;
+-03558                         dma_desc->status.b.ioc = 0;
+-03559                         dma_desc->status.b.sp = 0;
+-03560                         dma_desc->status.b.bytes = maxxfer_local;
+-03561                         dma_desc->buf = ep->dma_addr + offset;
+-03562                         dma_desc->status.b.sts = 0;
+-03563                         dma_desc->status.b.bs = BS_HOST_READY;
+-03564 
+-03565                         xfer_est -= maxxfer_local;
+-03566                         offset += maxxfer_local;
+-03567                 } else {
+-03568                         dma_desc->status.b.bs = BS_HOST_BUSY;
+-03569                         dma_desc->status.b.l = 1;
+-03570                         dma_desc->status.b.ioc = 1;
+-03571                         if (ep->is_in) {
+-03572                                 dma_desc->status.b.sp =
+-03573                                     (xfer_est %
+-03574                                      ep->maxpacket) ? 1 : ((ep->
+-03575                                                             sent_zlp) ? 1 : 0);
+-03576                                 dma_desc->status.b.bytes = xfer_est;
+-03577                         } else {
+-03578                                 if (maxxfer_local == ep->maxpacket)
+-03579                                         dma_desc->status.b.bytes = xfer_est;
+-03580                                 else    
+-03581                                         dma_desc->status.b.bytes =
+-03582                                                 xfer_est + ((4 - (xfer_est & 0x3)) & 0x3);
+-03583                         }
+-03584 
+-03585                         dma_desc->buf = ep->dma_addr + offset;
+-03586                         dma_desc->status.b.sts = 0;
+-03587                         dma_desc->status.b.bs = BS_HOST_READY;
+-03588                 }
+-03589                 dma_desc++;
+-03590         }
+-03591 }
+-03596 static int32_t write_isoc_tx_fifo(dwc_otg_core_if_t * core_if, dwc_ep_t * dwc_ep)
+-03597 {
+-03598         dwc_otg_dev_if_t *dev_if = core_if->dev_if;
+-03599         dwc_otg_dev_in_ep_regs_t *ep_regs;
+-03600         dtxfsts_data_t txstatus = {.d32 = 0 };
+-03601         uint32_t len = 0;
+-03602         int epnum = dwc_ep->num;
+-03603         int dwords;
+-03604 
+-03605         DWC_DEBUGPL(DBG_PCD, "Dedicated TxFifo Empty: %d \n", epnum);
+-03606 
+-03607         ep_regs = core_if->dev_if->in_ep_regs[epnum];
+-03608 
+-03609         len = dwc_ep->xfer_len - dwc_ep->xfer_count;
+-03610 
+-03611         if (len > dwc_ep->maxpacket) {
+-03612                 len = dwc_ep->maxpacket;
+-03613         }
+-03614 
+-03615         dwords = (len + 3) / 4;
+-03616 
+-03617         /* While there is space in the queue and space in the FIFO and
+-03618          * More data to tranfer, Write packets to the Tx FIFO */
+-03619         txstatus.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->dtxfsts);
+-03620         DWC_DEBUGPL(DBG_PCDV, "b4 dtxfsts[%d]=0x%08x\n", epnum, txstatus.d32);
+-03621 
+-03622         while (txstatus.b.txfspcavail > dwords &&
+-03623                dwc_ep->xfer_count < dwc_ep->xfer_len &&
+-03624                dwc_ep->xfer_len != 0) {
+-03625                 /* Write the FIFO */
+-03626                 dwc_otg_ep_write_packet(core_if, dwc_ep, 0);
+-03627 
+-03628                 len = dwc_ep->xfer_len - dwc_ep->xfer_count;
+-03629                 if (len > dwc_ep->maxpacket) {
+-03630                         len = dwc_ep->maxpacket;
+-03631                 }
+-03632 
+-03633                 dwords = (len + 3) / 4;
+-03634                 txstatus.d32 =
+-03635                     DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->dtxfsts);
+-03636                 DWC_DEBUGPL(DBG_PCDV, "dtxfsts[%d]=0x%08x\n", epnum,
+-03637                             txstatus.d32);
+-03638         }
+-03639 
+-03640         DWC_DEBUGPL(DBG_PCDV, "b4 dtxfsts[%d]=0x%08x\n", epnum,
+-03641                     DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->dtxfsts));
+-03642 
+-03643         return 1;
+-03644 }
+-03655 void dwc_otg_ep_start_transfer(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
+-03656 {
+-03657         depctl_data_t depctl;
+-03658         deptsiz_data_t deptsiz;
+-03659         gintmsk_data_t intr_mask = {.d32 = 0 };
+-03660 
+-03661         DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "%s()\n", __func__);
+-03662         DWC_DEBUGPL(DBG_PCD, "ep%d-%s xfer_len=%d xfer_cnt=%d "
+-03663                     "xfer_buff=%p start_xfer_buff=%p, total_len = %d\n",
+-03664                     ep->num, (ep->is_in ? "IN" : "OUT"), ep->xfer_len,
+-03665                     ep->xfer_count, ep->xfer_buff, ep->start_xfer_buff,
+-03666                     ep->total_len);
+-03667         /* IN endpoint */
+-03668         if (ep->is_in == 1) {
+-03669                 dwc_otg_dev_in_ep_regs_t *in_regs =
+-03670                     core_if->dev_if->in_ep_regs[ep->num];
+-03671 
+-03672                 gnptxsts_data_t gtxstatus;
+-03673 
+-03674                 gtxstatus.d32 =
+-03675                     DWC_READ_REG32(&core_if->core_global_regs->gnptxsts);
+-03676 
+-03677                 if (core_if->en_multiple_tx_fifo == 0
+-03678                     && gtxstatus.b.nptxqspcavail == 0
+-03679                     && !core_if->dma_enable) {
+-03680 #ifdef DEBUG
+-03681                         DWC_PRINTF("TX Queue Full (0x%0x)\n", gtxstatus.d32);
+-03682 #endif
+-03683                         return;
+-03684                 }
+-03685 
+-03686                 depctl.d32 = DWC_READ_REG32(&(in_regs->diepctl));
+-03687                 deptsiz.d32 = DWC_READ_REG32(&(in_regs->dieptsiz));
+-03688 
+-03689                 if (ep->maxpacket > ep->maxxfer / MAX_PKT_CNT)
+-03690                         ep->xfer_len += (ep->maxxfer < (ep->total_len - ep->xfer_len)) ?
+-03691                                 ep->maxxfer : (ep->total_len - ep->xfer_len);
+-03692                 else 
+-03693                         ep->xfer_len += (MAX_PKT_CNT * ep->maxpacket < (ep->total_len - ep->xfer_len)) ?
+-03694                                  MAX_PKT_CNT * ep->maxpacket : (ep->total_len - ep->xfer_len);
+-03695 
+-03696 
+-03697                 /* Zero Length Packet? */
+-03698                 if ((ep->xfer_len - ep->xfer_count) == 0) {
+-03699                         deptsiz.b.xfersize = 0;
+-03700                         deptsiz.b.pktcnt = 1;
+-03701                 } else {
+-03702                         /* Program the transfer size and packet count
+-03703                          *      as follows: xfersize = N * maxpacket +
+-03704                          *      short_packet pktcnt = N + (short_packet
+-03705                          *      exist ? 1 : 0) 
+-03706                          */
+-03707                         deptsiz.b.xfersize = ep->xfer_len - ep->xfer_count;
+-03708                         deptsiz.b.pktcnt =
+-03709                             (ep->xfer_len - ep->xfer_count - 1 +
+-03710                              ep->maxpacket) / ep->maxpacket;
+-03711                         if (deptsiz.b.pktcnt > MAX_PKT_CNT) {
+-03712                                 deptsiz.b.pktcnt = MAX_PKT_CNT;
+-03713                                 deptsiz.b.xfersize = deptsiz.b.pktcnt * ep->maxpacket;
+-03714                         } 
+-03715                         if (ep->type == DWC_OTG_EP_TYPE_ISOC) 
+-03716                                 deptsiz.b.mc = deptsiz.b.pktcnt;
+-03717                 }
+-03718 
+-03719                 /* Write the DMA register */
+-03720                 if (core_if->dma_enable) {
+-03721                         if (core_if->dma_desc_enable == 0) {
+-03722                                 if (ep->type != DWC_OTG_EP_TYPE_ISOC)
+-03723                                         deptsiz.b.mc = 1;
+-03724                                 DWC_WRITE_REG32(&in_regs->dieptsiz,
+-03725                                                 deptsiz.d32);
+-03726                                 DWC_WRITE_REG32(&(in_regs->diepdma),
+-03727                                                 (uint32_t) ep->dma_addr);
+-03728                         } else {
+-03729 #ifdef DWC_UTE_CFI
+-03730                                 /* The descriptor chain should be already initialized by now */
+-03731                                 if (ep->buff_mode != BM_STANDARD) {
+-03732                                         DWC_WRITE_REG32(&in_regs->diepdma,
+-03733                                                         ep->descs_dma_addr);
+-03734                                 } else {
+-03735 #endif
+-03736                                         init_dma_desc_chain(core_if, ep);
+-03738                                         DWC_WRITE_REG32(&in_regs->diepdma,
+-03739                                                         ep->dma_desc_addr);
+-03740 #ifdef DWC_UTE_CFI
+-03741                                 }
+-03742 #endif
+-03743                         }
+-03744                 } else {
+-03745                         DWC_WRITE_REG32(&in_regs->dieptsiz, deptsiz.d32);
+-03746                         if (ep->type != DWC_OTG_EP_TYPE_ISOC) {
+-03752                                 if (core_if->en_multiple_tx_fifo == 0) {
+-03753                                         intr_mask.b.nptxfempty = 1;
+-03754                                         DWC_MODIFY_REG32
+-03755                                             (&core_if->core_global_regs->gintmsk,
+-03756                                              intr_mask.d32, intr_mask.d32);
+-03757                                 } else {
+-03758                                         /* Enable the Tx FIFO Empty Interrupt for this EP */
+-03759                                         if (ep->xfer_len > 0) {
+-03760                                                 uint32_t fifoemptymsk = 0;
+-03761                                                 fifoemptymsk = 1 << ep->num;
+-03762                                                 DWC_MODIFY_REG32
+-03763                                                     (&core_if->dev_if->dev_global_regs->dtknqr4_fifoemptymsk,
+-03764                                                      0, fifoemptymsk);
+-03765 
+-03766                                         }
+-03767                                 }
+-03768                         }  else {
+-03769                                          write_isoc_tx_fifo(core_if, ep);
+-03770                         }
+-03771                 }
+-03772                 if (!core_if->core_params->en_multiple_tx_fifo && core_if->dma_enable)
+-03773                         depctl.b.nextep = core_if->nextep_seq[ep->num];
+-03774                 
+-03775                 if (ep->type == DWC_OTG_EP_TYPE_ISOC)
+-03776                 {
+-03777                         dsts_data_t dsts = {.d32 = 0};
+-03778                         if (ep->bInterval == 1) {
+-03779                                 dsts.d32 =
+-03780                                         DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts);
+-03781                                 ep->frame_num = dsts.b.soffn + ep->bInterval;
+-03782                                 if (ep->frame_num > 0x3FFF)
+-03783                                 {
+-03784                                         ep->frm_overrun = 1;
+-03785                                         ep->frame_num &= 0x3FFF;
+-03786                                 } else 
+-03787                                         ep->frm_overrun = 0;
+-03788                                 if (ep->frame_num & 0x1) {
+-03789                                         depctl.b.setd1pid = 1;
+-03790                                 } else {
+-03791                                         depctl.b.setd0pid = 1;
+-03792                                 }
+-03793                         }
+-03794                 }
+-03795                 /* EP enable, IN data in FIFO */
+-03796                 depctl.b.cnak = 1;
+-03797                 depctl.b.epena = 1;
+-03798                 DWC_WRITE_REG32(&in_regs->diepctl, depctl.d32);
+-03799 
+-03800         } else {
+-03801                 /* OUT endpoint */
+-03802                 dwc_otg_dev_out_ep_regs_t *out_regs =
+-03803                     core_if->dev_if->out_ep_regs[ep->num];
+-03804 
+-03805                 depctl.d32 = DWC_READ_REG32(&(out_regs->doepctl));
+-03806                 deptsiz.d32 = DWC_READ_REG32(&(out_regs->doeptsiz));
+-03807 
+-03808                 if (!core_if->dma_desc_enable) {        
+-03809                         if (ep->maxpacket > ep->maxxfer / MAX_PKT_CNT)
+-03810                                 ep->xfer_len += (ep->maxxfer < (ep->total_len - ep->xfer_len)) ?
+-03811                                 ep->maxxfer : (ep->total_len - ep->xfer_len);
+-03812                 else
+-03813                                         ep->xfer_len += (MAX_PKT_CNT * ep->maxpacket < (ep->total_len 
+-03814                                         - ep->xfer_len)) ? MAX_PKT_CNT * ep->maxpacket : (ep->total_len - ep->xfer_len);
+-03815                 }
+-03816 
+-03817                 /* Program the transfer size and packet count as follows:
+-03818                  *
+-03819                  *      pktcnt = N                                                                                
+-03820                  *      xfersize = N * maxpacket
+-03821                  */
+-03822                 if ((ep->xfer_len - ep->xfer_count) == 0) {
+-03823                         /* Zero Length Packet */
+-03824                         deptsiz.b.xfersize = ep->maxpacket;
+-03825                         deptsiz.b.pktcnt = 1;
+-03826                 } else {
+-03827                         deptsiz.b.pktcnt =
+-03828                             (ep->xfer_len - ep->xfer_count +
+-03829                              (ep->maxpacket - 1)) / ep->maxpacket;
+-03830                         if (deptsiz.b.pktcnt > MAX_PKT_CNT) {
+-03831                                 deptsiz.b.pktcnt = MAX_PKT_CNT;
+-03832                         }
+-03833                         if (!core_if->dma_desc_enable) {
+-03834                                 ep->xfer_len =
+-03835                                         deptsiz.b.pktcnt * ep->maxpacket + ep->xfer_count;
+-03836                         }
+-03837                         deptsiz.b.xfersize = ep->xfer_len - ep->xfer_count;
+-03838                 }
+-03839 
+-03840                 DWC_DEBUGPL(DBG_PCDV, "ep%d xfersize=%d pktcnt=%d\n",
+-03841                             ep->num, deptsiz.b.xfersize, deptsiz.b.pktcnt);
+-03842 
+-03843                 if (core_if->dma_enable) {
+-03844                         if (!core_if->dma_desc_enable) {
+-03845                                 DWC_WRITE_REG32(&out_regs->doeptsiz,
+-03846                                                 deptsiz.d32);
+-03847 
+-03848                                 DWC_WRITE_REG32(&(out_regs->doepdma),
+-03849                                                 (uint32_t) ep->dma_addr);
+-03850                         } else {
+-03851 #ifdef DWC_UTE_CFI
+-03852                                 /* The descriptor chain should be already initialized by now */
+-03853                                 if (ep->buff_mode != BM_STANDARD) {
+-03854                                         DWC_WRITE_REG32(&out_regs->doepdma,
+-03855                                                         ep->descs_dma_addr);
+-03856                                 } else {
+-03857 #endif
+-03858 
+-03859                                         if (!ep->xfer_len)
+-03860                                                 ep->xfer_len = ep->total_len;
+-03861                                         init_dma_desc_chain(core_if, ep);
+-03862 
+-03863                                         if (core_if->core_params->dev_out_nak) {
+-03864                                                 if (ep->type == DWC_OTG_EP_TYPE_BULK) {
+-03865                                                         deptsiz.b.pktcnt = (ep->total_len +
+-03866                                                                 (ep->maxpacket - 1)) / ep->maxpacket;
+-03867                                                         deptsiz.b.xfersize = ep->total_len;
+-03868                                                         /* Remember initial value of doeptsiz */
+-03869                                                         core_if->start_doeptsiz_val[ep->num] = deptsiz.d32;
+-03870                                                         DWC_WRITE_REG32(&out_regs->doeptsiz,
+-03871                                                                 deptsiz.d32);                                                                                                   
+-03872                                                 }
+-03873                                         }
+-03875                                         DWC_WRITE_REG32(&out_regs->doepdma,
+-03876                                                         ep->dma_desc_addr);
+-03877 #ifdef DWC_UTE_CFI
+-03878                                 }
+-03879 #endif
+-03880                         }
+-03881                 } else {
+-03882                         DWC_WRITE_REG32(&out_regs->doeptsiz, deptsiz.d32);
+-03883                 }
+-03884 
+-03885                 if (ep->type == DWC_OTG_EP_TYPE_ISOC)
+-03886                 {
+-03887                         dsts_data_t dsts = {.d32 = 0};
+-03888                         if (ep->bInterval == 1) {
+-03889                                 dsts.d32 =
+-03890                                         DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts);
+-03891                                 ep->frame_num = dsts.b.soffn + ep->bInterval;
+-03892                                 if (ep->frame_num > 0x3FFF)
+-03893                                 {
+-03894                                         ep->frm_overrun = 1;
+-03895                                         ep->frame_num &= 0x3FFF;
+-03896                                 } else 
+-03897                                         ep->frm_overrun = 0;
+-03898 
+-03899                                 if (ep->frame_num & 0x1) {
+-03900                                         depctl.b.setd1pid = 1;
+-03901                                 } else {
+-03902                                         depctl.b.setd0pid = 1;
+-03903                                 }
+-03904                         }
+-03905                 }
+-03906 
+-03907                 /* EP enable */
+-03908                 depctl.b.cnak = 1;
+-03909                 depctl.b.epena = 1;
+-03910 
+-03911                 DWC_WRITE_REG32(&out_regs->doepctl, depctl.d32);
+-03912 
+-03913                 DWC_DEBUGPL(DBG_PCD, "DOEPCTL=%08x DOEPTSIZ=%08x\n",
+-03914                             DWC_READ_REG32(&out_regs->doepctl),
+-03915                             DWC_READ_REG32(&out_regs->doeptsiz));
+-03916                 DWC_DEBUGPL(DBG_PCD, "DAINTMSK=%08x GINTMSK=%08x\n",
+-03917                             DWC_READ_REG32(&core_if->dev_if->
+-03918                                            dev_global_regs->daintmsk),
+-03919                             DWC_READ_REG32(&core_if->
+-03920                                            core_global_regs->gintmsk));
+-03921 
+-03922 
+-03923                 /* Timer is scheduling only for out bulk transfers for 
+-03924                  * "Device DDMA OUT NAK Enhancement" feature to inform user 
+-03925                  * about received data payload in case of timeout 
+-03926                  */
+-03927                 if (core_if->core_params->dev_out_nak) {
+-03928                         if (ep->type == DWC_OTG_EP_TYPE_BULK) {
+-03929                                 core_if->ep_xfer_info[ep->num].core_if = core_if;
+-03930                                 core_if->ep_xfer_info[ep->num].ep = ep;
+-03931                                 core_if->ep_xfer_info[ep->num].state = 1;
+-03932 
+-03933                                 /* Start a timer for this transfer. */
+-03934                                 DWC_TIMER_SCHEDULE(core_if->ep_xfer_timer[ep->num], 10000);
+-03935                         }
+-03936                 }
+-03937         }
+-03938 }
+-03939 
+-03948 void dwc_otg_ep_start_zl_transfer(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
+-03949 {
+-03950 
+-03951         depctl_data_t depctl;
+-03952         deptsiz_data_t deptsiz;
+-03953         gintmsk_data_t intr_mask = {.d32 = 0 };
+-03954 
+-03955         DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "%s()\n", __func__);
+-03956         DWC_PRINTF("zero length transfer is called\n");
+-03957 
+-03958         /* IN endpoint */
+-03959         if (ep->is_in == 1) {
+-03960                 dwc_otg_dev_in_ep_regs_t *in_regs =
+-03961                     core_if->dev_if->in_ep_regs[ep->num];
+-03962 
+-03963                 depctl.d32 = DWC_READ_REG32(&(in_regs->diepctl));
+-03964                 deptsiz.d32 = DWC_READ_REG32(&(in_regs->dieptsiz));
+-03965 
+-03966                 deptsiz.b.xfersize = 0;
+-03967                 deptsiz.b.pktcnt = 1;
+-03968 
+-03969                 /* Write the DMA register */
+-03970                 if (core_if->dma_enable) {
+-03971                         if (core_if->dma_desc_enable == 0) {
+-03972                                 deptsiz.b.mc = 1;
+-03973                                 DWC_WRITE_REG32(&in_regs->dieptsiz,
+-03974                                                 deptsiz.d32);
+-03975                                 DWC_WRITE_REG32(&(in_regs->diepdma),
+-03976                                                 (uint32_t) ep->dma_addr);
+-03977                         }
+-03978                 } else {
+-03979                         DWC_WRITE_REG32(&in_regs->dieptsiz, deptsiz.d32);
+-03985                         if (core_if->en_multiple_tx_fifo == 0) {
+-03986                                 intr_mask.b.nptxfempty = 1;
+-03987                                 DWC_MODIFY_REG32(&core_if->
+-03988                                                  core_global_regs->gintmsk,
+-03989                                                  intr_mask.d32, intr_mask.d32);
+-03990                         } else {
+-03991                                 /* Enable the Tx FIFO Empty Interrupt for this EP */
+-03992                                 if (ep->xfer_len > 0) {
+-03993                                         uint32_t fifoemptymsk = 0;
+-03994                                         fifoemptymsk = 1 << ep->num;
+-03995                                         DWC_MODIFY_REG32(&core_if->
+-03996                                                          dev_if->dev_global_regs->dtknqr4_fifoemptymsk,
+-03997                                                          0, fifoemptymsk);
+-03998                                 }
+-03999                         }
+-04000                 }
+-04001 
+-04002                 if (!core_if->core_params->en_multiple_tx_fifo && core_if->dma_enable)
+-04003                         depctl.b.nextep = core_if->nextep_seq[ep->num];
+-04004                 /* EP enable, IN data in FIFO */
+-04005                 depctl.b.cnak = 1;
+-04006                 depctl.b.epena = 1;
+-04007                 DWC_WRITE_REG32(&in_regs->diepctl, depctl.d32);
+-04008 
+-04009         } else {
+-04010                 /* OUT endpoint */
+-04011                 dwc_otg_dev_out_ep_regs_t *out_regs =
+-04012                     core_if->dev_if->out_ep_regs[ep->num];
+-04013 
+-04014                 depctl.d32 = DWC_READ_REG32(&(out_regs->doepctl));
+-04015                 deptsiz.d32 = DWC_READ_REG32(&(out_regs->doeptsiz));
+-04016 
+-04017                 /* Zero Length Packet */
+-04018                 deptsiz.b.xfersize = ep->maxpacket;
+-04019                 deptsiz.b.pktcnt = 1;
+-04020 
+-04021                 if (core_if->dma_enable) {
+-04022                         if (!core_if->dma_desc_enable) {
+-04023                                 DWC_WRITE_REG32(&out_regs->doeptsiz,
+-04024                                                 deptsiz.d32);
+-04025 
+-04026                                 DWC_WRITE_REG32(&(out_regs->doepdma),
+-04027                                                 (uint32_t) ep->dma_addr);
+-04028                         }
+-04029                 } else {
+-04030                         DWC_WRITE_REG32(&out_regs->doeptsiz, deptsiz.d32);
+-04031                 }
+-04032 
+-04033                 /* EP enable */
+-04034                 depctl.b.cnak = 1;
+-04035                 depctl.b.epena = 1;
+-04036 
+-04037                 DWC_WRITE_REG32(&out_regs->doepctl, depctl.d32);
+-04038 
+-04039         }
+-04040 }
+-04041 
+-04051 void dwc_otg_ep0_start_transfer(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
+-04052 {
+-04053         depctl_data_t depctl;
+-04054         deptsiz0_data_t deptsiz;
+-04055         gintmsk_data_t intr_mask = {.d32 = 0 };
+-04056         dwc_otg_dev_dma_desc_t *dma_desc;
+-04057 
+-04058         DWC_DEBUGPL(DBG_PCD, "ep%d-%s xfer_len=%d xfer_cnt=%d "
+-04059                     "xfer_buff=%p start_xfer_buff=%p \n",
+-04060                     ep->num, (ep->is_in ? "IN" : "OUT"), ep->xfer_len,
+-04061                     ep->xfer_count, ep->xfer_buff, ep->start_xfer_buff);
+-04062 
+-04063         ep->total_len = ep->xfer_len;
+-04064 
+-04065         /* IN endpoint */
+-04066         if (ep->is_in == 1) {
+-04067                 dwc_otg_dev_in_ep_regs_t *in_regs =
+-04068                     core_if->dev_if->in_ep_regs[0];
+-04069 
+-04070                 gnptxsts_data_t gtxstatus;
+-04071 
+-04072                 gtxstatus.d32 =
+-04073                     DWC_READ_REG32(&core_if->core_global_regs->gnptxsts);
+-04074 
+-04075                 if (core_if->en_multiple_tx_fifo == 0
+-04076                     && gtxstatus.b.nptxqspcavail == 0
+-04077                     && !core_if->dma_enable) {
+-04078 #ifdef DEBUG
+-04079                         deptsiz.d32 = DWC_READ_REG32(&in_regs->dieptsiz);
+-04080                         DWC_DEBUGPL(DBG_PCD, "DIEPCTL0=%0x\n",
+-04081                                     DWC_READ_REG32(&in_regs->diepctl));
+-04082                         DWC_DEBUGPL(DBG_PCD, "DIEPTSIZ0=%0x (sz=%d, pcnt=%d)\n",
+-04083                                     deptsiz.d32,
+-04084                                     deptsiz.b.xfersize, deptsiz.b.pktcnt);
+-04085                         DWC_PRINTF("TX Queue or FIFO Full (0x%0x)\n",
+-04086                                    gtxstatus.d32);
+-04087 #endif
+-04088                         return;
+-04089                 }
+-04090 
+-04091                 depctl.d32 = DWC_READ_REG32(&in_regs->diepctl);
+-04092                 deptsiz.d32 = DWC_READ_REG32(&in_regs->dieptsiz);
+-04093 
+-04094                 /* Zero Length Packet? */
+-04095                 if (ep->xfer_len == 0) {
+-04096                         deptsiz.b.xfersize = 0;
+-04097                         deptsiz.b.pktcnt = 1;
+-04098                 } else {
+-04099                         /* Program the transfer size and packet count
+-04100                          *      as follows: xfersize = N * maxpacket +
+-04101                          *      short_packet pktcnt = N + (short_packet
+-04102                          *      exist ? 1 : 0) 
+-04103                          */
+-04104                         if (ep->xfer_len > ep->maxpacket) {
+-04105                                 ep->xfer_len = ep->maxpacket;
+-04106                                 deptsiz.b.xfersize = ep->maxpacket;
+-04107                         } else {
+-04108                                 deptsiz.b.xfersize = ep->xfer_len;
+-04109                         }
+-04110                         deptsiz.b.pktcnt = 1;
+-04111 
+-04112                 }
+-04113                 DWC_DEBUGPL(DBG_PCDV,
+-04114                             "IN len=%d  xfersize=%d pktcnt=%d [%08x]\n",
+-04115                             ep->xfer_len, deptsiz.b.xfersize, deptsiz.b.pktcnt,
+-04116                             deptsiz.d32);
+-04117 
+-04118                 /* Write the DMA register */
+-04119                 if (core_if->dma_enable) {
+-04120                         if (core_if->dma_desc_enable == 0) {
+-04121                                 DWC_WRITE_REG32(&in_regs->dieptsiz,
+-04122                                                 deptsiz.d32);
+-04123 
+-04124                                 DWC_WRITE_REG32(&(in_regs->diepdma),
+-04125                                                 (uint32_t) ep->dma_addr);
+-04126                         } else {
+-04127                                 dma_desc = core_if->dev_if->in_desc_addr;
+-04128 
+-04130                                 dma_desc->status.b.bs = BS_HOST_BUSY;
+-04131                                 dma_desc->status.b.l = 1;
+-04132                                 dma_desc->status.b.ioc = 1;
+-04133                                 dma_desc->status.b.sp =
+-04134                                     (ep->xfer_len == ep->maxpacket) ? 0 : 1;
+-04135                                 dma_desc->status.b.bytes = ep->xfer_len;
+-04136                                 dma_desc->buf = ep->dma_addr;
+-04137                                 dma_desc->status.b.sts = 0;
+-04138                                 dma_desc->status.b.bs = BS_HOST_READY;
+-04139 
+-04141                                 DWC_WRITE_REG32(&in_regs->diepdma,
+-04142                                                 core_if->
+-04143                                                 dev_if->dma_in_desc_addr);
+-04144                         }
+-04145                 } else {
+-04146                         DWC_WRITE_REG32(&in_regs->dieptsiz, deptsiz.d32);
+-04147                 }
+-04148 
+-04149                 if (!core_if->core_params->en_multiple_tx_fifo && core_if->dma_enable)
+-04150                         depctl.b.nextep = core_if->nextep_seq[ep->num];
+-04151                 /* EP enable, IN data in FIFO */
+-04152                 depctl.b.cnak = 1;
+-04153                 depctl.b.epena = 1;
+-04154                 DWC_WRITE_REG32(&in_regs->diepctl, depctl.d32);
+-04155 
+-04160                 if (!core_if->dma_enable) {
+-04161                         if (core_if->en_multiple_tx_fifo == 0) {
+-04162                                 intr_mask.b.nptxfempty = 1;
+-04163                                 DWC_MODIFY_REG32(&core_if->
+-04164                                                  core_global_regs->gintmsk,
+-04165                                                  intr_mask.d32, intr_mask.d32);
+-04166                         } else {
+-04167                                 /* Enable the Tx FIFO Empty Interrupt for this EP */
+-04168                                 if (ep->xfer_len > 0) {
+-04169                                         uint32_t fifoemptymsk = 0;
+-04170                                         fifoemptymsk |= 1 << ep->num;
+-04171                                         DWC_MODIFY_REG32(&core_if->
+-04172                                                          dev_if->dev_global_regs->dtknqr4_fifoemptymsk,
+-04173                                                          0, fifoemptymsk);
+-04174                                 }
+-04175                         }
+-04176                 }
+-04177         } else {
+-04178                 /* OUT endpoint */
+-04179                 dwc_otg_dev_out_ep_regs_t *out_regs =
+-04180                     core_if->dev_if->out_ep_regs[0];
+-04181 
+-04182                 depctl.d32 = DWC_READ_REG32(&out_regs->doepctl);
+-04183                 deptsiz.d32 = DWC_READ_REG32(&out_regs->doeptsiz);
+-04184 
+-04185                 /* Program the transfer size and packet count as follows:
+-04186                  *      xfersize = N * (maxpacket + 4 - (maxpacket % 4))
+-04187                  *      pktcnt = N                                                                                      */
+-04188                 /* Zero Length Packet */
+-04189                 deptsiz.b.xfersize = ep->maxpacket;
+-04190                 deptsiz.b.pktcnt = 1;
+-04191 
+-04192                 DWC_DEBUGPL(DBG_PCDV, "len=%d  xfersize=%d pktcnt=%d\n",
+-04193                             ep->xfer_len, deptsiz.b.xfersize, deptsiz.b.pktcnt);
+-04194 
+-04195                 if (core_if->dma_enable) {
+-04196                         if (!core_if->dma_desc_enable) {
+-04197                                 DWC_WRITE_REG32(&out_regs->doeptsiz,
+-04198                                                 deptsiz.d32);
+-04199 
+-04200                                 DWC_WRITE_REG32(&(out_regs->doepdma),
+-04201                                                 (uint32_t) ep->dma_addr);
+-04202                         } else {
+-04203                                 dma_desc = core_if->dev_if->out_desc_addr;
+-04204 
+-04206                                 dma_desc->status.b.bs = BS_HOST_BUSY;
+-04207                                 dma_desc->status.b.l = 1;
+-04208                                 dma_desc->status.b.ioc = 1;
+-04209                                 dma_desc->status.b.bytes = ep->maxpacket;
+-04210                                 dma_desc->buf = ep->dma_addr;
+-04211                                 dma_desc->status.b.sts = 0;
+-04212                                 dma_desc->status.b.bs = BS_HOST_READY;
+-04213 
+-04215                                 DWC_WRITE_REG32(&out_regs->doepdma,
+-04216                                                 core_if->
+-04217                                                 dev_if->dma_out_desc_addr);
+-04218                         }
+-04219                 } else {
+-04220                         DWC_WRITE_REG32(&out_regs->doeptsiz, deptsiz.d32);
+-04221                 }
+-04222 
+-04223                 /* EP enable */
+-04224                 depctl.b.cnak = 1;
+-04225                 depctl.b.epena = 1;
+-04226                 DWC_WRITE_REG32(&(out_regs->doepctl), depctl.d32);
+-04227         }
+-04228 }
+-04229 
+-04239 void dwc_otg_ep0_continue_transfer(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
+-04240 {
+-04241         depctl_data_t depctl;
+-04242         deptsiz0_data_t deptsiz;
+-04243         gintmsk_data_t intr_mask = {.d32 = 0 };
+-04244         dwc_otg_dev_dma_desc_t *dma_desc;
+-04245 
+-04246         if (ep->is_in == 1) {
+-04247                 dwc_otg_dev_in_ep_regs_t *in_regs =
+-04248                     core_if->dev_if->in_ep_regs[0];
+-04249                 gnptxsts_data_t tx_status = {.d32 = 0 };
+-04250 
+-04251                 tx_status.d32 =
+-04252                     DWC_READ_REG32(&core_if->core_global_regs->gnptxsts);
+-04256                 depctl.d32 = DWC_READ_REG32(&in_regs->diepctl);
+-04257                 deptsiz.d32 = DWC_READ_REG32(&in_regs->dieptsiz);
+-04258 
+-04259                 /* Program the transfer size and packet count
+-04260                  *      as follows: xfersize = N * maxpacket +
+-04261                  *      short_packet pktcnt = N + (short_packet
+-04262                  *      exist ? 1 : 0) 
+-04263                  */
+-04264 
+-04265                 if (core_if->dma_desc_enable == 0) {
+-04266                         deptsiz.b.xfersize =
+-04267                             (ep->total_len - ep->xfer_count) >
+-04268                             ep->maxpacket ? ep->maxpacket : (ep->total_len -
+-04269                                                              ep->xfer_count);
+-04270                         deptsiz.b.pktcnt = 1;
+-04271                         if (core_if->dma_enable == 0) {
+-04272                                 ep->xfer_len += deptsiz.b.xfersize;
+-04273                         } else {
+-04274                                 ep->xfer_len = deptsiz.b.xfersize;
+-04275                         }
+-04276                         DWC_WRITE_REG32(&in_regs->dieptsiz, deptsiz.d32);
+-04277                 } else {
+-04278                         ep->xfer_len =
+-04279                             (ep->total_len - ep->xfer_count) >
+-04280                             ep->maxpacket ? ep->maxpacket : (ep->total_len -
+-04281                                                              ep->xfer_count);
+-04282 
+-04283                         dma_desc = core_if->dev_if->in_desc_addr;
+-04284 
+-04286                         dma_desc->status.b.bs = BS_HOST_BUSY;
+-04287                         dma_desc->status.b.l = 1;
+-04288                         dma_desc->status.b.ioc = 1;
+-04289                         dma_desc->status.b.sp =
+-04290                             (ep->xfer_len == ep->maxpacket) ? 0 : 1;
+-04291                         dma_desc->status.b.bytes = ep->xfer_len;
+-04292                         dma_desc->buf = ep->dma_addr;
+-04293                         dma_desc->status.b.sts = 0;
+-04294                         dma_desc->status.b.bs = BS_HOST_READY;
+-04295 
+-04297                         DWC_WRITE_REG32(&in_regs->diepdma,
+-04298                                         core_if->dev_if->dma_in_desc_addr);
+-04299                 }
+-04300 
+-04301                 DWC_DEBUGPL(DBG_PCDV,
+-04302                             "IN len=%d  xfersize=%d pktcnt=%d [%08x]\n",
+-04303                             ep->xfer_len, deptsiz.b.xfersize, deptsiz.b.pktcnt,
+-04304                             deptsiz.d32);
+-04305 
+-04306                 /* Write the DMA register */
+-04307                 if (core_if->hwcfg2.b.architecture == DWC_INT_DMA_ARCH) {
+-04308                         if (core_if->dma_desc_enable == 0)
+-04309                                 DWC_WRITE_REG32(&(in_regs->diepdma),
+-04310                                                 (uint32_t) ep->dma_addr);
+-04311                 }
+-04312                 if (!core_if->core_params->en_multiple_tx_fifo && core_if->dma_enable)
+-04313                         depctl.b.nextep = core_if->nextep_seq[ep->num];
+-04314                 /* EP enable, IN data in FIFO */
+-04315                 depctl.b.cnak = 1;
+-04316                 depctl.b.epena = 1;
+-04317                 DWC_WRITE_REG32(&in_regs->diepctl, depctl.d32);
+-04318 
+-04323                 if (!core_if->dma_enable) {
+-04324                         if (core_if->en_multiple_tx_fifo == 0) {
+-04325                                 /* First clear it from GINTSTS */
+-04326                                 intr_mask.b.nptxfempty = 1;
+-04327                                 DWC_MODIFY_REG32(&core_if->
+-04328                                                  core_global_regs->gintmsk,
+-04329                                                  intr_mask.d32, intr_mask.d32);
+-04330 
+-04331                         } else {
+-04332                                 /* Enable the Tx FIFO Empty Interrupt for this EP */
+-04333                                 if (ep->xfer_len > 0) {
+-04334                                         uint32_t fifoemptymsk = 0;
+-04335                                         fifoemptymsk |= 1 << ep->num;
+-04336                                         DWC_MODIFY_REG32(&core_if->
+-04337                                                          dev_if->dev_global_regs->dtknqr4_fifoemptymsk,
+-04338                                                          0, fifoemptymsk);
+-04339                                 }
+-04340                         }
+-04341                 }
+-04342         } else {
+-04343                 dwc_otg_dev_out_ep_regs_t *out_regs =
+-04344                     core_if->dev_if->out_ep_regs[0];
+-04345 
+-04346                 depctl.d32 = DWC_READ_REG32(&out_regs->doepctl);
+-04347                 deptsiz.d32 = DWC_READ_REG32(&out_regs->doeptsiz);
+-04348 
+-04349                 /* Program the transfer size and packet count
+-04350                  *      as follows: xfersize = N * maxpacket +
+-04351                  *      short_packet pktcnt = N + (short_packet
+-04352                  *      exist ? 1 : 0) 
+-04353                  */
+-04354                 deptsiz.b.xfersize = ep->maxpacket;
+-04355                 deptsiz.b.pktcnt = 1;
+-04356 
+-04357                 if (core_if->dma_desc_enable == 0) {
+-04358                         DWC_WRITE_REG32(&out_regs->doeptsiz, deptsiz.d32);
+-04359                 } else {
+-04360                         dma_desc = core_if->dev_if->out_desc_addr;
+-04361 
+-04363                         dma_desc->status.b.bs = BS_HOST_BUSY;
+-04364                         dma_desc->status.b.l = 1;
+-04365                         dma_desc->status.b.ioc = 1;
+-04366                         dma_desc->status.b.bytes = ep->maxpacket;
+-04367                         dma_desc->buf = ep->dma_addr;
+-04368                         dma_desc->status.b.sts = 0;
+-04369                         dma_desc->status.b.bs = BS_HOST_READY;
+-04370 
+-04372                         DWC_WRITE_REG32(&out_regs->doepdma,
+-04373                                         core_if->dev_if->dma_out_desc_addr);
+-04374                 }
+-04375 
+-04376                 DWC_DEBUGPL(DBG_PCDV,
+-04377                             "IN len=%d  xfersize=%d pktcnt=%d [%08x]\n",
+-04378                             ep->xfer_len, deptsiz.b.xfersize, deptsiz.b.pktcnt,
+-04379                             deptsiz.d32);
+-04380 
+-04381                 /* Write the DMA register */
+-04382                 if (core_if->hwcfg2.b.architecture == DWC_INT_DMA_ARCH) {
+-04383                         if (core_if->dma_desc_enable == 0)
+-04384                                 DWC_WRITE_REG32(&(out_regs->doepdma),
+-04385                                                 (uint32_t) ep->dma_addr);
+-04386 
+-04387                 }
+-04388 
+-04389                 /* EP enable, IN data in FIFO */
+-04390                 depctl.b.cnak = 1;
+-04391                 depctl.b.epena = 1;
+-04392                 DWC_WRITE_REG32(&out_regs->doepctl, depctl.d32);
+-04393 
+-04394         }
+-04395 }
+-04396 
+-04397 #ifdef DEBUG
+-04398 void dump_msg(const u8 * buf, unsigned int length)
+-04399 {
+-04400         unsigned int start, num, i;
+-04401         char line[52], *p;
+-04402 
+-04403         if (length >= 512)
+-04404                 return;
+-04405         start = 0;
+-04406         while (length > 0) {
+-04407                 num = length < 16u ? length : 16u;
+-04408                 p = line;
+-04409                 for (i = 0; i < num; ++i) {
+-04410                         if (i == 8)
+-04411                                 *p++ = ' ';
+-04412                         DWC_SPRINTF(p, " %02x", buf[i]);
+-04413                         p += 3;
+-04414                 }
+-04415                 *p = 0;
+-04416                 DWC_PRINTF("%6x: %s\n", start, line);
+-04417                 buf += num;
+-04418                 start += num;
+-04419                 length -= num;
+-04420         }
+-04421 }
+-04422 #else
+-04423 static inline void dump_msg(const u8 * buf, unsigned int length)
+-04424 {
+-04425 }
+-04426 #endif
+-04427 
+-04438 void dwc_otg_ep_write_packet(dwc_otg_core_if_t * core_if, dwc_ep_t * ep,
+-04439                              int dma)
+-04440 {
+-04456         uint32_t i;
+-04457         uint32_t byte_count;
+-04458         uint32_t dword_count;
+-04459         uint32_t *fifo;
+-04460         uint32_t *data_buff = (uint32_t *) ep->xfer_buff;
+-04461 
+-04462         DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "%s(%p,%p)\n", __func__, core_if,
+-04463                     ep);
+-04464         if (ep->xfer_count >= ep->xfer_len) {
+-04465                 DWC_WARN("%s() No data for EP%d!!!\n", __func__, ep->num);
+-04466                 return;
+-04467         }
+-04468 
+-04469         /* Find the byte length of the packet either short packet or MPS */
+-04470         if ((ep->xfer_len - ep->xfer_count) < ep->maxpacket) {
+-04471                 byte_count = ep->xfer_len - ep->xfer_count;
+-04472         } else {
+-04473                 byte_count = ep->maxpacket;
+-04474         }
+-04475 
+-04476         /* Find the DWORD length, padded by extra bytes as neccessary if MPS
+-04477          * is not a multiple of DWORD */
+-04478         dword_count = (byte_count + 3) / 4;
+-04479 
+-04480 #ifdef VERBOSE
+-04481         dump_msg(ep->xfer_buff, byte_count);
+-04482 #endif
+-04483 
+-04487         fifo = core_if->data_fifo[ep->num];
+-04488 
+-04489         DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "fifo=%p buff=%p *p=%08x bc=%d\n",
+-04490                     fifo, data_buff, *data_buff, byte_count);
+-04491 
+-04492         if (!dma) {
+-04493                 for (i = 0; i < dword_count; i++, data_buff++) {
+-04494                         DWC_WRITE_REG32(fifo, *data_buff);
+-04495                 }
+-04496         }
+-04497 
+-04498         ep->xfer_count += byte_count;
+-04499         ep->xfer_buff += byte_count;
+-04500         ep->dma_addr += byte_count;
+-04501 }
+-04502 
+-04509 void dwc_otg_ep_set_stall(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
+-04510 {
+-04511         depctl_data_t depctl;
+-04512         volatile uint32_t *depctl_addr;
+-04513 
+-04514         DWC_DEBUGPL(DBG_PCD, "%s ep%d-%s\n", __func__, ep->num,
+-04515                     (ep->is_in ? "IN" : "OUT"));
+-04516 
+-04517         if (ep->is_in == 1) {
+-04518                 depctl_addr = &(core_if->dev_if->in_ep_regs[ep->num]->diepctl);
+-04519                 depctl.d32 = DWC_READ_REG32(depctl_addr);
+-04520 
+-04521                 /* set the disable and stall bits */
+-04522                 if (depctl.b.epena) {
+-04523                         depctl.b.epdis = 1;
+-04524                 }
+-04525                 depctl.b.stall = 1;
+-04526                 DWC_WRITE_REG32(depctl_addr, depctl.d32);
+-04527         } else {
+-04528                 depctl_addr = &(core_if->dev_if->out_ep_regs[ep->num]->doepctl);
+-04529                 depctl.d32 = DWC_READ_REG32(depctl_addr);
+-04530 
+-04531                 /* set the stall bit */
+-04532                 depctl.b.stall = 1;
+-04533                 DWC_WRITE_REG32(depctl_addr, depctl.d32);
+-04534         }
+-04535 
+-04536         DWC_DEBUGPL(DBG_PCD, "DEPCTL=%0x\n", DWC_READ_REG32(depctl_addr));
+-04537 
+-04538         return;
+-04539 }
+-04540 
+-04547 void dwc_otg_ep_clear_stall(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
+-04548 {
+-04549         depctl_data_t depctl;
+-04550         volatile uint32_t *depctl_addr;
+-04551 
+-04552         DWC_DEBUGPL(DBG_PCD, "%s ep%d-%s\n", __func__, ep->num,
+-04553                     (ep->is_in ? "IN" : "OUT"));
+-04554 
+-04555         if (ep->is_in == 1) {
+-04556                 depctl_addr = &(core_if->dev_if->in_ep_regs[ep->num]->diepctl);
+-04557         } else {
+-04558                 depctl_addr = &(core_if->dev_if->out_ep_regs[ep->num]->doepctl);
+-04559         }
+-04560 
+-04561         depctl.d32 = DWC_READ_REG32(depctl_addr);
+-04562 
+-04563         /* clear the stall bits */
+-04564         depctl.b.stall = 0;
+-04565 
+-04566         /*
+-04567          * USB Spec 9.4.5: For endpoints using data toggle, regardless
+-04568          * of whether an endpoint has the Halt feature set, a
+-04569          * ClearFeature(ENDPOINT_HALT) request always results in the
+-04570          * data toggle being reinitialized to DATA0.
+-04571          */
+-04572         if (ep->type == DWC_OTG_EP_TYPE_INTR ||
+-04573             ep->type == DWC_OTG_EP_TYPE_BULK) {
+-04574                 depctl.b.setd0pid = 1;  /* DATA0 */
+-04575         }
+-04576 
+-04577         DWC_WRITE_REG32(depctl_addr, depctl.d32);
+-04578         DWC_DEBUGPL(DBG_PCD, "DEPCTL=%0x\n", DWC_READ_REG32(depctl_addr));
+-04579         return;
+-04580 }
+-04581 
+-04590 void dwc_otg_read_packet(dwc_otg_core_if_t * core_if,
+-04591                          uint8_t * dest, uint16_t bytes)
+-04592 {
+-04593         int i;
+-04594         int word_count = (bytes + 3) / 4;
+-04595 
+-04596         volatile uint32_t *fifo = core_if->data_fifo[0];
+-04597         uint32_t *data_buff = (uint32_t *) dest;
+-04598 
+-04605         DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "%s(%p,%p,%d)\n", __func__,
+-04606                     core_if, dest, bytes);
+-04607 
+-04608         for (i = 0; i < word_count; i++, data_buff++) {
+-04609                 *data_buff = DWC_READ_REG32(fifo);
+-04610         }
+-04611 
+-04612         return;
+-04613 }
+-04614 
+-04620 void dwc_otg_dump_dev_registers(dwc_otg_core_if_t * core_if)
+-04621 {
+-04622         int i;
+-04623         volatile uint32_t *addr;
+-04624 
+-04625         DWC_PRINTF("Device Global Registers\n");
+-04626         addr = &core_if->dev_if->dev_global_regs->dcfg;
+-04627         DWC_PRINTF("DCFG                 @0x%08lX : 0x%08X\n", (unsigned long) addr,
+-04628                    DWC_READ_REG32(addr));
+-04629         addr = &core_if->dev_if->dev_global_regs->dctl;
+-04630         DWC_PRINTF("DCTL                 @0x%08lX : 0x%08X\n", (unsigned long) addr,
+-04631                    DWC_READ_REG32(addr));
+-04632         addr = &core_if->dev_if->dev_global_regs->dsts;
+-04633         DWC_PRINTF("DSTS                 @0x%08lX : 0x%08X\n", (unsigned long) addr,
+-04634                    DWC_READ_REG32(addr));
+-04635         addr = &core_if->dev_if->dev_global_regs->diepmsk;
+-04636         DWC_PRINTF("DIEPMSK      @0x%08lX : 0x%08X\n", (unsigned long)addr,
+-04637                    DWC_READ_REG32(addr));
+-04638         addr = &core_if->dev_if->dev_global_regs->doepmsk;
+-04639         DWC_PRINTF("DOEPMSK      @0x%08lX : 0x%08X\n", (unsigned long)addr,
+-04640                    DWC_READ_REG32(addr));
+-04641         addr = &core_if->dev_if->dev_global_regs->daint;
+-04642         DWC_PRINTF("DAINT        @0x%08lX : 0x%08X\n", (unsigned long)addr,
+-04643                    DWC_READ_REG32(addr));
+-04644         addr = &core_if->dev_if->dev_global_regs->daintmsk;
+-04645         DWC_PRINTF("DAINTMSK     @0x%08lX : 0x%08X\n", (unsigned long)addr,
+-04646                    DWC_READ_REG32(addr));
+-04647         addr = &core_if->dev_if->dev_global_regs->dtknqr1;
+-04648         DWC_PRINTF("DTKNQR1      @0x%08lX : 0x%08X\n", (unsigned long)addr,
+-04649                    DWC_READ_REG32(addr));
+-04650         if (core_if->hwcfg2.b.dev_token_q_depth > 6) {
+-04651                 addr = &core_if->dev_if->dev_global_regs->dtknqr2;
+-04652                 DWC_PRINTF("DTKNQR2      @0x%08lX : 0x%08X\n",
+-04653                            (unsigned long)addr, DWC_READ_REG32(addr));
+-04654         }
+-04655 
+-04656         addr = &core_if->dev_if->dev_global_regs->dvbusdis;
+-04657         DWC_PRINTF("DVBUSID      @0x%08lX : 0x%08X\n", (unsigned long)addr,
+-04658                    DWC_READ_REG32(addr));
+-04659 
+-04660         addr = &core_if->dev_if->dev_global_regs->dvbuspulse;
+-04661         DWC_PRINTF("DVBUSPULSE  @0x%08lX : 0x%08X\n",
+-04662                    (unsigned long)addr, DWC_READ_REG32(addr));
+-04663 
+-04664         addr = &core_if->dev_if->dev_global_regs->dtknqr3_dthrctl;
+-04665         DWC_PRINTF("DTKNQR3_DTHRCTL      @0x%08lX : 0x%08X\n",
+-04666                    (unsigned long)addr, DWC_READ_REG32(addr));
+-04667 
+-04668         if (core_if->hwcfg2.b.dev_token_q_depth > 22) {
+-04669                 addr = &core_if->dev_if->dev_global_regs->dtknqr4_fifoemptymsk;
+-04670                 DWC_PRINTF("DTKNQR4      @0x%08lX : 0x%08X\n",
+-04671                            (unsigned long)addr, DWC_READ_REG32(addr));
+-04672         }
+-04673 
+-04674         addr = &core_if->dev_if->dev_global_regs->dtknqr4_fifoemptymsk;
+-04675         DWC_PRINTF("FIFOEMPMSK   @0x%08lX : 0x%08X\n", (unsigned long)addr,
+-04676                    DWC_READ_REG32(addr));
+-04677 
+-04678         if (core_if->hwcfg2.b.multi_proc_int) {
+-04679 
+-04680                 addr = &core_if->dev_if->dev_global_regs->deachint;
+-04681                 DWC_PRINTF("DEACHINT     @0x%08lX : 0x%08X\n",
+-04682                            (unsigned long)addr, DWC_READ_REG32(addr));
+-04683                 addr = &core_if->dev_if->dev_global_regs->deachintmsk;
+-04684                 DWC_PRINTF("DEACHINTMSK  @0x%08lX : 0x%08X\n",
+-04685                            (unsigned long)addr, DWC_READ_REG32(addr));
+-04686 
+-04687                 for (i = 0; i <= core_if->dev_if->num_in_eps; i++) {
+-04688                         addr =
+-04689                             &core_if->dev_if->dev_global_regs->
+-04690                             diepeachintmsk[i];
+-04691                         DWC_PRINTF("DIEPEACHINTMSK[%d]   @0x%08lX : 0x%08X\n",
+-04692                                    i, (unsigned long)addr,
+-04693                                    DWC_READ_REG32(addr));
+-04694                 }
+-04695 
+-04696                 for (i = 0; i <= core_if->dev_if->num_out_eps; i++) {
+-04697                         addr =
+-04698                             &core_if->dev_if->dev_global_regs->
+-04699                             doepeachintmsk[i];
+-04700                         DWC_PRINTF("DOEPEACHINTMSK[%d]   @0x%08lX : 0x%08X\n",
+-04701                                    i, (unsigned long)addr,
+-04702                                    DWC_READ_REG32(addr));
+-04703                 }
+-04704         }
+-04705 
+-04706         for (i = 0; i <= core_if->dev_if->num_in_eps; i++) {
+-04707                 DWC_PRINTF("Device IN EP %d Registers\n", i);
+-04708                 addr = &core_if->dev_if->in_ep_regs[i]->diepctl;
+-04709                 DWC_PRINTF("DIEPCTL      @0x%08lX : 0x%08X\n",
+-04710                            (unsigned long)addr, DWC_READ_REG32(addr));
+-04711                 addr = &core_if->dev_if->in_ep_regs[i]->diepint;
+-04712                 DWC_PRINTF("DIEPINT      @0x%08lX : 0x%08X\n",
+-04713                            (unsigned long)addr, DWC_READ_REG32(addr));
+-04714                 addr = &core_if->dev_if->in_ep_regs[i]->dieptsiz;
+-04715                 DWC_PRINTF("DIETSIZ      @0x%08lX : 0x%08X\n",
+-04716                            (unsigned long)addr, DWC_READ_REG32(addr));
+-04717                 addr = &core_if->dev_if->in_ep_regs[i]->diepdma;
+-04718                 DWC_PRINTF("DIEPDMA      @0x%08lX : 0x%08X\n",
+-04719                            (unsigned long)addr, DWC_READ_REG32(addr));
+-04720                 addr = &core_if->dev_if->in_ep_regs[i]->dtxfsts;
+-04721                 DWC_PRINTF("DTXFSTS      @0x%08lX : 0x%08X\n",
+-04722                            (unsigned long)addr, DWC_READ_REG32(addr));
+-04723                 addr = &core_if->dev_if->in_ep_regs[i]->diepdmab;
+-04724                 DWC_PRINTF("DIEPDMAB     @0x%08lX : 0x%08X\n",
+-04725                            (unsigned long)addr, 0 /*DWC_READ_REG32(addr) */ );
+-04726         }
+-04727 
+-04728         for (i = 0; i <= core_if->dev_if->num_out_eps; i++) {
+-04729                 DWC_PRINTF("Device OUT EP %d Registers\n", i);
+-04730                 addr = &core_if->dev_if->out_ep_regs[i]->doepctl;
+-04731                 DWC_PRINTF("DOEPCTL      @0x%08lX : 0x%08X\n",
+-04732                            (unsigned long)addr, DWC_READ_REG32(addr));
+-04733                 addr = &core_if->dev_if->out_ep_regs[i]->doepint;
+-04734                 DWC_PRINTF("DOEPINT      @0x%08lX : 0x%08X\n",
+-04735                            (unsigned long)addr, DWC_READ_REG32(addr));
+-04736                 addr = &core_if->dev_if->out_ep_regs[i]->doeptsiz;
+-04737                 DWC_PRINTF("DOETSIZ      @0x%08lX : 0x%08X\n",
+-04738                            (unsigned long)addr, DWC_READ_REG32(addr));
+-04739                 addr = &core_if->dev_if->out_ep_regs[i]->doepdma;
+-04740                 DWC_PRINTF("DOEPDMA      @0x%08lX : 0x%08X\n",
+-04741                            (unsigned long)addr, DWC_READ_REG32(addr));
+-04742                 if (core_if->dma_enable) {      /* Don't access this register in SLAVE mode */
+-04743                         addr = &core_if->dev_if->out_ep_regs[i]->doepdmab;
+-04744                         DWC_PRINTF("DOEPDMAB     @0x%08lX : 0x%08X\n",
+-04745                                    (unsigned long)addr, DWC_READ_REG32(addr));
+-04746                 }
+-04747 
+-04748         }
+-04749 }
+-04750 
+-04756 void dwc_otg_dump_spram(dwc_otg_core_if_t * core_if)
+-04757 {
+-04758         volatile uint8_t *addr, *start_addr, *end_addr;
+-04759 
+-04760         DWC_PRINTF("SPRAM Data:\n");
+-04761         start_addr = (void *)core_if->core_global_regs;
+-04762         DWC_PRINTF("Base Address: 0x%8lX\n", (unsigned long)start_addr);
+-04763         start_addr += 0x00028000;
+-04764         end_addr = (void *)core_if->core_global_regs;
+-04765         end_addr += 0x000280e0;
+-04766 
+-04767         for (addr = start_addr; addr < end_addr; addr += 16) {
+-04768                 DWC_PRINTF
+-04769                     ("0x%8lX:\t%2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X\n",
+-04770                      (unsigned long)addr, addr[0], addr[1], addr[2], addr[3],
+-04771                      addr[4], addr[5], addr[6], addr[7], addr[8], addr[9],
+-04772                      addr[10], addr[11], addr[12], addr[13], addr[14], addr[15]
+-04773                     );
+-04774         }
+-04775 
+-04776         return;
+-04777 }
+-04778 
+-04784 void dwc_otg_dump_host_registers(dwc_otg_core_if_t * core_if)
+-04785 {
+-04786         int i;
+-04787         volatile uint32_t *addr;
+-04788 
+-04789         DWC_PRINTF("Host Global Registers\n");
+-04790         addr = &core_if->host_if->host_global_regs->hcfg;
+-04791         DWC_PRINTF("HCFG                 @0x%08lX : 0x%08X\n",
+-04792                    (unsigned long)addr, DWC_READ_REG32(addr));
+-04793         addr = &core_if->host_if->host_global_regs->hfir;
+-04794         DWC_PRINTF("HFIR                 @0x%08lX : 0x%08X\n",
+-04795                    (unsigned long)addr, DWC_READ_REG32(addr));
+-04796         addr = &core_if->host_if->host_global_regs->hfnum;
+-04797         DWC_PRINTF("HFNUM        @0x%08lX : 0x%08X\n", (unsigned long)addr,
+-04798                    DWC_READ_REG32(addr));
+-04799         addr = &core_if->host_if->host_global_regs->hptxsts;
+-04800         DWC_PRINTF("HPTXSTS      @0x%08lX : 0x%08X\n", (unsigned long)addr,
+-04801                    DWC_READ_REG32(addr));
+-04802         addr = &core_if->host_if->host_global_regs->haint;
+-04803         DWC_PRINTF("HAINT        @0x%08lX : 0x%08X\n", (unsigned long)addr,
+-04804                    DWC_READ_REG32(addr));
+-04805         addr = &core_if->host_if->host_global_regs->haintmsk;
+-04806         DWC_PRINTF("HAINTMSK     @0x%08lX : 0x%08X\n", (unsigned long)addr,
+-04807                    DWC_READ_REG32(addr));
+-04808         if (core_if->dma_desc_enable) {
+-04809                 addr = &core_if->host_if->host_global_regs->hflbaddr;
+-04810                 DWC_PRINTF("HFLBADDR     @0x%08lX : 0x%08X\n",
+-04811                            (unsigned long)addr, DWC_READ_REG32(addr));
+-04812         }
+-04813 
+-04814         addr = core_if->host_if->hprt0;
+-04815         DWC_PRINTF("HPRT0        @0x%08lX : 0x%08X\n", (unsigned long)addr,
+-04816                    DWC_READ_REG32(addr));
+-04817 
+-04818         for (i = 0; i < core_if->core_params->host_channels; i++) {
+-04819                 DWC_PRINTF("Host Channel %d Specific Registers\n", i);
+-04820                 addr = &core_if->host_if->hc_regs[i]->hcchar;
+-04821                 DWC_PRINTF("HCCHAR       @0x%08lX : 0x%08X\n",
+-04822                            (unsigned long)addr, DWC_READ_REG32(addr));
+-04823                 addr = &core_if->host_if->hc_regs[i]->hcsplt;
+-04824                 DWC_PRINTF("HCSPLT       @0x%08lX : 0x%08X\n",
+-04825                            (unsigned long)addr, DWC_READ_REG32(addr));
+-04826                 addr = &core_if->host_if->hc_regs[i]->hcint;
+-04827                 DWC_PRINTF("HCINT        @0x%08lX : 0x%08X\n",
+-04828                            (unsigned long)addr, DWC_READ_REG32(addr));
+-04829                 addr = &core_if->host_if->hc_regs[i]->hcintmsk;
+-04830                 DWC_PRINTF("HCINTMSK     @0x%08lX : 0x%08X\n",
+-04831                            (unsigned long)addr, DWC_READ_REG32(addr));
+-04832                 addr = &core_if->host_if->hc_regs[i]->hctsiz;
+-04833                 DWC_PRINTF("HCTSIZ       @0x%08lX : 0x%08X\n",
+-04834                            (unsigned long)addr, DWC_READ_REG32(addr));
+-04835                 addr = &core_if->host_if->hc_regs[i]->hcdma;
+-04836                 DWC_PRINTF("HCDMA        @0x%08lX : 0x%08X\n",
+-04837                            (unsigned long)addr, DWC_READ_REG32(addr));
+-04838                 if (core_if->dma_desc_enable) {
+-04839                         addr = &core_if->host_if->hc_regs[i]->hcdmab;
+-04840                         DWC_PRINTF("HCDMAB       @0x%08lX : 0x%08X\n",
+-04841                                    (unsigned long)addr, DWC_READ_REG32(addr));
+-04842                 }
+-04843 
+-04844         }
+-04845         return;
+-04846 }
+-04847 
+-04853 void dwc_otg_dump_global_registers(dwc_otg_core_if_t * core_if)
+-04854 {
+-04855         int i, ep_num;
+-04856         volatile uint32_t *addr;
+-04857         char *txfsiz;
+-04858 
+-04859         DWC_PRINTF("Core Global Registers\n");
+-04860         addr = &core_if->core_global_regs->gotgctl;
+-04861         DWC_PRINTF("GOTGCTL      @0x%08lX : 0x%08X\n", (unsigned long)addr,
+-04862                    DWC_READ_REG32(addr));
+-04863         addr = &core_if->core_global_regs->gotgint;
+-04864         DWC_PRINTF("GOTGINT      @0x%08lX : 0x%08X\n", (unsigned long)addr,
+-04865                    DWC_READ_REG32(addr));
+-04866         addr = &core_if->core_global_regs->gahbcfg;
+-04867         DWC_PRINTF("GAHBCFG      @0x%08lX : 0x%08X\n", (unsigned long)addr,
+-04868                    DWC_READ_REG32(addr));
+-04869         addr = &core_if->core_global_regs->gusbcfg;
+-04870         DWC_PRINTF("GUSBCFG      @0x%08lX : 0x%08X\n", (unsigned long)addr,
+-04871                    DWC_READ_REG32(addr));
+-04872         addr = &core_if->core_global_regs->grstctl;
+-04873         DWC_PRINTF("GRSTCTL      @0x%08lX : 0x%08X\n", (unsigned long)addr,
+-04874                    DWC_READ_REG32(addr));
+-04875         addr = &core_if->core_global_regs->gintsts;
+-04876         DWC_PRINTF("GINTSTS      @0x%08lX : 0x%08X\n", (unsigned long)addr,
+-04877                    DWC_READ_REG32(addr));
+-04878         addr = &core_if->core_global_regs->gintmsk;
+-04879         DWC_PRINTF("GINTMSK      @0x%08lX : 0x%08X\n", (unsigned long)addr,
+-04880                    DWC_READ_REG32(addr));
+-04881         addr = &core_if->core_global_regs->grxstsr;
+-04882         DWC_PRINTF("GRXSTSR      @0x%08lX : 0x%08X\n", (unsigned long)addr,
+-04883                    DWC_READ_REG32(addr));
+-04884         addr = &core_if->core_global_regs->grxfsiz;
+-04885         DWC_PRINTF("GRXFSIZ      @0x%08lX : 0x%08X\n", (unsigned long)addr,
+-04886                    DWC_READ_REG32(addr));
+-04887         addr = &core_if->core_global_regs->gnptxfsiz;
+-04888         DWC_PRINTF("GNPTXFSIZ @0x%08lX : 0x%08X\n", (unsigned long)addr,
+-04889                    DWC_READ_REG32(addr));
+-04890         addr = &core_if->core_global_regs->gnptxsts;
+-04891         DWC_PRINTF("GNPTXSTS     @0x%08lX : 0x%08X\n", (unsigned long)addr,
+-04892                    DWC_READ_REG32(addr));
+-04893         addr = &core_if->core_global_regs->gi2cctl;
+-04894         DWC_PRINTF("GI2CCTL      @0x%08lX : 0x%08X\n", (unsigned long)addr,
+-04895                    DWC_READ_REG32(addr));
+-04896         addr = &core_if->core_global_regs->gpvndctl;
+-04897         DWC_PRINTF("GPVNDCTL     @0x%08lX : 0x%08X\n", (unsigned long)addr,
+-04898                    DWC_READ_REG32(addr));
+-04899         addr = &core_if->core_global_regs->ggpio;
+-04900         DWC_PRINTF("GGPIO        @0x%08lX : 0x%08X\n", (unsigned long)addr,
+-04901                    DWC_READ_REG32(addr));
+-04902         addr = &core_if->core_global_regs->guid;
+-04903         DWC_PRINTF("GUID                 @0x%08lX : 0x%08X\n",
+-04904                    (unsigned long)addr, DWC_READ_REG32(addr));
+-04905         addr = &core_if->core_global_regs->gsnpsid;
+-04906         DWC_PRINTF("GSNPSID      @0x%08lX : 0x%08X\n", (unsigned long)addr,
+-04907                    DWC_READ_REG32(addr));
+-04908         addr = &core_if->core_global_regs->ghwcfg1;
+-04909         DWC_PRINTF("GHWCFG1      @0x%08lX : 0x%08X\n", (unsigned long)addr,
+-04910                    DWC_READ_REG32(addr));
+-04911         addr = &core_if->core_global_regs->ghwcfg2;
+-04912         DWC_PRINTF("GHWCFG2      @0x%08lX : 0x%08X\n", (unsigned long)addr,
+-04913                    DWC_READ_REG32(addr));
+-04914         addr = &core_if->core_global_regs->ghwcfg3;
+-04915         DWC_PRINTF("GHWCFG3      @0x%08lX : 0x%08X\n", (unsigned long)addr,
+-04916                    DWC_READ_REG32(addr));
+-04917         addr = &core_if->core_global_regs->ghwcfg4;
+-04918         DWC_PRINTF("GHWCFG4      @0x%08lX : 0x%08X\n", (unsigned long)addr,
+-04919                    DWC_READ_REG32(addr));
+-04920         addr = &core_if->core_global_regs->glpmcfg;
+-04921         DWC_PRINTF("GLPMCFG      @0x%08lX : 0x%08X\n", (unsigned long)addr,
+-04922                    DWC_READ_REG32(addr));
+-04923         addr = &core_if->core_global_regs->gpwrdn;
+-04924         DWC_PRINTF("GPWRDN       @0x%08lX : 0x%08X\n", (unsigned long)addr,
+-04925                    DWC_READ_REG32(addr));
+-04926         addr = &core_if->core_global_regs->gdfifocfg;
+-04927         DWC_PRINTF("GDFIFOCFG    @0x%08lX : 0x%08X\n", (unsigned long)addr,
+-04928                    DWC_READ_REG32(addr));
+-04929         addr = &core_if->core_global_regs->adpctl;
+-04930         DWC_PRINTF("ADPCTL       @0x%08lX : 0x%08X\n", (unsigned long)addr,
+-04931                    dwc_otg_adp_read_reg(core_if));
+-04932         addr = &core_if->core_global_regs->hptxfsiz;
+-04933         DWC_PRINTF("HPTXFSIZ     @0x%08lX : 0x%08X\n", (unsigned long)addr,
+-04934                    DWC_READ_REG32(addr));
+-04935 
+-04936         if (core_if->en_multiple_tx_fifo == 0) {
+-04937                 ep_num = core_if->hwcfg4.b.num_dev_perio_in_ep;
+-04938                 txfsiz = "DPTXFSIZ";
+-04939         } else {
+-04940                 ep_num = core_if->hwcfg4.b.num_in_eps;
+-04941                 txfsiz = "DIENPTXF";
+-04942         }
+-04943         for (i = 0; i < ep_num; i++) {
+-04944                 addr = &core_if->core_global_regs->dtxfsiz[i];
+-04945                 DWC_PRINTF("%s[%d] @0x%08lX : 0x%08X\n", txfsiz, i + 1,
+-04946                            (unsigned long)addr, DWC_READ_REG32(addr));
+-04947         }
+-04948         addr = core_if->pcgcctl;
+-04949         DWC_PRINTF("PCGCCTL      @0x%08lX : 0x%08X\n", (unsigned long)addr,
+-04950                    DWC_READ_REG32(addr));
+-04951 }
+-04952 
+-04959 void dwc_otg_flush_tx_fifo(dwc_otg_core_if_t * core_if, const int num)
+-04960 {
+-04961         dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
+-04962         volatile grstctl_t greset = {.d32 = 0 };
+-04963         int count = 0;
+-04964 
+-04965         DWC_DEBUGPL((DBG_CIL | DBG_PCDV), "Flush Tx FIFO %d\n", num);
+-04966 
+-04967         greset.b.txfflsh = 1;
+-04968         greset.b.txfnum = num;
+-04969         DWC_WRITE_REG32(&global_regs->grstctl, greset.d32);
+-04970 
+-04971         do {
+-04972                 greset.d32 = DWC_READ_REG32(&global_regs->grstctl);
+-04973                 if (++count > 10000) {
+-04974                         DWC_WARN("%s() HANG! GRSTCTL=%0x GNPTXSTS=0x%08x\n",
+-04975                                  __func__, greset.d32,
+-04976                                  DWC_READ_REG32(&global_regs->gnptxsts));
+-04977                         break;
+-04978                 }
+-04979                 dwc_udelay(1);
+-04980         } while (greset.b.txfflsh == 1);
+-04981 
+-04982         /* Wait for 3 PHY Clocks */
+-04983         dwc_udelay(1);
+-04984 }
+-04985 
+-04991 void dwc_otg_flush_rx_fifo(dwc_otg_core_if_t * core_if)
+-04992 {
+-04993         dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
+-04994         volatile grstctl_t greset = {.d32 = 0 };
+-04995         int count = 0;
+-04996 
+-04997         DWC_DEBUGPL((DBG_CIL | DBG_PCDV), "%s\n", __func__);
+-04998         /*
+-04999          *
+-05000          */
+-05001         greset.b.rxfflsh = 1;
+-05002         DWC_WRITE_REG32(&global_regs->grstctl, greset.d32);
+-05003 
+-05004         do {
+-05005                 greset.d32 = DWC_READ_REG32(&global_regs->grstctl);
+-05006                 if (++count > 10000) {
+-05007                         DWC_WARN("%s() HANG! GRSTCTL=%0x\n", __func__,
+-05008                                  greset.d32);
+-05009                         break;
+-05010                 }
+-05011                 dwc_udelay(1);
+-05012         } while (greset.b.rxfflsh == 1);
+-05013 
+-05014         /* Wait for 3 PHY Clocks */
+-05015         dwc_udelay(1);
+-05016 }
+-05017 
+-05022 void dwc_otg_core_reset(dwc_otg_core_if_t * core_if)
+-05023 {
+-05024         dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
+-05025         volatile grstctl_t greset = {.d32 = 0 };
+-05026         int count = 0;
+-05027 
+-05028         DWC_DEBUGPL(DBG_CILV, "%s\n", __func__);
+-05029         /* Wait for AHB master IDLE state. */
+-05030         do {
+-05031                 dwc_udelay(10);
+-05032                 greset.d32 = DWC_READ_REG32(&global_regs->grstctl);
+-05033                 if (++count > 100000) {
+-05034                         DWC_WARN("%s() HANG! AHB Idle GRSTCTL=%0x\n", __func__,
+-05035                                  greset.d32);
+-05036                         return;
+-05037                 }
+-05038         }
+-05039         while (greset.b.ahbidle == 0);
+-05040 
+-05041         /* Core Soft Reset */
+-05042         count = 0;
+-05043         greset.b.csftrst = 1;
+-05044         DWC_WRITE_REG32(&global_regs->grstctl, greset.d32);
+-05045         do {
+-05046                 greset.d32 = DWC_READ_REG32(&global_regs->grstctl);
+-05047                 if (++count > 10000) {
+-05048                         DWC_WARN("%s() HANG! Soft Reset GRSTCTL=%0x\n",
+-05049                                  __func__, greset.d32);
+-05050                         break;
+-05051                 }
+-05052                 dwc_udelay(1);
+-05053         }
+-05054         while (greset.b.csftrst == 1);
+-05055 
+-05056         /* Wait for 3 PHY Clocks */
+-05057         dwc_mdelay(100);
+-05058 }
+-05059 
+-05060 uint8_t dwc_otg_is_device_mode(dwc_otg_core_if_t * _core_if)
+-05061 {
+-05062         return (dwc_otg_mode(_core_if) != DWC_HOST_MODE);
+-05063 }
+-05064 
+-05065 uint8_t dwc_otg_is_host_mode(dwc_otg_core_if_t * _core_if)
+-05066 {
+-05067         return (dwc_otg_mode(_core_if) == DWC_HOST_MODE);
+-05068 }
+-05069 
+-05078 void dwc_otg_cil_register_hcd_callbacks(dwc_otg_core_if_t * core_if,
+-05079                                         dwc_otg_cil_callbacks_t * cb, void *p)
+-05080 {
+-05081         core_if->hcd_cb = cb;
+-05082         cb->p = p;
+-05083 }
+-05084 
+-05093 void dwc_otg_cil_register_pcd_callbacks(dwc_otg_core_if_t * core_if,
+-05094                                         dwc_otg_cil_callbacks_t * cb, void *p)
+-05095 {
+-05096         core_if->pcd_cb = cb;
+-05097         cb->p = p;
+-05098 }
+-05099 
+-05100 #ifdef DWC_EN_ISOC
+-05101 
+-05109 void write_isoc_frame_data(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
+-05110 {
+-05111         dwc_otg_dev_in_ep_regs_t *ep_regs;
+-05112         dtxfsts_data_t txstatus = {.d32 = 0 };
+-05113         uint32_t len = 0;
+-05114         uint32_t dwords;
+-05115 
+-05116         ep->xfer_len = ep->data_per_frame;
+-05117         ep->xfer_count = 0;
+-05118 
+-05119         ep_regs = core_if->dev_if->in_ep_regs[ep->num];
+-05120 
+-05121         len = ep->xfer_len - ep->xfer_count;
+-05122 
+-05123         if (len > ep->maxpacket) {
+-05124                 len = ep->maxpacket;
+-05125         }
+-05126 
+-05127         dwords = (len + 3) / 4;
+-05128 
+-05129         /* While there is space in the queue and space in the FIFO and
+-05130          * More data to tranfer, Write packets to the Tx FIFO */
+-05131         txstatus.d32 =
+-05132             DWC_READ_REG32(&core_if->dev_if->in_ep_regs[ep->num]->dtxfsts);
+-05133         DWC_DEBUGPL(DBG_PCDV, "b4 dtxfsts[%d]=0x%08x\n", ep->num, txstatus.d32);
+-05134 
+-05135         while (txstatus.b.txfspcavail > dwords &&
+-05136                ep->xfer_count < ep->xfer_len && ep->xfer_len != 0) {
+-05137                 /* Write the FIFO */
+-05138                 dwc_otg_ep_write_packet(core_if, ep, 0);
+-05139 
+-05140                 len = ep->xfer_len - ep->xfer_count;
+-05141                 if (len > ep->maxpacket) {
+-05142                         len = ep->maxpacket;
+-05143                 }
+-05144 
+-05145                 dwords = (len + 3) / 4;
+-05146                 txstatus.d32 =
+-05147                     DWC_READ_REG32(&core_if->dev_if->
+-05148                                    in_ep_regs[ep->num]->dtxfsts);
+-05149                 DWC_DEBUGPL(DBG_PCDV, "dtxfsts[%d]=0x%08x\n", ep->num,
+-05150                             txstatus.d32);
+-05151         }
+-05152 }
+-05153 
+-05161 void dwc_otg_iso_ep_start_frm_transfer(dwc_otg_core_if_t * core_if,
+-05162                                        dwc_ep_t * ep)
+-05163 {
+-05164         deptsiz_data_t deptsiz = {.d32 = 0 };
+-05165         depctl_data_t depctl = {.d32 = 0 };
+-05166         dsts_data_t dsts = {.d32 = 0 };
+-05167         volatile uint32_t *addr;
+-05168 
+-05169         if (ep->is_in) {
+-05170                 addr = &core_if->dev_if->in_ep_regs[ep->num]->diepctl;
+-05171         } else {
+-05172                 addr = &core_if->dev_if->out_ep_regs[ep->num]->doepctl;
+-05173         }
+-05174 
+-05175         ep->xfer_len = ep->data_per_frame;
+-05176         ep->xfer_count = 0;
+-05177         ep->xfer_buff = ep->cur_pkt_addr;
+-05178         ep->dma_addr = ep->cur_pkt_dma_addr;
+-05179 
+-05180         if (ep->is_in) {
+-05181                 /* Program the transfer size and packet count
+-05182                  *      as follows: xfersize = N * maxpacket +
+-05183                  *      short_packet pktcnt = N + (short_packet
+-05184                  *      exist ? 1 : 0) 
+-05185                  */
+-05186                 deptsiz.b.xfersize = ep->xfer_len;
+-05187                 deptsiz.b.pktcnt =
+-05188                     (ep->xfer_len - 1 + ep->maxpacket) / ep->maxpacket;
+-05189                 deptsiz.b.mc = deptsiz.b.pktcnt;
+-05190                 DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[ep->num]->dieptsiz,
+-05191                                 deptsiz.d32);
+-05192 
+-05193                 /* Write the DMA register */
+-05194                 if (core_if->dma_enable) {
+-05195                         DWC_WRITE_REG32(&
+-05196                                         (core_if->dev_if->in_ep_regs[ep->num]->
+-05197                                          diepdma), (uint32_t) ep->dma_addr);
+-05198                 }
+-05199         } else {
+-05200                 deptsiz.b.pktcnt =
+-05201                     (ep->xfer_len + (ep->maxpacket - 1)) / ep->maxpacket;
+-05202                 deptsiz.b.xfersize = deptsiz.b.pktcnt * ep->maxpacket;
+-05203 
+-05204                 DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[ep->num]->
+-05205                                 doeptsiz, deptsiz.d32);
+-05206 
+-05207                 if (core_if->dma_enable) {
+-05208                         DWC_WRITE_REG32(&
+-05209                                         (core_if->dev_if->out_ep_regs[ep->num]->
+-05210                                          doepdma), (uint32_t) ep->dma_addr);
+-05211                 }
+-05212         }
+-05213 
+-05216         depctl.d32 = 0;
+-05217         if (ep->bInterval == 1) {
+-05218                 dsts.d32 =
+-05219                     DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts);
+-05220                 ep->next_frame = dsts.b.soffn + ep->bInterval;
+-05221 
+-05222                 if (ep->next_frame & 0x1) {
+-05223                         depctl.b.setd1pid = 1;
+-05224                 } else {
+-05225                         depctl.b.setd0pid = 1;
+-05226                 }
+-05227         } else {
+-05228                 ep->next_frame += ep->bInterval;
+-05229 
+-05230                 if (ep->next_frame & 0x1) {
+-05231                         depctl.b.setd1pid = 1;
+-05232                 } else {
+-05233                         depctl.b.setd0pid = 1;
+-05234                 }
+-05235         }
+-05236         depctl.b.epena = 1;
+-05237         depctl.b.cnak = 1;
+-05238 
+-05239         DWC_MODIFY_REG32(addr, 0, depctl.d32);
+-05240         depctl.d32 = DWC_READ_REG32(addr);
+-05241 
+-05242         if (ep->is_in && core_if->dma_enable == 0) {
+-05243                 write_isoc_frame_data(core_if, ep);
+-05244         }
+-05245 
+-05246 }
+-05247 #endif /* DWC_EN_ISOC */
+-05248 
+-05249 static void dwc_otg_set_uninitialized(int32_t * p, int size)
+-05250 {
+-05251         int i;
+-05252         for (i = 0; i < size; i++) {
+-05253                 p[i] = -1;
+-05254         }
+-05255 }
+-05256 
+-05257 static int dwc_otg_param_initialized(int32_t val)
+-05258 {
+-05259         return val != -1;
+-05260 }
+-05261 
+-05262 static int dwc_otg_setup_params(dwc_otg_core_if_t * core_if)
+-05263 {
+-05264         int i;
+-05265         core_if->core_params = DWC_ALLOC(sizeof(*core_if->core_params));
+-05266         if (!core_if->core_params) {
+-05267                 return -DWC_E_NO_MEMORY;
+-05268         }
+-05269         dwc_otg_set_uninitialized((int32_t *) core_if->core_params,
+-05270                                   sizeof(*core_if->core_params) /
+-05271                                   sizeof(int32_t));
+-05272         DWC_PRINTF("Setting default values for core params\n");
+-05273         dwc_otg_set_param_otg_cap(core_if, dwc_param_otg_cap_default);
+-05274         dwc_otg_set_param_dma_enable(core_if, dwc_param_dma_enable_default);
+-05275         dwc_otg_set_param_dma_desc_enable(core_if,
+-05276                                           dwc_param_dma_desc_enable_default);
+-05277         dwc_otg_set_param_opt(core_if, dwc_param_opt_default);
+-05278         dwc_otg_set_param_dma_burst_size(core_if,
+-05279                                          dwc_param_dma_burst_size_default);
+-05280         dwc_otg_set_param_host_support_fs_ls_low_power(core_if,
+-05281                                                        dwc_param_host_support_fs_ls_low_power_default);
+-05282         dwc_otg_set_param_enable_dynamic_fifo(core_if,
+-05283                                               dwc_param_enable_dynamic_fifo_default);
+-05284         dwc_otg_set_param_data_fifo_size(core_if,
+-05285                                          dwc_param_data_fifo_size_default);
+-05286         dwc_otg_set_param_dev_rx_fifo_size(core_if,
+-05287                                            dwc_param_dev_rx_fifo_size_default);
+-05288         dwc_otg_set_param_dev_nperio_tx_fifo_size(core_if,
+-05289                                                   dwc_param_dev_nperio_tx_fifo_size_default);
+-05290         dwc_otg_set_param_host_rx_fifo_size(core_if,
+-05291                                             dwc_param_host_rx_fifo_size_default);
+-05292         dwc_otg_set_param_host_nperio_tx_fifo_size(core_if,
+-05293                                                    dwc_param_host_nperio_tx_fifo_size_default);
+-05294         dwc_otg_set_param_host_perio_tx_fifo_size(core_if,
+-05295                                                   dwc_param_host_perio_tx_fifo_size_default);
+-05296         dwc_otg_set_param_max_transfer_size(core_if,
+-05297                                             dwc_param_max_transfer_size_default);
+-05298         dwc_otg_set_param_max_packet_count(core_if,
+-05299                                            dwc_param_max_packet_count_default);
+-05300         dwc_otg_set_param_host_channels(core_if,
+-05301                                         dwc_param_host_channels_default);
+-05302         dwc_otg_set_param_dev_endpoints(core_if,
+-05303                                         dwc_param_dev_endpoints_default);
+-05304         dwc_otg_set_param_phy_type(core_if, dwc_param_phy_type_default);
+-05305         dwc_otg_set_param_speed(core_if, dwc_param_speed_default);
+-05306         dwc_otg_set_param_host_ls_low_power_phy_clk(core_if,
+-05307                                                     dwc_param_host_ls_low_power_phy_clk_default);
+-05308         dwc_otg_set_param_phy_ulpi_ddr(core_if, dwc_param_phy_ulpi_ddr_default);
+-05309         dwc_otg_set_param_phy_ulpi_ext_vbus(core_if,
+-05310                                             dwc_param_phy_ulpi_ext_vbus_default);
+-05311         dwc_otg_set_param_phy_utmi_width(core_if,
+-05312                                          dwc_param_phy_utmi_width_default);
+-05313         dwc_otg_set_param_ts_dline(core_if, dwc_param_ts_dline_default);
+-05314         dwc_otg_set_param_i2c_enable(core_if, dwc_param_i2c_enable_default);
+-05315         dwc_otg_set_param_ulpi_fs_ls(core_if, dwc_param_ulpi_fs_ls_default);
+-05316         dwc_otg_set_param_en_multiple_tx_fifo(core_if,
+-05317                                               dwc_param_en_multiple_tx_fifo_default);
+-05318         for (i = 0; i < 15; i++) {
+-05319                 dwc_otg_set_param_dev_perio_tx_fifo_size(core_if,
+-05320                                                          dwc_param_dev_perio_tx_fifo_size_default,
+-05321                                                          i);
+-05322         }
+-05323 
+-05324         for (i = 0; i < 15; i++) {
+-05325                 dwc_otg_set_param_dev_tx_fifo_size(core_if,
+-05326                                                    dwc_param_dev_tx_fifo_size_default,
+-05327                                                    i);
+-05328         }
+-05329         dwc_otg_set_param_thr_ctl(core_if, dwc_param_thr_ctl_default);
+-05330         dwc_otg_set_param_mpi_enable(core_if, dwc_param_mpi_enable_default);
+-05331         dwc_otg_set_param_pti_enable(core_if, dwc_param_pti_enable_default);
+-05332         dwc_otg_set_param_lpm_enable(core_if, dwc_param_lpm_enable_default);
+-05333         dwc_otg_set_param_ic_usb_cap(core_if, dwc_param_ic_usb_cap_default);
+-05334         dwc_otg_set_param_tx_thr_length(core_if,
+-05335                                         dwc_param_tx_thr_length_default);
+-05336         dwc_otg_set_param_rx_thr_length(core_if,
+-05337                                         dwc_param_rx_thr_length_default);
+-05338         dwc_otg_set_param_ahb_thr_ratio(core_if,
+-05339                                         dwc_param_ahb_thr_ratio_default);
+-05340         dwc_otg_set_param_power_down(core_if, dwc_param_power_down_default);
+-05341         dwc_otg_set_param_reload_ctl(core_if, dwc_param_reload_ctl_default);
+-05342         dwc_otg_set_param_dev_out_nak(core_if, dwc_param_dev_out_nak_default);
+-05343         dwc_otg_set_param_cont_on_bna(core_if, dwc_param_cont_on_bna_default);
+-05344         dwc_otg_set_param_ahb_single(core_if, dwc_param_ahb_single_default);
+-05345         dwc_otg_set_param_otg_ver(core_if, dwc_param_otg_ver_default);
+-05346         dwc_otg_set_param_adp_enable(core_if, dwc_param_adp_enable_default);
+-05347         return 0;
+-05348 }
+-05349 
+-05350 uint8_t dwc_otg_is_dma_enable(dwc_otg_core_if_t * core_if)
+-05351 {
+-05352         return core_if->dma_enable;
+-05353 }
+-05354 
+-05355 /* Checks if the parameter is outside of its valid range of values */
+-05356 #define DWC_OTG_PARAM_TEST(_param_, _low_, _high_) \
+-05357                 (((_param_) < (_low_)) || \
+-05358                 ((_param_) > (_high_)))
+-05359 
+-05360 /* Parameter access functions */
+-05361 int dwc_otg_set_param_otg_cap(dwc_otg_core_if_t * core_if, int32_t val)
+-05362 {
+-05363         int valid;
+-05364         int retval = 0;
+-05365         if (DWC_OTG_PARAM_TEST(val, 0, 2)) {
+-05366                 DWC_WARN("Wrong value for otg_cap parameter\n");
+-05367                 DWC_WARN("otg_cap parameter must be 0,1 or 2\n");
+-05368                 retval = -DWC_E_INVALID;
+-05369                 goto out;
+-05370         }
+-05371 
+-05372         valid = 1;
+-05373         switch (val) {
+-05374         case DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE:
+-05375                 if (core_if->hwcfg2.b.op_mode !=
+-05376                     DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG)
+-05377                         valid = 0;
+-05378                 break;
+-05379         case DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE:
+-05380                 if ((core_if->hwcfg2.b.op_mode !=
+-05381                      DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG)
+-05382                     && (core_if->hwcfg2.b.op_mode !=
+-05383                         DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG)
+-05384                     && (core_if->hwcfg2.b.op_mode !=
+-05385                         DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE)
+-05386                     && (core_if->hwcfg2.b.op_mode !=
+-05387                         DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST)) {
+-05388                         valid = 0;
+-05389                 }
+-05390                 break;
+-05391         case DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE:
+-05392                 /* always valid */
+-05393                 break;
+-05394         }
+-05395         if (!valid) {
+-05396                 if (dwc_otg_param_initialized(core_if->core_params->otg_cap)) {
+-05397                         DWC_ERROR
+-05398                             ("%d invalid for otg_cap paremter. Check HW configuration.\n",
+-05399                              val);
+-05400                 }
+-05401                 val =
+-05402                     (((core_if->hwcfg2.b.op_mode ==
+-05403                        DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG)
+-05404                       || (core_if->hwcfg2.b.op_mode ==
+-05405                           DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG)
+-05406                       || (core_if->hwcfg2.b.op_mode ==
+-05407                           DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE)
+-05408                       || (core_if->hwcfg2.b.op_mode ==
+-05409                           DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST)) ?
+-05410                      DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE :
+-05411                      DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE);
+-05412                 retval = -DWC_E_INVALID;
+-05413         }
+-05414 
+-05415         core_if->core_params->otg_cap = val;
+-05416 out:
+-05417         return retval;
+-05418 }
+-05419 
+-05420 int32_t dwc_otg_get_param_otg_cap(dwc_otg_core_if_t * core_if)
+-05421 {
+-05422         return core_if->core_params->otg_cap;
+-05423 }
+-05424 
+-05425 int dwc_otg_set_param_opt(dwc_otg_core_if_t * core_if, int32_t val)
+-05426 {
+-05427         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
+-05428                 DWC_WARN("Wrong value for opt parameter\n");
+-05429                 return -DWC_E_INVALID;
+-05430         }
+-05431         core_if->core_params->opt = val;
+-05432         return 0;
+-05433 }
+-05434 
+-05435 int32_t dwc_otg_get_param_opt(dwc_otg_core_if_t * core_if)
+-05436 {
+-05437         return core_if->core_params->opt;
+-05438 }
+-05439 
+-05440 int dwc_otg_set_param_dma_enable(dwc_otg_core_if_t * core_if, int32_t val)
+-05441 {
+-05442         int retval = 0;
+-05443         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
+-05444                 DWC_WARN("Wrong value for dma enable\n");
+-05445                 return -DWC_E_INVALID;
+-05446         }
+-05447 
+-05448         if ((val == 1) && (core_if->hwcfg2.b.architecture == 0)) {
+-05449                 if (dwc_otg_param_initialized(core_if->core_params->dma_enable)) {
+-05450                         DWC_ERROR
+-05451                             ("%d invalid for dma_enable paremter. Check HW configuration.\n",
+-05452                              val);
+-05453                 }
+-05454                 val = 0;
+-05455                 retval = -DWC_E_INVALID;
+-05456         }
+-05457 
+-05458         core_if->core_params->dma_enable = val;
+-05459         if (val == 0) {
+-05460                 dwc_otg_set_param_dma_desc_enable(core_if, 0);
+-05461         }
+-05462         return retval;
+-05463 }
+-05464 
+-05465 int32_t dwc_otg_get_param_dma_enable(dwc_otg_core_if_t * core_if)
+-05466 {
+-05467         return core_if->core_params->dma_enable;
+-05468 }
+-05469 
+-05470 int dwc_otg_set_param_dma_desc_enable(dwc_otg_core_if_t * core_if, int32_t val)
+-05471 {
+-05472         int retval = 0;
+-05473         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
+-05474                 DWC_WARN("Wrong value for dma_enable\n");
+-05475                 DWC_WARN("dma_desc_enable must be 0 or 1\n");
+-05476                 return -DWC_E_INVALID;
+-05477         }
+-05478 
+-05479         if ((val == 1)
+-05480             && ((dwc_otg_get_param_dma_enable(core_if) == 0)
+-05481                 || (core_if->hwcfg4.b.desc_dma == 0))) {
+-05482                 if (dwc_otg_param_initialized
+-05483                     (core_if->core_params->dma_desc_enable)) {
+-05484                         DWC_ERROR
+-05485                             ("%d invalid for dma_desc_enable paremter. Check HW configuration.\n",
+-05486                              val);
+-05487                 }
+-05488                 val = 0;
+-05489                 retval = -DWC_E_INVALID;
+-05490         }
+-05491         core_if->core_params->dma_desc_enable = val;
+-05492         return retval;
+-05493 }
+-05494 
+-05495 int32_t dwc_otg_get_param_dma_desc_enable(dwc_otg_core_if_t * core_if)
+-05496 {
+-05497         return core_if->core_params->dma_desc_enable;
+-05498 }
+-05499 
+-05500 int dwc_otg_set_param_host_support_fs_ls_low_power(dwc_otg_core_if_t * core_if,
+-05501                                                    int32_t val)
+-05502 {
+-05503         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
+-05504                 DWC_WARN("Wrong value for host_support_fs_low_power\n");
+-05505                 DWC_WARN("host_support_fs_low_power must be 0 or 1\n");
+-05506                 return -DWC_E_INVALID;
+-05507         }
+-05508         core_if->core_params->host_support_fs_ls_low_power = val;
+-05509         return 0;
+-05510 }
+-05511 
+-05512 int32_t dwc_otg_get_param_host_support_fs_ls_low_power(dwc_otg_core_if_t *
+-05513                                                        core_if)
+-05514 {
+-05515         return core_if->core_params->host_support_fs_ls_low_power;
+-05516 }
+-05517 
+-05518 int dwc_otg_set_param_enable_dynamic_fifo(dwc_otg_core_if_t * core_if,
+-05519                                           int32_t val)
+-05520 {
+-05521         int retval = 0;
+-05522         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
+-05523                 DWC_WARN("Wrong value for enable_dynamic_fifo\n");
+-05524                 DWC_WARN("enable_dynamic_fifo must be 0 or 1\n");
+-05525                 return -DWC_E_INVALID;
+-05526         }
+-05527 
+-05528         if ((val == 1) && (core_if->hwcfg2.b.dynamic_fifo == 0)) {
+-05529                 if (dwc_otg_param_initialized
+-05530                     (core_if->core_params->enable_dynamic_fifo)) {
+-05531                         DWC_ERROR
+-05532                             ("%d invalid for enable_dynamic_fifo paremter. Check HW configuration.\n",
+-05533                              val);
+-05534                 }
+-05535                 val = 0;
+-05536                 retval = -DWC_E_INVALID;
+-05537         }
+-05538         core_if->core_params->enable_dynamic_fifo = val;
+-05539         return retval;
+-05540 }
+-05541 
+-05542 int32_t dwc_otg_get_param_enable_dynamic_fifo(dwc_otg_core_if_t * core_if)
+-05543 {
+-05544         return core_if->core_params->enable_dynamic_fifo;
+-05545 }
+-05546 
+-05547 int dwc_otg_set_param_data_fifo_size(dwc_otg_core_if_t * core_if, int32_t val)
+-05548 {
+-05549         int retval = 0;
+-05550         if (DWC_OTG_PARAM_TEST(val, 32, 32768)) {
+-05551                 DWC_WARN("Wrong value for data_fifo_size\n");
+-05552                 DWC_WARN("data_fifo_size must be 32-32768\n");
+-05553                 return -DWC_E_INVALID;
+-05554         }
+-05555 
+-05556         if (val > core_if->hwcfg3.b.dfifo_depth) {
+-05557                 if (dwc_otg_param_initialized
+-05558                     (core_if->core_params->data_fifo_size)) {
+-05559                         DWC_ERROR
+-05560                             ("%d invalid for data_fifo_size parameter. Check HW configuration.\n",
+-05561                              val);
+-05562                 }
+-05563                 val = core_if->hwcfg3.b.dfifo_depth;
+-05564                 retval = -DWC_E_INVALID;
+-05565         }
+-05566 
+-05567         core_if->core_params->data_fifo_size = val;
+-05568         return retval;
+-05569 }
+-05570 
+-05571 int32_t dwc_otg_get_param_data_fifo_size(dwc_otg_core_if_t * core_if)
+-05572 {
+-05573         return core_if->core_params->data_fifo_size;
+-05574 }
+-05575 
+-05576 int dwc_otg_set_param_dev_rx_fifo_size(dwc_otg_core_if_t * core_if, int32_t val)
+-05577 {
+-05578         int retval = 0;
+-05579         if (DWC_OTG_PARAM_TEST(val, 16, 32768)) {
+-05580                 DWC_WARN("Wrong value for dev_rx_fifo_size\n");
+-05581                 DWC_WARN("dev_rx_fifo_size must be 16-32768\n");
+-05582                 return -DWC_E_INVALID;
+-05583         }
+-05584 
+-05585         if (val > DWC_READ_REG32(&core_if->core_global_regs->grxfsiz)) {
+-05586                 if (dwc_otg_param_initialized(core_if->core_params->dev_rx_fifo_size)) {
+-05587                 DWC_WARN("%d invalid for dev_rx_fifo_size parameter\n", val);
+-05588                 }
+-05589                 val = DWC_READ_REG32(&core_if->core_global_regs->grxfsiz);
+-05590                 retval = -DWC_E_INVALID;
+-05591         }
+-05592 
+-05593         core_if->core_params->dev_rx_fifo_size = val;
+-05594         return retval;
+-05595 }
+-05596 
+-05597 int32_t dwc_otg_get_param_dev_rx_fifo_size(dwc_otg_core_if_t * core_if)
+-05598 {
+-05599         return core_if->core_params->dev_rx_fifo_size;
+-05600 }
+-05601 
+-05602 int dwc_otg_set_param_dev_nperio_tx_fifo_size(dwc_otg_core_if_t * core_if,
+-05603                                               int32_t val)
+-05604 {
+-05605         int retval = 0;
+-05606 
+-05607         if (DWC_OTG_PARAM_TEST(val, 16, 32768)) {
+-05608                 DWC_WARN("Wrong value for dev_nperio_tx_fifo\n");
+-05609                 DWC_WARN("dev_nperio_tx_fifo must be 16-32768\n");
+-05610                 return -DWC_E_INVALID;
+-05611         }
+-05612 
+-05613         if (val > (DWC_READ_REG32(&core_if->core_global_regs->gnptxfsiz) >> 16)) {
+-05614                 if (dwc_otg_param_initialized
+-05615                     (core_if->core_params->dev_nperio_tx_fifo_size)) {
+-05616                         DWC_ERROR
+-05617                             ("%d invalid for dev_nperio_tx_fifo_size. Check HW configuration.\n",
+-05618                              val);
+-05619                 }
+-05620                 val =
+-05621                     (DWC_READ_REG32(&core_if->core_global_regs->gnptxfsiz) >>
+-05622                      16);
+-05623                 retval = -DWC_E_INVALID;
+-05624         }
+-05625 
+-05626         core_if->core_params->dev_nperio_tx_fifo_size = val;
+-05627         return retval;
+-05628 }
+-05629 
+-05630 int32_t dwc_otg_get_param_dev_nperio_tx_fifo_size(dwc_otg_core_if_t * core_if)
+-05631 {
+-05632         return core_if->core_params->dev_nperio_tx_fifo_size;
+-05633 }
+-05634 
+-05635 int dwc_otg_set_param_host_rx_fifo_size(dwc_otg_core_if_t * core_if,
+-05636                                         int32_t val)
+-05637 {
+-05638         int retval = 0;
+-05639 
+-05640         if (DWC_OTG_PARAM_TEST(val, 16, 32768)) {
+-05641                 DWC_WARN("Wrong value for host_rx_fifo_size\n");
+-05642                 DWC_WARN("host_rx_fifo_size must be 16-32768\n");
+-05643                 return -DWC_E_INVALID;
+-05644         }
+-05645 
+-05646         if (val > DWC_READ_REG32(&core_if->core_global_regs->grxfsiz)) {
+-05647                 if (dwc_otg_param_initialized
+-05648                     (core_if->core_params->host_rx_fifo_size)) {
+-05649                         DWC_ERROR
+-05650                             ("%d invalid for host_rx_fifo_size. Check HW configuration.\n",
+-05651                              val);
+-05652                 }
+-05653                 val = DWC_READ_REG32(&core_if->core_global_regs->grxfsiz);
+-05654                 retval = -DWC_E_INVALID;
+-05655         }
+-05656 
+-05657         core_if->core_params->host_rx_fifo_size = val;
+-05658         return retval;
+-05659 
+-05660 }
+-05661 
+-05662 int32_t dwc_otg_get_param_host_rx_fifo_size(dwc_otg_core_if_t * core_if)
+-05663 {
+-05664         return core_if->core_params->host_rx_fifo_size;
+-05665 }
+-05666 
+-05667 int dwc_otg_set_param_host_nperio_tx_fifo_size(dwc_otg_core_if_t * core_if,
+-05668                                                int32_t val)
+-05669 {
+-05670         int retval = 0;
+-05671 
+-05672         if (DWC_OTG_PARAM_TEST(val, 16, 32768)) {
+-05673                 DWC_WARN("Wrong value for host_nperio_tx_fifo_size\n");
+-05674                 DWC_WARN("host_nperio_tx_fifo_size must be 16-32768\n");
+-05675                 return -DWC_E_INVALID;
+-05676         }
+-05677 
+-05678         if (val > (DWC_READ_REG32(&core_if->core_global_regs->gnptxfsiz) >> 16)) {
+-05679                 if (dwc_otg_param_initialized
+-05680                     (core_if->core_params->host_nperio_tx_fifo_size)) {
+-05681                         DWC_ERROR
+-05682                             ("%d invalid for host_nperio_tx_fifo_size. Check HW configuration.\n",
+-05683                              val);
+-05684                 }
+-05685                 val =
+-05686                     (DWC_READ_REG32(&core_if->core_global_regs->gnptxfsiz) >>
+-05687                      16);
+-05688                 retval = -DWC_E_INVALID;
+-05689         }
+-05690 
+-05691         core_if->core_params->host_nperio_tx_fifo_size = val;
+-05692         return retval;
+-05693 }
+-05694 
+-05695 int32_t dwc_otg_get_param_host_nperio_tx_fifo_size(dwc_otg_core_if_t * core_if)
+-05696 {
+-05697         return core_if->core_params->host_nperio_tx_fifo_size;
+-05698 }
+-05699 
+-05700 int dwc_otg_set_param_host_perio_tx_fifo_size(dwc_otg_core_if_t * core_if,
+-05701                                               int32_t val)
+-05702 {
+-05703         int retval = 0;
+-05704         if (DWC_OTG_PARAM_TEST(val, 16, 32768)) {
+-05705                 DWC_WARN("Wrong value for host_perio_tx_fifo_size\n");
+-05706                 DWC_WARN("host_perio_tx_fifo_size must be 16-32768\n");
+-05707                 return -DWC_E_INVALID;
+-05708         }
+-05709 
+-05710         if (val >
+-05711                 ((core_if->hptxfsiz.d32)>> 16)) {
+-05712                 if (dwc_otg_param_initialized
+-05713                     (core_if->core_params->host_perio_tx_fifo_size)) {
+-05714                         DWC_ERROR
+-05715                             ("%d invalid for host_perio_tx_fifo_size. Check HW configuration.\n",
+-05716                              val);
+-05717                 }
+-05718                 val = (core_if->hptxfsiz.d32) >> 16;
+-05719                 retval = -DWC_E_INVALID;
+-05720         }
+-05721 
+-05722         core_if->core_params->host_perio_tx_fifo_size = val;
+-05723         return retval;
+-05724 }
+-05725 
+-05726 int32_t dwc_otg_get_param_host_perio_tx_fifo_size(dwc_otg_core_if_t * core_if)
+-05727 {
+-05728         return core_if->core_params->host_perio_tx_fifo_size;
+-05729 }
+-05730 
+-05731 int dwc_otg_set_param_max_transfer_size(dwc_otg_core_if_t * core_if,
+-05732                                         int32_t val)
+-05733 {
+-05734         int retval = 0;
+-05735 
+-05736         if (DWC_OTG_PARAM_TEST(val, 2047, 524288)) {
+-05737                 DWC_WARN("Wrong value for max_transfer_size\n");
+-05738                 DWC_WARN("max_transfer_size must be 2047-524288\n");
+-05739                 return -DWC_E_INVALID;
+-05740         }
+-05741 
+-05742         if (val >= (1 << (core_if->hwcfg3.b.xfer_size_cntr_width + 11))) {
+-05743                 if (dwc_otg_param_initialized
+-05744                     (core_if->core_params->max_transfer_size)) {
+-05745                         DWC_ERROR
+-05746                             ("%d invalid for max_transfer_size. Check HW configuration.\n",
+-05747                              val);
+-05748                 }
+-05749                 val =
+-05750                     ((1 << (core_if->hwcfg3.b.packet_size_cntr_width + 11)) -
+-05751                      1);
+-05752                 retval = -DWC_E_INVALID;
+-05753         }
+-05754 
+-05755         core_if->core_params->max_transfer_size = val;
+-05756         return retval;
+-05757 }
+-05758 
+-05759 int32_t dwc_otg_get_param_max_transfer_size(dwc_otg_core_if_t * core_if)
+-05760 {
+-05761         return core_if->core_params->max_transfer_size;
+-05762 }
+-05763 
+-05764 int dwc_otg_set_param_max_packet_count(dwc_otg_core_if_t * core_if, int32_t val)
+-05765 {
+-05766         int retval = 0;
+-05767 
+-05768         if (DWC_OTG_PARAM_TEST(val, 15, 511)) {
+-05769                 DWC_WARN("Wrong value for max_packet_count\n");
+-05770                 DWC_WARN("max_packet_count must be 15-511\n");
+-05771                 return -DWC_E_INVALID;
+-05772         }
+-05773 
+-05774         if (val > (1 << (core_if->hwcfg3.b.packet_size_cntr_width + 4))) {
+-05775                 if (dwc_otg_param_initialized
+-05776                     (core_if->core_params->max_packet_count)) {
+-05777                         DWC_ERROR
+-05778                             ("%d invalid for max_packet_count. Check HW configuration.\n",
+-05779                              val);
+-05780                 }
+-05781                 val =
+-05782                     ((1 << (core_if->hwcfg3.b.packet_size_cntr_width + 4)) - 1);
+-05783                 retval = -DWC_E_INVALID;
+-05784         }
+-05785 
+-05786         core_if->core_params->max_packet_count = val;
+-05787         return retval;
+-05788 }
+-05789 
+-05790 int32_t dwc_otg_get_param_max_packet_count(dwc_otg_core_if_t * core_if)
+-05791 {
+-05792         return core_if->core_params->max_packet_count;
+-05793 }
+-05794 
+-05795 int dwc_otg_set_param_host_channels(dwc_otg_core_if_t * core_if, int32_t val)
+-05796 {
+-05797         int retval = 0;
+-05798 
+-05799         if (DWC_OTG_PARAM_TEST(val, 1, 16)) {
+-05800                 DWC_WARN("Wrong value for host_channels\n");
+-05801                 DWC_WARN("host_channels must be 1-16\n");
+-05802                 return -DWC_E_INVALID;
+-05803         }
+-05804 
+-05805         if (val > (core_if->hwcfg2.b.num_host_chan + 1)) {
+-05806                 if (dwc_otg_param_initialized
+-05807                     (core_if->core_params->host_channels)) {
+-05808                         DWC_ERROR
+-05809                             ("%d invalid for host_channels. Check HW configurations.\n",
+-05810                              val);
+-05811                 }
+-05812                 val = (core_if->hwcfg2.b.num_host_chan + 1);
+-05813                 retval = -DWC_E_INVALID;
+-05814         }
+-05815 
+-05816         core_if->core_params->host_channels = val;
+-05817         return retval;
+-05818 }
+-05819 
+-05820 int32_t dwc_otg_get_param_host_channels(dwc_otg_core_if_t * core_if)
+-05821 {
+-05822         return core_if->core_params->host_channels;
+-05823 }
+-05824 
+-05825 int dwc_otg_set_param_dev_endpoints(dwc_otg_core_if_t * core_if, int32_t val)
+-05826 {
+-05827         int retval = 0;
+-05828 
+-05829         if (DWC_OTG_PARAM_TEST(val, 1, 15)) {
+-05830                 DWC_WARN("Wrong value for dev_endpoints\n");
+-05831                 DWC_WARN("dev_endpoints must be 1-15\n");
+-05832                 return -DWC_E_INVALID;
+-05833         }
+-05834 
+-05835         if (val > (core_if->hwcfg2.b.num_dev_ep)) {
+-05836                 if (dwc_otg_param_initialized
+-05837                     (core_if->core_params->dev_endpoints)) {
+-05838                         DWC_ERROR
+-05839                             ("%d invalid for dev_endpoints. Check HW configurations.\n",
+-05840                              val);
+-05841                 }
+-05842                 val = core_if->hwcfg2.b.num_dev_ep;
+-05843                 retval = -DWC_E_INVALID;
+-05844         }
+-05845 
+-05846         core_if->core_params->dev_endpoints = val;
+-05847         return retval;
+-05848 }
+-05849 
+-05850 int32_t dwc_otg_get_param_dev_endpoints(dwc_otg_core_if_t * core_if)
+-05851 {
+-05852         return core_if->core_params->dev_endpoints;
+-05853 }
+-05854 
+-05855 int dwc_otg_set_param_phy_type(dwc_otg_core_if_t * core_if, int32_t val)
+-05856 {
+-05857         int retval = 0;
+-05858         int valid = 0;
+-05859 
+-05860         if (DWC_OTG_PARAM_TEST(val, 0, 2)) {
+-05861                 DWC_WARN("Wrong value for phy_type\n");
+-05862                 DWC_WARN("phy_type must be 0,1 or 2\n");
+-05863                 return -DWC_E_INVALID;
+-05864         }
+-05865 #ifndef NO_FS_PHY_HW_CHECKS
+-05866         if ((val == DWC_PHY_TYPE_PARAM_UTMI) &&
+-05867             ((core_if->hwcfg2.b.hs_phy_type == 1) ||
+-05868              (core_if->hwcfg2.b.hs_phy_type == 3))) {
+-05869                 valid = 1;
+-05870         } else if ((val == DWC_PHY_TYPE_PARAM_ULPI) &&
+-05871                    ((core_if->hwcfg2.b.hs_phy_type == 2) ||
+-05872                     (core_if->hwcfg2.b.hs_phy_type == 3))) {
+-05873                 valid = 1;
+-05874         } else if ((val == DWC_PHY_TYPE_PARAM_FS) &&
+-05875                    (core_if->hwcfg2.b.fs_phy_type == 1)) {
+-05876                 valid = 1;
+-05877         }
+-05878         if (!valid) {
+-05879                 if (dwc_otg_param_initialized(core_if->core_params->phy_type)) {
+-05880                         DWC_ERROR
+-05881                             ("%d invalid for phy_type. Check HW configurations.\n",
+-05882                              val);
+-05883                 }
+-05884                 if (core_if->hwcfg2.b.hs_phy_type) {
+-05885                         if ((core_if->hwcfg2.b.hs_phy_type == 3) ||
+-05886                             (core_if->hwcfg2.b.hs_phy_type == 1)) {
+-05887                                 val = DWC_PHY_TYPE_PARAM_UTMI;
+-05888                         } else {
+-05889                                 val = DWC_PHY_TYPE_PARAM_ULPI;
+-05890                         }
+-05891                 }
+-05892                 retval = -DWC_E_INVALID;
+-05893         }
+-05894 #endif
+-05895         core_if->core_params->phy_type = val;
+-05896         return retval;
+-05897 }
+-05898 
+-05899 int32_t dwc_otg_get_param_phy_type(dwc_otg_core_if_t * core_if)
+-05900 {
+-05901         return core_if->core_params->phy_type;
+-05902 }
+-05903 
+-05904 int dwc_otg_set_param_speed(dwc_otg_core_if_t * core_if, int32_t val)
+-05905 {
+-05906         int retval = 0;
+-05907         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
+-05908                 DWC_WARN("Wrong value for speed parameter\n");
+-05909                 DWC_WARN("max_speed parameter must be 0 or 1\n");
+-05910                 return -DWC_E_INVALID;
+-05911         }
+-05912         if ((val == 0)
+-05913             && dwc_otg_get_param_phy_type(core_if) == DWC_PHY_TYPE_PARAM_FS) {
+-05914                 if (dwc_otg_param_initialized(core_if->core_params->speed)) {
+-05915                         DWC_ERROR
+-05916                             ("%d invalid for speed paremter. Check HW configuration.\n",
+-05917                              val);
+-05918                 }
+-05919                 val =
+-05920                     (dwc_otg_get_param_phy_type(core_if) ==
+-05921                      DWC_PHY_TYPE_PARAM_FS ? 1 : 0);
+-05922                 retval = -DWC_E_INVALID;
+-05923         }
+-05924         core_if->core_params->speed = val;
+-05925         return retval;
+-05926 }
+-05927 
+-05928 int32_t dwc_otg_get_param_speed(dwc_otg_core_if_t * core_if)
+-05929 {
+-05930         return core_if->core_params->speed;
+-05931 }
+-05932 
+-05933 int dwc_otg_set_param_host_ls_low_power_phy_clk(dwc_otg_core_if_t * core_if,
+-05934                                                 int32_t val)
+-05935 {
+-05936         int retval = 0;
+-05937 
+-05938         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
+-05939                 DWC_WARN
+-05940                     ("Wrong value for host_ls_low_power_phy_clk parameter\n");
+-05941                 DWC_WARN("host_ls_low_power_phy_clk must be 0 or 1\n");
+-05942                 return -DWC_E_INVALID;
+-05943         }
+-05944 
+-05945         if ((val == DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ)
+-05946             && (dwc_otg_get_param_phy_type(core_if) == DWC_PHY_TYPE_PARAM_FS)) {
+-05947                 if (dwc_otg_param_initialized
+-05948                     (core_if->core_params->host_ls_low_power_phy_clk)) {
+-05949                         DWC_ERROR
+-05950                             ("%d invalid for host_ls_low_power_phy_clk. Check HW configuration.\n",
+-05951                              val);
+-05952                 }
+-05953                 val =
+-05954                     (dwc_otg_get_param_phy_type(core_if) ==
+-05955                      DWC_PHY_TYPE_PARAM_FS) ?
+-05956                     DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ :
+-05957                     DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ;
+-05958                 retval = -DWC_E_INVALID;
+-05959         }
+-05960 
+-05961         core_if->core_params->host_ls_low_power_phy_clk = val;
+-05962         return retval;
+-05963 }
+-05964 
+-05965 int32_t dwc_otg_get_param_host_ls_low_power_phy_clk(dwc_otg_core_if_t * core_if)
+-05966 {
+-05967         return core_if->core_params->host_ls_low_power_phy_clk;
+-05968 }
+-05969 
+-05970 int dwc_otg_set_param_phy_ulpi_ddr(dwc_otg_core_if_t * core_if, int32_t val)
+-05971 {
+-05972         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
+-05973                 DWC_WARN("Wrong value for phy_ulpi_ddr\n");
+-05974                 DWC_WARN("phy_upli_ddr must be 0 or 1\n");
+-05975                 return -DWC_E_INVALID;
+-05976         }
+-05977 
+-05978         core_if->core_params->phy_ulpi_ddr = val;
+-05979         return 0;
+-05980 }
+-05981 
+-05982 int32_t dwc_otg_get_param_phy_ulpi_ddr(dwc_otg_core_if_t * core_if)
+-05983 {
+-05984         return core_if->core_params->phy_ulpi_ddr;
+-05985 }
+-05986 
+-05987 int dwc_otg_set_param_phy_ulpi_ext_vbus(dwc_otg_core_if_t * core_if,
+-05988                                         int32_t val)
+-05989 {
+-05990         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
+-05991                 DWC_WARN("Wrong valaue for phy_ulpi_ext_vbus\n");
+-05992                 DWC_WARN("phy_ulpi_ext_vbus must be 0 or 1\n");
+-05993                 return -DWC_E_INVALID;
+-05994         }
+-05995 
+-05996         core_if->core_params->phy_ulpi_ext_vbus = val;
+-05997         return 0;
+-05998 }
+-05999 
+-06000 int32_t dwc_otg_get_param_phy_ulpi_ext_vbus(dwc_otg_core_if_t * core_if)
+-06001 {
+-06002         return core_if->core_params->phy_ulpi_ext_vbus;
+-06003 }
+-06004 
+-06005 int dwc_otg_set_param_phy_utmi_width(dwc_otg_core_if_t * core_if, int32_t val)
+-06006 {
+-06007         if (DWC_OTG_PARAM_TEST(val, 8, 8) && DWC_OTG_PARAM_TEST(val, 16, 16)) {
+-06008                 DWC_WARN("Wrong valaue for phy_utmi_width\n");
+-06009                 DWC_WARN("phy_utmi_width must be 8 or 16\n");
+-06010                 return -DWC_E_INVALID;
+-06011         }
+-06012 
+-06013         core_if->core_params->phy_utmi_width = val;
+-06014         return 0;
+-06015 }
+-06016 
+-06017 int32_t dwc_otg_get_param_phy_utmi_width(dwc_otg_core_if_t * core_if)
+-06018 {
+-06019         return core_if->core_params->phy_utmi_width;
+-06020 }
+-06021 
+-06022 int dwc_otg_set_param_ulpi_fs_ls(dwc_otg_core_if_t * core_if, int32_t val)
+-06023 {
+-06024         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
+-06025                 DWC_WARN("Wrong valaue for ulpi_fs_ls\n");
+-06026                 DWC_WARN("ulpi_fs_ls must be 0 or 1\n");
+-06027                 return -DWC_E_INVALID;
+-06028         }
+-06029 
+-06030         core_if->core_params->ulpi_fs_ls = val;
+-06031         return 0;
+-06032 }
+-06033 
+-06034 int32_t dwc_otg_get_param_ulpi_fs_ls(dwc_otg_core_if_t * core_if)
+-06035 {
+-06036         return core_if->core_params->ulpi_fs_ls;
+-06037 }
+-06038 
+-06039 int dwc_otg_set_param_ts_dline(dwc_otg_core_if_t * core_if, int32_t val)
+-06040 {
+-06041         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
+-06042                 DWC_WARN("Wrong valaue for ts_dline\n");
+-06043                 DWC_WARN("ts_dline must be 0 or 1\n");
+-06044                 return -DWC_E_INVALID;
+-06045         }
+-06046 
+-06047         core_if->core_params->ts_dline = val;
+-06048         return 0;
+-06049 }
+-06050 
+-06051 int32_t dwc_otg_get_param_ts_dline(dwc_otg_core_if_t * core_if)
+-06052 {
+-06053         return core_if->core_params->ts_dline;
+-06054 }
+-06055 
+-06056 int dwc_otg_set_param_i2c_enable(dwc_otg_core_if_t * core_if, int32_t val)
+-06057 {
+-06058         int retval = 0;
+-06059         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
+-06060                 DWC_WARN("Wrong valaue for i2c_enable\n");
+-06061                 DWC_WARN("i2c_enable must be 0 or 1\n");
+-06062                 return -DWC_E_INVALID;
+-06063         }
+-06064 #ifndef NO_FS_PHY_HW_CHECK
+-06065         if (val == 1 && core_if->hwcfg3.b.i2c == 0) {
+-06066                 if (dwc_otg_param_initialized(core_if->core_params->i2c_enable)) {
+-06067                         DWC_ERROR
+-06068                             ("%d invalid for i2c_enable. Check HW configuration.\n",
+-06069                              val);
+-06070                 }
+-06071                 val = 0;
+-06072                 retval = -DWC_E_INVALID;
+-06073         }
+-06074 #endif
+-06075 
+-06076         core_if->core_params->i2c_enable = val;
+-06077         return retval;
+-06078 }
+-06079 
+-06080 int32_t dwc_otg_get_param_i2c_enable(dwc_otg_core_if_t * core_if)
+-06081 {
+-06082         return core_if->core_params->i2c_enable;
+-06083 }
+-06084 
+-06085 int dwc_otg_set_param_dev_perio_tx_fifo_size(dwc_otg_core_if_t * core_if,
+-06086                                              int32_t val, int fifo_num)
+-06087 {
+-06088         int retval = 0;
+-06089 
+-06090         if (DWC_OTG_PARAM_TEST(val, 4, 768)) {
+-06091                 DWC_WARN("Wrong value for dev_perio_tx_fifo_size\n");
+-06092                 DWC_WARN("dev_perio_tx_fifo_size must be 4-768\n");
+-06093                 return -DWC_E_INVALID;
+-06094         }
+-06095 
+-06096         if (val >
+-06097             (DWC_READ_REG32(&core_if->core_global_regs->dtxfsiz[fifo_num]))) {
+-06098                 if (dwc_otg_param_initialized
+-06099                     (core_if->core_params->dev_perio_tx_fifo_size[fifo_num])) {
+-06100                         DWC_ERROR
+-06101                             ("`%d' invalid for parameter `dev_perio_fifo_size_%d'. Check HW configuration.\n",
+-06102                              val, fifo_num);
+-06103                 }
+-06104                 val = (DWC_READ_REG32(&core_if->core_global_regs->dtxfsiz[fifo_num]));
+-06105                 retval = -DWC_E_INVALID;
+-06106         }
+-06107 
+-06108         core_if->core_params->dev_perio_tx_fifo_size[fifo_num] = val;
+-06109         return retval;
+-06110 }
+-06111 
+-06112 int32_t dwc_otg_get_param_dev_perio_tx_fifo_size(dwc_otg_core_if_t * core_if,
+-06113                                                  int fifo_num)
+-06114 {
+-06115         return core_if->core_params->dev_perio_tx_fifo_size[fifo_num];
+-06116 }
+-06117 
+-06118 int dwc_otg_set_param_en_multiple_tx_fifo(dwc_otg_core_if_t * core_if,
+-06119                                           int32_t val)
+-06120 {
+-06121         int retval = 0;
+-06122         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
+-06123                 DWC_WARN("Wrong valaue for en_multiple_tx_fifo,\n");
+-06124                 DWC_WARN("en_multiple_tx_fifo must be 0 or 1\n");
+-06125                 return -DWC_E_INVALID;
+-06126         }
+-06127 
+-06128         if (val == 1 && core_if->hwcfg4.b.ded_fifo_en == 0) {
+-06129                 if (dwc_otg_param_initialized
+-06130                     (core_if->core_params->en_multiple_tx_fifo)) {
+-06131                         DWC_ERROR
+-06132                             ("%d invalid for parameter en_multiple_tx_fifo. Check HW configuration.\n",
+-06133                              val);
+-06134                 }
+-06135                 val = 0;
+-06136                 retval = -DWC_E_INVALID;
+-06137         }
+-06138 
+-06139         core_if->core_params->en_multiple_tx_fifo = val;
+-06140         return retval;
+-06141 }
+-06142 
+-06143 int32_t dwc_otg_get_param_en_multiple_tx_fifo(dwc_otg_core_if_t * core_if)
+-06144 {
+-06145         return core_if->core_params->en_multiple_tx_fifo;
+-06146 }
+-06147 
+-06148 int dwc_otg_set_param_dev_tx_fifo_size(dwc_otg_core_if_t * core_if, int32_t val,
+-06149                                        int fifo_num)
+-06150 {
+-06151         int retval = 0;
+-06152 
+-06153         if (DWC_OTG_PARAM_TEST(val, 4, 768)) {
+-06154                 DWC_WARN("Wrong value for dev_tx_fifo_size\n");
+-06155                 DWC_WARN("dev_tx_fifo_size must be 4-768\n");
+-06156                 return -DWC_E_INVALID;
+-06157         }
+-06158 
+-06159         if (val >
+-06160             (DWC_READ_REG32(&core_if->core_global_regs->dtxfsiz[fifo_num]))) {
+-06161                 if (dwc_otg_param_initialized
+-06162                     (core_if->core_params->dev_tx_fifo_size[fifo_num])) {
+-06163                         DWC_ERROR
+-06164                             ("`%d' invalid for parameter `dev_tx_fifo_size_%d'. Check HW configuration.\n",
+-06165                              val, fifo_num);
+-06166                 }
+-06167                 val = (DWC_READ_REG32(&core_if->core_global_regs->dtxfsiz[fifo_num]));
+-06168                 retval = -DWC_E_INVALID;
+-06169         }
+-06170 
+-06171         core_if->core_params->dev_tx_fifo_size[fifo_num] = val;
+-06172         return retval;
+-06173 }
+-06174 
+-06175 int32_t dwc_otg_get_param_dev_tx_fifo_size(dwc_otg_core_if_t * core_if,
+-06176                                            int fifo_num)
+-06177 {
+-06178         return core_if->core_params->dev_tx_fifo_size[fifo_num];
+-06179 }
+-06180 
+-06181 int dwc_otg_set_param_thr_ctl(dwc_otg_core_if_t * core_if, int32_t val)
+-06182 {
+-06183         int retval = 0;
+-06184 
+-06185         if (DWC_OTG_PARAM_TEST(val, 0, 7)) {
+-06186                 DWC_WARN("Wrong value for thr_ctl\n");
+-06187                 DWC_WARN("thr_ctl must be 0-7\n");
+-06188                 return -DWC_E_INVALID;
+-06189         }
+-06190 
+-06191         if ((val != 0) &&
+-06192             (!dwc_otg_get_param_dma_enable(core_if) ||
+-06193              !core_if->hwcfg4.b.ded_fifo_en)) {
+-06194                 if (dwc_otg_param_initialized(core_if->core_params->thr_ctl)) {
+-06195                         DWC_ERROR
+-06196                             ("%d invalid for parameter thr_ctl. Check HW configuration.\n",
+-06197                              val);
+-06198                 }
+-06199                 val = 0;
+-06200                 retval = -DWC_E_INVALID;
+-06201         }
+-06202 
+-06203         core_if->core_params->thr_ctl = val;
+-06204         return retval;
+-06205 }
+-06206 
+-06207 int32_t dwc_otg_get_param_thr_ctl(dwc_otg_core_if_t * core_if)
+-06208 {
+-06209         return core_if->core_params->thr_ctl;
+-06210 }
+-06211 
+-06212 int dwc_otg_set_param_lpm_enable(dwc_otg_core_if_t * core_if, int32_t val)
+-06213 {
+-06214         int retval = 0;
+-06215 
+-06216         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
+-06217                 DWC_WARN("Wrong value for lpm_enable\n");
+-06218                 DWC_WARN("lpm_enable must be 0 or 1\n");
+-06219                 return -DWC_E_INVALID;
+-06220         }
+-06221 
+-06222         if (val && !core_if->hwcfg3.b.otg_lpm_en) {
+-06223                 if (dwc_otg_param_initialized(core_if->core_params->lpm_enable)) {
+-06224                         DWC_ERROR
+-06225                             ("%d invalid for parameter lpm_enable. Check HW configuration.\n",
+-06226                              val);
+-06227                 }
+-06228                 val = 0;
+-06229                 retval = -DWC_E_INVALID;
+-06230         }
+-06231 
+-06232         core_if->core_params->lpm_enable = val;
+-06233         return retval;
+-06234 }
+-06235 
+-06236 int32_t dwc_otg_get_param_lpm_enable(dwc_otg_core_if_t * core_if)
+-06237 {
+-06238         return core_if->core_params->lpm_enable;
+-06239 }
+-06240 
+-06241 int dwc_otg_set_param_tx_thr_length(dwc_otg_core_if_t * core_if, int32_t val)
+-06242 {
+-06243         if (DWC_OTG_PARAM_TEST(val, 8, 128)) {
+-06244                 DWC_WARN("Wrong valaue for tx_thr_length\n");
+-06245                 DWC_WARN("tx_thr_length must be 8 - 128\n");
+-06246                 return -DWC_E_INVALID;
+-06247         }
+-06248 
+-06249         core_if->core_params->tx_thr_length = val;
+-06250         return 0;
+-06251 }
+-06252 
+-06253 int32_t dwc_otg_get_param_tx_thr_length(dwc_otg_core_if_t * core_if)
+-06254 {
+-06255         return core_if->core_params->tx_thr_length;
+-06256 }
+-06257 
+-06258 int dwc_otg_set_param_rx_thr_length(dwc_otg_core_if_t * core_if, int32_t val)
+-06259 {
+-06260         if (DWC_OTG_PARAM_TEST(val, 8, 128)) {
+-06261                 DWC_WARN("Wrong valaue for rx_thr_length\n");
+-06262                 DWC_WARN("rx_thr_length must be 8 - 128\n");
+-06263                 return -DWC_E_INVALID;
+-06264         }
+-06265 
+-06266         core_if->core_params->rx_thr_length = val;
+-06267         return 0;
+-06268 }
+-06269 
+-06270 int32_t dwc_otg_get_param_rx_thr_length(dwc_otg_core_if_t * core_if)
+-06271 {
+-06272         return core_if->core_params->rx_thr_length;
+-06273 }
+-06274 
+-06275 int dwc_otg_set_param_dma_burst_size(dwc_otg_core_if_t * core_if, int32_t val)
+-06276 {
+-06277         if (DWC_OTG_PARAM_TEST(val, 1, 1) &&
+-06278             DWC_OTG_PARAM_TEST(val, 4, 4) &&
+-06279             DWC_OTG_PARAM_TEST(val, 8, 8) &&
+-06280             DWC_OTG_PARAM_TEST(val, 16, 16) &&
+-06281             DWC_OTG_PARAM_TEST(val, 32, 32) &&
+-06282             DWC_OTG_PARAM_TEST(val, 64, 64) &&
+-06283             DWC_OTG_PARAM_TEST(val, 128, 128) &&
+-06284             DWC_OTG_PARAM_TEST(val, 256, 256)) {
+-06285                 DWC_WARN("`%d' invalid for parameter `dma_burst_size'\n", val);
+-06286                 return -DWC_E_INVALID;
+-06287         }
+-06288         core_if->core_params->dma_burst_size = val;
+-06289         return 0;
+-06290 }
+-06291 
+-06292 int32_t dwc_otg_get_param_dma_burst_size(dwc_otg_core_if_t * core_if)
+-06293 {
+-06294         return core_if->core_params->dma_burst_size;
+-06295 }
+-06296 
+-06297 int dwc_otg_set_param_pti_enable(dwc_otg_core_if_t * core_if, int32_t val)
+-06298 {
+-06299         int retval = 0;
+-06300         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
+-06301                 DWC_WARN("`%d' invalid for parameter `pti_enable'\n", val);
+-06302                 return -DWC_E_INVALID;
+-06303         }
+-06304         if (val && (core_if->snpsid < OTG_CORE_REV_2_72a)) {
+-06305                 if (dwc_otg_param_initialized(core_if->core_params->pti_enable)) {
+-06306                         DWC_ERROR
+-06307                             ("%d invalid for parameter pti_enable. Check HW configuration.\n",
+-06308                              val);
+-06309                 }
+-06310                 retval = -DWC_E_INVALID;
+-06311                 val = 0;
+-06312         }
+-06313         core_if->core_params->pti_enable = val;
+-06314         return retval;
+-06315 }
+-06316 
+-06317 int32_t dwc_otg_get_param_pti_enable(dwc_otg_core_if_t * core_if)
+-06318 {
+-06319         return core_if->core_params->pti_enable;
+-06320 }
+-06321 
+-06322 int dwc_otg_set_param_mpi_enable(dwc_otg_core_if_t * core_if, int32_t val)
+-06323 {
+-06324         int retval = 0;
+-06325         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
+-06326                 DWC_WARN("`%d' invalid for parameter `mpi_enable'\n", val);
+-06327                 return -DWC_E_INVALID;
+-06328         }
+-06329         if (val && (core_if->hwcfg2.b.multi_proc_int == 0)) {
+-06330                 if (dwc_otg_param_initialized(core_if->core_params->mpi_enable)) {
+-06331                         DWC_ERROR
+-06332                             ("%d invalid for parameter mpi_enable. Check HW configuration.\n",
+-06333                              val);
+-06334                 }
+-06335                 retval = -DWC_E_INVALID;
+-06336                 val = 0;
+-06337         }
+-06338         core_if->core_params->mpi_enable = val;
+-06339         return retval;
+-06340 }
+-06341 
+-06342 int32_t dwc_otg_get_param_mpi_enable(dwc_otg_core_if_t * core_if)
+-06343 {
+-06344         return core_if->core_params->mpi_enable;
+-06345 }
+-06346 
+-06347 int dwc_otg_set_param_adp_enable(dwc_otg_core_if_t * core_if, int32_t val)
+-06348 {
+-06349         int retval = 0;
+-06350         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
+-06351                 DWC_WARN("`%d' invalid for parameter `adp_enable'\n", val);
+-06352                 return -DWC_E_INVALID;
+-06353         }
+-06354         if (val && (core_if->hwcfg3.b.adp_supp == 0)) {
+-06355                 if (dwc_otg_param_initialized
+-06356                     (core_if->core_params->adp_supp_enable)) {
+-06357                         DWC_ERROR
+-06358                             ("%d invalid for parameter adp_enable. Check HW configuration.\n",
+-06359                              val);
+-06360                 }
+-06361                 retval = -DWC_E_INVALID;
+-06362                 val = 0;
+-06363         }
+-06364         core_if->core_params->adp_supp_enable = val;
+-06365         /*Set OTG version 2.0 in case of enabling ADP*/
+-06366         if (val)
+-06367                 dwc_otg_set_param_otg_ver(core_if, 1);
+-06368 
+-06369         return retval;
+-06370 }
+-06371 
+-06372 int32_t dwc_otg_get_param_adp_enable(dwc_otg_core_if_t * core_if)
+-06373 {
+-06374         return core_if->core_params->adp_supp_enable;
+-06375 }
+-06376 
+-06377 int dwc_otg_set_param_ic_usb_cap(dwc_otg_core_if_t * core_if, int32_t val)
+-06378 {
+-06379         int retval = 0;
+-06380         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
+-06381                 DWC_WARN("`%d' invalid for parameter `ic_usb_cap'\n", val);
+-06382                 DWC_WARN("ic_usb_cap must be 0 or 1\n");
+-06383                 return -DWC_E_INVALID;
+-06384         }
+-06385 
+-06386         if (val && (core_if->hwcfg2.b.otg_enable_ic_usb == 0)) {
+-06387                 if (dwc_otg_param_initialized(core_if->core_params->ic_usb_cap)) {
+-06388                         DWC_ERROR
+-06389                             ("%d invalid for parameter ic_usb_cap. Check HW configuration.\n",
+-06390                              val);
+-06391                 }
+-06392                 retval = -DWC_E_INVALID;
+-06393                 val = 0;
+-06394         }
+-06395         core_if->core_params->ic_usb_cap = val;
+-06396         return retval;
+-06397 }
+-06398 
+-06399 int32_t dwc_otg_get_param_ic_usb_cap(dwc_otg_core_if_t * core_if)
+-06400 {
+-06401         return core_if->core_params->ic_usb_cap;
+-06402 }
+-06403 
+-06404 int dwc_otg_set_param_ahb_thr_ratio(dwc_otg_core_if_t * core_if, int32_t val)
+-06405 {
+-06406         int retval = 0;
+-06407         int valid = 1;
+-06408 
+-06409         if (DWC_OTG_PARAM_TEST(val, 0, 3)) {
+-06410                 DWC_WARN("`%d' invalid for parameter `ahb_thr_ratio'\n", val);
+-06411                 DWC_WARN("ahb_thr_ratio must be 0 - 3\n");
+-06412                 return -DWC_E_INVALID;
+-06413         }
+-06414 
+-06415         if (val
+-06416             && (core_if->snpsid < OTG_CORE_REV_2_81a
+-06417                 || !dwc_otg_get_param_thr_ctl(core_if))) {
+-06418                 valid = 0;
+-06419         } else if (val
+-06420                    && ((dwc_otg_get_param_tx_thr_length(core_if) / (1 << val)) <
+-06421                        4)) {
+-06422                 valid = 0;
+-06423         }
+-06424         if (valid == 0) {
+-06425                 if (dwc_otg_param_initialized
+-06426                     (core_if->core_params->ahb_thr_ratio)) {
+-06427                         DWC_ERROR
+-06428                             ("%d invalid for parameter ahb_thr_ratio. Check HW configuration.\n",
+-06429                              val);
+-06430                 }
+-06431                 retval = -DWC_E_INVALID;
+-06432                 val = 0;
+-06433         }
+-06434 
+-06435         core_if->core_params->ahb_thr_ratio = val;
+-06436         return retval;
+-06437 }
+-06438 
+-06439 int32_t dwc_otg_get_param_ahb_thr_ratio(dwc_otg_core_if_t * core_if)
+-06440 {
+-06441         return core_if->core_params->ahb_thr_ratio;
+-06442 }
+-06443 
+-06444 int dwc_otg_set_param_power_down(dwc_otg_core_if_t * core_if, int32_t val)
+-06445 {
+-06446         int retval = 0;
+-06447         int valid = 1;
+-06448 
+-06449         if (DWC_OTG_PARAM_TEST(val, 0, 2)) {
+-06450                 DWC_WARN("`%d' invalid for parameter `power_down'\n", val);
+-06451                 DWC_WARN("power_down must be 0 - 2\n");
+-06452                 return -DWC_E_INVALID;
+-06453         }
+-06454 
+-06455         if ((val == 2) && (core_if->snpsid < OTG_CORE_REV_2_91a)) {
+-06456                 valid = 0;
+-06457         }
+-06458         if (valid == 0) {
+-06459                 if (dwc_otg_param_initialized(core_if->core_params->power_down)) {
+-06460                         DWC_ERROR
+-06461                             ("%d invalid for parameter power_down. Check HW configuration.\n",
+-06462                              val);
+-06463                 }
+-06464                 retval = -DWC_E_INVALID;
+-06465                 val = 0;
+-06466         }
+-06467         core_if->core_params->power_down = val;
+-06468         return retval;
+-06469 }
+-06470 
+-06471 int32_t dwc_otg_get_param_power_down(dwc_otg_core_if_t * core_if)
+-06472 {
+-06473         return core_if->core_params->power_down;
+-06474 }
+-06475 
+-06476 int dwc_otg_set_param_reload_ctl(dwc_otg_core_if_t * core_if, int32_t val)
+-06477 {
+-06478         int retval = 0;
+-06479         int valid = 1;
+-06480 
+-06481         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
+-06482                 DWC_WARN("`%d' invalid for parameter `reload_ctl'\n", val);
+-06483                 DWC_WARN("reload_ctl must be 0 or 1\n");
+-06484                 return -DWC_E_INVALID;
+-06485         }
+-06486 
+-06487         if ((val == 1) && (core_if->snpsid < OTG_CORE_REV_2_92a)) {
+-06488                 valid = 0;
+-06489         }
+-06490         if (valid == 0) {
+-06491                 if (dwc_otg_param_initialized(core_if->core_params->reload_ctl)) {
+-06492                         DWC_ERROR("%d invalid for parameter reload_ctl."
+-06493                                   "Check HW configuration.\n", val);
+-06494                 }
+-06495                 retval = -DWC_E_INVALID;
+-06496                 val = 0;
+-06497         }
+-06498         core_if->core_params->reload_ctl = val;
+-06499         return retval;
+-06500 }
+-06501 
+-06502 int32_t dwc_otg_get_param_reload_ctl(dwc_otg_core_if_t * core_if)
+-06503 {
+-06504         return core_if->core_params->reload_ctl;
+-06505 }
+-06506 
+-06507 int dwc_otg_set_param_dev_out_nak(dwc_otg_core_if_t * core_if, int32_t val)
+-06508 {
+-06509         int retval = 0;
+-06510         int valid = 1;
+-06511 
+-06512         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
+-06513                 DWC_WARN("`%d' invalid for parameter `dev_out_nak'\n", val);
+-06514                 DWC_WARN("dev_out_nak must be 0 or 1\n");
+-06515                 return -DWC_E_INVALID;
+-06516         }
+-06517 
+-06518         if ((val == 1) && ((core_if->snpsid < OTG_CORE_REV_2_93a) ||
+-06519                 !(core_if->core_params->dma_desc_enable))) {
+-06520                 valid = 0;
+-06521         }
+-06522         if (valid == 0) {
+-06523                 if (dwc_otg_param_initialized(core_if->core_params->dev_out_nak)) {
+-06524                         DWC_ERROR("%d invalid for parameter dev_out_nak."
+-06525                                 "Check HW configuration.\n", val);
+-06526                 }
+-06527                 retval = -DWC_E_INVALID;
+-06528                 val = 0;
+-06529         }
+-06530         core_if->core_params->dev_out_nak = val;
+-06531         return retval;
+-06532 }
+-06533 
+-06534 int32_t dwc_otg_get_param_dev_out_nak(dwc_otg_core_if_t * core_if)
+-06535 {
+-06536         return core_if->core_params->dev_out_nak;
+-06537 }
+-06538 
+-06539 int dwc_otg_set_param_cont_on_bna(dwc_otg_core_if_t * core_if, int32_t val)
+-06540 {
+-06541         int retval = 0;
+-06542         int valid = 1;
+-06543 
+-06544         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
+-06545                 DWC_WARN("`%d' invalid for parameter `cont_on_bna'\n", val);
+-06546                 DWC_WARN("cont_on_bna must be 0 or 1\n");
+-06547                 return -DWC_E_INVALID;
+-06548         }
+-06549 
+-06550         if ((val == 1) && ((core_if->snpsid < OTG_CORE_REV_2_94a) ||
+-06551                 !(core_if->core_params->dma_desc_enable))) {
+-06552                         valid = 0;
+-06553         }
+-06554         if (valid == 0) {
+-06555                 if (dwc_otg_param_initialized(core_if->core_params->cont_on_bna)) {
+-06556                         DWC_ERROR("%d invalid for parameter cont_on_bna."
+-06557                                 "Check HW configuration.\n", val);
+-06558                 }
+-06559                 retval = -DWC_E_INVALID;
+-06560                 val = 0;
+-06561         }
+-06562         core_if->core_params->cont_on_bna = val;
+-06563         return retval;
+-06564 }
+-06565 
+-06566 int32_t dwc_otg_get_param_cont_on_bna(dwc_otg_core_if_t * core_if)
+-06567 {
+-06568         return core_if->core_params->cont_on_bna;
+-06569 }
+-06570 
+-06571 int dwc_otg_set_param_ahb_single(dwc_otg_core_if_t * core_if, int32_t val)
+-06572 {
+-06573         int retval = 0;
+-06574         int valid = 1;
+-06575 
+-06576         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
+-06577                 DWC_WARN("`%d' invalid for parameter `ahb_single'\n", val);
+-06578                 DWC_WARN("ahb_single must be 0 or 1\n");
+-06579                 return -DWC_E_INVALID;
+-06580         }
+-06581 
+-06582         if ((val == 1) && (core_if->snpsid < OTG_CORE_REV_2_94a)) {
+-06583                         valid = 0;
+-06584         }
+-06585         if (valid == 0) {
+-06586                 if (dwc_otg_param_initialized(core_if->core_params->ahb_single)) {
+-06587                         DWC_ERROR("%d invalid for parameter ahb_single."
+-06588                                 "Check HW configuration.\n", val);
+-06589                 }
+-06590                 retval = -DWC_E_INVALID;
+-06591                 val = 0;
+-06592         }
+-06593         core_if->core_params->ahb_single = val;
+-06594         return retval;
+-06595 }
+-06596 
+-06597 int32_t dwc_otg_get_param_ahb_single(dwc_otg_core_if_t * core_if)
+-06598 {
+-06599         return core_if->core_params->ahb_single;
+-06600 }
+-06601 
+-06602 int dwc_otg_set_param_otg_ver(dwc_otg_core_if_t * core_if, int32_t val)
+-06603 {
+-06604         int retval = 0;
+-06605 
+-06606         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
+-06607                 DWC_WARN("`%d' invalid for parameter `otg_ver'\n", val);
+-06608                 DWC_WARN
+-06609                     ("otg_ver must be 0(for OTG 1.3 support) or 1(for OTG 2.0 support)\n");
+-06610                 return -DWC_E_INVALID;
+-06611         }
+-06612 
+-06613         core_if->core_params->otg_ver = val;
+-06614         return retval;
+-06615 }
+-06616 
+-06617 int32_t dwc_otg_get_param_otg_ver(dwc_otg_core_if_t * core_if)
+-06618 {
+-06619         return core_if->core_params->otg_ver;
+-06620 }
+-06621 
+-06622 uint32_t dwc_otg_get_hnpstatus(dwc_otg_core_if_t * core_if)
+-06623 {
+-06624         gotgctl_data_t otgctl;
+-06625         otgctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->gotgctl);
+-06626         return otgctl.b.hstnegscs;
+-06627 }
+-06628 
+-06629 uint32_t dwc_otg_get_srpstatus(dwc_otg_core_if_t * core_if)
+-06630 {
+-06631         gotgctl_data_t otgctl;
+-06632         otgctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->gotgctl);
+-06633         return otgctl.b.sesreqscs;
+-06634 }
+-06635 
+-06636 void dwc_otg_set_hnpreq(dwc_otg_core_if_t * core_if, uint32_t val)
+-06637 {
+-06638         if(core_if->otg_ver == 0) {
+-06639                 gotgctl_data_t otgctl;
+-06640                 otgctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->gotgctl);
+-06641                 otgctl.b.hnpreq = val;
+-06642                 DWC_WRITE_REG32(&core_if->core_global_regs->gotgctl, otgctl.d32);
+-06643         } else {
+-06644                 core_if->otg_sts = val;
+-06645         }
+-06646 }
+-06647 
+-06648 uint32_t dwc_otg_get_gsnpsid(dwc_otg_core_if_t * core_if)
+-06649 {
+-06650         return core_if->snpsid;
+-06651 }
+-06652 
+-06653 uint32_t dwc_otg_get_mode(dwc_otg_core_if_t * core_if)
+-06654 {
+-06655         gintsts_data_t gintsts;
+-06656         gintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts);
+-06657         return gintsts.b.curmode;
+-06658 }
+-06659 
+-06660 uint32_t dwc_otg_get_hnpcapable(dwc_otg_core_if_t * core_if)
+-06661 {
+-06662         gusbcfg_data_t usbcfg;
+-06663         usbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
+-06664         return usbcfg.b.hnpcap;
+-06665 }
+-06666 
+-06667 void dwc_otg_set_hnpcapable(dwc_otg_core_if_t * core_if, uint32_t val)
+-06668 {
+-06669         gusbcfg_data_t usbcfg;
+-06670         usbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
+-06671         usbcfg.b.hnpcap = val;
+-06672         DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, usbcfg.d32);
+-06673 }
+-06674 
+-06675 uint32_t dwc_otg_get_srpcapable(dwc_otg_core_if_t * core_if)
+-06676 {
+-06677         gusbcfg_data_t usbcfg;
+-06678         usbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
+-06679         return usbcfg.b.srpcap;
+-06680 }
+-06681 
+-06682 void dwc_otg_set_srpcapable(dwc_otg_core_if_t * core_if, uint32_t val)
+-06683 {
+-06684         gusbcfg_data_t usbcfg;
+-06685         usbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
+-06686         usbcfg.b.srpcap = val;
+-06687         DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, usbcfg.d32);
+-06688 }
+-06689 
+-06690 uint32_t dwc_otg_get_devspeed(dwc_otg_core_if_t * core_if)
+-06691 {
+-06692         dcfg_data_t dcfg;
+-06693         dcfg.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg);
+-06694         return dcfg.b.devspd;
+-06695 }
+-06696 
+-06697 void dwc_otg_set_devspeed(dwc_otg_core_if_t * core_if, uint32_t val)
+-06698 {
+-06699         dcfg_data_t dcfg;
+-06700         dcfg.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg);
+-06701         dcfg.b.devspd = val;
+-06702         DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dcfg, dcfg.d32);
+-06703 }
+-06704 
+-06705 uint32_t dwc_otg_get_busconnected(dwc_otg_core_if_t * core_if)
+-06706 {
+-06707         hprt0_data_t hprt0;
+-06708         hprt0.d32 = DWC_READ_REG32(core_if->host_if->hprt0);
+-06709         return hprt0.b.prtconnsts;
+-06710 }
+-06711 
+-06712 uint32_t dwc_otg_get_enumspeed(dwc_otg_core_if_t * core_if)
+-06713 {
+-06714         dsts_data_t dsts;
+-06715         dsts.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts);
+-06716         return dsts.b.enumspd;
+-06717 }
+-06718 
+-06719 uint32_t dwc_otg_get_prtpower(dwc_otg_core_if_t * core_if)
+-06720 {
+-06721         hprt0_data_t hprt0;
+-06722         hprt0.d32 = DWC_READ_REG32(core_if->host_if->hprt0);
+-06723         return hprt0.b.prtpwr;
+-06724 
+-06725 }
+-06726 
+-06727 uint32_t dwc_otg_get_core_state(dwc_otg_core_if_t * core_if)
+-06728 {
+-06729         return core_if->hibernation_suspend;
+-06730 }
+-06731 
+-06732 void dwc_otg_set_prtpower(dwc_otg_core_if_t * core_if, uint32_t val)
+-06733 {
+-06734         hprt0_data_t hprt0;
+-06735         hprt0.d32 = dwc_otg_read_hprt0(core_if);
+-06736         hprt0.b.prtpwr = val;
+-06737         DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
+-06738 }
+-06739 
+-06740 uint32_t dwc_otg_get_prtsuspend(dwc_otg_core_if_t * core_if)
+-06741 {
+-06742         hprt0_data_t hprt0;
+-06743         hprt0.d32 = DWC_READ_REG32(core_if->host_if->hprt0);
+-06744         return hprt0.b.prtsusp;
+-06745 
+-06746 }
+-06747 
+-06748 void dwc_otg_set_prtsuspend(dwc_otg_core_if_t * core_if, uint32_t val)
+-06749 {
+-06750         hprt0_data_t hprt0;
+-06751         hprt0.d32 = dwc_otg_read_hprt0(core_if);
+-06752         hprt0.b.prtsusp = val;
+-06753         DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
+-06754 }
+-06755 
+-06756 uint32_t dwc_otg_get_fr_interval(dwc_otg_core_if_t * core_if)
+-06757 {
+-06758         hfir_data_t hfir;
+-06759         hfir.d32 = DWC_READ_REG32(&core_if->host_if->host_global_regs->hfir);
+-06760         return hfir.b.frint;
+-06761 
+-06762 }
+-06763 
+-06764 void dwc_otg_set_fr_interval(dwc_otg_core_if_t * core_if, uint32_t val)
+-06765 {
+-06766         hfir_data_t hfir;
+-06767         uint32_t fram_int;
+-06768         fram_int = calc_frame_interval(core_if);
+-06769         hfir.d32 = DWC_READ_REG32(&core_if->host_if->host_global_regs->hfir);
+-06770         if (!core_if->core_params->reload_ctl) {
+-06771                 DWC_WARN("\nCannot reload HFIR register.HFIR.HFIRRldCtrl bit is"
+-06772                          "not set to 1.\nShould load driver with reload_ctl=1"
+-06773                          " module parameter\n");
+-06774                 return;
+-06775         }
+-06776         switch (fram_int) {
+-06777         case 3750:
+-06778                 if ((val < 3350) || (val > 4150)) {
+-06779                         DWC_WARN("HFIR interval for HS core and 30 MHz"
+-06780                                  "clock freq should be from 3350 to 4150\n");
+-06781                         return;
+-06782                 }
+-06783                 break;
+-06784         case 30000:
+-06785                 if ((val < 26820) || (val > 33180)) {
+-06786                         DWC_WARN("HFIR interval for FS/LS core and 30 MHz"
+-06787                                  "clock freq should be from 26820 to 33180\n");
+-06788                         return;
+-06789                 }
+-06790                 break;
+-06791         case 6000:
+-06792                 if ((val < 5360) || (val > 6640)) {
+-06793                         DWC_WARN("HFIR interval for HS core and 48 MHz"
+-06794                                  "clock freq should be from 5360 to 6640\n");
+-06795                         return;
+-06796                 }
+-06797                 break;
+-06798         case 48000:
+-06799                 if ((val < 42912) || (val > 53088)) {
+-06800                         DWC_WARN("HFIR interval for FS/LS core and 48 MHz"
+-06801                                  "clock freq should be from 42912 to 53088\n");
+-06802                         return;
+-06803                 }
+-06804                 break;
+-06805         case 7500:
+-06806                 if ((val < 6700) || (val > 8300)) {
+-06807                         DWC_WARN("HFIR interval for HS core and 60 MHz"
+-06808                                  "clock freq should be from 6700 to 8300\n");
+-06809                         return;
+-06810                 }
+-06811                 break;
+-06812         case 60000:
+-06813                 if ((val < 53640) || (val > 65536)) {
+-06814                         DWC_WARN("HFIR interval for FS/LS core and 60 MHz"
+-06815                                  "clock freq should be from 53640 to 65536\n");
+-06816                         return;
+-06817                 }
+-06818                 break;
+-06819         default:
+-06820                 DWC_WARN("Unknown frame interval\n");
+-06821                 return;
+-06822                 break;
+-06823 
+-06824         }
+-06825         hfir.b.frint = val;
+-06826         DWC_WRITE_REG32(&core_if->host_if->host_global_regs->hfir, hfir.d32);
+-06827 }
+-06828 
+-06829 uint32_t dwc_otg_get_mode_ch_tim(dwc_otg_core_if_t * core_if)
+-06830 {
+-06831         hcfg_data_t hcfg;
+-06832         hcfg.d32 = DWC_READ_REG32(&core_if->host_if->host_global_regs->hcfg);
+-06833         return hcfg.b.modechtimen;
+-06834 
+-06835 }
+-06836 
+-06837 void dwc_otg_set_mode_ch_tim(dwc_otg_core_if_t * core_if, uint32_t val)
+-06838 {
+-06839         hcfg_data_t hcfg;
+-06840         hcfg.d32 = DWC_READ_REG32(&core_if->host_if->host_global_regs->hcfg);
+-06841         hcfg.b.modechtimen = val;
+-06842         DWC_WRITE_REG32(&core_if->host_if->host_global_regs->hcfg, hcfg.d32);
+-06843 }
+-06844 
+-06845 void dwc_otg_set_prtresume(dwc_otg_core_if_t * core_if, uint32_t val)
+-06846 {
+-06847         hprt0_data_t hprt0;
+-06848         hprt0.d32 = dwc_otg_read_hprt0(core_if);
+-06849         hprt0.b.prtres = val;
+-06850         DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
+-06851 }
+-06852 
+-06853 uint32_t dwc_otg_get_remotewakesig(dwc_otg_core_if_t * core_if)
+-06854 {
+-06855         dctl_data_t dctl;
+-06856         dctl.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dctl);
+-06857         return dctl.b.rmtwkupsig;
+-06858 }
+-06859 
+-06860 uint32_t dwc_otg_get_lpm_portsleepstatus(dwc_otg_core_if_t * core_if)
+-06861 {
+-06862         glpmcfg_data_t lpmcfg;
+-06863         lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
+-06864 
+-06865         DWC_ASSERT(!
+-06866                    ((core_if->lx_state == DWC_OTG_L1) ^ lpmcfg.b.prt_sleep_sts),
+-06867                    "lx_state = %d, lmpcfg.prt_sleep_sts = %d\n",
+-06868                    core_if->lx_state, lpmcfg.b.prt_sleep_sts);
+-06869 
+-06870         return lpmcfg.b.prt_sleep_sts;
+-06871 }
+-06872 
+-06873 uint32_t dwc_otg_get_lpm_remotewakeenabled(dwc_otg_core_if_t * core_if)
+-06874 {
+-06875         glpmcfg_data_t lpmcfg;
+-06876         lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
+-06877         return lpmcfg.b.rem_wkup_en;
+-06878 }
+-06879 
+-06880 uint32_t dwc_otg_get_lpmresponse(dwc_otg_core_if_t * core_if)
+-06881 {
+-06882         glpmcfg_data_t lpmcfg;
+-06883         lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
+-06884         return lpmcfg.b.appl_resp;
+-06885 }
+-06886 
+-06887 void dwc_otg_set_lpmresponse(dwc_otg_core_if_t * core_if, uint32_t val)
+-06888 {
+-06889         glpmcfg_data_t lpmcfg;
+-06890         lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
+-06891         lpmcfg.b.appl_resp = val;
+-06892         DWC_WRITE_REG32(&core_if->core_global_regs->glpmcfg, lpmcfg.d32);
+-06893 }
+-06894 
+-06895 uint32_t dwc_otg_get_hsic_connect(dwc_otg_core_if_t * core_if)
+-06896 {
+-06897         glpmcfg_data_t lpmcfg;
+-06898         lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
+-06899         return lpmcfg.b.hsic_connect;
+-06900 }
+-06901 
+-06902 void dwc_otg_set_hsic_connect(dwc_otg_core_if_t * core_if, uint32_t val)
+-06903 {
+-06904         glpmcfg_data_t lpmcfg;
+-06905         lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
+-06906         lpmcfg.b.hsic_connect = val;
+-06907         DWC_WRITE_REG32(&core_if->core_global_regs->glpmcfg, lpmcfg.d32);
+-06908 }
+-06909 
+-06910 uint32_t dwc_otg_get_inv_sel_hsic(dwc_otg_core_if_t * core_if)
+-06911 {
+-06912         glpmcfg_data_t lpmcfg;
+-06913         lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
+-06914         return lpmcfg.b.inv_sel_hsic;
+-06915 
+-06916 }
+-06917 
+-06918 void dwc_otg_set_inv_sel_hsic(dwc_otg_core_if_t * core_if, uint32_t val)
+-06919 {
+-06920         glpmcfg_data_t lpmcfg;
+-06921         lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
+-06922         lpmcfg.b.inv_sel_hsic = val;
+-06923         DWC_WRITE_REG32(&core_if->core_global_regs->glpmcfg, lpmcfg.d32);
+-06924 }
+-06925 
+-06926 uint32_t dwc_otg_get_gotgctl(dwc_otg_core_if_t * core_if)
+-06927 {
+-06928         return DWC_READ_REG32(&core_if->core_global_regs->gotgctl);
+-06929 }
+-06930 
+-06931 void dwc_otg_set_gotgctl(dwc_otg_core_if_t * core_if, uint32_t val)
+-06932 {
+-06933         DWC_WRITE_REG32(&core_if->core_global_regs->gotgctl, val);
+-06934 }
+-06935 
+-06936 uint32_t dwc_otg_get_gusbcfg(dwc_otg_core_if_t * core_if)
+-06937 {
+-06938         return DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
+-06939 }
+-06940 
+-06941 void dwc_otg_set_gusbcfg(dwc_otg_core_if_t * core_if, uint32_t val)
+-06942 {
+-06943         DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, val);
+-06944 }
+-06945 
+-06946 uint32_t dwc_otg_get_grxfsiz(dwc_otg_core_if_t * core_if)
+-06947 {
+-06948         return DWC_READ_REG32(&core_if->core_global_regs->grxfsiz);
+-06949 }
+-06950 
+-06951 void dwc_otg_set_grxfsiz(dwc_otg_core_if_t * core_if, uint32_t val)
+-06952 {
+-06953         DWC_WRITE_REG32(&core_if->core_global_regs->grxfsiz, val);
+-06954 }
+-06955 
+-06956 uint32_t dwc_otg_get_gnptxfsiz(dwc_otg_core_if_t * core_if)
+-06957 {
+-06958         return DWC_READ_REG32(&core_if->core_global_regs->gnptxfsiz);
+-06959 }
+-06960 
+-06961 void dwc_otg_set_gnptxfsiz(dwc_otg_core_if_t * core_if, uint32_t val)
+-06962 {
+-06963         DWC_WRITE_REG32(&core_if->core_global_regs->gnptxfsiz, val);
+-06964 }
+-06965 
+-06966 uint32_t dwc_otg_get_gpvndctl(dwc_otg_core_if_t * core_if)
+-06967 {
+-06968         return DWC_READ_REG32(&core_if->core_global_regs->gpvndctl);
+-06969 }
+-06970 
+-06971 void dwc_otg_set_gpvndctl(dwc_otg_core_if_t * core_if, uint32_t val)
+-06972 {
+-06973         DWC_WRITE_REG32(&core_if->core_global_regs->gpvndctl, val);
+-06974 }
+-06975 
+-06976 uint32_t dwc_otg_get_ggpio(dwc_otg_core_if_t * core_if)
+-06977 {
+-06978         return DWC_READ_REG32(&core_if->core_global_regs->ggpio);
+-06979 }
+-06980 
+-06981 void dwc_otg_set_ggpio(dwc_otg_core_if_t * core_if, uint32_t val)
+-06982 {
+-06983         DWC_WRITE_REG32(&core_if->core_global_regs->ggpio, val);
+-06984 }
+-06985 
+-06986 uint32_t dwc_otg_get_hprt0(dwc_otg_core_if_t * core_if)
+-06987 {
+-06988         return DWC_READ_REG32(core_if->host_if->hprt0);
+-06989 
+-06990 }
+-06991 
+-06992 void dwc_otg_set_hprt0(dwc_otg_core_if_t * core_if, uint32_t val)
+-06993 {
+-06994         DWC_WRITE_REG32(core_if->host_if->hprt0, val);
+-06995 }
+-06996 
+-06997 uint32_t dwc_otg_get_guid(dwc_otg_core_if_t * core_if)
+-06998 {
+-06999         return DWC_READ_REG32(&core_if->core_global_regs->guid);
+-07000 }
+-07001 
+-07002 void dwc_otg_set_guid(dwc_otg_core_if_t * core_if, uint32_t val)
+-07003 {
+-07004         DWC_WRITE_REG32(&core_if->core_global_regs->guid, val);
+-07005 }
+-07006 
+-07007 uint32_t dwc_otg_get_hptxfsiz(dwc_otg_core_if_t * core_if)
+-07008 {
+-07009         return DWC_READ_REG32(&core_if->core_global_regs->hptxfsiz);
+-07010 }
+-07011 
+-07012 uint16_t dwc_otg_get_otg_version(dwc_otg_core_if_t * core_if)
+-07013 {
+-07014         return ((core_if->otg_ver == 1) ? (uint16_t)0x0200 : (uint16_t)0x0103);
+-07015 }
+-07016 
+-07023 void dwc_otg_pcd_start_srp_timer(dwc_otg_core_if_t * core_if)
+-07024 {
+-07025         core_if->srp_timer_started = 1;
+-07026         DWC_TIMER_SCHEDULE(core_if->srp_timer, 6000 /* 6 secs */ );
+-07027 }
+-07028 
+-07029 void dwc_otg_initiate_srp(dwc_otg_core_if_t * core_if)
+-07030 {
+-07031         uint32_t *addr = (uint32_t *) & (core_if->core_global_regs->gotgctl);
+-07032         gotgctl_data_t mem;
+-07033         gotgctl_data_t val;
+-07034 
+-07035         val.d32 = DWC_READ_REG32(addr);
+-07036         if (val.b.sesreq) {
+-07037                 DWC_ERROR("Session Request Already active!\n");
+-07038                 return;
+-07039         }
+-07040 
+-07041         DWC_INFO("Session Request Initated\n"); //NOTICE
+-07042         mem.d32 = DWC_READ_REG32(addr);
+-07043         mem.b.sesreq = 1;
+-07044         DWC_WRITE_REG32(addr, mem.d32);
+-07045 
+-07046         /* Start the SRP timer */
+-07047         dwc_otg_pcd_start_srp_timer(core_if);
+-07048         return;
+-07049 }
+-
                                                                                Generated on Thu Oct 27 03:56:37 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__cil_8c.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/dwc__otg__cil_8c.html 2013-07-26 19:34:40.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,3837 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_cil.c File Reference +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                dwc_otg_cil.c File Reference

                                                                                The Core Interface Layer provides basic services for accessing and managing the DWC_otg hardware. More... +-

                                                                                +-#include "dwc_os.h"
                                                                                +-#include "dwc_otg_regs.h"
                                                                                +-#include "dwc_otg_cil.h"
                                                                                +- +-

                                                                                +-Go to the source code of this file. +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-

                                                                                Defines

                                                                                #define DWC_OTG_PARAM_TEST(_param_, _low_, _high_)

                                                                                Functions

                                                                                +-int dwc_otg_setup_params (dwc_otg_core_if_t *core_if)
                                                                                dwc_otg_core_if_t * dwc_otg_cil_init (const uint32_t *reg_base_addr)
                                                                                 This function is called to initialize the DWC_otg CSR data structures.
                                                                                void dwc_otg_cil_remove (dwc_otg_core_if_t *core_if)
                                                                                 This function frees the structures allocated by dwc_otg_cil_init().
                                                                                void dwc_otg_enable_global_interrupts (dwc_otg_core_if_t *core_if)
                                                                                 This function enables the controller's Global Interrupt in the AHB Config register.
                                                                                void dwc_otg_disable_global_interrupts (dwc_otg_core_if_t *core_if)
                                                                                 This function disables the controller's Global Interrupt in the AHB Config register.
                                                                                void dwc_otg_enable_common_interrupts (dwc_otg_core_if_t *core_if)
                                                                                 This function initializes the commmon interrupts, used in both device and host modes.
                                                                                +-int dwc_otg_device_hibernation_restore (dwc_otg_core_if_t *core_if, int rem_wakeup, int reset)
                                                                                +-int dwc_otg_host_hibernation_restore (dwc_otg_core_if_t *core_if, int rem_wakeup, int reset)
                                                                                +-int dwc_otg_save_global_regs (dwc_otg_core_if_t *core_if)
                                                                                 Saves global register values into system memory.
                                                                                +-int dwc_otg_save_gintmsk_reg (dwc_otg_core_if_t *core_if)
                                                                                 Saves GINTMSK register before setting the msk bits.
                                                                                +-int dwc_otg_save_dev_regs (dwc_otg_core_if_t *core_if)
                                                                                 Saves device register values into system memory.
                                                                                +-int dwc_otg_save_host_regs (dwc_otg_core_if_t *core_if)
                                                                                 Saves host register values into system memory.
                                                                                +-int dwc_otg_restore_global_regs (dwc_otg_core_if_t *core_if)
                                                                                 Restore global register values.
                                                                                +-int dwc_otg_restore_dev_regs (dwc_otg_core_if_t *core_if, int rem_wakeup)
                                                                                 Restore device register values.
                                                                                +-int dwc_otg_restore_host_regs (dwc_otg_core_if_t *core_if, int reset)
                                                                                 Restore host register values.
                                                                                +-int restore_lpm_i2c_regs (dwc_otg_core_if_t *core_if)
                                                                                +-int restore_essential_regs (dwc_otg_core_if_t *core_if, int rmode, int is_host)
                                                                                +-void init_fslspclksel (dwc_otg_core_if_t *core_if)
                                                                                 Initializes the FSLSPClkSel field of the HCFG register depending on the PHY type.
                                                                                +-void init_devspd (dwc_otg_core_if_t *core_if)
                                                                                 Initializes the DevSpd field of the DCFG register depending on the PHY type and the enumeration speed of the device.
                                                                                uint32_t calc_num_in_eps (dwc_otg_core_if_t *core_if)
                                                                                 This function calculates the number of IN EPS using GHWCFG1 and GHWCFG2 registers values.
                                                                                uint32_t calc_num_out_eps (dwc_otg_core_if_t *core_if)
                                                                                 This function calculates the number of OUT EPS using GHWCFG1 and GHWCFG2 registers values.
                                                                                void dwc_otg_core_init (dwc_otg_core_if_t *core_if)
                                                                                 This function initializes the DWC_otg controller registers and prepares the core for device mode or host mode operation.
                                                                                void dwc_otg_enable_device_interrupts (dwc_otg_core_if_t *core_if)
                                                                                 This function enables the Device mode interrupts.
                                                                                void dwc_otg_core_dev_init (dwc_otg_core_if_t *core_if)
                                                                                 This function initializes the DWC_otg controller registers for device mode.
                                                                                void dwc_otg_enable_host_interrupts (dwc_otg_core_if_t *core_if)
                                                                                 This function enables the Host mode interrupts.
                                                                                void dwc_otg_disable_host_interrupts (dwc_otg_core_if_t *core_if)
                                                                                 This function disables the Host Mode interrupts.
                                                                                void dwc_otg_core_host_init (dwc_otg_core_if_t *core_if)
                                                                                 This function initializes the DWC_otg controller registers for host mode.
                                                                                void dwc_otg_hc_init (dwc_otg_core_if_t *core_if, dwc_hc_t *hc)
                                                                                 Prepares a host channel for transferring packets to/from a specific endpoint.
                                                                                void dwc_otg_hc_halt (dwc_otg_core_if_t *core_if, dwc_hc_t *hc, dwc_otg_halt_status_e halt_status)
                                                                                 Attempts to halt a host channel.
                                                                                void dwc_otg_hc_cleanup (dwc_otg_core_if_t *core_if, dwc_hc_t *hc)
                                                                                 Clears the transfer state for a host channel.
                                                                                void hc_set_even_odd_frame (dwc_otg_core_if_t *core_if, dwc_hc_t *hc, hcchar_data_t *hcchar)
                                                                                 Sets the channel property that indicates in which frame a periodic transfer should occur.
                                                                                +-void ep_xfer_timeout (void *ptr)
                                                                                +-void set_pid_isoc (dwc_hc_t *hc)
                                                                                void dwc_otg_hc_start_transfer (dwc_otg_core_if_t *core_if, dwc_hc_t *hc)
                                                                                 This function does the setup for a data transfer for a host channel and starts the transfer.
                                                                                void dwc_otg_hc_start_transfer_ddma (dwc_otg_core_if_t *core_if, dwc_hc_t *hc)
                                                                                 This function does the setup for a data transfer for a host channel and starts the transfer in Descriptor DMA mode.
                                                                                int dwc_otg_hc_continue_transfer (dwc_otg_core_if_t *core_if, dwc_hc_t *hc)
                                                                                 This function continues a data transfer that was started by previous call to dwc_otg_hc_start_transfer.
                                                                                void dwc_otg_hc_do_ping (dwc_otg_core_if_t *core_if, dwc_hc_t *hc)
                                                                                 Starts a PING transfer.
                                                                                +-void dwc_otg_hc_write_packet (dwc_otg_core_if_t *core_if, dwc_hc_t *hc)
                                                                                uint32_t dwc_otg_get_frame_number (dwc_otg_core_if_t *core_if)
                                                                                 Gets the current USB frame number.
                                                                                +-uint32_t calc_frame_interval (dwc_otg_core_if_t *core_if)
                                                                                 Calculates and gets the frame Interval value of HFIR register according PHY type and speed.The application can modify a value of HFIR register only after the Port Enable bit of the Host Port Control and Status register (HPRT.PrtEnaPort) has been set.
                                                                                void dwc_otg_read_setup_packet (dwc_otg_core_if_t *core_if, uint32_t *dest)
                                                                                 This function reads a setup packet from the Rx FIFO into the destination buffer.
                                                                                void dwc_otg_ep0_activate (dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
                                                                                 This function enables EP0 OUT to receive SETUP packets and configures EP0 IN for transmitting packets.
                                                                                void dwc_otg_ep_activate (dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
                                                                                 This function activates an EP.
                                                                                void dwc_otg_ep_deactivate (dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
                                                                                 This function deactivates an EP.
                                                                                void init_dma_desc_chain (dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
                                                                                 This function initializes dma descriptor chain.
                                                                                +-int32_t write_isoc_tx_fifo (dwc_otg_core_if_t *core_if, dwc_ep_t *dwc_ep)
                                                                                 This function is called when to write ISOC data into appropriate dedicated periodic FIFO.
                                                                                void dwc_otg_ep_start_transfer (dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
                                                                                 This function does the setup for a data transfer for an EP and starts the transfer.
                                                                                void dwc_otg_ep_start_zl_transfer (dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
                                                                                 This function setup a zero length transfer in Buffer DMA and Slave modes for usb requests with zero field set.
                                                                                void dwc_otg_ep0_start_transfer (dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
                                                                                 This function does the setup for a data transfer for EP0 and starts the transfer.
                                                                                void dwc_otg_ep0_continue_transfer (dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
                                                                                 This function continues control IN transfers started by dwc_otg_ep0_start_transfer, when the transfer does not fit in a single packet.
                                                                                +-void dump_msg (const u8 *buf, unsigned int length)
                                                                                void dwc_otg_ep_write_packet (dwc_otg_core_if_t *core_if, dwc_ep_t *ep, int dma)
                                                                                 This function writes a packet into the Tx FIFO associated with the EP.
                                                                                void dwc_otg_ep_set_stall (dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
                                                                                 Set the EP STALL.
                                                                                void dwc_otg_ep_clear_stall (dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
                                                                                 Clear the EP STALL.
                                                                                void dwc_otg_read_packet (dwc_otg_core_if_t *core_if, uint8_t *dest, uint16_t bytes)
                                                                                 This function reads a packet from the Rx FIFO into the destination buffer.
                                                                                void dwc_otg_dump_dev_registers (dwc_otg_core_if_t *core_if)
                                                                                 Dump core registers and SPRAM.
                                                                                void dwc_otg_dump_spram (dwc_otg_core_if_t *core_if)
                                                                                 This functions reads the SPRAM and prints its content.
                                                                                void dwc_otg_dump_host_registers (dwc_otg_core_if_t *core_if)
                                                                                 This function reads the host registers and prints them.
                                                                                void dwc_otg_dump_global_registers (dwc_otg_core_if_t *core_if)
                                                                                 This function reads the core global registers and prints them.
                                                                                void dwc_otg_flush_tx_fifo (dwc_otg_core_if_t *core_if, const int num)
                                                                                 Flush a Tx FIFO.
                                                                                void dwc_otg_flush_rx_fifo (dwc_otg_core_if_t *core_if)
                                                                                 Flush Rx FIFO.
                                                                                void dwc_otg_core_reset (dwc_otg_core_if_t *core_if)
                                                                                 Do core a soft reset of the core.
                                                                                +-uint8_t dwc_otg_is_device_mode (dwc_otg_core_if_t *_core_if)
                                                                                +-uint8_t dwc_otg_is_host_mode (dwc_otg_core_if_t *_core_if)
                                                                                void dwc_otg_cil_register_hcd_callbacks (dwc_otg_core_if_t *core_if, dwc_otg_cil_callbacks_t *cb, void *p)
                                                                                 Register HCD callbacks.
                                                                                void dwc_otg_cil_register_pcd_callbacks (dwc_otg_core_if_t *core_if, dwc_otg_cil_callbacks_t *cb, void *p)
                                                                                 Register PCD callbacks.
                                                                                void write_isoc_frame_data (dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
                                                                                 This function writes isoc data per 1 (micro)frame into tx fifo.
                                                                                void dwc_otg_iso_ep_start_frm_transfer (dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
                                                                                 This function initializes a descriptor chain for Isochronous transfer.
                                                                                +-void dwc_otg_set_uninitialized (int32_t *p, int size)
                                                                                +-int dwc_otg_param_initialized (int32_t val)
                                                                                +-uint8_t dwc_otg_is_dma_enable (dwc_otg_core_if_t *core_if)
                                                                                int dwc_otg_set_param_otg_cap (dwc_otg_core_if_t *core_if, int32_t val)
                                                                                 Specifies the OTG capabilities.
                                                                                +-int32_t dwc_otg_get_param_otg_cap (dwc_otg_core_if_t *core_if)
                                                                                +-int dwc_otg_set_param_opt (dwc_otg_core_if_t *core_if, int32_t val)
                                                                                +-int32_t dwc_otg_get_param_opt (dwc_otg_core_if_t *core_if)
                                                                                int dwc_otg_set_param_dma_enable (dwc_otg_core_if_t *core_if, int32_t val)
                                                                                 Specifies whether to use slave or DMA mode for accessing the data FIFOs.
                                                                                +-int32_t dwc_otg_get_param_dma_enable (dwc_otg_core_if_t *core_if)
                                                                                int dwc_otg_set_param_dma_desc_enable (dwc_otg_core_if_t *core_if, int32_t val)
                                                                                 When DMA mode is enabled specifies whether to use address DMA or DMA Descritor mode for accessing the data FIFOs in device mode.
                                                                                +-int32_t dwc_otg_get_param_dma_desc_enable (dwc_otg_core_if_t *core_if)
                                                                                int dwc_otg_set_param_host_support_fs_ls_low_power (dwc_otg_core_if_t *core_if, int32_t val)
                                                                                 Specifies whether low power mode is supported when attached to a Full Speed or Low Speed device in host mode.
                                                                                +-int32_t dwc_otg_get_param_host_support_fs_ls_low_power (dwc_otg_core_if_t *core_if)
                                                                                +-int dwc_otg_set_param_enable_dynamic_fifo (dwc_otg_core_if_t *core_if, int32_t val)
                                                                                 0 - Use cC FIFO size parameters 1 - Allow dynamic FIFO sizing (default)
                                                                                +-int32_t dwc_otg_get_param_enable_dynamic_fifo (dwc_otg_core_if_t *core_if)
                                                                                int dwc_otg_set_param_data_fifo_size (dwc_otg_core_if_t *core_if, int32_t val)
                                                                                 Total number of 4-byte words in the data FIFO memory.
                                                                                +-int32_t dwc_otg_get_param_data_fifo_size (dwc_otg_core_if_t *core_if)
                                                                                int dwc_otg_set_param_dev_rx_fifo_size (dwc_otg_core_if_t *core_if, int32_t val)
                                                                                 Number of 4-byte words in the Rx FIFO in device mode when dynamic FIFO sizing is enabled.
                                                                                +-int32_t dwc_otg_get_param_dev_rx_fifo_size (dwc_otg_core_if_t *core_if)
                                                                                int dwc_otg_set_param_dev_nperio_tx_fifo_size (dwc_otg_core_if_t *core_if, int32_t val)
                                                                                 Number of 4-byte words in the non-periodic Tx FIFO in device mode when dynamic FIFO sizing is enabled.
                                                                                +-int32_t dwc_otg_get_param_dev_nperio_tx_fifo_size (dwc_otg_core_if_t *core_if)
                                                                                int dwc_otg_set_param_host_rx_fifo_size (dwc_otg_core_if_t *core_if, int32_t val)
                                                                                 Number of 4-byte words in the Rx FIFO in host mode when dynamic FIFO sizing is enabled.
                                                                                +-int32_t dwc_otg_get_param_host_rx_fifo_size (dwc_otg_core_if_t *core_if)
                                                                                int dwc_otg_set_param_host_nperio_tx_fifo_size (dwc_otg_core_if_t *core_if, int32_t val)
                                                                                 Number of 4-byte words in the non-periodic Tx FIFO in host mode when Dynamic FIFO sizing is enabled in the core.
                                                                                +-int32_t dwc_otg_get_param_host_nperio_tx_fifo_size (dwc_otg_core_if_t *core_if)
                                                                                int dwc_otg_set_param_host_perio_tx_fifo_size (dwc_otg_core_if_t *core_if, int32_t val)
                                                                                 Number of 4-byte words in the host periodic Tx FIFO when dynamic FIFO sizing is enabled.
                                                                                +-int32_t dwc_otg_get_param_host_perio_tx_fifo_size (dwc_otg_core_if_t *core_if)
                                                                                int dwc_otg_set_param_max_transfer_size (dwc_otg_core_if_t *core_if, int32_t val)
                                                                                 The maximum transfer size supported in bytes.
                                                                                +-int32_t dwc_otg_get_param_max_transfer_size (dwc_otg_core_if_t *core_if)
                                                                                int dwc_otg_set_param_max_packet_count (dwc_otg_core_if_t *core_if, int32_t val)
                                                                                 The maximum number of packets in a transfer.
                                                                                +-int32_t dwc_otg_get_param_max_packet_count (dwc_otg_core_if_t *core_if)
                                                                                int dwc_otg_set_param_host_channels (dwc_otg_core_if_t *core_if, int32_t val)
                                                                                 The number of host channel registers to use.
                                                                                +-int32_t dwc_otg_get_param_host_channels (dwc_otg_core_if_t *core_if)
                                                                                int dwc_otg_set_param_dev_endpoints (dwc_otg_core_if_t *core_if, int32_t val)
                                                                                 The number of endpoints in addition to EP0 available for device mode operations.
                                                                                +-int32_t dwc_otg_get_param_dev_endpoints (dwc_otg_core_if_t *core_if)
                                                                                int dwc_otg_set_param_phy_type (dwc_otg_core_if_t *core_if, int32_t val)
                                                                                 Specifies the type of PHY interface to use.
                                                                                +-int32_t dwc_otg_get_param_phy_type (dwc_otg_core_if_t *core_if)
                                                                                int dwc_otg_set_param_speed (dwc_otg_core_if_t *core_if, int32_t val)
                                                                                 Specifies the maximum speed of operation in host and device mode.
                                                                                +-int32_t dwc_otg_get_param_speed (dwc_otg_core_if_t *core_if)
                                                                                int dwc_otg_set_param_host_ls_low_power_phy_clk (dwc_otg_core_if_t *core_if, int32_t val)
                                                                                 Specifies the PHY clock rate in low power mode when connected to a Low Speed device in host mode.
                                                                                +-int32_t dwc_otg_get_param_host_ls_low_power_phy_clk (dwc_otg_core_if_t *core_if)
                                                                                int dwc_otg_set_param_phy_ulpi_ddr (dwc_otg_core_if_t *core_if, int32_t val)
                                                                                 Specifies whether the ULPI operates at double or single data rate.
                                                                                +-int32_t dwc_otg_get_param_phy_ulpi_ddr (dwc_otg_core_if_t *core_if)
                                                                                +-int dwc_otg_set_param_phy_ulpi_ext_vbus (dwc_otg_core_if_t *core_if, int32_t val)
                                                                                 Specifies whether to use the internal or external supply to drive the vbus with a ULPI phy.
                                                                                +-int32_t dwc_otg_get_param_phy_ulpi_ext_vbus (dwc_otg_core_if_t *core_if)
                                                                                int dwc_otg_set_param_phy_utmi_width (dwc_otg_core_if_t *core_if, int32_t val)
                                                                                 Specifies the UTMI+ Data Width.
                                                                                +-int32_t dwc_otg_get_param_phy_utmi_width (dwc_otg_core_if_t *core_if)
                                                                                +-int dwc_otg_set_param_ulpi_fs_ls (dwc_otg_core_if_t *core_if, int32_t val)
                                                                                +-int32_t dwc_otg_get_param_ulpi_fs_ls (dwc_otg_core_if_t *core_if)
                                                                                +-int dwc_otg_set_param_ts_dline (dwc_otg_core_if_t *core_if, int32_t val)
                                                                                +-int32_t dwc_otg_get_param_ts_dline (dwc_otg_core_if_t *core_if)
                                                                                int dwc_otg_set_param_i2c_enable (dwc_otg_core_if_t *core_if, int32_t val)
                                                                                 Specifies whether to use the I2Cinterface for full speed PHY.
                                                                                +-int32_t dwc_otg_get_param_i2c_enable (dwc_otg_core_if_t *core_if)
                                                                                int dwc_otg_set_param_dev_perio_tx_fifo_size (dwc_otg_core_if_t *core_if, int32_t val, int fifo_num)
                                                                                 Number of 4-byte words in each of the periodic Tx FIFOs in device mode when dynamic FIFO sizing is enabled.
                                                                                +-int32_t dwc_otg_get_param_dev_perio_tx_fifo_size (dwc_otg_core_if_t *core_if, int fifo_num)
                                                                                +-int dwc_otg_set_param_en_multiple_tx_fifo (dwc_otg_core_if_t *core_if, int32_t val)
                                                                                 Specifies whether dedicated transmit FIFOs are enabled for non periodic IN endpoints in device mode 0 - No 1 - Yes.
                                                                                +-int32_t dwc_otg_get_param_en_multiple_tx_fifo (dwc_otg_core_if_t *core_if)
                                                                                +-int dwc_otg_set_param_dev_tx_fifo_size (dwc_otg_core_if_t *core_if, int32_t val, int fifo_num)
                                                                                +-int32_t dwc_otg_get_param_dev_tx_fifo_size (dwc_otg_core_if_t *core_if, int fifo_num)
                                                                                +-int dwc_otg_set_param_thr_ctl (dwc_otg_core_if_t *core_if, int32_t val)
                                                                                 Thresholding enable flag- bit 0 - enable non-ISO Tx thresholding bit 1 - enable ISO Tx thresholding bit 2 - enable Rx thresholding.
                                                                                +-int32_t dwc_otg_get_param_thr_ctl (dwc_otg_core_if_t *core_if)
                                                                                +-int dwc_otg_set_param_lpm_enable (dwc_otg_core_if_t *core_if, int32_t val)
                                                                                 Specifies whether LPM (Link Power Management) support is enabled.
                                                                                +-int32_t dwc_otg_get_param_lpm_enable (dwc_otg_core_if_t *core_if)
                                                                                +-int dwc_otg_set_param_tx_thr_length (dwc_otg_core_if_t *core_if, int32_t val)
                                                                                 Thresholding length for Tx FIFOs in 32 bit DWORDs.
                                                                                +-int32_t dwc_otg_get_param_tx_thr_length (dwc_otg_core_if_t *core_if)
                                                                                +-int dwc_otg_set_param_rx_thr_length (dwc_otg_core_if_t *core_if, int32_t val)
                                                                                 Thresholding length for Rx FIFOs in 32 bit DWORDs.
                                                                                +-int32_t dwc_otg_get_param_rx_thr_length (dwc_otg_core_if_t *core_if)
                                                                                int dwc_otg_set_param_dma_burst_size (dwc_otg_core_if_t *core_if, int32_t val)
                                                                                 The DMA Burst size (applicable only for External DMA Mode).
                                                                                +-int32_t dwc_otg_get_param_dma_burst_size (dwc_otg_core_if_t *core_if)
                                                                                +-int dwc_otg_set_param_pti_enable (dwc_otg_core_if_t *core_if, int32_t val)
                                                                                 Specifies whether PTI enhancement is enabled.
                                                                                +-int32_t dwc_otg_get_param_pti_enable (dwc_otg_core_if_t *core_if)
                                                                                +-int dwc_otg_set_param_mpi_enable (dwc_otg_core_if_t *core_if, int32_t val)
                                                                                 Specifies whether MPI enhancement is enabled.
                                                                                +-int32_t dwc_otg_get_param_mpi_enable (dwc_otg_core_if_t *core_if)
                                                                                +-int dwc_otg_set_param_adp_enable (dwc_otg_core_if_t *core_if, int32_t val)
                                                                                 Specifies whether ADP capability is enabled.
                                                                                +-int32_t dwc_otg_get_param_adp_enable (dwc_otg_core_if_t *core_if)
                                                                                +-int dwc_otg_set_param_ic_usb_cap (dwc_otg_core_if_t *core_if, int32_t val)
                                                                                 Specifies whether IC_USB capability is enabled.
                                                                                +-int32_t dwc_otg_get_param_ic_usb_cap (dwc_otg_core_if_t *core_if)
                                                                                +-int dwc_otg_set_param_ahb_thr_ratio (dwc_otg_core_if_t *core_if, int32_t val)
                                                                                +-int32_t dwc_otg_get_param_ahb_thr_ratio (dwc_otg_core_if_t *core_if)
                                                                                +-int dwc_otg_set_param_power_down (dwc_otg_core_if_t *core_if, int32_t val)
                                                                                +-int32_t dwc_otg_get_param_power_down (dwc_otg_core_if_t *core_if)
                                                                                +-int dwc_otg_set_param_reload_ctl (dwc_otg_core_if_t *core_if, int32_t val)
                                                                                +-int32_t dwc_otg_get_param_reload_ctl (dwc_otg_core_if_t *core_if)
                                                                                +-int dwc_otg_set_param_dev_out_nak (dwc_otg_core_if_t *core_if, int32_t val)
                                                                                +-int32_t dwc_otg_get_param_dev_out_nak (dwc_otg_core_if_t *core_if)
                                                                                +-int dwc_otg_set_param_cont_on_bna (dwc_otg_core_if_t *core_if, int32_t val)
                                                                                +-int32_t dwc_otg_get_param_cont_on_bna (dwc_otg_core_if_t *core_if)
                                                                                +-int dwc_otg_set_param_ahb_single (dwc_otg_core_if_t *core_if, int32_t val)
                                                                                +-int32_t dwc_otg_get_param_ahb_single (dwc_otg_core_if_t *core_if)
                                                                                +-int dwc_otg_set_param_otg_ver (dwc_otg_core_if_t *core_if, int32_t val)
                                                                                +-int32_t dwc_otg_get_param_otg_ver (dwc_otg_core_if_t *core_if)
                                                                                +-uint32_t dwc_otg_get_hnpstatus (dwc_otg_core_if_t *core_if)
                                                                                 Get host negotiation status.
                                                                                +-uint32_t dwc_otg_get_srpstatus (dwc_otg_core_if_t *core_if)
                                                                                 Get srp status.
                                                                                +-void dwc_otg_set_hnpreq (dwc_otg_core_if_t *core_if, uint32_t val)
                                                                                 Set hnpreq bit in the GOTGCTL register.
                                                                                +-uint32_t dwc_otg_get_gsnpsid (dwc_otg_core_if_t *core_if)
                                                                                 Get Content of SNPSID register.
                                                                                uint32_t dwc_otg_get_mode (dwc_otg_core_if_t *core_if)
                                                                                 Get current mode.
                                                                                +-uint32_t dwc_otg_get_hnpcapable (dwc_otg_core_if_t *core_if)
                                                                                 Get value of hnpcapable field in the GUSBCFG register.
                                                                                +-void dwc_otg_set_hnpcapable (dwc_otg_core_if_t *core_if, uint32_t val)
                                                                                 Set value of hnpcapable field in the GUSBCFG register.
                                                                                +-uint32_t dwc_otg_get_srpcapable (dwc_otg_core_if_t *core_if)
                                                                                 Get value of srpcapable field in the GUSBCFG register.
                                                                                +-void dwc_otg_set_srpcapable (dwc_otg_core_if_t *core_if, uint32_t val)
                                                                                 Set value of srpcapable field in the GUSBCFG register.
                                                                                +-uint32_t dwc_otg_get_devspeed (dwc_otg_core_if_t *core_if)
                                                                                 Get value of devspeed field in the DCFG register.
                                                                                +-void dwc_otg_set_devspeed (dwc_otg_core_if_t *core_if, uint32_t val)
                                                                                 Set value of devspeed field in the DCFG register.
                                                                                +-uint32_t dwc_otg_get_busconnected (dwc_otg_core_if_t *core_if)
                                                                                 Get the value of busconnected field from the HPRT0 register.
                                                                                +-uint32_t dwc_otg_get_enumspeed (dwc_otg_core_if_t *core_if)
                                                                                 Gets the device enumeration Speed.
                                                                                +-uint32_t dwc_otg_get_prtpower (dwc_otg_core_if_t *core_if)
                                                                                 Get value of prtpwr field from the HPRT0 register.
                                                                                +-uint32_t dwc_otg_get_core_state (dwc_otg_core_if_t *core_if)
                                                                                 Get value of flag indicating core state - hibernated or not.
                                                                                +-void dwc_otg_set_prtpower (dwc_otg_core_if_t *core_if, uint32_t val)
                                                                                 Set value of prtpwr field from the HPRT0 register.
                                                                                +-uint32_t dwc_otg_get_prtsuspend (dwc_otg_core_if_t *core_if)
                                                                                 Get value of prtsusp field from the HPRT0 regsiter.
                                                                                +-void dwc_otg_set_prtsuspend (dwc_otg_core_if_t *core_if, uint32_t val)
                                                                                 Set value of prtpwr field from the HPRT0 register.
                                                                                +-uint32_t dwc_otg_get_fr_interval (dwc_otg_core_if_t *core_if)
                                                                                 Get value of Fram Interval field from the HFIR regsiter.
                                                                                +-void dwc_otg_set_fr_interval (dwc_otg_core_if_t *core_if, uint32_t val)
                                                                                 Set value of Frame Interval field from the HFIR regsiter.
                                                                                +-uint32_t dwc_otg_get_mode_ch_tim (dwc_otg_core_if_t *core_if)
                                                                                 Get value of ModeChTimEn field from the HCFG regsiter.
                                                                                +-void dwc_otg_set_mode_ch_tim (dwc_otg_core_if_t *core_if, uint32_t val)
                                                                                 Set value of ModeChTimEn field from the HCFG regsiter.
                                                                                +-void dwc_otg_set_prtresume (dwc_otg_core_if_t *core_if, uint32_t val)
                                                                                 Set value of prtres field from the HPRT0 register FIXME Remove?
                                                                                +-uint32_t dwc_otg_get_remotewakesig (dwc_otg_core_if_t *core_if)
                                                                                 Get value of rmtwkupsig bit in DCTL register.
                                                                                +-uint32_t dwc_otg_get_lpm_portsleepstatus (dwc_otg_core_if_t *core_if)
                                                                                 Get value of prt_sleep_sts field from the GLPMCFG register.
                                                                                +-uint32_t dwc_otg_get_lpm_remotewakeenabled (dwc_otg_core_if_t *core_if)
                                                                                 Get value of rem_wkup_en field from the GLPMCFG register.
                                                                                +-uint32_t dwc_otg_get_lpmresponse (dwc_otg_core_if_t *core_if)
                                                                                 Get value of appl_resp field from the GLPMCFG register.
                                                                                +-void dwc_otg_set_lpmresponse (dwc_otg_core_if_t *core_if, uint32_t val)
                                                                                 Set value of appl_resp field from the GLPMCFG register.
                                                                                +-uint32_t dwc_otg_get_hsic_connect (dwc_otg_core_if_t *core_if)
                                                                                 Get value of hsic_connect field from the GLPMCFG register.
                                                                                +-void dwc_otg_set_hsic_connect (dwc_otg_core_if_t *core_if, uint32_t val)
                                                                                 Set value of hsic_connect field from the GLPMCFG register.
                                                                                +-uint32_t dwc_otg_get_inv_sel_hsic (dwc_otg_core_if_t *core_if)
                                                                                 Get value of inv_sel_hsic field from the GLPMCFG register.
                                                                                +-void dwc_otg_set_inv_sel_hsic (dwc_otg_core_if_t *core_if, uint32_t val)
                                                                                 Set value of inv_sel_hsic field from the GLPMFG register.
                                                                                +-uint32_t dwc_otg_get_gotgctl (dwc_otg_core_if_t *core_if)
                                                                                 GOTGCTL register.
                                                                                +-void dwc_otg_set_gotgctl (dwc_otg_core_if_t *core_if, uint32_t val)
                                                                                +-uint32_t dwc_otg_get_gusbcfg (dwc_otg_core_if_t *core_if)
                                                                                 GUSBCFG register.
                                                                                +-void dwc_otg_set_gusbcfg (dwc_otg_core_if_t *core_if, uint32_t val)
                                                                                +-uint32_t dwc_otg_get_grxfsiz (dwc_otg_core_if_t *core_if)
                                                                                 GRXFSIZ register.
                                                                                +-void dwc_otg_set_grxfsiz (dwc_otg_core_if_t *core_if, uint32_t val)
                                                                                +-uint32_t dwc_otg_get_gnptxfsiz (dwc_otg_core_if_t *core_if)
                                                                                 GNPTXFSIZ register.
                                                                                +-void dwc_otg_set_gnptxfsiz (dwc_otg_core_if_t *core_if, uint32_t val)
                                                                                +-uint32_t dwc_otg_get_gpvndctl (dwc_otg_core_if_t *core_if)
                                                                                +-void dwc_otg_set_gpvndctl (dwc_otg_core_if_t *core_if, uint32_t val)
                                                                                +-uint32_t dwc_otg_get_ggpio (dwc_otg_core_if_t *core_if)
                                                                                 GGPIO register.
                                                                                +-void dwc_otg_set_ggpio (dwc_otg_core_if_t *core_if, uint32_t val)
                                                                                +-uint32_t dwc_otg_get_hprt0 (dwc_otg_core_if_t *core_if)
                                                                                 HPRT0 register.
                                                                                +-void dwc_otg_set_hprt0 (dwc_otg_core_if_t *core_if, uint32_t val)
                                                                                +-uint32_t dwc_otg_get_guid (dwc_otg_core_if_t *core_if)
                                                                                 GUID register.
                                                                                +-void dwc_otg_set_guid (dwc_otg_core_if_t *core_if, uint32_t val)
                                                                                +-uint32_t dwc_otg_get_hptxfsiz (dwc_otg_core_if_t *core_if)
                                                                                 GHPTXFSIZE.
                                                                                uint16_t dwc_otg_get_otg_version (dwc_otg_core_if_t *core_if)
                                                                                 Returns OTG version - either 1.3 or 2.0.
                                                                                void dwc_otg_pcd_start_srp_timer (dwc_otg_core_if_t *core_if)
                                                                                 Start the SRP timer to detect when the SRP does not complete within 6 seconds.
                                                                                +-void dwc_otg_initiate_srp (dwc_otg_core_if_t *core_if)
                                                                                +-

                                                                                Detailed Description

                                                                                +-The Core Interface Layer provides basic services for accessing and managing the DWC_otg hardware. +-

                                                                                +-These services are used by both the Host Controller Driver and the Peripheral Controller Driver.

                                                                                +-The CIL manages the memory map for the core so that the HCD and PCD don't have to do this separately. It also handles basic tasks like reading/writing the registers and data FIFOs in the controller. Some of the data access functions provide encapsulation of several operations required to perform a task, such as writing multiple registers to start a transfer. Finally, the CIL performs basic services that are not specific to either the host or device modes of operation. These services include management of the OTG Host Negotiation Protocol (HNP) and Session Request Protocol (SRP). A Diagnostic API is also provided to allow testing of the controller hardware.

                                                                                +-The Core Interface Layer has the following requirements:

                                                                                  +-
                                                                                • Provides basic controller operations.
                                                                                • Minimal use of OS services.
                                                                                • The OS services used will be abstracted by using inline functions or macros.
                                                                                +- +-

                                                                                +-Definition in file dwc_otg_cil.c.

                                                                                Define Documentation

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                #define DWC_OTG_PARAM_TEST ( _param_,
                                                                                _low_,
                                                                                _high_   ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Value:

                                                                                (((_param_) < (_low_)) || \
+-                ((_param_) > (_high_)))
+-
                                                                                +-

                                                                                +-Definition at line 5356 of file dwc_otg_cil.c.

                                                                                +-

                                                                                Function Documentation

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                dwc_otg_core_if_t* dwc_otg_cil_init ( const uint32_t *  reg_base_addr  ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This function is called to initialize the DWC_otg CSR data structures. +-

                                                                                +-The register addresses in the device and host structures are initialized from the base address supplied by the caller. The calling function must make the OS calls to get the base address of the DWC_otg controller registers. The core_params argument holds the parameters that specify how the core should be configured.

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +-
                                                                                reg_base_addr Base address of DWC_otg core registers
                                                                                +-
                                                                                +-

                                                                                +-ADP initialization +-

                                                                                +-Definition at line 78 of file dwc_otg_cil.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                void dwc_otg_cil_remove ( dwc_otg_core_if_t *  core_if  ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This function frees the structures allocated by dwc_otg_cil_init(). +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +-
                                                                                core_if The core interface pointer returned from dwc_otg_cil_init().
                                                                                +-
                                                                                +-

                                                                                +-Remove ADP Stuff +-

                                                                                +-Definition at line 285 of file dwc_otg_cil.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                void dwc_otg_enable_global_interrupts ( dwc_otg_core_if_t *  core_if  ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This function enables the controller's Global Interrupt in the AHB Config register. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +-
                                                                                core_if Programming view of DWC_otg controller.
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 322 of file dwc_otg_cil.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                void dwc_otg_disable_global_interrupts ( dwc_otg_core_if_t *  core_if  ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This function disables the controller's Global Interrupt in the AHB Config register. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +-
                                                                                core_if Programming view of DWC_otg controller.
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 335 of file dwc_otg_cil.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                void dwc_otg_enable_common_interrupts ( dwc_otg_core_if_t *  core_if  )  [static]
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This function initializes the commmon interrupts, used in both device and host modes. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +-
                                                                                core_if Programming view of the DWC_otg controller
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 349 of file dwc_otg_cil.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                uint32_t calc_num_in_eps ( dwc_otg_core_if_t *  core_if  )  [static]
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This function calculates the number of IN EPS using GHWCFG1 and GHWCFG2 registers values. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +-
                                                                                core_if Programming view of the DWC_otg controller
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 1147 of file dwc_otg_cil.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                uint32_t calc_num_out_eps ( dwc_otg_core_if_t *  core_if  )  [static]
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This function calculates the number of OUT EPS using GHWCFG1 and GHWCFG2 registers values. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +-
                                                                                core_if Programming view of the DWC_otg controller
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 1176 of file dwc_otg_cil.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                void dwc_otg_core_init ( dwc_otg_core_if_t *  core_if  ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This function initializes the DWC_otg controller registers and prepares the core for device mode or host mode operation. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +-
                                                                                core_if Programming view of the DWC_otg controller
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 1199 of file dwc_otg_cil.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                void dwc_otg_enable_device_interrupts ( dwc_otg_core_if_t *  core_if  ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This function enables the Device mode interrupts. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +-
                                                                                core_if Programming view of DWC_otg controller
                                                                                +-
                                                                                +-

                                                                                +-

                                                                                Todo:
                                                                                NGS: Should this be a module parameter?
                                                                                +- +-

                                                                                +-Definition at line 1526 of file dwc_otg_cil.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                void dwc_otg_core_dev_init ( dwc_otg_core_if_t *  core_if  ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This function initializes the DWC_otg controller registers for device mode. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +-
                                                                                core_if Programming view of DWC_otg controller
                                                                                +-
                                                                                +-

                                                                                +-Set Periodic Tx FIFO Mask all bits 0

                                                                                +-Set Tx FIFO Mask all bits 0

                                                                                +-

                                                                                Todo:
                                                                                NGS: Fix Periodic FIFO Sizing!

                                                                                +-Finish debug of this

                                                                                +-- if the condition needed to be checked or in any case all pending interrutps should be cleared?

                                                                                +- +-

                                                                                +-Definition at line 1620 of file dwc_otg_cil.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                void dwc_otg_enable_host_interrupts ( dwc_otg_core_if_t *  core_if  ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This function enables the Host mode interrupts. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +-
                                                                                core_if Programming view of DWC_otg controller
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 1955 of file dwc_otg_cil.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                void dwc_otg_disable_host_interrupts ( dwc_otg_core_if_t *  core_if  ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This function disables the Host Mode interrupts. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +-
                                                                                core_if Programming view of DWC_otg controller
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 1988 of file dwc_otg_cil.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                void dwc_otg_core_host_init ( dwc_otg_core_if_t *  core_if  ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This function initializes the DWC_otg controller registers for host mode. +-

                                                                                +-This function flushes the Tx and Rx FIFOs and it flushes any entries in the request queues. Host channels are reset to ensure that they are ready for performing transfers.

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +-
                                                                                core_if Programming view of DWC_otg controller
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 2019 of file dwc_otg_cil.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                void dwc_otg_hc_init ( dwc_otg_core_if_t *  core_if,
                                                                                dwc_hc_t *  hc
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Prepares a host channel for transferring packets to/from a specific endpoint. +-

                                                                                +-The HCCHARn register is set up with the characteristics specified in _hc. Host channel interrupts that may need to be serviced while this transfer is in progress are enabled.

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +-
                                                                                core_if Programming view of DWC_otg controller
                                                                                hc Information needed to initialize the host channel
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 2206 of file dwc_otg_cil.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                void dwc_otg_hc_halt ( dwc_otg_core_if_t *  core_if,
                                                                                dwc_hc_t *  hc,
                                                                                dwc_otg_halt_status_e  halt_status
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Attempts to halt a host channel. +-

                                                                                +-This function should only be called in Slave mode or to abort a transfer in either Slave mode or DMA mode. Under normal circumstances in DMA mode, the controller halts the channel when the transfer is complete or a condition occurs that requires application intervention.

                                                                                +-In slave mode, checks for a free request queue entry, then sets the Channel Enable and Channel Disable bits of the Host Channel Characteristics register of the specified channel to intiate the halt. If there is no free request queue entry, sets only the Channel Disable bit of the HCCHARn register to flush requests for this channel. In the latter case, sets a flag to indicate that the host channel needs to be halted when a request queue slot is open.

                                                                                +-In DMA mode, always sets the Channel Enable and Channel Disable bits of the HCCHARn register. The controller ensures there is space in the request queue before submitting the halt request.

                                                                                +-Some time may elapse before the core flushes any posted requests for this host channel and halts. The Channel Halted interrupt handler completes the deactivation of the host channel.

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +- +-
                                                                                core_if Controller register interface.
                                                                                hc Host channel to halt.
                                                                                halt_status Reason for halting the channel.
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 2394 of file dwc_otg_cil.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                void dwc_otg_hc_cleanup ( dwc_otg_core_if_t *  core_if,
                                                                                dwc_hc_t *  hc
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Clears the transfer state for a host channel. +-

                                                                                +-This function is normally called after a transfer is done and the host channel is being released.

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +-
                                                                                core_if Programming view of DWC_otg controller.
                                                                                hc Identifies the host channel to clean up.
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 2521 of file dwc_otg_cil.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                void hc_set_even_odd_frame ( dwc_otg_core_if_t *  core_if,
                                                                                dwc_hc_t *  hc,
                                                                                hcchar_data_t *  hcchar
                                                                                )  [inline, static]
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Sets the channel property that indicates in which frame a periodic transfer should occur. +-

                                                                                +-This is always set to the _next_ frame. This function has no effect on non-periodic transfers.

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +- +-
                                                                                core_if Programming view of DWC_otg controller.
                                                                                hc Identifies the host channel to set up and its properties.
                                                                                hcchar Current value of the HCCHAR register for the specified host channel.
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 2549 of file dwc_otg_cil.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                void dwc_otg_hc_start_transfer ( dwc_otg_core_if_t *  core_if,
                                                                                dwc_hc_t *  hc
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This function does the setup for a data transfer for a host channel and starts the transfer. +-

                                                                                +-May be called in either Slave mode or DMA mode. In Slave mode, the caller must ensure that there is sufficient space in the request queue and Tx Data FIFO.

                                                                                +-For an OUT transfer in Slave mode, it loads a data packet into the appropriate FIFO. If necessary, additional data packets will be loaded in the Host ISR.

                                                                                +-For an IN transfer in Slave mode, a data packet is requested. The data packets are unloaded from the Rx FIFO in the Host ISR. If necessary, additional data packets are requested in the Host ISR.

                                                                                +-For a PING transfer in Slave mode, the Do Ping bit is set in the HCTSIZ register along with a packet count of 1 and the channel is enabled. This causes a single PING transaction to occur. Other fields in HCTSIZ are simply set to 0 since no data transfer occurs in this case.

                                                                                +-For a PING transfer in DMA mode, the HCTSIZ register is initialized with all the information required to perform the subsequent data transfer. In addition, the Do Ping bit is set in the HCTSIZ register. In this case, the controller performs the entire PING protocol, then starts the data transfer.

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +-
                                                                                core_if Programming view of DWC_otg controller.
                                                                                hc Information needed to initialize the host channel. The xfer_len value may be reduced to accommodate the max widths of the XferSize and PktCnt fields in the HCTSIZn register. The multi_count value may be changed to reflect the final xfer_len value.
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 2703 of file dwc_otg_cil.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                void dwc_otg_hc_start_transfer_ddma ( dwc_otg_core_if_t *  core_if,
                                                                                dwc_hc_t *  hc
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This function does the setup for a data transfer for a host channel and starts the transfer in Descriptor DMA mode. +-

                                                                                +-Initializes HCTSIZ register. For a PING transfer the Do Ping bit is set. Sets PID and NTD values. For periodic transfers initializes SCHED_INFO field with micro-frame bitmap.

                                                                                +-Initializes HCDMA register with descriptor list address and CTD value then starts the transfer via enabling the channel.

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +-
                                                                                core_if Programming view of DWC_otg controller.
                                                                                hc Information needed to initialize the host channel.
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 2872 of file dwc_otg_cil.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                int dwc_otg_hc_continue_transfer ( dwc_otg_core_if_t *  core_if,
                                                                                dwc_hc_t *  hc
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This function continues a data transfer that was started by previous call to dwc_otg_hc_start_transfer. +-

                                                                                +-The caller must ensure there is sufficient space in the request queue and Tx Data FIFO. This function should only be called in Slave mode. In DMA mode, the controller acts autonomously to complete transfers programmed to a host channel.

                                                                                +-For an OUT transfer, a new data packet is loaded into the appropriate FIFO if there is any data remaining to be queued. For an IN transfer, another data packet is always requested. For the SETUP phase of a control transfer, this function does nothing.

                                                                                +-

                                                                                Returns:
                                                                                1 if a new request is queued, 0 if no more requests are required for this transfer.
                                                                                +- +-

                                                                                +-Definition at line 2952 of file dwc_otg_cil.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                void dwc_otg_hc_do_ping ( dwc_otg_core_if_t *  core_if,
                                                                                dwc_hc_t *  hc
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Starts a PING transfer. +-

                                                                                +-This function should only be called in Slave mode. The Do Ping bit is set in the HCTSIZ register, then the channel is enabled. +-

                                                                                +-Definition at line 3014 of file dwc_otg_cil.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                uint32_t dwc_otg_get_frame_number ( dwc_otg_core_if_t *  core_if  ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Gets the current USB frame number. +-

                                                                                +-This is the frame number from the last SOF packet. +-

                                                                                +-Definition at line 3086 of file dwc_otg_cil.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                void dwc_otg_read_setup_packet ( dwc_otg_core_if_t *  core_if,
                                                                                uint32_t *  dest
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This function reads a setup packet from the Rx FIFO into the destination buffer. +-

                                                                                +-This function is called from the Rx Status Queue Level (RxStsQLvl) Interrupt routine when a SETUP packet has been received in Slave mode.

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +-
                                                                                core_if Programming view of DWC_otg controller.
                                                                                dest Destination buffer for packet data.
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 3144 of file dwc_otg_cil.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                void dwc_otg_ep0_activate ( dwc_otg_core_if_t *  core_if,
                                                                                dwc_ep_t *  ep
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This function enables EP0 OUT to receive SETUP packets and configures EP0 IN for transmitting packets. +-

                                                                                +-It is normally called when the "Enumeration Done" interrupt occurs.

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +-
                                                                                core_if Programming view of DWC_otg controller.
                                                                                ep The EP0 data.
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 3161 of file dwc_otg_cil.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                void dwc_otg_ep_activate ( dwc_otg_core_if_t *  core_if,
                                                                                dwc_ep_t *  ep
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This function activates an EP. +-

                                                                                +-The Device EP control register for the EP is configured as defined in the ep structure. Note: This function is not used for EP0.

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +-
                                                                                core_if Programming view of DWC_otg controller.
                                                                                ep The EP to activate.
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 3214 of file dwc_otg_cil.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                void dwc_otg_ep_deactivate ( dwc_otg_core_if_t *  core_if,
                                                                                dwc_ep_t *  ep
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This function deactivates an EP. +-

                                                                                +-This is done by clearing the USB Active EP bit in the Device EP control register. Note: This function is not used for EP0. EP0 cannot be deactivated.

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +-
                                                                                core_if Programming view of DWC_otg controller.
                                                                                ep The EP to deactivate.
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 3369 of file dwc_otg_cil.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                void init_dma_desc_chain ( dwc_otg_core_if_t *  core_if,
                                                                                dwc_ep_t *  ep
                                                                                )  [static]
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This function initializes dma descriptor chain. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +-
                                                                                core_if Programming view of DWC_otg controller.
                                                                                ep The EP to start the transfer on.
                                                                                +-
                                                                                +-

                                                                                +-DMA Descriptor Setup +-

                                                                                +-Definition at line 3515 of file dwc_otg_cil.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                void dwc_otg_ep_start_transfer ( dwc_otg_core_if_t *  core_if,
                                                                                dwc_ep_t *  ep
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This function does the setup for a data transfer for an EP and starts the transfer. +-

                                                                                +-For an IN transfer, the packets will be loaded into the appropriate Tx FIFO in the ISR. For OUT transfers, the packets are unloaded from the Rx FIFO in the ISR. the ISR.

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +-
                                                                                core_if Programming view of DWC_otg controller.
                                                                                ep The EP to start the transfer on.
                                                                                +-
                                                                                +-

                                                                                +-DIEPDMAn Register write

                                                                                +-Enable the Non-Periodic Tx FIFO empty interrupt, or the Tx FIFO epmty interrupt in dedicated Tx FIFO mode, the data will be written into the fifo by the ISR.

                                                                                +-This is used for interrupt out transfers

                                                                                +-DOEPDMAn Register write +-

                                                                                +-Definition at line 3655 of file dwc_otg_cil.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                void dwc_otg_ep_start_zl_transfer ( dwc_otg_core_if_t *  core_if,
                                                                                dwc_ep_t *  ep
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This function setup a zero length transfer in Buffer DMA and Slave modes for usb requests with zero field set. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +-
                                                                                core_if Programming view of DWC_otg controller.
                                                                                ep The EP to start the transfer on.
                                                                                +-
                                                                                +-

                                                                                +-Enable the Non-Periodic Tx FIFO empty interrupt, or the Tx FIFO epmty interrupt in dedicated Tx FIFO mode, the data will be written into the fifo by the ISR. +-

                                                                                +-Definition at line 3948 of file dwc_otg_cil.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                void dwc_otg_ep0_start_transfer ( dwc_otg_core_if_t *  core_if,
                                                                                dwc_ep_t *  ep
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This function does the setup for a data transfer for EP0 and starts the transfer. +-

                                                                                +-For an IN transfer, the packets will be loaded into the appropriate Tx FIFO in the ISR. For OUT transfers, the packets are unloaded from the Rx FIFO in the ISR.

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +-
                                                                                core_if Programming view of DWC_otg controller.
                                                                                ep The EP0 data.
                                                                                +-
                                                                                +-

                                                                                +-DMA Descriptor Setup

                                                                                +-DIEPDMA0 Register write

                                                                                +-Enable the Non-Periodic Tx FIFO empty interrupt, the data will be written into the fifo by the ISR.

                                                                                +-DMA Descriptor Setup

                                                                                +-DOEPDMA0 Register write +-

                                                                                +-Definition at line 4051 of file dwc_otg_cil.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                void dwc_otg_ep0_continue_transfer ( dwc_otg_core_if_t *  core_if,
                                                                                dwc_ep_t *  ep
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This function continues control IN transfers started by dwc_otg_ep0_start_transfer, when the transfer does not fit in a single packet. +-

                                                                                +-NOTE: The DIEPCTL0/DOEPCTL0 registers only have one bit for the packet count.

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +-
                                                                                core_if Programming view of DWC_otg controller.
                                                                                ep The EP0 data.
                                                                                +-
                                                                                +-

                                                                                +-

                                                                                Todo:
                                                                                Should there be check for room in the Tx Status Queue. If not remove the code above this comment.
                                                                                +-

                                                                                +-DMA Descriptor Setup

                                                                                +-DIEPDMA0 Register write

                                                                                +-Enable the Non-Periodic Tx FIFO empty interrupt, the data will be written into the fifo by the ISR.

                                                                                +-DMA Descriptor Setup

                                                                                +-DOEPDMA0 Register write +-

                                                                                +-Definition at line 4239 of file dwc_otg_cil.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                void dwc_otg_ep_write_packet ( dwc_otg_core_if_t *  core_if,
                                                                                dwc_ep_t *  ep,
                                                                                int  dma
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This function writes a packet into the Tx FIFO associated with the EP. +-

                                                                                +-For non-periodic EPs the non-periodic Tx FIFO is written. For periodic EPs the periodic Tx FIFO associated with the EP is written with all packets for the next micro-frame.

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +- +-
                                                                                core_if Programming view of DWC_otg controller.
                                                                                ep The EP to write packet for.
                                                                                dma Indicates if DMA is being used.
                                                                                +-
                                                                                +-

                                                                                +-The buffer is padded to DWORD on a per packet basis in slave/dma mode if the MPS is not DWORD aligned. The last packet, if short, is also padded to a multiple of DWORD.

                                                                                +-ep->xfer_buff always starts DWORD aligned in memory and is a multiple of DWORD in length

                                                                                +-ep->xfer_len can be any number of bytes

                                                                                +-ep->xfer_count is a multiple of ep->maxpacket until the last packet

                                                                                +-FIFO access is DWORD

                                                                                +-

                                                                                Todo:
                                                                                NGS Where are the Periodic Tx FIFO addresses intialized? What should this be?
                                                                                +- +-

                                                                                +-Definition at line 4438 of file dwc_otg_cil.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                void dwc_otg_ep_set_stall ( dwc_otg_core_if_t *  core_if,
                                                                                dwc_ep_t *  ep
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Set the EP STALL. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +-
                                                                                core_if Programming view of DWC_otg controller.
                                                                                ep The EP to set the stall on.
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 4509 of file dwc_otg_cil.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                void dwc_otg_ep_clear_stall ( dwc_otg_core_if_t *  core_if,
                                                                                dwc_ep_t *  ep
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Clear the EP STALL. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +-
                                                                                core_if Programming view of DWC_otg controller.
                                                                                ep The EP to clear stall from.
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 4547 of file dwc_otg_cil.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                void dwc_otg_read_packet ( dwc_otg_core_if_t *  core_if,
                                                                                uint8_t *  dest,
                                                                                uint16_t  bytes
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This function reads a packet from the Rx FIFO into the destination buffer. +-

                                                                                +-To read SETUP data use dwc_otg_read_setup_packet.

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +- +-
                                                                                core_if Programming view of DWC_otg controller.
                                                                                dest Destination buffer for the packet.
                                                                                bytes Number of bytes to copy to the destination.
                                                                                +-
                                                                                +-

                                                                                +-

                                                                                Todo:
                                                                                Account for the case where _dest is not dword aligned. This requires reading data from the FIFO into a uint32_t temp buffer, then moving it into the data buffer.
                                                                                +- +-

                                                                                +-Definition at line 4590 of file dwc_otg_cil.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                void dwc_otg_dump_dev_registers ( dwc_otg_core_if_t *  core_if  ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Dump core registers and SPRAM. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +-
                                                                                core_if Programming view of DWC_otg controller.
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 4620 of file dwc_otg_cil.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                void dwc_otg_dump_spram ( dwc_otg_core_if_t *  core_if  ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This functions reads the SPRAM and prints its content. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +-
                                                                                core_if Programming view of DWC_otg controller.
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 4756 of file dwc_otg_cil.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                void dwc_otg_dump_host_registers ( dwc_otg_core_if_t *  core_if  ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This function reads the host registers and prints them. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +-
                                                                                core_if Programming view of DWC_otg controller.
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 4784 of file dwc_otg_cil.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                void dwc_otg_dump_global_registers ( dwc_otg_core_if_t *  core_if  ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This function reads the core global registers and prints them. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +-
                                                                                core_if Programming view of DWC_otg controller.
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 4853 of file dwc_otg_cil.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                void dwc_otg_flush_tx_fifo ( dwc_otg_core_if_t *  core_if,
                                                                                const int  num
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Flush a Tx FIFO. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +-
                                                                                core_if Programming view of DWC_otg controller.
                                                                                num Tx FIFO to flush.
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 4959 of file dwc_otg_cil.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                void dwc_otg_flush_rx_fifo ( dwc_otg_core_if_t *  core_if  ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Flush Rx FIFO. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +-
                                                                                core_if Programming view of DWC_otg controller.
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 4991 of file dwc_otg_cil.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                void dwc_otg_core_reset ( dwc_otg_core_if_t *  core_if  ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Do core a soft reset of the core. +-

                                                                                +-Be careful with this because it resets all the internal state machines of the core. +-

                                                                                +-Definition at line 5022 of file dwc_otg_cil.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                void dwc_otg_cil_register_hcd_callbacks ( dwc_otg_core_if_t *  core_if,
                                                                                dwc_otg_cil_callbacks_t *  cb,
                                                                                void *  p
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Register HCD callbacks. +-

                                                                                +-The callbacks are used to start and stop the HCD for interrupt processing.

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +- +-
                                                                                core_if Programming view of DWC_otg controller.
                                                                                cb the HCD callback structure.
                                                                                p pointer to be passed to callback function (usb_hcd*).
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 5078 of file dwc_otg_cil.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                void dwc_otg_cil_register_pcd_callbacks ( dwc_otg_core_if_t *  core_if,
                                                                                dwc_otg_cil_callbacks_t *  cb,
                                                                                void *  p
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Register PCD callbacks. +-

                                                                                +-The callbacks are used to start and stop the PCD for interrupt processing.

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +- +-
                                                                                core_if Programming view of DWC_otg controller.
                                                                                cb the PCD callback structure.
                                                                                p pointer to be passed to callback function (pcd*).
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 5093 of file dwc_otg_cil.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                void write_isoc_frame_data ( dwc_otg_core_if_t *  core_if,
                                                                                dwc_ep_t *  ep
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This function writes isoc data per 1 (micro)frame into tx fifo. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +-
                                                                                core_if Programming view of DWC_otg controller.
                                                                                ep The EP to start the transfer on.
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 5109 of file dwc_otg_cil.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                void dwc_otg_iso_ep_start_frm_transfer ( dwc_otg_core_if_t *  core_if,
                                                                                dwc_ep_t *  ep
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This function initializes a descriptor chain for Isochronous transfer. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +-
                                                                                core_if Programming view of DWC_otg controller.
                                                                                ep The EP to start the transfer on.
                                                                                +-
                                                                                +-

                                                                                +-Enable endpoint, clear nak +-

                                                                                +-Definition at line 5161 of file dwc_otg_cil.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                int dwc_otg_set_param_otg_cap ( dwc_otg_core_if_t *  core_if,
                                                                                int32_t  val
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Specifies the OTG capabilities. +-

                                                                                +-The driver will automatically detect the value for this parameter if none is specified. 0 - HNP and SRP capable (default) 1 - SRP Only capable 2 - No HNP/SRP capable +-

                                                                                +-Definition at line 5361 of file dwc_otg_cil.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                int dwc_otg_set_param_dma_enable ( dwc_otg_core_if_t *  core_if,
                                                                                int32_t  val
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Specifies whether to use slave or DMA mode for accessing the data FIFOs. +-

                                                                                +-The driver will automatically detect the value for this parameter if none is specified. 0 - Slave 1 - DMA (default, if available) +-

                                                                                +-Definition at line 5440 of file dwc_otg_cil.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                int dwc_otg_set_param_dma_desc_enable ( dwc_otg_core_if_t *  core_if,
                                                                                int32_t  val
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-When DMA mode is enabled specifies whether to use address DMA or DMA Descritor mode for accessing the data FIFOs in device mode. +-

                                                                                +-The driver will automatically detect the value for this parameter if none is specified. 0 - address DMA 1 - DMA Descriptor(default, if available) +-

                                                                                +-Definition at line 5470 of file dwc_otg_cil.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                int dwc_otg_set_param_host_support_fs_ls_low_power ( dwc_otg_core_if_t *  core_if,
                                                                                int32_t  val
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Specifies whether low power mode is supported when attached to a Full Speed or Low Speed device in host mode. +-

                                                                                +-0 - Don't support low power mode (default) 1 - Support low power mode +-

                                                                                +-Definition at line 5500 of file dwc_otg_cil.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                int dwc_otg_set_param_data_fifo_size ( dwc_otg_core_if_t *  core_if,
                                                                                int32_t  val
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Total number of 4-byte words in the data FIFO memory. +-

                                                                                +-This memory includes the Rx FIFO, non-periodic Tx FIFO, and periodic Tx FIFOs. 32 to 32768 (default 8192) Note: The total FIFO memory depth in the FPGA configuration is 8192. +-

                                                                                +-Definition at line 5547 of file dwc_otg_cil.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                int dwc_otg_set_param_dev_rx_fifo_size ( dwc_otg_core_if_t *  core_if,
                                                                                int32_t  val
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Number of 4-byte words in the Rx FIFO in device mode when dynamic FIFO sizing is enabled. +-

                                                                                +-16 to 32768 (default 1064) +-

                                                                                +-Definition at line 5576 of file dwc_otg_cil.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                int dwc_otg_set_param_dev_nperio_tx_fifo_size ( dwc_otg_core_if_t *  core_if,
                                                                                int32_t  val
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Number of 4-byte words in the non-periodic Tx FIFO in device mode when dynamic FIFO sizing is enabled. +-

                                                                                +-16 to 32768 (default 1024) +-

                                                                                +-Definition at line 5602 of file dwc_otg_cil.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                int dwc_otg_set_param_host_rx_fifo_size ( dwc_otg_core_if_t *  core_if,
                                                                                int32_t  val
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Number of 4-byte words in the Rx FIFO in host mode when dynamic FIFO sizing is enabled. +-

                                                                                +-16 to 32768 (default 1024) +-

                                                                                +-Definition at line 5635 of file dwc_otg_cil.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                int dwc_otg_set_param_host_nperio_tx_fifo_size ( dwc_otg_core_if_t *  core_if,
                                                                                int32_t  val
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Number of 4-byte words in the non-periodic Tx FIFO in host mode when Dynamic FIFO sizing is enabled in the core. +-

                                                                                +-16 to 32768 (default 1024) +-

                                                                                +-Definition at line 5667 of file dwc_otg_cil.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                int dwc_otg_set_param_host_perio_tx_fifo_size ( dwc_otg_core_if_t *  core_if,
                                                                                int32_t  val
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Number of 4-byte words in the host periodic Tx FIFO when dynamic FIFO sizing is enabled. +-

                                                                                +-16 to 32768 (default 1024) +-

                                                                                +-Definition at line 5700 of file dwc_otg_cil.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                int dwc_otg_set_param_max_transfer_size ( dwc_otg_core_if_t *  core_if,
                                                                                int32_t  val
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-The maximum transfer size supported in bytes. +-

                                                                                +-2047 to 65,535 (default 65,535) +-

                                                                                +-Definition at line 5731 of file dwc_otg_cil.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                int dwc_otg_set_param_max_packet_count ( dwc_otg_core_if_t *  core_if,
                                                                                int32_t  val
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-The maximum number of packets in a transfer. +-

                                                                                +-15 to 511 (default 511) +-

                                                                                +-Definition at line 5764 of file dwc_otg_cil.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                int dwc_otg_set_param_host_channels ( dwc_otg_core_if_t *  core_if,
                                                                                int32_t  val
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-The number of host channel registers to use. +-

                                                                                +-1 to 16 (default 12) Note: The FPGA configuration supports a maximum of 12 host channels. +-

                                                                                +-Definition at line 5795 of file dwc_otg_cil.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                int dwc_otg_set_param_dev_endpoints ( dwc_otg_core_if_t *  core_if,
                                                                                int32_t  val
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-The number of endpoints in addition to EP0 available for device mode operations. +-

                                                                                +-1 to 15 (default 6 IN and OUT) Note: The FPGA configuration supports a maximum of 6 IN and OUT endpoints in addition to EP0. +-

                                                                                +-Definition at line 5825 of file dwc_otg_cil.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                int dwc_otg_set_param_phy_type ( dwc_otg_core_if_t *  core_if,
                                                                                int32_t  val
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Specifies the type of PHY interface to use. +-

                                                                                +-By default, the driver will automatically detect the phy_type.

                                                                                +-0 - Full Speed PHY 1 - UTMI+ (default) 2 - ULPI +-

                                                                                +-Definition at line 5855 of file dwc_otg_cil.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                int dwc_otg_set_param_speed ( dwc_otg_core_if_t *  core_if,
                                                                                int32_t  val
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Specifies the maximum speed of operation in host and device mode. +-

                                                                                +-The actual speed depends on the speed of the attached device and the value of phy_type. The actual speed depends on the speed of the attached device. 0 - High Speed (default) 1 - Full Speed +-

                                                                                +-Definition at line 5904 of file dwc_otg_cil.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                int dwc_otg_set_param_host_ls_low_power_phy_clk ( dwc_otg_core_if_t *  core_if,
                                                                                int32_t  val
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Specifies the PHY clock rate in low power mode when connected to a Low Speed device in host mode. +-

                                                                                +-This parameter is applicable only if HOST_SUPPORT_FS_LS_LOW_POWER is enabled. If PHY_TYPE is set to FS then defaults to 6 MHZ otherwise 48 MHZ.

                                                                                +-0 - 48 MHz 1 - 6 MHz +-

                                                                                +-Definition at line 5933 of file dwc_otg_cil.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                int dwc_otg_set_param_phy_ulpi_ddr ( dwc_otg_core_if_t *  core_if,
                                                                                int32_t  val
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Specifies whether the ULPI operates at double or single data rate. +-

                                                                                +-This parameter is only applicable if PHY_TYPE is ULPI.

                                                                                +-0 - single data rate ULPI interface with 8 bit wide data bus (default) 1 - double data rate ULPI interface with 4 bit wide data bus +-

                                                                                +-Definition at line 5970 of file dwc_otg_cil.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                int dwc_otg_set_param_phy_utmi_width ( dwc_otg_core_if_t *  core_if,
                                                                                int32_t  val
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Specifies the UTMI+ Data Width. +-

                                                                                +-This parameter is applicable for a PHY_TYPE of UTMI+ or ULPI. (For a ULPI PHY_TYPE, this parameter indicates the data width between the MAC and the ULPI Wrapper.) Also, this parameter is applicable only if the OTG_HSPHY_WIDTH cC parameter was set to "8 and 16 bits", meaning that the core has been configured to work at either data path width.

                                                                                +-8 or 16 bits (default 16) +-

                                                                                +-Definition at line 6005 of file dwc_otg_cil.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                int dwc_otg_set_param_i2c_enable ( dwc_otg_core_if_t *  core_if,
                                                                                int32_t  val
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Specifies whether to use the I2Cinterface for full speed PHY. +-

                                                                                +-This parameter is only applicable if PHY_TYPE is FS. 0 - No (default) 1 - Yes +-

                                                                                +-Definition at line 6056 of file dwc_otg_cil.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                int dwc_otg_set_param_dev_perio_tx_fifo_size ( dwc_otg_core_if_t *  core_if,
                                                                                int32_t  val,
                                                                                int  fifo_num
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Number of 4-byte words in each of the periodic Tx FIFOs in device mode when dynamic FIFO sizing is enabled. +-

                                                                                +-4 to 768 (default 256) +-

                                                                                +-Definition at line 6085 of file dwc_otg_cil.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                int dwc_otg_set_param_dma_burst_size ( dwc_otg_core_if_t *  core_if,
                                                                                int32_t  val
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-The DMA Burst size (applicable only for External DMA Mode). +-

                                                                                +-1, 4, 8 16, 32, 64, 128, 256 (default 32) +-

                                                                                +-Definition at line 6275 of file dwc_otg_cil.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                uint32_t dwc_otg_get_mode ( dwc_otg_core_if_t *  core_if  ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Get current mode. +-

                                                                                +-Returns 0 if in device mode, and 1 if in host mode. +-

                                                                                +-Definition at line 6653 of file dwc_otg_cil.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                uint16_t dwc_otg_get_otg_version ( dwc_otg_core_if_t *  core_if  ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Returns OTG version - either 1.3 or 2.0. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +-
                                                                                core_if The core_if structure pointer
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 7012 of file dwc_otg_cil.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                void dwc_otg_pcd_start_srp_timer ( dwc_otg_core_if_t *  core_if  ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Start the SRP timer to detect when the SRP does not complete within 6 seconds. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +-
                                                                                core_if the pointer to core_if strucure.
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 7023 of file dwc_otg_cil.c.

                                                                                +-

                                                                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__cil_8h-source.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/dwc__otg__cil_8h-source.html 2013-07-26 19:34:40.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,908 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_cil.h Source File +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                dwc_otg_cil.h

                                                                                Go to the documentation of this file.
                                                                                00001 /* ==========================================================================
+-00002  * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_cil.h $
+-00003  * $Revision: #122 $
+-00004  * $Date: 2011/10/24 $
+-00005  * $Change: 1871160 $
+-00006  *
+-00007  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
+-00008  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
+-00009  * otherwise expressly agreed to in writing between Synopsys and you.
+-00010  *
+-00011  * The Software IS NOT an item of Licensed Software or Licensed Product under
+-00012  * any End User Software License Agreement or Agreement for Licensed Product
+-00013  * with Synopsys or any supplement thereto. You are permitted to use and
+-00014  * redistribute this Software in source and binary forms, with or without
+-00015  * modification, provided that redistributions of source code must retain this
+-00016  * notice. You may not view, use, disclose, copy or distribute this file or
+-00017  * any information contained herein except pursuant to this license grant from
+-00018  * Synopsys. If you do not agree with this notice, including the disclaimer
+-00019  * below, then you are not authorized to use the Software.
+-00020  *
+-00021  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
+-00022  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+-00023  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+-00024  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
+-00025  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+-00026  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+-00027  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+-00028  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+-00029  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+-00030  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+-00031  * DAMAGE.
+-00032  * ========================================================================== */
+-00033 
+-00034 #if !defined(__DWC_CIL_H__)
+-00035 #define __DWC_CIL_H__
+-00036 
+-00037 #include "dwc_list.h"
+-00038 #include "dwc_otg_dbg.h"
+-00039 #include "dwc_otg_regs.h"
+-00040 
+-00041 #include "dwc_otg_core_if.h"
+-00042 #include "dwc_otg_adp.h"
+-00043 
+-00049 #ifdef DWC_UTE_CFI
+-00050 
+-00051 #define MAX_DMA_DESCS_PER_EP    256
+-00052 
+-00056 typedef enum _data_buffer_mode {
+-00057         BM_STANDARD = 0,        /* data buffer is in normal mode */
+-00058         BM_SG = 1,              /* data buffer uses the scatter/gather mode */
+-00059         BM_CONCAT = 2,          /* data buffer uses the concatenation mode */
+-00060         BM_CIRCULAR = 3,        /* data buffer uses the circular DMA mode */
+-00061         BM_ALIGN = 4            /* data buffer is in buffer alignment mode */
+-00062 } data_buffer_mode_e;
+-00063 #endif //DWC_UTE_CFI
+-00064 
+-00067 #define OTG_CORE_REV_2_60a      0x4F54260A
+-00068 #define OTG_CORE_REV_2_71a      0x4F54271A
+-00069 #define OTG_CORE_REV_2_72a      0x4F54272A
+-00070 #define OTG_CORE_REV_2_80a      0x4F54280A
+-00071 #define OTG_CORE_REV_2_81a      0x4F54281A
+-00072 #define OTG_CORE_REV_2_90a      0x4F54290A
+-00073 #define OTG_CORE_REV_2_91a      0x4F54291A
+-00074 #define OTG_CORE_REV_2_92a      0x4F54292A
+-00075 #define OTG_CORE_REV_2_93a      0x4F54293A
+-00076 #define OTG_CORE_REV_2_94a      0x4F54294A
+-00077 
+-00081 typedef struct iso_pkt_info {
+-00082         uint32_t offset;
+-00083         uint32_t length;
+-00084         int32_t status;
+-00085 } iso_pkt_info_t;
+-00086 
+-00092 typedef struct dwc_ep {
+-00094         uint8_t num;
+-00096         unsigned is_in:1;
+-00098         unsigned active:1;
+-00099 
+-00103         unsigned tx_fifo_num:4;
+-00105         unsigned type:2;
+-00106 #define DWC_OTG_EP_TYPE_CONTROL    0
+-00107 #define DWC_OTG_EP_TYPE_ISOC       1
+-00108 #define DWC_OTG_EP_TYPE_BULK       2
+-00109 #define DWC_OTG_EP_TYPE_INTR       3
+-00110 
+-00112         unsigned data_pid_start:1;
+-00114         unsigned even_odd_frame:1;
+-00116         unsigned maxpacket:11;
+-00117 
+-00119         uint32_t maxxfer;
+-00120 
+-00129         dwc_dma_t dma_addr;
+-00130 
+-00131         dwc_dma_t dma_desc_addr;
+-00132         dwc_otg_dev_dma_desc_t *desc_addr;
+-00133 
+-00134         uint8_t *start_xfer_buff;
+-00136         uint8_t *xfer_buff;
+-00138         unsigned xfer_len:19;
+-00140         unsigned xfer_count:19;
+-00142         unsigned sent_zlp:1;
+-00144         unsigned total_len:19;
+-00145 
+-00147         unsigned stall_clear_flag:1;
+-00148 
+-00149 #ifdef DWC_UTE_CFI
+-00150         /* The buffer mode */
+-00151         data_buffer_mode_e buff_mode;
+-00152 
+-00153         /* The chain of DMA descriptors.
+-00154          * MAX_DMA_DESCS_PER_EP will be allocated for each active EP.
+-00155          */
+-00156         dwc_otg_dma_desc_t *descs;
+-00157 
+-00158         /* The DMA address of the descriptors chain start */
+-00159         dma_addr_t descs_dma_addr;
+-00161         uint32_t cfi_req_len;
+-00162 #endif                          //DWC_UTE_CFI
+-00163 
+-00165 #define MAX_DMA_DESC_CNT 256
+-00166 
+-00167         uint32_t desc_cnt;
+-00168         
+-00170         uint32_t bInterval;
+-00172         uint32_t frame_num;
+-00174         uint8_t frm_overrun;
+-00175 
+-00176 #ifdef DWC_UTE_PER_IO
+-00177 
+-00178         uint32_t xiso_frame_num;
+-00180         uint32_t xiso_bInterval;
+-00182         int xiso_active_xfers;
+-00183         int xiso_queued_xfers;
+-00184 #endif
+-00185 #ifdef DWC_EN_ISOC
+-00186 
+-00191         dwc_dma_t dma_addr0;
+-00192         dwc_dma_t dma_addr1;
+-00193 
+-00194         dwc_dma_t iso_dma_desc_addr;
+-00195         dwc_otg_dev_dma_desc_t *iso_desc_addr;
+-00196 
+-00198         uint8_t *xfer_buff0;
+-00199         uint8_t *xfer_buff1;
+-00200 
+-00202         uint32_t proc_buf_num;
+-00204         uint32_t buf_proc_intrvl;
+-00206         uint32_t data_per_frame;
+-00207 
+-00208         /* todo - pattern data support is to be implemented in the future */
+-00210         uint32_t data_pattern_frame;
+-00212         uint32_t sync_frame;
+-00213 
+-00215         uint32_t bInterval;
+-00217         uint32_t pkt_per_frm;
+-00219         uint32_t next_frame;
+-00221         uint32_t pkt_cnt;
+-00223         iso_pkt_info_t *pkt_info;
+-00225         uint32_t cur_pkt;
+-00227         uint8_t *cur_pkt_addr;
+-00229         uint32_t cur_pkt_dma_addr;
+-00230 #endif                          /* DWC_EN_ISOC */
+-00231 
+-00233 } dwc_ep_t;
+-00234 
+-00235 /*
+-00236  * Reasons for halting a host channel.
+-00237  */
+-00238 typedef enum dwc_otg_halt_status {
+-00239         DWC_OTG_HC_XFER_NO_HALT_STATUS,
+-00240         DWC_OTG_HC_XFER_COMPLETE,
+-00241         DWC_OTG_HC_XFER_URB_COMPLETE,
+-00242         DWC_OTG_HC_XFER_ACK,
+-00243         DWC_OTG_HC_XFER_NAK,
+-00244         DWC_OTG_HC_XFER_NYET,
+-00245         DWC_OTG_HC_XFER_STALL,
+-00246         DWC_OTG_HC_XFER_XACT_ERR,
+-00247         DWC_OTG_HC_XFER_FRAME_OVERRUN,
+-00248         DWC_OTG_HC_XFER_BABBLE_ERR,
+-00249         DWC_OTG_HC_XFER_DATA_TOGGLE_ERR,
+-00250         DWC_OTG_HC_XFER_AHB_ERR,
+-00251         DWC_OTG_HC_XFER_PERIODIC_INCOMPLETE,
+-00252         DWC_OTG_HC_XFER_URB_DEQUEUE
+-00253 } dwc_otg_halt_status_e;
+-00254 
+-00260 typedef struct dwc_hc {
+-00262         uint8_t hc_num;
+-00263 
+-00265         unsigned dev_addr:7;
+-00266 
+-00268         unsigned ep_num:4;
+-00269 
+-00271         unsigned ep_is_in:1;
+-00272 
+-00280         unsigned speed:2;
+-00281 #define DWC_OTG_EP_SPEED_LOW    0
+-00282 #define DWC_OTG_EP_SPEED_FULL   1
+-00283 #define DWC_OTG_EP_SPEED_HIGH   2
+-00284 
+-00293         unsigned ep_type:2;
+-00294 
+-00296         unsigned max_packet:11;
+-00297 
+-00306         unsigned data_pid_start:2;
+-00307 #define DWC_OTG_HC_PID_DATA0 0
+-00308 #define DWC_OTG_HC_PID_DATA2 1
+-00309 #define DWC_OTG_HC_PID_DATA1 2
+-00310 #define DWC_OTG_HC_PID_MDATA 3
+-00311 #define DWC_OTG_HC_PID_SETUP 3
+-00312 
+-00314         unsigned multi_count:2;
+-00315 
+-00320         uint8_t *xfer_buff;
+-00325         dwc_dma_t align_buff;
+-00327         uint32_t xfer_len;
+-00329         uint32_t xfer_count;
+-00331         uint16_t start_pkt_count;
+-00332 
+-00337         uint8_t xfer_started;
+-00338 
+-00343         uint8_t do_ping;
+-00344 
+-00349         uint8_t error_state;
+-00350 
+-00357         uint8_t halt_on_queue;
+-00358 
+-00363         uint8_t halt_pending;
+-00364 
+-00368         dwc_otg_halt_status_e halt_status;
+-00369 
+-00370         /*
+-00371          * Split settings for the host channel
+-00372          */
+-00373         uint8_t do_split;                  
+-00374         uint8_t complete_split;    
+-00375         uint8_t hub_addr;                  
+-00377         uint8_t port_addr;                 
+-00384         uint8_t xact_pos;
+-00385 
+-00387         uint8_t short_read;
+-00388 
+-00393         uint8_t requests;
+-00394 
+-00398         struct dwc_otg_qh *qh;
+-00399 
+-00403          DWC_CIRCLEQ_ENTRY(dwc_hc) hc_list_entry;
+-00404 
+-00409         uint16_t ntd;
+-00410 
+-00412         dwc_dma_t desc_list_addr;
+-00413 
+-00415         uint8_t schinfo;
+-00416 
+-00418 } dwc_hc_t;
+-00419 
+-00424 typedef struct dwc_otg_core_params {
+-00425         int32_t opt;
+-00426 
+-00434         int32_t otg_cap;
+-00435 
+-00443         int32_t dma_enable;
+-00444 
+-00452         int32_t dma_desc_enable;
+-00456         int32_t dma_burst_size; /* Translate this to GAHBCFG values */
+-00457 
+-00466         int32_t speed;
+-00472         int32_t host_support_fs_ls_low_power;
+-00473 
+-00482         int32_t host_ls_low_power_phy_clk;
+-00483 
+-00488         int32_t enable_dynamic_fifo;
+-00489 
+-00496         int32_t data_fifo_size;
+-00497 
+-00502         int32_t dev_rx_fifo_size;
+-00503 
+-00508         int32_t dev_nperio_tx_fifo_size;
+-00509 
+-00514         uint32_t dev_perio_tx_fifo_size[MAX_PERIO_FIFOS];
+-00515 
+-00520         int32_t host_rx_fifo_size;
+-00521 
+-00526         int32_t host_nperio_tx_fifo_size;
+-00527 
+-00532         int32_t host_perio_tx_fifo_size;
+-00533 
+-00537         int32_t max_transfer_size;
+-00538 
+-00542         int32_t max_packet_count;
+-00543 
+-00548         int32_t host_channels;
+-00549 
+-00556         int32_t dev_endpoints;
+-00557 
+-00566         int32_t phy_type;
+-00567 
+-00579         int32_t phy_utmi_width;
+-00580 
+-00591         int32_t phy_ulpi_ddr;
+-00592 
+-00597         int32_t phy_ulpi_ext_vbus;
+-00598 
+-00605         int32_t i2c_enable;
+-00606 
+-00607         int32_t ulpi_fs_ls;
+-00608 
+-00609         int32_t ts_dline;
+-00610 
+-00617         int32_t en_multiple_tx_fifo;
+-00618 
+-00623         uint32_t dev_tx_fifo_size[MAX_TX_FIFOS];
+-00624 
+-00630         uint32_t thr_ctl;
+-00631 
+-00635         uint32_t tx_thr_length;
+-00636 
+-00640         uint32_t rx_thr_length;
+-00641 
+-00645         int32_t lpm_enable;
+-00646 
+-00652         int32_t pti_enable;
+-00653 
+-00659         int32_t mpi_enable;
+-00660 
+-00665         int32_t ic_usb_cap;
+-00666 
+-00673         int32_t ahb_thr_ratio;
+-00674 
+-00679         int32_t adp_supp_enable;
+-00680 
+-00685         int32_t reload_ctl;
+-00686 
+-00691         int32_t dev_out_nak;
+-00692 
+-00699         int32_t cont_on_bna;
+-00700 
+-00707         int32_t ahb_single;
+-00708 
+-00714         int32_t power_down;
+-00715 
+-00720         int32_t otg_ver;
+-00721 
+-00722 } dwc_otg_core_params_t;
+-00723 
+-00724 #ifdef DEBUG
+-00725 struct dwc_otg_core_if;
+-00726 typedef struct hc_xfer_info {
+-00727         struct dwc_otg_core_if *core_if;
+-00728         dwc_hc_t *hc;
+-00729 } hc_xfer_info_t;
+-00730 #endif
+-00731 
+-00732 typedef struct ep_xfer_info {
+-00733         struct dwc_otg_core_if *core_if;
+-00734         dwc_ep_t *ep;
+-00735         uint8_t state;
+-00736 } ep_xfer_info_t;
+-00737 /*
+-00738  * Device States
+-00739  */
+-00740 typedef enum dwc_otg_lx_state {
+-00742         DWC_OTG_L0,
+-00744         DWC_OTG_L1,
+-00746         DWC_OTG_L2,
+-00748         DWC_OTG_L3
+-00749 } dwc_otg_lx_state_e;
+-00750 
+-00751 struct dwc_otg_global_regs_backup {
+-00752         uint32_t gotgctl_local;
+-00753         uint32_t gintmsk_local;
+-00754         uint32_t gahbcfg_local;
+-00755         uint32_t gusbcfg_local;
+-00756         uint32_t grxfsiz_local;
+-00757         uint32_t gnptxfsiz_local;
+-00758 #ifdef CONFIG_USB_DWC_OTG_LPM
+-00759         uint32_t glpmcfg_local;
+-00760 #endif
+-00761         uint32_t gi2cctl_local;
+-00762         uint32_t hptxfsiz_local;
+-00763         uint32_t pcgcctl_local;
+-00764         uint32_t gdfifocfg_local;
+-00765         uint32_t dtxfsiz_local[MAX_EPS_CHANNELS];
+-00766         uint32_t gpwrdn_local;
+-00767 };
+-00768 
+-00769 struct dwc_otg_host_regs_backup {
+-00770         uint32_t hcfg_local;
+-00771         uint32_t haintmsk_local;
+-00772         uint32_t hcintmsk_local[MAX_EPS_CHANNELS];
+-00773         uint32_t hprt0_local;
+-00774         uint32_t hfir_local;
+-00775 };
+-00776 
+-00777 struct dwc_otg_dev_regs_backup {
+-00778         uint32_t dcfg;
+-00779         uint32_t dctl;
+-00780         uint32_t daintmsk;
+-00781         uint32_t diepmsk;
+-00782         uint32_t doepmsk;
+-00783         uint32_t diepctl[MAX_EPS_CHANNELS];
+-00784         uint32_t dieptsiz[MAX_EPS_CHANNELS];
+-00785         uint32_t diepdma[MAX_EPS_CHANNELS];
+-00786 };
+-00792 struct dwc_otg_core_if {
+-00794         dwc_otg_core_params_t *core_params;
+-00795 
+-00797         dwc_otg_core_global_regs_t *core_global_regs;
+-00798 
+-00800         dwc_otg_dev_if_t *dev_if;
+-00802         dwc_otg_host_if_t *host_if;
+-00803 
+-00805         uint32_t snpsid;
+-00806 
+-00807         /*
+-00808          * Set to 1 if the core PHY interface bits in USBCFG have been
+-00809          * initialized.
+-00810          */
+-00811         uint8_t phy_init_done;
+-00812 
+-00813         /*
+-00814          * SRP Success flag, set by srp success interrupt in FS I2C mode
+-00815          */
+-00816         uint8_t srp_success;
+-00817         uint8_t srp_timer_started;
+-00820         dwc_timer_t *srp_timer;
+-00821 
+-00822 #ifdef DWC_DEV_SRPCAP
+-00823         /* This timer is needed to power on the hibernated host core if SRP is not
+-00824          * initiated on connected SRP capable device for limited period of time
+-00825          */
+-00826         uint8_t pwron_timer_started;
+-00827         dwc_timer_t *pwron_timer;
+-00828 #endif
+-00829         /* Common configuration information */
+-00831         volatile uint32_t *pcgcctl;
+-00832 #define DWC_OTG_PCGCCTL_OFFSET 0xE00
+-00833 
+-00835         uint32_t *data_fifo[MAX_EPS_CHANNELS];
+-00836 #define DWC_OTG_DATA_FIFO_OFFSET 0x1000
+-00837 #define DWC_OTG_DATA_FIFO_SIZE 0x1000
+-00838 
+-00840         uint16_t total_fifo_size;
+-00842         uint16_t rx_fifo_size;
+-00844         uint16_t nperio_tx_fifo_size;
+-00845 
+-00847         uint8_t dma_enable;
+-00848 
+-00850         uint8_t dma_desc_enable;
+-00851 
+-00853         uint8_t pti_enh_enable;
+-00854 
+-00856         uint8_t multiproc_int_enable;
+-00857 
+-00859         uint8_t en_multiple_tx_fifo;
+-00860 
+-00863         uint8_t queuing_high_bandwidth;
+-00864 
+-00866         hwcfg1_data_t hwcfg1;
+-00867         hwcfg2_data_t hwcfg2;
+-00868         hwcfg3_data_t hwcfg3;
+-00869         hwcfg4_data_t hwcfg4;
+-00870         fifosize_data_t hptxfsiz;
+-00871 
+-00873         hcfg_data_t hcfg;
+-00874         dcfg_data_t dcfg;
+-00875 
+-00881         uint8_t op_state;
+-00882 
+-00888         uint8_t restart_hcd_on_session_req;
+-00889 
+-00892 #define A_HOST          (1)
+-00893 
+-00894 #define A_SUSPEND       (2)
+-00895 
+-00896 #define A_PERIPHERAL    (3)
+-00897 
+-00898 #define B_PERIPHERAL    (4)
+-00899 
+-00900 #define B_HOST          (5)
+-00901 
+-00903         struct dwc_otg_cil_callbacks *hcd_cb;
+-00905         struct dwc_otg_cil_callbacks *pcd_cb;
+-00906 
+-00908         uint32_t p_tx_msk;
+-00910         uint32_t tx_msk;
+-00911 
+-00913         dwc_workq_t *wq_otg;
+-00914 
+-00916         dwc_timer_t *wkp_timer;
+-00918         uint32_t start_doeptsiz_val[MAX_EPS_CHANNELS];
+-00919         ep_xfer_info_t ep_xfer_info[MAX_EPS_CHANNELS];
+-00920         dwc_timer_t *ep_xfer_timer[MAX_EPS_CHANNELS];
+-00921 #ifdef DEBUG
+-00922         uint32_t start_hcchar_val[MAX_EPS_CHANNELS];
+-00923 
+-00924         hc_xfer_info_t hc_xfer_info[MAX_EPS_CHANNELS];
+-00925         dwc_timer_t *hc_xfer_timer[MAX_EPS_CHANNELS];
+-00926 
+-00927         uint32_t hfnum_7_samples;
+-00928         uint64_t hfnum_7_frrem_accum;
+-00929         uint32_t hfnum_0_samples;
+-00930         uint64_t hfnum_0_frrem_accum;
+-00931         uint32_t hfnum_other_samples;
+-00932         uint64_t hfnum_other_frrem_accum;
+-00933 #endif
+-00934 
+-00935 #ifdef DWC_UTE_CFI
+-00936         uint16_t pwron_rxfsiz;
+-00937         uint16_t pwron_gnptxfsiz;
+-00938         uint16_t pwron_txfsiz[15];
+-00939 
+-00940         uint16_t init_rxfsiz;
+-00941         uint16_t init_gnptxfsiz;
+-00942         uint16_t init_txfsiz[15];
+-00943 #endif
+-00944 
+-00946         dwc_otg_lx_state_e lx_state;
+-00947 
+-00949         struct dwc_otg_global_regs_backup *gr_backup;
+-00951         struct dwc_otg_host_regs_backup *hr_backup;
+-00953         struct dwc_otg_dev_regs_backup *dr_backup;
+-00954 
+-00956         uint32_t power_down;
+-00957 
+-00959         uint32_t adp_enable;
+-00960 
+-00962         dwc_otg_adp_t adp;
+-00963 
+-00965         int hibernation_suspend;
+-00966 
+-00968         uint32_t otg_ver;
+-00969 
+-00971         uint8_t otg_sts;
+-00972 
+-00974         dwc_spinlock_t *lock;
+-00975 
+-00978         uint8_t start_predict;
+-00979 
+-00982         uint8_t nextep_seq[MAX_EPS_CHANNELS];
+-00983 
+-00985         uint8_t first_in_nextep_seq;
+-00986 
+-00988         uint32_t frame_num; 
+-00989 
+-00990 };
+-00991 
+-00992 #ifdef DEBUG
+-00993 /*
+-00994  * This function is called when transfer is timed out.
+-00995  */
+-00996 extern void hc_xfer_timeout(void *ptr);
+-00997 #endif
+-00998 
+-00999 /*
+-01000  * This function is called when transfer is timed out on endpoint.
+-01001  */
+-01002 extern void ep_xfer_timeout(void *ptr);
+-01003 
+-01004 /*
+-01005  * The following functions are functions for works
+-01006  * using during handling some interrupts
+-01007  */
+-01008 extern void w_conn_id_status_change(void *p);
+-01009 
+-01010 extern void w_wakeup_detected(void *p);
+-01011 
+-01013 extern int dwc_otg_save_global_regs(dwc_otg_core_if_t * core_if);
+-01015 extern int dwc_otg_save_dev_regs(dwc_otg_core_if_t * core_if);
+-01017 extern int dwc_otg_save_host_regs(dwc_otg_core_if_t * core_if);
+-01019 extern int dwc_otg_restore_global_regs(dwc_otg_core_if_t * core_if);
+-01021 extern int dwc_otg_restore_host_regs(dwc_otg_core_if_t * core_if, int reset);
+-01023 extern int dwc_otg_restore_dev_regs(dwc_otg_core_if_t * core_if,
+-01024                                     int rem_wakeup);
+-01025 extern int restore_lpm_i2c_regs(dwc_otg_core_if_t * core_if);
+-01026 extern int restore_essential_regs(dwc_otg_core_if_t * core_if, int rmode,
+-01027                                   int is_host);
+-01028 
+-01029 extern int dwc_otg_host_hibernation_restore(dwc_otg_core_if_t * core_if,
+-01030                                             int restore_mode, int reset);
+-01031 extern int dwc_otg_device_hibernation_restore(dwc_otg_core_if_t * core_if,
+-01032                                               int rem_wakeup, int reset);
+-01033 
+-01034 /*
+-01035  * The following functions support initialization of the CIL driver component
+-01036  * and the DWC_otg controller.
+-01037  */
+-01038 extern void dwc_otg_core_host_init(dwc_otg_core_if_t * _core_if);
+-01039 extern void dwc_otg_core_dev_init(dwc_otg_core_if_t * _core_if);
+-01040 
+-01046 extern void dwc_otg_wakeup(dwc_otg_core_if_t * _core_if);
+-01047 extern void dwc_otg_read_setup_packet(dwc_otg_core_if_t * _core_if,
+-01048                                       uint32_t * _dest);
+-01049 extern uint32_t dwc_otg_get_frame_number(dwc_otg_core_if_t * _core_if);
+-01050 extern void dwc_otg_ep0_activate(dwc_otg_core_if_t * _core_if, dwc_ep_t * _ep);
+-01051 extern void dwc_otg_ep_activate(dwc_otg_core_if_t * _core_if, dwc_ep_t * _ep);
+-01052 extern void dwc_otg_ep_deactivate(dwc_otg_core_if_t * _core_if, dwc_ep_t * _ep);
+-01053 extern void dwc_otg_ep_start_transfer(dwc_otg_core_if_t * _core_if,
+-01054                                       dwc_ep_t * _ep);
+-01055 extern void dwc_otg_ep_start_zl_transfer(dwc_otg_core_if_t * _core_if,
+-01056                                          dwc_ep_t * _ep);
+-01057 extern void dwc_otg_ep0_start_transfer(dwc_otg_core_if_t * _core_if,
+-01058                                        dwc_ep_t * _ep);
+-01059 extern void dwc_otg_ep0_continue_transfer(dwc_otg_core_if_t * _core_if,
+-01060                                           dwc_ep_t * _ep);
+-01061 extern void dwc_otg_ep_write_packet(dwc_otg_core_if_t * _core_if,
+-01062                                     dwc_ep_t * _ep, int _dma);
+-01063 extern void dwc_otg_ep_set_stall(dwc_otg_core_if_t * _core_if, dwc_ep_t * _ep);
+-01064 extern void dwc_otg_ep_clear_stall(dwc_otg_core_if_t * _core_if,
+-01065                                    dwc_ep_t * _ep);
+-01066 extern void dwc_otg_enable_device_interrupts(dwc_otg_core_if_t * _core_if);
+-01067 
+-01068 #ifdef DWC_EN_ISOC
+-01069 extern void dwc_otg_iso_ep_start_frm_transfer(dwc_otg_core_if_t * core_if,
+-01070                                               dwc_ep_t * ep);
+-01071 extern void dwc_otg_iso_ep_start_buf_transfer(dwc_otg_core_if_t * core_if,
+-01072                                               dwc_ep_t * ep);
+-01073 #endif /* DWC_EN_ISOC */
+-01074 
+-01081 extern void dwc_otg_hc_init(dwc_otg_core_if_t * _core_if, dwc_hc_t * _hc);
+-01082 extern void dwc_otg_hc_halt(dwc_otg_core_if_t * _core_if,
+-01083                             dwc_hc_t * _hc, dwc_otg_halt_status_e _halt_status);
+-01084 extern void dwc_otg_hc_cleanup(dwc_otg_core_if_t * _core_if, dwc_hc_t * _hc);
+-01085 extern void dwc_otg_hc_start_transfer(dwc_otg_core_if_t * _core_if,
+-01086                                       dwc_hc_t * _hc);
+-01087 extern int dwc_otg_hc_continue_transfer(dwc_otg_core_if_t * _core_if,
+-01088                                         dwc_hc_t * _hc);
+-01089 extern void dwc_otg_hc_do_ping(dwc_otg_core_if_t * _core_if, dwc_hc_t * _hc);
+-01090 extern void dwc_otg_hc_write_packet(dwc_otg_core_if_t * _core_if,
+-01091                                     dwc_hc_t * _hc);
+-01092 extern void dwc_otg_enable_host_interrupts(dwc_otg_core_if_t * _core_if);
+-01093 extern void dwc_otg_disable_host_interrupts(dwc_otg_core_if_t * _core_if);
+-01094 
+-01095 extern void dwc_otg_hc_start_transfer_ddma(dwc_otg_core_if_t * core_if,
+-01096                                            dwc_hc_t * hc);
+-01097 
+-01098 extern uint32_t calc_frame_interval(dwc_otg_core_if_t * core_if);
+-01099 
+-01100 /* Macro used to clear one channel interrupt */
+-01101 #define clear_hc_int(_hc_regs_, _intr_) \
+-01102 do { \
+-01103         hcint_data_t hcint_clear = {.d32 = 0}; \
+-01104         hcint_clear.b._intr_ = 1; \
+-01105         DWC_WRITE_REG32(&(_hc_regs_)->hcint, hcint_clear.d32); \
+-01106 } while (0)
+-01107 
+-01108 /*
+-01109  * Macro used to disable one channel interrupt. Channel interrupts are
+-01110  * disabled when the channel is halted or released by the interrupt handler.
+-01111  * There is no need to handle further interrupts of that type until the
+-01112  * channel is re-assigned. In fact, subsequent handling may cause crashes
+-01113  * because the channel structures are cleaned up when the channel is released.
+-01114  */
+-01115 #define disable_hc_int(_hc_regs_, _intr_) \
+-01116 do { \
+-01117         hcintmsk_data_t hcintmsk = {.d32 = 0}; \
+-01118         hcintmsk.b._intr_ = 1; \
+-01119         DWC_MODIFY_REG32(&(_hc_regs_)->hcintmsk, hcintmsk.d32, 0); \
+-01120 } while (0)
+-01121 
+-01127 static inline uint32_t dwc_otg_read_hprt0(dwc_otg_core_if_t * _core_if)
+-01128 {
+-01129         hprt0_data_t hprt0;
+-01130         hprt0.d32 = DWC_READ_REG32(_core_if->host_if->hprt0);
+-01131         hprt0.b.prtena = 0;
+-01132         hprt0.b.prtconndet = 0;
+-01133         hprt0.b.prtenchng = 0;
+-01134         hprt0.b.prtovrcurrchng = 0;
+-01135         return hprt0.d32;
+-01136 }
+-01137 
+-01146 extern void dwc_otg_read_packet(dwc_otg_core_if_t * core_if,
+-01147                                 uint8_t * dest, uint16_t bytes);
+-01148 
+-01149 extern void dwc_otg_flush_tx_fifo(dwc_otg_core_if_t * _core_if, const int _num);
+-01150 extern void dwc_otg_flush_rx_fifo(dwc_otg_core_if_t * _core_if);
+-01151 extern void dwc_otg_core_reset(dwc_otg_core_if_t * _core_if);
+-01152 
+-01156 static inline uint32_t dwc_otg_read_core_intr(dwc_otg_core_if_t * core_if)
+-01157 {
+-01158         return (DWC_READ_REG32(&core_if->core_global_regs->gintsts) &
+-01159                 DWC_READ_REG32(&core_if->core_global_regs->gintmsk));
+-01160 }
+-01161 
+-01165 static inline uint32_t dwc_otg_read_otg_intr(dwc_otg_core_if_t * core_if)
+-01166 {
+-01167         return (DWC_READ_REG32(&core_if->core_global_regs->gotgint));
+-01168 }
+-01169 
+-01174 static inline uint32_t dwc_otg_read_dev_all_in_ep_intr(dwc_otg_core_if_t *
+-01175                                                        core_if)
+-01176 {
+-01177 
+-01178         uint32_t v;
+-01179 
+-01180         if (core_if->multiproc_int_enable) {
+-01181                 v = DWC_READ_REG32(&core_if->dev_if->
+-01182                                    dev_global_regs->deachint) &
+-01183                     DWC_READ_REG32(&core_if->
+-01184                                    dev_if->dev_global_regs->deachintmsk);
+-01185         } else {
+-01186                 v = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->daint) &
+-01187                     DWC_READ_REG32(&core_if->dev_if->dev_global_regs->daintmsk);
+-01188         }
+-01189         return (v & 0xffff);
+-01190 }
+-01191 
+-01196 static inline uint32_t dwc_otg_read_dev_all_out_ep_intr(dwc_otg_core_if_t *
+-01197                                                         core_if)
+-01198 {
+-01199         uint32_t v;
+-01200 
+-01201         if (core_if->multiproc_int_enable) {
+-01202                 v = DWC_READ_REG32(&core_if->dev_if->
+-01203                                    dev_global_regs->deachint) &
+-01204                     DWC_READ_REG32(&core_if->
+-01205                                    dev_if->dev_global_regs->deachintmsk);
+-01206         } else {
+-01207                 v = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->daint) &
+-01208                     DWC_READ_REG32(&core_if->dev_if->dev_global_regs->daintmsk);
+-01209         }
+-01210 
+-01211         return ((v & 0xffff0000) >> 16);
+-01212 }
+-01213 
+-01217 static inline uint32_t dwc_otg_read_dev_in_ep_intr(dwc_otg_core_if_t * core_if,
+-01218                                                    dwc_ep_t * ep)
+-01219 {
+-01220         dwc_otg_dev_if_t *dev_if = core_if->dev_if;
+-01221         uint32_t v, msk, emp;
+-01222 
+-01223         if (core_if->multiproc_int_enable) {
+-01224                 msk =
+-01225                     DWC_READ_REG32(&dev_if->
+-01226                                    dev_global_regs->diepeachintmsk[ep->num]);
+-01227                 emp =
+-01228                     DWC_READ_REG32(&dev_if->
+-01229                                    dev_global_regs->dtknqr4_fifoemptymsk);
+-01230                 msk |= ((emp >> ep->num) & 0x1) << 7;
+-01231                 v = DWC_READ_REG32(&dev_if->in_ep_regs[ep->num]->diepint) & msk;
+-01232         } else {
+-01233                 msk = DWC_READ_REG32(&dev_if->dev_global_regs->diepmsk);
+-01234                 emp =
+-01235                     DWC_READ_REG32(&dev_if->
+-01236                                    dev_global_regs->dtknqr4_fifoemptymsk);
+-01237                 msk |= ((emp >> ep->num) & 0x1) << 7;
+-01238                 v = DWC_READ_REG32(&dev_if->in_ep_regs[ep->num]->diepint) & msk;
+-01239         }
+-01240 
+-01241         return v;
+-01242 }
+-01243 
+-01247 static inline uint32_t dwc_otg_read_dev_out_ep_intr(dwc_otg_core_if_t *
+-01248                                                     _core_if, dwc_ep_t * _ep)
+-01249 {
+-01250         dwc_otg_dev_if_t *dev_if = _core_if->dev_if;
+-01251         uint32_t v;
+-01252         doepmsk_data_t msk = {.d32 = 0 };
+-01253 
+-01254         if (_core_if->multiproc_int_enable) {
+-01255                 msk.d32 =
+-01256                     DWC_READ_REG32(&dev_if->
+-01257                                    dev_global_regs->doepeachintmsk[_ep->num]);
+-01258                 if (_core_if->pti_enh_enable) {
+-01259                         msk.b.pktdrpsts = 1;
+-01260                 }
+-01261                 v = DWC_READ_REG32(&dev_if->
+-01262                                    out_ep_regs[_ep->num]->doepint) & msk.d32;
+-01263         } else {
+-01264                 msk.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->doepmsk);
+-01265                 if (_core_if->pti_enh_enable) {
+-01266                         msk.b.pktdrpsts = 1;
+-01267                 }
+-01268                 v = DWC_READ_REG32(&dev_if->
+-01269                                    out_ep_regs[_ep->num]->doepint) & msk.d32;
+-01270         }
+-01271         return v;
+-01272 }
+-01273 
+-01277 static inline uint32_t dwc_otg_read_host_all_channels_intr(dwc_otg_core_if_t *
+-01278                                                            _core_if)
+-01279 {
+-01280         return (DWC_READ_REG32(&_core_if->host_if->host_global_regs->haint));
+-01281 }
+-01282 
+-01283 static inline uint32_t dwc_otg_read_host_channel_intr(dwc_otg_core_if_t *
+-01284                                                       _core_if, dwc_hc_t * _hc)
+-01285 {
+-01286         return (DWC_READ_REG32
+-01287                 (&_core_if->host_if->hc_regs[_hc->hc_num]->hcint));
+-01288 }
+-01289 
+-01295 static inline uint32_t dwc_otg_mode(dwc_otg_core_if_t * _core_if)
+-01296 {
+-01297         return (DWC_READ_REG32(&_core_if->core_global_regs->gintsts) & 0x1);
+-01298 }
+-01299 
+-01307 typedef struct dwc_otg_cil_callbacks {
+-01309         int (*start) (void *_p);
+-01311         int (*stop) (void *_p);
+-01313         int (*disconnect) (void *_p);
+-01315         int (*resume_wakeup) (void *_p);
+-01317         int (*suspend) (void *_p);
+-01319         int (*session_start) (void *_p);
+-01320 #ifdef CONFIG_USB_DWC_OTG_LPM
+-01321 
+-01322         int (*sleep) (void *_p);
+-01323 #endif
+-01324 
+-01325         void *p;
+-01326 } dwc_otg_cil_callbacks_t;
+-01327 
+-01328 extern void dwc_otg_cil_register_pcd_callbacks(dwc_otg_core_if_t * _core_if,
+-01329                                                dwc_otg_cil_callbacks_t * _cb,
+-01330                                                void *_p);
+-01331 extern void dwc_otg_cil_register_hcd_callbacks(dwc_otg_core_if_t * _core_if,
+-01332                                                dwc_otg_cil_callbacks_t * _cb,
+-01333                                                void *_p);
+-01334 
+-01335 void dwc_otg_initiate_srp(dwc_otg_core_if_t * core_if);
+-01336 
+-01338 
+-01342 static inline void cil_hcd_start(dwc_otg_core_if_t * core_if)
+-01343 {
+-01344         if (core_if->hcd_cb && core_if->hcd_cb->start) {
+-01345                 core_if->hcd_cb->start(core_if->hcd_cb->p);
+-01346         }
+-01347 }
+-01348 
+-01353 static inline void cil_hcd_stop(dwc_otg_core_if_t * core_if)
+-01354 {
+-01355         if (core_if->hcd_cb && core_if->hcd_cb->stop) {
+-01356                 core_if->hcd_cb->stop(core_if->hcd_cb->p);
+-01357         }
+-01358 }
+-01359 
+-01364 static inline void cil_hcd_disconnect(dwc_otg_core_if_t * core_if)
+-01365 {
+-01366         if (core_if->hcd_cb && core_if->hcd_cb->disconnect) {
+-01367                 core_if->hcd_cb->disconnect(core_if->hcd_cb->p);
+-01368         }
+-01369 }
+-01370 
+-01376 static inline void cil_hcd_session_start(dwc_otg_core_if_t * core_if)
+-01377 {
+-01378         if (core_if->hcd_cb && core_if->hcd_cb->session_start) {
+-01379                 core_if->hcd_cb->session_start(core_if->hcd_cb->p);
+-01380         }
+-01381 }
+-01382 
+-01383 #ifdef CONFIG_USB_DWC_OTG_LPM
+-01384 
+-01390 static inline void cil_hcd_sleep(dwc_otg_core_if_t * core_if)
+-01391 {
+-01392         if (core_if->hcd_cb && core_if->hcd_cb->sleep) {
+-01393                 core_if->hcd_cb->sleep(core_if->hcd_cb->p);
+-01394         }
+-01395 }
+-01396 #endif
+-01397 
+-01402 static inline void cil_hcd_resume(dwc_otg_core_if_t * core_if)
+-01403 {
+-01404         if (core_if->hcd_cb && core_if->hcd_cb->resume_wakeup) {
+-01405                 core_if->hcd_cb->resume_wakeup(core_if->hcd_cb->p);
+-01406         }
+-01407 }
+-01408 
+-01413 static inline void cil_pcd_start(dwc_otg_core_if_t * core_if)
+-01414 {
+-01415         if (core_if->pcd_cb && core_if->pcd_cb->start) {
+-01416                 core_if->pcd_cb->start(core_if->pcd_cb->p);
+-01417         }
+-01418 }
+-01419 
+-01424 static inline void cil_pcd_stop(dwc_otg_core_if_t * core_if)
+-01425 {
+-01426         if (core_if->pcd_cb && core_if->pcd_cb->stop) {
+-01427                 core_if->pcd_cb->stop(core_if->pcd_cb->p);
+-01428         }
+-01429 }
+-01430 
+-01435 static inline void cil_pcd_suspend(dwc_otg_core_if_t * core_if)
+-01436 {
+-01437         if (core_if->pcd_cb && core_if->pcd_cb->suspend) {
+-01438                 core_if->pcd_cb->suspend(core_if->pcd_cb->p);
+-01439         }
+-01440 }
+-01441 
+-01446 static inline void cil_pcd_resume(dwc_otg_core_if_t * core_if)
+-01447 {
+-01448         if (core_if->pcd_cb && core_if->pcd_cb->resume_wakeup) {
+-01449                 core_if->pcd_cb->resume_wakeup(core_if->pcd_cb->p);
+-01450         }
+-01451 }
+-01452 
+-01454 
+-01455 #endif
+-
                                                                                Generated on Thu Oct 27 03:56:37 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__cil_8h.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/dwc__otg__cil_8h.html 2013-07-26 19:34:40.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,2598 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_cil.h File Reference +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                dwc_otg_cil.h File Reference

                                                                                This file contains the interface to the Core Interface Layer. More... +-

                                                                                +-#include "dwc_list.h"
                                                                                +-#include "dwc_otg_dbg.h"
                                                                                +-#include "dwc_otg_regs.h"
                                                                                +-#include "dwc_otg_core_if.h"
                                                                                +-#include "dwc_otg_adp.h"
                                                                                +- +-

                                                                                +-Go to the source code of this file. +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-

                                                                                Data Structures

                                                                                struct  iso_pkt_info
                                                                                 Information for each ISOC packet. More...
                                                                                struct  dwc_ep
                                                                                 The dwc_ep structure represents the state of a single endpoint when acting in device mode. More...
                                                                                struct  dwc_hc
                                                                                 Host channel descriptor. More...
                                                                                struct  dwc_otg_core_params
                                                                                 The following parameters may be specified when starting the module. More...
                                                                                struct  ep_xfer_info
                                                                                struct  dwc_otg_global_regs_backup
                                                                                struct  dwc_otg_host_regs_backup
                                                                                struct  dwc_otg_dev_regs_backup
                                                                                struct  dwc_otg_core_if
                                                                                 The dwc_otg_core_if structure contains information needed to manage the DWC_otg controller acting in either host or device mode. More...
                                                                                struct  dwc_otg_cil_callbacks
                                                                                 DWC_otg CIL callback structure. More...

                                                                                Transfer state

                                                                                +-#define MAX_DMA_DESC_CNT   256
                                                                                 Max DMA Descriptor count for any EP.

                                                                                Host CIL Functions

                                                                                The following functions support managing the DWC_otg controller in host mode.

                                                                                #define clear_hc_int(_hc_regs_, _intr_)
                                                                                #define disable_hc_int(_hc_regs_, _intr_)
                                                                                void dwc_otg_hc_init (dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc)
                                                                                 Prepares a host channel for transferring packets to/from a specific endpoint.
                                                                                void dwc_otg_hc_halt (dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc, dwc_otg_halt_status_e _halt_status)
                                                                                 Attempts to halt a host channel.
                                                                                void dwc_otg_hc_cleanup (dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc)
                                                                                 Clears the transfer state for a host channel.
                                                                                void dwc_otg_hc_start_transfer (dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc)
                                                                                 This function does the setup for a data transfer for a host channel and starts the transfer.
                                                                                int dwc_otg_hc_continue_transfer (dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc)
                                                                                 This function continues a data transfer that was started by previous call to dwc_otg_hc_start_transfer.
                                                                                void dwc_otg_hc_do_ping (dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc)
                                                                                 Starts a PING transfer.
                                                                                +-void dwc_otg_hc_write_packet (dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc)
                                                                                void dwc_otg_enable_host_interrupts (dwc_otg_core_if_t *_core_if)
                                                                                 This function enables the Host mode interrupts.
                                                                                void dwc_otg_disable_host_interrupts (dwc_otg_core_if_t *_core_if)
                                                                                 This function disables the Host Mode interrupts.
                                                                                void dwc_otg_hc_start_transfer_ddma (dwc_otg_core_if_t *core_if, dwc_hc_t *hc)
                                                                                 This function does the setup for a data transfer for a host channel and starts the transfer in Descriptor DMA mode.
                                                                                +-uint32_t calc_frame_interval (dwc_otg_core_if_t *core_if)
                                                                                 Calculates and gets the frame Interval value of HFIR register according PHY type and speed.The application can modify a value of HFIR register only after the Port Enable bit of the Host Port Control and Status register (HPRT.PrtEnaPort) has been set.
                                                                                uint32_t dwc_otg_read_hprt0 (dwc_otg_core_if_t *_core_if)
                                                                                 This function Reads HPRT0 in preparation to modify.

                                                                                Device CIL Functions

                                                                                The following functions support managing the DWC_otg controller in device mode.

                                                                                +-void dwc_otg_wakeup (dwc_otg_core_if_t *_core_if)
                                                                                void dwc_otg_read_setup_packet (dwc_otg_core_if_t *_core_if, uint32_t *_dest)
                                                                                 This function reads a setup packet from the Rx FIFO into the destination buffer.
                                                                                uint32_t dwc_otg_get_frame_number (dwc_otg_core_if_t *_core_if)
                                                                                 Gets the current USB frame number.
                                                                                void dwc_otg_ep0_activate (dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep)
                                                                                 This function enables EP0 OUT to receive SETUP packets and configures EP0 IN for transmitting packets.
                                                                                void dwc_otg_ep_activate (dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep)
                                                                                 This function activates an EP.
                                                                                void dwc_otg_ep_deactivate (dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep)
                                                                                 This function deactivates an EP.
                                                                                void dwc_otg_ep_start_transfer (dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep)
                                                                                 This function does the setup for a data transfer for an EP and starts the transfer.
                                                                                void dwc_otg_ep_start_zl_transfer (dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep)
                                                                                 This function setup a zero length transfer in Buffer DMA and Slave modes for usb requests with zero field set.
                                                                                void dwc_otg_ep0_start_transfer (dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep)
                                                                                 This function does the setup for a data transfer for EP0 and starts the transfer.
                                                                                void dwc_otg_ep0_continue_transfer (dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep)
                                                                                 This function continues control IN transfers started by dwc_otg_ep0_start_transfer, when the transfer does not fit in a single packet.
                                                                                void dwc_otg_ep_write_packet (dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep, int _dma)
                                                                                 This function writes a packet into the Tx FIFO associated with the EP.
                                                                                void dwc_otg_ep_set_stall (dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep)
                                                                                 Set the EP STALL.
                                                                                void dwc_otg_ep_clear_stall (dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep)
                                                                                 Clear the EP STALL.
                                                                                void dwc_otg_enable_device_interrupts (dwc_otg_core_if_t *_core_if)
                                                                                 This function enables the Device mode interrupts.
                                                                                void dwc_otg_iso_ep_start_frm_transfer (dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
                                                                                 This function initializes a descriptor chain for Isochronous transfer.
                                                                                void dwc_otg_iso_ep_start_buf_transfer (dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
                                                                                 This function initializes a descriptor chain for Isochronous transfer.

                                                                                Common CIL Functions

                                                                                The following functions support managing the DWC_otg controller in either device or host mode.

                                                                                void dwc_otg_read_packet (dwc_otg_core_if_t *core_if, uint8_t *dest, uint16_t bytes)
                                                                                 This function reads a packet from the Rx FIFO into the destination buffer.
                                                                                void dwc_otg_flush_tx_fifo (dwc_otg_core_if_t *_core_if, const int _num)
                                                                                 Flush a Tx FIFO.
                                                                                void dwc_otg_flush_rx_fifo (dwc_otg_core_if_t *_core_if)
                                                                                 Flush Rx FIFO.
                                                                                void dwc_otg_core_reset (dwc_otg_core_if_t *_core_if)
                                                                                 Do core a soft reset of the core.
                                                                                +-uint32_t dwc_otg_read_core_intr (dwc_otg_core_if_t *core_if)
                                                                                 This function returns the Core Interrupt register.
                                                                                +-uint32_t dwc_otg_read_otg_intr (dwc_otg_core_if_t *core_if)
                                                                                 This function returns the OTG Interrupt register.
                                                                                +-uint32_t dwc_otg_read_dev_all_in_ep_intr (dwc_otg_core_if_t *core_if)
                                                                                 This function reads the Device All Endpoints Interrupt register and returns the IN endpoint interrupt bits.
                                                                                +-uint32_t dwc_otg_read_dev_all_out_ep_intr (dwc_otg_core_if_t *core_if)
                                                                                 This function reads the Device All Endpoints Interrupt register and returns the OUT endpoint interrupt bits.
                                                                                +-uint32_t dwc_otg_read_dev_in_ep_intr (dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
                                                                                 This function returns the Device IN EP Interrupt register.
                                                                                +-uint32_t dwc_otg_read_dev_out_ep_intr (dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep)
                                                                                 This function returns the Device OUT EP Interrupt register.
                                                                                +-uint32_t dwc_otg_read_host_all_channels_intr (dwc_otg_core_if_t *_core_if)
                                                                                 This function returns the Host All Channel Interrupt register.
                                                                                +-uint32_t dwc_otg_read_host_channel_intr (dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc)
                                                                                uint32_t dwc_otg_mode (dwc_otg_core_if_t *_core_if)
                                                                                 This function returns the mode of the operation, host or device.

                                                                                Defines

                                                                                +-#define __DWC_CIL_H__
                                                                                +-#define OTG_CORE_REV_2_60a   0x4F54260A
                                                                                 Macros defined for DWC OTG HW Release version.
                                                                                +-#define OTG_CORE_REV_2_71a   0x4F54271A
                                                                                +-#define OTG_CORE_REV_2_72a   0x4F54272A
                                                                                +-#define OTG_CORE_REV_2_80a   0x4F54280A
                                                                                +-#define OTG_CORE_REV_2_81a   0x4F54281A
                                                                                +-#define OTG_CORE_REV_2_90a   0x4F54290A
                                                                                +-#define OTG_CORE_REV_2_91a   0x4F54291A
                                                                                +-#define OTG_CORE_REV_2_92a   0x4F54292A
                                                                                +-#define OTG_CORE_REV_2_93a   0x4F54293A
                                                                                +-#define OTG_CORE_REV_2_94a   0x4F54294A
                                                                                +-#define DWC_OTG_EP_TYPE_CONTROL   0
                                                                                +-#define DWC_OTG_EP_TYPE_ISOC   1
                                                                                +-#define DWC_OTG_EP_TYPE_BULK   2
                                                                                +-#define DWC_OTG_EP_TYPE_INTR   3
                                                                                +-#define DWC_OTG_EP_SPEED_LOW   0
                                                                                +-#define DWC_OTG_EP_SPEED_FULL   1
                                                                                +-#define DWC_OTG_EP_SPEED_HIGH   2
                                                                                +-#define DWC_OTG_HC_PID_DATA0   0
                                                                                +-#define DWC_OTG_HC_PID_DATA2   1
                                                                                +-#define DWC_OTG_HC_PID_DATA1   2
                                                                                +-#define DWC_OTG_HC_PID_MDATA   3
                                                                                +-#define DWC_OTG_HC_PID_SETUP   3
                                                                                +-#define DWC_OTG_PCGCCTL_OFFSET   0xE00
                                                                                +-#define DWC_OTG_DATA_FIFO_OFFSET   0x1000
                                                                                +-#define DWC_OTG_DATA_FIFO_SIZE   0x1000
                                                                                +-#define A_HOST   (1)
                                                                                 A-Device is a_host.
                                                                                +-#define A_SUSPEND   (2)
                                                                                 A-Device is a_suspend.
                                                                                +-#define A_PERIPHERAL   (3)
                                                                                 A-Device is a_peripherial.
                                                                                +-#define B_PERIPHERAL   (4)
                                                                                 B-Device is operating as a Peripheral.
                                                                                +-#define B_HOST   (5)
                                                                                 B-Device is operating as a Host.

                                                                                Typedefs

                                                                                +-typedef iso_pkt_info iso_pkt_info_t
                                                                                 Information for each ISOC packet.
                                                                                typedef dwc_ep dwc_ep_t
                                                                                 The dwc_ep structure represents the state of a single endpoint when acting in device mode.
                                                                                +-typedef enum dwc_otg_halt_status dwc_otg_halt_status_e
                                                                                typedef dwc_hc dwc_hc_t
                                                                                 Host channel descriptor.
                                                                                typedef dwc_otg_core_params dwc_otg_core_params_t
                                                                                 The following parameters may be specified when starting the module.
                                                                                +-typedef ep_xfer_info ep_xfer_info_t
                                                                                +-typedef enum dwc_otg_lx_state dwc_otg_lx_state_e
                                                                                typedef dwc_otg_cil_callbacks dwc_otg_cil_callbacks_t
                                                                                 DWC_otg CIL callback structure.

                                                                                Enumerations

                                                                                enum  dwc_otg_halt_status {
                                                                                +-  DWC_OTG_HC_XFER_NO_HALT_STATUS, +-DWC_OTG_HC_XFER_COMPLETE, +-DWC_OTG_HC_XFER_URB_COMPLETE, +-DWC_OTG_HC_XFER_ACK, +-
                                                                                +-  DWC_OTG_HC_XFER_NAK, +-DWC_OTG_HC_XFER_NYET, +-DWC_OTG_HC_XFER_STALL, +-DWC_OTG_HC_XFER_XACT_ERR, +-
                                                                                +-  DWC_OTG_HC_XFER_FRAME_OVERRUN, +-DWC_OTG_HC_XFER_BABBLE_ERR, +-DWC_OTG_HC_XFER_DATA_TOGGLE_ERR, +-DWC_OTG_HC_XFER_AHB_ERR, +-
                                                                                +-  DWC_OTG_HC_XFER_PERIODIC_INCOMPLETE, +-DWC_OTG_HC_XFER_URB_DEQUEUE +-
                                                                                +- }
                                                                                enum  dwc_otg_lx_state { DWC_OTG_L0, +-DWC_OTG_L1, +-DWC_OTG_L2, +-DWC_OTG_L3 +- }

                                                                                Functions

                                                                                +-void ep_xfer_timeout (void *ptr)
                                                                                +-void w_conn_id_status_change (void *p)
                                                                                void w_wakeup_detected (void *p)
                                                                                +-int dwc_otg_save_global_regs (dwc_otg_core_if_t *core_if)
                                                                                 Saves global register values into system memory.
                                                                                +-int dwc_otg_save_dev_regs (dwc_otg_core_if_t *core_if)
                                                                                 Saves device register values into system memory.
                                                                                +-int dwc_otg_save_host_regs (dwc_otg_core_if_t *core_if)
                                                                                 Saves host register values into system memory.
                                                                                +-int dwc_otg_restore_global_regs (dwc_otg_core_if_t *core_if)
                                                                                 Restore global register values.
                                                                                +-int dwc_otg_restore_host_regs (dwc_otg_core_if_t *core_if, int reset)
                                                                                 Restore host register values.
                                                                                +-int dwc_otg_restore_dev_regs (dwc_otg_core_if_t *core_if, int rem_wakeup)
                                                                                 Restore device register values.
                                                                                +-int restore_lpm_i2c_regs (dwc_otg_core_if_t *core_if)
                                                                                +-int restore_essential_regs (dwc_otg_core_if_t *core_if, int rmode, int is_host)
                                                                                +-int dwc_otg_host_hibernation_restore (dwc_otg_core_if_t *core_if, int restore_mode, int reset)
                                                                                +-int dwc_otg_device_hibernation_restore (dwc_otg_core_if_t *core_if, int rem_wakeup, int reset)
                                                                                void dwc_otg_core_host_init (dwc_otg_core_if_t *_core_if)
                                                                                 This function initializes the DWC_otg controller registers for host mode.
                                                                                void dwc_otg_core_dev_init (dwc_otg_core_if_t *_core_if)
                                                                                 This function initializes the DWC_otg controller registers for device mode.
                                                                                void dwc_otg_cil_register_pcd_callbacks (dwc_otg_core_if_t *_core_if, dwc_otg_cil_callbacks_t *_cb, void *_p)
                                                                                 Register PCD callbacks.
                                                                                void dwc_otg_cil_register_hcd_callbacks (dwc_otg_core_if_t *_core_if, dwc_otg_cil_callbacks_t *_cb, void *_p)
                                                                                 Register HCD callbacks.
                                                                                +-void dwc_otg_initiate_srp (dwc_otg_core_if_t *core_if)
                                                                                void cil_hcd_start (dwc_otg_core_if_t *core_if)
                                                                                 Start the HCD.
                                                                                void cil_hcd_stop (dwc_otg_core_if_t *core_if)
                                                                                 Stop the HCD.
                                                                                void cil_hcd_disconnect (dwc_otg_core_if_t *core_if)
                                                                                 Disconnect the HCD.
                                                                                void cil_hcd_session_start (dwc_otg_core_if_t *core_if)
                                                                                 Inform the HCD the a New Session has begun.
                                                                                void cil_hcd_resume (dwc_otg_core_if_t *core_if)
                                                                                 Resume the HCD.
                                                                                void cil_pcd_start (dwc_otg_core_if_t *core_if)
                                                                                 Start the PCD.
                                                                                void cil_pcd_stop (dwc_otg_core_if_t *core_if)
                                                                                 Stop the PCD.
                                                                                void cil_pcd_suspend (dwc_otg_core_if_t *core_if)
                                                                                 Suspend the PCD.
                                                                                void cil_pcd_resume (dwc_otg_core_if_t *core_if)
                                                                                 Resume the PCD.
                                                                                +-

                                                                                Detailed Description

                                                                                +-This file contains the interface to the Core Interface Layer. +-

                                                                                +- +-

                                                                                +-Definition in file dwc_otg_cil.h.

                                                                                Define Documentation

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                #define clear_hc_int ( _hc_regs_,
                                                                                _intr_   ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Value:

                                                                                do { \
+-        hcint_data_t hcint_clear = {.d32 = 0}; \
+-        hcint_clear.b._intr_ = 1; \
+-        DWC_WRITE_REG32(&(_hc_regs_)->hcint, hcint_clear.d32); \
+-} while (0)
+-
                                                                                +-

                                                                                +-Definition at line 1101 of file dwc_otg_cil.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                #define disable_hc_int ( _hc_regs_,
                                                                                _intr_   ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Value:

                                                                                do { \
+-        hcintmsk_data_t hcintmsk = {.d32 = 0}; \
+-        hcintmsk.b._intr_ = 1; \
+-        DWC_MODIFY_REG32(&(_hc_regs_)->hcintmsk, hcintmsk.d32, 0); \
+-} while (0)
+-
                                                                                +-

                                                                                +-Definition at line 1115 of file dwc_otg_cil.h.

                                                                                +-

                                                                                Typedef Documentation

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                typedef struct dwc_ep dwc_ep_t
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-The dwc_ep structure represents the state of a single endpoint when acting in device mode. +-

                                                                                +-It contains the data items needed for an endpoint to be activated and transfer packets.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                typedef struct dwc_hc dwc_hc_t
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Host channel descriptor. +-

                                                                                +-This structure represents the state of a single host channel when acting in host mode. It contains the data items needed to transfer packets to an endpoint via a host channel.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                typedef struct dwc_otg_core_params dwc_otg_core_params_t
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-The following parameters may be specified when starting the module. +-

                                                                                +-These parameters define how the DWC_otg controller should be configured.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                typedef struct dwc_otg_cil_callbacks dwc_otg_cil_callbacks_t
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-DWC_otg CIL callback structure. +-

                                                                                +-This structure allows the HCD and PCD to register functions used for starting and stopping the PCD and HCD for role change on for a DRD.

                                                                                +-

                                                                                Enumeration Type Documentation

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                enum dwc_otg_lx_state
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-

                                                                                Enumeration values:
                                                                                +- +- +- +- +- +-
                                                                                DWC_OTG_L0  +-On state.
                                                                                DWC_OTG_L1  +-LPM sleep state.
                                                                                DWC_OTG_L2  +-USB suspend state.
                                                                                DWC_OTG_L3  +-Off state.
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 740 of file dwc_otg_cil.h.

                                                                                +-

                                                                                Function Documentation

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                void w_wakeup_detected ( void *  p  ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Change to L0 state +-

                                                                                +-Definition at line 398 of file dwc_otg_cil_intr.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                void dwc_otg_core_host_init ( dwc_otg_core_if_t *  core_if  ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This function initializes the DWC_otg controller registers for host mode. +-

                                                                                +-This function flushes the Tx and Rx FIFOs and it flushes any entries in the request queues. Host channels are reset to ensure that they are ready for performing transfers.

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +-
                                                                                core_if Programming view of DWC_otg controller
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 2019 of file dwc_otg_cil.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                void dwc_otg_core_dev_init ( dwc_otg_core_if_t *  core_if  ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This function initializes the DWC_otg controller registers for device mode. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +-
                                                                                core_if Programming view of DWC_otg controller
                                                                                +-
                                                                                +-

                                                                                +-Set Periodic Tx FIFO Mask all bits 0

                                                                                +-Set Tx FIFO Mask all bits 0

                                                                                +-

                                                                                Todo:
                                                                                NGS: Fix Periodic FIFO Sizing!

                                                                                +-Finish debug of this

                                                                                +-- if the condition needed to be checked or in any case all pending interrutps should be cleared?

                                                                                +- +-

                                                                                +-Definition at line 1620 of file dwc_otg_cil.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                void dwc_otg_read_setup_packet ( dwc_otg_core_if_t *  core_if,
                                                                                uint32_t *  dest
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This function reads a setup packet from the Rx FIFO into the destination buffer. +-

                                                                                +-This function is called from the Rx Status Queue Level (RxStsQLvl) Interrupt routine when a SETUP packet has been received in Slave mode.

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +-
                                                                                core_if Programming view of DWC_otg controller.
                                                                                dest Destination buffer for packet data.
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 3144 of file dwc_otg_cil.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                uint32_t dwc_otg_get_frame_number ( dwc_otg_core_if_t *  core_if  ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Gets the current USB frame number. +-

                                                                                +-This is the frame number from the last SOF packet. +-

                                                                                +-Definition at line 3086 of file dwc_otg_cil.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                void dwc_otg_ep0_activate ( dwc_otg_core_if_t *  core_if,
                                                                                dwc_ep_t *  ep
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This function enables EP0 OUT to receive SETUP packets and configures EP0 IN for transmitting packets. +-

                                                                                +-It is normally called when the "Enumeration Done" interrupt occurs.

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +-
                                                                                core_if Programming view of DWC_otg controller.
                                                                                ep The EP0 data.
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 3161 of file dwc_otg_cil.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                void dwc_otg_ep_activate ( dwc_otg_core_if_t *  core_if,
                                                                                dwc_ep_t *  ep
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This function activates an EP. +-

                                                                                +-The Device EP control register for the EP is configured as defined in the ep structure. Note: This function is not used for EP0.

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +-
                                                                                core_if Programming view of DWC_otg controller.
                                                                                ep The EP to activate.
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 3214 of file dwc_otg_cil.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                void dwc_otg_ep_deactivate ( dwc_otg_core_if_t *  core_if,
                                                                                dwc_ep_t *  ep
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This function deactivates an EP. +-

                                                                                +-This is done by clearing the USB Active EP bit in the Device EP control register. Note: This function is not used for EP0. EP0 cannot be deactivated.

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +-
                                                                                core_if Programming view of DWC_otg controller.
                                                                                ep The EP to deactivate.
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 3369 of file dwc_otg_cil.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                void dwc_otg_ep_start_transfer ( dwc_otg_core_if_t *  core_if,
                                                                                dwc_ep_t *  ep
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This function does the setup for a data transfer for an EP and starts the transfer. +-

                                                                                +-For an IN transfer, the packets will be loaded into the appropriate Tx FIFO in the ISR. For OUT transfers, the packets are unloaded from the Rx FIFO in the ISR. the ISR.

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +-
                                                                                core_if Programming view of DWC_otg controller.
                                                                                ep The EP to start the transfer on.
                                                                                +-
                                                                                +-

                                                                                +-DIEPDMAn Register write

                                                                                +-Enable the Non-Periodic Tx FIFO empty interrupt, or the Tx FIFO epmty interrupt in dedicated Tx FIFO mode, the data will be written into the fifo by the ISR.

                                                                                +-This is used for interrupt out transfers

                                                                                +-DOEPDMAn Register write +-

                                                                                +-Definition at line 3655 of file dwc_otg_cil.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                void dwc_otg_ep_start_zl_transfer ( dwc_otg_core_if_t *  core_if,
                                                                                dwc_ep_t *  ep
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This function setup a zero length transfer in Buffer DMA and Slave modes for usb requests with zero field set. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +-
                                                                                core_if Programming view of DWC_otg controller.
                                                                                ep The EP to start the transfer on.
                                                                                +-
                                                                                +-

                                                                                +-Enable the Non-Periodic Tx FIFO empty interrupt, or the Tx FIFO epmty interrupt in dedicated Tx FIFO mode, the data will be written into the fifo by the ISR. +-

                                                                                +-Definition at line 3948 of file dwc_otg_cil.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                void dwc_otg_ep0_start_transfer ( dwc_otg_core_if_t *  core_if,
                                                                                dwc_ep_t *  ep
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This function does the setup for a data transfer for EP0 and starts the transfer. +-

                                                                                +-For an IN transfer, the packets will be loaded into the appropriate Tx FIFO in the ISR. For OUT transfers, the packets are unloaded from the Rx FIFO in the ISR.

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +-
                                                                                core_if Programming view of DWC_otg controller.
                                                                                ep The EP0 data.
                                                                                +-
                                                                                +-

                                                                                +-DMA Descriptor Setup

                                                                                +-DIEPDMA0 Register write

                                                                                +-Enable the Non-Periodic Tx FIFO empty interrupt, the data will be written into the fifo by the ISR.

                                                                                +-DMA Descriptor Setup

                                                                                +-DOEPDMA0 Register write +-

                                                                                +-Definition at line 4051 of file dwc_otg_cil.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                void dwc_otg_ep0_continue_transfer ( dwc_otg_core_if_t *  core_if,
                                                                                dwc_ep_t *  ep
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This function continues control IN transfers started by dwc_otg_ep0_start_transfer, when the transfer does not fit in a single packet. +-

                                                                                +-NOTE: The DIEPCTL0/DOEPCTL0 registers only have one bit for the packet count.

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +-
                                                                                core_if Programming view of DWC_otg controller.
                                                                                ep The EP0 data.
                                                                                +-
                                                                                +-

                                                                                +-

                                                                                Todo:
                                                                                Should there be check for room in the Tx Status Queue. If not remove the code above this comment.
                                                                                +-

                                                                                +-DMA Descriptor Setup

                                                                                +-DIEPDMA0 Register write

                                                                                +-Enable the Non-Periodic Tx FIFO empty interrupt, the data will be written into the fifo by the ISR.

                                                                                +-DMA Descriptor Setup

                                                                                +-DOEPDMA0 Register write +-

                                                                                +-Definition at line 4239 of file dwc_otg_cil.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                void dwc_otg_ep_write_packet ( dwc_otg_core_if_t *  core_if,
                                                                                dwc_ep_t *  ep,
                                                                                int  dma
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This function writes a packet into the Tx FIFO associated with the EP. +-

                                                                                +-For non-periodic EPs the non-periodic Tx FIFO is written. For periodic EPs the periodic Tx FIFO associated with the EP is written with all packets for the next micro-frame.

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +- +-
                                                                                core_if Programming view of DWC_otg controller.
                                                                                ep The EP to write packet for.
                                                                                dma Indicates if DMA is being used.
                                                                                +-
                                                                                +-

                                                                                +-The buffer is padded to DWORD on a per packet basis in slave/dma mode if the MPS is not DWORD aligned. The last packet, if short, is also padded to a multiple of DWORD.

                                                                                +-ep->xfer_buff always starts DWORD aligned in memory and is a multiple of DWORD in length

                                                                                +-ep->xfer_len can be any number of bytes

                                                                                +-ep->xfer_count is a multiple of ep->maxpacket until the last packet

                                                                                +-FIFO access is DWORD

                                                                                +-

                                                                                Todo:
                                                                                NGS Where are the Periodic Tx FIFO addresses intialized? What should this be?
                                                                                +- +-

                                                                                +-Definition at line 4438 of file dwc_otg_cil.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                void dwc_otg_ep_set_stall ( dwc_otg_core_if_t *  core_if,
                                                                                dwc_ep_t *  ep
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Set the EP STALL. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +-
                                                                                core_if Programming view of DWC_otg controller.
                                                                                ep The EP to set the stall on.
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 4509 of file dwc_otg_cil.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                void dwc_otg_ep_clear_stall ( dwc_otg_core_if_t *  core_if,
                                                                                dwc_ep_t *  ep
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Clear the EP STALL. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +-
                                                                                core_if Programming view of DWC_otg controller.
                                                                                ep The EP to clear stall from.
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 4547 of file dwc_otg_cil.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                void dwc_otg_enable_device_interrupts ( dwc_otg_core_if_t *  core_if  ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This function enables the Device mode interrupts. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +-
                                                                                core_if Programming view of DWC_otg controller
                                                                                +-
                                                                                +-

                                                                                +-

                                                                                Todo:
                                                                                NGS: Should this be a module parameter?
                                                                                +- +-

                                                                                +-Definition at line 1526 of file dwc_otg_cil.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                void dwc_otg_iso_ep_start_frm_transfer ( dwc_otg_core_if_t *  core_if,
                                                                                dwc_ep_t *  ep
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This function initializes a descriptor chain for Isochronous transfer. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +-
                                                                                core_if Programming view of DWC_otg controller.
                                                                                ep The EP to start the transfer on.
                                                                                +-
                                                                                +-

                                                                                +-Enable endpoint, clear nak +-

                                                                                +-Definition at line 5161 of file dwc_otg_cil.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                void dwc_otg_iso_ep_start_buf_transfer ( dwc_otg_core_if_t *  core_if,
                                                                                dwc_ep_t *  ep
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This function initializes a descriptor chain for Isochronous transfer. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +-
                                                                                core_if Programming view of DWC_otg controller.
                                                                                ep The EP to start the transfer on.
                                                                                +-
                                                                                +-

                                                                                +-Enable endpoint, clear nak +-

                                                                                +-Definition at line 540 of file dwc_otg_pcd.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                void dwc_otg_hc_init ( dwc_otg_core_if_t *  core_if,
                                                                                dwc_hc_t *  hc
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Prepares a host channel for transferring packets to/from a specific endpoint. +-

                                                                                +-The HCCHARn register is set up with the characteristics specified in _hc. Host channel interrupts that may need to be serviced while this transfer is in progress are enabled.

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +-
                                                                                core_if Programming view of DWC_otg controller
                                                                                hc Information needed to initialize the host channel
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 2206 of file dwc_otg_cil.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                void dwc_otg_hc_halt ( dwc_otg_core_if_t *  core_if,
                                                                                dwc_hc_t *  hc,
                                                                                dwc_otg_halt_status_e  halt_status
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Attempts to halt a host channel. +-

                                                                                +-This function should only be called in Slave mode or to abort a transfer in either Slave mode or DMA mode. Under normal circumstances in DMA mode, the controller halts the channel when the transfer is complete or a condition occurs that requires application intervention.

                                                                                +-In slave mode, checks for a free request queue entry, then sets the Channel Enable and Channel Disable bits of the Host Channel Characteristics register of the specified channel to intiate the halt. If there is no free request queue entry, sets only the Channel Disable bit of the HCCHARn register to flush requests for this channel. In the latter case, sets a flag to indicate that the host channel needs to be halted when a request queue slot is open.

                                                                                +-In DMA mode, always sets the Channel Enable and Channel Disable bits of the HCCHARn register. The controller ensures there is space in the request queue before submitting the halt request.

                                                                                +-Some time may elapse before the core flushes any posted requests for this host channel and halts. The Channel Halted interrupt handler completes the deactivation of the host channel.

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +- +-
                                                                                core_if Controller register interface.
                                                                                hc Host channel to halt.
                                                                                halt_status Reason for halting the channel.
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 2394 of file dwc_otg_cil.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                void dwc_otg_hc_cleanup ( dwc_otg_core_if_t *  core_if,
                                                                                dwc_hc_t *  hc
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Clears the transfer state for a host channel. +-

                                                                                +-This function is normally called after a transfer is done and the host channel is being released.

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +-
                                                                                core_if Programming view of DWC_otg controller.
                                                                                hc Identifies the host channel to clean up.
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 2521 of file dwc_otg_cil.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                void dwc_otg_hc_start_transfer ( dwc_otg_core_if_t *  core_if,
                                                                                dwc_hc_t *  hc
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This function does the setup for a data transfer for a host channel and starts the transfer. +-

                                                                                +-May be called in either Slave mode or DMA mode. In Slave mode, the caller must ensure that there is sufficient space in the request queue and Tx Data FIFO.

                                                                                +-For an OUT transfer in Slave mode, it loads a data packet into the appropriate FIFO. If necessary, additional data packets will be loaded in the Host ISR.

                                                                                +-For an IN transfer in Slave mode, a data packet is requested. The data packets are unloaded from the Rx FIFO in the Host ISR. If necessary, additional data packets are requested in the Host ISR.

                                                                                +-For a PING transfer in Slave mode, the Do Ping bit is set in the HCTSIZ register along with a packet count of 1 and the channel is enabled. This causes a single PING transaction to occur. Other fields in HCTSIZ are simply set to 0 since no data transfer occurs in this case.

                                                                                +-For a PING transfer in DMA mode, the HCTSIZ register is initialized with all the information required to perform the subsequent data transfer. In addition, the Do Ping bit is set in the HCTSIZ register. In this case, the controller performs the entire PING protocol, then starts the data transfer.

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +-
                                                                                core_if Programming view of DWC_otg controller.
                                                                                hc Information needed to initialize the host channel. The xfer_len value may be reduced to accommodate the max widths of the XferSize and PktCnt fields in the HCTSIZn register. The multi_count value may be changed to reflect the final xfer_len value.
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 2703 of file dwc_otg_cil.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                int dwc_otg_hc_continue_transfer ( dwc_otg_core_if_t *  core_if,
                                                                                dwc_hc_t *  hc
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This function continues a data transfer that was started by previous call to dwc_otg_hc_start_transfer. +-

                                                                                +-The caller must ensure there is sufficient space in the request queue and Tx Data FIFO. This function should only be called in Slave mode. In DMA mode, the controller acts autonomously to complete transfers programmed to a host channel.

                                                                                +-For an OUT transfer, a new data packet is loaded into the appropriate FIFO if there is any data remaining to be queued. For an IN transfer, another data packet is always requested. For the SETUP phase of a control transfer, this function does nothing.

                                                                                +-

                                                                                Returns:
                                                                                1 if a new request is queued, 0 if no more requests are required for this transfer.
                                                                                +- +-

                                                                                +-Definition at line 2952 of file dwc_otg_cil.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                void dwc_otg_hc_do_ping ( dwc_otg_core_if_t *  core_if,
                                                                                dwc_hc_t *  hc
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Starts a PING transfer. +-

                                                                                +-This function should only be called in Slave mode. The Do Ping bit is set in the HCTSIZ register, then the channel is enabled. +-

                                                                                +-Definition at line 3014 of file dwc_otg_cil.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                void dwc_otg_enable_host_interrupts ( dwc_otg_core_if_t *  core_if  ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This function enables the Host mode interrupts. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +-
                                                                                core_if Programming view of DWC_otg controller
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 1955 of file dwc_otg_cil.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                void dwc_otg_disable_host_interrupts ( dwc_otg_core_if_t *  core_if  ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This function disables the Host Mode interrupts. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +-
                                                                                core_if Programming view of DWC_otg controller
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 1988 of file dwc_otg_cil.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                void dwc_otg_hc_start_transfer_ddma ( dwc_otg_core_if_t *  core_if,
                                                                                dwc_hc_t *  hc
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This function does the setup for a data transfer for a host channel and starts the transfer in Descriptor DMA mode. +-

                                                                                +-Initializes HCTSIZ register. For a PING transfer the Do Ping bit is set. Sets PID and NTD values. For periodic transfers initializes SCHED_INFO field with micro-frame bitmap.

                                                                                +-Initializes HCDMA register with descriptor list address and CTD value then starts the transfer via enabling the channel.

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +-
                                                                                core_if Programming view of DWC_otg controller.
                                                                                hc Information needed to initialize the host channel.
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 2872 of file dwc_otg_cil.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                uint32_t dwc_otg_read_hprt0 ( dwc_otg_core_if_t *  _core_if  )  [inline, static]
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This function Reads HPRT0 in preparation to modify. +-

                                                                                +-It keeps the WC bits 0 so that if they are read as 1, they won't clear when you write it back +-

                                                                                +-Definition at line 1127 of file dwc_otg_cil.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                void dwc_otg_read_packet ( dwc_otg_core_if_t *  core_if,
                                                                                uint8_t *  dest,
                                                                                uint16_t  bytes
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This function reads a packet from the Rx FIFO into the destination buffer. +-

                                                                                +-To read SETUP data use dwc_otg_read_setup_packet.

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +- +-
                                                                                core_if Programming view of DWC_otg controller.
                                                                                dest Destination buffer for the packet.
                                                                                bytes Number of bytes to copy to the destination.
                                                                                +-
                                                                                +-

                                                                                +-

                                                                                Todo:
                                                                                Account for the case where _dest is not dword aligned. This requires reading data from the FIFO into a uint32_t temp buffer, then moving it into the data buffer.
                                                                                +- +-

                                                                                +-Definition at line 4590 of file dwc_otg_cil.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                void dwc_otg_flush_tx_fifo ( dwc_otg_core_if_t *  core_if,
                                                                                const int  num
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Flush a Tx FIFO. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +-
                                                                                core_if Programming view of DWC_otg controller.
                                                                                num Tx FIFO to flush.
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 4959 of file dwc_otg_cil.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                void dwc_otg_flush_rx_fifo ( dwc_otg_core_if_t *  core_if  ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Flush Rx FIFO. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +-
                                                                                core_if Programming view of DWC_otg controller.
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 4991 of file dwc_otg_cil.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                void dwc_otg_core_reset ( dwc_otg_core_if_t *  core_if  ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Do core a soft reset of the core. +-

                                                                                +-Be careful with this because it resets all the internal state machines of the core. +-

                                                                                +-Definition at line 5022 of file dwc_otg_cil.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                uint32_t dwc_otg_mode ( dwc_otg_core_if_t *  _core_if  )  [inline, static]
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This function returns the mode of the operation, host or device. +-

                                                                                +-

                                                                                Returns:
                                                                                0 - Device Mode, 1 - Host Mode
                                                                                +- +-

                                                                                +-Definition at line 1295 of file dwc_otg_cil.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                void dwc_otg_cil_register_pcd_callbacks ( dwc_otg_core_if_t *  core_if,
                                                                                dwc_otg_cil_callbacks_t *  cb,
                                                                                void *  p
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Register PCD callbacks. +-

                                                                                +-The callbacks are used to start and stop the PCD for interrupt processing.

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +- +-
                                                                                core_if Programming view of DWC_otg controller.
                                                                                cb the PCD callback structure.
                                                                                p pointer to be passed to callback function (pcd*).
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 5093 of file dwc_otg_cil.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                void dwc_otg_cil_register_hcd_callbacks ( dwc_otg_core_if_t *  core_if,
                                                                                dwc_otg_cil_callbacks_t *  cb,
                                                                                void *  p
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Register HCD callbacks. +-

                                                                                +-The callbacks are used to start and stop the HCD for interrupt processing.

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +- +-
                                                                                core_if Programming view of DWC_otg controller.
                                                                                cb the HCD callback structure.
                                                                                p pointer to be passed to callback function (usb_hcd*).
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 5078 of file dwc_otg_cil.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                void cil_hcd_start ( dwc_otg_core_if_t *  core_if  )  [inline, static]
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Start the HCD. +-

                                                                                +-Helper function for using the HCD callbacks.

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +-
                                                                                core_if Programming view of DWC_otg controller.
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 1342 of file dwc_otg_cil.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                void cil_hcd_stop ( dwc_otg_core_if_t *  core_if  )  [inline, static]
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Stop the HCD. +-

                                                                                +-Helper function for using the HCD callbacks.

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +-
                                                                                core_if Programming view of DWC_otg controller.
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 1353 of file dwc_otg_cil.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                void cil_hcd_disconnect ( dwc_otg_core_if_t *  core_if  )  [inline, static]
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Disconnect the HCD. +-

                                                                                +-Helper function for using the HCD callbacks.

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +-
                                                                                core_if Programming view of DWC_otg controller.
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 1364 of file dwc_otg_cil.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                void cil_hcd_session_start ( dwc_otg_core_if_t *  core_if  )  [inline, static]
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Inform the HCD the a New Session has begun. +-

                                                                                +-Helper function for using the HCD callbacks.

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +-
                                                                                core_if Programming view of DWC_otg controller.
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 1376 of file dwc_otg_cil.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                void cil_hcd_resume ( dwc_otg_core_if_t *  core_if  )  [inline, static]
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Resume the HCD. +-

                                                                                +-Helper function for using the HCD callbacks.

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +-
                                                                                core_if Programming view of DWC_otg controller.
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 1402 of file dwc_otg_cil.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                void cil_pcd_start ( dwc_otg_core_if_t *  core_if  )  [inline, static]
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Start the PCD. +-

                                                                                +-Helper function for using the PCD callbacks.

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +-
                                                                                core_if Programming view of DWC_otg controller.
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 1413 of file dwc_otg_cil.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                void cil_pcd_stop ( dwc_otg_core_if_t *  core_if  )  [inline, static]
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Stop the PCD. +-

                                                                                +-Helper function for using the PCD callbacks.

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +-
                                                                                core_if Programming view of DWC_otg controller.
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 1424 of file dwc_otg_cil.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                void cil_pcd_suspend ( dwc_otg_core_if_t *  core_if  )  [inline, static]
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Suspend the PCD. +-

                                                                                +-Helper function for using the PCD callbacks.

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +-
                                                                                core_if Programming view of DWC_otg controller.
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 1435 of file dwc_otg_cil.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                void cil_pcd_resume ( dwc_otg_core_if_t *  core_if  )  [inline, static]
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Resume the PCD. +-

                                                                                +-Helper function for using the PCD callbacks.

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +-
                                                                                core_if Programming view of DWC_otg controller.
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 1446 of file dwc_otg_cil.h.

                                                                                +-

                                                                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__cil__intr_8c-source.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/dwc__otg__cil__intr_8c-source.html 2013-07-26 19:34:40.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,1297 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_cil_intr.c Source File +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                dwc_otg_cil_intr.c

                                                                                Go to the documentation of this file.
                                                                                00001 /* ==========================================================================
+-00002  * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_cil_intr.c $
+-00003  * $Revision: #31 $
+-00004  * $Date: 2011/10/24 $
+-00005  * $Change: 1871286 $
+-00006  *
+-00007  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
+-00008  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
+-00009  * otherwise expressly agreed to in writing between Synopsys and you.
+-00010  *
+-00011  * The Software IS NOT an item of Licensed Software or Licensed Product under
+-00012  * any End User Software License Agreement or Agreement for Licensed Product
+-00013  * with Synopsys or any supplement thereto. You are permitted to use and
+-00014  * redistribute this Software in source and binary forms, with or without
+-00015  * modification, provided that redistributions of source code must retain this
+-00016  * notice. You may not view, use, disclose, copy or distribute this file or
+-00017  * any information contained herein except pursuant to this license grant from
+-00018  * Synopsys. If you do not agree with this notice, including the disclaimer
+-00019  * below, then you are not authorized to use the Software.
+-00020  *
+-00021  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
+-00022  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+-00023  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+-00024  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
+-00025  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+-00026  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+-00027  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+-00028  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+-00029  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+-00030  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+-00031  * DAMAGE.
+-00032  * ========================================================================== */
+-00033 
+-00042 #include "dwc_os.h"
+-00043 #include "dwc_otg_regs.h"
+-00044 #include "dwc_otg_cil.h"
+-00045 #include "dwc_otg_driver.h"
+-00046 #include "dwc_otg_pcd.h"
+-00047 #include "dwc_otg_hcd.h"
+-00048 
+-00049 #ifdef DEBUG
+-00050 inline const char *op_state_str(dwc_otg_core_if_t * core_if)
+-00051 {
+-00052         return (core_if->op_state == A_HOST ? "a_host" :
+-00053                 (core_if->op_state == A_SUSPEND ? "a_suspend" :
+-00054                  (core_if->op_state == A_PERIPHERAL ? "a_peripheral" :
+-00055                   (core_if->op_state == B_PERIPHERAL ? "b_peripheral" :
+-00056                    (core_if->op_state == B_HOST ? "b_host" : "unknown")))));
+-00057 }
+-00058 #endif
+-00059 
+-00064 int32_t dwc_otg_handle_mode_mismatch_intr(dwc_otg_core_if_t * core_if)
+-00065 {
+-00066         gintsts_data_t gintsts;
+-00067         DWC_WARN("Mode Mismatch Interrupt: currently in %s mode\n",
+-00068                  dwc_otg_mode(core_if) ? "Host" : "Device");
+-00069 
+-00070         /* Clear interrupt */
+-00071         gintsts.d32 = 0;
+-00072         gintsts.b.modemismatch = 1;
+-00073         DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
+-00074         return 1;
+-00075 }
+-00076 
+-00084 int32_t dwc_otg_handle_otg_intr(dwc_otg_core_if_t * core_if)
+-00085 {
+-00086         dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
+-00087         gotgint_data_t gotgint;
+-00088         gotgctl_data_t gotgctl;
+-00089         gintmsk_data_t gintmsk;
+-00090         gpwrdn_data_t gpwrdn;
+-00091 
+-00092         gotgint.d32 = DWC_READ_REG32(&global_regs->gotgint);
+-00093         gotgctl.d32 = DWC_READ_REG32(&global_regs->gotgctl);
+-00094         DWC_DEBUGPL(DBG_CIL, "++OTG Interrupt gotgint=%0x [%s]\n", gotgint.d32,
+-00095                     op_state_str(core_if));
+-00096 
+-00097         if (gotgint.b.sesenddet) {
+-00098                 DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: "
+-00099                             "Session End Detected++ (%s)\n",
+-00100                             op_state_str(core_if));
+-00101                 gotgctl.d32 = DWC_READ_REG32(&global_regs->gotgctl);
+-00102 
+-00103                 if (core_if->op_state == B_HOST) {
+-00104                         cil_pcd_start(core_if);
+-00105                         core_if->op_state = B_PERIPHERAL;
+-00106                 } else {
+-00107                         /* If not B_HOST and Device HNP still set. HNP
+-00108                          * Did not succeed!*/
+-00109                         if (gotgctl.b.devhnpen) {
+-00110                                 DWC_DEBUGPL(DBG_ANY, "Session End Detected\n");
+-00111                                 __DWC_ERROR("Device Not Connected/Responding!\n");
+-00112                         }
+-00113 
+-00114                         /* If Session End Detected the B-Cable has
+-00115                          * been disconnected. */
+-00116                         /* Reset PCD and Gadget driver to a
+-00117                          * clean state. */
+-00118                         core_if->lx_state = DWC_OTG_L0;
+-00119                         DWC_SPINUNLOCK(core_if->lock);
+-00120                         cil_pcd_stop(core_if);
+-00121                         DWC_SPINLOCK(core_if->lock);
+-00122 
+-00123                         if (core_if->adp_enable) {
+-00124                                 if (core_if->power_down == 2) {
+-00125                                         gpwrdn.d32 = 0;
+-00126                                         gpwrdn.b.pwrdnswtch = 1;
+-00127                                         DWC_MODIFY_REG32(&core_if->
+-00128                                                          core_global_regs->
+-00129                                                          gpwrdn, gpwrdn.d32, 0);
+-00130                                 }
+-00131 
+-00132                                 gpwrdn.d32 = 0;
+-00133                                 gpwrdn.b.pmuintsel = 1;
+-00134                                 gpwrdn.b.pmuactv = 1;
+-00135                                 DWC_MODIFY_REG32(&core_if->core_global_regs->
+-00136                                                  gpwrdn, 0, gpwrdn.d32);
+-00137 
+-00138                                 dwc_otg_adp_sense_start(core_if);
+-00139                         }
+-00140                 }
+-00141 
+-00142                 gotgctl.d32 = 0;
+-00143                 gotgctl.b.devhnpen = 1;
+-00144                 DWC_MODIFY_REG32(&global_regs->gotgctl, gotgctl.d32, 0);
+-00145         }
+-00146         if (gotgint.b.sesreqsucstschng) {
+-00147                 DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: "
+-00148                             "Session Reqeust Success Status Change++\n");
+-00149                 gotgctl.d32 = DWC_READ_REG32(&global_regs->gotgctl);
+-00150                 if (gotgctl.b.sesreqscs) {
+-00151 
+-00152                         if ((core_if->core_params->phy_type ==
+-00153                              DWC_PHY_TYPE_PARAM_FS) && (core_if->core_params->i2c_enable)) {
+-00154                                 core_if->srp_success = 1;
+-00155                         } else {
+-00156                                 DWC_SPINUNLOCK(core_if->lock);
+-00157                                 cil_pcd_resume(core_if);
+-00158                                 DWC_SPINLOCK(core_if->lock);
+-00159                                 /* Clear Session Request */
+-00160                                 gotgctl.d32 = 0;
+-00161                                 gotgctl.b.sesreq = 1;
+-00162                                 DWC_MODIFY_REG32(&global_regs->gotgctl,
+-00163                                                  gotgctl.d32, 0);
+-00164                         }
+-00165                 }
+-00166         }
+-00167         if (gotgint.b.hstnegsucstschng) {
+-00168                 /* Print statements during the HNP interrupt handling
+-00169                  * can cause it to fail.*/
+-00170                 gotgctl.d32 = DWC_READ_REG32(&global_regs->gotgctl);
+-00171                 if (gotgctl.b.hstnegscs) {
+-00172                         if (dwc_otg_is_host_mode(core_if)) {
+-00173                                 core_if->op_state = B_HOST;
+-00174                                 /*
+-00175                                  * Need to disable SOF interrupt immediately.
+-00176                                  * When switching from device to host, the PCD
+-00177                                  * interrupt handler won't handle the
+-00178                                  * interrupt if host mode is already set. The
+-00179                                  * HCD interrupt handler won't get called if
+-00180                                  * the HCD state is HALT. This means that the
+-00181                                  * interrupt does not get handled and Linux
+-00182                                  * complains loudly.
+-00183                                  */
+-00184                                 gintmsk.d32 = 0;
+-00185                                 gintmsk.b.sofintr = 1;
+-00186                                 DWC_MODIFY_REG32(&global_regs->gintmsk,
+-00187                                                  gintmsk.d32, 0);
+-00188                                 /* Call callback function with spin lock released */
+-00189                                 DWC_SPINUNLOCK(core_if->lock);
+-00190                                 cil_pcd_stop(core_if);
+-00191                                 /*
+-00192                                  * Initialize the Core for Host mode.
+-00193                                  */
+-00194                                 cil_hcd_start(core_if);
+-00195                                 DWC_SPINLOCK(core_if->lock);
+-00196                                 core_if->op_state = B_HOST;
+-00197                         }
+-00198                 } else {
+-00199                         gotgctl.d32 = 0;
+-00200                         gotgctl.b.hnpreq = 1;
+-00201                         gotgctl.b.devhnpen = 1;
+-00202                         DWC_MODIFY_REG32(&global_regs->gotgctl, gotgctl.d32, 0);
+-00203                         DWC_DEBUGPL(DBG_ANY, "HNP Failed\n");
+-00204                         __DWC_ERROR("Device Not Connected/Responding\n");
+-00205                 }
+-00206         }
+-00207         if (gotgint.b.hstnegdet) {
+-00208                 /* The disconnect interrupt is set at the same time as
+-00209                  * Host Negotiation Detected.  During the mode
+-00210                  * switch all interrupts are cleared so the disconnect
+-00211                  * interrupt handler will not get executed.
+-00212                  */
+-00213                 DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: "
+-00214                             "Host Negotiation Detected++ (%s)\n",
+-00215                             (dwc_otg_is_host_mode(core_if) ? "Host" :
+-00216                              "Device"));
+-00217                 if (dwc_otg_is_device_mode(core_if)) {
+-00218                         DWC_DEBUGPL(DBG_ANY, "a_suspend->a_peripheral (%d)\n",
+-00219                                     core_if->op_state);
+-00220                         DWC_SPINUNLOCK(core_if->lock);
+-00221                         cil_hcd_disconnect(core_if);
+-00222                         cil_pcd_start(core_if);
+-00223                         DWC_SPINLOCK(core_if->lock);
+-00224                         core_if->op_state = A_PERIPHERAL;
+-00225                 } else {
+-00226                         /*
+-00227                          * Need to disable SOF interrupt immediately. When
+-00228                          * switching from device to host, the PCD interrupt
+-00229                          * handler won't handle the interrupt if host mode is
+-00230                          * already set. The HCD interrupt handler won't get
+-00231                          * called if the HCD state is HALT. This means that
+-00232                          * the interrupt does not get handled and Linux
+-00233                          * complains loudly.
+-00234                          */
+-00235                         gintmsk.d32 = 0;
+-00236                         gintmsk.b.sofintr = 1;
+-00237                         DWC_MODIFY_REG32(&global_regs->gintmsk, gintmsk.d32, 0);
+-00238                         DWC_SPINUNLOCK(core_if->lock);
+-00239                         cil_pcd_stop(core_if);
+-00240                         cil_hcd_start(core_if);
+-00241                         DWC_SPINLOCK(core_if->lock);
+-00242                         core_if->op_state = A_HOST;
+-00243                 }
+-00244         }
+-00245         if (gotgint.b.adevtoutchng) {
+-00246                 DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: "
+-00247                             "A-Device Timeout Change++\n");
+-00248         }
+-00249         if (gotgint.b.debdone) {
+-00250                 DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: " "Debounce Done++\n");
+-00251         }
+-00252 
+-00253         /* Clear GOTGINT */
+-00254         DWC_WRITE_REG32(&core_if->core_global_regs->gotgint, gotgint.d32);
+-00255 
+-00256         return 1;
+-00257 }
+-00258 
+-00259 void w_conn_id_status_change(void *p)
+-00260 {
+-00261         dwc_otg_core_if_t *core_if = p;
+-00262         uint32_t count = 0;
+-00263         gotgctl_data_t gotgctl = {.d32 = 0 };
+-00264 
+-00265         gotgctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->gotgctl);
+-00266         DWC_DEBUGPL(DBG_CIL, "gotgctl=%0x\n", gotgctl.d32);
+-00267         DWC_DEBUGPL(DBG_CIL, "gotgctl.b.conidsts=%d\n", gotgctl.b.conidsts);
+-00268 
+-00269         /* B-Device connector (Device Mode) */
+-00270         if (gotgctl.b.conidsts) {
+-00271                 /* Wait for switch to device mode. */
+-00272                 while (!dwc_otg_is_device_mode(core_if)) {
+-00273                         DWC_PRINTF("Waiting for Peripheral Mode, Mode=%s\n",
+-00274                                    (dwc_otg_is_host_mode(core_if) ? "Host" :
+-00275                                     "Peripheral"));
+-00276                         dwc_mdelay(100);
+-00277                         if (++count > 10000)
+-00278                                 break;
+-00279                 }
+-00280                 DWC_ASSERT(++count < 10000,
+-00281                            "Connection id status change timed out");
+-00282                 core_if->op_state = B_PERIPHERAL;
+-00283                 dwc_otg_core_init(core_if);
+-00284                 dwc_otg_enable_global_interrupts(core_if);
+-00285                 cil_pcd_start(core_if);
+-00286         } else {
+-00287                 /* A-Device connector (Host Mode) */
+-00288                 while (!dwc_otg_is_host_mode(core_if)) {
+-00289                         DWC_PRINTF("Waiting for Host Mode, Mode=%s\n",
+-00290                                    (dwc_otg_is_host_mode(core_if) ? "Host" :
+-00291                                     "Peripheral"));
+-00292                         dwc_mdelay(100);
+-00293                         if (++count > 10000)
+-00294                                 break;
+-00295                 }
+-00296                 DWC_ASSERT(++count < 10000,
+-00297                            "Connection id status change timed out");
+-00298                 core_if->op_state = A_HOST;
+-00299                 /*
+-00300                  * Initialize the Core for Host mode.
+-00301                  */
+-00302                 dwc_otg_core_init(core_if);
+-00303                 dwc_otg_enable_global_interrupts(core_if);
+-00304                 cil_hcd_start(core_if);
+-00305         }
+-00306 }
+-00307 
+-00319 int32_t dwc_otg_handle_conn_id_status_change_intr(dwc_otg_core_if_t * core_if)
+-00320 {
+-00321 
+-00322         /*
+-00323          * Need to disable SOF interrupt immediately. If switching from device
+-00324          * to host, the PCD interrupt handler won't handle the interrupt if
+-00325          * host mode is already set. The HCD interrupt handler won't get
+-00326          * called if the HCD state is HALT. This means that the interrupt does
+-00327          * not get handled and Linux complains loudly.
+-00328          */
+-00329         gintmsk_data_t gintmsk = {.d32 = 0 };
+-00330         gintsts_data_t gintsts = {.d32 = 0 };
+-00331 
+-00332         gintmsk.b.sofintr = 1;
+-00333         DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, gintmsk.d32, 0);
+-00334 
+-00335         DWC_DEBUGPL(DBG_CIL,
+-00336                     " ++Connector ID Status Change Interrupt++  (%s)\n",
+-00337                     (dwc_otg_is_host_mode(core_if) ? "Host" : "Device"));
+-00338         
+-00339         DWC_SPINUNLOCK(core_if->lock);
+-00340 
+-00341         /*
+-00342          * Need to schedule a work, as there are possible DELAY function calls
+-00343          * Release lock before scheduling workq as it holds spinlock during scheduling
+-00344          */
+-00345 
+-00346         DWC_WORKQ_SCHEDULE(core_if->wq_otg, w_conn_id_status_change,
+-00347                            core_if, "connection id status change");
+-00348         DWC_SPINLOCK(core_if->lock);
+-00349 
+-00350         /* Set flag and clear interrupt */
+-00351         gintsts.b.conidstschng = 1;
+-00352         DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
+-00353 
+-00354         return 1;
+-00355 }
+-00356 
+-00366 int32_t dwc_otg_handle_session_req_intr(dwc_otg_core_if_t * core_if)
+-00367 {
+-00368         gintsts_data_t gintsts;
+-00369 
+-00370 #ifndef DWC_HOST_ONLY
+-00371         DWC_DEBUGPL(DBG_ANY, "++Session Request Interrupt++\n");
+-00372 
+-00373         if (dwc_otg_is_device_mode(core_if)) {
+-00374                 DWC_PRINTF("SRP: Device mode\n");
+-00375         } else {
+-00376                 hprt0_data_t hprt0;
+-00377                 DWC_PRINTF("SRP: Host mode\n");
+-00378 
+-00379                 /* Turn on the port power bit. */
+-00380                 hprt0.d32 = dwc_otg_read_hprt0(core_if);
+-00381                 hprt0.b.prtpwr = 1;
+-00382                 DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
+-00383 
+-00384                 /* Start the Connection timer. So a message can be displayed
+-00385                  * if connect does not occur within 10 seconds. */
+-00386                 cil_hcd_session_start(core_if);
+-00387         }
+-00388 #endif
+-00389 
+-00390         /* Clear interrupt */
+-00391         gintsts.d32 = 0;
+-00392         gintsts.b.sessreqintr = 1;
+-00393         DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
+-00394 
+-00395         return 1;
+-00396 }
+-00397 
+-00398 void w_wakeup_detected(void *p)
+-00399 {
+-00400         dwc_otg_core_if_t *core_if = (dwc_otg_core_if_t *) p;
+-00401         /*
+-00402          * Clear the Resume after 70ms. (Need 20 ms minimum. Use 70 ms
+-00403          * so that OPT tests pass with all PHYs).
+-00404          */
+-00405         hprt0_data_t hprt0 = {.d32 = 0 };
+-00406 #if 0
+-00407         pcgcctl_data_t pcgcctl = {.d32 = 0 };
+-00408         /* Restart the Phy Clock */
+-00409         pcgcctl.b.stoppclk = 1;
+-00410         DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32, 0);
+-00411         dwc_udelay(10);
+-00412 #endif //0
+-00413         hprt0.d32 = dwc_otg_read_hprt0(core_if);
+-00414         DWC_DEBUGPL(DBG_ANY, "Resume: HPRT0=%0x\n", hprt0.d32);
+-00415 //      dwc_mdelay(70);
+-00416         hprt0.b.prtres = 0;     /* Resume */
+-00417         DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
+-00418         DWC_DEBUGPL(DBG_ANY, "Clear Resume: HPRT0=%0x\n",
+-00419                     DWC_READ_REG32(core_if->host_if->hprt0));
+-00420 
+-00421         cil_hcd_resume(core_if);
+-00422 
+-00424         core_if->lx_state = DWC_OTG_L0;
+-00425 }
+-00426 
+-00434 int32_t dwc_otg_handle_wakeup_detected_intr(dwc_otg_core_if_t * core_if)
+-00435 {
+-00436         gintsts_data_t gintsts;
+-00437 
+-00438         DWC_DEBUGPL(DBG_ANY,
+-00439                     "++Resume and Remote Wakeup Detected Interrupt++\n");
+-00440 
+-00441         DWC_PRINTF("%s lxstate = %d\n", __func__, core_if->lx_state);
+-00442 
+-00443         if (dwc_otg_is_device_mode(core_if)) {
+-00444                 dctl_data_t dctl = {.d32 = 0 };
+-00445                 DWC_DEBUGPL(DBG_PCD, "DSTS=0x%0x\n",
+-00446                             DWC_READ_REG32(&core_if->dev_if->
+-00447                                            dev_global_regs->dsts));
+-00448                 if (core_if->lx_state == DWC_OTG_L2) {
+-00449 #ifdef PARTIAL_POWER_DOWN
+-00450                         if (core_if->hwcfg4.b.power_optimiz) {
+-00451                                 pcgcctl_data_t power = {.d32 = 0 };
+-00452 
+-00453                                 power.d32 = DWC_READ_REG32(core_if->pcgcctl);
+-00454                                 DWC_DEBUGPL(DBG_CIL, "PCGCCTL=%0x\n",
+-00455                                             power.d32);
+-00456 
+-00457                                 power.b.stoppclk = 0;
+-00458                                 DWC_WRITE_REG32(core_if->pcgcctl, power.d32);
+-00459 
+-00460                                 power.b.pwrclmp = 0;
+-00461                                 DWC_WRITE_REG32(core_if->pcgcctl, power.d32);
+-00462 
+-00463                                 power.b.rstpdwnmodule = 0;
+-00464                                 DWC_WRITE_REG32(core_if->pcgcctl, power.d32);
+-00465                         }
+-00466 #endif
+-00467                         /* Clear the Remote Wakeup Signaling */
+-00468                         dctl.b.rmtwkupsig = 1;
+-00469                         DWC_MODIFY_REG32(&core_if->dev_if->
+-00470                                          dev_global_regs->dctl, dctl.d32, 0);
+-00471 
+-00472                         DWC_SPINUNLOCK(core_if->lock);
+-00473                         if (core_if->pcd_cb && core_if->pcd_cb->resume_wakeup) {
+-00474                                 core_if->pcd_cb->resume_wakeup(core_if->pcd_cb->p);
+-00475                         }
+-00476                         DWC_SPINLOCK(core_if->lock);
+-00477                 } else {
+-00478                         glpmcfg_data_t lpmcfg;
+-00479                         lpmcfg.d32 =
+-00480                             DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
+-00481                         lpmcfg.b.hird_thres &= (~(1 << 4));
+-00482                         DWC_WRITE_REG32(&core_if->core_global_regs->glpmcfg,
+-00483                                         lpmcfg.d32);
+-00484                 }
+-00486                 core_if->lx_state = DWC_OTG_L0;
+-00487         } else {
+-00488                 if (core_if->lx_state != DWC_OTG_L1) {
+-00489                         pcgcctl_data_t pcgcctl = {.d32 = 0 };
+-00490 
+-00491                         /* Restart the Phy Clock */
+-00492                         pcgcctl.b.stoppclk = 1;
+-00493                         DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32, 0);
+-00494                         DWC_TIMER_SCHEDULE(core_if->wkp_timer, 71);
+-00495                 } else {
+-00497                         core_if->lx_state = DWC_OTG_L0;
+-00498                 }
+-00499         }
+-00500 
+-00501         /* Clear interrupt */
+-00502         gintsts.d32 = 0;
+-00503         gintsts.b.wkupintr = 1;
+-00504         DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
+-00505 
+-00506         return 1;
+-00507 }
+-00508 
+-00513 static int32_t dwc_otg_handle_pwrdn_disconnect_intr(dwc_otg_core_if_t *core_if)
+-00514 {
+-00515         gpwrdn_data_t gpwrdn = { .d32 = 0 };
+-00516         gpwrdn_data_t gpwrdn_temp = { .d32 = 0 };
+-00517         gpwrdn_temp.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
+-00518 
+-00519         DWC_PRINTF("%s called\n", __FUNCTION__);
+-00520 
+-00521         if (!core_if->hibernation_suspend) {
+-00522                 DWC_PRINTF("Already exited from Hibernation\n");
+-00523                 return 1;
+-00524         }
+-00525 
+-00526         /* Switch on the voltage to the core */
+-00527         gpwrdn.b.pwrdnswtch = 1;
+-00528         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
+-00529         dwc_udelay(10);
+-00530 
+-00531         /* Reset the core */
+-00532         gpwrdn.d32 = 0;
+-00533         gpwrdn.b.pwrdnrstn = 1;
+-00534         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
+-00535         dwc_udelay(10);
+-00536 
+-00537         /* Disable power clamps*/
+-00538         gpwrdn.d32 = 0;
+-00539         gpwrdn.b.pwrdnclmp = 1;
+-00540         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
+-00541 
+-00542         /* Remove reset the core signal */
+-00543         gpwrdn.d32 = 0;
+-00544         gpwrdn.b.pwrdnrstn = 1;
+-00545         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
+-00546         dwc_udelay(10);
+-00547 
+-00548         /* Disable PMU interrupt */
+-00549         gpwrdn.d32 = 0;
+-00550         gpwrdn.b.pmuintsel = 1;
+-00551         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
+-00552 
+-00553         core_if->hibernation_suspend = 0;
+-00554 
+-00555         /* Disable PMU */
+-00556         gpwrdn.d32 = 0;
+-00557         gpwrdn.b.pmuactv = 1;
+-00558         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
+-00559         dwc_udelay(10);
+-00560 
+-00561         if (gpwrdn_temp.b.idsts) {
+-00562                 core_if->op_state = B_PERIPHERAL;
+-00563                 dwc_otg_core_init(core_if);
+-00564                 dwc_otg_enable_global_interrupts(core_if);
+-00565                 cil_pcd_start(core_if);
+-00566         } else {
+-00567                 core_if->op_state = A_HOST;
+-00568                 dwc_otg_core_init(core_if);
+-00569                 dwc_otg_enable_global_interrupts(core_if);
+-00570                 cil_hcd_start(core_if);
+-00571         }
+-00572 
+-00573         return 1;
+-00574 }
+-00575 
+-00580 static int32_t dwc_otg_handle_pwrdn_wakeup_detected_intr(dwc_otg_core_if_t * core_if)
+-00581 {
+-00582         gpwrdn_data_t gpwrdn = {.d32 = 0 };
+-00583         DWC_DEBUGPL(DBG_ANY,
+-00584                     "++Powerdown Remote Wakeup Detected Interrupt++\n");
+-00585 
+-00586         if (!core_if->hibernation_suspend) {
+-00587                 DWC_PRINTF("Already exited from Hibernation\n");
+-00588                 return 1;
+-00589         }
+-00590 
+-00591         gpwrdn.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
+-00592         if (gpwrdn.b.idsts) {   // Device Mode
+-00593                 if ((core_if->power_down == 2)
+-00594                     && (core_if->hibernation_suspend == 1)) {
+-00595                         dwc_otg_device_hibernation_restore(core_if, 0, 0);
+-00596                 }
+-00597         } else {
+-00598                 if ((core_if->power_down == 2)
+-00599                     && (core_if->hibernation_suspend == 1)) {
+-00600                         dwc_otg_host_hibernation_restore(core_if, 1, 0);
+-00601                 }
+-00602         }
+-00603         return 1;
+-00604 }
+-00605 
+-00606 static int32_t dwc_otg_handle_pwrdn_idsts_change(dwc_otg_device_t *otg_dev)
+-00607 {
+-00608         gpwrdn_data_t gpwrdn = {.d32 = 0 };
+-00609         gpwrdn_data_t gpwrdn_temp = {.d32 = 0 };
+-00610         dwc_otg_core_if_t *core_if = otg_dev->core_if;
+-00611 
+-00612         DWC_DEBUGPL(DBG_ANY, "%s called\n", __FUNCTION__);
+-00613         gpwrdn_temp.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
+-00614         if (core_if->power_down == 2)
+-00615         {               
+-00616                 if (!core_if->hibernation_suspend) {
+-00617                         DWC_PRINTF("Already exited from Hibernation\n");
+-00618                         return 1;
+-00619                 }
+-00620                 DWC_DEBUGPL(DBG_ANY, "Exit from hibernation on ID sts change\n");
+-00621                 /* Switch on the voltage to the core */
+-00622                 gpwrdn.b.pwrdnswtch = 1;
+-00623                 DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
+-00624                 dwc_udelay(10);
+-00625 
+-00626                 /* Reset the core */
+-00627                 gpwrdn.d32 = 0;
+-00628                 gpwrdn.b.pwrdnrstn = 1;
+-00629                 DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
+-00630                 dwc_udelay(10);
+-00631 
+-00632                 /* Disable power clamps */
+-00633                 gpwrdn.d32 = 0;
+-00634                 gpwrdn.b.pwrdnclmp = 1;
+-00635                 DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
+-00636 
+-00637                 /* Remove reset the core signal */
+-00638                 gpwrdn.d32 = 0;
+-00639                 gpwrdn.b.pwrdnrstn = 1;
+-00640                 DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
+-00641                 dwc_udelay(10);
+-00642 
+-00643                 /* Disable PMU interrupt */
+-00644                 gpwrdn.d32 = 0;
+-00645                 gpwrdn.b.pmuintsel = 1;
+-00646                 DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
+-00647 
+-00648                 /*Indicates that we are exiting from hibernation */
+-00649                 core_if->hibernation_suspend = 0;
+-00650 
+-00651                 /* Disable PMU */
+-00652                 gpwrdn.d32 = 0;
+-00653                 gpwrdn.b.pmuactv = 1;
+-00654                 DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
+-00655                 dwc_udelay(10);
+-00656 
+-00657                 gpwrdn.d32 = core_if->gr_backup->gpwrdn_local;
+-00658                 if (gpwrdn.b.dis_vbus == 1) {
+-00659                         gpwrdn.d32 = 0;
+-00660                         gpwrdn.b.dis_vbus = 1;
+-00661                         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
+-00662                 }
+-00663 
+-00664                 if (gpwrdn_temp.b.idsts) {
+-00665                         core_if->op_state = B_PERIPHERAL;
+-00666                         dwc_otg_core_init(core_if);
+-00667                         dwc_otg_enable_global_interrupts(core_if);
+-00668                         cil_pcd_start(core_if);
+-00669                 } else {
+-00670                         core_if->op_state = A_HOST;
+-00671                         dwc_otg_core_init(core_if);
+-00672                         dwc_otg_enable_global_interrupts(core_if);
+-00673                         cil_hcd_start(core_if);
+-00674                 }
+-00675         }
+-00676 
+-00677         if (core_if->adp_enable)
+-00678         {
+-00679                 uint8_t is_host = 0;
+-00680                 DWC_SPINUNLOCK(core_if->lock);
+-00681                 /* Change the core_if's lock to hcd/pcd lock depend on mode? */
+-00682 #ifndef DWC_HOST_ONLY           
+-00683                 if (gpwrdn_temp.b.idsts)
+-00684                         core_if->lock = otg_dev->pcd->lock;
+-00685 #endif
+-00686 #ifndef DWC_DEVICE_ONLY
+-00687                 if (!gpwrdn_temp.b.idsts) {
+-00688                                 core_if->lock = otg_dev->hcd->lock;     
+-00689                                 is_host = 1;
+-00690                 }
+-00691 #endif
+-00692                 DWC_PRINTF("RESTART ADP\n");
+-00693                 if (core_if->adp.probe_enabled)         
+-00694                         dwc_otg_adp_probe_stop(core_if);
+-00695                 if (core_if->adp.sense_enabled)         
+-00696                         dwc_otg_adp_sense_stop(core_if);
+-00697                 if (core_if->adp.sense_timer_started)           
+-00698                         DWC_TIMER_CANCEL(core_if->adp.sense_timer);
+-00699                 if (core_if->adp.vbuson_timer_started)          
+-00700                         DWC_TIMER_CANCEL(core_if->adp.vbuson_timer);
+-00701                 core_if->adp.probe_timer_values[0] = -1;
+-00702                 core_if->adp.probe_timer_values[1] = -1;
+-00703                 core_if->adp.sense_timer_started = 0;
+-00704                 core_if->adp.vbuson_timer_started = 0;
+-00705                 core_if->adp.probe_counter = 0;
+-00706                 core_if->adp.gpwrdn = 0;
+-00707                 
+-00708                 /* Disable PMU and restart ADP */
+-00709                 gpwrdn_temp.d32 = 0;
+-00710                 gpwrdn_temp.b.pmuactv = 1;
+-00711                 gpwrdn_temp.b.pmuintsel = 1;
+-00712                 DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
+-00713                 DWC_PRINTF("Check point 1\n");
+-00714                 dwc_mdelay(110);
+-00715                 dwc_otg_adp_start(core_if, is_host);
+-00716                 DWC_SPINLOCK(core_if->lock);
+-00717         }
+-00718         
+-00719 
+-00720         return 1;
+-00721 }
+-00722 
+-00723 static int32_t dwc_otg_handle_pwrdn_session_change(dwc_otg_core_if_t * core_if)
+-00724 {
+-00725         gpwrdn_data_t gpwrdn = {.d32 = 0 };
+-00726         int32_t otg_cap_param = core_if->core_params->otg_cap;
+-00727         DWC_DEBUGPL(DBG_ANY, "%s called\n", __FUNCTION__);
+-00728 
+-00729         gpwrdn.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
+-00730         if (core_if->power_down == 2) {
+-00731                 if (!core_if->hibernation_suspend) {
+-00732                         DWC_PRINTF("Already exited from Hibernation\n");
+-00733                         return 1;
+-00734                 }
+-00735 
+-00736                 if ((otg_cap_param != DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE ||
+-00737                          otg_cap_param != DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE) &&
+-00738                         gpwrdn.b.bsessvld == 0) {
+-00739                         /* Save gpwrdn register for further usage if stschng interrupt */
+-00740                         core_if->gr_backup->gpwrdn_local =
+-00741                                 DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
+-00742                         /*Exit from ISR and wait for stschng interrupt with bsessvld = 1 */
+-00743                         return 1;
+-00744                 }
+-00745 
+-00746                 /* Switch on the voltage to the core */
+-00747                 gpwrdn.d32 = 0;
+-00748                 gpwrdn.b.pwrdnswtch = 1;
+-00749                 DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
+-00750                 dwc_udelay(10);
+-00751 
+-00752                 /* Reset the core */
+-00753                 gpwrdn.d32 = 0;
+-00754                 gpwrdn.b.pwrdnrstn = 1;
+-00755                 DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
+-00756                 dwc_udelay(10);
+-00757 
+-00758                 /* Disable power clamps */
+-00759                 gpwrdn.d32 = 0;
+-00760                 gpwrdn.b.pwrdnclmp = 1;
+-00761                 DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
+-00762 
+-00763                 /* Remove reset the core signal */
+-00764                 gpwrdn.d32 = 0;
+-00765                 gpwrdn.b.pwrdnrstn = 1;
+-00766                 DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
+-00767                 dwc_udelay(10);
+-00768 
+-00769                 /* Disable PMU interrupt */
+-00770                 gpwrdn.d32 = 0;
+-00771                 gpwrdn.b.pmuintsel = 1;
+-00772                 DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
+-00773                 dwc_udelay(10);
+-00774 
+-00775                 /*Indicates that we are exiting from hibernation */
+-00776                 core_if->hibernation_suspend = 0;
+-00777 
+-00778                 /* Disable PMU */
+-00779                 gpwrdn.d32 = 0;
+-00780                 gpwrdn.b.pmuactv = 1;
+-00781                 DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
+-00782                 dwc_udelay(10);
+-00783 
+-00784                 core_if->op_state = B_PERIPHERAL;
+-00785                 dwc_otg_core_init(core_if);
+-00786                 dwc_otg_enable_global_interrupts(core_if);
+-00787                 cil_pcd_start(core_if);
+-00788 
+-00789                 if (otg_cap_param == DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE ||
+-00790                         otg_cap_param == DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE) {
+-00791                         /*
+-00792                          * Initiate SRP after initial ADP probe.
+-00793                          */
+-00794                         dwc_otg_initiate_srp(core_if);  
+-00795                 }
+-00796         }
+-00797 
+-00798         return 1;
+-00799 }
+-00804 static uint32_t dwc_otg_handle_pwrdn_stschng_intr(dwc_otg_device_t *otg_dev)
+-00805 {
+-00806         int retval;
+-00807         gpwrdn_data_t gpwrdn = {.d32 = 0 };
+-00808         gpwrdn_data_t gpwrdn_temp = {.d32 = 0 };
+-00809         dwc_otg_core_if_t *core_if = otg_dev->core_if;
+-00810 
+-00811         DWC_PRINTF("%s called\n", __FUNCTION__);
+-00812         
+-00813         if (core_if->power_down == 2) {
+-00814                 if (core_if->hibernation_suspend <= 0) {
+-00815                         DWC_PRINTF("Already exited from Hibernation\n");
+-00816                         return 1;
+-00817                 } else
+-00818                         gpwrdn_temp.d32 = core_if->gr_backup->gpwrdn_local;
+-00819 
+-00820         } else {
+-00821                 gpwrdn_temp.d32 = core_if->adp.gpwrdn;
+-00822         }
+-00823 
+-00824         gpwrdn.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
+-00825         
+-00826         if (gpwrdn.b.idsts ^ gpwrdn_temp.b.idsts) {
+-00827                 retval = dwc_otg_handle_pwrdn_idsts_change(otg_dev);
+-00828         } else if (gpwrdn.b.bsessvld ^ gpwrdn_temp.b.bsessvld) {
+-00829                 retval = dwc_otg_handle_pwrdn_session_change(core_if);
+-00830         }
+-00831 
+-00832         return retval;
+-00833 }
+-00834 
+-00839 static int32_t dwc_otg_handle_pwrdn_srp_intr(dwc_otg_core_if_t * core_if)
+-00840 {
+-00841         gpwrdn_data_t gpwrdn = {.d32 = 0 };
+-00842 
+-00843         DWC_PRINTF("%s called\n", __FUNCTION__);
+-00844 
+-00845         if (!core_if->hibernation_suspend) {
+-00846                 DWC_PRINTF("Already exited from Hibernation\n");
+-00847                 return 1;
+-00848         }
+-00849 #ifdef DWC_DEV_SRPCAP
+-00850         if (core_if->pwron_timer_started) {
+-00851                 core_if->pwron_timer_started = 0;
+-00852                 DWC_TIMER_CANCEL(core_if->pwron_timer);
+-00853         }
+-00854 #endif
+-00855 
+-00856         /* Switch on the voltage to the core */
+-00857         gpwrdn.b.pwrdnswtch = 1;
+-00858         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
+-00859         dwc_udelay(10);
+-00860 
+-00861         /* Reset the core */
+-00862         gpwrdn.d32 = 0;
+-00863         gpwrdn.b.pwrdnrstn = 1;
+-00864         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
+-00865         dwc_udelay(10);
+-00866 
+-00867         /* Disable power clamps */
+-00868         gpwrdn.d32 = 0;
+-00869         gpwrdn.b.pwrdnclmp = 1;
+-00870         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
+-00871 
+-00872         /* Remove reset the core signal */
+-00873         gpwrdn.d32 = 0;
+-00874         gpwrdn.b.pwrdnrstn = 1;
+-00875         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
+-00876         dwc_udelay(10);
+-00877 
+-00878         /* Disable PMU interrupt */
+-00879         gpwrdn.d32 = 0;
+-00880         gpwrdn.b.pmuintsel = 1;
+-00881         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
+-00882 
+-00883         /* Indicates that we are exiting from hibernation */
+-00884         core_if->hibernation_suspend = 0;
+-00885 
+-00886         /* Disable PMU */
+-00887         gpwrdn.d32 = 0;
+-00888         gpwrdn.b.pmuactv = 1;
+-00889         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
+-00890         dwc_udelay(10);
+-00891 
+-00892         /* Programm Disable VBUS to 0 */
+-00893         gpwrdn.d32 = 0;
+-00894         gpwrdn.b.dis_vbus = 1;
+-00895         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
+-00896 
+-00897         /*Initialize the core as Host */
+-00898         core_if->op_state = A_HOST;
+-00899         dwc_otg_core_init(core_if);
+-00900         dwc_otg_enable_global_interrupts(core_if);
+-00901         cil_hcd_start(core_if);
+-00902 
+-00903         return 1;
+-00904 }
+-00905 
+-00908 int32_t dwc_otg_handle_restore_done_intr(dwc_otg_core_if_t * core_if)
+-00909 {
+-00910         pcgcctl_data_t pcgcctl;
+-00911         DWC_DEBUGPL(DBG_ANY, "++Restore Done Interrupt++\n");
+-00912 
+-00913         //TODO De-assert restore signal. 8.a
+-00914         pcgcctl.d32 = DWC_READ_REG32(core_if->pcgcctl);
+-00915         if (pcgcctl.b.restoremode == 1) {
+-00916                 gintmsk_data_t gintmsk = {.d32 = 0 };
+-00917                 /*
+-00918                  * If restore mode is Remote Wakeup,
+-00919                  * unmask Remote Wakeup interrupt.
+-00920                  */
+-00921                 gintmsk.b.wkupintr = 1;
+-00922                 DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk,
+-00923                                  0, gintmsk.d32);
+-00924         }
+-00925 
+-00926         return 1;
+-00927 }
+-00928 
+-00933 int32_t dwc_otg_handle_disconnect_intr(dwc_otg_core_if_t * core_if)
+-00934 {
+-00935         gintsts_data_t gintsts;
+-00936 
+-00937         DWC_DEBUGPL(DBG_ANY, "++Disconnect Detected Interrupt++ (%s) %s\n",
+-00938                     (dwc_otg_is_host_mode(core_if) ? "Host" : "Device"),
+-00939                     op_state_str(core_if));
+-00940 
+-00942 #ifndef DWC_HOST_ONLY
+-00943         if (core_if->op_state == B_HOST) {
+-00944                 /* If in device mode Disconnect and stop the HCD, then
+-00945                  * start the PCD. */
+-00946                 DWC_SPINUNLOCK(core_if->lock);
+-00947                 cil_hcd_disconnect(core_if);
+-00948                 cil_pcd_start(core_if);
+-00949                 DWC_SPINLOCK(core_if->lock);
+-00950                 core_if->op_state = B_PERIPHERAL;
+-00951         } else if (dwc_otg_is_device_mode(core_if)) {
+-00952                 gotgctl_data_t gotgctl = {.d32 = 0 };
+-00953                 gotgctl.d32 =
+-00954                     DWC_READ_REG32(&core_if->core_global_regs->gotgctl);
+-00955                 if (gotgctl.b.hstsethnpen == 1) {
+-00956                         /* Do nothing, if HNP in process the OTG
+-00957                          * interrupt "Host Negotiation Detected"
+-00958                          * interrupt will do the mode switch.
+-00959                          */
+-00960                 } else if (gotgctl.b.devhnpen == 0) {
+-00961                         /* If in device mode Disconnect and stop the HCD, then
+-00962                          * start the PCD. */
+-00963                         DWC_SPINUNLOCK(core_if->lock);
+-00964                         cil_hcd_disconnect(core_if);
+-00965                         cil_pcd_start(core_if);
+-00966                         DWC_SPINLOCK(core_if->lock);
+-00967                         core_if->op_state = B_PERIPHERAL;
+-00968                 } else {
+-00969                         DWC_DEBUGPL(DBG_ANY, "!a_peripheral && !devhnpen\n");
+-00970                 }
+-00971         } else {
+-00972                 if (core_if->op_state == A_HOST) {
+-00973                         /* A-Cable still connected but device disconnected. */
+-00974                         cil_hcd_disconnect(core_if);
+-00975                         if (core_if->adp_enable) {
+-00976                                 gpwrdn_data_t gpwrdn = { .d32 = 0 };
+-00977                                 cil_hcd_stop(core_if);
+-00978                                 /* Enable Power Down Logic */
+-00979                                 gpwrdn.b.pmuintsel = 1;
+-00980                                 gpwrdn.b.pmuactv = 1;
+-00981                                 DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
+-00982                                 dwc_otg_adp_probe_start(core_if);
+-00983 
+-00984                                 /* Power off the core */
+-00985                                 if (core_if->power_down == 2) {
+-00986                                         gpwrdn.d32 = 0;
+-00987                                         gpwrdn.b.pwrdnswtch = 1;
+-00988                                         DWC_MODIFY_REG32(&core_if->
+-00989                                                          core_global_regs->
+-00990                                                          gpwrdn, gpwrdn.d32, 0);
+-00991                                 }
+-00992                         }
+-00993                 }
+-00994         }
+-00995 #endif
+-00996         /* Change to L3(OFF) state */
+-00997         core_if->lx_state = DWC_OTG_L3;
+-00998 
+-00999         gintsts.d32 = 0;
+-01000         gintsts.b.disconnect = 1;
+-01001         DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
+-01002         return 1;
+-01003 }
+-01004 
+-01015 int32_t dwc_otg_handle_usb_suspend_intr(dwc_otg_core_if_t * core_if)
+-01016 {
+-01017         dsts_data_t dsts;
+-01018         gintsts_data_t gintsts;
+-01019         dcfg_data_t dcfg;
+-01020 
+-01021         DWC_DEBUGPL(DBG_ANY, "USB SUSPEND\n");
+-01022 
+-01023         if (dwc_otg_is_device_mode(core_if)) {
+-01024                 /* Check the Device status register to determine if the Suspend
+-01025                  * state is active. */
+-01026                 dsts.d32 =
+-01027                     DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts);
+-01028                 DWC_DEBUGPL(DBG_PCD, "DSTS=0x%0x\n", dsts.d32);
+-01029                 DWC_DEBUGPL(DBG_PCD, "DSTS.Suspend Status=%d "
+-01030                             "HWCFG4.power Optimize=%d\n",
+-01031                             dsts.b.suspsts, core_if->hwcfg4.b.power_optimiz);
+-01032 
+-01033 #ifdef PARTIAL_POWER_DOWN
+-01034 
+-01036                 if (dsts.b.suspsts && core_if->hwcfg4.b.power_optimiz) {
+-01037                         pcgcctl_data_t power = {.d32 = 0 };
+-01038                         DWC_DEBUGPL(DBG_CIL, "suspend\n");
+-01039 
+-01040                         power.b.pwrclmp = 1;
+-01041                         DWC_WRITE_REG32(core_if->pcgcctl, power.d32);
+-01042 
+-01043                         power.b.rstpdwnmodule = 1;
+-01044                         DWC_MODIFY_REG32(core_if->pcgcctl, 0, power.d32);
+-01045 
+-01046                         power.b.stoppclk = 1;
+-01047                         DWC_MODIFY_REG32(core_if->pcgcctl, 0, power.d32);
+-01048 
+-01049                 } else {
+-01050                         DWC_DEBUGPL(DBG_ANY, "disconnect?\n");
+-01051                 }
+-01052 #endif
+-01053                 /* PCD callback for suspend. Release the lock inside of callback function */
+-01054                 cil_pcd_suspend(core_if);
+-01055                 if (core_if->power_down == 2)
+-01056                 {
+-01057                         dcfg.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg);
+-01058                         DWC_DEBUGPL(DBG_ANY,"lx_state = %08x\n",core_if->lx_state);
+-01059                         DWC_DEBUGPL(DBG_ANY," device address = %08d\n",dcfg.b.devaddr);
+-01060 
+-01061                         if (core_if->lx_state != DWC_OTG_L3 && dcfg.b.devaddr) {
+-01062                                 pcgcctl_data_t pcgcctl = {.d32 = 0 };
+-01063                                 gpwrdn_data_t gpwrdn = {.d32 = 0 };
+-01064                                 gusbcfg_data_t gusbcfg = {.d32 = 0 };
+-01065 
+-01066                                 /* Change to L2(suspend) state */
+-01067                                 core_if->lx_state = DWC_OTG_L2;
+-01068 
+-01069                                 /* Clear interrupt in gintsts */
+-01070                                 gintsts.d32 = 0;
+-01071                                 gintsts.b.usbsuspend = 1;
+-01072                                 DWC_WRITE_REG32(&core_if->core_global_regs->
+-01073                                                 gintsts, gintsts.d32);
+-01074                                 DWC_PRINTF("Start of hibernation completed\n");
+-01075                                 dwc_otg_save_global_regs(core_if);
+-01076                                 dwc_otg_save_dev_regs(core_if);
+-01077 
+-01078                                 gusbcfg.d32 =
+-01079                                     DWC_READ_REG32(&core_if->core_global_regs->
+-01080                                                    gusbcfg);
+-01081                                 if (gusbcfg.b.ulpi_utmi_sel == 1) {
+-01082                                         /* ULPI interface */
+-01083                                         /* Suspend the Phy Clock */
+-01084                                         pcgcctl.d32 = 0;
+-01085                                         pcgcctl.b.stoppclk = 1;
+-01086                                         DWC_MODIFY_REG32(core_if->pcgcctl, 0,
+-01087                                                          pcgcctl.d32);
+-01088                                         dwc_udelay(10);
+-01089                                         gpwrdn.b.pmuactv = 1;
+-01090                                         DWC_MODIFY_REG32(&core_if->
+-01091                                                          core_global_regs->
+-01092                                                          gpwrdn, 0, gpwrdn.d32);
+-01093                                 } else {
+-01094                                         /* UTMI+ Interface */
+-01095                                         gpwrdn.b.pmuactv = 1;
+-01096                                         DWC_MODIFY_REG32(&core_if->
+-01097                                                          core_global_regs->
+-01098                                                          gpwrdn, 0, gpwrdn.d32);
+-01099                                         dwc_udelay(10);
+-01100                                         pcgcctl.b.stoppclk = 1;
+-01101                                         DWC_MODIFY_REG32(core_if->pcgcctl, 0,
+-01102                                                          pcgcctl.d32);
+-01103                                         dwc_udelay(10);
+-01104                                 }
+-01105 
+-01106                                 /* Set flag to indicate that we are in hibernation */
+-01107                                 core_if->hibernation_suspend = 1;
+-01108                                 /* Enable interrupts from wake up logic */
+-01109                                 gpwrdn.d32 = 0;
+-01110                                 gpwrdn.b.pmuintsel = 1;
+-01111                                 DWC_MODIFY_REG32(&core_if->core_global_regs->
+-01112                                                  gpwrdn, 0, gpwrdn.d32);
+-01113                                 dwc_udelay(10);
+-01114 
+-01115                                 /* Unmask device mode interrupts in GPWRDN */
+-01116                                 gpwrdn.d32 = 0;
+-01117                                 gpwrdn.b.rst_det_msk = 1;
+-01118                                 gpwrdn.b.lnstchng_msk = 1;
+-01119                                 gpwrdn.b.sts_chngint_msk = 1;
+-01120                                 DWC_MODIFY_REG32(&core_if->core_global_regs->
+-01121                                                  gpwrdn, 0, gpwrdn.d32);
+-01122                                 dwc_udelay(10);
+-01123 
+-01124                                 /* Enable Power Down Clamp */
+-01125                                 gpwrdn.d32 = 0;
+-01126                                 gpwrdn.b.pwrdnclmp = 1;
+-01127                                 DWC_MODIFY_REG32(&core_if->core_global_regs->
+-01128                                                  gpwrdn, 0, gpwrdn.d32);
+-01129                                 dwc_udelay(10);
+-01130 
+-01131                                 /* Switch off VDD */
+-01132                                 gpwrdn.d32 = 0;
+-01133                                 gpwrdn.b.pwrdnswtch = 1;
+-01134                                 DWC_MODIFY_REG32(&core_if->core_global_regs->
+-01135                                                  gpwrdn, 0, gpwrdn.d32);
+-01136 
+-01137                                 /* Save gpwrdn register for further usage if stschng interrupt */
+-01138                                 core_if->gr_backup->gpwrdn_local =
+-01139                                                         DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
+-01140                                 DWC_PRINTF("Hibernation completed\n");
+-01141 
+-01142                                 return 1;
+-01143                         }
+-01144                 }
+-01145         } else {
+-01146                 if (core_if->op_state == A_PERIPHERAL) {
+-01147                         DWC_DEBUGPL(DBG_ANY, "a_peripheral->a_host\n");
+-01148                         /* Clear the a_peripheral flag, back to a_host. */
+-01149                         DWC_SPINUNLOCK(core_if->lock);
+-01150                         cil_pcd_stop(core_if);
+-01151                         cil_hcd_start(core_if);
+-01152                         DWC_SPINLOCK(core_if->lock);
+-01153                         core_if->op_state = A_HOST;
+-01154                 }
+-01155         }
+-01156 
+-01157         /* Change to L2(suspend) state */
+-01158         core_if->lx_state = DWC_OTG_L2;
+-01159 
+-01160         /* Clear interrupt */
+-01161         gintsts.d32 = 0;
+-01162         gintsts.b.usbsuspend = 1;
+-01163         DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
+-01164 
+-01165         return 1;
+-01166 }
+-01167 
+-01168 #ifdef CONFIG_USB_DWC_OTG_LPM
+-01169 
+-01172 static int32_t dwc_otg_handle_lpm_intr(dwc_otg_core_if_t * core_if)
+-01173 {
+-01174         glpmcfg_data_t lpmcfg;
+-01175         gintsts_data_t gintsts;
+-01176 
+-01177         if (!core_if->core_params->lpm_enable) {
+-01178                 DWC_PRINTF("Unexpected LPM interrupt\n");
+-01179         }
+-01180 
+-01181         lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
+-01182         DWC_PRINTF("LPM config register = 0x%08x\n", lpmcfg.d32);
+-01183 
+-01184         if (dwc_otg_is_host_mode(core_if)) {
+-01185                 cil_hcd_sleep(core_if);
+-01186         } else {
+-01187                 lpmcfg.b.hird_thres |= (1 << 4);
+-01188                 DWC_WRITE_REG32(&core_if->core_global_regs->glpmcfg,
+-01189                                 lpmcfg.d32);
+-01190         }
+-01191 
+-01192         /* Examine prt_sleep_sts after TL1TokenTetry period max (10 us) */
+-01193         dwc_udelay(10);
+-01194         lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
+-01195         if (lpmcfg.b.prt_sleep_sts) {
+-01196                 /* Save the current state */
+-01197                 core_if->lx_state = DWC_OTG_L1;
+-01198         }
+-01199 
+-01200         /* Clear interrupt  */
+-01201         gintsts.d32 = 0;
+-01202         gintsts.b.lpmtranrcvd = 1;
+-01203         DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
+-01204         return 1;
+-01205 }
+-01206 #endif /* CONFIG_USB_DWC_OTG_LPM */
+-01207 
+-01211 static inline uint32_t dwc_otg_read_common_intr(dwc_otg_core_if_t * core_if)
+-01212 {
+-01213         gahbcfg_data_t gahbcfg = {.d32 = 0 };
+-01214         gintsts_data_t gintsts;
+-01215         gintmsk_data_t gintmsk;
+-01216         gintmsk_data_t gintmsk_common = {.d32 = 0 };
+-01217         gintmsk_common.b.wkupintr = 1;
+-01218         gintmsk_common.b.sessreqintr = 1;
+-01219         gintmsk_common.b.conidstschng = 1;
+-01220         gintmsk_common.b.otgintr = 1;
+-01221         gintmsk_common.b.modemismatch = 1;
+-01222         gintmsk_common.b.disconnect = 1;
+-01223         gintmsk_common.b.usbsuspend = 1;
+-01224 #ifdef CONFIG_USB_DWC_OTG_LPM
+-01225         gintmsk_common.b.lpmtranrcvd = 1;
+-01226 #endif
+-01227         gintmsk_common.b.restoredone = 1;
+-01231         gintmsk_common.b.portintr = 1;
+-01232 
+-01233         gintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts);
+-01234         gintmsk.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintmsk);
+-01235         gahbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gahbcfg);
+-01236 
+-01237 #ifdef DEBUG
+-01238         /* if any common interrupts set */
+-01239         if (gintsts.d32 & gintmsk_common.d32) {
+-01240                 DWC_DEBUGPL(DBG_ANY, "gintsts=%08x  gintmsk=%08x\n",
+-01241                             gintsts.d32, gintmsk.d32);
+-01242         }
+-01243 #endif
+-01244         if (gahbcfg.b.glblintrmsk)      
+-01245                 return ((gintsts.d32 & gintmsk.d32) & gintmsk_common.d32);
+-01246         else
+-01247                 return 0;
+-01248 
+-01249 }
+-01250 
+-01251 /* MACRO for clearing interupt bits in GPWRDN register */
+-01252 #define CLEAR_GPWRDN_INTR(__core_if,__intr) \
+-01253 do { \
+-01254                 gpwrdn_data_t gpwrdn = {.d32=0}; \
+-01255                 gpwrdn.b.__intr = 1; \
+-01256                 DWC_MODIFY_REG32(&__core_if->core_global_regs->gpwrdn, \
+-01257                 0, gpwrdn.d32); \
+-01258 } while (0)
+-01259 
+-01275 int32_t dwc_otg_handle_common_intr(void *dev)
+-01276 {
+-01277         int retval = 0;
+-01278         gintsts_data_t gintsts;
+-01279         gpwrdn_data_t gpwrdn = {.d32 = 0 };
+-01280         dwc_otg_device_t *otg_dev = dev;
+-01281         dwc_otg_core_if_t *core_if = otg_dev->core_if;
+-01282         gpwrdn.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
+-01283         if (dwc_otg_is_device_mode(core_if))
+-01284                 core_if->frame_num = dwc_otg_get_frame_number(core_if);
+-01285                 
+-01286         if (core_if->lock)
+-01287                 DWC_SPINLOCK(core_if->lock);
+-01288 
+-01289         if (core_if->hibernation_suspend <= 0) {
+-01290                 gintsts.d32 = dwc_otg_read_common_intr(core_if);
+-01291 
+-01292                 if (gintsts.b.modemismatch) {
+-01293                         retval |= dwc_otg_handle_mode_mismatch_intr(core_if);
+-01294                 }
+-01295                 if (gintsts.b.otgintr) {
+-01296                         retval |= dwc_otg_handle_otg_intr(core_if);
+-01297                 }
+-01298                 if (gintsts.b.conidstschng) {
+-01299                         retval |= dwc_otg_handle_conn_id_status_change_intr(core_if);
+-01300                 }
+-01301                 if (gintsts.b.disconnect) {
+-01302                         retval |= dwc_otg_handle_disconnect_intr(core_if);
+-01303                 }
+-01304                 if (gintsts.b.sessreqintr) {
+-01305                         retval |= dwc_otg_handle_session_req_intr(core_if);
+-01306                 }
+-01307                 if (gintsts.b.wkupintr) {
+-01308                         retval |= dwc_otg_handle_wakeup_detected_intr(core_if);
+-01309                 }
+-01310                 if (gintsts.b.usbsuspend) {
+-01311                         retval |= dwc_otg_handle_usb_suspend_intr(core_if);
+-01312                 }
+-01313 #ifdef CONFIG_USB_DWC_OTG_LPM
+-01314                 if (gintsts.b.lpmtranrcvd) {
+-01315                         retval |= dwc_otg_handle_lpm_intr(core_if);
+-01316                 }
+-01317 #endif
+-01318                 if (gintsts.b.restoredone) {
+-01319                         gintsts.d32 = 0;
+-01320                         if (core_if->power_down == 2)
+-01321                                 core_if->hibernation_suspend = -1;
+-01322                         gintsts.b.restoredone = 1;
+-01323                         DWC_WRITE_REG32(&core_if->core_global_regs->gintsts,gintsts.d32);
+-01324                         DWC_PRINTF(" --Restore done interrupt received-- \n");
+-01325                         retval |= 1;
+-01326                 }
+-01327                 if (gintsts.b.portintr && dwc_otg_is_device_mode(core_if)) {
+-01328                         /* The port interrupt occurs while in device mode with HPRT0
+-01329                          * Port Enable/Disable.
+-01330                          */
+-01331                         gintsts.d32 = 0;
+-01332                         gintsts.b.portintr = 1;
+-01333                         DWC_WRITE_REG32(&core_if->core_global_regs->gintsts,gintsts.d32);
+-01334                         retval |= 1;
+-01335 
+-01336                 }
+-01337         } else {
+-01338                 DWC_DEBUGPL(DBG_ANY, "gpwrdn=%08x\n", gpwrdn.d32);
+-01339 
+-01340                 if (gpwrdn.b.disconn_det && gpwrdn.b.disconn_det_msk) {
+-01341                         CLEAR_GPWRDN_INTR(core_if, disconn_det);
+-01342                         if (gpwrdn.b.linestate == 0) {
+-01343                                 dwc_otg_handle_pwrdn_disconnect_intr(core_if);
+-01344                         } else {
+-01345                                 DWC_PRINTF("Disconnect detected while linestate is not 0\n");
+-01346                         }
+-01347 
+-01348                         retval |= 1;
+-01349                 }
+-01350                 if (gpwrdn.b.lnstschng && gpwrdn.b.lnstchng_msk) {
+-01351                         CLEAR_GPWRDN_INTR(core_if, lnstschng);
+-01352                         /* remote wakeup from hibernation */
+-01353                         if (gpwrdn.b.linestate == 2 || gpwrdn.b.linestate == 1) {
+-01354                                 dwc_otg_handle_pwrdn_wakeup_detected_intr(core_if);
+-01355                         } else {
+-01356                                 DWC_PRINTF("gpwrdn.linestate = %d\n", gpwrdn.b.linestate);
+-01357                         }
+-01358                         retval |= 1;
+-01359                 }
+-01360                 if (gpwrdn.b.rst_det && gpwrdn.b.rst_det_msk) {
+-01361                         CLEAR_GPWRDN_INTR(core_if, rst_det);
+-01362                         if (gpwrdn.b.linestate == 0) {
+-01363                                 DWC_PRINTF("Reset detected\n");
+-01364                                 retval |= dwc_otg_device_hibernation_restore(core_if, 0, 1);
+-01365                         }
+-01366                 }
+-01367                 if (gpwrdn.b.srp_det && gpwrdn.b.srp_det_msk) {
+-01368                         CLEAR_GPWRDN_INTR(core_if, srp_det);
+-01369                         dwc_otg_handle_pwrdn_srp_intr(core_if);
+-01370                         retval |= 1;
+-01371                 }
+-01372         }
+-01373         /* Handle ADP interrupt here */
+-01374         if (gpwrdn.b.adp_int) {
+-01375                 DWC_PRINTF("ADP interrupt\n");
+-01376                 CLEAR_GPWRDN_INTR(core_if, adp_int);
+-01377                 dwc_otg_adp_handle_intr(core_if);
+-01378                 retval |= 1;
+-01379         }
+-01380         if (gpwrdn.b.sts_chngint && gpwrdn.b.sts_chngint_msk) {
+-01381                 DWC_PRINTF("STS CHNG interrupt asserted\n");
+-01382                 CLEAR_GPWRDN_INTR(core_if, sts_chngint);
+-01383                 dwc_otg_handle_pwrdn_stschng_intr(otg_dev);
+-01384 
+-01385                 retval |= 1;
+-01386         }
+-01387         if (core_if->lock)
+-01388                 DWC_SPINUNLOCK(core_if->lock);
+-01389 
+-01390         return retval;
+-01391 }
+-
                                                                                Generated on Thu Oct 27 03:56:37 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__cil__intr_8c.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/dwc__otg__cil__intr_8c.html 2013-07-26 19:34:40.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,483 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_cil_intr.c File Reference +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                dwc_otg_cil_intr.c File Reference

                                                                                The Core Interface Layer provides basic services for accessing and managing the DWC_otg hardware. More... +-

                                                                                +-#include "dwc_os.h"
                                                                                +-#include "dwc_otg_regs.h"
                                                                                +-#include "dwc_otg_cil.h"
                                                                                +-#include "dwc_otg_driver.h"
                                                                                +-#include "dwc_otg_pcd.h"
                                                                                +-#include "dwc_otg_hcd.h"
                                                                                +- +-

                                                                                +-Go to the source code of this file. +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-

                                                                                Defines

                                                                                #define CLEAR_GPWRDN_INTR(__core_if, __intr)

                                                                                Functions

                                                                                int32_t dwc_otg_handle_mode_mismatch_intr (dwc_otg_core_if_t *core_if)
                                                                                 This function will log a debug message.
                                                                                int32_t dwc_otg_handle_otg_intr (dwc_otg_core_if_t *core_if)
                                                                                 This function handles the OTG Interrupts.
                                                                                +-void w_conn_id_status_change (void *p)
                                                                                int32_t dwc_otg_handle_conn_id_status_change_intr (dwc_otg_core_if_t *core_if)
                                                                                 This function handles the Connector ID Status Change Interrupt.
                                                                                int32_t dwc_otg_handle_session_req_intr (dwc_otg_core_if_t *core_if)
                                                                                 This interrupt indicates that a device is initiating the Session Request Protocol to request the host to turn on bus power so a new session can begin.
                                                                                void w_wakeup_detected (void *p)
                                                                                int32_t dwc_otg_handle_wakeup_detected_intr (dwc_otg_core_if_t *core_if)
                                                                                 This interrupt indicates that the DWC_otg controller has detected a resume or remote wakeup sequence.
                                                                                +-int32_t dwc_otg_handle_pwrdn_disconnect_intr (dwc_otg_core_if_t *core_if)
                                                                                 This interrupt indicates that the Wakeup Logic has detected a Device disconnect.
                                                                                +-int32_t dwc_otg_handle_pwrdn_wakeup_detected_intr (dwc_otg_core_if_t *core_if)
                                                                                 This interrupt indicates that the Wakeup Logic has detected a remote wakeup sequence.
                                                                                +-int32_t dwc_otg_handle_pwrdn_idsts_change (dwc_otg_device_t *otg_dev)
                                                                                +-int32_t dwc_otg_handle_pwrdn_session_change (dwc_otg_core_if_t *core_if)
                                                                                +-uint32_t dwc_otg_handle_pwrdn_stschng_intr (dwc_otg_device_t *otg_dev)
                                                                                 This interrupt indicates that the Wakeup Logic has detected a status change either on IDDIG or BSessVld.
                                                                                +-int32_t dwc_otg_handle_pwrdn_srp_intr (dwc_otg_core_if_t *core_if)
                                                                                 This interrupt indicates that the Wakeup Logic has detected a SRP.
                                                                                +-int32_t dwc_otg_handle_restore_done_intr (dwc_otg_core_if_t *core_if)
                                                                                 This interrupt indicates that restore command after Hibernation was completed by the core.
                                                                                int32_t dwc_otg_handle_disconnect_intr (dwc_otg_core_if_t *core_if)
                                                                                 This interrupt indicates that a device has been disconnected from the root port.
                                                                                int32_t dwc_otg_handle_usb_suspend_intr (dwc_otg_core_if_t *core_if)
                                                                                 This interrupt indicates that SUSPEND state has been detected on the USB.
                                                                                uint32_t dwc_otg_read_common_intr (dwc_otg_core_if_t *core_if)
                                                                                 This function returns the Core Interrupt register.
                                                                                int32_t dwc_otg_handle_common_intr (void *dev)
                                                                                 This function should be called on every hardware interrupt.
                                                                                +-

                                                                                Detailed Description

                                                                                +-The Core Interface Layer provides basic services for accessing and managing the DWC_otg hardware. +-

                                                                                +-These services are used by both the Host Controller Driver and the Peripheral Controller Driver.

                                                                                +-This file contains the Common Interrupt handlers. +-

                                                                                +-Definition in file dwc_otg_cil_intr.c.

                                                                                Define Documentation

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                #define CLEAR_GPWRDN_INTR ( __core_if,
                                                                                __intr   ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Value:

                                                                                do { \
+-                gpwrdn_data_t gpwrdn = {.d32=0}; \
+-                gpwrdn.b.__intr = 1; \
+-                DWC_MODIFY_REG32(&__core_if->core_global_regs->gpwrdn, \
+-                0, gpwrdn.d32); \
+-} while (0)
+-
                                                                                +-

                                                                                +-Definition at line 1252 of file dwc_otg_cil_intr.c.

                                                                                +-

                                                                                Function Documentation

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                int32_t dwc_otg_handle_mode_mismatch_intr ( dwc_otg_core_if_t *  core_if  ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This function will log a debug message. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +-
                                                                                core_if Programming view of DWC_otg controller.
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 64 of file dwc_otg_cil_intr.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                int32_t dwc_otg_handle_otg_intr ( dwc_otg_core_if_t *  core_if  ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This function handles the OTG Interrupts. +-

                                                                                +-It reads the OTG Interrupt Register (GOTGINT) to determine what interrupt has occurred.

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +-
                                                                                core_if Programming view of DWC_otg controller.
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 84 of file dwc_otg_cil_intr.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                int32_t dwc_otg_handle_conn_id_status_change_intr ( dwc_otg_core_if_t *  core_if  ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This function handles the Connector ID Status Change Interrupt. +-

                                                                                +-It reads the OTG Interrupt Register (GOTCTL) to determine whether this is a Device to Host Mode transition or a Host Mode to Device Transition.

                                                                                +-This only occurs when the cable is connected/removed from the PHY connector.

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +-
                                                                                core_if Programming view of DWC_otg controller.
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 319 of file dwc_otg_cil_intr.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                int32_t dwc_otg_handle_session_req_intr ( dwc_otg_core_if_t *  core_if  ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This interrupt indicates that a device is initiating the Session Request Protocol to request the host to turn on bus power so a new session can begin. +-

                                                                                +-The handler responds by turning on bus power. If the DWC_otg controller is in low power mode, the handler brings the controller out of low power mode before turning on bus power.

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +-
                                                                                core_if Programming view of DWC_otg controller.
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 366 of file dwc_otg_cil_intr.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                void w_wakeup_detected ( void *  p  ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Change to L0 state +-

                                                                                +-Definition at line 398 of file dwc_otg_cil_intr.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                int32_t dwc_otg_handle_wakeup_detected_intr ( dwc_otg_core_if_t *  core_if  ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This interrupt indicates that the DWC_otg controller has detected a resume or remote wakeup sequence. +-

                                                                                +-If the DWC_otg controller is in low power mode, the handler must brings the controller out of low power mode. The controller automatically begins resume signaling. The handler schedules a time to stop resume signaling.

                                                                                +-Change to L0 state

                                                                                +-Change to L0 state +-

                                                                                +-Definition at line 434 of file dwc_otg_cil_intr.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                int32_t dwc_otg_handle_disconnect_intr ( dwc_otg_core_if_t *  core_if  ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This interrupt indicates that a device has been disconnected from the root port. +-

                                                                                +-

                                                                                Todo:
                                                                                Consolidate this if statement.
                                                                                +- +-

                                                                                +-Definition at line 933 of file dwc_otg_cil_intr.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                int32_t dwc_otg_handle_usb_suspend_intr ( dwc_otg_core_if_t *  core_if  ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This interrupt indicates that SUSPEND state has been detected on the USB. +-

                                                                                +-For HNP the USB Suspend interrupt signals the change from "a_peripheral" to "a_host".

                                                                                +-When power management is enabled the core will be put in low power mode. +-

                                                                                +-Definition at line 1015 of file dwc_otg_cil_intr.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                uint32_t dwc_otg_read_common_intr ( dwc_otg_core_if_t *  core_if  )  [inline, static]
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This function returns the Core Interrupt register. +-

                                                                                +-

                                                                                Todo:
                                                                                : The port interrupt occurs while in device mode. Added code to CIL to clear the interrupt for now!
                                                                                +- +-

                                                                                +-Definition at line 1211 of file dwc_otg_cil_intr.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                int32_t dwc_otg_handle_common_intr ( void *  dev  ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This function should be called on every hardware interrupt. +-

                                                                                +-The common interrupts are those that occur in both Host and Device mode. This handler handles the following interrupts:

                                                                                  +-
                                                                                • Mode Mismatch Interrupt
                                                                                • Disconnect Interrupt
                                                                                • OTG Interrupt
                                                                                • Connector ID Status Change Interrupt
                                                                                • Session Request Interrupt.
                                                                                • Resume / Remote Wakeup Detected Interrupt.
                                                                                • LPM Transaction Received Interrupt
                                                                                • ADP Transaction Received Interrupt
                                                                                +- +-

                                                                                +-Definition at line 1275 of file dwc_otg_cil_intr.c.

                                                                                +-

                                                                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__core__if_8h-source.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/dwc__otg__core__if_8h-source.html 2013-07-26 19:34:40.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,397 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_core_if.h Source File +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                dwc_otg_core_if.h

                                                                                Go to the documentation of this file.
                                                                                00001 /* ==========================================================================
+-00002  * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_core_if.h $
+-00003  * $Revision: #12 $
+-00004  * $Date: 2011/10/24 $
+-00005  * $Change: 1871159 $
+-00006  *
+-00007  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
+-00008  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
+-00009  * otherwise expressly agreed to in writing between Synopsys and you.
+-00010  *
+-00011  * The Software IS NOT an item of Licensed Software or Licensed Product under
+-00012  * any End User Software License Agreement or Agreement for Licensed Product
+-00013  * with Synopsys or any supplement thereto. You are permitted to use and
+-00014  * redistribute this Software in source and binary forms, with or without
+-00015  * modification, provided that redistributions of source code must retain this
+-00016  * notice. You may not view, use, disclose, copy or distribute this file or
+-00017  * any information contained herein except pursuant to this license grant from
+-00018  * Synopsys. If you do not agree with this notice, including the disclaimer
+-00019  * below, then you are not authorized to use the Software.
+-00020  *
+-00021  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
+-00022  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+-00023  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+-00024  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
+-00025  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+-00026  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+-00027  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+-00028  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+-00029  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+-00030  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+-00031  * DAMAGE.
+-00032  * ========================================================================== */
+-00033 #if !defined(__DWC_CORE_IF_H__)
+-00034 #define __DWC_CORE_IF_H__
+-00035 
+-00036 #include "dwc_os.h"
+-00037 
+-00042 struct dwc_otg_core_if;
+-00043 typedef struct dwc_otg_core_if dwc_otg_core_if_t;
+-00044 
+-00046 #define MAX_PERIO_FIFOS 15
+-00047 
+-00048 #define MAX_TX_FIFOS 15
+-00049 
+-00051 #define MAX_EPS_CHANNELS 16
+-00052 
+-00053 extern dwc_otg_core_if_t *dwc_otg_cil_init(const uint32_t * _reg_base_addr);
+-00054 extern void dwc_otg_core_init(dwc_otg_core_if_t * _core_if);
+-00055 extern void dwc_otg_cil_remove(dwc_otg_core_if_t * _core_if);
+-00056 
+-00057 extern void dwc_otg_enable_global_interrupts(dwc_otg_core_if_t * _core_if);
+-00058 extern void dwc_otg_disable_global_interrupts(dwc_otg_core_if_t * _core_if);
+-00059 
+-00060 extern uint8_t dwc_otg_is_device_mode(dwc_otg_core_if_t * _core_if);
+-00061 extern uint8_t dwc_otg_is_host_mode(dwc_otg_core_if_t * _core_if);
+-00062 
+-00063 extern uint8_t dwc_otg_is_dma_enable(dwc_otg_core_if_t * core_if);
+-00064 
+-00066 extern int32_t dwc_otg_handle_common_intr(void *otg_dev);
+-00067 
+-00078 extern int dwc_otg_set_param_otg_cap(dwc_otg_core_if_t * core_if, int32_t val);
+-00079 extern int32_t dwc_otg_get_param_otg_cap(dwc_otg_core_if_t * core_if);
+-00080 #define DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE 0
+-00081 #define DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE 1
+-00082 #define DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE 2
+-00083 #define dwc_param_otg_cap_default DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE
+-00084 
+-00085 extern int dwc_otg_set_param_opt(dwc_otg_core_if_t * core_if, int32_t val);
+-00086 extern int32_t dwc_otg_get_param_opt(dwc_otg_core_if_t * core_if);
+-00087 #define dwc_param_opt_default 1
+-00088 
+-00096 extern int dwc_otg_set_param_dma_enable(dwc_otg_core_if_t * core_if,
+-00097                                         int32_t val);
+-00098 extern int32_t dwc_otg_get_param_dma_enable(dwc_otg_core_if_t * core_if);
+-00099 #define dwc_param_dma_enable_default 1
+-00100 
+-00109 extern int dwc_otg_set_param_dma_desc_enable(dwc_otg_core_if_t * core_if,
+-00110                                              int32_t val);
+-00111 extern int32_t dwc_otg_get_param_dma_desc_enable(dwc_otg_core_if_t * core_if);
+-00112 #define dwc_param_dma_desc_enable_default 1
+-00113 
+-00117 extern int dwc_otg_set_param_dma_burst_size(dwc_otg_core_if_t * core_if,
+-00118                                             int32_t val);
+-00119 extern int32_t dwc_otg_get_param_dma_burst_size(dwc_otg_core_if_t * core_if);
+-00120 #define dwc_param_dma_burst_size_default 32
+-00121 
+-00130 extern int dwc_otg_set_param_speed(dwc_otg_core_if_t * core_if, int32_t val);
+-00131 extern int32_t dwc_otg_get_param_speed(dwc_otg_core_if_t * core_if);
+-00132 #define dwc_param_speed_default 0
+-00133 #define DWC_SPEED_PARAM_HIGH 0
+-00134 #define DWC_SPEED_PARAM_FULL 1
+-00135 
+-00141 extern int dwc_otg_set_param_host_support_fs_ls_low_power(dwc_otg_core_if_t *
+-00142                                                           core_if, int32_t val);
+-00143 extern int32_t dwc_otg_get_param_host_support_fs_ls_low_power(dwc_otg_core_if_t
+-00144                                                               * core_if);
+-00145 #define dwc_param_host_support_fs_ls_low_power_default 0
+-00146 
+-00155 extern int dwc_otg_set_param_host_ls_low_power_phy_clk(dwc_otg_core_if_t *
+-00156                                                        core_if, int32_t val);
+-00157 extern int32_t dwc_otg_get_param_host_ls_low_power_phy_clk(dwc_otg_core_if_t *
+-00158                                                            core_if);
+-00159 #define dwc_param_host_ls_low_power_phy_clk_default 0
+-00160 #define DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ 0
+-00161 #define DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ 1
+-00162 
+-00167 extern int dwc_otg_set_param_enable_dynamic_fifo(dwc_otg_core_if_t * core_if,
+-00168                                                  int32_t val);
+-00169 extern int32_t dwc_otg_get_param_enable_dynamic_fifo(dwc_otg_core_if_t *
+-00170                                                      core_if);
+-00171 #define dwc_param_enable_dynamic_fifo_default 1
+-00172 
+-00179 extern int dwc_otg_set_param_data_fifo_size(dwc_otg_core_if_t * core_if,
+-00180                                             int32_t val);
+-00181 extern int32_t dwc_otg_get_param_data_fifo_size(dwc_otg_core_if_t * core_if);
+-00182 #define dwc_param_data_fifo_size_default 8192
+-00183 
+-00188 extern int dwc_otg_set_param_dev_rx_fifo_size(dwc_otg_core_if_t * core_if,
+-00189                                               int32_t val);
+-00190 extern int32_t dwc_otg_get_param_dev_rx_fifo_size(dwc_otg_core_if_t * core_if);
+-00191 #define dwc_param_dev_rx_fifo_size_default 1064
+-00192 
+-00197 extern int dwc_otg_set_param_dev_nperio_tx_fifo_size(dwc_otg_core_if_t *
+-00198                                                      core_if, int32_t val);
+-00199 extern int32_t dwc_otg_get_param_dev_nperio_tx_fifo_size(dwc_otg_core_if_t *
+-00200                                                          core_if);
+-00201 #define dwc_param_dev_nperio_tx_fifo_size_default 1024
+-00202 
+-00207 extern int dwc_otg_set_param_dev_perio_tx_fifo_size(dwc_otg_core_if_t * core_if,
+-00208                                                     int32_t val, int fifo_num);
+-00209 extern int32_t dwc_otg_get_param_dev_perio_tx_fifo_size(dwc_otg_core_if_t *
+-00210                                                         core_if, int fifo_num);
+-00211 #define dwc_param_dev_perio_tx_fifo_size_default 256
+-00212 
+-00217 extern int dwc_otg_set_param_host_rx_fifo_size(dwc_otg_core_if_t * core_if,
+-00218                                                int32_t val);
+-00219 extern int32_t dwc_otg_get_param_host_rx_fifo_size(dwc_otg_core_if_t * core_if);
+-00220 #define dwc_param_host_rx_fifo_size_default 1024
+-00221 
+-00226 extern int dwc_otg_set_param_host_nperio_tx_fifo_size(dwc_otg_core_if_t *
+-00227                                                       core_if, int32_t val);
+-00228 extern int32_t dwc_otg_get_param_host_nperio_tx_fifo_size(dwc_otg_core_if_t *
+-00229                                                           core_if);
+-00230 #define dwc_param_host_nperio_tx_fifo_size_default 1024
+-00231 
+-00236 extern int dwc_otg_set_param_host_perio_tx_fifo_size(dwc_otg_core_if_t *
+-00237                                                      core_if, int32_t val);
+-00238 extern int32_t dwc_otg_get_param_host_perio_tx_fifo_size(dwc_otg_core_if_t *
+-00239                                                          core_if);
+-00240 #define dwc_param_host_perio_tx_fifo_size_default 1024
+-00241 
+-00245 extern int dwc_otg_set_param_max_transfer_size(dwc_otg_core_if_t * core_if,
+-00246                                                int32_t val);
+-00247 extern int32_t dwc_otg_get_param_max_transfer_size(dwc_otg_core_if_t * core_if);
+-00248 #define dwc_param_max_transfer_size_default 65535
+-00249 
+-00253 extern int dwc_otg_set_param_max_packet_count(dwc_otg_core_if_t * core_if,
+-00254                                               int32_t val);
+-00255 extern int32_t dwc_otg_get_param_max_packet_count(dwc_otg_core_if_t * core_if);
+-00256 #define dwc_param_max_packet_count_default 511
+-00257 
+-00262 extern int dwc_otg_set_param_host_channels(dwc_otg_core_if_t * core_if,
+-00263                                            int32_t val);
+-00264 extern int32_t dwc_otg_get_param_host_channels(dwc_otg_core_if_t * core_if);
+-00265 #define dwc_param_host_channels_default 12
+-00266 
+-00273 extern int dwc_otg_set_param_dev_endpoints(dwc_otg_core_if_t * core_if,
+-00274                                            int32_t val);
+-00275 extern int32_t dwc_otg_get_param_dev_endpoints(dwc_otg_core_if_t * core_if);
+-00276 #define dwc_param_dev_endpoints_default 6
+-00277 
+-00286 extern int dwc_otg_set_param_phy_type(dwc_otg_core_if_t * core_if, int32_t val);
+-00287 extern int32_t dwc_otg_get_param_phy_type(dwc_otg_core_if_t * core_if);
+-00288 #define DWC_PHY_TYPE_PARAM_FS 0
+-00289 #define DWC_PHY_TYPE_PARAM_UTMI 1
+-00290 #define DWC_PHY_TYPE_PARAM_ULPI 2
+-00291 #define dwc_param_phy_type_default DWC_PHY_TYPE_PARAM_UTMI
+-00292 
+-00304 extern int dwc_otg_set_param_phy_utmi_width(dwc_otg_core_if_t * core_if,
+-00305                                             int32_t val);
+-00306 extern int32_t dwc_otg_get_param_phy_utmi_width(dwc_otg_core_if_t * core_if);
+-00307 #define dwc_param_phy_utmi_width_default 16
+-00308 
+-00319 extern int dwc_otg_set_param_phy_ulpi_ddr(dwc_otg_core_if_t * core_if,
+-00320                                           int32_t val);
+-00321 extern int32_t dwc_otg_get_param_phy_ulpi_ddr(dwc_otg_core_if_t * core_if);
+-00322 #define dwc_param_phy_ulpi_ddr_default 0
+-00323 
+-00328 extern int dwc_otg_set_param_phy_ulpi_ext_vbus(dwc_otg_core_if_t * core_if,
+-00329                                                int32_t val);
+-00330 extern int32_t dwc_otg_get_param_phy_ulpi_ext_vbus(dwc_otg_core_if_t * core_if);
+-00331 #define DWC_PHY_ULPI_INTERNAL_VBUS 0
+-00332 #define DWC_PHY_ULPI_EXTERNAL_VBUS 1
+-00333 #define dwc_param_phy_ulpi_ext_vbus_default DWC_PHY_ULPI_INTERNAL_VBUS
+-00334 
+-00341 extern int dwc_otg_set_param_i2c_enable(dwc_otg_core_if_t * core_if,
+-00342                                         int32_t val);
+-00343 extern int32_t dwc_otg_get_param_i2c_enable(dwc_otg_core_if_t * core_if);
+-00344 #define dwc_param_i2c_enable_default 0
+-00345 
+-00346 extern int dwc_otg_set_param_ulpi_fs_ls(dwc_otg_core_if_t * core_if,
+-00347                                         int32_t val);
+-00348 extern int32_t dwc_otg_get_param_ulpi_fs_ls(dwc_otg_core_if_t * core_if);
+-00349 #define dwc_param_ulpi_fs_ls_default 0
+-00350 
+-00351 extern int dwc_otg_set_param_ts_dline(dwc_otg_core_if_t * core_if, int32_t val);
+-00352 extern int32_t dwc_otg_get_param_ts_dline(dwc_otg_core_if_t * core_if);
+-00353 #define dwc_param_ts_dline_default 0
+-00354 
+-00361 extern int dwc_otg_set_param_en_multiple_tx_fifo(dwc_otg_core_if_t * core_if,
+-00362                                                  int32_t val);
+-00363 extern int32_t dwc_otg_get_param_en_multiple_tx_fifo(dwc_otg_core_if_t *
+-00364                                                      core_if);
+-00365 #define dwc_param_en_multiple_tx_fifo_default 1
+-00366 
+-00371 extern int dwc_otg_set_param_dev_tx_fifo_size(dwc_otg_core_if_t * core_if,
+-00372                                               int fifo_num, int32_t val);
+-00373 extern int32_t dwc_otg_get_param_dev_tx_fifo_size(dwc_otg_core_if_t * core_if,
+-00374                                                   int fifo_num);
+-00375 #define dwc_param_dev_tx_fifo_size_default 768
+-00376 
+-00382 extern int dwc_otg_set_param_thr_ctl(dwc_otg_core_if_t * core_if, int32_t val);
+-00383 extern int32_t dwc_otg_get_thr_ctl(dwc_otg_core_if_t * core_if, int fifo_num);
+-00384 #define dwc_param_thr_ctl_default 0
+-00385 
+-00389 extern int dwc_otg_set_param_tx_thr_length(dwc_otg_core_if_t * core_if,
+-00390                                            int32_t val);
+-00391 extern int32_t dwc_otg_get_tx_thr_length(dwc_otg_core_if_t * core_if);
+-00392 #define dwc_param_tx_thr_length_default 64
+-00393 
+-00397 extern int dwc_otg_set_param_rx_thr_length(dwc_otg_core_if_t * core_if,
+-00398                                            int32_t val);
+-00399 extern int32_t dwc_otg_get_rx_thr_length(dwc_otg_core_if_t * core_if);
+-00400 #define dwc_param_rx_thr_length_default 64
+-00401 
+-00405 extern int dwc_otg_set_param_lpm_enable(dwc_otg_core_if_t * core_if,
+-00406                                         int32_t val);
+-00407 extern int32_t dwc_otg_get_param_lpm_enable(dwc_otg_core_if_t * core_if);
+-00408 #define dwc_param_lpm_enable_default 1
+-00409 
+-00413 extern int dwc_otg_set_param_pti_enable(dwc_otg_core_if_t * core_if,
+-00414                                         int32_t val);
+-00415 extern int32_t dwc_otg_get_param_pti_enable(dwc_otg_core_if_t * core_if);
+-00416 #define dwc_param_pti_enable_default 0
+-00417 
+-00421 extern int dwc_otg_set_param_mpi_enable(dwc_otg_core_if_t * core_if,
+-00422                                         int32_t val);
+-00423 extern int32_t dwc_otg_get_param_mpi_enable(dwc_otg_core_if_t * core_if);
+-00424 #define dwc_param_mpi_enable_default 0
+-00425 
+-00429 extern int dwc_otg_set_param_adp_enable(dwc_otg_core_if_t * core_if,
+-00430                                         int32_t val);
+-00431 extern int32_t dwc_otg_get_param_adp_enable(dwc_otg_core_if_t * core_if);
+-00432 #define dwc_param_adp_enable_default 0
+-00433 
+-00438 extern int dwc_otg_set_param_ic_usb_cap(dwc_otg_core_if_t * core_if,
+-00439                                         int32_t val);
+-00440 extern int32_t dwc_otg_get_param_ic_usb_cap(dwc_otg_core_if_t * core_if);
+-00441 #define dwc_param_ic_usb_cap_default 0
+-00442 
+-00443 extern int dwc_otg_set_param_ahb_thr_ratio(dwc_otg_core_if_t * core_if,
+-00444                                            int32_t val);
+-00445 extern int32_t dwc_otg_get_param_ahb_thr_ratio(dwc_otg_core_if_t * core_if);
+-00446 #define dwc_param_ahb_thr_ratio_default 0
+-00447 
+-00448 extern int dwc_otg_set_param_power_down(dwc_otg_core_if_t * core_if,
+-00449                                         int32_t val);
+-00450 extern int32_t dwc_otg_get_param_power_down(dwc_otg_core_if_t * core_if);
+-00451 #define dwc_param_power_down_default 0
+-00452 
+-00453 extern int dwc_otg_set_param_reload_ctl(dwc_otg_core_if_t * core_if,
+-00454                                         int32_t val);
+-00455 extern int32_t dwc_otg_get_param_reload_ctl(dwc_otg_core_if_t * core_if);
+-00456 #define dwc_param_reload_ctl_default 0
+-00457 
+-00458 extern int dwc_otg_set_param_dev_out_nak(dwc_otg_core_if_t * core_if,
+-00459                                                                                 int32_t val);
+-00460 extern int32_t dwc_otg_get_param_dev_out_nak(dwc_otg_core_if_t * core_if);
+-00461 #define dwc_param_dev_out_nak_default 0
+-00462 
+-00463 extern int dwc_otg_set_param_cont_on_bna(dwc_otg_core_if_t * core_if,
+-00464                                                                                  int32_t val);
+-00465 extern int32_t dwc_otg_get_param_cont_on_bna(dwc_otg_core_if_t * core_if);
+-00466 #define dwc_param_cont_on_bna_default 0
+-00467 
+-00468 extern int dwc_otg_set_param_ahb_single(dwc_otg_core_if_t * core_if,
+-00469                                                                                  int32_t val);
+-00470 extern int32_t dwc_otg_get_param_ahb_single(dwc_otg_core_if_t * core_if);
+-00471 #define dwc_param_ahb_single_default 0
+-00472 
+-00473 extern int dwc_otg_set_param_otg_ver(dwc_otg_core_if_t * core_if, int32_t val);
+-00474 extern int32_t dwc_otg_get_param_otg_ver(dwc_otg_core_if_t * core_if);
+-00475 #define dwc_param_otg_ver_default 0
+-00476 
+-00484 extern void dwc_otg_dump_dev_registers(dwc_otg_core_if_t * _core_if);
+-00485 extern void dwc_otg_dump_spram(dwc_otg_core_if_t * _core_if);
+-00486 extern void dwc_otg_dump_host_registers(dwc_otg_core_if_t * _core_if);
+-00487 extern void dwc_otg_dump_global_registers(dwc_otg_core_if_t * _core_if);
+-00488 
+-00492 extern uint32_t dwc_otg_get_hnpstatus(dwc_otg_core_if_t * core_if);
+-00493 
+-00497 extern uint32_t dwc_otg_get_srpstatus(dwc_otg_core_if_t * core_if);
+-00498 
+-00502 extern void dwc_otg_set_hnpreq(dwc_otg_core_if_t * core_if, uint32_t val);
+-00503 
+-00507 extern uint32_t dwc_otg_get_gsnpsid(dwc_otg_core_if_t * core_if);
+-00508 
+-00513 extern uint32_t dwc_otg_get_mode(dwc_otg_core_if_t * core_if);
+-00514 
+-00518 extern uint32_t dwc_otg_get_hnpcapable(dwc_otg_core_if_t * core_if);
+-00522 extern void dwc_otg_set_hnpcapable(dwc_otg_core_if_t * core_if, uint32_t val);
+-00523 
+-00527 extern uint32_t dwc_otg_get_srpcapable(dwc_otg_core_if_t * core_if);
+-00531 extern void dwc_otg_set_srpcapable(dwc_otg_core_if_t * core_if, uint32_t val);
+-00532 
+-00536 extern uint32_t dwc_otg_get_devspeed(dwc_otg_core_if_t * core_if);
+-00540 extern void dwc_otg_set_devspeed(dwc_otg_core_if_t * core_if, uint32_t val);
+-00541 
+-00545 extern uint32_t dwc_otg_get_busconnected(dwc_otg_core_if_t * core_if);
+-00546 
+-00550 extern uint32_t dwc_otg_get_enumspeed(dwc_otg_core_if_t * core_if);
+-00551 
+-00555 extern uint32_t dwc_otg_get_prtpower(dwc_otg_core_if_t * core_if);
+-00556 
+-00560 extern uint32_t dwc_otg_get_core_state(dwc_otg_core_if_t * core_if);
+-00561 
+-00565 extern void dwc_otg_set_prtpower(dwc_otg_core_if_t * core_if, uint32_t val);
+-00566 
+-00570 extern uint32_t dwc_otg_get_prtsuspend(dwc_otg_core_if_t * core_if);
+-00574 extern void dwc_otg_set_prtsuspend(dwc_otg_core_if_t * core_if, uint32_t val);
+-00575 
+-00579 extern uint32_t dwc_otg_get_mode_ch_tim(dwc_otg_core_if_t * core_if);
+-00583 extern void dwc_otg_set_mode_ch_tim(dwc_otg_core_if_t * core_if, uint32_t val);
+-00584 
+-00588 extern uint32_t dwc_otg_get_fr_interval(dwc_otg_core_if_t * core_if);
+-00592 extern void dwc_otg_set_fr_interval(dwc_otg_core_if_t * core_if, uint32_t val);
+-00593 
+-00598 extern void dwc_otg_set_prtresume(dwc_otg_core_if_t * core_if, uint32_t val);
+-00599 
+-00603 extern uint32_t dwc_otg_get_remotewakesig(dwc_otg_core_if_t * core_if);
+-00604 
+-00608 extern uint32_t dwc_otg_get_lpm_portsleepstatus(dwc_otg_core_if_t * core_if);
+-00609 
+-00613 extern uint32_t dwc_otg_get_lpm_remotewakeenabled(dwc_otg_core_if_t * core_if);
+-00614 
+-00618 extern uint32_t dwc_otg_get_lpmresponse(dwc_otg_core_if_t * core_if);
+-00622 extern void dwc_otg_set_lpmresponse(dwc_otg_core_if_t * core_if, uint32_t val);
+-00623 
+-00627 extern uint32_t dwc_otg_get_hsic_connect(dwc_otg_core_if_t * core_if);
+-00631 extern void dwc_otg_set_hsic_connect(dwc_otg_core_if_t * core_if, uint32_t val);
+-00632 
+-00636 extern uint32_t dwc_otg_get_inv_sel_hsic(dwc_otg_core_if_t * core_if);
+-00640 extern void dwc_otg_set_inv_sel_hsic(dwc_otg_core_if_t * core_if, uint32_t val);
+-00641 
+-00642 /*
+-00643  * Some functions for accessing registers
+-00644  */
+-00645 
+-00649 extern uint32_t dwc_otg_get_gotgctl(dwc_otg_core_if_t * core_if);
+-00650 extern void dwc_otg_set_gotgctl(dwc_otg_core_if_t * core_if, uint32_t val);
+-00651 
+-00655 extern uint32_t dwc_otg_get_gusbcfg(dwc_otg_core_if_t * core_if);
+-00656 extern void dwc_otg_set_gusbcfg(dwc_otg_core_if_t * core_if, uint32_t val);
+-00657 
+-00661 extern uint32_t dwc_otg_get_grxfsiz(dwc_otg_core_if_t * core_if);
+-00662 extern void dwc_otg_set_grxfsiz(dwc_otg_core_if_t * core_if, uint32_t val);
+-00663 
+-00667 extern uint32_t dwc_otg_get_gnptxfsiz(dwc_otg_core_if_t * core_if);
+-00668 extern void dwc_otg_set_gnptxfsiz(dwc_otg_core_if_t * core_if, uint32_t val);
+-00669 
+-00670 extern uint32_t dwc_otg_get_gpvndctl(dwc_otg_core_if_t * core_if);
+-00671 extern void dwc_otg_set_gpvndctl(dwc_otg_core_if_t * core_if, uint32_t val);
+-00672 
+-00676 extern uint32_t dwc_otg_get_ggpio(dwc_otg_core_if_t * core_if);
+-00677 extern void dwc_otg_set_ggpio(dwc_otg_core_if_t * core_if, uint32_t val);
+-00678 
+-00682 extern uint32_t dwc_otg_get_guid(dwc_otg_core_if_t * core_if);
+-00683 extern void dwc_otg_set_guid(dwc_otg_core_if_t * core_if, uint32_t val);
+-00684 
+-00688 extern uint32_t dwc_otg_get_hprt0(dwc_otg_core_if_t * core_if);
+-00689 extern void dwc_otg_set_hprt0(dwc_otg_core_if_t * core_if, uint32_t val);
+-00690 
+-00694 extern uint32_t dwc_otg_get_hptxfsiz(dwc_otg_core_if_t * core_if);
+-00695 
+-00698 #endif                          /* __DWC_CORE_IF_H__ */
+-
                                                                                Generated on Thu Oct 27 03:56:37 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__core__if_8h.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/dwc__otg__core__if_8h.html 2013-07-26 19:34:40.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,2076 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_core_if.h File Reference +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                dwc_otg_core_if.h File Reference

                                                                                This file defines DWC_OTG Core API. More... +-

                                                                                +-#include "dwc_os.h"
                                                                                +- +-

                                                                                +-Go to the source code of this file. +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-

                                                                                OTG Core Parameters

                                                                                +-#define DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE   0
                                                                                +-#define DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE   1
                                                                                +-#define DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE   2
                                                                                +-#define dwc_param_otg_cap_default   DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE
                                                                                +-#define dwc_param_opt_default   1
                                                                                +-#define dwc_param_dma_enable_default   1
                                                                                +-#define dwc_param_dma_desc_enable_default   1
                                                                                +-#define dwc_param_dma_burst_size_default   32
                                                                                +-#define dwc_param_speed_default   0
                                                                                +-#define DWC_SPEED_PARAM_HIGH   0
                                                                                +-#define DWC_SPEED_PARAM_FULL   1
                                                                                +-#define dwc_param_host_support_fs_ls_low_power_default   0
                                                                                +-#define dwc_param_host_ls_low_power_phy_clk_default   0
                                                                                +-#define DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ   0
                                                                                +-#define DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ   1
                                                                                +-#define dwc_param_enable_dynamic_fifo_default   1
                                                                                +-#define dwc_param_data_fifo_size_default   8192
                                                                                +-#define dwc_param_dev_rx_fifo_size_default   1064
                                                                                +-#define dwc_param_dev_nperio_tx_fifo_size_default   1024
                                                                                +-#define dwc_param_dev_perio_tx_fifo_size_default   256
                                                                                +-#define dwc_param_host_rx_fifo_size_default   1024
                                                                                +-#define dwc_param_host_nperio_tx_fifo_size_default   1024
                                                                                +-#define dwc_param_host_perio_tx_fifo_size_default   1024
                                                                                +-#define dwc_param_max_transfer_size_default   65535
                                                                                +-#define dwc_param_max_packet_count_default   511
                                                                                +-#define dwc_param_host_channels_default   12
                                                                                +-#define dwc_param_dev_endpoints_default   6
                                                                                +-#define DWC_PHY_TYPE_PARAM_FS   0
                                                                                +-#define DWC_PHY_TYPE_PARAM_UTMI   1
                                                                                +-#define DWC_PHY_TYPE_PARAM_ULPI   2
                                                                                +-#define dwc_param_phy_type_default   DWC_PHY_TYPE_PARAM_UTMI
                                                                                +-#define dwc_param_phy_utmi_width_default   16
                                                                                +-#define dwc_param_phy_ulpi_ddr_default   0
                                                                                +-#define DWC_PHY_ULPI_INTERNAL_VBUS   0
                                                                                +-#define DWC_PHY_ULPI_EXTERNAL_VBUS   1
                                                                                +-#define dwc_param_phy_ulpi_ext_vbus_default   DWC_PHY_ULPI_INTERNAL_VBUS
                                                                                +-#define dwc_param_i2c_enable_default   0
                                                                                +-#define dwc_param_ulpi_fs_ls_default   0
                                                                                +-#define dwc_param_ts_dline_default   0
                                                                                +-#define dwc_param_en_multiple_tx_fifo_default   1
                                                                                +-#define dwc_param_dev_tx_fifo_size_default   768
                                                                                +-#define dwc_param_thr_ctl_default   0
                                                                                +-#define dwc_param_tx_thr_length_default   64
                                                                                +-#define dwc_param_rx_thr_length_default   64
                                                                                +-#define dwc_param_lpm_enable_default   1
                                                                                +-#define dwc_param_pti_enable_default   0
                                                                                +-#define dwc_param_mpi_enable_default   0
                                                                                +-#define dwc_param_adp_enable_default   0
                                                                                +-#define dwc_param_ic_usb_cap_default   0
                                                                                +-#define dwc_param_ahb_thr_ratio_default   0
                                                                                +-#define dwc_param_power_down_default   0
                                                                                +-#define dwc_param_reload_ctl_default   0
                                                                                +-#define dwc_param_dev_out_nak_default   0
                                                                                +-#define dwc_param_cont_on_bna_default   0
                                                                                +-#define dwc_param_ahb_single_default   0
                                                                                +-#define dwc_param_otg_ver_default   0
                                                                                int dwc_otg_set_param_otg_cap (dwc_otg_core_if_t *core_if, int32_t val)
                                                                                 Specifies the OTG capabilities.
                                                                                +-int32_t dwc_otg_get_param_otg_cap (dwc_otg_core_if_t *core_if)
                                                                                +-int dwc_otg_set_param_opt (dwc_otg_core_if_t *core_if, int32_t val)
                                                                                +-int32_t dwc_otg_get_param_opt (dwc_otg_core_if_t *core_if)
                                                                                int dwc_otg_set_param_dma_enable (dwc_otg_core_if_t *core_if, int32_t val)
                                                                                 Specifies whether to use slave or DMA mode for accessing the data FIFOs.
                                                                                +-int32_t dwc_otg_get_param_dma_enable (dwc_otg_core_if_t *core_if)
                                                                                int dwc_otg_set_param_dma_desc_enable (dwc_otg_core_if_t *core_if, int32_t val)
                                                                                 When DMA mode is enabled specifies whether to use address DMA or DMA Descritor mode for accessing the data FIFOs in device mode.
                                                                                +-int32_t dwc_otg_get_param_dma_desc_enable (dwc_otg_core_if_t *core_if)
                                                                                int dwc_otg_set_param_dma_burst_size (dwc_otg_core_if_t *core_if, int32_t val)
                                                                                 The DMA Burst size (applicable only for External DMA Mode).
                                                                                +-int32_t dwc_otg_get_param_dma_burst_size (dwc_otg_core_if_t *core_if)
                                                                                int dwc_otg_set_param_speed (dwc_otg_core_if_t *core_if, int32_t val)
                                                                                 Specifies the maximum speed of operation in host and device mode.
                                                                                +-int32_t dwc_otg_get_param_speed (dwc_otg_core_if_t *core_if)
                                                                                int dwc_otg_set_param_host_support_fs_ls_low_power (dwc_otg_core_if_t *core_if, int32_t val)
                                                                                 Specifies whether low power mode is supported when attached to a Full Speed or Low Speed device in host mode.
                                                                                +-int32_t dwc_otg_get_param_host_support_fs_ls_low_power (dwc_otg_core_if_t *core_if)
                                                                                int dwc_otg_set_param_host_ls_low_power_phy_clk (dwc_otg_core_if_t *core_if, int32_t val)
                                                                                 Specifies the PHY clock rate in low power mode when connected to a Low Speed device in host mode.
                                                                                +-int32_t dwc_otg_get_param_host_ls_low_power_phy_clk (dwc_otg_core_if_t *core_if)
                                                                                +-int dwc_otg_set_param_enable_dynamic_fifo (dwc_otg_core_if_t *core_if, int32_t val)
                                                                                 0 - Use cC FIFO size parameters 1 - Allow dynamic FIFO sizing (default)
                                                                                +-int32_t dwc_otg_get_param_enable_dynamic_fifo (dwc_otg_core_if_t *core_if)
                                                                                int dwc_otg_set_param_data_fifo_size (dwc_otg_core_if_t *core_if, int32_t val)
                                                                                 Total number of 4-byte words in the data FIFO memory.
                                                                                +-int32_t dwc_otg_get_param_data_fifo_size (dwc_otg_core_if_t *core_if)
                                                                                int dwc_otg_set_param_dev_rx_fifo_size (dwc_otg_core_if_t *core_if, int32_t val)
                                                                                 Number of 4-byte words in the Rx FIFO in device mode when dynamic FIFO sizing is enabled.
                                                                                +-int32_t dwc_otg_get_param_dev_rx_fifo_size (dwc_otg_core_if_t *core_if)
                                                                                int dwc_otg_set_param_dev_nperio_tx_fifo_size (dwc_otg_core_if_t *core_if, int32_t val)
                                                                                 Number of 4-byte words in the non-periodic Tx FIFO in device mode when dynamic FIFO sizing is enabled.
                                                                                +-int32_t dwc_otg_get_param_dev_nperio_tx_fifo_size (dwc_otg_core_if_t *core_if)
                                                                                int dwc_otg_set_param_dev_perio_tx_fifo_size (dwc_otg_core_if_t *core_if, int32_t val, int fifo_num)
                                                                                 Number of 4-byte words in each of the periodic Tx FIFOs in device mode when dynamic FIFO sizing is enabled.
                                                                                +-int32_t dwc_otg_get_param_dev_perio_tx_fifo_size (dwc_otg_core_if_t *core_if, int fifo_num)
                                                                                int dwc_otg_set_param_host_rx_fifo_size (dwc_otg_core_if_t *core_if, int32_t val)
                                                                                 Number of 4-byte words in the Rx FIFO in host mode when dynamic FIFO sizing is enabled.
                                                                                +-int32_t dwc_otg_get_param_host_rx_fifo_size (dwc_otg_core_if_t *core_if)
                                                                                int dwc_otg_set_param_host_nperio_tx_fifo_size (dwc_otg_core_if_t *core_if, int32_t val)
                                                                                 Number of 4-byte words in the non-periodic Tx FIFO in host mode when Dynamic FIFO sizing is enabled in the core.
                                                                                +-int32_t dwc_otg_get_param_host_nperio_tx_fifo_size (dwc_otg_core_if_t *core_if)
                                                                                int dwc_otg_set_param_host_perio_tx_fifo_size (dwc_otg_core_if_t *core_if, int32_t val)
                                                                                 Number of 4-byte words in the host periodic Tx FIFO when dynamic FIFO sizing is enabled.
                                                                                +-int32_t dwc_otg_get_param_host_perio_tx_fifo_size (dwc_otg_core_if_t *core_if)
                                                                                int dwc_otg_set_param_max_transfer_size (dwc_otg_core_if_t *core_if, int32_t val)
                                                                                 The maximum transfer size supported in bytes.
                                                                                +-int32_t dwc_otg_get_param_max_transfer_size (dwc_otg_core_if_t *core_if)
                                                                                int dwc_otg_set_param_max_packet_count (dwc_otg_core_if_t *core_if, int32_t val)
                                                                                 The maximum number of packets in a transfer.
                                                                                +-int32_t dwc_otg_get_param_max_packet_count (dwc_otg_core_if_t *core_if)
                                                                                int dwc_otg_set_param_host_channels (dwc_otg_core_if_t *core_if, int32_t val)
                                                                                 The number of host channel registers to use.
                                                                                +-int32_t dwc_otg_get_param_host_channels (dwc_otg_core_if_t *core_if)
                                                                                int dwc_otg_set_param_dev_endpoints (dwc_otg_core_if_t *core_if, int32_t val)
                                                                                 The number of endpoints in addition to EP0 available for device mode operations.
                                                                                +-int32_t dwc_otg_get_param_dev_endpoints (dwc_otg_core_if_t *core_if)
                                                                                int dwc_otg_set_param_phy_type (dwc_otg_core_if_t *core_if, int32_t val)
                                                                                 Specifies the type of PHY interface to use.
                                                                                +-int32_t dwc_otg_get_param_phy_type (dwc_otg_core_if_t *core_if)
                                                                                int dwc_otg_set_param_phy_utmi_width (dwc_otg_core_if_t *core_if, int32_t val)
                                                                                 Specifies the UTMI+ Data Width.
                                                                                +-int32_t dwc_otg_get_param_phy_utmi_width (dwc_otg_core_if_t *core_if)
                                                                                int dwc_otg_set_param_phy_ulpi_ddr (dwc_otg_core_if_t *core_if, int32_t val)
                                                                                 Specifies whether the ULPI operates at double or single data rate.
                                                                                +-int32_t dwc_otg_get_param_phy_ulpi_ddr (dwc_otg_core_if_t *core_if)
                                                                                +-int dwc_otg_set_param_phy_ulpi_ext_vbus (dwc_otg_core_if_t *core_if, int32_t val)
                                                                                 Specifies whether to use the internal or external supply to drive the vbus with a ULPI phy.
                                                                                +-int32_t dwc_otg_get_param_phy_ulpi_ext_vbus (dwc_otg_core_if_t *core_if)
                                                                                int dwc_otg_set_param_i2c_enable (dwc_otg_core_if_t *core_if, int32_t val)
                                                                                 Specifies whether to use the I2Cinterface for full speed PHY.
                                                                                +-int32_t dwc_otg_get_param_i2c_enable (dwc_otg_core_if_t *core_if)
                                                                                +-int dwc_otg_set_param_ulpi_fs_ls (dwc_otg_core_if_t *core_if, int32_t val)
                                                                                +-int32_t dwc_otg_get_param_ulpi_fs_ls (dwc_otg_core_if_t *core_if)
                                                                                +-int dwc_otg_set_param_ts_dline (dwc_otg_core_if_t *core_if, int32_t val)
                                                                                +-int32_t dwc_otg_get_param_ts_dline (dwc_otg_core_if_t *core_if)
                                                                                +-int dwc_otg_set_param_en_multiple_tx_fifo (dwc_otg_core_if_t *core_if, int32_t val)
                                                                                 Specifies whether dedicated transmit FIFOs are enabled for non periodic IN endpoints in device mode 0 - No 1 - Yes.
                                                                                +-int32_t dwc_otg_get_param_en_multiple_tx_fifo (dwc_otg_core_if_t *core_if)
                                                                                int dwc_otg_set_param_dev_tx_fifo_size (dwc_otg_core_if_t *core_if, int fifo_num, int32_t val)
                                                                                 Number of 4-byte words in each of the Tx FIFOs in device mode when dynamic FIFO sizing is enabled.
                                                                                +-int32_t dwc_otg_get_param_dev_tx_fifo_size (dwc_otg_core_if_t *core_if, int fifo_num)
                                                                                +-int dwc_otg_set_param_thr_ctl (dwc_otg_core_if_t *core_if, int32_t val)
                                                                                 Thresholding enable flag- bit 0 - enable non-ISO Tx thresholding bit 1 - enable ISO Tx thresholding bit 2 - enable Rx thresholding.
                                                                                +-int32_t dwc_otg_get_thr_ctl (dwc_otg_core_if_t *core_if, int fifo_num)
                                                                                +-int dwc_otg_set_param_tx_thr_length (dwc_otg_core_if_t *core_if, int32_t val)
                                                                                 Thresholding length for Tx FIFOs in 32 bit DWORDs.
                                                                                +-int32_t dwc_otg_get_tx_thr_length (dwc_otg_core_if_t *core_if)
                                                                                +-int dwc_otg_set_param_rx_thr_length (dwc_otg_core_if_t *core_if, int32_t val)
                                                                                 Thresholding length for Rx FIFOs in 32 bit DWORDs.
                                                                                +-int32_t dwc_otg_get_rx_thr_length (dwc_otg_core_if_t *core_if)
                                                                                +-int dwc_otg_set_param_lpm_enable (dwc_otg_core_if_t *core_if, int32_t val)
                                                                                 Specifies whether LPM (Link Power Management) support is enabled.
                                                                                +-int32_t dwc_otg_get_param_lpm_enable (dwc_otg_core_if_t *core_if)
                                                                                +-int dwc_otg_set_param_pti_enable (dwc_otg_core_if_t *core_if, int32_t val)
                                                                                 Specifies whether PTI enhancement is enabled.
                                                                                +-int32_t dwc_otg_get_param_pti_enable (dwc_otg_core_if_t *core_if)
                                                                                +-int dwc_otg_set_param_mpi_enable (dwc_otg_core_if_t *core_if, int32_t val)
                                                                                 Specifies whether MPI enhancement is enabled.
                                                                                +-int32_t dwc_otg_get_param_mpi_enable (dwc_otg_core_if_t *core_if)
                                                                                +-int dwc_otg_set_param_adp_enable (dwc_otg_core_if_t *core_if, int32_t val)
                                                                                 Specifies whether ADP capability is enabled.
                                                                                +-int32_t dwc_otg_get_param_adp_enable (dwc_otg_core_if_t *core_if)
                                                                                +-int dwc_otg_set_param_ic_usb_cap (dwc_otg_core_if_t *core_if, int32_t val)
                                                                                 Specifies whether IC_USB capability is enabled.
                                                                                +-int32_t dwc_otg_get_param_ic_usb_cap (dwc_otg_core_if_t *core_if)
                                                                                +-int dwc_otg_set_param_ahb_thr_ratio (dwc_otg_core_if_t *core_if, int32_t val)
                                                                                +-int32_t dwc_otg_get_param_ahb_thr_ratio (dwc_otg_core_if_t *core_if)
                                                                                +-int dwc_otg_set_param_power_down (dwc_otg_core_if_t *core_if, int32_t val)
                                                                                +-int32_t dwc_otg_get_param_power_down (dwc_otg_core_if_t *core_if)
                                                                                +-int dwc_otg_set_param_reload_ctl (dwc_otg_core_if_t *core_if, int32_t val)
                                                                                +-int32_t dwc_otg_get_param_reload_ctl (dwc_otg_core_if_t *core_if)
                                                                                +-int dwc_otg_set_param_dev_out_nak (dwc_otg_core_if_t *core_if, int32_t val)
                                                                                +-int32_t dwc_otg_get_param_dev_out_nak (dwc_otg_core_if_t *core_if)
                                                                                +-int dwc_otg_set_param_cont_on_bna (dwc_otg_core_if_t *core_if, int32_t val)
                                                                                +-int32_t dwc_otg_get_param_cont_on_bna (dwc_otg_core_if_t *core_if)
                                                                                +-int dwc_otg_set_param_ahb_single (dwc_otg_core_if_t *core_if, int32_t val)
                                                                                +-int32_t dwc_otg_get_param_ahb_single (dwc_otg_core_if_t *core_if)
                                                                                +-int dwc_otg_set_param_otg_ver (dwc_otg_core_if_t *core_if, int32_t val)
                                                                                +-int32_t dwc_otg_get_param_otg_ver (dwc_otg_core_if_t *core_if)

                                                                                Access to registers and bit-fields

                                                                                void dwc_otg_dump_dev_registers (dwc_otg_core_if_t *_core_if)
                                                                                 Dump core registers and SPRAM.
                                                                                void dwc_otg_dump_spram (dwc_otg_core_if_t *_core_if)
                                                                                 This functions reads the SPRAM and prints its content.
                                                                                void dwc_otg_dump_host_registers (dwc_otg_core_if_t *_core_if)
                                                                                 This function reads the host registers and prints them.
                                                                                void dwc_otg_dump_global_registers (dwc_otg_core_if_t *_core_if)
                                                                                 This function reads the core global registers and prints them.
                                                                                +-uint32_t dwc_otg_get_hnpstatus (dwc_otg_core_if_t *core_if)
                                                                                 Get host negotiation status.
                                                                                +-uint32_t dwc_otg_get_srpstatus (dwc_otg_core_if_t *core_if)
                                                                                 Get srp status.
                                                                                +-void dwc_otg_set_hnpreq (dwc_otg_core_if_t *core_if, uint32_t val)
                                                                                 Set hnpreq bit in the GOTGCTL register.
                                                                                +-uint32_t dwc_otg_get_gsnpsid (dwc_otg_core_if_t *core_if)
                                                                                 Get Content of SNPSID register.
                                                                                uint32_t dwc_otg_get_mode (dwc_otg_core_if_t *core_if)
                                                                                 Get current mode.
                                                                                +-uint32_t dwc_otg_get_hnpcapable (dwc_otg_core_if_t *core_if)
                                                                                 Get value of hnpcapable field in the GUSBCFG register.
                                                                                +-void dwc_otg_set_hnpcapable (dwc_otg_core_if_t *core_if, uint32_t val)
                                                                                 Set value of hnpcapable field in the GUSBCFG register.
                                                                                +-uint32_t dwc_otg_get_srpcapable (dwc_otg_core_if_t *core_if)
                                                                                 Get value of srpcapable field in the GUSBCFG register.
                                                                                +-void dwc_otg_set_srpcapable (dwc_otg_core_if_t *core_if, uint32_t val)
                                                                                 Set value of srpcapable field in the GUSBCFG register.
                                                                                +-uint32_t dwc_otg_get_devspeed (dwc_otg_core_if_t *core_if)
                                                                                 Get value of devspeed field in the DCFG register.
                                                                                +-void dwc_otg_set_devspeed (dwc_otg_core_if_t *core_if, uint32_t val)
                                                                                 Set value of devspeed field in the DCFG register.
                                                                                +-uint32_t dwc_otg_get_busconnected (dwc_otg_core_if_t *core_if)
                                                                                 Get the value of busconnected field from the HPRT0 register.
                                                                                +-uint32_t dwc_otg_get_enumspeed (dwc_otg_core_if_t *core_if)
                                                                                 Gets the device enumeration Speed.
                                                                                +-uint32_t dwc_otg_get_prtpower (dwc_otg_core_if_t *core_if)
                                                                                 Get value of prtpwr field from the HPRT0 register.
                                                                                +-uint32_t dwc_otg_get_core_state (dwc_otg_core_if_t *core_if)
                                                                                 Get value of flag indicating core state - hibernated or not.
                                                                                +-void dwc_otg_set_prtpower (dwc_otg_core_if_t *core_if, uint32_t val)
                                                                                 Set value of prtpwr field from the HPRT0 register.
                                                                                +-uint32_t dwc_otg_get_prtsuspend (dwc_otg_core_if_t *core_if)
                                                                                 Get value of prtsusp field from the HPRT0 regsiter.
                                                                                +-void dwc_otg_set_prtsuspend (dwc_otg_core_if_t *core_if, uint32_t val)
                                                                                 Set value of prtpwr field from the HPRT0 register.
                                                                                +-uint32_t dwc_otg_get_mode_ch_tim (dwc_otg_core_if_t *core_if)
                                                                                 Get value of ModeChTimEn field from the HCFG regsiter.
                                                                                +-void dwc_otg_set_mode_ch_tim (dwc_otg_core_if_t *core_if, uint32_t val)
                                                                                 Set value of ModeChTimEn field from the HCFG regsiter.
                                                                                +-uint32_t dwc_otg_get_fr_interval (dwc_otg_core_if_t *core_if)
                                                                                 Get value of Fram Interval field from the HFIR regsiter.
                                                                                +-void dwc_otg_set_fr_interval (dwc_otg_core_if_t *core_if, uint32_t val)
                                                                                 Set value of Frame Interval field from the HFIR regsiter.
                                                                                +-void dwc_otg_set_prtresume (dwc_otg_core_if_t *core_if, uint32_t val)
                                                                                 Set value of prtres field from the HPRT0 register FIXME Remove?
                                                                                +-uint32_t dwc_otg_get_remotewakesig (dwc_otg_core_if_t *core_if)
                                                                                 Get value of rmtwkupsig bit in DCTL register.
                                                                                +-uint32_t dwc_otg_get_lpm_portsleepstatus (dwc_otg_core_if_t *core_if)
                                                                                 Get value of prt_sleep_sts field from the GLPMCFG register.
                                                                                +-uint32_t dwc_otg_get_lpm_remotewakeenabled (dwc_otg_core_if_t *core_if)
                                                                                 Get value of rem_wkup_en field from the GLPMCFG register.
                                                                                +-uint32_t dwc_otg_get_lpmresponse (dwc_otg_core_if_t *core_if)
                                                                                 Get value of appl_resp field from the GLPMCFG register.
                                                                                +-void dwc_otg_set_lpmresponse (dwc_otg_core_if_t *core_if, uint32_t val)
                                                                                 Set value of appl_resp field from the GLPMCFG register.
                                                                                +-uint32_t dwc_otg_get_hsic_connect (dwc_otg_core_if_t *core_if)
                                                                                 Get value of hsic_connect field from the GLPMCFG register.
                                                                                +-void dwc_otg_set_hsic_connect (dwc_otg_core_if_t *core_if, uint32_t val)
                                                                                 Set value of hsic_connect field from the GLPMCFG register.
                                                                                +-uint32_t dwc_otg_get_inv_sel_hsic (dwc_otg_core_if_t *core_if)
                                                                                 Get value of inv_sel_hsic field from the GLPMCFG register.
                                                                                +-void dwc_otg_set_inv_sel_hsic (dwc_otg_core_if_t *core_if, uint32_t val)
                                                                                 Set value of inv_sel_hsic field from the GLPMFG register.
                                                                                +-uint32_t dwc_otg_get_gotgctl (dwc_otg_core_if_t *core_if)
                                                                                 GOTGCTL register.
                                                                                +-void dwc_otg_set_gotgctl (dwc_otg_core_if_t *core_if, uint32_t val)
                                                                                +-uint32_t dwc_otg_get_gusbcfg (dwc_otg_core_if_t *core_if)
                                                                                 GUSBCFG register.
                                                                                +-void dwc_otg_set_gusbcfg (dwc_otg_core_if_t *core_if, uint32_t val)
                                                                                +-uint32_t dwc_otg_get_grxfsiz (dwc_otg_core_if_t *core_if)
                                                                                 GRXFSIZ register.
                                                                                +-void dwc_otg_set_grxfsiz (dwc_otg_core_if_t *core_if, uint32_t val)
                                                                                +-uint32_t dwc_otg_get_gnptxfsiz (dwc_otg_core_if_t *core_if)
                                                                                 GNPTXFSIZ register.
                                                                                +-void dwc_otg_set_gnptxfsiz (dwc_otg_core_if_t *core_if, uint32_t val)
                                                                                +-uint32_t dwc_otg_get_gpvndctl (dwc_otg_core_if_t *core_if)
                                                                                +-void dwc_otg_set_gpvndctl (dwc_otg_core_if_t *core_if, uint32_t val)
                                                                                +-uint32_t dwc_otg_get_ggpio (dwc_otg_core_if_t *core_if)
                                                                                 GGPIO register.
                                                                                +-void dwc_otg_set_ggpio (dwc_otg_core_if_t *core_if, uint32_t val)
                                                                                +-uint32_t dwc_otg_get_guid (dwc_otg_core_if_t *core_if)
                                                                                 GUID register.
                                                                                +-void dwc_otg_set_guid (dwc_otg_core_if_t *core_if, uint32_t val)
                                                                                +-uint32_t dwc_otg_get_hprt0 (dwc_otg_core_if_t *core_if)
                                                                                 HPRT0 register.
                                                                                +-void dwc_otg_set_hprt0 (dwc_otg_core_if_t *core_if, uint32_t val)
                                                                                +-uint32_t dwc_otg_get_hptxfsiz (dwc_otg_core_if_t *core_if)
                                                                                 GHPTXFSIZE.

                                                                                Defines

                                                                                +-#define __DWC_CORE_IF_H__
                                                                                +-#define MAX_PERIO_FIFOS   15
                                                                                 Maximum number of Periodic FIFOs.
                                                                                +-#define MAX_TX_FIFOS   15
                                                                                 Maximum number of Periodic FIFOs.
                                                                                +-#define MAX_EPS_CHANNELS   16
                                                                                 Maximum number of Endpoints/HostChannels.

                                                                                Typedefs

                                                                                +-typedef dwc_otg_core_if dwc_otg_core_if_t

                                                                                Functions

                                                                                dwc_otg_core_if_t * dwc_otg_cil_init (const uint32_t *_reg_base_addr)
                                                                                 This function is called to initialize the DWC_otg CSR data structures.
                                                                                void dwc_otg_core_init (dwc_otg_core_if_t *_core_if)
                                                                                 This function initializes the DWC_otg controller registers and prepares the core for device mode or host mode operation.
                                                                                void dwc_otg_cil_remove (dwc_otg_core_if_t *_core_if)
                                                                                 This function frees the structures allocated by dwc_otg_cil_init().
                                                                                void dwc_otg_enable_global_interrupts (dwc_otg_core_if_t *_core_if)
                                                                                 This function enables the controller's Global Interrupt in the AHB Config register.
                                                                                void dwc_otg_disable_global_interrupts (dwc_otg_core_if_t *_core_if)
                                                                                 This function disables the controller's Global Interrupt in the AHB Config register.
                                                                                +-uint8_t dwc_otg_is_device_mode (dwc_otg_core_if_t *_core_if)
                                                                                +-uint8_t dwc_otg_is_host_mode (dwc_otg_core_if_t *_core_if)
                                                                                +-uint8_t dwc_otg_is_dma_enable (dwc_otg_core_if_t *core_if)
                                                                                int32_t dwc_otg_handle_common_intr (void *otg_dev)
                                                                                 This function should be called on every hardware interrupt.
                                                                                +-

                                                                                Detailed Description

                                                                                +-This file defines DWC_OTG Core API. +-

                                                                                +- +-

                                                                                +-Definition in file dwc_otg_core_if.h.

                                                                                Function Documentation

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                dwc_otg_core_if_t* dwc_otg_cil_init ( const uint32_t *  reg_base_addr  ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This function is called to initialize the DWC_otg CSR data structures. +-

                                                                                +-The register addresses in the device and host structures are initialized from the base address supplied by the caller. The calling function must make the OS calls to get the base address of the DWC_otg controller registers. The core_params argument holds the parameters that specify how the core should be configured.

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +-
                                                                                reg_base_addr Base address of DWC_otg core registers
                                                                                +-
                                                                                +-

                                                                                +-ADP initialization +-

                                                                                +-Definition at line 78 of file dwc_otg_cil.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                void dwc_otg_core_init ( dwc_otg_core_if_t *  core_if  ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This function initializes the DWC_otg controller registers and prepares the core for device mode or host mode operation. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +-
                                                                                core_if Programming view of the DWC_otg controller
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 1199 of file dwc_otg_cil.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                void dwc_otg_cil_remove ( dwc_otg_core_if_t *  core_if  ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This function frees the structures allocated by dwc_otg_cil_init(). +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +-
                                                                                core_if The core interface pointer returned from dwc_otg_cil_init().
                                                                                +-
                                                                                +-

                                                                                +-Remove ADP Stuff +-

                                                                                +-Definition at line 285 of file dwc_otg_cil.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                void dwc_otg_enable_global_interrupts ( dwc_otg_core_if_t *  core_if  ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This function enables the controller's Global Interrupt in the AHB Config register. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +-
                                                                                core_if Programming view of DWC_otg controller.
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 322 of file dwc_otg_cil.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                void dwc_otg_disable_global_interrupts ( dwc_otg_core_if_t *  core_if  ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This function disables the controller's Global Interrupt in the AHB Config register. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +-
                                                                                core_if Programming view of DWC_otg controller.
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 335 of file dwc_otg_cil.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                int32_t dwc_otg_handle_common_intr ( void *  dev  ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This function should be called on every hardware interrupt. +-

                                                                                +-The common interrupts are those that occur in both Host and Device mode. This handler handles the following interrupts:

                                                                                  +-
                                                                                • Mode Mismatch Interrupt
                                                                                • Disconnect Interrupt
                                                                                • OTG Interrupt
                                                                                • Connector ID Status Change Interrupt
                                                                                • Session Request Interrupt.
                                                                                • Resume / Remote Wakeup Detected Interrupt.
                                                                                • LPM Transaction Received Interrupt
                                                                                • ADP Transaction Received Interrupt
                                                                                +- +-

                                                                                +-Definition at line 1275 of file dwc_otg_cil_intr.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                int dwc_otg_set_param_otg_cap ( dwc_otg_core_if_t *  core_if,
                                                                                int32_t  val
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Specifies the OTG capabilities. +-

                                                                                +-The driver will automatically detect the value for this parameter if none is specified. 0 - HNP and SRP capable (default) 1 - SRP Only capable 2 - No HNP/SRP capable +-

                                                                                +-Definition at line 5361 of file dwc_otg_cil.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                int dwc_otg_set_param_dma_enable ( dwc_otg_core_if_t *  core_if,
                                                                                int32_t  val
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Specifies whether to use slave or DMA mode for accessing the data FIFOs. +-

                                                                                +-The driver will automatically detect the value for this parameter if none is specified. 0 - Slave 1 - DMA (default, if available) +-

                                                                                +-Definition at line 5440 of file dwc_otg_cil.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                int dwc_otg_set_param_dma_desc_enable ( dwc_otg_core_if_t *  core_if,
                                                                                int32_t  val
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-When DMA mode is enabled specifies whether to use address DMA or DMA Descritor mode for accessing the data FIFOs in device mode. +-

                                                                                +-The driver will automatically detect the value for this parameter if none is specified. 0 - address DMA 1 - DMA Descriptor(default, if available) +-

                                                                                +-Definition at line 5470 of file dwc_otg_cil.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                int dwc_otg_set_param_dma_burst_size ( dwc_otg_core_if_t *  core_if,
                                                                                int32_t  val
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-The DMA Burst size (applicable only for External DMA Mode). +-

                                                                                +-1, 4, 8 16, 32, 64, 128, 256 (default 32) +-

                                                                                +-Definition at line 6275 of file dwc_otg_cil.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                int dwc_otg_set_param_speed ( dwc_otg_core_if_t *  core_if,
                                                                                int32_t  val
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Specifies the maximum speed of operation in host and device mode. +-

                                                                                +-The actual speed depends on the speed of the attached device and the value of phy_type. The actual speed depends on the speed of the attached device. 0 - High Speed (default) 1 - Full Speed +-

                                                                                +-Definition at line 5904 of file dwc_otg_cil.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                int dwc_otg_set_param_host_support_fs_ls_low_power ( dwc_otg_core_if_t *  core_if,
                                                                                int32_t  val
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Specifies whether low power mode is supported when attached to a Full Speed or Low Speed device in host mode. +-

                                                                                +-0 - Don't support low power mode (default) 1 - Support low power mode +-

                                                                                +-Definition at line 5500 of file dwc_otg_cil.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                int dwc_otg_set_param_host_ls_low_power_phy_clk ( dwc_otg_core_if_t *  core_if,
                                                                                int32_t  val
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Specifies the PHY clock rate in low power mode when connected to a Low Speed device in host mode. +-

                                                                                +-This parameter is applicable only if HOST_SUPPORT_FS_LS_LOW_POWER is enabled. If PHY_TYPE is set to FS then defaults to 6 MHZ otherwise 48 MHZ.

                                                                                +-0 - 48 MHz 1 - 6 MHz +-

                                                                                +-Definition at line 5933 of file dwc_otg_cil.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                int dwc_otg_set_param_data_fifo_size ( dwc_otg_core_if_t *  core_if,
                                                                                int32_t  val
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Total number of 4-byte words in the data FIFO memory. +-

                                                                                +-This memory includes the Rx FIFO, non-periodic Tx FIFO, and periodic Tx FIFOs. 32 to 32768 (default 8192) Note: The total FIFO memory depth in the FPGA configuration is 8192. +-

                                                                                +-Definition at line 5547 of file dwc_otg_cil.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                int dwc_otg_set_param_dev_rx_fifo_size ( dwc_otg_core_if_t *  core_if,
                                                                                int32_t  val
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Number of 4-byte words in the Rx FIFO in device mode when dynamic FIFO sizing is enabled. +-

                                                                                +-16 to 32768 (default 1064) +-

                                                                                +-Definition at line 5576 of file dwc_otg_cil.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                int dwc_otg_set_param_dev_nperio_tx_fifo_size ( dwc_otg_core_if_t *  core_if,
                                                                                int32_t  val
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Number of 4-byte words in the non-periodic Tx FIFO in device mode when dynamic FIFO sizing is enabled. +-

                                                                                +-16 to 32768 (default 1024) +-

                                                                                +-Definition at line 5602 of file dwc_otg_cil.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                int dwc_otg_set_param_dev_perio_tx_fifo_size ( dwc_otg_core_if_t *  core_if,
                                                                                int32_t  val,
                                                                                int  fifo_num
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Number of 4-byte words in each of the periodic Tx FIFOs in device mode when dynamic FIFO sizing is enabled. +-

                                                                                +-4 to 768 (default 256) +-

                                                                                +-Definition at line 6085 of file dwc_otg_cil.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                int dwc_otg_set_param_host_rx_fifo_size ( dwc_otg_core_if_t *  core_if,
                                                                                int32_t  val
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Number of 4-byte words in the Rx FIFO in host mode when dynamic FIFO sizing is enabled. +-

                                                                                +-16 to 32768 (default 1024) +-

                                                                                +-Definition at line 5635 of file dwc_otg_cil.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                int dwc_otg_set_param_host_nperio_tx_fifo_size ( dwc_otg_core_if_t *  core_if,
                                                                                int32_t  val
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Number of 4-byte words in the non-periodic Tx FIFO in host mode when Dynamic FIFO sizing is enabled in the core. +-

                                                                                +-16 to 32768 (default 1024) +-

                                                                                +-Definition at line 5667 of file dwc_otg_cil.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                int dwc_otg_set_param_host_perio_tx_fifo_size ( dwc_otg_core_if_t *  core_if,
                                                                                int32_t  val
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Number of 4-byte words in the host periodic Tx FIFO when dynamic FIFO sizing is enabled. +-

                                                                                +-16 to 32768 (default 1024) +-

                                                                                +-Definition at line 5700 of file dwc_otg_cil.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                int dwc_otg_set_param_max_transfer_size ( dwc_otg_core_if_t *  core_if,
                                                                                int32_t  val
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-The maximum transfer size supported in bytes. +-

                                                                                +-2047 to 65,535 (default 65,535) +-

                                                                                +-Definition at line 5731 of file dwc_otg_cil.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                int dwc_otg_set_param_max_packet_count ( dwc_otg_core_if_t *  core_if,
                                                                                int32_t  val
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-The maximum number of packets in a transfer. +-

                                                                                +-15 to 511 (default 511) +-

                                                                                +-Definition at line 5764 of file dwc_otg_cil.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                int dwc_otg_set_param_host_channels ( dwc_otg_core_if_t *  core_if,
                                                                                int32_t  val
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-The number of host channel registers to use. +-

                                                                                +-1 to 16 (default 12) Note: The FPGA configuration supports a maximum of 12 host channels. +-

                                                                                +-Definition at line 5795 of file dwc_otg_cil.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                int dwc_otg_set_param_dev_endpoints ( dwc_otg_core_if_t *  core_if,
                                                                                int32_t  val
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-The number of endpoints in addition to EP0 available for device mode operations. +-

                                                                                +-1 to 15 (default 6 IN and OUT) Note: The FPGA configuration supports a maximum of 6 IN and OUT endpoints in addition to EP0. +-

                                                                                +-Definition at line 5825 of file dwc_otg_cil.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                int dwc_otg_set_param_phy_type ( dwc_otg_core_if_t *  core_if,
                                                                                int32_t  val
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Specifies the type of PHY interface to use. +-

                                                                                +-By default, the driver will automatically detect the phy_type.

                                                                                +-0 - Full Speed PHY 1 - UTMI+ (default) 2 - ULPI +-

                                                                                +-Definition at line 5855 of file dwc_otg_cil.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                int dwc_otg_set_param_phy_utmi_width ( dwc_otg_core_if_t *  core_if,
                                                                                int32_t  val
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Specifies the UTMI+ Data Width. +-

                                                                                +-This parameter is applicable for a PHY_TYPE of UTMI+ or ULPI. (For a ULPI PHY_TYPE, this parameter indicates the data width between the MAC and the ULPI Wrapper.) Also, this parameter is applicable only if the OTG_HSPHY_WIDTH cC parameter was set to "8 and 16 bits", meaning that the core has been configured to work at either data path width.

                                                                                +-8 or 16 bits (default 16) +-

                                                                                +-Definition at line 6005 of file dwc_otg_cil.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                int dwc_otg_set_param_phy_ulpi_ddr ( dwc_otg_core_if_t *  core_if,
                                                                                int32_t  val
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Specifies whether the ULPI operates at double or single data rate. +-

                                                                                +-This parameter is only applicable if PHY_TYPE is ULPI.

                                                                                +-0 - single data rate ULPI interface with 8 bit wide data bus (default) 1 - double data rate ULPI interface with 4 bit wide data bus +-

                                                                                +-Definition at line 5970 of file dwc_otg_cil.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                int dwc_otg_set_param_i2c_enable ( dwc_otg_core_if_t *  core_if,
                                                                                int32_t  val
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Specifies whether to use the I2Cinterface for full speed PHY. +-

                                                                                +-This parameter is only applicable if PHY_TYPE is FS. 0 - No (default) 1 - Yes +-

                                                                                +-Definition at line 6056 of file dwc_otg_cil.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                int dwc_otg_set_param_dev_tx_fifo_size ( dwc_otg_core_if_t *  core_if,
                                                                                int  fifo_num,
                                                                                int32_t  val
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Number of 4-byte words in each of the Tx FIFOs in device mode when dynamic FIFO sizing is enabled. +-

                                                                                +-4 to 768 (default 256)

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                void dwc_otg_dump_dev_registers ( dwc_otg_core_if_t *  core_if  ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Dump core registers and SPRAM. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +-
                                                                                core_if Programming view of DWC_otg controller.
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 4620 of file dwc_otg_cil.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                void dwc_otg_dump_spram ( dwc_otg_core_if_t *  core_if  ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This functions reads the SPRAM and prints its content. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +-
                                                                                core_if Programming view of DWC_otg controller.
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 4756 of file dwc_otg_cil.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                void dwc_otg_dump_host_registers ( dwc_otg_core_if_t *  core_if  ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This function reads the host registers and prints them. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +-
                                                                                core_if Programming view of DWC_otg controller.
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 4784 of file dwc_otg_cil.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                void dwc_otg_dump_global_registers ( dwc_otg_core_if_t *  core_if  ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This function reads the core global registers and prints them. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +-
                                                                                core_if Programming view of DWC_otg controller.
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 4853 of file dwc_otg_cil.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                uint32_t dwc_otg_get_mode ( dwc_otg_core_if_t *  core_if  ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Get current mode. +-

                                                                                +-Returns 0 if in device mode, and 1 if in host mode. +-

                                                                                +-Definition at line 6653 of file dwc_otg_cil.c.

                                                                                +-

                                                                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__dbg_8h-source.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/dwc__otg__dbg_8h-source.html 2013-07-26 19:34:40.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,88 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_dbg.h Source File +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                dwc_otg_dbg.h

                                                                                Go to the documentation of this file.
                                                                                00001 /* ==========================================================================
+-00002  *
+-00003  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
+-00004  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
+-00005  * otherwise expressly agreed to in writing between Synopsys and you.
+-00006  * 
+-00007  * The Software IS NOT an item of Licensed Software or Licensed Product under
+-00008  * any End User Software License Agreement or Agreement for Licensed Product
+-00009  * with Synopsys or any supplement thereto. You are permitted to use and
+-00010  * redistribute this Software in source and binary forms, with or without
+-00011  * modification, provided that redistributions of source code must retain this
+-00012  * notice. You may not view, use, disclose, copy or distribute this file or
+-00013  * any information contained herein except pursuant to this license grant from
+-00014  * Synopsys. If you do not agree with this notice, including the disclaimer
+-00015  * below, then you are not authorized to use the Software.
+-00016  * 
+-00017  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
+-00018  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+-00019  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+-00020  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
+-00021  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+-00022  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+-00023  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+-00024  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+-00025  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+-00026  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+-00027  * DAMAGE.
+-00028  * ========================================================================== */
+-00029 
+-00030 #ifndef __DWC_OTG_DBG_H__
+-00031 #define __DWC_OTG_DBG_H__
+-00032 
+-00041 extern uint32_t g_dbg_lvl;
+-00045 static inline uint32_t SET_DEBUG_LEVEL(const uint32_t new)
+-00046 {
+-00047         uint32_t old = g_dbg_lvl;
+-00048         g_dbg_lvl = new;
+-00049         return old;
+-00050 }
+-00051 
+-00053 #define DBG_CIL         (0x2)
+-00054 
+-00056 #define DBG_CILV        (0x20)
+-00057 
+-00059 #define DBG_PCD         (0x4)
+-00060 
+-00062 #define DBG_PCDV        (0x40)
+-00063 
+-00064 #define DBG_HCD         (0x8)
+-00065 
+-00067 #define DBG_HCDV        (0x80)
+-00068 
+-00070 #define DBG_HCD_URB     (0x800)
+-00071 
+-00073 #define DBG_ANY         (0xFF)
+-00074 
+-00076 #define DBG_OFF         0
+-00077 
+-00079 #define USB_DWC "DWC_otg: "
+-00080 
+-00098 #ifdef DEBUG
+-00099 
+-00100 # define DWC_DEBUGPL(lvl, x...) do{ if ((lvl)&g_dbg_lvl)__DWC_DEBUG(USB_DWC x ); }while(0)
+-00101 # define DWC_DEBUGP(x...)       DWC_DEBUGPL(DBG_ANY, x )
+-00102 
+-00103 # define CHK_DEBUG_LEVEL(level) ((level) & g_dbg_lvl)
+-00104 
+-00105 #else
+-00106 
+-00107 # define DWC_DEBUGPL(lvl, x...) do{}while(0)
+-00108 # define DWC_DEBUGP(x...)
+-00109 
+-00110 # define CHK_DEBUG_LEVEL(level) (0)
+-00111 
+-00112 #endif /*DEBUG*/
+-00113 #endif
+-
                                                                                Generated on Thu Oct 27 03:56:37 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__dbg_8h.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/dwc__otg__dbg_8h.html 2013-07-26 19:34:40.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,129 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_dbg.h File Reference +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                dwc_otg_dbg.h File Reference

                                                                                This file defines debug levels. More... +-

                                                                                +- +-

                                                                                +-Go to the source code of this file. +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-

                                                                                Defines

                                                                                +-#define DBG_CIL   (0x2)
                                                                                 When debug level has the DBG_CIL bit set, display CIL Debug messages.
                                                                                +-#define DBG_CILV   (0x20)
                                                                                 When debug level has the DBG_CILV bit set, display CIL Verbose debug messages.
                                                                                +-#define DBG_PCD   (0x4)
                                                                                 When debug level has the DBG_PCD bit set, display PCD (Device) debug messages.
                                                                                +-#define DBG_PCDV   (0x40)
                                                                                 When debug level has the DBG_PCDV set, display PCD (Device) Verbose debug messages.
                                                                                +-#define DBG_HCD   (0x8)
                                                                                 When debug level has the DBG_HCD bit set, display Host debug messages.
                                                                                +-#define DBG_HCDV   (0x80)
                                                                                 When debug level has the DBG_HCDV bit set, display Verbose Host debug messages.
                                                                                +-#define DBG_HCD_URB   (0x800)
                                                                                 When debug level has the DBG_HCD_URB bit set, display enqueued URBs in host mode.
                                                                                +-#define DBG_ANY   (0xFF)
                                                                                 When debug level has any bit set, display debug messages.
                                                                                +-#define DBG_OFF   0
                                                                                 All debug messages off.
                                                                                +-#define USB_DWC   "DWC_otg: "
                                                                                 Prefix string for DWC_DEBUG print macros.
                                                                                #define DWC_DEBUGPL(lvl, x...)   do{}while(0)
                                                                                 Print a debug message when the Global debug level variable contains the bit defined in lvl.
                                                                                +-#define DWC_DEBUGP(x...)
                                                                                +-#define CHK_DEBUG_LEVEL(level)   (0)

                                                                                Functions

                                                                                +-uint32_t SET_DEBUG_LEVEL (const uint32_t new)
                                                                                 Set the Debug Level variable.

                                                                                Variables

                                                                                +-uint32_t g_dbg_lvl
                                                                                 The Debug Level bit-mask variable.
                                                                                +-

                                                                                Detailed Description

                                                                                +-This file defines debug levels. +-

                                                                                +-Debugging support vanishes in non-debug builds. +-

                                                                                +-Definition in file dwc_otg_dbg.h.

                                                                                Define Documentation

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                #define DWC_DEBUGPL ( lvl,
                                                                                x...   )    do{}while(0)
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Print a debug message when the Global debug level variable contains the bit defined in lvl. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +-
                                                                                [in] lvl - Debug level, use one of the DBG_ constants above.
                                                                                [in] x - like printf
                                                                                +-
                                                                                +-Example:

                                                                                +- DWC_DEBUGPL( DBG_ANY, "%s(%p)\n", __func__, _reg_base_addr);
                                                                                +- results in:
                                                                                +- usb-DWC_otg: dwc_otg_cil_init(ca867000) +-

                                                                                +-Definition at line 107 of file dwc_otg_dbg.h.

                                                                                +-

                                                                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__driver_8c-source.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/dwc__otg__driver_8c-source.html 2013-07-26 19:34:40.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,1141 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_driver.c Source File +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                dwc_otg_driver.c

                                                                                Go to the documentation of this file.
                                                                                00001 /* ==========================================================================
+-00002  * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_driver.c $
+-00003  * $Revision: #91 $
+-00004  * $Date: 2011/10/24 $
+-00005  * $Change: 1871159 $
+-00006  *
+-00007  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
+-00008  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
+-00009  * otherwise expressly agreed to in writing between Synopsys and you.
+-00010  *
+-00011  * The Software IS NOT an item of Licensed Software or Licensed Product under
+-00012  * any End User Software License Agreement or Agreement for Licensed Product
+-00013  * with Synopsys or any supplement thereto. You are permitted to use and
+-00014  * redistribute this Software in source and binary forms, with or without
+-00015  * modification, provided that redistributions of source code must retain this
+-00016  * notice. You may not view, use, disclose, copy or distribute this file or
+-00017  * any information contained herein except pursuant to this license grant from
+-00018  * Synopsys. If you do not agree with this notice, including the disclaimer
+-00019  * below, then you are not authorized to use the Software.
+-00020  *
+-00021  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
+-00022  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+-00023  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+-00024  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
+-00025  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+-00026  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+-00027  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+-00028  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+-00029  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+-00030  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+-00031  * DAMAGE.
+-00032  * ========================================================================== */
+-00033 
+-00051 #include "dwc_otg_os_dep.h"
+-00052 #include "dwc_os.h"
+-00053 #include "dwc_otg_dbg.h"
+-00054 #include "dwc_otg_driver.h"
+-00055 #include "dwc_otg_attr.h"
+-00056 #include "dwc_otg_core_if.h"
+-00057 #include "dwc_otg_pcd_if.h"
+-00058 #include "dwc_otg_hcd_if.h"
+-00059 
+-00060 #define DWC_DRIVER_VERSION      "2.94a 27-OCT-2011"
+-00061 #define DWC_DRIVER_DESC         "HS OTG USB Controller driver"
+-00062 
+-00063 static const char dwc_driver_name[] = "dwc_otg";
+-00064 
+-00065 extern int pcd_init(
+-00066 #ifdef LM_INTERFACE
+-00067                            struct lm_device *_dev
+-00068 #elif  defined(PCI_INTERFACE)
+-00069                            struct pci_dev *_dev
+-00070 #endif
+-00071     );
+-00072 extern int hcd_init(
+-00073 #ifdef LM_INTERFACE
+-00074                            struct lm_device *_dev
+-00075 #elif  defined(PCI_INTERFACE)
+-00076                            struct pci_dev *_dev
+-00077 #endif
+-00078     );
+-00079 
+-00080 extern int pcd_remove(
+-00081 #ifdef LM_INTERFACE
+-00082                              struct lm_device *_dev
+-00083 #elif  defined(PCI_INTERFACE)
+-00084                              struct pci_dev *_dev
+-00085 #endif
+-00086     );
+-00087 
+-00088 extern void hcd_remove(
+-00089 #ifdef LM_INTERFACE
+-00090                               struct lm_device *_dev
+-00091 #elif  defined(PCI_INTERFACE)
+-00092                               struct pci_dev *_dev
+-00093 #endif
+-00094     );
+-00095 
+-00096 extern void dwc_otg_adp_start(dwc_otg_core_if_t * core_if, uint8_t is_host);
+-00097 
+-00098 /*-------------------------------------------------------------------------*/
+-00099 /* Encapsulate the module parameter settings */
+-00100 
+-00101 struct dwc_otg_driver_module_params {
+-00102         int32_t opt;
+-00103         int32_t otg_cap;
+-00104         int32_t dma_enable;
+-00105         int32_t dma_desc_enable;
+-00106         int32_t dma_burst_size;
+-00107         int32_t speed;
+-00108         int32_t host_support_fs_ls_low_power;
+-00109         int32_t host_ls_low_power_phy_clk;
+-00110         int32_t enable_dynamic_fifo;
+-00111         int32_t data_fifo_size;
+-00112         int32_t dev_rx_fifo_size;
+-00113         int32_t dev_nperio_tx_fifo_size;
+-00114         uint32_t dev_perio_tx_fifo_size[MAX_PERIO_FIFOS];
+-00115         int32_t host_rx_fifo_size;
+-00116         int32_t host_nperio_tx_fifo_size;
+-00117         int32_t host_perio_tx_fifo_size;
+-00118         int32_t max_transfer_size;
+-00119         int32_t max_packet_count;
+-00120         int32_t host_channels;
+-00121         int32_t dev_endpoints;
+-00122         int32_t phy_type;
+-00123         int32_t phy_utmi_width;
+-00124         int32_t phy_ulpi_ddr;
+-00125         int32_t phy_ulpi_ext_vbus;
+-00126         int32_t i2c_enable;
+-00127         int32_t ulpi_fs_ls;
+-00128         int32_t ts_dline;
+-00129         int32_t en_multiple_tx_fifo;
+-00130         uint32_t dev_tx_fifo_size[MAX_TX_FIFOS];
+-00131         uint32_t thr_ctl;
+-00132         uint32_t tx_thr_length;
+-00133         uint32_t rx_thr_length;
+-00134         int32_t pti_enable;
+-00135         int32_t mpi_enable;
+-00136         int32_t lpm_enable;
+-00137         int32_t ic_usb_cap;
+-00138         int32_t ahb_thr_ratio;
+-00139         int32_t power_down;
+-00140         int32_t reload_ctl;
+-00141         int32_t dev_out_nak;
+-00142         int32_t cont_on_bna;
+-00143         int32_t ahb_single;
+-00144         int32_t otg_ver;
+-00145         int32_t adp_enable;
+-00146 };
+-00147 
+-00148 static struct dwc_otg_driver_module_params dwc_otg_module_params = {
+-00149         .opt = -1,
+-00150         .otg_cap = -1,
+-00151         .dma_enable = -1,
+-00152         .dma_desc_enable = -1,
+-00153         .dma_burst_size = -1,
+-00154         .speed = -1,
+-00155         .host_support_fs_ls_low_power = -1,
+-00156         .host_ls_low_power_phy_clk = -1,
+-00157         .enable_dynamic_fifo = -1,
+-00158         .data_fifo_size = -1,
+-00159         .dev_rx_fifo_size = -1,
+-00160         .dev_nperio_tx_fifo_size = -1,
+-00161         .dev_perio_tx_fifo_size = {
+-00162                                    /* dev_perio_tx_fifo_size_1 */
+-00163                                    -1,
+-00164                                    -1,
+-00165                                    -1,
+-00166                                    -1,
+-00167                                    -1,
+-00168                                    -1,
+-00169                                    -1,
+-00170                                    -1,
+-00171                                    -1,
+-00172                                    -1,
+-00173                                    -1,
+-00174                                    -1,
+-00175                                    -1,
+-00176                                    -1,
+-00177                                    -1
+-00178                                    /* 15 */
+-00179                                    },
+-00180         .host_rx_fifo_size = -1,
+-00181         .host_nperio_tx_fifo_size = -1,
+-00182         .host_perio_tx_fifo_size = -1,
+-00183         .max_transfer_size = -1,
+-00184         .max_packet_count = -1,
+-00185         .host_channels = -1,
+-00186         .dev_endpoints = -1,
+-00187         .phy_type = -1,
+-00188         .phy_utmi_width = -1,
+-00189         .phy_ulpi_ddr = -1,
+-00190         .phy_ulpi_ext_vbus = -1,
+-00191         .i2c_enable = -1,
+-00192         .ulpi_fs_ls = -1,
+-00193         .ts_dline = -1,
+-00194         .en_multiple_tx_fifo = -1,
+-00195         .dev_tx_fifo_size = {
+-00196                              /* dev_tx_fifo_size */
+-00197                              -1,
+-00198                              -1,
+-00199                              -1,
+-00200                              -1,
+-00201                              -1,
+-00202                              -1,
+-00203                              -1,
+-00204                              -1,
+-00205                              -1,
+-00206                              -1,
+-00207                              -1,
+-00208                              -1,
+-00209                              -1,
+-00210                              -1,
+-00211                              -1
+-00212                              /* 15 */
+-00213                              },
+-00214         .thr_ctl = -1,
+-00215         .tx_thr_length = -1,
+-00216         .rx_thr_length = -1,
+-00217         .pti_enable = -1,
+-00218         .mpi_enable = -1,
+-00219         .lpm_enable = -1,
+-00220         .ic_usb_cap = -1,
+-00221         .ahb_thr_ratio = -1,
+-00222         .power_down = -1,
+-00223         .reload_ctl = -1,
+-00224         .dev_out_nak = -1,
+-00225         .cont_on_bna = -1,
+-00226         .ahb_single = -1,
+-00227         .otg_ver = -1,
+-00228         .adp_enable = -1,
+-00229 };
+-00230 
+-00234 static ssize_t version_show(struct device_driver *dev, char *buf)
+-00235 {
+-00236         return snprintf(buf, sizeof(DWC_DRIVER_VERSION) + 2, "%s\n",
+-00237                         DWC_DRIVER_VERSION);
+-00238 }
+-00239 
+-00240 static DRIVER_ATTR(version, S_IRUGO, version_show, NULL);
+-00241 
+-00245 uint32_t g_dbg_lvl = 0;         /* OFF */
+-00246 
+-00250 static ssize_t dbg_level_show(struct device_driver *drv, char *buf)
+-00251 {
+-00252         return sprintf(buf, "0x%0x\n", g_dbg_lvl);
+-00253 }
+-00254 
+-00258 static ssize_t dbg_level_store(struct device_driver *drv, const char *buf,
+-00259                                size_t count)
+-00260 {
+-00261         g_dbg_lvl = simple_strtoul(buf, NULL, 16);
+-00262         return count;
+-00263 }
+-00264 
+-00265 static DRIVER_ATTR(debuglevel, S_IRUGO | S_IWUSR, dbg_level_show,
+-00266                    dbg_level_store);
+-00267 
+-00272 static int set_parameters(dwc_otg_core_if_t * core_if)
+-00273 {
+-00274         int retval = 0;
+-00275         int i;
+-00276 
+-00277         if (dwc_otg_module_params.otg_cap != -1) {
+-00278                 retval +=
+-00279                     dwc_otg_set_param_otg_cap(core_if,
+-00280                                               dwc_otg_module_params.otg_cap);
+-00281         }
+-00282         if (dwc_otg_module_params.dma_enable != -1) {
+-00283                 retval +=
+-00284                     dwc_otg_set_param_dma_enable(core_if,
+-00285                                                  dwc_otg_module_params.
+-00286                                                  dma_enable);
+-00287         }
+-00288         if (dwc_otg_module_params.dma_desc_enable != -1) {
+-00289                 retval +=
+-00290                     dwc_otg_set_param_dma_desc_enable(core_if,
+-00291                                                       dwc_otg_module_params.
+-00292                                                       dma_desc_enable);
+-00293         }
+-00294         if (dwc_otg_module_params.opt != -1) {
+-00295                 retval +=
+-00296                     dwc_otg_set_param_opt(core_if, dwc_otg_module_params.opt);
+-00297         }
+-00298         if (dwc_otg_module_params.dma_burst_size != -1) {
+-00299                 retval +=
+-00300                     dwc_otg_set_param_dma_burst_size(core_if,
+-00301                                                      dwc_otg_module_params.
+-00302                                                      dma_burst_size);
+-00303         }
+-00304         if (dwc_otg_module_params.host_support_fs_ls_low_power != -1) {
+-00305                 retval +=
+-00306                     dwc_otg_set_param_host_support_fs_ls_low_power(core_if,
+-00307                                                                    dwc_otg_module_params.
+-00308                                                                    host_support_fs_ls_low_power);
+-00309         }
+-00310         if (dwc_otg_module_params.enable_dynamic_fifo != -1) {
+-00311                 retval +=
+-00312                     dwc_otg_set_param_enable_dynamic_fifo(core_if,
+-00313                                                           dwc_otg_module_params.
+-00314                                                           enable_dynamic_fifo);
+-00315         }
+-00316         if (dwc_otg_module_params.data_fifo_size != -1) {
+-00317                 retval +=
+-00318                     dwc_otg_set_param_data_fifo_size(core_if,
+-00319                                                      dwc_otg_module_params.
+-00320                                                      data_fifo_size);
+-00321         }
+-00322         if (dwc_otg_module_params.dev_rx_fifo_size != -1) {
+-00323                 retval +=
+-00324                     dwc_otg_set_param_dev_rx_fifo_size(core_if,
+-00325                                                        dwc_otg_module_params.
+-00326                                                        dev_rx_fifo_size);
+-00327         }
+-00328         if (dwc_otg_module_params.dev_nperio_tx_fifo_size != -1) {
+-00329                 retval +=
+-00330                     dwc_otg_set_param_dev_nperio_tx_fifo_size(core_if,
+-00331                                                               dwc_otg_module_params.
+-00332                                                               dev_nperio_tx_fifo_size);
+-00333         }
+-00334         if (dwc_otg_module_params.host_rx_fifo_size != -1) {
+-00335                 retval +=
+-00336                     dwc_otg_set_param_host_rx_fifo_size(core_if,
+-00337                                                         dwc_otg_module_params.host_rx_fifo_size);
+-00338         }
+-00339         if (dwc_otg_module_params.host_nperio_tx_fifo_size != -1) {
+-00340                 retval +=
+-00341                     dwc_otg_set_param_host_nperio_tx_fifo_size(core_if,
+-00342                                                                dwc_otg_module_params.
+-00343                                                                host_nperio_tx_fifo_size);
+-00344         }
+-00345         if (dwc_otg_module_params.host_perio_tx_fifo_size != -1) {
+-00346                 retval +=
+-00347                     dwc_otg_set_param_host_perio_tx_fifo_size(core_if,
+-00348                                                               dwc_otg_module_params.
+-00349                                                               host_perio_tx_fifo_size);
+-00350         }
+-00351         if (dwc_otg_module_params.max_transfer_size != -1) {
+-00352                 retval +=
+-00353                     dwc_otg_set_param_max_transfer_size(core_if,
+-00354                                                         dwc_otg_module_params.
+-00355                                                         max_transfer_size);
+-00356         }
+-00357         if (dwc_otg_module_params.max_packet_count != -1) {
+-00358                 retval +=
+-00359                     dwc_otg_set_param_max_packet_count(core_if,
+-00360                                                        dwc_otg_module_params.
+-00361                                                        max_packet_count);
+-00362         }
+-00363         if (dwc_otg_module_params.host_channels != -1) {
+-00364                 retval +=
+-00365                     dwc_otg_set_param_host_channels(core_if,
+-00366                                                     dwc_otg_module_params.
+-00367                                                     host_channels);
+-00368         }
+-00369         if (dwc_otg_module_params.dev_endpoints != -1) {
+-00370                 retval +=
+-00371                     dwc_otg_set_param_dev_endpoints(core_if,
+-00372                                                     dwc_otg_module_params.
+-00373                                                     dev_endpoints);
+-00374         }
+-00375         if (dwc_otg_module_params.phy_type != -1) {
+-00376                 retval +=
+-00377                     dwc_otg_set_param_phy_type(core_if,
+-00378                                                dwc_otg_module_params.phy_type);
+-00379         }
+-00380         if (dwc_otg_module_params.speed != -1) {
+-00381                 retval +=
+-00382                     dwc_otg_set_param_speed(core_if,
+-00383                                             dwc_otg_module_params.speed);
+-00384         }
+-00385         if (dwc_otg_module_params.host_ls_low_power_phy_clk != -1) {
+-00386                 retval +=
+-00387                     dwc_otg_set_param_host_ls_low_power_phy_clk(core_if,
+-00388                                                                 dwc_otg_module_params.
+-00389                                                                 host_ls_low_power_phy_clk);
+-00390         }
+-00391         if (dwc_otg_module_params.phy_ulpi_ddr != -1) {
+-00392                 retval +=
+-00393                     dwc_otg_set_param_phy_ulpi_ddr(core_if,
+-00394                                                    dwc_otg_module_params.
+-00395                                                    phy_ulpi_ddr);
+-00396         }
+-00397         if (dwc_otg_module_params.phy_ulpi_ext_vbus != -1) {
+-00398                 retval +=
+-00399                     dwc_otg_set_param_phy_ulpi_ext_vbus(core_if,
+-00400                                                         dwc_otg_module_params.
+-00401                                                         phy_ulpi_ext_vbus);
+-00402         }
+-00403         if (dwc_otg_module_params.phy_utmi_width != -1) {
+-00404                 retval +=
+-00405                     dwc_otg_set_param_phy_utmi_width(core_if,
+-00406                                                      dwc_otg_module_params.
+-00407                                                      phy_utmi_width);
+-00408         }
+-00409         if (dwc_otg_module_params.ulpi_fs_ls != -1) {
+-00410                 retval +=
+-00411                     dwc_otg_set_param_ulpi_fs_ls(core_if,
+-00412                                                  dwc_otg_module_params.ulpi_fs_ls);
+-00413         }
+-00414         if (dwc_otg_module_params.ts_dline != -1) {
+-00415                 retval +=
+-00416                     dwc_otg_set_param_ts_dline(core_if,
+-00417                                                dwc_otg_module_params.ts_dline);
+-00418         }
+-00419         if (dwc_otg_module_params.i2c_enable != -1) {
+-00420                 retval +=
+-00421                     dwc_otg_set_param_i2c_enable(core_if,
+-00422                                                  dwc_otg_module_params.
+-00423                                                  i2c_enable);
+-00424         }
+-00425         if (dwc_otg_module_params.en_multiple_tx_fifo != -1) {
+-00426                 retval +=
+-00427                     dwc_otg_set_param_en_multiple_tx_fifo(core_if,
+-00428                                                           dwc_otg_module_params.
+-00429                                                           en_multiple_tx_fifo);
+-00430         }
+-00431         for (i = 0; i < 15; i++) {
+-00432                 if (dwc_otg_module_params.dev_perio_tx_fifo_size[i] != -1) {
+-00433                         retval +=
+-00434                             dwc_otg_set_param_dev_perio_tx_fifo_size(core_if,
+-00435                                                                      dwc_otg_module_params.
+-00436                                                                      dev_perio_tx_fifo_size
+-00437                                                                      [i], i);
+-00438                 }
+-00439         }
+-00440 
+-00441         for (i = 0; i < 15; i++) {
+-00442                 if (dwc_otg_module_params.dev_tx_fifo_size[i] != -1) {
+-00443                         retval += dwc_otg_set_param_dev_tx_fifo_size(core_if,
+-00444                                                                      dwc_otg_module_params.
+-00445                                                                      dev_tx_fifo_size
+-00446                                                                      [i], i);
+-00447                 }
+-00448         }
+-00449         if (dwc_otg_module_params.thr_ctl != -1) {
+-00450                 retval +=
+-00451                     dwc_otg_set_param_thr_ctl(core_if,
+-00452                                               dwc_otg_module_params.thr_ctl);
+-00453         }
+-00454         if (dwc_otg_module_params.mpi_enable != -1) {
+-00455                 retval +=
+-00456                     dwc_otg_set_param_mpi_enable(core_if,
+-00457                                                  dwc_otg_module_params.
+-00458                                                  mpi_enable);
+-00459         }
+-00460         if (dwc_otg_module_params.pti_enable != -1) {
+-00461                 retval +=
+-00462                     dwc_otg_set_param_pti_enable(core_if,
+-00463                                                  dwc_otg_module_params.
+-00464                                                  pti_enable);
+-00465         }
+-00466         if (dwc_otg_module_params.lpm_enable != -1) {
+-00467                 retval +=
+-00468                     dwc_otg_set_param_lpm_enable(core_if,
+-00469                                                  dwc_otg_module_params.
+-00470                                                  lpm_enable);
+-00471         }
+-00472         if (dwc_otg_module_params.ic_usb_cap != -1) {
+-00473                 retval +=
+-00474                     dwc_otg_set_param_ic_usb_cap(core_if,
+-00475                                                  dwc_otg_module_params.
+-00476                                                  ic_usb_cap);
+-00477         }
+-00478         if (dwc_otg_module_params.tx_thr_length != -1) {
+-00479                 retval +=
+-00480                     dwc_otg_set_param_tx_thr_length(core_if,
+-00481                                                     dwc_otg_module_params.tx_thr_length);
+-00482         }
+-00483         if (dwc_otg_module_params.rx_thr_length != -1) {
+-00484                 retval +=
+-00485                     dwc_otg_set_param_rx_thr_length(core_if,
+-00486                                                     dwc_otg_module_params.
+-00487                                                     rx_thr_length);
+-00488         }
+-00489         if (dwc_otg_module_params.ahb_thr_ratio != -1) {
+-00490                 retval +=
+-00491                     dwc_otg_set_param_ahb_thr_ratio(core_if,
+-00492                                                     dwc_otg_module_params.ahb_thr_ratio);
+-00493         }
+-00494         if (dwc_otg_module_params.power_down != -1) {
+-00495                 retval +=
+-00496                     dwc_otg_set_param_power_down(core_if,
+-00497                                                  dwc_otg_module_params.power_down);
+-00498         }
+-00499         if (dwc_otg_module_params.reload_ctl != -1) {
+-00500                 retval +=
+-00501                     dwc_otg_set_param_reload_ctl(core_if,
+-00502                                                  dwc_otg_module_params.reload_ctl);
+-00503         }
+-00504 
+-00505         if (dwc_otg_module_params.dev_out_nak != -1) {
+-00506                 retval +=
+-00507                         dwc_otg_set_param_dev_out_nak(core_if,
+-00508                         dwc_otg_module_params.dev_out_nak);
+-00509         }
+-00510 
+-00511         if (dwc_otg_module_params.cont_on_bna != -1) {
+-00512                 retval +=
+-00513                         dwc_otg_set_param_cont_on_bna(core_if,
+-00514                         dwc_otg_module_params.cont_on_bna);
+-00515         }
+-00516 
+-00517         if (dwc_otg_module_params.ahb_single != -1) {
+-00518                 retval +=
+-00519                         dwc_otg_set_param_ahb_single(core_if,
+-00520                         dwc_otg_module_params.ahb_single);
+-00521         }
+-00522 
+-00523         if (dwc_otg_module_params.otg_ver != -1) {
+-00524                 retval +=
+-00525                     dwc_otg_set_param_otg_ver(core_if,
+-00526                                               dwc_otg_module_params.otg_ver);
+-00527         }
+-00528         if (dwc_otg_module_params.adp_enable != -1) {
+-00529                 retval +=
+-00530                     dwc_otg_set_param_adp_enable(core_if,
+-00531                                                  dwc_otg_module_params.
+-00532                                                  adp_enable);
+-00533         }
+-00534         return retval;
+-00535 }
+-00536 
+-00541 static irqreturn_t dwc_otg_common_irq(int irq, void *dev)
+-00542 {
+-00543         int32_t retval = IRQ_NONE;
+-00544 
+-00545         retval = dwc_otg_handle_common_intr(dev);
+-00546         if (retval != 0) {
+-00547                 S3C2410X_CLEAR_EINTPEND();
+-00548         }
+-00549         return IRQ_RETVAL(retval);
+-00550 }
+-00551 
+-00561 static void dwc_otg_driver_remove(
+-00562 #ifdef LM_INTERFACE
+-00563                                          struct lm_device *_dev
+-00564 #elif defined(PCI_INTERFACE)
+-00565                                          struct pci_dev *_dev
+-00566 #endif
+-00567     )
+-00568 {
+-00569 #ifdef LM_INTERFACE
+-00570         dwc_otg_device_t *otg_dev = lm_get_drvdata(_dev);
+-00571 #elif defined(PCI_INTERFACE)
+-00572         dwc_otg_device_t *otg_dev = pci_get_drvdata(_dev);
+-00573 #endif
+-00574 
+-00575         DWC_DEBUGPL(DBG_ANY, "%s(%p)\n", __func__, _dev);
+-00576 
+-00577         if (!otg_dev) {
+-00578                 /* Memory allocation for the dwc_otg_device failed. */
+-00579                 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev NULL!\n", __func__);
+-00580                 return;
+-00581         }
+-00582 #ifndef DWC_DEVICE_ONLY
+-00583         if (otg_dev->hcd) {
+-00584                 hcd_remove(_dev);
+-00585         } else {
+-00586                 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->hcd NULL!\n", __func__);
+-00587                 return;
+-00588         }
+-00589 #endif
+-00590 
+-00591 #ifndef DWC_HOST_ONLY
+-00592         if (otg_dev->pcd) {
+-00593                 pcd_remove(_dev);
+-00594         } else {
+-00595                 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->pcd NULL!\n", __func__);
+-00596                 return;
+-00597         }
+-00598 #endif
+-00599         /*
+-00600          * Free the IRQ
+-00601          */
+-00602         if (otg_dev->common_irq_installed) {
+-00603                 free_irq(_dev->irq, otg_dev);
+-00604         } else {
+-00605                 DWC_DEBUGPL(DBG_ANY, "%s: There is no installed irq!\n", __func__);
+-00606                 return;
+-00607         }
+-00608 
+-00609         if (otg_dev->core_if) {
+-00610                 dwc_otg_cil_remove(otg_dev->core_if);
+-00611         } else {
+-00612                 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->core_if NULL!\n", __func__);
+-00613                 return;
+-00614         }
+-00615 
+-00616         /*
+-00617          * Remove the device attributes
+-00618          */
+-00619         dwc_otg_attr_remove(_dev);
+-00620 
+-00621         /*
+-00622          * Return the memory.
+-00623          */
+-00624         if (otg_dev->os_dep.base) {
+-00625                 iounmap(otg_dev->os_dep.base);
+-00626         }
+-00627         DWC_FREE(otg_dev);
+-00628 
+-00629         /*
+-00630          * Clear the drvdata pointer.
+-00631          */
+-00632 #ifdef LM_INTERFACE
+-00633         lm_set_drvdata(_dev, 0);
+-00634 #elif defined(PCI_INTERFACE)
+-00635     release_mem_region(otg_dev->os_dep.rsrc_start, otg_dev->os_dep.rsrc_len);
+-00636         pci_set_drvdata(_dev, 0);
+-00637 #endif
+-00638 }
+-00639 
+-00651 static int dwc_otg_driver_probe(
+-00652 #ifdef LM_INTERFACE
+-00653                                        struct lm_device *_dev
+-00654 #elif defined(PCI_INTERFACE)
+-00655                                        struct pci_dev *_dev,
+-00656                                        const struct pci_device_id *id
+-00657 #endif
+-00658     )
+-00659 {
+-00660         int retval = 0;
+-00661         dwc_otg_device_t *dwc_otg_device;
+-00662 
+-00663         dev_dbg(&_dev->dev, "dwc_otg_driver_probe(%p)\n", _dev);
+-00664 #ifdef LM_INTERFACE
+-00665         dev_dbg(&_dev->dev, "start=0x%08x\n", (unsigned)_dev->resource.start);
+-00666 #elif defined(PCI_INTERFACE)
+-00667         if (!id) {
+-00668                 DWC_ERROR("Invalid pci_device_id %p", id);
+-00669                 return -EINVAL;
+-00670         }
+-00671 
+-00672         if (!_dev || (pci_enable_device(_dev) < 0)) {
+-00673                 DWC_ERROR("Invalid pci_device %p", _dev);
+-00674                 return -ENODEV;
+-00675         }
+-00676         dev_dbg(&_dev->dev, "start=0x%08x\n", (unsigned)pci_resource_start(_dev,0));
+-00677         /* other stuff needed as well? */
+-00678 
+-00679 #endif
+-00680 
+-00681         dwc_otg_device = DWC_ALLOC(sizeof(dwc_otg_device_t));
+-00682 
+-00683         if (!dwc_otg_device) {
+-00684                 dev_err(&_dev->dev, "kmalloc of dwc_otg_device failed\n");
+-00685                 return -ENOMEM;
+-00686         }
+-00687 
+-00688         memset(dwc_otg_device, 0, sizeof(*dwc_otg_device));
+-00689         dwc_otg_device->os_dep.reg_offset = 0xFFFFFFFF;
+-00690 
+-00691         /*
+-00692          * Map the DWC_otg Core memory into virtual address space.
+-00693          */
+-00694 #ifdef LM_INTERFACE
+-00695         dwc_otg_device->os_dep.base = ioremap(_dev->resource.start, SZ_256K);
+-00696 
+-00697         if (!dwc_otg_device->os_dep.base) {
+-00698                 dev_err(&_dev->dev, "ioremap() failed\n");
+-00699                 DWC_FREE(dwc_otg_device);
+-00700                 return -ENOMEM;
+-00701         }
+-00702         dev_dbg(&_dev->dev, "base=0x%08x\n",
+-00703                 (unsigned)dwc_otg_device->os_dep.base);
+-00704 #elif defined(PCI_INTERFACE)
+-00705         _dev->current_state = PCI_D0;
+-00706         _dev->dev.power.power_state = PMSG_ON;
+-00707 
+-00708         if (!_dev->irq) {
+-00709                 DWC_ERROR("Found HC with no IRQ. Check BIOS/PCI %s setup!",
+-00710                           pci_name(_dev));
+-00711                 iounmap(dwc_otg_device->os_dep.base);
+-00712                 DWC_FREE(dwc_otg_device);
+-00713                 return -ENODEV;
+-00714         }
+-00715 
+-00716         dwc_otg_device->os_dep.rsrc_start = pci_resource_start(_dev, 0);
+-00717         dwc_otg_device->os_dep.rsrc_len = pci_resource_len(_dev, 0);
+-00718         DWC_DEBUGPL(DBG_ANY, "PCI resource: start=%08x, len=%08x\n",
+-00719                     (unsigned)dwc_otg_device->os_dep.rsrc_start,
+-00720                     (unsigned)dwc_otg_device->os_dep.rsrc_len);
+-00721         if (!request_mem_region
+-00722             (dwc_otg_device->os_dep.rsrc_start, dwc_otg_device->os_dep.rsrc_len,
+-00723              "dwc_otg")) {
+-00724                 dev_dbg(&_dev->dev, "error requesting memory\n");
+-00725                 iounmap(dwc_otg_device->os_dep.base);
+-00726                 DWC_FREE(dwc_otg_device);
+-00727                 return -EFAULT;
+-00728         }
+-00729 
+-00730         dwc_otg_device->os_dep.base =
+-00731             ioremap_nocache(dwc_otg_device->os_dep.rsrc_start,
+-00732                             dwc_otg_device->os_dep.rsrc_len);
+-00733         if (dwc_otg_device->os_dep.base == NULL) {
+-00734                 dev_dbg(&_dev->dev, "error mapping memory\n");
+-00735                 release_mem_region(dwc_otg_device->os_dep.rsrc_start,
+-00736                                    dwc_otg_device->os_dep.rsrc_len);
+-00737                 iounmap(dwc_otg_device->os_dep.base);
+-00738                 DWC_FREE(dwc_otg_device);
+-00739                 return -EFAULT;
+-00740         }
+-00741         dev_dbg(&_dev->dev, "base=0x%p (before adjust) \n",
+-00742                 dwc_otg_device->os_dep.base);
+-00743         dwc_otg_device->os_dep.base = (char *)dwc_otg_device->os_dep.base;
+-00744         dev_dbg(&_dev->dev, "base=0x%p (after adjust) \n",
+-00745                 dwc_otg_device->os_dep.base);
+-00746         dev_dbg(&_dev->dev, "%s: mapped PA 0x%x to VA 0x%p\n", __func__,
+-00747                 (unsigned)dwc_otg_device->os_dep.rsrc_start,
+-00748                 dwc_otg_device->os_dep.base);
+-00749 
+-00750         pci_set_master(_dev);
+-00751         pci_set_drvdata(_dev, dwc_otg_device);
+-00752 #endif
+-00753 
+-00754         /*
+-00755          * Initialize driver data to point to the global DWC_otg
+-00756          * Device structure.
+-00757          */
+-00758 #ifdef LM_INTERFACE
+-00759         lm_set_drvdata(_dev, dwc_otg_device);
+-00760 #endif
+-00761         dev_dbg(&_dev->dev, "dwc_otg_device=0x%p\n", dwc_otg_device);
+-00762 
+-00763         dwc_otg_device->core_if = dwc_otg_cil_init(dwc_otg_device->os_dep.base);
+-00764         if (!dwc_otg_device->core_if) {
+-00765                 dev_err(&_dev->dev, "CIL initialization failed!\n");
+-00766                 retval = -ENOMEM;
+-00767                 goto fail;
+-00768         }
+-00769 
+-00770         /*
+-00771          * Attempt to ensure this device is really a DWC_otg Controller.
+-00772          * Read and verify the SNPSID register contents. The value should be
+-00773          * 0x45F42XXX, which corresponds to "OT2", as in "OTG version 2.XX".
+-00774          */
+-00775 
+-00776         if ((dwc_otg_get_gsnpsid(dwc_otg_device->core_if) & 0xFFFFF000) !=
+-00777             0x4F542000) {
+-00778                 dev_err(&_dev->dev, "Bad value for SNPSID: 0x%08x\n",
+-00779                         dwc_otg_get_gsnpsid(dwc_otg_device->core_if));
+-00780                 retval = -EINVAL;
+-00781                 goto fail;
+-00782         }
+-00783 
+-00784         /*
+-00785          * Validate parameter values.
+-00786          */
+-00787         if (set_parameters(dwc_otg_device->core_if)) {
+-00788                 retval = -EINVAL;
+-00789                 goto fail;
+-00790         }
+-00791 
+-00792         /*
+-00793          * Create Device Attributes in sysfs
+-00794          */
+-00795         dwc_otg_attr_create(_dev);
+-00796 
+-00797         /*
+-00798          * Disable the global interrupt until all the interrupt
+-00799          * handlers are installed.
+-00800          */
+-00801         dwc_otg_disable_global_interrupts(dwc_otg_device->core_if);
+-00802 
+-00803         /*
+-00804          * Install the interrupt handler for the common interrupts before
+-00805          * enabling common interrupts in core_init below.
+-00806          */
+-00807         DWC_DEBUGPL(DBG_CIL, "registering (common) handler for irq%d\n",
+-00808                     _dev->irq);
+-00809         retval = request_irq(_dev->irq, dwc_otg_common_irq,
+-00810                              IRQF_SHARED | IRQF_DISABLED | IRQ_LEVEL, "dwc_otg",
+-00811                              dwc_otg_device);
+-00812         if (retval) {
+-00813                 DWC_ERROR("request of irq%d failed\n", _dev->irq);
+-00814                 retval = -EBUSY;
+-00815                 goto fail;
+-00816         } else {
+-00817                 dwc_otg_device->common_irq_installed = 1;
+-00818         }
+-00819 
+-00820 #ifdef LM_INTERFACE
+-00821         set_irq_type(_dev->irq, IRQT_LOW);
+-00822 #endif
+-00823         /*
+-00824          * Initialize the DWC_otg core.
+-00825          */
+-00826         dwc_otg_core_init(dwc_otg_device->core_if);
+-00827                 
+-00828 #ifndef DWC_HOST_ONLY
+-00829         /*
+-00830          * Initialize the PCD
+-00831          */
+-00832         retval = pcd_init(_dev);
+-00833         if (retval != 0) {
+-00834                 DWC_ERROR("pcd_init failed\n");
+-00835                 dwc_otg_device->pcd = NULL;
+-00836                 goto fail;
+-00837         }       
+-00838 #endif
+-00839 #ifndef DWC_DEVICE_ONLY
+-00840         /*
+-00841          * Initialize the HCD
+-00842          */
+-00843         retval = hcd_init(_dev);
+-00844         if (retval != 0) {
+-00845                 DWC_ERROR("hcd_init failed\n");
+-00846                 dwc_otg_device->hcd = NULL;
+-00847                 goto fail;
+-00848         }
+-00849 #endif
+-00850 #ifdef PCI_INTERFACE
+-00851         pci_set_drvdata(_dev, dwc_otg_device);
+-00852         dwc_otg_device->os_dep.pcidev = _dev;
+-00853 #endif
+-00854 
+-00855         /*
+-00856          * Enable the global interrupt after all the interrupt
+-00857          * handlers are installed if there is no ADP support else 
+-00858          * perform initial actions required for Internal ADP logic.
+-00859          */
+-00860         if (!dwc_otg_get_param_adp_enable(dwc_otg_device->core_if))     
+-00861                 dwc_otg_enable_global_interrupts(dwc_otg_device->core_if);
+-00862         else
+-00863                 dwc_otg_adp_start(dwc_otg_device->core_if, 
+-00864                                                         dwc_otg_is_host_mode(dwc_otg_device->core_if));
+-00865 
+-00866         return 0;
+-00867 
+-00868 fail:
+-00869         dwc_otg_driver_remove(_dev);
+-00870         return retval;
+-00871 }
+-00872 
+-00884 #ifdef LM_INTERFACE
+-00885 static struct lm_driver dwc_otg_driver = {
+-00886         .drv = {.name = (char *)dwc_driver_name,},
+-00887         .probe = dwc_otg_driver_probe,
+-00888         .remove = dwc_otg_driver_remove,
+-00889 };
+-00890 #elif defined(PCI_INTERFACE)
+-00891 static const struct pci_device_id pci_ids[] = { {
+-00892                                                  PCI_DEVICE(0x16c3, 0xabcd),
+-00893                                                  .driver_data =
+-00894                                                  (unsigned long)0xdeadbeef,
+-00895                                                  }, { /* end: all zeroes */ }
+-00896 };
+-00897 
+-00898 MODULE_DEVICE_TABLE(pci, pci_ids);
+-00899 
+-00900 /* pci driver glue; this is a "new style" PCI driver module */
+-00901 static struct pci_driver dwc_otg_driver = {
+-00902         .name = "dwc_otg",
+-00903         .id_table = pci_ids,
+-00904 
+-00905         .probe = dwc_otg_driver_probe,
+-00906         .remove = dwc_otg_driver_remove,
+-00907 
+-00908         .driver = {
+-00909                    .name = (char *)dwc_driver_name,
+-00910                    },
+-00911 };
+-00912 #endif
+-00913 
+-00924 static int __init dwc_otg_driver_init(void)
+-00925 {
+-00926         int retval = 0;
+-00927         int error;
+-00928         printk(KERN_INFO "%s: version %s\n", dwc_driver_name,
+-00929                DWC_DRIVER_VERSION);
+-00930 #ifdef LM_INTERFACE
+-00931         retval = lm_driver_register(&dwc_otg_driver);
+-00932 #elif defined(PCI_INTERFACE)
+-00933         retval = pci_register_driver(&dwc_otg_driver);
+-00934 #endif
+-00935         if (retval < 0) {
+-00936                 printk(KERN_ERR "%s retval=%d\n", __func__, retval);
+-00937                 return retval;
+-00938         }
+-00939 #ifdef LM_INTERFACE
+-00940         error = driver_create_file(&dwc_otg_driver.drv, &driver_attr_version);
+-00941         error = driver_create_file(&dwc_otg_driver.drv, &driver_attr_debuglevel);
+-00942 #elif defined(PCI_INTERFACE)
+-00943         error = driver_create_file(&dwc_otg_driver.driver, &driver_attr_version);
+-00944         error = driver_create_file(&dwc_otg_driver.driver, &driver_attr_debuglevel);
+-00945 #endif
+-00946         return retval;
+-00947 }
+-00948 
+-00949 module_init(dwc_otg_driver_init);
+-00950 
+-00957 static void __exit dwc_otg_driver_cleanup(void)
+-00958 {
+-00959         printk(KERN_DEBUG "dwc_otg_driver_cleanup()\n");
+-00960 
+-00961 #ifdef LM_INTERFACE
+-00962         driver_remove_file(&dwc_otg_driver.drv, &driver_attr_debuglevel);
+-00963         driver_remove_file(&dwc_otg_driver.drv, &driver_attr_version);
+-00964         lm_driver_unregister(&dwc_otg_driver);
+-00965 #elif defined(PCI_INTERFACE)
+-00966         driver_remove_file(&dwc_otg_driver.driver, &driver_attr_debuglevel);
+-00967         driver_remove_file(&dwc_otg_driver.driver, &driver_attr_version);
+-00968         pci_unregister_driver(&dwc_otg_driver);
+-00969 #endif
+-00970 
+-00971         printk(KERN_INFO "%s module removed\n", dwc_driver_name);
+-00972 }
+-00973 
+-00974 module_exit(dwc_otg_driver_cleanup);
+-00975 
+-00976 MODULE_DESCRIPTION(DWC_DRIVER_DESC);
+-00977 MODULE_AUTHOR("Synopsys Inc.");
+-00978 MODULE_LICENSE("GPL");
+-00979 
+-00980 module_param_named(otg_cap, dwc_otg_module_params.otg_cap, int, 0444);
+-00981 MODULE_PARM_DESC(otg_cap, "OTG Capabilities 0=HNP&SRP 1=SRP Only 2=None");
+-00982 module_param_named(opt, dwc_otg_module_params.opt, int, 0444);
+-00983 MODULE_PARM_DESC(opt, "OPT Mode");
+-00984 module_param_named(dma_enable, dwc_otg_module_params.dma_enable, int, 0444);
+-00985 MODULE_PARM_DESC(dma_enable, "DMA Mode 0=Slave 1=DMA enabled");
+-00986 
+-00987 module_param_named(dma_desc_enable, dwc_otg_module_params.dma_desc_enable, int,
+-00988                    0444);
+-00989 MODULE_PARM_DESC(dma_desc_enable,
+-00990                  "DMA Desc Mode 0=Address DMA 1=DMA Descriptor enabled");
+-00991 
+-00992 module_param_named(dma_burst_size, dwc_otg_module_params.dma_burst_size, int,
+-00993                    0444);
+-00994 MODULE_PARM_DESC(dma_burst_size,
+-00995                  "DMA Burst Size 1, 4, 8, 16, 32, 64, 128, 256");
+-00996 module_param_named(speed, dwc_otg_module_params.speed, int, 0444);
+-00997 MODULE_PARM_DESC(speed, "Speed 0=High Speed 1=Full Speed");
+-00998 module_param_named(host_support_fs_ls_low_power,
+-00999                    dwc_otg_module_params.host_support_fs_ls_low_power, int,
+-01000                    0444);
+-01001 MODULE_PARM_DESC(host_support_fs_ls_low_power,
+-01002                  "Support Low Power w/FS or LS 0=Support 1=Don't Support");
+-01003 module_param_named(host_ls_low_power_phy_clk,
+-01004                    dwc_otg_module_params.host_ls_low_power_phy_clk, int, 0444);
+-01005 MODULE_PARM_DESC(host_ls_low_power_phy_clk,
+-01006                  "Low Speed Low Power Clock 0=48Mhz 1=6Mhz");
+-01007 module_param_named(enable_dynamic_fifo,
+-01008                    dwc_otg_module_params.enable_dynamic_fifo, int, 0444);
+-01009 MODULE_PARM_DESC(enable_dynamic_fifo, "0=cC Setting 1=Allow Dynamic Sizing");
+-01010 module_param_named(data_fifo_size, dwc_otg_module_params.data_fifo_size, int,
+-01011                    0444);
+-01012 MODULE_PARM_DESC(data_fifo_size,
+-01013                  "Total number of words in the data FIFO memory 32-32768");
+-01014 module_param_named(dev_rx_fifo_size, dwc_otg_module_params.dev_rx_fifo_size,
+-01015                    int, 0444);
+-01016 MODULE_PARM_DESC(dev_rx_fifo_size, "Number of words in the Rx FIFO 16-32768");
+-01017 module_param_named(dev_nperio_tx_fifo_size,
+-01018                    dwc_otg_module_params.dev_nperio_tx_fifo_size, int, 0444);
+-01019 MODULE_PARM_DESC(dev_nperio_tx_fifo_size,
+-01020                  "Number of words in the non-periodic Tx FIFO 16-32768");
+-01021 module_param_named(dev_perio_tx_fifo_size_1,
+-01022                    dwc_otg_module_params.dev_perio_tx_fifo_size[0], int, 0444);
+-01023 MODULE_PARM_DESC(dev_perio_tx_fifo_size_1,
+-01024                  "Number of words in the periodic Tx FIFO 4-768");
+-01025 module_param_named(dev_perio_tx_fifo_size_2,
+-01026                    dwc_otg_module_params.dev_perio_tx_fifo_size[1], int, 0444);
+-01027 MODULE_PARM_DESC(dev_perio_tx_fifo_size_2,
+-01028                  "Number of words in the periodic Tx FIFO 4-768");
+-01029 module_param_named(dev_perio_tx_fifo_size_3,
+-01030                    dwc_otg_module_params.dev_perio_tx_fifo_size[2], int, 0444);
+-01031 MODULE_PARM_DESC(dev_perio_tx_fifo_size_3,
+-01032                  "Number of words in the periodic Tx FIFO 4-768");
+-01033 module_param_named(dev_perio_tx_fifo_size_4,
+-01034                    dwc_otg_module_params.dev_perio_tx_fifo_size[3], int, 0444);
+-01035 MODULE_PARM_DESC(dev_perio_tx_fifo_size_4,
+-01036                  "Number of words in the periodic Tx FIFO 4-768");
+-01037 module_param_named(dev_perio_tx_fifo_size_5,
+-01038                    dwc_otg_module_params.dev_perio_tx_fifo_size[4], int, 0444);
+-01039 MODULE_PARM_DESC(dev_perio_tx_fifo_size_5,
+-01040                  "Number of words in the periodic Tx FIFO 4-768");
+-01041 module_param_named(dev_perio_tx_fifo_size_6,
+-01042                    dwc_otg_module_params.dev_perio_tx_fifo_size[5], int, 0444);
+-01043 MODULE_PARM_DESC(dev_perio_tx_fifo_size_6,
+-01044                  "Number of words in the periodic Tx FIFO 4-768");
+-01045 module_param_named(dev_perio_tx_fifo_size_7,
+-01046                    dwc_otg_module_params.dev_perio_tx_fifo_size[6], int, 0444);
+-01047 MODULE_PARM_DESC(dev_perio_tx_fifo_size_7,
+-01048                  "Number of words in the periodic Tx FIFO 4-768");
+-01049 module_param_named(dev_perio_tx_fifo_size_8,
+-01050                    dwc_otg_module_params.dev_perio_tx_fifo_size[7], int, 0444);
+-01051 MODULE_PARM_DESC(dev_perio_tx_fifo_size_8,
+-01052                  "Number of words in the periodic Tx FIFO 4-768");
+-01053 module_param_named(dev_perio_tx_fifo_size_9,
+-01054                    dwc_otg_module_params.dev_perio_tx_fifo_size[8], int, 0444);
+-01055 MODULE_PARM_DESC(dev_perio_tx_fifo_size_9,
+-01056                  "Number of words in the periodic Tx FIFO 4-768");
+-01057 module_param_named(dev_perio_tx_fifo_size_10,
+-01058                    dwc_otg_module_params.dev_perio_tx_fifo_size[9], int, 0444);
+-01059 MODULE_PARM_DESC(dev_perio_tx_fifo_size_10,
+-01060                  "Number of words in the periodic Tx FIFO 4-768");
+-01061 module_param_named(dev_perio_tx_fifo_size_11,
+-01062                    dwc_otg_module_params.dev_perio_tx_fifo_size[10], int, 0444);
+-01063 MODULE_PARM_DESC(dev_perio_tx_fifo_size_11,
+-01064                  "Number of words in the periodic Tx FIFO 4-768");
+-01065 module_param_named(dev_perio_tx_fifo_size_12,
+-01066                    dwc_otg_module_params.dev_perio_tx_fifo_size[11], int, 0444);
+-01067 MODULE_PARM_DESC(dev_perio_tx_fifo_size_12,
+-01068                  "Number of words in the periodic Tx FIFO 4-768");
+-01069 module_param_named(dev_perio_tx_fifo_size_13,
+-01070                    dwc_otg_module_params.dev_perio_tx_fifo_size[12], int, 0444);
+-01071 MODULE_PARM_DESC(dev_perio_tx_fifo_size_13,
+-01072                  "Number of words in the periodic Tx FIFO 4-768");
+-01073 module_param_named(dev_perio_tx_fifo_size_14,
+-01074                    dwc_otg_module_params.dev_perio_tx_fifo_size[13], int, 0444);
+-01075 MODULE_PARM_DESC(dev_perio_tx_fifo_size_14,
+-01076                  "Number of words in the periodic Tx FIFO 4-768");
+-01077 module_param_named(dev_perio_tx_fifo_size_15,
+-01078                    dwc_otg_module_params.dev_perio_tx_fifo_size[14], int, 0444);
+-01079 MODULE_PARM_DESC(dev_perio_tx_fifo_size_15,
+-01080                  "Number of words in the periodic Tx FIFO 4-768");
+-01081 module_param_named(host_rx_fifo_size, dwc_otg_module_params.host_rx_fifo_size,
+-01082                    int, 0444);
+-01083 MODULE_PARM_DESC(host_rx_fifo_size, "Number of words in the Rx FIFO 16-32768");
+-01084 module_param_named(host_nperio_tx_fifo_size,
+-01085                    dwc_otg_module_params.host_nperio_tx_fifo_size, int, 0444);
+-01086 MODULE_PARM_DESC(host_nperio_tx_fifo_size,
+-01087                  "Number of words in the non-periodic Tx FIFO 16-32768");
+-01088 module_param_named(host_perio_tx_fifo_size,
+-01089                    dwc_otg_module_params.host_perio_tx_fifo_size, int, 0444);
+-01090 MODULE_PARM_DESC(host_perio_tx_fifo_size,
+-01091                  "Number of words in the host periodic Tx FIFO 16-32768");
+-01092 module_param_named(max_transfer_size, dwc_otg_module_params.max_transfer_size,
+-01093                    int, 0444);
+-01095 MODULE_PARM_DESC(max_transfer_size,
+-01096                  "The maximum transfer size supported in bytes 2047-65535");
+-01097 module_param_named(max_packet_count, dwc_otg_module_params.max_packet_count,
+-01098                    int, 0444);
+-01099 MODULE_PARM_DESC(max_packet_count,
+-01100                  "The maximum number of packets in a transfer 15-511");
+-01101 module_param_named(host_channels, dwc_otg_module_params.host_channels, int,
+-01102                    0444);
+-01103 MODULE_PARM_DESC(host_channels,
+-01104                  "The number of host channel registers to use 1-16");
+-01105 module_param_named(dev_endpoints, dwc_otg_module_params.dev_endpoints, int,
+-01106                    0444);
+-01107 MODULE_PARM_DESC(dev_endpoints,
+-01108                  "The number of endpoints in addition to EP0 available for device mode 1-15");
+-01109 module_param_named(phy_type, dwc_otg_module_params.phy_type, int, 0444);
+-01110 MODULE_PARM_DESC(phy_type, "0=Reserved 1=UTMI+ 2=ULPI");
+-01111 module_param_named(phy_utmi_width, dwc_otg_module_params.phy_utmi_width, int,
+-01112                    0444);
+-01113 MODULE_PARM_DESC(phy_utmi_width, "Specifies the UTMI+ Data Width 8 or 16 bits");
+-01114 module_param_named(phy_ulpi_ddr, dwc_otg_module_params.phy_ulpi_ddr, int, 0444);
+-01115 MODULE_PARM_DESC(phy_ulpi_ddr,
+-01116                  "ULPI at double or single data rate 0=Single 1=Double");
+-01117 module_param_named(phy_ulpi_ext_vbus, dwc_otg_module_params.phy_ulpi_ext_vbus,
+-01118                    int, 0444);
+-01119 MODULE_PARM_DESC(phy_ulpi_ext_vbus,
+-01120                  "ULPI PHY using internal or external vbus 0=Internal");
+-01121 module_param_named(i2c_enable, dwc_otg_module_params.i2c_enable, int, 0444);
+-01122 MODULE_PARM_DESC(i2c_enable, "FS PHY Interface");
+-01123 module_param_named(ulpi_fs_ls, dwc_otg_module_params.ulpi_fs_ls, int, 0444);
+-01124 MODULE_PARM_DESC(ulpi_fs_ls, "ULPI PHY FS/LS mode only");
+-01125 module_param_named(ts_dline, dwc_otg_module_params.ts_dline, int, 0444);
+-01126 MODULE_PARM_DESC(ts_dline, "Term select Dline pulsing for all PHYs");
+-01127 module_param_named(debug, g_dbg_lvl, int, 0444);
+-01128 MODULE_PARM_DESC(debug, "");
+-01129 
+-01130 module_param_named(en_multiple_tx_fifo,
+-01131                    dwc_otg_module_params.en_multiple_tx_fifo, int, 0444);
+-01132 MODULE_PARM_DESC(en_multiple_tx_fifo,
+-01133                  "Dedicated Non Periodic Tx FIFOs 0=disabled 1=enabled");
+-01134 module_param_named(dev_tx_fifo_size_1,
+-01135                    dwc_otg_module_params.dev_tx_fifo_size[0], int, 0444);
+-01136 MODULE_PARM_DESC(dev_tx_fifo_size_1, "Number of words in the Tx FIFO 4-768");
+-01137 module_param_named(dev_tx_fifo_size_2,
+-01138                    dwc_otg_module_params.dev_tx_fifo_size[1], int, 0444);
+-01139 MODULE_PARM_DESC(dev_tx_fifo_size_2, "Number of words in the Tx FIFO 4-768");
+-01140 module_param_named(dev_tx_fifo_size_3,
+-01141                    dwc_otg_module_params.dev_tx_fifo_size[2], int, 0444);
+-01142 MODULE_PARM_DESC(dev_tx_fifo_size_3, "Number of words in the Tx FIFO 4-768");
+-01143 module_param_named(dev_tx_fifo_size_4,
+-01144                    dwc_otg_module_params.dev_tx_fifo_size[3], int, 0444);
+-01145 MODULE_PARM_DESC(dev_tx_fifo_size_4, "Number of words in the Tx FIFO 4-768");
+-01146 module_param_named(dev_tx_fifo_size_5,
+-01147                    dwc_otg_module_params.dev_tx_fifo_size[4], int, 0444);
+-01148 MODULE_PARM_DESC(dev_tx_fifo_size_5, "Number of words in the Tx FIFO 4-768");
+-01149 module_param_named(dev_tx_fifo_size_6,
+-01150                    dwc_otg_module_params.dev_tx_fifo_size[5], int, 0444);
+-01151 MODULE_PARM_DESC(dev_tx_fifo_size_6, "Number of words in the Tx FIFO 4-768");
+-01152 module_param_named(dev_tx_fifo_size_7,
+-01153                    dwc_otg_module_params.dev_tx_fifo_size[6], int, 0444);
+-01154 MODULE_PARM_DESC(dev_tx_fifo_size_7, "Number of words in the Tx FIFO 4-768");
+-01155 module_param_named(dev_tx_fifo_size_8,
+-01156                    dwc_otg_module_params.dev_tx_fifo_size[7], int, 0444);
+-01157 MODULE_PARM_DESC(dev_tx_fifo_size_8, "Number of words in the Tx FIFO 4-768");
+-01158 module_param_named(dev_tx_fifo_size_9,
+-01159                    dwc_otg_module_params.dev_tx_fifo_size[8], int, 0444);
+-01160 MODULE_PARM_DESC(dev_tx_fifo_size_9, "Number of words in the Tx FIFO 4-768");
+-01161 module_param_named(dev_tx_fifo_size_10,
+-01162                    dwc_otg_module_params.dev_tx_fifo_size[9], int, 0444);
+-01163 MODULE_PARM_DESC(dev_tx_fifo_size_10, "Number of words in the Tx FIFO 4-768");
+-01164 module_param_named(dev_tx_fifo_size_11,
+-01165                    dwc_otg_module_params.dev_tx_fifo_size[10], int, 0444);
+-01166 MODULE_PARM_DESC(dev_tx_fifo_size_11, "Number of words in the Tx FIFO 4-768");
+-01167 module_param_named(dev_tx_fifo_size_12,
+-01168                    dwc_otg_module_params.dev_tx_fifo_size[11], int, 0444);
+-01169 MODULE_PARM_DESC(dev_tx_fifo_size_12, "Number of words in the Tx FIFO 4-768");
+-01170 module_param_named(dev_tx_fifo_size_13,
+-01171                    dwc_otg_module_params.dev_tx_fifo_size[12], int, 0444);
+-01172 MODULE_PARM_DESC(dev_tx_fifo_size_13, "Number of words in the Tx FIFO 4-768");
+-01173 module_param_named(dev_tx_fifo_size_14,
+-01174                    dwc_otg_module_params.dev_tx_fifo_size[13], int, 0444);
+-01175 MODULE_PARM_DESC(dev_tx_fifo_size_14, "Number of words in the Tx FIFO 4-768");
+-01176 module_param_named(dev_tx_fifo_size_15,
+-01177                    dwc_otg_module_params.dev_tx_fifo_size[14], int, 0444);
+-01178 MODULE_PARM_DESC(dev_tx_fifo_size_15, "Number of words in the Tx FIFO 4-768");
+-01179 
+-01180 module_param_named(thr_ctl, dwc_otg_module_params.thr_ctl, int, 0444);
+-01181 MODULE_PARM_DESC(thr_ctl,
+-01182                  "Thresholding enable flag bit 0 - non ISO Tx thr., 1 - ISO Tx thr., 2 - Rx thr.- bit 0=disabled 1=enabled");
+-01183 module_param_named(tx_thr_length, dwc_otg_module_params.tx_thr_length, int,
+-01184                    0444);
+-01185 MODULE_PARM_DESC(tx_thr_length, "Tx Threshold length in 32 bit DWORDs");
+-01186 module_param_named(rx_thr_length, dwc_otg_module_params.rx_thr_length, int,
+-01187                    0444);
+-01188 MODULE_PARM_DESC(rx_thr_length, "Rx Threshold length in 32 bit DWORDs");
+-01189 
+-01190 module_param_named(pti_enable, dwc_otg_module_params.pti_enable, int, 0444);
+-01191 module_param_named(mpi_enable, dwc_otg_module_params.mpi_enable, int, 0444);
+-01192 module_param_named(lpm_enable, dwc_otg_module_params.lpm_enable, int, 0444);
+-01193 MODULE_PARM_DESC(lpm_enable, "LPM Enable 0=LPM Disabled 1=LPM Enabled");
+-01194 module_param_named(ic_usb_cap, dwc_otg_module_params.ic_usb_cap, int, 0444);
+-01195 MODULE_PARM_DESC(ic_usb_cap,
+-01196                  "IC_USB Capability 0=IC_USB Disabled 1=IC_USB Enabled");
+-01197 module_param_named(ahb_thr_ratio, dwc_otg_module_params.ahb_thr_ratio, int,
+-01198                    0444);
+-01199 MODULE_PARM_DESC(ahb_thr_ratio, "AHB Threshold Ratio");
+-01200 module_param_named(power_down, dwc_otg_module_params.power_down, int, 0444);
+-01201 MODULE_PARM_DESC(power_down, "Power Down Mode");
+-01202 module_param_named(reload_ctl, dwc_otg_module_params.reload_ctl, int, 0444);
+-01203 MODULE_PARM_DESC(reload_ctl, "HFIR Reload Control");
+-01204 module_param_named(dev_out_nak, dwc_otg_module_params.dev_out_nak, int, 0444);
+-01205 MODULE_PARM_DESC(dev_out_nak, "Enable Device OUT NAK");
+-01206 module_param_named(cont_on_bna, dwc_otg_module_params.cont_on_bna, int, 0444);
+-01207 MODULE_PARM_DESC(cont_on_bna, "Enable Enable Continue on BNA");
+-01208 module_param_named(ahb_single, dwc_otg_module_params.ahb_single, int, 0444);
+-01209 MODULE_PARM_DESC(ahb_single, "Enable AHB Single Support");
+-01210 module_param_named(adp_enable, dwc_otg_module_params.adp_enable, int, 0444);
+-01211 MODULE_PARM_DESC(adp_enable, "ADP Enable 0=ADP Disabled 1=ADP Enabled");
+-01212 module_param_named(otg_ver, dwc_otg_module_params.otg_ver, int, 0444);
+-01213 MODULE_PARM_DESC(otg_ver, "OTG revision supported 0=OTG 1.3 1=OTG 2.0");
+-01214 
+-
                                                                                Generated on Thu Oct 27 03:56:37 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__driver_8c.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/dwc__otg__driver_8c.html 2013-07-26 19:34:40.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,808 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_driver.c File Reference +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                dwc_otg_driver.c File Reference

                                                                                The dwc_otg_driver module provides the initialization and cleanup entry points for the DWC_otg driver. More... +-

                                                                                +-#include "dwc_otg_os_dep.h"
                                                                                +-#include "dwc_os.h"
                                                                                +-#include "dwc_otg_dbg.h"
                                                                                +-#include "dwc_otg_driver.h"
                                                                                +-#include "dwc_otg_attr.h"
                                                                                +-#include "dwc_otg_core_if.h"
                                                                                +-#include "dwc_otg_pcd_if.h"
                                                                                +-#include "dwc_otg_hcd_if.h"
                                                                                +- +-

                                                                                +-Go to the source code of this file. +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-

                                                                                Data Structures

                                                                                struct  dwc_otg_driver_module_params

                                                                                Defines

                                                                                +-#define DWC_DRIVER_VERSION   "2.94a 27-OCT-2011"
                                                                                +-#define DWC_DRIVER_DESC   "HS OTG USB Controller driver"

                                                                                Functions

                                                                                +-int pcd_init ()
                                                                                 This function initialized the PCD portion of the driver.
                                                                                int hcd_init ()
                                                                                 Initializes the HCD.
                                                                                +-int pcd_remove ()
                                                                                 Cleanup the PCD.
                                                                                void hcd_remove ()
                                                                                 Removes the HCD.
                                                                                void dwc_otg_adp_start (dwc_otg_core_if_t *core_if, uint8_t is_host)
                                                                                 Called right after driver is loaded to perform initial actions for ADP.
                                                                                +-ssize_t version_show (struct device_driver *dev, char *buf)
                                                                                 This function shows the Driver Version.
                                                                                +- DRIVER_ATTR (version, S_IRUGO, version_show, NULL)
                                                                                +-ssize_t dbg_level_show (struct device_driver *drv, char *buf)
                                                                                 This function shows the driver Debug Level.
                                                                                +-ssize_t dbg_level_store (struct device_driver *drv, const char *buf, size_t count)
                                                                                 This function stores the driver Debug Level.
                                                                                +- DRIVER_ATTR (debuglevel, S_IRUGO|S_IWUSR, dbg_level_show, dbg_level_store)
                                                                                +-int set_parameters (dwc_otg_core_if_t *core_if)
                                                                                 This function is called during module intialization to pass module parameters to the DWC_OTG CORE.
                                                                                +-irqreturn_t dwc_otg_common_irq (int irq, void *dev)
                                                                                 This function is the top level interrupt handler for the Common (Device and host modes) interrupts.
                                                                                void dwc_otg_driver_remove ()
                                                                                 This function is called when a lm_device is unregistered with the dwc_otg_driver.
                                                                                int dwc_otg_driver_probe ()
                                                                                 This function is called when an lm_device is bound to a dwc_otg_driver.
                                                                                int __init dwc_otg_driver_init (void)
                                                                                 This function is called when the dwc_otg_driver is installed with the insmod command.
                                                                                +- module_init (dwc_otg_driver_init)
                                                                                void __exit dwc_otg_driver_cleanup (void)
                                                                                 This function is called when the driver is removed from the kernel with the rmmod command.
                                                                                +- module_exit (dwc_otg_driver_cleanup)
                                                                                +- MODULE_DESCRIPTION (DWC_DRIVER_DESC)
                                                                                +- MODULE_AUTHOR ("Synopsys Inc.")
                                                                                +- MODULE_LICENSE ("GPL")
                                                                                +- module_param_named (otg_cap, dwc_otg_module_params.otg_cap, int, 0444)
                                                                                +- MODULE_PARM_DESC (otg_cap,"OTG Capabilities 0=HNP&SRP 1=SRP Only 2=None")
                                                                                +- module_param_named (opt, dwc_otg_module_params.opt, int, 0444)
                                                                                +- MODULE_PARM_DESC (opt,"OPT Mode")
                                                                                +- module_param_named (dma_enable, dwc_otg_module_params.dma_enable, int, 0444)
                                                                                +- MODULE_PARM_DESC (dma_enable,"DMA Mode 0=Slave 1=DMA enabled")
                                                                                +- module_param_named (dma_desc_enable, dwc_otg_module_params.dma_desc_enable, int, 0444)
                                                                                +- MODULE_PARM_DESC (dma_desc_enable,"DMA Desc Mode 0=Address DMA 1=DMA Descriptor enabled")
                                                                                +- module_param_named (dma_burst_size, dwc_otg_module_params.dma_burst_size, int, 0444)
                                                                                +- MODULE_PARM_DESC (dma_burst_size,"DMA Burst Size 1, 4, 8, 16, 32, 64, 128, 256")
                                                                                +- module_param_named (speed, dwc_otg_module_params.speed, int, 0444)
                                                                                +- MODULE_PARM_DESC (speed,"Speed 0=High Speed 1=Full Speed")
                                                                                +- module_param_named (host_support_fs_ls_low_power, dwc_otg_module_params.host_support_fs_ls_low_power, int, 0444)
                                                                                +- MODULE_PARM_DESC (host_support_fs_ls_low_power,"Support Low Power w/FS or LS 0=Support 1=Don't Support")
                                                                                +- module_param_named (host_ls_low_power_phy_clk, dwc_otg_module_params.host_ls_low_power_phy_clk, int, 0444)
                                                                                +- MODULE_PARM_DESC (host_ls_low_power_phy_clk,"Low Speed Low Power Clock 0=48Mhz 1=6Mhz")
                                                                                +- module_param_named (enable_dynamic_fifo, dwc_otg_module_params.enable_dynamic_fifo, int, 0444)
                                                                                +- MODULE_PARM_DESC (enable_dynamic_fifo,"0=cC Setting 1=Allow Dynamic Sizing")
                                                                                +- module_param_named (data_fifo_size, dwc_otg_module_params.data_fifo_size, int, 0444)
                                                                                +- MODULE_PARM_DESC (data_fifo_size,"Total number of words in the data FIFO memory 32-32768")
                                                                                +- module_param_named (dev_rx_fifo_size, dwc_otg_module_params.dev_rx_fifo_size, int, 0444)
                                                                                +- MODULE_PARM_DESC (dev_rx_fifo_size,"Number of words in the Rx FIFO 16-32768")
                                                                                +- module_param_named (dev_nperio_tx_fifo_size, dwc_otg_module_params.dev_nperio_tx_fifo_size, int, 0444)
                                                                                +- MODULE_PARM_DESC (dev_nperio_tx_fifo_size,"Number of words in the non-periodic Tx FIFO 16-32768")
                                                                                +- module_param_named (dev_perio_tx_fifo_size_1, dwc_otg_module_params.dev_perio_tx_fifo_size[0], int, 0444)
                                                                                +- MODULE_PARM_DESC (dev_perio_tx_fifo_size_1,"Number of words in the periodic Tx FIFO 4-768")
                                                                                +- module_param_named (dev_perio_tx_fifo_size_2, dwc_otg_module_params.dev_perio_tx_fifo_size[1], int, 0444)
                                                                                +- MODULE_PARM_DESC (dev_perio_tx_fifo_size_2,"Number of words in the periodic Tx FIFO 4-768")
                                                                                +- module_param_named (dev_perio_tx_fifo_size_3, dwc_otg_module_params.dev_perio_tx_fifo_size[2], int, 0444)
                                                                                +- MODULE_PARM_DESC (dev_perio_tx_fifo_size_3,"Number of words in the periodic Tx FIFO 4-768")
                                                                                +- module_param_named (dev_perio_tx_fifo_size_4, dwc_otg_module_params.dev_perio_tx_fifo_size[3], int, 0444)
                                                                                +- MODULE_PARM_DESC (dev_perio_tx_fifo_size_4,"Number of words in the periodic Tx FIFO 4-768")
                                                                                +- module_param_named (dev_perio_tx_fifo_size_5, dwc_otg_module_params.dev_perio_tx_fifo_size[4], int, 0444)
                                                                                +- MODULE_PARM_DESC (dev_perio_tx_fifo_size_5,"Number of words in the periodic Tx FIFO 4-768")
                                                                                +- module_param_named (dev_perio_tx_fifo_size_6, dwc_otg_module_params.dev_perio_tx_fifo_size[5], int, 0444)
                                                                                +- MODULE_PARM_DESC (dev_perio_tx_fifo_size_6,"Number of words in the periodic Tx FIFO 4-768")
                                                                                +- module_param_named (dev_perio_tx_fifo_size_7, dwc_otg_module_params.dev_perio_tx_fifo_size[6], int, 0444)
                                                                                +- MODULE_PARM_DESC (dev_perio_tx_fifo_size_7,"Number of words in the periodic Tx FIFO 4-768")
                                                                                +- module_param_named (dev_perio_tx_fifo_size_8, dwc_otg_module_params.dev_perio_tx_fifo_size[7], int, 0444)
                                                                                +- MODULE_PARM_DESC (dev_perio_tx_fifo_size_8,"Number of words in the periodic Tx FIFO 4-768")
                                                                                +- module_param_named (dev_perio_tx_fifo_size_9, dwc_otg_module_params.dev_perio_tx_fifo_size[8], int, 0444)
                                                                                +- MODULE_PARM_DESC (dev_perio_tx_fifo_size_9,"Number of words in the periodic Tx FIFO 4-768")
                                                                                +- module_param_named (dev_perio_tx_fifo_size_10, dwc_otg_module_params.dev_perio_tx_fifo_size[9], int, 0444)
                                                                                +- module_param_named (dev_perio_tx_fifo_size_11, dwc_otg_module_params.dev_perio_tx_fifo_size[10], int, 0444)
                                                                                +- module_param_named (dev_perio_tx_fifo_size_12, dwc_otg_module_params.dev_perio_tx_fifo_size[11], int, 0444)
                                                                                +- module_param_named (dev_perio_tx_fifo_size_13, dwc_otg_module_params.dev_perio_tx_fifo_size[12], int, 0444)
                                                                                +- module_param_named (dev_perio_tx_fifo_size_14, dwc_otg_module_params.dev_perio_tx_fifo_size[13], int, 0444)
                                                                                +- module_param_named (dev_perio_tx_fifo_size_15, dwc_otg_module_params.dev_perio_tx_fifo_size[14], int, 0444)
                                                                                +- module_param_named (host_rx_fifo_size, dwc_otg_module_params.host_rx_fifo_size, int, 0444)
                                                                                +- MODULE_PARM_DESC (host_rx_fifo_size,"Number of words in the Rx FIFO 16-32768")
                                                                                +- module_param_named (host_nperio_tx_fifo_size, dwc_otg_module_params.host_nperio_tx_fifo_size, int, 0444)
                                                                                +- MODULE_PARM_DESC (host_nperio_tx_fifo_size,"Number of words in the non-periodic Tx FIFO 16-32768")
                                                                                +- module_param_named (host_perio_tx_fifo_size, dwc_otg_module_params.host_perio_tx_fifo_size, int, 0444)
                                                                                +- MODULE_PARM_DESC (host_perio_tx_fifo_size,"Number of words in the host periodic Tx FIFO 16-32768")
                                                                                +- module_param_named (max_transfer_size, dwc_otg_module_params.max_transfer_size, int, 0444)
                                                                                 MODULE_PARM_DESC (max_transfer_size,"The maximum transfer size supported in bytes 2047-65535")
                                                                                +- module_param_named (max_packet_count, dwc_otg_module_params.max_packet_count, int, 0444)
                                                                                +- MODULE_PARM_DESC (max_packet_count,"The maximum number of packets in a transfer 15-511")
                                                                                +- module_param_named (host_channels, dwc_otg_module_params.host_channels, int, 0444)
                                                                                +- MODULE_PARM_DESC (host_channels,"The number of host channel registers to use 1-16")
                                                                                +- module_param_named (dev_endpoints, dwc_otg_module_params.dev_endpoints, int, 0444)
                                                                                +- MODULE_PARM_DESC (dev_endpoints,"The number of endpoints in addition to EP0 available for device mode 1-15")
                                                                                +- module_param_named (phy_type, dwc_otg_module_params.phy_type, int, 0444)
                                                                                +- MODULE_PARM_DESC (phy_type,"0=Reserved 1=UTMI+ 2=ULPI")
                                                                                +- module_param_named (phy_utmi_width, dwc_otg_module_params.phy_utmi_width, int, 0444)
                                                                                +- MODULE_PARM_DESC (phy_utmi_width,"Specifies the UTMI+ Data Width 8 or 16 bits")
                                                                                +- module_param_named (phy_ulpi_ddr, dwc_otg_module_params.phy_ulpi_ddr, int, 0444)
                                                                                +- MODULE_PARM_DESC (phy_ulpi_ddr,"ULPI at double or single data rate 0=Single 1=Double")
                                                                                +- module_param_named (phy_ulpi_ext_vbus, dwc_otg_module_params.phy_ulpi_ext_vbus, int, 0444)
                                                                                +- MODULE_PARM_DESC (phy_ulpi_ext_vbus,"ULPI PHY using internal or external vbus 0=Internal")
                                                                                +- module_param_named (i2c_enable, dwc_otg_module_params.i2c_enable, int, 0444)
                                                                                +- MODULE_PARM_DESC (i2c_enable,"FS PHY Interface")
                                                                                +- module_param_named (ulpi_fs_ls, dwc_otg_module_params.ulpi_fs_ls, int, 0444)
                                                                                +- MODULE_PARM_DESC (ulpi_fs_ls,"ULPI PHY FS/LS mode only")
                                                                                +- module_param_named (ts_dline, dwc_otg_module_params.ts_dline, int, 0444)
                                                                                +- MODULE_PARM_DESC (ts_dline,"Term select Dline pulsing for all PHYs")
                                                                                +- module_param_named (debug, g_dbg_lvl, int, 0444)
                                                                                +- MODULE_PARM_DESC (debug,"")
                                                                                +- module_param_named (en_multiple_tx_fifo, dwc_otg_module_params.en_multiple_tx_fifo, int, 0444)
                                                                                +- MODULE_PARM_DESC (en_multiple_tx_fifo,"Dedicated Non Periodic Tx FIFOs 0=disabled 1=enabled")
                                                                                +- module_param_named (dev_tx_fifo_size_1, dwc_otg_module_params.dev_tx_fifo_size[0], int, 0444)
                                                                                +- MODULE_PARM_DESC (dev_tx_fifo_size_1,"Number of words in the Tx FIFO 4-768")
                                                                                +- module_param_named (dev_tx_fifo_size_2, dwc_otg_module_params.dev_tx_fifo_size[1], int, 0444)
                                                                                +- MODULE_PARM_DESC (dev_tx_fifo_size_2,"Number of words in the Tx FIFO 4-768")
                                                                                +- module_param_named (dev_tx_fifo_size_3, dwc_otg_module_params.dev_tx_fifo_size[2], int, 0444)
                                                                                +- MODULE_PARM_DESC (dev_tx_fifo_size_3,"Number of words in the Tx FIFO 4-768")
                                                                                +- module_param_named (dev_tx_fifo_size_4, dwc_otg_module_params.dev_tx_fifo_size[3], int, 0444)
                                                                                +- MODULE_PARM_DESC (dev_tx_fifo_size_4,"Number of words in the Tx FIFO 4-768")
                                                                                +- module_param_named (dev_tx_fifo_size_5, dwc_otg_module_params.dev_tx_fifo_size[4], int, 0444)
                                                                                +- MODULE_PARM_DESC (dev_tx_fifo_size_5,"Number of words in the Tx FIFO 4-768")
                                                                                +- module_param_named (dev_tx_fifo_size_6, dwc_otg_module_params.dev_tx_fifo_size[5], int, 0444)
                                                                                +- MODULE_PARM_DESC (dev_tx_fifo_size_6,"Number of words in the Tx FIFO 4-768")
                                                                                +- module_param_named (dev_tx_fifo_size_7, dwc_otg_module_params.dev_tx_fifo_size[6], int, 0444)
                                                                                +- MODULE_PARM_DESC (dev_tx_fifo_size_7,"Number of words in the Tx FIFO 4-768")
                                                                                +- module_param_named (dev_tx_fifo_size_8, dwc_otg_module_params.dev_tx_fifo_size[7], int, 0444)
                                                                                +- MODULE_PARM_DESC (dev_tx_fifo_size_8,"Number of words in the Tx FIFO 4-768")
                                                                                +- module_param_named (dev_tx_fifo_size_9, dwc_otg_module_params.dev_tx_fifo_size[8], int, 0444)
                                                                                +- MODULE_PARM_DESC (dev_tx_fifo_size_9,"Number of words in the Tx FIFO 4-768")
                                                                                +- module_param_named (dev_tx_fifo_size_10, dwc_otg_module_params.dev_tx_fifo_size[9], int, 0444)
                                                                                +- module_param_named (dev_tx_fifo_size_11, dwc_otg_module_params.dev_tx_fifo_size[10], int, 0444)
                                                                                +- module_param_named (dev_tx_fifo_size_12, dwc_otg_module_params.dev_tx_fifo_size[11], int, 0444)
                                                                                +- module_param_named (dev_tx_fifo_size_13, dwc_otg_module_params.dev_tx_fifo_size[12], int, 0444)
                                                                                +- module_param_named (dev_tx_fifo_size_14, dwc_otg_module_params.dev_tx_fifo_size[13], int, 0444)
                                                                                +- module_param_named (dev_tx_fifo_size_15, dwc_otg_module_params.dev_tx_fifo_size[14], int, 0444)
                                                                                +- module_param_named (thr_ctl, dwc_otg_module_params.thr_ctl, int, 0444)
                                                                                +- MODULE_PARM_DESC (thr_ctl,"Thresholding enable flag bit 0 - non ISO Tx thr., 1 - ISO Tx thr., 2 - Rx thr.- bit 0=disabled 1=enabled")
                                                                                +- module_param_named (tx_thr_length, dwc_otg_module_params.tx_thr_length, int, 0444)
                                                                                +- MODULE_PARM_DESC (tx_thr_length,"Tx Threshold length in 32 bit DWORDs")
                                                                                +- module_param_named (rx_thr_length, dwc_otg_module_params.rx_thr_length, int, 0444)
                                                                                +- MODULE_PARM_DESC (rx_thr_length,"Rx Threshold length in 32 bit DWORDs")
                                                                                +- module_param_named (pti_enable, dwc_otg_module_params.pti_enable, int, 0444)
                                                                                +- module_param_named (mpi_enable, dwc_otg_module_params.mpi_enable, int, 0444)
                                                                                +- module_param_named (lpm_enable, dwc_otg_module_params.lpm_enable, int, 0444)
                                                                                +- MODULE_PARM_DESC (lpm_enable,"LPM Enable 0=LPM Disabled 1=LPM Enabled")
                                                                                +- module_param_named (ic_usb_cap, dwc_otg_module_params.ic_usb_cap, int, 0444)
                                                                                +- MODULE_PARM_DESC (ic_usb_cap,"IC_USB Capability 0=IC_USB Disabled 1=IC_USB Enabled")
                                                                                +- module_param_named (ahb_thr_ratio, dwc_otg_module_params.ahb_thr_ratio, int, 0444)
                                                                                +- MODULE_PARM_DESC (ahb_thr_ratio,"AHB Threshold Ratio")
                                                                                +- module_param_named (power_down, dwc_otg_module_params.power_down, int, 0444)
                                                                                +- MODULE_PARM_DESC (power_down,"Power Down Mode")
                                                                                +- module_param_named (reload_ctl, dwc_otg_module_params.reload_ctl, int, 0444)
                                                                                +- MODULE_PARM_DESC (reload_ctl,"HFIR Reload Control")
                                                                                +- module_param_named (dev_out_nak, dwc_otg_module_params.dev_out_nak, int, 0444)
                                                                                +- MODULE_PARM_DESC (dev_out_nak,"Enable Device OUT NAK")
                                                                                +- module_param_named (cont_on_bna, dwc_otg_module_params.cont_on_bna, int, 0444)
                                                                                +- MODULE_PARM_DESC (cont_on_bna,"Enable Enable Continue on BNA")
                                                                                +- module_param_named (ahb_single, dwc_otg_module_params.ahb_single, int, 0444)
                                                                                +- MODULE_PARM_DESC (ahb_single,"Enable AHB Single Support")
                                                                                +- module_param_named (adp_enable, dwc_otg_module_params.adp_enable, int, 0444)
                                                                                +- MODULE_PARM_DESC (adp_enable,"ADP Enable 0=ADP Disabled 1=ADP Enabled")
                                                                                +- module_param_named (otg_ver, dwc_otg_module_params.otg_ver, int, 0444)
                                                                                +- MODULE_PARM_DESC (otg_ver,"OTG revision supported 0=OTG 1.3 1=OTG 2.0")

                                                                                Variables

                                                                                +-const char dwc_driver_name [] = "dwc_otg"
                                                                                +-dwc_otg_driver_module_params dwc_otg_module_params
                                                                                +-uint32_t g_dbg_lvl = 0
                                                                                 The Debug Level bit-mask variable.
                                                                                +-

                                                                                Detailed Description

                                                                                +-The dwc_otg_driver module provides the initialization and cleanup entry points for the DWC_otg driver. +-

                                                                                +-This module will be dynamically installed after Linux is booted using the insmod command. When the module is installed, the dwc_otg_driver_init function is called. When the module is removed (using rmmod), the dwc_otg_driver_cleanup function is called.

                                                                                +-This module also defines a data structure for the dwc_otg_driver, which is used in conjunction with the standard ARM lm_device structure. These structures allow the OTG driver to comply with the standard Linux driver model in which devices and drivers are registered with a bus driver. This has the benefit that Linux can expose attributes of the driver and device in its special sysfs file system. Users can then read or write files in this file system to perform diagnostics on the driver components or the device. +-

                                                                                +-Definition in file dwc_otg_driver.c.

                                                                                Function Documentation

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +-
                                                                                int hcd_init (   ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Initializes the HCD. +-

                                                                                +-This function allocates memory for and initializes the static parts of the usb_hcd and dwc_otg_hcd structures. It also registers the USB bus with the core and calls the hc_driver->start() function. It returns a negative error on failure. +-

                                                                                +-Definition at line 339 of file dwc_otg_hcd_linux.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +-
                                                                                void hcd_remove (   ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Removes the HCD. +-

                                                                                +-Frees memory and resources associated with the HCD and deregisters the bus. +-

                                                                                +-Definition at line 441 of file dwc_otg_hcd_linux.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                void dwc_otg_adp_start ( dwc_otg_core_if_t *  core_if,
                                                                                uint8_t  is_host
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Called right after driver is loaded to perform initial actions for ADP. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +-
                                                                                core_if the pointer to core_if structure.
                                                                                is_host - flag for current mode of operation either from GINTSTS or GPWRDN
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 458 of file dwc_otg_adp.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +-
                                                                                void dwc_otg_driver_remove (   )  [static]
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This function is called when a lm_device is unregistered with the dwc_otg_driver. +-

                                                                                +-This happens, for example, when the rmmod command is executed. The device may or may not be electrically present. If it is present, the driver stops device processing. Any resources used on behalf of this device are freed.

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +-
                                                                                _dev 
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 561 of file dwc_otg_driver.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +-
                                                                                int dwc_otg_driver_probe (   )  [static]
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This function is called when an lm_device is bound to a dwc_otg_driver. +-

                                                                                +-It creates the driver components required to control the device (CIL, HCD, and PCD) and it initializes the device. The driver components are stored in a dwc_otg_device structure. A reference to the dwc_otg_device is saved in the lm_device. This allows the driver to access the dwc_otg_device structure on subsequent calls to driver methods for this device.

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +-
                                                                                _dev Bus device
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 651 of file dwc_otg_driver.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                int __init dwc_otg_driver_init ( void   )  [static]
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This function is called when the dwc_otg_driver is installed with the insmod command. +-

                                                                                +-It registers the dwc_otg_driver structure with the appropriate bus driver. This will cause the dwc_otg_driver_probe function to be called. In addition, the bus driver will automatically expose attributes defined for the device and driver in the special sysfs file system.

                                                                                +-

                                                                                Returns:
                                                                                +- +-

                                                                                +-Definition at line 924 of file dwc_otg_driver.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                void __exit dwc_otg_driver_cleanup ( void   )  [static]
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This function is called when the driver is removed from the kernel with the rmmod command. +-

                                                                                +-The driver unregisters itself with its bus driver. +-

                                                                                +-Definition at line 957 of file dwc_otg_driver.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                MODULE_PARM_DESC ( max_transfer_size ,
                                                                                "The maximum transfer size supported in bytes 2047-65535" 
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-

                                                                                Todo:
                                                                                Set the max to 512K, modify checks
                                                                                +-
                                                                                +-

                                                                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__driver_8h-source.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/dwc__otg__driver_8h-source.html 2013-07-26 19:34:40.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,84 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_driver.h Source File +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                dwc_otg_driver.h

                                                                                Go to the documentation of this file.
                                                                                00001 /* ==========================================================================
+-00002  * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_driver.h $
+-00003  * $Revision: #19 $
+-00004  * $Date: 2010/11/15 $
+-00005  * $Change: 1627671 $
+-00006  *
+-00007  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
+-00008  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
+-00009  * otherwise expressly agreed to in writing between Synopsys and you.
+-00010  * 
+-00011  * The Software IS NOT an item of Licensed Software or Licensed Product under
+-00012  * any End User Software License Agreement or Agreement for Licensed Product
+-00013  * with Synopsys or any supplement thereto. You are permitted to use and
+-00014  * redistribute this Software in source and binary forms, with or without
+-00015  * modification, provided that redistributions of source code must retain this
+-00016  * notice. You may not view, use, disclose, copy or distribute this file or
+-00017  * any information contained herein except pursuant to this license grant from
+-00018  * Synopsys. If you do not agree with this notice, including the disclaimer
+-00019  * below, then you are not authorized to use the Software.
+-00020  * 
+-00021  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
+-00022  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+-00023  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+-00024  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
+-00025  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+-00026  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+-00027  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+-00028  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+-00029  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+-00030  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+-00031  * DAMAGE.
+-00032  * ========================================================================== */
+-00033 
+-00034 #ifndef __DWC_OTG_DRIVER_H__
+-00035 #define __DWC_OTG_DRIVER_H__
+-00036 
+-00040 #include "dwc_otg_os_dep.h"
+-00041 #include "dwc_otg_core_if.h"
+-00042 
+-00043 /* Type declarations */
+-00044 struct dwc_otg_pcd;
+-00045 struct dwc_otg_hcd;
+-00046 
+-00051 typedef struct dwc_otg_device {
+-00055         struct os_dependent os_dep;
+-00056 
+-00058         dwc_otg_core_if_t *core_if;
+-00059 
+-00061         struct dwc_otg_pcd *pcd;
+-00062 
+-00064         struct dwc_otg_hcd *hcd;
+-00065 
+-00067         uint8_t common_irq_installed;
+-00068 
+-00069 } dwc_otg_device_t;
+-00070 
+-00071 /*We must clear S3C24XX_EINTPEND external interrupt register 
+-00072  * because after clearing in this register trigerred IRQ from 
+-00073  * H/W core in kernel interrupt can be occured again before OTG
+-00074  * handlers clear all IRQ sources of Core registers because of
+-00075  * timing latencies and Low Level IRQ Type.
+-00076  */
+-00077 #ifdef CONFIG_MACH_IPMATE
+-00078 #define  S3C2410X_CLEAR_EINTPEND()   \
+-00079 do { \
+-00080         __raw_writel(1UL << 11,S3C24XX_EINTPEND); \
+-00081 } while (0)
+-00082 #else
+-00083 #define  S3C2410X_CLEAR_EINTPEND()   do { } while (0)
+-00084 #endif
+-00085 
+-00086 #endif
+-
                                                                                Generated on Thu Oct 27 03:56:37 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__driver_8h.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/dwc__otg__driver_8h.html 2013-07-26 19:34:40.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,39 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_driver.h File Reference +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                dwc_otg_driver.h File Reference

                                                                                This file contains the interface to the Linux driver. More... +-

                                                                                +-#include "dwc_otg_os_dep.h"
                                                                                +-#include "dwc_otg_core_if.h"
                                                                                +- +-

                                                                                +-Go to the source code of this file. +- +- +- +- +- +- +- +- +- +- +- +- +-

                                                                                Data Structures

                                                                                struct  dwc_otg_device
                                                                                 This structure is a wrapper that encapsulates the driver components used to manage a single DWC_otg controller. More...

                                                                                Defines

                                                                                +-#define S3C2410X_CLEAR_EINTPEND()   do { } while (0)

                                                                                Typedefs

                                                                                +-typedef dwc_otg_device dwc_otg_device_t
                                                                                 This structure is a wrapper that encapsulates the driver components used to manage a single DWC_otg controller.
                                                                                +-

                                                                                Detailed Description

                                                                                +-This file contains the interface to the Linux driver. +-

                                                                                +- +-

                                                                                +-Definition in file dwc_otg_driver.h.

                                                                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__hcd_8c-source.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/dwc__otg__hcd_8c-source.html 2013-07-26 19:34:41.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,3216 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_hcd.c Source File +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                dwc_otg_hcd.c

                                                                                Go to the documentation of this file.
                                                                                00001 /* ==========================================================================
+-00002  * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd.c $
+-00003  * $Revision: #104 $
+-00004  * $Date: 2011/10/24 $
+-00005  * $Change: 1871159 $
+-00006  *
+-00007  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
+-00008  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
+-00009  * otherwise expressly agreed to in writing between Synopsys and you.
+-00010  *
+-00011  * The Software IS NOT an item of Licensed Software or Licensed Product under
+-00012  * any End User Software License Agreement or Agreement for Licensed Product
+-00013  * with Synopsys or any supplement thereto. You are permitted to use and
+-00014  * redistribute this Software in source and binary forms, with or without
+-00015  * modification, provided that redistributions of source code must retain this
+-00016  * notice. You may not view, use, disclose, copy or distribute this file or
+-00017  * any information contained herein except pursuant to this license grant from
+-00018  * Synopsys. If you do not agree with this notice, including the disclaimer
+-00019  * below, then you are not authorized to use the Software.
+-00020  *
+-00021  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
+-00022  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+-00023  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+-00024  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
+-00025  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+-00026  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+-00027  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+-00028  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+-00029  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+-00030  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+-00031  * DAMAGE.
+-00032  * ========================================================================== */
+-00033 #ifndef DWC_DEVICE_ONLY
+-00034 
+-00042 #include "dwc_otg_hcd.h"
+-00043 #include "dwc_otg_regs.h"
+-00044 
+-00045 dwc_otg_hcd_t *dwc_otg_hcd_alloc_hcd(void)
+-00046 {
+-00047         return DWC_ALLOC(sizeof(dwc_otg_hcd_t));
+-00048 }
+-00049 
+-00054 void dwc_otg_hcd_connect_timeout(void *ptr)
+-00055 {
+-00056         DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, ptr);
+-00057         DWC_PRINTF("Connect Timeout\n");
+-00058         __DWC_ERROR("Device Not Connected/Responding\n");
+-00059 }
+-00060 
+-00061 #ifdef DEBUG
+-00062 static void dump_channel_info(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
+-00063 {
+-00064         if (qh->channel != NULL) {
+-00065                 dwc_hc_t *hc = qh->channel;
+-00066                 dwc_list_link_t *item;
+-00067                 dwc_otg_qh_t *qh_item;
+-00068                 int num_channels = hcd->core_if->core_params->host_channels;
+-00069                 int i;
+-00070 
+-00071                 dwc_otg_hc_regs_t *hc_regs;
+-00072                 hcchar_data_t hcchar;
+-00073                 hcsplt_data_t hcsplt;
+-00074                 hctsiz_data_t hctsiz;
+-00075                 uint32_t hcdma;
+-00076 
+-00077                 hc_regs = hcd->core_if->host_if->hc_regs[hc->hc_num];
+-00078                 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
+-00079                 hcsplt.d32 = DWC_READ_REG32(&hc_regs->hcsplt);
+-00080                 hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
+-00081                 hcdma = DWC_READ_REG32(&hc_regs->hcdma);
+-00082 
+-00083                 DWC_PRINTF("  Assigned to channel %p:\n", hc);
+-00084                 DWC_PRINTF("    hcchar 0x%08x, hcsplt 0x%08x\n", hcchar.d32,
+-00085                            hcsplt.d32);
+-00086                 DWC_PRINTF("    hctsiz 0x%08x, hcdma 0x%08x\n", hctsiz.d32,
+-00087                            hcdma);
+-00088                 DWC_PRINTF("    dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
+-00089                            hc->dev_addr, hc->ep_num, hc->ep_is_in);
+-00090                 DWC_PRINTF("    ep_type: %d\n", hc->ep_type);
+-00091                 DWC_PRINTF("    max_packet: %d\n", hc->max_packet);
+-00092                 DWC_PRINTF("    data_pid_start: %d\n", hc->data_pid_start);
+-00093                 DWC_PRINTF("    xfer_started: %d\n", hc->xfer_started);
+-00094                 DWC_PRINTF("    halt_status: %d\n", hc->halt_status);
+-00095                 DWC_PRINTF("    xfer_buff: %p\n", hc->xfer_buff);
+-00096                 DWC_PRINTF("    xfer_len: %d\n", hc->xfer_len);
+-00097                 DWC_PRINTF("    qh: %p\n", hc->qh);
+-00098                 DWC_PRINTF("  NP inactive sched:\n");
+-00099                 DWC_LIST_FOREACH(item, &hcd->non_periodic_sched_inactive) {
+-00100                         qh_item =
+-00101                             DWC_LIST_ENTRY(item, dwc_otg_qh_t, qh_list_entry);
+-00102                         DWC_PRINTF("    %p\n", qh_item);
+-00103                 }
+-00104                 DWC_PRINTF("  NP active sched:\n");
+-00105                 DWC_LIST_FOREACH(item, &hcd->non_periodic_sched_active) {
+-00106                         qh_item =
+-00107                             DWC_LIST_ENTRY(item, dwc_otg_qh_t, qh_list_entry);
+-00108                         DWC_PRINTF("    %p\n", qh_item);
+-00109                 }
+-00110                 DWC_PRINTF("  Channels: \n");
+-00111                 for (i = 0; i < num_channels; i++) {
+-00112                         dwc_hc_t *hc = hcd->hc_ptr_array[i];
+-00113                         DWC_PRINTF("    %2d: %p\n", i, hc);
+-00114                 }
+-00115         }
+-00116 }
+-00117 #endif /* DEBUG */
+-00118 
+-00123 static void hcd_start_func(void *_vp)
+-00124 {
+-00125         dwc_otg_hcd_t *hcd = (dwc_otg_hcd_t *) _vp;
+-00126 
+-00127         DWC_DEBUGPL(DBG_HCDV, "%s() %p\n", __func__, hcd);
+-00128         if (hcd) {
+-00129                 hcd->fops->start(hcd);
+-00130         }
+-00131 }
+-00132 
+-00133 static void del_xfer_timers(dwc_otg_hcd_t * hcd)
+-00134 {
+-00135 #ifdef DEBUG
+-00136         int i;
+-00137         int num_channels = hcd->core_if->core_params->host_channels;
+-00138         for (i = 0; i < num_channels; i++) {
+-00139                 DWC_TIMER_CANCEL(hcd->core_if->hc_xfer_timer[i]);
+-00140         }
+-00141 #endif
+-00142 }
+-00143 
+-00144 static void del_timers(dwc_otg_hcd_t * hcd)
+-00145 {
+-00146         del_xfer_timers(hcd);
+-00147         DWC_TIMER_CANCEL(hcd->conn_timer);
+-00148 }
+-00149 
+-00154 static void kill_urbs_in_qh_list(dwc_otg_hcd_t * hcd, dwc_list_link_t * qh_list)
+-00155 {
+-00156         dwc_list_link_t *qh_item;
+-00157         dwc_otg_qh_t *qh;
+-00158         dwc_otg_qtd_t *qtd, *qtd_tmp;
+-00159 
+-00160         DWC_LIST_FOREACH(qh_item, qh_list) {
+-00161                 qh = DWC_LIST_ENTRY(qh_item, dwc_otg_qh_t, qh_list_entry);
+-00162                 DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp,
+-00163                                          &qh->qtd_list, qtd_list_entry) {
+-00164                         qtd = DWC_CIRCLEQ_FIRST(&qh->qtd_list);
+-00165                         if (qtd->urb != NULL) {
+-00166                                 hcd->fops->complete(hcd, qtd->urb->priv,
+-00167                                                     qtd->urb, -DWC_E_TIMEOUT);
+-00168                                 dwc_otg_hcd_qtd_remove_and_free(hcd, qtd, qh);
+-00169                         }
+-00170 
+-00171                 }
+-00172         }
+-00173 }
+-00174 
+-00181 static void kill_all_urbs(dwc_otg_hcd_t * hcd)
+-00182 {
+-00183         kill_urbs_in_qh_list(hcd, &hcd->non_periodic_sched_inactive);
+-00184         kill_urbs_in_qh_list(hcd, &hcd->non_periodic_sched_active);
+-00185         kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_inactive);
+-00186         kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_ready);
+-00187         kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_assigned);
+-00188         kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_queued);
+-00189 }
+-00190 
+-00197 static void dwc_otg_hcd_start_connect_timer(dwc_otg_hcd_t * hcd)
+-00198 {
+-00199         DWC_TIMER_SCHEDULE(hcd->conn_timer, 10000 /* 10 secs */ );
+-00200 }
+-00201 
+-00207 static int32_t dwc_otg_hcd_session_start_cb(void *p)
+-00208 {
+-00209         dwc_otg_hcd_t *dwc_otg_hcd;
+-00210         DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, p);
+-00211         dwc_otg_hcd = p;
+-00212         dwc_otg_hcd_start_connect_timer(dwc_otg_hcd);
+-00213         return 1;
+-00214 }
+-00215 
+-00222 static int32_t dwc_otg_hcd_start_cb(void *p)
+-00223 {
+-00224         dwc_otg_hcd_t *dwc_otg_hcd = p;
+-00225         dwc_otg_core_if_t *core_if;
+-00226         hprt0_data_t hprt0;
+-00227 
+-00228         core_if = dwc_otg_hcd->core_if;
+-00229 
+-00230         if (core_if->op_state == B_HOST) {
+-00231                 /*
+-00232                  * Reset the port.  During a HNP mode switch the reset
+-00233                  * needs to occur within 1ms and have a duration of at
+-00234                  * least 50ms.
+-00235                  */
+-00236                 hprt0.d32 = dwc_otg_read_hprt0(core_if);
+-00237                 hprt0.b.prtrst = 1;
+-00238                 DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
+-00239         }
+-00240         DWC_WORKQ_SCHEDULE_DELAYED(core_if->wq_otg,
+-00241                                    hcd_start_func, dwc_otg_hcd, 50,
+-00242                                    "start hcd");
+-00243 
+-00244         return 1;
+-00245 }
+-00246 
+-00252 static int32_t dwc_otg_hcd_disconnect_cb(void *p)
+-00253 {
+-00254         gintsts_data_t intr;
+-00255         dwc_otg_hcd_t *dwc_otg_hcd = p;
+-00256 
+-00257         /*
+-00258          * Set status flags for the hub driver.
+-00259          */
+-00260         dwc_otg_hcd->flags.b.port_connect_status_change = 1;
+-00261         dwc_otg_hcd->flags.b.port_connect_status = 0;
+-00262 
+-00263         /*
+-00264          * Shutdown any transfers in process by clearing the Tx FIFO Empty
+-00265          * interrupt mask and status bits and disabling subsequent host
+-00266          * channel interrupts.
+-00267          */
+-00268         intr.d32 = 0;
+-00269         intr.b.nptxfempty = 1;
+-00270         intr.b.ptxfempty = 1;
+-00271         intr.b.hcintr = 1;
+-00272         DWC_MODIFY_REG32(&dwc_otg_hcd->core_if->core_global_regs->gintmsk,
+-00273                          intr.d32, 0);
+-00274         DWC_MODIFY_REG32(&dwc_otg_hcd->core_if->core_global_regs->gintsts,
+-00275                          intr.d32, 0);
+-00276 
+-00277         del_timers(dwc_otg_hcd);
+-00278 
+-00279         /*
+-00280          * Turn off the vbus power only if the core has transitioned to device
+-00281          * mode. If still in host mode, need to keep power on to detect a
+-00282          * reconnection.
+-00283          */
+-00284         if (dwc_otg_is_device_mode(dwc_otg_hcd->core_if)) {
+-00285                 if (dwc_otg_hcd->core_if->op_state != A_SUSPEND) {
+-00286                         hprt0_data_t hprt0 = {.d32 = 0 };
+-00287                         DWC_PRINTF("Disconnect: PortPower off\n");
+-00288                         hprt0.b.prtpwr = 0;
+-00289                         DWC_WRITE_REG32(dwc_otg_hcd->core_if->host_if->hprt0,
+-00290                                         hprt0.d32);
+-00291                 }
+-00292 
+-00293                 dwc_otg_disable_host_interrupts(dwc_otg_hcd->core_if);
+-00294         }
+-00295 
+-00296         /* Respond with an error status to all URBs in the schedule. */
+-00297         kill_all_urbs(dwc_otg_hcd);
+-00298 
+-00299         if (dwc_otg_is_host_mode(dwc_otg_hcd->core_if)) {
+-00300                 /* Clean up any host channels that were in use. */
+-00301                 int num_channels;
+-00302                 int i;
+-00303                 dwc_hc_t *channel;
+-00304                 dwc_otg_hc_regs_t *hc_regs;
+-00305                 hcchar_data_t hcchar;
+-00306 
+-00307                 num_channels = dwc_otg_hcd->core_if->core_params->host_channels;
+-00308 
+-00309                 if (!dwc_otg_hcd->core_if->dma_enable) {
+-00310                         /* Flush out any channel requests in slave mode. */
+-00311                         for (i = 0; i < num_channels; i++) {
+-00312                                 channel = dwc_otg_hcd->hc_ptr_array[i];
+-00313                                 if (DWC_CIRCLEQ_EMPTY_ENTRY
+-00314                                     (channel, hc_list_entry)) {
+-00315                                         hc_regs =
+-00316                                             dwc_otg_hcd->core_if->
+-00317                                             host_if->hc_regs[i];
+-00318                                         hcchar.d32 =
+-00319                                             DWC_READ_REG32(&hc_regs->hcchar);
+-00320                                         if (hcchar.b.chen) {
+-00321                                                 hcchar.b.chen = 0;
+-00322                                                 hcchar.b.chdis = 1;
+-00323                                                 hcchar.b.epdir = 0;
+-00324                                                 DWC_WRITE_REG32
+-00325                                                     (&hc_regs->hcchar,
+-00326                                                      hcchar.d32);
+-00327                                         }
+-00328                                 }
+-00329                         }
+-00330                 }
+-00331 
+-00332                 for (i = 0; i < num_channels; i++) {
+-00333                         channel = dwc_otg_hcd->hc_ptr_array[i];
+-00334                         if (DWC_CIRCLEQ_EMPTY_ENTRY(channel, hc_list_entry)) {
+-00335                                 hc_regs =
+-00336                                     dwc_otg_hcd->core_if->host_if->hc_regs[i];
+-00337                                 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
+-00338                                 if (hcchar.b.chen) {
+-00339                                         /* Halt the channel. */
+-00340                                         hcchar.b.chdis = 1;
+-00341                                         DWC_WRITE_REG32(&hc_regs->hcchar,
+-00342                                                         hcchar.d32);
+-00343                                 }
+-00344 
+-00345                                 dwc_otg_hc_cleanup(dwc_otg_hcd->core_if,
+-00346                                                    channel);
+-00347                                 DWC_CIRCLEQ_INSERT_TAIL
+-00348                                     (&dwc_otg_hcd->free_hc_list, channel,
+-00349                                      hc_list_entry);
+-00350                                 /*
+-00351                                  * Added for Descriptor DMA to prevent channel double cleanup
+-00352                                  * in release_channel_ddma(). Which called from ep_disable
+-00353                                  * when device disconnect.
+-00354                                  */
+-00355                                 channel->qh = NULL;
+-00356                         }
+-00357                 }
+-00358         }
+-00359 
+-00360         if (dwc_otg_hcd->fops->disconnect) {
+-00361                 dwc_otg_hcd->fops->disconnect(dwc_otg_hcd);
+-00362         }
+-00363 
+-00364         return 1;
+-00365 }
+-00366 
+-00372 static int32_t dwc_otg_hcd_stop_cb(void *p)
+-00373 {
+-00374         dwc_otg_hcd_t *dwc_otg_hcd = p;
+-00375 
+-00376         DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, p);
+-00377         dwc_otg_hcd_stop(dwc_otg_hcd);
+-00378         return 1;
+-00379 }
+-00380 
+-00381 #ifdef CONFIG_USB_DWC_OTG_LPM
+-00382 
+-00387 static int dwc_otg_hcd_sleep_cb(void *p)
+-00388 {
+-00389         dwc_otg_hcd_t *hcd = p;
+-00390 
+-00391         dwc_otg_hcd_free_hc_from_lpm(hcd);
+-00392 
+-00393         return 0;
+-00394 }
+-00395 #endif
+-00396 
+-00402 static int dwc_otg_hcd_rem_wakeup_cb(void *p)
+-00403 {
+-00404         dwc_otg_hcd_t *hcd = p;
+-00405 
+-00406         if (hcd->core_if->lx_state == DWC_OTG_L2) {
+-00407                 hcd->flags.b.port_suspend_change = 1;
+-00408         }
+-00409 #ifdef CONFIG_USB_DWC_OTG_LPM
+-00410         else {
+-00411                 hcd->flags.b.port_l1_change = 1;
+-00412         }
+-00413 #endif
+-00414         return 0;
+-00415 }
+-00416 
+-00421 void dwc_otg_hcd_stop(dwc_otg_hcd_t * hcd)
+-00422 {
+-00423         hprt0_data_t hprt0 = {.d32 = 0 };
+-00424 
+-00425         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD STOP\n");
+-00426 
+-00427         /*
+-00428          * The root hub should be disconnected before this function is called.
+-00429          * The disconnect will clear the QTD lists (via ..._hcd_urb_dequeue)
+-00430          * and the QH lists (via ..._hcd_endpoint_disable).
+-00431          */
+-00432 
+-00433         /* Turn off all host-specific interrupts. */
+-00434         dwc_otg_disable_host_interrupts(hcd->core_if);
+-00435 
+-00436         /* Turn off the vbus power */
+-00437         DWC_PRINTF("PortPower off\n");
+-00438         hprt0.b.prtpwr = 0;
+-00439         DWC_WRITE_REG32(hcd->core_if->host_if->hprt0, hprt0.d32);
+-00440         dwc_mdelay(1);
+-00441 }
+-00442 
+-00443 int dwc_otg_hcd_urb_enqueue(dwc_otg_hcd_t * hcd,
+-00444                             dwc_otg_hcd_urb_t * dwc_otg_urb, void **ep_handle,
+-00445                             int atomic_alloc)
+-00446 {
+-00447         dwc_irqflags_t flags;
+-00448         int retval = 0;
+-00449         dwc_otg_qtd_t *qtd;
+-00450         gintmsk_data_t intr_mask = {.d32 = 0 };
+-00451 
+-00452         if (!hcd->flags.b.port_connect_status) {
+-00453                 /* No longer connected. */
+-00454                 DWC_ERROR("Not connected\n");
+-00455                 return -DWC_E_NO_DEVICE;
+-00456         }
+-00457 
+-00458         qtd = dwc_otg_hcd_qtd_create(dwc_otg_urb, atomic_alloc);
+-00459         if (qtd == NULL) {
+-00460                 DWC_ERROR("DWC OTG HCD URB Enqueue failed creating QTD\n");
+-00461                 return -DWC_E_NO_MEMORY;
+-00462         }
+-00463 
+-00464         retval =
+-00465             dwc_otg_hcd_qtd_add(qtd, hcd, (dwc_otg_qh_t **) ep_handle, atomic_alloc);
+-00466         if (retval < 0) {
+-00467                 DWC_ERROR("DWC OTG HCD URB Enqueue failed adding QTD. "
+-00468                           "Error status %d\n", retval);
+-00469                 dwc_otg_hcd_qtd_free(qtd);
+-00470         } else {
+-00471                 qtd->qh = *ep_handle;
+-00472         }
+-00473         intr_mask.d32 = DWC_READ_REG32(&hcd->core_if->core_global_regs->gintmsk);
+-00474         if (!intr_mask.b.sofintr && retval == 0) {
+-00475                 dwc_otg_transaction_type_e tr_type;
+-00476                 if ((qtd->qh->ep_type == UE_BULK)
+-00477                     && !(qtd->urb->flags & URB_GIVEBACK_ASAP)) {
+-00478                         /* Do not schedule SG transactions until qtd has URB_GIVEBACK_ASAP set */
+-00479                         return 0;
+-00480                 }
+-00481                 DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
+-00482                 tr_type = dwc_otg_hcd_select_transactions(hcd);
+-00483                 if (tr_type != DWC_OTG_TRANSACTION_NONE) {
+-00484                         dwc_otg_hcd_queue_transactions(hcd, tr_type);
+-00485                 }
+-00486                 DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
+-00487         }
+-00488 
+-00489         return retval;
+-00490 }
+-00491 
+-00492 int dwc_otg_hcd_urb_dequeue(dwc_otg_hcd_t * hcd,
+-00493                             dwc_otg_hcd_urb_t * dwc_otg_urb)
+-00494 {
+-00495         dwc_otg_qh_t *qh;
+-00496         dwc_otg_qtd_t *urb_qtd;
+-00497 
+-00498         urb_qtd = dwc_otg_urb->qtd;
+-00499         qh = urb_qtd->qh;
+-00500 #ifdef DEBUG
+-00501         if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
+-00502                 if (urb_qtd->in_process) {
+-00503                         dump_channel_info(hcd, qh);
+-00504                 }
+-00505         }
+-00506 #endif
+-00507         if (urb_qtd->in_process && qh->channel) {
+-00508                 /* The QTD is in process (it has been assigned to a channel). */
+-00509                 if (hcd->flags.b.port_connect_status) {
+-00510                         /*
+-00511                          * If still connected (i.e. in host mode), halt the
+-00512                          * channel so it can be used for other transfers. If
+-00513                          * no longer connected, the host registers can't be
+-00514                          * written to halt the channel since the core is in
+-00515                          * device mode.
+-00516                          */
+-00517                         dwc_otg_hc_halt(hcd->core_if, qh->channel,
+-00518                                         DWC_OTG_HC_XFER_URB_DEQUEUE);
+-00519                 }
+-00520         }
+-00521 
+-00522         /*
+-00523          * Free the QTD and clean up the associated QH. Leave the QH in the
+-00524          * schedule if it has any remaining QTDs.
+-00525          */
+-00526 
+-00527         if (!hcd->core_if->dma_desc_enable) {
+-00528                 uint8_t b = urb_qtd->in_process;
+-00529                 dwc_otg_hcd_qtd_remove_and_free(hcd, urb_qtd, qh);
+-00530                 if (b) {
+-00531                         dwc_otg_hcd_qh_deactivate(hcd, qh, 0);
+-00532                         qh->channel = NULL;
+-00533                 } else if (DWC_CIRCLEQ_EMPTY(&qh->qtd_list)) {
+-00534                         dwc_otg_hcd_qh_remove(hcd, qh);
+-00535                 }
+-00536         } else {
+-00537                 dwc_otg_hcd_qtd_remove_and_free(hcd, urb_qtd, qh);
+-00538         }
+-00539         return 0;
+-00540 }
+-00541 
+-00542 int dwc_otg_hcd_endpoint_disable(dwc_otg_hcd_t * hcd, void *ep_handle,
+-00543                                  int retry)
+-00544 {
+-00545         dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle;
+-00546         int retval = 0;
+-00547         dwc_irqflags_t flags;
+-00548 
+-00549         if (retry < 0) {
+-00550                 retval = -DWC_E_INVALID;
+-00551                 goto done;
+-00552         }
+-00553 
+-00554         if (!qh) {
+-00555                 retval = -DWC_E_INVALID;
+-00556                 goto done;
+-00557         }
+-00558 
+-00559         DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
+-00560 
+-00561         while (!DWC_CIRCLEQ_EMPTY(&qh->qtd_list) && retry) {
+-00562                 DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
+-00563                 retry--;
+-00564                 dwc_msleep(5);
+-00565                 DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
+-00566         }
+-00567 
+-00568         dwc_otg_hcd_qh_remove(hcd, qh);
+-00569 
+-00570         DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
+-00571         /*
+-00572          * Split dwc_otg_hcd_qh_remove_and_free() into qh_remove
+-00573          * and qh_free to prevent stack dump on DWC_DMA_FREE() with
+-00574          * irq_disabled (spinlock_irqsave) in dwc_otg_hcd_desc_list_free()
+-00575          * and dwc_otg_hcd_frame_list_alloc().
+-00576          */
+-00577         dwc_otg_hcd_qh_free(hcd, qh);
+-00578 
+-00579 done:
+-00580         return retval;
+-00581 }
+-00582 
+-00583 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,30)
+-00584 int dwc_otg_hcd_endpoint_reset(dwc_otg_hcd_t * hcd, void *ep_handle)
+-00585 {
+-00586         int retval = 0;
+-00587         dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle;
+-00588         if (!qh)
+-00589                 return -DWC_E_INVALID;
+-00590 
+-00591         qh->data_toggle = DWC_OTG_HC_PID_DATA0;
+-00592         return retval;
+-00593 }
+-00594 #endif
+-00595 
+-00599 static dwc_otg_cil_callbacks_t hcd_cil_callbacks = {
+-00600         .start = dwc_otg_hcd_start_cb,
+-00601         .stop = dwc_otg_hcd_stop_cb,
+-00602         .disconnect = dwc_otg_hcd_disconnect_cb,
+-00603         .session_start = dwc_otg_hcd_session_start_cb,
+-00604         .resume_wakeup = dwc_otg_hcd_rem_wakeup_cb,
+-00605 #ifdef CONFIG_USB_DWC_OTG_LPM
+-00606         .sleep = dwc_otg_hcd_sleep_cb,
+-00607 #endif
+-00608         .p = 0,
+-00609 };
+-00610 
+-00614 static void reset_tasklet_func(void *data)
+-00615 {
+-00616         dwc_otg_hcd_t *dwc_otg_hcd = (dwc_otg_hcd_t *) data;
+-00617         dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;
+-00618         hprt0_data_t hprt0;
+-00619 
+-00620         DWC_DEBUGPL(DBG_HCDV, "USB RESET tasklet called\n");
+-00621 
+-00622         hprt0.d32 = dwc_otg_read_hprt0(core_if);
+-00623         hprt0.b.prtrst = 1;
+-00624         DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
+-00625         dwc_mdelay(60);
+-00626 
+-00627         hprt0.b.prtrst = 0;
+-00628         DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
+-00629         dwc_otg_hcd->flags.b.port_reset_change = 1;
+-00630 }
+-00631 
+-00632 static void qh_list_free(dwc_otg_hcd_t * hcd, dwc_list_link_t * qh_list)
+-00633 {
+-00634         dwc_list_link_t *item;
+-00635         dwc_otg_qh_t *qh;
+-00636         dwc_irqflags_t flags;
+-00637 
+-00638         if (!qh_list->next) {
+-00639                 /* The list hasn't been initialized yet. */
+-00640                 return;
+-00641         }
+-00642         /*
+-00643          * Hold spinlock here. Not needed in that case if bellow 
+-00644          * function is being called from ISR 
+-00645          */
+-00646         DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
+-00647         /* Ensure there are no QTDs or URBs left. */
+-00648         kill_urbs_in_qh_list(hcd, qh_list);
+-00649         DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
+-00650 
+-00651         DWC_LIST_FOREACH(item, qh_list) {
+-00652                 qh = DWC_LIST_ENTRY(item, dwc_otg_qh_t, qh_list_entry);
+-00653                 dwc_otg_hcd_qh_remove_and_free(hcd, qh);
+-00654         }
+-00655 }
+-00656 
+-00661 void dwc_otg_hcd_power_up(void *ptr)
+-00662 {
+-00663         gpwrdn_data_t gpwrdn = {.d32 = 0 };
+-00664         dwc_otg_core_if_t *core_if = (dwc_otg_core_if_t *) ptr;
+-00665 
+-00666         DWC_PRINTF("%s called\n", __FUNCTION__);
+-00667 
+-00668         if (!core_if->hibernation_suspend) {
+-00669                 DWC_PRINTF("Already exited from Hibernation\n");
+-00670                 return;
+-00671         }
+-00672 
+-00673         /* Switch on the voltage to the core */
+-00674         gpwrdn.b.pwrdnswtch = 1;
+-00675         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
+-00676         dwc_udelay(10);
+-00677 
+-00678         /* Reset the core */
+-00679         gpwrdn.d32 = 0;
+-00680         gpwrdn.b.pwrdnrstn = 1;
+-00681         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
+-00682         dwc_udelay(10);
+-00683 
+-00684         /* Disable power clamps */
+-00685         gpwrdn.d32 = 0;
+-00686         gpwrdn.b.pwrdnclmp = 1;
+-00687         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
+-00688 
+-00689         /* Remove reset the core signal */
+-00690         gpwrdn.d32 = 0;
+-00691         gpwrdn.b.pwrdnrstn = 1;
+-00692         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
+-00693         dwc_udelay(10);
+-00694 
+-00695         /* Disable PMU interrupt */
+-00696         gpwrdn.d32 = 0;
+-00697         gpwrdn.b.pmuintsel = 1;
+-00698         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
+-00699 
+-00700         core_if->hibernation_suspend = 0;
+-00701 
+-00702         /* Disable PMU */
+-00703         gpwrdn.d32 = 0;
+-00704         gpwrdn.b.pmuactv = 1;
+-00705         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
+-00706         dwc_udelay(10);
+-00707 
+-00708         /* Enable VBUS */
+-00709         gpwrdn.d32 = 0;
+-00710         gpwrdn.b.dis_vbus = 1;
+-00711         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
+-00712 
+-00713         core_if->op_state = A_HOST;
+-00714         dwc_otg_core_init(core_if);
+-00715         dwc_otg_enable_global_interrupts(core_if);
+-00716         cil_hcd_start(core_if);
+-00717 }
+-00718 
+-00723 static void dwc_otg_hcd_free(dwc_otg_hcd_t * dwc_otg_hcd)
+-00724 {
+-00725         int i;
+-00726 
+-00727         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD FREE\n");
+-00728 
+-00729         del_timers(dwc_otg_hcd);
+-00730 
+-00731         /* Free memory for QH/QTD lists */
+-00732         qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->non_periodic_sched_inactive);
+-00733         qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->non_periodic_sched_active);
+-00734         qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_inactive);
+-00735         qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_ready);
+-00736         qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_assigned);
+-00737         qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_queued);
+-00738 
+-00739         /* Free memory for the host channels. */
+-00740         for (i = 0; i < MAX_EPS_CHANNELS; i++) {
+-00741                 dwc_hc_t *hc = dwc_otg_hcd->hc_ptr_array[i];
+-00742 
+-00743 #ifdef DEBUG
+-00744                 if (dwc_otg_hcd->core_if->hc_xfer_timer[i]) {
+-00745                         DWC_TIMER_FREE(dwc_otg_hcd->core_if->hc_xfer_timer[i]);
+-00746                 }
+-00747 #endif
+-00748                 if (hc != NULL) {
+-00749                         DWC_DEBUGPL(DBG_HCDV, "HCD Free channel #%i, hc=%p\n",
+-00750                                     i, hc);
+-00751                         DWC_FREE(hc);
+-00752                 }
+-00753         }
+-00754 
+-00755         if (dwc_otg_hcd->core_if->dma_enable) {
+-00756                 if (dwc_otg_hcd->status_buf_dma) {
+-00757                         DWC_DMA_FREE(DWC_OTG_HCD_STATUS_BUF_SIZE,
+-00758                                      dwc_otg_hcd->status_buf,
+-00759                                      dwc_otg_hcd->status_buf_dma);
+-00760                 }
+-00761         } else if (dwc_otg_hcd->status_buf != NULL) {
+-00762                 DWC_FREE(dwc_otg_hcd->status_buf);
+-00763         }
+-00764         DWC_SPINLOCK_FREE(dwc_otg_hcd->lock);
+-00765         /* Set core_if's lock pointer to NULL */
+-00766         dwc_otg_hcd->core_if->lock = NULL;
+-00767 
+-00768         DWC_TIMER_FREE(dwc_otg_hcd->conn_timer);
+-00769         DWC_TASK_FREE(dwc_otg_hcd->reset_tasklet);
+-00770 
+-00771 #ifdef DWC_DEV_SRPCAP
+-00772         if (dwc_otg_hcd->core_if->power_down == 2 &&
+-00773             dwc_otg_hcd->core_if->pwron_timer) {
+-00774                 DWC_TIMER_FREE(dwc_otg_hcd->core_if->pwron_timer);
+-00775         }
+-00776 #endif
+-00777         DWC_FREE(dwc_otg_hcd);
+-00778 }
+-00779 
+-00780 int dwc_otg_hcd_init(dwc_otg_hcd_t * hcd, dwc_otg_core_if_t * core_if)
+-00781 {
+-00782         int retval = 0;
+-00783         int num_channels;
+-00784         int i;
+-00785         dwc_hc_t *channel;
+-00786 
+-00787         hcd->lock = DWC_SPINLOCK_ALLOC();
+-00788         if (!hcd->lock) {
+-00789                 DWC_ERROR("Could not allocate lock for pcd");
+-00790                 DWC_FREE(hcd);
+-00791                 retval = -DWC_E_NO_MEMORY;
+-00792                 goto out;
+-00793         }
+-00794         hcd->core_if = core_if;
+-00795 
+-00796         /* Register the HCD CIL Callbacks */
+-00797         dwc_otg_cil_register_hcd_callbacks(hcd->core_if,
+-00798                                            &hcd_cil_callbacks, hcd);
+-00799 
+-00800         /* Initialize the non-periodic schedule. */
+-00801         DWC_LIST_INIT(&hcd->non_periodic_sched_inactive);
+-00802         DWC_LIST_INIT(&hcd->non_periodic_sched_active);
+-00803 
+-00804         /* Initialize the periodic schedule. */
+-00805         DWC_LIST_INIT(&hcd->periodic_sched_inactive);
+-00806         DWC_LIST_INIT(&hcd->periodic_sched_ready);
+-00807         DWC_LIST_INIT(&hcd->periodic_sched_assigned);
+-00808         DWC_LIST_INIT(&hcd->periodic_sched_queued);
+-00809 
+-00810         /*
+-00811          * Create a host channel descriptor for each host channel implemented
+-00812          * in the controller. Initialize the channel descriptor array.
+-00813          */
+-00814         DWC_CIRCLEQ_INIT(&hcd->free_hc_list);
+-00815         num_channels = hcd->core_if->core_params->host_channels;
+-00816         DWC_MEMSET(hcd->hc_ptr_array, 0, sizeof(hcd->hc_ptr_array));
+-00817         for (i = 0; i < num_channels; i++) {
+-00818                 channel = DWC_ALLOC(sizeof(dwc_hc_t));
+-00819                 if (channel == NULL) {
+-00820                         retval = -DWC_E_NO_MEMORY;
+-00821                         DWC_ERROR("%s: host channel allocation failed\n",
+-00822                                   __func__);
+-00823                         dwc_otg_hcd_free(hcd);
+-00824                         goto out;
+-00825                 }
+-00826                 channel->hc_num = i;
+-00827                 hcd->hc_ptr_array[i] = channel;
+-00828 #ifdef DEBUG
+-00829                 hcd->core_if->hc_xfer_timer[i] =
+-00830                     DWC_TIMER_ALLOC("hc timer", hc_xfer_timeout,
+-00831                                     &hcd->core_if->hc_xfer_info[i]);
+-00832 #endif
+-00833                 DWC_DEBUGPL(DBG_HCDV, "HCD Added channel #%d, hc=%p\n", i,
+-00834                             channel);
+-00835         }
+-00836 
+-00837         /* Initialize the Connection timeout timer. */
+-00838         hcd->conn_timer = DWC_TIMER_ALLOC("Connection timer",
+-00839                                           dwc_otg_hcd_connect_timeout, 0);
+-00840 
+-00841         /* Initialize reset tasklet. */
+-00842         hcd->reset_tasklet = DWC_TASK_ALLOC("reset_tasklet", reset_tasklet_func, hcd);
+-00843 #ifdef DWC_DEV_SRPCAP
+-00844         if (hcd->core_if->power_down == 2) {
+-00845                 /* Initialize Power on timer for Host power up in case hibernation */
+-00846                 hcd->core_if->pwron_timer = DWC_TIMER_ALLOC("PWRON TIMER",
+-00847                                                                         dwc_otg_hcd_power_up, core_if);
+-00848         }
+-00849 #endif  
+-00850 
+-00851         /*
+-00852          * Allocate space for storing data on status transactions. Normally no
+-00853          * data is sent, but this space acts as a bit bucket. This must be
+-00854          * done after usb_add_hcd since that function allocates the DMA buffer
+-00855          * pool.
+-00856          */
+-00857         if (hcd->core_if->dma_enable) {
+-00858                 hcd->status_buf =
+-00859                     DWC_DMA_ALLOC(DWC_OTG_HCD_STATUS_BUF_SIZE,
+-00860                                   &hcd->status_buf_dma);
+-00861         } else {
+-00862                 hcd->status_buf = DWC_ALLOC(DWC_OTG_HCD_STATUS_BUF_SIZE);
+-00863         }
+-00864         if (!hcd->status_buf) {
+-00865                 retval = -DWC_E_NO_MEMORY;
+-00866                 DWC_ERROR("%s: status_buf allocation failed\n", __func__);
+-00867                 dwc_otg_hcd_free(hcd);
+-00868                 goto out;
+-00869         }
+-00870 
+-00871         hcd->otg_port = 1;
+-00872         hcd->frame_list = NULL;
+-00873         hcd->frame_list_dma = 0;
+-00874         hcd->periodic_qh_count = 0;
+-00875 out:
+-00876         return retval;
+-00877 }
+-00878 
+-00879 void dwc_otg_hcd_remove(dwc_otg_hcd_t * hcd)
+-00880 {
+-00881         /* Turn off all host-specific interrupts. */
+-00882         dwc_otg_disable_host_interrupts(hcd->core_if);
+-00883 
+-00884         dwc_otg_hcd_free(hcd);
+-00885 }
+-00886 
+-00890 static void dwc_otg_hcd_reinit(dwc_otg_hcd_t * hcd)
+-00891 {
+-00892         int num_channels;
+-00893         int i;
+-00894         dwc_hc_t *channel;
+-00895         dwc_hc_t *channel_tmp;
+-00896 
+-00897         hcd->flags.d32 = 0;
+-00898 
+-00899         hcd->non_periodic_qh_ptr = &hcd->non_periodic_sched_active;
+-00900         hcd->non_periodic_channels = 0;
+-00901         hcd->periodic_channels = 0;
+-00902 
+-00903         /*
+-00904          * Put all channels in the free channel list and clean up channel
+-00905          * states.
+-00906          */
+-00907         DWC_CIRCLEQ_FOREACH_SAFE(channel, channel_tmp,
+-00908                                  &hcd->free_hc_list, hc_list_entry) {
+-00909                 DWC_CIRCLEQ_REMOVE(&hcd->free_hc_list, channel, hc_list_entry);
+-00910         }
+-00911 
+-00912         num_channels = hcd->core_if->core_params->host_channels;
+-00913         for (i = 0; i < num_channels; i++) {
+-00914                 channel = hcd->hc_ptr_array[i];
+-00915                 DWC_CIRCLEQ_INSERT_TAIL(&hcd->free_hc_list, channel,
+-00916                                         hc_list_entry);
+-00917                 dwc_otg_hc_cleanup(hcd->core_if, channel);
+-00918         }
+-00919 
+-00920         /* Initialize the DWC core for host mode operation. */
+-00921         dwc_otg_core_host_init(hcd->core_if);
+-00922 
+-00923         /* Set core_if's lock pointer to the hcd->lock */
+-00924         hcd->core_if->lock = hcd->lock;
+-00925 }
+-00926 
+-00936 static void assign_and_init_hc(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
+-00937 {
+-00938         dwc_hc_t *hc;
+-00939         dwc_otg_qtd_t *qtd;
+-00940         dwc_otg_hcd_urb_t *urb;
+-00941         void* ptr = NULL;
+-00942 
+-00943         DWC_DEBUGPL(DBG_HCDV, "%s(%p,%p)\n", __func__, hcd, qh);
+-00944 
+-00945         hc = DWC_CIRCLEQ_FIRST(&hcd->free_hc_list);
+-00946 
+-00947         /* Remove the host channel from the free list. */
+-00948         DWC_CIRCLEQ_REMOVE_INIT(&hcd->free_hc_list, hc, hc_list_entry);
+-00949 
+-00950         qtd = DWC_CIRCLEQ_FIRST(&qh->qtd_list);
+-00951 
+-00952         urb = qtd->urb;
+-00953         qh->channel = hc;
+-00954 
+-00955         qtd->in_process = 1;
+-00956 
+-00957         /*
+-00958          * Use usb_pipedevice to determine device address. This address is
+-00959          * 0 before the SET_ADDRESS command and the correct address afterward.
+-00960          */
+-00961         hc->dev_addr = dwc_otg_hcd_get_dev_addr(&urb->pipe_info);
+-00962         hc->ep_num = dwc_otg_hcd_get_ep_num(&urb->pipe_info);
+-00963         hc->speed = qh->dev_speed;
+-00964         hc->max_packet = dwc_max_packet(qh->maxp);
+-00965 
+-00966         hc->xfer_started = 0;
+-00967         hc->halt_status = DWC_OTG_HC_XFER_NO_HALT_STATUS;
+-00968         hc->error_state = (qtd->error_count > 0);
+-00969         hc->halt_on_queue = 0;
+-00970         hc->halt_pending = 0;
+-00971         hc->requests = 0;
+-00972 
+-00973         /*
+-00974          * The following values may be modified in the transfer type section
+-00975          * below. The xfer_len value may be reduced when the transfer is
+-00976          * started to accommodate the max widths of the XferSize and PktCnt
+-00977          * fields in the HCTSIZn register.
+-00978          */
+-00979 
+-00980         hc->ep_is_in = (dwc_otg_hcd_is_pipe_in(&urb->pipe_info) != 0);
+-00981         if (hc->ep_is_in) {
+-00982                 hc->do_ping = 0;
+-00983         } else {
+-00984                 hc->do_ping = qh->ping_state;
+-00985         }
+-00986 
+-00987         hc->data_pid_start = qh->data_toggle;
+-00988         hc->multi_count = 1;
+-00989 
+-00990         if (hcd->core_if->dma_enable) {
+-00991                 hc->xfer_buff = (uint8_t *) urb->dma + urb->actual_length;
+-00992 
+-00993                 /* For non-dword aligned case */
+-00994                 if (((unsigned long)hc->xfer_buff & 0x3)
+-00995                     && !hcd->core_if->dma_desc_enable) {
+-00996                         ptr = (uint8_t *) urb->buf + urb->actual_length;
+-00997                 }
+-00998         } else {
+-00999                 hc->xfer_buff = (uint8_t *) urb->buf + urb->actual_length;
+-01000         }
+-01001         hc->xfer_len = urb->length - urb->actual_length;
+-01002         hc->xfer_count = 0;
+-01003 
+-01004         /*
+-01005          * Set the split attributes
+-01006          */
+-01007         hc->do_split = 0;
+-01008         if (qh->do_split) {
+-01009                 uint32_t hub_addr, port_addr;
+-01010                 hc->do_split = 1;
+-01011                 hc->xact_pos = qtd->isoc_split_pos;
+-01012                 hc->complete_split = qtd->complete_split;
+-01013                 hcd->fops->hub_info(hcd, urb->priv, &hub_addr, &port_addr);
+-01014                 hc->hub_addr = (uint8_t) hub_addr;
+-01015                 hc->port_addr = (uint8_t) port_addr;
+-01016         }
+-01017 
+-01018         switch (dwc_otg_hcd_get_pipe_type(&urb->pipe_info)) {
+-01019         case UE_CONTROL:
+-01020                 hc->ep_type = DWC_OTG_EP_TYPE_CONTROL;
+-01021                 switch (qtd->control_phase) {
+-01022                 case DWC_OTG_CONTROL_SETUP:
+-01023                         DWC_DEBUGPL(DBG_HCDV, "  Control setup transaction\n");
+-01024                         hc->do_ping = 0;
+-01025                         hc->ep_is_in = 0;
+-01026                         hc->data_pid_start = DWC_OTG_HC_PID_SETUP;
+-01027                         if (hcd->core_if->dma_enable) {
+-01028                                 hc->xfer_buff = (uint8_t *) urb->setup_dma;
+-01029                         } else {
+-01030                                 hc->xfer_buff = (uint8_t *) urb->setup_packet;
+-01031                         }
+-01032                         hc->xfer_len = 8;
+-01033                         ptr = NULL;
+-01034                         break;
+-01035                 case DWC_OTG_CONTROL_DATA:
+-01036                         DWC_DEBUGPL(DBG_HCDV, "  Control data transaction\n");
+-01037                         hc->data_pid_start = qtd->data_toggle;
+-01038                         break;
+-01039                 case DWC_OTG_CONTROL_STATUS:
+-01040                         /*
+-01041                          * Direction is opposite of data direction or IN if no
+-01042                          * data.
+-01043                          */
+-01044                         DWC_DEBUGPL(DBG_HCDV, "  Control status transaction\n");
+-01045                         if (urb->length == 0) {
+-01046                                 hc->ep_is_in = 1;
+-01047                         } else {
+-01048                                 hc->ep_is_in =
+-01049                                     dwc_otg_hcd_is_pipe_out(&urb->pipe_info);
+-01050                         }
+-01051                         if (hc->ep_is_in) {
+-01052                                 hc->do_ping = 0;
+-01053                         }
+-01054 
+-01055                         hc->data_pid_start = DWC_OTG_HC_PID_DATA1;
+-01056 
+-01057                         hc->xfer_len = 0;
+-01058                         if (hcd->core_if->dma_enable) {
+-01059                                 hc->xfer_buff = (uint8_t *) hcd->status_buf_dma;
+-01060                         } else {
+-01061                                 hc->xfer_buff = (uint8_t *) hcd->status_buf;
+-01062                         }
+-01063                         ptr = NULL;
+-01064                         break;
+-01065                 }
+-01066                 break;
+-01067         case UE_BULK:
+-01068                 hc->ep_type = DWC_OTG_EP_TYPE_BULK;
+-01069                 break;
+-01070         case UE_INTERRUPT:
+-01071                 hc->ep_type = DWC_OTG_EP_TYPE_INTR;
+-01072                 break;
+-01073         case UE_ISOCHRONOUS:
+-01074                 {
+-01075                         struct dwc_otg_hcd_iso_packet_desc *frame_desc;
+-01076 
+-01077                         hc->ep_type = DWC_OTG_EP_TYPE_ISOC;
+-01078 
+-01079                         if (hcd->core_if->dma_desc_enable)
+-01080                                 break;
+-01081 
+-01082                         frame_desc = &urb->iso_descs[qtd->isoc_frame_index];
+-01083 
+-01084                         frame_desc->status = 0;
+-01085 
+-01086                         if (hcd->core_if->dma_enable) {
+-01087                                 hc->xfer_buff = (uint8_t *) urb->dma;
+-01088                         } else {
+-01089                                 hc->xfer_buff = (uint8_t *) urb->buf;
+-01090                         }
+-01091                         hc->xfer_buff +=
+-01092                             frame_desc->offset + qtd->isoc_split_offset;
+-01093                         hc->xfer_len =
+-01094                             frame_desc->length - qtd->isoc_split_offset;
+-01095 
+-01096                         /* For non-dword aligned buffers */
+-01097                         if (((unsigned long)hc->xfer_buff & 0x3)
+-01098                             && hcd->core_if->dma_enable) {
+-01099                                 ptr =
+-01100                                     (uint8_t *) urb->buf + frame_desc->offset +
+-01101                                     qtd->isoc_split_offset;
+-01102                         } else
+-01103                                 ptr = NULL;
+-01104 
+-01105                         if (hc->xact_pos == DWC_HCSPLIT_XACTPOS_ALL) {
+-01106                                 if (hc->xfer_len <= 188) {
+-01107                                         hc->xact_pos = DWC_HCSPLIT_XACTPOS_ALL;
+-01108                                 } else {
+-01109                                         hc->xact_pos =
+-01110                                             DWC_HCSPLIT_XACTPOS_BEGIN;
+-01111                                 }
+-01112                         }
+-01113                 }
+-01114                 break;
+-01115         }
+-01116         /* non DWORD-aligned buffer case */     
+-01117         if (ptr) {
+-01118                 uint32_t buf_size;
+-01119                 if (hc->ep_type != DWC_OTG_EP_TYPE_ISOC) {
+-01120                         buf_size = hcd->core_if->core_params->max_transfer_size;
+-01121                 } else {                                
+-01122                         buf_size = 4096;
+-01123                 }
+-01124                 if (!qh->dw_align_buf) {
+-01125                         qh->dw_align_buf = DWC_DMA_ALLOC_ATOMIC(buf_size,
+-01126                                                          &qh->dw_align_buf_dma);
+-01127                         if (!qh->dw_align_buf) {
+-01128                                 DWC_ERROR
+-01129                                     ("%s: Failed to allocate memory to handle "
+-01130                                      "non-dword aligned buffer case\n",
+-01131                                      __func__);
+-01132                                 return;
+-01133                         }
+-01134                 }
+-01135                 if (!hc->ep_is_in) {
+-01136                         dwc_memcpy(qh->dw_align_buf, ptr, hc->xfer_len);
+-01137                 }
+-01138                 hc->align_buff = qh->dw_align_buf_dma;
+-01139         } else {
+-01140                 hc->align_buff = 0;
+-01141         }
+-01142 
+-01143         if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
+-01144             hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
+-01145                 /*
+-01146                  * This value may be modified when the transfer is started to
+-01147                  * reflect the actual transfer length.
+-01148                  */
+-01149                 hc->multi_count = dwc_hb_mult(qh->maxp);
+-01150         }
+-01151 
+-01152         if (hcd->core_if->dma_desc_enable)
+-01153                 hc->desc_list_addr = qh->desc_list_dma;
+-01154 
+-01155         dwc_otg_hc_init(hcd->core_if, hc);
+-01156         hc->qh = qh;
+-01157 }
+-01158 
+-01168 dwc_otg_transaction_type_e dwc_otg_hcd_select_transactions(dwc_otg_hcd_t * hcd)
+-01169 {
+-01170         dwc_list_link_t *qh_ptr;
+-01171         dwc_otg_qh_t *qh;
+-01172         int num_channels;
+-01173         dwc_otg_transaction_type_e ret_val = DWC_OTG_TRANSACTION_NONE;
+-01174 
+-01175 #ifdef DEBUG_SOF
+-01176         DWC_DEBUGPL(DBG_HCD, "  Select Transactions\n");
+-01177 #endif
+-01178 
+-01179         /* Process entries in the periodic ready list. */
+-01180         qh_ptr = DWC_LIST_FIRST(&hcd->periodic_sched_ready);
+-01181 
+-01182         while (qh_ptr != &hcd->periodic_sched_ready &&
+-01183                !DWC_CIRCLEQ_EMPTY(&hcd->free_hc_list)) {
+-01184 
+-01185                 qh = DWC_LIST_ENTRY(qh_ptr, dwc_otg_qh_t, qh_list_entry);
+-01186                 assign_and_init_hc(hcd, qh);
+-01187 
+-01188                 /*
+-01189                  * Move the QH from the periodic ready schedule to the
+-01190                  * periodic assigned schedule.
+-01191                  */
+-01192                 qh_ptr = DWC_LIST_NEXT(qh_ptr);
+-01193                 DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_assigned,
+-01194                                    &qh->qh_list_entry);
+-01195 
+-01196                 ret_val = DWC_OTG_TRANSACTION_PERIODIC;
+-01197         }
+-01198 
+-01199         /*
+-01200          * Process entries in the inactive portion of the non-periodic
+-01201          * schedule. Some free host channels may not be used if they are
+-01202          * reserved for periodic transfers.
+-01203          */
+-01204         qh_ptr = hcd->non_periodic_sched_inactive.next;
+-01205         num_channels = hcd->core_if->core_params->host_channels;
+-01206         while (qh_ptr != &hcd->non_periodic_sched_inactive &&
+-01207                (hcd->non_periodic_channels <
+-01208                 num_channels - hcd->periodic_channels) &&
+-01209                !DWC_CIRCLEQ_EMPTY(&hcd->free_hc_list)) {
+-01210 
+-01211                 qh = DWC_LIST_ENTRY(qh_ptr, dwc_otg_qh_t, qh_list_entry);
+-01212 
+-01213                 assign_and_init_hc(hcd, qh);
+-01214 
+-01215                 /*
+-01216                  * Move the QH from the non-periodic inactive schedule to the
+-01217                  * non-periodic active schedule.
+-01218                  */
+-01219                 qh_ptr = DWC_LIST_NEXT(qh_ptr);
+-01220                 DWC_LIST_MOVE_HEAD(&hcd->non_periodic_sched_active,
+-01221                                    &qh->qh_list_entry);
+-01222 
+-01223                 if (ret_val == DWC_OTG_TRANSACTION_NONE) {
+-01224                         ret_val = DWC_OTG_TRANSACTION_NON_PERIODIC;
+-01225                 } else {
+-01226                         ret_val = DWC_OTG_TRANSACTION_ALL;
+-01227                 }
+-01228 
+-01229                 hcd->non_periodic_channels++;
+-01230         }
+-01231 
+-01232         return ret_val;
+-01233 }
+-01234 
+-01253 static int queue_transaction(dwc_otg_hcd_t * hcd,
+-01254                              dwc_hc_t * hc, uint16_t fifo_dwords_avail)
+-01255 {
+-01256         int retval;
+-01257 
+-01258         if (hcd->core_if->dma_enable) {
+-01259                 if (hcd->core_if->dma_desc_enable) {
+-01260                         if (!hc->xfer_started
+-01261                             || (hc->ep_type == DWC_OTG_EP_TYPE_ISOC)) {
+-01262                                 dwc_otg_hcd_start_xfer_ddma(hcd, hc->qh);
+-01263                                 hc->qh->ping_state = 0;
+-01264                         }
+-01265                 } else if (!hc->xfer_started) {
+-01266                         dwc_otg_hc_start_transfer(hcd->core_if, hc);
+-01267                         hc->qh->ping_state = 0;
+-01268                 }
+-01269                 retval = 0;
+-01270         } else if (hc->halt_pending) {
+-01271                 /* Don't queue a request if the channel has been halted. */
+-01272                 retval = 0;
+-01273         } else if (hc->halt_on_queue) {
+-01274                 dwc_otg_hc_halt(hcd->core_if, hc, hc->halt_status);
+-01275                 retval = 0;
+-01276         } else if (hc->do_ping) {
+-01277                 if (!hc->xfer_started) {
+-01278                         dwc_otg_hc_start_transfer(hcd->core_if, hc);
+-01279                 }
+-01280                 retval = 0;
+-01281         } else if (!hc->ep_is_in || hc->data_pid_start == DWC_OTG_HC_PID_SETUP) {
+-01282                 if ((fifo_dwords_avail * 4) >= hc->max_packet) {
+-01283                         if (!hc->xfer_started) {
+-01284                                 dwc_otg_hc_start_transfer(hcd->core_if, hc);
+-01285                                 retval = 1;
+-01286                         } else {
+-01287                                 retval =
+-01288                                     dwc_otg_hc_continue_transfer(hcd->core_if,
+-01289                                                                  hc);
+-01290                         }
+-01291                 } else {
+-01292                         retval = -1;
+-01293                 }
+-01294         } else {
+-01295                 if (!hc->xfer_started) {
+-01296                         dwc_otg_hc_start_transfer(hcd->core_if, hc);
+-01297                         retval = 1;
+-01298                 } else {
+-01299                         retval = dwc_otg_hc_continue_transfer(hcd->core_if, hc);
+-01300                 }
+-01301         }
+-01302 
+-01303         return retval;
+-01304 }
+-01305 
+-01313 static void process_periodic_channels(dwc_otg_hcd_t * hcd)
+-01314 {
+-01315         hptxsts_data_t tx_status;
+-01316         dwc_list_link_t *qh_ptr;
+-01317         dwc_otg_qh_t *qh;
+-01318         int status;
+-01319         int no_queue_space = 0;
+-01320         int no_fifo_space = 0;
+-01321 
+-01322         dwc_otg_host_global_regs_t *host_regs;
+-01323         host_regs = hcd->core_if->host_if->host_global_regs;
+-01324 
+-01325         DWC_DEBUGPL(DBG_HCDV, "Queue periodic transactions\n");
+-01326 #ifdef DEBUG
+-01327         tx_status.d32 = DWC_READ_REG32(&host_regs->hptxsts);
+-01328         DWC_DEBUGPL(DBG_HCDV,
+-01329                     "  P Tx Req Queue Space Avail (before queue): %d\n",
+-01330                     tx_status.b.ptxqspcavail);
+-01331         DWC_DEBUGPL(DBG_HCDV, "  P Tx FIFO Space Avail (before queue): %d\n",
+-01332                     tx_status.b.ptxfspcavail);
+-01333 #endif
+-01334 
+-01335         qh_ptr = hcd->periodic_sched_assigned.next;
+-01336         while (qh_ptr != &hcd->periodic_sched_assigned) {
+-01337                 tx_status.d32 = DWC_READ_REG32(&host_regs->hptxsts);
+-01338                 if (tx_status.b.ptxqspcavail == 0) {
+-01339                         no_queue_space = 1;
+-01340                         break;
+-01341                 }
+-01342 
+-01343                 qh = DWC_LIST_ENTRY(qh_ptr, dwc_otg_qh_t, qh_list_entry);
+-01344 
+-01345                 /*
+-01346                  * Set a flag if we're queuing high-bandwidth in slave mode.
+-01347                  * The flag prevents any halts to get into the request queue in
+-01348                  * the middle of multiple high-bandwidth packets getting queued.
+-01349                  */
+-01350                 if (!hcd->core_if->dma_enable && qh->channel->multi_count > 1) {
+-01351                         hcd->core_if->queuing_high_bandwidth = 1;
+-01352                 }
+-01353                 status =
+-01354                     queue_transaction(hcd, qh->channel,
+-01355                                       tx_status.b.ptxfspcavail);
+-01356                 if (status < 0) {
+-01357                         no_fifo_space = 1;
+-01358                         break;
+-01359                 }
+-01360 
+-01361                 /*
+-01362                  * In Slave mode, stay on the current transfer until there is
+-01363                  * nothing more to do or the high-bandwidth request count is
+-01364                  * reached. In DMA mode, only need to queue one request. The
+-01365                  * controller automatically handles multiple packets for
+-01366                  * high-bandwidth transfers.
+-01367                  */
+-01368                 if (hcd->core_if->dma_enable || status == 0 ||
+-01369                     qh->channel->requests == qh->channel->multi_count) {
+-01370                         qh_ptr = qh_ptr->next;
+-01371                         /*
+-01372                          * Move the QH from the periodic assigned schedule to
+-01373                          * the periodic queued schedule.
+-01374                          */
+-01375                         DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_queued,
+-01376                                            &qh->qh_list_entry);
+-01377 
+-01378                         /* done queuing high bandwidth */
+-01379                         hcd->core_if->queuing_high_bandwidth = 0;
+-01380                 }
+-01381         }
+-01382 
+-01383         if (!hcd->core_if->dma_enable) {
+-01384                 dwc_otg_core_global_regs_t *global_regs;
+-01385                 gintmsk_data_t intr_mask = {.d32 = 0 };
+-01386 
+-01387                 global_regs = hcd->core_if->core_global_regs;
+-01388                 intr_mask.b.ptxfempty = 1;
+-01389 #ifdef DEBUG
+-01390                 tx_status.d32 = DWC_READ_REG32(&host_regs->hptxsts);
+-01391                 DWC_DEBUGPL(DBG_HCDV,
+-01392                             "  P Tx Req Queue Space Avail (after queue): %d\n",
+-01393                             tx_status.b.ptxqspcavail);
+-01394                 DWC_DEBUGPL(DBG_HCDV,
+-01395                             "  P Tx FIFO Space Avail (after queue): %d\n",
+-01396                             tx_status.b.ptxfspcavail);
+-01397 #endif
+-01398                 if (!DWC_LIST_EMPTY(&hcd->periodic_sched_assigned) ||
+-01399                     no_queue_space || no_fifo_space) {
+-01400                         /*
+-01401                          * May need to queue more transactions as the request
+-01402                          * queue or Tx FIFO empties. Enable the periodic Tx
+-01403                          * FIFO empty interrupt. (Always use the half-empty
+-01404                          * level to ensure that new requests are loaded as
+-01405                          * soon as possible.)
+-01406                          */
+-01407                         DWC_MODIFY_REG32(&global_regs->gintmsk, 0,
+-01408                                          intr_mask.d32);
+-01409                 } else {
+-01410                         /*
+-01411                          * Disable the Tx FIFO empty interrupt since there are
+-01412                          * no more transactions that need to be queued right
+-01413                          * now. This function is called from interrupt
+-01414                          * handlers to queue more transactions as transfer
+-01415                          * states change.
+-01416                          */
+-01417                         DWC_MODIFY_REG32(&global_regs->gintmsk, intr_mask.d32,
+-01418                                          0);
+-01419                 }
+-01420         }
+-01421 }
+-01422 
+-01430 static void process_non_periodic_channels(dwc_otg_hcd_t * hcd)
+-01431 {
+-01432         gnptxsts_data_t tx_status;
+-01433         dwc_list_link_t *orig_qh_ptr;
+-01434         dwc_otg_qh_t *qh;
+-01435         int status;
+-01436         int no_queue_space = 0;
+-01437         int no_fifo_space = 0;
+-01438         int more_to_do = 0;
+-01439 
+-01440         dwc_otg_core_global_regs_t *global_regs =
+-01441             hcd->core_if->core_global_regs;
+-01442 
+-01443         DWC_DEBUGPL(DBG_HCDV, "Queue non-periodic transactions\n");
+-01444 #ifdef DEBUG
+-01445         tx_status.d32 = DWC_READ_REG32(&global_regs->gnptxsts);
+-01446         DWC_DEBUGPL(DBG_HCDV,
+-01447                     "  NP Tx Req Queue Space Avail (before queue): %d\n",
+-01448                     tx_status.b.nptxqspcavail);
+-01449         DWC_DEBUGPL(DBG_HCDV, "  NP Tx FIFO Space Avail (before queue): %d\n",
+-01450                     tx_status.b.nptxfspcavail);
+-01451 #endif
+-01452         /*
+-01453          * Keep track of the starting point. Skip over the start-of-list
+-01454          * entry.
+-01455          */
+-01456         if (hcd->non_periodic_qh_ptr == &hcd->non_periodic_sched_active) {
+-01457                 hcd->non_periodic_qh_ptr = hcd->non_periodic_qh_ptr->next;
+-01458         }
+-01459         orig_qh_ptr = hcd->non_periodic_qh_ptr;
+-01460 
+-01461         /*
+-01462          * Process once through the active list or until no more space is
+-01463          * available in the request queue or the Tx FIFO.
+-01464          */
+-01465         do {
+-01466                 tx_status.d32 = DWC_READ_REG32(&global_regs->gnptxsts);
+-01467                 if (!hcd->core_if->dma_enable && tx_status.b.nptxqspcavail == 0) {
+-01468                         no_queue_space = 1;
+-01469                         break;
+-01470                 }
+-01471 
+-01472                 qh = DWC_LIST_ENTRY(hcd->non_periodic_qh_ptr, dwc_otg_qh_t,
+-01473                                     qh_list_entry);
+-01474                 status =
+-01475                     queue_transaction(hcd, qh->channel,
+-01476                                       tx_status.b.nptxfspcavail);
+-01477 
+-01478                 if (status > 0) {
+-01479                         more_to_do = 1;
+-01480                 } else if (status < 0) {
+-01481                         no_fifo_space = 1;
+-01482                         break;
+-01483                 }
+-01484 
+-01485                 /* Advance to next QH, skipping start-of-list entry. */
+-01486                 hcd->non_periodic_qh_ptr = hcd->non_periodic_qh_ptr->next;
+-01487                 if (hcd->non_periodic_qh_ptr == &hcd->non_periodic_sched_active) {
+-01488                         hcd->non_periodic_qh_ptr =
+-01489                             hcd->non_periodic_qh_ptr->next;
+-01490                 }
+-01491 
+-01492         } while (hcd->non_periodic_qh_ptr != orig_qh_ptr);
+-01493 
+-01494         if (!hcd->core_if->dma_enable) {
+-01495                 gintmsk_data_t intr_mask = {.d32 = 0 };
+-01496                 intr_mask.b.nptxfempty = 1;
+-01497 
+-01498 #ifdef DEBUG
+-01499                 tx_status.d32 = DWC_READ_REG32(&global_regs->gnptxsts);
+-01500                 DWC_DEBUGPL(DBG_HCDV,
+-01501                             "  NP Tx Req Queue Space Avail (after queue): %d\n",
+-01502                             tx_status.b.nptxqspcavail);
+-01503                 DWC_DEBUGPL(DBG_HCDV,
+-01504                             "  NP Tx FIFO Space Avail (after queue): %d\n",
+-01505                             tx_status.b.nptxfspcavail);
+-01506 #endif
+-01507                 if (more_to_do || no_queue_space || no_fifo_space) {
+-01508                         /*
+-01509                          * May need to queue more transactions as the request
+-01510                          * queue or Tx FIFO empties. Enable the non-periodic
+-01511                          * Tx FIFO empty interrupt. (Always use the half-empty
+-01512                          * level to ensure that new requests are loaded as
+-01513                          * soon as possible.)
+-01514                          */
+-01515                         DWC_MODIFY_REG32(&global_regs->gintmsk, 0,
+-01516                                          intr_mask.d32);
+-01517                 } else {
+-01518                         /*
+-01519                          * Disable the Tx FIFO empty interrupt since there are
+-01520                          * no more transactions that need to be queued right
+-01521                          * now. This function is called from interrupt
+-01522                          * handlers to queue more transactions as transfer
+-01523                          * states change.
+-01524                          */
+-01525                         DWC_MODIFY_REG32(&global_regs->gintmsk, intr_mask.d32,
+-01526                                          0);
+-01527                 }
+-01528         }
+-01529 }
+-01530 
+-01540 void dwc_otg_hcd_queue_transactions(dwc_otg_hcd_t * hcd,
+-01541                                     dwc_otg_transaction_type_e tr_type)
+-01542 {
+-01543 #ifdef DEBUG_SOF
+-01544         DWC_DEBUGPL(DBG_HCD, "Queue Transactions\n");
+-01545 #endif
+-01546         /* Process host channels associated with periodic transfers. */
+-01547         if ((tr_type == DWC_OTG_TRANSACTION_PERIODIC ||
+-01548              tr_type == DWC_OTG_TRANSACTION_ALL) &&
+-01549             !DWC_LIST_EMPTY(&hcd->periodic_sched_assigned)) {
+-01550 
+-01551                 process_periodic_channels(hcd);
+-01552         }
+-01553 
+-01554         /* Process host channels associated with non-periodic transfers. */
+-01555         if (tr_type == DWC_OTG_TRANSACTION_NON_PERIODIC ||
+-01556             tr_type == DWC_OTG_TRANSACTION_ALL) {
+-01557                 if (!DWC_LIST_EMPTY(&hcd->non_periodic_sched_active)) {
+-01558                         process_non_periodic_channels(hcd);
+-01559                 } else {
+-01560                         /*
+-01561                          * Ensure NP Tx FIFO empty interrupt is disabled when
+-01562                          * there are no non-periodic transfers to process.
+-01563                          */
+-01564                         gintmsk_data_t gintmsk = {.d32 = 0 };
+-01565                         gintmsk.b.nptxfempty = 1;
+-01566                         DWC_MODIFY_REG32(&hcd->core_if->
+-01567                                          core_global_regs->gintmsk, gintmsk.d32,
+-01568                                          0);
+-01569                 }
+-01570         }
+-01571 }
+-01572 
+-01573 #ifdef DWC_HS_ELECT_TST
+-01574 /*
+-01575  * Quick and dirty hack to implement the HS Electrical Test
+-01576  * SINGLE_STEP_GET_DEVICE_DESCRIPTOR feature.
+-01577  *
+-01578  * This code was copied from our userspace app "hset". It sends a
+-01579  * Get Device Descriptor control sequence in two parts, first the
+-01580  * Setup packet by itself, followed some time later by the In and
+-01581  * Ack packets. Rather than trying to figure out how to add this
+-01582  * functionality to the normal driver code, we just hijack the
+-01583  * hardware, using these two function to drive the hardware
+-01584  * directly.
+-01585  */
+-01586 
+-01587 static dwc_otg_core_global_regs_t *global_regs;
+-01588 static dwc_otg_host_global_regs_t *hc_global_regs;
+-01589 static dwc_otg_hc_regs_t *hc_regs;
+-01590 static uint32_t *data_fifo;
+-01591 
+-01592 static void do_setup(void)
+-01593 {
+-01594         gintsts_data_t gintsts;
+-01595         hctsiz_data_t hctsiz;
+-01596         hcchar_data_t hcchar;
+-01597         haint_data_t haint;
+-01598         hcint_data_t hcint;
+-01599 
+-01600         /* Enable HAINTs */
+-01601         DWC_WRITE_REG32(&hc_global_regs->haintmsk, 0x0001);
+-01602 
+-01603         /* Enable HCINTs */
+-01604         DWC_WRITE_REG32(&hc_regs->hcintmsk, 0x04a3);
+-01605 
+-01606         /* Read GINTSTS */
+-01607         gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
+-01608 
+-01609         /* Read HAINT */
+-01610         haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
+-01611 
+-01612         /* Read HCINT */
+-01613         hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
+-01614 
+-01615         /* Read HCCHAR */
+-01616         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
+-01617 
+-01618         /* Clear HCINT */
+-01619         DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
+-01620 
+-01621         /* Clear HAINT */
+-01622         DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
+-01623 
+-01624         /* Clear GINTSTS */
+-01625         DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
+-01626 
+-01627         /* Read GINTSTS */
+-01628         gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
+-01629 
+-01630         /*
+-01631          * Send Setup packet (Get Device Descriptor)
+-01632          */
+-01633 
+-01634         /* Make sure channel is disabled */
+-01635         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
+-01636         if (hcchar.b.chen) {
+-01637                 hcchar.b.chdis = 1;
+-01638 //              hcchar.b.chen = 1;
+-01639                 DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
+-01640                 //sleep(1);
+-01641                 dwc_mdelay(1000);
+-01642 
+-01643                 /* Read GINTSTS */
+-01644                 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
+-01645 
+-01646                 /* Read HAINT */
+-01647                 haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
+-01648 
+-01649                 /* Read HCINT */
+-01650                 hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
+-01651 
+-01652                 /* Read HCCHAR */
+-01653                 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
+-01654 
+-01655                 /* Clear HCINT */
+-01656                 DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
+-01657 
+-01658                 /* Clear HAINT */
+-01659                 DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
+-01660 
+-01661                 /* Clear GINTSTS */
+-01662                 DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
+-01663 
+-01664                 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
+-01665         }
+-01666 
+-01667         /* Set HCTSIZ */
+-01668         hctsiz.d32 = 0;
+-01669         hctsiz.b.xfersize = 8;
+-01670         hctsiz.b.pktcnt = 1;
+-01671         hctsiz.b.pid = DWC_OTG_HC_PID_SETUP;
+-01672         DWC_WRITE_REG32(&hc_regs->hctsiz, hctsiz.d32);
+-01673 
+-01674         /* Set HCCHAR */
+-01675         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
+-01676         hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
+-01677         hcchar.b.epdir = 0;
+-01678         hcchar.b.epnum = 0;
+-01679         hcchar.b.mps = 8;
+-01680         hcchar.b.chen = 1;
+-01681         DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
+-01682 
+-01683         /* Fill FIFO with Setup data for Get Device Descriptor */
+-01684         data_fifo = (uint32_t *) ((char *)global_regs + 0x1000);
+-01685         DWC_WRITE_REG32(data_fifo++, 0x01000680);
+-01686         DWC_WRITE_REG32(data_fifo++, 0x00080000);
+-01687 
+-01688         gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
+-01689 
+-01690         /* Wait for host channel interrupt */
+-01691         do {
+-01692                 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
+-01693         } while (gintsts.b.hcintr == 0);
+-01694 
+-01695         /* Disable HCINTs */
+-01696         DWC_WRITE_REG32(&hc_regs->hcintmsk, 0x0000);
+-01697 
+-01698         /* Disable HAINTs */
+-01699         DWC_WRITE_REG32(&hc_global_regs->haintmsk, 0x0000);
+-01700 
+-01701         /* Read HAINT */
+-01702         haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
+-01703 
+-01704         /* Read HCINT */
+-01705         hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
+-01706 
+-01707         /* Read HCCHAR */
+-01708         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
+-01709 
+-01710         /* Clear HCINT */
+-01711         DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
+-01712 
+-01713         /* Clear HAINT */
+-01714         DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
+-01715 
+-01716         /* Clear GINTSTS */
+-01717         DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
+-01718 
+-01719         /* Read GINTSTS */
+-01720         gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
+-01721 }
+-01722 
+-01723 static void do_in_ack(void)
+-01724 {
+-01725         gintsts_data_t gintsts;
+-01726         hctsiz_data_t hctsiz;
+-01727         hcchar_data_t hcchar;
+-01728         haint_data_t haint;
+-01729         hcint_data_t hcint;
+-01730         host_grxsts_data_t grxsts;
+-01731 
+-01732         /* Enable HAINTs */
+-01733         DWC_WRITE_REG32(&hc_global_regs->haintmsk, 0x0001);
+-01734 
+-01735         /* Enable HCINTs */
+-01736         DWC_WRITE_REG32(&hc_regs->hcintmsk, 0x04a3);
+-01737 
+-01738         /* Read GINTSTS */
+-01739         gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
+-01740 
+-01741         /* Read HAINT */
+-01742         haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
+-01743 
+-01744         /* Read HCINT */
+-01745         hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
+-01746 
+-01747         /* Read HCCHAR */
+-01748         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
+-01749 
+-01750         /* Clear HCINT */
+-01751         DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
+-01752 
+-01753         /* Clear HAINT */
+-01754         DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
+-01755 
+-01756         /* Clear GINTSTS */
+-01757         DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
+-01758 
+-01759         /* Read GINTSTS */
+-01760         gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
+-01761 
+-01762         /*
+-01763          * Receive Control In packet
+-01764          */
+-01765 
+-01766         /* Make sure channel is disabled */
+-01767         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
+-01768         if (hcchar.b.chen) {
+-01769                 hcchar.b.chdis = 1;
+-01770                 hcchar.b.chen = 1;
+-01771                 DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
+-01772                 //sleep(1);
+-01773                 dwc_mdelay(1000);
+-01774 
+-01775                 /* Read GINTSTS */
+-01776                 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
+-01777 
+-01778                 /* Read HAINT */
+-01779                 haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
+-01780 
+-01781                 /* Read HCINT */
+-01782                 hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
+-01783 
+-01784                 /* Read HCCHAR */
+-01785                 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
+-01786 
+-01787                 /* Clear HCINT */
+-01788                 DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
+-01789 
+-01790                 /* Clear HAINT */
+-01791                 DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
+-01792 
+-01793                 /* Clear GINTSTS */
+-01794                 DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
+-01795 
+-01796                 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
+-01797         }
+-01798 
+-01799         /* Set HCTSIZ */
+-01800         hctsiz.d32 = 0;
+-01801         hctsiz.b.xfersize = 8;
+-01802         hctsiz.b.pktcnt = 1;
+-01803         hctsiz.b.pid = DWC_OTG_HC_PID_DATA1;
+-01804         DWC_WRITE_REG32(&hc_regs->hctsiz, hctsiz.d32);
+-01805 
+-01806         /* Set HCCHAR */
+-01807         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
+-01808         hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
+-01809         hcchar.b.epdir = 1;
+-01810         hcchar.b.epnum = 0;
+-01811         hcchar.b.mps = 8;
+-01812         hcchar.b.chen = 1;
+-01813         DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
+-01814 
+-01815         gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
+-01816 
+-01817         /* Wait for receive status queue interrupt */
+-01818         do {
+-01819                 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
+-01820         } while (gintsts.b.rxstsqlvl == 0);
+-01821 
+-01822         /* Read RXSTS */
+-01823         grxsts.d32 = DWC_READ_REG32(&global_regs->grxstsp);
+-01824 
+-01825         /* Clear RXSTSQLVL in GINTSTS */
+-01826         gintsts.d32 = 0;
+-01827         gintsts.b.rxstsqlvl = 1;
+-01828         DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
+-01829 
+-01830         switch (grxsts.b.pktsts) {
+-01831         case DWC_GRXSTS_PKTSTS_IN:
+-01832                 /* Read the data into the host buffer */
+-01833                 if (grxsts.b.bcnt > 0) {
+-01834                         int i;
+-01835                         int word_count = (grxsts.b.bcnt + 3) / 4;
+-01836 
+-01837                         data_fifo = (uint32_t *) ((char *)global_regs + 0x1000);
+-01838 
+-01839                         for (i = 0; i < word_count; i++) {
+-01840                                 (void)DWC_READ_REG32(data_fifo++);
+-01841                         }
+-01842                 }
+-01843                 break;
+-01844 
+-01845         default:
+-01846                 break;
+-01847         }
+-01848 
+-01849         gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
+-01850 
+-01851         /* Wait for receive status queue interrupt */
+-01852         do {
+-01853                 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
+-01854         } while (gintsts.b.rxstsqlvl == 0);
+-01855 
+-01856         /* Read RXSTS */
+-01857         grxsts.d32 = DWC_READ_REG32(&global_regs->grxstsp);
+-01858 
+-01859         /* Clear RXSTSQLVL in GINTSTS */
+-01860         gintsts.d32 = 0;
+-01861         gintsts.b.rxstsqlvl = 1;
+-01862         DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
+-01863 
+-01864         switch (grxsts.b.pktsts) {
+-01865         case DWC_GRXSTS_PKTSTS_IN_XFER_COMP:
+-01866                 break;
+-01867 
+-01868         default:
+-01869                 break;
+-01870         }
+-01871 
+-01872         gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
+-01873 
+-01874         /* Wait for host channel interrupt */
+-01875         do {
+-01876                 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
+-01877         } while (gintsts.b.hcintr == 0);
+-01878 
+-01879         /* Read HAINT */
+-01880         haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
+-01881 
+-01882         /* Read HCINT */
+-01883         hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
+-01884 
+-01885         /* Read HCCHAR */
+-01886         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
+-01887 
+-01888         /* Clear HCINT */
+-01889         DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
+-01890 
+-01891         /* Clear HAINT */
+-01892         DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
+-01893 
+-01894         /* Clear GINTSTS */
+-01895         DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
+-01896 
+-01897         /* Read GINTSTS */
+-01898         gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
+-01899 
+-01900 //      usleep(100000);
+-01901 //      mdelay(100);
+-01902         dwc_mdelay(1);
+-01903 
+-01904         /*
+-01905          * Send handshake packet
+-01906          */
+-01907 
+-01908         /* Read HAINT */
+-01909         haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
+-01910 
+-01911         /* Read HCINT */
+-01912         hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
+-01913 
+-01914         /* Read HCCHAR */
+-01915         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
+-01916 
+-01917         /* Clear HCINT */
+-01918         DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
+-01919 
+-01920         /* Clear HAINT */
+-01921         DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
+-01922 
+-01923         /* Clear GINTSTS */
+-01924         DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
+-01925 
+-01926         /* Read GINTSTS */
+-01927         gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
+-01928 
+-01929         /* Make sure channel is disabled */
+-01930         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
+-01931         if (hcchar.b.chen) {
+-01932                 hcchar.b.chdis = 1;
+-01933                 hcchar.b.chen = 1;
+-01934                 DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
+-01935                 //sleep(1);
+-01936                 dwc_mdelay(1000);
+-01937 
+-01938                 /* Read GINTSTS */
+-01939                 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
+-01940 
+-01941                 /* Read HAINT */
+-01942                 haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
+-01943 
+-01944                 /* Read HCINT */
+-01945                 hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
+-01946 
+-01947                 /* Read HCCHAR */
+-01948                 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
+-01949 
+-01950                 /* Clear HCINT */
+-01951                 DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
+-01952 
+-01953                 /* Clear HAINT */
+-01954                 DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
+-01955 
+-01956                 /* Clear GINTSTS */
+-01957                 DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
+-01958 
+-01959                 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
+-01960         }
+-01961 
+-01962         /* Set HCTSIZ */
+-01963         hctsiz.d32 = 0;
+-01964         hctsiz.b.xfersize = 0;
+-01965         hctsiz.b.pktcnt = 1;
+-01966         hctsiz.b.pid = DWC_OTG_HC_PID_DATA1;
+-01967         DWC_WRITE_REG32(&hc_regs->hctsiz, hctsiz.d32);
+-01968 
+-01969         /* Set HCCHAR */
+-01970         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
+-01971         hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
+-01972         hcchar.b.epdir = 0;
+-01973         hcchar.b.epnum = 0;
+-01974         hcchar.b.mps = 8;
+-01975         hcchar.b.chen = 1;
+-01976         DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
+-01977 
+-01978         gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
+-01979 
+-01980         /* Wait for host channel interrupt */
+-01981         do {
+-01982                 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
+-01983         } while (gintsts.b.hcintr == 0);
+-01984 
+-01985         /* Disable HCINTs */
+-01986         DWC_WRITE_REG32(&hc_regs->hcintmsk, 0x0000);
+-01987 
+-01988         /* Disable HAINTs */
+-01989         DWC_WRITE_REG32(&hc_global_regs->haintmsk, 0x0000);
+-01990 
+-01991         /* Read HAINT */
+-01992         haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
+-01993 
+-01994         /* Read HCINT */
+-01995         hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
+-01996 
+-01997         /* Read HCCHAR */
+-01998         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
+-01999 
+-02000         /* Clear HCINT */
+-02001         DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
+-02002 
+-02003         /* Clear HAINT */
+-02004         DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
+-02005 
+-02006         /* Clear GINTSTS */
+-02007         DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
+-02008 
+-02009         /* Read GINTSTS */
+-02010         gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
+-02011 }
+-02012 #endif
+-02013 
+-02015 int dwc_otg_hcd_hub_control(dwc_otg_hcd_t * dwc_otg_hcd,
+-02016                             uint16_t typeReq,
+-02017                             uint16_t wValue,
+-02018                             uint16_t wIndex, uint8_t * buf, uint16_t wLength)
+-02019 {
+-02020         int retval = 0;
+-02021 
+-02022         dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;
+-02023         usb_hub_descriptor_t *hub_desc;
+-02024         hprt0_data_t hprt0 = {.d32 = 0 };
+-02025 
+-02026         uint32_t port_status;
+-02027 
+-02028         switch (typeReq) {
+-02029         case UCR_CLEAR_HUB_FEATURE:
+-02030                 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
+-02031                             "ClearHubFeature 0x%x\n", wValue);
+-02032                 switch (wValue) {
+-02033                 case UHF_C_HUB_LOCAL_POWER:
+-02034                 case UHF_C_HUB_OVER_CURRENT:
+-02035                         /* Nothing required here */
+-02036                         break;
+-02037                 default:
+-02038                         retval = -DWC_E_INVALID;
+-02039                         DWC_ERROR("DWC OTG HCD - "
+-02040                                   "ClearHubFeature request %xh unknown\n",
+-02041                                   wValue);
+-02042                 }
+-02043                 break;
+-02044         case UCR_CLEAR_PORT_FEATURE:
+-02045 #ifdef CONFIG_USB_DWC_OTG_LPM
+-02046                 if (wValue != UHF_PORT_L1)
+-02047 #endif
+-02048                         if (!wIndex || wIndex > 1)
+-02049                                 goto error;
+-02050 
+-02051                 switch (wValue) {
+-02052                 case UHF_PORT_ENABLE:
+-02053                         DWC_DEBUGPL(DBG_ANY, "DWC OTG HCD HUB CONTROL - "
+-02054                                     "ClearPortFeature USB_PORT_FEAT_ENABLE\n");
+-02055                         hprt0.d32 = dwc_otg_read_hprt0(core_if);
+-02056                         hprt0.b.prtena = 1;
+-02057                         DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
+-02058                         break;
+-02059                 case UHF_PORT_SUSPEND:
+-02060                         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
+-02061                                     "ClearPortFeature USB_PORT_FEAT_SUSPEND\n");
+-02062 
+-02063                         if (core_if->power_down == 2) {
+-02064                                 dwc_otg_host_hibernation_restore(core_if, 0, 0);
+-02065                         } else {
+-02066                                 DWC_WRITE_REG32(core_if->pcgcctl, 0);
+-02067                                 dwc_mdelay(5);
+-02068 
+-02069                                 hprt0.d32 = dwc_otg_read_hprt0(core_if);
+-02070                                 hprt0.b.prtres = 1;
+-02071                                 DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
+-02072                                 hprt0.b.prtsusp = 0;
+-02073                                 /* Clear Resume bit */
+-02074                                 dwc_mdelay(100);
+-02075                                 hprt0.b.prtres = 0;
+-02076                                 DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
+-02077                         }
+-02078                         break;
+-02079 #ifdef CONFIG_USB_DWC_OTG_LPM
+-02080                 case UHF_PORT_L1:
+-02081                         {
+-02082                                 pcgcctl_data_t pcgcctl = {.d32 = 0 };
+-02083                                 glpmcfg_data_t lpmcfg = {.d32 = 0 };
+-02084 
+-02085                                 lpmcfg.d32 =
+-02086                                     DWC_READ_REG32(&core_if->
+-02087                                                    core_global_regs->glpmcfg);
+-02088                                 lpmcfg.b.en_utmi_sleep = 0;
+-02089                                 lpmcfg.b.hird_thres &= (~(1 << 4));
+-02090                                 lpmcfg.b.prt_sleep_sts = 1;
+-02091                                 DWC_WRITE_REG32(&core_if->
+-02092                                                 core_global_regs->glpmcfg,
+-02093                                                 lpmcfg.d32);
+-02094 
+-02095                                 /* Clear Enbl_L1Gating bit. */
+-02096                                 pcgcctl.b.enbl_sleep_gating = 1;
+-02097                                 DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32,
+-02098                                                  0);
+-02099 
+-02100                                 dwc_mdelay(5);
+-02101 
+-02102                                 hprt0.d32 = dwc_otg_read_hprt0(core_if);
+-02103                                 hprt0.b.prtres = 1;
+-02104                                 DWC_WRITE_REG32(core_if->host_if->hprt0,
+-02105                                                 hprt0.d32);
+-02106                                 /* This bit will be cleared in wakeup interrupt handle */
+-02107                                 break;
+-02108                         }
+-02109 #endif
+-02110                 case UHF_PORT_POWER:
+-02111                         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
+-02112                                     "ClearPortFeature USB_PORT_FEAT_POWER\n");
+-02113                         hprt0.d32 = dwc_otg_read_hprt0(core_if);
+-02114                         hprt0.b.prtpwr = 0;
+-02115                         DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
+-02116                         break;
+-02117                 case UHF_PORT_INDICATOR:
+-02118                         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
+-02119                                     "ClearPortFeature USB_PORT_FEAT_INDICATOR\n");
+-02120                         /* Port inidicator not supported */
+-02121                         break;
+-02122                 case UHF_C_PORT_CONNECTION:
+-02123                         /* Clears drivers internal connect status change
+-02124                          * flag */
+-02125                         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
+-02126                                     "ClearPortFeature USB_PORT_FEAT_C_CONNECTION\n");
+-02127                         dwc_otg_hcd->flags.b.port_connect_status_change = 0;
+-02128                         break;
+-02129                 case UHF_C_PORT_RESET:
+-02130                         /* Clears the driver's internal Port Reset Change
+-02131                          * flag */
+-02132                         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
+-02133                                     "ClearPortFeature USB_PORT_FEAT_C_RESET\n");
+-02134                         dwc_otg_hcd->flags.b.port_reset_change = 0;
+-02135                         break;
+-02136                 case UHF_C_PORT_ENABLE:
+-02137                         /* Clears the driver's internal Port
+-02138                          * Enable/Disable Change flag */
+-02139                         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
+-02140                                     "ClearPortFeature USB_PORT_FEAT_C_ENABLE\n");
+-02141                         dwc_otg_hcd->flags.b.port_enable_change = 0;
+-02142                         break;
+-02143                 case UHF_C_PORT_SUSPEND:
+-02144                         /* Clears the driver's internal Port Suspend
+-02145                          * Change flag, which is set when resume signaling on
+-02146                          * the host port is complete */
+-02147                         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
+-02148                                     "ClearPortFeature USB_PORT_FEAT_C_SUSPEND\n");
+-02149                         dwc_otg_hcd->flags.b.port_suspend_change = 0;
+-02150                         break;
+-02151 #ifdef CONFIG_USB_DWC_OTG_LPM
+-02152                 case UHF_C_PORT_L1:
+-02153                         dwc_otg_hcd->flags.b.port_l1_change = 0;
+-02154                         break;
+-02155 #endif
+-02156                 case UHF_C_PORT_OVER_CURRENT:
+-02157                         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
+-02158                                     "ClearPortFeature USB_PORT_FEAT_C_OVER_CURRENT\n");
+-02159                         dwc_otg_hcd->flags.b.port_over_current_change = 0;
+-02160                         break;
+-02161                 default:
+-02162                         retval = -DWC_E_INVALID;
+-02163                         DWC_ERROR("DWC OTG HCD - "
+-02164                                   "ClearPortFeature request %xh "
+-02165                                   "unknown or unsupported\n", wValue);
+-02166                 }
+-02167                 break;
+-02168         case UCR_GET_HUB_DESCRIPTOR:
+-02169                 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
+-02170                             "GetHubDescriptor\n");
+-02171                 hub_desc = (usb_hub_descriptor_t *) buf;
+-02172                 hub_desc->bDescLength = 9;
+-02173                 hub_desc->bDescriptorType = 0x29;
+-02174                 hub_desc->bNbrPorts = 1;
+-02175                 USETW(hub_desc->wHubCharacteristics, 0x08);
+-02176                 hub_desc->bPwrOn2PwrGood = 1;
+-02177                 hub_desc->bHubContrCurrent = 0;
+-02178                 hub_desc->DeviceRemovable[0] = 0;
+-02179                 hub_desc->DeviceRemovable[1] = 0xff;
+-02180                 break;
+-02181         case UCR_GET_HUB_STATUS:
+-02182                 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
+-02183                             "GetHubStatus\n");
+-02184                 DWC_MEMSET(buf, 0, 4);
+-02185                 break;
+-02186         case UCR_GET_PORT_STATUS:
+-02187                 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
+-02188                             "GetPortStatus wIndex = 0x%04x FLAGS=0x%08x\n",
+-02189                             wIndex, dwc_otg_hcd->flags.d32);
+-02190                 if (!wIndex || wIndex > 1)
+-02191                         goto error;
+-02192 
+-02193                 port_status = 0;
+-02194 
+-02195                 if (dwc_otg_hcd->flags.b.port_connect_status_change)
+-02196                         port_status |= (1 << UHF_C_PORT_CONNECTION);
+-02197 
+-02198                 if (dwc_otg_hcd->flags.b.port_enable_change)
+-02199                         port_status |= (1 << UHF_C_PORT_ENABLE);
+-02200 
+-02201                 if (dwc_otg_hcd->flags.b.port_suspend_change)
+-02202                         port_status |= (1 << UHF_C_PORT_SUSPEND);
+-02203 
+-02204                 if (dwc_otg_hcd->flags.b.port_l1_change)
+-02205                         port_status |= (1 << UHF_C_PORT_L1);
+-02206 
+-02207                 if (dwc_otg_hcd->flags.b.port_reset_change) {
+-02208                         port_status |= (1 << UHF_C_PORT_RESET);
+-02209                 }
+-02210 
+-02211                 if (dwc_otg_hcd->flags.b.port_over_current_change) {
+-02212                         DWC_WARN("Overcurrent change detected\n");
+-02213                         port_status |= (1 << UHF_C_PORT_OVER_CURRENT);
+-02214                 }
+-02215 
+-02216                 if (!dwc_otg_hcd->flags.b.port_connect_status) {
+-02217                         /*
+-02218                          * The port is disconnected, which means the core is
+-02219                          * either in device mode or it soon will be. Just
+-02220                          * return 0's for the remainder of the port status
+-02221                          * since the port register can't be read if the core
+-02222                          * is in device mode.
+-02223                          */
+-02224                         *((__le32 *) buf) = dwc_cpu_to_le32(&port_status);
+-02225                         break;
+-02226                 }
+-02227 
+-02228                 hprt0.d32 = DWC_READ_REG32(core_if->host_if->hprt0);
+-02229                 DWC_DEBUGPL(DBG_HCDV, "  HPRT0: 0x%08x\n", hprt0.d32);
+-02230 
+-02231                 if (hprt0.b.prtconnsts)
+-02232                         port_status |= (1 << UHF_PORT_CONNECTION);
+-02233 
+-02234                 if (hprt0.b.prtena)
+-02235                         port_status |= (1 << UHF_PORT_ENABLE);
+-02236 
+-02237                 if (hprt0.b.prtsusp)
+-02238                         port_status |= (1 << UHF_PORT_SUSPEND);
+-02239 
+-02240                 if (hprt0.b.prtovrcurract)
+-02241                         port_status |= (1 << UHF_PORT_OVER_CURRENT);
+-02242 
+-02243                 if (hprt0.b.prtrst)
+-02244                         port_status |= (1 << UHF_PORT_RESET);
+-02245 
+-02246                 if (hprt0.b.prtpwr)
+-02247                         port_status |= (1 << UHF_PORT_POWER);
+-02248 
+-02249                 if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_HIGH_SPEED)
+-02250                         port_status |= (1 << UHF_PORT_HIGH_SPEED);
+-02251                 else if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_LOW_SPEED)
+-02252                         port_status |= (1 << UHF_PORT_LOW_SPEED);
+-02253 
+-02254                 if (hprt0.b.prttstctl)
+-02255                         port_status |= (1 << UHF_PORT_TEST);
+-02256                 if (dwc_otg_get_lpm_portsleepstatus(dwc_otg_hcd->core_if)) {
+-02257                         port_status |= (1 << UHF_PORT_L1);
+-02258                 }
+-02259                 /*
+-02260                    For Synopsys HW emulation of Power down wkup_control asserts the 
+-02261                    hreset_n and prst_n on suspned. This causes the HPRT0 to be zero. 
+-02262                    We intentionally tell the software that port is in L2Suspend state. 
+-02263                    Only for STE.
+-02264                 */
+-02265                 if ((core_if->power_down == 2)
+-02266                     && (core_if->hibernation_suspend == 1)) {
+-02267                         port_status |= (1 << UHF_PORT_SUSPEND);
+-02268                 }
+-02269                 /* USB_PORT_FEAT_INDICATOR unsupported always 0 */
+-02270 
+-02271                 *((__le32 *) buf) = dwc_cpu_to_le32(&port_status);
+-02272 
+-02273                 break;
+-02274         case UCR_SET_HUB_FEATURE:
+-02275                 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
+-02276                             "SetHubFeature\n");
+-02277                 /* No HUB features supported */
+-02278                 break;
+-02279         case UCR_SET_PORT_FEATURE:
+-02280                 if (wValue != UHF_PORT_TEST && (!wIndex || wIndex > 1))
+-02281                         goto error;
+-02282 
+-02283                 if (!dwc_otg_hcd->flags.b.port_connect_status) {
+-02284                         /*
+-02285                          * The port is disconnected, which means the core is
+-02286                          * either in device mode or it soon will be. Just
+-02287                          * return without doing anything since the port
+-02288                          * register can't be written if the core is in device
+-02289                          * mode.
+-02290                          */
+-02291                         break;
+-02292                 }
+-02293 
+-02294                 switch (wValue) {
+-02295                 case UHF_PORT_SUSPEND:
+-02296                         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
+-02297                                     "SetPortFeature - USB_PORT_FEAT_SUSPEND\n");
+-02298                         if (dwc_otg_hcd_otg_port(dwc_otg_hcd) != wIndex) {
+-02299                                 goto error;
+-02300                         }
+-02301                         if (core_if->power_down == 2) {
+-02302                                 int timeout = 300;
+-02303                                 dwc_irqflags_t flags;
+-02304                                 pcgcctl_data_t pcgcctl = {.d32 = 0 };
+-02305                                 gpwrdn_data_t gpwrdn = {.d32 = 0 };
+-02306                                 gusbcfg_data_t gusbcfg = {.d32 = 0 };
+-02307 #ifdef DWC_DEV_SRPCAP
+-02308                                 int32_t otg_cap_param = core_if->core_params->otg_cap;
+-02309 #endif
+-02310                                 DWC_PRINTF("Preparing for complete power-off\n");
+-02311 
+-02312                                 /* Save registers before hibernation */
+-02313                                 dwc_otg_save_global_regs(core_if);
+-02314                                 dwc_otg_save_host_regs(core_if);
+-02315 
+-02316                                 hprt0.d32 = dwc_otg_read_hprt0(core_if);
+-02317                                 hprt0.b.prtsusp = 1;
+-02318                                 hprt0.b.prtena = 0;
+-02319                                 DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
+-02320                                 /* Spin hprt0.b.prtsusp to became 1 */
+-02321                                 do {
+-02322                                         hprt0.d32 = dwc_otg_read_hprt0(core_if);
+-02323                                         if (hprt0.b.prtsusp) {
+-02324                                                 break;
+-02325                                         }
+-02326                                         dwc_mdelay(1);
+-02327                                 } while (--timeout);
+-02328                                 if (!timeout) {
+-02329                                         DWC_WARN("Suspend wasn't genereted\n");
+-02330                                 }
+-02331                                 dwc_udelay(10);
+-02332 
+-02333                                 /*
+-02334                                  * We need to disable interrupts to prevent servicing of any IRQ
+-02335                                  * during going to hibernation
+-02336                                  */
+-02337                                 DWC_SPINLOCK_IRQSAVE(dwc_otg_hcd->lock, &flags);
+-02338                                 core_if->lx_state = DWC_OTG_L2;
+-02339 #ifdef DWC_DEV_SRPCAP
+-02340                                 hprt0.d32 = dwc_otg_read_hprt0(core_if);
+-02341                                 hprt0.b.prtpwr = 0;
+-02342                                 hprt0.b.prtena = 0;
+-02343                                 DWC_WRITE_REG32(core_if->host_if->hprt0,
+-02344                                                 hprt0.d32);
+-02345 #endif
+-02346                                 gusbcfg.d32 =
+-02347                                     DWC_READ_REG32(&core_if->core_global_regs->
+-02348                                                    gusbcfg);
+-02349                                 if (gusbcfg.b.ulpi_utmi_sel == 1) {
+-02350                                         /* ULPI interface */
+-02351                                         /* Suspend the Phy Clock */
+-02352                                         pcgcctl.d32 = 0;
+-02353                                         pcgcctl.b.stoppclk = 1;
+-02354                                         DWC_MODIFY_REG32(core_if->pcgcctl, 0,
+-02355                                                          pcgcctl.d32);
+-02356                                         dwc_udelay(10);
+-02357                                         gpwrdn.b.pmuactv = 1;
+-02358                                         DWC_MODIFY_REG32(&core_if->
+-02359                                                          core_global_regs->
+-02360                                                          gpwrdn, 0, gpwrdn.d32);
+-02361                                 } else {
+-02362                                         /* UTMI+ Interface */
+-02363                                         gpwrdn.b.pmuactv = 1;
+-02364                                         DWC_MODIFY_REG32(&core_if->
+-02365                                                          core_global_regs->
+-02366                                                          gpwrdn, 0, gpwrdn.d32);
+-02367                                         dwc_udelay(10);
+-02368                                         pcgcctl.b.stoppclk = 1;
+-02369                                         DWC_MODIFY_REG32(core_if->pcgcctl, 0, pcgcctl.d32);
+-02370                                         dwc_udelay(10);
+-02371                                 }
+-02372 #ifdef DWC_DEV_SRPCAP                           
+-02373                                 gpwrdn.d32 = 0;
+-02374                                 gpwrdn.b.dis_vbus = 1;
+-02375                                 DWC_MODIFY_REG32(&core_if->core_global_regs->
+-02376                                                  gpwrdn, 0, gpwrdn.d32);
+-02377 #endif
+-02378                                 gpwrdn.d32 = 0;
+-02379                                 gpwrdn.b.pmuintsel = 1;
+-02380                                 DWC_MODIFY_REG32(&core_if->core_global_regs->
+-02381                                                  gpwrdn, 0, gpwrdn.d32);
+-02382                                 dwc_udelay(10);
+-02383 
+-02384                                 gpwrdn.d32 = 0;
+-02385 #ifdef DWC_DEV_SRPCAP
+-02386                                 gpwrdn.b.srp_det_msk = 1;
+-02387 #endif
+-02388                                 gpwrdn.b.disconn_det_msk = 1;
+-02389                                 gpwrdn.b.lnstchng_msk = 1;
+-02390                                 gpwrdn.b.sts_chngint_msk = 1;
+-02391                                 DWC_MODIFY_REG32(&core_if->core_global_regs->
+-02392                                                  gpwrdn, 0, gpwrdn.d32);
+-02393                                 dwc_udelay(10);
+-02394 
+-02395                                 /* Enable Power Down Clamp and all interrupts in GPWRDN */
+-02396                                 gpwrdn.d32 = 0;
+-02397                                 gpwrdn.b.pwrdnclmp = 1;
+-02398                                 DWC_MODIFY_REG32(&core_if->core_global_regs->
+-02399                                                  gpwrdn, 0, gpwrdn.d32);
+-02400                                 dwc_udelay(10);
+-02401 
+-02402                                 /* Switch off VDD */
+-02403                                 gpwrdn.d32 = 0;
+-02404                                 gpwrdn.b.pwrdnswtch = 1;
+-02405                                 DWC_MODIFY_REG32(&core_if->core_global_regs->
+-02406                                                  gpwrdn, 0, gpwrdn.d32);
+-02407 
+-02408 #ifdef DWC_DEV_SRPCAP
+-02409                                 if (otg_cap_param == DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE)
+-02410                                 {
+-02411                                         core_if->pwron_timer_started = 1;
+-02412                                         DWC_TIMER_SCHEDULE(core_if->pwron_timer, 6000 /* 6 secs */ );
+-02413                                 }
+-02414 #endif
+-02415                                 /* Save gpwrdn register for further usage if stschng interrupt */
+-02416                                 core_if->gr_backup->gpwrdn_local =
+-02417                                                 DWC_READ_REG32(&core_if->core_global_regs->gpwrdn);
+-02418 
+-02419                                 /* Set flag to indicate that we are in hibernation */
+-02420                                 core_if->hibernation_suspend = 1;
+-02421                                 DWC_SPINUNLOCK_IRQRESTORE(dwc_otg_hcd->lock,flags);
+-02422 
+-02423                                 DWC_PRINTF("Host hibernation completed\n");
+-02424                                 // Exit from case statement
+-02425                                 break;
+-02426 
+-02427                         }
+-02428                         if (dwc_otg_hcd_otg_port(dwc_otg_hcd) == wIndex &&
+-02429                             dwc_otg_hcd->fops->get_b_hnp_enable(dwc_otg_hcd)) {
+-02430                                 gotgctl_data_t gotgctl = {.d32 = 0 };
+-02431                                 gotgctl.b.hstsethnpen = 1;
+-02432                                 DWC_MODIFY_REG32(&core_if->core_global_regs->
+-02433                                                  gotgctl, 0, gotgctl.d32);
+-02434                                 core_if->op_state = A_SUSPEND;
+-02435                         }
+-02436                         hprt0.d32 = dwc_otg_read_hprt0(core_if);
+-02437                         hprt0.b.prtsusp = 1;
+-02438                         DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
+-02439                         {
+-02440                                 dwc_irqflags_t flags;
+-02441                                 /* Update lx_state */
+-02442                                 DWC_SPINLOCK_IRQSAVE(dwc_otg_hcd->lock, &flags);
+-02443                                 core_if->lx_state = DWC_OTG_L2;
+-02444                                 DWC_SPINUNLOCK_IRQRESTORE(dwc_otg_hcd->lock, flags);
+-02445                         }
+-02446                         /* Suspend the Phy Clock */
+-02447                         {
+-02448                                 pcgcctl_data_t pcgcctl = {.d32 = 0 };
+-02449                                 pcgcctl.b.stoppclk = 1;
+-02450                                 DWC_MODIFY_REG32(core_if->pcgcctl, 0,
+-02451                                                  pcgcctl.d32);
+-02452                                 dwc_udelay(10);
+-02453                         }
+-02454 
+-02455                         /* For HNP the bus must be suspended for at least 200ms. */
+-02456                         if (dwc_otg_hcd->fops->get_b_hnp_enable(dwc_otg_hcd)) {
+-02457                                 pcgcctl_data_t pcgcctl = {.d32 = 0 };
+-02458                                 pcgcctl.b.stoppclk = 1;
+-02459                 DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32, 0);
+-02460                                 dwc_mdelay(200);
+-02461                         }
+-02462 
+-02464 #if 0 //vahrama !!!!!!!!!!!!!!!!!!
+-02465                         if (core_if->adp_enable) {
+-02466                                 gotgctl_data_t gotgctl = {.d32 = 0 };
+-02467                                 gpwrdn_data_t gpwrdn;
+-02468 
+-02469                                 while (gotgctl.b.asesvld == 1) {
+-02470                                         gotgctl.d32 =
+-02471                                             DWC_READ_REG32(&core_if->
+-02472                                                            core_global_regs->
+-02473                                                            gotgctl);
+-02474                                         dwc_mdelay(100);
+-02475                                 }
+-02476 
+-02477                                 /* Enable Power Down Logic */
+-02478                                 gpwrdn.d32 = 0;
+-02479                                 gpwrdn.b.pmuactv = 1;
+-02480                                 DWC_MODIFY_REG32(&core_if->core_global_regs->
+-02481                                                  gpwrdn, 0, gpwrdn.d32);
+-02482 
+-02483                                 /* Unmask SRP detected interrupt from Power Down Logic */
+-02484                                 gpwrdn.d32 = 0;
+-02485                                 gpwrdn.b.srp_det_msk = 1;
+-02486                                 DWC_MODIFY_REG32(&core_if->core_global_regs->
+-02487                                                  gpwrdn, 0, gpwrdn.d32);
+-02488 
+-02489                                 dwc_otg_adp_probe_start(core_if);
+-02490                         }
+-02491 #endif
+-02492                         break;
+-02493                 case UHF_PORT_POWER:
+-02494                         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
+-02495                                     "SetPortFeature - USB_PORT_FEAT_POWER\n");
+-02496                         hprt0.d32 = dwc_otg_read_hprt0(core_if);
+-02497                         hprt0.b.prtpwr = 1;
+-02498                         DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
+-02499                         break;
+-02500                 case UHF_PORT_RESET:
+-02501                         if ((core_if->power_down == 2)
+-02502                             && (core_if->hibernation_suspend == 1)) {
+-02503                                 /* If we are going to exit from Hibernated
+-02504                                  * state via USB RESET.
+-02505                                  */
+-02506                                 dwc_otg_host_hibernation_restore(core_if, 0, 1);
+-02507                         } else {
+-02508                                 hprt0.d32 = dwc_otg_read_hprt0(core_if);
+-02509 
+-02510                                 DWC_DEBUGPL(DBG_HCD,
+-02511                                             "DWC OTG HCD HUB CONTROL - "
+-02512                                             "SetPortFeature - USB_PORT_FEAT_RESET\n");
+-02513                                 {
+-02514                                         pcgcctl_data_t pcgcctl = {.d32 = 0 };
+-02515                                         pcgcctl.b.enbl_sleep_gating = 1;
+-02516                                         pcgcctl.b.stoppclk = 1;
+-02517                                         DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32, 0);
+-02518                                         DWC_WRITE_REG32(core_if->pcgcctl, 0);
+-02519                                 }
+-02520 #ifdef CONFIG_USB_DWC_OTG_LPM
+-02521                                 {
+-02522                                         glpmcfg_data_t lpmcfg;
+-02523                                         lpmcfg.d32 =
+-02524                                                 DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
+-02525                                         if (lpmcfg.b.prt_sleep_sts) {
+-02526                                                 lpmcfg.b.en_utmi_sleep = 0;
+-02527                                                 lpmcfg.b.hird_thres &= (~(1 << 4));
+-02528                                                 DWC_WRITE_REG32
+-02529                                                     (&core_if->core_global_regs->glpmcfg,
+-02530                                                      lpmcfg.d32);
+-02531                                                 dwc_mdelay(1);
+-02532                                         }
+-02533                                 }
+-02534 #endif
+-02535                                 hprt0.d32 = dwc_otg_read_hprt0(core_if);
+-02536                                 /* Clear suspend bit if resetting from suspended state. */
+-02537                                 hprt0.b.prtsusp = 0;
+-02538                                 /* When B-Host the Port reset bit is set in
+-02539                                  * the Start HCD Callback function, so that
+-02540                                  * the reset is started within 1ms of the HNP
+-02541                                  * success interrupt. */
+-02542                                 if (!dwc_otg_hcd_is_b_host(dwc_otg_hcd)) {
+-02543                                         hprt0.b.prtpwr = 1;
+-02544                                         hprt0.b.prtrst = 1;
+-02545                                         DWC_PRINTF("Indeed it is in host mode hprt0 = %08x\n",hprt0.d32);
+-02546                                         DWC_WRITE_REG32(core_if->host_if->hprt0,
+-02547                                                         hprt0.d32);
+-02548                                 }
+-02549                                 /* Clear reset bit in 10ms (FS/LS) or 50ms (HS) */
+-02550                                 dwc_mdelay(60);
+-02551                                 hprt0.b.prtrst = 0;
+-02552                                 DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
+-02553                                 core_if->lx_state = DWC_OTG_L0; /* Now back to the on state */
+-02554                         }
+-02555                         break;
+-02556 #ifdef DWC_HS_ELECT_TST
+-02557                 case UHF_PORT_TEST:
+-02558                         {
+-02559                                 uint32_t t;
+-02560                                 gintmsk_data_t gintmsk;
+-02561 
+-02562                                 t = (wIndex >> 8);      /* MSB wIndex USB */
+-02563                                 DWC_DEBUGPL(DBG_HCD,
+-02564                                             "DWC OTG HCD HUB CONTROL - "
+-02565                                             "SetPortFeature - USB_PORT_FEAT_TEST %d\n",
+-02566                                             t);
+-02567                                 DWC_WARN("USB_PORT_FEAT_TEST %d\n", t);
+-02568                                 if (t < 6) {
+-02569                                         hprt0.d32 = dwc_otg_read_hprt0(core_if);
+-02570                                         hprt0.b.prttstctl = t;
+-02571                                         DWC_WRITE_REG32(core_if->host_if->hprt0,
+-02572                                                         hprt0.d32);
+-02573                                 } else {
+-02574                                         /* Setup global vars with reg addresses (quick and
+-02575                                          * dirty hack, should be cleaned up)
+-02576                                          */
+-02577                                         global_regs = core_if->core_global_regs;
+-02578                                         hc_global_regs =
+-02579                                             core_if->host_if->host_global_regs;
+-02580                                         hc_regs =
+-02581                                             (dwc_otg_hc_regs_t *) ((char *)
+-02582                                                                    global_regs +
+-02583                                                                    0x500);
+-02584                                         data_fifo =
+-02585                                             (uint32_t *) ((char *)global_regs +
+-02586                                                           0x1000);
+-02587 
+-02588                                         if (t == 6) {   /* HS_HOST_PORT_SUSPEND_RESUME */
+-02589                                                 /* Save current interrupt mask */
+-02590                                                 gintmsk.d32 =
+-02591                                                     DWC_READ_REG32
+-02592                                                     (&global_regs->gintmsk);
+-02593 
+-02594                                                 /* Disable all interrupts while we muck with
+-02595                                                  * the hardware directly
+-02596                                                  */
+-02597                                                 DWC_WRITE_REG32(&global_regs->gintmsk, 0);
+-02598 
+-02599                                                 /* 15 second delay per the test spec */
+-02600                                                 dwc_mdelay(15000);
+-02601 
+-02602                                                 /* Drive suspend on the root port */
+-02603                                                 hprt0.d32 =
+-02604                                                     dwc_otg_read_hprt0(core_if);
+-02605                                                 hprt0.b.prtsusp = 1;
+-02606                                                 hprt0.b.prtres = 0;
+-02607                                                 DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
+-02608 
+-02609                                                 /* 15 second delay per the test spec */
+-02610                                                 dwc_mdelay(15000);
+-02611 
+-02612                                                 /* Drive resume on the root port */
+-02613                                                 hprt0.d32 =
+-02614                                                     dwc_otg_read_hprt0(core_if);
+-02615                                                 hprt0.b.prtsusp = 0;
+-02616                                                 hprt0.b.prtres = 1;
+-02617                                                 DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
+-02618                                                 dwc_mdelay(100);
+-02619 
+-02620                                                 /* Clear the resume bit */
+-02621                                                 hprt0.b.prtres = 0;
+-02622                                                 DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
+-02623 
+-02624                                                 /* Restore interrupts */
+-02625                                                 DWC_WRITE_REG32(&global_regs->gintmsk, gintmsk.d32);
+-02626                                         } else if (t == 7) {    /* SINGLE_STEP_GET_DEVICE_DESCRIPTOR setup */
+-02627                                                 /* Save current interrupt mask */
+-02628                                                 gintmsk.d32 =
+-02629                                                     DWC_READ_REG32
+-02630                                                     (&global_regs->gintmsk);
+-02631 
+-02632                                                 /* Disable all interrupts while we muck with
+-02633                                                  * the hardware directly
+-02634                                                  */
+-02635                                                 DWC_WRITE_REG32(&global_regs->gintmsk, 0);
+-02636 
+-02637                                                 /* 15 second delay per the test spec */
+-02638                                                 dwc_mdelay(15000);
+-02639 
+-02640                                                 /* Send the Setup packet */
+-02641                                                 do_setup();
+-02642 
+-02643                                                 /* 15 second delay so nothing else happens for awhile */
+-02644                                                 dwc_mdelay(15000);
+-02645 
+-02646                                                 /* Restore interrupts */
+-02647                                                 DWC_WRITE_REG32(&global_regs->gintmsk, gintmsk.d32);
+-02648                                         } else if (t == 8) {    /* SINGLE_STEP_GET_DEVICE_DESCRIPTOR execute */
+-02649                                                 /* Save current interrupt mask */
+-02650                                                 gintmsk.d32 =
+-02651                                                     DWC_READ_REG32
+-02652                                                     (&global_regs->gintmsk);
+-02653 
+-02654                                                 /* Disable all interrupts while we muck with
+-02655                                                  * the hardware directly
+-02656                                                  */
+-02657                                                 DWC_WRITE_REG32(&global_regs->gintmsk, 0);
+-02658 
+-02659                                                 /* Send the Setup packet */
+-02660                                                 do_setup();
+-02661 
+-02662                                                 /* 15 second delay so nothing else happens for awhile */
+-02663                                                 dwc_mdelay(15000);
+-02664 
+-02665                                                 /* Send the In and Ack packets */
+-02666                                                 do_in_ack();
+-02667 
+-02668                                                 /* 15 second delay so nothing else happens for awhile */
+-02669                                                 dwc_mdelay(15000);
+-02670 
+-02671                                                 /* Restore interrupts */
+-02672                                                 DWC_WRITE_REG32(&global_regs->gintmsk, gintmsk.d32);
+-02673                                         }
+-02674                                 }
+-02675                                 break;
+-02676                         }
+-02677 #endif /* DWC_HS_ELECT_TST */
+-02678 
+-02679                 case UHF_PORT_INDICATOR:
+-02680                         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
+-02681                                     "SetPortFeature - USB_PORT_FEAT_INDICATOR\n");
+-02682                         /* Not supported */
+-02683                         break;
+-02684                 default:
+-02685                         retval = -DWC_E_INVALID;
+-02686                         DWC_ERROR("DWC OTG HCD - "
+-02687                                   "SetPortFeature request %xh "
+-02688                                   "unknown or unsupported\n", wValue);
+-02689                         break;
+-02690                 }
+-02691                 break;
+-02692 #ifdef CONFIG_USB_DWC_OTG_LPM
+-02693         case UCR_SET_AND_TEST_PORT_FEATURE:
+-02694                 if (wValue != UHF_PORT_L1) {
+-02695                         goto error;
+-02696                 }
+-02697                 {
+-02698                         int portnum, hird, devaddr, remwake;
+-02699                         glpmcfg_data_t lpmcfg;
+-02700                         uint32_t time_usecs;
+-02701                         gintsts_data_t gintsts;
+-02702                         gintmsk_data_t gintmsk;
+-02703 
+-02704                         if (!dwc_otg_get_param_lpm_enable(core_if)) {
+-02705                                 goto error;
+-02706                         }
+-02707                         if (wValue != UHF_PORT_L1 || wLength != 1) {
+-02708                                 goto error;
+-02709                         }
+-02710                         /* Check if the port currently is in SLEEP state */
+-02711                         lpmcfg.d32 =
+-02712                             DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
+-02713                         if (lpmcfg.b.prt_sleep_sts) {
+-02714                                 DWC_INFO("Port is already in sleep mode\n");
+-02715                                 buf[0] = 0;     /* Return success */
+-02716                                 break;
+-02717                         }
+-02718 
+-02719                         portnum = wIndex & 0xf;
+-02720                         hird = (wIndex >> 4) & 0xf;
+-02721                         devaddr = (wIndex >> 8) & 0x7f;
+-02722                         remwake = (wIndex >> 15);
+-02723 
+-02724                         if (portnum != 1) {
+-02725                                 retval = -DWC_E_INVALID;
+-02726                                 DWC_WARN
+-02727                                     ("Wrong port number(%d) in SetandTestPortFeature request\n",
+-02728                                      portnum);
+-02729                                 break;
+-02730                         }
+-02731 
+-02732                         DWC_PRINTF
+-02733                             ("SetandTestPortFeature request: portnum = %d, hird = %d, devaddr = %d, rewake = %d\n",
+-02734                              portnum, hird, devaddr, remwake);
+-02735                         /* Disable LPM interrupt */
+-02736                         gintmsk.d32 = 0;
+-02737                         gintmsk.b.lpmtranrcvd = 1;
+-02738                         DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk,
+-02739                                          gintmsk.d32, 0);
+-02740 
+-02741                         if (dwc_otg_hcd_send_lpm
+-02742                             (dwc_otg_hcd, devaddr, hird, remwake)) {
+-02743                                 retval = -DWC_E_INVALID;
+-02744                                 break;
+-02745                         }
+-02746 
+-02747                         time_usecs = 10 * (lpmcfg.b.retry_count + 1);
+-02748                         /* We will consider timeout if time_usecs microseconds pass,
+-02749                          * and we don't receive LPM transaction status.
+-02750                          * After receiving non-error responce(ACK/NYET/STALL) from device,
+-02751                          *  core will set lpmtranrcvd bit.
+-02752                          */
+-02753                         do {
+-02754                                 gintsts.d32 =
+-02755                                     DWC_READ_REG32(&core_if->core_global_regs->gintsts);
+-02756                                 if (gintsts.b.lpmtranrcvd) {
+-02757                                         break;
+-02758                                 }
+-02759                                 dwc_udelay(1);
+-02760                         } while (--time_usecs);
+-02761                         /* lpm_int bit will be cleared in LPM interrupt handler */
+-02762 
+-02763                         /* Now fill status
+-02764                          * 0x00 - Success
+-02765                          * 0x10 - NYET
+-02766                          * 0x11 - Timeout
+-02767                          */
+-02768                         if (!gintsts.b.lpmtranrcvd) {
+-02769                                 buf[0] = 0x3;   /* Completion code is Timeout */
+-02770                                 dwc_otg_hcd_free_hc_from_lpm(dwc_otg_hcd);
+-02771                         } else {
+-02772                                 lpmcfg.d32 =
+-02773                                     DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
+-02774                                 if (lpmcfg.b.lpm_resp == 0x3) {
+-02775                                         /* ACK responce from the device */
+-02776                                         buf[0] = 0x00;  /* Success */
+-02777                                 } else if (lpmcfg.b.lpm_resp == 0x2) {
+-02778                                         /* NYET responce from the device */
+-02779                                         buf[0] = 0x2;
+-02780                                 } else {
+-02781                                         /* Otherwise responce with Timeout */
+-02782                                         buf[0] = 0x3;
+-02783                                 }
+-02784                         }
+-02785                         DWC_PRINTF("Device responce to LPM trans is %x\n",
+-02786                                    lpmcfg.b.lpm_resp);
+-02787                         DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, 0,
+-02788                                          gintmsk.d32);
+-02789 
+-02790                         break;
+-02791                 }
+-02792 #endif /* CONFIG_USB_DWC_OTG_LPM */
+-02793         default:
+-02794 error:
+-02795                 retval = -DWC_E_INVALID;
+-02796                 DWC_WARN("DWC OTG HCD - "
+-02797                          "Unknown hub control request type or invalid typeReq: %xh wIndex: %xh wValue: %xh\n",
+-02798                          typeReq, wIndex, wValue);
+-02799                 break;
+-02800         }
+-02801 
+-02802         return retval;
+-02803 }
+-02804 
+-02805 #ifdef CONFIG_USB_DWC_OTG_LPM
+-02806 
+-02807 int dwc_otg_hcd_get_hc_for_lpm_tran(dwc_otg_hcd_t * hcd, uint8_t devaddr)
+-02808 {
+-02809         dwc_otg_core_if_t *core_if = hcd->core_if;
+-02810         dwc_hc_t *hc;
+-02811         hcchar_data_t hcchar;
+-02812         gintmsk_data_t gintmsk = {.d32 = 0 };
+-02813 
+-02814         if (DWC_CIRCLEQ_EMPTY(&hcd->free_hc_list)) {
+-02815                 DWC_PRINTF("No free channel to select for LPM transaction\n");
+-02816                 return -1;
+-02817         }
+-02818 
+-02819         hc = DWC_CIRCLEQ_FIRST(&hcd->free_hc_list);
+-02820 
+-02821         /* Mask host channel interrupts. */
+-02822         gintmsk.b.hcintr = 1;
+-02823         DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, gintmsk.d32, 0);
+-02824 
+-02825         /* Fill fields that core needs for LPM transaction */
+-02826         hcchar.b.devaddr = devaddr;
+-02827         hcchar.b.epnum = 0;
+-02828         hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
+-02829         hcchar.b.mps = 64;
+-02830         hcchar.b.lspddev = (hc->speed == DWC_OTG_EP_SPEED_LOW);
+-02831         hcchar.b.epdir = 0;     /* OUT */
+-02832         DWC_WRITE_REG32(&core_if->host_if->hc_regs[hc->hc_num]->hcchar,
+-02833                         hcchar.d32);
+-02834 
+-02835         /* Remove the host channel from the free list. */
+-02836         DWC_CIRCLEQ_REMOVE_INIT(&hcd->free_hc_list, hc, hc_list_entry);
+-02837 
+-02838         DWC_PRINTF("hcnum = %d devaddr = %d\n", hc->hc_num, devaddr);
+-02839 
+-02840         return hc->hc_num;
+-02841 }
+-02842 
+-02844 void dwc_otg_hcd_free_hc_from_lpm(dwc_otg_hcd_t * hcd)
+-02845 {
+-02846         dwc_hc_t *hc;
+-02847         glpmcfg_data_t lpmcfg;
+-02848         uint8_t hc_num;
+-02849 
+-02850         lpmcfg.d32 = DWC_READ_REG32(&hcd->core_if->core_global_regs->glpmcfg);
+-02851         hc_num = lpmcfg.b.lpm_chan_index;
+-02852 
+-02853         hc = hcd->hc_ptr_array[hc_num];
+-02854 
+-02855         DWC_PRINTF("Freeing channel %d after LPM\n", hc_num);
+-02856         /* Return host channel to free list */
+-02857         DWC_CIRCLEQ_INSERT_TAIL(&hcd->free_hc_list, hc, hc_list_entry);
+-02858 }
+-02859 
+-02860 int dwc_otg_hcd_send_lpm(dwc_otg_hcd_t * hcd, uint8_t devaddr, uint8_t hird,
+-02861                          uint8_t bRemoteWake)
+-02862 {
+-02863         glpmcfg_data_t lpmcfg;
+-02864         pcgcctl_data_t pcgcctl = {.d32 = 0 };
+-02865         int channel;
+-02866 
+-02867         channel = dwc_otg_hcd_get_hc_for_lpm_tran(hcd, devaddr);
+-02868         if (channel < 0) {
+-02869                 return channel;
+-02870         }
+-02871 
+-02872         pcgcctl.b.enbl_sleep_gating = 1;
+-02873         DWC_MODIFY_REG32(hcd->core_if->pcgcctl, 0, pcgcctl.d32);
+-02874 
+-02875         /* Read LPM config register */
+-02876         lpmcfg.d32 = DWC_READ_REG32(&hcd->core_if->core_global_regs->glpmcfg);
+-02877 
+-02878         /* Program LPM transaction fields */
+-02879         lpmcfg.b.rem_wkup_en = bRemoteWake;
+-02880         lpmcfg.b.hird = hird;
+-02881         lpmcfg.b.hird_thres = 0x1c;
+-02882         lpmcfg.b.lpm_chan_index = channel;
+-02883         lpmcfg.b.en_utmi_sleep = 1;
+-02884         /* Program LPM config register */
+-02885         DWC_WRITE_REG32(&hcd->core_if->core_global_regs->glpmcfg, lpmcfg.d32);
+-02886 
+-02887         /* Send LPM transaction */
+-02888         lpmcfg.b.send_lpm = 1;
+-02889         DWC_WRITE_REG32(&hcd->core_if->core_global_regs->glpmcfg, lpmcfg.d32);
+-02890 
+-02891         return 0;
+-02892 }
+-02893 
+-02894 #endif /* CONFIG_USB_DWC_OTG_LPM */
+-02895 
+-02896 int dwc_otg_hcd_is_status_changed(dwc_otg_hcd_t * hcd, int port)
+-02897 {
+-02898         int retval;
+-02899 
+-02900         if (port != 1) {
+-02901                 return -DWC_E_INVALID;
+-02902         }
+-02903 
+-02904         retval = (hcd->flags.b.port_connect_status_change ||
+-02905                   hcd->flags.b.port_reset_change ||
+-02906                   hcd->flags.b.port_enable_change ||
+-02907                   hcd->flags.b.port_suspend_change ||
+-02908                   hcd->flags.b.port_over_current_change);
+-02909 #ifdef DEBUG
+-02910         if (retval) {
+-02911                 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB STATUS DATA:"
+-02912                             " Root port status changed\n");
+-02913                 DWC_DEBUGPL(DBG_HCDV, "  port_connect_status_change: %d\n",
+-02914                             hcd->flags.b.port_connect_status_change);
+-02915                 DWC_DEBUGPL(DBG_HCDV, "  port_reset_change: %d\n",
+-02916                             hcd->flags.b.port_reset_change);
+-02917                 DWC_DEBUGPL(DBG_HCDV, "  port_enable_change: %d\n",
+-02918                             hcd->flags.b.port_enable_change);
+-02919                 DWC_DEBUGPL(DBG_HCDV, "  port_suspend_change: %d\n",
+-02920                             hcd->flags.b.port_suspend_change);
+-02921                 DWC_DEBUGPL(DBG_HCDV, "  port_over_current_change: %d\n",
+-02922                             hcd->flags.b.port_over_current_change);
+-02923         }
+-02924 #endif
+-02925         return retval;
+-02926 }
+-02927 
+-02928 int dwc_otg_hcd_get_frame_number(dwc_otg_hcd_t * dwc_otg_hcd)
+-02929 {
+-02930         hfnum_data_t hfnum;
+-02931         hfnum.d32 =
+-02932             DWC_READ_REG32(&dwc_otg_hcd->core_if->host_if->host_global_regs->
+-02933                            hfnum);
+-02934 
+-02935 #ifdef DEBUG_SOF
+-02936         DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD GET FRAME NUMBER %d\n",
+-02937                     hfnum.b.frnum);
+-02938 #endif
+-02939         return hfnum.b.frnum;
+-02940 }
+-02941 
+-02942 int dwc_otg_hcd_start(dwc_otg_hcd_t * hcd,
+-02943                       struct dwc_otg_hcd_function_ops *fops)
+-02944 {
+-02945         int retval = 0;
+-02946 
+-02947         hcd->fops = fops;
+-02948         if (!dwc_otg_is_device_mode(hcd->core_if) && 
+-02949                 (!hcd->core_if->adp_enable || hcd->core_if->adp.adp_started)) {
+-02950                 dwc_otg_hcd_reinit(hcd);
+-02951         } else {
+-02952                 retval = -DWC_E_NO_DEVICE;
+-02953         }
+-02954 
+-02955         return retval;
+-02956 }
+-02957 
+-02958 void *dwc_otg_hcd_get_priv_data(dwc_otg_hcd_t * hcd)
+-02959 {
+-02960         return hcd->priv;
+-02961 }
+-02962 
+-02963 void dwc_otg_hcd_set_priv_data(dwc_otg_hcd_t * hcd, void *priv_data)
+-02964 {
+-02965         hcd->priv = priv_data;
+-02966 }
+-02967 
+-02968 uint32_t dwc_otg_hcd_otg_port(dwc_otg_hcd_t * hcd)
+-02969 {
+-02970         return hcd->otg_port;
+-02971 }
+-02972 
+-02973 uint32_t dwc_otg_hcd_is_b_host(dwc_otg_hcd_t * hcd)
+-02974 {
+-02975         uint32_t is_b_host;
+-02976         if (hcd->core_if->op_state == B_HOST) {
+-02977                 is_b_host = 1;
+-02978         } else {
+-02979                 is_b_host = 0;
+-02980         }
+-02981 
+-02982         return is_b_host;
+-02983 }
+-02984 
+-02985 dwc_otg_hcd_urb_t *dwc_otg_hcd_urb_alloc(dwc_otg_hcd_t * hcd,
+-02986                                          int iso_desc_count, int atomic_alloc)
+-02987 {
+-02988         dwc_otg_hcd_urb_t *dwc_otg_urb;
+-02989         uint32_t size;
+-02990 
+-02991         size =
+-02992             sizeof(*dwc_otg_urb) +
+-02993             iso_desc_count * sizeof(struct dwc_otg_hcd_iso_packet_desc);
+-02994         if (atomic_alloc)
+-02995                 dwc_otg_urb = DWC_ALLOC_ATOMIC(size);
+-02996         else
+-02997                 dwc_otg_urb = DWC_ALLOC(size);
+-02998 
+-02999         dwc_otg_urb->packet_count = iso_desc_count;
+-03000 
+-03001         return dwc_otg_urb;
+-03002 }
+-03003 
+-03004 void dwc_otg_hcd_urb_set_pipeinfo(dwc_otg_hcd_urb_t * dwc_otg_urb,
+-03005                                   uint8_t dev_addr, uint8_t ep_num,
+-03006                                   uint8_t ep_type, uint8_t ep_dir, uint16_t mps)
+-03007 {
+-03008         dwc_otg_hcd_fill_pipe(&dwc_otg_urb->pipe_info, dev_addr, ep_num,
+-03009                               ep_type, ep_dir, mps);
+-03010 #if 0
+-03011         DWC_PRINTF
+-03012             ("addr = %d, ep_num = %d, ep_dir = 0x%x, ep_type = 0x%x, mps = %d\n",
+-03013              dev_addr, ep_num, ep_dir, ep_type, mps);
+-03014 #endif
+-03015 }
+-03016 
+-03017 void dwc_otg_hcd_urb_set_params(dwc_otg_hcd_urb_t * dwc_otg_urb,
+-03018                                 void *urb_handle, void *buf, dwc_dma_t dma,
+-03019                                 uint32_t buflen, void *setup_packet,
+-03020                                 dwc_dma_t setup_dma, uint32_t flags,
+-03021                                 uint16_t interval)
+-03022 {
+-03023         dwc_otg_urb->priv = urb_handle;
+-03024         dwc_otg_urb->buf = buf;
+-03025         dwc_otg_urb->dma = dma;
+-03026         dwc_otg_urb->length = buflen;
+-03027         dwc_otg_urb->setup_packet = setup_packet;
+-03028         dwc_otg_urb->setup_dma = setup_dma;
+-03029         dwc_otg_urb->flags = flags;
+-03030         dwc_otg_urb->interval = interval;
+-03031         dwc_otg_urb->status = -DWC_E_IN_PROGRESS;
+-03032 }
+-03033 
+-03034 uint32_t dwc_otg_hcd_urb_get_status(dwc_otg_hcd_urb_t * dwc_otg_urb)
+-03035 {
+-03036         return dwc_otg_urb->status;
+-03037 }
+-03038 
+-03039 uint32_t dwc_otg_hcd_urb_get_actual_length(dwc_otg_hcd_urb_t * dwc_otg_urb)
+-03040 {
+-03041         return dwc_otg_urb->actual_length;
+-03042 }
+-03043 
+-03044 uint32_t dwc_otg_hcd_urb_get_error_count(dwc_otg_hcd_urb_t * dwc_otg_urb)
+-03045 {
+-03046         return dwc_otg_urb->error_count;
+-03047 }
+-03048 
+-03049 void dwc_otg_hcd_urb_set_iso_desc_params(dwc_otg_hcd_urb_t * dwc_otg_urb,
+-03050                                          int desc_num, uint32_t offset,
+-03051                                          uint32_t length)
+-03052 {
+-03053         dwc_otg_urb->iso_descs[desc_num].offset = offset;
+-03054         dwc_otg_urb->iso_descs[desc_num].length = length;
+-03055 }
+-03056 
+-03057 uint32_t dwc_otg_hcd_urb_get_iso_desc_status(dwc_otg_hcd_urb_t * dwc_otg_urb,
+-03058                                              int desc_num)
+-03059 {
+-03060         return dwc_otg_urb->iso_descs[desc_num].status;
+-03061 }
+-03062 
+-03063 uint32_t dwc_otg_hcd_urb_get_iso_desc_actual_length(dwc_otg_hcd_urb_t *
+-03064                                                     dwc_otg_urb, int desc_num)
+-03065 {
+-03066         return dwc_otg_urb->iso_descs[desc_num].actual_length;
+-03067 }
+-03068 
+-03069 int dwc_otg_hcd_is_bandwidth_allocated(dwc_otg_hcd_t * hcd, void *ep_handle)
+-03070 {
+-03071         int allocated = 0;
+-03072         dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle;
+-03073 
+-03074         if (qh) {
+-03075                 if (!DWC_LIST_EMPTY(&qh->qh_list_entry)) {
+-03076                         allocated = 1;
+-03077                 }
+-03078         }
+-03079         return allocated;
+-03080 }
+-03081 
+-03082 int dwc_otg_hcd_is_bandwidth_freed(dwc_otg_hcd_t * hcd, void *ep_handle)
+-03083 {
+-03084         dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle;
+-03085         int freed = 0;
+-03086         DWC_ASSERT(qh, "qh is not allocated\n");
+-03087 
+-03088         if (DWC_LIST_EMPTY(&qh->qh_list_entry)) {
+-03089                 freed = 1;
+-03090         }
+-03091 
+-03092         return freed;
+-03093 }
+-03094 
+-03095 uint8_t dwc_otg_hcd_get_ep_bandwidth(dwc_otg_hcd_t * hcd, void *ep_handle)
+-03096 {
+-03097         dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle;
+-03098         DWC_ASSERT(qh, "qh is not allocated\n");
+-03099         return qh->usecs;
+-03100 }
+-03101 
+-03102 void dwc_otg_hcd_dump_state(dwc_otg_hcd_t * hcd)
+-03103 {
+-03104 #ifdef DEBUG
+-03105         int num_channels;
+-03106         int i;
+-03107         gnptxsts_data_t np_tx_status;
+-03108         hptxsts_data_t p_tx_status;
+-03109 
+-03110         num_channels = hcd->core_if->core_params->host_channels;
+-03111         DWC_PRINTF("\n");
+-03112         DWC_PRINTF
+-03113             ("************************************************************\n");
+-03114         DWC_PRINTF("HCD State:\n");
+-03115         DWC_PRINTF("  Num channels: %d\n", num_channels);
+-03116         for (i = 0; i < num_channels; i++) {
+-03117                 dwc_hc_t *hc = hcd->hc_ptr_array[i];
+-03118                 DWC_PRINTF("  Channel %d:\n", i);
+-03119                 DWC_PRINTF("    dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
+-03120                            hc->dev_addr, hc->ep_num, hc->ep_is_in);
+-03121                 DWC_PRINTF("    speed: %d\n", hc->speed);
+-03122                 DWC_PRINTF("    ep_type: %d\n", hc->ep_type);
+-03123                 DWC_PRINTF("    max_packet: %d\n", hc->max_packet);
+-03124                 DWC_PRINTF("    data_pid_start: %d\n", hc->data_pid_start);
+-03125                 DWC_PRINTF("    multi_count: %d\n", hc->multi_count);
+-03126                 DWC_PRINTF("    xfer_started: %d\n", hc->xfer_started);
+-03127                 DWC_PRINTF("    xfer_buff: %p\n", hc->xfer_buff);
+-03128                 DWC_PRINTF("    xfer_len: %d\n", hc->xfer_len);
+-03129                 DWC_PRINTF("    xfer_count: %d\n", hc->xfer_count);
+-03130                 DWC_PRINTF("    halt_on_queue: %d\n", hc->halt_on_queue);
+-03131                 DWC_PRINTF("    halt_pending: %d\n", hc->halt_pending);
+-03132                 DWC_PRINTF("    halt_status: %d\n", hc->halt_status);
+-03133                 DWC_PRINTF("    do_split: %d\n", hc->do_split);
+-03134                 DWC_PRINTF("    complete_split: %d\n", hc->complete_split);
+-03135                 DWC_PRINTF("    hub_addr: %d\n", hc->hub_addr);
+-03136                 DWC_PRINTF("    port_addr: %d\n", hc->port_addr);
+-03137                 DWC_PRINTF("    xact_pos: %d\n", hc->xact_pos);
+-03138                 DWC_PRINTF("    requests: %d\n", hc->requests);
+-03139                 DWC_PRINTF("    qh: %p\n", hc->qh);
+-03140                 if (hc->xfer_started) {
+-03141                         hfnum_data_t hfnum;
+-03142                         hcchar_data_t hcchar;
+-03143                         hctsiz_data_t hctsiz;
+-03144                         hcint_data_t hcint;
+-03145                         hcintmsk_data_t hcintmsk;
+-03146                         hfnum.d32 =
+-03147                             DWC_READ_REG32(&hcd->core_if->
+-03148                                            host_if->host_global_regs->hfnum);
+-03149                         hcchar.d32 =
+-03150                             DWC_READ_REG32(&hcd->core_if->host_if->
+-03151                                            hc_regs[i]->hcchar);
+-03152                         hctsiz.d32 =
+-03153                             DWC_READ_REG32(&hcd->core_if->host_if->
+-03154                                            hc_regs[i]->hctsiz);
+-03155                         hcint.d32 =
+-03156                             DWC_READ_REG32(&hcd->core_if->host_if->
+-03157                                            hc_regs[i]->hcint);
+-03158                         hcintmsk.d32 =
+-03159                             DWC_READ_REG32(&hcd->core_if->host_if->
+-03160                                            hc_regs[i]->hcintmsk);
+-03161                         DWC_PRINTF("    hfnum: 0x%08x\n", hfnum.d32);
+-03162                         DWC_PRINTF("    hcchar: 0x%08x\n", hcchar.d32);
+-03163                         DWC_PRINTF("    hctsiz: 0x%08x\n", hctsiz.d32);
+-03164                         DWC_PRINTF("    hcint: 0x%08x\n", hcint.d32);
+-03165                         DWC_PRINTF("    hcintmsk: 0x%08x\n", hcintmsk.d32);
+-03166                 }
+-03167                 if (hc->xfer_started && hc->qh) {
+-03168                         dwc_otg_qtd_t *qtd;
+-03169                         dwc_otg_hcd_urb_t *urb;
+-03170                         
+-03171                         DWC_CIRCLEQ_FOREACH(qtd, &hc->qh->qtd_list, qtd_list_entry) {
+-03172                                 if (!qtd->in_process)
+-03173                                         break;
+-03174                                 
+-03175                                 urb = qtd->urb;
+-03176                         DWC_PRINTF("    URB Info:\n");
+-03177                         DWC_PRINTF("      qtd: %p, urb: %p\n", qtd, urb);
+-03178                         if (urb) {
+-03179                                 DWC_PRINTF("      Dev: %d, EP: %d %s\n",
+-03180                                            dwc_otg_hcd_get_dev_addr(&urb->
+-03181                                                                     pipe_info),
+-03182                                            dwc_otg_hcd_get_ep_num(&urb->
+-03183                                                                   pipe_info),
+-03184                                            dwc_otg_hcd_is_pipe_in(&urb->
+-03185                                                                   pipe_info) ?
+-03186                                            "IN" : "OUT");
+-03187                                 DWC_PRINTF("      Max packet size: %d\n",
+-03188                                            dwc_otg_hcd_get_mps(&urb->
+-03189                                                                pipe_info));
+-03190                                 DWC_PRINTF("      transfer_buffer: %p\n",
+-03191                                            urb->buf);
+-03192                                 DWC_PRINTF("      transfer_dma: %p\n",
+-03193                                            (void *)urb->dma);
+-03194                                 DWC_PRINTF("      transfer_buffer_length: %d\n",
+-03195                                            urb->length);
+-03196                                         DWC_PRINTF("      actual_length: %d\n",
+-03197                                                    urb->actual_length);
+-03198                                 }
+-03199                         }
+-03200                 }
+-03201         }
+-03202         DWC_PRINTF("  non_periodic_channels: %d\n", hcd->non_periodic_channels);
+-03203         DWC_PRINTF("  periodic_channels: %d\n", hcd->periodic_channels);
+-03204         DWC_PRINTF("  periodic_usecs: %d\n", hcd->periodic_usecs);
+-03205         np_tx_status.d32 =
+-03206             DWC_READ_REG32(&hcd->core_if->core_global_regs->gnptxsts);
+-03207         DWC_PRINTF("  NP Tx Req Queue Space Avail: %d\n",
+-03208                    np_tx_status.b.nptxqspcavail);
+-03209         DWC_PRINTF("  NP Tx FIFO Space Avail: %d\n",
+-03210                    np_tx_status.b.nptxfspcavail);
+-03211         p_tx_status.d32 =
+-03212             DWC_READ_REG32(&hcd->core_if->host_if->host_global_regs->hptxsts);
+-03213         DWC_PRINTF("  P Tx Req Queue Space Avail: %d\n",
+-03214                    p_tx_status.b.ptxqspcavail);
+-03215         DWC_PRINTF("  P Tx FIFO Space Avail: %d\n", p_tx_status.b.ptxfspcavail);
+-03216         dwc_otg_hcd_dump_frrem(hcd);
+-03217         dwc_otg_dump_global_registers(hcd->core_if);
+-03218         dwc_otg_dump_host_registers(hcd->core_if);
+-03219         DWC_PRINTF
+-03220             ("************************************************************\n");
+-03221         DWC_PRINTF("\n");
+-03222 #endif
+-03223 }
+-03224 
+-03225 #ifdef DEBUG
+-03226 void dwc_print_setup_data(uint8_t * setup)
+-03227 {
+-03228         int i;
+-03229         if (CHK_DEBUG_LEVEL(DBG_HCD)) {
+-03230                 DWC_PRINTF("Setup Data = MSB ");
+-03231                 for (i = 7; i >= 0; i--)
+-03232                         DWC_PRINTF("%02x ", setup[i]);
+-03233                 DWC_PRINTF("\n");
+-03234                 DWC_PRINTF("  bmRequestType Tranfer = %s\n",
+-03235                            (setup[0] & 0x80) ? "Device-to-Host" :
+-03236                            "Host-to-Device");
+-03237                 DWC_PRINTF("  bmRequestType Type = ");
+-03238                 switch ((setup[0] & 0x60) >> 5) {
+-03239                 case 0:
+-03240                         DWC_PRINTF("Standard\n");
+-03241                         break;
+-03242                 case 1:
+-03243                         DWC_PRINTF("Class\n");
+-03244                         break;
+-03245                 case 2:
+-03246                         DWC_PRINTF("Vendor\n");
+-03247                         break;
+-03248                 case 3:
+-03249                         DWC_PRINTF("Reserved\n");
+-03250                         break;
+-03251                 }
+-03252                 DWC_PRINTF("  bmRequestType Recipient = ");
+-03253                 switch (setup[0] & 0x1f) {
+-03254                 case 0:
+-03255                         DWC_PRINTF("Device\n");
+-03256                         break;
+-03257                 case 1:
+-03258                         DWC_PRINTF("Interface\n");
+-03259                         break;
+-03260                 case 2:
+-03261                         DWC_PRINTF("Endpoint\n");
+-03262                         break;
+-03263                 case 3:
+-03264                         DWC_PRINTF("Other\n");
+-03265                         break;
+-03266                 default:
+-03267                         DWC_PRINTF("Reserved\n");
+-03268                         break;
+-03269                 }
+-03270                 DWC_PRINTF("  bRequest = 0x%0x\n", setup[1]);
+-03271                 DWC_PRINTF("  wValue = 0x%0x\n", *((uint16_t *) & setup[2]));
+-03272                 DWC_PRINTF("  wIndex = 0x%0x\n", *((uint16_t *) & setup[4]));
+-03273                 DWC_PRINTF("  wLength = 0x%0x\n\n", *((uint16_t *) & setup[6]));
+-03274         }
+-03275 }
+-03276 #endif
+-03277 
+-03278 void dwc_otg_hcd_dump_frrem(dwc_otg_hcd_t * hcd)
+-03279 {
+-03280 #if 0
+-03281         DWC_PRINTF("Frame remaining at SOF:\n");
+-03282         DWC_PRINTF("  samples %u, accum %llu, avg %llu\n",
+-03283                    hcd->frrem_samples, hcd->frrem_accum,
+-03284                    (hcd->frrem_samples > 0) ?
+-03285                    hcd->frrem_accum / hcd->frrem_samples : 0);
+-03286 
+-03287         DWC_PRINTF("\n");
+-03288         DWC_PRINTF("Frame remaining at start_transfer (uframe 7):\n");
+-03289         DWC_PRINTF("  samples %u, accum %llu, avg %llu\n",
+-03290                    hcd->core_if->hfnum_7_samples,
+-03291                    hcd->core_if->hfnum_7_frrem_accum,
+-03292                    (hcd->core_if->hfnum_7_samples >
+-03293                     0) ? hcd->core_if->hfnum_7_frrem_accum /
+-03294                    hcd->core_if->hfnum_7_samples : 0);
+-03295         DWC_PRINTF("Frame remaining at start_transfer (uframe 0):\n");
+-03296         DWC_PRINTF("  samples %u, accum %llu, avg %llu\n",
+-03297                    hcd->core_if->hfnum_0_samples,
+-03298                    hcd->core_if->hfnum_0_frrem_accum,
+-03299                    (hcd->core_if->hfnum_0_samples >
+-03300                     0) ? hcd->core_if->hfnum_0_frrem_accum /
+-03301                    hcd->core_if->hfnum_0_samples : 0);
+-03302         DWC_PRINTF("Frame remaining at start_transfer (uframe 1-6):\n");
+-03303         DWC_PRINTF("  samples %u, accum %llu, avg %llu\n",
+-03304                    hcd->core_if->hfnum_other_samples,
+-03305                    hcd->core_if->hfnum_other_frrem_accum,
+-03306                    (hcd->core_if->hfnum_other_samples >
+-03307                     0) ? hcd->core_if->hfnum_other_frrem_accum /
+-03308                    hcd->core_if->hfnum_other_samples : 0);
+-03309 
+-03310         DWC_PRINTF("\n");
+-03311         DWC_PRINTF("Frame remaining at sample point A (uframe 7):\n");
+-03312         DWC_PRINTF("  samples %u, accum %llu, avg %llu\n",
+-03313                    hcd->hfnum_7_samples_a, hcd->hfnum_7_frrem_accum_a,
+-03314                    (hcd->hfnum_7_samples_a > 0) ?
+-03315                    hcd->hfnum_7_frrem_accum_a / hcd->hfnum_7_samples_a : 0);
+-03316         DWC_PRINTF("Frame remaining at sample point A (uframe 0):\n");
+-03317         DWC_PRINTF("  samples %u, accum %llu, avg %llu\n",
+-03318                    hcd->hfnum_0_samples_a, hcd->hfnum_0_frrem_accum_a,
+-03319                    (hcd->hfnum_0_samples_a > 0) ?
+-03320                    hcd->hfnum_0_frrem_accum_a / hcd->hfnum_0_samples_a : 0);
+-03321         DWC_PRINTF("Frame remaining at sample point A (uframe 1-6):\n");
+-03322         DWC_PRINTF("  samples %u, accum %llu, avg %llu\n",
+-03323                    hcd->hfnum_other_samples_a, hcd->hfnum_other_frrem_accum_a,
+-03324                    (hcd->hfnum_other_samples_a > 0) ?
+-03325                    hcd->hfnum_other_frrem_accum_a /
+-03326                    hcd->hfnum_other_samples_a : 0);
+-03327 
+-03328         DWC_PRINTF("\n");
+-03329         DWC_PRINTF("Frame remaining at sample point B (uframe 7):\n");
+-03330         DWC_PRINTF("  samples %u, accum %llu, avg %llu\n",
+-03331                    hcd->hfnum_7_samples_b, hcd->hfnum_7_frrem_accum_b,
+-03332                    (hcd->hfnum_7_samples_b > 0) ?
+-03333                    hcd->hfnum_7_frrem_accum_b / hcd->hfnum_7_samples_b : 0);
+-03334         DWC_PRINTF("Frame remaining at sample point B (uframe 0):\n");
+-03335         DWC_PRINTF("  samples %u, accum %llu, avg %llu\n",
+-03336                    hcd->hfnum_0_samples_b, hcd->hfnum_0_frrem_accum_b,
+-03337                    (hcd->hfnum_0_samples_b > 0) ?
+-03338                    hcd->hfnum_0_frrem_accum_b / hcd->hfnum_0_samples_b : 0);
+-03339         DWC_PRINTF("Frame remaining at sample point B (uframe 1-6):\n");
+-03340         DWC_PRINTF("  samples %u, accum %llu, avg %llu\n",
+-03341                    hcd->hfnum_other_samples_b, hcd->hfnum_other_frrem_accum_b,
+-03342                    (hcd->hfnum_other_samples_b > 0) ?
+-03343                    hcd->hfnum_other_frrem_accum_b /
+-03344                    hcd->hfnum_other_samples_b : 0);
+-03345 #endif
+-03346 }
+-03347 
+-03348 #endif /* DWC_DEVICE_ONLY */
+-
                                                                                Generated on Thu Oct 27 03:56:37 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__hcd_8c.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/dwc__otg__hcd_8c.html 2013-07-26 19:34:41.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,2192 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_hcd.c File Reference +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                dwc_otg_hcd.c File Reference

                                                                                This file implements HCD Core. More... +-

                                                                                +-#include "dwc_otg_hcd.h"
                                                                                +-#include "dwc_otg_regs.h"
                                                                                +- +-

                                                                                +-Go to the source code of this file. +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-

                                                                                Functions

                                                                                +-dwc_otg_hcd_t * dwc_otg_hcd_alloc_hcd (void)
                                                                                 This function allocates dwc_otg_hcd structure and returns pointer on it.
                                                                                void dwc_otg_hcd_connect_timeout (void *ptr)
                                                                                 Connection timeout function.
                                                                                void hcd_start_func (void *_vp)
                                                                                 Work queue function for starting the HCD when A-Cable is connected.
                                                                                +-void del_xfer_timers (dwc_otg_hcd_t *hcd)
                                                                                +-void del_timers (dwc_otg_hcd_t *hcd)
                                                                                void kill_urbs_in_qh_list (dwc_otg_hcd_t *hcd, dwc_list_link_t *qh_list)
                                                                                 Processes all the URBs in a single list of QHs.
                                                                                void kill_all_urbs (dwc_otg_hcd_t *hcd)
                                                                                 Responds with an error status of ETIMEDOUT to all URBs in the non-periodic and periodic schedules.
                                                                                void dwc_otg_hcd_start_connect_timer (dwc_otg_hcd_t *hcd)
                                                                                 Start the connection timer.
                                                                                int32_t dwc_otg_hcd_session_start_cb (void *p)
                                                                                 HCD Callback function for disconnect of the HCD.
                                                                                int32_t dwc_otg_hcd_start_cb (void *p)
                                                                                 HCD Callback function for starting the HCD when A-Cable is connected.
                                                                                int32_t dwc_otg_hcd_disconnect_cb (void *p)
                                                                                 HCD Callback function for disconnect of the HCD.
                                                                                int32_t dwc_otg_hcd_stop_cb (void *p)
                                                                                 HCD Callback function for stopping the HCD.
                                                                                int dwc_otg_hcd_rem_wakeup_cb (void *p)
                                                                                 HCD Callback function for Remote Wakeup.
                                                                                void dwc_otg_hcd_stop (dwc_otg_hcd_t *hcd)
                                                                                 Halts the DWC_otg host mode operations in a clean manner.
                                                                                int dwc_otg_hcd_urb_enqueue (dwc_otg_hcd_t *hcd, dwc_otg_hcd_urb_t *dwc_otg_urb, void **ep_handle, int atomic_alloc)
                                                                                 Queue URB.
                                                                                int dwc_otg_hcd_urb_dequeue (dwc_otg_hcd_t *hcd, dwc_otg_hcd_urb_t *dwc_otg_urb)
                                                                                 De-queue the specified URB.
                                                                                int dwc_otg_hcd_endpoint_disable (dwc_otg_hcd_t *hcd, void *ep_handle, int retry)
                                                                                 Frees resources in the DWC_otg controller related to a given endpoint.
                                                                                +-int dwc_otg_hcd_endpoint_reset (dwc_otg_hcd_t *hcd, void *ep_handle)
                                                                                +-void reset_tasklet_func (void *data)
                                                                                 Reset tasklet function.
                                                                                +-void qh_list_free (dwc_otg_hcd_t *hcd, dwc_list_link_t *qh_list)
                                                                                +-void dwc_otg_hcd_power_up (void *ptr)
                                                                                 Exit from Hibernation if Host did not detect SRP from connected SRP capable Device during SRP time by host power up.
                                                                                +-void dwc_otg_hcd_free (dwc_otg_hcd_t *dwc_otg_hcd)
                                                                                 Frees secondary storage associated with the dwc_otg_hcd structure contained in the struct usb_hcd field.
                                                                                int dwc_otg_hcd_init (dwc_otg_hcd_t *hcd, dwc_otg_core_if_t *core_if)
                                                                                 This function should be called to initiate HCD Core.
                                                                                void dwc_otg_hcd_remove (dwc_otg_hcd_t *hcd)
                                                                                 Frees HCD.
                                                                                +-void dwc_otg_hcd_reinit (dwc_otg_hcd_t *hcd)
                                                                                 Initializes dynamic portions of the DWC_otg HCD state.
                                                                                void assign_and_init_hc (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
                                                                                 Assigns transactions from a QTD to a free host channel and initializes the host channel to perform the transactions.
                                                                                dwc_otg_transaction_type_e dwc_otg_hcd_select_transactions (dwc_otg_hcd_t *hcd)
                                                                                 This function selects transactions from the HCD transfer schedule and assigns them to available host channels.
                                                                                int queue_transaction (dwc_otg_hcd_t *hcd, dwc_hc_t *hc, uint16_t fifo_dwords_avail)
                                                                                 Attempts to queue a single transaction request for a host channel associated with either a periodic or non-periodic transfer.
                                                                                void process_periodic_channels (dwc_otg_hcd_t *hcd)
                                                                                 Processes periodic channels for the next frame and queues transactions for these channels to the DWC_otg controller.
                                                                                void process_non_periodic_channels (dwc_otg_hcd_t *hcd)
                                                                                 Processes active non-periodic channels and queues transactions for these channels to the DWC_otg controller.
                                                                                void dwc_otg_hcd_queue_transactions (dwc_otg_hcd_t *hcd, dwc_otg_transaction_type_e tr_type)
                                                                                 This function processes the currently active host channels and queues transactions for these channels to the DWC_otg controller.
                                                                                int dwc_otg_hcd_hub_control (dwc_otg_hcd_t *dwc_otg_hcd, uint16_t typeReq, uint16_t wValue, uint16_t wIndex, uint8_t *buf, uint16_t wLength)
                                                                                 Handles hub class-specific requests.
                                                                                int dwc_otg_hcd_is_status_changed (dwc_otg_hcd_t *hcd, int port)
                                                                                 Returns 1 if status of specified port is changed and 0 otherwise.
                                                                                int dwc_otg_hcd_get_frame_number (dwc_otg_hcd_t *dwc_otg_hcd)
                                                                                 Returns current frame number.
                                                                                int dwc_otg_hcd_start (dwc_otg_hcd_t *hcd, struct dwc_otg_hcd_function_ops *fops)
                                                                                 This function initializes the HCD Core.
                                                                                void * dwc_otg_hcd_get_priv_data (dwc_otg_hcd_t *hcd)
                                                                                 Returns private data set by dwc_otg_hcd_set_priv_data function.
                                                                                void dwc_otg_hcd_set_priv_data (dwc_otg_hcd_t *hcd, void *priv_data)
                                                                                 Set private data.
                                                                                uint32_t dwc_otg_hcd_otg_port (dwc_otg_hcd_t *hcd)
                                                                                 Returns otg port number.
                                                                                uint32_t dwc_otg_hcd_is_b_host (dwc_otg_hcd_t *hcd)
                                                                                 Returns 1 if currently core is acting as B host, and 0 otherwise.
                                                                                dwc_otg_hcd_urb_t * dwc_otg_hcd_urb_alloc (dwc_otg_hcd_t *hcd, int iso_desc_count, int atomic_alloc)
                                                                                 Allocates memory for dwc_otg_hcd_urb structure.
                                                                                void dwc_otg_hcd_urb_set_pipeinfo (dwc_otg_hcd_urb_t *dwc_otg_urb, uint8_t dev_addr, uint8_t ep_num, uint8_t ep_type, uint8_t ep_dir, uint16_t mps)
                                                                                 Set pipe information in URB.
                                                                                void dwc_otg_hcd_urb_set_params (dwc_otg_hcd_urb_t *dwc_otg_urb, void *urb_handle, void *buf, dwc_dma_t dma, uint32_t buflen, void *setup_packet, dwc_dma_t setup_dma, uint32_t flags, uint16_t interval)
                                                                                 Sets dwc_otg_hcd_urb parameters.
                                                                                uint32_t dwc_otg_hcd_urb_get_status (dwc_otg_hcd_urb_t *dwc_otg_urb)
                                                                                 Gets status from dwc_otg_hcd_urb.
                                                                                uint32_t dwc_otg_hcd_urb_get_actual_length (dwc_otg_hcd_urb_t *dwc_otg_urb)
                                                                                 Gets actual length from dwc_otg_hcd_urb.
                                                                                uint32_t dwc_otg_hcd_urb_get_error_count (dwc_otg_hcd_urb_t *dwc_otg_urb)
                                                                                 Gets error count from dwc_otg_hcd_urb.
                                                                                void dwc_otg_hcd_urb_set_iso_desc_params (dwc_otg_hcd_urb_t *dwc_otg_urb, int desc_num, uint32_t offset, uint32_t length)
                                                                                 Set ISOC descriptor offset and length.
                                                                                uint32_t dwc_otg_hcd_urb_get_iso_desc_status (dwc_otg_hcd_urb_t *dwc_otg_urb, int desc_num)
                                                                                 Get status of ISOC descriptor, specified by desc_num.
                                                                                uint32_t dwc_otg_hcd_urb_get_iso_desc_actual_length (dwc_otg_hcd_urb_t *dwc_otg_urb, int desc_num)
                                                                                 Get actual length of ISOC descriptor, specified by desc_num.
                                                                                int dwc_otg_hcd_is_bandwidth_allocated (dwc_otg_hcd_t *hcd, void *ep_handle)
                                                                                 Call this function to check if bandwidth was allocated for specified endpoint.
                                                                                int dwc_otg_hcd_is_bandwidth_freed (dwc_otg_hcd_t *hcd, void *ep_handle)
                                                                                 Call this function to check if bandwidth was freed for specified endpoint.
                                                                                uint8_t dwc_otg_hcd_get_ep_bandwidth (dwc_otg_hcd_t *hcd, void *ep_handle)
                                                                                 Returns bandwidth allocated for specified endpoint in microseconds.
                                                                                void dwc_otg_hcd_dump_state (dwc_otg_hcd_t *hcd)
                                                                                 Dumps hcd state.
                                                                                void dwc_otg_hcd_dump_frrem (dwc_otg_hcd_t *hcd)
                                                                                 Dump the average frame remaining at SOF.

                                                                                Variables

                                                                                dwc_otg_cil_callbacks_t hcd_cil_callbacks
                                                                                 HCD Callback structure for handling mode switching.
                                                                                +-

                                                                                Detailed Description

                                                                                +-This file implements HCD Core. +-

                                                                                +-All code in this file is portable and doesn't use any OS specific functions. Interface provided by HCD Core is defined in <hcd_if.h> header file. +-

                                                                                +-Definition in file dwc_otg_hcd.c.

                                                                                Function Documentation

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                void dwc_otg_hcd_connect_timeout ( void *  ptr  ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Connection timeout function. +-

                                                                                +-An OTG host is required to display a message if the device does not connect within 10 seconds. +-

                                                                                +-Definition at line 54 of file dwc_otg_hcd.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                void hcd_start_func ( void *  _vp  )  [static]
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Work queue function for starting the HCD when A-Cable is connected. +-

                                                                                +-The hcd_start() must be called in a process context. +-

                                                                                +-Definition at line 123 of file dwc_otg_hcd.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                void kill_urbs_in_qh_list ( dwc_otg_hcd_t *  hcd,
                                                                                dwc_list_link_t *  qh_list
                                                                                )  [static]
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Processes all the URBs in a single list of QHs. +-

                                                                                +-Completes them with -ETIMEDOUT and frees the QTD. +-

                                                                                +-Definition at line 154 of file dwc_otg_hcd.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                void kill_all_urbs ( dwc_otg_hcd_t *  hcd  )  [static]
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Responds with an error status of ETIMEDOUT to all URBs in the non-periodic and periodic schedules. +-

                                                                                +-The QTD associated with each URB is removed from the schedule and freed. This function may be called when a disconnect is detected or when the HCD is being stopped. +-

                                                                                +-Definition at line 181 of file dwc_otg_hcd.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                void dwc_otg_hcd_start_connect_timer ( dwc_otg_hcd_t *  hcd  )  [static]
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Start the connection timer. +-

                                                                                +-An OTG host is required to display a message if the device does not connect within 10 seconds. The timer is deleted if a port connect interrupt occurs before the timer expires. +-

                                                                                +-Definition at line 197 of file dwc_otg_hcd.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                int32_t dwc_otg_hcd_session_start_cb ( void *  p  )  [static]
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-HCD Callback function for disconnect of the HCD. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +-
                                                                                p void pointer to the struct usb_hcd
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 207 of file dwc_otg_hcd.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                int32_t dwc_otg_hcd_start_cb ( void *  p  )  [static]
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-HCD Callback function for starting the HCD when A-Cable is connected. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +-
                                                                                p void pointer to the struct usb_hcd
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 222 of file dwc_otg_hcd.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                int32_t dwc_otg_hcd_disconnect_cb ( void *  p  )  [static]
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-HCD Callback function for disconnect of the HCD. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +-
                                                                                p void pointer to the struct usb_hcd
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 252 of file dwc_otg_hcd.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                int32_t dwc_otg_hcd_stop_cb ( void *  p  )  [static]
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-HCD Callback function for stopping the HCD. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +-
                                                                                p void pointer to the struct usb_hcd
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 372 of file dwc_otg_hcd.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                int dwc_otg_hcd_rem_wakeup_cb ( void *  p  )  [static]
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-HCD Callback function for Remote Wakeup. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +-
                                                                                p void pointer to the struct usb_hcd
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 402 of file dwc_otg_hcd.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                void dwc_otg_hcd_stop ( dwc_otg_hcd_t *  hcd  ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Halts the DWC_otg host mode operations in a clean manner. +-

                                                                                +-USB transfers are stopped. +-

                                                                                +-Definition at line 421 of file dwc_otg_hcd.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                int dwc_otg_hcd_urb_enqueue ( dwc_otg_hcd_t *  dwc_otg_hcd,
                                                                                dwc_otg_hcd_urb_t *  dwc_otg_urb,
                                                                                void **  ep_handle,
                                                                                int  atomic_alloc
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Queue URB. +-

                                                                                +-After transfer is completes, the complete callback will be called with the URB status

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +- +- +-
                                                                                dwc_otg_hcd The HCD
                                                                                dwc_otg_urb DWC_OTG URB
                                                                                ep_handle Out parameter for returning endpoint handle
                                                                                atomic_alloc Flag to do atomic allocation if needed
                                                                                +-
                                                                                +-Returns -DWC_E_NO_DEVICE if no device is connected. Returns -DWC_E_NO_MEMORY if there is no enough memory. Returns 0 on success. +-

                                                                                +-Definition at line 443 of file dwc_otg_hcd.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                int dwc_otg_hcd_urb_dequeue ( dwc_otg_hcd_t *  dwc_otg_hcd,
                                                                                dwc_otg_hcd_urb_t *  dwc_otg_urb
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-De-queue the specified URB. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +-
                                                                                dwc_otg_hcd The HCD
                                                                                dwc_otg_urb DWC_OTG URB
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 492 of file dwc_otg_hcd.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                int dwc_otg_hcd_endpoint_disable ( dwc_otg_hcd_t *  hcd,
                                                                                void *  ep_handle,
                                                                                int  retry
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Frees resources in the DWC_otg controller related to a given endpoint. +-

                                                                                +-Any URBs for the endpoint must already be dequeued.

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +- +-
                                                                                hcd The HCD
                                                                                ep_handle Endpoint handle, returned by dwc_otg_hcd_urb_enqueue function
                                                                                retry Number of retries if there are queued transfers.
                                                                                +-
                                                                                +-Returns -DWC_E_INVALID if invalid arguments are passed. Returns 0 on success +-

                                                                                +-Definition at line 542 of file dwc_otg_hcd.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                int dwc_otg_hcd_init ( dwc_otg_hcd_t *  hcd,
                                                                                dwc_otg_core_if_t *  core_if
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This function should be called to initiate HCD Core. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +-
                                                                                hcd The HCD
                                                                                core_if The DWC_OTG Core
                                                                                +-
                                                                                +-Returns -DWC_E_NO_MEMORY if no enough memory. Returns 0 on success +-

                                                                                +-Definition at line 780 of file dwc_otg_hcd.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                void dwc_otg_hcd_remove ( dwc_otg_hcd_t *  hcd  ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Frees HCD. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +-
                                                                                hcd The HCD
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 879 of file dwc_otg_hcd.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                void assign_and_init_hc ( dwc_otg_hcd_t *  hcd,
                                                                                dwc_otg_qh_t *  qh
                                                                                )  [static]
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Assigns transactions from a QTD to a free host channel and initializes the host channel to perform the transactions. +-

                                                                                +-The host channel is removed from the free list.

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +-
                                                                                hcd The HCD state structure.
                                                                                qh Transactions from the first QTD for this QH are selected and assigned to a free host channel.
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 936 of file dwc_otg_hcd.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                dwc_otg_transaction_type_e dwc_otg_hcd_select_transactions ( dwc_otg_hcd_t *  hcd  ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This function selects transactions from the HCD transfer schedule and assigns them to available host channels. +-

                                                                                +-It is called from HCD interrupt handler functions.

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +-
                                                                                hcd The HCD state structure.
                                                                                +-
                                                                                +-
                                                                                Returns:
                                                                                The types of new transactions that were assigned to host channels.
                                                                                +- +-

                                                                                +-Definition at line 1168 of file dwc_otg_hcd.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                int queue_transaction ( dwc_otg_hcd_t *  hcd,
                                                                                dwc_hc_t *  hc,
                                                                                uint16_t  fifo_dwords_avail
                                                                                )  [static]
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Attempts to queue a single transaction request for a host channel associated with either a periodic or non-periodic transfer. +-

                                                                                +-This function assumes that there is space available in the appropriate request queue. For an OUT transfer or SETUP transaction in Slave mode, it checks whether space is available in the appropriate Tx FIFO.

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +- +-
                                                                                hcd The HCD state structure.
                                                                                hc Host channel descriptor associated with either a periodic or non-periodic transfer.
                                                                                fifo_dwords_avail Number of DWORDs available in the periodic Tx FIFO for periodic transfers or the non-periodic Tx FIFO for non-periodic transfers.
                                                                                +-
                                                                                +-
                                                                                Returns:
                                                                                1 if a request is queued and more requests may be needed to complete the transfer, 0 if no more requests are required for this transfer, -1 if there is insufficient space in the Tx FIFO.
                                                                                +- +-

                                                                                +-Definition at line 1253 of file dwc_otg_hcd.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                void process_periodic_channels ( dwc_otg_hcd_t *  hcd  )  [static]
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Processes periodic channels for the next frame and queues transactions for these channels to the DWC_otg controller. +-

                                                                                +-After queueing transactions, the Periodic Tx FIFO Empty interrupt is enabled if there are more transactions to queue as Periodic Tx FIFO or request queue space becomes available. Otherwise, the Periodic Tx FIFO Empty interrupt is disabled. +-

                                                                                +-Definition at line 1313 of file dwc_otg_hcd.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                void process_non_periodic_channels ( dwc_otg_hcd_t *  hcd  )  [static]
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Processes active non-periodic channels and queues transactions for these channels to the DWC_otg controller. +-

                                                                                +-After queueing transactions, the NP Tx FIFO Empty interrupt is enabled if there are more transactions to queue as NP Tx FIFO or request queue space becomes available. Otherwise, the NP Tx FIFO Empty interrupt is disabled. +-

                                                                                +-Definition at line 1430 of file dwc_otg_hcd.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                void dwc_otg_hcd_queue_transactions ( dwc_otg_hcd_t *  hcd,
                                                                                dwc_otg_transaction_type_e  tr_type
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This function processes the currently active host channels and queues transactions for these channels to the DWC_otg controller. +-

                                                                                +-It is called from HCD interrupt handler functions.

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +-
                                                                                hcd The HCD state structure.
                                                                                tr_type The type(s) of transactions to queue (non-periodic, periodic, or both).
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 1540 of file dwc_otg_hcd.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                int dwc_otg_hcd_hub_control ( dwc_otg_hcd_t *  dwc_otg_hcd,
                                                                                uint16_t  typeReq,
                                                                                uint16_t  wValue,
                                                                                uint16_t  wIndex,
                                                                                uint8_t *  buf,
                                                                                uint16_t  wLength
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Handles hub class-specific requests. +-

                                                                                +-

                                                                                Todo:
                                                                                  +-
                                                                                • check how sw can wait for 1 sec to check asesvld???
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 2015 of file dwc_otg_hcd.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                int dwc_otg_hcd_is_status_changed ( dwc_otg_hcd_t *  hcd,
                                                                                int  port
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Returns 1 if status of specified port is changed and 0 otherwise. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +-
                                                                                hcd The HCD
                                                                                port Port number
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 2896 of file dwc_otg_hcd.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                int dwc_otg_hcd_get_frame_number ( dwc_otg_hcd_t *  hcd  ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Returns current frame number. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +-
                                                                                hcd The HCD
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 2928 of file dwc_otg_hcd.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                int dwc_otg_hcd_start ( dwc_otg_hcd_t *  hcd,
                                                                                struct dwc_otg_hcd_function_ops *  fops
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This function initializes the HCD Core. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +-
                                                                                hcd The HCD
                                                                                fops The Function Driver Operations data structure containing pointers to all callbacks.
                                                                                +-
                                                                                +-Returns -DWC_E_NO_DEVICE if Core is currently is in device mode. Returns 0 on success +-

                                                                                +-Definition at line 2942 of file dwc_otg_hcd.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                void* dwc_otg_hcd_get_priv_data ( dwc_otg_hcd_t *  hcd  ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Returns private data set by dwc_otg_hcd_set_priv_data function. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +-
                                                                                hcd The HCD
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 2958 of file dwc_otg_hcd.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                void dwc_otg_hcd_set_priv_data ( dwc_otg_hcd_t *  hcd,
                                                                                void *  priv_data
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Set private data. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +-
                                                                                hcd The HCD
                                                                                priv_data pointer to be stored in private data
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 2963 of file dwc_otg_hcd.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                uint32_t dwc_otg_hcd_otg_port ( dwc_otg_hcd_t *  hcd  ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Returns otg port number. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +-
                                                                                hcd The HCD
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 2968 of file dwc_otg_hcd.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                uint32_t dwc_otg_hcd_is_b_host ( dwc_otg_hcd_t *  hcd  ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Returns 1 if currently core is acting as B host, and 0 otherwise. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +-
                                                                                hcd The HCD
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 2973 of file dwc_otg_hcd.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                dwc_otg_hcd_urb_t* dwc_otg_hcd_urb_alloc ( dwc_otg_hcd_t *  hcd,
                                                                                int  iso_desc_count,
                                                                                int  atomic_alloc
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Allocates memory for dwc_otg_hcd_urb structure. +-

                                                                                +-Allocated memory should be freed by call of DWC_FREE.

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +- +-
                                                                                hcd The HCD
                                                                                iso_desc_count Count of ISOC descriptors
                                                                                atomic_alloc Specefies whether to perform atomic allocation.
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 2985 of file dwc_otg_hcd.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                void dwc_otg_hcd_urb_set_pipeinfo ( dwc_otg_hcd_urb_t *  hcd_urb,
                                                                                uint8_t  devaddr,
                                                                                uint8_t  ep_num,
                                                                                uint8_t  ep_type,
                                                                                uint8_t  ep_dir,
                                                                                uint16_t  mps
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Set pipe information in URB. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +- +- +- +- +-
                                                                                hcd_urb DWC_OTG URB
                                                                                devaddr Device Address
                                                                                ep_num Endpoint Number
                                                                                ep_type Endpoint Type
                                                                                ep_dir Endpoint Direction
                                                                                mps Max Packet Size
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 3004 of file dwc_otg_hcd.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                void dwc_otg_hcd_urb_set_params ( dwc_otg_hcd_urb_t *  urb,
                                                                                void *  urb_handle,
                                                                                void *  buf,
                                                                                dwc_dma_t  dma,
                                                                                uint32_t  buflen,
                                                                                void *  sp,
                                                                                dwc_dma_t  sp_dma,
                                                                                uint32_t  flags,
                                                                                uint16_t  interval
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Sets dwc_otg_hcd_urb parameters. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +- +- +- +- +- +- +- +-
                                                                                urb DWC_OTG URB allocated by dwc_otg_hcd_urb_alloc function.
                                                                                urb_handle Unique handle for request, this will be passed back to function driver in completion callback.
                                                                                buf The buffer for the data
                                                                                dma The DMA buffer for the data
                                                                                buflen Transfer length
                                                                                sp Buffer for setup data
                                                                                sp_dma DMA address of setup data buffer
                                                                                flags Transfer flags
                                                                                interval Polling interval for interrupt or isochronous transfers.
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 3017 of file dwc_otg_hcd.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                uint32_t dwc_otg_hcd_urb_get_status ( dwc_otg_hcd_urb_t *  dwc_otg_urb  ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Gets status from dwc_otg_hcd_urb. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +-
                                                                                dwc_otg_urb DWC_OTG URB
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 3034 of file dwc_otg_hcd.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                uint32_t dwc_otg_hcd_urb_get_actual_length ( dwc_otg_hcd_urb_t *  dwc_otg_urb  ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Gets actual length from dwc_otg_hcd_urb. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +-
                                                                                dwc_otg_urb DWC_OTG URB
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 3039 of file dwc_otg_hcd.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                uint32_t dwc_otg_hcd_urb_get_error_count ( dwc_otg_hcd_urb_t *  dwc_otg_urb  ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Gets error count from dwc_otg_hcd_urb. +-

                                                                                +-Only for ISOC URBs

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +-
                                                                                dwc_otg_urb DWC_OTG URB
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 3044 of file dwc_otg_hcd.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                void dwc_otg_hcd_urb_set_iso_desc_params ( dwc_otg_hcd_urb_t *  dwc_otg_urb,
                                                                                int  desc_num,
                                                                                uint32_t  offset,
                                                                                uint32_t  length
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Set ISOC descriptor offset and length. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +- +- +-
                                                                                dwc_otg_urb DWC_OTG URB
                                                                                desc_num ISOC descriptor number
                                                                                offset Offset from beginig of buffer.
                                                                                length Transaction length
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 3049 of file dwc_otg_hcd.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                uint32_t dwc_otg_hcd_urb_get_iso_desc_status ( dwc_otg_hcd_urb_t *  dwc_otg_urb,
                                                                                int  desc_num
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Get status of ISOC descriptor, specified by desc_num. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +-
                                                                                dwc_otg_urb DWC_OTG URB
                                                                                desc_num ISOC descriptor number
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 3057 of file dwc_otg_hcd.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                uint32_t dwc_otg_hcd_urb_get_iso_desc_actual_length ( dwc_otg_hcd_urb_t *  dwc_otg_urb,
                                                                                int  desc_num
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Get actual length of ISOC descriptor, specified by desc_num. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +-
                                                                                dwc_otg_urb DWC_OTG URB
                                                                                desc_num ISOC descriptor number
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 3063 of file dwc_otg_hcd.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                int dwc_otg_hcd_is_bandwidth_allocated ( dwc_otg_hcd_t *  hcd,
                                                                                void *  ep_handle
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Call this function to check if bandwidth was allocated for specified endpoint. +-

                                                                                +-Only for ISOC and INTERRUPT endpoints.

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +-
                                                                                hcd The HCD
                                                                                ep_handle Endpoint handle
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 3069 of file dwc_otg_hcd.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                int dwc_otg_hcd_is_bandwidth_freed ( dwc_otg_hcd_t *  hcd,
                                                                                void *  ep_handle
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Call this function to check if bandwidth was freed for specified endpoint. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +-
                                                                                hcd The HCD
                                                                                ep_handle Endpoint handle
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 3082 of file dwc_otg_hcd.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                uint8_t dwc_otg_hcd_get_ep_bandwidth ( dwc_otg_hcd_t *  hcd,
                                                                                void *  ep_handle
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Returns bandwidth allocated for specified endpoint in microseconds. +-

                                                                                +-Only for ISOC and INTERRUPT endpoints.

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +-
                                                                                hcd The HCD
                                                                                ep_handle Endpoint handle
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 3095 of file dwc_otg_hcd.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                void dwc_otg_hcd_dump_state ( dwc_otg_hcd_t *  hcd  ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Dumps hcd state. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +-
                                                                                hcd The HCD
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 3102 of file dwc_otg_hcd.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                void dwc_otg_hcd_dump_frrem ( dwc_otg_hcd_t *  hcd  ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Dump the average frame remaining at SOF. +-

                                                                                +-This can be used to determine average interrupt latency. Frame remaining is also shown for start transfer and two additional sample points. Currently this function is not implemented.

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +-
                                                                                hcd The HCD
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 3278 of file dwc_otg_hcd.c.

                                                                                +-

                                                                                Variable Documentation

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                dwc_otg_cil_callbacks_t hcd_cil_callbacks [static]
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Initial value:

                                                                                 {
+-        .start = dwc_otg_hcd_start_cb,
+-        .stop = dwc_otg_hcd_stop_cb,
+-        .disconnect = dwc_otg_hcd_disconnect_cb,
+-        .session_start = dwc_otg_hcd_session_start_cb,
+-        .resume_wakeup = dwc_otg_hcd_rem_wakeup_cb,
+-
+-
+-
+-        .p = 0,
+-}
+-
                                                                                HCD Callback structure for handling mode switching. +-

                                                                                +- +-

                                                                                +-Definition at line 599 of file dwc_otg_hcd.c.

                                                                                +-

                                                                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__hcd_8h-source.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/dwc__otg__hcd_8h-source.html 2013-07-26 19:34:41.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,516 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_hcd.h Source File +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                dwc_otg_hcd.h

                                                                                Go to the documentation of this file.
                                                                                00001 /* ==========================================================================
+-00002  * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd.h $
+-00003  * $Revision: #58 $
+-00004  * $Date: 2011/09/15 $
+-00005  * $Change: 1846647 $
+-00006  *
+-00007  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
+-00008  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
+-00009  * otherwise expressly agreed to in writing between Synopsys and you.
+-00010  *
+-00011  * The Software IS NOT an item of Licensed Software or Licensed Product under
+-00012  * any End User Software License Agreement or Agreement for Licensed Product
+-00013  * with Synopsys or any supplement thereto. You are permitted to use and
+-00014  * redistribute this Software in source and binary forms, with or without
+-00015  * modification, provided that redistributions of source code must retain this
+-00016  * notice. You may not view, use, disclose, copy or distribute this file or
+-00017  * any information contained herein except pursuant to this license grant from
+-00018  * Synopsys. If you do not agree with this notice, including the disclaimer
+-00019  * below, then you are not authorized to use the Software.
+-00020  *
+-00021  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
+-00022  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+-00023  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+-00024  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
+-00025  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+-00026  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+-00027  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+-00028  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+-00029  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+-00030  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+-00031  * DAMAGE.
+-00032  * ========================================================================== */
+-00033 #ifndef DWC_DEVICE_ONLY
+-00034 #ifndef __DWC_HCD_H__
+-00035 #define __DWC_HCD_H__
+-00036 
+-00037 #include "dwc_otg_os_dep.h"
+-00038 #include "usb.h"
+-00039 #include "dwc_otg_hcd_if.h"
+-00040 #include "dwc_otg_core_if.h"
+-00041 #include "dwc_list.h"
+-00042 #include "dwc_otg_cil.h"
+-00043 
+-00056 struct dwc_otg_hcd_pipe_info {
+-00057         uint8_t dev_addr;
+-00058         uint8_t ep_num;
+-00059         uint8_t pipe_type;
+-00060         uint8_t pipe_dir;
+-00061         uint16_t mps;
+-00062 };
+-00063 
+-00064 struct dwc_otg_hcd_iso_packet_desc {
+-00065         uint32_t offset;
+-00066         uint32_t length;
+-00067         uint32_t actual_length;
+-00068         uint32_t status;
+-00069 };
+-00070 
+-00071 struct dwc_otg_qtd;
+-00072 
+-00073 struct dwc_otg_hcd_urb {
+-00074         void *priv;
+-00075         struct dwc_otg_qtd *qtd;
+-00076         void *buf;
+-00077         dwc_dma_t dma;
+-00078         void *setup_packet;
+-00079         dwc_dma_t setup_dma;
+-00080         uint32_t length;
+-00081         uint32_t actual_length;
+-00082         uint32_t status;
+-00083         uint32_t error_count;
+-00084         uint32_t packet_count;
+-00085         uint32_t flags;
+-00086         uint16_t interval;
+-00087         struct dwc_otg_hcd_pipe_info pipe_info;
+-00088         struct dwc_otg_hcd_iso_packet_desc iso_descs[0];
+-00089 };
+-00090 
+-00091 static inline uint8_t dwc_otg_hcd_get_ep_num(struct dwc_otg_hcd_pipe_info *pipe)
+-00092 {
+-00093         return pipe->ep_num;
+-00094 }
+-00095 
+-00096 static inline uint8_t dwc_otg_hcd_get_pipe_type(struct dwc_otg_hcd_pipe_info
+-00097                                                 *pipe)
+-00098 {
+-00099         return pipe->pipe_type;
+-00100 }
+-00101 
+-00102 static inline uint16_t dwc_otg_hcd_get_mps(struct dwc_otg_hcd_pipe_info *pipe)
+-00103 {
+-00104         return pipe->mps;
+-00105 }
+-00106 
+-00107 static inline uint8_t dwc_otg_hcd_get_dev_addr(struct dwc_otg_hcd_pipe_info
+-00108                                                *pipe)
+-00109 {
+-00110         return pipe->dev_addr;
+-00111 }
+-00112 
+-00113 static inline uint8_t dwc_otg_hcd_is_pipe_isoc(struct dwc_otg_hcd_pipe_info
+-00114                                                *pipe)
+-00115 {
+-00116         return (pipe->pipe_type == UE_ISOCHRONOUS);
+-00117 }
+-00118 
+-00119 static inline uint8_t dwc_otg_hcd_is_pipe_int(struct dwc_otg_hcd_pipe_info
+-00120                                               *pipe)
+-00121 {
+-00122         return (pipe->pipe_type == UE_INTERRUPT);
+-00123 }
+-00124 
+-00125 static inline uint8_t dwc_otg_hcd_is_pipe_bulk(struct dwc_otg_hcd_pipe_info
+-00126                                                *pipe)
+-00127 {
+-00128         return (pipe->pipe_type == UE_BULK);
+-00129 }
+-00130 
+-00131 static inline uint8_t dwc_otg_hcd_is_pipe_control(struct dwc_otg_hcd_pipe_info
+-00132                                                   *pipe)
+-00133 {
+-00134         return (pipe->pipe_type == UE_CONTROL);
+-00135 }
+-00136 
+-00137 static inline uint8_t dwc_otg_hcd_is_pipe_in(struct dwc_otg_hcd_pipe_info *pipe)
+-00138 {
+-00139         return (pipe->pipe_dir == UE_DIR_IN);
+-00140 }
+-00141 
+-00142 static inline uint8_t dwc_otg_hcd_is_pipe_out(struct dwc_otg_hcd_pipe_info
+-00143                                               *pipe)
+-00144 {
+-00145         return (!dwc_otg_hcd_is_pipe_in(pipe));
+-00146 }
+-00147 
+-00148 static inline void dwc_otg_hcd_fill_pipe(struct dwc_otg_hcd_pipe_info *pipe,
+-00149                                          uint8_t devaddr, uint8_t ep_num,
+-00150                                          uint8_t pipe_type, uint8_t pipe_dir,
+-00151                                          uint16_t mps)
+-00152 {
+-00153         pipe->dev_addr = devaddr;
+-00154         pipe->ep_num = ep_num;
+-00155         pipe->pipe_type = pipe_type;
+-00156         pipe->pipe_dir = pipe_dir;
+-00157         pipe->mps = mps;
+-00158 }
+-00159 
+-00163 typedef enum dwc_otg_control_phase {
+-00164         DWC_OTG_CONTROL_SETUP,
+-00165         DWC_OTG_CONTROL_DATA,
+-00166         DWC_OTG_CONTROL_STATUS
+-00167 } dwc_otg_control_phase_e;
+-00168 
+-00170 typedef enum dwc_otg_transaction_type {
+-00171         DWC_OTG_TRANSACTION_NONE,
+-00172         DWC_OTG_TRANSACTION_PERIODIC,
+-00173         DWC_OTG_TRANSACTION_NON_PERIODIC,
+-00174         DWC_OTG_TRANSACTION_ALL
+-00175 } dwc_otg_transaction_type_e;
+-00176 
+-00177 struct dwc_otg_qh;
+-00178 
+-00192 typedef struct dwc_otg_qtd {
+-00200         uint8_t data_toggle;
+-00201 
+-00203         dwc_otg_control_phase_e control_phase;
+-00204 
+-00207         uint8_t complete_split;
+-00208 
+-00210         uint32_t ssplit_out_xfer_count;
+-00211 
+-00216         uint8_t error_count;
+-00217 
+-00225         uint16_t isoc_frame_index;
+-00226 
+-00228         uint8_t isoc_split_pos;
+-00229 
+-00231         uint16_t isoc_split_offset;
+-00232 
+-00234         struct dwc_otg_hcd_urb *urb;
+-00235 
+-00236         struct dwc_otg_qh *qh;
+-00237 
+-00239          DWC_CIRCLEQ_ENTRY(dwc_otg_qtd) qtd_list_entry;
+-00240 
+-00242         uint8_t in_process;
+-00243 
+-00245         uint8_t n_desc;
+-00246 
+-00251         uint16_t isoc_frame_index_last;
+-00252 
+-00253 } dwc_otg_qtd_t;
+-00254 
+-00255 DWC_CIRCLEQ_HEAD(dwc_otg_qtd_list, dwc_otg_qtd);
+-00256 
+-00262 typedef struct dwc_otg_qh {
+-00271         uint8_t ep_type;
+-00272         uint8_t ep_is_in;
+-00273 
+-00275         uint16_t maxp;
+-00276 
+-00284         uint8_t dev_speed;
+-00285 
+-00293         uint8_t data_toggle;
+-00294 
+-00296         uint8_t ping_state;
+-00297 
+-00301         struct dwc_otg_qtd_list qtd_list;
+-00302 
+-00304         struct dwc_hc *channel;
+-00305 
+-00307         uint8_t do_split;
+-00308 
+-00313         uint16_t usecs;
+-00314 
+-00316         uint16_t interval;
+-00317 
+-00322         uint16_t sched_frame;
+-00323 
+-00325         uint16_t start_split_frame;
+-00326 
+-00333         uint8_t *dw_align_buf;
+-00334         dwc_dma_t dw_align_buf_dma;
+-00335 
+-00337         dwc_list_link_t qh_list_entry;
+-00338 
+-00343         dwc_otg_host_dma_desc_t *desc_list;
+-00344 
+-00346         dwc_dma_t desc_list_dma;
+-00347 
+-00353         uint32_t *n_bytes;
+-00354 
+-00356         uint16_t ntd;
+-00357 
+-00359         uint8_t td_first;
+-00361         uint8_t td_last;
+-00362 
+-00365 } dwc_otg_qh_t;
+-00366 
+-00367 DWC_CIRCLEQ_HEAD(hc_list, dwc_hc);
+-00368 
+-00373 struct dwc_otg_hcd {
+-00375         struct dwc_otg_device *otg_dev;
+-00377         dwc_otg_core_if_t *core_if;
+-00378 
+-00380         struct dwc_otg_hcd_function_ops *fops;
+-00381 
+-00383         volatile union dwc_otg_hcd_internal_flags {
+-00384                 uint32_t d32;
+-00385                 struct {
+-00386                         unsigned port_connect_status_change:1;
+-00387                         unsigned port_connect_status:1;
+-00388                         unsigned port_reset_change:1;
+-00389                         unsigned port_enable_change:1;
+-00390                         unsigned port_suspend_change:1;
+-00391                         unsigned port_over_current_change:1;
+-00392                         unsigned port_l1_change:1;
+-00393                         unsigned reserved:26;
+-00394                 } b;
+-00395         } flags;
+-00396 
+-00402         dwc_list_link_t non_periodic_sched_inactive;
+-00403 
+-00409         dwc_list_link_t non_periodic_sched_active;
+-00410 
+-00415         dwc_list_link_t *non_periodic_qh_ptr;
+-00416 
+-00431         dwc_list_link_t periodic_sched_inactive;
+-00432 
+-00440         dwc_list_link_t periodic_sched_ready;
+-00441 
+-00449         dwc_list_link_t periodic_sched_assigned;
+-00450 
+-00460         dwc_list_link_t periodic_sched_queued;
+-00461 
+-00467         uint16_t periodic_usecs;
+-00468 
+-00473         uint16_t frame_number;
+-00474 
+-00478         uint16_t periodic_qh_count;
+-00479 
+-00484         struct hc_list free_hc_list;
+-00491         int periodic_channels;
+-00492 
+-00496         int non_periodic_channels;
+-00497 
+-00503         struct dwc_hc *hc_ptr_array[MAX_EPS_CHANNELS];
+-00504 
+-00510         uint8_t *status_buf;
+-00511 
+-00515         dma_addr_t status_buf_dma;
+-00516 #define DWC_OTG_HCD_STATUS_BUF_SIZE 64
+-00517 
+-00523         dwc_timer_t *conn_timer;
+-00524 
+-00525         /* Tasket to do a reset */
+-00526         dwc_tasklet_t *reset_tasklet;
+-00527 
+-00528         /*  */
+-00529         dwc_spinlock_t *lock;
+-00530 
+-00534         void *priv;
+-00535 
+-00536         uint8_t otg_port;
+-00537 
+-00539         uint32_t *frame_list;
+-00540 
+-00542         dma_addr_t frame_list_dma;
+-00543 
+-00544 #ifdef DEBUG
+-00545         uint32_t frrem_samples;
+-00546         uint64_t frrem_accum;
+-00547 
+-00548         uint32_t hfnum_7_samples_a;
+-00549         uint64_t hfnum_7_frrem_accum_a;
+-00550         uint32_t hfnum_0_samples_a;
+-00551         uint64_t hfnum_0_frrem_accum_a;
+-00552         uint32_t hfnum_other_samples_a;
+-00553         uint64_t hfnum_other_frrem_accum_a;
+-00554 
+-00555         uint32_t hfnum_7_samples_b;
+-00556         uint64_t hfnum_7_frrem_accum_b;
+-00557         uint32_t hfnum_0_samples_b;
+-00558         uint64_t hfnum_0_frrem_accum_b;
+-00559         uint32_t hfnum_other_samples_b;
+-00560         uint64_t hfnum_other_frrem_accum_b;
+-00561 #endif
+-00562 };
+-00563 
+-00566 extern dwc_otg_transaction_type_e dwc_otg_hcd_select_transactions(dwc_otg_hcd_t
+-00567                                                                   * hcd);
+-00568 extern void dwc_otg_hcd_queue_transactions(dwc_otg_hcd_t * hcd,
+-00569                                            dwc_otg_transaction_type_e tr_type);
+-00570 
+-00575 extern int32_t dwc_otg_hcd_handle_intr(dwc_otg_hcd_t * dwc_otg_hcd);
+-00576 extern int32_t dwc_otg_hcd_handle_sof_intr(dwc_otg_hcd_t * dwc_otg_hcd);
+-00577 extern int32_t dwc_otg_hcd_handle_rx_status_q_level_intr(dwc_otg_hcd_t *
+-00578                                                          dwc_otg_hcd);
+-00579 extern int32_t dwc_otg_hcd_handle_np_tx_fifo_empty_intr(dwc_otg_hcd_t *
+-00580                                                         dwc_otg_hcd);
+-00581 extern int32_t dwc_otg_hcd_handle_perio_tx_fifo_empty_intr(dwc_otg_hcd_t *
+-00582                                                            dwc_otg_hcd);
+-00583 extern int32_t dwc_otg_hcd_handle_incomplete_periodic_intr(dwc_otg_hcd_t *
+-00584                                                            dwc_otg_hcd);
+-00585 extern int32_t dwc_otg_hcd_handle_port_intr(dwc_otg_hcd_t * dwc_otg_hcd);
+-00586 extern int32_t dwc_otg_hcd_handle_conn_id_status_change_intr(dwc_otg_hcd_t *
+-00587                                                              dwc_otg_hcd);
+-00588 extern int32_t dwc_otg_hcd_handle_disconnect_intr(dwc_otg_hcd_t * dwc_otg_hcd);
+-00589 extern int32_t dwc_otg_hcd_handle_hc_intr(dwc_otg_hcd_t * dwc_otg_hcd);
+-00590 extern int32_t dwc_otg_hcd_handle_hc_n_intr(dwc_otg_hcd_t * dwc_otg_hcd,
+-00591                                             uint32_t num);
+-00592 extern int32_t dwc_otg_hcd_handle_session_req_intr(dwc_otg_hcd_t * dwc_otg_hcd);
+-00593 extern int32_t dwc_otg_hcd_handle_wakeup_detected_intr(dwc_otg_hcd_t *
+-00594                                                        dwc_otg_hcd);
+-00600 /* Implemented in dwc_otg_hcd_queue.c */
+-00601 extern dwc_otg_qh_t *dwc_otg_hcd_qh_create(dwc_otg_hcd_t * hcd,
+-00602                                            dwc_otg_hcd_urb_t * urb, int atomic_alloc);
+-00603 extern void dwc_otg_hcd_qh_free(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh);
+-00604 extern int dwc_otg_hcd_qh_add(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh);
+-00605 extern void dwc_otg_hcd_qh_remove(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh);
+-00606 extern void dwc_otg_hcd_qh_deactivate(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh,
+-00607                                       int sched_csplit);
+-00608 
+-00610 static inline void dwc_otg_hcd_qh_remove_and_free(dwc_otg_hcd_t * hcd,
+-00611                                                   dwc_otg_qh_t * qh)
+-00612 {
+-00613         dwc_irqflags_t flags;
+-00614         DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
+-00615         dwc_otg_hcd_qh_remove(hcd, qh);
+-00616         DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
+-00617         dwc_otg_hcd_qh_free(hcd, qh);
+-00618 }
+-00619 
+-00622 static inline dwc_otg_qh_t *dwc_otg_hcd_qh_alloc(int atomic_alloc)
+-00623 {
+-00624         if (atomic_alloc)
+-00625                 return (dwc_otg_qh_t *) DWC_ALLOC_ATOMIC(sizeof(dwc_otg_qh_t));
+-00626         else
+-00627                 return (dwc_otg_qh_t *) DWC_ALLOC(sizeof(dwc_otg_qh_t));
+-00628 }
+-00629 
+-00630 extern dwc_otg_qtd_t *dwc_otg_hcd_qtd_create(dwc_otg_hcd_urb_t * urb,
+-00631                                              int atomic_alloc);
+-00632 extern void dwc_otg_hcd_qtd_init(dwc_otg_qtd_t * qtd, dwc_otg_hcd_urb_t * urb);
+-00633 extern int dwc_otg_hcd_qtd_add(dwc_otg_qtd_t * qtd, dwc_otg_hcd_t * dwc_otg_hcd,
+-00634                                dwc_otg_qh_t ** qh, int atomic_alloc);
+-00635 
+-00638 static inline dwc_otg_qtd_t *dwc_otg_hcd_qtd_alloc(int atomic_alloc)
+-00639 {
+-00640         if (atomic_alloc)
+-00641                 return (dwc_otg_qtd_t *) DWC_ALLOC_ATOMIC(sizeof(dwc_otg_qtd_t));
+-00642         else
+-00643                 return (dwc_otg_qtd_t *) DWC_ALLOC(sizeof(dwc_otg_qtd_t));
+-00644 }
+-00645 
+-00649 static inline void dwc_otg_hcd_qtd_free(dwc_otg_qtd_t * qtd)
+-00650 {
+-00651         DWC_FREE(qtd);
+-00652 }
+-00653 
+-00659 static inline void dwc_otg_hcd_qtd_remove(dwc_otg_hcd_t * hcd,
+-00660                                           dwc_otg_qtd_t * qtd,
+-00661                                           dwc_otg_qh_t * qh)
+-00662 {
+-00663         DWC_CIRCLEQ_REMOVE(&qh->qtd_list, qtd, qtd_list_entry);
+-00664 }
+-00665 
+-00669 static inline void dwc_otg_hcd_qtd_remove_and_free(dwc_otg_hcd_t * hcd,
+-00670                                                    dwc_otg_qtd_t * qtd,
+-00671                                                    dwc_otg_qh_t * qh)
+-00672 {
+-00673         dwc_otg_hcd_qtd_remove(hcd, qtd, qh);
+-00674         dwc_otg_hcd_qtd_free(qtd);
+-00675 }
+-00676 
+-00682 extern void dwc_otg_hcd_start_xfer_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh);
+-00683 extern void dwc_otg_hcd_complete_xfer_ddma(dwc_otg_hcd_t * hcd,
+-00684                                            dwc_hc_t * hc,
+-00685                                            dwc_otg_hc_regs_t * hc_regs,
+-00686                                            dwc_otg_halt_status_e halt_status);
+-00687 
+-00688 extern int dwc_otg_hcd_qh_init_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh);
+-00689 extern void dwc_otg_hcd_qh_free_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh);
+-00690 
+-00695 dwc_otg_qh_t *dwc_urb_to_qh(dwc_otg_hcd_urb_t * urb);
+-00698 #ifdef CONFIG_USB_DWC_OTG_LPM
+-00699 extern int dwc_otg_hcd_get_hc_for_lpm_tran(dwc_otg_hcd_t * hcd,
+-00700                                            uint8_t devaddr);
+-00701 extern void dwc_otg_hcd_free_hc_from_lpm(dwc_otg_hcd_t * hcd);
+-00702 #endif
+-00703 
+-00705 #define dwc_list_to_qh(_list_head_ptr_) container_of(_list_head_ptr_, dwc_otg_qh_t, qh_list_entry)
+-00706 
+-00708 #define dwc_list_to_qtd(_list_head_ptr_) container_of(_list_head_ptr_, dwc_otg_qtd_t, qtd_list_entry)
+-00709 
+-00711 #define dwc_qh_is_non_per(_qh_ptr_) ((_qh_ptr_->ep_type == UE_BULK) || \
+-00712                                      (_qh_ptr_->ep_type == UE_CONTROL))
+-00713 
+-00715 #define dwc_hb_mult(wMaxPacketSize) (1 + (((wMaxPacketSize) >> 11) & 0x03))
+-00716 
+-00718 #define dwc_max_packet(wMaxPacketSize) ((wMaxPacketSize) & 0x07ff)
+-00719 
+-00725 static inline int dwc_frame_num_le(uint16_t frame1, uint16_t frame2)
+-00726 {
+-00727         return ((frame2 - frame1) & DWC_HFNUM_MAX_FRNUM) <=
+-00728             (DWC_HFNUM_MAX_FRNUM >> 1);
+-00729 }
+-00730 
+-00736 static inline int dwc_frame_num_gt(uint16_t frame1, uint16_t frame2)
+-00737 {
+-00738         return (frame1 != frame2) &&
+-00739             (((frame1 - frame2) & DWC_HFNUM_MAX_FRNUM) <
+-00740              (DWC_HFNUM_MAX_FRNUM >> 1));
+-00741 }
+-00742 
+-00747 static inline uint16_t dwc_frame_num_inc(uint16_t frame, uint16_t inc)
+-00748 {
+-00749         return (frame + inc) & DWC_HFNUM_MAX_FRNUM;
+-00750 }
+-00751 
+-00752 static inline uint16_t dwc_full_frame_num(uint16_t frame)
+-00753 {
+-00754         return (frame & DWC_HFNUM_MAX_FRNUM) >> 3;
+-00755 }
+-00756 
+-00757 static inline uint16_t dwc_micro_frame_num(uint16_t frame)
+-00758 {
+-00759         return frame & 0x7;
+-00760 }
+-00761 
+-00762 void dwc_otg_hcd_save_data_toggle(dwc_hc_t * hc,
+-00763                                   dwc_otg_hc_regs_t * hc_regs,
+-00764                                   dwc_otg_qtd_t * qtd);
+-00765 
+-00766 #ifdef DEBUG
+-00767 
+-00776 #define dwc_sample_frrem(_hcd, _qh, _letter) \
+-00777 { \
+-00778         hfnum_data_t hfnum; \
+-00779         dwc_otg_qtd_t *qtd; \
+-00780         qtd = list_entry(_qh->qtd_list.next, dwc_otg_qtd_t, qtd_list_entry); \
+-00781         if (usb_pipeint(qtd->urb->pipe) && _qh->start_split_frame != 0 && !qtd->complete_split) { \
+-00782                 hfnum.d32 = DWC_READ_REG32(&_hcd->core_if->host_if->host_global_regs->hfnum); \
+-00783                 switch (hfnum.b.frnum & 0x7) { \
+-00784                 case 7: \
+-00785                         _hcd->hfnum_7_samples_##_letter++; \
+-00786                         _hcd->hfnum_7_frrem_accum_##_letter += hfnum.b.frrem; \
+-00787                         break; \
+-00788                 case 0: \
+-00789                         _hcd->hfnum_0_samples_##_letter++; \
+-00790                         _hcd->hfnum_0_frrem_accum_##_letter += hfnum.b.frrem; \
+-00791                         break; \
+-00792                 default: \
+-00793                         _hcd->hfnum_other_samples_##_letter++; \
+-00794                         _hcd->hfnum_other_frrem_accum_##_letter += hfnum.b.frrem; \
+-00795                         break; \
+-00796                 } \
+-00797         } \
+-00798 }
+-00799 #else
+-00800 #define dwc_sample_frrem(_hcd, _qh, _letter)
+-00801 #endif
+-00802 #endif
+-00803 #endif /* DWC_DEVICE_ONLY */
+-
                                                                                Generated on Thu Oct 27 03:56:37 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__hcd_8h.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/dwc__otg__hcd_8h.html 2013-07-26 19:34:41.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,1570 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_hcd.h File Reference +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                dwc_otg_hcd.h File Reference

                                                                                This file contains the structures, constants, and interfaces for the Host Contoller Driver (HCD). More... +-

                                                                                +-#include "dwc_otg_os_dep.h"
                                                                                +-#include "usb.h"
                                                                                +-#include "dwc_otg_hcd_if.h"
                                                                                +-#include "dwc_otg_core_if.h"
                                                                                +-#include "dwc_list.h"
                                                                                +-#include "dwc_otg_cil.h"
                                                                                +- +-

                                                                                +-Go to the source code of this file. +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-

                                                                                Data Structures

                                                                                struct  dwc_otg_hcd_pipe_info
                                                                                struct  dwc_otg_hcd_iso_packet_desc
                                                                                struct  dwc_otg_hcd_urb
                                                                                struct  dwc_otg_qtd
                                                                                 A Queue Transfer Descriptor (QTD) holds the state of a bulk, control, interrupt, or isochronous transfer. More...
                                                                                struct  dwc_otg_qh
                                                                                 A Queue Head (QH) holds the static characteristics of an endpoint and maintains a list of transfers (QTDs) for that endpoint. More...
                                                                                struct  dwc_otg_hcd
                                                                                 This structure holds the state of the HCD, including the non-periodic and periodic schedules. More...
                                                                                union  dwc_otg_hcd::dwc_otg_hcd_internal_flags
                                                                                 Internal DWC HCD Flags. More...

                                                                                Transaction Execution Functions

                                                                                dwc_otg_transaction_type_e dwc_otg_hcd_select_transactions (dwc_otg_hcd_t *hcd)
                                                                                 This function selects transactions from the HCD transfer schedule and assigns them to available host channels.
                                                                                void dwc_otg_hcd_queue_transactions (dwc_otg_hcd_t *hcd, dwc_otg_transaction_type_e tr_type)
                                                                                 This function processes the currently active host channels and queues transactions for these channels to the DWC_otg controller.

                                                                                Interrupt Handler Functions

                                                                                int32_t dwc_otg_hcd_handle_intr (dwc_otg_hcd_t *dwc_otg_hcd)
                                                                                 This function handles interrupts for the HCD.
                                                                                int32_t dwc_otg_hcd_handle_sof_intr (dwc_otg_hcd_t *dwc_otg_hcd)
                                                                                 Handles the start-of-frame interrupt in host mode.
                                                                                int32_t dwc_otg_hcd_handle_rx_status_q_level_intr (dwc_otg_hcd_t *dwc_otg_hcd)
                                                                                 Handles the Rx Status Queue Level Interrupt, which indicates that there is at least one packet in the Rx FIFO.
                                                                                int32_t dwc_otg_hcd_handle_np_tx_fifo_empty_intr (dwc_otg_hcd_t *dwc_otg_hcd)
                                                                                 This interrupt occurs when the non-periodic Tx FIFO is half-empty.
                                                                                int32_t dwc_otg_hcd_handle_perio_tx_fifo_empty_intr (dwc_otg_hcd_t *dwc_otg_hcd)
                                                                                 This interrupt occurs when the periodic Tx FIFO is half-empty.
                                                                                +-int32_t dwc_otg_hcd_handle_incomplete_periodic_intr (dwc_otg_hcd_t *dwc_otg_hcd)
                                                                                int32_t dwc_otg_hcd_handle_port_intr (dwc_otg_hcd_t *dwc_otg_hcd)
                                                                                 There are multiple conditions that can cause a port interrupt.
                                                                                +-int32_t dwc_otg_hcd_handle_conn_id_status_change_intr (dwc_otg_hcd_t *dwc_otg_hcd)
                                                                                +-int32_t dwc_otg_hcd_handle_disconnect_intr (dwc_otg_hcd_t *dwc_otg_hcd)
                                                                                int32_t dwc_otg_hcd_handle_hc_intr (dwc_otg_hcd_t *dwc_otg_hcd)
                                                                                 This interrupt indicates that one or more host channels has a pending interrupt.
                                                                                +-int32_t dwc_otg_hcd_handle_hc_n_intr (dwc_otg_hcd_t *dwc_otg_hcd, uint32_t num)
                                                                                 Handles interrupt for a specific Host Channel.
                                                                                +-int32_t dwc_otg_hcd_handle_session_req_intr (dwc_otg_hcd_t *dwc_otg_hcd)
                                                                                +-int32_t dwc_otg_hcd_handle_wakeup_detected_intr (dwc_otg_hcd_t *dwc_otg_hcd)

                                                                                Schedule Queue Functions

                                                                                dwc_otg_qh_t * dwc_otg_hcd_qh_create (dwc_otg_hcd_t *hcd, dwc_otg_hcd_urb_t *urb, int atomic_alloc)
                                                                                 This function allocates and initializes a QH.
                                                                                void dwc_otg_hcd_qh_free (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
                                                                                 Free each QTD in the QH's QTD-list then free the QH.
                                                                                int dwc_otg_hcd_qh_add (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
                                                                                 This function adds a QH to either the non periodic or periodic schedule if it is not already in the schedule.
                                                                                void dwc_otg_hcd_qh_remove (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
                                                                                 Removes a QH from either the non-periodic or periodic schedule.
                                                                                void dwc_otg_hcd_qh_deactivate (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh, int sched_csplit)
                                                                                 Deactivates a QH.
                                                                                +-void dwc_otg_hcd_qh_remove_and_free (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
                                                                                 Remove and free a QH.
                                                                                dwc_otg_qh_t * dwc_otg_hcd_qh_alloc (int atomic_alloc)
                                                                                 Allocates memory for a QH structure.
                                                                                dwc_otg_qtd_t * dwc_otg_hcd_qtd_create (dwc_otg_hcd_urb_t *urb, int atomic_alloc)
                                                                                 This function allocates and initializes a QTD.
                                                                                void dwc_otg_hcd_qtd_init (dwc_otg_qtd_t *qtd, dwc_otg_hcd_urb_t *urb)
                                                                                 Initializes a QTD structure.
                                                                                int dwc_otg_hcd_qtd_add (dwc_otg_qtd_t *qtd, dwc_otg_hcd_t *dwc_otg_hcd, dwc_otg_qh_t **qh, int atomic_alloc)
                                                                                 This function adds a QTD to the QTD-list of a QH.
                                                                                dwc_otg_qtd_t * dwc_otg_hcd_qtd_alloc (int atomic_alloc)
                                                                                 Allocates memory for a QTD structure.
                                                                                void dwc_otg_hcd_qtd_free (dwc_otg_qtd_t *qtd)
                                                                                 Frees the memory for a QTD structure.
                                                                                void dwc_otg_hcd_qtd_remove (dwc_otg_hcd_t *hcd, dwc_otg_qtd_t *qtd, dwc_otg_qh_t *qh)
                                                                                 Removes a QTD from list.
                                                                                +-void dwc_otg_hcd_qtd_remove_and_free (dwc_otg_hcd_t *hcd, dwc_otg_qtd_t *qtd, dwc_otg_qh_t *qh)
                                                                                 Remove and free a QTD Need to disable IRQ and hold hcd lock while calling this function out of interrupt servicing chain.

                                                                                Descriptor DMA Supporting Functions

                                                                                void dwc_otg_hcd_start_xfer_ddma (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
                                                                                 For Control and Bulk endpoints initializes descriptor list and starts the transfer.
                                                                                void dwc_otg_hcd_complete_xfer_ddma (dwc_otg_hcd_t *hcd, dwc_hc_t *hc, dwc_otg_hc_regs_t *hc_regs, dwc_otg_halt_status_e halt_status)
                                                                                 This function is called from interrupt handlers.
                                                                                int dwc_otg_hcd_qh_init_ddma (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
                                                                                 Initializes a QH structure's Descriptor DMA related members.
                                                                                void dwc_otg_hcd_qh_free_ddma (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
                                                                                 Frees descriptor list memory associated with the QH.

                                                                                Internal Functions

                                                                                +-dwc_otg_qh_t * dwc_urb_to_qh (dwc_otg_hcd_urb_t *urb)

                                                                                Defines

                                                                                +-#define DWC_OTG_HCD_STATUS_BUF_SIZE   64
                                                                                +-#define dwc_list_to_qh(_list_head_ptr_)   container_of(_list_head_ptr_, dwc_otg_qh_t, qh_list_entry)
                                                                                 Gets the QH that contains the list_head.
                                                                                +-#define dwc_list_to_qtd(_list_head_ptr_)   container_of(_list_head_ptr_, dwc_otg_qtd_t, qtd_list_entry)
                                                                                 Gets the QTD that contains the list_head.
                                                                                #define dwc_qh_is_non_per(_qh_ptr_)
                                                                                 Check if QH is non-periodic.
                                                                                +-#define dwc_hb_mult(wMaxPacketSize)   (1 + (((wMaxPacketSize) >> 11) & 0x03))
                                                                                 High bandwidth multiplier as encoded in highspeed endpoint descriptors.
                                                                                +-#define dwc_max_packet(wMaxPacketSize)   ((wMaxPacketSize) & 0x07ff)
                                                                                 Packet size for any kind of endpoint descriptor.
                                                                                +-#define dwc_sample_frrem(_hcd, _qh, _letter)

                                                                                Typedefs

                                                                                +-typedef enum dwc_otg_control_phase dwc_otg_control_phase_e
                                                                                 Phases for control transfers.
                                                                                +-typedef enum dwc_otg_transaction_type dwc_otg_transaction_type_e
                                                                                 Transaction types.
                                                                                typedef dwc_otg_qtd dwc_otg_qtd_t
                                                                                 A Queue Transfer Descriptor (QTD) holds the state of a bulk, control, interrupt, or isochronous transfer.
                                                                                typedef dwc_otg_qh dwc_otg_qh_t
                                                                                 A Queue Head (QH) holds the static characteristics of an endpoint and maintains a list of transfers (QTDs) for that endpoint.

                                                                                Enumerations

                                                                                enum  dwc_otg_control_phase { DWC_OTG_CONTROL_SETUP, +-DWC_OTG_CONTROL_DATA, +-DWC_OTG_CONTROL_STATUS +- }
                                                                                 Phases for control transfers.
                                                                                enum  dwc_otg_transaction_type { DWC_OTG_TRANSACTION_NONE, +-DWC_OTG_TRANSACTION_PERIODIC, +-DWC_OTG_TRANSACTION_NON_PERIODIC, +-DWC_OTG_TRANSACTION_ALL +- }
                                                                                 Transaction types.

                                                                                Functions

                                                                                +-uint8_t dwc_otg_hcd_get_ep_num (struct dwc_otg_hcd_pipe_info *pipe)
                                                                                +-uint8_t dwc_otg_hcd_get_pipe_type (struct dwc_otg_hcd_pipe_info *pipe)
                                                                                +-uint16_t dwc_otg_hcd_get_mps (struct dwc_otg_hcd_pipe_info *pipe)
                                                                                +-uint8_t dwc_otg_hcd_get_dev_addr (struct dwc_otg_hcd_pipe_info *pipe)
                                                                                +-uint8_t dwc_otg_hcd_is_pipe_isoc (struct dwc_otg_hcd_pipe_info *pipe)
                                                                                +-uint8_t dwc_otg_hcd_is_pipe_int (struct dwc_otg_hcd_pipe_info *pipe)
                                                                                +-uint8_t dwc_otg_hcd_is_pipe_bulk (struct dwc_otg_hcd_pipe_info *pipe)
                                                                                +-uint8_t dwc_otg_hcd_is_pipe_control (struct dwc_otg_hcd_pipe_info *pipe)
                                                                                +-uint8_t dwc_otg_hcd_is_pipe_in (struct dwc_otg_hcd_pipe_info *pipe)
                                                                                +-uint8_t dwc_otg_hcd_is_pipe_out (struct dwc_otg_hcd_pipe_info *pipe)
                                                                                +-void dwc_otg_hcd_fill_pipe (struct dwc_otg_hcd_pipe_info *pipe, uint8_t devaddr, uint8_t ep_num, uint8_t pipe_type, uint8_t pipe_dir, uint16_t mps)
                                                                                +- DWC_CIRCLEQ_HEAD (dwc_otg_qtd_list, dwc_otg_qtd)
                                                                                +- DWC_CIRCLEQ_HEAD (hc_list, dwc_hc)
                                                                                int dwc_frame_num_le (uint16_t frame1, uint16_t frame2)
                                                                                 Returns true if _frame1 is less than or equal to _frame2.
                                                                                int dwc_frame_num_gt (uint16_t frame1, uint16_t frame2)
                                                                                 Returns true if _frame1 is greater than _frame2.
                                                                                uint16_t dwc_frame_num_inc (uint16_t frame, uint16_t inc)
                                                                                 Increments _frame by the amount specified by _inc.
                                                                                +-uint16_t dwc_full_frame_num (uint16_t frame)
                                                                                +-uint16_t dwc_micro_frame_num (uint16_t frame)
                                                                                +-void dwc_otg_hcd_save_data_toggle (dwc_hc_t *hc, dwc_otg_hc_regs_t *hc_regs, dwc_otg_qtd_t *qtd)
                                                                                +-

                                                                                Detailed Description

                                                                                +-This file contains the structures, constants, and interfaces for the Host Contoller Driver (HCD). +-

                                                                                +-The Host Controller Driver (HCD) is responsible for translating requests from the USB Driver into the appropriate actions on the DWC_otg controller. It isolates the USBD from the specifics of the controller by providing an API to the USBD. +-

                                                                                +-Definition in file dwc_otg_hcd.h.

                                                                                Define Documentation

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                #define dwc_qh_is_non_per ( _qh_ptr_   ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Value:

                                                                                ((_qh_ptr_->ep_type == UE_BULK) || \
+-                                     (_qh_ptr_->ep_type == UE_CONTROL))
+-
                                                                                Check if QH is non-periodic. +-

                                                                                +- +-

                                                                                +-Definition at line 711 of file dwc_otg_hcd.h.

                                                                                +-

                                                                                Typedef Documentation

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                typedef struct dwc_otg_qtd dwc_otg_qtd_t
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-A Queue Transfer Descriptor (QTD) holds the state of a bulk, control, interrupt, or isochronous transfer. +-

                                                                                +-A single QTD is created for each URB (of one of these types) submitted to the HCD. The transfer associated with a QTD may require one or multiple transactions.

                                                                                +-A QTD is linked to a Queue Head, which is entered in either the non-periodic or periodic schedule for execution. When a QTD is chosen for execution, some or all of its transactions may be executed. After execution, the state of the QTD is updated. The QTD may be retired if all its transactions are complete or if an error occurred. Otherwise, it remains in the schedule so more transactions can be executed later.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                typedef struct dwc_otg_qh dwc_otg_qh_t
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-A Queue Head (QH) holds the static characteristics of an endpoint and maintains a list of transfers (QTDs) for that endpoint. +-

                                                                                +-A QH structure may be entered in either the non-periodic or periodic schedule.

                                                                                +-

                                                                                Function Documentation

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                dwc_otg_transaction_type_e dwc_otg_hcd_select_transactions ( dwc_otg_hcd_t *  hcd  ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This function selects transactions from the HCD transfer schedule and assigns them to available host channels. +-

                                                                                +-It is called from HCD interrupt handler functions.

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +-
                                                                                hcd The HCD state structure.
                                                                                +-
                                                                                +-
                                                                                Returns:
                                                                                The types of new transactions that were assigned to host channels.
                                                                                +- +-

                                                                                +-Definition at line 1168 of file dwc_otg_hcd.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                void dwc_otg_hcd_queue_transactions ( dwc_otg_hcd_t *  hcd,
                                                                                dwc_otg_transaction_type_e  tr_type
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This function processes the currently active host channels and queues transactions for these channels to the DWC_otg controller. +-

                                                                                +-It is called from HCD interrupt handler functions.

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +-
                                                                                hcd The HCD state structure.
                                                                                tr_type The type(s) of transactions to queue (non-periodic, periodic, or both).
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 1540 of file dwc_otg_hcd.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                int32_t dwc_otg_hcd_handle_intr ( dwc_otg_hcd_t *  dwc_otg_hcd  ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This function handles interrupts for the HCD. +-

                                                                                +-

                                                                                Todo:
                                                                                Implement i2cintr handler.
                                                                                +- +-

                                                                                +-Definition at line 43 of file dwc_otg_hcd_intr.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                int32_t dwc_otg_hcd_handle_sof_intr ( dwc_otg_hcd_t *  hcd  ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Handles the start-of-frame interrupt in host mode. +-

                                                                                +-Non-periodic transactions may be queued to the DWC_otg controller for the current (micro)frame. Periodic transactions may be queued to the controller for the next (micro)frame. +-

                                                                                +-Definition at line 175 of file dwc_otg_hcd_intr.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                int32_t dwc_otg_hcd_handle_rx_status_q_level_intr ( dwc_otg_hcd_t *  dwc_otg_hcd  ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Handles the Rx Status Queue Level Interrupt, which indicates that there is at least one packet in the Rx FIFO. +-

                                                                                +-The packets are moved from the FIFO to memory if the DWC_otg controller is operating in Slave mode. +-

                                                                                +-Definition at line 228 of file dwc_otg_hcd_intr.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                int32_t dwc_otg_hcd_handle_np_tx_fifo_empty_intr ( dwc_otg_hcd_t *  dwc_otg_hcd  ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This interrupt occurs when the non-periodic Tx FIFO is half-empty. +-

                                                                                +-More data packets may be written to the FIFO for OUT transfers. More requests may be written to the non-periodic request queue for IN transfers. This interrupt is enabled only in Slave mode. +-

                                                                                +-Definition at line 281 of file dwc_otg_hcd_intr.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                int32_t dwc_otg_hcd_handle_perio_tx_fifo_empty_intr ( dwc_otg_hcd_t *  dwc_otg_hcd  ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This interrupt occurs when the periodic Tx FIFO is half-empty. +-

                                                                                +-More data packets may be written to the FIFO for OUT transfers. More requests may be written to the periodic request queue for IN transfers. This interrupt is enabled only in Slave mode. +-

                                                                                +-Definition at line 293 of file dwc_otg_hcd_intr.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                int32_t dwc_otg_hcd_handle_port_intr ( dwc_otg_hcd_t *  dwc_otg_hcd  ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-There are multiple conditions that can cause a port interrupt. +-

                                                                                +-This function determines which interrupt conditions have occurred and handles them appropriately.

                                                                                +-

                                                                                Todo:
                                                                                  +-
                                                                                • check if steps performed in 'else' block should be perfromed regardles adp
                                                                                +-
                                                                                +-

                                                                                +-Overcurrent Change Interrupt +-

                                                                                +-Definition at line 304 of file dwc_otg_hcd_intr.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                int32_t dwc_otg_hcd_handle_hc_intr ( dwc_otg_hcd_t *  dwc_otg_hcd  ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This interrupt indicates that one or more host channels has a pending interrupt. +-

                                                                                +-There are multiple conditions that can cause each host channel interrupt. This function determines which conditions have occurred for each host channel interrupt and handles them appropriately. +-

                                                                                +-Definition at line 493 of file dwc_otg_hcd_intr.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                dwc_otg_qh_t* dwc_otg_hcd_qh_create ( dwc_otg_hcd_t *  hcd,
                                                                                dwc_otg_hcd_urb_t *  urb,
                                                                                int  atomic_alloc
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This function allocates and initializes a QH. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +- +-
                                                                                hcd The HCD state structure for the DWC OTG controller.
                                                                                urb Holds the information about the device/endpoint that we need to initialize the QH.
                                                                                atomic_alloc Flag to do atomic allocation if needed
                                                                                +-
                                                                                +-
                                                                                Returns:
                                                                                Returns pointer to the newly allocated QH, or NULL on error.
                                                                                +-

                                                                                +-

                                                                                Todo:
                                                                                add memflags argument
                                                                                +- +-

                                                                                +-Definition at line 290 of file dwc_otg_hcd_queue.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                void dwc_otg_hcd_qh_free ( dwc_otg_hcd_t *  hcd,
                                                                                dwc_otg_qh_t *  qh
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Free each QTD in the QH's QTD-list then free the QH. +-

                                                                                +-QH should already be removed from a list. QTD list should already be empty if called from URB Dequeue.

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +-
                                                                                hcd HCD instance.
                                                                                qh The QH to free.
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 53 of file dwc_otg_hcd_queue.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                int dwc_otg_hcd_qh_add ( dwc_otg_hcd_t *  hcd,
                                                                                dwc_otg_qh_t *  qh
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This function adds a QH to either the non periodic or periodic schedule if it is not already in the schedule. +-

                                                                                +-If the QH is already in the schedule, no action is taken.

                                                                                +-

                                                                                Returns:
                                                                                0 if successful, negative error code otherwise.
                                                                                +- +-

                                                                                +-Definition at line 468 of file dwc_otg_hcd_queue.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                void dwc_otg_hcd_qh_remove ( dwc_otg_hcd_t *  hcd,
                                                                                dwc_otg_qh_t *  qh
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Removes a QH from either the non-periodic or periodic schedule. +-

                                                                                +-Memory is not freed.

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +-
                                                                                hcd The HCD state structure.
                                                                                qh QH to remove from schedule.
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 519 of file dwc_otg_hcd_queue.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                void dwc_otg_hcd_qh_deactivate ( dwc_otg_hcd_t *  hcd,
                                                                                dwc_otg_qh_t *  qh,
                                                                                int  sched_next_periodic_split
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Deactivates a QH. +-

                                                                                +-For non-periodic QHs, removes the QH from the active non-periodic schedule. The QH is added to the inactive non-periodic schedule if any QTDs are still attached to the QH.

                                                                                +-For periodic QHs, the QH is removed from the periodic queued schedule. If there are any QTDs still attached to the QH, the QH is added to either the periodic inactive schedule or the periodic ready schedule and its next scheduled frame is calculated. The QH is placed in the ready schedule if the scheduled frame has been reached already. Otherwise it's placed in the inactive schedule. If there are no QTDs attached to the QH, the QH is completely removed from the periodic schedule. +-

                                                                                +-Definition at line 558 of file dwc_otg_hcd_queue.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                dwc_otg_qh_t* dwc_otg_hcd_qh_alloc ( int  atomic_alloc  )  [inline, static]
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Allocates memory for a QH structure. +-

                                                                                +-

                                                                                Returns:
                                                                                Returns the memory allocate or NULL on error.
                                                                                +- +-

                                                                                +-Definition at line 622 of file dwc_otg_hcd.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                dwc_otg_qtd_t* dwc_otg_hcd_qtd_create ( dwc_otg_hcd_urb_t *  urb,
                                                                                int  atomic_alloc
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This function allocates and initializes a QTD. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +-
                                                                                urb The URB to create a QTD from. Each URB-QTD pair will end up pointing to each other so each pair should have a unique correlation.
                                                                                atomic_alloc Flag to do atomic alloc if needed
                                                                                +-
                                                                                +-
                                                                                Returns:
                                                                                Returns pointer to the newly allocated QTD, or NULL on error.
                                                                                +- +-

                                                                                +-Definition at line 638 of file dwc_otg_hcd_queue.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                void dwc_otg_hcd_qtd_init ( dwc_otg_qtd_t *  qtd,
                                                                                dwc_otg_hcd_urb_t *  urb
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Initializes a QTD structure. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +-
                                                                                qtd The QTD to initialize.
                                                                                urb The URB to use for initialization.
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 656 of file dwc_otg_hcd_queue.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                int dwc_otg_hcd_qtd_add ( dwc_otg_qtd_t *  qtd,
                                                                                dwc_otg_hcd_t *  hcd,
                                                                                dwc_otg_qh_t **  qh,
                                                                                int  atomic_alloc
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This function adds a QTD to the QTD-list of a QH. +-

                                                                                +-It will find the correct QH to place the QTD into. If it does not find a QH, then it will create a new QH. If the QH to which the QTD is added is not currently scheduled, it is placed into the proper schedule based on its EP type.

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +- +- +-
                                                                                [in] qtd The QTD to add
                                                                                [in] hcd The DWC HCD structure
                                                                                [out] qh out parameter to return queue head
                                                                                atomic_alloc Flag to do atomic alloc if needed
                                                                                +-
                                                                                +-
                                                                                Returns:
                                                                                0 if successful, negative error code otherwise.
                                                                                +- +-

                                                                                +-Definition at line 694 of file dwc_otg_hcd_queue.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                dwc_otg_qtd_t* dwc_otg_hcd_qtd_alloc ( int  atomic_alloc  )  [inline, static]
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Allocates memory for a QTD structure. +-

                                                                                +-

                                                                                Returns:
                                                                                Returns the memory allocate or NULL on error.
                                                                                +- +-

                                                                                +-Definition at line 638 of file dwc_otg_hcd.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                void dwc_otg_hcd_qtd_free ( dwc_otg_qtd_t *  qtd  )  [inline, static]
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Frees the memory for a QTD structure. +-

                                                                                +-QTD should already be removed from list.

                                                                                Parameters:
                                                                                +- +- +-
                                                                                qtd QTD to free.
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 649 of file dwc_otg_hcd.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                void dwc_otg_hcd_qtd_remove ( dwc_otg_hcd_t *  hcd,
                                                                                dwc_otg_qtd_t *  qtd,
                                                                                dwc_otg_qh_t *  qh
                                                                                )  [inline, static]
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Removes a QTD from list. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +- +-
                                                                                hcd HCD instance.
                                                                                qtd QTD to remove from list.
                                                                                qh QTD belongs to.
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 659 of file dwc_otg_hcd.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                void dwc_otg_hcd_start_xfer_ddma ( dwc_otg_hcd_t *  hcd,
                                                                                dwc_otg_qh_t *  qh
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-For Control and Bulk endpoints initializes descriptor list and starts the transfer. +-

                                                                                +-For Interrupt and Isochronous endpoints initializes descriptor list then updates FrameList, marking appropriate entries as active. In case of Isochronous, the starting descriptor index is calculated based on the scheduled frame, but only on the first transfer descriptor within a session. Then starts the transfer via enabling the channel. For Isochronous endpoint the channel is not halted on XferComplete interrupt so remains assigned to the endpoint(QH) until session is done.

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +-
                                                                                hcd The HCD state structure for the DWC OTG controller.
                                                                                qh The QH to init.
                                                                                +-
                                                                                +-
                                                                                Returns:
                                                                                0 if successful, negative error code otherwise.
                                                                                +- +-

                                                                                +-Definition at line 702 of file dwc_otg_hcd_ddma.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                void dwc_otg_hcd_complete_xfer_ddma ( dwc_otg_hcd_t *  hcd,
                                                                                dwc_hc_t *  hc,
                                                                                dwc_otg_hc_regs_t *  hc_regs,
                                                                                dwc_otg_halt_status_e  halt_status
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This function is called from interrupt handlers. +-

                                                                                +-Scans the descriptor list, updates URB's status and calls completion routine for the URB if it's done. Releases the channel to be used by other transfers. In case of Isochronous endpoint the channel is not halted until the end of the session, i.e. QTD list is empty. If periodic channel released the FrameList is updated accordingly.

                                                                                +-Calls transaction selection routines to activate pending transfers.

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +- +- +-
                                                                                hcd The HCD state structure for the DWC OTG controller.
                                                                                hc Host channel, the transfer is completed on.
                                                                                hc_regs Host channel registers.
                                                                                halt_status Reason the channel is being halted, or just XferComplete for isochronous transfer
                                                                                +-
                                                                                +-

                                                                                +-

                                                                                Todo:
                                                                                Consider the case when period exceeds FrameList size. Frame Rollover interrupt should be used.
                                                                                +- +-

                                                                                +-Definition at line 1062 of file dwc_otg_hcd_ddma.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                int dwc_otg_hcd_qh_init_ddma ( dwc_otg_hcd_t *  hcd,
                                                                                dwc_otg_qh_t *  qh
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Initializes a QH structure's Descriptor DMA related members. +-

                                                                                +-Allocates memory for descriptor list. On first periodic QH, allocates memory for FrameList and enables periodic scheduling.

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +-
                                                                                hcd The HCD state structure for the DWC OTG controller.
                                                                                qh The QH to init.
                                                                                +-
                                                                                +-
                                                                                Returns:
                                                                                0 if successful, negative error code otherwise.
                                                                                +- +-

                                                                                +-Definition at line 312 of file dwc_otg_hcd_ddma.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                void dwc_otg_hcd_qh_free_ddma ( dwc_otg_hcd_t *  hcd,
                                                                                dwc_otg_qh_t *  qh
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Frees descriptor list memory associated with the QH. +-

                                                                                +-If QH is periodic and the last, frees FrameList memory and disables periodic scheduling.

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +-
                                                                                hcd The HCD state structure for the DWC OTG controller.
                                                                                qh The QH to init.
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 346 of file dwc_otg_hcd_ddma.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                int dwc_frame_num_le ( uint16_t  frame1,
                                                                                uint16_t  frame2
                                                                                )  [inline, static]
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Returns true if _frame1 is less than or equal to _frame2. +-

                                                                                +-The comparison is done modulo DWC_HFNUM_MAX_FRNUM. This accounts for the rollover of the frame number when the max frame number is reached. +-

                                                                                +-Definition at line 725 of file dwc_otg_hcd.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                int dwc_frame_num_gt ( uint16_t  frame1,
                                                                                uint16_t  frame2
                                                                                )  [inline, static]
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Returns true if _frame1 is greater than _frame2. +-

                                                                                +-The comparison is done modulo DWC_HFNUM_MAX_FRNUM. This accounts for the rollover of the frame number when the max frame number is reached. +-

                                                                                +-Definition at line 736 of file dwc_otg_hcd.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                uint16_t dwc_frame_num_inc ( uint16_t  frame,
                                                                                uint16_t  inc
                                                                                )  [inline, static]
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Increments _frame by the amount specified by _inc. +-

                                                                                +-The addition is done modulo DWC_HFNUM_MAX_FRNUM. Returns the incremented value. +-

                                                                                +-Definition at line 747 of file dwc_otg_hcd.h.

                                                                                +-

                                                                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__hcd__ddma_8c-source.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/dwc__otg__hcd__ddma_8c-source.html 2013-07-26 19:34:41.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,1074 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_hcd_ddma.c Source File +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                dwc_otg_hcd_ddma.c

                                                                                Go to the documentation of this file.
                                                                                00001 /*==========================================================================
+-00002  * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd_ddma.c $
+-00003  * $Revision: #10 $
+-00004  * $Date: 2011/10/20 $
+-00005  * $Change: 1869464 $
+-00006  *
+-00007  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
+-00008  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
+-00009  * otherwise expressly agreed to in writing between Synopsys and you.
+-00010  *
+-00011  * The Software IS NOT an item of Licensed Software or Licensed Product under
+-00012  * any End User Software License Agreement or Agreement for Licensed Product
+-00013  * with Synopsys or any supplement thereto. You are permitted to use and
+-00014  * redistribute this Software in source and binary forms, with or without
+-00015  * modification, provided that redistributions of source code must retain this
+-00016  * notice. You may not view, use, disclose, copy or distribute this file or
+-00017  * any information contained herein except pursuant to this license grant from
+-00018  * Synopsys. If you do not agree with this notice, including the disclaimer
+-00019  * below, then you are not authorized to use the Software.
+-00020  *
+-00021  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
+-00022  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+-00023  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+-00024  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
+-00025  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+-00026  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+-00027  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+-00028  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+-00029  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+-00030  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+-00031  * DAMAGE.
+-00032  * ========================================================================== */
+-00033 #ifndef DWC_DEVICE_ONLY
+-00034 
+-00039 #include "dwc_otg_hcd.h"
+-00040 #include "dwc_otg_regs.h"
+-00041 
+-00042 static inline uint8_t frame_list_idx(uint16_t frame)
+-00043 {
+-00044         return (frame & (MAX_FRLIST_EN_NUM - 1));
+-00045 }
+-00046 
+-00047 static inline uint16_t desclist_idx_inc(uint16_t idx, uint16_t inc, uint8_t speed)
+-00048 {
+-00049         return (idx + inc) &
+-00050             (((speed ==
+-00051                DWC_OTG_EP_SPEED_HIGH) ? MAX_DMA_DESC_NUM_HS_ISOC :
+-00052               MAX_DMA_DESC_NUM_GENERIC) - 1);
+-00053 }
+-00054 
+-00055 static inline uint16_t desclist_idx_dec(uint16_t idx, uint16_t inc, uint8_t speed)
+-00056 {
+-00057         return (idx - inc) &
+-00058             (((speed ==
+-00059                DWC_OTG_EP_SPEED_HIGH) ? MAX_DMA_DESC_NUM_HS_ISOC :
+-00060               MAX_DMA_DESC_NUM_GENERIC) - 1);
+-00061 }
+-00062 
+-00063 static inline uint16_t max_desc_num(dwc_otg_qh_t * qh)
+-00064 {
+-00065         return (((qh->ep_type == UE_ISOCHRONOUS)
+-00066                  && (qh->dev_speed == DWC_OTG_EP_SPEED_HIGH))
+-00067                 ? MAX_DMA_DESC_NUM_HS_ISOC : MAX_DMA_DESC_NUM_GENERIC);
+-00068 }
+-00069 static inline uint16_t frame_incr_val(dwc_otg_qh_t * qh)
+-00070 {
+-00071         return ((qh->dev_speed == DWC_OTG_EP_SPEED_HIGH)
+-00072                 ? ((qh->interval + 8 - 1) / 8)
+-00073                 : qh->interval);
+-00074 }
+-00075 
+-00076 static int desc_list_alloc(dwc_otg_qh_t * qh)
+-00077 {
+-00078         int retval = 0;
+-00079 
+-00080         qh->desc_list = (dwc_otg_host_dma_desc_t *)
+-00081             DWC_DMA_ALLOC(sizeof(dwc_otg_host_dma_desc_t) * max_desc_num(qh),
+-00082                           &qh->desc_list_dma);
+-00083 
+-00084         if (!qh->desc_list) {
+-00085                 retval = -DWC_E_NO_MEMORY;
+-00086                 DWC_ERROR("%s: DMA descriptor list allocation failed\n", __func__);
+-00087                 
+-00088         }
+-00089 
+-00090         dwc_memset(qh->desc_list, 0x00,
+-00091                    sizeof(dwc_otg_host_dma_desc_t) * max_desc_num(qh));
+-00092 
+-00093         qh->n_bytes =
+-00094             (uint32_t *) DWC_ALLOC(sizeof(uint32_t) * max_desc_num(qh));
+-00095 
+-00096         if (!qh->n_bytes) {
+-00097                 retval = -DWC_E_NO_MEMORY;
+-00098                 DWC_ERROR
+-00099                     ("%s: Failed to allocate array for descriptors' size actual values\n",
+-00100                      __func__);
+-00101 
+-00102         }
+-00103         return retval;
+-00104 
+-00105 }
+-00106 
+-00107 static void desc_list_free(dwc_otg_qh_t * qh)
+-00108 {
+-00109         if (qh->desc_list) {
+-00110                 DWC_DMA_FREE(max_desc_num(qh), qh->desc_list,
+-00111                              qh->desc_list_dma);
+-00112                 qh->desc_list = NULL;
+-00113         }
+-00114 
+-00115         if (qh->n_bytes) {
+-00116                 DWC_FREE(qh->n_bytes);
+-00117                 qh->n_bytes = NULL;
+-00118         }
+-00119 }
+-00120 
+-00121 static int frame_list_alloc(dwc_otg_hcd_t * hcd)
+-00122 {
+-00123         int retval = 0;
+-00124         if (hcd->frame_list)
+-00125                 return 0;
+-00126 
+-00127         hcd->frame_list = DWC_DMA_ALLOC(4 * MAX_FRLIST_EN_NUM,
+-00128                                         &hcd->frame_list_dma);
+-00129         if (!hcd->frame_list) {
+-00130                 retval = -DWC_E_NO_MEMORY;
+-00131                 DWC_ERROR("%s: Frame List allocation failed\n", __func__);
+-00132         }
+-00133 
+-00134         dwc_memset(hcd->frame_list, 0x00, 4 * MAX_FRLIST_EN_NUM);
+-00135 
+-00136         return retval;
+-00137 }
+-00138 
+-00139 static void frame_list_free(dwc_otg_hcd_t * hcd)
+-00140 {
+-00141         if (!hcd->frame_list)
+-00142                 return;
+-00143         
+-00144         DWC_DMA_FREE(4 * MAX_FRLIST_EN_NUM, hcd->frame_list, hcd->frame_list_dma);
+-00145         hcd->frame_list = NULL;
+-00146 }
+-00147 
+-00148 static void per_sched_enable(dwc_otg_hcd_t * hcd, uint16_t fr_list_en)
+-00149 {
+-00150 
+-00151         hcfg_data_t hcfg;
+-00152 
+-00153         hcfg.d32 = DWC_READ_REG32(&hcd->core_if->host_if->host_global_regs->hcfg);
+-00154 
+-00155         if (hcfg.b.perschedena) {
+-00156                 /* already enabled */
+-00157                 return;
+-00158         }
+-00159 
+-00160         DWC_WRITE_REG32(&hcd->core_if->host_if->host_global_regs->hflbaddr,
+-00161                         hcd->frame_list_dma);
+-00162 
+-00163         switch (fr_list_en) {
+-00164         case 64:
+-00165                 hcfg.b.frlisten = 3;
+-00166                 break;
+-00167         case 32:
+-00168                 hcfg.b.frlisten = 2;
+-00169                 break;
+-00170         case 16:
+-00171                 hcfg.b.frlisten = 1;
+-00172                 break;
+-00173         case 8:
+-00174                 hcfg.b.frlisten = 0;
+-00175                 break;
+-00176         default:
+-00177                 break;
+-00178         }
+-00179 
+-00180         hcfg.b.perschedena = 1;
+-00181 
+-00182         DWC_DEBUGPL(DBG_HCD, "Enabling Periodic schedule\n");
+-00183         DWC_WRITE_REG32(&hcd->core_if->host_if->host_global_regs->hcfg, hcfg.d32);
+-00184 
+-00185 }
+-00186 
+-00187 static void per_sched_disable(dwc_otg_hcd_t * hcd)
+-00188 {
+-00189         hcfg_data_t hcfg;
+-00190 
+-00191         hcfg.d32 = DWC_READ_REG32(&hcd->core_if->host_if->host_global_regs->hcfg);
+-00192         
+-00193         if (!hcfg.b.perschedena) {
+-00194                 /* already disabled */
+-00195                 return;
+-00196         }
+-00197         hcfg.b.perschedena = 0;
+-00198 
+-00199         DWC_DEBUGPL(DBG_HCD, "Disabling Periodic schedule\n");
+-00200         DWC_WRITE_REG32(&hcd->core_if->host_if->host_global_regs->hcfg, hcfg.d32);
+-00201 }
+-00202 
+-00203 /* 
+-00204  * Activates/Deactivates FrameList entries for the channel 
+-00205  * based on endpoint servicing period.
+-00206  */
+-00207 void update_frame_list(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh, uint8_t enable)
+-00208 {
+-00209         uint16_t i, j, inc;
+-00210         dwc_hc_t *hc = NULL;
+-00211 
+-00212         if (!qh->channel) {
+-00213                 DWC_ERROR("qh->channel = %p", qh->channel);
+-00214                 return;
+-00215         }
+-00216 
+-00217         if (!hcd) {
+-00218                 DWC_ERROR("------hcd = %p", hcd);
+-00219                 return;
+-00220         }
+-00221 
+-00222         if (!hcd->frame_list) {
+-00223                 DWC_ERROR("-------hcd->frame_list = %p", hcd->frame_list);
+-00224                 return;
+-00225         }
+-00226 
+-00227         hc = qh->channel;
+-00228         inc = frame_incr_val(qh);
+-00229         if (qh->ep_type == UE_ISOCHRONOUS)
+-00230                 i = frame_list_idx(qh->sched_frame);
+-00231         else
+-00232                 i = 0;
+-00233 
+-00234         j = i;
+-00235         do {
+-00236                 if (enable)
+-00237                         hcd->frame_list[j] |= (1 << hc->hc_num);
+-00238                 else
+-00239                         hcd->frame_list[j] &= ~(1 << hc->hc_num);
+-00240                 j = (j + inc) & (MAX_FRLIST_EN_NUM - 1);
+-00241         }
+-00242         while (j != i);
+-00243         if (!enable)
+-00244                 return;
+-00245         hc->schinfo = 0;
+-00246         if (qh->channel->speed == DWC_OTG_EP_SPEED_HIGH) {
+-00247                 j = 1;
+-00248                 /* TODO - check this */
+-00249                 inc = (8 + qh->interval - 1) / qh->interval;
+-00250                 for (i = 0; i < inc; i++) {
+-00251                         hc->schinfo |= j;
+-00252                         j = j << qh->interval;
+-00253                 }
+-00254         } else {
+-00255                 hc->schinfo = 0xff;
+-00256         }
+-00257 }
+-00258 
+-00259 #if 1
+-00260 void dump_frame_list(dwc_otg_hcd_t * hcd)
+-00261 {
+-00262         int i = 0;
+-00263         DWC_PRINTF("--FRAME LIST (hex) --\n");
+-00264         for (i = 0; i < MAX_FRLIST_EN_NUM; i++) {
+-00265                 DWC_PRINTF("%x\t", hcd->frame_list[i]);
+-00266                 if (!(i % 8) && i)
+-00267                         DWC_PRINTF("\n");
+-00268         }
+-00269         DWC_PRINTF("\n----\n");
+-00270 
+-00271 }
+-00272 #endif
+-00273 
+-00274 static void release_channel_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
+-00275 {
+-00276         dwc_hc_t *hc = qh->channel;
+-00277         if (dwc_qh_is_non_per(qh))
+-00278                 hcd->non_periodic_channels--;
+-00279         else
+-00280                 update_frame_list(hcd, qh, 0);
+-00281 
+-00282         /* 
+-00283          * The condition is added to prevent double cleanup try in case of device
+-00284          * disconnect. See channel cleanup in dwc_otg_hcd_disconnect_cb().
+-00285          */
+-00286         if (hc->qh) {
+-00287                 dwc_otg_hc_cleanup(hcd->core_if, hc);
+-00288                 DWC_CIRCLEQ_INSERT_TAIL(&hcd->free_hc_list, hc, hc_list_entry);
+-00289                 hc->qh = NULL;
+-00290         }
+-00291 
+-00292         qh->channel = NULL;
+-00293         qh->ntd = 0;
+-00294 
+-00295         if (qh->desc_list) {
+-00296                 dwc_memset(qh->desc_list, 0x00,
+-00297                            sizeof(dwc_otg_host_dma_desc_t) * max_desc_num(qh));
+-00298         }
+-00299 }
+-00300 
+-00312 int dwc_otg_hcd_qh_init_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
+-00313 {
+-00314         int retval = 0;
+-00315 
+-00316         if (qh->do_split) {
+-00317                 DWC_ERROR("SPLIT Transfers are not supported in Descriptor DMA.\n");
+-00318                 return -1;
+-00319         }
+-00320 
+-00321         retval = desc_list_alloc(qh);
+-00322 
+-00323         if ((retval == 0)
+-00324             && (qh->ep_type == UE_ISOCHRONOUS || qh->ep_type == UE_INTERRUPT)) {
+-00325                 if (!hcd->frame_list) {
+-00326                         retval = frame_list_alloc(hcd);
+-00327                         /* Enable periodic schedule on first periodic QH */
+-00328                         if (retval == 0)
+-00329                                 per_sched_enable(hcd, MAX_FRLIST_EN_NUM);
+-00330                 }
+-00331         }
+-00332 
+-00333         qh->ntd = 0;
+-00334 
+-00335         return retval;
+-00336 }
+-00337 
+-00346 void dwc_otg_hcd_qh_free_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
+-00347 {
+-00348         desc_list_free(qh);
+-00349 
+-00350         /* 
+-00351          * Channel still assigned due to some reasons. 
+-00352          * Seen on Isoc URB dequeue. Channel halted but no subsequent
+-00353          * ChHalted interrupt to release the channel. Afterwards
+-00354          * when it comes here from endpoint disable routine
+-00355          * channel remains assigned.
+-00356          */
+-00357         if (qh->channel)
+-00358                 release_channel_ddma(hcd, qh);
+-00359 
+-00360         if ((qh->ep_type == UE_ISOCHRONOUS || qh->ep_type == UE_INTERRUPT)
+-00361             && !hcd->periodic_channels && hcd->frame_list) {
+-00362 
+-00363                 per_sched_disable(hcd);
+-00364                 frame_list_free(hcd);
+-00365         }
+-00366 }
+-00367 
+-00368 static uint8_t frame_to_desc_idx(dwc_otg_qh_t * qh, uint16_t frame_idx)
+-00369 {
+-00370         if (qh->dev_speed == DWC_OTG_EP_SPEED_HIGH) {
+-00371                 /* 
+-00372                  * Descriptor set(8 descriptors) index
+-00373                  * which is 8-aligned.
+-00374                  */
+-00375                 return (frame_idx & ((MAX_DMA_DESC_NUM_HS_ISOC / 8) - 1)) * 8;
+-00376         } else {
+-00377                 return (frame_idx & (MAX_DMA_DESC_NUM_GENERIC - 1));
+-00378         }
+-00379 }
+-00380 
+-00381 /* 
+-00382  * Determine starting frame for Isochronous transfer. 
+-00383  * Few frames skipped to prevent race condition with HC. 
+-00384  */
+-00385 static uint8_t calc_starting_frame(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh,
+-00386                                    uint8_t * skip_frames)
+-00387 {
+-00388         uint16_t frame = 0;
+-00389         hcd->frame_number = dwc_otg_hcd_get_frame_number(hcd);
+-00390         
+-00391         /* sched_frame is always frame number(not uFrame) both in FS and HS !! */
+-00392         
+-00393         /* 
+-00394          * skip_frames is used to limit activated descriptors number
+-00395          * to avoid the situation when HC services the last activated
+-00396          * descriptor firstly.
+-00397          * Example for FS:
+-00398          * Current frame is 1, scheduled frame is 3. Since HC always fetches the descriptor
+-00399          * corresponding to curr_frame+1, the descriptor corresponding to frame 2
+-00400          * will be fetched. If the number of descriptors is max=64 (or greather) the
+-00401          * list will be fully programmed with Active descriptors and it is possible
+-00402          * case(rare) that the latest descriptor(considering rollback) corresponding
+-00403          * to frame 2 will be serviced first. HS case is more probable because, in fact,
+-00404          * up to 11 uframes(16 in the code) may be skipped.
+-00405          */
+-00406         if (qh->dev_speed == DWC_OTG_EP_SPEED_HIGH) {
+-00407                 /* 
+-00408                  * Consider uframe counter also, to start xfer asap.
+-00409                  * If half of the frame elapsed skip 2 frames otherwise
+-00410                  * just 1 frame. 
+-00411                  * Starting descriptor index must be 8-aligned, so
+-00412                  * if the current frame is near to complete the next one
+-00413                  * is skipped as well.
+-00414                  */
+-00415 
+-00416                 if (dwc_micro_frame_num(hcd->frame_number) >= 5) {
+-00417                         *skip_frames = 2 * 8;
+-00418                         frame = dwc_frame_num_inc(hcd->frame_number, *skip_frames);
+-00419                 } else {
+-00420                         *skip_frames = 1 * 8;
+-00421                         frame = dwc_frame_num_inc(hcd->frame_number, *skip_frames);
+-00422                 }
+-00423 
+-00424                 frame = dwc_full_frame_num(frame);
+-00425         } else {
+-00426                 /* 
+-00427                  * Two frames are skipped for FS - the current and the next.
+-00428                  * But for descriptor programming, 1 frame(descriptor) is enough,
+-00429                  * see example above.
+-00430                  */
+-00431                 *skip_frames = 1;
+-00432                 frame = dwc_frame_num_inc(hcd->frame_number, 2);
+-00433         }
+-00434 
+-00435         return frame;
+-00436 }
+-00437 
+-00438 /* 
+-00439  * Calculate initial descriptor index for isochronous transfer
+-00440  * based on scheduled frame. 
+-00441  */
+-00442 static uint8_t recalc_initial_desc_idx(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
+-00443 {
+-00444         uint16_t frame = 0, fr_idx, fr_idx_tmp;
+-00445         uint8_t skip_frames = 0;
+-00446         /* 
+-00447          * With current ISOC processing algorithm the channel is being
+-00448          * released when no more QTDs in the list(qh->ntd == 0).
+-00449          * Thus this function is called only when qh->ntd == 0 and qh->channel == 0. 
+-00450          *
+-00451          * So qh->channel != NULL branch is not used and just not removed from the
+-00452          * source file. It is required for another possible approach which is,
+-00453          * do not disable and release the channel when ISOC session completed, 
+-00454          * just move QH to inactive schedule until new QTD arrives. 
+-00455          * On new QTD, the QH moved back to 'ready' schedule,
+-00456          * starting frame and therefore starting desc_index are recalculated.
+-00457          * In this case channel is released only on ep_disable.
+-00458          */
+-00459 
+-00460         /* Calculate starting descriptor index. For INTERRUPT endpoint it is always 0. */
+-00461         if (qh->channel) {
+-00462                 frame = calc_starting_frame(hcd, qh, &skip_frames);
+-00463                 /* 
+-00464                  * Calculate initial descriptor index based on FrameList current bitmap
+-00465                  * and servicing period.
+-00466                  */
+-00467                 fr_idx_tmp = frame_list_idx(frame);
+-00468                 fr_idx =
+-00469                     (MAX_FRLIST_EN_NUM + frame_list_idx(qh->sched_frame) -
+-00470                      fr_idx_tmp)
+-00471                     % frame_incr_val(qh);
+-00472                 fr_idx = (fr_idx + fr_idx_tmp) % MAX_FRLIST_EN_NUM;
+-00473         } else {
+-00474                 qh->sched_frame = calc_starting_frame(hcd, qh, &skip_frames);
+-00475                 fr_idx = frame_list_idx(qh->sched_frame);
+-00476         }
+-00477 
+-00478         qh->td_first = qh->td_last = frame_to_desc_idx(qh, fr_idx);
+-00479 
+-00480         return skip_frames;
+-00481 }
+-00482 
+-00483 #define ISOC_URB_GIVEBACK_ASAP
+-00484 
+-00485 #define MAX_ISOC_XFER_SIZE_FS 1023
+-00486 #define MAX_ISOC_XFER_SIZE_HS 3072
+-00487 #define DESCNUM_THRESHOLD 4
+-00488 
+-00489 static void init_isoc_dma_desc(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh,
+-00490                                uint8_t skip_frames)
+-00491 {
+-00492         struct dwc_otg_hcd_iso_packet_desc *frame_desc;
+-00493         dwc_otg_qtd_t *qtd;
+-00494         dwc_otg_host_dma_desc_t *dma_desc;
+-00495         uint16_t idx, inc, n_desc, ntd_max, max_xfer_size;
+-00496 
+-00497         idx = qh->td_last;
+-00498         inc = qh->interval;
+-00499         n_desc = 0;
+-00500 
+-00501         ntd_max = (max_desc_num(qh) + qh->interval - 1) / qh->interval;
+-00502         if (skip_frames && !qh->channel)
+-00503                 ntd_max = ntd_max - skip_frames / qh->interval;
+-00504 
+-00505         max_xfer_size =
+-00506             (qh->dev_speed ==
+-00507              DWC_OTG_EP_SPEED_HIGH) ? MAX_ISOC_XFER_SIZE_HS :
+-00508             MAX_ISOC_XFER_SIZE_FS;
+-00509 
+-00510         DWC_CIRCLEQ_FOREACH(qtd, &qh->qtd_list, qtd_list_entry) {
+-00511                 while ((qh->ntd < ntd_max)
+-00512                        && (qtd->isoc_frame_index_last <
+-00513                            qtd->urb->packet_count)) {
+-00514 
+-00515                         dma_desc = &qh->desc_list[idx];
+-00516                         dwc_memset(dma_desc, 0x00, sizeof(dwc_otg_host_dma_desc_t));
+-00517 
+-00518                         frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index_last];
+-00519 
+-00520                         if (frame_desc->length > max_xfer_size)
+-00521                                 qh->n_bytes[idx] = max_xfer_size;
+-00522                         else
+-00523                                 qh->n_bytes[idx] = frame_desc->length;
+-00524                         dma_desc->status.b_isoc.n_bytes = qh->n_bytes[idx];
+-00525                         dma_desc->status.b_isoc.a = 1;
+-00526                         dma_desc->status.b_isoc.sts = 0;
+-00527 
+-00528                         dma_desc->buf = qtd->urb->dma + frame_desc->offset;
+-00529 
+-00530                         qh->ntd++;
+-00531 
+-00532                         qtd->isoc_frame_index_last++;
+-00533 
+-00534 #ifdef  ISOC_URB_GIVEBACK_ASAP
+-00535                         /* 
+-00536                          * Set IOC for each descriptor corresponding to the 
+-00537                          * last frame of the URB.
+-00538                          */
+-00539                         if (qtd->isoc_frame_index_last ==
+-00540                             qtd->urb->packet_count)
+-00541                                 dma_desc->status.b_isoc.ioc = 1;
+-00542 
+-00543 #endif
+-00544                         idx = desclist_idx_inc(idx, inc, qh->dev_speed);
+-00545                         n_desc++;
+-00546 
+-00547                 }
+-00548                 qtd->in_process = 1;
+-00549         }
+-00550 
+-00551         qh->td_last = idx;
+-00552 
+-00553 #ifdef  ISOC_URB_GIVEBACK_ASAP
+-00554         /* Set IOC for the last descriptor if descriptor list is full */
+-00555         if (qh->ntd == ntd_max) {
+-00556                 idx = desclist_idx_dec(qh->td_last, inc, qh->dev_speed);
+-00557                 qh->desc_list[idx].status.b_isoc.ioc = 1;
+-00558         }
+-00559 #else
+-00560         /* 
+-00561          * Set IOC bit only for one descriptor. 
+-00562          * Always try to be ahead of HW processing,
+-00563          * i.e. on IOC generation driver activates next descriptors but
+-00564          * core continues to process descriptors followed the one with IOC set.
+-00565          */
+-00566 
+-00567         if (n_desc > DESCNUM_THRESHOLD) {
+-00568                 /* 
+-00569                  * Move IOC "up". Required even if there is only one QTD 
+-00570                  * in the list, cause QTDs migth continue to be queued,
+-00571                  * but during the activation it was only one queued.
+-00572                  * Actually more than one QTD might be in the list if this function called 
+-00573                  * from XferCompletion - QTDs was queued during HW processing of the previous
+-00574                  * descriptor chunk.
+-00575                  */
+-00576                 idx = dwc_desclist_idx_dec(idx, inc * ((qh->ntd + 1) / 2), qh->dev_speed);
+-00577         } else {
+-00578                 /* 
+-00579                  * Set the IOC for the latest descriptor
+-00580                  * if either number of descriptor is not greather than threshold
+-00581                  * or no more new descriptors activated.
+-00582                  */
+-00583                 idx = dwc_desclist_idx_dec(qh->td_last, inc, qh->dev_speed);
+-00584         }
+-00585 
+-00586         qh->desc_list[idx].status.b_isoc.ioc = 1;
+-00587 #endif
+-00588 }
+-00589 
+-00590 static void init_non_isoc_dma_desc(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
+-00591 {
+-00592 
+-00593         dwc_hc_t *hc;
+-00594         dwc_otg_host_dma_desc_t *dma_desc;
+-00595         dwc_otg_qtd_t *qtd;
+-00596         int num_packets, len, n_desc = 0;
+-00597 
+-00598         hc = qh->channel;
+-00599 
+-00600         /* 
+-00601          * Start with hc->xfer_buff initialized in 
+-00602          * assign_and_init_hc(), then if SG transfer consists of multiple URBs,
+-00603          * this pointer re-assigned to the buffer of the currently processed QTD.
+-00604          * For non-SG request there is always one QTD active.
+-00605          */
+-00606 
+-00607         DWC_CIRCLEQ_FOREACH(qtd, &qh->qtd_list, qtd_list_entry) {
+-00608 
+-00609                 if (n_desc) {
+-00610                         /* SG request - more than 1 QTDs */
+-00611                         hc->xfer_buff = (uint8_t *)qtd->urb->dma + qtd->urb->actual_length;
+-00612                         hc->xfer_len = qtd->urb->length - qtd->urb->actual_length;
+-00613                 }
+-00614 
+-00615                 qtd->n_desc = 0;
+-00616 
+-00617                 do {
+-00618                         dma_desc = &qh->desc_list[n_desc];
+-00619                         len = hc->xfer_len;
+-00620 
+-00621                         if (len > MAX_DMA_DESC_SIZE)
+-00622                                 len = MAX_DMA_DESC_SIZE - hc->max_packet + 1;
+-00623 
+-00624                         if (hc->ep_is_in) {
+-00625                                 if (len > 0) {
+-00626                                         num_packets = (len + hc->max_packet - 1) / hc->max_packet;
+-00627                                 } else {
+-00628                                         /* Need 1 packet for transfer length of 0. */
+-00629                                         num_packets = 1;
+-00630                                 }
+-00631                                 /* Always program an integral # of max packets for IN transfers. */
+-00632                                 len = num_packets * hc->max_packet;
+-00633                         }
+-00634 
+-00635                         dma_desc->status.b.n_bytes = len;
+-00636 
+-00637                         qh->n_bytes[n_desc] = len;
+-00638 
+-00639                         if ((qh->ep_type == UE_CONTROL)
+-00640                             && (qtd->control_phase == DWC_OTG_CONTROL_SETUP))
+-00641                                 dma_desc->status.b.sup = 1;     /* Setup Packet */
+-00642 
+-00643                         dma_desc->status.b.a = 1;       /* Active descriptor */
+-00644                         dma_desc->status.b.sts = 0;
+-00645 
+-00646                         dma_desc->buf =
+-00647                             ((unsigned long)hc->xfer_buff & 0xffffffff);
+-00648 
+-00649                         /* 
+-00650                          * Last descriptor(or single) of IN transfer 
+-00651                          * with actual size less than MaxPacket.
+-00652                          */
+-00653                         if (len > hc->xfer_len) {
+-00654                                 hc->xfer_len = 0;
+-00655                         } else {
+-00656                                 hc->xfer_buff += len;
+-00657                                 hc->xfer_len -= len;
+-00658                         }
+-00659 
+-00660                         qtd->n_desc++;
+-00661                         n_desc++;
+-00662                 }
+-00663                 while ((hc->xfer_len > 0) && (n_desc != MAX_DMA_DESC_NUM_GENERIC));
+-00664                 
+-00665 
+-00666                 qtd->in_process = 1;
+-00667 
+-00668                 if (qh->ep_type == UE_CONTROL)
+-00669                         break;
+-00670 
+-00671                 if (n_desc == MAX_DMA_DESC_NUM_GENERIC)
+-00672                         break;
+-00673         }
+-00674 
+-00675         if (n_desc) {
+-00676                 /* Request Transfer Complete interrupt for the last descriptor */
+-00677                 qh->desc_list[n_desc - 1].status.b.ioc = 1;
+-00678                 /* End of List indicator */
+-00679                 qh->desc_list[n_desc - 1].status.b.eol = 1;
+-00680 
+-00681                 hc->ntd = n_desc;
+-00682         }
+-00683 }
+-00684 
+-00702 void dwc_otg_hcd_start_xfer_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
+-00703 {
+-00704         /* Channel is already assigned */
+-00705         dwc_hc_t *hc = qh->channel;
+-00706         uint8_t skip_frames = 0;
+-00707 
+-00708         switch (hc->ep_type) {
+-00709         case DWC_OTG_EP_TYPE_CONTROL:
+-00710         case DWC_OTG_EP_TYPE_BULK:
+-00711                 init_non_isoc_dma_desc(hcd, qh);
+-00712 
+-00713                 dwc_otg_hc_start_transfer_ddma(hcd->core_if, hc);
+-00714                 break;
+-00715         case DWC_OTG_EP_TYPE_INTR:
+-00716                 init_non_isoc_dma_desc(hcd, qh);
+-00717 
+-00718                 update_frame_list(hcd, qh, 1);
+-00719 
+-00720                 dwc_otg_hc_start_transfer_ddma(hcd->core_if, hc);
+-00721                 break;
+-00722         case DWC_OTG_EP_TYPE_ISOC:
+-00723 
+-00724                 if (!qh->ntd)
+-00725                         skip_frames = recalc_initial_desc_idx(hcd, qh);
+-00726 
+-00727                 init_isoc_dma_desc(hcd, qh, skip_frames);
+-00728 
+-00729                 if (!hc->xfer_started) {
+-00730 
+-00731                         update_frame_list(hcd, qh, 1);
+-00732 
+-00733                         /* 
+-00734                          * Always set to max, instead of actual size.
+-00735                          * Otherwise ntd will be changed with 
+-00736                          * channel being enabled. Not recommended.
+-00737                          *
+-00738                          */
+-00739                         hc->ntd = max_desc_num(qh);
+-00740                         /* Enable channel only once for ISOC */
+-00741                         dwc_otg_hc_start_transfer_ddma(hcd->core_if, hc);
+-00742                 }
+-00743 
+-00744                 break;
+-00745         default:
+-00746 
+-00747                 break;
+-00748         }
+-00749 }
+-00750 
+-00751 static void complete_isoc_xfer_ddma(dwc_otg_hcd_t * hcd,
+-00752                                     dwc_hc_t * hc,
+-00753                                     dwc_otg_hc_regs_t * hc_regs,
+-00754                                     dwc_otg_halt_status_e halt_status)
+-00755 {
+-00756         struct dwc_otg_hcd_iso_packet_desc *frame_desc;
+-00757         dwc_otg_qtd_t *qtd, *qtd_tmp;
+-00758         dwc_otg_qh_t *qh;
+-00759         dwc_otg_host_dma_desc_t *dma_desc;
+-00760         uint16_t idx, remain;
+-00761         uint8_t urb_compl;
+-00762 
+-00763         qh = hc->qh;
+-00764         idx = qh->td_first;
+-00765 
+-00766         if (hc->halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE) {
+-00767                 DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp, &hc->qh->qtd_list, qtd_list_entry)
+-00768                     qtd->in_process = 0;
+-00769                 return;
+-00770         } else if ((halt_status == DWC_OTG_HC_XFER_AHB_ERR) ||
+-00771                    (halt_status == DWC_OTG_HC_XFER_BABBLE_ERR)) {
+-00772                 /* 
+-00773                  * Channel is halted in these error cases.
+-00774                  * Considered as serious issues.
+-00775                  * Complete all URBs marking all frames as failed, 
+-00776                  * irrespective whether some of the descriptors(frames) succeeded or no.
+-00777                  * Pass error code to completion routine as well, to
+-00778                  * update urb->status, some of class drivers might use it to stop
+-00779                  * queing transfer requests.
+-00780                  */
+-00781                 int err = (halt_status == DWC_OTG_HC_XFER_AHB_ERR)
+-00782                     ? (-DWC_E_IO)
+-00783                     : (-DWC_E_OVERFLOW);
+-00784                                                 
+-00785                 DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp, &hc->qh->qtd_list, qtd_list_entry) {
+-00786                         for (idx = 0; idx < qtd->urb->packet_count; idx++) {
+-00787                                 frame_desc = &qtd->urb->iso_descs[idx];
+-00788                                 frame_desc->status = err;
+-00789                         }
+-00790                         hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, err);
+-00791                         dwc_otg_hcd_qtd_remove_and_free(hcd, qtd, qh);
+-00792                 }
+-00793                 return;
+-00794         }
+-00795 
+-00796         DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp, &hc->qh->qtd_list, qtd_list_entry) {
+-00797 
+-00798                 if (!qtd->in_process)
+-00799                         break;
+-00800 
+-00801                 urb_compl = 0;
+-00802 
+-00803                 do {
+-00804 
+-00805                         dma_desc = &qh->desc_list[idx];
+-00806                         
+-00807                         frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index];
+-00808                         remain = hc->ep_is_in ? dma_desc->status.b_isoc.n_bytes : 0;
+-00809 
+-00810                         if (dma_desc->status.b_isoc.sts == DMA_DESC_STS_PKTERR) {
+-00811                                 /* 
+-00812                                  * XactError or, unable to complete all the transactions 
+-00813                                  * in the scheduled micro-frame/frame, 
+-00814                                  * both indicated by DMA_DESC_STS_PKTERR.
+-00815                                  */
+-00816                                 qtd->urb->error_count++;
+-00817                                 frame_desc->actual_length = qh->n_bytes[idx] - remain;
+-00818                                 frame_desc->status = -DWC_E_PROTOCOL;
+-00819                         } else {
+-00820                                 /* Success */
+-00821                                                                 
+-00822                                 frame_desc->actual_length = qh->n_bytes[idx] - remain;
+-00823                                 frame_desc->status = 0;
+-00824                         }
+-00825 
+-00826                         if (++qtd->isoc_frame_index == qtd->urb->packet_count) {
+-00827                                 /*
+-00828                                  * urb->status is not used for isoc transfers here.
+-00829                                  * The individual frame_desc status are used instead.
+-00830                                  */
+-00831 
+-00832                                 hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, 0);
+-00833                                 dwc_otg_hcd_qtd_remove_and_free(hcd, qtd, qh);
+-00834 
+-00835                                 /* 
+-00836                                  * This check is necessary because urb_dequeue can be called 
+-00837                                  * from urb complete callback(sound driver example).
+-00838                                  * All pending URBs are dequeued there, so no need for
+-00839                                  * further processing.
+-00840                                  */
+-00841                                 if (hc->halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE) {   
+-00842                                         return;
+-00843                                 }
+-00844 
+-00845                                 urb_compl = 1;
+-00846 
+-00847                         }
+-00848 
+-00849                         qh->ntd--;
+-00850 
+-00851                         /* Stop if IOC requested descriptor reached */
+-00852                         if (dma_desc->status.b_isoc.ioc) {
+-00853                                 idx = desclist_idx_inc(idx, qh->interval, hc->speed);   
+-00854                                 goto stop_scan;
+-00855                         }
+-00856 
+-00857                         idx = desclist_idx_inc(idx, qh->interval, hc->speed);
+-00858 
+-00859                         if (urb_compl)
+-00860                                 break;
+-00861                 }
+-00862                 while (idx != qh->td_first);
+-00863         }
+-00864 stop_scan:
+-00865         qh->td_first = idx;
+-00866 }
+-00867 
+-00868 uint8_t update_non_isoc_urb_state_ddma(dwc_otg_hcd_t * hcd,
+-00869                                        dwc_hc_t * hc,
+-00870                                        dwc_otg_qtd_t * qtd,
+-00871                                        dwc_otg_host_dma_desc_t * dma_desc,
+-00872                                        dwc_otg_halt_status_e halt_status,
+-00873                                        uint32_t n_bytes, uint8_t * xfer_done)
+-00874 {
+-00875 
+-00876         uint16_t remain = hc->ep_is_in ? dma_desc->status.b.n_bytes : 0;
+-00877         dwc_otg_hcd_urb_t *urb = qtd->urb;
+-00878 
+-00879         if (halt_status == DWC_OTG_HC_XFER_AHB_ERR) {
+-00880                 urb->status = -DWC_E_IO;
+-00881                 return 1;
+-00882         }
+-00883         if (dma_desc->status.b.sts == DMA_DESC_STS_PKTERR) {
+-00884                 switch (halt_status) {
+-00885                 case DWC_OTG_HC_XFER_STALL:
+-00886                         urb->status = -DWC_E_PIPE;
+-00887                         break;
+-00888                 case DWC_OTG_HC_XFER_BABBLE_ERR:
+-00889                         urb->status = -DWC_E_OVERFLOW;
+-00890                         break;
+-00891                 case DWC_OTG_HC_XFER_XACT_ERR:
+-00892                         urb->status = -DWC_E_PROTOCOL;
+-00893                         break;
+-00894                 default:        
+-00895                         DWC_ERROR("%s: Unhandled descriptor error status (%d)\n", __func__,
+-00896                                   halt_status);
+-00897                         break;
+-00898                 }
+-00899                 return 1;
+-00900         }
+-00901 
+-00902         if (dma_desc->status.b.a == 1) {
+-00903                 DWC_DEBUGPL(DBG_HCDV,
+-00904                             "Active descriptor encountered on channel %d\n",
+-00905                             hc->hc_num);
+-00906                 return 0;
+-00907         }
+-00908 
+-00909         if (hc->ep_type == DWC_OTG_EP_TYPE_CONTROL) {
+-00910                 if (qtd->control_phase == DWC_OTG_CONTROL_DATA) {
+-00911                         urb->actual_length += n_bytes - remain;
+-00912                         if (remain || urb->actual_length == urb->length) {
+-00913                                 /* 
+-00914                                  * For Control Data stage do not set urb->status=0 to prevent
+-00915                                  * URB callback. Set it when Status phase done. See below.
+-00916                                  */
+-00917                                 *xfer_done = 1;
+-00918                         }
+-00919 
+-00920                 } else if (qtd->control_phase == DWC_OTG_CONTROL_STATUS) {
+-00921                         urb->status = 0;
+-00922                         *xfer_done = 1;
+-00923                 }
+-00924                 /* No handling for SETUP stage */
+-00925         } else {
+-00926                 /* BULK and INTR */
+-00927                 urb->actual_length += n_bytes - remain;
+-00928                 if (remain || urb->actual_length == urb->length) {
+-00929                         urb->status = 0;
+-00930                         *xfer_done = 1;
+-00931                 }
+-00932         }
+-00933 
+-00934         return 0;
+-00935 }
+-00936 
+-00937 static void complete_non_isoc_xfer_ddma(dwc_otg_hcd_t * hcd,
+-00938                                         dwc_hc_t * hc,
+-00939                                         dwc_otg_hc_regs_t * hc_regs,
+-00940                                         dwc_otg_halt_status_e halt_status)
+-00941 {
+-00942         dwc_otg_hcd_urb_t *urb = NULL;
+-00943         dwc_otg_qtd_t *qtd, *qtd_tmp;
+-00944         dwc_otg_qh_t *qh;
+-00945         dwc_otg_host_dma_desc_t *dma_desc;
+-00946         uint32_t n_bytes, n_desc, i;
+-00947         uint8_t failed = 0, xfer_done;
+-00948 
+-00949         n_desc = 0;
+-00950 
+-00951         qh = hc->qh;
+-00952 
+-00953         if (hc->halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE) {
+-00954                 DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp, &hc->qh->qtd_list, qtd_list_entry) {
+-00955                         qtd->in_process = 0;
+-00956                 }
+-00957                 return;
+-00958         }
+-00959 
+-00960         DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp, &qh->qtd_list, qtd_list_entry) {
+-00961 
+-00962                 urb = qtd->urb;
+-00963 
+-00964                 n_bytes = 0;
+-00965                 xfer_done = 0;
+-00966 
+-00967                 for (i = 0; i < qtd->n_desc; i++) {
+-00968                         dma_desc = &qh->desc_list[n_desc];
+-00969 
+-00970                         n_bytes = qh->n_bytes[n_desc];
+-00971 
+-00972                         failed =
+-00973                             update_non_isoc_urb_state_ddma(hcd, hc, qtd,
+-00974                                                            dma_desc,
+-00975                                                            halt_status, n_bytes,
+-00976                                                            &xfer_done);
+-00977 
+-00978                         if (failed
+-00979                             || (xfer_done
+-00980                                 && (urb->status != -DWC_E_IN_PROGRESS))) {
+-00981 
+-00982                                 hcd->fops->complete(hcd, urb->priv, urb,
+-00983                                                     urb->status);
+-00984                                 dwc_otg_hcd_qtd_remove_and_free(hcd, qtd, qh);
+-00985 
+-00986                                 if (failed)
+-00987                                         goto stop_scan;
+-00988                         } else if (qh->ep_type == UE_CONTROL) {
+-00989                                 if (qtd->control_phase == DWC_OTG_CONTROL_SETUP) {
+-00990                                         if (urb->length > 0) {
+-00991                                                 qtd->control_phase = DWC_OTG_CONTROL_DATA;
+-00992                                         } else {
+-00993                                                 qtd->control_phase = DWC_OTG_CONTROL_STATUS;
+-00994                                         }
+-00995                                         DWC_DEBUGPL(DBG_HCDV, "  Control setup transaction done\n");
+-00996                                 } else if (qtd->control_phase == DWC_OTG_CONTROL_DATA) {
+-00997                                         if (xfer_done) {
+-00998                                                 qtd->control_phase = DWC_OTG_CONTROL_STATUS;
+-00999                                                 DWC_DEBUGPL(DBG_HCDV, "  Control data transfer done\n");
+-01000                                         } else if (i + 1 == qtd->n_desc) {
+-01001                                                 /* 
+-01002                                                  * Last descriptor for Control data stage which is
+-01003                                                  * not completed yet.
+-01004                                                  */
+-01005                                                 dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
+-01006                                         }
+-01007                                 }
+-01008                         }
+-01009 
+-01010                         n_desc++;
+-01011                 }
+-01012 
+-01013         }
+-01014 
+-01015 stop_scan:
+-01016 
+-01017         if (qh->ep_type != UE_CONTROL) {
+-01018                 /* 
+-01019                  * Resetting the data toggle for bulk
+-01020                  * and interrupt endpoints in case of stall. See handle_hc_stall_intr() 
+-01021                  */
+-01022                 if (halt_status == DWC_OTG_HC_XFER_STALL)
+-01023                         qh->data_toggle = DWC_OTG_HC_PID_DATA0;
+-01024                 else
+-01025                         dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
+-01026         }
+-01027 
+-01028         if (halt_status == DWC_OTG_HC_XFER_COMPLETE) {
+-01029                 hcint_data_t hcint;
+-01030                 hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
+-01031                 if (hcint.b.nyet) {
+-01032                         /*
+-01033                          * Got a NYET on the last transaction of the transfer. It
+-01034                          * means that the endpoint should be in the PING state at the
+-01035                          * beginning of the next transfer.
+-01036                          */
+-01037                         qh->ping_state = 1;
+-01038                         clear_hc_int(hc_regs, nyet);
+-01039                 }
+-01040 
+-01041         }
+-01042 
+-01043 }
+-01044 
+-01062 void dwc_otg_hcd_complete_xfer_ddma(dwc_otg_hcd_t * hcd,
+-01063                                     dwc_hc_t * hc,
+-01064                                     dwc_otg_hc_regs_t * hc_regs,
+-01065                                     dwc_otg_halt_status_e halt_status)
+-01066 {
+-01067         uint8_t continue_isoc_xfer = 0;
+-01068         dwc_otg_transaction_type_e tr_type;
+-01069         dwc_otg_qh_t *qh = hc->qh;
+-01070 
+-01071         if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
+-01072 
+-01073                 complete_isoc_xfer_ddma(hcd, hc, hc_regs, halt_status);
+-01074 
+-01075                 /* Release the channel if halted or session completed */
+-01076                 if (halt_status != DWC_OTG_HC_XFER_COMPLETE ||
+-01077                     DWC_CIRCLEQ_EMPTY(&qh->qtd_list)) {
+-01078 
+-01079                         /* Halt the channel if session completed */
+-01080                         if (halt_status == DWC_OTG_HC_XFER_COMPLETE) {
+-01081                                 dwc_otg_hc_halt(hcd->core_if, hc, halt_status);
+-01082                         }
+-01083 
+-01084                         release_channel_ddma(hcd, qh);
+-01085                         dwc_otg_hcd_qh_remove(hcd, qh);
+-01086                 } else {
+-01087                         /* Keep in assigned schedule to continue transfer */
+-01088                         DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_assigned,
+-01089                                            &qh->qh_list_entry);
+-01090                         continue_isoc_xfer = 1;
+-01091 
+-01092                 }
+-01096         } else {
+-01097                 /* Scan descriptor list to complete the URB(s), then release the channel */
+-01098                 complete_non_isoc_xfer_ddma(hcd, hc, hc_regs, halt_status);
+-01099 
+-01100                 release_channel_ddma(hcd, qh);
+-01101                 dwc_otg_hcd_qh_remove(hcd, qh);
+-01102 
+-01103                 if (!DWC_CIRCLEQ_EMPTY(&qh->qtd_list)) {
+-01104                         /* Add back to inactive non-periodic schedule on normal completion */
+-01105                         dwc_otg_hcd_qh_add(hcd, qh);
+-01106                 }
+-01107 
+-01108         }
+-01109         tr_type = dwc_otg_hcd_select_transactions(hcd);
+-01110         if (tr_type != DWC_OTG_TRANSACTION_NONE || continue_isoc_xfer) {
+-01111                 if (continue_isoc_xfer) {
+-01112                         if (tr_type == DWC_OTG_TRANSACTION_NONE) {
+-01113                                 tr_type = DWC_OTG_TRANSACTION_PERIODIC;
+-01114                         } else if (tr_type == DWC_OTG_TRANSACTION_NON_PERIODIC) {
+-01115                                 tr_type = DWC_OTG_TRANSACTION_ALL;
+-01116                         }
+-01117                 }
+-01118                 dwc_otg_hcd_queue_transactions(hcd, tr_type);
+-01119         }
+-01120 }
+-01121 
+-01122 #endif /* DWC_DEVICE_ONLY */
+-
                                                                                Generated on Thu Oct 27 03:56:37 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__hcd__ddma_8c.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/dwc__otg__hcd__ddma_8c.html 2013-07-26 19:34:41.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,330 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_hcd_ddma.c File Reference +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                dwc_otg_hcd_ddma.c File Reference

                                                                                This file contains Descriptor DMA support implementation for host mode. More... +-

                                                                                +-#include "dwc_otg_hcd.h"
                                                                                +-#include "dwc_otg_regs.h"
                                                                                +- +-

                                                                                +-Go to the source code of this file. +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-

                                                                                Defines

                                                                                +-#define ISOC_URB_GIVEBACK_ASAP
                                                                                +-#define MAX_ISOC_XFER_SIZE_FS   1023
                                                                                +-#define MAX_ISOC_XFER_SIZE_HS   3072
                                                                                +-#define DESCNUM_THRESHOLD   4

                                                                                Functions

                                                                                +-uint8_t frame_list_idx (uint16_t frame)
                                                                                +-uint16_t desclist_idx_inc (uint16_t idx, uint16_t inc, uint8_t speed)
                                                                                +-uint16_t desclist_idx_dec (uint16_t idx, uint16_t inc, uint8_t speed)
                                                                                +-uint16_t max_desc_num (dwc_otg_qh_t *qh)
                                                                                +-uint16_t frame_incr_val (dwc_otg_qh_t *qh)
                                                                                +-int desc_list_alloc (dwc_otg_qh_t *qh)
                                                                                +-void desc_list_free (dwc_otg_qh_t *qh)
                                                                                +-int frame_list_alloc (dwc_otg_hcd_t *hcd)
                                                                                +-void frame_list_free (dwc_otg_hcd_t *hcd)
                                                                                +-void per_sched_enable (dwc_otg_hcd_t *hcd, uint16_t fr_list_en)
                                                                                +-void per_sched_disable (dwc_otg_hcd_t *hcd)
                                                                                +-void update_frame_list (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh, uint8_t enable)
                                                                                +-void dump_frame_list (dwc_otg_hcd_t *hcd)
                                                                                +-void release_channel_ddma (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
                                                                                int dwc_otg_hcd_qh_init_ddma (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
                                                                                 Initializes a QH structure's Descriptor DMA related members.
                                                                                void dwc_otg_hcd_qh_free_ddma (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
                                                                                 Frees descriptor list memory associated with the QH.
                                                                                +-uint8_t frame_to_desc_idx (dwc_otg_qh_t *qh, uint16_t frame_idx)
                                                                                +-uint8_t calc_starting_frame (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh, uint8_t *skip_frames)
                                                                                +-uint8_t recalc_initial_desc_idx (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
                                                                                +-void init_isoc_dma_desc (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh, uint8_t skip_frames)
                                                                                +-void init_non_isoc_dma_desc (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
                                                                                void dwc_otg_hcd_start_xfer_ddma (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
                                                                                 For Control and Bulk endpoints initializes descriptor list and starts the transfer.
                                                                                +-void complete_isoc_xfer_ddma (dwc_otg_hcd_t *hcd, dwc_hc_t *hc, dwc_otg_hc_regs_t *hc_regs, dwc_otg_halt_status_e halt_status)
                                                                                +-uint8_t update_non_isoc_urb_state_ddma (dwc_otg_hcd_t *hcd, dwc_hc_t *hc, dwc_otg_qtd_t *qtd, dwc_otg_host_dma_desc_t *dma_desc, dwc_otg_halt_status_e halt_status, uint32_t n_bytes, uint8_t *xfer_done)
                                                                                +-void complete_non_isoc_xfer_ddma (dwc_otg_hcd_t *hcd, dwc_hc_t *hc, dwc_otg_hc_regs_t *hc_regs, dwc_otg_halt_status_e halt_status)
                                                                                void dwc_otg_hcd_complete_xfer_ddma (dwc_otg_hcd_t *hcd, dwc_hc_t *hc, dwc_otg_hc_regs_t *hc_regs, dwc_otg_halt_status_e halt_status)
                                                                                 This function is called from interrupt handlers.
                                                                                +-

                                                                                Detailed Description

                                                                                +-This file contains Descriptor DMA support implementation for host mode. +-

                                                                                +- +-

                                                                                +-Definition in file dwc_otg_hcd_ddma.c.

                                                                                Function Documentation

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                int dwc_otg_hcd_qh_init_ddma ( dwc_otg_hcd_t *  hcd,
                                                                                dwc_otg_qh_t *  qh
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Initializes a QH structure's Descriptor DMA related members. +-

                                                                                +-Allocates memory for descriptor list. On first periodic QH, allocates memory for FrameList and enables periodic scheduling.

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +-
                                                                                hcd The HCD state structure for the DWC OTG controller.
                                                                                qh The QH to init.
                                                                                +-
                                                                                +-
                                                                                Returns:
                                                                                0 if successful, negative error code otherwise.
                                                                                +- +-

                                                                                +-Definition at line 312 of file dwc_otg_hcd_ddma.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                void dwc_otg_hcd_qh_free_ddma ( dwc_otg_hcd_t *  hcd,
                                                                                dwc_otg_qh_t *  qh
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Frees descriptor list memory associated with the QH. +-

                                                                                +-If QH is periodic and the last, frees FrameList memory and disables periodic scheduling.

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +-
                                                                                hcd The HCD state structure for the DWC OTG controller.
                                                                                qh The QH to init.
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 346 of file dwc_otg_hcd_ddma.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                void dwc_otg_hcd_start_xfer_ddma ( dwc_otg_hcd_t *  hcd,
                                                                                dwc_otg_qh_t *  qh
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-For Control and Bulk endpoints initializes descriptor list and starts the transfer. +-

                                                                                +-For Interrupt and Isochronous endpoints initializes descriptor list then updates FrameList, marking appropriate entries as active. In case of Isochronous, the starting descriptor index is calculated based on the scheduled frame, but only on the first transfer descriptor within a session. Then starts the transfer via enabling the channel. For Isochronous endpoint the channel is not halted on XferComplete interrupt so remains assigned to the endpoint(QH) until session is done.

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +-
                                                                                hcd The HCD state structure for the DWC OTG controller.
                                                                                qh The QH to init.
                                                                                +-
                                                                                +-
                                                                                Returns:
                                                                                0 if successful, negative error code otherwise.
                                                                                +- +-

                                                                                +-Definition at line 702 of file dwc_otg_hcd_ddma.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                void dwc_otg_hcd_complete_xfer_ddma ( dwc_otg_hcd_t *  hcd,
                                                                                dwc_hc_t *  hc,
                                                                                dwc_otg_hc_regs_t *  hc_regs,
                                                                                dwc_otg_halt_status_e  halt_status
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This function is called from interrupt handlers. +-

                                                                                +-Scans the descriptor list, updates URB's status and calls completion routine for the URB if it's done. Releases the channel to be used by other transfers. In case of Isochronous endpoint the channel is not halted until the end of the session, i.e. QTD list is empty. If periodic channel released the FrameList is updated accordingly.

                                                                                +-Calls transaction selection routines to activate pending transfers.

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +- +- +-
                                                                                hcd The HCD state structure for the DWC OTG controller.
                                                                                hc Host channel, the transfer is completed on.
                                                                                hc_regs Host channel registers.
                                                                                halt_status Reason the channel is being halted, or just XferComplete for isochronous transfer
                                                                                +-
                                                                                +-

                                                                                +-

                                                                                Todo:
                                                                                Consider the case when period exceeds FrameList size. Frame Rollover interrupt should be used.
                                                                                +- +-

                                                                                +-Definition at line 1062 of file dwc_otg_hcd_ddma.c.

                                                                                +-

                                                                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__hcd__if_8h-source.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/dwc__otg__hcd__if_8h-source.html 2013-07-26 19:34:41.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,192 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_hcd_if.h Source File +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                dwc_otg_hcd_if.h

                                                                                Go to the documentation of this file.
                                                                                00001 /* ==========================================================================
+-00002  * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd_if.h $
+-00003  * $Revision: #12 $
+-00004  * $Date: 2011/10/26 $
+-00005  * $Change: 1873028 $
+-00006  *
+-00007  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
+-00008  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
+-00009  * otherwise expressly agreed to in writing between Synopsys and you.
+-00010  *
+-00011  * The Software IS NOT an item of Licensed Software or Licensed Product under
+-00012  * any End User Software License Agreement or Agreement for Licensed Product
+-00013  * with Synopsys or any supplement thereto. You are permitted to use and
+-00014  * redistribute this Software in source and binary forms, with or without
+-00015  * modification, provided that redistributions of source code must retain this
+-00016  * notice. You may not view, use, disclose, copy or distribute this file or
+-00017  * any information contained herein except pursuant to this license grant from
+-00018  * Synopsys. If you do not agree with this notice, including the disclaimer
+-00019  * below, then you are not authorized to use the Software.
+-00020  *
+-00021  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
+-00022  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+-00023  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+-00024  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
+-00025  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+-00026  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+-00027  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+-00028  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+-00029  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+-00030  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+-00031  * DAMAGE.
+-00032  * ========================================================================== */
+-00033 #ifndef DWC_DEVICE_ONLY
+-00034 #ifndef __DWC_HCD_IF_H__
+-00035 #define __DWC_HCD_IF_H__
+-00036 
+-00037 #include "dwc_otg_core_if.h"
+-00038 
+-00043 struct dwc_otg_hcd;
+-00044 typedef struct dwc_otg_hcd dwc_otg_hcd_t;
+-00045 
+-00046 struct dwc_otg_hcd_urb;
+-00047 typedef struct dwc_otg_hcd_urb dwc_otg_hcd_urb_t;
+-00048 
+-00053 typedef int (*dwc_otg_hcd_start_cb_t) (dwc_otg_hcd_t * hcd);
+-00054 
+-00056 typedef int (*dwc_otg_hcd_disconnect_cb_t) (dwc_otg_hcd_t * hcd);
+-00057 
+-00059 typedef int (*dwc_otg_hcd_hub_info_from_urb_cb_t) (dwc_otg_hcd_t * hcd,
+-00060                                                    void *urb_handle,
+-00061                                                    uint32_t * hub_addr,
+-00062                                                    uint32_t * port_addr);
+-00064 typedef int (*dwc_otg_hcd_speed_from_urb_cb_t) (dwc_otg_hcd_t * hcd,
+-00065                                                 void *urb_handle);
+-00066 
+-00068 typedef int (*dwc_otg_hcd_complete_urb_cb_t) (dwc_otg_hcd_t * hcd,
+-00069                                               void *urb_handle,
+-00070                                               dwc_otg_hcd_urb_t * dwc_otg_urb,
+-00071                                               int32_t status);
+-00072 
+-00074 typedef int (*dwc_otg_hcd_get_b_hnp_enable) (dwc_otg_hcd_t * hcd);
+-00075 
+-00076 struct dwc_otg_hcd_function_ops {
+-00077         dwc_otg_hcd_start_cb_t start;
+-00078         dwc_otg_hcd_disconnect_cb_t disconnect;
+-00079         dwc_otg_hcd_hub_info_from_urb_cb_t hub_info;
+-00080         dwc_otg_hcd_speed_from_urb_cb_t speed;
+-00081         dwc_otg_hcd_complete_urb_cb_t complete;
+-00082         dwc_otg_hcd_get_b_hnp_enable get_b_hnp_enable;
+-00083 };
+-00089 extern dwc_otg_hcd_t *dwc_otg_hcd_alloc_hcd(void);
+-00090 
+-00099 extern int dwc_otg_hcd_init(dwc_otg_hcd_t * hcd, dwc_otg_core_if_t * core_if);
+-00100 
+-00105 extern void dwc_otg_hcd_remove(dwc_otg_hcd_t * hcd);
+-00106 
+-00114 extern int32_t dwc_otg_hcd_handle_intr(dwc_otg_hcd_t * dwc_otg_hcd);
+-00115 
+-00122 extern void *dwc_otg_hcd_get_priv_data(dwc_otg_hcd_t * hcd);
+-00123 
+-00130 extern void dwc_otg_hcd_set_priv_data(dwc_otg_hcd_t * hcd, void *priv_data);
+-00131 
+-00141 extern int dwc_otg_hcd_start(dwc_otg_hcd_t * hcd,
+-00142                              struct dwc_otg_hcd_function_ops *fops);
+-00143 
+-00150 extern void dwc_otg_hcd_stop(dwc_otg_hcd_t * hcd);
+-00151 
+-00165 extern int dwc_otg_hcd_hub_control(dwc_otg_hcd_t * dwc_otg_hcd,
+-00166                                    uint16_t typeReq, uint16_t wValue,
+-00167                                    uint16_t wIndex, uint8_t * buf,
+-00168                                    uint16_t wLength);
+-00169 
+-00175 extern uint32_t dwc_otg_hcd_otg_port(dwc_otg_hcd_t * hcd);
+-00176 
+-00182 extern uint16_t dwc_otg_get_otg_version(dwc_otg_core_if_t * core_if);
+-00183 
+-00189 extern uint32_t dwc_otg_hcd_is_b_host(dwc_otg_hcd_t * hcd);
+-00190 
+-00196 extern int dwc_otg_hcd_get_frame_number(dwc_otg_hcd_t * hcd);
+-00197 
+-00203 extern void dwc_otg_hcd_dump_state(dwc_otg_hcd_t * hcd);
+-00204 
+-00213 extern void dwc_otg_hcd_dump_frrem(dwc_otg_hcd_t * hcd);
+-00214 
+-00226 extern int dwc_otg_hcd_send_lpm(dwc_otg_hcd_t * hcd, uint8_t devaddr,
+-00227                                 uint8_t hird, uint8_t bRemoteWake);
+-00228 
+-00229 /* URB interface */
+-00230 
+-00239 extern dwc_otg_hcd_urb_t *dwc_otg_hcd_urb_alloc(dwc_otg_hcd_t * hcd,
+-00240                                                 int iso_desc_count,
+-00241                                                 int atomic_alloc);
+-00242 
+-00253 extern void dwc_otg_hcd_urb_set_pipeinfo(dwc_otg_hcd_urb_t * hcd_urb,
+-00254                                          uint8_t devaddr, uint8_t ep_num,
+-00255                                          uint8_t ep_type, uint8_t ep_dir,
+-00256                                          uint16_t mps);
+-00257 
+-00258 /* Transfer flags */
+-00259 #define URB_GIVEBACK_ASAP 0x1
+-00260 #define URB_SEND_ZERO_PACKET 0x2
+-00261 
+-00276 extern void dwc_otg_hcd_urb_set_params(dwc_otg_hcd_urb_t * urb,
+-00277                                        void *urb_handle, void *buf,
+-00278                                        dwc_dma_t dma, uint32_t buflen, void *sp,
+-00279                                        dwc_dma_t sp_dma, uint32_t flags,
+-00280                                        uint16_t interval);
+-00281 
+-00286 extern uint32_t dwc_otg_hcd_urb_get_status(dwc_otg_hcd_urb_t * dwc_otg_urb);
+-00287 
+-00292 extern uint32_t dwc_otg_hcd_urb_get_actual_length(dwc_otg_hcd_urb_t *
+-00293                                                   dwc_otg_urb);
+-00294 
+-00299 extern uint32_t dwc_otg_hcd_urb_get_error_count(dwc_otg_hcd_urb_t *
+-00300                                                 dwc_otg_urb);
+-00301 
+-00309 extern void dwc_otg_hcd_urb_set_iso_desc_params(dwc_otg_hcd_urb_t * dwc_otg_urb,
+-00310                                                 int desc_num, uint32_t offset,
+-00311                                                 uint32_t length);
+-00312 
+-00318 extern uint32_t dwc_otg_hcd_urb_get_iso_desc_status(dwc_otg_hcd_urb_t *
+-00319                                                     dwc_otg_urb, int desc_num);
+-00320 
+-00326 extern uint32_t dwc_otg_hcd_urb_get_iso_desc_actual_length(dwc_otg_hcd_urb_t *
+-00327                                                            dwc_otg_urb,
+-00328                                                            int desc_num);
+-00329 
+-00341 extern int dwc_otg_hcd_urb_enqueue(dwc_otg_hcd_t * dwc_otg_hcd,
+-00342                                    dwc_otg_hcd_urb_t * dwc_otg_urb,
+-00343                                    void **ep_handle, int atomic_alloc);
+-00344 
+-00350 extern int dwc_otg_hcd_urb_dequeue(dwc_otg_hcd_t * dwc_otg_hcd,
+-00351                                    dwc_otg_hcd_urb_t * dwc_otg_urb);
+-00352 
+-00363 extern int dwc_otg_hcd_endpoint_disable(dwc_otg_hcd_t * hcd, void *ep_handle,
+-00364                                         int retry);
+-00365 
+-00366 /* Resets the data toggle in qh structure. This function can be called from
+-00367  * usb_clear_halt routine.
+-00368  *
+-00369  * @param hcd The HCD
+-00370  * @param ep_handle Endpoint handle, returned by dwc_otg_hcd_urb_enqueue function
+-00371  *
+-00372  * Returns -DWC_E_INVALID if invalid arguments are passed.
+-00373  * Returns 0 on success
+-00374  */
+-00375 extern int dwc_otg_hcd_endpoint_reset(dwc_otg_hcd_t * hcd, void *ep_handle);
+-00376 
+-00382 extern int dwc_otg_hcd_is_status_changed(dwc_otg_hcd_t * hcd, int port);
+-00383 
+-00390 extern int dwc_otg_hcd_is_bandwidth_allocated(dwc_otg_hcd_t * hcd,
+-00391                                               void *ep_handle);
+-00392 
+-00398 extern int dwc_otg_hcd_is_bandwidth_freed(dwc_otg_hcd_t * hcd, void *ep_handle);
+-00399 
+-00406 extern uint8_t dwc_otg_hcd_get_ep_bandwidth(dwc_otg_hcd_t * hcd,
+-00407                                             void *ep_handle);
+-00408 
+-00411 #endif /* __DWC_HCD_IF_H__ */
+-00412 #endif /* DWC_DEVICE_ONLY */
+-
                                                                                Generated on Thu Oct 27 03:56:37 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__hcd__if_8h.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/dwc__otg__hcd__if_8h.html 2013-07-26 19:34:41.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,1645 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_hcd_if.h File Reference +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                dwc_otg_hcd_if.h File Reference

                                                                                This file defines DWC_OTG HCD Core API. More... +-

                                                                                +-#include "dwc_otg_core_if.h"
                                                                                +- +-

                                                                                +-Go to the source code of this file. +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-

                                                                                Data Structures

                                                                                struct  dwc_otg_hcd_function_ops

                                                                                HCD Core API

                                                                                +-#define URB_GIVEBACK_ASAP   0x1
                                                                                +-#define URB_SEND_ZERO_PACKET   0x2
                                                                                +-dwc_otg_hcd_t * dwc_otg_hcd_alloc_hcd (void)
                                                                                 This function allocates dwc_otg_hcd structure and returns pointer on it.
                                                                                int dwc_otg_hcd_init (dwc_otg_hcd_t *hcd, dwc_otg_core_if_t *core_if)
                                                                                 This function should be called to initiate HCD Core.
                                                                                void dwc_otg_hcd_remove (dwc_otg_hcd_t *hcd)
                                                                                 Frees HCD.
                                                                                int32_t dwc_otg_hcd_handle_intr (dwc_otg_hcd_t *dwc_otg_hcd)
                                                                                 This function should be called on every hardware interrupt.
                                                                                void * dwc_otg_hcd_get_priv_data (dwc_otg_hcd_t *hcd)
                                                                                 Returns private data set by dwc_otg_hcd_set_priv_data function.
                                                                                void dwc_otg_hcd_set_priv_data (dwc_otg_hcd_t *hcd, void *priv_data)
                                                                                 Set private data.
                                                                                int dwc_otg_hcd_start (dwc_otg_hcd_t *hcd, struct dwc_otg_hcd_function_ops *fops)
                                                                                 This function initializes the HCD Core.
                                                                                void dwc_otg_hcd_stop (dwc_otg_hcd_t *hcd)
                                                                                 Halts the DWC_otg host mode operations in a clean manner.
                                                                                int dwc_otg_hcd_hub_control (dwc_otg_hcd_t *dwc_otg_hcd, uint16_t typeReq, uint16_t wValue, uint16_t wIndex, uint8_t *buf, uint16_t wLength)
                                                                                 Handles hub class-specific requests.
                                                                                uint32_t dwc_otg_hcd_otg_port (dwc_otg_hcd_t *hcd)
                                                                                 Returns otg port number.
                                                                                uint16_t dwc_otg_get_otg_version (dwc_otg_core_if_t *core_if)
                                                                                 Returns OTG version - either 1.3 or 2.0.
                                                                                uint32_t dwc_otg_hcd_is_b_host (dwc_otg_hcd_t *hcd)
                                                                                 Returns 1 if currently core is acting as B host, and 0 otherwise.
                                                                                int dwc_otg_hcd_get_frame_number (dwc_otg_hcd_t *hcd)
                                                                                 Returns current frame number.
                                                                                void dwc_otg_hcd_dump_state (dwc_otg_hcd_t *hcd)
                                                                                 Dumps hcd state.
                                                                                void dwc_otg_hcd_dump_frrem (dwc_otg_hcd_t *hcd)
                                                                                 Dump the average frame remaining at SOF.
                                                                                int dwc_otg_hcd_send_lpm (dwc_otg_hcd_t *hcd, uint8_t devaddr, uint8_t hird, uint8_t bRemoteWake)
                                                                                 Sends LPM transaction to the local device.
                                                                                dwc_otg_hcd_urb_t * dwc_otg_hcd_urb_alloc (dwc_otg_hcd_t *hcd, int iso_desc_count, int atomic_alloc)
                                                                                 Allocates memory for dwc_otg_hcd_urb structure.
                                                                                void dwc_otg_hcd_urb_set_pipeinfo (dwc_otg_hcd_urb_t *hcd_urb, uint8_t devaddr, uint8_t ep_num, uint8_t ep_type, uint8_t ep_dir, uint16_t mps)
                                                                                 Set pipe information in URB.
                                                                                void dwc_otg_hcd_urb_set_params (dwc_otg_hcd_urb_t *urb, void *urb_handle, void *buf, dwc_dma_t dma, uint32_t buflen, void *sp, dwc_dma_t sp_dma, uint32_t flags, uint16_t interval)
                                                                                 Sets dwc_otg_hcd_urb parameters.
                                                                                uint32_t dwc_otg_hcd_urb_get_status (dwc_otg_hcd_urb_t *dwc_otg_urb)
                                                                                 Gets status from dwc_otg_hcd_urb.
                                                                                uint32_t dwc_otg_hcd_urb_get_actual_length (dwc_otg_hcd_urb_t *dwc_otg_urb)
                                                                                 Gets actual length from dwc_otg_hcd_urb.
                                                                                uint32_t dwc_otg_hcd_urb_get_error_count (dwc_otg_hcd_urb_t *dwc_otg_urb)
                                                                                 Gets error count from dwc_otg_hcd_urb.
                                                                                void dwc_otg_hcd_urb_set_iso_desc_params (dwc_otg_hcd_urb_t *dwc_otg_urb, int desc_num, uint32_t offset, uint32_t length)
                                                                                 Set ISOC descriptor offset and length.
                                                                                uint32_t dwc_otg_hcd_urb_get_iso_desc_status (dwc_otg_hcd_urb_t *dwc_otg_urb, int desc_num)
                                                                                 Get status of ISOC descriptor, specified by desc_num.
                                                                                uint32_t dwc_otg_hcd_urb_get_iso_desc_actual_length (dwc_otg_hcd_urb_t *dwc_otg_urb, int desc_num)
                                                                                 Get actual length of ISOC descriptor, specified by desc_num.
                                                                                int dwc_otg_hcd_urb_enqueue (dwc_otg_hcd_t *dwc_otg_hcd, dwc_otg_hcd_urb_t *dwc_otg_urb, void **ep_handle, int atomic_alloc)
                                                                                 Queue URB.
                                                                                int dwc_otg_hcd_urb_dequeue (dwc_otg_hcd_t *dwc_otg_hcd, dwc_otg_hcd_urb_t *dwc_otg_urb)
                                                                                 De-queue the specified URB.
                                                                                int dwc_otg_hcd_endpoint_disable (dwc_otg_hcd_t *hcd, void *ep_handle, int retry)
                                                                                 Frees resources in the DWC_otg controller related to a given endpoint.
                                                                                +-int dwc_otg_hcd_endpoint_reset (dwc_otg_hcd_t *hcd, void *ep_handle)
                                                                                int dwc_otg_hcd_is_status_changed (dwc_otg_hcd_t *hcd, int port)
                                                                                 Returns 1 if status of specified port is changed and 0 otherwise.
                                                                                int dwc_otg_hcd_is_bandwidth_allocated (dwc_otg_hcd_t *hcd, void *ep_handle)
                                                                                 Call this function to check if bandwidth was allocated for specified endpoint.
                                                                                int dwc_otg_hcd_is_bandwidth_freed (dwc_otg_hcd_t *hcd, void *ep_handle)
                                                                                 Call this function to check if bandwidth was freed for specified endpoint.
                                                                                uint8_t dwc_otg_hcd_get_ep_bandwidth (dwc_otg_hcd_t *hcd, void *ep_handle)
                                                                                 Returns bandwidth allocated for specified endpoint in microseconds.

                                                                                HCD Function Driver Callbacks

                                                                                +-typedef int(* dwc_otg_hcd_start_cb_t )(dwc_otg_hcd_t *hcd)
                                                                                 This function is called whenever core switches to host mode.
                                                                                +-typedef int(* dwc_otg_hcd_disconnect_cb_t )(dwc_otg_hcd_t *hcd)
                                                                                 This function is called when device has been disconnected.
                                                                                +-typedef int(* dwc_otg_hcd_hub_info_from_urb_cb_t )(dwc_otg_hcd_t *hcd, void *urb_handle, uint32_t *hub_addr, uint32_t *port_addr)
                                                                                 Wrapper provides this function to HCD to core, so it can get hub information to which device is connected.
                                                                                +-typedef int(* dwc_otg_hcd_speed_from_urb_cb_t )(dwc_otg_hcd_t *hcd, void *urb_handle)
                                                                                 Via this function HCD core gets device speed.
                                                                                +-typedef int(* dwc_otg_hcd_complete_urb_cb_t )(dwc_otg_hcd_t *hcd, void *urb_handle, dwc_otg_hcd_urb_t *dwc_otg_urb, int32_t status)
                                                                                 This function is called when urb is completed.
                                                                                +-typedef int(* dwc_otg_hcd_get_b_hnp_enable )(dwc_otg_hcd_t *hcd)
                                                                                 Via this function HCD core gets b_hnp_enable parameter.

                                                                                Typedefs

                                                                                +-typedef dwc_otg_hcd dwc_otg_hcd_t
                                                                                +-typedef dwc_otg_hcd_urb dwc_otg_hcd_urb_t
                                                                                +-

                                                                                Detailed Description

                                                                                +-This file defines DWC_OTG HCD Core API. +-

                                                                                +- +-

                                                                                +-Definition in file dwc_otg_hcd_if.h.

                                                                                Function Documentation

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                int dwc_otg_hcd_init ( dwc_otg_hcd_t *  hcd,
                                                                                dwc_otg_core_if_t *  core_if
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This function should be called to initiate HCD Core. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +-
                                                                                hcd The HCD
                                                                                core_if The DWC_OTG Core
                                                                                +-
                                                                                +-Returns -DWC_E_NO_MEMORY if no enough memory. Returns 0 on success +-

                                                                                +-Definition at line 780 of file dwc_otg_hcd.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                void dwc_otg_hcd_remove ( dwc_otg_hcd_t *  hcd  ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Frees HCD. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +-
                                                                                hcd The HCD
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 879 of file dwc_otg_hcd.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                int32_t dwc_otg_hcd_handle_intr ( dwc_otg_hcd_t *  dwc_otg_hcd  ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This function should be called on every hardware interrupt. +-

                                                                                +-

                                                                                Todo:
                                                                                Implement i2cintr handler.
                                                                                +- +-

                                                                                +-Definition at line 43 of file dwc_otg_hcd_intr.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                void* dwc_otg_hcd_get_priv_data ( dwc_otg_hcd_t *  hcd  ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Returns private data set by dwc_otg_hcd_set_priv_data function. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +-
                                                                                hcd The HCD
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 2958 of file dwc_otg_hcd.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                void dwc_otg_hcd_set_priv_data ( dwc_otg_hcd_t *  hcd,
                                                                                void *  priv_data
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Set private data. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +-
                                                                                hcd The HCD
                                                                                priv_data pointer to be stored in private data
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 2963 of file dwc_otg_hcd.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                int dwc_otg_hcd_start ( dwc_otg_hcd_t *  hcd,
                                                                                struct dwc_otg_hcd_function_ops *  fops
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This function initializes the HCD Core. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +-
                                                                                hcd The HCD
                                                                                fops The Function Driver Operations data structure containing pointers to all callbacks.
                                                                                +-
                                                                                +-Returns -DWC_E_NO_DEVICE if Core is currently is in device mode. Returns 0 on success +-

                                                                                +-Definition at line 2942 of file dwc_otg_hcd.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                void dwc_otg_hcd_stop ( dwc_otg_hcd_t *  hcd  ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Halts the DWC_otg host mode operations in a clean manner. +-

                                                                                +-USB transfers are stopped. +-

                                                                                +-Definition at line 421 of file dwc_otg_hcd.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                int dwc_otg_hcd_hub_control ( dwc_otg_hcd_t *  dwc_otg_hcd,
                                                                                uint16_t  typeReq,
                                                                                uint16_t  wValue,
                                                                                uint16_t  wIndex,
                                                                                uint8_t *  buf,
                                                                                uint16_t  wLength
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Handles hub class-specific requests. +-

                                                                                +-

                                                                                Todo:
                                                                                  +-
                                                                                • check how sw can wait for 1 sec to check asesvld???
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 2015 of file dwc_otg_hcd.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                uint32_t dwc_otg_hcd_otg_port ( dwc_otg_hcd_t *  hcd  ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Returns otg port number. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +-
                                                                                hcd The HCD
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 2968 of file dwc_otg_hcd.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                uint16_t dwc_otg_get_otg_version ( dwc_otg_core_if_t *  core_if  ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Returns OTG version - either 1.3 or 2.0. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +-
                                                                                core_if The core_if structure pointer
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 7012 of file dwc_otg_cil.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                uint32_t dwc_otg_hcd_is_b_host ( dwc_otg_hcd_t *  hcd  ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Returns 1 if currently core is acting as B host, and 0 otherwise. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +-
                                                                                hcd The HCD
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 2973 of file dwc_otg_hcd.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                int dwc_otg_hcd_get_frame_number ( dwc_otg_hcd_t *  hcd  ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Returns current frame number. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +-
                                                                                hcd The HCD
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 2928 of file dwc_otg_hcd.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                void dwc_otg_hcd_dump_state ( dwc_otg_hcd_t *  hcd  ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Dumps hcd state. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +-
                                                                                hcd The HCD
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 3102 of file dwc_otg_hcd.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                void dwc_otg_hcd_dump_frrem ( dwc_otg_hcd_t *  hcd  ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Dump the average frame remaining at SOF. +-

                                                                                +-This can be used to determine average interrupt latency. Frame remaining is also shown for start transfer and two additional sample points. Currently this function is not implemented.

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +-
                                                                                hcd The HCD
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 3278 of file dwc_otg_hcd.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                int dwc_otg_hcd_send_lpm ( dwc_otg_hcd_t *  hcd,
                                                                                uint8_t  devaddr,
                                                                                uint8_t  hird,
                                                                                uint8_t  bRemoteWake
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Sends LPM transaction to the local device. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +- +- +-
                                                                                hcd The HCD
                                                                                devaddr Device Address
                                                                                hird Host initiated resume duration
                                                                                bRemoteWake Value of bRemoteWake field in LPM transaction
                                                                                +-
                                                                                +-Returns negative value if sending LPM transaction was not succeeded. Returns 0 on success.
                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                dwc_otg_hcd_urb_t* dwc_otg_hcd_urb_alloc ( dwc_otg_hcd_t *  hcd,
                                                                                int  iso_desc_count,
                                                                                int  atomic_alloc
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Allocates memory for dwc_otg_hcd_urb structure. +-

                                                                                +-Allocated memory should be freed by call of DWC_FREE.

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +- +-
                                                                                hcd The HCD
                                                                                iso_desc_count Count of ISOC descriptors
                                                                                atomic_alloc Specefies whether to perform atomic allocation.
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 2985 of file dwc_otg_hcd.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                void dwc_otg_hcd_urb_set_pipeinfo ( dwc_otg_hcd_urb_t *  hcd_urb,
                                                                                uint8_t  devaddr,
                                                                                uint8_t  ep_num,
                                                                                uint8_t  ep_type,
                                                                                uint8_t  ep_dir,
                                                                                uint16_t  mps
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Set pipe information in URB. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +- +- +- +- +-
                                                                                hcd_urb DWC_OTG URB
                                                                                devaddr Device Address
                                                                                ep_num Endpoint Number
                                                                                ep_type Endpoint Type
                                                                                ep_dir Endpoint Direction
                                                                                mps Max Packet Size
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 3004 of file dwc_otg_hcd.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                void dwc_otg_hcd_urb_set_params ( dwc_otg_hcd_urb_t *  urb,
                                                                                void *  urb_handle,
                                                                                void *  buf,
                                                                                dwc_dma_t  dma,
                                                                                uint32_t  buflen,
                                                                                void *  sp,
                                                                                dwc_dma_t  sp_dma,
                                                                                uint32_t  flags,
                                                                                uint16_t  interval
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Sets dwc_otg_hcd_urb parameters. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +- +- +- +- +- +- +- +-
                                                                                urb DWC_OTG URB allocated by dwc_otg_hcd_urb_alloc function.
                                                                                urb_handle Unique handle for request, this will be passed back to function driver in completion callback.
                                                                                buf The buffer for the data
                                                                                dma The DMA buffer for the data
                                                                                buflen Transfer length
                                                                                sp Buffer for setup data
                                                                                sp_dma DMA address of setup data buffer
                                                                                flags Transfer flags
                                                                                interval Polling interval for interrupt or isochronous transfers.
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 3017 of file dwc_otg_hcd.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                uint32_t dwc_otg_hcd_urb_get_status ( dwc_otg_hcd_urb_t *  dwc_otg_urb  ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Gets status from dwc_otg_hcd_urb. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +-
                                                                                dwc_otg_urb DWC_OTG URB
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 3034 of file dwc_otg_hcd.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                uint32_t dwc_otg_hcd_urb_get_actual_length ( dwc_otg_hcd_urb_t *  dwc_otg_urb  ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Gets actual length from dwc_otg_hcd_urb. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +-
                                                                                dwc_otg_urb DWC_OTG URB
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 3039 of file dwc_otg_hcd.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                uint32_t dwc_otg_hcd_urb_get_error_count ( dwc_otg_hcd_urb_t *  dwc_otg_urb  ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Gets error count from dwc_otg_hcd_urb. +-

                                                                                +-Only for ISOC URBs

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +-
                                                                                dwc_otg_urb DWC_OTG URB
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 3044 of file dwc_otg_hcd.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                void dwc_otg_hcd_urb_set_iso_desc_params ( dwc_otg_hcd_urb_t *  dwc_otg_urb,
                                                                                int  desc_num,
                                                                                uint32_t  offset,
                                                                                uint32_t  length
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Set ISOC descriptor offset and length. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +- +- +-
                                                                                dwc_otg_urb DWC_OTG URB
                                                                                desc_num ISOC descriptor number
                                                                                offset Offset from beginig of buffer.
                                                                                length Transaction length
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 3049 of file dwc_otg_hcd.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                uint32_t dwc_otg_hcd_urb_get_iso_desc_status ( dwc_otg_hcd_urb_t *  dwc_otg_urb,
                                                                                int  desc_num
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Get status of ISOC descriptor, specified by desc_num. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +-
                                                                                dwc_otg_urb DWC_OTG URB
                                                                                desc_num ISOC descriptor number
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 3057 of file dwc_otg_hcd.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                uint32_t dwc_otg_hcd_urb_get_iso_desc_actual_length ( dwc_otg_hcd_urb_t *  dwc_otg_urb,
                                                                                int  desc_num
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Get actual length of ISOC descriptor, specified by desc_num. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +-
                                                                                dwc_otg_urb DWC_OTG URB
                                                                                desc_num ISOC descriptor number
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 3063 of file dwc_otg_hcd.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                int dwc_otg_hcd_urb_enqueue ( dwc_otg_hcd_t *  dwc_otg_hcd,
                                                                                dwc_otg_hcd_urb_t *  dwc_otg_urb,
                                                                                void **  ep_handle,
                                                                                int  atomic_alloc
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Queue URB. +-

                                                                                +-After transfer is completes, the complete callback will be called with the URB status

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +- +- +-
                                                                                dwc_otg_hcd The HCD
                                                                                dwc_otg_urb DWC_OTG URB
                                                                                ep_handle Out parameter for returning endpoint handle
                                                                                atomic_alloc Flag to do atomic allocation if needed
                                                                                +-
                                                                                +-Returns -DWC_E_NO_DEVICE if no device is connected. Returns -DWC_E_NO_MEMORY if there is no enough memory. Returns 0 on success. +-

                                                                                +-Definition at line 443 of file dwc_otg_hcd.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                int dwc_otg_hcd_urb_dequeue ( dwc_otg_hcd_t *  dwc_otg_hcd,
                                                                                dwc_otg_hcd_urb_t *  dwc_otg_urb
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-De-queue the specified URB. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +-
                                                                                dwc_otg_hcd The HCD
                                                                                dwc_otg_urb DWC_OTG URB
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 492 of file dwc_otg_hcd.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                int dwc_otg_hcd_endpoint_disable ( dwc_otg_hcd_t *  hcd,
                                                                                void *  ep_handle,
                                                                                int  retry
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Frees resources in the DWC_otg controller related to a given endpoint. +-

                                                                                +-Any URBs for the endpoint must already be dequeued.

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +- +-
                                                                                hcd The HCD
                                                                                ep_handle Endpoint handle, returned by dwc_otg_hcd_urb_enqueue function
                                                                                retry Number of retries if there are queued transfers.
                                                                                +-
                                                                                +-Returns -DWC_E_INVALID if invalid arguments are passed. Returns 0 on success +-

                                                                                +-Definition at line 542 of file dwc_otg_hcd.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                int dwc_otg_hcd_is_status_changed ( dwc_otg_hcd_t *  hcd,
                                                                                int  port
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Returns 1 if status of specified port is changed and 0 otherwise. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +-
                                                                                hcd The HCD
                                                                                port Port number
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 2896 of file dwc_otg_hcd.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                int dwc_otg_hcd_is_bandwidth_allocated ( dwc_otg_hcd_t *  hcd,
                                                                                void *  ep_handle
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Call this function to check if bandwidth was allocated for specified endpoint. +-

                                                                                +-Only for ISOC and INTERRUPT endpoints.

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +-
                                                                                hcd The HCD
                                                                                ep_handle Endpoint handle
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 3069 of file dwc_otg_hcd.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                int dwc_otg_hcd_is_bandwidth_freed ( dwc_otg_hcd_t *  hcd,
                                                                                void *  ep_handle
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Call this function to check if bandwidth was freed for specified endpoint. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +-
                                                                                hcd The HCD
                                                                                ep_handle Endpoint handle
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 3082 of file dwc_otg_hcd.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                uint8_t dwc_otg_hcd_get_ep_bandwidth ( dwc_otg_hcd_t *  hcd,
                                                                                void *  ep_handle
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Returns bandwidth allocated for specified endpoint in microseconds. +-

                                                                                +-Only for ISOC and INTERRUPT endpoints.

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +-
                                                                                hcd The HCD
                                                                                ep_handle Endpoint handle
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 3095 of file dwc_otg_hcd.c.

                                                                                +-

                                                                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__hcd__intr_8c-source.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/dwc__otg__hcd__intr_8c-source.html 2013-07-26 19:34:41.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,1921 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_hcd_intr.c Source File +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                dwc_otg_hcd_intr.c

                                                                                Go to the documentation of this file.
                                                                                00001 /* ==========================================================================
+-00002  * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd_intr.c $
+-00003  * $Revision: #89 $
+-00004  * $Date: 2011/10/20 $
+-00005  * $Change: 1869487 $
+-00006  *
+-00007  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
+-00008  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
+-00009  * otherwise expressly agreed to in writing between Synopsys and you.
+-00010  *
+-00011  * The Software IS NOT an item of Licensed Software or Licensed Product under
+-00012  * any End User Software License Agreement or Agreement for Licensed Product
+-00013  * with Synopsys or any supplement thereto. You are permitted to use and
+-00014  * redistribute this Software in source and binary forms, with or without
+-00015  * modification, provided that redistributions of source code must retain this
+-00016  * notice. You may not view, use, disclose, copy or distribute this file or
+-00017  * any information contained herein except pursuant to this license grant from
+-00018  * Synopsys. If you do not agree with this notice, including the disclaimer
+-00019  * below, then you are not authorized to use the Software.
+-00020  *
+-00021  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
+-00022  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+-00023  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+-00024  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
+-00025  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+-00026  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+-00027  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+-00028  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+-00029  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+-00030  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+-00031  * DAMAGE.
+-00032  * ========================================================================== */
+-00033 #ifndef DWC_DEVICE_ONLY
+-00034 
+-00035 #include "dwc_otg_hcd.h"
+-00036 #include "dwc_otg_regs.h"
+-00037 
+-00043 int32_t dwc_otg_hcd_handle_intr(dwc_otg_hcd_t * dwc_otg_hcd)
+-00044 {
+-00045         int retval = 0;
+-00046 
+-00047         dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;
+-00048         gintsts_data_t gintsts;
+-00049 #ifdef DEBUG
+-00050         dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
+-00051 #endif
+-00052 
+-00053         /* Exit from ISR if core is hibernated */
+-00054         if (core_if->hibernation_suspend == 1) {
+-00055                 return retval;
+-00056         }
+-00057         DWC_SPINLOCK(dwc_otg_hcd->lock);
+-00058         /* Check if HOST Mode */
+-00059         if (dwc_otg_is_host_mode(core_if)) {
+-00060                 gintsts.d32 = dwc_otg_read_core_intr(core_if);
+-00061                 if (!gintsts.d32) {
+-00062                         DWC_SPINUNLOCK(dwc_otg_hcd->lock);
+-00063                         return 0;
+-00064                 }
+-00065 #ifdef DEBUG
+-00066                 /* Don't print debug message in the interrupt handler on SOF */
+-00067 #ifndef DEBUG_SOF
+-00068                 if (gintsts.d32 != DWC_SOF_INTR_MASK)
+-00069 #endif
+-00070                         DWC_DEBUGPL(DBG_HCD, "\n");
+-00071 #endif
+-00072 
+-00073 #ifdef DEBUG
+-00074 #ifndef DEBUG_SOF
+-00075                 if (gintsts.d32 != DWC_SOF_INTR_MASK)
+-00076 #endif
+-00077                         DWC_DEBUGPL(DBG_HCD,
+-00078                                     "DWC OTG HCD Interrupt Detected gintsts&gintmsk=0x%08x\n",
+-00079                                     gintsts.d32);
+-00080 #endif
+-00081 
+-00082                 if (gintsts.b.sofintr) {
+-00083                         retval |= dwc_otg_hcd_handle_sof_intr(dwc_otg_hcd);
+-00084                 }
+-00085                 if (gintsts.b.rxstsqlvl) {
+-00086                         retval |=
+-00087                             dwc_otg_hcd_handle_rx_status_q_level_intr
+-00088                             (dwc_otg_hcd);
+-00089                 }
+-00090                 if (gintsts.b.nptxfempty) {
+-00091                         retval |=
+-00092                             dwc_otg_hcd_handle_np_tx_fifo_empty_intr
+-00093                             (dwc_otg_hcd);
+-00094                 }
+-00095                 if (gintsts.b.i2cintr) {
+-00097                 }
+-00098                 if (gintsts.b.portintr) {
+-00099                         retval |= dwc_otg_hcd_handle_port_intr(dwc_otg_hcd);
+-00100                 }
+-00101                 if (gintsts.b.hcintr) {
+-00102                         retval |= dwc_otg_hcd_handle_hc_intr(dwc_otg_hcd);
+-00103                 }
+-00104                 if (gintsts.b.ptxfempty) {
+-00105                         retval |=
+-00106                             dwc_otg_hcd_handle_perio_tx_fifo_empty_intr
+-00107                             (dwc_otg_hcd);
+-00108                 }
+-00109 #ifdef DEBUG
+-00110 #ifndef DEBUG_SOF
+-00111                 if (gintsts.d32 != DWC_SOF_INTR_MASK)
+-00112 #endif
+-00113                 {
+-00114                         DWC_DEBUGPL(DBG_HCD,
+-00115                                     "DWC OTG HCD Finished Servicing Interrupts\n");
+-00116                         DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD gintsts=0x%08x\n",
+-00117                                     DWC_READ_REG32(&global_regs->gintsts));
+-00118                         DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD gintmsk=0x%08x\n",
+-00119                                     DWC_READ_REG32(&global_regs->gintmsk));
+-00120                 }
+-00121 #endif
+-00122 
+-00123 #ifdef DEBUG
+-00124 #ifndef DEBUG_SOF
+-00125                 if (gintsts.d32 != DWC_SOF_INTR_MASK)
+-00126 #endif
+-00127                         DWC_DEBUGPL(DBG_HCD, "\n");
+-00128 #endif
+-00129 
+-00130         }
+-00131         DWC_SPINUNLOCK(dwc_otg_hcd->lock);
+-00132         return retval;
+-00133 }
+-00134 
+-00135 #ifdef DWC_TRACK_MISSED_SOFS
+-00136 #warning Compiling code to track missed SOFs
+-00137 #define FRAME_NUM_ARRAY_SIZE 1000
+-00138 
+-00141 static inline void track_missed_sofs(uint16_t curr_frame_number)
+-00142 {
+-00143         static uint16_t frame_num_array[FRAME_NUM_ARRAY_SIZE];
+-00144         static uint16_t last_frame_num_array[FRAME_NUM_ARRAY_SIZE];
+-00145         static int frame_num_idx = 0;
+-00146         static uint16_t last_frame_num = DWC_HFNUM_MAX_FRNUM;
+-00147         static int dumped_frame_num_array = 0;
+-00148 
+-00149         if (frame_num_idx < FRAME_NUM_ARRAY_SIZE) {
+-00150                 if (((last_frame_num + 1) & DWC_HFNUM_MAX_FRNUM) !=
+-00151                     curr_frame_number) {
+-00152                         frame_num_array[frame_num_idx] = curr_frame_number;
+-00153                         last_frame_num_array[frame_num_idx++] = last_frame_num;
+-00154                 }
+-00155         } else if (!dumped_frame_num_array) {
+-00156                 int i;
+-00157                 DWC_PRINTF("Frame     Last Frame\n");
+-00158                 DWC_PRINTF("-----     ----------\n");
+-00159                 for (i = 0; i < FRAME_NUM_ARRAY_SIZE; i++) {
+-00160                         DWC_PRINTF("0x%04x    0x%04x\n",
+-00161                                    frame_num_array[i], last_frame_num_array[i]);
+-00162                 }
+-00163                 dumped_frame_num_array = 1;
+-00164         }
+-00165         last_frame_num = curr_frame_number;
+-00166 }
+-00167 #endif
+-00168 
+-00175 int32_t dwc_otg_hcd_handle_sof_intr(dwc_otg_hcd_t * hcd)
+-00176 {
+-00177         hfnum_data_t hfnum;
+-00178         dwc_list_link_t *qh_entry;
+-00179         dwc_otg_qh_t *qh;
+-00180         dwc_otg_transaction_type_e tr_type;
+-00181         gintsts_data_t gintsts = {.d32 = 0 };
+-00182 
+-00183         hfnum.d32 =
+-00184             DWC_READ_REG32(&hcd->core_if->host_if->host_global_regs->hfnum);
+-00185 
+-00186 #ifdef DEBUG_SOF
+-00187         DWC_DEBUGPL(DBG_HCD, "--Start of Frame Interrupt--\n");
+-00188 #endif
+-00189         hcd->frame_number = hfnum.b.frnum;
+-00190 
+-00191 #ifdef DEBUG
+-00192         hcd->frrem_accum += hfnum.b.frrem;
+-00193         hcd->frrem_samples++;
+-00194 #endif
+-00195 
+-00196 #ifdef DWC_TRACK_MISSED_SOFS
+-00197         track_missed_sofs(hcd->frame_number);
+-00198 #endif
+-00199         /* Determine whether any periodic QHs should be executed. */
+-00200         qh_entry = DWC_LIST_FIRST(&hcd->periodic_sched_inactive);
+-00201         while (qh_entry != &hcd->periodic_sched_inactive) {
+-00202                 qh = DWC_LIST_ENTRY(qh_entry, dwc_otg_qh_t, qh_list_entry);
+-00203                 qh_entry = qh_entry->next;
+-00204                 if (dwc_frame_num_le(qh->sched_frame, hcd->frame_number)) {
+-00205                         /*
+-00206                          * Move QH to the ready list to be executed next
+-00207                          * (micro)frame.
+-00208                          */
+-00209                         DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_ready,
+-00210                                            &qh->qh_list_entry);
+-00211                 }
+-00212         }
+-00213         tr_type = dwc_otg_hcd_select_transactions(hcd);
+-00214         if (tr_type != DWC_OTG_TRANSACTION_NONE) {
+-00215                 dwc_otg_hcd_queue_transactions(hcd, tr_type);
+-00216         }
+-00217 
+-00218         /* Clear interrupt */
+-00219         gintsts.b.sofintr = 1;
+-00220         DWC_WRITE_REG32(&hcd->core_if->core_global_regs->gintsts, gintsts.d32);
+-00221 
+-00222         return 1;
+-00223 }
+-00224 
+-00228 int32_t dwc_otg_hcd_handle_rx_status_q_level_intr(dwc_otg_hcd_t * dwc_otg_hcd)
+-00229 {
+-00230         host_grxsts_data_t grxsts;
+-00231         dwc_hc_t *hc = NULL;
+-00232 
+-00233         DWC_DEBUGPL(DBG_HCD, "--RxStsQ Level Interrupt--\n");
+-00234 
+-00235         grxsts.d32 =
+-00236             DWC_READ_REG32(&dwc_otg_hcd->core_if->core_global_regs->grxstsp);
+-00237 
+-00238         hc = dwc_otg_hcd->hc_ptr_array[grxsts.b.chnum];
+-00239         if (!hc) {
+-00240                 DWC_ERROR("Unable to get corresponding channel\n");
+-00241                 return 0;
+-00242         }
+-00243 
+-00244         /* Packet Status */
+-00245         DWC_DEBUGPL(DBG_HCDV, "    Ch num = %d\n", grxsts.b.chnum);
+-00246         DWC_DEBUGPL(DBG_HCDV, "    Count = %d\n", grxsts.b.bcnt);
+-00247         DWC_DEBUGPL(DBG_HCDV, "    DPID = %d, hc.dpid = %d\n", grxsts.b.dpid,
+-00248                     hc->data_pid_start);
+-00249         DWC_DEBUGPL(DBG_HCDV, "    PStatus = %d\n", grxsts.b.pktsts);
+-00250 
+-00251         switch (grxsts.b.pktsts) {
+-00252         case DWC_GRXSTS_PKTSTS_IN:
+-00253                 /* Read the data into the host buffer. */
+-00254                 if (grxsts.b.bcnt > 0) {
+-00255                         dwc_otg_read_packet(dwc_otg_hcd->core_if,
+-00256                                             hc->xfer_buff, grxsts.b.bcnt);
+-00257 
+-00258                         /* Update the HC fields for the next packet received. */
+-00259                         hc->xfer_count += grxsts.b.bcnt;
+-00260                         hc->xfer_buff += grxsts.b.bcnt;
+-00261                 }
+-00262 
+-00263         case DWC_GRXSTS_PKTSTS_IN_XFER_COMP:
+-00264         case DWC_GRXSTS_PKTSTS_DATA_TOGGLE_ERR:
+-00265         case DWC_GRXSTS_PKTSTS_CH_HALTED:
+-00266                 /* Handled in interrupt, just ignore data */
+-00267                 break;
+-00268         default:
+-00269                 DWC_ERROR("RX_STS_Q Interrupt: Unknown status %d\n",
+-00270                           grxsts.b.pktsts);
+-00271                 break;
+-00272         }
+-00273 
+-00274         return 1;
+-00275 }
+-00276 
+-00281 int32_t dwc_otg_hcd_handle_np_tx_fifo_empty_intr(dwc_otg_hcd_t * dwc_otg_hcd)
+-00282 {
+-00283         DWC_DEBUGPL(DBG_HCD, "--Non-Periodic TxFIFO Empty Interrupt--\n");
+-00284         dwc_otg_hcd_queue_transactions(dwc_otg_hcd,
+-00285                                        DWC_OTG_TRANSACTION_NON_PERIODIC);
+-00286         return 1;
+-00287 }
+-00288 
+-00293 int32_t dwc_otg_hcd_handle_perio_tx_fifo_empty_intr(dwc_otg_hcd_t * dwc_otg_hcd)
+-00294 {
+-00295         DWC_DEBUGPL(DBG_HCD, "--Periodic TxFIFO Empty Interrupt--\n");
+-00296         dwc_otg_hcd_queue_transactions(dwc_otg_hcd,
+-00297                                        DWC_OTG_TRANSACTION_PERIODIC);
+-00298         return 1;
+-00299 }
+-00300 
+-00304 int32_t dwc_otg_hcd_handle_port_intr(dwc_otg_hcd_t * dwc_otg_hcd)
+-00305 {
+-00306         int retval = 0;
+-00307         hprt0_data_t hprt0;
+-00308         hprt0_data_t hprt0_modify;
+-00309 
+-00310         hprt0.d32 = DWC_READ_REG32(dwc_otg_hcd->core_if->host_if->hprt0);
+-00311         hprt0_modify.d32 = DWC_READ_REG32(dwc_otg_hcd->core_if->host_if->hprt0);
+-00312 
+-00313         /* Clear appropriate bits in HPRT0 to clear the interrupt bit in
+-00314          * GINTSTS */
+-00315 
+-00316         hprt0_modify.b.prtena = 0;
+-00317         hprt0_modify.b.prtconndet = 0;
+-00318         hprt0_modify.b.prtenchng = 0;
+-00319         hprt0_modify.b.prtovrcurrchng = 0;
+-00320 
+-00321         /* Port Connect Detected
+-00322          * Set flag and clear if detected */
+-00323         if (dwc_otg_hcd->core_if->hibernation_suspend == 1) {
+-00324                 // Dont modify port status if we are in hibernation state
+-00325                 hprt0_modify.b.prtconndet = 1;
+-00326                 hprt0_modify.b.prtenchng = 1;
+-00327                 DWC_WRITE_REG32(dwc_otg_hcd->core_if->host_if->hprt0, hprt0_modify.d32);
+-00328                 hprt0.d32 = DWC_READ_REG32(dwc_otg_hcd->core_if->host_if->hprt0);
+-00329                 return retval;
+-00330         }
+-00331 
+-00332         if (hprt0.b.prtconndet) {
+-00334                 if (dwc_otg_hcd->core_if->adp_enable &&         
+-00335                                 dwc_otg_hcd->core_if->adp.vbuson_timer_started == 1) {
+-00336                         DWC_PRINTF("PORT CONNECT DETECTED ----------------\n");
+-00337                         DWC_TIMER_CANCEL(dwc_otg_hcd->core_if->adp.vbuson_timer);
+-00338                         dwc_otg_hcd->core_if->adp.vbuson_timer_started = 0;
+-00339                         /* TODO - check if this is required, as
+-00340                          * host initialization was already performed
+-00341                          * after initial ADP probing
+-00342                          */
+-00343                         /*dwc_otg_hcd->core_if->adp.vbuson_timer_started = 0;
+-00344                         dwc_otg_core_init(dwc_otg_hcd->core_if);
+-00345                         dwc_otg_enable_global_interrupts(dwc_otg_hcd->core_if);
+-00346                         cil_hcd_start(dwc_otg_hcd->core_if);*/
+-00347                 } else {
+-00348                 
+-00349                         DWC_DEBUGPL(DBG_HCD, "--Port Interrupt HPRT0=0x%08x "
+-00350                                     "Port Connect Detected--\n", hprt0.d32);
+-00351                         dwc_otg_hcd->flags.b.port_connect_status_change = 1;
+-00352                         dwc_otg_hcd->flags.b.port_connect_status = 1;
+-00353                         hprt0_modify.b.prtconndet = 1;
+-00354         
+-00355                         /* B-Device has connected, Delete the connection timer. */
+-00356                         DWC_TIMER_CANCEL(dwc_otg_hcd->conn_timer);
+-00357                 }
+-00358                 /* The Hub driver asserts a reset when it sees port connect
+-00359                  * status change flag */
+-00360                 retval |= 1;
+-00361         }
+-00362 
+-00363         /* Port Enable Changed
+-00364          * Clear if detected - Set internal flag if disabled */
+-00365         if (hprt0.b.prtenchng) {
+-00366                 DWC_DEBUGPL(DBG_HCD, "  --Port Interrupt HPRT0=0x%08x "
+-00367                             "Port Enable Changed--\n", hprt0.d32);
+-00368                 hprt0_modify.b.prtenchng = 1;
+-00369                 if (hprt0.b.prtena == 1) {
+-00370                         hfir_data_t hfir;
+-00371                         int do_reset = 0;
+-00372                         dwc_otg_core_params_t *params =
+-00373                             dwc_otg_hcd->core_if->core_params;
+-00374                         dwc_otg_core_global_regs_t *global_regs =
+-00375                             dwc_otg_hcd->core_if->core_global_regs;
+-00376                         dwc_otg_host_if_t *host_if =
+-00377                             dwc_otg_hcd->core_if->host_if;
+-00378                             
+-00379                         /* Every time when port enables calculate
+-00380                          * HFIR.FrInterval
+-00381                          */
+-00382                         hfir.d32 = DWC_READ_REG32(&host_if->host_global_regs->hfir);
+-00383                         hfir.b.frint = calc_frame_interval(dwc_otg_hcd->core_if);
+-00384                         DWC_WRITE_REG32(&host_if->host_global_regs->hfir, hfir.d32);
+-00385 
+-00386                         /* Check if we need to adjust the PHY clock speed for
+-00387                          * low power and adjust it */
+-00388                         if (params->host_support_fs_ls_low_power) {
+-00389                                 gusbcfg_data_t usbcfg;
+-00390 
+-00391                                 usbcfg.d32 =
+-00392                                     DWC_READ_REG32(&global_regs->gusbcfg);
+-00393 
+-00394                                 if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_LOW_SPEED
+-00395                                     || hprt0.b.prtspd ==
+-00396                                     DWC_HPRT0_PRTSPD_FULL_SPEED) {
+-00397                                         /*
+-00398                                          * Low power
+-00399                                          */
+-00400                                         hcfg_data_t hcfg;
+-00401                                         if (usbcfg.b.phylpwrclksel == 0) {
+-00402                                                 /* Set PHY low power clock select for FS/LS devices */
+-00403                                                 usbcfg.b.phylpwrclksel = 1;
+-00404                                                 DWC_WRITE_REG32
+-00405                                                     (&global_regs->gusbcfg,
+-00406                                                      usbcfg.d32);
+-00407                                                 do_reset = 1;
+-00408                                         }
+-00409 
+-00410                                         hcfg.d32 =
+-00411                                             DWC_READ_REG32
+-00412                                             (&host_if->host_global_regs->hcfg);
+-00413 
+-00414                                         if (hprt0.b.prtspd ==
+-00415                                             DWC_HPRT0_PRTSPD_LOW_SPEED
+-00416                                             && params->host_ls_low_power_phy_clk
+-00417                                             ==
+-00418                                             DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ)
+-00419                                         {
+-00420                                                 /* 6 MHZ */
+-00421                                                 DWC_DEBUGPL(DBG_CIL,
+-00422                                                             "FS_PHY programming HCFG to 6 MHz (Low Power)\n");
+-00423                                                 if (hcfg.b.fslspclksel !=
+-00424                                                     DWC_HCFG_6_MHZ) {
+-00425                                                         hcfg.b.fslspclksel =
+-00426                                                             DWC_HCFG_6_MHZ;
+-00427                                                         DWC_WRITE_REG32
+-00428                                                             (&host_if->host_global_regs->hcfg,
+-00429                                                              hcfg.d32);
+-00430                                                         do_reset = 1;
+-00431                                                 }
+-00432                                         } else {
+-00433                                                 /* 48 MHZ */
+-00434                                                 DWC_DEBUGPL(DBG_CIL,
+-00435                                                             "FS_PHY programming HCFG to 48 MHz ()\n");
+-00436                                                 if (hcfg.b.fslspclksel !=
+-00437                                                     DWC_HCFG_48_MHZ) {
+-00438                                                         hcfg.b.fslspclksel =
+-00439                                                             DWC_HCFG_48_MHZ;
+-00440                                                         DWC_WRITE_REG32
+-00441                                                             (&host_if->host_global_regs->hcfg,
+-00442                                                              hcfg.d32);
+-00443                                                         do_reset = 1;
+-00444                                                 }
+-00445                                         }
+-00446                                 } else {
+-00447                                         /*
+-00448                                          * Not low power
+-00449                                          */
+-00450                                         if (usbcfg.b.phylpwrclksel == 1) {
+-00451                                                 usbcfg.b.phylpwrclksel = 0;
+-00452                                                 DWC_WRITE_REG32
+-00453                                                     (&global_regs->gusbcfg,
+-00454                                                      usbcfg.d32);
+-00455                                                 do_reset = 1;
+-00456                                         }
+-00457                                 }
+-00458 
+-00459                                 if (do_reset) {
+-00460                                         DWC_TASK_SCHEDULE(dwc_otg_hcd->reset_tasklet);
+-00461                                 }
+-00462                         }
+-00463 
+-00464                         if (!do_reset) {
+-00465                                 /* Port has been enabled set the reset change flag */
+-00466                                 dwc_otg_hcd->flags.b.port_reset_change = 1;
+-00467                         }
+-00468                 } else {
+-00469                         dwc_otg_hcd->flags.b.port_enable_change = 1;
+-00470                 }
+-00471                 retval |= 1;
+-00472         }
+-00473 
+-00475         if (hprt0.b.prtovrcurrchng) {
+-00476                 DWC_DEBUGPL(DBG_HCD, "  --Port Interrupt HPRT0=0x%08x "
+-00477                             "Port Overcurrent Changed--\n", hprt0.d32);
+-00478                 dwc_otg_hcd->flags.b.port_over_current_change = 1;
+-00479                 hprt0_modify.b.prtovrcurrchng = 1;
+-00480                 retval |= 1;
+-00481         }
+-00482 
+-00483         /* Clear Port Interrupts */
+-00484         DWC_WRITE_REG32(dwc_otg_hcd->core_if->host_if->hprt0, hprt0_modify.d32);
+-00485 
+-00486         return retval;
+-00487 }
+-00488 
+-00493 int32_t dwc_otg_hcd_handle_hc_intr(dwc_otg_hcd_t * dwc_otg_hcd)
+-00494 {
+-00495         int i;
+-00496         int retval = 0;
+-00497         haint_data_t haint;
+-00498 
+-00499         /* Clear appropriate bits in HCINTn to clear the interrupt bit in
+-00500          * GINTSTS */
+-00501 
+-00502         haint.d32 = dwc_otg_read_host_all_channels_intr(dwc_otg_hcd->core_if);
+-00503 
+-00504         for (i = 0; i < dwc_otg_hcd->core_if->core_params->host_channels; i++) {
+-00505                 if (haint.b2.chint & (1 << i)) {
+-00506                         retval |= dwc_otg_hcd_handle_hc_n_intr(dwc_otg_hcd, i);
+-00507                 }
+-00508         }
+-00509 
+-00510         return retval;
+-00511 }
+-00512 
+-00523 static uint32_t get_actual_xfer_length(dwc_hc_t * hc,
+-00524                                        dwc_otg_hc_regs_t * hc_regs,
+-00525                                        dwc_otg_qtd_t * qtd,
+-00526                                        dwc_otg_halt_status_e halt_status,
+-00527                                        int *short_read)
+-00528 {
+-00529         hctsiz_data_t hctsiz;
+-00530         uint32_t length;
+-00531 
+-00532         if (short_read != NULL) {
+-00533                 *short_read = 0;
+-00534         }
+-00535         hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
+-00536 
+-00537         if (halt_status == DWC_OTG_HC_XFER_COMPLETE) {
+-00538                 if (hc->ep_is_in) {
+-00539                         length = hc->xfer_len - hctsiz.b.xfersize;
+-00540                         if (short_read != NULL) {
+-00541                                 *short_read = (hctsiz.b.xfersize != 0);
+-00542                         }
+-00543                 } else if (hc->qh->do_split) {
+-00544                         length = qtd->ssplit_out_xfer_count;
+-00545                 } else {
+-00546                         length = hc->xfer_len;
+-00547                 }
+-00548         } else {
+-00549                 /*
+-00550                  * Must use the hctsiz.pktcnt field to determine how much data
+-00551                  * has been transferred. This field reflects the number of
+-00552                  * packets that have been transferred via the USB. This is
+-00553                  * always an integral number of packets if the transfer was
+-00554                  * halted before its normal completion. (Can't use the
+-00555                  * hctsiz.xfersize field because that reflects the number of
+-00556                  * bytes transferred via the AHB, not the USB).
+-00557                  */
+-00558                 length =
+-00559                     (hc->start_pkt_count - hctsiz.b.pktcnt) * hc->max_packet;
+-00560         }
+-00561 
+-00562         return length;
+-00563 }
+-00564 
+-00574 static int update_urb_state_xfer_comp(dwc_hc_t * hc,
+-00575                                       dwc_otg_hc_regs_t * hc_regs,
+-00576                                       dwc_otg_hcd_urb_t * urb,
+-00577                                       dwc_otg_qtd_t * qtd)
+-00578 {
+-00579         int xfer_done = 0;
+-00580         int short_read = 0;
+-00581 
+-00582         int xfer_length;
+-00583 
+-00584         xfer_length = get_actual_xfer_length(hc, hc_regs, qtd,
+-00585                                              DWC_OTG_HC_XFER_COMPLETE,
+-00586                                              &short_read);
+-00587 
+-00588 
+-00589         /* non DWORD-aligned buffer case handling. */
+-00590         if (hc->align_buff && xfer_length && hc->ep_is_in) {
+-00591                 dwc_memcpy(urb->buf + urb->actual_length, hc->qh->dw_align_buf,
+-00592                            xfer_length);
+-00593         }
+-00594 
+-00595         urb->actual_length += xfer_length;
+-00596 
+-00597         if (xfer_length && (hc->ep_type == DWC_OTG_EP_TYPE_BULK) &&
+-00598             (urb->flags & URB_SEND_ZERO_PACKET)
+-00599             && (urb->actual_length == urb->length)
+-00600             && !(urb->length % hc->max_packet)) {
+-00601                 xfer_done = 0;
+-00602         } else if (short_read || urb->actual_length == urb->length) {
+-00603                 xfer_done = 1;
+-00604                 urb->status = 0;
+-00605         }
+-00606         
+-00607 #ifdef DEBUG
+-00608         {
+-00609                 hctsiz_data_t hctsiz;
+-00610                 hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
+-00611                 DWC_DEBUGPL(DBG_HCDV, "DWC_otg: %s: %s, channel %d\n",
+-00612                             __func__, (hc->ep_is_in ? "IN" : "OUT"),
+-00613                             hc->hc_num);
+-00614                 DWC_DEBUGPL(DBG_HCDV, "  hc->xfer_len %d\n", hc->xfer_len);
+-00615                 DWC_DEBUGPL(DBG_HCDV, "  hctsiz.xfersize %d\n",
+-00616                             hctsiz.b.xfersize);
+-00617                 DWC_DEBUGPL(DBG_HCDV, "  urb->transfer_buffer_length %d\n",
+-00618                             urb->length);
+-00619                 DWC_DEBUGPL(DBG_HCDV, "  urb->actual_length %d\n",
+-00620                             urb->actual_length);
+-00621                 DWC_DEBUGPL(DBG_HCDV, "  short_read %d, xfer_done %d\n",
+-00622                             short_read, xfer_done);
+-00623         }
+-00624 #endif
+-00625 
+-00626         return xfer_done;
+-00627 }
+-00628 
+-00629 /*
+-00630  * Save the starting data toggle for the next transfer. The data toggle is
+-00631  * saved in the QH for non-control transfers and it's saved in the QTD for
+-00632  * control transfers.
+-00633  */
+-00634 void dwc_otg_hcd_save_data_toggle(dwc_hc_t * hc,
+-00635                              dwc_otg_hc_regs_t * hc_regs, dwc_otg_qtd_t * qtd)
+-00636 {
+-00637         hctsiz_data_t hctsiz;
+-00638         hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
+-00639 
+-00640         if (hc->ep_type != DWC_OTG_EP_TYPE_CONTROL) {
+-00641                 dwc_otg_qh_t *qh = hc->qh;
+-00642                 if (hctsiz.b.pid == DWC_HCTSIZ_DATA0) {
+-00643                         qh->data_toggle = DWC_OTG_HC_PID_DATA0;
+-00644                 } else {
+-00645                         qh->data_toggle = DWC_OTG_HC_PID_DATA1;
+-00646                 }
+-00647         } else {
+-00648                 if (hctsiz.b.pid == DWC_HCTSIZ_DATA0) {
+-00649                         qtd->data_toggle = DWC_OTG_HC_PID_DATA0;
+-00650                 } else {
+-00651                         qtd->data_toggle = DWC_OTG_HC_PID_DATA1;
+-00652                 }
+-00653         }
+-00654 }
+-00655 
+-00665 static dwc_otg_halt_status_e
+-00666 update_isoc_urb_state(dwc_otg_hcd_t * hcd,
+-00667                       dwc_hc_t * hc,
+-00668                       dwc_otg_hc_regs_t * hc_regs,
+-00669                       dwc_otg_qtd_t * qtd, dwc_otg_halt_status_e halt_status)
+-00670 {
+-00671         dwc_otg_hcd_urb_t *urb = qtd->urb;
+-00672         dwc_otg_halt_status_e ret_val = halt_status;
+-00673         struct dwc_otg_hcd_iso_packet_desc *frame_desc;
+-00674 
+-00675         frame_desc = &urb->iso_descs[qtd->isoc_frame_index];
+-00676         switch (halt_status) {
+-00677         case DWC_OTG_HC_XFER_COMPLETE:
+-00678                 frame_desc->status = 0;
+-00679                 frame_desc->actual_length =
+-00680                     get_actual_xfer_length(hc, hc_regs, qtd, halt_status, NULL);
+-00681 
+-00682                 /* non DWORD-aligned buffer case handling. */
+-00683                 if (hc->align_buff && frame_desc->actual_length && hc->ep_is_in) {
+-00684                         dwc_memcpy(urb->buf + frame_desc->offset + qtd->isoc_split_offset,
+-00685                                    hc->qh->dw_align_buf, frame_desc->actual_length);
+-00686                 }
+-00687                 
+-00688                 break;
+-00689         case DWC_OTG_HC_XFER_FRAME_OVERRUN:
+-00690                 urb->error_count++;
+-00691                 if (hc->ep_is_in) {
+-00692                         frame_desc->status = -DWC_E_NO_STREAM_RES;
+-00693                 } else {
+-00694                         frame_desc->status = -DWC_E_COMMUNICATION;
+-00695                 }
+-00696                 frame_desc->actual_length = 0;
+-00697                 break;
+-00698         case DWC_OTG_HC_XFER_BABBLE_ERR:
+-00699                 urb->error_count++;
+-00700                 frame_desc->status = -DWC_E_OVERFLOW;
+-00701                 /* Don't need to update actual_length in this case. */
+-00702                 break;
+-00703         case DWC_OTG_HC_XFER_XACT_ERR:
+-00704                 urb->error_count++;
+-00705                 frame_desc->status = -DWC_E_PROTOCOL;
+-00706                 frame_desc->actual_length =
+-00707                     get_actual_xfer_length(hc, hc_regs, qtd, halt_status, NULL);
+-00708 
+-00709                 /* non DWORD-aligned buffer case handling. */
+-00710                 if (hc->align_buff && frame_desc->actual_length && hc->ep_is_in) {
+-00711                         dwc_memcpy(urb->buf + frame_desc->offset + qtd->isoc_split_offset,
+-00712                                    hc->qh->dw_align_buf, frame_desc->actual_length);
+-00713                 }
+-00714                 /* Skip whole frame */
+-00715                 if (hc->qh->do_split && (hc->ep_type == DWC_OTG_EP_TYPE_ISOC) &&
+-00716                     hc->ep_is_in && hcd->core_if->dma_enable) {
+-00717                         qtd->complete_split = 0;
+-00718                         qtd->isoc_split_offset = 0;
+-00719                 }
+-00720 
+-00721                 break;
+-00722         default:
+-00723                 DWC_ASSERT(1, "Unhandled _halt_status (%d)\n", halt_status);
+-00724                 break;
+-00725         }
+-00726         if (++qtd->isoc_frame_index == urb->packet_count) {
+-00727                 /*
+-00728                  * urb->status is not used for isoc transfers.
+-00729                  * The individual frame_desc statuses are used instead.
+-00730                  */
+-00731                 hcd->fops->complete(hcd, urb->priv, urb, 0);
+-00732                 ret_val = DWC_OTG_HC_XFER_URB_COMPLETE;
+-00733         } else {
+-00734                 ret_val = DWC_OTG_HC_XFER_COMPLETE;
+-00735         }
+-00736         return ret_val;
+-00737 }
+-00738 
+-00746 static void deactivate_qh(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh, int free_qtd)
+-00747 {
+-00748         int continue_split = 0;
+-00749         dwc_otg_qtd_t *qtd;
+-00750 
+-00751         DWC_DEBUGPL(DBG_HCDV, "  %s(%p,%p,%d)\n", __func__, hcd, qh, free_qtd);
+-00752 
+-00753         qtd = DWC_CIRCLEQ_FIRST(&qh->qtd_list);
+-00754 
+-00755         if (qtd->complete_split) {
+-00756                 continue_split = 1;
+-00757         } else if (qtd->isoc_split_pos == DWC_HCSPLIT_XACTPOS_MID ||
+-00758                    qtd->isoc_split_pos == DWC_HCSPLIT_XACTPOS_END) {
+-00759                 continue_split = 1;
+-00760         }
+-00761 
+-00762         if (free_qtd) {
+-00763                 dwc_otg_hcd_qtd_remove_and_free(hcd, qtd, qh);
+-00764                 continue_split = 0;
+-00765         }
+-00766 
+-00767         qh->channel = NULL;
+-00768         dwc_otg_hcd_qh_deactivate(hcd, qh, continue_split);
+-00769 }
+-00770 
+-00782 static void release_channel(dwc_otg_hcd_t * hcd,
+-00783                             dwc_hc_t * hc,
+-00784                             dwc_otg_qtd_t * qtd,
+-00785                             dwc_otg_halt_status_e halt_status)
+-00786 {
+-00787         dwc_otg_transaction_type_e tr_type;
+-00788         int free_qtd;
+-00789 
+-00790         DWC_DEBUGPL(DBG_HCDV, "  %s: channel %d, halt_status %d\n",
+-00791                     __func__, hc->hc_num, halt_status);
+-00792 
+-00793         switch (halt_status) {
+-00794         case DWC_OTG_HC_XFER_URB_COMPLETE:
+-00795                 free_qtd = 1;
+-00796                 break;
+-00797         case DWC_OTG_HC_XFER_AHB_ERR:
+-00798         case DWC_OTG_HC_XFER_STALL:
+-00799         case DWC_OTG_HC_XFER_BABBLE_ERR:
+-00800                 free_qtd = 1;
+-00801                 break;
+-00802         case DWC_OTG_HC_XFER_XACT_ERR:
+-00803                 if (qtd->error_count >= 3) {
+-00804                         DWC_DEBUGPL(DBG_HCDV,
+-00805                                     "  Complete URB with transaction error\n");
+-00806                         free_qtd = 1;
+-00807                         qtd->urb->status = -DWC_E_PROTOCOL;
+-00808                         hcd->fops->complete(hcd, qtd->urb->priv,
+-00809                                             qtd->urb, -DWC_E_PROTOCOL);
+-00810                 } else {
+-00811                         free_qtd = 0;
+-00812                 }
+-00813                 break;
+-00814         case DWC_OTG_HC_XFER_URB_DEQUEUE:
+-00815                 /*
+-00816                  * The QTD has already been removed and the QH has been
+-00817                  * deactivated. Don't want to do anything except release the
+-00818                  * host channel and try to queue more transfers.
+-00819                  */
+-00820                 goto cleanup;
+-00821         case DWC_OTG_HC_XFER_NO_HALT_STATUS:
+-00822                 free_qtd = 0;
+-00823                 break;
+-00824         case DWC_OTG_HC_XFER_PERIODIC_INCOMPLETE:
+-00825                 DWC_DEBUGPL(DBG_HCDV,
+-00826                         "  Complete URB with I/O error\n");
+-00827                 free_qtd = 1;
+-00828                 qtd->urb->status = -DWC_E_IO;
+-00829                 hcd->fops->complete(hcd, qtd->urb->priv,
+-00830                         qtd->urb, -DWC_E_IO);
+-00831                 break;
+-00832         default:
+-00833                 free_qtd = 0;
+-00834                 break;
+-00835         }
+-00836 
+-00837         deactivate_qh(hcd, hc->qh, free_qtd);
+-00838 
+-00839 cleanup:
+-00840         /*
+-00841          * Release the host channel for use by other transfers. The cleanup
+-00842          * function clears the channel interrupt enables and conditions, so
+-00843          * there's no need to clear the Channel Halted interrupt separately.
+-00844          */
+-00845         dwc_otg_hc_cleanup(hcd->core_if, hc);
+-00846         DWC_CIRCLEQ_INSERT_TAIL(&hcd->free_hc_list, hc, hc_list_entry);
+-00847 
+-00848         switch (hc->ep_type) {
+-00849         case DWC_OTG_EP_TYPE_CONTROL:
+-00850         case DWC_OTG_EP_TYPE_BULK:
+-00851                 hcd->non_periodic_channels--;
+-00852                 break;
+-00853 
+-00854         default:
+-00855                 /*
+-00856                  * Don't release reservations for periodic channels here.
+-00857                  * That's done when a periodic transfer is descheduled (i.e.
+-00858                  * when the QH is removed from the periodic schedule).
+-00859                  */
+-00860                 break;
+-00861         }
+-00862 
+-00863         /* Try to queue more transfers now that there's a free channel. */
+-00864         tr_type = dwc_otg_hcd_select_transactions(hcd);
+-00865         if (tr_type != DWC_OTG_TRANSACTION_NONE) {
+-00866                 dwc_otg_hcd_queue_transactions(hcd, tr_type);
+-00867         }
+-00868 }
+-00869 
+-00880 static void halt_channel(dwc_otg_hcd_t * hcd,
+-00881                          dwc_hc_t * hc,
+-00882                          dwc_otg_qtd_t * qtd, dwc_otg_halt_status_e halt_status)
+-00883 {
+-00884         if (hcd->core_if->dma_enable) {
+-00885                 release_channel(hcd, hc, qtd, halt_status);
+-00886                 return;
+-00887         }
+-00888 
+-00889         /* Slave mode processing... */
+-00890         dwc_otg_hc_halt(hcd->core_if, hc, halt_status);
+-00891 
+-00892         if (hc->halt_on_queue) {
+-00893                 gintmsk_data_t gintmsk = {.d32 = 0 };
+-00894                 dwc_otg_core_global_regs_t *global_regs;
+-00895                 global_regs = hcd->core_if->core_global_regs;
+-00896 
+-00897                 if (hc->ep_type == DWC_OTG_EP_TYPE_CONTROL ||
+-00898                     hc->ep_type == DWC_OTG_EP_TYPE_BULK) {
+-00899                         /*
+-00900                          * Make sure the Non-periodic Tx FIFO empty interrupt
+-00901                          * is enabled so that the non-periodic schedule will
+-00902                          * be processed.
+-00903                          */
+-00904                         gintmsk.b.nptxfempty = 1;
+-00905                         DWC_MODIFY_REG32(&global_regs->gintmsk, 0, gintmsk.d32);
+-00906                 } else {
+-00907                         /*
+-00908                          * Move the QH from the periodic queued schedule to
+-00909                          * the periodic assigned schedule. This allows the
+-00910                          * halt to be queued when the periodic schedule is
+-00911                          * processed.
+-00912                          */
+-00913                         DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_assigned,
+-00914                                            &hc->qh->qh_list_entry);
+-00915 
+-00916                         /*
+-00917                          * Make sure the Periodic Tx FIFO Empty interrupt is
+-00918                          * enabled so that the periodic schedule will be
+-00919                          * processed.
+-00920                          */
+-00921                         gintmsk.b.ptxfempty = 1;
+-00922                         DWC_MODIFY_REG32(&global_regs->gintmsk, 0, gintmsk.d32);
+-00923                 }
+-00924         }
+-00925 }
+-00926 
+-00932 static void complete_non_periodic_xfer(dwc_otg_hcd_t * hcd,
+-00933                                        dwc_hc_t * hc,
+-00934                                        dwc_otg_hc_regs_t * hc_regs,
+-00935                                        dwc_otg_qtd_t * qtd,
+-00936                                        dwc_otg_halt_status_e halt_status)
+-00937 {
+-00938         hcint_data_t hcint;
+-00939 
+-00940         qtd->error_count = 0;
+-00941 
+-00942         hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
+-00943         if (hcint.b.nyet) {
+-00944                 /*
+-00945                  * Got a NYET on the last transaction of the transfer. This
+-00946                  * means that the endpoint should be in the PING state at the
+-00947                  * beginning of the next transfer.
+-00948                  */
+-00949                 hc->qh->ping_state = 1;
+-00950                 clear_hc_int(hc_regs, nyet);
+-00951         }
+-00952 
+-00953         /*
+-00954          * Always halt and release the host channel to make it available for
+-00955          * more transfers. There may still be more phases for a control
+-00956          * transfer or more data packets for a bulk transfer at this point,
+-00957          * but the host channel is still halted. A channel will be reassigned
+-00958          * to the transfer when the non-periodic schedule is processed after
+-00959          * the channel is released. This allows transactions to be queued
+-00960          * properly via dwc_otg_hcd_queue_transactions, which also enables the
+-00961          * Tx FIFO Empty interrupt if necessary.
+-00962          */
+-00963         if (hc->ep_is_in) {
+-00964                 /*
+-00965                  * IN transfers in Slave mode require an explicit disable to
+-00966                  * halt the channel. (In DMA mode, this call simply releases
+-00967                  * the channel.)
+-00968                  */
+-00969                 halt_channel(hcd, hc, qtd, halt_status);
+-00970         } else {
+-00971                 /*
+-00972                  * The channel is automatically disabled by the core for OUT
+-00973                  * transfers in Slave mode.
+-00974                  */
+-00975                 release_channel(hcd, hc, qtd, halt_status);
+-00976         }
+-00977 }
+-00978 
+-00984 static void complete_periodic_xfer(dwc_otg_hcd_t * hcd,
+-00985                                    dwc_hc_t * hc,
+-00986                                    dwc_otg_hc_regs_t * hc_regs,
+-00987                                    dwc_otg_qtd_t * qtd,
+-00988                                    dwc_otg_halt_status_e halt_status)
+-00989 {
+-00990         hctsiz_data_t hctsiz;
+-00991         qtd->error_count = 0;
+-00992 
+-00993         hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
+-00994         if (!hc->ep_is_in || hctsiz.b.pktcnt == 0) {
+-00995                 /* Core halts channel in these cases. */
+-00996                 release_channel(hcd, hc, qtd, halt_status);
+-00997         } else {
+-00998                 /* Flush any outstanding requests from the Tx queue. */
+-00999                 halt_channel(hcd, hc, qtd, halt_status);
+-01000         }
+-01001 }
+-01002 
+-01003 static int32_t handle_xfercomp_isoc_split_in(dwc_otg_hcd_t * hcd,
+-01004                                              dwc_hc_t * hc,
+-01005                                              dwc_otg_hc_regs_t * hc_regs,
+-01006                                              dwc_otg_qtd_t * qtd)
+-01007 {
+-01008         uint32_t len;
+-01009         struct dwc_otg_hcd_iso_packet_desc *frame_desc;
+-01010         frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index];
+-01011 
+-01012         len = get_actual_xfer_length(hc, hc_regs, qtd,
+-01013                                      DWC_OTG_HC_XFER_COMPLETE, NULL);
+-01014 
+-01015         if (!len) {
+-01016                 qtd->complete_split = 0;
+-01017                 qtd->isoc_split_offset = 0;
+-01018                 return 0;
+-01019         }
+-01020         frame_desc->actual_length += len;
+-01021 
+-01022         if (hc->align_buff && len)
+-01023                 dwc_memcpy(qtd->urb->buf + frame_desc->offset +
+-01024                            qtd->isoc_split_offset, hc->qh->dw_align_buf, len);
+-01025         qtd->isoc_split_offset += len;
+-01026 
+-01027         if (frame_desc->length == frame_desc->actual_length) {
+-01028                 frame_desc->status = 0;
+-01029                 qtd->isoc_frame_index++;
+-01030                 qtd->complete_split = 0;
+-01031                 qtd->isoc_split_offset = 0;
+-01032         }
+-01033 
+-01034         if (qtd->isoc_frame_index == qtd->urb->packet_count) {
+-01035                 hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, 0);
+-01036                 release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE);
+-01037         } else {
+-01038                 release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NO_HALT_STATUS);
+-01039         }
+-01040 
+-01041         return 1;               /* Indicates that channel released */
+-01042 }
+-01043 
+-01048 static int32_t handle_hc_xfercomp_intr(dwc_otg_hcd_t * hcd,
+-01049                                        dwc_hc_t * hc,
+-01050                                        dwc_otg_hc_regs_t * hc_regs,
+-01051                                        dwc_otg_qtd_t * qtd)
+-01052 {
+-01053         int urb_xfer_done;
+-01054         dwc_otg_halt_status_e halt_status = DWC_OTG_HC_XFER_COMPLETE;
+-01055         dwc_otg_hcd_urb_t *urb = qtd->urb;
+-01056         int pipe_type = dwc_otg_hcd_get_pipe_type(&urb->pipe_info);
+-01057 
+-01058         DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
+-01059                     "Transfer Complete--\n", hc->hc_num);
+-01060 
+-01061         if (hcd->core_if->dma_desc_enable) {
+-01062                 dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs, halt_status);
+-01063                 if (pipe_type == UE_ISOCHRONOUS) {
+-01064                         /* Do not disable the interrupt, just clear it */
+-01065                         clear_hc_int(hc_regs, xfercomp);
+-01066                         return 1;
+-01067                 }
+-01068                 goto handle_xfercomp_done;
+-01069         }
+-01070 
+-01071         /*
+-01072          * Handle xfer complete on CSPLIT.
+-01073          */
+-01074 
+-01075         if (hc->qh->do_split) {
+-01076                 if ((hc->ep_type == DWC_OTG_EP_TYPE_ISOC) && hc->ep_is_in
+-01077                     && hcd->core_if->dma_enable) {
+-01078                         if (qtd->complete_split
+-01079                             && handle_xfercomp_isoc_split_in(hcd, hc, hc_regs,
+-01080                                                              qtd))
+-01081                                 goto handle_xfercomp_done;
+-01082                 } else {
+-01083                         qtd->complete_split = 0;
+-01084                 }
+-01085         }
+-01086 
+-01087         /* Update the QTD and URB states. */
+-01088         switch (pipe_type) {
+-01089         case UE_CONTROL:
+-01090                 switch (qtd->control_phase) {
+-01091                 case DWC_OTG_CONTROL_SETUP:
+-01092                         if (urb->length > 0) {
+-01093                                 qtd->control_phase = DWC_OTG_CONTROL_DATA;
+-01094                         } else {
+-01095                                 qtd->control_phase = DWC_OTG_CONTROL_STATUS;
+-01096                         }
+-01097                         DWC_DEBUGPL(DBG_HCDV,
+-01098                                     "  Control setup transaction done\n");
+-01099                         halt_status = DWC_OTG_HC_XFER_COMPLETE;
+-01100                         break;
+-01101                 case DWC_OTG_CONTROL_DATA:{
+-01102                                 urb_xfer_done =
+-01103                                     update_urb_state_xfer_comp(hc, hc_regs, urb,
+-01104                                                                qtd);
+-01105                                 if (urb_xfer_done) {
+-01106                                         qtd->control_phase =
+-01107                                             DWC_OTG_CONTROL_STATUS;
+-01108                                         DWC_DEBUGPL(DBG_HCDV,
+-01109                                                     "  Control data transfer done\n");
+-01110                                 } else {
+-01111                                         dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
+-01112                                 }
+-01113                                 halt_status = DWC_OTG_HC_XFER_COMPLETE;
+-01114                                 break;
+-01115                         }
+-01116                 case DWC_OTG_CONTROL_STATUS:
+-01117                         DWC_DEBUGPL(DBG_HCDV, "  Control transfer complete\n");
+-01118                         if (urb->status == -DWC_E_IN_PROGRESS) {
+-01119                                 urb->status = 0;
+-01120                         }
+-01121                         hcd->fops->complete(hcd, urb->priv, urb, urb->status);
+-01122                         halt_status = DWC_OTG_HC_XFER_URB_COMPLETE;
+-01123                         break;
+-01124                 }
+-01125 
+-01126                 complete_non_periodic_xfer(hcd, hc, hc_regs, qtd, halt_status);
+-01127                 break;
+-01128         case UE_BULK:
+-01129                 DWC_DEBUGPL(DBG_HCDV, "  Bulk transfer complete\n");
+-01130                 urb_xfer_done =
+-01131                     update_urb_state_xfer_comp(hc, hc_regs, urb, qtd);
+-01132                 if (urb_xfer_done) {
+-01133                         hcd->fops->complete(hcd, urb->priv, urb, urb->status);
+-01134                         halt_status = DWC_OTG_HC_XFER_URB_COMPLETE;
+-01135                 } else {
+-01136                         halt_status = DWC_OTG_HC_XFER_COMPLETE;
+-01137                 }
+-01138 
+-01139                 dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
+-01140                 complete_non_periodic_xfer(hcd, hc, hc_regs, qtd, halt_status);
+-01141                 break;
+-01142         case UE_INTERRUPT:
+-01143                 DWC_DEBUGPL(DBG_HCDV, "  Interrupt transfer complete\n");
+-01144                 urb_xfer_done =
+-01145                         update_urb_state_xfer_comp(hc, hc_regs, urb, qtd);
+-01146 
+-01147                 /*
+-01148                  * Interrupt URB is done on the first transfer complete
+-01149                  * interrupt.
+-01150                  */
+-01151                 if (urb_xfer_done) {
+-01152                                 hcd->fops->complete(hcd, urb->priv, urb, urb->status);
+-01153                                 halt_status = DWC_OTG_HC_XFER_URB_COMPLETE;
+-01154                 } else {
+-01155                                 halt_status = DWC_OTG_HC_XFER_COMPLETE;
+-01156                 }
+-01157 
+-01158                 dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
+-01159                 complete_periodic_xfer(hcd, hc, hc_regs, qtd, halt_status);
+-01160                 break;
+-01161         case UE_ISOCHRONOUS:
+-01162                 DWC_DEBUGPL(DBG_HCDV, "  Isochronous transfer complete\n");
+-01163                 if (qtd->isoc_split_pos == DWC_HCSPLIT_XACTPOS_ALL) {
+-01164                         halt_status =
+-01165                             update_isoc_urb_state(hcd, hc, hc_regs, qtd,
+-01166                                                   DWC_OTG_HC_XFER_COMPLETE);
+-01167                 }
+-01168                 complete_periodic_xfer(hcd, hc, hc_regs, qtd, halt_status);
+-01169                 break;
+-01170         }
+-01171 
+-01172 handle_xfercomp_done:
+-01173         disable_hc_int(hc_regs, xfercompl);
+-01174 
+-01175         return 1;
+-01176 }
+-01177 
+-01182 static int32_t handle_hc_stall_intr(dwc_otg_hcd_t * hcd,
+-01183                                     dwc_hc_t * hc,
+-01184                                     dwc_otg_hc_regs_t * hc_regs,
+-01185                                     dwc_otg_qtd_t * qtd)
+-01186 {
+-01187         dwc_otg_hcd_urb_t *urb = qtd->urb;
+-01188         int pipe_type = dwc_otg_hcd_get_pipe_type(&urb->pipe_info);
+-01189 
+-01190         DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
+-01191                     "STALL Received--\n", hc->hc_num);
+-01192 
+-01193         if (hcd->core_if->dma_desc_enable) {
+-01194                 dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs, DWC_OTG_HC_XFER_STALL);
+-01195                 goto handle_stall_done;
+-01196         }
+-01197 
+-01198         if (pipe_type == UE_CONTROL) {
+-01199                 hcd->fops->complete(hcd, urb->priv, urb, -DWC_E_PIPE);
+-01200         }
+-01201 
+-01202         if (pipe_type == UE_BULK || pipe_type == UE_INTERRUPT) {
+-01203                 hcd->fops->complete(hcd, urb->priv, urb, -DWC_E_PIPE);
+-01204                 /*
+-01205                  * USB protocol requires resetting the data toggle for bulk
+-01206                  * and interrupt endpoints when a CLEAR_FEATURE(ENDPOINT_HALT)
+-01207                  * setup command is issued to the endpoint. Anticipate the
+-01208                  * CLEAR_FEATURE command since a STALL has occurred and reset
+-01209                  * the data toggle now.
+-01210                  */
+-01211                 hc->qh->data_toggle = 0;
+-01212         }
+-01213 
+-01214         halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_STALL);
+-01215 
+-01216 handle_stall_done:
+-01217         disable_hc_int(hc_regs, stall);
+-01218 
+-01219         return 1;
+-01220 }
+-01221 
+-01222 /*
+-01223  * Updates the state of the URB when a transfer has been stopped due to an
+-01224  * abnormal condition before the transfer completes. Modifies the
+-01225  * actual_length field of the URB to reflect the number of bytes that have
+-01226  * actually been transferred via the host channel.
+-01227  */
+-01228 static void update_urb_state_xfer_intr(dwc_hc_t * hc,
+-01229                                        dwc_otg_hc_regs_t * hc_regs,
+-01230                                        dwc_otg_hcd_urb_t * urb,
+-01231                                        dwc_otg_qtd_t * qtd,
+-01232                                        dwc_otg_halt_status_e halt_status)
+-01233 {
+-01234         uint32_t bytes_transferred = get_actual_xfer_length(hc, hc_regs, qtd,
+-01235                                                             halt_status, NULL);
+-01236         /* non DWORD-aligned buffer case handling. */
+-01237         if (hc->align_buff && bytes_transferred && hc->ep_is_in) {
+-01238                 dwc_memcpy(urb->buf + urb->actual_length, hc->qh->dw_align_buf,
+-01239                            bytes_transferred);
+-01240         }
+-01241 
+-01242         urb->actual_length += bytes_transferred;
+-01243 
+-01244 #ifdef DEBUG
+-01245         {
+-01246                 hctsiz_data_t hctsiz;
+-01247                 hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
+-01248                 DWC_DEBUGPL(DBG_HCDV, "DWC_otg: %s: %s, channel %d\n",
+-01249                             __func__, (hc->ep_is_in ? "IN" : "OUT"),
+-01250                             hc->hc_num);
+-01251                 DWC_DEBUGPL(DBG_HCDV, "  hc->start_pkt_count %d\n",
+-01252                             hc->start_pkt_count);
+-01253                 DWC_DEBUGPL(DBG_HCDV, "  hctsiz.pktcnt %d\n", hctsiz.b.pktcnt);
+-01254                 DWC_DEBUGPL(DBG_HCDV, "  hc->max_packet %d\n", hc->max_packet);
+-01255                 DWC_DEBUGPL(DBG_HCDV, "  bytes_transferred %d\n",
+-01256                             bytes_transferred);
+-01257                 DWC_DEBUGPL(DBG_HCDV, "  urb->actual_length %d\n",
+-01258                             urb->actual_length);
+-01259                 DWC_DEBUGPL(DBG_HCDV, "  urb->transfer_buffer_length %d\n",
+-01260                             urb->length);
+-01261         }
+-01262 #endif
+-01263 }
+-01264 
+-01269 static int32_t handle_hc_nak_intr(dwc_otg_hcd_t * hcd,
+-01270                                   dwc_hc_t * hc,
+-01271                                   dwc_otg_hc_regs_t * hc_regs,
+-01272                                   dwc_otg_qtd_t * qtd)
+-01273 {
+-01274         DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
+-01275                     "NAK Received--\n", hc->hc_num);
+-01276 
+-01277         /*
+-01278          * Handle NAK for IN/OUT SSPLIT/CSPLIT transfers, bulk, control, and
+-01279          * interrupt.  Re-start the SSPLIT transfer.
+-01280          */
+-01281         if (hc->do_split) {
+-01282                 if (hc->complete_split) {
+-01283                         qtd->error_count = 0;
+-01284                 }
+-01285                 qtd->complete_split = 0;
+-01286                 halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NAK);
+-01287                 goto handle_nak_done;
+-01288         }
+-01289 
+-01290         switch (dwc_otg_hcd_get_pipe_type(&qtd->urb->pipe_info)) {
+-01291         case UE_CONTROL:
+-01292         case UE_BULK:
+-01293                 if (hcd->core_if->dma_enable && hc->ep_is_in) {
+-01294                         /*
+-01295                          * NAK interrupts are enabled on bulk/control IN
+-01296                          * transfers in DMA mode for the sole purpose of
+-01297                          * resetting the error count after a transaction error
+-01298                          * occurs. The core will continue transferring data.
+-01299                          */
+-01300                         qtd->error_count = 0;
+-01301                         goto handle_nak_done;
+-01302                 }
+-01303 
+-01304                 /*
+-01305                  * NAK interrupts normally occur during OUT transfers in DMA
+-01306                  * or Slave mode. For IN transfers, more requests will be
+-01307                  * queued as request queue space is available.
+-01308                  */
+-01309                 qtd->error_count = 0;
+-01310 
+-01311                 if (!hc->qh->ping_state) {
+-01312                         update_urb_state_xfer_intr(hc, hc_regs,
+-01313                                                    qtd->urb, qtd,
+-01314                                                    DWC_OTG_HC_XFER_NAK);
+-01315                         dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
+-01316 
+-01317                         if (hc->speed == DWC_OTG_EP_SPEED_HIGH)
+-01318                                 hc->qh->ping_state = 1;
+-01319                 }
+-01320 
+-01321                 /*
+-01322                  * Halt the channel so the transfer can be re-started from
+-01323                  * the appropriate point or the PING protocol will
+-01324                  * start/continue.
+-01325                  */
+-01326                 halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NAK);
+-01327                 break;
+-01328         case UE_INTERRUPT:
+-01329                 qtd->error_count = 0;
+-01330                 halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NAK);
+-01331                 break;
+-01332         case UE_ISOCHRONOUS:
+-01333                 /* Should never get called for isochronous transfers. */
+-01334                 DWC_ASSERT(1, "NACK interrupt for ISOC transfer\n");
+-01335                 break;
+-01336         }
+-01337 
+-01338 handle_nak_done:
+-01339         disable_hc_int(hc_regs, nak);
+-01340 
+-01341         return 1;
+-01342 }
+-01343 
+-01349 static int32_t handle_hc_ack_intr(dwc_otg_hcd_t * hcd,
+-01350                                   dwc_hc_t * hc,
+-01351                                   dwc_otg_hc_regs_t * hc_regs,
+-01352                                   dwc_otg_qtd_t * qtd)
+-01353 {
+-01354         DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
+-01355                     "ACK Received--\n", hc->hc_num);
+-01356 
+-01357         if (hc->do_split) {
+-01358                 /*
+-01359                  * Handle ACK on SSPLIT.
+-01360                  * ACK should not occur in CSPLIT.
+-01361                  */
+-01362                 if (!hc->ep_is_in && hc->data_pid_start != DWC_OTG_HC_PID_SETUP) {
+-01363                         qtd->ssplit_out_xfer_count = hc->xfer_len;
+-01364                 }
+-01365                 if (!(hc->ep_type == DWC_OTG_EP_TYPE_ISOC && !hc->ep_is_in)) {
+-01366                         /* Don't need complete for isochronous out transfers. */
+-01367                         qtd->complete_split = 1;
+-01368                 }
+-01369 
+-01370                 /* ISOC OUT */
+-01371                 if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC && !hc->ep_is_in) {
+-01372                         switch (hc->xact_pos) {
+-01373                         case DWC_HCSPLIT_XACTPOS_ALL:
+-01374                                 break;
+-01375                         case DWC_HCSPLIT_XACTPOS_END:
+-01376                                 qtd->isoc_split_pos = DWC_HCSPLIT_XACTPOS_ALL;
+-01377                                 qtd->isoc_split_offset = 0;
+-01378                                 break;
+-01379                         case DWC_HCSPLIT_XACTPOS_BEGIN:
+-01380                         case DWC_HCSPLIT_XACTPOS_MID:
+-01381                                 /*
+-01382                                  * For BEGIN or MID, calculate the length for
+-01383                                  * the next microframe to determine the correct
+-01384                                  * SSPLIT token, either MID or END.
+-01385                                  */
+-01386                                 {
+-01387                                         struct dwc_otg_hcd_iso_packet_desc
+-01388                                         *frame_desc;
+-01389 
+-01390                                         frame_desc =
+-01391                                             &qtd->urb->
+-01392                                             iso_descs[qtd->isoc_frame_index];
+-01393                                         qtd->isoc_split_offset += 188;
+-01394 
+-01395                                         if ((frame_desc->length -
+-01396                                              qtd->isoc_split_offset) <= 188) {
+-01397                                                 qtd->isoc_split_pos =
+-01398                                                     DWC_HCSPLIT_XACTPOS_END;
+-01399                                         } else {
+-01400                                                 qtd->isoc_split_pos =
+-01401                                                     DWC_HCSPLIT_XACTPOS_MID;
+-01402                                         }
+-01403 
+-01404                                 }
+-01405                                 break;
+-01406                         }
+-01407                 } else {
+-01408                         halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_ACK);
+-01409                 }
+-01410         } else {
+-01411                 qtd->error_count = 0;
+-01412 
+-01413                 if (hc->qh->ping_state) {
+-01414                         hc->qh->ping_state = 0;
+-01415                         /*
+-01416                          * Halt the channel so the transfer can be re-started
+-01417                          * from the appropriate point. This only happens in
+-01418                          * Slave mode. In DMA mode, the ping_state is cleared
+-01419                          * when the transfer is started because the core
+-01420                          * automatically executes the PING, then the transfer.
+-01421                          */
+-01422                         halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_ACK);
+-01423                 }
+-01424         }
+-01425 
+-01426         /*
+-01427          * If the ACK occurred when _not_ in the PING state, let the channel
+-01428          * continue transferring data after clearing the error count.
+-01429          */
+-01430 
+-01431         disable_hc_int(hc_regs, ack);
+-01432 
+-01433         return 1;
+-01434 }
+-01435 
+-01443 static int32_t handle_hc_nyet_intr(dwc_otg_hcd_t * hcd,
+-01444                                    dwc_hc_t * hc,
+-01445                                    dwc_otg_hc_regs_t * hc_regs,
+-01446                                    dwc_otg_qtd_t * qtd)
+-01447 {
+-01448         DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
+-01449                     "NYET Received--\n", hc->hc_num);
+-01450 
+-01451         /*
+-01452          * NYET on CSPLIT
+-01453          * re-do the CSPLIT immediately on non-periodic
+-01454          */
+-01455         if (hc->do_split && hc->complete_split) {
+-01456                 if (hc->ep_is_in && (hc->ep_type == DWC_OTG_EP_TYPE_ISOC)
+-01457                     && hcd->core_if->dma_enable) {
+-01458                         qtd->complete_split = 0;
+-01459                         qtd->isoc_split_offset = 0;
+-01460                         if (++qtd->isoc_frame_index == qtd->urb->packet_count) {
+-01461                                 hcd->fops->complete(hcd, qtd->urb->priv, qtd->urb, 0);
+-01462                                 release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_URB_COMPLETE);    
+-01463                         }
+-01464                         else
+-01465                                 release_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NO_HALT_STATUS);  
+-01466                         goto handle_nyet_done;
+-01467                 }
+-01468                 
+-01469                 if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
+-01470                     hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
+-01471                         int frnum = dwc_otg_hcd_get_frame_number(hcd);
+-01472 
+-01473                         if (dwc_full_frame_num(frnum) !=
+-01474                             dwc_full_frame_num(hc->qh->sched_frame)) {
+-01475                                 /*
+-01476                                  * No longer in the same full speed frame.
+-01477                                  * Treat this as a transaction error.
+-01478                                  */
+-01479 #if 0
+-01480 
+-01486                                 qtd->error_count++;
+-01487 #endif
+-01488                                 qtd->complete_split = 0;
+-01489                                 halt_channel(hcd, hc, qtd,
+-01490                                              DWC_OTG_HC_XFER_XACT_ERR);
+-01492                                 goto handle_nyet_done;
+-01493                         }
+-01494                 }
+-01495 
+-01496                 halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NYET);
+-01497                 goto handle_nyet_done;
+-01498         }
+-01499 
+-01500         hc->qh->ping_state = 1;
+-01501         qtd->error_count = 0;
+-01502 
+-01503         update_urb_state_xfer_intr(hc, hc_regs, qtd->urb, qtd,
+-01504                                    DWC_OTG_HC_XFER_NYET);
+-01505         dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
+-01506 
+-01507         /*
+-01508          * Halt the channel and re-start the transfer so the PING
+-01509          * protocol will start.
+-01510          */
+-01511         halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NYET);
+-01512 
+-01513 handle_nyet_done:
+-01514         disable_hc_int(hc_regs, nyet);
+-01515         return 1;
+-01516 }
+-01517 
+-01522 static int32_t handle_hc_babble_intr(dwc_otg_hcd_t * hcd,
+-01523                                      dwc_hc_t * hc,
+-01524                                      dwc_otg_hc_regs_t * hc_regs,
+-01525                                      dwc_otg_qtd_t * qtd)
+-01526 {
+-01527         DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
+-01528                     "Babble Error--\n", hc->hc_num);
+-01529 
+-01530         if (hcd->core_if->dma_desc_enable) {
+-01531                 dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs,
+-01532                                                DWC_OTG_HC_XFER_BABBLE_ERR);
+-01533                 goto handle_babble_done;
+-01534         }
+-01535 
+-01536         if (hc->ep_type != DWC_OTG_EP_TYPE_ISOC) {
+-01537                 hcd->fops->complete(hcd, qtd->urb->priv,
+-01538                                     qtd->urb, -DWC_E_OVERFLOW);
+-01539                 halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_BABBLE_ERR);
+-01540         } else {
+-01541                 dwc_otg_halt_status_e halt_status;
+-01542                 halt_status = update_isoc_urb_state(hcd, hc, hc_regs, qtd,
+-01543                                                     DWC_OTG_HC_XFER_BABBLE_ERR);
+-01544                 halt_channel(hcd, hc, qtd, halt_status);
+-01545         }
+-01546 
+-01547 handle_babble_done:
+-01548         disable_hc_int(hc_regs, bblerr);
+-01549         return 1;
+-01550 }
+-01551 
+-01556 static int32_t handle_hc_ahberr_intr(dwc_otg_hcd_t * hcd,
+-01557                                      dwc_hc_t * hc,
+-01558                                      dwc_otg_hc_regs_t * hc_regs,
+-01559                                      dwc_otg_qtd_t * qtd)
+-01560 {
+-01561         hcchar_data_t hcchar;
+-01562         hcsplt_data_t hcsplt;
+-01563         hctsiz_data_t hctsiz;
+-01564         uint32_t hcdma;
+-01565         char *pipetype, *speed;
+-01566 
+-01567         dwc_otg_hcd_urb_t *urb = qtd->urb;
+-01568 
+-01569         DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
+-01570                     "AHB Error--\n", hc->hc_num);
+-01571 
+-01572         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
+-01573         hcsplt.d32 = DWC_READ_REG32(&hc_regs->hcsplt);
+-01574         hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
+-01575         hcdma = DWC_READ_REG32(&hc_regs->hcdma);
+-01576 
+-01577         DWC_ERROR("AHB ERROR, Channel %d\n", hc->hc_num);
+-01578         DWC_ERROR("  hcchar 0x%08x, hcsplt 0x%08x\n", hcchar.d32, hcsplt.d32);
+-01579         DWC_ERROR("  hctsiz 0x%08x, hcdma 0x%08x\n", hctsiz.d32, hcdma);
+-01580         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD URB Enqueue\n");
+-01581         DWC_ERROR("  Device address: %d\n",
+-01582                   dwc_otg_hcd_get_dev_addr(&urb->pipe_info));
+-01583         DWC_ERROR("  Endpoint: %d, %s\n",
+-01584                   dwc_otg_hcd_get_ep_num(&urb->pipe_info),
+-01585                   (dwc_otg_hcd_is_pipe_in(&urb->pipe_info) ? "IN" : "OUT"));
+-01586 
+-01587         switch (dwc_otg_hcd_get_pipe_type(&urb->pipe_info)) {
+-01588         case UE_CONTROL:
+-01589                 pipetype = "CONTROL";
+-01590                 break;
+-01591         case UE_BULK:
+-01592                 pipetype = "BULK";
+-01593                 break;
+-01594         case UE_INTERRUPT:
+-01595                 pipetype = "INTERRUPT";
+-01596                 break;
+-01597         case UE_ISOCHRONOUS:
+-01598                 pipetype = "ISOCHRONOUS";
+-01599                 break;
+-01600         default:
+-01601                 pipetype = "UNKNOWN";
+-01602                 break;
+-01603         }
+-01604 
+-01605         DWC_ERROR("  Endpoint type: %s\n", pipetype);
+-01606 
+-01607         switch (hc->speed) {
+-01608         case DWC_OTG_EP_SPEED_HIGH:
+-01609                 speed = "HIGH";
+-01610                 break;
+-01611         case DWC_OTG_EP_SPEED_FULL:
+-01612                 speed = "FULL";
+-01613                 break;
+-01614         case DWC_OTG_EP_SPEED_LOW:
+-01615                 speed = "LOW";
+-01616                 break;
+-01617         default:
+-01618                 speed = "UNKNOWN";
+-01619                 break;
+-01620         };
+-01621 
+-01622         DWC_ERROR("  Speed: %s\n", speed);
+-01623 
+-01624         DWC_ERROR("  Max packet size: %d\n",
+-01625                   dwc_otg_hcd_get_mps(&urb->pipe_info));
+-01626         DWC_ERROR("  Data buffer length: %d\n", urb->length);
+-01627         DWC_ERROR("  Transfer buffer: %p, Transfer DMA: %p\n",
+-01628                   urb->buf, (void *)urb->dma);
+-01629         DWC_ERROR("  Setup buffer: %p, Setup DMA: %p\n",
+-01630                   urb->setup_packet, (void *)urb->setup_dma);
+-01631         DWC_ERROR("  Interval: %d\n", urb->interval);
+-01632 
+-01633         /* Core haltes the channel for Descriptor DMA mode */
+-01634         if (hcd->core_if->dma_desc_enable) {
+-01635                 dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs,
+-01636                                                DWC_OTG_HC_XFER_AHB_ERR);
+-01637                 goto handle_ahberr_done;
+-01638         }
+-01639 
+-01640         hcd->fops->complete(hcd, urb->priv, urb, -DWC_E_IO);
+-01641 
+-01642         /*
+-01643          * Force a channel halt. Don't call halt_channel because that won't
+-01644          * write to the HCCHARn register in DMA mode to force the halt.
+-01645          */
+-01646         dwc_otg_hc_halt(hcd->core_if, hc, DWC_OTG_HC_XFER_AHB_ERR);
+-01647 handle_ahberr_done:
+-01648         disable_hc_int(hc_regs, ahberr);
+-01649         return 1;
+-01650 }
+-01651 
+-01656 static int32_t handle_hc_xacterr_intr(dwc_otg_hcd_t * hcd,
+-01657                                       dwc_hc_t * hc,
+-01658                                       dwc_otg_hc_regs_t * hc_regs,
+-01659                                       dwc_otg_qtd_t * qtd)
+-01660 {
+-01661         DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
+-01662                     "Transaction Error--\n", hc->hc_num);
+-01663 
+-01664         if (hcd->core_if->dma_desc_enable) {
+-01665                 dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs,
+-01666                                                DWC_OTG_HC_XFER_XACT_ERR);
+-01667                 goto handle_xacterr_done;
+-01668         }
+-01669 
+-01670         switch (dwc_otg_hcd_get_pipe_type(&qtd->urb->pipe_info)) {
+-01671         case UE_CONTROL:
+-01672         case UE_BULK:
+-01673                 qtd->error_count++;
+-01674                 if (!hc->qh->ping_state) {
+-01675 
+-01676                         update_urb_state_xfer_intr(hc, hc_regs,
+-01677                                                    qtd->urb, qtd,
+-01678                                                    DWC_OTG_HC_XFER_XACT_ERR);
+-01679                         dwc_otg_hcd_save_data_toggle(hc, hc_regs, qtd);
+-01680                         if (!hc->ep_is_in && hc->speed == DWC_OTG_EP_SPEED_HIGH) {
+-01681                                 hc->qh->ping_state = 1;
+-01682                         }
+-01683                 }
+-01684 
+-01685                 /*
+-01686                  * Halt the channel so the transfer can be re-started from
+-01687                  * the appropriate point or the PING protocol will start.
+-01688                  */
+-01689                 halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_XACT_ERR);
+-01690                 break;
+-01691         case UE_INTERRUPT:
+-01692                 qtd->error_count++;
+-01693                 if (hc->do_split && hc->complete_split) {
+-01694                         qtd->complete_split = 0;
+-01695                 }
+-01696                 halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_XACT_ERR);
+-01697                 break;
+-01698         case UE_ISOCHRONOUS:
+-01699                 {
+-01700                         dwc_otg_halt_status_e halt_status;
+-01701                         halt_status =
+-01702                             update_isoc_urb_state(hcd, hc, hc_regs, qtd,
+-01703                                                   DWC_OTG_HC_XFER_XACT_ERR);
+-01704 
+-01705                         halt_channel(hcd, hc, qtd, halt_status);
+-01706                 }
+-01707                 break;
+-01708         }
+-01709 handle_xacterr_done:
+-01710         disable_hc_int(hc_regs, xacterr);
+-01711 
+-01712         return 1;
+-01713 }
+-01714 
+-01719 static int32_t handle_hc_frmovrun_intr(dwc_otg_hcd_t * hcd,
+-01720                                        dwc_hc_t * hc,
+-01721                                        dwc_otg_hc_regs_t * hc_regs,
+-01722                                        dwc_otg_qtd_t * qtd)
+-01723 {
+-01724         DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
+-01725                     "Frame Overrun--\n", hc->hc_num);
+-01726 
+-01727         switch (dwc_otg_hcd_get_pipe_type(&qtd->urb->pipe_info)) {
+-01728         case UE_CONTROL:
+-01729         case UE_BULK:
+-01730                 break;
+-01731         case UE_INTERRUPT:
+-01732                 halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_FRAME_OVERRUN);
+-01733                 break;
+-01734         case UE_ISOCHRONOUS:
+-01735                 {
+-01736                         dwc_otg_halt_status_e halt_status;
+-01737                         halt_status =
+-01738                             update_isoc_urb_state(hcd, hc, hc_regs, qtd,
+-01739                                                   DWC_OTG_HC_XFER_FRAME_OVERRUN);
+-01740 
+-01741                         halt_channel(hcd, hc, qtd, halt_status);
+-01742                 }
+-01743                 break;
+-01744         }
+-01745 
+-01746         disable_hc_int(hc_regs, frmovrun);
+-01747 
+-01748         return 1;
+-01749 }
+-01750 
+-01755 static int32_t handle_hc_datatglerr_intr(dwc_otg_hcd_t * hcd,
+-01756                                          dwc_hc_t * hc,
+-01757                                          dwc_otg_hc_regs_t * hc_regs,
+-01758                                          dwc_otg_qtd_t * qtd)
+-01759 {
+-01760         DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
+-01761                     "Data Toggle Error--\n", hc->hc_num);
+-01762 
+-01763         if (hc->ep_is_in) {
+-01764                 qtd->error_count = 0;
+-01765         } else {
+-01766                 DWC_ERROR("Data Toggle Error on OUT transfer,"
+-01767                           "channel %d\n", hc->hc_num);
+-01768         }
+-01769 
+-01770         disable_hc_int(hc_regs, datatglerr);
+-01771 
+-01772         return 1;
+-01773 }
+-01774 
+-01775 #ifdef DEBUG
+-01776 
+-01782 static inline int halt_status_ok(dwc_otg_hcd_t * hcd,
+-01783                                  dwc_hc_t * hc,
+-01784                                  dwc_otg_hc_regs_t * hc_regs,
+-01785                                  dwc_otg_qtd_t * qtd)
+-01786 {
+-01787         hcchar_data_t hcchar;
+-01788         hctsiz_data_t hctsiz;
+-01789         hcint_data_t hcint;
+-01790         hcintmsk_data_t hcintmsk;
+-01791         hcsplt_data_t hcsplt;
+-01792 
+-01793         if (hc->halt_status == DWC_OTG_HC_XFER_NO_HALT_STATUS) {
+-01794                 /*
+-01795                  * This code is here only as a check. This condition should
+-01796                  * never happen. Ignore the halt if it does occur.
+-01797                  */
+-01798                 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
+-01799                 hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
+-01800                 hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
+-01801                 hcintmsk.d32 = DWC_READ_REG32(&hc_regs->hcintmsk);
+-01802                 hcsplt.d32 = DWC_READ_REG32(&hc_regs->hcsplt);
+-01803                 DWC_WARN
+-01804                     ("%s: hc->halt_status == DWC_OTG_HC_XFER_NO_HALT_STATUS, "
+-01805                      "channel %d, hcchar 0x%08x, hctsiz 0x%08x, "
+-01806                      "hcint 0x%08x, hcintmsk 0x%08x, "
+-01807                      "hcsplt 0x%08x, qtd->complete_split %d\n", __func__,
+-01808                      hc->hc_num, hcchar.d32, hctsiz.d32, hcint.d32,
+-01809                      hcintmsk.d32, hcsplt.d32, qtd->complete_split);
+-01810 
+-01811                 DWC_WARN("%s: no halt status, channel %d, ignoring interrupt\n",
+-01812                          __func__, hc->hc_num);
+-01813                 DWC_WARN("\n");
+-01814                 clear_hc_int(hc_regs, chhltd);
+-01815                 return 0;
+-01816         }
+-01817 
+-01818         /*
+-01819          * This code is here only as a check. hcchar.chdis should
+-01820          * never be set when the halt interrupt occurs. Halt the
+-01821          * channel again if it does occur.
+-01822          */
+-01823         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
+-01824         if (hcchar.b.chdis) {
+-01825                 DWC_WARN("%s: hcchar.chdis set unexpectedly, "
+-01826                          "hcchar 0x%08x, trying to halt again\n",
+-01827                          __func__, hcchar.d32);
+-01828                 clear_hc_int(hc_regs, chhltd);
+-01829                 hc->halt_pending = 0;
+-01830                 halt_channel(hcd, hc, qtd, hc->halt_status);
+-01831                 return 0;
+-01832         }
+-01833 
+-01834         return 1;
+-01835 }
+-01836 #endif
+-01837 
+-01842 static void handle_hc_chhltd_intr_dma(dwc_otg_hcd_t * hcd,
+-01843                                       dwc_hc_t * hc,
+-01844                                       dwc_otg_hc_regs_t * hc_regs,
+-01845                                       dwc_otg_qtd_t * qtd)
+-01846 {
+-01847         hcint_data_t hcint;
+-01848         hcintmsk_data_t hcintmsk;
+-01849         int out_nak_enh = 0;
+-01850 
+-01851         /* For core with OUT NAK enhancement, the flow for high-
+-01852          * speed CONTROL/BULK OUT is handled a little differently.
+-01853          */
+-01854         if (hcd->core_if->snpsid >= OTG_CORE_REV_2_71a) {
+-01855                 if (hc->speed == DWC_OTG_EP_SPEED_HIGH && !hc->ep_is_in &&
+-01856                     (hc->ep_type == DWC_OTG_EP_TYPE_CONTROL ||
+-01857                      hc->ep_type == DWC_OTG_EP_TYPE_BULK)) {
+-01858                         out_nak_enh = 1;
+-01859                 }
+-01860         }
+-01861 
+-01862         if (hc->halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE ||
+-01863             (hc->halt_status == DWC_OTG_HC_XFER_AHB_ERR
+-01864              && !hcd->core_if->dma_desc_enable)) {
+-01865                 /*
+-01866                  * Just release the channel. A dequeue can happen on a
+-01867                  * transfer timeout. In the case of an AHB Error, the channel
+-01868                  * was forced to halt because there's no way to gracefully
+-01869                  * recover.
+-01870                  */
+-01871                 if (hcd->core_if->dma_desc_enable)
+-01872                         dwc_otg_hcd_complete_xfer_ddma(hcd, hc, hc_regs,
+-01873                                                        hc->halt_status);
+-01874                 else
+-01875                         release_channel(hcd, hc, qtd, hc->halt_status);
+-01876                 return;
+-01877         }
+-01878 
+-01879         /* Read the HCINTn register to determine the cause for the halt. */
+-01880         hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
+-01881         hcintmsk.d32 = DWC_READ_REG32(&hc_regs->hcintmsk);
+-01882 
+-01883         if (hcint.b.xfercomp) {
+-01890                 if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC && !hc->ep_is_in) {
+-01891                         handle_hc_ack_intr(hcd, hc, hc_regs, qtd);
+-01892                 }
+-01893                 handle_hc_xfercomp_intr(hcd, hc, hc_regs, qtd);
+-01894         } else if (hcint.b.stall) {
+-01895                 handle_hc_stall_intr(hcd, hc, hc_regs, qtd);
+-01896         } else if (hcint.b.xacterr && !hcd->core_if->dma_desc_enable) {
+-01897                 if (out_nak_enh) {
+-01898                         if (hcint.b.nyet || hcint.b.nak || hcint.b.ack) {
+-01899                                 DWC_DEBUG("XactErr with NYET/NAK/ACK\n");
+-01900                                 qtd->error_count = 0;
+-01901                         } else {
+-01902                                 DWC_DEBUG("XactErr without NYET/NAK/ACK\n");
+-01903                         }
+-01904                 }
+-01905 
+-01906                 /*
+-01907                  * Must handle xacterr before nak or ack. Could get a xacterr
+-01908                  * at the same time as either of these on a BULK/CONTROL OUT
+-01909                  * that started with a PING. The xacterr takes precedence.
+-01910                  */
+-01911                 handle_hc_xacterr_intr(hcd, hc, hc_regs, qtd);
+-01912         } else if (hcint.b.xcs_xact && hcd->core_if->dma_desc_enable) {
+-01913                 handle_hc_xacterr_intr(hcd, hc, hc_regs, qtd);
+-01914         } else if (hcint.b.ahberr && hcd->core_if->dma_desc_enable) {
+-01915                 handle_hc_ahberr_intr(hcd, hc, hc_regs, qtd);
+-01916         } else if (hcint.b.bblerr) {
+-01917                 handle_hc_babble_intr(hcd, hc, hc_regs, qtd);
+-01918         } else if (hcint.b.frmovrun) {
+-01919                 handle_hc_frmovrun_intr(hcd, hc, hc_regs, qtd);
+-01920         } else if (!out_nak_enh) {
+-01921                 if (hcint.b.nyet) {
+-01922                         /*
+-01923                          * Must handle nyet before nak or ack. Could get a nyet at the
+-01924                          * same time as either of those on a BULK/CONTROL OUT that
+-01925                          * started with a PING. The nyet takes precedence.
+-01926                          */
+-01927                         handle_hc_nyet_intr(hcd, hc, hc_regs, qtd);
+-01928                 } else if (hcint.b.nak && !hcintmsk.b.nak) {
+-01929                         /*
+-01930                          * If nak is not masked, it's because a non-split IN transfer
+-01931                          * is in an error state. In that case, the nak is handled by
+-01932                          * the nak interrupt handler, not here. Handle nak here for
+-01933                          * BULK/CONTROL OUT transfers, which halt on a NAK to allow
+-01934                          * rewinding the buffer pointer.
+-01935                          */
+-01936                         handle_hc_nak_intr(hcd, hc, hc_regs, qtd);
+-01937                 } else if (hcint.b.ack && !hcintmsk.b.ack) {
+-01938                         /*
+-01939                          * If ack is not masked, it's because a non-split IN transfer
+-01940                          * is in an error state. In that case, the ack is handled by
+-01941                          * the ack interrupt handler, not here. Handle ack here for
+-01942                          * split transfers. Start splits halt on ACK.
+-01943                          */
+-01944                         handle_hc_ack_intr(hcd, hc, hc_regs, qtd);
+-01945                 } else {
+-01946                         if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
+-01947                             hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
+-01948                                 /*
+-01949                                  * A periodic transfer halted with no other channel
+-01950                                  * interrupts set. Assume it was halted by the core
+-01951                                  * because it could not be completed in its scheduled
+-01952                                  * (micro)frame.
+-01953                                  */
+-01954 #ifdef DEBUG
+-01955                                 DWC_PRINTF
+-01956                                     ("%s: Halt channel %d (assume incomplete periodic transfer)\n",
+-01957                                      __func__, hc->hc_num);
+-01958 #endif
+-01959                                 halt_channel(hcd, hc, qtd,
+-01960                                              DWC_OTG_HC_XFER_PERIODIC_INCOMPLETE);
+-01961                         } else {
+-01962                                 DWC_ERROR
+-01963                                     ("%s: Channel %d, DMA Mode -- ChHltd set, but reason "
+-01964                                      "for halting is unknown, hcint 0x%08x, intsts 0x%08x\n",
+-01965                                      __func__, hc->hc_num, hcint.d32,
+-01966                                      DWC_READ_REG32(&hcd->
+-01967                                                     core_if->core_global_regs->
+-01968                                                     gintsts));
+-01969                         }
+-01970 
+-01971                 }
+-01972         } else {
+-01973                 DWC_PRINTF("NYET/NAK/ACK/other in non-error case, 0x%08x\n",
+-01974                            hcint.d32);
+-01975         }
+-01976 }
+-01977 
+-01989 static int32_t handle_hc_chhltd_intr(dwc_otg_hcd_t * hcd,
+-01990                                      dwc_hc_t * hc,
+-01991                                      dwc_otg_hc_regs_t * hc_regs,
+-01992                                      dwc_otg_qtd_t * qtd)
+-01993 {
+-01994         DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
+-01995                     "Channel Halted--\n", hc->hc_num);
+-01996 
+-01997         if (hcd->core_if->dma_enable) {
+-01998                 handle_hc_chhltd_intr_dma(hcd, hc, hc_regs, qtd);
+-01999         } else {
+-02000 #ifdef DEBUG
+-02001                 if (!halt_status_ok(hcd, hc, hc_regs, qtd)) {
+-02002                         return 1;
+-02003                 }
+-02004 #endif
+-02005                 release_channel(hcd, hc, qtd, hc->halt_status);
+-02006         }
+-02007 
+-02008         return 1;
+-02009 }
+-02010 
+-02012 int32_t dwc_otg_hcd_handle_hc_n_intr(dwc_otg_hcd_t * dwc_otg_hcd, uint32_t num)
+-02013 {
+-02014         int retval = 0;
+-02015         hcint_data_t hcint;
+-02016         hcintmsk_data_t hcintmsk;
+-02017         dwc_hc_t *hc;
+-02018         dwc_otg_hc_regs_t *hc_regs;
+-02019         dwc_otg_qtd_t *qtd;
+-02020 
+-02021         DWC_DEBUGPL(DBG_HCDV, "--Host Channel Interrupt--, Channel %d\n", num);
+-02022 
+-02023         hc = dwc_otg_hcd->hc_ptr_array[num];
+-02024         hc_regs = dwc_otg_hcd->core_if->host_if->hc_regs[num];
+-02025         qtd = DWC_CIRCLEQ_FIRST(&hc->qh->qtd_list);
+-02026 
+-02027         hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
+-02028         hcintmsk.d32 = DWC_READ_REG32(&hc_regs->hcintmsk);
+-02029         DWC_DEBUGPL(DBG_HCDV,
+-02030                     "  hcint 0x%08x, hcintmsk 0x%08x, hcint&hcintmsk 0x%08x\n",
+-02031                     hcint.d32, hcintmsk.d32, (hcint.d32 & hcintmsk.d32));
+-02032         hcint.d32 = hcint.d32 & hcintmsk.d32;
+-02033 
+-02034         if (!dwc_otg_hcd->core_if->dma_enable) {
+-02035                 if (hcint.b.chhltd && hcint.d32 != 0x2) {
+-02036                         hcint.b.chhltd = 0;
+-02037                 }
+-02038         }
+-02039 
+-02040         if (hcint.b.xfercomp) {
+-02041                 retval |=
+-02042                     handle_hc_xfercomp_intr(dwc_otg_hcd, hc, hc_regs, qtd);
+-02043                 /*
+-02044                  * If NYET occurred at same time as Xfer Complete, the NYET is
+-02045                  * handled by the Xfer Complete interrupt handler. Don't want
+-02046                  * to call the NYET interrupt handler in this case.
+-02047                  */
+-02048                 hcint.b.nyet = 0;
+-02049         }
+-02050         if (hcint.b.chhltd) {
+-02051                 retval |= handle_hc_chhltd_intr(dwc_otg_hcd, hc, hc_regs, qtd);
+-02052         }
+-02053         if (hcint.b.ahberr) {
+-02054                 retval |= handle_hc_ahberr_intr(dwc_otg_hcd, hc, hc_regs, qtd);
+-02055         }
+-02056         if (hcint.b.stall) {
+-02057                 retval |= handle_hc_stall_intr(dwc_otg_hcd, hc, hc_regs, qtd);
+-02058         }
+-02059         if (hcint.b.nak) {
+-02060                 retval |= handle_hc_nak_intr(dwc_otg_hcd, hc, hc_regs, qtd);
+-02061         }
+-02062         if (hcint.b.ack) {
+-02063                 retval |= handle_hc_ack_intr(dwc_otg_hcd, hc, hc_regs, qtd);
+-02064         }
+-02065         if (hcint.b.nyet) {
+-02066                 retval |= handle_hc_nyet_intr(dwc_otg_hcd, hc, hc_regs, qtd);
+-02067         }
+-02068         if (hcint.b.xacterr) {
+-02069                 retval |= handle_hc_xacterr_intr(dwc_otg_hcd, hc, hc_regs, qtd);
+-02070         }
+-02071         if (hcint.b.bblerr) {
+-02072                 retval |= handle_hc_babble_intr(dwc_otg_hcd, hc, hc_regs, qtd);
+-02073         }
+-02074         if (hcint.b.frmovrun) {
+-02075                 retval |=
+-02076                     handle_hc_frmovrun_intr(dwc_otg_hcd, hc, hc_regs, qtd);
+-02077         }
+-02078         if (hcint.b.datatglerr) {
+-02079                 retval |=
+-02080                     handle_hc_datatglerr_intr(dwc_otg_hcd, hc, hc_regs, qtd);
+-02081         }
+-02082 
+-02083         return retval;
+-02084 }
+-02085 
+-02086 #endif /* DWC_DEVICE_ONLY */
+-
                                                                                Generated on Thu Oct 27 03:56:37 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__hcd__intr_8c.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/dwc__otg__hcd__intr_8c.html 2013-07-26 19:34:41.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,1450 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_hcd_intr.c File Reference +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                dwc_otg_hcd_intr.c File Reference

                                                                                This file contains the implementation of the HCD Interrupt handlers. More... +-

                                                                                +-#include "dwc_otg_hcd.h"
                                                                                +-#include "dwc_otg_regs.h"
                                                                                +- +-

                                                                                +-Go to the source code of this file. +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-

                                                                                Functions

                                                                                int32_t dwc_otg_hcd_handle_intr (dwc_otg_hcd_t *dwc_otg_hcd)
                                                                                 This function should be called on every hardware interrupt.
                                                                                int32_t dwc_otg_hcd_handle_sof_intr (dwc_otg_hcd_t *hcd)
                                                                                 Handles the start-of-frame interrupt in host mode.
                                                                                int32_t dwc_otg_hcd_handle_rx_status_q_level_intr (dwc_otg_hcd_t *dwc_otg_hcd)
                                                                                 Handles the Rx Status Queue Level Interrupt, which indicates that there is at least one packet in the Rx FIFO.
                                                                                int32_t dwc_otg_hcd_handle_np_tx_fifo_empty_intr (dwc_otg_hcd_t *dwc_otg_hcd)
                                                                                 This interrupt occurs when the non-periodic Tx FIFO is half-empty.
                                                                                int32_t dwc_otg_hcd_handle_perio_tx_fifo_empty_intr (dwc_otg_hcd_t *dwc_otg_hcd)
                                                                                 This interrupt occurs when the periodic Tx FIFO is half-empty.
                                                                                int32_t dwc_otg_hcd_handle_port_intr (dwc_otg_hcd_t *dwc_otg_hcd)
                                                                                 There are multiple conditions that can cause a port interrupt.
                                                                                int32_t dwc_otg_hcd_handle_hc_intr (dwc_otg_hcd_t *dwc_otg_hcd)
                                                                                 This interrupt indicates that one or more host channels has a pending interrupt.
                                                                                uint32_t get_actual_xfer_length (dwc_hc_t *hc, dwc_otg_hc_regs_t *hc_regs, dwc_otg_qtd_t *qtd, dwc_otg_halt_status_e halt_status, int *short_read)
                                                                                 Gets the actual length of a transfer after the transfer halts.
                                                                                int update_urb_state_xfer_comp (dwc_hc_t *hc, dwc_otg_hc_regs_t *hc_regs, dwc_otg_hcd_urb_t *urb, dwc_otg_qtd_t *qtd)
                                                                                 Updates the state of the URB after a Transfer Complete interrupt on the host channel.
                                                                                +-void dwc_otg_hcd_save_data_toggle (dwc_hc_t *hc, dwc_otg_hc_regs_t *hc_regs, dwc_otg_qtd_t *qtd)
                                                                                dwc_otg_halt_status_e update_isoc_urb_state (dwc_otg_hcd_t *hcd, dwc_hc_t *hc, dwc_otg_hc_regs_t *hc_regs, dwc_otg_qtd_t *qtd, dwc_otg_halt_status_e halt_status)
                                                                                 Updates the state of an Isochronous URB when the transfer is stopped for any reason.
                                                                                void deactivate_qh (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh, int free_qtd)
                                                                                 Frees the first QTD in the QH's list if free_qtd is 1.
                                                                                void release_channel (dwc_otg_hcd_t *hcd, dwc_hc_t *hc, dwc_otg_qtd_t *qtd, dwc_otg_halt_status_e halt_status)
                                                                                 Releases a host channel for use by other transfers.
                                                                                void halt_channel (dwc_otg_hcd_t *hcd, dwc_hc_t *hc, dwc_otg_qtd_t *qtd, dwc_otg_halt_status_e halt_status)
                                                                                 Halts a host channel.
                                                                                void complete_non_periodic_xfer (dwc_otg_hcd_t *hcd, dwc_hc_t *hc, dwc_otg_hc_regs_t *hc_regs, dwc_otg_qtd_t *qtd, dwc_otg_halt_status_e halt_status)
                                                                                 Performs common cleanup for non-periodic transfers after a Transfer Complete interrupt.
                                                                                void complete_periodic_xfer (dwc_otg_hcd_t *hcd, dwc_hc_t *hc, dwc_otg_hc_regs_t *hc_regs, dwc_otg_qtd_t *qtd, dwc_otg_halt_status_e halt_status)
                                                                                 Performs common cleanup for periodic transfers after a Transfer Complete interrupt.
                                                                                +-int32_t handle_xfercomp_isoc_split_in (dwc_otg_hcd_t *hcd, dwc_hc_t *hc, dwc_otg_hc_regs_t *hc_regs, dwc_otg_qtd_t *qtd)
                                                                                int32_t handle_hc_xfercomp_intr (dwc_otg_hcd_t *hcd, dwc_hc_t *hc, dwc_otg_hc_regs_t *hc_regs, dwc_otg_qtd_t *qtd)
                                                                                 Handles a host channel Transfer Complete interrupt.
                                                                                int32_t handle_hc_stall_intr (dwc_otg_hcd_t *hcd, dwc_hc_t *hc, dwc_otg_hc_regs_t *hc_regs, dwc_otg_qtd_t *qtd)
                                                                                 Handles a host channel STALL interrupt.
                                                                                +-void update_urb_state_xfer_intr (dwc_hc_t *hc, dwc_otg_hc_regs_t *hc_regs, dwc_otg_hcd_urb_t *urb, dwc_otg_qtd_t *qtd, dwc_otg_halt_status_e halt_status)
                                                                                int32_t handle_hc_nak_intr (dwc_otg_hcd_t *hcd, dwc_hc_t *hc, dwc_otg_hc_regs_t *hc_regs, dwc_otg_qtd_t *qtd)
                                                                                 Handles a host channel NAK interrupt.
                                                                                int32_t handle_hc_ack_intr (dwc_otg_hcd_t *hcd, dwc_hc_t *hc, dwc_otg_hc_regs_t *hc_regs, dwc_otg_qtd_t *qtd)
                                                                                 Handles a host channel ACK interrupt.
                                                                                int32_t handle_hc_nyet_intr (dwc_otg_hcd_t *hcd, dwc_hc_t *hc, dwc_otg_hc_regs_t *hc_regs, dwc_otg_qtd_t *qtd)
                                                                                 Handles a host channel NYET interrupt.
                                                                                int32_t handle_hc_babble_intr (dwc_otg_hcd_t *hcd, dwc_hc_t *hc, dwc_otg_hc_regs_t *hc_regs, dwc_otg_qtd_t *qtd)
                                                                                 Handles a host channel babble interrupt.
                                                                                int32_t handle_hc_ahberr_intr (dwc_otg_hcd_t *hcd, dwc_hc_t *hc, dwc_otg_hc_regs_t *hc_regs, dwc_otg_qtd_t *qtd)
                                                                                 Handles a host channel AHB error interrupt.
                                                                                int32_t handle_hc_xacterr_intr (dwc_otg_hcd_t *hcd, dwc_hc_t *hc, dwc_otg_hc_regs_t *hc_regs, dwc_otg_qtd_t *qtd)
                                                                                 Handles a host channel transaction error interrupt.
                                                                                int32_t handle_hc_frmovrun_intr (dwc_otg_hcd_t *hcd, dwc_hc_t *hc, dwc_otg_hc_regs_t *hc_regs, dwc_otg_qtd_t *qtd)
                                                                                 Handles a host channel frame overrun interrupt.
                                                                                int32_t handle_hc_datatglerr_intr (dwc_otg_hcd_t *hcd, dwc_hc_t *hc, dwc_otg_hc_regs_t *hc_regs, dwc_otg_qtd_t *qtd)
                                                                                 Handles a host channel data toggle error interrupt.
                                                                                void handle_hc_chhltd_intr_dma (dwc_otg_hcd_t *hcd, dwc_hc_t *hc, dwc_otg_hc_regs_t *hc_regs, dwc_otg_qtd_t *qtd)
                                                                                 Handles a host Channel Halted interrupt in DMA mode.
                                                                                int32_t handle_hc_chhltd_intr (dwc_otg_hcd_t *hcd, dwc_hc_t *hc, dwc_otg_hc_regs_t *hc_regs, dwc_otg_qtd_t *qtd)
                                                                                 Handles a host channel Channel Halted interrupt.
                                                                                +-int32_t dwc_otg_hcd_handle_hc_n_intr (dwc_otg_hcd_t *dwc_otg_hcd, uint32_t num)
                                                                                 Handles interrupt for a specific Host Channel.
                                                                                +-

                                                                                Detailed Description

                                                                                +-This file contains the implementation of the HCD Interrupt handlers. +-

                                                                                +- +-

                                                                                +-Definition in file dwc_otg_hcd_intr.c.

                                                                                Function Documentation

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                int32_t dwc_otg_hcd_handle_intr ( dwc_otg_hcd_t *  dwc_otg_hcd  ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This function should be called on every hardware interrupt. +-

                                                                                +-

                                                                                Todo:
                                                                                Implement i2cintr handler.
                                                                                +- +-

                                                                                +-Definition at line 43 of file dwc_otg_hcd_intr.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                int32_t dwc_otg_hcd_handle_sof_intr ( dwc_otg_hcd_t *  hcd  ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Handles the start-of-frame interrupt in host mode. +-

                                                                                +-Non-periodic transactions may be queued to the DWC_otg controller for the current (micro)frame. Periodic transactions may be queued to the controller for the next (micro)frame. +-

                                                                                +-Definition at line 175 of file dwc_otg_hcd_intr.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                int32_t dwc_otg_hcd_handle_rx_status_q_level_intr ( dwc_otg_hcd_t *  dwc_otg_hcd  ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Handles the Rx Status Queue Level Interrupt, which indicates that there is at least one packet in the Rx FIFO. +-

                                                                                +-The packets are moved from the FIFO to memory if the DWC_otg controller is operating in Slave mode. +-

                                                                                +-Definition at line 228 of file dwc_otg_hcd_intr.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                int32_t dwc_otg_hcd_handle_np_tx_fifo_empty_intr ( dwc_otg_hcd_t *  dwc_otg_hcd  ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This interrupt occurs when the non-periodic Tx FIFO is half-empty. +-

                                                                                +-More data packets may be written to the FIFO for OUT transfers. More requests may be written to the non-periodic request queue for IN transfers. This interrupt is enabled only in Slave mode. +-

                                                                                +-Definition at line 281 of file dwc_otg_hcd_intr.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                int32_t dwc_otg_hcd_handle_perio_tx_fifo_empty_intr ( dwc_otg_hcd_t *  dwc_otg_hcd  ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This interrupt occurs when the periodic Tx FIFO is half-empty. +-

                                                                                +-More data packets may be written to the FIFO for OUT transfers. More requests may be written to the periodic request queue for IN transfers. This interrupt is enabled only in Slave mode. +-

                                                                                +-Definition at line 293 of file dwc_otg_hcd_intr.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                int32_t dwc_otg_hcd_handle_port_intr ( dwc_otg_hcd_t *  dwc_otg_hcd  ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-There are multiple conditions that can cause a port interrupt. +-

                                                                                +-This function determines which interrupt conditions have occurred and handles them appropriately.

                                                                                +-

                                                                                Todo:
                                                                                  +-
                                                                                • check if steps performed in 'else' block should be perfromed regardles adp
                                                                                +-
                                                                                +-

                                                                                +-Overcurrent Change Interrupt +-

                                                                                +-Definition at line 304 of file dwc_otg_hcd_intr.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                int32_t dwc_otg_hcd_handle_hc_intr ( dwc_otg_hcd_t *  dwc_otg_hcd  ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This interrupt indicates that one or more host channels has a pending interrupt. +-

                                                                                +-There are multiple conditions that can cause each host channel interrupt. This function determines which conditions have occurred for each host channel interrupt and handles them appropriately. +-

                                                                                +-Definition at line 493 of file dwc_otg_hcd_intr.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                uint32_t get_actual_xfer_length ( dwc_hc_t *  hc,
                                                                                dwc_otg_hc_regs_t *  hc_regs,
                                                                                dwc_otg_qtd_t *  qtd,
                                                                                dwc_otg_halt_status_e  halt_status,
                                                                                int *  short_read
                                                                                )  [static]
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Gets the actual length of a transfer after the transfer halts. +-

                                                                                +-_halt_status holds the reason for the halt.

                                                                                +-For IN transfers where halt_status is DWC_OTG_HC_XFER_COMPLETE, *short_read is set to 1 upon return if less than the requested number of bytes were transferred. Otherwise, *short_read is set to 0 upon return. short_read may also be NULL on entry, in which case it remains unchanged. +-

                                                                                +-Definition at line 523 of file dwc_otg_hcd_intr.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                int update_urb_state_xfer_comp ( dwc_hc_t *  hc,
                                                                                dwc_otg_hc_regs_t *  hc_regs,
                                                                                dwc_otg_hcd_urb_t *  urb,
                                                                                dwc_otg_qtd_t *  qtd
                                                                                )  [static]
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Updates the state of the URB after a Transfer Complete interrupt on the host channel. +-

                                                                                +-Updates the actual_length field of the URB based on the number of bytes transferred via the host channel. Sets the URB status if the data transfer is finished.

                                                                                +-

                                                                                Returns:
                                                                                1 if the data transfer specified by the URB is completely finished, 0 otherwise.
                                                                                +- +-

                                                                                +-Definition at line 574 of file dwc_otg_hcd_intr.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                dwc_otg_halt_status_e update_isoc_urb_state ( dwc_otg_hcd_t *  hcd,
                                                                                dwc_hc_t *  hc,
                                                                                dwc_otg_hc_regs_t *  hc_regs,
                                                                                dwc_otg_qtd_t *  qtd,
                                                                                dwc_otg_halt_status_e  halt_status
                                                                                )  [static]
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Updates the state of an Isochronous URB when the transfer is stopped for any reason. +-

                                                                                +-The fields of the current entry in the frame descriptor array are set based on the transfer state and the input _halt_status. Completes the Isochronous URB if all the URB frames have been completed.

                                                                                +-

                                                                                Returns:
                                                                                DWC_OTG_HC_XFER_COMPLETE if there are more frames remaining to be transferred in the URB. Otherwise return DWC_OTG_HC_XFER_URB_COMPLETE.
                                                                                +- +-

                                                                                +-Definition at line 666 of file dwc_otg_hcd_intr.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                void deactivate_qh ( dwc_otg_hcd_t *  hcd,
                                                                                dwc_otg_qh_t *  qh,
                                                                                int  free_qtd
                                                                                )  [static]
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Frees the first QTD in the QH's list if free_qtd is 1. +-

                                                                                +-For non-periodic QHs, removes the QH from the active non-periodic schedule. If any QTDs are still linked to the QH, the QH is added to the end of the inactive non-periodic schedule. For periodic QHs, removes the QH from the periodic schedule if no more QTDs are linked to the QH. +-

                                                                                +-Definition at line 746 of file dwc_otg_hcd_intr.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                void release_channel ( dwc_otg_hcd_t *  hcd,
                                                                                dwc_hc_t *  hc,
                                                                                dwc_otg_qtd_t *  qtd,
                                                                                dwc_otg_halt_status_e  halt_status
                                                                                )  [static]
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Releases a host channel for use by other transfers. +-

                                                                                +-Attempts to select and queue more transactions since at least one host channel is available.

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +- +- +-
                                                                                hcd The HCD state structure.
                                                                                hc The host channel to release.
                                                                                qtd The QTD associated with the host channel. This QTD may be freed if the transfer is complete or an error has occurred.
                                                                                halt_status Reason the channel is being released. This status determines the actions taken by this function.
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 782 of file dwc_otg_hcd_intr.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                void halt_channel ( dwc_otg_hcd_t *  hcd,
                                                                                dwc_hc_t *  hc,
                                                                                dwc_otg_qtd_t *  qtd,
                                                                                dwc_otg_halt_status_e  halt_status
                                                                                )  [static]
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Halts a host channel. +-

                                                                                +-If the channel cannot be halted immediately because the request queue is full, this function ensures that the FIFO empty interrupt for the appropriate queue is enabled so that the halt request can be queued when there is space in the request queue.

                                                                                +-This function may also be called in DMA mode. In that case, the channel is simply released since the core always halts the channel automatically in DMA mode. +-

                                                                                +-Definition at line 880 of file dwc_otg_hcd_intr.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                void complete_non_periodic_xfer ( dwc_otg_hcd_t *  hcd,
                                                                                dwc_hc_t *  hc,
                                                                                dwc_otg_hc_regs_t *  hc_regs,
                                                                                dwc_otg_qtd_t *  qtd,
                                                                                dwc_otg_halt_status_e  halt_status
                                                                                )  [static]
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Performs common cleanup for non-periodic transfers after a Transfer Complete interrupt. +-

                                                                                +-This function should be called after any endpoint type specific handling is finished to release the host channel. +-

                                                                                +-Definition at line 932 of file dwc_otg_hcd_intr.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                void complete_periodic_xfer ( dwc_otg_hcd_t *  hcd,
                                                                                dwc_hc_t *  hc,
                                                                                dwc_otg_hc_regs_t *  hc_regs,
                                                                                dwc_otg_qtd_t *  qtd,
                                                                                dwc_otg_halt_status_e  halt_status
                                                                                )  [static]
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Performs common cleanup for periodic transfers after a Transfer Complete interrupt. +-

                                                                                +-This function should be called after any endpoint type specific handling is finished to release the host channel. +-

                                                                                +-Definition at line 984 of file dwc_otg_hcd_intr.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                int32_t handle_hc_xfercomp_intr ( dwc_otg_hcd_t *  hcd,
                                                                                dwc_hc_t *  hc,
                                                                                dwc_otg_hc_regs_t *  hc_regs,
                                                                                dwc_otg_qtd_t *  qtd
                                                                                )  [static]
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Handles a host channel Transfer Complete interrupt. +-

                                                                                +-This handler may be called in either DMA mode or Slave mode. +-

                                                                                +-Definition at line 1048 of file dwc_otg_hcd_intr.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                int32_t handle_hc_stall_intr ( dwc_otg_hcd_t *  hcd,
                                                                                dwc_hc_t *  hc,
                                                                                dwc_otg_hc_regs_t *  hc_regs,
                                                                                dwc_otg_qtd_t *  qtd
                                                                                )  [static]
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Handles a host channel STALL interrupt. +-

                                                                                +-This handler may be called in either DMA mode or Slave mode. +-

                                                                                +-Definition at line 1182 of file dwc_otg_hcd_intr.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                int32_t handle_hc_nak_intr ( dwc_otg_hcd_t *  hcd,
                                                                                dwc_hc_t *  hc,
                                                                                dwc_otg_hc_regs_t *  hc_regs,
                                                                                dwc_otg_qtd_t *  qtd
                                                                                )  [static]
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Handles a host channel NAK interrupt. +-

                                                                                +-This handler may be called in either DMA mode or Slave mode. +-

                                                                                +-Definition at line 1269 of file dwc_otg_hcd_intr.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                int32_t handle_hc_ack_intr ( dwc_otg_hcd_t *  hcd,
                                                                                dwc_hc_t *  hc,
                                                                                dwc_otg_hc_regs_t *  hc_regs,
                                                                                dwc_otg_qtd_t *  qtd
                                                                                )  [static]
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Handles a host channel ACK interrupt. +-

                                                                                +-This interrupt is enabled when performing the PING protocol in Slave mode, when errors occur during either Slave mode or DMA mode, and during Start Split transactions. +-

                                                                                +-Definition at line 1349 of file dwc_otg_hcd_intr.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                int32_t handle_hc_nyet_intr ( dwc_otg_hcd_t *  hcd,
                                                                                dwc_hc_t *  hc,
                                                                                dwc_otg_hc_regs_t *  hc_regs,
                                                                                dwc_otg_qtd_t *  qtd
                                                                                )  [static]
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Handles a host channel NYET interrupt. +-

                                                                                +-This interrupt should only occur on Bulk and Control OUT endpoints and for complete split transactions. If a NYET occurs at the same time as a Transfer Complete interrupt, it is handled in the xfercomp interrupt handler, not here. This handler may be called in either DMA mode or Slave mode.

                                                                                +-

                                                                                Todo:
                                                                                add support for isoc release
                                                                                +- +-

                                                                                +-Definition at line 1443 of file dwc_otg_hcd_intr.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                int32_t handle_hc_babble_intr ( dwc_otg_hcd_t *  hcd,
                                                                                dwc_hc_t *  hc,
                                                                                dwc_otg_hc_regs_t *  hc_regs,
                                                                                dwc_otg_qtd_t *  qtd
                                                                                )  [static]
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Handles a host channel babble interrupt. +-

                                                                                +-This handler may be called in either DMA mode or Slave mode. +-

                                                                                +-Definition at line 1522 of file dwc_otg_hcd_intr.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                int32_t handle_hc_ahberr_intr ( dwc_otg_hcd_t *  hcd,
                                                                                dwc_hc_t *  hc,
                                                                                dwc_otg_hc_regs_t *  hc_regs,
                                                                                dwc_otg_qtd_t *  qtd
                                                                                )  [static]
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Handles a host channel AHB error interrupt. +-

                                                                                +-This handler is only called in DMA mode. +-

                                                                                +-Definition at line 1556 of file dwc_otg_hcd_intr.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                int32_t handle_hc_xacterr_intr ( dwc_otg_hcd_t *  hcd,
                                                                                dwc_hc_t *  hc,
                                                                                dwc_otg_hc_regs_t *  hc_regs,
                                                                                dwc_otg_qtd_t *  qtd
                                                                                )  [static]
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Handles a host channel transaction error interrupt. +-

                                                                                +-This handler may be called in either DMA mode or Slave mode. +-

                                                                                +-Definition at line 1656 of file dwc_otg_hcd_intr.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                int32_t handle_hc_frmovrun_intr ( dwc_otg_hcd_t *  hcd,
                                                                                dwc_hc_t *  hc,
                                                                                dwc_otg_hc_regs_t *  hc_regs,
                                                                                dwc_otg_qtd_t *  qtd
                                                                                )  [static]
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Handles a host channel frame overrun interrupt. +-

                                                                                +-This handler may be called in either DMA mode or Slave mode. +-

                                                                                +-Definition at line 1719 of file dwc_otg_hcd_intr.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                int32_t handle_hc_datatglerr_intr ( dwc_otg_hcd_t *  hcd,
                                                                                dwc_hc_t *  hc,
                                                                                dwc_otg_hc_regs_t *  hc_regs,
                                                                                dwc_otg_qtd_t *  qtd
                                                                                )  [static]
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Handles a host channel data toggle error interrupt. +-

                                                                                +-This handler may be called in either DMA mode or Slave mode. +-

                                                                                +-Definition at line 1755 of file dwc_otg_hcd_intr.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                void handle_hc_chhltd_intr_dma ( dwc_otg_hcd_t *  hcd,
                                                                                dwc_hc_t *  hc,
                                                                                dwc_otg_hc_regs_t *  hc_regs,
                                                                                dwc_otg_qtd_t *  qtd
                                                                                )  [static]
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Handles a host Channel Halted interrupt in DMA mode. +-

                                                                                +-This handler determines the reason the channel halted and proceeds accordingly.

                                                                                +-

                                                                                Todo:
                                                                                This is here because of a possible hardware bug. Spec says that on SPLIT-ISOC OUT transfers in DMA mode that a HALT interrupt w/ACK bit set should occur, but I only see the XFERCOMP bit, even with it masked out. This is a workaround for that behavior. Should fix this when hardware is fixed.
                                                                                +- +-

                                                                                +-Definition at line 1842 of file dwc_otg_hcd_intr.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                int32_t handle_hc_chhltd_intr ( dwc_otg_hcd_t *  hcd,
                                                                                dwc_hc_t *  hc,
                                                                                dwc_otg_hc_regs_t *  hc_regs,
                                                                                dwc_otg_qtd_t *  qtd
                                                                                )  [static]
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Handles a host channel Channel Halted interrupt. +-

                                                                                +-In slave mode, this handler is called only when the driver specifically requests a halt. This occurs during handling other host channel interrupts (e.g. nak, xacterr, stall, nyet, etc.).

                                                                                +-In DMA mode, this is the interrupt that occurs when the core has finished processing a transfer on a channel. Other host channel interrupts (except ahberr) are disabled in DMA mode. +-

                                                                                +-Definition at line 1989 of file dwc_otg_hcd_intr.c.

                                                                                +-

                                                                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__hcd__linux_8c-source.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/dwc__otg__hcd__linux_8c-source.html 2013-07-26 19:34:41.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,791 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_hcd_linux.c Source File +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                dwc_otg_hcd_linux.c

                                                                                Go to the documentation of this file.
                                                                                00001 /* ==========================================================================
+-00002  * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd_linux.c $
+-00003  * $Revision: #20 $
+-00004  * $Date: 2011/10/26 $
+-00005  * $Change: 1872981 $
+-00006  *
+-00007  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
+-00008  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
+-00009  * otherwise expressly agreed to in writing between Synopsys and you.
+-00010  *
+-00011  * The Software IS NOT an item of Licensed Software or Licensed Product under
+-00012  * any End User Software License Agreement or Agreement for Licensed Product
+-00013  * with Synopsys or any supplement thereto. You are permitted to use and
+-00014  * redistribute this Software in source and binary forms, with or without
+-00015  * modification, provided that redistributions of source code must retain this
+-00016  * notice. You may not view, use, disclose, copy or distribute this file or
+-00017  * any information contained herein except pursuant to this license grant from
+-00018  * Synopsys. If you do not agree with this notice, including the disclaimer
+-00019  * below, then you are not authorized to use the Software.
+-00020  *
+-00021  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
+-00022  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+-00023  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+-00024  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
+-00025  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+-00026  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+-00027  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+-00028  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+-00029  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+-00030  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+-00031  * DAMAGE.
+-00032  * ========================================================================== */
+-00033 #ifndef DWC_DEVICE_ONLY
+-00034 
+-00041 #include <linux/kernel.h>
+-00042 #include <linux/module.h>
+-00043 #include <linux/moduleparam.h>
+-00044 #include <linux/init.h>
+-00045 #include <linux/device.h>
+-00046 #include <linux/errno.h>
+-00047 #include <linux/list.h>
+-00048 #include <linux/interrupt.h>
+-00049 #include <linux/string.h>
+-00050 #include <linux/dma-mapping.h>
+-00051 #include <linux/version.h>
+-00052 #include <asm/io.h>
+-00053 #include <linux/usb.h>
+-00054 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,35)
+-00055 #include <../drivers/usb/core/hcd.h>
+-00056 #else
+-00057 #include <linux/usb/hcd.h>
+-00058 #endif
+-00059 
+-00060 #include "dwc_otg_hcd_if.h"
+-00061 #include "dwc_otg_dbg.h"
+-00062 #include "dwc_otg_driver.h"
+-00063 #include "dwc_otg_hcd.h"
+-00068 #define dwc_ep_addr_to_endpoint(_bEndpointAddress_) ((_bEndpointAddress_ & USB_ENDPOINT_NUMBER_MASK) | \
+-00069                                                      ((_bEndpointAddress_ & USB_DIR_IN) != 0) << 4)
+-00070 
+-00071 static const char dwc_otg_hcd_name[] = "dwc_otg_hcd";
+-00072 
+-00075 static int urb_enqueue(struct usb_hcd *hcd,
+-00076 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28)
+-00077                        struct usb_host_endpoint *ep,
+-00078 #endif
+-00079                        struct urb *urb, gfp_t mem_flags);
+-00080 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28)
+-00081 static int urb_dequeue(struct usb_hcd *hcd, struct urb *urb);
+-00082 #else
+-00083 static int urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status);
+-00084 #endif
+-00085 
+-00086 static void endpoint_disable(struct usb_hcd *hcd, struct usb_host_endpoint *ep);
+-00087 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,30)
+-00088 static void endpoint_reset(struct usb_hcd *hcd, struct usb_host_endpoint *ep);
+-00089 #endif
+-00090 static irqreturn_t dwc_otg_hcd_irq(struct usb_hcd *hcd);
+-00091 extern int hcd_start(struct usb_hcd *hcd);
+-00092 extern void hcd_stop(struct usb_hcd *hcd);
+-00093 static int get_frame_number(struct usb_hcd *hcd);
+-00094 extern int hub_status_data(struct usb_hcd *hcd, char *buf);
+-00095 extern int hub_control(struct usb_hcd *hcd,
+-00096                        u16 typeReq,
+-00097                        u16 wValue, u16 wIndex, char *buf, u16 wLength);
+-00098 
+-00099 struct wrapper_priv_data {
+-00100         dwc_otg_hcd_t *dwc_otg_hcd;
+-00101 };
+-00102 
+-00105 static struct hc_driver dwc_otg_hc_driver = {
+-00106 
+-00107         .description = dwc_otg_hcd_name,
+-00108         .product_desc = "DWC OTG Controller",
+-00109         .hcd_priv_size = sizeof(struct wrapper_priv_data),
+-00110 
+-00111         .irq = dwc_otg_hcd_irq,
+-00112 
+-00113         .flags = HCD_MEMORY | HCD_USB2,
+-00114 
+-00115         //.reset =              
+-00116         .start = hcd_start,
+-00117         //.suspend =            
+-00118         //.resume =             
+-00119         .stop = hcd_stop,
+-00120 
+-00121         .urb_enqueue = urb_enqueue,
+-00122         .urb_dequeue = urb_dequeue,
+-00123         .endpoint_disable = endpoint_disable,
+-00124 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,30)
+-00125         .endpoint_reset = endpoint_reset,
+-00126 #endif
+-00127         .get_frame_number = get_frame_number,
+-00128 
+-00129         .hub_status_data = hub_status_data,
+-00130         .hub_control = hub_control,
+-00131         //.bus_suspend =                
+-00132         //.bus_resume =         
+-00133 };
+-00134 
+-00136 static inline dwc_otg_hcd_t *hcd_to_dwc_otg_hcd(struct usb_hcd *hcd)
+-00137 {
+-00138         struct wrapper_priv_data *p;
+-00139         p = (struct wrapper_priv_data *)(hcd->hcd_priv);
+-00140         return p->dwc_otg_hcd;
+-00141 }
+-00142 
+-00144 static inline struct usb_hcd *dwc_otg_hcd_to_hcd(dwc_otg_hcd_t * dwc_otg_hcd)
+-00145 {
+-00146         return dwc_otg_hcd_get_priv_data(dwc_otg_hcd);
+-00147 }
+-00148 
+-00150 inline struct usb_host_endpoint *dwc_urb_to_endpoint(struct urb *urb)
+-00151 {
+-00152         struct usb_device *dev = urb->dev;
+-00153         int ep_num = usb_pipeendpoint(urb->pipe);
+-00154 
+-00155         if (usb_pipein(urb->pipe))
+-00156                 return dev->ep_in[ep_num];
+-00157         else
+-00158                 return dev->ep_out[ep_num];
+-00159 }
+-00160 
+-00161 static int _disconnect(dwc_otg_hcd_t * hcd)
+-00162 {
+-00163         struct usb_hcd *usb_hcd = dwc_otg_hcd_to_hcd(hcd);
+-00164 
+-00165         usb_hcd->self.is_b_host = 0;
+-00166         return 0;
+-00167 }
+-00168 
+-00169 static int _start(dwc_otg_hcd_t * hcd)
+-00170 {
+-00171         struct usb_hcd *usb_hcd = dwc_otg_hcd_to_hcd(hcd);
+-00172 
+-00173         usb_hcd->self.is_b_host = dwc_otg_hcd_is_b_host(hcd);
+-00174         hcd_start(usb_hcd);
+-00175 
+-00176         return 0;
+-00177 }
+-00178 
+-00179 static int _hub_info(dwc_otg_hcd_t * hcd, void *urb_handle, uint32_t * hub_addr,
+-00180                      uint32_t * port_addr)
+-00181 {
+-00182         struct urb *urb = (struct urb *)urb_handle;
+-00183         if (urb->dev->tt) {
+-00184                 *hub_addr = urb->dev->tt->hub->devnum;
+-00185         } else {
+-00186                 *hub_addr = 0;
+-00187         }
+-00188         *port_addr = urb->dev->ttport;
+-00189         return 0;
+-00190 }
+-00191 
+-00192 static int _speed(dwc_otg_hcd_t * hcd, void *urb_handle)
+-00193 {
+-00194         struct urb *urb = (struct urb *)urb_handle;
+-00195         return urb->dev->speed;
+-00196 }
+-00197 
+-00198 static int _get_b_hnp_enable(dwc_otg_hcd_t * hcd)
+-00199 {
+-00200         struct usb_hcd *usb_hcd = dwc_otg_hcd_to_hcd(hcd);
+-00201         return usb_hcd->self.b_hnp_enable;
+-00202 }
+-00203 
+-00204 static void allocate_bus_bandwidth(struct usb_hcd *hcd, uint32_t bw,
+-00205                                    struct urb *urb)
+-00206 {
+-00207         hcd_to_bus(hcd)->bandwidth_allocated += bw / urb->interval;
+-00208         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
+-00209                 hcd_to_bus(hcd)->bandwidth_isoc_reqs++;
+-00210         } else {
+-00211                 hcd_to_bus(hcd)->bandwidth_int_reqs++;
+-00212         }
+-00213 }
+-00214 
+-00215 static void free_bus_bandwidth(struct usb_hcd *hcd, uint32_t bw,
+-00216                                struct urb *urb)
+-00217 {
+-00218         hcd_to_bus(hcd)->bandwidth_allocated -= bw / urb->interval;
+-00219         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
+-00220                 hcd_to_bus(hcd)->bandwidth_isoc_reqs--;
+-00221         } else {
+-00222                 hcd_to_bus(hcd)->bandwidth_int_reqs--;
+-00223         }
+-00224 }
+-00225 
+-00230 static int _complete(dwc_otg_hcd_t * hcd, void *urb_handle,
+-00231                      dwc_otg_hcd_urb_t * dwc_otg_urb, int32_t status)
+-00232 {
+-00233         struct urb *urb = (struct urb *)urb_handle;
+-00234 #ifdef DEBUG
+-00235         if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
+-00236                 DWC_PRINTF("%s: urb %p, device %d, ep %d %s, status=%d\n",
+-00237                            __func__, urb, usb_pipedevice(urb->pipe),
+-00238                            usb_pipeendpoint(urb->pipe),
+-00239                            usb_pipein(urb->pipe) ? "IN" : "OUT", status);
+-00240                 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
+-00241                         int i;
+-00242                         for (i = 0; i < urb->number_of_packets; i++) {
+-00243                                 DWC_PRINTF("  ISO Desc %d status: %d\n",
+-00244                                            i, urb->iso_frame_desc[i].status);
+-00245                         }
+-00246                 }
+-00247         }
+-00248 #endif
+-00249 
+-00250         urb->actual_length = dwc_otg_hcd_urb_get_actual_length(dwc_otg_urb);
+-00251         /* Convert status value. */
+-00252         switch (status) {
+-00253         case -DWC_E_PROTOCOL:
+-00254                 status = -EPROTO;
+-00255                 break;
+-00256         case -DWC_E_IN_PROGRESS:
+-00257                 status = -EINPROGRESS;
+-00258                 break;
+-00259         case -DWC_E_PIPE:
+-00260                 status = -EPIPE;
+-00261                 break;
+-00262         case -DWC_E_IO:
+-00263                 status = -EIO;
+-00264                 break;
+-00265         case -DWC_E_TIMEOUT:
+-00266                 status = -ETIMEDOUT;
+-00267                 break;
+-00268         case -DWC_E_OVERFLOW:
+-00269                 status = -EOVERFLOW;
+-00270                 break;
+-00271         default:
+-00272                 if (status) {
+-00273                         DWC_PRINTF("Uknown urb status %d\n", status);
+-00274 
+-00275                 }
+-00276         }
+-00277 
+-00278         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
+-00279                 int i;
+-00280 
+-00281                 urb->error_count = dwc_otg_hcd_urb_get_error_count(dwc_otg_urb);
+-00282                 for (i = 0; i < urb->number_of_packets; ++i) {
+-00283                         urb->iso_frame_desc[i].actual_length =
+-00284                             dwc_otg_hcd_urb_get_iso_desc_actual_length
+-00285                             (dwc_otg_urb, i);
+-00286                         urb->iso_frame_desc[i].status =
+-00287                             dwc_otg_hcd_urb_get_iso_desc_status(dwc_otg_urb, i);
+-00288                 }
+-00289         }
+-00290 
+-00291         urb->status = status;
+-00292         urb->hcpriv = NULL;
+-00293         if (!status) {
+-00294                 if ((urb->transfer_flags & URB_SHORT_NOT_OK) &&
+-00295                     (urb->actual_length < urb->transfer_buffer_length)) {
+-00296                         urb->status = -EREMOTEIO;
+-00297                 }
+-00298         }
+-00299 
+-00300         if ((usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) ||
+-00301             (usb_pipetype(urb->pipe) == PIPE_INTERRUPT)) {
+-00302                 struct usb_host_endpoint *ep = dwc_urb_to_endpoint(urb);
+-00303                 if (ep) {
+-00304                         free_bus_bandwidth(dwc_otg_hcd_to_hcd(hcd),
+-00305                                            dwc_otg_hcd_get_ep_bandwidth(hcd,
+-00306                                                                         ep->hcpriv),
+-00307                                            urb);
+-00308                 }
+-00309         }
+-00310 
+-00311         DWC_FREE(dwc_otg_urb);
+-00312 
+-00313         DWC_SPINUNLOCK(hcd->lock);
+-00314 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28)
+-00315         usb_hcd_giveback_urb(dwc_otg_hcd_to_hcd(hcd), urb);
+-00316 #else
+-00317         usb_hcd_giveback_urb(dwc_otg_hcd_to_hcd(hcd), urb, status);
+-00318 #endif
+-00319         DWC_SPINLOCK(hcd->lock);
+-00320 
+-00321         return 0;
+-00322 }
+-00323 
+-00324 static struct dwc_otg_hcd_function_ops hcd_fops = {
+-00325         .start = _start,
+-00326         .disconnect = _disconnect,
+-00327         .hub_info = _hub_info,
+-00328         .speed = _speed,
+-00329         .complete = _complete,
+-00330         .get_b_hnp_enable = _get_b_hnp_enable,
+-00331 };
+-00332 
+-00339 int hcd_init(
+-00340 #ifdef LM_INTERFACE
+-00341                     struct lm_device *_dev
+-00342 #elif  defined(PCI_INTERFACE)
+-00343                     struct pci_dev *_dev
+-00344 #endif
+-00345     )
+-00346 {
+-00347         struct usb_hcd *hcd = NULL;
+-00348         dwc_otg_hcd_t *dwc_otg_hcd = NULL;
+-00349 #ifdef LM_INTERFACE
+-00350         dwc_otg_device_t *otg_dev = lm_get_drvdata(_dev);
+-00351 #elif  defined(PCI_INTERFACE)
+-00352         dwc_otg_device_t *otg_dev = pci_get_drvdata(_dev);
+-00353 #endif
+-00354 
+-00355         int retval = 0;
+-00356 
+-00357         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD INIT\n");
+-00358 
+-00359         /* Set device flags indicating whether the HCD supports DMA. */
+-00360         if (dwc_otg_is_dma_enable(otg_dev->core_if)) {
+-00361 #ifdef LM_INTERFACE
+-00362                 _dev->dev.dma_mask = (void *)~0;
+-00363                 _dev->dev.coherent_dma_mask = ~0;
+-00364 #elif  defined(PCI_INTERFACE)
+-00365                 pci_set_dma_mask(_dev, DMA_32BIT_MASK);
+-00366                 pci_set_consistent_dma_mask(_dev, DMA_32BIT_MASK);
+-00367 #endif
+-00368 
+-00369         } else {
+-00370 #ifdef LM_INTERFACE
+-00371                 _dev->dev.dma_mask = (void *)0;
+-00372                 _dev->dev.coherent_dma_mask = 0;
+-00373 #elif  defined(PCI_INTERFACE)
+-00374                 pci_set_dma_mask(_dev, 0);
+-00375                 pci_set_consistent_dma_mask(_dev, 0);
+-00376 #endif
+-00377         }
+-00378 
+-00379         /*
+-00380          * Allocate memory for the base HCD plus the DWC OTG HCD.
+-00381          * Initialize the base HCD.
+-00382          */
+-00383 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30)
+-00384         hcd = usb_create_hcd(&dwc_otg_hc_driver, &_dev->dev, _dev->dev.bus_id);
+-00385 #else
+-00386         hcd = usb_create_hcd(&dwc_otg_hc_driver, &_dev->dev, dev_name(&_dev->dev));
+-00387         hcd->has_tt = 1;
+-00388 //      hcd->uses_new_polling = 1;
+-00389 //      hcd->poll_rh = 0;
+-00390 #endif
+-00391         if (!hcd) {
+-00392                 retval = -ENOMEM;
+-00393                 goto error1;
+-00394         }
+-00395 
+-00396         hcd->regs = otg_dev->os_dep.base;
+-00397 
+-00398         /* Initialize the DWC OTG HCD. */
+-00399         dwc_otg_hcd = dwc_otg_hcd_alloc_hcd();
+-00400         if (!dwc_otg_hcd) {
+-00401                 goto error2;
+-00402         }
+-00403         ((struct wrapper_priv_data *)(hcd->hcd_priv))->dwc_otg_hcd =
+-00404             dwc_otg_hcd;
+-00405         otg_dev->hcd = dwc_otg_hcd;
+-00406 
+-00407         if (dwc_otg_hcd_init(dwc_otg_hcd, otg_dev->core_if)) {
+-00408                 goto error2;
+-00409         }
+-00410 
+-00411         otg_dev->hcd->otg_dev = otg_dev;
+-00412         hcd->self.otg_port = dwc_otg_hcd_otg_port(dwc_otg_hcd);
+-00413 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,33) //don't support for LM(with 2.6.20.1 kernel)
+-00414         hcd->self.otg_version = dwc_otg_get_otg_version(otg_dev->core_if);
+-00415         /* Don't support SG list at this point */
+-00416         hcd->self.sg_tablesize = 0;
+-00417 #endif
+-00418         /*
+-00419          * Finish generic HCD initialization and start the HCD. This function
+-00420          * allocates the DMA buffer pool, registers the USB bus, requests the
+-00421          * IRQ line, and calls hcd_start method.
+-00422          */
+-00423         retval = usb_add_hcd(hcd, _dev->irq, IRQF_SHARED | IRQF_DISABLED);
+-00424         if (retval < 0) {
+-00425                 goto error2;
+-00426         }
+-00427 
+-00428         dwc_otg_hcd_set_priv_data(dwc_otg_hcd, hcd);
+-00429         return 0;
+-00430 
+-00431 error2:
+-00432         usb_put_hcd(hcd);
+-00433 error1:
+-00434         return retval;
+-00435 }
+-00436 
+-00441 void hcd_remove(
+-00442 #ifdef LM_INTERFACE
+-00443                        struct lm_device *_dev
+-00444 #elif  defined(PCI_INTERFACE)
+-00445                        struct pci_dev *_dev
+-00446 #endif
+-00447     )
+-00448 {
+-00449 #ifdef LM_INTERFACE
+-00450         dwc_otg_device_t *otg_dev = lm_get_drvdata(_dev);
+-00451 #elif  defined(PCI_INTERFACE)
+-00452         dwc_otg_device_t *otg_dev = pci_get_drvdata(_dev);
+-00453 #endif
+-00454 
+-00455         dwc_otg_hcd_t *dwc_otg_hcd;
+-00456         struct usb_hcd *hcd;
+-00457 
+-00458         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD REMOVE\n");
+-00459 
+-00460         if (!otg_dev) {
+-00461                 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev NULL!\n", __func__);
+-00462                 return;
+-00463         }
+-00464 
+-00465         dwc_otg_hcd = otg_dev->hcd;
+-00466 
+-00467         if (!dwc_otg_hcd) {
+-00468                 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->hcd NULL!\n", __func__);
+-00469                 return;
+-00470         }
+-00471 
+-00472         hcd = dwc_otg_hcd_to_hcd(dwc_otg_hcd);
+-00473 
+-00474         if (!hcd) {
+-00475                 DWC_DEBUGPL(DBG_ANY,
+-00476                             "%s: dwc_otg_hcd_to_hcd(dwc_otg_hcd) NULL!\n",
+-00477                             __func__);
+-00478                 return;
+-00479         }
+-00480         usb_remove_hcd(hcd);
+-00481         dwc_otg_hcd_set_priv_data(dwc_otg_hcd, NULL);
+-00482         dwc_otg_hcd_remove(dwc_otg_hcd);
+-00483         usb_put_hcd(hcd);
+-00484 }
+-00485 
+-00486 /* =========================================================================
+-00487  *  Linux HC Driver Functions
+-00488  * ========================================================================= */
+-00489 
+-00493 int hcd_start(struct usb_hcd *hcd)
+-00494 {
+-00495         dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
+-00496         struct usb_bus *bus;
+-00497 
+-00498         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD START\n");
+-00499         bus = hcd_to_bus(hcd);
+-00500 
+-00501         hcd->state = HC_STATE_RUNNING;
+-00502         if (dwc_otg_hcd_start(dwc_otg_hcd, &hcd_fops)) {
+-00503                 return 0;
+-00504         }
+-00505 
+-00506         /* Initialize and connect root hub if one is not already attached */
+-00507         if (bus->root_hub) {
+-00508                 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Has Root Hub\n");
+-00509                 /* Inform the HUB driver to resume. */
+-00510                 usb_hcd_resume_root_hub(hcd);
+-00511         }
+-00512 
+-00513         return 0;
+-00514 }
+-00515 
+-00520 void hcd_stop(struct usb_hcd *hcd)
+-00521 {
+-00522         dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
+-00523 
+-00524         dwc_otg_hcd_stop(dwc_otg_hcd);
+-00525 }
+-00526 
+-00528 static int get_frame_number(struct usb_hcd *hcd)
+-00529 {
+-00530         dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
+-00531 
+-00532         return dwc_otg_hcd_get_frame_number(dwc_otg_hcd);
+-00533 }
+-00534 
+-00535 #ifdef DEBUG
+-00536 static void dump_urb_info(struct urb *urb, char *fn_name)
+-00537 {
+-00538         DWC_PRINTF("%s, urb %p\n", fn_name, urb);
+-00539         DWC_PRINTF("  Device address: %d\n", usb_pipedevice(urb->pipe));
+-00540         DWC_PRINTF("  Endpoint: %d, %s\n", usb_pipeendpoint(urb->pipe),
+-00541                    (usb_pipein(urb->pipe) ? "IN" : "OUT"));
+-00542         DWC_PRINTF("  Endpoint type: %s\n", ( {
+-00543                                              char *pipetype;
+-00544                                              switch (usb_pipetype(urb->pipe)) {
+-00545 case PIPE_CONTROL:
+-00546 pipetype = "CONTROL"; break; case PIPE_BULK:
+-00547 pipetype = "BULK"; break; case PIPE_INTERRUPT:
+-00548 pipetype = "INTERRUPT"; break; case PIPE_ISOCHRONOUS:
+-00549 pipetype = "ISOCHRONOUS"; break; default:
+-00550                                              pipetype = "UNKNOWN"; break;};
+-00551                                              pipetype;}
+-00552                    )) ;
+-00553         DWC_PRINTF("  Speed: %s\n", ( {
+-00554                                      char *speed; switch (urb->dev->speed) {
+-00555 case USB_SPEED_HIGH:
+-00556 speed = "HIGH"; break; case USB_SPEED_FULL:
+-00557 speed = "FULL"; break; case USB_SPEED_LOW:
+-00558 speed = "LOW"; break; default:
+-00559                                      speed = "UNKNOWN"; break;};
+-00560                                      speed;}
+-00561                    )) ;
+-00562         DWC_PRINTF("  Max packet size: %d\n",
+-00563                    usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe)));
+-00564         DWC_PRINTF("  Data buffer length: %d\n", urb->transfer_buffer_length);
+-00565         DWC_PRINTF("  Transfer buffer: %p, Transfer DMA: %p\n",
+-00566                    urb->transfer_buffer, (void *)urb->transfer_dma);
+-00567         DWC_PRINTF("  Setup buffer: %p, Setup DMA: %p\n",
+-00568                    urb->setup_packet, (void *)urb->setup_dma);
+-00569         DWC_PRINTF("  Interval: %d\n", urb->interval);
+-00570         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
+-00571                 int i;
+-00572                 for (i = 0; i < urb->number_of_packets; i++) {
+-00573                         DWC_PRINTF("  ISO Desc %d:\n", i);
+-00574                         DWC_PRINTF("    offset: %d, length %d\n",
+-00575                                    urb->iso_frame_desc[i].offset,
+-00576                                    urb->iso_frame_desc[i].length);
+-00577                 }
+-00578         }
+-00579 }
+-00580 
+-00581 #endif
+-00582 
+-00586 static int urb_enqueue(struct usb_hcd *hcd,
+-00587 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28)
+-00588                        struct usb_host_endpoint *ep,
+-00589 #endif
+-00590                        struct urb *urb, gfp_t mem_flags)
+-00591 {
+-00592         int retval = 0;
+-00593 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,28)
+-00594         struct usb_host_endpoint *ep = urb->ep;
+-00595 #endif
+-00596         dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
+-00597         dwc_otg_hcd_urb_t *dwc_otg_urb;
+-00598         int i;
+-00599         int alloc_bandwidth = 0;
+-00600         uint8_t ep_type = 0;
+-00601         uint32_t flags = 0;
+-00602         void *buf;
+-00603 
+-00604 #ifdef DEBUG
+-00605         if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
+-00606                 dump_urb_info(urb, "urb_enqueue");
+-00607         }
+-00608 #endif
+-00609 
+-00610         if ((usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
+-00611             || (usb_pipetype(urb->pipe) == PIPE_INTERRUPT)) {
+-00612                 if (!dwc_otg_hcd_is_bandwidth_allocated
+-00613                     (dwc_otg_hcd, &ep->hcpriv)) {
+-00614                         alloc_bandwidth = 1;
+-00615                 }
+-00616         }
+-00617 
+-00618         switch (usb_pipetype(urb->pipe)) {
+-00619         case PIPE_CONTROL:
+-00620                 ep_type = USB_ENDPOINT_XFER_CONTROL;
+-00621                 break;
+-00622         case PIPE_ISOCHRONOUS:
+-00623                 ep_type = USB_ENDPOINT_XFER_ISOC;
+-00624                 break;
+-00625         case PIPE_BULK:
+-00626                 ep_type = USB_ENDPOINT_XFER_BULK;
+-00627                 break;
+-00628         case PIPE_INTERRUPT:
+-00629                 ep_type = USB_ENDPOINT_XFER_INT;
+-00630                 break;
+-00631         default:
+-00632                 DWC_WARN("Wrong ep type\n");
+-00633         }
+-00634 
+-00635         dwc_otg_urb = dwc_otg_hcd_urb_alloc(dwc_otg_hcd,
+-00636                                             urb->number_of_packets,
+-00637                                             mem_flags == GFP_ATOMIC ? 1 : 0);
+-00638 
+-00639         dwc_otg_hcd_urb_set_pipeinfo(dwc_otg_urb, usb_pipedevice(urb->pipe),
+-00640                                      usb_pipeendpoint(urb->pipe), ep_type,
+-00641                                      usb_pipein(urb->pipe),
+-00642                                      usb_maxpacket(urb->dev, urb->pipe,
+-00643                                                    !(usb_pipein(urb->pipe))));
+-00644 
+-00645         buf = urb->transfer_buffer;
+-00646         if (hcd->self.uses_dma) {
+-00647                 /*
+-00648                  * Calculate virtual address from physical address,
+-00649                  * because some class driver may not fill transfer_buffer.
+-00650                  * In Buffer DMA mode virual address is used,
+-00651                  * when handling non DWORD aligned buffers.
+-00652                  */
+-00653                 buf = phys_to_virt(urb->transfer_dma);
+-00654         }
+-00655 
+-00656         if (!(urb->transfer_flags & URB_NO_INTERRUPT))
+-00657                 flags |= URB_GIVEBACK_ASAP;
+-00658         if (urb->transfer_flags & URB_ZERO_PACKET)
+-00659                 flags |= URB_SEND_ZERO_PACKET;
+-00660 
+-00661         dwc_otg_hcd_urb_set_params(dwc_otg_urb, urb, buf,
+-00662                                    urb->transfer_dma,
+-00663                                    urb->transfer_buffer_length,
+-00664                                    urb->setup_packet,
+-00665                                    urb->setup_dma, flags, urb->interval);
+-00666 
+-00667         for (i = 0; i < urb->number_of_packets; ++i) {
+-00668                 dwc_otg_hcd_urb_set_iso_desc_params(dwc_otg_urb, i,
+-00669                                                     urb->
+-00670                                                     iso_frame_desc[i].offset,
+-00671                                                     urb->
+-00672                                                     iso_frame_desc[i].length);
+-00673         }
+-00674 
+-00675         urb->hcpriv = dwc_otg_urb;
+-00676         retval = dwc_otg_hcd_urb_enqueue(dwc_otg_hcd, dwc_otg_urb, &ep->hcpriv,
+-00677                                          mem_flags == GFP_ATOMIC ? 1 : 0);
+-00678         if (!retval) {
+-00679                 if (alloc_bandwidth) {
+-00680                         allocate_bus_bandwidth(hcd,
+-00681                                                dwc_otg_hcd_get_ep_bandwidth
+-00682                                                (dwc_otg_hcd, ep->hcpriv), urb);
+-00683                 }
+-00684         } else {
+-00685                 if (retval == -DWC_E_NO_DEVICE) {
+-00686                         retval = -ENODEV;
+-00687                 }
+-00688         }
+-00689 
+-00690         return retval;
+-00691 }
+-00692 
+-00695 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28)
+-00696 static int urb_dequeue(struct usb_hcd *hcd, struct urb *urb)
+-00697 #else
+-00698 static int urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
+-00699 #endif
+-00700 {
+-00701         dwc_irqflags_t flags;
+-00702         dwc_otg_hcd_t *dwc_otg_hcd;
+-00703         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD URB Dequeue\n");
+-00704 
+-00705         dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
+-00706 
+-00707 #ifdef DEBUG
+-00708         if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
+-00709                 dump_urb_info(urb, "urb_dequeue");
+-00710         }
+-00711 #endif
+-00712 
+-00713         DWC_SPINLOCK_IRQSAVE(dwc_otg_hcd->lock, &flags);
+-00714 
+-00715         dwc_otg_hcd_urb_dequeue(dwc_otg_hcd, urb->hcpriv);
+-00716 
+-00717         DWC_FREE(urb->hcpriv);
+-00718         urb->hcpriv = NULL;
+-00719         DWC_SPINUNLOCK_IRQRESTORE(dwc_otg_hcd->lock, flags);
+-00720 
+-00721         /* Higher layer software sets URB status. */
+-00722 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28)
+-00723         usb_hcd_giveback_urb(hcd, urb);
+-00724 #else
+-00725         usb_hcd_giveback_urb(hcd, urb, status);
+-00726 #endif
+-00727         if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
+-00728                 DWC_PRINTF("Called usb_hcd_giveback_urb()\n");
+-00729                 DWC_PRINTF("  urb->status = %d\n", urb->status);
+-00730         }
+-00731 
+-00732         return 0;
+-00733 }
+-00734 
+-00735 /* Frees resources in the DWC_otg controller related to a given endpoint. Also
+-00736  * clears state in the HCD related to the endpoint. Any URBs for the endpoint
+-00737  * must already be dequeued. */
+-00738 static void endpoint_disable(struct usb_hcd *hcd, struct usb_host_endpoint *ep)
+-00739 {
+-00740         dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
+-00741 
+-00742         DWC_DEBUGPL(DBG_HCD,
+-00743                     "DWC OTG HCD EP DISABLE: _bEndpointAddress=0x%02x, "
+-00744                     "endpoint=%d\n", ep->desc.bEndpointAddress,
+-00745                     dwc_ep_addr_to_endpoint(ep->desc.bEndpointAddress));
+-00746         dwc_otg_hcd_endpoint_disable(dwc_otg_hcd, ep->hcpriv, 250);
+-00747         ep->hcpriv = NULL;
+-00748 }
+-00749 
+-00750 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,30)
+-00751 /* Resets endpoint specific parameter values, in current version used to reset 
+-00752  * the data toggle(as a WA). This function can be called from usb_clear_halt routine */
+-00753 static void endpoint_reset(struct usb_hcd *hcd, struct usb_host_endpoint *ep)
+-00754 {
+-00755         dwc_irqflags_t flags;
+-00756         struct usb_device *udev = NULL;
+-00757         int epnum = usb_endpoint_num(&ep->desc);
+-00758         int is_out = usb_endpoint_dir_out(&ep->desc);
+-00759         int is_control = usb_endpoint_xfer_control(&ep->desc);
+-00760         dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
+-00761 #ifdef LM_INTERFACE
+-00762         struct lm_device *_dev = dwc_otg_hcd->otg_dev->os_dep.lmdev;
+-00763 #elif defined(PCI_INTERFACE)
+-00764         struct pci_dev *_dev = dwc_otg_hcd->otg_dev->os_dep.pcidev;
+-00765 #endif
+-00766 
+-00767         if (_dev)
+-00768                 udev = to_usb_device(&_dev->dev);
+-00769         else
+-00770                 return;
+-00771 
+-00772         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD EP RESET: Endpoint Num=0x%02d\n", epnum);
+-00773 
+-00774         DWC_SPINLOCK_IRQSAVE(dwc_otg_hcd->lock, &flags);
+-00775         usb_settoggle(udev, epnum, is_out, 0);
+-00776         if (is_control)
+-00777                 usb_settoggle(udev, epnum, !is_out, 0);
+-00778 
+-00779         if (ep->hcpriv) {
+-00780                 dwc_otg_hcd_endpoint_reset(dwc_otg_hcd, ep->hcpriv);
+-00781         }
+-00782         DWC_SPINUNLOCK_IRQRESTORE(dwc_otg_hcd->lock, flags);
+-00783 }
+-00784 #endif
+-00785 
+-00791 static irqreturn_t dwc_otg_hcd_irq(struct usb_hcd *hcd)
+-00792 {
+-00793         dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
+-00794         int32_t retval = dwc_otg_hcd_handle_intr(dwc_otg_hcd);
+-00795         if (retval != 0) {
+-00796                 S3C2410X_CLEAR_EINTPEND();
+-00797         }
+-00798         return IRQ_RETVAL(retval);
+-00799 }
+-00800 
+-00805 int hub_status_data(struct usb_hcd *hcd, char *buf)
+-00806 {
+-00807         dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
+-00808 
+-00809         buf[0] = 0;
+-00810         buf[0] |= (dwc_otg_hcd_is_status_changed(dwc_otg_hcd, 1)) << 1;
+-00811 
+-00812         return (buf[0] != 0);
+-00813 }
+-00814 
+-00816 int hub_control(struct usb_hcd *hcd,
+-00817                 u16 typeReq, u16 wValue, u16 wIndex, char *buf, u16 wLength)
+-00818 {
+-00819         int retval;
+-00820 
+-00821         retval = dwc_otg_hcd_hub_control(hcd_to_dwc_otg_hcd(hcd),
+-00822                                          typeReq, wValue, wIndex, buf, wLength);
+-00823 
+-00824         switch (retval) {
+-00825         case -DWC_E_INVALID:
+-00826                 retval = -EINVAL;
+-00827                 break;
+-00828         }
+-00829 
+-00830         return retval;
+-00831 }
+-00832 
+-00833 #endif /* DWC_DEVICE_ONLY */
+-
                                                                                Generated on Thu Oct 27 03:56:37 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__hcd__linux_8c.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/dwc__otg__hcd__linux_8c.html 2013-07-26 19:34:41.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,604 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_hcd_linux.c File Reference +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                dwc_otg_hcd_linux.c File Reference

                                                                                This file contains the implementation of the HCD. More... +-

                                                                                +-#include <linux/kernel.h>
                                                                                +-#include <linux/module.h>
                                                                                +-#include <linux/moduleparam.h>
                                                                                +-#include <linux/init.h>
                                                                                +-#include <linux/device.h>
                                                                                +-#include <linux/errno.h>
                                                                                +-#include <linux/list.h>
                                                                                +-#include <linux/interrupt.h>
                                                                                +-#include <linux/string.h>
                                                                                +-#include <linux/dma-mapping.h>
                                                                                +-#include <linux/version.h>
                                                                                +-#include <asm/io.h>
                                                                                +-#include <linux/usb.h>
                                                                                +-#include <linux/usb/hcd.h>
                                                                                +-#include "dwc_otg_hcd_if.h"
                                                                                +-#include "dwc_otg_dbg.h"
                                                                                +-#include "dwc_otg_driver.h"
                                                                                +-#include "dwc_otg_hcd.h"
                                                                                +- +-

                                                                                +-Go to the source code of this file. +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-

                                                                                Data Structures

                                                                                struct  wrapper_priv_data

                                                                                Linux HC Driver API Functions

                                                                                int urb_enqueue (struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags)
                                                                                 Starts processing a USB transfer request specified by a USB Request Block (URB).
                                                                                int urb_dequeue (struct usb_hcd *hcd, struct urb *urb, int status)
                                                                                 Aborts/cancels a USB transfer request.
                                                                                +-void endpoint_disable (struct usb_hcd *hcd, struct usb_host_endpoint *ep)
                                                                                +-void endpoint_reset (struct usb_hcd *hcd, struct usb_host_endpoint *ep)
                                                                                irqreturn_t dwc_otg_hcd_irq (struct usb_hcd *hcd)
                                                                                 Handles host mode interrupts for the DWC_otg controller.
                                                                                int hcd_start (struct usb_hcd *hcd)
                                                                                 Initializes the DWC_otg controller and its root hub and prepares it for host mode operation.
                                                                                void hcd_stop (struct usb_hcd *hcd)
                                                                                 Halts the DWC_otg host mode operations in a clean manner.
                                                                                +-int get_frame_number (struct usb_hcd *hcd)
                                                                                 Returns the current frame number.
                                                                                int hub_status_data (struct usb_hcd *hcd, char *buf)
                                                                                 Creates Status Change bitmap for the root hub and root port.
                                                                                +-int hub_control (struct usb_hcd *hcd, u16 typeReq, u16 wValue, u16 wIndex, char *buf, u16 wLength)
                                                                                 Handles hub class-specific requests.

                                                                                Defines

                                                                                #define dwc_ep_addr_to_endpoint(_bEndpointAddress_)
                                                                                 Gets the endpoint number from a _bEndpointAddress argument.

                                                                                Functions

                                                                                +-dwc_otg_hcd_t * hcd_to_dwc_otg_hcd (struct usb_hcd *hcd)
                                                                                 Gets the dwc_otg_hcd from a struct usb_hcd.
                                                                                +-usb_hcd * dwc_otg_hcd_to_hcd (dwc_otg_hcd_t *dwc_otg_hcd)
                                                                                 Gets the struct usb_hcd that contains a dwc_otg_hcd_t.
                                                                                +-usb_host_endpoint * dwc_urb_to_endpoint (struct urb *urb)
                                                                                 Gets the usb_host_endpoint associated with an URB.
                                                                                +-int _disconnect (dwc_otg_hcd_t *hcd)
                                                                                +-int _start (dwc_otg_hcd_t *hcd)
                                                                                +-int _hub_info (dwc_otg_hcd_t *hcd, void *urb_handle, uint32_t *hub_addr, uint32_t *port_addr)
                                                                                +-int _speed (dwc_otg_hcd_t *hcd, void *urb_handle)
                                                                                +-int _get_b_hnp_enable (dwc_otg_hcd_t *hcd)
                                                                                +-void allocate_bus_bandwidth (struct usb_hcd *hcd, uint32_t bw, struct urb *urb)
                                                                                +-void free_bus_bandwidth (struct usb_hcd *hcd, uint32_t bw, struct urb *urb)
                                                                                int _complete (dwc_otg_hcd_t *hcd, void *urb_handle, dwc_otg_hcd_urb_t *dwc_otg_urb, int32_t status)
                                                                                 Sets the final status of an URB and returns it to the device driver.
                                                                                int hcd_init ()
                                                                                 Initializes the HCD.
                                                                                void hcd_remove ()
                                                                                 Removes the HCD.

                                                                                Variables

                                                                                +-const char dwc_otg_hcd_name [] = "dwc_otg_hcd"
                                                                                hc_driver dwc_otg_hc_driver
                                                                                dwc_otg_hcd_function_ops hcd_fops
                                                                                +-

                                                                                Detailed Description

                                                                                +-This file contains the implementation of the HCD. +-

                                                                                +-In Linux, the HCD implements the hc_driver API. +-

                                                                                +-Definition in file dwc_otg_hcd_linux.c.

                                                                                Define Documentation

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                #define dwc_ep_addr_to_endpoint ( _bEndpointAddress_   ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Value:

                                                                                ((_bEndpointAddress_ & USB_ENDPOINT_NUMBER_MASK) | \
+-                                                     ((_bEndpointAddress_ & USB_DIR_IN) != 0) << 4)
+-
                                                                                Gets the endpoint number from a _bEndpointAddress argument. +-

                                                                                +-The endpoint is qualified with its direction (possible 32 endpoints per device). +-

                                                                                +-Definition at line 68 of file dwc_otg_hcd_linux.c.

                                                                                +-

                                                                                Function Documentation

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                int urb_enqueue ( struct usb_hcd *  hcd,
                                                                                struct urb *  urb,
                                                                                gfp_t  mem_flags
                                                                                )  [static]
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Starts processing a USB transfer request specified by a USB Request Block (URB). +-

                                                                                +-mem_flags indicates the type of memory allocation to use while processing this URB. +-

                                                                                +-Definition at line 586 of file dwc_otg_hcd_linux.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                int urb_dequeue ( struct usb_hcd *  hcd,
                                                                                struct urb *  urb,
                                                                                int  status
                                                                                )  [static]
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Aborts/cancels a USB transfer request. +-

                                                                                +-Always returns 0 to indicate success. +-

                                                                                +-Definition at line 698 of file dwc_otg_hcd_linux.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                irqreturn_t dwc_otg_hcd_irq ( struct usb_hcd *  hcd  )  [static]
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Handles host mode interrupts for the DWC_otg controller. +-

                                                                                +-Returns IRQ_NONE if there was no interrupt to handle. Returns IRQ_HANDLED if there was a valid interrupt.

                                                                                +-This function is called by the USB core when an interrupt occurs +-

                                                                                +-Definition at line 791 of file dwc_otg_hcd_linux.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                int hcd_start ( struct usb_hcd *  hcd  ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Initializes the DWC_otg controller and its root hub and prepares it for host mode operation. +-

                                                                                +-Activates the root port. Returns 0 on success and a negative error code on failure. +-

                                                                                +-Definition at line 493 of file dwc_otg_hcd_linux.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                void hcd_stop ( struct usb_hcd *  hcd  ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Halts the DWC_otg host mode operations in a clean manner. +-

                                                                                +-USB transfers are stopped. +-

                                                                                +-Definition at line 520 of file dwc_otg_hcd_linux.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                int hub_status_data ( struct usb_hcd *  hcd,
                                                                                char *  buf
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Creates Status Change bitmap for the root hub and root port. +-

                                                                                +-The bitmap is returned in buf. Bit 0 is the status change indicator for the root hub. Bit 1 is the status change indicator for the single root port. Returns 1 if either change indicator is 1, otherwise returns 0. +-

                                                                                +-Definition at line 805 of file dwc_otg_hcd_linux.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                int _complete ( dwc_otg_hcd_t *  hcd,
                                                                                void *  urb_handle,
                                                                                dwc_otg_hcd_urb_t *  dwc_otg_urb,
                                                                                int32_t  status
                                                                                )  [static]
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Sets the final status of an URB and returns it to the device driver. +-

                                                                                +-Any required cleanup of the URB is performed. +-

                                                                                +-Definition at line 230 of file dwc_otg_hcd_linux.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +-
                                                                                int hcd_init (   ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Initializes the HCD. +-

                                                                                +-This function allocates memory for and initializes the static parts of the usb_hcd and dwc_otg_hcd structures. It also registers the USB bus with the core and calls the hc_driver->start() function. It returns a negative error on failure. +-

                                                                                +-Definition at line 339 of file dwc_otg_hcd_linux.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +-
                                                                                void hcd_remove (   ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Removes the HCD. +-

                                                                                +-Frees memory and resources associated with the HCD and deregisters the bus. +-

                                                                                +-Definition at line 441 of file dwc_otg_hcd_linux.c.

                                                                                +-

                                                                                Variable Documentation

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                struct hc_driver dwc_otg_hc_driver [static]
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Initial value:

                                                                                 {
+-
+-        .description = dwc_otg_hcd_name,
+-        .product_desc = "DWC OTG Controller",
+-        .hcd_priv_size = sizeof(struct wrapper_priv_data),
+-
+-        .irq = dwc_otg_hcd_irq,
+-
+-        .flags = HCD_MEMORY | HCD_USB2,
+-
+-        
+-        .start = hcd_start,
+-        
+-        
+-        .stop = hcd_stop,
+-
+-        .urb_enqueue = urb_enqueue,
+-        .urb_dequeue = urb_dequeue,
+-        .endpoint_disable = endpoint_disable,
+-
+-        .endpoint_reset = endpoint_reset,
+-
+-        .get_frame_number = get_frame_number,
+-
+-        .hub_status_data = hub_status_data,
+-        .hub_control = hub_control,
+-        
+-        
+-}
+-
                                                                                +-

                                                                                +-Definition at line 105 of file dwc_otg_hcd_linux.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                struct dwc_otg_hcd_function_ops hcd_fops [static]
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Initial value:

                                                                                 {
+-        .start = _start,
+-        .disconnect = _disconnect,
+-        .hub_info = _hub_info,
+-        .speed = _speed,
+-        .complete = _complete,
+-        .get_b_hnp_enable = _get_b_hnp_enable,
+-}
+-
                                                                                +-

                                                                                +-Definition at line 324 of file dwc_otg_hcd_linux.c.

                                                                                +-

                                                                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__hcd__queue_8c-source.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/dwc__otg__hcd__queue_8c-source.html 2013-07-26 19:34:41.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,612 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_hcd_queue.c Source File +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                dwc_otg_hcd_queue.c

                                                                                Go to the documentation of this file.
                                                                                00001 /* ==========================================================================
+-00002  * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd_queue.c $
+-00003  * $Revision: #44 $
+-00004  * $Date: 2011/10/26 $
+-00005  * $Change: 1873028 $
+-00006  *
+-00007  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
+-00008  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
+-00009  * otherwise expressly agreed to in writing between Synopsys and you.
+-00010  * 
+-00011  * The Software IS NOT an item of Licensed Software or Licensed Product under
+-00012  * any End User Software License Agreement or Agreement for Licensed Product
+-00013  * with Synopsys or any supplement thereto. You are permitted to use and
+-00014  * redistribute this Software in source and binary forms, with or without
+-00015  * modification, provided that redistributions of source code must retain this
+-00016  * notice. You may not view, use, disclose, copy or distribute this file or
+-00017  * any information contained herein except pursuant to this license grant from
+-00018  * Synopsys. If you do not agree with this notice, including the disclaimer
+-00019  * below, then you are not authorized to use the Software.
+-00020  * 
+-00021  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
+-00022  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+-00023  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+-00024  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
+-00025  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+-00026  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+-00027  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+-00028  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+-00029  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+-00030  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+-00031  * DAMAGE.
+-00032  * ========================================================================== */
+-00033 #ifndef DWC_DEVICE_ONLY
+-00034 
+-00042 #include "dwc_otg_hcd.h"
+-00043 #include "dwc_otg_regs.h"
+-00044 
+-00053 void dwc_otg_hcd_qh_free(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
+-00054 {
+-00055         dwc_otg_qtd_t *qtd, *qtd_tmp;
+-00056 
+-00057         /* Free each QTD in the QTD list */
+-00058         DWC_SPINLOCK(hcd->lock);
+-00059         DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp, &qh->qtd_list, qtd_list_entry) {
+-00060                 DWC_CIRCLEQ_REMOVE(&qh->qtd_list, qtd, qtd_list_entry);
+-00061                 dwc_otg_hcd_qtd_free(qtd);
+-00062         }
+-00063 
+-00064         if (hcd->core_if->dma_desc_enable) {
+-00065                 dwc_otg_hcd_qh_free_ddma(hcd, qh);
+-00066         } else if (qh->dw_align_buf) {
+-00067                 uint32_t buf_size;
+-00068                 if (qh->ep_type == UE_ISOCHRONOUS) {
+-00069                         buf_size = 4096;
+-00070                 } else {
+-00071                         buf_size = hcd->core_if->core_params->max_transfer_size;
+-00072                 }
+-00073                 DWC_DMA_FREE(buf_size, qh->dw_align_buf, qh->dw_align_buf_dma);
+-00074         }
+-00075 
+-00076         DWC_FREE(qh);
+-00077         DWC_SPINUNLOCK(hcd->lock);
+-00078         return;
+-00079 }
+-00080 
+-00081 #define BitStuffTime(bytecount)  ((8 * 7* bytecount) / 6)
+-00082 #define HS_HOST_DELAY           5       /* nanoseconds */
+-00083 #define FS_LS_HOST_DELAY        1000    /* nanoseconds */
+-00084 #define HUB_LS_SETUP            333     /* nanoseconds */
+-00085 #define NS_TO_US(ns)            ((ns + 500) / 1000)
+-00086                                 /* convert & round nanoseconds to microseconds */
+-00087 
+-00088 static uint32_t calc_bus_time(int speed, int is_in, int is_isoc, int bytecount)
+-00089 {
+-00090         unsigned long retval;
+-00091 
+-00092         switch (speed) {
+-00093         case USB_SPEED_HIGH:
+-00094                 if (is_isoc) {
+-00095                         retval =
+-00096                             ((38 * 8 * 2083) +
+-00097                              (2083 * (3 + BitStuffTime(bytecount)))) / 1000 +
+-00098                             HS_HOST_DELAY;
+-00099                 } else {
+-00100                         retval =
+-00101                             ((55 * 8 * 2083) +
+-00102                              (2083 * (3 + BitStuffTime(bytecount)))) / 1000 +
+-00103                             HS_HOST_DELAY;
+-00104                 }
+-00105                 break;
+-00106         case USB_SPEED_FULL:
+-00107                 if (is_isoc) {
+-00108                         retval =
+-00109                             (8354 * (31 + 10 * BitStuffTime(bytecount))) / 1000;
+-00110                         if (is_in) {
+-00111                                 retval = 7268 + FS_LS_HOST_DELAY + retval;
+-00112                         } else {
+-00113                                 retval = 6265 + FS_LS_HOST_DELAY + retval;
+-00114                         }
+-00115                 } else {
+-00116                         retval =
+-00117                             (8354 * (31 + 10 * BitStuffTime(bytecount))) / 1000;
+-00118                         retval = 9107 + FS_LS_HOST_DELAY + retval;
+-00119                 }
+-00120                 break;
+-00121         case USB_SPEED_LOW:
+-00122                 if (is_in) {
+-00123                         retval =
+-00124                             (67667 * (31 + 10 * BitStuffTime(bytecount))) /
+-00125                             1000;
+-00126                         retval =
+-00127                             64060 + (2 * HUB_LS_SETUP) + FS_LS_HOST_DELAY +
+-00128                             retval;
+-00129                 } else {
+-00130                         retval =
+-00131                             (66700 * (31 + 10 * BitStuffTime(bytecount))) /
+-00132                             1000;
+-00133                         retval =
+-00134                             64107 + (2 * HUB_LS_SETUP) + FS_LS_HOST_DELAY +
+-00135                             retval;
+-00136                 }
+-00137                 break;
+-00138         default:
+-00139                 DWC_WARN("Unknown device speed\n");
+-00140                 retval = -1;
+-00141         }
+-00142 
+-00143         return NS_TO_US(retval);
+-00144 }
+-00145 
+-00154 #define SCHEDULE_SLOP 10
+-00155 void qh_init(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh, dwc_otg_hcd_urb_t * urb)
+-00156 {
+-00157         char *speed, *type;
+-00158         int dev_speed;
+-00159         uint32_t hub_addr, hub_port;
+-00160 
+-00161         dwc_memset(qh, 0, sizeof(dwc_otg_qh_t));
+-00162 
+-00163         /* Initialize QH */
+-00164         qh->ep_type = dwc_otg_hcd_get_pipe_type(&urb->pipe_info);
+-00165         qh->ep_is_in = dwc_otg_hcd_is_pipe_in(&urb->pipe_info) ? 1 : 0;
+-00166 
+-00167         qh->data_toggle = DWC_OTG_HC_PID_DATA0;
+-00168         qh->maxp = dwc_otg_hcd_get_mps(&urb->pipe_info);
+-00169         DWC_CIRCLEQ_INIT(&qh->qtd_list);
+-00170         DWC_LIST_INIT(&qh->qh_list_entry);
+-00171         qh->channel = NULL;
+-00172 
+-00173         /* FS/LS Enpoint on HS Hub 
+-00174          * NOT virtual root hub */
+-00175         dev_speed = hcd->fops->speed(hcd, urb->priv);
+-00176 
+-00177         hcd->fops->hub_info(hcd, urb->priv, &hub_addr, &hub_port);
+-00178         qh->do_split = 0;
+-00179 
+-00180         if (((dev_speed == USB_SPEED_LOW) ||
+-00181              (dev_speed == USB_SPEED_FULL)) &&
+-00182             (hub_addr != 0 && hub_addr != 1)) {
+-00183                 DWC_DEBUGPL(DBG_HCD,
+-00184                             "QH init: EP %d: TT found at hub addr %d, for port %d\n",
+-00185                             dwc_otg_hcd_get_ep_num(&urb->pipe_info), hub_addr,
+-00186                             hub_port);
+-00187                 qh->do_split = 1;
+-00188         }
+-00189 
+-00190         if (qh->ep_type == UE_INTERRUPT || qh->ep_type == UE_ISOCHRONOUS) {
+-00191                 /* Compute scheduling parameters once and save them. */
+-00192                 hprt0_data_t hprt;
+-00193 
+-00195                 int bytecount =
+-00196                     dwc_hb_mult(qh->maxp) * dwc_max_packet(qh->maxp);
+-00197 
+-00198                 qh->usecs =
+-00199                     calc_bus_time((qh->do_split ? USB_SPEED_HIGH : dev_speed),
+-00200                                   qh->ep_is_in, (qh->ep_type == UE_ISOCHRONOUS),
+-00201                                   bytecount);
+-00202                 /* Start in a slightly future (micro)frame. */
+-00203                 qh->sched_frame = dwc_frame_num_inc(hcd->frame_number,
+-00204                                                     SCHEDULE_SLOP);
+-00205                 qh->interval = urb->interval;
+-00206 
+-00207 #if 0
+-00208                 /* Increase interrupt polling rate for debugging. */
+-00209                 if (qh->ep_type == UE_INTERRUPT) {
+-00210                         qh->interval = 8;
+-00211                 }
+-00212 #endif
+-00213                 hprt.d32 = DWC_READ_REG32(hcd->core_if->host_if->hprt0);
+-00214                 if ((hprt.b.prtspd == DWC_HPRT0_PRTSPD_HIGH_SPEED) &&
+-00215                     ((dev_speed == USB_SPEED_LOW) ||
+-00216                      (dev_speed == USB_SPEED_FULL))) {
+-00217                         qh->interval *= 8;
+-00218                         qh->sched_frame |= 0x7;
+-00219                         qh->start_split_frame = qh->sched_frame;
+-00220                 }
+-00221 
+-00222         }
+-00223 
+-00224         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD QH Initialized\n");
+-00225         DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH  - qh = %p\n", qh);
+-00226         DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH  - Device Address = %d\n",
+-00227                     dwc_otg_hcd_get_dev_addr(&urb->pipe_info));
+-00228         DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH  - Endpoint %d, %s\n",
+-00229                     dwc_otg_hcd_get_ep_num(&urb->pipe_info),
+-00230                     dwc_otg_hcd_is_pipe_in(&urb->pipe_info) ? "IN" : "OUT");
+-00231         switch (dev_speed) {
+-00232         case USB_SPEED_LOW:
+-00233                 qh->dev_speed = DWC_OTG_EP_SPEED_LOW;
+-00234                 speed = "low";
+-00235                 break;
+-00236         case USB_SPEED_FULL:
+-00237                 qh->dev_speed = DWC_OTG_EP_SPEED_FULL;
+-00238                 speed = "full";
+-00239                 break;
+-00240         case USB_SPEED_HIGH:
+-00241                 qh->dev_speed = DWC_OTG_EP_SPEED_HIGH;
+-00242                 speed = "high";
+-00243                 break;
+-00244         default:
+-00245                 speed = "?";
+-00246                 break;
+-00247         }
+-00248         DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH  - Speed = %s\n", speed);
+-00249 
+-00250         switch (qh->ep_type) {
+-00251         case UE_ISOCHRONOUS:
+-00252                 type = "isochronous";
+-00253                 break;
+-00254         case UE_INTERRUPT:
+-00255                 type = "interrupt";
+-00256                 break;
+-00257         case UE_CONTROL:
+-00258                 type = "control";
+-00259                 break;
+-00260         case UE_BULK:
+-00261                 type = "bulk";
+-00262                 break;
+-00263         default:
+-00264                 type = "?";
+-00265                 break;
+-00266         }
+-00267 
+-00268         DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH  - Type = %s\n", type);
+-00269 
+-00270 #ifdef DEBUG
+-00271         if (qh->ep_type == UE_INTERRUPT) {
+-00272                 DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - usecs = %d\n",
+-00273                             qh->usecs);
+-00274                 DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - interval = %d\n",
+-00275                             qh->interval);
+-00276         }
+-00277 #endif
+-00278 
+-00279 }
+-00280 
+-00290 dwc_otg_qh_t *dwc_otg_hcd_qh_create(dwc_otg_hcd_t * hcd,
+-00291                                     dwc_otg_hcd_urb_t * urb, int atomic_alloc)
+-00292 {
+-00293         dwc_otg_qh_t *qh;
+-00294 
+-00295         /* Allocate memory */
+-00297         qh = dwc_otg_hcd_qh_alloc(atomic_alloc);
+-00298         if (qh == NULL) {
+-00299                 DWC_ERROR("qh allocation failed");
+-00300                 return NULL;
+-00301         }
+-00302 
+-00303         qh_init(hcd, qh, urb);
+-00304 
+-00305         if (hcd->core_if->dma_desc_enable
+-00306             && (dwc_otg_hcd_qh_init_ddma(hcd, qh) < 0)) {
+-00307                 dwc_otg_hcd_qh_free(hcd, qh);
+-00308                 return NULL;
+-00309         }
+-00310 
+-00311         return qh;
+-00312 }
+-00313 
+-00319 static int periodic_channel_available(dwc_otg_hcd_t * hcd)
+-00320 {
+-00321         /*
+-00322          * Currently assuming that there is a dedicated host channnel for each
+-00323          * periodic transaction plus at least one host channel for
+-00324          * non-periodic transactions.
+-00325          */
+-00326         int status;
+-00327         int num_channels;
+-00328 
+-00329         num_channels = hcd->core_if->core_params->host_channels;
+-00330         if ((hcd->periodic_channels + hcd->non_periodic_channels < num_channels)
+-00331             && (hcd->periodic_channels < num_channels - 1)) {
+-00332                 status = 0;
+-00333         } else {
+-00334                 DWC_INFO("%s: Total channels: %d, Periodic: %d, Non-periodic: %d\n",
+-00335                         __func__, num_channels, hcd->periodic_channels, hcd->non_periodic_channels);    //NOTICE
+-00336                 status = -DWC_E_NO_SPACE;
+-00337         }
+-00338 
+-00339         return status;
+-00340 }
+-00341 
+-00352 static int check_periodic_bandwidth(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
+-00353 {
+-00354         int status;
+-00355         int16_t max_claimed_usecs;
+-00356 
+-00357         status = 0;
+-00358 
+-00359         if ((qh->dev_speed == DWC_OTG_EP_SPEED_HIGH) || qh->do_split) {
+-00360                 /*
+-00361                  * High speed mode.
+-00362                  * Max periodic usecs is 80% x 125 usec = 100 usec.
+-00363                  */
+-00364 
+-00365                 max_claimed_usecs = 100 - qh->usecs;
+-00366         } else {
+-00367                 /*
+-00368                  * Full speed mode.
+-00369                  * Max periodic usecs is 90% x 1000 usec = 900 usec.
+-00370                  */
+-00371                 max_claimed_usecs = 900 - qh->usecs;
+-00372         }
+-00373 
+-00374         if (hcd->periodic_usecs > max_claimed_usecs) {
+-00375                 DWC_INFO("%s: already claimed usecs %d, required usecs %d\n", __func__, hcd->periodic_usecs, qh->usecs);        //NOTICE
+-00376                 status = -DWC_E_NO_SPACE;
+-00377         }
+-00378 
+-00379         return status;
+-00380 }
+-00381 
+-00392 static int check_max_xfer_size(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
+-00393 {
+-00394         int status;
+-00395         uint32_t max_xfer_size;
+-00396         uint32_t max_channel_xfer_size;
+-00397 
+-00398         status = 0;
+-00399 
+-00400         max_xfer_size = dwc_max_packet(qh->maxp) * dwc_hb_mult(qh->maxp);
+-00401         max_channel_xfer_size = hcd->core_if->core_params->max_transfer_size;
+-00402 
+-00403         if (max_xfer_size > max_channel_xfer_size) {
+-00404                 DWC_INFO("%s: Periodic xfer length %d > " "max xfer length for channel %d\n",
+-00405                                 __func__, max_xfer_size, max_channel_xfer_size);        //NOTICE
+-00406                 status = -DWC_E_NO_SPACE;
+-00407         }
+-00408 
+-00409         return status;
+-00410 }
+-00411 
+-00421 static int schedule_periodic(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
+-00422 {
+-00423         int status = 0;
+-00424 
+-00425         status = periodic_channel_available(hcd);
+-00426         if (status) {
+-00427                 DWC_INFO("%s: No host channel available for periodic " "transfer.\n", __func__);        //NOTICE
+-00428                 return status;
+-00429         }
+-00430 
+-00431         status = check_periodic_bandwidth(hcd, qh);
+-00432         if (status) {
+-00433                 DWC_INFO("%s: Insufficient periodic bandwidth for " "periodic transfer.\n", __func__);  //NOTICE
+-00434                 return status;
+-00435         }
+-00436 
+-00437         status = check_max_xfer_size(hcd, qh);
+-00438         if (status) {
+-00439                 DWC_INFO("%s: Channel max transfer size too small " "for periodic transfer.\n", __func__);      //NOTICE
+-00440                 return status;
+-00441         }
+-00442 
+-00443         if (hcd->core_if->dma_desc_enable) {
+-00444                 /* Don't rely on SOF and start in ready schedule */
+-00445                 DWC_LIST_INSERT_TAIL(&hcd->periodic_sched_ready, &qh->qh_list_entry);
+-00446         }
+-00447         else {
+-00448         /* Always start in the inactive schedule. */
+-00449         DWC_LIST_INSERT_TAIL(&hcd->periodic_sched_inactive, &qh->qh_list_entry);
+-00450         }
+-00451 
+-00452         /* Reserve the periodic channel. */
+-00453         hcd->periodic_channels++;
+-00454 
+-00455         /* Update claimed usecs per (micro)frame. */
+-00456         hcd->periodic_usecs += qh->usecs;
+-00457 
+-00458         return status;
+-00459 }
+-00460 
+-00468 int dwc_otg_hcd_qh_add(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
+-00469 {
+-00470         int status = 0;
+-00471         gintmsk_data_t intr_mask = {.d32 = 0 };
+-00472 
+-00473         if (!DWC_LIST_EMPTY(&qh->qh_list_entry)) {
+-00474                 /* QH already in a schedule. */
+-00475                 return status;
+-00476         }
+-00477 
+-00478         /* Add the new QH to the appropriate schedule */
+-00479         if (dwc_qh_is_non_per(qh)) {
+-00480                 /* Always start in the inactive schedule. */
+-00481                 DWC_LIST_INSERT_TAIL(&hcd->non_periodic_sched_inactive,
+-00482                                      &qh->qh_list_entry);
+-00483         } else {
+-00484                 status = schedule_periodic(hcd, qh);
+-00485                 if ( !hcd->periodic_qh_count ) {
+-00486                         intr_mask.b.sofintr = 1;
+-00487                         DWC_MODIFY_REG32(&hcd->core_if->core_global_regs->gintmsk,
+-00488                                                                 intr_mask.d32, intr_mask.d32);
+-00489                 }
+-00490                 hcd->periodic_qh_count++;
+-00491         }
+-00492 
+-00493         return status;
+-00494 }
+-00495 
+-00502 static void deschedule_periodic(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
+-00503 {
+-00504         DWC_LIST_REMOVE_INIT(&qh->qh_list_entry);
+-00505 
+-00506         /* Release the periodic channel reservation. */
+-00507         hcd->periodic_channels--;
+-00508 
+-00509         /* Update claimed usecs per (micro)frame. */
+-00510         hcd->periodic_usecs -= qh->usecs;
+-00511 }
+-00512 
+-00519 void dwc_otg_hcd_qh_remove(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh)
+-00520 {
+-00521         gintmsk_data_t intr_mask = {.d32 = 0 };
+-00522 
+-00523         if (DWC_LIST_EMPTY(&qh->qh_list_entry)) {
+-00524                 /* QH is not in a schedule. */
+-00525                 return;
+-00526         }
+-00527 
+-00528         if (dwc_qh_is_non_per(qh)) {
+-00529                 if (hcd->non_periodic_qh_ptr == &qh->qh_list_entry) {
+-00530                         hcd->non_periodic_qh_ptr =
+-00531                             hcd->non_periodic_qh_ptr->next;
+-00532                 }
+-00533                 DWC_LIST_REMOVE_INIT(&qh->qh_list_entry);
+-00534         } else {
+-00535                 deschedule_periodic(hcd, qh);
+-00536                 hcd->periodic_qh_count--;
+-00537                 if( !hcd->periodic_qh_count ) {
+-00538                         intr_mask.b.sofintr = 1;
+-00539                                 DWC_MODIFY_REG32(&hcd->core_if->core_global_regs->gintmsk,
+-00540                                                                         intr_mask.d32, 0);
+-00541                 }
+-00542         }
+-00543 }
+-00544 
+-00558 void dwc_otg_hcd_qh_deactivate(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh,
+-00559                                int sched_next_periodic_split)
+-00560 {       
+-00561         if (dwc_qh_is_non_per(qh)) {
+-00562                 dwc_otg_hcd_qh_remove(hcd, qh);
+-00563                 if (!DWC_CIRCLEQ_EMPTY(&qh->qtd_list)) {
+-00564                         /* Add back to inactive non-periodic schedule. */
+-00565                         dwc_otg_hcd_qh_add(hcd, qh);
+-00566                 }
+-00567         } else {
+-00568                 uint16_t frame_number = dwc_otg_hcd_get_frame_number(hcd);
+-00569 
+-00570                 if (qh->do_split) {
+-00571                         /* Schedule the next continuing periodic split transfer */
+-00572                         if (sched_next_periodic_split) {
+-00573 
+-00574                                 qh->sched_frame = frame_number;
+-00575                                 if (dwc_frame_num_le(frame_number,
+-00576                                                      dwc_frame_num_inc
+-00577                                                      (qh->start_split_frame,
+-00578                                                       1))) {
+-00579                                         /*
+-00580                                          * Allow one frame to elapse after start
+-00581                                          * split microframe before scheduling
+-00582                                          * complete split, but DONT if we are
+-00583                                          * doing the next start split in the
+-00584                                          * same frame for an ISOC out.
+-00585                                          */
+-00586                                         if ((qh->ep_type != UE_ISOCHRONOUS) ||
+-00587                                             (qh->ep_is_in != 0)) {
+-00588                                                 qh->sched_frame =
+-00589                                                     dwc_frame_num_inc(qh->sched_frame, 1);
+-00590                                         }
+-00591                                 }
+-00592                         } else {
+-00593                                 qh->sched_frame =
+-00594                                     dwc_frame_num_inc(qh->start_split_frame,
+-00595                                                       qh->interval);
+-00596                                 if (dwc_frame_num_le
+-00597                                     (qh->sched_frame, frame_number)) {
+-00598                                         qh->sched_frame = frame_number;
+-00599                                 }
+-00600                                 qh->sched_frame |= 0x7;
+-00601                                 qh->start_split_frame = qh->sched_frame;
+-00602                         }
+-00603                 } else {
+-00604                         qh->sched_frame =
+-00605                             dwc_frame_num_inc(qh->sched_frame, qh->interval);
+-00606                         if (dwc_frame_num_le(qh->sched_frame, frame_number)) {
+-00607                                 qh->sched_frame = frame_number;
+-00608                         }
+-00609                 }
+-00610 
+-00611                 if (DWC_CIRCLEQ_EMPTY(&qh->qtd_list)) {
+-00612                         dwc_otg_hcd_qh_remove(hcd, qh);
+-00613                 } else {
+-00614                         /*
+-00615                          * Remove from periodic_sched_queued and move to
+-00616                          * appropriate queue.
+-00617                          */
+-00618                         if (qh->sched_frame == frame_number) {
+-00619                                 DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_ready,
+-00620                                                    &qh->qh_list_entry);
+-00621                         } else {
+-00622                                 DWC_LIST_MOVE_HEAD
+-00623                                     (&hcd->periodic_sched_inactive,
+-00624                                      &qh->qh_list_entry);
+-00625                         }
+-00626                 }
+-00627         }
+-00628 }
+-00629 
+-00638 dwc_otg_qtd_t *dwc_otg_hcd_qtd_create(dwc_otg_hcd_urb_t * urb, int atomic_alloc)
+-00639 {
+-00640         dwc_otg_qtd_t *qtd;
+-00641 
+-00642         qtd = dwc_otg_hcd_qtd_alloc(atomic_alloc);
+-00643         if (qtd == NULL) {
+-00644                 return NULL;
+-00645         }
+-00646 
+-00647         dwc_otg_hcd_qtd_init(qtd, urb);
+-00648         return qtd;
+-00649 }
+-00650 
+-00656 void dwc_otg_hcd_qtd_init(dwc_otg_qtd_t * qtd, dwc_otg_hcd_urb_t * urb)
+-00657 {
+-00658         dwc_memset(qtd, 0, sizeof(dwc_otg_qtd_t));
+-00659         qtd->urb = urb;
+-00660         if (dwc_otg_hcd_get_pipe_type(&urb->pipe_info) == UE_CONTROL) {
+-00661                 /*
+-00662                  * The only time the QTD data toggle is used is on the data
+-00663                  * phase of control transfers. This phase always starts with
+-00664                  * DATA1.
+-00665                  */
+-00666                 qtd->data_toggle = DWC_OTG_HC_PID_DATA1;
+-00667                 qtd->control_phase = DWC_OTG_CONTROL_SETUP;
+-00668         }
+-00669 
+-00670         /* start split */
+-00671         qtd->complete_split = 0;
+-00672         qtd->isoc_split_pos = DWC_HCSPLIT_XACTPOS_ALL;
+-00673         qtd->isoc_split_offset = 0;
+-00674         qtd->in_process = 0;
+-00675 
+-00676         /* Store the qtd ptr in the urb to reference what QTD. */
+-00677         urb->qtd = qtd;
+-00678         return;
+-00679 }
+-00680 
+-00694 int dwc_otg_hcd_qtd_add(dwc_otg_qtd_t * qtd,
+-00695                         dwc_otg_hcd_t * hcd, dwc_otg_qh_t ** qh, int atomic_alloc)
+-00696 {
+-00697         int retval = 0;
+-00698         dwc_irqflags_t flags;
+-00699 
+-00700         dwc_otg_hcd_urb_t *urb = qtd->urb;
+-00701 
+-00702         /*
+-00703          * Get the QH which holds the QTD-list to insert to. Create QH if it
+-00704          * doesn't exist.
+-00705          */
+-00706         if (*qh == NULL) {
+-00707                 *qh = dwc_otg_hcd_qh_create(hcd, urb, atomic_alloc);
+-00708                 if (*qh == NULL) {
+-00709                         retval = -1;
+-00710                         goto done;
+-00711                 }
+-00712         }
+-00713         DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
+-00714         retval = dwc_otg_hcd_qh_add(hcd, *qh);
+-00715         if (retval == 0) {
+-00716                 DWC_CIRCLEQ_INSERT_TAIL(&((*qh)->qtd_list), qtd,
+-00717                                         qtd_list_entry);
+-00718         }
+-00719         DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
+-00720 
+-00721 done:
+-00722 
+-00723         return retval;
+-00724 }
+-00725 
+-00726 #endif /* DWC_DEVICE_ONLY */
+-
                                                                                Generated on Thu Oct 27 03:56:37 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__hcd__queue_8c.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/dwc__otg__hcd__queue_8c.html 2013-07-26 19:34:41.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,799 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_hcd_queue.c File Reference +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                dwc_otg_hcd_queue.c File Reference

                                                                                This file contains the functions to manage Queue Heads and Queue Transfer Descriptors. More... +-

                                                                                +-#include "dwc_otg_hcd.h"
                                                                                +-#include "dwc_otg_regs.h"
                                                                                +- +-

                                                                                +-Go to the source code of this file. +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-

                                                                                Defines

                                                                                +-#define BitStuffTime(bytecount)   ((8 * 7* bytecount) / 6)
                                                                                +-#define HS_HOST_DELAY   5
                                                                                +-#define FS_LS_HOST_DELAY   1000
                                                                                +-#define HUB_LS_SETUP   333
                                                                                +-#define NS_TO_US(ns)   ((ns + 500) / 1000)
                                                                                #define SCHEDULE_SLOP   10
                                                                                 Initializes a QH structure.

                                                                                Functions

                                                                                void dwc_otg_hcd_qh_free (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
                                                                                 Free each QTD in the QH's QTD-list then free the QH.
                                                                                +-uint32_t calc_bus_time (int speed, int is_in, int is_isoc, int bytecount)
                                                                                void qh_init (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh, dwc_otg_hcd_urb_t *urb)
                                                                                dwc_otg_qh_t * dwc_otg_hcd_qh_create (dwc_otg_hcd_t *hcd, dwc_otg_hcd_urb_t *urb, int atomic_alloc)
                                                                                 This function allocates and initializes a QH.
                                                                                int periodic_channel_available (dwc_otg_hcd_t *hcd)
                                                                                 Checks that a channel is available for a periodic transfer.
                                                                                int check_periodic_bandwidth (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
                                                                                 Checks that there is sufficient bandwidth for the specified QH in the periodic schedule.
                                                                                int check_max_xfer_size (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
                                                                                 Checks that the max transfer size allowed in a host channel is large enough to handle the maximum data transfer in a single (micro)frame for a periodic transfer.
                                                                                int schedule_periodic (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
                                                                                 Schedules an interrupt or isochronous transfer in the periodic schedule.
                                                                                int dwc_otg_hcd_qh_add (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
                                                                                 This function adds a QH to either the non periodic or periodic schedule if it is not already in the schedule.
                                                                                void deschedule_periodic (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
                                                                                 Removes an interrupt or isochronous transfer from the periodic schedule.
                                                                                void dwc_otg_hcd_qh_remove (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
                                                                                 Removes a QH from either the non-periodic or periodic schedule.
                                                                                void dwc_otg_hcd_qh_deactivate (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh, int sched_next_periodic_split)
                                                                                 Deactivates a QH.
                                                                                dwc_otg_qtd_t * dwc_otg_hcd_qtd_create (dwc_otg_hcd_urb_t *urb, int atomic_alloc)
                                                                                 This function allocates and initializes a QTD.
                                                                                void dwc_otg_hcd_qtd_init (dwc_otg_qtd_t *qtd, dwc_otg_hcd_urb_t *urb)
                                                                                 Initializes a QTD structure.
                                                                                int dwc_otg_hcd_qtd_add (dwc_otg_qtd_t *qtd, dwc_otg_hcd_t *hcd, dwc_otg_qh_t **qh, int atomic_alloc)
                                                                                 This function adds a QTD to the QTD-list of a QH.
                                                                                +-

                                                                                Detailed Description

                                                                                +-This file contains the functions to manage Queue Heads and Queue Transfer Descriptors. +-

                                                                                +- +-

                                                                                +-Definition in file dwc_otg_hcd_queue.c.

                                                                                Define Documentation

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                #define SCHEDULE_SLOP   10
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Initializes a QH structure. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +- +-
                                                                                hcd The HCD state structure for the DWC OTG controller.
                                                                                qh The QH to init.
                                                                                urb Holds the information about the device/endpoint that we need to initialize the QH.
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 154 of file dwc_otg_hcd_queue.c.

                                                                                +-

                                                                                Function Documentation

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                void dwc_otg_hcd_qh_free ( dwc_otg_hcd_t *  hcd,
                                                                                dwc_otg_qh_t *  qh
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Free each QTD in the QH's QTD-list then free the QH. +-

                                                                                +-QH should already be removed from a list. QTD list should already be empty if called from URB Dequeue.

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +-
                                                                                hcd HCD instance.
                                                                                qh The QH to free.
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 53 of file dwc_otg_hcd_queue.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                void qh_init ( dwc_otg_hcd_t *  hcd,
                                                                                dwc_otg_qh_t *  qh,
                                                                                dwc_otg_hcd_urb_t *  urb
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-

                                                                                Todo:
                                                                                Account for split transfers in the bus time.
                                                                                +- +-

                                                                                +-Definition at line 155 of file dwc_otg_hcd_queue.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                dwc_otg_qh_t* dwc_otg_hcd_qh_create ( dwc_otg_hcd_t *  hcd,
                                                                                dwc_otg_hcd_urb_t *  urb,
                                                                                int  atomic_alloc
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This function allocates and initializes a QH. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +- +-
                                                                                hcd The HCD state structure for the DWC OTG controller.
                                                                                urb Holds the information about the device/endpoint that we need to initialize the QH.
                                                                                atomic_alloc Flag to do atomic allocation if needed
                                                                                +-
                                                                                +-
                                                                                Returns:
                                                                                Returns pointer to the newly allocated QH, or NULL on error.
                                                                                +-

                                                                                +-

                                                                                Todo:
                                                                                add memflags argument
                                                                                +- +-

                                                                                +-Definition at line 290 of file dwc_otg_hcd_queue.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                int periodic_channel_available ( dwc_otg_hcd_t *  hcd  )  [static]
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Checks that a channel is available for a periodic transfer. +-

                                                                                +-

                                                                                Returns:
                                                                                0 if successful, negative error code otherise.
                                                                                +- +-

                                                                                +-Definition at line 319 of file dwc_otg_hcd_queue.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                int check_periodic_bandwidth ( dwc_otg_hcd_t *  hcd,
                                                                                dwc_otg_qh_t *  qh
                                                                                )  [static]
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Checks that there is sufficient bandwidth for the specified QH in the periodic schedule. +-

                                                                                +-For simplicity, this calculation assumes that all the transfers in the periodic schedule may occur in the same (micro)frame.

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +-
                                                                                hcd The HCD state structure for the DWC OTG controller.
                                                                                qh QH containing periodic bandwidth required.
                                                                                +-
                                                                                +-
                                                                                Returns:
                                                                                0 if successful, negative error code otherwise.
                                                                                +- +-

                                                                                +-Definition at line 352 of file dwc_otg_hcd_queue.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                int check_max_xfer_size ( dwc_otg_hcd_t *  hcd,
                                                                                dwc_otg_qh_t *  qh
                                                                                )  [static]
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Checks that the max transfer size allowed in a host channel is large enough to handle the maximum data transfer in a single (micro)frame for a periodic transfer. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +-
                                                                                hcd The HCD state structure for the DWC OTG controller.
                                                                                qh QH for a periodic endpoint.
                                                                                +-
                                                                                +-
                                                                                Returns:
                                                                                0 if successful, negative error code otherwise.
                                                                                +- +-

                                                                                +-Definition at line 392 of file dwc_otg_hcd_queue.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                int schedule_periodic ( dwc_otg_hcd_t *  hcd,
                                                                                dwc_otg_qh_t *  qh
                                                                                )  [static]
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Schedules an interrupt or isochronous transfer in the periodic schedule. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +-
                                                                                hcd The HCD state structure for the DWC OTG controller.
                                                                                qh QH for the periodic transfer. The QH should already contain the scheduling information.
                                                                                +-
                                                                                +-
                                                                                Returns:
                                                                                0 if successful, negative error code otherwise.
                                                                                +- +-

                                                                                +-Definition at line 421 of file dwc_otg_hcd_queue.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                int dwc_otg_hcd_qh_add ( dwc_otg_hcd_t *  hcd,
                                                                                dwc_otg_qh_t *  qh
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This function adds a QH to either the non periodic or periodic schedule if it is not already in the schedule. +-

                                                                                +-If the QH is already in the schedule, no action is taken.

                                                                                +-

                                                                                Returns:
                                                                                0 if successful, negative error code otherwise.
                                                                                +- +-

                                                                                +-Definition at line 468 of file dwc_otg_hcd_queue.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                void deschedule_periodic ( dwc_otg_hcd_t *  hcd,
                                                                                dwc_otg_qh_t *  qh
                                                                                )  [static]
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Removes an interrupt or isochronous transfer from the periodic schedule. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +-
                                                                                hcd The HCD state structure for the DWC OTG controller.
                                                                                qh QH for the periodic transfer.
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 502 of file dwc_otg_hcd_queue.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                void dwc_otg_hcd_qh_remove ( dwc_otg_hcd_t *  hcd,
                                                                                dwc_otg_qh_t *  qh
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Removes a QH from either the non-periodic or periodic schedule. +-

                                                                                +-Memory is not freed.

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +-
                                                                                hcd The HCD state structure.
                                                                                qh QH to remove from schedule.
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 519 of file dwc_otg_hcd_queue.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                void dwc_otg_hcd_qh_deactivate ( dwc_otg_hcd_t *  hcd,
                                                                                dwc_otg_qh_t *  qh,
                                                                                int  sched_next_periodic_split
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Deactivates a QH. +-

                                                                                +-For non-periodic QHs, removes the QH from the active non-periodic schedule. The QH is added to the inactive non-periodic schedule if any QTDs are still attached to the QH.

                                                                                +-For periodic QHs, the QH is removed from the periodic queued schedule. If there are any QTDs still attached to the QH, the QH is added to either the periodic inactive schedule or the periodic ready schedule and its next scheduled frame is calculated. The QH is placed in the ready schedule if the scheduled frame has been reached already. Otherwise it's placed in the inactive schedule. If there are no QTDs attached to the QH, the QH is completely removed from the periodic schedule. +-

                                                                                +-Definition at line 558 of file dwc_otg_hcd_queue.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                dwc_otg_qtd_t* dwc_otg_hcd_qtd_create ( dwc_otg_hcd_urb_t *  urb,
                                                                                int  atomic_alloc
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This function allocates and initializes a QTD. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +-
                                                                                urb The URB to create a QTD from. Each URB-QTD pair will end up pointing to each other so each pair should have a unique correlation.
                                                                                atomic_alloc Flag to do atomic alloc if needed
                                                                                +-
                                                                                +-
                                                                                Returns:
                                                                                Returns pointer to the newly allocated QTD, or NULL on error.
                                                                                +- +-

                                                                                +-Definition at line 638 of file dwc_otg_hcd_queue.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                void dwc_otg_hcd_qtd_init ( dwc_otg_qtd_t *  qtd,
                                                                                dwc_otg_hcd_urb_t *  urb
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Initializes a QTD structure. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +-
                                                                                qtd The QTD to initialize.
                                                                                urb The URB to use for initialization.
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 656 of file dwc_otg_hcd_queue.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                int dwc_otg_hcd_qtd_add ( dwc_otg_qtd_t *  qtd,
                                                                                dwc_otg_hcd_t *  hcd,
                                                                                dwc_otg_qh_t **  qh,
                                                                                int  atomic_alloc
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This function adds a QTD to the QTD-list of a QH. +-

                                                                                +-It will find the correct QH to place the QTD into. If it does not find a QH, then it will create a new QH. If the QH to which the QTD is added is not currently scheduled, it is placed into the proper schedule based on its EP type.

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +- +- +-
                                                                                [in] qtd The QTD to add
                                                                                [in] hcd The DWC HCD structure
                                                                                [out] qh out parameter to return queue head
                                                                                atomic_alloc Flag to do atomic alloc if needed
                                                                                +-
                                                                                +-
                                                                                Returns:
                                                                                0 if successful, negative error code otherwise.
                                                                                +- +-

                                                                                +-Definition at line 694 of file dwc_otg_hcd_queue.c.

                                                                                +-

                                                                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__os__dep_8h-source.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/dwc__otg__os__dep_8h-source.html 2013-07-26 19:34:41.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,102 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_os_dep.h Source File +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                dwc_otg_os_dep.h

                                                                                Go to the documentation of this file.
                                                                                00001 #ifndef _DWC_OS_DEP_H_
+-00002 #define _DWC_OS_DEP_H_
+-00003 
+-00011 #include <linux/kernel.h>
+-00012 #include <linux/module.h>
+-00013 #include <linux/moduleparam.h>
+-00014 #include <linux/init.h>
+-00015 #include <linux/device.h>
+-00016 #include <linux/errno.h>
+-00017 #include <linux/types.h>
+-00018 #include <linux/slab.h>
+-00019 #include <linux/list.h>
+-00020 #include <linux/interrupt.h>
+-00021 #include <linux/ctype.h>
+-00022 #include <linux/string.h>
+-00023 #include <linux/dma-mapping.h>
+-00024 #include <linux/jiffies.h>
+-00025 #include <linux/delay.h>
+-00026 #include <linux/timer.h>
+-00027 #include <linux/workqueue.h>
+-00028 #include <linux/stat.h>
+-00029 #include <linux/pci.h>
+-00030 
+-00031 #include <linux/version.h>
+-00032 
+-00033 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
+-00034 # include <linux/irq.h>
+-00035 #endif
+-00036 
+-00037 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,21)
+-00038 # include <linux/usb/ch9.h>
+-00039 #else
+-00040 # include <linux/usb_ch9.h>
+-00041 #endif
+-00042 
+-00043 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,24)
+-00044 # include <linux/usb/gadget.h>
+-00045 #else
+-00046 # include <linux/usb_gadget.h>
+-00047 #endif
+-00048 
+-00049 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20)
+-00050 # include <asm/irq.h>
+-00051 #endif
+-00052 
+-00053 #ifdef PCI_INTERFACE
+-00054 # include <asm/io.h>
+-00055 #endif
+-00056 
+-00057 #ifdef LM_INTERFACE
+-00058 # include <asm/unaligned.h>
+-00059 # include <asm/sizes.h>
+-00060 # include <asm/param.h>
+-00061 # include <asm/io.h>
+-00062 # include <asm/arch/lm.h>
+-00063 # include <asm/arch/irqs.h>
+-00064 # include <asm/arch/regs-irq.h>
+-00065 #endif
+-00066 
+-00068 #define DWC_OS_PAGE_SIZE        PAGE_SIZE
+-00069 
+-00070 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,14)
+-00071 typedef int gfp_t;
+-00072 #endif
+-00073 
+-00074 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18)
+-00075 # define IRQF_SHARED SA_SHIRQ
+-00076 #endif
+-00077 
+-00078 typedef struct os_dependent {
+-00080         void *base;
+-00081 
+-00083         uint32_t reg_offset;
+-00084 
+-00085 #ifdef LM_INTERFACE
+-00086         struct lm_device *lmdev;
+-00087 #elif  defined(PCI_INTERFACE)
+-00088         struct pci_dev *pcidev;
+-00089 
+-00091         resource_size_t rsrc_start;
+-00092         
+-00094         resource_size_t rsrc_len;
+-00095 #endif
+-00096 } os_dependent_t;
+-00097 
+-00098 #ifdef __cplusplus
+-00099 }
+-00100 #endif
+-00101 
+-00102 #endif /* _DWC_OS_DEP_H_ */
+-
                                                                                Generated on Thu Oct 27 03:56:37 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__os__dep_8h.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/dwc__otg__os__dep_8h.html 2013-07-26 19:34:41.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,59 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_os_dep.h File Reference +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                dwc_otg_os_dep.h File Reference

                                                                                This file contains OS dependent structures. More... +-

                                                                                +-#include <linux/kernel.h>
                                                                                +-#include <linux/module.h>
                                                                                +-#include <linux/moduleparam.h>
                                                                                +-#include <linux/init.h>
                                                                                +-#include <linux/device.h>
                                                                                +-#include <linux/errno.h>
                                                                                +-#include <linux/types.h>
                                                                                +-#include <linux/slab.h>
                                                                                +-#include <linux/list.h>
                                                                                +-#include <linux/interrupt.h>
                                                                                +-#include <linux/ctype.h>
                                                                                +-#include <linux/string.h>
                                                                                +-#include <linux/dma-mapping.h>
                                                                                +-#include <linux/jiffies.h>
                                                                                +-#include <linux/delay.h>
                                                                                +-#include <linux/timer.h>
                                                                                +-#include <linux/workqueue.h>
                                                                                +-#include <linux/stat.h>
                                                                                +-#include <linux/pci.h>
                                                                                +-#include <linux/version.h>
                                                                                +-#include <linux/irq.h>
                                                                                +-#include <linux/usb/ch9.h>
                                                                                +-#include <linux/usb/gadget.h>
                                                                                +- +-

                                                                                +-Go to the source code of this file. +- +- +- +- +- +- +- +- +- +- +- +-

                                                                                Data Structures

                                                                                struct  os_dependent

                                                                                Defines

                                                                                +-#define DWC_OS_PAGE_SIZE   PAGE_SIZE
                                                                                 The OS page size.

                                                                                Typedefs

                                                                                +-typedef os_dependent os_dependent_t
                                                                                +-

                                                                                Detailed Description

                                                                                +-This file contains OS dependent structures. +-

                                                                                +- +-

                                                                                +-Definition in file dwc_otg_os_dep.h.

                                                                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__pcd_8c-source.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/dwc__otg__pcd_8c-source.html 2013-07-26 19:34:41.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,2438 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_pcd.c Source File +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                dwc_otg_pcd.c

                                                                                Go to the documentation of this file.
                                                                                00001 /* ==========================================================================
+-00002  * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_pcd.c $
+-00003  * $Revision: #99 $
+-00004  * $Date: 2011/10/24 $
+-00005  * $Change: 1871160 $
+-00006  *
+-00007  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
+-00008  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
+-00009  * otherwise expressly agreed to in writing between Synopsys and you.
+-00010  *
+-00011  * The Software IS NOT an item of Licensed Software or Licensed Product under
+-00012  * any End User Software License Agreement or Agreement for Licensed Product
+-00013  * with Synopsys or any supplement thereto. You are permitted to use and
+-00014  * redistribute this Software in source and binary forms, with or without
+-00015  * modification, provided that redistributions of source code must retain this
+-00016  * notice. You may not view, use, disclose, copy or distribute this file or
+-00017  * any information contained herein except pursuant to this license grant from
+-00018  * Synopsys. If you do not agree with this notice, including the disclaimer
+-00019  * below, then you are not authorized to use the Software.
+-00020  *
+-00021  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
+-00022  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+-00023  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+-00024  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
+-00025  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+-00026  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+-00027  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+-00028  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+-00029  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+-00030  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+-00031  * DAMAGE.
+-00032  * ========================================================================== */
+-00033 #ifndef DWC_HOST_ONLY
+-00034 
+-00051 #include "dwc_otg_pcd.h"
+-00052 
+-00053 #ifdef DWC_UTE_CFI
+-00054 #include "dwc_otg_cfi.h"
+-00055 
+-00056 extern int init_cfi(cfiobject_t * cfiobj);
+-00057 #endif
+-00058 
+-00062 static dwc_otg_pcd_ep_t *get_ep_from_handle(dwc_otg_pcd_t * pcd, void *handle)
+-00063 {
+-00064         int i;
+-00065         if (pcd->ep0.priv == handle) {
+-00066                 return &pcd->ep0;
+-00067         }
+-00068         for (i = 0; i < MAX_EPS_CHANNELS - 1; i++) {
+-00069                 if (pcd->in_ep[i].priv == handle)
+-00070                         return &pcd->in_ep[i];
+-00071                 if (pcd->out_ep[i].priv == handle)
+-00072                         return &pcd->out_ep[i];
+-00073         }
+-00074 
+-00075         return NULL;
+-00076 }
+-00077 
+-00081 void dwc_otg_request_done(dwc_otg_pcd_ep_t * ep, dwc_otg_pcd_request_t * req,
+-00082                           int32_t status)
+-00083 {
+-00084         unsigned stopped = ep->stopped;
+-00085         
+-00086         DWC_DEBUGPL(DBG_PCDV, "%s(ep %p req %p)\n", __func__, ep, req);
+-00087         DWC_CIRCLEQ_REMOVE_INIT(&ep->queue, req, queue_entry);
+-00088 
+-00089         /* don't modify queue heads during completion callback */
+-00090         ep->stopped = 1;
+-00091         /* spin_unlock/spin_lock now done in fops->complete() */
+-00092         ep->pcd->fops->complete(ep->pcd, ep->priv, req->priv, status,
+-00093                                 req->actual);
+-00094 
+-00095         if (ep->pcd->request_pending > 0) {
+-00096                 --ep->pcd->request_pending;
+-00097         }
+-00098 
+-00099         ep->stopped = stopped;
+-00100         DWC_FREE(req);
+-00101 }
+-00102 
+-00106 void dwc_otg_request_nuke(dwc_otg_pcd_ep_t * ep)
+-00107 {
+-00108         dwc_otg_pcd_request_t *req;
+-00109 
+-00110         ep->stopped = 1;
+-00111 
+-00112         /* called with irqs blocked?? */
+-00113         while (!DWC_CIRCLEQ_EMPTY(&ep->queue)) {
+-00114                 req = DWC_CIRCLEQ_FIRST(&ep->queue);
+-00115                 dwc_otg_request_done(ep, req, -DWC_E_SHUTDOWN);
+-00116         }
+-00117 }
+-00118 
+-00119 void dwc_otg_pcd_start(dwc_otg_pcd_t * pcd,
+-00120                        const struct dwc_otg_pcd_function_ops *fops)
+-00121 {
+-00122         pcd->fops = fops;
+-00123 }
+-00124 
+-00131 static int32_t dwc_otg_pcd_start_cb(void *p)
+-00132 {
+-00133         dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *) p;
+-00134         dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
+-00135 
+-00136         /*
+-00137          * Initialized the Core for Device mode.
+-00138          */
+-00139         if (dwc_otg_is_device_mode(core_if)) {
+-00140                 dwc_otg_core_dev_init(core_if);
+-00141                 /* Set core_if's lock pointer to the pcd->lock */
+-00142                 core_if->lock = pcd->lock;
+-00143         }
+-00144         return 1;
+-00145 }
+-00146 
+-00148 #ifdef DWC_UTE_CFI
+-00149 uint8_t *cfiw_ep_alloc_buffer(dwc_otg_pcd_t * pcd, void *pep, dwc_dma_t * addr,
+-00150                               size_t buflen, int flags)
+-00151 {
+-00152         dwc_otg_pcd_ep_t *ep;
+-00153         ep = get_ep_from_handle(pcd, pep);
+-00154         if (!ep) {
+-00155                 DWC_WARN("bad ep\n");
+-00156                 return -DWC_E_INVALID;
+-00157         }
+-00158 
+-00159         return pcd->cfi->ops.ep_alloc_buf(pcd->cfi, pcd, ep, addr, buflen,
+-00160                                           flags);
+-00161 }
+-00162 #else
+-00163 uint8_t *cfiw_ep_alloc_buffer(dwc_otg_pcd_t * pcd, void *pep, dwc_dma_t * addr,
+-00164                               size_t buflen, int flags);
+-00165 #endif
+-00166 
+-00173 static int32_t dwc_otg_pcd_resume_cb(void *p)
+-00174 {
+-00175         dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *) p;
+-00176 
+-00177         if (pcd->fops->resume) {
+-00178                 pcd->fops->resume(pcd);
+-00179         }
+-00180 
+-00181         /* Stop the SRP timeout timer. */
+-00182         if ((GET_CORE_IF(pcd)->core_params->phy_type != DWC_PHY_TYPE_PARAM_FS)
+-00183             || (!GET_CORE_IF(pcd)->core_params->i2c_enable)) {
+-00184                 if (GET_CORE_IF(pcd)->srp_timer_started) {
+-00185                         GET_CORE_IF(pcd)->srp_timer_started = 0;
+-00186                         DWC_TIMER_CANCEL(GET_CORE_IF(pcd)->srp_timer);
+-00187                 }
+-00188         }
+-00189         return 1;
+-00190 }
+-00191 
+-00197 static int32_t dwc_otg_pcd_suspend_cb(void *p)
+-00198 {
+-00199         dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *) p;
+-00200 
+-00201         if (pcd->fops->suspend) {
+-00202                 DWC_SPINUNLOCK(pcd->lock);
+-00203                 pcd->fops->suspend(pcd);
+-00204                 DWC_SPINLOCK(pcd->lock);
+-00205         }
+-00206 
+-00207         return 1;
+-00208 }
+-00209 
+-00216 static int32_t dwc_otg_pcd_stop_cb(void *p)
+-00217 {
+-00218         dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *) p;
+-00219         extern void dwc_otg_pcd_stop(dwc_otg_pcd_t * _pcd);
+-00220 
+-00221         dwc_otg_pcd_stop(pcd);
+-00222         return 1;
+-00223 }
+-00224 
+-00228 static dwc_otg_cil_callbacks_t pcd_callbacks = {
+-00229         .start = dwc_otg_pcd_start_cb,
+-00230         .stop = dwc_otg_pcd_stop_cb,
+-00231         .suspend = dwc_otg_pcd_suspend_cb,
+-00232         .resume_wakeup = dwc_otg_pcd_resume_cb,
+-00233         .p = 0,                 /* Set at registration */
+-00234 };
+-00235 
+-00240 dwc_otg_dev_dma_desc_t *dwc_otg_ep_alloc_desc_chain(dwc_dma_t * dma_desc_addr,
+-00241                                                     uint32_t count)
+-00242 {
+-00243         return DWC_DMA_ALLOC_ATOMIC(count * sizeof(dwc_otg_dev_dma_desc_t), 
+-00244                                                         dma_desc_addr);
+-00245 }
+-00246 
+-00250 void dwc_otg_ep_free_desc_chain(dwc_otg_dev_dma_desc_t * desc_addr,
+-00251                                 uint32_t dma_desc_addr, uint32_t count)
+-00252 {
+-00253         DWC_DMA_FREE(count * sizeof(dwc_otg_dev_dma_desc_t), desc_addr,
+-00254                      dma_desc_addr);
+-00255 }
+-00256 
+-00257 #ifdef DWC_EN_ISOC
+-00258 
+-00266 void dwc_otg_iso_ep_start_ddma_transfer(dwc_otg_core_if_t * core_if,
+-00267                                         dwc_ep_t * dwc_ep)
+-00268 {
+-00269 
+-00270         dsts_data_t dsts = {.d32 = 0 };
+-00271         depctl_data_t depctl = {.d32 = 0 };
+-00272         volatile uint32_t *addr;
+-00273         int i, j;
+-00274         uint32_t len;
+-00275 
+-00276         if (dwc_ep->is_in)
+-00277                 dwc_ep->desc_cnt = dwc_ep->buf_proc_intrvl / dwc_ep->bInterval;
+-00278         else
+-00279                 dwc_ep->desc_cnt =
+-00280                     dwc_ep->buf_proc_intrvl * dwc_ep->pkt_per_frm /
+-00281                     dwc_ep->bInterval;
+-00282 
+-00284         dwc_ep->iso_desc_addr =
+-00285             dwc_otg_ep_alloc_desc_chain(&dwc_ep->iso_dma_desc_addr,
+-00286                                         dwc_ep->desc_cnt * 2);
+-00287         if (dwc_ep->desc_addr) {
+-00288                 DWC_WARN("%s, can't allocate DMA descriptor chain\n", __func__);
+-00289                 return;
+-00290         }
+-00291 
+-00292         dsts.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts);
+-00293 
+-00295         if (dwc_ep->is_in == 0) {
+-00296                 dev_dma_desc_sts_t sts = {.d32 = 0 };
+-00297                 dwc_otg_dev_dma_desc_t *dma_desc = dwc_ep->iso_desc_addr;
+-00298                 dma_addr_t dma_ad;
+-00299                 uint32_t data_per_desc;
+-00300                 dwc_otg_dev_out_ep_regs_t *out_regs =
+-00301                     core_if->dev_if->out_ep_regs[dwc_ep->num];
+-00302                 int offset;
+-00303 
+-00304                 addr = &core_if->dev_if->out_ep_regs[dwc_ep->num]->doepctl;
+-00305                 dma_ad = (dma_addr_t) DWC_READ_REG32(&(out_regs->doepdma));
+-00306 
+-00308                 dma_ad = dwc_ep->dma_addr0;
+-00309 
+-00310                 sts.b_iso_out.bs = BS_HOST_READY;
+-00311                 sts.b_iso_out.rxsts = 0;
+-00312                 sts.b_iso_out.l = 0;
+-00313                 sts.b_iso_out.sp = 0;
+-00314                 sts.b_iso_out.ioc = 0;
+-00315                 sts.b_iso_out.pid = 0;
+-00316                 sts.b_iso_out.framenum = 0;
+-00317 
+-00318                 offset = 0;
+-00319                 for (i = 0; i < dwc_ep->desc_cnt - dwc_ep->pkt_per_frm;
+-00320                      i += dwc_ep->pkt_per_frm) {
+-00321 
+-00322                         for (j = 0; j < dwc_ep->pkt_per_frm; ++j) {
+-00323                                 uint32_t len = (j + 1) * dwc_ep->maxpacket;
+-00324                                 if (len > dwc_ep->data_per_frame)
+-00325                                         data_per_desc =
+-00326                                             dwc_ep->data_per_frame -
+-00327                                             j * dwc_ep->maxpacket;
+-00328                                 else
+-00329                                         data_per_desc = dwc_ep->maxpacket;
+-00330                                 len = data_per_desc % 4;
+-00331                                 if (len)
+-00332                                         data_per_desc += 4 - len;
+-00333 
+-00334                                 sts.b_iso_out.rxbytes = data_per_desc;
+-00335                                 dma_desc->buf = dma_ad;
+-00336                                 dma_desc->status.d32 = sts.d32;
+-00337 
+-00338                                 offset += data_per_desc;
+-00339                                 dma_desc++;
+-00340                                 dma_ad += data_per_desc;
+-00341                         }
+-00342                 }
+-00343 
+-00344                 for (j = 0; j < dwc_ep->pkt_per_frm - 1; ++j) {
+-00345                         uint32_t len = (j + 1) * dwc_ep->maxpacket;
+-00346                         if (len > dwc_ep->data_per_frame)
+-00347                                 data_per_desc =
+-00348                                     dwc_ep->data_per_frame -
+-00349                                     j * dwc_ep->maxpacket;
+-00350                         else
+-00351                                 data_per_desc = dwc_ep->maxpacket;
+-00352                         len = data_per_desc % 4;
+-00353                         if (len)
+-00354                                 data_per_desc += 4 - len;
+-00355                         sts.b_iso_out.rxbytes = data_per_desc;
+-00356                         dma_desc->buf = dma_ad;
+-00357                         dma_desc->status.d32 = sts.d32;
+-00358 
+-00359                         offset += data_per_desc;
+-00360                         dma_desc++;
+-00361                         dma_ad += data_per_desc;
+-00362                 }
+-00363 
+-00364                 sts.b_iso_out.ioc = 1;
+-00365                 len = (j + 1) * dwc_ep->maxpacket;
+-00366                 if (len > dwc_ep->data_per_frame)
+-00367                         data_per_desc =
+-00368                             dwc_ep->data_per_frame - j * dwc_ep->maxpacket;
+-00369                 else
+-00370                         data_per_desc = dwc_ep->maxpacket;
+-00371                 len = data_per_desc % 4;
+-00372                 if (len)
+-00373                         data_per_desc += 4 - len;
+-00374                 sts.b_iso_out.rxbytes = data_per_desc;
+-00375 
+-00376                 dma_desc->buf = dma_ad;
+-00377                 dma_desc->status.d32 = sts.d32;
+-00378                 dma_desc++;
+-00379 
+-00381                 sts.b_iso_out.ioc = 0;
+-00382                 dma_ad = dwc_ep->dma_addr1;
+-00383 
+-00384                 offset = 0;
+-00385                 for (i = 0; i < dwc_ep->desc_cnt - dwc_ep->pkt_per_frm;
+-00386                      i += dwc_ep->pkt_per_frm) {
+-00387                         for (j = 0; j < dwc_ep->pkt_per_frm; ++j) {
+-00388                                 uint32_t len = (j + 1) * dwc_ep->maxpacket;
+-00389                                 if (len > dwc_ep->data_per_frame)
+-00390                                         data_per_desc =
+-00391                                             dwc_ep->data_per_frame -
+-00392                                             j * dwc_ep->maxpacket;
+-00393                                 else
+-00394                                         data_per_desc = dwc_ep->maxpacket;
+-00395                                 len = data_per_desc % 4;
+-00396                                 if (len)
+-00397                                         data_per_desc += 4 - len;
+-00398 
+-00399                                 data_per_desc =
+-00400                                     sts.b_iso_out.rxbytes = data_per_desc;
+-00401                                 dma_desc->buf = dma_ad;
+-00402                                 dma_desc->status.d32 = sts.d32;
+-00403 
+-00404                                 offset += data_per_desc;
+-00405                                 dma_desc++;
+-00406                                 dma_ad += data_per_desc;
+-00407                         }
+-00408                 }
+-00409                 for (j = 0; j < dwc_ep->pkt_per_frm - 1; ++j) {
+-00410                         data_per_desc =
+-00411                             ((j + 1) * dwc_ep->maxpacket >
+-00412                              dwc_ep->data_per_frame) ? dwc_ep->data_per_frame -
+-00413                             j * dwc_ep->maxpacket : dwc_ep->maxpacket;
+-00414                         data_per_desc +=
+-00415                             (data_per_desc % 4) ? (4 - data_per_desc % 4) : 0;
+-00416                         sts.b_iso_out.rxbytes = data_per_desc;
+-00417                         dma_desc->buf = dma_ad;
+-00418                         dma_desc->status.d32 = sts.d32;
+-00419 
+-00420                         offset += data_per_desc;
+-00421                         dma_desc++;
+-00422                         dma_ad += data_per_desc;
+-00423                 }
+-00424 
+-00425                 sts.b_iso_out.ioc = 1;
+-00426                 sts.b_iso_out.l = 1;
+-00427                 data_per_desc =
+-00428                     ((j + 1) * dwc_ep->maxpacket >
+-00429                      dwc_ep->data_per_frame) ? dwc_ep->data_per_frame -
+-00430                     j * dwc_ep->maxpacket : dwc_ep->maxpacket;
+-00431                 data_per_desc +=
+-00432                     (data_per_desc % 4) ? (4 - data_per_desc % 4) : 0;
+-00433                 sts.b_iso_out.rxbytes = data_per_desc;
+-00434 
+-00435                 dma_desc->buf = dma_ad;
+-00436                 dma_desc->status.d32 = sts.d32;
+-00437 
+-00438                 dwc_ep->next_frame = 0;
+-00439 
+-00441                 DWC_WRITE_REG32(&(out_regs->doepdma),
+-00442                                 (uint32_t) dwc_ep->iso_dma_desc_addr);
+-00443 
+-00444         }
+-00446         else {
+-00447                 dev_dma_desc_sts_t sts = {.d32 = 0 };
+-00448                 dwc_otg_dev_dma_desc_t *dma_desc = dwc_ep->iso_desc_addr;
+-00449                 dma_addr_t dma_ad;
+-00450                 dwc_otg_dev_in_ep_regs_t *in_regs =
+-00451                     core_if->dev_if->in_ep_regs[dwc_ep->num];
+-00452                 unsigned int frmnumber;
+-00453                 fifosize_data_t txfifosize, rxfifosize;
+-00454 
+-00455                 txfifosize.d32 =
+-00456                     DWC_READ_REG32(&core_if->dev_if->
+-00457                                    in_ep_regs[dwc_ep->num]->dtxfsts);
+-00458                 rxfifosize.d32 =
+-00459                     DWC_READ_REG32(&core_if->core_global_regs->grxfsiz);
+-00460 
+-00461                 addr = &core_if->dev_if->in_ep_regs[dwc_ep->num]->diepctl;
+-00462 
+-00463                 dma_ad = dwc_ep->dma_addr0;
+-00464 
+-00465                 dsts.d32 =
+-00466                     DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts);
+-00467 
+-00468                 sts.b_iso_in.bs = BS_HOST_READY;
+-00469                 sts.b_iso_in.txsts = 0;
+-00470                 sts.b_iso_in.sp =
+-00471                     (dwc_ep->data_per_frame % dwc_ep->maxpacket) ? 1 : 0;
+-00472                 sts.b_iso_in.ioc = 0;
+-00473                 sts.b_iso_in.pid = dwc_ep->pkt_per_frm;
+-00474 
+-00475                 frmnumber = dwc_ep->next_frame;
+-00476 
+-00477                 sts.b_iso_in.framenum = frmnumber;
+-00478                 sts.b_iso_in.txbytes = dwc_ep->data_per_frame;
+-00479                 sts.b_iso_in.l = 0;
+-00480 
+-00482                 for (i = 0; i < dwc_ep->desc_cnt - 1; i++) {
+-00483                         dma_desc->buf = dma_ad;
+-00484                         dma_desc->status.d32 = sts.d32;
+-00485                         dma_desc++;
+-00486 
+-00487                         dma_ad += dwc_ep->data_per_frame;
+-00488                         sts.b_iso_in.framenum += dwc_ep->bInterval;
+-00489                 }
+-00490 
+-00491                 sts.b_iso_in.ioc = 1;
+-00492                 dma_desc->buf = dma_ad;
+-00493                 dma_desc->status.d32 = sts.d32;
+-00494                 ++dma_desc;
+-00495 
+-00497                 sts.b_iso_in.ioc = 0;
+-00498                 dma_ad = dwc_ep->dma_addr1;
+-00499 
+-00500                 for (i = 0; i < dwc_ep->desc_cnt - dwc_ep->pkt_per_frm;
+-00501                      i += dwc_ep->pkt_per_frm) {
+-00502                         dma_desc->buf = dma_ad;
+-00503                         dma_desc->status.d32 = sts.d32;
+-00504                         dma_desc++;
+-00505 
+-00506                         dma_ad += dwc_ep->data_per_frame;
+-00507                         sts.b_iso_in.framenum += dwc_ep->bInterval;
+-00508 
+-00509                         sts.b_iso_in.ioc = 0;
+-00510                 }
+-00511                 sts.b_iso_in.ioc = 1;
+-00512                 sts.b_iso_in.l = 1;
+-00513 
+-00514                 dma_desc->buf = dma_ad;
+-00515                 dma_desc->status.d32 = sts.d32;
+-00516 
+-00517                 dwc_ep->next_frame = sts.b_iso_in.framenum + dwc_ep->bInterval;
+-00518 
+-00520                 DWC_WRITE_REG32(&(in_regs->diepdma),
+-00521                                 (uint32_t) dwc_ep->iso_dma_desc_addr);
+-00522         }
+-00524         depctl.d32 = 0;
+-00525         depctl.b.epena = 1;
+-00526         depctl.b.usbactep = 1;
+-00527         depctl.b.cnak = 1;
+-00528 
+-00529         DWC_MODIFY_REG32(addr, depctl.d32, depctl.d32);
+-00530         depctl.d32 = DWC_READ_REG32(addr);
+-00531 }
+-00532 
+-00540 void dwc_otg_iso_ep_start_buf_transfer(dwc_otg_core_if_t * core_if,
+-00541                                        dwc_ep_t * ep)
+-00542 {
+-00543         depctl_data_t depctl = {.d32 = 0 };
+-00544         volatile uint32_t *addr;
+-00545 
+-00546         if (ep->is_in) {
+-00547                 addr = &core_if->dev_if->in_ep_regs[ep->num]->diepctl;
+-00548         } else {
+-00549                 addr = &core_if->dev_if->out_ep_regs[ep->num]->doepctl;
+-00550         }
+-00551 
+-00552         if (core_if->dma_enable == 0 || core_if->dma_desc_enable != 0) {
+-00553                 return;
+-00554         } else {
+-00555                 deptsiz_data_t deptsiz = {.d32 = 0 };
+-00556 
+-00557                 ep->xfer_len =
+-00558                     ep->data_per_frame * ep->buf_proc_intrvl / ep->bInterval;
+-00559                 ep->pkt_cnt =
+-00560                     (ep->xfer_len - 1 + ep->maxpacket) / ep->maxpacket;
+-00561                 ep->xfer_count = 0;
+-00562                 ep->xfer_buff =
+-00563                     (ep->proc_buf_num) ? ep->xfer_buff1 : ep->xfer_buff0;
+-00564                 ep->dma_addr =
+-00565                     (ep->proc_buf_num) ? ep->dma_addr1 : ep->dma_addr0;
+-00566 
+-00567                 if (ep->is_in) {
+-00568                         /* Program the transfer size and packet count
+-00569                          *      as follows: xfersize = N * maxpacket +
+-00570                          *      short_packet pktcnt = N + (short_packet
+-00571                          *      exist ? 1 : 0) 
+-00572                          */
+-00573                         deptsiz.b.mc = ep->pkt_per_frm;
+-00574                         deptsiz.b.xfersize = ep->xfer_len;
+-00575                         deptsiz.b.pktcnt =
+-00576                             (ep->xfer_len - 1 + ep->maxpacket) / ep->maxpacket;
+-00577                         DWC_WRITE_REG32(&core_if->dev_if->
+-00578                                         in_ep_regs[ep->num]->dieptsiz,
+-00579                                         deptsiz.d32);
+-00580 
+-00581                         /* Write the DMA register */
+-00582                         DWC_WRITE_REG32(&
+-00583                                         (core_if->dev_if->
+-00584                                          in_ep_regs[ep->num]->diepdma),
+-00585                                         (uint32_t) ep->dma_addr);
+-00586 
+-00587                 } else {
+-00588                         deptsiz.b.pktcnt =
+-00589                             (ep->xfer_len + (ep->maxpacket - 1)) /
+-00590                             ep->maxpacket;
+-00591                         deptsiz.b.xfersize = deptsiz.b.pktcnt * ep->maxpacket;
+-00592 
+-00593                         DWC_WRITE_REG32(&core_if->dev_if->
+-00594                                         out_ep_regs[ep->num]->doeptsiz,
+-00595                                         deptsiz.d32);
+-00596 
+-00597                         /* Write the DMA register */
+-00598                         DWC_WRITE_REG32(&
+-00599                                         (core_if->dev_if->
+-00600                                          out_ep_regs[ep->num]->doepdma),
+-00601                                         (uint32_t) ep->dma_addr);
+-00602 
+-00603                 }
+-00605                 depctl.d32 = 0;
+-00606                 depctl.b.epena = 1;
+-00607                 depctl.b.cnak = 1;
+-00608 
+-00609                 DWC_MODIFY_REG32(addr, depctl.d32, depctl.d32);
+-00610         }
+-00611 }
+-00612 
+-00623 static void dwc_otg_iso_ep_start_transfer(dwc_otg_core_if_t * core_if,
+-00624                                           dwc_ep_t * ep)
+-00625 {
+-00626         if (core_if->dma_enable) {
+-00627                 if (core_if->dma_desc_enable) {
+-00628                         if (ep->is_in) {
+-00629                                 ep->desc_cnt = ep->pkt_cnt / ep->pkt_per_frm;
+-00630                         } else {
+-00631                                 ep->desc_cnt = ep->pkt_cnt;
+-00632                         }
+-00633                         dwc_otg_iso_ep_start_ddma_transfer(core_if, ep);
+-00634                 } else {
+-00635                         if (core_if->pti_enh_enable) {
+-00636                                 dwc_otg_iso_ep_start_buf_transfer(core_if, ep);
+-00637                         } else {
+-00638                                 ep->cur_pkt_addr =
+-00639                                     (ep->proc_buf_num) ? ep->
+-00640                                     xfer_buff1 : ep->xfer_buff0;
+-00641                                 ep->cur_pkt_dma_addr =
+-00642                                     (ep->proc_buf_num) ? ep->
+-00643                                     dma_addr1 : ep->dma_addr0;
+-00644                                 dwc_otg_iso_ep_start_frm_transfer(core_if, ep);
+-00645                         }
+-00646                 }
+-00647         } else {
+-00648                 ep->cur_pkt_addr =
+-00649                     (ep->proc_buf_num) ? ep->xfer_buff1 : ep->xfer_buff0;
+-00650                 ep->cur_pkt_dma_addr =
+-00651                     (ep->proc_buf_num) ? ep->dma_addr1 : ep->dma_addr0;
+-00652                 dwc_otg_iso_ep_start_frm_transfer(core_if, ep);
+-00653         }
+-00654 }
+-00655 
+-00664 void dwc_otg_iso_ep_stop_transfer(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
+-00665 {
+-00666         depctl_data_t depctl = {.d32 = 0 };
+-00667         volatile uint32_t *addr;
+-00668 
+-00669         if (ep->is_in == 1) {
+-00670                 addr = &core_if->dev_if->in_ep_regs[ep->num]->diepctl;
+-00671         } else {
+-00672                 addr = &core_if->dev_if->out_ep_regs[ep->num]->doepctl;
+-00673         }
+-00674 
+-00675         /* disable the ep */
+-00676         depctl.d32 = DWC_READ_REG32(addr);
+-00677 
+-00678         depctl.b.epdis = 1;
+-00679         depctl.b.snak = 1;
+-00680 
+-00681         DWC_WRITE_REG32(addr, depctl.d32);
+-00682 
+-00683         if (core_if->dma_desc_enable &&
+-00684             ep->iso_desc_addr && ep->iso_dma_desc_addr) {
+-00685                 dwc_otg_ep_free_desc_chain(ep->iso_desc_addr,
+-00686                                            ep->iso_dma_desc_addr,
+-00687                                            ep->desc_cnt * 2);
+-00688         }
+-00689 
+-00690         /* reset varibales */
+-00691         ep->dma_addr0 = 0;
+-00692         ep->dma_addr1 = 0;
+-00693         ep->xfer_buff0 = 0;
+-00694         ep->xfer_buff1 = 0;
+-00695         ep->data_per_frame = 0;
+-00696         ep->data_pattern_frame = 0;
+-00697         ep->sync_frame = 0;
+-00698         ep->buf_proc_intrvl = 0;
+-00699         ep->bInterval = 0;
+-00700         ep->proc_buf_num = 0;
+-00701         ep->pkt_per_frm = 0;
+-00702         ep->pkt_per_frm = 0;
+-00703         ep->desc_cnt = 0;
+-00704         ep->iso_desc_addr = 0;
+-00705         ep->iso_dma_desc_addr = 0;
+-00706 }
+-00707 
+-00708 int dwc_otg_pcd_iso_ep_start(dwc_otg_pcd_t * pcd, void *ep_handle,
+-00709                              uint8_t * buf0, uint8_t * buf1, dwc_dma_t dma0,
+-00710                              dwc_dma_t dma1, int sync_frame, int dp_frame,
+-00711                              int data_per_frame, int start_frame,
+-00712                              int buf_proc_intrvl, void *req_handle,
+-00713                              int atomic_alloc)
+-00714 {
+-00715         dwc_otg_pcd_ep_t *ep;
+-00716         dwc_irqflags_t flags = 0;
+-00717         dwc_ep_t *dwc_ep;
+-00718         int32_t frm_data;
+-00719         dsts_data_t dsts;
+-00720         dwc_otg_core_if_t *core_if;
+-00721 
+-00722         ep = get_ep_from_handle(pcd, ep_handle);
+-00723 
+-00724         if (!ep || !ep->desc || ep->dwc_ep.num == 0) {
+-00725                 DWC_WARN("bad ep\n");
+-00726                 return -DWC_E_INVALID;
+-00727         }
+-00728 
+-00729         DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
+-00730         core_if = GET_CORE_IF(pcd);
+-00731         dwc_ep = &ep->dwc_ep;
+-00732 
+-00733         if (ep->iso_req_handle) {
+-00734                 DWC_WARN("ISO request in progress\n");
+-00735         }
+-00736 
+-00737         dwc_ep->dma_addr0 = dma0;
+-00738         dwc_ep->dma_addr1 = dma1;
+-00739 
+-00740         dwc_ep->xfer_buff0 = buf0;
+-00741         dwc_ep->xfer_buff1 = buf1;
+-00742 
+-00743         dwc_ep->data_per_frame = data_per_frame;
+-00744 
+-00746         dwc_ep->data_pattern_frame = dp_frame;
+-00747         dwc_ep->sync_frame = sync_frame;
+-00748 
+-00749         dwc_ep->buf_proc_intrvl = buf_proc_intrvl;
+-00750 
+-00751         dwc_ep->bInterval = 1 << (ep->desc->bInterval - 1);
+-00752 
+-00753         dwc_ep->proc_buf_num = 0;
+-00754 
+-00755         dwc_ep->pkt_per_frm = 0;
+-00756         frm_data = ep->dwc_ep.data_per_frame;
+-00757         while (frm_data > 0) {
+-00758                 dwc_ep->pkt_per_frm++;
+-00759                 frm_data -= ep->dwc_ep.maxpacket;
+-00760         }
+-00761 
+-00762         dsts.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts);
+-00763 
+-00764         if (start_frame == -1) {
+-00765                 dwc_ep->next_frame = dsts.b.soffn + 1;
+-00766                 if (dwc_ep->bInterval != 1) {
+-00767                         dwc_ep->next_frame =
+-00768                             dwc_ep->next_frame + (dwc_ep->bInterval - 1 -
+-00769                                                   dwc_ep->next_frame %
+-00770                                                   dwc_ep->bInterval);
+-00771                 }
+-00772         } else {
+-00773                 dwc_ep->next_frame = start_frame;
+-00774         }
+-00775 
+-00776         if (!core_if->pti_enh_enable) {
+-00777                 dwc_ep->pkt_cnt =
+-00778                     dwc_ep->buf_proc_intrvl * dwc_ep->pkt_per_frm /
+-00779                     dwc_ep->bInterval;
+-00780         } else {
+-00781                 dwc_ep->pkt_cnt =
+-00782                     (dwc_ep->data_per_frame *
+-00783                      (dwc_ep->buf_proc_intrvl / dwc_ep->bInterval)
+-00784                      - 1 + dwc_ep->maxpacket) / dwc_ep->maxpacket;
+-00785         }
+-00786 
+-00787         if (core_if->dma_desc_enable) {
+-00788                 dwc_ep->desc_cnt =
+-00789                     dwc_ep->buf_proc_intrvl * dwc_ep->pkt_per_frm /
+-00790                     dwc_ep->bInterval;
+-00791         }
+-00792 
+-00793         if (atomic_alloc) {
+-00794                 dwc_ep->pkt_info =
+-00795                     DWC_ALLOC_ATOMIC(sizeof(iso_pkt_info_t) * dwc_ep->pkt_cnt);
+-00796         } else {
+-00797                 dwc_ep->pkt_info =
+-00798                     DWC_ALLOC(sizeof(iso_pkt_info_t) * dwc_ep->pkt_cnt);
+-00799         }
+-00800         if (!dwc_ep->pkt_info) {
+-00801                 DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
+-00802                 return -DWC_E_NO_MEMORY;
+-00803         }
+-00804         if (core_if->pti_enh_enable) {
+-00805                 dwc_memset(dwc_ep->pkt_info, 0,
+-00806                            sizeof(iso_pkt_info_t) * dwc_ep->pkt_cnt);
+-00807         }
+-00808 
+-00809         dwc_ep->cur_pkt = 0;
+-00810         ep->iso_req_handle = req_handle;
+-00811 
+-00812         DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
+-00813         dwc_otg_iso_ep_start_transfer(core_if, dwc_ep);
+-00814         return 0;
+-00815 }
+-00816 
+-00817 int dwc_otg_pcd_iso_ep_stop(dwc_otg_pcd_t * pcd, void *ep_handle,
+-00818                             void *req_handle)
+-00819 {
+-00820         dwc_irqflags_t flags = 0;
+-00821         dwc_otg_pcd_ep_t *ep;
+-00822         dwc_ep_t *dwc_ep;
+-00823 
+-00824         ep = get_ep_from_handle(pcd, ep_handle);
+-00825         if (!ep || !ep->desc || ep->dwc_ep.num == 0) {
+-00826                 DWC_WARN("bad ep\n");
+-00827                 return -DWC_E_INVALID;
+-00828         }
+-00829         dwc_ep = &ep->dwc_ep;
+-00830 
+-00831         dwc_otg_iso_ep_stop_transfer(GET_CORE_IF(pcd), dwc_ep);
+-00832 
+-00833         DWC_FREE(dwc_ep->pkt_info);
+-00834         DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
+-00835         if (ep->iso_req_handle != req_handle) {
+-00836                 DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
+-00837                 return -DWC_E_INVALID;
+-00838         }
+-00839 
+-00840         DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
+-00841 
+-00842         ep->iso_req_handle = 0;
+-00843         return 0;
+-00844 }
+-00845 
+-00853 void dwc_otg_iso_buffer_done(dwc_otg_pcd_t * pcd, dwc_otg_pcd_ep_t * ep,
+-00854                              void *req_handle)
+-00855 {
+-00856         int i;
+-00857         dwc_ep_t *dwc_ep;
+-00858 
+-00859         dwc_ep = &ep->dwc_ep;
+-00860 
+-00861         DWC_SPINUNLOCK(ep->pcd->lock);
+-00862         pcd->fops->isoc_complete(pcd, ep->priv, ep->iso_req_handle,
+-00863                                  dwc_ep->proc_buf_num ^ 0x1);
+-00864         DWC_SPINLOCK(ep->pcd->lock);
+-00865 
+-00866         for (i = 0; i < dwc_ep->pkt_cnt; ++i) {
+-00867                 dwc_ep->pkt_info[i].status = 0;
+-00868                 dwc_ep->pkt_info[i].offset = 0;
+-00869                 dwc_ep->pkt_info[i].length = 0;
+-00870         }
+-00871 }
+-00872 
+-00873 int dwc_otg_pcd_get_iso_packet_count(dwc_otg_pcd_t * pcd, void *ep_handle,
+-00874                                      void *iso_req_handle)
+-00875 {
+-00876         dwc_otg_pcd_ep_t *ep;
+-00877         dwc_ep_t *dwc_ep;
+-00878 
+-00879         ep = get_ep_from_handle(pcd, ep_handle);
+-00880         if (!ep->desc || ep->dwc_ep.num == 0) {
+-00881                 DWC_WARN("bad ep\n");
+-00882                 return -DWC_E_INVALID;
+-00883         }
+-00884         dwc_ep = &ep->dwc_ep;
+-00885 
+-00886         return dwc_ep->pkt_cnt;
+-00887 }
+-00888 
+-00889 void dwc_otg_pcd_get_iso_packet_params(dwc_otg_pcd_t * pcd, void *ep_handle,
+-00890                                        void *iso_req_handle, int packet,
+-00891                                        int *status, int *actual, int *offset)
+-00892 {
+-00893         dwc_otg_pcd_ep_t *ep;
+-00894         dwc_ep_t *dwc_ep;
+-00895 
+-00896         ep = get_ep_from_handle(pcd, ep_handle);
+-00897         if (!ep)
+-00898                 DWC_WARN("bad ep\n");
+-00899 
+-00900         dwc_ep = &ep->dwc_ep;
+-00901 
+-00902         *status = dwc_ep->pkt_info[packet].status;
+-00903         *actual = dwc_ep->pkt_info[packet].length;
+-00904         *offset = dwc_ep->pkt_info[packet].offset;
+-00905 }
+-00906 
+-00907 #endif /* DWC_EN_ISOC */
+-00908 
+-00909 static void dwc_otg_pcd_init_ep(dwc_otg_pcd_t * pcd, dwc_otg_pcd_ep_t * pcd_ep,
+-00910                                 uint32_t is_in, uint32_t ep_num)
+-00911 {
+-00912         /* Init EP structure */
+-00913         pcd_ep->desc = 0;
+-00914         pcd_ep->pcd = pcd;
+-00915         pcd_ep->stopped = 1;
+-00916         pcd_ep->queue_sof = 0;
+-00917 
+-00918         /* Init DWC ep structure */
+-00919         pcd_ep->dwc_ep.is_in = is_in;
+-00920         pcd_ep->dwc_ep.num = ep_num;
+-00921         pcd_ep->dwc_ep.active = 0;
+-00922         pcd_ep->dwc_ep.tx_fifo_num = 0;
+-00923         /* Control until ep is actvated */
+-00924         pcd_ep->dwc_ep.type = DWC_OTG_EP_TYPE_CONTROL;
+-00925         pcd_ep->dwc_ep.maxpacket = MAX_PACKET_SIZE;
+-00926         pcd_ep->dwc_ep.dma_addr = 0;
+-00927         pcd_ep->dwc_ep.start_xfer_buff = 0;
+-00928         pcd_ep->dwc_ep.xfer_buff = 0;
+-00929         pcd_ep->dwc_ep.xfer_len = 0;
+-00930         pcd_ep->dwc_ep.xfer_count = 0;
+-00931         pcd_ep->dwc_ep.sent_zlp = 0;
+-00932         pcd_ep->dwc_ep.total_len = 0;
+-00933         pcd_ep->dwc_ep.desc_addr = 0;
+-00934         pcd_ep->dwc_ep.dma_desc_addr = 0;
+-00935         DWC_CIRCLEQ_INIT(&pcd_ep->queue);
+-00936 }
+-00937 
+-00941 static void dwc_otg_pcd_reinit(dwc_otg_pcd_t * pcd)
+-00942 {
+-00943         int i;
+-00944         uint32_t hwcfg1;
+-00945         dwc_otg_pcd_ep_t *ep;
+-00946         int in_ep_cntr, out_ep_cntr;
+-00947         uint32_t num_in_eps = (GET_CORE_IF(pcd))->dev_if->num_in_eps;
+-00948         uint32_t num_out_eps = (GET_CORE_IF(pcd))->dev_if->num_out_eps;
+-00949 
+-00953         ep = &pcd->ep0;
+-00954         dwc_otg_pcd_init_ep(pcd, ep, 0, 0);
+-00955 
+-00956         in_ep_cntr = 0;
+-00957         hwcfg1 = (GET_CORE_IF(pcd))->hwcfg1.d32 >> 3;
+-00958         for (i = 1; in_ep_cntr < num_in_eps; i++) {
+-00959                 if ((hwcfg1 & 0x1) == 0) {
+-00960                         dwc_otg_pcd_ep_t *ep = &pcd->in_ep[in_ep_cntr];
+-00961                         in_ep_cntr++;
+-00967                         dwc_otg_pcd_init_ep(pcd, ep, 1 /* IN */ , i);
+-00968 
+-00969                         DWC_CIRCLEQ_INIT(&ep->queue);
+-00970                 }
+-00971                 hwcfg1 >>= 2;
+-00972         }
+-00973 
+-00974         out_ep_cntr = 0;
+-00975         hwcfg1 = (GET_CORE_IF(pcd))->hwcfg1.d32 >> 2;
+-00976         for (i = 1; out_ep_cntr < num_out_eps; i++) {
+-00977                 if ((hwcfg1 & 0x1) == 0) {
+-00978                         dwc_otg_pcd_ep_t *ep = &pcd->out_ep[out_ep_cntr];
+-00979                         out_ep_cntr++;
+-00985                         dwc_otg_pcd_init_ep(pcd, ep, 0 /* OUT */ , i);
+-00986                         DWC_CIRCLEQ_INIT(&ep->queue);
+-00987                 }
+-00988                 hwcfg1 >>= 2;
+-00989         }
+-00990 
+-00991         pcd->ep0state = EP0_DISCONNECT;
+-00992         pcd->ep0.dwc_ep.maxpacket = MAX_EP0_SIZE;
+-00993         pcd->ep0.dwc_ep.type = DWC_OTG_EP_TYPE_CONTROL;
+-00994 }
+-00995 
+-01000 static void srp_timeout(void *ptr)
+-01001 {
+-01002         gotgctl_data_t gotgctl;
+-01003         dwc_otg_core_if_t *core_if = (dwc_otg_core_if_t *) ptr;
+-01004         volatile uint32_t *addr = &core_if->core_global_regs->gotgctl;
+-01005 
+-01006         gotgctl.d32 = DWC_READ_REG32(addr);
+-01007 
+-01008         core_if->srp_timer_started = 0;
+-01009         
+-01010         if (core_if->adp_enable) {
+-01011                 if (gotgctl.b.bsesvld == 0) {
+-01012                         gpwrdn_data_t gpwrdn = {.d32 = 0 };
+-01013                         DWC_PRINTF("SRP Timeout BSESSVLD = 0\n");
+-01014                         /* Power off the core */
+-01015                         if (core_if->power_down == 2) {
+-01016                                 gpwrdn.b.pwrdnswtch = 1;
+-01017                                 DWC_MODIFY_REG32(&core_if->core_global_regs->
+-01018                                         gpwrdn, gpwrdn.d32, 0);
+-01019                         }
+-01020 
+-01021                         gpwrdn.d32 = 0;
+-01022                         gpwrdn.b.pmuintsel = 1;
+-01023                         gpwrdn.b.pmuactv = 1;
+-01024                         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
+-01025                         dwc_otg_adp_probe_start(core_if);
+-01026                 } else {
+-01027                         DWC_PRINTF("SRP Timeout BSESSVLD = 1\n");
+-01028                         core_if->op_state = B_PERIPHERAL;
+-01029                         dwc_otg_core_init(core_if);
+-01030                         dwc_otg_enable_global_interrupts(core_if);
+-01031                         cil_pcd_start(core_if);
+-01032                 }
+-01033         }
+-01034 
+-01035         if ((core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS) &&
+-01036             (core_if->core_params->i2c_enable)) {
+-01037                 DWC_PRINTF("SRP Timeout\n");
+-01038 
+-01039                 if ((core_if->srp_success) && (gotgctl.b.bsesvld)) {
+-01040                         if (core_if->pcd_cb && core_if->pcd_cb->resume_wakeup) {
+-01041                                 core_if->pcd_cb->resume_wakeup(core_if->pcd_cb->p);
+-01042                         }
+-01043 
+-01044                         /* Clear Session Request */
+-01045                         gotgctl.d32 = 0;
+-01046                         gotgctl.b.sesreq = 1;
+-01047                         DWC_MODIFY_REG32(&core_if->core_global_regs->gotgctl,
+-01048                                          gotgctl.d32, 0);
+-01049 
+-01050                         core_if->srp_success = 0;
+-01051                 } else {
+-01052                         __DWC_ERROR("Device not connected/responding\n");
+-01053                         gotgctl.b.sesreq = 0;
+-01054                         DWC_WRITE_REG32(addr, gotgctl.d32);
+-01055                 }
+-01056         } else if (gotgctl.b.sesreq) {
+-01057                 DWC_PRINTF("SRP Timeout\n");
+-01058 
+-01059                 __DWC_ERROR("Device not connected/responding\n");
+-01060                 gotgctl.b.sesreq = 0;
+-01061                 DWC_WRITE_REG32(addr, gotgctl.d32);
+-01062         } else {
+-01063                 DWC_PRINTF(" SRP GOTGCTL=%0x\n", gotgctl.d32);
+-01064         }
+-01065 }
+-01066 
+-01071 extern void start_next_request(dwc_otg_pcd_ep_t * ep);
+-01072 
+-01073 static void start_xfer_tasklet_func(void *data)
+-01074 {
+-01075         dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *) data;
+-01076         dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
+-01077 
+-01078         int i;
+-01079         depctl_data_t diepctl;
+-01080 
+-01081         DWC_DEBUGPL(DBG_PCDV, "Start xfer tasklet\n");
+-01082 
+-01083         diepctl.d32 = DWC_READ_REG32(&core_if->dev_if->in_ep_regs[0]->diepctl);
+-01084 
+-01085         if (pcd->ep0.queue_sof) {
+-01086                 pcd->ep0.queue_sof = 0;
+-01087                 start_next_request(&pcd->ep0);
+-01088                 // break;
+-01089         }
+-01090 
+-01091         for (i = 0; i < core_if->dev_if->num_in_eps; i++) {
+-01092                 depctl_data_t diepctl;
+-01093                 diepctl.d32 =
+-01094                     DWC_READ_REG32(&core_if->dev_if->in_ep_regs[i]->diepctl);
+-01095 
+-01096                 if (pcd->in_ep[i].queue_sof) {
+-01097                         pcd->in_ep[i].queue_sof = 0;
+-01098                         start_next_request(&pcd->in_ep[i]);
+-01099                         // break;
+-01100                 }
+-01101         }
+-01102 
+-01103         return;
+-01104 }
+-01105 
+-01110 dwc_otg_pcd_t *dwc_otg_pcd_init(dwc_otg_core_if_t * core_if)
+-01111 {
+-01112         dwc_otg_pcd_t *pcd = NULL;
+-01113         dwc_otg_dev_if_t *dev_if;
+-01114         int i;
+-01115 
+-01116         /*
+-01117          * Allocate PCD structure
+-01118          */
+-01119         pcd = DWC_ALLOC(sizeof(dwc_otg_pcd_t));
+-01120 
+-01121         if (pcd == NULL) {
+-01122                 return NULL;
+-01123         }
+-01124 
+-01125         pcd->lock = DWC_SPINLOCK_ALLOC();
+-01126         if (!pcd->lock) {
+-01127                 DWC_ERROR("Could not allocate lock for pcd");
+-01128                 DWC_FREE(pcd);
+-01129                 return NULL;
+-01130         }
+-01131         /* Set core_if's lock pointer to hcd->lock */
+-01132         core_if->lock = pcd->lock;
+-01133         pcd->core_if = core_if;
+-01134 
+-01135         dev_if = core_if->dev_if;
+-01136         dev_if->isoc_ep = NULL;
+-01137 
+-01138         if (core_if->hwcfg4.b.ded_fifo_en) {
+-01139                 DWC_PRINTF("Dedicated Tx FIFOs mode\n");
+-01140         } else {
+-01141                 DWC_PRINTF("Shared Tx FIFO mode\n");
+-01142         }
+-01143 
+-01144         /*
+-01145          * Initialized the Core for Device mode here if there is nod ADP support. 
+-01146          * Otherwise it will be done later in dwc_otg_adp_start routine.
+-01147          */                                                                                                                                                              
+-01148         if (dwc_otg_is_device_mode(core_if) /*&& !core_if->adp_enable*/) {
+-01149                 dwc_otg_core_dev_init(core_if);
+-01150         }
+-01151 
+-01152         /*
+-01153          * Register the PCD Callbacks.
+-01154          */
+-01155         dwc_otg_cil_register_pcd_callbacks(core_if, &pcd_callbacks, pcd);
+-01156 
+-01157         /*
+-01158          * Initialize the DMA buffer for SETUP packets
+-01159          */
+-01160         if (GET_CORE_IF(pcd)->dma_enable) {
+-01161                 pcd->setup_pkt =
+-01162                     DWC_DMA_ALLOC(sizeof(*pcd->setup_pkt) * 5,
+-01163                                   &pcd->setup_pkt_dma_handle);
+-01164                 if (pcd->setup_pkt == NULL) {
+-01165                         DWC_FREE(pcd);
+-01166                         return NULL;
+-01167                 }
+-01168 
+-01169                 pcd->status_buf =
+-01170                     DWC_DMA_ALLOC(sizeof(uint16_t),
+-01171                                   &pcd->status_buf_dma_handle);
+-01172                 if (pcd->status_buf == NULL) {
+-01173                         DWC_DMA_FREE(sizeof(*pcd->setup_pkt) * 5,
+-01174                                      pcd->setup_pkt, pcd->setup_pkt_dma_handle);
+-01175                         DWC_FREE(pcd);
+-01176                         return NULL;
+-01177                 }
+-01178 
+-01179                 if (GET_CORE_IF(pcd)->dma_desc_enable) {
+-01180                         dev_if->setup_desc_addr[0] =
+-01181                             dwc_otg_ep_alloc_desc_chain(&dev_if->
+-01182                                                         dma_setup_desc_addr[0],
+-01183                                                         1);
+-01184                         dev_if->setup_desc_addr[1] =
+-01185                             dwc_otg_ep_alloc_desc_chain(&dev_if->
+-01186                                                         dma_setup_desc_addr[1],
+-01187                                                         1);
+-01188                         dev_if->in_desc_addr =
+-01189                             dwc_otg_ep_alloc_desc_chain(&dev_if->
+-01190                                                         dma_in_desc_addr, 1);
+-01191                         dev_if->out_desc_addr =
+-01192                             dwc_otg_ep_alloc_desc_chain(&dev_if->
+-01193                                                         dma_out_desc_addr, 1);
+-01194 
+-01195                         if (dev_if->setup_desc_addr[0] == 0
+-01196                             || dev_if->setup_desc_addr[1] == 0
+-01197                             || dev_if->in_desc_addr == 0
+-01198                             || dev_if->out_desc_addr == 0) {
+-01199 
+-01200                                 if (dev_if->out_desc_addr)
+-01201                                         dwc_otg_ep_free_desc_chain(dev_if->
+-01202                                                                    out_desc_addr,
+-01203                                                                    dev_if->
+-01204                                                                    dma_out_desc_addr,
+-01205                                                                    1);
+-01206                                 if (dev_if->in_desc_addr)
+-01207                                         dwc_otg_ep_free_desc_chain(dev_if->
+-01208                                                                    in_desc_addr,
+-01209                                                                    dev_if->
+-01210                                                                    dma_in_desc_addr,
+-01211                                                                    1);
+-01212                                 if (dev_if->setup_desc_addr[1])
+-01213                                         dwc_otg_ep_free_desc_chain(dev_if->
+-01214                                                                    setup_desc_addr
+-01215                                                                    [1],
+-01216                                                                    dev_if->
+-01217                                                                    dma_setup_desc_addr
+-01218                                                                    [1], 1);
+-01219                                 if (dev_if->setup_desc_addr[0])
+-01220                                         dwc_otg_ep_free_desc_chain(dev_if->
+-01221                                                                    setup_desc_addr
+-01222                                                                    [0],
+-01223                                                                    dev_if->
+-01224                                                                    dma_setup_desc_addr
+-01225                                                                    [0], 1);
+-01226 
+-01227                                 DWC_DMA_FREE(sizeof(*pcd->setup_pkt) * 5,
+-01228                                              pcd->setup_pkt,
+-01229                                              pcd->setup_pkt_dma_handle);
+-01230                                 DWC_DMA_FREE(sizeof(*pcd->status_buf),
+-01231                                              pcd->status_buf,
+-01232                                              pcd->status_buf_dma_handle);
+-01233 
+-01234                                 DWC_FREE(pcd);
+-01235 
+-01236                                 return NULL;
+-01237                         }
+-01238                 }
+-01239         } else {
+-01240                 pcd->setup_pkt = DWC_ALLOC(sizeof(*pcd->setup_pkt) * 5);
+-01241                 if (pcd->setup_pkt == NULL) {
+-01242                         DWC_FREE(pcd);
+-01243                         return NULL;
+-01244                 }
+-01245 
+-01246                 pcd->status_buf = DWC_ALLOC(sizeof(uint16_t));
+-01247                 if (pcd->status_buf == NULL) {
+-01248                         DWC_FREE(pcd->setup_pkt);
+-01249                         DWC_FREE(pcd);
+-01250                         return NULL;
+-01251                 }
+-01252         }
+-01253 
+-01254         dwc_otg_pcd_reinit(pcd);
+-01255 
+-01256         /* Allocate the cfi object for the PCD */
+-01257 #ifdef DWC_UTE_CFI
+-01258         pcd->cfi = DWC_ALLOC(sizeof(cfiobject_t));
+-01259         if (NULL == pcd->cfi)
+-01260                 goto fail;
+-01261         if (init_cfi(pcd->cfi)) {
+-01262                 CFI_INFO("%s: Failed to init the CFI object\n", __func__);
+-01263                 goto fail;
+-01264         }
+-01265 #endif
+-01266 
+-01267         /* Initialize tasklets */
+-01268         pcd->start_xfer_tasklet = DWC_TASK_ALLOC("xfer_tasklet",
+-01269                                                  start_xfer_tasklet_func, pcd);
+-01270         pcd->test_mode_tasklet = DWC_TASK_ALLOC("test_mode_tasklet",
+-01271                                                 do_test_mode, pcd);
+-01272 
+-01273         /* Initialize SRP timer */
+-01274         core_if->srp_timer = DWC_TIMER_ALLOC("SRP TIMER", srp_timeout, core_if);
+-01275         
+-01276         if (core_if->core_params->dev_out_nak) {
+-01281                 for(i = 0; i < MAX_EPS_CHANNELS; i++) {
+-01282                         pcd->core_if->ep_xfer_timer[i] =
+-01283                                 DWC_TIMER_ALLOC("ep timer", ep_xfer_timeout,
+-01284                                 &pcd->core_if->ep_xfer_info[i]);
+-01285                 }
+-01286         }
+-01287         
+-01288         return pcd;
+-01289 #ifdef DWC_UTE_CFI
+-01290 fail:
+-01291 #endif
+-01292         if (pcd->setup_pkt)
+-01293                 DWC_FREE(pcd->setup_pkt);
+-01294         if (pcd->status_buf)
+-01295                 DWC_FREE(pcd->status_buf);
+-01296 #ifdef DWC_UTE_CFI
+-01297         if (pcd->cfi)
+-01298                 DWC_FREE(pcd->cfi);
+-01299 #endif
+-01300         if (pcd)
+-01301                 DWC_FREE(pcd);
+-01302         return NULL;
+-01303 
+-01304 }
+-01305 
+-01309 void dwc_otg_pcd_remove(dwc_otg_pcd_t * pcd)
+-01310 {
+-01311         dwc_otg_dev_if_t *dev_if = GET_CORE_IF(pcd)->dev_if;
+-01312         int i;
+-01313         if (pcd->core_if->core_params->dev_out_nak) {
+-01314                 for (i = 0; i < MAX_EPS_CHANNELS; i++) {
+-01315                         DWC_TIMER_CANCEL(pcd->core_if->ep_xfer_timer[i]);
+-01316                         pcd->core_if->ep_xfer_info[i].state = 0;
+-01317                 }
+-01318         }
+-01319 
+-01320         if (GET_CORE_IF(pcd)->dma_enable) {
+-01321                 DWC_DMA_FREE(sizeof(*pcd->setup_pkt) * 5, pcd->setup_pkt,
+-01322                              pcd->setup_pkt_dma_handle);
+-01323                 DWC_DMA_FREE(sizeof(uint16_t), pcd->status_buf,
+-01324                              pcd->status_buf_dma_handle);
+-01325                 if (GET_CORE_IF(pcd)->dma_desc_enable) {
+-01326                         dwc_otg_ep_free_desc_chain(dev_if->setup_desc_addr[0],
+-01327                                                    dev_if->dma_setup_desc_addr
+-01328                                                    [0], 1);
+-01329                         dwc_otg_ep_free_desc_chain(dev_if->setup_desc_addr[1],
+-01330                                                    dev_if->dma_setup_desc_addr
+-01331                                                    [1], 1);
+-01332                         dwc_otg_ep_free_desc_chain(dev_if->in_desc_addr,
+-01333                                                    dev_if->dma_in_desc_addr, 1);
+-01334                         dwc_otg_ep_free_desc_chain(dev_if->out_desc_addr,
+-01335                                                    dev_if->dma_out_desc_addr,
+-01336                                                    1);
+-01337                 }
+-01338         } else {
+-01339                 DWC_FREE(pcd->setup_pkt);
+-01340                 DWC_FREE(pcd->status_buf);
+-01341         }
+-01342         DWC_SPINLOCK_FREE(pcd->lock);
+-01343         /* Set core_if's lock pointer to NULL */
+-01344         pcd->core_if->lock = NULL;
+-01345 
+-01346         DWC_TASK_FREE(pcd->start_xfer_tasklet);
+-01347         DWC_TASK_FREE(pcd->test_mode_tasklet);
+-01348         if (pcd->core_if->core_params->dev_out_nak) {
+-01349                 for (i = 0; i < MAX_EPS_CHANNELS; i++) {
+-01350                         if (pcd->core_if->ep_xfer_timer[i]) {
+-01351                                         DWC_TIMER_FREE(pcd->core_if->ep_xfer_timer[i]);
+-01352                         }
+-01353                 }
+-01354         }
+-01355 
+-01356 /* Release the CFI object's dynamic memory */
+-01357 #ifdef DWC_UTE_CFI
+-01358         if (pcd->cfi->ops.release) {
+-01359                 pcd->cfi->ops.release(pcd->cfi);
+-01360         }
+-01361 #endif
+-01362 
+-01363         DWC_FREE(pcd);
+-01364 }
+-01365 
+-01369 uint32_t dwc_otg_pcd_is_dualspeed(dwc_otg_pcd_t * pcd)
+-01370 {
+-01371         dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
+-01372 
+-01373         if ((core_if->core_params->speed == DWC_SPEED_PARAM_FULL) ||
+-01374             ((core_if->hwcfg2.b.hs_phy_type == 2) &&
+-01375              (core_if->hwcfg2.b.fs_phy_type == 1) &&
+-01376              (core_if->core_params->ulpi_fs_ls))) {
+-01377                 return 0;
+-01378         }
+-01379 
+-01380         return 1;
+-01381 }
+-01382 
+-01386 uint32_t dwc_otg_pcd_is_otg(dwc_otg_pcd_t * pcd)
+-01387 {
+-01388         dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
+-01389         gusbcfg_data_t usbcfg = {.d32 = 0 };
+-01390 
+-01391         usbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
+-01392         if (!usbcfg.b.srpcap || !usbcfg.b.hnpcap) {
+-01393                 return 0;
+-01394         }
+-01395 
+-01396         return 1;
+-01397 }
+-01398 
+-01403 static uint32_t assign_tx_fifo(dwc_otg_core_if_t * core_if)
+-01404 {
+-01405         uint32_t TxMsk = 1;
+-01406         int i;
+-01407 
+-01408         for (i = 0; i < core_if->hwcfg4.b.num_in_eps; ++i) {
+-01409                 if ((TxMsk & core_if->tx_msk) == 0) {
+-01410                         core_if->tx_msk |= TxMsk;
+-01411                         return i + 1;
+-01412                 }
+-01413                 TxMsk <<= 1;
+-01414         }
+-01415         return 0;
+-01416 }
+-01417 
+-01422 static uint32_t assign_perio_tx_fifo(dwc_otg_core_if_t * core_if)
+-01423 {
+-01424         uint32_t PerTxMsk = 1;
+-01425         int i;
+-01426         for (i = 0; i < core_if->hwcfg4.b.num_dev_perio_in_ep; ++i) {
+-01427                 if ((PerTxMsk & core_if->p_tx_msk) == 0) {
+-01428                         core_if->p_tx_msk |= PerTxMsk;
+-01429                         return i + 1;
+-01430                 }
+-01431                 PerTxMsk <<= 1;
+-01432         }
+-01433         return 0;
+-01434 }
+-01435 
+-01440 static void release_perio_tx_fifo(dwc_otg_core_if_t * core_if,
+-01441                                   uint32_t fifo_num)
+-01442 {
+-01443         core_if->p_tx_msk =
+-01444             (core_if->p_tx_msk & (1 << (fifo_num - 1))) ^ core_if->p_tx_msk;
+-01445 }
+-01446 
+-01451 static void release_tx_fifo(dwc_otg_core_if_t * core_if, uint32_t fifo_num)
+-01452 {
+-01453         core_if->tx_msk =
+-01454             (core_if->tx_msk & (1 << (fifo_num - 1))) ^ core_if->tx_msk;
+-01455 }
+-01456 
+-01461 int dwc_otg_pcd_ep_enable(dwc_otg_pcd_t * pcd,
+-01462                           const uint8_t * ep_desc, void *usb_ep)
+-01463 {
+-01464         int num, dir;
+-01465         dwc_otg_pcd_ep_t *ep = NULL;
+-01466         const usb_endpoint_descriptor_t *desc;
+-01467         dwc_irqflags_t flags;
+-01468         fifosize_data_t dptxfsiz = {.d32 = 0 };
+-01469         gdfifocfg_data_t gdfifocfg = {.d32 = 0 };
+-01470         gdfifocfg_data_t gdfifocfgbase = {.d32 = 0 };
+-01471         int retval = 0;
+-01472         int i, epcount;
+-01473 
+-01474         desc = (const usb_endpoint_descriptor_t *)ep_desc;
+-01475 
+-01476         if (!desc) {
+-01477                 pcd->ep0.priv = usb_ep;
+-01478                 ep = &pcd->ep0;
+-01479                 retval = -DWC_E_INVALID;
+-01480                 goto out;
+-01481         }
+-01482 
+-01483         num = UE_GET_ADDR(desc->bEndpointAddress);
+-01484         dir = UE_GET_DIR(desc->bEndpointAddress);
+-01485 
+-01486         if (!desc->wMaxPacketSize) {
+-01487                 DWC_WARN("bad maxpacketsize\n");
+-01488                 retval = -DWC_E_INVALID;
+-01489                 goto out;
+-01490         }
+-01491 
+-01492         if (dir == UE_DIR_IN) {
+-01493                 epcount = pcd->core_if->dev_if->num_in_eps;
+-01494                 for (i = 0; i < epcount; i++) {
+-01495                         if (num == pcd->in_ep[i].dwc_ep.num) {
+-01496                                 ep = &pcd->in_ep[i];
+-01497                                 break;
+-01498                         }
+-01499                 }
+-01500         } else {
+-01501                 epcount = pcd->core_if->dev_if->num_out_eps;
+-01502                 for (i = 0; i < epcount; i++) {
+-01503                         if (num == pcd->out_ep[i].dwc_ep.num) {
+-01504                                 ep = &pcd->out_ep[i];
+-01505                                 break;
+-01506                         }
+-01507                 }
+-01508         }
+-01509 
+-01510         if (!ep) {
+-01511                 DWC_WARN("bad address\n");
+-01512                 retval = -DWC_E_INVALID;
+-01513                 goto out;
+-01514         }
+-01515 
+-01516         DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
+-01517 
+-01518         ep->desc = desc;
+-01519         ep->priv = usb_ep;
+-01520 
+-01521         /*
+-01522          * Activate the EP
+-01523          */
+-01524         ep->stopped = 0;
+-01525 
+-01526         ep->dwc_ep.is_in = (dir == UE_DIR_IN);
+-01527         ep->dwc_ep.maxpacket = UGETW(desc->wMaxPacketSize);
+-01528 
+-01529         ep->dwc_ep.type = desc->bmAttributes & UE_XFERTYPE;
+-01530 
+-01531         if (ep->dwc_ep.is_in) {
+-01532                 if (!GET_CORE_IF(pcd)->en_multiple_tx_fifo) {
+-01533                         ep->dwc_ep.tx_fifo_num = 0;
+-01534 
+-01535                         if (ep->dwc_ep.type == UE_ISOCHRONOUS) {
+-01536                                 /*
+-01537                                  * if ISOC EP then assign a Periodic Tx FIFO.
+-01538                                  */
+-01539                                 ep->dwc_ep.tx_fifo_num =
+-01540                                     assign_perio_tx_fifo(GET_CORE_IF(pcd));
+-01541                         }
+-01542                 } else {
+-01543                         /*
+-01544                          * if Dedicated FIFOs mode is on then assign a Tx FIFO.
+-01545                          */
+-01546                         ep->dwc_ep.tx_fifo_num =
+-01547                             assign_tx_fifo(GET_CORE_IF(pcd));
+-01548                 }
+-01549 
+-01550                 /* Calculating EP info controller base address */
+-01551                 if (ep->dwc_ep.tx_fifo_num && GET_CORE_IF(pcd)->en_multiple_tx_fifo) {
+-01552                         gdfifocfg.d32 =
+-01553                             DWC_READ_REG32(&GET_CORE_IF(pcd)->core_global_regs->
+-01554                                            gdfifocfg);
+-01555                         gdfifocfgbase.d32 = gdfifocfg.d32 >> 16;
+-01556                         dptxfsiz.d32 =
+-01557                             (DWC_READ_REG32
+-01558                              (&GET_CORE_IF(pcd)->
+-01559                               core_global_regs->dtxfsiz[ep->dwc_ep.
+-01560                                                         tx_fifo_num-1]) >> 16);
+-01561                         gdfifocfg.b.epinfobase =
+-01562                             gdfifocfgbase.d32 + dptxfsiz.d32;
+-01563                         DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->
+-01564                                         gdfifocfg, gdfifocfg.d32);
+-01565                 }
+-01566         }
+-01567         /* Set initial data PID. */
+-01568         if (ep->dwc_ep.type == UE_BULK) {
+-01569                 ep->dwc_ep.data_pid_start = 0;
+-01570         }
+-01571 
+-01572         /* Alloc DMA Descriptors */
+-01573         if (GET_CORE_IF(pcd)->dma_desc_enable) {
+-01574 #ifndef DWC_UTE_PER_IO
+-01575                 if (ep->dwc_ep.type != UE_ISOCHRONOUS) {
+-01576 #endif
+-01577                         ep->dwc_ep.desc_addr =
+-01578                             dwc_otg_ep_alloc_desc_chain(&ep->
+-01579                                                         dwc_ep.dma_desc_addr,
+-01580                                                         MAX_DMA_DESC_CNT);
+-01581                         if (!ep->dwc_ep.desc_addr) {
+-01582                                 DWC_WARN("%s, can't allocate DMA descriptor\n",
+-01583                                          __func__);
+-01584                                 retval = -DWC_E_SHUTDOWN;
+-01585                                 DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
+-01586                                 goto out;
+-01587                         }
+-01588 #ifndef DWC_UTE_PER_IO
+-01589                 }
+-01590 #endif
+-01591         }
+-01592 
+-01593         DWC_DEBUGPL(DBG_PCD, "Activate %s: type=%d, mps=%d desc=%p\n",
+-01594                     (ep->dwc_ep.is_in ? "IN" : "OUT"),
+-01595                     ep->dwc_ep.type, ep->dwc_ep.maxpacket, ep->desc);
+-01596 #ifdef DWC_UTE_PER_IO
+-01597         ep->dwc_ep.xiso_bInterval = 1 << (ep->desc->bInterval - 1);
+-01598 #endif
+-01599         if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) {
+-01600                 ep->dwc_ep.bInterval = 1 << (ep->desc->bInterval - 1);
+-01601                 ep->dwc_ep.frame_num = 0xFFFFFFFF;
+-01602         }               
+-01603 
+-01604         dwc_otg_ep_activate(GET_CORE_IF(pcd), &ep->dwc_ep);
+-01605 
+-01606 #ifdef DWC_UTE_CFI
+-01607         if (pcd->cfi->ops.ep_enable) {
+-01608                 pcd->cfi->ops.ep_enable(pcd->cfi, pcd, ep);
+-01609         }
+-01610 #endif
+-01611 
+-01612         DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
+-01613 
+-01614 out:
+-01615         return retval;
+-01616 }
+-01617 
+-01622 int dwc_otg_pcd_ep_disable(dwc_otg_pcd_t * pcd, void *ep_handle)
+-01623 {
+-01624         dwc_otg_pcd_ep_t *ep;
+-01625         dwc_irqflags_t flags;
+-01626         dwc_otg_dev_dma_desc_t *desc_addr;
+-01627         dwc_dma_t dma_desc_addr;
+-01628         gdfifocfg_data_t gdfifocfgbase = {.d32 = 0 };
+-01629         gdfifocfg_data_t gdfifocfg = {.d32 = 0 };
+-01630         fifosize_data_t dptxfsiz = {.d32 = 0 };
+-01631 
+-01632         ep = get_ep_from_handle(pcd, ep_handle);
+-01633 
+-01634         if (!ep || !ep->desc) {
+-01635                 DWC_DEBUGPL(DBG_PCD, "bad ep address\n");
+-01636                 return -DWC_E_INVALID;
+-01637         }
+-01638 
+-01639         DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
+-01640 
+-01641         dwc_otg_request_nuke(ep);
+-01642 
+-01643         dwc_otg_ep_deactivate(GET_CORE_IF(pcd), &ep->dwc_ep);
+-01644         if (pcd->core_if->core_params->dev_out_nak)
+-01645         {
+-01646                 DWC_TIMER_CANCEL(pcd->core_if->ep_xfer_timer[ep->dwc_ep.num]);
+-01647                 pcd->core_if->ep_xfer_info[ep->dwc_ep.num].state = 0;
+-01648         }
+-01649         ep->desc = NULL;
+-01650         ep->stopped = 1;
+-01651 
+-01652         gdfifocfg.d32 =
+-01653             DWC_READ_REG32(&GET_CORE_IF(pcd)->core_global_regs->gdfifocfg);
+-01654         gdfifocfgbase.d32 = gdfifocfg.d32 >> 16;
+-01655 
+-01656         if (ep->dwc_ep.is_in) {
+-01657                 if (GET_CORE_IF(pcd)->en_multiple_tx_fifo) {
+-01658                         /* Flush the Tx FIFO */
+-01659                         dwc_otg_flush_tx_fifo(GET_CORE_IF(pcd), ep->dwc_ep.tx_fifo_num);
+-01660                 }
+-01661                 release_perio_tx_fifo(GET_CORE_IF(pcd), ep->dwc_ep.tx_fifo_num);
+-01662                 release_tx_fifo(GET_CORE_IF(pcd), ep->dwc_ep.tx_fifo_num);
+-01663                 if (GET_CORE_IF(pcd)->en_multiple_tx_fifo) {
+-01664                         /* Decreasing EPinfo Base Addr */
+-01665                         dptxfsiz.d32 =
+-01666                             (DWC_READ_REG32
+-01667                              (&GET_CORE_IF(pcd)->
+-01668                                 core_global_regs->dtxfsiz[ep->dwc_ep.tx_fifo_num-1]) >> 16);
+-01669                         gdfifocfg.b.epinfobase = gdfifocfgbase.d32 - dptxfsiz.d32;
+-01670                         DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gdfifocfg,
+-01671                                         gdfifocfg.d32);
+-01672                 }
+-01673         }
+-01674 
+-01675         /* Free DMA Descriptors */
+-01676         if (GET_CORE_IF(pcd)->dma_desc_enable) {
+-01677                 if (ep->dwc_ep.type != UE_ISOCHRONOUS) {
+-01678                         desc_addr = ep->dwc_ep.desc_addr;
+-01679                         dma_desc_addr = ep->dwc_ep.dma_desc_addr;
+-01680 
+-01681                         /* Cannot call dma_free_coherent() with IRQs disabled */
+-01682                         DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
+-01683                         dwc_otg_ep_free_desc_chain(desc_addr, dma_desc_addr,
+-01684                                                    MAX_DMA_DESC_CNT);
+-01685 
+-01686                         goto out_unlocked;
+-01687                 }
+-01688         }
+-01689         DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
+-01690 
+-01691 out_unlocked:
+-01692         DWC_DEBUGPL(DBG_PCD, "%d %s disabled\n", ep->dwc_ep.num,
+-01693                     ep->dwc_ep.is_in ? "IN" : "OUT");
+-01694         return 0;
+-01695 
+-01696 }
+-01697 
+-01698 /******************************************************************************/
+-01699 #ifdef DWC_UTE_PER_IO
+-01700 
+-01705 void dwc_pcd_xiso_ereq_free(dwc_otg_pcd_ep_t * ep, dwc_otg_pcd_request_t * req)
+-01706 {
+-01707         DWC_FREE(req->ext_req.per_io_frame_descs);
+-01708         DWC_FREE(req);
+-01709 }
+-01710 
+-01715 int dwc_otg_pcd_xiso_start_next_request(dwc_otg_pcd_t * pcd,
+-01716                                         dwc_otg_pcd_ep_t * ep)
+-01717 {
+-01718         int i;
+-01719         dwc_otg_pcd_request_t *req = NULL;
+-01720         dwc_ep_t *dwcep = NULL;
+-01721         struct dwc_iso_xreq_port *ereq = NULL;
+-01722         struct dwc_iso_pkt_desc_port *ddesc_iso;
+-01723         uint16_t nat;
+-01724         depctl_data_t diepctl;
+-01725 
+-01726         dwcep = &ep->dwc_ep;
+-01727 
+-01728         if (dwcep->xiso_active_xfers > 0) {
+-01729 #if 0   //Disable this to decrease s/w overhead that is crucial for Isoc transfers
+-01730                 DWC_WARN("There are currently active transfers for EP%d \
+-01731                                 (active=%d; queued=%d)", dwcep->num, dwcep->xiso_active_xfers, 
+-01732                                 dwcep->xiso_queued_xfers);
+-01733 #endif
+-01734                 return 0;
+-01735         }
+-01736 
+-01737         nat = UGETW(ep->desc->wMaxPacketSize);
+-01738         nat = (nat >> 11) & 0x03;
+-01739 
+-01740         if (!DWC_CIRCLEQ_EMPTY(&ep->queue)) {
+-01741                 req = DWC_CIRCLEQ_FIRST(&ep->queue);
+-01742                 ereq = &req->ext_req;
+-01743                 ep->stopped = 0;
+-01744 
+-01745                 /* Get the frame number */
+-01746                 dwcep->xiso_frame_num =
+-01747                     dwc_otg_get_frame_number(GET_CORE_IF(pcd));
+-01748                 DWC_DEBUG("FRM_NUM=%d", dwcep->xiso_frame_num);
+-01749 
+-01750                 ddesc_iso = ereq->per_io_frame_descs;
+-01751 
+-01752                 if (dwcep->is_in) {
+-01753                         /* Setup DMA Descriptor chain for IN Isoc request */
+-01754                         for (i = 0; i < ereq->pio_pkt_count; i++) {
+-01755                                 //if ((i % (nat + 1)) == 0)
+-01756                                 if ( i > 0 )
+-01757                                         dwcep->xiso_frame_num = (dwcep->xiso_bInterval +
+-01758                                                                                 dwcep->xiso_frame_num) & 0x3FFF;
+-01759                                 dwcep->desc_addr[i].buf =
+-01760                                     req->dma + ddesc_iso[i].offset;
+-01761                                 dwcep->desc_addr[i].status.b_iso_in.txbytes =
+-01762                                     ddesc_iso[i].length;
+-01763                                 dwcep->desc_addr[i].status.b_iso_in.framenum =
+-01764                                     dwcep->xiso_frame_num;
+-01765                                 dwcep->desc_addr[i].status.b_iso_in.bs =
+-01766                                     BS_HOST_READY;
+-01767                                 dwcep->desc_addr[i].status.b_iso_in.txsts = 0;
+-01768                                 dwcep->desc_addr[i].status.b_iso_in.sp =
+-01769                                     (ddesc_iso[i].length %
+-01770                                      dwcep->maxpacket) ? 1 : 0;
+-01771                                 dwcep->desc_addr[i].status.b_iso_in.ioc = 0;
+-01772                                 dwcep->desc_addr[i].status.b_iso_in.pid = nat + 1;
+-01773                                 dwcep->desc_addr[i].status.b_iso_in.l = 0;
+-01774 
+-01775                                 /* Process the last descriptor */
+-01776                                 if (i == ereq->pio_pkt_count - 1) {
+-01777                                         dwcep->desc_addr[i].status.b_iso_in.ioc = 1;
+-01778                                         dwcep->desc_addr[i].status.b_iso_in.l = 1;
+-01779                                 }
+-01780                         }
+-01781 
+-01782                         /* Setup and start the transfer for this endpoint */
+-01783                         dwcep->xiso_active_xfers++;
+-01784                         DWC_WRITE_REG32(&GET_CORE_IF(pcd)->dev_if->
+-01785                                         in_ep_regs[dwcep->num]->diepdma,
+-01786                                         dwcep->dma_desc_addr);
+-01787                         diepctl.d32 = 0;
+-01788                         diepctl.b.epena = 1;
+-01789                         diepctl.b.cnak = 1;
+-01790                         DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->dev_if->
+-01791                                          in_ep_regs[dwcep->num]->diepctl, 0,
+-01792                                          diepctl.d32);
+-01793                 } else {
+-01794                         /* Setup DMA Descriptor chain for OUT Isoc request */
+-01795                         for (i = 0; i < ereq->pio_pkt_count; i++) {
+-01796                                 //if ((i % (nat + 1)) == 0)
+-01797                                 dwcep->xiso_frame_num = (dwcep->xiso_bInterval + 
+-01798                                                                                 dwcep->xiso_frame_num) & 0x3FFF;
+-01799                                 dwcep->desc_addr[i].buf =
+-01800                                     req->dma + ddesc_iso[i].offset;
+-01801                                 dwcep->desc_addr[i].status.b_iso_out.rxbytes =
+-01802                                     ddesc_iso[i].length;
+-01803                                 dwcep->desc_addr[i].status.b_iso_out.framenum =
+-01804                                     dwcep->xiso_frame_num;
+-01805                                 dwcep->desc_addr[i].status.b_iso_out.bs =
+-01806                                     BS_HOST_READY;
+-01807                                 dwcep->desc_addr[i].status.b_iso_out.rxsts = 0;
+-01808                                 dwcep->desc_addr[i].status.b_iso_out.sp =
+-01809                                     (ddesc_iso[i].length %
+-01810                                      dwcep->maxpacket) ? 1 : 0;
+-01811                                 dwcep->desc_addr[i].status.b_iso_out.ioc = 0;
+-01812                                 dwcep->desc_addr[i].status.b_iso_out.pid = nat + 1;
+-01813                                 dwcep->desc_addr[i].status.b_iso_out.l = 0;
+-01814                                 
+-01815                                 /* Process the last descriptor */
+-01816                                 if (i == ereq->pio_pkt_count - 1) {
+-01817                                         dwcep->desc_addr[i].status.b_iso_out.ioc = 1;
+-01818                                         dwcep->desc_addr[i].status.b_iso_out.l = 1;
+-01819                                 }                       
+-01820                         }
+-01821                         
+-01822                         /* Setup and start the transfer for this endpoint */
+-01823                         dwcep->xiso_active_xfers++;
+-01824                         DWC_WRITE_REG32(&GET_CORE_IF(pcd)->dev_if->
+-01825                                         out_ep_regs[dwcep->num]->doepdma,
+-01826                                         dwcep->dma_desc_addr);
+-01827                         diepctl.d32 = 0;
+-01828                         diepctl.b.epena = 1;
+-01829                         diepctl.b.cnak = 1;
+-01830                         DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->dev_if->
+-01831                                          out_ep_regs[dwcep->num]->doepctl, 0,
+-01832                                          diepctl.d32);
+-01833                 }
+-01834 
+-01835         } else {
+-01836                 ep->stopped = 1;
+-01837         }
+-01838 
+-01839         return 0;
+-01840 }
+-01841 
+-01845 void complete_xiso_ep(dwc_otg_pcd_ep_t * ep)
+-01846 {
+-01847         dwc_otg_pcd_request_t *req = NULL;
+-01848         struct dwc_iso_xreq_port *ereq = NULL;
+-01849         struct dwc_iso_pkt_desc_port *ddesc_iso = NULL;
+-01850         dwc_ep_t *dwcep = NULL;
+-01851         int i;
+-01852 
+-01853         //DWC_DEBUG();
+-01854         dwcep = &ep->dwc_ep;
+-01855 
+-01856         /* Get the first pending request from the queue */
+-01857         if (!DWC_CIRCLEQ_EMPTY(&ep->queue)) {
+-01858                 req = DWC_CIRCLEQ_FIRST(&ep->queue);
+-01859                 if (!req) {
+-01860                         DWC_PRINTF("complete_ep 0x%p, req = NULL!\n", ep);
+-01861                         return;
+-01862                 }
+-01863                 dwcep->xiso_active_xfers--;
+-01864                 dwcep->xiso_queued_xfers--;
+-01865                 /* Remove this request from the queue */
+-01866                 DWC_CIRCLEQ_REMOVE_INIT(&ep->queue, req, queue_entry);
+-01867         } else {
+-01868                 DWC_PRINTF("complete_ep 0x%p, ep->queue empty!\n", ep);
+-01869                 return;
+-01870         }
+-01871 
+-01872         ep->stopped = 1;
+-01873         ereq = &req->ext_req;
+-01874         ddesc_iso = ereq->per_io_frame_descs;
+-01875 
+-01876         if (dwcep->xiso_active_xfers < 0) {
+-01877                 DWC_WARN("EP#%d (xiso_active_xfers=%d)", dwcep->num,
+-01878                          dwcep->xiso_active_xfers);
+-01879         }
+-01880 
+-01881         /* Fill the Isoc descs of portable extended req from dma descriptors */
+-01882         for (i = 0; i < ereq->pio_pkt_count; i++) {
+-01883                 if (dwcep->is_in) {     /* IN endpoints */
+-01884                         ddesc_iso[i].actual_length = ddesc_iso[i].length -
+-01885                             dwcep->desc_addr[i].status.b_iso_in.txbytes;
+-01886                         ddesc_iso[i].status =
+-01887                             dwcep->desc_addr[i].status.b_iso_in.txsts;
+-01888                 } else {        /* OUT endpoints */
+-01889                         ddesc_iso[i].actual_length = ddesc_iso[i].length -
+-01890                             dwcep->desc_addr[i].status.b_iso_out.rxbytes;
+-01891                         ddesc_iso[i].status =
+-01892                             dwcep->desc_addr[i].status.b_iso_out.rxsts;
+-01893                 }
+-01894         }
+-01895 
+-01896         DWC_SPINUNLOCK(ep->pcd->lock);
+-01897 
+-01898         /* Call the completion function in the non-portable logic */
+-01899         ep->pcd->fops->xisoc_complete(ep->pcd, ep->priv, req->priv, 0,
+-01900                                       &req->ext_req);
+-01901 
+-01902         DWC_SPINLOCK(ep->pcd->lock);
+-01903 
+-01904         /* Free the request - specific freeing needed for extended request object */
+-01905         dwc_pcd_xiso_ereq_free(ep, req);
+-01906 
+-01907         /* Start the next request */
+-01908         dwc_otg_pcd_xiso_start_next_request(ep->pcd, ep);
+-01909 
+-01910         return;
+-01911 }
+-01912 
+-01917 static int dwc_otg_pcd_xiso_create_pkt_descs(dwc_otg_pcd_request_t * req,
+-01918                                              void *ereq_nonport,
+-01919                                              int atomic_alloc)
+-01920 {
+-01921         struct dwc_iso_xreq_port *ereq = NULL;
+-01922         struct dwc_iso_xreq_port *req_mapped = NULL;
+-01923         struct dwc_iso_pkt_desc_port *ipds = NULL;      /* To be created in this function */
+-01924         uint32_t pkt_count;
+-01925         int i;
+-01926 
+-01927         ereq = &req->ext_req;
+-01928         req_mapped = (struct dwc_iso_xreq_port *)ereq_nonport;
+-01929         pkt_count = req_mapped->pio_pkt_count;
+-01930 
+-01931         /* Create the isoc descs */
+-01932         if (atomic_alloc) {
+-01933                 ipds = DWC_ALLOC_ATOMIC(sizeof(*ipds) * pkt_count);
+-01934         } else {
+-01935                 ipds = DWC_ALLOC(sizeof(*ipds) * pkt_count);
+-01936         }
+-01937 
+-01938         if (!ipds) {
+-01939                 DWC_ERROR("Failed to allocate isoc descriptors");
+-01940                 return -DWC_E_NO_MEMORY;
+-01941         }
+-01942 
+-01943         /* Initialize the extended request fields */
+-01944         ereq->per_io_frame_descs = ipds;
+-01945         ereq->error_count = 0;
+-01946         ereq->pio_alloc_pkt_count = pkt_count;
+-01947         ereq->pio_pkt_count = pkt_count;
+-01948         ereq->tr_sub_flags = req_mapped->tr_sub_flags;
+-01949 
+-01950         /* Init the Isoc descriptors */
+-01951         for (i = 0; i < pkt_count; i++) {
+-01952                 ipds[i].length = req_mapped->per_io_frame_descs[i].length;
+-01953                 ipds[i].offset = req_mapped->per_io_frame_descs[i].offset;
+-01954                 ipds[i].status = req_mapped->per_io_frame_descs[i].status;      /* 0 */
+-01955                 ipds[i].actual_length =
+-01956                     req_mapped->per_io_frame_descs[i].actual_length;
+-01957         }
+-01958 
+-01959         return 0;
+-01960 }
+-01961 
+-01962 static void prn_ext_request(struct dwc_iso_xreq_port *ereq)
+-01963 {
+-01964         struct dwc_iso_pkt_desc_port *xfd = NULL;
+-01965         int i;
+-01966 
+-01967         DWC_DEBUG("per_io_frame_descs=%p", ereq->per_io_frame_descs);
+-01968         DWC_DEBUG("tr_sub_flags=%d", ereq->tr_sub_flags);
+-01969         DWC_DEBUG("error_count=%d", ereq->error_count);
+-01970         DWC_DEBUG("pio_alloc_pkt_count=%d", ereq->pio_alloc_pkt_count);
+-01971         DWC_DEBUG("pio_pkt_count=%d", ereq->pio_pkt_count);
+-01972         DWC_DEBUG("res=%d", ereq->res);
+-01973 
+-01974         for (i = 0; i < ereq->pio_pkt_count; i++) {
+-01975                 xfd = &ereq->per_io_frame_descs[0];
+-01976                 DWC_DEBUG("FD #%d", i);
+-01977 
+-01978                 DWC_DEBUG("xfd->actual_length=%d", xfd->actual_length);
+-01979                 DWC_DEBUG("xfd->length=%d", xfd->length);
+-01980                 DWC_DEBUG("xfd->offset=%d", xfd->offset);
+-01981                 DWC_DEBUG("xfd->status=%d", xfd->status);
+-01982         }
+-01983 }
+-01984 
+-01988 int dwc_otg_pcd_xiso_ep_queue(dwc_otg_pcd_t * pcd, void *ep_handle,
+-01989                               uint8_t * buf, dwc_dma_t dma_buf, uint32_t buflen,
+-01990                               int zero, void *req_handle, int atomic_alloc,
+-01991                               void *ereq_nonport)
+-01992 {
+-01993         dwc_otg_pcd_request_t *req = NULL;
+-01994         dwc_otg_pcd_ep_t *ep;
+-01995         dwc_irqflags_t flags;
+-01996         int res;
+-01997 
+-01998         ep = get_ep_from_handle(pcd, ep_handle);
+-01999         if (!ep) {
+-02000                 DWC_WARN("bad ep\n");
+-02001                 return -DWC_E_INVALID;
+-02002         }
+-02003 
+-02004         /* We support this extension only for DDMA mode */
+-02005         if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC)
+-02006                 if (!GET_CORE_IF(pcd)->dma_desc_enable)
+-02007                         return -DWC_E_INVALID;
+-02008 
+-02009         /* Create a dwc_otg_pcd_request_t object */
+-02010         if (atomic_alloc) {
+-02011                 req = DWC_ALLOC_ATOMIC(sizeof(*req));
+-02012         } else {
+-02013                 req = DWC_ALLOC(sizeof(*req));
+-02014         }
+-02015 
+-02016         if (!req) {
+-02017                 return -DWC_E_NO_MEMORY;
+-02018         }
+-02019 
+-02020         /* Create the Isoc descs for this request which shall be the exact match
+-02021          * of the structure sent to us from the non-portable logic */
+-02022         res =
+-02023             dwc_otg_pcd_xiso_create_pkt_descs(req, ereq_nonport, atomic_alloc);
+-02024         if (res) {
+-02025                 DWC_WARN("Failed to init the Isoc descriptors");
+-02026                 DWC_FREE(req);
+-02027                 return res;
+-02028         }
+-02029 
+-02030         DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
+-02031 
+-02032         DWC_CIRCLEQ_INIT_ENTRY(req, queue_entry);
+-02033         req->buf = buf;
+-02034         req->dma = dma_buf;
+-02035         req->length = buflen;
+-02036         req->sent_zlp = zero;
+-02037         req->priv = req_handle;
+-02038 
+-02039         //DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
+-02040         ep->dwc_ep.dma_addr = dma_buf;
+-02041         ep->dwc_ep.start_xfer_buff = buf;
+-02042         ep->dwc_ep.xfer_buff = buf;
+-02043         ep->dwc_ep.xfer_len = 0;
+-02044         ep->dwc_ep.xfer_count = 0;
+-02045         ep->dwc_ep.sent_zlp = 0;
+-02046         ep->dwc_ep.total_len = buflen;
+-02047 
+-02048         /* Add this request to the tail */
+-02049         DWC_CIRCLEQ_INSERT_TAIL(&ep->queue, req, queue_entry);
+-02050         ep->dwc_ep.xiso_queued_xfers++;
+-02051 
+-02052 //DWC_DEBUG("CP_0");
+-02053 //DWC_DEBUG("req->ext_req.tr_sub_flags=%d", req->ext_req.tr_sub_flags);
+-02054 //prn_ext_request((struct dwc_iso_xreq_port *) ereq_nonport);
+-02055 //prn_ext_request(&req->ext_req);
+-02056 
+-02057         //DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
+-02058 
+-02059         /* If the req->status == ASAP  then check if there is any active transfer
+-02060          * for this endpoint. If no active transfers, then get the first entry
+-02061          * from the queue and start that transfer
+-02062          */
+-02063         if (req->ext_req.tr_sub_flags == DWC_EREQ_TF_ASAP) {
+-02064                 res = dwc_otg_pcd_xiso_start_next_request(pcd, ep);
+-02065                 if (res) {
+-02066                         DWC_WARN("Failed to start the next Isoc transfer");
+-02067                         DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
+-02068                         DWC_FREE(req);
+-02069                         return res;
+-02070                 }
+-02071         }
+-02072 
+-02073         DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
+-02074         return 0;
+-02075 }
+-02076 
+-02077 #endif
+-02078 /* END ifdef DWC_UTE_PER_IO ***************************************************/
+-02079 int dwc_otg_pcd_ep_queue(dwc_otg_pcd_t * pcd, void *ep_handle,
+-02080                          uint8_t * buf, dwc_dma_t dma_buf, uint32_t buflen,
+-02081                          int zero, void *req_handle, int atomic_alloc)
+-02082 {
+-02083         dwc_irqflags_t flags;
+-02084         dwc_otg_pcd_request_t *req;
+-02085         dwc_otg_pcd_ep_t *ep;
+-02086         uint32_t max_transfer;
+-02087 
+-02088         ep = get_ep_from_handle(pcd, ep_handle);
+-02089         if (!ep || (!ep->desc && ep->dwc_ep.num != 0)) {
+-02090                 DWC_WARN("bad ep\n");
+-02091                 return -DWC_E_INVALID;
+-02092         }
+-02093 
+-02094         if (atomic_alloc) {
+-02095                 req = DWC_ALLOC_ATOMIC(sizeof(*req));
+-02096         } else {
+-02097                 req = DWC_ALLOC(sizeof(*req));
+-02098         }
+-02099 
+-02100         if (!req) {
+-02101                 return -DWC_E_NO_MEMORY;
+-02102         }
+-02103         DWC_CIRCLEQ_INIT_ENTRY(req, queue_entry);
+-02104         if (!GET_CORE_IF(pcd)->core_params->opt) {
+-02105                 if (ep->dwc_ep.num != 0) {
+-02106                         DWC_ERROR("queue req %p, len %d buf %p\n",
+-02107                                   req_handle, buflen, buf);
+-02108                 }
+-02109         }
+-02110 
+-02111         req->buf = buf;
+-02112         req->dma = dma_buf;
+-02113         req->length = buflen;
+-02114         req->sent_zlp = zero;
+-02115         req->priv = req_handle;
+-02116         req->dw_align_buf = NULL;
+-02117         if ((dma_buf & 0x3) && GET_CORE_IF(pcd)->dma_enable
+-02118                         && !GET_CORE_IF(pcd)->dma_desc_enable)
+-02119                 req->dw_align_buf = DWC_DMA_ALLOC(buflen,
+-02120                                  &req->dw_align_buf_dma);
+-02121         DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
+-02122 
+-02123         /*
+-02124          * After adding request to the queue for IN ISOC wait for In Token Received
+-02125          * when TX FIFO is empty interrupt and for OUT ISOC wait for OUT Token 
+-02126          * Received when EP is disabled interrupt to obtain starting microframe
+-02127          * (odd/even) start transfer
+-02128          */
+-02129         if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC)
+-02130         {
+-02131                 if (req != 0) {
+-02132                         depctl_data_t depctl = {.d32 = DWC_READ_REG32(&pcd->core_if->dev_if->in_ep_regs[ep->dwc_ep.num]->diepctl)};
+-02133                         ++pcd->request_pending;
+-02134 
+-02135                         DWC_CIRCLEQ_INSERT_TAIL(&ep->queue, req, queue_entry);
+-02136                         if (ep->dwc_ep.is_in)
+-02137                         {
+-02138                                 depctl.b.cnak = 1;
+-02139                                 DWC_WRITE_REG32(&pcd->core_if->dev_if->in_ep_regs[ep->dwc_ep.num]->diepctl, depctl.d32);
+-02140                         }
+-02141                         
+-02142                         DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
+-02143                 }
+-02144                 return 0;
+-02145         }
+-02146 
+-02147         /*
+-02148          * For EP0 IN without premature status, zlp is required?
+-02149          */
+-02150         if (ep->dwc_ep.num == 0 && ep->dwc_ep.is_in) {
+-02151                 DWC_DEBUGPL(DBG_PCDV, "%d-OUT ZLP\n", ep->dwc_ep.num);
+-02152                 //_req->zero = 1;
+-02153         }
+-02154 
+-02155         /* Start the transfer */
+-02156         if (DWC_CIRCLEQ_EMPTY(&ep->queue) && !ep->stopped) {
+-02157                 /* EP0 Transfer? */
+-02158                 if (ep->dwc_ep.num == 0) {
+-02159                         switch (pcd->ep0state) {
+-02160                         case EP0_IN_DATA_PHASE:
+-02161                                 DWC_DEBUGPL(DBG_PCD,
+-02162                                             "%s ep0: EP0_IN_DATA_PHASE\n",
+-02163                                             __func__);
+-02164                                 break;
+-02165 
+-02166                         case EP0_OUT_DATA_PHASE:
+-02167                                 DWC_DEBUGPL(DBG_PCD,
+-02168                                             "%s ep0: EP0_OUT_DATA_PHASE\n",
+-02169                                             __func__);
+-02170                                 if (pcd->request_config) {
+-02171                                         /* Complete STATUS PHASE */
+-02172                                         ep->dwc_ep.is_in = 1;
+-02173                                         pcd->ep0state = EP0_IN_STATUS_PHASE;
+-02174                                 }
+-02175                                 break;
+-02176 
+-02177                         case EP0_IN_STATUS_PHASE:
+-02178                                 DWC_DEBUGPL(DBG_PCD,
+-02179                                             "%s ep0: EP0_IN_STATUS_PHASE\n",
+-02180                                             __func__);
+-02181                                 break;
+-02182 
+-02183                         default:
+-02184                                 DWC_DEBUGPL(DBG_ANY, "ep0: odd state %d\n",
+-02185                                             pcd->ep0state);
+-02186                                 DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
+-02187                                 return -DWC_E_SHUTDOWN;
+-02188                         }
+-02189 
+-02190                         ep->dwc_ep.dma_addr = dma_buf;
+-02191                         ep->dwc_ep.start_xfer_buff = buf;
+-02192                         ep->dwc_ep.xfer_buff = buf;
+-02193                         ep->dwc_ep.xfer_len = buflen;
+-02194                         ep->dwc_ep.xfer_count = 0;
+-02195                         ep->dwc_ep.sent_zlp = 0;
+-02196                         ep->dwc_ep.total_len = ep->dwc_ep.xfer_len;
+-02197 
+-02198                         if (zero) {
+-02199                                 if ((ep->dwc_ep.xfer_len %
+-02200                                      ep->dwc_ep.maxpacket == 0)
+-02201                                     && (ep->dwc_ep.xfer_len != 0)) {
+-02202                                         ep->dwc_ep.sent_zlp = 1;
+-02203                                 }
+-02204 
+-02205                         }
+-02206 
+-02207                         dwc_otg_ep0_start_transfer(GET_CORE_IF(pcd),
+-02208                                                    &ep->dwc_ep);
+-02209                 }               // non-ep0 endpoints
+-02210                 else {
+-02211 #ifdef DWC_UTE_CFI
+-02212                         if (ep->dwc_ep.buff_mode != BM_STANDARD) {
+-02213                                 /* store the request length */
+-02214                                 ep->dwc_ep.cfi_req_len = buflen;
+-02215                                 pcd->cfi->ops.build_descriptors(pcd->cfi, pcd,
+-02216                                                                 ep, req);
+-02217                         } else {
+-02218 #endif
+-02219                                 max_transfer =
+-02220                                     GET_CORE_IF(ep->pcd)->
+-02221                                     core_params->max_transfer_size;
+-02222 
+-02223                                 /* Setup and start the Transfer */
+-02224                                 if (req->dw_align_buf){
+-02225                                         if (ep->dwc_ep.is_in)
+-02226                                                 dwc_memcpy(req->dw_align_buf, buf, buflen);
+-02227                                         ep->dwc_ep.dma_addr = req->dw_align_buf_dma;
+-02228                                         ep->dwc_ep.start_xfer_buff = req->dw_align_buf;
+-02229                                         ep->dwc_ep.xfer_buff = req->dw_align_buf;
+-02230                                 } else {
+-02231                                         ep->dwc_ep.dma_addr = dma_buf;
+-02232                                         ep->dwc_ep.start_xfer_buff = buf;
+-02233                                         ep->dwc_ep.xfer_buff = buf;     
+-02234                                 }
+-02235                                 ep->dwc_ep.xfer_len = 0;
+-02236                                 ep->dwc_ep.xfer_count = 0;
+-02237                                 ep->dwc_ep.sent_zlp = 0;
+-02238                                 ep->dwc_ep.total_len = buflen;
+-02239 
+-02240                                 ep->dwc_ep.maxxfer = max_transfer;
+-02241                                 if (GET_CORE_IF(pcd)->dma_desc_enable) {
+-02242                                         uint32_t out_max_xfer =
+-02243                                             DDMA_MAX_TRANSFER_SIZE -
+-02244                                             (DDMA_MAX_TRANSFER_SIZE % 4);
+-02245                                         if (ep->dwc_ep.is_in) {
+-02246                                                 if (ep->dwc_ep.maxxfer >
+-02247                                                     DDMA_MAX_TRANSFER_SIZE) {
+-02248                                                         ep->dwc_ep.maxxfer =
+-02249                                                             DDMA_MAX_TRANSFER_SIZE;
+-02250                                                 }
+-02251                                         } else {
+-02252                                                 if (ep->dwc_ep.maxxfer >
+-02253                                                     out_max_xfer) {
+-02254                                                         ep->dwc_ep.maxxfer =
+-02255                                                             out_max_xfer;
+-02256                                                 }
+-02257                                         }
+-02258                                 }
+-02259                                 if (ep->dwc_ep.maxxfer < ep->dwc_ep.total_len) {
+-02260                                         ep->dwc_ep.maxxfer -=
+-02261                                             (ep->dwc_ep.maxxfer %
+-02262                                              ep->dwc_ep.maxpacket);
+-02263                                 }
+-02264 
+-02265                                 if (zero) {
+-02266                                         if ((ep->dwc_ep.total_len %
+-02267                                              ep->dwc_ep.maxpacket == 0)
+-02268                                             && (ep->dwc_ep.total_len != 0)) {
+-02269                                                 ep->dwc_ep.sent_zlp = 1;
+-02270                                         }
+-02271                                 }
+-02272 #ifdef DWC_UTE_CFI
+-02273                         }
+-02274 #endif
+-02275                         dwc_otg_ep_start_transfer(GET_CORE_IF(pcd),
+-02276                                                   &ep->dwc_ep);
+-02277                 }
+-02278         }
+-02279 
+-02280         if (req != 0) {
+-02281                 ++pcd->request_pending;
+-02282                 DWC_CIRCLEQ_INSERT_TAIL(&ep->queue, req, queue_entry);
+-02283                 if (ep->dwc_ep.is_in && ep->stopped
+-02284                     && !(GET_CORE_IF(pcd)->dma_enable)) {
+-02286                         diepmsk_data_t diepmsk = {.d32 = 0 };
+-02287                         diepmsk.b.intktxfemp = 1;
+-02288                         if (GET_CORE_IF(pcd)->multiproc_int_enable) {
+-02289                                 DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->dev_if->
+-02290                                                  dev_global_regs->
+-02291                                                  diepeachintmsk[ep->dwc_ep.num],
+-02292                                                  0, diepmsk.d32);
+-02293                         } else {
+-02294                                 DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->dev_if->
+-02295                                                  dev_global_regs->diepmsk, 0,
+-02296                                                  diepmsk.d32);
+-02297                         }
+-02298 
+-02299                 }
+-02300         }
+-02301         DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
+-02302 
+-02303         return 0;
+-02304 }
+-02305 
+-02306 int dwc_otg_pcd_ep_dequeue(dwc_otg_pcd_t * pcd, void *ep_handle,
+-02307                            void *req_handle)
+-02308 {
+-02309         dwc_irqflags_t flags;
+-02310         dwc_otg_pcd_request_t *req;
+-02311         dwc_otg_pcd_ep_t *ep;
+-02312 
+-02313         ep = get_ep_from_handle(pcd, ep_handle);
+-02314         if (!ep || (!ep->desc && ep->dwc_ep.num != 0)) {
+-02315                 DWC_WARN("bad argument\n");
+-02316                 return -DWC_E_INVALID;
+-02317         }
+-02318 
+-02319         DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
+-02320 
+-02321         /* make sure it's actually queued on this endpoint */
+-02322         DWC_CIRCLEQ_FOREACH(req, &ep->queue, queue_entry) {
+-02323                 if (req->priv == (void *)req_handle) {
+-02324                         break;
+-02325                 }
+-02326         }
+-02327 
+-02328         if (req->priv != (void *)req_handle) {
+-02329                 DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
+-02330                 return -DWC_E_INVALID;
+-02331         }
+-02332 
+-02333         if (!DWC_CIRCLEQ_EMPTY_ENTRY(req, queue_entry)) {
+-02334                 dwc_otg_request_done(ep, req, -DWC_E_RESTART);
+-02335         } else {
+-02336                 req = NULL;
+-02337         }
+-02338 
+-02339         DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
+-02340 
+-02341         return req ? 0 : -DWC_E_SHUTDOWN;
+-02342 
+-02343 }
+-02344 
+-02345 int dwc_otg_pcd_ep_halt(dwc_otg_pcd_t * pcd, void *ep_handle, int value)
+-02346 {
+-02347         dwc_otg_pcd_ep_t *ep;
+-02348         dwc_irqflags_t flags;
+-02349         int retval = 0;
+-02350 
+-02351         ep = get_ep_from_handle(pcd, ep_handle);
+-02352 
+-02353         if (!ep || (!ep->desc && ep != &pcd->ep0) ||
+-02354             (ep->desc && (ep->desc->bmAttributes == UE_ISOCHRONOUS))) {
+-02355                 DWC_WARN("%s, bad ep\n", __func__);
+-02356                 return -DWC_E_INVALID;
+-02357         }
+-02358 
+-02359         DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
+-02360         if (!DWC_CIRCLEQ_EMPTY(&ep->queue)) {
+-02361                 DWC_WARN("%d %s XFer In process\n", ep->dwc_ep.num,
+-02362                          ep->dwc_ep.is_in ? "IN" : "OUT");
+-02363                 retval = -DWC_E_AGAIN;
+-02364         } else if (value == 0) {
+-02365                 dwc_otg_ep_clear_stall(GET_CORE_IF(pcd), &ep->dwc_ep);
+-02366         } else if (value == 1) {
+-02367                 if (ep->dwc_ep.is_in == 1 && GET_CORE_IF(pcd)->dma_desc_enable) {
+-02368                         dtxfsts_data_t txstatus;
+-02369                         fifosize_data_t txfifosize;
+-02370 
+-02371                         txfifosize.d32 =
+-02372                             DWC_READ_REG32(&GET_CORE_IF(pcd)->core_global_regs->
+-02373                                            dtxfsiz[ep->dwc_ep.tx_fifo_num]);
+-02374                         txstatus.d32 =
+-02375                             DWC_READ_REG32(&GET_CORE_IF(pcd)->dev_if->
+-02376                                            in_ep_regs[ep->dwc_ep.num]->dtxfsts);
+-02377 
+-02378                         if (txstatus.b.txfspcavail < txfifosize.b.depth) {
+-02379                                 DWC_WARN("%s() Data In Tx Fifo\n", __func__);
+-02380                                 retval = -DWC_E_AGAIN;
+-02381                         } else {
+-02382                                 if (ep->dwc_ep.num == 0) {
+-02383                                         pcd->ep0state = EP0_STALL;
+-02384                                 }
+-02385 
+-02386                                 ep->stopped = 1;
+-02387                                 dwc_otg_ep_set_stall(GET_CORE_IF(pcd),
+-02388                                                      &ep->dwc_ep);
+-02389                         }
+-02390                 } else {
+-02391                         if (ep->dwc_ep.num == 0) {
+-02392                                 pcd->ep0state = EP0_STALL;
+-02393                         }
+-02394 
+-02395                         ep->stopped = 1;
+-02396                         dwc_otg_ep_set_stall(GET_CORE_IF(pcd), &ep->dwc_ep);
+-02397                 }
+-02398         } else if (value == 2) {
+-02399                 ep->dwc_ep.stall_clear_flag = 0;
+-02400         } else if (value == 3) {
+-02401                 ep->dwc_ep.stall_clear_flag = 1;
+-02402         }
+-02403 
+-02404         DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
+-02405 
+-02406         return retval;
+-02407 }
+-02408 
+-02412 void dwc_otg_pcd_rem_wkup_from_suspend(dwc_otg_pcd_t * pcd, int set)
+-02413 {
+-02414         dctl_data_t dctl = { 0 };
+-02415         dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
+-02416         dsts_data_t dsts;
+-02417 
+-02418         dsts.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts);
+-02419         if (!dsts.b.suspsts) {
+-02420                 DWC_WARN("Remote wakeup while is not in suspend state\n");
+-02421         }
+-02422         /* Check if DEVICE_REMOTE_WAKEUP feature enabled */
+-02423         if (pcd->remote_wakeup_enable) {
+-02424                 if (set) {
+-02425 
+-02426                         if (core_if->adp_enable) {
+-02427                                 gpwrdn_data_t gpwrdn;
+-02428 
+-02429                                 dwc_otg_adp_probe_stop(core_if);
+-02430 
+-02431                                 /* Mask SRP detected interrupt from Power Down Logic */
+-02432                                 gpwrdn.d32 = 0;
+-02433                                 gpwrdn.b.srp_det_msk = 1;
+-02434                                 DWC_MODIFY_REG32(&core_if->core_global_regs->
+-02435                                                  gpwrdn, gpwrdn.d32, 0);
+-02436 
+-02437                                 /* Disable Power Down Logic */
+-02438                                 gpwrdn.d32 = 0;
+-02439                                 gpwrdn.b.pmuactv = 1;
+-02440                                 DWC_MODIFY_REG32(&core_if->core_global_regs->
+-02441                                                  gpwrdn, gpwrdn.d32, 0);
+-02442 
+-02443                                 /*
+-02444                                  * Initialize the Core for Device mode.
+-02445                                  */
+-02446                                 core_if->op_state = B_PERIPHERAL;
+-02447                                 dwc_otg_core_init(core_if);
+-02448                                 dwc_otg_enable_global_interrupts(core_if);
+-02449                                 cil_pcd_start(core_if);
+-02450 
+-02451                                 dwc_otg_initiate_srp(core_if);
+-02452                         }
+-02453 
+-02454                         dctl.b.rmtwkupsig = 1;
+-02455                         DWC_MODIFY_REG32(&core_if->dev_if->
+-02456                                          dev_global_regs->dctl, 0, dctl.d32);
+-02457                         DWC_DEBUGPL(DBG_PCD, "Set Remote Wakeup\n");
+-02458 
+-02459                         dwc_mdelay(2);
+-02460                         DWC_MODIFY_REG32(&core_if->dev_if->
+-02461                                          dev_global_regs->dctl, dctl.d32, 0);
+-02462                         DWC_DEBUGPL(DBG_PCD, "Clear Remote Wakeup\n");
+-02463                 }
+-02464         } else {
+-02465                 DWC_DEBUGPL(DBG_PCD, "Remote Wakeup is disabled\n");
+-02466         }
+-02467 }
+-02468 
+-02469 #ifdef CONFIG_USB_DWC_OTG_LPM
+-02470 
+-02473 void dwc_otg_pcd_rem_wkup_from_sleep(dwc_otg_pcd_t * pcd, int set)
+-02474 {
+-02475         glpmcfg_data_t lpmcfg;
+-02476         dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
+-02477 
+-02478         lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
+-02479 
+-02480         /* Check if we are in L1 state */
+-02481         if (!lpmcfg.b.prt_sleep_sts) {
+-02482                 DWC_DEBUGPL(DBG_PCD, "Device is not in sleep state\n");
+-02483                 return;
+-02484         }
+-02485 
+-02486         /* Check if host allows remote wakeup */
+-02487         if (!lpmcfg.b.rem_wkup_en) {
+-02488                 DWC_DEBUGPL(DBG_PCD, "Host does not allow remote wakeup\n");
+-02489                 return;
+-02490         }
+-02491 
+-02492         /* Check if Resume OK */
+-02493         if (!lpmcfg.b.sleep_state_resumeok) {
+-02494                 DWC_DEBUGPL(DBG_PCD, "Sleep state resume is not OK\n");
+-02495                 return;
+-02496         }
+-02497 
+-02498         lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
+-02499         lpmcfg.b.en_utmi_sleep = 0;
+-02500         lpmcfg.b.hird_thres &= (~(1 << 4));
+-02501         DWC_WRITE_REG32(&core_if->core_global_regs->glpmcfg, lpmcfg.d32);
+-02502 
+-02503         if (set) {
+-02504                 dctl_data_t dctl = {.d32 = 0 };
+-02505                 dctl.b.rmtwkupsig = 1;
+-02506                 /* Set RmtWkUpSig bit to start remote wakup signaling.
+-02507                  * Hardware will automatically clear this bit.
+-02508                  */
+-02509                 DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl,
+-02510                                  0, dctl.d32);
+-02511                 DWC_DEBUGPL(DBG_PCD, "Set Remote Wakeup\n");
+-02512         }
+-02513 
+-02514 }
+-02515 #endif
+-02516 
+-02520 void dwc_otg_pcd_remote_wakeup(dwc_otg_pcd_t * pcd, int set)
+-02521 {
+-02522         dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
+-02523         dwc_irqflags_t flags;
+-02524         if (dwc_otg_is_device_mode(core_if)) {
+-02525                 DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
+-02526 #ifdef CONFIG_USB_DWC_OTG_LPM
+-02527                 if (core_if->lx_state == DWC_OTG_L1) {
+-02528                         dwc_otg_pcd_rem_wkup_from_sleep(pcd, set);
+-02529                 } else {
+-02530 #endif
+-02531                         dwc_otg_pcd_rem_wkup_from_suspend(pcd, set);
+-02532 #ifdef CONFIG_USB_DWC_OTG_LPM
+-02533                 }
+-02534 #endif
+-02535                 DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
+-02536         }
+-02537         return;
+-02538 }
+-02539 
+-02540 void dwc_otg_pcd_disconnect_us(dwc_otg_pcd_t * pcd, int no_of_usecs)
+-02541 {
+-02542         dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
+-02543         dctl_data_t dctl = { 0 };
+-02544 
+-02545         if (dwc_otg_is_device_mode(core_if)) {
+-02546                 dctl.b.sftdiscon = 1;
+-02547                 DWC_PRINTF("Soft disconnect for %d useconds\n",no_of_usecs);
+-02548                 DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, 0, dctl.d32);
+-02549                 dwc_udelay(no_of_usecs);
+-02550                 DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32,0);
+-02551                 
+-02552         } else{
+-02553                 DWC_PRINTF("NOT SUPPORTED IN HOST MODE\n");
+-02554         }
+-02555         return;
+-02556 
+-02557 }
+-02558 
+-02559 int dwc_otg_pcd_wakeup(dwc_otg_pcd_t * pcd)
+-02560 {
+-02561         dsts_data_t dsts;
+-02562         gotgctl_data_t gotgctl;
+-02563 
+-02564         /*
+-02565          * This function starts the Protocol if no session is in progress. If
+-02566          * a session is already in progress, but the device is suspended,
+-02567          * remote wakeup signaling is started.
+-02568          */
+-02569 
+-02570         /* Check if valid session */
+-02571         gotgctl.d32 =
+-02572             DWC_READ_REG32(&(GET_CORE_IF(pcd)->core_global_regs->gotgctl));
+-02573         if (gotgctl.b.bsesvld) {
+-02574                 /* Check if suspend state */
+-02575                 dsts.d32 =
+-02576                     DWC_READ_REG32(&
+-02577                                    (GET_CORE_IF(pcd)->dev_if->
+-02578                                     dev_global_regs->dsts));
+-02579                 if (dsts.b.suspsts) {
+-02580                         dwc_otg_pcd_remote_wakeup(pcd, 1);
+-02581                 }
+-02582         } else {
+-02583                 dwc_otg_pcd_initiate_srp(pcd);
+-02584         }
+-02585 
+-02586         return 0;
+-02587 
+-02588 }
+-02589 
+-02596 void dwc_otg_pcd_initiate_srp(dwc_otg_pcd_t * pcd)
+-02597 {
+-02598         dwc_irqflags_t flags;
+-02599         DWC_SPINLOCK_IRQSAVE(pcd->lock, &flags);
+-02600         dwc_otg_initiate_srp(GET_CORE_IF(pcd));
+-02601         DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags);
+-02602 }
+-02603 
+-02604 int dwc_otg_pcd_get_frame_number(dwc_otg_pcd_t * pcd)
+-02605 {
+-02606         return dwc_otg_get_frame_number(GET_CORE_IF(pcd));
+-02607 }
+-02608 
+-02609 int dwc_otg_pcd_is_lpm_enabled(dwc_otg_pcd_t * pcd)
+-02610 {
+-02611         return GET_CORE_IF(pcd)->core_params->lpm_enable;
+-02612 }
+-02613 
+-02614 uint32_t get_b_hnp_enable(dwc_otg_pcd_t * pcd)
+-02615 {
+-02616         return pcd->b_hnp_enable;
+-02617 }
+-02618 
+-02619 uint32_t get_a_hnp_support(dwc_otg_pcd_t * pcd)
+-02620 {
+-02621         return pcd->a_hnp_support;
+-02622 }
+-02623 
+-02624 uint32_t get_a_alt_hnp_support(dwc_otg_pcd_t * pcd)
+-02625 {
+-02626         return pcd->a_alt_hnp_support;
+-02627 }
+-02628 
+-02629 int dwc_otg_pcd_get_rmwkup_enable(dwc_otg_pcd_t * pcd)
+-02630 {
+-02631         return pcd->remote_wakeup_enable;
+-02632 }
+-02633 
+-02634 #endif /* DWC_HOST_ONLY */
+-
                                                                                Generated on Thu Oct 27 03:56:37 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__pcd_8c.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/dwc__otg__pcd_8c.html 2013-07-26 19:34:42.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,1502 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_pcd.c File Reference +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                dwc_otg_pcd.c File Reference

                                                                                This file implements PCD Core. More... +-

                                                                                +-#include "dwc_otg_pcd.h"
                                                                                +- +-

                                                                                +-Go to the source code of this file. +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-

                                                                                Functions

                                                                                +-dwc_otg_pcd_ep_t * get_ep_from_handle (dwc_otg_pcd_t *pcd, void *handle)
                                                                                 Choose endpoint from ep arrays using usb_ep structure.
                                                                                void dwc_otg_request_done (dwc_otg_pcd_ep_t *ep, dwc_otg_pcd_request_t *req, int32_t status)
                                                                                 This function completes a request.
                                                                                +-void dwc_otg_request_nuke (dwc_otg_pcd_ep_t *ep)
                                                                                 This function terminates all the requsts in the EP request queue.
                                                                                void dwc_otg_pcd_start (dwc_otg_pcd_t *pcd, const struct dwc_otg_pcd_function_ops *fops)
                                                                                 Call this to bind the function driver to the PCD Core.
                                                                                int32_t dwc_otg_pcd_start_cb (void *p)
                                                                                 PCD Callback function for initializing the PCD when switching to device mode.
                                                                                +-uint8_t * cfiw_ep_alloc_buffer (dwc_otg_pcd_t *pcd, void *pep, dwc_dma_t *addr, size_t buflen, int flags)
                                                                                 CFI-specific buffer allocation function for EP.
                                                                                int32_t dwc_otg_pcd_resume_cb (void *p)
                                                                                 PCD Callback function for notifying the PCD when resuming from suspend.
                                                                                int32_t dwc_otg_pcd_suspend_cb (void *p)
                                                                                 PCD Callback function for notifying the PCD device is suspended.
                                                                                int32_t dwc_otg_pcd_stop_cb (void *p)
                                                                                 PCD Callback function for stopping the PCD when switching to Host mode.
                                                                                +-dwc_otg_dev_dma_desc_t * dwc_otg_ep_alloc_desc_chain (dwc_dma_t *dma_desc_addr, uint32_t count)
                                                                                 This function allocates a DMA Descriptor chain for the Endpoint buffer to be used for a transfer to/from the specified endpoint.
                                                                                +-void dwc_otg_ep_free_desc_chain (dwc_otg_dev_dma_desc_t *desc_addr, uint32_t dma_desc_addr, uint32_t count)
                                                                                 This function frees a DMA Descriptor chain that was allocated by ep_alloc_desc.
                                                                                void dwc_otg_iso_ep_start_ddma_transfer (dwc_otg_core_if_t *core_if, dwc_ep_t *dwc_ep)
                                                                                 This function initializes a descriptor chain for Isochronous transfer.
                                                                                void dwc_otg_iso_ep_start_buf_transfer (dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
                                                                                 This function initializes a descriptor chain for Isochronous transfer.
                                                                                void dwc_otg_iso_ep_start_transfer (dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
                                                                                 This function does the setup for a data transfer for an EP and starts the transfer.
                                                                                void dwc_otg_iso_ep_stop_transfer (dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
                                                                                 This function stops transfer for an EP and resets the ep's variables.
                                                                                int dwc_otg_pcd_iso_ep_start (dwc_otg_pcd_t *pcd, void *ep_handle, uint8_t *buf0, uint8_t *buf1, dwc_dma_t dma0, dwc_dma_t dma1, int sync_frame, int dp_frame, int data_per_frame, int start_frame, int buf_proc_intrvl, void *req_handle, int atomic_alloc)
                                                                                 Start isochronous transfers on the endpoint referenced by ep_handle.
                                                                                int dwc_otg_pcd_iso_ep_stop (dwc_otg_pcd_t *pcd, void *ep_handle, void *req_handle)
                                                                                 Stop ISOC transfers on endpoint referenced by ep_handle.
                                                                                void dwc_otg_iso_buffer_done (dwc_otg_pcd_t *pcd, dwc_otg_pcd_ep_t *ep, void *req_handle)
                                                                                 This function is used for perodical data exchnage between PCD and gadget drivers.
                                                                                int dwc_otg_pcd_get_iso_packet_count (dwc_otg_pcd_t *pcd, void *ep_handle, void *iso_req_handle)
                                                                                 Get ISOC packet count.
                                                                                void dwc_otg_pcd_get_iso_packet_params (dwc_otg_pcd_t *pcd, void *ep_handle, void *iso_req_handle, int packet, int *status, int *actual, int *offset)
                                                                                 Get ISOC packet status.
                                                                                +-void dwc_otg_pcd_init_ep (dwc_otg_pcd_t *pcd, dwc_otg_pcd_ep_t *pcd_ep, uint32_t is_in, uint32_t ep_num)
                                                                                void dwc_otg_pcd_reinit (dwc_otg_pcd_t *pcd)
                                                                                 Initialize ep's.
                                                                                void srp_timeout (void *ptr)
                                                                                 This function is called when the SRP timer expires.
                                                                                +-void start_next_request (dwc_otg_pcd_ep_t *ep)
                                                                                 Tasklet.
                                                                                +-void start_xfer_tasklet_func (void *data)
                                                                                dwc_otg_pcd_t * dwc_otg_pcd_init (dwc_otg_core_if_t *core_if)
                                                                                 Call this function to get pointer on dwc_otg_pcd_t, this pointer will be used for all PCD API functions.
                                                                                void dwc_otg_pcd_remove (dwc_otg_pcd_t *pcd)
                                                                                 Frees PCD allocated by dwc_otg_pcd_init.
                                                                                +-uint32_t dwc_otg_pcd_is_dualspeed (dwc_otg_pcd_t *pcd)
                                                                                 This function returns whether device is dualspeed.
                                                                                +-uint32_t dwc_otg_pcd_is_otg (dwc_otg_pcd_t *pcd)
                                                                                 This function returns whether device is otg.
                                                                                +-uint32_t assign_tx_fifo (dwc_otg_core_if_t *core_if)
                                                                                 This function assigns periodic Tx FIFO to an periodic EP in shared Tx FIFO mode.
                                                                                +-uint32_t assign_perio_tx_fifo (dwc_otg_core_if_t *core_if)
                                                                                 This function assigns periodic Tx FIFO to an periodic EP in shared Tx FIFO mode.
                                                                                +-void release_perio_tx_fifo (dwc_otg_core_if_t *core_if, uint32_t fifo_num)
                                                                                 This function releases periodic Tx FIFO in shared Tx FIFO mode.
                                                                                +-void release_tx_fifo (dwc_otg_core_if_t *core_if, uint32_t fifo_num)
                                                                                 This function releases periodic Tx FIFO in shared Tx FIFO mode.
                                                                                int dwc_otg_pcd_ep_enable (dwc_otg_pcd_t *pcd, const uint8_t *ep_desc, void *usb_ep)
                                                                                 Enables an endpoint for use.
                                                                                int dwc_otg_pcd_ep_disable (dwc_otg_pcd_t *pcd, void *ep_handle)
                                                                                 Disable the endpoint referenced by ep_handle.
                                                                                int dwc_otg_pcd_ep_queue (dwc_otg_pcd_t *pcd, void *ep_handle, uint8_t *buf, dwc_dma_t dma_buf, uint32_t buflen, int zero, void *req_handle, int atomic_alloc)
                                                                                 Queue a data transfer request on the endpoint referenced by ep_handle.
                                                                                int dwc_otg_pcd_ep_dequeue (dwc_otg_pcd_t *pcd, void *ep_handle, void *req_handle)
                                                                                 De-queue the specified data transfer that has not yet completed.
                                                                                int dwc_otg_pcd_ep_halt (dwc_otg_pcd_t *pcd, void *ep_handle, int value)
                                                                                 Halt (STALL) an endpoint or clear it.
                                                                                +-void dwc_otg_pcd_rem_wkup_from_suspend (dwc_otg_pcd_t *pcd, int set)
                                                                                 This function initiates remote wakeup of the host from suspend state.
                                                                                +-void dwc_otg_pcd_remote_wakeup (dwc_otg_pcd_t *pcd, int set)
                                                                                 Starts remote wakeup signaling.
                                                                                +-void dwc_otg_pcd_disconnect_us (dwc_otg_pcd_t *pcd, int no_of_usecs)
                                                                                 Starts micorsecond soft disconnect.
                                                                                int dwc_otg_pcd_wakeup (dwc_otg_pcd_t *pcd)
                                                                                 This function starts the SRP Protocol if no session is in progress.
                                                                                void dwc_otg_pcd_initiate_srp (dwc_otg_pcd_t *pcd)
                                                                                 Initiate SRP.
                                                                                +-int dwc_otg_pcd_get_frame_number (dwc_otg_pcd_t *pcd)
                                                                                 This function returns current frame number.
                                                                                +-int dwc_otg_pcd_is_lpm_enabled (dwc_otg_pcd_t *pcd)
                                                                                 This function returns 1 if LPM support is enabled, and 0 otherwise.
                                                                                +-uint32_t get_b_hnp_enable (dwc_otg_pcd_t *pcd)
                                                                                 These functions allow to get hnp parameters.
                                                                                +-uint32_t get_a_hnp_support (dwc_otg_pcd_t *pcd)
                                                                                +-uint32_t get_a_alt_hnp_support (dwc_otg_pcd_t *pcd)
                                                                                +-int dwc_otg_pcd_get_rmwkup_enable (dwc_otg_pcd_t *pcd)
                                                                                 This function returns 1 if remote wakeup is allowed and 0, otherwise.

                                                                                Variables

                                                                                dwc_otg_cil_callbacks_t pcd_callbacks
                                                                                 PCD Callback structure for handling mode switching.
                                                                                +-

                                                                                Detailed Description

                                                                                +-This file implements PCD Core. +-

                                                                                +-All code in this file is portable and doesn't use any OS specific functions. PCD Core provides Interface, defined in <dwc_otg_pcd_if.h> header file, which can be used to implement OS specific PCD interface.

                                                                                +-An important function of the PCD is managing interrupts generated by the DWC_otg controller. The implementation of the DWC_otg device mode interrupt service routines is in dwc_otg_pcd_intr.c.

                                                                                +-

                                                                                Todo:
                                                                                Add Device Mode test modes (Test J mode, Test K mode, etc).

                                                                                +-Does it work when the request size is greater than DEPTSIZ transfer size

                                                                                +- +-

                                                                                +-Definition in file dwc_otg_pcd.c.

                                                                                Function Documentation

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                void dwc_otg_request_done ( dwc_otg_pcd_ep_t *  ep,
                                                                                dwc_otg_pcd_request_t *  req,
                                                                                int32_t  status
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This function completes a request. +-

                                                                                +-It call's the request call back. +-

                                                                                +-Definition at line 81 of file dwc_otg_pcd.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                void dwc_otg_pcd_start ( dwc_otg_pcd_t *  pcd,
                                                                                const struct dwc_otg_pcd_function_ops *  fops
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Call this to bind the function driver to the PCD Core. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +-
                                                                                pcd Pointer on dwc_otg_pcd_t returned by dwc_otg_pcd_init function.
                                                                                fops The Function Driver Ops data structure containing pointers to all callbacks.
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 119 of file dwc_otg_pcd.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                int32_t dwc_otg_pcd_start_cb ( void *  p  )  [static]
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-PCD Callback function for initializing the PCD when switching to device mode. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +-
                                                                                p void pointer to the dwc_otg_pcd_t
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 131 of file dwc_otg_pcd.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                int32_t dwc_otg_pcd_resume_cb ( void *  p  )  [static]
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-PCD Callback function for notifying the PCD when resuming from suspend. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +-
                                                                                p void pointer to the dwc_otg_pcd_t
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 173 of file dwc_otg_pcd.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                int32_t dwc_otg_pcd_suspend_cb ( void *  p  )  [static]
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-PCD Callback function for notifying the PCD device is suspended. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +-
                                                                                p void pointer to the dwc_otg_pcd_t
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 197 of file dwc_otg_pcd.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                int32_t dwc_otg_pcd_stop_cb ( void *  p  )  [static]
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-PCD Callback function for stopping the PCD when switching to Host mode. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +-
                                                                                p void pointer to the dwc_otg_pcd_t
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 216 of file dwc_otg_pcd.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                void dwc_otg_iso_ep_start_ddma_transfer ( dwc_otg_core_if_t *  core_if,
                                                                                dwc_ep_t *  dwc_ep
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This function initializes a descriptor chain for Isochronous transfer. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +-
                                                                                core_if Programming view of DWC_otg controller.
                                                                                dwc_ep The EP to start the transfer on.
                                                                                +-
                                                                                +-

                                                                                +-Allocate descriptors for double buffering

                                                                                +-ISO OUT EP

                                                                                +-Buffer 0 descriptors setup

                                                                                +-Buffer 1 descriptors setup

                                                                                +-Write dma_ad into DOEPDMA register

                                                                                +-ISO IN EP

                                                                                +-Buffer 0 descriptors setup

                                                                                +-Buffer 1 descriptors setup

                                                                                +-Write dma_ad into diepdma register

                                                                                +-Enable endpoint, clear nak +-

                                                                                +-Definition at line 266 of file dwc_otg_pcd.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                void dwc_otg_iso_ep_start_buf_transfer ( dwc_otg_core_if_t *  core_if,
                                                                                dwc_ep_t *  ep
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This function initializes a descriptor chain for Isochronous transfer. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +-
                                                                                core_if Programming view of DWC_otg controller.
                                                                                ep The EP to start the transfer on.
                                                                                +-
                                                                                +-

                                                                                +-Enable endpoint, clear nak +-

                                                                                +-Definition at line 540 of file dwc_otg_pcd.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                void dwc_otg_iso_ep_start_transfer ( dwc_otg_core_if_t *  core_if,
                                                                                dwc_ep_t *  ep
                                                                                )  [static]
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This function does the setup for a data transfer for an EP and starts the transfer. +-

                                                                                +-For an IN transfer, the packets will be loaded into the appropriate Tx FIFO in the ISR. For OUT transfers, the packets are unloaded from the Rx FIFO in the ISR.

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +-
                                                                                core_if Programming view of DWC_otg controller.
                                                                                ep The EP to start the transfer on.
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 623 of file dwc_otg_pcd.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                void dwc_otg_iso_ep_stop_transfer ( dwc_otg_core_if_t *  core_if,
                                                                                dwc_ep_t *  ep
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This function stops transfer for an EP and resets the ep's variables. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +-
                                                                                core_if Programming view of DWC_otg controller.
                                                                                ep The EP to start the transfer on.
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 664 of file dwc_otg_pcd.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                int dwc_otg_pcd_iso_ep_start ( dwc_otg_pcd_t *  pcd,
                                                                                void *  ep_handle,
                                                                                uint8_t *  buf0,
                                                                                uint8_t *  buf1,
                                                                                dwc_dma_t  dma0,
                                                                                dwc_dma_t  dma1,
                                                                                int  sync_frame,
                                                                                int  dp_frame,
                                                                                int  data_per_frame,
                                                                                int  start_frame,
                                                                                int  buf_proc_intrvl,
                                                                                void *  req_handle,
                                                                                int  atomic_alloc
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Start isochronous transfers on the endpoint referenced by ep_handle. +-

                                                                                +-

                                                                                Todo:
                                                                                  +-
                                                                                • pattern data support is to be implemented in the future
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 708 of file dwc_otg_pcd.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                int dwc_otg_pcd_iso_ep_stop ( dwc_otg_pcd_t *  pcd,
                                                                                void *  ep_handle,
                                                                                void *  req_handle
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Stop ISOC transfers on endpoint referenced by ep_handle. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +- +-
                                                                                pcd The PCD
                                                                                ep_handle The handle of the endpoint
                                                                                req_handle Handle of ISOC request
                                                                                +-
                                                                                +-Returns -DWC_E_INVALID if incorrect arguments are passed to the function Returns 0 on success +-

                                                                                +-Definition at line 817 of file dwc_otg_pcd.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                void dwc_otg_iso_buffer_done ( dwc_otg_pcd_t *  pcd,
                                                                                dwc_otg_pcd_ep_t *  ep,
                                                                                void *  req_handle
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This function is used for perodical data exchnage between PCD and gadget drivers. +-

                                                                                +-for Isochronous EPs

                                                                                +-

                                                                                  +-
                                                                                • Every time a sync period completes this function is called to perform data exchange between PCD and gadget
                                                                                +- +-

                                                                                +-Definition at line 853 of file dwc_otg_pcd.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                int dwc_otg_pcd_get_iso_packet_count ( dwc_otg_pcd_t *  pcd,
                                                                                void *  ep_handle,
                                                                                void *  iso_req_handle
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Get ISOC packet count. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +- +-
                                                                                pcd The PCD
                                                                                ep_handle The handle of the endpoint
                                                                                iso_req_handle 
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 873 of file dwc_otg_pcd.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                void dwc_otg_pcd_get_iso_packet_params ( dwc_otg_pcd_t *  pcd,
                                                                                void *  ep_handle,
                                                                                void *  iso_req_handle,
                                                                                int  packet,
                                                                                int *  status,
                                                                                int *  actual,
                                                                                int *  offset
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Get ISOC packet status. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +- +- +- +- +- +-
                                                                                pcd The PCD
                                                                                ep_handle The handle of the endpoint
                                                                                iso_req_handle Isochronoush request handle
                                                                                packet Number of packet
                                                                                status Out parameter for returning status
                                                                                actual Out parameter for returning actual length
                                                                                offset Out parameter for returning offset
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 889 of file dwc_otg_pcd.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                void dwc_otg_pcd_reinit ( dwc_otg_pcd_t *  pcd  )  [static]
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Initialize ep's. +-

                                                                                +-Initialize the EP0 structure.

                                                                                +-

                                                                                Todo:
                                                                                NGS: Add direction to EP, based on contents of HWCFG1. Need a copy of HWCFG1 in pcd structure? sprintf(";r

                                                                                +-NGS: Add direction to EP, based on contents of HWCFG1. Need a copy of HWCFG1 in pcd structure? sprintf(";r

                                                                                +- +-

                                                                                +-Definition at line 941 of file dwc_otg_pcd.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                void srp_timeout ( void *  ptr  )  [static]
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This function is called when the SRP timer expires. +-

                                                                                +-The SRP should complete within 6 seconds. +-

                                                                                +-Definition at line 1000 of file dwc_otg_pcd.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                dwc_otg_pcd_t* dwc_otg_pcd_init ( dwc_otg_core_if_t *  core_if  ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Call this function to get pointer on dwc_otg_pcd_t, this pointer will be used for all PCD API functions. +-

                                                                                +-Initialize xfer timeout timer. Implemented for 2.93a feature "Device DDMA OUT NAK Enhancement" +-

                                                                                +-Definition at line 1110 of file dwc_otg_pcd.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                void dwc_otg_pcd_remove ( dwc_otg_pcd_t *  pcd  ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Frees PCD allocated by dwc_otg_pcd_init. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +-
                                                                                pcd The PCD
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 1309 of file dwc_otg_pcd.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                int dwc_otg_pcd_ep_enable ( dwc_otg_pcd_t *  pcd,
                                                                                const uint8_t *  ep_desc,
                                                                                void *  usb_ep
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Enables an endpoint for use. +-

                                                                                +-This function enables an endpoint in the PCD. The endpoint is described by the ep_desc which has the same format as a USB ep descriptor. The ep_handle parameter is used to refer to the endpoint from other API functions and in callbacks. Normally this should be called after a SET_CONFIGURATION/SET_INTERFACE to configure the core for that interface.

                                                                                +-Returns -DWC_E_INVALID if invalid parameters were passed. Returns -DWC_E_SHUTDOWN if any other error ocurred. Returns 0 on success.

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +- +-
                                                                                pcd The PCD
                                                                                ep_desc Endpoint descriptor
                                                                                usb_ep Handle on endpoint, that will be used to identify endpoint.
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 1461 of file dwc_otg_pcd.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                int dwc_otg_pcd_ep_disable ( dwc_otg_pcd_t *  pcd,
                                                                                void *  ep_handle
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Disable the endpoint referenced by ep_handle. +-

                                                                                +-Returns -DWC_E_INVALID if invalid parameters were passed. Returns -DWC_E_SHUTDOWN if any other error occurred. Returns 0 on success. +-

                                                                                +-Definition at line 1622 of file dwc_otg_pcd.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                int dwc_otg_pcd_ep_queue ( dwc_otg_pcd_t *  pcd,
                                                                                void *  ep_handle,
                                                                                uint8_t *  buf,
                                                                                dwc_dma_t  dma_buf,
                                                                                uint32_t  buflen,
                                                                                int  zero,
                                                                                void *  req_handle,
                                                                                int  atomic_alloc
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Queue a data transfer request on the endpoint referenced by ep_handle. +-

                                                                                +-

                                                                                Todo:
                                                                                NGS Create a function for this.
                                                                                +- +-

                                                                                +-Definition at line 2079 of file dwc_otg_pcd.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                int dwc_otg_pcd_ep_dequeue ( dwc_otg_pcd_t *  pcd,
                                                                                void *  ep_handle,
                                                                                void *  req_handle
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-De-queue the specified data transfer that has not yet completed. +-

                                                                                +-Returns -DWC_E_INVALID if invalid parameters were passed. Returns -DWC_E_SHUTDOWN if any other error ocurred. Returns 0 on success. +-

                                                                                +-Definition at line 2306 of file dwc_otg_pcd.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                int dwc_otg_pcd_ep_halt ( dwc_otg_pcd_t *  pcd,
                                                                                void *  ep_handle,
                                                                                int  value
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Halt (STALL) an endpoint or clear it. +-

                                                                                +-Returns -DWC_E_INVALID if invalid parameters were passed. Returns -DWC_E_SHUTDOWN if any other error ocurred. Returns -DWC_E_AGAIN if the STALL cannot be sent and must be tried again later Returns 0 on success. +-

                                                                                +-Definition at line 2345 of file dwc_otg_pcd.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                int dwc_otg_pcd_wakeup ( dwc_otg_pcd_t *  pcd  ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This function starts the SRP Protocol if no session is in progress. +-

                                                                                +-If a session is already in progress, but the device is suspended, remote wakeup signaling is started. +-

                                                                                +-Definition at line 2559 of file dwc_otg_pcd.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                void dwc_otg_pcd_initiate_srp ( dwc_otg_pcd_t *  pcd  ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Initiate SRP. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +-
                                                                                pcd the pcd structure.
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 2596 of file dwc_otg_pcd.c.

                                                                                +-

                                                                                Variable Documentation

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                dwc_otg_cil_callbacks_t pcd_callbacks [static]
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Initial value:

                                                                                 {
+-        .start = dwc_otg_pcd_start_cb,
+-        .stop = dwc_otg_pcd_stop_cb,
+-        .suspend = dwc_otg_pcd_suspend_cb,
+-        .resume_wakeup = dwc_otg_pcd_resume_cb,
+-        .p = 0,                 
+-}
+-
                                                                                PCD Callback structure for handling mode switching. +-

                                                                                +- +-

                                                                                +-Definition at line 228 of file dwc_otg_pcd.c.

                                                                                +-

                                                                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__pcd_8h-source.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/dwc__otg__pcd_8h-source.html 2013-07-26 19:34:42.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,189 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_pcd.h Source File +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                dwc_otg_pcd.h

                                                                                Go to the documentation of this file.
                                                                                00001 /* ==========================================================================
+-00002  * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_pcd.h $
+-00003  * $Revision: #46 $
+-00004  * $Date: 2011/10/20 $
+-00005  * $Change: 1870124 $
+-00006  *
+-00007  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
+-00008  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
+-00009  * otherwise expressly agreed to in writing between Synopsys and you.
+-00010  *
+-00011  * The Software IS NOT an item of Licensed Software or Licensed Product under
+-00012  * any End User Software License Agreement or Agreement for Licensed Product
+-00013  * with Synopsys or any supplement thereto. You are permitted to use and
+-00014  * redistribute this Software in source and binary forms, with or without
+-00015  * modification, provided that redistributions of source code must retain this
+-00016  * notice. You may not view, use, disclose, copy or distribute this file or
+-00017  * any information contained herein except pursuant to this license grant from
+-00018  * Synopsys. If you do not agree with this notice, including the disclaimer
+-00019  * below, then you are not authorized to use the Software.
+-00020  *
+-00021  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
+-00022  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+-00023  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+-00024  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
+-00025  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+-00026  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+-00027  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+-00028  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+-00029  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+-00030  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+-00031  * DAMAGE.
+-00032  * ========================================================================== */
+-00033 #ifndef DWC_HOST_ONLY
+-00034 #if !defined(__DWC_PCD_H__)
+-00035 #define __DWC_PCD_H__
+-00036 
+-00037 #include "dwc_otg_os_dep.h"
+-00038 #include "usb.h"
+-00039 #include "dwc_otg_cil.h"
+-00040 #include "dwc_otg_pcd_if.h"
+-00041 struct cfiobject;
+-00042 
+-00059 #define DWC_DMA_ADDR_INVALID    (~(dwc_dma_t)0)
+-00060 
+-00062 #define DDMA_MAX_TRANSFER_SIZE 65535
+-00063 
+-00067 #define GET_CORE_IF( _pcd ) (_pcd->core_if)
+-00068 
+-00072 typedef enum ep0_state {
+-00073         EP0_DISCONNECT,         /* no host */
+-00074         EP0_IDLE,
+-00075         EP0_IN_DATA_PHASE,
+-00076         EP0_OUT_DATA_PHASE,
+-00077         EP0_IN_STATUS_PHASE,
+-00078         EP0_OUT_STATUS_PHASE,
+-00079         EP0_STALL,
+-00080 } ep0state_e;
+-00081 
+-00083 struct dwc_otg_pcd;
+-00084 
+-00088 typedef struct usb_iso_request dwc_otg_pcd_iso_request_t;
+-00089 
+-00090 #ifdef DWC_UTE_PER_IO
+-00091 
+-00096 struct dwc_iso_pkt_desc_port {
+-00097         uint32_t offset;
+-00098         uint32_t length;        /* expected length */
+-00099         uint32_t actual_length;
+-00100         uint32_t status;
+-00101 };
+-00102 
+-00103 struct dwc_iso_xreq_port {
+-00105         uint32_t tr_sub_flags;
+-00107 #define DWC_EREQ_TF_ASAP                0x00000002
+-00108 
+-00109 #define DWC_EREQ_TF_ENQUEUE             0x00000004
+-00110 
+-00115         uint32_t pio_pkt_count;
+-00117         uint32_t pio_alloc_pkt_count;
+-00119         uint32_t error_count;
+-00121         uint32_t res;
+-00123         struct dwc_iso_pkt_desc_port *per_io_frame_descs;
+-00124 };
+-00125 #endif
+-00126 
+-00129 typedef struct dwc_otg_pcd_request {
+-00130         void *priv;
+-00131         void *buf;
+-00132         dwc_dma_t dma;
+-00133         uint32_t length;
+-00134         uint32_t actual;
+-00135         unsigned sent_zlp:1;
+-00140      uint8_t *dw_align_buf;
+-00141      dwc_dma_t dw_align_buf_dma;
+-00142 
+-00143          DWC_CIRCLEQ_ENTRY(dwc_otg_pcd_request) queue_entry;
+-00144 #ifdef DWC_UTE_PER_IO
+-00145         struct dwc_iso_xreq_port ext_req;
+-00146         //void *priv_ereq_nport; /*  */
+-00147 #endif
+-00148 } dwc_otg_pcd_request_t;
+-00149 
+-00150 DWC_CIRCLEQ_HEAD(req_list, dwc_otg_pcd_request);
+-00151 
+-00156 typedef struct dwc_otg_pcd_ep {
+-00158         const usb_endpoint_descriptor_t *desc;
+-00159 
+-00161         struct req_list queue;
+-00162         unsigned stopped:1;
+-00163         unsigned disabling:1;
+-00164         unsigned dma:1;
+-00165         unsigned queue_sof:1;
+-00166 
+-00167 #ifdef DWC_EN_ISOC
+-00168 
+-00169         void *iso_req_handle;
+-00170 #endif                          //_EN_ISOC_
+-00171 
+-00173         dwc_ep_t dwc_ep;
+-00174 
+-00176         struct dwc_otg_pcd *pcd;
+-00177 
+-00178         void *priv;
+-00179 } dwc_otg_pcd_ep_t;
+-00180 
+-00184 struct dwc_otg_pcd {
+-00185         const struct dwc_otg_pcd_function_ops *fops;
+-00187         struct dwc_otg_device *otg_dev;
+-00189         dwc_otg_core_if_t *core_if;
+-00191         ep0state_e ep0state;
+-00193         unsigned ep0_pending:1;
+-00195         unsigned request_config:1;
+-00197         unsigned remote_wakeup_enable:1;
+-00199         unsigned b_hnp_enable:1;
+-00201         unsigned a_hnp_support:1;
+-00203         unsigned a_alt_hnp_support:1;
+-00205         unsigned request_pending;
+-00206 
+-00211         union {
+-00212                 usb_device_request_t req;
+-00213                 uint32_t d32[2];
+-00214         } *setup_pkt;
+-00215 
+-00216         dwc_dma_t setup_pkt_dma_handle;
+-00217 
+-00219         uint16_t *status_buf;
+-00220         dwc_dma_t status_buf_dma_handle;
+-00221 
+-00223         dwc_otg_pcd_ep_t ep0;
+-00224 
+-00226         dwc_otg_pcd_ep_t in_ep[MAX_EPS_CHANNELS - 1];
+-00228         dwc_otg_pcd_ep_t out_ep[MAX_EPS_CHANNELS - 1];
+-00230 //        unsigned      num_eps : 4;
+-00231         dwc_spinlock_t *lock;
+-00232 
+-00236         dwc_tasklet_t *test_mode_tasklet;
+-00237 
+-00239         dwc_tasklet_t *start_xfer_tasklet;
+-00240 
+-00242         unsigned test_mode;
+-00246 #ifdef DWC_UTE_CFI
+-00247         struct cfiobject *cfi;
+-00248 #endif
+-00249 
+-00250 };
+-00251 
+-00252 //FIXME this functions should be static, and this prototypes should be removed
+-00253 extern void dwc_otg_request_nuke(dwc_otg_pcd_ep_t * ep);
+-00254 extern void dwc_otg_request_done(dwc_otg_pcd_ep_t * ep,
+-00255                                  dwc_otg_pcd_request_t * req, int32_t status);
+-00256 
+-00257 void dwc_otg_iso_buffer_done(dwc_otg_pcd_t * pcd, dwc_otg_pcd_ep_t * ep,
+-00258                              void *req_handle);
+-00259 
+-00260 extern void do_test_mode(void *data);
+-00261 #endif
+-00262 #endif /* DWC_HOST_ONLY */
+-
                                                                                Generated on Thu Oct 27 03:56:37 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__pcd_8h.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/dwc__otg__pcd_8h.html 2013-07-26 19:34:42.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,283 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_pcd.h File Reference +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                dwc_otg_pcd.h File Reference

                                                                                This file contains the structures, constants, and interfaces for the Perpherial Contoller Driver (PCD). More... +-

                                                                                +-#include "dwc_otg_os_dep.h"
                                                                                +-#include "usb.h"
                                                                                +-#include "dwc_otg_cil.h"
                                                                                +-#include "dwc_otg_pcd_if.h"
                                                                                +- +-

                                                                                +-Go to the source code of this file. +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-

                                                                                Data Structures

                                                                                struct  dwc_otg_pcd_request
                                                                                 DWC_otg request structure. More...
                                                                                struct  dwc_otg_pcd_ep
                                                                                 PCD EP structure. More...
                                                                                struct  dwc_otg_pcd
                                                                                 DWC_otg PCD Structure. More...

                                                                                Defines

                                                                                +-#define __DWC_PCD_H__
                                                                                +-#define DWC_DMA_ADDR_INVALID   (~(dwc_dma_t)0)
                                                                                 Invalid DMA Address.
                                                                                +-#define DDMA_MAX_TRANSFER_SIZE   65535
                                                                                 Max Transfer size for any EP.
                                                                                +-#define GET_CORE_IF(_pcd)   (_pcd->core_if)
                                                                                 Get the pointer to the core_if from the pcd pointer.

                                                                                Typedefs

                                                                                +-typedef enum ep0_state ep0state_e
                                                                                 States of EP0.
                                                                                +-typedef usb_iso_request dwc_otg_pcd_iso_request_t
                                                                                 DWC_otg iso request structure.
                                                                                typedef dwc_otg_pcd_request dwc_otg_pcd_request_t
                                                                                 DWC_otg request structure.
                                                                                typedef dwc_otg_pcd_ep dwc_otg_pcd_ep_t
                                                                                 PCD EP structure.

                                                                                Enumerations

                                                                                enum  ep0_state {
                                                                                +-  EP0_DISCONNECT, +-EP0_IDLE, +-EP0_IN_DATA_PHASE, +-EP0_OUT_DATA_PHASE, +-
                                                                                +-  EP0_IN_STATUS_PHASE, +-EP0_OUT_STATUS_PHASE, +-EP0_STALL +-
                                                                                +- }
                                                                                 States of EP0.

                                                                                Functions

                                                                                +- DWC_CIRCLEQ_HEAD (req_list, dwc_otg_pcd_request)
                                                                                +-void dwc_otg_request_nuke (dwc_otg_pcd_ep_t *ep)
                                                                                 This function terminates all the requsts in the EP request queue.
                                                                                void dwc_otg_request_done (dwc_otg_pcd_ep_t *ep, dwc_otg_pcd_request_t *req, int32_t status)
                                                                                 This function completes a request.
                                                                                void dwc_otg_iso_buffer_done (dwc_otg_pcd_t *pcd, dwc_otg_pcd_ep_t *ep, void *req_handle)
                                                                                 This function is used for perodical data exchnage between PCD and gadget drivers.
                                                                                void do_test_mode (void *data)
                                                                                 This function is called when the SET_FEATURE TEST_MODE Setup packet is sent from the host.
                                                                                +-

                                                                                Detailed Description

                                                                                +-This file contains the structures, constants, and interfaces for the Perpherial Contoller Driver (PCD). +-

                                                                                +-The Peripheral Controller Driver (PCD) for Linux will implement the Gadget API, so that the existing Gadget drivers can be used. For the Mass Storage Function driver the File-backed USB Storage Gadget (FBS) driver will be used. The FBS driver supports the Control-Bulk (CB), Control-Bulk-Interrupt (CBI), and Bulk-Only transports. +-

                                                                                +-Definition in file dwc_otg_pcd.h.

                                                                                Typedef Documentation

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                typedef struct dwc_otg_pcd_request dwc_otg_pcd_request_t
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-DWC_otg request structure. +-

                                                                                +-This structure is a list of requests.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                typedef struct dwc_otg_pcd_ep dwc_otg_pcd_ep_t
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-PCD EP structure. +-

                                                                                +-This structure describes an EP, there is an array of EPs in the PCD structure.

                                                                                +-

                                                                                Function Documentation

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                void dwc_otg_request_done ( dwc_otg_pcd_ep_t *  ep,
                                                                                dwc_otg_pcd_request_t *  req,
                                                                                int32_t  status
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This function completes a request. +-

                                                                                +-It call's the request call back. +-

                                                                                +-Definition at line 81 of file dwc_otg_pcd.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                void dwc_otg_iso_buffer_done ( dwc_otg_pcd_t *  pcd,
                                                                                dwc_otg_pcd_ep_t *  ep,
                                                                                void *  req_handle
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This function is used for perodical data exchnage between PCD and gadget drivers. +-

                                                                                +-for Isochronous EPs

                                                                                +-

                                                                                  +-
                                                                                • Every time a sync period completes this function is called to perform data exchange between PCD and gadget
                                                                                +- +-

                                                                                +-Definition at line 853 of file dwc_otg_pcd.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                void do_test_mode ( void *  data  ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This function is called when the SET_FEATURE TEST_MODE Setup packet is sent from the host. +-

                                                                                +-The Device Control register is written with the Test Mode bits set to the specified Test Mode. This is done as a tasklet so that the "Status" phase of the control transfer completes before transmitting the TEST packets.

                                                                                +-

                                                                                Todo:
                                                                                This has not been tested since the tasklet struct was put into the PCD struct!
                                                                                +- +-

                                                                                +-Definition at line 1423 of file dwc_otg_pcd_intr.c.

                                                                                +-

                                                                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__pcd__if_8h-source.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/dwc__otg__pcd__if_8h-source.html 2013-07-26 19:34:42.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,178 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_pcd_if.h Source File +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                dwc_otg_pcd_if.h

                                                                                Go to the documentation of this file.
                                                                                00001 /* ==========================================================================
+-00002  * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_pcd_if.h $
+-00003  * $Revision: #11 $
+-00004  * $Date: 2011/10/26 $
+-00005  * $Change: 1873028 $
+-00006  *
+-00007  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
+-00008  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
+-00009  * otherwise expressly agreed to in writing between Synopsys and you.
+-00010  *
+-00011  * The Software IS NOT an item of Licensed Software or Licensed Product under
+-00012  * any End User Software License Agreement or Agreement for Licensed Product
+-00013  * with Synopsys or any supplement thereto. You are permitted to use and
+-00014  * redistribute this Software in source and binary forms, with or without
+-00015  * modification, provided that redistributions of source code must retain this
+-00016  * notice. You may not view, use, disclose, copy or distribute this file or
+-00017  * any information contained herein except pursuant to this license grant from
+-00018  * Synopsys. If you do not agree with this notice, including the disclaimer
+-00019  * below, then you are not authorized to use the Software.
+-00020  *
+-00021  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
+-00022  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+-00023  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+-00024  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
+-00025  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+-00026  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+-00027  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+-00028  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+-00029  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+-00030  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+-00031  * DAMAGE.
+-00032  * ========================================================================== */
+-00033 #ifndef DWC_HOST_ONLY
+-00034 
+-00035 #if !defined(__DWC_PCD_IF_H__)
+-00036 #define __DWC_PCD_IF_H__
+-00037 
+-00038 //#include "dwc_os.h"
+-00039 #include "dwc_otg_core_if.h"
+-00040 
+-00045 struct dwc_otg_pcd;
+-00046 typedef struct dwc_otg_pcd dwc_otg_pcd_t;
+-00047 
+-00049 #define MAX_EP0_SIZE    64
+-00050 
+-00051 #define MAX_PACKET_SIZE 1024
+-00052 
+-00061 typedef int (*dwc_completion_cb_t) (dwc_otg_pcd_t * pcd, void *ep_handle,
+-00062                                     void *req_handle, int32_t status,
+-00063                                     uint32_t actual);
+-00071 typedef int (*dwc_isoc_completion_cb_t) (dwc_otg_pcd_t * pcd, void *ep_handle,
+-00072                                          void *req_handle, int proc_buf_num);
+-00081 typedef int (*dwc_setup_cb_t) (dwc_otg_pcd_t * pcd, uint8_t * bytes);
+-00086 typedef int (*dwc_disconnect_cb_t) (dwc_otg_pcd_t * pcd);
+-00088 typedef int (*dwc_connect_cb_t) (dwc_otg_pcd_t * pcd, int speed);
+-00090 typedef int (*dwc_suspend_cb_t) (dwc_otg_pcd_t * pcd);
+-00093 typedef int (*dwc_sleep_cb_t) (dwc_otg_pcd_t * pcd);
+-00096 typedef int (*dwc_resume_cb_t) (dwc_otg_pcd_t * pcd);
+-00100 typedef int (*dwc_hnp_params_changed_cb_t) (dwc_otg_pcd_t * pcd);
+-00102 typedef int (*dwc_reset_cb_t) (dwc_otg_pcd_t * pcd);
+-00103 
+-00104 typedef int (*cfi_setup_cb_t) (dwc_otg_pcd_t * pcd, void *ctrl_req_bytes);
+-00105 
+-00112 typedef int (*xiso_completion_cb_t) (dwc_otg_pcd_t * pcd, void *ep_handle,
+-00113                                      void *req_handle, int32_t status,
+-00114                                      void *ereq_port);
+-00116 struct dwc_otg_pcd_function_ops {
+-00117         dwc_connect_cb_t connect;
+-00118         dwc_disconnect_cb_t disconnect;
+-00119         dwc_setup_cb_t setup;
+-00120         dwc_completion_cb_t complete;
+-00121         dwc_isoc_completion_cb_t isoc_complete;
+-00122         dwc_suspend_cb_t suspend;
+-00123         dwc_sleep_cb_t sleep;
+-00124         dwc_resume_cb_t resume;
+-00125         dwc_reset_cb_t reset;
+-00126         dwc_hnp_params_changed_cb_t hnp_changed;
+-00127         cfi_setup_cb_t cfi_setup;
+-00128 #ifdef DWC_UTE_PER_IO
+-00129         xiso_completion_cb_t xisoc_complete;
+-00130 #endif
+-00131 };
+-00142 extern dwc_otg_pcd_t *dwc_otg_pcd_init(dwc_otg_core_if_t * core_if);
+-00143 
+-00148 extern void dwc_otg_pcd_remove(dwc_otg_pcd_t * pcd);
+-00149 
+-00155 extern void dwc_otg_pcd_start(dwc_otg_pcd_t * pcd,
+-00156                               const struct dwc_otg_pcd_function_ops *fops);
+-00157 
+-00173 extern int dwc_otg_pcd_ep_enable(dwc_otg_pcd_t * pcd,
+-00174                                  const uint8_t * ep_desc, void *usb_ep);
+-00175 
+-00181 extern int dwc_otg_pcd_ep_disable(dwc_otg_pcd_t * pcd, void *ep_handle);
+-00182 
+-00201 extern int dwc_otg_pcd_ep_queue(dwc_otg_pcd_t * pcd, void *ep_handle,
+-00202                                 uint8_t * buf, dwc_dma_t dma_buf,
+-00203                                 uint32_t buflen, int zero, void *req_handle,
+-00204                                 int atomic_alloc);
+-00205 #ifdef DWC_UTE_PER_IO
+-00206 
+-00211 extern int dwc_otg_pcd_xiso_ep_queue(dwc_otg_pcd_t * pcd, void *ep_handle,
+-00212                                      uint8_t * buf, dwc_dma_t dma_buf,
+-00213                                      uint32_t buflen, int zero,
+-00214                                      void *req_handle, int atomic_alloc,
+-00215                                      void *ereq_nonport);
+-00216 
+-00217 #endif
+-00218 
+-00224 extern int dwc_otg_pcd_ep_dequeue(dwc_otg_pcd_t * pcd, void *ep_handle,
+-00225                                   void *req_handle);
+-00226 
+-00233 extern int dwc_otg_pcd_ep_halt(dwc_otg_pcd_t * pcd, void *ep_handle, int value);
+-00234 
+-00236 extern int32_t dwc_otg_pcd_handle_intr(dwc_otg_pcd_t * pcd);
+-00237 
+-00239 extern int dwc_otg_pcd_get_frame_number(dwc_otg_pcd_t * pcd);
+-00240 
+-00267 extern int dwc_otg_pcd_iso_ep_start(dwc_otg_pcd_t * pcd, void *ep_handle,
+-00268                                     uint8_t * buf0, uint8_t * buf1,
+-00269                                     dwc_dma_t dma0, dwc_dma_t dma1,
+-00270                                     int sync_frame, int dp_frame,
+-00271                                     int data_per_frame, int start_frame,
+-00272                                     int buf_proc_intrvl, void *req_handle,
+-00273                                     int atomic_alloc);
+-00274 
+-00284 int dwc_otg_pcd_iso_ep_stop(dwc_otg_pcd_t * pcd, void *ep_handle,
+-00285                             void *req_handle);
+-00286 
+-00298 extern void dwc_otg_pcd_get_iso_packet_params(dwc_otg_pcd_t * pcd,
+-00299                                               void *ep_handle,
+-00300                                               void *iso_req_handle, int packet,
+-00301                                               int *status, int *actual,
+-00302                                               int *offset);
+-00303 
+-00310 extern int dwc_otg_pcd_get_iso_packet_count(dwc_otg_pcd_t * pcd,
+-00311                                             void *ep_handle,
+-00312                                             void *iso_req_handle);
+-00313 
+-00318 extern int dwc_otg_pcd_wakeup(dwc_otg_pcd_t * pcd);
+-00319 
+-00321 extern int dwc_otg_pcd_is_lpm_enabled(dwc_otg_pcd_t * pcd);
+-00322 
+-00324 extern int dwc_otg_pcd_get_rmwkup_enable(dwc_otg_pcd_t * pcd);
+-00325 
+-00327 extern void dwc_otg_pcd_initiate_srp(dwc_otg_pcd_t * pcd);
+-00328 
+-00330 extern void dwc_otg_pcd_remote_wakeup(dwc_otg_pcd_t * pcd, int set);
+-00331 
+-00333 extern void dwc_otg_pcd_disconnect_us(dwc_otg_pcd_t * pcd, int no_of_usecs);
+-00335 extern uint32_t dwc_otg_pcd_is_dualspeed(dwc_otg_pcd_t * pcd);
+-00336 
+-00338 extern uint32_t dwc_otg_pcd_is_otg(dwc_otg_pcd_t * pcd);
+-00339 
+-00341 extern uint32_t get_b_hnp_enable(dwc_otg_pcd_t * pcd);
+-00342 extern uint32_t get_a_hnp_support(dwc_otg_pcd_t * pcd);
+-00343 extern uint32_t get_a_alt_hnp_support(dwc_otg_pcd_t * pcd);
+-00344 
+-00347 extern uint8_t *cfiw_ep_alloc_buffer(dwc_otg_pcd_t * pcd, void *pep,
+-00348                                      dwc_dma_t * addr, size_t buflen,
+-00349                                      int flags);
+-00350 
+-00351 /******************************************************************************/
+-00352 
+-00355 #endif                          /* __DWC_PCD_IF_H__ */
+-00356 
+-00357 #endif                          /* DWC_HOST_ONLY */
+-
                                                                                Generated on Thu Oct 27 03:56:37 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__pcd__if_8h.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/dwc__otg__pcd__if_8h.html 2013-07-26 19:34:42.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,1156 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_pcd_if.h File Reference +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                dwc_otg_pcd_if.h File Reference

                                                                                This file defines DWC_OTG PCD Core API. More... +-

                                                                                +-#include "dwc_otg_core_if.h"
                                                                                +- +-

                                                                                +-Go to the source code of this file. +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-

                                                                                Data Structures

                                                                                struct  dwc_otg_pcd_function_ops
                                                                                 Function Driver Ops Data Structure. More...

                                                                                Function Driver Callbacks

                                                                                typedef int(* dwc_completion_cb_t )(dwc_otg_pcd_t *pcd, void *ep_handle, void *req_handle, int32_t status, uint32_t actual)
                                                                                 This function will be called whenever a previously queued request has completed.
                                                                                typedef int(* dwc_isoc_completion_cb_t )(dwc_otg_pcd_t *pcd, void *ep_handle, void *req_handle, int proc_buf_num)
                                                                                 This function will be called whenever a previousle queued ISOC request has completed.
                                                                                typedef int(* dwc_setup_cb_t )(dwc_otg_pcd_t *pcd, uint8_t *bytes)
                                                                                 This function should handle any SETUP request that cannot be handled by the PCD Core.
                                                                                typedef int(* dwc_disconnect_cb_t )(dwc_otg_pcd_t *pcd)
                                                                                 This is called whenever the device has been disconnected.
                                                                                +-typedef int(* dwc_connect_cb_t )(dwc_otg_pcd_t *pcd, int speed)
                                                                                 This function is called when device has been connected.
                                                                                +-typedef int(* dwc_suspend_cb_t )(dwc_otg_pcd_t *pcd)
                                                                                 This function is called when device has been suspended.
                                                                                typedef int(* dwc_sleep_cb_t )(dwc_otg_pcd_t *pcd)
                                                                                 This function is called when device has received LPM tokens, i.e.
                                                                                +-typedef int(* dwc_resume_cb_t )(dwc_otg_pcd_t *pcd)
                                                                                 This function is called when device has been resumed from suspend(L2) or L1 sleep state.
                                                                                typedef int(* dwc_hnp_params_changed_cb_t )(dwc_otg_pcd_t *pcd)
                                                                                 This function is called whenever hnp params has been changed.
                                                                                +-typedef int(* dwc_reset_cb_t )(dwc_otg_pcd_t *pcd)
                                                                                 This function is called whenever USB RESET is detected.
                                                                                +-typedef int(* cfi_setup_cb_t )(dwc_otg_pcd_t *pcd, void *ctrl_req_bytes)
                                                                                typedef int(* xiso_completion_cb_t )(dwc_otg_pcd_t *pcd, void *ep_handle, void *req_handle, int32_t status, void *ereq_port)

                                                                                Function Driver Functions

                                                                                dwc_otg_pcd_t * dwc_otg_pcd_init (dwc_otg_core_if_t *core_if)
                                                                                 Call this function to get pointer on dwc_otg_pcd_t, this pointer will be used for all PCD API functions.
                                                                                void dwc_otg_pcd_remove (dwc_otg_pcd_t *pcd)
                                                                                 Frees PCD allocated by dwc_otg_pcd_init.
                                                                                void dwc_otg_pcd_start (dwc_otg_pcd_t *pcd, const struct dwc_otg_pcd_function_ops *fops)
                                                                                 Call this to bind the function driver to the PCD Core.
                                                                                int dwc_otg_pcd_ep_enable (dwc_otg_pcd_t *pcd, const uint8_t *ep_desc, void *usb_ep)
                                                                                 Enables an endpoint for use.
                                                                                int dwc_otg_pcd_ep_disable (dwc_otg_pcd_t *pcd, void *ep_handle)
                                                                                 Disable the endpoint referenced by ep_handle.
                                                                                int dwc_otg_pcd_ep_queue (dwc_otg_pcd_t *pcd, void *ep_handle, uint8_t *buf, dwc_dma_t dma_buf, uint32_t buflen, int zero, void *req_handle, int atomic_alloc)
                                                                                 Queue a data transfer request on the endpoint referenced by ep_handle.
                                                                                int dwc_otg_pcd_ep_dequeue (dwc_otg_pcd_t *pcd, void *ep_handle, void *req_handle)
                                                                                 De-queue the specified data transfer that has not yet completed.
                                                                                int dwc_otg_pcd_ep_halt (dwc_otg_pcd_t *pcd, void *ep_handle, int value)
                                                                                 Halt (STALL) an endpoint or clear it.
                                                                                int32_t dwc_otg_pcd_handle_intr (dwc_otg_pcd_t *pcd)
                                                                                 This function should be called on every hardware interrupt.
                                                                                +-int dwc_otg_pcd_get_frame_number (dwc_otg_pcd_t *pcd)
                                                                                 This function returns current frame number.
                                                                                int dwc_otg_pcd_iso_ep_start (dwc_otg_pcd_t *pcd, void *ep_handle, uint8_t *buf0, uint8_t *buf1, dwc_dma_t dma0, dwc_dma_t dma1, int sync_frame, int dp_frame, int data_per_frame, int start_frame, int buf_proc_intrvl, void *req_handle, int atomic_alloc)
                                                                                 Start isochronous transfers on the endpoint referenced by ep_handle.
                                                                                int dwc_otg_pcd_iso_ep_stop (dwc_otg_pcd_t *pcd, void *ep_handle, void *req_handle)
                                                                                 Stop ISOC transfers on endpoint referenced by ep_handle.
                                                                                void dwc_otg_pcd_get_iso_packet_params (dwc_otg_pcd_t *pcd, void *ep_handle, void *iso_req_handle, int packet, int *status, int *actual, int *offset)
                                                                                 Get ISOC packet status.
                                                                                int dwc_otg_pcd_get_iso_packet_count (dwc_otg_pcd_t *pcd, void *ep_handle, void *iso_req_handle)
                                                                                 Get ISOC packet count.
                                                                                int dwc_otg_pcd_wakeup (dwc_otg_pcd_t *pcd)
                                                                                 This function starts the SRP Protocol if no session is in progress.
                                                                                +-int dwc_otg_pcd_is_lpm_enabled (dwc_otg_pcd_t *pcd)
                                                                                 This function returns 1 if LPM support is enabled, and 0 otherwise.
                                                                                +-int dwc_otg_pcd_get_rmwkup_enable (dwc_otg_pcd_t *pcd)
                                                                                 This function returns 1 if remote wakeup is allowed and 0, otherwise.
                                                                                void dwc_otg_pcd_initiate_srp (dwc_otg_pcd_t *pcd)
                                                                                 Initiate SRP.
                                                                                +-void dwc_otg_pcd_remote_wakeup (dwc_otg_pcd_t *pcd, int set)
                                                                                 Starts remote wakeup signaling.
                                                                                +-void dwc_otg_pcd_disconnect_us (dwc_otg_pcd_t *pcd, int no_of_usecs)
                                                                                 Starts micorsecond soft disconnect.
                                                                                +-uint32_t dwc_otg_pcd_is_dualspeed (dwc_otg_pcd_t *pcd)
                                                                                 This function returns whether device is dualspeed.
                                                                                +-uint32_t dwc_otg_pcd_is_otg (dwc_otg_pcd_t *pcd)
                                                                                 This function returns whether device is otg.
                                                                                +-uint32_t get_b_hnp_enable (dwc_otg_pcd_t *pcd)
                                                                                 These functions allow to get hnp parameters.
                                                                                +-uint32_t get_a_hnp_support (dwc_otg_pcd_t *pcd)
                                                                                +-uint32_t get_a_alt_hnp_support (dwc_otg_pcd_t *pcd)
                                                                                +-uint8_t * cfiw_ep_alloc_buffer (dwc_otg_pcd_t *pcd, void *pep, dwc_dma_t *addr, size_t buflen, int flags)
                                                                                 Allocate a cfi buffer.

                                                                                Defines

                                                                                +-#define __DWC_PCD_IF_H__
                                                                                +-#define MAX_EP0_SIZE   64
                                                                                 Maxpacket size for EP0.
                                                                                +-#define MAX_PACKET_SIZE   1024
                                                                                 Maxpacket size for any EP.

                                                                                Typedefs

                                                                                +-typedef dwc_otg_pcd dwc_otg_pcd_t
                                                                                +-

                                                                                Detailed Description

                                                                                +-This file defines DWC_OTG PCD Core API. +-

                                                                                +- +-

                                                                                +-Definition in file dwc_otg_pcd_if.h.

                                                                                Typedef Documentation

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                typedef int(* dwc_completion_cb_t)(dwc_otg_pcd_t *pcd, void *ep_handle, void *req_handle, int32_t status, uint32_t actual)
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This function will be called whenever a previously queued request has completed. +-

                                                                                +-The status value will be set to -DWC_E_SHUTDOWN to indicated a failed or aborted transfer, or -DWC_E_RESTART to indicate the device was reset, or -DWC_E_TIMEOUT to indicate it timed out, or -DWC_E_INVALID to indicate invalid parameters. +-

                                                                                +-Definition at line 61 of file dwc_otg_pcd_if.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                typedef int(* dwc_isoc_completion_cb_t)(dwc_otg_pcd_t *pcd, void *ep_handle, void *req_handle, int proc_buf_num)
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This function will be called whenever a previousle queued ISOC request has completed. +-

                                                                                +-Count of ISOC packets could be read using dwc_otg_pcd_get_iso_packet_count function. The status of each ISOC packet could be read using dwc_otg_pcd_get_iso_packet_* functions. +-

                                                                                +-Definition at line 71 of file dwc_otg_pcd_if.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                typedef int(* dwc_setup_cb_t)(dwc_otg_pcd_t *pcd, uint8_t *bytes)
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This function should handle any SETUP request that cannot be handled by the PCD Core. +-

                                                                                +-This includes most GET_DESCRIPTORs, SET_CONFIGS, Any class-specific requests, etc. The function must non-blocking.

                                                                                +-Returns 0 on success. Returns -DWC_E_NOT_SUPPORTED if the request is not supported. Returns -DWC_E_INVALID if the setup request had invalid parameters or bytes. Returns -DWC_E_SHUTDOWN on any other error. +-

                                                                                +-Definition at line 81 of file dwc_otg_pcd_if.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                typedef int(* dwc_disconnect_cb_t)(dwc_otg_pcd_t *pcd)
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This is called whenever the device has been disconnected. +-

                                                                                +-The function driver should take appropriate action to clean up all pending requests in the PCD Core, remove all endpoints (except ep0), and initialize back to reset state. +-

                                                                                +-Definition at line 86 of file dwc_otg_pcd_if.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                typedef int(* dwc_sleep_cb_t)(dwc_otg_pcd_t *pcd)
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This function is called when device has received LPM tokens, i.e. +-

                                                                                +-device has been sent to sleep state. +-

                                                                                +-Definition at line 93 of file dwc_otg_pcd_if.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                typedef int(* dwc_hnp_params_changed_cb_t)(dwc_otg_pcd_t *pcd)
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This function is called whenever hnp params has been changed. +-

                                                                                +-User can call get_b_hnp_enable, get_a_hnp_support, get_a_alt_hnp_support functions to get hnp parameters. +-

                                                                                +-Definition at line 100 of file dwc_otg_pcd_if.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                typedef int(* xiso_completion_cb_t)(dwc_otg_pcd_t *pcd, void *ep_handle, void *req_handle, int32_t status, void *ereq_port)
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +-
                                                                                ep_handle Void pointer to the usb_ep structure
                                                                                ereq_port Pointer to the extended request structure created in the portable part.
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 112 of file dwc_otg_pcd_if.h.

                                                                                +-

                                                                                Function Documentation

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                dwc_otg_pcd_t* dwc_otg_pcd_init ( dwc_otg_core_if_t *  core_if  ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Call this function to get pointer on dwc_otg_pcd_t, this pointer will be used for all PCD API functions. +-

                                                                                +-Initialize xfer timeout timer. Implemented for 2.93a feature "Device DDMA OUT NAK Enhancement" +-

                                                                                +-Definition at line 1110 of file dwc_otg_pcd.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                void dwc_otg_pcd_remove ( dwc_otg_pcd_t *  pcd  ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Frees PCD allocated by dwc_otg_pcd_init. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +-
                                                                                pcd The PCD
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 1309 of file dwc_otg_pcd.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                void dwc_otg_pcd_start ( dwc_otg_pcd_t *  pcd,
                                                                                const struct dwc_otg_pcd_function_ops *  fops
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Call this to bind the function driver to the PCD Core. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +-
                                                                                pcd Pointer on dwc_otg_pcd_t returned by dwc_otg_pcd_init function.
                                                                                fops The Function Driver Ops data structure containing pointers to all callbacks.
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 119 of file dwc_otg_pcd.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                int dwc_otg_pcd_ep_enable ( dwc_otg_pcd_t *  pcd,
                                                                                const uint8_t *  ep_desc,
                                                                                void *  usb_ep
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Enables an endpoint for use. +-

                                                                                +-This function enables an endpoint in the PCD. The endpoint is described by the ep_desc which has the same format as a USB ep descriptor. The ep_handle parameter is used to refer to the endpoint from other API functions and in callbacks. Normally this should be called after a SET_CONFIGURATION/SET_INTERFACE to configure the core for that interface.

                                                                                +-Returns -DWC_E_INVALID if invalid parameters were passed. Returns -DWC_E_SHUTDOWN if any other error ocurred. Returns 0 on success.

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +- +-
                                                                                pcd The PCD
                                                                                ep_desc Endpoint descriptor
                                                                                usb_ep Handle on endpoint, that will be used to identify endpoint.
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 1461 of file dwc_otg_pcd.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                int dwc_otg_pcd_ep_disable ( dwc_otg_pcd_t *  pcd,
                                                                                void *  ep_handle
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Disable the endpoint referenced by ep_handle. +-

                                                                                +-Returns -DWC_E_INVALID if invalid parameters were passed. Returns -DWC_E_SHUTDOWN if any other error occurred. Returns 0 on success. +-

                                                                                +-Definition at line 1622 of file dwc_otg_pcd.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                int dwc_otg_pcd_ep_queue ( dwc_otg_pcd_t *  pcd,
                                                                                void *  ep_handle,
                                                                                uint8_t *  buf,
                                                                                dwc_dma_t  dma_buf,
                                                                                uint32_t  buflen,
                                                                                int  zero,
                                                                                void *  req_handle,
                                                                                int  atomic_alloc
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Queue a data transfer request on the endpoint referenced by ep_handle. +-

                                                                                +-

                                                                                Todo:
                                                                                NGS Create a function for this.
                                                                                +- +-

                                                                                +-Definition at line 2079 of file dwc_otg_pcd.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                int dwc_otg_pcd_ep_dequeue ( dwc_otg_pcd_t *  pcd,
                                                                                void *  ep_handle,
                                                                                void *  req_handle
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-De-queue the specified data transfer that has not yet completed. +-

                                                                                +-Returns -DWC_E_INVALID if invalid parameters were passed. Returns -DWC_E_SHUTDOWN if any other error ocurred. Returns 0 on success. +-

                                                                                +-Definition at line 2306 of file dwc_otg_pcd.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                int dwc_otg_pcd_ep_halt ( dwc_otg_pcd_t *  pcd,
                                                                                void *  ep_handle,
                                                                                int  value
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Halt (STALL) an endpoint or clear it. +-

                                                                                +-Returns -DWC_E_INVALID if invalid parameters were passed. Returns -DWC_E_SHUTDOWN if any other error ocurred. Returns -DWC_E_AGAIN if the STALL cannot be sent and must be tried again later Returns 0 on success. +-

                                                                                +-Definition at line 2345 of file dwc_otg_pcd.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                int32_t dwc_otg_pcd_handle_intr ( dwc_otg_pcd_t *  pcd  ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This function should be called on every hardware interrupt. +-

                                                                                +-The PCD handles the device interrupts. Many conditions can cause a device interrupt. When an interrupt occurs, the device interrupt service routine determines the cause of the interrupt and dispatches handling to the appropriate function. These interrupt handling functions are described below.

                                                                                +-All interrupt registers are processed from LSB to MSB. +-

                                                                                +-Definition at line 4702 of file dwc_otg_pcd_intr.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                int dwc_otg_pcd_iso_ep_start ( dwc_otg_pcd_t *  pcd,
                                                                                void *  ep_handle,
                                                                                uint8_t *  buf0,
                                                                                uint8_t *  buf1,
                                                                                dwc_dma_t  dma0,
                                                                                dwc_dma_t  dma1,
                                                                                int  sync_frame,
                                                                                int  dp_frame,
                                                                                int  data_per_frame,
                                                                                int  start_frame,
                                                                                int  buf_proc_intrvl,
                                                                                void *  req_handle,
                                                                                int  atomic_alloc
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Start isochronous transfers on the endpoint referenced by ep_handle. +-

                                                                                +-

                                                                                Todo:
                                                                                  +-
                                                                                • pattern data support is to be implemented in the future
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 708 of file dwc_otg_pcd.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                int dwc_otg_pcd_iso_ep_stop ( dwc_otg_pcd_t *  pcd,
                                                                                void *  ep_handle,
                                                                                void *  req_handle
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Stop ISOC transfers on endpoint referenced by ep_handle. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +- +-
                                                                                pcd The PCD
                                                                                ep_handle The handle of the endpoint
                                                                                req_handle Handle of ISOC request
                                                                                +-
                                                                                +-Returns -DWC_E_INVALID if incorrect arguments are passed to the function Returns 0 on success +-

                                                                                +-Definition at line 817 of file dwc_otg_pcd.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                void dwc_otg_pcd_get_iso_packet_params ( dwc_otg_pcd_t *  pcd,
                                                                                void *  ep_handle,
                                                                                void *  iso_req_handle,
                                                                                int  packet,
                                                                                int *  status,
                                                                                int *  actual,
                                                                                int *  offset
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Get ISOC packet status. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +- +- +- +- +- +-
                                                                                pcd The PCD
                                                                                ep_handle The handle of the endpoint
                                                                                iso_req_handle Isochronoush request handle
                                                                                packet Number of packet
                                                                                status Out parameter for returning status
                                                                                actual Out parameter for returning actual length
                                                                                offset Out parameter for returning offset
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 889 of file dwc_otg_pcd.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                int dwc_otg_pcd_get_iso_packet_count ( dwc_otg_pcd_t *  pcd,
                                                                                void *  ep_handle,
                                                                                void *  iso_req_handle
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Get ISOC packet count. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +- +-
                                                                                pcd The PCD
                                                                                ep_handle The handle of the endpoint
                                                                                iso_req_handle 
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 873 of file dwc_otg_pcd.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                int dwc_otg_pcd_wakeup ( dwc_otg_pcd_t *  pcd  ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This function starts the SRP Protocol if no session is in progress. +-

                                                                                +-If a session is already in progress, but the device is suspended, remote wakeup signaling is started. +-

                                                                                +-Definition at line 2559 of file dwc_otg_pcd.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                void dwc_otg_pcd_initiate_srp ( dwc_otg_pcd_t *  pcd  ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Initiate SRP. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +-
                                                                                pcd the pcd structure.
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 2596 of file dwc_otg_pcd.c.

                                                                                +-

                                                                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__pcd__intr_8c-source.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/dwc__otg__pcd__intr_8c-source.html 2013-07-26 19:34:42.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,4338 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_pcd_intr.c Source File +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                dwc_otg_pcd_intr.c

                                                                                Go to the documentation of this file.
                                                                                00001 /* ==========================================================================
+-00002  * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_pcd_intr.c $
+-00003  * $Revision: #113 $
+-00004  * $Date: 2011/10/24 $
+-00005  * $Change: 1871160 $
+-00006  *
+-00007  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
+-00008  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
+-00009  * otherwise expressly agreed to in writing between Synopsys and you.
+-00010  *
+-00011  * The Software IS NOT an item of Licensed Software or Licensed Product under
+-00012  * any End User Software License Agreement or Agreement for Licensed Product
+-00013  * with Synopsys or any supplement thereto. You are permitted to use and
+-00014  * redistribute this Software in source and binary forms, with or without
+-00015  * modification, provided that redistributions of source code must retain this
+-00016  * notice. You may not view, use, disclose, copy or distribute this file or
+-00017  * any information contained herein except pursuant to this license grant from
+-00018  * Synopsys. If you do not agree with this notice, including the disclaimer
+-00019  * below, then you are not authorized to use the Software.
+-00020  *
+-00021  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
+-00022  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+-00023  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+-00024  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
+-00025  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+-00026  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+-00027  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+-00028  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+-00029  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+-00030  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+-00031  * DAMAGE.
+-00032  * ========================================================================== */
+-00033 #ifndef DWC_HOST_ONLY
+-00034 
+-00035 #include "dwc_otg_pcd.h"
+-00036 
+-00037 #ifdef DWC_UTE_CFI
+-00038 #include "dwc_otg_cfi.h"
+-00039 #endif
+-00040 
+-00041 #ifdef DWC_UTE_PER_IO
+-00042 extern void complete_xiso_ep(dwc_otg_pcd_ep_t * ep);
+-00043 #endif
+-00044 //#define PRINT_CFI_DMA_DESCS
+-00045 
+-00046 #define DEBUG_EP0
+-00047 
+-00051 static void dwc_otg_pcd_update_otg(dwc_otg_pcd_t * pcd, const unsigned reset)
+-00052 {
+-00053 
+-00054         if (reset) {
+-00055                 pcd->b_hnp_enable = 0;
+-00056                 pcd->a_hnp_support = 0;
+-00057                 pcd->a_alt_hnp_support = 0;
+-00058         }
+-00059 
+-00060         if (pcd->fops->hnp_changed) {
+-00061                 pcd->fops->hnp_changed(pcd);
+-00062         }
+-00063 }
+-00064 
+-00079 static inline void print_ep0_state(dwc_otg_pcd_t * pcd)
+-00080 {
+-00081 #ifdef DEBUG
+-00082         char str[40];
+-00083 
+-00084         switch (pcd->ep0state) {
+-00085         case EP0_DISCONNECT:
+-00086                 dwc_strcpy(str, "EP0_DISCONNECT");
+-00087                 break;
+-00088         case EP0_IDLE:
+-00089                 dwc_strcpy(str, "EP0_IDLE");
+-00090                 break;
+-00091         case EP0_IN_DATA_PHASE:
+-00092                 dwc_strcpy(str, "EP0_IN_DATA_PHASE");
+-00093                 break;
+-00094         case EP0_OUT_DATA_PHASE:
+-00095                 dwc_strcpy(str, "EP0_OUT_DATA_PHASE");
+-00096                 break;
+-00097         case EP0_IN_STATUS_PHASE:
+-00098                 dwc_strcpy(str, "EP0_IN_STATUS_PHASE");
+-00099                 break;
+-00100         case EP0_OUT_STATUS_PHASE:
+-00101                 dwc_strcpy(str, "EP0_OUT_STATUS_PHASE");
+-00102                 break;
+-00103         case EP0_STALL:
+-00104                 dwc_strcpy(str, "EP0_STALL");
+-00105                 break;
+-00106         default:
+-00107                 dwc_strcpy(str, "EP0_INVALID");
+-00108         }
+-00109 
+-00110         DWC_DEBUGPL(DBG_ANY, "%s(%d)\n", str, pcd->ep0state);
+-00111 #endif
+-00112 }
+-00113 
+-00119 static inline void print_memory_payload(dwc_otg_pcd_t * pcd,  dwc_ep_t * ep)
+-00120 {
+-00121 #ifdef DEBUG
+-00122         deptsiz_data_t deptsiz_init = {.d32 = 0 };
+-00123         deptsiz_data_t deptsiz_updt = {.d32 = 0 };
+-00124         int pack_num;
+-00125         unsigned payload;
+-00126         
+-00127         deptsiz_init.d32 = pcd->core_if->start_doeptsiz_val[ep->num];
+-00128         deptsiz_updt.d32 =
+-00129                 DWC_READ_REG32(&pcd->core_if->dev_if->
+-00130                                                 out_ep_regs[ep->num]->doeptsiz);
+-00131         /* Payload will be */
+-00132         payload = deptsiz_init.b.xfersize - deptsiz_updt.b.xfersize;
+-00133         /* Packet count is decremented every time a packet
+-00134          * is written to the RxFIFO not in to the external memory
+-00135          * So, if payload == 0, then it means no packet was sent to ext memory*/
+-00136         pack_num = (!payload) ? 0 : (deptsiz_init.b.pktcnt - deptsiz_updt.b.pktcnt);
+-00137         DWC_DEBUGPL(DBG_PCDV,
+-00138                 "Payload for EP%d-%s\n",
+-00139                 ep->num, (ep->is_in ? "IN" : "OUT"));
+-00140         DWC_DEBUGPL(DBG_PCDV,
+-00141                 "Number of transfered bytes = 0x%08x\n", payload);
+-00142         DWC_DEBUGPL(DBG_PCDV,
+-00143                 "Number of transfered packets = %d\n", pack_num);       
+-00144 #endif  
+-00145 }
+-00146 
+-00147 
+-00148 #ifdef DWC_UTE_CFI
+-00149 static inline void print_desc(struct dwc_otg_dma_desc *ddesc,
+-00150                               const uint8_t * epname, int descnum)
+-00151 {
+-00152         CFI_INFO
+-00153             ("%s DMA_DESC(%d) buf=0x%08x bytes=0x%04x; sp=0x%x; l=0x%x; sts=0x%02x; bs=0x%02x\n",
+-00154              epname, descnum, ddesc->buf, ddesc->status.b.bytes,
+-00155              ddesc->status.b.sp, ddesc->status.b.l, ddesc->status.b.sts,
+-00156              ddesc->status.b.bs);
+-00157 }
+-00158 #endif
+-00159 
+-00163 static inline dwc_otg_pcd_ep_t *get_in_ep(dwc_otg_pcd_t * pcd, uint32_t ep_num)
+-00164 {
+-00165         int i;
+-00166         int num_in_eps = GET_CORE_IF(pcd)->dev_if->num_in_eps;
+-00167         if (ep_num == 0) {
+-00168                 return &pcd->ep0;
+-00169         } else {
+-00170                 for (i = 0; i < num_in_eps; ++i) {
+-00171                         if (pcd->in_ep[i].dwc_ep.num == ep_num)
+-00172                                 return &pcd->in_ep[i];
+-00173                 }
+-00174                 return 0;
+-00175         }
+-00176 }
+-00177 
+-00181 static inline dwc_otg_pcd_ep_t *get_out_ep(dwc_otg_pcd_t * pcd, uint32_t ep_num)
+-00182 {
+-00183         int i;
+-00184         int num_out_eps = GET_CORE_IF(pcd)->dev_if->num_out_eps;
+-00185         if (ep_num == 0) {
+-00186                 return &pcd->ep0;
+-00187         } else {
+-00188                 for (i = 0; i < num_out_eps; ++i) {
+-00189                         if (pcd->out_ep[i].dwc_ep.num == ep_num)
+-00190                                 return &pcd->out_ep[i];
+-00191                 }
+-00192                 return 0;
+-00193         }
+-00194 }
+-00195 
+-00200 dwc_otg_pcd_ep_t *get_ep_by_addr(dwc_otg_pcd_t * pcd, u16 wIndex)
+-00201 {
+-00202         dwc_otg_pcd_ep_t *ep;
+-00203         uint32_t ep_num = UE_GET_ADDR(wIndex);
+-00204 
+-00205         if (ep_num == 0) {
+-00206                 ep = &pcd->ep0;
+-00207         } else if (UE_GET_DIR(wIndex) == UE_DIR_IN) {   /* in ep */
+-00208                 ep = &pcd->in_ep[ep_num - 1];
+-00209         } else {
+-00210                 ep = &pcd->out_ep[ep_num - 1];
+-00211         }
+-00212 
+-00213         return ep;
+-00214 }
+-00215 
+-00220 void start_next_request(dwc_otg_pcd_ep_t * ep)
+-00221 {
+-00222         dwc_otg_pcd_request_t *req = 0;
+-00223         uint32_t max_transfer =
+-00224             GET_CORE_IF(ep->pcd)->core_params->max_transfer_size;
+-00225 
+-00226 #ifdef DWC_UTE_CFI
+-00227         struct dwc_otg_pcd *pcd;
+-00228         pcd = ep->pcd;
+-00229 #endif
+-00230 
+-00231         if (!DWC_CIRCLEQ_EMPTY(&ep->queue)) {
+-00232                 req = DWC_CIRCLEQ_FIRST(&ep->queue);
+-00233 
+-00234 #ifdef DWC_UTE_CFI
+-00235                 if (ep->dwc_ep.buff_mode != BM_STANDARD) {
+-00236                         ep->dwc_ep.cfi_req_len = req->length;
+-00237                         pcd->cfi->ops.build_descriptors(pcd->cfi, pcd, ep, req);
+-00238                 } else {
+-00239 #endif
+-00240                         /* Setup and start the Transfer */
+-00241                         if (req->dw_align_buf) {
+-00242                                 ep->dwc_ep.dma_addr = req->dw_align_buf_dma;
+-00243                                 ep->dwc_ep.start_xfer_buff = req->dw_align_buf;
+-00244                                 ep->dwc_ep.xfer_buff = req->dw_align_buf;
+-00245                         } else {
+-00246                                 ep->dwc_ep.dma_addr = req->dma;
+-00247                                 ep->dwc_ep.start_xfer_buff = req->buf;
+-00248                                 ep->dwc_ep.xfer_buff = req->buf;
+-00249                         }
+-00250                         ep->dwc_ep.sent_zlp = 0;
+-00251                         ep->dwc_ep.total_len = req->length;
+-00252                         ep->dwc_ep.xfer_len = 0;
+-00253                         ep->dwc_ep.xfer_count = 0;
+-00254 
+-00255                         ep->dwc_ep.maxxfer = max_transfer;
+-00256                         if (GET_CORE_IF(ep->pcd)->dma_desc_enable) {
+-00257                                 uint32_t out_max_xfer = DDMA_MAX_TRANSFER_SIZE
+-00258                                     - (DDMA_MAX_TRANSFER_SIZE % 4);
+-00259                                 if (ep->dwc_ep.is_in) {
+-00260                                         if (ep->dwc_ep.maxxfer >
+-00261                                             DDMA_MAX_TRANSFER_SIZE) {
+-00262                                                 ep->dwc_ep.maxxfer =
+-00263                                                     DDMA_MAX_TRANSFER_SIZE;
+-00264                                         }
+-00265                                 } else {
+-00266                                         if (ep->dwc_ep.maxxfer > out_max_xfer) {
+-00267                                                 ep->dwc_ep.maxxfer =
+-00268                                                     out_max_xfer;
+-00269                                         }
+-00270                                 }
+-00271                         }
+-00272                         if (ep->dwc_ep.maxxfer < ep->dwc_ep.total_len) {
+-00273                                 ep->dwc_ep.maxxfer -=
+-00274                                     (ep->dwc_ep.maxxfer % ep->dwc_ep.maxpacket);
+-00275                         }
+-00276                         if (req->sent_zlp) {
+-00277                                 if ((ep->dwc_ep.total_len %
+-00278                                      ep->dwc_ep.maxpacket == 0)
+-00279                                     && (ep->dwc_ep.total_len != 0)) {
+-00280                                         ep->dwc_ep.sent_zlp = 1;
+-00281                                 }
+-00282 
+-00283                         }
+-00284 #ifdef DWC_UTE_CFI
+-00285                 }
+-00286 #endif
+-00287                 dwc_otg_ep_start_transfer(GET_CORE_IF(ep->pcd), &ep->dwc_ep);
+-00288         } else if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) {
+-00289                 DWC_PRINTF("There are no more ISOC requests \n");
+-00290                 ep->dwc_ep.frame_num = 0xFFFFFFFF;
+-00291         }
+-00292 }
+-00293 
+-00298 int32_t dwc_otg_pcd_handle_sof_intr(dwc_otg_pcd_t * pcd)
+-00299 {
+-00300         dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
+-00301 
+-00302         gintsts_data_t gintsts;
+-00303 
+-00304         DWC_DEBUGPL(DBG_PCD, "SOF\n");
+-00305 
+-00306         /* Clear interrupt */
+-00307         gintsts.d32 = 0;
+-00308         gintsts.b.sofintr = 1;
+-00309         DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
+-00310 
+-00311         return 1;
+-00312 }
+-00313 
+-00331 int32_t dwc_otg_pcd_handle_rx_status_q_level_intr(dwc_otg_pcd_t * pcd)
+-00332 {
+-00333         dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
+-00334         dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
+-00335         gintmsk_data_t gintmask = {.d32 = 0 };
+-00336         device_grxsts_data_t status;
+-00337         dwc_otg_pcd_ep_t *ep;
+-00338         gintsts_data_t gintsts;
+-00339 #ifdef DEBUG
+-00340         static char *dpid_str[] = { "D0", "D2", "D1", "MDATA" };
+-00341 #endif
+-00342 
+-00343         //DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, _pcd);
+-00344         /* Disable the Rx Status Queue Level interrupt */
+-00345         gintmask.b.rxstsqlvl = 1;
+-00346         DWC_MODIFY_REG32(&global_regs->gintmsk, gintmask.d32, 0);
+-00347 
+-00348         /* Get the Status from the top of the FIFO */
+-00349         status.d32 = DWC_READ_REG32(&global_regs->grxstsp);
+-00350 
+-00351         DWC_DEBUGPL(DBG_PCD, "EP:%d BCnt:%d DPID:%s "
+-00352                     "pktsts:%x Frame:%d(0x%0x)\n",
+-00353                     status.b.epnum, status.b.bcnt,
+-00354                     dpid_str[status.b.dpid],
+-00355                     status.b.pktsts, status.b.fn, status.b.fn);
+-00356         /* Get pointer to EP structure */
+-00357         ep = get_out_ep(pcd, status.b.epnum);
+-00358 
+-00359         switch (status.b.pktsts) {
+-00360         case DWC_DSTS_GOUT_NAK:
+-00361                 DWC_DEBUGPL(DBG_PCDV, "Global OUT NAK\n");
+-00362                 break;
+-00363         case DWC_STS_DATA_UPDT:
+-00364                 DWC_DEBUGPL(DBG_PCDV, "OUT Data Packet\n");
+-00365                 if (status.b.bcnt && ep->dwc_ep.xfer_buff) {
+-00367                         dwc_otg_read_packet(core_if,
+-00368                                             ep->dwc_ep.xfer_buff,
+-00369                                             status.b.bcnt);
+-00370                         ep->dwc_ep.xfer_count += status.b.bcnt;
+-00371                         ep->dwc_ep.xfer_buff += status.b.bcnt;
+-00372                 }
+-00373                 break;
+-00374         case DWC_STS_XFER_COMP:
+-00375                 DWC_DEBUGPL(DBG_PCDV, "OUT Complete\n");
+-00376                 break;
+-00377         case DWC_DSTS_SETUP_COMP:
+-00378 #ifdef DEBUG_EP0
+-00379                 DWC_DEBUGPL(DBG_PCDV, "Setup Complete\n");
+-00380 #endif
+-00381                 break;
+-00382         case DWC_DSTS_SETUP_UPDT:
+-00383                 dwc_otg_read_setup_packet(core_if, pcd->setup_pkt->d32);
+-00384 #ifdef DEBUG_EP0
+-00385                 DWC_DEBUGPL(DBG_PCD,
+-00386                             "SETUP PKT: %02x.%02x v%04x i%04x l%04x\n",
+-00387                             pcd->setup_pkt->req.bmRequestType,
+-00388                             pcd->setup_pkt->req.bRequest,
+-00389                             UGETW(pcd->setup_pkt->req.wValue),
+-00390                             UGETW(pcd->setup_pkt->req.wIndex),
+-00391                             UGETW(pcd->setup_pkt->req.wLength));
+-00392 #endif
+-00393                 ep->dwc_ep.xfer_count += status.b.bcnt;
+-00394                 break;
+-00395         default:
+-00396                 DWC_DEBUGPL(DBG_PCDV, "Invalid Packet Status (0x%0x)\n",
+-00397                             status.b.pktsts);
+-00398                 break;
+-00399         }
+-00400 
+-00401         /* Enable the Rx Status Queue Level interrupt */
+-00402         DWC_MODIFY_REG32(&global_regs->gintmsk, 0, gintmask.d32);
+-00403         /* Clear interrupt */
+-00404         gintsts.d32 = 0;
+-00405         gintsts.b.rxstsqlvl = 1;
+-00406         DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
+-00407 
+-00408         //DWC_DEBUGPL(DBG_PCDV, "EXIT: %s\n", __func__);
+-00409         return 1;
+-00410 }
+-00411 
+-00424 static inline int get_ep_of_last_in_token(dwc_otg_core_if_t * core_if)
+-00425 {
+-00426         dwc_otg_device_global_regs_t *dev_global_regs =
+-00427             core_if->dev_if->dev_global_regs;
+-00428         const uint32_t TOKEN_Q_DEPTH = core_if->hwcfg2.b.dev_token_q_depth;
+-00429         /* Number of Token Queue Registers */
+-00430         const int DTKNQ_REG_CNT = (TOKEN_Q_DEPTH + 7) / 8;
+-00431         dtknq1_data_t dtknqr1;
+-00432         uint32_t in_tkn_epnums[4];
+-00433         int ndx = 0;
+-00434         int i = 0;
+-00435         volatile uint32_t *addr = &dev_global_regs->dtknqr1;
+-00436         int epnum = 0;
+-00437 
+-00438         //DWC_DEBUGPL(DBG_PCD,"dev_token_q_depth=%d\n",TOKEN_Q_DEPTH);
+-00439 
+-00440         /* Read the DTKNQ Registers */
+-00441         for (i = 0; i < DTKNQ_REG_CNT; i++) {
+-00442                 in_tkn_epnums[i] = DWC_READ_REG32(addr);
+-00443                 DWC_DEBUGPL(DBG_PCDV, "DTKNQR%d=0x%08x\n", i + 1,
+-00444                             in_tkn_epnums[i]);
+-00445                 if (addr == &dev_global_regs->dvbusdis) {
+-00446                         addr = &dev_global_regs->dtknqr3_dthrctl;
+-00447                 } else {
+-00448                         ++addr;
+-00449                 }
+-00450 
+-00451         }
+-00452 
+-00453         /* Copy the DTKNQR1 data to the bit field. */
+-00454         dtknqr1.d32 = in_tkn_epnums[0];
+-00455         /* Get the EP numbers */
+-00456         in_tkn_epnums[0] = dtknqr1.b.epnums0_5;
+-00457         ndx = dtknqr1.b.intknwptr - 1;
+-00458 
+-00459         //DWC_DEBUGPL(DBG_PCDV,"ndx=%d\n",ndx);
+-00460         if (ndx == -1) {
+-00463                 int cnt = TOKEN_Q_DEPTH;
+-00464                 if (TOKEN_Q_DEPTH <= 6) {
+-00465                         cnt = TOKEN_Q_DEPTH - 1;
+-00466                 } else if (TOKEN_Q_DEPTH <= 14) {
+-00467                         cnt = TOKEN_Q_DEPTH - 7;
+-00468                 } else if (TOKEN_Q_DEPTH <= 22) {
+-00469                         cnt = TOKEN_Q_DEPTH - 15;
+-00470                 } else {
+-00471                         cnt = TOKEN_Q_DEPTH - 23;
+-00472                 }
+-00473                 epnum = (in_tkn_epnums[DTKNQ_REG_CNT - 1] >> (cnt * 4)) & 0xF;
+-00474         } else {
+-00475                 if (ndx <= 5) {
+-00476                         epnum = (in_tkn_epnums[0] >> (ndx * 4)) & 0xF;
+-00477                 } else if (ndx <= 13) {
+-00478                         ndx -= 6;
+-00479                         epnum = (in_tkn_epnums[1] >> (ndx * 4)) & 0xF;
+-00480                 } else if (ndx <= 21) {
+-00481                         ndx -= 14;
+-00482                         epnum = (in_tkn_epnums[2] >> (ndx * 4)) & 0xF;
+-00483                 } else if (ndx <= 29) {
+-00484                         ndx -= 22;
+-00485                         epnum = (in_tkn_epnums[3] >> (ndx * 4)) & 0xF;
+-00486                 }
+-00487         }
+-00488         //DWC_DEBUGPL(DBG_PCD,"epnum=%d\n",epnum);
+-00489         return epnum;
+-00490 }
+-00491 
+-00497 int32_t dwc_otg_pcd_handle_np_tx_fifo_empty_intr(dwc_otg_pcd_t * pcd)
+-00498 {
+-00499         dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
+-00500         dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
+-00501         dwc_otg_dev_in_ep_regs_t *ep_regs;
+-00502         gnptxsts_data_t txstatus = {.d32 = 0 };
+-00503         gintsts_data_t gintsts;
+-00504 
+-00505         int epnum = 0;
+-00506         dwc_otg_pcd_ep_t *ep = 0;
+-00507         uint32_t len = 0;
+-00508         int dwords;
+-00509 
+-00510         /* Get the epnum from the IN Token Learning Queue. */
+-00511         epnum = get_ep_of_last_in_token(core_if);
+-00512         ep = get_in_ep(pcd, epnum);
+-00513 
+-00514         DWC_DEBUGPL(DBG_PCD, "NP TxFifo Empty: %d \n", epnum);
+-00515 
+-00516         ep_regs = core_if->dev_if->in_ep_regs[epnum];
+-00517 
+-00518         len = ep->dwc_ep.xfer_len - ep->dwc_ep.xfer_count;
+-00519         if (len > ep->dwc_ep.maxpacket) {
+-00520                 len = ep->dwc_ep.maxpacket;
+-00521         }
+-00522         dwords = (len + 3) / 4;
+-00523 
+-00524         /* While there is space in the queue and space in the FIFO and
+-00525          * More data to tranfer, Write packets to the Tx FIFO */
+-00526         txstatus.d32 = DWC_READ_REG32(&global_regs->gnptxsts);
+-00527         DWC_DEBUGPL(DBG_PCDV, "b4 GNPTXSTS=0x%08x\n", txstatus.d32);
+-00528 
+-00529         while (txstatus.b.nptxqspcavail > 0 &&
+-00530                txstatus.b.nptxfspcavail > dwords &&
+-00531                ep->dwc_ep.xfer_count < ep->dwc_ep.xfer_len) {
+-00532                 /* Write the FIFO */
+-00533                 dwc_otg_ep_write_packet(core_if, &ep->dwc_ep, 0);
+-00534                 len = ep->dwc_ep.xfer_len - ep->dwc_ep.xfer_count;
+-00535 
+-00536                 if (len > ep->dwc_ep.maxpacket) {
+-00537                         len = ep->dwc_ep.maxpacket;
+-00538                 }
+-00539 
+-00540                 dwords = (len + 3) / 4;
+-00541                 txstatus.d32 = DWC_READ_REG32(&global_regs->gnptxsts);
+-00542                 DWC_DEBUGPL(DBG_PCDV, "GNPTXSTS=0x%08x\n", txstatus.d32);
+-00543         }
+-00544 
+-00545         DWC_DEBUGPL(DBG_PCDV, "GNPTXSTS=0x%08x\n",
+-00546                     DWC_READ_REG32(&global_regs->gnptxsts));
+-00547 
+-00548         /* Clear interrupt */
+-00549         gintsts.d32 = 0;
+-00550         gintsts.b.nptxfempty = 1;
+-00551         DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
+-00552 
+-00553         return 1;
+-00554 }
+-00555 
+-00561 static int32_t write_empty_tx_fifo(dwc_otg_pcd_t * pcd, uint32_t epnum)
+-00562 {
+-00563         dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
+-00564         dwc_otg_dev_if_t *dev_if = core_if->dev_if;
+-00565         dwc_otg_dev_in_ep_regs_t *ep_regs;
+-00566         dtxfsts_data_t txstatus = {.d32 = 0 };
+-00567         dwc_otg_pcd_ep_t *ep = 0;
+-00568         uint32_t len = 0;
+-00569         int dwords;
+-00570 
+-00571         ep = get_in_ep(pcd, epnum);
+-00572 
+-00573         DWC_DEBUGPL(DBG_PCD, "Dedicated TxFifo Empty: %d \n", epnum);
+-00574 
+-00575         ep_regs = core_if->dev_if->in_ep_regs[epnum];
+-00576 
+-00577         len = ep->dwc_ep.xfer_len - ep->dwc_ep.xfer_count;
+-00578 
+-00579         if (len > ep->dwc_ep.maxpacket) {
+-00580                 len = ep->dwc_ep.maxpacket;
+-00581         }
+-00582 
+-00583         dwords = (len + 3) / 4;
+-00584 
+-00585         /* While there is space in the queue and space in the FIFO and
+-00586          * More data to tranfer, Write packets to the Tx FIFO */
+-00587         txstatus.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->dtxfsts);
+-00588         DWC_DEBUGPL(DBG_PCDV, "b4 dtxfsts[%d]=0x%08x\n", epnum, txstatus.d32);
+-00589 
+-00590         while (txstatus.b.txfspcavail > dwords &&
+-00591                ep->dwc_ep.xfer_count < ep->dwc_ep.xfer_len &&
+-00592                ep->dwc_ep.xfer_len != 0) {
+-00593                 /* Write the FIFO */
+-00594                 dwc_otg_ep_write_packet(core_if, &ep->dwc_ep, 0);
+-00595 
+-00596                 len = ep->dwc_ep.xfer_len - ep->dwc_ep.xfer_count;
+-00597                 if (len > ep->dwc_ep.maxpacket) {
+-00598                         len = ep->dwc_ep.maxpacket;
+-00599                 }
+-00600 
+-00601                 dwords = (len + 3) / 4;
+-00602                 txstatus.d32 =
+-00603                     DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->dtxfsts);
+-00604                 DWC_DEBUGPL(DBG_PCDV, "dtxfsts[%d]=0x%08x\n", epnum,
+-00605                             txstatus.d32);
+-00606         }
+-00607 
+-00608         DWC_DEBUGPL(DBG_PCDV, "b4 dtxfsts[%d]=0x%08x\n", epnum,
+-00609                     DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->dtxfsts));
+-00610 
+-00611         return 1;
+-00612 }
+-00613 
+-00619 void dwc_otg_pcd_stop(dwc_otg_pcd_t * pcd)
+-00620 {
+-00621         int i, num_in_eps, num_out_eps;
+-00622         dwc_otg_pcd_ep_t *ep;
+-00623 
+-00624         gintmsk_data_t intr_mask = {.d32 = 0 };
+-00625 
+-00626         DWC_SPINLOCK(pcd->lock);
+-00627 
+-00628         num_in_eps = GET_CORE_IF(pcd)->dev_if->num_in_eps;
+-00629         num_out_eps = GET_CORE_IF(pcd)->dev_if->num_out_eps;
+-00630 
+-00631         DWC_DEBUGPL(DBG_PCDV, "%s() \n", __func__);
+-00632         /* don't disconnect drivers more than once */
+-00633         if (pcd->ep0state == EP0_DISCONNECT) {
+-00634                 DWC_DEBUGPL(DBG_ANY, "%s() Already Disconnected\n", __func__);
+-00635                 DWC_SPINUNLOCK(pcd->lock);
+-00636                 return;
+-00637         }
+-00638         pcd->ep0state = EP0_DISCONNECT;
+-00639 
+-00640         /* Reset the OTG state. */
+-00641         dwc_otg_pcd_update_otg(pcd, 1);
+-00642 
+-00643         /* Disable the NP Tx Fifo Empty Interrupt. */
+-00644         intr_mask.b.nptxfempty = 1;
+-00645         DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk,
+-00646                          intr_mask.d32, 0);
+-00647 
+-00648         /* Flush the FIFOs */
+-00650         dwc_otg_flush_tx_fifo(GET_CORE_IF(pcd), 0x10);
+-00651         dwc_otg_flush_rx_fifo(GET_CORE_IF(pcd));
+-00652 
+-00653         /* prevent new request submissions, kill any outstanding requests  */
+-00654         ep = &pcd->ep0;
+-00655         dwc_otg_request_nuke(ep);
+-00656         /* prevent new request submissions, kill any outstanding requests  */
+-00657         for (i = 0; i < num_in_eps; i++) {
+-00658                 dwc_otg_pcd_ep_t *ep = &pcd->in_ep[i];
+-00659                 dwc_otg_request_nuke(ep);
+-00660         }
+-00661         /* prevent new request submissions, kill any outstanding requests  */
+-00662         for (i = 0; i < num_out_eps; i++) {
+-00663                 dwc_otg_pcd_ep_t *ep = &pcd->out_ep[i];
+-00664                 dwc_otg_request_nuke(ep);
+-00665         }
+-00666 
+-00667         /* report disconnect; the driver is already quiesced */
+-00668         if (pcd->fops->disconnect) {
+-00669                 DWC_SPINUNLOCK(pcd->lock);
+-00670                 pcd->fops->disconnect(pcd);
+-00671                 DWC_SPINLOCK(pcd->lock);
+-00672         }
+-00673         DWC_SPINUNLOCK(pcd->lock);
+-00674 }
+-00675 
+-00679 int32_t dwc_otg_pcd_handle_i2c_intr(dwc_otg_pcd_t * pcd)
+-00680 {
+-00681         gintmsk_data_t intr_mask = {.d32 = 0 };
+-00682         gintsts_data_t gintsts;
+-00683 
+-00684         DWC_PRINTF("INTERRUPT Handler not implemented for %s\n", "i2cintr");
+-00685         intr_mask.b.i2cintr = 1;
+-00686         DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk,
+-00687                          intr_mask.d32, 0);
+-00688 
+-00689         /* Clear interrupt */
+-00690         gintsts.d32 = 0;
+-00691         gintsts.b.i2cintr = 1;
+-00692         DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
+-00693                         gintsts.d32);
+-00694         return 1;
+-00695 }
+-00696 
+-00700 int32_t dwc_otg_pcd_handle_early_suspend_intr(dwc_otg_pcd_t * pcd)
+-00701 {
+-00702         gintsts_data_t gintsts;
+-00703 #if defined(VERBOSE)
+-00704         DWC_PRINTF("Early Suspend Detected\n");
+-00705 #endif
+-00706 
+-00707         /* Clear interrupt */
+-00708         gintsts.d32 = 0;
+-00709         gintsts.b.erlysuspend = 1;
+-00710         DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
+-00711                         gintsts.d32);
+-00712         return 1;
+-00713 }
+-00714 
+-00732 static inline void ep0_out_start(dwc_otg_core_if_t * core_if,
+-00733                                  dwc_otg_pcd_t * pcd)
+-00734 {
+-00735         dwc_otg_dev_if_t *dev_if = core_if->dev_if;
+-00736         deptsiz0_data_t doeptsize0 = {.d32 = 0 };
+-00737         dwc_otg_dev_dma_desc_t *dma_desc;
+-00738         depctl_data_t doepctl = {.d32 = 0 };
+-00739 
+-00740 #ifdef VERBOSE
+-00741         DWC_DEBUGPL(DBG_PCDV, "%s() doepctl0=%0x\n", __func__,
+-00742                     DWC_READ_REG32(&dev_if->out_ep_regs[0]->doepctl));
+-00743 #endif
+-00744 
+-00745         doeptsize0.b.supcnt = 3;
+-00746         doeptsize0.b.pktcnt = 1;
+-00747         doeptsize0.b.xfersize = 8 * 3;
+-00748 
+-00749         if (core_if->dma_enable) {
+-00750                 if (!core_if->dma_desc_enable) {
+-00752                         DWC_WRITE_REG32(&dev_if->out_ep_regs[0]->doeptsiz,
+-00753                                         doeptsize0.d32);
+-00754 
+-00756                         DWC_WRITE_REG32(&dev_if->out_ep_regs[0]->doepdma,
+-00757                                         pcd->setup_pkt_dma_handle);
+-00758                 } else {
+-00759                         dev_if->setup_desc_index =
+-00760                             (dev_if->setup_desc_index + 1) & 1;
+-00761                         dma_desc =
+-00762                             dev_if->setup_desc_addr[dev_if->setup_desc_index];
+-00763 
+-00765                         dma_desc->status.b.bs = BS_HOST_BUSY;
+-00766                         dma_desc->status.b.l = 1;
+-00767                         dma_desc->status.b.ioc = 1;
+-00768                         dma_desc->status.b.bytes = pcd->ep0.dwc_ep.maxpacket;
+-00769                         dma_desc->buf = pcd->setup_pkt_dma_handle;
+-00770                         dma_desc->status.b.sts = 0;
+-00771                         dma_desc->status.b.bs = BS_HOST_READY;
+-00772 
+-00774                         DWC_WRITE_REG32(&dev_if->out_ep_regs[0]->doepdma,
+-00775                                         dev_if->
+-00776                                         dma_setup_desc_addr
+-00777                                         [dev_if->setup_desc_index]);
+-00778                 }
+-00779 
+-00780         } else {
+-00782                 DWC_WRITE_REG32(&dev_if->out_ep_regs[0]->doeptsiz,
+-00783                                 doeptsize0.d32);
+-00784         }
+-00785 
+-00787         doepctl.b.epena = 1;
+-00788         doepctl.b.cnak = 1;
+-00789         DWC_WRITE_REG32(&dev_if->out_ep_regs[0]->doepctl, doepctl.d32);
+-00790 
+-00791 #ifdef VERBOSE
+-00792         DWC_DEBUGPL(DBG_PCDV, "doepctl0=%0x\n",
+-00793                     DWC_READ_REG32(&dev_if->out_ep_regs[0]->doepctl));
+-00794         DWC_DEBUGPL(DBG_PCDV, "diepctl0=%0x\n",
+-00795                     DWC_READ_REG32(&dev_if->in_ep_regs[0]->diepctl));
+-00796 #endif
+-00797 }
+-00798 
+-00822 int32_t dwc_otg_pcd_handle_usb_reset_intr(dwc_otg_pcd_t * pcd)
+-00823 {
+-00824         dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
+-00825         dwc_otg_dev_if_t *dev_if = core_if->dev_if;
+-00826         depctl_data_t doepctl = {.d32 = 0 };
+-00827         depctl_data_t diepctl = {.d32 = 0 };
+-00828         daint_data_t daintmsk = {.d32 = 0 };
+-00829         doepmsk_data_t doepmsk = {.d32 = 0 };
+-00830         diepmsk_data_t diepmsk = {.d32 = 0 };
+-00831         dcfg_data_t dcfg = {.d32 = 0 };
+-00832         grstctl_t resetctl = {.d32 = 0 };
+-00833         dctl_data_t dctl = {.d32 = 0 };
+-00834         int i = 0;
+-00835         gintsts_data_t gintsts;
+-00836         pcgcctl_data_t power = {.d32 = 0 };
+-00837 
+-00838         power.d32 = DWC_READ_REG32(core_if->pcgcctl);
+-00839         if (power.b.stoppclk) {
+-00840                 power.d32 = 0;
+-00841                 power.b.stoppclk = 1;
+-00842                 DWC_MODIFY_REG32(core_if->pcgcctl, power.d32, 0);
+-00843 
+-00844                 power.b.pwrclmp = 1;
+-00845                 DWC_MODIFY_REG32(core_if->pcgcctl, power.d32, 0);
+-00846 
+-00847                 power.b.rstpdwnmodule = 1;
+-00848                 DWC_MODIFY_REG32(core_if->pcgcctl, power.d32, 0);
+-00849         }
+-00850 
+-00851         core_if->lx_state = DWC_OTG_L0;
+-00852 
+-00853         DWC_PRINTF("USB RESET\n");
+-00854 #ifdef DWC_EN_ISOC
+-00855         for (i = 1; i < 16; ++i) {
+-00856                 dwc_otg_pcd_ep_t *ep;
+-00857                 dwc_ep_t *dwc_ep;
+-00858                 ep = get_in_ep(pcd, i);
+-00859                 if (ep != 0) {
+-00860                         dwc_ep = &ep->dwc_ep;
+-00861                         dwc_ep->next_frame = 0xffffffff;
+-00862                 }
+-00863         }
+-00864 #endif /* DWC_EN_ISOC */
+-00865 
+-00866         /* reset the HNP settings */
+-00867         dwc_otg_pcd_update_otg(pcd, 1);
+-00868 
+-00869         /* Clear the Remote Wakeup Signalling */
+-00870         dctl.b.rmtwkupsig = 1;
+-00871         DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32, 0);
+-00872 
+-00873         /* Set NAK for all OUT EPs */
+-00874         doepctl.b.snak = 1;
+-00875         for (i = 0; i <= dev_if->num_out_eps; i++) {
+-00876                 DWC_WRITE_REG32(&dev_if->out_ep_regs[i]->doepctl, doepctl.d32);
+-00877         }
+-00878 
+-00879         /* Flush the NP Tx FIFO */
+-00880         dwc_otg_flush_tx_fifo(core_if, 0x10);
+-00881         /* Flush the Learning Queue */
+-00882         resetctl.b.intknqflsh = 1;
+-00883         DWC_WRITE_REG32(&core_if->core_global_regs->grstctl, resetctl.d32);
+-00884 
+-00885         if (!core_if->core_params->en_multiple_tx_fifo && core_if->dma_enable) {
+-00886                 core_if->start_predict = 0;
+-00887                 for (i = 0; i<= core_if->dev_if->num_in_eps; ++i) {
+-00888                         core_if->nextep_seq[i] = 0xff;  // 0xff - EP not active
+-00889                 }
+-00890                 core_if->nextep_seq[0] = 0;     
+-00891                 core_if->first_in_nextep_seq = 0;
+-00892                 diepctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[0]->diepctl);
+-00893                 diepctl.b.nextep = 0;
+-00894                 DWC_WRITE_REG32(&dev_if->in_ep_regs[0]->diepctl, diepctl.d32);
+-00895                 
+-00896                 /* Update IN Endpoint Mismatch Count by active IN NP EP count + 1 */
+-00897                 dcfg.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->dcfg);
+-00898                 dcfg.b.epmscnt = 2;
+-00899                 DWC_WRITE_REG32(&dev_if->dev_global_regs->dcfg, dcfg.d32);
+-00900 
+-00901                 DWC_DEBUGPL(DBG_PCDV,"%s first_in_nextep_seq= %2d; nextep_seq[]:\n", 
+-00902                         __func__, core_if->first_in_nextep_seq);
+-00903                 for (i=0; i <= core_if->dev_if->num_in_eps; i++) {
+-00904                         DWC_DEBUGPL(DBG_PCDV, "%2d\n", core_if->nextep_seq[i]);
+-00905                 }
+-00906         }
+-00907 
+-00908         if (core_if->multiproc_int_enable) {
+-00909                 daintmsk.b.inep0 = 1;
+-00910                 daintmsk.b.outep0 = 1;
+-00911                 DWC_WRITE_REG32(&dev_if->dev_global_regs->deachintmsk,
+-00912                                 daintmsk.d32);
+-00913 
+-00914                 doepmsk.b.setup = 1;
+-00915                 doepmsk.b.xfercompl = 1;
+-00916                 doepmsk.b.ahberr = 1;
+-00917                 doepmsk.b.epdisabled = 1;
+-00918 
+-00919                 if (core_if->dma_desc_enable) {
+-00920                         doepmsk.b.stsphsercvd = 1;
+-00921                         doepmsk.b.bna = 1;
+-00922                 }
+-00923 /*              
+-00924                 doepmsk.b.babble = 1;
+-00925                 doepmsk.b.nyet = 1;
+-00926                 
+-00927                 if (core_if->dma_enable) {
+-00928                         doepmsk.b.nak = 1;
+-00929                 }
+-00930 */
+-00931                 DWC_WRITE_REG32(&dev_if->dev_global_regs->doepeachintmsk[0],
+-00932                                 doepmsk.d32);
+-00933 
+-00934                 diepmsk.b.xfercompl = 1;
+-00935                 diepmsk.b.timeout = 1;
+-00936                 diepmsk.b.epdisabled = 1;
+-00937                 diepmsk.b.ahberr = 1;
+-00938                 diepmsk.b.intknepmis = 1; 
+-00939                 if (!core_if->en_multiple_tx_fifo && core_if->dma_enable)
+-00940                         diepmsk.b.intknepmis = 0; 
+-00941 
+-00942 /*              if (core_if->dma_desc_enable) {
+-00943                         diepmsk.b.bna = 1;
+-00944                 }
+-00945 */
+-00946 /*              
+-00947                 if (core_if->dma_enable) {
+-00948                         diepmsk.b.nak = 1;
+-00949                 }
+-00950 */
+-00951                 DWC_WRITE_REG32(&dev_if->dev_global_regs->diepeachintmsk[0],
+-00952                                 diepmsk.d32);
+-00953         } else {
+-00954                 daintmsk.b.inep0 = 1;
+-00955                 daintmsk.b.outep0 = 1;
+-00956                 DWC_WRITE_REG32(&dev_if->dev_global_regs->daintmsk,
+-00957                                 daintmsk.d32);
+-00958 
+-00959                 doepmsk.b.setup = 1;
+-00960                 doepmsk.b.xfercompl = 1;
+-00961                 doepmsk.b.ahberr = 1;
+-00962                 doepmsk.b.epdisabled = 1;
+-00963 
+-00964                 if (core_if->dma_desc_enable) {
+-00965                         doepmsk.b.stsphsercvd = 1;
+-00966                         doepmsk.b.bna = 1;
+-00967                 }
+-00968                 DWC_WRITE_REG32(&dev_if->dev_global_regs->doepmsk, doepmsk.d32);
+-00969 
+-00970                 diepmsk.b.xfercompl = 1;
+-00971                 diepmsk.b.timeout = 1;
+-00972                 diepmsk.b.epdisabled = 1;
+-00973                 diepmsk.b.ahberr = 1;
+-00974                 if (!core_if->en_multiple_tx_fifo && core_if->dma_enable)
+-00975                         diepmsk.b.intknepmis = 0; 
+-00976 /*
+-00977                 if (core_if->dma_desc_enable) {
+-00978                         diepmsk.b.bna = 1;
+-00979                 }
+-00980 */
+-00981 
+-00982                 DWC_WRITE_REG32(&dev_if->dev_global_regs->diepmsk, diepmsk.d32);
+-00983         }
+-00984 
+-00985         /* Reset Device Address */
+-00986         dcfg.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->dcfg);
+-00987         dcfg.b.devaddr = 0;
+-00988         DWC_WRITE_REG32(&dev_if->dev_global_regs->dcfg, dcfg.d32);
+-00989 
+-00990         /* setup EP0 to receive SETUP packets */
+-00991         ep0_out_start(core_if, pcd);
+-00992 
+-00993         /* Clear interrupt */
+-00994         gintsts.d32 = 0;
+-00995         gintsts.b.usbreset = 1;
+-00996         DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
+-00997 
+-00998         return 1;
+-00999 }
+-01000 
+-01007 static int get_device_speed(dwc_otg_core_if_t * core_if)
+-01008 {
+-01009         dsts_data_t dsts;
+-01010         int speed = 0;
+-01011         dsts.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts);
+-01012 
+-01013         switch (dsts.b.enumspd) {
+-01014         case DWC_DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ:
+-01015                 speed = USB_SPEED_HIGH;
+-01016                 break;
+-01017         case DWC_DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ:
+-01018         case DWC_DSTS_ENUMSPD_FS_PHY_48MHZ:
+-01019                 speed = USB_SPEED_FULL;
+-01020                 break;
+-01021 
+-01022         case DWC_DSTS_ENUMSPD_LS_PHY_6MHZ:
+-01023                 speed = USB_SPEED_LOW;
+-01024                 break;
+-01025         }
+-01026 
+-01027         return speed;
+-01028 }
+-01029 
+-01035 int32_t dwc_otg_pcd_handle_enum_done_intr(dwc_otg_pcd_t * pcd)
+-01036 {
+-01037         dwc_otg_pcd_ep_t *ep0 = &pcd->ep0;
+-01038         gintsts_data_t gintsts;
+-01039         gusbcfg_data_t gusbcfg;
+-01040         dwc_otg_core_global_regs_t *global_regs =
+-01041             GET_CORE_IF(pcd)->core_global_regs;
+-01042         uint8_t utmi16b, utmi8b;
+-01043         int speed;
+-01044         DWC_DEBUGPL(DBG_PCD, "SPEED ENUM\n");
+-01045 
+-01046         if (GET_CORE_IF(pcd)->snpsid >= OTG_CORE_REV_2_60a) {
+-01047                 utmi16b = 6;    //vahrama old value was 6;
+-01048                 utmi8b = 9;
+-01049         } else {
+-01050                 utmi16b = 4;
+-01051                 utmi8b = 8;
+-01052         }
+-01053         dwc_otg_ep0_activate(GET_CORE_IF(pcd), &ep0->dwc_ep);
+-01054 
+-01055 #ifdef DEBUG_EP0
+-01056         print_ep0_state(pcd);
+-01057 #endif
+-01058 
+-01059         if (pcd->ep0state == EP0_DISCONNECT) {
+-01060                 pcd->ep0state = EP0_IDLE;
+-01061         } else if (pcd->ep0state == EP0_STALL) {
+-01062                 pcd->ep0state = EP0_IDLE;
+-01063         }
+-01064 
+-01065         pcd->ep0state = EP0_IDLE;
+-01066 
+-01067         ep0->stopped = 0;
+-01068 
+-01069         speed = get_device_speed(GET_CORE_IF(pcd));
+-01070         pcd->fops->connect(pcd, speed);
+-01071 
+-01072         /* Set USB turnaround time based on device speed and PHY interface. */
+-01073         gusbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg);
+-01074         if (speed == USB_SPEED_HIGH) {
+-01075                 if (GET_CORE_IF(pcd)->hwcfg2.b.hs_phy_type ==
+-01076                     DWC_HWCFG2_HS_PHY_TYPE_ULPI) {
+-01077                         /* ULPI interface */
+-01078                         gusbcfg.b.usbtrdtim = 9;
+-01079                 }
+-01080                 if (GET_CORE_IF(pcd)->hwcfg2.b.hs_phy_type ==
+-01081                     DWC_HWCFG2_HS_PHY_TYPE_UTMI) {
+-01082                         /* UTMI+ interface */
+-01083                         if (GET_CORE_IF(pcd)->hwcfg4.b.utmi_phy_data_width == 0) {
+-01084                                 gusbcfg.b.usbtrdtim = utmi8b;
+-01085                         } else if (GET_CORE_IF(pcd)->hwcfg4.
+-01086                                    b.utmi_phy_data_width == 1) {
+-01087                                 gusbcfg.b.usbtrdtim = utmi16b;
+-01088                         } else if (GET_CORE_IF(pcd)->
+-01089                                    core_params->phy_utmi_width == 8) {
+-01090                                 gusbcfg.b.usbtrdtim = utmi8b;
+-01091                         } else {
+-01092                                 gusbcfg.b.usbtrdtim = utmi16b;
+-01093                         }
+-01094                 }
+-01095                 if (GET_CORE_IF(pcd)->hwcfg2.b.hs_phy_type ==
+-01096                     DWC_HWCFG2_HS_PHY_TYPE_UTMI_ULPI) {
+-01097                         /* UTMI+  OR  ULPI interface */
+-01098                         if (gusbcfg.b.ulpi_utmi_sel == 1) {
+-01099                                 /* ULPI interface */
+-01100                                 gusbcfg.b.usbtrdtim = 9;
+-01101                         } else {
+-01102                                 /* UTMI+ interface */
+-01103                                 if (GET_CORE_IF(pcd)->
+-01104                                     core_params->phy_utmi_width == 16) {
+-01105                                         gusbcfg.b.usbtrdtim = utmi16b;
+-01106                                 } else {
+-01107                                         gusbcfg.b.usbtrdtim = utmi8b;
+-01108                                 }
+-01109                         }
+-01110                 }
+-01111         } else {
+-01112                 /* Full or low speed */
+-01113                 gusbcfg.b.usbtrdtim = 9;
+-01114         }
+-01115         DWC_WRITE_REG32(&global_regs->gusbcfg, gusbcfg.d32);
+-01116 
+-01117         /* Clear interrupt */
+-01118         gintsts.d32 = 0;
+-01119         gintsts.b.enumdone = 1;
+-01120         DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
+-01121                         gintsts.d32);
+-01122         return 1;
+-01123 }
+-01124 
+-01130 int32_t dwc_otg_pcd_handle_isoc_out_packet_dropped_intr(dwc_otg_pcd_t * pcd)
+-01131 {
+-01132         gintmsk_data_t intr_mask = {.d32 = 0 };
+-01133         gintsts_data_t gintsts;
+-01134 
+-01135         DWC_WARN("INTERRUPT Handler not implemented for %s\n",
+-01136                  "ISOC Out Dropped");
+-01137 
+-01138         intr_mask.b.isooutdrop = 1;
+-01139         DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk,
+-01140                          intr_mask.d32, 0);
+-01141 
+-01142         /* Clear interrupt */
+-01143         gintsts.d32 = 0;
+-01144         gintsts.b.isooutdrop = 1;
+-01145         DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
+-01146                         gintsts.d32);
+-01147 
+-01148         return 1;
+-01149 }
+-01150 
+-01156 int32_t dwc_otg_pcd_handle_end_periodic_frame_intr(dwc_otg_pcd_t * pcd)
+-01157 {
+-01158         gintmsk_data_t intr_mask = {.d32 = 0 };
+-01159         gintsts_data_t gintsts;
+-01160         DWC_PRINTF("INTERRUPT Handler not implemented for %s\n", "EOP");
+-01161 
+-01162         intr_mask.b.eopframe = 1;
+-01163         DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk,
+-01164                          intr_mask.d32, 0);
+-01165 
+-01166         /* Clear interrupt */
+-01167         gintsts.d32 = 0;
+-01168         gintsts.b.eopframe = 1;
+-01169         DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
+-01170                         gintsts.d32);
+-01171 
+-01172         return 1;
+-01173 }
+-01174 
+-01184 int32_t dwc_otg_pcd_handle_ep_mismatch_intr(dwc_otg_pcd_t * pcd)
+-01185 {
+-01186         gintsts_data_t gintsts;
+-01187         dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
+-01188         dctl_data_t dctl;
+-01189         gintmsk_data_t intr_mask = {.d32 = 0 };
+-01190 
+-01191         if (!core_if->en_multiple_tx_fifo && core_if->dma_enable) {
+-01192                 core_if->start_predict = 1;
+-01193         
+-01194                 DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, core_if);
+-01195         
+-01196                 gintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts);
+-01197                 if (!gintsts.b.ginnakeff) {
+-01198                         /* Disable EP Mismatch interrupt */
+-01199                         intr_mask.d32 = 0;
+-01200                         intr_mask.b.epmismatch = 1;
+-01201                         DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, intr_mask.d32, 0);
+-01202                         /* Enable the Global IN NAK Effective Interrupt */
+-01203                         intr_mask.d32 = 0;
+-01204                         intr_mask.b.ginnakeff = 1;
+-01205                         DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, 0, intr_mask.d32);
+-01206                         /* Set the global non-periodic IN NAK handshake */
+-01207                         dctl.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dctl);
+-01208                         dctl.b.sgnpinnak = 1;
+-01209                         DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32);
+-01210                 } else {
+-01211                         DWC_PRINTF("gintsts.b.ginnakeff = 1! dctl.b.sgnpinnak not set\n");
+-01212                 }
+-01213                 /* Disabling of all EP's will be done in dwc_otg_pcd_handle_in_nak_effective()
+-01214                  * handler after Global IN NAK Effective interrupt will be asserted */
+-01215         }
+-01216         /* Clear interrupt */
+-01217         gintsts.d32 = 0;
+-01218         gintsts.b.epmismatch = 1;
+-01219         DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
+-01220 
+-01221         return 1;
+-01222 }
+-01223 
+-01232 int32_t dwc_otg_pcd_handle_ep_fetsusp_intr(dwc_otg_pcd_t * pcd)
+-01233 {
+-01234         gintsts_data_t gintsts;
+-01235         gintmsk_data_t gintmsk_data;
+-01236         dctl_data_t dctl;
+-01237         dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
+-01238         DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, core_if);
+-01239         
+-01240         /* Clear the global non-periodic IN NAK handshake */
+-01241         dctl.d32 = 0;
+-01242         dctl.b.cgnpinnak = 1;
+-01243         DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32, dctl.d32); 
+-01244         
+-01245         /* Mask GINTSTS.FETSUSP interrupt */
+-01246         gintmsk_data.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintmsk);
+-01247         gintmsk_data.b.fetsusp = 0;
+-01248         DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, gintmsk_data.d32);
+-01249 
+-01250         /* Clear interrupt */
+-01251         gintsts.d32 = 0;
+-01252         gintsts.b.fetsusp = 1;
+-01253         DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
+-01254 
+-01255         return 1;
+-01256 }
+-01260 static inline void ep0_do_stall(dwc_otg_pcd_t * pcd, const int err_val)
+-01261 {
+-01262         dwc_otg_pcd_ep_t *ep0 = &pcd->ep0;
+-01263         usb_device_request_t *ctrl = &pcd->setup_pkt->req;
+-01264         DWC_WARN("req %02x.%02x protocol STALL; err %d\n",
+-01265                  ctrl->bmRequestType, ctrl->bRequest, err_val);
+-01266 
+-01267         ep0->dwc_ep.is_in = 1;
+-01268         dwc_otg_ep_set_stall(GET_CORE_IF(pcd), &ep0->dwc_ep);
+-01269         pcd->ep0.stopped = 1;
+-01270         pcd->ep0state = EP0_IDLE;
+-01271         ep0_out_start(GET_CORE_IF(pcd), pcd);
+-01272 }
+-01273 
+-01277 static inline void do_gadget_setup(dwc_otg_pcd_t * pcd,
+-01278                                    usb_device_request_t * ctrl)
+-01279 {
+-01280         int ret = 0;
+-01281         DWC_SPINUNLOCK(pcd->lock);
+-01282         ret = pcd->fops->setup(pcd, (uint8_t *) ctrl);
+-01283         DWC_SPINLOCK(pcd->lock);
+-01284         if (ret < 0) {
+-01285                 ep0_do_stall(pcd, ret);
+-01286         }
+-01287 
+-01300         if (ret == 256 + 999) {
+-01301                 pcd->request_config = 1;
+-01302         }
+-01303 }
+-01304 
+-01305 #ifdef DWC_UTE_CFI
+-01306 
+-01310 static inline int cfi_gadget_setup(dwc_otg_pcd_t * pcd,
+-01311                                    struct cfi_usb_ctrlrequest *ctrl_req)
+-01312 {
+-01313         int ret = 0;
+-01314 
+-01315         if (pcd->fops && pcd->fops->cfi_setup) {
+-01316                 DWC_SPINUNLOCK(pcd->lock);
+-01317                 ret = pcd->fops->cfi_setup(pcd, ctrl_req);
+-01318                 DWC_SPINLOCK(pcd->lock);
+-01319                 if (ret < 0) {
+-01320                         ep0_do_stall(pcd, ret);
+-01321                         return ret;
+-01322                 }
+-01323         }
+-01324 
+-01325         return ret;
+-01326 }
+-01327 #endif
+-01328 
+-01333 static inline void do_setup_in_status_phase(dwc_otg_pcd_t * pcd)
+-01334 {
+-01335         dwc_otg_pcd_ep_t *ep0 = &pcd->ep0;
+-01336         if (pcd->ep0state == EP0_STALL) {
+-01337                 return;
+-01338         }
+-01339 
+-01340         pcd->ep0state = EP0_IN_STATUS_PHASE;
+-01341 
+-01342         /* Prepare for more SETUP Packets */
+-01343         DWC_DEBUGPL(DBG_PCD, "EP0 IN ZLP\n");
+-01344         ep0->dwc_ep.xfer_len = 0;
+-01345         ep0->dwc_ep.xfer_count = 0;
+-01346         ep0->dwc_ep.is_in = 1;
+-01347         ep0->dwc_ep.dma_addr = pcd->setup_pkt_dma_handle;
+-01348         dwc_otg_ep0_start_transfer(GET_CORE_IF(pcd), &ep0->dwc_ep);
+-01349 
+-01350         /* Prepare for more SETUP Packets */
+-01351         //ep0_out_start(GET_CORE_IF(pcd), pcd);
+-01352 }
+-01353 
+-01358 static inline void do_setup_out_status_phase(dwc_otg_pcd_t * pcd)
+-01359 {
+-01360         dwc_otg_pcd_ep_t *ep0 = &pcd->ep0;
+-01361         if (pcd->ep0state == EP0_STALL) {
+-01362                 DWC_DEBUGPL(DBG_PCD, "EP0 STALLED\n");
+-01363                 return;
+-01364         }
+-01365         pcd->ep0state = EP0_OUT_STATUS_PHASE;
+-01366 
+-01367         DWC_DEBUGPL(DBG_PCD, "EP0 OUT ZLP\n");
+-01368         ep0->dwc_ep.xfer_len = 0;
+-01369         ep0->dwc_ep.xfer_count = 0;
+-01370         ep0->dwc_ep.is_in = 0;
+-01371         ep0->dwc_ep.dma_addr = pcd->setup_pkt_dma_handle;
+-01372         dwc_otg_ep0_start_transfer(GET_CORE_IF(pcd), &ep0->dwc_ep);
+-01373 
+-01374         /* Prepare for more SETUP Packets */
+-01375         if (GET_CORE_IF(pcd)->dma_enable == 0) {
+-01376                 ep0_out_start(GET_CORE_IF(pcd), pcd);
+-01377         }
+-01378 }
+-01379 
+-01384 static inline void pcd_clear_halt(dwc_otg_pcd_t * pcd, dwc_otg_pcd_ep_t * ep)
+-01385 {
+-01386         if (ep->dwc_ep.stall_clear_flag == 0)
+-01387                 dwc_otg_ep_clear_stall(GET_CORE_IF(pcd), &ep->dwc_ep);
+-01388 
+-01389         /* Reactive the EP */
+-01390         dwc_otg_ep_activate(GET_CORE_IF(pcd), &ep->dwc_ep);
+-01391         if (ep->stopped) {
+-01392                 ep->stopped = 0;
+-01393                 /* If there is a request in the EP queue start it */
+-01394 
+-01398                 /*
+-01399                  * Above fixme is solved by implmenting a tasklet to call the
+-01400                  * start_next_request(), outside of interrupt context at some
+-01401                  * time after the current time, after a clear-halt setup packet.
+-01402                  * Still need to implement ep mismatch in the future if a gadget
+-01403                  * ever uses more than one endpoint at once
+-01404                  */
+-01405                 ep->queue_sof = 1;
+-01406                 DWC_TASK_SCHEDULE(pcd->start_xfer_tasklet);
+-01407         }
+-01408         /* Start Control Status Phase */
+-01409         do_setup_in_status_phase(pcd);
+-01410 }
+-01411 
+-01423 void do_test_mode(void *data)
+-01424 {
+-01425         dctl_data_t dctl;
+-01426         dwc_otg_pcd_t *pcd = (dwc_otg_pcd_t *) data;
+-01427         dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
+-01428         int test_mode = pcd->test_mode;
+-01429 
+-01430 //        DWC_WARN("%s() has not been tested since being rewritten!\n", __func__);
+-01431 
+-01432         dctl.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dctl);
+-01433         switch (test_mode) {
+-01434         case 1:         // TEST_J
+-01435                 dctl.b.tstctl = 1;
+-01436                 break;
+-01437 
+-01438         case 2:         // TEST_K
+-01439                 dctl.b.tstctl = 2;
+-01440                 break;
+-01441 
+-01442         case 3:         // TEST_SE0_NAK
+-01443                 dctl.b.tstctl = 3;
+-01444                 break;
+-01445 
+-01446         case 4:         // TEST_PACKET
+-01447                 dctl.b.tstctl = 4;
+-01448                 break;
+-01449 
+-01450         case 5:         // TEST_FORCE_ENABLE
+-01451                 dctl.b.tstctl = 5;
+-01452                 break;
+-01453         }
+-01454         DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32);
+-01455 }
+-01456 
+-01460 static inline void do_get_status(dwc_otg_pcd_t * pcd)
+-01461 {
+-01462         usb_device_request_t ctrl = pcd->setup_pkt->req;
+-01463         dwc_otg_pcd_ep_t *ep;
+-01464         dwc_otg_pcd_ep_t *ep0 = &pcd->ep0;
+-01465         uint16_t *status = pcd->status_buf;
+-01466         dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
+-01467 
+-01468 #ifdef DEBUG_EP0
+-01469         DWC_DEBUGPL(DBG_PCD,
+-01470                     "GET_STATUS %02x.%02x v%04x i%04x l%04x\n",
+-01471                     ctrl.bmRequestType, ctrl.bRequest,
+-01472                     UGETW(ctrl.wValue), UGETW(ctrl.wIndex),
+-01473                     UGETW(ctrl.wLength));
+-01474 #endif
+-01475 
+-01476         switch (UT_GET_RECIPIENT(ctrl.bmRequestType)) {
+-01477         case UT_DEVICE:
+-01478                 if(UGETW(ctrl.wIndex) == 0xF000) { /* OTG Status selector */
+-01479                         DWC_PRINTF("wIndex - %d\n", UGETW(ctrl.wIndex));
+-01480                         DWC_PRINTF("OTG VERSION - %d\n", core_if->otg_ver);
+-01481                         DWC_PRINTF("OTG CAP - %d, %d\n", core_if->core_params->otg_cap,
+-01482                                                 DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE);
+-01483                         if(core_if->otg_ver == 1 && 
+-01484                         core_if->core_params->otg_cap == DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE) {
+-01485                                 uint8_t *otgsts = (uint8_t*)pcd->status_buf;
+-01486                                 *otgsts = (core_if->otg_sts & 0x1);
+-01487                                 pcd->ep0_pending = 1;
+-01488                                 ep0->dwc_ep.start_xfer_buff = (uint8_t *) otgsts;
+-01489                                 ep0->dwc_ep.xfer_buff = (uint8_t *) otgsts;
+-01490                                 ep0->dwc_ep.dma_addr = pcd->status_buf_dma_handle;
+-01491                                 ep0->dwc_ep.xfer_len = 1;
+-01492                                 ep0->dwc_ep.xfer_count = 0;
+-01493                                 ep0->dwc_ep.total_len = ep0->dwc_ep.xfer_len;
+-01494                                 dwc_otg_ep0_start_transfer(GET_CORE_IF(pcd), &ep0->dwc_ep);
+-01495                                 return;
+-01496                         } else {
+-01497                                 ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED);
+-01498                                 return;
+-01499                         }
+-01500                         break;
+-01501                 } else {
+-01502                         *status = 0x1;  /* Self powered */
+-01503                         *status |= pcd->remote_wakeup_enable << 1;
+-01504                         break;
+-01505                 }
+-01506         case UT_INTERFACE:
+-01507                 *status = 0;
+-01508                 break;
+-01509 
+-01510         case UT_ENDPOINT:
+-01511                 ep = get_ep_by_addr(pcd, UGETW(ctrl.wIndex));
+-01512                 if (ep == 0 || UGETW(ctrl.wLength) > 2) {
+-01513                         ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED);
+-01514                         return;
+-01515                 }
+-01517                 *status = ep->stopped;
+-01518                 break;
+-01519         }
+-01520         pcd->ep0_pending = 1;
+-01521         ep0->dwc_ep.start_xfer_buff = (uint8_t *) status;
+-01522         ep0->dwc_ep.xfer_buff = (uint8_t *) status;
+-01523         ep0->dwc_ep.dma_addr = pcd->status_buf_dma_handle;
+-01524         ep0->dwc_ep.xfer_len = 2;
+-01525         ep0->dwc_ep.xfer_count = 0;
+-01526         ep0->dwc_ep.total_len = ep0->dwc_ep.xfer_len;
+-01527         dwc_otg_ep0_start_transfer(GET_CORE_IF(pcd), &ep0->dwc_ep);
+-01528 }
+-01529 
+-01533 static inline void do_set_feature(dwc_otg_pcd_t * pcd)
+-01534 {
+-01535         dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
+-01536         dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
+-01537         usb_device_request_t ctrl = pcd->setup_pkt->req;
+-01538         dwc_otg_pcd_ep_t *ep = 0;
+-01539         int32_t otg_cap_param = core_if->core_params->otg_cap;
+-01540         gotgctl_data_t gotgctl = {.d32 = 0 };
+-01541 
+-01542         DWC_DEBUGPL(DBG_PCD, "SET_FEATURE:%02x.%02x v%04x i%04x l%04x\n",
+-01543                     ctrl.bmRequestType, ctrl.bRequest,
+-01544                     UGETW(ctrl.wValue), UGETW(ctrl.wIndex),
+-01545                     UGETW(ctrl.wLength));
+-01546         DWC_DEBUGPL(DBG_PCD, "otg_cap=%d\n", otg_cap_param);
+-01547 
+-01548         switch (UT_GET_RECIPIENT(ctrl.bmRequestType)) {
+-01549         case UT_DEVICE:
+-01550                 switch (UGETW(ctrl.wValue)) {
+-01551                 case UF_DEVICE_REMOTE_WAKEUP:
+-01552                         pcd->remote_wakeup_enable = 1;
+-01553                         break;
+-01554 
+-01555                 case UF_TEST_MODE:
+-01556                         /* Setup the Test Mode tasklet to do the Test
+-01557                          * Packet generation after the SETUP Status
+-01558                          * phase has completed. */
+-01559 
+-01563                         pcd->test_mode = UGETW(ctrl.wIndex) >> 8;
+-01564                         DWC_TASK_SCHEDULE(pcd->test_mode_tasklet);
+-01565                         break;
+-01566 
+-01567                 case UF_DEVICE_B_HNP_ENABLE:
+-01568                         DWC_DEBUGPL(DBG_PCDV,
+-01569                                     "SET_FEATURE: USB_DEVICE_B_HNP_ENABLE\n");
+-01570 
+-01571                         /* dev may initiate HNP */
+-01572                         if (otg_cap_param == DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE) {
+-01573                                 pcd->b_hnp_enable = 1;
+-01574                                 dwc_otg_pcd_update_otg(pcd, 0);
+-01575                                 DWC_DEBUGPL(DBG_PCD, "Request B HNP\n");
+-01578                                 gotgctl.b.devhnpen = 1;
+-01579                                 gotgctl.b.hnpreq = 1;
+-01580                                 DWC_WRITE_REG32(&global_regs->gotgctl,
+-01581                                                 gotgctl.d32);
+-01582                         } else {
+-01583                                 ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED);
+-01584                                 return;
+-01585                         }
+-01586                         break;
+-01587 
+-01588                 case UF_DEVICE_A_HNP_SUPPORT:
+-01589                         /* RH port supports HNP */
+-01590                         DWC_DEBUGPL(DBG_PCDV,
+-01591                                     "SET_FEATURE: USB_DEVICE_A_HNP_SUPPORT\n");
+-01592                         if (otg_cap_param == DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE) {
+-01593                                 pcd->a_hnp_support = 1;
+-01594                                 dwc_otg_pcd_update_otg(pcd, 0);
+-01595                         } else {
+-01596                                 ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED);
+-01597                                 return;
+-01598                         }
+-01599                         break;
+-01600 
+-01601                 case UF_DEVICE_A_ALT_HNP_SUPPORT:
+-01602                         /* other RH port does */
+-01603                         DWC_DEBUGPL(DBG_PCDV,
+-01604                                     "SET_FEATURE: USB_DEVICE_A_ALT_HNP_SUPPORT\n");
+-01605                         if (otg_cap_param == DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE) {
+-01606                                 pcd->a_alt_hnp_support = 1;
+-01607                                 dwc_otg_pcd_update_otg(pcd, 0);
+-01608                         } else {
+-01609                                 ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED);
+-01610                                 return;
+-01611                         }
+-01612                         break;
+-01613 
+-01614                 default:
+-01615                         ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED);
+-01616                         return;
+-01617 
+-01618                 }
+-01619                 do_setup_in_status_phase(pcd);
+-01620                 break;
+-01621 
+-01622         case UT_INTERFACE:
+-01623                 do_gadget_setup(pcd, &ctrl);
+-01624                 break;
+-01625 
+-01626         case UT_ENDPOINT:
+-01627                 if (UGETW(ctrl.wValue) == UF_ENDPOINT_HALT) {
+-01628                         ep = get_ep_by_addr(pcd, UGETW(ctrl.wIndex));
+-01629                         if (ep == 0) {
+-01630                                 ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED);
+-01631                                 return;
+-01632                         }
+-01633                         ep->stopped = 1;
+-01634                         dwc_otg_ep_set_stall(core_if, &ep->dwc_ep);
+-01635                 }
+-01636                 do_setup_in_status_phase(pcd);
+-01637                 break;
+-01638         }
+-01639 }
+-01640 
+-01644 static inline void do_clear_feature(dwc_otg_pcd_t * pcd)
+-01645 {
+-01646         usb_device_request_t ctrl = pcd->setup_pkt->req;
+-01647         dwc_otg_pcd_ep_t *ep = 0;
+-01648 
+-01649         DWC_DEBUGPL(DBG_PCD,
+-01650                     "CLEAR_FEATURE:%02x.%02x v%04x i%04x l%04x\n",
+-01651                     ctrl.bmRequestType, ctrl.bRequest,
+-01652                     UGETW(ctrl.wValue), UGETW(ctrl.wIndex),
+-01653                     UGETW(ctrl.wLength));
+-01654 
+-01655         switch (UT_GET_RECIPIENT(ctrl.bmRequestType)) {
+-01656         case UT_DEVICE:
+-01657                 switch (UGETW(ctrl.wValue)) {
+-01658                 case UF_DEVICE_REMOTE_WAKEUP:
+-01659                         pcd->remote_wakeup_enable = 0;
+-01660                         break;
+-01661 
+-01662                 case UF_TEST_MODE:
+-01664                         break;
+-01665 
+-01666                 default:
+-01667                         ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED);
+-01668                         return;
+-01669                 }
+-01670                 do_setup_in_status_phase(pcd);
+-01671                 break;
+-01672 
+-01673         case UT_ENDPOINT:
+-01674                 ep = get_ep_by_addr(pcd, UGETW(ctrl.wIndex));
+-01675                 if (ep == 0) {
+-01676                         ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED);
+-01677                         return;
+-01678                 }
+-01679 
+-01680                 pcd_clear_halt(pcd, ep);
+-01681 
+-01682                 break;
+-01683         }
+-01684 }
+-01685 
+-01689 static inline void do_set_address(dwc_otg_pcd_t * pcd)
+-01690 {
+-01691         dwc_otg_dev_if_t *dev_if = GET_CORE_IF(pcd)->dev_if;
+-01692         usb_device_request_t ctrl = pcd->setup_pkt->req;
+-01693 
+-01694         if (ctrl.bmRequestType == UT_DEVICE) {
+-01695                 dcfg_data_t dcfg = {.d32 = 0 };
+-01696 
+-01697 #ifdef DEBUG_EP0
+-01698 //                      DWC_DEBUGPL(DBG_PCDV, "SET_ADDRESS:%d\n", ctrl.wValue);
+-01699 #endif
+-01700                 dcfg.b.devaddr = UGETW(ctrl.wValue);
+-01701                 DWC_MODIFY_REG32(&dev_if->dev_global_regs->dcfg, 0, dcfg.d32);
+-01702                 do_setup_in_status_phase(pcd);
+-01703         }
+-01704 }
+-01705 
+-01756 static inline void pcd_setup(dwc_otg_pcd_t * pcd)
+-01757 {
+-01758         dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
+-01759         dwc_otg_dev_if_t *dev_if = core_if->dev_if;
+-01760         usb_device_request_t ctrl = pcd->setup_pkt->req;
+-01761         dwc_otg_pcd_ep_t *ep0 = &pcd->ep0;
+-01762 
+-01763         deptsiz0_data_t doeptsize0 = {.d32 = 0 };
+-01764 
+-01765 #ifdef DWC_UTE_CFI
+-01766         int retval = 0;
+-01767         struct cfi_usb_ctrlrequest cfi_req;
+-01768 #endif
+-01769 
+-01770 #ifdef DEBUG_EP0
+-01771         DWC_DEBUGPL(DBG_PCD, "SETUP %02x.%02x v%04x i%04x l%04x\n",
+-01772                     ctrl.bmRequestType, ctrl.bRequest,
+-01773                     UGETW(ctrl.wValue), UGETW(ctrl.wIndex),
+-01774                     UGETW(ctrl.wLength));
+-01775 #endif
+-01776 
+-01777         doeptsize0.d32 = DWC_READ_REG32(&dev_if->out_ep_regs[0]->doeptsiz);
+-01778 
+-01781         if (core_if->dma_enable && core_if->dma_desc_enable == 0
+-01782             && (doeptsize0.b.supcnt < 2)) {
+-01783                 DWC_ERROR
+-01784                     ("\n\n-----------    CANNOT handle > 1 setup packet in DMA mode\n\n");
+-01785         }
+-01786 
+-01787         /* Clean up the request queue */
+-01788         dwc_otg_request_nuke(ep0);
+-01789         ep0->stopped = 0;
+-01790 
+-01791         if (ctrl.bmRequestType & UE_DIR_IN) {
+-01792                 ep0->dwc_ep.is_in = 1;
+-01793                 pcd->ep0state = EP0_IN_DATA_PHASE;
+-01794         } else {
+-01795                 ep0->dwc_ep.is_in = 0;
+-01796                 pcd->ep0state = EP0_OUT_DATA_PHASE;
+-01797         }
+-01798 
+-01799         if (UGETW(ctrl.wLength) == 0) {
+-01800                 ep0->dwc_ep.is_in = 1;
+-01801                 pcd->ep0state = EP0_IN_STATUS_PHASE;
+-01802         }
+-01803 
+-01804         if (UT_GET_TYPE(ctrl.bmRequestType) != UT_STANDARD) {
+-01805 
+-01806 #ifdef DWC_UTE_CFI
+-01807                 DWC_MEMCPY(&cfi_req, &ctrl, sizeof(usb_device_request_t));
+-01808 
+-01809                 //printk(KERN_ALERT "CFI: req_type=0x%02x; req=0x%02x\n", 
+-01810                                 ctrl.bRequestType, ctrl.bRequest);
+-01811                 if (UT_GET_TYPE(cfi_req.bRequestType) == UT_VENDOR) {
+-01812                         if (cfi_req.bRequest > 0xB0 && cfi_req.bRequest < 0xBF) {
+-01813                                 retval = cfi_setup(pcd, &cfi_req);
+-01814                                 if (retval < 0) {
+-01815                                         ep0_do_stall(pcd, retval);
+-01816                                         pcd->ep0_pending = 0;
+-01817                                         return;
+-01818                                 }
+-01819 
+-01820                                 /* if need gadget setup then call it and check the retval */
+-01821                                 if (pcd->cfi->need_gadget_att) {
+-01822                                         retval =
+-01823                                             cfi_gadget_setup(pcd,
+-01824                                                              &pcd->
+-01825                                                              cfi->ctrl_req);
+-01826                                         if (retval < 0) {
+-01827                                                 pcd->ep0_pending = 0;
+-01828                                                 return;
+-01829                                         }
+-01830                                 }
+-01831 
+-01832                                 if (pcd->cfi->need_status_in_complete) {
+-01833                                         do_setup_in_status_phase(pcd);
+-01834                                 }
+-01835                                 return;
+-01836                         }
+-01837                 }
+-01838 #endif
+-01839 
+-01840                 /* handle non-standard (class/vendor) requests in the gadget driver */
+-01841                 do_gadget_setup(pcd, &ctrl);
+-01842                 return;
+-01843         }
+-01844 
+-01847 
+-01848 
+-01849 
+-01850         switch (ctrl.bRequest) {
+-01851         case UR_GET_STATUS:
+-01852                 do_get_status(pcd);
+-01853                 break;
+-01854 
+-01855         case UR_CLEAR_FEATURE:
+-01856                 do_clear_feature(pcd);
+-01857                 break;
+-01858 
+-01859         case UR_SET_FEATURE:
+-01860                 do_set_feature(pcd);
+-01861                 break;
+-01862 
+-01863         case UR_SET_ADDRESS:
+-01864                 do_set_address(pcd);
+-01865                 break;
+-01866 
+-01867         case UR_SET_INTERFACE:
+-01868         case UR_SET_CONFIG:
+-01869 //              _pcd->request_config = 1;       /* Configuration changed */
+-01870                 do_gadget_setup(pcd, &ctrl);
+-01871                 break;
+-01872 
+-01873         case UR_SYNCH_FRAME:
+-01874                 do_gadget_setup(pcd, &ctrl);
+-01875                 break;
+-01876 
+-01877         default:
+-01878                 /* Call the Gadget Driver's setup functions */
+-01879                 do_gadget_setup(pcd, &ctrl);
+-01880                 break;
+-01881         }
+-01882 }
+-01883 
+-01887 static int32_t ep0_complete_request(dwc_otg_pcd_ep_t * ep)
+-01888 {
+-01889         dwc_otg_core_if_t *core_if = GET_CORE_IF(ep->pcd);
+-01890         dwc_otg_dev_if_t *dev_if = core_if->dev_if;
+-01891         dwc_otg_dev_in_ep_regs_t *in_ep_regs =
+-01892             dev_if->in_ep_regs[ep->dwc_ep.num];
+-01893 #ifdef DEBUG_EP0
+-01894         dwc_otg_dev_out_ep_regs_t *out_ep_regs =
+-01895             dev_if->out_ep_regs[ep->dwc_ep.num];
+-01896 #endif
+-01897         deptsiz0_data_t deptsiz;
+-01898         dev_dma_desc_sts_t desc_sts;
+-01899         dwc_otg_pcd_request_t *req;
+-01900         int is_last = 0;
+-01901         dwc_otg_pcd_t *pcd = ep->pcd;
+-01902 
+-01903 #ifdef DWC_UTE_CFI
+-01904         struct cfi_usb_ctrlrequest *ctrlreq;
+-01905         int retval = -DWC_E_NOT_SUPPORTED;
+-01906 #endif
+-01907 
+-01908         if (pcd->ep0_pending && DWC_CIRCLEQ_EMPTY(&ep->queue)) {
+-01909                 if (ep->dwc_ep.is_in) {
+-01910 #ifdef DEBUG_EP0
+-01911                         DWC_DEBUGPL(DBG_PCDV, "Do setup OUT status phase\n");
+-01912 #endif
+-01913                         do_setup_out_status_phase(pcd);
+-01914                 } else {
+-01915 #ifdef DEBUG_EP0
+-01916                         DWC_DEBUGPL(DBG_PCDV, "Do setup IN status phase\n");
+-01917 #endif
+-01918 
+-01919 #ifdef DWC_UTE_CFI
+-01920                         ctrlreq = &pcd->cfi->ctrl_req;
+-01921 
+-01922                         if (UT_GET_TYPE(ctrlreq->bRequestType) == UT_VENDOR) {
+-01923                                 if (ctrlreq->bRequest > 0xB0
+-01924                                     && ctrlreq->bRequest < 0xBF) {
+-01925 
+-01926                                         /* Return if the PCD failed to handle the request */
+-01927                                         if ((retval =
+-01928                                              pcd->cfi->ops.
+-01929                                              ctrl_write_complete(pcd->cfi,
+-01930                                                                  pcd)) < 0) {
+-01931                                                 CFI_INFO
+-01932                                                     ("ERROR setting a new value in the PCD(%d)\n",
+-01933                                                      retval);
+-01934                                                 ep0_do_stall(pcd, retval);
+-01935                                                 pcd->ep0_pending = 0;
+-01936                                                 return 0;
+-01937                                         }
+-01938 
+-01939                                         /* If the gadget needs to be notified on the request */
+-01940                                         if (pcd->cfi->need_gadget_att == 1) {
+-01941                                                 //retval = do_gadget_setup(pcd, &pcd->cfi->ctrl_req);
+-01942                                                 retval =
+-01943                                                     cfi_gadget_setup(pcd,
+-01944                                                                      &pcd->cfi->
+-01945                                                                      ctrl_req);
+-01946 
+-01947                                                 /* Return from the function if the gadget failed to process
+-01948                                                  * the request properly - this should never happen !!!
+-01949                                                  */
+-01950                                                 if (retval < 0) {
+-01951                                                         CFI_INFO
+-01952                                                             ("ERROR setting a new value in the gadget(%d)\n",
+-01953                                                              retval);
+-01954                                                         pcd->ep0_pending = 0;
+-01955                                                         return 0;
+-01956                                                 }
+-01957                                         }
+-01958 
+-01959                                         CFI_INFO("%s: RETVAL=%d\n", __func__,
+-01960                                                  retval);
+-01961                                         /* If we hit here then the PCD and the gadget has properly
+-01962                                          * handled the request - so send the ZLP IN to the host.
+-01963                                          */
+-01964                                         /* @todo: MAS - decide whether we need to start the setup
+-01965                                          * stage based on the need_setup value of the cfi object
+-01966                                          */
+-01967                                         do_setup_in_status_phase(pcd);
+-01968                                         pcd->ep0_pending = 0;
+-01969                                         return 1;
+-01970                                 }
+-01971                         }
+-01972 #endif
+-01973 
+-01974                         do_setup_in_status_phase(pcd);
+-01975                 }
+-01976                 pcd->ep0_pending = 0;
+-01977                 return 1;
+-01978         }
+-01979 
+-01980         if (DWC_CIRCLEQ_EMPTY(&ep->queue)) {
+-01981                 return 0;
+-01982         }
+-01983         req = DWC_CIRCLEQ_FIRST(&ep->queue);
+-01984 
+-01985         if (pcd->ep0state == EP0_OUT_STATUS_PHASE
+-01986             || pcd->ep0state == EP0_IN_STATUS_PHASE) {
+-01987                 is_last = 1;
+-01988         } else if (ep->dwc_ep.is_in) {
+-01989                 deptsiz.d32 = DWC_READ_REG32(&in_ep_regs->dieptsiz);
+-01990                 if (core_if->dma_desc_enable != 0)
+-01991                         desc_sts = dev_if->in_desc_addr->status;
+-01992 #ifdef DEBUG_EP0
+-01993                 DWC_DEBUGPL(DBG_PCDV, "%d len=%d  xfersize=%d pktcnt=%d\n",
+-01994                             ep->dwc_ep.num, ep->dwc_ep.xfer_len,
+-01995                             deptsiz.b.xfersize, deptsiz.b.pktcnt);
+-01996 #endif
+-01997 
+-01998                 if (((core_if->dma_desc_enable == 0)
+-01999                      && (deptsiz.b.xfersize == 0))
+-02000                     || ((core_if->dma_desc_enable != 0)
+-02001                         && (desc_sts.b.bytes == 0))) {
+-02002                         req->actual = ep->dwc_ep.xfer_count;
+-02003                         /* Is a Zero Len Packet needed? */
+-02004                         if (req->sent_zlp) {
+-02005 #ifdef DEBUG_EP0
+-02006                                 DWC_DEBUGPL(DBG_PCD, "Setup Rx ZLP\n");
+-02007 #endif
+-02008                                 req->sent_zlp = 0;
+-02009                         }
+-02010                         do_setup_out_status_phase(pcd);
+-02011                 }
+-02012         } else {
+-02013                 /* ep0-OUT */
+-02014 #ifdef DEBUG_EP0
+-02015                 deptsiz.d32 = DWC_READ_REG32(&out_ep_regs->doeptsiz);
+-02016                 DWC_DEBUGPL(DBG_PCDV, "%d len=%d xsize=%d pktcnt=%d\n",
+-02017                             ep->dwc_ep.num, ep->dwc_ep.xfer_len,
+-02018                             deptsiz.b.xfersize, deptsiz.b.pktcnt);
+-02019 #endif
+-02020                 req->actual = ep->dwc_ep.xfer_count;
+-02021 
+-02022                 /* Is a Zero Len Packet needed? */
+-02023                 if (req->sent_zlp) {
+-02024 #ifdef DEBUG_EP0
+-02025                         DWC_DEBUGPL(DBG_PCDV, "Setup Tx ZLP\n");
+-02026 #endif
+-02027                         req->sent_zlp = 0;
+-02028                 }
+-02029                 if (core_if->dma_desc_enable == 0)
+-02030                         do_setup_in_status_phase(pcd);
+-02031         }
+-02032 
+-02033         /* Complete the request */
+-02034         if (is_last) {
+-02035                 dwc_otg_request_done(ep, req, 0);
+-02036                 ep->dwc_ep.start_xfer_buff = 0;
+-02037                 ep->dwc_ep.xfer_buff = 0;
+-02038                 ep->dwc_ep.xfer_len = 0;
+-02039                 return 1;
+-02040         }
+-02041         return 0;
+-02042 }
+-02043 
+-02044 #ifdef DWC_UTE_CFI
+-02045 
+-02051 static inline int cfi_calc_desc_residue(dwc_otg_pcd_ep_t * ep)
+-02052 {
+-02053         int32_t ret = 0;
+-02054         int i;
+-02055         struct dwc_otg_dma_desc *ddesc = NULL;
+-02056         struct cfi_ep *cfiep;
+-02057 
+-02058         /* See if the pcd_ep has its respective cfi_ep mapped */
+-02059         cfiep = get_cfi_ep_by_pcd_ep(ep->pcd->cfi, ep);
+-02060         if (!cfiep) {
+-02061                 CFI_INFO("%s: Failed to find ep\n", __func__);
+-02062                 return -1;
+-02063         }
+-02064 
+-02065         ddesc = ep->dwc_ep.descs;
+-02066 
+-02067         for (i = 0; (i < cfiep->desc_count) && (i < MAX_DMA_DESCS_PER_EP); i++) {
+-02068 
+-02069 #if defined(PRINT_CFI_DMA_DESCS)
+-02070                 print_desc(ddesc, ep->ep.name, i);
+-02071 #endif
+-02072                 ret += ddesc->status.b.bytes;
+-02073                 ddesc++;
+-02074         }
+-02075 
+-02076         if (ret)
+-02077                 CFI_INFO("!!!!!!!!!! WARNING (%s) - residue=%d\n", __func__,
+-02078                          ret);
+-02079 
+-02080         return ret;
+-02081 }
+-02082 #endif
+-02083 
+-02088 static void complete_ep(dwc_otg_pcd_ep_t * ep)
+-02089 {
+-02090         dwc_otg_core_if_t *core_if = GET_CORE_IF(ep->pcd);
+-02091         dwc_otg_dev_if_t *dev_if = core_if->dev_if;
+-02092         dwc_otg_dev_in_ep_regs_t *in_ep_regs =
+-02093             dev_if->in_ep_regs[ep->dwc_ep.num];
+-02094         deptsiz_data_t deptsiz;
+-02095         dev_dma_desc_sts_t desc_sts;
+-02096         dwc_otg_pcd_request_t *req = 0;
+-02097         dwc_otg_dev_dma_desc_t *dma_desc;
+-02098         uint32_t byte_count = 0;
+-02099         int is_last = 0;
+-02100         int i;
+-02101 
+-02102         DWC_DEBUGPL(DBG_PCDV, "%s() %d-%s\n", __func__, ep->dwc_ep.num,
+-02103                     (ep->dwc_ep.is_in ? "IN" : "OUT"));
+-02104 
+-02105         /* Get any pending requests */
+-02106         if (!DWC_CIRCLEQ_EMPTY(&ep->queue)) {
+-02107                 req = DWC_CIRCLEQ_FIRST(&ep->queue);
+-02108                 if (!req) {
+-02109                         DWC_PRINTF("complete_ep 0x%p, req = NULL!\n", ep);
+-02110                         return;
+-02111                 }
+-02112         } else {
+-02113                 DWC_PRINTF("complete_ep 0x%p, ep->queue empty!\n", ep);
+-02114                 return;
+-02115         }
+-02116 
+-02117         DWC_DEBUGPL(DBG_PCD, "Requests %d\n", ep->pcd->request_pending);
+-02118 
+-02119         if (ep->dwc_ep.is_in) {
+-02120                 deptsiz.d32 = DWC_READ_REG32(&in_ep_regs->dieptsiz);
+-02121 
+-02122                 if (core_if->dma_enable) {
+-02123                         if (core_if->dma_desc_enable == 0) {
+-02124                                 if (deptsiz.b.xfersize == 0
+-02125                                     && deptsiz.b.pktcnt == 0) {
+-02126                                         byte_count =
+-02127                                             ep->dwc_ep.xfer_len -
+-02128                                             ep->dwc_ep.xfer_count;
+-02129 
+-02130                                         ep->dwc_ep.xfer_buff += byte_count;
+-02131                                         ep->dwc_ep.dma_addr += byte_count;
+-02132                                         ep->dwc_ep.xfer_count += byte_count;
+-02133 
+-02134                                         DWC_DEBUGPL(DBG_PCDV,
+-02135                                                     "%d-%s len=%d  xfersize=%d pktcnt=%d\n",
+-02136                                                     ep->dwc_ep.num,
+-02137                                                     (ep->dwc_ep.
+-02138                                                      is_in ? "IN" : "OUT"),
+-02139                                                     ep->dwc_ep.xfer_len,
+-02140                                                     deptsiz.b.xfersize,
+-02141                                                     deptsiz.b.pktcnt);
+-02142 
+-02143                                         if (ep->dwc_ep.xfer_len <
+-02144                                             ep->dwc_ep.total_len) {
+-02145                                                 dwc_otg_ep_start_transfer
+-02146                                                     (core_if, &ep->dwc_ep);
+-02147                                         } else if (ep->dwc_ep.sent_zlp) {
+-02148                                                 /*     
+-02149                                                  * This fragment of code should initiate 0
+-02150                                                  * length transfer in case if it is queued
+-02151                                                  * a transfer with size divisible to EPs max
+-02152                                                  * packet size and with usb_request zero field
+-02153                                                  * is set, which means that after data is transfered,
+-02154                                                  * it is also should be transfered
+-02155                                                  * a 0 length packet at the end. For Slave and
+-02156                                                  * Buffer DMA modes in this case SW has
+-02157                                                  * to initiate 2 transfers one with transfer size,
+-02158                                                  * and the second with 0 size. For Descriptor
+-02159                                                  * DMA mode SW is able to initiate a transfer,
+-02160                                                  * which will handle all the packets including
+-02161                                                  * the last  0 length.
+-02162                                                  */
+-02163                                                 ep->dwc_ep.sent_zlp = 0;
+-02164                                                 dwc_otg_ep_start_zl_transfer
+-02165                                                     (core_if, &ep->dwc_ep);
+-02166                                         } else {
+-02167                                                 is_last = 1;
+-02168                                         }
+-02169                                 } else {
+-02170                                         if(ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC)
+-02171                                         {
+-02172                                                 req->actual = 0;
+-02173                                                 dwc_otg_request_done(ep, req, 0);
+-02174 
+-02175                                                 ep->dwc_ep.start_xfer_buff = 0;
+-02176                                                 ep->dwc_ep.xfer_buff = 0;
+-02177                                                 ep->dwc_ep.xfer_len = 0;
+-02178 
+-02179                                                 /* If there is a request in the queue start it. */
+-02180                                                 start_next_request(ep);
+-02181                                         } else
+-02182                                                 DWC_WARN
+-02183                                                 ("Incomplete transfer (%d - %s [siz=%d pkt=%d])\n",
+-02184                                                 ep->dwc_ep.num,
+-02185                                                 (ep->dwc_ep.is_in ? "IN" : "OUT"),
+-02186                                                 deptsiz.b.xfersize,
+-02187                                                 deptsiz.b.pktcnt);
+-02188                                 }
+-02189                         } else {
+-02190                                 dma_desc = ep->dwc_ep.desc_addr;
+-02191                                 byte_count = 0;
+-02192                                 ep->dwc_ep.sent_zlp = 0;
+-02193 
+-02194 #ifdef DWC_UTE_CFI
+-02195                                 CFI_INFO("%s: BUFFER_MODE=%d\n", __func__,
+-02196                                          ep->dwc_ep.buff_mode);
+-02197                                 if (ep->dwc_ep.buff_mode != BM_STANDARD) {
+-02198                                         int residue;
+-02199 
+-02200                                         residue = cfi_calc_desc_residue(ep);
+-02201                                         if (residue < 0)
+-02202                                                 return;
+-02203 
+-02204                                         byte_count = residue;
+-02205                                 } else {
+-02206 #endif
+-02207                                         for (i = 0; i < ep->dwc_ep.desc_cnt;
+-02208                                              ++i) {
+-02209                                         desc_sts = dma_desc->status;
+-02210                                         byte_count += desc_sts.b.bytes;
+-02211                                         dma_desc++;
+-02212                                 }
+-02213 #ifdef DWC_UTE_CFI
+-02214                                 }
+-02215 #endif
+-02216                                 if (byte_count == 0) {
+-02217                                         ep->dwc_ep.xfer_count =
+-02218                                             ep->dwc_ep.total_len;
+-02219                                         is_last = 1;
+-02220                                 } else {
+-02221                                         DWC_WARN("Incomplete transfer\n");
+-02222                                 }
+-02223                         }
+-02224                 } else {
+-02225                         if (deptsiz.b.xfersize == 0 && deptsiz.b.pktcnt == 0) {
+-02226                                 DWC_DEBUGPL(DBG_PCDV,
+-02227                                             "%d-%s len=%d  xfersize=%d pktcnt=%d\n",
+-02228                                             ep->dwc_ep.num,
+-02229                                             ep->dwc_ep.is_in ? "IN" : "OUT",
+-02230                                             ep->dwc_ep.xfer_len,
+-02231                                             deptsiz.b.xfersize,
+-02232                                             deptsiz.b.pktcnt);
+-02233 
+-02234                                 /*      Check if the whole transfer was completed, 
+-02235                                  *      if no, setup transfer for next portion of data
+-02236                                  */
+-02237                                 if (ep->dwc_ep.xfer_len < ep->dwc_ep.total_len) {
+-02238                                         dwc_otg_ep_start_transfer(core_if,
+-02239                                                                   &ep->dwc_ep);
+-02240                                 } else if (ep->dwc_ep.sent_zlp) {
+-02241                                         /*     
+-02242                                          * This fragment of code should initiate 0
+-02243                                          * length trasfer in case if it is queued
+-02244                                          * a trasfer with size divisible to EPs max
+-02245                                          * packet size and with usb_request zero field
+-02246                                          * is set, which means that after data is transfered,
+-02247                                          * it is also should be transfered
+-02248                                          * a 0 length packet at the end. For Slave and
+-02249                                          * Buffer DMA modes in this case SW has
+-02250                                          * to initiate 2 transfers one with transfer size,
+-02251                                          * and the second with 0 size. For Desriptor
+-02252                                          * DMA mode SW is able to initiate a transfer,
+-02253                                          * which will handle all the packets including
+-02254                                          * the last  0 legth.
+-02255                                          */
+-02256                                         ep->dwc_ep.sent_zlp = 0;
+-02257                                         dwc_otg_ep_start_zl_transfer(core_if,
+-02258                                                                      &ep->dwc_ep);
+-02259                                 } else {
+-02260                                         is_last = 1;
+-02261                                 }
+-02262                         } else {
+-02263                                 DWC_WARN
+-02264                                     ("Incomplete transfer (%d-%s [siz=%d pkt=%d])\n",
+-02265                                      ep->dwc_ep.num,
+-02266                                      (ep->dwc_ep.is_in ? "IN" : "OUT"),
+-02267                                      deptsiz.b.xfersize, deptsiz.b.pktcnt);
+-02268                         }
+-02269                 }
+-02270         } else {
+-02271                 dwc_otg_dev_out_ep_regs_t *out_ep_regs =
+-02272                     dev_if->out_ep_regs[ep->dwc_ep.num];
+-02273                 desc_sts.d32 = 0;
+-02274                 if (core_if->dma_enable) {
+-02275                         if (core_if->dma_desc_enable) {
+-02276                                 dma_desc = ep->dwc_ep.desc_addr;
+-02277                                 byte_count = 0;
+-02278                                 ep->dwc_ep.sent_zlp = 0;
+-02279 
+-02280 #ifdef DWC_UTE_CFI
+-02281                                 CFI_INFO("%s: BUFFER_MODE=%d\n", __func__,
+-02282                                          ep->dwc_ep.buff_mode);
+-02283                                 if (ep->dwc_ep.buff_mode != BM_STANDARD) {
+-02284                                         int residue;
+-02285                                         residue = cfi_calc_desc_residue(ep);
+-02286                                         if (residue < 0)
+-02287                                                 return;
+-02288                                         byte_count = residue;
+-02289                                 } else {
+-02290 #endif
+-02291 
+-02292                                         for (i = 0; i < ep->dwc_ep.desc_cnt;
+-02293                                              ++i) {
+-02294                                                 desc_sts = dma_desc->status;
+-02295                                                 byte_count += desc_sts.b.bytes;
+-02296                                                 dma_desc++;
+-02297                                         }
+-02298 
+-02299 #ifdef DWC_UTE_CFI
+-02300                                 }
+-02301 #endif
+-02302                                 /* Checking for interrupt Out transfers with not 
+-02303                                  * dword aligned mps sizes 
+-02304                                  */
+-02305                                 if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_INTR &&
+-02306                                                         (ep->dwc_ep.maxpacket%4)) {
+-02307                                         ep->dwc_ep.xfer_count = ep->dwc_ep.total_len - byte_count;
+-02308                                         if ((ep->dwc_ep.xfer_len % ep->dwc_ep.maxpacket) &&
+-02309                                                 (ep->dwc_ep.xfer_len/ep->dwc_ep.maxpacket < MAX_DMA_DESC_CNT))
+-02310                                                 ep->dwc_ep.xfer_len -=
+-02311                                                         (ep->dwc_ep.desc_cnt - 1) * ep->dwc_ep.maxpacket +
+-02312                                                                         ep->dwc_ep.xfer_len % ep->dwc_ep.maxpacket;
+-02313                                         else                                            
+-02314                                                 ep->dwc_ep.xfer_len -=
+-02315                                                                         ep->dwc_ep.desc_cnt * ep->dwc_ep.maxpacket;
+-02316                                         if (ep->dwc_ep.xfer_len > 0) {
+-02317                                                 dwc_otg_ep_start_transfer(core_if,
+-02318                                                                   &ep->dwc_ep);
+-02319                                         } else {
+-02320                                                 is_last = 1;
+-02321                                         }
+-02322                                 } else {
+-02323                                         ep->dwc_ep.xfer_count = ep->dwc_ep.total_len
+-02324                                                 - byte_count +
+-02325                                                 ((4 - (ep->dwc_ep.total_len & 0x3)) & 0x3);
+-02326                                         is_last = 1;
+-02327                                 }       
+-02328                         } else {
+-02329                                 deptsiz.d32 = 0;
+-02330                                 deptsiz.d32 =
+-02331                                     DWC_READ_REG32(&out_ep_regs->doeptsiz);
+-02332 
+-02333                                 byte_count = (ep->dwc_ep.xfer_len -
+-02334                                               ep->dwc_ep.xfer_count -
+-02335                                               deptsiz.b.xfersize);
+-02336                                 ep->dwc_ep.xfer_buff += byte_count;
+-02337                                 ep->dwc_ep.dma_addr += byte_count;
+-02338                                 ep->dwc_ep.xfer_count += byte_count;
+-02339 
+-02340                                 /*      Check if the whole transfer was completed, 
+-02341                                  *      if no, setup transfer for next portion of data
+-02342                                  */
+-02343                                 if (ep->dwc_ep.xfer_len < ep->dwc_ep.total_len) {
+-02344                                         dwc_otg_ep_start_transfer(core_if,
+-02345                                                                   &ep->dwc_ep);
+-02346                                 } else if (ep->dwc_ep.sent_zlp) {
+-02347                                         /*     
+-02348                                          * This fragment of code should initiate 0
+-02349                                          * length trasfer in case if it is queued
+-02350                                          * a trasfer with size divisible to EPs max
+-02351                                          * packet size and with usb_request zero field
+-02352                                          * is set, which means that after data is transfered,
+-02353                                          * it is also should be transfered
+-02354                                          * a 0 length packet at the end. For Slave and
+-02355                                          * Buffer DMA modes in this case SW has
+-02356                                          * to initiate 2 transfers one with transfer size,
+-02357                                          * and the second with 0 size. For Desriptor
+-02358                                          * DMA mode SW is able to initiate a transfer,
+-02359                                          * which will handle all the packets including
+-02360                                          * the last  0 legth.
+-02361                                          */
+-02362                                         ep->dwc_ep.sent_zlp = 0;
+-02363                                         dwc_otg_ep_start_zl_transfer(core_if,
+-02364                                                                      &ep->dwc_ep);
+-02365                                 } else {
+-02366                                         is_last = 1;
+-02367                                 }
+-02368                         }
+-02369                 } else {
+-02370                         /*      Check if the whole transfer was completed, 
+-02371                          *      if no, setup transfer for next portion of data
+-02372                          */
+-02373                         if (ep->dwc_ep.xfer_len < ep->dwc_ep.total_len) {
+-02374                                 dwc_otg_ep_start_transfer(core_if, &ep->dwc_ep);
+-02375                         } else if (ep->dwc_ep.sent_zlp) {
+-02376                                 /*     
+-02377                                  * This fragment of code should initiate 0
+-02378                                  * length transfer in case if it is queued
+-02379                                  * a transfer with size divisible to EPs max
+-02380                                  * packet size and with usb_request zero field
+-02381                                  * is set, which means that after data is transfered,
+-02382                                  * it is also should be transfered
+-02383                                  * a 0 length packet at the end. For Slave and
+-02384                                  * Buffer DMA modes in this case SW has
+-02385                                  * to initiate 2 transfers one with transfer size,
+-02386                                  * and the second with 0 size. For Descriptor
+-02387                                  * DMA mode SW is able to initiate a transfer,
+-02388                                  * which will handle all the packets including
+-02389                                  * the last  0 length.
+-02390                                  */
+-02391                                 ep->dwc_ep.sent_zlp = 0;
+-02392                                 dwc_otg_ep_start_zl_transfer(core_if,
+-02393                                                              &ep->dwc_ep);
+-02394                         } else {
+-02395                                 is_last = 1;
+-02396                         }
+-02397                 }
+-02398 
+-02399                 DWC_DEBUGPL(DBG_PCDV,
+-02400                             "addr %p,    %d-%s len=%d cnt=%d xsize=%d pktcnt=%d\n",
+-02401                             &out_ep_regs->doeptsiz, ep->dwc_ep.num,
+-02402                             ep->dwc_ep.is_in ? "IN" : "OUT",
+-02403                             ep->dwc_ep.xfer_len, ep->dwc_ep.xfer_count,
+-02404                             deptsiz.b.xfersize, deptsiz.b.pktcnt);
+-02405         }
+-02406 
+-02407         /* Complete the request */
+-02408         if (is_last) {
+-02409 #ifdef DWC_UTE_CFI
+-02410                 if (ep->dwc_ep.buff_mode != BM_STANDARD) {
+-02411                         req->actual = ep->dwc_ep.cfi_req_len - byte_count;
+-02412                 } else {
+-02413 #endif
+-02414                         req->actual = ep->dwc_ep.xfer_count;
+-02415 #ifdef DWC_UTE_CFI
+-02416                 }
+-02417 #endif
+-02418                 if (req->dw_align_buf) {
+-02419                         if (!ep->dwc_ep.is_in) {
+-02420                                 dwc_memcpy(req->buf, req->dw_align_buf, req->length); 
+-02421                         }
+-02422                         DWC_DMA_FREE(req->length, req->dw_align_buf,
+-02423                                      req->dw_align_buf_dma);
+-02424                 }
+-02425 
+-02426                 dwc_otg_request_done(ep, req, 0);
+-02427 
+-02428                 ep->dwc_ep.start_xfer_buff = 0;
+-02429                 ep->dwc_ep.xfer_buff = 0;
+-02430                 ep->dwc_ep.xfer_len = 0;
+-02431 
+-02432                 /* If there is a request in the queue start it. */
+-02433                 start_next_request(ep);
+-02434         }
+-02435 }
+-02436 
+-02437 #ifdef DWC_EN_ISOC
+-02438 
+-02443 static void dwc_otg_pcd_handle_iso_bna(dwc_otg_pcd_ep_t * ep)
+-02444 {
+-02445         dwc_ep_t *dwc_ep = &ep->dwc_ep;
+-02446         volatile uint32_t *addr;
+-02447         depctl_data_t depctl = {.d32 = 0 };
+-02448         dwc_otg_pcd_t *pcd = ep->pcd;
+-02449         dwc_otg_dev_dma_desc_t *dma_desc;
+-02450         int i;
+-02451 
+-02452         dma_desc =
+-02453             dwc_ep->iso_desc_addr + dwc_ep->desc_cnt * (dwc_ep->proc_buf_num);
+-02454 
+-02455         if (dwc_ep->is_in) {
+-02456                 dev_dma_desc_sts_t sts = {.d32 = 0 };
+-02457                 for (i = 0; i < dwc_ep->desc_cnt; ++i, ++dma_desc) {
+-02458                         sts.d32 = dma_desc->status.d32;
+-02459                         sts.b_iso_in.bs = BS_HOST_READY;
+-02460                         dma_desc->status.d32 = sts.d32;
+-02461                 }
+-02462         } else {
+-02463                 dev_dma_desc_sts_t sts = {.d32 = 0 };
+-02464                 for (i = 0; i < dwc_ep->desc_cnt; ++i, ++dma_desc) {
+-02465                         sts.d32 = dma_desc->status.d32;
+-02466                         sts.b_iso_out.bs = BS_HOST_READY;
+-02467                         dma_desc->status.d32 = sts.d32;
+-02468                 }
+-02469         }
+-02470 
+-02471         if (dwc_ep->is_in == 0) {
+-02472                 addr =
+-02473                     &GET_CORE_IF(pcd)->dev_if->out_ep_regs[dwc_ep->
+-02474                                                            num]->doepctl;
+-02475         } else {
+-02476                 addr =
+-02477                     &GET_CORE_IF(pcd)->dev_if->in_ep_regs[dwc_ep->num]->diepctl;
+-02478         }
+-02479         depctl.b.epena = 1;
+-02480         DWC_MODIFY_REG32(addr, depctl.d32, depctl.d32);
+-02481 }
+-02482 
+-02490 void set_current_pkt_info(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
+-02491 {
+-02492         deptsiz_data_t deptsiz = {.d32 = 0 };
+-02493         dma_addr_t dma_addr;
+-02494         uint32_t offset;
+-02495 
+-02496         if (ep->proc_buf_num)
+-02497                 dma_addr = ep->dma_addr1;
+-02498         else
+-02499                 dma_addr = ep->dma_addr0;
+-02500 
+-02501         if (ep->is_in) {
+-02502                 deptsiz.d32 =
+-02503                     DWC_READ_REG32(&core_if->dev_if->
+-02504                                    in_ep_regs[ep->num]->dieptsiz);
+-02505                 offset = ep->data_per_frame;
+-02506         } else {
+-02507                 deptsiz.d32 =
+-02508                     DWC_READ_REG32(&core_if->dev_if->
+-02509                                    out_ep_regs[ep->num]->doeptsiz);
+-02510                 offset =
+-02511                     ep->data_per_frame +
+-02512                     (0x4 & (0x4 - (ep->data_per_frame & 0x3)));
+-02513         }
+-02514 
+-02515         if (!deptsiz.b.xfersize) {
+-02516                 ep->pkt_info[ep->cur_pkt].length = ep->data_per_frame;
+-02517                 ep->pkt_info[ep->cur_pkt].offset =
+-02518                     ep->cur_pkt_dma_addr - dma_addr;
+-02519                 ep->pkt_info[ep->cur_pkt].status = 0;
+-02520         } else {
+-02521                 ep->pkt_info[ep->cur_pkt].length = ep->data_per_frame;
+-02522                 ep->pkt_info[ep->cur_pkt].offset =
+-02523                     ep->cur_pkt_dma_addr - dma_addr;
+-02524                 ep->pkt_info[ep->cur_pkt].status = -DWC_E_NO_DATA;
+-02525         }
+-02526         ep->cur_pkt_addr += offset;
+-02527         ep->cur_pkt_dma_addr += offset;
+-02528         ep->cur_pkt++;
+-02529 }
+-02530 
+-02538 static void set_ddma_iso_pkts_info(dwc_otg_core_if_t * core_if,
+-02539                                    dwc_ep_t * dwc_ep)
+-02540 {
+-02541         dwc_otg_dev_dma_desc_t *dma_desc;
+-02542         dev_dma_desc_sts_t sts = {.d32 = 0 };
+-02543         iso_pkt_info_t *iso_packet;
+-02544         uint32_t data_per_desc;
+-02545         uint32_t offset;
+-02546         int i, j;
+-02547 
+-02548         iso_packet = dwc_ep->pkt_info;
+-02549 
+-02552         if (dwc_ep->is_in == 0) {
+-02553                 dma_desc =
+-02554                     dwc_ep->iso_desc_addr +
+-02555                     dwc_ep->desc_cnt * dwc_ep->proc_buf_num;
+-02556                 offset = 0;
+-02557 
+-02558                 for (i = 0; i < dwc_ep->desc_cnt - dwc_ep->pkt_per_frm;
+-02559                      i += dwc_ep->pkt_per_frm) {
+-02560                         for (j = 0; j < dwc_ep->pkt_per_frm; ++j) {
+-02561                                 data_per_desc =
+-02562                                     ((j + 1) * dwc_ep->maxpacket >
+-02563                                      dwc_ep->
+-02564                                      data_per_frame) ? dwc_ep->data_per_frame -
+-02565                                     j * dwc_ep->maxpacket : dwc_ep->maxpacket;
+-02566                                 data_per_desc +=
+-02567                                     (data_per_desc % 4) ? (4 -
+-02568                                                            data_per_desc %
+-02569                                                            4) : 0;
+-02570 
+-02571                                 sts.d32 = dma_desc->status.d32;
+-02572 
+-02573                                 /* Write status in iso_packet_decsriptor  */
+-02574                                 iso_packet->status =
+-02575                                     sts.b_iso_out.rxsts +
+-02576                                     (sts.b_iso_out.bs ^ BS_DMA_DONE);
+-02577                                 if (iso_packet->status) {
+-02578                                         iso_packet->status = -DWC_E_NO_DATA;
+-02579                                 }
+-02580 
+-02581                                 /* Received data length */
+-02582                                 if (!sts.b_iso_out.rxbytes) {
+-02583                                         iso_packet->length =
+-02584                                             data_per_desc -
+-02585                                             sts.b_iso_out.rxbytes;
+-02586                                 } else {
+-02587                                         iso_packet->length =
+-02588                                             data_per_desc -
+-02589                                             sts.b_iso_out.rxbytes + (4 -
+-02590                                                                      dwc_ep->data_per_frame
+-02591                                                                      % 4);
+-02592                                 }
+-02593 
+-02594                                 iso_packet->offset = offset;
+-02595 
+-02596                                 offset += data_per_desc;
+-02597                                 dma_desc++;
+-02598                                 iso_packet++;
+-02599                         }
+-02600                 }
+-02601 
+-02602                 for (j = 0; j < dwc_ep->pkt_per_frm - 1; ++j) {
+-02603                         data_per_desc =
+-02604                             ((j + 1) * dwc_ep->maxpacket >
+-02605                              dwc_ep->data_per_frame) ? dwc_ep->data_per_frame -
+-02606                             j * dwc_ep->maxpacket : dwc_ep->maxpacket;
+-02607                         data_per_desc +=
+-02608                             (data_per_desc % 4) ? (4 - data_per_desc % 4) : 0;
+-02609 
+-02610                         sts.d32 = dma_desc->status.d32;
+-02611 
+-02612                         /* Write status in iso_packet_decsriptor  */
+-02613                         iso_packet->status =
+-02614                             sts.b_iso_out.rxsts +
+-02615                             (sts.b_iso_out.bs ^ BS_DMA_DONE);
+-02616                         if (iso_packet->status) {
+-02617                                 iso_packet->status = -DWC_E_NO_DATA;
+-02618                         }
+-02619 
+-02620                         /* Received data length */
+-02621                         iso_packet->length =
+-02622                             dwc_ep->data_per_frame - sts.b_iso_out.rxbytes;
+-02623 
+-02624                         iso_packet->offset = offset;
+-02625 
+-02626                         offset += data_per_desc;
+-02627                         iso_packet++;
+-02628                         dma_desc++;
+-02629                 }
+-02630 
+-02631                 sts.d32 = dma_desc->status.d32;
+-02632 
+-02633                 /* Write status in iso_packet_decsriptor  */
+-02634                 iso_packet->status =
+-02635                     sts.b_iso_out.rxsts + (sts.b_iso_out.bs ^ BS_DMA_DONE);
+-02636                 if (iso_packet->status) {
+-02637                         iso_packet->status = -DWC_E_NO_DATA;
+-02638                 }
+-02639                 /* Received data length */
+-02640                 if (!sts.b_iso_out.rxbytes) {
+-02641                         iso_packet->length =
+-02642                             dwc_ep->data_per_frame - sts.b_iso_out.rxbytes;
+-02643                 } else {
+-02644                         iso_packet->length =
+-02645                             dwc_ep->data_per_frame - sts.b_iso_out.rxbytes +
+-02646                             (4 - dwc_ep->data_per_frame % 4);
+-02647                 }
+-02648 
+-02649                 iso_packet->offset = offset;
+-02650         } else {
+-02653                 dma_desc =
+-02654                     dwc_ep->iso_desc_addr +
+-02655                     dwc_ep->desc_cnt * dwc_ep->proc_buf_num;
+-02656 
+-02657                 for (i = 0; i < dwc_ep->desc_cnt - 1; i++) {
+-02658                         sts.d32 = dma_desc->status.d32;
+-02659 
+-02660                         /* Write status in iso packet descriptor */
+-02661                         iso_packet->status =
+-02662                             sts.b_iso_in.txsts +
+-02663                             (sts.b_iso_in.bs ^ BS_DMA_DONE);
+-02664                         if (iso_packet->status != 0) {
+-02665                                 iso_packet->status = -DWC_E_NO_DATA;
+-02666 
+-02667                         }
+-02668                         /* Bytes has been transfered */
+-02669                         iso_packet->length =
+-02670                             dwc_ep->data_per_frame - sts.b_iso_in.txbytes;
+-02671 
+-02672                         dma_desc++;
+-02673                         iso_packet++;
+-02674                 }
+-02675 
+-02676                 sts.d32 = dma_desc->status.d32;
+-02677                 while (sts.b_iso_in.bs == BS_DMA_BUSY) {
+-02678                         sts.d32 = dma_desc->status.d32;
+-02679                 }
+-02680 
+-02681                 /* Write status in iso packet descriptor ??? do be done with ERROR codes */
+-02682                 iso_packet->status =
+-02683                     sts.b_iso_in.txsts + (sts.b_iso_in.bs ^ BS_DMA_DONE);
+-02684                 if (iso_packet->status != 0) {
+-02685                         iso_packet->status = -DWC_E_NO_DATA;
+-02686                 }
+-02687 
+-02688                 /* Bytes has been transfered */
+-02689                 iso_packet->length =
+-02690                     dwc_ep->data_per_frame - sts.b_iso_in.txbytes;
+-02691         }
+-02692 }
+-02693 
+-02701 static void reinit_ddma_iso_xfer(dwc_otg_core_if_t * core_if, dwc_ep_t * dwc_ep)
+-02702 {
+-02703         int i, j;
+-02704         dwc_otg_dev_dma_desc_t *dma_desc;
+-02705         dma_addr_t dma_ad;
+-02706         volatile uint32_t *addr;
+-02707         dev_dma_desc_sts_t sts = {.d32 = 0 };
+-02708         uint32_t data_per_desc;
+-02709 
+-02710         if (dwc_ep->is_in == 0) {
+-02711                 addr = &core_if->dev_if->out_ep_regs[dwc_ep->num]->doepctl;
+-02712         } else {
+-02713                 addr = &core_if->dev_if->in_ep_regs[dwc_ep->num]->diepctl;
+-02714         }
+-02715 
+-02716         if (dwc_ep->proc_buf_num == 0) {
+-02718                 dma_ad = dwc_ep->dma_addr0;
+-02719         } else {
+-02721                 dma_ad = dwc_ep->dma_addr1;
+-02722         }
+-02723 
+-02726         if (dwc_ep->is_in == 0) {
+-02727                 dma_desc =
+-02728                     dwc_ep->iso_desc_addr +
+-02729                     dwc_ep->desc_cnt * dwc_ep->proc_buf_num;
+-02730 
+-02731                 sts.b_iso_out.bs = BS_HOST_READY;
+-02732                 sts.b_iso_out.rxsts = 0;
+-02733                 sts.b_iso_out.l = 0;
+-02734                 sts.b_iso_out.sp = 0;
+-02735                 sts.b_iso_out.ioc = 0;
+-02736                 sts.b_iso_out.pid = 0;
+-02737                 sts.b_iso_out.framenum = 0;
+-02738 
+-02739                 for (i = 0; i < dwc_ep->desc_cnt - dwc_ep->pkt_per_frm;
+-02740                      i += dwc_ep->pkt_per_frm) {
+-02741                         for (j = 0; j < dwc_ep->pkt_per_frm; ++j) {
+-02742                                 data_per_desc =
+-02743                                     ((j + 1) * dwc_ep->maxpacket >
+-02744                                      dwc_ep->
+-02745                                      data_per_frame) ? dwc_ep->data_per_frame -
+-02746                                     j * dwc_ep->maxpacket : dwc_ep->maxpacket;
+-02747                                 data_per_desc +=
+-02748                                     (data_per_desc % 4) ? (4 -
+-02749                                                            data_per_desc %
+-02750                                                            4) : 0;
+-02751                                 sts.b_iso_out.rxbytes = data_per_desc;
+-02752                                 dma_desc->buf = dma_ad;
+-02753                                 dma_desc->status.d32 = sts.d32;
+-02754 
+-02755                                 dma_ad += data_per_desc;
+-02756                                 dma_desc++;
+-02757                         }
+-02758                 }
+-02759 
+-02760                 for (j = 0; j < dwc_ep->pkt_per_frm - 1; ++j) {
+-02761 
+-02762                         data_per_desc =
+-02763                             ((j + 1) * dwc_ep->maxpacket >
+-02764                              dwc_ep->data_per_frame) ? dwc_ep->data_per_frame -
+-02765                             j * dwc_ep->maxpacket : dwc_ep->maxpacket;
+-02766                         data_per_desc +=
+-02767                             (data_per_desc % 4) ? (4 - data_per_desc % 4) : 0;
+-02768                         sts.b_iso_out.rxbytes = data_per_desc;
+-02769 
+-02770                         dma_desc->buf = dma_ad;
+-02771                         dma_desc->status.d32 = sts.d32;
+-02772 
+-02773                         dma_desc++;
+-02774                         dma_ad += data_per_desc;
+-02775                 }
+-02776 
+-02777                 sts.b_iso_out.ioc = 1;
+-02778                 sts.b_iso_out.l = dwc_ep->proc_buf_num;
+-02779 
+-02780                 data_per_desc =
+-02781                     ((j + 1) * dwc_ep->maxpacket >
+-02782                      dwc_ep->data_per_frame) ? dwc_ep->data_per_frame -
+-02783                     j * dwc_ep->maxpacket : dwc_ep->maxpacket;
+-02784                 data_per_desc +=
+-02785                     (data_per_desc % 4) ? (4 - data_per_desc % 4) : 0;
+-02786                 sts.b_iso_out.rxbytes = data_per_desc;
+-02787 
+-02788                 dma_desc->buf = dma_ad;
+-02789                 dma_desc->status.d32 = sts.d32;
+-02790         } else {
+-02793                 dma_desc =
+-02794                     dwc_ep->iso_desc_addr +
+-02795                     dwc_ep->desc_cnt * dwc_ep->proc_buf_num;
+-02796 
+-02797                 sts.b_iso_in.bs = BS_HOST_READY;
+-02798                 sts.b_iso_in.txsts = 0;
+-02799                 sts.b_iso_in.sp = 0;
+-02800                 sts.b_iso_in.ioc = 0;
+-02801                 sts.b_iso_in.pid = dwc_ep->pkt_per_frm;
+-02802                 sts.b_iso_in.framenum = dwc_ep->next_frame;
+-02803                 sts.b_iso_in.txbytes = dwc_ep->data_per_frame;
+-02804                 sts.b_iso_in.l = 0;
+-02805 
+-02806                 for (i = 0; i < dwc_ep->desc_cnt - 1; i++) {
+-02807                         dma_desc->buf = dma_ad;
+-02808                         dma_desc->status.d32 = sts.d32;
+-02809 
+-02810                         sts.b_iso_in.framenum += dwc_ep->bInterval;
+-02811                         dma_ad += dwc_ep->data_per_frame;
+-02812                         dma_desc++;
+-02813                 }
+-02814 
+-02815                 sts.b_iso_in.ioc = 1;
+-02816                 sts.b_iso_in.l = dwc_ep->proc_buf_num;
+-02817 
+-02818                 dma_desc->buf = dma_ad;
+-02819                 dma_desc->status.d32 = sts.d32;
+-02820 
+-02821                 dwc_ep->next_frame =
+-02822                     sts.b_iso_in.framenum + dwc_ep->bInterval * 1;
+-02823         }
+-02824         dwc_ep->proc_buf_num = (dwc_ep->proc_buf_num ^ 1) & 0x1;
+-02825 }
+-02826 
+-02835 static uint32_t handle_iso_out_pkt_dropped(dwc_otg_core_if_t * core_if,
+-02836                                            dwc_ep_t * dwc_ep)
+-02837 {
+-02838         uint32_t dma_addr;
+-02839         uint32_t drp_pkt;
+-02840         uint32_t drp_pkt_cnt;
+-02841         deptsiz_data_t deptsiz = {.d32 = 0 };
+-02842         depctl_data_t depctl = {.d32 = 0 };
+-02843         int i;
+-02844 
+-02845         deptsiz.d32 =
+-02846             DWC_READ_REG32(&core_if->dev_if->
+-02847                            out_ep_regs[dwc_ep->num]->doeptsiz);
+-02848 
+-02849         drp_pkt = dwc_ep->pkt_cnt - deptsiz.b.pktcnt;
+-02850         drp_pkt_cnt = dwc_ep->pkt_per_frm - (drp_pkt % dwc_ep->pkt_per_frm);
+-02851 
+-02852         /* Setting dropped packets status */
+-02853         for (i = 0; i < drp_pkt_cnt; ++i) {
+-02854                 dwc_ep->pkt_info[drp_pkt].status = -DWC_E_NO_DATA;
+-02855                 drp_pkt++;
+-02856                 deptsiz.b.pktcnt--;
+-02857         }
+-02858 
+-02859         if (deptsiz.b.pktcnt > 0) {
+-02860                 deptsiz.b.xfersize =
+-02861                     dwc_ep->xfer_len - (dwc_ep->pkt_cnt -
+-02862                                         deptsiz.b.pktcnt) * dwc_ep->maxpacket;
+-02863         } else {
+-02864                 deptsiz.b.xfersize = 0;
+-02865                 deptsiz.b.pktcnt = 0;
+-02866         }
+-02867 
+-02868         DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[dwc_ep->num]->doeptsiz,
+-02869                         deptsiz.d32);
+-02870 
+-02871         if (deptsiz.b.pktcnt > 0) {
+-02872                 if (dwc_ep->proc_buf_num) {
+-02873                         dma_addr =
+-02874                             dwc_ep->dma_addr1 + dwc_ep->xfer_len -
+-02875                             deptsiz.b.xfersize;
+-02876                 } else {
+-02877                         dma_addr =
+-02878                             dwc_ep->dma_addr0 + dwc_ep->xfer_len -
+-02879                             deptsiz.b.xfersize;;
+-02880                 }
+-02881 
+-02882                 DWC_WRITE_REG32(&core_if->dev_if->
+-02883                                 out_ep_regs[dwc_ep->num]->doepdma, dma_addr);
+-02884 
+-02886                 depctl.d32 = 0;
+-02887                 depctl.b.epena = 1;
+-02888                 depctl.b.cnak = 1;
+-02889 
+-02890                 DWC_MODIFY_REG32(&core_if->dev_if->
+-02891                                  out_ep_regs[dwc_ep->num]->doepctl, depctl.d32,
+-02892                                  depctl.d32);
+-02893                 return 0;
+-02894         } else {
+-02895                 return 1;
+-02896         }
+-02897 }
+-02898 
+-02906 static uint32_t set_iso_pkts_info(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
+-02907 {
+-02908         int i, j;
+-02909         dma_addr_t dma_ad;
+-02910         iso_pkt_info_t *packet_info = ep->pkt_info;
+-02911         uint32_t offset;
+-02912         uint32_t frame_data;
+-02913         deptsiz_data_t deptsiz;
+-02914 
+-02915         if (ep->proc_buf_num == 0) {
+-02917                 dma_ad = ep->dma_addr0;
+-02918         } else {
+-02920                 dma_ad = ep->dma_addr1;
+-02921         }
+-02922 
+-02923         if (ep->is_in) {
+-02924                 deptsiz.d32 =
+-02925                     DWC_READ_REG32(&core_if->dev_if->
+-02926                                    in_ep_regs[ep->num]->dieptsiz);
+-02927         } else {
+-02928                 deptsiz.d32 =
+-02929                     DWC_READ_REG32(&core_if->dev_if->
+-02930                                    out_ep_regs[ep->num]->doeptsiz);
+-02931         }
+-02932 
+-02933         if (!deptsiz.b.xfersize) {
+-02934                 offset = 0;
+-02935                 for (i = 0; i < ep->pkt_cnt; i += ep->pkt_per_frm) {
+-02936                         frame_data = ep->data_per_frame;
+-02937                         for (j = 0; j < ep->pkt_per_frm; ++j) {
+-02938 
+-02939                                 /* Packet status - is not set as initially
+-02940                                  * it is set to 0 and if packet was sent
+-02941                                  successfully, status field will remain 0*/
+-02942 
+-02943                                 /* Bytes has been transfered */
+-02944                                 packet_info->length =
+-02945                                     (ep->maxpacket <
+-02946                                      frame_data) ? ep->maxpacket : frame_data;
+-02947 
+-02948                                 /* Received packet offset */
+-02949                                 packet_info->offset = offset;
+-02950                                 offset += packet_info->length;
+-02951                                 frame_data -= packet_info->length;
+-02952 
+-02953                                 packet_info++;
+-02954                         }
+-02955                 }
+-02956                 return 1;
+-02957         } else {
+-02958                 /* This is a workaround for in case of Transfer Complete with
+-02959                  * PktDrpSts interrupts merging - in this case Transfer complete
+-02960                  * interrupt for Isoc Out Endpoint is asserted without PktDrpSts
+-02961                  * set and with DOEPTSIZ register non zero. Investigations showed,
+-02962                  * that this happens when Out packet is dropped, but because of
+-02963                  * interrupts merging during first interrupt handling PktDrpSts
+-02964                  * bit is cleared and for next merged interrupts it is not reset.
+-02965                  * In this case SW hadles the interrupt as if PktDrpSts bit is set.
+-02966                  */
+-02967                 if (ep->is_in) {
+-02968                         return 1;
+-02969                 } else {
+-02970                         return handle_iso_out_pkt_dropped(core_if, ep);
+-02971                 }
+-02972         }
+-02973 }
+-02974 
+-02982 static void complete_iso_ep(dwc_otg_pcd_t * pcd, dwc_otg_pcd_ep_t * ep)
+-02983 {
+-02984         dwc_otg_core_if_t *core_if = GET_CORE_IF(ep->pcd);
+-02985         dwc_ep_t *dwc_ep = &ep->dwc_ep;
+-02986         uint8_t is_last = 0;
+-02987 
+-02988         if (ep->dwc_ep.next_frame == 0xffffffff) {
+-02989                 DWC_WARN("Next frame is not set!\n");
+-02990                 return;
+-02991         }
+-02992 
+-02993         if (core_if->dma_enable) {
+-02994                 if (core_if->dma_desc_enable) {
+-02995                         set_ddma_iso_pkts_info(core_if, dwc_ep);
+-02996                         reinit_ddma_iso_xfer(core_if, dwc_ep);
+-02997                         is_last = 1;
+-02998                 } else {
+-02999                         if (core_if->pti_enh_enable) {
+-03000                                 if (set_iso_pkts_info(core_if, dwc_ep)) {
+-03001                                         dwc_ep->proc_buf_num =
+-03002                                             (dwc_ep->proc_buf_num ^ 1) & 0x1;
+-03003                                         dwc_otg_iso_ep_start_buf_transfer
+-03004                                             (core_if, dwc_ep);
+-03005                                         is_last = 1;
+-03006                                 }
+-03007                         } else {
+-03008                                 set_current_pkt_info(core_if, dwc_ep);
+-03009                                 if (dwc_ep->cur_pkt >= dwc_ep->pkt_cnt) {
+-03010                                         is_last = 1;
+-03011                                         dwc_ep->cur_pkt = 0;
+-03012                                         dwc_ep->proc_buf_num =
+-03013                                             (dwc_ep->proc_buf_num ^ 1) & 0x1;
+-03014                                         if (dwc_ep->proc_buf_num) {
+-03015                                                 dwc_ep->cur_pkt_addr =
+-03016                                                     dwc_ep->xfer_buff1;
+-03017                                                 dwc_ep->cur_pkt_dma_addr =
+-03018                                                     dwc_ep->dma_addr1;
+-03019                                         } else {
+-03020                                                 dwc_ep->cur_pkt_addr =
+-03021                                                     dwc_ep->xfer_buff0;
+-03022                                                 dwc_ep->cur_pkt_dma_addr =
+-03023                                                     dwc_ep->dma_addr0;
+-03024                                         }
+-03025 
+-03026                                 }
+-03027                                 dwc_otg_iso_ep_start_frm_transfer(core_if,
+-03028                                                                   dwc_ep);
+-03029                         }
+-03030                 }
+-03031         } else {
+-03032                 set_current_pkt_info(core_if, dwc_ep);
+-03033                 if (dwc_ep->cur_pkt >= dwc_ep->pkt_cnt) {
+-03034                         is_last = 1;
+-03035                         dwc_ep->cur_pkt = 0;
+-03036                         dwc_ep->proc_buf_num = (dwc_ep->proc_buf_num ^ 1) & 0x1;
+-03037                         if (dwc_ep->proc_buf_num) {
+-03038                                 dwc_ep->cur_pkt_addr = dwc_ep->xfer_buff1;
+-03039                                 dwc_ep->cur_pkt_dma_addr = dwc_ep->dma_addr1;
+-03040                         } else {
+-03041                                 dwc_ep->cur_pkt_addr = dwc_ep->xfer_buff0;
+-03042                                 dwc_ep->cur_pkt_dma_addr = dwc_ep->dma_addr0;
+-03043                         }
+-03044 
+-03045                 }
+-03046                 dwc_otg_iso_ep_start_frm_transfer(core_if, dwc_ep);
+-03047         }
+-03048         if (is_last)
+-03049                 dwc_otg_iso_buffer_done(pcd, ep, ep->iso_req_handle);
+-03050 }
+-03051 #endif /* DWC_EN_ISOC */
+-03052 
+-03057 static void dwc_otg_pcd_handle_noniso_bna(dwc_otg_pcd_ep_t * ep)
+-03058 {
+-03059         dwc_ep_t *dwc_ep = &ep->dwc_ep;
+-03060         volatile uint32_t *addr;
+-03061         depctl_data_t depctl = {.d32 = 0 };
+-03062         dwc_otg_pcd_t *pcd = ep->pcd;
+-03063         dwc_otg_dev_dma_desc_t *dma_desc;
+-03064         dev_dma_desc_sts_t sts = {.d32 = 0 };
+-03065         dwc_otg_core_if_t *core_if = ep->pcd->core_if;
+-03066         int i, start;
+-03067 
+-03068         if (!dwc_ep->desc_cnt)
+-03069                 DWC_WARN("Descriptor count = %d\n", dwc_ep->desc_cnt);
+-03070 
+-03071         if (core_if->core_params->cont_on_bna && !dwc_ep->is_in
+-03072                                                         && dwc_ep->type != DWC_OTG_EP_TYPE_CONTROL) {
+-03073                 uint32_t doepdma;
+-03074                 dwc_otg_dev_out_ep_regs_t *out_regs =
+-03075                         core_if->dev_if->out_ep_regs[dwc_ep->num];
+-03076                 doepdma = DWC_READ_REG32(&(out_regs->doepdma));
+-03077                 start = (doepdma - dwc_ep->dma_desc_addr)/sizeof(dwc_otg_dev_dma_desc_t);
+-03078                 dma_desc = &(dwc_ep->desc_addr[start]);
+-03079         } else {
+-03080                 start = 0;
+-03081                 dma_desc = dwc_ep->desc_addr;
+-03082         }
+-03083         
+-03084 
+-03085         for (i = start; i < dwc_ep->desc_cnt; ++i, ++dma_desc) {
+-03086                 sts.d32 = dma_desc->status.d32;
+-03087                 sts.b.bs = BS_HOST_READY;
+-03088                 dma_desc->status.d32 = sts.d32;
+-03089         }
+-03090 
+-03091         if (dwc_ep->is_in == 0) {
+-03092                 addr =
+-03093                     &GET_CORE_IF(pcd)->dev_if->out_ep_regs[dwc_ep->
+-03094                                                            num]->doepctl;
+-03095         } else {
+-03096                 addr =
+-03097                     &GET_CORE_IF(pcd)->dev_if->in_ep_regs[dwc_ep->num]->diepctl;
+-03098         }
+-03099         depctl.b.epena = 1;
+-03100         depctl.b.cnak = 1;
+-03101         DWC_MODIFY_REG32(addr, 0, depctl.d32);
+-03102 }
+-03103 
+-03110 static void handle_ep0(dwc_otg_pcd_t * pcd)
+-03111 {
+-03112         dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
+-03113         dwc_otg_pcd_ep_t *ep0 = &pcd->ep0;
+-03114         dev_dma_desc_sts_t desc_sts;
+-03115         deptsiz0_data_t deptsiz;
+-03116         uint32_t byte_count;
+-03117 
+-03118 #ifdef DEBUG_EP0
+-03119         DWC_DEBUGPL(DBG_PCDV, "%s()\n", __func__);
+-03120         print_ep0_state(pcd);
+-03121 #endif
+-03122 
+-03123 //      DWC_PRINTF("HANDLE EP0\n");
+-03124 
+-03125         switch (pcd->ep0state) {
+-03126         case EP0_DISCONNECT:
+-03127                 break;
+-03128 
+-03129         case EP0_IDLE:
+-03130                 pcd->request_config = 0;
+-03131 
+-03132                 pcd_setup(pcd);
+-03133                 break;
+-03134 
+-03135         case EP0_IN_DATA_PHASE:
+-03136 #ifdef DEBUG_EP0
+-03137                 DWC_DEBUGPL(DBG_PCD, "DATA_IN EP%d-%s: type=%d, mps=%d\n",
+-03138                             ep0->dwc_ep.num, (ep0->dwc_ep.is_in ? "IN" : "OUT"),
+-03139                             ep0->dwc_ep.type, ep0->dwc_ep.maxpacket);
+-03140 #endif
+-03141 
+-03142                 if (core_if->dma_enable != 0) {
+-03143                         /*
+-03144                          * For EP0 we can only program 1 packet at a time so we
+-03145                          * need to do the make calculations after each complete.
+-03146                          * Call write_packet to make the calculations, as in
+-03147                          * slave mode, and use those values to determine if we
+-03148                          * can complete.
+-03149                          */
+-03150                         if (core_if->dma_desc_enable == 0) {
+-03151                                 deptsiz.d32 =
+-03152                                     DWC_READ_REG32(&core_if->
+-03153                                                    dev_if->in_ep_regs[0]->
+-03154                                                    dieptsiz);
+-03155                                 byte_count =
+-03156                                     ep0->dwc_ep.xfer_len - deptsiz.b.xfersize;
+-03157                         } else {
+-03158                                 desc_sts =
+-03159                                     core_if->dev_if->in_desc_addr->status;
+-03160                                 byte_count =
+-03161                                     ep0->dwc_ep.xfer_len - desc_sts.b.bytes;
+-03162                         }
+-03163                         ep0->dwc_ep.xfer_count += byte_count;
+-03164                         ep0->dwc_ep.xfer_buff += byte_count;
+-03165                         ep0->dwc_ep.dma_addr += byte_count;
+-03166                 }
+-03167                 if (ep0->dwc_ep.xfer_count < ep0->dwc_ep.total_len) {
+-03168                         dwc_otg_ep0_continue_transfer(GET_CORE_IF(pcd),
+-03169                                                       &ep0->dwc_ep);
+-03170                         DWC_DEBUGPL(DBG_PCD, "CONTINUE TRANSFER\n");
+-03171                 } else if (ep0->dwc_ep.sent_zlp) {
+-03172                         dwc_otg_ep0_continue_transfer(GET_CORE_IF(pcd),
+-03173                                                       &ep0->dwc_ep);
+-03174                         ep0->dwc_ep.sent_zlp = 0;
+-03175                         DWC_DEBUGPL(DBG_PCD, "CONTINUE TRANSFER\n");
+-03176                 } else {
+-03177                         ep0_complete_request(ep0);
+-03178                         DWC_DEBUGPL(DBG_PCD, "COMPLETE TRANSFER\n");
+-03179                 }
+-03180                 break;
+-03181         case EP0_OUT_DATA_PHASE:
+-03182 #ifdef DEBUG_EP0
+-03183                 DWC_DEBUGPL(DBG_PCD, "DATA_OUT EP%d-%s: type=%d, mps=%d\n",
+-03184                             ep0->dwc_ep.num, (ep0->dwc_ep.is_in ? "IN" : "OUT"),
+-03185                             ep0->dwc_ep.type, ep0->dwc_ep.maxpacket);
+-03186 #endif
+-03187                 if (core_if->dma_enable != 0) {
+-03188                         if (core_if->dma_desc_enable == 0) {
+-03189                                 deptsiz.d32 =
+-03190                                     DWC_READ_REG32(&core_if->
+-03191                                                    dev_if->out_ep_regs[0]->
+-03192                                                    doeptsiz);
+-03193                                 byte_count =
+-03194                                     ep0->dwc_ep.maxpacket - deptsiz.b.xfersize;
+-03195                         } else {
+-03196                                 desc_sts =
+-03197                                     core_if->dev_if->out_desc_addr->status;
+-03198                                 byte_count =
+-03199                                     ep0->dwc_ep.maxpacket - desc_sts.b.bytes;
+-03200                         }
+-03201                         ep0->dwc_ep.xfer_count += byte_count;
+-03202                         ep0->dwc_ep.xfer_buff += byte_count;
+-03203                         ep0->dwc_ep.dma_addr += byte_count;
+-03204                 }
+-03205                 if (ep0->dwc_ep.xfer_count < ep0->dwc_ep.total_len) {
+-03206                         dwc_otg_ep0_continue_transfer(GET_CORE_IF(pcd),
+-03207                                                       &ep0->dwc_ep);
+-03208                         DWC_DEBUGPL(DBG_PCD, "CONTINUE TRANSFER\n");
+-03209                 } else if (ep0->dwc_ep.sent_zlp) {
+-03210                         dwc_otg_ep0_continue_transfer(GET_CORE_IF(pcd),
+-03211                                                       &ep0->dwc_ep);
+-03212                         ep0->dwc_ep.sent_zlp = 0;
+-03213                         DWC_DEBUGPL(DBG_PCD, "CONTINUE TRANSFER\n");
+-03214                 } else {
+-03215                         ep0_complete_request(ep0);
+-03216                         DWC_DEBUGPL(DBG_PCD, "COMPLETE TRANSFER\n");
+-03217                 }
+-03218                 break;
+-03219 
+-03220         case EP0_IN_STATUS_PHASE:
+-03221         case EP0_OUT_STATUS_PHASE:
+-03222                 DWC_DEBUGPL(DBG_PCD, "CASE: EP0_STATUS\n");
+-03223                 ep0_complete_request(ep0);
+-03224                 pcd->ep0state = EP0_IDLE;
+-03225                 ep0->stopped = 1;
+-03226                 ep0->dwc_ep.is_in = 0;  /* OUT for next SETUP */
+-03227 
+-03228                 /* Prepare for more SETUP Packets */
+-03229                 if (core_if->dma_enable) {
+-03230                         ep0_out_start(core_if, pcd);
+-03231                 }
+-03232                 break;
+-03233 
+-03234         case EP0_STALL:
+-03235                 DWC_ERROR("EP0 STALLed, should not get here pcd_setup()\n");
+-03236                 break;
+-03237         }
+-03238 #ifdef DEBUG_EP0
+-03239         print_ep0_state(pcd);
+-03240 #endif
+-03241 }
+-03242 
+-03246 static void restart_transfer(dwc_otg_pcd_t * pcd, const uint32_t epnum)
+-03247 {
+-03248         dwc_otg_core_if_t *core_if;
+-03249         dwc_otg_dev_if_t *dev_if;
+-03250         deptsiz_data_t dieptsiz = {.d32 = 0 };
+-03251         dwc_otg_pcd_ep_t *ep;
+-03252 
+-03253         ep = get_in_ep(pcd, epnum);
+-03254 
+-03255 #ifdef DWC_EN_ISOC
+-03256         if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) {
+-03257                 return;
+-03258         }
+-03259 #endif /* DWC_EN_ISOC  */
+-03260 
+-03261         core_if = GET_CORE_IF(pcd);
+-03262         dev_if = core_if->dev_if;
+-03263 
+-03264         dieptsiz.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->dieptsiz);
+-03265 
+-03266         DWC_DEBUGPL(DBG_PCD, "xfer_buff=%p xfer_count=%0x xfer_len=%0x"
+-03267                     " stopped=%d\n", ep->dwc_ep.xfer_buff,
+-03268                     ep->dwc_ep.xfer_count, ep->dwc_ep.xfer_len, ep->stopped);
+-03269         /*
+-03270          * If xfersize is 0 and pktcnt in not 0, resend the last packet.
+-03271          */
+-03272         if (dieptsiz.b.pktcnt && dieptsiz.b.xfersize == 0 &&
+-03273             ep->dwc_ep.start_xfer_buff != 0) {
+-03274                 if (ep->dwc_ep.total_len <= ep->dwc_ep.maxpacket) {
+-03275                         ep->dwc_ep.xfer_count = 0;
+-03276                         ep->dwc_ep.xfer_buff = ep->dwc_ep.start_xfer_buff;
+-03277                         ep->dwc_ep.xfer_len = ep->dwc_ep.xfer_count;
+-03278                 } else {
+-03279                         ep->dwc_ep.xfer_count -= ep->dwc_ep.maxpacket;
+-03280                         /* convert packet size to dwords. */
+-03281                         ep->dwc_ep.xfer_buff -= ep->dwc_ep.maxpacket;
+-03282                         ep->dwc_ep.xfer_len = ep->dwc_ep.xfer_count;
+-03283                 }
+-03284                 ep->stopped = 0;
+-03285                 DWC_DEBUGPL(DBG_PCD, "xfer_buff=%p xfer_count=%0x "
+-03286                             "xfer_len=%0x stopped=%d\n",
+-03287                             ep->dwc_ep.xfer_buff,
+-03288                             ep->dwc_ep.xfer_count, ep->dwc_ep.xfer_len,
+-03289                             ep->stopped);
+-03290                 if (epnum == 0) {
+-03291                         dwc_otg_ep0_start_transfer(core_if, &ep->dwc_ep);
+-03292                 } else {
+-03293                         dwc_otg_ep_start_transfer(core_if, &ep->dwc_ep);
+-03294                 }
+-03295         }
+-03296 }
+-03297 
+-03298 /*
+-03299  * This function create new nextep sequnce based on Learn Queue.
+-03300  *
+-03301  * @param core_if Programming view of DWC_otg controller
+-03302  */
+-03303 void predict_nextep_seq( dwc_otg_core_if_t * core_if)
+-03304 {
+-03305         dwc_otg_device_global_regs_t *dev_global_regs =
+-03306             core_if->dev_if->dev_global_regs;
+-03307         const uint32_t TOKEN_Q_DEPTH = core_if->hwcfg2.b.dev_token_q_depth;
+-03308         /* Number of Token Queue Registers */
+-03309         const int DTKNQ_REG_CNT = (TOKEN_Q_DEPTH + 7) / 8;
+-03310         dtknq1_data_t dtknqr1;
+-03311         uint32_t in_tkn_epnums[4];
+-03312         uint8_t seqnum[MAX_EPS_CHANNELS];
+-03313         uint8_t intkn_seq[TOKEN_Q_DEPTH];
+-03314         grstctl_t resetctl = {.d32 = 0 };
+-03315         uint8_t temp;
+-03316         int ndx = 0;
+-03317         int start = 0;
+-03318         int end = 0;
+-03319         int sort_done = 0;
+-03320         int i = 0;
+-03321         volatile uint32_t *addr = &dev_global_regs->dtknqr1;
+-03322 
+-03323 
+-03324         DWC_DEBUGPL(DBG_PCD,"dev_token_q_depth=%d\n",TOKEN_Q_DEPTH);
+-03325 
+-03326         /* Read the DTKNQ Registers */
+-03327         for (i = 0; i < DTKNQ_REG_CNT; i++) {
+-03328                 in_tkn_epnums[i] = DWC_READ_REG32(addr);
+-03329                 DWC_DEBUGPL(DBG_PCDV, "DTKNQR%d=0x%08x\n", i + 1,
+-03330                             in_tkn_epnums[i]);
+-03331                 if (addr == &dev_global_regs->dvbusdis) {
+-03332                         addr = &dev_global_regs->dtknqr3_dthrctl;
+-03333                 } else {
+-03334                         ++addr;
+-03335                 }
+-03336 
+-03337         }
+-03338 
+-03339         /* Copy the DTKNQR1 data to the bit field. */
+-03340         dtknqr1.d32 = in_tkn_epnums[0];
+-03341         if (dtknqr1.b.wrap_bit) {
+-03342                 ndx = dtknqr1.b.intknwptr;
+-03343                 end = ndx -1;
+-03344                 if (end < 0) 
+-03345                         end = TOKEN_Q_DEPTH -1;
+-03346         } else {
+-03347                 ndx = 0;
+-03348                 end = dtknqr1.b.intknwptr -1;
+-03349                 if (end < 0) 
+-03350                         end = 0;
+-03351         }
+-03352         start = ndx;
+-03353         
+-03354         /* Fill seqnum[] by initial values: EP number + 31 */
+-03355         for (i=0; i <= core_if->dev_if->num_in_eps; i++) {
+-03356                 seqnum[i] = i +31;
+-03357         }
+-03358         
+-03359         /* Fill intkn_seq[] from in_tkn_epnums[0] */
+-03360         for (i=0; i < 6; i++) 
+-03361                 intkn_seq[i] = (in_tkn_epnums[0] >> ((7-i) * 4)) & 0xf;
+-03362         
+-03363         if (TOKEN_Q_DEPTH > 6) {
+-03364                 /* Fill intkn_seq[] from in_tkn_epnums[1] */
+-03365                 for (i=6; i < 14; i++) 
+-03366                         intkn_seq[i] = (in_tkn_epnums[1] >> ((7-(i-6)) * 4)) & 0xf;
+-03367         }
+-03368         
+-03369         if (TOKEN_Q_DEPTH > 14) {
+-03370                 /* Fill intkn_seq[] from in_tkn_epnums[1] */
+-03371                 for (i=14; i < 22; i++) 
+-03372                         intkn_seq[i] = (in_tkn_epnums[2] >> ((7-(i-14)) * 4)) & 0xf;
+-03373         }
+-03374 
+-03375         if (TOKEN_Q_DEPTH > 22) {
+-03376                 /* Fill intkn_seq[] from in_tkn_epnums[1] */
+-03377                 for (i=22; i < 30; i++) 
+-03378                         intkn_seq[i] = (in_tkn_epnums[3] >> ((7-(i-22)) * 4)) & 0xf;
+-03379         }
+-03380 
+-03381         DWC_DEBUGPL(DBG_PCDV,"%s start=%d end=%d intkn_seq[]:\n", __func__, start, end);
+-03382         for (i=0; i<TOKEN_Q_DEPTH; i++) 
+-03383                 DWC_DEBUGPL(DBG_PCDV,"%d\n", intkn_seq[i]);
+-03384 
+-03385         /* Update seqnum based on intkn_seq[] */
+-03386         i = 0;
+-03387         do {
+-03388                 seqnum[intkn_seq[ndx]] = i;
+-03389                 ndx++;
+-03390                 i++;
+-03391                 if (ndx == TOKEN_Q_DEPTH) 
+-03392                         ndx = 0;
+-03393         } while ( i < TOKEN_Q_DEPTH );
+-03394         
+-03395         /* Mark non active EP's in seqnum[] by 0xff */
+-03396         for (i=0; i<=core_if->dev_if->num_in_eps; i++) {
+-03397                 if (core_if->nextep_seq[i] == 0xff )
+-03398                         seqnum[i] = 0xff;
+-03399         }
+-03400         
+-03401         /* Sort seqnum[] */
+-03402         sort_done = 0;
+-03403         while (!sort_done) {
+-03404                 sort_done = 1;
+-03405                 for (i=0; i<core_if->dev_if->num_in_eps; i++) {
+-03406                         if (seqnum[i] > seqnum[i+1]) {
+-03407                                 temp = seqnum[i];
+-03408                                 seqnum[i] = seqnum[i+1];
+-03409                                 seqnum[i+1] = temp;
+-03410                                 sort_done = 0;
+-03411                         }
+-03412                 }
+-03413         }
+-03414 
+-03415         ndx = start + seqnum[0];
+-03416         if (ndx >= TOKEN_Q_DEPTH) 
+-03417                 ndx = ndx % TOKEN_Q_DEPTH;
+-03418         core_if->first_in_nextep_seq = intkn_seq[ndx];
+-03419         
+-03420         /* Update seqnum[] by EP numbers  */
+-03421         for (i=0; i<=core_if->dev_if->num_in_eps; i++) {
+-03422                 ndx = start + i;
+-03423                 if (seqnum[i] < 31) {
+-03424                         ndx = start + seqnum[i];
+-03425                         if (ndx >= TOKEN_Q_DEPTH) 
+-03426                                 ndx = ndx % TOKEN_Q_DEPTH;
+-03427                         seqnum[i] = intkn_seq[ndx];
+-03428                 } else {
+-03429                         if (seqnum[i] < 0xff) {
+-03430                                 seqnum[i] = seqnum[i] - 31;
+-03431                         } else {
+-03432                                 break;
+-03433                         }
+-03434                 }
+-03435         }
+-03436 
+-03437         /* Update nextep_seq[] based on seqnum[] */
+-03438         for (i=0; i<core_if->dev_if->num_in_eps; i++) {
+-03439                 if (seqnum[i] != 0xff) {
+-03440                         if (seqnum[i+1] != 0xff) {
+-03441                                 core_if->nextep_seq[seqnum[i]] = seqnum[i+1];
+-03442                         } else {
+-03443                                 core_if->nextep_seq[seqnum[i]] = core_if->first_in_nextep_seq;
+-03444                                 break;
+-03445                         }
+-03446                 } else {
+-03447                         break;
+-03448                 }
+-03449         }
+-03450         
+-03451         DWC_DEBUGPL(DBG_PCDV, "%s first_in_nextep_seq= %2d; nextep_seq[]:\n", 
+-03452                 __func__, core_if->first_in_nextep_seq);
+-03453         for (i=0; i <= core_if->dev_if->num_in_eps; i++) {
+-03454                 DWC_DEBUGPL(DBG_PCDV,"%2d\n", core_if->nextep_seq[i]);
+-03455         }
+-03456 
+-03457         /* Flush the Learning Queue */
+-03458         resetctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->grstctl);
+-03459         resetctl.b.intknqflsh = 1;
+-03460         DWC_WRITE_REG32(&core_if->core_global_regs->grstctl, resetctl.d32);
+-03461         
+-03462 
+-03463 }
+-03464 
+-03468 static inline void handle_in_ep_disable_intr(dwc_otg_pcd_t * pcd,
+-03469                                              const uint32_t epnum)
+-03470 {
+-03471         dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
+-03472         dwc_otg_dev_if_t *dev_if = core_if->dev_if;
+-03473         deptsiz_data_t dieptsiz = {.d32 = 0 };
+-03474         dctl_data_t dctl = {.d32 = 0 };
+-03475         dwc_otg_pcd_ep_t *ep;
+-03476         dwc_ep_t *dwc_ep;
+-03477         gintmsk_data_t gintmsk_data;
+-03478         depctl_data_t depctl;
+-03479         uint32_t diepdma;
+-03480         uint32_t remain_to_transfer = 0;
+-03481         uint8_t i;
+-03482         uint32_t xfer_size;
+-03483         
+-03484         ep = get_in_ep(pcd, epnum);
+-03485         dwc_ep = &ep->dwc_ep;
+-03486 
+-03487         if (dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) {
+-03488                 dwc_otg_flush_tx_fifo(core_if, dwc_ep->tx_fifo_num);
+-03489                 complete_ep(ep);
+-03490                 return;
+-03491         }
+-03492 
+-03493         DWC_DEBUGPL(DBG_PCD, "diepctl%d=%0x\n", epnum,
+-03494                     DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->diepctl));
+-03495         dieptsiz.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->dieptsiz);
+-03496         depctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->diepctl);
+-03497 
+-03498         DWC_DEBUGPL(DBG_ANY, "pktcnt=%d size=%d\n",
+-03499                     dieptsiz.b.pktcnt, dieptsiz.b.xfersize);
+-03500         
+-03501         if ((core_if->start_predict == 0) || (depctl.b.eptype & 1)) { 
+-03502                 if (ep->stopped) {
+-03503                         if (core_if->en_multiple_tx_fifo)
+-03504                                 /* Flush the Tx FIFO */
+-03505                                 dwc_otg_flush_tx_fifo(core_if, dwc_ep->tx_fifo_num);
+-03506                         /* Clear the Global IN NP NAK */
+-03507                         dctl.d32 = 0;
+-03508                         dctl.b.cgnpinnak = 1;
+-03509                         DWC_MODIFY_REG32(&dev_if->dev_global_regs->dctl, dctl.d32, dctl.d32); 
+-03510                         /* Restart the transaction */
+-03511                         if (dieptsiz.b.pktcnt != 0 || dieptsiz.b.xfersize != 0) {
+-03512                                 restart_transfer(pcd, epnum);
+-03513                         }
+-03514                 } else {
+-03515                         /* Restart the transaction */
+-03516                         if (dieptsiz.b.pktcnt != 0 || dieptsiz.b.xfersize != 0) {
+-03517                                 restart_transfer(pcd, epnum);
+-03518                         }
+-03519                         DWC_DEBUGPL(DBG_ANY, "STOPPED!!!\n");
+-03520                 }
+-03521                 return;
+-03522         }
+-03523 
+-03524         if (core_if->start_predict > 2) {       // NP IN EP
+-03525                 core_if->start_predict--;
+-03526                 return;
+-03527         }
+-03528 
+-03529         core_if->start_predict--;
+-03530         
+-03531         if (core_if->start_predict == 1) {      // All NP IN Ep's disabled now
+-03532 
+-03533                 predict_nextep_seq(core_if);
+-03534                         
+-03535                 /* Update all active IN EP's NextEP field based of nextep_seq[] */
+-03536                 for ( i = 0; i <= core_if->dev_if->num_in_eps; i++) {
+-03537                         depctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl);
+-03538                         if (core_if->nextep_seq[i] != 0xff) {   // Active NP IN EP
+-03539                                 depctl.b.nextep = core_if->nextep_seq[i];
+-03540                                 DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->diepctl, depctl.d32);
+-03541                         }
+-03542                 }
+-03543                 /* Flush Shared NP TxFIFO */
+-03544                 dwc_otg_flush_tx_fifo(core_if, 0);
+-03545                 /* Rewind buffers */
+-03546                 if (!core_if->dma_desc_enable) {                
+-03547                         i = core_if->first_in_nextep_seq;
+-03548                         do {
+-03549                                 ep = get_in_ep(pcd, i);
+-03550                                 dieptsiz.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[i]->dieptsiz);
+-03551                                 xfer_size = ep->dwc_ep.total_len - ep->dwc_ep.xfer_count;
+-03552                                 if (xfer_size > ep->dwc_ep.maxxfer) 
+-03553                                         xfer_size = ep->dwc_ep.maxxfer;
+-03554                                 depctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl);
+-03555                                 if (dieptsiz.b.pktcnt != 0) {
+-03556                                         if (xfer_size == 0) {
+-03557                                                 remain_to_transfer = 0;
+-03558                                         } else {
+-03559                                                 if ((xfer_size % ep->dwc_ep.maxpacket) == 0) {
+-03560                                                         remain_to_transfer = 
+-03561                                                                 dieptsiz.b.pktcnt * ep->dwc_ep.maxpacket;
+-03562                                                 } else {
+-03563                                                         remain_to_transfer = ((dieptsiz.b.pktcnt -1) * ep->dwc_ep.maxpacket) 
+-03564                                                                 + (xfer_size % ep->dwc_ep.maxpacket);
+-03565                                                 }
+-03566                                         }
+-03567                                         diepdma = DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepdma);
+-03568                                         dieptsiz.b.xfersize = remain_to_transfer;
+-03569                                         DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->dieptsiz, dieptsiz.d32);
+-03570                                         diepdma = ep->dwc_ep.dma_addr + (xfer_size - remain_to_transfer);
+-03571                                         DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->diepdma, diepdma);
+-03572                                 }
+-03573                                 i = core_if->nextep_seq[i];
+-03574                         } while (i != core_if->first_in_nextep_seq);
+-03575                 } else { // dma_desc_enable
+-03576                                 DWC_PRINTF("%s Learning Queue not supported in DDMA\n", __func__);
+-03577                 }
+-03578                                 
+-03579                 /* Restart transfers in predicted sequences */
+-03580                 i = core_if->first_in_nextep_seq;
+-03581                 do {
+-03582                         dieptsiz.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[i]->dieptsiz);
+-03583                         depctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl);
+-03584                         if (dieptsiz.b.pktcnt != 0) {
+-03585                                 depctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl);
+-03586                                 depctl.b.epena = 1;
+-03587                                 depctl.b.cnak = 1;
+-03588                                 DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->diepctl, depctl.d32);
+-03589                         }
+-03590                         i = core_if->nextep_seq[i];
+-03591                 } while (i != core_if->first_in_nextep_seq);
+-03592 
+-03593                 /* Clear the global non-periodic IN NAK handshake */
+-03594                 dctl.d32 = 0;
+-03595                 dctl.b.cgnpinnak = 1;
+-03596                 DWC_MODIFY_REG32(&dev_if->dev_global_regs->dctl, dctl.d32, dctl.d32); 
+-03597                         
+-03598                 /* Unmask EP Mismatch interrupt */
+-03599                 gintmsk_data.d32 = 0;
+-03600                 gintmsk_data.b.epmismatch = 1;
+-03601                 DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, 0, gintmsk_data.d32);
+-03602                 
+-03603                 core_if->start_predict = 0;
+-03604 
+-03605         } 
+-03606 }
+-03607 
+-03611 static inline void handle_in_ep_timeout_intr(dwc_otg_pcd_t * pcd,
+-03612                                              const uint32_t epnum)
+-03613 {
+-03614         dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
+-03615         dwc_otg_dev_if_t *dev_if = core_if->dev_if;
+-03616 
+-03617 #ifdef DEBUG
+-03618         deptsiz_data_t dieptsiz = {.d32 = 0 };
+-03619         uint32_t num = 0;
+-03620 #endif
+-03621         dctl_data_t dctl = {.d32 = 0 };
+-03622         dwc_otg_pcd_ep_t *ep;
+-03623 
+-03624         gintmsk_data_t intr_mask = {.d32 = 0 };
+-03625 
+-03626         ep = get_in_ep(pcd, epnum);
+-03627 
+-03628         /* Disable the NP Tx Fifo Empty Interrrupt */
+-03629         if (!core_if->dma_enable) {
+-03630                 intr_mask.b.nptxfempty = 1;
+-03631                 DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk,
+-03632                                  intr_mask.d32, 0);
+-03633         }
+-03636         /*
+-03637          * Non-periodic EP
+-03638          */
+-03639         /* Enable the Global IN NAK Effective Interrupt */
+-03640         intr_mask.b.ginnakeff = 1;
+-03641         DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, 0, intr_mask.d32);
+-03642 
+-03643         /* Set Global IN NAK */
+-03644         dctl.b.sgnpinnak = 1;
+-03645         DWC_MODIFY_REG32(&dev_if->dev_global_regs->dctl, dctl.d32, dctl.d32);
+-03646 
+-03647         ep->stopped = 1;
+-03648 
+-03649 #ifdef DEBUG
+-03650         dieptsiz.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[num]->dieptsiz);
+-03651         DWC_DEBUGPL(DBG_ANY, "pktcnt=%d size=%d\n",
+-03652                     dieptsiz.b.pktcnt, dieptsiz.b.xfersize);
+-03653 #endif
+-03654 
+-03655 #ifdef DISABLE_PERIODIC_EP
+-03656         /*
+-03657          * Set the NAK bit for this EP to
+-03658          * start the disable process.
+-03659          */
+-03660         diepctl.d32 = 0;
+-03661         diepctl.b.snak = 1;
+-03662         DWC_MODIFY_REG32(&dev_if->in_ep_regs[num]->diepctl, diepctl.d32,
+-03663                          diepctl.d32);
+-03664         ep->disabling = 1;
+-03665         ep->stopped = 1;
+-03666 #endif
+-03667 }
+-03668 
+-03672 static inline int32_t handle_in_ep_nak_intr(dwc_otg_pcd_t * pcd,
+-03673                                             const uint32_t epnum)
+-03674 {
+-03676         dwc_otg_core_if_t *core_if;
+-03677         diepmsk_data_t intr_mask = {.d32 = 0 };
+-03678 
+-03679         DWC_PRINTF("INTERRUPT Handler not implemented for %s\n", "IN EP NAK");
+-03680         core_if = GET_CORE_IF(pcd);
+-03681         intr_mask.b.nak = 1;
+-03682 
+-03683         if (core_if->multiproc_int_enable) {
+-03684                 DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->
+-03685                                  diepeachintmsk[epnum], intr_mask.d32, 0);
+-03686         } else {
+-03687                 DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->diepmsk,
+-03688                                  intr_mask.d32, 0);
+-03689         }
+-03690 
+-03691         return 1;
+-03692 }
+-03693 
+-03697 static inline int32_t handle_out_ep_babble_intr(dwc_otg_pcd_t * pcd,
+-03698                                                 const uint32_t epnum)
+-03699 {
+-03701         dwc_otg_core_if_t *core_if;
+-03702         doepmsk_data_t intr_mask = {.d32 = 0 };
+-03703 
+-03704         DWC_PRINTF("INTERRUPT Handler not implemented for %s\n",
+-03705                    "OUT EP Babble");
+-03706         core_if = GET_CORE_IF(pcd);
+-03707         intr_mask.b.babble = 1;
+-03708 
+-03709         if (core_if->multiproc_int_enable) {
+-03710                 DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->
+-03711                                  doepeachintmsk[epnum], intr_mask.d32, 0);
+-03712         } else {
+-03713                 DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->doepmsk,
+-03714                                  intr_mask.d32, 0);
+-03715         }
+-03716 
+-03717         return 1;
+-03718 }
+-03719 
+-03723 static inline int32_t handle_out_ep_nak_intr(dwc_otg_pcd_t * pcd,
+-03724                                              const uint32_t epnum)
+-03725 {
+-03727         dwc_otg_core_if_t *core_if;
+-03728         doepmsk_data_t intr_mask = {.d32 = 0 };
+-03729 
+-03730         DWC_PRINTF("INTERRUPT Handler not implemented for %s\n", "OUT EP NAK");
+-03731         core_if = GET_CORE_IF(pcd);
+-03732         intr_mask.b.nak = 1;
+-03733 
+-03734         if (core_if->multiproc_int_enable) {
+-03735                 DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->
+-03736                                  doepeachintmsk[epnum], intr_mask.d32, 0);
+-03737         } else {
+-03738                 DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->doepmsk,
+-03739                                  intr_mask.d32, 0);
+-03740         }
+-03741 
+-03742         return 1;
+-03743 }
+-03744 
+-03748 static inline int32_t handle_out_ep_nyet_intr(dwc_otg_pcd_t * pcd,
+-03749                                               const uint32_t epnum)
+-03750 {
+-03752         dwc_otg_core_if_t *core_if;
+-03753         doepmsk_data_t intr_mask = {.d32 = 0 };
+-03754 
+-03755         DWC_PRINTF("INTERRUPT Handler not implemented for %s\n", "OUT EP NYET");
+-03756         core_if = GET_CORE_IF(pcd);
+-03757         intr_mask.b.nyet = 1;
+-03758 
+-03759         if (core_if->multiproc_int_enable) {
+-03760                 DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->
+-03761                                  doepeachintmsk[epnum], intr_mask.d32, 0);
+-03762         } else {
+-03763                 DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->doepmsk,
+-03764                                  intr_mask.d32, 0);
+-03765         }
+-03766 
+-03767         return 1;
+-03768 }
+-03769 
+-03786 static int32_t dwc_otg_pcd_handle_in_ep_intr(dwc_otg_pcd_t * pcd)
+-03787 {
+-03788 #define CLEAR_IN_EP_INTR(__core_if,__epnum,__intr) \
+-03789 do { \
+-03790                 diepint_data_t diepint = {.d32=0}; \
+-03791                 diepint.b.__intr = 1; \
+-03792                 DWC_WRITE_REG32(&__core_if->dev_if->in_ep_regs[__epnum]->diepint, \
+-03793                 diepint.d32); \
+-03794 } while (0)
+-03795 
+-03796         dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
+-03797         dwc_otg_dev_if_t *dev_if = core_if->dev_if;
+-03798         diepint_data_t diepint = {.d32 = 0 };
+-03799         depctl_data_t depctl = {.d32 = 0 };
+-03800         uint32_t ep_intr;
+-03801         uint32_t epnum = 0;
+-03802         dwc_otg_pcd_ep_t *ep;
+-03803         dwc_ep_t *dwc_ep;
+-03804         gintmsk_data_t intr_mask = {.d32 = 0 };
+-03805 
+-03806         DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, pcd);
+-03807 
+-03808         /* Read in the device interrupt bits */
+-03809         ep_intr = dwc_otg_read_dev_all_in_ep_intr(core_if);
+-03810 
+-03811         /* Service the Device IN interrupts for each endpoint */
+-03812         while (ep_intr) {
+-03813                 if (ep_intr & 0x1) {
+-03814                         uint32_t empty_msk;
+-03815                         /* Get EP pointer */
+-03816                         ep = get_in_ep(pcd, epnum);
+-03817                         dwc_ep = &ep->dwc_ep;
+-03818 
+-03819                         depctl.d32 =
+-03820                             DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->diepctl);
+-03821                         empty_msk =
+-03822                             DWC_READ_REG32(&dev_if->
+-03823                                            dev_global_regs->dtknqr4_fifoemptymsk);
+-03824 
+-03825                         DWC_DEBUGPL(DBG_PCDV,
+-03826                                     "IN EP INTERRUPT - %d\nepmty_msk - %8x  diepctl - %8x\n",
+-03827                                     epnum, empty_msk, depctl.d32);
+-03828 
+-03829                         DWC_DEBUGPL(DBG_PCD,
+-03830                                     "EP%d-%s: type=%d, mps=%d\n",
+-03831                                     dwc_ep->num, (dwc_ep->is_in ? "IN" : "OUT"),
+-03832                                     dwc_ep->type, dwc_ep->maxpacket);
+-03833 
+-03834                         diepint.d32 =
+-03835                             dwc_otg_read_dev_in_ep_intr(core_if, dwc_ep);
+-03836 
+-03837                         DWC_DEBUGPL(DBG_PCDV,
+-03838                                     "EP %d Interrupt Register - 0x%x\n", epnum,
+-03839                                     diepint.d32);
+-03840                         /* Transfer complete */
+-03841                         if (diepint.b.xfercompl) {
+-03842                                 /* Disable the NP Tx FIFO Empty
+-03843                                  * Interrrupt */
+-03844                                 if (core_if->en_multiple_tx_fifo == 0) {
+-03845                                         intr_mask.b.nptxfempty = 1;
+-03846                                         DWC_MODIFY_REG32
+-03847                                             (&core_if->core_global_regs->gintmsk,
+-03848                                              intr_mask.d32, 0);
+-03849                                 } else {
+-03850                                         /* Disable the Tx FIFO Empty Interrupt for this EP */
+-03851                                         uint32_t fifoemptymsk =
+-03852                                             0x1 << dwc_ep->num;
+-03853                                         DWC_MODIFY_REG32(&core_if->
+-03854                                                          dev_if->dev_global_regs->dtknqr4_fifoemptymsk,
+-03855                                                          fifoemptymsk, 0);
+-03856                                 }
+-03857                                 /* Clear the bit in DIEPINTn for this interrupt */
+-03858                                 CLEAR_IN_EP_INTR(core_if, epnum, xfercompl);
+-03859 
+-03860                                 /* Complete the transfer */
+-03861                                 if (epnum == 0) {
+-03862                                         handle_ep0(pcd);
+-03863                                 }
+-03864 #ifdef DWC_EN_ISOC
+-03865                                 else if (dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) {
+-03866                                         if (!ep->stopped)
+-03867                                                 complete_iso_ep(pcd, ep);
+-03868                                 }
+-03869 #endif /* DWC_EN_ISOC */
+-03870 #ifdef DWC_UTE_PER_IO
+-03871                                 else if (dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) {
+-03872                                         if (!ep->stopped)
+-03873                                                 complete_xiso_ep(ep);
+-03874                                 }
+-03875 #endif /* DWC_UTE_PER_IO */
+-03876                                 else {
+-03877                                         if (dwc_ep->type == DWC_OTG_EP_TYPE_ISOC && 
+-03878                                                         dwc_ep->bInterval > 1) {
+-03879                                                 dwc_ep->frame_num += dwc_ep->bInterval;
+-03880                                                 if (dwc_ep->frame_num > 0x3FFF)
+-03881                                                 {
+-03882                                                         dwc_ep->frm_overrun = 1;
+-03883                                                         dwc_ep->frame_num &= 0x3FFF;
+-03884                                                 } else 
+-03885                                                         dwc_ep->frm_overrun = 0;
+-03886                                         }
+-03887                                         complete_ep(ep);
+-03888                                         if(diepint.b.nak)
+-03889                                                 CLEAR_IN_EP_INTR(core_if, epnum, nak);
+-03890                                 }
+-03891                         }
+-03892                         /* Endpoint disable      */
+-03893                         if (diepint.b.epdisabled) {
+-03894                                 DWC_DEBUGPL(DBG_ANY, "EP%d IN disabled\n",
+-03895                                             epnum);
+-03896                                 handle_in_ep_disable_intr(pcd, epnum);
+-03897 
+-03898                                 /* Clear the bit in DIEPINTn for this interrupt */
+-03899                                 CLEAR_IN_EP_INTR(core_if, epnum, epdisabled);
+-03900                         }
+-03901                         /* AHB Error */
+-03902                         if (diepint.b.ahberr) {
+-03903                                 DWC_ERROR("EP%d IN AHB Error\n", epnum);
+-03904                                 /* Clear the bit in DIEPINTn for this interrupt */
+-03905                                 CLEAR_IN_EP_INTR(core_if, epnum, ahberr);
+-03906                         }
+-03907                         /* TimeOUT Handshake (non-ISOC IN EPs) */
+-03908                         if (diepint.b.timeout) {
+-03909                                 DWC_ERROR("EP%d IN Time-out\n", epnum);
+-03910                                 handle_in_ep_timeout_intr(pcd, epnum);
+-03911 
+-03912                                 CLEAR_IN_EP_INTR(core_if, epnum, timeout);
+-03913                         }
+-03915                         if (diepint.b.intktxfemp) {
+-03916                                 DWC_DEBUGPL(DBG_ANY,
+-03917                                             "EP%d IN TKN TxFifo Empty\n",
+-03918                                             epnum);
+-03919                                 if (!ep->stopped && epnum != 0) {
+-03920 
+-03921                                         diepmsk_data_t diepmsk = {.d32 = 0 };
+-03922                                         diepmsk.b.intktxfemp = 1;
+-03923 
+-03924                                         if (core_if->multiproc_int_enable) {
+-03925                                                 DWC_MODIFY_REG32
+-03926                                                     (&dev_if->dev_global_regs->diepeachintmsk
+-03927                                                      [epnum], diepmsk.d32, 0);
+-03928                                         } else {
+-03929                                                 DWC_MODIFY_REG32
+-03930                                                     (&dev_if->dev_global_regs->diepmsk,
+-03931                                                      diepmsk.d32, 0);
+-03932                                         }
+-03933                                 } else if (core_if->dma_desc_enable
+-03934                                            && epnum == 0
+-03935                                            && pcd->ep0state ==
+-03936                                            EP0_OUT_STATUS_PHASE) {
+-03937                                         // EP0 IN set STALL
+-03938                                         depctl.d32 =
+-03939                                             DWC_READ_REG32(&dev_if->in_ep_regs
+-03940                                                            [epnum]->diepctl);
+-03941 
+-03942                                         /* set the disable and stall bits */
+-03943                                         if (depctl.b.epena) {
+-03944                                                 depctl.b.epdis = 1;
+-03945                                         }
+-03946                                         depctl.b.stall = 1;
+-03947                                         DWC_WRITE_REG32(&dev_if->in_ep_regs
+-03948                                                         [epnum]->diepctl,
+-03949                                                         depctl.d32);
+-03950                                 }
+-03951                                 CLEAR_IN_EP_INTR(core_if, epnum, intktxfemp);
+-03952                         }
+-03954                         if (diepint.b.intknepmis) {
+-03955                                 DWC_DEBUGPL(DBG_ANY,
+-03956                                             "EP%d IN TKN EP Mismatch\n", epnum);
+-03957                                 CLEAR_IN_EP_INTR(core_if, epnum, intknepmis);                           
+-03958                         }
+-03960                         if (diepint.b.inepnakeff) {
+-03961                                 DWC_DEBUGPL(DBG_ANY,
+-03962                                             "EP%d IN EP NAK Effective\n",
+-03963                                             epnum);
+-03964                                 /* Periodic EP */
+-03965                                 if (ep->disabling) {
+-03966                                         depctl.d32 = 0;
+-03967                                         depctl.b.snak = 1;
+-03968                                         depctl.b.epdis = 1;
+-03969                                         DWC_MODIFY_REG32(&dev_if->in_ep_regs
+-03970                                                          [epnum]->diepctl,
+-03971                                                          depctl.d32,
+-03972                                                          depctl.d32);
+-03973                                 }
+-03974                                 CLEAR_IN_EP_INTR(core_if, epnum, inepnakeff);
+-03975 
+-03976                         }
+-03977 
+-03979                         if (diepint.b.emptyintr) {
+-03980                                 DWC_DEBUGPL(DBG_ANY,
+-03981                                             "EP%d Tx FIFO Empty Intr \n",
+-03982                                             epnum);
+-03983                                 write_empty_tx_fifo(pcd, epnum);
+-03984 
+-03985                                 CLEAR_IN_EP_INTR(core_if, epnum, emptyintr);
+-03986 
+-03987                         }
+-03988 
+-03990                         if (diepint.b.bna) {
+-03991                                 CLEAR_IN_EP_INTR(core_if, epnum, bna);
+-03992                                 if (core_if->dma_desc_enable) {
+-03993 #ifdef DWC_EN_ISOC
+-03994                                         if (dwc_ep->type ==
+-03995                                             DWC_OTG_EP_TYPE_ISOC) {
+-03996                                                 /*
+-03997                                                  * This checking is performed to prevent first "false" BNA
+-03998                                                  * handling occuring right after reconnect
+-03999                                                  */
+-04000                                                 if (dwc_ep->next_frame !=
+-04001                                                     0xffffffff)
+-04002                                                         dwc_otg_pcd_handle_iso_bna(ep);
+-04003                                         } else
+-04004 #endif                          /* DWC_EN_ISOC */
+-04005                                         {
+-04006                                                 dwc_otg_pcd_handle_noniso_bna(ep);
+-04007                                         }
+-04008                                 }
+-04009                         }
+-04010                         /* NAK Interrutp */
+-04011                         if (diepint.b.nak) {
+-04012                                 DWC_DEBUGPL(DBG_ANY, "EP%d IN NAK Interrupt\n",
+-04013                                             epnum);
+-04014                                 if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC)
+-04015                                 {
+-04016                                         depctl_data_t depctl;
+-04017                                         if (ep->dwc_ep.frame_num == 0xFFFFFFFF) 
+-04018                                         {
+-04019                                                 ep->dwc_ep.frame_num = core_if->frame_num;
+-04020                                                 if (ep->dwc_ep.bInterval > 1) 
+-04021                                                 {
+-04022                                                         depctl.d32 = 0;
+-04023                                                         depctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->diepctl);
+-04024                                                         if (ep->dwc_ep.frame_num & 0x1) {
+-04025                                                                 depctl.b.setd1pid = 1;
+-04026                                                                 depctl.b.setd0pid = 0;
+-04027                                                         } else {
+-04028                                                                 depctl.b.setd0pid = 1;
+-04029                                                                 depctl.b.setd1pid = 0;
+-04030                                                         }
+-04031                                                         DWC_WRITE_REG32(&dev_if->in_ep_regs[epnum]->diepctl, depctl.d32);
+-04032                                                 }
+-04033                                                 start_next_request(ep);
+-04034                                         }
+-04035                                         ep->dwc_ep.frame_num += ep->dwc_ep.bInterval;
+-04036                                         if (dwc_ep->frame_num > 0x3FFF)
+-04037                                         {
+-04038                                                 dwc_ep->frm_overrun = 1;
+-04039                                                 dwc_ep->frame_num &= 0x3FFF;
+-04040                                         } else 
+-04041                                                 dwc_ep->frm_overrun = 0;
+-04042                                 }
+-04043 
+-04044                                 CLEAR_IN_EP_INTR(core_if, epnum, nak);
+-04045                         }
+-04046                 }
+-04047                 epnum++;
+-04048                 ep_intr >>= 1;
+-04049         }
+-04050 
+-04051         return 1;
+-04052 #undef CLEAR_IN_EP_INTR
+-04053 }
+-04054 
+-04068 static int32_t dwc_otg_pcd_handle_out_ep_intr(dwc_otg_pcd_t * pcd)
+-04069 {
+-04070 #define CLEAR_OUT_EP_INTR(__core_if,__epnum,__intr) \
+-04071 do { \
+-04072                 doepint_data_t doepint = {.d32=0}; \
+-04073                 doepint.b.__intr = 1; \
+-04074                 DWC_WRITE_REG32(&__core_if->dev_if->out_ep_regs[__epnum]->doepint, \
+-04075                 doepint.d32); \
+-04076 } while (0)
+-04077 
+-04078         dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
+-04079         uint32_t ep_intr;
+-04080         doepint_data_t doepint = {.d32 = 0 };
+-04081         uint32_t epnum = 0;
+-04082         dwc_otg_pcd_ep_t *ep;
+-04083         dwc_ep_t *dwc_ep;
+-04084         dctl_data_t dctl = {.d32 = 0 };
+-04085         gintmsk_data_t gintmsk = {.d32 = 0 };
+-04086 
+-04087 
+-04088         DWC_DEBUGPL(DBG_PCDV, "%s()\n", __func__);
+-04089 
+-04090         /* Read in the device interrupt bits */
+-04091         ep_intr = dwc_otg_read_dev_all_out_ep_intr(core_if);
+-04092 
+-04093         while (ep_intr) {
+-04094                 if (ep_intr & 0x1) {
+-04095                         /* Get EP pointer */
+-04096                         ep = get_out_ep(pcd, epnum);
+-04097                         dwc_ep = &ep->dwc_ep;
+-04098 
+-04099 #ifdef VERBOSE
+-04100                         DWC_DEBUGPL(DBG_PCDV,
+-04101                                     "EP%d-%s: type=%d, mps=%d\n",
+-04102                                     dwc_ep->num, (dwc_ep->is_in ? "IN" : "OUT"),
+-04103                                     dwc_ep->type, dwc_ep->maxpacket);
+-04104 #endif
+-04105                         doepint.d32 =
+-04106                             dwc_otg_read_dev_out_ep_intr(core_if, dwc_ep);
+-04107 
+-04108                         /* Transfer complete */
+-04109                         if (doepint.b.xfercompl) {
+-04110 
+-04111                                 if (epnum == 0) {
+-04112                                         /* Clear the bit in DOEPINTn for this interrupt */
+-04113                                         CLEAR_OUT_EP_INTR(core_if, epnum,
+-04114                                                           xfercompl);
+-04115                                         if (core_if->dma_desc_enable == 0
+-04116                                             || pcd->ep0state != EP0_IDLE)
+-04117                                                 handle_ep0(pcd);
+-04118 #ifdef DWC_EN_ISOC
+-04119                                 } else if (dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) {
+-04120                                         if (doepint.b.pktdrpsts == 0) {
+-04121                                                 /* Clear the bit in DOEPINTn for this interrupt */
+-04122                                                 CLEAR_OUT_EP_INTR(core_if,
+-04123                                                                   epnum,
+-04124                                                                   xfercompl);
+-04125                                                 complete_iso_ep(pcd, ep);
+-04126                                         } else {
+-04127 
+-04128                                                 doepint_data_t doepint = {.d32 = 0 };
+-04129                                                 doepint.b.xfercompl = 1;
+-04130                                                 doepint.b.pktdrpsts = 1;
+-04131                                                 DWC_WRITE_REG32
+-04132                                                     (&core_if->dev_if->out_ep_regs
+-04133                                                      [epnum]->doepint,
+-04134                                                      doepint.d32);
+-04135                                                 if (handle_iso_out_pkt_dropped
+-04136                                                     (core_if, dwc_ep)) {
+-04137                                                         complete_iso_ep(pcd,
+-04138                                                                         ep);
+-04139                                                 }
+-04140                                         }
+-04141 #endif /* DWC_EN_ISOC */
+-04142 #ifdef DWC_UTE_PER_IO
+-04143                                 } else if (dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) {
+-04144                                         CLEAR_OUT_EP_INTR(core_if, epnum, xfercompl);
+-04145                                         if (!ep->stopped)
+-04146                                                 complete_xiso_ep(ep);
+-04147 #endif /* DWC_UTE_PER_IO */
+-04148                                 } else {
+-04149                                         /* Clear the bit in DOEPINTn for this interrupt */
+-04150                                         CLEAR_OUT_EP_INTR(core_if, epnum,
+-04151                                                           xfercompl);
+-04152 
+-04153                                         if (core_if->core_params->dev_out_nak) {
+-04154                                                 DWC_TIMER_CANCEL(pcd->core_if->ep_xfer_timer[epnum]);
+-04155                                                 pcd->core_if->ep_xfer_info[epnum].state = 0;
+-04156 #ifdef DEBUG
+-04157                                                 print_memory_payload(pcd, dwc_ep);
+-04158 #endif
+-04159                                         }
+-04160                                         complete_ep(ep);                                                
+-04161                                 }
+-04162 
+-04163                         }
+-04164 
+-04165                         /* Endpoint disable      */
+-04166                         if (doepint.b.epdisabled) {
+-04167 
+-04168                                 /* Clear the bit in DOEPINTn for this interrupt */
+-04169                                 CLEAR_OUT_EP_INTR(core_if, epnum, epdisabled);
+-04170                                 if (core_if->core_params->dev_out_nak) {
+-04171 #ifdef DEBUG
+-04172                                         print_memory_payload(pcd, dwc_ep);
+-04173 #endif
+-04174                                         /* In case of timeout condition */
+-04175                                         if (core_if->ep_xfer_info[epnum].state == 2) {
+-04176                                                 dctl.d32 = DWC_READ_REG32(&core_if->dev_if->
+-04177                                                                                 dev_global_regs->dctl);
+-04178                                                 dctl.b.cgoutnak = 1;
+-04179                                                 DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl,
+-04180                                                                                                                                 dctl.d32);
+-04181                                                 /* Unmask goutnakeff interrupt which was masked
+-04182                                                  * during handle nak out interrupt */
+-04183                                                 gintmsk.b.goutnakeff = 1;
+-04184                                                 DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk,
+-04185                                                                                                                                 0, gintmsk.d32);
+-04186                                         
+-04187                                                 complete_ep(ep);
+-04188                                         }
+-04189                                 }
+-04190                                 if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC)
+-04191                                 {
+-04192                                         dctl_data_t dctl;
+-04193                                         gintmsk_data_t intr_mask = {.d32 = 0};
+-04194                                         dwc_otg_pcd_request_t *req = 0;
+-04195 
+-04196                                         dctl.d32 = DWC_READ_REG32(&core_if->dev_if->
+-04197                                                 dev_global_regs->dctl);
+-04198                                         dctl.b.cgoutnak = 1;
+-04199                                         DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl,
+-04200                                                 dctl.d32);
+-04201 
+-04202                                         intr_mask.d32 = 0;
+-04203                                         intr_mask.b.incomplisoout = 1;     
+-04204 
+-04205                                         /* Get any pending requests */
+-04206                                         if (!DWC_CIRCLEQ_EMPTY(&ep->queue)) {
+-04207                                                 req = DWC_CIRCLEQ_FIRST(&ep->queue);
+-04208                                                 if (!req) {
+-04209                                                         DWC_PRINTF("complete_ep 0x%p, req = NULL!\n", ep);
+-04210                                                 } else {
+-04211                                                         dwc_otg_request_done(ep, req, 0);
+-04212                                                         start_next_request(ep);
+-04213                                                 }
+-04214                                         } else {
+-04215                                                 DWC_PRINTF("complete_ep 0x%p, ep->queue empty!\n", ep);
+-04216                                         }
+-04217                                 }
+-04218                         }
+-04219                         /* AHB Error */
+-04220                         if (doepint.b.ahberr) {
+-04221                                 DWC_ERROR("EP%d OUT AHB Error\n", epnum);
+-04222                                 DWC_ERROR("EP%d DEPDMA=0x%08x \n",
+-04223                                           epnum, core_if->dev_if->out_ep_regs[epnum]->doepdma);
+-04224                                 CLEAR_OUT_EP_INTR(core_if, epnum, ahberr);
+-04225                         }
+-04226                         /* Setup Phase Done (contorl EPs) */
+-04227                         if (doepint.b.setup) {
+-04228 #ifdef DEBUG_EP0
+-04229                                 DWC_DEBUGPL(DBG_PCD, "EP%d SETUP Done\n",
+-04230                                             epnum);
+-04231 #endif
+-04232                                 CLEAR_OUT_EP_INTR(core_if, epnum, setup);
+-04233 
+-04234                                 handle_ep0(pcd);
+-04235                         }
+-04236 
+-04238                         if (doepint.b.bna) {
+-04239                                 CLEAR_OUT_EP_INTR(core_if, epnum, bna);
+-04240                                 if (core_if->dma_desc_enable) {
+-04241 #ifdef DWC_EN_ISOC
+-04242                                         if (dwc_ep->type ==
+-04243                                             DWC_OTG_EP_TYPE_ISOC) {
+-04244                                                 /*
+-04245                                                  * This checking is performed to prevent first "false" BNA
+-04246                                                  * handling occuring right after reconnect
+-04247                                                  */
+-04248                                                 if (dwc_ep->next_frame !=
+-04249                                                     0xffffffff)
+-04250                                                         dwc_otg_pcd_handle_iso_bna(ep);
+-04251                                         } else
+-04252 #endif                          /* DWC_EN_ISOC */
+-04253                                         {
+-04254                                                 dwc_otg_pcd_handle_noniso_bna(ep);
+-04255                                         }
+-04256                                 }
+-04257                         }
+-04258                         if (doepint.b.stsphsercvd) {
+-04259                                 CLEAR_OUT_EP_INTR(core_if, epnum, stsphsercvd);
+-04260                                 if (core_if->dma_desc_enable) {
+-04261                                         do_setup_in_status_phase(pcd);
+-04262                                 }
+-04263                         }
+-04264                         /* Babble Interrutp */
+-04265                         if (doepint.b.babble) {
+-04266                                 DWC_DEBUGPL(DBG_ANY, "EP%d OUT Babble\n",
+-04267                                             epnum);
+-04268                                 handle_out_ep_babble_intr(pcd, epnum);
+-04269 
+-04270                                 CLEAR_OUT_EP_INTR(core_if, epnum, babble);
+-04271                         }
+-04272                         if (doepint.b.outtknepdis)
+-04273                         {
+-04274                                 DWC_DEBUGPL(DBG_ANY, "EP%d OUT Token received when EP is \
+-04275                                         disabled\n",epnum);
+-04276                                 if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC)
+-04277                                 {
+-04278                                         doepmsk_data_t doepmsk = {.d32 = 0};
+-04279                                         ep->dwc_ep.frame_num = core_if->frame_num;
+-04280                                         if (ep->dwc_ep.bInterval > 1) 
+-04281                                         {
+-04282                                                 depctl_data_t depctl;
+-04283                                                 depctl.d32 = DWC_READ_REG32(&core_if->dev_if->
+-04284                                                                                                         out_ep_regs[epnum]->doepctl);
+-04285                                                 if (ep->dwc_ep.frame_num & 0x1) {
+-04286                                                         depctl.b.setd1pid = 1;
+-04287                                                         depctl.b.setd0pid = 0;
+-04288                                                 } else {
+-04289                                                         depctl.b.setd0pid = 1;
+-04290                                                         depctl.b.setd1pid = 0;
+-04291                                                 }
+-04292                                                 DWC_WRITE_REG32(&core_if->dev_if->
+-04293                                                                                 out_ep_regs[epnum]->doepctl, depctl.d32);
+-04294                                         }
+-04295                                         start_next_request(ep);
+-04296                                         doepmsk.b.outtknepdis = 1;
+-04297                                         DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->doepmsk, 
+-04298                                                                  doepmsk.d32, 0);
+-04299                                 }
+-04300                                 CLEAR_OUT_EP_INTR(core_if, epnum, outtknepdis);
+-04301                         }
+-04302                         
+-04303                         /* NAK Interrutp */
+-04304                         if (doepint.b.nak) {
+-04305                                 DWC_DEBUGPL(DBG_ANY, "EP%d OUT NAK\n", epnum);
+-04306                                 handle_out_ep_nak_intr(pcd, epnum);
+-04307 
+-04308                                 CLEAR_OUT_EP_INTR(core_if, epnum, nak);
+-04309                         }
+-04310                         /* NYET Interrutp */
+-04311                         if (doepint.b.nyet) {
+-04312                                 DWC_DEBUGPL(DBG_ANY, "EP%d OUT NYET\n", epnum);
+-04313                                 handle_out_ep_nyet_intr(pcd, epnum);
+-04314 
+-04315                                 CLEAR_OUT_EP_INTR(core_if, epnum, nyet);
+-04316                         }
+-04317                 }
+-04318 
+-04319                 epnum++;
+-04320                 ep_intr >>= 1;
+-04321         }
+-04322 
+-04323         return 1;
+-04324 
+-04325 #undef CLEAR_OUT_EP_INTR
+-04326 }
+-04327 static int drop_transfer(uint32_t trgt_fr, uint32_t curr_fr, uint8_t frm_overrun)
+-04328 {
+-04329         int retval = 0;
+-04330         if(!frm_overrun && curr_fr >= trgt_fr) 
+-04331                 retval = 1;
+-04332         else if (frm_overrun && (curr_fr >= trgt_fr && ((curr_fr - trgt_fr) < 0x3FFF/2)))
+-04333                 retval = 1;
+-04334         return retval;
+-04335 }
+-04348 int32_t dwc_otg_pcd_handle_incomplete_isoc_in_intr(dwc_otg_pcd_t * pcd)
+-04349 {
+-04350         gintsts_data_t gintsts;
+-04351 
+-04352 #ifdef DWC_EN_ISOC
+-04353         dwc_otg_dev_if_t *dev_if;
+-04354         deptsiz_data_t deptsiz = {.d32 = 0 };
+-04355         depctl_data_t depctl = {.d32 = 0 };
+-04356         dsts_data_t dsts = {.d32 = 0 };
+-04357         dwc_ep_t *dwc_ep;
+-04358         int i;
+-04359 
+-04360         dev_if = GET_CORE_IF(pcd)->dev_if;
+-04361 
+-04362         for (i = 1; i <= dev_if->num_in_eps; ++i) {
+-04363                 dwc_ep = &pcd->in_ep[i].dwc_ep;
+-04364                 if (dwc_ep->active && dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) {
+-04365                         deptsiz.d32 =
+-04366                             DWC_READ_REG32(&dev_if->in_ep_regs[i]->dieptsiz);
+-04367                         depctl.d32 =
+-04368                             DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl);
+-04369 
+-04370                         if (depctl.b.epdis && deptsiz.d32) {
+-04371                                 set_current_pkt_info(GET_CORE_IF(pcd), dwc_ep);
+-04372                                 if (dwc_ep->cur_pkt >= dwc_ep->pkt_cnt) {
+-04373                                         dwc_ep->cur_pkt = 0;
+-04374                                         dwc_ep->proc_buf_num =
+-04375                                             (dwc_ep->proc_buf_num ^ 1) & 0x1;
+-04376 
+-04377                                         if (dwc_ep->proc_buf_num) {
+-04378                                                 dwc_ep->cur_pkt_addr =
+-04379                                                     dwc_ep->xfer_buff1;
+-04380                                                 dwc_ep->cur_pkt_dma_addr =
+-04381                                                     dwc_ep->dma_addr1;
+-04382                                         } else {
+-04383                                                 dwc_ep->cur_pkt_addr =
+-04384                                                     dwc_ep->xfer_buff0;
+-04385                                                 dwc_ep->cur_pkt_dma_addr =
+-04386                                                     dwc_ep->dma_addr0;
+-04387                                         }
+-04388 
+-04389                                 }
+-04390 
+-04391                                 dsts.d32 =
+-04392                                     DWC_READ_REG32(&GET_CORE_IF(pcd)->dev_if->
+-04393                                                    dev_global_regs->dsts);
+-04394                                 dwc_ep->next_frame = dsts.b.soffn;
+-04395 
+-04396                                 dwc_otg_iso_ep_start_frm_transfer(GET_CORE_IF
+-04397                                                                   (pcd),
+-04398                                                                   dwc_ep);
+-04399                         }
+-04400                 }
+-04401         }
+-04402 
+-04403 #else
+-04404         depctl_data_t depctl = {.d32 = 0 };
+-04405         dwc_ep_t *dwc_ep;
+-04406         dwc_otg_dev_if_t *dev_if;
+-04407         int i;
+-04408         dev_if = GET_CORE_IF(pcd)->dev_if;
+-04409 
+-04410         DWC_DEBUGPL(DBG_PCD,"Incomplete ISO IN \n");
+-04411         
+-04412         for (i = 1; i <= dev_if->num_in_eps; ++i) {
+-04413                 dwc_ep = &pcd->in_ep[i-1].dwc_ep;
+-04414                 depctl.d32 =
+-04415                         DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl);
+-04416                 if (depctl.b.epena && dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) {
+-04417                         if (drop_transfer(dwc_ep->frame_num, GET_CORE_IF(pcd)->frame_num, 
+-04418                                                         dwc_ep->frm_overrun))
+-04419                         {
+-04420                                 depctl.d32 =
+-04421                                         DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl);
+-04422                                 depctl.b.snak = 1;
+-04423                                 depctl.b.epdis = 1;
+-04424                                 DWC_MODIFY_REG32(&dev_if->in_ep_regs[i]->diepctl, depctl.d32, depctl.d32);
+-04425                         }
+-04426                 }
+-04427         }
+-04428 
+-04429         /*intr_mask.b.incomplisoin = 1;
+-04430         DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk,
+-04431                          intr_mask.d32, 0);      */
+-04432 #endif                          //DWC_EN_ISOC
+-04433 
+-04434         /* Clear interrupt */
+-04435         gintsts.d32 = 0;
+-04436         gintsts.b.incomplisoin = 1;
+-04437         DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
+-04438                         gintsts.d32);
+-04439 
+-04440         return 1;
+-04441 }
+-04442 
+-04458 int32_t dwc_otg_pcd_handle_incomplete_isoc_out_intr(dwc_otg_pcd_t * pcd)
+-04459 {
+-04460 
+-04461         gintsts_data_t gintsts;
+-04462 
+-04463 #ifdef DWC_EN_ISOC
+-04464         dwc_otg_dev_if_t *dev_if;
+-04465         deptsiz_data_t deptsiz = {.d32 = 0 };
+-04466         depctl_data_t depctl = {.d32 = 0 };
+-04467         dsts_data_t dsts = {.d32 = 0 };
+-04468         dwc_ep_t *dwc_ep;
+-04469         int i;
+-04470 
+-04471         dev_if = GET_CORE_IF(pcd)->dev_if;
+-04472 
+-04473         for (i = 1; i <= dev_if->num_out_eps; ++i) {
+-04474                 dwc_ep = &pcd->in_ep[i].dwc_ep;
+-04475                 if (pcd->out_ep[i].dwc_ep.active &&
+-04476                     pcd->out_ep[i].dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) {
+-04477                         deptsiz.d32 =
+-04478                             DWC_READ_REG32(&dev_if->out_ep_regs[i]->doeptsiz);
+-04479                         depctl.d32 =
+-04480                             DWC_READ_REG32(&dev_if->out_ep_regs[i]->doepctl);
+-04481 
+-04482                         if (depctl.b.epdis && deptsiz.d32) {
+-04483                                 set_current_pkt_info(GET_CORE_IF(pcd),
+-04484                                                      &pcd->out_ep[i].dwc_ep);
+-04485                                 if (dwc_ep->cur_pkt >= dwc_ep->pkt_cnt) {
+-04486                                         dwc_ep->cur_pkt = 0;
+-04487                                         dwc_ep->proc_buf_num =
+-04488                                             (dwc_ep->proc_buf_num ^ 1) & 0x1;
+-04489 
+-04490                                         if (dwc_ep->proc_buf_num) {
+-04491                                                 dwc_ep->cur_pkt_addr =
+-04492                                                     dwc_ep->xfer_buff1;
+-04493                                                 dwc_ep->cur_pkt_dma_addr =
+-04494                                                     dwc_ep->dma_addr1;
+-04495                                         } else {
+-04496                                                 dwc_ep->cur_pkt_addr =
+-04497                                                     dwc_ep->xfer_buff0;
+-04498                                                 dwc_ep->cur_pkt_dma_addr =
+-04499                                                     dwc_ep->dma_addr0;
+-04500                                         }
+-04501 
+-04502                                 }
+-04503 
+-04504                                 dsts.d32 =
+-04505                                     DWC_READ_REG32(&GET_CORE_IF(pcd)->dev_if->
+-04506                                                    dev_global_regs->dsts);
+-04507                                 dwc_ep->next_frame = dsts.b.soffn;
+-04508 
+-04509                                 dwc_otg_iso_ep_start_frm_transfer(GET_CORE_IF
+-04510                                                                   (pcd),
+-04511                                                                   dwc_ep);
+-04512                         }
+-04513                 }
+-04514         }
+-04515 #else
+-04516 
+-04517         gintmsk_data_t intr_mask = {.d32 = 0 };
+-04518         dwc_otg_core_if_t *core_if;
+-04519         deptsiz_data_t deptsiz = {.d32 = 0 };
+-04520         depctl_data_t depctl = {.d32 = 0 };
+-04521         dctl_data_t dctl = {.d32 = 0 };
+-04522         dwc_ep_t *dwc_ep = NULL;
+-04523         int i;
+-04524         core_if = GET_CORE_IF(pcd);
+-04525 
+-04526         for (i = 0; i < core_if->dev_if->num_out_eps; ++i) {
+-04527                 dwc_ep = &pcd->out_ep[i].dwc_ep;
+-04528                 depctl.d32 =
+-04529                         DWC_READ_REG32(&core_if->dev_if->out_ep_regs[dwc_ep->num]->doepctl);
+-04530                 if (depctl.b.epena && depctl.b.dpid == (core_if->frame_num & 0x1)) {
+-04531                         core_if->dev_if->isoc_ep = dwc_ep;      
+-04532                         deptsiz.d32 =
+-04533                                         DWC_READ_REG32(&core_if->dev_if->out_ep_regs[dwc_ep->num]->doeptsiz);
+-04534                                 break;
+-04535                 }
+-04536         }
+-04537         dctl.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dctl);
+-04538         gintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts);
+-04539         intr_mask.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintmsk);
+-04540 
+-04541         if (!intr_mask.b.goutnakeff) {
+-04542                 /* Unmask it */
+-04543                 intr_mask.b.goutnakeff = 1;
+-04544                 DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, intr_mask.d32);
+-04545         }
+-04546         if (!gintsts.b.goutnakeff) {
+-04547                 dctl.b.sgoutnak = 1;
+-04548         }
+-04549         DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32);
+-04550 
+-04551         depctl.d32 = DWC_READ_REG32(&core_if->dev_if->out_ep_regs[dwc_ep->num]->doepctl);
+-04552         if (depctl.b.epena) {
+-04553                 depctl.b.epdis = 1;
+-04554                 depctl.b.snak = 1;
+-04555         }
+-04556         DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[dwc_ep->num]->doepctl, depctl.d32);
+-04557 
+-04558         intr_mask.d32 = 0;
+-04559         intr_mask.b.incomplisoout = 1;
+-04560                 
+-04561 #endif /* DWC_EN_ISOC */
+-04562 
+-04563         /* Clear interrupt */
+-04564         gintsts.d32 = 0;
+-04565         gintsts.b.incomplisoout = 1;
+-04566         DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
+-04567                         gintsts.d32);
+-04568 
+-04569         return 1;
+-04570 }
+-04571 
+-04576 int32_t dwc_otg_pcd_handle_in_nak_effective(dwc_otg_pcd_t * pcd)
+-04577 {
+-04578         dwc_otg_dev_if_t *dev_if = GET_CORE_IF(pcd)->dev_if;
+-04579         depctl_data_t diepctl = {.d32 = 0 };
+-04580         gintmsk_data_t intr_mask = {.d32 = 0 };
+-04581         gintsts_data_t gintsts;
+-04582         dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
+-04583         int i;
+-04584 
+-04585         DWC_DEBUGPL(DBG_PCD, "Global IN NAK Effective\n");
+-04586 
+-04587         /* Disable all active IN EPs */
+-04588         for (i = 0; i <= dev_if->num_in_eps; i++) {
+-04589                 diepctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl);
+-04590                 if (!(diepctl.b.eptype & 1) && diepctl.b.epena) {
+-04591                         if (core_if->start_predict > 0)
+-04592                                 core_if->start_predict++;
+-04593                         diepctl.b.epdis = 1;
+-04594                         diepctl.b.snak = 1;
+-04595                         DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->diepctl, diepctl.d32);
+-04596                 }                                               
+-04597         }
+-04598         
+-04599 
+-04600         /* Disable the Global IN NAK Effective Interrupt */
+-04601         intr_mask.b.ginnakeff = 1;
+-04602         DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk,
+-04603                          intr_mask.d32, 0);
+-04604 
+-04605         /* Clear interrupt */
+-04606         gintsts.d32 = 0;
+-04607         gintsts.b.ginnakeff = 1;
+-04608         DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
+-04609                         gintsts.d32);
+-04610 
+-04611         return 1;
+-04612 }
+-04613 
+-04618 int32_t dwc_otg_pcd_handle_out_nak_effective(dwc_otg_pcd_t * pcd)
+-04619 {
+-04620         dwc_otg_dev_if_t *dev_if = GET_CORE_IF(pcd)->dev_if;
+-04621         gintmsk_data_t intr_mask = {.d32 = 0 };
+-04622         gintsts_data_t gintsts;
+-04623         depctl_data_t doepctl;
+-04624         int i;
+-04625 
+-04626         /* Disable the Global OUT NAK Effective Interrupt */
+-04627         intr_mask.b.goutnakeff = 1;
+-04628         DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintmsk,
+-04629                 intr_mask.d32, 0);
+-04630         
+-04631         /* If DEV OUT NAK enabled*/
+-04632         if (pcd->core_if->core_params->dev_out_nak) {
+-04633                 /* Run over all out endpoints to determine the ep number on
+-04634                  * which the timeout has happened 
+-04635                  */
+-04636                 for (i = 0; i <= dev_if->num_out_eps; i++) {
+-04637                         if ( pcd->core_if->ep_xfer_info[i].state == 2 )
+-04638                                 break;
+-04639                 }
+-04640                 if (i > dev_if->num_out_eps) {
+-04641                         dctl_data_t dctl;
+-04642                         dctl.d32 = DWC_READ_REG32(&dev_if->
+-04643                                 dev_global_regs->dctl);
+-04644                         dctl.b.cgoutnak = 1;
+-04645                         DWC_WRITE_REG32(&dev_if->dev_global_regs->dctl,
+-04646                                 dctl.d32);
+-04647                         goto out;
+-04648                 }
+-04649 
+-04650                 /* Disable the endpoint */
+-04651                 doepctl.d32 = DWC_READ_REG32(&dev_if->
+-04652                                                                                 out_ep_regs[i]->doepctl);
+-04653                 if (doepctl.b.epena) {
+-04654                         doepctl.b.epdis = 1;
+-04655                         doepctl.b.snak = 1;
+-04656                 }
+-04657                 DWC_WRITE_REG32(&dev_if->out_ep_regs[i]->doepctl, doepctl.d32);
+-04658                 return 1;
+-04659         }
+-04660         /* We come here from Incomplete ISO OUT handler */
+-04661         if(dev_if->isoc_ep)
+-04662         {
+-04663                 dwc_ep_t *dwc_ep = (dwc_ep_t *)dev_if->isoc_ep;
+-04664                 uint32_t epnum = dwc_ep->num;
+-04665                 doepint_data_t doepint;
+-04666                 doepint.d32 = DWC_READ_REG32(&dev_if->out_ep_regs[dwc_ep->num]->doepint);
+-04667                 dev_if->isoc_ep = NULL;
+-04668                 doepctl.d32 = DWC_READ_REG32(&dev_if->out_ep_regs[epnum]->doepctl);
+-04669                 DWC_PRINTF("Before disable DOEPCTL = %08x\n", doepctl.d32);
+-04670                 if (doepctl.b.epena) {
+-04671                         doepctl.b.epdis = 1;
+-04672                         doepctl.b.snak = 1;
+-04673                 }
+-04674                 DWC_WRITE_REG32(&dev_if->out_ep_regs[epnum]->doepctl, doepctl.d32);
+-04675                 return 1;
+-04676         } else
+-04677                 DWC_PRINTF("INTERRUPT Handler not implemented for %s\n",
+-04678                            "Global OUT NAK Effective\n");
+-04679         
+-04680 out:
+-04681         /* Clear interrupt */
+-04682         gintsts.d32 = 0;
+-04683         gintsts.b.goutnakeff = 1;
+-04684         DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gintsts,
+-04685                         gintsts.d32);
+-04686 
+-04687         return 1;
+-04688 }
+-04689 
+-04702 int32_t dwc_otg_pcd_handle_intr(dwc_otg_pcd_t * pcd)
+-04703 {
+-04704         dwc_otg_core_if_t *core_if = GET_CORE_IF(pcd);
+-04705 #ifdef VERBOSE
+-04706         dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
+-04707 #endif
+-04708         gintsts_data_t gintr_status;
+-04709         int32_t retval = 0;
+-04710 
+-04711         /* Exit from ISR if core is hibernated */
+-04712         if (core_if->hibernation_suspend == 1) {
+-04713                 return retval;
+-04714         }
+-04715 #ifdef VERBOSE
+-04716         DWC_DEBUGPL(DBG_ANY, "%s() gintsts=%08x  gintmsk=%08x\n",
+-04717                     __func__,
+-04718                     DWC_READ_REG32(&global_regs->gintsts),
+-04719                     DWC_READ_REG32(&global_regs->gintmsk));
+-04720 #endif
+-04721 
+-04722         if (dwc_otg_is_device_mode(core_if)) {
+-04723                 DWC_SPINLOCK(pcd->lock);
+-04724 #ifdef VERBOSE
+-04725                 DWC_DEBUGPL(DBG_PCDV, "%s() gintsts=%08x  gintmsk=%08x\n",
+-04726                             __func__,
+-04727                             DWC_READ_REG32(&global_regs->gintsts),
+-04728                             DWC_READ_REG32(&global_regs->gintmsk));
+-04729 #endif
+-04730 
+-04731                 gintr_status.d32 = dwc_otg_read_core_intr(core_if);
+-04732 
+-04733                 DWC_DEBUGPL(DBG_PCDV, "%s: gintsts&gintmsk=%08x\n",
+-04734                             __func__, gintr_status.d32);
+-04735 
+-04736                 if (gintr_status.b.sofintr) {
+-04737                         retval |= dwc_otg_pcd_handle_sof_intr(pcd);
+-04738                 }
+-04739                 if (gintr_status.b.rxstsqlvl) {
+-04740                         retval |=
+-04741                             dwc_otg_pcd_handle_rx_status_q_level_intr(pcd);
+-04742                 }
+-04743                 if (gintr_status.b.nptxfempty) {
+-04744                         retval |= dwc_otg_pcd_handle_np_tx_fifo_empty_intr(pcd);
+-04745                 }
+-04746                 if (gintr_status.b.goutnakeff) {
+-04747                         retval |= dwc_otg_pcd_handle_out_nak_effective(pcd);
+-04748                 }
+-04749                 if (gintr_status.b.i2cintr) {
+-04750                         retval |= dwc_otg_pcd_handle_i2c_intr(pcd);
+-04751                 }
+-04752                 if (gintr_status.b.erlysuspend) {
+-04753                         retval |= dwc_otg_pcd_handle_early_suspend_intr(pcd);
+-04754                 }
+-04755                 if (gintr_status.b.usbreset) {
+-04756                         retval |= dwc_otg_pcd_handle_usb_reset_intr(pcd);
+-04757                 }
+-04758                 if (gintr_status.b.enumdone) {
+-04759                         retval |= dwc_otg_pcd_handle_enum_done_intr(pcd);
+-04760                 }
+-04761                 if (gintr_status.b.isooutdrop) {
+-04762                         retval |=
+-04763                             dwc_otg_pcd_handle_isoc_out_packet_dropped_intr
+-04764                             (pcd);
+-04765                 }
+-04766                 if (gintr_status.b.eopframe) {
+-04767                         retval |=
+-04768                             dwc_otg_pcd_handle_end_periodic_frame_intr(pcd);
+-04769                 }
+-04770                 if (gintr_status.b.inepint) {
+-04771                         if (!core_if->multiproc_int_enable) {
+-04772                                 retval |= dwc_otg_pcd_handle_in_ep_intr(pcd);
+-04773                         }
+-04774                 }
+-04775                 if (gintr_status.b.outepintr) {
+-04776                         if (!core_if->multiproc_int_enable) {
+-04777                                 retval |= dwc_otg_pcd_handle_out_ep_intr(pcd);
+-04778                         }
+-04779                 }
+-04780                 if (gintr_status.b.epmismatch) {
+-04781                         retval |= dwc_otg_pcd_handle_ep_mismatch_intr(pcd);
+-04782                 }
+-04783                 if (gintr_status.b.fetsusp) {
+-04784                         retval |= dwc_otg_pcd_handle_ep_fetsusp_intr(pcd);
+-04785                 }
+-04786                 if (gintr_status.b.ginnakeff) {
+-04787                         retval |= dwc_otg_pcd_handle_in_nak_effective(pcd);
+-04788                 }
+-04789                 if (gintr_status.b.incomplisoin) {
+-04790                         retval |=
+-04791                             dwc_otg_pcd_handle_incomplete_isoc_in_intr(pcd);
+-04792                 }
+-04793                 if (gintr_status.b.incomplisoout) {
+-04794                         retval |=
+-04795                             dwc_otg_pcd_handle_incomplete_isoc_out_intr(pcd);
+-04796                 }
+-04797 
+-04798                 /* In MPI mode Device Endpoints interrupts are asserted
+-04799                  * without setting outepintr and inepint bits set, so these
+-04800                  * Interrupt handlers are called without checking these bit-fields
+-04801                  */
+-04802                 if (core_if->multiproc_int_enable) {
+-04803                         retval |= dwc_otg_pcd_handle_in_ep_intr(pcd);
+-04804                         retval |= dwc_otg_pcd_handle_out_ep_intr(pcd);
+-04805                 }
+-04806 #ifdef VERBOSE
+-04807                 DWC_DEBUGPL(DBG_PCDV, "%s() gintsts=%0x\n", __func__,
+-04808                             DWC_READ_REG32(&global_regs->gintsts));
+-04809 #endif
+-04810                 DWC_SPINUNLOCK(pcd->lock);
+-04811         }
+-04812         return retval;
+-04813 }
+-04814 
+-04815 #endif /* DWC_HOST_ONLY */
+-
                                                                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__pcd__intr_8c.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/dwc__otg__pcd__intr_8c.html 2013-07-26 19:34:42.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,1883 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_pcd_intr.c File Reference +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                dwc_otg_pcd_intr.c File Reference

                                                                                This file contains the implementation of the PCD Interrupt handlers. More... +-

                                                                                +-#include "dwc_otg_pcd.h"
                                                                                +- +-

                                                                                +-Go to the source code of this file. +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-

                                                                                Defines

                                                                                +-#define DEBUG_EP0
                                                                                #define CLEAR_IN_EP_INTR(__core_if, __epnum, __intr)
                                                                                #define CLEAR_OUT_EP_INTR(__core_if, __epnum, __intr)

                                                                                Functions

                                                                                +-void dwc_otg_pcd_update_otg (dwc_otg_pcd_t *pcd, const unsigned reset)
                                                                                 This function updates OTG.
                                                                                +-void print_ep0_state (dwc_otg_pcd_t *pcd)
                                                                                 This function prints the ep0 state for debug purposes.
                                                                                +-void print_memory_payload (dwc_otg_pcd_t *pcd, dwc_ep_t *ep)
                                                                                 This function calculate the size of the payload in the memory for out endpoints and prints size for debug purposes(used in 2.93a DevOutNak feature).
                                                                                +-dwc_otg_pcd_ep_t * get_in_ep (dwc_otg_pcd_t *pcd, uint32_t ep_num)
                                                                                 This function returns pointer to in ep struct with number ep_num.
                                                                                +-dwc_otg_pcd_ep_t * get_out_ep (dwc_otg_pcd_t *pcd, uint32_t ep_num)
                                                                                 This function returns pointer to out ep struct with number ep_num.
                                                                                +-dwc_otg_pcd_ep_t * get_ep_by_addr (dwc_otg_pcd_t *pcd, u16 wIndex)
                                                                                 This functions gets a pointer to an EP from the wIndex address value of the control request.
                                                                                +-void start_next_request (dwc_otg_pcd_ep_t *ep)
                                                                                 Tasklet.
                                                                                int32_t dwc_otg_pcd_handle_sof_intr (dwc_otg_pcd_t *pcd)
                                                                                 This function handles the SOF Interrupts.
                                                                                int32_t dwc_otg_pcd_handle_rx_status_q_level_intr (dwc_otg_pcd_t *pcd)
                                                                                 This function handles the Rx Status Queue Level Interrupt, which indicates that there is a least one packet in the Rx FIFO.
                                                                                int get_ep_of_last_in_token (dwc_otg_core_if_t *core_if)
                                                                                 This function examines the Device IN Token Learning Queue to determine the EP number of the last IN token received.
                                                                                int32_t dwc_otg_pcd_handle_np_tx_fifo_empty_intr (dwc_otg_pcd_t *pcd)
                                                                                 This interrupt occurs when the non-periodic Tx FIFO is half-empty.
                                                                                int32_t write_empty_tx_fifo (dwc_otg_pcd_t *pcd, uint32_t epnum)
                                                                                 This function is called when dedicated Tx FIFO Empty interrupt occurs.
                                                                                void dwc_otg_pcd_stop (dwc_otg_pcd_t *pcd)
                                                                                 This function is called when the Device is disconnected.
                                                                                +-int32_t dwc_otg_pcd_handle_i2c_intr (dwc_otg_pcd_t *pcd)
                                                                                 This interrupt indicates that ...
                                                                                +-int32_t dwc_otg_pcd_handle_early_suspend_intr (dwc_otg_pcd_t *pcd)
                                                                                 This interrupt indicates that ...
                                                                                void ep0_out_start (dwc_otg_core_if_t *core_if, dwc_otg_pcd_t *pcd)
                                                                                 This function configures EPO to receive SETUP packets.
                                                                                int32_t dwc_otg_pcd_handle_usb_reset_intr (dwc_otg_pcd_t *pcd)
                                                                                 This interrupt occurs when a USB Reset is detected.
                                                                                int get_device_speed (dwc_otg_core_if_t *core_if)
                                                                                 Get the device speed from the device status register and convert it to USB speed constant.
                                                                                int32_t dwc_otg_pcd_handle_enum_done_intr (dwc_otg_pcd_t *pcd)
                                                                                 Read the device status register and set the device speed in the data structure.
                                                                                int32_t dwc_otg_pcd_handle_isoc_out_packet_dropped_intr (dwc_otg_pcd_t *pcd)
                                                                                 This interrupt indicates that the ISO OUT Packet was dropped due to Rx FIFO full or Rx Status Queue Full.
                                                                                int32_t dwc_otg_pcd_handle_end_periodic_frame_intr (dwc_otg_pcd_t *pcd)
                                                                                 This interrupt indicates the end of the portion of the micro-frame for periodic transactions.
                                                                                int32_t dwc_otg_pcd_handle_ep_mismatch_intr (dwc_otg_pcd_t *pcd)
                                                                                 This interrupt indicates that EP of the packet on the top of the non-periodic Tx FIFO does not match EP of the IN Token received.
                                                                                int32_t dwc_otg_pcd_handle_ep_fetsusp_intr (dwc_otg_pcd_t *pcd)
                                                                                 This interrupt is valid only in DMA mode.
                                                                                +-void ep0_do_stall (dwc_otg_pcd_t *pcd, const int err_val)
                                                                                 This funcion stalls EP0.
                                                                                void do_gadget_setup (dwc_otg_pcd_t *pcd, usb_device_request_t *ctrl)
                                                                                 This functions delegates the setup command to the gadget driver.
                                                                                +-void do_setup_in_status_phase (dwc_otg_pcd_t *pcd)
                                                                                 This function starts the Zero-Length Packet for the IN status phase of a 2 stage control transfer.
                                                                                +-void do_setup_out_status_phase (dwc_otg_pcd_t *pcd)
                                                                                 This function starts the Zero-Length Packet for the OUT status phase of a 2 stage control transfer.
                                                                                void pcd_clear_halt (dwc_otg_pcd_t *pcd, dwc_otg_pcd_ep_t *ep)
                                                                                 Clear the EP halt (STALL) and if pending requests start the transfer.
                                                                                void do_test_mode (void *data)
                                                                                 This function is called when the SET_FEATURE TEST_MODE Setup packet is sent from the host.
                                                                                void do_get_status (dwc_otg_pcd_t *pcd)
                                                                                 This function process the GET_STATUS Setup Commands.
                                                                                void do_set_feature (dwc_otg_pcd_t *pcd)
                                                                                 This function process the SET_FEATURE Setup Commands.
                                                                                void do_clear_feature (dwc_otg_pcd_t *pcd)
                                                                                 This function process the CLEAR_FEATURE Setup Commands.
                                                                                +-void do_set_address (dwc_otg_pcd_t *pcd)
                                                                                 This function process the SET_ADDRESS Setup Commands.
                                                                                void pcd_setup (dwc_otg_pcd_t *pcd)
                                                                                 This function processes SETUP commands.
                                                                                +-int32_t ep0_complete_request (dwc_otg_pcd_ep_t *ep)
                                                                                 This function completes the ep0 control transfer.
                                                                                void complete_ep (dwc_otg_pcd_ep_t *ep)
                                                                                 This function completes the request for the EP.
                                                                                +-void dwc_otg_pcd_handle_iso_bna (dwc_otg_pcd_ep_t *ep)
                                                                                 This function BNA interrupt for Isochronous EPs.
                                                                                void set_current_pkt_info (dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
                                                                                 This function sets latest iso packet information(non-PTI mode).
                                                                                void set_ddma_iso_pkts_info (dwc_otg_core_if_t *core_if, dwc_ep_t *dwc_ep)
                                                                                 This function sets latest iso packet information(DDMA mode).
                                                                                void reinit_ddma_iso_xfer (dwc_otg_core_if_t *core_if, dwc_ep_t *dwc_ep)
                                                                                 This function reinitialize DMA Descriptors for Isochronous transfer.
                                                                                uint32_t handle_iso_out_pkt_dropped (dwc_otg_core_if_t *core_if, dwc_ep_t *dwc_ep)
                                                                                 This function is to handle Iso EP transfer complete interrupt in case Iso out packet was dropped.
                                                                                uint32_t set_iso_pkts_info (dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
                                                                                 This function sets iso packets information(PTI mode).
                                                                                void complete_iso_ep (dwc_otg_pcd_t *pcd, dwc_otg_pcd_ep_t *ep)
                                                                                 This function is to handle Iso EP transfer complete interrupt.
                                                                                +-void dwc_otg_pcd_handle_noniso_bna (dwc_otg_pcd_ep_t *ep)
                                                                                 This function handle BNA interrupt for Non Isochronous EPs.
                                                                                void handle_ep0 (dwc_otg_pcd_t *pcd)
                                                                                 This function handles EP0 Control transfers.
                                                                                +-void restart_transfer (dwc_otg_pcd_t *pcd, const uint32_t epnum)
                                                                                 Restart transfer.
                                                                                +-void predict_nextep_seq (dwc_otg_core_if_t *core_if)
                                                                                +-void handle_in_ep_disable_intr (dwc_otg_pcd_t *pcd, const uint32_t epnum)
                                                                                 handle the IN EP disable interrupt.
                                                                                void handle_in_ep_timeout_intr (dwc_otg_pcd_t *pcd, const uint32_t epnum)
                                                                                 Handler for the IN EP timeout handshake interrupt.
                                                                                int32_t handle_in_ep_nak_intr (dwc_otg_pcd_t *pcd, const uint32_t epnum)
                                                                                 Handler for the IN EP NAK interrupt.
                                                                                int32_t handle_out_ep_babble_intr (dwc_otg_pcd_t *pcd, const uint32_t epnum)
                                                                                 Handler for the OUT EP Babble interrupt.
                                                                                int32_t handle_out_ep_nak_intr (dwc_otg_pcd_t *pcd, const uint32_t epnum)
                                                                                 Handler for the OUT EP NAK interrupt.
                                                                                int32_t handle_out_ep_nyet_intr (dwc_otg_pcd_t *pcd, const uint32_t epnum)
                                                                                 Handler for the OUT EP NYET interrupt.
                                                                                int32_t dwc_otg_pcd_handle_in_ep_intr (dwc_otg_pcd_t *pcd)
                                                                                 This interrupt indicates that an IN EP has a pending Interrupt.
                                                                                int32_t dwc_otg_pcd_handle_out_ep_intr (dwc_otg_pcd_t *pcd)
                                                                                 This interrupt indicates that an OUT EP has a pending Interrupt.
                                                                                +-int drop_transfer (uint32_t trgt_fr, uint32_t curr_fr, uint8_t frm_overrun)
                                                                                int32_t dwc_otg_pcd_handle_incomplete_isoc_in_intr (dwc_otg_pcd_t *pcd)
                                                                                 Incomplete ISO IN Transfer Interrupt.
                                                                                int32_t dwc_otg_pcd_handle_incomplete_isoc_out_intr (dwc_otg_pcd_t *pcd)
                                                                                 Incomplete ISO OUT Transfer Interrupt.
                                                                                +-int32_t dwc_otg_pcd_handle_in_nak_effective (dwc_otg_pcd_t *pcd)
                                                                                 This function handles the Global IN NAK Effective interrupt.
                                                                                +-int32_t dwc_otg_pcd_handle_out_nak_effective (dwc_otg_pcd_t *pcd)
                                                                                 OUT NAK Effective.
                                                                                int32_t dwc_otg_pcd_handle_intr (dwc_otg_pcd_t *pcd)
                                                                                 This function should be called on every hardware interrupt.
                                                                                +-

                                                                                Detailed Description

                                                                                +-This file contains the implementation of the PCD Interrupt handlers. +-

                                                                                +-The PCD handles the device interrupts. Many conditions can cause a device interrupt. When an interrupt occurs, the device interrupt service routine determines the cause of the interrupt and dispatches handling to the appropriate function. These interrupt handling functions are described below. All interrupt registers are processed from LSB to MSB. +-

                                                                                +-Definition in file dwc_otg_pcd_intr.c.

                                                                                Define Documentation

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                #define CLEAR_IN_EP_INTR ( __core_if,
                                                                                __epnum,
                                                                                __intr   ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Value:

                                                                                do { \
+-                diepint_data_t diepint = {.d32=0}; \
+-                diepint.b.__intr = 1; \
+-                DWC_WRITE_REG32(&__core_if->dev_if->in_ep_regs[__epnum]->diepint, \
+-                diepint.d32); \
+-} while (0)
+-
                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                #define CLEAR_OUT_EP_INTR ( __core_if,
                                                                                __epnum,
                                                                                __intr   ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Value:

                                                                                do { \
+-                doepint_data_t doepint = {.d32=0}; \
+-                doepint.b.__intr = 1; \
+-                DWC_WRITE_REG32(&__core_if->dev_if->out_ep_regs[__epnum]->doepint, \
+-                doepint.d32); \
+-} while (0)
+-
                                                                                +-

                                                                                Function Documentation

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                int32_t dwc_otg_pcd_handle_sof_intr ( dwc_otg_pcd_t *  pcd  ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This function handles the SOF Interrupts. +-

                                                                                +-At this time the SOF Interrupt is disabled. +-

                                                                                +-Definition at line 298 of file dwc_otg_pcd_intr.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                int32_t dwc_otg_pcd_handle_rx_status_q_level_intr ( dwc_otg_pcd_t *  pcd  ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This function handles the Rx Status Queue Level Interrupt, which indicates that there is a least one packet in the Rx FIFO. +-

                                                                                +-The packets are moved from the FIFO to memory, where they will be processed when the Endpoint Interrupt Register indicates Transfer Complete or SETUP Phase Done.

                                                                                +-Repeat the following until the Rx Status Queue is empty:

                                                                                  +-
                                                                                1. Read the Receive Status Pop Register (GRXSTSP) to get Packet info
                                                                                2. If Receive FIFO is empty then skip to step Clear the interrupt and exit
                                                                                3. If SETUP Packet call dwc_otg_read_setup_packet to copy the SETUP data to the buffer
                                                                                4. If OUT Data Packet call dwc_otg_read_packet to copy the data to the destination buffer
                                                                                +-

                                                                                +-

                                                                                Todo:
                                                                                NGS Check for buffer overflow?
                                                                                +- +-

                                                                                +-Definition at line 331 of file dwc_otg_pcd_intr.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                int get_ep_of_last_in_token ( dwc_otg_core_if_t *  core_if  )  [inline, static]
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This function examines the Device IN Token Learning Queue to determine the EP number of the last IN token received. +-

                                                                                +-This implementation is for the Mass Storage device where there are only 2 IN EPs (Control-IN and BULK-IN).

                                                                                +-The EP numbers for the first six IN Tokens are in DTKNQR1 and there are 8 EP Numbers in each of the other possible DTKNQ Registers.

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +-
                                                                                core_if Programming view of DWC_otg controller.
                                                                                +-
                                                                                +-

                                                                                +-

                                                                                Todo:
                                                                                Find a simpler way to calculate the max queue position.
                                                                                +- +-

                                                                                +-Definition at line 424 of file dwc_otg_pcd_intr.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                int32_t dwc_otg_pcd_handle_np_tx_fifo_empty_intr ( dwc_otg_pcd_t *  pcd  ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This interrupt occurs when the non-periodic Tx FIFO is half-empty. +-

                                                                                +-The active request is checked for the next packet to be loaded into the non-periodic Tx FIFO. +-

                                                                                +-Definition at line 497 of file dwc_otg_pcd_intr.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                int32_t write_empty_tx_fifo ( dwc_otg_pcd_t *  pcd,
                                                                                uint32_t  epnum
                                                                                )  [static]
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This function is called when dedicated Tx FIFO Empty interrupt occurs. +-

                                                                                +-The active request is checked for the next packet to be loaded into apropriate Tx FIFO. +-

                                                                                +-Definition at line 561 of file dwc_otg_pcd_intr.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                void dwc_otg_pcd_stop ( dwc_otg_pcd_t *  pcd  ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This function is called when the Device is disconnected. +-

                                                                                +-It stops any active requests and informs the Gadget driver of the disconnect.

                                                                                +-

                                                                                Todo:
                                                                                NGS Flush Periodic FIFOs
                                                                                +- +-

                                                                                +-Definition at line 619 of file dwc_otg_pcd_intr.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                void ep0_out_start ( dwc_otg_core_if_t *  core_if,
                                                                                dwc_otg_pcd_t *  pcd
                                                                                )  [inline, static]
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This function configures EPO to receive SETUP packets. +-

                                                                                +-

                                                                                Todo:
                                                                                NGS: Update the comments from the HW FS.
                                                                                +-
                                                                                  +-
                                                                                1. Program the following fields in the endpoint specific registers for Control OUT EP 0, in order to receive a setup packet
                                                                                +-
                                                                                  +-
                                                                                • DOEPTSIZ0.Packet Count = 3 (To receive up to 3 back to back setup packets)
                                                                                • DOEPTSIZE0.Transfer Size = 24 Bytes (To receive up to 3 back to back setup packets)
                                                                                    +-
                                                                                  • In DMA mode, DOEPDMA0 Register with a memory address to store any setup packets received
                                                                                  +-
                                                                                +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +-
                                                                                core_if Programming view of DWC_otg controller.
                                                                                pcd Programming view of the PCD.
                                                                                +-
                                                                                +-

                                                                                +-put here as for Hermes mode deptisz register should not be written

                                                                                +-

                                                                                Todo:
                                                                                dma needs to handle multiple setup packets (up to 3)
                                                                                +-

                                                                                +-DMA Descriptor Setup

                                                                                +-DOEPDMA0 Register write

                                                                                +-put here as for Hermes mode deptisz register should not be written

                                                                                +-DOEPCTL0 Register write +-

                                                                                +-Definition at line 732 of file dwc_otg_pcd_intr.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                int32_t dwc_otg_pcd_handle_usb_reset_intr ( dwc_otg_pcd_t *  pcd  ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This interrupt occurs when a USB Reset is detected. +-

                                                                                +-When the USB Reset Interrupt occurs the device state is set to DEFAULT and the EP0 state is set to IDLE.

                                                                                  +-
                                                                                1. Set the NAK bit for all OUT endpoints (DOEPCTLn.SNAK = 1)
                                                                                2. Unmask the following interrupt bits
                                                                                    +-
                                                                                  • DAINTMSK.INEP0 = 1 (Control 0 IN endpoint)
                                                                                  +-
                                                                                +-
                                                                                  +-
                                                                                • DAINTMSK.OUTEP0 = 1 (Control 0 OUT endpoint)
                                                                                • DOEPMSK.SETUP = 1
                                                                                • DOEPMSK.XferCompl = 1
                                                                                • DIEPMSK.XferCompl = 1
                                                                                • DIEPMSK.TimeOut = 1
                                                                                +-
                                                                                  +-
                                                                                1. Program the following fields in the endpoint specific registers for Control OUT EP 0, in order to receive a setup packet
                                                                                +-
                                                                                  +-
                                                                                • DOEPTSIZ0.Packet Count = 3 (To receive up to 3 back to back setup packets)
                                                                                • DOEPTSIZE0.Transfer Size = 24 Bytes (To receive up to 3 back to back setup packets)
                                                                                    +-
                                                                                  • In DMA mode, DOEPDMA0 Register with a memory address to store any setup packets received At this point, all the required initialization, except for enabling the control 0 OUT endpoint is done, for receiving SETUP packets.
                                                                                  +-
                                                                                +- +-

                                                                                +-Definition at line 822 of file dwc_otg_pcd_intr.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                int get_device_speed ( dwc_otg_core_if_t *  core_if  )  [static]
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Get the device speed from the device status register and convert it to USB speed constant. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +-
                                                                                core_if Programming view of DWC_otg controller.
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 1007 of file dwc_otg_pcd_intr.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                int32_t dwc_otg_pcd_handle_enum_done_intr ( dwc_otg_pcd_t *  pcd  ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Read the device status register and set the device speed in the data structure. +-

                                                                                +-Set up EP0 to receive SETUP packets by calling dwc_ep0_activate. +-

                                                                                +-Definition at line 1035 of file dwc_otg_pcd_intr.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                int32_t dwc_otg_pcd_handle_isoc_out_packet_dropped_intr ( dwc_otg_pcd_t *  pcd  ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This interrupt indicates that the ISO OUT Packet was dropped due to Rx FIFO full or Rx Status Queue Full. +-

                                                                                +-If this interrupt occurs read all the data from the Rx FIFO. +-

                                                                                +-Definition at line 1130 of file dwc_otg_pcd_intr.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                int32_t dwc_otg_pcd_handle_end_periodic_frame_intr ( dwc_otg_pcd_t *  pcd  ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This interrupt indicates the end of the portion of the micro-frame for periodic transactions. +-

                                                                                +-If there is a periodic transaction for the next frame, load the packets into the EP periodic Tx FIFO. +-

                                                                                +-Definition at line 1156 of file dwc_otg_pcd_intr.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                int32_t dwc_otg_pcd_handle_ep_mismatch_intr ( dwc_otg_pcd_t *  pcd  ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This interrupt indicates that EP of the packet on the top of the non-periodic Tx FIFO does not match EP of the IN Token received. +-

                                                                                +-The "Device IN Token Queue" Registers are read to determine the order the IN Tokens have been received. The non-periodic Tx FIFO is flushed, so it can be reloaded in the order seen in the IN Token Queue. +-

                                                                                +-Definition at line 1184 of file dwc_otg_pcd_intr.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                int32_t dwc_otg_pcd_handle_ep_fetsusp_intr ( dwc_otg_pcd_t *  pcd  ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This interrupt is valid only in DMA mode. +-

                                                                                +-This interrupt indicates that the core has stopped fetching data for IN endpoints due to the unavailability of TxFIFO space or Request Queue space. This interrupt is used by the application for an endpoint mismatch algorithm.

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +-
                                                                                pcd The PCD
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 1232 of file dwc_otg_pcd_intr.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                void do_gadget_setup ( dwc_otg_pcd_t *  pcd,
                                                                                usb_device_request_t *  ctrl
                                                                                )  [inline, static]
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This functions delegates the setup command to the gadget driver. +-

                                                                                +-

                                                                                Todo:
                                                                                This is a g_file_storage gadget driver specific workaround: a DELAYED_STATUS result from the fsg_setup routine will result in the gadget queueing a EP0 IN status phase for a two-stage control transfer. Exactly the same as a SET_CONFIGURATION/SET_INTERFACE except that this is a class specific request. Need a generic way to know when the gadget driver will queue the status phase. Can we assume when we call the gadget driver setup() function that it will always queue and require the following flag? Need to look into this.
                                                                                +- +-

                                                                                +-Definition at line 1277 of file dwc_otg_pcd_intr.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                void pcd_clear_halt ( dwc_otg_pcd_t *  pcd,
                                                                                dwc_otg_pcd_ep_t *  ep
                                                                                )  [inline, static]
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Clear the EP halt (STALL) and if pending requests start the transfer. +-

                                                                                +-

                                                                                Todo:
                                                                                FIXME: this causes an EP mismatch in DMA mode. epmismatch not yet implemented.
                                                                                +- +-

                                                                                +-Definition at line 1384 of file dwc_otg_pcd_intr.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                void do_test_mode ( void *  data  ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This function is called when the SET_FEATURE TEST_MODE Setup packet is sent from the host. +-

                                                                                +-The Device Control register is written with the Test Mode bits set to the specified Test Mode. This is done as a tasklet so that the "Status" phase of the control transfer completes before transmitting the TEST packets.

                                                                                +-

                                                                                Todo:
                                                                                This has not been tested since the tasklet struct was put into the PCD struct!
                                                                                +- +-

                                                                                +-Definition at line 1423 of file dwc_otg_pcd_intr.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                void do_get_status ( dwc_otg_pcd_t *  pcd  )  [inline, static]
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This function process the GET_STATUS Setup Commands. +-

                                                                                +-

                                                                                Todo:
                                                                                check for EP stall
                                                                                +- +-

                                                                                +-Definition at line 1460 of file dwc_otg_pcd_intr.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                void do_set_feature ( dwc_otg_pcd_t *  pcd  )  [inline, static]
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This function process the SET_FEATURE Setup Commands. +-

                                                                                +-

                                                                                Todo:
                                                                                This has not been tested since the tasklet struct was put into the PCD struct!

                                                                                +-Is the gotgctl.devhnpen cleared by a USB Reset?

                                                                                +- +-

                                                                                +-Definition at line 1533 of file dwc_otg_pcd_intr.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                void do_clear_feature ( dwc_otg_pcd_t *  pcd  )  [inline, static]
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This function process the CLEAR_FEATURE Setup Commands. +-

                                                                                +-

                                                                                Todo:
                                                                                Add CLEAR_FEATURE for TEST modes.
                                                                                +- +-

                                                                                +-Definition at line 1644 of file dwc_otg_pcd_intr.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                void pcd_setup ( dwc_otg_pcd_t *  pcd  )  [inline, static]
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This function processes SETUP commands. +-

                                                                                +-In Linux, the USB Command processing is done in two places - the first being the PCD and the second in the Gadget Driver (for example, the File-Backed Storage Gadget Driver).

                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                Command Driver Description

                                                                                +-

                                                                                GET_STATUS PCD Command is processed as defined in chapter 9 of the USB 2.0 Specification chapter 9

                                                                                +-

                                                                                CLEAR_FEATURE PCD The Device and Endpoint requests are the ENDPOINT_HALT feature is procesed, all others the interface requests are ignored.

                                                                                +-

                                                                                SET_FEATURE PCD The Device and Endpoint requests are processed by the PCD. Interface requests are passed to the Gadget Driver.

                                                                                +-

                                                                                SET_ADDRESS PCD Program the DCFG reg, with device address received

                                                                                +-

                                                                                GET_DESCRIPTOR Gadget Driver Return the requested descriptor

                                                                                +-

                                                                                SET_DESCRIPTOR Gadget Driver Optional - not implemented by any of the existing Gadget Drivers.

                                                                                +-

                                                                                SET_CONFIGURATION Gadget Driver Disable all EPs and enable EPs for new configuration.

                                                                                +-

                                                                                GET_CONFIGURATION Gadget Driver Return the current configuration

                                                                                +-

                                                                                SET_INTERFACE Gadget Driver Disable all EPs and enable EPs for new configuration.

                                                                                +-

                                                                                GET_INTERFACE Gadget Driver Return the current interface.

                                                                                +-

                                                                                SYNC_FRAME PCD Display debug message.
                                                                                +-

                                                                                +-When the SETUP Phase Done interrupt occurs, the PCD SETUP commands are processed by pcd_setup. Calling the Function Driver's setup function from pcd_setup processes the gadget SETUP commands.

                                                                                +-

                                                                                Todo:
                                                                                handle > 1 setup packet , assert error for now

                                                                                +-NGS: Handle bad setup packet?

                                                                                +- +-

                                                                                +-Definition at line 1756 of file dwc_otg_pcd_intr.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                void complete_ep ( dwc_otg_pcd_ep_t *  ep  )  [static]
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This function completes the request for the EP. +-

                                                                                +-If there are additional requests for the EP in the queue they will be started. +-

                                                                                +-Definition at line 2088 of file dwc_otg_pcd_intr.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                void set_current_pkt_info ( dwc_otg_core_if_t *  core_if,
                                                                                dwc_ep_t *  ep
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This function sets latest iso packet information(non-PTI mode). +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +-
                                                                                core_if Programming view of DWC_otg controller.
                                                                                ep The EP to start the transfer on.
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 2490 of file dwc_otg_pcd_intr.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                void set_ddma_iso_pkts_info ( dwc_otg_core_if_t *  core_if,
                                                                                dwc_ep_t *  dwc_ep
                                                                                )  [static]
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This function sets latest iso packet information(DDMA mode). +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +-
                                                                                core_if Programming view of DWC_otg controller.
                                                                                dwc_ep The EP to start the transfer on.
                                                                                +-
                                                                                +-

                                                                                +-Reinit closed DMA Descriptors

                                                                                +-ISO OUT EP

                                                                                +-ISO IN EP +-

                                                                                +-Definition at line 2538 of file dwc_otg_pcd_intr.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                void reinit_ddma_iso_xfer ( dwc_otg_core_if_t *  core_if,
                                                                                dwc_ep_t *  dwc_ep
                                                                                )  [static]
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This function reinitialize DMA Descriptors for Isochronous transfer. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +-
                                                                                core_if Programming view of DWC_otg controller.
                                                                                dwc_ep The EP to start the transfer on.
                                                                                +-
                                                                                +-

                                                                                +-Buffer 0 descriptors setup

                                                                                +-Buffer 1 descriptors setup

                                                                                +-Reinit closed DMA Descriptors

                                                                                +-ISO OUT EP

                                                                                +-ISO IN EP +-

                                                                                +-Definition at line 2701 of file dwc_otg_pcd_intr.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                uint32_t handle_iso_out_pkt_dropped ( dwc_otg_core_if_t *  core_if,
                                                                                dwc_ep_t *  dwc_ep
                                                                                )  [static]
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This function is to handle Iso EP transfer complete interrupt in case Iso out packet was dropped. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +-
                                                                                core_if Programming view of DWC_otg controller.
                                                                                dwc_ep The EP for wihich transfer complete was asserted
                                                                                +-
                                                                                +-

                                                                                +-Re-enable endpoint, clear nak +-

                                                                                +-Definition at line 2835 of file dwc_otg_pcd_intr.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                uint32_t set_iso_pkts_info ( dwc_otg_core_if_t *  core_if,
                                                                                dwc_ep_t *  ep
                                                                                )  [static]
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This function sets iso packets information(PTI mode). +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +-
                                                                                core_if Programming view of DWC_otg controller.
                                                                                ep The EP to start the transfer on.
                                                                                +-
                                                                                +-

                                                                                +-Buffer 0 descriptors setup

                                                                                +-Buffer 1 descriptors setup +-

                                                                                +-Definition at line 2906 of file dwc_otg_pcd_intr.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                void complete_iso_ep ( dwc_otg_pcd_t *  pcd,
                                                                                dwc_otg_pcd_ep_t *  ep
                                                                                )  [static]
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This function is to handle Iso EP transfer complete interrupt. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +-
                                                                                pcd The PCD
                                                                                ep The EP for which transfer complete was asserted
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 2982 of file dwc_otg_pcd_intr.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                void handle_ep0 ( dwc_otg_pcd_t *  pcd  )  [static]
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This function handles EP0 Control transfers. +-

                                                                                +-The state of the control tranfers are tracked in ep0state. +-

                                                                                +-Definition at line 3110 of file dwc_otg_pcd_intr.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                void handle_in_ep_timeout_intr ( dwc_otg_pcd_t *  pcd,
                                                                                const uint32_t  epnum
                                                                                )  [inline, static]
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Handler for the IN EP timeout handshake interrupt. +-

                                                                                +-

                                                                                Todo:
                                                                                NGS Check EP type. Implement for Periodic EPs
                                                                                +- +-

                                                                                +-Definition at line 3611 of file dwc_otg_pcd_intr.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                int32_t handle_in_ep_nak_intr ( dwc_otg_pcd_t *  pcd,
                                                                                const uint32_t  epnum
                                                                                )  [inline, static]
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Handler for the IN EP NAK interrupt. +-

                                                                                +-

                                                                                Todo:
                                                                                implement ISR
                                                                                +- +-

                                                                                +-Definition at line 3672 of file dwc_otg_pcd_intr.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                int32_t handle_out_ep_babble_intr ( dwc_otg_pcd_t *  pcd,
                                                                                const uint32_t  epnum
                                                                                )  [inline, static]
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Handler for the OUT EP Babble interrupt. +-

                                                                                +-

                                                                                Todo:
                                                                                implement ISR
                                                                                +- +-

                                                                                +-Definition at line 3697 of file dwc_otg_pcd_intr.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                int32_t handle_out_ep_nak_intr ( dwc_otg_pcd_t *  pcd,
                                                                                const uint32_t  epnum
                                                                                )  [inline, static]
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Handler for the OUT EP NAK interrupt. +-

                                                                                +-

                                                                                Todo:
                                                                                implement ISR
                                                                                +- +-

                                                                                +-Definition at line 3723 of file dwc_otg_pcd_intr.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                int32_t handle_out_ep_nyet_intr ( dwc_otg_pcd_t *  pcd,
                                                                                const uint32_t  epnum
                                                                                )  [inline, static]
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Handler for the OUT EP NYET interrupt. +-

                                                                                +-

                                                                                Todo:
                                                                                implement ISR
                                                                                +- +-

                                                                                +-Definition at line 3748 of file dwc_otg_pcd_intr.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                int32_t dwc_otg_pcd_handle_in_ep_intr ( dwc_otg_pcd_t *  pcd  )  [static]
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This interrupt indicates that an IN EP has a pending Interrupt. +-

                                                                                +-The sequence for handling the IN EP interrupt is shown below:

                                                                                  +-
                                                                                1. Read the Device All Endpoint Interrupt register
                                                                                2. Repeat the following for each IN EP interrupt bit set (from LSB to MSB).
                                                                                3. Read the Device Endpoint Interrupt (DIEPINTn) register
                                                                                4. If "Transfer Complete" call the request complete function
                                                                                5. If "Endpoint Disabled" complete the EP disable procedure.
                                                                                6. If "AHB Error Interrupt" log error
                                                                                7. If "Time-out Handshake" log error
                                                                                8. If "IN Token Received when TxFIFO Empty" write packet to Tx FIFO.
                                                                                9. If "IN Token EP Mismatch" (disable, this is handled by EP Mismatch Interrupt)
                                                                                +-

                                                                                +-IN Token received with TxF Empty

                                                                                +-IN Token Received with EP mismatch

                                                                                +-IN Endpoint NAK Effective

                                                                                +-IN EP Tx FIFO Empty Intr

                                                                                +-IN EP BNA Intr +-

                                                                                +-Definition at line 3786 of file dwc_otg_pcd_intr.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                int32_t dwc_otg_pcd_handle_out_ep_intr ( dwc_otg_pcd_t *  pcd  )  [static]
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This interrupt indicates that an OUT EP has a pending Interrupt. +-

                                                                                +-The sequence for handling the OUT EP interrupt is shown below:

                                                                                  +-
                                                                                1. Read the Device All Endpoint Interrupt register
                                                                                2. Repeat the following for each OUT EP interrupt bit set (from LSB to MSB).
                                                                                3. Read the Device Endpoint Interrupt (DOEPINTn) register
                                                                                4. If "Transfer Complete" call the request complete function
                                                                                5. If "Endpoint Disabled" complete the EP disable procedure.
                                                                                6. If "AHB Error Interrupt" log error
                                                                                7. If "Setup Phase Done" process Setup Packet (See Standard USB Command Processing)
                                                                                +-

                                                                                +-OUT EP BNA Intr +-

                                                                                +-Definition at line 4068 of file dwc_otg_pcd_intr.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                int32_t dwc_otg_pcd_handle_incomplete_isoc_in_intr ( dwc_otg_pcd_t *  pcd  ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Incomplete ISO IN Transfer Interrupt. +-

                                                                                +-This interrupt indicates one of the following conditions occurred while transmitting an ISOC transaction.

                                                                                  +-
                                                                                • Corrupted IN Token for ISOC EP.
                                                                                • Packet not complete in FIFO. The follow actions will be taken:
                                                                                    +-
                                                                                  1. Determine the EP
                                                                                  2. Set incomplete flag in dwc_ep structure
                                                                                  3. Disable EP; when "Endpoint Disabled" interrupt is received Flush FIFO
                                                                                  +-
                                                                                +- +-

                                                                                +-Definition at line 4348 of file dwc_otg_pcd_intr.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                int32_t dwc_otg_pcd_handle_incomplete_isoc_out_intr ( dwc_otg_pcd_t *  pcd  ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Incomplete ISO OUT Transfer Interrupt. +-

                                                                                +-This interrupt indicates that the core has dropped an ISO OUT packet. The following conditions can be the cause:

                                                                                  +-
                                                                                • FIFO Full, the entire packet would not fit in the FIFO.
                                                                                • CRC Error
                                                                                • Corrupted Token The follow actions will be taken:
                                                                                    +-
                                                                                  1. Determine the EP
                                                                                  2. Set incomplete flag in dwc_ep structure
                                                                                  3. Read any data from the FIFO
                                                                                  4. Disable EP. When "Endpoint Disabled" interrupt is received re-enable EP.
                                                                                  +-
                                                                                +- +-

                                                                                +-Definition at line 4458 of file dwc_otg_pcd_intr.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                int32_t dwc_otg_pcd_handle_intr ( dwc_otg_pcd_t *  pcd  ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This function should be called on every hardware interrupt. +-

                                                                                +-The PCD handles the device interrupts. Many conditions can cause a device interrupt. When an interrupt occurs, the device interrupt service routine determines the cause of the interrupt and dispatches handling to the appropriate function. These interrupt handling functions are described below.

                                                                                +-All interrupt registers are processed from LSB to MSB. +-

                                                                                +-Definition at line 4702 of file dwc_otg_pcd_intr.c.

                                                                                +-

                                                                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__pcd__linux_8c-source.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/dwc__otg__pcd__linux_8c-source.html 2013-07-26 19:34:42.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,1122 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_pcd_linux.c Source File +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                dwc_otg_pcd_linux.c

                                                                                Go to the documentation of this file.
                                                                                00001  /* ==========================================================================
+-00002   * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_pcd_linux.c $
+-00003   * $Revision: #19 $
+-00004   * $Date: 2011/10/26 $
+-00005   * $Change: 1873028 $
+-00006   *
+-00007   * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
+-00008   * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
+-00009   * otherwise expressly agreed to in writing between Synopsys and you.
+-00010   *
+-00011   * The Software IS NOT an item of Licensed Software or Licensed Product under
+-00012   * any End User Software License Agreement or Agreement for Licensed Product
+-00013   * with Synopsys or any supplement thereto. You are permitted to use and
+-00014   * redistribute this Software in source and binary forms, with or without
+-00015   * modification, provided that redistributions of source code must retain this
+-00016   * notice. You may not view, use, disclose, copy or distribute this file or
+-00017   * any information contained herein except pursuant to this license grant from
+-00018   * Synopsys. If you do not agree with this notice, including the disclaimer
+-00019   * below, then you are not authorized to use the Software.
+-00020   *
+-00021   * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
+-00022   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+-00023   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+-00024   * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
+-00025   * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+-00026   * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+-00027   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+-00028   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+-00029   * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+-00030   * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+-00031   * DAMAGE.
+-00032   * ========================================================================== */
+-00033 #ifndef DWC_HOST_ONLY
+-00034 
+-00056 #include "dwc_otg_os_dep.h"
+-00057 #include "dwc_otg_pcd_if.h"
+-00058 #include "dwc_otg_pcd.h"
+-00059 #include "dwc_otg_driver.h"
+-00060 #include "dwc_otg_dbg.h"
+-00061 
+-00062 static struct gadget_wrapper {
+-00063         dwc_otg_pcd_t *pcd;
+-00064 
+-00065         struct usb_gadget gadget;
+-00066         struct usb_gadget_driver *driver;
+-00067 
+-00068         struct usb_ep ep0;
+-00069         struct usb_ep in_ep[16];
+-00070         struct usb_ep out_ep[16];
+-00071 
+-00072 } *gadget_wrapper;
+-00073 
+-00074 /* Display the contents of the buffer */
+-00075 extern void dump_msg(const u8 * buf, unsigned int length);
+-00080 static struct dwc_otg_pcd_ep *ep_from_handle(dwc_otg_pcd_t * pcd, void *handle)
+-00081 {
+-00082         int i;
+-00083         if (pcd->ep0.priv == handle) {
+-00084                 return &pcd->ep0;
+-00085         }
+-00086 
+-00087         for (i = 0; i < MAX_EPS_CHANNELS - 1; i++) {
+-00088                 if (pcd->in_ep[i].priv == handle)
+-00089                         return &pcd->in_ep[i];
+-00090                 if (pcd->out_ep[i].priv == handle)
+-00091                         return &pcd->out_ep[i];
+-00092         }
+-00093 
+-00094         return NULL;
+-00095 }
+-00096 
+-00097 /* USB Endpoint Operations */
+-00098 /*
+-00099  * The following sections briefly describe the behavior of the Gadget
+-00100  * API endpoint operations implemented in the DWC_otg driver
+-00101  * software. Detailed descriptions of the generic behavior of each of
+-00102  * these functions can be found in the Linux header file
+-00103  * include/linux/usb_gadget.h.
+-00104  *
+-00105  * The Gadget API provides wrapper functions for each of the function
+-00106  * pointers defined in usb_ep_ops. The Gadget Driver calls the wrapper
+-00107  * function, which then calls the underlying PCD function. The
+-00108  * following sections are named according to the wrapper
+-00109  * functions. Within each section, the corresponding DWC_otg PCD
+-00110  * function name is specified.
+-00111  *
+-00112  */
+-00113 
+-00121 static int ep_enable(struct usb_ep *usb_ep,
+-00122                      const struct usb_endpoint_descriptor *ep_desc)
+-00123 {
+-00124         int retval;
+-00125 
+-00126         DWC_DEBUGPL(DBG_PCDV, "%s(%p,%p)\n", __func__, usb_ep, ep_desc);
+-00127 
+-00128         if (!usb_ep || !ep_desc || ep_desc->bDescriptorType != USB_DT_ENDPOINT) {
+-00129                 DWC_WARN("%s, bad ep or descriptor\n", __func__);
+-00130                 return -EINVAL;
+-00131         }
+-00132         if (usb_ep == &gadget_wrapper->ep0) {
+-00133                 DWC_WARN("%s, bad ep(0)\n", __func__);
+-00134                 return -EINVAL;
+-00135         }
+-00136 
+-00137         /* Check FIFO size? */
+-00138         if (!ep_desc->wMaxPacketSize) {
+-00139                 DWC_WARN("%s, bad %s maxpacket\n", __func__, usb_ep->name);
+-00140                 return -ERANGE;
+-00141         }
+-00142 
+-00143         if (!gadget_wrapper->driver ||
+-00144             gadget_wrapper->gadget.speed == USB_SPEED_UNKNOWN) {
+-00145                 DWC_WARN("%s, bogus device state\n", __func__);
+-00146                 return -ESHUTDOWN;
+-00147         }
+-00148 
+-00149         /* Delete after check - MAS */
+-00150 #if 0
+-00151         nat = (uint32_t) ep_desc->wMaxPacketSize;
+-00152         printk(KERN_ALERT "%s: nat (before) =%d\n", __func__, nat);
+-00153         nat = (nat >> 11) & 0x03;
+-00154         printk(KERN_ALERT "%s: nat (after) =%d\n", __func__, nat);
+-00155 #endif
+-00156         retval = dwc_otg_pcd_ep_enable(gadget_wrapper->pcd,
+-00157                                        (const uint8_t *)ep_desc,
+-00158                                        (void *)usb_ep);
+-00159         if (retval) {
+-00160                 DWC_WARN("dwc_otg_pcd_ep_enable failed\n");
+-00161                 return -EINVAL;
+-00162         }
+-00163 
+-00164         usb_ep->maxpacket = le16_to_cpu(ep_desc->wMaxPacketSize);
+-00165 
+-00166         return 0;
+-00167 }
+-00168 
+-00177 static int ep_disable(struct usb_ep *usb_ep)
+-00178 {
+-00179         int retval;
+-00180 
+-00181         DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, usb_ep);
+-00182         if (!usb_ep) {
+-00183                 DWC_DEBUGPL(DBG_PCD, "%s, %s not enabled\n", __func__,
+-00184                             usb_ep ? usb_ep->name : NULL);
+-00185                 return -EINVAL;
+-00186         }
+-00187 
+-00188         retval = dwc_otg_pcd_ep_disable(gadget_wrapper->pcd, usb_ep);
+-00189         if (retval) {
+-00190                 retval = -EINVAL;
+-00191         }
+-00192 
+-00193         return retval;
+-00194 }
+-00195 
+-00203 static struct usb_request *dwc_otg_pcd_alloc_request(struct usb_ep *ep,
+-00204                                                      gfp_t gfp_flags)
+-00205 {
+-00206         struct usb_request *usb_req;
+-00207 
+-00208         DWC_DEBUGPL(DBG_PCDV, "%s(%p,%d)\n", __func__, ep, gfp_flags);
+-00209         if (0 == ep) {
+-00210                 DWC_WARN("%s() %s\n", __func__, "Invalid EP!\n");
+-00211                 return 0;
+-00212         }
+-00213         usb_req = kmalloc(sizeof(*usb_req), gfp_flags);
+-00214         if (0 == usb_req) {
+-00215                 DWC_WARN("%s() %s\n", __func__, "request allocation failed!\n");
+-00216                 return 0;
+-00217         }
+-00218         memset(usb_req, 0, sizeof(*usb_req));
+-00219         usb_req->dma = DWC_DMA_ADDR_INVALID;
+-00220 
+-00221         return usb_req;
+-00222 }
+-00223 
+-00230 static void dwc_otg_pcd_free_request(struct usb_ep *ep, struct usb_request *req)
+-00231 {
+-00232         DWC_DEBUGPL(DBG_PCDV, "%s(%p,%p)\n", __func__, ep, req);
+-00233 
+-00234         if (0 == ep || 0 == req) {
+-00235                 DWC_WARN("%s() %s\n", __func__,
+-00236                          "Invalid ep or req argument!\n");
+-00237                 return;
+-00238         }
+-00239 
+-00240         kfree(req);
+-00241 }
+-00242 
+-00243 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28)
+-00244 
+-00254 static void *dwc_otg_pcd_alloc_buffer(struct usb_ep *usb_ep, unsigned bytes,
+-00255                                       dma_addr_t * dma, gfp_t gfp_flags)
+-00256 {
+-00257         void *buf;
+-00258         dwc_otg_pcd_t *pcd = 0;
+-00259 
+-00260         pcd = gadget_wrapper->pcd;
+-00261 
+-00262         DWC_DEBUGPL(DBG_PCDV, "%s(%p,%d,%p,%0x)\n", __func__, usb_ep, bytes,
+-00263                     dma, gfp_flags);
+-00264 
+-00265         /* Check dword alignment */
+-00266         if ((bytes & 0x3UL) != 0) {
+-00267                 DWC_WARN("%s() Buffer size is not a multiple of"
+-00268                          "DWORD size (%d)", __func__, bytes);
+-00269         }
+-00270 
+-00271         buf = dma_alloc_coherent(NULL, bytes, dma, gfp_flags);
+-00272 
+-00273         /* Check dword alignment */
+-00274         if (((int)buf & 0x3UL) != 0) {
+-00275                 DWC_WARN("%s() Buffer is not DWORD aligned (%p)",
+-00276                          __func__, buf);
+-00277         }
+-00278 
+-00279         return buf;
+-00280 }
+-00281 
+-00290 static void dwc_otg_pcd_free_buffer(struct usb_ep *usb_ep, void *buf,
+-00291                                     dma_addr_t dma, unsigned bytes)
+-00292 {
+-00293         dwc_otg_pcd_t *pcd = 0;
+-00294 
+-00295         pcd = gadget_wrapper->pcd;
+-00296 
+-00297         DWC_DEBUGPL(DBG_PCDV, "%s(%p,%0x,%d)\n", __func__, buf, dma, bytes);
+-00298 
+-00299         dma_free_coherent(NULL, bytes, buf, dma);
+-00300 }
+-00301 #endif
+-00302 
+-00317 static int ep_queue(struct usb_ep *usb_ep, struct usb_request *usb_req,
+-00318                     gfp_t gfp_flags)
+-00319 {
+-00320         dwc_otg_pcd_t *pcd;
+-00321         struct dwc_otg_pcd_ep *ep = NULL;
+-00322         int retval = 0, is_isoc_ep = 0;
+-00323         dma_addr_t dma_addr = DWC_DMA_ADDR_INVALID;
+-00324 
+-00325         DWC_DEBUGPL(DBG_PCDV, "%s(%p,%p,%d)\n",
+-00326                     __func__, usb_ep, usb_req, gfp_flags);
+-00327 
+-00328         if (!usb_req || !usb_req->complete || !usb_req->buf) {
+-00329                 DWC_WARN("bad params\n");
+-00330                 return -EINVAL;
+-00331         }
+-00332 
+-00333         if (!usb_ep) {
+-00334                 DWC_WARN("bad ep\n");
+-00335                 return -EINVAL;
+-00336         }
+-00337 
+-00338         pcd = gadget_wrapper->pcd;
+-00339         if (!gadget_wrapper->driver ||
+-00340             gadget_wrapper->gadget.speed == USB_SPEED_UNKNOWN) {
+-00341                 DWC_DEBUGPL(DBG_PCDV, "gadget.speed=%d\n",
+-00342                             gadget_wrapper->gadget.speed);
+-00343                 DWC_WARN("bogus device state\n");
+-00344                 return -ESHUTDOWN;
+-00345         }
+-00346 
+-00347         DWC_DEBUGPL(DBG_PCD, "%s queue req %p, len %d buf %p\n",
+-00348                     usb_ep->name, usb_req, usb_req->length, usb_req->buf);
+-00349 
+-00350         usb_req->status = -EINPROGRESS;
+-00351         usb_req->actual = 0;
+-00352 
+-00353         ep = ep_from_handle(pcd, usb_ep);
+-00354         if (ep == NULL)
+-00355                 is_isoc_ep = 0;
+-00356         else
+-00357                 is_isoc_ep = (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) ? 1 : 0;
+-00358 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28)
+-00359         dma_addr = usb_req->dma;
+-00360 #else
+-00361         if (GET_CORE_IF(pcd)->dma_enable) {
+-00362                 struct pci_dev *dev = gadget_wrapper->pcd->otg_dev->os_dep.pcidev;
+-00363                 if (usb_req->length != 0 && usb_req->dma == DWC_DMA_ADDR_INVALID) {
+-00364                         dma_addr = pci_map_single(dev, usb_req->buf, usb_req->length, 
+-00365                                         ep->dwc_ep.is_in ? PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
+-00366                 }
+-00367         }
+-00368 #endif
+-00369 
+-00370 #ifdef DWC_UTE_PER_IO
+-00371         if (is_isoc_ep == 1) {
+-00372                 retval = dwc_otg_pcd_xiso_ep_queue(pcd, usb_ep, usb_req->buf, dma_addr,
+-00373                         usb_req->length, usb_req->zero, usb_req,
+-00374                         gfp_flags == GFP_ATOMIC ? 1 : 0, &usb_req->ext_req);
+-00375                 if (retval)
+-00376                         return -EINVAL;
+-00377 
+-00378                 return 0;
+-00379         }
+-00380 #endif
+-00381         retval = dwc_otg_pcd_ep_queue(pcd, usb_ep, usb_req->buf, dma_addr,
+-00382                                       usb_req->length, usb_req->zero, usb_req,
+-00383                                       gfp_flags == GFP_ATOMIC ? 1 : 0);
+-00384         if (retval) {
+-00385                 return -EINVAL;
+-00386         }
+-00387 
+-00388         return 0;
+-00389 }
+-00390 
+-00394 static int ep_dequeue(struct usb_ep *usb_ep, struct usb_request *usb_req)
+-00395 {
+-00396         DWC_DEBUGPL(DBG_PCDV, "%s(%p,%p)\n", __func__, usb_ep, usb_req);
+-00397 
+-00398         if (!usb_ep || !usb_req) {
+-00399                 DWC_WARN("bad argument\n");
+-00400                 return -EINVAL;
+-00401         }
+-00402         if (!gadget_wrapper->driver ||
+-00403             gadget_wrapper->gadget.speed == USB_SPEED_UNKNOWN) {
+-00404                 DWC_WARN("bogus device state\n");
+-00405                 return -ESHUTDOWN;
+-00406         }
+-00407         if (dwc_otg_pcd_ep_dequeue(gadget_wrapper->pcd, usb_ep, usb_req)) {
+-00408                 return -EINVAL;
+-00409         }
+-00410 
+-00411         return 0;
+-00412 }
+-00413 
+-00430 static int ep_halt(struct usb_ep *usb_ep, int value)
+-00431 {
+-00432         int retval = 0;
+-00433 
+-00434         DWC_DEBUGPL(DBG_PCD, "HALT %s %d\n", usb_ep->name, value);
+-00435 
+-00436         if (!usb_ep) {
+-00437                 DWC_WARN("bad ep\n");
+-00438                 return -EINVAL;
+-00439         }
+-00440 
+-00441         retval = dwc_otg_pcd_ep_halt(gadget_wrapper->pcd, usb_ep, value);
+-00442         if (retval == -DWC_E_AGAIN) {
+-00443                 return -EAGAIN;
+-00444         } else if (retval) {
+-00445                 retval = -EINVAL;
+-00446         }
+-00447 
+-00448         return retval;
+-00449 }
+-00450 
+-00451 #ifdef DWC_EN_ISOC
+-00452 
+-00461 static int iso_ep_start(struct usb_ep *usb_ep, struct usb_iso_request *req,
+-00462                         gfp_t gfp_flags)
+-00463 {
+-00464         int retval = 0;
+-00465 
+-00466         if (!req || !req->process_buffer || !req->buf0 || !req->buf1) {
+-00467                 DWC_WARN("bad params\n");
+-00468                 return -EINVAL;
+-00469         }
+-00470 
+-00471         if (!usb_ep) {
+-00472                 DWC_PRINTF("bad params\n");
+-00473                 return -EINVAL;
+-00474         }
+-00475 
+-00476         req->status = -EINPROGRESS;
+-00477 
+-00478         retval =
+-00479             dwc_otg_pcd_iso_ep_start(gadget_wrapper->pcd, usb_ep, req->buf0,
+-00480                                      req->buf1, req->dma0, req->dma1,
+-00481                                      req->sync_frame, req->data_pattern_frame,
+-00482                                      req->data_per_frame,
+-00483                                      req->flags & USB_REQ_ISO_ASAP ? -1 : req->
+-00484                                      start_frame, req->buf_proc_intrvl, req,
+-00485                                      gfp_flags == GFP_ATOMIC ? 1 : 0);
+-00486 
+-00487         if (retval) {
+-00488                 return -EINVAL;
+-00489         }
+-00490 
+-00491         return retval;
+-00492 }
+-00493 
+-00497 static int iso_ep_stop(struct usb_ep *usb_ep, struct usb_iso_request *req)
+-00498 {
+-00499         int retval = 0;
+-00500         if (!usb_ep) {
+-00501                 DWC_WARN("bad ep\n");
+-00502         }
+-00503 
+-00504         if (!gadget_wrapper->driver ||
+-00505             gadget_wrapper->gadget.speed == USB_SPEED_UNKNOWN) {
+-00506                 DWC_DEBUGPL(DBG_PCDV, "gadget.speed=%d\n",
+-00507                             gadget_wrapper->gadget.speed);
+-00508                 DWC_WARN("bogus device state\n");
+-00509         }
+-00510 
+-00511         dwc_otg_pcd_iso_ep_stop(gadget_wrapper->pcd, usb_ep, req);
+-00512         if (retval) {
+-00513                 retval = -EINVAL;
+-00514         }
+-00515 
+-00516         return retval;
+-00517 }
+-00518 
+-00519 static struct usb_iso_request *alloc_iso_request(struct usb_ep *ep,
+-00520                                                  int packets, gfp_t gfp_flags)
+-00521 {
+-00522         struct usb_iso_request *pReq = NULL;
+-00523         uint32_t req_size;
+-00524 
+-00525         req_size = sizeof(struct usb_iso_request);
+-00526         req_size +=
+-00527             (2 * packets * (sizeof(struct usb_gadget_iso_packet_descriptor)));
+-00528 
+-00529         pReq = kmalloc(req_size, gfp_flags);
+-00530         if (!pReq) {
+-00531                 DWC_WARN("Can't allocate Iso Request\n");
+-00532                 return 0;
+-00533         }
+-00534         pReq->iso_packet_desc0 = (void *)(pReq + 1);
+-00535 
+-00536         pReq->iso_packet_desc1 = pReq->iso_packet_desc0 + packets;
+-00537 
+-00538         return pReq;
+-00539 }
+-00540 
+-00541 static void free_iso_request(struct usb_ep *ep, struct usb_iso_request *req)
+-00542 {
+-00543         kfree(req);
+-00544 }
+-00545 
+-00546 static struct usb_isoc_ep_ops dwc_otg_pcd_ep_ops = {
+-00547         .ep_ops = {
+-00548                    .enable = ep_enable,
+-00549                    .disable = ep_disable,
+-00550 
+-00551                    .alloc_request = dwc_otg_pcd_alloc_request,
+-00552                    .free_request = dwc_otg_pcd_free_request,
+-00553 
+-00554 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28)
+-00555                    .alloc_buffer = dwc_otg_pcd_alloc_buffer,
+-00556                    .free_buffer = dwc_otg_pcd_free_buffer,
+-00557 #endif
+-00558 
+-00559                    .queue = ep_queue,
+-00560                    .dequeue = ep_dequeue,
+-00561 
+-00562                    .set_halt = ep_halt,
+-00563                    .fifo_status = 0,
+-00564                    .fifo_flush = 0,
+-00565                    },
+-00566         .iso_ep_start = iso_ep_start,
+-00567         .iso_ep_stop = iso_ep_stop,
+-00568         .alloc_iso_request = alloc_iso_request,
+-00569         .free_iso_request = free_iso_request,
+-00570 };
+-00571 
+-00572 #else
+-00573 
+-00574 static struct usb_ep_ops dwc_otg_pcd_ep_ops = {
+-00575         .enable = ep_enable,
+-00576         .disable = ep_disable,
+-00577 
+-00578         .alloc_request = dwc_otg_pcd_alloc_request,
+-00579         .free_request = dwc_otg_pcd_free_request,
+-00580 
+-00581 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,28)
+-00582         .alloc_buffer = dwc_otg_pcd_alloc_buffer,
+-00583         .free_buffer = dwc_otg_pcd_free_buffer,
+-00584 #endif
+-00585 
+-00586         .queue = ep_queue,
+-00587         .dequeue = ep_dequeue,
+-00588 
+-00589         .set_halt = ep_halt,
+-00590         .fifo_status = 0,
+-00591         .fifo_flush = 0,
+-00592 
+-00593 };
+-00594 
+-00595 #endif /* _EN_ISOC_ */
+-00596 /*      Gadget Operations */
+-00615 static int get_frame_number(struct usb_gadget *gadget)
+-00616 {
+-00617         struct gadget_wrapper *d;
+-00618 
+-00619         DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, gadget);
+-00620 
+-00621         if (gadget == 0) {
+-00622                 return -ENODEV;
+-00623         }
+-00624 
+-00625         d = container_of(gadget, struct gadget_wrapper, gadget);
+-00626         return dwc_otg_pcd_get_frame_number(d->pcd);
+-00627 }
+-00628 
+-00629 #ifdef CONFIG_USB_DWC_OTG_LPM
+-00630 static int test_lpm_enabled(struct usb_gadget *gadget)
+-00631 {
+-00632         struct gadget_wrapper *d;
+-00633 
+-00634         d = container_of(gadget, struct gadget_wrapper, gadget);
+-00635 
+-00636         return dwc_otg_pcd_is_lpm_enabled(d->pcd);
+-00637 }
+-00638 #endif
+-00639 
+-00646 static int wakeup(struct usb_gadget *gadget)
+-00647 {
+-00648         struct gadget_wrapper *d;
+-00649 
+-00650         DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, gadget);
+-00651 
+-00652         if (gadget == 0) {
+-00653                 return -ENODEV;
+-00654         } else {
+-00655                 d = container_of(gadget, struct gadget_wrapper, gadget);
+-00656         }
+-00657         dwc_otg_pcd_wakeup(d->pcd);
+-00658         return 0;
+-00659 }
+-00660 
+-00661 static const struct usb_gadget_ops dwc_otg_pcd_ops = {
+-00662         .get_frame = get_frame_number,
+-00663         .wakeup = wakeup,
+-00664 #ifdef CONFIG_USB_DWC_OTG_LPM
+-00665         .lpm_support = test_lpm_enabled,
+-00666 #endif
+-00667         // current versions must always be self-powered
+-00668 };
+-00669 
+-00670 static int _setup(dwc_otg_pcd_t * pcd, uint8_t * bytes)
+-00671 {
+-00672         int retval = -DWC_E_NOT_SUPPORTED;
+-00673         if (gadget_wrapper->driver && gadget_wrapper->driver->setup) {
+-00674                 retval = gadget_wrapper->driver->setup(&gadget_wrapper->gadget,
+-00675                                                        (struct usb_ctrlrequest
+-00676                                                         *)bytes);
+-00677         }
+-00678 
+-00679         if (retval == -ENOTSUPP) {
+-00680                 retval = -DWC_E_NOT_SUPPORTED;
+-00681         } else if (retval < 0) {
+-00682                 retval = -DWC_E_INVALID;
+-00683         }
+-00684 
+-00685         return retval;
+-00686 }
+-00687 
+-00688 #ifdef DWC_EN_ISOC
+-00689 static int _isoc_complete(dwc_otg_pcd_t * pcd, void *ep_handle,
+-00690                           void *req_handle, int proc_buf_num)
+-00691 {
+-00692         int i, packet_count;
+-00693         struct usb_gadget_iso_packet_descriptor *iso_packet = 0;
+-00694         struct usb_iso_request *iso_req = req_handle;
+-00695 
+-00696         if (proc_buf_num) {
+-00697                 iso_packet = iso_req->iso_packet_desc1;
+-00698         } else {
+-00699                 iso_packet = iso_req->iso_packet_desc0;
+-00700         }
+-00701         packet_count =
+-00702             dwc_otg_pcd_get_iso_packet_count(pcd, ep_handle, req_handle);
+-00703         for (i = 0; i < packet_count; ++i) {
+-00704                 int status;
+-00705                 int actual;
+-00706                 int offset;
+-00707                 dwc_otg_pcd_get_iso_packet_params(pcd, ep_handle, req_handle,
+-00708                                                   i, &status, &actual, &offset);
+-00709                 switch (status) {
+-00710                 case -DWC_E_NO_DATA:
+-00711                         status = -ENODATA;
+-00712                         break;
+-00713                 default:
+-00714                         if (status) {
+-00715                                 DWC_PRINTF("unknown status in isoc packet\n");
+-00716                         }
+-00717 
+-00718                 }
+-00719                 iso_packet[i].status = status;
+-00720                 iso_packet[i].offset = offset;
+-00721                 iso_packet[i].actual_length = actual;
+-00722         }
+-00723 
+-00724         iso_req->status = 0;
+-00725         iso_req->process_buffer(ep_handle, iso_req);
+-00726 
+-00727         return 0;
+-00728 }
+-00729 #endif /* DWC_EN_ISOC */
+-00730 
+-00731 #ifdef DWC_UTE_PER_IO
+-00732 
+-00744 static int _xisoc_complete(dwc_otg_pcd_t * pcd, void *ep_handle,
+-00745                            void *req_handle, int32_t status, void *ereq_port)
+-00746 {
+-00747         struct dwc_ute_iso_req_ext *ereqorg = NULL;
+-00748         struct dwc_iso_xreq_port *ereqport = NULL;
+-00749         struct dwc_ute_iso_packet_descriptor *desc_org = NULL;
+-00750         int i;
+-00751         struct usb_request *req;
+-00752         //struct dwc_ute_iso_packet_descriptor *
+-00753         //int status = 0;
+-00754 
+-00755         req = (struct usb_request *)req_handle;
+-00756         ereqorg = &req->ext_req;
+-00757         ereqport = (struct dwc_iso_xreq_port *)ereq_port;
+-00758         desc_org = ereqorg->per_io_frame_descs;
+-00759 
+-00760         if (req && req->complete) {
+-00761                 /* Copy the request data from the portable logic to our request */
+-00762                 for (i = 0; i < ereqport->pio_pkt_count; i++) {
+-00763                         desc_org[i].actual_length =
+-00764                             ereqport->per_io_frame_descs[i].actual_length;
+-00765                         desc_org[i].status =
+-00766                             ereqport->per_io_frame_descs[i].status;
+-00767                 }
+-00768 
+-00769                 switch (status) {
+-00770                 case -DWC_E_SHUTDOWN:
+-00771                         req->status = -ESHUTDOWN;
+-00772                         break;
+-00773                 case -DWC_E_RESTART:
+-00774                         req->status = -ECONNRESET;
+-00775                         break;
+-00776                 case -DWC_E_INVALID:
+-00777                         req->status = -EINVAL;
+-00778                         break;
+-00779                 case -DWC_E_TIMEOUT:
+-00780                         req->status = -ETIMEDOUT;
+-00781                         break;
+-00782                 default:
+-00783                         req->status = status;
+-00784                 }
+-00785 
+-00786                 /* And call the gadget's completion */
+-00787                 req->complete(ep_handle, req);
+-00788         }
+-00789 
+-00790         return 0;
+-00791 }
+-00792 #endif /* DWC_UTE_PER_IO */
+-00793 static int _complete(dwc_otg_pcd_t * pcd, void *ep_handle,
+-00794                      void *req_handle, int32_t status, uint32_t actual)
+-00795 {
+-00796         struct usb_request *req = (struct usb_request *)req_handle;
+-00797 #if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,27)
+-00798         struct dwc_otg_pcd_ep *ep = NULL;
+-00799 #endif
+-00800 #ifdef PCI_INTERFACE
+-00801         struct pci_dev *dev = NULL;
+-00802 #endif
+-00803 
+-00804         if (req && req->complete) {
+-00805                 switch (status) {
+-00806                 case -DWC_E_SHUTDOWN:
+-00807                         req->status = -ESHUTDOWN;
+-00808                         break;
+-00809                 case -DWC_E_RESTART:
+-00810                         req->status = -ECONNRESET;
+-00811                         break;
+-00812                 case -DWC_E_INVALID:
+-00813                         req->status = -EINVAL;
+-00814                         break;
+-00815                 case -DWC_E_TIMEOUT:
+-00816                         req->status = -ETIMEDOUT;
+-00817                         break;
+-00818                 default:
+-00819                         req->status = status;
+-00820 
+-00821                 }
+-00822 
+-00823                 req->actual = actual;
+-00824                 DWC_SPINUNLOCK(pcd->lock);
+-00825                 req->complete(ep_handle, req);
+-00826                 DWC_SPINLOCK(pcd->lock);
+-00827         }
+-00828 #ifdef PCI_INTERFACE
+-00829         dev = gadget_wrapper->pcd->otg_dev->os_dep.pcidev;
+-00830         ep = ep_from_handle(pcd, ep_handle);
+-00831         if (GET_CORE_IF(pcd)->dma_enable) {
+-00832                 if (req->length != 0)
+-00833                         pci_unmap_single(dev, req->dma, req->length,
+-00834                                          ep->dwc_ep.
+-00835                                          is_in ? PCI_DMA_TODEVICE :
+-00836                                          PCI_DMA_FROMDEVICE);
+-00837         }
+-00838 #endif
+-00839 
+-00840         return 0;
+-00841 }
+-00842 
+-00843 static int _connect(dwc_otg_pcd_t * pcd, int speed)
+-00844 {
+-00845         gadget_wrapper->gadget.speed = speed;
+-00846         return 0;
+-00847 }
+-00848 
+-00849 static int _disconnect(dwc_otg_pcd_t * pcd)
+-00850 {
+-00851         if (gadget_wrapper->driver && gadget_wrapper->driver->disconnect) {
+-00852                 gadget_wrapper->driver->disconnect(&gadget_wrapper->gadget);
+-00853         }
+-00854         return 0;
+-00855 }
+-00856 
+-00857 static int _resume(dwc_otg_pcd_t * pcd)
+-00858 {
+-00859         if (gadget_wrapper->driver && gadget_wrapper->driver->resume) {
+-00860                 gadget_wrapper->driver->resume(&gadget_wrapper->gadget);
+-00861         }
+-00862 
+-00863         return 0;
+-00864 }
+-00865 
+-00866 static int _suspend(dwc_otg_pcd_t * pcd)
+-00867 {
+-00868         if (gadget_wrapper->driver && gadget_wrapper->driver->suspend) {
+-00869                 gadget_wrapper->driver->suspend(&gadget_wrapper->gadget);
+-00870         }
+-00871         return 0;
+-00872 }
+-00873 
+-00877 static int _hnp_changed(dwc_otg_pcd_t * pcd)
+-00878 {
+-00879 
+-00880         if (!gadget_wrapper->gadget.is_otg)
+-00881                 return 0;
+-00882 
+-00883         gadget_wrapper->gadget.b_hnp_enable = get_b_hnp_enable(pcd);
+-00884         gadget_wrapper->gadget.a_hnp_support = get_a_hnp_support(pcd);
+-00885         gadget_wrapper->gadget.a_alt_hnp_support = get_a_alt_hnp_support(pcd);
+-00886         return 0;
+-00887 }
+-00888 
+-00889 static int _reset(dwc_otg_pcd_t * pcd)
+-00890 {
+-00891         return 0;
+-00892 }
+-00893 
+-00894 #ifdef DWC_UTE_CFI
+-00895 static int _cfi_setup(dwc_otg_pcd_t * pcd, void *cfi_req)
+-00896 {
+-00897         int retval = -DWC_E_INVALID;
+-00898         if (gadget_wrapper->driver->cfi_feature_setup) {
+-00899                 retval =
+-00900                     gadget_wrapper->driver->
+-00901                     cfi_feature_setup(&gadget_wrapper->gadget,
+-00902                                       (struct cfi_usb_ctrlrequest *)cfi_req);
+-00903         }
+-00904 
+-00905         return retval;
+-00906 }
+-00907 #endif
+-00908 
+-00909 static const struct dwc_otg_pcd_function_ops fops = {
+-00910         .complete = _complete,
+-00911 #ifdef DWC_EN_ISOC
+-00912         .isoc_complete = _isoc_complete,
+-00913 #endif
+-00914         .setup = _setup,
+-00915         .disconnect = _disconnect,
+-00916         .connect = _connect,
+-00917         .resume = _resume,
+-00918         .suspend = _suspend,
+-00919         .hnp_changed = _hnp_changed,
+-00920         .reset = _reset,
+-00921 #ifdef DWC_UTE_CFI
+-00922         .cfi_setup = _cfi_setup,
+-00923 #endif
+-00924 #ifdef DWC_UTE_PER_IO
+-00925         .xisoc_complete = _xisoc_complete,
+-00926 #endif
+-00927 };
+-00928 
+-00932 static irqreturn_t dwc_otg_pcd_irq(int irq, void *dev)
+-00933 {
+-00934         dwc_otg_pcd_t *pcd = dev;
+-00935         int32_t retval = IRQ_NONE;
+-00936 
+-00937         retval = dwc_otg_pcd_handle_intr(pcd);
+-00938         if (retval != 0) {
+-00939                 S3C2410X_CLEAR_EINTPEND();
+-00940         }
+-00941         return IRQ_RETVAL(retval);
+-00942 }
+-00943 
+-00950 void gadget_add_eps(struct gadget_wrapper *d)
+-00951 {
+-00952         static const char *names[] = {
+-00953 
+-00954                 "ep0",
+-00955                 "ep1in",
+-00956                 "ep2in",
+-00957                 "ep3in",
+-00958                 "ep4in",
+-00959                 "ep5in",
+-00960                 "ep6in",
+-00961                 "ep7in",
+-00962                 "ep8in",
+-00963                 "ep9in",
+-00964                 "ep10in",
+-00965                 "ep11in",
+-00966                 "ep12in",
+-00967                 "ep13in",
+-00968                 "ep14in",
+-00969                 "ep15in",
+-00970                 "ep1out",
+-00971                 "ep2out",
+-00972                 "ep3out",
+-00973                 "ep4out",
+-00974                 "ep5out",
+-00975                 "ep6out",
+-00976                 "ep7out",
+-00977                 "ep8out",
+-00978                 "ep9out",
+-00979                 "ep10out",
+-00980                 "ep11out",
+-00981                 "ep12out",
+-00982                 "ep13out",
+-00983                 "ep14out",
+-00984                 "ep15out"
+-00985         };
+-00986 
+-00987         int i;
+-00988         struct usb_ep *ep;
+-00989         int8_t dev_endpoints;
+-00990 
+-00991         DWC_DEBUGPL(DBG_PCDV, "%s\n", __func__);
+-00992 
+-00993         INIT_LIST_HEAD(&d->gadget.ep_list);
+-00994         d->gadget.ep0 = &d->ep0;
+-00995         d->gadget.speed = USB_SPEED_UNKNOWN;
+-00996 
+-00997         INIT_LIST_HEAD(&d->gadget.ep0->ep_list);
+-00998 
+-01002         ep = &d->ep0;
+-01003 
+-01004         /* Init the usb_ep structure. */
+-01005         ep->name = names[0];
+-01006         ep->ops = (struct usb_ep_ops *)&dwc_otg_pcd_ep_ops;
+-01007 
+-01012         ep->maxpacket = MAX_PACKET_SIZE;
+-01013         dwc_otg_pcd_ep_enable(d->pcd, NULL, ep);
+-01014 
+-01015         list_add_tail(&ep->ep_list, &d->gadget.ep_list);
+-01016 
+-01020         dev_endpoints = d->pcd->core_if->dev_if->num_in_eps;
+-01021 
+-01022         for (i = 0; i < dev_endpoints; i++) {
+-01023                 ep = &d->in_ep[i];
+-01024 
+-01025                 /* Init the usb_ep structure. */
+-01026                 ep->name = names[d->pcd->in_ep[i].dwc_ep.num];
+-01027                 ep->ops = (struct usb_ep_ops *)&dwc_otg_pcd_ep_ops;
+-01028 
+-01033                 ep->maxpacket = MAX_PACKET_SIZE;
+-01034                 list_add_tail(&ep->ep_list, &d->gadget.ep_list);
+-01035         }
+-01036 
+-01037         dev_endpoints = d->pcd->core_if->dev_if->num_out_eps;
+-01038 
+-01039         for (i = 0; i < dev_endpoints; i++) {
+-01040                 ep = &d->out_ep[i];
+-01041 
+-01042                 /* Init the usb_ep structure. */
+-01043                 ep->name = names[15 + d->pcd->out_ep[i].dwc_ep.num];
+-01044                 ep->ops = (struct usb_ep_ops *)&dwc_otg_pcd_ep_ops;
+-01045 
+-01050                 ep->maxpacket = MAX_PACKET_SIZE;
+-01051 
+-01052                 list_add_tail(&ep->ep_list, &d->gadget.ep_list);
+-01053         }
+-01054 
+-01055         /* remove ep0 from the list.  There is a ep0 pointer. */
+-01056         list_del_init(&d->ep0.ep_list);
+-01057 
+-01058         d->ep0.maxpacket = MAX_EP0_SIZE;
+-01059 }
+-01060 
+-01067 static void dwc_otg_pcd_gadget_release(struct device *dev)
+-01068 {
+-01069         DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, dev);
+-01070 }
+-01071 
+-01072 static struct gadget_wrapper *alloc_wrapper(
+-01073 #ifdef LM_INTERFACE
+-01074         struct lm_device *_dev
+-01075 #elif  defined(PCI_INTERFACE)
+-01076         struct pci_dev *_dev
+-01077 #endif
+-01078     )
+-01079 {
+-01080         static char pcd_name[] = "dwc_otg_pcd";
+-01081 #ifdef LM_INTERFACE
+-01082         dwc_otg_device_t *otg_dev = lm_get_drvdata(_dev);
+-01083 #elif defined(PCI_INTERFACE)
+-01084         dwc_otg_device_t *otg_dev = pci_get_drvdata(_dev);
+-01085 #endif
+-01086 
+-01087         struct gadget_wrapper *d;
+-01088         int retval;
+-01089 
+-01090         d = DWC_ALLOC(sizeof(*d));
+-01091         if (d == NULL) {
+-01092                 return NULL;
+-01093         }
+-01094 
+-01095         memset(d, 0, sizeof(*d));
+-01096 
+-01097         d->gadget.name = pcd_name;
+-01098         d->pcd = otg_dev->pcd;
+-01099 
+-01100 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30)
+-01101         strcpy(d->gadget.dev.bus_id, "gadget");
+-01102 #else
+-01103         dev_set_name(&d->gadget.dev, "%s", "gadget");
+-01104 #endif
+-01105 
+-01106         d->gadget.dev.parent = &_dev->dev;
+-01107         d->gadget.dev.release = dwc_otg_pcd_gadget_release;
+-01108         d->gadget.ops = &dwc_otg_pcd_ops;
+-01109         d->gadget.is_dualspeed = dwc_otg_pcd_is_dualspeed(otg_dev->pcd);
+-01110         d->gadget.is_otg = dwc_otg_pcd_is_otg(otg_dev->pcd);
+-01111 
+-01112         d->driver = 0;
+-01113         /* Register the gadget device */
+-01114         retval = device_register(&d->gadget.dev);
+-01115         if (retval != 0) {
+-01116                 DWC_ERROR("device_register failed\n");
+-01117                 DWC_FREE(d);
+-01118                 return NULL;
+-01119         }
+-01120 
+-01121         return d;
+-01122 }
+-01123 
+-01124 static void free_wrapper(struct gadget_wrapper *d)
+-01125 {
+-01126         if (d->driver) {
+-01127                 /* should have been done already by driver model core */
+-01128                 DWC_WARN("driver '%s' is still registered\n",
+-01129                          d->driver->driver.name);
+-01130                 usb_gadget_unregister_driver(d->driver);
+-01131         }
+-01132 
+-01133         device_unregister(&d->gadget.dev);
+-01134         DWC_FREE(d);
+-01135 }
+-01136 
+-01141 int pcd_init(
+-01142 #ifdef LM_INTERFACE
+-01143         struct lm_device *_dev
+-01144 #elif  defined(PCI_INTERFACE)
+-01145         struct pci_dev *_dev
+-01146 #endif
+-01147     )
+-01148 {
+-01149 #ifdef LM_INTERFACE
+-01150         dwc_otg_device_t *otg_dev = lm_get_drvdata(_dev);
+-01151 #elif  defined(PCI_INTERFACE)
+-01152         dwc_otg_device_t *otg_dev = pci_get_drvdata(_dev);
+-01153 #endif
+-01154 
+-01155         int retval = 0;
+-01156 
+-01157         DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, _dev);
+-01158 
+-01159         otg_dev->pcd = dwc_otg_pcd_init(otg_dev->core_if);
+-01160 
+-01161         if (!otg_dev->pcd) {
+-01162                 DWC_ERROR("dwc_otg_pcd_init failed\n");
+-01163                 return -ENOMEM;
+-01164         }
+-01165 
+-01166         otg_dev->pcd->otg_dev = otg_dev;
+-01167         gadget_wrapper = alloc_wrapper(_dev);
+-01168 
+-01169         /*
+-01170          * Initialize EP structures
+-01171          */
+-01172         gadget_add_eps(gadget_wrapper);
+-01173         /*
+-01174          * Setup interupt handler
+-01175          */
+-01176         DWC_DEBUGPL(DBG_ANY, "registering handler for irq%d\n", _dev->irq);
+-01177         retval = request_irq(_dev->irq, dwc_otg_pcd_irq,
+-01178                              IRQF_SHARED | IRQF_DISABLED,
+-01179                              gadget_wrapper->gadget.name, otg_dev->pcd);
+-01180         if (retval != 0) {
+-01181                 DWC_ERROR("request of irq%d failed\n", _dev->irq);
+-01182                 free_wrapper(gadget_wrapper);
+-01183                 return -EBUSY;
+-01184         }
+-01185 
+-01186         dwc_otg_pcd_start(gadget_wrapper->pcd, &fops);
+-01187 
+-01188         return retval;
+-01189 }
+-01190 
+-01194 void pcd_remove(
+-01195 #ifdef LM_INTERFACE
+-01196         struct lm_device *_dev
+-01197 #elif  defined(PCI_INTERFACE)
+-01198         struct pci_dev *_dev
+-01199 #endif
+-01200     )
+-01201 {
+-01202 #ifdef LM_INTERFACE
+-01203         dwc_otg_device_t *otg_dev = lm_get_drvdata(_dev);
+-01204 #elif  defined(PCI_INTERFACE)
+-01205         dwc_otg_device_t *otg_dev = pci_get_drvdata(_dev);
+-01206 #endif
+-01207         dwc_otg_pcd_t *pcd = otg_dev->pcd;
+-01208 
+-01209         DWC_DEBUGPL(DBG_PCDV, "%s(%p)\n", __func__, _dev);
+-01210 
+-01211         /*
+-01212          * Free the IRQ
+-01213          */
+-01214         free_irq(_dev->irq, pcd);
+-01215         dwc_otg_pcd_remove(otg_dev->pcd);
+-01216         free_wrapper(gadget_wrapper);
+-01217         otg_dev->pcd = 0;
+-01218 }
+-01219 
+-01231 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,37)
+-01232 int usb_gadget_register_driver(struct usb_gadget_driver *driver)
+-01233 #else
+-01234 int usb_gadget_probe_driver(struct usb_gadget_driver *driver,
+-01235                 int (*bind)(struct usb_gadget *))
+-01236 #endif
+-01237 {
+-01238         int retval;
+-01239 
+-01240         DWC_DEBUGPL(DBG_PCD, "registering gadget driver '%s'\n",
+-01241                     driver->driver.name);
+-01242 
+-01243         if (!driver || driver->speed == USB_SPEED_UNKNOWN ||
+-01244 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,37)
+-01245             !driver->bind ||
+-01246 #else
+-01247                 !bind ||
+-01248 #endif
+-01249             !driver->unbind || !driver->disconnect || !driver->setup) {
+-01250                 DWC_DEBUGPL(DBG_PCDV, "EINVAL\n");
+-01251                 return -EINVAL;
+-01252         }
+-01253         if (gadget_wrapper == 0) {
+-01254                 DWC_DEBUGPL(DBG_PCDV, "ENODEV\n");
+-01255                 return -ENODEV;
+-01256         }
+-01257         if (gadget_wrapper->driver != 0) {
+-01258                 DWC_DEBUGPL(DBG_PCDV, "EBUSY (%p)\n", gadget_wrapper->driver);
+-01259                 return -EBUSY;
+-01260         }
+-01261 
+-01262         /* hook up the driver */
+-01263         gadget_wrapper->driver = driver;
+-01264         gadget_wrapper->gadget.dev.driver = &driver->driver;
+-01265 
+-01266         DWC_DEBUGPL(DBG_PCD, "bind to driver %s\n", driver->driver.name);
+-01267 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,37)
+-01268         retval = driver->bind(&gadget_wrapper->gadget);
+-01269 #else
+-01270         retval = bind(&gadget_wrapper->gadget);
+-01271 #endif
+-01272         if (retval) {
+-01273                 DWC_ERROR("bind to driver %s --> error %d\n",
+-01274                           driver->driver.name, retval);
+-01275                 gadget_wrapper->driver = 0;
+-01276                 gadget_wrapper->gadget.dev.driver = 0;
+-01277                 return retval;
+-01278         }
+-01279         DWC_DEBUGPL(DBG_ANY, "registered gadget driver '%s'\n",
+-01280                     driver->driver.name);
+-01281         return 0;
+-01282 }
+-01283 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,37)
+-01284 EXPORT_SYMBOL(usb_gadget_register_driver);
+-01285 #else
+-01286 EXPORT_SYMBOL(usb_gadget_probe_driver);
+-01287 #endif
+-01288 
+-01294 int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
+-01295 {
+-01296         //DWC_DEBUGPL(DBG_PCDV,"%s(%p)\n", __func__, _driver);
+-01297 
+-01298         if (gadget_wrapper == 0) {
+-01299                 DWC_DEBUGPL(DBG_ANY, "%s Return(%d): s_pcd==0\n", __func__,
+-01300                             -ENODEV);
+-01301                 return -ENODEV;
+-01302         }
+-01303         if (driver == 0 || driver != gadget_wrapper->driver) {
+-01304                 DWC_DEBUGPL(DBG_ANY, "%s Return(%d): driver?\n", __func__,
+-01305                             -EINVAL);
+-01306                 return -EINVAL;
+-01307         }
+-01308 
+-01309         driver->unbind(&gadget_wrapper->gadget);
+-01310         gadget_wrapper->driver = 0;
+-01311 
+-01312         DWC_DEBUGPL(DBG_ANY, "unregistered driver '%s'\n", driver->driver.name);
+-01313         return 0;
+-01314 }
+-01315 
+-01316 EXPORT_SYMBOL(usb_gadget_unregister_driver);
+-01317 
+-01318 #endif /* DWC_HOST_ONLY */
+-
                                                                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__pcd__linux_8c.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/dwc__otg__pcd__linux_8c.html 2013-07-26 19:34:42.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,798 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_pcd_linux.c File Reference +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                dwc_otg_pcd_linux.c File Reference

                                                                                This file implements the Peripheral Controller Driver. More... +-

                                                                                +-#include "dwc_otg_os_dep.h"
                                                                                +-#include "dwc_otg_pcd_if.h"
                                                                                +-#include "dwc_otg_pcd.h"
                                                                                +-#include "dwc_otg_driver.h"
                                                                                +-#include "dwc_otg_dbg.h"
                                                                                +- +-

                                                                                +-Go to the source code of this file. +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-

                                                                                Data Structures

                                                                                struct  gadget_wrapper

                                                                                Functions

                                                                                +-void dump_msg (const u8 *buf, unsigned int length)
                                                                                +-dwc_otg_pcd_ep * ep_from_handle (dwc_otg_pcd_t *pcd, void *handle)
                                                                                 Get the dwc_otg_pcd_ep_t* from usb_ep* pointer - NULL in case if the endpoint is not found.
                                                                                int ep_enable (struct usb_ep *usb_ep, const struct usb_endpoint_descriptor *ep_desc)
                                                                                 This function is called by the Gadget Driver for each EP to be configured for the current configuration (SET_CONFIGURATION).
                                                                                int ep_disable (struct usb_ep *usb_ep)
                                                                                 This function is called when an EP is disabled due to disconnect or change in configuration.
                                                                                usb_request * dwc_otg_pcd_alloc_request (struct usb_ep *ep, gfp_t gfp_flags)
                                                                                 This function allocates a request object to use with the specified endpoint.
                                                                                void dwc_otg_pcd_free_request (struct usb_ep *ep, struct usb_request *req)
                                                                                 This function frees a request object.
                                                                                int ep_queue (struct usb_ep *usb_ep, struct usb_request *usb_req, gfp_t gfp_flags)
                                                                                 This function is used to submit an I/O Request to an EP.
                                                                                +-int ep_dequeue (struct usb_ep *usb_ep, struct usb_request *usb_req)
                                                                                 This function cancels an I/O request from an EP.
                                                                                int ep_halt (struct usb_ep *usb_ep, int value)
                                                                                 usb_ep_set_halt stalls an endpoint.
                                                                                int iso_ep_start (struct usb_ep *usb_ep, struct usb_iso_request *req, gfp_t gfp_flags)
                                                                                 This function is used to submit an ISOC Transfer Request to an EP.
                                                                                +-int iso_ep_stop (struct usb_ep *usb_ep, struct usb_iso_request *req)
                                                                                 This function stops ISO EP Periodic Data Transfer.
                                                                                +-usb_iso_request * alloc_iso_request (struct usb_ep *ep, int packets, gfp_t gfp_flags)
                                                                                +-void free_iso_request (struct usb_ep *ep, struct usb_iso_request *req)
                                                                                +-int get_frame_number (struct usb_gadget *gadget)
                                                                                 Gets the USB Frame number of the last SOF.
                                                                                int wakeup (struct usb_gadget *gadget)
                                                                                 Initiates Session Request Protocol (SRP) to wakeup the host if no session is in progress.
                                                                                +-int _setup (dwc_otg_pcd_t *pcd, uint8_t *bytes)
                                                                                +-int _isoc_complete (dwc_otg_pcd_t *pcd, void *ep_handle, void *req_handle, int proc_buf_num)
                                                                                +-int _complete (dwc_otg_pcd_t *pcd, void *ep_handle, void *req_handle, int32_t status, uint32_t actual)
                                                                                +-int _connect (dwc_otg_pcd_t *pcd, int speed)
                                                                                +-int _disconnect (dwc_otg_pcd_t *pcd)
                                                                                +-int _resume (dwc_otg_pcd_t *pcd)
                                                                                +-int _suspend (dwc_otg_pcd_t *pcd)
                                                                                +-int _hnp_changed (dwc_otg_pcd_t *pcd)
                                                                                 This function updates the otg values in the gadget structure.
                                                                                +-int _reset (dwc_otg_pcd_t *pcd)
                                                                                +-irqreturn_t dwc_otg_pcd_irq (int irq, void *dev)
                                                                                 This function is the top level PCD interrupt handler.
                                                                                void gadget_add_eps (struct gadget_wrapper *d)
                                                                                 This function initialized the usb_ep structures to there default state.
                                                                                void dwc_otg_pcd_gadget_release (struct device *dev)
                                                                                 This function releases the Gadget device.
                                                                                +-gadget_wrapper * alloc_wrapper ()
                                                                                +-void free_wrapper (struct gadget_wrapper *d)
                                                                                +-int pcd_init ()
                                                                                 This function initialized the PCD portion of the driver.
                                                                                +-void pcd_remove ()
                                                                                 Cleanup the PCD.
                                                                                int usb_gadget_probe_driver (struct usb_gadget_driver *driver, int(*bind)(struct usb_gadget *))
                                                                                 This function registers a gadget driver with the PCD.
                                                                                +- EXPORT_SYMBOL (usb_gadget_probe_driver)
                                                                                int usb_gadget_unregister_driver (struct usb_gadget_driver *driver)
                                                                                 This function unregisters a gadget driver.
                                                                                +- EXPORT_SYMBOL (usb_gadget_unregister_driver)

                                                                                Variables

                                                                                +-gadget_wrapper * gadget_wrapper
                                                                                usb_isoc_ep_ops dwc_otg_pcd_ep_ops
                                                                                const struct usb_gadget_ops dwc_otg_pcd_ops
                                                                                const struct dwc_otg_pcd_function_ops fops
                                                                                +-

                                                                                Detailed Description

                                                                                +-This file implements the Peripheral Controller Driver. +-

                                                                                +-The Peripheral Controller Driver (PCD) is responsible for translating requests from the Function Driver into the appropriate actions on the DWC_otg controller. It isolates the Function Driver from the specifics of the controller by providing an API to the Function Driver.

                                                                                +-The Peripheral Controller Driver for Linux will implement the Gadget API, so that the existing Gadget drivers can be used. (Gadget Driver is the Linux terminology for a Function Driver.)

                                                                                +-The Linux Gadget API is defined in the header file <linux/usb_gadget.h>. The USB EP operations API is defined in the structure usb_ep_ops and the USB Controller API is defined in the structure usb_gadget_ops. +-

                                                                                +-Definition in file dwc_otg_pcd_linux.c.

                                                                                Function Documentation

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                int ep_enable ( struct usb_ep *  usb_ep,
                                                                                const struct usb_endpoint_descriptor *  ep_desc
                                                                                )  [static]
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This function is called by the Gadget Driver for each EP to be configured for the current configuration (SET_CONFIGURATION). +-

                                                                                +-This function initializes the dwc_otg_ep_t data structure, and then calls dwc_otg_ep_activate. +-

                                                                                +-Definition at line 121 of file dwc_otg_pcd_linux.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                int ep_disable ( struct usb_ep *  usb_ep  )  [static]
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This function is called when an EP is disabled due to disconnect or change in configuration. +-

                                                                                +-Any pending requests will terminate with a status of -ESHUTDOWN.

                                                                                +-This function modifies the dwc_otg_ep_t data structure for this EP, and then calls dwc_otg_ep_deactivate. +-

                                                                                +-Definition at line 177 of file dwc_otg_pcd_linux.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                struct usb_request* dwc_otg_pcd_alloc_request ( struct usb_ep *  ep,
                                                                                gfp_t  gfp_flags
                                                                                )  [static]
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This function allocates a request object to use with the specified endpoint. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +-
                                                                                ep The endpoint to be used with with the request
                                                                                gfp_flags the GFP_* flags to use.
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 203 of file dwc_otg_pcd_linux.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                void dwc_otg_pcd_free_request ( struct usb_ep *  ep,
                                                                                struct usb_request *  req
                                                                                )  [static]
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This function frees a request object. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +-
                                                                                ep The endpoint associated with the request
                                                                                req The request being freed
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 230 of file dwc_otg_pcd_linux.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                int ep_queue ( struct usb_ep *  usb_ep,
                                                                                struct usb_request *  usb_req,
                                                                                gfp_t  gfp_flags
                                                                                )  [static]
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This function is used to submit an I/O Request to an EP. +-

                                                                                +-

                                                                                  +-
                                                                                • When the request completes the request's completion callback is called to return the request to the driver.
                                                                                • An EP, except control EPs, may have multiple requests pending.
                                                                                • Once submitted the request cannot be examined or modified.
                                                                                • Each request is turned into one or more packets.
                                                                                • A BULK EP can queue any amount of data; the transfer is packetized.
                                                                                • Zero length Packets are specified with the request 'zero' flag.
                                                                                +- +-

                                                                                +-Definition at line 317 of file dwc_otg_pcd_linux.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                int ep_halt ( struct usb_ep *  usb_ep,
                                                                                int  value
                                                                                )  [static]
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-usb_ep_set_halt stalls an endpoint. +-

                                                                                +-usb_ep_clear_halt clears an endpoint halt and resets its data toggle.

                                                                                +-Both of these functions are implemented with the same underlying function. The behavior depends on the value argument.

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +-
                                                                                [in] usb_ep the Endpoint to halt or clear halt.
                                                                                [in] value 
                                                                                  +-
                                                                                • 0 means clear_halt.
                                                                                • 1 means set_halt,
                                                                                • 2 means clear stall lock flag.
                                                                                • 3 means set stall lock flag.
                                                                                +-
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 430 of file dwc_otg_pcd_linux.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                int iso_ep_start ( struct usb_ep *  usb_ep,
                                                                                struct usb_iso_request *  req,
                                                                                gfp_t  gfp_flags
                                                                                )  [static]
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This function is used to submit an ISOC Transfer Request to an EP. +-

                                                                                +-

                                                                                  +-
                                                                                • Every time a sync period completes the request's completion callback is called to provide data to the gadget driver.
                                                                                • Once submitted the request cannot be modified.
                                                                                • Each request is turned into periodic data packets untill ISO Transfer is stopped..
                                                                                +- +-

                                                                                +-Definition at line 461 of file dwc_otg_pcd_linux.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                int wakeup ( struct usb_gadget *  gadget  )  [static]
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Initiates Session Request Protocol (SRP) to wakeup the host if no session is in progress. +-

                                                                                +-If a session is already in progress, but the device is suspended, remote wakeup signaling is started. +-

                                                                                +-Definition at line 646 of file dwc_otg_pcd_linux.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                void gadget_add_eps ( struct gadget_wrapper *  d  ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This function initialized the usb_ep structures to there default state. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +-
                                                                                d Pointer on gadget_wrapper.
                                                                                +-
                                                                                +-

                                                                                +-Initialize the EP0 structure.

                                                                                +-

                                                                                Todo:
                                                                                NGS: What should the max packet size be set to here? Before EP type is set?

                                                                                +-NGS: What should the max packet size be set to here? Before EP type is set?

                                                                                +-NGS: What should the max packet size be set to here? Before EP type is set?

                                                                                +-

                                                                                +-Initialize the EP structures. +-

                                                                                +-Definition at line 950 of file dwc_otg_pcd_linux.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                void dwc_otg_pcd_gadget_release ( struct device *  dev  )  [static]
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This function releases the Gadget device. +-

                                                                                +-required by device_unregister().

                                                                                +-

                                                                                Todo:
                                                                                Should this do something? Should it free the PCD?
                                                                                +- +-

                                                                                +-Definition at line 1067 of file dwc_otg_pcd_linux.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                int usb_gadget_probe_driver ( struct usb_gadget_driver *  driver,
                                                                                int(*)(struct usb_gadget *)  bind
                                                                                ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This function registers a gadget driver with the PCD. +-

                                                                                +-When a driver is successfully registered, it will receive control requests including set_configuration(), which enables non-control requests. then usb traffic follows until a disconnect is reported. then a host may connect again, or the driver might get unbound.

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +-
                                                                                driver The driver being registered
                                                                                bind The bind function of gadget driver
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 1234 of file dwc_otg_pcd_linux.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +- +- +- +- +- +-
                                                                                int usb_gadget_unregister_driver ( struct usb_gadget_driver *  driver  ) 
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This function unregisters a gadget driver. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +-
                                                                                driver The driver being unregistered
                                                                                +-
                                                                                +- +-

                                                                                +-Definition at line 1294 of file dwc_otg_pcd_linux.c.

                                                                                +-

                                                                                Variable Documentation

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                struct usb_isoc_ep_ops dwc_otg_pcd_ep_ops [static]
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Initial value:

                                                                                 {
+-        .ep_ops = {
+-                   .enable = ep_enable,
+-                   .disable = ep_disable,
+-
+-                   .alloc_request = dwc_otg_pcd_alloc_request,
+-                   .free_request = dwc_otg_pcd_free_request,
+-
+-
+-
+-
+-
+-
+-                   .queue = ep_queue,
+-                   .dequeue = ep_dequeue,
+-
+-                   .set_halt = ep_halt,
+-                   .fifo_status = 0,
+-                   .fifo_flush = 0,
+-                   },
+-        .iso_ep_start = iso_ep_start,
+-        .iso_ep_stop = iso_ep_stop,
+-        .alloc_iso_request = alloc_iso_request,
+-        .free_iso_request = free_iso_request,
+-}
+-
                                                                                +-

                                                                                +-Definition at line 546 of file dwc_otg_pcd_linux.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                const struct usb_gadget_ops dwc_otg_pcd_ops [static]
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Initial value:

                                                                                 {
+-        .get_frame = get_frame_number,
+-        .wakeup = wakeup,
+-
+-
+-
+-        
+-}
+-
                                                                                +-

                                                                                +-Definition at line 661 of file dwc_otg_pcd_linux.c.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                const struct dwc_otg_pcd_function_ops fops [static]
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Initial value:

                                                                                 {
+-        .complete = _complete,
+-
+-        .isoc_complete = _isoc_complete,
+-
+-        .setup = _setup,
+-        .disconnect = _disconnect,
+-        .connect = _connect,
+-        .resume = _resume,
+-        .suspend = _suspend,
+-        .hnp_changed = _hnp_changed,
+-        .reset = _reset,
+-
+-
+-
+-
+-
+-
+-}
+-
                                                                                +-

                                                                                +-Definition at line 909 of file dwc_otg_pcd_linux.c.

                                                                                +-

                                                                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__regs_8h-source.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/dwc__otg__regs_8h-source.html 2013-07-26 19:34:42.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,1382 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_regs.h Source File +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                dwc_otg_regs.h

                                                                                Go to the documentation of this file.
                                                                                00001 /* ==========================================================================
+-00002  * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_regs.h $
+-00003  * $Revision: #97 $
+-00004  * $Date: 2011/10/24 $
+-00005  * $Change: 1871160 $
+-00006  *
+-00007  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
+-00008  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
+-00009  * otherwise expressly agreed to in writing between Synopsys and you.
+-00010  *
+-00011  * The Software IS NOT an item of Licensed Software or Licensed Product under
+-00012  * any End User Software License Agreement or Agreement for Licensed Product
+-00013  * with Synopsys or any supplement thereto. You are permitted to use and
+-00014  * redistribute this Software in source and binary forms, with or without
+-00015  * modification, provided that redistributions of source code must retain this
+-00016  * notice. You may not view, use, disclose, copy or distribute this file or
+-00017  * any information contained herein except pursuant to this license grant from
+-00018  * Synopsys. If you do not agree with this notice, including the disclaimer
+-00019  * below, then you are not authorized to use the Software.
+-00020  *
+-00021  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
+-00022  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+-00023  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+-00024  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
+-00025  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+-00026  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+-00027  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+-00028  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+-00029  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+-00030  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+-00031  * DAMAGE.
+-00032  * ========================================================================== */
+-00033 
+-00034 #ifndef __DWC_OTG_REGS_H__
+-00035 #define __DWC_OTG_REGS_H__
+-00036 
+-00037 #include "dwc_otg_core_if.h"
+-00038 
+-00066 /****************************************************************************/
+-00071 typedef struct dwc_otg_core_global_regs {
+-00073         volatile uint32_t gotgctl;
+-00075         volatile uint32_t gotgint;
+-00077         volatile uint32_t gahbcfg;
+-00078 
+-00079 #define DWC_GLBINTRMASK         0x0001
+-00080 #define DWC_DMAENABLE           0x0020
+-00081 #define DWC_NPTXEMPTYLVL_EMPTY  0x0080
+-00082 #define DWC_NPTXEMPTYLVL_HALFEMPTY      0x0000
+-00083 #define DWC_PTXEMPTYLVL_EMPTY   0x0100
+-00084 #define DWC_PTXEMPTYLVL_HALFEMPTY       0x0000
+-00085 
+-00087         volatile uint32_t gusbcfg;
+-00089         volatile uint32_t grstctl;
+-00091         volatile uint32_t gintsts;
+-00093         volatile uint32_t gintmsk;
+-00095         volatile uint32_t grxstsr;
+-00097         volatile uint32_t grxstsp;
+-00099         volatile uint32_t grxfsiz;
+-00101         volatile uint32_t gnptxfsiz;
+-00104         volatile uint32_t gnptxsts;
+-00106         volatile uint32_t gi2cctl;
+-00108         volatile uint32_t gpvndctl;
+-00110         volatile uint32_t ggpio;
+-00112         volatile uint32_t guid;
+-00114         volatile uint32_t gsnpsid;
+-00116         volatile uint32_t ghwcfg1;
+-00118         volatile uint32_t ghwcfg2;
+-00119 #define DWC_SLAVE_ONLY_ARCH 0
+-00120 #define DWC_EXT_DMA_ARCH 1
+-00121 #define DWC_INT_DMA_ARCH 2
+-00122 
+-00123 #define DWC_MODE_HNP_SRP_CAPABLE        0
+-00124 #define DWC_MODE_SRP_ONLY_CAPABLE       1
+-00125 #define DWC_MODE_NO_HNP_SRP_CAPABLE             2
+-00126 #define DWC_MODE_SRP_CAPABLE_DEVICE             3
+-00127 #define DWC_MODE_NO_SRP_CAPABLE_DEVICE  4
+-00128 #define DWC_MODE_SRP_CAPABLE_HOST       5
+-00129 #define DWC_MODE_NO_SRP_CAPABLE_HOST    6
+-00130 
+-00132         volatile uint32_t ghwcfg3;
+-00134         volatile uint32_t ghwcfg4;
+-00136         volatile uint32_t glpmcfg;
+-00138         volatile uint32_t gpwrdn;
+-00140         volatile uint32_t gdfifocfg;
+-00142         volatile uint32_t adpctl;
+-00144         volatile uint32_t reserved39[39];
+-00146         volatile uint32_t hptxfsiz;
+-00150         volatile uint32_t dtxfsiz[15];
+-00151 } dwc_otg_core_global_regs_t;
+-00152 
+-00158 typedef union gotgctl_data {
+-00160         uint32_t d32;
+-00162         struct {
+-00163                 unsigned sesreqscs:1;
+-00164                 unsigned sesreq:1;
+-00165                 unsigned vbvalidoven:1;
+-00166                 unsigned vbvalidovval:1;
+-00167                 unsigned avalidoven:1;
+-00168                 unsigned avalidovval:1;
+-00169                 unsigned bvalidoven:1;
+-00170                 unsigned bvalidovval:1;
+-00171                 unsigned hstnegscs:1;
+-00172                 unsigned hnpreq:1;
+-00173                 unsigned hstsethnpen:1;
+-00174                 unsigned devhnpen:1;
+-00175                 unsigned reserved12_15:4;
+-00176                 unsigned conidsts:1;
+-00177                 unsigned dbnctime:1;
+-00178                 unsigned asesvld:1;
+-00179                 unsigned bsesvld:1;
+-00180                 unsigned otgver:1;
+-00181                 unsigned reserved1:1;
+-00182                 unsigned multvalidbc:5;
+-00183                 unsigned chirpen:1;
+-00184                 unsigned reserved28_31:4;
+-00185         } b;
+-00186 } gotgctl_data_t;
+-00187 
+-00193 typedef union gotgint_data {
+-00195         uint32_t d32;
+-00197         struct {
+-00199                 unsigned reserved0_1:2;
+-00200 
+-00202                 unsigned sesenddet:1;
+-00203 
+-00204                 unsigned reserved3_7:5;
+-00205 
+-00207                 unsigned sesreqsucstschng:1;
+-00209                 unsigned hstnegsucstschng:1;
+-00210 
+-00211                 unsigned reserved10_16:7;
+-00212 
+-00214                 unsigned hstnegdet:1;
+-00216                 unsigned adevtoutchng:1;
+-00218                 unsigned debdone:1;
+-00220                 unsigned mvic:1;
+-00221 
+-00222                 unsigned reserved31_21:11;
+-00223 
+-00224         } b;
+-00225 } gotgint_data_t;
+-00226 
+-00232 typedef union gahbcfg_data {
+-00234         uint32_t d32;
+-00236         struct {
+-00237                 unsigned glblintrmsk:1;
+-00238 #define DWC_GAHBCFG_GLBINT_ENABLE               1
+-00239 
+-00240                 unsigned hburstlen:4;
+-00241 #define DWC_GAHBCFG_INT_DMA_BURST_SINGLE        0
+-00242 #define DWC_GAHBCFG_INT_DMA_BURST_INCR          1
+-00243 #define DWC_GAHBCFG_INT_DMA_BURST_INCR4         3
+-00244 #define DWC_GAHBCFG_INT_DMA_BURST_INCR8         5
+-00245 #define DWC_GAHBCFG_INT_DMA_BURST_INCR16        7
+-00246 
+-00247                 unsigned dmaenable:1;
+-00248 #define DWC_GAHBCFG_DMAENABLE                   1
+-00249                 unsigned reserved:1;
+-00250                 unsigned nptxfemplvl_txfemplvl:1;
+-00251                 unsigned ptxfemplvl:1;
+-00252 #define DWC_GAHBCFG_TXFEMPTYLVL_EMPTY           1
+-00253 #define DWC_GAHBCFG_TXFEMPTYLVL_HALFEMPTY       0
+-00254                 unsigned reserved9_20:12;
+-00255                 unsigned remmemsupp:1;
+-00256                 unsigned notialldmawrit:1;
+-00257                 unsigned ahbsingle:1;
+-00258                 unsigned reserved24_31:8;
+-00259         } b;
+-00260 } gahbcfg_data_t;
+-00261 
+-00267 typedef union gusbcfg_data {
+-00269         uint32_t d32;
+-00271         struct {
+-00272                 unsigned toutcal:3;
+-00273                 unsigned phyif:1;
+-00274                 unsigned ulpi_utmi_sel:1;
+-00275                 unsigned fsintf:1;
+-00276                 unsigned physel:1;
+-00277                 unsigned ddrsel:1;
+-00278                 unsigned srpcap:1;
+-00279                 unsigned hnpcap:1;
+-00280                 unsigned usbtrdtim:4;
+-00281                 unsigned reserved1:1;
+-00282                 unsigned phylpwrclksel:1;
+-00283                 unsigned otgutmifssel:1;
+-00284                 unsigned ulpi_fsls:1;
+-00285                 unsigned ulpi_auto_res:1;
+-00286                 unsigned ulpi_clk_sus_m:1;
+-00287                 unsigned ulpi_ext_vbus_drv:1;
+-00288                 unsigned ulpi_int_vbus_indicator:1;
+-00289                 unsigned term_sel_dl_pulse:1;
+-00290                 unsigned indicator_complement:1;
+-00291                 unsigned indicator_pass_through:1;
+-00292                 unsigned ulpi_int_prot_dis:1;
+-00293                 unsigned ic_usb_cap:1;
+-00294                 unsigned ic_traffic_pull_remove:1;
+-00295                 unsigned tx_end_delay:1;
+-00296                 unsigned force_host_mode:1;
+-00297                 unsigned force_dev_mode:1;
+-00298                 unsigned reserved31:1;
+-00299         } b;
+-00300 } gusbcfg_data_t;
+-00301 
+-00307 typedef union grstctl_data {
+-00309         uint32_t d32;
+-00311         struct {
+-00347                 unsigned csftrst:1;
+-00354                 unsigned hsftrst:1;
+-00363                 unsigned hstfrm:1;
+-00367                 unsigned intknqflsh:1;
+-00382                 unsigned rxfflsh:1;
+-00397                 unsigned txfflsh:1;
+-00398 
+-00414                 unsigned txfnum:5;
+-00416                 unsigned reserved11_29:19;
+-00419                 unsigned dmareq:1;
+-00422                 unsigned ahbidle:1;
+-00423         } b;
+-00424 } grstctl_t;
+-00425 
+-00431 typedef union gintmsk_data {
+-00433         uint32_t d32;
+-00435         struct {
+-00436                 unsigned reserved0:1;
+-00437                 unsigned modemismatch:1;
+-00438                 unsigned otgintr:1;
+-00439                 unsigned sofintr:1;
+-00440                 unsigned rxstsqlvl:1;
+-00441                 unsigned nptxfempty:1;
+-00442                 unsigned ginnakeff:1;
+-00443                 unsigned goutnakeff:1;
+-00444                 unsigned ulpickint:1;
+-00445                 unsigned i2cintr:1;
+-00446                 unsigned erlysuspend:1;
+-00447                 unsigned usbsuspend:1;
+-00448                 unsigned usbreset:1;
+-00449                 unsigned enumdone:1;
+-00450                 unsigned isooutdrop:1;
+-00451                 unsigned eopframe:1;
+-00452                 unsigned restoredone:1;
+-00453                 unsigned epmismatch:1;
+-00454                 unsigned inepintr:1;
+-00455                 unsigned outepintr:1;
+-00456                 unsigned incomplisoin:1;
+-00457                 unsigned incomplisoout:1;
+-00458                 unsigned fetsusp:1;
+-00459                 unsigned resetdet:1;
+-00460                 unsigned portintr:1;
+-00461                 unsigned hcintr:1;
+-00462                 unsigned ptxfempty:1;
+-00463                 unsigned lpmtranrcvd:1;
+-00464                 unsigned conidstschng:1;
+-00465                 unsigned disconnect:1;
+-00466                 unsigned sessreqintr:1;
+-00467                 unsigned wkupintr:1;
+-00468         } b;
+-00469 } gintmsk_data_t;
+-00475 typedef union gintsts_data {
+-00477         uint32_t d32;
+-00478 #define DWC_SOF_INTR_MASK 0x0008
+-00479 
+-00480         struct {
+-00481 #define DWC_HOST_MODE 1
+-00482                 unsigned curmode:1;
+-00483                 unsigned modemismatch:1;
+-00484                 unsigned otgintr:1;
+-00485                 unsigned sofintr:1;
+-00486                 unsigned rxstsqlvl:1;
+-00487                 unsigned nptxfempty:1;
+-00488                 unsigned ginnakeff:1;
+-00489                 unsigned goutnakeff:1;
+-00490                 unsigned ulpickint:1;
+-00491                 unsigned i2cintr:1;
+-00492                 unsigned erlysuspend:1;
+-00493                 unsigned usbsuspend:1;
+-00494                 unsigned usbreset:1;
+-00495                 unsigned enumdone:1;
+-00496                 unsigned isooutdrop:1;
+-00497                 unsigned eopframe:1;
+-00498                 unsigned restoredone:1;
+-00499                 unsigned epmismatch:1;
+-00500                 unsigned inepint:1;
+-00501                 unsigned outepintr:1;
+-00502                 unsigned incomplisoin:1;
+-00503                 unsigned incomplisoout:1;
+-00504                 unsigned fetsusp:1;
+-00505                 unsigned resetdet:1;
+-00506                 unsigned portintr:1;
+-00507                 unsigned hcintr:1;
+-00508                 unsigned ptxfempty:1;
+-00509                 unsigned lpmtranrcvd:1;
+-00510                 unsigned conidstschng:1;
+-00511                 unsigned disconnect:1;
+-00512                 unsigned sessreqintr:1;
+-00513                 unsigned wkupintr:1;
+-00514         } b;
+-00515 } gintsts_data_t;
+-00516 
+-00522 typedef union device_grxsts_data {
+-00524         uint32_t d32;
+-00526         struct {
+-00527                 unsigned epnum:4;
+-00528                 unsigned bcnt:11;
+-00529                 unsigned dpid:2;
+-00530 
+-00531 #define DWC_STS_DATA_UPDT               0x2     // OUT Data Packet
+-00532 #define DWC_STS_XFER_COMP               0x3     // OUT Data Transfer Complete
+-00533 
+-00534 #define DWC_DSTS_GOUT_NAK               0x1     // Global OUT NAK
+-00535 #define DWC_DSTS_SETUP_COMP             0x4     // Setup Phase Complete
+-00536 #define DWC_DSTS_SETUP_UPDT 0x6 // SETUP Packet
+-00537                 unsigned pktsts:4;
+-00538                 unsigned fn:4;
+-00539                 unsigned reserved25_31:7;
+-00540         } b;
+-00541 } device_grxsts_data_t;
+-00542 
+-00548 typedef union host_grxsts_data {
+-00550         uint32_t d32;
+-00552         struct {
+-00553                 unsigned chnum:4;
+-00554                 unsigned bcnt:11;
+-00555                 unsigned dpid:2;
+-00556 
+-00557                 unsigned pktsts:4;
+-00558 #define DWC_GRXSTS_PKTSTS_IN                      0x2
+-00559 #define DWC_GRXSTS_PKTSTS_IN_XFER_COMP    0x3
+-00560 #define DWC_GRXSTS_PKTSTS_DATA_TOGGLE_ERR 0x5
+-00561 #define DWC_GRXSTS_PKTSTS_CH_HALTED               0x7
+-00562 
+-00563                 unsigned reserved21_31:11;
+-00564         } b;
+-00565 } host_grxsts_data_t;
+-00566 
+-00572 typedef union fifosize_data {
+-00574         uint32_t d32;
+-00576         struct {
+-00577                 unsigned startaddr:16;
+-00578                 unsigned depth:16;
+-00579         } b;
+-00580 } fifosize_data_t;
+-00581 
+-00588 typedef union gnptxsts_data {
+-00590         uint32_t d32;
+-00592         struct {
+-00593                 unsigned nptxfspcavail:16;
+-00594                 unsigned nptxqspcavail:8;
+-00605                 unsigned nptxqtop_terminate:1;
+-00606                 unsigned nptxqtop_token:2;
+-00607                 unsigned nptxqtop_chnep:4;
+-00608                 unsigned reserved:1;
+-00609         } b;
+-00610 } gnptxsts_data_t;
+-00611 
+-00618 typedef union dtxfsts_data {
+-00620         uint32_t d32;
+-00622         struct {
+-00623                 unsigned txfspcavail:16;
+-00624                 unsigned reserved:16;
+-00625         } b;
+-00626 } dtxfsts_data_t;
+-00627 
+-00633 typedef union gi2cctl_data {
+-00635         uint32_t d32;
+-00637         struct {
+-00638                 unsigned rwdata:8;
+-00639                 unsigned regaddr:8;
+-00640                 unsigned addr:7;
+-00641                 unsigned i2cen:1;
+-00642                 unsigned ack:1;
+-00643                 unsigned i2csuspctl:1;
+-00644                 unsigned i2cdevaddr:2;
+-00645                 unsigned i2cdatse0:1;
+-00646                 unsigned reserved:1;
+-00647                 unsigned rw:1;
+-00648                 unsigned bsydne:1;
+-00649         } b;
+-00650 } gi2cctl_data_t;
+-00651 
+-00657 typedef union gpvndctl_data {
+-00659         uint32_t d32;
+-00661         struct {
+-00662                 unsigned regdata:8;
+-00663                 unsigned vctrl:8;
+-00664                 unsigned regaddr16_21:6;
+-00665                 unsigned regwr:1;
+-00666                 unsigned reserved23_24:2;
+-00667                 unsigned newregreq:1;
+-00668                 unsigned vstsbsy:1;
+-00669                 unsigned vstsdone:1;
+-00670                 unsigned reserved28_30:3;
+-00671                 unsigned disulpidrvr:1;
+-00672         } b;
+-00673 } gpvndctl_data_t;
+-00674 
+-00681 typedef union ggpio_data {
+-00683         uint32_t d32;
+-00685         struct {
+-00686                 unsigned gpi:16;
+-00687                 unsigned gpo:16;
+-00688         } b;
+-00689 } ggpio_data_t;
+-00690 
+-00696 typedef union guid_data {
+-00698         uint32_t d32;
+-00700         struct {
+-00701                 unsigned rwdata:32;
+-00702         } b;
+-00703 } guid_data_t;
+-00704 
+-00710 typedef union gsnpsid_data {
+-00712         uint32_t d32;
+-00714         struct {
+-00715                 unsigned rwdata:32;
+-00716         } b;
+-00717 } gsnpsid_data_t;
+-00718 
+-00724 typedef union hwcfg1_data {
+-00726         uint32_t d32;
+-00728         struct {
+-00729                 unsigned ep_dir0:2;
+-00730                 unsigned ep_dir1:2;
+-00731                 unsigned ep_dir2:2;
+-00732                 unsigned ep_dir3:2;
+-00733                 unsigned ep_dir4:2;
+-00734                 unsigned ep_dir5:2;
+-00735                 unsigned ep_dir6:2;
+-00736                 unsigned ep_dir7:2;
+-00737                 unsigned ep_dir8:2;
+-00738                 unsigned ep_dir9:2;
+-00739                 unsigned ep_dir10:2;
+-00740                 unsigned ep_dir11:2;
+-00741                 unsigned ep_dir12:2;
+-00742                 unsigned ep_dir13:2;
+-00743                 unsigned ep_dir14:2;
+-00744                 unsigned ep_dir15:2;
+-00745         } b;
+-00746 } hwcfg1_data_t;
+-00747 
+-00753 typedef union hwcfg2_data {
+-00755         uint32_t d32;
+-00757         struct {
+-00758                 /* GHWCFG2 */
+-00759                 unsigned op_mode:3;
+-00760 #define DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG 0
+-00761 #define DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG 1
+-00762 #define DWC_HWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE_OTG 2
+-00763 #define DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE 3
+-00764 #define DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE 4
+-00765 #define DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST 5
+-00766 #define DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST 6
+-00767 
+-00768                 unsigned architecture:2;
+-00769                 unsigned point2point:1;
+-00770                 unsigned hs_phy_type:2;
+-00771 #define DWC_HWCFG2_HS_PHY_TYPE_NOT_SUPPORTED 0
+-00772 #define DWC_HWCFG2_HS_PHY_TYPE_UTMI 1
+-00773 #define DWC_HWCFG2_HS_PHY_TYPE_ULPI 2
+-00774 #define DWC_HWCFG2_HS_PHY_TYPE_UTMI_ULPI 3
+-00775 
+-00776                 unsigned fs_phy_type:2;
+-00777                 unsigned num_dev_ep:4;
+-00778                 unsigned num_host_chan:4;
+-00779                 unsigned perio_ep_supported:1;
+-00780                 unsigned dynamic_fifo:1;
+-00781                 unsigned multi_proc_int:1;
+-00782                 unsigned reserved21:1;
+-00783                 unsigned nonperio_tx_q_depth:2;
+-00784                 unsigned host_perio_tx_q_depth:2;
+-00785                 unsigned dev_token_q_depth:5;
+-00786                 unsigned otg_enable_ic_usb:1;
+-00787         } b;
+-00788 } hwcfg2_data_t;
+-00789 
+-00795 typedef union hwcfg3_data {
+-00797         uint32_t d32;
+-00799         struct {
+-00800                 /* GHWCFG3 */
+-00801                 unsigned xfer_size_cntr_width:4;
+-00802                 unsigned packet_size_cntr_width:3;
+-00803                 unsigned otg_func:1;
+-00804                 unsigned i2c:1;
+-00805                 unsigned vendor_ctrl_if:1;
+-00806                 unsigned optional_features:1;
+-00807                 unsigned synch_reset_type:1;
+-00808                 unsigned adp_supp:1;
+-00809                 unsigned otg_enable_hsic:1;
+-00810                 unsigned bc_support:1;
+-00811                 unsigned otg_lpm_en:1;
+-00812                 unsigned dfifo_depth:16;
+-00813         } b;
+-00814 } hwcfg3_data_t;
+-00815 
+-00821 typedef union hwcfg4_data {
+-00823         uint32_t d32;
+-00825         struct {
+-00826                 unsigned num_dev_perio_in_ep:4;
+-00827                 unsigned power_optimiz:1;
+-00828                 unsigned min_ahb_freq:1;
+-00829                 unsigned part_power_down:1;
+-00830                 unsigned reserved:7;
+-00831                 unsigned utmi_phy_data_width:2;
+-00832                 unsigned num_dev_mode_ctrl_ep:4;
+-00833                 unsigned iddig_filt_en:1;
+-00834                 unsigned vbus_valid_filt_en:1;
+-00835                 unsigned a_valid_filt_en:1;
+-00836                 unsigned b_valid_filt_en:1;
+-00837                 unsigned session_end_filt_en:1;
+-00838                 unsigned ded_fifo_en:1;
+-00839                 unsigned num_in_eps:4;
+-00840                 unsigned desc_dma:1;
+-00841                 unsigned desc_dma_dyn:1;
+-00842         } b;
+-00843 } hwcfg4_data_t;
+-00844 
+-00850 typedef union glpmctl_data {
+-00852         uint32_t d32;
+-00854         struct {
+-00859                 unsigned lpm_cap_en:1;
+-00864                 unsigned appl_resp:1;
+-00873                 unsigned hird:4;
+-00882                 unsigned rem_wkup_en:1;
+-00887                 unsigned en_utmi_sleep:1;
+-00890                 unsigned hird_thres:5;
+-00901                 unsigned lpm_resp:2;
+-00906                 unsigned prt_sleep_sts:1;
+-00911                 unsigned sleep_state_resumeok:1;
+-00917                 unsigned lpm_chan_index:4;
+-00922                 unsigned retry_count:3;
+-00928                 unsigned send_lpm:1;
+-00933                 unsigned retry_count_sts:3;
+-00934                 unsigned reserved28_29:2;
+-00942                 unsigned hsic_connect:1;
+-00946                 unsigned inv_sel_hsic:1;
+-00947         } b;
+-00948 } glpmcfg_data_t;
+-00949 
+-00955 typedef union adpctl_data {
+-00957         uint32_t d32;
+-00959         struct {
+-00968                 unsigned prb_dschg:2;
+-00979                 unsigned prb_delta:2;
+-00987                 unsigned prb_per:2;
+-00997                 unsigned rtim:11;
+-01002                 unsigned enaprb:1;
+-01007                 unsigned enasns:1;
+-01012                 unsigned adpres:1;
+-01018                 unsigned adpen:1;
+-01024                 unsigned adp_prb_int:1;
+-01031                 unsigned adp_sns_int:1;
+-01040                 unsigned adp_tmout_int:1;
+-01045                 unsigned adp_prb_int_msk:1;
+-01050                 unsigned adp_sns_int_msk:1;
+-01055                 unsigned adp_tmout_int_msk:1;
+-01062                 unsigned ar:2;
+-01064                 unsigned reserved29_31:3;
+-01065         } b;
+-01066 } adpctl_data_t;
+-01067 
+-01069 // Device Registers
+-01079 typedef struct dwc_otg_dev_global_regs {
+-01081         volatile uint32_t dcfg;
+-01083         volatile uint32_t dctl;
+-01085         volatile uint32_t dsts;
+-01087         uint32_t unused;
+-01090         volatile uint32_t diepmsk;
+-01093         volatile uint32_t doepmsk;
+-01095         volatile uint32_t daint;
+-01098         volatile uint32_t daintmsk;
+-01101         volatile uint32_t dtknqr1;
+-01104         volatile uint32_t dtknqr2;
+-01106         volatile uint32_t dvbusdis;
+-01108         volatile uint32_t dvbuspulse;
+-01112         volatile uint32_t dtknqr3_dthrctl;
+-01116         volatile uint32_t dtknqr4_fifoemptymsk;
+-01119         volatile uint32_t deachint;
+-01122         volatile uint32_t deachintmsk;
+-01125         volatile uint32_t diepeachintmsk[MAX_EPS_CHANNELS];
+-01128         volatile uint32_t doepeachintmsk[MAX_EPS_CHANNELS];
+-01129 } dwc_otg_device_global_regs_t;
+-01130 
+-01137 typedef union dcfg_data {
+-01139         uint32_t d32;
+-01141         struct {
+-01143                 unsigned devspd:2;
+-01145                 unsigned nzstsouthshk:1;
+-01146 #define DWC_DCFG_SEND_STALL 1
+-01147 
+-01148                 unsigned ena32khzs:1;
+-01150                 unsigned devaddr:7;
+-01152                 unsigned perfrint:2;
+-01153 #define DWC_DCFG_FRAME_INTERVAL_80 0
+-01154 #define DWC_DCFG_FRAME_INTERVAL_85 1
+-01155 #define DWC_DCFG_FRAME_INTERVAL_90 2
+-01156 #define DWC_DCFG_FRAME_INTERVAL_95 3
+-01157                 
+-01159                 unsigned endevoutnak:1;
+-01160 
+-01161                 unsigned reserved14_17:4;
+-01163                 unsigned epmscnt:5;
+-01165                 unsigned descdma:1;
+-01166                 unsigned perschintvl:2;
+-01167                 unsigned resvalid:6;
+-01168         } b;
+-01169 } dcfg_data_t;
+-01170 
+-01176 typedef union dctl_data {
+-01178         uint32_t d32;
+-01180         struct {
+-01182                 unsigned rmtwkupsig:1;
+-01184                 unsigned sftdiscon:1;
+-01186                 unsigned gnpinnaksts:1;
+-01188                 unsigned goutnaksts:1;
+-01190                 unsigned tstctl:3;
+-01192                 unsigned sgnpinnak:1;
+-01194                 unsigned cgnpinnak:1;
+-01196                 unsigned sgoutnak:1;
+-01198                 unsigned cgoutnak:1;
+-01200                 unsigned pwronprgdone:1;
+-01202                 unsigned reserved:1;
+-01204                 unsigned gmc:2;
+-01206                 unsigned ifrmnum:1;
+-01208                 unsigned nakonbble:1;
+-01210                 unsigned encontonbna:1;
+-01211 
+-01212                 unsigned reserved18_31:14;
+-01213         } b;
+-01214 } dctl_data_t;
+-01215 
+-01221 typedef union dsts_data {
+-01223         uint32_t d32;
+-01225         struct {
+-01227                 unsigned suspsts:1;
+-01229                 unsigned enumspd:2;
+-01230 #define DWC_DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ 0
+-01231 #define DWC_DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ 1
+-01232 #define DWC_DSTS_ENUMSPD_LS_PHY_6MHZ               2
+-01233 #define DWC_DSTS_ENUMSPD_FS_PHY_48MHZ              3
+-01234 
+-01235                 unsigned errticerr:1;
+-01236                 unsigned reserved4_7:4;
+-01238                 unsigned soffn:14;
+-01239                 unsigned reserved22_31:10;
+-01240         } b;
+-01241 } dsts_data_t;
+-01242 
+-01250 typedef union diepint_data {
+-01252         uint32_t d32;
+-01254         struct {
+-01256                 unsigned xfercompl:1;
+-01258                 unsigned epdisabled:1;
+-01260                 unsigned ahberr:1;
+-01262                 unsigned timeout:1;
+-01264                 unsigned intktxfemp:1;
+-01266                 unsigned intknepmis:1;
+-01268                 unsigned inepnakeff:1;
+-01270                 unsigned emptyintr:1;
+-01271 
+-01272                 unsigned txfifoundrn:1;
+-01273 
+-01275                 unsigned bna:1;
+-01276 
+-01277                 unsigned reserved10_12:3;
+-01279                 unsigned nak:1;
+-01280 
+-01281                 unsigned reserved14_31:18;
+-01282         } b;
+-01283 } diepint_data_t;
+-01284 
+-01289 typedef union diepint_data diepmsk_data_t;
+-01290 
+-01298 typedef union doepint_data {
+-01300         uint32_t d32;
+-01302         struct {
+-01304                 unsigned xfercompl:1;
+-01306                 unsigned epdisabled:1;
+-01308                 unsigned ahberr:1;
+-01310                 unsigned setup:1;
+-01312                 unsigned outtknepdis:1;
+-01313 
+-01314                 unsigned stsphsercvd:1;
+-01316                 unsigned back2backsetup:1;
+-01317 
+-01318                 unsigned reserved7:1;
+-01320                 unsigned outpkterr:1;
+-01322                 unsigned bna:1;
+-01323 
+-01324                 unsigned reserved10:1;
+-01326                 unsigned pktdrpsts:1;
+-01328                 unsigned babble:1;
+-01330                 unsigned nak:1;
+-01332                 unsigned nyet:1;
+-01333 
+-01334                 unsigned reserved15_31:17;
+-01335         } b;
+-01336 } doepint_data_t;
+-01337 
+-01342 typedef union doepint_data doepmsk_data_t;
+-01343 
+-01350 typedef union daint_data {
+-01352         uint32_t d32;
+-01354         struct {
+-01356                 unsigned in:16;
+-01358                 unsigned out:16;
+-01359         } ep;
+-01360         struct {
+-01362                 unsigned inep0:1;
+-01363                 unsigned inep1:1;
+-01364                 unsigned inep2:1;
+-01365                 unsigned inep3:1;
+-01366                 unsigned inep4:1;
+-01367                 unsigned inep5:1;
+-01368                 unsigned inep6:1;
+-01369                 unsigned inep7:1;
+-01370                 unsigned inep8:1;
+-01371                 unsigned inep9:1;
+-01372                 unsigned inep10:1;
+-01373                 unsigned inep11:1;
+-01374                 unsigned inep12:1;
+-01375                 unsigned inep13:1;
+-01376                 unsigned inep14:1;
+-01377                 unsigned inep15:1;
+-01379                 unsigned outep0:1;
+-01380                 unsigned outep1:1;
+-01381                 unsigned outep2:1;
+-01382                 unsigned outep3:1;
+-01383                 unsigned outep4:1;
+-01384                 unsigned outep5:1;
+-01385                 unsigned outep6:1;
+-01386                 unsigned outep7:1;
+-01387                 unsigned outep8:1;
+-01388                 unsigned outep9:1;
+-01389                 unsigned outep10:1;
+-01390                 unsigned outep11:1;
+-01391                 unsigned outep12:1;
+-01392                 unsigned outep13:1;
+-01393                 unsigned outep14:1;
+-01394                 unsigned outep15:1;
+-01395         } b;
+-01396 } daint_data_t;
+-01397 
+-01404 typedef union dtknq1_data {
+-01406         uint32_t d32;
+-01408         struct {
+-01410                 unsigned intknwptr:5;
+-01412                 unsigned reserved05_06:2;
+-01414                 unsigned wrap_bit:1;
+-01416                 unsigned epnums0_5:24;
+-01417         } b;
+-01418 } dtknq1_data_t;
+-01419 
+-01425 typedef union dthrctl_data {
+-01427         uint32_t d32;
+-01429         struct {
+-01431                 unsigned non_iso_thr_en:1;
+-01433                 unsigned iso_thr_en:1;
+-01435                 unsigned tx_thr_len:9;
+-01437                 unsigned ahb_thr_ratio:2;
+-01439                 unsigned reserved13_15:3;
+-01441                 unsigned rx_thr_en:1;
+-01443                 unsigned rx_thr_len:9;
+-01444                 unsigned reserved26:1;
+-01446                 unsigned arbprken:1;
+-01448                 unsigned reserved28_31:4;
+-01449         } b;
+-01450 } dthrctl_data_t;
+-01451 
+-01462 typedef struct dwc_otg_dev_in_ep_regs {
+-01465         volatile uint32_t diepctl;
+-01467         uint32_t reserved04;
+-01470         volatile uint32_t diepint;
+-01472         uint32_t reserved0C;
+-01475         volatile uint32_t dieptsiz;
+-01478         volatile uint32_t diepdma;
+-01481         volatile uint32_t dtxfsts;
+-01484         volatile uint32_t diepdmab;
+-01485 } dwc_otg_dev_in_ep_regs_t;
+-01486 
+-01497 typedef struct dwc_otg_dev_out_ep_regs {
+-01500         volatile uint32_t doepctl;
+-01502         uint32_t reserved04;
+-01505         volatile uint32_t doepint;
+-01507         uint32_t reserved0C;
+-01510         volatile uint32_t doeptsiz;
+-01513         volatile uint32_t doepdma;
+-01515         uint32_t unused;
+-01518         uint32_t doepdmab;
+-01519 } dwc_otg_dev_out_ep_regs_t;
+-01520 
+-01526 typedef union depctl_data {
+-01528         uint32_t d32;
+-01530         struct {
+-01538                 unsigned mps:11;
+-01539 #define DWC_DEP0CTL_MPS_64       0
+-01540 #define DWC_DEP0CTL_MPS_32       1
+-01541 #define DWC_DEP0CTL_MPS_16       2
+-01542 #define DWC_DEP0CTL_MPS_8        3
+-01543 
+-01547                 unsigned nextep:4;
+-01548 
+-01550                 unsigned usbactep:1;
+-01551 
+-01566                 unsigned dpid:1;
+-01567 
+-01569                 unsigned naksts:1;
+-01570 
+-01576                 unsigned eptype:2;
+-01577 
+-01581                 unsigned snp:1;
+-01582 
+-01584                 unsigned stall:1;
+-01585 
+-01589                 unsigned txfnum:4;
+-01590 
+-01592                 unsigned cnak:1;
+-01594                 unsigned snak:1;
+-01603                 unsigned setd0pid:1;
+-01611                 unsigned setd1pid:1;
+-01612 
+-01614                 unsigned epdis:1;
+-01616                 unsigned epena:1;
+-01617         } b;
+-01618 } depctl_data_t;
+-01619 
+-01625 typedef union deptsiz_data {
+-01627         uint32_t d32;
+-01629         struct {
+-01631                 unsigned xfersize:19;
+-01633 #define MAX_PKT_CNT 1023
+-01634 
+-01635                 unsigned pktcnt:10;
+-01637                 unsigned mc:2;
+-01638                 unsigned reserved:1;
+-01639         } b;
+-01640 } deptsiz_data_t;
+-01641 
+-01647 typedef union deptsiz0_data {
+-01649         uint32_t d32;
+-01651         struct {
+-01653                 unsigned xfersize:7;
+-01655                 unsigned reserved7_18:12;
+-01657                 unsigned pktcnt:2;
+-01659                 unsigned reserved21_28:8;
+-01661                 unsigned supcnt:2;
+-01662                 unsigned reserved31;
+-01663         } b;
+-01664 } deptsiz0_data_t;
+-01665 
+-01667 // DMA Descriptor Specific Structures
+-01668 //
+-01669 
+-01672 #define BS_HOST_READY   0x0
+-01673 #define BS_DMA_BUSY             0x1
+-01674 #define BS_DMA_DONE             0x2
+-01675 #define BS_HOST_BUSY    0x3
+-01676 
+-01679 #define RTS_SUCCESS             0x0
+-01680 #define RTS_BUFFLUSH    0x1
+-01681 #define RTS_RESERVED    0x2
+-01682 #define RTS_BUFERR              0x3
+-01683 
+-01690 typedef union dev_dma_desc_sts {
+-01692         uint32_t d32;
+-01694         struct {
+-01696                 unsigned bytes:16;
+-01698                 unsigned nak:1;
+-01699                 unsigned reserved17_22:6;
+-01701                 unsigned mtrf:1;
+-01703                 unsigned sr:1;
+-01705                 unsigned ioc:1;
+-01707                 unsigned sp:1;
+-01709                 unsigned l:1;
+-01711                 unsigned sts:2;
+-01713                 unsigned bs:2;
+-01714         } b;
+-01715 
+-01716 //#ifdef DWC_EN_ISOC
+-01718         struct {
+-01720                 unsigned rxbytes:11;
+-01721 
+-01722                 unsigned reserved11:1;
+-01724                 unsigned framenum:11;
+-01726                 unsigned pid:2;
+-01728                 unsigned ioc:1;
+-01730                 unsigned sp:1;
+-01732                 unsigned l:1;
+-01734                 unsigned rxsts:2;
+-01736                 unsigned bs:2;
+-01737         } b_iso_out;
+-01738 
+-01740         struct {
+-01742                 unsigned txbytes:12;
+-01744                 unsigned framenum:11;
+-01746                 unsigned pid:2;
+-01748                 unsigned ioc:1;
+-01750                 unsigned sp:1;
+-01752                 unsigned l:1;
+-01754                 unsigned txsts:2;
+-01756                 unsigned bs:2;
+-01757         } b_iso_in;
+-01758 //#endif                                /* DWC_EN_ISOC */
+-01759 } dev_dma_desc_sts_t;
+-01760 
+-01767 typedef struct dwc_otg_dev_dma_desc {
+-01769         dev_dma_desc_sts_t status;
+-01771         uint32_t buf;
+-01772 } dwc_otg_dev_dma_desc_t;
+-01773 
+-01779 typedef struct dwc_otg_dev_if {
+-01783         dwc_otg_device_global_regs_t *dev_global_regs;
+-01784 #define DWC_DEV_GLOBAL_REG_OFFSET 0x800
+-01785 
+-01789         dwc_otg_dev_in_ep_regs_t *in_ep_regs[MAX_EPS_CHANNELS];
+-01790 #define DWC_DEV_IN_EP_REG_OFFSET 0x900
+-01791 #define DWC_EP_REG_OFFSET 0x20
+-01792 
+-01794         dwc_otg_dev_out_ep_regs_t *out_ep_regs[MAX_EPS_CHANNELS];
+-01795 #define DWC_DEV_OUT_EP_REG_OFFSET 0xB00
+-01796 
+-01797         /* Device configuration information */
+-01798         uint8_t speed;                           
+-01799         uint8_t num_in_eps;              
+-01800         uint8_t num_out_eps;             
+-01803         uint16_t perio_tx_fifo_size[MAX_PERIO_FIFOS];
+-01804 
+-01806         uint16_t tx_fifo_size[MAX_TX_FIFOS];
+-01807 
+-01809         uint16_t rx_thr_en;
+-01810         uint16_t iso_tx_thr_en;
+-01811         uint16_t non_iso_tx_thr_en;
+-01812 
+-01813         uint16_t rx_thr_length;
+-01814         uint16_t tx_thr_length;
+-01815 
+-01822         dwc_dma_t dma_setup_desc_addr[2];
+-01823         dwc_otg_dev_dma_desc_t *setup_desc_addr[2];
+-01824 
+-01826         dwc_otg_dev_dma_desc_t *psetup;
+-01827 
+-01829         uint32_t setup_desc_index;
+-01830 
+-01832         dwc_dma_t dma_in_desc_addr;
+-01833         dwc_otg_dev_dma_desc_t *in_desc_addr;
+-01834 
+-01836         dwc_dma_t dma_out_desc_addr;
+-01837         dwc_otg_dev_dma_desc_t *out_desc_addr;
+-01838 
+-01840         uint32_t spd;
+-01842         void *isoc_ep;
+-01843 
+-01844 } dwc_otg_dev_if_t;
+-01845 
+-01847 // Host Mode Register Structures
+-01848 //
+-01854 typedef struct dwc_otg_host_global_regs {
+-01856         volatile uint32_t hcfg;
+-01858         volatile uint32_t hfir;
+-01860         volatile uint32_t hfnum;
+-01862         uint32_t reserved40C;
+-01864         volatile uint32_t hptxsts;
+-01866         volatile uint32_t haint;
+-01868         volatile uint32_t haintmsk;
+-01870         volatile uint32_t hflbaddr;
+-01871 } dwc_otg_host_global_regs_t;
+-01872 
+-01878 typedef union hcfg_data {
+-01880         uint32_t d32;
+-01881 
+-01883         struct {
+-01885                 unsigned fslspclksel:2;
+-01886 #define DWC_HCFG_30_60_MHZ 0
+-01887 #define DWC_HCFG_48_MHZ    1
+-01888 #define DWC_HCFG_6_MHZ     2
+-01889 
+-01891                 unsigned fslssupp:1;
+-01892                 unsigned reserved3_6:4;
+-01894                 unsigned ena32khzs:1;
+-01896                 unsigned resvalid:8;
+-01897                 unsigned reserved16_22:7;
+-01899                 unsigned descdma:1;
+-01901                 unsigned frlisten:2;
+-01903                 unsigned perschedena:1;
+-01904                 unsigned reserved27_30:4;
+-01905                 unsigned modechtimen:1;
+-01906         } b;
+-01907 } hcfg_data_t;
+-01908 
+-01913 typedef union hfir_data {
+-01915         uint32_t d32;
+-01916 
+-01918         struct {
+-01919                 unsigned frint:16;
+-01920                 unsigned hfirrldctrl:1;
+-01921                 unsigned reserved:15;
+-01922         } b;
+-01923 } hfir_data_t;
+-01924 
+-01929 typedef union hfnum_data {
+-01931         uint32_t d32;
+-01932 
+-01934         struct {
+-01935                 unsigned frnum:16;
+-01936 #define DWC_HFNUM_MAX_FRNUM 0x3FFF
+-01937                 unsigned frrem:16;
+-01938         } b;
+-01939 } hfnum_data_t;
+-01940 
+-01941 typedef union hptxsts_data {
+-01943         uint32_t d32;
+-01944 
+-01946         struct {
+-01947                 unsigned ptxfspcavail:16;
+-01948                 unsigned ptxqspcavail:8;
+-01958                 unsigned ptxqtop_terminate:1;
+-01959                 unsigned ptxqtop_token:2;
+-01960                 unsigned ptxqtop_chnum:4;
+-01961                 unsigned ptxqtop_odd:1;
+-01962         } b;
+-01963 } hptxsts_data_t;
+-01964 
+-01971 typedef union hprt0_data {
+-01973         uint32_t d32;
+-01975         struct {
+-01976                 unsigned prtconnsts:1;
+-01977                 unsigned prtconndet:1;
+-01978                 unsigned prtena:1;
+-01979                 unsigned prtenchng:1;
+-01980                 unsigned prtovrcurract:1;
+-01981                 unsigned prtovrcurrchng:1;
+-01982                 unsigned prtres:1;
+-01983                 unsigned prtsusp:1;
+-01984                 unsigned prtrst:1;
+-01985                 unsigned reserved9:1;
+-01986                 unsigned prtlnsts:2;
+-01987                 unsigned prtpwr:1;
+-01988                 unsigned prttstctl:4;
+-01989                 unsigned prtspd:2;
+-01990 #define DWC_HPRT0_PRTSPD_HIGH_SPEED 0
+-01991 #define DWC_HPRT0_PRTSPD_FULL_SPEED 1
+-01992 #define DWC_HPRT0_PRTSPD_LOW_SPEED      2
+-01993                 unsigned reserved19_31:13;
+-01994         } b;
+-01995 } hprt0_data_t;
+-01996 
+-02001 typedef union haint_data {
+-02003         uint32_t d32;
+-02005         struct {
+-02006                 unsigned ch0:1;
+-02007                 unsigned ch1:1;
+-02008                 unsigned ch2:1;
+-02009                 unsigned ch3:1;
+-02010                 unsigned ch4:1;
+-02011                 unsigned ch5:1;
+-02012                 unsigned ch6:1;
+-02013                 unsigned ch7:1;
+-02014                 unsigned ch8:1;
+-02015                 unsigned ch9:1;
+-02016                 unsigned ch10:1;
+-02017                 unsigned ch11:1;
+-02018                 unsigned ch12:1;
+-02019                 unsigned ch13:1;
+-02020                 unsigned ch14:1;
+-02021                 unsigned ch15:1;
+-02022                 unsigned reserved:16;
+-02023         } b;
+-02024 
+-02025         struct {
+-02026                 unsigned chint:16;
+-02027                 unsigned reserved:16;
+-02028         } b2;
+-02029 } haint_data_t;
+-02030 
+-02035 typedef union haintmsk_data {
+-02037         uint32_t d32;
+-02039         struct {
+-02040                 unsigned ch0:1;
+-02041                 unsigned ch1:1;
+-02042                 unsigned ch2:1;
+-02043                 unsigned ch3:1;
+-02044                 unsigned ch4:1;
+-02045                 unsigned ch5:1;
+-02046                 unsigned ch6:1;
+-02047                 unsigned ch7:1;
+-02048                 unsigned ch8:1;
+-02049                 unsigned ch9:1;
+-02050                 unsigned ch10:1;
+-02051                 unsigned ch11:1;
+-02052                 unsigned ch12:1;
+-02053                 unsigned ch13:1;
+-02054                 unsigned ch14:1;
+-02055                 unsigned ch15:1;
+-02056                 unsigned reserved:16;
+-02057         } b;
+-02058 
+-02059         struct {
+-02060                 unsigned chint:16;
+-02061                 unsigned reserved:16;
+-02062         } b2;
+-02063 } haintmsk_data_t;
+-02064 
+-02068 typedef struct dwc_otg_hc_regs {
+-02070         volatile uint32_t hcchar;
+-02072         volatile uint32_t hcsplt;
+-02074         volatile uint32_t hcint;
+-02076         volatile uint32_t hcintmsk;
+-02078         volatile uint32_t hctsiz;
+-02080         volatile uint32_t hcdma;
+-02081         volatile uint32_t reserved;
+-02083         volatile uint32_t hcdmab;
+-02084 } dwc_otg_hc_regs_t;
+-02085 
+-02092 typedef union hcchar_data {
+-02094         uint32_t d32;
+-02095 
+-02097         struct {
+-02099                 unsigned mps:11;
+-02100 
+-02102                 unsigned epnum:4;
+-02103 
+-02105                 unsigned epdir:1;
+-02106 
+-02107                 unsigned reserved:1;
+-02108 
+-02110                 unsigned lspddev:1;
+-02111 
+-02113                 unsigned eptype:2;
+-02114 
+-02116                 unsigned multicnt:2;
+-02117 
+-02119                 unsigned devaddr:7;
+-02120 
+-02125                 unsigned oddfrm:1;
+-02126 
+-02128                 unsigned chdis:1;
+-02129 
+-02131                 unsigned chen:1;
+-02132         } b;
+-02133 } hcchar_data_t;
+-02134 
+-02135 typedef union hcsplt_data {
+-02137         uint32_t d32;
+-02138 
+-02140         struct {
+-02142                 unsigned prtaddr:7;
+-02143 
+-02145                 unsigned hubaddr:7;
+-02146 
+-02148                 unsigned xactpos:2;
+-02149 #define DWC_HCSPLIT_XACTPOS_MID 0
+-02150 #define DWC_HCSPLIT_XACTPOS_END 1
+-02151 #define DWC_HCSPLIT_XACTPOS_BEGIN 2
+-02152 #define DWC_HCSPLIT_XACTPOS_ALL 3
+-02153 
+-02155                 unsigned compsplt:1;
+-02156 
+-02158                 unsigned reserved:14;
+-02159 
+-02161                 unsigned spltena:1;
+-02162         } b;
+-02163 } hcsplt_data_t;
+-02164 
+-02169 typedef union hcint_data {
+-02171         uint32_t d32;
+-02173         struct {
+-02175                 unsigned xfercomp:1;
+-02177                 unsigned chhltd:1;
+-02179                 unsigned ahberr:1;
+-02181                 unsigned stall:1;
+-02183                 unsigned nak:1;
+-02185                 unsigned ack:1;
+-02187                 unsigned nyet:1;
+-02189                 unsigned xacterr:1;
+-02191                 unsigned bblerr:1;
+-02193                 unsigned frmovrun:1;
+-02195                 unsigned datatglerr:1;
+-02197                 unsigned bna:1;
+-02199                 unsigned xcs_xact:1;
+-02201                 unsigned frm_list_roll:1;
+-02203                 unsigned reserved14_31:18;
+-02204         } b;
+-02205 } hcint_data_t;
+-02206 
+-02213 typedef union hcintmsk_data {
+-02215         uint32_t d32;
+-02216 
+-02218         struct {
+-02219                 unsigned xfercompl:1;
+-02220                 unsigned chhltd:1;
+-02221                 unsigned ahberr:1;
+-02222                 unsigned stall:1;
+-02223                 unsigned nak:1;
+-02224                 unsigned ack:1;
+-02225                 unsigned nyet:1;
+-02226                 unsigned xacterr:1;
+-02227                 unsigned bblerr:1;
+-02228                 unsigned frmovrun:1;
+-02229                 unsigned datatglerr:1;
+-02230                 unsigned bna:1;
+-02231                 unsigned xcs_xact:1;
+-02232                 unsigned frm_list_roll:1;
+-02233                 unsigned reserved14_31:18;
+-02234         } b;
+-02235 } hcintmsk_data_t;
+-02236 
+-02244 typedef union hctsiz_data {
+-02246         uint32_t d32;
+-02247 
+-02249         struct {
+-02251                 unsigned xfersize:19;
+-02252 
+-02254                 unsigned pktcnt:10;
+-02255 
+-02263                 unsigned pid:2;
+-02264 #define DWC_HCTSIZ_DATA0 0
+-02265 #define DWC_HCTSIZ_DATA1 2
+-02266 #define DWC_HCTSIZ_DATA2 1
+-02267 #define DWC_HCTSIZ_MDATA 3
+-02268 #define DWC_HCTSIZ_SETUP 3
+-02269 
+-02271                 unsigned dopng:1;
+-02272         } b;
+-02273 
+-02275         struct {
+-02277                 unsigned schinfo:8;
+-02278 
+-02284                 unsigned ntd:8;
+-02285 
+-02287                 unsigned reserved16_28:13;
+-02288 
+-02296                 unsigned pid:2;
+-02297 
+-02299                 unsigned dopng:1;
+-02300         } b_ddma;
+-02301 } hctsiz_data_t;
+-02302 
+-02307 typedef union hcdma_data {
+-02309         uint32_t d32;
+-02311         struct {
+-02312                 unsigned reserved0_2:3;
+-02314                 unsigned ctd:8;
+-02316                 unsigned dma_addr:21;
+-02317         } b;
+-02318 } hcdma_data_t;
+-02319 
+-02325 typedef union host_dma_desc_sts {
+-02327         uint32_t d32;
+-02330         /* for non-isochronous  */
+-02331         struct {
+-02333                 unsigned n_bytes:17;
+-02335                 unsigned qtd_offset:6;
+-02340                 unsigned a_qtd:1;
+-02345                 unsigned sup:1;
+-02347                 unsigned ioc:1;
+-02349                 unsigned eol:1;
+-02350                 unsigned reserved27:1;
+-02352                 unsigned sts:2;
+-02353 #define DMA_DESC_STS_PKTERR     1
+-02354                 unsigned reserved30:1;
+-02356                 unsigned a:1;
+-02357         } b;
+-02358         /* for isochronous */
+-02359         struct {
+-02361                 unsigned n_bytes:12;
+-02362                 unsigned reserved12_24:13;
+-02364                 unsigned ioc:1;
+-02365                 unsigned reserved26_27:2;
+-02367                 unsigned sts:2;
+-02368                 unsigned reserved30:1;
+-02370                 unsigned a:1;
+-02371         } b_isoc;
+-02372 } host_dma_desc_sts_t;
+-02373 
+-02374 #define MAX_DMA_DESC_SIZE               131071
+-02375 #define MAX_DMA_DESC_NUM_GENERIC        64
+-02376 #define MAX_DMA_DESC_NUM_HS_ISOC        256
+-02377 #define MAX_FRLIST_EN_NUM               64
+-02378 
+-02384 typedef struct dwc_otg_host_dma_desc {
+-02386         host_dma_desc_sts_t status;
+-02388         uint32_t buf;
+-02389 } dwc_otg_host_dma_desc_t;
+-02390 
+-02398 typedef struct dwc_otg_host_if {
+-02400         dwc_otg_host_global_regs_t *host_global_regs;
+-02401 #define DWC_OTG_HOST_GLOBAL_REG_OFFSET 0x400
+-02402 
+-02404         volatile uint32_t *hprt0;
+-02405 #define DWC_OTG_HOST_PORT_REGS_OFFSET 0x440
+-02406 
+-02408         dwc_otg_hc_regs_t *hc_regs[MAX_EPS_CHANNELS];
+-02409 #define DWC_OTG_HOST_CHAN_REGS_OFFSET 0x500
+-02410 #define DWC_OTG_CHAN_REGS_OFFSET 0x20
+-02411 
+-02412         /* Host configuration information */
+-02414         uint8_t num_host_channels;
+-02416         uint8_t perio_eps_supported;
+-02418         uint16_t perio_tx_fifo_size;
+-02419 
+-02420 } dwc_otg_host_if_t;
+-02421 
+-02427 typedef union pcgcctl_data {
+-02429         uint32_t d32;
+-02430 
+-02432         struct {
+-02434                 unsigned stoppclk:1;
+-02436                 unsigned gatehclk:1;
+-02438                 unsigned pwrclmp:1;
+-02440                 unsigned rstpdwnmodule:1;
+-02442                 unsigned reserved:1;
+-02444                 unsigned enbl_sleep_gating:1;
+-02446                 unsigned phy_in_sleep:1;
+-02448                 unsigned deep_sleep:1;
+-02449                 unsigned resetaftsusp:1;
+-02450                 unsigned restoremode:1;
+-02451                 unsigned reserved10_12:3;
+-02452                 unsigned ess_reg_restored:1;
+-02453                 unsigned prt_clk_sel:2;
+-02454                 unsigned port_power:1;
+-02455                 unsigned max_xcvrselect:2;
+-02456                 unsigned max_termsel:1;
+-02457                 unsigned mac_dev_addr:7;
+-02458                 unsigned p2hd_dev_enum_spd:2;
+-02459                 unsigned p2hd_prt_spd:2;
+-02460                 unsigned if_dev_mode:1;
+-02461         } b;
+-02462 } pcgcctl_data_t;
+-02463 
+-02469 typedef union gdfifocfg_data {
+-02470         /* raw register data */
+-02471         uint32_t d32;
+-02473         struct {
+-02475                 unsigned gdfifocfg:16;
+-02477                 unsigned epinfobase:16;
+-02478         } b;
+-02479 } gdfifocfg_data_t;
+-02480 
+-02486 typedef union gpwrdn_data {
+-02487         /* raw register data */
+-02488         uint32_t d32;
+-02489 
+-02491         struct {
+-02493                 unsigned pmuintsel:1;
+-02495                 unsigned pmuactv:1;
+-02497                 unsigned restore:1;
+-02499                 unsigned pwrdnclmp:1;
+-02501                 unsigned pwrdnrstn:1;
+-02503                 unsigned pwrdnswtch:1;
+-02505                 unsigned dis_vbus:1;
+-02507                 unsigned lnstschng:1;
+-02509                 unsigned lnstchng_msk:1;
+-02511                 unsigned rst_det:1;
+-02513                 unsigned rst_det_msk:1;
+-02515                 unsigned disconn_det:1;
+-02517                 unsigned disconn_det_msk:1;
+-02519                 unsigned connect_det:1;
+-02521                 unsigned connect_det_msk:1;
+-02523                 unsigned srp_det:1;
+-02525                 unsigned srp_det_msk:1;
+-02527                 unsigned sts_chngint:1;
+-02529                 unsigned sts_chngint_msk:1;
+-02531                 unsigned linestate:2;
+-02533                 unsigned idsts:1;
+-02535                 unsigned bsessvld:1;
+-02537                 unsigned adp_int:1;
+-02539                 unsigned mult_val_id_bc:5;
+-02541                 unsigned reserved29_31:3;
+-02542         } b;
+-02543 } gpwrdn_data_t;
+-02544 
+-02545 #endif
+-
                                                                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/dwc__otg__regs_8h.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/dwc__otg__regs_8h.html 2013-07-26 19:34:42.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,2031 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_regs.h File Reference +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                dwc_otg_regs.h File Reference

                                                                                This file contains the data structures for accessing the DWC_otg core registers. More... +-

                                                                                +-#include "dwc_otg_core_if.h"
                                                                                +- +-

                                                                                +-Go to the source code of this file. +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-

                                                                                Data Structures

                                                                                struct  dwc_otg_core_global_regs
                                                                                 DWC_otg Core registers . More...
                                                                                union  gotgctl_data
                                                                                 This union represents the bit fields of the Core OTG Control and Status Register (GOTGCTL). More...
                                                                                union  gotgint_data
                                                                                 This union represents the bit fields of the Core OTG Interrupt Register (GOTGINT). More...
                                                                                union  gahbcfg_data
                                                                                 This union represents the bit fields of the Core AHB Configuration Register (GAHBCFG). More...
                                                                                union  gusbcfg_data
                                                                                 This union represents the bit fields of the Core USB Configuration Register (GUSBCFG). More...
                                                                                union  grstctl_data
                                                                                 This union represents the bit fields of the Core Reset Register (GRSTCTL). More...
                                                                                union  gintmsk_data
                                                                                 This union represents the bit fields of the Core Interrupt Mask Register (GINTMSK). More...
                                                                                union  gintsts_data
                                                                                 This union represents the bit fields of the Core Interrupt Register (GINTSTS). More...
                                                                                union  device_grxsts_data
                                                                                 This union represents the bit fields in the Device Receive Status Read and Pop Registers (GRXSTSR, GRXSTSP) Read the register into the d32 element then read out the bits using the bit elements. More...
                                                                                union  host_grxsts_data
                                                                                 This union represents the bit fields in the Host Receive Status Read and Pop Registers (GRXSTSR, GRXSTSP) Read the register into the d32 element then read out the bits using the bit elements. More...
                                                                                union  fifosize_data
                                                                                 This union represents the bit fields in the FIFO Size Registers (HPTXFSIZ, GNPTXFSIZ, DPTXFSIZn, DIEPTXFn). More...
                                                                                union  gnptxsts_data
                                                                                 This union represents the bit fields in the Non-Periodic Transmit FIFO/Queue Status Register (GNPTXSTS). More...
                                                                                union  dtxfsts_data
                                                                                 This union represents the bit fields in the Transmit FIFO Status Register (DTXFSTS). More...
                                                                                union  gi2cctl_data
                                                                                 This union represents the bit fields in the I2C Control Register (I2CCTL). More...
                                                                                union  gpvndctl_data
                                                                                 This union represents the bit fields in the PHY Vendor Control Register (GPVNDCTL). More...
                                                                                union  ggpio_data
                                                                                 This union represents the bit fields in the General Purpose Input/Output Register (GGPIO). More...
                                                                                union  guid_data
                                                                                 This union represents the bit fields in the User ID Register (GUID). More...
                                                                                union  gsnpsid_data
                                                                                 This union represents the bit fields in the Synopsys ID Register (GSNPSID). More...
                                                                                union  hwcfg1_data
                                                                                 This union represents the bit fields in the User HW Config1 Register. More...
                                                                                union  hwcfg2_data
                                                                                 This union represents the bit fields in the User HW Config2 Register. More...
                                                                                union  hwcfg3_data
                                                                                 This union represents the bit fields in the User HW Config3 Register. More...
                                                                                union  hwcfg4_data
                                                                                 This union represents the bit fields in the User HW Config4 Register. More...
                                                                                union  glpmctl_data
                                                                                 This union represents the bit fields of the Core LPM Configuration Register (GLPMCFG). More...
                                                                                union  adpctl_data
                                                                                 This union represents the bit fields of the Core ADP Timer, Control and Status Register (ADPTIMCTLSTS). More...
                                                                                struct  dwc_otg_dev_global_regs
                                                                                 Device Global Registers. More...
                                                                                union  dcfg_data
                                                                                 This union represents the bit fields in the Device Configuration Register. More...
                                                                                union  dctl_data
                                                                                 This union represents the bit fields in the Device Control Register. More...
                                                                                union  dsts_data
                                                                                 This union represents the bit fields in the Device Status Register. More...
                                                                                union  diepint_data
                                                                                 This union represents the bit fields in the Device IN EP Interrupt Register and the Device IN EP Common Mask Register. More...
                                                                                union  doepint_data
                                                                                 This union represents the bit fields in the Device OUT EP Interrupt Registerand Device OUT EP Common Interrupt Mask Register. More...
                                                                                union  daint_data
                                                                                 This union represents the bit fields in the Device All EP Interrupt and Mask Registers. More...
                                                                                union  dtknq1_data
                                                                                 This union represents the bit fields in the Device IN Token Queue Read Registers. More...
                                                                                union  dthrctl_data
                                                                                 This union represents Threshold control Register Read and write the register into the d32 member. More...
                                                                                struct  dwc_otg_dev_in_ep_regs
                                                                                 Device Logical IN Endpoint-Specific Registers. More...
                                                                                struct  dwc_otg_dev_out_ep_regs
                                                                                 Device Logical OUT Endpoint-Specific Registers. More...
                                                                                union  depctl_data
                                                                                 This union represents the bit fields in the Device EP Control Register. More...
                                                                                union  deptsiz_data
                                                                                 This union represents the bit fields in the Device EP Transfer Size Register. More...
                                                                                union  deptsiz0_data
                                                                                 This union represents the bit fields in the Device EP 0 Transfer Size Register. More...
                                                                                union  dev_dma_desc_sts
                                                                                 This union represents the bit fields in the DMA Descriptor status quadlet. More...
                                                                                struct  dwc_otg_dev_dma_desc
                                                                                 DMA Descriptor structure. More...
                                                                                struct  dwc_otg_dev_if
                                                                                 The dwc_otg_dev_if structure contains information needed to manage the DWC_otg controller acting in device mode. More...
                                                                                struct  dwc_otg_host_global_regs
                                                                                 The Host Global Registers structure defines the size and relative field offsets for the Host Mode Global Registers. More...
                                                                                union  hcfg_data
                                                                                 This union represents the bit fields in the Host Configuration Register. More...
                                                                                union  hfir_data
                                                                                 This union represents the bit fields in the Host Frame Remaing/Number Register. More...
                                                                                union  hfnum_data
                                                                                 This union represents the bit fields in the Host Frame Remaing/Number Register. More...
                                                                                union  hptxsts_data
                                                                                union  hprt0_data
                                                                                 This union represents the bit fields in the Host Port Control and Status Register. More...
                                                                                union  haint_data
                                                                                 This union represents the bit fields in the Host All Interrupt Register. More...
                                                                                union  haintmsk_data
                                                                                 This union represents the bit fields in the Host All Interrupt Register. More...
                                                                                struct  dwc_otg_hc_regs
                                                                                 Host Channel Specific Registers. More...
                                                                                union  hcchar_data
                                                                                 This union represents the bit fields in the Host Channel Characteristics Register. More...
                                                                                union  hcsplt_data
                                                                                union  hcint_data
                                                                                 This union represents the bit fields in the Host All Interrupt Register. More...
                                                                                union  hcintmsk_data
                                                                                 This union represents the bit fields in the Host Channel Interrupt Mask Register. More...
                                                                                union  hctsiz_data
                                                                                 This union represents the bit fields in the Host Channel Transfer Size Register. More...
                                                                                union  hcdma_data
                                                                                 This union represents the bit fields in the Host DMA Address Register used in Descriptor DMA mode. More...
                                                                                union  host_dma_desc_sts
                                                                                 This union represents the bit fields in the DMA Descriptor status quadlet for host mode. More...
                                                                                struct  dwc_otg_host_dma_desc
                                                                                 Host-mode DMA Descriptor structure. More...
                                                                                struct  dwc_otg_host_if
                                                                                 OTG Host Interface Structure. More...
                                                                                union  pcgcctl_data
                                                                                 This union represents the bit fields in the Power and Clock Gating Control Register. More...
                                                                                union  gdfifocfg_data
                                                                                 This union represents the bit fields in the Global Data FIFO Software Configuration Register. More...
                                                                                union  gpwrdn_data
                                                                                 This union represents the bit fields in the Global Power Down Register Register. More...

                                                                                Defines

                                                                                +-#define DWC_GLBINTRMASK   0x0001
                                                                                +-#define DWC_DMAENABLE   0x0020
                                                                                +-#define DWC_NPTXEMPTYLVL_EMPTY   0x0080
                                                                                +-#define DWC_NPTXEMPTYLVL_HALFEMPTY   0x0000
                                                                                +-#define DWC_PTXEMPTYLVL_EMPTY   0x0100
                                                                                +-#define DWC_PTXEMPTYLVL_HALFEMPTY   0x0000
                                                                                +-#define DWC_SLAVE_ONLY_ARCH   0
                                                                                +-#define DWC_EXT_DMA_ARCH   1
                                                                                +-#define DWC_INT_DMA_ARCH   2
                                                                                +-#define DWC_MODE_HNP_SRP_CAPABLE   0
                                                                                +-#define DWC_MODE_SRP_ONLY_CAPABLE   1
                                                                                +-#define DWC_MODE_NO_HNP_SRP_CAPABLE   2
                                                                                +-#define DWC_MODE_SRP_CAPABLE_DEVICE   3
                                                                                +-#define DWC_MODE_NO_SRP_CAPABLE_DEVICE   4
                                                                                +-#define DWC_MODE_SRP_CAPABLE_HOST   5
                                                                                +-#define DWC_MODE_NO_SRP_CAPABLE_HOST   6
                                                                                +-#define DWC_GAHBCFG_GLBINT_ENABLE   1
                                                                                +-#define DWC_GAHBCFG_INT_DMA_BURST_SINGLE   0
                                                                                +-#define DWC_GAHBCFG_INT_DMA_BURST_INCR   1
                                                                                +-#define DWC_GAHBCFG_INT_DMA_BURST_INCR4   3
                                                                                +-#define DWC_GAHBCFG_INT_DMA_BURST_INCR8   5
                                                                                +-#define DWC_GAHBCFG_INT_DMA_BURST_INCR16   7
                                                                                +-#define DWC_GAHBCFG_DMAENABLE   1
                                                                                +-#define DWC_GAHBCFG_TXFEMPTYLVL_EMPTY   1
                                                                                +-#define DWC_GAHBCFG_TXFEMPTYLVL_HALFEMPTY   0
                                                                                +-#define DWC_SOF_INTR_MASK   0x0008
                                                                                +-#define DWC_HOST_MODE   1
                                                                                +-#define DWC_STS_DATA_UPDT   0x2
                                                                                +-#define DWC_STS_XFER_COMP   0x3
                                                                                +-#define DWC_DSTS_GOUT_NAK   0x1
                                                                                +-#define DWC_DSTS_SETUP_COMP   0x4
                                                                                +-#define DWC_DSTS_SETUP_UPDT   0x6
                                                                                +-#define DWC_GRXSTS_PKTSTS_IN   0x2
                                                                                +-#define DWC_GRXSTS_PKTSTS_IN_XFER_COMP   0x3
                                                                                +-#define DWC_GRXSTS_PKTSTS_DATA_TOGGLE_ERR   0x5
                                                                                +-#define DWC_GRXSTS_PKTSTS_CH_HALTED   0x7
                                                                                +-#define DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG   0
                                                                                +-#define DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG   1
                                                                                +-#define DWC_HWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE_OTG   2
                                                                                +-#define DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE   3
                                                                                +-#define DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE   4
                                                                                +-#define DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST   5
                                                                                +-#define DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST   6
                                                                                +-#define DWC_HWCFG2_HS_PHY_TYPE_NOT_SUPPORTED   0
                                                                                +-#define DWC_HWCFG2_HS_PHY_TYPE_UTMI   1
                                                                                +-#define DWC_HWCFG2_HS_PHY_TYPE_ULPI   2
                                                                                +-#define DWC_HWCFG2_HS_PHY_TYPE_UTMI_ULPI   3
                                                                                +-#define DWC_DCFG_SEND_STALL   1
                                                                                +-#define DWC_DCFG_FRAME_INTERVAL_80   0
                                                                                +-#define DWC_DCFG_FRAME_INTERVAL_85   1
                                                                                +-#define DWC_DCFG_FRAME_INTERVAL_90   2
                                                                                +-#define DWC_DCFG_FRAME_INTERVAL_95   3
                                                                                +-#define DWC_DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ   0
                                                                                +-#define DWC_DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ   1
                                                                                +-#define DWC_DSTS_ENUMSPD_LS_PHY_6MHZ   2
                                                                                +-#define DWC_DSTS_ENUMSPD_FS_PHY_48MHZ   3
                                                                                +-#define DWC_DEP0CTL_MPS_64   0
                                                                                +-#define DWC_DEP0CTL_MPS_32   1
                                                                                +-#define DWC_DEP0CTL_MPS_16   2
                                                                                +-#define DWC_DEP0CTL_MPS_8   3
                                                                                +-#define MAX_PKT_CNT   1023
                                                                                 Max packet count for EP (pow(2,10)-1).
                                                                                +-#define BS_HOST_READY   0x0
                                                                                 Buffer status definitions.
                                                                                +-#define BS_DMA_BUSY   0x1
                                                                                +-#define BS_DMA_DONE   0x2
                                                                                +-#define BS_HOST_BUSY   0x3
                                                                                +-#define RTS_SUCCESS   0x0
                                                                                 Receive/Transmit status definitions.
                                                                                +-#define RTS_BUFFLUSH   0x1
                                                                                +-#define RTS_RESERVED   0x2
                                                                                +-#define RTS_BUFERR   0x3
                                                                                +-#define DWC_DEV_GLOBAL_REG_OFFSET   0x800
                                                                                +-#define DWC_DEV_IN_EP_REG_OFFSET   0x900
                                                                                +-#define DWC_EP_REG_OFFSET   0x20
                                                                                +-#define DWC_DEV_OUT_EP_REG_OFFSET   0xB00
                                                                                +-#define DWC_HCFG_30_60_MHZ   0
                                                                                +-#define DWC_HCFG_48_MHZ   1
                                                                                +-#define DWC_HCFG_6_MHZ   2
                                                                                +-#define DWC_HFNUM_MAX_FRNUM   0x3FFF
                                                                                +-#define DWC_HPRT0_PRTSPD_HIGH_SPEED   0
                                                                                +-#define DWC_HPRT0_PRTSPD_FULL_SPEED   1
                                                                                +-#define DWC_HPRT0_PRTSPD_LOW_SPEED   2
                                                                                +-#define DWC_HCSPLIT_XACTPOS_MID   0
                                                                                +-#define DWC_HCSPLIT_XACTPOS_END   1
                                                                                +-#define DWC_HCSPLIT_XACTPOS_BEGIN   2
                                                                                +-#define DWC_HCSPLIT_XACTPOS_ALL   3
                                                                                +-#define DWC_HCTSIZ_DATA0   0
                                                                                +-#define DWC_HCTSIZ_DATA1   2
                                                                                +-#define DWC_HCTSIZ_DATA2   1
                                                                                +-#define DWC_HCTSIZ_MDATA   3
                                                                                +-#define DWC_HCTSIZ_SETUP   3
                                                                                +-#define DMA_DESC_STS_PKTERR   1
                                                                                +-#define MAX_DMA_DESC_SIZE   131071
                                                                                +-#define MAX_DMA_DESC_NUM_GENERIC   64
                                                                                +-#define MAX_DMA_DESC_NUM_HS_ISOC   256
                                                                                +-#define MAX_FRLIST_EN_NUM   64
                                                                                +-#define DWC_OTG_HOST_GLOBAL_REG_OFFSET   0x400
                                                                                +-#define DWC_OTG_HOST_PORT_REGS_OFFSET   0x440
                                                                                +-#define DWC_OTG_HOST_CHAN_REGS_OFFSET   0x500
                                                                                +-#define DWC_OTG_CHAN_REGS_OFFSET   0x20

                                                                                Typedefs

                                                                                typedef dwc_otg_core_global_regs dwc_otg_core_global_regs_t
                                                                                 DWC_otg Core registers .
                                                                                typedef gotgctl_data gotgctl_data_t
                                                                                 This union represents the bit fields of the Core OTG Control and Status Register (GOTGCTL).
                                                                                typedef gotgint_data gotgint_data_t
                                                                                 This union represents the bit fields of the Core OTG Interrupt Register (GOTGINT).
                                                                                typedef gahbcfg_data gahbcfg_data_t
                                                                                 This union represents the bit fields of the Core AHB Configuration Register (GAHBCFG).
                                                                                typedef gusbcfg_data gusbcfg_data_t
                                                                                 This union represents the bit fields of the Core USB Configuration Register (GUSBCFG).
                                                                                typedef grstctl_data grstctl_t
                                                                                 This union represents the bit fields of the Core Reset Register (GRSTCTL).
                                                                                typedef gintmsk_data gintmsk_data_t
                                                                                 This union represents the bit fields of the Core Interrupt Mask Register (GINTMSK).
                                                                                typedef gintsts_data gintsts_data_t
                                                                                 This union represents the bit fields of the Core Interrupt Register (GINTSTS).
                                                                                +-typedef device_grxsts_data device_grxsts_data_t
                                                                                 This union represents the bit fields in the Device Receive Status Read and Pop Registers (GRXSTSR, GRXSTSP) Read the register into the d32 element then read out the bits using the bit elements.
                                                                                +-typedef host_grxsts_data host_grxsts_data_t
                                                                                 This union represents the bit fields in the Host Receive Status Read and Pop Registers (GRXSTSR, GRXSTSP) Read the register into the d32 element then read out the bits using the bit elements.
                                                                                typedef fifosize_data fifosize_data_t
                                                                                 This union represents the bit fields in the FIFO Size Registers (HPTXFSIZ, GNPTXFSIZ, DPTXFSIZn, DIEPTXFn).
                                                                                typedef gnptxsts_data gnptxsts_data_t
                                                                                 This union represents the bit fields in the Non-Periodic Transmit FIFO/Queue Status Register (GNPTXSTS).
                                                                                typedef dtxfsts_data dtxfsts_data_t
                                                                                 This union represents the bit fields in the Transmit FIFO Status Register (DTXFSTS).
                                                                                typedef gi2cctl_data gi2cctl_data_t
                                                                                 This union represents the bit fields in the I2C Control Register (I2CCTL).
                                                                                typedef gpvndctl_data gpvndctl_data_t
                                                                                 This union represents the bit fields in the PHY Vendor Control Register (GPVNDCTL).
                                                                                typedef ggpio_data ggpio_data_t
                                                                                 This union represents the bit fields in the General Purpose Input/Output Register (GGPIO).
                                                                                typedef guid_data guid_data_t
                                                                                 This union represents the bit fields in the User ID Register (GUID).
                                                                                typedef gsnpsid_data gsnpsid_data_t
                                                                                 This union represents the bit fields in the Synopsys ID Register (GSNPSID).
                                                                                typedef hwcfg1_data hwcfg1_data_t
                                                                                 This union represents the bit fields in the User HW Config1 Register.
                                                                                typedef hwcfg2_data hwcfg2_data_t
                                                                                 This union represents the bit fields in the User HW Config2 Register.
                                                                                typedef hwcfg3_data hwcfg3_data_t
                                                                                 This union represents the bit fields in the User HW Config3 Register.
                                                                                typedef hwcfg4_data hwcfg4_data_t
                                                                                 This union represents the bit fields in the User HW Config4 Register.
                                                                                typedef glpmctl_data glpmcfg_data_t
                                                                                 This union represents the bit fields of the Core LPM Configuration Register (GLPMCFG).
                                                                                typedef adpctl_data adpctl_data_t
                                                                                 This union represents the bit fields of the Core ADP Timer, Control and Status Register (ADPTIMCTLSTS).
                                                                                typedef dwc_otg_dev_global_regs dwc_otg_device_global_regs_t
                                                                                 Device Global Registers.
                                                                                typedef dcfg_data dcfg_data_t
                                                                                 This union represents the bit fields in the Device Configuration Register.
                                                                                typedef dctl_data dctl_data_t
                                                                                 This union represents the bit fields in the Device Control Register.
                                                                                typedef dsts_data dsts_data_t
                                                                                 This union represents the bit fields in the Device Status Register.
                                                                                typedef diepint_data diepint_data_t
                                                                                 This union represents the bit fields in the Device IN EP Interrupt Register and the Device IN EP Common Mask Register.
                                                                                +-typedef diepint_data diepmsk_data_t
                                                                                 This union represents the bit fields in the Device IN EP Common/Dedicated Interrupt Mask Register.
                                                                                typedef doepint_data doepint_data_t
                                                                                 This union represents the bit fields in the Device OUT EP Interrupt Registerand Device OUT EP Common Interrupt Mask Register.
                                                                                +-typedef doepint_data doepmsk_data_t
                                                                                 This union represents the bit fields in the Device OUT EP Common/Dedicated Interrupt Mask Register.
                                                                                typedef daint_data daint_data_t
                                                                                 This union represents the bit fields in the Device All EP Interrupt and Mask Registers.
                                                                                typedef dtknq1_data dtknq1_data_t
                                                                                 This union represents the bit fields in the Device IN Token Queue Read Registers.
                                                                                typedef dthrctl_data dthrctl_data_t
                                                                                 This union represents Threshold control Register Read and write the register into the d32 member.
                                                                                typedef dwc_otg_dev_in_ep_regs dwc_otg_dev_in_ep_regs_t
                                                                                 Device Logical IN Endpoint-Specific Registers.
                                                                                typedef dwc_otg_dev_out_ep_regs dwc_otg_dev_out_ep_regs_t
                                                                                 Device Logical OUT Endpoint-Specific Registers.
                                                                                typedef depctl_data depctl_data_t
                                                                                 This union represents the bit fields in the Device EP Control Register.
                                                                                typedef deptsiz_data deptsiz_data_t
                                                                                 This union represents the bit fields in the Device EP Transfer Size Register.
                                                                                typedef deptsiz0_data deptsiz0_data_t
                                                                                 This union represents the bit fields in the Device EP 0 Transfer Size Register.
                                                                                typedef dev_dma_desc_sts dev_dma_desc_sts_t
                                                                                 This union represents the bit fields in the DMA Descriptor status quadlet.
                                                                                typedef dwc_otg_dev_dma_desc dwc_otg_dev_dma_desc_t
                                                                                 DMA Descriptor structure.
                                                                                typedef dwc_otg_dev_if dwc_otg_dev_if_t
                                                                                 The dwc_otg_dev_if structure contains information needed to manage the DWC_otg controller acting in device mode.
                                                                                typedef dwc_otg_host_global_regs dwc_otg_host_global_regs_t
                                                                                 The Host Global Registers structure defines the size and relative field offsets for the Host Mode Global Registers.
                                                                                typedef hcfg_data hcfg_data_t
                                                                                 This union represents the bit fields in the Host Configuration Register.
                                                                                +-typedef hfir_data hfir_data_t
                                                                                 This union represents the bit fields in the Host Frame Remaing/Number Register.
                                                                                +-typedef hfnum_data hfnum_data_t
                                                                                 This union represents the bit fields in the Host Frame Remaing/Number Register.
                                                                                +-typedef hptxsts_data hptxsts_data_t
                                                                                typedef hprt0_data hprt0_data_t
                                                                                 This union represents the bit fields in the Host Port Control and Status Register.
                                                                                +-typedef haint_data haint_data_t
                                                                                 This union represents the bit fields in the Host All Interrupt Register.
                                                                                +-typedef haintmsk_data haintmsk_data_t
                                                                                 This union represents the bit fields in the Host All Interrupt Register.
                                                                                typedef dwc_otg_hc_regs dwc_otg_hc_regs_t
                                                                                 Host Channel Specific Registers.
                                                                                typedef hcchar_data hcchar_data_t
                                                                                 This union represents the bit fields in the Host Channel Characteristics Register.
                                                                                +-typedef hcsplt_data hcsplt_data_t
                                                                                +-typedef hcint_data hcint_data_t
                                                                                 This union represents the bit fields in the Host All Interrupt Register.
                                                                                typedef hcintmsk_data hcintmsk_data_t
                                                                                 This union represents the bit fields in the Host Channel Interrupt Mask Register.
                                                                                typedef hctsiz_data hctsiz_data_t
                                                                                 This union represents the bit fields in the Host Channel Transfer Size Register.
                                                                                +-typedef hcdma_data hcdma_data_t
                                                                                 This union represents the bit fields in the Host DMA Address Register used in Descriptor DMA mode.
                                                                                typedef host_dma_desc_sts host_dma_desc_sts_t
                                                                                 This union represents the bit fields in the DMA Descriptor status quadlet for host mode.
                                                                                typedef dwc_otg_host_dma_desc dwc_otg_host_dma_desc_t
                                                                                 Host-mode DMA Descriptor structure.
                                                                                typedef dwc_otg_host_if dwc_otg_host_if_t
                                                                                 OTG Host Interface Structure.
                                                                                typedef pcgcctl_data pcgcctl_data_t
                                                                                 This union represents the bit fields in the Power and Clock Gating Control Register.
                                                                                typedef gdfifocfg_data gdfifocfg_data_t
                                                                                 This union represents the bit fields in the Global Data FIFO Software Configuration Register.
                                                                                typedef gpwrdn_data gpwrdn_data_t
                                                                                 This union represents the bit fields in the Global Power Down Register Register.
                                                                                +-

                                                                                Detailed Description

                                                                                +-This file contains the data structures for accessing the DWC_otg core registers. +-

                                                                                +-The application interfaces with the HS OTG core by reading from and writing to the Control and Status Register (CSR) space through the AHB Slave interface. These registers are 32 bits wide, and the addresses are 32-bit-block aligned. CSRs are classified as follows:

                                                                                  +-
                                                                                • Core Global Registers
                                                                                • Device Mode Registers
                                                                                • Device Global Registers
                                                                                • Device Endpoint Specific Registers
                                                                                • Host Mode Registers
                                                                                • Host Global Registers
                                                                                • Host Port CSRs
                                                                                • Host Channel Specific Registers
                                                                                +-

                                                                                +-Only the Core Global registers can be accessed in both Device and Host modes. When the HS OTG core is operating in one mode, either Device or Host, the application must not access registers from the other mode. When the core switches from one mode to another, the registers in the new mode of operation must be reprogrammed as they would be after a power-on reset. +-

                                                                                +-Definition in file dwc_otg_regs.h.

                                                                                Typedef Documentation

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                typedef struct dwc_otg_core_global_regs dwc_otg_core_global_regs_t
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-DWC_otg Core registers . +-

                                                                                +-The dwc_otg_core_global_regs structure defines the size and relative field offsets for the Core Global registers.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                typedef union gotgctl_data gotgctl_data_t
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This union represents the bit fields of the Core OTG Control and Status Register (GOTGCTL). +-

                                                                                +-Set the bits using the bit fields then write the d32 value to the register.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                typedef union gotgint_data gotgint_data_t
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This union represents the bit fields of the Core OTG Interrupt Register (GOTGINT). +-

                                                                                +-Set/clear the bits using the bit fields then write the d32 value to the register.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                typedef union gahbcfg_data gahbcfg_data_t
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This union represents the bit fields of the Core AHB Configuration Register (GAHBCFG). +-

                                                                                +-Set/clear the bits using the bit fields then write the d32 value to the register.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                typedef union gusbcfg_data gusbcfg_data_t
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This union represents the bit fields of the Core USB Configuration Register (GUSBCFG). +-

                                                                                +-Set the bits using the bit fields then write the d32 value to the register.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                typedef union grstctl_data grstctl_t
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This union represents the bit fields of the Core Reset Register (GRSTCTL). +-

                                                                                +-Set/clear the bits using the bit fields then write the d32 value to the register.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                typedef union gintmsk_data gintmsk_data_t
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This union represents the bit fields of the Core Interrupt Mask Register (GINTMSK). +-

                                                                                +-Set/clear the bits using the bit fields then write the d32 value to the register.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                typedef union gintsts_data gintsts_data_t
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This union represents the bit fields of the Core Interrupt Register (GINTSTS). +-

                                                                                +-Set/clear the bits using the bit fields then write the d32 value to the register.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                typedef union fifosize_data fifosize_data_t
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This union represents the bit fields in the FIFO Size Registers (HPTXFSIZ, GNPTXFSIZ, DPTXFSIZn, DIEPTXFn). +-

                                                                                +-Read the register into the d32 element then read out the bits using the bit elements.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                typedef union gnptxsts_data gnptxsts_data_t
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This union represents the bit fields in the Non-Periodic Transmit FIFO/Queue Status Register (GNPTXSTS). +-

                                                                                +-Read the register into the d32 element then read out the bits using the bit elements.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                typedef union dtxfsts_data dtxfsts_data_t
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This union represents the bit fields in the Transmit FIFO Status Register (DTXFSTS). +-

                                                                                +-Read the register into the d32 element then read out the bits using the bit elements.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                typedef union gi2cctl_data gi2cctl_data_t
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This union represents the bit fields in the I2C Control Register (I2CCTL). +-

                                                                                +-Read the register into the d32 element then read out the bits using the bit elements.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                typedef union gpvndctl_data gpvndctl_data_t
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This union represents the bit fields in the PHY Vendor Control Register (GPVNDCTL). +-

                                                                                +-Read the register into the d32 element then read out the bits using the bit elements.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                typedef union ggpio_data ggpio_data_t
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This union represents the bit fields in the General Purpose Input/Output Register (GGPIO). +-

                                                                                +-Read the register into the d32 element then read out the bits using the bit elements.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                typedef union guid_data guid_data_t
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This union represents the bit fields in the User ID Register (GUID). +-

                                                                                +-Read the register into the d32 element then read out the bits using the bit elements.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                typedef union gsnpsid_data gsnpsid_data_t
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This union represents the bit fields in the Synopsys ID Register (GSNPSID). +-

                                                                                +-Read the register into the d32 element then read out the bits using the bit elements.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                typedef union hwcfg1_data hwcfg1_data_t
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This union represents the bit fields in the User HW Config1 Register. +-

                                                                                +-Read the register into the d32 element then read out the bits using the bit elements.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                typedef union hwcfg2_data hwcfg2_data_t
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This union represents the bit fields in the User HW Config2 Register. +-

                                                                                +-Read the register into the d32 element then read out the bits using the bit elements.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                typedef union hwcfg3_data hwcfg3_data_t
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This union represents the bit fields in the User HW Config3 Register. +-

                                                                                +-Read the register into the d32 element then read out the bits using the bit elements.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                typedef union hwcfg4_data hwcfg4_data_t
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This union represents the bit fields in the User HW Config4 Register. +-

                                                                                +-Read the register into the d32 element then read out the bits using the bit elements.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                typedef union glpmctl_data glpmcfg_data_t
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This union represents the bit fields of the Core LPM Configuration Register (GLPMCFG). +-

                                                                                +-Set the bits using bit fields then write the d32 value to the register.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                typedef union adpctl_data adpctl_data_t
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This union represents the bit fields of the Core ADP Timer, Control and Status Register (ADPTIMCTLSTS). +-

                                                                                +-Set the bits using bit fields then write the d32 value to the register.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                typedef struct dwc_otg_dev_global_regs dwc_otg_device_global_regs_t
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Device Global Registers. +-

                                                                                +-Offsets 800h-BFFh

                                                                                +-The following structures define the size and relative field offsets for the Device Mode Registers.

                                                                                +-These registers are visible only in Device mode and must not be accessed in Host mode, as the results are unknown.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                typedef union dcfg_data dcfg_data_t
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This union represents the bit fields in the Device Configuration Register. +-

                                                                                +-Read the register into the d32 member then set/clear the bits using the bit elements. Write the d32 member to the dcfg register.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                typedef union dctl_data dctl_data_t
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This union represents the bit fields in the Device Control Register. +-

                                                                                +-Read the register into the d32 member then set/clear the bits using the bit elements.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                typedef union dsts_data dsts_data_t
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This union represents the bit fields in the Device Status Register. +-

                                                                                +-Read the register into the d32 member then set/clear the bits using the bit elements.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                typedef union diepint_data diepint_data_t
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This union represents the bit fields in the Device IN EP Interrupt Register and the Device IN EP Common Mask Register. +-

                                                                                +-

                                                                                  +-
                                                                                • Read the register into the d32 member then set/clear the bits using the bit elements.
                                                                                +-
                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                typedef union doepint_data doepint_data_t
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This union represents the bit fields in the Device OUT EP Interrupt Registerand Device OUT EP Common Interrupt Mask Register. +-

                                                                                +-

                                                                                  +-
                                                                                • Read the register into the d32 member then set/clear the bits using the bit elements.
                                                                                +-
                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                typedef union daint_data daint_data_t
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This union represents the bit fields in the Device All EP Interrupt and Mask Registers. +-

                                                                                +-

                                                                                  +-
                                                                                • Read the register into the d32 member then set/clear the bits using the bit elements.
                                                                                +-
                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                typedef union dtknq1_data dtknq1_data_t
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This union represents the bit fields in the Device IN Token Queue Read Registers. +-

                                                                                +-

                                                                                  +-
                                                                                • Read the register into the d32 member.
                                                                                • READ-ONLY Register
                                                                                +-
                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                typedef union dthrctl_data dthrctl_data_t
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This union represents Threshold control Register Read and write the register into the d32 member. +-

                                                                                +-

                                                                                  +-
                                                                                • * - READ-WRITABLE Register
                                                                                +-
                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                typedef struct dwc_otg_dev_in_ep_regs dwc_otg_dev_in_ep_regs_t
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Device Logical IN Endpoint-Specific Registers. +-

                                                                                +-Offsets 900h-AFCh

                                                                                +-There will be one set of endpoint registers per logical endpoint implemented.

                                                                                +-These registers are visible only in Device mode and must not be accessed in Host mode, as the results are unknown.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                typedef struct dwc_otg_dev_out_ep_regs dwc_otg_dev_out_ep_regs_t
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Device Logical OUT Endpoint-Specific Registers. +-

                                                                                +-Offsets: B00h-CFCh

                                                                                +-There will be one set of endpoint registers per logical endpoint implemented.

                                                                                +-These registers are visible only in Device mode and must not be accessed in Host mode, as the results are unknown.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                typedef union depctl_data depctl_data_t
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This union represents the bit fields in the Device EP Control Register. +-

                                                                                +-Read the register into the d32 member then set/clear the bits using the bit elements.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                typedef union deptsiz_data deptsiz_data_t
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This union represents the bit fields in the Device EP Transfer Size Register. +-

                                                                                +-Read the register into the d32 member then set/clear the bits using the bit elements.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                typedef union deptsiz0_data deptsiz0_data_t
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This union represents the bit fields in the Device EP 0 Transfer Size Register. +-

                                                                                +-Read the register into the d32 member then set/clear the bits using the bit elements.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                typedef union dev_dma_desc_sts dev_dma_desc_sts_t
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This union represents the bit fields in the DMA Descriptor status quadlet. +-

                                                                                +-Read the quadlet into the d32 member then set/clear the bits using the bit, b_iso_out and b_iso_in elements.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                typedef struct dwc_otg_dev_dma_desc dwc_otg_dev_dma_desc_t
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-DMA Descriptor structure. +-

                                                                                +-DMA Descriptor structure contains two quadlets: Status quadlet and Data buffer pointer.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                typedef struct dwc_otg_dev_if dwc_otg_dev_if_t
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-The dwc_otg_dev_if structure contains information needed to manage the DWC_otg controller acting in device mode. +-

                                                                                +-It represents the programming view of the device-specific aspects of the controller.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                typedef struct dwc_otg_host_global_regs dwc_otg_host_global_regs_t
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-The Host Global Registers structure defines the size and relative field offsets for the Host Mode Global Registers. +-

                                                                                +-Host Global Registers offsets 400h-7FFh.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                typedef union hcfg_data hcfg_data_t
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This union represents the bit fields in the Host Configuration Register. +-

                                                                                +-Read the register into the d32 member then set/clear the bits using the bit elements. Write the d32 member to the hcfg register.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                typedef union hprt0_data hprt0_data_t
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This union represents the bit fields in the Host Port Control and Status Register. +-

                                                                                +-Read the register into the d32 member then set/clear the bits using the bit elements. Write the d32 member to the hprt0 register.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                typedef struct dwc_otg_hc_regs dwc_otg_hc_regs_t
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Host Channel Specific Registers. +-

                                                                                +-500h-5FCh

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                typedef union hcchar_data hcchar_data_t
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This union represents the bit fields in the Host Channel Characteristics Register. +-

                                                                                +-Read the register into the d32 member then set/clear the bits using the bit elements. Write the d32 member to the hcchar register.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                typedef union hcintmsk_data hcintmsk_data_t
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This union represents the bit fields in the Host Channel Interrupt Mask Register. +-

                                                                                +-Read the register into the d32 member then set/clear the bits using the bit elements. Write the d32 member to the hcintmsk register.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                typedef union hctsiz_data hctsiz_data_t
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This union represents the bit fields in the Host Channel Transfer Size Register. +-

                                                                                +-Read the register into the d32 member then set/clear the bits using the bit elements. Write the d32 member to the hcchar register.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                typedef union host_dma_desc_sts host_dma_desc_sts_t
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This union represents the bit fields in the DMA Descriptor status quadlet for host mode. +-

                                                                                +-Read the quadlet into the d32 member then set/clear the bits using the bit elements.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                typedef struct dwc_otg_host_dma_desc dwc_otg_host_dma_desc_t
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Host-mode DMA Descriptor structure. +-

                                                                                +-DMA Descriptor structure contains two quadlets: Status quadlet and Data buffer pointer.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                typedef struct dwc_otg_host_if dwc_otg_host_if_t
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-OTG Host Interface Structure. +-

                                                                                +-The OTG Host Interface Structure structure contains information needed to manage the DWC_otg controller acting in host mode. It represents the programming view of the host-specific aspects of the controller.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                typedef union pcgcctl_data pcgcctl_data_t
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This union represents the bit fields in the Power and Clock Gating Control Register. +-

                                                                                +-Read the register into the d32 member then set/clear the bits using the bit elements.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                typedef union gdfifocfg_data gdfifocfg_data_t
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This union represents the bit fields in the Global Data FIFO Software Configuration Register. +-

                                                                                +-Read the register into the d32 member then set/clear the bits using the bit elements.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                typedef union gpwrdn_data gpwrdn_data_t
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This union represents the bit fields in the Global Power Down Register Register. +-

                                                                                +-Read the register into the d32 member then set/clear the bits using the bit elements.

                                                                                +-

                                                                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/files.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/files.html 2013-07-26 19:34:42.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,42 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: File Index +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver File List

                                                                                Here is a list of all documented files with brief descriptions: +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                dwc_cfi_common.h [code]This file contains the CFI specific common constants, interfaces (functions and macros) and structures for Linux
                                                                                dwc_otg_adp.c [code]This file contains the most of the Attach Detect Protocol implementation for the driver to support OTG Rev2.0
                                                                                dwc_otg_adp.h [code]This file contains the Attach Detect Protocol interfaces and defines (functions) and structures for Linux
                                                                                dwc_otg_attr.c [code]The diagnostic interface will provide access to the controller for bringing up the hardware and testing
                                                                                dwc_otg_attr.h [code]This file contains the interface to the Linux device attributes
                                                                                dwc_otg_cfi.c [code]This file contains the most of the CFI(Core Feature Interface) implementation for the OTG
                                                                                dwc_otg_cfi.h [code]This file contains the CFI related OTG PCD specific common constants, interfaces(functions and macros) and data structures.The CFI Protocol is an optional interface for internal testing purposes that a DUT may implement to support testing of configurable features
                                                                                dwc_otg_cil.c [code]The Core Interface Layer provides basic services for accessing and managing the DWC_otg hardware
                                                                                dwc_otg_cil.h [code]This file contains the interface to the Core Interface Layer
                                                                                dwc_otg_cil_intr.c [code]The Core Interface Layer provides basic services for accessing and managing the DWC_otg hardware
                                                                                dwc_otg_core_if.h [code]This file defines DWC_OTG Core API
                                                                                dwc_otg_dbg.h [code]This file defines debug levels
                                                                                dwc_otg_driver.c [code]The dwc_otg_driver module provides the initialization and cleanup entry points for the DWC_otg driver
                                                                                dwc_otg_driver.h [code]This file contains the interface to the Linux driver
                                                                                dwc_otg_hcd.c [code]This file implements HCD Core
                                                                                dwc_otg_hcd.h [code]This file contains the structures, constants, and interfaces for the Host Contoller Driver (HCD)
                                                                                dwc_otg_hcd_ddma.c [code]This file contains Descriptor DMA support implementation for host mode
                                                                                dwc_otg_hcd_if.h [code]This file defines DWC_OTG HCD Core API
                                                                                dwc_otg_hcd_intr.c [code]This file contains the implementation of the HCD Interrupt handlers
                                                                                dwc_otg_hcd_linux.c [code]This file contains the implementation of the HCD
                                                                                dwc_otg_hcd_queue.c [code]This file contains the functions to manage Queue Heads and Queue Transfer Descriptors
                                                                                dwc_otg_os_dep.h [code]This file contains OS dependent structures
                                                                                dwc_otg_pcd.c [code]This file implements PCD Core
                                                                                dwc_otg_pcd.h [code]This file contains the structures, constants, and interfaces for the Perpherial Contoller Driver (PCD)
                                                                                dwc_otg_pcd_if.h [code]This file defines DWC_OTG PCD Core API
                                                                                dwc_otg_pcd_intr.c [code]This file contains the implementation of the PCD Interrupt handlers
                                                                                dwc_otg_pcd_linux.c [code]This file implements the Peripheral Controller Driver
                                                                                dwc_otg_regs.h [code]This file contains the data structures for accessing the DWC_otg core registers
                                                                                +-
                                                                                Generated on Thu Oct 27 03:56:37 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/functions.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/functions.html 2013-07-26 19:34:42.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,595 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-
                                                                                All | Functions | Variables
                                                                                +-
                                                                                a | b | c | d | e | f | g | h | i | l | m | n | o | p | q | r | s | t | u | w | x
                                                                                +- +-

                                                                                +- +-

                                                                                +-Here is a list of all documented struct and union fields with links to the struct/union documentation for each field:

                                                                                - a -

                                                                                +-

                                                                                - b -

                                                                                +-

                                                                                - c -

                                                                                +-

                                                                                - d -

                                                                                +-

                                                                                - e -

                                                                                +-

                                                                                - f -

                                                                                +-

                                                                                - g -

                                                                                +-

                                                                                - h -

                                                                                +-

                                                                                - i -

                                                                                +-

                                                                                - l -

                                                                                +-

                                                                                - m -

                                                                                +-

                                                                                - n -

                                                                                +-

                                                                                - o -

                                                                                +-

                                                                                - p -

                                                                                +-

                                                                                - q -

                                                                                +-

                                                                                - r -

                                                                                +-

                                                                                - s -

                                                                                +-

                                                                                - t -

                                                                                +-

                                                                                - u -

                                                                                +-

                                                                                - w -

                                                                                +-

                                                                                - x -

                                                                                +-
                                                                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/functions_func.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/functions_func.html 2013-07-26 19:34:42.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,18 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields - Functions +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-
                                                                                All | Functions | Variables
                                                                                +- +-

                                                                                +-

                                                                                +-
                                                                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/functions_vars.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/functions_vars.html 2013-07-26 19:34:42.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,594 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Data Fields - Variables +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-
                                                                                All | Functions | Variables
                                                                                +-
                                                                                a | b | c | d | e | f | g | h | i | l | m | n | o | p | q | r | s | t | u | w | x
                                                                                +- +-

                                                                                +- +-

                                                                                +-

                                                                                - a -

                                                                                +-

                                                                                - b -

                                                                                +-

                                                                                - c -

                                                                                +-

                                                                                - d -

                                                                                +-

                                                                                - e -

                                                                                +-

                                                                                - f -

                                                                                +-

                                                                                - g -

                                                                                +-

                                                                                - h -

                                                                                +-

                                                                                - i -

                                                                                +-

                                                                                - l -

                                                                                +-

                                                                                - m -

                                                                                +-

                                                                                - n -

                                                                                +-

                                                                                - o -

                                                                                +-

                                                                                - p -

                                                                                +-

                                                                                - q -

                                                                                +-

                                                                                - r -

                                                                                +-

                                                                                - s -

                                                                                +-

                                                                                - t -

                                                                                +-

                                                                                - u -

                                                                                +-

                                                                                - w -

                                                                                +-

                                                                                - x -

                                                                                +-
                                                                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/globals.html 2013-07-26 19:34:43.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,680 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Globals +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-
                                                                                All | Functions | Variables | Typedefs | Enumerations | Enumeration values | Defines
                                                                                +-
                                                                                _ | a | b | c | d | e | f | g | h | i | k | m | o | p | q | r | s | u | v | w | x
                                                                                +- +-

                                                                                +- +-

                                                                                +-Here is a list of all documented functions, variables, defines, enums, and typedefs with links to the documentation:

                                                                                - _ -

                                                                                +-

                                                                                - a -

                                                                                +-

                                                                                - b -

                                                                                +-

                                                                                - c -

                                                                                +-

                                                                                - d -

                                                                                +-

                                                                                - e -

                                                                                +-

                                                                                - f -

                                                                                +-

                                                                                - g -

                                                                                +-

                                                                                - h -

                                                                                +-

                                                                                - i -

                                                                                +-

                                                                                - k -

                                                                                +-

                                                                                - m -

                                                                                +-

                                                                                - o -

                                                                                +-

                                                                                - p -

                                                                                +-

                                                                                - q -

                                                                                +-

                                                                                - r -

                                                                                +-

                                                                                - s -

                                                                                +-

                                                                                - u -

                                                                                +-

                                                                                - v -

                                                                                +-

                                                                                - w -

                                                                                +-

                                                                                - x -

                                                                                +-
                                                                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_defs.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/globals_defs.html 2013-07-26 19:34:43.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,89 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Globals - Defines +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-
                                                                                All | Functions | Variables | Typedefs | Enumerations | Enumeration values | Defines
                                                                                +-
                                                                                a | b | c | d | f | g | m | o | r | s | u | v
                                                                                +- +-

                                                                                +- +-

                                                                                +-

                                                                                - a -

                                                                                +-

                                                                                - b -

                                                                                +-

                                                                                - c -

                                                                                +-

                                                                                - d -

                                                                                +-

                                                                                - f -

                                                                                +-

                                                                                - g -

                                                                                +-

                                                                                - m -

                                                                                +-

                                                                                - o -

                                                                                +-

                                                                                - r -

                                                                                +-

                                                                                - s -

                                                                                +-

                                                                                - u -

                                                                                +-

                                                                                - v -

                                                                                +-
                                                                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_enum.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/globals_enum.html 2013-07-26 19:34:43.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,21 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Globals - Enumerations +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-
                                                                                All | Functions | Variables | Typedefs | Enumerations | Enumeration values | Defines
                                                                                +- +-

                                                                                +-

                                                                                +-
                                                                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_eval.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/globals_eval.html 2013-07-26 19:34:43.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,21 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Globals - Enumeration values +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-
                                                                                All | Functions | Variables | Typedefs | Enumerations | Enumeration values | Defines
                                                                                +- +-

                                                                                +-

                                                                                +-
                                                                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_func.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/globals_func.html 2013-07-26 19:34:43.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,522 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Globals - Functions +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-
                                                                                All | Functions | Variables | Typedefs | Enumerations | Enumeration values | Defines
                                                                                +-
                                                                                _ | a | b | c | d | e | f | g | h | i | k | m | p | q | r | s | u | v | w
                                                                                +- +-

                                                                                +- +-

                                                                                +-

                                                                                - _ -

                                                                                +-

                                                                                - a -

                                                                                +-

                                                                                - b -

                                                                                +-

                                                                                - c -

                                                                                +-

                                                                                - d -

                                                                                +-

                                                                                - e -

                                                                                +-

                                                                                - f -

                                                                                +-

                                                                                - g -

                                                                                +-

                                                                                - h -

                                                                                +-

                                                                                - i -

                                                                                +-

                                                                                - k -

                                                                                +-

                                                                                - m -

                                                                                +-

                                                                                - p -

                                                                                +-

                                                                                - q -

                                                                                +-

                                                                                - r -

                                                                                +-

                                                                                - s -

                                                                                +-

                                                                                - u -

                                                                                +-

                                                                                - v -

                                                                                +-

                                                                                - w -

                                                                                +-
                                                                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_type.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/globals_type.html 2013-07-26 19:34:43.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,132 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Globals - Typedefs +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-
                                                                                All | Functions | Variables | Typedefs | Enumerations | Enumeration values | Defines
                                                                                +-
                                                                                a | c | d | e | f | g | h | i | p | x
                                                                                +- +-

                                                                                +- +-

                                                                                +-

                                                                                - a -

                                                                                +-

                                                                                - c -

                                                                                +-

                                                                                - d -

                                                                                +-

                                                                                - e -

                                                                                +-

                                                                                - f -

                                                                                +-

                                                                                - g -

                                                                                +-

                                                                                - h -

                                                                                +-

                                                                                - i -

                                                                                +-

                                                                                - p -

                                                                                +-

                                                                                - x -

                                                                                +-
                                                                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/globals_vars.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/globals_vars.html 2013-07-26 19:34:43.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,22 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Globals - Variables +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-
                                                                                All | Functions | Variables | Typedefs | Enumerations | Enumeration values | Defines
                                                                                +- +-

                                                                                +-

                                                                                +-
                                                                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/index.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/index.html 2013-07-26 19:31:22.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,8 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver +- +- +- +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/linux module attributes.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/linux module attributes.html 2013-07-26 19:34:43.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,131 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-The Linux module attributes feature is used to provide the Linux Diagnostic Interface. These attributes are accessed through sysfs. The diagnostic interface will provide access to the controller for bringing up the hardware and testing.

                                                                                +-The following table shows the attributes. +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                Name Description Access

                                                                                +-

                                                                                mode Returns the current mode: 0 for device mode, 1 for host mode Read

                                                                                +-

                                                                                hnpcapable Gets or sets the "HNP-capable" bit in the Core USB Configuraton Register. Read returns the current value. Read/Write

                                                                                +-

                                                                                srpcapable Gets or sets the "SRP-capable" bit in the Core USB Configuraton Register. Read returns the current value. Read/Write

                                                                                +-

                                                                                hsic_connect Gets or sets the "HSIC-Connect" bit in the GLPMCFG Register. Read returns the current value. Read/Write

                                                                                +-

                                                                                inv_sel_hsic Gets or sets the "Invert Select HSIC" bit in the GLPMFG Register. Read returns the current value. Read/Write

                                                                                +-

                                                                                hnp Initiates the Host Negotiation Protocol. Read returns the status. Read/Write

                                                                                +-

                                                                                srp Initiates the Session Request Protocol. Read returns the status. Read/Write

                                                                                +-

                                                                                buspower Gets or sets the Power State of the bus (0 - Off or 1 - On) Read/Write

                                                                                +-

                                                                                bussuspend Suspends the USB bus. Read/Write

                                                                                +-

                                                                                busconnected Gets the connection status of the bus Read

                                                                                +-

                                                                                gotgctl Gets or sets the Core Control Status Register. Read/Write

                                                                                +-

                                                                                gusbcfg Gets or sets the Core USB Configuration Register Read/Write

                                                                                +-

                                                                                grxfsiz Gets or sets the Receive FIFO Size Register Read/Write

                                                                                +-

                                                                                gnptxfsiz Gets or sets the non-periodic Transmit Size Register Read/Write

                                                                                +-

                                                                                gpvndctl Gets or sets the PHY Vendor Control Register Read/Write

                                                                                +-

                                                                                ggpio Gets the value in the lower 16-bits of the General Purpose IO Register or sets the upper 16 bits. Read/Write

                                                                                +-

                                                                                guid Gets or sets the value of the User ID Register Read/Write

                                                                                +-

                                                                                gsnpsid Gets the value of the Synopsys ID Regester Read

                                                                                +-

                                                                                devspeed Gets or sets the device speed setting in the DCFG register Read/Write

                                                                                +-

                                                                                enumspeed Gets the device enumeration Speed. Read

                                                                                +-

                                                                                hptxfsiz Gets the value of the Host Periodic Transmit FIFO Read

                                                                                +-

                                                                                hprt0 Gets or sets the value in the Host Port Control and Status Register Read/Write

                                                                                +-

                                                                                regoffset Sets the register offset for the next Register Access Read/Write

                                                                                +-

                                                                                regvalue Gets or sets the value of the register at the offset in the regoffset attribute. Read/Write

                                                                                +-

                                                                                remote_wakeup On read, shows the status of Remote Wakeup. On write, initiates a remote wakeup of the host. When bit 0 is 1 and Remote Wakeup is enabled, the Remote Wakeup signalling bit in the Device Control Register is set for 1 milli-second. Read/Write

                                                                                +-

                                                                                rem_wakeup_pwrdn On read, shows the status core - hibernated or not. On write, initiates a remote wakeup of the device from Hibernation. Read/Write

                                                                                +-

                                                                                mode_ch_tim_en This bit is used to enable or disable the host core to wait for 200 PHY clock cycles at the end of Resume to change the opmode signal to the PHY to 00 after Suspend or LPM. Read/Write

                                                                                +-

                                                                                fr_interval On read, shows the value of HFIR Frame Interval. On write, dynamically reload HFIR register during runtime. The application can write a value to this register only after the Port Enable bit of the Host Port Control and Status register (HPRT.PrtEnaPort) has been set Read/Write

                                                                                +-

                                                                                disconnect_us On read, shows the status of disconnect_device_us. On write, sets disconnect_us which causes soft disconnect for 100us. Applicable only for device mode of operation. Read/Write

                                                                                +-

                                                                                regdump Dumps the contents of core registers. Read

                                                                                +-

                                                                                spramdump Dumps the contents of core registers. Read

                                                                                +-

                                                                                hcddump Dumps the current HCD state. Read

                                                                                +-

                                                                                hcd_frrem Shows the average value of the Frame Remaining field in the Host Frame Number/Frame Remaining register when an SOF interrupt occurs. This can be used to determine the average interrupt latency. Also shows the average Frame Remaining value for start_transfer and the "a" and "b" sample points. The "a" and "b" sample points may be used during debugging bto determine how long it takes to execute a section of the HCD code. Read

                                                                                +-

                                                                                rd_reg_test Displays the time required to read the GNPTXFSIZ register many times (the output shows the number of times the register is read). Read

                                                                                +-

                                                                                wr_reg_test Displays the time required to write the GNPTXFSIZ register many times (the output shows the number of times the register is written). Read

                                                                                +-

                                                                                lpm_response Gets or sets lpm_response mode. Applicable only in device mode. Write

                                                                                +-

                                                                                sleep_status Shows sleep status of device. Read

                                                                                +-

                                                                                +-

                                                                                +-Example usage: To get the current mode: cat /sys/devices/lm0/mode

                                                                                +-To power down the USB: echo 0 > /sys/devices/lm0/buspower

                                                                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/main.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/main.html 2013-07-26 19:34:43.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,14 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Main Page +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver Documentation

                                                                                +-

                                                                                +-

                                                                                v2.94a

                                                                                Generated on Thu Oct 27 03:56:37 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/module parameters.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/module parameters.html 2013-07-26 19:34:43.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,231 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-The following parameters may be specified when starting the module. These parameters define how the DWC_otg controller should be configured. Parameter values are passed to the CIL initialization function dwc_otg_cil_init

                                                                                +-Example: modprobe dwc_otg speed=1 otg_cap=1

                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-
                                                                                Parameter NameMeaning

                                                                                +-

                                                                                otg_cap Specifies the OTG capabilities. The driver will automatically detect the value for this parameter if none is specified.
                                                                                  +-
                                                                                • 0: HNP and SRP capable (default, if available)
                                                                                • 1: SRP Only capable
                                                                                • 2: No HNP/SRP capable
                                                                                +-

                                                                                +-

                                                                                dma_enable Specifies whether to use slave or DMA mode for accessing the data FIFOs. The driver will automatically detect the value for this parameter if none is specified.
                                                                                  +-
                                                                                • 0: Slave
                                                                                • 1: DMA (default, if available)
                                                                                +-

                                                                                +-

                                                                                dma_burst_size The DMA Burst size (applicable only for External DMA Mode).
                                                                                  +-
                                                                                • Values: 1, 4, 8 16, 32, 64, 128, 256 (default 32)
                                                                                +-

                                                                                +-

                                                                                speed Specifies the maximum speed of operation in host and device mode. The actual speed depends on the speed of the attached device and the value of phy_type.
                                                                                  +-
                                                                                • 0: High Speed (default)
                                                                                • 1: Full Speed
                                                                                +-

                                                                                +-

                                                                                host_support_fs_ls_low_power Specifies whether low power mode is supported when attached to a Full Speed or Low Speed device in host mode.
                                                                                  +-
                                                                                • 0: Don't support low power mode (default)
                                                                                • 1: Support low power mode
                                                                                +-

                                                                                +-

                                                                                host_ls_low_power_phy_clk Specifies the PHY clock rate in low power mode when connected to a Low Speed device in host mode. This parameter is applicable only if HOST_SUPPORT_FS_LS_LOW_POWER is enabled.
                                                                                  +-
                                                                                • 0: 48 MHz (default)
                                                                                • 1: 6 MHz
                                                                                +-

                                                                                +-

                                                                                enable_dynamic_fifo Specifies whether FIFOs may be resized by the driver software.
                                                                                  +-
                                                                                • 0: Use cC FIFO size parameters
                                                                                • 1: Allow dynamic FIFO sizing (default)
                                                                                +-

                                                                                +-

                                                                                data_fifo_size Total number of 4-byte words in the data FIFO memory. This memory includes the Rx FIFO, non-periodic Tx FIFO, and periodic Tx FIFOs.
                                                                                  +-
                                                                                • Values: 32 to 32768 (default 8192)
                                                                                +-

                                                                                +-Note: The total FIFO memory depth in the FPGA configuration is 8192.

                                                                                +-

                                                                                dev_rx_fifo_size Number of 4-byte words in the Rx FIFO in device mode when dynamic FIFO sizing is enabled.
                                                                                  +-
                                                                                • Values: 16 to 32768 (default 1064)
                                                                                +-

                                                                                +-

                                                                                dev_nperio_tx_fifo_size Number of 4-byte words in the non-periodic Tx FIFO in device mode when dynamic FIFO sizing is enabled.
                                                                                  +-
                                                                                • Values: 16 to 32768 (default 1024)
                                                                                +-

                                                                                +-

                                                                                dev_perio_tx_fifo_size_n (n = 1 to 15) Number of 4-byte words in each of the periodic Tx FIFOs in device mode when dynamic FIFO sizing is enabled.
                                                                                  +-
                                                                                • Values: 4 to 768 (default 256)
                                                                                +-

                                                                                +-

                                                                                host_rx_fifo_size Number of 4-byte words in the Rx FIFO in host mode when dynamic FIFO sizing is enabled.
                                                                                  +-
                                                                                • Values: 16 to 32768 (default 1024)
                                                                                +-

                                                                                +-

                                                                                host_nperio_tx_fifo_size Number of 4-byte words in the non-periodic Tx FIFO in host mode when dynamic FIFO sizing is enabled in the core.
                                                                                  +-
                                                                                • Values: 16 to 32768 (default 1024)
                                                                                +-

                                                                                +-

                                                                                host_perio_tx_fifo_size Number of 4-byte words in the host periodic Tx FIFO when dynamic FIFO sizing is enabled.
                                                                                  +-
                                                                                • Values: 16 to 32768 (default 1024)
                                                                                +-

                                                                                +-

                                                                                max_transfer_size The maximum transfer size supported in bytes.
                                                                                  +-
                                                                                • Values: 2047 to 65,535 (default 65,535)
                                                                                +-

                                                                                +-

                                                                                max_packet_count The maximum number of packets in a transfer.
                                                                                  +-
                                                                                • Values: 15 to 511 (default 511)
                                                                                +-

                                                                                +-

                                                                                host_channels The number of host channel registers to use.
                                                                                  +-
                                                                                • Values: 1 to 16 (default 12)
                                                                                +-

                                                                                +-Note: The FPGA configuration supports a maximum of 12 host channels.

                                                                                +-

                                                                                dev_endpoints The number of endpoints in addition to EP0 available for device mode operations.
                                                                                  +-
                                                                                • Values: 1 to 15 (default 6 IN and OUT)
                                                                                +-

                                                                                +-Note: The FPGA configuration supports a maximum of 6 IN and OUT endpoints in addition to EP0.

                                                                                +-

                                                                                phy_type Specifies the type of PHY interface to use. By default, the driver will automatically detect the phy_type.
                                                                                  +-
                                                                                • 0: Full Speed
                                                                                • 1: UTMI+ (default, if available)
                                                                                • 2: ULPI
                                                                                +-

                                                                                +-

                                                                                phy_utmi_width Specifies the UTMI+ Data Width. This parameter is applicable for a phy_type of UTMI+. Also, this parameter is applicable only if the OTG_HSPHY_WIDTH cC parameter was set to "8 and 16 bits", meaning that the core has been configured to work at either data path width.
                                                                                  +-
                                                                                • Values: 8 or 16 bits (default 16)
                                                                                +-

                                                                                +-

                                                                                phy_ulpi_ddr Specifies whether the ULPI operates at double or single data rate. This parameter is only applicable if phy_type is ULPI.
                                                                                  +-
                                                                                • 0: single data rate ULPI interface with 8 bit wide data bus (default)
                                                                                • 1: double data rate ULPI interface with 4 bit wide data bus
                                                                                +-

                                                                                +-

                                                                                i2c_enable Specifies whether to use the I2C interface for full speed PHY. This parameter is only applicable if PHY_TYPE is FS.
                                                                                  +-
                                                                                • 0: Disabled (default)
                                                                                • 1: Enabled
                                                                                +-

                                                                                +-

                                                                                ulpi_fs_ls Specifies whether to use ULPI FS/LS mode only.
                                                                                  +-
                                                                                • 0: Disabled (default)
                                                                                • 1: Enabled
                                                                                +-

                                                                                +-

                                                                                ts_dline Specifies whether term select D-Line pulsing for all PHYs is enabled.
                                                                                  +-
                                                                                • 0: Disabled (default)
                                                                                • 1: Enabled
                                                                                +-

                                                                                +-

                                                                                en_multiple_tx_fifo Specifies whether dedicatedto tx fifos are enabled for non periodic IN EPs. The driver will automatically detect the value for this parameter if none is specified.
                                                                                  +-
                                                                                • 0: Disabled
                                                                                • 1: Enabled (default, if available)
                                                                                +-

                                                                                +-

                                                                                dev_tx_fifo_size_n (n = 1 to 15) Number of 4-byte words in each of the Tx FIFOs in device mode when dynamic FIFO sizing is enabled.
                                                                                  +-
                                                                                • Values: 4 to 768 (default 256)
                                                                                +-

                                                                                +-

                                                                                tx_thr_length Transmit Threshold length in 32 bit double words
                                                                                  +-
                                                                                • Values: 8 to 128 (default 64)
                                                                                +-

                                                                                +-

                                                                                rx_thr_length Receive Threshold length in 32 bit double words
                                                                                  +-
                                                                                • Values: 8 to 128 (default 64)
                                                                                +-

                                                                                +-

                                                                                thr_ctl Specifies whether to enable Thresholding for Device mode. Bits 0, 1, 2 of this parmater specifies if thresholding is enabled for non-Iso Tx, Iso Tx and Rx transfers accordingly. The driver will automatically detect the value for this parameter if none is specified.
                                                                                  +-
                                                                                • Values: 0 to 7 (default 0) Bit values indicate:
                                                                                • 0: Thresholding disabled
                                                                                • 1: Thresholding enabled
                                                                                +-

                                                                                +-

                                                                                dma_desc_enable Specifies whether to enable Descriptor DMA mode. The driver will automatically detect the value for this parameter if none is specified.
                                                                                  +-
                                                                                • 0: Descriptor DMA disabled
                                                                                • 1: Descriptor DMA (default, if available)
                                                                                +-

                                                                                +-

                                                                                mpi_enable Specifies whether to enable MPI enhancement mode. The driver will automatically detect the value for this parameter if none is specified.
                                                                                  +-
                                                                                • 0: MPI disabled (default)
                                                                                • 1: MPI enable
                                                                                +-

                                                                                +-

                                                                                pti_enable Specifies whether to enable PTI enhancement support. The driver will automatically detect the value for this parameter if none is specified.
                                                                                  +-
                                                                                • 0: PTI disabled (default)
                                                                                • 1: PTI enable
                                                                                +-

                                                                                +-

                                                                                lpm_enable Specifies whether to enable LPM support. The driver will automatically detect the value for this parameter if none is specified.
                                                                                  +-
                                                                                • 0: LPM disabled
                                                                                • 1: LPM enable (default, if available)
                                                                                +-

                                                                                +-

                                                                                ic_usb_cap Specifies whether to enable IC_USB capability. The driver will automatically detect the value for this parameter if none is specified.
                                                                                  +-
                                                                                • 0: IC_USB disabled (default, if available)
                                                                                • 1: IC_USB enable
                                                                                +-

                                                                                +-

                                                                                ahb_thr_ratio Specifies AHB Threshold ratio.
                                                                                  +-
                                                                                • Values: 0 to 3 (default 0)
                                                                                +-

                                                                                +-

                                                                                power_down Specifies Power Down(Hibernation) Mode. The driver will automatically detect the value for this parameter if none is specified.
                                                                                  +-
                                                                                • 0: Power Down disabled (default)
                                                                                • 2: Power Down enabled
                                                                                +-

                                                                                +-

                                                                                reload_ctl Specifies whether dynamic reloading of the HFIR register is allowed during run time. The driver will automatically detect the value for this parameter if none is specified. In case the HFIR value is reloaded when HFIR.RldCtrl == 1'b0 the core might misbehave.
                                                                                  +-
                                                                                • 0: Reload Control disabled (default)
                                                                                • 1: Reload Control enabled
                                                                                +-

                                                                                +-

                                                                                dev_out_nak Specifies whether Device OUT NAK enhancement enabled or no. The driver will automatically detect the value for this parameter if none is specified. This parameter is valid only when OTG_EN_DESC_DMA == 1’b1.
                                                                                  +-
                                                                                • 0: The core does not set NAK after Bulk OUT transfer complete (default)
                                                                                • 1: The core sets NAK after Bulk OUT transfer complete
                                                                                +-

                                                                                +-

                                                                                cont_on_bna Specifies whether Enable Continue on BNA enabled or no. After receiving BNA interrupt the core disables the endpoint,when the endpoint is re-enabled by the application the
                                                                                  +-
                                                                                • 0: Core starts processing from the DOEPDMA descriptor (default)
                                                                                • 1: Core starts processing from the descriptor which received the BNA. This parameter is valid only when OTG_EN_DESC_DMA == 1’b1.
                                                                                +-

                                                                                +-

                                                                                ahb_single This bit when programmed supports SINGLE transfers for remainder data in a transfer for DMA mode of operation.
                                                                                  +-
                                                                                • 0: The remainder data will be sent using INCR burst size (default)
                                                                                • 1: The remainder data will be sent using SINGLE burst size.
                                                                                +-

                                                                                +-

                                                                                adp_enable Specifies whether ADP feature is enabled. The driver will automatically detect the value for this parameter if none is specified.
                                                                                  +-
                                                                                • 0: ADP feature disabled (default)
                                                                                • 1: ADP feature enabled
                                                                                +-

                                                                                +-

                                                                                otg_ver Specifies whether OTG is performing as USB OTG Revision 2.0 or Revision 1.3 USB OTG device.
                                                                                  +-
                                                                                • 0: OTG 2.0 support disabled (default)
                                                                                • 1: OTG 2.0 support enabled
                                                                                +-
                                                                                +-

                                                                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/pages.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/pages.html 2013-07-26 19:34:43.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,20 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Page Index +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver Related Pages

                                                                                Here is a list of all related documentation pages: +-
                                                                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/struct__ddma__align__buffer__setup.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/struct__ddma__align__buffer__setup.html 2013-07-26 19:34:43.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,34 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: _ddma_align_buffer_setup Struct Reference +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                _ddma_align_buffer_setup Struct Reference

                                                                                Descriptor DMA Alignment Buffer setup structure. +-More... +-

                                                                                +-#include <dwc_otg_cfi.h> +-

                                                                                +- +- +- +- +- +- +- +-

                                                                                Data Fields

                                                                                +-uint8_t bEndpointAddress
                                                                                +-uint8_t bAlign
                                                                                +-

                                                                                Detailed Description

                                                                                +-Descriptor DMA Alignment Buffer setup structure. +-

                                                                                +- +-

                                                                                +-Definition at line 116 of file dwc_otg_cfi.h.

                                                                                The documentation for this struct was generated from the following file: +-
                                                                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/struct__ddma__concat__buffer__setup.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/struct__ddma__concat__buffer__setup.html 2013-07-26 19:34:43.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,34 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: _ddma_concat_buffer_setup Struct Reference +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                _ddma_concat_buffer_setup Struct Reference

                                                                                Descriptor DMA Concatenation Buffer setup structure. +-More... +-

                                                                                +-#include <dwc_otg_cfi.h> +-

                                                                                +- +- +- +- +- +- +- +-

                                                                                Data Fields

                                                                                +-ddma_concat_buffer_setup_hdr_t hdr
                                                                                +-uint16_t * wTxBytes
                                                                                +-

                                                                                Detailed Description

                                                                                +-Descriptor DMA Concatenation Buffer setup structure. +-

                                                                                +- +-

                                                                                +-Definition at line 106 of file dwc_otg_cfi.h.

                                                                                The documentation for this struct was generated from the following file: +-
                                                                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/struct__ddma__concat__buffer__setup__hdr.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/struct__ddma__concat__buffer__setup__hdr.html 2013-07-26 19:34:43.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,37 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: _ddma_concat_buffer_setup_hdr Struct Reference +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                _ddma_concat_buffer_setup_hdr Struct Reference

                                                                                Descriptor DMA Concatenation Buffer setup structure. +-More... +-

                                                                                +-#include <dwc_otg_cfi.h> +-

                                                                                +- +- +- +- +- +- +- +- +- +-

                                                                                Data Fields

                                                                                +-uint8_t bEndpointAddress
                                                                                +-uint8_t bDescCount
                                                                                +-uint16_t wSize
                                                                                +-

                                                                                Detailed Description

                                                                                +-Descriptor DMA Concatenation Buffer setup structure. +-

                                                                                +- +-

                                                                                +-Definition at line 94 of file dwc_otg_cfi.h.

                                                                                The documentation for this struct was generated from the following file: +-
                                                                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/struct__ddma__sg__buffer__setup.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/struct__ddma__sg__buffer__setup.html 2013-07-26 19:34:43.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,45 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: _ddma_sg_buffer_setup Struct Reference +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                _ddma_sg_buffer_setup Struct Reference

                                                                                Descriptor DMA SG Buffer setup structure (SG buffer). +-More... +-

                                                                                +-#include <dwc_otg_cfi.h> +-

                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +-

                                                                                Data Fields

                                                                                +-uint8_t bOutEndpointAddress
                                                                                +-uint8_t bInEndpointAddress
                                                                                +-uint8_t bOffset
                                                                                +-uint8_t bCount
                                                                                +-uint16_t wSize
                                                                                +-

                                                                                Detailed Description

                                                                                +-Descriptor DMA SG Buffer setup structure (SG buffer). +-

                                                                                +-This structure is also used for setting up a buffer for Circular DDMA. +-

                                                                                +- +-

                                                                                +-Definition at line 78 of file dwc_otg_cfi.h.

                                                                                The documentation for this struct was generated from the following file: +-
                                                                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/struct__rx__fifo__size__setup.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/struct__rx__fifo__size__setup.html 2013-07-26 19:34:43.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,31 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: _rx_fifo_size_setup Struct Reference +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                _rx_fifo_size_setup Struct Reference

                                                                                Transmit FIFO Size setup structure. +-More... +-

                                                                                +-#include <dwc_otg_cfi.h> +-

                                                                                +- +- +- +- +- +-

                                                                                Data Fields

                                                                                +-uint16_t wDepth
                                                                                +-

                                                                                Detailed Description

                                                                                +-Transmit FIFO Size setup structure. +-

                                                                                +- +-

                                                                                +-Definition at line 131 of file dwc_otg_cfi.h.

                                                                                The documentation for this struct was generated from the following file: +-
                                                                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/struct__tx__fifo__size__setup.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/struct__tx__fifo__size__setup.html 2013-07-26 19:34:43.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,34 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: _tx_fifo_size_setup Struct Reference +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                _tx_fifo_size_setup Struct Reference

                                                                                Transmit FIFO Size setup structure. +-More... +-

                                                                                +-#include <dwc_otg_cfi.h> +-

                                                                                +- +- +- +- +- +- +- +-

                                                                                Data Fields

                                                                                +-uint8_t bEndpointAddress
                                                                                +-uint16_t wDepth
                                                                                +-

                                                                                Detailed Description

                                                                                +-Transmit FIFO Size setup structure. +-

                                                                                +- +-

                                                                                +-Definition at line 124 of file dwc_otg_cfi.h.

                                                                                The documentation for this struct was generated from the following file: +-
                                                                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structcfi__all__features__header.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/structcfi__all__features__header.html 2013-07-26 19:34:43.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,71 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: cfi_all_features_header Struct Reference +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                cfi_all_features_header Struct Reference

                                                                                This structure is the header of the Core Features dataset returned to the Host. +-More... +-

                                                                                +-#include <dwc_cfi_common.h> +-

                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-

                                                                                Data Fields

                                                                                +-uint16_t wTotalLen
                                                                                 The total length of the features dataset returned to the Host.
                                                                                uint16_t wVersion
                                                                                 CFI version number inBinary-Coded Decimal (i.e., 1.00 is 100H).
                                                                                +-uint16_t wCoreID
                                                                                 The ID of the Core.
                                                                                +-uint16_t wNumFeatures
                                                                                 Number of features returned by VEN_CORE_GET_FEATURES request.
                                                                                +-

                                                                                Detailed Description

                                                                                +-This structure is the header of the Core Features dataset returned to the Host. +-

                                                                                +- +-

                                                                                +-Definition at line 69 of file dwc_cfi_common.h.

                                                                                Field Documentation

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                uint16_t cfi_all_features_header::wVersion
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-CFI version number inBinary-Coded Decimal (i.e., 1.00 is 100H). +-

                                                                                +-This field identifies the version of the CFI Specification with which the device is compliant. +-

                                                                                +-Definition at line 82 of file dwc_cfi_common.h.

                                                                                +-

                                                                                The documentation for this struct was generated from the following file: +-
                                                                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structcfi__ep.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/structcfi__ep.html 2013-07-26 19:34:43.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,57 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: cfi_ep Struct Reference +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                cfi_ep Struct Reference

                                                                                The CFI wrapper of the enabled and activated dwc_otg_pcd_ep structures. +-More... +-

                                                                                +-#include <dwc_otg_cfi.h> +-

                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-

                                                                                Data Fields

                                                                                +-dwc_list_link_t lh
                                                                                +-dwc_otg_pcd_ep * ep
                                                                                +-dwc_otg_dma_desc * dma_desc_last
                                                                                +-ddma_sg_buffer_setup_t * bm_sg
                                                                                +-ddma_sg_buffer_setup_t * bm_circ
                                                                                +-ddma_concat_buffer_setup_t * bm_concat
                                                                                +-ddma_align_buffer_setup_t * bm_align
                                                                                +-uint32_t xfer_len
                                                                                +-uint32_t desc_count
                                                                                +-

                                                                                Detailed Description

                                                                                +-The CFI wrapper of the enabled and activated dwc_otg_pcd_ep structures. +-

                                                                                +-This structure is used to store the buffer setup data for any enabled endpoint in the PCD. +-

                                                                                +- +-

                                                                                +-Definition at line 157 of file dwc_otg_cfi.h.

                                                                                The documentation for this struct was generated from the following file: +-
                                                                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structcfi__feature__desc__header.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/structcfi__feature__desc__header.html 2013-07-26 19:34:43.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,48 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: cfi_feature_desc_header Struct Reference +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                cfi_feature_desc_header Struct Reference

                                                                                This structure is a header of the Core Feature descriptor dataset returned to the Host after the VEN_CORE_GET_FEATURES request. +-More... +-

                                                                                +-#include <dwc_cfi_common.h> +-

                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-

                                                                                Data Fields

                                                                                +-uint16_t wFeatureID
                                                                                 The feature ID.
                                                                                +-uint16_t wLength
                                                                                 Length of this feature descriptor in bytes - including the length of the feature name string.
                                                                                +-uint16_t wDataLength
                                                                                 The data length of this feature in bytes.
                                                                                +-uint8_t bmAttributes
                                                                                 Attributes of this features D0: Access rights 0 - Read/Write 1 - Read only.
                                                                                +-uint8_t bNameLen
                                                                                 Length of the feature name in bytes.
                                                                                +-

                                                                                Detailed Description

                                                                                +-This structure is a header of the Core Feature descriptor dataset returned to the Host after the VEN_CORE_GET_FEATURES request. +-

                                                                                +- +-

                                                                                +-Definition at line 99 of file dwc_cfi_common.h.

                                                                                The documentation for this struct was generated from the following file: +-
                                                                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structcfi__ops.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/structcfi__ops.html 2013-07-26 19:34:43.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,52 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: cfi_ops Struct Reference +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                cfi_ops Struct Reference

                                                                                This is the interface for the CFI operations. +-More... +-

                                                                                +-#include <dwc_otg_cfi.h> +-

                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +-

                                                                                Data Fields

                                                                                +-int(* ep_enable )(struct cfiobject *cfi, struct dwc_otg_pcd *pcd, struct dwc_otg_pcd_ep *ep)
                                                                                +-void *(* ep_alloc_buf )(struct cfiobject *cfi, struct dwc_otg_pcd *pcd, struct dwc_otg_pcd_ep *ep, dma_addr_t *dma, unsigned size, gfp_t flags)
                                                                                +-void(* release )(struct cfiobject *cfi)
                                                                                +-int(* ctrl_write_complete )(struct cfiobject *cfi, struct dwc_otg_pcd *pcd)
                                                                                +-void(* build_descriptors )(struct cfiobject *cfi, struct dwc_otg_pcd *pcd, struct dwc_otg_pcd_ep *ep, dwc_otg_pcd_request_t *req)
                                                                                +-

                                                                                Detailed Description

                                                                                +-This is the interface for the CFI operations. +-

                                                                                +-

                                                                                Parameters:
                                                                                +- +- +- +- +-
                                                                                ep_enable Called when any endpoint is enabled and activated.
                                                                                release Called when the CFI object is released and it needs to correctly deallocate the dynamic memory
                                                                                ctrl_write_complete Called when the data stage of the request is complete
                                                                                +-
                                                                                +- +-

                                                                                +- +-

                                                                                +-Definition at line 200 of file dwc_otg_cfi.h.

                                                                                The documentation for this struct was generated from the following file: +-
                                                                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structcfi__string.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/structcfi__string.html 2013-07-26 19:34:43.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,36 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: cfi_string Struct Reference +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                cfi_string Struct Reference

                                                                                This structure describes a NULL terminated string referenced by its id field. +-More... +-

                                                                                +-#include <dwc_cfi_common.h> +-

                                                                                +- +- +- +- +- +- +- +-

                                                                                Data Fields

                                                                                +-uint16_t id
                                                                                +-const uint8_t * s
                                                                                +-

                                                                                Detailed Description

                                                                                +-This structure describes a NULL terminated string referenced by its id field. +-

                                                                                +-It is very similar to usb_string structure but has the id field type set to 16-bit. +-

                                                                                +- +-

                                                                                +-Definition at line 136 of file dwc_cfi_common.h.

                                                                                The documentation for this struct was generated from the following file: +-
                                                                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structcfi__usb__ctrlrequest.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/structcfi__usb__ctrlrequest.html 2013-07-26 19:34:43.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,46 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: cfi_usb_ctrlrequest Struct Reference +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                cfi_usb_ctrlrequest Struct Reference

                                                                                struct cfi_usb_ctrlrequest - the CFI implementation of the struct usb_ctrlrequest This structure encapsulates the standard usb_ctrlrequest and adds a pointer to the data returned in the data stage of a 3-stage Control Write requests. +-More... +-

                                                                                +-#include <dwc_otg_cfi.h> +-

                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-

                                                                                Data Fields

                                                                                +-uint8_t bRequestType
                                                                                +-uint8_t bRequest
                                                                                +-uint16_t wValue
                                                                                +-uint16_t wIndex
                                                                                +-uint16_t wLength
                                                                                +-uint8_t * data
                                                                                +-

                                                                                Detailed Description

                                                                                +-struct cfi_usb_ctrlrequest - the CFI implementation of the struct usb_ctrlrequest This structure encapsulates the standard usb_ctrlrequest and adds a pointer to the data returned in the data stage of a 3-stage Control Write requests. +-

                                                                                +- +-

                                                                                +-Definition at line 141 of file dwc_otg_cfi.h.

                                                                                The documentation for this struct was generated from the following file: +-
                                                                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structdwc__ep.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/structdwc__ep.html 2013-07-26 19:34:43.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,241 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_ep Struct Reference +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                dwc_ep Struct Reference

                                                                                The dwc_ep structure represents the state of a single endpoint when acting in device mode. +-More... +-

                                                                                +-#include <dwc_otg_cil.h> +-

                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-

                                                                                Data Fields

                                                                                +-uint8_t num
                                                                                 EP number used for register address lookup.
                                                                                +-unsigned is_in:1
                                                                                 EP direction 0 = OUT.
                                                                                +-unsigned active:1
                                                                                 EP active.
                                                                                unsigned tx_fifo_num:4
                                                                                 Periodic Tx FIFO # for IN EPs For INTR EP set to 0 to use non-periodic Tx FIFO.
                                                                                +-unsigned type:2
                                                                                 EP type: 0 - Control, 1 - ISOC, 2 - BULK, 3 - INTR.
                                                                                +-unsigned data_pid_start:1
                                                                                 DATA start PID for INTR and BULK EP.
                                                                                +-unsigned even_odd_frame:1
                                                                                 Frame (even/odd) for ISOC EP.
                                                                                +-unsigned maxpacket:11
                                                                                 Max Packet bytes.
                                                                                +-uint32_t maxxfer
                                                                                 Max Transfer size.
                                                                                Transfer state
                                                                                dwc_dma_t dma_addr
                                                                                 Pointer to the beginning of the transfer buffer -- do not modify during transfer.
                                                                                +-dwc_dma_t dma_desc_addr
                                                                                +-dwc_otg_dev_dma_desc_t * desc_addr
                                                                                +-uint8_t * start_xfer_buff
                                                                                +-uint8_t * xfer_buff
                                                                                 pointer to the transfer buffer
                                                                                +-unsigned xfer_len:19
                                                                                 Number of bytes to transfer.
                                                                                +-unsigned xfer_count:19
                                                                                 Number of bytes transferred.
                                                                                +-unsigned sent_zlp:1
                                                                                 Sent ZLP.
                                                                                +-unsigned total_len:19
                                                                                 Total len for control transfer.
                                                                                +-unsigned stall_clear_flag:1
                                                                                 stall clear flag
                                                                                +-uint32_t desc_cnt
                                                                                 Allocated DMA Desc count.
                                                                                +-uint32_t bInterval
                                                                                 bInterval
                                                                                +-uint32_t frame_num
                                                                                 Next frame num to setup next ISOC transfer.
                                                                                +-uint8_t frm_overrun
                                                                                 Indicates SOF number overrun in DSTS.
                                                                                +-dwc_dma_t dma_addr0
                                                                                 DMA addresses of ISOC buffers.
                                                                                +-dwc_dma_t dma_addr1
                                                                                +-dwc_dma_t iso_dma_desc_addr
                                                                                +-dwc_otg_dev_dma_desc_t * iso_desc_addr
                                                                                +-uint8_t * xfer_buff0
                                                                                 pointer to the transfer buffers
                                                                                +-uint8_t * xfer_buff1
                                                                                +-uint32_t proc_buf_num
                                                                                 number of ISOC Buffer is processing
                                                                                +-uint32_t buf_proc_intrvl
                                                                                 Interval of ISOC Buffer processing.
                                                                                +-uint32_t data_per_frame
                                                                                 Data size for regular frame.
                                                                                +-uint32_t data_pattern_frame
                                                                                 Data size for pattern frame.
                                                                                +-uint32_t sync_frame
                                                                                 Frame number of pattern data.
                                                                                +-uint32_t pkt_per_frm
                                                                                 ISO Packet number per frame.
                                                                                +-uint32_t next_frame
                                                                                 Next frame num for which will be setup DMA Desc.
                                                                                +-uint32_t pkt_cnt
                                                                                 Number of packets per buffer processing.
                                                                                +-iso_pkt_info_t * pkt_info
                                                                                 Info for all isoc packets.
                                                                                +-uint32_t cur_pkt
                                                                                 current pkt number
                                                                                +-uint8_t * cur_pkt_addr
                                                                                 current pkt number
                                                                                +-uint32_t cur_pkt_dma_addr
                                                                                 current pkt number
                                                                                +-

                                                                                Detailed Description

                                                                                +-The dwc_ep structure represents the state of a single endpoint when acting in device mode. +-

                                                                                +-It contains the data items needed for an endpoint to be activated and transfer packets. +-

                                                                                +- +-

                                                                                +-Definition at line 92 of file dwc_otg_cil.h.

                                                                                Field Documentation

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                unsigned dwc_ep::tx_fifo_num
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Periodic Tx FIFO # for IN EPs For INTR EP set to 0 to use non-periodic Tx FIFO. +-

                                                                                +-If dedicated Tx FIFOs are enabled Tx FIFO # FOR IN EPs +-

                                                                                +-Definition at line 103 of file dwc_otg_cil.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                dwc_dma_t dwc_ep::dma_addr
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Pointer to the beginning of the transfer buffer -- do not modify during transfer. +-

                                                                                +- +-

                                                                                +-Definition at line 129 of file dwc_otg_cil.h.

                                                                                +-

                                                                                The documentation for this struct was generated from the following file: +-
                                                                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structdwc__hc.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/structdwc__hc.html 2013-07-26 19:34:43.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,535 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_hc Struct Reference +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                dwc_hc Struct Reference

                                                                                Host channel descriptor. +-More... +-

                                                                                +-#include <dwc_otg_cil.h> +-

                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-

                                                                                Public Member Functions

                                                                                +- DWC_CIRCLEQ_ENTRY (dwc_hc) hc_list_entry
                                                                                 Entry in list of host channels.

                                                                                Data Fields

                                                                                +-uint8_t hc_num
                                                                                 Host channel number used for register address lookup.
                                                                                +-unsigned dev_addr:7
                                                                                 Device to access.
                                                                                +-unsigned ep_num:4
                                                                                 EP to access.
                                                                                unsigned ep_is_in:1
                                                                                 EP direction.
                                                                                unsigned speed:2
                                                                                 EP speed.
                                                                                unsigned ep_type:2
                                                                                 Endpoint type.
                                                                                +-unsigned max_packet:11
                                                                                 Max packet size in bytes.
                                                                                unsigned data_pid_start:2
                                                                                 PID for initial transaction.
                                                                                +-unsigned multi_count:2
                                                                                 Number of periodic transactions per (micro)frame.
                                                                                Transfer State
                                                                                +-uint8_t * xfer_buff
                                                                                 Pointer to the current transfer buffer position.
                                                                                dwc_dma_t align_buff
                                                                                 In Buffer DMA mode this buffer will be used if xfer_buff is not DWORD aligned.
                                                                                +-uint32_t xfer_len
                                                                                 Total number of bytes to transfer.
                                                                                +-uint32_t xfer_count
                                                                                 Number of bytes transferred so far.
                                                                                +-uint16_t start_pkt_count
                                                                                 Packet count at start of transfer.
                                                                                uint8_t xfer_started
                                                                                 Flag to indicate whether the transfer has been started.
                                                                                uint8_t do_ping
                                                                                 Set to 1 to indicate that a PING request should be issued on this channel.
                                                                                uint8_t error_state
                                                                                 Set to 1 to indicate that the error count for this transaction is non-zero.
                                                                                uint8_t halt_on_queue
                                                                                 Set to 1 to indicate that this channel should be halted the next time a request is queued for the channel.
                                                                                uint8_t halt_pending
                                                                                 Set to 1 if the host channel has been halted, but the core is not finished flushing queued requests.
                                                                                dwc_otg_halt_status_e halt_status
                                                                                 Reason for halting the host channel.
                                                                                +-uint8_t do_split
                                                                                 Enable split for the channel.
                                                                                +-uint8_t complete_split
                                                                                 Enable complete split.
                                                                                +-uint8_t hub_addr
                                                                                 Address of high speed hub.
                                                                                +-uint8_t port_addr
                                                                                 Port of the low/full speed device.
                                                                                uint8_t xact_pos
                                                                                 Split transaction position One of the following values: DWC_HCSPLIT_XACTPOS_MID DWC_HCSPLIT_XACTPOS_BEGIN DWC_HCSPLIT_XACTPOS_END DWC_HCSPLIT_XACTPOS_ALL.
                                                                                +-uint8_t short_read
                                                                                 Set when the host channel does a short read.
                                                                                uint8_t requests
                                                                                 Number of requests issued for this channel since it was assigned to the current transfer (not counting PINGs).
                                                                                dwc_otg_qh * qh
                                                                                 Queue Head for the transfer being processed by this channel.
                                                                                Descriptor DMA support
                                                                                +-uint16_t ntd
                                                                                 Number of Transfer Descriptors.
                                                                                +-dwc_dma_t desc_list_addr
                                                                                 Descriptor List DMA address.
                                                                                +-uint8_t schinfo
                                                                                 Scheduling micro-frame bitmap.
                                                                                +-

                                                                                Detailed Description

                                                                                +-Host channel descriptor. +-

                                                                                +-This structure represents the state of a single host channel when acting in host mode. It contains the data items needed to transfer packets to an endpoint via a host channel. +-

                                                                                +- +-

                                                                                +-Definition at line 260 of file dwc_otg_cil.h.

                                                                                Field Documentation

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                unsigned dwc_hc::ep_is_in
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-EP direction. +-

                                                                                +-0: OUT, 1: IN +-

                                                                                +-Definition at line 271 of file dwc_otg_cil.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                unsigned dwc_hc::speed
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-EP speed. +-

                                                                                +-One of the following values:

                                                                                  +-
                                                                                • DWC_OTG_EP_SPEED_LOW
                                                                                • DWC_OTG_EP_SPEED_FULL
                                                                                • DWC_OTG_EP_SPEED_HIGH
                                                                                +- +-

                                                                                +-Definition at line 280 of file dwc_otg_cil.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                unsigned dwc_hc::ep_type
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Endpoint type. +-

                                                                                +-One of the following values:

                                                                                  +-
                                                                                • DWC_OTG_EP_TYPE_CONTROL: 0
                                                                                • DWC_OTG_EP_TYPE_ISOC: 1
                                                                                • DWC_OTG_EP_TYPE_BULK: 2
                                                                                • DWC_OTG_EP_TYPE_INTR: 3
                                                                                +- +-

                                                                                +-Definition at line 293 of file dwc_otg_cil.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                unsigned dwc_hc::data_pid_start
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-PID for initial transaction. +-

                                                                                +-0: DATA0,
                                                                                +- 1: DATA2,
                                                                                +- 2: DATA1,
                                                                                +- 3: MDATA (non-Control EP), SETUP (Control EP) +-

                                                                                +-Definition at line 306 of file dwc_otg_cil.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                dwc_dma_t dwc_hc::align_buff
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-In Buffer DMA mode this buffer will be used if xfer_buff is not DWORD aligned. +-

                                                                                +- +-

                                                                                +-Definition at line 325 of file dwc_otg_cil.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                uint8_t dwc_hc::xfer_started
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Flag to indicate whether the transfer has been started. +-

                                                                                +-Set to 1 if it has been started, 0 otherwise. +-

                                                                                +-Definition at line 337 of file dwc_otg_cil.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                uint8_t dwc_hc::do_ping
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Set to 1 to indicate that a PING request should be issued on this channel. +-

                                                                                +-If 0, process normally. +-

                                                                                +-Definition at line 343 of file dwc_otg_cil.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                uint8_t dwc_hc::error_state
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Set to 1 to indicate that the error count for this transaction is non-zero. +-

                                                                                +-Set to 0 if the error count is 0. +-

                                                                                +-Definition at line 349 of file dwc_otg_cil.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                uint8_t dwc_hc::halt_on_queue
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Set to 1 to indicate that this channel should be halted the next time a request is queued for the channel. +-

                                                                                +-This is necessary in slave mode if no request queue space is available when an attempt is made to halt the channel. +-

                                                                                +-Definition at line 357 of file dwc_otg_cil.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                uint8_t dwc_hc::halt_pending
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Set to 1 if the host channel has been halted, but the core is not finished flushing queued requests. +-

                                                                                +-Otherwise 0. +-

                                                                                +-Definition at line 363 of file dwc_otg_cil.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                dwc_otg_halt_status_e dwc_hc::halt_status
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Reason for halting the host channel. +-

                                                                                +- +-

                                                                                +-Definition at line 368 of file dwc_otg_cil.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                uint8_t dwc_hc::xact_pos
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Split transaction position One of the following values: DWC_HCSPLIT_XACTPOS_MID DWC_HCSPLIT_XACTPOS_BEGIN DWC_HCSPLIT_XACTPOS_END DWC_HCSPLIT_XACTPOS_ALL. +-

                                                                                +-

                                                                                  +-
                                                                                • * - * - * -
                                                                                +- +-

                                                                                +-Definition at line 384 of file dwc_otg_cil.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                uint8_t dwc_hc::requests
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Number of requests issued for this channel since it was assigned to the current transfer (not counting PINGs). +-

                                                                                +- +-

                                                                                +-Definition at line 393 of file dwc_otg_cil.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                struct dwc_otg_qh* dwc_hc::qh
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Queue Head for the transfer being processed by this channel. +-

                                                                                +- +-

                                                                                +-Definition at line 398 of file dwc_otg_cil.h.

                                                                                +-

                                                                                The documentation for this struct was generated from the following file: +-
                                                                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__cil__callbacks.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__cil__callbacks.html 2013-07-26 19:34:43.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,58 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_cil_callbacks Struct Reference +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                dwc_otg_cil_callbacks Struct Reference

                                                                                DWC_otg CIL callback structure. +-More... +-

                                                                                +-#include <dwc_otg_cil.h> +-

                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-

                                                                                Data Fields

                                                                                +-int(* start )(void *_p)
                                                                                 Start function for role change.
                                                                                +-int(* stop )(void *_p)
                                                                                 Stop Function for role change.
                                                                                +-int(* disconnect )(void *_p)
                                                                                 Disconnect Function for role change.
                                                                                +-int(* resume_wakeup )(void *_p)
                                                                                 Resume/Remote wakeup Function.
                                                                                +-int(* suspend )(void *_p)
                                                                                 Suspend function.
                                                                                +-int(* session_start )(void *_p)
                                                                                 Session Start (SRP).
                                                                                +-void * p
                                                                                 Pointer passed to start() and stop().
                                                                                +-

                                                                                Detailed Description

                                                                                +-DWC_otg CIL callback structure. +-

                                                                                +-This structure allows the HCD and PCD to register functions used for starting and stopping the PCD and HCD for role change on for a DRD. +-

                                                                                +- +-

                                                                                +-Definition at line 1307 of file dwc_otg_cil.h.

                                                                                The documentation for this struct was generated from the following file: +-
                                                                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__core__global__regs.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__core__global__regs.html 2013-07-26 19:34:43.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,741 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_core_global_regs Struct Reference +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                dwc_otg_core_global_regs Struct Reference

                                                                                DWC_otg Core registers . +-More... +-

                                                                                +-#include <dwc_otg_regs.h> +-

                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-

                                                                                Data Fields

                                                                                volatile uint32_t gotgctl
                                                                                 OTG Control and Status Register.
                                                                                volatile uint32_t gotgint
                                                                                 OTG Interrupt Register.
                                                                                volatile uint32_t gahbcfg
                                                                                 Core AHB Configuration Register.
                                                                                volatile uint32_t gusbcfg
                                                                                 Core USB Configuration Register.
                                                                                volatile uint32_t grstctl
                                                                                 Core Reset Register.
                                                                                volatile uint32_t gintsts
                                                                                 Core Interrupt Register.
                                                                                volatile uint32_t gintmsk
                                                                                 Core Interrupt Mask Register.
                                                                                volatile uint32_t grxstsr
                                                                                 Receive Status Queue Read Register (Read Only).
                                                                                volatile uint32_t grxstsp
                                                                                 Receive Status Queue Read & POP Register (Read Only).
                                                                                volatile uint32_t grxfsiz
                                                                                 Receive FIFO Size Register.
                                                                                volatile uint32_t gnptxfsiz
                                                                                 Non Periodic Transmit FIFO Size Register.
                                                                                volatile uint32_t gnptxsts
                                                                                 Non Periodic Transmit FIFO/Queue Status Register (Read Only).
                                                                                volatile uint32_t gi2cctl
                                                                                 I2C Access Register.
                                                                                volatile uint32_t gpvndctl
                                                                                 PHY Vendor Control Register.
                                                                                volatile uint32_t ggpio
                                                                                 General Purpose Input/Output Register.
                                                                                volatile uint32_t guid
                                                                                 User ID Register.
                                                                                volatile uint32_t gsnpsid
                                                                                 Synopsys ID Register (Read Only).
                                                                                volatile uint32_t ghwcfg1
                                                                                 User HW Config1 Register (Read Only).
                                                                                volatile uint32_t ghwcfg2
                                                                                 User HW Config2 Register (Read Only).
                                                                                volatile uint32_t ghwcfg3
                                                                                 User HW Config3 Register (Read Only).
                                                                                volatile uint32_t ghwcfg4
                                                                                 User HW Config4 Register (Read Only).
                                                                                +-volatile uint32_t glpmcfg
                                                                                 Core LPM Configuration register Offset: 054h.
                                                                                +-volatile uint32_t gpwrdn
                                                                                 Global PowerDn Register Offset: 058h.
                                                                                +-volatile uint32_t gdfifocfg
                                                                                 Global DFIFO SW Config Register Offset: 05Ch.
                                                                                +-volatile uint32_t adpctl
                                                                                 ADP Control Register Offset: 060h.
                                                                                +-volatile uint32_t reserved39 [39]
                                                                                 Reserved Offset: 064h-0FFh.
                                                                                volatile uint32_t hptxfsiz
                                                                                 Host Periodic Transmit FIFO Size Register.
                                                                                volatile uint32_t dtxfsiz [15]
                                                                                 Device Periodic Transmit FIFO#n Register if dedicated fifos are disabled, otherwise Device Transmit FIFO#n Register.
                                                                                +-

                                                                                Detailed Description

                                                                                +-DWC_otg Core registers . +-

                                                                                +-The dwc_otg_core_global_regs structure defines the size and relative field offsets for the Core Global registers. +-

                                                                                +- +-

                                                                                +-Definition at line 71 of file dwc_otg_regs.h.

                                                                                Field Documentation

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                volatile uint32_t dwc_otg_core_global_regs::gotgctl
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-OTG Control and Status Register. +-

                                                                                +-Offset: 000h +-

                                                                                +-Definition at line 73 of file dwc_otg_regs.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                volatile uint32_t dwc_otg_core_global_regs::gotgint
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-OTG Interrupt Register. +-

                                                                                +-Offset: 004h +-

                                                                                +-Definition at line 75 of file dwc_otg_regs.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                volatile uint32_t dwc_otg_core_global_regs::gahbcfg
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Core AHB Configuration Register. +-

                                                                                +-Offset: 008h +-

                                                                                +-Definition at line 77 of file dwc_otg_regs.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                volatile uint32_t dwc_otg_core_global_regs::gusbcfg
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Core USB Configuration Register. +-

                                                                                +-Offset: 00Ch +-

                                                                                +-Definition at line 87 of file dwc_otg_regs.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                volatile uint32_t dwc_otg_core_global_regs::grstctl
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Core Reset Register. +-

                                                                                +-Offset: 010h +-

                                                                                +-Definition at line 89 of file dwc_otg_regs.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                volatile uint32_t dwc_otg_core_global_regs::gintsts
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Core Interrupt Register. +-

                                                                                +-Offset: 014h +-

                                                                                +-Definition at line 91 of file dwc_otg_regs.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                volatile uint32_t dwc_otg_core_global_regs::gintmsk
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Core Interrupt Mask Register. +-

                                                                                +-Offset: 018h +-

                                                                                +-Definition at line 93 of file dwc_otg_regs.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                volatile uint32_t dwc_otg_core_global_regs::grxstsr
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Receive Status Queue Read Register (Read Only). +-

                                                                                +-Offset: 01Ch +-

                                                                                +-Definition at line 95 of file dwc_otg_regs.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                volatile uint32_t dwc_otg_core_global_regs::grxstsp
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Receive Status Queue Read & POP Register (Read Only). +-

                                                                                +-Offset: 020h +-

                                                                                +-Definition at line 97 of file dwc_otg_regs.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                volatile uint32_t dwc_otg_core_global_regs::grxfsiz
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Receive FIFO Size Register. +-

                                                                                +-Offset: 024h +-

                                                                                +-Definition at line 99 of file dwc_otg_regs.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                volatile uint32_t dwc_otg_core_global_regs::gnptxfsiz
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Non Periodic Transmit FIFO Size Register. +-

                                                                                +-Offset: 028h +-

                                                                                +-Definition at line 101 of file dwc_otg_regs.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                volatile uint32_t dwc_otg_core_global_regs::gnptxsts
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Non Periodic Transmit FIFO/Queue Status Register (Read Only). +-

                                                                                +-Offset: 02Ch +-

                                                                                +-Definition at line 104 of file dwc_otg_regs.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                volatile uint32_t dwc_otg_core_global_regs::gi2cctl
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-I2C Access Register. +-

                                                                                +-Offset: 030h +-

                                                                                +-Definition at line 106 of file dwc_otg_regs.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                volatile uint32_t dwc_otg_core_global_regs::gpvndctl
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-PHY Vendor Control Register. +-

                                                                                +-Offset: 034h +-

                                                                                +-Definition at line 108 of file dwc_otg_regs.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                volatile uint32_t dwc_otg_core_global_regs::ggpio
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-General Purpose Input/Output Register. +-

                                                                                +-Offset: 038h +-

                                                                                +-Definition at line 110 of file dwc_otg_regs.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                volatile uint32_t dwc_otg_core_global_regs::guid
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-User ID Register. +-

                                                                                +-Offset: 03Ch +-

                                                                                +-Definition at line 112 of file dwc_otg_regs.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                volatile uint32_t dwc_otg_core_global_regs::gsnpsid
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Synopsys ID Register (Read Only). +-

                                                                                +-Offset: 040h +-

                                                                                +-Definition at line 114 of file dwc_otg_regs.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                volatile uint32_t dwc_otg_core_global_regs::ghwcfg1
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-User HW Config1 Register (Read Only). +-

                                                                                +-Offset: 044h +-

                                                                                +-Definition at line 116 of file dwc_otg_regs.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                volatile uint32_t dwc_otg_core_global_regs::ghwcfg2
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-User HW Config2 Register (Read Only). +-

                                                                                +-Offset: 048h +-

                                                                                +-Definition at line 118 of file dwc_otg_regs.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                volatile uint32_t dwc_otg_core_global_regs::ghwcfg3
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-User HW Config3 Register (Read Only). +-

                                                                                +-Offset: 04Ch +-

                                                                                +-Definition at line 132 of file dwc_otg_regs.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                volatile uint32_t dwc_otg_core_global_regs::ghwcfg4
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-User HW Config4 Register (Read Only). +-

                                                                                +-Offset: 050h +-

                                                                                +-Definition at line 134 of file dwc_otg_regs.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                volatile uint32_t dwc_otg_core_global_regs::hptxfsiz
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Host Periodic Transmit FIFO Size Register. +-

                                                                                +-Offset: 100h +-

                                                                                +-Definition at line 146 of file dwc_otg_regs.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                volatile uint32_t dwc_otg_core_global_regs::dtxfsiz[15]
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Device Periodic Transmit FIFO#n Register if dedicated fifos are disabled, otherwise Device Transmit FIFO#n Register. +-

                                                                                +-Offset: 104h + (FIFO_Number-1)*04h, 1 <= FIFO Number <= 15 (1<=n<=15). +-

                                                                                +-Definition at line 150 of file dwc_otg_regs.h.

                                                                                +-

                                                                                The documentation for this struct was generated from the following file: +-
                                                                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__core__if.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__core__if.html 2013-07-26 19:34:43.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,311 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_core_if Struct Reference +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                dwc_otg_core_if Struct Reference

                                                                                The dwc_otg_core_if structure contains information needed to manage the DWC_otg controller acting in either host or device mode. +-More... +-

                                                                                +-#include <dwc_otg_cil.h> +-

                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-

                                                                                Data Fields

                                                                                +-dwc_otg_core_params_t * core_params
                                                                                 Parameters that define how the core should be configured.
                                                                                +-dwc_otg_core_global_regs_t * core_global_regs
                                                                                 Core Global registers starting at offset 000h.
                                                                                +-dwc_otg_dev_if_t * dev_if
                                                                                 Device-specific information.
                                                                                +-dwc_otg_host_if_t * host_if
                                                                                 Host-specific information.
                                                                                +-uint32_t snpsid
                                                                                 Value from SNPSID register.
                                                                                +-uint8_t phy_init_done
                                                                                +-uint8_t srp_success
                                                                                +-uint8_t srp_timer_started
                                                                                dwc_timer_t * srp_timer
                                                                                 Timer for SRP.
                                                                                +-volatile uint32_t * pcgcctl
                                                                                 Power and Clock Gating Control Register.
                                                                                +-uint32_t * data_fifo [MAX_EPS_CHANNELS]
                                                                                 Push/pop addresses for endpoints or host channels.
                                                                                +-uint16_t total_fifo_size
                                                                                 Total RAM for FIFOs (Bytes).
                                                                                +-uint16_t rx_fifo_size
                                                                                 Size of Rx FIFO (Bytes).
                                                                                +-uint16_t nperio_tx_fifo_size
                                                                                 Size of Non-periodic Tx FIFO (Bytes).
                                                                                +-uint8_t dma_enable
                                                                                 1 if DMA is enabled, 0 otherwise.
                                                                                +-uint8_t dma_desc_enable
                                                                                 1 if DMA descriptor is enabled, 0 otherwise.
                                                                                +-uint8_t pti_enh_enable
                                                                                 1 if PTI Enhancement mode is enabled, 0 otherwise.
                                                                                +-uint8_t multiproc_int_enable
                                                                                 1 if MPI Enhancement mode is enabled, 0 otherwise.
                                                                                +-uint8_t en_multiple_tx_fifo
                                                                                 1 if dedicated Tx FIFOs are enabled, 0 otherwise.
                                                                                +-uint8_t queuing_high_bandwidth
                                                                                 Set to 1 if multiple packets of a high-bandwidth transfer is in process of being queued.
                                                                                +-hwcfg1_data_t hwcfg1
                                                                                 Hardware Configuration -- stored here for convenience.
                                                                                +-hwcfg2_data_t hwcfg2
                                                                                +-hwcfg3_data_t hwcfg3
                                                                                +-hwcfg4_data_t hwcfg4
                                                                                +-fifosize_data_t hptxfsiz
                                                                                +-hcfg_data_t hcfg
                                                                                 Host and Device Configuration -- stored here for convenience.
                                                                                +-dcfg_data_t dcfg
                                                                                uint8_t op_state
                                                                                 The operational State, during transations (a_host>>a_peripherial and b_device=>b_host) this may not match the core but allows the software to determine transitions.
                                                                                uint8_t restart_hcd_on_session_req
                                                                                 Set to 1 if the HCD needs to be restarted on a session request interrupt.
                                                                                +-dwc_otg_cil_callbacks * hcd_cb
                                                                                 HCD callbacks.
                                                                                +-dwc_otg_cil_callbacks * pcd_cb
                                                                                 PCD callbacks.
                                                                                +-uint32_t p_tx_msk
                                                                                 Device mode Periodic Tx FIFO Mask.
                                                                                +-uint32_t tx_msk
                                                                                 Device mode Periodic Tx FIFO Mask.
                                                                                +-dwc_workq_t * wq_otg
                                                                                 Workqueue object used for handling several interrupts.
                                                                                +-dwc_timer_t * wkp_timer
                                                                                 Timer object used for handling "Wakeup Detected" Interrupt.
                                                                                +-uint32_t start_doeptsiz_val [MAX_EPS_CHANNELS]
                                                                                 This arrays used for debug purposes for DEV OUT NAK enhancement.
                                                                                +-ep_xfer_info_t ep_xfer_info [MAX_EPS_CHANNELS]
                                                                                +-dwc_timer_t * ep_xfer_timer [MAX_EPS_CHANNELS]
                                                                                +-dwc_otg_lx_state_e lx_state
                                                                                 Lx state of device.
                                                                                +-dwc_otg_global_regs_backup * gr_backup
                                                                                 Saved Core Global registers.
                                                                                +-dwc_otg_host_regs_backup * hr_backup
                                                                                 Saved Host registers.
                                                                                +-dwc_otg_dev_regs_backup * dr_backup
                                                                                 Saved Device registers.
                                                                                +-uint32_t power_down
                                                                                 Power Down Enable.
                                                                                +-uint32_t adp_enable
                                                                                 ADP support Enable.
                                                                                +-dwc_otg_adp_t adp
                                                                                 ADP structure object.
                                                                                +-int hibernation_suspend
                                                                                 hibernation/suspend flag
                                                                                +-uint32_t otg_ver
                                                                                 OTG revision supported.
                                                                                +-uint8_t otg_sts
                                                                                 OTG status flag used for HNP polling.
                                                                                +-dwc_spinlock_t * lock
                                                                                 Pointer to either hcd->lock or pcd->lock.
                                                                                +-uint8_t start_predict
                                                                                 Start predict NextEP based on Learning Queue if equal 1, also used as counter of disabled NP IN EP's.
                                                                                +-uint8_t nextep_seq [MAX_EPS_CHANNELS]
                                                                                 NextEp sequence, including EP0: nextep_seq[] = EP if non-periodic and active, 0xff otherwise.
                                                                                +-uint8_t first_in_nextep_seq
                                                                                 Index of fisrt EP in nextep_seq array which should be re-enabled *.
                                                                                +-uint32_t frame_num
                                                                                 Frame number while entering to ISR - needed for ISOCs *.
                                                                                +-

                                                                                Detailed Description

                                                                                +-The dwc_otg_core_if structure contains information needed to manage the DWC_otg controller acting in either host or device mode. +-

                                                                                +-It represents the programming view of the controller as a whole. +-

                                                                                +- +-

                                                                                +-Definition at line 792 of file dwc_otg_cil.h.

                                                                                Field Documentation

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                dwc_timer_t* dwc_otg_core_if::srp_timer
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Timer for SRP. +-

                                                                                +-If it expires before SRP is successful clear the SRP. +-

                                                                                +-Definition at line 820 of file dwc_otg_cil.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                uint8_t dwc_otg_core_if::op_state
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-The operational State, during transations (a_host>>a_peripherial and b_device=>b_host) this may not match the core but allows the software to determine transitions. +-

                                                                                +- +-

                                                                                +-Definition at line 881 of file dwc_otg_cil.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                uint8_t dwc_otg_core_if::restart_hcd_on_session_req
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Set to 1 if the HCD needs to be restarted on a session request interrupt. +-

                                                                                +-This is required if no connector ID status change has occurred since the HCD was last disconnected. +-

                                                                                +-Definition at line 888 of file dwc_otg_cil.h.

                                                                                +-

                                                                                The documentation for this struct was generated from the following file: +-
                                                                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__core__params.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__core__params.html 2013-07-26 19:34:43.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,936 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_core_params Struct Reference +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                dwc_otg_core_params Struct Reference

                                                                                The following parameters may be specified when starting the module. +-More... +-

                                                                                +-#include <dwc_otg_cil.h> +-

                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-

                                                                                Data Fields

                                                                                +-int32_t opt
                                                                                int32_t otg_cap
                                                                                 Specifies the OTG capabilities.
                                                                                int32_t dma_enable
                                                                                 Specifies whether to use slave or DMA mode for accessing the data FIFOs.
                                                                                int32_t dma_desc_enable
                                                                                 When DMA mode is enabled specifies whether to use address DMA or DMA Descriptor mode for accessing the data FIFOs in device mode.
                                                                                int32_t dma_burst_size
                                                                                 The DMA Burst size (applicable only for External DMA Mode).
                                                                                int32_t speed
                                                                                 Specifies the maximum speed of operation in host and device mode.
                                                                                int32_t host_support_fs_ls_low_power
                                                                                 Specifies whether low power mode is supported when attached to a Full Speed or Low Speed device in host mode.
                                                                                int32_t host_ls_low_power_phy_clk
                                                                                 Specifies the PHY clock rate in low power mode when connected to a Low Speed device in host mode.
                                                                                +-int32_t enable_dynamic_fifo
                                                                                 0 - Use cC FIFO size parameters 1 - Allow dynamic FIFO sizing (default)
                                                                                int32_t data_fifo_size
                                                                                 Total number of 4-byte words in the data FIFO memory.
                                                                                int32_t dev_rx_fifo_size
                                                                                 Number of 4-byte words in the Rx FIFO in device mode when dynamic FIFO sizing is enabled.
                                                                                int32_t dev_nperio_tx_fifo_size
                                                                                 Number of 4-byte words in the non-periodic Tx FIFO in device mode when dynamic FIFO sizing is enabled.
                                                                                uint32_t dev_perio_tx_fifo_size [MAX_PERIO_FIFOS]
                                                                                 Number of 4-byte words in each of the periodic Tx FIFOs in device mode when dynamic FIFO sizing is enabled.
                                                                                int32_t host_rx_fifo_size
                                                                                 Number of 4-byte words in the Rx FIFO in host mode when dynamic FIFO sizing is enabled.
                                                                                int32_t host_nperio_tx_fifo_size
                                                                                 Number of 4-byte words in the non-periodic Tx FIFO in host mode when Dynamic FIFO sizing is enabled in the core.
                                                                                int32_t host_perio_tx_fifo_size
                                                                                 Number of 4-byte words in the host periodic Tx FIFO when dynamic FIFO sizing is enabled.
                                                                                int32_t max_transfer_size
                                                                                 The maximum transfer size supported in bytes.
                                                                                int32_t max_packet_count
                                                                                 The maximum number of packets in a transfer.
                                                                                int32_t host_channels
                                                                                 The number of host channel registers to use.
                                                                                int32_t dev_endpoints
                                                                                 The number of endpoints in addition to EP0 available for device mode operations.
                                                                                int32_t phy_type
                                                                                 Specifies the type of PHY interface to use.
                                                                                int32_t phy_utmi_width
                                                                                 Specifies the UTMI+ Data Width.
                                                                                int32_t phy_ulpi_ddr
                                                                                 Specifies whether the ULPI operates at double or single data rate.
                                                                                int32_t phy_ulpi_ext_vbus
                                                                                 Specifies whether to use the internal or external supply to drive the vbus with a ULPI phy.
                                                                                int32_t i2c_enable
                                                                                 Specifies whether to use the I2Cinterface for full speed PHY.
                                                                                +-int32_t ulpi_fs_ls
                                                                                +-int32_t ts_dline
                                                                                +-int32_t en_multiple_tx_fifo
                                                                                 Specifies whether dedicated transmit FIFOs are enabled for non periodic IN endpoints in device mode 0 - No 1 - Yes.
                                                                                uint32_t dev_tx_fifo_size [MAX_TX_FIFOS]
                                                                                 Number of 4-byte words in each of the Tx FIFOs in device mode when dynamic FIFO sizing is enabled.
                                                                                +-uint32_t thr_ctl
                                                                                 Thresholding enable flag- bit 0 - enable non-ISO Tx thresholding bit 1 - enable ISO Tx thresholding bit 2 - enable Rx thresholding.
                                                                                +-uint32_t tx_thr_length
                                                                                 Thresholding length for Tx FIFOs in 32 bit DWORDs.
                                                                                +-uint32_t rx_thr_length
                                                                                 Thresholding length for Rx FIFOs in 32 bit DWORDs.
                                                                                +-int32_t lpm_enable
                                                                                 Specifies whether LPM (Link Power Management) support is enabled.
                                                                                +-int32_t pti_enable
                                                                                 Per Transfer Interrupt mode enable flag 1 - Enabled 0 - Disabled.
                                                                                +-int32_t mpi_enable
                                                                                 Multi Processor Interrupt mode enable flag 1 - Enabled 0 - Disabled.
                                                                                +-int32_t ic_usb_cap
                                                                                 IS_USB Capability 1 - Enabled 0 - Disabled.
                                                                                +-int32_t ahb_thr_ratio
                                                                                 AHB Threshold Ratio 2'b00 AHB Threshold = MAC Threshold 2'b01 AHB Threshold = 1/2 MAC Threshold 2'b10 AHB Threshold = 1/4 MAC Threshold 2'b11 AHB Threshold = 1/8 MAC Threshold.
                                                                                +-int32_t adp_supp_enable
                                                                                 ADP Support 1 - Enabled 0 - Disabled.
                                                                                int32_t reload_ctl
                                                                                 HFIR Reload Control 0 - The HFIR cannot be reloaded dynamically.
                                                                                int32_t dev_out_nak
                                                                                 DCFG: Enable device Out NAK 0 - The core does not set NAK after Bulk Out transfer complete.
                                                                                int32_t cont_on_bna
                                                                                 DCFG: Enable Continue on BNA After receiving BNA interrupt the core disables the endpoint,when the endpoint is re-enabled by the application the core starts processing 0 - from the DOEPDMA descriptor 1 - from the descriptor which received the BNA.
                                                                                int32_t ahb_single
                                                                                 GAHBCFG: AHB Single Support This bit when programmed supports SINGLE transfers for remainder data in a transfer for DMA mode of operation.
                                                                                +-int32_t power_down
                                                                                 Core Power down mode 0 - No Power Down is enabled 1 - Reserved 2 - Complete Power Down (Hibernation).
                                                                                +-int32_t otg_ver
                                                                                 OTG revision supported 0 - OTG 1.3 revision 1 - OTG 2.0 revision.
                                                                                +-

                                                                                Detailed Description

                                                                                +-The following parameters may be specified when starting the module. +-

                                                                                +-These parameters define how the DWC_otg controller should be configured. +-

                                                                                +- +-

                                                                                +-Definition at line 424 of file dwc_otg_cil.h.

                                                                                Field Documentation

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                int32_t dwc_otg_core_params::otg_cap
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Specifies the OTG capabilities. +-

                                                                                +-The driver will automatically detect the value for this parameter if none is specified. 0 - HNP and SRP capable (default) 1 - SRP Only capable 2 - No HNP/SRP capable +-

                                                                                +-Definition at line 434 of file dwc_otg_cil.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                int32_t dwc_otg_core_params::dma_enable
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Specifies whether to use slave or DMA mode for accessing the data FIFOs. +-

                                                                                +-The driver will automatically detect the value for this parameter if none is specified. 0 - Slave 1 - DMA (default, if available) +-

                                                                                +-Definition at line 443 of file dwc_otg_cil.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                int32_t dwc_otg_core_params::dma_desc_enable
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-When DMA mode is enabled specifies whether to use address DMA or DMA Descriptor mode for accessing the data FIFOs in device mode. +-

                                                                                +-The driver will automatically detect the value for this if none is specified. 0 - address DMA 1 - DMA Descriptor(default, if available) +-

                                                                                +-Definition at line 452 of file dwc_otg_cil.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                int32_t dwc_otg_core_params::dma_burst_size
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-The DMA Burst size (applicable only for External DMA Mode). +-

                                                                                +-1, 4, 8 16, 32, 64, 128, 256 (default 32) +-

                                                                                +-Definition at line 456 of file dwc_otg_cil.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                int32_t dwc_otg_core_params::speed
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Specifies the maximum speed of operation in host and device mode. +-

                                                                                +-The actual speed depends on the speed of the attached device and the value of phy_type. The actual speed depends on the speed of the attached device. 0 - High Speed (default) 1 - Full Speed +-

                                                                                +-Definition at line 466 of file dwc_otg_cil.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                int32_t dwc_otg_core_params::host_support_fs_ls_low_power
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Specifies whether low power mode is supported when attached to a Full Speed or Low Speed device in host mode. +-

                                                                                +-0 - Don't support low power mode (default) 1 - Support low power mode +-

                                                                                +-Definition at line 472 of file dwc_otg_cil.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                int32_t dwc_otg_core_params::host_ls_low_power_phy_clk
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Specifies the PHY clock rate in low power mode when connected to a Low Speed device in host mode. +-

                                                                                +-This parameter is applicable only if HOST_SUPPORT_FS_LS_LOW_POWER is enabled. If PHY_TYPE is set to FS then defaults to 6 MHZ otherwise 48 MHZ.

                                                                                +-0 - 48 MHz 1 - 6 MHz +-

                                                                                +-Definition at line 482 of file dwc_otg_cil.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                int32_t dwc_otg_core_params::data_fifo_size
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Total number of 4-byte words in the data FIFO memory. +-

                                                                                +-This memory includes the Rx FIFO, non-periodic Tx FIFO, and periodic Tx FIFOs. 32 to 32768 (default 8192) Note: The total FIFO memory depth in the FPGA configuration is 8192. +-

                                                                                +-Definition at line 496 of file dwc_otg_cil.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                int32_t dwc_otg_core_params::dev_rx_fifo_size
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Number of 4-byte words in the Rx FIFO in device mode when dynamic FIFO sizing is enabled. +-

                                                                                +-16 to 32768 (default 1064) +-

                                                                                +-Definition at line 502 of file dwc_otg_cil.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                int32_t dwc_otg_core_params::dev_nperio_tx_fifo_size
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Number of 4-byte words in the non-periodic Tx FIFO in device mode when dynamic FIFO sizing is enabled. +-

                                                                                +-16 to 32768 (default 1024) +-

                                                                                +-Definition at line 508 of file dwc_otg_cil.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                uint32_t dwc_otg_core_params::dev_perio_tx_fifo_size[MAX_PERIO_FIFOS]
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Number of 4-byte words in each of the periodic Tx FIFOs in device mode when dynamic FIFO sizing is enabled. +-

                                                                                +-4 to 768 (default 256) +-

                                                                                +-Definition at line 514 of file dwc_otg_cil.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                int32_t dwc_otg_core_params::host_rx_fifo_size
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Number of 4-byte words in the Rx FIFO in host mode when dynamic FIFO sizing is enabled. +-

                                                                                +-16 to 32768 (default 1024) +-

                                                                                +-Definition at line 520 of file dwc_otg_cil.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                int32_t dwc_otg_core_params::host_nperio_tx_fifo_size
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Number of 4-byte words in the non-periodic Tx FIFO in host mode when Dynamic FIFO sizing is enabled in the core. +-

                                                                                +-16 to 32768 (default 1024) +-

                                                                                +-Definition at line 526 of file dwc_otg_cil.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                int32_t dwc_otg_core_params::host_perio_tx_fifo_size
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Number of 4-byte words in the host periodic Tx FIFO when dynamic FIFO sizing is enabled. +-

                                                                                +-16 to 32768 (default 1024) +-

                                                                                +-Definition at line 532 of file dwc_otg_cil.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                int32_t dwc_otg_core_params::max_transfer_size
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-The maximum transfer size supported in bytes. +-

                                                                                +-2047 to 65,535 (default 65,535) +-

                                                                                +-Definition at line 537 of file dwc_otg_cil.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                int32_t dwc_otg_core_params::max_packet_count
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-The maximum number of packets in a transfer. +-

                                                                                +-15 to 511 (default 511) +-

                                                                                +-Definition at line 542 of file dwc_otg_cil.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                int32_t dwc_otg_core_params::host_channels
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-The number of host channel registers to use. +-

                                                                                +-1 to 16 (default 12) Note: The FPGA configuration supports a maximum of 12 host channels. +-

                                                                                +-Definition at line 548 of file dwc_otg_cil.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                int32_t dwc_otg_core_params::dev_endpoints
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-The number of endpoints in addition to EP0 available for device mode operations. +-

                                                                                +-1 to 15 (default 6 IN and OUT) Note: The FPGA configuration supports a maximum of 6 IN and OUT endpoints in addition to EP0. +-

                                                                                +-Definition at line 556 of file dwc_otg_cil.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                int32_t dwc_otg_core_params::phy_type
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Specifies the type of PHY interface to use. +-

                                                                                +-By default, the driver will automatically detect the phy_type.

                                                                                +-0 - Full Speed PHY 1 - UTMI+ (default) 2 - ULPI +-

                                                                                +-Definition at line 566 of file dwc_otg_cil.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                int32_t dwc_otg_core_params::phy_utmi_width
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Specifies the UTMI+ Data Width. +-

                                                                                +-This parameter is applicable for a PHY_TYPE of UTMI+ or ULPI. (For a ULPI PHY_TYPE, this parameter indicates the data width between the MAC and the ULPI Wrapper.) Also, this parameter is applicable only if the OTG_HSPHY_WIDTH cC parameter was set to "8 and 16 bits", meaning that the core has been configured to work at either data path width.

                                                                                +-8 or 16 bits (default 16) +-

                                                                                +-Definition at line 579 of file dwc_otg_cil.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                int32_t dwc_otg_core_params::phy_ulpi_ddr
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Specifies whether the ULPI operates at double or single data rate. +-

                                                                                +-This parameter is only applicable if PHY_TYPE is ULPI.

                                                                                +-0 - single data rate ULPI interface with 8 bit wide data bus (default) 1 - double data rate ULPI interface with 4 bit wide data bus +-

                                                                                +-Definition at line 591 of file dwc_otg_cil.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                int32_t dwc_otg_core_params::phy_ulpi_ext_vbus
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Specifies whether to use the internal or external supply to drive the vbus with a ULPI phy. +-

                                                                                +- +-

                                                                                +-Definition at line 597 of file dwc_otg_cil.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                int32_t dwc_otg_core_params::i2c_enable
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Specifies whether to use the I2Cinterface for full speed PHY. +-

                                                                                +-This parameter is only applicable if PHY_TYPE is FS. 0 - No (default) 1 - Yes +-

                                                                                +-Definition at line 605 of file dwc_otg_cil.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                uint32_t dwc_otg_core_params::dev_tx_fifo_size[MAX_TX_FIFOS]
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Number of 4-byte words in each of the Tx FIFOs in device mode when dynamic FIFO sizing is enabled. +-

                                                                                +-4 to 768 (default 256) +-

                                                                                +-Definition at line 623 of file dwc_otg_cil.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                int32_t dwc_otg_core_params::reload_ctl
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-HFIR Reload Control 0 - The HFIR cannot be reloaded dynamically. +-

                                                                                +-1 - Allow dynamic reloading of the HFIR register during runtime. +-

                                                                                +-Definition at line 685 of file dwc_otg_cil.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                int32_t dwc_otg_core_params::dev_out_nak
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-DCFG: Enable device Out NAK 0 - The core does not set NAK after Bulk Out transfer complete. +-

                                                                                +-1 - The core sets NAK after Bulk OUT transfer complete. +-

                                                                                +-Definition at line 691 of file dwc_otg_cil.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                int32_t dwc_otg_core_params::cont_on_bna
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-DCFG: Enable Continue on BNA After receiving BNA interrupt the core disables the endpoint,when the endpoint is re-enabled by the application the core starts processing 0 - from the DOEPDMA descriptor 1 - from the descriptor which received the BNA. +-

                                                                                +- +-

                                                                                +-Definition at line 699 of file dwc_otg_cil.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                int32_t dwc_otg_core_params::ahb_single
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-GAHBCFG: AHB Single Support This bit when programmed supports SINGLE transfers for remainder data in a transfer for DMA mode of operation. +-

                                                                                +-0 - in this case the remainder data will be sent using INCR burst size. 1 - in this case the remainder data will be sent using SINGLE burst size. +-

                                                                                +-Definition at line 707 of file dwc_otg_cil.h.

                                                                                +-

                                                                                The documentation for this struct was generated from the following file: +-
                                                                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__dev__dma__desc.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__dev__dma__desc.html 2013-07-26 19:34:43.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,38 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_dev_dma_desc Struct Reference +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                dwc_otg_dev_dma_desc Struct Reference

                                                                                DMA Descriptor structure. +-More... +-

                                                                                +-#include <dwc_otg_regs.h> +-

                                                                                +- +- +- +- +- +- +- +- +- +-

                                                                                Data Fields

                                                                                +-dev_dma_desc_sts_t status
                                                                                 DMA Descriptor status quadlet.
                                                                                +-uint32_t buf
                                                                                 DMA Descriptor data buffer pointer.
                                                                                +-

                                                                                Detailed Description

                                                                                +-DMA Descriptor structure. +-

                                                                                +-DMA Descriptor structure contains two quadlets: Status quadlet and Data buffer pointer. +-

                                                                                +- +-

                                                                                +-Definition at line 1767 of file dwc_otg_regs.h.

                                                                                The documentation for this struct was generated from the following file: +-
                                                                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__dev__global__regs.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__dev__global__regs.html 2013-07-26 19:34:43.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,573 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_dev_global_regs Struct Reference +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                dwc_otg_dev_global_regs Struct Reference

                                                                                Device Global Registers. +-More... +-

                                                                                +-#include <dwc_otg_regs.h> +-

                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-

                                                                                Data Fields

                                                                                volatile uint32_t dcfg
                                                                                 Device Configuration Register.
                                                                                volatile uint32_t dctl
                                                                                 Device Control Register.
                                                                                volatile uint32_t dsts
                                                                                 Device Status Register (Read Only).
                                                                                uint32_t unused
                                                                                 Reserved.
                                                                                volatile uint32_t diepmsk
                                                                                 Device IN Endpoint Common Interrupt Mask Register.
                                                                                volatile uint32_t doepmsk
                                                                                 Device OUT Endpoint Common Interrupt Mask Register.
                                                                                volatile uint32_t daint
                                                                                 Device All Endpoints Interrupt Register.
                                                                                volatile uint32_t daintmsk
                                                                                 Device All Endpoints Interrupt Mask Register.
                                                                                volatile uint32_t dtknqr1
                                                                                 Device IN Token Queue Read Register-1 (Read Only).
                                                                                volatile uint32_t dtknqr2
                                                                                 Device IN Token Queue Read Register-2 (Read Only).
                                                                                volatile uint32_t dvbusdis
                                                                                 Device VBUS discharge Register.
                                                                                volatile uint32_t dvbuspulse
                                                                                 Device VBUS Pulse Register.
                                                                                volatile uint32_t dtknqr3_dthrctl
                                                                                 Device IN Token Queue Read Register-3 (Read Only).
                                                                                volatile uint32_t dtknqr4_fifoemptymsk
                                                                                 Device IN Token Queue Read Register-4 (Read Only).
                                                                                volatile uint32_t deachint
                                                                                 Device Each Endpoint Interrupt Register (Read Only).
                                                                                volatile uint32_t deachintmsk
                                                                                 Device Each Endpoint Interrupt mask Register (Read/Write).
                                                                                volatile uint32_t diepeachintmsk [MAX_EPS_CHANNELS]
                                                                                 Device Each In Endpoint Interrupt mask Register (Read/Write).
                                                                                volatile uint32_t doepeachintmsk [MAX_EPS_CHANNELS]
                                                                                 Device Each Out Endpoint Interrupt mask Register (Read/Write).
                                                                                +-

                                                                                Detailed Description

                                                                                +-Device Global Registers. +-

                                                                                +-Offsets 800h-BFFh

                                                                                +-The following structures define the size and relative field offsets for the Device Mode Registers.

                                                                                +-These registers are visible only in Device mode and must not be accessed in Host mode, as the results are unknown. +-

                                                                                +- +-

                                                                                +-Definition at line 1079 of file dwc_otg_regs.h.

                                                                                Field Documentation

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                volatile uint32_t dwc_otg_dev_global_regs::dcfg
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Device Configuration Register. +-

                                                                                +-Offset 800h +-

                                                                                +-Definition at line 1081 of file dwc_otg_regs.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                volatile uint32_t dwc_otg_dev_global_regs::dctl
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Device Control Register. +-

                                                                                +-Offset: 804h +-

                                                                                +-Definition at line 1083 of file dwc_otg_regs.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                volatile uint32_t dwc_otg_dev_global_regs::dsts
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Device Status Register (Read Only). +-

                                                                                +-Offset: 808h +-

                                                                                +-Definition at line 1085 of file dwc_otg_regs.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                uint32_t dwc_otg_dev_global_regs::unused
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Reserved. +-

                                                                                +-Offset: 80Ch +-

                                                                                +-Definition at line 1087 of file dwc_otg_regs.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                volatile uint32_t dwc_otg_dev_global_regs::diepmsk
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Device IN Endpoint Common Interrupt Mask Register. +-

                                                                                +-Offset: 810h +-

                                                                                +-Definition at line 1090 of file dwc_otg_regs.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                volatile uint32_t dwc_otg_dev_global_regs::doepmsk
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Device OUT Endpoint Common Interrupt Mask Register. +-

                                                                                +-Offset: 814h +-

                                                                                +-Definition at line 1093 of file dwc_otg_regs.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                volatile uint32_t dwc_otg_dev_global_regs::daint
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Device All Endpoints Interrupt Register. +-

                                                                                +-Offset: 818h +-

                                                                                +-Definition at line 1095 of file dwc_otg_regs.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                volatile uint32_t dwc_otg_dev_global_regs::daintmsk
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Device All Endpoints Interrupt Mask Register. +-

                                                                                +-Offset: 81Ch +-

                                                                                +-Definition at line 1098 of file dwc_otg_regs.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                volatile uint32_t dwc_otg_dev_global_regs::dtknqr1
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Device IN Token Queue Read Register-1 (Read Only). +-

                                                                                +-Offset: 820h +-

                                                                                +-Definition at line 1101 of file dwc_otg_regs.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                volatile uint32_t dwc_otg_dev_global_regs::dtknqr2
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Device IN Token Queue Read Register-2 (Read Only). +-

                                                                                +-Offset: 824h +-

                                                                                +-Definition at line 1104 of file dwc_otg_regs.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                volatile uint32_t dwc_otg_dev_global_regs::dvbusdis
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Device VBUS discharge Register. +-

                                                                                +-Offset: 828h +-

                                                                                +-Definition at line 1106 of file dwc_otg_regs.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                volatile uint32_t dwc_otg_dev_global_regs::dvbuspulse
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Device VBUS Pulse Register. +-

                                                                                +-Offset: 82Ch +-

                                                                                +-Definition at line 1108 of file dwc_otg_regs.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                volatile uint32_t dwc_otg_dev_global_regs::dtknqr3_dthrctl
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Device IN Token Queue Read Register-3 (Read Only). +-

                                                                                +-/ Device Thresholding control register (Read/Write) Offset: 830h +-

                                                                                +-Definition at line 1112 of file dwc_otg_regs.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                volatile uint32_t dwc_otg_dev_global_regs::dtknqr4_fifoemptymsk
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Device IN Token Queue Read Register-4 (Read Only). +-

                                                                                +-/ Device IN EPs empty Inr. Mask Register (Read/Write) Offset: 834h +-

                                                                                +-Definition at line 1116 of file dwc_otg_regs.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                volatile uint32_t dwc_otg_dev_global_regs::deachint
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Device Each Endpoint Interrupt Register (Read Only). +-

                                                                                +-/ Offset: 838h +-

                                                                                +-Definition at line 1119 of file dwc_otg_regs.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                volatile uint32_t dwc_otg_dev_global_regs::deachintmsk
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Device Each Endpoint Interrupt mask Register (Read/Write). +-

                                                                                +-/ Offset: 83Ch +-

                                                                                +-Definition at line 1122 of file dwc_otg_regs.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                volatile uint32_t dwc_otg_dev_global_regs::diepeachintmsk[MAX_EPS_CHANNELS]
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Device Each In Endpoint Interrupt mask Register (Read/Write). +-

                                                                                +-/ Offset: 840h +-

                                                                                +-Definition at line 1125 of file dwc_otg_regs.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                volatile uint32_t dwc_otg_dev_global_regs::doepeachintmsk[MAX_EPS_CHANNELS]
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Device Each Out Endpoint Interrupt mask Register (Read/Write). +-

                                                                                +-/ Offset: 880h +-

                                                                                +-Definition at line 1128 of file dwc_otg_regs.h.

                                                                                +-

                                                                                The documentation for this struct was generated from the following file: +-
                                                                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__dev__if.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__dev__if.html 2013-07-26 19:34:43.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,142 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_dev_if Struct Reference +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                dwc_otg_dev_if Struct Reference

                                                                                The dwc_otg_dev_if structure contains information needed to manage the DWC_otg controller acting in device mode. +-More... +-

                                                                                +-#include <dwc_otg_regs.h> +-

                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-

                                                                                Data Fields

                                                                                dwc_otg_device_global_regs_t * dev_global_regs
                                                                                 Pointer to device Global registers.
                                                                                +-dwc_otg_dev_in_ep_regs_t * in_ep_regs [MAX_EPS_CHANNELS]
                                                                                 Device Logical IN Endpoint-Specific Registers 900h-AFCh.
                                                                                +-dwc_otg_dev_out_ep_regs_t * out_ep_regs [MAX_EPS_CHANNELS]
                                                                                 Device Logical OUT Endpoint-Specific Registers B00h-CFCh.
                                                                                +-uint8_t speed
                                                                                 Device Speed 0: Unknown, 1: LS, 2:FS, 3: HS.
                                                                                +-uint8_t num_in_eps
                                                                                 Number # of Tx EP range: 0-15 exept ep0.
                                                                                +-uint8_t num_out_eps
                                                                                 Number # of Rx EP range: 0-15 exept ep 0.
                                                                                +-uint16_t perio_tx_fifo_size [MAX_PERIO_FIFOS]
                                                                                 Size of periodic FIFOs (Bytes).
                                                                                +-uint16_t tx_fifo_size [MAX_TX_FIFOS]
                                                                                 Size of Tx FIFOs (Bytes).
                                                                                +-uint16_t rx_thr_en
                                                                                 Thresholding enable flags and length varaiables *.
                                                                                +-uint16_t iso_tx_thr_en
                                                                                +-uint16_t non_iso_tx_thr_en
                                                                                +-uint16_t rx_thr_length
                                                                                +-uint16_t tx_thr_length
                                                                                +-dwc_dma_t dma_setup_desc_addr [2]
                                                                                 2 descriptors for SETUP packets
                                                                                +-dwc_otg_dev_dma_desc_t * setup_desc_addr [2]
                                                                                +-dwc_otg_dev_dma_desc_t * psetup
                                                                                 Pointer to Descriptor with latest SETUP packet.
                                                                                +-uint32_t setup_desc_index
                                                                                 Index of current SETUP handler descriptor.
                                                                                +-dwc_dma_t dma_in_desc_addr
                                                                                 Descriptor for Data In or Status In phases.
                                                                                +-dwc_otg_dev_dma_desc_t * in_desc_addr
                                                                                +-dwc_dma_t dma_out_desc_addr
                                                                                 Descriptor for Data Out or Status Out phases.
                                                                                +-dwc_otg_dev_dma_desc_t * out_desc_addr
                                                                                +-uint32_t spd
                                                                                 Setup Packet Detected - if set clear NAK when queueing.
                                                                                +-void * isoc_ep
                                                                                 Isoc ep pointer on which incomplete happens.
                                                                                +-

                                                                                Detailed Description

                                                                                +-The dwc_otg_dev_if structure contains information needed to manage the DWC_otg controller acting in device mode. +-

                                                                                +-It represents the programming view of the device-specific aspects of the controller. +-

                                                                                +- +-

                                                                                +-Definition at line 1779 of file dwc_otg_regs.h.

                                                                                Field Documentation

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                dwc_otg_device_global_regs_t* dwc_otg_dev_if::dev_global_regs
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Pointer to device Global registers. +-

                                                                                +-Device Global Registers starting at offset 800h +-

                                                                                +-Definition at line 1783 of file dwc_otg_regs.h.

                                                                                +-

                                                                                The documentation for this struct was generated from the following file: +-
                                                                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__dev__in__ep__regs.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__dev__in__ep__regs.html 2013-07-26 19:34:43.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,273 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_dev_in_ep_regs Struct Reference +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                dwc_otg_dev_in_ep_regs Struct Reference

                                                                                Device Logical IN Endpoint-Specific Registers. +-More... +-

                                                                                +-#include <dwc_otg_regs.h> +-

                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-

                                                                                Data Fields

                                                                                volatile uint32_t diepctl
                                                                                 Device IN Endpoint Control Register.
                                                                                uint32_t reserved04
                                                                                 Reserved.
                                                                                volatile uint32_t diepint
                                                                                 Device IN Endpoint Interrupt Register.
                                                                                uint32_t reserved0C
                                                                                 Reserved.
                                                                                volatile uint32_t dieptsiz
                                                                                 Device IN Endpoint Transfer Size Register.
                                                                                volatile uint32_t diepdma
                                                                                 Device IN Endpoint DMA Address Register.
                                                                                volatile uint32_t dtxfsts
                                                                                 Device IN Endpoint Transmit FIFO Status Register.
                                                                                volatile uint32_t diepdmab
                                                                                 Device IN Endpoint DMA Buffer Register.
                                                                                +-

                                                                                Detailed Description

                                                                                +-Device Logical IN Endpoint-Specific Registers. +-

                                                                                +-Offsets 900h-AFCh

                                                                                +-There will be one set of endpoint registers per logical endpoint implemented.

                                                                                +-These registers are visible only in Device mode and must not be accessed in Host mode, as the results are unknown. +-

                                                                                +- +-

                                                                                +-Definition at line 1462 of file dwc_otg_regs.h.

                                                                                Field Documentation

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                volatile uint32_t dwc_otg_dev_in_ep_regs::diepctl
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Device IN Endpoint Control Register. +-

                                                                                +-Offset:900h + (ep_num * 20h) + 00h +-

                                                                                +-Definition at line 1465 of file dwc_otg_regs.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                uint32_t dwc_otg_dev_in_ep_regs::reserved04
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Reserved. +-

                                                                                +-Offset:900h + (ep_num * 20h) + 04h +-

                                                                                +-Definition at line 1467 of file dwc_otg_regs.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                volatile uint32_t dwc_otg_dev_in_ep_regs::diepint
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Device IN Endpoint Interrupt Register. +-

                                                                                +-Offset:900h + (ep_num * 20h) + 08h +-

                                                                                +-Definition at line 1470 of file dwc_otg_regs.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                uint32_t dwc_otg_dev_in_ep_regs::reserved0C
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Reserved. +-

                                                                                +-Offset:900h + (ep_num * 20h) + 0Ch +-

                                                                                +-Definition at line 1472 of file dwc_otg_regs.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                volatile uint32_t dwc_otg_dev_in_ep_regs::dieptsiz
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Device IN Endpoint Transfer Size Register. +-

                                                                                +-Offset:900h + (ep_num * 20h) + 10h +-

                                                                                +-Definition at line 1475 of file dwc_otg_regs.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                volatile uint32_t dwc_otg_dev_in_ep_regs::diepdma
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Device IN Endpoint DMA Address Register. +-

                                                                                +-Offset:900h + (ep_num * 20h) + 14h +-

                                                                                +-Definition at line 1478 of file dwc_otg_regs.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                volatile uint32_t dwc_otg_dev_in_ep_regs::dtxfsts
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Device IN Endpoint Transmit FIFO Status Register. +-

                                                                                +-Offset:900h + (ep_num * 20h) + 18h +-

                                                                                +-Definition at line 1481 of file dwc_otg_regs.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                volatile uint32_t dwc_otg_dev_in_ep_regs::diepdmab
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Device IN Endpoint DMA Buffer Register. +-

                                                                                +-Offset:900h + (ep_num * 20h) + 1Ch +-

                                                                                +-Definition at line 1484 of file dwc_otg_regs.h.

                                                                                +-

                                                                                The documentation for this struct was generated from the following file: +-
                                                                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__dev__out__ep__regs.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__dev__out__ep__regs.html 2013-07-26 19:34:43.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,273 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_dev_out_ep_regs Struct Reference +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                dwc_otg_dev_out_ep_regs Struct Reference

                                                                                Device Logical OUT Endpoint-Specific Registers. +-More... +-

                                                                                +-#include <dwc_otg_regs.h> +-

                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-

                                                                                Data Fields

                                                                                volatile uint32_t doepctl
                                                                                 Device OUT Endpoint Control Register.
                                                                                uint32_t reserved04
                                                                                 Reserved.
                                                                                volatile uint32_t doepint
                                                                                 Device OUT Endpoint Interrupt Register.
                                                                                uint32_t reserved0C
                                                                                 Reserved.
                                                                                volatile uint32_t doeptsiz
                                                                                 Device OUT Endpoint Transfer Size Register.
                                                                                volatile uint32_t doepdma
                                                                                 Device OUT Endpoint DMA Address Register.
                                                                                uint32_t unused
                                                                                 Reserved.
                                                                                uint32_t doepdmab
                                                                                 Device OUT Endpoint DMA Buffer Register.
                                                                                +-

                                                                                Detailed Description

                                                                                +-Device Logical OUT Endpoint-Specific Registers. +-

                                                                                +-Offsets: B00h-CFCh

                                                                                +-There will be one set of endpoint registers per logical endpoint implemented.

                                                                                +-These registers are visible only in Device mode and must not be accessed in Host mode, as the results are unknown. +-

                                                                                +- +-

                                                                                +-Definition at line 1497 of file dwc_otg_regs.h.

                                                                                Field Documentation

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                volatile uint32_t dwc_otg_dev_out_ep_regs::doepctl
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Device OUT Endpoint Control Register. +-

                                                                                +-Offset:B00h + (ep_num * 20h) + 00h +-

                                                                                +-Definition at line 1500 of file dwc_otg_regs.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                uint32_t dwc_otg_dev_out_ep_regs::reserved04
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Reserved. +-

                                                                                +-Offset:B00h + (ep_num * 20h) + 04h +-

                                                                                +-Definition at line 1502 of file dwc_otg_regs.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                volatile uint32_t dwc_otg_dev_out_ep_regs::doepint
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Device OUT Endpoint Interrupt Register. +-

                                                                                +-Offset:B00h + (ep_num * 20h) + 08h +-

                                                                                +-Definition at line 1505 of file dwc_otg_regs.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                uint32_t dwc_otg_dev_out_ep_regs::reserved0C
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Reserved. +-

                                                                                +-Offset:B00h + (ep_num * 20h) + 0Ch +-

                                                                                +-Definition at line 1507 of file dwc_otg_regs.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                volatile uint32_t dwc_otg_dev_out_ep_regs::doeptsiz
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Device OUT Endpoint Transfer Size Register. +-

                                                                                +-Offset: B00h + (ep_num * 20h) + 10h +-

                                                                                +-Definition at line 1510 of file dwc_otg_regs.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                volatile uint32_t dwc_otg_dev_out_ep_regs::doepdma
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Device OUT Endpoint DMA Address Register. +-

                                                                                +-Offset:B00h + (ep_num * 20h) + 14h +-

                                                                                +-Definition at line 1513 of file dwc_otg_regs.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                uint32_t dwc_otg_dev_out_ep_regs::unused
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Reserved. +-

                                                                                +-Offset:B00h + * (ep_num * 20h) + 18h +-

                                                                                +-Definition at line 1515 of file dwc_otg_regs.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                uint32_t dwc_otg_dev_out_ep_regs::doepdmab
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Device OUT Endpoint DMA Buffer Register. +-

                                                                                +-Offset:B00h + (ep_num * 20h) + 1Ch +-

                                                                                +-Definition at line 1518 of file dwc_otg_regs.h.

                                                                                +-

                                                                                The documentation for this struct was generated from the following file: +-
                                                                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__device.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__device.html 2013-07-26 19:34:43.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,75 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_device Struct Reference +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                dwc_otg_device Struct Reference

                                                                                This structure is a wrapper that encapsulates the driver components used to manage a single DWC_otg controller. +-More... +-

                                                                                +-#include <dwc_otg_driver.h> +-

                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-

                                                                                Data Fields

                                                                                os_dependent os_dep
                                                                                 Structure containing OS-dependent stuff.
                                                                                +-dwc_otg_core_if_t * core_if
                                                                                 Pointer to the core interface structure.
                                                                                +-dwc_otg_pcd * pcd
                                                                                 Pointer to the PCD structure.
                                                                                +-dwc_otg_hcd * hcd
                                                                                 Pointer to the HCD structure.
                                                                                +-uint8_t common_irq_installed
                                                                                 Flag to indicate whether the common IRQ handler is installed.
                                                                                +-

                                                                                Detailed Description

                                                                                +-This structure is a wrapper that encapsulates the driver components used to manage a single DWC_otg controller. +-

                                                                                +- +-

                                                                                +-Definition at line 51 of file dwc_otg_driver.h.

                                                                                Field Documentation

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                struct os_dependent dwc_otg_device::os_dep
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Structure containing OS-dependent stuff. +-

                                                                                +-KEEP THIS STRUCT AT THE VERY BEGINNING OF THE DEVICE STRUCT. OSes such as FreeBSD and NetBSD require this. +-

                                                                                +-Definition at line 55 of file dwc_otg_driver.h.

                                                                                +-

                                                                                The documentation for this struct was generated from the following file: +-
                                                                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__hc__regs.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__hc__regs.html 2013-07-26 19:34:43.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,244 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_hc_regs Struct Reference +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                dwc_otg_hc_regs Struct Reference

                                                                                Host Channel Specific Registers. +-More... +-

                                                                                +-#include <dwc_otg_regs.h> +-

                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-

                                                                                Data Fields

                                                                                volatile uint32_t hcchar
                                                                                 Host Channel 0 Characteristic Register.
                                                                                volatile uint32_t hcsplt
                                                                                 Host Channel 0 Split Control Register.
                                                                                volatile uint32_t hcint
                                                                                 Host Channel 0 Interrupt Register.
                                                                                volatile uint32_t hcintmsk
                                                                                 Host Channel 0 Interrupt Mask Register.
                                                                                volatile uint32_t hctsiz
                                                                                 Host Channel 0 Transfer Size Register.
                                                                                volatile uint32_t hcdma
                                                                                 Host Channel 0 DMA Address Register.
                                                                                +-volatile uint32_t reserved
                                                                                volatile uint32_t hcdmab
                                                                                 Host Channel 0 DMA Buffer Address Register.
                                                                                +-

                                                                                Detailed Description

                                                                                +-Host Channel Specific Registers. +-

                                                                                +-500h-5FCh +-

                                                                                +- +-

                                                                                +-Definition at line 2068 of file dwc_otg_regs.h.

                                                                                Field Documentation

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                volatile uint32_t dwc_otg_hc_regs::hcchar
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Host Channel 0 Characteristic Register. +-

                                                                                +-Offset: 500h + (chan_num * 20h) + 00h +-

                                                                                +-Definition at line 2070 of file dwc_otg_regs.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                volatile uint32_t dwc_otg_hc_regs::hcsplt
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Host Channel 0 Split Control Register. +-

                                                                                +-Offset: 500h + (chan_num * 20h) + 04h +-

                                                                                +-Definition at line 2072 of file dwc_otg_regs.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                volatile uint32_t dwc_otg_hc_regs::hcint
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Host Channel 0 Interrupt Register. +-

                                                                                +-Offset: 500h + (chan_num * 20h) + 08h +-

                                                                                +-Definition at line 2074 of file dwc_otg_regs.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                volatile uint32_t dwc_otg_hc_regs::hcintmsk
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Host Channel 0 Interrupt Mask Register. +-

                                                                                +-Offset: 500h + (chan_num * 20h) + 0Ch +-

                                                                                +-Definition at line 2076 of file dwc_otg_regs.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                volatile uint32_t dwc_otg_hc_regs::hctsiz
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Host Channel 0 Transfer Size Register. +-

                                                                                +-Offset: 500h + (chan_num * 20h) + 10h +-

                                                                                +-Definition at line 2078 of file dwc_otg_regs.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                volatile uint32_t dwc_otg_hc_regs::hcdma
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Host Channel 0 DMA Address Register. +-

                                                                                +-Offset: 500h + (chan_num * 20h) + 14h +-

                                                                                +-Definition at line 2080 of file dwc_otg_regs.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                volatile uint32_t dwc_otg_hc_regs::hcdmab
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Host Channel 0 DMA Buffer Address Register. +-

                                                                                +-Offset: 500h + (chan_num * 20h) + 1Ch +-

                                                                                +-Definition at line 2083 of file dwc_otg_regs.h.

                                                                                +-

                                                                                The documentation for this struct was generated from the following file: +-
                                                                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__hcd.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__hcd.html 2013-07-26 19:34:43.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,603 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_hcd Struct Reference +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                dwc_otg_hcd Struct Reference

                                                                                This structure holds the state of the HCD, including the non-periodic and periodic schedules. +-More... +-

                                                                                +-#include <dwc_otg_hcd.h> +-

                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-

                                                                                Data Fields

                                                                                +-dwc_otg_device * otg_dev
                                                                                 The DWC otg device pointer.
                                                                                +-dwc_otg_core_if_t * core_if
                                                                                 DWC OTG Core Interface Layer.
                                                                                +-dwc_otg_hcd_function_ops * fops
                                                                                 Function HCD driver callbacks.
                                                                                +-dwc_otg_hcd::dwc_otg_hcd_internal_flags flags
                                                                                 Internal DWC HCD Flags.
                                                                                dwc_list_link_t non_periodic_sched_inactive
                                                                                 Inactive items in the non-periodic schedule.
                                                                                dwc_list_link_t non_periodic_sched_active
                                                                                 Active items in the non-periodic schedule.
                                                                                dwc_list_link_t * non_periodic_qh_ptr
                                                                                 Pointer to the next Queue Head to process in the active non-periodic schedule.
                                                                                dwc_list_link_t periodic_sched_inactive
                                                                                 Inactive items in the periodic schedule.
                                                                                dwc_list_link_t periodic_sched_ready
                                                                                 List of periodic QHs that are ready for execution in the next frame, but have not yet been assigned to host channels.
                                                                                dwc_list_link_t periodic_sched_assigned
                                                                                 List of periodic QHs to be executed in the next frame that are assigned to host channels.
                                                                                dwc_list_link_t periodic_sched_queued
                                                                                 List of periodic QHs that have been queued for execution.
                                                                                uint16_t periodic_usecs
                                                                                 Total bandwidth claimed so far for periodic transfers.
                                                                                uint16_t frame_number
                                                                                 Frame number read from the core at SOF.
                                                                                uint16_t periodic_qh_count
                                                                                 Count of periodic QHs, if using several eps.
                                                                                hc_list free_hc_list
                                                                                 Free host channels in the controller.
                                                                                int periodic_channels
                                                                                 Number of host channels assigned to periodic transfers.
                                                                                int non_periodic_channels
                                                                                 Number of host channels assigned to non-periodic transfers.
                                                                                dwc_hc * hc_ptr_array [MAX_EPS_CHANNELS]
                                                                                 Array of pointers to the host channel descriptors.
                                                                                uint8_t * status_buf
                                                                                 Buffer to use for any data received during the status phase of a control transfer.
                                                                                dma_addr_t status_buf_dma
                                                                                 DMA address for status_buf.
                                                                                dwc_timer_t * conn_timer
                                                                                 Connection timer.
                                                                                +-dwc_tasklet_t * reset_tasklet
                                                                                +-dwc_spinlock_t * lock
                                                                                void * priv
                                                                                 Private data that could be used by OS wrapper.
                                                                                +-uint8_t otg_port
                                                                                +-uint32_t * frame_list
                                                                                 Frame List.
                                                                                +-dma_addr_t frame_list_dma
                                                                                 Frame List DMA address.
                                                                                +-

                                                                                Detailed Description

                                                                                +-This structure holds the state of the HCD, including the non-periodic and periodic schedules. +-

                                                                                +- +-

                                                                                +-Definition at line 373 of file dwc_otg_hcd.h.

                                                                                Field Documentation

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                dwc_list_link_t dwc_otg_hcd::non_periodic_sched_inactive
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Inactive items in the non-periodic schedule. +-

                                                                                +-This is a list of Queue Heads. Transfers associated with these Queue Heads are not currently assigned to a host channel. +-

                                                                                +-Definition at line 402 of file dwc_otg_hcd.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                dwc_list_link_t dwc_otg_hcd::non_periodic_sched_active
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Active items in the non-periodic schedule. +-

                                                                                +-This is a list of Queue Heads. Transfers associated with these Queue Heads are currently assigned to a host channel. +-

                                                                                +-Definition at line 409 of file dwc_otg_hcd.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                dwc_list_link_t* dwc_otg_hcd::non_periodic_qh_ptr
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Pointer to the next Queue Head to process in the active non-periodic schedule. +-

                                                                                +- +-

                                                                                +-Definition at line 415 of file dwc_otg_hcd.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                dwc_list_link_t dwc_otg_hcd::periodic_sched_inactive
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Inactive items in the periodic schedule. +-

                                                                                +-This is a list of QHs for periodic transfers that are _not_ scheduled for the next frame. Each QH in the list has an interval counter that determines when it needs to be scheduled for execution. This scheduling mechanism allows only a simple calculation for periodic bandwidth used (i.e. must assume that all periodic transfers may need to execute in the same frame). However, it greatly simplifies scheduling and should be sufficient for the vast majority of OTG hosts, which need to connect to a small number of peripherals at one time.

                                                                                +-Items move from this list to periodic_sched_ready when the QH interval counter is 0 at SOF. +-

                                                                                +-Definition at line 431 of file dwc_otg_hcd.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                dwc_list_link_t dwc_otg_hcd::periodic_sched_ready
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-List of periodic QHs that are ready for execution in the next frame, but have not yet been assigned to host channels. +-

                                                                                +-Items move from this list to periodic_sched_assigned as host channels become available during the current frame. +-

                                                                                +-Definition at line 440 of file dwc_otg_hcd.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                dwc_list_link_t dwc_otg_hcd::periodic_sched_assigned
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-List of periodic QHs to be executed in the next frame that are assigned to host channels. +-

                                                                                +-Items move from this list to periodic_sched_queued as the transactions for the QH are queued to the DWC_otg controller. +-

                                                                                +-Definition at line 449 of file dwc_otg_hcd.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                dwc_list_link_t dwc_otg_hcd::periodic_sched_queued
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-List of periodic QHs that have been queued for execution. +-

                                                                                +-Items move from this list to either periodic_sched_inactive or periodic_sched_ready when the channel associated with the transfer is released. If the interval for the QH is 1, the item moves to periodic_sched_ready because it must be rescheduled for the next frame. Otherwise, the item moves to periodic_sched_inactive. +-

                                                                                +-Definition at line 460 of file dwc_otg_hcd.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                uint16_t dwc_otg_hcd::periodic_usecs
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Total bandwidth claimed so far for periodic transfers. +-

                                                                                +-This value is in microseconds per (micro)frame. The assumption is that all periodic transfers may occur in the same (micro)frame. +-

                                                                                +-Definition at line 467 of file dwc_otg_hcd.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                uint16_t dwc_otg_hcd::frame_number
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Frame number read from the core at SOF. +-

                                                                                +-The value ranges from 0 to DWC_HFNUM_MAX_FRNUM. +-

                                                                                +-Definition at line 473 of file dwc_otg_hcd.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                uint16_t dwc_otg_hcd::periodic_qh_count
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Count of periodic QHs, if using several eps. +-

                                                                                +-For SOF enable/disable. +-

                                                                                +-Definition at line 478 of file dwc_otg_hcd.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                struct hc_list dwc_otg_hcd::free_hc_list
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Free host channels in the controller. +-

                                                                                +-This is a list of dwc_hc_t items. +-

                                                                                +-Definition at line 484 of file dwc_otg_hcd.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                int dwc_otg_hcd::periodic_channels
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Number of host channels assigned to periodic transfers. +-

                                                                                +-Currently assuming that there is a dedicated host channel for each periodic transaction and at least one host channel available for non-periodic transactions. +-

                                                                                +-Definition at line 491 of file dwc_otg_hcd.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                int dwc_otg_hcd::non_periodic_channels
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Number of host channels assigned to non-periodic transfers. +-

                                                                                +- +-

                                                                                +-Definition at line 496 of file dwc_otg_hcd.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                struct dwc_hc* dwc_otg_hcd::hc_ptr_array[MAX_EPS_CHANNELS]
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Array of pointers to the host channel descriptors. +-

                                                                                +-Allows accessing a host channel descriptor given the host channel number. This is useful in interrupt handlers. +-

                                                                                +-Definition at line 503 of file dwc_otg_hcd.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                uint8_t* dwc_otg_hcd::status_buf
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Buffer to use for any data received during the status phase of a control transfer. +-

                                                                                +-Normally no data is transferred during the status phase. This buffer is used as a bit bucket. +-

                                                                                +-Definition at line 510 of file dwc_otg_hcd.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                dma_addr_t dwc_otg_hcd::status_buf_dma
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-DMA address for status_buf. +-

                                                                                +- +-

                                                                                +-Definition at line 515 of file dwc_otg_hcd.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                dwc_timer_t* dwc_otg_hcd::conn_timer
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Connection timer. +-

                                                                                +-An OTG host must display a message if the device does not connect. Started when the VBus power is turned on via sysfs attribute "buspower". +-

                                                                                +-Definition at line 523 of file dwc_otg_hcd.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                void* dwc_otg_hcd::priv
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Private data that could be used by OS wrapper. +-

                                                                                +- +-

                                                                                +-Definition at line 534 of file dwc_otg_hcd.h.

                                                                                +-

                                                                                The documentation for this struct was generated from the following file: +-
                                                                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__host__dma__desc.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__host__dma__desc.html 2013-07-26 19:34:43.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,38 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_host_dma_desc Struct Reference +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                dwc_otg_host_dma_desc Struct Reference

                                                                                Host-mode DMA Descriptor structure. +-More... +-

                                                                                +-#include <dwc_otg_regs.h> +-

                                                                                +- +- +- +- +- +- +- +- +- +-

                                                                                Data Fields

                                                                                +-host_dma_desc_sts_t status
                                                                                 DMA Descriptor status quadlet.
                                                                                +-uint32_t buf
                                                                                 DMA Descriptor data buffer pointer.
                                                                                +-

                                                                                Detailed Description

                                                                                +-Host-mode DMA Descriptor structure. +-

                                                                                +-DMA Descriptor structure contains two quadlets: Status quadlet and Data buffer pointer. +-

                                                                                +- +-

                                                                                +-Definition at line 2384 of file dwc_otg_regs.h.

                                                                                The documentation for this struct was generated from the following file: +-
                                                                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__host__global__regs.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__host__global__regs.html 2013-07-26 19:34:43.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,271 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_host_global_regs Struct Reference +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                dwc_otg_host_global_regs Struct Reference

                                                                                The Host Global Registers structure defines the size and relative field offsets for the Host Mode Global Registers. +-More... +-

                                                                                +-#include <dwc_otg_regs.h> +-

                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-

                                                                                Data Fields

                                                                                volatile uint32_t hcfg
                                                                                 Host Configuration Register.
                                                                                volatile uint32_t hfir
                                                                                 Host Frame Interval Register.
                                                                                volatile uint32_t hfnum
                                                                                 Host Frame Number / Frame Remaining Register.
                                                                                uint32_t reserved40C
                                                                                 Reserved.
                                                                                volatile uint32_t hptxsts
                                                                                 Host Periodic Transmit FIFO/ Queue Status Register.
                                                                                volatile uint32_t haint
                                                                                 Host All Channels Interrupt Register.
                                                                                volatile uint32_t haintmsk
                                                                                 Host All Channels Interrupt Mask Register.
                                                                                volatile uint32_t hflbaddr
                                                                                 Host Frame List Base Address Register .
                                                                                +-

                                                                                Detailed Description

                                                                                +-The Host Global Registers structure defines the size and relative field offsets for the Host Mode Global Registers. +-

                                                                                +-Host Global Registers offsets 400h-7FFh. +-

                                                                                +- +-

                                                                                +-Definition at line 1854 of file dwc_otg_regs.h.

                                                                                Field Documentation

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                volatile uint32_t dwc_otg_host_global_regs::hcfg
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Host Configuration Register. +-

                                                                                +-Offset: 400h +-

                                                                                +-Definition at line 1856 of file dwc_otg_regs.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                volatile uint32_t dwc_otg_host_global_regs::hfir
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Host Frame Interval Register. +-

                                                                                +-Offset: 404h +-

                                                                                +-Definition at line 1858 of file dwc_otg_regs.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                volatile uint32_t dwc_otg_host_global_regs::hfnum
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Host Frame Number / Frame Remaining Register. +-

                                                                                +-Offset: 408h +-

                                                                                +-Definition at line 1860 of file dwc_otg_regs.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                uint32_t dwc_otg_host_global_regs::reserved40C
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Reserved. +-

                                                                                +-Offset: 40Ch +-

                                                                                +-Definition at line 1862 of file dwc_otg_regs.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                volatile uint32_t dwc_otg_host_global_regs::hptxsts
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Host Periodic Transmit FIFO/ Queue Status Register. +-

                                                                                +-Offset: 410h +-

                                                                                +-Definition at line 1864 of file dwc_otg_regs.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                volatile uint32_t dwc_otg_host_global_regs::haint
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Host All Channels Interrupt Register. +-

                                                                                +-Offset: 414h +-

                                                                                +-Definition at line 1866 of file dwc_otg_regs.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                volatile uint32_t dwc_otg_host_global_regs::haintmsk
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Host All Channels Interrupt Mask Register. +-

                                                                                +-Offset: 418h +-

                                                                                +-Definition at line 1868 of file dwc_otg_regs.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                volatile uint32_t dwc_otg_host_global_regs::hflbaddr
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Host Frame List Base Address Register . +-

                                                                                +-Offset: 41Ch +-

                                                                                +-Definition at line 1870 of file dwc_otg_regs.h.

                                                                                +-

                                                                                The documentation for this struct was generated from the following file: +-
                                                                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__host__if.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__host__if.html 2013-07-26 19:34:43.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,54 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_host_if Struct Reference +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                dwc_otg_host_if Struct Reference

                                                                                OTG Host Interface Structure. +-More... +-

                                                                                +-#include <dwc_otg_regs.h> +-

                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-

                                                                                Data Fields

                                                                                +-dwc_otg_host_global_regs_t * host_global_regs
                                                                                 Host Global Registers starting at offset 400h.
                                                                                +-volatile uint32_t * hprt0
                                                                                 Host Port 0 Control and Status Register.
                                                                                +-dwc_otg_hc_regs_t * hc_regs [MAX_EPS_CHANNELS]
                                                                                 Host Channel Specific Registers at offsets 500h-5FCh.
                                                                                +-uint8_t num_host_channels
                                                                                 Number of Host Channels (range: 1-16).
                                                                                +-uint8_t perio_eps_supported
                                                                                 Periodic EPs supported (0: no, 1: yes).
                                                                                +-uint16_t perio_tx_fifo_size
                                                                                 Periodic Tx FIFO Size (Only 1 host periodic Tx FIFO).
                                                                                +-

                                                                                Detailed Description

                                                                                +-OTG Host Interface Structure. +-

                                                                                +-The OTG Host Interface Structure structure contains information needed to manage the DWC_otg controller acting in host mode. It represents the programming view of the host-specific aspects of the controller. +-

                                                                                +- +-

                                                                                +-Definition at line 2398 of file dwc_otg_regs.h.

                                                                                The documentation for this struct was generated from the following file: +-
                                                                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__pcd.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__pcd.html 2013-07-26 19:34:43.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,172 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_pcd Struct Reference +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                dwc_otg_pcd Struct Reference

                                                                                DWC_otg PCD Structure. +-More... +-

                                                                                +-#include <dwc_otg_pcd.h> +-

                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-

                                                                                Data Fields

                                                                                +-const struct dwc_otg_pcd_function_ops * fops
                                                                                +-dwc_otg_device * otg_dev
                                                                                 The DWC otg device pointer.
                                                                                +-dwc_otg_core_if_t * core_if
                                                                                 Core Interface.
                                                                                +-ep0state_e ep0state
                                                                                 State of EP0.
                                                                                +-unsigned ep0_pending:1
                                                                                 EP0 Request is pending.
                                                                                +-unsigned request_config:1
                                                                                 Indicates when SET CONFIGURATION Request is in process.
                                                                                +-unsigned remote_wakeup_enable:1
                                                                                 The state of the Remote Wakeup Enable.
                                                                                +-unsigned b_hnp_enable:1
                                                                                 The state of the B-Device HNP Enable.
                                                                                +-unsigned a_hnp_support:1
                                                                                 The state of A-Device HNP Support.
                                                                                +-unsigned a_alt_hnp_support:1
                                                                                 The state of the A-Device Alt HNP support.
                                                                                +-unsigned request_pending
                                                                                 Count of pending Requests.
                                                                                union {
                                                                                   usb_device_request_t   req
                                                                                   uint32_t   d32 [2]
                                                                                } setup_pkt
                                                                                 SETUP packet for EP0 This structure is allocated as a DMA buffer on PCD initialization with enough space for up to 3 setup packets.
                                                                                +-dwc_dma_t setup_pkt_dma_handle
                                                                                +-uint16_t * status_buf
                                                                                 2-byte dma buffer used to return status from GET_STATUS
                                                                                +-dwc_dma_t status_buf_dma_handle
                                                                                +-dwc_otg_pcd_ep_t ep0
                                                                                 EP0.
                                                                                +-dwc_otg_pcd_ep_t in_ep [MAX_EPS_CHANNELS-1]
                                                                                 Array of IN EPs.
                                                                                +-dwc_otg_pcd_ep_t out_ep [MAX_EPS_CHANNELS-1]
                                                                                 Array of OUT EPs.
                                                                                +-dwc_spinlock_t * lock
                                                                                 number of valid EPs in the above array.
                                                                                dwc_tasklet_t * test_mode_tasklet
                                                                                 Tasklet to defer starting of TEST mode transmissions until Status Phase has been completed.
                                                                                +-dwc_tasklet_t * start_xfer_tasklet
                                                                                 Tasklet to delay starting of xfer in DMA mode.
                                                                                +-unsigned test_mode
                                                                                 The test mode to enter when the tasklet is executed.
                                                                                +-

                                                                                Detailed Description

                                                                                +-DWC_otg PCD Structure. +-

                                                                                +-This structure encapsulates the data for the dwc_otg PCD. +-

                                                                                +- +-

                                                                                +-Definition at line 184 of file dwc_otg_pcd.h.

                                                                                Field Documentation

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                union { ... } * dwc_otg_pcd::setup_pkt
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-SETUP packet for EP0 This structure is allocated as a DMA buffer on PCD initialization with enough space for up to 3 setup packets. +-

                                                                                +-

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                dwc_tasklet_t* dwc_otg_pcd::test_mode_tasklet
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Tasklet to defer starting of TEST mode transmissions until Status Phase has been completed. +-

                                                                                +- +-

                                                                                +-Definition at line 236 of file dwc_otg_pcd.h.

                                                                                +-

                                                                                The documentation for this struct was generated from the following file: +-
                                                                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__pcd__ep.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__pcd__ep.html 2013-07-26 19:34:43.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,65 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_pcd_ep Struct Reference +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                dwc_otg_pcd_ep Struct Reference

                                                                                PCD EP structure. +-More... +-

                                                                                +-#include <dwc_otg_pcd.h> +-

                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-

                                                                                Data Fields

                                                                                +-const usb_endpoint_descriptor_t * desc
                                                                                 USB EP Descriptor.
                                                                                +-req_list queue
                                                                                 queue of dwc_otg_pcd_requests.
                                                                                +-unsigned stopped:1
                                                                                +-unsigned disabling:1
                                                                                +-unsigned dma:1
                                                                                +-unsigned queue_sof:1
                                                                                +-void * iso_req_handle
                                                                                 ISOC req handle passed.
                                                                                +-dwc_ep_t dwc_ep
                                                                                 DWC_otg ep data.
                                                                                +-dwc_otg_pcd * pcd
                                                                                 Pointer to PCD.
                                                                                +-void * priv
                                                                                +-

                                                                                Detailed Description

                                                                                +-PCD EP structure. +-

                                                                                +-This structure describes an EP, there is an array of EPs in the PCD structure. +-

                                                                                +- +-

                                                                                +-Definition at line 156 of file dwc_otg_pcd.h.

                                                                                The documentation for this struct was generated from the following file: +-
                                                                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__pcd__function__ops.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__pcd__function__ops.html 2013-07-26 19:34:43.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,61 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_pcd_function_ops Struct Reference +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                dwc_otg_pcd_function_ops Struct Reference

                                                                                Function Driver Ops Data Structure. +-More... +-

                                                                                +-#include <dwc_otg_pcd_if.h> +-

                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-

                                                                                Data Fields

                                                                                +-dwc_connect_cb_t connect
                                                                                +-dwc_disconnect_cb_t disconnect
                                                                                +-dwc_setup_cb_t setup
                                                                                +-dwc_completion_cb_t complete
                                                                                +-dwc_isoc_completion_cb_t isoc_complete
                                                                                +-dwc_suspend_cb_t suspend
                                                                                +-dwc_sleep_cb_t sleep
                                                                                +-dwc_resume_cb_t resume
                                                                                +-dwc_reset_cb_t reset
                                                                                +-dwc_hnp_params_changed_cb_t hnp_changed
                                                                                +-cfi_setup_cb_t cfi_setup
                                                                                +-

                                                                                Detailed Description

                                                                                +-Function Driver Ops Data Structure. +-

                                                                                +- +-

                                                                                +-Definition at line 116 of file dwc_otg_pcd_if.h.

                                                                                The documentation for this struct was generated from the following file: +-
                                                                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__pcd__request.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__pcd__request.html 2013-07-26 19:34:43.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,59 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_pcd_request Struct Reference +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                dwc_otg_pcd_request Struct Reference

                                                                                DWC_otg request structure. +-More... +-

                                                                                +-#include <dwc_otg_pcd.h> +-

                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-

                                                                                Public Member Functions

                                                                                +- DWC_CIRCLEQ_ENTRY (dwc_otg_pcd_request) queue_entry

                                                                                Data Fields

                                                                                +-void * priv
                                                                                +-void * buf
                                                                                +-dwc_dma_t dma
                                                                                +-uint32_t length
                                                                                +-uint32_t actual
                                                                                +-unsigned sent_zlp:1
                                                                                +-uint8_t * dw_align_buf
                                                                                 Used instead of original buffer if it(physical address) is not dword-aligned.
                                                                                +-dwc_dma_t dw_align_buf_dma
                                                                                +-

                                                                                Detailed Description

                                                                                +-DWC_otg request structure. +-

                                                                                +-This structure is a list of requests. +-

                                                                                +- +-

                                                                                +-Definition at line 129 of file dwc_otg_pcd.h.

                                                                                The documentation for this struct was generated from the following file: +-
                                                                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__qh.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__qh.html 2013-07-26 19:34:43.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,308 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_qh Struct Reference +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                dwc_otg_qh Struct Reference

                                                                                A Queue Head (QH) holds the static characteristics of an endpoint and maintains a list of transfers (QTDs) for that endpoint. +-More... +-

                                                                                +-#include <dwc_otg_hcd.h> +-

                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-

                                                                                Data Fields

                                                                                uint8_t ep_type
                                                                                 Endpoint type.
                                                                                +-uint8_t ep_is_in
                                                                                +-uint16_t maxp
                                                                                 wMaxPacketSize Field of Endpoint Descriptor.
                                                                                uint8_t dev_speed
                                                                                 Device speed.
                                                                                uint8_t data_toggle
                                                                                 Determines the PID of the next data packet for non-control transfers.
                                                                                +-uint8_t ping_state
                                                                                 Ping state if 1.
                                                                                dwc_otg_qtd_list qtd_list
                                                                                 List of QTDs for this QH.
                                                                                +-dwc_hc * channel
                                                                                 Host channel currently processing transfers for this QH.
                                                                                +-uint8_t do_split
                                                                                 Full/low speed endpoint on high-speed hub requires split.
                                                                                uint8_t * dw_align_buf
                                                                                 Used instead of original buffer if it(physical address) is not dword-aligned.
                                                                                +-dwc_dma_t dw_align_buf_dma
                                                                                +-dwc_list_link_t qh_list_entry
                                                                                 Entry for QH in either the periodic or non-periodic schedule.
                                                                                Periodic schedule information
                                                                                +-uint16_t usecs
                                                                                 Bandwidth in microseconds per (micro)frame.
                                                                                +-uint16_t interval
                                                                                 Interval between transfers in (micro)frames.
                                                                                uint16_t sched_frame
                                                                                 (micro)frame to initialize a periodic transfer.
                                                                                +-uint16_t start_split_frame
                                                                                 (micro)frame at which last start split was initialized.
                                                                                Descriptor DMA support
                                                                                +-dwc_otg_host_dma_desc_t * desc_list
                                                                                 Descriptor List.
                                                                                +-dwc_dma_t desc_list_dma
                                                                                 Descriptor List physical address.
                                                                                uint32_t * n_bytes
                                                                                 Xfer Bytes array.
                                                                                +-uint16_t ntd
                                                                                 Actual number of transfer descriptors in a list.
                                                                                +-uint8_t td_first
                                                                                 First activated isochronous transfer descriptor index.
                                                                                +-uint8_t td_last
                                                                                 Last activated isochronous transfer descriptor index.
                                                                                +-

                                                                                Detailed Description

                                                                                +-A Queue Head (QH) holds the static characteristics of an endpoint and maintains a list of transfers (QTDs) for that endpoint. +-

                                                                                +-A QH structure may be entered in either the non-periodic or periodic schedule. +-

                                                                                +- +-

                                                                                +-Definition at line 262 of file dwc_otg_hcd.h.

                                                                                Field Documentation

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                uint8_t dwc_otg_qh::ep_type
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Endpoint type. +-

                                                                                +-One of the following values:

                                                                                  +-
                                                                                • UE_CONTROL
                                                                                • UE_BULK
                                                                                • UE_INTERRUPT
                                                                                • UE_ISOCHRONOUS
                                                                                +- +-

                                                                                +-Definition at line 271 of file dwc_otg_hcd.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                uint8_t dwc_otg_qh::dev_speed
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Device speed. +-

                                                                                +-One of the following values:

                                                                                  +-
                                                                                • DWC_OTG_EP_SPEED_LOW
                                                                                • DWC_OTG_EP_SPEED_FULL
                                                                                • DWC_OTG_EP_SPEED_HIGH
                                                                                +- +-

                                                                                +-Definition at line 284 of file dwc_otg_hcd.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                uint8_t dwc_otg_qh::data_toggle
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Determines the PID of the next data packet for non-control transfers. +-

                                                                                +-Ignored for control transfers.
                                                                                +- One of the following values:

                                                                                  +-
                                                                                • DWC_OTG_HC_PID_DATA0
                                                                                • DWC_OTG_HC_PID_DATA1
                                                                                +- +-

                                                                                +-Definition at line 293 of file dwc_otg_hcd.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                struct dwc_otg_qtd_list dwc_otg_qh::qtd_list
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-List of QTDs for this QH. +-

                                                                                +- +-

                                                                                +-Definition at line 301 of file dwc_otg_hcd.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                uint16_t dwc_otg_qh::sched_frame
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-(micro)frame to initialize a periodic transfer. +-

                                                                                +-The transfer executes in the following (micro)frame. +-

                                                                                +-Definition at line 322 of file dwc_otg_hcd.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                uint8_t* dwc_otg_qh::dw_align_buf
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Used instead of original buffer if it(physical address) is not dword-aligned. +-

                                                                                +- +-

                                                                                +-Definition at line 333 of file dwc_otg_hcd.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                uint32_t* dwc_otg_qh::n_bytes
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Xfer Bytes array. +-

                                                                                +-Each element corresponds to a descriptor and indicates original XferSize size value for the descriptor. +-

                                                                                +-Definition at line 353 of file dwc_otg_hcd.h.

                                                                                +-

                                                                                The documentation for this struct was generated from the following file: +-
                                                                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__qtd.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/structdwc__otg__qtd.html 2013-07-26 19:34:43.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,195 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_qtd Struct Reference +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                dwc_otg_qtd Struct Reference

                                                                                A Queue Transfer Descriptor (QTD) holds the state of a bulk, control, interrupt, or isochronous transfer. +-More... +-

                                                                                +-#include <dwc_otg_hcd.h> +-

                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-

                                                                                Public Member Functions

                                                                                +- DWC_CIRCLEQ_ENTRY (dwc_otg_qtd) qtd_list_entry
                                                                                 This list of QTDs.

                                                                                Data Fields

                                                                                uint8_t data_toggle
                                                                                 Determines the PID of the next data packet for the data phase of control transfers.
                                                                                +-dwc_otg_control_phase_e control_phase
                                                                                 Current phase for control transfers (Setup, Data, or Status).
                                                                                +-uint8_t complete_split
                                                                                 Keep track of the current split type for FS/LS endpoints on a HS Hub.
                                                                                +-uint32_t ssplit_out_xfer_count
                                                                                 How many bytes transferred during SSPLIT OUT.
                                                                                uint8_t error_count
                                                                                 Holds the number of bus errors that have occurred for a transaction within this transfer.
                                                                                uint16_t isoc_frame_index
                                                                                 Index of the next frame descriptor for an isochronous transfer.
                                                                                +-uint8_t isoc_split_pos
                                                                                 Position of the ISOC split on full/low speed.
                                                                                +-uint16_t isoc_split_offset
                                                                                 Position of the ISOC split in the buffer for the current frame.
                                                                                +-dwc_otg_hcd_urb * urb
                                                                                 URB for this transfer.
                                                                                +-dwc_otg_qh * qh
                                                                                +-uint8_t in_process
                                                                                 Indicates if this QTD is currently processed by HW.
                                                                                +-uint8_t n_desc
                                                                                 Number of DMA descriptors for this QTD.
                                                                                uint16_t isoc_frame_index_last
                                                                                 Last activated frame(packet) index.
                                                                                +-

                                                                                Detailed Description

                                                                                +-A Queue Transfer Descriptor (QTD) holds the state of a bulk, control, interrupt, or isochronous transfer. +-

                                                                                +-A single QTD is created for each URB (of one of these types) submitted to the HCD. The transfer associated with a QTD may require one or multiple transactions.

                                                                                +-A QTD is linked to a Queue Head, which is entered in either the non-periodic or periodic schedule for execution. When a QTD is chosen for execution, some or all of its transactions may be executed. After execution, the state of the QTD is updated. The QTD may be retired if all its transactions are complete or if an error occurred. Otherwise, it remains in the schedule so more transactions can be executed later. +-

                                                                                +- +-

                                                                                +-Definition at line 192 of file dwc_otg_hcd.h.

                                                                                Field Documentation

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                uint8_t dwc_otg_qtd::data_toggle
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Determines the PID of the next data packet for the data phase of control transfers. +-

                                                                                +-Ignored for other transfer types.
                                                                                +- One of the following values:

                                                                                  +-
                                                                                • DWC_OTG_HC_PID_DATA0
                                                                                • DWC_OTG_HC_PID_DATA1
                                                                                +- +-

                                                                                +-Definition at line 200 of file dwc_otg_hcd.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                uint8_t dwc_otg_qtd::error_count
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Holds the number of bus errors that have occurred for a transaction within this transfer. +-

                                                                                +- +-

                                                                                +-Definition at line 216 of file dwc_otg_hcd.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                uint16_t dwc_otg_qtd::isoc_frame_index
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Index of the next frame descriptor for an isochronous transfer. +-

                                                                                +-A frame descriptor describes the buffer position and length of the data to be transferred in the next scheduled (micro)frame of an isochronous transfer. It also holds status for that transaction. The frame index starts at 0. +-

                                                                                +-Definition at line 225 of file dwc_otg_hcd.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                uint16_t dwc_otg_qtd::isoc_frame_index_last
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Last activated frame(packet) index. +-

                                                                                +-Used in Descriptor DMA mode only. +-

                                                                                +-Definition at line 251 of file dwc_otg_hcd.h.

                                                                                +-

                                                                                The documentation for this struct was generated from the following file: +-
                                                                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/structiso__pkt__info.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/structiso__pkt__info.html 2013-07-26 19:34:43.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,37 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: iso_pkt_info Struct Reference +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                iso_pkt_info Struct Reference

                                                                                Information for each ISOC packet. +-More... +-

                                                                                +-#include <dwc_otg_cil.h> +-

                                                                                +- +- +- +- +- +- +- +- +- +-

                                                                                Data Fields

                                                                                +-uint32_t offset
                                                                                +-uint32_t length
                                                                                +-int32_t status
                                                                                +-

                                                                                Detailed Description

                                                                                +-Information for each ISOC packet. +-

                                                                                +- +-

                                                                                +-Definition at line 81 of file dwc_otg_cil.h.

                                                                                The documentation for this struct was generated from the following file: +-
                                                                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/todo.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/todo.html 2013-07-26 19:34:43.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,229 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: Todo List +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                Todo List

                                                                                +-
                                                                                Global srp_show (struct device *_dev, struct device_attribute *attr, char *buf)
                                                                                +-
                                                                                Add code to initiate the SRP.
                                                                                +-
                                                                                +-

                                                                                +-

                                                                                +-
                                                                                Global buspower_show (struct device *_dev, struct device_attribute *attr, char *buf)
                                                                                +-
                                                                                Need to do more for power on/off?
                                                                                +-
                                                                                +-

                                                                                +-

                                                                                +-
                                                                                Global bussuspend_show (struct device *_dev, struct device_attribute *attr, char *buf)
                                                                                +-
                                                                                Need to do more for suspend?
                                                                                +-
                                                                                +-

                                                                                +-

                                                                                +-
                                                                                Global dwc_otg_enable_device_interrupts (dwc_otg_core_if_t *core_if)
                                                                                +-
                                                                                NGS: Should this be a module parameter?
                                                                                +-
                                                                                +-

                                                                                +-

                                                                                +-
                                                                                Global dwc_otg_core_dev_init (dwc_otg_core_if_t *core_if)
                                                                                +-
                                                                                NGS: Fix Periodic FIFO Sizing!

                                                                                +-Finish debug of this

                                                                                +-- if the condition needed to be checked or in any case all pending interrutps should be cleared?

                                                                                +-
                                                                                +-

                                                                                +-

                                                                                +-
                                                                                Global dwc_otg_ep0_continue_transfer (dwc_otg_core_if_t *core_if, dwc_ep_t *ep)
                                                                                +-
                                                                                Should there be check for room in the Tx Status Queue. If not remove the code above this comment.
                                                                                +-
                                                                                +-

                                                                                +-

                                                                                +-
                                                                                Global dwc_otg_ep_write_packet (dwc_otg_core_if_t *core_if, dwc_ep_t *ep, int dma)
                                                                                +-
                                                                                NGS Where are the Periodic Tx FIFO addresses intialized? What should this be?
                                                                                +-
                                                                                +-

                                                                                +-

                                                                                +-
                                                                                Global dwc_otg_read_packet (dwc_otg_core_if_t *core_if, uint8_t *dest, uint16_t bytes)
                                                                                +-
                                                                                Account for the case where _dest is not dword aligned. This requires reading data from the FIFO into a uint32_t temp buffer, then moving it into the data buffer.
                                                                                +-
                                                                                +-

                                                                                +-

                                                                                +-
                                                                                Global dwc_otg_handle_disconnect_intr (dwc_otg_core_if_t *core_if)
                                                                                +-
                                                                                Consolidate this if statement.
                                                                                +-
                                                                                +-

                                                                                +-

                                                                                +-
                                                                                Global dwc_otg_read_common_intr (dwc_otg_core_if_t *core_if)
                                                                                +-
                                                                                : The port interrupt occurs while in device mode. Added code to CIL to clear the interrupt for now!
                                                                                +-
                                                                                +-

                                                                                +-

                                                                                +-
                                                                                Global MODULE_PARM_DESC (max_transfer_size,"The maximum transfer size supported in bytes 2047-65535")
                                                                                +-
                                                                                Set the max to 512K, modify checks
                                                                                +-
                                                                                +-

                                                                                +-

                                                                                +-
                                                                                Global dwc_otg_hcd_hub_control (dwc_otg_hcd_t *dwc_otg_hcd, uint16_t typeReq, uint16_t wValue, uint16_t wIndex, uint8_t *buf, uint16_t wLength)
                                                                                +-
                                                                                - check how sw can wait for 1 sec to check asesvld???
                                                                                +-
                                                                                +-

                                                                                +-

                                                                                +-
                                                                                Global dwc_otg_hcd_handle_intr (dwc_otg_hcd_t *dwc_otg_hcd)
                                                                                +-
                                                                                Implement i2cintr handler.
                                                                                +-
                                                                                +-

                                                                                +-

                                                                                +-
                                                                                Global dwc_otg_hcd_handle_port_intr (dwc_otg_hcd_t *dwc_otg_hcd)
                                                                                +-
                                                                                - check if steps performed in 'else' block should be perfromed regardles adp
                                                                                +-
                                                                                +-

                                                                                +-

                                                                                +-
                                                                                Global dwc_otg_hcd_qh_create (dwc_otg_hcd_t *hcd, dwc_otg_hcd_urb_t *urb, int atomic_alloc)
                                                                                +-
                                                                                add memflags argument
                                                                                +-
                                                                                +-

                                                                                +-

                                                                                +-
                                                                                Global dwc_otg_hcd_complete_xfer_ddma (dwc_otg_hcd_t *hcd, dwc_hc_t *hc, dwc_otg_hc_regs_t *hc_regs, dwc_otg_halt_status_e halt_status)
                                                                                +-
                                                                                Consider the case when period exceeds FrameList size. Frame Rollover interrupt should be used.
                                                                                +-
                                                                                +-

                                                                                +-

                                                                                +-
                                                                                Global handle_hc_nyet_intr (dwc_otg_hcd_t *hcd, dwc_hc_t *hc, dwc_otg_hc_regs_t *hc_regs, dwc_otg_qtd_t *qtd)
                                                                                +-
                                                                                add support for isoc release
                                                                                +-
                                                                                +-

                                                                                +-

                                                                                +-
                                                                                Global handle_hc_chhltd_intr_dma (dwc_otg_hcd_t *hcd, dwc_hc_t *hc, dwc_otg_hc_regs_t *hc_regs, dwc_otg_qtd_t *qtd)
                                                                                +-
                                                                                This is here because of a possible hardware bug. Spec says that on SPLIT-ISOC OUT transfers in DMA mode that a HALT interrupt w/ACK bit set should occur, but I only see the XFERCOMP bit, even with it masked out. This is a workaround for that behavior. Should fix this when hardware is fixed.
                                                                                +-
                                                                                +-

                                                                                +-

                                                                                +-
                                                                                Global qh_init (dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh, dwc_otg_hcd_urb_t *urb)
                                                                                +-
                                                                                Account for split transfers in the bus time.
                                                                                +-
                                                                                +-

                                                                                +-

                                                                                +-
                                                                                File dwc_otg_pcd.c
                                                                                +-
                                                                                Add Device Mode test modes (Test J mode, Test K mode, etc).

                                                                                +-Does it work when the request size is greater than DEPTSIZ transfer size

                                                                                +-
                                                                                +-

                                                                                +-

                                                                                +-
                                                                                Global dwc_otg_pcd_iso_ep_start (dwc_otg_pcd_t *pcd, void *ep_handle, uint8_t *buf0, uint8_t *buf1, dwc_dma_t dma0, dwc_dma_t dma1, int sync_frame, int dp_frame, int data_per_frame, int start_frame, int buf_proc_intrvl, void *req_handle, int atomic_alloc)
                                                                                +-
                                                                                - pattern data support is to be implemented in the future
                                                                                +-
                                                                                +-

                                                                                +-

                                                                                +-
                                                                                Global dwc_otg_pcd_reinit (dwc_otg_pcd_t *pcd)
                                                                                +-
                                                                                NGS: Add direction to EP, based on contents of HWCFG1. Need a copy of HWCFG1 in pcd structure? sprintf(";r

                                                                                +-NGS: Add direction to EP, based on contents of HWCFG1. Need a copy of HWCFG1 in pcd structure? sprintf(";r

                                                                                +-
                                                                                +-

                                                                                +-

                                                                                +-
                                                                                Global dwc_otg_pcd_ep_queue (dwc_otg_pcd_t *pcd, void *ep_handle, uint8_t *buf, dwc_dma_t dma_buf, uint32_t buflen, int zero, void *req_handle, int atomic_alloc)
                                                                                +-
                                                                                NGS Create a function for this.
                                                                                +-
                                                                                +-

                                                                                +-

                                                                                +-
                                                                                Global do_test_mode (void *data)
                                                                                +-
                                                                                This has not been tested since the tasklet struct was put into the PCD struct!
                                                                                +-
                                                                                +-

                                                                                +-

                                                                                +-
                                                                                Global dwc_otg_pcd_handle_rx_status_q_level_intr (dwc_otg_pcd_t *pcd)
                                                                                +-
                                                                                NGS Check for buffer overflow?
                                                                                +-
                                                                                +-

                                                                                +-

                                                                                +-
                                                                                Global get_ep_of_last_in_token (dwc_otg_core_if_t *core_if)
                                                                                +-
                                                                                Find a simpler way to calculate the max queue position.
                                                                                +-
                                                                                +-

                                                                                +-

                                                                                +-
                                                                                Global dwc_otg_pcd_stop (dwc_otg_pcd_t *pcd)
                                                                                +-
                                                                                NGS Flush Periodic FIFOs
                                                                                +-
                                                                                +-

                                                                                +-

                                                                                +-
                                                                                Global ep0_out_start (dwc_otg_core_if_t *core_if, dwc_otg_pcd_t *pcd)
                                                                                +-
                                                                                NGS: Update the comments from the HW FS.
                                                                                +-
                                                                                +-

                                                                                +-

                                                                                +-
                                                                                Global ep0_out_start (dwc_otg_core_if_t *core_if, dwc_otg_pcd_t *pcd)
                                                                                +-
                                                                                dma needs to handle multiple setup packets (up to 3)
                                                                                +-
                                                                                +-

                                                                                +-

                                                                                +-
                                                                                Global do_gadget_setup (dwc_otg_pcd_t *pcd, usb_device_request_t *ctrl)
                                                                                +-
                                                                                This is a g_file_storage gadget driver specific workaround: a DELAYED_STATUS result from the fsg_setup routine will result in the gadget queueing a EP0 IN status phase for a two-stage control transfer. Exactly the same as a SET_CONFIGURATION/SET_INTERFACE except that this is a class specific request. Need a generic way to know when the gadget driver will queue the status phase. Can we assume when we call the gadget driver setup() function that it will always queue and require the following flag? Need to look into this.
                                                                                +-
                                                                                +-

                                                                                +-

                                                                                +-
                                                                                Global pcd_clear_halt (dwc_otg_pcd_t *pcd, dwc_otg_pcd_ep_t *ep)
                                                                                +-
                                                                                FIXME: this causes an EP mismatch in DMA mode. epmismatch not yet implemented.
                                                                                +-
                                                                                +-

                                                                                +-

                                                                                +-
                                                                                Global do_get_status (dwc_otg_pcd_t *pcd)
                                                                                +-
                                                                                check for EP stall
                                                                                +-
                                                                                +-

                                                                                +-

                                                                                +-
                                                                                Global do_set_feature (dwc_otg_pcd_t *pcd)
                                                                                +-
                                                                                This has not been tested since the tasklet struct was put into the PCD struct!

                                                                                +-Is the gotgctl.devhnpen cleared by a USB Reset?

                                                                                +-
                                                                                +-

                                                                                +-

                                                                                +-
                                                                                Global do_clear_feature (dwc_otg_pcd_t *pcd)
                                                                                +-
                                                                                Add CLEAR_FEATURE for TEST modes.
                                                                                +-
                                                                                +-

                                                                                +-

                                                                                +-
                                                                                Global pcd_setup (dwc_otg_pcd_t *pcd)
                                                                                +-
                                                                                handle > 1 setup packet , assert error for now

                                                                                +-NGS: Handle bad setup packet?

                                                                                +-
                                                                                +-

                                                                                +-

                                                                                +-
                                                                                Global handle_in_ep_timeout_intr (dwc_otg_pcd_t *pcd, const uint32_t epnum)
                                                                                +-
                                                                                NGS Check EP type. Implement for Periodic EPs
                                                                                +-
                                                                                +-

                                                                                +-

                                                                                +-
                                                                                Global handle_in_ep_nak_intr (dwc_otg_pcd_t *pcd, const uint32_t epnum)
                                                                                +-
                                                                                implement ISR
                                                                                +-
                                                                                +-

                                                                                +-

                                                                                +-
                                                                                Global handle_out_ep_babble_intr (dwc_otg_pcd_t *pcd, const uint32_t epnum)
                                                                                +-
                                                                                implement ISR
                                                                                +-
                                                                                +-

                                                                                +-

                                                                                +-
                                                                                Global handle_out_ep_nak_intr (dwc_otg_pcd_t *pcd, const uint32_t epnum)
                                                                                +-
                                                                                implement ISR
                                                                                +-
                                                                                +-

                                                                                +-

                                                                                +-
                                                                                Global handle_out_ep_nyet_intr (dwc_otg_pcd_t *pcd, const uint32_t epnum)
                                                                                +-
                                                                                implement ISR
                                                                                +-
                                                                                +-

                                                                                +-

                                                                                +-
                                                                                Global gadget_add_eps (struct gadget_wrapper *d)
                                                                                +-
                                                                                NGS: What should the max packet size be set to here? Before EP type is set?

                                                                                +-NGS: What should the max packet size be set to here? Before EP type is set?

                                                                                +-NGS: What should the max packet size be set to here? Before EP type is set?

                                                                                +-
                                                                                +-

                                                                                +-

                                                                                +-
                                                                                Global dwc_otg_pcd_gadget_release (struct device *dev)
                                                                                +-
                                                                                Should this do something? Should it free the PCD?
                                                                                +-
                                                                                +-
                                                                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/tree.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/tree.html 2013-07-26 19:34:43.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,246 +0,0 @@ +- +- +- +- +- +- +- TreeView +- +- +- +- +- +-
                                                                                +-

                                                                                DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver

                                                                                +-
                                                                                +-

                                                                                o*Main Page

                                                                                +-

                                                                                o+File List

                                                                                +- +-

                                                                                o+Data Structures

                                                                                +-
                                                                                +-

                                                                                |o*_ddma_align_buffer_setup

                                                                                +-

                                                                                |o*_ddma_concat_buffer_setup

                                                                                +-

                                                                                |o*_ddma_concat_buffer_setup_hdr

                                                                                +-

                                                                                |o*_ddma_sg_buffer_setup

                                                                                +-

                                                                                |o*_rx_fifo_size_setup

                                                                                +-

                                                                                |o*_tx_fifo_size_setup

                                                                                +-

                                                                                |o*adpctl_data

                                                                                +-

                                                                                |o*cfi_all_features_header

                                                                                +-

                                                                                |o*cfi_ep

                                                                                +-

                                                                                |o*cfi_feature_desc_header

                                                                                +-

                                                                                |o*cfi_ops

                                                                                +-

                                                                                |o*cfi_string

                                                                                +-

                                                                                |o*cfi_usb_ctrlrequest

                                                                                +-

                                                                                |o*daint_data

                                                                                +-

                                                                                |o*dcfg_data

                                                                                +-

                                                                                |o*dctl_data

                                                                                +-

                                                                                |o*depctl_data

                                                                                +-

                                                                                |o*deptsiz0_data

                                                                                +-

                                                                                |o*deptsiz_data

                                                                                +-

                                                                                |o*dev_dma_desc_sts

                                                                                +-

                                                                                |o*device_grxsts_data

                                                                                +-

                                                                                |o*diepint_data

                                                                                +-

                                                                                |o*doepint_data

                                                                                +-

                                                                                |o*dsts_data

                                                                                +-

                                                                                |o*dthrctl_data

                                                                                +-

                                                                                |o*dtknq1_data

                                                                                +-

                                                                                |o*dtxfsts_data

                                                                                +-

                                                                                |o*dwc_ep

                                                                                +-

                                                                                |o*dwc_hc

                                                                                +-

                                                                                |o*dwc_otg_cil_callbacks

                                                                                +-

                                                                                |o*dwc_otg_core_global_regs

                                                                                +-

                                                                                |o*dwc_otg_core_if

                                                                                +-

                                                                                |o*dwc_otg_core_params

                                                                                +-

                                                                                |o*dwc_otg_dev_dma_desc

                                                                                +-

                                                                                |o*dwc_otg_dev_global_regs

                                                                                +-

                                                                                |o*dwc_otg_dev_if

                                                                                +-

                                                                                |o*dwc_otg_dev_in_ep_regs

                                                                                +-

                                                                                |o*dwc_otg_dev_out_ep_regs

                                                                                +-

                                                                                |o*dwc_otg_device

                                                                                +-

                                                                                |o*dwc_otg_hc_regs

                                                                                +-

                                                                                |o*dwc_otg_hcd

                                                                                +-

                                                                                |o*dwc_otg_hcd::dwc_otg_hcd_internal_flags

                                                                                +-

                                                                                |o*dwc_otg_host_dma_desc

                                                                                +-

                                                                                |o*dwc_otg_host_global_regs

                                                                                +-

                                                                                |o*dwc_otg_host_if

                                                                                +-

                                                                                |o*dwc_otg_pcd

                                                                                +-

                                                                                |o*dwc_otg_pcd_ep

                                                                                +-

                                                                                |o*dwc_otg_pcd_function_ops

                                                                                +-

                                                                                |o*dwc_otg_pcd_request

                                                                                +-

                                                                                |o*dwc_otg_qh

                                                                                +-

                                                                                |o*dwc_otg_qtd

                                                                                +-

                                                                                |o*fifosize_data

                                                                                +-

                                                                                |o*gahbcfg_data

                                                                                +-

                                                                                |o*gdfifocfg_data

                                                                                +-

                                                                                |o*ggpio_data

                                                                                +-

                                                                                |o*gi2cctl_data

                                                                                +-

                                                                                |o*gintmsk_data

                                                                                +-

                                                                                |o*gintsts_data

                                                                                +-

                                                                                |o*glpmctl_data

                                                                                +-

                                                                                |o*gnptxsts_data

                                                                                +-

                                                                                |o*gotgctl_data

                                                                                +-

                                                                                |o*gotgint_data

                                                                                +-

                                                                                |o*gpvndctl_data

                                                                                +-

                                                                                |o*gpwrdn_data

                                                                                +-

                                                                                |o*grstctl_data

                                                                                +-

                                                                                |o*gsnpsid_data

                                                                                +-

                                                                                |o*guid_data

                                                                                +-

                                                                                |o*gusbcfg_data

                                                                                +-

                                                                                |o*haint_data

                                                                                +-

                                                                                |o*haintmsk_data

                                                                                +-

                                                                                |o*hcchar_data

                                                                                +-

                                                                                |o*hcdma_data

                                                                                +-

                                                                                |o*hcfg_data

                                                                                +-

                                                                                |o*hcint_data

                                                                                +-

                                                                                |o*hcintmsk_data

                                                                                +-

                                                                                |o*hctsiz_data

                                                                                +-

                                                                                |o*hfir_data

                                                                                +-

                                                                                |o*hfnum_data

                                                                                +-

                                                                                |o*host_dma_desc_sts

                                                                                +-

                                                                                |o*host_grxsts_data

                                                                                +-

                                                                                |o*hprt0_data

                                                                                +-

                                                                                |o*hwcfg1_data

                                                                                +-

                                                                                |o*hwcfg2_data

                                                                                +-

                                                                                |o*hwcfg3_data

                                                                                +-

                                                                                |o*hwcfg4_data

                                                                                +-

                                                                                |o*iso_pkt_info

                                                                                +-

                                                                                |\*pcgcctl_data

                                                                                +-
                                                                                +-

                                                                                o*Data Fields

                                                                                +-

                                                                                o*Globals

                                                                                +-

                                                                                \+Related Pages

                                                                                +- +-
                                                                                +-
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/unionadpctl__data.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/unionadpctl__data.html 2013-07-26 19:34:43.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,440 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: adpctl_data Union Reference +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                adpctl_data Union Reference

                                                                                This union represents the bit fields of the Core ADP Timer, Control and Status Register (ADPTIMCTLSTS). +-More... +-

                                                                                +-#include <dwc_otg_regs.h> +-

                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-

                                                                                Data Fields

                                                                                +-uint32_t d32
                                                                                 raw register data
                                                                                +-struct {
                                                                                   unsigned   prb_dschg:2
                                                                                 Probe Discharge (PRB_DSCHG) These bits set the times for TADP_DSCHG.
                                                                                   unsigned   prb_delta:2
                                                                                 Probe Delta (PRB_DELTA) These bits set the resolution for RTIM value.
                                                                                   unsigned   prb_per:2
                                                                                 Probe Period (PRB_PER) These bits sets the TADP_PRD as shown in Figure 4 as follows: 2'b00 - 0.625 to 0.925 sec (typical 0.775 sec) 2'b01 - 1.25 to 1.85 sec (typical 1.55 sec) 2'b10 - 1.9 to 2.6 sec (typical 2.275 sec) 2'b11 - Reserved.
                                                                                   unsigned   rtim:11
                                                                                 These bits capture the latest time it took for VBUS to ramp from VADP_SINK to VADP_PRB.
                                                                                   unsigned   enaprb:1
                                                                                 Enable Probe (EnaPrb) When programmed to 1'b1, the core performs a probe operation.
                                                                                   unsigned   enasns:1
                                                                                 Enable Sense (EnaSns) When programmed to 1'b1, the core performs a Sense operation.
                                                                                   unsigned   adpres:1
                                                                                 ADP Reset (ADPRes) When set, ADP controller is reset.
                                                                                   unsigned   adpen:1
                                                                                 ADP Enable (ADPEn) When set, the core performs either ADP probing or sensing based on EnaPrb or EnaSns.
                                                                                   unsigned   adp_prb_int:1
                                                                                 ADP Probe Interrupt (ADP_PRB_INT) When this bit is set, it means that the VBUS voltage is greater than VADP_PRB or VADP_PRB is reached.
                                                                                   unsigned   adp_sns_int:1
                                                                                 ADP Sense Interrupt (ADP_SNS_INT) When this bit is set, it means that the VBUS voltage is greater than VADP_SNS value or VADP_SNS is reached.
                                                                                   unsigned   adp_tmout_int:1
                                                                                 ADP Tomeout Interrupt (ADP_TMOUT_INT) This bit is relevant only for an ADP probe.
                                                                                   unsigned   adp_prb_int_msk:1
                                                                                 ADP Probe Interrupt Mask (ADP_PRB_INT_MSK) When this bit is set, it unmasks the interrupt due to ADP_PRB_INT.
                                                                                   unsigned   adp_sns_int_msk:1
                                                                                 ADP Sense Interrupt Mask (ADP_SNS_INT_MSK) When this bit is set, it unmasks the interrupt due to ADP_SNS_INT.
                                                                                   unsigned   adp_tmout_int_msk:1
                                                                                 ADP Timoeout Interrupt Mask (ADP_TMOUT_MSK) When this bit is set, it unmasks the interrupt due to ADP_TMOUT_INT.
                                                                                   unsigned   ar:2
                                                                                 Access Request 2'b00 - Read/Write Valid (updated by the core) 2'b01 - Read 2'b00 - Write 2'b00 - Reserved.
                                                                                   unsigned   reserved29_31:3
                                                                                 Reserved.
                                                                                } b
                                                                                 register bits
                                                                                +-

                                                                                Detailed Description

                                                                                +-This union represents the bit fields of the Core ADP Timer, Control and Status Register (ADPTIMCTLSTS). +-

                                                                                +-Set the bits using bit fields then write the d32 value to the register. +-

                                                                                +- +-

                                                                                +-Definition at line 955 of file dwc_otg_regs.h.

                                                                                Field Documentation

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                unsigned adpctl_data::prb_dschg
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Probe Discharge (PRB_DSCHG) These bits set the times for TADP_DSCHG. +-

                                                                                +-These bits are defined as follows: 2'b00 - 4 msec 2'b01 - 8 msec 2'b10 - 16 msec 2'b11 - 32 msec +-

                                                                                +-Definition at line 968 of file dwc_otg_regs.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                unsigned adpctl_data::prb_delta
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Probe Delta (PRB_DELTA) These bits set the resolution for RTIM value. +-

                                                                                +-The bits are defined in units of 32 kHz clock cycles as follows: 2'b00 - 1 cycles 2'b01 - 2 cycles 2'b10 - 3 cycles 2'b11 - 4 cycles For example if this value is chosen to 2'b01, it means that RTIM increments for every 3(three) 32Khz clock cycles. +-

                                                                                +-Definition at line 979 of file dwc_otg_regs.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                unsigned adpctl_data::rtim
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-These bits capture the latest time it took for VBUS to ramp from VADP_SINK to VADP_PRB. +-

                                                                                +-0x000 - 1 cycles 0x001 - 2 cycles 0x002 - 3 cycles etc 0x7FF - 2048 cycles A time of 1024 cycles at 32 kHz corresponds to a time of 32 msec. +-

                                                                                +-Definition at line 997 of file dwc_otg_regs.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                unsigned adpctl_data::enaprb
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Enable Probe (EnaPrb) When programmed to 1'b1, the core performs a probe operation. +-

                                                                                +-This bit is valid only if OTG_Ver = 1'b1. +-

                                                                                +-Definition at line 1002 of file dwc_otg_regs.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                unsigned adpctl_data::enasns
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Enable Sense (EnaSns) When programmed to 1'b1, the core performs a Sense operation. +-

                                                                                +-This bit is valid only if OTG_Ver = 1'b1. +-

                                                                                +-Definition at line 1007 of file dwc_otg_regs.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                unsigned adpctl_data::adpres
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-ADP Reset (ADPRes) When set, ADP controller is reset. +-

                                                                                +-This bit is valid only if OTG_Ver = 1'b1. +-

                                                                                +-Definition at line 1012 of file dwc_otg_regs.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                unsigned adpctl_data::adpen
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-ADP Enable (ADPEn) When set, the core performs either ADP probing or sensing based on EnaPrb or EnaSns. +-

                                                                                +-This bit is valid only if OTG_Ver = 1'b1. +-

                                                                                +-Definition at line 1018 of file dwc_otg_regs.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                unsigned adpctl_data::adp_prb_int
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-ADP Probe Interrupt (ADP_PRB_INT) When this bit is set, it means that the VBUS voltage is greater than VADP_PRB or VADP_PRB is reached. +-

                                                                                +-This bit is valid only if OTG_Ver = 1'b1. +-

                                                                                +-Definition at line 1024 of file dwc_otg_regs.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                unsigned adpctl_data::adp_sns_int
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-ADP Sense Interrupt (ADP_SNS_INT) When this bit is set, it means that the VBUS voltage is greater than VADP_SNS value or VADP_SNS is reached. +-

                                                                                +-This bit is valid only if OTG_Ver = 1'b1. +-

                                                                                +-Definition at line 1031 of file dwc_otg_regs.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                unsigned adpctl_data::adp_tmout_int
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-ADP Tomeout Interrupt (ADP_TMOUT_INT) This bit is relevant only for an ADP probe. +-

                                                                                +-When this bit is set, it means that the ramp time has completed ie ADPCTL.RTIM has reached its terminal value of 0x7FF. This is a debug feature that allows software to read the ramp time after each cycle. This bit is valid only if OTG_Ver = 1'b1. +-

                                                                                +-Definition at line 1040 of file dwc_otg_regs.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                unsigned adpctl_data::adp_prb_int_msk
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-ADP Probe Interrupt Mask (ADP_PRB_INT_MSK) When this bit is set, it unmasks the interrupt due to ADP_PRB_INT. +-

                                                                                +-This bit is valid only if OTG_Ver = 1'b1. +-

                                                                                +-Definition at line 1045 of file dwc_otg_regs.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                unsigned adpctl_data::adp_sns_int_msk
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-ADP Sense Interrupt Mask (ADP_SNS_INT_MSK) When this bit is set, it unmasks the interrupt due to ADP_SNS_INT. +-

                                                                                +-This bit is valid only if OTG_Ver = 1'b1. +-

                                                                                +-Definition at line 1050 of file dwc_otg_regs.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                unsigned adpctl_data::adp_tmout_int_msk
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-ADP Timoeout Interrupt Mask (ADP_TMOUT_MSK) When this bit is set, it unmasks the interrupt due to ADP_TMOUT_INT. +-

                                                                                +-This bit is valid only if OTG_Ver = 1'b1. +-

                                                                                +-Definition at line 1055 of file dwc_otg_regs.h.

                                                                                +-

                                                                                The documentation for this union was generated from the following file: +-
                                                                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/uniondaint__data.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/uniondaint__data.html 2013-07-26 19:34:43.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,119 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: daint_data Union Reference +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                daint_data Union Reference

                                                                                This union represents the bit fields in the Device All EP Interrupt and Mask Registers. +-More... +-

                                                                                +-#include <dwc_otg_regs.h> +-

                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-

                                                                                Data Fields

                                                                                +-uint32_t d32
                                                                                 raw register data
                                                                                +-struct {
                                                                                   unsigned   in:16
                                                                                 IN Endpoint bits.
                                                                                   unsigned   out:16
                                                                                 OUT Endpoint bits.
                                                                                } ep
                                                                                 register bits
                                                                                +-struct {
                                                                                   unsigned   inep0:1
                                                                                 IN Endpoint bits.
                                                                                   unsigned   inep1:1
                                                                                   unsigned   inep2:1
                                                                                   unsigned   inep3:1
                                                                                   unsigned   inep4:1
                                                                                   unsigned   inep5:1
                                                                                   unsigned   inep6:1
                                                                                   unsigned   inep7:1
                                                                                   unsigned   inep8:1
                                                                                   unsigned   inep9:1
                                                                                   unsigned   inep10:1
                                                                                   unsigned   inep11:1
                                                                                   unsigned   inep12:1
                                                                                   unsigned   inep13:1
                                                                                   unsigned   inep14:1
                                                                                   unsigned   inep15:1
                                                                                   unsigned   outep0:1
                                                                                 OUT Endpoint bits.
                                                                                   unsigned   outep1:1
                                                                                   unsigned   outep2:1
                                                                                   unsigned   outep3:1
                                                                                   unsigned   outep4:1
                                                                                   unsigned   outep5:1
                                                                                   unsigned   outep6:1
                                                                                   unsigned   outep7:1
                                                                                   unsigned   outep8:1
                                                                                   unsigned   outep9:1
                                                                                   unsigned   outep10:1
                                                                                   unsigned   outep11:1
                                                                                   unsigned   outep12:1
                                                                                   unsigned   outep13:1
                                                                                   unsigned   outep14:1
                                                                                   unsigned   outep15:1
                                                                                } b
                                                                                +-

                                                                                Detailed Description

                                                                                +-This union represents the bit fields in the Device All EP Interrupt and Mask Registers. +-

                                                                                +-

                                                                                  +-
                                                                                • Read the register into the d32 member then set/clear the bits using the bit elements.
                                                                                +- +-

                                                                                +- +-

                                                                                +-Definition at line 1350 of file dwc_otg_regs.h.

                                                                                The documentation for this union was generated from the following file: +-
                                                                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/uniondcfg__data.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/uniondcfg__data.html 2013-07-26 19:34:43.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,69 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dcfg_data Union Reference +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                dcfg_data Union Reference

                                                                                This union represents the bit fields in the Device Configuration Register. +-More... +-

                                                                                +-#include <dwc_otg_regs.h> +-

                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-

                                                                                Data Fields

                                                                                +-uint32_t d32
                                                                                 raw register data
                                                                                +-struct {
                                                                                   unsigned   devspd:2
                                                                                 Device Speed.
                                                                                   unsigned   nzstsouthshk:1
                                                                                 Non Zero Length Status OUT Handshake.
                                                                                   unsigned   ena32khzs:1
                                                                                   unsigned   devaddr:7
                                                                                 Device Addresses.
                                                                                   unsigned   perfrint:2
                                                                                 Periodic Frame Interval.
                                                                                   unsigned   endevoutnak:1
                                                                                 Enable Device OUT NAK for bulk in DDMA mode.
                                                                                   unsigned   reserved14_17:4
                                                                                   unsigned   epmscnt:5
                                                                                 In Endpoint Mis-match count.
                                                                                   unsigned   descdma:1
                                                                                 Enable Descriptor DMA in Device mode.
                                                                                   unsigned   perschintvl:2
                                                                                   unsigned   resvalid:6
                                                                                } b
                                                                                 register bits
                                                                                +-

                                                                                Detailed Description

                                                                                +-This union represents the bit fields in the Device Configuration Register. +-

                                                                                +-Read the register into the d32 member then set/clear the bits using the bit elements. Write the d32 member to the dcfg register. +-

                                                                                +- +-

                                                                                +-Definition at line 1137 of file dwc_otg_regs.h.

                                                                                The documentation for this union was generated from the following file: +-
                                                                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/uniondctl__data.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/uniondctl__data.html 2013-07-26 19:34:43.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,87 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dctl_data Union Reference +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                dctl_data Union Reference

                                                                                This union represents the bit fields in the Device Control Register. +-More... +-

                                                                                +-#include <dwc_otg_regs.h> +-

                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-

                                                                                Data Fields

                                                                                +-uint32_t d32
                                                                                 raw register data
                                                                                +-struct {
                                                                                   unsigned   rmtwkupsig:1
                                                                                 Remote Wakeup.
                                                                                   unsigned   sftdiscon:1
                                                                                 Soft Disconnect.
                                                                                   unsigned   gnpinnaksts:1
                                                                                 Global Non-Periodic IN NAK Status.
                                                                                   unsigned   goutnaksts:1
                                                                                 Global OUT NAK Status.
                                                                                   unsigned   tstctl:3
                                                                                 Test Control.
                                                                                   unsigned   sgnpinnak:1
                                                                                 Set Global Non-Periodic IN NAK.
                                                                                   unsigned   cgnpinnak:1
                                                                                 Clear Global Non-Periodic IN NAK.
                                                                                   unsigned   sgoutnak:1
                                                                                 Set Global OUT NAK.
                                                                                   unsigned   cgoutnak:1
                                                                                 Clear Global OUT NAK.
                                                                                   unsigned   pwronprgdone:1
                                                                                 Power-On Programming Done.
                                                                                   unsigned   reserved:1
                                                                                 Reserved.
                                                                                   unsigned   gmc:2
                                                                                 Global Multi Count.
                                                                                   unsigned   ifrmnum:1
                                                                                 Ignore Frame Number for ISOC EPs.
                                                                                   unsigned   nakonbble:1
                                                                                 NAK on Babble.
                                                                                   unsigned   encontonbna:1
                                                                                 Enable Continue on BNA.
                                                                                   unsigned   reserved18_31:14
                                                                                } b
                                                                                 register bits
                                                                                +-

                                                                                Detailed Description

                                                                                +-This union represents the bit fields in the Device Control Register. +-

                                                                                +-Read the register into the d32 member then set/clear the bits using the bit elements. +-

                                                                                +- +-

                                                                                +-Definition at line 1176 of file dwc_otg_regs.h.

                                                                                The documentation for this union was generated from the following file: +-
                                                                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/uniondepctl__data.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/uniondepctl__data.html 2013-07-26 19:34:43.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,170 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: depctl_data Union Reference +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                depctl_data Union Reference

                                                                                This union represents the bit fields in the Device EP Control Register. +-More... +-

                                                                                +-#include <dwc_otg_regs.h> +-

                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-

                                                                                Data Fields

                                                                                +-uint32_t d32
                                                                                 raw register data
                                                                                +-struct {
                                                                                   unsigned   mps:11
                                                                                 Maximum Packet Size IN/OUT EPn IN/OUT EP0 - 2 bits 2'b00: 64 Bytes 2'b01: 32 2'b10: 16 2'b11: 8.
                                                                                   unsigned   nextep:4
                                                                                 Next Endpoint IN EPn/IN EP0 OUT EPn/OUT EP0 - reserved.
                                                                                   unsigned   usbactep:1
                                                                                 USB Active Endpoint.
                                                                                   unsigned   dpid:1
                                                                                 Endpoint DPID (INTR/Bulk IN and OUT endpoints) This field contains the PID of the packet going to be received or transmitted on this endpoint.
                                                                                   unsigned   naksts:1
                                                                                 NAK Status.
                                                                                   unsigned   eptype:2
                                                                                 Endpoint Type 2'b00: Control 2'b01: Isochronous 2'b10: Bulk 2'b11: Interrupt.
                                                                                   unsigned   snp:1
                                                                                 Snoop Mode OUT EPn/OUT EP0 IN EPn/IN EP0 - reserved.
                                                                                   unsigned   stall:1
                                                                                 Stall Handshake.
                                                                                   unsigned   txfnum:4
                                                                                 Tx Fifo Number IN EPn/IN EP0 OUT EPn/OUT EP0 - reserved.
                                                                                   unsigned   cnak:1
                                                                                 Clear NAK.
                                                                                   unsigned   snak:1
                                                                                 Set NAK.
                                                                                   unsigned   setd0pid:1
                                                                                 Set DATA0 PID (INTR/Bulk IN and OUT endpoints) Writing to this field sets the Endpoint DPID (DPID) field in this register to DATA0.
                                                                                   unsigned   setd1pid:1
                                                                                 Set DATA1 PID (INTR/Bulk IN and OUT endpoints) Writing to this field sets the Endpoint DPID (DPID) field in this register to DATA1 Set Odd (micro)frame (SetOddFr) (ISO IN and OUT Endpoints) Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to odd (micro) frame.
                                                                                   unsigned   epdis:1
                                                                                 Endpoint Disable.
                                                                                   unsigned   epena:1
                                                                                 Endpoint Enable.
                                                                                } b
                                                                                 register bits
                                                                                +-

                                                                                Detailed Description

                                                                                +-This union represents the bit fields in the Device EP Control Register. +-

                                                                                +-Read the register into the d32 member then set/clear the bits using the bit elements. +-

                                                                                +- +-

                                                                                +-Definition at line 1526 of file dwc_otg_regs.h.

                                                                                Field Documentation

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                unsigned depctl_data::dpid
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Endpoint DPID (INTR/Bulk IN and OUT endpoints) This field contains the PID of the packet going to be received or transmitted on this endpoint. +-

                                                                                +-The application should program the PID of the first packet going to be received or transmitted on this endpoint , after the endpoint is activated. Application use the SetD1PID and SetD0PID fields of this register to program either D0 or D1 PID.

                                                                                +-The encoding for this field is

                                                                                  +-
                                                                                • 0: D0
                                                                                • 1: D1
                                                                                +- +-

                                                                                +-Definition at line 1566 of file dwc_otg_regs.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                unsigned depctl_data::setd0pid
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Set DATA0 PID (INTR/Bulk IN and OUT endpoints) Writing to this field sets the Endpoint DPID (DPID) field in this register to DATA0. +-

                                                                                +-Set Even (micro)frame (SetEvenFr) (ISO IN and OUT Endpoints) Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to even (micro) frame. +-

                                                                                +-Definition at line 1603 of file dwc_otg_regs.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                unsigned depctl_data::setd1pid
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Set DATA1 PID (INTR/Bulk IN and OUT endpoints) Writing to this field sets the Endpoint DPID (DPID) field in this register to DATA1 Set Odd (micro)frame (SetOddFr) (ISO IN and OUT Endpoints) Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to odd (micro) frame. +-

                                                                                +- +-

                                                                                +-Definition at line 1611 of file dwc_otg_regs.h.

                                                                                +-

                                                                                The documentation for this union was generated from the following file: +-
                                                                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/uniondeptsiz0__data.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/uniondeptsiz0__data.html 2013-07-26 19:34:43.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,57 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: deptsiz0_data Union Reference +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                deptsiz0_data Union Reference

                                                                                This union represents the bit fields in the Device EP 0 Transfer Size Register. +-More... +-

                                                                                +-#include <dwc_otg_regs.h> +-

                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-

                                                                                Data Fields

                                                                                +-uint32_t d32
                                                                                 raw register data
                                                                                +-struct {
                                                                                   unsigned   xfersize:7
                                                                                 Transfer size.
                                                                                   unsigned   reserved7_18:12
                                                                                 Reserved.
                                                                                   unsigned   pktcnt:2
                                                                                 Packet Count.
                                                                                   unsigned   reserved21_28:8
                                                                                 Reserved.
                                                                                   unsigned   supcnt:2
                                                                                 Setup Packet Count (DOEPTSIZ0 Only).
                                                                                   unsigned   reserved31
                                                                                } b
                                                                                 register bits
                                                                                +-

                                                                                Detailed Description

                                                                                +-This union represents the bit fields in the Device EP 0 Transfer Size Register. +-

                                                                                +-Read the register into the d32 member then set/clear the bits using the bit elements. +-

                                                                                +- +-

                                                                                +-Definition at line 1647 of file dwc_otg_regs.h.

                                                                                The documentation for this union was generated from the following file: +-
                                                                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/uniondeptsiz__data.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/uniondeptsiz__data.html 2013-07-26 19:34:43.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,51 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: deptsiz_data Union Reference +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                deptsiz_data Union Reference

                                                                                This union represents the bit fields in the Device EP Transfer Size Register. +-More... +-

                                                                                +-#include <dwc_otg_regs.h> +-

                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-

                                                                                Data Fields

                                                                                +-uint32_t d32
                                                                                 raw register data
                                                                                +-struct {
                                                                                   unsigned   xfersize:19
                                                                                 Transfer size.
                                                                                   unsigned   pktcnt:10
                                                                                 Packet Count.
                                                                                   unsigned   mc:2
                                                                                 Multi Count - Periodic IN endpoints.
                                                                                   unsigned   reserved:1
                                                                                } b
                                                                                 register bits
                                                                                +-

                                                                                Detailed Description

                                                                                +-This union represents the bit fields in the Device EP Transfer Size Register. +-

                                                                                +-Read the register into the d32 member then set/clear the bits using the bit elements. +-

                                                                                +- +-

                                                                                +-Definition at line 1625 of file dwc_otg_regs.h.

                                                                                The documentation for this union was generated from the following file: +-
                                                                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/uniondev__dma__desc__sts.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/uniondev__dma__desc__sts.html 2013-07-26 19:34:43.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,131 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dev_dma_desc_sts Union Reference +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                dev_dma_desc_sts Union Reference

                                                                                This union represents the bit fields in the DMA Descriptor status quadlet. +-More... +-

                                                                                +-#include <dwc_otg_regs.h> +-

                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-

                                                                                Data Fields

                                                                                +-uint32_t d32
                                                                                 raw register data
                                                                                +-struct {
                                                                                   unsigned   bytes:16
                                                                                 Received number of bytes.
                                                                                   unsigned   nak:1
                                                                                 NAK bit - only for OUT EPs.
                                                                                   unsigned   reserved17_22:6
                                                                                   unsigned   mtrf:1
                                                                                 Multiple Transfer - only for OUT EPs.
                                                                                   unsigned   sr:1
                                                                                 Setup Packet received - only for OUT EPs.
                                                                                   unsigned   ioc:1
                                                                                 Interrupt On Complete.
                                                                                   unsigned   sp:1
                                                                                 Short Packet.
                                                                                   unsigned   l:1
                                                                                 Last.
                                                                                   unsigned   sts:2
                                                                                 Receive Status.
                                                                                   unsigned   bs:2
                                                                                 Buffer Status.
                                                                                } b
                                                                                 quadlet bits
                                                                                +-struct {
                                                                                   unsigned   rxbytes:11
                                                                                 Received number of bytes.
                                                                                   unsigned   reserved11:1
                                                                                   unsigned   framenum:11
                                                                                 Frame Number.
                                                                                   unsigned   pid:2
                                                                                 Received ISO Data PID.
                                                                                   unsigned   ioc:1
                                                                                 Interrupt On Complete.
                                                                                   unsigned   sp:1
                                                                                 Short Packet.
                                                                                   unsigned   l:1
                                                                                 Last.
                                                                                   unsigned   rxsts:2
                                                                                 Receive Status.
                                                                                   unsigned   bs:2
                                                                                 Buffer Status.
                                                                                } b_iso_out
                                                                                 iso out quadlet bits
                                                                                +-struct {
                                                                                   unsigned   txbytes:12
                                                                                 Transmited number of bytes.
                                                                                   unsigned   framenum:11
                                                                                 Frame Number.
                                                                                   unsigned   pid:2
                                                                                 Transmited ISO Data PID.
                                                                                   unsigned   ioc:1
                                                                                 Interrupt On Complete.
                                                                                   unsigned   sp:1
                                                                                 Short Packet.
                                                                                   unsigned   l:1
                                                                                 Last.
                                                                                   unsigned   txsts:2
                                                                                 Transmit Status.
                                                                                   unsigned   bs:2
                                                                                 Buffer Status.
                                                                                } b_iso_in
                                                                                 iso in quadlet bits
                                                                                +-

                                                                                Detailed Description

                                                                                +-This union represents the bit fields in the DMA Descriptor status quadlet. +-

                                                                                +-Read the quadlet into the d32 member then set/clear the bits using the bit, b_iso_out and b_iso_in elements. +-

                                                                                +- +-

                                                                                +-Definition at line 1690 of file dwc_otg_regs.h.

                                                                                The documentation for this union was generated from the following file: +-
                                                                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/uniondevice__grxsts__data.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/uniondevice__grxsts__data.html 2013-07-26 19:34:43.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,50 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: device_grxsts_data Union Reference +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                device_grxsts_data Union Reference

                                                                                This union represents the bit fields in the Device Receive Status Read and Pop Registers (GRXSTSR, GRXSTSP) Read the register into the d32 element then read out the bits using the bit elements. +-More... +-

                                                                                +-#include <dwc_otg_regs.h> +-

                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-

                                                                                Data Fields

                                                                                +-uint32_t d32
                                                                                 raw register data
                                                                                +-struct {
                                                                                   unsigned   epnum:4
                                                                                   unsigned   bcnt:11
                                                                                   unsigned   dpid:2
                                                                                   unsigned   pktsts:4
                                                                                   unsigned   fn:4
                                                                                   unsigned   reserved25_31:7
                                                                                } b
                                                                                 register bits
                                                                                +-

                                                                                Detailed Description

                                                                                +-This union represents the bit fields in the Device Receive Status Read and Pop Registers (GRXSTSR, GRXSTSP) Read the register into the d32 element then read out the bits using the bit elements. +-

                                                                                +- +-

                                                                                +-Definition at line 522 of file dwc_otg_regs.h.

                                                                                The documentation for this union was generated from the following file: +-
                                                                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/uniondiepint__data.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/uniondiepint__data.html 2013-07-26 19:34:43.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,78 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: diepint_data Union Reference +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                diepint_data Union Reference

                                                                                This union represents the bit fields in the Device IN EP Interrupt Register and the Device IN EP Common Mask Register. +-More... +-

                                                                                +-#include <dwc_otg_regs.h> +-

                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-

                                                                                Data Fields

                                                                                +-uint32_t d32
                                                                                 raw register data
                                                                                +-struct {
                                                                                   unsigned   xfercompl:1
                                                                                 Transfer complete mask.
                                                                                   unsigned   epdisabled:1
                                                                                 Endpoint disable mask.
                                                                                   unsigned   ahberr:1
                                                                                 AHB Error mask.
                                                                                   unsigned   timeout:1
                                                                                 TimeOUT Handshake mask (non-ISOC EPs).
                                                                                   unsigned   intktxfemp:1
                                                                                 IN Token received with TxF Empty mask.
                                                                                   unsigned   intknepmis:1
                                                                                 IN Token Received with EP mismatch mask.
                                                                                   unsigned   inepnakeff:1
                                                                                 IN Endpoint NAK Effective mask.
                                                                                   unsigned   emptyintr:1
                                                                                 Reserved.
                                                                                   unsigned   txfifoundrn:1
                                                                                   unsigned   bna:1
                                                                                 BNA Interrupt mask.
                                                                                   unsigned   reserved10_12:3
                                                                                   unsigned   nak:1
                                                                                 BNA Interrupt mask.
                                                                                   unsigned   reserved14_31:18
                                                                                } b
                                                                                 register bits
                                                                                +-

                                                                                Detailed Description

                                                                                +-This union represents the bit fields in the Device IN EP Interrupt Register and the Device IN EP Common Mask Register. +-

                                                                                +-

                                                                                  +-
                                                                                • Read the register into the d32 member then set/clear the bits using the bit elements.
                                                                                +- +-

                                                                                +- +-

                                                                                +-Definition at line 1250 of file dwc_otg_regs.h.

                                                                                The documentation for this union was generated from the following file: +-
                                                                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/uniondoepint__data.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/uniondoepint__data.html 2013-07-26 19:34:43.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,86 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: doepint_data Union Reference +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                doepint_data Union Reference

                                                                                This union represents the bit fields in the Device OUT EP Interrupt Registerand Device OUT EP Common Interrupt Mask Register. +-More... +-

                                                                                +-#include <dwc_otg_regs.h> +-

                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-

                                                                                Data Fields

                                                                                +-uint32_t d32
                                                                                 raw register data
                                                                                +-struct {
                                                                                   unsigned   xfercompl:1
                                                                                 Transfer complete.
                                                                                   unsigned   epdisabled:1
                                                                                 Endpoint disable.
                                                                                   unsigned   ahberr:1
                                                                                 AHB Error.
                                                                                   unsigned   setup:1
                                                                                 Setup Phase Done (contorl EPs).
                                                                                   unsigned   outtknepdis:1
                                                                                 OUT Token Received when Endpoint Disabled.
                                                                                   unsigned   stsphsercvd:1
                                                                                   unsigned   back2backsetup:1
                                                                                 Back-to-Back SETUP Packets Received.
                                                                                   unsigned   reserved7:1
                                                                                   unsigned   outpkterr:1
                                                                                 OUT packet Error.
                                                                                   unsigned   bna:1
                                                                                 BNA Interrupt.
                                                                                   unsigned   reserved10:1
                                                                                   unsigned   pktdrpsts:1
                                                                                 Packet Drop Status.
                                                                                   unsigned   babble:1
                                                                                 Babble Interrupt.
                                                                                   unsigned   nak:1
                                                                                 NAK Interrupt.
                                                                                   unsigned   nyet:1
                                                                                 NYET Interrupt.
                                                                                   unsigned   reserved15_31:17
                                                                                } b
                                                                                 register bits
                                                                                +-

                                                                                Detailed Description

                                                                                +-This union represents the bit fields in the Device OUT EP Interrupt Registerand Device OUT EP Common Interrupt Mask Register. +-

                                                                                +-

                                                                                  +-
                                                                                • Read the register into the d32 member then set/clear the bits using the bit elements.
                                                                                +- +-

                                                                                +- +-

                                                                                +-Definition at line 1298 of file dwc_otg_regs.h.

                                                                                The documentation for this union was generated from the following file: +-
                                                                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/uniondsts__data.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/uniondsts__data.html 2013-07-26 19:34:43.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,56 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dsts_data Union Reference +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                dsts_data Union Reference

                                                                                This union represents the bit fields in the Device Status Register. +-More... +-

                                                                                +-#include <dwc_otg_regs.h> +-

                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-

                                                                                Data Fields

                                                                                +-uint32_t d32
                                                                                 raw register data
                                                                                +-struct {
                                                                                   unsigned   suspsts:1
                                                                                 Suspend Status.
                                                                                   unsigned   enumspd:2
                                                                                 Enumerated Speed.
                                                                                   unsigned   errticerr:1
                                                                                 Erratic Error.
                                                                                   unsigned   reserved4_7:4
                                                                                   unsigned   soffn:14
                                                                                 Frame or Microframe Number of the received SOF.
                                                                                   unsigned   reserved22_31:10
                                                                                } b
                                                                                 register bits
                                                                                +-

                                                                                Detailed Description

                                                                                +-This union represents the bit fields in the Device Status Register. +-

                                                                                +-Read the register into the d32 member then set/clear the bits using the bit elements. +-

                                                                                +- +-

                                                                                +-Definition at line 1221 of file dwc_otg_regs.h.

                                                                                The documentation for this union was generated from the following file: +-
                                                                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/uniondthrctl__data.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/uniondthrctl__data.html 2013-07-26 19:34:43.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,207 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dthrctl_data Union Reference +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                dthrctl_data Union Reference

                                                                                This union represents Threshold control Register Read and write the register into the d32 member. +-More... +-

                                                                                +-#include <dwc_otg_regs.h> +-

                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-

                                                                                Data Fields

                                                                                +-uint32_t d32
                                                                                 raw register data
                                                                                +-struct {
                                                                                   unsigned   non_iso_thr_en:1
                                                                                 non ISO Tx Thr.
                                                                                   unsigned   iso_thr_en:1
                                                                                 ISO Tx Thr.
                                                                                   unsigned   tx_thr_len:9
                                                                                 Tx Thr.
                                                                                   unsigned   ahb_thr_ratio:2
                                                                                 AHB Threshold ratio.
                                                                                   unsigned   reserved13_15:3
                                                                                 Reserved.
                                                                                   unsigned   rx_thr_en:1
                                                                                 Rx Thr.
                                                                                   unsigned   rx_thr_len:9
                                                                                 Rx Thr.
                                                                                   unsigned   reserved26:1
                                                                                   unsigned   arbprken:1
                                                                                 Arbiter Parking Enable.
                                                                                   unsigned   reserved28_31:4
                                                                                 Reserved.
                                                                                } b
                                                                                 register bits
                                                                                +-

                                                                                Detailed Description

                                                                                +-This union represents Threshold control Register Read and write the register into the d32 member. +-

                                                                                +-

                                                                                  +-
                                                                                • * - READ-WRITABLE Register
                                                                                +- +-

                                                                                +- +-

                                                                                +-Definition at line 1425 of file dwc_otg_regs.h.

                                                                                Field Documentation

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                unsigned dthrctl_data::non_iso_thr_en
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-non ISO Tx Thr. +-

                                                                                +-Enable +-

                                                                                +-Definition at line 1431 of file dwc_otg_regs.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                unsigned dthrctl_data::iso_thr_en
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-ISO Tx Thr. +-

                                                                                +-Enable +-

                                                                                +-Definition at line 1433 of file dwc_otg_regs.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                unsigned dthrctl_data::tx_thr_len
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Tx Thr. +-

                                                                                +-Length +-

                                                                                +-Definition at line 1435 of file dwc_otg_regs.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                unsigned dthrctl_data::rx_thr_en
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Rx Thr. +-

                                                                                +-Enable +-

                                                                                +-Definition at line 1441 of file dwc_otg_regs.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                unsigned dthrctl_data::rx_thr_len
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Rx Thr. +-

                                                                                +-Length +-

                                                                                +-Definition at line 1443 of file dwc_otg_regs.h.

                                                                                +-

                                                                                The documentation for this union was generated from the following file: +-
                                                                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/uniondtknq1__data.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/uniondtknq1__data.html 2013-07-26 19:34:43.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,82 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dtknq1_data Union Reference +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                dtknq1_data Union Reference

                                                                                This union represents the bit fields in the Device IN Token Queue Read Registers. +-More... +-

                                                                                +-#include <dwc_otg_regs.h> +-

                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-

                                                                                Data Fields

                                                                                +-uint32_t d32
                                                                                 raw register data
                                                                                +-struct {
                                                                                   unsigned   intknwptr:5
                                                                                 In Token Queue Write Pointer.
                                                                                   unsigned   reserved05_06:2
                                                                                 Reserved.
                                                                                   unsigned   wrap_bit:1
                                                                                 write pointer has wrapped.
                                                                                   unsigned   epnums0_5:24
                                                                                 EP Numbers of IN Tokens 0 ...
                                                                                } b
                                                                                 register bits
                                                                                +-

                                                                                Detailed Description

                                                                                +-This union represents the bit fields in the Device IN Token Queue Read Registers. +-

                                                                                +-

                                                                                  +-
                                                                                • Read the register into the d32 member.
                                                                                • READ-ONLY Register
                                                                                +- +-

                                                                                +- +-

                                                                                +-Definition at line 1404 of file dwc_otg_regs.h.

                                                                                Field Documentation

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                unsigned dtknq1_data::epnums0_5
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-EP Numbers of IN Tokens 0 ... +-

                                                                                +-4 +-

                                                                                +-Definition at line 1416 of file dwc_otg_regs.h.

                                                                                +-

                                                                                The documentation for this union was generated from the following file: +-
                                                                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/uniondtxfsts__data.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/uniondtxfsts__data.html 2013-07-26 19:34:43.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,44 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dtxfsts_data Union Reference +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                dtxfsts_data Union Reference

                                                                                This union represents the bit fields in the Transmit FIFO Status Register (DTXFSTS). +-More... +-

                                                                                +-#include <dwc_otg_regs.h> +-

                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-

                                                                                Data Fields

                                                                                +-uint32_t d32
                                                                                 raw register data
                                                                                +-struct {
                                                                                   unsigned   txfspcavail:16
                                                                                   unsigned   reserved:16
                                                                                } b
                                                                                 register bits
                                                                                +-

                                                                                Detailed Description

                                                                                +-This union represents the bit fields in the Transmit FIFO Status Register (DTXFSTS). +-

                                                                                +-Read the register into the d32 element then read out the bits using the bit elements. +-

                                                                                +- +-

                                                                                +-Definition at line 618 of file dwc_otg_regs.h.

                                                                                The documentation for this union was generated from the following file: +-
                                                                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/uniondwc__otg__hcd_1_1dwc__otg__hcd__internal__flags.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/uniondwc__otg__hcd_1_1dwc__otg__hcd__internal__flags.html 2013-07-26 19:34:43.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,52 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: dwc_otg_hcd::dwc_otg_hcd_internal_flags Union Reference +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                dwc_otg_hcd::dwc_otg_hcd_internal_flags Union Reference

                                                                                Internal DWC HCD Flags. +-More... +-

                                                                                +-#include <dwc_otg_hcd.h> +-

                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-

                                                                                Data Fields

                                                                                +-uint32_t d32
                                                                                +-struct {
                                                                                   unsigned   port_connect_status_change:1
                                                                                   unsigned   port_connect_status:1
                                                                                   unsigned   port_reset_change:1
                                                                                   unsigned   port_enable_change:1
                                                                                   unsigned   port_suspend_change:1
                                                                                   unsigned   port_over_current_change:1
                                                                                   unsigned   port_l1_change:1
                                                                                   unsigned   reserved:26
                                                                                } b
                                                                                +-

                                                                                Detailed Description

                                                                                +-Internal DWC HCD Flags. +-

                                                                                +- +-

                                                                                +-Definition at line 383 of file dwc_otg_hcd.h.

                                                                                The documentation for this union was generated from the following file: +-
                                                                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/unionfifosize__data.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/unionfifosize__data.html 2013-07-26 19:34:43.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,44 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: fifosize_data Union Reference +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                fifosize_data Union Reference

                                                                                This union represents the bit fields in the FIFO Size Registers (HPTXFSIZ, GNPTXFSIZ, DPTXFSIZn, DIEPTXFn). +-More... +-

                                                                                +-#include <dwc_otg_regs.h> +-

                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-

                                                                                Data Fields

                                                                                +-uint32_t d32
                                                                                 raw register data
                                                                                +-struct {
                                                                                   unsigned   startaddr:16
                                                                                   unsigned   depth:16
                                                                                } b
                                                                                 register bits
                                                                                +-

                                                                                Detailed Description

                                                                                +-This union represents the bit fields in the FIFO Size Registers (HPTXFSIZ, GNPTXFSIZ, DPTXFSIZn, DIEPTXFn). +-

                                                                                +-Read the register into the d32 element then read out the bits using the bit elements. +-

                                                                                +- +-

                                                                                +-Definition at line 572 of file dwc_otg_regs.h.

                                                                                The documentation for this union was generated from the following file: +-
                                                                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/uniongahbcfg__data.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/uniongahbcfg__data.html 2013-07-26 19:34:43.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,62 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: gahbcfg_data Union Reference +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                gahbcfg_data Union Reference

                                                                                This union represents the bit fields of the Core AHB Configuration Register (GAHBCFG). +-More... +-

                                                                                +-#include <dwc_otg_regs.h> +-

                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-

                                                                                Data Fields

                                                                                +-uint32_t d32
                                                                                 raw register data
                                                                                +-struct {
                                                                                   unsigned   glblintrmsk:1
                                                                                   unsigned   hburstlen:4
                                                                                   unsigned   dmaenable:1
                                                                                   unsigned   reserved:1
                                                                                   unsigned   nptxfemplvl_txfemplvl:1
                                                                                   unsigned   ptxfemplvl:1
                                                                                   unsigned   reserved9_20:12
                                                                                   unsigned   remmemsupp:1
                                                                                   unsigned   notialldmawrit:1
                                                                                   unsigned   ahbsingle:1
                                                                                   unsigned   reserved24_31:8
                                                                                } b
                                                                                 register bits
                                                                                +-

                                                                                Detailed Description

                                                                                +-This union represents the bit fields of the Core AHB Configuration Register (GAHBCFG). +-

                                                                                +-Set/clear the bits using the bit fields then write the d32 value to the register. +-

                                                                                +- +-

                                                                                +-Definition at line 232 of file dwc_otg_regs.h.

                                                                                The documentation for this union was generated from the following file: +-
                                                                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/uniongdfifocfg__data.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/uniongdfifocfg__data.html 2013-07-26 19:34:43.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,45 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: gdfifocfg_data Union Reference +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                gdfifocfg_data Union Reference

                                                                                This union represents the bit fields in the Global Data FIFO Software Configuration Register. +-More... +-

                                                                                +-#include <dwc_otg_regs.h> +-

                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-

                                                                                Data Fields

                                                                                +-uint32_t d32
                                                                                +-struct {
                                                                                   unsigned   gdfifocfg:16
                                                                                 OTG Data FIFO depth.
                                                                                   unsigned   epinfobase:16
                                                                                 Start address of EP info controller.
                                                                                } b
                                                                                 register bits
                                                                                +-

                                                                                Detailed Description

                                                                                +-This union represents the bit fields in the Global Data FIFO Software Configuration Register. +-

                                                                                +-Read the register into the d32 member then set/clear the bits using the bit elements. +-

                                                                                +- +-

                                                                                +-Definition at line 2469 of file dwc_otg_regs.h.

                                                                                The documentation for this union was generated from the following file: +-
                                                                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/unionggpio__data.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/unionggpio__data.html 2013-07-26 19:34:43.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,44 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: ggpio_data Union Reference +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                ggpio_data Union Reference

                                                                                This union represents the bit fields in the General Purpose Input/Output Register (GGPIO). +-More... +-

                                                                                +-#include <dwc_otg_regs.h> +-

                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-

                                                                                Data Fields

                                                                                +-uint32_t d32
                                                                                 raw register data
                                                                                +-struct {
                                                                                   unsigned   gpi:16
                                                                                   unsigned   gpo:16
                                                                                } b
                                                                                 register bits
                                                                                +-

                                                                                Detailed Description

                                                                                +-This union represents the bit fields in the General Purpose Input/Output Register (GGPIO). +-

                                                                                +-Read the register into the d32 element then read out the bits using the bit elements. +-

                                                                                +- +-

                                                                                +-Definition at line 681 of file dwc_otg_regs.h.

                                                                                The documentation for this union was generated from the following file: +-
                                                                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/uniongi2cctl__data.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/uniongi2cctl__data.html 2013-07-26 19:34:43.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,62 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: gi2cctl_data Union Reference +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                gi2cctl_data Union Reference

                                                                                This union represents the bit fields in the I2C Control Register (I2CCTL). +-More... +-

                                                                                +-#include <dwc_otg_regs.h> +-

                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-

                                                                                Data Fields

                                                                                +-uint32_t d32
                                                                                 raw register data
                                                                                +-struct {
                                                                                   unsigned   rwdata:8
                                                                                   unsigned   regaddr:8
                                                                                   unsigned   addr:7
                                                                                   unsigned   i2cen:1
                                                                                   unsigned   ack:1
                                                                                   unsigned   i2csuspctl:1
                                                                                   unsigned   i2cdevaddr:2
                                                                                   unsigned   i2cdatse0:1
                                                                                   unsigned   reserved:1
                                                                                   unsigned   rw:1
                                                                                   unsigned   bsydne:1
                                                                                } b
                                                                                 register bits
                                                                                +-

                                                                                Detailed Description

                                                                                +-This union represents the bit fields in the I2C Control Register (I2CCTL). +-

                                                                                +-Read the register into the d32 element then read out the bits using the bit elements. +-

                                                                                +- +-

                                                                                +-Definition at line 633 of file dwc_otg_regs.h.

                                                                                The documentation for this union was generated from the following file: +-
                                                                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/uniongintmsk__data.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/uniongintmsk__data.html 2013-07-26 19:34:43.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,104 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: gintmsk_data Union Reference +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                gintmsk_data Union Reference

                                                                                This union represents the bit fields of the Core Interrupt Mask Register (GINTMSK). +-More... +-

                                                                                +-#include <dwc_otg_regs.h> +-

                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-

                                                                                Data Fields

                                                                                +-uint32_t d32
                                                                                 raw register data
                                                                                +-struct {
                                                                                   unsigned   reserved0:1
                                                                                   unsigned   modemismatch:1
                                                                                   unsigned   otgintr:1
                                                                                   unsigned   sofintr:1
                                                                                   unsigned   rxstsqlvl:1
                                                                                   unsigned   nptxfempty:1
                                                                                   unsigned   ginnakeff:1
                                                                                   unsigned   goutnakeff:1
                                                                                   unsigned   ulpickint:1
                                                                                   unsigned   i2cintr:1
                                                                                   unsigned   erlysuspend:1
                                                                                   unsigned   usbsuspend:1
                                                                                   unsigned   usbreset:1
                                                                                   unsigned   enumdone:1
                                                                                   unsigned   isooutdrop:1
                                                                                   unsigned   eopframe:1
                                                                                   unsigned   restoredone:1
                                                                                   unsigned   epmismatch:1
                                                                                   unsigned   inepintr:1
                                                                                   unsigned   outepintr:1
                                                                                   unsigned   incomplisoin:1
                                                                                   unsigned   incomplisoout:1
                                                                                   unsigned   fetsusp:1
                                                                                   unsigned   resetdet:1
                                                                                   unsigned   portintr:1
                                                                                   unsigned   hcintr:1
                                                                                   unsigned   ptxfempty:1
                                                                                   unsigned   lpmtranrcvd:1
                                                                                   unsigned   conidstschng:1
                                                                                   unsigned   disconnect:1
                                                                                   unsigned   sessreqintr:1
                                                                                   unsigned   wkupintr:1
                                                                                } b
                                                                                 register bits
                                                                                +-

                                                                                Detailed Description

                                                                                +-This union represents the bit fields of the Core Interrupt Mask Register (GINTMSK). +-

                                                                                +-Set/clear the bits using the bit fields then write the d32 value to the register. +-

                                                                                +- +-

                                                                                +-Definition at line 431 of file dwc_otg_regs.h.

                                                                                The documentation for this union was generated from the following file: +-
                                                                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/uniongintsts__data.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/uniongintsts__data.html 2013-07-26 19:34:43.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,104 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: gintsts_data Union Reference +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                gintsts_data Union Reference

                                                                                This union represents the bit fields of the Core Interrupt Register (GINTSTS). +-More... +-

                                                                                +-#include <dwc_otg_regs.h> +-

                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-

                                                                                Data Fields

                                                                                +-uint32_t d32
                                                                                 raw register data
                                                                                +-struct {
                                                                                   unsigned   curmode:1
                                                                                   unsigned   modemismatch:1
                                                                                   unsigned   otgintr:1
                                                                                   unsigned   sofintr:1
                                                                                   unsigned   rxstsqlvl:1
                                                                                   unsigned   nptxfempty:1
                                                                                   unsigned   ginnakeff:1
                                                                                   unsigned   goutnakeff:1
                                                                                   unsigned   ulpickint:1
                                                                                   unsigned   i2cintr:1
                                                                                   unsigned   erlysuspend:1
                                                                                   unsigned   usbsuspend:1
                                                                                   unsigned   usbreset:1
                                                                                   unsigned   enumdone:1
                                                                                   unsigned   isooutdrop:1
                                                                                   unsigned   eopframe:1
                                                                                   unsigned   restoredone:1
                                                                                   unsigned   epmismatch:1
                                                                                   unsigned   inepint:1
                                                                                   unsigned   outepintr:1
                                                                                   unsigned   incomplisoin:1
                                                                                   unsigned   incomplisoout:1
                                                                                   unsigned   fetsusp:1
                                                                                   unsigned   resetdet:1
                                                                                   unsigned   portintr:1
                                                                                   unsigned   hcintr:1
                                                                                   unsigned   ptxfempty:1
                                                                                   unsigned   lpmtranrcvd:1
                                                                                   unsigned   conidstschng:1
                                                                                   unsigned   disconnect:1
                                                                                   unsigned   sessreqintr:1
                                                                                   unsigned   wkupintr:1
                                                                                } b
                                                                                 register bits
                                                                                +-

                                                                                Detailed Description

                                                                                +-This union represents the bit fields of the Core Interrupt Register (GINTSTS). +-

                                                                                +-Set/clear the bits using the bit fields then write the d32 value to the register. +-

                                                                                +- +-

                                                                                +-Definition at line 475 of file dwc_otg_regs.h.

                                                                                The documentation for this union was generated from the following file: +-
                                                                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/unionglpmctl__data.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/unionglpmctl__data.html 2013-07-26 19:34:43.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,441 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: glpmctl_data Union Reference +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                glpmctl_data Union Reference

                                                                                This union represents the bit fields of the Core LPM Configuration Register (GLPMCFG). +-More... +-

                                                                                +-#include <dwc_otg_regs.h> +-

                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-

                                                                                Data Fields

                                                                                +-uint32_t d32
                                                                                 raw register data
                                                                                +-struct {
                                                                                   unsigned   lpm_cap_en:1
                                                                                 LPM-Capable (LPMCap) (Device and Host) The application uses this bit to control the DWC_otg core LPM capabilities.
                                                                                   unsigned   appl_resp:1
                                                                                 LPM response programmed by application (AppL1Res) (Device) Handshake response to LPM token pre-programmed by device application software.
                                                                                   unsigned   hird:4
                                                                                 Host Initiated Resume Duration (HIRD) (Device and Host) In Host mode this field indicates the value of HIRD to be sent in an LPM transaction.
                                                                                   unsigned   rem_wkup_en:1
                                                                                 RemoteWakeEnable (bRemoteWake) (Device and Host) In Host mode this bit indicates the value of remote wake up to be sent in wIndex field of LPM transaction.
                                                                                   unsigned   en_utmi_sleep:1
                                                                                 Enable utmi_sleep_n (EnblSlpM) (Device and Host) The application uses this bit to control the utmi_sleep_n assertion to the PHY when in L1 state.
                                                                                   unsigned   hird_thres:5
                                                                                 HIRD Threshold (HIRD_Thres) (Device and Host).
                                                                                   unsigned   lpm_resp:2
                                                                                 LPM Response (CoreL1Res) (Device and Host) In Host mode this bit contains handsake response to LPM transaction.
                                                                                   unsigned   prt_sleep_sts:1
                                                                                 Port Sleep Status (SlpSts) (Device and Host) This bit is set as long as a Sleep condition is present on the USB bus.
                                                                                   unsigned   sleep_state_resumeok:1
                                                                                 Sleep State Resume OK (L1ResumeOK) (Device and Host) Indicates that the application or host can start resume from Sleep state.
                                                                                   unsigned   lpm_chan_index:4
                                                                                 LPM channel Index (LPM_Chnl_Indx) (Host) The channel number on which the LPM transaction has to be applied while sending an LPM transaction to the local device.
                                                                                   unsigned   retry_count:3
                                                                                 LPM Retry Count (LPM_Retry_Cnt) (Host) Number host retries that would be performed if the device response was not valid response.
                                                                                   unsigned   send_lpm:1
                                                                                 Send LPM Transaction (SndLPM) (Host) When set by application software, an LPM transaction containing two tokens is sent.
                                                                                   unsigned   retry_count_sts:3
                                                                                 LPM Retry status (LPM_RetryCnt_Sts) (Host) Number of LPM Host Retries still remaining to be transmitted for the current LPM sequence.
                                                                                   unsigned   reserved28_29:2
                                                                                   unsigned   hsic_connect:1
                                                                                 In host mode once this bit is set, the host configures to drive the HSIC Idle state on the bus.
                                                                                   unsigned   inv_sel_hsic:1
                                                                                 This bit overrides and functionally inverts the if_select_hsic input port signal.
                                                                                } b
                                                                                 register bits
                                                                                +-

                                                                                Detailed Description

                                                                                +-This union represents the bit fields of the Core LPM Configuration Register (GLPMCFG). +-

                                                                                +-Set the bits using bit fields then write the d32 value to the register. +-

                                                                                +- +-

                                                                                +-Definition at line 850 of file dwc_otg_regs.h.

                                                                                Field Documentation

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                unsigned glpmctl_data::lpm_cap_en
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-LPM-Capable (LPMCap) (Device and Host) The application uses this bit to control the DWC_otg core LPM capabilities. +-

                                                                                +- +-

                                                                                +-Definition at line 859 of file dwc_otg_regs.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                unsigned glpmctl_data::appl_resp
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-LPM response programmed by application (AppL1Res) (Device) Handshake response to LPM token pre-programmed by device application software. +-

                                                                                +- +-

                                                                                +-Definition at line 864 of file dwc_otg_regs.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                unsigned glpmctl_data::hird
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Host Initiated Resume Duration (HIRD) (Device and Host) In Host mode this field indicates the value of HIRD to be sent in an LPM transaction. +-

                                                                                +-In Device mode this field is updated with the Received LPM Token HIRD bmAttribute when an ACK/NYET/STALL response is sent to an LPM transaction. +-

                                                                                +-Definition at line 873 of file dwc_otg_regs.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                unsigned glpmctl_data::rem_wkup_en
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-RemoteWakeEnable (bRemoteWake) (Device and Host) In Host mode this bit indicates the value of remote wake up to be sent in wIndex field of LPM transaction. +-

                                                                                +-In Device mode this field is updated with the Received LPM Token bRemoteWake bmAttribute when an ACK/NYET/STALL response is sent to an LPM transaction. +-

                                                                                +-Definition at line 882 of file dwc_otg_regs.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                unsigned glpmctl_data::en_utmi_sleep
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Enable utmi_sleep_n (EnblSlpM) (Device and Host) The application uses this bit to control the utmi_sleep_n assertion to the PHY when in L1 state. +-

                                                                                +- +-

                                                                                +-Definition at line 887 of file dwc_otg_regs.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                unsigned glpmctl_data::lpm_resp
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-LPM Response (CoreL1Res) (Device and Host) In Host mode this bit contains handsake response to LPM transaction. +-

                                                                                +-In Device mode the response of the core to LPM transaction received is reflected in these two bits.

                                                                                  +-
                                                                                • 0x0 : ERROR (No handshake response)
                                                                                • 0x1 : STALL
                                                                                • 0x2 : NYET
                                                                                • 0x3 : ACK
                                                                                +- +-

                                                                                +-Definition at line 901 of file dwc_otg_regs.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                unsigned glpmctl_data::prt_sleep_sts
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Port Sleep Status (SlpSts) (Device and Host) This bit is set as long as a Sleep condition is present on the USB bus. +-

                                                                                +- +-

                                                                                +-Definition at line 906 of file dwc_otg_regs.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                unsigned glpmctl_data::sleep_state_resumeok
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Sleep State Resume OK (L1ResumeOK) (Device and Host) Indicates that the application or host can start resume from Sleep state. +-

                                                                                +- +-

                                                                                +-Definition at line 911 of file dwc_otg_regs.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                unsigned glpmctl_data::lpm_chan_index
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-LPM channel Index (LPM_Chnl_Indx) (Host) The channel number on which the LPM transaction has to be applied while sending an LPM transaction to the local device. +-

                                                                                +- +-

                                                                                +-Definition at line 917 of file dwc_otg_regs.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                unsigned glpmctl_data::retry_count
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-LPM Retry Count (LPM_Retry_Cnt) (Host) Number host retries that would be performed if the device response was not valid response. +-

                                                                                +- +-

                                                                                +-Definition at line 922 of file dwc_otg_regs.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                unsigned glpmctl_data::send_lpm
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Send LPM Transaction (SndLPM) (Host) When set by application software, an LPM transaction containing two tokens is sent. +-

                                                                                +- +-

                                                                                +-Definition at line 928 of file dwc_otg_regs.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                unsigned glpmctl_data::hsic_connect
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-In host mode once this bit is set, the host configures to drive the HSIC Idle state on the bus. +-

                                                                                +-It then waits for the device to initiate the Connect sequence. In device mode once this bit is set, the device waits for the HSIC Idle line state on the bus. Upon receving the Idle line state, it initiates the HSIC Connect sequence. +-

                                                                                +-Definition at line 942 of file dwc_otg_regs.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                unsigned glpmctl_data::inv_sel_hsic
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-This bit overrides and functionally inverts the if_select_hsic input port signal. +-

                                                                                +- +-

                                                                                +-Definition at line 946 of file dwc_otg_regs.h.

                                                                                +-

                                                                                The documentation for this union was generated from the following file: +-
                                                                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/uniongnptxsts__data.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/uniongnptxsts__data.html 2013-07-26 19:34:43.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,83 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: gnptxsts_data Union Reference +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                gnptxsts_data Union Reference

                                                                                This union represents the bit fields in the Non-Periodic Transmit FIFO/Queue Status Register (GNPTXSTS). +-More... +-

                                                                                +-#include <dwc_otg_regs.h> +-

                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-

                                                                                Data Fields

                                                                                +-uint32_t d32
                                                                                 raw register data
                                                                                +-struct {
                                                                                   unsigned   nptxfspcavail:16
                                                                                   unsigned   nptxqspcavail:8
                                                                                   unsigned   nptxqtop_terminate:1
                                                                                 Top of the Non-Periodic Transmit Request Queue bit 24 - Terminate (Last entry for the selected channel/EP) bits 26:25 - Token Type 2'b00 - IN/OUT 2'b01 - Zero Length OUT 2'b10 - PING/Complete Split 2'b11 - Channel Halt bits 30:27 - Channel/EP Number.
                                                                                   unsigned   nptxqtop_token:2
                                                                                   unsigned   nptxqtop_chnep:4
                                                                                   unsigned   reserved:1
                                                                                } b
                                                                                 register bits
                                                                                +-

                                                                                Detailed Description

                                                                                +-This union represents the bit fields in the Non-Periodic Transmit FIFO/Queue Status Register (GNPTXSTS). +-

                                                                                +-Read the register into the d32 element then read out the bits using the bit elements. +-

                                                                                +- +-

                                                                                +-Definition at line 588 of file dwc_otg_regs.h.

                                                                                Field Documentation

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                unsigned gnptxsts_data::nptxqtop_terminate
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Top of the Non-Periodic Transmit Request Queue bit 24 - Terminate (Last entry for the selected channel/EP) bits 26:25 - Token Type 2'b00 - IN/OUT 2'b01 - Zero Length OUT 2'b10 - PING/Complete Split 2'b11 - Channel Halt bits 30:27 - Channel/EP Number. +-

                                                                                +-

                                                                                  +-
                                                                                • * - * - * - * - * - * -
                                                                                +- +-

                                                                                +-Definition at line 605 of file dwc_otg_regs.h.

                                                                                +-

                                                                                The documentation for this union was generated from the following file: +-
                                                                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/uniongotgctl__data.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/uniongotgctl__data.html 2013-07-26 19:34:43.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,84 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: gotgctl_data Union Reference +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                gotgctl_data Union Reference

                                                                                This union represents the bit fields of the Core OTG Control and Status Register (GOTGCTL). +-More... +-

                                                                                +-#include <dwc_otg_regs.h> +-

                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-

                                                                                Data Fields

                                                                                +-uint32_t d32
                                                                                 raw register data
                                                                                +-struct {
                                                                                   unsigned   sesreqscs:1
                                                                                   unsigned   sesreq:1
                                                                                   unsigned   vbvalidoven:1
                                                                                   unsigned   vbvalidovval:1
                                                                                   unsigned   avalidoven:1
                                                                                   unsigned   avalidovval:1
                                                                                   unsigned   bvalidoven:1
                                                                                   unsigned   bvalidovval:1
                                                                                   unsigned   hstnegscs:1
                                                                                   unsigned   hnpreq:1
                                                                                   unsigned   hstsethnpen:1
                                                                                   unsigned   devhnpen:1
                                                                                   unsigned   reserved12_15:4
                                                                                   unsigned   conidsts:1
                                                                                   unsigned   dbnctime:1
                                                                                   unsigned   asesvld:1
                                                                                   unsigned   bsesvld:1
                                                                                   unsigned   otgver:1
                                                                                   unsigned   reserved1:1
                                                                                   unsigned   multvalidbc:5
                                                                                   unsigned   chirpen:1
                                                                                   unsigned   reserved28_31:4
                                                                                } b
                                                                                 register bits
                                                                                +-

                                                                                Detailed Description

                                                                                +-This union represents the bit fields of the Core OTG Control and Status Register (GOTGCTL). +-

                                                                                +-Set the bits using the bit fields then write the d32 value to the register. +-

                                                                                +- +-

                                                                                +-Definition at line 158 of file dwc_otg_regs.h.

                                                                                The documentation for this union was generated from the following file: +-
                                                                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/uniongotgint__data.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/uniongotgint__data.html 2013-07-26 19:34:43.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,70 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: gotgint_data Union Reference +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                gotgint_data Union Reference

                                                                                This union represents the bit fields of the Core OTG Interrupt Register (GOTGINT). +-More... +-

                                                                                +-#include <dwc_otg_regs.h> +-

                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-

                                                                                Data Fields

                                                                                +-uint32_t d32
                                                                                 raw register data
                                                                                +-struct {
                                                                                   unsigned   reserved0_1:2
                                                                                 Current Mode.
                                                                                   unsigned   sesenddet:1
                                                                                 Session End Detected.
                                                                                   unsigned   reserved3_7:5
                                                                                   unsigned   sesreqsucstschng:1
                                                                                 Session Request Success Status Change.
                                                                                   unsigned   hstnegsucstschng:1
                                                                                 Host Negotiation Success Status Change.
                                                                                   unsigned   reserved10_16:7
                                                                                   unsigned   hstnegdet:1
                                                                                 Host Negotiation Detected.
                                                                                   unsigned   adevtoutchng:1
                                                                                 A-Device Timeout Change.
                                                                                   unsigned   debdone:1
                                                                                 Debounce Done.
                                                                                   unsigned   mvic:1
                                                                                 Multi-Valued input changed.
                                                                                   unsigned   reserved31_21:11
                                                                                } b
                                                                                 register bits
                                                                                +-

                                                                                Detailed Description

                                                                                +-This union represents the bit fields of the Core OTG Interrupt Register (GOTGINT). +-

                                                                                +-Set/clear the bits using the bit fields then write the d32 value to the register. +-

                                                                                +- +-

                                                                                +-Definition at line 193 of file dwc_otg_regs.h.

                                                                                The documentation for this union was generated from the following file: +-
                                                                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/uniongpvndctl__data.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/uniongpvndctl__data.html 2013-07-26 19:34:43.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,60 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: gpvndctl_data Union Reference +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                gpvndctl_data Union Reference

                                                                                This union represents the bit fields in the PHY Vendor Control Register (GPVNDCTL). +-More... +-

                                                                                +-#include <dwc_otg_regs.h> +-

                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-

                                                                                Data Fields

                                                                                +-uint32_t d32
                                                                                 raw register data
                                                                                +-struct {
                                                                                   unsigned   regdata:8
                                                                                   unsigned   vctrl:8
                                                                                   unsigned   regaddr16_21:6
                                                                                   unsigned   regwr:1
                                                                                   unsigned   reserved23_24:2
                                                                                   unsigned   newregreq:1
                                                                                   unsigned   vstsbsy:1
                                                                                   unsigned   vstsdone:1
                                                                                   unsigned   reserved28_30:3
                                                                                   unsigned   disulpidrvr:1
                                                                                } b
                                                                                 register bits
                                                                                +-

                                                                                Detailed Description

                                                                                +-This union represents the bit fields in the PHY Vendor Control Register (GPVNDCTL). +-

                                                                                +-Read the register into the d32 element then read out the bits using the bit elements. +-

                                                                                +- +-

                                                                                +-Definition at line 657 of file dwc_otg_regs.h.

                                                                                The documentation for this union was generated from the following file: +-
                                                                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/uniongpwrdn__data.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/uniongpwrdn__data.html 2013-07-26 19:34:43.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,114 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: gpwrdn_data Union Reference +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                gpwrdn_data Union Reference

                                                                                This union represents the bit fields in the Global Power Down Register Register. +-More... +-

                                                                                +-#include <dwc_otg_regs.h> +-

                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-

                                                                                Data Fields

                                                                                +-uint32_t d32
                                                                                +-struct {
                                                                                   unsigned   pmuintsel:1
                                                                                 PMU Interrupt Select.
                                                                                   unsigned   pmuactv:1
                                                                                 PMU Active.
                                                                                   unsigned   restore:1
                                                                                 Restore.
                                                                                   unsigned   pwrdnclmp:1
                                                                                 Power Down Clamp.
                                                                                   unsigned   pwrdnrstn:1
                                                                                 Power Down Reset.
                                                                                   unsigned   pwrdnswtch:1
                                                                                 Power Down Switch.
                                                                                   unsigned   dis_vbus:1
                                                                                 Disable VBUS.
                                                                                   unsigned   lnstschng:1
                                                                                 Line State Change.
                                                                                   unsigned   lnstchng_msk:1
                                                                                 Line state change mask.
                                                                                   unsigned   rst_det:1
                                                                                 Reset Detected.
                                                                                   unsigned   rst_det_msk:1
                                                                                 Reset Detect mask.
                                                                                   unsigned   disconn_det:1
                                                                                 Disconnect Detected.
                                                                                   unsigned   disconn_det_msk:1
                                                                                 Disconnect Detect mask.
                                                                                   unsigned   connect_det:1
                                                                                 Connect Detected.
                                                                                   unsigned   connect_det_msk:1
                                                                                 Connect Detected Mask.
                                                                                   unsigned   srp_det:1
                                                                                 SRP Detected.
                                                                                   unsigned   srp_det_msk:1
                                                                                 SRP Detect mask.
                                                                                   unsigned   sts_chngint:1
                                                                                 Status Change Interrupt.
                                                                                   unsigned   sts_chngint_msk:1
                                                                                 Status Change Interrupt Mask.
                                                                                   unsigned   linestate:2
                                                                                 Line State.
                                                                                   unsigned   idsts:1
                                                                                 Indicates current mode(status of IDDIG signal).
                                                                                   unsigned   bsessvld:1
                                                                                 B Session Valid signal status.
                                                                                   unsigned   adp_int:1
                                                                                 ADP Event Detected.
                                                                                   unsigned   mult_val_id_bc:5
                                                                                 Multi Valued ID pin.
                                                                                   unsigned   reserved29_31:3
                                                                                 Reserved 24_31.
                                                                                } b
                                                                                 register bits
                                                                                +-

                                                                                Detailed Description

                                                                                +-This union represents the bit fields in the Global Power Down Register Register. +-

                                                                                +-Read the register into the d32 member then set/clear the bits using the bit elements. +-

                                                                                +- +-

                                                                                +-Definition at line 2486 of file dwc_otg_regs.h.

                                                                                The documentation for this union was generated from the following file: +-
                                                                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/uniongrstctl__data.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/uniongrstctl__data.html 2013-07-26 19:34:43.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,296 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: grstctl_data Union Reference +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                grstctl_data Union Reference

                                                                                This union represents the bit fields of the Core Reset Register (GRSTCTL). +-More... +-

                                                                                +-#include <dwc_otg_regs.h> +-

                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-

                                                                                Data Fields

                                                                                +-uint32_t d32
                                                                                 raw register data
                                                                                +-struct {
                                                                                   unsigned   csftrst:1
                                                                                 Core Soft Reset (CSftRst) (Device and Host).
                                                                                   unsigned   hsftrst:1
                                                                                 Hclk Soft Reset.
                                                                                   unsigned   hstfrm:1
                                                                                 Host Frame Counter Reset (Host Only)
                                                                                +-.
                                                                                   unsigned   intknqflsh:1
                                                                                 In Token Sequence Learning Queue Flush (INTknQFlsh) (Device Only).
                                                                                   unsigned   rxfflsh:1
                                                                                 RxFIFO Flush (RxFFlsh) (Device and Host).
                                                                                   unsigned   txfflsh:1
                                                                                 TxFIFO Flush (TxFFlsh) (Device and Host).
                                                                                   unsigned   txfnum:5
                                                                                 TxFIFO Number (TxFNum) (Device and Host).
                                                                                   unsigned   reserved11_29:19
                                                                                 Reserved.
                                                                                   unsigned   dmareq:1
                                                                                 DMA Request Signal.
                                                                                   unsigned   ahbidle:1
                                                                                 AHB Master Idle.
                                                                                } b
                                                                                 register bits
                                                                                +-

                                                                                Detailed Description

                                                                                +-This union represents the bit fields of the Core Reset Register (GRSTCTL). +-

                                                                                +-Set/clear the bits using the bit fields then write the d32 value to the register. +-

                                                                                +- +-

                                                                                +-Definition at line 307 of file dwc_otg_regs.h.

                                                                                Field Documentation

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                unsigned grstctl_data::csftrst
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Core Soft Reset (CSftRst) (Device and Host). +-

                                                                                +-The application can flush the control logic in the entire core using this bit. This bit resets the pipelines in the AHB Clock domain as well as the PHY Clock domain.

                                                                                +-The state machines are reset to an IDLE state, the control bits in the CSRs are cleared, all the transmit FIFOs and the receive FIFO are flushed.

                                                                                +-The status mask bits that control the generation of the interrupt, are cleared, to clear the interrupt. The interrupt status bits are not cleared, so the application can get the status of any events that occurred in the core after it has set this bit.

                                                                                +-Any transactions on the AHB are terminated as soon as possible following the protocol. Any transactions on the USB are terminated immediately.

                                                                                +-The configuration settings in the CSRs are unchanged, so the software doesn't have to reprogram these registers (Device Configuration/Host Configuration/Core System Configuration/Core PHY Configuration).

                                                                                +-The application can write to this bit, any time it wants to reset the core. This is a self clearing bit and the core clears this bit after all the necessary logic is reset in the core, which may take several clocks, depending on the current state of the core. +-

                                                                                +-Definition at line 347 of file dwc_otg_regs.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                unsigned grstctl_data::hsftrst
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Hclk Soft Reset. +-

                                                                                +-The application uses this bit to reset the control logic in the AHB clock domain. Only AHB clock domain pipelines are reset. +-

                                                                                +-Definition at line 354 of file dwc_otg_regs.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                unsigned grstctl_data::hstfrm
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Host Frame Counter Reset (Host Only)
                                                                                +-. +-

                                                                                +-The application can reset the (micro)frame number counter inside the core, using this bit. When the (micro)frame counter is reset, the subsequent SOF sent out by the core, will have a (micro)frame number of 0. +-

                                                                                +-Definition at line 363 of file dwc_otg_regs.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                unsigned grstctl_data::rxfflsh
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-RxFIFO Flush (RxFFlsh) (Device and Host). +-

                                                                                +-The application can flush the entire Receive FIFO using this bit. The application must first ensure that the core is not in the middle of a transaction. The application should write into this bit, only after making sure that neither the DMA engine is reading from the RxFIFO nor the MAC is writing the data in to the FIFO. The application should wait until the bit is cleared before performing any other operations. This bit will takes 8 clocks (slowest of PHY or AHB clock) to clear. +-

                                                                                +-Definition at line 382 of file dwc_otg_regs.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                unsigned grstctl_data::txfflsh
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-TxFIFO Flush (TxFFlsh) (Device and Host). +-

                                                                                +-This bit is used to selectively flush a single or all transmit FIFOs. The application must first ensure that the core is not in the middle of a transaction. The application should write into this bit, only after making sure that neither the DMA engine is writing into the TxFIFO nor the MAC is reading the data out of the FIFO. The application should wait until the core clears this bit, before performing any operations. This bit will takes 8 clocks (slowest of PHY or AHB clock) to clear. +-

                                                                                +-Definition at line 397 of file dwc_otg_regs.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                unsigned grstctl_data::txfnum
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-TxFIFO Number (TxFNum) (Device and Host). +-

                                                                                +-This is the FIFO number which needs to be flushed, using the TxFIFO Flush bit. This field should not be changed until the TxFIFO Flush bit is cleared by the core.

                                                                                  +-
                                                                                • 0x0 : Non Periodic TxFIFO Flush
                                                                                • 0x1 : Periodic TxFIFO #1 Flush in device mode or Periodic TxFIFO in host mode
                                                                                • 0x2 : Periodic TxFIFO #2 Flush in device mode.
                                                                                • ...
                                                                                • 0xF : Periodic TxFIFO #15 Flush in device mode
                                                                                • 0x10: Flush all the Transmit NonPeriodic and Transmit Periodic FIFOs in the core
                                                                                +- +-

                                                                                +-Definition at line 414 of file dwc_otg_regs.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                unsigned grstctl_data::dmareq
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-DMA Request Signal. +-

                                                                                +-Indicated DMA request is in probress. Used for debug purpose. +-

                                                                                +-Definition at line 419 of file dwc_otg_regs.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                unsigned grstctl_data::ahbidle
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-AHB Master Idle. +-

                                                                                +-Indicates the AHB Master State Machine is in IDLE condition. +-

                                                                                +-Definition at line 422 of file dwc_otg_regs.h.

                                                                                +-

                                                                                The documentation for this union was generated from the following file: +-
                                                                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/uniongsnpsid__data.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/uniongsnpsid__data.html 2013-07-26 19:34:43.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,42 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: gsnpsid_data Union Reference +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                gsnpsid_data Union Reference

                                                                                This union represents the bit fields in the Synopsys ID Register (GSNPSID). +-More... +-

                                                                                +-#include <dwc_otg_regs.h> +-

                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +-

                                                                                Data Fields

                                                                                +-uint32_t d32
                                                                                 raw register data
                                                                                +-struct {
                                                                                   unsigned   rwdata:32
                                                                                } b
                                                                                 register bits
                                                                                +-

                                                                                Detailed Description

                                                                                +-This union represents the bit fields in the Synopsys ID Register (GSNPSID). +-

                                                                                +-Read the register into the d32 element then read out the bits using the bit elements. +-

                                                                                +- +-

                                                                                +-Definition at line 710 of file dwc_otg_regs.h.

                                                                                The documentation for this union was generated from the following file: +-
                                                                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/unionguid__data.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/unionguid__data.html 2013-07-26 19:34:43.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,42 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: guid_data Union Reference +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                guid_data Union Reference

                                                                                This union represents the bit fields in the User ID Register (GUID). +-More... +-

                                                                                +-#include <dwc_otg_regs.h> +-

                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +-

                                                                                Data Fields

                                                                                +-uint32_t d32
                                                                                 raw register data
                                                                                +-struct {
                                                                                   unsigned   rwdata:32
                                                                                } b
                                                                                 register bits
                                                                                +-

                                                                                Detailed Description

                                                                                +-This union represents the bit fields in the User ID Register (GUID). +-

                                                                                +-Read the register into the d32 element then read out the bits using the bit elements. +-

                                                                                +- +-

                                                                                +-Definition at line 696 of file dwc_otg_regs.h.

                                                                                The documentation for this union was generated from the following file: +-
                                                                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/uniongusbcfg__data.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/uniongusbcfg__data.html 2013-07-26 19:34:43.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,94 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: gusbcfg_data Union Reference +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                gusbcfg_data Union Reference

                                                                                This union represents the bit fields of the Core USB Configuration Register (GUSBCFG). +-More... +-

                                                                                +-#include <dwc_otg_regs.h> +-

                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-

                                                                                Data Fields

                                                                                +-uint32_t d32
                                                                                 raw register data
                                                                                +-struct {
                                                                                   unsigned   toutcal:3
                                                                                   unsigned   phyif:1
                                                                                   unsigned   ulpi_utmi_sel:1
                                                                                   unsigned   fsintf:1
                                                                                   unsigned   physel:1
                                                                                   unsigned   ddrsel:1
                                                                                   unsigned   srpcap:1
                                                                                   unsigned   hnpcap:1
                                                                                   unsigned   usbtrdtim:4
                                                                                   unsigned   reserved1:1
                                                                                   unsigned   phylpwrclksel:1
                                                                                   unsigned   otgutmifssel:1
                                                                                   unsigned   ulpi_fsls:1
                                                                                   unsigned   ulpi_auto_res:1
                                                                                   unsigned   ulpi_clk_sus_m:1
                                                                                   unsigned   ulpi_ext_vbus_drv:1
                                                                                   unsigned   ulpi_int_vbus_indicator:1
                                                                                   unsigned   term_sel_dl_pulse:1
                                                                                   unsigned   indicator_complement:1
                                                                                   unsigned   indicator_pass_through:1
                                                                                   unsigned   ulpi_int_prot_dis:1
                                                                                   unsigned   ic_usb_cap:1
                                                                                   unsigned   ic_traffic_pull_remove:1
                                                                                   unsigned   tx_end_delay:1
                                                                                   unsigned   force_host_mode:1
                                                                                   unsigned   force_dev_mode:1
                                                                                   unsigned   reserved31:1
                                                                                } b
                                                                                 register bits
                                                                                +-

                                                                                Detailed Description

                                                                                +-This union represents the bit fields of the Core USB Configuration Register (GUSBCFG). +-

                                                                                +-Set the bits using the bit fields then write the d32 value to the register. +-

                                                                                +- +-

                                                                                +-Definition at line 267 of file dwc_otg_regs.h.

                                                                                The documentation for this union was generated from the following file: +-
                                                                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/unionhaint__data.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/unionhaint__data.html 2013-07-26 19:34:43.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,81 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: haint_data Union Reference +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                haint_data Union Reference

                                                                                This union represents the bit fields in the Host All Interrupt Register. +-More... +-

                                                                                +-#include <dwc_otg_regs.h> +-

                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-

                                                                                Data Fields

                                                                                +-uint32_t d32
                                                                                 raw register data
                                                                                +-struct {
                                                                                   unsigned   ch0:1
                                                                                   unsigned   ch1:1
                                                                                   unsigned   ch2:1
                                                                                   unsigned   ch3:1
                                                                                   unsigned   ch4:1
                                                                                   unsigned   ch5:1
                                                                                   unsigned   ch6:1
                                                                                   unsigned   ch7:1
                                                                                   unsigned   ch8:1
                                                                                   unsigned   ch9:1
                                                                                   unsigned   ch10:1
                                                                                   unsigned   ch11:1
                                                                                   unsigned   ch12:1
                                                                                   unsigned   ch13:1
                                                                                   unsigned   ch14:1
                                                                                   unsigned   ch15:1
                                                                                   unsigned   reserved:16
                                                                                } b
                                                                                 register bits
                                                                                +-struct {
                                                                                   unsigned   chint:16
                                                                                   unsigned   reserved:16
                                                                                } b2
                                                                                +-

                                                                                Detailed Description

                                                                                +-This union represents the bit fields in the Host All Interrupt Register. +-

                                                                                +- +-

                                                                                +-Definition at line 2001 of file dwc_otg_regs.h.

                                                                                The documentation for this union was generated from the following file: +-
                                                                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/unionhaintmsk__data.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/unionhaintmsk__data.html 2013-07-26 19:34:43.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,81 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: haintmsk_data Union Reference +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                haintmsk_data Union Reference

                                                                                This union represents the bit fields in the Host All Interrupt Register. +-More... +-

                                                                                +-#include <dwc_otg_regs.h> +-

                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-

                                                                                Data Fields

                                                                                +-uint32_t d32
                                                                                 raw register data
                                                                                +-struct {
                                                                                   unsigned   ch0:1
                                                                                   unsigned   ch1:1
                                                                                   unsigned   ch2:1
                                                                                   unsigned   ch3:1
                                                                                   unsigned   ch4:1
                                                                                   unsigned   ch5:1
                                                                                   unsigned   ch6:1
                                                                                   unsigned   ch7:1
                                                                                   unsigned   ch8:1
                                                                                   unsigned   ch9:1
                                                                                   unsigned   ch10:1
                                                                                   unsigned   ch11:1
                                                                                   unsigned   ch12:1
                                                                                   unsigned   ch13:1
                                                                                   unsigned   ch14:1
                                                                                   unsigned   ch15:1
                                                                                   unsigned   reserved:16
                                                                                } b
                                                                                 register bits
                                                                                +-struct {
                                                                                   unsigned   chint:16
                                                                                   unsigned   reserved:16
                                                                                } b2
                                                                                +-

                                                                                Detailed Description

                                                                                +-This union represents the bit fields in the Host All Interrupt Register. +-

                                                                                +- +-

                                                                                +-Definition at line 2035 of file dwc_otg_regs.h.

                                                                                The documentation for this union was generated from the following file: +-
                                                                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/unionhcchar__data.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/unionhcchar__data.html 2013-07-26 19:34:43.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,127 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: hcchar_data Union Reference +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                hcchar_data Union Reference

                                                                                This union represents the bit fields in the Host Channel Characteristics Register. +-More... +-

                                                                                +-#include <dwc_otg_regs.h> +-

                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-

                                                                                Data Fields

                                                                                +-uint32_t d32
                                                                                 raw register data
                                                                                +-struct {
                                                                                   unsigned   mps:11
                                                                                 Maximum packet size in bytes.
                                                                                   unsigned   epnum:4
                                                                                 Endpoint number.
                                                                                   unsigned   epdir:1
                                                                                 0: OUT, 1: IN
                                                                                   unsigned   reserved:1
                                                                                   unsigned   lspddev:1
                                                                                 0: Full/high speed device, 1: Low speed device
                                                                                   unsigned   eptype:2
                                                                                 0: Control, 1: Isoc, 2: Bulk, 3: Intr
                                                                                   unsigned   multicnt:2
                                                                                 Packets per frame for periodic transfers.
                                                                                   unsigned   devaddr:7
                                                                                 Device address.
                                                                                   unsigned   oddfrm:1
                                                                                 Frame to transmit periodic transaction.
                                                                                   unsigned   chdis:1
                                                                                 Channel disable.
                                                                                   unsigned   chen:1
                                                                                 Channel enable.
                                                                                } b
                                                                                 register bits
                                                                                +-

                                                                                Detailed Description

                                                                                +-This union represents the bit fields in the Host Channel Characteristics Register. +-

                                                                                +-Read the register into the d32 member then set/clear the bits using the bit elements. Write the d32 member to the hcchar register. +-

                                                                                +- +-

                                                                                +-Definition at line 2092 of file dwc_otg_regs.h.

                                                                                Field Documentation

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                unsigned hcchar_data::multicnt
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Packets per frame for periodic transfers. +-

                                                                                +-0 is reserved. +-

                                                                                +-Definition at line 2116 of file dwc_otg_regs.h.

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                unsigned hcchar_data::oddfrm
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Frame to transmit periodic transaction. +-

                                                                                +-0: even, 1: odd +-

                                                                                +-Definition at line 2125 of file dwc_otg_regs.h.

                                                                                +-

                                                                                The documentation for this union was generated from the following file: +-
                                                                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/unionhcdma__data.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/unionhcdma__data.html 2013-07-26 19:34:43.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,74 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: hcdma_data Union Reference +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                hcdma_data Union Reference

                                                                                This union represents the bit fields in the Host DMA Address Register used in Descriptor DMA mode. +-More... +-

                                                                                +-#include <dwc_otg_regs.h> +-

                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-

                                                                                Data Fields

                                                                                +-uint32_t d32
                                                                                 raw register data
                                                                                +-struct {
                                                                                   unsigned   reserved0_2:3
                                                                                   unsigned   ctd:8
                                                                                 Current Transfer Descriptor.
                                                                                   unsigned   dma_addr:21
                                                                                 Start Address of Descriptor List.
                                                                                } b
                                                                                 register bits
                                                                                +-

                                                                                Detailed Description

                                                                                +-This union represents the bit fields in the Host DMA Address Register used in Descriptor DMA mode. +-

                                                                                +- +-

                                                                                +-Definition at line 2307 of file dwc_otg_regs.h.

                                                                                Field Documentation

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                unsigned hcdma_data::ctd
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Current Transfer Descriptor. +-

                                                                                +-Not used for ISOC +-

                                                                                +-Definition at line 2314 of file dwc_otg_regs.h.

                                                                                +-

                                                                                The documentation for this union was generated from the following file: +-
                                                                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/unionhcfg__data.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/unionhcfg__data.html 2013-07-26 19:34:43.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,69 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: hcfg_data Union Reference +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                hcfg_data Union Reference

                                                                                This union represents the bit fields in the Host Configuration Register. +-More... +-

                                                                                +-#include <dwc_otg_regs.h> +-

                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-

                                                                                Data Fields

                                                                                +-uint32_t d32
                                                                                 raw register data
                                                                                +-struct {
                                                                                   unsigned   fslspclksel:2
                                                                                 FS/LS Phy Clock Select.
                                                                                   unsigned   fslssupp:1
                                                                                 FS/LS Only Support.
                                                                                   unsigned   reserved3_6:4
                                                                                   unsigned   ena32khzs:1
                                                                                 Enable 32-KHz Suspend Mode.
                                                                                   unsigned   resvalid:8
                                                                                 Resume Validation Periiod.
                                                                                   unsigned   reserved16_22:7
                                                                                   unsigned   descdma:1
                                                                                 Enable Scatter/gather DMA in Host mode.
                                                                                   unsigned   frlisten:2
                                                                                 Frame List Entries.
                                                                                   unsigned   perschedena:1
                                                                                 Enable Periodic Scheduling.
                                                                                   unsigned   reserved27_30:4
                                                                                   unsigned   modechtimen:1
                                                                                } b
                                                                                 register bits
                                                                                +-

                                                                                Detailed Description

                                                                                +-This union represents the bit fields in the Host Configuration Register. +-

                                                                                +-Read the register into the d32 member then set/clear the bits using the bit elements. Write the d32 member to the hcfg register. +-

                                                                                +- +-

                                                                                +-Definition at line 1878 of file dwc_otg_regs.h.

                                                                                The documentation for this union was generated from the following file: +-
                                                                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/unionhcint__data.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/unionhcint__data.html 2013-07-26 19:34:43.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,83 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: hcint_data Union Reference +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                hcint_data Union Reference

                                                                                This union represents the bit fields in the Host All Interrupt Register. +-More... +-

                                                                                +-#include <dwc_otg_regs.h> +-

                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-

                                                                                Data Fields

                                                                                +-uint32_t d32
                                                                                 raw register data
                                                                                +-struct {
                                                                                   unsigned   xfercomp:1
                                                                                 Transfer Complete.
                                                                                   unsigned   chhltd:1
                                                                                 Channel Halted.
                                                                                   unsigned   ahberr:1
                                                                                 AHB Error.
                                                                                   unsigned   stall:1
                                                                                 STALL Response Received.
                                                                                   unsigned   nak:1
                                                                                 NAK Response Received.
                                                                                   unsigned   ack:1
                                                                                 ACK Response Received.
                                                                                   unsigned   nyet:1
                                                                                 NYET Response Received.
                                                                                   unsigned   xacterr:1
                                                                                 Transaction Err.
                                                                                   unsigned   bblerr:1
                                                                                 Babble Error.
                                                                                   unsigned   frmovrun:1
                                                                                 Frame Overrun.
                                                                                   unsigned   datatglerr:1
                                                                                 Data Toggle Error.
                                                                                   unsigned   bna:1
                                                                                 Buffer Not Available (only for DDMA mode).
                                                                                   unsigned   xcs_xact:1
                                                                                 Exessive transaction error (only for DDMA mode).
                                                                                   unsigned   frm_list_roll:1
                                                                                 Frame List Rollover interrupt.
                                                                                   unsigned   reserved14_31:18
                                                                                 Reserved.
                                                                                } b
                                                                                 register bits
                                                                                +-

                                                                                Detailed Description

                                                                                +-This union represents the bit fields in the Host All Interrupt Register. +-

                                                                                +- +-

                                                                                +-Definition at line 2169 of file dwc_otg_regs.h.

                                                                                The documentation for this union was generated from the following file: +-
                                                                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/unionhcintmsk__data.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/unionhcintmsk__data.html 2013-07-26 19:34:43.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,70 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: hcintmsk_data Union Reference +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                hcintmsk_data Union Reference

                                                                                This union represents the bit fields in the Host Channel Interrupt Mask Register. +-More... +-

                                                                                +-#include <dwc_otg_regs.h> +-

                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-

                                                                                Data Fields

                                                                                +-uint32_t d32
                                                                                 raw register data
                                                                                +-struct {
                                                                                   unsigned   xfercompl:1
                                                                                   unsigned   chhltd:1
                                                                                   unsigned   ahberr:1
                                                                                   unsigned   stall:1
                                                                                   unsigned   nak:1
                                                                                   unsigned   ack:1
                                                                                   unsigned   nyet:1
                                                                                   unsigned   xacterr:1
                                                                                   unsigned   bblerr:1
                                                                                   unsigned   frmovrun:1
                                                                                   unsigned   datatglerr:1
                                                                                   unsigned   bna:1
                                                                                   unsigned   xcs_xact:1
                                                                                   unsigned   frm_list_roll:1
                                                                                   unsigned   reserved14_31:18
                                                                                } b
                                                                                 register bits
                                                                                +-

                                                                                Detailed Description

                                                                                +-This union represents the bit fields in the Host Channel Interrupt Mask Register. +-

                                                                                +-Read the register into the d32 member then set/clear the bits using the bit elements. Write the d32 member to the hcintmsk register. +-

                                                                                +- +-

                                                                                +-Definition at line 2213 of file dwc_otg_regs.h.

                                                                                The documentation for this union was generated from the following file: +-
                                                                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/unionhctsiz__data.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/unionhctsiz__data.html 2013-07-26 19:34:43.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,101 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: hctsiz_data Union Reference +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                hctsiz_data Union Reference

                                                                                This union represents the bit fields in the Host Channel Transfer Size Register. +-More... +-

                                                                                +-#include <dwc_otg_regs.h> +-

                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-

                                                                                Data Fields

                                                                                +-uint32_t d32
                                                                                 raw register data
                                                                                +-struct {
                                                                                   unsigned   xfersize:19
                                                                                 Total transfer size in bytes.
                                                                                   unsigned   pktcnt:10
                                                                                 Data packets to transfer.
                                                                                   unsigned   pid:2
                                                                                 Packet ID for next data packet 0: DATA0 1: DATA2 2: DATA1 3: MDATA (non-Control), SETUP (Control).
                                                                                   unsigned   dopng:1
                                                                                 Do PING protocol when 1.
                                                                                } b
                                                                                 register bits
                                                                                +-struct {
                                                                                   unsigned   schinfo:8
                                                                                 Scheduling information.
                                                                                   unsigned   ntd:8
                                                                                 Number of transfer descriptors.
                                                                                   unsigned   reserved16_28:13
                                                                                 Data packets to transfer.
                                                                                   unsigned   pid:2
                                                                                 Packet ID for next data packet 0: DATA0 1: DATA2 2: DATA1 3: MDATA (non-Control).
                                                                                   unsigned   dopng:1
                                                                                 Do PING protocol when 1.
                                                                                } b_ddma
                                                                                 register bits
                                                                                +-

                                                                                Detailed Description

                                                                                +-This union represents the bit fields in the Host Channel Transfer Size Register. +-

                                                                                +-Read the register into the d32 member then set/clear the bits using the bit elements. Write the d32 member to the hcchar register. +-

                                                                                +- +-

                                                                                +-Definition at line 2244 of file dwc_otg_regs.h.

                                                                                Field Documentation

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                unsigned hctsiz_data::ntd
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Number of transfer descriptors. +-

                                                                                +-Max value: 64 in general, 256 only for HS isochronous endpoint. +-

                                                                                +-Definition at line 2284 of file dwc_otg_regs.h.

                                                                                +-

                                                                                The documentation for this union was generated from the following file: +-
                                                                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/unionhfir__data.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/unionhfir__data.html 2013-07-26 19:34:43.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,44 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: hfir_data Union Reference +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                hfir_data Union Reference

                                                                                This union represents the bit fields in the Host Frame Remaing/Number Register. +-More... +-

                                                                                +-#include <dwc_otg_regs.h> +-

                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-

                                                                                Data Fields

                                                                                +-uint32_t d32
                                                                                 raw register data
                                                                                +-struct {
                                                                                   unsigned   frint:16
                                                                                   unsigned   hfirrldctrl:1
                                                                                   unsigned   reserved:15
                                                                                } b
                                                                                 register bits
                                                                                +-

                                                                                Detailed Description

                                                                                +-This union represents the bit fields in the Host Frame Remaing/Number Register. +-

                                                                                +- +-

                                                                                +-Definition at line 1913 of file dwc_otg_regs.h.

                                                                                The documentation for this union was generated from the following file: +-
                                                                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/unionhfnum__data.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/unionhfnum__data.html 2013-07-26 19:34:43.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,42 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: hfnum_data Union Reference +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                hfnum_data Union Reference

                                                                                This union represents the bit fields in the Host Frame Remaing/Number Register. +-More... +-

                                                                                +-#include <dwc_otg_regs.h> +-

                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-

                                                                                Data Fields

                                                                                +-uint32_t d32
                                                                                 raw register data
                                                                                +-struct {
                                                                                   unsigned   frnum:16
                                                                                   unsigned   frrem:16
                                                                                } b
                                                                                 register bits
                                                                                +-

                                                                                Detailed Description

                                                                                +-This union represents the bit fields in the Host Frame Remaing/Number Register. +-

                                                                                +- +-

                                                                                +-Definition at line 1929 of file dwc_otg_regs.h.

                                                                                The documentation for this union was generated from the following file: +-
                                                                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/unionhost__dma__desc__sts.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/unionhost__dma__desc__sts.html 2013-07-26 19:34:43.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,119 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: host_dma_desc_sts Union Reference +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                host_dma_desc_sts Union Reference

                                                                                This union represents the bit fields in the DMA Descriptor status quadlet for host mode. +-More... +-

                                                                                +-#include <dwc_otg_regs.h> +-

                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-

                                                                                Data Fields

                                                                                +-uint32_t d32
                                                                                 raw register data
                                                                                +-struct {
                                                                                   unsigned   n_bytes:17
                                                                                 Number of bytes.
                                                                                   unsigned   qtd_offset:6
                                                                                 QTD offset to jump when Short Packet received - only for IN EPs.
                                                                                   unsigned   a_qtd:1
                                                                                 Set to request the core to jump to alternate QTD if Short Packet received - only for IN EPs.
                                                                                   unsigned   sup:1
                                                                                 Setup Packet bit.
                                                                                   unsigned   ioc:1
                                                                                 Interrupt On Complete.
                                                                                   unsigned   eol:1
                                                                                 End of List.
                                                                                   unsigned   reserved27:1
                                                                                   unsigned   sts:2
                                                                                 Rx/Tx Status.
                                                                                   unsigned   reserved30:1
                                                                                   unsigned   a:1
                                                                                 Active Bit.
                                                                                } b
                                                                                 quadlet bits
                                                                                +-struct {
                                                                                   unsigned   n_bytes:12
                                                                                 Number of bytes.
                                                                                   unsigned   reserved12_24:13
                                                                                   unsigned   ioc:1
                                                                                 Interrupt On Complete.
                                                                                   unsigned   reserved26_27:2
                                                                                   unsigned   sts:2
                                                                                 Rx/Tx Status.
                                                                                   unsigned   reserved30:1
                                                                                   unsigned   a:1
                                                                                 Active Bit.
                                                                                } b_isoc
                                                                                +-

                                                                                Detailed Description

                                                                                +-This union represents the bit fields in the DMA Descriptor status quadlet for host mode. +-

                                                                                +-Read the quadlet into the d32 member then set/clear the bits using the bit elements. +-

                                                                                +- +-

                                                                                +-Definition at line 2325 of file dwc_otg_regs.h.

                                                                                Field Documentation

                                                                                +-

                                                                                +- +- +- +- +-
                                                                                +- +- +- +- +-
                                                                                unsigned host_dma_desc_sts::sup
                                                                                +-
                                                                                +- +- +- +- +- +-
                                                                                +-   +- +- +-

                                                                                +-Setup Packet bit. +-

                                                                                +-When set indicates that buffer contains setup packet. +-

                                                                                +-Definition at line 2345 of file dwc_otg_regs.h.

                                                                                +-

                                                                                The documentation for this union was generated from the following file: +-
                                                                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/unionhost__grxsts__data.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/unionhost__grxsts__data.html 2013-07-26 19:34:43.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,48 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: host_grxsts_data Union Reference +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                host_grxsts_data Union Reference

                                                                                This union represents the bit fields in the Host Receive Status Read and Pop Registers (GRXSTSR, GRXSTSP) Read the register into the d32 element then read out the bits using the bit elements. +-More... +-

                                                                                +-#include <dwc_otg_regs.h> +-

                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-

                                                                                Data Fields

                                                                                +-uint32_t d32
                                                                                 raw register data
                                                                                +-struct {
                                                                                   unsigned   chnum:4
                                                                                   unsigned   bcnt:11
                                                                                   unsigned   dpid:2
                                                                                   unsigned   pktsts:4
                                                                                   unsigned   reserved21_31:11
                                                                                } b
                                                                                 register bits
                                                                                +-

                                                                                Detailed Description

                                                                                +-This union represents the bit fields in the Host Receive Status Read and Pop Registers (GRXSTSR, GRXSTSP) Read the register into the d32 element then read out the bits using the bit elements. +-

                                                                                +- +-

                                                                                +-Definition at line 548 of file dwc_otg_regs.h.

                                                                                The documentation for this union was generated from the following file: +-
                                                                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/unionhprt0__data.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/unionhprt0__data.html 2013-07-26 19:34:43.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,70 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: hprt0_data Union Reference +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                hprt0_data Union Reference

                                                                                This union represents the bit fields in the Host Port Control and Status Register. +-More... +-

                                                                                +-#include <dwc_otg_regs.h> +-

                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-

                                                                                Data Fields

                                                                                +-uint32_t d32
                                                                                 raw register data
                                                                                +-struct {
                                                                                   unsigned   prtconnsts:1
                                                                                   unsigned   prtconndet:1
                                                                                   unsigned   prtena:1
                                                                                   unsigned   prtenchng:1
                                                                                   unsigned   prtovrcurract:1
                                                                                   unsigned   prtovrcurrchng:1
                                                                                   unsigned   prtres:1
                                                                                   unsigned   prtsusp:1
                                                                                   unsigned   prtrst:1
                                                                                   unsigned   reserved9:1
                                                                                   unsigned   prtlnsts:2
                                                                                   unsigned   prtpwr:1
                                                                                   unsigned   prttstctl:4
                                                                                   unsigned   prtspd:2
                                                                                   unsigned   reserved19_31:13
                                                                                } b
                                                                                 register bits
                                                                                +-

                                                                                Detailed Description

                                                                                +-This union represents the bit fields in the Host Port Control and Status Register. +-

                                                                                +-Read the register into the d32 member then set/clear the bits using the bit elements. Write the d32 member to the hprt0 register. +-

                                                                                +- +-

                                                                                +-Definition at line 1971 of file dwc_otg_regs.h.

                                                                                The documentation for this union was generated from the following file: +-
                                                                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/unionhwcfg1__data.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/unionhwcfg1__data.html 2013-07-26 19:34:43.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,72 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: hwcfg1_data Union Reference +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                hwcfg1_data Union Reference

                                                                                This union represents the bit fields in the User HW Config1 Register. +-More... +-

                                                                                +-#include <dwc_otg_regs.h> +-

                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-

                                                                                Data Fields

                                                                                +-uint32_t d32
                                                                                 raw register data
                                                                                +-struct {
                                                                                   unsigned   ep_dir0:2
                                                                                   unsigned   ep_dir1:2
                                                                                   unsigned   ep_dir2:2
                                                                                   unsigned   ep_dir3:2
                                                                                   unsigned   ep_dir4:2
                                                                                   unsigned   ep_dir5:2
                                                                                   unsigned   ep_dir6:2
                                                                                   unsigned   ep_dir7:2
                                                                                   unsigned   ep_dir8:2
                                                                                   unsigned   ep_dir9:2
                                                                                   unsigned   ep_dir10:2
                                                                                   unsigned   ep_dir11:2
                                                                                   unsigned   ep_dir12:2
                                                                                   unsigned   ep_dir13:2
                                                                                   unsigned   ep_dir14:2
                                                                                   unsigned   ep_dir15:2
                                                                                } b
                                                                                 register bits
                                                                                +-

                                                                                Detailed Description

                                                                                +-This union represents the bit fields in the User HW Config1 Register. +-

                                                                                +-Read the register into the d32 element then read out the bits using the bit elements. +-

                                                                                +- +-

                                                                                +-Definition at line 724 of file dwc_otg_regs.h.

                                                                                The documentation for this union was generated from the following file: +-
                                                                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/unionhwcfg2__data.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/unionhwcfg2__data.html 2013-07-26 19:34:43.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,70 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: hwcfg2_data Union Reference +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                hwcfg2_data Union Reference

                                                                                This union represents the bit fields in the User HW Config2 Register. +-More... +-

                                                                                +-#include <dwc_otg_regs.h> +-

                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-

                                                                                Data Fields

                                                                                +-uint32_t d32
                                                                                 raw register data
                                                                                +-struct {
                                                                                   unsigned   op_mode:3
                                                                                   unsigned   architecture:2
                                                                                   unsigned   point2point:1
                                                                                   unsigned   hs_phy_type:2
                                                                                   unsigned   fs_phy_type:2
                                                                                   unsigned   num_dev_ep:4
                                                                                   unsigned   num_host_chan:4
                                                                                   unsigned   perio_ep_supported:1
                                                                                   unsigned   dynamic_fifo:1
                                                                                   unsigned   multi_proc_int:1
                                                                                   unsigned   reserved21:1
                                                                                   unsigned   nonperio_tx_q_depth:2
                                                                                   unsigned   host_perio_tx_q_depth:2
                                                                                   unsigned   dev_token_q_depth:5
                                                                                   unsigned   otg_enable_ic_usb:1
                                                                                } b
                                                                                 register bits
                                                                                +-

                                                                                Detailed Description

                                                                                +-This union represents the bit fields in the User HW Config2 Register. +-

                                                                                +-Read the register into the d32 element then read out the bits using the bit elements. +-

                                                                                +- +-

                                                                                +-Definition at line 753 of file dwc_otg_regs.h.

                                                                                The documentation for this union was generated from the following file: +-
                                                                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/unionhwcfg3__data.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/unionhwcfg3__data.html 2013-07-26 19:34:43.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,64 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: hwcfg3_data Union Reference +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                hwcfg3_data Union Reference

                                                                                This union represents the bit fields in the User HW Config3 Register. +-More... +-

                                                                                +-#include <dwc_otg_regs.h> +-

                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-

                                                                                Data Fields

                                                                                +-uint32_t d32
                                                                                 raw register data
                                                                                +-struct {
                                                                                   unsigned   xfer_size_cntr_width:4
                                                                                   unsigned   packet_size_cntr_width:3
                                                                                   unsigned   otg_func:1
                                                                                   unsigned   i2c:1
                                                                                   unsigned   vendor_ctrl_if:1
                                                                                   unsigned   optional_features:1
                                                                                   unsigned   synch_reset_type:1
                                                                                   unsigned   adp_supp:1
                                                                                   unsigned   otg_enable_hsic:1
                                                                                   unsigned   bc_support:1
                                                                                   unsigned   otg_lpm_en:1
                                                                                   unsigned   dfifo_depth:16
                                                                                } b
                                                                                 register bits
                                                                                +-

                                                                                Detailed Description

                                                                                +-This union represents the bit fields in the User HW Config3 Register. +-

                                                                                +-Read the register into the d32 element then read out the bits using the bit elements. +-

                                                                                +- +-

                                                                                +-Definition at line 795 of file dwc_otg_regs.h.

                                                                                The documentation for this union was generated from the following file: +-
                                                                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/unionhwcfg4__data.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/unionhwcfg4__data.html 2013-07-26 19:34:43.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,72 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: hwcfg4_data Union Reference +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                hwcfg4_data Union Reference

                                                                                This union represents the bit fields in the User HW Config4 Register. +-More... +-

                                                                                +-#include <dwc_otg_regs.h> +-

                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-

                                                                                Data Fields

                                                                                +-uint32_t d32
                                                                                 raw register data
                                                                                +-struct {
                                                                                   unsigned   num_dev_perio_in_ep:4
                                                                                   unsigned   power_optimiz:1
                                                                                   unsigned   min_ahb_freq:1
                                                                                   unsigned   part_power_down:1
                                                                                   unsigned   reserved:7
                                                                                   unsigned   utmi_phy_data_width:2
                                                                                   unsigned   num_dev_mode_ctrl_ep:4
                                                                                   unsigned   iddig_filt_en:1
                                                                                   unsigned   vbus_valid_filt_en:1
                                                                                   unsigned   a_valid_filt_en:1
                                                                                   unsigned   b_valid_filt_en:1
                                                                                   unsigned   session_end_filt_en:1
                                                                                   unsigned   ded_fifo_en:1
                                                                                   unsigned   num_in_eps:4
                                                                                   unsigned   desc_dma:1
                                                                                   unsigned   desc_dma_dyn:1
                                                                                } b
                                                                                 register bits
                                                                                +-

                                                                                Detailed Description

                                                                                +-This union represents the bit fields in the User HW Config4 Register. +-

                                                                                +-Read the register into the d32 element then read out the bits using the bit elements. +-

                                                                                +- +-

                                                                                +-Definition at line 821 of file dwc_otg_regs.h.

                                                                                The documentation for this union was generated from the following file: +-
                                                                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/html/unionpcgcctl__data.html +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/html/unionpcgcctl__data.html 2013-07-26 19:34:43.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,88 +0,0 @@ +- +- +-DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver: pcgcctl_data Union Reference +- +- +- +-
                                                                                Main Page | Data Structures | File List | Data Fields | Globals | Related Pages
                                                                                +-

                                                                                pcgcctl_data Union Reference

                                                                                This union represents the bit fields in the Power and Clock Gating Control Register. +-More... +-

                                                                                +-#include <dwc_otg_regs.h> +-

                                                                                +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +- +-

                                                                                Data Fields

                                                                                +-uint32_t d32
                                                                                 raw register data
                                                                                +-struct {
                                                                                   unsigned   stoppclk:1
                                                                                 Stop Pclk.
                                                                                   unsigned   gatehclk:1
                                                                                 Gate Hclk.
                                                                                   unsigned   pwrclmp:1
                                                                                 Power Clamp.
                                                                                   unsigned   rstpdwnmodule:1
                                                                                 Reset Power Down Modules.
                                                                                   unsigned   reserved:1
                                                                                 Reserved.
                                                                                   unsigned   enbl_sleep_gating:1
                                                                                 Enable Sleep Clock Gating (Enbl_L1Gating).
                                                                                   unsigned   phy_in_sleep:1
                                                                                 PHY In Sleep (PhySleep).
                                                                                   unsigned   deep_sleep:1
                                                                                 Deep Sleep.
                                                                                   unsigned   resetaftsusp:1
                                                                                   unsigned   restoremode:1
                                                                                   unsigned   reserved10_12:3
                                                                                   unsigned   ess_reg_restored:1
                                                                                   unsigned   prt_clk_sel:2
                                                                                   unsigned   port_power:1
                                                                                   unsigned   max_xcvrselect:2
                                                                                   unsigned   max_termsel:1
                                                                                   unsigned   mac_dev_addr:7
                                                                                   unsigned   p2hd_dev_enum_spd:2
                                                                                   unsigned   p2hd_prt_spd:2
                                                                                   unsigned   if_dev_mode:1
                                                                                } b
                                                                                 register bits
                                                                                +-

                                                                                Detailed Description

                                                                                +-This union represents the bit fields in the Power and Clock Gating Control Register. +-

                                                                                +-Read the register into the d32 member then set/clear the bits using the bit elements. +-

                                                                                +- +-

                                                                                +-Definition at line 2427 of file dwc_otg_regs.h.

                                                                                The documentation for this union was generated from the following file: +-
                                                                                Generated on Thu Oct 27 03:56:38 2011 for DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver by  +- +-doxygen 1.3.9.1
                                                                                +- +- diff -Nru linux-3.2.46/debian/patches/rpi/rpi_217_d52d21b77c3e120afde1c7c298307ce176e21a94.patch linux-3.2.46/debian/patches/rpi/rpi_217_d52d21b77c3e120afde1c7c298307ce176e21a94.patch --- linux-3.2.46/debian/patches/rpi/rpi_217_d52d21b77c3e120afde1c7c298307ce176e21a94.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_217_d52d21b77c3e120afde1c7c298307ce176e21a94.patch 2013-07-26 19:35:34.000000000 +0000 @@ -0,0 +1,69 @@ +commit d52d21b77c3e120afde1c7c298307ce176e21a94 +Author: popcornmix +Date: Sun Aug 19 20:56:11 2012 +0100 + + Fix for broken GPIO with 3.2 kernel + +Index: linux-3.2.46/arch/arm/mach-bcm2708/bcm2708_gpio.c +=================================================================== +--- linux-3.2.46.orig/arch/arm/mach-bcm2708/bcm2708_gpio.c 2013-07-26 19:33:45.000000000 +0000 ++++ linux-3.2.46/arch/arm/mach-bcm2708/bcm2708_gpio.c 2013-07-26 19:35:33.000000000 +0000 +@@ -70,7 +70,7 @@ + unsigned gpio_field_offset = (offset - 10 * gpio_bank) * 3; + + //printk(KERN_ERR DRIVER_NAME ": bcm2708_gpio_set_function %p (%d,%d)\n", gc, offset, function); +- if (offset >= ARCH_NR_GPIOS) ++ if (offset >= BCM_NR_GPIOS) + return -EINVAL; + + spin_lock_irqsave(&lock, flags); +@@ -108,7 +108,7 @@ + unsigned gpio_field_offset = (offset - 32 * gpio_bank); + unsigned lev; + +- if (offset >= ARCH_NR_GPIOS) ++ if (offset >= BCM_NR_GPIOS) + return 0; + lev = readl(gpio->base + GPIOLEV(gpio_bank)); + //printk(KERN_ERR DRIVER_NAME ": bcm2708_gpio_get %p (%d)=%d\n", gc, offset, 0x1 & (lev>>gpio_field_offset)); +@@ -121,7 +121,7 @@ + unsigned gpio_bank = offset / 32; + unsigned gpio_field_offset = (offset - 32 * gpio_bank); + //printk(KERN_ERR DRIVER_NAME ": bcm2708_gpio_set %p (%d=%d)\n", gc, offset, value); +- if (offset >= ARCH_NR_GPIOS) ++ if (offset >= BCM_NR_GPIOS) + return; + if (value) + writel(1 << gpio_field_offset, gpio->base + GPIOSET(gpio_bank)); +@@ -280,7 +280,7 @@ + + ucb->gc.label = "bcm2708_gpio"; + ucb->gc.base = 0; +- ucb->gc.ngpio = ARCH_NR_GPIOS; ++ ucb->gc.ngpio = BCM_NR_GPIOS; + ucb->gc.owner = THIS_MODULE; + + ucb->gc.direction_input = bcm2708_gpio_dir_in; +Index: linux-3.2.46/arch/arm/mach-bcm2708/include/mach/gpio.h +=================================================================== +--- linux-3.2.46.orig/arch/arm/mach-bcm2708/include/mach/gpio.h 2013-07-26 19:33:45.000000000 +0000 ++++ linux-3.2.46/arch/arm/mach-bcm2708/include/mach/gpio.h 2013-07-26 19:35:33.000000000 +0000 +@@ -9,7 +9,7 @@ + #ifndef __ASM_ARCH_GPIO_H + #define __ASM_ARCH_GPIO_H + +-#define ARCH_NR_GPIOS 54 // number of gpio lines ++#define BCM_NR_GPIOS 54 // number of gpio lines + + #include + #include +@@ -40,6 +40,9 @@ + static inline unsigned gpio_to_irq(unsigned gpio) { + return GPIO_IRQ_START+gpio; + } ++#define gpio_to_irq gpio_to_irq ++ + #endif /* CONFIG_GPIOLIB */ + + #endif ++ diff -Nru linux-3.2.46/debian/patches/rpi/rpi_218_e5c8bb0e76069d9afefcc9d96d8faca384cc67d2.patch linux-3.2.46/debian/patches/rpi/rpi_218_e5c8bb0e76069d9afefcc9d96d8faca384cc67d2.patch --- linux-3.2.46/debian/patches/rpi/rpi_218_e5c8bb0e76069d9afefcc9d96d8faca384cc67d2.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_218_e5c8bb0e76069d9afefcc9d96d8faca384cc67d2.patch 2013-07-26 19:35:36.000000000 +0000 @@ -0,0 +1,32 @@ +commit e5c8bb0e76069d9afefcc9d96d8faca384cc67d2 +Author: ddv2005 +Date: Mon Aug 20 10:48:38 2012 -0400 + + Revert "Disable IRQs in dwc_otg_hcd_qh_free" because DWC_DMA_FREE should be called with enabled IRQs. + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_hcd_queue.c +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/dwc_otg_hcd_queue.c 2013-07-26 19:35:17.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_hcd_queue.c 2013-07-26 19:35:35.000000000 +0000 +@@ -54,11 +54,10 @@ + */ + void dwc_otg_hcd_qh_free(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh) + { +- dwc_irqflags_t flags; + dwc_otg_qtd_t *qtd, *qtd_tmp; + + /* Free each QTD in the QTD list */ +- DWC_SPINLOCK_IRQSAVE(hcd->lock,&flags); ++ DWC_SPINLOCK(hcd->lock); + DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp, &qh->qtd_list, qtd_list_entry) { + DWC_CIRCLEQ_REMOVE(&qh->qtd_list, qtd, qtd_list_entry); + dwc_otg_hcd_qtd_free(qtd); +@@ -77,7 +76,7 @@ + } + + DWC_FREE(qh); +- DWC_SPINUNLOCK_IRQRESTORE(hcd->lock,flags); ++ DWC_SPINUNLOCK(hcd->lock); + return; + } + diff -Nru linux-3.2.46/debian/patches/rpi/rpi_219_d47734bbc53386d08c6a5a6a5bc4219e881cc778.patch linux-3.2.46/debian/patches/rpi/rpi_219_d47734bbc53386d08c6a5a6a5bc4219e881cc778.patch --- linux-3.2.46/debian/patches/rpi/rpi_219_d47734bbc53386d08c6a5a6a5bc4219e881cc778.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_219_d47734bbc53386d08c6a5a6a5bc4219e881cc778.patch 2013-07-26 19:35:37.000000000 +0000 @@ -0,0 +1,734 @@ +commit d47734bbc53386d08c6a5a6a5bc4219e881cc778 +Author: popcornmix +Date: Tue Aug 21 10:40:36 2012 +0100 + + Regenerate defconfigs for udpated kernel verision + +Index: linux-3.2.46/arch/arm/configs/bcmrpi_cutdown_defconfig +=================================================================== +--- linux-3.2.46.orig/arch/arm/configs/bcmrpi_cutdown_defconfig 2013-07-26 19:33:57.000000000 +0000 ++++ linux-3.2.46/arch/arm/configs/bcmrpi_cutdown_defconfig 2013-07-26 19:35:36.000000000 +0000 +@@ -3,7 +3,6 @@ + # CONFIG_LOCALVERSION_AUTO is not set + CONFIG_SYSVIPC=y + CONFIG_POSIX_MQUEUE=y +-CONFIG_TINY_RCU=y + CONFIG_IKCONFIG=y + CONFIG_IKCONFIG_PROC=y + CONFIG_SCHED_AUTOGROUP=y +@@ -100,12 +99,43 @@ + CONFIG_SCSI_MULTI_LUN=y + # CONFIG_SCSI_LOWLEVEL is not set + CONFIG_NETDEVICES=y ++CONFIG_NETCONSOLE=m + CONFIG_TUN=m + CONFIG_PHYLIB=m + CONFIG_MDIO_BITBANG=m +-CONFIG_NET_ETHERNET=y +-# CONFIG_NETDEV_1000 is not set +-# CONFIG_NETDEV_10000 is not set ++CONFIG_PPP=m ++CONFIG_PPP_BSDCOMP=m ++CONFIG_PPP_DEFLATE=m ++CONFIG_PPP_ASYNC=m ++CONFIG_PPP_SYNC_TTY=m ++CONFIG_SLIP=m ++CONFIG_SLIP_COMPRESSED=y ++CONFIG_USB_CATC=m ++CONFIG_USB_KAWETH=m ++CONFIG_USB_PEGASUS=m ++CONFIG_USB_RTL8150=m ++CONFIG_USB_USBNET=y ++CONFIG_USB_NET_AX8817X=m ++CONFIG_USB_NET_CDCETHER=m ++CONFIG_USB_NET_CDC_EEM=m ++CONFIG_USB_NET_DM9601=m ++CONFIG_USB_NET_SMSC75XX=m ++CONFIG_USB_NET_SMSC95XX=y ++CONFIG_USB_NET_GL620A=m ++CONFIG_USB_NET_NET1080=m ++CONFIG_USB_NET_PLUSB=m ++CONFIG_USB_NET_MCS7830=m ++CONFIG_USB_NET_CDC_SUBSET=m ++CONFIG_USB_ALI_M5632=y ++CONFIG_USB_AN2720=y ++CONFIG_USB_KC2190=y ++# CONFIG_USB_NET_ZAURUS is not set ++CONFIG_USB_NET_CX82310_ETH=m ++CONFIG_USB_NET_KALMIA=m ++CONFIG_USB_NET_INT51X1=m ++CONFIG_USB_IPHETH=m ++CONFIG_USB_SIERRA_NET=m ++CONFIG_USB_VL600=m + CONFIG_LIBERTAS_THINFIRM=m + CONFIG_LIBERTAS_THINFIRM_USB=m + CONFIG_AT76C50X_USB=m +@@ -138,40 +168,6 @@ + CONFIG_MWIFIEX=m + CONFIG_MWIFIEX_SDIO=m + CONFIG_WIMAX_I2400M_USB=m +-CONFIG_USB_CATC=m +-CONFIG_USB_KAWETH=m +-CONFIG_USB_PEGASUS=m +-CONFIG_USB_RTL8150=m +-CONFIG_USB_USBNET=y +-CONFIG_USB_NET_AX8817X=m +-CONFIG_USB_NET_CDCETHER=m +-CONFIG_USB_NET_CDC_EEM=m +-CONFIG_USB_NET_DM9601=m +-CONFIG_USB_NET_SMSC75XX=m +-CONFIG_USB_NET_SMSC95XX=y +-CONFIG_USB_NET_GL620A=m +-CONFIG_USB_NET_NET1080=m +-CONFIG_USB_NET_PLUSB=m +-CONFIG_USB_NET_MCS7830=m +-CONFIG_USB_NET_CDC_SUBSET=m +-CONFIG_USB_ALI_M5632=y +-CONFIG_USB_AN2720=y +-CONFIG_USB_KC2190=y +-# CONFIG_USB_NET_ZAURUS is not set +-CONFIG_USB_NET_CX82310_ETH=m +-CONFIG_USB_NET_KALMIA=m +-CONFIG_USB_NET_INT51X1=m +-CONFIG_USB_IPHETH=m +-CONFIG_USB_SIERRA_NET=m +-CONFIG_USB_VL600=m +-CONFIG_PPP=m +-CONFIG_PPP_ASYNC=m +-CONFIG_PPP_SYNC_TTY=m +-CONFIG_PPP_DEFLATE=m +-CONFIG_PPP_BSDCOMP=m +-CONFIG_SLIP=m +-CONFIG_SLIP_COMPRESSED=y +-CONFIG_NETCONSOLE=m + CONFIG_INPUT_POLLDEV=m + # CONFIG_INPUT_MOUSEDEV_PSAUX is not set + CONFIG_INPUT_JOYDEV=m +@@ -180,7 +176,6 @@ + # CONFIG_INPUT_MOUSE is not set + CONFIG_INPUT_MISC=y + CONFIG_INPUT_AD714X=m +-CONFIG_INPUT_ATI_REMOTE=m + CONFIG_INPUT_ATI_REMOTE2=m + CONFIG_INPUT_KEYSPAN_REMOTE=m + CONFIG_INPUT_POWERMATE=m +@@ -206,7 +201,6 @@ + # CONFIG_HWMON is not set + CONFIG_WATCHDOG=y + CONFIG_BCM2708_WDT=m +-# CONFIG_MFD_SUPPORT is not set + CONFIG_MEDIA_SUPPORT=m + CONFIG_VIDEO_DEV=m + CONFIG_USB_VIDEO_CLASS=m +Index: linux-3.2.46/arch/arm/configs/bcmrpi_defconfig +=================================================================== +--- linux-3.2.46.orig/arch/arm/configs/bcmrpi_defconfig 2013-07-26 19:34:37.000000000 +0000 ++++ linux-3.2.46/arch/arm/configs/bcmrpi_defconfig 2013-07-26 19:35:36.000000000 +0000 +@@ -1,46 +1,30 @@ + CONFIG_EXPERIMENTAL=y ++CONFIG_LOCALVERSION="-cutdown" + # CONFIG_LOCALVERSION_AUTO is not set + CONFIG_SYSVIPC=y + CONFIG_POSIX_MQUEUE=y +-CONFIG_BSD_PROCESS_ACCT=y +-CONFIG_BSD_PROCESS_ACCT_V3=y +-CONFIG_FHANDLE=y +-CONFIG_AUDIT=y +-CONFIG_TINY_RCU=y + CONFIG_IKCONFIG=y + CONFIG_IKCONFIG_PROC=y +-CONFIG_CGROUP_FREEZER=y +-CONFIG_CGROUP_DEVICE=y +-CONFIG_CGROUP_CPUACCT=y +-CONFIG_RESOURCE_COUNTERS=y +-CONFIG_BLK_CGROUP=y +-CONFIG_NAMESPACES=y + CONFIG_SCHED_AUTOGROUP=y ++# CONFIG_UID16 is not set ++# CONFIG_KALLSYMS is not set + CONFIG_EMBEDDED=y ++# CONFIG_VM_EVENT_COUNTERS is not set + # CONFIG_COMPAT_BRK is not set + CONFIG_SLAB=y +-CONFIG_PROFILING=y +-CONFIG_OPROFILE=m +-CONFIG_KPROBES=y + CONFIG_MODULES=y + CONFIG_MODULE_UNLOAD=y + CONFIG_MODVERSIONS=y + CONFIG_MODULE_SRCVERSION_ALL=y + # CONFIG_BLK_DEV_BSG is not set +-CONFIG_BLK_DEV_THROTTLING=y +-CONFIG_CFQ_GROUP_IOSCHED=y + CONFIG_ARCH_BCM2708=y + CONFIG_NO_HZ=y + CONFIG_HIGH_RES_TIMERS=y + CONFIG_PREEMPT=y + CONFIG_AEABI=y +-CONFIG_UACCESS_WITH_MEMCPY=y +-CONFIG_SECCOMP=y +-CONFIG_CC_STACKPROTECTOR=y + CONFIG_ZBOOT_ROM_TEXT=0x0 + CONFIG_ZBOOT_ROM_BSS=0x0 + CONFIG_CMDLINE="dwc_otg.lpm_enable=0 console=ttyAMA0,115200 kgdboc=ttyAMA0,115200 root=/dev/mmcblk0p2 rootfstype=ext3 rootwait" +-CONFIG_KEXEC=y + CONFIG_CPU_IDLE=y + CONFIG_VFP=y + CONFIG_BINFMT_MISC=m +@@ -51,226 +35,19 @@ + CONFIG_NET_KEY=m + CONFIG_INET=y + CONFIG_IP_MULTICAST=y +-CONFIG_IP_ADVANCED_ROUTER=y +-CONFIG_IP_MULTIPLE_TABLES=y +-CONFIG_IP_ROUTE_MULTIPATH=y +-CONFIG_IP_ROUTE_VERBOSE=y + CONFIG_IP_PNP=y + CONFIG_IP_PNP_DHCP=y + CONFIG_IP_PNP_RARP=y +-CONFIG_NET_IPIP=m + CONFIG_SYN_COOKIES=y + # CONFIG_INET_XFRM_MODE_TRANSPORT is not set + # CONFIG_INET_XFRM_MODE_TUNNEL is not set + # CONFIG_INET_XFRM_MODE_BEET is not set ++# CONFIG_INET_LRO is not set + # CONFIG_INET_DIAG is not set + CONFIG_IPV6_PRIVACY=y +-CONFIG_NETFILTER=y +-CONFIG_NF_CONNTRACK=m +-CONFIG_NF_CONNTRACK_ZONES=y +-CONFIG_NF_CONNTRACK_EVENTS=y +-CONFIG_NF_CONNTRACK_TIMESTAMP=y +-CONFIG_NF_CT_PROTO_DCCP=m +-CONFIG_NF_CT_PROTO_SCTP=m +-CONFIG_NF_CT_PROTO_UDPLITE=m +-CONFIG_NF_CONNTRACK_AMANDA=m +-CONFIG_NF_CONNTRACK_FTP=m +-CONFIG_NF_CONNTRACK_H323=m +-CONFIG_NF_CONNTRACK_IRC=m +-CONFIG_NF_CONNTRACK_NETBIOS_NS=m +-CONFIG_NF_CONNTRACK_SNMP=m +-CONFIG_NF_CONNTRACK_PPTP=m +-CONFIG_NF_CONNTRACK_SANE=m +-CONFIG_NF_CONNTRACK_SIP=m +-CONFIG_NF_CONNTRACK_TFTP=m +-CONFIG_NF_CT_NETLINK=m +-CONFIG_NETFILTER_TPROXY=m +-CONFIG_NETFILTER_XT_SET=m +-CONFIG_NETFILTER_XT_TARGET_AUDIT=m +-CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m +-CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m +-CONFIG_NETFILTER_XT_TARGET_CONNMARK=m +-CONFIG_NETFILTER_XT_TARGET_CT=m +-CONFIG_NETFILTER_XT_TARGET_DSCP=m +-CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m +-CONFIG_NETFILTER_XT_TARGET_LED=m +-CONFIG_NETFILTER_XT_TARGET_MARK=m +-CONFIG_NETFILTER_XT_TARGET_NFLOG=m +-CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m +-CONFIG_NETFILTER_XT_TARGET_NOTRACK=m +-CONFIG_NETFILTER_XT_TARGET_TEE=m +-CONFIG_NETFILTER_XT_TARGET_TPROXY=m +-CONFIG_NETFILTER_XT_TARGET_TRACE=m +-CONFIG_NETFILTER_XT_TARGET_TCPMSS=m +-CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m +-CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m +-CONFIG_NETFILTER_XT_MATCH_CLUSTER=m +-CONFIG_NETFILTER_XT_MATCH_COMMENT=m +-CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m +-CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m +-CONFIG_NETFILTER_XT_MATCH_CONNMARK=m +-CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m +-CONFIG_NETFILTER_XT_MATCH_CPU=m +-CONFIG_NETFILTER_XT_MATCH_DCCP=m +-CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m +-CONFIG_NETFILTER_XT_MATCH_DSCP=m +-CONFIG_NETFILTER_XT_MATCH_ESP=m +-CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m +-CONFIG_NETFILTER_XT_MATCH_HELPER=m +-CONFIG_NETFILTER_XT_MATCH_IPRANGE=m +-CONFIG_NETFILTER_XT_MATCH_LENGTH=m +-CONFIG_NETFILTER_XT_MATCH_LIMIT=m +-CONFIG_NETFILTER_XT_MATCH_MAC=m +-CONFIG_NETFILTER_XT_MATCH_MARK=m +-CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m +-CONFIG_NETFILTER_XT_MATCH_OSF=m +-CONFIG_NETFILTER_XT_MATCH_OWNER=m +-CONFIG_NETFILTER_XT_MATCH_POLICY=m +-CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m +-CONFIG_NETFILTER_XT_MATCH_QUOTA=m +-CONFIG_NETFILTER_XT_MATCH_RATEEST=m +-CONFIG_NETFILTER_XT_MATCH_REALM=m +-CONFIG_NETFILTER_XT_MATCH_RECENT=m +-CONFIG_NETFILTER_XT_MATCH_SCTP=m +-CONFIG_NETFILTER_XT_MATCH_SOCKET=m +-CONFIG_NETFILTER_XT_MATCH_STATE=m +-CONFIG_NETFILTER_XT_MATCH_STATISTIC=m +-CONFIG_NETFILTER_XT_MATCH_STRING=m +-CONFIG_NETFILTER_XT_MATCH_TCPMSS=m +-CONFIG_NETFILTER_XT_MATCH_TIME=m +-CONFIG_NETFILTER_XT_MATCH_U32=m +-CONFIG_IP_SET=m +-CONFIG_IP_SET_BITMAP_IP=m +-CONFIG_IP_SET_BITMAP_IPMAC=m +-CONFIG_IP_SET_BITMAP_PORT=m +-CONFIG_IP_SET_HASH_IP=m +-CONFIG_IP_SET_HASH_IPPORT=m +-CONFIG_IP_SET_HASH_IPPORTIP=m +-CONFIG_IP_SET_HASH_IPPORTNET=m +-CONFIG_IP_SET_HASH_NET=m +-CONFIG_IP_SET_HASH_NETPORT=m +-CONFIG_IP_SET_HASH_NETIFACE=m +-CONFIG_IP_SET_LIST_SET=m +-CONFIG_NF_CONNTRACK_IPV4=m +-CONFIG_IP_NF_IPTABLES=m +-CONFIG_IP_NF_MATCH_AH=m +-CONFIG_IP_NF_MATCH_ECN=m +-CONFIG_IP_NF_MATCH_TTL=m +-CONFIG_IP_NF_FILTER=m +-CONFIG_IP_NF_TARGET_REJECT=m +-CONFIG_IP_NF_TARGET_LOG=m +-CONFIG_IP_NF_TARGET_ULOG=m +-CONFIG_NF_NAT=m +-CONFIG_IP_NF_TARGET_MASQUERADE=m +-CONFIG_IP_NF_TARGET_NETMAP=m +-CONFIG_IP_NF_TARGET_REDIRECT=m +-CONFIG_IP_NF_MANGLE=m +-CONFIG_IP_NF_TARGET_ECN=m +-CONFIG_IP_NF_TARGET_TTL=m +-CONFIG_IP_NF_RAW=m +-CONFIG_IP_NF_ARPTABLES=m +-CONFIG_IP_NF_ARPFILTER=m +-CONFIG_IP_NF_ARP_MANGLE=m +-CONFIG_NF_CONNTRACK_IPV6=m +-CONFIG_IP6_NF_IPTABLES=m +-CONFIG_IP6_NF_MATCH_AH=m +-CONFIG_IP6_NF_MATCH_EUI64=m +-CONFIG_IP6_NF_MATCH_FRAG=m +-CONFIG_IP6_NF_MATCH_OPTS=m +-CONFIG_IP6_NF_MATCH_HL=m +-CONFIG_IP6_NF_MATCH_IPV6HEADER=m +-CONFIG_IP6_NF_MATCH_MH=m +-CONFIG_IP6_NF_MATCH_RT=m +-CONFIG_IP6_NF_TARGET_HL=m +-CONFIG_IP6_NF_TARGET_LOG=m +-CONFIG_IP6_NF_FILTER=m +-CONFIG_IP6_NF_TARGET_REJECT=m +-CONFIG_IP6_NF_MANGLE=m +-CONFIG_IP6_NF_RAW=m +-CONFIG_BRIDGE_NF_EBTABLES=m +-CONFIG_BRIDGE_EBT_BROUTE=m +-CONFIG_BRIDGE_EBT_T_FILTER=m +-CONFIG_BRIDGE_EBT_T_NAT=m +-CONFIG_BRIDGE_EBT_802_3=m +-CONFIG_BRIDGE_EBT_AMONG=m +-CONFIG_BRIDGE_EBT_ARP=m +-CONFIG_BRIDGE_EBT_IP=m +-CONFIG_BRIDGE_EBT_IP6=m +-CONFIG_BRIDGE_EBT_LIMIT=m +-CONFIG_BRIDGE_EBT_MARK=m +-CONFIG_BRIDGE_EBT_PKTTYPE=m +-CONFIG_BRIDGE_EBT_STP=m +-CONFIG_BRIDGE_EBT_VLAN=m +-CONFIG_BRIDGE_EBT_ARPREPLY=m +-CONFIG_BRIDGE_EBT_DNAT=m +-CONFIG_BRIDGE_EBT_MARK_T=m +-CONFIG_BRIDGE_EBT_REDIRECT=m +-CONFIG_BRIDGE_EBT_SNAT=m +-CONFIG_BRIDGE_EBT_LOG=m +-CONFIG_BRIDGE_EBT_ULOG=m +-CONFIG_BRIDGE_EBT_NFLOG=m +-CONFIG_BRIDGE=m +-CONFIG_VLAN_8021Q=m +-CONFIG_VLAN_8021Q_GVRP=y +-CONFIG_NET_SCHED=y +-CONFIG_NET_SCH_CBQ=m +-CONFIG_NET_SCH_HTB=m +-CONFIG_NET_SCH_HFSC=m +-CONFIG_NET_SCH_PRIO=m +-CONFIG_NET_SCH_MULTIQ=m +-CONFIG_NET_SCH_RED=m +-CONFIG_NET_SCH_SFB=m +-CONFIG_NET_SCH_SFQ=m +-CONFIG_NET_SCH_TEQL=m +-CONFIG_NET_SCH_TBF=m +-CONFIG_NET_SCH_GRED=m +-CONFIG_NET_SCH_DSMARK=m +-CONFIG_NET_SCH_NETEM=m +-CONFIG_NET_SCH_DRR=m +-CONFIG_NET_SCH_MQPRIO=m +-CONFIG_NET_SCH_CHOKE=m +-CONFIG_NET_SCH_QFQ=m +-CONFIG_NET_CLS_BASIC=m +-CONFIG_NET_CLS_TCINDEX=m +-CONFIG_NET_CLS_ROUTE4=m +-CONFIG_NET_CLS_FW=m +-CONFIG_NET_CLS_U32=m +-CONFIG_CLS_U32_MARK=y +-CONFIG_NET_CLS_RSVP=m +-CONFIG_NET_CLS_RSVP6=m +-CONFIG_NET_CLS_FLOW=m +-CONFIG_NET_CLS_CGROUP=m +-CONFIG_NET_EMATCH=y +-CONFIG_NET_EMATCH_CMP=m +-CONFIG_NET_EMATCH_NBYTE=m +-CONFIG_NET_EMATCH_U32=m +-CONFIG_NET_EMATCH_META=m +-CONFIG_NET_EMATCH_TEXT=m +-CONFIG_NET_CLS_ACT=y +-CONFIG_NET_ACT_POLICE=m +-CONFIG_NET_ACT_GACT=m +-CONFIG_GACT_PROB=y +-CONFIG_NET_ACT_MIRRED=m +-CONFIG_NET_ACT_IPT=m +-CONFIG_NET_ACT_NAT=m +-CONFIG_NET_ACT_PEDIT=m +-CONFIG_NET_ACT_SIMP=m +-CONFIG_NET_ACT_SKBEDIT=m +-CONFIG_NET_ACT_CSUM=m + CONFIG_NET_PKTGEN=m +-CONFIG_HAMRADIO=y +-CONFIG_AX25=m +-CONFIG_NETROM=m +-CONFIG_ROSE=m +-CONFIG_MKISS=m +-CONFIG_6PACK=m +-CONFIG_BPQETHER=m +-CONFIG_BAYCOM_SER_FDX=m +-CONFIG_BAYCOM_SER_HDX=m +-CONFIG_YAM=m + CONFIG_IRDA=m + CONFIG_IRLAN=m +-CONFIG_IRNET=m + CONFIG_IRCOMM=m + CONFIG_IRDA_ULTRA=y + CONFIG_IRDA_CACHE_LAST_LSAP=y +@@ -308,6 +85,7 @@ + CONFIG_NFC=m + CONFIG_NFC_PN533=m + CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y + CONFIG_BLK_DEV_LOOP=y + CONFIG_BLK_DEV_CRYPTOLOOP=m + CONFIG_BLK_DEV_NBD=m +@@ -317,29 +95,47 @@ + CONFIG_SCSI=y + # CONFIG_SCSI_PROC_FS is not set + CONFIG_BLK_DEV_SD=y +-CONFIG_CHR_DEV_ST=m +-CONFIG_CHR_DEV_OSST=m + CONFIG_BLK_DEV_SR=m + CONFIG_SCSI_MULTI_LUN=y + # CONFIG_SCSI_LOWLEVEL is not set +-CONFIG_MD=y +-CONFIG_BLK_DEV_DM=m +-CONFIG_DM_CRYPT=m +-CONFIG_DM_SNAPSHOT=m +-CONFIG_DM_MIRROR=m +-CONFIG_DM_RAID=m +-CONFIG_DM_LOG_USERSPACE=m +-CONFIG_DM_ZERO=m +-CONFIG_DM_DELAY=m + CONFIG_NETDEVICES=y +-CONFIG_BONDING=m +-CONFIG_MACVLAN=m ++CONFIG_NETCONSOLE=m + CONFIG_TUN=m + CONFIG_PHYLIB=m + CONFIG_MDIO_BITBANG=m +-CONFIG_NET_ETHERNET=y +-# CONFIG_NETDEV_1000 is not set +-# CONFIG_NETDEV_10000 is not set ++CONFIG_PPP=m ++CONFIG_PPP_BSDCOMP=m ++CONFIG_PPP_DEFLATE=m ++CONFIG_PPP_ASYNC=m ++CONFIG_PPP_SYNC_TTY=m ++CONFIG_SLIP=m ++CONFIG_SLIP_COMPRESSED=y ++CONFIG_USB_CATC=m ++CONFIG_USB_KAWETH=m ++CONFIG_USB_PEGASUS=m ++CONFIG_USB_RTL8150=m ++CONFIG_USB_USBNET=y ++CONFIG_USB_NET_AX8817X=m ++CONFIG_USB_NET_CDCETHER=m ++CONFIG_USB_NET_CDC_EEM=m ++CONFIG_USB_NET_DM9601=m ++CONFIG_USB_NET_SMSC75XX=m ++CONFIG_USB_NET_SMSC95XX=y ++CONFIG_USB_NET_GL620A=m ++CONFIG_USB_NET_NET1080=m ++CONFIG_USB_NET_PLUSB=m ++CONFIG_USB_NET_MCS7830=m ++CONFIG_USB_NET_CDC_SUBSET=m ++CONFIG_USB_ALI_M5632=y ++CONFIG_USB_AN2720=y ++CONFIG_USB_KC2190=y ++# CONFIG_USB_NET_ZAURUS is not set ++CONFIG_USB_NET_CX82310_ETH=m ++CONFIG_USB_NET_KALMIA=m ++CONFIG_USB_NET_INT51X1=m ++CONFIG_USB_IPHETH=m ++CONFIG_USB_SIERRA_NET=m ++CONFIG_USB_VL600=m + CONFIG_LIBERTAS_THINFIRM=m + CONFIG_LIBERTAS_THINFIRM_USB=m + CONFIG_AT76C50X_USB=m +@@ -352,7 +148,6 @@ + CONFIG_ATH9K_HTC=m + CONFIG_CARL9170=m + CONFIG_B43=m +-CONFIG_B43_PHY_N=y + CONFIG_B43LEGACY=m + CONFIG_HOSTAP=m + CONFIG_IWM=m +@@ -373,45 +168,6 @@ + CONFIG_MWIFIEX=m + CONFIG_MWIFIEX_SDIO=m + CONFIG_WIMAX_I2400M_USB=m +-CONFIG_USB_CATC=m +-CONFIG_USB_KAWETH=m +-CONFIG_USB_PEGASUS=m +-CONFIG_USB_RTL8150=m +-CONFIG_USB_USBNET=y +-CONFIG_USB_NET_AX8817X=m +-CONFIG_USB_NET_CDCETHER=m +-CONFIG_USB_NET_CDC_EEM=m +-CONFIG_USB_NET_DM9601=m +-CONFIG_USB_NET_SMSC75XX=m +-CONFIG_USB_NET_SMSC95XX=y +-CONFIG_USB_NET_GL620A=m +-CONFIG_USB_NET_NET1080=m +-CONFIG_USB_NET_PLUSB=m +-CONFIG_USB_NET_MCS7830=m +-CONFIG_USB_NET_CDC_SUBSET=m +-CONFIG_USB_ALI_M5632=y +-CONFIG_USB_AN2720=y +-CONFIG_USB_KC2190=y +-# CONFIG_USB_NET_ZAURUS is not set +-CONFIG_USB_NET_CX82310_ETH=m +-CONFIG_USB_NET_KALMIA=m +-CONFIG_USB_NET_INT51X1=m +-CONFIG_USB_IPHETH=m +-CONFIG_USB_SIERRA_NET=m +-CONFIG_USB_VL600=m +-CONFIG_PPP=m +-CONFIG_PPP_MULTILINK=y +-CONFIG_PPP_FILTER=y +-CONFIG_PPP_ASYNC=m +-CONFIG_PPP_SYNC_TTY=m +-CONFIG_PPP_DEFLATE=m +-CONFIG_PPP_BSDCOMP=m +-CONFIG_PPP_MPPE=m +-CONFIG_PPPOE=m +-CONFIG_SLIP=m +-CONFIG_SLIP_COMPRESSED=y +-CONFIG_SLIP_SMART=y +-CONFIG_NETCONSOLE=m + CONFIG_INPUT_POLLDEV=m + # CONFIG_INPUT_MOUSEDEV_PSAUX is not set + CONFIG_INPUT_JOYDEV=m +@@ -420,7 +176,6 @@ + # CONFIG_INPUT_MOUSE is not set + CONFIG_INPUT_MISC=y + CONFIG_INPUT_AD714X=m +-CONFIG_INPUT_ATI_REMOTE=m + CONFIG_INPUT_ATI_REMOTE2=m + CONFIG_INPUT_KEYSPAN_REMOTE=m + CONFIG_INPUT_POWERMATE=m +@@ -440,38 +195,14 @@ + # CONFIG_DEVKMEM is not set + CONFIG_SERIAL_AMBA_PL011=y + CONFIG_SERIAL_AMBA_PL011_CONSOLE=y +-CONFIG_TTY_PRINTK=y + # CONFIG_HW_RANDOM is not set + CONFIG_RAW_DRIVER=y +-CONFIG_I2C=y +-CONFIG_I2C_CHARDEV=m +-CONFIG_I2C_BCM2708=m +-CONFIG_SPI=y +-CONFIG_SPI_BCM2708=m +-CONFIG_SPI_SPIDEV=m + CONFIG_GPIO_SYSFS=y +-CONFIG_W1=m +-CONFIG_W1_MASTER_DS2490=m +-CONFIG_W1_MASTER_DS2482=m +-CONFIG_W1_MASTER_DS1WM=m +-CONFIG_W1_MASTER_GPIO=m +-CONFIG_W1_SLAVE_THERM=m +-CONFIG_W1_SLAVE_SMEM=m +-CONFIG_W1_SLAVE_DS2408=m +-CONFIG_W1_SLAVE_DS2423=m +-CONFIG_W1_SLAVE_DS2431=m +-CONFIG_W1_SLAVE_DS2433=m +-CONFIG_W1_SLAVE_DS2760=m +-CONFIG_W1_SLAVE_DS2780=m +-CONFIG_W1_SLAVE_BQ27000=m + # CONFIG_HWMON is not set + CONFIG_WATCHDOG=y + CONFIG_BCM2708_WDT=m +-# CONFIG_MFD_SUPPORT is not set + CONFIG_MEDIA_SUPPORT=m + CONFIG_VIDEO_DEV=m +-CONFIG_DVB_CORE=m +-CONFIG_MEDIA_ATTACH=y + CONFIG_USB_VIDEO_CLASS=m + CONFIG_USB_M5602=m + CONFIG_USB_STV06XX=m +@@ -517,61 +248,11 @@ + CONFIG_USB_GSPCA_VICAM=m + CONFIG_USB_GSPCA_XIRLINK_CIT=m + CONFIG_USB_GSPCA_ZC3XX=m +-CONFIG_VIDEO_PVRUSB2=m + CONFIG_VIDEO_HDPVR=m +-CONFIG_VIDEO_EM28XX=m +-CONFIG_VIDEO_EM28XX_ALSA=m +-CONFIG_VIDEO_EM28XX_DVB=m +-CONFIG_VIDEO_TLG2300=m +-CONFIG_VIDEO_CX231XX=m +-CONFIG_VIDEO_CX231XX_ALSA=m +-CONFIG_VIDEO_CX231XX_DVB=m +-CONFIG_VIDEO_USBVISION=m +-CONFIG_USB_ET61X251=m +-CONFIG_USB_SN9C102=m + CONFIG_USB_PWC=m + CONFIG_USB_ZR364XX=m + CONFIG_USB_STKWEBCAM=m + CONFIG_USB_S2255=m +-CONFIG_USB_DSBR=m +-CONFIG_RADIO_SI470X=y +-CONFIG_USB_SI470X=m +-CONFIG_USB_MR800=m +-CONFIG_DVB_USB=m +-CONFIG_DVB_USB_A800=m +-CONFIG_DVB_USB_DIBUSB_MB=m +-CONFIG_DVB_USB_DIBUSB_MC=m +-CONFIG_DVB_USB_DIB0700=m +-CONFIG_DVB_USB_UMT_010=m +-CONFIG_DVB_USB_CXUSB=m +-CONFIG_DVB_USB_M920X=m +-CONFIG_DVB_USB_GL861=m +-CONFIG_DVB_USB_AU6610=m +-CONFIG_DVB_USB_DIGITV=m +-CONFIG_DVB_USB_VP7045=m +-CONFIG_DVB_USB_VP702X=m +-CONFIG_DVB_USB_GP8PSK=m +-CONFIG_DVB_USB_NOVA_T_USB2=m +-CONFIG_DVB_USB_TTUSB2=m +-CONFIG_DVB_USB_DTT200U=m +-CONFIG_DVB_USB_OPERA1=m +-CONFIG_DVB_USB_AF9005=m +-CONFIG_DVB_USB_AF9005_REMOTE=m +-CONFIG_DVB_USB_DW2102=m +-CONFIG_DVB_USB_CINERGY_T2=m +-CONFIG_DVB_USB_ANYSEE=m +-CONFIG_DVB_USB_DTV5100=m +-CONFIG_DVB_USB_AF9015=m +-CONFIG_DVB_USB_CE6230=m +-CONFIG_DVB_USB_FRIIO=m +-CONFIG_DVB_USB_EC168=m +-CONFIG_DVB_USB_AZ6027=m +-CONFIG_DVB_USB_LME2510=m +-CONFIG_DVB_USB_TECHNISAT_USB2=m +-CONFIG_SMS_SIANO_MDTV=m +-CONFIG_SMS_USB_DRV=m +-CONFIG_DVB_B2C2_FLEXCOP=m +-CONFIG_DVB_B2C2_FLEXCOP_USB=m + CONFIG_FB=y + CONFIG_FB_BCM2708=y + CONFIG_FRAMEBUFFER_CONSOLE=y +@@ -747,12 +428,6 @@ + CONFIG_UIO=m + CONFIG_UIO_PDRV=m + CONFIG_UIO_PDRV_GENIRQ=m +-CONFIG_STAGING=y +-CONFIG_W35UND=m +-CONFIG_PRISM2_USB=m +-CONFIG_R8712U=m +-CONFIG_R8712_AP=y +-CONFIG_ZRAM=m + # CONFIG_IOMMU_SUPPORT is not set + CONFIG_EXT4_FS=y + CONFIG_EXT4_FS_POSIX_ACL=y +@@ -764,7 +439,6 @@ + CONFIG_JFS_FS=m + CONFIG_JFS_POSIX_ACL=y + CONFIG_JFS_SECURITY=y +-CONFIG_JFS_STATISTICS=y + CONFIG_XFS_FS=m + CONFIG_XFS_QUOTA=y + CONFIG_XFS_POSIX_ACL=y +@@ -774,13 +448,10 @@ + CONFIG_BTRFS_FS=m + CONFIG_BTRFS_FS_POSIX_ACL=y + CONFIG_NILFS2_FS=m +-CONFIG_FANOTIFY=y + CONFIG_AUTOFS4_FS=y + CONFIG_FUSE_FS=m + CONFIG_CUSE=m + CONFIG_FSCACHE=y +-CONFIG_FSCACHE_STATS=y +-CONFIG_FSCACHE_HISTOGRAM=y + CONFIG_CACHEFILES=y + CONFIG_ISO9660_FS=m + CONFIG_JOLIET=y +@@ -793,9 +464,6 @@ + CONFIG_TMPFS=y + CONFIG_TMPFS_POSIX_ACL=y + CONFIG_CONFIGFS_FS=y +-CONFIG_ECRYPT_FS=m +-CONFIG_HFS_FS=m +-CONFIG_HFSPLUS_FS=m + CONFIG_SQUASHFS=m + CONFIG_SQUASHFS_XATTR=y + CONFIG_SQUASHFS_LZO=y +@@ -806,13 +474,11 @@ + CONFIG_NFS_V4=y + CONFIG_ROOT_NFS=y + CONFIG_NFS_FSCACHE=y +-CONFIG_NFSD=m + CONFIG_CIFS=m + CONFIG_CIFS_WEAK_PW_HASH=y + CONFIG_CIFS_XATTR=y + CONFIG_CIFS_POSIX=y + CONFIG_9P_FS=m +-CONFIG_9P_FS_POSIX_ACL=y + CONFIG_PARTITION_ADVANCED=y + CONFIG_MAC_PARTITION=y + CONFIG_EFI_PARTITION=y +@@ -854,29 +520,15 @@ + CONFIG_NLS_ISO8859_15=m + CONFIG_NLS_KOI8_R=m + CONFIG_NLS_KOI8_U=m +-CONFIG_PRINTK_TIME=y +-CONFIG_DETECT_HUNG_TASK=y +-CONFIG_TIMER_STATS=y ++CONFIG_NLS_UTF8=m ++# CONFIG_SCHED_DEBUG is not set + # CONFIG_DEBUG_PREEMPT is not set +-CONFIG_DEBUG_MEMORY_INIT=y +-CONFIG_BOOT_PRINTK_DELAY=y +-CONFIG_LATENCYTOP=y +-CONFIG_SYSCTL_SYSCALL_CHECK=y +-# CONFIG_EVENT_POWER_TRACING_DEPRECATED is not set +-CONFIG_IRQSOFF_TRACER=y +-CONFIG_PREEMPT_TRACER=y +-CONFIG_SCHED_TRACER=y +-CONFIG_STACK_TRACER=y +-CONFIG_BLK_DEV_IO_TRACE=y +-CONFIG_FUNCTION_PROFILER=y +-CONFIG_KGDB=y +-CONFIG_KGDB_KDB=y +-CONFIG_KDB_KEYBOARD=y +-CONFIG_STRICT_DEVMEM=y ++# CONFIG_DEBUG_BUGVERBOSE is not set ++# CONFIG_FTRACE is not set ++# CONFIG_ARM_UNWIND is not set + CONFIG_CRYPTO_AUTHENC=m + CONFIG_CRYPTO_SEQIV=m + CONFIG_CRYPTO_CBC=y +-CONFIG_CRYPTO_XTS=m + CONFIG_CRYPTO_HMAC=y + CONFIG_CRYPTO_XCBC=m + CONFIG_CRYPTO_MD5=y diff -Nru linux-3.2.46/debian/patches/rpi/rpi_220_cbc60c791cb6fafea5ddae0d8429ac0923237128.patch linux-3.2.46/debian/patches/rpi/rpi_220_cbc60c791cb6fafea5ddae0d8429ac0923237128.patch --- linux-3.2.46/debian/patches/rpi/rpi_220_cbc60c791cb6fafea5ddae0d8429ac0923237128.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_220_cbc60c791cb6fafea5ddae0d8429ac0923237128.patch 2013-07-26 19:35:39.000000000 +0000 @@ -0,0 +1,32 @@ +commit cbc60c791cb6fafea5ddae0d8429ac0923237128 +Author: popcornmix +Date: Tue Aug 21 12:25:47 2012 +0100 + + Another fix for 10 second hang on closing sound driver + +Index: linux-3.2.46/sound/arm/bcm2835-pcm.c +=================================================================== +--- linux-3.2.46.orig/sound/arm/bcm2835-pcm.c 2013-07-26 19:34:33.000000000 +0000 ++++ linux-3.2.46/sound/arm/bcm2835-pcm.c 2013-07-26 19:35:38.000000000 +0000 +@@ -72,7 +72,7 @@ + frames_to_bytes(alsa_stream->substream->runtime, alsa_stream->substream->runtime->status->hw_ptr), + new_period); + if (alsa_stream->buffer_size) { +- alsa_stream->pos += consumed; ++ alsa_stream->pos += consumed &~ (1<<30); + alsa_stream->pos %= alsa_stream->buffer_size; + } + +Index: linux-3.2.46/sound/arm/bcm2835.h +=================================================================== +--- linux-3.2.46.orig/sound/arm/bcm2835.h 2013-07-26 19:34:33.000000000 +0000 ++++ linux-3.2.46/sound/arm/bcm2835.h 2013-07-26 19:35:38.000000000 +0000 +@@ -28,7 +28,7 @@ + /* + #define AUDIO_DEBUG_ENABLE + #define AUDIO_VERBOSE_DEBUG_ENABLE +-*. ++*/ + + /* Debug macros */ + diff -Nru linux-3.2.46/debian/patches/rpi/rpi_221_4a0a5565a02b84d1061bc3dccc5384b4b6829851.patch linux-3.2.46/debian/patches/rpi/rpi_221_4a0a5565a02b84d1061bc3dccc5384b4b6829851.patch --- linux-3.2.46/debian/patches/rpi/rpi_221_4a0a5565a02b84d1061bc3dccc5384b4b6829851.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_221_4a0a5565a02b84d1061bc3dccc5384b4b6829851.patch 2013-07-26 19:35:40.000000000 +0000 @@ -0,0 +1,38 @@ +commit 4a0a5565a02b84d1061bc3dccc5384b4b6829851 +Author: Simon Arlott +Date: Sat Jun 9 16:48:15 2012 +0100 + + amba-pl011: Don't send a character during startup + + This causes a corrupted character to be sent and + there's no explanation for why it is required. + + If it worked correctly it would send an extra 0x00 + which isn't appropriate either. + + Signed-off-by: Simon Arlott + +Index: linux-3.2.46/drivers/tty/serial/amba-pl011.c +=================================================================== +--- linux-3.2.46.orig/drivers/tty/serial/amba-pl011.c 2013-05-30 13:35:16.000000000 +0000 ++++ linux-3.2.46/drivers/tty/serial/amba-pl011.c 2013-07-26 19:35:39.000000000 +0000 +@@ -1394,6 +1394,11 @@ + writew(uap->vendor->ifls, uap->port.membase + UART011_IFLS); + + /* ++ * The write to UART01x_DR causes a corrupted character to be sent ++ * - why is it required? ++ */ ++#if 0 ++ /* + * Provoke TX FIFO interrupt into asserting. + */ + cr = UART01x_CR_UARTEN | UART011_CR_TXE | UART011_CR_LBE; +@@ -1414,6 +1419,7 @@ + writew(0, uap->port.membase + UART01x_DR); + while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_BUSY) + barrier(); ++#endif + + cr = UART01x_CR_UARTEN | UART011_CR_RXE | UART011_CR_TXE; + writew(cr, uap->port.membase + UART011_CR); diff -Nru linux-3.2.46/debian/patches/rpi/rpi_222_b1eebb494f955fe2a772394b17720386460f60ba.patch linux-3.2.46/debian/patches/rpi/rpi_222_b1eebb494f955fe2a772394b17720386460f60ba.patch --- linux-3.2.46/debian/patches/rpi/rpi_222_b1eebb494f955fe2a772394b17720386460f60ba.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_222_b1eebb494f955fe2a772394b17720386460f60ba.patch 2013-07-26 19:35:41.000000000 +0000 @@ -0,0 +1,736 @@ +commit b1eebb494f955fe2a772394b17720386460f60ba +Author: popcornmix +Date: Tue Aug 21 12:45:14 2012 +0100 + + Revert "Regenerate defconfigs for udpated kernel verision" + + This reverts commit d47734bbc53386d08c6a5a6a5bc4219e881cc778. + +Index: linux-3.2.46/arch/arm/configs/bcmrpi_cutdown_defconfig +=================================================================== +--- linux-3.2.46.orig/arch/arm/configs/bcmrpi_cutdown_defconfig 2013-07-26 19:35:36.000000000 +0000 ++++ linux-3.2.46/arch/arm/configs/bcmrpi_cutdown_defconfig 2013-07-26 19:35:40.000000000 +0000 +@@ -3,6 +3,7 @@ + # CONFIG_LOCALVERSION_AUTO is not set + CONFIG_SYSVIPC=y + CONFIG_POSIX_MQUEUE=y ++CONFIG_TINY_RCU=y + CONFIG_IKCONFIG=y + CONFIG_IKCONFIG_PROC=y + CONFIG_SCHED_AUTOGROUP=y +@@ -99,43 +100,12 @@ + CONFIG_SCSI_MULTI_LUN=y + # CONFIG_SCSI_LOWLEVEL is not set + CONFIG_NETDEVICES=y +-CONFIG_NETCONSOLE=m + CONFIG_TUN=m + CONFIG_PHYLIB=m + CONFIG_MDIO_BITBANG=m +-CONFIG_PPP=m +-CONFIG_PPP_BSDCOMP=m +-CONFIG_PPP_DEFLATE=m +-CONFIG_PPP_ASYNC=m +-CONFIG_PPP_SYNC_TTY=m +-CONFIG_SLIP=m +-CONFIG_SLIP_COMPRESSED=y +-CONFIG_USB_CATC=m +-CONFIG_USB_KAWETH=m +-CONFIG_USB_PEGASUS=m +-CONFIG_USB_RTL8150=m +-CONFIG_USB_USBNET=y +-CONFIG_USB_NET_AX8817X=m +-CONFIG_USB_NET_CDCETHER=m +-CONFIG_USB_NET_CDC_EEM=m +-CONFIG_USB_NET_DM9601=m +-CONFIG_USB_NET_SMSC75XX=m +-CONFIG_USB_NET_SMSC95XX=y +-CONFIG_USB_NET_GL620A=m +-CONFIG_USB_NET_NET1080=m +-CONFIG_USB_NET_PLUSB=m +-CONFIG_USB_NET_MCS7830=m +-CONFIG_USB_NET_CDC_SUBSET=m +-CONFIG_USB_ALI_M5632=y +-CONFIG_USB_AN2720=y +-CONFIG_USB_KC2190=y +-# CONFIG_USB_NET_ZAURUS is not set +-CONFIG_USB_NET_CX82310_ETH=m +-CONFIG_USB_NET_KALMIA=m +-CONFIG_USB_NET_INT51X1=m +-CONFIG_USB_IPHETH=m +-CONFIG_USB_SIERRA_NET=m +-CONFIG_USB_VL600=m ++CONFIG_NET_ETHERNET=y ++# CONFIG_NETDEV_1000 is not set ++# CONFIG_NETDEV_10000 is not set + CONFIG_LIBERTAS_THINFIRM=m + CONFIG_LIBERTAS_THINFIRM_USB=m + CONFIG_AT76C50X_USB=m +@@ -168,6 +138,40 @@ + CONFIG_MWIFIEX=m + CONFIG_MWIFIEX_SDIO=m + CONFIG_WIMAX_I2400M_USB=m ++CONFIG_USB_CATC=m ++CONFIG_USB_KAWETH=m ++CONFIG_USB_PEGASUS=m ++CONFIG_USB_RTL8150=m ++CONFIG_USB_USBNET=y ++CONFIG_USB_NET_AX8817X=m ++CONFIG_USB_NET_CDCETHER=m ++CONFIG_USB_NET_CDC_EEM=m ++CONFIG_USB_NET_DM9601=m ++CONFIG_USB_NET_SMSC75XX=m ++CONFIG_USB_NET_SMSC95XX=y ++CONFIG_USB_NET_GL620A=m ++CONFIG_USB_NET_NET1080=m ++CONFIG_USB_NET_PLUSB=m ++CONFIG_USB_NET_MCS7830=m ++CONFIG_USB_NET_CDC_SUBSET=m ++CONFIG_USB_ALI_M5632=y ++CONFIG_USB_AN2720=y ++CONFIG_USB_KC2190=y ++# CONFIG_USB_NET_ZAURUS is not set ++CONFIG_USB_NET_CX82310_ETH=m ++CONFIG_USB_NET_KALMIA=m ++CONFIG_USB_NET_INT51X1=m ++CONFIG_USB_IPHETH=m ++CONFIG_USB_SIERRA_NET=m ++CONFIG_USB_VL600=m ++CONFIG_PPP=m ++CONFIG_PPP_ASYNC=m ++CONFIG_PPP_SYNC_TTY=m ++CONFIG_PPP_DEFLATE=m ++CONFIG_PPP_BSDCOMP=m ++CONFIG_SLIP=m ++CONFIG_SLIP_COMPRESSED=y ++CONFIG_NETCONSOLE=m + CONFIG_INPUT_POLLDEV=m + # CONFIG_INPUT_MOUSEDEV_PSAUX is not set + CONFIG_INPUT_JOYDEV=m +@@ -176,6 +180,7 @@ + # CONFIG_INPUT_MOUSE is not set + CONFIG_INPUT_MISC=y + CONFIG_INPUT_AD714X=m ++CONFIG_INPUT_ATI_REMOTE=m + CONFIG_INPUT_ATI_REMOTE2=m + CONFIG_INPUT_KEYSPAN_REMOTE=m + CONFIG_INPUT_POWERMATE=m +@@ -201,6 +206,7 @@ + # CONFIG_HWMON is not set + CONFIG_WATCHDOG=y + CONFIG_BCM2708_WDT=m ++# CONFIG_MFD_SUPPORT is not set + CONFIG_MEDIA_SUPPORT=m + CONFIG_VIDEO_DEV=m + CONFIG_USB_VIDEO_CLASS=m +Index: linux-3.2.46/arch/arm/configs/bcmrpi_defconfig +=================================================================== +--- linux-3.2.46.orig/arch/arm/configs/bcmrpi_defconfig 2013-07-26 19:35:36.000000000 +0000 ++++ linux-3.2.46/arch/arm/configs/bcmrpi_defconfig 2013-07-26 19:35:40.000000000 +0000 +@@ -1,30 +1,46 @@ + CONFIG_EXPERIMENTAL=y +-CONFIG_LOCALVERSION="-cutdown" + # CONFIG_LOCALVERSION_AUTO is not set + CONFIG_SYSVIPC=y + CONFIG_POSIX_MQUEUE=y ++CONFIG_BSD_PROCESS_ACCT=y ++CONFIG_BSD_PROCESS_ACCT_V3=y ++CONFIG_FHANDLE=y ++CONFIG_AUDIT=y ++CONFIG_TINY_RCU=y + CONFIG_IKCONFIG=y + CONFIG_IKCONFIG_PROC=y ++CONFIG_CGROUP_FREEZER=y ++CONFIG_CGROUP_DEVICE=y ++CONFIG_CGROUP_CPUACCT=y ++CONFIG_RESOURCE_COUNTERS=y ++CONFIG_BLK_CGROUP=y ++CONFIG_NAMESPACES=y + CONFIG_SCHED_AUTOGROUP=y +-# CONFIG_UID16 is not set +-# CONFIG_KALLSYMS is not set + CONFIG_EMBEDDED=y +-# CONFIG_VM_EVENT_COUNTERS is not set + # CONFIG_COMPAT_BRK is not set + CONFIG_SLAB=y ++CONFIG_PROFILING=y ++CONFIG_OPROFILE=m ++CONFIG_KPROBES=y + CONFIG_MODULES=y + CONFIG_MODULE_UNLOAD=y + CONFIG_MODVERSIONS=y + CONFIG_MODULE_SRCVERSION_ALL=y + # CONFIG_BLK_DEV_BSG is not set ++CONFIG_BLK_DEV_THROTTLING=y ++CONFIG_CFQ_GROUP_IOSCHED=y + CONFIG_ARCH_BCM2708=y + CONFIG_NO_HZ=y + CONFIG_HIGH_RES_TIMERS=y + CONFIG_PREEMPT=y + CONFIG_AEABI=y ++CONFIG_UACCESS_WITH_MEMCPY=y ++CONFIG_SECCOMP=y ++CONFIG_CC_STACKPROTECTOR=y + CONFIG_ZBOOT_ROM_TEXT=0x0 + CONFIG_ZBOOT_ROM_BSS=0x0 + CONFIG_CMDLINE="dwc_otg.lpm_enable=0 console=ttyAMA0,115200 kgdboc=ttyAMA0,115200 root=/dev/mmcblk0p2 rootfstype=ext3 rootwait" ++CONFIG_KEXEC=y + CONFIG_CPU_IDLE=y + CONFIG_VFP=y + CONFIG_BINFMT_MISC=m +@@ -35,19 +51,226 @@ + CONFIG_NET_KEY=m + CONFIG_INET=y + CONFIG_IP_MULTICAST=y ++CONFIG_IP_ADVANCED_ROUTER=y ++CONFIG_IP_MULTIPLE_TABLES=y ++CONFIG_IP_ROUTE_MULTIPATH=y ++CONFIG_IP_ROUTE_VERBOSE=y + CONFIG_IP_PNP=y + CONFIG_IP_PNP_DHCP=y + CONFIG_IP_PNP_RARP=y ++CONFIG_NET_IPIP=m + CONFIG_SYN_COOKIES=y + # CONFIG_INET_XFRM_MODE_TRANSPORT is not set + # CONFIG_INET_XFRM_MODE_TUNNEL is not set + # CONFIG_INET_XFRM_MODE_BEET is not set +-# CONFIG_INET_LRO is not set + # CONFIG_INET_DIAG is not set + CONFIG_IPV6_PRIVACY=y ++CONFIG_NETFILTER=y ++CONFIG_NF_CONNTRACK=m ++CONFIG_NF_CONNTRACK_ZONES=y ++CONFIG_NF_CONNTRACK_EVENTS=y ++CONFIG_NF_CONNTRACK_TIMESTAMP=y ++CONFIG_NF_CT_PROTO_DCCP=m ++CONFIG_NF_CT_PROTO_SCTP=m ++CONFIG_NF_CT_PROTO_UDPLITE=m ++CONFIG_NF_CONNTRACK_AMANDA=m ++CONFIG_NF_CONNTRACK_FTP=m ++CONFIG_NF_CONNTRACK_H323=m ++CONFIG_NF_CONNTRACK_IRC=m ++CONFIG_NF_CONNTRACK_NETBIOS_NS=m ++CONFIG_NF_CONNTRACK_SNMP=m ++CONFIG_NF_CONNTRACK_PPTP=m ++CONFIG_NF_CONNTRACK_SANE=m ++CONFIG_NF_CONNTRACK_SIP=m ++CONFIG_NF_CONNTRACK_TFTP=m ++CONFIG_NF_CT_NETLINK=m ++CONFIG_NETFILTER_TPROXY=m ++CONFIG_NETFILTER_XT_SET=m ++CONFIG_NETFILTER_XT_TARGET_AUDIT=m ++CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m ++CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m ++CONFIG_NETFILTER_XT_TARGET_CONNMARK=m ++CONFIG_NETFILTER_XT_TARGET_CT=m ++CONFIG_NETFILTER_XT_TARGET_DSCP=m ++CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m ++CONFIG_NETFILTER_XT_TARGET_LED=m ++CONFIG_NETFILTER_XT_TARGET_MARK=m ++CONFIG_NETFILTER_XT_TARGET_NFLOG=m ++CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m ++CONFIG_NETFILTER_XT_TARGET_NOTRACK=m ++CONFIG_NETFILTER_XT_TARGET_TEE=m ++CONFIG_NETFILTER_XT_TARGET_TPROXY=m ++CONFIG_NETFILTER_XT_TARGET_TRACE=m ++CONFIG_NETFILTER_XT_TARGET_TCPMSS=m ++CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m ++CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m ++CONFIG_NETFILTER_XT_MATCH_CLUSTER=m ++CONFIG_NETFILTER_XT_MATCH_COMMENT=m ++CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m ++CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m ++CONFIG_NETFILTER_XT_MATCH_CONNMARK=m ++CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m ++CONFIG_NETFILTER_XT_MATCH_CPU=m ++CONFIG_NETFILTER_XT_MATCH_DCCP=m ++CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m ++CONFIG_NETFILTER_XT_MATCH_DSCP=m ++CONFIG_NETFILTER_XT_MATCH_ESP=m ++CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m ++CONFIG_NETFILTER_XT_MATCH_HELPER=m ++CONFIG_NETFILTER_XT_MATCH_IPRANGE=m ++CONFIG_NETFILTER_XT_MATCH_LENGTH=m ++CONFIG_NETFILTER_XT_MATCH_LIMIT=m ++CONFIG_NETFILTER_XT_MATCH_MAC=m ++CONFIG_NETFILTER_XT_MATCH_MARK=m ++CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m ++CONFIG_NETFILTER_XT_MATCH_OSF=m ++CONFIG_NETFILTER_XT_MATCH_OWNER=m ++CONFIG_NETFILTER_XT_MATCH_POLICY=m ++CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m ++CONFIG_NETFILTER_XT_MATCH_QUOTA=m ++CONFIG_NETFILTER_XT_MATCH_RATEEST=m ++CONFIG_NETFILTER_XT_MATCH_REALM=m ++CONFIG_NETFILTER_XT_MATCH_RECENT=m ++CONFIG_NETFILTER_XT_MATCH_SCTP=m ++CONFIG_NETFILTER_XT_MATCH_SOCKET=m ++CONFIG_NETFILTER_XT_MATCH_STATE=m ++CONFIG_NETFILTER_XT_MATCH_STATISTIC=m ++CONFIG_NETFILTER_XT_MATCH_STRING=m ++CONFIG_NETFILTER_XT_MATCH_TCPMSS=m ++CONFIG_NETFILTER_XT_MATCH_TIME=m ++CONFIG_NETFILTER_XT_MATCH_U32=m ++CONFIG_IP_SET=m ++CONFIG_IP_SET_BITMAP_IP=m ++CONFIG_IP_SET_BITMAP_IPMAC=m ++CONFIG_IP_SET_BITMAP_PORT=m ++CONFIG_IP_SET_HASH_IP=m ++CONFIG_IP_SET_HASH_IPPORT=m ++CONFIG_IP_SET_HASH_IPPORTIP=m ++CONFIG_IP_SET_HASH_IPPORTNET=m ++CONFIG_IP_SET_HASH_NET=m ++CONFIG_IP_SET_HASH_NETPORT=m ++CONFIG_IP_SET_HASH_NETIFACE=m ++CONFIG_IP_SET_LIST_SET=m ++CONFIG_NF_CONNTRACK_IPV4=m ++CONFIG_IP_NF_IPTABLES=m ++CONFIG_IP_NF_MATCH_AH=m ++CONFIG_IP_NF_MATCH_ECN=m ++CONFIG_IP_NF_MATCH_TTL=m ++CONFIG_IP_NF_FILTER=m ++CONFIG_IP_NF_TARGET_REJECT=m ++CONFIG_IP_NF_TARGET_LOG=m ++CONFIG_IP_NF_TARGET_ULOG=m ++CONFIG_NF_NAT=m ++CONFIG_IP_NF_TARGET_MASQUERADE=m ++CONFIG_IP_NF_TARGET_NETMAP=m ++CONFIG_IP_NF_TARGET_REDIRECT=m ++CONFIG_IP_NF_MANGLE=m ++CONFIG_IP_NF_TARGET_ECN=m ++CONFIG_IP_NF_TARGET_TTL=m ++CONFIG_IP_NF_RAW=m ++CONFIG_IP_NF_ARPTABLES=m ++CONFIG_IP_NF_ARPFILTER=m ++CONFIG_IP_NF_ARP_MANGLE=m ++CONFIG_NF_CONNTRACK_IPV6=m ++CONFIG_IP6_NF_IPTABLES=m ++CONFIG_IP6_NF_MATCH_AH=m ++CONFIG_IP6_NF_MATCH_EUI64=m ++CONFIG_IP6_NF_MATCH_FRAG=m ++CONFIG_IP6_NF_MATCH_OPTS=m ++CONFIG_IP6_NF_MATCH_HL=m ++CONFIG_IP6_NF_MATCH_IPV6HEADER=m ++CONFIG_IP6_NF_MATCH_MH=m ++CONFIG_IP6_NF_MATCH_RT=m ++CONFIG_IP6_NF_TARGET_HL=m ++CONFIG_IP6_NF_TARGET_LOG=m ++CONFIG_IP6_NF_FILTER=m ++CONFIG_IP6_NF_TARGET_REJECT=m ++CONFIG_IP6_NF_MANGLE=m ++CONFIG_IP6_NF_RAW=m ++CONFIG_BRIDGE_NF_EBTABLES=m ++CONFIG_BRIDGE_EBT_BROUTE=m ++CONFIG_BRIDGE_EBT_T_FILTER=m ++CONFIG_BRIDGE_EBT_T_NAT=m ++CONFIG_BRIDGE_EBT_802_3=m ++CONFIG_BRIDGE_EBT_AMONG=m ++CONFIG_BRIDGE_EBT_ARP=m ++CONFIG_BRIDGE_EBT_IP=m ++CONFIG_BRIDGE_EBT_IP6=m ++CONFIG_BRIDGE_EBT_LIMIT=m ++CONFIG_BRIDGE_EBT_MARK=m ++CONFIG_BRIDGE_EBT_PKTTYPE=m ++CONFIG_BRIDGE_EBT_STP=m ++CONFIG_BRIDGE_EBT_VLAN=m ++CONFIG_BRIDGE_EBT_ARPREPLY=m ++CONFIG_BRIDGE_EBT_DNAT=m ++CONFIG_BRIDGE_EBT_MARK_T=m ++CONFIG_BRIDGE_EBT_REDIRECT=m ++CONFIG_BRIDGE_EBT_SNAT=m ++CONFIG_BRIDGE_EBT_LOG=m ++CONFIG_BRIDGE_EBT_ULOG=m ++CONFIG_BRIDGE_EBT_NFLOG=m ++CONFIG_BRIDGE=m ++CONFIG_VLAN_8021Q=m ++CONFIG_VLAN_8021Q_GVRP=y ++CONFIG_NET_SCHED=y ++CONFIG_NET_SCH_CBQ=m ++CONFIG_NET_SCH_HTB=m ++CONFIG_NET_SCH_HFSC=m ++CONFIG_NET_SCH_PRIO=m ++CONFIG_NET_SCH_MULTIQ=m ++CONFIG_NET_SCH_RED=m ++CONFIG_NET_SCH_SFB=m ++CONFIG_NET_SCH_SFQ=m ++CONFIG_NET_SCH_TEQL=m ++CONFIG_NET_SCH_TBF=m ++CONFIG_NET_SCH_GRED=m ++CONFIG_NET_SCH_DSMARK=m ++CONFIG_NET_SCH_NETEM=m ++CONFIG_NET_SCH_DRR=m ++CONFIG_NET_SCH_MQPRIO=m ++CONFIG_NET_SCH_CHOKE=m ++CONFIG_NET_SCH_QFQ=m ++CONFIG_NET_CLS_BASIC=m ++CONFIG_NET_CLS_TCINDEX=m ++CONFIG_NET_CLS_ROUTE4=m ++CONFIG_NET_CLS_FW=m ++CONFIG_NET_CLS_U32=m ++CONFIG_CLS_U32_MARK=y ++CONFIG_NET_CLS_RSVP=m ++CONFIG_NET_CLS_RSVP6=m ++CONFIG_NET_CLS_FLOW=m ++CONFIG_NET_CLS_CGROUP=m ++CONFIG_NET_EMATCH=y ++CONFIG_NET_EMATCH_CMP=m ++CONFIG_NET_EMATCH_NBYTE=m ++CONFIG_NET_EMATCH_U32=m ++CONFIG_NET_EMATCH_META=m ++CONFIG_NET_EMATCH_TEXT=m ++CONFIG_NET_CLS_ACT=y ++CONFIG_NET_ACT_POLICE=m ++CONFIG_NET_ACT_GACT=m ++CONFIG_GACT_PROB=y ++CONFIG_NET_ACT_MIRRED=m ++CONFIG_NET_ACT_IPT=m ++CONFIG_NET_ACT_NAT=m ++CONFIG_NET_ACT_PEDIT=m ++CONFIG_NET_ACT_SIMP=m ++CONFIG_NET_ACT_SKBEDIT=m ++CONFIG_NET_ACT_CSUM=m + CONFIG_NET_PKTGEN=m ++CONFIG_HAMRADIO=y ++CONFIG_AX25=m ++CONFIG_NETROM=m ++CONFIG_ROSE=m ++CONFIG_MKISS=m ++CONFIG_6PACK=m ++CONFIG_BPQETHER=m ++CONFIG_BAYCOM_SER_FDX=m ++CONFIG_BAYCOM_SER_HDX=m ++CONFIG_YAM=m + CONFIG_IRDA=m + CONFIG_IRLAN=m ++CONFIG_IRNET=m + CONFIG_IRCOMM=m + CONFIG_IRDA_ULTRA=y + CONFIG_IRDA_CACHE_LAST_LSAP=y +@@ -85,7 +308,6 @@ + CONFIG_NFC=m + CONFIG_NFC_PN533=m + CONFIG_DEVTMPFS=y +-CONFIG_DEVTMPFS_MOUNT=y + CONFIG_BLK_DEV_LOOP=y + CONFIG_BLK_DEV_CRYPTOLOOP=m + CONFIG_BLK_DEV_NBD=m +@@ -95,47 +317,29 @@ + CONFIG_SCSI=y + # CONFIG_SCSI_PROC_FS is not set + CONFIG_BLK_DEV_SD=y ++CONFIG_CHR_DEV_ST=m ++CONFIG_CHR_DEV_OSST=m + CONFIG_BLK_DEV_SR=m + CONFIG_SCSI_MULTI_LUN=y + # CONFIG_SCSI_LOWLEVEL is not set ++CONFIG_MD=y ++CONFIG_BLK_DEV_DM=m ++CONFIG_DM_CRYPT=m ++CONFIG_DM_SNAPSHOT=m ++CONFIG_DM_MIRROR=m ++CONFIG_DM_RAID=m ++CONFIG_DM_LOG_USERSPACE=m ++CONFIG_DM_ZERO=m ++CONFIG_DM_DELAY=m + CONFIG_NETDEVICES=y +-CONFIG_NETCONSOLE=m ++CONFIG_BONDING=m ++CONFIG_MACVLAN=m + CONFIG_TUN=m + CONFIG_PHYLIB=m + CONFIG_MDIO_BITBANG=m +-CONFIG_PPP=m +-CONFIG_PPP_BSDCOMP=m +-CONFIG_PPP_DEFLATE=m +-CONFIG_PPP_ASYNC=m +-CONFIG_PPP_SYNC_TTY=m +-CONFIG_SLIP=m +-CONFIG_SLIP_COMPRESSED=y +-CONFIG_USB_CATC=m +-CONFIG_USB_KAWETH=m +-CONFIG_USB_PEGASUS=m +-CONFIG_USB_RTL8150=m +-CONFIG_USB_USBNET=y +-CONFIG_USB_NET_AX8817X=m +-CONFIG_USB_NET_CDCETHER=m +-CONFIG_USB_NET_CDC_EEM=m +-CONFIG_USB_NET_DM9601=m +-CONFIG_USB_NET_SMSC75XX=m +-CONFIG_USB_NET_SMSC95XX=y +-CONFIG_USB_NET_GL620A=m +-CONFIG_USB_NET_NET1080=m +-CONFIG_USB_NET_PLUSB=m +-CONFIG_USB_NET_MCS7830=m +-CONFIG_USB_NET_CDC_SUBSET=m +-CONFIG_USB_ALI_M5632=y +-CONFIG_USB_AN2720=y +-CONFIG_USB_KC2190=y +-# CONFIG_USB_NET_ZAURUS is not set +-CONFIG_USB_NET_CX82310_ETH=m +-CONFIG_USB_NET_KALMIA=m +-CONFIG_USB_NET_INT51X1=m +-CONFIG_USB_IPHETH=m +-CONFIG_USB_SIERRA_NET=m +-CONFIG_USB_VL600=m ++CONFIG_NET_ETHERNET=y ++# CONFIG_NETDEV_1000 is not set ++# CONFIG_NETDEV_10000 is not set + CONFIG_LIBERTAS_THINFIRM=m + CONFIG_LIBERTAS_THINFIRM_USB=m + CONFIG_AT76C50X_USB=m +@@ -148,6 +352,7 @@ + CONFIG_ATH9K_HTC=m + CONFIG_CARL9170=m + CONFIG_B43=m ++CONFIG_B43_PHY_N=y + CONFIG_B43LEGACY=m + CONFIG_HOSTAP=m + CONFIG_IWM=m +@@ -168,6 +373,45 @@ + CONFIG_MWIFIEX=m + CONFIG_MWIFIEX_SDIO=m + CONFIG_WIMAX_I2400M_USB=m ++CONFIG_USB_CATC=m ++CONFIG_USB_KAWETH=m ++CONFIG_USB_PEGASUS=m ++CONFIG_USB_RTL8150=m ++CONFIG_USB_USBNET=y ++CONFIG_USB_NET_AX8817X=m ++CONFIG_USB_NET_CDCETHER=m ++CONFIG_USB_NET_CDC_EEM=m ++CONFIG_USB_NET_DM9601=m ++CONFIG_USB_NET_SMSC75XX=m ++CONFIG_USB_NET_SMSC95XX=y ++CONFIG_USB_NET_GL620A=m ++CONFIG_USB_NET_NET1080=m ++CONFIG_USB_NET_PLUSB=m ++CONFIG_USB_NET_MCS7830=m ++CONFIG_USB_NET_CDC_SUBSET=m ++CONFIG_USB_ALI_M5632=y ++CONFIG_USB_AN2720=y ++CONFIG_USB_KC2190=y ++# CONFIG_USB_NET_ZAURUS is not set ++CONFIG_USB_NET_CX82310_ETH=m ++CONFIG_USB_NET_KALMIA=m ++CONFIG_USB_NET_INT51X1=m ++CONFIG_USB_IPHETH=m ++CONFIG_USB_SIERRA_NET=m ++CONFIG_USB_VL600=m ++CONFIG_PPP=m ++CONFIG_PPP_MULTILINK=y ++CONFIG_PPP_FILTER=y ++CONFIG_PPP_ASYNC=m ++CONFIG_PPP_SYNC_TTY=m ++CONFIG_PPP_DEFLATE=m ++CONFIG_PPP_BSDCOMP=m ++CONFIG_PPP_MPPE=m ++CONFIG_PPPOE=m ++CONFIG_SLIP=m ++CONFIG_SLIP_COMPRESSED=y ++CONFIG_SLIP_SMART=y ++CONFIG_NETCONSOLE=m + CONFIG_INPUT_POLLDEV=m + # CONFIG_INPUT_MOUSEDEV_PSAUX is not set + CONFIG_INPUT_JOYDEV=m +@@ -176,6 +420,7 @@ + # CONFIG_INPUT_MOUSE is not set + CONFIG_INPUT_MISC=y + CONFIG_INPUT_AD714X=m ++CONFIG_INPUT_ATI_REMOTE=m + CONFIG_INPUT_ATI_REMOTE2=m + CONFIG_INPUT_KEYSPAN_REMOTE=m + CONFIG_INPUT_POWERMATE=m +@@ -195,14 +440,38 @@ + # CONFIG_DEVKMEM is not set + CONFIG_SERIAL_AMBA_PL011=y + CONFIG_SERIAL_AMBA_PL011_CONSOLE=y ++CONFIG_TTY_PRINTK=y + # CONFIG_HW_RANDOM is not set + CONFIG_RAW_DRIVER=y ++CONFIG_I2C=y ++CONFIG_I2C_CHARDEV=m ++CONFIG_I2C_BCM2708=m ++CONFIG_SPI=y ++CONFIG_SPI_BCM2708=m ++CONFIG_SPI_SPIDEV=m + CONFIG_GPIO_SYSFS=y ++CONFIG_W1=m ++CONFIG_W1_MASTER_DS2490=m ++CONFIG_W1_MASTER_DS2482=m ++CONFIG_W1_MASTER_DS1WM=m ++CONFIG_W1_MASTER_GPIO=m ++CONFIG_W1_SLAVE_THERM=m ++CONFIG_W1_SLAVE_SMEM=m ++CONFIG_W1_SLAVE_DS2408=m ++CONFIG_W1_SLAVE_DS2423=m ++CONFIG_W1_SLAVE_DS2431=m ++CONFIG_W1_SLAVE_DS2433=m ++CONFIG_W1_SLAVE_DS2760=m ++CONFIG_W1_SLAVE_DS2780=m ++CONFIG_W1_SLAVE_BQ27000=m + # CONFIG_HWMON is not set + CONFIG_WATCHDOG=y + CONFIG_BCM2708_WDT=m ++# CONFIG_MFD_SUPPORT is not set + CONFIG_MEDIA_SUPPORT=m + CONFIG_VIDEO_DEV=m ++CONFIG_DVB_CORE=m ++CONFIG_MEDIA_ATTACH=y + CONFIG_USB_VIDEO_CLASS=m + CONFIG_USB_M5602=m + CONFIG_USB_STV06XX=m +@@ -248,11 +517,61 @@ + CONFIG_USB_GSPCA_VICAM=m + CONFIG_USB_GSPCA_XIRLINK_CIT=m + CONFIG_USB_GSPCA_ZC3XX=m ++CONFIG_VIDEO_PVRUSB2=m + CONFIG_VIDEO_HDPVR=m ++CONFIG_VIDEO_EM28XX=m ++CONFIG_VIDEO_EM28XX_ALSA=m ++CONFIG_VIDEO_EM28XX_DVB=m ++CONFIG_VIDEO_TLG2300=m ++CONFIG_VIDEO_CX231XX=m ++CONFIG_VIDEO_CX231XX_ALSA=m ++CONFIG_VIDEO_CX231XX_DVB=m ++CONFIG_VIDEO_USBVISION=m ++CONFIG_USB_ET61X251=m ++CONFIG_USB_SN9C102=m + CONFIG_USB_PWC=m + CONFIG_USB_ZR364XX=m + CONFIG_USB_STKWEBCAM=m + CONFIG_USB_S2255=m ++CONFIG_USB_DSBR=m ++CONFIG_RADIO_SI470X=y ++CONFIG_USB_SI470X=m ++CONFIG_USB_MR800=m ++CONFIG_DVB_USB=m ++CONFIG_DVB_USB_A800=m ++CONFIG_DVB_USB_DIBUSB_MB=m ++CONFIG_DVB_USB_DIBUSB_MC=m ++CONFIG_DVB_USB_DIB0700=m ++CONFIG_DVB_USB_UMT_010=m ++CONFIG_DVB_USB_CXUSB=m ++CONFIG_DVB_USB_M920X=m ++CONFIG_DVB_USB_GL861=m ++CONFIG_DVB_USB_AU6610=m ++CONFIG_DVB_USB_DIGITV=m ++CONFIG_DVB_USB_VP7045=m ++CONFIG_DVB_USB_VP702X=m ++CONFIG_DVB_USB_GP8PSK=m ++CONFIG_DVB_USB_NOVA_T_USB2=m ++CONFIG_DVB_USB_TTUSB2=m ++CONFIG_DVB_USB_DTT200U=m ++CONFIG_DVB_USB_OPERA1=m ++CONFIG_DVB_USB_AF9005=m ++CONFIG_DVB_USB_AF9005_REMOTE=m ++CONFIG_DVB_USB_DW2102=m ++CONFIG_DVB_USB_CINERGY_T2=m ++CONFIG_DVB_USB_ANYSEE=m ++CONFIG_DVB_USB_DTV5100=m ++CONFIG_DVB_USB_AF9015=m ++CONFIG_DVB_USB_CE6230=m ++CONFIG_DVB_USB_FRIIO=m ++CONFIG_DVB_USB_EC168=m ++CONFIG_DVB_USB_AZ6027=m ++CONFIG_DVB_USB_LME2510=m ++CONFIG_DVB_USB_TECHNISAT_USB2=m ++CONFIG_SMS_SIANO_MDTV=m ++CONFIG_SMS_USB_DRV=m ++CONFIG_DVB_B2C2_FLEXCOP=m ++CONFIG_DVB_B2C2_FLEXCOP_USB=m + CONFIG_FB=y + CONFIG_FB_BCM2708=y + CONFIG_FRAMEBUFFER_CONSOLE=y +@@ -428,6 +747,12 @@ + CONFIG_UIO=m + CONFIG_UIO_PDRV=m + CONFIG_UIO_PDRV_GENIRQ=m ++CONFIG_STAGING=y ++CONFIG_W35UND=m ++CONFIG_PRISM2_USB=m ++CONFIG_R8712U=m ++CONFIG_R8712_AP=y ++CONFIG_ZRAM=m + # CONFIG_IOMMU_SUPPORT is not set + CONFIG_EXT4_FS=y + CONFIG_EXT4_FS_POSIX_ACL=y +@@ -439,6 +764,7 @@ + CONFIG_JFS_FS=m + CONFIG_JFS_POSIX_ACL=y + CONFIG_JFS_SECURITY=y ++CONFIG_JFS_STATISTICS=y + CONFIG_XFS_FS=m + CONFIG_XFS_QUOTA=y + CONFIG_XFS_POSIX_ACL=y +@@ -448,10 +774,13 @@ + CONFIG_BTRFS_FS=m + CONFIG_BTRFS_FS_POSIX_ACL=y + CONFIG_NILFS2_FS=m ++CONFIG_FANOTIFY=y + CONFIG_AUTOFS4_FS=y + CONFIG_FUSE_FS=m + CONFIG_CUSE=m + CONFIG_FSCACHE=y ++CONFIG_FSCACHE_STATS=y ++CONFIG_FSCACHE_HISTOGRAM=y + CONFIG_CACHEFILES=y + CONFIG_ISO9660_FS=m + CONFIG_JOLIET=y +@@ -464,6 +793,9 @@ + CONFIG_TMPFS=y + CONFIG_TMPFS_POSIX_ACL=y + CONFIG_CONFIGFS_FS=y ++CONFIG_ECRYPT_FS=m ++CONFIG_HFS_FS=m ++CONFIG_HFSPLUS_FS=m + CONFIG_SQUASHFS=m + CONFIG_SQUASHFS_XATTR=y + CONFIG_SQUASHFS_LZO=y +@@ -474,11 +806,13 @@ + CONFIG_NFS_V4=y + CONFIG_ROOT_NFS=y + CONFIG_NFS_FSCACHE=y ++CONFIG_NFSD=m + CONFIG_CIFS=m + CONFIG_CIFS_WEAK_PW_HASH=y + CONFIG_CIFS_XATTR=y + CONFIG_CIFS_POSIX=y + CONFIG_9P_FS=m ++CONFIG_9P_FS_POSIX_ACL=y + CONFIG_PARTITION_ADVANCED=y + CONFIG_MAC_PARTITION=y + CONFIG_EFI_PARTITION=y +@@ -520,15 +854,29 @@ + CONFIG_NLS_ISO8859_15=m + CONFIG_NLS_KOI8_R=m + CONFIG_NLS_KOI8_U=m +-CONFIG_NLS_UTF8=m +-# CONFIG_SCHED_DEBUG is not set ++CONFIG_PRINTK_TIME=y ++CONFIG_DETECT_HUNG_TASK=y ++CONFIG_TIMER_STATS=y + # CONFIG_DEBUG_PREEMPT is not set +-# CONFIG_DEBUG_BUGVERBOSE is not set +-# CONFIG_FTRACE is not set +-# CONFIG_ARM_UNWIND is not set ++CONFIG_DEBUG_MEMORY_INIT=y ++CONFIG_BOOT_PRINTK_DELAY=y ++CONFIG_LATENCYTOP=y ++CONFIG_SYSCTL_SYSCALL_CHECK=y ++# CONFIG_EVENT_POWER_TRACING_DEPRECATED is not set ++CONFIG_IRQSOFF_TRACER=y ++CONFIG_PREEMPT_TRACER=y ++CONFIG_SCHED_TRACER=y ++CONFIG_STACK_TRACER=y ++CONFIG_BLK_DEV_IO_TRACE=y ++CONFIG_FUNCTION_PROFILER=y ++CONFIG_KGDB=y ++CONFIG_KGDB_KDB=y ++CONFIG_KDB_KEYBOARD=y ++CONFIG_STRICT_DEVMEM=y + CONFIG_CRYPTO_AUTHENC=m + CONFIG_CRYPTO_SEQIV=m + CONFIG_CRYPTO_CBC=y ++CONFIG_CRYPTO_XTS=m + CONFIG_CRYPTO_HMAC=y + CONFIG_CRYPTO_XCBC=m + CONFIG_CRYPTO_MD5=y diff -Nru linux-3.2.46/debian/patches/rpi/rpi_223_ddebe4dc47bf1d6e95cb478ce3d4a72a99a4e677.patch linux-3.2.46/debian/patches/rpi/rpi_223_ddebe4dc47bf1d6e95cb478ce3d4a72a99a4e677.patch --- linux-3.2.46/debian/patches/rpi/rpi_223_ddebe4dc47bf1d6e95cb478ce3d4a72a99a4e677.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_223_ddebe4dc47bf1d6e95cb478ce3d4a72a99a4e677.patch 2013-07-26 19:35:43.000000000 +0000 @@ -0,0 +1,256 @@ +commit ddebe4dc47bf1d6e95cb478ce3d4a72a99a4e677 +Author: popcornmix +Date: Tue Aug 21 13:10:02 2012 +0100 + + Regenerate defconfigs for updated kernel verision, try 2 + +Index: linux-3.2.46/arch/arm/configs/bcmrpi_cutdown_defconfig +=================================================================== +--- linux-3.2.46.orig/arch/arm/configs/bcmrpi_cutdown_defconfig 2013-07-26 19:35:40.000000000 +0000 ++++ linux-3.2.46/arch/arm/configs/bcmrpi_cutdown_defconfig 2013-07-26 19:35:42.000000000 +0000 +@@ -3,7 +3,6 @@ + # CONFIG_LOCALVERSION_AUTO is not set + CONFIG_SYSVIPC=y + CONFIG_POSIX_MQUEUE=y +-CONFIG_TINY_RCU=y + CONFIG_IKCONFIG=y + CONFIG_IKCONFIG_PROC=y + CONFIG_SCHED_AUTOGROUP=y +@@ -100,12 +99,43 @@ + CONFIG_SCSI_MULTI_LUN=y + # CONFIG_SCSI_LOWLEVEL is not set + CONFIG_NETDEVICES=y ++CONFIG_NETCONSOLE=m + CONFIG_TUN=m + CONFIG_PHYLIB=m + CONFIG_MDIO_BITBANG=m +-CONFIG_NET_ETHERNET=y +-# CONFIG_NETDEV_1000 is not set +-# CONFIG_NETDEV_10000 is not set ++CONFIG_PPP=m ++CONFIG_PPP_BSDCOMP=m ++CONFIG_PPP_DEFLATE=m ++CONFIG_PPP_ASYNC=m ++CONFIG_PPP_SYNC_TTY=m ++CONFIG_SLIP=m ++CONFIG_SLIP_COMPRESSED=y ++CONFIG_USB_CATC=m ++CONFIG_USB_KAWETH=m ++CONFIG_USB_PEGASUS=m ++CONFIG_USB_RTL8150=m ++CONFIG_USB_USBNET=y ++CONFIG_USB_NET_AX8817X=m ++CONFIG_USB_NET_CDCETHER=m ++CONFIG_USB_NET_CDC_EEM=m ++CONFIG_USB_NET_DM9601=m ++CONFIG_USB_NET_SMSC75XX=m ++CONFIG_USB_NET_SMSC95XX=y ++CONFIG_USB_NET_GL620A=m ++CONFIG_USB_NET_NET1080=m ++CONFIG_USB_NET_PLUSB=m ++CONFIG_USB_NET_MCS7830=m ++CONFIG_USB_NET_CDC_SUBSET=m ++CONFIG_USB_ALI_M5632=y ++CONFIG_USB_AN2720=y ++CONFIG_USB_KC2190=y ++# CONFIG_USB_NET_ZAURUS is not set ++CONFIG_USB_NET_CX82310_ETH=m ++CONFIG_USB_NET_KALMIA=m ++CONFIG_USB_NET_INT51X1=m ++CONFIG_USB_IPHETH=m ++CONFIG_USB_SIERRA_NET=m ++CONFIG_USB_VL600=m + CONFIG_LIBERTAS_THINFIRM=m + CONFIG_LIBERTAS_THINFIRM_USB=m + CONFIG_AT76C50X_USB=m +@@ -138,40 +168,6 @@ + CONFIG_MWIFIEX=m + CONFIG_MWIFIEX_SDIO=m + CONFIG_WIMAX_I2400M_USB=m +-CONFIG_USB_CATC=m +-CONFIG_USB_KAWETH=m +-CONFIG_USB_PEGASUS=m +-CONFIG_USB_RTL8150=m +-CONFIG_USB_USBNET=y +-CONFIG_USB_NET_AX8817X=m +-CONFIG_USB_NET_CDCETHER=m +-CONFIG_USB_NET_CDC_EEM=m +-CONFIG_USB_NET_DM9601=m +-CONFIG_USB_NET_SMSC75XX=m +-CONFIG_USB_NET_SMSC95XX=y +-CONFIG_USB_NET_GL620A=m +-CONFIG_USB_NET_NET1080=m +-CONFIG_USB_NET_PLUSB=m +-CONFIG_USB_NET_MCS7830=m +-CONFIG_USB_NET_CDC_SUBSET=m +-CONFIG_USB_ALI_M5632=y +-CONFIG_USB_AN2720=y +-CONFIG_USB_KC2190=y +-# CONFIG_USB_NET_ZAURUS is not set +-CONFIG_USB_NET_CX82310_ETH=m +-CONFIG_USB_NET_KALMIA=m +-CONFIG_USB_NET_INT51X1=m +-CONFIG_USB_IPHETH=m +-CONFIG_USB_SIERRA_NET=m +-CONFIG_USB_VL600=m +-CONFIG_PPP=m +-CONFIG_PPP_ASYNC=m +-CONFIG_PPP_SYNC_TTY=m +-CONFIG_PPP_DEFLATE=m +-CONFIG_PPP_BSDCOMP=m +-CONFIG_SLIP=m +-CONFIG_SLIP_COMPRESSED=y +-CONFIG_NETCONSOLE=m + CONFIG_INPUT_POLLDEV=m + # CONFIG_INPUT_MOUSEDEV_PSAUX is not set + CONFIG_INPUT_JOYDEV=m +@@ -180,7 +176,6 @@ + # CONFIG_INPUT_MOUSE is not set + CONFIG_INPUT_MISC=y + CONFIG_INPUT_AD714X=m +-CONFIG_INPUT_ATI_REMOTE=m + CONFIG_INPUT_ATI_REMOTE2=m + CONFIG_INPUT_KEYSPAN_REMOTE=m + CONFIG_INPUT_POWERMATE=m +@@ -206,7 +201,6 @@ + # CONFIG_HWMON is not set + CONFIG_WATCHDOG=y + CONFIG_BCM2708_WDT=m +-# CONFIG_MFD_SUPPORT is not set + CONFIG_MEDIA_SUPPORT=m + CONFIG_VIDEO_DEV=m + CONFIG_USB_VIDEO_CLASS=m +Index: linux-3.2.46/arch/arm/configs/bcmrpi_defconfig +=================================================================== +--- linux-3.2.46.orig/arch/arm/configs/bcmrpi_defconfig 2013-07-26 19:35:40.000000000 +0000 ++++ linux-3.2.46/arch/arm/configs/bcmrpi_defconfig 2013-07-26 19:35:42.000000000 +0000 +@@ -6,7 +6,6 @@ + CONFIG_BSD_PROCESS_ACCT_V3=y + CONFIG_FHANDLE=y + CONFIG_AUDIT=y +-CONFIG_TINY_RCU=y + CONFIG_IKCONFIG=y + CONFIG_IKCONFIG_PROC=y + CONFIG_CGROUP_FREEZER=y +@@ -334,12 +333,48 @@ + CONFIG_NETDEVICES=y + CONFIG_BONDING=m + CONFIG_MACVLAN=m ++CONFIG_NETCONSOLE=m + CONFIG_TUN=m + CONFIG_PHYLIB=m + CONFIG_MDIO_BITBANG=m +-CONFIG_NET_ETHERNET=y +-# CONFIG_NETDEV_1000 is not set +-# CONFIG_NETDEV_10000 is not set ++CONFIG_PPP=m ++CONFIG_PPP_BSDCOMP=m ++CONFIG_PPP_DEFLATE=m ++CONFIG_PPP_FILTER=y ++CONFIG_PPP_MPPE=m ++CONFIG_PPP_MULTILINK=y ++CONFIG_PPPOE=m ++CONFIG_PPP_ASYNC=m ++CONFIG_PPP_SYNC_TTY=m ++CONFIG_SLIP=m ++CONFIG_SLIP_COMPRESSED=y ++CONFIG_SLIP_SMART=y ++CONFIG_USB_CATC=m ++CONFIG_USB_KAWETH=m ++CONFIG_USB_PEGASUS=m ++CONFIG_USB_RTL8150=m ++CONFIG_USB_USBNET=y ++CONFIG_USB_NET_AX8817X=m ++CONFIG_USB_NET_CDCETHER=m ++CONFIG_USB_NET_CDC_EEM=m ++CONFIG_USB_NET_DM9601=m ++CONFIG_USB_NET_SMSC75XX=m ++CONFIG_USB_NET_SMSC95XX=y ++CONFIG_USB_NET_GL620A=m ++CONFIG_USB_NET_NET1080=m ++CONFIG_USB_NET_PLUSB=m ++CONFIG_USB_NET_MCS7830=m ++CONFIG_USB_NET_CDC_SUBSET=m ++CONFIG_USB_ALI_M5632=y ++CONFIG_USB_AN2720=y ++CONFIG_USB_KC2190=y ++# CONFIG_USB_NET_ZAURUS is not set ++CONFIG_USB_NET_CX82310_ETH=m ++CONFIG_USB_NET_KALMIA=m ++CONFIG_USB_NET_INT51X1=m ++CONFIG_USB_IPHETH=m ++CONFIG_USB_SIERRA_NET=m ++CONFIG_USB_VL600=m + CONFIG_LIBERTAS_THINFIRM=m + CONFIG_LIBERTAS_THINFIRM_USB=m + CONFIG_AT76C50X_USB=m +@@ -373,45 +408,6 @@ + CONFIG_MWIFIEX=m + CONFIG_MWIFIEX_SDIO=m + CONFIG_WIMAX_I2400M_USB=m +-CONFIG_USB_CATC=m +-CONFIG_USB_KAWETH=m +-CONFIG_USB_PEGASUS=m +-CONFIG_USB_RTL8150=m +-CONFIG_USB_USBNET=y +-CONFIG_USB_NET_AX8817X=m +-CONFIG_USB_NET_CDCETHER=m +-CONFIG_USB_NET_CDC_EEM=m +-CONFIG_USB_NET_DM9601=m +-CONFIG_USB_NET_SMSC75XX=m +-CONFIG_USB_NET_SMSC95XX=y +-CONFIG_USB_NET_GL620A=m +-CONFIG_USB_NET_NET1080=m +-CONFIG_USB_NET_PLUSB=m +-CONFIG_USB_NET_MCS7830=m +-CONFIG_USB_NET_CDC_SUBSET=m +-CONFIG_USB_ALI_M5632=y +-CONFIG_USB_AN2720=y +-CONFIG_USB_KC2190=y +-# CONFIG_USB_NET_ZAURUS is not set +-CONFIG_USB_NET_CX82310_ETH=m +-CONFIG_USB_NET_KALMIA=m +-CONFIG_USB_NET_INT51X1=m +-CONFIG_USB_IPHETH=m +-CONFIG_USB_SIERRA_NET=m +-CONFIG_USB_VL600=m +-CONFIG_PPP=m +-CONFIG_PPP_MULTILINK=y +-CONFIG_PPP_FILTER=y +-CONFIG_PPP_ASYNC=m +-CONFIG_PPP_SYNC_TTY=m +-CONFIG_PPP_DEFLATE=m +-CONFIG_PPP_BSDCOMP=m +-CONFIG_PPP_MPPE=m +-CONFIG_PPPOE=m +-CONFIG_SLIP=m +-CONFIG_SLIP_COMPRESSED=y +-CONFIG_SLIP_SMART=y +-CONFIG_NETCONSOLE=m + CONFIG_INPUT_POLLDEV=m + # CONFIG_INPUT_MOUSEDEV_PSAUX is not set + CONFIG_INPUT_JOYDEV=m +@@ -420,7 +416,6 @@ + # CONFIG_INPUT_MOUSE is not set + CONFIG_INPUT_MISC=y + CONFIG_INPUT_AD714X=m +-CONFIG_INPUT_ATI_REMOTE=m + CONFIG_INPUT_ATI_REMOTE2=m + CONFIG_INPUT_KEYSPAN_REMOTE=m + CONFIG_INPUT_POWERMATE=m +@@ -467,7 +462,6 @@ + # CONFIG_HWMON is not set + CONFIG_WATCHDOG=y + CONFIG_BCM2708_WDT=m +-# CONFIG_MFD_SUPPORT is not set + CONFIG_MEDIA_SUPPORT=m + CONFIG_VIDEO_DEV=m + CONFIG_DVB_CORE=m +@@ -751,7 +745,6 @@ + CONFIG_W35UND=m + CONFIG_PRISM2_USB=m + CONFIG_R8712U=m +-CONFIG_R8712_AP=y + CONFIG_ZRAM=m + # CONFIG_IOMMU_SUPPORT is not set + CONFIG_EXT4_FS=y diff -Nru linux-3.2.46/debian/patches/rpi/rpi_224_e6b8622bffcc4823913f491b40904a7f27710569.patch linux-3.2.46/debian/patches/rpi/rpi_224_e6b8622bffcc4823913f491b40904a7f27710569.patch --- linux-3.2.46/debian/patches/rpi/rpi_224_e6b8622bffcc4823913f491b40904a7f27710569.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_224_e6b8622bffcc4823913f491b40904a7f27710569.patch 2013-07-26 19:35:44.000000000 +0000 @@ -0,0 +1,164 @@ +commit e6b8622bffcc4823913f491b40904a7f27710569 +Author: popcornmix +Date: Tue Aug 21 18:49:44 2012 +0100 + + Read memory size for vc_mem through mailbox property channel + +Index: linux-3.2.46/arch/arm/mach-bcm2708/include/mach/vcio.h +=================================================================== +--- linux-3.2.46.orig/arch/arm/mach-bcm2708/include/mach/vcio.h 2013-07-26 19:31:51.000000000 +0000 ++++ linux-3.2.46/arch/arm/mach-bcm2708/include/mach/vcio.h 2013-07-26 19:35:43.000000000 +0000 +@@ -34,7 +34,8 @@ + #define MBOX_CHAN_LEDS 4 /* for use by the leds interface */ + #define MBOX_CHAN_BUTTONS 5 /* for use by the buttons interface */ + #define MBOX_CHAN_TOUCH 6 /* for use by the touchscreen interface */ +-#define MBOX_CHAN_COUNT 7 ++#define MBOX_CHAN_PROPERTY 8 /* for use by the property channel */ ++#define MBOX_CHAN_COUNT 9 + + extern int /*rc*/ bcm_mailbox_read(unsigned chan, uint32_t *data28); + extern int /*rc*/ bcm_mailbox_write(unsigned chan, uint32_t data28); +Index: linux-3.2.46/arch/arm/mach-bcm2708/include/mach/vmalloc.h +=================================================================== +--- linux-3.2.46.orig/arch/arm/mach-bcm2708/include/mach/vmalloc.h 2013-07-26 19:31:51.000000000 +0000 ++++ linux-3.2.46/arch/arm/mach-bcm2708/include/mach/vmalloc.h 2013-07-26 19:35:43.000000000 +0000 +@@ -17,4 +17,4 @@ + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +-#define VMALLOC_END (0xd8000000) ++#define VMALLOC_END (0xe8000000) +Index: linux-3.2.46/arch/arm/mach-bcm2708/vc_mem.c +=================================================================== +--- linux-3.2.46.orig/arch/arm/mach-bcm2708/vc_mem.c 2013-07-26 19:32:41.000000000 +0000 ++++ linux-3.2.46/arch/arm/mach-bcm2708/vc_mem.c 2013-07-26 19:35:43.000000000 +0000 +@@ -21,6 +21,7 @@ + #include + #include + #include ++#include + + #ifdef CONFIG_ARCH_KONA + #include +@@ -30,12 +31,12 @@ + #endif + + #include "mach/vc_mem.h" +-//#include "interface/vchiq_arm/vchiq_connected.h" ++#include + + #define DRIVER_NAME "vc-mem" + + // Uncomment to enable debug logging +-//#define ENABLE_DBG ++#define ENABLE_DBG + + #if defined(ENABLE_DBG) + #define LOG_DBG( fmt, ... ) printk( KERN_INFO fmt "\n", ##__VA_ARGS__ ) +@@ -67,23 +68,8 @@ + * bootloader (and/or kernel). When that happens, the values of these variables + * would be calculated and assigned in the init function. + */ +-#ifdef CONFIG_ARCH_KONA +- +-#include +-unsigned long mm_vc_mem_phys_addr = VC_EMI; +- +-#elif CONFIG_ARCH_BCM2708 +- + // in the 2835 VC in mapped above ARM, but ARM has full access to VC space + unsigned long mm_vc_mem_phys_addr = 0x00000000; +- +-#else +- +-#include +-unsigned long mm_vc_mem_phys_addr = MM_ADDR_IO_VC_EMI; +- +-#endif +- + unsigned int mm_vc_mem_size = 0; + unsigned int mm_vc_mem_base = 0; + +@@ -125,6 +111,64 @@ + return 0; + } + ++ ++/* tag part of the message */ ++struct vc_msg_tag { ++ uint32_t tag_id; /* the message id */ ++ uint32_t buffer_size; /* size of the buffer (which in this case is always 8 bytes) */ ++ uint32_t data_size; /* amount of data being sent or received */ ++ uint32_t base; /* the address of memory base */ ++ uint32_t size; /* the size of memory in bytes */ ++}; ++ ++struct vc_set_msg { ++ uint32_t msg_size; /* simply, sizeof(struct vc_msg) */ ++ uint32_t request_code; /* holds various information like the success and number of bytes returned (refer to mailboxes wiki) */ ++ struct vc_msg_tag tag[2]; /* the array of tag structures above to make */ ++ uint32_t end_tag; /* an end identifier, should be set to NULL */ ++}; ++ ++#define VCMSG_GET_ARM_MEMORY 0x00010005 ++#define VCMSG_GET_VC_MEMORY 0x00010006 ++ ++static void vc_mem_update(void) ++{ ++ uint32_t success; ++ dma_addr_t vc_mem; /* the memory address accessed from videocore */ ++ struct vc_set_msg *get_mem; /* the memory address accessed from driver */ ++ ++ /* allocate some memory for the messages to use throughout the lifetime of the driver, use the larger of the two message structures */ ++ get_mem = (struct vc_set_msg *)dma_alloc_coherent(NULL, PAGE_ALIGN(sizeof(struct vc_set_msg)), &vc_mem, GFP_ATOMIC); ++ /* clear any garbage */ ++ memset(get_mem, 0, sizeof(struct vc_set_msg)); ++ /* create the message */ ++ get_mem->msg_size = sizeof(struct vc_set_msg); ++ get_mem->tag[0].tag_id = VCMSG_GET_VC_MEMORY; ++ get_mem->tag[0].buffer_size = 8; ++ get_mem->tag[0].data_size = 0; ++ get_mem->tag[1].tag_id = VCMSG_GET_ARM_MEMORY; ++ get_mem->tag[1].buffer_size = 8; ++ get_mem->tag[1].data_size = 0; ++ ++ /* send the message */ ++ wmb(); ++ bcm_mailbox_write(MBOX_CHAN_PROPERTY,(uint32_t)vc_mem); ++ bcm_mailbox_read(MBOX_CHAN_PROPERTY, &success); ++ rmb(); ++ ++ LOG_DBG("%s: resp %x, vcbase=%x vcsize=%x armbase=%x armsize=%x", __func__, get_mem->request_code, ++ get_mem->tag[0].base, get_mem->tag[0].size, get_mem->tag[1].base, get_mem->tag[1].size); ++ ++ /* check we're all good */ ++ if (get_mem->request_code & 0x80000000) { ++ mm_vc_mem_base = get_mem->tag[0].base; ++ mm_vc_mem_size = get_mem->tag[0].size+get_mem->tag[1].size; ++ mm_vc_mem_phys_addr = get_mem->tag[1].base; ++ } ++ dma_free_coherent(NULL, PAGE_ALIGN(sizeof(struct vc_set_msg)), (void *)get_mem, vc_mem); ++} ++ ++ + /**************************************************************************** + * + * vc_mem_get_size +@@ -134,7 +178,7 @@ + static void + vc_mem_get_size(void) + { +- mm_vc_mem_size = 256 * 1024 * 1024; // Static for now ++ vc_mem_update(); + } + + /**************************************************************************** +@@ -146,7 +190,7 @@ + static void + vc_mem_get_base(void) + { +- mm_vc_mem_base = 128 * 1024 * 1024; // Static for now ++ vc_mem_update(); + } + + /**************************************************************************** diff -Nru linux-3.2.46/debian/patches/rpi/rpi_225_2b039107863998de874b555a9e5af921792370e5.patch linux-3.2.46/debian/patches/rpi/rpi_225_2b039107863998de874b555a9e5af921792370e5.patch --- linux-3.2.46/debian/patches/rpi/rpi_225_2b039107863998de874b555a9e5af921792370e5.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_225_2b039107863998de874b555a9e5af921792370e5.patch 2013-07-26 19:35:45.000000000 +0000 @@ -0,0 +1,32 @@ +commit 2b039107863998de874b555a9e5af921792370e5 +Author: popcornmix +Date: Tue Aug 21 18:57:05 2012 +0100 + + Revert "amba-pl011: Don't send a character during startup" + + This reverts commit 4a0a5565a02b84d1061bc3dccc5384b4b6829851. + +Index: linux-3.2.46/drivers/tty/serial/amba-pl011.c +=================================================================== +--- linux-3.2.46.orig/drivers/tty/serial/amba-pl011.c 2013-07-26 19:35:39.000000000 +0000 ++++ linux-3.2.46/drivers/tty/serial/amba-pl011.c 2013-07-26 19:35:45.000000000 +0000 +@@ -1394,11 +1394,6 @@ + writew(uap->vendor->ifls, uap->port.membase + UART011_IFLS); + + /* +- * The write to UART01x_DR causes a corrupted character to be sent +- * - why is it required? +- */ +-#if 0 +- /* + * Provoke TX FIFO interrupt into asserting. + */ + cr = UART01x_CR_UARTEN | UART011_CR_TXE | UART011_CR_LBE; +@@ -1419,7 +1414,6 @@ + writew(0, uap->port.membase + UART01x_DR); + while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_BUSY) + barrier(); +-#endif + + cr = UART01x_CR_UARTEN | UART011_CR_RXE | UART011_CR_TXE; + writew(cr, uap->port.membase + UART011_CR); diff -Nru linux-3.2.46/debian/patches/rpi/rpi_226_091073bcab483b976ee33dfe914c28df87914a3b.patch linux-3.2.46/debian/patches/rpi/rpi_226_091073bcab483b976ee33dfe914c28df87914a3b.patch --- linux-3.2.46/debian/patches/rpi/rpi_226_091073bcab483b976ee33dfe914c28df87914a3b.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_226_091073bcab483b976ee33dfe914c28df87914a3b.patch 2013-07-26 19:35:48.000000000 +0000 @@ -0,0 +1,2440 @@ +commit 091073bcab483b976ee33dfe914c28df87914a3b +Author: popcornmix +Date: Wed Aug 22 12:43:36 2012 +0100 + + Update to dwc_otg 3.00. Seems to be a very minor update (mostly adding support for a newer version of hardware) + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/doc/doxygen.cfg +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/doc/doxygen.cfg 2013-07-26 19:34:39.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/doc/doxygen.cfg 2013-07-26 19:35:46.000000000 +0000 +@@ -4,7 +4,7 @@ + # Project related configuration options + #--------------------------------------------------------------------------- + PROJECT_NAME = "DesignWare USB 2.0 OTG Controller (DWC_otg) Device Driver" +-PROJECT_NUMBER = v2.94a ++PROJECT_NUMBER = v3.00a + OUTPUT_DIRECTORY = ./doc/ + CREATE_SUBDIRS = NO + OUTPUT_LANGUAGE = English +Index: linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_cil.c +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/dwc_otg_cil.c 2013-07-26 19:35:17.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_cil.c 2013-07-26 19:35:46.000000000 +0000 +@@ -1,8 +1,8 @@ + /* ========================================================================== + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_cil.c $ +- * $Revision: #189 $ +- * $Date: 2011/10/24 $ +- * $Change: 1871160 $ ++ * $Revision: #191 $ ++ * $Date: 2012/08/10 $ ++ * $Change: 2047372 $ + * + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless +@@ -284,12 +284,19 @@ + */ + void dwc_otg_cil_remove(dwc_otg_core_if_t * core_if) + { ++ dctl_data_t dctl = {.d32 = 0 }; + DWC_DEBUGPL(DBG_CILV, "%s(%p)\n", __func__, core_if); + + /* Disable all interrupts */ + DWC_MODIFY_REG32(&core_if->core_global_regs->gahbcfg, 1, 0); + DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, 0); + ++ dctl.b.sftdiscon = 1; ++ if (core_if->snpsid >= OTG_CORE_REV_3_00a) { ++ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, 0, ++ dctl.d32); ++ } ++ + if (core_if->wq_otg) { + DWC_WORKQ_WAIT_WORK_DONE(core_if->wq_otg, 500); + DWC_WORKQ_FREE(core_if->wq_otg); +@@ -942,9 +949,9 @@ + return -DWC_E_INVALID; + } + +- if (!rem_wakeup) +- { +- DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl, dr->dctl); ++ if (!rem_wakeup) { ++ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl, ++ dr->dctl); + } + + DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->daintmsk, dr->daintmsk); +@@ -952,9 +959,9 @@ + DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->doepmsk, dr->doepmsk); + + for (i = 0; i < core_if->dev_if->num_in_eps; ++i) { +- DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[i]->diepctl, dr->diepctl[i]); + DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[i]->dieptsiz, dr->dieptsiz[i]); + DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[i]->diepdma, dr->diepdma[i]); ++ DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[i]->diepctl, dr->diepctl[i]); + } + + return 0; +@@ -1788,58 +1795,60 @@ + + txfifosize.b.startaddr += txfifosize.b.depth; + } +- /* Calculating DFIFOCFG for Device mode to include RxFIFO and NPTXFIFO */ +- gdfifocfg.d32 = DWC_READ_REG32(&global_regs->gdfifocfg); +- hwcfg3.d32 = DWC_READ_REG32(&global_regs->ghwcfg3); +- gdfifocfg.b.gdfifocfg = (DWC_READ_REG32(&global_regs->ghwcfg3) >> 16); +- DWC_WRITE_REG32(&global_regs->gdfifocfg, gdfifocfg.d32); +- rxfsiz = (DWC_READ_REG32(&global_regs->grxfsiz) & 0x0000ffff); +- nptxfsiz = (DWC_READ_REG32(&global_regs->gnptxfsiz) >> 16); +- gdfifocfg.b.epinfobase = rxfsiz + nptxfsiz; +- DWC_WRITE_REG32(&global_regs->gdfifocfg, gdfifocfg.d32); ++ if (core_if->snpsid <= OTG_CORE_REV_2_94a) { ++ /* Calculating DFIFOCFG for Device mode to include RxFIFO and NPTXFIFO */ ++ gdfifocfg.d32 = DWC_READ_REG32(&global_regs->gdfifocfg); ++ hwcfg3.d32 = DWC_READ_REG32(&global_regs->ghwcfg3); ++ gdfifocfg.b.gdfifocfg = (DWC_READ_REG32(&global_regs->ghwcfg3) >> 16); ++ DWC_WRITE_REG32(&global_regs->gdfifocfg, gdfifocfg.d32); ++ rxfsiz = (DWC_READ_REG32(&global_regs->grxfsiz) & 0x0000ffff); ++ nptxfsiz = (DWC_READ_REG32(&global_regs->gnptxfsiz) >> 16); ++ gdfifocfg.b.epinfobase = rxfsiz + nptxfsiz; ++ DWC_WRITE_REG32(&global_regs->gdfifocfg, gdfifocfg.d32); ++ } + } +- } +- +- /* Flush the FIFOs */ +- dwc_otg_flush_tx_fifo(core_if, 0x10); /* all Tx FIFOs */ +- dwc_otg_flush_rx_fifo(core_if); + +- /* Flush the Learning Queue. */ +- resetctl.b.intknqflsh = 1; +- DWC_WRITE_REG32(&core_if->core_global_regs->grstctl, resetctl.d32); +- +- if (!core_if->core_params->en_multiple_tx_fifo && core_if->dma_enable) { +- core_if->start_predict = 0; +- for (i = 0; i<= core_if->dev_if->num_in_eps; ++i) { +- core_if->nextep_seq[i] = 0xff; // 0xff - EP not active +- } +- core_if->nextep_seq[0] = 0; +- core_if->first_in_nextep_seq = 0; +- diepctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[0]->diepctl); +- diepctl.b.nextep = 0; +- DWC_WRITE_REG32(&dev_if->in_ep_regs[0]->diepctl, diepctl.d32); ++ /* Flush the FIFOs */ ++ dwc_otg_flush_tx_fifo(core_if, 0x10); /* all Tx FIFOs */ ++ dwc_otg_flush_rx_fifo(core_if); ++ ++ /* Flush the Learning Queue. */ ++ resetctl.b.intknqflsh = 1; ++ DWC_WRITE_REG32(&core_if->core_global_regs->grstctl, resetctl.d32); ++ ++ if (!core_if->core_params->en_multiple_tx_fifo && core_if->dma_enable) { ++ core_if->start_predict = 0; ++ for (i = 0; i<= core_if->dev_if->num_in_eps; ++i) { ++ core_if->nextep_seq[i] = 0xff; // 0xff - EP not active ++ } ++ core_if->nextep_seq[0] = 0; ++ core_if->first_in_nextep_seq = 0; ++ diepctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[0]->diepctl); ++ diepctl.b.nextep = 0; ++ DWC_WRITE_REG32(&dev_if->in_ep_regs[0]->diepctl, diepctl.d32); + +- /* Update IN Endpoint Mismatch Count by active IN NP EP count + 1 */ +- dcfg.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->dcfg); +- dcfg.b.epmscnt = 2; +- DWC_WRITE_REG32(&dev_if->dev_global_regs->dcfg, dcfg.d32); +- +- DWC_DEBUGPL(DBG_CILV,"%s first_in_nextep_seq= %2d; nextep_seq[]:\n", +- __func__, core_if->first_in_nextep_seq); +- for (i=0; i <= core_if->dev_if->num_in_eps; i++) { +- DWC_DEBUGPL(DBG_CILV, "%2d ", core_if->nextep_seq[i]); ++ /* Update IN Endpoint Mismatch Count by active IN NP EP count + 1 */ ++ dcfg.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->dcfg); ++ dcfg.b.epmscnt = 2; ++ DWC_WRITE_REG32(&dev_if->dev_global_regs->dcfg, dcfg.d32); ++ ++ DWC_DEBUGPL(DBG_CILV,"%s first_in_nextep_seq= %2d; nextep_seq[]:\n", ++ __func__, core_if->first_in_nextep_seq); ++ for (i=0; i <= core_if->dev_if->num_in_eps; i++) { ++ DWC_DEBUGPL(DBG_CILV, "%2d ", core_if->nextep_seq[i]); ++ } ++ DWC_DEBUGPL(DBG_CILV,"\n"); + } +- DWC_DEBUGPL(DBG_CILV,"\n"); +- } + +- /* Clear all pending Device Interrupts */ +- /** @todo - if the condition needed to be checked +- * or in any case all pending interrutps should be cleared? +- */ +- if (core_if->multiproc_int_enable) { +- for (i = 0; i < core_if->dev_if->num_in_eps; ++i) { +- DWC_WRITE_REG32(&dev_if-> +- dev_global_regs->diepeachintmsk[i], 0); ++ /* Clear all pending Device Interrupts */ ++ /** @todo - if the condition needed to be checked ++ * or in any case all pending interrutps should be cleared? ++ */ ++ if (core_if->multiproc_int_enable) { ++ for (i = 0; i < core_if->dev_if->num_in_eps; ++i) { ++ DWC_WRITE_REG32(&dev_if-> ++ dev_global_regs->diepeachintmsk[i], 0); ++ } + } + + for (i = 0; i < core_if->dev_if->num_out_eps; ++i) { +@@ -1878,9 +1887,35 @@ + depctl_data_t depctl; + depctl.d32 = DWC_READ_REG32(&dev_if->out_ep_regs[i]->doepctl); + if (depctl.b.epena) { ++ dctl_data_t dctl = {.d32 = 0 }; ++ gintmsk_data_t gintsts = {.d32 = 0 }; ++ doepint_data_t doepint = {.d32 = 0 }; ++ dctl.b.sgoutnak = 1; ++ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, 0, dctl.d32); ++ do { ++ dwc_udelay(10); ++ gintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts); ++ } while (!gintsts.b.goutnakeff); ++ gintsts.d32 = 0; ++ gintsts.b.goutnakeff = 1; ++ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32); ++ + depctl.d32 = 0; + depctl.b.epdis = 1; + depctl.b.snak = 1; ++ DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[i]->doepctl, depctl.d32); ++ do { ++ dwc_udelay(10); ++ doepint.d32 = DWC_READ_REG32(&core_if->dev_if-> ++ out_ep_regs[i]->doepint); ++ } while (!doepint.b.epdisabled); ++ ++ doepint.b.epdisabled = 1; ++ DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[i]->doepint, doepint.d32); ++ ++ dctl.d32 = 0; ++ dctl.b.cgoutnak = 1; ++ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, 0, dctl.d32); + } else { + depctl.d32 = 0; + } +@@ -1927,9 +1962,8 @@ + diepmsk_data_t msk = {.d32 = 0 }; + msk.b.txfifoundrn = 1; + if (core_if->multiproc_int_enable) { +- DWC_MODIFY_REG32(&dev_if-> +- dev_global_regs->diepeachintmsk[0], +- msk.d32, msk.d32); ++ DWC_MODIFY_REG32(&dev_if->dev_global_regs-> ++ diepeachintmsk[0], msk.d32, msk.d32); + } else { + DWC_MODIFY_REG32(&dev_if->dev_global_regs->diepmsk, + msk.d32, msk.d32); +@@ -2125,7 +2159,8 @@ + DWC_DEBUGPL(DBG_CIL, "new hptxfsiz=%08x\n", + DWC_READ_REG32(&global_regs->hptxfsiz)); + +- if (core_if->en_multiple_tx_fifo) { ++ if (core_if->en_multiple_tx_fifo ++ && core_if->snpsid <= OTG_CORE_REV_2_94a) { + /* Global DFIFOCFG calculation for Host mode - include RxFIFO, NPTXFIFO and HPTXFIFO */ + gdfifocfg.d32 = DWC_READ_REG32(&global_regs->gdfifocfg); + rxfsiz = (DWC_READ_REG32(&global_regs->grxfsiz) & 0x0000ffff); +@@ -2624,26 +2659,26 @@ + /* Put the sate to 2 as it was time outed */ + xfer_info->state = 2; + +- dctl.d32 = DWC_READ_REG32(&xfer_info->core_if-> +- dev_if->dev_global_regs->dctl); +- gintsts.d32 = DWC_READ_REG32(&xfer_info->core_if-> +- core_global_regs->gintsts); +- gintmsk.d32 = DWC_READ_REG32(&xfer_info->core_if-> +- core_global_regs->gintmsk); ++ dctl.d32 = ++ DWC_READ_REG32(&xfer_info->core_if->dev_if->dev_global_regs->dctl); ++ gintsts.d32 = ++ DWC_READ_REG32(&xfer_info->core_if->core_global_regs->gintsts); ++ gintmsk.d32 = ++ DWC_READ_REG32(&xfer_info->core_if->core_global_regs->gintmsk); + + if (!gintmsk.b.goutnakeff) { + /* Unmask it */ + gintmsk.b.goutnakeff = 1; +- DWC_WRITE_REG32(&xfer_info->core_if-> +- core_global_regs->gintmsk, gintmsk.d32); ++ DWC_WRITE_REG32(&xfer_info->core_if->core_global_regs->gintmsk, ++ gintmsk.d32); + + } + + if (!gintsts.b.goutnakeff) { + dctl.b.sgoutnak = 1; + } +- DWC_WRITE_REG32(&xfer_info->core_if->dev_if-> +- dev_global_regs->dctl, dctl.d32); ++ DWC_WRITE_REG32(&xfer_info->core_if->dev_if->dev_global_regs->dctl, ++ dctl.d32); + + } + +@@ -3149,11 +3184,20 @@ + */ + void dwc_otg_read_setup_packet(dwc_otg_core_if_t * core_if, uint32_t * dest) + { ++ device_grxsts_data_t status; + /* Get the 8 bytes of a setup transaction data */ + + /* Pop 2 DWORDS off the receive data FIFO into memory */ + dest[0] = DWC_READ_REG32(core_if->data_fifo[0]); + dest[1] = DWC_READ_REG32(core_if->data_fifo[0]); ++ if (core_if->snpsid >= OTG_CORE_REV_3_00a) { ++ status.d32 = ++ DWC_READ_REG32(&core_if->core_global_regs->grxstsp); ++ DWC_DEBUGPL(DBG_ANY, ++ "EP:%d BCnt:%d " "pktsts:%x Frame:%d(0x%0x)\n", ++ status.b.epnum, status.b.bcnt, status.b.pktsts, ++ status.b.fn, status.b.fn); ++ } + } + + /** +@@ -3172,6 +3216,7 @@ + depctl_data_t doepctl; + dctl_data_t dctl = {.d32 = 0 }; + ++ ep->stp_rollover = 0; + /* Read the Device Status and Endpoint 0 Control registers */ + dsts.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->dsts); + diepctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[0]->diepctl); +@@ -3192,9 +3237,10 @@ + DWC_WRITE_REG32(&dev_if->in_ep_regs[0]->diepctl, diepctl.d32); + + /* Enable OUT EP for receive */ ++ if (core_if->snpsid <= OTG_CORE_REV_2_94a) { + doepctl.b.epena = 1; + DWC_WRITE_REG32(&dev_if->out_ep_regs[0]->doepctl, doepctl.d32); +- ++ } + #ifdef VERBOSE + DWC_DEBUGPL(DBG_PCDV, "doepctl0=%0x\n", + DWC_READ_REG32(&dev_if->out_ep_regs[0]->doepctl)); +@@ -3271,10 +3317,12 @@ + dcfg.b.epmscnt++; + DWC_WRITE_REG32(&dev_if->dev_global_regs->dcfg, dcfg.d32); + +- DWC_DEBUGPL(DBG_PCDV,"%s first_in_nextep_seq= %2d; nextep_seq[]:\n", ++ DWC_DEBUGPL(DBG_PCDV, ++ "%s first_in_nextep_seq= %2d; nextep_seq[]:\n", + __func__, core_if->first_in_nextep_seq); + for (i=0; i <= core_if->dev_if->num_in_eps; i++) { +- DWC_DEBUGPL(DBG_PCDV, "%2d\n", core_if->nextep_seq[i]); ++ DWC_DEBUGPL(DBG_PCDV, "%2d\n", ++ core_if->nextep_seq[i]); + } + + } +@@ -3341,8 +3389,7 @@ + 0, daintmsk.d32); + } else { + if (ep->type == DWC_OTG_EP_TYPE_ISOC) { +- if (ep->is_in) +- { ++ if (ep->is_in) { + diepmsk_data_t diepmsk = {.d32 = 0 }; + diepmsk.b.nak = 1; + DWC_MODIFY_REG32(&dev_if->dev_global_regs->diepmsk, 0, diepmsk.d32); +@@ -3410,11 +3457,14 @@ + core_if->first_in_nextep_seq = i; + core_if->nextep_seq[ep->num] = 0xff; + depctl.b.nextep = 0; +- dcfg.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg); ++ dcfg.d32 = ++ DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg); + dcfg.b.epmscnt--; +- DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dcfg, dcfg.d32); ++ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dcfg, ++ dcfg.d32); + +- DWC_DEBUGPL(DBG_PCDV,"%s first_in_nextep_seq= %2d; nextep_seq[]:\n", ++ DWC_DEBUGPL(DBG_PCDV, ++ "%s first_in_nextep_seq= %2d; nextep_seq[]:\n", + __func__, core_if->first_in_nextep_seq); + for (i=0; i <= core_if->dev_if->num_in_eps; i++) { + DWC_DEBUGPL(DBG_PCDV, "%2d\n", core_if->nextep_seq[i]); +@@ -3429,43 +3479,47 @@ + + DWC_WRITE_REG32(addr, depctl.d32); + depctl.d32 = DWC_READ_REG32(addr); +- if (core_if->dma_enable && ep->type == DWC_OTG_EP_TYPE_ISOC && depctl.b.epena) +- { ++ if (core_if->dma_enable && ep->type == DWC_OTG_EP_TYPE_ISOC ++ && depctl.b.epena) { + depctl_data_t depctl = {.d32 = 0}; +- if (ep->is_in) +- { ++ if (ep->is_in) { + diepint_data_t diepint = {.d32 = 0}; + + depctl.b.snak = 1; +- DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[ep->num]->diepctl, depctl.d32); +- do +- { ++ DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[ep->num]-> ++ diepctl, depctl.d32); ++ do { + dwc_udelay(10); +- diepint.d32 = DWC_READ_REG32(&core_if->dev_if-> +- in_ep_regs[ep->num]->diepint); ++ diepint.d32 = ++ DWC_READ_REG32(&core_if-> ++ dev_if->in_ep_regs[ep->num]-> ++ diepint); + } while (!diepint.b.inepnakeff); + diepint.b.inepnakeff = 1; +- DWC_WRITE_REG32(&core_if->dev_if-> +- in_ep_regs[ep->num]->diepint, diepint.d32); ++ DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[ep->num]-> ++ diepint, diepint.d32); + depctl.d32 = 0; + depctl.b.epdis = 1; +- DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[ep->num]->diepctl, depctl.d32); +- do +- { ++ DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[ep->num]-> ++ diepctl, depctl.d32); ++ do { + dwc_udelay(10); +- diepint.d32 = DWC_READ_REG32(&core_if->dev_if-> +- in_ep_regs[ep->num]->diepint); ++ diepint.d32 = ++ DWC_READ_REG32(&core_if-> ++ dev_if->in_ep_regs[ep->num]-> ++ diepint); + } while (!diepint.b.epdisabled); + diepint.b.epdisabled = 1; +- DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[ep->num]->diepint, diepint.d32); ++ DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[ep->num]-> ++ diepint, diepint.d32); + } else { + dctl_data_t dctl = {.d32 = 0}; + gintmsk_data_t gintsts = {.d32 = 0}; + doepint_data_t doepint = {.d32 = 0}; + dctl.b.sgoutnak = 1; +- DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, 0, dctl.d32); +- do +- { ++ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs-> ++ dctl, 0, dctl.d32); ++ do { + dwc_udelay(10); + gintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts); + } while (!gintsts.b.goutnakeff); +@@ -3552,8 +3606,7 @@ + (total_len % maxxfer_local); + } else + xfer_est = ep->desc_cnt * maxxfer_local; +- } +- else ++ } else + xfer_est = total_len; + offset = 0; + for (i = 0; i < ep->desc_cnt; ++i) { +@@ -3626,8 +3679,7 @@ + DWC_DEBUGPL(DBG_PCDV, "b4 dtxfsts[%d]=0x%08x\n", epnum, txstatus.d32); + + while (txstatus.b.txfspcavail > dwords && +- dwc_ep->xfer_count < dwc_ep->xfer_len && +- dwc_ep->xfer_len != 0) { ++ dwc_ep->xfer_count < dwc_ep->xfer_len && dwc_ep->xfer_len != 0) { + /* Write the FIFO */ + dwc_otg_ep_write_packet(core_if, dwc_ep, 0); + +@@ -3681,8 +3733,7 @@ + DWC_READ_REG32(&core_if->core_global_regs->gnptxsts); + + if (core_if->en_multiple_tx_fifo == 0 +- && gtxstatus.b.nptxqspcavail == 0 +- && !core_if->dma_enable) { ++ && gtxstatus.b.nptxqspcavail == 0 && !core_if->dma_enable) { + #ifdef DEBUG + DWC_PRINTF("TX Queue Full (0x%0x)\n", gtxstatus.d32); + #endif +@@ -3778,15 +3829,14 @@ + if (!core_if->core_params->en_multiple_tx_fifo && core_if->dma_enable) + depctl.b.nextep = core_if->nextep_seq[ep->num]; + +- if (ep->type == DWC_OTG_EP_TYPE_ISOC) +- { ++ if (ep->type == DWC_OTG_EP_TYPE_ISOC) { + dsts_data_t dsts = {.d32 = 0}; + if (ep->bInterval == 1) { + dsts.d32 = +- DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts); ++ DWC_READ_REG32(&core_if->dev_if-> ++ dev_global_regs->dsts); + ep->frame_num = dsts.b.soffn + ep->bInterval; +- if (ep->frame_num > 0x3FFF) +- { ++ if (ep->frame_num > 0x3FFF) { + ep->frm_overrun = 1; + ep->frame_num &= 0x3FFF; + } else +@@ -3888,15 +3938,14 @@ + DWC_WRITE_REG32(&out_regs->doeptsiz, deptsiz.d32); + } + +- if (ep->type == DWC_OTG_EP_TYPE_ISOC) +- { ++ if (ep->type == DWC_OTG_EP_TYPE_ISOC) { + dsts_data_t dsts = {.d32 = 0}; + if (ep->bInterval == 1) { + dsts.d32 = +- DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts); ++ DWC_READ_REG32(&core_if->dev_if-> ++ dev_global_regs->dsts); + ep->frame_num = dsts.b.soffn + ep->bInterval; +- if (ep->frame_num > 0x3FFF) +- { ++ if (ep->frame_num > 0x3FFF) { + ep->frm_overrun = 1; + ep->frame_num &= 0x3FFF; + } else +@@ -3920,11 +3969,10 @@ + DWC_READ_REG32(&out_regs->doepctl), + DWC_READ_REG32(&out_regs->doeptsiz)); + DWC_DEBUGPL(DBG_PCD, "DAINTMSK=%08x GINTMSK=%08x\n", +- DWC_READ_REG32(&core_if->dev_if-> +- dev_global_regs->daintmsk), +- DWC_READ_REG32(&core_if-> +- core_global_regs->gintmsk)); +- ++ DWC_READ_REG32(&core_if->dev_if->dev_global_regs-> ++ daintmsk), ++ DWC_READ_REG32(&core_if->core_global_regs-> ++ gintmsk)); + + /* Timer is scheduling only for out bulk transfers for + * "Device DDMA OUT NAK Enhancement" feature to inform user +@@ -4075,9 +4123,19 @@ + + gnptxsts_data_t gtxstatus; + ++ if (core_if->snpsid >= OTG_CORE_REV_3_00a) { ++ depctl.d32 = DWC_READ_REG32(&in_regs->diepctl); ++ if (depctl.b.epena) ++ return; ++ } ++ + gtxstatus.d32 = + DWC_READ_REG32(&core_if->core_global_regs->gnptxsts); + ++ /* If dedicated FIFO every time flush fifo before enable ep*/ ++ if (core_if->en_multiple_tx_fifo && core_if->snpsid >= OTG_CORE_REV_3_00a) ++ dwc_otg_flush_tx_fifo(core_if, ep->tx_fifo_num); ++ + if (core_if->en_multiple_tx_fifo == 0 + && gtxstatus.b.nptxqspcavail == 0 + && !core_if->dma_enable) { +@@ -4194,6 +4252,8 @@ + /* Zero Length Packet */ + deptsiz.b.xfersize = ep->maxpacket; + deptsiz.b.pktcnt = 1; ++ if (core_if->snpsid >= OTG_CORE_REV_3_00a) ++ deptsiz.b.supcnt = 3; + + DWC_DEBUGPL(DBG_PCDV, "len=%d xfersize=%d pktcnt=%d\n", + ep->xfer_len, deptsiz.b.xfersize, deptsiz.b.pktcnt); +@@ -4210,6 +4270,10 @@ + + /** DMA Descriptor Setup */ + dma_desc->status.b.bs = BS_HOST_BUSY; ++ if (core_if->snpsid >= OTG_CORE_REV_3_00a) { ++ dma_desc->status.b.mtrf = 0; ++ dma_desc->status.b.sr = 0; ++ } + dma_desc->status.b.l = 1; + dma_desc->status.b.ioc = 1; + dma_desc->status.b.bytes = ep->maxpacket; +@@ -4219,8 +4283,8 @@ + + /** DOEPDMA0 Register write */ + DWC_WRITE_REG32(&out_regs->doepdma, +- core_if-> +- dev_if->dma_out_desc_addr); ++ core_if->dev_if-> ++ dma_out_desc_addr); + } + } else { + DWC_WRITE_REG32(&out_regs->doeptsiz, deptsiz.d32); +@@ -4630,14 +4694,14 @@ + + DWC_PRINTF("Device Global Registers\n"); + addr = &core_if->dev_if->dev_global_regs->dcfg; +- DWC_PRINTF("DCFG @0x%08lX : 0x%08X\n", (unsigned long) addr, +- DWC_READ_REG32(addr)); ++ DWC_PRINTF("DCFG @0x%08lX : 0x%08X\n", ++ (unsigned long)addr, DWC_READ_REG32(addr)); + addr = &core_if->dev_if->dev_global_regs->dctl; +- DWC_PRINTF("DCTL @0x%08lX : 0x%08X\n", (unsigned long) addr, +- DWC_READ_REG32(addr)); ++ DWC_PRINTF("DCTL @0x%08lX : 0x%08X\n", ++ (unsigned long)addr, DWC_READ_REG32(addr)); + addr = &core_if->dev_if->dev_global_regs->dsts; +- DWC_PRINTF("DSTS @0x%08lX : 0x%08X\n", (unsigned long) addr, +- DWC_READ_REG32(addr)); ++ DWC_PRINTF("DSTS @0x%08lX : 0x%08X\n", ++ (unsigned long)addr, DWC_READ_REG32(addr)); + addr = &core_if->dev_if->dev_global_regs->diepmsk; + DWC_PRINTF("DIEPMSK @0x%08lX : 0x%08X\n", (unsigned long)addr, + DWC_READ_REG32(addr)); +@@ -4692,8 +4756,8 @@ + + for (i = 0; i <= core_if->dev_if->num_in_eps; i++) { + addr = +- &core_if->dev_if->dev_global_regs-> +- diepeachintmsk[i]; ++ &core_if->dev_if-> ++ dev_global_regs->diepeachintmsk[i]; + DWC_PRINTF("DIEPEACHINTMSK[%d] @0x%08lX : 0x%08X\n", + i, (unsigned long)addr, + DWC_READ_REG32(addr)); +@@ -4701,8 +4765,8 @@ + + for (i = 0; i <= core_if->dev_if->num_out_eps; i++) { + addr = +- &core_if->dev_if->dev_global_regs-> +- doepeachintmsk[i]; ++ &core_if->dev_if-> ++ dev_global_regs->doepeachintmsk[i]; + DWC_PRINTF("DOEPEACHINTMSK[%d] @0x%08lX : 0x%08X\n", + i, (unsigned long)addr, + DWC_READ_REG32(addr)); +@@ -5150,8 +5214,8 @@ + + dwords = (len + 3) / 4; + txstatus.d32 = +- DWC_READ_REG32(&core_if->dev_if-> +- in_ep_regs[ep->num]->dtxfsts); ++ DWC_READ_REG32(&core_if->dev_if->in_ep_regs[ep->num]-> ++ dtxfsts); + DWC_DEBUGPL(DBG_PCDV, "dtxfsts[%d]=0x%08x\n", ep->num, + txstatus.d32); + } +@@ -5207,13 +5271,14 @@ + (ep->xfer_len + (ep->maxpacket - 1)) / ep->maxpacket; + deptsiz.b.xfersize = deptsiz.b.pktcnt * ep->maxpacket; + +- DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[ep->num]-> +- doeptsiz, deptsiz.d32); ++ DWC_WRITE_REG32(&core_if->dev_if-> ++ out_ep_regs[ep->num]->doeptsiz, deptsiz.d32); + + if (core_if->dma_enable) { + DWC_WRITE_REG32(& +- (core_if->dev_if->out_ep_regs[ep->num]-> +- doepdma), (uint32_t) ep->dma_addr); ++ (core_if->dev_if-> ++ out_ep_regs[ep->num]->doepdma), ++ (uint32_t) ep->dma_addr); + } + } + +@@ -5715,8 +5780,7 @@ + return -DWC_E_INVALID; + } + +- if (val > +- ((core_if->hptxfsiz.d32)>> 16)) { ++ if (val > ((core_if->hptxfsiz.d32) >> 16)) { + if (dwc_otg_param_initialized + (core_if->core_params->host_perio_tx_fifo_size)) { + DWC_ERROR +@@ -6453,8 +6517,10 @@ + { + int retval = 0; + int valid = 1; ++ hwcfg4_data_t hwcfg4 = {.d32 = 0 }; ++ hwcfg4.d32 = DWC_READ_REG32(&core_if->core_global_regs->ghwcfg4); + +- if (DWC_OTG_PARAM_TEST(val, 0, 2)) { ++ if (DWC_OTG_PARAM_TEST(val, 0, 3)) { + DWC_WARN("`%d' invalid for parameter `power_down'\n", val); + DWC_WARN("power_down must be 0 - 2\n"); + return -DWC_E_INVALID; +@@ -6463,6 +6529,11 @@ + if ((val == 2) && (core_if->snpsid < OTG_CORE_REV_2_91a)) { + valid = 0; + } ++ if ((val == 3) ++ && ((core_if->snpsid < OTG_CORE_REV_3_00a) ++ || (hwcfg4.b.xhiber == 0))) { ++ valid = 0; ++ } + if (valid == 0) { + if (dwc_otg_param_initialized(core_if->core_params->power_down)) { + DWC_ERROR +Index: linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_cil.h +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/dwc_otg_cil.h 2013-07-26 19:35:17.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_cil.h 2013-07-26 19:35:46.000000000 +0000 +@@ -1,8 +1,8 @@ + /* ========================================================================== + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_cil.h $ +- * $Revision: #122 $ +- * $Date: 2011/10/24 $ +- * $Change: 1871160 $ ++ * $Revision: #123 $ ++ * $Date: 2012/08/10 $ ++ * $Change: 2047372 $ + * + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless +@@ -74,6 +74,7 @@ + #define OTG_CORE_REV_2_92a 0x4F54292A + #define OTG_CORE_REV_2_93a 0x4F54293A + #define OTG_CORE_REV_2_94a 0x4F54294A ++#define OTG_CORE_REV_3_00a 0x4F54300A + + /** + * Information for each ISOC packet. +@@ -146,6 +147,9 @@ + /** stall clear flag */ + unsigned stall_clear_flag:1; + ++ /** SETUP pkt cnt rollover flag for EP0 out*/ ++ unsigned stp_rollover; ++ + #ifdef DWC_UTE_CFI + /* The buffer mode */ + data_buffer_mode_e buff_mode; +@@ -764,6 +768,8 @@ + uint32_t gdfifocfg_local; + uint32_t dtxfsiz_local[MAX_EPS_CHANNELS]; + uint32_t gpwrdn_local; ++ uint32_t xhib_pcgcctl; ++ uint32_t xhib_gpwrdn; + }; + + struct dwc_otg_host_regs_backup { +@@ -964,6 +970,9 @@ + /** hibernation/suspend flag */ + int hibernation_suspend; + ++ /** Device mode extended hibernation flag */ ++ int xhib; ++ + /** OTG revision supported */ + uint32_t otg_ver; + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_cil_intr.c +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/dwc_otg_cil_intr.c 2013-07-26 19:34:44.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_cil_intr.c 2013-07-26 19:35:46.000000000 +0000 +@@ -1,8 +1,8 @@ + /* ========================================================================== + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_cil_intr.c $ +- * $Revision: #31 $ +- * $Date: 2011/10/24 $ +- * $Change: 1871286 $ ++ * $Revision: #32 $ ++ * $Date: 2012/08/10 $ ++ * $Change: 2047372 $ + * + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless +@@ -168,6 +168,10 @@ + /* Print statements during the HNP interrupt handling + * can cause it to fail.*/ + gotgctl.d32 = DWC_READ_REG32(&global_regs->gotgctl); ++ /* WA for 3.00a- HW is not setting cur_mode, even sometimes ++ * this does not help*/ ++ if (core_if->snpsid >= OTG_CORE_REV_3_00a) ++ dwc_udelay(100); + if (gotgctl.b.hstnegscs) { + if (dwc_otg_is_host_mode(core_if)) { + core_if->op_state = B_HOST; +@@ -443,8 +447,8 @@ + if (dwc_otg_is_device_mode(core_if)) { + dctl_data_t dctl = {.d32 = 0 }; + DWC_DEBUGPL(DBG_PCD, "DSTS=0x%0x\n", +- DWC_READ_REG32(&core_if->dev_if-> +- dev_global_regs->dsts)); ++ DWC_READ_REG32(&core_if->dev_if->dev_global_regs-> ++ dsts)); + if (core_if->lx_state == DWC_OTG_L2) { + #ifdef PARTIAL_POWER_DOWN + if (core_if->hwcfg4.b.power_optimiz) { +@@ -466,8 +470,8 @@ + #endif + /* Clear the Remote Wakeup Signaling */ + dctl.b.rmtwkupsig = 1; +- DWC_MODIFY_REG32(&core_if->dev_if-> +- dev_global_regs->dctl, dctl.d32, 0); ++ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs-> ++ dctl, dctl.d32, 0); + + DWC_SPINUNLOCK(core_if->lock); + if (core_if->pcd_cb && core_if->pcd_cb->resume_wakeup) { +@@ -611,8 +615,7 @@ + + DWC_DEBUGPL(DBG_ANY, "%s called\n", __FUNCTION__); + gpwrdn_temp.d32 = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn); +- if (core_if->power_down == 2) +- { ++ if (core_if->power_down == 2) { + if (!core_if->hibernation_suspend) { + DWC_PRINTF("Already exited from Hibernation\n"); + return 1; +@@ -674,8 +677,7 @@ + } + } + +- if (core_if->adp_enable) +- { ++ if (core_if->adp_enable) { + uint8_t is_host = 0; + DWC_SPINUNLOCK(core_if->lock); + /* Change the core_if's lock to hcd/pcd lock depend on mode? */ +@@ -978,16 +980,17 @@ + /* Enable Power Down Logic */ + gpwrdn.b.pmuintsel = 1; + gpwrdn.b.pmuactv = 1; +- DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32); ++ DWC_MODIFY_REG32(&core_if->core_global_regs-> ++ gpwrdn, 0, gpwrdn.d32); + dwc_otg_adp_probe_start(core_if); + + /* Power off the core */ + if (core_if->power_down == 2) { + gpwrdn.d32 = 0; + gpwrdn.b.pwrdnswtch = 1; +- DWC_MODIFY_REG32(&core_if-> +- core_global_regs-> +- gpwrdn, gpwrdn.d32, 0); ++ DWC_MODIFY_REG32 ++ (&core_if->core_global_regs->gpwrdn, ++ gpwrdn.d32, 0); + } + } + } +@@ -1141,6 +1144,49 @@ + + return 1; + } ++ } else if (core_if->power_down == 3) { ++ pcgcctl_data_t pcgcctl = {.d32 = 0 }; ++ dcfg.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg); ++ DWC_DEBUGPL(DBG_ANY, "lx_state = %08x\n",core_if->lx_state); ++ DWC_DEBUGPL(DBG_ANY, " device address = %08d\n",dcfg.b.devaddr); ++ ++ if (core_if->lx_state != DWC_OTG_L3 && dcfg.b.devaddr) { ++ DWC_DEBUGPL(DBG_ANY, "Start entering to extended hibernation\n"); ++ core_if->xhib = 1; ++ ++ /* Clear interrupt in gintsts */ ++ gintsts.d32 = 0; ++ gintsts.b.usbsuspend = 1; ++ DWC_WRITE_REG32(&core_if->core_global_regs-> ++ gintsts, gintsts.d32); ++ ++ dwc_otg_save_global_regs(core_if); ++ dwc_otg_save_dev_regs(core_if); ++ ++ /* Wait for 10 PHY clocks */ ++ dwc_udelay(10); ++ ++ /* Program GPIO register while entering to xHib */ ++ DWC_WRITE_REG32(&core_if->core_global_regs->ggpio, 0x1); ++ ++ pcgcctl.b.enbl_extnd_hiber = 1; ++ DWC_MODIFY_REG32(core_if->pcgcctl, 0, pcgcctl.d32); ++ DWC_MODIFY_REG32(core_if->pcgcctl, 0, pcgcctl.d32); ++ ++ pcgcctl.d32 = 0; ++ pcgcctl.b.extnd_hiber_pwrclmp = 1; ++ DWC_MODIFY_REG32(core_if->pcgcctl, 0, pcgcctl.d32); ++ ++ pcgcctl.d32 = 0; ++ pcgcctl.b.extnd_hiber_switch = 1; ++ core_if->gr_backup->xhib_gpwrdn = DWC_READ_REG32(&core_if->core_global_regs->gpwrdn); ++ core_if->gr_backup->xhib_pcgcctl = DWC_READ_REG32(core_if->pcgcctl) | pcgcctl.d32; ++ DWC_MODIFY_REG32(core_if->pcgcctl, 0, pcgcctl.d32); ++ ++ DWC_DEBUGPL(DBG_ANY, "Finished entering to extended hibernation\n"); ++ ++ return 1; ++ } + } + } else { + if (core_if->op_state == A_PERIPHERAL) { +@@ -1165,6 +1211,70 @@ + return 1; + } + ++static int32_t dwc_otg_handle_xhib_exit_intr(dwc_otg_core_if_t * core_if) ++{ ++ gpwrdn_data_t gpwrdn = {.d32 = 0 }; ++ pcgcctl_data_t pcgcctl = {.d32 = 0 }; ++ gahbcfg_data_t gahbcfg = {.d32 = 0 }; ++ ++ dwc_udelay(10); ++ ++ /* Program GPIO register while entering to xHib */ ++ DWC_WRITE_REG32(&core_if->core_global_regs->ggpio, 0x0); ++ ++ pcgcctl.d32 = core_if->gr_backup->xhib_pcgcctl; ++ pcgcctl.b.extnd_hiber_pwrclmp = 0; ++ DWC_WRITE_REG32(core_if->pcgcctl, pcgcctl.d32); ++ dwc_udelay(10); ++ ++ gpwrdn.d32 = core_if->gr_backup->xhib_gpwrdn; ++ gpwrdn.b.restore = 1; ++ DWC_WRITE_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32); ++ dwc_udelay(10); ++ ++ restore_lpm_i2c_regs(core_if); ++ ++ pcgcctl.d32 = core_if->gr_backup->pcgcctl_local & (0x3FFFF << 14); ++ pcgcctl.b.max_xcvrselect = 1; ++ pcgcctl.b.ess_reg_restored = 0; ++ pcgcctl.b.extnd_hiber_switch = 0; ++ pcgcctl.b.extnd_hiber_pwrclmp = 0; ++ pcgcctl.b.enbl_extnd_hiber = 1; ++ DWC_WRITE_REG32(core_if->pcgcctl, pcgcctl.d32); ++ ++ gahbcfg.d32 = core_if->gr_backup->gahbcfg_local; ++ gahbcfg.b.glblintrmsk = 1; ++ DWC_WRITE_REG32(&core_if->core_global_regs->gahbcfg, gahbcfg.d32); ++ ++ DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF); ++ DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, 0x1 << 16); ++ ++ DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, ++ core_if->gr_backup->gusbcfg_local); ++ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dcfg, ++ core_if->dr_backup->dcfg); ++ ++ pcgcctl.d32 = 0; ++ pcgcctl.d32 = core_if->gr_backup->pcgcctl_local & (0x3FFFF << 14); ++ pcgcctl.b.max_xcvrselect = 1; ++ pcgcctl.d32 |= 0x608; ++ DWC_WRITE_REG32(core_if->pcgcctl, pcgcctl.d32); ++ dwc_udelay(10); ++ ++ pcgcctl.d32 = 0; ++ pcgcctl.d32 = core_if->gr_backup->pcgcctl_local & (0x3FFFF << 14); ++ pcgcctl.b.max_xcvrselect = 1; ++ pcgcctl.b.ess_reg_restored = 1; ++ pcgcctl.b.enbl_extnd_hiber = 1; ++ pcgcctl.b.rstpdwnmodule = 1; ++ pcgcctl.b.restoremode = 1; ++ DWC_WRITE_REG32(core_if->pcgcctl, pcgcctl.d32); ++ ++ DWC_DEBUGPL(DBG_ANY, "%s called\n", __FUNCTION__); ++ ++ return 1; ++} ++ + #ifdef CONFIG_USB_DWC_OTG_LPM + /** + * This function hadles LPM transaction received interrupt. +@@ -1286,6 +1396,16 @@ + if (core_if->lock) + DWC_SPINLOCK(core_if->lock); + ++ if (core_if->power_down == 3 && core_if->xhib == 1) { ++ DWC_DEBUGPL(DBG_ANY, "Exiting from xHIB state\n"); ++ retval |= dwc_otg_handle_xhib_exit_intr(core_if); ++ core_if->xhib = 2; ++ if (core_if->lock) ++ DWC_SPINUNLOCK(core_if->lock); ++ ++ return retval; ++ } ++ + if (core_if->hibernation_suspend <= 0) { + gintsts.d32 = dwc_otg_read_common_intr(core_if); + +@@ -1296,7 +1416,8 @@ + retval |= dwc_otg_handle_otg_intr(core_if); + } + if (gintsts.b.conidstschng) { +- retval |= dwc_otg_handle_conn_id_status_change_intr(core_if); ++ retval |= ++ dwc_otg_handle_conn_id_status_change_intr(core_if); + } + if (gintsts.b.disconnect) { + retval |= dwc_otg_handle_disconnect_intr(core_if); +@@ -1319,6 +1440,57 @@ + gintsts.d32 = 0; + if (core_if->power_down == 2) + core_if->hibernation_suspend = -1; ++ else if (core_if->power_down == 3 && core_if->xhib == 2) { ++ gpwrdn_data_t gpwrdn = {.d32 = 0 }; ++ pcgcctl_data_t pcgcctl = {.d32 = 0 }; ++ dctl_data_t dctl = {.d32 = 0 }; ++ ++ DWC_WRITE_REG32(&core_if->core_global_regs-> ++ gintsts, 0xFFFFFFFF); ++ ++ DWC_DEBUGPL(DBG_ANY, ++ "RESTORE DONE generated\n"); ++ ++ gpwrdn.b.restore = 1; ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0); ++ dwc_udelay(10); ++ ++ pcgcctl.b.rstpdwnmodule = 1; ++ DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32, 0); ++ ++ DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, core_if->gr_backup->gusbcfg_local); ++ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dcfg, core_if->dr_backup->dcfg); ++ DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl, core_if->dr_backup->dctl); ++ dwc_udelay(50); ++ ++ dctl.b.pwronprgdone = 1; ++ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, 0, dctl.d32); ++ dwc_udelay(10); ++ ++ dwc_otg_restore_global_regs(core_if); ++ dwc_otg_restore_dev_regs(core_if, 0); ++ ++ dctl.d32 = 0; ++ dctl.b.pwronprgdone = 1; ++ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32, 0); ++ dwc_udelay(10); ++ ++ pcgcctl.d32 = 0; ++ pcgcctl.b.enbl_extnd_hiber = 1; ++ DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32, 0); ++ ++ /* The core will be in ON STATE */ ++ core_if->lx_state = DWC_OTG_L0; ++ core_if->xhib = 0; ++ ++ DWC_SPINUNLOCK(core_if->lock); ++ if (core_if->pcd_cb && core_if->pcd_cb->resume_wakeup) { ++ core_if->pcd_cb->resume_wakeup(core_if->pcd_cb->p); ++ } ++ DWC_SPINLOCK(core_if->lock); ++ ++ } ++ + gintsts.b.restoredone = 1; + DWC_WRITE_REG32(&core_if->core_global_regs->gintsts,gintsts.d32); + DWC_PRINTF(" --Restore done interrupt received-- \n"); +Index: linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_core_if.h +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/dwc_otg_core_if.h 2013-07-26 19:34:44.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_core_if.h 2013-07-26 19:35:46.000000000 +0000 +@@ -1,8 +1,8 @@ + /* ========================================================================== + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_core_if.h $ +- * $Revision: #12 $ +- * $Date: 2011/10/24 $ +- * $Change: 1871159 $ ++ * $Revision: #13 $ ++ * $Date: 2012/08/10 $ ++ * $Change: 2047372 $ + * + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless +Index: linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_driver.c +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/dwc_otg_driver.c 2013-07-26 19:35:16.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_driver.c 2013-07-26 19:35:46.000000000 +0000 +@@ -1,8 +1,8 @@ + /* ========================================================================== + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_driver.c $ +- * $Revision: #91 $ +- * $Date: 2011/10/24 $ +- * $Change: 1871159 $ ++ * $Revision: #92 $ ++ * $Date: 2012/08/10 $ ++ * $Change: 2047372 $ + * + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless +@@ -57,7 +57,7 @@ + #include "dwc_otg_pcd_if.h" + #include "dwc_otg_hcd_if.h" + +-#define DWC_DRIVER_VERSION "2.94b 27-OCT-2011 (rev 01-DEC-2011)" ++#define DWC_DRIVER_VERSION "3.00a 10-AUG-2012" + #define DWC_DRIVER_DESC "HS OTG USB Controller driver" + + bool microframe_schedule; +@@ -836,11 +836,12 @@ + /* + * Attempt to ensure this device is really a DWC_otg Controller. + * Read and verify the SNPSID register contents. The value should be +- * 0x45F42XXX, which corresponds to "OT2", as in "OTG version 2.XX". ++ * 0x45F42XXX or 0x45F42XXX, which corresponds to either "OT2" or "OTG3", ++ * as in "OTG version 2.XX" or "OTG version 3.XX". + */ + +- if ((dwc_otg_get_gsnpsid(dwc_otg_device->core_if) & 0xFFFFF000) != +- 0x4F542000) { ++ if (((dwc_otg_get_gsnpsid(dwc_otg_device->core_if) & 0xFFFFF000) != 0x4F542000) && ++ ((dwc_otg_get_gsnpsid(dwc_otg_device->core_if) & 0xFFFFF000) != 0x4F543000)) { + dev_err(&_dev->dev, "Bad value for SNPSID: 0x%08x\n", + dwc_otg_get_gsnpsid(dwc_otg_device->core_if)); + retval = -EINVAL; +Index: linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_pcd.c +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/dwc_otg_pcd.c 2013-07-26 19:34:44.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_pcd.c 2013-07-26 19:35:46.000000000 +0000 +@@ -1,8 +1,8 @@ + /* ========================================================================== + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_pcd.c $ +- * $Revision: #99 $ +- * $Date: 2011/10/24 $ +- * $Change: 1871160 $ ++ * $Revision: #101 $ ++ * $Date: 2012/08/10 $ ++ * $Change: 2047372 $ + * + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless +@@ -453,8 +453,8 @@ + fifosize_data_t txfifosize, rxfifosize; + + txfifosize.d32 = +- DWC_READ_REG32(&core_if->dev_if-> +- in_ep_regs[dwc_ep->num]->dtxfsts); ++ DWC_READ_REG32(&core_if->dev_if->in_ep_regs[dwc_ep->num]-> ++ dtxfsts); + rxfifosize.d32 = + DWC_READ_REG32(&core_if->core_global_regs->grxfsiz); + +@@ -574,15 +574,13 @@ + deptsiz.b.xfersize = ep->xfer_len; + deptsiz.b.pktcnt = + (ep->xfer_len - 1 + ep->maxpacket) / ep->maxpacket; +- DWC_WRITE_REG32(&core_if->dev_if-> +- in_ep_regs[ep->num]->dieptsiz, +- deptsiz.d32); ++ DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[ep->num]-> ++ dieptsiz, deptsiz.d32); + + /* Write the DMA register */ + DWC_WRITE_REG32(& +- (core_if->dev_if-> +- in_ep_regs[ep->num]->diepdma), +- (uint32_t) ep->dma_addr); ++ (core_if->dev_if->in_ep_regs[ep->num]-> ++ diepdma), (uint32_t) ep->dma_addr); + + } else { + deptsiz.b.pktcnt = +@@ -590,15 +588,13 @@ + ep->maxpacket; + deptsiz.b.xfersize = deptsiz.b.pktcnt * ep->maxpacket; + +- DWC_WRITE_REG32(&core_if->dev_if-> +- out_ep_regs[ep->num]->doeptsiz, +- deptsiz.d32); ++ DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[ep->num]-> ++ doeptsiz, deptsiz.d32); + + /* Write the DMA register */ + DWC_WRITE_REG32(& +- (core_if->dev_if-> +- out_ep_regs[ep->num]->doepdma), +- (uint32_t) ep->dma_addr); ++ (core_if->dev_if->out_ep_regs[ep->num]-> ++ doepdma), (uint32_t) ep->dma_addr); + + } + /** Enable endpoint, clear nak */ +@@ -636,11 +632,11 @@ + dwc_otg_iso_ep_start_buf_transfer(core_if, ep); + } else { + ep->cur_pkt_addr = +- (ep->proc_buf_num) ? ep-> +- xfer_buff1 : ep->xfer_buff0; ++ (ep->proc_buf_num) ? ep->xfer_buff1 : ep-> ++ xfer_buff0; + ep->cur_pkt_dma_addr = +- (ep->proc_buf_num) ? ep-> +- dma_addr1 : ep->dma_addr0; ++ (ep->proc_buf_num) ? ep->dma_addr1 : ep-> ++ dma_addr0; + dwc_otg_iso_ep_start_frm_transfer(core_if, ep); + } + } +@@ -1014,14 +1010,16 @@ + /* Power off the core */ + if (core_if->power_down == 2) { + gpwrdn.b.pwrdnswtch = 1; +- DWC_MODIFY_REG32(&core_if->core_global_regs-> +- gpwrdn, gpwrdn.d32, 0); ++ DWC_MODIFY_REG32(&core_if-> ++ core_global_regs->gpwrdn, ++ gpwrdn.d32, 0); + } + + gpwrdn.d32 = 0; + gpwrdn.b.pmuintsel = 1; + gpwrdn.b.pmuactv = 1; +- DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32); ++ DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, ++ gpwrdn.d32); + dwc_otg_adp_probe_start(core_if); + } else { + DWC_PRINTF("SRP Timeout BSESSVLD = 1\n"); +@@ -1180,19 +1178,18 @@ + + if (GET_CORE_IF(pcd)->dma_desc_enable) { + dev_if->setup_desc_addr[0] = +- dwc_otg_ep_alloc_desc_chain(&dev_if-> +- dma_setup_desc_addr[0], +- 1); ++ dwc_otg_ep_alloc_desc_chain ++ (&dev_if->dma_setup_desc_addr[0], 1); + dev_if->setup_desc_addr[1] = +- dwc_otg_ep_alloc_desc_chain(&dev_if-> +- dma_setup_desc_addr[1], +- 1); ++ dwc_otg_ep_alloc_desc_chain ++ (&dev_if->dma_setup_desc_addr[1], 1); + dev_if->in_desc_addr = +- dwc_otg_ep_alloc_desc_chain(&dev_if-> +- dma_in_desc_addr, 1); ++ dwc_otg_ep_alloc_desc_chain ++ (&dev_if->dma_in_desc_addr, 1); + dev_if->out_desc_addr = +- dwc_otg_ep_alloc_desc_chain(&dev_if-> +- dma_out_desc_addr, 1); ++ dwc_otg_ep_alloc_desc_chain ++ (&dev_if->dma_out_desc_addr, 1); ++ pcd->data_terminated = 0; + + if (dev_if->setup_desc_addr[0] == 0 + || dev_if->setup_desc_addr[1] == 0 +@@ -1200,31 +1197,21 @@ + || dev_if->out_desc_addr == 0) { + + if (dev_if->out_desc_addr) +- dwc_otg_ep_free_desc_chain(dev_if-> +- out_desc_addr, +- dev_if-> +- dma_out_desc_addr, +- 1); ++ dwc_otg_ep_free_desc_chain ++ (dev_if->out_desc_addr, ++ dev_if->dma_out_desc_addr, 1); + if (dev_if->in_desc_addr) +- dwc_otg_ep_free_desc_chain(dev_if-> +- in_desc_addr, +- dev_if-> +- dma_in_desc_addr, +- 1); ++ dwc_otg_ep_free_desc_chain ++ (dev_if->in_desc_addr, ++ dev_if->dma_in_desc_addr, 1); + if (dev_if->setup_desc_addr[1]) +- dwc_otg_ep_free_desc_chain(dev_if-> +- setup_desc_addr +- [1], +- dev_if-> +- dma_setup_desc_addr +- [1], 1); ++ dwc_otg_ep_free_desc_chain ++ (dev_if->setup_desc_addr[1], ++ dev_if->dma_setup_desc_addr[1], 1); + if (dev_if->setup_desc_addr[0]) +- dwc_otg_ep_free_desc_chain(dev_if-> +- setup_desc_addr +- [0], +- dev_if-> +- dma_setup_desc_addr +- [0], 1); ++ dwc_otg_ep_free_desc_chain ++ (dev_if->setup_desc_addr[0], ++ dev_if->dma_setup_desc_addr[0], 1); + + DWC_DMA_FREE(sizeof(*pcd->setup_pkt) * 5, + pcd->setup_pkt, +@@ -1550,20 +1537,23 @@ + } + + /* Calculating EP info controller base address */ +- if (ep->dwc_ep.tx_fifo_num && GET_CORE_IF(pcd)->en_multiple_tx_fifo) { ++ if (ep->dwc_ep.tx_fifo_num ++ && GET_CORE_IF(pcd)->en_multiple_tx_fifo) { + gdfifocfg.d32 = +- DWC_READ_REG32(&GET_CORE_IF(pcd)->core_global_regs-> +- gdfifocfg); ++ DWC_READ_REG32(&GET_CORE_IF(pcd)-> ++ core_global_regs->gdfifocfg); + gdfifocfgbase.d32 = gdfifocfg.d32 >> 16; + dptxfsiz.d32 = + (DWC_READ_REG32 +- (&GET_CORE_IF(pcd)-> +- core_global_regs->dtxfsiz[ep->dwc_ep. +- tx_fifo_num-1]) >> 16); ++ (&GET_CORE_IF(pcd)->core_global_regs-> ++ dtxfsiz[ep->dwc_ep.tx_fifo_num - 1]) >> 16); + gdfifocfg.b.epinfobase = + gdfifocfgbase.d32 + dptxfsiz.d32; +- DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs-> +- gdfifocfg, gdfifocfg.d32); ++ if (GET_CORE_IF(pcd)->snpsid <= OTG_CORE_REV_2_94a) { ++ DWC_WRITE_REG32(&GET_CORE_IF(pcd)-> ++ core_global_regs->gdfifocfg, ++ gdfifocfg.d32); ++ } + } + } + /* Set initial data PID. */ +@@ -1643,8 +1633,7 @@ + dwc_otg_request_nuke(ep); + + dwc_otg_ep_deactivate(GET_CORE_IF(pcd), &ep->dwc_ep); +- if (pcd->core_if->core_params->dev_out_nak) +- { ++ if (pcd->core_if->core_params->dev_out_nak) { + DWC_TIMER_CANCEL(pcd->core_if->ep_xfer_timer[ep->dwc_ep.num]); + pcd->core_if->ep_xfer_info[ep->dwc_ep.num].state = 0; + } +@@ -1658,7 +1647,8 @@ + if (ep->dwc_ep.is_in) { + if (GET_CORE_IF(pcd)->en_multiple_tx_fifo) { + /* Flush the Tx FIFO */ +- dwc_otg_flush_tx_fifo(GET_CORE_IF(pcd), ep->dwc_ep.tx_fifo_num); ++ dwc_otg_flush_tx_fifo(GET_CORE_IF(pcd), ++ ep->dwc_ep.tx_fifo_num); + } + release_perio_tx_fifo(GET_CORE_IF(pcd), ep->dwc_ep.tx_fifo_num); + release_tx_fifo(GET_CORE_IF(pcd), ep->dwc_ep.tx_fifo_num); +@@ -1669,8 +1659,10 @@ + (&GET_CORE_IF(pcd)-> + core_global_regs->dtxfsiz[ep->dwc_ep.tx_fifo_num-1]) >> 16); + gdfifocfg.b.epinfobase = gdfifocfgbase.d32 - dptxfsiz.d32; +- DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gdfifocfg, ++ if (GET_CORE_IF(pcd)->snpsid <= OTG_CORE_REV_2_94a) { ++ DWC_WRITE_REG32(&GET_CORE_IF(pcd)->core_global_regs->gdfifocfg, + gdfifocfg.d32); ++ } + } + } + +@@ -1756,7 +1748,8 @@ + for (i = 0; i < ereq->pio_pkt_count; i++) { + //if ((i % (nat + 1)) == 0) + if ( i > 0 ) +- dwcep->xiso_frame_num = (dwcep->xiso_bInterval + ++ dwcep->xiso_frame_num = ++ (dwcep->xiso_bInterval + + dwcep->xiso_frame_num) & 0x3FFF; + dwcep->desc_addr[i].buf = + req->dma + ddesc_iso[i].offset; +@@ -1823,15 +1816,15 @@ + + /* Setup and start the transfer for this endpoint */ + dwcep->xiso_active_xfers++; +- DWC_WRITE_REG32(&GET_CORE_IF(pcd)->dev_if-> +- out_ep_regs[dwcep->num]->doepdma, +- dwcep->dma_desc_addr); ++ DWC_WRITE_REG32(&GET_CORE_IF(pcd)-> ++ dev_if->out_ep_regs[dwcep->num]-> ++ doepdma, dwcep->dma_desc_addr); + diepctl.d32 = 0; + diepctl.b.epena = 1; + diepctl.b.cnak = 1; +- DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->dev_if-> +- out_ep_regs[dwcep->num]->doepctl, 0, +- diepctl.d32); ++ DWC_MODIFY_REG32(&GET_CORE_IF(pcd)-> ++ dev_if->out_ep_regs[dwcep->num]-> ++ doepctl, 0, diepctl.d32); + } + + } else { +@@ -2128,17 +2121,20 @@ + * Received when EP is disabled interrupt to obtain starting microframe + * (odd/even) start transfer + */ +- if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) +- { ++ if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) { + if (req != 0) { +- depctl_data_t depctl = {.d32 = DWC_READ_REG32(&pcd->core_if->dev_if->in_ep_regs[ep->dwc_ep.num]->diepctl)}; ++ depctl_data_t depctl = {.d32 = ++ DWC_READ_REG32(&pcd->core_if->dev_if-> ++ in_ep_regs[ep->dwc_ep.num]-> ++ diepctl) }; + ++pcd->request_pending; + + DWC_CIRCLEQ_INSERT_TAIL(&ep->queue, req, queue_entry); +- if (ep->dwc_ep.is_in) +- { ++ if (ep->dwc_ep.is_in) { + depctl.b.cnak = 1; +- DWC_WRITE_REG32(&pcd->core_if->dev_if->in_ep_regs[ep->dwc_ep.num]->diepctl, depctl.d32); ++ DWC_WRITE_REG32(&pcd->core_if->dev_if-> ++ in_ep_regs[ep->dwc_ep.num]-> ++ diepctl, depctl.d32); + } + + DWC_SPINUNLOCK_IRQRESTORE(pcd->lock, flags); +@@ -2219,16 +2215,20 @@ + } else { + #endif + max_transfer = +- GET_CORE_IF(ep->pcd)-> +- core_params->max_transfer_size; ++ GET_CORE_IF(ep->pcd)->core_params-> ++ max_transfer_size; + + /* Setup and start the Transfer */ + if (req->dw_align_buf){ + if (ep->dwc_ep.is_in) +- dwc_memcpy(req->dw_align_buf, buf, buflen); +- ep->dwc_ep.dma_addr = req->dw_align_buf_dma; +- ep->dwc_ep.start_xfer_buff = req->dw_align_buf; +- ep->dwc_ep.xfer_buff = req->dw_align_buf; ++ dwc_memcpy(req->dw_align_buf, ++ buf, buflen); ++ ep->dwc_ep.dma_addr = ++ req->dw_align_buf_dma; ++ ep->dwc_ep.start_xfer_buff = ++ req->dw_align_buf; ++ ep->dwc_ep.xfer_buff = ++ req->dw_align_buf; + } else { + ep->dwc_ep.dma_addr = dma_buf; + ep->dwc_ep.start_xfer_buff = buf; +@@ -2288,14 +2288,14 @@ + diepmsk_data_t diepmsk = {.d32 = 0 }; + diepmsk.b.intktxfemp = 1; + if (GET_CORE_IF(pcd)->multiproc_int_enable) { +- DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->dev_if-> +- dev_global_regs-> +- diepeachintmsk[ep->dwc_ep.num], +- 0, diepmsk.d32); +- } else { +- DWC_MODIFY_REG32(&GET_CORE_IF(pcd)->dev_if-> +- dev_global_regs->diepmsk, 0, ++ DWC_MODIFY_REG32(&GET_CORE_IF(pcd)-> ++ dev_if->dev_global_regs->diepeachintmsk ++ [ep->dwc_ep.num], 0, + diepmsk.d32); ++ } else { ++ DWC_MODIFY_REG32(&GET_CORE_IF(pcd)-> ++ dev_if->dev_global_regs-> ++ diepmsk, 0, diepmsk.d32); + } + + } +@@ -2379,11 +2379,13 @@ + fifosize_data_t txfifosize; + + txfifosize.d32 = +- DWC_READ_REG32(&GET_CORE_IF(pcd)->core_global_regs-> +- dtxfsiz[ep->dwc_ep.tx_fifo_num]); ++ DWC_READ_REG32(&GET_CORE_IF(pcd)-> ++ core_global_regs->dtxfsiz[ep->dwc_ep. ++ tx_fifo_num]); + txstatus.d32 = +- DWC_READ_REG32(&GET_CORE_IF(pcd)->dev_if-> +- in_ep_regs[ep->dwc_ep.num]->dtxfsts); ++ DWC_READ_REG32(&GET_CORE_IF(pcd)-> ++ dev_if->in_ep_regs[ep->dwc_ep.num]-> ++ dtxfsts); + + if (txstatus.b.txfspcavail < txfifosize.b.depth) { + DWC_WARN("%s() Data In Tx Fifo\n", __func__); +@@ -2501,14 +2503,16 @@ + /* Mask SRP detected interrupt from Power Down Logic */ + gpwrdn.d32 = 0; + gpwrdn.b.srp_det_msk = 1; +- DWC_MODIFY_REG32(&core_if->core_global_regs-> +- gpwrdn, gpwrdn.d32, 0); ++ DWC_MODIFY_REG32(&core_if-> ++ core_global_regs->gpwrdn, ++ gpwrdn.d32, 0); + + /* Disable Power Down Logic */ + gpwrdn.d32 = 0; + gpwrdn.b.pmuactv = 1; +- DWC_MODIFY_REG32(&core_if->core_global_regs-> +- gpwrdn, gpwrdn.d32, 0); ++ DWC_MODIFY_REG32(&core_if-> ++ core_global_regs->gpwrdn, ++ gpwrdn.d32, 0); + + /* + * Initialize the Core for Device mode. +@@ -2522,13 +2526,13 @@ + } + + dctl.b.rmtwkupsig = 1; +- DWC_MODIFY_REG32(&core_if->dev_if-> +- dev_global_regs->dctl, 0, dctl.d32); ++ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs-> ++ dctl, 0, dctl.d32); + DWC_DEBUGPL(DBG_PCD, "Set Remote Wakeup\n"); + + dwc_mdelay(2); +- DWC_MODIFY_REG32(&core_if->dev_if-> +- dev_global_regs->dctl, dctl.d32, 0); ++ DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs-> ++ dctl, dctl.d32, 0); + DWC_DEBUGPL(DBG_PCD, "Clear Remote Wakeup\n"); + } + } else { +Index: linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_pcd.h +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/dwc_otg_pcd.h 2013-07-26 19:34:44.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_pcd.h 2013-07-26 19:35:46.000000000 +0000 +@@ -1,8 +1,8 @@ + /* ========================================================================== + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_pcd.h $ +- * $Revision: #46 $ +- * $Date: 2011/10/20 $ +- * $Change: 1870124 $ ++ * $Revision: #48 $ ++ * $Date: 2012/08/10 $ ++ * $Change: 2047372 $ + * + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless +@@ -215,6 +215,10 @@ + + dwc_dma_t setup_pkt_dma_handle; + ++ /* Additional buffer and flag for CTRL_WR premature case */ ++ uint8_t *backup_buf; ++ unsigned data_terminated; ++ + /** 2-byte dma buffer used to return status from GET_STATUS */ + uint16_t *status_buf; + dwc_dma_t status_buf_dma_handle; +Index: linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_pcd_intr.c +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/dwc_otg_pcd_intr.c 2013-07-26 19:34:44.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_pcd_intr.c 2013-07-26 19:35:46.000000000 +0000 +@@ -1,8 +1,8 @@ + /* ========================================================================== + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_pcd_intr.c $ +- * $Revision: #113 $ +- * $Date: 2011/10/24 $ +- * $Change: 1871160 $ ++ * $Revision: #116 $ ++ * $Date: 2012/08/10 $ ++ * $Change: 2047372 $ + * + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless +@@ -741,6 +741,12 @@ + DWC_DEBUGPL(DBG_PCDV, "%s() doepctl0=%0x\n", __func__, + DWC_READ_REG32(&dev_if->out_ep_regs[0]->doepctl)); + #endif ++ if (core_if->snpsid >= OTG_CORE_REV_3_00a) { ++ doepctl.d32 = DWC_READ_REG32(&dev_if->out_ep_regs[0]->doepctl); ++ if (doepctl.b.epena) { ++ return; ++ } ++ } + + doeptsize0.b.supcnt = 3; + doeptsize0.b.pktcnt = 1; +@@ -763,6 +769,10 @@ + + /** DMA Descriptor Setup */ + dma_desc->status.b.bs = BS_HOST_BUSY; ++ if (core_if->snpsid >= OTG_CORE_REV_3_00a) { ++ dma_desc->status.b.sr = 0; ++ dma_desc->status.b.mtrf = 0; ++ } + dma_desc->status.b.l = 1; + dma_desc->status.b.ioc = 1; + dma_desc->status.b.bytes = pcd->ep0.dwc_ep.maxpacket; +@@ -772,8 +782,7 @@ + + /** DOEPDMA0 Register write */ + DWC_WRITE_REG32(&dev_if->out_ep_regs[0]->doepdma, +- dev_if-> +- dma_setup_desc_addr ++ dev_if->dma_setup_desc_addr + [dev_if->setup_desc_index]); + } + +@@ -783,10 +792,15 @@ + doeptsize0.d32); + } + +- /** DOEPCTL0 Register write */ ++ /** DOEPCTL0 Register write cnak will be set after setup interrupt */ ++ doepctl.d32 = 0; + doepctl.b.epena = 1; ++ if (core_if->snpsid <= OTG_CORE_REV_2_94a) { + doepctl.b.cnak = 1; + DWC_WRITE_REG32(&dev_if->out_ep_regs[0]->doepctl, doepctl.d32); ++ } else { ++ DWC_MODIFY_REG32(&dev_if->out_ep_regs[0]->doepctl, 0, doepctl.d32); ++ } + + #ifdef VERBOSE + DWC_DEBUGPL(DBG_PCDV, "doepctl0=%0x\n", +@@ -898,7 +912,8 @@ + dcfg.b.epmscnt = 2; + DWC_WRITE_REG32(&dev_if->dev_global_regs->dcfg, dcfg.d32); + +- DWC_DEBUGPL(DBG_PCDV,"%s first_in_nextep_seq= %2d; nextep_seq[]:\n", ++ DWC_DEBUGPL(DBG_PCDV, ++ "%s first_in_nextep_seq= %2d; nextep_seq[]:\n", + __func__, core_if->first_in_nextep_seq); + for (i=0; i <= core_if->dev_if->num_in_eps; i++) { + DWC_DEBUGPL(DBG_PCDV, "%2d\n", core_if->nextep_seq[i]); +@@ -916,10 +931,13 @@ + doepmsk.b.ahberr = 1; + doepmsk.b.epdisabled = 1; + +- if (core_if->dma_desc_enable) { ++ if ((core_if->dma_desc_enable) || ++ (core_if->dma_enable ++ && core_if->snpsid >= OTG_CORE_REV_3_00a)) { + doepmsk.b.stsphsercvd = 1; +- doepmsk.b.bna = 1; + } ++ if (core_if->dma_desc_enable) ++ doepmsk.b.bna = 1; + /* + doepmsk.b.babble = 1; + doepmsk.b.nyet = 1; +@@ -961,10 +979,13 @@ + doepmsk.b.ahberr = 1; + doepmsk.b.epdisabled = 1; + +- if (core_if->dma_desc_enable) { ++ if ((core_if->dma_desc_enable) || ++ (core_if->dma_enable ++ && core_if->snpsid >= OTG_CORE_REV_3_00a)) { + doepmsk.b.stsphsercvd = 1; +- doepmsk.b.bna = 1; + } ++ if (core_if->dma_desc_enable) ++ doepmsk.b.bna = 1; + DWC_WRITE_REG32(&dev_if->dev_global_regs->doepmsk, doepmsk.d32); + + diepmsk.b.xfercompl = 1; +@@ -988,7 +1009,8 @@ + DWC_WRITE_REG32(&dev_if->dev_global_regs->dcfg, dcfg.d32); + + /* setup EP0 to receive SETUP packets */ +- ep0_out_start(core_if, pcd); ++ if (core_if->snpsid <= OTG_CORE_REV_2_94a) ++ ep0_out_start(core_if, pcd); + + /* Clear interrupt */ + gintsts.d32 = 0; +@@ -1051,6 +1073,9 @@ + utmi8b = 8; + } + dwc_otg_ep0_activate(GET_CORE_IF(pcd), &ep0->dwc_ep); ++ if (GET_CORE_IF(pcd)->snpsid >= OTG_CORE_REV_3_00a) { ++ ep0_out_start(GET_CORE_IF(pcd), pcd); ++ } + + #ifdef DEBUG_EP0 + print_ep0_state(pcd); +@@ -1341,6 +1366,14 @@ + + /* Prepare for more SETUP Packets */ + DWC_DEBUGPL(DBG_PCD, "EP0 IN ZLP\n"); ++ if ((GET_CORE_IF(pcd)->snpsid >= OTG_CORE_REV_3_00a) ++ && (pcd->core_if->dma_desc_enable) ++ && (ep0->dwc_ep.xfer_count < ep0->dwc_ep.total_len)) { ++ DWC_DEBUGPL(DBG_PCDV, ++ "Data terminated wait next packet in out_desc_addr\n"); ++ pcd->backup_buf = phys_to_virt(ep0->dwc_ep.dma_addr); ++ pcd->data_terminated = 1; ++ } + ep0->dwc_ep.xfer_len = 0; + ep0->dwc_ep.xfer_count = 0; + ep0->dwc_ep.is_in = 1; +@@ -1478,20 +1511,25 @@ + if(UGETW(ctrl.wIndex) == 0xF000) { /* OTG Status selector */ + DWC_PRINTF("wIndex - %d\n", UGETW(ctrl.wIndex)); + DWC_PRINTF("OTG VERSION - %d\n", core_if->otg_ver); +- DWC_PRINTF("OTG CAP - %d, %d\n", core_if->core_params->otg_cap, ++ DWC_PRINTF("OTG CAP - %d, %d\n", ++ core_if->core_params->otg_cap, + DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE); +- if(core_if->otg_ver == 1 && +- core_if->core_params->otg_cap == DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE) { ++ if (core_if->otg_ver == 1 ++ && core_if->core_params->otg_cap == ++ DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE) { + uint8_t *otgsts = (uint8_t*)pcd->status_buf; + *otgsts = (core_if->otg_sts & 0x1); + pcd->ep0_pending = 1; +- ep0->dwc_ep.start_xfer_buff = (uint8_t *) otgsts; ++ ep0->dwc_ep.start_xfer_buff = ++ (uint8_t *) otgsts; + ep0->dwc_ep.xfer_buff = (uint8_t *) otgsts; +- ep0->dwc_ep.dma_addr = pcd->status_buf_dma_handle; ++ ep0->dwc_ep.dma_addr = ++ pcd->status_buf_dma_handle; + ep0->dwc_ep.xfer_len = 1; + ep0->dwc_ep.xfer_count = 0; + ep0->dwc_ep.total_len = ep0->dwc_ep.xfer_len; +- dwc_otg_ep0_start_transfer(GET_CORE_IF(pcd), &ep0->dwc_ep); ++ dwc_otg_ep0_start_transfer(GET_CORE_IF(pcd), ++ &ep0->dwc_ep); + return; + } else { + ep0_do_stall(pcd, -DWC_E_NOT_SUPPORTED); +@@ -1767,22 +1805,28 @@ + struct cfi_usb_ctrlrequest cfi_req; + #endif + +-#ifdef DEBUG_EP0 +- DWC_DEBUGPL(DBG_PCD, "SETUP %02x.%02x v%04x i%04x l%04x\n", +- ctrl.bmRequestType, ctrl.bRequest, +- UGETW(ctrl.wValue), UGETW(ctrl.wIndex), +- UGETW(ctrl.wLength)); +-#endif +- + doeptsize0.d32 = DWC_READ_REG32(&dev_if->out_ep_regs[0]->doeptsiz); + +- /** @todo handle > 1 setup packet , assert error for now */ +- ++ /** In BDMA more then 1 setup packet is not supported till 3.00a */ + if (core_if->dma_enable && core_if->dma_desc_enable == 0 +- && (doeptsize0.b.supcnt < 2)) { ++ && (doeptsize0.b.supcnt < 2) ++ && (core_if->snpsid < OTG_CORE_REV_2_94a)) { + DWC_ERROR + ("\n\n----------- CANNOT handle > 1 setup packet in DMA mode\n\n"); + } ++ if ((core_if->snpsid >= OTG_CORE_REV_3_00a) ++ && (core_if->dma_enable == 1) && (core_if->dma_desc_enable == 0)) { ++ ctrl = ++ (pcd->setup_pkt + ++ (3 - doeptsize0.b.supcnt - 1 + ++ ep0->dwc_ep.stp_rollover))->req; ++ } ++#ifdef DEBUG_EP0 ++ DWC_DEBUGPL(DBG_PCD, "SETUP %02x.%02x v%04x i%04x l%04x\n", ++ ctrl.bmRequestType, ctrl.bRequest, ++ UGETW(ctrl.wValue), UGETW(ctrl.wIndex), ++ UGETW(ctrl.wLength)); ++#endif + + /* Clean up the request queue */ + dwc_otg_request_nuke(ep0); +@@ -2028,8 +2072,18 @@ + #endif + req->sent_zlp = 0; + } +- if (core_if->dma_desc_enable == 0) ++ /* For older cores do setup in status phase in Slave/BDMA modes, ++ * starting from 3.00 do that only in slave, and for DMA modes ++ * just re-enable ep 0 OUT here*/ ++ if (core_if->dma_enable == 0 ++ || (core_if->dma_desc_enable == 0 ++ && core_if->snpsid <= OTG_CORE_REV_2_94a)) { + do_setup_in_status_phase(pcd); ++ } else if (core_if->snpsid >= OTG_CORE_REV_3_00a) { ++ DWC_DEBUGPL(DBG_PCDV, ++ "Enable out ep before in status phase\n"); ++ ep0_out_start(core_if, pcd); ++ } + } + + /* Complete the request */ +@@ -2169,8 +2223,8 @@ + is_last = 1; + } + } else { +- if(ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) +- { ++ if (ep->dwc_ep.type == ++ DWC_OTG_EP_TYPE_ISOC) { + req->actual = 0; + dwc_otg_request_done(ep, req, 0); + +@@ -2306,25 +2360,34 @@ + */ + if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_INTR && + (ep->dwc_ep.maxpacket%4)) { +- ep->dwc_ep.xfer_count = ep->dwc_ep.total_len - byte_count; +- if ((ep->dwc_ep.xfer_len % ep->dwc_ep.maxpacket) && +- (ep->dwc_ep.xfer_len/ep->dwc_ep.maxpacket < MAX_DMA_DESC_CNT)) ++ ep->dwc_ep.xfer_count = ++ ep->dwc_ep.total_len - byte_count; ++ if ((ep->dwc_ep.xfer_len % ++ ep->dwc_ep.maxpacket) ++ && (ep->dwc_ep.xfer_len / ++ ep->dwc_ep.maxpacket < ++ MAX_DMA_DESC_CNT)) + ep->dwc_ep.xfer_len -= +- (ep->dwc_ep.desc_cnt - 1) * ep->dwc_ep.maxpacket + +- ep->dwc_ep.xfer_len % ep->dwc_ep.maxpacket; ++ (ep->dwc_ep.desc_cnt - ++ 1) * ep->dwc_ep.maxpacket + ++ ep->dwc_ep.xfer_len % ++ ep->dwc_ep.maxpacket; + else + ep->dwc_ep.xfer_len -= +- ep->dwc_ep.desc_cnt * ep->dwc_ep.maxpacket; ++ ep->dwc_ep.desc_cnt * ++ ep->dwc_ep.maxpacket; + if (ep->dwc_ep.xfer_len > 0) { +- dwc_otg_ep_start_transfer(core_if, +- &ep->dwc_ep); ++ dwc_otg_ep_start_transfer ++ (core_if, &ep->dwc_ep); + } else { + is_last = 1; + } + } else { +- ep->dwc_ep.xfer_count = ep->dwc_ep.total_len +- - byte_count + +- ((4 - (ep->dwc_ep.total_len & 0x3)) & 0x3); ++ ep->dwc_ep.xfer_count = ++ ep->dwc_ep.total_len - byte_count + ++ ((4 - ++ (ep->dwc_ep. ++ total_len & 0x3)) & 0x3); + is_last = 1; + } + } else { +@@ -2924,12 +2987,12 @@ + + if (ep->is_in) { + deptsiz.d32 = +- DWC_READ_REG32(&core_if->dev_if-> +- in_ep_regs[ep->num]->dieptsiz); ++ DWC_READ_REG32(&core_if->dev_if->in_ep_regs[ep->num]-> ++ dieptsiz); + } else { + deptsiz.d32 = +- DWC_READ_REG32(&core_if->dev_if-> +- out_ep_regs[ep->num]->doeptsiz); ++ DWC_READ_REG32(&core_if->dev_if->out_ep_regs[ep->num]-> ++ doeptsiz); + } + + if (!deptsiz.b.xfersize) { +@@ -3068,7 +3131,8 @@ + int i, start; + + if (!dwc_ep->desc_cnt) +- DWC_WARN("Descriptor count = %d\n", dwc_ep->desc_cnt); ++ DWC_WARN("Ep%d %s Descriptor count = %d \n", dwc_ep->num, ++ (dwc_ep->is_in ? "IN" : "OUT"), dwc_ep->desc_cnt); + + if (core_if->core_params->cont_on_bna && !dwc_ep->is_in + && dwc_ep->type != DWC_OTG_EP_TYPE_CONTROL) { +@@ -3092,8 +3156,8 @@ + + if (dwc_ep->is_in == 0) { + addr = +- &GET_CORE_IF(pcd)->dev_if->out_ep_regs[dwc_ep-> +- num]->doepctl; ++ &GET_CORE_IF(pcd)->dev_if->out_ep_regs[dwc_ep->num]-> ++ doepctl; + } else { + addr = + &GET_CORE_IF(pcd)->dev_if->in_ep_regs[dwc_ep->num]->diepctl; +@@ -3106,7 +3170,7 @@ + /** + * This function handles EP0 Control transfers. + * +- * The state of the control tranfers are tracked in ++ * The state of the control transfers are tracked in + * ep0state. + */ + static void handle_ep0(dwc_otg_pcd_t * pcd) +@@ -3174,7 +3238,7 @@ + dwc_otg_ep0_continue_transfer(GET_CORE_IF(pcd), + &ep0->dwc_ep); + ep0->dwc_ep.sent_zlp = 0; +- DWC_DEBUGPL(DBG_PCD, "CONTINUE TRANSFER\n"); ++ DWC_DEBUGPL(DBG_PCD, "CONTINUE TRANSFER sent zlp\n"); + } else { + ep0_complete_request(ep0); + DWC_DEBUGPL(DBG_PCD, "COMPLETE TRANSFER\n"); +@@ -3212,7 +3276,7 @@ + dwc_otg_ep0_continue_transfer(GET_CORE_IF(pcd), + &ep0->dwc_ep); + ep0->dwc_ep.sent_zlp = 0; +- DWC_DEBUGPL(DBG_PCD, "CONTINUE TRANSFER\n"); ++ DWC_DEBUGPL(DBG_PCD, "CONTINUE TRANSFER sent zlp\n"); + } else { + ep0_complete_request(ep0); + DWC_DEBUGPL(DBG_PCD, "COMPLETE TRANSFER\n"); +@@ -3365,22 +3429,26 @@ + if (TOKEN_Q_DEPTH > 6) { + /* Fill intkn_seq[] from in_tkn_epnums[1] */ + for (i=6; i < 14; i++) +- intkn_seq[i] = (in_tkn_epnums[1] >> ((7-(i-6)) * 4)) & 0xf; ++ intkn_seq[i] = ++ (in_tkn_epnums[1] >> ((7 - (i - 6)) * 4)) & 0xf; + } + + if (TOKEN_Q_DEPTH > 14) { + /* Fill intkn_seq[] from in_tkn_epnums[1] */ + for (i=14; i < 22; i++) +- intkn_seq[i] = (in_tkn_epnums[2] >> ((7-(i-14)) * 4)) & 0xf; ++ intkn_seq[i] = ++ (in_tkn_epnums[2] >> ((7 - (i - 14)) * 4)) & 0xf; + } + + if (TOKEN_Q_DEPTH > 22) { + /* Fill intkn_seq[] from in_tkn_epnums[1] */ + for (i=22; i < 30; i++) +- intkn_seq[i] = (in_tkn_epnums[3] >> ((7-(i-22)) * 4)) & 0xf; ++ intkn_seq[i] = ++ (in_tkn_epnums[3] >> ((7 - (i - 22)) * 4)) & 0xf; + } + +- DWC_DEBUGPL(DBG_PCDV,"%s start=%d end=%d intkn_seq[]:\n", __func__, start, end); ++ DWC_DEBUGPL(DBG_PCDV, "%s start=%d end=%d intkn_seq[]:\n", __func__, ++ start, end); + for (i=0; idev_if->num_in_eps; i++) { +- depctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl); ++ depctl.d32 = ++ DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl); + if (core_if->nextep_seq[i] != 0xff) { // Active NP IN EP + depctl.b.nextep = core_if->nextep_seq[i]; + DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->diepctl, depctl.d32); +@@ -3729,7 +3798,7 @@ + dwc_otg_core_if_t *core_if; + doepmsk_data_t intr_mask = {.d32 = 0 }; + +- DWC_PRINTF("INTERRUPT Handler not implemented for %s\n", "OUT EP NAK"); ++ DWC_DEBUGPL(DBG_ANY, "INTERRUPT Handler not implemented for %s\n", "OUT EP NAK"); + core_if = GET_CORE_IF(pcd); + intr_mask.b.nak = 1; + +@@ -3842,7 +3911,7 @@ + /* Transfer complete */ + if (diepint.b.xfercompl) { + /* Disable the NP Tx FIFO Empty +- * Interrrupt */ ++ * Interrupt */ + if (core_if->en_multiple_tx_fifo == 0) { + intr_mask.b.nptxfempty = 1; + DWC_MODIFY_REG32 +@@ -4013,14 +4082,11 @@ + if (diepint.b.nak) { + DWC_DEBUGPL(DBG_ANY, "EP%d IN NAK Interrupt\n", + epnum); +- if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) +- { ++ if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) { + depctl_data_t depctl; +- if (ep->dwc_ep.frame_num == 0xFFFFFFFF) +- { ++ if (ep->dwc_ep.frame_num == 0xFFFFFFFF) { + ep->dwc_ep.frame_num = core_if->frame_num; +- if (ep->dwc_ep.bInterval > 1) +- { ++ if (ep->dwc_ep.bInterval > 1) { + depctl.d32 = 0; + depctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->diepctl); + if (ep->dwc_ep.frame_num & 0x1) { +@@ -4035,8 +4101,7 @@ + start_next_request(ep); + } + ep->dwc_ep.frame_num += ep->dwc_ep.bInterval; +- if (dwc_ep->frame_num > 0x3FFF) +- { ++ if (dwc_ep->frame_num > 0x3FFF) { + dwc_ep->frm_overrun = 1; + dwc_ep->frame_num &= 0x3FFF; + } else +@@ -4106,17 +4171,290 @@ + #endif + doepint.d32 = + dwc_otg_read_dev_out_ep_intr(core_if, dwc_ep); +- ++ /* Moved this interrupt upper due to core deffect of asserting ++ * OUT EP 0 xfercompl along with stsphsrcvd in BDMA */ ++ if (doepint.b.stsphsercvd) { ++ deptsiz0_data_t deptsiz; ++ CLEAR_OUT_EP_INTR(core_if, epnum, stsphsercvd); ++ deptsiz.d32 = ++ DWC_READ_REG32(&core_if->dev_if-> ++ out_ep_regs[0]->doeptsiz); ++ if (core_if->snpsid >= OTG_CORE_REV_3_00a ++ && core_if->dma_enable ++ && core_if->dma_desc_enable == 0 ++ && doepint.b.xfercompl ++ && deptsiz.b.xfersize == 24) { ++ CLEAR_OUT_EP_INTR(core_if, epnum, ++ xfercompl); ++ doepint.b.xfercompl = 0; ++ ep0_out_start(core_if, pcd); ++ } ++ if ((core_if->dma_desc_enable) || ++ (core_if->dma_enable ++ && core_if->snpsid >= ++ OTG_CORE_REV_3_00a)) { ++ do_setup_in_status_phase(pcd); ++ } ++ } + /* Transfer complete */ + if (doepint.b.xfercompl) { + + if (epnum == 0) { + /* Clear the bit in DOEPINTn for this interrupt */ +- CLEAR_OUT_EP_INTR(core_if, epnum, +- xfercompl); ++ CLEAR_OUT_EP_INTR(core_if, epnum, xfercompl); ++ if (core_if->snpsid >= OTG_CORE_REV_3_00a) { ++ DWC_DEBUGPL(DBG_PCDV, "DOEPINT=%x doepint=%x\n", ++ DWC_READ_REG32(&core_if->dev_if->out_ep_regs[0]->doepint), ++ doepint.d32); ++ DWC_DEBUGPL(DBG_PCDV, "DOEPCTL=%x \n", ++ DWC_READ_REG32(&core_if->dev_if->out_ep_regs[0]->doepctl)); ++ ++ if (core_if->snpsid >= OTG_CORE_REV_3_00a ++ && core_if->dma_enable == 0) { ++ doepint_data_t doepint; ++ doepint.d32 = DWC_READ_REG32(&core_if->dev_if-> ++ out_ep_regs[0]->doepint); ++ if (pcd->ep0state == EP0_IDLE && doepint.b.sr) { ++ CLEAR_OUT_EP_INTR(core_if, epnum, sr); ++ goto exit_xfercompl; ++ } ++ } ++ /* In case of DDMA look at SR bit to go to the Data Stage */ ++ if (core_if->dma_desc_enable) { ++ dev_dma_desc_sts_t status = {.d32 = 0}; ++ if (pcd->ep0state == EP0_IDLE) { ++ status.d32 = core_if->dev_if->setup_desc_addr[core_if-> ++ dev_if->setup_desc_index]->status.d32; ++ if(pcd->data_terminated) { ++ pcd->data_terminated = 0; ++ status.d32 = core_if->dev_if->out_desc_addr->status.d32; ++ dwc_memcpy(&pcd->setup_pkt->req, pcd->backup_buf, 8); ++ } ++ if (status.b.sr) { ++ if (doepint.b.setup) { ++ DWC_DEBUGPL(DBG_PCDV, "DMA DESC EP0_IDLE SR=1 setup=1\n"); ++ /* Already started data stage, clear setup */ ++ CLEAR_OUT_EP_INTR(core_if, epnum, setup); ++ doepint.b.setup = 0; ++ handle_ep0(pcd); ++ /* Prepare for more setup packets */ ++ if (pcd->ep0state == EP0_IN_STATUS_PHASE || ++ pcd->ep0state == EP0_IN_DATA_PHASE) { ++ ep0_out_start(core_if, pcd); ++ } ++ ++ goto exit_xfercompl; ++ } else { ++ /* Prepare for more setup packets */ ++ DWC_DEBUGPL(DBG_PCDV, ++ "EP0_IDLE SR=1 setup=0 new setup comes\n"); ++ ep0_out_start(core_if, pcd); ++ } ++ } ++ } else { ++ dwc_otg_pcd_request_t *req; ++ dev_dma_desc_sts_t status = {.d32 = 0}; ++ diepint_data_t diepint0; ++ diepint0.d32 = DWC_READ_REG32(&core_if->dev_if-> ++ in_ep_regs[0]->diepint); ++ ++ if (pcd->ep0state == EP0_STALL || pcd->ep0state == EP0_DISCONNECT) { ++ DWC_ERROR("EP0 is stalled/disconnected\n"); ++ } ++ ++ /* Clear IN xfercompl if set */ ++ if (diepint0.b.xfercompl && (pcd->ep0state == EP0_IN_STATUS_PHASE ++ || pcd->ep0state == EP0_IN_DATA_PHASE)) { ++ DWC_WRITE_REG32(&core_if->dev_if-> ++ in_ep_regs[0]->diepint, diepint0.d32); ++ } ++ ++ status.d32 = core_if->dev_if->setup_desc_addr[core_if-> ++ dev_if->setup_desc_index]->status.d32; ++ ++ if (ep->dwc_ep.xfer_count != ep->dwc_ep.total_len ++ && (pcd->ep0state == EP0_OUT_DATA_PHASE)) ++ status.d32 = core_if->dev_if->out_desc_addr->status.d32; ++ if (pcd->ep0state == EP0_OUT_STATUS_PHASE) ++ status.d32 = status.d32 = core_if->dev_if-> ++ out_desc_addr->status.d32; ++ ++ if (status.b.sr) { ++ if (DWC_CIRCLEQ_EMPTY(&ep->queue)) { ++ DWC_DEBUGPL(DBG_PCDV, "Request queue empty!!\n"); ++ } else { ++ DWC_DEBUGPL(DBG_PCDV, "complete req!!\n"); ++ req = DWC_CIRCLEQ_FIRST(&ep->queue); ++ if (ep->dwc_ep.xfer_count != ep->dwc_ep.total_len && ++ pcd->ep0state == EP0_OUT_DATA_PHASE) { ++ /* Read arrived setup packet from req->buf */ ++ dwc_memcpy(&pcd->setup_pkt->req, ++ req->buf + ep->dwc_ep.xfer_count, 8); ++ } ++ req->actual = ep->dwc_ep.xfer_count; ++ dwc_otg_request_done(ep, req, -ECONNRESET); ++ ep->dwc_ep.start_xfer_buff = 0; ++ ep->dwc_ep.xfer_buff = 0; ++ ep->dwc_ep.xfer_len = 0; ++ } ++ pcd->ep0state = EP0_IDLE; ++ if (doepint.b.setup) { ++ DWC_DEBUGPL(DBG_PCDV, "EP0_IDLE SR=1 setup=1\n"); ++ /* Data stage started, clear setup */ ++ CLEAR_OUT_EP_INTR(core_if, epnum, setup); ++ doepint.b.setup = 0; ++ handle_ep0(pcd); ++ /* Prepare for setup packets if ep0in was enabled*/ ++ if (pcd->ep0state == EP0_IN_STATUS_PHASE) { ++ ep0_out_start(core_if, pcd); ++ } ++ ++ goto exit_xfercompl; ++ } else { ++ /* Prepare for more setup packets */ ++ DWC_DEBUGPL(DBG_PCDV, ++ "EP0_IDLE SR=1 setup=0 new setup comes 2\n"); ++ ep0_out_start(core_if, pcd); ++ } ++ } ++ } ++ } ++ if (core_if->snpsid >= OTG_CORE_REV_2_94a && core_if->dma_enable ++ && core_if->dma_desc_enable == 0) { ++ doepint_data_t doepint_temp = {.d32 = 0}; ++ deptsiz0_data_t doeptsize0 = {.d32 = 0 }; ++ doepint_temp.d32 = DWC_READ_REG32(&core_if->dev_if-> ++ out_ep_regs[ep->dwc_ep.num]->doepint); ++ doeptsize0.d32 = DWC_READ_REG32(&core_if->dev_if-> ++ out_ep_regs[ep->dwc_ep.num]->doeptsiz); ++ if (pcd->ep0state == EP0_IDLE) { ++ if (doepint_temp.b.sr) { ++ CLEAR_OUT_EP_INTR(core_if, epnum, sr); ++ } ++ doepint.d32 = DWC_READ_REG32(&core_if->dev_if-> ++ out_ep_regs[0]->doepint); ++ if (doeptsize0.b.supcnt == 3) { ++ DWC_DEBUGPL(DBG_ANY, "Rolling over!!!!!!!\n"); ++ ep->dwc_ep.stp_rollover = 1; ++ } ++ if (doepint.b.setup) { ++retry: ++ /* Already started data stage, clear setup */ ++ CLEAR_OUT_EP_INTR(core_if, epnum, setup); ++ doepint.b.setup = 0; ++ handle_ep0(pcd); ++ ep->dwc_ep.stp_rollover = 0; ++ /* Prepare for more setup packets */ ++ if (pcd->ep0state == EP0_IN_STATUS_PHASE || ++ pcd->ep0state == EP0_IN_DATA_PHASE) { ++ ep0_out_start(core_if, pcd); ++ } ++ goto exit_xfercompl; ++ } else { ++ /* Prepare for more setup packets */ ++ DWC_DEBUGPL(DBG_ANY, ++ "EP0_IDLE SR=1 setup=0 new setup comes\n"); ++ doepint.d32 = DWC_READ_REG32(&core_if->dev_if-> ++ out_ep_regs[0]->doepint); ++ if(doepint.b.setup) ++ goto retry; ++ ep0_out_start(core_if, pcd); ++ } ++ } else { ++ dwc_otg_pcd_request_t *req; ++ diepint_data_t diepint0 = {.d32 = 0}; ++ doepint_data_t doepint_temp = {.d32 = 0}; ++ depctl_data_t diepctl0; ++ diepint0.d32 = DWC_READ_REG32(&core_if->dev_if-> ++ in_ep_regs[0]->diepint); ++ diepctl0.d32 = DWC_READ_REG32(&core_if->dev_if-> ++ in_ep_regs[0]->diepctl); ++ ++ if (pcd->ep0state == EP0_IN_DATA_PHASE ++ || pcd->ep0state == EP0_IN_STATUS_PHASE) { ++ if (diepint0.b.xfercompl) { ++ DWC_WRITE_REG32(&core_if->dev_if-> ++ in_ep_regs[0]->diepint, diepint0.d32); ++ } ++ if (diepctl0.b.epena) { ++ diepint_data_t diepint = {.d32 = 0}; ++ diepctl0.b.snak = 1; ++ DWC_WRITE_REG32(&core_if->dev_if-> ++ in_ep_regs[0]->diepctl, diepctl0.d32); ++ do { ++ dwc_udelay(10); ++ diepint.d32 = DWC_READ_REG32(&core_if->dev_if-> ++ in_ep_regs[0]->diepint); ++ } while (!diepint.b.inepnakeff); ++ diepint.b.inepnakeff = 1; ++ DWC_WRITE_REG32(&core_if->dev_if-> ++ in_ep_regs[0]->diepint, diepint.d32); ++ diepctl0.d32 = 0; ++ diepctl0.b.epdis = 1; ++ DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[0]->diepctl, ++ diepctl0.d32); ++ do { ++ dwc_udelay(10); ++ diepint.d32 = DWC_READ_REG32(&core_if->dev_if-> ++ in_ep_regs[0]->diepint); ++ } while (!diepint.b.epdisabled); ++ diepint.b.epdisabled = 1; ++ DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[0]->diepint, ++ diepint.d32); ++ } ++ } ++ doepint_temp.d32 = DWC_READ_REG32(&core_if->dev_if-> ++ out_ep_regs[ep->dwc_ep.num]->doepint); ++ if (doepint_temp.b.sr) { ++ CLEAR_OUT_EP_INTR(core_if, epnum, sr); ++ if (DWC_CIRCLEQ_EMPTY(&ep->queue)) { ++ DWC_DEBUGPL(DBG_PCDV, "Request queue empty!!\n"); ++ } else { ++ DWC_DEBUGPL(DBG_PCDV, "complete req!!\n"); ++ req = DWC_CIRCLEQ_FIRST(&ep->queue); ++ if (ep->dwc_ep.xfer_count != ep->dwc_ep.total_len && ++ pcd->ep0state == EP0_OUT_DATA_PHASE) { ++ /* Read arrived setup packet from req->buf */ ++ dwc_memcpy(&pcd->setup_pkt->req, ++ req->buf + ep->dwc_ep.xfer_count, 8); ++ } ++ req->actual = ep->dwc_ep.xfer_count; ++ dwc_otg_request_done(ep, req, -ECONNRESET); ++ ep->dwc_ep.start_xfer_buff = 0; ++ ep->dwc_ep.xfer_buff = 0; ++ ep->dwc_ep.xfer_len = 0; ++ } ++ pcd->ep0state = EP0_IDLE; ++ if (doepint.b.setup) { ++ DWC_DEBUGPL(DBG_PCDV, "EP0_IDLE SR=1 setup=1\n"); ++ /* Data stage started, clear setup */ ++ CLEAR_OUT_EP_INTR(core_if, epnum, setup); ++ doepint.b.setup = 0; ++ handle_ep0(pcd); ++ /* Prepare for setup packets if ep0in was enabled*/ ++ if (pcd->ep0state == EP0_IN_STATUS_PHASE) { ++ ep0_out_start(core_if, pcd); ++ } ++ goto exit_xfercompl; ++ } else { ++ /* Prepare for more setup packets */ ++ DWC_DEBUGPL(DBG_PCDV, ++ "EP0_IDLE SR=1 setup=0 new setup comes 2\n"); ++ ep0_out_start(core_if, pcd); ++ } ++ } ++ } ++ } ++ if (core_if->dma_enable == 0 || pcd->ep0state != EP0_IDLE) ++ handle_ep0(pcd); ++exit_xfercompl: ++ DWC_DEBUGPL(DBG_PCDV, "DOEPINT=%x doepint=%x\n", ++ dwc_otg_read_dev_out_ep_intr(core_if, dwc_ep), doepint.d32); ++ } else { + if (core_if->dma_desc_enable == 0 + || pcd->ep0state != EP0_IDLE) + handle_ep0(pcd); ++ } + #ifdef DWC_EN_ISOC + } else if (dwc_ep->type == DWC_OTG_EP_TYPE_ISOC) { + if (doepint.b.pktdrpsts == 0) { +@@ -4228,8 +4566,7 @@ + /* Setup Phase Done (contorl EPs) */ + if (doepint.b.setup) { + #ifdef DEBUG_EP0 +- DWC_DEBUGPL(DBG_PCD, "EP%d SETUP Done\n", +- epnum); ++ DWC_DEBUGPL(DBG_PCD, "EP%d SETUP Done\n", epnum); + #endif + CLEAR_OUT_EP_INTR(core_if, epnum, setup); + +@@ -4257,13 +4594,7 @@ + } + } + } +- if (doepint.b.stsphsercvd) { +- CLEAR_OUT_EP_INTR(core_if, epnum, stsphsercvd); +- if (core_if->dma_desc_enable) { +- do_setup_in_status_phase(pcd); +- } +- } +- /* Babble Interrutp */ ++ /* Babble Interrupt */ + if (doepint.b.babble) { + DWC_DEBUGPL(DBG_ANY, "EP%d OUT Babble\n", + epnum); +@@ -4271,16 +4602,13 @@ + + CLEAR_OUT_EP_INTR(core_if, epnum, babble); + } +- if (doepint.b.outtknepdis) +- { ++ if (doepint.b.outtknepdis) { + DWC_DEBUGPL(DBG_ANY, "EP%d OUT Token received when EP is \ + disabled\n",epnum); +- if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) +- { ++ if (ep->dwc_ep.type == DWC_OTG_EP_TYPE_ISOC) { + doepmsk_data_t doepmsk = {.d32 = 0}; + ep->dwc_ep.frame_num = core_if->frame_num; +- if (ep->dwc_ep.bInterval > 1) +- { ++ if (ep->dwc_ep.bInterval > 1) { + depctl_data_t depctl; + depctl.d32 = DWC_READ_REG32(&core_if->dev_if-> + out_ep_regs[epnum]->doepctl); +@@ -4331,7 +4659,8 @@ + int retval = 0; + if(!frm_overrun && curr_fr >= trgt_fr) + retval = 1; +- else if (frm_overrun && (curr_fr >= trgt_fr && ((curr_fr - trgt_fr) < 0x3FFF/2))) ++ else if (frm_overrun ++ && (curr_fr >= trgt_fr && ((curr_fr - trgt_fr) < 0x3FFF / 2))) + retval = 1; + return retval; + } +@@ -4641,8 +4970,8 @@ + } + if (i > dev_if->num_out_eps) { + dctl_data_t dctl; +- dctl.d32 = DWC_READ_REG32(&dev_if-> +- dev_global_regs->dctl); ++ dctl.d32 = ++ DWC_READ_REG32(&dev_if->dev_global_regs->dctl); + dctl.b.cgoutnak = 1; + DWC_WRITE_REG32(&dev_if->dev_global_regs->dctl, + dctl.d32); +@@ -4650,8 +4979,7 @@ + } + + /* Disable the endpoint */ +- doepctl.d32 = DWC_READ_REG32(&dev_if-> +- out_ep_regs[i]->doepctl); ++ doepctl.d32 = DWC_READ_REG32(&dev_if->out_ep_regs[i]->doepctl); + if (doepctl.b.epena) { + doepctl.b.epdis = 1; + doepctl.b.snak = 1; +@@ -4660,20 +4988,22 @@ + return 1; + } + /* We come here from Incomplete ISO OUT handler */ +- if(dev_if->isoc_ep) +- { ++ if (dev_if->isoc_ep) { + dwc_ep_t *dwc_ep = (dwc_ep_t *)dev_if->isoc_ep; + uint32_t epnum = dwc_ep->num; + doepint_data_t doepint; +- doepint.d32 = DWC_READ_REG32(&dev_if->out_ep_regs[dwc_ep->num]->doepint); ++ doepint.d32 = ++ DWC_READ_REG32(&dev_if->out_ep_regs[dwc_ep->num]->doepint); + dev_if->isoc_ep = NULL; +- doepctl.d32 = DWC_READ_REG32(&dev_if->out_ep_regs[epnum]->doepctl); ++ doepctl.d32 = ++ DWC_READ_REG32(&dev_if->out_ep_regs[epnum]->doepctl); + DWC_PRINTF("Before disable DOEPCTL = %08x\n", doepctl.d32); + if (doepctl.b.epena) { + doepctl.b.epdis = 1; + doepctl.b.snak = 1; + } +- DWC_WRITE_REG32(&dev_if->out_ep_regs[epnum]->doepctl, doepctl.d32); ++ DWC_WRITE_REG32(&dev_if->out_ep_regs[epnum]->doepctl, ++ doepctl.d32); + return 1; + } else + DWC_PRINTF("INTERRUPT Handler not implemented for %s\n", +Index: linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_pcd_linux.c +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/dwc_otg_pcd_linux.c 2013-07-26 19:34:44.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_pcd_linux.c 2013-07-26 19:35:46.000000000 +0000 +@@ -1,8 +1,8 @@ + /* ========================================================================== + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_pcd_linux.c $ +- * $Revision: #19 $ +- * $Date: 2011/10/26 $ +- * $Change: 1873028 $ ++ * $Revision: #21 $ ++ * $Date: 2012/08/10 $ ++ * $Change: 2047372 $ + * + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless +@@ -525,9 +525,10 @@ + req->buf1, req->dma0, req->dma1, + req->sync_frame, req->data_pattern_frame, + req->data_per_frame, +- req->flags & USB_REQ_ISO_ASAP ? -1 : req-> +- start_frame, req->buf_proc_intrvl, req, +- gfp_flags == GFP_ATOMIC ? 1 : 0); ++ req-> ++ flags & USB_REQ_ISO_ASAP ? -1 : ++ req->start_frame, req->buf_proc_intrvl, ++ req, gfp_flags == GFP_ATOMIC ? 1 : 0); + + if (retval) { + return -EINVAL; +Index: linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_regs.h +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/dwc_otg_regs.h 2013-07-26 19:34:44.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_regs.h 2013-07-26 19:35:46.000000000 +0000 +@@ -1,8 +1,8 @@ + /* ========================================================================== + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_regs.h $ +- * $Revision: #97 $ +- * $Date: 2011/10/24 $ +- * $Change: 1871160 $ ++ * $Revision: #98 $ ++ * $Date: 2012/08/10 $ ++ * $Change: 2047372 $ + * + * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, + * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless +@@ -826,8 +826,9 @@ + unsigned num_dev_perio_in_ep:4; + unsigned power_optimiz:1; + unsigned min_ahb_freq:1; +- unsigned part_power_down:1; +- unsigned reserved:7; ++ unsigned hiber:1; ++ unsigned xhiber:1; ++ unsigned reserved:6; + unsigned utmi_phy_data_width:2; + unsigned num_dev_mode_ctrl_ep:4; + unsigned iddig_filt_en:1; +@@ -1330,8 +1331,10 @@ + unsigned nak:1; + /** NYET Interrupt */ + unsigned nyet:1; ++ /** Bit indicating setup packet received */ ++ unsigned sr:1; + +- unsigned reserved15_31:17; ++ unsigned reserved16_31:16; + } b; + } doepint_data_t; + +@@ -2448,7 +2451,9 @@ + unsigned deep_sleep:1; + unsigned resetaftsusp:1; + unsigned restoremode:1; +- unsigned reserved10_12:3; ++ unsigned enbl_extnd_hiber:1; ++ unsigned extnd_hiber_pwrclmp:1; ++ unsigned extnd_hiber_switch:1; + unsigned ess_reg_restored:1; + unsigned prt_clk_sel:2; + unsigned port_power:1; diff -Nru linux-3.2.46/debian/patches/rpi/rpi_227_a915a4f6e8969a599627ca6b3e2cd7714608d222.patch linux-3.2.46/debian/patches/rpi/rpi_227_a915a4f6e8969a599627ca6b3e2cd7714608d222.patch --- linux-3.2.46/debian/patches/rpi/rpi_227_a915a4f6e8969a599627ca6b3e2cd7714608d222.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_227_a915a4f6e8969a599627ca6b3e2cd7714608d222.patch 2013-07-26 19:35:49.000000000 +0000 @@ -0,0 +1,71 @@ +commit a915a4f6e8969a599627ca6b3e2cd7714608d222 +Author: Frank Buss +Date: Thu Aug 23 02:42:34 2012 +0200 + + enabling the realtime clock 1-wire chip DS1307 and 1-wire on GPIO4 (as a module) + +Index: linux-3.2.46/arch/arm/configs/bcmrpi_defconfig +=================================================================== +--- linux-3.2.46.orig/arch/arm/configs/bcmrpi_defconfig 2013-07-26 19:35:42.000000000 +0000 ++++ linux-3.2.46/arch/arm/configs/bcmrpi_defconfig 2013-07-26 19:35:48.000000000 +0000 +@@ -738,6 +738,8 @@ + CONFIG_LEDS_TRIGGER_TIMER=m + CONFIG_LEDS_TRIGGER_HEARTBEAT=m + CONFIG_LEDS_TRIGGER_DEFAULT_ON=m ++CONFIG_RTC_CLASS=y ++CONFIG_RTC_DRV_DS1307=m + CONFIG_UIO=m + CONFIG_UIO_PDRV=m + CONFIG_UIO_PDRV_GENIRQ=m +Index: linux-3.2.46/arch/arm/mach-bcm2708/bcm2708.c +=================================================================== +--- linux-3.2.46.orig/arch/arm/mach-bcm2708/bcm2708.c 2013-07-26 19:34:26.000000000 +0000 ++++ linux-3.2.46/arch/arm/mach-bcm2708/bcm2708.c 2013-07-26 19:35:48.000000000 +0000 +@@ -32,6 +32,7 @@ + #include + #include + #include ++#include + + #include + #include +@@ -69,6 +70,9 @@ + */ + #define DMA_MASK_BITS_COMMON 32 + ++// use GPIO 4 for the one-wire GPIO pin, if enabled ++#define W1_GPIO 4 ++ + static DEFINE_CLOCK_DATA(cd); + + /* command line parameters */ +@@ -291,6 +295,19 @@ + }; + #endif /* CONFIG_MMC_BCM2708 */ + ++#if defined(CONFIG_W1_MASTER_GPIO) || defined(CONFIG_W1_MASTER_GPIO_MODULE) ++static struct w1_gpio_platform_data w1_gpio_pdata = { ++ .pin = W1_GPIO, ++ .is_open_drain = 0, ++}; ++ ++static struct platform_device w1_device = { ++ .name = "w1-gpio", ++ .id = -1, ++ .dev.platform_data = &w1_gpio_pdata, ++}; ++#endif ++ + static u64 fb_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON); + + static struct platform_device bcm2708_fb_device = { +@@ -592,6 +609,9 @@ + #ifdef CONFIG_BCM2708_GPIO + bcm_register_device(&bcm2708_gpio_device); + #endif ++#if defined(CONFIG_W1_MASTER_GPIO) || defined(CONFIG_W1_MASTER_GPIO_MODULE) ++ platform_device_register(&w1_device); ++#endif + bcm_register_device(&bcm2708_systemtimer_device); + #ifdef CONFIG_MMC_BCM2708 + bcm_register_device(&bcm2708_mci_device); diff -Nru linux-3.2.46/debian/patches/rpi/rpi_228_5412f282ae16b8872e0da31b576122d5b3440228.patch linux-3.2.46/debian/patches/rpi/rpi_228_5412f282ae16b8872e0da31b576122d5b3440228.patch --- linux-3.2.46/debian/patches/rpi/rpi_228_5412f282ae16b8872e0da31b576122d5b3440228.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_228_5412f282ae16b8872e0da31b576122d5b3440228.patch 2013-07-26 19:35:50.000000000 +0000 @@ -0,0 +1,41 @@ +commit 5412f282ae16b8872e0da31b576122d5b3440228 +Author: popcornmix +Date: Fri Aug 24 23:21:20 2012 +0100 + + Switch of tracing options in kernel. Costs 20% in iperf speed, and 10% in xbmc framerate + +Index: linux-3.2.46/arch/arm/configs/bcmrpi_defconfig +=================================================================== +--- linux-3.2.46.orig/arch/arm/configs/bcmrpi_defconfig 2013-07-26 19:35:48.000000000 +0000 ++++ linux-3.2.46/arch/arm/configs/bcmrpi_defconfig 2013-07-26 19:35:49.000000000 +0000 +@@ -15,6 +15,7 @@ + CONFIG_BLK_CGROUP=y + CONFIG_NAMESPACES=y + CONFIG_SCHED_AUTOGROUP=y ++CONFIG_RELAY=y + CONFIG_EMBEDDED=y + # CONFIG_COMPAT_BRK is not set + CONFIG_SLAB=y +@@ -850,6 +851,7 @@ + CONFIG_NLS_KOI8_R=m + CONFIG_NLS_KOI8_U=m + CONFIG_PRINTK_TIME=y ++CONFIG_DEBUG_FS=y + CONFIG_DETECT_HUNG_TASK=y + CONFIG_TIMER_STATS=y + # CONFIG_DEBUG_PREEMPT is not set +@@ -857,13 +859,7 @@ + CONFIG_BOOT_PRINTK_DELAY=y + CONFIG_LATENCYTOP=y + CONFIG_SYSCTL_SYSCALL_CHECK=y +-# CONFIG_EVENT_POWER_TRACING_DEPRECATED is not set +-CONFIG_IRQSOFF_TRACER=y +-CONFIG_PREEMPT_TRACER=y +-CONFIG_SCHED_TRACER=y +-CONFIG_STACK_TRACER=y +-CONFIG_BLK_DEV_IO_TRACE=y +-CONFIG_FUNCTION_PROFILER=y ++# CONFIG_KPROBE_EVENT is not set + CONFIG_KGDB=y + CONFIG_KGDB_KDB=y + CONFIG_KDB_KEYBOARD=y diff -Nru linux-3.2.46/debian/patches/rpi/rpi_229_afe58ac9e71636ff2f46e231c9d5fcd615ef933d.patch linux-3.2.46/debian/patches/rpi/rpi_229_afe58ac9e71636ff2f46e231c9d5fcd615ef933d.patch --- linux-3.2.46/debian/patches/rpi/rpi_229_afe58ac9e71636ff2f46e231c9d5fcd615ef933d.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_229_afe58ac9e71636ff2f46e231c9d5fcd615ef933d.patch 2013-07-26 19:35:52.000000000 +0000 @@ -0,0 +1,19 @@ +commit afe58ac9e71636ff2f46e231c9d5fcd615ef933d +Author: popcornmix +Date: Fri Aug 24 23:25:13 2012 +0100 + + Turn on microframe_schedule by default. Can still be disabled on command line + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_driver.c +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/dwc_otg_driver.c 2013-07-26 19:35:46.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_driver.c 2013-07-26 19:35:51.000000000 +0000 +@@ -60,7 +60,7 @@ + #define DWC_DRIVER_VERSION "3.00a 10-AUG-2012" + #define DWC_DRIVER_DESC "HS OTG USB Controller driver" + +-bool microframe_schedule; ++bool microframe_schedule=true; + + static const char dwc_driver_name[] = "dwc_otg"; + diff -Nru linux-3.2.46/debian/patches/rpi/rpi_230_e886b451281bfd198e36078048d8775b8c8ef5c9.patch linux-3.2.46/debian/patches/rpi/rpi_230_e886b451281bfd198e36078048d8775b8c8ef5c9.patch --- linux-3.2.46/debian/patches/rpi/rpi_230_e886b451281bfd198e36078048d8775b8c8ef5c9.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_230_e886b451281bfd198e36078048d8775b8c8ef5c9.patch 2013-07-26 19:35:53.000000000 +0000 @@ -0,0 +1,504 @@ +commit e886b451281bfd198e36078048d8775b8c8ef5c9 +Author: popcornmix +Date: Tue Aug 28 16:42:10 2012 +0100 + + Add low-latency mode to sdcard driver. Enable with sdhci-bcm2708.enable_llm=1. Thanks ddv2005. + +Index: linux-3.2.46/drivers/mmc/host/sdhci-bcm2708.c +=================================================================== +--- linux-3.2.46.orig/drivers/mmc/host/sdhci-bcm2708.c 2013-07-26 19:34:34.000000000 +0000 ++++ linux-3.2.46/drivers/mmc/host/sdhci-bcm2708.c 2013-07-26 19:35:52.000000000 +0000 +@@ -140,6 +140,7 @@ + static int emmc_clock_freq = BCM2708_EMMC_CLOCK_FREQ; + static bool sync_after_dma = 1; + static bool missing_status = 1; ++bool enable_llm = 0; + + #if 0 + static void hptime_test(void) +@@ -880,12 +881,11 @@ + struct sdhci_host *host = dev_id; + struct sdhci_bcm2708_priv *host_priv = SDHCI_HOST_PRIV(host); + u32 dma_cs; /* control and status register */ +- unsigned long flags; + + BUG_ON(NULL == dev_id); + BUG_ON(NULL == host_priv->dma_chan_base); + +- spin_lock_irqsave(&host->lock, flags); ++ sdhci_spin_lock(host); + + dma_cs = readl(host_priv->dma_chan_base + BCM2708_DMA_CS); + +@@ -926,8 +926,7 @@ + + result = IRQ_HANDLED; + } +- +- spin_unlock_irqrestore(&host->lock, flags); ++ sdhci_spin_unlock(host); + + return result; + } +@@ -1314,9 +1313,12 @@ + sdhci_bcm2708_ops.missing_status = sdhci_bcm2708_missing_status; + } + ++ printk("sdhci: %s low-latency mode\n",enable_llm?"Enable":"Disable"); ++ + host->hw_name = "BCM2708_Arasan"; + host->ops = &sdhci_bcm2708_ops; + host->irq = platform_get_irq(pdev, 0); ++ host->second_irq = 0; + + host->quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION | + SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | +@@ -1382,12 +1384,13 @@ + } + host_priv->dma_chan = ret; + +- ret = request_irq(host_priv->dma_irq, sdhci_bcm2708_dma_irq, +- IRQF_SHARED, DRIVER_NAME " (dma)", host); ++ ret = request_irq(host_priv->dma_irq, sdhci_bcm2708_dma_irq,0,//IRQF_SHARED, ++ DRIVER_NAME " (dma)", host); + if (ret) { + dev_err(&pdev->dev, "cannot set DMA IRQ\n"); + goto err_add_dma_irq; + } ++ host->second_irq = host_priv->dma_irq; + DBG("DMA CBs %p handle %08X DMA%d %p DMA IRQ %d\n", + host_priv->cb_base, (unsigned)host_priv->cb_handle, + host_priv->dma_chan, host_priv->dma_chan_base, +@@ -1513,6 +1516,7 @@ + module_param(emmc_clock_freq, int, 0444); + module_param(sync_after_dma, bool, 0444); + module_param(missing_status, bool, 0444); ++module_param(enable_llm, bool, 0444); + + MODULE_DESCRIPTION("Secure Digital Host Controller Interface platform driver"); + MODULE_AUTHOR("Broadcom "); +@@ -1523,5 +1527,6 @@ + MODULE_PARM_DESC(emmc_clock_freq, "Specify the speed of emmc clock"); + MODULE_PARM_DESC(sync_after_dma, "Block in driver until dma complete"); + MODULE_PARM_DESC(missing_status, "Use the missing status quirk"); ++MODULE_PARM_DESC(enable_llm, "Enable low-latency mode"); + + +Index: linux-3.2.46/drivers/mmc/host/sdhci.c +=================================================================== +--- linux-3.2.46.orig/drivers/mmc/host/sdhci.c 2013-07-26 19:31:51.000000000 +0000 ++++ linux-3.2.46/drivers/mmc/host/sdhci.c 2013-07-26 19:35:52.000000000 +0000 +@@ -121,6 +121,79 @@ + * Low level functions * + * * + \*****************************************************************************/ ++extern bool enable_llm; ++static int sdhci_locked=0; ++void sdhci_spin_lock(struct sdhci_host *host) ++{ ++ spin_lock(&host->lock); ++ if(enable_llm) ++ { ++ disable_irq_nosync(host->irq); ++ if(host->second_irq) ++ disable_irq_nosync(host->second_irq); ++ local_irq_enable(); ++ } ++} ++ ++void sdhci_spin_unlock(struct sdhci_host *host) ++{ ++ if(enable_llm) ++ { ++ local_irq_disable(); ++ enable_irq(host->irq); ++ if(host->second_irq) ++ enable_irq(host->second_irq); ++ } ++ spin_unlock(&host->lock); ++} ++ ++void sdhci_spin_lock_irqsave(struct sdhci_host *host,unsigned long *flags) ++{ ++ if(enable_llm) ++ { ++ while(sdhci_locked) ++ { ++ preempt_schedule(); ++ } ++ spin_lock_irqsave(&host->lock,*flags); ++ disable_irq(host->irq); ++ if(host->second_irq) ++ disable_irq(host->second_irq); ++ local_irq_enable(); ++ } ++ else ++ spin_lock_irqsave(&host->lock,*flags); ++} ++ ++void sdhci_spin_unlock_irqrestore(struct sdhci_host *host,unsigned long flags) ++{ ++ if(enable_llm) ++ { ++ local_irq_disable(); ++ enable_irq(host->irq); ++ if(host->second_irq) ++ enable_irq(host->second_irq); ++ } ++ spin_unlock_irqrestore(&host->lock,flags); ++} ++ ++static void sdhci_spin_enable_schedule(struct sdhci_host *host) ++{ ++ if(enable_llm) ++ { ++ sdhci_locked = 1; ++ preempt_enable(); ++ } ++} ++ ++static void sdhci_spin_disable_schedule(struct sdhci_host *host) ++{ ++ if(enable_llm) ++ { ++ preempt_disable(); ++ sdhci_locked = 0; ++ } ++} + + static void sdhci_clear_set_irqs(struct sdhci_host *host, u32 clear, u32 set) + { +@@ -207,7 +280,9 @@ + return; + } + timeout--; ++ sdhci_spin_enable_schedule(host); + mdelay(1); ++ sdhci_spin_disable_schedule(host); + } + + if (host->ops->platform_reset_exit) +@@ -270,7 +345,7 @@ + struct sdhci_host *host = container_of(led, struct sdhci_host, led); + unsigned long flags; + +- spin_lock_irqsave(&host->lock, flags); ++ sdhci_spin_lock_irqsave(host, &flags); + + if (host->runtime_suspended) + goto out; +@@ -280,7 +355,7 @@ + else + sdhci_activate_led(host); + out: +- spin_unlock_irqrestore(&host->lock, flags); ++ sdhci_spin_unlock_irqrestore(host, flags); + } + #endif + +@@ -988,7 +1063,9 @@ + return; + } + timeout--; ++ sdhci_spin_enable_schedule(host); + mdelay(1); ++ sdhci_spin_disable_schedule(host); + } + DBG("send cmd %d - wait 0x%X irq 0x%x\n", cmd->opcode, mask, + sdhci_readl(host, SDHCI_INT_STATUS)); +@@ -1164,7 +1241,9 @@ + return; + } + timeout--; ++ sdhci_spin_enable_schedule(host); + mdelay(1); ++ sdhci_spin_disable_schedule(host); + } + + clk |= SDHCI_CLOCK_CARD_EN; +@@ -1277,7 +1356,7 @@ + + sdhci_runtime_pm_get(host); + +- spin_lock_irqsave(&host->lock, flags); ++ sdhci_spin_lock_irqsave(host, &flags); + + WARN_ON(host->mrq != NULL); + +@@ -1319,9 +1398,9 @@ + */ + if ((host->flags & SDHCI_NEEDS_RETUNING) && + !(present_state & (SDHCI_DOING_WRITE | SDHCI_DOING_READ))) { +- spin_unlock_irqrestore(&host->lock, flags); ++ sdhci_spin_unlock_irqrestore(host, flags); + sdhci_execute_tuning(mmc); +- spin_lock_irqsave(&host->lock, flags); ++ sdhci_spin_lock_irqsave(host, &flags); + + /* Restore original mmc_request structure */ + host->mrq = mrq; +@@ -1334,7 +1413,7 @@ + } + + mmiowb(); +- spin_unlock_irqrestore(&host->lock, flags); ++ sdhci_spin_unlock_irqrestore(host, flags); + } + + static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios) +@@ -1343,7 +1422,7 @@ + u8 ctrl; + int rc; + +- spin_lock_irqsave(&host->lock, flags); ++ sdhci_spin_lock_irqsave(host, &flags); + + if (host->flags & SDHCI_DEVICE_DEAD) + goto out; +@@ -1489,7 +1568,7 @@ + + out: + mmiowb(); +- spin_unlock_irqrestore(&host->lock, flags); ++ sdhci_spin_unlock_irqrestore(host, flags); + + if (ios->power_mode == MMC_POWER_OFF) { + do +@@ -1512,7 +1591,7 @@ + unsigned long flags; + int is_readonly; + +- spin_lock_irqsave(&host->lock, flags); ++ sdhci_spin_lock_irqsave(host, &flags); + + if (host->flags & SDHCI_DEVICE_DEAD) + is_readonly = 0; +@@ -1522,7 +1601,7 @@ + is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE) + & SDHCI_WRITE_PROTECT); + +- spin_unlock_irqrestore(&host->lock, flags); ++ sdhci_spin_unlock_irqrestore(host, flags); + + /* This quirk needs to be replaced by a callback-function later */ + return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ? +@@ -1595,9 +1674,9 @@ + struct sdhci_host *host = mmc_priv(mmc); + unsigned long flags; + +- spin_lock_irqsave(&host->lock, flags); ++ sdhci_spin_lock_irqsave(host, &flags); + sdhci_enable_sdio_irq_nolock(host, enable); +- spin_unlock_irqrestore(&host->lock, flags); ++ sdhci_spin_unlock_irqrestore(host, flags); + } + + static int sdhci_do_start_signal_voltage_switch(struct sdhci_host *host, +@@ -1900,7 +1979,7 @@ + if (host->version < SDHCI_SPEC_300) + return; + +- spin_lock_irqsave(&host->lock, flags); ++ sdhci_spin_lock_irqsave(host, &flags); + + ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); + +@@ -1918,7 +1997,7 @@ + host->flags &= ~SDHCI_PV_ENABLED; + } + +- spin_unlock_irqrestore(&host->lock, flags); ++ sdhci_spin_unlock_irqrestore(host, flags); + } + + static void sdhci_enable_preset_value(struct mmc_host *mmc, bool enable) +@@ -1956,7 +2035,7 @@ + + host = (struct sdhci_host*)param; + +- spin_lock_irqsave(&host->lock, flags); ++ sdhci_spin_lock_irqsave(host, &flags); + + /* Check host->mrq first in case we are runtime suspended */ + if (host->mrq && +@@ -1973,7 +2052,7 @@ + tasklet_schedule(&host->finish_tasklet); + } + +- spin_unlock_irqrestore(&host->lock, flags); ++ sdhci_spin_unlock_irqrestore(host, flags); + + mmc_detect_change(host->mmc, msecs_to_jiffies(200)); + } +@@ -1986,14 +2065,14 @@ + + host = (struct sdhci_host*)param; + +- spin_lock_irqsave(&host->lock, flags); ++ sdhci_spin_lock_irqsave(host, &flags); + + /* + * If this tasklet gets rescheduled while running, it will + * be run again afterwards but without any active request. + */ + if (!host->mrq) { +- spin_unlock_irqrestore(&host->lock, flags); ++ sdhci_spin_unlock_irqrestore(host, flags); + return; + } + +@@ -2036,7 +2115,7 @@ + #endif + + mmiowb(); +- spin_unlock_irqrestore(&host->lock, flags); ++ sdhci_spin_unlock_irqrestore(host, flags); + + mmc_request_done(host->mmc, mrq); + sdhci_runtime_pm_put(host); +@@ -2049,7 +2128,7 @@ + + host = (struct sdhci_host*)data; + +- spin_lock_irqsave(&host->lock, flags); ++ sdhci_spin_lock_irqsave(host, &flags); + + if (host->mrq) { + pr_err("%s: Timeout waiting for hardware " +@@ -2070,7 +2149,7 @@ + } + + mmiowb(); +- spin_unlock_irqrestore(&host->lock, flags); ++ sdhci_spin_unlock_irqrestore(host, flags); + } + + static void sdhci_tuning_timer(unsigned long data) +@@ -2080,11 +2159,11 @@ + + host = (struct sdhci_host *)data; + +- spin_lock_irqsave(&host->lock, flags); ++ sdhci_spin_lock_irqsave(host, &flags); + + host->flags |= SDHCI_NEEDS_RETUNING; + +- spin_unlock_irqrestore(&host->lock, flags); ++ sdhci_spin_unlock_irqrestore(host, flags); + } + + /*****************************************************************************\ +@@ -2304,10 +2383,10 @@ + u32 intmask; + int cardint = 0; + +- spin_lock(&host->lock); ++ sdhci_spin_lock(host); + + if (host->runtime_suspended) { +- spin_unlock(&host->lock); ++ sdhci_spin_unlock(host); + pr_warning("%s: got irq while runtime suspended\n", + mmc_hostname(host->mmc)); + return IRQ_HANDLED; +@@ -2411,7 +2490,7 @@ + + mmiowb(); + out: +- spin_unlock(&host->lock); ++ sdhci_spin_unlock(host); + + /* + * We have to delay this as it calls back into the driver. +@@ -2531,15 +2610,15 @@ + host->flags &= ~SDHCI_NEEDS_RETUNING; + } + +- spin_lock_irqsave(&host->lock, flags); ++ sdhci_spin_lock_irqsave(host, &flags); + sdhci_mask_irqs(host, SDHCI_INT_ALL_MASK); +- spin_unlock_irqrestore(&host->lock, flags); ++ sdhci_spin_unlock_irqrestore(host, flags); + + synchronize_irq(host->irq); + +- spin_lock_irqsave(&host->lock, flags); ++ sdhci_spin_lock_irqsave(host, &flags); + host->runtime_suspended = true; +- spin_unlock_irqrestore(&host->lock, flags); ++ sdhci_spin_unlock_irqrestore(host, flags); + + return ret; + } +@@ -2571,7 +2650,7 @@ + (host->tuning_mode == SDHCI_TUNING_MODE_1)) + host->flags |= SDHCI_NEEDS_RETUNING; + +- spin_lock_irqsave(&host->lock, flags); ++ sdhci_spin_lock_irqsave(host, &flags); + + host->runtime_suspended = false; + +@@ -2582,7 +2661,7 @@ + /* Enable Card Detection */ + sdhci_enable_card_detection(host); + +- spin_unlock_irqrestore(&host->lock, flags); ++ sdhci_spin_unlock_irqrestore(host, flags); + + return ret; + } +@@ -3029,7 +3108,7 @@ + host->tuning_timer.function = sdhci_tuning_timer; + } + +- ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED, ++ ret = request_irq(host->irq, sdhci_irq, 0,//IRQF_SHARED, + mmc_hostname(mmc), host); + if (ret) + goto untasklet; +@@ -3094,7 +3173,7 @@ + unsigned long flags; + + if (dead) { +- spin_lock_irqsave(&host->lock, flags); ++ sdhci_spin_lock_irqsave(host, &flags); + + host->flags |= SDHCI_DEVICE_DEAD; + +@@ -3106,7 +3185,7 @@ + tasklet_schedule(&host->finish_tasklet); + } + +- spin_unlock_irqrestore(&host->lock, flags); ++ sdhci_spin_unlock_irqrestore(host, flags); + } + + sdhci_disable_card_detection(host); +Index: linux-3.2.46/drivers/mmc/host/sdhci.h +=================================================================== +--- linux-3.2.46.orig/drivers/mmc/host/sdhci.h 2013-07-26 19:31:52.000000000 +0000 ++++ linux-3.2.46/drivers/mmc/host/sdhci.h 2013-07-26 19:35:52.000000000 +0000 +@@ -426,4 +426,10 @@ + extern int sdhci_runtime_resume_host(struct sdhci_host *host); + #endif + ++extern void sdhci_spin_lock_irqsave(struct sdhci_host *host,unsigned long *flags); ++extern void sdhci_spin_unlock_irqrestore(struct sdhci_host *host,unsigned long flags); ++extern void sdhci_spin_lock(struct sdhci_host *host); ++extern void sdhci_spin_unlock(struct sdhci_host *host); ++ ++ + #endif /* __SDHCI_HW_H */ +Index: linux-3.2.46/include/linux/mmc/sdhci.h +=================================================================== +--- linux-3.2.46.orig/include/linux/mmc/sdhci.h 2013-07-26 19:31:52.000000000 +0000 ++++ linux-3.2.46/include/linux/mmc/sdhci.h 2013-07-26 19:35:52.000000000 +0000 +@@ -93,6 +93,7 @@ + #define SDHCI_QUIRK2_OWN_CARD_DETECTION (1<<0) + + int irq; /* Device IRQ */ ++ int second_irq; /* Additional IRQ to disable/enable in low-latency mode */ + void __iomem *ioaddr; /* Mapped address */ + + const struct sdhci_ops *ops; /* Low level hw interface */ diff -Nru linux-3.2.46/debian/patches/rpi/rpi_231_307d9fbb18900c17bc9deeb4020c5ed599053947.patch linux-3.2.46/debian/patches/rpi/rpi_231_307d9fbb18900c17bc9deeb4020c5ed599053947.patch --- linux-3.2.46/debian/patches/rpi/rpi_231_307d9fbb18900c17bc9deeb4020c5ed599053947.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_231_307d9fbb18900c17bc9deeb4020c5ed599053947.patch 2013-07-26 19:35:54.000000000 +0000 @@ -0,0 +1,112 @@ +commit 307d9fbb18900c17bc9deeb4020c5ed599053947 +Author: popcornmix +Date: Tue Aug 28 17:40:49 2012 +0100 + + Fix build for non-preempt case. Fix warning + +Index: linux-3.2.46/drivers/mmc/host/sdhci-bcm2708.c +=================================================================== +--- linux-3.2.46.orig/drivers/mmc/host/sdhci-bcm2708.c 2013-07-26 19:35:52.000000000 +0000 ++++ linux-3.2.46/drivers/mmc/host/sdhci-bcm2708.c 2013-07-26 19:35:53.000000000 +0000 +@@ -653,7 +653,7 @@ + sdhci_bcm2708_platdma_reset(struct sdhci_host *host, struct mmc_data *data) + { + struct sdhci_bcm2708_priv *host_priv = SDHCI_HOST_PRIV(host); +- unsigned long flags; ++// unsigned long flags; + + BUG_ON(NULL == host); + +@@ -750,7 +750,7 @@ + int sg_len; + int sg_ix; + int sg_todo; +- unsigned long flags; ++// unsigned long flags; + + BUG_ON(NULL == host); + +Index: linux-3.2.46/drivers/mmc/host/sdhci.c +=================================================================== +--- linux-3.2.46.orig/drivers/mmc/host/sdhci.c 2013-07-26 19:35:52.000000000 +0000 ++++ linux-3.2.46/drivers/mmc/host/sdhci.c 2013-07-26 19:35:53.000000000 +0000 +@@ -126,6 +126,7 @@ + void sdhci_spin_lock(struct sdhci_host *host) + { + spin_lock(&host->lock); ++#ifdef CONFIG_PREEMPT + if(enable_llm) + { + disable_irq_nosync(host->irq); +@@ -133,10 +134,12 @@ + disable_irq_nosync(host->second_irq); + local_irq_enable(); + } ++#endif + } + + void sdhci_spin_unlock(struct sdhci_host *host) + { ++#ifdef CONFIG_PREEMPT + if(enable_llm) + { + local_irq_disable(); +@@ -144,11 +147,13 @@ + if(host->second_irq) + enable_irq(host->second_irq); + } ++#endif + spin_unlock(&host->lock); + } + + void sdhci_spin_lock_irqsave(struct sdhci_host *host,unsigned long *flags) + { ++#ifdef CONFIG_PREEMPT + if(enable_llm) + { + while(sdhci_locked) +@@ -162,11 +167,13 @@ + local_irq_enable(); + } + else ++#endif + spin_lock_irqsave(&host->lock,*flags); + } + + void sdhci_spin_unlock_irqrestore(struct sdhci_host *host,unsigned long flags) + { ++#ifdef CONFIG_PREEMPT + if(enable_llm) + { + local_irq_disable(); +@@ -174,25 +181,30 @@ + if(host->second_irq) + enable_irq(host->second_irq); + } ++#endif + spin_unlock_irqrestore(&host->lock,flags); + } + + static void sdhci_spin_enable_schedule(struct sdhci_host *host) + { ++#ifdef CONFIG_PREEMPT + if(enable_llm) + { + sdhci_locked = 1; + preempt_enable(); + } ++#endif + } + + static void sdhci_spin_disable_schedule(struct sdhci_host *host) + { ++#ifdef CONFIG_PREEMPT + if(enable_llm) + { + preempt_disable(); + sdhci_locked = 0; + } ++#endif + } + + static void sdhci_clear_set_irqs(struct sdhci_host *host, u32 clear, u32 set) diff -Nru linux-3.2.46/debian/patches/rpi/rpi_232_c1e6924f2ddb697ecf4157ce53e850a38439aa79.patch linux-3.2.46/debian/patches/rpi/rpi_232_c1e6924f2ddb697ecf4157ce53e850a38439aa79.patch --- linux-3.2.46/debian/patches/rpi/rpi_232_c1e6924f2ddb697ecf4157ce53e850a38439aa79.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_232_c1e6924f2ddb697ecf4157ce53e850a38439aa79.patch 2013-07-26 19:35:56.000000000 +0000 @@ -0,0 +1,21 @@ +commit c1e6924f2ddb697ecf4157ce53e850a38439aa79 +Author: popcornmix +Date: Wed Aug 29 21:46:25 2012 +0100 + + Add config options to allow iotop to run + +Index: linux-3.2.46/arch/arm/configs/bcmrpi_defconfig +=================================================================== +--- linux-3.2.46.orig/arch/arm/configs/bcmrpi_defconfig 2013-07-26 19:35:49.000000000 +0000 ++++ linux-3.2.46/arch/arm/configs/bcmrpi_defconfig 2013-07-26 19:35:55.000000000 +0000 +@@ -5,6 +5,10 @@ + CONFIG_BSD_PROCESS_ACCT=y + CONFIG_BSD_PROCESS_ACCT_V3=y + CONFIG_FHANDLE=y ++CONFIG_TASKSTATS=y ++CONFIG_TASK_DELAY_ACCT=y ++CONFIG_TASK_XACCT=y ++CONFIG_TASK_IO_ACCOUNTING=y + CONFIG_AUDIT=y + CONFIG_IKCONFIG=y + CONFIG_IKCONFIG_PROC=y diff -Nru linux-3.2.46/debian/patches/rpi/rpi_233_46d14862c3e91a866883c93be8c6c78ffd149439.patch linux-3.2.46/debian/patches/rpi/rpi_233_46d14862c3e91a866883c93be8c6c78ffd149439.patch --- linux-3.2.46/debian/patches/rpi/rpi_233_46d14862c3e91a866883c93be8c6c78ffd149439.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_233_46d14862c3e91a866883c93be8c6c78ffd149439.patch 2013-07-26 19:35:57.000000000 +0000 @@ -0,0 +1,47 @@ +commit 46d14862c3e91a866883c93be8c6c78ffd149439 +Author: popcornmix +Date: Wed Aug 29 21:54:01 2012 +0100 + + Fix for vmalloc failure with modprobe and cutdown kernel + +Index: linux-3.2.46/kernel/module.c +=================================================================== +--- linux-3.2.46.orig/kernel/module.c 2013-05-30 13:35:16.000000000 +0000 ++++ linux-3.2.46/kernel/module.c 2013-07-26 19:35:56.000000000 +0000 +@@ -2606,20 +2606,23 @@ + memset(ptr, 0, mod->core_size); + mod->module_core = ptr; + +- ptr = module_alloc_update_bounds(mod->init_size); +- /* +- * The pointer to this block is stored in the module structure +- * which is inside the block. This block doesn't need to be +- * scanned as it contains data and code that will be freed +- * after the module is initialized. +- */ +- kmemleak_ignore(ptr); +- if (!ptr && mod->init_size) { +- module_free(mod, mod->module_core); +- return -ENOMEM; ++ if (mod->init_size) { ++ ptr = module_alloc_update_bounds(mod->init_size); ++ /* ++ * The pointer to this block is stored in the module structure ++ * which is inside the block. This block doesn't need to be ++ * scanned as it contains data and code that will be freed ++ * after the module is initialized. ++ */ ++ kmemleak_ignore(ptr); ++ if (!ptr && mod->init_size) { ++ module_free(mod, mod->module_core); ++ return -ENOMEM; ++ } ++ memset(ptr, 0, mod->init_size); ++ mod->module_init = ptr; + } +- memset(ptr, 0, mod->init_size); +- mod->module_init = ptr; ++ else mod->module_init = NULL; + + /* Transfer each section which specifies SHF_ALLOC */ + DEBUGP("final section addresses:\n"); diff -Nru linux-3.2.46/debian/patches/rpi/rpi_234_70428950df6af8fb89531dd970d0bca03a36fc1b.patch linux-3.2.46/debian/patches/rpi/rpi_234_70428950df6af8fb89531dd970d0bca03a36fc1b.patch --- linux-3.2.46/debian/patches/rpi/rpi_234_70428950df6af8fb89531dd970d0bca03a36fc1b.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_234_70428950df6af8fb89531dd970d0bca03a36fc1b.patch 2013-07-26 19:35:58.000000000 +0000 @@ -0,0 +1,19 @@ +commit 70428950df6af8fb89531dd970d0bca03a36fc1b +Author: popcornmix +Date: Fri Aug 31 12:53:51 2012 +0100 + + Enable low latency mode by default in sdcard driver. Can be disabled with sdhci-bcm2708.enable_llm=0 + +Index: linux-3.2.46/drivers/mmc/host/sdhci-bcm2708.c +=================================================================== +--- linux-3.2.46.orig/drivers/mmc/host/sdhci-bcm2708.c 2013-07-26 19:35:53.000000000 +0000 ++++ linux-3.2.46/drivers/mmc/host/sdhci-bcm2708.c 2013-07-26 19:35:57.000000000 +0000 +@@ -140,7 +140,7 @@ + static int emmc_clock_freq = BCM2708_EMMC_CLOCK_FREQ; + static bool sync_after_dma = 1; + static bool missing_status = 1; +-bool enable_llm = 0; ++bool enable_llm = 1; + + #if 0 + static void hptime_test(void) diff -Nru linux-3.2.46/debian/patches/rpi/rpi_235_1259e0ca243421307b9eb6eb45baca90abfb90a7.patch linux-3.2.46/debian/patches/rpi/rpi_235_1259e0ca243421307b9eb6eb45baca90abfb90a7.patch --- linux-3.2.46/debian/patches/rpi/rpi_235_1259e0ca243421307b9eb6eb45baca90abfb90a7.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_235_1259e0ca243421307b9eb6eb45baca90abfb90a7.patch 2013-07-26 19:36:01.000000000 +0000 @@ -0,0 +1,1147 @@ +commit 1259e0ca243421307b9eb6eb45baca90abfb90a7 +Author: popcornmix +Date: Sat Sep 1 00:29:19 2012 +0100 + + Add FIQ patch to dwc_otg driver. Enable with dwc_otg.fiq_fix_enable=1. Should give about 10% more ARM performance. + Thanks to Gordon and Costas + +Index: linux-3.2.46/arch/arm/Kconfig +=================================================================== +--- linux-3.2.46.orig/arch/arm/Kconfig 2013-07-26 19:34:24.000000000 +0000 ++++ linux-3.2.46/arch/arm/Kconfig 2013-07-26 19:35:59.000000000 +0000 +@@ -1,4 +1,4 @@ +-config ARM ++iconfig ARM + bool + default y + select HAVE_AOUT +@@ -969,6 +969,7 @@ + select ARM_ERRATA_411920 + select MACH_BCM2708 + select VC4 ++ select FIQ + help + This enables support for Broadcom BCM2708 boards. + +Index: linux-3.2.46/arch/arm/include/asm/fiq.h +=================================================================== +--- linux-3.2.46.orig/arch/arm/include/asm/fiq.h 2013-05-30 13:35:16.000000000 +0000 ++++ linux-3.2.46/arch/arm/include/asm/fiq.h 2013-07-26 19:35:59.000000000 +0000 +@@ -42,6 +42,7 @@ + /* helpers defined in fiqasm.S: */ + extern void __set_fiq_regs(unsigned long const *regs); + extern void __get_fiq_regs(unsigned long *regs); ++extern void __FIQ_Branch(unsigned long *regs); + + static inline void set_fiq_regs(struct pt_regs const *regs) + { +Index: linux-3.2.46/arch/arm/kernel/fiq.c +=================================================================== +--- linux-3.2.46.orig/arch/arm/kernel/fiq.c 2013-05-30 13:35:16.000000000 +0000 ++++ linux-3.2.46/arch/arm/kernel/fiq.c 2013-07-26 19:35:59.000000000 +0000 +@@ -135,6 +135,7 @@ + EXPORT_SYMBOL(set_fiq_handler); + EXPORT_SYMBOL(__set_fiq_regs); /* defined in fiqasm.S */ + EXPORT_SYMBOL(__get_fiq_regs); /* defined in fiqasm.S */ ++EXPORT_SYMBOL(__FIQ_Branch); /* defined in fiqasm.S */ + EXPORT_SYMBOL(claim_fiq); + EXPORT_SYMBOL(release_fiq); + EXPORT_SYMBOL(enable_fiq); +Index: linux-3.2.46/arch/arm/kernel/fiqasm.S +=================================================================== +--- linux-3.2.46.orig/arch/arm/kernel/fiqasm.S 2013-05-30 13:35:16.000000000 +0000 ++++ linux-3.2.46/arch/arm/kernel/fiqasm.S 2013-07-26 19:35:59.000000000 +0000 +@@ -47,3 +47,7 @@ + mov r0, r0 @ avoid hazard prior to ARMv4 + mov pc, lr + ENDPROC(__get_fiq_regs) ++ ++ENTRY(__FIQ_Branch) ++ mov pc, r8 ++ENDPROC(__FIQ_Branch) +Index: linux-3.2.46/arch/arm/mach-bcm2708/armctrl.c +=================================================================== +--- linux-3.2.46.orig/arch/arm/mach-bcm2708/armctrl.c 2013-07-26 19:31:51.000000000 +0000 ++++ linux-3.2.46/arch/arm/mach-bcm2708/armctrl.c 2013-07-26 19:35:59.000000000 +0000 +@@ -59,12 +59,20 @@ + IO_ADDRESS(ARM_IRQ_DIBL3), + 0 + }; ++ ++ if(d->irq >= FIQ_START) ++ { ++ writel(0, __io(IO_ADDRESS(ARM_IRQ_FAST))); ++ } ++ else ++ { + #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,38) +- unsigned int data = (unsigned int)irq_get_chip_data(d->irq); ++ unsigned int data = (unsigned int)irq_get_chip_data(d->irq); + #else +- unsigned int data = (unsigned int)get_irq_chip_data(irq); ++ unsigned int data = (unsigned int)get_irq_chip_data(irq); + #endif +- writel(1 << (data & 0x1f), __io(disables[(data >> 5) & 0x3])); ++ writel(1 << (data & 0x1f), __io(disables[(data >> 5) & 0x3])); ++ } + } + + #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,38) +@@ -79,12 +87,21 @@ + IO_ADDRESS(ARM_IRQ_ENBL3), + 0 + }; ++ ++ if(d->irq >= FIQ_START) ++ { ++ unsigned int data = (unsigned int)irq_get_chip_data(d->irq) - FIQ_START; ++ writel(0x80 | data, __io(IO_ADDRESS(ARM_IRQ_FAST))); ++ } ++ else ++ { + #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,38) +- unsigned int data = (unsigned int)irq_get_chip_data(d->irq); ++ unsigned int data = (unsigned int)irq_get_chip_data(d->irq); + #else +- unsigned int data = (unsigned int)get_irq_chip_data(irq); ++ unsigned int data = (unsigned int)get_irq_chip_data(irq); + #endif +- writel(1 << (data & 0x1f), __io(enables[(data >> 5) & 0x3])); ++ writel(1 << (data & 0x1f), __io(enables[(data >> 5) & 0x3])); ++ } + } + + #if defined(CONFIG_PM) +@@ -379,7 +396,7 @@ + + for (irq = 0; irq < NR_IRQS; irq++) { + unsigned int data = irq; +- if (irq >= INTERRUPT_JPEG) ++ if (irq >= INTERRUPT_JPEG && irq <= INTERRUPT_ARASANSDIO) + data = remap_irqs[irq - INTERRUPT_JPEG]; + + #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,38) +Index: linux-3.2.46/arch/arm/mach-bcm2708/bcm2708.c +=================================================================== +--- linux-3.2.46.orig/arch/arm/mach-bcm2708/bcm2708.c 2013-07-26 19:35:48.000000000 +0000 ++++ linux-3.2.46/arch/arm/mach-bcm2708/bcm2708.c 2013-07-26 19:35:59.000000000 +0000 +@@ -349,12 +349,32 @@ + .flags = IORESOURCE_MEM, + }, + [1] = { +- .start = IRQ_USB, +- .end = IRQ_USB, ++ .start = MPHI_BASE, ++ .end = MPHI_BASE + SZ_4K - 1, ++ .flags = IORESOURCE_MEM, ++ }, ++ [2] = { ++ .start = IRQ_HOSTPORT, ++ .end = IRQ_HOSTPORT, + .flags = IORESOURCE_IRQ, + }, + }; + ++extern bool fiq_fix_enable; ++ ++static struct resource bcm2708_usb_resources_no_fiq_fix[] = { ++ [0] = { ++ .start = USB_BASE, ++ .end = USB_BASE + SZ_128K - 1, ++ .flags = IORESOURCE_MEM, ++ }, ++ [1] = { ++ .start = IRQ_USB, ++ .end = IRQ_USB, ++ .flags = IORESOURCE_IRQ, ++ }, ++}; ++ + static u64 usb_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON); + + static struct platform_device bcm2708_usb_device = { +@@ -617,6 +637,11 @@ + bcm_register_device(&bcm2708_mci_device); + #endif + bcm_register_device(&bcm2708_fb_device); ++ if (!fiq_fix_enable) ++ { ++ bcm2708_usb_device.resource = bcm2708_usb_resources_no_fiq_fix; ++ bcm2708_usb_device.num_resources = ARRAY_SIZE(bcm2708_usb_resources_no_fiq_fix); ++ } + bcm_register_device(&bcm2708_usb_device); + bcm_register_device(&bcm2708_uart1_device); + bcm_register_device(&bcm2708_powerman_device); +Index: linux-3.2.46/arch/arm/mach-bcm2708/include/mach/irqs.h +=================================================================== +--- linux-3.2.46.orig/arch/arm/mach-bcm2708/include/mach/irqs.h 2013-07-26 19:33:45.000000000 +0000 ++++ linux-3.2.46/arch/arm/mach-bcm2708/include/mach/irqs.h 2013-07-26 19:35:59.000000000 +0000 +@@ -106,91 +106,94 @@ + #define IRQ_PENDING1 (IRQ_ARMCTRL_START + INTERRUPT_PENDING1) + #define IRQ_PENDING2 (IRQ_ARMCTRL_START + INTERRUPT_PENDING2) + ++#define FIQ_START HARD_IRQS ++ + /* + * FIQ interrupts definitions are the same as the INT definitions. + */ +-#define FIQ_TIMER0 INT_TIMER0 +-#define FIQ_TIMER1 INT_TIMER1 +-#define FIQ_TIMER2 INT_TIMER2 +-#define FIQ_TIMER3 INT_TIMER3 +-#define FIQ_CODEC0 INT_CODEC0 +-#define FIQ_CODEC1 INT_CODEC1 +-#define FIQ_CODEC2 INT_CODEC2 +-#define FIQ_JPEG INT_JPEG +-#define FIQ_ISP INT_ISP +-#define FIQ_USB INT_USB +-#define FIQ_3D INT_3D +-#define FIQ_TRANSPOSER INT_TRANSPOSER +-#define FIQ_MULTICORESYNC0 INT_MULTICORESYNC0 +-#define FIQ_MULTICORESYNC1 INT_MULTICORESYNC1 +-#define FIQ_MULTICORESYNC2 INT_MULTICORESYNC2 +-#define FIQ_MULTICORESYNC3 INT_MULTICORESYNC3 +-#define FIQ_DMA0 INT_DMA0 +-#define FIQ_DMA1 INT_DMA1 +-#define FIQ_DMA2 INT_DMA2 +-#define FIQ_DMA3 INT_DMA3 +-#define FIQ_DMA4 INT_DMA4 +-#define FIQ_DMA5 INT_DMA5 +-#define FIQ_DMA6 INT_DMA6 +-#define FIQ_DMA7 INT_DMA7 +-#define FIQ_DMA8 INT_DMA8 +-#define FIQ_DMA9 INT_DMA9 +-#define FIQ_DMA10 INT_DMA10 +-#define FIQ_DMA11 INT_DMA11 +-#define FIQ_DMA12 INT_DMA12 +-#define FIQ_AUX INT_AUX +-#define FIQ_ARM INT_ARM +-#define FIQ_VPUDMA INT_VPUDMA +-#define FIQ_HOSTPORT INT_HOSTPORT +-#define FIQ_VIDEOSCALER INT_VIDEOSCALER +-#define FIQ_CCP2TX INT_CCP2TX +-#define FIQ_SDC INT_SDC +-#define FIQ_DSI0 INT_DSI0 +-#define FIQ_AVE INT_AVE +-#define FIQ_CAM0 INT_CAM0 +-#define FIQ_CAM1 INT_CAM1 +-#define FIQ_HDMI0 INT_HDMI0 +-#define FIQ_HDMI1 INT_HDMI1 +-#define FIQ_PIXELVALVE1 INT_PIXELVALVE1 +-#define FIQ_I2CSPISLV INT_I2CSPISLV +-#define FIQ_DSI1 INT_DSI1 +-#define FIQ_PWA0 INT_PWA0 +-#define FIQ_PWA1 INT_PWA1 +-#define FIQ_CPR INT_CPR +-#define FIQ_SMI INT_SMI +-#define FIQ_GPIO0 INT_GPIO0 +-#define FIQ_GPIO1 INT_GPIO1 +-#define FIQ_GPIO2 INT_GPIO2 +-#define FIQ_GPIO3 INT_GPIO3 +-#define FIQ_I2C INT_I2C +-#define FIQ_SPI INT_SPI +-#define FIQ_I2SPCM INT_I2SPCM +-#define FIQ_SDIO INT_SDIO +-#define FIQ_UART INT_UART +-#define FIQ_SLIMBUS INT_SLIMBUS +-#define FIQ_VEC INT_VEC +-#define FIQ_CPG INT_CPG +-#define FIQ_RNG INT_RNG +-#define FIQ_ARASANSDIO INT_ARASANSDIO +-#define FIQ_AVSPMON INT_AVSPMON +- +-#define FIQ_ARM_TIMER INT_ARM_TIMER +-#define FIQ_ARM_MAILBOX INT_ARM_MAILBOX +-#define FIQ_ARM_DOORBELL_0 INT_ARM_DOORBELL_0 +-#define FIQ_ARM_DOORBELL_1 INT_ARM_DOORBELL_1 +-#define FIQ_VPU0_HALTED INT_VPU0_HALTED +-#define FIQ_VPU1_HALTED INT_VPU1_HALTED +-#define FIQ_ILLEGAL_TYPE0 INT_ILLEGAL_TYPE0 +-#define FIQ_ILLEGAL_TYPE1 INT_ILLEGAL_TYPE1 +-#define FIQ_PENDING1 INT_PENDING1 +-#define FIQ_PENDING2 INT_PENDING2 ++#define FIQ_TIMER0 (FIQ_START+INTERRUPT_TIMER0) ++#define FIQ_TIMER1 (FIQ_START+INTERRUPT_TIMER1) ++#define FIQ_TIMER2 (FIQ_START+INTERRUPT_TIMER2) ++#define FIQ_TIMER3 (FIQ_START+INTERRUPT_TIMER3) ++#define FIQ_CODEC0 (FIQ_START+INTERRUPT_CODEC0) ++#define FIQ_CODEC1 (FIQ_START+INTERRUPT_CODEC1) ++#define FIQ_CODEC2 (FIQ_START+INTERRUPT_CODEC2) ++#define FIQ_JPEG (FIQ_START+INTERRUPT_JPEG) ++#define FIQ_ISP (FIQ_START+INTERRUPT_ISP) ++#define FIQ_USB (FIQ_START+INTERRUPT_USB) ++#define FIQ_3D (FIQ_START+INTERRUPT_3D) ++#define FIQ_TRANSPOSER (FIQ_START+INTERRUPT_TRANSPOSER) ++#define FIQ_MULTICORESYNC0 (FIQ_START+INTERRUPT_MULTICORESYNC0) ++#define FIQ_MULTICORESYNC1 (FIQ_START+INTERRUPT_MULTICORESYNC1) ++#define FIQ_MULTICORESYNC2 (FIQ_START+INTERRUPT_MULTICORESYNC2) ++#define FIQ_MULTICORESYNC3 (FIQ_START+INTERRUPT_MULTICORESYNC3) ++#define FIQ_DMA0 (FIQ_START+INTERRUPT_DMA0) ++#define FIQ_DMA1 (FIQ_START+INTERRUPT_DMA1) ++#define FIQ_DMA2 (FIQ_START+INTERRUPT_DMA2) ++#define FIQ_DMA3 (FIQ_START+INTERRUPT_DMA3) ++#define FIQ_DMA4 (FIQ_START+INTERRUPT_DMA4) ++#define FIQ_DMA5 (FIQ_START+INTERRUPT_DMA5) ++#define FIQ_DMA6 (FIQ_START+INTERRUPT_DMA6) ++#define FIQ_DMA7 (FIQ_START+INTERRUPT_DMA7) ++#define FIQ_DMA8 (FIQ_START+INTERRUPT_DMA8) ++#define FIQ_DMA9 (FIQ_START+INTERRUPT_DMA9) ++#define FIQ_DMA10 (FIQ_START+INTERRUPT_DMA10) ++#define FIQ_DMA11 (FIQ_START+INTERRUPT_DMA11) ++#define FIQ_DMA12 (FIQ_START+INTERRUPT_DMA12) ++#define FIQ_AUX (FIQ_START+INTERRUPT_AUX) ++#define FIQ_ARM (FIQ_START+INTERRUPT_ARM) ++#define FIQ_VPUDMA (FIQ_START+INTERRUPT_VPUDMA) ++#define FIQ_HOSTPORT (FIQ_START+INTERRUPT_HOSTPORT) ++#define FIQ_VIDEOSCALER (FIQ_START+INTERRUPT_VIDEOSCALER) ++#define FIQ_CCP2TX (FIQ_START+INTERRUPT_CCP2TX) ++#define FIQ_SDC (FIQ_START+INTERRUPT_SDC) ++#define FIQ_DSI0 (FIQ_START+INTERRUPT_DSI0) ++#define FIQ_AVE (FIQ_START+INTERRUPT_AVE) ++#define FIQ_CAM0 (FIQ_START+INTERRUPT_CAM0) ++#define FIQ_CAM1 (FIQ_START+INTERRUPT_CAM1) ++#define FIQ_HDMI0 (FIQ_START+INTERRUPT_HDMI0) ++#define FIQ_HDMI1 (FIQ_START+INTERRUPT_HDMI1) ++#define FIQ_PIXELVALVE1 (FIQ_START+INTERRUPT_PIXELVALVE1) ++#define FIQ_I2CSPISLV (FIQ_START+INTERRUPT_I2CSPISLV) ++#define FIQ_DSI1 (FIQ_START+INTERRUPT_DSI1) ++#define FIQ_PWA0 (FIQ_START+INTERRUPT_PWA0) ++#define FIQ_PWA1 (FIQ_START+INTERRUPT_PWA1) ++#define FIQ_CPR (FIQ_START+INTERRUPT_CPR) ++#define FIQ_SMI (FIQ_START+INTERRUPT_SMI) ++#define FIQ_GPIO0 (FIQ_START+INTERRUPT_GPIO0) ++#define FIQ_GPIO1 (FIQ_START+INTERRUPT_GPIO1) ++#define FIQ_GPIO2 (FIQ_START+INTERRUPT_GPIO2) ++#define FIQ_GPIO3 (FIQ_START+INTERRUPT_GPIO3) ++#define FIQ_I2C (FIQ_START+INTERRUPT_I2C) ++#define FIQ_SPI (FIQ_START+INTERRUPT_SPI) ++#define FIQ_I2SPCM (FIQ_START+INTERRUPT_I2SPCM) ++#define FIQ_SDIO (FIQ_START+INTERRUPT_SDIO) ++#define FIQ_UART (FIQ_START+INTERRUPT_UART) ++#define FIQ_SLIMBUS (FIQ_START+INTERRUPT_SLIMBUS) ++#define FIQ_VEC (FIQ_START+INTERRUPT_VEC) ++#define FIQ_CPG (FIQ_START+INTERRUPT_CPG) ++#define FIQ_RNG (FIQ_START+INTERRUPT_RNG) ++#define FIQ_ARASANSDIO (FIQ_START+INTERRUPT_ARASANSDIO) ++#define FIQ_AVSPMON (FIQ_START+INTERRUPT_AVSPMON) ++ ++#define FIQ_ARM_TIMER (FIQ_START+INTERRUPT_ARM_TIMER) ++#define FIQ_ARM_MAILBOX (FIQ_START+INTERRUPT_ARM_MAILBOX) ++#define FIQ_ARM_DOORBELL_0 (FIQ_START+INTERRUPT_ARM_DOORBELL_0) ++#define FIQ_ARM_DOORBELL_1 (FIQ_START+INTERRUPT_ARM_DOORBELL_1) ++#define FIQ_VPU0_HALTED (FIQ_START+INTERRUPT_VPU0_HALTED) ++#define FIQ_VPU1_HALTED (FIQ_START+INTERRUPT_VPU1_HALTED) ++#define FIQ_ILLEGAL_TYPE0 (FIQ_START+INTERRUPT_ILLEGAL_TYPE0) ++#define FIQ_ILLEGAL_TYPE1 (FIQ_START+INTERRUPT_ILLEGAL_TYPE1) ++#define FIQ_PENDING1 (FIQ_START+INTERRUPT_PENDING1) ++#define FIQ_PENDING2 (FIQ_START+INTERRUPT_PENDING2) + +-#define HARD_IRQS (64 + 21) +-#define GPIO_IRQ_START HARD_IRQS ++#define GPIO_IRQ_START (HARD_IRQS + FIQ_IRQS) + +-#define GPIO_IRQS 32*5 ++#define HARD_IRQS (64 + 21) ++#define FIQ_IRQS (64 + 21) ++#define GPIO_IRQS (32*5) + +-#define NR_IRQS HARD_IRQS+GPIO_IRQS ++#define NR_IRQS HARD_IRQS+FIQ_IRQS+GPIO_IRQS + + + #endif /* _BCM2708_IRQS_H_ */ +Index: linux-3.2.46/arch/arm/mach-bcm2708/include/mach/platform.h +=================================================================== +--- linux-3.2.46.orig/arch/arm/mach-bcm2708/include/mach/platform.h 2013-07-26 19:34:01.000000000 +0000 ++++ linux-3.2.46/arch/arm/mach-bcm2708/include/mach/platform.h 2013-07-26 19:35:59.000000000 +0000 +@@ -56,7 +56,9 @@ + */ + + #define BCM2708_PERI_BASE 0x20000000 ++#define IC0_BASE (BCM2708_PERI_BASE + 0x2000) + #define ST_BASE (BCM2708_PERI_BASE + 0x3000) /* System Timer */ ++#define MPHI_BASE (BCM2708_PERI_BASE + 0x6000) /* Message -based Parallel Host Interface */ + #define DMA_BASE (BCM2708_PERI_BASE + 0x7000) /* DMA controller */ + #define ARM_BASE (BCM2708_PERI_BASE + 0xB000) /* BCM2708 ARM control block */ + #define PM_BASE (BCM2708_PERI_BASE + 0x100000) /* Power Management, Reset controller and Watchdog registers */ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/Makefile +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/Makefile 2013-07-26 19:34:39.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/Makefile 2013-07-26 19:35:59.000000000 +0000 +@@ -36,6 +36,7 @@ + dwc_otg-objs += dwc_otg_pcd_linux.o dwc_otg_pcd.o dwc_otg_pcd_intr.o + dwc_otg-objs += dwc_otg_hcd.o dwc_otg_hcd_linux.o dwc_otg_hcd_intr.o dwc_otg_hcd_queue.o dwc_otg_hcd_ddma.o + dwc_otg-objs += dwc_otg_adp.o ++dwc_otg-objs += dwc_otg_mphi_fix.o + ifneq ($(CFI),) + dwc_otg-objs += dwc_otg_cfi.o + endif +Index: linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_cil_intr.c +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/dwc_otg_cil_intr.c 2013-07-26 19:35:46.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_cil_intr.c 2013-07-26 19:35:59.000000000 +0000 +@@ -45,6 +45,9 @@ + #include "dwc_otg_driver.h" + #include "dwc_otg_pcd.h" + #include "dwc_otg_hcd.h" ++#include "dwc_otg_mphi_fix.h" ++ ++extern bool fiq_fix_enable; + + #ifdef DEBUG + inline const char *op_state_str(dwc_otg_core_if_t * core_if) +@@ -1351,10 +1354,15 @@ + gintsts.d32, gintmsk.d32); + } + #endif +- if (gahbcfg.b.glblintrmsk) ++ if (!fiq_fix_enable){ ++ if (gahbcfg.b.glblintrmsk) ++ return ((gintsts.d32 & gintmsk.d32) & gintmsk_common.d32); ++ else ++ return 0; ++ } ++ else { + return ((gintsts.d32 & gintmsk.d32) & gintmsk_common.d32); +- else +- return 0; ++ } + + } + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_dbg.h +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/dwc_otg_dbg.h 2013-07-26 19:34:44.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_dbg.h 2013-07-26 19:35:59.000000000 +0000 +@@ -49,6 +49,7 @@ + return old; + } + ++#define DBG_USER (0x1) + /** When debug level has the DBG_CIL bit set, display CIL Debug messages. */ + #define DBG_CIL (0x2) + /** When debug level has the DBG_CILV bit set, display CIL Verbose debug +Index: linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_driver.c +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/dwc_otg_driver.c 2013-07-26 19:35:51.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_driver.c 2013-07-26 19:35:59.000000000 +0000 +@@ -64,6 +64,8 @@ + + static const char dwc_driver_name[] = "dwc_otg"; + ++extern void* dummy_send; ++ + extern int pcd_init( + #ifdef LM_INTERFACE + struct lm_device *_dev +@@ -238,6 +240,10 @@ + .adp_enable = -1, + }; + ++//Global variable to switch the fiq fix on or off ++bool fiq_fix_enable = false; ++ ++ + /** + * This function shows the Driver Version. + */ +@@ -779,17 +785,33 @@ + _dev->resource->start, + _dev->resource->end - _dev->resource->start + 1); + #if 1 +- if (!request_mem_region(_dev->resource->start, +- _dev->resource->end - _dev->resource->start + 1, ++ if (!request_mem_region(_dev->resource[0].start, ++ _dev->resource[0].end - _dev->resource[0].start + 1, + "dwc_otg")) { + dev_dbg(&_dev->dev, "error reserving mapped memory\n"); + retval = -EFAULT; + goto fail; + } + +- dwc_otg_device->os_dep.base = ioremap_nocache(_dev->resource->start, +- _dev->resource->end - +- _dev->resource->start+1); ++ dwc_otg_device->os_dep.base = ioremap_nocache(_dev->resource[0].start, ++ _dev->resource[0].end - ++ _dev->resource[0].start+1); ++ if (fiq_fix_enable) ++ { ++ if (!request_mem_region(_dev->resource[1].start, ++ _dev->resource[1].end - _dev->resource[1].start + 1, ++ "dwc_otg")) { ++ dev_dbg(&_dev->dev, "error reserving mapped memory\n"); ++ retval = -EFAULT; ++ goto fail; ++ } ++ ++ dwc_otg_device->os_dep.mphi_base = ioremap_nocache(_dev->resource[1].start, ++ _dev->resource[1].end - ++ _dev->resource[1].start + 1); ++ dummy_send = (void *) kmalloc(16, GFP_ATOMIC); ++ } ++ + #else + { + struct map_desc desc = { +@@ -1063,6 +1085,7 @@ + printk(KERN_ERR "%s retval=%d\n", __func__, retval); + return retval; + } ++ printk(KERN_DEBUG "dwc_otg: FIQ %s\n", fiq_fix_enable ? "enabled":"disabled"); + + error = driver_create_file(drv, &driver_attr_version); + #ifdef DEBUG +@@ -1343,6 +1366,10 @@ + module_param(microframe_schedule, bool, 0444); + MODULE_PARM_DESC(microframe_schedule, "Enable the microframe scheduler"); + ++ ++module_param(fiq_fix_enable, bool, 0444); ++MODULE_PARM_DESC(fiq_fix_enable, "Enable the fiq fix"); ++ + /** @page "Module Parameters" + * + * The following parameters may be specified when starting the module. +Index: linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_hcd.c +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/dwc_otg_hcd.c 2013-07-26 19:35:17.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_hcd.c 2013-07-26 19:35:59.000000000 +0000 +@@ -53,6 +53,8 @@ + static int last_sel_trans_num_avail_hc_at_end = 0; + #endif /* DEBUG_HOST_CHANNELS */ + ++extern int g_next_sched_frame, g_np_count, g_np_sent; ++ + dwc_otg_hcd_t *dwc_otg_hcd_alloc_hcd(void) + { + return DWC_ALLOC(sizeof(dwc_otg_hcd_t)); +@@ -407,6 +409,7 @@ + } + #endif + ++ + /** + * HCD Callback function for Remote Wakeup. + * +@@ -1330,6 +1333,8 @@ + &qh->qh_list_entry); + DWC_SPINUNLOCK_IRQRESTORE(channel_lock, flags); + ++ g_np_sent++; ++ + if (ret_val == DWC_OTG_TRANSACTION_NONE) { + ret_val = DWC_OTG_TRANSACTION_NON_PERIODIC; + } else { +Index: linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_hcd.h +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/dwc_otg_hcd.h 2013-07-26 19:35:17.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_hcd.h 2013-07-26 19:35:59.000000000 +0000 +@@ -594,7 +594,7 @@ + /** @name Interrupt Handler Functions */ + /** @{ */ + extern int32_t dwc_otg_hcd_handle_intr(dwc_otg_hcd_t * dwc_otg_hcd); +-extern int32_t dwc_otg_hcd_handle_sof_intr(dwc_otg_hcd_t * dwc_otg_hcd); ++extern int32_t dwc_otg_hcd_handle_sof_intr(dwc_otg_hcd_t * dwc_otg_hcd, int32_t); + extern int32_t dwc_otg_hcd_handle_rx_status_q_level_intr(dwc_otg_hcd_t * + dwc_otg_hcd); + extern int32_t dwc_otg_hcd_handle_np_tx_fifo_empty_intr(dwc_otg_hcd_t * +Index: linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_hcd_if.h +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/dwc_otg_hcd_if.h 2013-07-26 19:34:44.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_hcd_if.h 2013-07-26 19:35:59.000000000 +0000 +@@ -113,6 +113,11 @@ + */ + extern int32_t dwc_otg_hcd_handle_intr(dwc_otg_hcd_t * dwc_otg_hcd); + ++/** This function is used to handle the fast interrupt ++ * ++ */ ++extern void __attribute__ ((naked)) dwc_otg_hcd_handle_fiq(void); ++ + /** + * Returns private data set by + * dwc_otg_hcd_set_priv_data function. +Index: linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c 2013-07-26 19:35:16.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c 2013-07-26 19:35:59.000000000 +0000 +@@ -34,6 +34,11 @@ + + #include "dwc_otg_hcd.h" + #include "dwc_otg_regs.h" ++#include "dwc_otg_mphi_fix.h" ++ ++#include ++#include ++ + + extern bool microframe_schedule; + +@@ -41,36 +46,105 @@ + * This file contains the implementation of the HCD Interrupt handlers. + */ + ++/* ++ * Some globals to communicate between the FIQ and INTERRUPT ++ */ ++ ++void * dummy_send; ++mphi_regs_t c_mphi_regs; ++int fiq_done, int_done; ++int g_next_sched_frame, g_np_count, g_np_sent, g_work_expected; ++static int mphi_int_count = 0 ; ++ ++extern bool fiq_fix_enable; ++ ++void __attribute__ ((naked)) dwc_otg_hcd_handle_fiq(void) ++{ ++ gintsts_data_t gintsts; ++ hfnum_data_t hfnum; ++ ++ /* entry takes care to store registers we will be treading on here */ ++ asm __volatile__ ( ++ "mov ip, sp ;" ++ /* stash FIQ and normal regs */ ++ "stmdb sp!, {r0-r12, lr};" ++ /* !! THIS SETS THE FRAME, adjust to > sizeof locals */ ++ "sub fp, ip, #256 ;" ++ ); ++ ++ fiq_done++; ++ gintsts.d32 = FIQ_READ_IO_ADDRESS(USB_BASE + 0x14) & FIQ_READ_IO_ADDRESS(USB_BASE + 0x18); ++ hfnum.d32 = FIQ_READ_IO_ADDRESS(USB_BASE + 0x408); ++ ++ if(gintsts.d32) ++ { ++ if(gintsts.b.sofintr && g_np_count == g_np_sent && dwc_frame_num_gt(g_next_sched_frame, hfnum.b.frnum)) ++ { ++ /* ++ * If np_count != np_sent that means we need to queue non-periodic (bulk) packets this packet ++ * g_next_sched_frame is the next frame we have periodic packets for ++ * ++ * if neither of these are required for this frame then just clear the interrupt ++ */ ++ gintsts.d32 = 0; ++ gintsts.b.sofintr = 1; ++ FIQ_WRITE_IO_ADDRESS((USB_BASE + 0x14), gintsts.d32); ++ ++ g_work_expected = 0; ++ } ++ else ++ { ++ g_work_expected = 1; ++ /* To enable the MPHI interrupt (INT 32) ++ */ ++ FIQ_WRITE( c_mphi_regs.outdda, (int) dummy_send); ++ FIQ_WRITE( c_mphi_regs.outddb, (1 << 29)); ++ ++ mphi_int_count++; ++ /* Clear the USB global interrupt so we don't just sit in the FIQ */ ++ FIQ_MODIFY_IO_ADDRESS((USB_BASE + 0x8),1,0); ++ ++ } ++ } ++ mb(); ++ ++ /* exit back to normal mode restoring everything */ ++ asm __volatile__ ( ++ /* return FIQ regs back to pristine state ++ * and get normal regs back ++ */ ++ "ldmia sp!, {r0-r12, lr};" ++ ++ /* return */ ++ "subs pc, lr, #4;" ++ ); ++} ++ + /** This function handles interrupts for the HCD. */ + int32_t dwc_otg_hcd_handle_intr(dwc_otg_hcd_t * dwc_otg_hcd) + { + int retval = 0; ++ static int last_time; + + dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if; + gintsts_data_t gintsts; ++ hfnum_data_t hfnum; ++ + #ifdef DEBUG + dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs; + +- //GRAYG: debugging +- if (NULL == global_regs) { +- DWC_DEBUGPL(DBG_HCD, "**** NULL regs: dwc_otg_hcd=%p " +- "core_if=%p\n", +- dwc_otg_hcd, global_regs); +- return retval; +- } + #endif + + /* Exit from ISR if core is hibernated */ + if (core_if->hibernation_suspend == 1) { +- return retval; ++ goto exit_handler_routine; + } + DWC_SPINLOCK(dwc_otg_hcd->lock); + /* Check if HOST Mode */ + if (dwc_otg_is_host_mode(core_if)) { + gintsts.d32 = dwc_otg_read_core_intr(core_if); + if (!gintsts.d32) { +- DWC_SPINUNLOCK(dwc_otg_hcd->lock); +- return 0; ++ goto exit_handler_routine; + } + #ifdef DEBUG + /* Don't print debug message in the interrupt handler on SOF */ +@@ -88,9 +162,14 @@ + "DWC OTG HCD Interrupt Detected gintsts&gintmsk=0x%08x core_if=%p\n", + gintsts.d32, core_if); + #endif +- +- if (gintsts.b.sofintr) { +- retval |= dwc_otg_hcd_handle_sof_intr(dwc_otg_hcd); ++ hfnum.d32 = DWC_READ_REG32(&dwc_otg_hcd->core_if->host_if->host_global_regs->hfnum); ++ if (gintsts.b.sofintr && g_np_count == g_np_sent && dwc_frame_num_gt(g_next_sched_frame, hfnum.b.frnum)) ++ { ++ /* Note, we should never get here if the FIQ is doing it's job properly*/ ++ retval |= dwc_otg_hcd_handle_sof_intr(dwc_otg_hcd, g_work_expected); ++ } ++ else if (gintsts.b.sofintr) { ++ retval |= dwc_otg_hcd_handle_sof_intr(dwc_otg_hcd, g_work_expected); + } + if (gintsts.b.rxstsqlvl) { + retval |= +@@ -138,11 +217,37 @@ + #endif + + } ++ ++exit_handler_routine: ++ ++ if (fiq_fix_enable) ++ { ++ /* Clear the MPHI interrupt */ ++ DWC_WRITE_REG32(c_mphi_regs.intstat, (1<<16)); ++ if (mphi_int_count >= 60) ++ { ++ DWC_WRITE_REG32(c_mphi_regs.ctrl, ((1<<31) + (1<<16))); ++ DWC_WRITE_REG32(c_mphi_regs.ctrl, (1<<31)); ++ mphi_int_count = 0; ++ } ++ int_done++; ++ if((jiffies / HZ) > last_time) ++ { ++ /* Once a second output the fiq and irq numbers, useful for debug */ ++ last_time = jiffies / HZ; ++ DWC_DEBUGPL(DBG_USER, "int_done = %d fiq_done = %d\n", int_done, fiq_done); ++ } ++ ++ /* Re-Enable FIQ interrupt from USB peripheral */ ++ DWC_MODIFY_REG32((uint32_t *)IO_ADDRESS(USB_BASE + 0x8), 0 , 1); ++ } ++ + DWC_SPINUNLOCK(dwc_otg_hcd->lock); + return retval; + } + + #ifdef DWC_TRACK_MISSED_SOFS ++ + #warning Compiling code to track missed SOFs + #define FRAME_NUM_ARRAY_SIZE 1000 + /** +@@ -182,13 +287,15 @@ + * (micro)frame. Periodic transactions may be queued to the controller for the + * next (micro)frame. + */ +-int32_t dwc_otg_hcd_handle_sof_intr(dwc_otg_hcd_t * hcd) ++int32_t dwc_otg_hcd_handle_sof_intr(dwc_otg_hcd_t * hcd, int32_t work_expected) + { + hfnum_data_t hfnum; + dwc_list_link_t *qh_entry; + dwc_otg_qh_t *qh; + dwc_otg_transaction_type_e tr_type; + gintsts_data_t gintsts = {.d32 = 0 }; ++ int did_something = 0; ++ int32_t next_sched_frame = -1; + + hfnum.d32 = + DWC_READ_REG32(&hcd->core_if->host_if->host_global_regs->hfnum); +@@ -218,12 +325,30 @@ + */ + DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_ready, + &qh->qh_list_entry); ++ ++ did_something = 1; ++ } ++ else ++ { ++ if(next_sched_frame < 0 || dwc_frame_num_le(qh->sched_frame, next_sched_frame)) ++ { ++ next_sched_frame = qh->sched_frame; ++ } + } + } ++ ++ g_next_sched_frame = next_sched_frame; ++ + tr_type = dwc_otg_hcd_select_transactions(hcd); + if (tr_type != DWC_OTG_TRANSACTION_NONE) { + dwc_otg_hcd_queue_transactions(hcd, tr_type); ++ did_something = 1; + } ++ if(work_expected && !did_something) ++ DWC_DEBUGPL(DBG_USER, "Nothing to do !! frame = %x, g_next_sched_frame = %x\n", (int) hfnum.b.frnum, g_next_sched_frame); ++ if(!work_expected && did_something) ++ DWC_DEBUGPL(DBG_USER, "Unexpected work done !! frame = %x, g_next_sched_frame = %x\n", (int) hfnum.b.frnum, g_next_sched_frame); ++ + + /* Clear interrupt */ + gintsts.b.sofintr = 1; +@@ -2102,5 +2227,4 @@ + + return retval; + } +- + #endif /* DWC_DEVICE_ONLY */ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c 2013-07-26 19:34:44.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c 2013-07-26 19:35:59.000000000 +0000 +@@ -1,3 +1,4 @@ ++ + /* ========================================================================== + * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd_linux.c $ + * $Revision: #20 $ +@@ -50,6 +51,7 @@ + #include + #include + #include ++#include + #include + #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,35) + #include <../drivers/usb/core/hcd.h> +@@ -67,6 +69,8 @@ + #include "dwc_otg_dbg.h" + #include "dwc_otg_driver.h" + #include "dwc_otg_hcd.h" ++#include "dwc_otg_mphi_fix.h" ++ + /** + * Gets the endpoint number from a _bEndpointAddress argument. The endpoint is + * qualified with its direction (possible 32 endpoints per device). +@@ -76,6 +80,8 @@ + + static const char dwc_otg_hcd_name[] = "dwc_otg_hcd"; + ++extern bool fiq_fix_enable; ++ + /** @name Linux HC Driver API Functions */ + /** @{ */ + /* manage i/o requests, device state */ +@@ -366,6 +372,12 @@ + .get_b_hnp_enable = _get_b_hnp_enable, + }; + ++static struct fiq_handler fh = { ++ .name = "usb_fiq", ++}; ++static uint8_t fiqStack[1024]; ++ ++extern mphi_regs_t c_mphi_regs; + /** + * Initializes the HCD. This function allocates memory for and initializes the + * static parts of the usb_hcd and dwc_otg_hcd structures. It also registers the +@@ -379,6 +391,7 @@ + dwc_otg_device_t *otg_dev = DWC_OTG_BUSDRVDATA(_dev); + int retval = 0; + u64 dmamask; ++ struct pt_regs regs; + + DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD INIT otg_dev=%p\n", otg_dev); + +@@ -396,6 +409,18 @@ + pci_set_consistent_dma_mask(_dev, dmamask); + #endif + ++ if (fiq_fix_enable) ++ { ++ // Set up fiq ++ claim_fiq(&fh); ++ set_fiq_handler(__FIQ_Branch, 8); ++ memset(®s,0,sizeof(regs)); ++ regs.ARM_r8 = (long)dwc_otg_hcd_handle_fiq; ++ regs.ARM_r9 = (long)0; ++ regs.ARM_sp = (long)fiqStack + sizeof(fiqStack) - 4; ++ set_fiq_regs(®s); ++ } ++ + /* + * Allocate memory for the base HCD plus the DWC OTG HCD. + * Initialize the base HCD. +@@ -415,6 +440,26 @@ + + hcd->regs = otg_dev->os_dep.base; + ++ if (fiq_fix_enable) ++ { ++ //Set the mphi periph to the required registers ++ c_mphi_regs.base = otg_dev->os_dep.mphi_base; ++ c_mphi_regs.ctrl = otg_dev->os_dep.mphi_base + 0x4c; ++ c_mphi_regs.outdda = otg_dev->os_dep.mphi_base + 0x28; ++ c_mphi_regs.outddb = otg_dev->os_dep.mphi_base + 0x2c; ++ c_mphi_regs.intstat = otg_dev->os_dep.mphi_base + 0x50; ++ ++ //Enable mphi peripheral ++ writel((1<<31),c_mphi_regs.ctrl); ++#ifdef DEBUG ++ if (readl(c_mphi_regs.ctrl) & 0x80000000) ++ DWC_DEBUGPL(DBG_USER, "MPHI periph has been enabled\n"); ++ else ++ DWC_DEBUGPL(DBG_USER, "MPHI periph has NOT been enabled\n"); ++#endif ++ // Enable FIQ interrupt from USB peripheral ++ enable_fiq(INTERRUPT_VC_USB); ++ } + /* Initialize the DWC OTG HCD. */ + dwc_otg_hcd = dwc_otg_hcd_alloc_hcd(); + if (!dwc_otg_hcd) { +Index: linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_hcd_queue.c +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/dwc_otg_hcd_queue.c 2013-07-26 19:35:35.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_hcd_queue.c 2013-07-26 19:35:59.000000000 +0000 +@@ -572,6 +572,9 @@ + return status; + } + ++ ++extern int g_next_sched_frame, g_np_count, g_np_sent; ++ + /** + * Schedules an interrupt or isochronous transfer in the periodic schedule. + * +@@ -630,8 +633,13 @@ + DWC_LIST_INSERT_TAIL(&hcd->periodic_sched_ready, &qh->qh_list_entry); + } + else { +- /* Always start in the inactive schedule. */ +- DWC_LIST_INSERT_TAIL(&hcd->periodic_sched_inactive, &qh->qh_list_entry); ++ if(DWC_LIST_EMPTY(&hcd->periodic_sched_inactive) || dwc_frame_num_le(qh->sched_frame, g_next_sched_frame)) ++ { ++ g_next_sched_frame = qh->sched_frame; ++ ++ } ++ /* Always start in the inactive schedule. */ ++ DWC_LIST_INSERT_TAIL(&hcd->periodic_sched_inactive, &qh->qh_list_entry); + } + + if (!microframe_schedule) { +@@ -645,6 +653,7 @@ + return status; + } + ++ + /** + * This function adds a QH to either the non periodic or periodic schedule if + * it is not already in the schedule. If the QH is already in the schedule, no +@@ -667,6 +676,7 @@ + /* Always start in the inactive schedule. */ + DWC_LIST_INSERT_TAIL(&hcd->non_periodic_sched_inactive, + &qh->qh_list_entry); ++ g_np_count++; + } else { + status = schedule_periodic(hcd, qh); + if ( !hcd->periodic_qh_count ) { +@@ -767,6 +777,7 @@ + if (sched_next_periodic_split) { + + qh->sched_frame = frame_number; ++ + if (dwc_frame_num_le(frame_number, + dwc_frame_num_inc + (qh->start_split_frame, +@@ -815,6 +826,11 @@ + DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_ready, + &qh->qh_list_entry); + } else { ++ if(!dwc_frame_num_le(g_next_sched_frame, qh->sched_frame)) ++ { ++ g_next_sched_frame = qh->sched_frame; ++ } ++ + DWC_LIST_MOVE_HEAD + (&hcd->periodic_sched_inactive, + &qh->qh_list_entry); +Index: linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_mphi_fix.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_mphi_fix.c 2013-07-26 19:35:59.000000000 +0000 +@@ -0,0 +1,113 @@ ++#include "dwc_otg_regs.h" ++#include "dwc_otg_dbg.h" ++ ++void dwc_debug_print_core_int_reg(gintsts_data_t gintsts, const char* function_name) ++{ ++ DWC_DEBUGPL(DBG_USER, "*** Debugging from within the %s function: ***\n" ++ "curmode: %1i Modemismatch: %1i otgintr: %1i sofintr: %1i\n" ++ "rxstsqlvl: %1i nptxfempty : %1i ginnakeff: %1i goutnakeff: %1i\n" ++ "ulpickint: %1i i2cintr: %1i erlysuspend:%1i usbsuspend: %1i\n" ++ "usbreset: %1i enumdone: %1i isooutdrop: %1i eopframe: %1i\n" ++ "restoredone: %1i epmismatch: %1i inepint: %1i outepintr: %1i\n" ++ "incomplisoin:%1i incomplisoout:%1i fetsusp: %1i resetdet: %1i\n" ++ "portintr: %1i hcintr: %1i ptxfempty: %1i lpmtranrcvd:%1i\n" ++ "conidstschng:%1i disconnect: %1i sessreqintr:%1i wkupintr: %1i\n", ++ function_name, ++ gintsts.b.curmode, ++ gintsts.b.modemismatch, ++ gintsts.b.otgintr, ++ gintsts.b.sofintr, ++ gintsts.b.rxstsqlvl, ++ gintsts.b.nptxfempty, ++ gintsts.b.ginnakeff, ++ gintsts.b.goutnakeff, ++ gintsts.b.ulpickint, ++ gintsts.b.i2cintr, ++ gintsts.b.erlysuspend, ++ gintsts.b.usbsuspend, ++ gintsts.b.usbreset, ++ gintsts.b.enumdone, ++ gintsts.b.isooutdrop, ++ gintsts.b.eopframe, ++ gintsts.b.restoredone, ++ gintsts.b.epmismatch, ++ gintsts.b.inepint, ++ gintsts.b.outepintr, ++ gintsts.b.incomplisoin, ++ gintsts.b.incomplisoout, ++ gintsts.b.fetsusp, ++ gintsts.b.resetdet, ++ gintsts.b.portintr, ++ gintsts.b.hcintr, ++ gintsts.b.ptxfempty, ++ gintsts.b.lpmtranrcvd, ++ gintsts.b.conidstschng, ++ gintsts.b.disconnect, ++ gintsts.b.sessreqintr, ++ gintsts.b.wkupintr); ++ return; ++} ++ ++void dwc_debug_core_int_mask(gintmsk_data_t gintmsk, const char* function_name) ++{ ++ DWC_DEBUGPL(DBG_USER, "Interrupt Mask status (called from %s) :\n" ++ "modemismatch: %1i otgintr: %1i sofintr: %1i rxstsqlvl: %1i\n" ++ "nptxfempty: %1i ginnakeff: %1i goutnakeff: %1i ulpickint: %1i\n" ++ "i2cintr: %1i erlysuspend:%1i usbsuspend: %1i usbreset: %1i\n" ++ "enumdone: %1i isooutdrop: %1i eopframe: %1i restoredone: %1i\n" ++ "epmismatch: %1i inepintr: %1i outepintr: %1i incomplisoin:%1i\n" ++ "incomplisoout:%1i fetsusp: %1i resetdet: %1i portintr: %1i\n" ++ "hcintr: %1i ptxfempty: %1i lpmtranrcvd:%1i conidstschng:%1i\n" ++ "disconnect: %1i sessreqintr:%1i wkupintr: %1i\n", ++ function_name, ++ gintmsk.b.modemismatch, ++ gintmsk.b.otgintr, ++ gintmsk.b.sofintr, ++ gintmsk.b.rxstsqlvl, ++ gintmsk.b.nptxfempty, ++ gintmsk.b.ginnakeff, ++ gintmsk.b.goutnakeff, ++ gintmsk.b.ulpickint, ++ gintmsk.b.i2cintr, ++ gintmsk.b.erlysuspend, ++ gintmsk.b.usbsuspend, ++ gintmsk.b.usbreset, ++ gintmsk.b.enumdone, ++ gintmsk.b.isooutdrop, ++ gintmsk.b.eopframe, ++ gintmsk.b.restoredone, ++ gintmsk.b.epmismatch, ++ gintmsk.b.inepintr, ++ gintmsk.b.outepintr, ++ gintmsk.b.incomplisoin, ++ gintmsk.b.incomplisoout, ++ gintmsk.b.fetsusp, ++ gintmsk.b.resetdet, ++ gintmsk.b.portintr, ++ gintmsk.b.hcintr, ++ gintmsk.b.ptxfempty, ++ gintmsk.b.lpmtranrcvd, ++ gintmsk.b.conidstschng, ++ gintmsk.b.disconnect, ++ gintmsk.b.sessreqintr, ++ gintmsk.b.wkupintr); ++ return; ++} ++ ++void dwc_debug_otg_int(gotgint_data_t gotgint, const char* function_name) ++{ ++ DWC_DEBUGPL(DBG_USER, "otg int register (from %s function):\n" ++ "sesenddet:%1i sesreqsucstschung:%2i hstnegsucstschng:%1i\n" ++ "hstnegdet:%1i adevtoutchng: %2i debdone: %1i\n" ++ "mvic: %1i\n", ++ function_name, ++ gotgint.b.sesenddet, ++ gotgint.b.sesreqsucstschng, ++ gotgint.b.hstnegsucstschng, ++ gotgint.b.hstnegdet, ++ gotgint.b.adevtoutchng, ++ gotgint.b.debdone, ++ gotgint.b.mvic); ++ ++ return; ++} +Index: linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_mphi_fix.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_mphi_fix.h 2013-07-26 19:35:59.000000000 +0000 +@@ -0,0 +1,36 @@ ++#ifndef __DWC_OTG_MPHI_FIX_H__ ++#define __DWC_OTG_MPHI_FIX_H__ ++ ++#define FIQ_WRITE_IO_ADDRESS(_addr_,_data_) *(volatile uint32_t *) IO_ADDRESS(_addr_) = _data_ ++#define FIQ_READ_IO_ADDRESS(_addr_) *(volatile uint32_t *) IO_ADDRESS(_addr_) ++#define FIQ_MODIFY_IO_ADDRESS(_addr_,_clear_,_set_) FIQ_WRITE_IO_ADDRESS(_addr_ , (FIQ_READ_IO_ADDRESS(_addr_)&~_clear_)|_set_) ++#define FIQ_WRITE(_addr_,_data_) *(volatile uint32_t *) _addr_ = _data_ ++ ++typedef struct { ++ volatile void* base; ++ volatile void* ctrl; ++ volatile void* outdda; ++ volatile void* outddb; ++ volatile void* intstat; ++} mphi_regs_t; ++ ++void dwc_debug_print_core_int_reg(gintsts_data_t gintsts, const char* function_name); ++void dwc_debug_core_int_mask(gintsts_data_t gintmsk, const char* function_name); ++void dwc_debug_otg_int(gotgint_data_t gotgint, const char* function_name); ++ ++ ++ ++#ifdef DEBUG ++#define DWC_DBG_PRINT_CORE_INT(_arg_) dwc_debug_print_core_int_reg(_arg_,__func__) ++#define DWC_DBG_PRINT_CORE_INT_MASK(_arg_) dwc_debug_core_int_mask(_arg_,__func__) ++#define DWC_DBG_PRINT_OTG_INT(_arg_) dwc_debug_otg_int(_arg_,__func__) ++ ++#else ++#define DWC_DBG_PRINT_CORE_INT(_arg_) ++#define DWC_DBG_PRINT_CORE_INT_MASK(_arg_) ++#define DWC_DBG_PRINT_OTG_INT(_arg_) ++ ++ ++#endif ++ ++#endif +Index: linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_os_dep.h +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/dwc_otg_os_dep.h 2013-07-26 19:34:44.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_os_dep.h 2013-07-26 19:35:59.000000000 +0000 +@@ -97,6 +97,9 @@ + /** Register offset for Diagnostic API */ + uint32_t reg_offset; + ++ /** Base address for MPHI peripheral */ ++ void *mphi_base; ++ + #ifdef LM_INTERFACE + struct lm_device *lmdev; + #elif defined(PCI_INTERFACE) diff -Nru linux-3.2.46/debian/patches/rpi/rpi_236_906508b90bc237cd73d5c3237f20d582d44b8fa7.patch linux-3.2.46/debian/patches/rpi/rpi_236_906508b90bc237cd73d5c3237f20d582d44b8fa7.patch --- linux-3.2.46/debian/patches/rpi/rpi_236_906508b90bc237cd73d5c3237f20d582d44b8fa7.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_236_906508b90bc237cd73d5c3237f20d582d44b8fa7.patch 2013-07-26 19:36:04.000000000 +0000 @@ -0,0 +1,16 @@ +commit 906508b90bc237cd73d5c3237f20d582d44b8fa7 +Author: popcornmix +Date: Sat Sep 1 00:31:47 2012 +0100 + + Fix typo + +Index: linux-3.2.46/arch/arm/Kconfig +=================================================================== +--- linux-3.2.46.orig/arch/arm/Kconfig 2013-07-26 19:35:59.000000000 +0000 ++++ linux-3.2.46/arch/arm/Kconfig 2013-07-26 19:36:02.000000000 +0000 +@@ -1,4 +1,4 @@ +-iconfig ARM ++config ARM + bool + default y + select HAVE_AOUT diff -Nru linux-3.2.46/debian/patches/rpi/rpi_237_1625539436b4965c445fff708eb28d3d55af7685.patch linux-3.2.46/debian/patches/rpi/rpi_237_1625539436b4965c445fff708eb28d3d55af7685.patch --- linux-3.2.46/debian/patches/rpi/rpi_237_1625539436b4965c445fff708eb28d3d55af7685.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_237_1625539436b4965c445fff708eb28d3d55af7685.patch 2013-07-26 19:36:23.000000000 +0000 @@ -0,0 +1,183799 @@ +commit 1625539436b4965c445fff708eb28d3d55af7685 +Author: popcornmix +Date: Mon Sep 3 17:10:23 2012 +0100 + + Add non-mainline source for rtl8188cu wireless driver as this is widely used. Disabled older rtlwifi driver + +Index: linux-3.2.46/drivers/net/wireless/Kconfig +=================================================================== +--- linux-3.2.46.orig/drivers/net/wireless/Kconfig 2013-05-30 13:35:16.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/Kconfig 2013-07-26 19:36:04.000000000 +0000 +@@ -281,10 +281,11 @@ + source "drivers/net/wireless/orinoco/Kconfig" + source "drivers/net/wireless/p54/Kconfig" + source "drivers/net/wireless/rt2x00/Kconfig" +-source "drivers/net/wireless/rtlwifi/Kconfig" ++#source "drivers/net/wireless/rtlwifi/Kconfig" + source "drivers/net/wireless/wl1251/Kconfig" + source "drivers/net/wireless/wl12xx/Kconfig" + source "drivers/net/wireless/zd1211rw/Kconfig" + source "drivers/net/wireless/mwifiex/Kconfig" ++source "drivers/net/wireless/rtl8192cu/Kconfig" + + endif # WLAN +Index: linux-3.2.46/drivers/net/wireless/Makefile +=================================================================== +--- linux-3.2.46.orig/drivers/net/wireless/Makefile 2013-05-30 13:35:16.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/Makefile 2013-07-26 19:36:04.000000000 +0000 +@@ -24,7 +24,7 @@ + obj-$(CONFIG_ZD1211RW) += zd1211rw/ + obj-$(CONFIG_RTL8180) += rtl818x/ + obj-$(CONFIG_RTL8187) += rtl818x/ +-obj-$(CONFIG_RTLWIFI) += rtlwifi/ ++#obj-$(CONFIG_RTLWIFI) += rtlwifi/ + + # 16-bit wireless PCMCIA client drivers + obj-$(CONFIG_PCMCIA_RAYCS) += ray_cs.o +@@ -61,3 +61,6 @@ + obj-$(CONFIG_BRCMFMAC) += brcm80211/ + obj-$(CONFIG_BRCMUMAC) += brcm80211/ + obj-$(CONFIG_BRCMSMAC) += brcm80211/ ++ ++obj-$(CONFIG_RTL8192CU) += rtl8192cu/ ++ +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/Kconfig +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/Kconfig 2013-07-26 19:36:04.000000000 +0000 +@@ -0,0 +1,6 @@ ++config RTL8192CU ++ tristate "Realtek 8192C USB WiFi" ++ depends on USB ++ ---help--- ++ Help message of RTL8192CU ++ +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/Makefile +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/Makefile 2013-07-26 19:36:04.000000000 +0000 +@@ -0,0 +1,545 @@ ++EXTRA_CFLAGS += $(USER_EXTRA_CFLAGS) ++EXTRA_CFLAGS += -O1 ++#EXTRA_CFLAGS += -O3 ++#EXTRA_CFLAGS += -Wall ++#EXTRA_CFLAGS += -Wextra ++#EXTRA_CFLAGS += -Werror ++#EXTRA_CFLAGS += -pedantic ++#EXTRA_CFLAGS += -Wshadow -Wpointer-arith -Wcast-qual -Wstrict-prototypes -Wmissing-prototypes ++ ++EXTRA_CFLAGS += -Wno-unused-variable ++EXTRA_CFLAGS += -Wno-unused-value ++EXTRA_CFLAGS += -Wno-unused-label ++EXTRA_CFLAGS += -Wno-unused-parameter ++EXTRA_CFLAGS += -Wno-unused-function ++EXTRA_CFLAGS += -Wno-unused ++ ++EXTRA_CFLAGS += -Wno-uninitialized ++ ++EXTRA_CFLAGS += -I$(src)/include ++ ++CONFIG_AUTOCFG_CP = n ++ ++CONFIG_RTL8192C = y ++CONFIG_RTL8192D = n ++ ++CONFIG_USB_HCI = y ++CONFIG_PCI_HCI = n ++CONFIG_SDIO_HCI = n ++ ++CONFIG_MP_INCLUDED = n ++CONFIG_POWER_SAVING = y ++CONFIG_USB_AUTOSUSPEND = n ++CONFIG_HW_PWRP_DETECTION = n ++CONFIG_WIFI_TEST = n ++CONFIG_BT_COEXISTENCE = n ++CONFIG_RTL8192CU_REDEFINE_1X1 =n ++CONFIG_WAKE_ON_WLAN = n ++ ++CONFIG_PLATFORM_I386_PC = n ++CONFIG_PLATFORM_TI_AM3517 = n ++CONFIG_PLATFORM_ANDROID_X86 = n ++CONFIG_PLATFORM_ARM_S3C2K4 = n ++CONFIG_PLATFORM_ARM_PXA2XX = n ++CONFIG_PLATFORM_ARM_S3C6K4 = n ++CONFIG_PLATFORM_MIPS_RMI = n ++CONFIG_PLATFORM_RTD2880B = n ++CONFIG_PLATFORM_MIPS_AR9132 = n ++CONFIG_PLATFORM_RTK_DMP = n ++CONFIG_PLATFORM_MIPS_PLM = n ++CONFIG_PLATFORM_MSTAR389 = n ++CONFIG_PLATFORM_MT53XX = n ++CONFIG_PLATFORM_ARM_MX51_241H = n ++CONFIG_PLATFORM_ACTIONS_ATJ227X = n ++CONFIG_PLATFORM_ARM_TEGRA3 = n ++CONFIG_PLATFORM_ARM_TCC8900 = n ++CONFIG_PLATFORM_ARM_TCC8920 = n ++CONFIG_PLATFORM_ARM_RK2818 = n ++CONFIG_PLATFORM_ARM_TI_PANDA = n ++CONFIG_PLATFORM_MIPS_JZ4760 = n ++CONFIG_PLATFORM_DMP_PHILIPS = n ++CONFIG_PLATFORM_TI_DM365 = n ++CONFIG_PLATFORM_MN10300 = n ++CONFIG_PLATFORM_MSTAR_TITANIA12 = n ++CONFIG_PLATFORM_ARM_BCM2708 = y ++ ++CONFIG_DRVEXT_MODULE = n ++ ++export TopDIR ?= $(shell pwd) ++ ++ ++ifeq ($(CONFIG_RTL8712), y) ++ ++RTL871X = rtl8712 ++ ++ifeq ($(CONFIG_SDIO_HCI), y) ++MODULE_NAME = 8712s ++endif ++ifeq ($(CONFIG_USB_HCI), y) ++MODULE_NAME = 8712u ++endif ++ ++endif ++ ++ifeq ($(CONFIG_RTL8192C), y) ++ ++RTL871X = rtl8192c ++ ++ifeq ($(CONFIG_SDIO_HCI), y) ++MODULE_NAME = 8192cs ++endif ++ifeq ($(CONFIG_USB_HCI), y) ++MODULE_NAME = 8192cu ++FW_FILES := hal/$(RTL871X)/usb/Hal8192CUHWImg.o ++ifneq ($(CONFIG_WAKE_ON_WLAN), n) ++FW_FILES += hal/$(RTL871X)/usb/Hal8192CUHWImg_wowlan.o ++endif ++endif ++ifeq ($(CONFIG_PCI_HCI), y) ++MODULE_NAME = 8192ce ++FW_FILES := hal/$(RTL871X)/pci/Hal8192CEHWImg.o ++endif ++ ++CHIP_FILES := hal/$(RTL871X)/$(RTL871X)_sreset.o ++CHIP_FILES += $(FW_FILES) ++endif ++ ++ifeq ($(CONFIG_RTL8192D), y) ++ ++RTL871X = rtl8192d ++ ++ifeq ($(CONFIG_SDIO_HCI), y) ++MODULE_NAME = 8192ds ++endif ++ifeq ($(CONFIG_USB_HCI), y) ++MODULE_NAME = 8192du ++FW_FILES := hal/$(RTL871X)/usb/Hal8192DUHWImg.o \ ++ hal/$(RTL871X)/usb/Hal8192DUTestHWImg.o ++ifneq ($(CONFIG_WAKE_ON_WLAN), n) ++FW_FILES += hal/$(RTL871X)/usb/Hal8192DUHWImg_wowlan.o ++endif ++endif ++ifeq ($(CONFIG_PCI_HCI), y) ++MODULE_NAME = 8192de ++FW_FILES := hal/$(RTL871X)/pci/Hal8192DEHWImg.o \ ++ hal/$(RTL871X)/pci/Hal8192DETestHWImg.o ++endif ++ ++CHIP_FILES += $(FW_FILES) ++endif ++ ++ifeq ($(CONFIG_SDIO_HCI), y) ++ ++HCI_NAME = sdio ++ ++_OS_INTFS_FILES := os_dep/osdep_service.o \ ++ os_dep/linux/os_intfs.o \ ++ os_dep/linux/sdio_intf.o \ ++ os_dep/linux/ioctl_linux.o \ ++ os_dep/linux/xmit_linux.o \ ++ os_dep/linux/mlme_linux.o \ ++ os_dep/linux/recv_linux.o \ ++ os_dep/linux/rtw_android.o ++ ++_HAL_INTFS_FILES := hal/$(RTL871X)/hal_init.o \ ++ hal/$(RTL871X)/sdio_halinit.o \ ++ hal/$(RTL871X)/sdio_ops.o \ ++ hal/$(RTL871X)/sdio_ops_linux.o ++ ++endif ++ ++ ++ifeq ($(CONFIG_USB_HCI), y) ++ ++HCI_NAME = usb ++ ++_OS_INTFS_FILES := os_dep/osdep_service.o \ ++ os_dep/linux/os_intfs.o \ ++ os_dep/linux/$(HCI_NAME)_intf.o \ ++ os_dep/linux/ioctl_linux.o \ ++ os_dep/linux/xmit_linux.o \ ++ os_dep/linux/mlme_linux.o \ ++ os_dep/linux/recv_linux.o \ ++ os_dep/linux/ioctl_cfg80211.o \ ++ os_dep/linux/rtw_android.o ++ ++_HAL_INTFS_FILES := hal/hal_init.o \ ++ hal/$(RTL871X)/$(RTL871X)_hal_init.o \ ++ hal/$(RTL871X)/$(RTL871X)_phycfg.o \ ++ hal/$(RTL871X)/$(RTL871X)_rf6052.o \ ++ hal/$(RTL871X)/$(RTL871X)_dm.o \ ++ hal/$(RTL871X)/$(RTL871X)_rxdesc.o \ ++ hal/$(RTL871X)/$(RTL871X)_cmd.o \ ++ hal/$(RTL871X)/$(RTL871X)_mp.o \ ++ hal/$(RTL871X)/usb/usb_ops_linux.o \ ++ hal/$(RTL871X)/usb/usb_halinit.o \ ++ hal/$(RTL871X)/usb/rtl$(MODULE_NAME)_led.o \ ++ hal/$(RTL871X)/usb/rtl$(MODULE_NAME)_xmit.o \ ++ hal/$(RTL871X)/usb/rtl$(MODULE_NAME)_recv.o ++ ++_HAL_INTFS_FILES += $(CHIP_FILES) ++ ++endif ++ ++ ++ifeq ($(CONFIG_PCI_HCI), y) ++ ++HCI_NAME = pci ++ ++_OS_INTFS_FILES := os_dep/osdep_service.o \ ++ os_dep/linux/os_intfs.o \ ++ os_dep/linux/$(HCI_NAME)_intf.o \ ++ os_dep/linux/ioctl_linux.o \ ++ os_dep/linux/xmit_linux.o \ ++ os_dep/linux/mlme_linux.o \ ++ os_dep/linux/recv_linux.o \ ++ os_dep/linux/rtw_android.o ++ ++_HAL_INTFS_FILES := hal/hal_init.o \ ++ hal/$(RTL871X)/$(RTL871X)_hal_init.o \ ++ hal/$(RTL871X)/$(RTL871X)_phycfg.o \ ++ hal/$(RTL871X)/$(RTL871X)_rf6052.o \ ++ hal/$(RTL871X)/$(RTL871X)_dm.o \ ++ hal/$(RTL871X)/$(RTL871X)_rxdesc.o \ ++ hal/$(RTL871X)/$(RTL871X)_cmd.o \ ++ hal/$(RTL871X)/$(RTL871X)_mp.o \ ++ hal/$(RTL871X)/pci/pci_ops_linux.o \ ++ hal/$(RTL871X)/pci/pci_halinit.o \ ++ hal/$(RTL871X)/pci/rtl$(MODULE_NAME)_led.o \ ++ hal/$(RTL871X)/pci/rtl$(MODULE_NAME)_xmit.o \ ++ hal/$(RTL871X)/pci/rtl$(MODULE_NAME)_recv.o ++ ++_HAL_INTFS_FILES += $(CHIP_FILES) ++ ++endif ++ ++ifeq ($(CONFIG_AUTOCFG_CP), y) ++$(shell cp $(TopDIR)/autoconf_$(RTL871X)_$(HCI_NAME)_linux.h $(TopDIR)/include/autoconf.h) ++endif ++ ++ ++ifeq ($(CONFIG_USB_HCI), y) ++ifeq ($(CONFIG_USB_AUTOSUSPEND), y) ++EXTRA_CFLAGS += -DCONFIG_USB_AUTOSUSPEND ++endif ++endif ++ ++ifeq ($(CONFIG_POWER_SAVING), y) ++EXTRA_CFLAGS += -DCONFIG_POWER_SAVING ++endif ++ ++ifeq ($(CONFIG_HW_PWRP_DETECTION), y) ++EXTRA_CFLAGS += -DCONFIG_HW_PWRP_DETECTION ++endif ++ ++ifeq ($(CONFIG_WIFI_TEST), y) ++EXTRA_CFLAGS += -DCONFIG_WIFI_TEST ++endif ++ ++ifeq ($(CONFIG_BT_COEXISTENCE), y) ++EXTRA_CFLAGS += -DCONFIG_BT_COEXISTENCE ++endif ++ ++ifeq ($(CONFIG_RTL8192CU_REDEFINE_1X1), y) ++EXTRA_CFLAGS += -DRTL8192C_RECONFIG_TO_1T1R ++endif ++ ++ifeq ($(CONFIG_WAKE_ON_WLAN), y) ++EXTRA_CFLAGS += -DCONFIG_WAKE_ON_WLAN ++endif ++ ++ifeq ($(CONFIG_PLATFORM_ARM_BCM2708), y) ++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN ++ARCH := arm ++CROSS_COMPILE ?= ++KVER := 3.2.27+ ++KSRC := /lib/modules/$(KVER)/build ++endif ++ ++ifeq ($(CONFIG_PLATFORM_I386_PC), y) ++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN ++SUBARCH := $(shell uname -m | sed -e s/i.86/i386/) ++ARCH ?= $(SUBARCH) ++CROSS_COMPILE ?= ++KVER := $(shell uname -r) ++KSRC := /lib/modules/$(KVER)/build ++MODDESTDIR := /lib/modules/$(KVER)/kernel/drivers/net/wireless/ ++INSTALL_PREFIX := ++endif ++ ++ifeq ($(CONFIG_PLATFORM_TI_AM3517), y) ++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_ANDROID -DCONFIG_PLATFORM_SHUTTLE ++CROSS_COMPILE := arm-eabi- ++KSRC := $(shell pwd)/../../../Android/kernel ++ARCH := arm ++endif ++ ++ifeq ($(CONFIG_PLATFORM_MSTAR_TITANIA12), y) ++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_MSTAR_TITANIA12 ++ARCH:=mips ++CROSS_COMPILE:= /work/mstar/mips-4.3/bin/mips-linux-gnu- ++KVER:= 2.6.28.9 ++KSRC:= /work/mstar/2.6.28.9/ ++endif ++ ++ifeq ($(CONFIG_PLATFORM_ANDROID_X86), y) ++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN ++SUBARCH := $(shell uname -m | sed -e s/i.86/i386/) ++ARCH := $(SUBARCH) ++CROSS_COMPILE := /media/DATA-2/android-x86/ics-x86_20120130/prebuilt/linux-x86/toolchain/i686-unknown-linux-gnu-4.2.1/bin/i686-unknown-linux-gnu- ++KSRC := /media/DATA-2/android-x86/ics-x86_20120130/out/target/product/generic_x86/obj/kernel ++MODULE_NAME :=wlan ++endif ++ ++ifeq ($(CONFIG_PLATFORM_ARM_PXA2XX), y) ++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN ++ARCH := arm ++CROSS_COMPILE := arm-none-linux-gnueabi- ++KVER := 2.6.34.1 ++KSRC ?= /usr/src/linux-2.6.34.1 ++endif ++ ++ifeq ($(CONFIG_PLATFORM_ARM_S3C2K4), y) ++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN ++ARCH := arm ++CROSS_COMPILE := arm-linux- ++KVER := 2.6.24.7_$(ARCH) ++KSRC := /usr/src/kernels/linux-$(KVER) ++endif ++ ++ifeq ($(CONFIG_PLATFORM_ARM_S3C6K4), y) ++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN ++ARCH := arm ++CROSS_COMPILE := arm-none-linux-gnueabi- ++KVER := 2.6.34.1 ++KSRC ?= /usr/src/linux-2.6.34.1 ++endif ++ ++ifeq ($(CONFIG_PLATFORM_RTD2880B), y) ++EXTRA_CFLAGS += -DCONFIG_BIG_ENDIAN -DCONFIG_PLATFORM_RTD2880B ++ARCH:= ++CROSS_COMPILE:= ++KVER:= ++KSRC:= ++endif ++ ++ifeq ($(CONFIG_PLATFORM_MIPS_RMI), y) ++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN ++ARCH:=mips ++CROSS_COMPILE:=mipsisa32r2-uclibc- ++KVER:= ++KSRC:= /root/work/kernel_realtek ++endif ++ ++ifeq ($(CONFIG_PLATFORM_MIPS_PLM), y) ++EXTRA_CFLAGS += -DCONFIG_BIG_ENDIAN ++ARCH:=mips ++CROSS_COMPILE:=mipsisa32r2-uclibc- ++KVER:= ++KSRC:= /root/work/kernel_realtek ++endif ++ ++ifeq ($(CONFIG_PLATFORM_MSTAR389), y) ++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_MSTAR389 ++ARCH:=mips ++CROSS_COMPILE:= mips-linux-gnu- ++KVER:= 2.6.28.10 ++KSRC:= /home/mstar/mstar_linux/2.6.28.9/ ++endif ++ ++ifeq ($(CONFIG_PLATFORM_MIPS_AR9132), y) ++EXTRA_CFLAGS += -DCONFIG_BIG_ENDIAN ++ARCH := mips ++CROSS_COMPILE := mips-openwrt-linux- ++KSRC := /home/alex/test_openwrt/tmp/linux-2.6.30.9 ++endif ++ ++ifeq ($(CONFIG_PLATFORM_DMP_PHILIPS), y) ++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DRTK_DMP_PLATFORM ++ARCH := mips ++#CROSS_COMPILE:=/usr/local/msdk-4.3.6-mips-EL-2.6.12.6-0.9.30.3/bin/mipsel-linux- ++CROSS_COMPILE:=/usr/local/toolchain_mipsel/bin/mipsel-linux- ++KSRC ?=/usr/local/Jupiter/linux-2.6.12 ++endif ++ ++ifeq ($(CONFIG_PLATFORM_RTK_DMP), y) ++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DRTK_DMP_PLATFORM ++ARCH:=mips ++CROSS_COMPILE:=mipsel-linux- ++KVER:= ++KSRC ?= /usr/src/work/DMP_Kernel/jupiter/linux-2.6.12 ++endif ++ ++ifeq ($(CONFIG_PLATFORM_MT53XX), y) ++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_MT53XX ++ARCH:= arm ++CROSS_COMPILE:= arm11_mtk_le- ++KVER:= 2.6.27 ++KSRC?= /proj/mtk00802/BD_Compare/BDP/Dev/BDP_V301/BDP_Linux/linux-2.6.27 ++endif ++ ++ifeq ($(CONFIG_PLATFORM_ARM_MX51_241H), y) ++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_WISTRON_PLATFORM ++ARCH := arm ++CROSS_COMPILE := /opt/freescale/usr/local/gcc-4.1.2-glibc-2.5-nptl-3/arm-none-linux-gnueabi/bin/arm-none-linux-gnueabi- ++KVER := 2.6.31 ++KSRC ?= /lib/modules/2.6.31-770-g0e46b52/source ++endif ++ ++ifeq ($(CONFIG_PLATFORM_ACTIONS_ATJ227X), y) ++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_ACTIONS_ATJ227X ++ARCH := mips ++CROSS_COMPILE := /home/cnsd4/project/actions/tools-2.6.27/bin/mipsel-linux-gnu- ++KVER := 2.6.27 ++KSRC := /home/cnsd4/project/actions/linux-2.6.27.28 ++endif ++ ++ifeq ($(CONFIG_PLATFORM_TI_DM365), y) ++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_TI_DM365 ++ARCH := arm ++CROSS_COMPILE := /home/cnsd4/Appro/mv_pro_5.0/montavista/pro/devkit/arm/v5t_le/bin/arm_v5t_le- ++KVER := 2.6.18 ++KSRC := /home/cnsd4/Appro/mv_pro_5.0/montavista/pro/devkit/lsp/ti-davinci/linux-dm365 ++endif ++ ++ifeq ($(CONFIG_PLATFORM_ARM_TEGRA3), y) ++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN #-DCONFIG_MINIMAL_MEMORY_USAGE ++ARCH ?= arm ++CROSS_COMPILE ?= /media/DATA-1/nvidia/gingerbread/prebuilt/linux-x86/toolchain/arm-eabi-4.4.3/bin/arm-eabi- ++KSRC ?= /media/DATA-1/nvidia/gingerbread/out/debug/target/product/cardhu/obj/KERNEL ++MODULE_NAME := wlan ++endif ++ ++ifeq ($(CONFIG_PLATFORM_ARM_TCC8900), y) ++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_MINIMAL_MEMORY_USAGE ++ARCH ?= arm ++CROSS_COMPILE ?= /media/DATA-1/telechips/SDK_2302_20110425/prebuilt/linux-x86/toolchain/arm-eabi-4.4.3/bin/arm-eabi- ++KSRC ?=/media/DATA-1/telechips/SDK_2302_20110425/kernel ++MODULE_NAME := wlan ++endif ++ ++ifeq ($(CONFIG_PLATFORM_ARM_TCC8920), y) ++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN #-DCONFIG_MINIMAL_MEMORY_USAGE ++ARCH := arm ++CROSS_COMPILE := /media/DATA-2/telechips/ics_sdk/prebuilt/linux-x86/toolchain/arm-eabi-4.4.3/bin/arm-eabi- ++KSRC := /media/DATA-2/telechips/ics_sdk/kernel ++MODULE_NAME := wlan ++endif ++ ++ifeq ($(CONFIG_PLATFORM_ARM_RK2818), y) ++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_ANDROID -DCONFIG_PLATFORM_ROCKCHIPS -DCONFIG_MINIMAL_MEMORY_USAGE ++ARCH := arm ++CROSS_COMPILE := /usr/src/release_fae_version/toolchain/arm-eabi-4.4.0/bin/arm-eabi- ++KSRC := /usr/src/release_fae_version/kernel25_A7_281x ++MODULE_NAME := wlan ++endif ++ ++ifeq ($(CONFIG_PLATFORM_ARM_TI_PANDA), y) ++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN #-DCONFIG_MINIMAL_MEMORY_USAGE ++ARCH := arm ++#CROSS_COMPILE := /media/DATA-1/aosp/ics-aosp_20111227/prebuilt/linux-x86/toolchain/arm-eabi-4.4.3/bin/arm-eabi- ++#KSRC := /media/DATA-1/aosp/android-omap-panda-3.0_20120104 ++CROSS_COMPILE := /media/DATA-1/android-4.0/prebuilt/linux-x86/toolchain/arm-eabi-4.4.3/bin/arm-eabi- ++KSRC := /media/DATA-1/android-4.0/panda_kernel/omap ++MODULE_NAME := wlan ++endif ++ ++ifeq ($(CONFIG_PLATFORM_MIPS_JZ4760), y) ++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_MINIMAL_MEMORY_USAGE ++ARCH ?= mips ++CROSS_COMPILE ?= /mnt/sdb5/Ingenic/Umido/mips-4.3/bin/mips-linux-gnu- ++KSRC ?= /mnt/sdb5/Ingenic/Umido/kernel ++endif ++ ++#Add setting for MN10300 ++ifeq ($(CONFIG_PLATFORM_MN10300), y) ++EXTRA_CFLAGS += -DCONFIG_LITTLE_ENDIAN -DCONFIG_PLATFORM_MN10300 ++ARCH := mn10300 ++CROSS_COMPILE := mn10300-linux- ++KVER := 2.6.32.2 ++KSRC := /home/winuser/work/Plat_sLD2T_V3010/usr/src/linux-2.6.32.2 ++INSTALL_PREFIX := ++endif ++ ++ifeq ($(CONFIG_MP_INCLUDED), y) ++MODULE_NAME := $(MODULE_NAME)_mp ++EXTRA_CFLAGS += -DCONFIG_MP_INCLUDED ++endif ++ ++ifneq ($(KERNELRELEASE),) ++ ++ ++rtk_core := core/rtw_cmd.o \ ++ core/rtw_security.o \ ++ core/rtw_debug.o \ ++ core/rtw_io.o \ ++ core/rtw_ioctl_query.o \ ++ core/rtw_ioctl_set.o \ ++ core/rtw_ieee80211.o \ ++ core/rtw_mlme.o \ ++ core/rtw_mlme_ext.o \ ++ core/rtw_wlan_util.o \ ++ core/rtw_pwrctrl.o \ ++ core/rtw_rf.o \ ++ core/rtw_recv.o \ ++ core/rtw_sta_mgt.o \ ++ core/rtw_xmit.o \ ++ core/rtw_p2p.o \ ++ core/rtw_br_ext.o \ ++ core/rtw_iol.o ++ ++$(MODULE_NAME)-y += $(rtk_core) ++ ++$(MODULE_NAME)-y += core/efuse/rtw_efuse.o ++ ++$(MODULE_NAME)-y += $(_HAL_INTFS_FILES) ++ ++$(MODULE_NAME)-y += $(_OS_INTFS_FILES) ++ ++ ++$(MODULE_NAME)-$(CONFIG_MP_INCLUDED) += core/rtw_mp.o \ ++ core/rtw_mp_ioctl.o \ ++ core/rtw_ioctl_rtl.o ++ ++obj-$(CONFIG_RTL8192CU) := $(MODULE_NAME).o ++ ++else ++ ++export CONFIG_RTL8192CU = m ++ ++all: modules ++ ++modules: ++ $(MAKE) ARCH=$(ARCH) CROSS_COMPILE=$(CROSS_COMPILE) -C $(KSRC) M=$(shell pwd) modules ++ ++strip: ++ $(CROSS_COMPILE)strip $(MODULE_NAME).ko --strip-unneeded ++ ++install: ++ install -p -m 644 $(MODULE_NAME).ko $(MODDESTDIR) ++ /sbin/depmod -a ${KVER} ++ ++uninstall: ++ rm -f $(MODDESTDIR)/$(MODULE_NAME).ko ++ /sbin/depmod -a ${KVER} ++ ++ ++config_r: ++ @echo "make config" ++ /bin/bash script/Configure script/config.in ++ ++.PHONY: modules clean ++ ++clean: ++ rm -fr *.mod.c *.mod *.o .*.cmd *.ko *~ ++ rm .tmp_versions -fr ; rm Module.symvers -fr ++ rm -fr Module.markers ; rm -fr modules.order ++ cd core/efuse ; rm -fr *.mod.c *.mod *.o .*.cmd *.ko ++ cd core ; rm -fr *.mod.c *.mod *.o .*.cmd *.ko ++ cd hal/$(RTL871X)/$(HCI_NAME) ; rm -fr *.mod.c *.mod *.o .*.cmd *.ko ++ cd hal/$(RTL871X) ; rm -fr *.mod.c *.mod *.o .*.cmd *.ko ++ cd hal ; rm -fr *.mod.c *.mod *.o .*.cmd *.ko ++ cd os_dep/linux ; rm -fr *.mod.c *.mod *.o .*.cmd *.ko ++ cd os_dep ; rm -fr *.mod.c *.mod *.o .*.cmd *.ko ++endif ++ +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/clean +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/clean 2013-07-26 19:36:04.000000000 +0000 +@@ -0,0 +1,9 @@ ++#!/bin/bash ++rmmod 8192cu ++rmmod 8192ce ++rmmod 8192du ++rmmod 8192de ++ ++rmmod rtl8192cu ++rmmod rtl8192c_common ++rmmod rtlwifi +\ No newline at end of file +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/core/efuse/rtw_efuse.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/core/efuse/rtw_efuse.c 2013-07-26 19:36:04.000000000 +0000 +@@ -0,0 +1,1097 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#define _RTW_EFUSE_C_ ++ ++#include ++#include ++#include ++ ++#include ++ ++ ++ ++/*------------------------Define local variable------------------------------*/ ++u8 fakeEfuseBank=0; ++u32 fakeEfuseUsedBytes=0; ++u8 fakeEfuseContent[EFUSE_MAX_HW_SIZE]={0}; ++u8 fakeEfuseInitMap[EFUSE_MAX_MAP_LEN]={0}; ++u8 fakeEfuseModifiedMap[EFUSE_MAX_MAP_LEN]={0}; ++ ++u32 BTEfuseUsedBytes=0; ++u8 BTEfuseContent[EFUSE_MAX_BT_BANK][EFUSE_MAX_HW_SIZE]; ++u8 BTEfuseInitMap[EFUSE_BT_MAX_MAP_LEN]={0}; ++u8 BTEfuseModifiedMap[EFUSE_BT_MAX_MAP_LEN]={0}; ++ ++u32 fakeBTEfuseUsedBytes=0; ++u8 fakeBTEfuseContent[EFUSE_MAX_BT_BANK][EFUSE_MAX_HW_SIZE]; ++u8 fakeBTEfuseInitMap[EFUSE_BT_MAX_MAP_LEN]={0}; ++u8 fakeBTEfuseModifiedMap[EFUSE_BT_MAX_MAP_LEN]={0}; ++/*------------------------Define local variable------------------------------*/ ++ ++//------------------------------------------------------------------------------ ++#define REG_EFUSE_CTRL 0x0030 ++#define EFUSE_CTRL REG_EFUSE_CTRL // E-Fuse Control. ++//------------------------------------------------------------------------------ ++ ++BOOLEAN ++Efuse_Read1ByteFromFakeContent( ++ IN PADAPTER pAdapter, ++ IN u16 Offset, ++ IN OUT u8 *Value ) ++{ ++ if(Offset >= EFUSE_MAX_HW_SIZE) ++ { ++ return _FALSE; ++ } ++ //DbgPrint("Read fake content, offset = %d\n", Offset); ++ if(fakeEfuseBank == 0) ++ *Value = fakeEfuseContent[Offset]; ++ else ++ *Value = fakeBTEfuseContent[fakeEfuseBank-1][Offset]; ++ return _TRUE; ++} ++BOOLEAN ++Efuse_Write1ByteToFakeContent( ++ IN PADAPTER pAdapter, ++ IN u16 Offset, ++ IN u8 Value ) ++{ ++ if(Offset >= EFUSE_MAX_HW_SIZE) ++ { ++ return _FALSE; ++ } ++ if(fakeEfuseBank == 0) ++ fakeEfuseContent[Offset] = Value; ++ else ++ { ++ fakeBTEfuseContent[fakeEfuseBank-1][Offset] = Value; ++ } ++ return _TRUE; ++} ++ ++/*----------------------------------------------------------------------------- ++ * Function: Efuse_PowerSwitch ++ * ++ * Overview: When we want to enable write operation, we should change to ++ * pwr on state. When we stop write, we should switch to 500k mode ++ * and disable LDO 2.5V. ++ * ++ * Input: NONE ++ * ++ * Output: NONE ++ * ++ * Return: NONE ++ * ++ * Revised History: ++ * When Who Remark ++ * 11/17/2008 MHC Create Version 0. ++ * ++ *---------------------------------------------------------------------------*/ ++VOID ++Efuse_PowerSwitch( ++ IN PADAPTER pAdapter, ++ IN u8 bWrite, ++ IN u8 PwrState) ++{ ++ pAdapter->HalFunc.EfusePowerSwitch(pAdapter, bWrite, PwrState); ++} ++ ++/*----------------------------------------------------------------------------- ++ * Function: efuse_GetCurrentSize ++ * ++ * Overview: Get current efuse size!!! ++ * ++ * Input: NONE ++ * ++ * Output: NONE ++ * ++ * Return: NONE ++ * ++ * Revised History: ++ * When Who Remark ++ * 11/16/2008 MHC Create Version 0. ++ * ++ *---------------------------------------------------------------------------*/ ++u16 ++Efuse_GetCurrentSize( ++ IN PADAPTER pAdapter, ++ IN u8 efuseType, ++ IN BOOLEAN bPseudoTest) ++{ ++ u16 ret=0; ++ ++ ret = pAdapter->HalFunc.EfuseGetCurrentSize(pAdapter, efuseType, bPseudoTest); ++ ++ return ret; ++} ++ ++/* 11/16/2008 MH Add description. Get current efuse area enabled word!!. */ ++u8 ++Efuse_CalculateWordCnts(IN u8 word_en) ++{ ++ u8 word_cnts = 0; ++ if(!(word_en & BIT(0))) word_cnts++; // 0 : write enable ++ if(!(word_en & BIT(1))) word_cnts++; ++ if(!(word_en & BIT(2))) word_cnts++; ++ if(!(word_en & BIT(3))) word_cnts++; ++ return word_cnts; ++} ++ ++// ++// Description: ++// Execute E-Fuse read byte operation. ++// Refered from SD1 Richard. ++// ++// Assumption: ++// 1. Boot from E-Fuse and successfully auto-load. ++// 2. PASSIVE_LEVEL (USB interface) ++// ++// Created by Roger, 2008.10.21. ++// ++VOID ++ReadEFuseByte( ++ PADAPTER Adapter, ++ u16 _offset, ++ u8 *pbuf, ++ IN BOOLEAN bPseudoTest) ++{ ++ u32 value32; ++ u8 readbyte; ++ u16 retry; ++ //u32 start=rtw_get_current_time(); ++ ++ if(bPseudoTest) ++ { ++ Efuse_Read1ByteFromFakeContent(Adapter, _offset, pbuf); ++ return; ++ } ++ ++ //Write Address ++ rtw_write8(Adapter, EFUSE_CTRL+1, (_offset & 0xff)); ++ readbyte = rtw_read8(Adapter, EFUSE_CTRL+2); ++ rtw_write8(Adapter, EFUSE_CTRL+2, ((_offset >> 8) & 0x03) | (readbyte & 0xfc)); ++ ++ //Write bit 32 0 ++ readbyte = rtw_read8(Adapter, EFUSE_CTRL+3); ++ rtw_write8(Adapter, EFUSE_CTRL+3, (readbyte & 0x7f)); ++ ++ //Check bit 32 read-ready ++ retry = 0; ++ value32 = rtw_read32(Adapter, EFUSE_CTRL); ++ //while(!(((value32 >> 24) & 0xff) & 0x80) && (retry<10)) ++ while(!(((value32 >> 24) & 0xff) & 0x80) && (retry<10000)) ++ { ++ value32 = rtw_read32(Adapter, EFUSE_CTRL); ++ retry++; ++ } ++ ++ // 20100205 Joseph: Add delay suggested by SD1 Victor. ++ // This fix the problem that Efuse read error in high temperature condition. ++ // Designer says that there shall be some delay after ready bit is set, or the ++ // result will always stay on last data we read. ++ rtw_udelay_os(50); ++ value32 = rtw_read32(Adapter, EFUSE_CTRL); ++ ++ *pbuf = (u8)(value32 & 0xff); ++ //MSG_8192C("ReadEFuseByte _offset:%08u, in %d ms\n",_offset ,rtw_get_passing_time_ms(start)); ++ ++} ++ ++ ++// ++// Description: ++// 1. Execute E-Fuse read byte operation according as map offset and ++// save to E-Fuse table. ++// 2. Refered from SD1 Richard. ++// ++// Assumption: ++// 1. Boot from E-Fuse and successfully auto-load. ++// 2. PASSIVE_LEVEL (USB interface) ++// ++// Created by Roger, 2008.10.21. ++// ++// 2008/12/12 MH 1. Reorganize code flow and reserve bytes. and add description. ++// 2. Add efuse utilization collect. ++// 2008/12/22 MH Read Efuse must check if we write section 1 data again!!! Sec1 ++// write addr must be after sec5. ++// ++VOID ++efuse_ReadEFuse( ++ PADAPTER Adapter, ++ u8 efuseType, ++ u16 _offset, ++ u16 _size_byte, ++ u8 *pbuf, ++ IN BOOLEAN bPseudoTest ++ ) ++{ ++ Adapter->HalFunc.ReadEFuse(Adapter, efuseType, _offset, _size_byte, pbuf, bPseudoTest); ++} ++ ++VOID ++EFUSE_GetEfuseDefinition( ++ IN PADAPTER pAdapter, ++ IN u8 efuseType, ++ IN u8 type, ++ OUT PVOID *pOut, ++ IN BOOLEAN bPseudoTest ++ ) ++{ ++ pAdapter->HalFunc.EFUSEGetEfuseDefinition(pAdapter, efuseType, type, pOut, bPseudoTest); ++} ++ ++/*----------------------------------------------------------------------------- ++ * Function: EFUSE_Read1Byte ++ * ++ * Overview: Copy from WMAC fot EFUSE read 1 byte. ++ * ++ * Input: NONE ++ * ++ * Output: NONE ++ * ++ * Return: NONE ++ * ++ * Revised History: ++ * When Who Remark ++ * 09/23/2008 MHC Copy from WMAC. ++ * ++ *---------------------------------------------------------------------------*/ ++u8 ++EFUSE_Read1Byte( ++ IN PADAPTER Adapter, ++ IN u16 Address) ++{ ++ u8 data; ++ u8 Bytetemp = {0x00}; ++ u8 temp = {0x00}; ++ u32 k=0; ++ u16 contentLen=0; ++ ++ EFUSE_GetEfuseDefinition(Adapter, EFUSE_WIFI , TYPE_EFUSE_REAL_CONTENT_LEN, (PVOID)&contentLen, _FALSE); ++ ++ if (Address < contentLen) //E-fuse 512Byte ++ { ++ //Write E-fuse Register address bit0~7 ++ temp = Address & 0xFF; ++ rtw_write8(Adapter, EFUSE_CTRL+1, temp); ++ Bytetemp = rtw_read8(Adapter, EFUSE_CTRL+2); ++ //Write E-fuse Register address bit8~9 ++ temp = ((Address >> 8) & 0x03) | (Bytetemp & 0xFC); ++ rtw_write8(Adapter, EFUSE_CTRL+2, temp); ++ ++ //Write 0x30[31]=0 ++ Bytetemp = rtw_read8(Adapter, EFUSE_CTRL+3); ++ temp = Bytetemp & 0x7F; ++ rtw_write8(Adapter, EFUSE_CTRL+3, temp); ++ ++ //Wait Write-ready (0x30[31]=1) ++ Bytetemp = rtw_read8(Adapter, EFUSE_CTRL+3); ++ while(!(Bytetemp & 0x80)) ++ { ++ Bytetemp = rtw_read8(Adapter, EFUSE_CTRL+3); ++ k++; ++ if(k==1000) ++ { ++ k=0; ++ break; ++ } ++ } ++ data=rtw_read8(Adapter, EFUSE_CTRL); ++ return data; ++ } ++ else ++ return 0xFF; ++ ++}/* EFUSE_Read1Byte */ ++ ++/*----------------------------------------------------------------------------- ++ * Function: EFUSE_Write1Byte ++ * ++ * Overview: Copy from WMAC fot EFUSE write 1 byte. ++ * ++ * Input: NONE ++ * ++ * Output: NONE ++ * ++ * Return: NONE ++ * ++ * Revised History: ++ * When Who Remark ++ * 09/23/2008 MHC Copy from WMAC. ++ * ++ *---------------------------------------------------------------------------*/ ++void ++EFUSE_Write1Byte( ++ IN PADAPTER Adapter, ++ IN u16 Address, ++ IN u8 Value) ++{ ++ u8 Bytetemp = {0x00}; ++ u8 temp = {0x00}; ++ u32 k=0; ++ u16 contentLen=0; ++ ++ //RT_TRACE(COMP_EFUSE, DBG_LOUD, ("Addr=%x Data =%x\n", Address, Value)); ++ EFUSE_GetEfuseDefinition(Adapter, EFUSE_WIFI , TYPE_EFUSE_REAL_CONTENT_LEN, (PVOID)&contentLen, _FALSE); ++ ++ if( Address < contentLen) //E-fuse 512Byte ++ { ++ rtw_write8(Adapter, EFUSE_CTRL, Value); ++ ++ //Write E-fuse Register address bit0~7 ++ temp = Address & 0xFF; ++ rtw_write8(Adapter, EFUSE_CTRL+1, temp); ++ Bytetemp = rtw_read8(Adapter, EFUSE_CTRL+2); ++ ++ //Write E-fuse Register address bit8~9 ++ temp = ((Address >> 8) & 0x03) | (Bytetemp & 0xFC); ++ rtw_write8(Adapter, EFUSE_CTRL+2, temp); ++ ++ //Write 0x30[31]=1 ++ Bytetemp = rtw_read8(Adapter, EFUSE_CTRL+3); ++ temp = Bytetemp | 0x80; ++ rtw_write8(Adapter, EFUSE_CTRL+3, temp); ++ ++ //Wait Write-ready (0x30[31]=0) ++ Bytetemp = rtw_read8(Adapter, EFUSE_CTRL+3); ++ while(Bytetemp & 0x80) ++ { ++ Bytetemp = rtw_read8(Adapter, EFUSE_CTRL+3); ++ k++; ++ if(k==100) ++ { ++ k=0; ++ break; ++ } ++ } ++ } ++}/* EFUSE_Write1Byte */ ++ ++/* 11/16/2008 MH Read one byte from real Efuse. */ ++u8 ++efuse_OneByteRead( ++ IN PADAPTER pAdapter, ++ IN u16 addr, ++ IN u8 *data, ++ IN BOOLEAN bPseudoTest) ++{ ++ u8 tmpidx = 0; ++ u8 bResult; ++ ++ if(bPseudoTest) ++ { ++ bResult = Efuse_Read1ByteFromFakeContent(pAdapter, addr, data); ++ return bResult; ++ } ++ // -----------------e-fuse reg ctrl --------------------------------- ++ //address ++ rtw_write8(pAdapter, EFUSE_CTRL+1, (u8)(addr&0xff)); ++ rtw_write8(pAdapter, EFUSE_CTRL+2, ((u8)((addr>>8) &0x03) ) | ++ (rtw_read8(pAdapter, EFUSE_CTRL+2)&0xFC )); ++ ++ rtw_write8(pAdapter, EFUSE_CTRL+3, 0x72);//read cmd ++ ++ while(!(0x80 &rtw_read8(pAdapter, EFUSE_CTRL+3))&&(tmpidx<100)) ++ { ++ tmpidx++; ++ } ++ if(tmpidx<100) ++ { ++ *data=rtw_read8(pAdapter, EFUSE_CTRL); ++ bResult = _TRUE; ++ } ++ else ++ { ++ *data = 0xff; ++ bResult = _FALSE; ++ } ++ return bResult; ++} ++ ++/* 11/16/2008 MH Write one byte to reald Efuse. */ ++u8 ++efuse_OneByteWrite( ++ IN PADAPTER pAdapter, ++ IN u16 addr, ++ IN u8 data, ++ IN BOOLEAN bPseudoTest) ++{ ++ u8 tmpidx = 0; ++ u8 bResult; ++ ++ if(bPseudoTest) ++ { ++ bResult = Efuse_Write1ByteToFakeContent(pAdapter, addr, data); ++ return bResult; ++ } ++ //RT_TRACE(COMP_EFUSE, DBG_LOUD, ("Addr = %x Data=%x\n", addr, data)); ++ ++ //return 0; ++ ++ // -----------------e-fuse reg ctrl --------------------------------- ++ //address ++ rtw_write8(pAdapter, EFUSE_CTRL+1, (u8)(addr&0xff)); ++ rtw_write8(pAdapter, EFUSE_CTRL+2, ++ (rtw_read8(pAdapter, EFUSE_CTRL+2)&0xFC )|(u8)((addr>>8)&0x03) ); ++ rtw_write8(pAdapter, EFUSE_CTRL, data);//data ++ ++ rtw_write8(pAdapter, EFUSE_CTRL+3, 0xF2);//write cmd ++ ++ while((0x80 & rtw_read8(pAdapter, EFUSE_CTRL+3)) && (tmpidx<100) ){ ++ tmpidx++; ++ } ++ ++ if(tmpidx<100) ++ { ++ bResult = _TRUE; ++ } ++ else ++ { ++ bResult = _FALSE; ++ } ++ ++ return bResult; ++} ++ ++int ++Efuse_PgPacketRead( IN PADAPTER pAdapter, ++ IN u8 offset, ++ IN u8 *data, ++ IN BOOLEAN bPseudoTest) ++{ ++ int ret=0; ++ ++ ret = pAdapter->HalFunc.Efuse_PgPacketRead(pAdapter, offset, data, bPseudoTest); ++ ++ return ret; ++} ++ ++int ++Efuse_PgPacketWrite(IN PADAPTER pAdapter, ++ IN u8 offset, ++ IN u8 word_en, ++ IN u8 *data, ++ IN BOOLEAN bPseudoTest) ++{ ++ int ret; ++ ++ ret = pAdapter->HalFunc.Efuse_PgPacketWrite(pAdapter, offset, word_en, data, bPseudoTest); ++ ++ return ret; ++} ++ ++/*----------------------------------------------------------------------------- ++ * Function: efuse_WordEnableDataRead ++ * ++ * Overview: Read allowed word in current efuse section data. ++ * ++ * Input: NONE ++ * ++ * Output: NONE ++ * ++ * Return: NONE ++ * ++ * Revised History: ++ * When Who Remark ++ * 11/16/2008 MHC Create Version 0. ++ * 11/21/2008 MHC Fix Write bug when we only enable late word. ++ * ++ *---------------------------------------------------------------------------*/ ++void ++efuse_WordEnableDataRead(IN u8 word_en, ++ IN u8 *sourdata, ++ IN u8 *targetdata) ++{ ++ if (!(word_en&BIT(0))) ++ { ++ targetdata[0] = sourdata[0]; ++ targetdata[1] = sourdata[1]; ++ } ++ if (!(word_en&BIT(1))) ++ { ++ targetdata[2] = sourdata[2]; ++ targetdata[3] = sourdata[3]; ++ } ++ if (!(word_en&BIT(2))) ++ { ++ targetdata[4] = sourdata[4]; ++ targetdata[5] = sourdata[5]; ++ } ++ if (!(word_en&BIT(3))) ++ { ++ targetdata[6] = sourdata[6]; ++ targetdata[7] = sourdata[7]; ++ } ++} ++ ++ ++u8 ++Efuse_WordEnableDataWrite( IN PADAPTER pAdapter, ++ IN u16 efuse_addr, ++ IN u8 word_en, ++ IN u8 *data, ++ IN BOOLEAN bPseudoTest) ++{ ++ u8 ret=0; ++ ++ ret = pAdapter->HalFunc.Efuse_WordEnableDataWrite(pAdapter, efuse_addr, word_en, data, bPseudoTest); ++ ++ return ret; ++} ++ ++static u8 efuse_read8(PADAPTER padapter, u16 address, u8 *value) ++{ ++ return efuse_OneByteRead(padapter,address, value, _FALSE); ++} ++ ++static u8 efuse_write8(PADAPTER padapter, u16 address, u8 *value) ++{ ++ return efuse_OneByteWrite(padapter,address, *value, _FALSE); ++} ++ ++/* ++ * read/wirte raw efuse data ++ */ ++u8 rtw_efuse_access(PADAPTER padapter, u8 bWrite, u16 start_addr, u16 cnts, u8 *data) ++{ ++ int i = 0; ++ u16 real_content_len = 0, max_available_size = 0; ++ u8 res = _FAIL ; ++ u8 (*rw8)(PADAPTER, u16, u8*); ++ ++ EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_REAL_CONTENT_LEN, (PVOID)&real_content_len, _FALSE); ++ EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_AVAILABLE_EFUSE_BYTES_TOTAL, (PVOID)&max_available_size, _FALSE); ++ ++ if (start_addr > real_content_len) ++ return _FAIL; ++ ++ if (_TRUE == bWrite) { ++ if ((start_addr + cnts) > max_available_size) ++ return _FAIL; ++ rw8 = &efuse_write8; ++ } else ++ rw8 = &efuse_read8; ++ ++ Efuse_PowerSwitch(padapter, bWrite, _TRUE); ++ ++ // e-fuse one byte read / write ++ for (i = 0; i < cnts; i++) { ++ if (start_addr >= real_content_len) { ++ res = _FAIL; ++ break; ++ } ++ ++ res = rw8(padapter, start_addr++, data++); ++ if (_FAIL == res) break; ++ } ++ ++ Efuse_PowerSwitch(padapter, bWrite, _FALSE); ++ ++ return res; ++} ++//------------------------------------------------------------------------------ ++u16 efuse_GetMaxSize(PADAPTER padapter) ++{ ++ u16 max_size; ++ EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI , TYPE_AVAILABLE_EFUSE_BYTES_TOTAL, (PVOID)&max_size, _FALSE); ++ return max_size; ++} ++//------------------------------------------------------------------------------ ++u8 efuse_GetCurrentSize(PADAPTER padapter, u16 *size) ++{ ++ Efuse_PowerSwitch(padapter, _FALSE, _TRUE); ++ *size = Efuse_GetCurrentSize(padapter, EFUSE_WIFI, _FALSE); ++ Efuse_PowerSwitch(padapter, _FALSE, _FALSE); ++ ++ return _SUCCESS; ++} ++//------------------------------------------------------------------------------ ++u8 rtw_efuse_map_read(PADAPTER padapter, u16 addr, u16 cnts, u8 *data) ++{ ++ u16 mapLen=0; ++ ++ EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_MAP_LEN, (PVOID)&mapLen, _FALSE); ++ ++ if ((addr + cnts) > mapLen) ++ return _FAIL; ++ ++ Efuse_PowerSwitch(padapter, _FALSE, _TRUE); ++ ++ efuse_ReadEFuse(padapter, EFUSE_WIFI, addr, cnts, data, _FALSE); ++ ++ Efuse_PowerSwitch(padapter, _FALSE, _FALSE); ++ ++ return _SUCCESS; ++} ++//------------------------------------------------------------------------------ ++u8 rtw_efuse_map_write(PADAPTER padapter, u16 addr, u16 cnts, u8 *data) ++{ ++ u8 offset, word_en; ++ u8 *map; ++ u8 newdata[PGPKT_DATA_SIZE]; ++ s32 i, j, idx; ++ u8 ret = _SUCCESS; ++ u16 mapLen=0; ++ ++ EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_MAP_LEN, (PVOID)&mapLen, _FALSE); ++ ++ if ((addr + cnts) > mapLen) ++ return _FAIL; ++ ++ map = rtw_zmalloc(mapLen); ++ if(map == NULL){ ++ return _FAIL; ++ } ++ ++ ret = rtw_efuse_map_read(padapter, 0, mapLen, map); ++ if (ret == _FAIL) goto exit; ++ ++ Efuse_PowerSwitch(padapter, _TRUE, _TRUE); ++ ++ offset = (addr >> 3); ++ word_en = 0xF; ++ _rtw_memset(newdata, 0xFF, PGPKT_DATA_SIZE); ++ i = addr & 0x7; // index of one package ++ j = 0; // index of new package ++ idx = 0; // data index ++ ++ if (i & 0x1) { ++ // odd start ++ if (data[idx] != map[addr+idx]) { ++ word_en &= ~BIT(i >> 1); ++ newdata[i-1] = map[addr+idx-1]; ++ newdata[i] = data[idx]; ++ } ++ i++; ++ idx++; ++ } ++ do { ++ for (; i < PGPKT_DATA_SIZE; i += 2) ++ { ++ if (cnts == idx) break; ++ if ((cnts - idx) == 1) { ++ if (data[idx] != map[addr+idx]) { ++ word_en &= ~BIT(i >> 1); ++ newdata[i] = data[idx]; ++ newdata[i+1] = map[addr+idx+1]; ++ } ++ idx++; ++ break; ++ } else { ++ if ((data[idx] != map[addr+idx]) || ++ (data[idx+1] != map[addr+idx+1])) ++ { ++ word_en &= ~BIT(i >> 1); ++ newdata[i] = data[idx]; ++ newdata[i+1] = data[idx + 1]; ++ } ++ idx += 2; ++ } ++ if (idx == cnts) break; ++ } ++ ++ if (word_en != 0xF) { ++ ret = Efuse_PgPacketWrite(padapter, offset, word_en, newdata, _FALSE); ++ DBG_8192C("offset=%x \n",offset); ++ DBG_8192C("word_en=%x \n",word_en); ++ ++ for(i=0;iefuse_eeprom_data[Offset]; ++ ++} // EFUSE_ShadowRead1Byte ++ ++//---------------Read Two Bytes ++static VOID ++efuse_ShadowRead2Byte( ++ IN PADAPTER pAdapter, ++ IN u16 Offset, ++ IN OUT u16 *Value) ++{ ++ EEPROM_EFUSE_PRIV *pEEPROM = GET_EEPROM_EFUSE_PRIV(pAdapter); ++ ++ *Value = pEEPROM->efuse_eeprom_data[Offset]; ++ *Value |= pEEPROM->efuse_eeprom_data[Offset+1]<<8; ++ ++} // EFUSE_ShadowRead2Byte ++ ++//---------------Read Four Bytes ++static VOID ++efuse_ShadowRead4Byte( ++ IN PADAPTER pAdapter, ++ IN u16 Offset, ++ IN OUT u32 *Value) ++{ ++ EEPROM_EFUSE_PRIV *pEEPROM = GET_EEPROM_EFUSE_PRIV(pAdapter); ++ ++ *Value = pEEPROM->efuse_eeprom_data[Offset]; ++ *Value |= pEEPROM->efuse_eeprom_data[Offset+1]<<8; ++ *Value |= pEEPROM->efuse_eeprom_data[Offset+2]<<16; ++ *Value |= pEEPROM->efuse_eeprom_data[Offset+3]<<24; ++ ++} // efuse_ShadowRead4Byte ++ ++ ++/*----------------------------------------------------------------------------- ++ * Function: efuse_ShadowWrite1Byte ++ * efuse_ShadowWrite2Byte ++ * efuse_ShadowWrite4Byte ++ * ++ * Overview: Write efuse modify map by one/two/four byte. ++ * ++ * Input: NONE ++ * ++ * Output: NONE ++ * ++ * Return: NONE ++ * ++ * Revised History: ++ * When Who Remark ++ * 11/12/2008 MHC Create Version 0. ++ * ++ *---------------------------------------------------------------------------*/ ++static VOID ++efuse_ShadowWrite1Byte( ++ IN PADAPTER pAdapter, ++ IN u16 Offset, ++ IN u8 Value) ++{ ++ EEPROM_EFUSE_PRIV *pEEPROM = GET_EEPROM_EFUSE_PRIV(pAdapter); ++ ++ pEEPROM->efuse_eeprom_data[Offset] = Value; ++ ++} // efuse_ShadowWrite1Byte ++ ++//---------------Write Two Bytes ++static VOID ++efuse_ShadowWrite2Byte( ++ IN PADAPTER pAdapter, ++ IN u16 Offset, ++ IN u16 Value) ++{ ++ EEPROM_EFUSE_PRIV *pEEPROM = GET_EEPROM_EFUSE_PRIV(pAdapter); ++ ++ pEEPROM->efuse_eeprom_data[Offset] = Value&0x00FF; ++ pEEPROM->efuse_eeprom_data[Offset+1] = Value>>8; ++ ++} // efuse_ShadowWrite1Byte ++ ++//---------------Write Four Bytes ++static VOID ++efuse_ShadowWrite4Byte( ++ IN PADAPTER pAdapter, ++ IN u16 Offset, ++ IN u32 Value) ++{ ++ EEPROM_EFUSE_PRIV *pEEPROM = GET_EEPROM_EFUSE_PRIV(pAdapter); ++ ++ pEEPROM->efuse_eeprom_data[Offset] = (u8)(Value&0x000000FF); ++ pEEPROM->efuse_eeprom_data[Offset+1] = (u8)((Value>>8)&0x0000FF); ++ pEEPROM->efuse_eeprom_data[Offset+2] = (u8)((Value>>16)&0x00FF); ++ pEEPROM->efuse_eeprom_data[Offset+3] = (u8)((Value>>24)&0xFF); ++ ++} // efuse_ShadowWrite1Byte ++ ++/*----------------------------------------------------------------------------- ++ * Function: EFUSE_ShadowMapUpdate ++ * ++ * Overview: Transfer current EFUSE content to shadow init and modify map. ++ * ++ * Input: NONE ++ * ++ * Output: NONE ++ * ++ * Return: NONE ++ * ++ * Revised History: ++ * When Who Remark ++ * 11/13/2008 MHC Create Version 0. ++ * ++ *---------------------------------------------------------------------------*/ ++void EFUSE_ShadowMapUpdate( ++ IN PADAPTER pAdapter, ++ IN u8 efuseType, ++ IN BOOLEAN bPseudoTest) ++{ ++ EEPROM_EFUSE_PRIV *pEEPROM = GET_EEPROM_EFUSE_PRIV(pAdapter); ++ u16 mapLen=0; ++ ++ EFUSE_GetEfuseDefinition(pAdapter, efuseType, TYPE_EFUSE_MAP_LEN, (PVOID)&mapLen, bPseudoTest); ++ ++ if (pEEPROM->bautoload_fail_flag == _TRUE) ++ { ++ _rtw_memset(pEEPROM->efuse_eeprom_data, 0xFF, mapLen); ++ } ++ else ++ { ++ #ifdef CONFIG_ADAPTOR_INFO_CACHING_FILE ++ if(_SUCCESS != retriveAdaptorInfoFile(pAdapter->registrypriv.adaptor_info_caching_file_path, pEEPROM)) { ++ #endif ++ ++ Efuse_ReadAllMap(pAdapter, efuseType, pEEPROM->efuse_eeprom_data, bPseudoTest); ++ ++ #ifdef CONFIG_ADAPTOR_INFO_CACHING_FILE ++ storeAdaptorInfoFile(pAdapter->registrypriv.adaptor_info_caching_file_path, pEEPROM); ++ } ++ #endif ++ } ++ ++ //PlatformMoveMemory((PVOID)&pHalData->EfuseMap[EFUSE_MODIFY_MAP][0], ++ //(PVOID)&pHalData->EfuseMap[EFUSE_INIT_MAP][0], mapLen); ++}// EFUSE_ShadowMapUpdate ++ ++ ++/*----------------------------------------------------------------------------- ++ * Function: EFUSE_ShadowRead ++ * ++ * Overview: Read from efuse init map !!!!! ++ * ++ * Input: NONE ++ * ++ * Output: NONE ++ * ++ * Return: NONE ++ * ++ * Revised History: ++ * When Who Remark ++ * 11/12/2008 MHC Create Version 0. ++ * ++ *---------------------------------------------------------------------------*/ ++void ++EFUSE_ShadowRead( ++ IN PADAPTER pAdapter, ++ IN u8 Type, ++ IN u16 Offset, ++ IN OUT u32 *Value ) ++{ ++ if (Type == 1) ++ efuse_ShadowRead1Byte(pAdapter, Offset, (u8 *)Value); ++ else if (Type == 2) ++ efuse_ShadowRead2Byte(pAdapter, Offset, (u16 *)Value); ++ else if (Type == 4) ++ efuse_ShadowRead4Byte(pAdapter, Offset, (u32 *)Value); ++ ++} // EFUSE_ShadowRead ++ ++/*----------------------------------------------------------------------------- ++ * Function: EFUSE_ShadowWrite ++ * ++ * Overview: Write efuse modify map for later update operation to use!!!!! ++ * ++ * Input: NONE ++ * ++ * Output: NONE ++ * ++ * Return: NONE ++ * ++ * Revised History: ++ * When Who Remark ++ * 11/12/2008 MHC Create Version 0. ++ * ++ *---------------------------------------------------------------------------*/ ++extern VOID ++EFUSE_ShadowWrite( ++ IN PADAPTER pAdapter, ++ IN u8 Type, ++ IN u16 Offset, ++ IN OUT u32 Value) ++{ ++#if (MP_DRIVER == 0) ++ return; ++#endif ++ ++ if (Type == 1) ++ efuse_ShadowWrite1Byte(pAdapter, Offset, (u8)Value); ++ else if (Type == 2) ++ efuse_ShadowWrite2Byte(pAdapter, Offset, (u16)Value); ++ else if (Type == 4) ++ efuse_ShadowWrite4Byte(pAdapter, Offset, (u32)Value); ++ ++} // EFUSE_ShadowWrite ++ ++VOID ++Efuse_InitSomeVar( ++ IN PADAPTER pAdapter ++ ) ++{ ++ u8 i; ++ ++ _rtw_memset((PVOID)&fakeEfuseContent[0], 0xff, EFUSE_MAX_HW_SIZE); ++ _rtw_memset((PVOID)&fakeEfuseInitMap[0], 0xff, EFUSE_MAX_MAP_LEN); ++ _rtw_memset((PVOID)&fakeEfuseModifiedMap[0], 0xff, EFUSE_MAX_MAP_LEN); ++ ++ for(i=0; i ++ ++ int isAdaptorInfoFileValid(void) ++{ ++ return _TRUE; ++} ++ ++int storeAdaptorInfoFile(char *path, struct eeprom_priv * eeprom_priv) ++{ ++ int ret =_SUCCESS; ++ ++ if(path && eeprom_priv) { ++ ret = rtw_store_to_file(path, eeprom_priv->efuse_eeprom_data, EEPROM_MAX_SIZE); ++ if(ret == EEPROM_MAX_SIZE) ++ ret = _SUCCESS; ++ else ++ ret = _FAIL; ++ } else { ++ DBG_8192C("%s NULL pointer\n",__FUNCTION__); ++ ret = _FAIL; ++ } ++ return ret; ++} ++ ++int retriveAdaptorInfoFile(char *path, struct eeprom_priv * eeprom_priv) ++{ ++ int ret = _SUCCESS; ++ mm_segment_t oldfs; ++ struct file *fp; ++ ++ if(path && eeprom_priv) { ++ ++ ret = rtw_retrive_from_file(path, eeprom_priv->efuse_eeprom_data, EEPROM_MAX_SIZE); ++ ++ if(ret == EEPROM_MAX_SIZE) ++ ret = _SUCCESS; ++ else ++ ret = _FAIL; ++ ++ #if 0 ++ if(isAdaptorInfoFileValid()) { ++ return 0; ++ } else { ++ return _FAIL; ++ } ++ #endif ++ ++ } else { ++ DBG_8192C("%s NULL pointer\n",__FUNCTION__); ++ ret = _FAIL; ++ } ++ return ret; ++} ++#endif //CONFIG_ADAPTOR_INFO_CACHING_FILE ++#endif //PLATFORM_LINUX ++ ++ +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/core/rtw_br_ext.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/core/rtw_br_ext.c 2013-07-26 19:36:04.000000000 +0000 +@@ -0,0 +1,1694 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#define _RTW_BR_EXT_C_ ++ ++#ifdef __KERNEL__ ++#include ++#include ++#include ++#include ++#include ++#include ++#endif ++ ++#if 1 // rtw_wifi_driver ++#include ++#include ++#include "rtw_br_ext.h" ++#else // rtw_wifi_driver ++#include "./8192cd_cfg.h" ++ ++#ifndef __KERNEL__ ++#include "./sys-support.h" ++#endif ++ ++#include "./8192cd.h" ++#include "./8192cd_headers.h" ++#include "./8192cd_br_ext.h" ++#include "./8192cd_debug.h" ++#endif // rtw_wifi_driver ++ ++#ifdef CL_IPV6_PASS ++#ifdef __KERNEL__ ++#include ++#include ++#include ++#include ++#endif ++#endif ++ ++#ifdef CONFIG_BR_EXT ++ ++//#define BR_EXT_DEBUG ++ ++#define NAT25_IPV4 01 ++#define NAT25_IPV6 02 ++#define NAT25_IPX 03 ++#define NAT25_APPLE 04 ++#define NAT25_PPPOE 05 ++ ++#define RTL_RELAY_TAG_LEN (ETH_ALEN) ++#define TAG_HDR_LEN 4 ++ ++#define MAGIC_CODE 0x8186 ++#define MAGIC_CODE_LEN 2 ++#define WAIT_TIME_PPPOE 5 // waiting time for pppoe server in sec ++ ++/*----------------------------------------------------------------- ++ How database records network address: ++ 0 1 2 3 4 5 6 7 8 9 10 ++ |----|----|----|----|----|----|----|----|----|----|----| ++ IPv4 |type| | IP addr | ++ IPX |type| Net addr | Node addr | ++ IPX |type| Net addr |Sckt addr| ++ Apple |type| Network |node| ++ PPPoE |type| SID | AC MAC | ++-----------------------------------------------------------------*/ ++ ++ ++//Find a tag in pppoe frame and return the pointer ++static __inline__ unsigned char *__nat25_find_pppoe_tag(struct pppoe_hdr *ph, unsigned short type) ++{ ++ unsigned char *cur_ptr, *start_ptr; ++ unsigned short tagLen, tagType; ++ ++ start_ptr = cur_ptr = (unsigned char *)ph->tag; ++ while((cur_ptr - start_ptr) < ntohs(ph->length)) { ++ // prevent un-alignment access ++ tagType = (unsigned short)((cur_ptr[0] << 8) + cur_ptr[1]); ++ tagLen = (unsigned short)((cur_ptr[2] << 8) + cur_ptr[3]); ++ if(tagType == type) ++ return cur_ptr; ++ cur_ptr = cur_ptr + TAG_HDR_LEN + tagLen; ++ } ++ return 0; ++} ++ ++ ++static __inline__ int __nat25_add_pppoe_tag(struct sk_buff *skb, struct pppoe_tag *tag) ++{ ++ struct pppoe_hdr *ph = (struct pppoe_hdr *)(skb->data + ETH_HLEN); ++ int data_len; ++ ++ data_len = tag->tag_len + TAG_HDR_LEN; ++ if (skb_tailroom(skb) < data_len) { ++ _DEBUG_ERR("skb_tailroom() failed in add SID tag!\n"); ++ return -1; ++ } ++ ++ skb_put(skb, data_len); ++ // have a room for new tag ++ memmove(((unsigned char *)ph->tag + data_len), (unsigned char *)ph->tag, ntohs(ph->length)); ++ ph->length = htons(ntohs(ph->length) + data_len); ++ memcpy((unsigned char *)ph->tag, tag, data_len); ++ return data_len; ++} ++ ++static int skb_pull_and_merge(struct sk_buff *skb, unsigned char *src, int len) ++{ ++ int tail_len; ++ unsigned long end, tail; ++ ++ if ((src+len) > skb->tail || skb->len < len) ++ return -1; ++ ++ tail = (unsigned long)skb->tail; ++ end = (unsigned long)src+len; ++ if (tail < end) ++ return -1; ++ ++ tail_len = (int)(tail-end); ++ if (tail_len > 0) ++ memmove(src, src+len, tail_len); ++ ++ skb_trim(skb, skb->len-len); ++ return 0; ++} ++ ++static __inline__ unsigned long __nat25_timeout(_adapter *priv) ++{ ++ unsigned long timeout; ++ ++ timeout = jiffies - NAT25_AGEING_TIME*HZ; ++ ++ return timeout; ++} ++ ++ ++static __inline__ int __nat25_has_expired(_adapter *priv, ++ struct nat25_network_db_entry *fdb) ++{ ++ if(time_before_eq(fdb->ageing_timer, __nat25_timeout(priv))) ++ return 1; ++ ++ return 0; ++} ++ ++ ++static __inline__ void __nat25_generate_ipv4_network_addr(unsigned char *networkAddr, ++ unsigned int *ipAddr) ++{ ++ memset(networkAddr, 0, MAX_NETWORK_ADDR_LEN); ++ ++ networkAddr[0] = NAT25_IPV4; ++ memcpy(networkAddr+7, (unsigned char *)ipAddr, 4); ++} ++ ++ ++static __inline__ void __nat25_generate_ipx_network_addr_with_node(unsigned char *networkAddr, ++ unsigned int *ipxNetAddr, unsigned char *ipxNodeAddr) ++{ ++ memset(networkAddr, 0, MAX_NETWORK_ADDR_LEN); ++ ++ networkAddr[0] = NAT25_IPX; ++ memcpy(networkAddr+1, (unsigned char *)ipxNetAddr, 4); ++ memcpy(networkAddr+5, ipxNodeAddr, 6); ++} ++ ++ ++static __inline__ void __nat25_generate_ipx_network_addr_with_socket(unsigned char *networkAddr, ++ unsigned int *ipxNetAddr, unsigned short *ipxSocketAddr) ++{ ++ memset(networkAddr, 0, MAX_NETWORK_ADDR_LEN); ++ ++ networkAddr[0] = NAT25_IPX; ++ memcpy(networkAddr+1, (unsigned char *)ipxNetAddr, 4); ++ memcpy(networkAddr+5, (unsigned char *)ipxSocketAddr, 2); ++} ++ ++ ++static __inline__ void __nat25_generate_apple_network_addr(unsigned char *networkAddr, ++ unsigned short *network, unsigned char *node) ++{ ++ memset(networkAddr, 0, MAX_NETWORK_ADDR_LEN); ++ ++ networkAddr[0] = NAT25_APPLE; ++ memcpy(networkAddr+1, (unsigned char *)network, 2); ++ networkAddr[3] = *node; ++} ++ ++ ++static __inline__ void __nat25_generate_pppoe_network_addr(unsigned char *networkAddr, ++ unsigned char *ac_mac, unsigned short *sid) ++{ ++ memset(networkAddr, 0, MAX_NETWORK_ADDR_LEN); ++ ++ networkAddr[0] = NAT25_PPPOE; ++ memcpy(networkAddr+1, (unsigned char *)sid, 2); ++ memcpy(networkAddr+3, (unsigned char *)ac_mac, 6); ++} ++ ++ ++#ifdef CL_IPV6_PASS ++static void __nat25_generate_ipv6_network_addr(unsigned char *networkAddr, ++ unsigned int *ipAddr) ++{ ++ memset(networkAddr, 0, MAX_NETWORK_ADDR_LEN); ++ ++ networkAddr[0] = NAT25_IPV6; ++ memcpy(networkAddr+1, (unsigned char *)ipAddr, 16); ++} ++ ++ ++static unsigned char *scan_tlv(unsigned char *data, int len, unsigned char tag, unsigned char len8b) ++{ ++ while (len > 0) { ++ if (*data == tag && *(data+1) == len8b && len >= len8b*8) ++ return data+2; ++ ++ len -= (*(data+1))*8; ++ data += (*(data+1))*8; ++ } ++ return NULL; ++} ++ ++ ++static int update_nd_link_layer_addr(unsigned char *data, int len, unsigned char *replace_mac) ++{ ++ struct icmp6hdr *icmphdr = (struct icmp6hdr *)data; ++ unsigned char *mac; ++ ++ if (icmphdr->icmp6_type == NDISC_ROUTER_SOLICITATION) { ++ if (len >= 8) { ++ mac = scan_tlv(&data[8], len-8, 1, 1); ++ if (mac) { ++ _DEBUG_INFO("Router Solicitation, replace MAC From: %02x:%02x:%02x:%02x:%02x:%02x, To: %02x:%02x:%02x:%02x:%02x:%02x\n", ++ mac[0],mac[1],mac[2],mac[3],mac[4],mac[5], ++ replace_mac[0],replace_mac[1],replace_mac[2],replace_mac[3],replace_mac[4],replace_mac[5]); ++ memcpy(mac, replace_mac, 6); ++ return 1; ++ } ++ } ++ } ++ else if (icmphdr->icmp6_type == NDISC_ROUTER_ADVERTISEMENT) { ++ if (len >= 16) { ++ mac = scan_tlv(&data[16], len-16, 1, 1); ++ if (mac) { ++ _DEBUG_INFO("Router Advertisement, replace MAC From: %02x:%02x:%02x:%02x:%02x:%02x, To: %02x:%02x:%02x:%02x:%02x:%02x\n", ++ mac[0],mac[1],mac[2],mac[3],mac[4],mac[5], ++ replace_mac[0],replace_mac[1],replace_mac[2],replace_mac[3],replace_mac[4],replace_mac[5]); ++ memcpy(mac, replace_mac, 6); ++ return 1; ++ } ++ } ++ } ++ else if (icmphdr->icmp6_type == NDISC_NEIGHBOUR_SOLICITATION) { ++ if (len >= 24) { ++ mac = scan_tlv(&data[24], len-24, 1, 1); ++ if (mac) { ++ _DEBUG_INFO("Neighbor Solicitation, replace MAC From: %02x:%02x:%02x:%02x:%02x:%02x, To: %02x:%02x:%02x:%02x:%02x:%02x\n", ++ mac[0],mac[1],mac[2],mac[3],mac[4],mac[5], ++ replace_mac[0],replace_mac[1],replace_mac[2],replace_mac[3],replace_mac[4],replace_mac[5]); ++ memcpy(mac, replace_mac, 6); ++ return 1; ++ } ++ } ++ } ++ else if (icmphdr->icmp6_type == NDISC_NEIGHBOUR_ADVERTISEMENT) { ++ if (len >= 24) { ++ mac = scan_tlv(&data[24], len-24, 2, 1); ++ if (mac) { ++ _DEBUG_INFO("Neighbor Advertisement, replace MAC From: %02x:%02x:%02x:%02x:%02x:%02x, To: %02x:%02x:%02x:%02x:%02x:%02x\n", ++ mac[0],mac[1],mac[2],mac[3],mac[4],mac[5], ++ replace_mac[0],replace_mac[1],replace_mac[2],replace_mac[3],replace_mac[4],replace_mac[5]); ++ memcpy(mac, replace_mac, 6); ++ return 1; ++ } ++ } ++ } ++ else if (icmphdr->icmp6_type == NDISC_REDIRECT) { ++ if (len >= 40) { ++ mac = scan_tlv(&data[40], len-40, 2, 1); ++ if (mac) { ++ _DEBUG_INFO("Redirect, replace MAC From: %02x:%02x:%02x:%02x:%02x:%02x, To: %02x:%02x:%02x:%02x:%02x:%02x\n", ++ mac[0],mac[1],mac[2],mac[3],mac[4],mac[5], ++ replace_mac[0],replace_mac[1],replace_mac[2],replace_mac[3],replace_mac[4],replace_mac[5]); ++ memcpy(mac, replace_mac, 6); ++ return 1; ++ } ++ } ++ } ++ return 0; ++} ++ ++ ++static void convert_ipv6_mac_to_mc(struct sk_buff *skb) ++{ ++ struct ipv6hdr *iph = (struct ipv6hdr *)(skb->data + ETH_HLEN); ++ unsigned char *dst_mac = skb->data; ++ ++ //dst_mac[0] = 0xff; ++ //dst_mac[1] = 0xff; ++ /*modified by qinjunjie,ipv6 multicast address ix 0x33-33-xx-xx-xx-xx*/ ++ dst_mac[0] = 0x33; ++ dst_mac[1] = 0x33; ++ memcpy(&dst_mac[2], &iph->daddr.s6_addr32[3], 4); ++ #if defined(__LINUX_2_6__) ++ /*modified by qinjunjie,warning:should not remove next line*/ ++ skb->pkt_type = PACKET_MULTICAST; ++ #endif ++} ++#endif /* CL_IPV6_PASS */ ++ ++ ++static __inline__ int __nat25_network_hash(unsigned char *networkAddr) ++{ ++ if(networkAddr[0] == NAT25_IPV4) ++ { ++ unsigned long x; ++ ++ x = networkAddr[7] ^ networkAddr[8] ^ networkAddr[9] ^ networkAddr[10]; ++ ++ return x & (NAT25_HASH_SIZE - 1); ++ } ++ else if(networkAddr[0] == NAT25_IPX) ++ { ++ unsigned long x; ++ ++ x = networkAddr[1] ^ networkAddr[2] ^ networkAddr[3] ^ networkAddr[4] ^ networkAddr[5] ^ ++ networkAddr[6] ^ networkAddr[7] ^ networkAddr[8] ^ networkAddr[9] ^ networkAddr[10]; ++ ++ return x & (NAT25_HASH_SIZE - 1); ++ } ++ else if(networkAddr[0] == NAT25_APPLE) ++ { ++ unsigned long x; ++ ++ x = networkAddr[1] ^ networkAddr[2] ^ networkAddr[3]; ++ ++ return x & (NAT25_HASH_SIZE - 1); ++ } ++ else if(networkAddr[0] == NAT25_PPPOE) ++ { ++ unsigned long x; ++ ++ x = networkAddr[0] ^ networkAddr[1] ^ networkAddr[2] ^ networkAddr[3] ^ networkAddr[4] ^ networkAddr[5] ^ networkAddr[6] ^ networkAddr[7] ^ networkAddr[8]; ++ ++ return x & (NAT25_HASH_SIZE - 1); ++ } ++#ifdef CL_IPV6_PASS ++ else if(networkAddr[0] == NAT25_IPV6) ++ { ++ unsigned long x; ++ ++ x = networkAddr[1] ^ networkAddr[2] ^ networkAddr[3] ^ networkAddr[4] ^ networkAddr[5] ^ ++ networkAddr[6] ^ networkAddr[7] ^ networkAddr[8] ^ networkAddr[9] ^ networkAddr[10] ^ ++ networkAddr[11] ^ networkAddr[12] ^ networkAddr[13] ^ networkAddr[14] ^ networkAddr[15] ^ ++ networkAddr[16]; ++ ++ return x & (NAT25_HASH_SIZE - 1); ++ } ++#endif ++ else ++ { ++ unsigned long x = 0; ++ int i; ++ ++ for (i=0; ibr_ext_lock, &irqL); ++ ++ ent->next_hash = priv->nethash[hash]; ++ if(ent->next_hash != NULL) ++ ent->next_hash->pprev_hash = &ent->next_hash; ++ priv->nethash[hash] = ent; ++ ent->pprev_hash = &priv->nethash[hash]; ++ ++ //_exit_critical_bh(&priv->br_ext_lock, &irqL); ++} ++ ++ ++static __inline__ void __network_hash_unlink(struct nat25_network_db_entry *ent) ++{ ++ // Caller must _enter_critical_bh already! ++ //_irqL irqL; ++ //_enter_critical_bh(&priv->br_ext_lock, &irqL); ++ ++ *(ent->pprev_hash) = ent->next_hash; ++ if(ent->next_hash != NULL) ++ ent->next_hash->pprev_hash = ent->pprev_hash; ++ ent->next_hash = NULL; ++ ent->pprev_hash = NULL; ++ ++ //_exit_critical_bh(&priv->br_ext_lock, &irqL); ++} ++ ++ ++static int __nat25_db_network_lookup_and_replace(_adapter *priv, ++ struct sk_buff *skb, unsigned char *networkAddr) ++{ ++ struct nat25_network_db_entry *db; ++ _irqL irqL; ++ _enter_critical_bh(&priv->br_ext_lock, &irqL); ++ ++ db = priv->nethash[__nat25_network_hash(networkAddr)]; ++ while (db != NULL) ++ { ++ if(!memcmp(db->networkAddr, networkAddr, MAX_NETWORK_ADDR_LEN)) ++ { ++ if(!__nat25_has_expired(priv, db)) ++ { ++ // replace the destination mac address ++ memcpy(skb->data, db->macAddr, ETH_ALEN); ++ atomic_inc(&db->use_count); ++ ++#ifdef CL_IPV6_PASS ++ DEBUG_INFO("NAT25: Lookup M:%02x%02x%02x%02x%02x%02x N:%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x" ++ "%02x%02x%02x%02x%02x%02x\n", ++ db->macAddr[0], ++ db->macAddr[1], ++ db->macAddr[2], ++ db->macAddr[3], ++ db->macAddr[4], ++ db->macAddr[5], ++ db->networkAddr[0], ++ db->networkAddr[1], ++ db->networkAddr[2], ++ db->networkAddr[3], ++ db->networkAddr[4], ++ db->networkAddr[5], ++ db->networkAddr[6], ++ db->networkAddr[7], ++ db->networkAddr[8], ++ db->networkAddr[9], ++ db->networkAddr[10], ++ db->networkAddr[11], ++ db->networkAddr[12], ++ db->networkAddr[13], ++ db->networkAddr[14], ++ db->networkAddr[15], ++ db->networkAddr[16]); ++#else ++ DEBUG_INFO("NAT25: Lookup M:%02x%02x%02x%02x%02x%02x N:%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x\n", ++ db->macAddr[0], ++ db->macAddr[1], ++ db->macAddr[2], ++ db->macAddr[3], ++ db->macAddr[4], ++ db->macAddr[5], ++ db->networkAddr[0], ++ db->networkAddr[1], ++ db->networkAddr[2], ++ db->networkAddr[3], ++ db->networkAddr[4], ++ db->networkAddr[5], ++ db->networkAddr[6], ++ db->networkAddr[7], ++ db->networkAddr[8], ++ db->networkAddr[9], ++ db->networkAddr[10]); ++#endif ++ } ++ _exit_critical_bh(&priv->br_ext_lock, &irqL); ++ return 1; ++ } ++ ++ db = db->next_hash; ++ } ++ ++ _exit_critical_bh(&priv->br_ext_lock, &irqL); ++ return 0; ++} ++ ++ ++static void __nat25_db_network_insert(_adapter *priv, ++ unsigned char *macAddr, unsigned char *networkAddr) ++{ ++ struct nat25_network_db_entry *db; ++ int hash; ++ _irqL irqL; ++ _enter_critical_bh(&priv->br_ext_lock, &irqL); ++ ++ hash = __nat25_network_hash(networkAddr); ++ db = priv->nethash[hash]; ++ while (db != NULL) ++ { ++ if(!memcmp(db->networkAddr, networkAddr, MAX_NETWORK_ADDR_LEN)) ++ { ++ memcpy(db->macAddr, macAddr, ETH_ALEN); ++ db->ageing_timer = jiffies; ++ _exit_critical_bh(&priv->br_ext_lock, &irqL); ++ return; ++ } ++ ++ db = db->next_hash; ++ } ++ ++ db = (struct nat25_network_db_entry *) _rtw_malloc(sizeof(*db)); ++ if(db == NULL) { ++ _exit_critical_bh(&priv->br_ext_lock, &irqL); ++ return; ++ } ++ ++ memcpy(db->networkAddr, networkAddr, MAX_NETWORK_ADDR_LEN); ++ memcpy(db->macAddr, macAddr, ETH_ALEN); ++ atomic_set(&db->use_count, 1); ++ db->ageing_timer = jiffies; ++ ++ __network_hash_link(priv, db, hash); ++ ++ _exit_critical_bh(&priv->br_ext_lock, &irqL); ++} ++ ++ ++static void __nat25_db_print(_adapter *priv) ++{ ++ _irqL irqL; ++ _enter_critical_bh(&priv->br_ext_lock, &irqL); ++ ++#ifdef BR_EXT_DEBUG ++ static int counter = 0; ++ int i, j; ++ struct nat25_network_db_entry *db; ++ ++ counter++; ++ if((counter % 16) != 0) ++ return; ++ ++ for(i=0, j=0; inethash[i]; ++ ++ while (db != NULL) ++ { ++#ifdef CL_IPV6_PASS ++ panic_printk("NAT25: DB(%d) H(%02d) C(%d) M:%02x%02x%02x%02x%02x%02x N:%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x" ++ "%02x%02x%02x%02x%02x%02x\n", ++ j, ++ i, ++ atomic_read(&db->use_count), ++ db->macAddr[0], ++ db->macAddr[1], ++ db->macAddr[2], ++ db->macAddr[3], ++ db->macAddr[4], ++ db->macAddr[5], ++ db->networkAddr[0], ++ db->networkAddr[1], ++ db->networkAddr[2], ++ db->networkAddr[3], ++ db->networkAddr[4], ++ db->networkAddr[5], ++ db->networkAddr[6], ++ db->networkAddr[7], ++ db->networkAddr[8], ++ db->networkAddr[9], ++ db->networkAddr[10], ++ db->networkAddr[11], ++ db->networkAddr[12], ++ db->networkAddr[13], ++ db->networkAddr[14], ++ db->networkAddr[15], ++ db->networkAddr[16]); ++#else ++ panic_printk("NAT25: DB(%d) H(%02d) C(%d) M:%02x%02x%02x%02x%02x%02x N:%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x\n", ++ j, ++ i, ++ atomic_read(&db->use_count), ++ db->macAddr[0], ++ db->macAddr[1], ++ db->macAddr[2], ++ db->macAddr[3], ++ db->macAddr[4], ++ db->macAddr[5], ++ db->networkAddr[0], ++ db->networkAddr[1], ++ db->networkAddr[2], ++ db->networkAddr[3], ++ db->networkAddr[4], ++ db->networkAddr[5], ++ db->networkAddr[6], ++ db->networkAddr[7], ++ db->networkAddr[8], ++ db->networkAddr[9], ++ db->networkAddr[10]); ++#endif ++ j++; ++ ++ db = db->next_hash; ++ } ++ } ++#endif ++ ++ _exit_critical_bh(&priv->br_ext_lock, &irqL); ++} ++ ++ ++ ++ ++/* ++ * NAT2.5 interface ++ */ ++ ++void nat25_db_cleanup(_adapter *priv) ++{ ++ int i; ++ _irqL irqL; ++ _enter_critical_bh(&priv->br_ext_lock, &irqL); ++ ++ for(i=0; inethash[i]; ++ while (f != NULL) { ++ struct nat25_network_db_entry *g; ++ ++ g = f->next_hash; ++ if(priv->scdb_entry == f) ++ { ++ memset(priv->scdb_mac, 0, ETH_ALEN); ++ memset(priv->scdb_ip, 0, 4); ++ priv->scdb_entry = NULL; ++ } ++ __network_hash_unlink(f); ++ _rtw_mfree((u8 *) f, sizeof(struct nat25_network_db_entry)); ++ ++ f = g; ++ } ++ } ++ ++ _exit_critical_bh(&priv->br_ext_lock, &irqL); ++} ++ ++ ++void nat25_db_expire(_adapter *priv) ++{ ++ int i; ++ _irqL irqL; ++ _enter_critical_bh(&priv->br_ext_lock, &irqL); ++ ++ //if(!priv->ethBrExtInfo.nat25_disable) ++ { ++ for (i=0; inethash[i]; ++ ++ while (f != NULL) ++ { ++ struct nat25_network_db_entry *g; ++ g = f->next_hash; ++ ++ if(__nat25_has_expired(priv, f)) ++ { ++ if(atomic_dec_and_test(&f->use_count)) ++ { ++#ifdef BR_EXT_DEBUG ++#ifdef CL_IPV6_PASS ++ panic_printk("NAT25 Expire H(%02d) M:%02x%02x%02x%02x%02x%02x N:%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x" ++ "%02x%02x%02x%02x%02x%02x\n", ++ i, ++ f->macAddr[0], ++ f->macAddr[1], ++ f->macAddr[2], ++ f->macAddr[3], ++ f->macAddr[4], ++ f->macAddr[5], ++ f->networkAddr[0], ++ f->networkAddr[1], ++ f->networkAddr[2], ++ f->networkAddr[3], ++ f->networkAddr[4], ++ f->networkAddr[5], ++ f->networkAddr[6], ++ f->networkAddr[7], ++ f->networkAddr[8], ++ f->networkAddr[9], ++ f->networkAddr[10], ++ f->networkAddr[11], ++ f->networkAddr[12], ++ f->networkAddr[13], ++ f->networkAddr[14], ++ f->networkAddr[15], ++ f->networkAddr[16]); ++#else ++ ++ panic_printk("NAT25 Expire H(%02d) M:%02x%02x%02x%02x%02x%02x N:%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x\n", ++ i, ++ f->macAddr[0], ++ f->macAddr[1], ++ f->macAddr[2], ++ f->macAddr[3], ++ f->macAddr[4], ++ f->macAddr[5], ++ f->networkAddr[0], ++ f->networkAddr[1], ++ f->networkAddr[2], ++ f->networkAddr[3], ++ f->networkAddr[4], ++ f->networkAddr[5], ++ f->networkAddr[6], ++ f->networkAddr[7], ++ f->networkAddr[8], ++ f->networkAddr[9], ++ f->networkAddr[10]); ++#endif ++#endif ++ if(priv->scdb_entry == f) ++ { ++ memset(priv->scdb_mac, 0, ETH_ALEN); ++ memset(priv->scdb_ip, 0, 4); ++ priv->scdb_entry = NULL; ++ } ++ __network_hash_unlink(f); ++ _rtw_mfree((u8 *) f, sizeof(struct nat25_network_db_entry)); ++ } ++ } ++ ++ f = g; ++ } ++ } ++ } ++ ++ _exit_critical_bh(&priv->br_ext_lock, &irqL); ++} ++ ++ ++#ifdef SUPPORT_TX_MCAST2UNI ++static int checkIPMcAndReplace(_adapter *priv, struct sk_buff *skb, unsigned int *dst_ip) ++{ ++ struct stat_info *pstat; ++ struct list_head *phead, *plist; ++ int i; ++ ++ phead = &priv->asoc_list; ++ plist = phead->next; ++ ++ while (plist != phead) { ++ pstat = list_entry(plist, struct stat_info, asoc_list); ++ plist = plist->next; ++ ++ if (pstat->ipmc_num == 0) ++ continue; ++ ++ for (i=0; iipmc[i].used && !memcmp(&pstat->ipmc[i].mcmac[3], ((unsigned char *)dst_ip)+1, 3)) { ++ memcpy(skb->data, pstat->ipmc[i].mcmac, ETH_ALEN); ++ return 1; ++ } ++ } ++ } ++ return 0; ++} ++#endif ++ ++int nat25_db_handle(_adapter *priv, struct sk_buff *skb, int method) ++{ ++ unsigned short protocol; ++ unsigned char networkAddr[MAX_NETWORK_ADDR_LEN]; ++ ++ if(skb == NULL) ++ return -1; ++ ++ if((method <= NAT25_MIN) || (method >= NAT25_MAX)) ++ return -1; ++ ++ protocol = *((unsigned short *)(skb->data + 2 * ETH_ALEN)); ++ ++ /*---------------------------------------------------*/ ++ /* Handle IP frame */ ++ /*---------------------------------------------------*/ ++ if(protocol == __constant_htons(ETH_P_IP)) ++ { ++ struct iphdr* iph = (struct iphdr *)(skb->data + ETH_HLEN); ++ ++ if(((unsigned char*)(iph) + (iph->ihl<<2)) >= (skb->data + ETH_HLEN + skb->len)) ++ { ++ DEBUG_WARN("NAT25: malformed IP packet !\n"); ++ return -1; ++ } ++ ++ switch(method) ++ { ++ case NAT25_CHECK: ++ return -1; ++ ++ case NAT25_INSERT: ++ { ++ //some muticast with source IP is all zero, maybe other case is illegal ++ //in class A, B, C, host address is all zero or all one is illegal ++ if (iph->saddr == 0) ++ return 0; ++ DEBUG_INFO("NAT25: Insert IP, SA=%08x, DA=%08x\n", iph->saddr, iph->daddr); ++ __nat25_generate_ipv4_network_addr(networkAddr, &iph->saddr); ++ //record source IP address and , source mac address into db ++ __nat25_db_network_insert(priv, skb->data+ETH_ALEN, networkAddr); ++ ++ __nat25_db_print(priv); ++ } ++ return 0; ++ ++ case NAT25_LOOKUP: ++ { ++ DEBUG_INFO("NAT25: Lookup IP, SA=%08x, DA=%08x\n", iph->saddr, iph->daddr); ++#ifdef SUPPORT_TX_MCAST2UNI ++ if (priv->pshare->rf_ft_var.mc2u_disable || ++ ((((OPMODE & (WIFI_STATION_STATE|WIFI_ASOC_STATE)) ++ == (WIFI_STATION_STATE|WIFI_ASOC_STATE)) && ++ !checkIPMcAndReplace(priv, skb, &iph->daddr)) || ++ (OPMODE & WIFI_ADHOC_STATE))) ++#endif ++ { ++ __nat25_generate_ipv4_network_addr(networkAddr, &iph->daddr); ++ ++ if (!__nat25_db_network_lookup_and_replace(priv, skb, networkAddr)) { ++ if (*((unsigned char *)&iph->daddr + 3) == 0xff) { ++ // L2 is unicast but L3 is broadcast, make L2 bacome broadcast ++ DEBUG_INFO("NAT25: Set DA as boardcast\n"); ++ memset(skb->data, 0xff, ETH_ALEN); ++ } ++ else { ++ // forward unknow IP packet to upper TCP/IP ++ DEBUG_INFO("NAT25: Replace DA with BR's MAC\n"); ++ memcpy(skb->data, priv->br_mac, ETH_ALEN); ++ } ++ } ++ } ++ } ++ return 0; ++ ++ default: ++ return -1; ++ } ++ } ++ ++ /*---------------------------------------------------*/ ++ /* Handle ARP frame */ ++ /*---------------------------------------------------*/ ++ else if(protocol == __constant_htons(ETH_P_ARP)) ++ { ++ struct arphdr *arp = (struct arphdr *)(skb->data + ETH_HLEN); ++ unsigned char *arp_ptr = (unsigned char *)(arp + 1); ++ unsigned int *sender, *target; ++ ++ if(arp->ar_pro != __constant_htons(ETH_P_IP)) ++ { ++ DEBUG_WARN("NAT25: arp protocol unknown (%4x)!\n", htons(arp->ar_pro)); ++ return -1; ++ } ++ ++ switch(method) ++ { ++ case NAT25_CHECK: ++ return 0; // skb_copy for all ARP frame ++ ++ case NAT25_INSERT: ++ { ++ DEBUG_INFO("NAT25: Insert ARP, MAC=%02x%02x%02x%02x%02x%02x\n", arp_ptr[0], ++ arp_ptr[1], arp_ptr[2], arp_ptr[3], arp_ptr[4], arp_ptr[5]); ++ ++ // change to ARP sender mac address to wlan STA address ++ memcpy(arp_ptr, GET_MY_HWADDR(priv), ETH_ALEN); ++ ++ arp_ptr += arp->ar_hln; ++ sender = (unsigned int *)arp_ptr; ++ ++ __nat25_generate_ipv4_network_addr(networkAddr, sender); ++ ++ __nat25_db_network_insert(priv, skb->data+ETH_ALEN, networkAddr); ++ ++ __nat25_db_print(priv); ++ } ++ return 0; ++ ++ case NAT25_LOOKUP: ++ { ++ DEBUG_INFO("NAT25: Lookup ARP\n"); ++ ++ arp_ptr += arp->ar_hln; ++ sender = (unsigned int *)arp_ptr; ++ arp_ptr += (arp->ar_hln + arp->ar_pln); ++ target = (unsigned int *)arp_ptr; ++ ++ __nat25_generate_ipv4_network_addr(networkAddr, target); ++ ++ __nat25_db_network_lookup_and_replace(priv, skb, networkAddr); ++ ++ // change to ARP target mac address to Lookup result ++ arp_ptr = (unsigned char *)(arp + 1); ++ arp_ptr += (arp->ar_hln + arp->ar_pln); ++ memcpy(arp_ptr, skb->data, ETH_ALEN); ++ } ++ return 0; ++ ++ default: ++ return -1; ++ } ++ } ++ ++ /*---------------------------------------------------*/ ++ /* Handle IPX and Apple Talk frame */ ++ /*---------------------------------------------------*/ ++ else if((protocol == __constant_htons(ETH_P_IPX)) || ++ (protocol <= __constant_htons(ETH_FRAME_LEN))) ++ { ++ unsigned char ipx_header[2] = {0xFF, 0xFF}; ++ struct ipxhdr *ipx = NULL; ++ struct elapaarp *ea = NULL; ++ struct ddpehdr *ddp = NULL; ++ unsigned char *framePtr = skb->data + ETH_HLEN; ++ ++ if(protocol == __constant_htons(ETH_P_IPX)) ++ { ++ DEBUG_INFO("NAT25: Protocol=IPX (Ethernet II)\n"); ++ ipx = (struct ipxhdr *)framePtr; ++ } ++ else if(protocol <= __constant_htons(ETH_FRAME_LEN)) ++ { ++ if(!memcmp(ipx_header, framePtr, 2)) ++ { ++ DEBUG_INFO("NAT25: Protocol=IPX (Ethernet 802.3)\n"); ++ ipx = (struct ipxhdr *)framePtr; ++ } ++ else ++ { ++ unsigned char ipx_8022_type = 0xE0; ++ unsigned char snap_8022_type = 0xAA; ++ ++ if(*framePtr == snap_8022_type) ++ { ++ unsigned char ipx_snap_id[5] = {0x0, 0x0, 0x0, 0x81, 0x37}; // IPX SNAP ID ++ unsigned char aarp_snap_id[5] = {0x00, 0x00, 0x00, 0x80, 0xF3}; // Apple Talk AARP SNAP ID ++ unsigned char ddp_snap_id[5] = {0x08, 0x00, 0x07, 0x80, 0x9B}; // Apple Talk DDP SNAP ID ++ ++ framePtr += 3; // eliminate the 802.2 header ++ ++ if(!memcmp(ipx_snap_id, framePtr, 5)) ++ { ++ framePtr += 5; // eliminate the SNAP header ++ ++ DEBUG_INFO("NAT25: Protocol=IPX (Ethernet SNAP)\n"); ++ ipx = (struct ipxhdr *)framePtr; ++ } ++ else if(!memcmp(aarp_snap_id, framePtr, 5)) ++ { ++ framePtr += 5; // eliminate the SNAP header ++ ++ ea = (struct elapaarp *)framePtr; ++ } ++ else if(!memcmp(ddp_snap_id, framePtr, 5)) ++ { ++ framePtr += 5; // eliminate the SNAP header ++ ++ ddp = (struct ddpehdr *)framePtr; ++ } ++ else ++ { ++ DEBUG_WARN("NAT25: Protocol=Ethernet SNAP %02x%02x%02x%02x%02x\n", framePtr[0], ++ framePtr[1], framePtr[2], framePtr[3], framePtr[4]); ++ return -1; ++ } ++ } ++ else if(*framePtr == ipx_8022_type) ++ { ++ framePtr += 3; // eliminate the 802.2 header ++ ++ if(!memcmp(ipx_header, framePtr, 2)) ++ { ++ DEBUG_INFO("NAT25: Protocol=IPX (Ethernet 802.2)\n"); ++ ipx = (struct ipxhdr *)framePtr; ++ } ++ else ++ return -1; ++ } ++ else ++ return -1; ++ } ++ } ++ else ++ return -1; ++ ++ /* IPX */ ++ if(ipx != NULL) ++ { ++ switch(method) ++ { ++ case NAT25_CHECK: ++ if(!memcmp(skb->data+ETH_ALEN, ipx->ipx_source.node, ETH_ALEN)) ++ { ++ DEBUG_INFO("NAT25: Check IPX skb_copy\n"); ++ return 0; ++ } ++ return -1; ++ ++ case NAT25_INSERT: ++ { ++ DEBUG_INFO("NAT25: Insert IPX, Dest=%08x,%02x%02x%02x%02x%02x%02x,%04x Source=%08x,%02x%02x%02x%02x%02x%02x,%04x\n", ++ ipx->ipx_dest.net, ++ ipx->ipx_dest.node[0], ++ ipx->ipx_dest.node[1], ++ ipx->ipx_dest.node[2], ++ ipx->ipx_dest.node[3], ++ ipx->ipx_dest.node[4], ++ ipx->ipx_dest.node[5], ++ ipx->ipx_dest.sock, ++ ipx->ipx_source.net, ++ ipx->ipx_source.node[0], ++ ipx->ipx_source.node[1], ++ ipx->ipx_source.node[2], ++ ipx->ipx_source.node[3], ++ ipx->ipx_source.node[4], ++ ipx->ipx_source.node[5], ++ ipx->ipx_source.sock); ++ ++ if(!memcmp(skb->data+ETH_ALEN, ipx->ipx_source.node, ETH_ALEN)) ++ { ++ DEBUG_INFO("NAT25: Use IPX Net, and Socket as network addr\n"); ++ ++ __nat25_generate_ipx_network_addr_with_socket(networkAddr, &ipx->ipx_source.net, &ipx->ipx_source.sock); ++ ++ // change IPX source node addr to wlan STA address ++ memcpy(ipx->ipx_source.node, GET_MY_HWADDR(priv), ETH_ALEN); ++ } ++ else ++ { ++ __nat25_generate_ipx_network_addr_with_node(networkAddr, &ipx->ipx_source.net, ipx->ipx_source.node); ++ } ++ ++ __nat25_db_network_insert(priv, skb->data+ETH_ALEN, networkAddr); ++ ++ __nat25_db_print(priv); ++ } ++ return 0; ++ ++ case NAT25_LOOKUP: ++ { ++ if(!memcmp(GET_MY_HWADDR(priv), ipx->ipx_dest.node, ETH_ALEN)) ++ { ++ DEBUG_INFO("NAT25: Lookup IPX, Modify Destination IPX Node addr\n"); ++ ++ __nat25_generate_ipx_network_addr_with_socket(networkAddr, &ipx->ipx_dest.net, &ipx->ipx_dest.sock); ++ ++ __nat25_db_network_lookup_and_replace(priv, skb, networkAddr); ++ ++ // replace IPX destination node addr with Lookup destination MAC addr ++ memcpy(ipx->ipx_dest.node, skb->data, ETH_ALEN); ++ } ++ else ++ { ++ __nat25_generate_ipx_network_addr_with_node(networkAddr, &ipx->ipx_dest.net, ipx->ipx_dest.node); ++ ++ __nat25_db_network_lookup_and_replace(priv, skb, networkAddr); ++ } ++ } ++ return 0; ++ ++ default: ++ return -1; ++ } ++ } ++ ++ /* AARP */ ++ else if(ea != NULL) ++ { ++ /* Sanity check fields. */ ++ if(ea->hw_len != ETH_ALEN || ea->pa_len != AARP_PA_ALEN) ++ { ++ DEBUG_WARN("NAT25: Appletalk AARP Sanity check fail!\n"); ++ return -1; ++ } ++ ++ switch(method) ++ { ++ case NAT25_CHECK: ++ return 0; ++ ++ case NAT25_INSERT: ++ { ++ // change to AARP source mac address to wlan STA address ++ memcpy(ea->hw_src, GET_MY_HWADDR(priv), ETH_ALEN); ++ ++ DEBUG_INFO("NAT25: Insert AARP, Source=%d,%d Destination=%d,%d\n", ++ ea->pa_src_net, ++ ea->pa_src_node, ++ ea->pa_dst_net, ++ ea->pa_dst_node); ++ ++ __nat25_generate_apple_network_addr(networkAddr, &ea->pa_src_net, &ea->pa_src_node); ++ ++ __nat25_db_network_insert(priv, skb->data+ETH_ALEN, networkAddr); ++ ++ __nat25_db_print(priv); ++ } ++ return 0; ++ ++ case NAT25_LOOKUP: ++ { ++ DEBUG_INFO("NAT25: Lookup AARP, Source=%d,%d Destination=%d,%d\n", ++ ea->pa_src_net, ++ ea->pa_src_node, ++ ea->pa_dst_net, ++ ea->pa_dst_node); ++ ++ __nat25_generate_apple_network_addr(networkAddr, &ea->pa_dst_net, &ea->pa_dst_node); ++ ++ __nat25_db_network_lookup_and_replace(priv, skb, networkAddr); ++ ++ // change to AARP destination mac address to Lookup result ++ memcpy(ea->hw_dst, skb->data, ETH_ALEN); ++ } ++ return 0; ++ ++ default: ++ return -1; ++ } ++ } ++ ++ /* DDP */ ++ else if(ddp != NULL) ++ { ++ switch(method) ++ { ++ case NAT25_CHECK: ++ return -1; ++ ++ case NAT25_INSERT: ++ { ++ DEBUG_INFO("NAT25: Insert DDP, Source=%d,%d Destination=%d,%d\n", ++ ddp->deh_snet, ++ ddp->deh_snode, ++ ddp->deh_dnet, ++ ddp->deh_dnode); ++ ++ __nat25_generate_apple_network_addr(networkAddr, &ddp->deh_snet, &ddp->deh_snode); ++ ++ __nat25_db_network_insert(priv, skb->data+ETH_ALEN, networkAddr); ++ ++ __nat25_db_print(priv); ++ } ++ return 0; ++ ++ case NAT25_LOOKUP: ++ { ++ DEBUG_INFO("NAT25: Lookup DDP, Source=%d,%d Destination=%d,%d\n", ++ ddp->deh_snet, ++ ddp->deh_snode, ++ ddp->deh_dnet, ++ ddp->deh_dnode); ++ ++ __nat25_generate_apple_network_addr(networkAddr, &ddp->deh_dnet, &ddp->deh_dnode); ++ ++ __nat25_db_network_lookup_and_replace(priv, skb, networkAddr); ++ } ++ return 0; ++ ++ default: ++ return -1; ++ } ++ } ++ ++ return -1; ++ } ++ ++ /*---------------------------------------------------*/ ++ /* Handle PPPoE frame */ ++ /*---------------------------------------------------*/ ++ else if((protocol == __constant_htons(ETH_P_PPP_DISC)) || ++ (protocol == __constant_htons(ETH_P_PPP_SES))) ++ { ++ struct pppoe_hdr *ph = (struct pppoe_hdr *)(skb->data + ETH_HLEN); ++ unsigned short *pMagic; ++ ++ switch(method) ++ { ++ case NAT25_CHECK: ++ if (ph->sid == 0) ++ return 0; ++ return 1; ++ ++ case NAT25_INSERT: ++ if(ph->sid == 0) // Discovery phase according to tag ++ { ++ if(ph->code == PADI_CODE || ph->code == PADR_CODE) ++ { ++ if (priv->ethBrExtInfo.addPPPoETag) { ++ struct pppoe_tag *tag, *pOldTag; ++ unsigned char tag_buf[40]; ++ int old_tag_len=0; ++ ++ tag = (struct pppoe_tag *)tag_buf; ++ pOldTag = (struct pppoe_tag *)__nat25_find_pppoe_tag(ph, ntohs(PTT_RELAY_SID)); ++ if (pOldTag) { // if SID existed, copy old value and delete it ++ old_tag_len = ntohs(pOldTag->tag_len); ++ if (old_tag_len+TAG_HDR_LEN+MAGIC_CODE_LEN+RTL_RELAY_TAG_LEN > sizeof(tag_buf)) { ++ DEBUG_ERR("SID tag length too long!\n"); ++ return -1; ++ } ++ ++ memcpy(tag->tag_data+MAGIC_CODE_LEN+RTL_RELAY_TAG_LEN, ++ pOldTag->tag_data, old_tag_len); ++ ++ if (skb_pull_and_merge(skb, (unsigned char *)pOldTag, TAG_HDR_LEN+old_tag_len) < 0) { ++ DEBUG_ERR("call skb_pull_and_merge() failed in PADI/R packet!\n"); ++ return -1; ++ } ++ ph->length = htons(ntohs(ph->length)-TAG_HDR_LEN-old_tag_len); ++ } ++ ++ tag->tag_type = PTT_RELAY_SID; ++ tag->tag_len = htons(MAGIC_CODE_LEN+RTL_RELAY_TAG_LEN+old_tag_len); ++ ++ // insert the magic_code+client mac in relay tag ++ pMagic = (unsigned short *)tag->tag_data; ++ *pMagic = htons(MAGIC_CODE); ++ memcpy(tag->tag_data+MAGIC_CODE_LEN, skb->data+ETH_ALEN, ETH_ALEN); ++ ++ //Add relay tag ++ if(__nat25_add_pppoe_tag(skb, tag) < 0) ++ return -1; ++ ++ DEBUG_INFO("NAT25: Insert PPPoE, forward %s packet\n", ++ (ph->code == PADI_CODE ? "PADI" : "PADR")); ++ } ++ else { // not add relay tag ++ if (priv->pppoe_connection_in_progress && ++ memcmp(skb->data+ETH_ALEN, priv->pppoe_addr, ETH_ALEN)) { ++ DEBUG_ERR("Discard PPPoE packet due to another PPPoE connection is in progress!\n"); ++ return -2; ++ } ++ ++ if (priv->pppoe_connection_in_progress == 0) ++ memcpy(priv->pppoe_addr, skb->data+ETH_ALEN, ETH_ALEN); ++ ++ priv->pppoe_connection_in_progress = WAIT_TIME_PPPOE; ++ } ++ } ++ else ++ return -1; ++ } ++ else // session phase ++ { ++ DEBUG_INFO("NAT25: Insert PPPoE, insert session packet to %s\n", skb->dev->name); ++ ++ __nat25_generate_pppoe_network_addr(networkAddr, skb->data, &(ph->sid)); ++ ++ __nat25_db_network_insert(priv, skb->data+ETH_ALEN, networkAddr); ++ ++ __nat25_db_print(priv); ++ ++ if (!priv->ethBrExtInfo.addPPPoETag && ++ priv->pppoe_connection_in_progress && ++ !memcmp(skb->data+ETH_ALEN, priv->pppoe_addr, ETH_ALEN)) ++ priv->pppoe_connection_in_progress = 0; ++ } ++ return 0; ++ ++ case NAT25_LOOKUP: ++ if(ph->code == PADO_CODE || ph->code == PADS_CODE) ++ { ++ if (priv->ethBrExtInfo.addPPPoETag) { ++ struct pppoe_tag *tag; ++ unsigned char *ptr; ++ unsigned short tagType, tagLen; ++ int offset=0; ++ ++ if((ptr = __nat25_find_pppoe_tag(ph, ntohs(PTT_RELAY_SID))) == 0) { ++ DEBUG_ERR("Fail to find PTT_RELAY_SID in FADO!\n"); ++ return -1; ++ } ++ ++ tag = (struct pppoe_tag *)ptr; ++ tagType = (unsigned short)((ptr[0] << 8) + ptr[1]); ++ tagLen = (unsigned short)((ptr[2] << 8) + ptr[3]); ++ ++ if((tagType != ntohs(PTT_RELAY_SID)) || (tagLen < (MAGIC_CODE_LEN+RTL_RELAY_TAG_LEN))) { ++ DEBUG_ERR("Invalid PTT_RELAY_SID tag length [%d]!\n", tagLen); ++ return -1; ++ } ++ ++ pMagic = (unsigned short *)tag->tag_data; ++ if (ntohs(*pMagic) != MAGIC_CODE) { ++ DEBUG_ERR("Can't find MAGIC_CODE in %s packet!\n", ++ (ph->code == PADO_CODE ? "PADO" : "PADS")); ++ return -1; ++ } ++ ++ memcpy(skb->data, tag->tag_data+MAGIC_CODE_LEN, ETH_ALEN); ++ ++ if (tagLen > MAGIC_CODE_LEN+RTL_RELAY_TAG_LEN) ++ offset = TAG_HDR_LEN; ++ ++ if (skb_pull_and_merge(skb, ptr+offset, TAG_HDR_LEN+MAGIC_CODE_LEN+RTL_RELAY_TAG_LEN-offset) < 0) { ++ DEBUG_ERR("call skb_pull_and_merge() failed in PADO packet!\n"); ++ return -1; ++ } ++ ph->length = htons(ntohs(ph->length)-(TAG_HDR_LEN+MAGIC_CODE_LEN+RTL_RELAY_TAG_LEN-offset)); ++ if (offset > 0) ++ tag->tag_len = htons(tagLen-MAGIC_CODE_LEN-RTL_RELAY_TAG_LEN); ++ ++ DEBUG_INFO("NAT25: Lookup PPPoE, forward %s Packet from %s\n", ++ (ph->code == PADO_CODE ? "PADO" : "PADS"), skb->dev->name); ++ } ++ else { // not add relay tag ++ if (!priv->pppoe_connection_in_progress) { ++ DEBUG_ERR("Discard PPPoE packet due to no connection in progresss!\n"); ++ return -1; ++ } ++ memcpy(skb->data, priv->pppoe_addr, ETH_ALEN); ++ priv->pppoe_connection_in_progress = WAIT_TIME_PPPOE; ++ } ++ } ++ else { ++ if(ph->sid != 0) ++ { ++ DEBUG_INFO("NAT25: Lookup PPPoE, lookup session packet from %s\n", skb->dev->name); ++ __nat25_generate_pppoe_network_addr(networkAddr, skb->data+ETH_ALEN, &(ph->sid)); ++ ++ __nat25_db_network_lookup_and_replace(priv, skb, networkAddr); ++ ++ __nat25_db_print(priv); ++ } ++ else ++ return -1; ++ ++ } ++ return 0; ++ ++ default: ++ return -1; ++ } ++ } ++ ++ /*---------------------------------------------------*/ ++ /* Handle EAP frame */ ++ /*---------------------------------------------------*/ ++ else if(protocol == __constant_htons(0x888e)) ++ { ++ switch(method) ++ { ++ case NAT25_CHECK: ++ return -1; ++ ++ case NAT25_INSERT: ++ return 0; ++ ++ case NAT25_LOOKUP: ++ return 0; ++ ++ default: ++ return -1; ++ } ++ } ++ ++ /*---------------------------------------------------*/ ++ /* Handle C-Media proprietary frame */ ++ /*---------------------------------------------------*/ ++ else if((protocol == __constant_htons(0xe2ae)) || ++ (protocol == __constant_htons(0xe2af))) ++ { ++ switch(method) ++ { ++ case NAT25_CHECK: ++ return -1; ++ ++ case NAT25_INSERT: ++ return 0; ++ ++ case NAT25_LOOKUP: ++ return 0; ++ ++ default: ++ return -1; ++ } ++ } ++ ++ /*---------------------------------------------------*/ ++ /* Handle IPV6 frame */ ++ /*---------------------------------------------------*/ ++#ifdef CL_IPV6_PASS ++ else if(protocol == __constant_htons(ETH_P_IPV6)) ++ { ++ struct ipv6hdr *iph = (struct ipv6hdr *)(skb->data + ETH_HLEN); ++ ++ if (sizeof(*iph) >= (skb->len - ETH_HLEN)) ++ { ++ DEBUG_WARN("NAT25: malformed IPv6 packet !\n"); ++ return -1; ++ } ++ ++ switch(method) ++ { ++ case NAT25_CHECK: ++ if (skb->data[0] & 1) ++ return 0; ++ return -1; ++ ++ case NAT25_INSERT: ++ { ++ DEBUG_INFO("NAT25: Insert IP, SA=%4x:%4x:%4x:%4x:%4x:%4x:%4x:%4x," ++ " DA=%4x:%4x:%4x:%4x:%4x:%4x:%4x:%4x\n", ++ iph->saddr.s6_addr16[0],iph->saddr.s6_addr16[1],iph->saddr.s6_addr16[2],iph->saddr.s6_addr16[3], ++ iph->saddr.s6_addr16[4],iph->saddr.s6_addr16[5],iph->saddr.s6_addr16[6],iph->saddr.s6_addr16[7], ++ iph->daddr.s6_addr16[0],iph->daddr.s6_addr16[1],iph->daddr.s6_addr16[2],iph->daddr.s6_addr16[3], ++ iph->daddr.s6_addr16[4],iph->daddr.s6_addr16[5],iph->daddr.s6_addr16[6],iph->daddr.s6_addr16[7]); ++ ++ if (memcmp(&iph->saddr, "\x0\x0\x0\x0\x0\x0\x0\x0\x0\x0\x0\x0\x0\x0\x0\x0", 16)) { ++ __nat25_generate_ipv6_network_addr(networkAddr, (unsigned int *)&iph->saddr); ++ __nat25_db_network_insert(priv, skb->data+ETH_ALEN, networkAddr); ++ __nat25_db_print(priv); ++ ++ if (iph->nexthdr == IPPROTO_ICMPV6 && ++ skb->len > (ETH_HLEN + sizeof(*iph) + 4)) { ++ if (update_nd_link_layer_addr(skb->data + ETH_HLEN + sizeof(*iph), ++ skb->len - ETH_HLEN - sizeof(*iph), GET_MY_HWADDR(priv))) { ++ struct icmp6hdr *hdr = (struct icmp6hdr *)(skb->data + ETH_HLEN + sizeof(*iph)); ++ hdr->icmp6_cksum = 0; ++ hdr->icmp6_cksum = csum_ipv6_magic(&iph->saddr, &iph->daddr, ++ iph->payload_len, ++ IPPROTO_ICMPV6, ++ csum_partial((__u8 *)hdr, iph->payload_len, 0)); ++ } ++ } ++ } ++ } ++ return 0; ++ ++ case NAT25_LOOKUP: ++ DEBUG_INFO("NAT25: Lookup IP, SA=%4x:%4x:%4x:%4x:%4x:%4x:%4x:%4x," ++ " DA=%4x:%4x:%4x:%4x:%4x:%4x:%4x:%4x\n", ++ iph->saddr.s6_addr16[0],iph->saddr.s6_addr16[1],iph->saddr.s6_addr16[2],iph->saddr.s6_addr16[3], ++ iph->saddr.s6_addr16[4],iph->saddr.s6_addr16[5],iph->saddr.s6_addr16[6],iph->saddr.s6_addr16[7], ++ iph->daddr.s6_addr16[0],iph->daddr.s6_addr16[1],iph->daddr.s6_addr16[2],iph->daddr.s6_addr16[3], ++ iph->daddr.s6_addr16[4],iph->daddr.s6_addr16[5],iph->daddr.s6_addr16[6],iph->daddr.s6_addr16[7]); ++ ++ ++ __nat25_generate_ipv6_network_addr(networkAddr, (unsigned int *)&iph->daddr); ++ if (!__nat25_db_network_lookup_and_replace(priv, skb, networkAddr)) { ++#ifdef SUPPORT_RX_UNI2MCAST ++ if (iph->daddr.s6_addr[0] == 0xff) ++ convert_ipv6_mac_to_mc(skb); ++#endif ++ } ++ return 0; ++ ++ default: ++ return -1; ++ } ++ } ++#endif // CL_IPV6_PASS ++ ++ return -1; ++} ++ ++ ++int nat25_handle_frame(_adapter *priv, struct sk_buff *skb) ++{ ++#ifdef BR_EXT_DEBUG ++ if((!priv->ethBrExtInfo.nat25_disable) && (!(skb->data[0] & 1))) ++ { ++ panic_printk("NAT25: Input Frame: DA=%02x%02x%02x%02x%02x%02x SA=%02x%02x%02x%02x%02x%02x\n", ++ skb->data[0], ++ skb->data[1], ++ skb->data[2], ++ skb->data[3], ++ skb->data[4], ++ skb->data[5], ++ skb->data[6], ++ skb->data[7], ++ skb->data[8], ++ skb->data[9], ++ skb->data[10], ++ skb->data[11]); ++ } ++#endif ++ ++ if(!(skb->data[0] & 1)) ++ { ++ int is_vlan_tag=0, i, retval=0; ++ unsigned short vlan_hdr=0; ++ ++ if (*((unsigned short *)(skb->data+ETH_ALEN*2)) == __constant_htons(ETH_P_8021Q)) { ++ is_vlan_tag = 1; ++ vlan_hdr = *((unsigned short *)(skb->data+ETH_ALEN*2+2)); ++ for (i=0; i<6; i++) ++ *((unsigned short *)(skb->data+ETH_ALEN*2+2-i*2)) = *((unsigned short *)(skb->data+ETH_ALEN*2-2-i*2)); ++ skb_pull(skb, 4); ++ } ++ ++ if (!priv->ethBrExtInfo.nat25_disable) ++ { ++ _irqL irqL; ++ _enter_critical_bh(&priv->br_ext_lock, &irqL); ++ /* ++ * This function look up the destination network address from ++ * the NAT2.5 database. Return value = -1 means that the ++ * corresponding network protocol is NOT support. ++ */ ++ if (!priv->ethBrExtInfo.nat25sc_disable && ++ (*((unsigned short *)(skb->data+ETH_ALEN*2)) == __constant_htons(ETH_P_IP)) && ++ !memcmp(priv->scdb_ip, skb->data+ETH_HLEN+16, 4)) { ++ memcpy(skb->data, priv->scdb_mac, ETH_ALEN); ++ ++ _exit_critical_bh(&priv->br_ext_lock, &irqL); ++ } ++ else { ++ _exit_critical_bh(&priv->br_ext_lock, &irqL); ++ ++ retval = nat25_db_handle(priv, skb, NAT25_LOOKUP); ++ } ++ } ++ else { ++ if (((*((unsigned short *)(skb->data+ETH_ALEN*2)) == __constant_htons(ETH_P_IP)) && ++ !memcmp(priv->br_ip, skb->data+ETH_HLEN+16, 4)) || ++ ((*((unsigned short *)(skb->data+ETH_ALEN*2)) == __constant_htons(ETH_P_ARP)) && ++ !memcmp(priv->br_ip, skb->data+ETH_HLEN+24, 4))) { ++ // for traffic to upper TCP/IP ++ retval = nat25_db_handle(priv, skb, NAT25_LOOKUP); ++ } ++ } ++ ++ if (is_vlan_tag) { ++ skb_push(skb, 4); ++ for (i=0; i<6; i++) ++ *((unsigned short *)(skb->data+i*2)) = *((unsigned short *)(skb->data+4+i*2)); ++ *((unsigned short *)(skb->data+ETH_ALEN*2)) = __constant_htons(ETH_P_8021Q); ++ *((unsigned short *)(skb->data+ETH_ALEN*2+2)) = vlan_hdr; ++ } ++ ++ if(retval == -1) { ++ //DEBUG_ERR("NAT25: Lookup fail!\n"); ++ return -1; ++ } ++ } ++ ++ return 0; ++} ++ ++#if 0 ++void mac_clone(_adapter *priv, unsigned char *addr) ++{ ++ struct sockaddr sa; ++ ++ memcpy(sa.sa_data, addr, ETH_ALEN); ++ DEBUG_INFO("MAC Clone: Addr=%02x%02x%02x%02x%02x%02x\n", ++ addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]); ++ rtl8192cd_set_hwaddr(priv->dev, &sa); ++} ++ ++ ++int mac_clone_handle_frame(_adapter *priv, struct sk_buff *skb) ++{ ++ if(priv->ethBrExtInfo.macclone_enable && !priv->macclone_completed) ++ { ++ if(!(skb->data[ETH_ALEN] & 1)) //// check any other particular MAC add ++ { ++ if(memcmp(skb->data+ETH_ALEN, GET_MY_HWADDR(priv), ETH_ALEN) && ++ ((priv->dev->br_port) && ++ memcmp(skb->data+ETH_ALEN, priv->br_mac, ETH_ALEN))) ++ { ++ mac_clone(priv, skb->data+ETH_ALEN); ++ priv->macclone_completed = 1; ++ } ++ } ++ } ++ ++ return 0; ++} ++#endif // 0 ++ ++#define SERVER_PORT 67 ++#define CLIENT_PORT 68 ++#define DHCP_MAGIC 0x63825363 ++#define BROADCAST_FLAG 0x8000 ++ ++struct dhcpMessage { ++ u_int8_t op; ++ u_int8_t htype; ++ u_int8_t hlen; ++ u_int8_t hops; ++ u_int32_t xid; ++ u_int16_t secs; ++ u_int16_t flags; ++ u_int32_t ciaddr; ++ u_int32_t yiaddr; ++ u_int32_t siaddr; ++ u_int32_t giaddr; ++ u_int8_t chaddr[16]; ++ u_int8_t sname[64]; ++ u_int8_t file[128]; ++ u_int32_t cookie; ++ u_int8_t options[308]; /* 312 - cookie */ ++}; ++ ++void dhcp_flag_bcast(_adapter *priv, struct sk_buff *skb) ++{ ++ if(skb == NULL) ++ return; ++ ++ if(!priv->ethBrExtInfo.dhcp_bcst_disable) ++ { ++ unsigned short protocol = *((unsigned short *)(skb->data + 2 * ETH_ALEN)); ++ ++ if(protocol == __constant_htons(ETH_P_IP)) // IP ++ { ++ struct iphdr* iph = (struct iphdr *)(skb->data + ETH_HLEN); ++ ++ if(iph->protocol == IPPROTO_UDP) // UDP ++ { ++ struct udphdr *udph = (struct udphdr *)((unsigned int)iph + (iph->ihl << 2)); ++ ++ if((udph->source == __constant_htons(CLIENT_PORT)) ++ && (udph->dest == __constant_htons(SERVER_PORT))) // DHCP request ++ { ++ struct dhcpMessage *dhcph = ++ (struct dhcpMessage *)((unsigned int)udph + sizeof(struct udphdr)); ++ ++ if(dhcph->cookie == __constant_htonl(DHCP_MAGIC)) // match magic word ++ { ++ if(!(dhcph->flags & htons(BROADCAST_FLAG))) // if not broadcast ++ { ++ register int sum = 0; ++ ++ DEBUG_INFO("DHCP: change flag of DHCP request to broadcast.\n"); ++ // or BROADCAST flag ++ dhcph->flags |= htons(BROADCAST_FLAG); ++ // recalculate checksum ++ sum = ~(udph->check) & 0xffff; ++ sum += dhcph->flags; ++ while(sum >> 16) ++ sum = (sum & 0xffff) + (sum >> 16); ++ udph->check = ~sum; ++ } ++ } ++ } ++ } ++ } ++ } ++} ++ ++ ++void *scdb_findEntry(_adapter *priv, unsigned char *macAddr, ++ unsigned char *ipAddr) ++{ ++ unsigned char networkAddr[MAX_NETWORK_ADDR_LEN]; ++ struct nat25_network_db_entry *db; ++ int hash; ++ //_irqL irqL; ++ //_enter_critical_bh(&priv->br_ext_lock, &irqL); ++ ++ __nat25_generate_ipv4_network_addr(networkAddr, (unsigned int *)ipAddr); ++ hash = __nat25_network_hash(networkAddr); ++ db = priv->nethash[hash]; ++ while (db != NULL) ++ { ++ if(!memcmp(db->networkAddr, networkAddr, MAX_NETWORK_ADDR_LEN)) { ++ //_exit_critical_bh(&priv->br_ext_lock, &irqL); ++ return (void *)db; ++ } ++ ++ db = db->next_hash; ++ } ++ ++ //_exit_critical_bh(&priv->br_ext_lock, &irqL); ++ return NULL; ++} ++ ++#endif // CONFIG_BR_EXT +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/core/rtw_cmd.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/core/rtw_cmd.c 2013-07-26 19:36:04.000000000 +0000 +@@ -0,0 +1,2573 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++******************************************************************************/ ++#define _RTW_CMD_C_ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#ifdef CONFIG_BR_EXT ++#include ++#endif //CONFIG_BR_EXT ++/* ++Caller and the rtw_cmd_thread can protect cmd_q by spin_lock. ++No irqsave is necessary. ++*/ ++ ++sint _rtw_init_cmd_priv (struct cmd_priv *pcmdpriv) ++{ ++ sint res=_SUCCESS; ++ ++_func_enter_; ++ ++ _rtw_init_sema(&(pcmdpriv->cmd_queue_sema), 0); ++ //_rtw_init_sema(&(pcmdpriv->cmd_done_sema), 0); ++ _rtw_init_sema(&(pcmdpriv->terminate_cmdthread_sema), 0); ++ ++ ++ _rtw_init_queue(&(pcmdpriv->cmd_queue)); ++ ++ //allocate DMA-able/Non-Page memory for cmd_buf and rsp_buf ++ ++ pcmdpriv->cmd_seq = 1; ++ ++ pcmdpriv->cmd_allocated_buf = rtw_zmalloc(MAX_CMDSZ + CMDBUFF_ALIGN_SZ); ++ ++ if (pcmdpriv->cmd_allocated_buf == NULL){ ++ res= _FAIL; ++ goto exit; ++ } ++ ++ //pcmdpriv->cmd_buf = pcmdpriv->cmd_allocated_buf + CMDBUFF_ALIGN_SZ - ( (SIZE_PTR)(pcmdpriv->cmd_allocated_buf) & (CMDBUFF_ALIGN_SZ-1)); ++ pcmdpriv->cmd_buf = (u8 *)N_BYTE_ALIGMENT((SIZE_PTR)(pcmdpriv->cmd_allocated_buf ), CMDBUFF_ALIGN_SZ); ++ ++ pcmdpriv->rsp_allocated_buf = rtw_zmalloc(MAX_RSPSZ + 4); ++ ++ if (pcmdpriv->rsp_allocated_buf == NULL){ ++ res= _FAIL; ++ goto exit; ++ } ++ ++ //pcmdpriv->rsp_buf = pcmdpriv->rsp_allocated_buf + 4 - ( (SIZE_PTR)(pcmdpriv->rsp_allocated_buf) & 3); ++ pcmdpriv->rsp_buf = (u8 *)N_BYTE_ALIGMENT((SIZE_PTR)(pcmdpriv->rsp_allocated_buf ), 4); ++ ++ pcmdpriv->cmd_issued_cnt = pcmdpriv->cmd_done_cnt = pcmdpriv->rsp_cnt = 0; ++ ++exit: ++ ++_func_exit_; ++ ++ return res; ++ ++} ++ ++ ++sint _rtw_init_evt_priv(struct evt_priv *pevtpriv) ++{ ++ sint res=_SUCCESS; ++ ++_func_enter_; ++ ++#ifdef CONFIG_H2CLBK ++ _rtw_init_sema(&(pevtpriv->lbkevt_done), 0); ++ pevtpriv->lbkevt_limit = 0; ++ pevtpriv->lbkevt_num = 0; ++ pevtpriv->cmdevt_parm = NULL; ++#endif ++ ++ //allocate DMA-able/Non-Page memory for cmd_buf and rsp_buf ++ ATOMIC_SET(&pevtpriv->event_seq, 0); ++ pevtpriv->evt_done_cnt = 0; ++ ++#ifdef CONFIG_EVENT_THREAD_MODE ++ ++ _rtw_init_sema(&(pevtpriv->evt_notify), 0); ++ _rtw_init_sema(&(pevtpriv->terminate_evtthread_sema), 0); ++ ++ pevtpriv->evt_allocated_buf = rtw_zmalloc(MAX_EVTSZ + 4); ++ if (pevtpriv->evt_allocated_buf == NULL){ ++ res= _FAIL; ++ goto exit; ++ } ++ //pevtpriv->evt_buf = pevtpriv->evt_allocated_buf + 4 - ((unsigned int)(pevtpriv->evt_allocated_buf) & 3); ++ pevtpriv->evt_buf = (u8 *)N_BYTE_ALIGMENT((SIZE_PTR)(pevtpriv->evt_allocated_buf ), 4); ++ ++ ++#ifdef CONFIG_SDIO_HCI ++ pevtpriv->allocated_c2h_mem = rtw_zmalloc(C2H_MEM_SZ +4); ++ ++ if (pevtpriv->allocated_c2h_mem == NULL){ ++ res= _FAIL; ++ goto exit; ++ } ++ ++ //pevtpriv->c2h_mem = pevtpriv->allocated_c2h_mem + 4 ++ //- ( (u32)(pevtpriv->allocated_c2h_mem) & 3); ++ pevtpriv->c2h_mem = (u8 *)N_BYTE_ALIGMENT((SIZE_PTR)(pevtpriv->allocated_c2h_mem ), 4); ++ ++#ifdef PLATFORM_OS_XP ++ pevtpriv->pc2h_mdl= IoAllocateMdl((u8 *)pevtpriv->c2h_mem, C2H_MEM_SZ , FALSE, FALSE, NULL); ++ ++ if(pevtpriv->pc2h_mdl == NULL){ ++ res= _FAIL; ++ goto exit; ++ } ++ MmBuildMdlForNonPagedPool(pevtpriv->pc2h_mdl); ++#endif ++#endif //end of CONFIG_SDIO_HCI ++ ++ _rtw_init_queue(&(pevtpriv->evt_queue)); ++ ++exit: ++ ++#endif //end of CONFIG_EVENT_THREAD_MODE ++ ++_func_exit_; ++ ++ return res; ++} ++ ++void _rtw_free_evt_priv (struct evt_priv *pevtpriv) ++{ ++_func_enter_; ++ ++ RT_TRACE(_module_rtl871x_cmd_c_,_drv_info_,("+_rtw_free_evt_priv \n")); ++ ++#ifdef CONFIG_EVENT_THREAD_MODE ++ _rtw_free_sema(&(pevtpriv->evt_notify)); ++ _rtw_free_sema(&(pevtpriv->terminate_evtthread_sema)); ++ ++ ++ if (pevtpriv->evt_allocated_buf) ++ rtw_mfree(pevtpriv->evt_allocated_buf, MAX_EVTSZ + 4); ++#endif ++ ++ RT_TRACE(_module_rtl871x_cmd_c_,_drv_info_,("-_rtw_free_evt_priv \n")); ++ ++_func_exit_; ++ ++} ++ ++void _rtw_free_cmd_priv (struct cmd_priv *pcmdpriv) ++{ ++_func_enter_; ++ ++ if(pcmdpriv){ ++ _rtw_spinlock_free(&(pcmdpriv->cmd_queue.lock)); ++ _rtw_free_sema(&(pcmdpriv->cmd_queue_sema)); ++ //_rtw_free_sema(&(pcmdpriv->cmd_done_sema)); ++ _rtw_free_sema(&(pcmdpriv->terminate_cmdthread_sema)); ++ ++ if (pcmdpriv->cmd_allocated_buf) ++ rtw_mfree(pcmdpriv->cmd_allocated_buf, MAX_CMDSZ + CMDBUFF_ALIGN_SZ); ++ ++ if (pcmdpriv->rsp_allocated_buf) ++ rtw_mfree(pcmdpriv->rsp_allocated_buf, MAX_RSPSZ + 4); ++ } ++_func_exit_; ++} ++ ++/* ++Calling Context: ++ ++rtw_enqueue_cmd can only be called between kernel thread, ++since only spin_lock is used. ++ ++ISR/Call-Back functions can't call this sub-function. ++ ++*/ ++ ++sint _rtw_enqueue_cmd(_queue *queue, struct cmd_obj *obj) ++{ ++ _irqL irqL; ++ ++_func_enter_; ++ ++ if (obj == NULL) ++ goto exit; ++ ++ //_enter_critical_bh(&queue->lock, &irqL); ++ _enter_critical(&queue->lock, &irqL); ++ ++ rtw_list_insert_tail(&obj->list, &queue->queue); ++ ++ //_exit_critical_bh(&queue->lock, &irqL); ++ _exit_critical(&queue->lock, &irqL); ++ ++exit: ++ ++_func_exit_; ++ ++ return _SUCCESS; ++} ++ ++struct cmd_obj *_rtw_dequeue_cmd(_queue *queue) ++{ ++ _irqL irqL; ++ struct cmd_obj *obj; ++ ++_func_enter_; ++ ++ //_enter_critical_bh(&(queue->lock), &irqL); ++ _enter_critical(&(queue->lock), &irqL); ++ ++ if (rtw_is_list_empty(&(queue->queue))) ++ obj = NULL; ++ else ++ { ++ obj = LIST_CONTAINOR(get_next(&(queue->queue)), struct cmd_obj, list); ++ rtw_list_delete(&obj->list); ++ } ++ ++ //_exit_critical_bh(&(queue->lock), &irqL); ++ _exit_critical(&(queue->lock), &irqL); ++ ++_func_exit_; ++ ++ return obj; ++} ++ ++u32 rtw_init_cmd_priv(struct cmd_priv *pcmdpriv) ++{ ++ u32 res; ++_func_enter_; ++ res = _rtw_init_cmd_priv (pcmdpriv); ++_func_exit_; ++ return res; ++} ++ ++u32 rtw_init_evt_priv (struct evt_priv *pevtpriv) ++{ ++ int res; ++_func_enter_; ++ res = _rtw_init_evt_priv(pevtpriv); ++_func_exit_; ++ return res; ++} ++ ++void rtw_free_evt_priv (struct evt_priv *pevtpriv) ++{ ++_func_enter_; ++ RT_TRACE(_module_rtl871x_cmd_c_,_drv_info_,("rtw_free_evt_priv\n")); ++ _rtw_free_evt_priv(pevtpriv); ++_func_exit_; ++} ++ ++void rtw_free_cmd_priv (struct cmd_priv *pcmdpriv) ++{ ++_func_enter_; ++ RT_TRACE(_module_rtl871x_cmd_c_,_drv_info_,("rtw_free_cmd_priv\n")); ++ _rtw_free_cmd_priv(pcmdpriv); ++_func_exit_; ++} ++ ++int rtw_cmd_filter(struct cmd_priv *pcmdpriv, struct cmd_obj *cmd_obj) ++{ ++ u8 bAllow = _FALSE; //set to _TRUE to allow enqueuing cmd when hw_init_completed is _FALSE ++ ++ #ifdef SUPPORT_HW_RFOFF_DETECTED ++ //To decide allow or not ++ if( (pcmdpriv->padapter->pwrctrlpriv.bHWPwrPindetect) ++ &&(!pcmdpriv->padapter->registrypriv.usbss_enable) ++ ) ++ { ++ if(cmd_obj->cmdcode == GEN_CMD_CODE(_Set_Drv_Extra) ) ++ { ++ struct drvextra_cmd_parm *pdrvextra_cmd_parm = (struct drvextra_cmd_parm *)cmd_obj->parmbuf; ++ if(pdrvextra_cmd_parm->ec_id == POWER_SAVING_CTRL_WK_CID) ++ { ++ //DBG_8192C("==>enqueue POWER_SAVING_CTRL_WK_CID\n"); ++ bAllow = _TRUE; ++ } ++ } ++ } ++#endif ++ ++ if(cmd_obj->cmdcode == GEN_CMD_CODE(_SetChannelPlan)) ++ bAllow = _TRUE; ++ ++ if( (pcmdpriv->padapter->hw_init_completed ==_FALSE && bAllow == _FALSE) ++ || pcmdpriv->cmdthd_running== _FALSE //com_thread not running ++ ) ++ { ++ //DBG_871X("%s:%s: drop cmdcode:%u, hw_init_completed:%u, cmdthd_running:%u\n", caller_func, __FUNCTION__, ++ // cmd_obj->cmdcode, ++ // pcmdpriv->padapter->hw_init_completed, ++ // pcmdpriv->cmdthd_running ++ //); ++ ++ return _FAIL; ++ } ++ return _SUCCESS; ++} ++ ++ ++ ++u32 rtw_enqueue_cmd(struct cmd_priv *pcmdpriv, struct cmd_obj *cmd_obj) ++{ ++ int res = _FAIL; ++ ++_func_enter_; ++ ++ if (cmd_obj == NULL) { ++ goto exit; ++ } ++ ++ if( _FAIL == (res=rtw_cmd_filter(pcmdpriv, cmd_obj)) ) { ++ rtw_free_cmd_obj(cmd_obj); ++ goto exit; ++ } ++ ++ res = _rtw_enqueue_cmd(&pcmdpriv->cmd_queue, cmd_obj); ++ ++ if(res == _SUCCESS) ++ _rtw_up_sema(&pcmdpriv->cmd_queue_sema); ++ ++exit: ++ ++_func_exit_; ++ ++ return res; ++} ++ ++struct cmd_obj *rtw_dequeue_cmd(struct cmd_priv *pcmdpriv) ++{ ++ struct cmd_obj *cmd_obj; ++ ++_func_enter_; ++ ++ cmd_obj = _rtw_dequeue_cmd(&pcmdpriv->cmd_queue); ++ ++_func_exit_; ++ return cmd_obj; ++} ++ ++void rtw_cmd_clr_isr(struct cmd_priv *pcmdpriv) ++{ ++_func_enter_; ++ pcmdpriv->cmd_done_cnt++; ++ //_rtw_up_sema(&(pcmdpriv->cmd_done_sema)); ++_func_exit_; ++} ++ ++void rtw_free_cmd_obj(struct cmd_obj *pcmd) ++{ ++_func_enter_; ++ ++ if((pcmd->cmdcode!=_JoinBss_CMD_) &&(pcmd->cmdcode!= _CreateBss_CMD_)) ++ { ++ //free parmbuf in cmd_obj ++ rtw_mfree((unsigned char*)pcmd->parmbuf, pcmd->cmdsz); ++ } ++ ++ if(pcmd->rsp!=NULL) ++ { ++ if(pcmd->rspsz!= 0) ++ { ++ //free rsp in cmd_obj ++ rtw_mfree((unsigned char*)pcmd->rsp, pcmd->rspsz); ++ } ++ } ++ ++ //free cmd_obj ++ rtw_mfree((unsigned char*)pcmd, sizeof(struct cmd_obj)); ++ ++_func_exit_; ++} ++ ++ ++thread_return rtw_cmd_thread(thread_context context) ++{ ++ u8 ret; ++ struct cmd_obj *pcmd; ++ u8 *pcmdbuf, *prspbuf; ++ u8 (*cmd_hdl)(_adapter *padapter, u8* pbuf); ++ void (*pcmd_callback)(_adapter *dev, struct cmd_obj *pcmd); ++ _adapter *padapter = (_adapter *)context; ++ struct cmd_priv *pcmdpriv = &(padapter->cmdpriv); ++ ++_func_enter_; ++ ++ thread_enter(padapter); ++ ++ pcmdbuf = pcmdpriv->cmd_buf; ++ prspbuf = pcmdpriv->rsp_buf; ++ ++ pcmdpriv->cmdthd_running=_TRUE; ++ _rtw_up_sema(&pcmdpriv->terminate_cmdthread_sema); ++ ++ RT_TRACE(_module_rtl871x_cmd_c_,_drv_info_,("start r871x rtw_cmd_thread !!!!\n")); ++ ++ while(1) ++ { ++ if ((_rtw_down_sema(&(pcmdpriv->cmd_queue_sema))) == _FAIL) ++ break; ++ ++ if (rtw_register_cmd_alive(padapter) != _SUCCESS) ++ { ++ continue; ++ } ++ ++_next: ++ if ((padapter->bDriverStopped == _TRUE)||(padapter->bSurpriseRemoved== _TRUE)) ++ { ++ DBG_8192C("###> rtw_cmd_thread break.................\n"); ++ RT_TRACE(_module_rtl871x_cmd_c_, _drv_info_, ("rtw_cmd_thread:bDriverStopped(%d) OR bSurpriseRemoved(%d)", padapter->bDriverStopped, padapter->bSurpriseRemoved)); ++ break; ++ } ++ ++ if(!(pcmd = rtw_dequeue_cmd(pcmdpriv))) { ++ rtw_unregister_cmd_alive(padapter); ++ continue; ++ } ++ ++ if( _FAIL == rtw_cmd_filter(pcmdpriv, pcmd) ) ++ { ++ pcmd->res = H2C_DROPPED; ++ goto post_process; ++ } ++ ++ pcmdpriv->cmd_issued_cnt++; ++ ++ pcmd->cmdsz = _RND4((pcmd->cmdsz));//_RND4 ++ ++ _rtw_memcpy(pcmdbuf, pcmd->parmbuf, pcmd->cmdsz); ++ ++ if(pcmd->cmdcode <= (sizeof(wlancmds) /sizeof(struct cmd_hdl))) ++ { ++ cmd_hdl = wlancmds[pcmd->cmdcode].h2cfuns; ++ ++ if (cmd_hdl) ++ { ++ ret = cmd_hdl(padapter, pcmdbuf); ++ pcmd->res = ret; ++ } ++ ++ pcmdpriv->cmd_seq++; ++ } ++ else ++ { ++ pcmd->res = H2C_PARAMETERS_ERROR; ++ } ++ ++ cmd_hdl = NULL; ++ ++post_process: ++ ++ //call callback function for post-processed ++ if(pcmd->cmdcode <= (sizeof(rtw_cmd_callback) /sizeof(struct _cmd_callback))) ++ { ++ pcmd_callback = rtw_cmd_callback[pcmd->cmdcode].callback; ++ if(pcmd_callback == NULL) ++ { ++ RT_TRACE(_module_rtl871x_cmd_c_,_drv_info_,("mlme_cmd_hdl(): pcmd_callback=0x%p, cmdcode=0x%x\n", pcmd_callback, pcmd->cmdcode)); ++ rtw_free_cmd_obj(pcmd); ++ } ++ else ++ { ++ //todo: !!! fill rsp_buf to pcmd->rsp if (pcmd->rsp!=NULL) ++ pcmd_callback(padapter, pcmd);//need conider that free cmd_obj in rtw_cmd_callback ++ } ++ } ++ ++ ++ flush_signals_thread(); ++ ++ goto _next; ++ ++ } ++ ++ pcmdpriv->cmdthd_running=_FALSE; ++ ++ DBG_871X("%s: leaving... check & free all cmd_obj resources\n", __FUNCTION__); ++ ++ // free all cmd_obj resources ++ do{ ++ pcmd = rtw_dequeue_cmd(pcmdpriv); ++ if(pcmd==NULL) ++ break; ++ ++ DBG_871X("%s: leaving... drop cmdcode:%u\n", __FUNCTION__, pcmd->cmdcode); ++ ++ rtw_free_cmd_obj(pcmd); ++ }while(1); ++ ++ DBG_871X("%s: leaving... call up terminate_cmdthread_sema\n", __FUNCTION__); ++ ++ _rtw_up_sema(&pcmdpriv->terminate_cmdthread_sema); ++ ++_func_exit_; ++ ++ thread_exit(); ++ ++} ++ ++ ++#ifdef CONFIG_EVENT_THREAD_MODE ++u32 rtw_enqueue_evt(struct evt_priv *pevtpriv, struct evt_obj *obj) ++{ ++ _irqL irqL; ++ int res; ++ _queue *queue = &pevtpriv->evt_queue; ++ ++_func_enter_; ++ ++ res = _SUCCESS; ++ ++ if (obj == NULL) { ++ res = _FAIL; ++ goto exit; ++ } ++ ++ _enter_critical_bh(&queue->lock, &irqL); ++ ++ rtw_list_insert_tail(&obj->list, &queue->queue); ++ ++ _exit_critical_bh(&queue->lock, &irqL); ++ ++ //rtw_evt_notify_isr(pevtpriv); ++ ++exit: ++ ++_func_exit_; ++ ++ return res; ++} ++ ++struct evt_obj *rtw_dequeue_evt(_queue *queue) ++{ ++ _irqL irqL; ++ struct evt_obj *pevtobj; ++ ++_func_enter_; ++ ++ _enter_critical_bh(&queue->lock, &irqL); ++ ++ if (rtw_is_list_empty(&(queue->queue))) ++ pevtobj = NULL; ++ else ++ { ++ pevtobj = LIST_CONTAINOR(get_next(&(queue->queue)), struct evt_obj, list); ++ rtw_list_delete(&pevtobj->list); ++ } ++ ++ _exit_critical_bh(&queue->lock, &irqL); ++ ++_func_exit_; ++ ++ return pevtobj; ++} ++ ++void rtw_free_evt_obj(struct evt_obj *pevtobj) ++{ ++_func_enter_; ++ ++ if(pevtobj->parmbuf) ++ rtw_mfree((unsigned char*)pevtobj->parmbuf, pevtobj->evtsz); ++ ++ rtw_mfree((unsigned char*)pevtobj, sizeof(struct evt_obj)); ++ ++_func_exit_; ++} ++ ++void rtw_evt_notify_isr(struct evt_priv *pevtpriv) ++{ ++_func_enter_; ++ pevtpriv->evt_done_cnt++; ++ _rtw_up_sema(&(pevtpriv->evt_notify)); ++_func_exit_; ++} ++#endif ++ ++ ++/* ++u8 rtw_setstandby_cmd(unsigned char *adapter) ++*/ ++u8 rtw_setstandby_cmd(_adapter *padapter, uint action) ++{ ++ struct cmd_obj* ph2c; ++ struct usb_suspend_parm* psetusbsuspend; ++ struct cmd_priv *pcmdpriv=&padapter->cmdpriv; ++ ++ u8 ret = _SUCCESS; ++ ++_func_enter_; ++ ++ ph2c = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj)); ++ if (ph2c == NULL) { ++ ret = _FAIL; ++ goto exit; ++ } ++ ++ psetusbsuspend = (struct usb_suspend_parm*)rtw_zmalloc(sizeof(struct usb_suspend_parm)); ++ if (psetusbsuspend == NULL) { ++ rtw_mfree((u8 *) ph2c, sizeof(struct cmd_obj)); ++ ret = _FAIL; ++ goto exit; ++ } ++ ++ psetusbsuspend->action = action; ++ ++ init_h2fwcmd_w_parm_no_rsp(ph2c, psetusbsuspend, GEN_CMD_CODE(_SetUsbSuspend)); ++ ++ ret = rtw_enqueue_cmd(pcmdpriv, ph2c); ++ ++exit: ++ ++_func_exit_; ++ ++ return ret; ++} ++ ++/* ++rtw_sitesurvey_cmd(~) ++ ### NOTE:#### (!!!!) ++ MUST TAKE CARE THAT BEFORE CALLING THIS FUNC, YOU SHOULD HAVE LOCKED pmlmepriv->lock ++*/ ++u8 rtw_sitesurvey_cmd(_adapter *padapter, NDIS_802_11_SSID *pssid, int ssid_max_num) ++{ ++ u8 res = _FAIL; ++ struct cmd_obj *ph2c; ++ struct sitesurvey_parm *psurveyPara; ++ struct cmd_priv *pcmdpriv = &padapter->cmdpriv; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++#ifdef CONFIG_P2P ++ struct wifidirect_info *pwdinfo= &(padapter->wdinfo); ++#endif //CONFIG_P2P ++ ++_func_enter_; ++ ++#ifdef CONFIG_LPS ++ if(check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE){ ++ rtw_lps_ctrl_wk_cmd(padapter, LPS_CTRL_SCAN, 1); ++ } ++#endif ++ ++#ifdef CONFIG_P2P ++ p2p_ps_wk_cmd(padapter, P2P_PS_SCAN, 1); ++#endif //CONFIG_P2P ++ ++ ph2c = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj)); ++ if (ph2c == NULL) ++ return _FAIL; ++ ++ psurveyPara = (struct sitesurvey_parm*)rtw_zmalloc(sizeof(struct sitesurvey_parm)); ++ if (psurveyPara == NULL) { ++ rtw_mfree((unsigned char*) ph2c, sizeof(struct cmd_obj)); ++ return _FAIL; ++ } ++ ++ rtw_free_network_queue(padapter, _FALSE); ++ ++ RT_TRACE(_module_rtl871x_cmd_c_, _drv_info_, ("\nflush network queue\n\n")); ++ ++ init_h2fwcmd_w_parm_no_rsp(ph2c, psurveyPara, GEN_CMD_CODE(_SiteSurvey)); ++ ++ psurveyPara->bsslimit = cpu_to_le32(48); ++ psurveyPara->scan_mode = cpu_to_le32(pmlmepriv->scan_mode); ++ ++ _rtw_memset(psurveyPara->ssid, 0, sizeof(NDIS_802_11_SSID)*RTW_SSID_SCAN_AMOUNT); ++ ++ if(pssid){ ++ int i; ++ for(i=0; issid[i], &pssid[i], sizeof(NDIS_802_11_SSID)); ++ //DBG_871X("%s scan for specific ssid: %s, %d\n", __FUNCTION__ ++ // , psurveyPara->ssid[i].Ssid, psurveyPara->ssid[i].SsidLength); ++ } ++ } ++ } ++ ++ set_fwstate(pmlmepriv, _FW_UNDER_SURVEY); ++ ++ res = rtw_enqueue_cmd(pcmdpriv, ph2c); ++ ++ if(res == _SUCCESS) { ++ ++ pmlmepriv->scan_start_time = rtw_get_current_time(); ++ ++ _set_timer(&pmlmepriv->scan_to_timer, SCANNING_TIMEOUT); ++ ++ rtw_led_control(padapter, LED_CTL_SITE_SURVEY); ++ ++ pmlmepriv->scan_interval = SCAN_INTERVAL;// 30*2 sec = 60sec ++ } else { ++ _clr_fwstate_(pmlmepriv, _FW_UNDER_SURVEY); ++ } ++ ++_func_exit_; ++ ++ return res; ++} ++ ++u8 rtw_setdatarate_cmd(_adapter *padapter, u8 *rateset) ++{ ++ struct cmd_obj* ph2c; ++ struct setdatarate_parm* pbsetdataratepara; ++ struct cmd_priv* pcmdpriv = &padapter->cmdpriv; ++ u8 res = _SUCCESS; ++ ++_func_enter_; ++ ++ ph2c = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj)); ++ if (ph2c == NULL) { ++ res = _FAIL; ++ goto exit; ++ } ++ ++ pbsetdataratepara = (struct setdatarate_parm*)rtw_zmalloc(sizeof(struct setdatarate_parm)); ++ if (pbsetdataratepara == NULL) { ++ rtw_mfree((u8 *) ph2c, sizeof(struct cmd_obj)); ++ res = _FAIL; ++ goto exit; ++ } ++ ++ init_h2fwcmd_w_parm_no_rsp(ph2c, pbsetdataratepara, GEN_CMD_CODE(_SetDataRate)); ++#ifdef MP_FIRMWARE_OFFLOAD ++ pbsetdataratepara->curr_rateidx = *(u32*)rateset; ++// _rtw_memcpy(pbsetdataratepara, rateset, sizeof(u32)); ++#else ++ pbsetdataratepara->mac_id = 5; ++ _rtw_memcpy(pbsetdataratepara->datarates, rateset, NumRates); ++#endif ++ res = rtw_enqueue_cmd(pcmdpriv, ph2c); ++exit: ++ ++_func_exit_; ++ ++ return res; ++} ++ ++u8 rtw_setbasicrate_cmd(_adapter *padapter, u8 *rateset) ++{ ++ struct cmd_obj* ph2c; ++ struct setbasicrate_parm* pssetbasicratepara; ++ struct cmd_priv* pcmdpriv=&padapter->cmdpriv; ++ u8 res = _SUCCESS; ++ ++_func_enter_; ++ ++ ph2c = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj)); ++ if (ph2c == NULL) { ++ res= _FAIL; ++ goto exit; ++ } ++ pssetbasicratepara = (struct setbasicrate_parm*)rtw_zmalloc(sizeof(struct setbasicrate_parm)); ++ ++ if (pssetbasicratepara == NULL) { ++ rtw_mfree((u8*) ph2c, sizeof(struct cmd_obj)); ++ res = _FAIL; ++ goto exit; ++ } ++ ++ init_h2fwcmd_w_parm_no_rsp(ph2c, pssetbasicratepara, _SetBasicRate_CMD_); ++ ++ _rtw_memcpy(pssetbasicratepara->basicrates, rateset, NumRates); ++ ++ res = rtw_enqueue_cmd(pcmdpriv, ph2c); ++exit: ++ ++_func_exit_; ++ ++ return res; ++} ++ ++ ++/* ++unsigned char rtw_setphy_cmd(unsigned char *adapter) ++ ++1. be called only after rtw_update_registrypriv_dev_network( ~) or mp testing program ++2. for AdHoc/Ap mode or mp mode? ++ ++*/ ++u8 rtw_setphy_cmd(_adapter *padapter, u8 modem, u8 ch) ++{ ++ struct cmd_obj* ph2c; ++ struct setphy_parm* psetphypara; ++ struct cmd_priv *pcmdpriv=&padapter->cmdpriv; ++// struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++// struct registry_priv* pregistry_priv = &padapter->registrypriv; ++ u8 res=_SUCCESS; ++ ++_func_enter_; ++ ++ ph2c = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj)); ++ if(ph2c==NULL){ ++ res= _FAIL; ++ goto exit; ++ } ++ psetphypara = (struct setphy_parm*)rtw_zmalloc(sizeof(struct setphy_parm)); ++ ++ if(psetphypara==NULL){ ++ rtw_mfree((u8 *) ph2c, sizeof(struct cmd_obj)); ++ res= _FAIL; ++ goto exit; ++ } ++ ++ init_h2fwcmd_w_parm_no_rsp(ph2c, psetphypara, _SetPhy_CMD_); ++ ++ RT_TRACE(_module_rtl871x_cmd_c_,_drv_info_,("CH=%d, modem=%d", ch, modem)); ++ ++ psetphypara->modem = modem; ++ psetphypara->rfchannel = ch; ++ ++ res = rtw_enqueue_cmd(pcmdpriv, ph2c); ++exit: ++_func_exit_; ++ return res; ++} ++ ++u8 rtw_setbbreg_cmd(_adapter*padapter, u8 offset, u8 val) ++{ ++ struct cmd_obj* ph2c; ++ struct writeBB_parm* pwritebbparm; ++ struct cmd_priv *pcmdpriv=&padapter->cmdpriv; ++ u8 res=_SUCCESS; ++_func_enter_; ++ ph2c = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj)); ++ if(ph2c==NULL){ ++ res= _FAIL; ++ goto exit; ++ } ++ pwritebbparm = (struct writeBB_parm*)rtw_zmalloc(sizeof(struct writeBB_parm)); ++ ++ if(pwritebbparm==NULL){ ++ rtw_mfree((u8 *) ph2c, sizeof(struct cmd_obj)); ++ res= _FAIL; ++ goto exit; ++ } ++ ++ init_h2fwcmd_w_parm_no_rsp(ph2c, pwritebbparm, GEN_CMD_CODE(_SetBBReg)); ++ ++ pwritebbparm->offset = offset; ++ pwritebbparm->value = val; ++ ++ res = rtw_enqueue_cmd(pcmdpriv, ph2c); ++exit: ++_func_exit_; ++ return res; ++} ++ ++u8 rtw_getbbreg_cmd(_adapter *padapter, u8 offset, u8 *pval) ++{ ++ struct cmd_obj* ph2c; ++ struct readBB_parm* prdbbparm; ++ struct cmd_priv *pcmdpriv=&padapter->cmdpriv; ++ u8 res=_SUCCESS; ++ ++_func_enter_; ++ ph2c = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj)); ++ if(ph2c==NULL){ ++ res=_FAIL; ++ goto exit; ++ } ++ prdbbparm = (struct readBB_parm*)rtw_zmalloc(sizeof(struct readBB_parm)); ++ ++ if(prdbbparm ==NULL){ ++ rtw_mfree((unsigned char *) ph2c, sizeof(struct cmd_obj)); ++ return _FAIL; ++ } ++ ++ _rtw_init_listhead(&ph2c->list); ++ ph2c->cmdcode =GEN_CMD_CODE(_GetBBReg); ++ ph2c->parmbuf = (unsigned char *)prdbbparm; ++ ph2c->cmdsz = sizeof(struct readBB_parm); ++ ph2c->rsp = pval; ++ ph2c->rspsz = sizeof(struct readBB_rsp); ++ ++ prdbbparm ->offset = offset; ++ ++ res = rtw_enqueue_cmd(pcmdpriv, ph2c); ++exit: ++_func_exit_; ++ return res; ++} ++ ++u8 rtw_setrfreg_cmd(_adapter *padapter, u8 offset, u32 val) ++{ ++ struct cmd_obj* ph2c; ++ struct writeRF_parm* pwriterfparm; ++ struct cmd_priv *pcmdpriv=&padapter->cmdpriv; ++ u8 res=_SUCCESS; ++_func_enter_; ++ ph2c = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj)); ++ if(ph2c==NULL){ ++ res= _FAIL; ++ goto exit; ++ } ++ pwriterfparm = (struct writeRF_parm*)rtw_zmalloc(sizeof(struct writeRF_parm)); ++ ++ if(pwriterfparm==NULL){ ++ rtw_mfree((u8 *) ph2c, sizeof(struct cmd_obj)); ++ res= _FAIL; ++ goto exit; ++ } ++ ++ init_h2fwcmd_w_parm_no_rsp(ph2c, pwriterfparm, GEN_CMD_CODE(_SetRFReg)); ++ ++ pwriterfparm->offset = offset; ++ pwriterfparm->value = val; ++ ++ res = rtw_enqueue_cmd(pcmdpriv, ph2c); ++exit: ++_func_exit_; ++ return res; ++} ++ ++u8 rtw_getrfreg_cmd(_adapter *padapter, u8 offset, u8 *pval) ++{ ++ struct cmd_obj* ph2c; ++ struct readRF_parm* prdrfparm; ++ struct cmd_priv *pcmdpriv=&padapter->cmdpriv; ++ u8 res=_SUCCESS; ++ ++_func_enter_; ++ ++ ph2c = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj)); ++ if(ph2c==NULL){ ++ res= _FAIL; ++ goto exit; ++ } ++ ++ prdrfparm = (struct readRF_parm*)rtw_zmalloc(sizeof(struct readRF_parm)); ++ if(prdrfparm ==NULL){ ++ rtw_mfree((u8 *) ph2c, sizeof(struct cmd_obj)); ++ res= _FAIL; ++ goto exit; ++ } ++ ++ _rtw_init_listhead(&ph2c->list); ++ ph2c->cmdcode =GEN_CMD_CODE(_GetRFReg); ++ ph2c->parmbuf = (unsigned char *)prdrfparm; ++ ph2c->cmdsz = sizeof(struct readRF_parm); ++ ph2c->rsp = pval; ++ ph2c->rspsz = sizeof(struct readRF_rsp); ++ ++ prdrfparm ->offset = offset; ++ ++ res = rtw_enqueue_cmd(pcmdpriv, ph2c); ++ ++exit: ++ ++_func_exit_; ++ ++ return res; ++} ++ ++void rtw_getbbrfreg_cmdrsp_callback(_adapter* padapter, struct cmd_obj *pcmd) ++{ ++ _func_enter_; ++ ++ //rtw_free_cmd_obj(pcmd); ++ rtw_mfree((unsigned char*) pcmd->parmbuf, pcmd->cmdsz); ++ rtw_mfree((unsigned char*) pcmd, sizeof(struct cmd_obj)); ++ ++#ifdef CONFIG_MP_INCLUDED ++ padapter->mppriv.workparam.bcompleted= _TRUE; ++#endif ++_func_exit_; ++} ++ ++void rtw_readtssi_cmdrsp_callback(_adapter* padapter, struct cmd_obj *pcmd) ++{ ++ _func_enter_; ++ ++ rtw_mfree((unsigned char*) pcmd->parmbuf, pcmd->cmdsz); ++ rtw_mfree((unsigned char*) pcmd, sizeof(struct cmd_obj)); ++ ++#ifdef CONFIG_MP_INCLUDED ++ padapter->mppriv.workparam.bcompleted= _TRUE; ++#endif ++ ++_func_exit_; ++} ++ ++u8 rtw_createbss_cmd(_adapter *padapter) ++{ ++ struct cmd_obj* pcmd; ++ struct cmd_priv *pcmdpriv=&padapter->cmdpriv; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ WLAN_BSSID_EX *pdev_network = &padapter->registrypriv.dev_network; ++ u8 res=_SUCCESS; ++ ++_func_enter_; ++ ++ rtw_led_control(padapter, LED_CTL_START_TO_LINK); ++ ++ if (pmlmepriv->assoc_ssid.SsidLength == 0){ ++ RT_TRACE(_module_rtl871x_cmd_c_,_drv_info_,(" createbss for Any SSid:%s\n",pmlmepriv->assoc_ssid.Ssid)); ++ } else { ++ RT_TRACE(_module_rtl871x_cmd_c_,_drv_info_,(" createbss for SSid:%s\n", pmlmepriv->assoc_ssid.Ssid)); ++ } ++ ++ pcmd = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj)); ++ if(pcmd==NULL){ ++ res= _FAIL; ++ goto exit; ++ } ++ ++ _rtw_init_listhead(&pcmd->list); ++ pcmd->cmdcode = _CreateBss_CMD_; ++ pcmd->parmbuf = (unsigned char *)pdev_network; ++ pcmd->cmdsz = get_WLAN_BSSID_EX_sz((WLAN_BSSID_EX*)pdev_network); ++ pcmd->rsp = NULL; ++ pcmd->rspsz = 0; ++ ++ pdev_network->Length = pcmd->cmdsz; ++ ++#ifdef CONFIG_RTL8712 ++ //notes: translate IELength & Length after assign the Length to cmdsz; ++ pdev_network->Length = cpu_to_le32(pcmd->cmdsz); ++ pdev_network->IELength = cpu_to_le32(pdev_network->IELength); ++ pdev_network->Ssid.SsidLength = cpu_to_le32(pdev_network->Ssid.SsidLength); ++#endif ++ ++ res = rtw_enqueue_cmd(pcmdpriv, pcmd); ++ ++exit: ++ ++_func_exit_; ++ ++ return res; ++} ++ ++u8 rtw_createbss_cmd_ex(_adapter *padapter, unsigned char *pbss, unsigned int sz) ++{ ++ struct cmd_obj* pcmd; ++ struct cmd_priv *pcmdpriv=&padapter->cmdpriv; ++ u8 res=_SUCCESS; ++ ++_func_enter_; ++ ++ pcmd = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj)); ++ if(pcmd==NULL){ ++ res= _FAIL; ++ goto exit; ++ } ++ ++ _rtw_init_listhead(&pcmd->list); ++ pcmd->cmdcode = GEN_CMD_CODE(_CreateBss); ++ pcmd->parmbuf = pbss; ++ pcmd->cmdsz = sz; ++ pcmd->rsp = NULL; ++ pcmd->rspsz = 0; ++ ++ res = rtw_enqueue_cmd(pcmdpriv, pcmd); ++ ++exit: ++ ++_func_exit_; ++ ++ return res; ++} ++ ++u8 rtw_joinbss_cmd(_adapter *padapter, struct wlan_network* pnetwork) ++{ ++ u8 *auth, res = _SUCCESS; ++ uint t_len = 0; ++ WLAN_BSSID_EX *psecnetwork; ++ struct cmd_obj *pcmd; ++ struct cmd_priv *pcmdpriv=&padapter->cmdpriv; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct qos_priv *pqospriv= &pmlmepriv->qospriv; ++ struct security_priv *psecuritypriv=&padapter->securitypriv; ++ struct registry_priv *pregistrypriv = &padapter->registrypriv; ++ struct ht_priv *phtpriv = &pmlmepriv->htpriv; ++ NDIS_802_11_NETWORK_INFRASTRUCTURE ndis_network_mode = pnetwork->network.InfrastructureMode; ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ ++_func_enter_; ++ ++ rtw_led_control(padapter, LED_CTL_START_TO_LINK); ++ ++ if (pmlmepriv->assoc_ssid.SsidLength == 0){ ++ RT_TRACE(_module_rtl871x_cmd_c_, _drv_info_, ("+Join cmd: Any SSid\n")); ++ } else { ++ RT_TRACE(_module_rtl871x_cmd_c_, _drv_notice_, ("+Join cmd: SSid=[%s]\n", pmlmepriv->assoc_ssid.Ssid)); ++ } ++ ++ pcmd = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj)); ++ if(pcmd==NULL){ ++ res=_FAIL; ++ RT_TRACE(_module_rtl871x_cmd_c_, _drv_err_, ("rtw_joinbss_cmd: memory allocate for cmd_obj fail!!!\n")); ++ goto exit; ++ } ++ /* // for IEs is pointer ++ t_len = sizeof (ULONG) + sizeof (NDIS_802_11_MAC_ADDRESS) + 2 + ++ sizeof (NDIS_802_11_SSID) + sizeof (ULONG) + ++ sizeof (NDIS_802_11_RSSI) + sizeof (NDIS_802_11_NETWORK_TYPE) + ++ sizeof (NDIS_802_11_CONFIGURATION) + ++ sizeof (NDIS_802_11_NETWORK_INFRASTRUCTURE) + ++ sizeof (NDIS_802_11_RATES_EX)+ sizeof(WLAN_PHY_INFO)+ sizeof (ULONG) + MAX_IE_SZ; ++ */ ++ //for IEs is fix buf size ++ t_len = sizeof(WLAN_BSSID_EX); ++ ++ ++ //for hidden ap to set fw_state here ++ if (check_fwstate(pmlmepriv, WIFI_STATION_STATE|WIFI_ADHOC_STATE) != _TRUE) ++ { ++ switch(ndis_network_mode) ++ { ++ case Ndis802_11IBSS: ++ set_fwstate(pmlmepriv, WIFI_ADHOC_STATE); ++ break; ++ ++ case Ndis802_11Infrastructure: ++ set_fwstate(pmlmepriv, WIFI_STATION_STATE); ++ break; ++ ++ case Ndis802_11APMode: ++ case Ndis802_11AutoUnknown: ++ case Ndis802_11InfrastructureMax: ++ break; ++ ++ } ++ } ++ ++ psecnetwork=(WLAN_BSSID_EX *)&psecuritypriv->sec_bss; ++ if(psecnetwork==NULL) ++ { ++ if(pcmd !=NULL) ++ rtw_mfree((unsigned char *)pcmd, sizeof(struct cmd_obj)); ++ ++ res=_FAIL; ++ ++ RT_TRACE(_module_rtl871x_cmd_c_, _drv_err_, ("rtw_joinbss_cmd :psecnetwork==NULL!!!\n")); ++ ++ goto exit; ++ } ++ ++ _rtw_memset(psecnetwork, 0, t_len); ++ ++ _rtw_memcpy(psecnetwork, &pnetwork->network, get_WLAN_BSSID_EX_sz(&pnetwork->network)); ++ ++ auth=&psecuritypriv->authenticator_ie[0]; ++ psecuritypriv->authenticator_ie[0]=(unsigned char)psecnetwork->IELength; ++ ++ if((psecnetwork->IELength-12) < (256-1)) { ++ _rtw_memcpy(&psecuritypriv->authenticator_ie[1], &psecnetwork->IEs[12], psecnetwork->IELength-12); ++ } else { ++ _rtw_memcpy(&psecuritypriv->authenticator_ie[1], &psecnetwork->IEs[12], (256-1)); ++ } ++ ++ psecnetwork->IELength = 0; ++ // Added by Albert 2009/02/18 ++ // If the the driver wants to use the bssid to create the connection. ++ // If not, we have to copy the connecting AP's MAC address to it so that ++ // the driver just has the bssid information for PMKIDList searching. ++ ++ if ( pmlmepriv->assoc_by_bssid == _FALSE ) ++ { ++ _rtw_memcpy( &pmlmepriv->assoc_bssid[ 0 ], &pnetwork->network.MacAddress[ 0 ], ETH_ALEN ); ++ } ++ ++ psecnetwork->IELength = rtw_restruct_sec_ie(padapter, &pnetwork->network.IEs[0], &psecnetwork->IEs[0], pnetwork->network.IELength); ++ ++ ++ pqospriv->qos_option = 0; ++ ++ if(pregistrypriv->wmm_enable) ++ { ++ u32 tmp_len; ++ ++ tmp_len = rtw_restruct_wmm_ie(padapter, &pnetwork->network.IEs[0], &psecnetwork->IEs[0], pnetwork->network.IELength, psecnetwork->IELength); ++ ++ if (psecnetwork->IELength != tmp_len) ++ { ++ psecnetwork->IELength = tmp_len; ++ pqospriv->qos_option = 1; //There is WMM IE in this corresp. beacon ++ } ++ else ++ { ++ pqospriv->qos_option = 0;//There is no WMM IE in this corresp. beacon ++ } ++ } ++ ++#ifdef CONFIG_80211N_HT ++ phtpriv->ht_option = _FALSE; ++ if(pregistrypriv->ht_enable) ++ { ++ // Added by Albert 2010/06/23 ++ // For the WEP mode, we will use the bg mode to do the connection to avoid some IOT issue. ++ // Especially for Realtek 8192u SoftAP. ++ if ( ( padapter->securitypriv.dot11PrivacyAlgrthm != _WEP40_ ) && ++ ( padapter->securitypriv.dot11PrivacyAlgrthm != _WEP104_ ) && ++ ( padapter->securitypriv.dot11PrivacyAlgrthm != _TKIP_ )) ++ { ++ //rtw_restructure_ht_ie ++ rtw_restructure_ht_ie(padapter, &pnetwork->network.IEs[0], &psecnetwork->IEs[0], ++ pnetwork->network.IELength, &psecnetwork->IELength); ++ } ++ } ++ ++#endif ++ ++ pmlmeinfo->assoc_AP_vendor = check_assoc_AP(pnetwork->network.IEs, pnetwork->network.IELength); ++ ++ #if 0 ++ psecuritypriv->supplicant_ie[0]=(u8)psecnetwork->IELength; ++ ++ if(psecnetwork->IELength < (256-1)) ++ { ++ _rtw_memcpy(&psecuritypriv->supplicant_ie[1], &psecnetwork->IEs[0], psecnetwork->IELength); ++ } ++ else ++ { ++ _rtw_memcpy(&psecuritypriv->supplicant_ie[1], &psecnetwork->IEs[0], (256-1)); ++ } ++ #endif ++ ++ pcmd->cmdsz = get_WLAN_BSSID_EX_sz(psecnetwork);//get cmdsz before endian conversion ++ ++#ifdef CONFIG_RTL8712 ++ //wlan_network endian conversion ++ psecnetwork->Length = cpu_to_le32(psecnetwork->Length); ++ psecnetwork->Ssid.SsidLength= cpu_to_le32(psecnetwork->Ssid.SsidLength); ++ psecnetwork->Privacy = cpu_to_le32(psecnetwork->Privacy); ++ psecnetwork->Rssi = cpu_to_le32(psecnetwork->Rssi); ++ psecnetwork->NetworkTypeInUse = cpu_to_le32(psecnetwork->NetworkTypeInUse); ++ psecnetwork->Configuration.ATIMWindow = cpu_to_le32(psecnetwork->Configuration.ATIMWindow); ++ psecnetwork->Configuration.BeaconPeriod = cpu_to_le32(psecnetwork->Configuration.BeaconPeriod); ++ psecnetwork->Configuration.DSConfig = cpu_to_le32(psecnetwork->Configuration.DSConfig); ++ psecnetwork->Configuration.FHConfig.DwellTime=cpu_to_le32(psecnetwork->Configuration.FHConfig.DwellTime); ++ psecnetwork->Configuration.FHConfig.HopPattern=cpu_to_le32(psecnetwork->Configuration.FHConfig.HopPattern); ++ psecnetwork->Configuration.FHConfig.HopSet=cpu_to_le32(psecnetwork->Configuration.FHConfig.HopSet); ++ psecnetwork->Configuration.FHConfig.Length=cpu_to_le32(psecnetwork->Configuration.FHConfig.Length); ++ psecnetwork->Configuration.Length = cpu_to_le32(psecnetwork->Configuration.Length); ++ psecnetwork->InfrastructureMode = cpu_to_le32(psecnetwork->InfrastructureMode); ++ psecnetwork->IELength = cpu_to_le32(psecnetwork->IELength); ++#endif ++ ++ _rtw_init_listhead(&pcmd->list); ++ pcmd->cmdcode = _JoinBss_CMD_;//GEN_CMD_CODE(_JoinBss) ++ pcmd->parmbuf = (unsigned char *)psecnetwork; ++ pcmd->rsp = NULL; ++ pcmd->rspsz = 0; ++ ++ res = rtw_enqueue_cmd(pcmdpriv, pcmd); ++ ++exit: ++ ++_func_exit_; ++ ++ return res; ++} ++ ++u8 rtw_disassoc_cmd(_adapter*padapter) // for sta_mode ++{ ++ struct cmd_obj* pdisconnect_cmd; ++ struct disconnect_parm* pdisconnect; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct cmd_priv *pcmdpriv = &padapter->cmdpriv; ++ ++ u8 res=_SUCCESS; ++ ++_func_enter_; ++ ++ RT_TRACE(_module_rtl871x_cmd_c_, _drv_notice_, ("+rtw_disassoc_cmd\n")); ++ ++ //if ((check_fwstate(pmlmepriv, _FW_LINKED)) == _TRUE) { ++ ++ pdisconnect_cmd = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj)); ++ if(pdisconnect_cmd == NULL){ ++ res=_FAIL; ++ goto exit; ++ } ++ ++ pdisconnect = (struct disconnect_parm*)rtw_zmalloc(sizeof(struct disconnect_parm)); ++ if(pdisconnect == NULL) { ++ rtw_mfree((u8 *)pdisconnect_cmd, sizeof(struct cmd_obj)); ++ res= _FAIL; ++ goto exit; ++ } ++ ++ init_h2fwcmd_w_parm_no_rsp(pdisconnect_cmd, pdisconnect, _DisConnect_CMD_); ++ res = rtw_enqueue_cmd(pcmdpriv, pdisconnect_cmd); ++ //} ++ ++exit: ++ ++_func_exit_; ++ ++ return res; ++} ++ ++u8 rtw_setopmode_cmd(_adapter *padapter, NDIS_802_11_NETWORK_INFRASTRUCTURE networktype) ++{ ++ struct cmd_obj* ph2c; ++ struct setopmode_parm* psetop; ++ ++ struct cmd_priv *pcmdpriv= &padapter->cmdpriv; ++ u8 res=_SUCCESS; ++ ++_func_enter_; ++ ++ ph2c = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj)); ++ if(ph2c==NULL){ ++ res= _FALSE; ++ goto exit; ++ } ++ psetop = (struct setopmode_parm*)rtw_zmalloc(sizeof(struct setopmode_parm)); ++ ++ if(psetop==NULL){ ++ rtw_mfree((u8 *) ph2c, sizeof(struct cmd_obj)); ++ res=_FALSE; ++ goto exit; ++ } ++ ++ init_h2fwcmd_w_parm_no_rsp(ph2c, psetop, _SetOpMode_CMD_); ++ psetop->mode = (u8)networktype; ++ ++ res = rtw_enqueue_cmd(pcmdpriv, ph2c); ++ ++exit: ++ ++_func_exit_; ++ ++ return res; ++} ++ ++u8 rtw_setstakey_cmd(_adapter *padapter, u8 *psta, u8 unicast_key) ++{ ++ struct cmd_obj* ph2c; ++ struct set_stakey_parm *psetstakey_para; ++ struct cmd_priv *pcmdpriv=&padapter->cmdpriv; ++ struct set_stakey_rsp *psetstakey_rsp = NULL; ++ ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct security_priv *psecuritypriv = &padapter->securitypriv; ++ struct sta_info* sta = (struct sta_info* )psta; ++ u8 res=_SUCCESS; ++ ++_func_enter_; ++ ++ ph2c = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj)); ++ if ( ph2c == NULL){ ++ res= _FAIL; ++ goto exit; ++ } ++ ++ psetstakey_para = (struct set_stakey_parm*)rtw_zmalloc(sizeof(struct set_stakey_parm)); ++ if(psetstakey_para==NULL){ ++ rtw_mfree((u8 *) ph2c, sizeof(struct cmd_obj)); ++ res=_FAIL; ++ goto exit; ++ } ++ ++ psetstakey_rsp = (struct set_stakey_rsp*)rtw_zmalloc(sizeof(struct set_stakey_rsp)); ++ if(psetstakey_rsp == NULL){ ++ rtw_mfree((u8 *) ph2c, sizeof(struct cmd_obj)); ++ rtw_mfree((u8 *) psetstakey_para, sizeof(struct set_stakey_parm)); ++ res=_FAIL; ++ goto exit; ++ } ++ ++ init_h2fwcmd_w_parm_no_rsp(ph2c, psetstakey_para, _SetStaKey_CMD_); ++ ph2c->rsp = (u8 *) psetstakey_rsp; ++ ph2c->rspsz = sizeof(struct set_stakey_rsp); ++ ++ _rtw_memcpy(psetstakey_para->addr, sta->hwaddr,ETH_ALEN); ++ ++ if(check_fwstate(pmlmepriv, WIFI_STATION_STATE)){ ++#ifdef CONFIG_TDLS ++ if(sta->tdls_sta_state&TDLS_LINKED_STATE) ++ psetstakey_para->algorithm=(u8)sta->dot118021XPrivacy; ++ else ++#endif ++ psetstakey_para->algorithm =(unsigned char) psecuritypriv->dot11PrivacyAlgrthm; ++ }else{ ++ GET_ENCRY_ALGO(psecuritypriv, sta, psetstakey_para->algorithm, _FALSE); ++ } ++ ++ if (unicast_key == _TRUE) { ++#ifdef CONFIG_TDLS ++ if((sta->tdls_sta_state&TDLS_LINKED_STATE)==TDLS_LINKED_STATE) ++ _rtw_memcpy(&psetstakey_para->key, sta->tpk.tk, 16); ++ else ++#endif ++ _rtw_memcpy(&psetstakey_para->key, &sta->dot118021x_UncstKey, 16); ++ } else { ++ _rtw_memcpy(&psetstakey_para->key, &psecuritypriv->dot118021XGrpKey[psecuritypriv->dot118021XGrpKeyid].skey, 16); ++ } ++ ++ //jeff: set this becasue at least sw key is ready ++ padapter->securitypriv.busetkipkey=_TRUE; ++ ++ res = rtw_enqueue_cmd(pcmdpriv, ph2c); ++ ++exit: ++ ++_func_exit_; ++ ++ return res; ++} ++ ++u8 rtw_setrttbl_cmd(_adapter *padapter, struct setratable_parm *prate_table) ++{ ++ struct cmd_obj* ph2c; ++ struct setratable_parm * psetrttblparm; ++ struct cmd_priv *pcmdpriv=&padapter->cmdpriv; ++ u8 res=_SUCCESS; ++_func_enter_; ++ ++ ph2c = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj)); ++ if(ph2c==NULL){ ++ res= _FAIL; ++ goto exit; ++ } ++ psetrttblparm = (struct setratable_parm*)rtw_zmalloc(sizeof(struct setratable_parm)); ++ ++ if(psetrttblparm==NULL){ ++ rtw_mfree((unsigned char *) ph2c, sizeof(struct cmd_obj)); ++ res= _FAIL; ++ goto exit; ++ } ++ ++ init_h2fwcmd_w_parm_no_rsp(ph2c, psetrttblparm, GEN_CMD_CODE(_SetRaTable)); ++ ++ _rtw_memcpy(psetrttblparm,prate_table,sizeof(struct setratable_parm)); ++ ++ res = rtw_enqueue_cmd(pcmdpriv, ph2c); ++exit: ++_func_exit_; ++ return res; ++ ++} ++ ++u8 rtw_getrttbl_cmd(_adapter *padapter, struct getratable_rsp *pval) ++{ ++ struct cmd_obj* ph2c; ++ struct getratable_parm * pgetrttblparm; ++ struct cmd_priv *pcmdpriv=&padapter->cmdpriv; ++ u8 res=_SUCCESS; ++_func_enter_; ++ ++ ph2c = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj)); ++ if(ph2c==NULL){ ++ res= _FAIL; ++ goto exit; ++ } ++ pgetrttblparm = (struct getratable_parm*)rtw_zmalloc(sizeof(struct getratable_parm)); ++ ++ if(pgetrttblparm==NULL){ ++ rtw_mfree((unsigned char *) ph2c, sizeof(struct cmd_obj)); ++ res= _FAIL; ++ goto exit; ++ } ++ ++// init_h2fwcmd_w_parm_no_rsp(ph2c, psetrttblparm, GEN_CMD_CODE(_SetRaTable)); ++ ++ _rtw_init_listhead(&ph2c->list); ++ ph2c->cmdcode =GEN_CMD_CODE(_GetRaTable); ++ ph2c->parmbuf = (unsigned char *)pgetrttblparm; ++ ph2c->cmdsz = sizeof(struct getratable_parm); ++ ph2c->rsp = (u8*)pval; ++ ph2c->rspsz = sizeof(struct getratable_rsp); ++ ++ pgetrttblparm ->rsvd = 0x0; ++ ++ res = rtw_enqueue_cmd(pcmdpriv, ph2c); ++exit: ++_func_exit_; ++ return res; ++ ++} ++ ++u8 rtw_setassocsta_cmd(_adapter *padapter, u8 *mac_addr) ++{ ++ struct cmd_priv *pcmdpriv = &padapter->cmdpriv; ++ struct cmd_obj* ph2c; ++ struct set_assocsta_parm *psetassocsta_para; ++ struct set_stakey_rsp *psetassocsta_rsp = NULL; ++ ++ u8 res=_SUCCESS; ++ ++_func_enter_; ++ ++ ph2c = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj)); ++ if(ph2c==NULL){ ++ res= _FAIL; ++ goto exit; ++ } ++ ++ psetassocsta_para = (struct set_assocsta_parm*)rtw_zmalloc(sizeof(struct set_assocsta_parm)); ++ if(psetassocsta_para==NULL){ ++ rtw_mfree((u8 *) ph2c, sizeof(struct cmd_obj)); ++ res=_FAIL; ++ goto exit; ++ } ++ ++ psetassocsta_rsp = (struct set_stakey_rsp*)rtw_zmalloc(sizeof(struct set_assocsta_rsp)); ++ if(psetassocsta_rsp==NULL){ ++ rtw_mfree((u8 *) ph2c, sizeof(struct cmd_obj)); ++ rtw_mfree((u8 *) psetassocsta_para, sizeof(struct set_assocsta_parm)); ++ return _FAIL; ++ } ++ ++ init_h2fwcmd_w_parm_no_rsp(ph2c, psetassocsta_para, _SetAssocSta_CMD_); ++ ph2c->rsp = (u8 *) psetassocsta_rsp; ++ ph2c->rspsz = sizeof(struct set_assocsta_rsp); ++ ++ _rtw_memcpy(psetassocsta_para->addr, mac_addr,ETH_ALEN); ++ ++ res = rtw_enqueue_cmd(pcmdpriv, ph2c); ++ ++exit: ++ ++_func_exit_; ++ ++ return res; ++ } ++ ++u8 rtw_addbareq_cmd(_adapter*padapter, u8 tid, u8 *addr) ++{ ++ struct cmd_priv *pcmdpriv = &padapter->cmdpriv; ++ struct cmd_obj* ph2c; ++ struct addBaReq_parm *paddbareq_parm; ++ ++ u8 res=_SUCCESS; ++ ++_func_enter_; ++ ++ ph2c = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj)); ++ if(ph2c==NULL){ ++ res= _FAIL; ++ goto exit; ++ } ++ ++ paddbareq_parm = (struct addBaReq_parm*)rtw_zmalloc(sizeof(struct addBaReq_parm)); ++ if(paddbareq_parm==NULL){ ++ rtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj)); ++ res= _FAIL; ++ goto exit; ++ } ++ ++ paddbareq_parm->tid = tid; ++ _rtw_memcpy(paddbareq_parm->addr, addr, ETH_ALEN); ++ ++ init_h2fwcmd_w_parm_no_rsp(ph2c, paddbareq_parm, GEN_CMD_CODE(_AddBAReq)); ++ ++ //DBG_8192C("rtw_addbareq_cmd, tid=%d\n", tid); ++ ++ //rtw_enqueue_cmd(pcmdpriv, ph2c); ++ res = rtw_enqueue_cmd(pcmdpriv, ph2c); ++ ++exit: ++ ++_func_exit_; ++ ++ return res; ++} ++ ++u8 rtw_dynamic_chk_wk_cmd(_adapter*padapter) ++{ ++ struct cmd_obj* ph2c; ++ struct drvextra_cmd_parm *pdrvextra_cmd_parm; ++ struct cmd_priv *pcmdpriv=&padapter->cmdpriv; ++ u8 res=_SUCCESS; ++ ++_func_enter_; ++ ++ ph2c = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj)); ++ if(ph2c==NULL){ ++ res= _FAIL; ++ goto exit; ++ } ++ ++ pdrvextra_cmd_parm = (struct drvextra_cmd_parm*)rtw_zmalloc(sizeof(struct drvextra_cmd_parm)); ++ if(pdrvextra_cmd_parm==NULL){ ++ rtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj)); ++ res= _FAIL; ++ goto exit; ++ } ++ ++ pdrvextra_cmd_parm->ec_id = DYNAMIC_CHK_WK_CID; ++ pdrvextra_cmd_parm->type_size = 0; ++ pdrvextra_cmd_parm->pbuf = NULL; ++ ++ init_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, GEN_CMD_CODE(_Set_Drv_Extra)); ++ ++ ++ //rtw_enqueue_cmd(pcmdpriv, ph2c); ++ res = rtw_enqueue_cmd(pcmdpriv, ph2c); ++ ++exit: ++ ++_func_exit_; ++ ++ return res; ++ ++} ++ ++u8 rtw_set_chplan_cmd(_adapter*padapter, u8 chplan, u8 enqueue) ++{ ++ struct cmd_obj* pcmdobj; ++ struct SetChannelPlan_param *setChannelPlan_param; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct cmd_priv *pcmdpriv = &padapter->cmdpriv; ++ ++ u8 res=_SUCCESS; ++ ++_func_enter_; ++ ++ RT_TRACE(_module_rtl871x_cmd_c_, _drv_notice_, ("+rtw_set_chplan_cmd\n")); ++ ++ //check input parameter ++ if(!rtw_is_channel_plan_valid(chplan)) { ++ res = _FAIL; ++ goto exit; ++ } ++ ++ //prepare cmd parameter ++ setChannelPlan_param = (struct SetChannelPlan_param *)rtw_zmalloc(sizeof(struct SetChannelPlan_param)); ++ if(setChannelPlan_param == NULL) { ++ res= _FAIL; ++ goto exit; ++ } ++ setChannelPlan_param->channel_plan=chplan; ++ ++ if(enqueue) ++ { ++ //need enqueue, prepare cmd_obj and enqueue ++ pcmdobj = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj)); ++ if(pcmdobj == NULL){ ++ rtw_mfree((u8 *)setChannelPlan_param, sizeof(struct SetChannelPlan_param)); ++ res=_FAIL; ++ goto exit; ++ } ++ ++ init_h2fwcmd_w_parm_no_rsp(pcmdobj, setChannelPlan_param, GEN_CMD_CODE(_SetChannelPlan)); ++ res = rtw_enqueue_cmd(pcmdpriv, pcmdobj); ++ } ++ else ++ { ++ //no need to enqueue, do the cmd hdl directly and free cmd parameter ++ if( H2C_SUCCESS !=set_chplan_hdl(padapter, (unsigned char *)setChannelPlan_param) ) ++ res = _FAIL; ++ ++ rtw_mfree((u8 *)setChannelPlan_param, sizeof(struct SetChannelPlan_param)); ++ } ++ ++ //do something based on res... ++ if(res == _SUCCESS) ++ padapter->mlmepriv.ChannelPlan = chplan; ++ ++exit: ++ ++_func_exit_; ++ ++ return res; ++} ++ ++u8 rtw_led_blink_cmd(_adapter*padapter, PLED_871x pLed) ++{ ++ struct cmd_obj* pcmdobj; ++ struct LedBlink_param *ledBlink_param; ++ struct cmd_priv *pcmdpriv = &padapter->cmdpriv; ++ ++ u8 res=_SUCCESS; ++ ++_func_enter_; ++ ++ RT_TRACE(_module_rtl871x_cmd_c_, _drv_notice_, ("+rtw_led_blink_cmd\n")); ++ ++ pcmdobj = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj)); ++ if(pcmdobj == NULL){ ++ res=_FAIL; ++ goto exit; ++ } ++ ++ ledBlink_param = (struct LedBlink_param *)rtw_zmalloc(sizeof(struct LedBlink_param)); ++ if(ledBlink_param == NULL) { ++ rtw_mfree((u8 *)pcmdobj, sizeof(struct cmd_obj)); ++ res= _FAIL; ++ goto exit; ++ } ++ ++ ledBlink_param->pLed=pLed; ++ ++ init_h2fwcmd_w_parm_no_rsp(pcmdobj, ledBlink_param, GEN_CMD_CODE(_LedBlink)); ++ res = rtw_enqueue_cmd(pcmdpriv, pcmdobj); ++ ++exit: ++ ++_func_exit_; ++ ++ return res; ++} ++ ++u8 rtw_set_csa_cmd(_adapter*padapter, u8 new_ch_no) ++{ ++ struct cmd_obj* pcmdobj; ++ struct SetChannelSwitch_param*setChannelSwitch_param; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct cmd_priv *pcmdpriv = &padapter->cmdpriv; ++ ++ u8 res=_SUCCESS; ++ ++_func_enter_; ++ ++ RT_TRACE(_module_rtl871x_cmd_c_, _drv_notice_, ("+rtw_set_csa_cmd\n")); ++ ++ pcmdobj = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj)); ++ if(pcmdobj == NULL){ ++ res=_FAIL; ++ goto exit; ++ } ++ ++ setChannelSwitch_param = (struct SetChannelSwitch_param *)rtw_zmalloc(sizeof(struct SetChannelSwitch_param)); ++ if(setChannelSwitch_param == NULL) { ++ rtw_mfree((u8 *)pcmdobj, sizeof(struct cmd_obj)); ++ res= _FAIL; ++ goto exit; ++ } ++ ++ setChannelSwitch_param->new_ch_no=new_ch_no; ++ ++ init_h2fwcmd_w_parm_no_rsp(pcmdobj, setChannelSwitch_param, GEN_CMD_CODE(_SetChannelSwitch)); ++ res = rtw_enqueue_cmd(pcmdpriv, pcmdobj); ++ ++exit: ++ ++_func_exit_; ++ ++ return res; ++} ++ ++u8 rtw_tdls_cmd(_adapter *padapter, u8 *addr, u8 option) ++{ ++ struct cmd_obj* pcmdobj; ++ struct TDLSoption_param *TDLSoption; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct cmd_priv *pcmdpriv = &padapter->cmdpriv; ++ ++ u8 res=_SUCCESS; ++ ++_func_enter_; ++ ++#ifdef CONFIG_TDLS ++ ++ RT_TRACE(_module_rtl871x_cmd_c_, _drv_notice_, ("+rtw_set_tdls_cmd\n")); ++ ++ pcmdobj = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj)); ++ if(pcmdobj == NULL){ ++ res=_FAIL; ++ goto exit; ++ } ++ ++ TDLSoption= (struct TDLSoption_param *)rtw_zmalloc(sizeof(struct TDLSoption_param)); ++ if(TDLSoption == NULL) { ++ rtw_mfree((u8 *)pcmdobj, sizeof(struct cmd_obj)); ++ res= _FAIL; ++ goto exit; ++ } ++ ++ _rtw_spinlock(&(padapter->tdlsinfo.cmd_lock)); ++ _rtw_memcpy(TDLSoption->addr, addr, 6); ++ TDLSoption->option = option; ++ _rtw_spinunlock(&(padapter->tdlsinfo.cmd_lock)); ++ init_h2fwcmd_w_parm_no_rsp(pcmdobj, TDLSoption, GEN_CMD_CODE(_TDLS)); ++ res = rtw_enqueue_cmd(pcmdpriv, pcmdobj); ++ ++#endif //CONFIG_TDLS ++ ++exit: ++ ++ ++_func_exit_; ++ ++ return res; ++} ++ ++static void traffic_status_watchdog(_adapter *padapter) ++{ ++#ifdef CONFIG_LPS ++ u8 bEnterPS; ++ u32 trx_threshold; ++ u32 rx_threshold; ++#endif ++ u8 bBusyTraffic = _FALSE, bTxBusyTraffic = _FALSE, bRxBusyTraffic = _FALSE; ++ u8 bHigherBusyTraffic = _FALSE, bHigherBusyRxTraffic = _FALSE, bHigherBusyTxTraffic = _FALSE; ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++#ifdef CONFIG_TDLS ++ struct tdls_info *ptdlsinfo = &(padapter->tdlsinfo); ++#endif //CONFIG_TDLS ++ ++ // ++ // Determine if our traffic is busy now ++ // ++ if((check_fwstate(pmlmepriv, _FW_LINKED)== _TRUE) ++ /*&& !MgntInitAdapterInProgress(pMgntInfo)*/) ++ { ++ ++ if( pmlmepriv->LinkDetectInfo.NumRxOkInPeriod > 100 || ++ pmlmepriv->LinkDetectInfo.NumTxOkInPeriod > 100 ) ++ { ++ bBusyTraffic = _TRUE; ++ ++ if(pmlmepriv->LinkDetectInfo.NumRxOkInPeriod > 100) ++ bRxBusyTraffic = _TRUE; ++ ++ if(pmlmepriv->LinkDetectInfo.NumTxOkInPeriod > 100) ++ bTxBusyTraffic = _TRUE; ++ } ++ ++ // Higher Tx/Rx data. ++ if( pmlmepriv->LinkDetectInfo.NumRxOkInPeriod > 4000 || ++ pmlmepriv->LinkDetectInfo.NumTxOkInPeriod > 4000 ) ++ { ++ bHigherBusyTraffic = _TRUE; ++ ++ // Extremely high Rx data. ++ if(pmlmepriv->LinkDetectInfo.NumRxOkInPeriod > 5000) ++ bHigherBusyRxTraffic = _TRUE; ++ ++ // Extremely high Tx data. ++ if(pmlmepriv->LinkDetectInfo.NumTxOkInPeriod > 5000) ++ bHigherBusyTxTraffic = _TRUE; ++ } ++ ++#ifdef CONFIG_TDLS ++#ifdef CONFIG_TDLS_AUTOSETUP ++ if( ( ptdlsinfo->watchdog_count % TDLS_WATCHDOG_PERIOD ) == 0 ) //10 * 2sec, periodically sending ++ issue_tdls_dis_req( padapter, NULL ); ++ ptdlsinfo->watchdog_count++; ++#endif //CONFIG_TDLS_AUTOSETUP ++#endif //CONFIG_TDLS ++ ++#ifdef CONFIG_LPS ++ // check traffic for powersaving. ++ if(padapter->registrypriv.intel_class_mode==1){ ++ trx_threshold=1; ++ rx_threshold=1; ++ } ++ else{ ++ trx_threshold=8; ++ rx_threshold=2; ++ } ++ if( ((pmlmepriv->LinkDetectInfo.NumRxUnicastOkInPeriod + pmlmepriv->LinkDetectInfo.NumTxOkInPeriod) > trx_threshold ) || ++ (pmlmepriv->LinkDetectInfo.NumRxUnicastOkInPeriod > rx_threshold) ) ++ { ++ //DBG_8192C("Tx = %d, Rx = %d \n",pmlmepriv->LinkDetectInfo.NumTxOkInPeriod,pmlmepriv->LinkDetectInfo.NumRxUnicastOkInPeriod); ++ bEnterPS= _FALSE; ++ } ++ else ++ { ++ bEnterPS= _TRUE; ++ } ++ ++ // LeisurePS only work in infra mode. ++ if(bEnterPS) ++ { ++ LPS_Enter(padapter); ++ } ++ else ++ { ++ LPS_Leave(padapter); ++ } ++#endif ++ } ++ else ++ { ++#ifdef CONFIG_LPS ++ LPS_Leave(padapter); ++#endif ++ } ++ ++ pmlmepriv->LinkDetectInfo.NumRxOkInPeriod = 0; ++ pmlmepriv->LinkDetectInfo.NumTxOkInPeriod = 0; ++ pmlmepriv->LinkDetectInfo.NumRxUnicastOkInPeriod = 0; ++ pmlmepriv->LinkDetectInfo.bBusyTraffic = bBusyTraffic; ++ pmlmepriv->LinkDetectInfo.bTxBusyTraffic = bTxBusyTraffic; ++ pmlmepriv->LinkDetectInfo.bRxBusyTraffic = bRxBusyTraffic; ++ pmlmepriv->LinkDetectInfo.bHigherBusyTraffic = bHigherBusyTraffic; ++ pmlmepriv->LinkDetectInfo.bHigherBusyRxTraffic = bHigherBusyRxTraffic; ++} ++ ++void dynamic_chk_wk_hdl(_adapter *padapter, u8 *pbuf, int sz) ++{ ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ //struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ #ifdef DBG_CONFIG_ERROR_DETECT ++ if(padapter->HalFunc.sreset_xmit_status_check) ++ padapter->HalFunc.sreset_xmit_status_check(padapter); ++ #endif ++ ++ //if(check_fwstate(pmlmepriv, _FW_UNDER_LINKING|_FW_UNDER_SURVEY)==_FALSE) ++ { ++ linked_status_chk(padapter); ++ traffic_status_watchdog(padapter); ++ } ++ ++ padapter->HalFunc.hal_dm_watchdog(padapter); ++ ++ //check_hw_pbc(padapter, pdrvextra_cmd->pbuf, pdrvextra_cmd->type_size); ++ ++} ++ ++#ifdef CONFIG_LPS ++void lps_ctrl_wk_hdl(_adapter *padapter, u8 lps_ctrl_type) ++{ ++ struct pwrctrl_priv *pwrpriv = &padapter->pwrctrlpriv; ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ u8 mstatus; ++ ++_func_enter_; ++ ++ if((check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE) ++ || (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE)) ++ { ++ return; ++ } ++ ++ switch(lps_ctrl_type) ++ { ++ case LPS_CTRL_SCAN: ++ //DBG_8192C("LPS_CTRL_SCAN \n"); ++ LeaveAllPowerSaveMode(padapter); ++ break; ++ case LPS_CTRL_JOINBSS: ++ //DBG_8192C("LPS_CTRL_JOINBSS \n"); ++ LPS_Leave(padapter); ++ break; ++ case LPS_CTRL_CONNECT: ++ //DBG_8192C("LPS_CTRL_CONNECT \n"); ++ mstatus = 1; ++ // Reset LPS Setting ++ padapter->pwrctrlpriv.LpsIdleCount = 0; ++ padapter->HalFunc.SetHwRegHandler(padapter, HW_VAR_H2C_FW_JOINBSSRPT, (u8 *)(&mstatus)); ++ break; ++ case LPS_CTRL_DISCONNECT: ++ //DBG_8192C("LPS_CTRL_DISCONNECT \n"); ++ mstatus = 0; ++ LPS_Leave(padapter); ++ padapter->HalFunc.SetHwRegHandler(padapter, HW_VAR_H2C_FW_JOINBSSRPT, (u8 *)(&mstatus)); ++ break; ++ case LPS_CTRL_SPECIAL_PACKET: ++ //DBG_8192C("LPS_CTRL_SPECIAL_PACKET \n"); ++ pwrpriv->DelayLPSLastTimeStamp = rtw_get_current_time(); ++ LPS_Leave(padapter); ++ break; ++ ++ default: ++ break; ++ } ++ ++_func_exit_; ++} ++ ++u8 rtw_lps_ctrl_wk_cmd(_adapter*padapter, u8 lps_ctrl_type, u8 enqueue) ++{ ++ struct cmd_obj *ph2c; ++ struct drvextra_cmd_parm *pdrvextra_cmd_parm; ++ struct cmd_priv *pcmdpriv = &padapter->cmdpriv; ++ struct pwrctrl_priv *pwrctrlpriv = &padapter->pwrctrlpriv; ++ u8 res = _SUCCESS; ++ ++_func_enter_; ++ ++ //if(!pwrctrlpriv->bLeisurePs) ++ // return res; ++ ++ if(enqueue) ++ { ++ ph2c = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj)); ++ if(ph2c==NULL){ ++ res= _FAIL; ++ goto exit; ++ } ++ ++ pdrvextra_cmd_parm = (struct drvextra_cmd_parm*)rtw_zmalloc(sizeof(struct drvextra_cmd_parm)); ++ if(pdrvextra_cmd_parm==NULL){ ++ rtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj)); ++ res= _FAIL; ++ goto exit; ++ } ++ ++ pdrvextra_cmd_parm->ec_id = LPS_CTRL_WK_CID; ++ pdrvextra_cmd_parm->type_size = lps_ctrl_type; ++ pdrvextra_cmd_parm->pbuf = NULL; ++ ++ init_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, GEN_CMD_CODE(_Set_Drv_Extra)); ++ ++ res = rtw_enqueue_cmd(pcmdpriv, ph2c); ++ } ++ else ++ { ++ lps_ctrl_wk_hdl(padapter, lps_ctrl_type); ++ } ++ ++exit: ++ ++_func_exit_; ++ ++ return res; ++ ++} ++ ++#endif ++#ifdef CONFIG_ANTENNA_DIVERSITY ++ ++void antenna_select_wk_hdl(_adapter *padapter, u8 antenna) ++{ ++ padapter->HalFunc.SetHwRegHandler(padapter, HW_VAR_ANTENNA_DIVERSITY_SELECT, (u8 *)(&antenna)); ++} ++ ++u8 rtw_antenna_select_cmd(_adapter*padapter, u8 antenna,u8 enqueue) ++{ ++ struct cmd_obj *ph2c; ++ struct drvextra_cmd_parm *pdrvextra_cmd_parm; ++ struct cmd_priv *pcmdpriv = &padapter->cmdpriv; ++ u8 bSupportAntDiv = _FALSE; ++ u8 res = _SUCCESS; ++ ++_func_enter_; ++ padapter->HalFunc.GetHalDefVarHandler(padapter, HAL_DEF_IS_SUPPORT_ANT_DIV, &(bSupportAntDiv)); ++ if(_FALSE == bSupportAntDiv ) return res; ++ ++ if(_TRUE == enqueue) ++ { ++ ph2c = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj)); ++ if(ph2c==NULL){ ++ res= _FAIL; ++ goto exit; ++ } ++ ++ pdrvextra_cmd_parm = (struct drvextra_cmd_parm*)rtw_zmalloc(sizeof(struct drvextra_cmd_parm)); ++ if(pdrvextra_cmd_parm==NULL){ ++ rtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj)); ++ res= _FAIL; ++ goto exit; ++ } ++ ++ pdrvextra_cmd_parm->ec_id = ANT_SELECT_WK_CID; ++ pdrvextra_cmd_parm->type_size = antenna; ++ pdrvextra_cmd_parm->pbuf = NULL; ++ init_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, GEN_CMD_CODE(_Set_Drv_Extra)); ++ ++ res = rtw_enqueue_cmd(pcmdpriv, ph2c); ++ } ++ else{ ++ antenna_select_wk_hdl(padapter,antenna ); ++ } ++exit: ++ ++_func_exit_; ++ ++ return res; ++ ++} ++#endif ++ ++void power_saving_wk_hdl(_adapter *padapter, u8 *pbuf, int sz) ++{ ++ rtw_ps_processor(padapter); ++} ++ ++#ifdef CONFIG_P2P ++u8 p2p_protocol_wk_cmd(_adapter*padapter, int intCmdType ) ++{ ++ struct cmd_obj *ph2c; ++ struct drvextra_cmd_parm *pdrvextra_cmd_parm; ++ struct wifidirect_info *pwdinfo= &(padapter->wdinfo); ++ struct cmd_priv *pcmdpriv = &padapter->cmdpriv; ++ u8 res = _SUCCESS; ++ ++_func_enter_; ++ ++ if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) ++ { ++ return res; ++ } ++ ++ ph2c = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj)); ++ if(ph2c==NULL){ ++ res= _FAIL; ++ goto exit; ++ } ++ ++ pdrvextra_cmd_parm = (struct drvextra_cmd_parm*)rtw_zmalloc(sizeof(struct drvextra_cmd_parm)); ++ if(pdrvextra_cmd_parm==NULL){ ++ rtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj)); ++ res= _FAIL; ++ goto exit; ++ } ++ ++ pdrvextra_cmd_parm->ec_id = P2P_PROTO_WK_CID; ++ pdrvextra_cmd_parm->type_size = intCmdType; // As the command tppe. ++ pdrvextra_cmd_parm->pbuf = NULL; // Must be NULL here ++ ++ init_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, GEN_CMD_CODE(_Set_Drv_Extra)); ++ ++ res = rtw_enqueue_cmd(pcmdpriv, ph2c); ++ ++exit: ++ ++_func_exit_; ++ ++ return res; ++ ++} ++#endif //CONFIG_P2P ++ ++u8 rtw_ps_cmd(_adapter*padapter) ++{ ++ struct cmd_obj *ppscmd; ++ struct drvextra_cmd_parm *pdrvextra_cmd_parm; ++ struct cmd_priv *pcmdpriv = &padapter->cmdpriv; ++ ++ u8 res = _SUCCESS; ++_func_enter_; ++ ++ ppscmd = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj)); ++ if(ppscmd==NULL){ ++ res= _FAIL; ++ goto exit; ++ } ++ ++ pdrvextra_cmd_parm = (struct drvextra_cmd_parm*)rtw_zmalloc(sizeof(struct drvextra_cmd_parm)); ++ if(pdrvextra_cmd_parm==NULL){ ++ rtw_mfree((unsigned char *)ppscmd, sizeof(struct cmd_obj)); ++ res= _FAIL; ++ goto exit; ++ } ++ ++ pdrvextra_cmd_parm->ec_id = POWER_SAVING_CTRL_WK_CID; ++ pdrvextra_cmd_parm->pbuf = NULL; ++ DBG_8192C("==> %s , enqueue CMD \n",__FUNCTION__); ++ init_h2fwcmd_w_parm_no_rsp(ppscmd, pdrvextra_cmd_parm, GEN_CMD_CODE(_Set_Drv_Extra)); ++ ++ res = rtw_enqueue_cmd(pcmdpriv, ppscmd); ++ ++exit: ++ ++_func_exit_; ++ ++ return res; ++ ++} ++ ++#ifdef CONFIG_AP_MODE ++ ++static void rtw_chk_hi_queue_hdl(_adapter *padapter) ++{ ++ int cnt=0; ++ struct sta_info *psta_bmc; ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ ++ psta_bmc = rtw_get_bcmc_stainfo(padapter); ++ if(!psta_bmc) ++ return; ++ ++ ++ if(psta_bmc->sleepq_len==0) ++ { ++ while((rtw_read32(padapter, 0x414)&0x00ffff00)!=0) ++ { ++ rtw_msleep_os(100); ++ ++ cnt++; ++ ++ if(cnt>10) ++ break; ++ } ++ ++ if(cnt<=10) ++ { ++ pstapriv->tim_bitmap &= ~BIT(0); ++ pstapriv->sta_dz_bitmap &= ~BIT(0); ++ ++ update_beacon(padapter, _TIM_IE_, NULL, _FALSE); ++ } ++ } ++ ++} ++ ++u8 rtw_chk_hi_queue_cmd(_adapter*padapter) ++{ ++ struct cmd_obj *ph2c; ++ struct drvextra_cmd_parm *pdrvextra_cmd_parm; ++ struct cmd_priv *pcmdpriv = &padapter->cmdpriv; ++ u8 res = _SUCCESS; ++ ++ ph2c = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj)); ++ if(ph2c==NULL){ ++ res= _FAIL; ++ goto exit; ++ } ++ ++ pdrvextra_cmd_parm = (struct drvextra_cmd_parm*)rtw_zmalloc(sizeof(struct drvextra_cmd_parm)); ++ if(pdrvextra_cmd_parm==NULL){ ++ rtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj)); ++ res= _FAIL; ++ goto exit; ++ } ++ ++ pdrvextra_cmd_parm->ec_id = CHECK_HIQ_WK_CID; ++ pdrvextra_cmd_parm->type_size = 0; ++ pdrvextra_cmd_parm->pbuf = NULL; ++ ++ init_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, GEN_CMD_CODE(_Set_Drv_Extra)); ++ ++ res = rtw_enqueue_cmd(pcmdpriv, ph2c); ++ ++exit: ++ ++ return res; ++ ++} ++#endif ++ ++u8 rtw_drvextra_cmd_hdl(_adapter *padapter, unsigned char *pbuf) ++{ ++ struct drvextra_cmd_parm *pdrvextra_cmd; ++ ++ if(!pbuf) ++ return H2C_PARAMETERS_ERROR; ++ ++ pdrvextra_cmd = (struct drvextra_cmd_parm*)pbuf; ++ ++ switch(pdrvextra_cmd->ec_id) ++ { ++ case DYNAMIC_CHK_WK_CID: ++ dynamic_chk_wk_hdl(padapter, pdrvextra_cmd->pbuf, pdrvextra_cmd->type_size); ++ break; ++ case POWER_SAVING_CTRL_WK_CID: ++ power_saving_wk_hdl(padapter, pdrvextra_cmd->pbuf, pdrvextra_cmd->type_size); ++ break; ++#ifdef CONFIG_LPS ++ case LPS_CTRL_WK_CID: ++ lps_ctrl_wk_hdl(padapter, (u8)pdrvextra_cmd->type_size); ++ break; ++#endif ++#ifdef CONFIG_ANTENNA_DIVERSITY ++ case ANT_SELECT_WK_CID: ++ antenna_select_wk_hdl(padapter, pdrvextra_cmd->type_size); ++ break; ++#endif ++#ifdef CONFIG_P2P ++ case P2P_PS_WK_CID: ++ p2p_ps_wk_hdl(padapter, pdrvextra_cmd->type_size); ++ break; ++ case P2P_PROTO_WK_CID: ++ // Commented by Albert 2011/07/01 ++ // I used the type_size as the type command ++ p2p_protocol_wk_hdl( padapter, pdrvextra_cmd->type_size ); ++ break; ++#endif //CONFIG_P2P ++#ifdef CONFIG_AP_MODE ++ case CHECK_HIQ_WK_CID: ++ rtw_chk_hi_queue_hdl(padapter); ++ break; ++#endif //CONFIG_AP_MODE ++ default: ++ break; ++ ++ } ++ ++ ++ if(pdrvextra_cmd->pbuf && pdrvextra_cmd->type_size>0) ++ { ++ rtw_mfree(pdrvextra_cmd->pbuf, pdrvextra_cmd->type_size); ++ } ++ ++ ++ return H2C_SUCCESS; ++ ++} ++ ++void rtw_survey_cmd_callback(_adapter* padapter , struct cmd_obj *pcmd) ++{ ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ ++_func_enter_; ++ ++ if(pcmd->res == H2C_DROPPED) ++ { ++ //TODO: cancel timer and do timeout handler directly... ++ //need to make timeout handlerOS independent ++ _set_timer(&pmlmepriv->scan_to_timer, 1); ++ } ++ else if (pcmd->res != H2C_SUCCESS) { ++ _set_timer(&pmlmepriv->scan_to_timer, 1); ++ RT_TRACE(_module_rtl871x_cmd_c_,_drv_err_,("\n ********Error: MgntActrtw_set_802_11_bssid_LIST_SCAN Fail ************\n\n.")); ++ } ++ ++ // free cmd ++ rtw_free_cmd_obj(pcmd); ++ ++_func_exit_; ++} ++void rtw_disassoc_cmd_callback(_adapter* padapter, struct cmd_obj *pcmd) ++{ ++ _irqL irqL; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ ++_func_enter_; ++ ++ if (pcmd->res != H2C_SUCCESS) ++ { ++ _enter_critical_bh(&pmlmepriv->lock, &irqL); ++ set_fwstate(pmlmepriv, _FW_LINKED); ++ _exit_critical_bh(&pmlmepriv->lock, &irqL); ++ ++ RT_TRACE(_module_rtl871x_cmd_c_,_drv_err_,("\n ***Error: disconnect_cmd_callback Fail ***\n.")); ++ ++ goto exit; ++ } ++#ifdef CONFIG_BR_EXT ++ else //clear bridge database ++ nat25_db_cleanup(padapter); ++#endif //CONFIG_BR_EXT ++ ++ // free cmd ++ rtw_free_cmd_obj(pcmd); ++ ++exit: ++ ++_func_exit_; ++} ++ ++ ++void rtw_joinbss_cmd_callback(_adapter* padapter, struct cmd_obj *pcmd) ++{ ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ ++_func_enter_; ++ ++ if(pcmd->res == H2C_DROPPED) ++ { ++ //TODO: cancel timer and do timeout handler directly... ++ //need to make timeout handlerOS independent ++ _set_timer(&pmlmepriv->assoc_timer, 1); ++ } ++ else if(pcmd->res != H2C_SUCCESS) ++ { ++ RT_TRACE(_module_rtl871x_cmd_c_,_drv_err_,("********Error:rtw_select_and_join_from_scanned_queue Wait Sema Fail ************\n")); ++ _set_timer(&pmlmepriv->assoc_timer, 1); ++ } ++ ++ rtw_free_cmd_obj(pcmd); ++ ++_func_exit_; ++} ++ ++void rtw_createbss_cmd_callback(_adapter *padapter, struct cmd_obj *pcmd) ++{ ++ _irqL irqL; ++ u8 timer_cancelled; ++ struct sta_info *psta = NULL; ++ struct wlan_network *pwlan = NULL; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ WLAN_BSSID_EX *pnetwork = (WLAN_BSSID_EX *)pcmd->parmbuf; ++ struct wlan_network *tgt_network = &(pmlmepriv->cur_network); ++ ++_func_enter_; ++ ++ if((pcmd->res != H2C_SUCCESS)) ++ { ++ RT_TRACE(_module_rtl871x_cmd_c_,_drv_err_,("\n ********Error: rtw_createbss_cmd_callback Fail ************\n\n.")); ++ _set_timer(&pmlmepriv->assoc_timer, 1 ); ++ } ++ ++ _cancel_timer(&pmlmepriv->assoc_timer, &timer_cancelled); ++ ++ //endian_convert ++ pnetwork->Length = le32_to_cpu(pnetwork->Length); ++ pnetwork->Ssid.SsidLength = le32_to_cpu(pnetwork->Ssid.SsidLength); ++ pnetwork->Privacy =le32_to_cpu(pnetwork->Privacy); ++ pnetwork->Rssi = le32_to_cpu(pnetwork->Rssi); ++ pnetwork->NetworkTypeInUse =le32_to_cpu(pnetwork->NetworkTypeInUse); ++ pnetwork->Configuration.ATIMWindow = le32_to_cpu(pnetwork->Configuration.ATIMWindow); ++ //pnetwork->Configuration.BeaconPeriod = le32_to_cpu(pnetwork->Configuration.BeaconPeriod); ++ pnetwork->Configuration.DSConfig =le32_to_cpu(pnetwork->Configuration.DSConfig); ++ pnetwork->Configuration.FHConfig.DwellTime=le32_to_cpu(pnetwork->Configuration.FHConfig.DwellTime); ++ pnetwork->Configuration.FHConfig.HopPattern=le32_to_cpu(pnetwork->Configuration.FHConfig.HopPattern); ++ pnetwork->Configuration.FHConfig.HopSet=le32_to_cpu(pnetwork->Configuration.FHConfig.HopSet); ++ pnetwork->Configuration.FHConfig.Length=le32_to_cpu(pnetwork->Configuration.FHConfig.Length); ++ pnetwork->Configuration.Length = le32_to_cpu(pnetwork->Configuration.Length); ++ pnetwork->InfrastructureMode = le32_to_cpu(pnetwork->InfrastructureMode); ++ pnetwork->IELength = le32_to_cpu(pnetwork->IELength); ++ ++ ++ _enter_critical_bh(&pmlmepriv->lock, &irqL); ++ ++ ++ if(check_fwstate(pmlmepriv, WIFI_AP_STATE) ) ++ { ++ psta = rtw_get_stainfo(&padapter->stapriv, pnetwork->MacAddress); ++ if(!psta) ++ { ++ psta = rtw_alloc_stainfo(&padapter->stapriv, pnetwork->MacAddress); ++ if (psta == NULL) ++ { ++ RT_TRACE(_module_rtl871x_cmd_c_,_drv_err_,("\nCan't alloc sta_info when createbss_cmd_callback\n")); ++ goto createbss_cmd_fail ; ++ } ++ } ++ ++ rtw_indicate_connect( padapter); ++ } ++ else ++ { ++ _irqL irqL; ++ ++ pwlan = _rtw_alloc_network(pmlmepriv); ++ _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); ++ if ( pwlan == NULL) ++ { ++ pwlan = rtw_get_oldest_wlan_network(&pmlmepriv->scanned_queue); ++ if( pwlan == NULL) ++ { ++ RT_TRACE(_module_rtl871x_cmd_c_,_drv_err_,("\n Error: can't get pwlan in rtw_joinbss_event_callback \n")); ++ _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); ++ goto createbss_cmd_fail; ++ } ++ pwlan->last_scanned = rtw_get_current_time(); ++ } ++ else ++ { ++ rtw_list_insert_tail(&(pwlan->list), &pmlmepriv->scanned_queue.queue); ++ } ++ ++ pnetwork->Length = get_WLAN_BSSID_EX_sz(pnetwork); ++ _rtw_memcpy(&(pwlan->network), pnetwork, pnetwork->Length); ++ //pwlan->fixed = _TRUE; ++ ++ //rtw_list_insert_tail(&(pwlan->list), &pmlmepriv->scanned_queue.queue); ++ ++ // copy pdev_network information to pmlmepriv->cur_network ++ _rtw_memcpy(&tgt_network->network, pnetwork, (get_WLAN_BSSID_EX_sz(pnetwork))); ++ ++ // reset DSConfig ++ //tgt_network->network.Configuration.DSConfig = (u32)rtw_ch2freq(pnetwork->Configuration.DSConfig); ++ ++ _clr_fwstate_(pmlmepriv, _FW_UNDER_LINKING); ++ ++#if 0 ++ if((pmlmepriv->fw_state) & WIFI_AP_STATE) ++ { ++ psta = rtw_alloc_stainfo(&padapter->stapriv, pnetwork->MacAddress); ++ ++ if (psta == NULL) { // for AP Mode & Adhoc Master Mode ++ RT_TRACE(_module_rtl871x_cmd_c_,_drv_err_,("\nCan't alloc sta_info when createbss_cmd_callback\n")); ++ goto createbss_cmd_fail ; ++ } ++ ++ rtw_indicate_connect( padapter); ++ } ++ else { ++ ++ //rtw_indicate_disconnect(dev); ++ } ++#endif ++ _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); ++ // we will set _FW_LINKED when there is one more sat to join us (rtw_stassoc_event_callback) ++ ++ } ++ ++createbss_cmd_fail: ++ ++ _exit_critical_bh(&pmlmepriv->lock, &irqL); ++ ++ rtw_free_cmd_obj(pcmd); ++ ++_func_exit_; ++ ++} ++ ++ ++ ++void rtw_setstaKey_cmdrsp_callback(_adapter* padapter , struct cmd_obj *pcmd) ++{ ++ ++ struct sta_priv * pstapriv = &padapter->stapriv; ++ struct set_stakey_rsp* psetstakey_rsp = (struct set_stakey_rsp*) (pcmd->rsp); ++ struct sta_info* psta = rtw_get_stainfo(pstapriv, psetstakey_rsp->addr); ++ ++_func_enter_; ++ ++ if(psta==NULL) ++ { ++ RT_TRACE(_module_rtl871x_cmd_c_,_drv_err_,("\nERROR: rtw_setstaKey_cmdrsp_callback => can't get sta_info \n\n")); ++ goto exit; ++ } ++ ++ //psta->aid = psta->mac_id = psetstakey_rsp->keyid; //CAM_ID(CAM_ENTRY) ++ ++exit: ++ ++ rtw_free_cmd_obj(pcmd); ++ ++_func_exit_; ++ ++} ++void rtw_setassocsta_cmdrsp_callback(_adapter* padapter, struct cmd_obj *pcmd) ++{ ++ _irqL irqL; ++ struct sta_priv * pstapriv = &padapter->stapriv; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct set_assocsta_parm* passocsta_parm = (struct set_assocsta_parm*)(pcmd->parmbuf); ++ struct set_assocsta_rsp* passocsta_rsp = (struct set_assocsta_rsp*) (pcmd->rsp); ++ struct sta_info* psta = rtw_get_stainfo(pstapriv, passocsta_parm->addr); ++ ++_func_enter_; ++ ++ if(psta==NULL) ++ { ++ RT_TRACE(_module_rtl871x_cmd_c_,_drv_err_,("\nERROR: setassocsta_cmdrsp_callbac => can't get sta_info \n\n")); ++ goto exit; ++ } ++ ++ psta->aid = psta->mac_id = passocsta_rsp->cam_id; ++ ++ _enter_critical_bh(&pmlmepriv->lock, &irqL); ++ ++ if ((check_fwstate(pmlmepriv, WIFI_MP_STATE) == _TRUE) && (check_fwstate(pmlmepriv, _FW_UNDER_LINKING) == _TRUE)) ++ _clr_fwstate_(pmlmepriv, _FW_UNDER_LINKING); ++ ++ set_fwstate(pmlmepriv, _FW_LINKED); ++ _exit_critical_bh(&pmlmepriv->lock, &irqL); ++ ++exit: ++ rtw_free_cmd_obj(pcmd); ++ ++_func_exit_; ++} ++ ++void rtw_getrttbl_cmd_cmdrsp_callback(_adapter* padapter, struct cmd_obj *pcmd) ++{ ++_func_enter_; ++ ++ rtw_free_cmd_obj(pcmd); ++#ifdef CONFIG_MP_INCLUDED ++ padapter->mppriv.workparam.bcompleted=_TRUE; ++#endif ++ ++_func_exit_; ++ ++} ++ +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/core/rtw_debug.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/core/rtw_debug.c 2013-07-26 19:36:04.000000000 +0000 +@@ -0,0 +1,662 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#define _RTW_DEBUG_C_ ++ ++ ++#include ++ ++#ifdef CONFIG_DEBUG_RTL871X ++ ++ u32 GlobalDebugLevel = _drv_info_; ++ ++ u64 GlobalDebugComponents = \ ++ _module_rtl871x_xmit_c_ | ++ _module_xmit_osdep_c_ | ++ _module_rtl871x_recv_c_ | ++ _module_recv_osdep_c_ | ++ _module_rtl871x_mlme_c_ | ++ _module_mlme_osdep_c_ | ++ _module_rtl871x_sta_mgt_c_ | ++ _module_rtl871x_cmd_c_ | ++ _module_cmd_osdep_c_ | ++ _module_rtl871x_io_c_ | ++ _module_io_osdep_c_ | ++ _module_os_intfs_c_| ++ _module_rtl871x_security_c_| ++ _module_rtl871x_eeprom_c_| ++ _module_hal_init_c_| ++ _module_hci_hal_init_c_| ++ _module_rtl871x_ioctl_c_| ++ _module_rtl871x_ioctl_set_c_| ++ _module_rtl871x_ioctl_query_c_| ++ _module_rtl871x_pwrctrl_c_| ++ _module_hci_intfs_c_| ++ _module_hci_ops_c_| ++ _module_hci_ops_os_c_| ++ _module_rtl871x_ioctl_os_c| ++ _module_rtl8712_cmd_c_| ++ _module_rtl8192c_xmit_c_| ++ _module_rtl8712_recv_c_ | ++ _module_mp_ | ++ _module_efuse_; ++ ++#endif ++ ++#ifdef CONFIG_PROC_DEBUG ++#include ++ ++int proc_get_drv_version(char *page, char **start, ++ off_t offset, int count, ++ int *eof, void *data) ++{ ++ struct net_device *dev = data; ++ ++ int len = 0; ++ ++ len += snprintf(page + len, count - len, "%s\n", DRIVERVERSION); ++ ++ *eof = 1; ++ return len; ++} ++ ++int proc_get_write_reg(char *page, char **start, ++ off_t offset, int count, ++ int *eof, void *data) ++{ ++ *eof = 1; ++ return 0; ++} ++ ++int proc_set_write_reg(struct file *file, const char *buffer, ++ unsigned long count, void *data) ++{ ++ struct net_device *dev = (struct net_device *)data; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ char tmp[32]; ++ u32 addr, val, len; ++ ++ if (count < 3) ++ { ++ DBG_8192C("argument size is less than 3\n"); ++ return -EFAULT; ++ } ++ ++ if (buffer && !copy_from_user(tmp, buffer, sizeof(tmp))) { ++ ++ int num = sscanf(tmp, "%x %x %x", &addr, &val, &len); ++ ++ if (num != 3) { ++ DBG_8192C("invalid write_reg parameter!\n"); ++ return count; ++ } ++ ++ switch(len) ++ { ++ case 1: ++ rtw_write8(padapter, addr, (u8)val); ++ break; ++ case 2: ++ rtw_write16(padapter, addr, (u16)val); ++ break; ++ case 4: ++ rtw_write32(padapter, addr, val); ++ break; ++ default: ++ DBG_8192C("error write length=%d", len); ++ break; ++ } ++ ++ } ++ ++ return count; ++ ++} ++ ++static u32 proc_get_read_addr=0xeeeeeeee; ++static u32 proc_get_read_len=0x4; ++ ++int proc_get_read_reg(char *page, char **start, ++ off_t offset, int count, ++ int *eof, void *data) ++{ ++ struct net_device *dev = data; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ ++ int len = 0; ++ ++ if(proc_get_read_addr==0xeeeeeeee) ++ { ++ *eof = 1; ++ return len; ++ } ++ ++ switch(proc_get_read_len) ++ { ++ case 1: ++ len += snprintf(page + len, count - len, "rtw_read8(0x%x)=0x%x\n", proc_get_read_addr, rtw_read8(padapter, proc_get_read_addr)); ++ break; ++ case 2: ++ len += snprintf(page + len, count - len, "rtw_read16(0x%x)=0x%x\n", proc_get_read_addr, rtw_read16(padapter, proc_get_read_addr)); ++ break; ++ case 4: ++ len += snprintf(page + len, count - len, "rtw_read32(0x%x)=0x%x\n", proc_get_read_addr, rtw_read32(padapter, proc_get_read_addr)); ++ break; ++ default: ++ len += snprintf(page + len, count - len, "error read length=%d\n", proc_get_read_len); ++ break; ++ } ++ ++ *eof = 1; ++ return len; ++ ++} ++ ++int proc_set_read_reg(struct file *file, const char *buffer, ++ unsigned long count, void *data) ++{ ++ struct net_device *dev = (struct net_device *)data; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ char tmp[16]; ++ u32 addr, len; ++ ++ if (count < 2) ++ { ++ DBG_8192C("argument size is less than 2\n"); ++ return -EFAULT; ++ } ++ ++ if (buffer && !copy_from_user(tmp, buffer, sizeof(tmp))) { ++ ++ int num = sscanf(tmp, "%x %x", &addr, &len); ++ ++ if (num != 2) { ++ DBG_8192C("invalid read_reg parameter!\n"); ++ return count; ++ } ++ ++ proc_get_read_addr = addr; ++ ++ proc_get_read_len = len; ++ } ++ ++ return count; ++ ++} ++ ++int proc_get_fwstate(char *page, char **start, ++ off_t offset, int count, ++ int *eof, void *data) ++{ ++ struct net_device *dev = data; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ ++ int len = 0; ++ ++ len += snprintf(page + len, count - len, "fwstate=0x%x\n", get_fwstate(pmlmepriv)); ++ ++ *eof = 1; ++ return len; ++} ++ ++int proc_get_sec_info(char *page, char **start, ++ off_t offset, int count, ++ int *eof, void *data) ++{ ++ struct net_device *dev = data; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct security_priv *psecuritypriv = &padapter->securitypriv; ++ ++ int len = 0; ++ ++ len += snprintf(page + len, count - len, "auth_alg=0x%x, enc_alg=0x%x, auth_type=0x%x, enc_type=0x%x\n", ++ psecuritypriv->dot11AuthAlgrthm, psecuritypriv->dot11PrivacyAlgrthm, ++ psecuritypriv->ndisauthtype, psecuritypriv->ndisencryptstatus); ++ ++ *eof = 1; ++ return len; ++} ++ ++int proc_get_mlmext_state(char *page, char **start, ++ off_t offset, int count, ++ int *eof, void *data) ++{ ++ struct net_device *dev = data; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ ++ int len = 0; ++ ++ len += snprintf(page + len, count - len, "pmlmeinfo->state=0x%x\n", pmlmeinfo->state); ++ ++ *eof = 1; ++ return len; ++} ++ ++int proc_get_qos_option(char *page, char **start, ++ off_t offset, int count, ++ int *eof, void *data) ++{ ++ struct net_device *dev = data; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ ++ int len = 0; ++ ++ len += snprintf(page + len, count - len, "qos_option=%d\n", pmlmepriv->qospriv.qos_option); ++ ++ *eof = 1; ++ return len; ++ ++} ++ ++int proc_get_ht_option(char *page, char **start, ++ off_t offset, int count, ++ int *eof, void *data) ++{ ++ struct net_device *dev = data; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ ++ int len = 0; ++ ++ len += snprintf(page + len, count - len, "ht_option=%d\n", pmlmepriv->htpriv.ht_option); ++ ++ *eof = 1; ++ return len; ++} ++ ++int proc_get_rf_info(char *page, char **start, ++ off_t offset, int count, ++ int *eof, void *data) ++{ ++ struct net_device *dev = data; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ int len = 0; ++ ++ len += snprintf(page + len, count - len, "cur_ch=%d, cur_bw=%d, cur_ch_offet=%d\n", ++ pmlmeext->cur_channel, pmlmeext->cur_bwmode, pmlmeext->cur_ch_offset); ++ ++ ++ *eof = 1; ++ return len; ++ ++} ++ ++int proc_get_ap_info(char *page, char **start, ++ off_t offset, int count, ++ int *eof, void *data) ++{ ++ struct sta_info *psta; ++ struct net_device *dev = data; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct wlan_network *cur_network = &(pmlmepriv->cur_network); ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ int len = 0; ++ ++ psta = rtw_get_stainfo(pstapriv, cur_network->network.MacAddress); ++ if(psta) ++ { ++ int i; ++ struct recv_reorder_ctrl *preorder_ctrl; ++ ++ len += snprintf(page + len, count - len, "SSID=%s\n", cur_network->network.Ssid.Ssid); ++ len += snprintf(page + len, count - len, "sta's macaddr:" MAC_FMT "\n", MAC_ARG(psta->hwaddr)); ++ len += snprintf(page + len, count - len, "cur_channel=%d, cur_bwmode=%d, cur_ch_offset=%d\n", pmlmeext->cur_channel, pmlmeext->cur_bwmode, pmlmeext->cur_ch_offset); ++ len += snprintf(page + len, count - len, "rtsen=%d, cts2slef=%d\n", psta->rtsen, psta->cts2self); ++ len += snprintf(page + len, count - len, "qos_en=%d, ht_en=%d, init_rate=%d\n", psta->qos_option, psta->htpriv.ht_option, psta->init_rate); ++ len += snprintf(page + len, count - len, "state=0x%x, aid=%d, macid=%d, raid=%d\n", psta->state, psta->aid, psta->mac_id, psta->raid); ++ len += snprintf(page + len, count - len, "bwmode=%d, ch_offset=%d, sgi=%d\n", psta->htpriv.bwmode, psta->htpriv.ch_offset, psta->htpriv.sgi); ++ len += snprintf(page + len, count - len, "ampdu_enable = %d\n", psta->htpriv.ampdu_enable); ++ len += snprintf(page + len, count - len, "agg_enable_bitmap=%x, candidate_tid_bitmap=%x\n", psta->htpriv.agg_enable_bitmap, psta->htpriv.candidate_tid_bitmap); ++ ++ for(i=0;i<16;i++) ++ { ++ preorder_ctrl = &psta->recvreorder_ctrl[i]; ++ if(preorder_ctrl->enable) ++ { ++ len += snprintf(page + len, count - len, "tid=%d, indicate_seq=%d\n", i, preorder_ctrl->indicate_seq); ++ } ++ } ++ ++ } ++ else ++ { ++ len += snprintf(page + len, count - len, "can't get sta's macaddr, cur_network's macaddr:" MAC_FMT "\n", MAC_ARG(cur_network->network.MacAddress)); ++ } ++ ++ *eof = 1; ++ return len; ++ ++} ++ ++int proc_get_adapter_state(char *page, char **start, ++ off_t offset, int count, ++ int *eof, void *data) ++{ ++ struct net_device *dev = data; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ int len = 0; ++ ++ len += snprintf(page + len, count - len, "bSurpriseRemoved=%d, bDriverStopped=%d\n", ++ padapter->bSurpriseRemoved, padapter->bDriverStopped); ++ ++ *eof = 1; ++ return len; ++ ++} ++ ++int proc_get_trx_info(char *page, char **start, ++ off_t offset, int count, ++ int *eof, void *data) ++{ ++ struct net_device *dev = data; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct xmit_priv *pxmitpriv = &padapter->xmitpriv; ++ struct recv_priv *precvpriv = &padapter->recvpriv; ++ int len = 0; ++ ++ len += snprintf(page + len, count - len, "free_xmitbuf_cnt=%d, free_xmitframe_cnt=%d, free_ext_xmitbuf_cnt=%d, free_recvframe_cnt=%d\n", ++ pxmitpriv->free_xmitbuf_cnt, pxmitpriv->free_xmitframe_cnt,pxmitpriv->free_xmit_extbuf_cnt, precvpriv->free_recvframe_cnt); ++#ifdef CONFIG_USB_HCI ++ len += snprintf(page + len, count - len, "rx_urb_pending_cn=%d\n", precvpriv->rx_pending_cnt); ++#endif ++ ++ *eof = 1; ++ return len; ++ ++} ++ ++ ++int proc_get_rx_signal(char *page, char **start, ++ off_t offset, int count, ++ int *eof, void *data) ++{ ++ struct net_device *dev = data; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ ++ int len = 0; ++ ++ len += snprintf(page + len, count - len, ++ "rssi:%d\n" ++ "rxpwdb:%d\n" ++ "signal_strength:%u\n" ++ "signal_qual:%u\n" ++ "noise:%u\n", ++ padapter->recvpriv.rssi, ++ padapter->recvpriv.rxpwdb, ++ padapter->recvpriv.signal_strength, ++ padapter->recvpriv.signal_qual, ++ padapter->recvpriv.noise ++ ); ++ ++ *eof = 1; ++ return len; ++} ++ ++int proc_set_rx_signal(struct file *file, const char *buffer, ++ unsigned long count, void *data) ++{ ++ struct net_device *dev = (struct net_device *)data; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ char tmp[32]; ++ u32 is_signal_dbg, signal_strength; ++ ++ if (count < 1) ++ return -EFAULT; ++ ++ if (buffer && !copy_from_user(tmp, buffer, sizeof(tmp))) { ++ ++ int num = sscanf(tmp, "%u %u", &is_signal_dbg, &signal_strength); ++ ++ is_signal_dbg = is_signal_dbg==0?0:1; ++ ++ if(is_signal_dbg && num!=2) ++ return count; ++ ++ signal_strength = signal_strength>100?100:signal_strength; ++ signal_strength = signal_strength<0?0:signal_strength; ++ ++ padapter->recvpriv.is_signal_dbg = is_signal_dbg; ++ padapter->recvpriv.signal_strength_dbg=signal_strength; ++ ++ if(is_signal_dbg) ++ DBG_871X("set %s %u\n", "DBG_SIGNAL_STRENGTH", signal_strength); ++ else ++ DBG_871X("set %s\n", "HW_SIGNAL_STRENGTH"); ++ ++ } ++ ++ return count; ++ ++} ++ ++int proc_get_rssi_disp(char *page, char **start, ++ off_t offset, int count, ++ int *eof, void *data) ++{ ++ *eof = 1; ++ return 0; ++} ++ ++int proc_set_rssi_disp(struct file *file, const char *buffer, ++ unsigned long count, void *data) ++{ ++ struct net_device *dev = (struct net_device *)data; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ char tmp[32]; ++ u32 enable=0; ++ ++ if (count < 1) ++ { ++ DBG_8192C("argument size is less than 1\n"); ++ return -EFAULT; ++ } ++ ++ if (buffer && !copy_from_user(tmp, buffer, sizeof(tmp))) { ++ ++ int num = sscanf(tmp, "%x", &enable); ++ ++ if (num != 1) { ++ DBG_8192C("invalid set_rssi_disp parameter!\n"); ++ return count; ++ } ++ ++ if(enable) ++ { ++ DBG_8192C("Turn On Rx RSSI Display Function\n"); ++ padapter->bRxRSSIDisplay = enable ; ++ } ++ else ++ { ++ DBG_8192C("Turn Off Rx RSSI Display Function\n"); ++ padapter->bRxRSSIDisplay = 0 ; ++ } ++ ++ } ++ ++ return count; ++ ++} ++ ++ ++#ifdef CONFIG_AP_MODE ++ ++int proc_get_all_sta_info(char *page, char **start, ++ off_t offset, int count, ++ int *eof, void *data) ++{ ++ _irqL irqL; ++ struct sta_info *psta; ++ struct net_device *dev = data; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ int i, j; ++ _list *plist, *phead; ++ struct recv_reorder_ctrl *preorder_ctrl; ++ int len = 0; ++ ++ ++ len += snprintf(page + len, count - len, "sta_dz_bitmap=0x%x, tim_bitmap=0x%x\n", pstapriv->sta_dz_bitmap, pstapriv->tim_bitmap); ++ ++ _enter_critical_bh(&pstapriv->sta_hash_lock, &irqL); ++ ++ for(i=0; i< NUM_STA; i++) ++ { ++ phead = &(pstapriv->sta_hash[i]); ++ plist = get_next(phead); ++ ++ while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) ++ { ++ psta = LIST_CONTAINOR(plist, struct sta_info, hash_list); ++ ++ plist = get_next(plist); ++ ++ //if(extra_arg == psta->aid) ++ { ++ len += snprintf(page + len, count - len, "sta's macaddr:" MAC_FMT "\n", MAC_ARG(psta->hwaddr)); ++ len += snprintf(page + len, count - len, "rtsen=%d, cts2slef=%d\n", psta->rtsen, psta->cts2self); ++ len += snprintf(page + len, count - len, "qos_en=%d, ht_en=%d, init_rate=%d\n", psta->qos_option, psta->htpriv.ht_option, psta->init_rate); ++ len += snprintf(page + len, count - len, "state=0x%x, aid=%d, macid=%d, raid=%d\n", psta->state, psta->aid, psta->mac_id, psta->raid); ++ len += snprintf(page + len, count - len, "bwmode=%d, ch_offset=%d, sgi=%d\n", psta->htpriv.bwmode, psta->htpriv.ch_offset, psta->htpriv.sgi); ++ len += snprintf(page + len, count - len, "ampdu_enable = %d\n", psta->htpriv.ampdu_enable); ++ len += snprintf(page + len, count - len, "agg_enable_bitmap=%x, candidate_tid_bitmap=%x\n", psta->htpriv.agg_enable_bitmap, psta->htpriv.candidate_tid_bitmap); ++ len += snprintf(page + len, count - len, "sleepq_len=%d\n", psta->sleepq_len); ++ len += snprintf(page + len, count - len, "capability=0x%x\n", psta->capability); ++ len += snprintf(page + len, count - len, "flags=0x%x\n", psta->flags); ++ len += snprintf(page + len, count - len, "wpa_psk=0x%x\n", psta->wpa_psk); ++ len += snprintf(page + len, count - len, "wpa2_group_cipher=0x%x\n", psta->wpa2_group_cipher); ++ len += snprintf(page + len, count - len, "wpa2_pairwise_cipher=0x%x\n", psta->wpa2_pairwise_cipher); ++ len += snprintf(page + len, count - len, "qos_info=0x%x\n", psta->qos_info); ++ len += snprintf(page + len, count - len, "dot118021XPrivacy=0x%x\n", psta->dot118021XPrivacy); ++ ++ for(j=0;j<16;j++) ++ { ++ preorder_ctrl = &psta->recvreorder_ctrl[j]; ++ if(preorder_ctrl->enable) ++ { ++ len += snprintf(page + len, count - len, "tid=%d, indicate_seq=%d\n", j, preorder_ctrl->indicate_seq); ++ } ++ } ++ ++ } ++ ++ } ++ ++ } ++ ++ _exit_critical_bh(&pstapriv->sta_hash_lock, &irqL); ++ ++ *eof = 1; ++ return len; ++ ++} ++ ++#endif ++ ++#ifdef DBG_MEMORY_LEAK ++#include ++extern atomic_t _malloc_cnt;; ++extern atomic_t _malloc_size;; ++ ++int proc_get_malloc_cnt(char *page, char **start, ++ off_t offset, int count, ++ int *eof, void *data) ++{ ++ ++ int len = 0; ++ ++ len += snprintf(page + len, count - len, "_malloc_cnt=%d\n", atomic_read(&_malloc_cnt)); ++ len += snprintf(page + len, count - len, "_malloc_size=%d\n", atomic_read(&_malloc_size)); ++ ++ *eof = 1; ++ return len; ++} ++#endif /* DBG_MEMORY_LEAK */ ++ ++#ifdef CONFIG_FIND_BEST_CHANNEL ++int proc_get_best_channel(char *page, char **start, ++ off_t offset, int count, ++ int *eof, void *data) ++{ ++ struct net_device *dev = data; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ int len = 0; ++ u32 i, best_channel_24G = 1, best_channel_5G = 36, index_24G = 0, index_5G = 0; ++ ++ for (i=0; pmlmeext->channel_set[i].ChannelNum !=0; i++) { ++ if ( pmlmeext->channel_set[i].ChannelNum == 1) ++ index_24G = i; ++ if ( pmlmeext->channel_set[i].ChannelNum == 36) ++ index_5G = i; ++ } ++ ++ for (i=0; pmlmeext->channel_set[i].ChannelNum !=0; i++) { ++ // 2.4G ++ if ( pmlmeext->channel_set[i].ChannelNum == 6 ) { ++ if ( pmlmeext->channel_set[i].rx_count < pmlmeext->channel_set[index_24G].rx_count ) { ++ index_24G = i; ++ best_channel_24G = pmlmeext->channel_set[i].ChannelNum; ++ } ++ } ++ ++ // 5G ++ if ( pmlmeext->channel_set[i].ChannelNum >= 36 ++ && pmlmeext->channel_set[i].ChannelNum < 140 ) { ++ // Find primary channel ++ if ( (( pmlmeext->channel_set[i].ChannelNum - 36) % 8 == 0) ++ && (pmlmeext->channel_set[i].rx_count < pmlmeext->channel_set[index_5G].rx_count) ) { ++ index_5G = i; ++ best_channel_5G = pmlmeext->channel_set[i].ChannelNum; ++ } ++ } ++ ++ if ( pmlmeext->channel_set[i].ChannelNum >= 149 ++ && pmlmeext->channel_set[i].ChannelNum < 165) { ++ // find primary channel ++ if ( (( pmlmeext->channel_set[i].ChannelNum - 149) % 8 == 0) ++ && (pmlmeext->channel_set[i].rx_count < pmlmeext->channel_set[index_5G].rx_count) ) { ++ index_5G = i; ++ best_channel_5G = pmlmeext->channel_set[i].ChannelNum; ++ } ++ } ++#if 1 // debug ++ len += snprintf(page + len, count - len, "The rx cnt of channel %3d = %d\n", ++ pmlmeext->channel_set[i].ChannelNum, pmlmeext->channel_set[i].rx_count); ++#endif ++ } ++ ++ len += snprintf(page + len, count - len, "best_channel_5G = %d\n", best_channel_5G); ++ len += snprintf(page + len, count - len, "best_channel_24G = %d\n", best_channel_24G); ++ ++ *eof = 1; ++ return len; ++ ++} ++#endif /* CONFIG_FIND_BEST_CHANNEL */ ++ ++#endif ++ +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/core/rtw_eeprom.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/core/rtw_eeprom.c 2013-07-26 19:36:04.000000000 +0000 +@@ -0,0 +1,424 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ++******************************************************************************/ ++#define _RTW_EEPROM_C_ ++ ++#include ++#include ++#include ++ ++void up_clk(_adapter* padapter, u16 *x) ++{ ++_func_enter_; ++ *x = *x | _EESK; ++ rtw_write8(padapter, EE_9346CR, (u8)*x); ++ rtw_udelay_os(CLOCK_RATE); ++ ++_func_exit_; ++ ++} ++ ++void down_clk(_adapter * padapter, u16 *x ) ++{ ++_func_enter_; ++ *x = *x & ~_EESK; ++ rtw_write8(padapter, EE_9346CR, (u8)*x); ++ rtw_udelay_os(CLOCK_RATE); ++_func_exit_; ++} ++ ++void shift_out_bits(_adapter * padapter, u16 data, u16 count) ++{ ++ u16 x,mask; ++_func_enter_; ++ ++ if(padapter->bSurpriseRemoved==_TRUE){ ++ RT_TRACE(_module_rtl871x_eeprom_c_,_drv_err_,("padapter->bSurpriseRemoved==_TRUE")); ++ goto out; ++ } ++ mask = 0x01 << (count - 1); ++ x = rtw_read8(padapter, EE_9346CR); ++ ++ x &= ~(_EEDO | _EEDI); ++ ++ do ++ { ++ x &= ~_EEDI; ++ if(data & mask) ++ x |= _EEDI; ++ if(padapter->bSurpriseRemoved==_TRUE){ ++ RT_TRACE(_module_rtl871x_eeprom_c_,_drv_err_,("padapter->bSurpriseRemoved==_TRUE")); ++ goto out; ++ } ++ rtw_write8(padapter, EE_9346CR, (u8)x); ++ rtw_udelay_os(CLOCK_RATE); ++ up_clk(padapter, &x); ++ down_clk(padapter, &x); ++ mask = mask >> 1; ++ } while(mask); ++ if(padapter->bSurpriseRemoved==_TRUE){ ++ RT_TRACE(_module_rtl871x_eeprom_c_,_drv_err_,("padapter->bSurpriseRemoved==_TRUE")); ++ goto out; ++ } ++ x &= ~_EEDI; ++ rtw_write8(padapter, EE_9346CR, (u8)x); ++out: ++_func_exit_; ++} ++ ++u16 shift_in_bits (_adapter * padapter) ++{ ++ u16 x,d=0,i; ++_func_enter_; ++ if(padapter->bSurpriseRemoved==_TRUE){ ++ RT_TRACE(_module_rtl871x_eeprom_c_,_drv_err_,("padapter->bSurpriseRemoved==_TRUE")); ++ goto out; ++ } ++ x = rtw_read8(padapter, EE_9346CR); ++ ++ x &= ~( _EEDO | _EEDI); ++ d = 0; ++ ++ for(i=0; i<16; i++) ++ { ++ d = d << 1; ++ up_clk(padapter, &x); ++ if(padapter->bSurpriseRemoved==_TRUE){ ++ RT_TRACE(_module_rtl871x_eeprom_c_,_drv_err_,("padapter->bSurpriseRemoved==_TRUE")); ++ goto out; ++ } ++ x = rtw_read8(padapter, EE_9346CR); ++ ++ x &= ~(_EEDI); ++ if(x & _EEDO) ++ d |= 1; ++ ++ down_clk(padapter, &x); ++ } ++out: ++_func_exit_; ++ ++ return d; ++} ++ ++void standby(_adapter * padapter ) ++{ ++ u8 x; ++_func_enter_; ++ x = rtw_read8(padapter, EE_9346CR); ++ ++ x &= ~(_EECS | _EESK); ++ rtw_write8(padapter, EE_9346CR,x); ++ ++ rtw_udelay_os(CLOCK_RATE); ++ x |= _EECS; ++ rtw_write8(padapter, EE_9346CR, x); ++ rtw_udelay_os(CLOCK_RATE); ++_func_exit_; ++} ++ ++u16 wait_eeprom_cmd_done(_adapter* padapter) ++{ ++ u8 x; ++ u16 i,res=_FALSE; ++_func_enter_; ++ standby(padapter ); ++ for (i=0; i<200; i++) ++ { ++ x = rtw_read8(padapter, EE_9346CR); ++ if (x & _EEDO){ ++ res=_TRUE; ++ goto exit; ++ } ++ rtw_udelay_os(CLOCK_RATE); ++ } ++exit: ++_func_exit_; ++ return res; ++} ++ ++void eeprom_clean(_adapter * padapter) ++{ ++ u16 x; ++_func_enter_; ++ if(padapter->bSurpriseRemoved==_TRUE){ ++ RT_TRACE(_module_rtl871x_eeprom_c_,_drv_err_,("padapter->bSurpriseRemoved==_TRUE")); ++ goto out; ++ } ++ x = rtw_read8(padapter, EE_9346CR); ++ if(padapter->bSurpriseRemoved==_TRUE){ ++ RT_TRACE(_module_rtl871x_eeprom_c_,_drv_err_,("padapter->bSurpriseRemoved==_TRUE")); ++ goto out; ++ } ++ x &= ~(_EECS | _EEDI); ++ rtw_write8(padapter, EE_9346CR, (u8)x); ++ if(padapter->bSurpriseRemoved==_TRUE){ ++ RT_TRACE(_module_rtl871x_eeprom_c_,_drv_err_,("padapter->bSurpriseRemoved==_TRUE")); ++ goto out; ++ } ++ up_clk(padapter, &x); ++ if(padapter->bSurpriseRemoved==_TRUE){ ++ RT_TRACE(_module_rtl871x_eeprom_c_,_drv_err_,("padapter->bSurpriseRemoved==_TRUE")); ++ goto out; ++ } ++ down_clk(padapter, &x); ++out: ++_func_exit_; ++} ++ ++void eeprom_write16(_adapter * padapter, u16 reg, u16 data) ++{ ++ u8 x; ++#ifdef CONFIG_RTL8712 ++ u8 tmp8_ori,tmp8_new,tmp8_clk_ori,tmp8_clk_new; ++ tmp8_ori=rtw_read8(padapter, 0x102502f1); ++ tmp8_new=tmp8_ori & 0xf7; ++ if(tmp8_ori != tmp8_new){ ++ rtw_write8(padapter, 0x102502f1, tmp8_new); ++ RT_TRACE(_module_rtl871x_mp_ioctl_c_,_drv_err_,("====write 0x102502f1=====\n")); ++ } ++ tmp8_clk_ori=rtw_read8(padapter,0x10250003); ++ tmp8_clk_new=tmp8_clk_ori|0x20; ++ if(tmp8_clk_new!=tmp8_clk_ori){ ++ RT_TRACE(_module_rtl871x_mp_ioctl_c_,_drv_err_,("====write 0x10250003=====\n")); ++ rtw_write8(padapter, 0x10250003, tmp8_clk_new); ++ } ++#endif ++_func_enter_; ++ ++ x = rtw_read8(padapter, EE_9346CR); ++ ++ x &= ~(_EEDI | _EEDO | _EESK | _EEM0); ++ x |= _EEM1 | _EECS; ++ rtw_write8(padapter, EE_9346CR, x); ++ ++ shift_out_bits(padapter, EEPROM_EWEN_OPCODE, 5); ++ ++ if(padapter->EepromAddressSize==8) //CF+ and SDIO ++ shift_out_bits(padapter, 0, 6); ++ else //USB ++ shift_out_bits(padapter, 0, 4); ++ ++ standby( padapter); ++ ++// Commented out by rcnjko, 2004.0 ++// // Erase this particular word. Write the erase opcode and register ++// // number in that order. The opcode is 3bits in length; reg is 6 bits long. ++// shift_out_bits(Adapter, EEPROM_ERASE_OPCODE, 3); ++// shift_out_bits(Adapter, reg, Adapter->EepromAddressSize); ++// ++// if (wait_eeprom_cmd_done(Adapter ) == FALSE) ++// { ++// return; ++// } ++ ++ ++ standby(padapter ); ++ ++ // write the new word to the EEPROM ++ ++ // send the write opcode the EEPORM ++ shift_out_bits(padapter, EEPROM_WRITE_OPCODE, 3); ++ ++ // select which word in the EEPROM that we are writing to. ++ shift_out_bits(padapter, reg, padapter->EepromAddressSize); ++ ++ // write the data to the selected EEPROM word. ++ shift_out_bits(padapter, data, 16); ++ ++ if (wait_eeprom_cmd_done(padapter ) == _FALSE) ++ { ++ ++ goto exit; ++ } ++ ++ standby(padapter ); ++ ++ shift_out_bits(padapter, EEPROM_EWDS_OPCODE, 5); ++ shift_out_bits(padapter, reg, 4); ++ ++ eeprom_clean(padapter ); ++exit: ++#ifdef CONFIG_RTL8712 ++ if(tmp8_clk_new!=tmp8_clk_ori) ++ rtw_write8(padapter, 0x10250003, tmp8_clk_ori); ++ if(tmp8_new!=tmp8_ori) ++ rtw_write8(padapter, 0x102502f1, tmp8_ori); ++ ++#endif ++_func_exit_; ++ return; ++} ++ ++u16 eeprom_read16(_adapter * padapter, u16 reg) //ReadEEprom ++{ ++ ++ u16 x; ++ u16 data=0; ++#ifdef CONFIG_RTL8712 ++ u8 tmp8_ori,tmp8_new,tmp8_clk_ori,tmp8_clk_new; ++ tmp8_ori= rtw_read8(padapter, 0x102502f1); ++ tmp8_new = tmp8_ori & 0xf7; ++ if(tmp8_ori != tmp8_new){ ++ rtw_write8(padapter, 0x102502f1, tmp8_new); ++ RT_TRACE(_module_rtl871x_mp_ioctl_c_,_drv_err_,("====write 0x102502f1=====\n")); ++ } ++ tmp8_clk_ori=rtw_read8(padapter,0x10250003); ++ tmp8_clk_new=tmp8_clk_ori|0x20; ++ if(tmp8_clk_new!=tmp8_clk_ori){ ++ RT_TRACE(_module_rtl871x_mp_ioctl_c_,_drv_err_,("====write 0x10250003=====\n")); ++ rtw_write8(padapter, 0x10250003, tmp8_clk_new); ++ } ++#endif ++_func_enter_; ++ ++ if(padapter->bSurpriseRemoved==_TRUE){ ++ RT_TRACE(_module_rtl871x_eeprom_c_,_drv_err_,("padapter->bSurpriseRemoved==_TRUE")); ++ goto out; ++ } ++ // select EEPROM, reset bits, set _EECS ++ x = rtw_read8(padapter, EE_9346CR); ++ ++ if(padapter->bSurpriseRemoved==_TRUE){ ++ RT_TRACE(_module_rtl871x_eeprom_c_,_drv_err_,("padapter->bSurpriseRemoved==_TRUE")); ++ goto out; ++ } ++ ++ x &= ~(_EEDI | _EEDO | _EESK | _EEM0); ++ x |= _EEM1 | _EECS; ++ rtw_write8(padapter, EE_9346CR, (unsigned char)x); ++ ++ // write the read opcode and register number in that order ++ // The opcode is 3bits in length, reg is 6 bits long ++ shift_out_bits(padapter, EEPROM_READ_OPCODE, 3); ++ shift_out_bits(padapter, reg, padapter->EepromAddressSize); ++ ++ // Now read the data (16 bits) in from the selected EEPROM word ++ data = shift_in_bits(padapter); ++ ++ eeprom_clean(padapter); ++out: ++#ifdef CONFIG_RTL8712 ++ if(tmp8_clk_new!=tmp8_clk_ori) ++ rtw_write8(padapter, 0x10250003, tmp8_clk_ori); ++ if(tmp8_new!=tmp8_ori) ++ rtw_write8(padapter, 0x102502f1, tmp8_ori); ++ ++#endif ++_func_exit_; ++ return data; ++ ++ ++} ++ ++ ++ ++ ++//From even offset ++void eeprom_read_sz(_adapter * padapter, u16 reg, u8* data, u32 sz) ++{ ++ ++ u16 x, data16; ++ u32 i; ++_func_enter_; ++ if(padapter->bSurpriseRemoved==_TRUE){ ++ RT_TRACE(_module_rtl871x_eeprom_c_,_drv_err_,("padapter->bSurpriseRemoved==_TRUE")); ++ goto out; ++ } ++ // select EEPROM, reset bits, set _EECS ++ x = rtw_read8(padapter, EE_9346CR); ++ ++ if(padapter->bSurpriseRemoved==_TRUE){ ++ RT_TRACE(_module_rtl871x_eeprom_c_,_drv_err_,("padapter->bSurpriseRemoved==_TRUE")); ++ goto out; ++ } ++ ++ x &= ~(_EEDI | _EEDO | _EESK | _EEM0); ++ x |= _EEM1 | _EECS; ++ rtw_write8(padapter, EE_9346CR, (unsigned char)x); ++ ++ // write the read opcode and register number in that order ++ // The opcode is 3bits in length, reg is 6 bits long ++ shift_out_bits(padapter, EEPROM_READ_OPCODE, 3); ++ shift_out_bits(padapter, reg, padapter->EepromAddressSize); ++ ++ ++ for(i=0; i>8; ++ } ++ ++ eeprom_clean(padapter); ++out: ++_func_exit_; ++ ++ ++ ++} ++ ++ ++//addr_off : address offset of the entry in eeprom (not the tuple number of eeprom (reg); that is addr_off !=reg) ++u8 eeprom_read(_adapter * padapter, u32 addr_off, u8 sz, u8* rbuf) ++{ ++ u8 quotient, remainder, addr_2align_odd; ++ u16 reg, stmp , i=0, idx = 0; ++_func_enter_; ++ reg = (u16)(addr_off >> 1); ++ addr_2align_odd = (u8)(addr_off & 0x1); ++ ++ if(addr_2align_odd) //read that start at high part: e.g 1,3,5,7,9,... ++ { ++ stmp = eeprom_read16(padapter, reg); ++ rbuf[idx++] = (u8) ((stmp>>8)&0xff); //return hogh-part of the short ++ reg++; sz--; ++ } ++ ++ quotient = sz >> 1; ++ remainder = sz & 0x1; ++ ++ for( i=0 ; i < quotient; i++) ++ { ++ stmp = eeprom_read16(padapter, reg+i); ++ rbuf[idx++] = (u8) (stmp&0xff); ++ rbuf[idx++] = (u8) ((stmp>>8)&0xff); ++ } ++ ++ reg = reg+i; ++ if(remainder){ //end of read at lower part of short : 0,2,4,6,... ++ stmp = eeprom_read16(padapter, reg); ++ rbuf[idx] = (u8)(stmp & 0xff); ++ } ++_func_exit_; ++ return _TRUE; ++} ++ ++ ++ ++VOID read_eeprom_content(_adapter * padapter) ++{ ++ ++_func_enter_; ++ ++ ++_func_exit_; ++} ++ +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/core/rtw_ieee80211.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/core/rtw_ieee80211.c 2013-07-26 19:36:04.000000000 +0000 +@@ -0,0 +1,1486 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#define _IEEE80211_C ++ ++#include ++#include ++#include ++#include ++#include ++ ++ ++//----------------------------------------------------------- ++// for adhoc-master to generate ie and provide supported-rate to fw ++//----------------------------------------------------------- ++ ++static u8 WIFI_CCKRATES[] = ++{(IEEE80211_CCK_RATE_1MB | IEEE80211_BASIC_RATE_MASK), ++ (IEEE80211_CCK_RATE_2MB | IEEE80211_BASIC_RATE_MASK), ++ (IEEE80211_CCK_RATE_5MB | IEEE80211_BASIC_RATE_MASK), ++ (IEEE80211_CCK_RATE_11MB | IEEE80211_BASIC_RATE_MASK)}; ++ ++static u8 WIFI_OFDMRATES[] = ++{(IEEE80211_OFDM_RATE_6MB), ++ (IEEE80211_OFDM_RATE_9MB), ++ (IEEE80211_OFDM_RATE_12MB), ++ (IEEE80211_OFDM_RATE_18MB), ++ (IEEE80211_OFDM_RATE_24MB), ++ IEEE80211_OFDM_RATE_36MB, ++ IEEE80211_OFDM_RATE_48MB, ++ IEEE80211_OFDM_RATE_54MB}; ++ ++ ++int rtw_get_bit_value_from_ieee_value(u8 val) ++{ ++ unsigned char dot11_rate_table[]={2,4,11,22,12,18,24,36,48,72,96,108,0}; // last element must be zero!! ++ ++ int i=0; ++ while(dot11_rate_table[i] != 0) { ++ if (dot11_rate_table[i] == val) ++ return BIT(i); ++ i++; ++ } ++ return 0; ++} ++ ++uint rtw_is_cckrates_included(u8 *rate) ++{ ++ u32 i = 0; ++ ++ while(rate[i]!=0) ++ { ++ if ( (((rate[i]) & 0x7f) == 2) || (((rate[i]) & 0x7f) == 4) || ++ (((rate[i]) & 0x7f) == 11) || (((rate[i]) & 0x7f) == 22) ) ++ return _TRUE; ++ i++; ++ } ++ ++ return _FALSE; ++} ++ ++uint rtw_is_cckratesonly_included(u8 *rate) ++{ ++ u32 i = 0; ++ ++ ++ while(rate[i]!=0) ++ { ++ if ( (((rate[i]) & 0x7f) != 2) && (((rate[i]) & 0x7f) != 4) && ++ (((rate[i]) & 0x7f) != 11) && (((rate[i]) & 0x7f) != 22) ) ++ ++ return _FALSE; ++ ++ i++; ++ } ++ ++ return _TRUE; ++ ++} ++ ++int rtw_check_network_type(unsigned char *rate, int ratelen, int channel) ++{ ++ if (channel > 14) ++ { ++ if ((rtw_is_cckrates_included(rate)) == _TRUE) ++ return WIRELESS_INVALID; ++ else ++ return WIRELESS_11A; ++ } ++ else // could be pure B, pure G, or B/G ++ { ++ if ((rtw_is_cckratesonly_included(rate)) == _TRUE) ++ return WIRELESS_11B; ++ else if((rtw_is_cckrates_included(rate)) == _TRUE) ++ return WIRELESS_11BG; ++ else ++ return WIRELESS_11G; ++ } ++ ++} ++ ++u8 *rtw_set_fixed_ie(unsigned char *pbuf, unsigned int len, unsigned char *source, ++ unsigned int *frlen) ++{ ++ _rtw_memcpy((void *)pbuf, (void *)source, len); ++ *frlen = *frlen + len; ++ return (pbuf + len); ++} ++ ++// rtw_set_ie will update frame length ++u8 *rtw_set_ie ++( ++ u8 *pbuf, ++ sint index, ++ uint len, ++ u8 *source, ++ uint *frlen //frame length ++) ++{ ++_func_enter_; ++ *pbuf = (u8)index; ++ ++ *(pbuf + 1) = (u8)len; ++ ++ if (len > 0) ++ _rtw_memcpy((void *)(pbuf + 2), (void *)source, len); ++ ++ *frlen = *frlen + (len + 2); ++ ++ return (pbuf + len + 2); ++_func_exit_; ++} ++ ++ ++ ++/*---------------------------------------------------------------------------- ++index: the information element id index, limit is the limit for search ++-----------------------------------------------------------------------------*/ ++u8 *rtw_get_ie(u8 *pbuf, sint index, sint *len, sint limit) ++{ ++ sint tmp,i; ++ u8 *p; ++_func_enter_; ++ if (limit < 1){ ++ _func_exit_; ++ return NULL; ++ } ++ ++ p = pbuf; ++ i = 0; ++ *len = 0; ++ while(1) ++ { ++ if (*p == index) ++ { ++ *len = *(p + 1); ++ return (p); ++ } ++ else ++ { ++ tmp = *(p + 1); ++ p += (tmp + 2); ++ i += (tmp + 2); ++ } ++ if (i >= limit) ++ break; ++ } ++_func_exit_; ++ return NULL; ++} ++ ++void rtw_set_supported_rate(u8* SupportedRates, uint mode) ++{ ++_func_enter_; ++ ++ _rtw_memset(SupportedRates, 0, NDIS_802_11_LENGTH_RATES_EX); ++ ++ switch (mode) ++ { ++ case WIRELESS_11B: ++ _rtw_memcpy(SupportedRates, WIFI_CCKRATES, IEEE80211_CCK_RATE_LEN); ++ break; ++ ++ case WIRELESS_11G: ++ case WIRELESS_11A: ++ case WIRELESS_11_5N: ++ case WIRELESS_11A_5N://Todo: no basic rate for ofdm ? ++ _rtw_memcpy(SupportedRates, WIFI_OFDMRATES, IEEE80211_NUM_OFDM_RATESLEN); ++ break; ++ ++ case WIRELESS_11BG: ++ case WIRELESS_11G_24N: ++ case WIRELESS_11_24N: ++ case WIRELESS_11BG_24N: ++ _rtw_memcpy(SupportedRates, WIFI_CCKRATES, IEEE80211_CCK_RATE_LEN); ++ _rtw_memcpy(SupportedRates + IEEE80211_CCK_RATE_LEN, WIFI_OFDMRATES, IEEE80211_NUM_OFDM_RATESLEN); ++ break; ++ ++ } ++_func_exit_; ++} ++ ++uint rtw_get_rateset_len(u8 *rateset) ++{ ++ uint i = 0; ++_func_enter_; ++ while(1) ++ { ++ if ((rateset[i]) == 0) ++ break; ++ ++ if (i > 12) ++ break; ++ ++ i++; ++ } ++_func_exit_; ++ return i; ++} ++ ++int rtw_generate_ie(struct registry_priv *pregistrypriv) ++{ ++ u8 wireless_mode; ++ int sz = 0, rateLen; ++ WLAN_BSSID_EX* pdev_network = &pregistrypriv->dev_network; ++ u8* ie = pdev_network->IEs; ++ ++_func_enter_; ++ ++ //timestamp will be inserted by hardware ++ sz += 8; ++ ie += sz; ++ ++ //beacon interval : 2bytes ++ *(u16*)ie = cpu_to_le16((u16)pdev_network->Configuration.BeaconPeriod);//BCN_INTERVAL; ++ sz += 2; ++ ie += 2; ++ ++ //capability info ++ *(u16*)ie = 0; ++ ++ *(u16*)ie |= cpu_to_le16(cap_IBSS); ++ ++ if(pregistrypriv->preamble == PREAMBLE_SHORT) ++ *(u16*)ie |= cpu_to_le16(cap_ShortPremble); ++ ++ if (pdev_network->Privacy) ++ *(u16*)ie |= cpu_to_le16(cap_Privacy); ++ ++ sz += 2; ++ ie += 2; ++ ++ //SSID ++ ie = rtw_set_ie(ie, _SSID_IE_, pdev_network->Ssid.SsidLength, pdev_network->Ssid.Ssid, &sz); ++ ++ //supported rates ++ if(pregistrypriv->wireless_mode == WIRELESS_11ABGN) ++ { ++ if(pdev_network->Configuration.DSConfig > 14) ++ wireless_mode = WIRELESS_11A_5N; ++ else ++ wireless_mode = WIRELESS_11BG_24N; ++ } ++ else ++ { ++ wireless_mode = pregistrypriv->wireless_mode; ++ } ++ ++ rtw_set_supported_rate(pdev_network->SupportedRates, wireless_mode) ; ++ ++ rateLen = rtw_get_rateset_len(pdev_network->SupportedRates); ++ ++ if (rateLen > 8) ++ { ++ ie = rtw_set_ie(ie, _SUPPORTEDRATES_IE_, 8, pdev_network->SupportedRates, &sz); ++ //ie = rtw_set_ie(ie, _EXT_SUPPORTEDRATES_IE_, (rateLen - 8), (pdev_network->SupportedRates + 8), &sz); ++ } ++ else ++ { ++ ie = rtw_set_ie(ie, _SUPPORTEDRATES_IE_, rateLen, pdev_network->SupportedRates, &sz); ++ } ++ ++ //DS parameter set ++ ie = rtw_set_ie(ie, _DSSET_IE_, 1, (u8 *)&(pdev_network->Configuration.DSConfig), &sz); ++ ++ ++ //IBSS Parameter Set ++ ++ ie = rtw_set_ie(ie, _IBSS_PARA_IE_, 2, (u8 *)&(pdev_network->Configuration.ATIMWindow), &sz); ++ ++ if (rateLen > 8) ++ { ++ ie = rtw_set_ie(ie, _EXT_SUPPORTEDRATES_IE_, (rateLen - 8), (pdev_network->SupportedRates + 8), &sz); ++ } ++ ++ ++ //HT Cap. ++ if(((pregistrypriv->wireless_mode&WIRELESS_11_5N)||(pregistrypriv->wireless_mode&WIRELESS_11_24N)) ++ && (pregistrypriv->ht_enable==_TRUE)) ++ { ++ //todo: ++ } ++ ++ //pdev_network->IELength = sz; //update IELength ++ ++_func_exit_; ++ ++ //return _SUCCESS; ++ ++ return sz; ++ ++} ++ ++unsigned char *rtw_get_wpa_ie(unsigned char *pie, int *wpa_ie_len, int limit) ++{ ++ int len; ++ u16 val16; ++ unsigned char wpa_oui_type[] = {0x00, 0x50, 0xf2, 0x01}; ++ u8 *pbuf = pie; ++ ++ while(1) ++ { ++ pbuf = rtw_get_ie(pbuf, _WPA_IE_ID_, &len, limit); ++ ++ if (pbuf) { ++ ++ //check if oui matches... ++ if (_rtw_memcmp((pbuf + 2), wpa_oui_type, sizeof (wpa_oui_type)) == _FALSE) { ++ ++ goto check_next_ie; ++ } ++ ++ //check version... ++ _rtw_memcpy((u8 *)&val16, (pbuf + 6), sizeof(val16)); ++ ++ val16 = le16_to_cpu(val16); ++ if (val16 != 0x0001) ++ goto check_next_ie; ++ ++ *wpa_ie_len = *(pbuf + 1); ++ ++ return pbuf; ++ ++ } ++ else { ++ ++ *wpa_ie_len = 0; ++ return NULL; ++ } ++ ++check_next_ie: ++ ++ limit = limit - (pbuf - pie) - 2 - len; ++ ++ if (limit <= 0) ++ break; ++ ++ pbuf += (2 + len); ++ ++ } ++ ++ *wpa_ie_len = 0; ++ ++ return NULL; ++ ++} ++ ++unsigned char *rtw_get_wpa2_ie(unsigned char *pie, int *rsn_ie_len, int limit) ++{ ++ ++ return rtw_get_ie(pie, _WPA2_IE_ID_,rsn_ie_len, limit); ++ ++} ++ ++int rtw_get_wpa_cipher_suite(u8 *s) ++{ ++ if (_rtw_memcmp(s, WPA_CIPHER_SUITE_NONE, WPA_SELECTOR_LEN) == _TRUE) ++ return WPA_CIPHER_NONE; ++ if (_rtw_memcmp(s, WPA_CIPHER_SUITE_WEP40, WPA_SELECTOR_LEN) == _TRUE) ++ return WPA_CIPHER_WEP40; ++ if (_rtw_memcmp(s, WPA_CIPHER_SUITE_TKIP, WPA_SELECTOR_LEN) == _TRUE) ++ return WPA_CIPHER_TKIP; ++ if (_rtw_memcmp(s, WPA_CIPHER_SUITE_CCMP, WPA_SELECTOR_LEN) == _TRUE) ++ return WPA_CIPHER_CCMP; ++ if (_rtw_memcmp(s, WPA_CIPHER_SUITE_WEP104, WPA_SELECTOR_LEN) == _TRUE) ++ return WPA_CIPHER_WEP104; ++ ++ return 0; ++} ++ ++int rtw_get_wpa2_cipher_suite(u8 *s) ++{ ++ if (_rtw_memcmp(s, RSN_CIPHER_SUITE_NONE, RSN_SELECTOR_LEN) == _TRUE) ++ return WPA_CIPHER_NONE; ++ if (_rtw_memcmp(s, RSN_CIPHER_SUITE_WEP40, RSN_SELECTOR_LEN) == _TRUE) ++ return WPA_CIPHER_WEP40; ++ if (_rtw_memcmp(s, RSN_CIPHER_SUITE_TKIP, RSN_SELECTOR_LEN) == _TRUE) ++ return WPA_CIPHER_TKIP; ++ if (_rtw_memcmp(s, RSN_CIPHER_SUITE_CCMP, RSN_SELECTOR_LEN) == _TRUE) ++ return WPA_CIPHER_CCMP; ++ if (_rtw_memcmp(s, RSN_CIPHER_SUITE_WEP104, RSN_SELECTOR_LEN) == _TRUE) ++ return WPA_CIPHER_WEP104; ++ ++ return 0; ++} ++ ++ ++int rtw_parse_wpa_ie(u8* wpa_ie, int wpa_ie_len, int *group_cipher, int *pairwise_cipher) ++{ ++ int i, ret=_SUCCESS; ++ int left, count; ++ u8 *pos; ++ ++ if (wpa_ie_len <= 0) { ++ /* No WPA IE - fail silently */ ++ return _FAIL; ++ } ++ ++ ++ if ((*wpa_ie != _WPA_IE_ID_) || (*(wpa_ie+1) != (u8)(wpa_ie_len - 2)) || ++ (_rtw_memcmp(wpa_ie+2, WPA_OUI_TYPE, WPA_SELECTOR_LEN) != _TRUE) ) ++ { ++ return _FAIL; ++ } ++ ++ pos = wpa_ie; ++ ++ pos += 8; ++ left = wpa_ie_len - 8; ++ ++ ++ //group_cipher ++ if (left >= WPA_SELECTOR_LEN) { ++ ++ *group_cipher = rtw_get_wpa_cipher_suite(pos); ++ ++ pos += WPA_SELECTOR_LEN; ++ left -= WPA_SELECTOR_LEN; ++ ++ } ++ else if (left > 0) ++ { ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("%s: ie length mismatch, %u too much", __FUNCTION__, left)); ++ ++ return _FAIL; ++ } ++ ++ ++ //pairwise_cipher ++ if (left >= 2) ++ { ++ //count = le16_to_cpu(*(u16*)pos); ++ count = RTW_GET_LE16(pos); ++ pos += 2; ++ left -= 2; ++ ++ if (count == 0 || left < count * WPA_SELECTOR_LEN) { ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("%s: ie count botch (pairwise), " ++ "count %u left %u", __FUNCTION__, count, left)); ++ return _FAIL; ++ } ++ ++ for (i = 0; i < count; i++) ++ { ++ *pairwise_cipher |= rtw_get_wpa_cipher_suite(pos); ++ ++ pos += WPA_SELECTOR_LEN; ++ left -= WPA_SELECTOR_LEN; ++ } ++ ++ } ++ else if (left == 1) ++ { ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("%s: ie too short (for key mgmt)", __FUNCTION__)); ++ return _FAIL; ++ } ++ ++ ++ return ret; ++ ++} ++ ++int rtw_parse_wpa2_ie(u8* rsn_ie, int rsn_ie_len, int *group_cipher, int *pairwise_cipher) ++{ ++ int i, ret=_SUCCESS; ++ int left, count; ++ u8 *pos; ++ ++ if (rsn_ie_len <= 0) { ++ /* No RSN IE - fail silently */ ++ return _FAIL; ++ } ++ ++ ++ if ((*rsn_ie!= _WPA2_IE_ID_) || (*(rsn_ie+1) != (u8)(rsn_ie_len - 2))) ++ { ++ return _FAIL; ++ } ++ ++ pos = rsn_ie; ++ pos += 4; ++ left = rsn_ie_len - 4; ++ ++ //group_cipher ++ if (left >= RSN_SELECTOR_LEN) { ++ ++ *group_cipher = rtw_get_wpa2_cipher_suite(pos); ++ ++ pos += RSN_SELECTOR_LEN; ++ left -= RSN_SELECTOR_LEN; ++ ++ } else if (left > 0) { ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("%s: ie length mismatch, %u too much", __FUNCTION__, left)); ++ return _FAIL; ++ } ++ ++ //pairwise_cipher ++ if (left >= 2) ++ { ++ //count = le16_to_cpu(*(u16*)pos); ++ count = RTW_GET_LE16(pos); ++ pos += 2; ++ left -= 2; ++ ++ if (count == 0 || left < count * RSN_SELECTOR_LEN) { ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("%s: ie count botch (pairwise), " ++ "count %u left %u", __FUNCTION__, count, left)); ++ return _FAIL; ++ } ++ ++ for (i = 0; i < count; i++) ++ { ++ *pairwise_cipher |= rtw_get_wpa2_cipher_suite(pos); ++ ++ pos += RSN_SELECTOR_LEN; ++ left -= RSN_SELECTOR_LEN; ++ } ++ ++ } ++ else if (left == 1) ++ { ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("%s: ie too short (for key mgmt)", __FUNCTION__)); ++ ++ return _FAIL; ++ } ++ ++ ++ return ret; ++ ++} ++ ++int rtw_get_sec_ie(u8 *in_ie,uint in_len,u8 *rsn_ie,u16 *rsn_len,u8 *wpa_ie,u16 *wpa_len) ++{ ++ u8 authmode, sec_idx, i; ++ u8 wpa_oui[4]={0x0,0x50,0xf2,0x01}; ++ uint cnt; ++ ++_func_enter_; ++ ++ //Search required WPA or WPA2 IE and copy to sec_ie[ ] ++ ++ cnt = (_TIMESTAMP_ + _BEACON_ITERVAL_ + _CAPABILITY_); ++ ++ sec_idx=0; ++ ++ while(cnt found WPS_IE.....\n"); ++ *wps_ielen = ie_ptr[1]+2; ++ match=_TRUE; ++ } ++ return match; ++} ++ ++/** ++ * rtw_get_wps_ie - Search WPS IE from a series of IEs ++ * @in_ie: Address of IEs to search ++ * @in_len: Length limit from in_ie ++ * @wps_ie: If not NULL and WPS IE is found, WPS IE will be copied to the buf starting from wps_ie ++ * @wps_ielen: If not NULL and WPS IE is found, will set to the length of the entire WPS IE ++ * ++ * Returns: The address of the WPS IE found, or NULL ++ */ ++u8 *rtw_get_wps_ie(u8 *in_ie, uint in_len, u8 *wps_ie, uint *wps_ielen) ++{ ++ uint cnt; ++ u8 *wpsie_ptr=NULL; ++ u8 eid, wps_oui[4]={0x0,0x50,0xf2,0x04}; ++ ++ if(wps_ielen) ++ *wps_ielen = 0; ++ ++ if(!in_ie || in_len<=0) ++ return wpsie_ptr; ++ ++ cnt = 0; ++ ++ while(cntwpa_ie = pos; ++ elems->wpa_ie_len = elen; ++ break; ++ case WME_OUI_TYPE: /* this is a Wi-Fi WME info. element */ ++ if (elen < 5) { ++ DBG_871X("short WME " ++ "information element ignored " ++ "(len=%lu)\n", ++ (unsigned long) elen); ++ return -1; ++ } ++ switch (pos[4]) { ++ case WME_OUI_SUBTYPE_INFORMATION_ELEMENT: ++ case WME_OUI_SUBTYPE_PARAMETER_ELEMENT: ++ elems->wme = pos; ++ elems->wme_len = elen; ++ break; ++ case WME_OUI_SUBTYPE_TSPEC_ELEMENT: ++ elems->wme_tspec = pos; ++ elems->wme_tspec_len = elen; ++ break; ++ default: ++ DBG_871X("unknown WME " ++ "information element ignored " ++ "(subtype=%d len=%lu)\n", ++ pos[4], (unsigned long) elen); ++ return -1; ++ } ++ break; ++ case 4: ++ /* Wi-Fi Protected Setup (WPS) IE */ ++ elems->wps_ie = pos; ++ elems->wps_ie_len = elen; ++ break; ++ default: ++ DBG_871X("Unknown Microsoft " ++ "information element ignored " ++ "(type=%d len=%lu)\n", ++ pos[3], (unsigned long) elen); ++ return -1; ++ } ++ break; ++ ++ case OUI_BROADCOM: ++ switch (pos[3]) { ++ case VENDOR_HT_CAPAB_OUI_TYPE: ++ elems->vendor_ht_cap = pos; ++ elems->vendor_ht_cap_len = elen; ++ break; ++ default: ++ DBG_871X("Unknown Broadcom " ++ "information element ignored " ++ "(type=%d len=%lu)\n", ++ pos[3], (unsigned long) elen); ++ return -1; ++ } ++ break; ++ ++ default: ++ DBG_871X("unknown vendor specific information " ++ "element ignored (vendor OUI %02x:%02x:%02x " ++ "len=%lu)\n", ++ pos[0], pos[1], pos[2], (unsigned long) elen); ++ return -1; ++ } ++ ++ return 0; ++ ++} ++ ++/** ++ * ieee802_11_parse_elems - Parse information elements in management frames ++ * @start: Pointer to the start of IEs ++ * @len: Length of IE buffer in octets ++ * @elems: Data structure for parsed elements ++ * @show_errors: Whether to show parsing errors in debug log ++ * Returns: Parsing result ++ */ ++ParseRes rtw_ieee802_11_parse_elems(u8 *start, uint len, ++ struct ieee802_11_elems *elems, ++ int show_errors) ++{ ++ uint left = len; ++ u8 *pos = start; ++ int unknown = 0; ++ ++ _rtw_memset(elems, 0, sizeof(*elems)); ++ ++ while (left >= 2) { ++ u8 id, elen; ++ ++ id = *pos++; ++ elen = *pos++; ++ left -= 2; ++ ++ if (elen > left) { ++ if (show_errors) { ++ DBG_871X("IEEE 802.11 element " ++ "parse failed (id=%d elen=%d " ++ "left=%lu)\n", ++ id, elen, (unsigned long) left); ++ } ++ return ParseFailed; ++ } ++ ++ switch (id) { ++ case WLAN_EID_SSID: ++ elems->ssid = pos; ++ elems->ssid_len = elen; ++ break; ++ case WLAN_EID_SUPP_RATES: ++ elems->supp_rates = pos; ++ elems->supp_rates_len = elen; ++ break; ++ case WLAN_EID_FH_PARAMS: ++ elems->fh_params = pos; ++ elems->fh_params_len = elen; ++ break; ++ case WLAN_EID_DS_PARAMS: ++ elems->ds_params = pos; ++ elems->ds_params_len = elen; ++ break; ++ case WLAN_EID_CF_PARAMS: ++ elems->cf_params = pos; ++ elems->cf_params_len = elen; ++ break; ++ case WLAN_EID_TIM: ++ elems->tim = pos; ++ elems->tim_len = elen; ++ break; ++ case WLAN_EID_IBSS_PARAMS: ++ elems->ibss_params = pos; ++ elems->ibss_params_len = elen; ++ break; ++ case WLAN_EID_CHALLENGE: ++ elems->challenge = pos; ++ elems->challenge_len = elen; ++ break; ++ case WLAN_EID_ERP_INFO: ++ elems->erp_info = pos; ++ elems->erp_info_len = elen; ++ break; ++ case WLAN_EID_EXT_SUPP_RATES: ++ elems->ext_supp_rates = pos; ++ elems->ext_supp_rates_len = elen; ++ break; ++ case WLAN_EID_VENDOR_SPECIFIC: ++ if (rtw_ieee802_11_parse_vendor_specific(pos, elen, ++ elems, ++ show_errors)) ++ unknown++; ++ break; ++ case WLAN_EID_RSN: ++ elems->rsn_ie = pos; ++ elems->rsn_ie_len = elen; ++ break; ++ case WLAN_EID_PWR_CAPABILITY: ++ elems->power_cap = pos; ++ elems->power_cap_len = elen; ++ break; ++ case WLAN_EID_SUPPORTED_CHANNELS: ++ elems->supp_channels = pos; ++ elems->supp_channels_len = elen; ++ break; ++ case WLAN_EID_MOBILITY_DOMAIN: ++ elems->mdie = pos; ++ elems->mdie_len = elen; ++ break; ++ case WLAN_EID_FAST_BSS_TRANSITION: ++ elems->ftie = pos; ++ elems->ftie_len = elen; ++ break; ++ case WLAN_EID_TIMEOUT_INTERVAL: ++ elems->timeout_int = pos; ++ elems->timeout_int_len = elen; ++ break; ++ case WLAN_EID_HT_CAP: ++ elems->ht_capabilities = pos; ++ elems->ht_capabilities_len = elen; ++ break; ++ case WLAN_EID_HT_OPERATION: ++ elems->ht_operation = pos; ++ elems->ht_operation_len = elen; ++ break; ++ default: ++ unknown++; ++ if (!show_errors) ++ break; ++ DBG_871X("IEEE 802.11 element parse " ++ "ignored unknown element (id=%d elen=%d)\n", ++ id, elen); ++ break; ++ } ++ ++ left -= elen; ++ pos += elen; ++ } ++ ++ if (left) ++ return ParseFailed; ++ ++ return unknown ? ParseUnknown : ParseOK; ++ ++} ++ ++u8 key_char2num(u8 ch) ++{ ++ if((ch>='0')&&(ch<='9')) ++ return ch - '0'; ++ else if ((ch>='a')&&(ch<='f')) ++ return ch - 'a' + 10; ++ else if ((ch>='A')&&(ch<='F')) ++ return ch - 'A' + 10; ++ else ++ return 0xff; ++} ++ ++u8 str_2char2num(u8 hch, u8 lch) ++{ ++ return ((key_char2num(hch) * 10 ) + key_char2num(lch)); ++} ++ ++u8 key_2char2num(u8 hch, u8 lch) ++{ ++ return ((key_char2num(hch) << 4) | key_char2num(lch)); ++} ++ ++extern char* rtw_initmac; ++void rtw_macaddr_cfg(u8 *mac_addr) ++{ ++ u8 mac[ETH_ALEN]; ++ if(mac_addr == NULL) return; ++ ++ if ( rtw_initmac ) ++ { // Users specify the mac address ++ int jj,kk; ++ ++ for( jj = 0, kk = 0; jj < ETH_ALEN; jj++, kk += 3 ) ++ { ++ mac[jj] = key_2char2num(rtw_initmac[kk], rtw_initmac[kk+ 1]); ++ } ++ _rtw_memcpy(mac_addr, mac, ETH_ALEN); ++ } ++ else ++ { // Use the mac address stored in the Efuse ++ _rtw_memcpy(mac, mac_addr, ETH_ALEN); ++ } ++ ++ if (((mac[0]==0xff) &&(mac[1]==0xff) && (mac[2]==0xff) && ++ (mac[3]==0xff) && (mac[4]==0xff) &&(mac[5]==0xff)) || ++ ((mac[0]==0x0) && (mac[1]==0x0) && (mac[2]==0x0) && ++ (mac[3]==0x0) && (mac[4]==0x0) &&(mac[5]==0x0))) ++ { ++ mac[0] = 0x00; ++ mac[1] = 0xe0; ++ mac[2] = 0x4c; ++ mac[3] = 0x87; ++ mac[4] = 0x00; ++ mac[5] = 0x00; ++ // use default mac addresss ++ _rtw_memcpy(mac_addr, mac, ETH_ALEN); ++ DBG_8192C("MAC Address from efuse error, assign default one !!!\n"); ++ } ++ ++ DBG_8192C("rtw_macaddr_cfg MAC Address = "MAC_FMT"\n", MAC_ARG(mac_addr)); ++} ++ ++void dump_ies(u8 *buf, u32 buf_len) { ++ u8* pos = (u8*)buf; ++ u8 id, len; ++ ++ while(pos-buf<=buf_len){ ++ id = *pos; ++ len = *(pos+1); ++ ++ DBG_871X("%s ID:%u, LEN:%u\n", __FUNCTION__, id, len); ++ #ifdef CONFIG_P2P ++ dump_p2p_ie(pos, len); ++ #endif ++ dump_wps_ie(pos, len); ++ ++ pos+=(2+len); ++ } ++} ++ ++void dump_wps_ie(u8 *ie, u32 ie_len) { ++ u8* pos = (u8*)ie; ++ u16 id; ++ u16 len; ++ ++ u8 *wps_ie; ++ uint wps_ielen; ++ ++ wps_ie = rtw_get_wps_ie(ie, ie_len, NULL, &wps_ielen); ++ if(wps_ie != ie || wps_ielen == 0) ++ return; ++ ++ pos+=6; ++ while(pos-ie < ie_len){ ++ id = RTW_GET_BE16(pos); ++ len = RTW_GET_BE16(pos + 2); ++ ++ DBG_871X("%s ID:0x%04x, LEN:%u\n", __FUNCTION__, id, len); ++ ++ pos+=(4+len); ++ } ++} ++ ++#ifdef CONFIG_P2P ++void dump_p2p_ie(u8 *ie, u32 ie_len) { ++ u8* pos = (u8*)ie; ++ u8 id; ++ u16 len; ++ ++ u8 *p2p_ie; ++ uint p2p_ielen; ++ ++ p2p_ie = rtw_get_p2p_ie(ie, ie_len, NULL, &p2p_ielen); ++ if(p2p_ie != ie || p2p_ielen == 0) ++ return; ++ ++ pos+=6; ++ while(pos-ie < ie_len){ ++ id = *pos; ++ len = RTW_GET_LE16(pos+1); ++ ++ DBG_871X("%s ID:%u, LEN:%u\n", __FUNCTION__, id, len); ++ ++ pos+=(3+len); ++ } ++} ++ ++/** ++ * rtw_get_p2p_ie - Search P2P IE from a series of IEs ++ * @in_ie: Address of IEs to search ++ * @in_len: Length limit from in_ie ++ * @p2p_ie: If not NULL and P2P IE is found, P2P IE will be copied to the buf starting from p2p_ie ++ * @p2p_ielen: If not NULL and P2P IE is found, will set to the length of the entire P2P IE ++ * ++ * Returns: The address of the P2P IE found, or NULL ++ */ ++u8 *rtw_get_p2p_ie(u8 *in_ie, uint in_len, u8 *p2p_ie, uint *p2p_ielen) ++{ ++ uint cnt = 0; ++ u8 *p2p_ie_ptr; ++ u8 eid, p2p_oui[4]={0x50,0x6F,0x9A,0x09}; ++ ++ if ( p2p_ielen != NULL ) ++ *p2p_ielen = 0; ++ ++ while(cnt0) ++ // dump_ies(ie, ielen); ++ break; ++ } ++ } ++ ++ return ielen; ++} ++ ++void rtw_WLAN_BSSID_EX_remove_p2p_attr(WLAN_BSSID_EX *bss_ex, u8 attr_id) ++{ ++ u8 *p2p_ie; ++ uint p2p_ielen, p2p_ielen_ori; ++ int cnt; ++ ++ if( (p2p_ie=rtw_get_p2p_ie(bss_ex->IEs+_FIXED_IE_LENGTH_, bss_ex->IELength-_FIXED_IE_LENGTH_, NULL, &p2p_ielen_ori)) ) ++ { ++ #if 0 ++ if(rtw_get_p2p_attr(p2p_ie, p2p_ielen_ori, attr_id, NULL, NULL)) { ++ DBG_871X("rtw_get_p2p_attr: GOT P2P_ATTR:%u!!!!!!!!\n", attr_id); ++ dump_ies(bss_ex->IEs+_FIXED_IE_LENGTH_, bss_ex->IELength-_FIXED_IE_LENGTH_); ++ } ++ #endif ++ ++ p2p_ielen=rtw_p2p_attr_remove(p2p_ie, p2p_ielen_ori, attr_id); ++ if(p2p_ielen != p2p_ielen_ori) { ++ ++ u8 *next_ie_ori = p2p_ie+p2p_ielen_ori; ++ u8 *next_ie = p2p_ie+p2p_ielen; ++ uint remain_len = bss_ex->IELength-(next_ie_ori-bss_ex->IEs); ++ ++ _rtw_memcpy(next_ie, next_ie_ori, remain_len); ++ _rtw_memset(next_ie+remain_len, 0, p2p_ielen_ori-p2p_ielen); ++ bss_ex->IELength -= p2p_ielen_ori-p2p_ielen; ++ ++ #if 0 ++ DBG_871X("remove P2P_ATTR:%u!\n", attr_id); ++ dump_ies(bss_ex->IEs+_FIXED_IE_LENGTH_, bss_ex->IELength-_FIXED_IE_LENGTH_); ++ #endif ++ } ++ } ++} ++ ++#ifdef CONFIG_WFD ++int rtw_get_wfd_ie(u8 *in_ie, uint in_len, u8 *wfd_ie, uint *wfd_ielen) ++{ ++ int match; ++ uint cnt = 0; ++ u8 eid, wfd_oui[4]={0x50,0x6F,0x9A,0x0A}; ++ ++ ++ match=_FALSE; ++ while(cnt 1 byte for attribute ID field, 2 bytes for length field ++ if(attr_content) ++ _rtw_memcpy( attr_content, &wfd_ie[ cnt + 3 ], attrlen ); ++ ++ if(attr_contentlen) ++ *attr_contentlen = attrlen; ++ ++ cnt += attrlen + 3; ++ ++ match = _TRUE; ++ break; ++ } ++ else ++ { ++ cnt += attrlen + 3; //goto next ++ } ++ ++ } ++ ++ return match; ++ ++} ++#endif // CONFIG_WFD ++#endif // CONFIG_P2P ++ +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/core/rtw_io.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/core/rtw_io.c 2013-07-26 19:36:04.000000000 +0000 +@@ -0,0 +1,490 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ++******************************************************************************/ ++/* ++ ++The purpose of rtw_io.c ++ ++a. provides the API ++ ++b. provides the protocol engine ++ ++c. provides the software interface between caller and the hardware interface ++ ++ ++Compiler Flag Option: ++ ++1. CONFIG_SDIO_HCI: ++ a. USE_SYNC_IRP: Only sync operations are provided. ++ b. USE_ASYNC_IRP:Both sync/async operations are provided. ++ ++2. CONFIG_USB_HCI: ++ a. USE_ASYNC_IRP: Both sync/async operations are provided. ++ ++3. CONFIG_CFIO_HCI: ++ b. USE_SYNC_IRP: Only sync operations are provided. ++ ++ ++Only sync read/rtw_write_mem operations are provided. ++ ++jackson@realtek.com.tw ++ ++*/ ++ ++#define _RTW_IO_C_ ++#include ++#include ++#include ++#include ++#include ++ ++#if defined (PLATFORM_LINUX) && defined (PLATFORM_WINDOWS) ++#error "Shall be Linux or Windows, but not both!\n" ++#endif ++ ++#ifdef CONFIG_SDIO_HCI ++#include ++#endif ++ ++#ifdef CONFIG_USB_HCI ++#include ++#endif ++ ++#ifdef CONFIG_PCI_HCI ++#include ++#endif ++ ++ ++u8 _rtw_read8(_adapter *adapter, u32 addr) ++{ ++ u8 r_val; ++ //struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue; ++ struct io_priv *pio_priv = &adapter->iopriv; ++ struct intf_hdl *pintfhdl = &(pio_priv->intf); ++ u8 (*_read8)(struct intf_hdl *pintfhdl, u32 addr); ++ _func_enter_; ++ _read8 = pintfhdl->io_ops._read8; ++ ++ r_val = _read8(pintfhdl, addr); ++ _func_exit_; ++ return r_val; ++} ++ ++u16 _rtw_read16(_adapter *adapter, u32 addr) ++{ ++ u16 r_val; ++ //struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue; ++ struct io_priv *pio_priv = &adapter->iopriv; ++ struct intf_hdl *pintfhdl = &(pio_priv->intf); ++ u16 (*_read16)(struct intf_hdl *pintfhdl, u32 addr); ++ _func_enter_; ++ _read16 = pintfhdl->io_ops._read16; ++ ++ r_val = _read16(pintfhdl, addr); ++ _func_exit_; ++ return r_val; ++} ++ ++u32 _rtw_read32(_adapter *adapter, u32 addr) ++{ ++ u32 r_val; ++ //struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue; ++ struct io_priv *pio_priv = &adapter->iopriv; ++ struct intf_hdl *pintfhdl = &(pio_priv->intf); ++ u32 (*_read32)(struct intf_hdl *pintfhdl, u32 addr); ++ _func_enter_; ++ _read32 = pintfhdl->io_ops._read32; ++ ++ r_val = _read32(pintfhdl, addr); ++ _func_exit_; ++ return r_val; ++ ++} ++ ++int _rtw_write8(_adapter *adapter, u32 addr, u8 val) ++{ ++ //struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue; ++ struct io_priv *pio_priv = &adapter->iopriv; ++ struct intf_hdl *pintfhdl = &(pio_priv->intf); ++ int (*_write8)(struct intf_hdl *pintfhdl, u32 addr, u8 val); ++ int ret; ++ _func_enter_; ++ _write8 = pintfhdl->io_ops._write8; ++ ++ ret = _write8(pintfhdl, addr, val); ++ _func_exit_; ++ ++ return RTW_STATUS_CODE(ret); ++} ++int _rtw_write16(_adapter *adapter, u32 addr, u16 val) ++{ ++ //struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue; ++ struct io_priv *pio_priv = &adapter->iopriv; ++ struct intf_hdl *pintfhdl = &(pio_priv->intf); ++ int (*_write16)(struct intf_hdl *pintfhdl, u32 addr, u16 val); ++ int ret; ++ _func_enter_; ++ _write16 = pintfhdl->io_ops._write16; ++ ++ ret = _write16(pintfhdl, addr, val); ++ _func_exit_; ++ ++ return RTW_STATUS_CODE(ret); ++} ++int _rtw_write32(_adapter *adapter, u32 addr, u32 val) ++{ ++ //struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue; ++ struct io_priv *pio_priv = &adapter->iopriv; ++ struct intf_hdl *pintfhdl = &(pio_priv->intf); ++ int (*_write32)(struct intf_hdl *pintfhdl, u32 addr, u32 val); ++ int ret; ++ _func_enter_; ++ _write32 = pintfhdl->io_ops._write32; ++ ++ ret = _write32(pintfhdl, addr, val); ++ _func_exit_; ++ ++ return RTW_STATUS_CODE(ret); ++} ++ ++int _rtw_writeN(_adapter *adapter, u32 addr ,u32 length , u8 *pdata) ++{ ++ //struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue; ++ struct io_priv *pio_priv = &adapter->iopriv; ++ struct intf_hdl *pintfhdl = (struct intf_hdl*)(&(pio_priv->intf)); ++ int (*_writeN)(struct intf_hdl *pintfhdl, u32 addr,u32 length, u8 *pdata); ++ int ret; ++ _func_enter_; ++ _writeN = pintfhdl->io_ops._writeN; ++ ++ ret = _writeN(pintfhdl, addr,length,pdata); ++ _func_exit_; ++ ++ return RTW_STATUS_CODE(ret); ++} ++int _rtw_write8_async(_adapter *adapter, u32 addr, u8 val) ++{ ++ //struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue; ++ struct io_priv *pio_priv = &adapter->iopriv; ++ struct intf_hdl *pintfhdl = &(pio_priv->intf); ++ int (*_write8_async)(struct intf_hdl *pintfhdl, u32 addr, u8 val); ++ int ret; ++ _func_enter_; ++ _write8_async = pintfhdl->io_ops._write8_async; ++ ++ ret = _write8_async(pintfhdl, addr, val); ++ _func_exit_; ++ ++ return RTW_STATUS_CODE(ret); ++} ++int _rtw_write16_async(_adapter *adapter, u32 addr, u16 val) ++{ ++ //struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue; ++ struct io_priv *pio_priv = &adapter->iopriv; ++ struct intf_hdl *pintfhdl = &(pio_priv->intf); ++ int (*_write16_async)(struct intf_hdl *pintfhdl, u32 addr, u16 val); ++ int ret; ++ _func_enter_; ++ _write16_async = pintfhdl->io_ops._write16_async; ++ ++ ret = _write16_async(pintfhdl, addr, val); ++ _func_exit_; ++ ++ return RTW_STATUS_CODE(ret); ++} ++int _rtw_write32_async(_adapter *adapter, u32 addr, u32 val) ++{ ++ //struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue; ++ struct io_priv *pio_priv = &adapter->iopriv; ++ struct intf_hdl *pintfhdl = &(pio_priv->intf); ++ int (*_write32_async)(struct intf_hdl *pintfhdl, u32 addr, u32 val); ++ int ret; ++ _func_enter_; ++ _write32_async = pintfhdl->io_ops._write32_async; ++ ++ ret = _write32_async(pintfhdl, addr, val); ++ _func_exit_; ++ ++ return RTW_STATUS_CODE(ret); ++} ++void _rtw_read_mem(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem) ++{ ++ void (*_read_mem)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem); ++ //struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue; ++ struct io_priv *pio_priv = &adapter->iopriv; ++ struct intf_hdl *pintfhdl = &(pio_priv->intf); ++ ++ _func_enter_; ++ ++ if( (adapter->bDriverStopped ==_TRUE) || (adapter->bSurpriseRemoved == _TRUE)) ++ { ++ RT_TRACE(_module_rtl871x_io_c_, _drv_info_, ("rtw_read_mem:bDriverStopped(%d) OR bSurpriseRemoved(%d)", adapter->bDriverStopped, adapter->bSurpriseRemoved)); ++ return; ++ } ++ ++ _read_mem = pintfhdl->io_ops._read_mem; ++ ++ _read_mem(pintfhdl, addr, cnt, pmem); ++ ++ _func_exit_; ++ ++} ++ ++void _rtw_write_mem(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem) ++{ ++ void (*_write_mem)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem); ++ //struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue; ++ struct io_priv *pio_priv = &adapter->iopriv; ++ struct intf_hdl *pintfhdl = &(pio_priv->intf); ++ ++ _func_enter_; ++ ++ _write_mem = pintfhdl->io_ops._write_mem; ++ ++ _write_mem(pintfhdl, addr, cnt, pmem); ++ ++ _func_exit_; ++ ++} ++ ++void _rtw_read_port(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem) ++{ ++ u32 (*_read_port)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem); ++ //struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue; ++ struct io_priv *pio_priv = &adapter->iopriv; ++ struct intf_hdl *pintfhdl = &(pio_priv->intf); ++ ++ _func_enter_; ++ ++ if( (adapter->bDriverStopped ==_TRUE) || (adapter->bSurpriseRemoved == _TRUE)) ++ { ++ RT_TRACE(_module_rtl871x_io_c_, _drv_info_, ("rtw_read_port:bDriverStopped(%d) OR bSurpriseRemoved(%d)", adapter->bDriverStopped, adapter->bSurpriseRemoved)); ++ return; ++ } ++ ++ _read_port = pintfhdl->io_ops._read_port; ++ ++ _read_port(pintfhdl, addr, cnt, pmem); ++ ++ _func_exit_; ++ ++} ++ ++void _rtw_read_port_cancel(_adapter *adapter) ++{ ++ void (*_read_port_cancel)(struct intf_hdl *pintfhdl); ++ struct io_priv *pio_priv = &adapter->iopriv; ++ struct intf_hdl *pintfhdl = &(pio_priv->intf); ++ ++ _read_port_cancel = pintfhdl->io_ops._read_port_cancel; ++ ++ if(_read_port_cancel) ++ _read_port_cancel(pintfhdl); ++ ++} ++ ++void _rtw_write_port(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem) ++{ ++ u32 (*_write_port)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem); ++ //struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue; ++ struct io_priv *pio_priv = &adapter->iopriv; ++ struct intf_hdl *pintfhdl = &(pio_priv->intf); ++ ++ _func_enter_; ++ ++ _write_port = pintfhdl->io_ops._write_port; ++ ++ _write_port(pintfhdl, addr, cnt, pmem); ++ ++ _func_exit_; ++ ++} ++ ++int _rtw_write_port_sync(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem) ++{ ++ int (*_write_port_sync)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem); ++ //struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue; ++ struct io_priv *pio_priv = &adapter->iopriv; ++ struct intf_hdl *pintfhdl = &(pio_priv->intf); ++ int ret = _SUCCESS; ++ ++ _func_enter_; ++ ++ _write_port_sync = pintfhdl->io_ops._write_port_sync; ++ ++ if(_write_port_sync) ++ ret = _write_port_sync(pintfhdl, addr, cnt, pmem); ++ else ++ ret = _FAIL; ++ ++ _func_exit_; ++ ++ return ret; ++} ++ ++void _rtw_write_port_cancel(_adapter *adapter) ++{ ++ void (*_write_port_cancel)(struct intf_hdl *pintfhdl); ++ struct io_priv *pio_priv = &adapter->iopriv; ++ struct intf_hdl *pintfhdl = &(pio_priv->intf); ++ ++ _write_port_cancel = pintfhdl->io_ops._write_port_cancel; ++ ++ if(_write_port_cancel) ++ _write_port_cancel(pintfhdl); ++ ++} ++ ++ ++void _rtw_attrib_read(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem){ ++#ifdef CONFIG_SDIO_HCI ++ void (*_attrib_read)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem); ++ ++ //struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue; ++ struct io_priv *pio_priv = &adapter->iopriv; ++ struct intf_hdl *pintfhdl = &(pio_priv->intf); ++ ++ _func_enter_; ++ ++ _attrib_read= pintfhdl->io_ops._attrib_read; ++ ++ _attrib_read(pintfhdl, addr, cnt, pmem); ++ ++ _func_exit_; ++#endif ++} ++ ++void _rtw_attrib_write(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem){ ++#ifdef CONFIG_SDIO_HCI ++ void (*_attrib_write)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem); ++ ++ //struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue; ++ struct io_priv *pio_priv = &adapter->iopriv; ++ struct intf_hdl *pintfhdl = &(pio_priv->intf); ++ ++ _func_enter_; ++ ++ _attrib_write= pintfhdl->io_ops._attrib_write; ++ ++ _attrib_write(pintfhdl, addr, cnt, pmem); ++ ++ _func_exit_; ++ ++#endif ++} ++ ++int rtw_init_io_priv(_adapter *padapter) ++{ ++ void (*set_intf_ops)(struct _io_ops *pops); ++ struct io_priv *piopriv = &padapter->iopriv; ++ struct intf_hdl *pintf = &piopriv->intf; ++ ++ piopriv->padapter = padapter; ++ pintf->padapter = padapter; ++ pintf->pintf_dev = &padapter->dvobjpriv; ++ ++ ++#ifdef CONFIG_SDIO_HCI ++ set_intf_ops = &sdio_set_intf_ops; ++#endif //END OF CONFIG_SDIO_HCI ++ ++ ++#ifdef CONFIG_USB_HCI ++ ++ if(padapter->chip_type == RTL8188C_8192C) ++ { ++#ifdef CONFIG_RTL8192C ++ set_intf_ops = &rtl8192cu_set_intf_ops; ++#endif ++ } ++ else if(padapter->chip_type == RTL8192D) ++ { ++#ifdef CONFIG_RTL8192D ++ set_intf_ops = &rtl8192du_set_intf_ops; ++#endif ++ } ++ else ++ { ++ set_intf_ops = NULL; ++ } ++#endif //END OF CONFIG_USB_HCI ++ ++#ifdef CONFIG_PCI_HCI ++ ++ if(padapter->chip_type == RTL8188C_8192C) ++ { ++#ifdef CONFIG_RTL8192C ++ set_intf_ops = &rtl8192ce_set_intf_ops; ++#endif ++ } ++ else if(padapter->chip_type == RTL8192D) ++ { ++#ifdef CONFIG_RTL8192D ++ set_intf_ops = &rtl8192de_set_intf_ops; ++#endif ++ } ++ else ++ { ++ set_intf_ops = NULL; ++ } ++#endif //END OF CONFIG_PCI_HCI ++ ++ ++ if(set_intf_ops==NULL) ++ return _FAIL; ++ ++ set_intf_ops(&pintf->io_ops); ++ ++ return _SUCCESS; ++ ++} ++ ++#ifdef DBG_IO ++int dbg_rtw_write8(_adapter *adapter, u32 addr, u8 val, const char *caller, const int line) ++{ ++ if(addr + 1 > DBG_IO_WRITE_SNIFF_ADDR_START && addr <= DBG_IO_WRITE_SNIFF_ADDR_END) ++ DBG_871X("DBG_IO %s:%d rtw_write8(0x%04x, 0x%02x)\n", caller, line, addr, val); ++ ++ return _rtw_write8(adapter, addr, val); ++} ++int dbg_rtw_write16(_adapter *adapter, u32 addr, u16 val, const char *caller, const int line) ++{ ++ if(addr + 2 > DBG_IO_WRITE_SNIFF_ADDR_START && addr <= DBG_IO_WRITE_SNIFF_ADDR_END) ++ DBG_871X("DBG_IO %s:%d rtw_write16(0x%04x, 0x%04x)\n", caller, line, addr, val); ++ ++ return _rtw_write16(adapter, addr, val); ++} ++int dbg_rtw_write32(_adapter *adapter, u32 addr, u32 val, const char *caller, const int line) ++{ ++ if(addr + 4 > DBG_IO_WRITE_SNIFF_ADDR_START && addr <= DBG_IO_WRITE_SNIFF_ADDR_END) ++ DBG_871X("DBG_IO %s:%d rtw_write32(0x%04x, 0x%08x)\n", caller, line, addr, val); ++ ++ return _rtw_write32(adapter, addr, val); ++} ++int dbg_rtw_writeN(_adapter *adapter, u32 addr ,u32 length , u8 *data, const char *caller, const int line) ++{ ++ if(addr + length> DBG_IO_WRITE_SNIFF_ADDR_START && addr <= DBG_IO_WRITE_SNIFF_ADDR_END) ++ DBG_871X("DBG_IO %s:%d rtw_writeN(0x%04x, %u)\n", caller, line, addr, length); ++ ++ return _rtw_writeN(adapter, addr, length, data); ++} ++#endif ++ ++ +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/core/rtw_ioctl_query.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/core/rtw_ioctl_query.c 2013-07-26 19:36:04.000000000 +0000 +@@ -0,0 +1,197 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ++******************************************************************************/ ++#define _RTW_IOCTL_QUERY_C_ ++ ++#include ++#include ++#include ++#include ++#include ++ ++ ++#ifdef PLATFORM_WINDOWS ++// ++// Added for WPA2-PSK, by Annie, 2005-09-20. ++// ++u8 ++query_802_11_capability( ++ _adapter* Adapter, ++ u8* pucBuf, ++ u32 * pulOutLen ++) ++{ ++ static NDIS_802_11_AUTHENTICATION_ENCRYPTION szAuthEnc[] = ++ { ++ {Ndis802_11AuthModeOpen, Ndis802_11EncryptionDisabled}, ++ {Ndis802_11AuthModeOpen, Ndis802_11Encryption1Enabled}, ++ {Ndis802_11AuthModeShared, Ndis802_11EncryptionDisabled}, ++ {Ndis802_11AuthModeShared, Ndis802_11Encryption1Enabled}, ++ {Ndis802_11AuthModeWPA, Ndis802_11Encryption2Enabled}, ++ {Ndis802_11AuthModeWPA, Ndis802_11Encryption3Enabled}, ++ {Ndis802_11AuthModeWPAPSK, Ndis802_11Encryption2Enabled}, ++ {Ndis802_11AuthModeWPAPSK, Ndis802_11Encryption3Enabled}, ++ {Ndis802_11AuthModeWPANone, Ndis802_11Encryption2Enabled}, ++ {Ndis802_11AuthModeWPANone, Ndis802_11Encryption3Enabled}, ++ {Ndis802_11AuthModeWPA2, Ndis802_11Encryption2Enabled}, ++ {Ndis802_11AuthModeWPA2, Ndis802_11Encryption3Enabled}, ++ {Ndis802_11AuthModeWPA2PSK, Ndis802_11Encryption2Enabled}, ++ {Ndis802_11AuthModeWPA2PSK, Ndis802_11Encryption3Enabled} ++ }; ++ static ULONG ulNumOfPairSupported = sizeof(szAuthEnc)/sizeof(NDIS_802_11_AUTHENTICATION_ENCRYPTION); ++ NDIS_802_11_CAPABILITY * pCap = (NDIS_802_11_CAPABILITY *)pucBuf; ++ u8* pucAuthEncryptionSupported = (u8*) pCap->AuthenticationEncryptionSupported; ++ ++ ++ pCap->Length = sizeof(NDIS_802_11_CAPABILITY); ++ if(ulNumOfPairSupported > 1 ) ++ pCap->Length += (ulNumOfPairSupported-1) * sizeof(NDIS_802_11_AUTHENTICATION_ENCRYPTION); ++ ++ pCap->Version = 2; ++ pCap->NoOfPMKIDs = NUM_PMKID_CACHE; ++ pCap->NoOfAuthEncryptPairsSupported = ulNumOfPairSupported; ++ ++ if( sizeof (szAuthEnc) <= 240 ) // 240 = 256 - 4*4 // SecurityInfo.szCapability: only 256 bytes in size. ++ { ++ _rtw_memcpy( pucAuthEncryptionSupported, (u8*)szAuthEnc, sizeof (szAuthEnc) ); ++ *pulOutLen = pCap->Length; ++ return _TRUE; ++ } ++ else ++ { ++ *pulOutLen = 0; ++ RT_TRACE(_module_rtl871x_ioctl_query_c_,_drv_info_,("_query_802_11_capability(): szAuthEnc size is too large.\n")); ++ return _FALSE; ++ } ++} ++ ++u8 query_802_11_association_information( _adapter *padapter,PNDIS_802_11_ASSOCIATION_INFORMATION pAssocInfo) ++{ ++ struct wlan_network *tgt_network; ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ struct security_priv *psecuritypriv=&(padapter->securitypriv); ++ WLAN_BSSID_EX *psecnetwork=(WLAN_BSSID_EX*)&(psecuritypriv->sec_bss); ++ u8 * pDest = (u8 *)pAssocInfo + sizeof(NDIS_802_11_ASSOCIATION_INFORMATION); ++ unsigned char i,*auth_ie,*supp_ie; ++ ++ //NdisZeroMemory(pAssocInfo, sizeof(NDIS_802_11_ASSOCIATION_INFORMATION)); ++ _rtw_memset(pAssocInfo, 0, sizeof(NDIS_802_11_ASSOCIATION_INFORMATION)); ++ //pAssocInfo->Length = sizeof(NDIS_802_11_ASSOCIATION_INFORMATION); ++ ++ //------------------------------------------------------ ++ // Association Request related information ++ //------------------------------------------------------ ++ // Req_1. AvailableRequestFixedIEs ++ if(psecnetwork!=NULL){ ++ ++ pAssocInfo->AvailableRequestFixedIEs |= NDIS_802_11_AI_REQFI_CAPABILITIES|NDIS_802_11_AI_REQFI_CURRENTAPADDRESS; ++ pAssocInfo->RequestFixedIEs.Capabilities = (unsigned short)* & psecnetwork->IEs[10]; ++ _rtw_memcpy(pAssocInfo->RequestFixedIEs.CurrentAPAddress, ++ & psecnetwork->MacAddress, 6); ++ ++ pAssocInfo->OffsetRequestIEs = sizeof(NDIS_802_11_ASSOCIATION_INFORMATION); ++ ++ if(check_fwstate( pmlmepriv, _FW_UNDER_LINKING|_FW_LINKED)==_TRUE) ++ { ++ ++ if(psecuritypriv->ndisauthtype>=Ndis802_11AuthModeWPA2) ++ pDest[0] =48; //RSN Information Element ++ else ++ pDest[0] =221; //WPA(SSN) Information Element ++ ++ RT_TRACE(_module_rtl871x_ioctl_query_c_,_drv_info_,("\n Adapter->ndisauthtype==Ndis802_11AuthModeWPA)?0xdd:0x30 [%d]",pDest[0])); ++ supp_ie=&psecuritypriv->supplicant_ie[0]; ++ for(i=0;inetwork.IELength=%d\n\n", i,(int)psecnetwork->IELength)); ++ while((iRequestIELength += (2 + supp_ie[1+i]);// (2 + psecnetwork->IEs[1+i]+4); ++ ++ } ++ ++ ++ RT_TRACE(_module_rtl871x_ioctl_query_c_,_drv_info_,("\n psecnetwork != NULL,fwstate==_FW_UNDER_LINKING \n")); ++ ++ } ++ ++ ++ //------------------------------------------------------ ++ // Association Response related information ++ //------------------------------------------------------ ++ ++ if(check_fwstate( pmlmepriv, _FW_LINKED)==_TRUE) ++ { ++ tgt_network =&(pmlmepriv->cur_network); ++ if(tgt_network!=NULL){ ++ pAssocInfo->AvailableResponseFixedIEs = ++ NDIS_802_11_AI_RESFI_CAPABILITIES ++ |NDIS_802_11_AI_RESFI_ASSOCIATIONID ++ ; ++ ++ pAssocInfo->ResponseFixedIEs.Capabilities =(unsigned short)* & tgt_network->network.IEs[10]; ++ pAssocInfo->ResponseFixedIEs.StatusCode = 0; ++ pAssocInfo->ResponseFixedIEs.AssociationId =(unsigned short) tgt_network->aid; ++ ++ pDest = (u8 *)pAssocInfo + sizeof(NDIS_802_11_ASSOCIATION_INFORMATION)+pAssocInfo->RequestIELength; ++ auth_ie=&psecuritypriv->authenticator_ie[0]; ++ ++ for(i=0;i0){ ++ _rtw_memcpy((u8 *)&pDest[0],&auth_ie[1],i); ++ pAssocInfo->ResponseIELength =i; ++ } ++ ++ ++ pAssocInfo->OffsetResponseIEs = sizeof(NDIS_802_11_ASSOCIATION_INFORMATION) + pAssocInfo->RequestIELength; ++ ++ ++ RT_TRACE(_module_rtl871x_ioctl_query_c_,_drv_info_,("\n tgt_network != NULL,fwstate==_FW_LINKED \n")); ++ } ++ } ++ RT_TRACE(_module_rtl871x_ioctl_query_c_,_drv_info_,("\n exit query_802_11_association_information \n")); ++_func_exit_; ++ ++ return _TRUE; ++} ++#endif ++ +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/core/rtw_ioctl_rtl.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/core/rtw_ioctl_rtl.c 2013-07-26 19:36:04.000000000 +0000 +@@ -0,0 +1,1032 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ++******************************************************************************/ ++#define _RTW_IOCTL_RTL_C_ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#ifdef CONFIG_MP_INCLUDED ++#include ++#include ++#endif ++ ++struct oid_obj_priv oid_rtl_seg_01_01[] = ++{ ++ {1, &oid_null_function}, //0x80 ++ {1, &oid_null_function}, //0x81 ++ {1, &oid_null_function}, //0x82 ++ {1, &oid_null_function}, //0x83//OID_RT_SET_SNIFFER_MODE ++ {1, &oid_rt_get_signal_quality_hdl}, //0x84 ++ {1, &oid_rt_get_small_packet_crc_hdl}, //0x85 ++ {1, &oid_rt_get_middle_packet_crc_hdl}, //0x86 ++ {1, &oid_rt_get_large_packet_crc_hdl}, //0x87 ++ {1, &oid_rt_get_tx_retry_hdl}, //0x88 ++ {1, &oid_rt_get_rx_retry_hdl}, //0x89 ++ {1, &oid_rt_pro_set_fw_dig_state_hdl}, //0x8A ++ {1, &oid_rt_pro_set_fw_ra_state_hdl} , //0x8B ++ {1, &oid_null_function}, //0x8C ++ {1, &oid_null_function}, //0x8D ++ {1, &oid_null_function}, //0x8E ++ {1, &oid_null_function}, //0x8F ++ {1, &oid_rt_get_rx_total_packet_hdl}, //0x90 ++ {1, &oid_rt_get_tx_beacon_ok_hdl}, //0x91 ++ {1, &oid_rt_get_tx_beacon_err_hdl}, //0x92 ++ {1, &oid_rt_get_rx_icv_err_hdl}, //0x93 ++ {1, &oid_rt_set_encryption_algorithm_hdl}, //0x94 ++ {1, &oid_null_function}, //0x95 ++ {1, &oid_rt_get_preamble_mode_hdl}, //0x96 ++ {1, &oid_null_function}, //0x97 ++ {1, &oid_rt_get_ap_ip_hdl}, //0x98 ++ {1, &oid_rt_get_channelplan_hdl}, //0x99 ++ {1, &oid_rt_set_preamble_mode_hdl}, //0x9A ++ {1, &oid_rt_set_bcn_intvl_hdl}, //0x9B ++ {1, &oid_null_function}, //0x9C ++ {1, &oid_rt_dedicate_probe_hdl}, //0x9D ++ {1, &oid_null_function}, //0x9E ++ {1, &oid_null_function}, //0x9F ++ {1, &oid_null_function}, //0xA0 ++ {1, &oid_null_function}, //0xA1 ++ {1, &oid_null_function}, //0xA2 ++ {1, &oid_null_function}, //0xA3 ++ {1, &oid_null_function}, //0xA4 ++ {1, &oid_null_function}, //0xA5 ++ {1, &oid_null_function}, //0xA6 ++ {1, &oid_rt_get_total_tx_bytes_hdl}, //0xA7 ++ {1, &oid_rt_get_total_rx_bytes_hdl}, //0xA8 ++ {1, &oid_rt_current_tx_power_level_hdl}, //0xA9 ++ {1, &oid_rt_get_enc_key_mismatch_count_hdl}, //0xAA ++ {1, &oid_rt_get_enc_key_match_count_hdl}, //0xAB ++ {1, &oid_rt_get_channel_hdl}, //0xAC ++ {1, &oid_rt_set_channelplan_hdl}, //0xAD ++ {1, &oid_rt_get_hardware_radio_off_hdl}, //0xAE ++ {1, &oid_null_function}, //0xAF ++ {1, &oid_null_function}, //0xB0 ++ {1, &oid_null_function}, //0xB1 ++ {1, &oid_null_function}, //0xB2 ++ {1, &oid_null_function}, //0xB3 ++ {1, &oid_rt_get_key_mismatch_hdl}, //0xB4 ++ {1, &oid_null_function}, //0xB5 ++ {1, &oid_null_function}, //0xB6 ++ {1, &oid_null_function}, //0xB7 ++ {1, &oid_null_function}, //0xB8 ++ {1, &oid_null_function}, //0xB9 ++ {1, &oid_null_function}, //0xBA ++ {1, &oid_rt_supported_wireless_mode_hdl}, //0xBB ++ {1, &oid_rt_get_channel_list_hdl}, //0xBC ++ {1, &oid_rt_get_scan_in_progress_hdl}, //0xBD ++ {1, &oid_null_function}, //0xBE ++ {1, &oid_null_function}, //0xBF ++ {1, &oid_null_function}, //0xC0 ++ {1, &oid_rt_forced_data_rate_hdl}, //0xC1 ++ {1, &oid_rt_wireless_mode_for_scan_list_hdl}, //0xC2 ++ {1, &oid_rt_get_bss_wireless_mode_hdl}, //0xC3 ++ {1, &oid_rt_scan_with_magic_packet_hdl}, //0xC4 ++ {1, &oid_null_function}, //0xC5 ++ {1, &oid_null_function}, //0xC6 ++ {1, &oid_null_function}, //0xC7 ++ {1, &oid_null_function}, //0xC8 ++ {1, &oid_null_function}, //0xC9 ++ {1, &oid_null_function}, //0xCA ++ {1, &oid_null_function}, //0xCB ++ {1, &oid_null_function}, //0xCC ++ {1, &oid_null_function}, //0xCD ++ {1, &oid_null_function}, //0xCE ++ {1, &oid_null_function}, //0xCF ++ ++}; ++ ++struct oid_obj_priv oid_rtl_seg_01_03[] = ++{ ++ {1, &oid_rt_ap_get_associated_station_list_hdl}, //0x00 ++ {1, &oid_null_function}, //0x01 ++ {1, &oid_rt_ap_switch_into_ap_mode_hdl}, //0x02 ++ {1, &oid_null_function}, //0x03 ++ {1, &oid_rt_ap_supported_hdl}, //0x04 ++ {1, &oid_rt_ap_set_passphrase_hdl}, //0x05 ++ ++}; ++ ++struct oid_obj_priv oid_rtl_seg_01_11[] = ++{ ++ {1, &oid_null_function}, //0xC0 OID_RT_PRO_RX_FILTER ++ {1, &oid_null_function}, //0xC1 OID_CE_USB_WRITE_REGISTRY ++ {1, &oid_null_function}, //0xC2 OID_CE_USB_READ_REGISTRY ++ {1, &oid_null_function}, //0xC3 OID_RT_PRO_SET_INITIAL_GAIN ++ {1, &oid_null_function}, //0xC4 OID_RT_PRO_SET_BB_RF_STANDBY_MODE ++ {1, &oid_null_function}, //0xC5 OID_RT_PRO_SET_BB_RF_SHUTDOWN_MODE ++ {1, &oid_null_function}, //0xC6 OID_RT_PRO_SET_TX_CHARGE_PUMP ++ {1, &oid_null_function}, //0xC7 OID_RT_PRO_SET_RX_CHARGE_PUMP ++ {1, &oid_rt_pro_rf_write_registry_hdl}, //0xC8 ++ {1, &oid_rt_pro_rf_read_registry_hdl}, //0xC9 ++ {1, &oid_null_function} //0xCA OID_RT_PRO_QUERY_RF_TYPE ++ ++}; ++ ++struct oid_obj_priv oid_rtl_seg_03_00[] = ++{ ++ {1, &oid_null_function}, //0x00 ++ {1, &oid_rt_get_connect_state_hdl}, //0x01 ++ {1, &oid_null_function}, //0x02 ++ {1, &oid_null_function}, //0x03 ++ {1, &oid_rt_set_default_key_id_hdl}, //0x04 ++ ++ ++}; ++ ++ ++//************** oid_rtl_seg_01_01 section start ************** ++ ++NDIS_STATUS oid_rt_pro_set_fw_dig_state_hdl(struct oid_par_priv* poid_par_priv) ++{ ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++#if 0 ++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); ++ _irqL oldirql; ++ ++ _func_enter_; ++ ++ if(poid_par_priv->type_of_oid != SET_OID) ++ { ++ status = NDIS_STATUS_NOT_ACCEPTED; ++ return status; ++ } ++ ++ _irqlevel_changed_(&oldirql,LOWER); ++ if(poid_par_priv->information_buf_len >= sizeof(struct setdig_parm)) ++ { ++ //DEBUG_ERR(("===> oid_rt_pro_set_fw_dig_state_hdl. type:0x%02x.\n",*((unsigned char*)poid_par_priv->information_buf ))); ++ if(!rtw_setfwdig_cmd(Adapter,*((unsigned char*)poid_par_priv->information_buf ))) ++ { ++ status = NDIS_STATUS_NOT_ACCEPTED; ++ } ++ ++ } ++ else{ ++ status = NDIS_STATUS_NOT_ACCEPTED; ++ } ++ _irqlevel_changed_(&oldirql,RAISE); ++ _func_exit_; ++#endif ++ return status; ++} ++//----------------------------------------------------------------------------- ++NDIS_STATUS oid_rt_pro_set_fw_ra_state_hdl(struct oid_par_priv* poid_par_priv) ++{ ++ ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++#if 0 ++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); ++ _irqL oldirql; ++ ++ _func_enter_; ++ if(poid_par_priv->type_of_oid != SET_OID) ++ { ++ status = NDIS_STATUS_NOT_ACCEPTED; ++ return status; ++ } ++ ++ ++ _irqlevel_changed_(&oldirql,LOWER); ++ ++ if(poid_par_priv->information_buf_len >= sizeof(struct setra_parm)) ++ { ++ //DEBUG_ERR(("===> oid_rt_pro_set_fw_ra_state_hdl. type:0x%02x.\n",*((unsigned char*)poid_par_priv->information_buf ))); ++ if(!rtw_setfwra_cmd(Adapter,*((unsigned char*)poid_par_priv->information_buf ))) ++ { ++ status = NDIS_STATUS_NOT_ACCEPTED; ++ } ++ ++ } ++ else{ ++ status = NDIS_STATUS_NOT_ACCEPTED; ++ } ++ _irqlevel_changed_(&oldirql,RAISE); ++ _func_exit_; ++#endif ++ return status; ++} ++//----------------------------------------------------------------------------- ++NDIS_STATUS oid_rt_get_signal_quality_hdl(struct oid_par_priv* poid_par_priv) ++{ ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++ //DEBUG_ERR(("<**********************oid_rt_get_signal_quality_hdl \n")); ++ if(poid_par_priv->type_of_oid != QUERY_OID) ++ { ++ status = NDIS_STATUS_NOT_ACCEPTED; ++ return status; ++ } ++ ++#if 0 ++ if(pMgntInfo->mAssoc || pMgntInfo->mIbss) ++ { ++ ulInfo = pAdapter->RxStats.SignalQuality; ++ *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; ++ } ++ else ++ { ++ ulInfo = 0xffffffff; // It stands for -1 in 4-byte integer. ++ } ++ break; ++#endif ++ ++ return status; ++} ++ ++//------------------------------------------------------------------------------ ++ ++NDIS_STATUS oid_rt_get_small_packet_crc_hdl(struct oid_par_priv* poid_par_priv) ++{ ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++ if(poid_par_priv->type_of_oid != QUERY_OID) ++ { ++ status = NDIS_STATUS_NOT_ACCEPTED; ++ return status; ++ } ++ ++ if(poid_par_priv->information_buf_len >= sizeof(ULONG) ) ++ { ++ *(ULONG *)poid_par_priv->information_buf = padapter->recvpriv.rx_smallpacket_crcerr; ++ *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; ++ } ++ else ++ { ++ status = NDIS_STATUS_INVALID_LENGTH; ++ } ++ ++ return status; ++} ++//------------------------------------------------------------------------------ ++NDIS_STATUS oid_rt_get_middle_packet_crc_hdl(struct oid_par_priv* poid_par_priv) ++{ ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++ if(poid_par_priv->type_of_oid != QUERY_OID) ++ { ++ status = NDIS_STATUS_NOT_ACCEPTED; ++ return status; ++ } ++ ++ if(poid_par_priv->information_buf_len >= sizeof(ULONG) ) ++ { ++ *(ULONG *)poid_par_priv->information_buf = padapter->recvpriv.rx_middlepacket_crcerr; ++ *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; ++ } ++ else ++ { ++ status = NDIS_STATUS_INVALID_LENGTH; ++ } ++ ++ ++ return status; ++} ++//------------------------------------------------------------------------------ ++NDIS_STATUS oid_rt_get_large_packet_crc_hdl(struct oid_par_priv* poid_par_priv) ++{ ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++ if(poid_par_priv->type_of_oid != QUERY_OID) ++ { ++ status = NDIS_STATUS_NOT_ACCEPTED; ++ return status; ++ } ++ ++ if(poid_par_priv->information_buf_len >= sizeof(ULONG) ) ++ { ++ *(ULONG *)poid_par_priv->information_buf = padapter->recvpriv.rx_largepacket_crcerr; ++ *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; ++ } ++ else ++ { ++ status = NDIS_STATUS_INVALID_LENGTH; ++ } ++ ++ ++ return status; ++} ++ ++//------------------------------------------------------------------------------ ++NDIS_STATUS oid_rt_get_tx_retry_hdl(struct oid_par_priv* poid_par_priv) ++{ ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++ if(poid_par_priv->type_of_oid != QUERY_OID) ++ { ++ status = NDIS_STATUS_NOT_ACCEPTED; ++ return status; ++ } ++ ++ return status; ++} ++NDIS_STATUS oid_rt_get_rx_retry_hdl(struct oid_par_priv* poid_par_priv) ++{ ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++ if(poid_par_priv->type_of_oid != QUERY_OID) ++ { ++ status = NDIS_STATUS_NOT_ACCEPTED; ++ return status; ++ } ++ *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; ++ return status; ++} ++//------------------------------------------------------------------------------ ++NDIS_STATUS oid_rt_get_rx_total_packet_hdl(struct oid_par_priv* poid_par_priv) ++{ ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++ if(poid_par_priv->type_of_oid != QUERY_OID) ++ { ++ status = NDIS_STATUS_NOT_ACCEPTED; ++ return status; ++ } ++ if(poid_par_priv->information_buf_len >= sizeof(ULONG) ) ++ { ++ *(u64 *)poid_par_priv->information_buf = padapter->recvpriv.rx_pkts + padapter->recvpriv.rx_drop; ++ *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; ++ } ++ else ++ { ++ status = NDIS_STATUS_INVALID_LENGTH; ++ } ++ ++ ++ return status; ++} ++//------------------------------------------------------------------------------ ++NDIS_STATUS oid_rt_get_tx_beacon_ok_hdl(struct oid_par_priv* poid_par_priv) ++{ ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++ if(poid_par_priv->type_of_oid != QUERY_OID) ++ { ++ status = NDIS_STATUS_NOT_ACCEPTED; ++ return status; ++ } ++ ++ return status; ++} ++NDIS_STATUS oid_rt_get_tx_beacon_err_hdl(struct oid_par_priv* poid_par_priv) ++{ ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++ if(poid_par_priv->type_of_oid != QUERY_OID) ++ { ++ status = NDIS_STATUS_NOT_ACCEPTED; ++ return status; ++ } ++ ++ return status; ++} ++//------------------------------------------------------------------------------ ++NDIS_STATUS oid_rt_get_rx_icv_err_hdl(struct oid_par_priv* poid_par_priv) ++{ ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++ if(poid_par_priv->type_of_oid != QUERY_OID) ++ { ++ status = NDIS_STATUS_NOT_ACCEPTED; ++ return status; ++ } ++ if(poid_par_priv->information_buf_len>= sizeof(u32)) ++ { ++ //_rtw_memcpy(*(uint *)poid_par_priv->information_buf,padapter->recvpriv.rx_icv_err,sizeof(u32)); ++ *(uint *)poid_par_priv->information_buf = padapter->recvpriv.rx_icv_err; ++ *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; ++ } ++ else ++ { ++ status = NDIS_STATUS_INVALID_LENGTH ; ++ } ++ ++ ++ return status; ++} ++//------------------------------------------------------------------------------ ++NDIS_STATUS oid_rt_set_encryption_algorithm_hdl(struct oid_par_priv* poid_par_priv) ++{ ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++ if(poid_par_priv->type_of_oid != SET_OID) ++ { ++ status = NDIS_STATUS_NOT_ACCEPTED; ++ return status; ++ } ++ ++ return status; ++} ++//------------------------------------------------------------------------------ ++NDIS_STATUS oid_rt_get_preamble_mode_hdl(struct oid_par_priv* poid_par_priv) ++{ ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ULONG preamblemode = 0 ; ++ ++ if(poid_par_priv->type_of_oid != QUERY_OID) ++ { ++ status = NDIS_STATUS_NOT_ACCEPTED; ++ return status; ++ } ++ if(poid_par_priv->information_buf_len>= sizeof(ULONG)) ++ { ++ if(padapter->registrypriv.preamble == PREAMBLE_LONG) ++ preamblemode = 0; ++ else if (padapter->registrypriv.preamble == PREAMBLE_AUTO) ++ preamblemode = 1; ++ else if (padapter->registrypriv.preamble == PREAMBLE_SHORT) ++ preamblemode = 2; ++ ++ ++ *(ULONG *)poid_par_priv->information_buf = preamblemode ; ++ *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; ++ } ++ else ++ { ++ status = NDIS_STATUS_INVALID_LENGTH ; ++ } ++ return status; ++} ++//------------------------------------------------------------------------------ ++NDIS_STATUS oid_rt_get_ap_ip_hdl(struct oid_par_priv* poid_par_priv) ++{ ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++ if(poid_par_priv->type_of_oid != QUERY_OID) ++ { ++ status = NDIS_STATUS_NOT_ACCEPTED; ++ return status; ++ } ++ ++ return status; ++} ++ ++NDIS_STATUS oid_rt_get_channelplan_hdl(struct oid_par_priv* poid_par_priv) ++{ ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); ++ struct eeprom_priv* peeprompriv = &padapter->eeprompriv; ++ ++ if(poid_par_priv->type_of_oid != QUERY_OID) ++ { ++ status = NDIS_STATUS_NOT_ACCEPTED; ++ return status; ++ } ++ *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; ++ *(u16 *)poid_par_priv->information_buf = peeprompriv->channel_plan ; ++ ++ return status; ++} ++NDIS_STATUS oid_rt_set_channelplan_hdl(struct oid_par_priv* poid_par_priv) ++{ ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); ++ struct eeprom_priv* peeprompriv = &padapter->eeprompriv; ++ ++ if(poid_par_priv->type_of_oid != SET_OID) ++ { ++ status = NDIS_STATUS_NOT_ACCEPTED; ++ return status; ++ } ++ ++ peeprompriv->channel_plan = *(u16 *)poid_par_priv->information_buf ; ++ ++ return status; ++} ++//------------------------------------------------------------------------------ ++NDIS_STATUS oid_rt_set_preamble_mode_hdl(struct oid_par_priv* poid_par_priv) ++{ ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ULONG preamblemode = 0; ++ if(poid_par_priv->type_of_oid != SET_OID) ++ { ++ status = NDIS_STATUS_NOT_ACCEPTED; ++ return status; ++ } ++ ++ if(poid_par_priv->information_buf_len>= sizeof(ULONG)) ++ { ++ preamblemode = *(ULONG *)poid_par_priv->information_buf ; ++ if( preamblemode == 0) ++ padapter->registrypriv.preamble = PREAMBLE_LONG; ++ else if (preamblemode==1 ) ++ padapter->registrypriv.preamble = PREAMBLE_AUTO; ++ else if ( preamblemode==2 ) ++ padapter->registrypriv.preamble = PREAMBLE_SHORT; ++ ++ *(ULONG *)poid_par_priv->information_buf = preamblemode ; ++ *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; ++ } ++ else ++ { ++ status = NDIS_STATUS_INVALID_LENGTH ; ++ } ++ ++ return status; ++} ++//------------------------------------------------------------------------------ ++NDIS_STATUS oid_rt_set_bcn_intvl_hdl(struct oid_par_priv* poid_par_priv) ++{ ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++ if(poid_par_priv->type_of_oid != SET_OID) ++ { ++ status = NDIS_STATUS_NOT_ACCEPTED; ++ return status; ++ } ++ ++ return status; ++} ++NDIS_STATUS oid_rt_dedicate_probe_hdl(struct oid_par_priv* poid_par_priv) ++{ ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++ return status; ++} ++//------------------------------------------------------------------------------ ++NDIS_STATUS oid_rt_get_total_tx_bytes_hdl(struct oid_par_priv* poid_par_priv) ++{ ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++ if(poid_par_priv->type_of_oid != QUERY_OID) ++ { ++ status = NDIS_STATUS_NOT_ACCEPTED; ++ return status; ++ } ++ if(poid_par_priv->information_buf_len>= sizeof(ULONG)) ++ { ++ *(u64 *)poid_par_priv->information_buf = padapter->xmitpriv.tx_bytes; ++ *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; ++ } ++ else ++ { ++ status = NDIS_STATUS_INVALID_LENGTH ; ++ } ++ ++ ++ return status; ++} ++//------------------------------------------------------------------------------ ++NDIS_STATUS oid_rt_get_total_rx_bytes_hdl(struct oid_par_priv* poid_par_priv) ++{ ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++ if(poid_par_priv->type_of_oid != QUERY_OID) ++ { ++ status = NDIS_STATUS_NOT_ACCEPTED; ++ return status; ++ } ++ if(poid_par_priv->information_buf_len>= sizeof(ULONG)) ++ { ++ //_rtw_memcpy(*(uint *)poid_par_priv->information_buf,padapter->recvpriv.rx_icv_err,sizeof(u32)); ++ *(u64 *)poid_par_priv->information_buf = padapter->recvpriv.rx_bytes; ++ *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; ++ } ++ else ++ { ++ status = NDIS_STATUS_INVALID_LENGTH ; ++ } ++ return status; ++} ++//------------------------------------------------------------------------------ ++NDIS_STATUS oid_rt_current_tx_power_level_hdl(struct oid_par_priv* poid_par_priv) ++{ ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++ return status; ++} ++NDIS_STATUS oid_rt_get_enc_key_mismatch_count_hdl(struct oid_par_priv* poid_par_priv) ++{ ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++ if(poid_par_priv->type_of_oid != QUERY_OID) ++ { ++ status = NDIS_STATUS_NOT_ACCEPTED; ++ return status; ++ } ++ ++ return status; ++} ++NDIS_STATUS oid_rt_get_enc_key_match_count_hdl(struct oid_par_priv* poid_par_priv) ++{ ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++ if(poid_par_priv->type_of_oid != QUERY_OID) ++ { ++ status = NDIS_STATUS_NOT_ACCEPTED; ++ return status; ++ } ++ ++ return status; ++} ++NDIS_STATUS oid_rt_get_channel_hdl(struct oid_par_priv* poid_par_priv) ++{ ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ NDIS_802_11_CONFIGURATION *pnic_Config; ++ ++ ULONG channelnum; ++ ++ _func_enter_; ++ if(poid_par_priv->type_of_oid != QUERY_OID) ++ { ++ status = NDIS_STATUS_NOT_ACCEPTED; ++ return status; ++ } ++ ++ if ( (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) || ++ (check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE)) ++ pnic_Config = &pmlmepriv->cur_network.network.Configuration; ++ else ++ pnic_Config = &padapter->registrypriv.dev_network.Configuration; ++ ++ channelnum = pnic_Config->DSConfig; ++ *(ULONG *)poid_par_priv->information_buf = channelnum; ++ ++ *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; ++ ++ _func_exit_; ++ ++ ++ ++ return status; ++} ++NDIS_STATUS oid_rt_get_hardware_radio_off_hdl(struct oid_par_priv* poid_par_priv) ++{ ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++ if(poid_par_priv->type_of_oid != QUERY_OID) ++ { ++ status = NDIS_STATUS_NOT_ACCEPTED; ++ return status; ++ } ++ ++ return status; ++} ++NDIS_STATUS oid_rt_get_key_mismatch_hdl(struct oid_par_priv* poid_par_priv) ++{ ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++ if(poid_par_priv->type_of_oid != QUERY_OID) ++ { ++ status = NDIS_STATUS_NOT_ACCEPTED; ++ return status; ++ } ++ ++ return status; ++} ++NDIS_STATUS oid_rt_supported_wireless_mode_hdl(struct oid_par_priv* poid_par_priv) ++{ ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ULONG ulInfo = 0 ; ++ //DEBUG_ERR(("<**********************oid_rt_supported_wireless_mode_hdl \n")); ++ if(poid_par_priv->type_of_oid != QUERY_OID) ++ { ++ status = NDIS_STATUS_NOT_ACCEPTED; ++ return status; ++ } ++ if(poid_par_priv->information_buf_len >= sizeof(ULONG)){ ++ ulInfo |= 0x0100; //WIRELESS_MODE_B ++ ulInfo |= 0x0200; //WIRELESS_MODE_G ++ ulInfo |= 0x0400; //WIRELESS_MODE_A ++ ++ *(ULONG *) poid_par_priv->information_buf = ulInfo; ++ //DEBUG_ERR(("<===oid_rt_supported_wireless_mode %x\n",ulInfo)); ++ *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; ++ } ++ else{ ++ status = NDIS_STATUS_INVALID_LENGTH; ++ } ++ ++ return status; ++} ++NDIS_STATUS oid_rt_get_channel_list_hdl(struct oid_par_priv* poid_par_priv) ++{ ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++ if(poid_par_priv->type_of_oid != QUERY_OID) ++ { ++ status = NDIS_STATUS_NOT_ACCEPTED; ++ return status; ++ } ++ ++ return status; ++} ++NDIS_STATUS oid_rt_get_scan_in_progress_hdl(struct oid_par_priv* poid_par_priv) ++{ ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++ if(poid_par_priv->type_of_oid != QUERY_OID) ++ { ++ status = NDIS_STATUS_NOT_ACCEPTED; ++ return status; ++ } ++ ++ return status; ++} ++ ++ ++NDIS_STATUS oid_rt_forced_data_rate_hdl(struct oid_par_priv* poid_par_priv) ++{ ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++ return status; ++} ++NDIS_STATUS oid_rt_wireless_mode_for_scan_list_hdl(struct oid_par_priv* poid_par_priv) ++{ ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++ return status; ++} ++NDIS_STATUS oid_rt_get_bss_wireless_mode_hdl(struct oid_par_priv* poid_par_priv) ++{ ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++ if(poid_par_priv->type_of_oid != QUERY_OID) ++ { ++ status = NDIS_STATUS_NOT_ACCEPTED; ++ return status; ++ } ++ ++ return status; ++} ++ ++NDIS_STATUS oid_rt_scan_with_magic_packet_hdl(struct oid_par_priv* poid_par_priv) ++{ ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++ return status; ++} ++//************** oid_rtl_seg_01_01 section end ************** ++ ++//************** oid_rtl_seg_01_03 section start ************** ++NDIS_STATUS oid_rt_ap_get_associated_station_list_hdl(struct oid_par_priv* poid_par_priv) ++{ ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++ if(poid_par_priv->type_of_oid != QUERY_OID) ++ { ++ status = NDIS_STATUS_NOT_ACCEPTED; ++ return status; ++ } ++ ++ return status; ++} ++NDIS_STATUS oid_rt_ap_switch_into_ap_mode_hdl(struct oid_par_priv* poid_par_priv) ++{ ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++ return status; ++} ++NDIS_STATUS oid_rt_ap_supported_hdl(struct oid_par_priv* poid_par_priv) ++{ ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++ return status; ++} ++NDIS_STATUS oid_rt_ap_set_passphrase_hdl(struct oid_par_priv* poid_par_priv) ++{ ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++ if(poid_par_priv->type_of_oid != SET_OID) ++ { ++ status = NDIS_STATUS_NOT_ACCEPTED; ++ return status; ++ } ++ ++ return status; ++} ++ ++//************** oid_rtl_seg_01_03 section end ************** ++ ++//**************** oid_rtl_seg_01_11 section start **************** ++NDIS_STATUS oid_rt_pro_rf_write_registry_hdl(struct oid_par_priv* poid_par_priv) ++{ ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); ++ _irqL oldirql; ++ _func_enter_; ++ //DEBUG_ERR(("<**********************oid_rt_pro_rf_write_registry_hdl \n")); ++ if(poid_par_priv->type_of_oid != SET_OID) //QUERY_OID ++ { ++ status = NDIS_STATUS_NOT_ACCEPTED; ++ return status; ++ } ++ ++ _irqlevel_changed_(&oldirql,LOWER); ++ if(poid_par_priv->information_buf_len== (sizeof(unsigned long)*3)) ++ { ++ //RegOffsetValue - The offset of RF register to write. ++ //RegDataWidth - The data width of RF register to write. ++ //RegDataValue - The value to write. ++ //RegOffsetValue = *((unsigned long*)InformationBuffer); ++ //RegDataWidth = *((unsigned long*)InformationBuffer+1); ++ //RegDataValue = *((unsigned long*)InformationBuffer+2); ++ if(!rtw_setrfreg_cmd(Adapter, ++ *(unsigned char*)poid_par_priv->information_buf, ++ (unsigned long)(*((unsigned long*)poid_par_priv->information_buf+2)))) ++ { ++ status = NDIS_STATUS_NOT_ACCEPTED; ++ } ++ ++ } ++ else{ ++ status = NDIS_STATUS_INVALID_LENGTH; ++ } ++ _irqlevel_changed_(&oldirql,RAISE); ++ _func_exit_; ++ ++ return status; ++} ++ ++//------------------------------------------------------------------------------ ++NDIS_STATUS oid_rt_pro_rf_read_registry_hdl(struct oid_par_priv* poid_par_priv) ++{ ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++#if 0 ++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); ++ _irqL oldirql; ++ _func_enter_; ++ ++ //DEBUG_ERR(("<**********************oid_rt_pro_rf_read_registry_hdl \n")); ++ if(poid_par_priv->type_of_oid != SET_OID) //QUERY_OID ++ { ++ status = NDIS_STATUS_NOT_ACCEPTED; ++ return status; ++ } ++ ++ _irqlevel_changed_(&oldirql,LOWER); ++ if(poid_par_priv->information_buf_len== (sizeof(unsigned long)*3)) ++ { ++ if(Adapter->mppriv.act_in_progress == _TRUE) ++ { ++ status = NDIS_STATUS_NOT_ACCEPTED; ++ } ++ else ++ { ++ //init workparam ++ Adapter->mppriv.act_in_progress = _TRUE; ++ Adapter->mppriv.workparam.bcompleted= _FALSE; ++ Adapter->mppriv.workparam.act_type = MPT_READ_RF; ++ Adapter->mppriv.workparam.io_offset = *(unsigned long*)poid_par_priv->information_buf; ++ Adapter->mppriv.workparam.io_value = 0xcccccccc; ++ ++ //RegOffsetValue - The offset of RF register to read. ++ //RegDataWidth - The data width of RF register to read. ++ //RegDataValue - The value to read. ++ //RegOffsetValue = *((unsigned long*)InformationBuffer); ++ //RegDataWidth = *((unsigned long*)InformationBuffer+1); ++ //RegDataValue = *((unsigned long*)InformationBuffer+2); ++ if(!rtw_getrfreg_cmd(Adapter, ++ *(unsigned char*)poid_par_priv->information_buf, ++ (unsigned char*)&Adapter->mppriv.workparam.io_value)) ++ { ++ status = NDIS_STATUS_NOT_ACCEPTED; ++ } ++ } ++ ++ ++ } ++ else { ++ status = NDIS_STATUS_INVALID_LENGTH; ++ } ++ _irqlevel_changed_(&oldirql,RAISE); ++ _func_exit_; ++#endif ++ return status; ++} ++ ++//**************** oid_rtl_seg_01_11 section end**************** ++ ++ ++//************** oid_rtl_seg_03_00 section start ************** ++enum _CONNECT_STATE_{ ++ CHECKINGSTATUS, ++ ASSOCIATED, ++ ADHOCMODE, ++ NOTASSOCIATED ++}; ++ ++NDIS_STATUS oid_rt_get_connect_state_hdl(struct oid_par_priv* poid_par_priv) ++{ ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ ++ ULONG ulInfo; ++ ++ if(poid_par_priv->type_of_oid != QUERY_OID) ++ { ++ status = NDIS_STATUS_NOT_ACCEPTED; ++ return status; ++ } ++ ++ // nStatus==0 CheckingStatus ++ // nStatus==1 Associated ++ // nStatus==2 AdHocMode ++ // nStatus==3 NotAssociated ++ ++ if(check_fwstate(pmlmepriv, _FW_UNDER_LINKING) == _TRUE) ++ ulInfo = CHECKINGSTATUS; ++ else if(check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) ++ ulInfo = ASSOCIATED; ++ else if(check_fwstate(pmlmepriv, WIFI_ADHOC_STATE)== _TRUE) ++ ulInfo = ADHOCMODE; ++ else ++ ulInfo = NOTASSOCIATED ; ++ ++ *(ULONG *)poid_par_priv->information_buf = ulInfo; ++ *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; ++ ++#if 0 ++ // Rearrange the order to let the UI still shows connection when scan is in progress ++ RT_TRACE(COMP_OID_QUERY, DBG_LOUD, ("===> Query OID_RT_GET_CONNECT_STATE.\n")); ++ if(pMgntInfo->mAssoc) ++ ulInfo = 1; ++ else if(pMgntInfo->mIbss) ++ ulInfo = 2; ++ else if(pMgntInfo->bScanInProgress) ++ ulInfo = 0; ++ else ++ ulInfo = 3; ++ ulInfoLen = sizeof(ULONG); ++ RT_TRACE(COMP_OID_QUERY, DBG_LOUD, ("<=== Query OID_RT_GET_CONNECT_STATE: %d\n", ulInfo)); ++#endif ++ ++ return status; ++} ++ ++NDIS_STATUS oid_rt_set_default_key_id_hdl(struct oid_par_priv* poid_par_priv) ++{ ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++ if(poid_par_priv->type_of_oid != SET_OID) ++ { ++ status = NDIS_STATUS_NOT_ACCEPTED; ++ return status; ++ } ++ ++ return status; ++} ++//************** oid_rtl_seg_03_00 section end ************** +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/core/rtw_ioctl_set.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/core/rtw_ioctl_set.c 2013-07-26 19:36:05.000000000 +0000 +@@ -0,0 +1,1426 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++******************************************************************************/ ++#define _RTW_IOCTL_SET_C_ ++ ++ ++#include ++#include ++#include ++#include ++#include ++ ++#ifdef CONFIG_USB_HCI ++#include ++#include ++#endif ++#ifdef CONFIG_SDIO_HCI ++#include ++#endif ++ ++extern void indicate_wx_scan_complete_event(_adapter *padapter); ++ ++#define IS_MAC_ADDRESS_BROADCAST(addr) \ ++( \ ++ ( (addr[0] == 0xff) && (addr[1] == 0xff) && \ ++ (addr[2] == 0xff) && (addr[3] == 0xff) && \ ++ (addr[4] == 0xff) && (addr[5] == 0xff) ) ? _TRUE : _FALSE \ ++) ++ ++u8 rtw_validate_ssid(NDIS_802_11_SSID *ssid) ++{ ++ u8 i; ++ u8 ret=_TRUE; ++ ++_func_enter_; ++ ++ if (ssid->SsidLength > 32) { ++ RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ("ssid length >32\n")); ++ ret= _FALSE; ++ goto exit; ++ } ++ ++ for(i = 0; i < ssid->SsidLength; i++) ++ { ++ //wifi, printable ascii code must be supported ++ if(!( (ssid->Ssid[i] >= 0x20) && (ssid->Ssid[i] <= 0x7e) )){ ++ RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ("ssid has nonprintabl ascii\n")); ++ ret= _FALSE; ++ break; ++ } ++ } ++ ++exit: ++ ++_func_exit_; ++ ++ return ret; ++} ++ ++u8 rtw_do_join(_adapter * padapter) ++{ ++ _irqL irqL; ++ _list *plist, *phead; ++ u8* pibss = NULL; ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ _queue *queue = &(pmlmepriv->scanned_queue); ++ u8 ret=_SUCCESS; ++ ++_func_enter_; ++ ++ _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); ++ phead = get_list_head(queue); ++ plist = get_next(phead); ++ ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_info_,("\n rtw_do_join: phead = %p; plist = %p \n\n\n", phead, plist)); ++ ++ pmlmepriv->cur_network.join_res = -2; ++ ++ set_fwstate(pmlmepriv, _FW_UNDER_LINKING); ++ ++ pmlmepriv->pscanned = plist; ++ ++ pmlmepriv->to_join = _TRUE; ++ ++ if(_rtw_queue_empty(queue)== _TRUE) ++ { ++ _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); ++ _clr_fwstate_(pmlmepriv, _FW_UNDER_LINKING); ++ ++ //when set_ssid/set_bssid for rtw_do_join(), but scanning queue is empty ++ //we try to issue sitesurvey firstly ++ ++ if(pmlmepriv->LinkDetectInfo.bBusyTraffic==_FALSE ++ #ifdef CONFIG_LAYER2_ROAMING ++ || pmlmepriv->to_roaming >0 ++ #endif ++ ) ++ { ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_info_,("rtw_do_join(): site survey if scanned_queue is empty\n.")); ++ // submit site_survey_cmd ++ if(_SUCCESS!=(ret=rtw_sitesurvey_cmd(padapter, &pmlmepriv->assoc_ssid, 1)) ) { ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("rtw_do_join(): site survey return error\n.")); ++ } ++ } ++ ++ goto exit; ++ } ++ else ++ { ++ int select_ret; ++ _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); ++ if((select_ret=rtw_select_and_join_from_scanned_queue(pmlmepriv))==_SUCCESS) ++ { ++ pmlmepriv->to_join = _FALSE; ++ _set_timer(&pmlmepriv->assoc_timer, MAX_JOIN_TIMEOUT); ++ } ++ else if(ret == 2)//there is no need to wait for join ++ { ++ ret = _SUCCESS; ++ clr_fwstate(pmlmepriv, _FW_UNDER_LINKING); ++ rtw_indicate_connect(padapter); ++ } ++ else ++ { ++ if(check_fwstate(pmlmepriv, WIFI_ADHOC_STATE)==_TRUE) ++ { ++ // submit createbss_cmd to change to a ADHOC_MASTER ++ ++ //pmlmepriv->lock has been acquired by caller... ++ WLAN_BSSID_EX *pdev_network = &(padapter->registrypriv.dev_network); ++ ++ pmlmepriv->fw_state = WIFI_ADHOC_MASTER_STATE; ++ ++ pibss = padapter->registrypriv.dev_network.MacAddress; ++ ++ _rtw_memset(&pdev_network->Ssid, 0, sizeof(NDIS_802_11_SSID)); ++ _rtw_memcpy(&pdev_network->Ssid, &pmlmepriv->assoc_ssid, sizeof(NDIS_802_11_SSID)); ++ ++ rtw_update_registrypriv_dev_network(padapter); ++ ++ rtw_generate_random_ibss(pibss); ++ ++ if(rtw_createbss_cmd(padapter)!=_SUCCESS) ++ { ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("***Error=>do_goin: rtw_createbss_cmd status FAIL*** \n ")); ++ ret = _FALSE; ++ goto exit; ++ } ++ ++ pmlmepriv->to_join = _FALSE; ++ ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_info_,("***Error=> rtw_select_and_join_from_scanned_queue FAIL under STA_Mode*** \n ")); ++ ++ } ++ else ++ { ++ // can't associate ; reset under-linking ++ _clr_fwstate_(pmlmepriv, _FW_UNDER_LINKING); ++ ++#if 0 ++ if((check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE)) ++ { ++ if(_rtw_memcmp(pmlmepriv->cur_network.network.Ssid.Ssid, pmlmepriv->assoc_ssid.Ssid, pmlmepriv->assoc_ssid.SsidLength)) ++ { ++ // for funk to do roaming ++ // funk will reconnect, but funk will not sitesurvey before reconnect ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_info_,("for funk to do roaming")); ++ if(pmlmepriv->sitesurveyctrl.traffic_busy==_FALSE) ++ rtw_sitesurvey_cmd(padapter, &pmlmepriv->assoc_ssid, 1); ++ } ++ ++ } ++#endif ++ ++ //when set_ssid/set_bssid for rtw_do_join(), but there are no desired bss in scanning queue ++ //we try to issue sitesurvey firstly ++ if(pmlmepriv->LinkDetectInfo.bBusyTraffic==_FALSE ++ #ifdef CONFIG_LAYER2_ROAMING ++ || pmlmepriv->to_roaming >0 ++ #endif ++ ) ++ { ++ //DBG_8192C("rtw_do_join() when no desired bss in scanning queue \n"); ++ if( _SUCCESS!=(ret=rtw_sitesurvey_cmd(padapter, &pmlmepriv->assoc_ssid, 1)) ){ ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("do_join(): site survey return error\n.")); ++ } ++ } ++ ++ ++ } ++ ++ } ++ ++ } ++ ++exit: ++ ++_func_exit_; ++ ++ return ret; ++} ++ ++#ifdef PLATFORM_WINDOWS ++u8 rtw_pnp_set_power_wakeup(_adapter* padapter) ++{ ++ u8 res=_SUCCESS; ++ ++_func_enter_; ++ ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("==>rtw_pnp_set_power_wakeup!!!\n")); ++ ++ res = rtw_setstandby_cmd(padapter, 0); ++ ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("<==rtw_pnp_set_power_wakeup!!!\n")); ++ ++_func_exit_; ++ ++ return res; ++} ++ ++u8 rtw_pnp_set_power_sleep(_adapter* padapter) ++{ ++ u8 res=_SUCCESS; ++ ++_func_enter_; ++ ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("==>rtw_pnp_set_power_sleep!!!\n")); ++ //DbgPrint("+rtw_pnp_set_power_sleep\n"); ++ ++ res = rtw_setstandby_cmd(padapter, 1); ++ ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("<==rtw_pnp_set_power_sleep!!!\n")); ++ ++_func_exit_; ++ ++ return res; ++} ++ ++u8 rtw_set_802_11_reload_defaults(_adapter * padapter, NDIS_802_11_RELOAD_DEFAULTS reloadDefaults) ++{ ++_func_enter_; ++ ++ switch( reloadDefaults) ++ { ++ case Ndis802_11ReloadWEPKeys: ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_info_,("SetInfo OID_802_11_RELOAD_DEFAULTS : Ndis802_11ReloadWEPKeys\n")); ++ break; ++ } ++ ++ // SecClearAllKeys(Adapter); ++ // 8711 CAM was not for En/Decrypt only ++ // so, we can't clear all keys. ++ // should we disable WPAcfg (ox0088) bit 1-2, instead of clear all CAM ++ ++ //TO DO... ++ ++_func_exit_; ++ ++ return _TRUE; ++} ++ ++u8 set_802_11_test(_adapter* padapter, NDIS_802_11_TEST *test) ++{ ++ u8 ret=_TRUE; ++ ++_func_enter_; ++ ++ switch(test->Type) ++ { ++ case 1: ++ NdisMIndicateStatus(padapter->hndis_adapter, NDIS_STATUS_MEDIA_SPECIFIC_INDICATION, (PVOID)&test->AuthenticationEvent, test->Length - 8); ++ NdisMIndicateStatusComplete(padapter->hndis_adapter); ++ break; ++ ++ case 2: ++ NdisMIndicateStatus(padapter->hndis_adapter, NDIS_STATUS_MEDIA_SPECIFIC_INDICATION, (PVOID)&test->RssiTrigger, sizeof(NDIS_802_11_RSSI)); ++ NdisMIndicateStatusComplete(padapter->hndis_adapter); ++ break; ++ ++ default: ++ ret=_FALSE; ++ break; ++ } ++ ++_func_exit_; ++ ++ return ret; ++} ++ ++u8 rtw_set_802_11_pmkid(_adapter* padapter, NDIS_802_11_PMKID *pmkid) ++{ ++ u8 ret=_SUCCESS; ++ ++ return ret; ++} ++ ++#endif ++ ++u8 rtw_set_802_11_bssid(_adapter* padapter, u8 *bssid) ++{ ++ _irqL irqL; ++ u8 status=_SUCCESS; ++ u32 cur_time = 0; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ _queue *queue = &pmlmepriv->scanned_queue; ++ ++_func_enter_; ++ ++ RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_notice_, ++ ("+rtw_set_802_11_bssid: bssid="MAC_FMT"\n", MAC_ARG(bssid) )); ++ ++ if ((bssid[0]==0x00 && bssid[1]==0x00 && bssid[2]==0x00 && bssid[3]==0x00 && bssid[4]==0x00 &&bssid[5]==0x00) || ++ (bssid[0]==0xFF && bssid[1]==0xFF && bssid[2]==0xFF && bssid[3]==0xFF && bssid[4]==0xFF &&bssid[5]==0xFF)) ++ { ++ status = _FAIL; ++ goto exit; ++ } ++ ++ _enter_critical_bh(&pmlmepriv->lock, &irqL); ++ ++ ++ DBG_871X("Set BSSID under fw_state=0x%08x\n", get_fwstate(pmlmepriv)); ++ if (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY) == _TRUE) { ++ goto handle_tkip_countermeasure; ++ } else if (check_fwstate(pmlmepriv, _FW_UNDER_LINKING) == _TRUE) { ++ goto release_mlme_lock; ++ } ++ ++ if (check_fwstate(pmlmepriv, _FW_LINKED|WIFI_ADHOC_MASTER_STATE) == _TRUE) ++ { ++ RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_info_, ("set_bssid: _FW_LINKED||WIFI_ADHOC_MASTER_STATE\n")); ++ ++ if (_rtw_memcmp(&pmlmepriv->cur_network.network.MacAddress, bssid, ETH_ALEN) == _TRUE) ++ { ++ if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _FALSE) ++ goto release_mlme_lock;//it means driver is in WIFI_ADHOC_MASTER_STATE, we needn't create bss again. ++ } else { ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_info_,("Set BSSID not the same bssid\n")); ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_info_,("set_bssid="MAC_FMT"\n", MAC_ARG(bssid) )); ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_info_,("cur_bssid="MAC_FMT"\n", MAC_ARG(pmlmepriv->cur_network.network.MacAddress) )); ++ ++ rtw_disassoc_cmd(padapter); ++ ++ if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) ++ rtw_indicate_disconnect(padapter); ++ ++ rtw_free_assoc_resources(padapter, 1); ++ ++ if ((check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE)) { ++ _clr_fwstate_(pmlmepriv, WIFI_ADHOC_MASTER_STATE); ++ set_fwstate(pmlmepriv, WIFI_ADHOC_STATE); ++ } ++ } ++ } ++ ++handle_tkip_countermeasure: ++ //should we add something here...? ++ ++#ifdef PLATFORM_LINUX ++ if (padapter->securitypriv.btkip_countermeasure == _TRUE) { ++ cur_time = rtw_get_current_time(); ++ ++ if( (cur_time - padapter->securitypriv.btkip_countermeasure_time) > 60 * HZ ) ++ { ++ padapter->securitypriv.btkip_countermeasure = _FALSE; ++ padapter->securitypriv.btkip_countermeasure_time = 0; ++ } ++ else ++ { ++ status = _FAIL; ++ goto release_mlme_lock; ++ } ++ } ++#endif ++ ++ _rtw_memcpy(&pmlmepriv->assoc_bssid, bssid, ETH_ALEN); ++ pmlmepriv->assoc_by_bssid=_TRUE; ++ ++ if (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY) == _TRUE) { ++ pmlmepriv->to_join = _TRUE; ++ } ++ else { ++ status = rtw_do_join(padapter); ++ } ++ ++release_mlme_lock: ++ _exit_critical_bh(&pmlmepriv->lock, &irqL); ++ ++exit: ++ RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ++ ("rtw_set_802_11_bssid: status=%d\n", status)); ++ ++_func_exit_; ++ ++ return status; ++} ++ ++u8 rtw_set_802_11_ssid(_adapter* padapter, NDIS_802_11_SSID *ssid) ++{ ++ _irqL irqL; ++ u8 status = _SUCCESS; ++ u32 cur_time = 0; ++ ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct wlan_network *pnetwork = &pmlmepriv->cur_network; ++ ++ ++_func_enter_; ++ ++ RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_notice_, ++ ("+rtw_set_802_11_ssid: ssid=[%s] fw_state=0x%08x\n", ++ ssid->Ssid, get_fwstate(pmlmepriv))); ++ ++ if(padapter->hw_init_completed==_FALSE){ ++ RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ++ ("set_ssid: hw_init_completed==_FALSE=>exit!!!\n")); ++ status = _FAIL; ++ goto exit; ++ } ++ ++ _enter_critical_bh(&pmlmepriv->lock, &irqL); ++ ++ DBG_871X("Set SSID under fw_state=0x%08x\n", get_fwstate(pmlmepriv)); ++ if (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY) == _TRUE) { ++ goto handle_tkip_countermeasure; ++ } else if (check_fwstate(pmlmepriv, _FW_UNDER_LINKING) == _TRUE) { ++ goto release_mlme_lock; ++ } ++ ++ if (check_fwstate(pmlmepriv, _FW_LINKED|WIFI_ADHOC_MASTER_STATE) == _TRUE) ++ { ++ RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_info_, ++ ("set_ssid: _FW_LINKED||WIFI_ADHOC_MASTER_STATE\n")); ++ ++ if ((pmlmepriv->assoc_ssid.SsidLength == ssid->SsidLength) && ++ (_rtw_memcmp(&pmlmepriv->assoc_ssid.Ssid, ssid->Ssid, ssid->SsidLength) == _TRUE)) ++ { ++ if((check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _FALSE)) ++ { ++ RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ++ ("Set SSID is the same ssid, fw_state=0x%08x\n", ++ get_fwstate(pmlmepriv))); ++ ++ if(rtw_is_same_ibss(padapter, pnetwork) == _FALSE) ++ { ++ //if in WIFI_ADHOC_MASTER_STATE | WIFI_ADHOC_STATE, create bss or rejoin again ++ rtw_disassoc_cmd(padapter); ++ ++ if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) ++ rtw_indicate_disconnect(padapter); ++ ++ rtw_free_assoc_resources(padapter, 1); ++ ++ if (check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE) { ++ _clr_fwstate_(pmlmepriv, WIFI_ADHOC_MASTER_STATE); ++ set_fwstate(pmlmepriv, WIFI_ADHOC_STATE); ++ } ++ } ++ else ++ { ++ goto release_mlme_lock;//it means driver is in WIFI_ADHOC_MASTER_STATE, we needn't create bss again. ++ } ++ } ++#ifdef CONFIG_LPS ++ else { ++ rtw_lps_ctrl_wk_cmd(padapter, LPS_CTRL_JOINBSS, 1); ++ } ++#endif ++ } ++ else ++ { ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_info_,("Set SSID not the same ssid\n")); ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_info_,("set_ssid=[%s] len=0x%x\n", ssid->Ssid, (unsigned int)ssid->SsidLength)); ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_info_,("assoc_ssid=[%s] len=0x%x\n", pmlmepriv->assoc_ssid.Ssid, (unsigned int)pmlmepriv->assoc_ssid.SsidLength)); ++ ++ rtw_disassoc_cmd(padapter); ++ ++ if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) ++ rtw_indicate_disconnect(padapter); ++ ++ rtw_free_assoc_resources(padapter, 1); ++ ++ if (check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE) { ++ _clr_fwstate_(pmlmepriv, WIFI_ADHOC_MASTER_STATE); ++ set_fwstate(pmlmepriv, WIFI_ADHOC_STATE); ++ } ++ } ++ } ++ ++handle_tkip_countermeasure: ++#ifdef PLATFORM_WINDOWS ++ if (padapter->securitypriv.btkip_countermeasure==_TRUE) ++ { ++ LARGE_INTEGER sys_time; ++ u32 diff_time,cur_time ; ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_info_,("rtw_set_802_11_ssid:padapter->securitypriv.btkip_countermeasure==_TRUE\n")); ++ NdisGetCurrentSystemTime(&sys_time); ++ cur_time=(u32)(sys_time.QuadPart/10); // In micro-second. ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_info_,("rtw_set_802_11_ssid:cur_time=0x%x\n",cur_time)); ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_info_,("rtw_set_802_11_ssid:psecuritypriv->last_mic_err_time=0x%x\n",padapter->securitypriv.btkip_countermeasure_time)); ++ diff_time = cur_time -padapter->securitypriv.btkip_countermeasure_time; // In micro-second. ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_info_,("rtw_set_802_11_ssid:diff_time=0x%x\n",diff_time)); ++ ++ if (diff_time > 60000000) { ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_info_,("rtw_set_802_11_ssid(): countermeasure time >60s.\n")); ++ padapter->securitypriv.btkip_countermeasure=_FALSE; ++ // Update MIC error time. ++ padapter->securitypriv.btkip_countermeasure_time=0; ++ } else { ++ // can't join in 60 seconds. ++ status = _FAIL; ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_info_,("rtw_set_802_11_ssid(): countermeasure time <60s.\n")); ++ goto release_mlme_lock; ++ } ++ } ++#endif ++ ++#ifdef PLATFORM_LINUX ++ if (padapter->securitypriv.btkip_countermeasure == _TRUE) { ++ cur_time = rtw_get_current_time(); ++ ++ if( (cur_time - padapter->securitypriv.btkip_countermeasure_time) > 60 * HZ ) ++ { ++ padapter->securitypriv.btkip_countermeasure = _FALSE; ++ padapter->securitypriv.btkip_countermeasure_time = 0; ++ } ++ else ++ { ++ status = _FAIL; ++ goto release_mlme_lock; ++ } ++ } ++#endif ++ ++ #ifdef CONFIG_VALIDATE_SSID ++ if (rtw_validate_ssid(ssid) == _FALSE) { ++ status = _FAIL; ++ goto release_mlme_lock; ++ } ++ #endif ++ ++ _rtw_memcpy(&pmlmepriv->assoc_ssid, ssid, sizeof(NDIS_802_11_SSID)); ++ pmlmepriv->assoc_by_bssid=_FALSE; ++ ++ if (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY) == _TRUE) { ++ pmlmepriv->to_join = _TRUE; ++ } ++ else { ++ status = rtw_do_join(padapter); ++ } ++ ++release_mlme_lock: ++ _exit_critical_bh(&pmlmepriv->lock, &irqL); ++ ++exit: ++ RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_err_, ++ ("-rtw_set_802_11_ssid: status=%d\n", status)); ++ ++_func_exit_; ++ ++ return status; ++ ++} ++ ++u8 rtw_set_802_11_infrastructure_mode(_adapter* padapter, ++ NDIS_802_11_NETWORK_INFRASTRUCTURE networktype) ++{ ++ _irqL irqL; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct wlan_network *cur_network = &pmlmepriv->cur_network; ++ NDIS_802_11_NETWORK_INFRASTRUCTURE* pold_state = &(cur_network->network.InfrastructureMode); ++ ++_func_enter_; ++ ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_notice_, ++ ("+rtw_set_802_11_infrastructure_mode: old=%d new=%d fw_state=0x%08x\n", ++ *pold_state, networktype, get_fwstate(pmlmepriv))); ++ ++ if(*pold_state != networktype) ++ { ++ _enter_critical_bh(&pmlmepriv->lock, &irqL); ++ ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_info_,(" change mode!")); ++ //DBG_871X("change mode, old_mode=%d, new_mode=%d, fw_state=0x%x\n", *pold_state, networktype, get_fwstate(pmlmepriv)); ++ ++ if((check_fwstate(pmlmepriv, _FW_LINKED)== _TRUE) ||(*pold_state==Ndis802_11IBSS)) ++ rtw_disassoc_cmd(padapter); ++ ++ if((check_fwstate(pmlmepriv, _FW_LINKED)== _TRUE) || ++ (check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE)== _TRUE) ) ++ rtw_free_assoc_resources(padapter, 1); ++ ++ ++ if((check_fwstate(pmlmepriv, _FW_LINKED)== _TRUE) || (*pold_state==Ndis802_11Infrastructure) ||(*pold_state==Ndis802_11IBSS)) ++ { ++ rtw_indicate_disconnect(padapter); //will clr Linked_state; before this function, we must have chked whether issue dis-assoc_cmd or not ++ } ++ ++ if(*pold_state==Ndis802_11APMode) ++ { ++ //change to other mode from Ndis802_11APMode ++ cur_network->join_res = -1; ++ ++#ifdef CONFIG_NATIVEAP_MLME ++ stop_ap_mode(padapter); ++#endif ++ } ++ ++ *pold_state = networktype; ++ ++ // clear WIFI_STATION_STATE; WIFI_AP_STATE; WIFI_ADHOC_STATE; WIFI_ADHOC_MASTER_STATE ++ //pmlmepriv->fw_state &= 0xffffff87; ++ _clr_fwstate_(pmlmepriv, WIFI_STATION_STATE|WIFI_AP_STATE|WIFI_ADHOC_STATE|WIFI_ADHOC_MASTER_STATE); ++ ++ switch(networktype) ++ { ++ case Ndis802_11IBSS: ++ set_fwstate(pmlmepriv, WIFI_ADHOC_STATE); ++ break; ++ ++ case Ndis802_11Infrastructure: ++ set_fwstate(pmlmepriv, WIFI_STATION_STATE); ++ break; ++ ++ case Ndis802_11APMode: ++ set_fwstate(pmlmepriv, WIFI_AP_STATE); ++#ifdef CONFIG_NATIVEAP_MLME ++ start_ap_mode(padapter); ++ //rtw_indicate_connect(padapter); ++#endif ++ ++ break; ++ ++ case Ndis802_11AutoUnknown: ++ case Ndis802_11InfrastructureMax: ++ break; ++ } ++ ++ //SecClearAllKeys(adapter); ++ ++ //RT_TRACE(COMP_OID_SET, DBG_LOUD, ("set_infrastructure: fw_state:%x after changing mode\n", ++ // get_fwstate(pmlmepriv) )); ++ ++ _exit_critical_bh(&pmlmepriv->lock, &irqL); ++ } ++ ++_func_exit_; ++ ++ return _TRUE; ++} ++ ++ ++u8 rtw_set_802_11_disassociate(_adapter *padapter) ++{ ++ _irqL irqL; ++ struct mlme_priv * pmlmepriv = &padapter->mlmepriv; ++ ++_func_enter_; ++ ++ _enter_critical_bh(&pmlmepriv->lock, &irqL); ++ ++ if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) ++ { ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_info_,("MgntActrtw_set_802_11_disassociate: rtw_indicate_disconnect\n")); ++ ++ rtw_disassoc_cmd(padapter); ++ rtw_indicate_disconnect(padapter); ++ rtw_free_assoc_resources(padapter, 1); ++ } ++ ++ _exit_critical_bh(&pmlmepriv->lock, &irqL); ++ ++_func_exit_; ++ ++ return _TRUE; ++} ++ ++u8 rtw_set_802_11_bssid_list_scan(_adapter* padapter) ++{ ++ _irqL irqL; ++ struct mlme_priv *pmlmepriv= &padapter->mlmepriv; ++ u8 res=_TRUE; ++ ++_func_enter_; ++ ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("+rtw_set_802_11_bssid_list_scan(), fw_state=%x\n", get_fwstate(pmlmepriv))); ++ ++ if (padapter == NULL) { ++ res=_FALSE; ++ goto exit; ++ } ++ if (padapter->hw_init_completed==_FALSE){ ++ res = _FALSE; ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("\n===rtw_set_802_11_bssid_list_scan:hw_init_completed==_FALSE===\n")); ++ goto exit; ++ } ++ ++ if ((check_fwstate(pmlmepriv, _FW_UNDER_SURVEY|_FW_UNDER_LINKING) == _TRUE) || ++ (pmlmepriv->LinkDetectInfo.bBusyTraffic == _TRUE)) ++ { ++ // Scan or linking is in progress, do nothing. ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("rtw_set_802_11_bssid_list_scan fail since fw_state = %x\n", get_fwstate(pmlmepriv))); ++ res = _TRUE; ++ ++ if(check_fwstate(pmlmepriv, (_FW_UNDER_SURVEY|_FW_UNDER_LINKING))== _TRUE){ ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("\n###_FW_UNDER_SURVEY|_FW_UNDER_LINKING\n\n")); ++ } else { ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("\n###pmlmepriv->sitesurveyctrl.traffic_busy==_TRUE\n\n")); ++ } ++ } else { ++ #ifdef CONFIG_SET_SCAN_DENY_TIMER ++ if(ATOMIC_READ(&pmlmepriv->set_scan_deny)==1){ ++ DBG_871X("%s:%d CONFIG_SET_SCAN_DENY_TIMER deny scan\n", __FUNCTION__, __LINE__); ++ indicate_wx_scan_complete_event(padapter); ++ return _SUCCESS; ++ } ++ #endif ++ ++ _enter_critical_bh(&pmlmepriv->lock, &irqL); ++ ++ res = rtw_sitesurvey_cmd(padapter, NULL, 0); ++ ++ _exit_critical_bh(&pmlmepriv->lock, &irqL); ++ } ++exit: ++ ++_func_exit_; ++ ++ return res; ++} ++ ++u8 rtw_set_802_11_authentication_mode(_adapter* padapter, NDIS_802_11_AUTHENTICATION_MODE authmode) ++{ ++ struct security_priv *psecuritypriv = &padapter->securitypriv; ++ int res; ++ u8 ret; ++ ++_func_enter_; ++ ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_info_,("set_802_11_auth.mode(): mode=%x\n", authmode)); ++ ++ psecuritypriv->ndisauthtype=authmode; ++ ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_info_,("rtw_set_802_11_authentication_mode:psecuritypriv->ndisauthtype=%d", psecuritypriv->ndisauthtype)); ++ ++ if(psecuritypriv->ndisauthtype>3) ++ psecuritypriv->dot11AuthAlgrthm=dot11AuthAlgrthm_8021X; ++ ++ res=rtw_set_auth(padapter,psecuritypriv); ++ ++ if(res==_SUCCESS) ++ ret=_TRUE; ++ else ++ ret=_FALSE; ++ ++_func_exit_; ++ ++ return ret; ++} ++ ++u8 rtw_set_802_11_add_wep(_adapter* padapter, NDIS_802_11_WEP *wep){ ++ ++ u8 bdefaultkey; ++ u8 btransmitkey; ++ sint keyid,res; ++ struct security_priv* psecuritypriv=&(padapter->securitypriv); ++ u8 ret=_SUCCESS; ++ ++_func_enter_; ++ ++ bdefaultkey=(wep->KeyIndex & 0x40000000) > 0 ? _FALSE : _TRUE; //for ??? ++ btransmitkey= (wep->KeyIndex & 0x80000000) > 0 ? _TRUE : _FALSE; //for ??? ++ keyid=wep->KeyIndex & 0x3fffffff; ++ ++ if(keyid>4) ++ { ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("MgntActrtw_set_802_11_add_wep:keyid>4=>fail\n")); ++ ret=_FALSE; ++ goto exit; ++ } ++ ++ switch(wep->KeyLength) ++ { ++ case 5: ++ psecuritypriv->dot11PrivacyAlgrthm=_WEP40_; ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_info_,("MgntActrtw_set_802_11_add_wep:wep->KeyLength=5\n")); ++ break; ++ case 13: ++ psecuritypriv->dot11PrivacyAlgrthm=_WEP104_; ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_info_,("MgntActrtw_set_802_11_add_wep:wep->KeyLength=13\n")); ++ break; ++ default: ++ psecuritypriv->dot11PrivacyAlgrthm=_NO_PRIVACY_; ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_info_,("MgntActrtw_set_802_11_add_wep:wep->KeyLength!=5 or 13\n")); ++ break; ++ } ++ ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_info_,("rtw_set_802_11_add_wep:befor memcpy, wep->KeyLength=0x%x wep->KeyIndex=0x%x keyid =%x\n",wep->KeyLength,wep->KeyIndex,keyid)); ++ ++ _rtw_memcpy(&(psecuritypriv->dot11DefKey[keyid].skey[0]),&(wep->KeyMaterial),wep->KeyLength); ++ ++ psecuritypriv->dot11DefKeylen[keyid]=wep->KeyLength; ++ ++ psecuritypriv->dot11PrivacyKeyIndex=keyid; ++ ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_info_,("rtw_set_802_11_add_wep:security key material : %x %x %x %x %x %x %x %x %x %x %x %x %x \n", ++ psecuritypriv->dot11DefKey[keyid].skey[0],psecuritypriv->dot11DefKey[keyid].skey[1],psecuritypriv->dot11DefKey[keyid].skey[2], ++ psecuritypriv->dot11DefKey[keyid].skey[3],psecuritypriv->dot11DefKey[keyid].skey[4],psecuritypriv->dot11DefKey[keyid].skey[5], ++ psecuritypriv->dot11DefKey[keyid].skey[6],psecuritypriv->dot11DefKey[keyid].skey[7],psecuritypriv->dot11DefKey[keyid].skey[8], ++ psecuritypriv->dot11DefKey[keyid].skey[9],psecuritypriv->dot11DefKey[keyid].skey[10],psecuritypriv->dot11DefKey[keyid].skey[11], ++ psecuritypriv->dot11DefKey[keyid].skey[12])); ++ ++ res=rtw_set_key(padapter,psecuritypriv, keyid, 1); ++ ++ if(res==_FAIL) ++ ret= _FALSE; ++exit: ++ ++_func_exit_; ++ ++ return ret; ++ ++} ++ ++u8 rtw_set_802_11_remove_wep(_adapter* padapter, u32 keyindex){ ++ ++ u8 ret=_SUCCESS; ++ ++_func_enter_; ++ ++ if (keyindex >= 0x80000000 || padapter == NULL){ ++ ++ ret=_FALSE; ++ goto exit; ++ ++ } ++ else ++ { ++ int res; ++ struct security_priv* psecuritypriv=&(padapter->securitypriv); ++ if( keyindex < 4 ){ ++ ++ _rtw_memset(&psecuritypriv->dot11DefKey[keyindex], 0, 16); ++ ++ res=rtw_set_key(padapter,psecuritypriv,keyindex, 0); ++ ++ psecuritypriv->dot11DefKeylen[keyindex]=0; ++ ++ if(res==_FAIL) ++ ret=_FAIL; ++ ++ } ++ else ++ { ++ ret=_FAIL; ++ } ++ ++ } ++ ++exit: ++ ++_func_exit_; ++ ++ return ret; ++ ++} ++ ++u8 rtw_set_802_11_add_key(_adapter* padapter, NDIS_802_11_KEY *key){ ++ ++ uint encryptionalgo; ++ u8 * pbssid; ++ struct sta_info *stainfo; ++ u8 bgroup = _FALSE; ++ u8 bgrouptkey = _FALSE;//can be remove later ++ u8 ret=_SUCCESS; ++ ++_func_enter_; ++ ++ if (((key->KeyIndex & 0x80000000) == 0) && ((key->KeyIndex & 0x40000000) > 0)){ ++ ++ // It is invalid to clear bit 31 and set bit 30. If the miniport driver encounters this combination, ++ // it must fail the request and return NDIS_STATUS_INVALID_DATA. ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_info_,("rtw_set_802_11_add_key: ((key->KeyIndex & 0x80000000) == 0)[=%d] ",(int)(key->KeyIndex & 0x80000000) == 0)); ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_info_,("rtw_set_802_11_add_key:((key->KeyIndex & 0x40000000) > 0)[=%d]" , (int)(key->KeyIndex & 0x40000000) > 0)); ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_info_,("rtw_set_802_11_add_key: key->KeyIndex=%d \n" ,(int)key->KeyIndex)); ++ ret= _FAIL; ++ goto exit; ++ } ++ ++ if(key->KeyIndex & 0x40000000) ++ { ++ // Pairwise key ++ ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("OID_802_11_ADD_KEY: +++++ Pairwise key +++++\n")); ++ ++ pbssid=get_bssid(&padapter->mlmepriv); ++ stainfo=rtw_get_stainfo(&padapter->stapriv, pbssid); ++ ++ if((stainfo!=NULL)&&(padapter->securitypriv.dot11AuthAlgrthm==dot11AuthAlgrthm_8021X)){ ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("OID_802_11_ADD_KEY:( stainfo!=NULL)&&(Adapter->securitypriv.dot11AuthAlgrthm==dot11AuthAlgrthm_8021X)\n")); ++ encryptionalgo=stainfo->dot118021XPrivacy; ++ } ++ else{ ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("OID_802_11_ADD_KEY: stainfo==NULL)||(Adapter->securitypriv.dot11AuthAlgrthm!=dot11AuthAlgrthm_8021X)\n")); ++ encryptionalgo=padapter->securitypriv.dot11PrivacyAlgrthm; ++ } ++ ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("rtw_set_802_11_add_key: (encryptionalgo ==%d)!\n",encryptionalgo )); ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("rtw_set_802_11_add_key: (Adapter->securitypriv.dot11PrivacyAlgrthm ==%d)!\n",padapter->securitypriv.dot11PrivacyAlgrthm)); ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("rtw_set_802_11_add_key: (Adapter->securitypriv.dot11AuthAlgrthm ==%d)!\n",padapter->securitypriv.dot11AuthAlgrthm)); ++ ++ if((stainfo!=NULL)){ ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("rtw_set_802_11_add_key: (stainfo->dot118021XPrivacy ==%d)!\n", stainfo->dot118021XPrivacy)); ++ } ++ ++ if(key->KeyIndex & 0x000000FF){ ++ // The key index is specified in the lower 8 bits by values of zero to 255. ++ // The key index should be set to zero for a Pairwise key, and the driver should fail with ++ // NDIS_STATUS_INVALID_DATA if the lower 8 bits is not zero ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,(" key->KeyIndex & 0x000000FF.\n")); ++ ret= _FAIL; ++ goto exit; ++ } ++ ++ // check BSSID ++ if (IS_MAC_ADDRESS_BROADCAST(key->BSSID) == _TRUE){ ++ ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("MacAddr_isBcst(key->BSSID)\n")); ++ ret= _FALSE; ++ goto exit; ++ } ++ ++ // Check key length for TKIP. ++ //if(encryptionAlgorithm == RT_ENC_TKIP_ENCRYPTION && key->KeyLength != 32) ++ if((encryptionalgo== _TKIP_)&& (key->KeyLength != 32)){ ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("TKIP KeyLength:0x%x != 32\n", key->KeyLength)); ++ ret=_FAIL; ++ goto exit; ++ ++ } ++ ++ // Check key length for AES. ++ if((encryptionalgo== _AES_)&& (key->KeyLength != 16)) { ++ // For our supplicant, EAPPkt9x.vxd, cannot differentiate TKIP and AES case. ++ if(key->KeyLength == 32) { ++ key->KeyLength = 16; ++ } else { ++ ret= _FAIL; ++ goto exit; ++ } ++ } ++ ++ // Check key length for WEP. For NDTEST, 2005.01.27, by rcnjko. ++ if( (encryptionalgo== _WEP40_|| encryptionalgo== _WEP104_) && (key->KeyLength != 5 || key->KeyLength != 13)) { ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("WEP KeyLength:0x%x != 5 or 13\n", key->KeyLength)); ++ ret=_FAIL; ++ goto exit; ++ } ++ ++ bgroup = _FALSE; ++ ++ // Check the pairwise key. Added by Annie, 2005-07-06. ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("------------------------------------------\n")); ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("[Pairwise Key set]\n")); ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("------------------------------------------\n")); ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("key index: 0x%8x(0x%8x)\n", key->KeyIndex,(key->KeyIndex&0x3))); ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("key Length: %d\n", key->KeyLength)); ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("------------------------------------------\n")); ++ ++ } ++ else ++ { ++ // Group key - KeyIndex(BIT30==0) ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("OID_802_11_ADD_KEY: +++++ Group key +++++\n")); ++ ++ ++ // when add wep key through add key and didn't assigned encryption type before ++ if((padapter->securitypriv.ndisauthtype<=3)&&(padapter->securitypriv.dot118021XGrpPrivacy==0)) ++ { ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("keylen=%d( Adapter->securitypriv.dot11PrivacyAlgrthm=%x )padapter->securitypriv.dot118021XGrpPrivacy(%x)\n", key->KeyLength,padapter->securitypriv.dot11PrivacyAlgrthm,padapter->securitypriv.dot118021XGrpPrivacy)); ++ ++ switch(key->KeyLength) ++ { ++ case 5: ++ padapter->securitypriv.dot11PrivacyAlgrthm=_WEP40_; ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("Adapter->securitypriv.dot11PrivacyAlgrthm= %x key->KeyLength=%u\n", padapter->securitypriv.dot11PrivacyAlgrthm,key->KeyLength)); ++ break; ++ case 13: ++ padapter->securitypriv.dot11PrivacyAlgrthm=_WEP104_; ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("Adapter->securitypriv.dot11PrivacyAlgrthm= %x key->KeyLength=%u\n", padapter->securitypriv.dot11PrivacyAlgrthm,key->KeyLength)); ++ break; ++ default: ++ padapter->securitypriv.dot11PrivacyAlgrthm=_NO_PRIVACY_; ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("Adapter->securitypriv.dot11PrivacyAlgrthm= %x key->KeyLength=%u \n", padapter->securitypriv.dot11PrivacyAlgrthm,key->KeyLength)); ++ break; ++ } ++ ++ encryptionalgo=padapter->securitypriv.dot11PrivacyAlgrthm; ++ ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,(" Adapter->securitypriv.dot11PrivacyAlgrthm=%x\n", padapter->securitypriv.dot11PrivacyAlgrthm)); ++ ++ } ++ else ++ { ++ encryptionalgo=padapter->securitypriv.dot118021XGrpPrivacy; ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("( Adapter->securitypriv.dot11PrivacyAlgrthm=%x )encryptionalgo(%x)=padapter->securitypriv.dot118021XGrpPrivacy(%x)keylen=%d\n", padapter->securitypriv.dot11PrivacyAlgrthm,encryptionalgo,padapter->securitypriv.dot118021XGrpPrivacy,key->KeyLength)); ++ ++ } ++ ++ if((check_fwstate(&padapter->mlmepriv, WIFI_ADHOC_STATE)==_TRUE) && (IS_MAC_ADDRESS_BROADCAST(key->BSSID) == _FALSE)) { ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,(" IBSS but BSSID is not Broadcast Address.\n")); ++ ret= _FAIL; ++ goto exit; ++ } ++ ++ // Check key length for TKIP ++ if((encryptionalgo== _TKIP_) && (key->KeyLength != 32)) { ++ ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,(" TKIP GTK KeyLength:%u != 32\n", key->KeyLength)); ++ ret= _FAIL; ++ goto exit; ++ ++ } else if(encryptionalgo== _AES_ && (key->KeyLength != 16 && key->KeyLength != 32) ) { ++ ++ // Check key length for AES ++ // For NDTEST, we allow keylen=32 in this case. 2005.01.27, by rcnjko. ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("<=== SetInfo, OID_802_11_ADD_KEY: AES GTK KeyLength:%u != 16 or 32\n", key->KeyLength)); ++ ret= _FAIL; ++ goto exit; ++ } ++ ++ // Change the key length for EAPPkt9x.vxd. Added by Annie, 2005-11-03. ++ if((encryptionalgo== _AES_) && (key->KeyLength == 32) ) { ++ key->KeyLength = 16; ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("AES key length changed: %u\n", key->KeyLength) ); ++ } ++ ++ if(key->KeyIndex & 0x8000000) {//error ??? 0x8000_0000 ++ bgrouptkey = _TRUE; ++ } ++ ++ if((check_fwstate(&padapter->mlmepriv, WIFI_ADHOC_STATE)==_TRUE)&&(check_fwstate(&padapter->mlmepriv, _FW_LINKED)==_TRUE)) ++ { ++ bgrouptkey = _TRUE; ++ } ++ ++ bgroup = _TRUE; ++ ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("------------------------------------------\n") ); ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("[Group Key set]\n") ); ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("------------------------------------------\n")) ; ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("key index: 0x%8x(0x%8x)\n", key->KeyIndex,(key->KeyIndex&0x3))); ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("key Length: %d\n", key->KeyLength)) ; ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("------------------------------------------\n")); ++ ++ } ++ ++ // If WEP encryption algorithm, just call rtw_set_802_11_add_wep(). ++ if((padapter->securitypriv.dot11AuthAlgrthm !=dot11AuthAlgrthm_8021X)&&(encryptionalgo== _WEP40_ || encryptionalgo== _WEP104_)) ++ { ++ u8 ret; ++ u32 keyindex; ++ u32 len = FIELD_OFFSET(NDIS_802_11_KEY, KeyMaterial) + key->KeyLength; ++ NDIS_802_11_WEP *wep = &padapter->securitypriv.ndiswep; ++ ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("OID_802_11_ADD_KEY: +++++ WEP key +++++\n")); ++ ++ wep->Length = len; ++ keyindex = key->KeyIndex&0x7fffffff; ++ wep->KeyIndex = keyindex ; ++ wep->KeyLength = key->KeyLength; ++ ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("OID_802_11_ADD_KEY:Before memcpy \n")); ++ ++ _rtw_memcpy(wep->KeyMaterial, key->KeyMaterial, key->KeyLength); ++ _rtw_memcpy(&(padapter->securitypriv.dot11DefKey[keyindex].skey[0]), key->KeyMaterial, key->KeyLength); ++ ++ padapter->securitypriv.dot11DefKeylen[keyindex]=key->KeyLength; ++ padapter->securitypriv.dot11PrivacyKeyIndex=keyindex; ++ ++ ret = rtw_set_802_11_add_wep(padapter, wep); ++ ++ goto exit; ++ ++ } ++ ++ if(key->KeyIndex & 0x20000000){ ++ // SetRSC ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("OID_802_11_ADD_KEY: +++++ SetRSC+++++\n")); ++ if(bgroup == _TRUE) ++ { ++ NDIS_802_11_KEY_RSC keysrc=key->KeyRSC & 0x00FFFFFFFFFFFFULL; ++ _rtw_memcpy(&padapter->securitypriv.dot11Grprxpn, &keysrc, 8); ++ } ++ else ++ { ++ NDIS_802_11_KEY_RSC keysrc=key->KeyRSC & 0x00FFFFFFFFFFFFULL; ++ _rtw_memcpy(&padapter->securitypriv.dot11Grptxpn, &keysrc, 8); ++ } ++ ++ } ++ ++ // Indicate this key idx is used for TX ++ // Save the key in KeyMaterial ++ if(bgroup == _TRUE) // Group transmit key ++ { ++ int res; ++ ++ if(bgrouptkey == _TRUE) ++ { ++ padapter->securitypriv.dot118021XGrpKeyid=(u8)key->KeyIndex; ++ } ++ ++ if((key->KeyIndex&0x3) == 0){ ++ ret = _FAIL; ++ goto exit; ++ } ++ ++ _rtw_memset(&padapter->securitypriv.dot118021XGrpKey[(u8)((key->KeyIndex) & 0x03)], 0, 16); ++ _rtw_memset(&padapter->securitypriv.dot118021XGrptxmickey[(u8)((key->KeyIndex) & 0x03)], 0, 16); ++ _rtw_memset(&padapter->securitypriv.dot118021XGrprxmickey[(u8)((key->KeyIndex) & 0x03)], 0, 16); ++ ++ if((key->KeyIndex & 0x10000000)) ++ { ++ _rtw_memcpy(&padapter->securitypriv.dot118021XGrptxmickey[(u8)((key->KeyIndex) & 0x03)], key->KeyMaterial + 16, 8); ++ _rtw_memcpy(&padapter->securitypriv.dot118021XGrprxmickey[(u8)((key->KeyIndex) & 0x03)], key->KeyMaterial + 24, 8); ++ ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("\n rtw_set_802_11_add_key:rx mic :0x%02x:0x%02x:0x%02x:0x%02x:0x%02x:0x%02x:0x%02x:0x%02x\n", ++ padapter->securitypriv.dot118021XGrprxmickey[(u8)((key->KeyIndex) & 0x03)].skey[0],padapter->securitypriv.dot118021XGrprxmickey[(u8)((key->KeyIndex-1) & 0x03)].skey[1], ++ padapter->securitypriv.dot118021XGrprxmickey[(u8)((key->KeyIndex) & 0x03)].skey[2],padapter->securitypriv.dot118021XGrprxmickey[(u8)((key->KeyIndex-1) & 0x03)].skey[3], ++ padapter->securitypriv.dot118021XGrprxmickey[(u8)((key->KeyIndex) & 0x03)].skey[4],padapter->securitypriv.dot118021XGrprxmickey[(u8)((key->KeyIndex-1) & 0x03)].skey[5], ++ padapter->securitypriv.dot118021XGrprxmickey[(u8)((key->KeyIndex) & 0x03)].skey[6],padapter->securitypriv.dot118021XGrprxmickey[(u8)((key->KeyIndex-1) & 0x03)].skey[7])); ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("\n rtw_set_802_11_add_key:set Group mic key!!!!!!!!\n")); ++ ++ } ++ else ++ { ++ _rtw_memcpy(&padapter->securitypriv.dot118021XGrptxmickey[(u8)((key->KeyIndex) & 0x03)], key->KeyMaterial + 24, 8); ++ _rtw_memcpy(&padapter->securitypriv.dot118021XGrprxmickey[(u8)((key->KeyIndex) & 0x03)], key->KeyMaterial + 16, 8); ++ ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("\n rtw_set_802_11_add_key:rx mic :0x%02x:0x%02x:0x%02x:0x%02x:0x%02x:0x%02x:0x%02x:0x%02x\n", ++ padapter->securitypriv.dot118021XGrprxmickey[(u8)((key->KeyIndex) & 0x03)].skey[0],padapter->securitypriv.dot118021XGrprxmickey[(u8)((key->KeyIndex-1) & 0x03)].skey[1], ++ padapter->securitypriv.dot118021XGrprxmickey[(u8)((key->KeyIndex) & 0x03)].skey[2],padapter->securitypriv.dot118021XGrprxmickey[(u8)((key->KeyIndex-1) & 0x03)].skey[3], ++ padapter->securitypriv.dot118021XGrprxmickey[(u8)((key->KeyIndex) & 0x03)].skey[4],padapter->securitypriv.dot118021XGrprxmickey[(u8)((key->KeyIndex-1) & 0x03)].skey[5], ++ padapter->securitypriv.dot118021XGrprxmickey[(u8)((key->KeyIndex) & 0x03)].skey[6],padapter->securitypriv.dot118021XGrprxmickey[(u8)((key->KeyIndex-1) & 0x03)].skey[7])); ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("\n rtw_set_802_11_add_key:set Group mic key!!!!!!!!\n")); ++ ++ } ++ ++ //set group key by index ++ _rtw_memcpy(&padapter->securitypriv.dot118021XGrpKey[(u8)((key->KeyIndex) & 0x03)], key->KeyMaterial, key->KeyLength); ++ ++ key->KeyIndex=key->KeyIndex & 0x03; ++ ++ padapter->securitypriv.binstallGrpkey=_TRUE; ++ ++ padapter->securitypriv.bcheck_grpkey=_FALSE; ++ ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("reset group key")); ++ ++ res=rtw_set_key(padapter,&padapter->securitypriv, key->KeyIndex, 1); ++ ++ if(res==_FAIL) ++ ret= _FAIL; ++ ++ goto exit; ++ ++ } ++ else // Pairwise Key ++ { ++ u8 res; ++ ++ pbssid=get_bssid(&padapter->mlmepriv); ++ stainfo=rtw_get_stainfo(&padapter->stapriv , pbssid ); ++ ++ if(stainfo!=NULL) ++ { ++ _rtw_memset( &stainfo->dot118021x_UncstKey, 0, 16);// clear keybuffer ++ ++ _rtw_memcpy(&stainfo->dot118021x_UncstKey, key->KeyMaterial, 16); ++ ++ if(encryptionalgo== _TKIP_) ++ { ++ padapter->securitypriv.busetkipkey=_FALSE; ++ ++ //_set_timer(&padapter->securitypriv.tkip_timer, 50); ++ ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("\n ==========_set_timer\n")); ++ ++ // if TKIP, save the Receive/Transmit MIC key in KeyMaterial[128-255] ++ if((key->KeyIndex & 0x10000000)){ ++ _rtw_memcpy(&stainfo->dot11tkiptxmickey, key->KeyMaterial + 16, 8); ++ _rtw_memcpy(&stainfo->dot11tkiprxmickey, key->KeyMaterial + 24, 8); ++ ++ } else { ++ _rtw_memcpy(&stainfo->dot11tkiptxmickey, key->KeyMaterial + 24, 8); ++ _rtw_memcpy(&stainfo->dot11tkiprxmickey, key->KeyMaterial + 16, 8); ++ ++ } ++ ++ } ++ else if(encryptionalgo == _AES_) ++ { ++ ++ } ++ ++ ++ //Set key to CAM through H2C command ++ if(bgrouptkey)//never go to here ++ { ++ res=rtw_setstakey_cmd(padapter, (unsigned char *)stainfo, _FALSE); ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("\n rtw_set_802_11_add_key:rtw_setstakey_cmd(group)\n")); ++ } ++ else{ ++ res=rtw_setstakey_cmd(padapter, (unsigned char *)stainfo, _TRUE); ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("\n rtw_set_802_11_add_key:rtw_setstakey_cmd(unicast)\n")); ++ } ++ ++ if(res ==_FALSE) ++ ret= _FAIL; ++ ++ } ++ ++ } ++ ++exit: ++ ++_func_exit_; ++ ++ return ret; ++} ++ ++u8 rtw_set_802_11_remove_key(_adapter* padapter, NDIS_802_11_REMOVE_KEY *key){ ++ ++ uint encryptionalgo; ++ u8 * pbssid; ++ struct sta_info *stainfo; ++ u8 bgroup = (key->KeyIndex & 0x4000000) > 0 ? _FALSE: _TRUE; ++ u8 keyIndex = (u8)key->KeyIndex & 0x03; ++ u8 ret=_SUCCESS; ++ ++_func_enter_; ++ ++ if ((key->KeyIndex & 0xbffffffc) > 0) { ++ ret=_FAIL; ++ goto exit; ++ } ++ ++ if (bgroup == _TRUE) { ++ encryptionalgo= padapter->securitypriv.dot118021XGrpPrivacy; ++ // clear group key by index ++ //NdisZeroMemory(Adapter->MgntInfo.SecurityInfo.KeyBuf[keyIndex], MAX_WEP_KEY_LEN); ++ //Adapter->MgntInfo.SecurityInfo.KeyLen[keyIndex] = 0; ++ ++ _rtw_memset(&padapter->securitypriv.dot118021XGrpKey[keyIndex], 0, 16); ++ ++ //! \todo Send a H2C Command to Firmware for removing this Key in CAM Entry. ++ ++ } else { ++ ++ pbssid=get_bssid(&padapter->mlmepriv); ++ stainfo=rtw_get_stainfo(&padapter->stapriv , pbssid ); ++ if(stainfo !=NULL){ ++ encryptionalgo=stainfo->dot118021XPrivacy; ++ ++ // clear key by BSSID ++ _rtw_memset(&stainfo->dot118021x_UncstKey, 0, 16); ++ ++ //! \todo Send a H2C Command to Firmware for disable this Key in CAM Entry. ++ ++ } ++ else{ ++ ret= _FAIL; ++ goto exit; ++ } ++ } ++ ++exit: ++ ++_func_exit_; ++ ++ return _TRUE; ++ ++} ++ ++/* ++* rtw_get_network_max_rate - ++* @adapter: pointer to _adapter structure ++* @bss: ++* ++* Return 0 or Mbps ++*/ ++u16 rtw_get_network_max_rate(_adapter *adapter, WLAN_BSSID_EX *bss) ++{ ++ int i =0; ++ u8 *p; ++ u16 rate = 0, max_rate = 0, ht_cap=_FALSE; ++ u32 ht_ielen = 0; ++ struct mlme_priv *pmlmepriv = &adapter->mlmepriv; ++ struct rtw_ieee80211_ht_cap *pht_capie; ++ u8 bw_40MHz=0, short_GI=0; ++ u16 mcs_rate=0; ++ u8 rf_type = 0; ++ struct registry_priv *pregpriv = &adapter->registrypriv; ++ ++#ifdef CONFIG_MP_INCLUDED ++ if (check_fwstate(pmlmepriv, WIFI_MP_STATE) == _TRUE) ++ return 0; ++#endif ++ ++ if((check_fwstate(pmlmepriv, _FW_LINKED) != _TRUE) ++ && (check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) != _TRUE)) ++ return 0; ++ ++ ++ p = rtw_get_ie(&bss->IEs[12], _HT_CAPABILITY_IE_, &ht_ielen, bss->IELength-12); ++ if(p && ht_ielen>0) ++ { ++ ht_cap = _TRUE; ++ pht_capie = (struct rtw_ieee80211_ht_cap *)(p+2); ++ ++ _rtw_memcpy(&mcs_rate , pht_capie->supp_mcs_set, 2); ++ ++ bw_40MHz = (pht_capie->cap_info&IEEE80211_HT_CAP_SUP_WIDTH) ? 1:0; ++ short_GI = (pht_capie->cap_info&(IEEE80211_HT_CAP_SGI_20|IEEE80211_HT_CAP_SGI_40)) ? 1:0; ++ } ++ ++ while( (bss->SupportedRates[i]!=0) && (bss->SupportedRates[i]!=0xFF)) ++ { ++ rate = bss->SupportedRates[i]&0x7F; ++ if(rate>max_rate) ++ max_rate = rate; ++ i++; ++ } ++ ++ //TODO: should consider case of WEP and TKIP ++ if(ht_cap == _TRUE) ++ { ++ adapter->HalFunc.GetHwRegHandler(adapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type)); ++ if(rf_type == RF_1T1R) ++ max_rate = (bw_40MHz) ? ((short_GI)?150:135):((short_GI)?72:65); ++ else ++ max_rate = (bw_40MHz) ? ((short_GI)?300:270):((short_GI)?144:130); ++ } ++ else ++ { ++ max_rate/=2; ++ } ++ ++ return max_rate; ++} ++ ++/* ++* rtw_set_scan_mode - ++* @adapter: pointer to _adapter structure ++* @scan_mode: ++* ++* Return _SUCCESS or _FAIL ++*/ ++int rtw_set_scan_mode(_adapter *adapter, RT_SCAN_TYPE scan_mode) ++{ ++ if(scan_mode != SCAN_ACTIVE && scan_mode != SCAN_PASSIVE) ++ return _FAIL; ++ ++ adapter->mlmepriv.scan_mode = scan_mode; ++ ++ return _SUCCESS; ++} ++ ++/* ++* rtw_set_channel_plan - ++* @adapter: pointer to _adapter structure ++* @channel_plan: ++* ++* Return _SUCCESS or _FAIL ++*/ ++int rtw_set_channel_plan(_adapter *adapter, u8 channel_plan) ++{ ++ struct registry_priv *pregistrypriv = &adapter->registrypriv; ++ struct mlme_priv *pmlmepriv = &adapter->mlmepriv; ++ ++ //handle by cmd_thread to sync with scan operation ++ return rtw_set_chplan_cmd(adapter, channel_plan, 1); ++} ++ ++/* ++* rtw_set_country - ++* @adapter: pointer to _adapter structure ++* @country_code: string of country code ++* ++* Return _SUCCESS or _FAIL ++*/ ++int rtw_set_country(_adapter *adapter, const char *country_code) ++{ ++ int channel_plan = RT_CHANNEL_DOMAIN_FCC; ++ ++ //TODO: should have a table to match country code and RT_CHANNEL_DOMAIN ++ //TODO: should consider 2-character and 3-character counter code ++ if(0 == strcmp(country_code, "US")) ++ channel_plan = RT_CHANNEL_DOMAIN_FCC; ++ else if(0 == strcmp(country_code, "EU")) ++ channel_plan = RT_CHANNEL_DOMAIN_ETSI; ++ else if(0 == strcmp(country_code, "JP")) ++ channel_plan = RT_CHANNEL_DOMAIN_MKK; ++ else ++ DBG_871X("%s unknown country_code:%s\n", __FUNCTION__, country_code); ++ ++ return rtw_set_channel_plan(adapter, channel_plan); ++} ++ +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/core/rtw_iol.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/core/rtw_iol.c 2013-07-26 19:36:05.000000000 +0000 +@@ -0,0 +1,266 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++ ++#include ++ ++#ifdef CONFIG_IOL ++struct xmit_frame *rtw_IOL_accquire_xmit_frame(ADAPTER *adapter) ++{ ++ struct xmit_frame *xmit_frame; ++ struct xmit_buf *xmitbuf; ++ struct pkt_attrib *pattrib; ++ struct xmit_priv *pxmitpriv = &(adapter->xmitpriv); ++ ++#if 1 ++ if ((xmit_frame = rtw_alloc_xmitframe(pxmitpriv)) == NULL) ++ { ++ DBG_871X("%s rtw_alloc_xmitframe return null\n", __FUNCTION__); ++ goto exit; ++ } ++ ++ if ((xmitbuf = rtw_alloc_xmitbuf(pxmitpriv)) == NULL) ++ { ++ DBG_871X("%s rtw_alloc_xmitbuf return null\n", __FUNCTION__); ++ rtw_free_xmitframe_ex(pxmitpriv, xmit_frame); ++ xmit_frame=NULL; ++ goto exit; ++ } ++ ++ xmit_frame->frame_tag = MGNT_FRAMETAG; ++ xmit_frame->pxmitbuf = xmitbuf; ++ xmit_frame->buf_addr = xmitbuf->pbuf; ++ xmitbuf->priv_data = xmit_frame; ++ ++ pattrib = &xmit_frame->attrib; ++ update_mgntframe_attrib(adapter, pattrib); ++ pattrib->qsel = 0x10; ++ pattrib->pktlen = pattrib->last_txcmdsz = 0; ++ ++#else ++ if ((xmit_frame = alloc_mgtxmitframe(pxmitpriv)) == NULL) ++ { ++ DBG_871X("%s alloc_mgtxmitframe return null\n", __FUNCTION__); ++ } ++ else { ++ pattrib = &xmit_frame->attrib; ++ update_mgntframe_attrib(adapter, pattrib); ++ pattrib->qsel = 0x10; ++ pattrib->pktlen = pattrib->last_txcmdsz = 0; ++ } ++#endif ++ ++exit: ++ return xmit_frame; ++} ++ ++ ++int rtw_IOL_append_cmds(struct xmit_frame *xmit_frame, u8 *IOL_cmds, u32 cmd_len) ++{ ++ struct pkt_attrib *pattrib = &xmit_frame->attrib; ++ u16 buf_offset; ++ u32 ori_len; ++ ++//Todo: bulkout without this offset ++#ifdef CONFIG_USB_HCI ++ buf_offset = TXDESC_OFFSET; ++#else ++ buf_offset = 0; ++#endif ++ ++ ori_len = buf_offset+pattrib->pktlen; ++ ++ //check if the io_buf can accommodate new cmds ++ if(ori_len + cmd_len + 8 > MAX_XMITBUF_SZ) { ++ DBG_871X("%s %u is large than MAX_XMITBUF_SZ:%u, can't accommodate new cmds\n", __FUNCTION__ ++ , ori_len + cmd_len + 8, MAX_XMITBUF_SZ); ++ return _FAIL; ++ } ++ ++ _rtw_memcpy(xmit_frame->buf_addr + buf_offset + pattrib->pktlen, IOL_cmds, cmd_len); ++ pattrib->pktlen += cmd_len; ++ pattrib->last_txcmdsz += cmd_len; ++ ++ //DBG_871X("%s ori:%u + cmd_len:%u = %u\n", __FUNCTION__, ori_len, cmd_len, buf_offset+pattrib->pktlen); ++ ++ return _SUCCESS; ++} ++ ++int rtw_IOL_append_LLT_cmd(struct xmit_frame *xmit_frame, u8 page_boundary) ++{ ++ IOL_CMD cmd = {0x0, IOL_CMD_LLT, 0x0, 0x0}; ++ ++ RTW_PUT_BE32((u8*)&cmd.value, (u32)page_boundary); ++ ++ return rtw_IOL_append_cmds(xmit_frame, (u8*)&cmd, 8); ++} ++ ++int _rtw_IOL_append_WB_cmd(struct xmit_frame *xmit_frame, u16 addr, u8 value) ++{ ++ IOL_CMD cmd = {0x0, IOL_CMD_WB_REG, 0x0, 0x0}; ++ ++ RTW_PUT_BE16((u8*)&cmd.address, (u16)addr); ++ RTW_PUT_BE32((u8*)&cmd.value, (u32)value); ++ ++ return rtw_IOL_append_cmds(xmit_frame, (u8*)&cmd, 8); ++} ++ ++int _rtw_IOL_append_WW_cmd(struct xmit_frame *xmit_frame, u16 addr, u16 value) ++{ ++ IOL_CMD cmd = {0x0, IOL_CMD_WW_REG, 0x0, 0x0}; ++ ++ RTW_PUT_BE16((u8*)&cmd.address, (u16)addr); ++ RTW_PUT_BE32((u8*)&cmd.value, (u32)value); ++ ++ return rtw_IOL_append_cmds(xmit_frame, (u8*)&cmd, 8); ++} ++ ++int _rtw_IOL_append_WD_cmd(struct xmit_frame *xmit_frame, u16 addr, u32 value) ++{ ++ IOL_CMD cmd = {0x0, IOL_CMD_WD_REG, 0x0, 0x0}; ++ u8* pos = (u8 *)&cmd; ++ ++ RTW_PUT_BE16((u8*)&cmd.address, (u16)addr); ++ RTW_PUT_BE32((u8*)&cmd.value, (u32)value); ++ ++ return rtw_IOL_append_cmds(xmit_frame, (u8*)&cmd, 8); ++} ++ ++#ifdef DBG_IO ++int dbg_rtw_IOL_append_WB_cmd(struct xmit_frame *xmit_frame, u16 addr, u8 value, const char *caller, const int line) ++{ ++ if(addr + 1 > DBG_IO_WRITE_SNIFF_ADDR_START && addr <= DBG_IO_WRITE_SNIFF_ADDR_END) ++ DBG_871X("DBG_IO %s:%d IOL_WB(0x%04x, 0x%02x)\n", caller, line, addr, value); ++ ++ return _rtw_IOL_append_WB_cmd(xmit_frame, addr, value); ++} ++ ++int dbg_rtw_IOL_append_WW_cmd(struct xmit_frame *xmit_frame, u16 addr, u16 value, const char *caller, const int line) ++{ ++ if(addr + 2 > DBG_IO_WRITE_SNIFF_ADDR_START && addr <= DBG_IO_WRITE_SNIFF_ADDR_END) ++ DBG_871X("DBG_IO %s:%d IOL_WW(0x%04x, 0x%04x)\n", caller, line, addr, value); ++ ++ return _rtw_IOL_append_WW_cmd(xmit_frame, addr, value); ++} ++ ++int dbg_rtw_IOL_append_WD_cmd(struct xmit_frame *xmit_frame, u16 addr, u32 value, const char *caller, const int line) ++{ ++ if(addr + 4 > DBG_IO_WRITE_SNIFF_ADDR_START && addr <= DBG_IO_WRITE_SNIFF_ADDR_END) ++ DBG_871X("DBG_IO %s:%d IOL_WD(0x%04x, 0x%08x)\n", caller, line, addr, value); ++ ++ return _rtw_IOL_append_WD_cmd(xmit_frame, addr, value); ++} ++#endif ++ ++int rtw_IOL_append_DELAY_US_cmd(struct xmit_frame *xmit_frame, u16 us) ++{ ++ IOL_CMD cmd = {0x0, IOL_CMD_DELAY_US, 0x0, 0x0}; ++ ++ RTW_PUT_BE32((u8*)&cmd.value, (u32)us); ++ ++ //DBG_871X("%s %u\n", __FUNCTION__, us); ++ ++ return rtw_IOL_append_cmds(xmit_frame, (u8*)&cmd, 8); ++} ++ ++int rtw_IOL_append_DELAY_MS_cmd(struct xmit_frame *xmit_frame, u16 ms) ++{ ++ IOL_CMD cmd = {0x0, IOL_CMD_DELAY_MS, 0x0, 0x0}; ++ ++ RTW_PUT_BE32((u8*)&cmd.value, (u32)ms); ++ ++ //DBG_871X("%s %u\n", __FUNCTION__, ms); ++ ++ return rtw_IOL_append_cmds(xmit_frame, (u8*)&cmd, 8); ++} ++ ++int rtw_IOL_append_END_cmd(struct xmit_frame *xmit_frame) ++{ ++ struct pkt_attrib *pattrib = &xmit_frame->attrib; ++ u16 buf_offset; ++ u32 ori_len; ++ IOL_CMD end_cmd = {0x0, IOL_CMD_END, 0x0, 0x0}; ++ ++//Todo: bulkout without this offset ++#ifdef CONFIG_USB_HCI ++ buf_offset = TXDESC_OFFSET; ++#else ++ buf_offset = 0; ++#endif ++ ++ ori_len = buf_offset+pattrib->pktlen; ++ ++ //check if the io_buf can accommodate new cmds ++ if(ori_len + 8 > MAX_XMITBUF_SZ) { ++ DBG_871X("%s %u is large than MAX_XMITBUF_SZ:%u, can't accommodate end cmd\n", __FUNCTION__ ++ , ori_len + 8, MAX_XMITBUF_SZ); ++ return _FAIL; ++ } ++ ++ _rtw_memcpy(xmit_frame->buf_addr + buf_offset + pattrib->pktlen, (u8*)&end_cmd, 8); ++ pattrib->pktlen += 8; ++ pattrib->last_txcmdsz += 8; ++ ++ //DBG_871X("%s ori:%u + 8 = %u\n", __FUNCTION__ , ori_len, buf_offset+pattrib->pktlen); ++ ++ return _SUCCESS; ++} ++ ++int rtw_IOL_exec_cmds_sync(ADAPTER *adapter, struct xmit_frame *xmit_frame, u32 max_wating_ms) ++{ ++ if(adapter->HalFunc.IOL_exec_cmds_sync) ++ return adapter->HalFunc.IOL_exec_cmds_sync(adapter, xmit_frame, max_wating_ms); ++ ++ return _FAIL; ++} ++ ++int rtw_IOL_exec_cmd_array_sync(PADAPTER adapter, u8 *IOL_cmds, u32 cmd_num, u32 max_wating_ms) ++{ ++ struct xmit_frame *xmit_frame; ++ ++ if((xmit_frame=rtw_IOL_accquire_xmit_frame(adapter)) == NULL) ++ return _FAIL; ++ ++ if(rtw_IOL_append_cmds(xmit_frame, IOL_cmds, cmd_num<<3) == _FAIL) ++ return _FAIL; ++ ++ return rtw_IOL_exec_cmds_sync(adapter, xmit_frame, max_wating_ms); ++} ++ ++int rtw_IOL_exec_empty_cmds_sync(ADAPTER *adapter, u32 max_wating_ms) ++{ ++ IOL_CMD end_cmd = {0x0, IOL_CMD_END, 0x0, 0x0}; ++ return rtw_IOL_exec_cmd_array_sync(adapter, (u8*)&end_cmd, 1, max_wating_ms); ++} ++ ++bool rtw_IOL_applied(ADAPTER *adapter) ++{ ++ if(adapter->registrypriv.force_iol) ++ return _TRUE; ++ ++#ifdef CONFIG_USB_HCI ++ if(!adapter->dvobjpriv.ishighspeed) ++ return _TRUE; ++#endif ++ ++ return _FALSE; ++} ++ ++#endif //CONFIG_IOL ++ +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/core/rtw_mlme.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/core/rtw_mlme.c 2013-07-26 19:36:05.000000000 +0000 +@@ -0,0 +1,3549 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++******************************************************************************/ ++#define _RTW_MLME_C_ ++ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++extern void indicate_wx_scan_complete_event(_adapter *padapter); ++extern u8 rtw_do_join(_adapter * padapter); ++ ++sint _rtw_init_mlme_priv (_adapter* padapter) ++{ ++ sint i; ++ u8 *pbuf; ++ struct wlan_network *pnetwork; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ sint res = _SUCCESS; ++ ++_func_enter_; ++ ++ // We don't need to memset padapter->XXX to zero, because adapter is allocated by rtw_zvmalloc(). ++ //_rtw_memset((u8 *)pmlmepriv, 0, sizeof(struct mlme_priv)); ++ ++ pmlmepriv->nic_hdl = (u8 *)padapter; ++ ++ pmlmepriv->pscanned = NULL; ++ pmlmepriv->fw_state = 0; ++ pmlmepriv->cur_network.network.InfrastructureMode = Ndis802_11AutoUnknown; ++ pmlmepriv->scan_mode=SCAN_ACTIVE;// 1: active, 0: pasive. Maybe someday we should rename this varable to "active_mode" (Jeff) ++ ++ _rtw_spinlock_init(&(pmlmepriv->lock)); ++ _rtw_init_queue(&(pmlmepriv->free_bss_pool)); ++ _rtw_init_queue(&(pmlmepriv->scanned_queue)); ++ ++ set_scanned_network_val(pmlmepriv, 0); ++ ++ _rtw_memset(&pmlmepriv->assoc_ssid,0,sizeof(NDIS_802_11_SSID)); ++ ++ pbuf = rtw_zvmalloc(MAX_BSS_CNT * (sizeof(struct wlan_network))); ++ ++ if (pbuf == NULL){ ++ res=_FAIL; ++ goto exit; ++ } ++ pmlmepriv->free_bss_buf = pbuf; ++ ++ pnetwork = (struct wlan_network *)pbuf; ++ ++ for(i = 0; i < MAX_BSS_CNT; i++) ++ { ++ _rtw_init_listhead(&(pnetwork->list)); ++ ++ rtw_list_insert_tail(&(pnetwork->list), &(pmlmepriv->free_bss_pool.queue)); ++ ++ pnetwork++; ++ } ++ ++ //allocate DMA-able/Non-Page memory for cmd_buf and rsp_buf ++ ++ #ifdef CONFIG_SET_SCAN_DENY_TIMER ++ ATOMIC_SET(&pmlmepriv->set_scan_deny, 0); ++ #endif ++ ++ rtw_init_mlme_timer(padapter); ++ ++exit: ++ ++_func_exit_; ++ ++ return res; ++} ++ ++void rtw_mfree_mlme_priv_lock (struct mlme_priv *pmlmepriv) ++{ ++ _rtw_spinlock_free(&pmlmepriv->lock); ++ _rtw_spinlock_free(&(pmlmepriv->free_bss_pool.lock)); ++ _rtw_spinlock_free(&(pmlmepriv->scanned_queue.lock)); ++} ++ ++static void rtw_free_mlme_ie_data(u8 **ppie, u32 *plen) ++{ ++ if(*ppie) ++ { ++ _rtw_mfree(*ppie, *plen); ++ *plen = 0; ++ *ppie=NULL; ++ } ++} ++ ++void rtw_free_mlme_priv_ie_data(struct mlme_priv *pmlmepriv) ++{ ++#if defined (CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME) ++ rtw_free_mlme_ie_data(&pmlmepriv->wps_beacon_ie, &pmlmepriv->wps_beacon_ie_len); ++ rtw_free_mlme_ie_data(&pmlmepriv->wps_probe_req_ie, &pmlmepriv->wps_probe_req_ie_len); ++ rtw_free_mlme_ie_data(&pmlmepriv->wps_probe_resp_ie, &pmlmepriv->wps_probe_resp_ie_len); ++ rtw_free_mlme_ie_data(&pmlmepriv->wps_assoc_resp_ie, &pmlmepriv->wps_assoc_resp_ie_len); ++ ++ rtw_free_mlme_ie_data(&pmlmepriv->p2p_beacon_ie, &pmlmepriv->p2p_beacon_ie_len); ++ rtw_free_mlme_ie_data(&pmlmepriv->p2p_probe_req_ie, &pmlmepriv->p2p_probe_req_ie_len); ++ rtw_free_mlme_ie_data(&pmlmepriv->p2p_probe_resp_ie, &pmlmepriv->p2p_probe_resp_ie_len); ++ rtw_free_mlme_ie_data(&pmlmepriv->p2p_go_probe_resp_ie, &pmlmepriv->p2p_go_probe_resp_ie_len); ++ rtw_free_mlme_ie_data(&pmlmepriv->p2p_assoc_req_ie, &pmlmepriv->p2p_assoc_req_ie_len); ++#endif ++} ++ ++void _rtw_free_mlme_priv (struct mlme_priv *pmlmepriv) ++{ ++_func_enter_; ++ ++ rtw_free_mlme_priv_ie_data(pmlmepriv); ++ ++ if(pmlmepriv){ ++ rtw_mfree_mlme_priv_lock (pmlmepriv); ++ ++ if (pmlmepriv->free_bss_buf) { ++ rtw_vmfree(pmlmepriv->free_bss_buf, MAX_BSS_CNT * sizeof(struct wlan_network)); ++ } ++ } ++_func_exit_; ++} ++ ++sint _rtw_enqueue_network(_queue *queue, struct wlan_network *pnetwork) ++{ ++ _irqL irqL; ++ ++_func_enter_; ++ ++ if (pnetwork == NULL) ++ goto exit; ++ ++ _enter_critical_bh(&queue->lock, &irqL); ++ ++ rtw_list_insert_tail(&pnetwork->list, &queue->queue); ++ ++ _exit_critical_bh(&queue->lock, &irqL); ++ ++exit: ++ ++_func_exit_; ++ ++ return _SUCCESS; ++} ++ ++struct wlan_network *_rtw_dequeue_network(_queue *queue) ++{ ++ _irqL irqL; ++ ++ struct wlan_network *pnetwork; ++ ++_func_enter_; ++ ++ _enter_critical_bh(&queue->lock, &irqL); ++ ++ if (_rtw_queue_empty(queue) == _TRUE) ++ ++ pnetwork = NULL; ++ ++ else ++ { ++ pnetwork = LIST_CONTAINOR(get_next(&queue->queue), struct wlan_network, list); ++ ++ rtw_list_delete(&(pnetwork->list)); ++ } ++ ++ _exit_critical_bh(&queue->lock, &irqL); ++ ++_func_exit_; ++ ++ return pnetwork; ++} ++ ++struct wlan_network *_rtw_alloc_network(struct mlme_priv *pmlmepriv )//(_queue *free_queue) ++{ ++ _irqL irqL; ++ struct wlan_network *pnetwork; ++ _queue *free_queue = &pmlmepriv->free_bss_pool; ++ _list* plist = NULL; ++ ++_func_enter_; ++ ++ _enter_critical_bh(&free_queue->lock, &irqL); ++ ++ if (_rtw_queue_empty(free_queue) == _TRUE) { ++ pnetwork=NULL; ++ goto exit; ++ } ++ plist = get_next(&(free_queue->queue)); ++ ++ pnetwork = LIST_CONTAINOR(plist , struct wlan_network, list); ++ ++ rtw_list_delete(&pnetwork->list); ++ ++ RT_TRACE(_module_rtl871x_mlme_c_, _drv_info_, ("_rtw_alloc_network: ptr=%p\n", plist)); ++ pnetwork->network_type = 0; ++ pnetwork->fixed = _FALSE; ++ pnetwork->last_scanned = rtw_get_current_time(); ++ pnetwork->aid=0; ++ pnetwork->join_res=0; ++ ++ pmlmepriv->num_of_scanned ++; ++ ++exit: ++ _exit_critical_bh(&free_queue->lock, &irqL); ++ ++_func_exit_; ++ ++ return pnetwork; ++} ++ ++void _rtw_free_network(struct mlme_priv *pmlmepriv ,struct wlan_network *pnetwork, u8 isfreeall) ++{ ++ u32 curr_time, delta_time; ++ u32 lifetime = SCANQUEUE_LIFETIME; ++ _irqL irqL; ++ _queue *free_queue = &(pmlmepriv->free_bss_pool); ++ ++_func_enter_; ++ ++ if (pnetwork == NULL) ++ goto exit; ++ ++ if (pnetwork->fixed == _TRUE) ++ goto exit; ++ ++ curr_time = rtw_get_current_time(); ++ ++ if ( (check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE)==_TRUE ) || ++ (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE)==_TRUE ) ) ++ lifetime = 1; ++ ++ if(!isfreeall) ++ { ++#ifdef PLATFORM_WINDOWS ++ ++ delta_time = (curr_time -pnetwork->last_scanned)/10; ++ ++ if(delta_time < lifetime*1000000)// unit:usec ++ { ++ goto exit; ++ } ++ ++#endif ++ ++#ifdef PLATFORM_LINUX ++ ++ delta_time = (curr_time -pnetwork->last_scanned)/HZ; ++ ++ if(delta_time < lifetime)// unit:sec ++ { ++ goto exit; ++ } ++ ++#endif ++ } ++ ++ _enter_critical_bh(&free_queue->lock, &irqL); ++ ++ rtw_list_delete(&(pnetwork->list)); ++ ++ rtw_list_insert_tail(&(pnetwork->list),&(free_queue->queue)); ++ ++ pmlmepriv->num_of_scanned --; ++ ++ ++ //DBG_871X("_rtw_free_network:SSID=%s\n", pnetwork->network.Ssid.Ssid); ++ ++ _exit_critical_bh(&free_queue->lock, &irqL); ++ ++exit: ++ ++_func_exit_; ++ ++} ++ ++void _rtw_free_network_nolock(struct mlme_priv *pmlmepriv, struct wlan_network *pnetwork) ++{ ++ ++ _queue *free_queue = &(pmlmepriv->free_bss_pool); ++ ++_func_enter_; ++ ++ if (pnetwork == NULL) ++ goto exit; ++ ++ if (pnetwork->fixed == _TRUE) ++ goto exit; ++ ++ //_enter_critical(&free_queue->lock, &irqL); ++ ++ rtw_list_delete(&(pnetwork->list)); ++ ++ rtw_list_insert_tail(&(pnetwork->list), get_list_head(free_queue)); ++ ++ pmlmepriv->num_of_scanned --; ++ ++ //_exit_critical(&free_queue->lock, &irqL); ++ ++exit: ++ ++_func_exit_; ++ ++} ++ ++ ++/* ++ return the wlan_network with the matching addr ++ ++ Shall be calle under atomic context... to avoid possible racing condition... ++*/ ++struct wlan_network *_rtw_find_network(_queue *scanned_queue, u8 *addr) ++{ ++ ++ //_irqL irqL; ++ _list *phead, *plist; ++ struct wlan_network *pnetwork = NULL; ++ u8 zero_addr[ETH_ALEN] = {0,0,0,0,0,0}; ++ ++_func_enter_; ++ ++ if(_rtw_memcmp(zero_addr, addr, ETH_ALEN)){ ++ pnetwork=NULL; ++ goto exit; ++ } ++ ++ //_enter_critical_bh(&scanned_queue->lock, &irqL); ++ ++ phead = get_list_head(scanned_queue); ++ plist = get_next(phead); ++ ++ while (plist != phead) ++ { ++ pnetwork = LIST_CONTAINOR(plist, struct wlan_network ,list); ++ ++ if (_rtw_memcmp(addr, pnetwork->network.MacAddress, ETH_ALEN) == _TRUE) ++ break; ++ ++ plist = get_next(plist); ++ } ++ ++ if(plist == phead) ++ pnetwork = NULL; ++ ++ //_exit_critical_bh(&scanned_queue->lock, &irqL); ++ ++exit: ++ ++_func_exit_; ++ ++ return pnetwork; ++ ++} ++ ++ ++void _rtw_free_network_queue(_adapter *padapter, u8 isfreeall) ++{ ++ _irqL irqL; ++ _list *phead, *plist; ++ struct wlan_network *pnetwork; ++ struct mlme_priv* pmlmepriv = &padapter->mlmepriv; ++ _queue *scanned_queue = &pmlmepriv->scanned_queue; ++ _queue *free_queue = &pmlmepriv->free_bss_pool; ++ u8 *mybssid = get_bssid(pmlmepriv); ++ ++_func_enter_; ++ ++ ++ _enter_critical_bh(&scanned_queue->lock, &irqL); ++ ++ phead = get_list_head(scanned_queue); ++ plist = get_next(phead); ++ ++ while (rtw_end_of_queue_search(phead, plist) == _FALSE) ++ { ++ ++ pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list); ++ ++ plist = get_next(plist); ++ ++ _rtw_free_network(pmlmepriv,pnetwork, isfreeall); ++ ++ } ++ ++ _exit_critical_bh(&scanned_queue->lock, &irqL); ++ ++_func_exit_; ++ ++} ++ ++ ++ ++ ++sint rtw_if_up(_adapter *padapter) { ++ ++ sint res; ++_func_enter_; ++ ++ if( padapter->bDriverStopped || padapter->bSurpriseRemoved || ++ (check_fwstate(&padapter->mlmepriv, _FW_LINKED)== _FALSE)){ ++ RT_TRACE(_module_rtl871x_mlme_c_, _drv_info_, ("rtw_if_up:bDriverStopped(%d) OR bSurpriseRemoved(%d)", padapter->bDriverStopped, padapter->bSurpriseRemoved)); ++ res=_FALSE; ++ } ++ else ++ res= _TRUE; ++ ++_func_exit_; ++ return res; ++} ++ ++ ++void rtw_generate_random_ibss(u8* pibss) ++{ ++ u32 curtime = rtw_get_current_time(); ++ ++_func_enter_; ++ pibss[0] = 0x02; //in ad-hoc mode bit1 must set to 1 ++ pibss[1] = 0x11; ++ pibss[2] = 0x87; ++ pibss[3] = (u8)(curtime & 0xff) ;//p[0]; ++ pibss[4] = (u8)((curtime>>8) & 0xff) ;//p[1]; ++ pibss[5] = (u8)((curtime>>16) & 0xff) ;//p[2]; ++_func_exit_; ++ return; ++} ++ ++u8 *rtw_get_capability_from_ie(u8 *ie) ++{ ++ return (ie + 8 + 2); ++} ++ ++ ++u16 rtw_get_capability(WLAN_BSSID_EX *bss) ++{ ++ u16 val; ++_func_enter_; ++ ++ _rtw_memcpy((u8 *)&val, rtw_get_capability_from_ie(bss->IEs), 2); ++ ++_func_exit_; ++ return le16_to_cpu(val); ++} ++ ++u8 *rtw_get_timestampe_from_ie(u8 *ie) ++{ ++ return (ie + 0); ++} ++ ++u8 *rtw_get_beacon_interval_from_ie(u8 *ie) ++{ ++ return (ie + 8); ++} ++ ++ ++int rtw_init_mlme_priv (_adapter *padapter)//(struct mlme_priv *pmlmepriv) ++{ ++ int res; ++_func_enter_; ++ res = _rtw_init_mlme_priv(padapter);// (pmlmepriv); ++_func_exit_; ++ return res; ++} ++ ++void rtw_free_mlme_priv (struct mlme_priv *pmlmepriv) ++{ ++_func_enter_; ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("rtw_free_mlme_priv\n")); ++ _rtw_free_mlme_priv (pmlmepriv); ++_func_exit_; ++} ++ ++int rtw_enqueue_network(_queue *queue, struct wlan_network *pnetwork) ++{ ++ int res; ++_func_enter_; ++ res = _rtw_enqueue_network(queue, pnetwork); ++_func_exit_; ++ return res; ++} ++ ++ ++ ++static struct wlan_network *rtw_dequeue_network(_queue *queue) ++{ ++ struct wlan_network *pnetwork; ++_func_enter_; ++ pnetwork = _rtw_dequeue_network(queue); ++_func_exit_; ++ return pnetwork; ++} ++ ++ ++struct wlan_network *rtw_alloc_network(struct mlme_priv *pmlmepriv )//(_queue *free_queue) ++{ ++ struct wlan_network *pnetwork; ++_func_enter_; ++ pnetwork = _rtw_alloc_network(pmlmepriv); ++_func_exit_; ++ return pnetwork; ++} ++ ++void rtw_free_network(struct mlme_priv *pmlmepriv, struct wlan_network *pnetwork, u8 is_freeall)//(struct wlan_network *pnetwork, _queue *free_queue) ++{ ++_func_enter_; ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("rtw_free_network==> ssid = %s \n\n" , pnetwork->network.Ssid.Ssid)); ++ _rtw_free_network(pmlmepriv, pnetwork, is_freeall); ++_func_exit_; ++} ++ ++ ++void rtw_free_network_nolock(struct mlme_priv *pmlmepriv, struct wlan_network *pnetwork ) ++{ ++_func_enter_; ++ //RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("rtw_free_network==> ssid = %s \n\n" , pnetwork->network.Ssid.Ssid)); ++ _rtw_free_network_nolock(pmlmepriv, pnetwork); ++_func_exit_; ++} ++ ++ ++void rtw_free_network_queue(_adapter* dev, u8 isfreeall) ++{ ++_func_enter_; ++ _rtw_free_network_queue(dev, isfreeall); ++_func_exit_; ++} ++ ++/* ++ return the wlan_network with the matching addr ++ ++ Shall be calle under atomic context... to avoid possible racing condition... ++*/ ++struct wlan_network *rtw_find_network(_queue *scanned_queue, u8 *addr) ++{ ++ struct wlan_network *pnetwork = _rtw_find_network(scanned_queue, addr); ++ ++ return pnetwork; ++} ++ ++int rtw_is_same_ibss(_adapter *adapter, struct wlan_network *pnetwork) ++{ ++ int ret=_TRUE; ++ struct security_priv *psecuritypriv = &adapter->securitypriv; ++ ++ if ( (psecuritypriv->dot11PrivacyAlgrthm != _NO_PRIVACY_ ) && ++ ( pnetwork->network.Privacy == 0 ) ) ++ { ++ ret=_FALSE; ++ } ++ else if((psecuritypriv->dot11PrivacyAlgrthm == _NO_PRIVACY_ ) && ++ ( pnetwork->network.Privacy == 1 ) ) ++ { ++ ret=_FALSE; ++ } ++ else ++ { ++ ret=_TRUE; ++ } ++ ++ return ret; ++ ++} ++ ++inline int is_same_ess(WLAN_BSSID_EX *a, WLAN_BSSID_EX *b) ++{ ++ //RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("(%s,%d)(%s,%d)\n", ++ // a->Ssid.Ssid,a->Ssid.SsidLength,b->Ssid.Ssid,b->Ssid.SsidLength)); ++ return (a->Ssid.SsidLength == b->Ssid.SsidLength) ++ && _rtw_memcmp(a->Ssid.Ssid, b->Ssid.Ssid, a->Ssid.SsidLength)==_TRUE; ++} ++ ++static int is_same_network(WLAN_BSSID_EX *src, WLAN_BSSID_EX *dst) ++{ ++ u16 s_cap, d_cap; ++ ++_func_enter_; ++ ++#ifdef PLATFORM_OS_XP ++ if ( ((uint)dst) <= 0x7fffffff || ++ ((uint)src) <= 0x7fffffff || ++ ((uint)&s_cap) <= 0x7fffffff || ++ ((uint)&d_cap) <= 0x7fffffff) ++ { ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("\n@@@@ error address of dst\n")); ++ ++ KeBugCheckEx(0x87110000, (ULONG_PTR)dst, (ULONG_PTR)src,(ULONG_PTR)&s_cap, (ULONG_PTR)&d_cap); ++ ++ return _FALSE; ++ } ++#endif ++ ++ ++ _rtw_memcpy((u8 *)&s_cap, rtw_get_capability_from_ie(src->IEs), 2); ++ _rtw_memcpy((u8 *)&d_cap, rtw_get_capability_from_ie(dst->IEs), 2); ++ ++ ++ s_cap = le16_to_cpu(s_cap); ++ d_cap = le16_to_cpu(d_cap); ++ ++_func_exit_; ++ ++ return ((src->Ssid.SsidLength == dst->Ssid.SsidLength) && ++ // (src->Configuration.DSConfig == dst->Configuration.DSConfig) && ++ ( (_rtw_memcmp(src->MacAddress, dst->MacAddress, ETH_ALEN)) == _TRUE) && ++ ( (_rtw_memcmp(src->Ssid.Ssid, dst->Ssid.Ssid, src->Ssid.SsidLength)) == _TRUE) && ++ ((s_cap & WLAN_CAPABILITY_IBSS) == ++ (d_cap & WLAN_CAPABILITY_IBSS)) && ++ ((s_cap & WLAN_CAPABILITY_BSS) == ++ (d_cap & WLAN_CAPABILITY_BSS))); ++ ++} ++ ++struct wlan_network * rtw_get_oldest_wlan_network(_queue *scanned_queue) ++{ ++ _list *plist, *phead; ++ ++ ++ struct wlan_network *pwlan = NULL; ++ struct wlan_network *oldest = NULL; ++_func_enter_; ++ phead = get_list_head(scanned_queue); ++ ++ plist = get_next(phead); ++ ++ while(1) ++ { ++ ++ if (rtw_end_of_queue_search(phead,plist)== _TRUE) ++ break; ++ ++ pwlan= LIST_CONTAINOR(plist, struct wlan_network, list); ++ ++ if(pwlan->fixed!=_TRUE) ++ { ++ if (oldest == NULL ||time_after(oldest->last_scanned, pwlan->last_scanned)) ++ oldest = pwlan; ++ } ++ ++ plist = get_next(plist); ++ } ++_func_exit_; ++ return oldest; ++ ++} ++ ++static void update_network(WLAN_BSSID_EX *dst, WLAN_BSSID_EX *src,_adapter * padapter) ++{ ++ u32 last_evm = 0, tmpVal; ++ u8 ss_ori = dst->PhyInfo.SignalStrength; ++ u8 sq_ori = dst->PhyInfo.SignalQuality; ++ long rssi_ori = dst->Rssi; ++ ++ u8 ss_smp = src->PhyInfo.SignalStrength; ++ u8 sq_smp = src->PhyInfo.SignalQuality; ++ long rssi_smp = src->Rssi; ++ ++_func_enter_; ++ ++#ifdef CONFIG_ANTENNA_DIVERSITY ++ padapter->HalFunc.SwAntDivCompareHandler(padapter, dst, src); ++#endif ++ ++ #if defined(DBG_RX_SIGNAL_DISPLAY_PROCESSING) && 1 ++ if(strcmp(dst->Ssid.Ssid, DBG_RX_SIGNAL_DISPLAY_SSID_MONITORED) == 0) { ++ DBG_871X("%s %s("MAC_FMT", ch%u) ss_ori:%3u, sq_ori:%3u, rssi_ori:%3ld, ss_smp:%3u, sq_smp:%3u, rssi_smp:%3ld\n" ++ , __FUNCTION__ ++ , src->Ssid.Ssid, MAC_ARG(src->MacAddress), src->Configuration.DSConfig ++ ,ss_ori, sq_ori, rssi_ori ++ ,ss_smp, sq_smp, rssi_smp ++ ); ++ } ++ #endif ++ ++ ++ //Update signal strength first. Alwlays using the newest value will cause large vibration of scan result's signal strength ++ //The rule below is 1/5 for sample value, 4/5 for history value ++ if (check_fwstate(&padapter->mlmepriv, _FW_LINKED) && is_same_network(&(padapter->mlmepriv.cur_network.network), src)) { ++ //Because we've process the rx phy info in rtl8192c_process_phy_info/rtl8192d_process_phy_info, ++ //we can just take the recvpriv's value ++ src->PhyInfo.SignalStrength = padapter->recvpriv.signal_strength; ++ src->PhyInfo.SignalQuality = padapter->recvpriv.signal_qual; ++ // the rssi value here is undecorated, and will be used for antenna diversity ++ if(src->PhyInfo.SignalQuality != 101) ++ src->Rssi = (src->Rssi+dst->Rssi*4)/5; ++ else ++ src->Rssi = dst->Rssi; ++ } ++ else { ++ if(src->PhyInfo.SignalQuality != 101) { ++ // handle bss info receving from the right channel ++ src->PhyInfo.SignalStrength = ((u32)(src->PhyInfo.SignalStrength)+(u32)(dst->PhyInfo.SignalStrength)*4)/5; ++ src->PhyInfo.SignalQuality = ((u32)(src->PhyInfo.SignalQuality)+(u32)(dst->PhyInfo.SignalQuality)*4)/5; ++ src->Rssi = (src->Rssi+dst->Rssi*4)/5; // the rssi value here is undecorated, and will be used for antenna diversity ++ } else { ++ // bss info not receving from the right channel, use the original RX signal infos ++ src->PhyInfo.SignalStrength = dst->PhyInfo.SignalStrength; ++ src->PhyInfo.SignalQuality = dst->PhyInfo.SignalQuality; ++ src->Rssi = dst->Rssi; ++ } ++ ++ } ++ ++ ++ _rtw_memcpy((u8 *)dst, (u8 *)src, get_WLAN_BSSID_EX_sz(src)); ++ ++ src->PhyInfo.SignalStrength = ss_smp; ++ src->PhyInfo.SignalQuality = sq_smp; ++ src->Rssi = rssi_smp; ++ ++ #if defined(DBG_RX_SIGNAL_DISPLAY_PROCESSING) && 1 ++ if(strcmp(dst->Ssid.Ssid, DBG_RX_SIGNAL_DISPLAY_SSID_MONITORED) == 0) { ++ DBG_871X("%s %s("MAC_FMT"), SignalStrength:%u, SignalQuality:%u, RawRSSI:%ld\n" ++ , __FUNCTION__ ++ , dst->Ssid.Ssid, MAC_ARG(dst->MacAddress), dst->PhyInfo.SignalStrength, dst->PhyInfo.SignalQuality, dst->Rssi); ++ } ++ #endif ++ ++#if 0 // old codes, may be useful one day... ++// DBG_8192C("update_network: rssi=0x%lx dst->Rssi=%d ,dst->Rssi=0x%lx , src->Rssi=0x%lx",(dst->Rssi+src->Rssi)/2,dst->Rssi,dst->Rssi,src->Rssi); ++ if (check_fwstate(&padapter->mlmepriv, _FW_LINKED) && is_same_network(&(padapter->mlmepriv.cur_network.network), src)) ++ { ++ ++ //DBG_8192C("b:ssid=%s update_network: src->rssi=0x%d padapter->recvpriv.ui_rssi=%d\n",src->Ssid.Ssid,src->Rssi,padapter->recvpriv.signal); ++ if(padapter->recvpriv.signal_qual_data.total_num++ >= PHY_LINKQUALITY_SLID_WIN_MAX) ++ { ++ padapter->recvpriv.signal_qual_data.total_num = PHY_LINKQUALITY_SLID_WIN_MAX; ++ last_evm = padapter->recvpriv.signal_qual_data.elements[padapter->recvpriv.signal_qual_data.index]; ++ padapter->recvpriv.signal_qual_data.total_val -= last_evm; ++ } ++ padapter->recvpriv.signal_qual_data.total_val += query_rx_pwr_percentage(src->Rssi); ++ ++ padapter->recvpriv.signal_qual_data.elements[padapter->recvpriv.signal_qual_data.index++] = query_rx_pwr_percentage(src->Rssi); ++ if(padapter->recvpriv.signal_qual_data.index >= PHY_LINKQUALITY_SLID_WIN_MAX) ++ padapter->recvpriv.signal_qual_data.index = 0; ++ ++ //DBG_8192C("Total SQ=%d pattrib->signal_qual= %d\n", padapter->recvpriv.signal_qual_data.total_val, src->Rssi); ++ ++ // <1> Showed on UI for user,in percentage. ++ tmpVal = padapter->recvpriv.signal_qual_data.total_val/padapter->recvpriv.signal_qual_data.total_num; ++ padapter->recvpriv.signal=(u8)tmpVal;//Link quality ++ ++ src->Rssi= translate_percentage_to_dbm(padapter->recvpriv.signal) ; ++ } ++ else{ ++// DBG_8192C("ELSE:ssid=%s update_network: src->rssi=0x%d dst->rssi=%d\n",src->Ssid.Ssid,src->Rssi,dst->Rssi); ++ src->Rssi=(src->Rssi +dst->Rssi)/2;//dBM ++ } ++ ++// DBG_8192C("a:update_network: src->rssi=0x%d padapter->recvpriv.ui_rssi=%d\n",src->Rssi,padapter->recvpriv.signal); ++ ++#endif ++ ++_func_exit_; ++} ++ ++static void update_current_network(_adapter *adapter, WLAN_BSSID_EX *pnetwork) ++{ ++ struct mlme_priv *pmlmepriv = &(adapter->mlmepriv); ++ ++_func_enter_; ++ ++#ifdef PLATFORM_OS_XP ++ if ((unsigned long)(&(pmlmepriv->cur_network.network)) < 0x7ffffff) ++ { ++ KeBugCheckEx(0x87111c1c, (ULONG_PTR)(&(pmlmepriv->cur_network.network)), 0, 0,0); ++ } ++#endif ++ ++ if ( (check_fwstate(pmlmepriv, _FW_LINKED)== _TRUE) && (is_same_network(&(pmlmepriv->cur_network.network), pnetwork))) ++ { ++ //RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,"Same Network\n"); ++ ++ //if(pmlmepriv->cur_network.network.IELength<= pnetwork->IELength) ++ { ++ update_network(&(pmlmepriv->cur_network.network), pnetwork,adapter); ++ rtw_update_protection(adapter, (pmlmepriv->cur_network.network.IEs) + sizeof (NDIS_802_11_FIXED_IEs), ++ pmlmepriv->cur_network.network.IELength); ++ } ++ } ++ ++_func_exit_; ++ ++} ++ ++ ++/* ++ ++Caller must hold pmlmepriv->lock first. ++ ++ ++*/ ++void rtw_update_scanned_network(_adapter *adapter, WLAN_BSSID_EX *target) ++{ ++ _irqL irqL; ++ _list *plist, *phead; ++ ULONG bssid_ex_sz; ++ struct mlme_priv *pmlmepriv = &(adapter->mlmepriv); ++ _queue *queue = &(pmlmepriv->scanned_queue); ++ struct wlan_network *pnetwork = NULL; ++ struct wlan_network *oldest = NULL; ++ ++_func_enter_; ++ _enter_critical_bh(&queue->lock, &irqL); ++ phead = get_list_head(queue); ++ plist = get_next(phead); ++ ++ while(1) ++ { ++ if (rtw_end_of_queue_search(phead,plist)== _TRUE) ++ break; ++ ++ pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list); ++ ++ if ((unsigned long)(pnetwork) < 0x7ffffff) ++ { ++#ifdef PLATFORM_OS_XP ++ KeBugCheckEx(0x87111c1c, (ULONG_PTR)pnetwork, 0, 0,0); ++#endif ++ } ++ ++ if (is_same_network(&(pnetwork->network), target)) ++ break; ++ ++ if ((oldest == ((struct wlan_network *)0)) || ++ time_after(oldest->last_scanned, pnetwork->last_scanned)) ++ oldest = pnetwork; ++ ++ plist = get_next(plist); ++ ++ } ++ ++ ++ /* If we didn't find a match, then get a new network slot to initialize ++ * with this beacon's information */ ++ if (rtw_end_of_queue_search(phead,plist)== _TRUE) { ++ ++ if (_rtw_queue_empty(&(pmlmepriv->free_bss_pool)) == _TRUE) { ++ /* If there are no more slots, expire the oldest */ ++ //list_del_init(&oldest->list); ++ pnetwork = oldest; ++ ++#ifdef CONFIG_ANTENNA_DIVERSITY ++ //target->PhyInfo.Optimum_antenna = pHalData->CurAntenna;//optimum_antenna=>For antenna diversity ++ adapter->HalFunc.GetHalDefVarHandler(adapter, HAL_DEF_CURRENT_ANTENNA, &(target->PhyInfo.Optimum_antenna)); ++#endif ++ _rtw_memcpy(&(pnetwork->network), target, get_WLAN_BSSID_EX_sz(target)); ++ pnetwork->last_scanned = rtw_get_current_time(); ++ //variable initialize ++ pnetwork->fixed = _FALSE; ++ pnetwork->last_scanned = rtw_get_current_time(); ++ ++ pnetwork->network_type = 0; ++ pnetwork->aid=0; ++ pnetwork->join_res=0; ++ } ++ else { ++ /* Otherwise just pull from the free list */ ++ ++ pnetwork = rtw_alloc_network(pmlmepriv); // will update scan_time ++ ++ if(pnetwork==NULL){ ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("\n\n\nsomething wrong here\n\n\n")); ++ goto exit; ++ } ++ ++ bssid_ex_sz = get_WLAN_BSSID_EX_sz(target); ++ target->Length = bssid_ex_sz; ++#ifdef CONFIG_ANTENNA_DIVERSITY ++ //target->PhyInfo.Optimum_antenna = pHalData->CurAntenna; ++ adapter->HalFunc.GetHalDefVarHandler(adapter, HAL_DEF_CURRENT_ANTENNA, &(target->PhyInfo.Optimum_antenna)); ++#endif ++ _rtw_memcpy(&(pnetwork->network), target, bssid_ex_sz ); ++ ++ rtw_list_insert_tail(&(pnetwork->list),&(queue->queue)); ++ ++ } ++ } ++ else { ++ /* we have an entry and we are going to update it. But this entry may ++ * be already expired. In this case we do the same as we found a new ++ * net and call the new_net handler ++ */ ++ //target.Reserved[0]==1, means that scaned network is a bcn frame. ++ if((pnetwork->network.IELength>target->IELength) && (target->Reserved[0]==1)) ++ goto exit; ++ ++ update_network(&(pnetwork->network),target,adapter); ++ ++ pnetwork->last_scanned = rtw_get_current_time(); ++ ++ } ++ ++exit: ++ _exit_critical_bh(&queue->lock, &irqL); ++_func_exit_; ++ ++} ++ ++ ++void rtw_add_network(_adapter *adapter, WLAN_BSSID_EX *pnetwork) ++{ ++ _irqL irqL; ++ struct mlme_priv *pmlmepriv = &(((_adapter *)adapter)->mlmepriv); ++ //_queue *queue = &(pmlmepriv->scanned_queue); ++ ++_func_enter_; ++ ++ //_enter_critical_bh(&queue->lock, &irqL); ++ ++ #if defined(CONFIG_P2P) && defined(CONFIG_P2P_REMOVE_GROUP_INFO) ++ rtw_WLAN_BSSID_EX_remove_p2p_attr(pnetwork, P2P_ATTR_GROUP_INFO); ++ #endif ++ ++ update_current_network(adapter, pnetwork); ++ ++ rtw_update_scanned_network(adapter, pnetwork); ++ ++ //_exit_critical_bh(&queue->lock, &irqL); ++ ++_func_exit_; ++} ++ ++//select the desired network based on the capability of the (i)bss. ++// check items: (1) security ++// (2) network_type ++// (3) WMM ++// (4) HT ++// (5) others ++int rtw_is_desired_network(_adapter *adapter, struct wlan_network *pnetwork) ++{ ++ struct security_priv *psecuritypriv = &adapter->securitypriv; ++ struct mlme_priv *pmlmepriv = &adapter->mlmepriv; ++ u32 desired_encmode; ++ u32 privacy; ++ ++ //u8 wps_ie[512]; ++ uint wps_ielen; ++ ++ int bselected = _TRUE; ++ ++ desired_encmode = psecuritypriv->ndisencryptstatus; ++ privacy = pnetwork->network.Privacy; ++ ++ if(psecuritypriv->wps_phase == _TRUE) ++ { ++ if(rtw_get_wps_ie(pnetwork->network.IEs+_FIXED_IE_LENGTH_, pnetwork->network.IELength-_FIXED_IE_LENGTH_, NULL, &wps_ielen)!=NULL) ++ { ++ return _TRUE; ++ } ++ else ++ { ++ return _FALSE; ++ } ++ } ++ if (adapter->registrypriv.wifi_spec == 1) //for correct flow of 8021X to do.... ++ { ++ if ((desired_encmode == Ndis802_11EncryptionDisabled) && (privacy != 0)) ++ bselected = _FALSE; ++ } ++ ++ ++ if ((desired_encmode != Ndis802_11EncryptionDisabled) && (privacy == 0)) { ++ DBG_871X("desired_encmode: %d, privacy: %d\n", desired_encmode, privacy); ++ bselected = _FALSE; ++ } ++ ++ if(check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE) ++ { ++ if(pnetwork->network.InfrastructureMode != pmlmepriv->cur_network.network.InfrastructureMode) ++ bselected = _FALSE; ++ } ++ ++ ++ return bselected; ++} ++ ++/* TODO: Perry : For Power Management */ ++void rtw_atimdone_event_callback(_adapter *adapter , u8 *pbuf) ++{ ++ ++_func_enter_; ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("receive atimdone_evet\n")); ++_func_exit_; ++ return; ++} ++ ++ ++void rtw_survey_event_callback(_adapter *adapter, u8 *pbuf) ++{ ++ _irqL irqL; ++ u32 len; ++ WLAN_BSSID_EX *pnetwork; ++ struct mlme_priv *pmlmepriv = &(adapter->mlmepriv); ++ ++_func_enter_; ++ ++ pnetwork = (WLAN_BSSID_EX *)pbuf; ++ ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_info_,("rtw_survey_event_callback, ssid=%s\n", pnetwork->Ssid.Ssid)); ++ ++#ifdef CONFIG_RTL8712 ++ //endian_convert ++ pnetwork->Length = le32_to_cpu(pnetwork->Length); ++ pnetwork->Ssid.SsidLength = le32_to_cpu(pnetwork->Ssid.SsidLength); ++ pnetwork->Privacy =le32_to_cpu( pnetwork->Privacy); ++ pnetwork->Rssi = le32_to_cpu(pnetwork->Rssi); ++ pnetwork->NetworkTypeInUse =le32_to_cpu(pnetwork->NetworkTypeInUse); ++ pnetwork->Configuration.ATIMWindow = le32_to_cpu(pnetwork->Configuration.ATIMWindow); ++ pnetwork->Configuration.BeaconPeriod = le32_to_cpu(pnetwork->Configuration.BeaconPeriod); ++ pnetwork->Configuration.DSConfig =le32_to_cpu(pnetwork->Configuration.DSConfig); ++ pnetwork->Configuration.FHConfig.DwellTime=le32_to_cpu(pnetwork->Configuration.FHConfig.DwellTime); ++ pnetwork->Configuration.FHConfig.HopPattern=le32_to_cpu(pnetwork->Configuration.FHConfig.HopPattern); ++ pnetwork->Configuration.FHConfig.HopSet=le32_to_cpu(pnetwork->Configuration.FHConfig.HopSet); ++ pnetwork->Configuration.FHConfig.Length=le32_to_cpu(pnetwork->Configuration.FHConfig.Length); ++ pnetwork->Configuration.Length = le32_to_cpu(pnetwork->Configuration.Length); ++ pnetwork->InfrastructureMode = le32_to_cpu(pnetwork->InfrastructureMode); ++ pnetwork->IELength = le32_to_cpu(pnetwork->IELength); ++#endif ++ ++ len = get_WLAN_BSSID_EX_sz(pnetwork); ++ if(len > (sizeof(WLAN_BSSID_EX))) ++ { ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("\n ****rtw_survey_event_callback: return a wrong bss ***\n")); ++ return; ++ } ++ ++ ++ _enter_critical_bh(&pmlmepriv->lock, &irqL); ++ ++ // update IBSS_network 's timestamp ++ if ((check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE)) == _TRUE) ++ { ++ //RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,"rtw_survey_event_callback : WIFI_ADHOC_MASTER_STATE \n\n"); ++ if(_rtw_memcmp(&(pmlmepriv->cur_network.network.MacAddress), pnetwork->MacAddress, ETH_ALEN)) ++ { ++ struct wlan_network* ibss_wlan = NULL; ++ _irqL irqL; ++ ++ _rtw_memcpy(pmlmepriv->cur_network.network.IEs, pnetwork->IEs, 8); ++ _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); ++ ibss_wlan = rtw_find_network(&pmlmepriv->scanned_queue, pnetwork->MacAddress); ++ if(ibss_wlan) ++ { ++ _rtw_memcpy(ibss_wlan->network.IEs , pnetwork->IEs, 8); ++ _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); ++ goto exit; ++ } ++ _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); ++ } ++ } ++ ++ // lock pmlmepriv->lock when you accessing network_q ++ if ((check_fwstate(pmlmepriv, _FW_UNDER_LINKING)) == _FALSE) ++ { ++ if( pnetwork->Ssid.Ssid[0] == 0 ) ++ { ++ pnetwork->Ssid.SsidLength = 0; ++ } ++ rtw_add_network(adapter, pnetwork); ++ } ++ ++exit: ++ ++ _exit_critical_bh(&pmlmepriv->lock, &irqL); ++ ++_func_exit_; ++ ++ return; ++} ++ ++ ++ ++void rtw_surveydone_event_callback(_adapter *adapter, u8 *pbuf) ++{ ++ _irqL irqL; ++ struct mlme_priv *pmlmepriv = &(adapter->mlmepriv); ++ ++#ifdef CONFIG_MLME_EXT ++ ++ mlmeext_surveydone_event_callback(adapter); ++ ++#endif ++ ++_func_enter_; ++ ++ _enter_critical_bh(&pmlmepriv->lock, &irqL); ++ ++ pmlmepriv->probereq_wpsie_len = 0 ;//reset to zero ++ ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_info_,("rtw_surveydone_event_callback: fw_state:%x\n\n", get_fwstate(pmlmepriv))); ++ ++ if (check_fwstate(pmlmepriv,_FW_UNDER_SURVEY)) ++ { ++ u8 timer_cancelled; ++ ++ _cancel_timer(&pmlmepriv->scan_to_timer, &timer_cancelled); ++ ++ _clr_fwstate_(pmlmepriv, _FW_UNDER_SURVEY); ++ } ++ else { ++ ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("nic status =%x, survey done event comes too late!\n", get_fwstate(pmlmepriv))); ++ } ++ ++ #ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS ++ rtw_set_signal_stat_timer(&adapter->recvpriv); ++ #endif ++ ++ if(pmlmepriv->to_join == _TRUE) ++ { ++ if((check_fwstate(pmlmepriv, WIFI_ADHOC_STATE)==_TRUE) ) ++ { ++ if(check_fwstate(pmlmepriv, _FW_LINKED)==_FALSE) ++ { ++ set_fwstate(pmlmepriv, _FW_UNDER_LINKING); ++ ++ if(rtw_select_and_join_from_scanned_queue(pmlmepriv)==_SUCCESS) ++ { ++ _set_timer(&pmlmepriv->assoc_timer, MAX_JOIN_TIMEOUT ); ++ } ++ else ++ { ++ WLAN_BSSID_EX *pdev_network = &(adapter->registrypriv.dev_network); ++ u8 *pibss = adapter->registrypriv.dev_network.MacAddress; ++ ++ //pmlmepriv->fw_state ^= _FW_UNDER_SURVEY;//because don't set assoc_timer ++ _clr_fwstate_(pmlmepriv, _FW_UNDER_SURVEY); ++ ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("switching to adhoc master\n")); ++ ++ _rtw_memset(&pdev_network->Ssid, 0, sizeof(NDIS_802_11_SSID)); ++ _rtw_memcpy(&pdev_network->Ssid, &pmlmepriv->assoc_ssid, sizeof(NDIS_802_11_SSID)); ++ ++ rtw_update_registrypriv_dev_network(adapter); ++ rtw_generate_random_ibss(pibss); ++ ++ pmlmepriv->fw_state = WIFI_ADHOC_MASTER_STATE; ++ ++ if(rtw_createbss_cmd(adapter)!=_SUCCESS) ++ { ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("Error=>rtw_createbss_cmd status FAIL\n")); ++ } ++ ++ pmlmepriv->to_join = _FALSE; ++ } ++ } ++ } ++ else ++ { ++ int s_ret; ++ set_fwstate(pmlmepriv, _FW_UNDER_LINKING); ++ pmlmepriv->to_join = _FALSE; ++ if(_SUCCESS == (s_ret=rtw_select_and_join_from_scanned_queue(pmlmepriv))) ++ { ++ _set_timer(&pmlmepriv->assoc_timer, MAX_JOIN_TIMEOUT); ++ } ++ else if(s_ret == 2)//there is no need to wait for join ++ { ++ _clr_fwstate_(pmlmepriv, _FW_UNDER_LINKING); ++ rtw_indicate_connect(adapter); ++ } ++ else ++ { ++ #ifdef CONFIG_LAYER2_ROAMING ++ DBG_871X("try_to_join, but select scanning queue fail, to_roaming:%d\n", pmlmepriv->to_roaming); ++ #else ++ DBG_871X("try_to_join, but select scanning queue fail\n"); ++ #endif ++ ++ #ifdef CONFIG_LAYER2_ROAMING ++ if(pmlmepriv->to_roaming!=0) { ++ if( --pmlmepriv->to_roaming == 0 ++ || _SUCCESS != rtw_sitesurvey_cmd(adapter, &pmlmepriv->assoc_ssid, 1) ++ ) { ++ pmlmepriv->to_roaming = 0; ++ rtw_free_assoc_resources(adapter, 1); ++ rtw_indicate_disconnect(adapter); ++ } else { ++ pmlmepriv->to_join = _TRUE; ++ } ++ } ++ #endif ++ _clr_fwstate_(pmlmepriv, _FW_UNDER_LINKING); ++ } ++ } ++ } ++ ++ indicate_wx_scan_complete_event(adapter); ++ //DBG_871X("scan complete in %dms\n",rtw_get_passing_time_ms(pmlmepriv->scan_start_time)); ++ ++ _exit_critical_bh(&pmlmepriv->lock, &irqL); ++ ++#ifdef CONFIG_P2P ++ p2p_ps_wk_cmd(adapter, P2P_PS_SCAN_DONE, 0); ++#endif //CONFIG_P2P ++ ++ rtw_os_xmit_schedule(adapter); ++ ++#ifdef CONFIG_DRVEXT_MODULE_WSC ++ drvext_surveydone_callback(&adapter->drvextpriv); ++#endif ++ ++#ifdef DBG_CONFIG_ERROR_DETECT ++ { ++ struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; ++ if(pmlmeext->sitesurvey_res.bss_cnt == 0){ ++ if(adapter->HalFunc.silentreset) ++ adapter->HalFunc.silentreset(adapter); ++ } ++ } ++ #endif ++ ++#ifdef CONFIG_IOCTL_CFG80211 ++ rtw_cfg80211_surveydone_event_callback(adapter); ++#endif //CONFIG_IOCTL_CFG80211 ++ ++_func_exit_; ++ ++} ++ ++void rtw_dummy_event_callback(_adapter *adapter , u8 *pbuf) ++{ ++ ++} ++ ++void rtw_fwdbg_event_callback(_adapter *adapter , u8 *pbuf) ++{ ++ ++} ++ ++static void free_scanqueue(struct mlme_priv *pmlmepriv) ++{ ++ _irqL irqL, irqL0; ++ _queue *free_queue = &pmlmepriv->free_bss_pool; ++ _queue *scan_queue = &pmlmepriv->scanned_queue; ++ _list *plist, *phead, *ptemp; ++ ++_func_enter_; ++ ++ RT_TRACE(_module_rtl871x_mlme_c_, _drv_notice_, ("+free_scanqueue\n")); ++ _enter_critical_bh(&scan_queue->lock, &irqL0); ++ _enter_critical_bh(&free_queue->lock, &irqL); ++ ++ phead = get_list_head(scan_queue); ++ plist = get_next(phead); ++ ++ while (plist != phead) ++ { ++ ptemp = get_next(plist); ++ rtw_list_delete(plist); ++ rtw_list_insert_tail(plist, &free_queue->queue); ++ plist =ptemp; ++ pmlmepriv->num_of_scanned --; ++ } ++ ++ _exit_critical_bh(&free_queue->lock, &irqL); ++ _exit_critical_bh(&scan_queue->lock, &irqL0); ++ ++_func_exit_; ++} ++ ++/* ++*rtw_free_assoc_resources: the caller has to lock pmlmepriv->lock ++*/ ++void rtw_free_assoc_resources(_adapter *adapter, int lock_scanned_queue) ++{ ++ _irqL irqL; ++ struct wlan_network* pwlan = NULL; ++ struct mlme_priv *pmlmepriv = &adapter->mlmepriv; ++ struct mlme_ext_info *pmlmeinfo = &adapter->mlmeextpriv.mlmext_info; ++ struct sta_priv *pstapriv = &adapter->stapriv; ++ struct wlan_network *tgt_network = &pmlmepriv->cur_network; ++ ++#ifdef CONFIG_TDLS ++ struct tdls_info *ptdlsinfo = &adapter->tdlsinfo; ++#endif //CONFIG_TDLS ++_func_enter_; ++ ++ RT_TRACE(_module_rtl871x_mlme_c_, _drv_notice_, ("+rtw_free_assoc_resources\n")); ++ ++ ++ ++ RT_TRACE(_module_rtl871x_mlme_c_, _drv_info_, ("tgt_network->network.MacAddress="MAC_FMT" ssid=%s\n", ++ MAC_ARG(tgt_network->network.MacAddress), tgt_network->network.Ssid.Ssid)); ++ ++ if(check_fwstate( pmlmepriv, WIFI_STATION_STATE|WIFI_AP_STATE)) ++ { ++ struct sta_info* psta; ++ ++ psta = rtw_get_stainfo(&adapter->stapriv, tgt_network->network.MacAddress); ++ ++#ifdef CONFIG_TDLS ++ if(ptdlsinfo->setup_state != UN_TDLS_STATE) ++ { ++ rtw_tdls_cmd(adapter, myid(&(adapter->eeprompriv)), TDLS_RS_RCR); ++ ptdlsinfo->setup_state = UN_TDLS_STATE; ++ rtw_free_all_stainfo(adapter); ++ _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL); ++ } ++ else ++ { ++ _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL); ++ rtw_free_stainfo(adapter, psta); ++ } ++#else ++ _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL); ++ rtw_free_stainfo(adapter, psta); ++#endif //CONFIG_TDLS ++ ++ _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL); ++ ++ } ++ ++ if(check_fwstate( pmlmepriv, WIFI_ADHOC_STATE|WIFI_ADHOC_MASTER_STATE|WIFI_AP_STATE)) ++ { ++ struct sta_info* psta; ++ ++ rtw_free_all_stainfo(adapter); ++ ++ psta = rtw_get_bcmc_stainfo(adapter); ++ _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL); ++ rtw_free_stainfo(adapter, psta); ++ _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL); ++ ++ rtw_init_bcmc_stainfo(adapter); ++ } ++ ++ if(lock_scanned_queue) ++ _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); ++ ++ pwlan = rtw_find_network(&pmlmepriv->scanned_queue, tgt_network->network.MacAddress); ++ if(pwlan) ++ { ++ pwlan->fixed = _FALSE; ++ } ++ else ++ { ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("rtw_free_assoc_resources : pwlan== NULL \n\n")); ++ } ++ ++ ++ if((check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) && (adapter->stapriv.asoc_sta_count== 1)) ++ /*||check_fwstate(pmlmepriv, WIFI_STATION_STATE)*/) ++ { ++ rtw_free_network_nolock(pmlmepriv, pwlan); ++ } ++ ++ if(lock_scanned_queue) ++ _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); ++ ++ pmlmepriv->key_mask = 0; ++ ++_func_exit_; ++ ++} ++ ++/* ++*rtw_indicate_connect: the caller has to lock pmlmepriv->lock ++*/ ++void rtw_indicate_connect(_adapter *padapter) ++{ ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct xmit_priv *pxmitpriv = &padapter->xmitpriv; ++ ++_func_enter_; ++ ++ RT_TRACE(_module_rtl871x_mlme_c_, _drv_err_, ("+rtw_indicate_connect\n")); ++ ++ pmlmepriv->to_join = _FALSE; ++#ifdef CONFIG_SW_ANTENNA_DIVERSITY ++ padapter->HalFunc.SetHwRegHandler(padapter, HW_VAR_ANTENNA_DIVERSITY_LINK, 0); ++#endif ++ set_fwstate(pmlmepriv, _FW_LINKED); ++ ++ rtw_led_control(padapter, LED_CTL_LINK); ++ ++#ifdef CONFIG_DRVEXT_MODULE ++ if(padapter->drvextpriv.enable_wpa) ++ { ++ indicate_l2_connect(padapter); ++ } ++ else ++#endif ++ { ++ rtw_os_indicate_connect(padapter); ++ } ++ ++ #ifdef CONFIG_LAYER2_ROAMING ++ pmlmepriv->to_roaming=0; ++ #endif ++ ++ #ifdef CONFIG_SET_SCAN_DENY_TIMER ++ rtw_set_scan_deny(pmlmepriv, 3000); ++ #endif ++ ++ RT_TRACE(_module_rtl871x_mlme_c_, _drv_err_, ("-rtw_indicate_connect: fw_state=0x%08x\n", get_fwstate(pmlmepriv))); ++ ++_func_exit_; ++ ++} ++ ++ ++/* ++*rtw_indicate_disconnect: the caller has to lock pmlmepriv->lock ++*/ ++void rtw_indicate_disconnect( _adapter *padapter ) ++{ ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ ++_func_enter_; ++ ++ RT_TRACE(_module_rtl871x_mlme_c_, _drv_err_, ("+rtw_indicate_disconnect\n")); ++ ++ _clr_fwstate_(pmlmepriv, _FW_LINKED|_FW_UNDER_LINKING); ++ ++ rtw_led_control(padapter, LED_CTL_NO_LINK); ++ ++ #ifdef CONFIG_LAYER2_ROAMING ++ if(pmlmepriv->to_roaming<=0) ++ #endif ++ rtw_os_indicate_disconnect(padapter); ++ ++#ifdef CONFIG_LPS ++ if(padapter->pwrctrlpriv.wowlan_mode==_FALSE){ ++ rtw_lps_ctrl_wk_cmd(padapter, LPS_CTRL_DISCONNECT, 1); ++ } ++#endif ++ ++#ifdef CONFIG_P2P ++ p2p_ps_wk_cmd(padapter, P2P_PS_DISABLE, 1); ++#endif //CONFIG_P2P ++ ++_func_exit_; ++} ++ ++inline void rtw_indicate_scan_done( _adapter *padapter, bool aborted) ++{ ++ rtw_os_indicate_scan_done(padapter, aborted); ++} ++ ++static struct sta_info *rtw_joinbss_update_stainfo(_adapter *padapter, struct wlan_network *pnetwork) ++{ ++ int i; ++ struct sta_info *bmc_sta, *psta=NULL; ++ struct recv_reorder_ctrl *preorder_ctrl; ++ struct sta_priv *pstapriv = &padapter->stapriv; ++#ifdef CONFIG_CONCURRENT_MODE ++ PADAPTER pbuddy_adapter = padapter->pbuddy_adapter; ++ struct mlme_priv *pbuddy_mlmepriv = &(pbuddy_adapter->mlmepriv); ++#endif ++ ++ psta = rtw_get_stainfo(pstapriv, pnetwork->network.MacAddress); ++ if(psta==NULL) { ++ psta = rtw_alloc_stainfo(pstapriv, pnetwork->network.MacAddress); ++ } ++ ++ if(psta) //update ptarget_sta ++ { ++ DBG_871X("%s\n", __FUNCTION__); ++ ++ psta->aid = pnetwork->join_res; ++#ifdef CONFIG_CONCURRENT_MODE ++ if((check_fwstate(pbuddy_mlmepriv, WIFI_STATION_STATE) == _TRUE) ++ && (check_fwstate(pbuddy_mlmepriv, _FW_LINKED) == _TRUE)) ++ { ++ psta->mac_id=2; ++ } ++ else ++#endif ++ { ++ psta->mac_id=0; ++ } ++ ++ //security related ++ if(padapter->securitypriv.dot11AuthAlgrthm== dot11AuthAlgrthm_8021X) ++ { ++ padapter->securitypriv.binstallGrpkey=_FALSE; ++ padapter->securitypriv.busetkipkey=_FALSE; ++ padapter->securitypriv.bgrpkey_handshake=_FALSE; ++ ++ psta->ieee8021x_blocked=_TRUE; ++ psta->dot118021XPrivacy=padapter->securitypriv.dot11PrivacyAlgrthm; ++ ++ _rtw_memset((u8 *)&psta->dot118021x_UncstKey, 0, sizeof (union Keytype)); ++ ++ _rtw_memset((u8 *)&psta->dot11tkiprxmickey, 0, sizeof (union Keytype)); ++ _rtw_memset((u8 *)&psta->dot11tkiptxmickey, 0, sizeof (union Keytype)); ++ ++ _rtw_memset((u8 *)&psta->dot11txpn, 0, sizeof (union pn48)); ++ _rtw_memset((u8 *)&psta->dot11rxpn, 0, sizeof (union pn48)); ++ } ++ ++ ++ //for A-MPDU Rx reordering buffer control for bmc_sta & sta_info ++ //if A-MPDU Rx is enabled, reseting rx_ordering_ctrl wstart_b(indicate_seq) to default value=0xffff ++ //todo: check if AP can send A-MPDU packets ++ for(i=0; i < 16 ; i++) ++ { ++ //preorder_ctrl = &precvpriv->recvreorder_ctrl[i]; ++ preorder_ctrl = &psta->recvreorder_ctrl[i]; ++ preorder_ctrl->enable = _FALSE; ++ preorder_ctrl->indicate_seq = 0xffff; ++ #ifdef DBG_RX_SEQ ++ DBG_871X("DBG_RX_SEQ %s:%d indicate_seq:%u \n", __FUNCTION__, __LINE__, ++ preorder_ctrl->indicate_seq); ++ #endif ++ preorder_ctrl->wend_b= 0xffff; ++ preorder_ctrl->wsize_b = 64;//max_ampdu_sz;//ex. 32(kbytes) -> wsize_b=32 ++ } ++ ++ ++ bmc_sta = rtw_get_bcmc_stainfo(padapter); ++ if(bmc_sta) ++ { ++ for(i=0; i < 16 ; i++) ++ { ++ //preorder_ctrl = &precvpriv->recvreorder_ctrl[i]; ++ preorder_ctrl = &bmc_sta->recvreorder_ctrl[i]; ++ preorder_ctrl->enable = _FALSE; ++ preorder_ctrl->indicate_seq = 0xffff; ++ #ifdef DBG_RX_SEQ ++ DBG_871X("DBG_RX_SEQ %s:%d indicate_seq:%u \n", __FUNCTION__, __LINE__, ++ preorder_ctrl->indicate_seq); ++ #endif ++ preorder_ctrl->wend_b= 0xffff; ++ preorder_ctrl->wsize_b = 64;//max_ampdu_sz;//ex. 32(kbytes) -> wsize_b=32 ++ } ++ } ++ ++ ++ //misc. ++ update_sta_info(padapter, psta); ++ ++ } ++ ++ return psta; ++ ++} ++ ++//pnetwork : returns from rtw_joinbss_event_callback ++//ptarget_wlan: found from scanned_queue ++static void rtw_joinbss_update_network(_adapter *padapter, struct wlan_network *ptarget_wlan, struct wlan_network *pnetwork) ++{ ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ struct wlan_network *cur_network = &(pmlmepriv->cur_network); ++ ++ DBG_871X("%s\n", __FUNCTION__); ++ ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_info_,("\nfw_state:%x, BSSID:"MAC_FMT"\n" ++ ,get_fwstate(pmlmepriv), MAC_ARG(pnetwork->network.MacAddress))); ++ ++ ++ // why not use ptarget_wlan?? ++ _rtw_memcpy(&cur_network->network, &pnetwork->network, pnetwork->network.Length); ++ //_rtw_memcpy(&cur_network->network, &ptarget_wlan->network, ptarget_wlan->network.Length); ++ ++ cur_network->aid = pnetwork->join_res; ++ ++ ++#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS ++ rtw_set_signal_stat_timer(&padapter->recvpriv); ++#endif ++ padapter->recvpriv.signal_strength = ptarget_wlan->network.PhyInfo.SignalStrength; ++ padapter->recvpriv.signal_qual = ptarget_wlan->network.PhyInfo.SignalQuality; ++ //the ptarget_wlan->network.Rssi is raw data, we use ptarget_wlan->network.PhyInfo.SignalStrength instead (has scaled) ++ padapter->recvpriv.rssi = translate_percentage_to_dbm(ptarget_wlan->network.PhyInfo.SignalStrength); ++#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS ++ rtw_set_signal_stat_timer(&padapter->recvpriv); ++#endif ++ ++ //update fw_state //will clr _FW_UNDER_LINKING here indirectly ++ switch(pnetwork->network.InfrastructureMode) ++ { ++ case Ndis802_11Infrastructure: ++ pmlmepriv->fw_state = WIFI_STATION_STATE; ++ break; ++ case Ndis802_11IBSS: ++ pmlmepriv->fw_state = WIFI_ADHOC_STATE; ++ break; ++ default: ++ pmlmepriv->fw_state = WIFI_NULL_STATE; ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("Invalid network_mode\n")); ++ break; ++ } ++ ++ rtw_update_protection(padapter, (cur_network->network.IEs) + sizeof (NDIS_802_11_FIXED_IEs), ++ (cur_network->network.IELength)); ++ ++#ifdef CONFIG_80211N_HT ++ rtw_update_ht_cap(padapter, cur_network->network.IEs, cur_network->network.IELength); ++#endif ++ ++ ++} ++ ++//Notes: the fucntion could be > passive_level (the same context as Rx tasklet) ++//pnetwork : returns from rtw_joinbss_event_callback ++//ptarget_wlan: found from scanned_queue ++//if join_res > 0, for (fw_state==WIFI_STATION_STATE), we check if "ptarget_sta" & "ptarget_wlan" exist. ++//if join_res > 0, for (fw_state==WIFI_ADHOC_STATE), we only check if "ptarget_wlan" exist. ++//if join_res > 0, update "cur_network->network" from "pnetwork->network" if (ptarget_wlan !=NULL). ++// ++//#define REJOIN ++void rtw_joinbss_event_prehandle(_adapter *adapter, u8 *pbuf) ++{ ++ _irqL irqL,irqL2; ++ int res; ++ static u8 retry=0; ++ u8 timer_cancelled; ++ struct sta_info *ptarget_sta= NULL, *pcur_sta = NULL; ++ struct sta_priv *pstapriv = &adapter->stapriv; ++ struct mlme_priv *pmlmepriv = &(adapter->mlmepriv); ++ struct wlan_network *pnetwork = (struct wlan_network *)pbuf; ++ struct wlan_network *cur_network = &(pmlmepriv->cur_network); ++ struct wlan_network *pcur_wlan = NULL, *ptarget_wlan = NULL; ++ unsigned int the_same_macaddr = _FALSE; ++ ++_func_enter_; ++ ++#ifdef CONFIG_RTL8712 ++ //endian_convert ++ pnetwork->join_res = le32_to_cpu(pnetwork->join_res); ++ pnetwork->network_type = le32_to_cpu(pnetwork->network_type); ++ pnetwork->network.Length = le32_to_cpu(pnetwork->network.Length); ++ pnetwork->network.Ssid.SsidLength = le32_to_cpu(pnetwork->network.Ssid.SsidLength); ++ pnetwork->network.Privacy =le32_to_cpu( pnetwork->network.Privacy); ++ pnetwork->network.Rssi = le32_to_cpu(pnetwork->network.Rssi); ++ pnetwork->network.NetworkTypeInUse =le32_to_cpu(pnetwork->network.NetworkTypeInUse) ; ++ pnetwork->network.Configuration.ATIMWindow = le32_to_cpu(pnetwork->network.Configuration.ATIMWindow); ++ pnetwork->network.Configuration.BeaconPeriod = le32_to_cpu(pnetwork->network.Configuration.BeaconPeriod); ++ pnetwork->network.Configuration.DSConfig = le32_to_cpu(pnetwork->network.Configuration.DSConfig); ++ pnetwork->network.Configuration.FHConfig.DwellTime=le32_to_cpu(pnetwork->network.Configuration.FHConfig.DwellTime); ++ pnetwork->network.Configuration.FHConfig.HopPattern=le32_to_cpu(pnetwork->network.Configuration.FHConfig.HopPattern); ++ pnetwork->network.Configuration.FHConfig.HopSet=le32_to_cpu(pnetwork->network.Configuration.FHConfig.HopSet); ++ pnetwork->network.Configuration.FHConfig.Length=le32_to_cpu(pnetwork->network.Configuration.FHConfig.Length); ++ pnetwork->network.Configuration.Length = le32_to_cpu(pnetwork->network.Configuration.Length); ++ pnetwork->network.InfrastructureMode = le32_to_cpu(pnetwork->network.InfrastructureMode); ++ pnetwork->network.IELength = le32_to_cpu(pnetwork->network.IELength ); ++#endif ++ ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_info_,("joinbss event call back received with res=%d\n", pnetwork->join_res)); ++ ++ rtw_get_encrypt_decrypt_from_registrypriv(adapter); ++ ++ ++ if (pmlmepriv->assoc_ssid.SsidLength == 0) ++ { ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("@@@@@ joinbss event call back for Any SSid\n")); ++ } ++ else ++ { ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("@@@@@ rtw_joinbss_event_callback for SSid:%s\n", pmlmepriv->assoc_ssid.Ssid)); ++ } ++ ++ the_same_macaddr = _rtw_memcmp(pnetwork->network.MacAddress, cur_network->network.MacAddress, ETH_ALEN); ++ ++ pnetwork->network.Length = get_WLAN_BSSID_EX_sz(&pnetwork->network); ++ if(pnetwork->network.Length > sizeof(WLAN_BSSID_EX)) ++ { ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("\n\n ***joinbss_evt_callback return a wrong bss ***\n\n")); ++ goto ignore_joinbss_callback; ++ } ++ ++ _enter_critical_bh(&pmlmepriv->lock, &irqL); ++ ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_info_,("\n rtw_joinbss_event_callback !! _enter_critical \n")); ++ ++ if(pnetwork->join_res > 0) ++ { ++ _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); ++ retry = 0; ++ if (check_fwstate(pmlmepriv,_FW_UNDER_LINKING) ) ++ { ++ //s1. find ptarget_wlan ++ if(check_fwstate(pmlmepriv, _FW_LINKED) ) ++ { ++ if(the_same_macaddr == _TRUE) ++ { ++ ptarget_wlan = rtw_find_network(&pmlmepriv->scanned_queue, cur_network->network.MacAddress); ++ } ++ else ++ { ++ pcur_wlan = rtw_find_network(&pmlmepriv->scanned_queue, cur_network->network.MacAddress); ++ if(pcur_wlan) pcur_wlan->fixed = _FALSE; ++ ++ pcur_sta = rtw_get_stainfo(pstapriv, cur_network->network.MacAddress); ++ if(pcur_sta){ ++ _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL2); ++ rtw_free_stainfo(adapter, pcur_sta); ++ _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL2); ++ } ++ ++ ptarget_wlan = rtw_find_network(&pmlmepriv->scanned_queue, pnetwork->network.MacAddress); ++ if(check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE){ ++ if(ptarget_wlan) ptarget_wlan->fixed = _TRUE; ++ } ++ } ++ ++ } ++ else ++ { ++ ptarget_wlan = rtw_find_network(&pmlmepriv->scanned_queue, pnetwork->network.MacAddress); ++ if(check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE){ ++ if(ptarget_wlan) ptarget_wlan->fixed = _TRUE; ++ } ++ } ++ ++ //s2. update cur_network ++ if(ptarget_wlan) ++ { ++ rtw_joinbss_update_network(adapter, ptarget_wlan, pnetwork); ++ } ++ else ++ { ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("Can't find ptarget_wlan when joinbss_event callback\n")); ++ _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); ++ goto ignore_joinbss_callback; ++ } ++ ++ ++ //s3. find ptarget_sta & update ptarget_sta after update cur_network only for station mode ++ if(check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE) ++ { ++ ptarget_sta = rtw_joinbss_update_stainfo(adapter, pnetwork); ++ if(ptarget_sta==NULL) ++ { ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("Can't update stainfo when joinbss_event callback\n")); ++ _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); ++ goto ignore_joinbss_callback; ++ } ++ } ++ ++ //s4. indicate connect ++ if(check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE) ++ { ++ rtw_indicate_connect(adapter); ++ } ++ else ++ { ++ //adhoc mode will rtw_indicate_connect when rtw_stassoc_event_callback ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_info_,("adhoc mode, fw_state:%x", get_fwstate(pmlmepriv))); ++ } ++ ++ ++ //s5. Cancle assoc_timer ++ _cancel_timer(&pmlmepriv->assoc_timer, &timer_cancelled); ++ ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_info_,("Cancle assoc_timer\n")); ++ ++ } ++ else ++ { ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("rtw_joinbss_event_callback err: fw_state:%x", get_fwstate(pmlmepriv))); ++ _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); ++ goto ignore_joinbss_callback; ++ } ++ ++ _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); ++ ++ } ++ else if(pnetwork->join_res == -4) ++ { ++ rtw_reset_securitypriv(adapter); ++ _set_timer(&pmlmepriv->assoc_timer, 1); ++ ++ //rtw_free_assoc_resources(adapter, 1); ++ ++ if((check_fwstate(pmlmepriv, _FW_UNDER_LINKING)) == _TRUE) ++ { ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("fail! clear _FW_UNDER_LINKING ^^^fw_state=%x\n", get_fwstate(pmlmepriv))); ++ _clr_fwstate_(pmlmepriv, _FW_UNDER_LINKING); ++ } ++ ++ } ++ else //if join_res < 0 (join fails), then try again ++ { ++ ++ #ifdef REJOIN ++ res = _FAIL; ++ if(retry < 2) { ++ res = rtw_select_and_join_from_scanned_queue(pmlmepriv); ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("rtw_select_and_join_from_scanned_queue again! res:%d\n",res)); ++ } ++ ++ if(res == _SUCCESS) ++ { ++ //extend time of assoc_timer ++ _set_timer(&pmlmepriv->assoc_timer, MAX_JOIN_TIMEOUT); ++ retry++; ++ } ++ else if(res == 2)//there is no need to wait for join ++ { ++ _clr_fwstate_(pmlmepriv, _FW_UNDER_LINKING); ++ rtw_indicate_connect(adapter); ++ } ++ else ++ { ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("Set Assoc_Timer = 1; can't find match ssid in scanned_q \n")); ++ #endif ++ ++ _set_timer(&pmlmepriv->assoc_timer, 1); ++ //rtw_free_assoc_resources(adapter, 1); ++ _clr_fwstate_(pmlmepriv, _FW_UNDER_LINKING); ++ ++ #ifdef REJOIN ++ retry = 0; ++ } ++ #endif ++ } ++ ++ignore_joinbss_callback: ++ ++ _exit_critical_bh(&pmlmepriv->lock, &irqL); ++ _func_exit_; ++} ++ ++void rtw_joinbss_event_callback(_adapter *adapter, u8 *pbuf) ++{ ++ struct wlan_network *pnetwork = (struct wlan_network *)pbuf; ++ struct xmit_priv *pxmitpriv = &adapter->xmitpriv; ++ ++_func_enter_; ++ ++ mlmeext_joinbss_event_callback(adapter, pnetwork->join_res); ++ ++ //Set Value to 1 to xmit data frame. ++ ATOMIC_SET(&pxmitpriv->HwRdyXmitData, 1); ++ rtw_os_xmit_schedule(adapter); ++ ++_func_exit_; ++} ++ ++void rtw_stassoc_event_callback(_adapter *adapter, u8 *pbuf) ++{ ++ _irqL irqL; ++ struct sta_info *psta; ++ struct mlme_priv *pmlmepriv = &(adapter->mlmepriv); ++ struct stassoc_event *pstassoc = (struct stassoc_event*)pbuf; ++ struct wlan_network *cur_network = &(pmlmepriv->cur_network); ++ struct wlan_network *ptarget_wlan = NULL; ++ ++_func_enter_; ++ ++ // to do: ++ if(rtw_access_ctrl(&adapter->acl_list, pstassoc->macaddr) == _FALSE) ++ return; ++ ++#if defined (CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME) ++ if(check_fwstate(pmlmepriv, WIFI_AP_STATE)) ++ { ++ psta = rtw_get_stainfo(&adapter->stapriv, pstassoc->macaddr); ++ if(psta) ++ { ++#ifdef CONFIG_IOCTL_CFG80211 ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,37)) || defined(CONFIG_CFG80211_FORCE_COMPATIBLE_2_6_37_UNDER) ++ u8 *passoc_req = NULL; ++ u32 assoc_req_len; ++ ++ _enter_critical_bh(&psta->lock, &irqL); ++ if(psta->passoc_req && psta->assoc_req_len>0) ++ { ++ passoc_req = rtw_zmalloc(psta->assoc_req_len); ++ if(passoc_req) ++ { ++ assoc_req_len = psta->assoc_req_len; ++ _rtw_memcpy(passoc_req, psta->passoc_req, assoc_req_len); ++ ++ _rtw_mfree(psta->passoc_req , psta->assoc_req_len); ++ psta->passoc_req = NULL; ++ psta->assoc_req_len = 0; ++ } ++ } ++ _exit_critical_bh(&psta->lock, &irqL); ++ ++ if(passoc_req && assoc_req_len>0) ++ { ++ rtw_cfg80211_indicate_sta_assoc(adapter, passoc_req, assoc_req_len); ++ ++ _rtw_mfree(passoc_req, assoc_req_len); ++ } ++#endif //LINUX_VERSION_CODE < KERNEL_VERSION(2,6,37)) || defined(CONFIG_CFG80211_FORCE_COMPATIBLE_2_6_37_UNDER) ++#endif //CONFIG_IOCTL_CFG80211 ++ ++ //bss_cap_update(adapter, psta); ++ //sta_info_update(adapter, psta); ++ ap_sta_info_defer_update(adapter, psta); ++ } ++ ++ goto exit; ++ } ++#endif ++ ++ psta = rtw_get_stainfo(&adapter->stapriv, pstassoc->macaddr); ++ if( psta != NULL) ++ { ++ //the sta have been in sta_info_queue => do nothing ++ ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("Error: rtw_stassoc_event_callback: sta has been in sta_hash_queue \n")); ++ ++ goto exit; //(between drv has received this event before and fw have not yet to set key to CAM_ENTRY) ++ } ++ ++ psta = rtw_alloc_stainfo(&adapter->stapriv, pstassoc->macaddr); ++ if (psta == NULL) { ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("Can't alloc sta_info when rtw_stassoc_event_callback\n")); ++ goto exit; ++ } ++ ++ //to do : init sta_info variable ++ psta->qos_option = 0; ++ psta->mac_id = le32_to_cpu((uint)pstassoc->cam_id); ++ //psta->aid = (uint)pstassoc->cam_id; ++ ++ if(adapter->securitypriv.dot11AuthAlgrthm==dot11AuthAlgrthm_8021X) ++ psta->dot118021XPrivacy = adapter->securitypriv.dot11PrivacyAlgrthm; ++ ++ psta->ieee8021x_blocked = _FALSE; ++ ++ _enter_critical_bh(&pmlmepriv->lock, &irqL); ++ ++ if ( (check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE)==_TRUE ) || ++ (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE)==_TRUE ) ) ++ { ++ if(adapter->stapriv.asoc_sta_count== 2) ++ { ++ _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); ++ ptarget_wlan = rtw_find_network(&pmlmepriv->scanned_queue, cur_network->network.MacAddress); ++ if(ptarget_wlan) ptarget_wlan->fixed = _TRUE; ++ _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); ++ // a sta + bc/mc_stainfo (not Ibss_stainfo) ++ rtw_indicate_connect(adapter); ++ } ++ } ++ ++ _exit_critical_bh(&pmlmepriv->lock, &irqL); ++ ++ ++ mlmeext_sta_add_event_callback(adapter, psta); ++ ++#ifdef CONFIG_RTL8711 ++ //submit SetStaKey_cmd to tell fw, fw will allocate an CAM entry for this sta ++ rtw_setstakey_cmd(adapter, (unsigned char*)psta, _FALSE); ++#endif ++ ++exit: ++ ++_func_exit_; ++ ++} ++ ++void rtw_stadel_event_callback(_adapter *adapter, u8 *pbuf) ++{ ++ _irqL irqL,irqL2; ++ struct sta_info *psta; ++ struct wlan_network* pwlan = NULL; ++ WLAN_BSSID_EX *pdev_network=NULL; ++ u8* pibss = NULL; ++ struct mlme_priv *pmlmepriv = &(adapter->mlmepriv); ++ struct stadel_event *pstadel = (struct stadel_event*)pbuf; ++ struct sta_priv *pstapriv = &adapter->stapriv; ++ struct wlan_network *tgt_network = &(pmlmepriv->cur_network); ++ ++_func_enter_; ++ ++ if(check_fwstate(pmlmepriv, WIFI_AP_STATE)) ++ { ++#ifdef CONFIG_IOCTL_CFG80211 ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,37)) || defined(CONFIG_CFG80211_FORCE_COMPATIBLE_2_6_37_UNDER) ++ rtw_cfg80211_indicate_sta_disassoc(adapter, pstadel->macaddr, *(u16*)pstadel->rsvd); ++#endif //(LINUX_VERSION_CODE < KERNEL_VERSION(2,6,37)) || defined(CONFIG_CFG80211_FORCE_COMPATIBLE_2_6_37_UNDER) ++#endif //CONFIG_IOCTL_CFG80211 ++ return; ++ } ++ ++ mlmeext_sta_del_event_callback(adapter); ++ ++ _enter_critical_bh(&pmlmepriv->lock, &irqL2); ++ ++ if(check_fwstate(pmlmepriv, WIFI_STATION_STATE) ) ++ { ++ ++ #ifdef CONFIG_LAYER2_ROAMING ++ if(pmlmepriv->to_roaming > 0) ++ pmlmepriv->to_roaming--; // this stadel_event is caused by roaming, decrease to_roaming ++ else if(pmlmepriv->to_roaming ==0) ++ pmlmepriv->to_roaming= adapter->registrypriv.max_roaming_times; ++ ++ if(*((unsigned short *)(pstadel->rsvd)) !=65535 ) //if stadel_event isn't caused by no rx ++ pmlmepriv->to_roaming=0; // don't roam ++ #endif //CONFIG_LAYER2_ROAMING ++ ++ ++ rtw_free_assoc_resources(adapter, 1); ++ rtw_indicate_disconnect(adapter); ++ _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); ++ // remove the network entry in scanned_queue ++ pwlan = rtw_find_network(&pmlmepriv->scanned_queue, tgt_network->network.MacAddress); ++ if (pwlan) { ++ pwlan->fixed = _FALSE; ++ rtw_free_network_nolock(pmlmepriv, pwlan); ++ } ++ _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); ++ #ifdef CONFIG_LAYER2_ROAMING ++ _rtw_roaming(adapter, tgt_network); ++ #endif //CONFIG_LAYER2_ROAMING ++ ++ } ++ ++ if ( check_fwstate(pmlmepriv,WIFI_ADHOC_MASTER_STATE) || ++ check_fwstate(pmlmepriv,WIFI_ADHOC_STATE)) ++ { ++ psta = rtw_get_stainfo(&adapter->stapriv, pstadel->macaddr); ++ ++ _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL); ++ rtw_free_stainfo(adapter, psta); ++ _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL); ++ ++ if(adapter->stapriv.asoc_sta_count== 1) //a sta + bc/mc_stainfo (not Ibss_stainfo) ++ { ++ //rtw_indicate_disconnect(adapter);//removed@20091105 ++ _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); ++ //free old ibss network ++ //pwlan = rtw_find_network(&pmlmepriv->scanned_queue, pstadel->macaddr); ++ pwlan = rtw_find_network(&pmlmepriv->scanned_queue, tgt_network->network.MacAddress); ++ if(pwlan) ++ { ++ pwlan->fixed = _FALSE; ++ rtw_free_network_nolock(pmlmepriv, pwlan); ++ } ++ _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); ++ //re-create ibss ++ pdev_network = &(adapter->registrypriv.dev_network); ++ pibss = adapter->registrypriv.dev_network.MacAddress; ++ ++ _rtw_memcpy(pdev_network, &tgt_network->network, get_WLAN_BSSID_EX_sz(&tgt_network->network)); ++ ++ _rtw_memset(&pdev_network->Ssid, 0, sizeof(NDIS_802_11_SSID)); ++ _rtw_memcpy(&pdev_network->Ssid, &pmlmepriv->assoc_ssid, sizeof(NDIS_802_11_SSID)); ++ ++ rtw_update_registrypriv_dev_network(adapter); ++ ++ rtw_generate_random_ibss(pibss); ++ ++ if(check_fwstate(pmlmepriv,WIFI_ADHOC_STATE)) ++ { ++ set_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE); ++ _clr_fwstate_(pmlmepriv, WIFI_ADHOC_STATE); ++ } ++ ++ if(rtw_createbss_cmd(adapter)!=_SUCCESS) ++ { ++ ++ RT_TRACE(_module_rtl871x_ioctl_set_c_,_drv_err_,("***Error=>stadel_event_callback: rtw_createbss_cmd status FAIL*** \n ")); ++ ++ } ++ ++ ++ } ++ ++ } ++ ++ _exit_critical_bh(&pmlmepriv->lock, &irqL2); ++ ++_func_exit_; ++ ++} ++ ++ ++void rtw_cpwm_event_callback(_adapter *adapter, u8 *pbuf) ++{ ++ struct reportpwrstate_parm *preportpwrstate = (struct reportpwrstate_parm *)pbuf; ++ ++_func_enter_; ++ ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("rtw_cpwm_event_callback !!!\n")); ++#ifdef CONFIG_PWRCTRL ++ preportpwrstate->state |= (u8)(adapter->pwrctrlpriv.cpwm_tog + 0x80); ++ cpwm_int_hdl(adapter, preportpwrstate); ++#endif ++ ++_func_exit_; ++ ++} ++ ++/* ++* _rtw_join_timeout_handler - Timeout/faliure handler for CMD JoinBss ++* @adapter: pointer to _adapter structure ++*/ ++void _rtw_join_timeout_handler (_adapter *adapter) ++{ ++ _irqL irqL; ++ struct mlme_priv *pmlmepriv = &adapter->mlmepriv; ++ int do_join_r; ++ ++#if 0 ++ if (adapter->bDriverStopped == _TRUE){ ++ _rtw_up_sema(&pmlmepriv->assoc_terminate); ++ return; ++ } ++#endif ++ ++_func_enter_; ++ ++ DBG_871X("%s, fw_state=%x\n", __FUNCTION__, get_fwstate(pmlmepriv)); ++ ++ if(adapter->bDriverStopped ||adapter->bSurpriseRemoved) ++ return; ++ ++ ++ _enter_critical_bh(&pmlmepriv->lock, &irqL); ++ ++ #ifdef CONFIG_LAYER2_ROAMING ++ if(pmlmepriv->to_roaming>0) { // join timeout caused by roaming ++ while(1) { ++ pmlmepriv->to_roaming--; ++ if(pmlmepriv->to_roaming!=0) { //try another , ++ DBG_871X("%s try another roaming\n", __FUNCTION__); ++ if( _SUCCESS!=(do_join_r=rtw_do_join(adapter)) ) { ++ DBG_871X("%s roaming do_join return %d\n", __FUNCTION__ ,do_join_r); ++ continue; ++ } ++ break; ++ } else { ++ DBG_871X("%s We've try roaming but fail\n", __FUNCTION__); ++ rtw_indicate_disconnect(adapter); ++ break; ++ } ++ } ++ ++ } else ++ #endif ++ { ++ rtw_indicate_disconnect(adapter); ++ free_scanqueue(pmlmepriv);//??? ++ } ++ ++ _exit_critical_bh(&pmlmepriv->lock, &irqL); ++ ++ ++#ifdef CONFIG_DRVEXT_MODULE_WSC ++ drvext_assoc_fail_indicate(&adapter->drvextpriv); ++#endif ++ ++_func_exit_; ++ ++} ++ ++ ++/* ++* rtw_scan_timeout_handler - Timeout/Faliure handler for CMD SiteSurvey ++* @adapter: pointer to _adapter structure ++*/ ++void rtw_scan_timeout_handler (_adapter *adapter) ++{ ++ _irqL irqL; ++ struct mlme_priv *pmlmepriv = &adapter->mlmepriv; ++ ++ DBG_871X("%s, fw_state=%x\n", __FUNCTION__, get_fwstate(pmlmepriv)); ++ ++ if(adapter->bDriverStopped ||adapter->bSurpriseRemoved) ++ return; ++ ++ _enter_critical_bh(&pmlmepriv->lock, &irqL); ++ ++ _clr_fwstate_(pmlmepriv, _FW_UNDER_SURVEY); ++ ++ _exit_critical_bh(&pmlmepriv->lock, &irqL); ++ ++ rtw_indicate_scan_done(adapter, _TRUE); ++} ++ ++static void rtw_auto_scan_handler(_adapter *padapter) ++{ ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct pwrctrl_priv *pwrctrlpriv = &padapter->pwrctrlpriv; ++ ++ //auto site survey per 60sec ++ if(pmlmepriv->scan_interval >0) ++ { ++ pmlmepriv->scan_interval--; ++ if(pmlmepriv->scan_interval==0) ++ { ++ if( pwrctrlpriv->power_mgnt != PS_MODE_ACTIVE ) ++ return; ++ ++/* ++ if (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY|_FW_UNDER_LINKING) == _TRUE) ++ { ++ DBG_8192C("exit %s when _FW_UNDER_SURVEY|_FW_UNDER_LINKING -> \n", __FUNCTION__); ++ return; ++ } ++ ++ if(pmlmepriv->sitesurveyctrl.traffic_busy == _TRUE) ++ { ++ DBG_8192C("%s exit cause traffic_busy(%x)\n",__FUNCTION__, pmlmepriv->sitesurveyctrl.traffic_busy); ++ return; ++ } ++*/ ++ ++ DBG_871X("%s\n", __FUNCTION__); ++ ++ rtw_set_802_11_bssid_list_scan(padapter); ++ ++ pmlmepriv->scan_interval = SCAN_INTERVAL;// 30*2 sec = 60sec ++ ++ } ++ ++ } ++ ++} ++ ++void rtw_dynamic_check_timer_handlder(_adapter *adapter) ++{ ++#ifdef CONFIG_AP_MODE ++ struct mlme_priv *pmlmepriv = &adapter->mlmepriv; ++#endif //CONFIG_AP_MODE ++ struct registry_priv *pregistrypriv = &adapter->registrypriv; ++ ++ if(adapter->hw_init_completed == _FALSE) ++ return; ++ ++ if ((adapter->bDriverStopped == _TRUE)||(adapter->bSurpriseRemoved== _TRUE)) ++ return; ++ ++ if(adapter->net_closed == _TRUE) ++ return; ++ ++ rtw_dynamic_chk_wk_cmd(adapter); ++ ++ if(pregistrypriv->wifi_spec==1) ++ { ++#ifdef CONFIG_P2P ++ struct wifidirect_info *pwdinfo = &adapter->wdinfo; ++ if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) ++#endif ++ { ++ //auto site survey ++ rtw_auto_scan_handler(adapter); ++ } ++ } ++ ++#ifdef CONFIG_AP_MODE ++ if(check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) ++ { ++ expire_timeout_chk(adapter); ++ } ++#endif ++ ++#ifdef CONFIG_BR_EXT ++ ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 35)) ++ rcu_read_lock(); ++#endif // (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 35)) ++ ++#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35)) ++ if( adapter->pnetdev->br_port ++#else // (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35)) ++ if( rcu_dereference(adapter->pnetdev->rx_handler_data) ++#endif // (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35)) ++ && (check_fwstate(pmlmepriv, WIFI_STATION_STATE|WIFI_ADHOC_STATE) == _TRUE) ) ++ { ++ // expire NAT2.5 entry ++ void nat25_db_expire(_adapter *priv); ++ nat25_db_expire(adapter); ++ ++ if (adapter->pppoe_connection_in_progress > 0) { ++ adapter->pppoe_connection_in_progress--; ++ } ++ ++ // due to rtw_dynamic_check_timer_handlder() is called every 2 seconds ++ if (adapter->pppoe_connection_in_progress > 0) { ++ adapter->pppoe_connection_in_progress--; ++ } ++ } ++ ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 35)) ++ rcu_read_unlock(); ++#endif // (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 35)) ++ ++#endif // CONFIG_BR_EXT ++ ++} ++ ++ ++#ifdef CONFIG_SET_SCAN_DENY_TIMER ++void rtw_set_scan_deny_timer_hdl(_adapter *adapter) ++{ ++ struct mlme_priv *mlmepriv = &adapter->mlmepriv; ++ ++ //allowed set scan ++ ATOMIC_SET(&mlmepriv->set_scan_deny, 0); ++} ++ ++void rtw_set_scan_deny(struct mlme_priv *mlmepriv, u32 ms) ++{ ++ ATOMIC_SET(&mlmepriv->set_scan_deny, 1); ++ _set_timer(&mlmepriv->set_scan_deny_timer, ms); ++} ++#endif ++ ++ ++#if defined(IEEE80211_SCAN_RESULT_EXPIRE) ++#define RTW_SCAN_RESULT_EXPIRE IEEE80211_SCAN_RESULT_EXPIRE/HZ*1000 -1000 //3000 -1000 ++#else ++#define RTW_SCAN_RESULT_EXPIRE 2000 ++#endif ++/* ++* Select a new join candidate from the original @param candidate and @param competitor ++* @return _TRUE: candidate is updated ++* @return _FALSE: candidate is not updated ++*/ ++static int rtw_check_join_candidate(struct mlme_priv *pmlmepriv ++ , struct wlan_network **candidate, struct wlan_network *competitor) ++{ ++ int updated = _FALSE; ++ _adapter *adapter = container_of(pmlmepriv, _adapter, mlmepriv); ++ ++ ++ //check bssid, if needed ++ if(pmlmepriv->assoc_by_bssid==_TRUE) { ++ if(_rtw_memcmp(competitor->network.MacAddress, pmlmepriv->assoc_bssid, ETH_ALEN) ==_FALSE) ++ goto exit; ++ } ++ ++ //check ssid, if needed ++ if(pmlmepriv->assoc_ssid.Ssid && pmlmepriv->assoc_ssid.SsidLength) { ++ if( competitor->network.Ssid.SsidLength != pmlmepriv->assoc_ssid.SsidLength ++ || _rtw_memcmp(competitor->network.Ssid.Ssid, pmlmepriv->assoc_ssid.Ssid, pmlmepriv->assoc_ssid.SsidLength) == _FALSE ++ ) ++ goto exit; ++ } ++ ++ if(rtw_is_desired_network(adapter, competitor) == _FALSE) ++ goto exit; ++ ++#ifdef CONFIG_LAYER2_ROAMING ++ if(pmlmepriv->to_roaming) { ++ if( rtw_get_passing_time_ms((u32)competitor->last_scanned) >= RTW_SCAN_RESULT_EXPIRE ++ || is_same_ess(&competitor->network, &pmlmepriv->cur_network.network) == _FALSE ++ ) ++ goto exit; ++ } ++#endif ++ ++ if(*candidate == NULL ||(*candidate)->network.Rssinetwork.Rssi ) ++ { ++ *candidate = competitor; ++ updated = _TRUE; ++ } ++ ++#if 0 ++ if(pmlmepriv->assoc_by_bssid==_TRUE) { // associate with bssid ++ if( (*candidate == NULL ||(*candidate)->network.Rssinetwork.Rssi ) ++ && _rtw_memcmp(competitor->network.MacAddress, pmlmepriv->assoc_bssid, ETH_ALEN)==_TRUE ++ ) { ++ *candidate = competitor; ++ updated = _TRUE; ++ } ++ } else if (pmlmepriv->assoc_ssid.SsidLength == 0 ) { // associate with ssid, but ssidlength is 0 ++ if( (*candidate == NULL ||(*candidate)->network.Rssinetwork.Rssi ) ) { ++ *candidate = competitor; ++ updated = _TRUE; ++ } ++ } else ++#ifdef CONFIG_LAYER2_ROAMING ++ if(pmlmepriv->to_roaming) { // roaming ++ if( (*candidate == NULL ||(*candidate)->network.Rssinetwork.Rssi ) ++ && is_same_ess(&competitor->network, &pmlmepriv->cur_network.network) ++ //&&(!is_same_network(&competitor->network, &pmlmepriv->cur_network.network)) ++ && rtw_get_passing_time_ms((u32)competitor->last_scanned) < RTW_SCAN_RESULT_EXPIRE ++ && rtw_is_desired_network(adapter, competitor) ++ ) { ++ *candidate = competitor; ++ updated = _TRUE; ++ } ++ ++ } else ++#endif ++ { // associate with ssid ++ if( (*candidate == NULL ||(*candidate)->network.Rssinetwork.Rssi ) ++ && (competitor->network.Ssid.SsidLength==pmlmepriv->assoc_ssid.SsidLength) ++ &&((_rtw_memcmp(competitor->network.Ssid.Ssid, pmlmepriv->assoc_ssid.Ssid, pmlmepriv->assoc_ssid.SsidLength)) == _TRUE) ++ && rtw_is_desired_network(adapter, competitor) ++ ) { ++ *candidate = competitor; ++ updated = _TRUE; ++ } ++ } ++#endif ++ ++ if(updated){ ++ DBG_871X("[by_bssid:%u][assoc_ssid:%s]" ++ #ifdef CONFIG_LAYER2_ROAMING ++ "[to_roaming:%u] " ++ #endif ++ "new candidate: %s("MAC_FMT") rssi:%d\n", ++ pmlmepriv->assoc_by_bssid, ++ pmlmepriv->assoc_ssid.Ssid, ++ #ifdef CONFIG_LAYER2_ROAMING ++ pmlmepriv->to_roaming, ++ #endif ++ (*candidate)->network.Ssid.Ssid, ++ MAC_ARG((*candidate)->network.MacAddress), ++ (int)(*candidate)->network.Rssi ++ ); ++ } ++ ++exit: ++ return updated; ++} ++ ++ ++/* ++Calling context: ++The caller of the sub-routine will be in critical section... ++ ++The caller must hold the following spinlock ++ ++pmlmepriv->lock ++ ++ ++*/ ++#if 1 ++int rtw_select_and_join_from_scanned_queue(struct mlme_priv *pmlmepriv ) ++{ ++ _irqL irqL; ++ int ret; ++ _list *phead; ++ _adapter *adapter; ++ _queue *queue = &(pmlmepriv->scanned_queue); ++ struct wlan_network *pnetwork = NULL; ++ struct wlan_network *candidate = NULL; ++ u8 bSupportAntDiv = _FALSE; ++ ++_func_enter_; ++ ++ _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); ++ phead = get_list_head(queue); ++ adapter = (_adapter *)pmlmepriv->nic_hdl; ++ ++ pmlmepriv->pscanned = get_next( phead ); ++ ++ while (!rtw_end_of_queue_search(phead, pmlmepriv->pscanned)) { ++ ++ pnetwork = LIST_CONTAINOR(pmlmepriv->pscanned, struct wlan_network, list); ++ if(pnetwork==NULL){ ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("%s return _FAIL:(pnetwork==NULL)\n", __FUNCTION__)); ++ ret = _FAIL; ++ goto exit; ++ } ++ ++ pmlmepriv->pscanned = get_next(pmlmepriv->pscanned); ++ ++ #if 0 ++ DBG_871X("MacAddress:"MAC_FMT" ssid:%s\n", MAC_ARG(pnetwork->network.MacAddress), pnetwork->network.Ssid.Ssid); ++ #endif ++ ++ rtw_check_join_candidate(pmlmepriv, &candidate, pnetwork); ++ ++ } ++ ++ if(candidate == NULL) { ++ DBG_871X("%s: return _FAIL(candidate == NULL)\n", __FUNCTION__); ++ ret = _FAIL; ++ goto exit; ++ } else { ++ DBG_871X("%s: candidate: %s("MAC_FMT")\n", __FUNCTION__, ++ candidate->network.Ssid.Ssid, MAC_ARG(candidate->network.MacAddress));; ++ } ++ ++ ++ // check for situation of _FW_LINKED ++ if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) ++ { ++ DBG_871X("%s: _FW_LINKED while ask_for_joinbss!!!\n", __FUNCTION__); ++ ++ #if 0 // for WPA/WPA2 authentication, wpa_supplicant will expect authentication from AP, it is needed to reconnect AP... ++ if(is_same_network(&pmlmepriv->cur_network.network, &candidate->network)) ++ { ++ DBG_871X("%s: _FW_LINKED and is same network, it needn't join again\n", __FUNCTION__); ++ ++ rtw_indicate_connect(adapter);//rtw_indicate_connect again ++ ++ ret = 2; ++ goto exit; ++ } ++ else ++ #endif ++ { ++ rtw_disassoc_cmd(adapter); ++ rtw_indicate_disconnect(adapter); ++ rtw_free_assoc_resources(adapter, 0); ++ } ++ } ++ ++ #ifdef CONFIG_ANTENNA_DIVERSITY ++ adapter->HalFunc.GetHalDefVarHandler(adapter, HAL_DEF_IS_SUPPORT_ANT_DIV, &(bSupportAntDiv)); ++ if(_TRUE == bSupportAntDiv) ++ { ++ u8 CurrentAntenna; ++ adapter->HalFunc.GetHalDefVarHandler(adapter, HAL_DEF_CURRENT_ANTENNA, &(CurrentAntenna)); ++ DBG_8192C("#### Opt_Ant_(%s) , cur_Ant(%s)\n", ++ (2==candidate->network.PhyInfo.Optimum_antenna)?"A":"B", ++ (2==CurrentAntenna)?"A":"B" ++ ); ++ } ++ #endif ++ ++ ret = rtw_joinbss_cmd(adapter, candidate); ++ ++exit: ++ _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); ++_func_exit_; ++ ++ return ret; ++ ++} ++#else ++int rtw_select_and_join_from_scanned_queue(struct mlme_priv *pmlmepriv ) ++{ ++ _irqL irqL; ++ _list *phead; ++ u8 CurrentAntenna; ++ unsigned char *dst_ssid, *src_ssid; ++ _adapter *adapter; ++ _queue *queue = &(pmlmepriv->scanned_queue); ++ struct wlan_network *pnetwork = NULL; ++ struct wlan_network *pnetwork_max_rssi = NULL; ++ #ifdef CONFIG_LAYER2_ROAMING ++ struct wlan_network * roaming_candidate=NULL; ++ u32 cur_time=rtw_get_current_time(); ++ #endif ++ ++_func_enter_; ++ _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); ++ phead = get_list_head(queue); ++ adapter = (_adapter *)pmlmepriv->nic_hdl; ++ ++ pmlmepriv->pscanned = get_next( phead ); ++ ++ while (!rtw_end_of_queue_search(phead, pmlmepriv->pscanned)) { ++ ++ pnetwork = LIST_CONTAINOR(pmlmepriv->pscanned, struct wlan_network, list); ++ if(pnetwork==NULL){ ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("(2)rtw_select_and_join_from_scanned_queue return _FAIL:(pnetwork==NULL)\n")); ++ _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); ++ return _FAIL; ++ } ++ ++ dst_ssid = pnetwork->network.Ssid.Ssid; ++ src_ssid = pmlmepriv->assoc_ssid.Ssid; ++ ++ pmlmepriv->pscanned = get_next(pmlmepriv->pscanned); ++ ++ #if 0 ++ DBG_871X("MacAddress:"MAC_FMT" ssid:%s\n", MAC_ARG(pnetwork->network.MacAddress), pnetwork->network.Ssid.Ssid); ++ #endif ++ ++ if(pmlmepriv->assoc_by_bssid==_TRUE) ++ { ++ if(_rtw_memcmp(pnetwork->network.MacAddress, pmlmepriv->assoc_bssid, ETH_ALEN)==_TRUE) ++ { ++ //remove the condition @ 20081125 ++ //if((pmlmepriv->cur_network.network.InfrastructureMode==Ndis802_11AutoUnknown)|| ++ // pmlmepriv->cur_network.network.InfrastructureMode == pnetwork->network.InfrastructureMode) ++ // goto ask_for_joinbss; ++ ++ if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) ++ { ++ if(is_same_network(&pmlmepriv->cur_network.network, &pnetwork->network)) ++ { ++ //DBG_871X("select_and_join(1): _FW_LINKED and is same network, it needn't join again\n"); ++ ++ rtw_indicate_connect(adapter);//rtw_indicate_connect again ++ _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); ++ return 2; ++ } ++ else ++ { ++ rtw_disassoc_cmd(adapter); ++ rtw_indicate_disconnect(adapter); ++ rtw_free_assoc_resources(adapter, 0); ++ _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); ++ goto ask_for_joinbss; ++ ++ } ++ } ++ else ++ { ++ _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); ++ goto ask_for_joinbss; ++ } ++ ++ } ++ ++ } else if (pmlmepriv->assoc_ssid.SsidLength == 0) { ++ goto ask_for_joinbss;//anyway, join first selected(dequeued) pnetwork if ssid_len=0 ++ ++ #ifdef CONFIG_LAYER2_ROAMING ++ } else if(pmlmepriv->to_roaming>0) { ++ ++ if( (roaming_candidate == NULL ||roaming_candidate->network.Rssinetwork.Rssi ) ++ && is_same_ess(&pnetwork->network, &pmlmepriv->cur_network.network) ++ //&&(!is_same_network(&pnetwork->network, &pmlmepriv->cur_network.network)) ++ && rtw_get_time_interval_ms((u32)pnetwork->last_scanned,cur_time) < 5000 ++ ) { ++ roaming_candidate = pnetwork; ++ //RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_, ++ DBG_871X ++ ("roaming_candidate???: %s("MAC_FMT")\n", ++ roaming_candidate->network.Ssid.Ssid, MAC_ARG(roaming_candidate->network.MacAddress) ) ++ //) ++ ; ++ } ++ continue; ++ #endif ++ ++ } else if ( (pnetwork->network.Ssid.SsidLength==pmlmepriv->assoc_ssid.SsidLength) ++ &&((_rtw_memcmp(dst_ssid, src_ssid, pmlmepriv->assoc_ssid.SsidLength)) == _TRUE) ++ ) ++ { ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("dst_ssid=%s, src_ssid=%s \n", dst_ssid, src_ssid)); ++#ifdef CONFIG_ANTENNA_DIVERSITY ++ adapter->HalFunc.GetHalDefVarHandler(adapter, HAL_DEF_CURRENT_ANTENNA, &(CurrentAntenna)); ++ DBG_8192C("#### dst_ssid=(%s) Opt_Ant_(%s) , cur_Ant(%s)\n", dst_ssid, ++ (2==pnetwork->network.PhyInfo.Optimum_antenna)?"A":"B", ++ (2==CurrentAntenna)?"A":"B"); ++#endif ++ //remove the condition @ 20081125 ++ //if((pmlmepriv->cur_network.network.InfrastructureMode==Ndis802_11AutoUnknown)|| ++ // pmlmepriv->cur_network.network.InfrastructureMode == pnetwork->network.InfrastructureMode) ++ //{ ++ // _rtw_memcpy(pmlmepriv->assoc_bssid, pnetwork->network.MacAddress, ETH_ALEN); ++ // goto ask_for_joinbss; ++ //} ++ ++ if(pmlmepriv->assoc_by_rssi==_TRUE)//if the ssid is the same, select the bss which has the max rssi ++ { ++ if( NULL==pnetwork_max_rssi|| pnetwork->network.Rssi > pnetwork_max_rssi->network.Rssi) ++ pnetwork_max_rssi = pnetwork; ++ } ++ else if(rtw_is_desired_network(adapter, pnetwork) == _TRUE) ++ { ++ if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) ++ { ++#if 0 ++ if(is_same_network(&pmlmepriv->cur_network.network, &pnetwork->network)) ++ { ++ DBG_871X("select_and_join(2): _FW_LINKED and is same network, it needn't join again\n"); ++ ++ rtw_indicate_connect(adapter);//rtw_indicate_connect again ++ ++ return 2; ++ } ++ else ++#endif ++ { ++ rtw_disassoc_cmd(adapter); ++ //rtw_indicate_disconnect(adapter);// ++ rtw_free_assoc_resources(adapter, 0); ++ _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); ++ goto ask_for_joinbss; ++ } ++ } ++ else ++ { ++ _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); ++ goto ask_for_joinbss; ++ } ++ ++ } ++ ++ ++ } ++ ++ } ++ _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); ++ #ifdef CONFIG_LAYER2_ROAMING ++ if(pmlmepriv->to_roaming>0 && roaming_candidate ){ ++ pnetwork=roaming_candidate; ++ DBG_871X("select_and_join_from_scanned_queue: roaming_candidate: %s("MAC_FMT")\n", ++ pnetwork->network.Ssid.Ssid, MAC_ARG(pnetwork->network.MacAddress)); ++ goto ask_for_joinbss; ++ } ++ #endif ++ ++ if((pmlmepriv->assoc_by_rssi==_TRUE) && (pnetwork_max_rssi!=NULL)) ++ { ++ pnetwork = pnetwork_max_rssi; ++ DBG_871X("select_and_join_from_scanned_queue: pnetwork_max_rssi: %s("MAC_FMT")\n", ++ pnetwork->network.Ssid.Ssid, MAC_ARG(pnetwork->network.MacAddress)); ++ goto ask_for_joinbss; ++ } ++ ++ DBG_871X("(1)rtw_select_and_join_from_scanned_queue return _FAIL\n"); ++ ++_func_exit_; ++ ++ return _FAIL; ++ ++ask_for_joinbss: ++ ++_func_exit_; ++ ++ return rtw_joinbss_cmd(adapter, pnetwork); ++ ++} ++#endif ++ ++ ++sint rtw_set_auth(_adapter * adapter,struct security_priv *psecuritypriv) ++{ ++ struct cmd_obj* pcmd; ++ struct setauth_parm *psetauthparm; ++ struct cmd_priv *pcmdpriv=&(adapter->cmdpriv); ++ sint res=_SUCCESS; ++ ++_func_enter_; ++ ++ pcmd = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj)); ++ if(pcmd==NULL){ ++ res= _FAIL; //try again ++ goto exit; ++ } ++ ++ psetauthparm=(struct setauth_parm*)rtw_zmalloc(sizeof(struct setauth_parm)); ++ if(psetauthparm==NULL){ ++ rtw_mfree((unsigned char *)pcmd, sizeof(struct cmd_obj)); ++ res= _FAIL; ++ goto exit; ++ } ++ ++ _rtw_memset(psetauthparm, 0, sizeof(struct setauth_parm)); ++ psetauthparm->mode=(unsigned char)psecuritypriv->dot11AuthAlgrthm; ++ ++ pcmd->cmdcode = _SetAuth_CMD_; ++ pcmd->parmbuf = (unsigned char *)psetauthparm; ++ pcmd->cmdsz = (sizeof(struct setauth_parm)); ++ pcmd->rsp = NULL; ++ pcmd->rspsz = 0; ++ ++ ++ _rtw_init_listhead(&pcmd->list); ++ ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("after enqueue set_auth_cmd, auth_mode=%x\n", psecuritypriv->dot11AuthAlgrthm)); ++ ++ res = rtw_enqueue_cmd(pcmdpriv, pcmd); ++ ++exit: ++ ++_func_exit_; ++ ++ return res; ++ ++} ++ ++ ++sint rtw_set_key(_adapter * adapter,struct security_priv *psecuritypriv,sint keyid, u8 set_tx) ++{ ++ u8 keylen; ++ struct cmd_obj *pcmd; ++ struct setkey_parm *psetkeyparm; ++ struct cmd_priv *pcmdpriv = &(adapter->cmdpriv); ++ struct mlme_priv *pmlmepriv = &(adapter->mlmepriv); ++ sint res=_SUCCESS; ++ ++_func_enter_; ++ ++ pcmd = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj)); ++ if(pcmd==NULL){ ++ res= _FAIL; //try again ++ goto exit; ++ } ++ psetkeyparm=(struct setkey_parm*)rtw_zmalloc(sizeof(struct setkey_parm)); ++ if(psetkeyparm==NULL){ ++ rtw_mfree((unsigned char *)pcmd, sizeof(struct cmd_obj)); ++ res= _FAIL; ++ goto exit; ++ } ++ ++ _rtw_memset(psetkeyparm, 0, sizeof(struct setkey_parm)); ++ ++ if(psecuritypriv->dot11AuthAlgrthm ==dot11AuthAlgrthm_8021X){ ++ psetkeyparm->algorithm=(unsigned char)psecuritypriv->dot118021XGrpPrivacy; ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("\n rtw_set_key: psetkeyparm->algorithm=(unsigned char)psecuritypriv->dot118021XGrpPrivacy=%d \n", psetkeyparm->algorithm)); ++ } ++ else{ ++ psetkeyparm->algorithm=(u8)psecuritypriv->dot11PrivacyAlgrthm; ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("\n rtw_set_key: psetkeyparm->algorithm=(u8)psecuritypriv->dot11PrivacyAlgrthm=%d \n", psetkeyparm->algorithm)); ++ ++ } ++ psetkeyparm->keyid = (u8)keyid;//0~3 ++ psetkeyparm->set_tx = set_tx; ++ pmlmepriv->key_mask |= BIT(psetkeyparm->keyid); ++#ifdef CONFIG_AUTOSUSPEND ++ if( _TRUE == adapter->pwrctrlpriv.bInternalAutoSuspend) ++ { ++ adapter->pwrctrlpriv.wepkeymask = pmlmepriv->key_mask; ++ DBG_8192C("....AutoSuspend pwrctrlpriv.wepkeymask(%x)\n",adapter->pwrctrlpriv.wepkeymask); ++ } ++#endif ++ DBG_8192C("==> rtw_set_key algorithm(%x),keyid(%x),key_mask(%x)\n",psetkeyparm->algorithm,psetkeyparm->keyid,pmlmepriv->key_mask); ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("\n rtw_set_key: psetkeyparm->algorithm=%d psetkeyparm->keyid=(u8)keyid=%d \n",psetkeyparm->algorithm, keyid)); ++ ++ switch(psetkeyparm->algorithm){ ++ ++ case _WEP40_: ++ keylen=5; ++ _rtw_memcpy(&(psetkeyparm->key[0]), &(psecuritypriv->dot11DefKey[keyid].skey[0]), keylen); ++ break; ++ case _WEP104_: ++ keylen=13; ++ _rtw_memcpy(&(psetkeyparm->key[0]), &(psecuritypriv->dot11DefKey[keyid].skey[0]), keylen); ++ break; ++ case _TKIP_: ++ keylen=16; ++ _rtw_memcpy(&psetkeyparm->key, &psecuritypriv->dot118021XGrpKey[keyid], keylen); ++ psetkeyparm->grpkey=1; ++ break; ++ case _AES_: ++ keylen=16; ++ _rtw_memcpy(&psetkeyparm->key, &psecuritypriv->dot118021XGrpKey[keyid], keylen); ++ psetkeyparm->grpkey=1; ++ break; ++ default: ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("\n rtw_set_key:psecuritypriv->dot11PrivacyAlgrthm = %x (must be 1 or 2 or 4 or 5)\n",psecuritypriv->dot11PrivacyAlgrthm)); ++ res= _FAIL; ++ goto exit; ++ } ++ ++ ++ pcmd->cmdcode = _SetKey_CMD_; ++ pcmd->parmbuf = (u8 *)psetkeyparm; ++ pcmd->cmdsz = (sizeof(struct setkey_parm)); ++ pcmd->rsp = NULL; ++ pcmd->rspsz = 0; ++ ++ ++ _rtw_init_listhead(&pcmd->list); ++ ++ //_rtw_init_sema(&(pcmd->cmd_sem), 0); ++ ++ res = rtw_enqueue_cmd(pcmdpriv, pcmd); ++ ++exit: ++_func_exit_; ++ return res; ++ ++} ++ ++ ++//adjust IEs for rtw_joinbss_cmd in WMM ++int rtw_restruct_wmm_ie(_adapter *adapter, u8 *in_ie, u8 *out_ie, uint in_len, uint initial_out_len) ++{ ++ unsigned int ielength=0; ++ unsigned int i, j; ++ ++ i = 12; //after the fixed IE ++ while(i=0 :if there is pre-auth key, and return the entry id ++// ++// ++ ++static int SecIsInPMKIDList(_adapter *Adapter, u8 *bssid) ++{ ++ struct security_priv *psecuritypriv=&Adapter->securitypriv; ++ int i=0; ++ ++ do ++ { ++ if( ( psecuritypriv->PMKIDList[i].bUsed ) && ++ ( _rtw_memcmp( psecuritypriv->PMKIDList[i].Bssid, bssid, ETH_ALEN ) == _TRUE ) ) ++ { ++ break; ++ } ++ else ++ { ++ i++; ++ //continue; ++ } ++ ++ }while(isecuritypriv; ++ ++ if(ie[13]<=20){ ++ // The RSN IE didn't include the PMK ID, append the PMK information ++ ie[ie_len]=1; ++ ie_len++; ++ ie[ie_len]=0; //PMKID count = 0x0100 ++ ie_len++; ++ _rtw_memcpy( &ie[ie_len], &psecuritypriv->PMKIDList[iEntry].PMKID, 16); ++ ++ ie_len+=16; ++ ie[13]+=18;//PMKID length = 2+16 ++ ++ } ++ return (ie_len); ++ ++} ++sint rtw_restruct_sec_ie(_adapter *adapter,u8 *in_ie, u8 *out_ie, uint in_len) ++{ ++ u8 authmode, securitytype, match; ++ u8 sec_ie[255], uncst_oui[4], bkup_ie[255]; ++ u8 wpa_oui[4]={0x0, 0x50, 0xf2, 0x01}; ++ uint ielength, cnt, remove_cnt; ++ int iEntry; ++ ++ struct mlme_priv *pmlmepriv = &adapter->mlmepriv; ++ struct security_priv *psecuritypriv=&adapter->securitypriv; ++ uint ndisauthmode=psecuritypriv->ndisauthtype; ++ uint ndissecuritytype = psecuritypriv->ndisencryptstatus; ++ ++_func_enter_; ++ ++ RT_TRACE(_module_rtl871x_mlme_c_, _drv_notice_, ++ ("+rtw_restruct_sec_ie: ndisauthmode=%d ndissecuritytype=%d\n", ++ ndisauthmode, ndissecuritytype)); ++ ++ //copy fixed ie only ++ _rtw_memcpy(out_ie, in_ie,12); ++ ielength=12; ++ ++ if((ndisauthmode==Ndis802_11AuthModeWPA)||(ndisauthmode==Ndis802_11AuthModeWPAPSK)) ++ authmode=_WPA_IE_ID_; ++ if((ndisauthmode==Ndis802_11AuthModeWPA2)||(ndisauthmode==Ndis802_11AuthModeWPA2PSK)) ++ authmode=_WPA2_IE_ID_; ++ ++ if(psecuritypriv->wps_phase == _TRUE) ++ { ++ //DBG_871X("wps_phase == _TRUE\n"); ++ ++ _rtw_memcpy(out_ie+ielength, psecuritypriv->wps_ie, psecuritypriv->wps_ie_len); ++ ++ ielength += psecuritypriv->wps_ie_len; ++ psecuritypriv->wps_phase = _FALSE; ++ ++ } ++ else if((ndisauthmode==Ndis802_11AuthModeWPA)||(ndisauthmode==Ndis802_11AuthModeWPAPSK)||(ndisauthmode==Ndis802_11AuthModeWPA2)||(ndisauthmode==Ndis802_11AuthModeWPA2PSK)) ++ { ++ //copy RSN or SSN ++ _rtw_memcpy(&out_ie[ielength], &psecuritypriv->supplicant_ie[0], psecuritypriv->supplicant_ie[1]+2); ++ ielength+=psecuritypriv->supplicant_ie[1]+2; ++ ++ rtw_report_sec_ie(adapter, authmode, psecuritypriv->supplicant_ie); ++ ++#ifdef CONFIG_DRVEXT_MODULE ++ drvext_report_sec_ie(&adapter->drvextpriv, authmode, sec_ie); ++#endif ++ ++ ++ ++ } ++ iEntry = SecIsInPMKIDList(adapter, pmlmepriv->assoc_bssid); ++ if(iEntry<0) ++ { ++ return ielength; ++ } ++ else ++ { ++ if(authmode == _WPA2_IE_ID_) ++ { ++ ielength=rtw_append_pmkid(adapter, iEntry, out_ie, ielength); ++ } ++ } ++ ++_func_exit_; ++ ++ return ielength; ++} ++ ++void rtw_init_registrypriv_dev_network( _adapter* adapter) ++{ ++ struct registry_priv* pregistrypriv = &adapter->registrypriv; ++ struct eeprom_priv* peepriv = &adapter->eeprompriv; ++ WLAN_BSSID_EX *pdev_network = &pregistrypriv->dev_network; ++ u8 *myhwaddr = myid(peepriv); ++ ++_func_enter_; ++ ++ _rtw_memcpy(pdev_network->MacAddress, myhwaddr, ETH_ALEN); ++ ++ _rtw_memcpy(&pdev_network->Ssid, &pregistrypriv->ssid, sizeof(NDIS_802_11_SSID)); ++ ++ pdev_network->Configuration.Length=sizeof(NDIS_802_11_CONFIGURATION); ++ pdev_network->Configuration.BeaconPeriod = 100; ++ pdev_network->Configuration.FHConfig.Length = 0; ++ pdev_network->Configuration.FHConfig.HopPattern = 0; ++ pdev_network->Configuration.FHConfig.HopSet = 0; ++ pdev_network->Configuration.FHConfig.DwellTime = 0; ++ ++ ++_func_exit_; ++ ++} ++ ++void rtw_update_registrypriv_dev_network(_adapter* adapter) ++{ ++ int sz=0; ++ struct registry_priv* pregistrypriv = &adapter->registrypriv; ++ WLAN_BSSID_EX *pdev_network = &pregistrypriv->dev_network; ++ struct security_priv* psecuritypriv = &adapter->securitypriv; ++ struct wlan_network *cur_network = &adapter->mlmepriv.cur_network; ++ struct xmit_priv *pxmitpriv = &adapter->xmitpriv; ++ ++_func_enter_; ++ ++#if 0 ++ pxmitpriv->vcs_setting = pregistrypriv->vrtl_carrier_sense; ++ pxmitpriv->vcs = pregistrypriv->vcs_type; ++ pxmitpriv->vcs_type = pregistrypriv->vcs_type; ++ //pxmitpriv->rts_thresh = pregistrypriv->rts_thresh; ++ pxmitpriv->frag_len = pregistrypriv->frag_thresh; ++ ++ adapter->qospriv.qos_option = pregistrypriv->wmm_enable; ++#endif ++ ++ pdev_network->Privacy = (psecuritypriv->dot11PrivacyAlgrthm > 0 ? 1 : 0) ; // adhoc no 802.1x ++ ++ pdev_network->Rssi = 0; ++ ++ switch(pregistrypriv->wireless_mode) ++ { ++ case WIRELESS_11B: ++ pdev_network->NetworkTypeInUse = (Ndis802_11DS); ++ break; ++ case WIRELESS_11G: ++ case WIRELESS_11BG: ++ case WIRELESS_11_24N: ++ case WIRELESS_11G_24N: ++ case WIRELESS_11BG_24N: ++ pdev_network->NetworkTypeInUse = (Ndis802_11OFDM24); ++ break; ++ case WIRELESS_11A: ++ case WIRELESS_11A_5N: ++ pdev_network->NetworkTypeInUse = (Ndis802_11OFDM5); ++ break; ++ case WIRELESS_11ABGN: ++ if(pregistrypriv->channel > 14) ++ pdev_network->NetworkTypeInUse = (Ndis802_11OFDM5); ++ else ++ pdev_network->NetworkTypeInUse = (Ndis802_11OFDM24); ++ break; ++ default : ++ // TODO ++ break; ++ } ++ ++ pdev_network->Configuration.DSConfig = (pregistrypriv->channel); ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_info_,("pregistrypriv->channel=%d, pdev_network->Configuration.DSConfig=0x%x\n", pregistrypriv->channel, pdev_network->Configuration.DSConfig)); ++ ++ if(cur_network->network.InfrastructureMode == Ndis802_11IBSS) ++ pdev_network->Configuration.ATIMWindow = (0); ++ ++ pdev_network->InfrastructureMode = (cur_network->network.InfrastructureMode); ++ ++ // 1. Supported rates ++ // 2. IE ++ ++ //rtw_set_supported_rate(pdev_network->SupportedRates, pregistrypriv->wireless_mode) ; // will be called in rtw_generate_ie ++ sz = rtw_generate_ie(pregistrypriv); ++ ++ pdev_network->IELength = sz; ++ ++ pdev_network->Length = get_WLAN_BSSID_EX_sz((WLAN_BSSID_EX *)pdev_network); ++ ++ //notes: translate IELength & Length after assign the Length to cmdsz in createbss_cmd(); ++ //pdev_network->IELength = cpu_to_le32(sz); ++ ++_func_exit_; ++ ++} ++ ++void rtw_get_encrypt_decrypt_from_registrypriv(_adapter* adapter) ++{ ++ u16 wpaconfig=0; ++ struct registry_priv* pregistrypriv = &adapter->registrypriv; ++ struct security_priv* psecuritypriv= &adapter->securitypriv; ++_func_enter_; ++ ++ ++_func_exit_; ++ ++} ++ ++//the fucntion is at passive_level ++void rtw_joinbss_reset(_adapter *padapter) ++{ ++ u8 threshold; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ ++#ifdef CONFIG_80211N_HT ++ struct ht_priv *phtpriv = &pmlmepriv->htpriv; ++#endif ++ ++ //todo: if you want to do something io/reg/hw setting before join_bss, please add code here ++ ++ ++ ++ ++#ifdef CONFIG_80211N_HT ++ ++ pmlmepriv->num_FortyMHzIntolerant = 0; ++ ++ pmlmepriv->num_sta_no_ht = 0; ++ ++ phtpriv->ampdu_enable = _FALSE;//reset to disabled ++ ++#ifdef CONFIG_USB_HCI ++ // TH=1 => means that invalidate usb rx aggregation ++ // TH=0 => means that validate usb rx aggregation, use init value. ++ if(phtpriv->ht_option) ++ { ++ if(padapter->registrypriv.wifi_spec==1) ++ threshold = 1; ++ else ++ threshold = 0; ++ padapter->HalFunc.SetHwRegHandler(padapter, HW_VAR_RXDMA_AGG_PG_TH, (u8 *)(&threshold)); ++ } ++ else ++ { ++ threshold = 1; ++ padapter->HalFunc.SetHwRegHandler(padapter, HW_VAR_RXDMA_AGG_PG_TH, (u8 *)(&threshold)); ++ } ++#endif ++ ++#endif ++ ++} ++ ++ ++#ifdef CONFIG_80211N_HT ++ ++//the fucntion is >= passive_level ++unsigned int rtw_restructure_ht_ie(_adapter *padapter, u8 *in_ie, u8 *out_ie, uint in_len, uint *pout_len) ++{ ++ u32 ielen, out_len; ++ unsigned char *p, *pframe; ++ struct rtw_ieee80211_ht_cap ht_capie; ++ unsigned char WMM_IE[] = {0x00, 0x50, 0xf2, 0x02, 0x00, 0x01, 0x00}; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct qos_priv *pqospriv= &pmlmepriv->qospriv; ++ struct ht_priv *phtpriv = &pmlmepriv->htpriv; ++ ++ ++ phtpriv->ht_option = _FALSE; ++ ++ p = rtw_get_ie(in_ie+12, _HT_CAPABILITY_IE_, &ielen, in_len-12); ++ ++ if(p && ielen>0) ++ { ++ if(pqospriv->qos_option == 0) ++ { ++ out_len = *pout_len; ++ pframe = rtw_set_ie(out_ie+out_len, _VENDOR_SPECIFIC_IE_, ++ _WMM_IE_Length_, WMM_IE, pout_len); ++ ++ pqospriv->qos_option = 1; ++ } ++ ++ out_len = *pout_len; ++ ++ _rtw_memset(&ht_capie, 0, sizeof(struct rtw_ieee80211_ht_cap)); ++ ++ ht_capie.cap_info = IEEE80211_HT_CAP_SUP_WIDTH |IEEE80211_HT_CAP_SGI_20 | ++ IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_TX_STBC | ++ IEEE80211_HT_CAP_DSSSCCK40; ++ ++ ++ { ++ u32 rx_packet_offset, max_recvbuf_sz; ++ padapter->HalFunc.GetHalDefVarHandler(padapter, HAL_DEF_RX_PACKET_OFFSET, &rx_packet_offset); ++ padapter->HalFunc.GetHalDefVarHandler(padapter, HAL_DEF_MAX_RECVBUF_SZ, &max_recvbuf_sz); ++ if(max_recvbuf_sz-rx_packet_offset>(8191-256)) { ++ DBG_871X("%s IEEE80211_HT_CAP_MAX_AMSDU is set\n", __FUNCTION__); ++ ht_capie.cap_info = ht_capie.cap_info |IEEE80211_HT_CAP_MAX_AMSDU; ++ } ++ } ++ ++ ht_capie.ampdu_params_info = (IEEE80211_HT_CAP_AMPDU_FACTOR&0x03); ++ ++ if(padapter->securitypriv.dot11PrivacyAlgrthm == _AES_ ) ++ ht_capie.ampdu_params_info |= (IEEE80211_HT_CAP_AMPDU_DENSITY&(0x07<<2)); ++ else ++ ht_capie.ampdu_params_info |= (IEEE80211_HT_CAP_AMPDU_DENSITY&0x00); ++ ++ ++ pframe = rtw_set_ie(out_ie+out_len, _HT_CAPABILITY_IE_, ++ sizeof(struct rtw_ieee80211_ht_cap), (unsigned char*)&ht_capie, pout_len); ++ ++ ++ //_rtw_memcpy(out_ie+out_len, p, ielen+2);//gtest ++ //*pout_len = *pout_len + (ielen+2); ++ ++ ++ phtpriv->ht_option = _TRUE; ++ ++ p = rtw_get_ie(in_ie+12, _HT_ADD_INFO_IE_, &ielen, in_len-12); ++ if(p && (ielen==sizeof(struct ieee80211_ht_addt_info))) ++ { ++ out_len = *pout_len; ++ pframe = rtw_set_ie(out_ie+out_len, _HT_ADD_INFO_IE_, ielen, p+2 , pout_len); ++ } ++ ++ } ++ ++ return (phtpriv->ht_option); ++ ++} ++ ++//the fucntion is > passive_level (in critical_section) ++void rtw_update_ht_cap(_adapter *padapter, u8 *pie, uint ie_len) ++{ ++ u8 *p, max_ampdu_sz; ++ int len; ++ //struct sta_info *bmc_sta, *psta; ++ struct rtw_ieee80211_ht_cap *pht_capie; ++ struct ieee80211_ht_addt_info *pht_addtinfo; ++ //struct recv_reorder_ctrl *preorder_ctrl; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct ht_priv *phtpriv = &pmlmepriv->htpriv; ++ //struct recv_priv *precvpriv = &padapter->recvpriv; ++ struct registry_priv *pregistrypriv = &padapter->registrypriv; ++ //struct wlan_network *pcur_network = &(pmlmepriv->cur_network);; ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ ++ ++ if(!phtpriv->ht_option) ++ return; ++ ++ if ((!pmlmeinfo->HT_info_enable) || (!pmlmeinfo->HT_caps_enable)) ++ return; ++ ++ DBG_871X("+rtw_update_ht_cap()\n"); ++ ++ //maybe needs check if ap supports rx ampdu. ++ if((phtpriv->ampdu_enable==_FALSE) &&(pregistrypriv->ampdu_enable==1)) ++ { ++ if(pregistrypriv->wifi_spec==1) ++ { ++ phtpriv->ampdu_enable = _FALSE; ++ } ++ else ++ { ++ phtpriv->ampdu_enable = _TRUE; ++ } ++ } ++ else if(pregistrypriv->ampdu_enable==2) ++ { ++ phtpriv->ampdu_enable = _TRUE; ++ } ++ ++ ++ //check Max Rx A-MPDU Size ++ len = 0; ++ p = rtw_get_ie(pie+sizeof (NDIS_802_11_FIXED_IEs), _HT_CAPABILITY_IE_, &len, ie_len-sizeof (NDIS_802_11_FIXED_IEs)); ++ if(p && len>0) ++ { ++ pht_capie = (struct rtw_ieee80211_ht_cap *)(p+2); ++ max_ampdu_sz = (pht_capie->ampdu_params_info & IEEE80211_HT_CAP_AMPDU_FACTOR); ++ max_ampdu_sz = 1 << (max_ampdu_sz+3); // max_ampdu_sz (kbytes); ++ ++ //DBG_8192C("rtw_update_ht_cap(): max_ampdu_sz=%d\n", max_ampdu_sz); ++ phtpriv->rx_ampdu_maxlen = max_ampdu_sz; ++ ++ } ++ ++ ++ len=0; ++ p = rtw_get_ie(pie+sizeof (NDIS_802_11_FIXED_IEs), _HT_ADD_INFO_IE_, &len, ie_len-sizeof (NDIS_802_11_FIXED_IEs)); ++ if(p && len>0) ++ { ++ pht_addtinfo = (struct ieee80211_ht_addt_info *)(p+2); ++ //todo: ++ } ++ ++ ++ //update cur_bwmode & cur_ch_offset ++ if ((pregistrypriv->cbw40_enable) && ++ (pmlmeinfo->HT_caps.HT_cap_element.HT_caps_info & BIT(1)) && ++ (pmlmeinfo->HT_info.infos[0] & BIT(2))) ++ { ++ //switch to the 40M Hz mode accoring to the AP ++ pmlmeext->cur_bwmode = HT_CHANNEL_WIDTH_40; ++ switch ((pmlmeinfo->HT_info.infos[0] & 0x3)) ++ { ++ case HT_EXTCHNL_OFFSET_UPPER: ++ pmlmeext->cur_ch_offset = HAL_PRIME_CHNL_OFFSET_LOWER; ++ break; ++ ++ case HT_EXTCHNL_OFFSET_LOWER: ++ pmlmeext->cur_ch_offset = HAL_PRIME_CHNL_OFFSET_UPPER; ++ break; ++ ++ default: ++ pmlmeext->cur_ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; ++ break; ++ } ++ } ++ ++ // ++ // Config SM Power Save setting ++ // ++ pmlmeinfo->SM_PS = (pmlmeinfo->HT_caps.HT_cap_element.HT_caps_info & 0x0C) >> 2; ++ if(pmlmeinfo->SM_PS == WLAN_HT_CAP_SM_PS_STATIC) ++ { ++ /*u8 i; ++ //update the MCS rates ++ for (i = 0; i < 16; i++) ++ { ++ pmlmeinfo->HT_caps.HT_cap_element.MCS_rate[i] &= MCS_rate_1R[i]; ++ }*/ ++ DBG_871X("%s(): WLAN_HT_CAP_SM_PS_STATIC\n",__FUNCTION__); ++ } ++ ++ // ++ // Config current HT Protection mode. ++ // ++ pmlmeinfo->HT_protection = pmlmeinfo->HT_info.infos[1] & 0x3; ++ ++ ++ ++#if 0 //move to rtw_update_sta_info_client() ++ //for A-MPDU Rx reordering buffer control for bmc_sta & sta_info ++ //if A-MPDU Rx is enabled, reseting rx_ordering_ctrl wstart_b(indicate_seq) to default value=0xffff ++ //todo: check if AP can send A-MPDU packets ++ bmc_sta = rtw_get_bcmc_stainfo(padapter); ++ if(bmc_sta) ++ { ++ for(i=0; i < 16 ; i++) ++ { ++ //preorder_ctrl = &precvpriv->recvreorder_ctrl[i]; ++ preorder_ctrl = &bmc_sta->recvreorder_ctrl[i]; ++ preorder_ctrl->enable = _FALSE; ++ preorder_ctrl->indicate_seq = 0xffff; ++ #ifdef DBG_RX_SEQ ++ DBG_871X("DBG_RX_SEQ %s:%d indicate_seq:%u \n", __FUNCTION__, __LINE__, ++ preorder_ctrl->indicate_seq); ++ #endif ++ preorder_ctrl->wend_b= 0xffff; ++ preorder_ctrl->wsize_b = 64;//max_ampdu_sz;//ex. 32(kbytes) -> wsize_b=32 ++ } ++ } ++ ++ psta = rtw_get_stainfo(&padapter->stapriv, pcur_network->network.MacAddress); ++ if(psta) ++ { ++ for(i=0; i < 16 ; i++) ++ { ++ //preorder_ctrl = &precvpriv->recvreorder_ctrl[i]; ++ preorder_ctrl = &psta->recvreorder_ctrl[i]; ++ preorder_ctrl->enable = _FALSE; ++ preorder_ctrl->indicate_seq = 0xffff; ++ #ifdef DBG_RX_SEQ ++ DBG_871X("DBG_RX_SEQ %s:%d indicate_seq:%u \n", __FUNCTION__, __LINE__, ++ preorder_ctrl->indicate_seq); ++ #endif ++ preorder_ctrl->wend_b= 0xffff; ++ preorder_ctrl->wsize_b = 64;//max_ampdu_sz;//ex. 32(kbytes) -> wsize_b=32 ++ } ++ } ++#endif ++ ++} ++ ++void rtw_issue_addbareq_cmd(_adapter *padapter, struct xmit_frame *pxmitframe) ++{ ++ u8 issued; ++ int priority; ++ struct sta_info *psta=NULL; ++ struct ht_priv *phtpriv; ++ struct pkt_attrib *pattrib =&pxmitframe->attrib; ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ s32 bmcst = IS_MCAST(pattrib->ra); ++ ++ if(bmcst || (padapter->mlmepriv.LinkDetectInfo.bTxBusyTraffic == _FALSE)) ++ return; ++ ++ priority = pattrib->priority; ++ ++ if (pattrib->psta) ++ psta = pattrib->psta; ++ else ++ psta = rtw_get_stainfo(&padapter->stapriv, pattrib->ra); ++ ++ if(psta==NULL) ++ return; ++ ++ phtpriv = &psta->htpriv; ++ ++ if((phtpriv->ht_option==_TRUE) && (phtpriv->ampdu_enable==_TRUE)) ++ { ++ issued = (phtpriv->agg_enable_bitmap>>priority)&0x1; ++ issued |= (phtpriv->candidate_tid_bitmap>>priority)&0x1; ++ ++ if(0==issued) ++ { ++ DBG_871X("rtw_issue_addbareq_cmd, p=%d\n", priority); ++ psta->htpriv.candidate_tid_bitmap |= BIT((u8)priority); ++ rtw_addbareq_cmd(padapter,(u8) priority, pattrib->ra); ++ } ++ } ++ ++} ++ ++#endif ++ ++#ifdef CONFIG_LAYER2_ROAMING ++void rtw_roaming(_adapter *padapter, struct wlan_network *tgt_network) ++{ ++ _irqL irqL; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ ++ _enter_critical_bh(&pmlmepriv->lock, &irqL); ++ _rtw_roaming(padapter, tgt_network); ++ _exit_critical_bh(&pmlmepriv->lock, &irqL); ++} ++void _rtw_roaming(_adapter *padapter, struct wlan_network *tgt_network) ++{ ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ int do_join_r; ++ ++ struct wlan_network *pnetwork; ++ ++ if(tgt_network != NULL) ++ pnetwork = tgt_network; ++ else ++ pnetwork = &pmlmepriv->cur_network; ++ ++ if(0 < pmlmepriv->to_roaming) { ++ DBG_871X("roaming from %s("MAC_FMT"), length:%d\n", ++ pnetwork->network.Ssid.Ssid, MAC_ARG(pnetwork->network.MacAddress), ++ pnetwork->network.Ssid.SsidLength); ++ _rtw_memcpy(&pmlmepriv->assoc_ssid, &pnetwork->network.Ssid, sizeof(NDIS_802_11_SSID)); ++ ++ pmlmepriv->assoc_by_bssid = _FALSE; ++ ++ while(1) { ++ if( _SUCCESS==(do_join_r=rtw_do_join(padapter)) ) { ++ break; ++ } else { ++ DBG_871X("roaming do_join return %d\n", do_join_r); ++ pmlmepriv->to_roaming--; ++ ++ if(0< pmlmepriv->to_roaming) { ++ continue; ++ } else { ++ DBG_871X("%s(%d) -to roaming fail, indicate_disconnect\n", __FUNCTION__,__LINE__); ++ rtw_indicate_disconnect(padapter); ++ break; ++ } ++ } ++ } ++ } ++ ++} ++#endif ++ +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/core/rtw_mlme_ext.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/core/rtw_mlme_ext.c 2013-07-26 19:36:05.000000000 +0000 +@@ -0,0 +1,12271 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#define _RTW_MLME_EXT_C_ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++struct mlme_handler mlme_sta_tbl[]={ ++ {WIFI_ASSOCREQ, "OnAssocReq", &OnAssocReq}, ++ {WIFI_ASSOCRSP, "OnAssocRsp", &OnAssocRsp}, ++ {WIFI_REASSOCREQ, "OnReAssocReq", &OnAssocReq}, ++ {WIFI_REASSOCRSP, "OnReAssocRsp", &OnAssocRsp}, ++ {WIFI_PROBEREQ, "OnProbeReq", &OnProbeReq}, ++ {WIFI_PROBERSP, "OnProbeRsp", &OnProbeRsp}, ++ ++ /*---------------------------------------------------------- ++ below 2 are reserved ++ -----------------------------------------------------------*/ ++ {0, "DoReserved", &DoReserved}, ++ {0, "DoReserved", &DoReserved}, ++ {WIFI_BEACON, "OnBeacon", &OnBeacon}, ++ {WIFI_ATIM, "OnATIM", &OnAtim}, ++ {WIFI_DISASSOC, "OnDisassoc", &OnDisassoc}, ++ {WIFI_AUTH, "OnAuth", &OnAuthClient}, ++ {WIFI_DEAUTH, "OnDeAuth", &OnDeAuth}, ++ {WIFI_ACTION, "OnAction", &OnAction}, ++}; ++ ++#ifdef _CONFIG_NATIVEAP_MLME_ ++struct mlme_handler mlme_ap_tbl[]={ ++ {WIFI_ASSOCREQ, "OnAssocReq", &OnAssocReq}, ++ {WIFI_ASSOCRSP, "OnAssocRsp", &OnAssocRsp}, ++ {WIFI_REASSOCREQ, "OnReAssocReq", &OnAssocReq}, ++ {WIFI_REASSOCRSP, "OnReAssocRsp", &OnAssocRsp}, ++ {WIFI_PROBEREQ, "OnProbeReq", &OnProbeReq}, ++ {WIFI_PROBERSP, "OnProbeRsp", &OnProbeRsp}, ++ ++ /*---------------------------------------------------------- ++ below 2 are reserved ++ -----------------------------------------------------------*/ ++ {0, "DoReserved", &DoReserved}, ++ {0, "DoReserved", &DoReserved}, ++ {WIFI_BEACON, "OnBeacon", &OnBeacon}, ++ {WIFI_ATIM, "OnATIM", &OnAtim}, ++ {WIFI_DISASSOC, "OnDisassoc", &OnDisassoc}, ++ {WIFI_AUTH, "OnAuth", &OnAuth}, ++ {WIFI_DEAUTH, "OnDeAuth", &OnDeAuth}, ++ {WIFI_ACTION, "OnAction", &OnAction}, ++}; ++#endif ++ ++struct action_handler OnAction_tbl[]={ ++ {RTW_WLAN_CATEGORY_SPECTRUM_MGMT, "ACTION_SPECTRUM_MGMT", &DoReserved}, ++ {RTW_WLAN_CATEGORY_QOS, "ACTION_QOS", &OnAction_qos}, ++ {RTW_WLAN_CATEGORY_DLS, "ACTION_DLS", &OnAction_dls}, ++ {RTW_WLAN_CATEGORY_BACK, "ACTION_BACK", &OnAction_back}, ++ {RTW_WLAN_CATEGORY_PUBLIC, "ACTION_PUBLIC", &OnAction_public}, ++ {RTW_WLAN_CATEGORY_RADIO_MEASUREMENT, "ACTION_RADIO_MEASUREMENT", &DoReserved}, ++ {RTW_WLAN_CATEGORY_FT, "ACTION_FT", &DoReserved}, ++ {RTW_WLAN_CATEGORY_HT, "ACTION_HT", &OnAction_ht}, ++ {RTW_WLAN_CATEGORY_SA_QUERY, "ACTION_SA_QUERY", &DoReserved}, ++ {RTW_WLAN_CATEGORY_WMM, "ACTION_WMM", &OnAction_wmm}, ++ {RTW_WLAN_CATEGORY_P2P, "ACTION_P2P", &OnAction_p2p}, ++}; ++ ++ ++/************************************************** ++OUI definitions for the vendor specific IE ++***************************************************/ ++unsigned char WPA_OUI[] = {0x00, 0x50, 0xf2, 0x01}; ++unsigned char WMM_OUI[] = {0x00, 0x50, 0xf2, 0x02}; ++unsigned char WPS_OUI[] = {0x00, 0x50, 0xf2, 0x04}; ++unsigned char P2P_OUI[] = {0x50,0x6F,0x9A,0x09}; ++unsigned char WFD_OUI[] = {0x50,0x6F,0x9A,0x0A}; ++ ++unsigned char WMM_INFO_OUI[] = {0x00, 0x50, 0xf2, 0x02, 0x00, 0x01}; ++unsigned char WMM_PARA_OUI[] = {0x00, 0x50, 0xf2, 0x02, 0x01, 0x01}; ++ ++unsigned char WPA_TKIP_CIPHER[4] = {0x00, 0x50, 0xf2, 0x02}; ++unsigned char RSN_TKIP_CIPHER[4] = {0x00, 0x0f, 0xac, 0x02}; ++ ++extern unsigned char REALTEK_96B_IE[]; ++ ++/******************************************************** ++MCS rate definitions ++*********************************************************/ ++#ifdef CONFIG_DISABLE_MCS13TO15 ++unsigned char MCS_rate_2R[16] = {0xff, 0x1f, 0x0, 0x0, 0x01, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}; ++#else //CONFIG_DISABLE_MCS13TO15 ++unsigned char MCS_rate_2R[16] = {0xff, 0xff, 0x0, 0x0, 0x01, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}; ++#endif //CONFIG_DISABLE_MCS13TO15 ++unsigned char MCS_rate_1R[16] = {0xff, 0x00, 0x0, 0x0, 0x01, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0}; ++ ++/******************************************************** ++ChannelPlan definitions ++*********************************************************/ ++/*static RT_CHANNEL_PLAN DefaultChannelPlan[RT_CHANNEL_DOMAIN_MAX] = { ++ {{1,2,3,4,5,6,7,8,9,10,11,36,40,44,48,52,56,60,64,100,104,108,112,116,132,136,140,149,153,157,161,165},32}, // 0x00, RT_CHANNEL_DOMAIN_FCC ++ {{1,2,3,4,5,6,7,8,9,10,11,36,40,44,48,52,56,60,64,100,104,108,112,116,136,140,149,153,157,161,165},31}, // 0x01, RT_CHANNEL_DOMAIN_IC ++ {{1,2,3,4,5,6,7,8,9,10,11,12,13,36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,128,132,136,140},32}, // 0x02, RT_CHANNEL_DOMAIN_ETSI ++ {{1,2,3,4,5,6,7,8,9,10,11,12,13},13}, // 0x03, RT_CHANNEL_DOMAIN_SPAIN ++ {{1,2,3,4,5,6,7,8,9,10,11,12,13},13}, // 0x04, RT_CHANNEL_DOMAIN_FRANCE ++ {{1,2,3,4,5,6,7,8,9,10,11,12,13},13}, // 0x05, RT_CHANNEL_DOMAIN_MKK ++ {{1,2,3,4,5,6,7,8,9,10,11,12,13},13}, // 0x06, RT_CHANNEL_DOMAIN_MKK1 ++ {{1,2,3,4,5,6,7,8,9,10,11,12,13,36,40,44,48,52,56,60,64},21}, // 0x07, RT_CHANNEL_DOMAIN_ISRAEL ++ {{1,2,3,4,5,6,7,8,9,10,11,12,13,14,36,40,44,48,52,56,60,64},22}, // 0x08, RT_CHANNEL_DOMAIN_TELEC ++ {{1,2,3,4,5,6,7,8,9,10,11,12,13,14},14}, // 0x09, RT_CHANNEL_DOMAIN_GLOBAL_DOAMIN ++ {{1,2,3,4,5,6,7,8,9,10,11,12,13},13}, // 0x0A, RT_CHANNEL_DOMAIN_WORLD_WIDE_13 ++ {{1,2,3,4,5,6,7,8,9,10,11,56,60,64,100,104,108,112,116,136,140,149,153,157,161,165},26}, // 0x0B, RT_CHANNEL_DOMAIN_TAIWAN ++ {{1,2,3,4,5,6,7,8,9,10,11,12,13,149,153,157,161,165},18}, // 0x0C, RT_CHANNEL_DOMAIN_CHINA ++ {{1,2,3,4,5,6,7,8,9,10,11,36,40,44,48,52,56,60,64,149,153,157,161,165},24}, // 0x0D, RT_CHANNEL_DOMAIN_SINGAPORE_INDIA_MEXICO ++ {{1,2,3,4,5,6,7,8,9,10,11,36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,149,153,157,161,165},31}, // 0x0E, RT_CHANNEL_DOMAIN_KOREA ++ {{1,2,3,4,5,6,7,8,9,10,11,36,40,44,48,52,56,60,64},19}, // 0x0F, RT_CHANNEL_DOMAIN_TURKEY ++ {{1,2,3,4,5,6,7,8,9,10,11,12,13,36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,128,132,136,140},32}, // 0x10, RT_CHANNEL_DOMAIN_JAPAN ++ {{1,2,3,4,5,6,7,8,9,10,11,36,40,44,48,149,153,157,161,165},20}, // 0x11, RT_CHANNEL_DOMAIN_FCC_NO_DFS ++ {{1,2,3,4,5,6,7,8,9,10,11,12,13,36,40,44,48},17}, // 0x12, RT_CHANNEL_DOMAIN_JAPAN_NO_DFS ++ {{1,2,3,4,5,6,7,8,9,10,11,12,13,36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,128,132,136,140,149,153,157,161,165},37}, // 0x13, RT_CHANNEL_DOMAIN_WORLD_WIDE_5G ++ {{1,2,3,4,5,6,7,8,9,10,11,56,60,64,149,153,157,161,165},19}, // 0x14, RT_CHANNEL_DOMAIN_TAIWAN_NO_DFS ++};*/ ++ ++static RT_CHANNEL_PLAN_2G RTW_ChannelPlan2G[RT_CHANNEL_DOMAIN_2G_MAX] = { ++ {{1,2,3,4,5,6,7,8,9,10,11,12,13},13}, // 0x00, RT_CHANNEL_DOMAIN_2G_WORLD , Passive scan CH 12, 13 ++ {{1,2,3,4,5,6,7,8,9,10,11,13,13},13}, // 0x01, RT_CHANNEL_DOMAIN_2G_ETSI1 ++ {{1,2,3,4,5,6,7,8,9,10,11},11}, // 0x02, RT_CHANNEL_DOMAIN_2G_FCC1 ++ {{1,2,3,4,5,6,7,8,9,10,11,12,13,14},14}, // 0x03, RT_CHANNEL_DOMAIN_2G_MIKK1 ++ {{10,11,12,13},4}, // 0x04, RT_CHANNEL_DOMAIN_2G_ETSI2 ++}; ++ ++static RT_CHANNEL_PLAN_5G RTW_ChannelPlan5G[RT_CHANNEL_DOMAIN_5G_MAX] = { ++ {{},0}, // 0x00, RT_CHANNEL_DOMAIN_5G_NULL ++ {{36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,128,132,136,140},19}, // 0x01, RT_CHANNEL_DOMAIN_5G_ETSI1 ++ {{36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,128,132,136,140,149,153,157,161,165},24}, // 0x02, RT_CHANNEL_DOMAIN_5G_ETSI2 ++ {{36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,128,132,149,153,157,161,165},22}, // 0x03, RT_CHANNEL_DOMAIN_5G_ETSI3 ++ {{36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,128,132,136,140,149,153,157,161,165},24}, // 0x04, RT_CHANNEL_DOMAIN_5G_FCC1 ++ {{36,40,44,48,149,153,157,161,165},9}, // 0x05, RT_CHANNEL_DOMAIN_5G_FCC2 ++ {{36,40,44,48,52,56,60,64,149,153,157,161,165},13}, // 0x06, RT_CHANNEL_DOMAIN_5G_FCC3 ++ {{36,40,44,48,52,56,60,64,149,153,157,161},12}, // 0x07, RT_CHANNEL_DOMAIN_5G_FCC4 ++ {{149,153,157,161,165},5}, // 0x08, RT_CHANNEL_DOMAIN_5G_FCC5 ++ {{36,40,44,48,52,56,60,64},8}, // 0x09, RT_CHANNEL_DOMAIN_5G_FCC6 ++ {{36,40,44,48,52,56,60,64,100,104,108,112,116,136,140,149,153,157,161,165},20}, // 0x0A, RT_CHANNEL_DOMAIN_5G_FCC7_IC1 ++ {{36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,149,153,157,161,165},20}, // 0x0B, RT_CHANNEL_DOMAIN_5G_KCC1 ++ {{36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,128,132,136,140},19}, // 0x0C, RT_CHANNEL_DOMAIN_5G_MKK1 ++ {{36,40,44,48,52,56,60,64},8}, // 0x0D, RT_CHANNEL_DOMAIN_5G_MKK2 ++ {{100,104,108,112,116,120,124,128,132,136,140},11}, // 0x0E, RT_CHANNEL_DOMAIN_5G_MKK3 ++ {{56,60,64,100,104,108,112,116,136,140,149,153,157,161,165},15}, // 0x0F, RT_CHANNEL_DOMAIN_5G_NCC1 ++ {{56,60,64,149,153,157,161,165},8}, // 0x10, RT_CHANNEL_DOMAIN_5G_NCC2 ++ ++ //===== Driver self defined for old channel plan Compatible ,Remember to modify if have new channel plan definition ===== ++ {{36,40,44,48,52,56,60,64,100,104,108,112,116,132,136,140,149,153,157,161,165},21}, // 0x11, RT_CHANNEL_DOMAIN_5G_FCC ++ {{36,40,44,48},4}, // 0x12, RT_CHANNEL_DOMAIN_5G_JAPAN_NO_DFS ++}; ++ ++static RT_CHANNEL_PLAN_MAP RTW_ChannelPlanMap[RT_CHANNEL_DOMAIN_MAX] = { ++ //===== 0x00 ~ 0x1F , Old Define ===== ++ {0x02,0x11}, //0x00, RT_CHANNEL_DOMAIN_FCC ++ {0x02,0x0A}, //0x01, RT_CHANNEL_DOMAIN_IC ++ {0x01,0x01}, //0x02, RT_CHANNEL_DOMAIN_ETSI ++ {0x01,0x00}, //0x03, RT_CHANNEL_DOMAIN_SPAIN ++ {0x01,0x00}, //0x04, RT_CHANNEL_DOMAIN_FRANCE ++ {0x01,0x00}, //0x05, RT_CHANNEL_DOMAIN_MKK ++ {0x01,0x00}, //0x06, RT_CHANNEL_DOMAIN_MKK1 ++ {0x01,0x09}, //0x07, RT_CHANNEL_DOMAIN_ISRAEL ++ {0x03,0x09}, //0x08, RT_CHANNEL_DOMAIN_TELEC ++ {0x03,0x00}, //0x09, RT_CHANNEL_DOMAIN_GLOBAL_DOAMIN ++ {0x00,0x00}, //0x0A, RT_CHANNEL_DOMAIN_WORLD_WIDE_13 ++ {0x02,0x0F}, //0x0B, RT_CHANNEL_DOMAIN_TAIWAN ++ {0x01,0x08}, //0x0C, RT_CHANNEL_DOMAIN_CHINA ++ {0x02,0x06}, //0x0D, RT_CHANNEL_DOMAIN_SINGAPORE_INDIA_MEXICO ++ {0x02,0x0B}, //0x0E, RT_CHANNEL_DOMAIN_KOREA ++ {0x02,0x09}, //0x0F, RT_CHANNEL_DOMAIN_TURKEY ++ {0x01,0x01}, //0x10, RT_CHANNEL_DOMAIN_JAPAN ++ {0x02,0x05}, //0x11, RT_CHANNEL_DOMAIN_FCC_NO_DFS ++ {0x01,0x12}, //0x12, RT_CHANNEL_DOMAIN_JAPAN_NO_DFS ++ {0x00,0x04}, //0x13, RT_CHANNEL_DOMAIN_WORLD_WIDE_5G ++ {0x02,0x10}, //0x14, RT_CHANNEL_DOMAIN_TAIWAN_NO_DFS ++ {0x00,0x00}, //0x15, ++ {0x00,0x00}, //0x16, ++ {0x00,0x00}, //0x17, ++ {0x00,0x00}, //0x18, ++ {0x00,0x00}, //0x19, ++ {0x00,0x00}, //0x1A, ++ {0x00,0x00}, //0x1B, ++ {0x00,0x00}, //0x1C, ++ {0x00,0x00}, //0x1D, ++ {0x00,0x00}, //0x1E, ++ {0x00,0x00}, //0x1F, ++ ++ //===== 0x20 ~ 0x7F ,New Define ===== ++ {0x00,0x00}, //0x20, RT_CHANNEL_DOMAIN_WORLD_NULL ++ {0x01,0x00}, //0x21, RT_CHANNEL_DOMAIN_ETSI1_NULL ++ {0x02,0x00}, //0x22, RT_CHANNEL_DOMAIN_FCC1_NULL ++ {0x03,0x00}, //0x23, RT_CHANNEL_DOMAIN_MKK1_NULL ++ {0x04,0x00}, //0x24, RT_CHANNEL_DOMAIN_ETSI2_NULL ++ {0x02,0x04}, //0x25, RT_CHANNEL_DOMAIN_FCC1_FCC1 ++ {0x00,0x01}, //0x26, RT_CHANNEL_DOMAIN_WORLD_ETSI1 ++ {0x03,0x0C}, //0x27, RT_CHANNEL_DOMAIN_MKK1_MKK1 ++ {0x00,0x0B}, //0x28, RT_CHANNEL_DOMAIN_WORLD_KCC1 ++ {0x00,0x05}, //0x29, RT_CHANNEL_DOMAIN_WORLD_FCC2 ++ {0x00,0x00}, //0x2A, ++ {0x00,0x00}, //0x2B, ++ {0x00,0x00}, //0x2C, ++ {0x00,0x00}, //0x2D, ++ {0x00,0x00}, //0x2E, ++ {0x00,0x00}, //0x2F, ++ {0x00,0x06}, //0x30, RT_CHANNEL_DOMAIN_WORLD_FCC3 ++ {0x00,0x07}, //0x31, RT_CHANNEL_DOMAIN_WORLD_FCC4 ++ {0x00,0x08}, //0x32, RT_CHANNEL_DOMAIN_WORLD_FCC5 ++ {0x00,0x09}, //0x33, RT_CHANNEL_DOMAIN_WORLD_FCC6 ++ {0x02,0x0A}, //0x34, RT_CHANNEL_DOMAIN_FCC1_FCC7 ++ {0x00,0x02}, //0x35, RT_CHANNEL_DOMAIN_WORLD_ETSI2 ++ {0x00,0x03}, //0x36, RT_CHANNEL_DOMAIN_WORLD_ETSI3 ++ {0x03,0x0D}, //0x37, RT_CHANNEL_DOMAIN_MKK1_MKK2 ++ {0x03,0x0E}, //0x38, RT_CHANNEL_DOMAIN_MKK1_MKK3 ++ {0x02,0x0F}, //0x39, RT_CHANNEL_DOMAIN_FCC1_NCC1 ++ {0x00,0x00}, //0x3A, ++ {0x00,0x00}, //0x3B, ++ {0x00,0x00}, //0x3C, ++ {0x00,0x00}, //0x3D, ++ {0x00,0x00}, //0x3E, ++ {0x00,0x00}, //0x3F, ++ {0x02,0x10}, //0x40, RT_CHANNEL_DOMAIN_FCC1_NCC2 ++}; ++ ++static RT_CHANNEL_PLAN_MAP RTW_CHANNEL_PLAN_MAP_REALTEK_DEFINE = {0x02,0x05}; ++ ++/* ++* Test if the given @param channel_set contains the channel specified by @param channel_num ++* @param channel_set the given channel set ++* @param channel_num the given channel number ++* @return _TRUE or _FALSE ++*/ ++int rtw_is_channel_set_contains_channel(RT_CHANNEL_INFO *channel_set, const u32 channel_num) ++{ ++ int i; ++ for(i=0;channel_set[i].ChannelNum!=0;i++){ ++ if(channel_num == channel_set[i].ChannelNum) ++ return _TRUE; ++ } ++ if(channel_set[i].ChannelNum == 0) ++ return _FALSE; ++ return _TRUE; ++} ++ ++/**************************************************************************** ++ ++Following are the initialization functions for WiFi MLME ++ ++*****************************************************************************/ ++ ++int init_hw_mlme_ext(_adapter *padapter) ++{ ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ ++ //set_opmode_cmd(padapter, infra_client_with_mlme);//removed ++ ++ set_channel_bwmode(padapter, pmlmeext->cur_channel, pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode); ++ ++ return _SUCCESS; ++} ++ ++static void init_mlme_ext_priv_value(_adapter* padapter) ++{ ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ ++#ifdef CONFIG_TDLS ++ u8 i; ++#endif ++ ++ //unsigned char default_channel_set[MAX_CHANNEL_NUM] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 0, 0}; ++ unsigned char mixed_datarate[NumRates] = {_1M_RATE_, _2M_RATE_, _5M_RATE_, _11M_RATE_, _6M_RATE_,_9M_RATE_, _12M_RATE_, _18M_RATE_, _24M_RATE_, _36M_RATE_, _48M_RATE_, _54M_RATE_, 0xff}; ++ unsigned char mixed_basicrate[NumRates] ={_1M_RATE_, _2M_RATE_, _5M_RATE_, _11M_RATE_, 0xff,}; ++ ++ ATOMIC_SET(&pmlmeext->event_seq, 0); ++ pmlmeext->mgnt_seq = 0;//reset to zero when disconnect at client mode ++ ++ pmlmeext->cur_channel = padapter->registrypriv.channel; ++ pmlmeext->cur_bwmode = HT_CHANNEL_WIDTH_20; ++ pmlmeext->cur_ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; ++ pmlmeext->retry = 0; ++ ++ pmlmeext->cur_wireless_mode = padapter->registrypriv.wireless_mode; ++ ++ //_rtw_memcpy(pmlmeext->channel_set, DefaultChannelPlan[padapter->mlmepriv.ChannelPlan].Channel, DefaultChannelPlan[padapter->mlmepriv.ChannelPlan].Len); ++ //_rtw_memcpy(pmlmeext->channel_set, default_channel_set, MAX_CHANNEL_NUM); ++ _rtw_memcpy(pmlmeext->datarate, mixed_datarate, NumRates); ++ _rtw_memcpy(pmlmeext->basicrate, mixed_basicrate, NumRates); ++ ++ pmlmeext->sitesurvey_res.state = SCAN_DISABLE; ++ pmlmeext->sitesurvey_res.channel_idx = 0; ++ pmlmeext->sitesurvey_res.bss_cnt = 0; ++ ++ pmlmeext->scan_abort = _FALSE; ++ ++ pmlmeinfo->state = WIFI_FW_NULL_STATE; ++ pmlmeinfo->reauth_count = 0; ++ pmlmeinfo->reassoc_count = 0; ++ pmlmeinfo->link_count = 0; ++ pmlmeinfo->auth_seq = 0; ++ pmlmeinfo->auth_algo = dot11AuthAlgrthm_Open; ++ pmlmeinfo->key_index = 0; ++ pmlmeinfo->iv = 0; ++ ++ pmlmeinfo->enc_algo = _NO_PRIVACY_; ++ pmlmeinfo->authModeToggle = 0; ++ ++ _rtw_memset(pmlmeinfo->chg_txt, 0, 128); ++ ++ pmlmeinfo->slotTime = SHORT_SLOT_TIME; ++ pmlmeinfo->preamble_mode = PREAMBLE_AUTO; ++ ++ pmlmeinfo->dialogToken = 0; ++} ++ ++static u8 init_channel_set(_adapter* padapter, u8 ChannelPlan, RT_CHANNEL_INFO *channel_set) ++{ ++ u8 index,chanset_size = 0; ++ u8 b5GBand = _FALSE, b2_4GBand = _FALSE; ++ u8 Index2G = 0, Index5G=0; ++ ++ _rtw_memset(channel_set, 0, sizeof(RT_CHANNEL_INFO)*MAX_CHANNEL_NUM); ++ ++ if(ChannelPlan >= RT_CHANNEL_DOMAIN_MAX && ChannelPlan != RT_CHANNEL_DOMAIN_REALTEK_DEFINE) ++ { ++ DBG_871X("ChannelPlan ID %x error !!!!!\n",ChannelPlan); ++ return chanset_size; ++ } ++ ++ if(padapter->registrypriv.wireless_mode & WIRELESS_11G) ++ { ++ b2_4GBand = _TRUE; ++ if(RT_CHANNEL_DOMAIN_REALTEK_DEFINE == ChannelPlan) ++ Index2G = RTW_CHANNEL_PLAN_MAP_REALTEK_DEFINE.Index2G; ++ else ++ Index2G = RTW_ChannelPlanMap[ChannelPlan].Index2G; ++ } ++ ++ if(padapter->registrypriv.wireless_mode & WIRELESS_11A) ++ { ++ b5GBand = _TRUE; ++ if(RT_CHANNEL_DOMAIN_REALTEK_DEFINE == ChannelPlan) ++ Index5G = RTW_CHANNEL_PLAN_MAP_REALTEK_DEFINE.Index5G; ++ else ++ Index5G = RTW_ChannelPlanMap[ChannelPlan].Index5G; ++ } ++ ++ if(b2_4GBand) ++ { ++ for(index=0;index= 1 && channel_set[chanset_size].ChannelNum <= 11) ++ channel_set[chanset_size].ScanType = SCAN_ACTIVE; ++ else if((channel_set[chanset_size].ChannelNum >= 12 && channel_set[chanset_size].ChannelNum <= 14)) ++ channel_set[chanset_size].ScanType = SCAN_PASSIVE; ++ } ++ else if(RT_CHANNEL_DOMAIN_WORLD_WIDE_13 == ChannelPlan || ++ RT_CHANNEL_DOMAIN_WORLD_WIDE_5G == ChannelPlan || ++ RT_CHANNEL_DOMAIN_2G_WORLD == Index2G)// channel 12~13, passive scan ++ { ++ if(channel_set[chanset_size].ChannelNum <= 11) ++ channel_set[chanset_size].ScanType = SCAN_ACTIVE; ++ else ++ channel_set[chanset_size].ScanType = SCAN_PASSIVE; ++ } ++ else ++ { ++ channel_set[chanset_size].ScanType = SCAN_ACTIVE; ++ } ++ ++ chanset_size++; ++ } ++ } ++ ++ if(b5GBand) ++ { ++ for(index=0;index= 149 ) ++ { ++ if(RT_CHANNEL_DOMAIN_WORLD_WIDE_5G== ChannelPlan)//passive scan for all 5G channels ++ channel_set[chanset_size].ScanType = SCAN_PASSIVE; ++ else ++ channel_set[chanset_size].ScanType = SCAN_ACTIVE; ++ } ++ else ++ { ++ channel_set[chanset_size].ScanType = SCAN_PASSIVE; ++ } ++ chanset_size++; ++#else /* CONFIG_DFS */ ++ if ( RTW_ChannelPlan5G[Index5G].Channel[index] <= 48 ++ || RTW_ChannelPlan5G[Index5G].Channel[index] >= 149 ) { ++ channel_set[chanset_size].ChannelNum = RTW_ChannelPlan5G[Index5G].Channel[index]; ++ if(RT_CHANNEL_DOMAIN_WORLD_WIDE_5G== ChannelPlan)//passive scan for all 5G channels ++ channel_set[chanset_size].ScanType = SCAN_PASSIVE; ++ else ++ channel_set[chanset_size].ScanType = SCAN_ACTIVE; ++ DBG_871X("%s(): channel_set[%d].ChannelNum = %d\n", __FUNCTION__, chanset_size, channel_set[chanset_size].ChannelNum); ++ chanset_size++; ++ } ++#endif /* CONFIG_DFS */ ++ } ++ } ++ ++ return chanset_size; ++} ++ ++int init_mlme_ext_priv(_adapter* padapter) ++{ ++ int res = _SUCCESS; ++ struct registry_priv* pregistrypriv = &padapter->registrypriv; ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ ++ // We don't need to memset padapter->XXX to zero, because adapter is allocated by rtw_zvmalloc(). ++ //_rtw_memset((u8 *)pmlmeext, 0, sizeof(struct mlme_ext_priv)); ++ ++ pmlmeext->padapter = padapter; ++ ++ //fill_fwpriv(padapter, &(pmlmeext->fwpriv)); ++ ++ init_mlme_ext_priv_value(padapter); ++ pmlmeinfo->bAcceptAddbaReq = pregistrypriv->bAcceptAddbaReq; ++ ++ init_mlme_ext_timer(padapter); ++ ++#ifdef CONFIG_AP_MODE ++ init_mlme_ap_info(padapter); ++#endif ++ ++ pmlmeext->max_chan_nums = init_channel_set(padapter, pmlmepriv->ChannelPlan,pmlmeext->channel_set); ++ ++ pmlmeext->chan_scan_time = SURVEY_TO; ++ pmlmeext->mlmeext_init = _TRUE; ++ ++ return res; ++ ++} ++ ++void free_mlme_ext_priv (struct mlme_ext_priv *pmlmeext) ++{ ++ _adapter *padapter = pmlmeext->padapter; ++ ++ if (!padapter) ++ return; ++ ++ if (padapter->bDriverStopped == _TRUE) ++ { ++ _cancel_timer_ex(&pmlmeext->survey_timer); ++ _cancel_timer_ex(&pmlmeext->link_timer); ++ //_cancel_timer_ex(&pmlmeext->ADDBA_timer); ++ } ++} ++ ++#ifdef CONFIG_TDLS ++int rtw_init_tdls_info(_adapter* padapter) ++{ ++ int res = _SUCCESS; ++ int i; ++ struct tdls_info *ptdlsinfo = &padapter->tdlsinfo; ++ ++ _rtw_memset(ptdlsinfo, 0, sizeof(struct tdls_info) ); ++ ++ ptdlsinfo->ap_prohibited = _FALSE; ++ ptdlsinfo->setup_state = UN_TDLS_STATE; ++ ptdlsinfo->sta_cnt = 0; ++ ptdlsinfo->sta_maximum = _FALSE; ++ ptdlsinfo->cam_entry_to_write = 6; ++ ptdlsinfo->cam_entry_to_clear = 0; ++ ptdlsinfo->ch_sensing = 0; ++ ptdlsinfo->cur_channel = 0; ++ ptdlsinfo->candidate_ch = 1; //when inplement channel switching, default candidate channel is 1 ++ ++ _rtw_spinlock_init(&ptdlsinfo->cmd_lock); ++ _rtw_spinlock_init(&ptdlsinfo->hdl_lock); ++ ++ return res; ++ ++} ++ ++void rtw_free_tdls_info(struct tdls_info *ptdlsinfo) ++{ ++ _rtw_spinlock_free(&ptdlsinfo->cmd_lock); ++ _rtw_spinlock_free(&ptdlsinfo->hdl_lock); ++ ++ _rtw_memset(ptdlsinfo, 0, sizeof(struct tdls_info) ); ++ ++} ++#endif //CONFIG_TDLS ++ ++static void UpdateBrateTbl( ++ IN PADAPTER Adapter, ++ IN u8 *mBratesOS ++) ++{ ++ u8 i; ++ u8 rate; ++ ++ // 1M, 2M, 5.5M, 11M, 6M, 12M, 24M are mandatory. ++ for(i=0;imlmeextpriv.cur_channel >= channel) ++ { ++ return (padapter->mlmeextpriv.cur_channel - channel); ++ } ++ else ++ { ++ return (channel-padapter->mlmeextpriv.cur_channel); ++ } ++ } ++ else ++ { ++ return 0; ++ } ++} ++static void _mgt_dispatcher(_adapter *padapter, struct mlme_handler *ptable, union recv_frame *precv_frame) ++{ ++ u8 bc_addr[ETH_ALEN] = {0xff,0xff,0xff,0xff,0xff,0xff}; ++ u8 *pframe = precv_frame->u.hdr.rx_data; ++ uint len = precv_frame->u.hdr.len; ++ ++ if(ptable->func) ++ { ++ //receive the frames that ra(a1) is my address or ra(a1) is bc address. ++ if (!_rtw_memcmp(GetAddr1Ptr(pframe), myid(&padapter->eeprompriv), ETH_ALEN) && ++ !_rtw_memcmp(GetAddr1Ptr(pframe), bc_addr, ETH_ALEN)) ++ { ++ return; ++ } ++ ++ ptable->func(padapter, precv_frame); ++ } ++ ++} ++ ++void mgt_dispatcher(_adapter *padapter, union recv_frame *precv_frame) ++{ ++ int index; ++ struct mlme_handler *ptable; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ u8 bc_addr[ETH_ALEN] = {0xff,0xff,0xff,0xff,0xff,0xff}; ++ u8 *pframe = precv_frame->u.hdr.rx_data; ++ uint len = precv_frame->u.hdr.len; ++ ++ RT_TRACE(_module_rtl871x_mlme_c_, _drv_info_, ++ ("+mgt_dispatcher: type(0x%x) subtype(0x%x)\n", ++ GetFrameType(pframe), GetFrameSubType(pframe))); ++ ++#if 0 ++ { ++ u8 *pbuf; ++ pbuf = GetAddr1Ptr(pframe); ++ DBG_8192C("A1-%x:%x:%x:%x:%x:%x\n", *pbuf, *(pbuf+1), *(pbuf+2), *(pbuf+3), *(pbuf+4), *(pbuf+5)); ++ pbuf = GetAddr2Ptr(pframe); ++ DBG_8192C("A2-%x:%x:%x:%x:%x:%x\n", *pbuf, *(pbuf+1), *(pbuf+2), *(pbuf+3), *(pbuf+4), *(pbuf+5)); ++ pbuf = GetAddr3Ptr(pframe); ++ DBG_8192C("A3-%x:%x:%x:%x:%x:%x\n", *pbuf, *(pbuf+1), *(pbuf+2), *(pbuf+3), *(pbuf+4), *(pbuf+5)); ++ } ++#endif ++ ++ if (GetFrameType(pframe) != WIFI_MGT_TYPE) ++ { ++ RT_TRACE(_module_rtl871x_mlme_c_, _drv_err_, ("mgt_dispatcher: type(0x%x) error!\n", GetFrameType(pframe))); ++ return; ++ } ++ ++ //receive the frames that ra(a1) is my address or ra(a1) is bc address. ++ if (!_rtw_memcmp(GetAddr1Ptr(pframe), myid(&padapter->eeprompriv), ETH_ALEN) && ++ !_rtw_memcmp(GetAddr1Ptr(pframe), bc_addr, ETH_ALEN)) ++ { ++ return; ++ } ++ ++ ptable = mlme_sta_tbl; ++ ++ index = GetFrameSubType(pframe) >> 4; ++ ++#ifdef CONFIG_TDLS ++ if((index << 4)==WIFI_ACTION){ ++ //category==public (4), action==TDLS_DISCOVERY_RESPONSE ++ if(*(pframe+24)==0x04 && *(pframe+25)==TDLS_DISCOVERY_RESPONSE){ ++ DBG_8192C("recv tdls discovery response frame\n"); ++ On_TDLS_Dis_Rsp(padapter, precv_frame); ++ } ++ } ++#endif ++ ++ if (index > 13) ++ { ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("Currently we do not support reserved sub-fr-type=%d\n", index)); ++ return; ++ } ++ ptable += index; ++ ++#if 0//gtest ++ sa = get_sa(pframe); ++ psta = search_assoc_sta(sa, padapter); ++ // only check last cache seq number for management frame ++ if (psta != NULL) { ++ if (GetRetry(pframe)) { ++ if (GetTupleCache(pframe) == psta->rxcache->nonqos_seq){ ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("drop due to decache!\n")); ++ return; ++ } ++ } ++ psta->rxcache->nonqos_seq = GetTupleCache(pframe); ++ } ++#else ++ ++ if(GetRetry(pframe)) ++ { ++ //RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("drop due to decache!\n")); ++ //return; ++ } ++#endif ++ ++#ifdef CONFIG_AP_MODE ++ switch (GetFrameSubType(pframe)) ++ { ++ case WIFI_AUTH: ++ if(check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) ++ ptable->func = &OnAuth; ++ else ++ ptable->func = &OnAuthClient; ++ //pass through ++ case WIFI_ASSOCREQ: ++ case WIFI_REASSOCREQ: ++ _mgt_dispatcher(padapter, ptable, precv_frame); ++#ifdef CONFIG_HOSTAPD_MLME ++ if(check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) ++ rtw_hostapd_mlme_rx(padapter, precv_frame); ++#endif ++ break; ++ case WIFI_PROBEREQ: ++ if(check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) ++ { ++#ifdef CONFIG_HOSTAPD_MLME ++ rtw_hostapd_mlme_rx(padapter, precv_frame); ++#else ++ _mgt_dispatcher(padapter, ptable, precv_frame); ++#endif ++ } ++ else ++ _mgt_dispatcher(padapter, ptable, precv_frame); ++ break; ++ case WIFI_BEACON: ++ _mgt_dispatcher(padapter, ptable, precv_frame); ++ break; ++ case WIFI_ACTION: ++ //if(check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) ++ _mgt_dispatcher(padapter, ptable, precv_frame); ++ break; ++ default: ++ _mgt_dispatcher(padapter, ptable, precv_frame); ++ if(check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) ++ rtw_hostapd_mlme_rx(padapter, precv_frame); ++ break; ++ } ++#else ++ ++ _mgt_dispatcher(padapter, ptable, precv_frame); ++ ++#endif ++ ++} ++ ++#ifdef CONFIG_P2P ++u32 p2p_listen_state_process(_adapter *padapter, unsigned char *da) ++{ ++ issue_probersp_p2p( padapter, da); ++ return _SUCCESS; ++} ++#endif //CONFIG_P2P ++ ++ ++/**************************************************************************** ++ ++Following are the callback functions for each subtype of the management frames ++ ++*****************************************************************************/ ++ ++unsigned int OnProbeReq(_adapter *padapter, union recv_frame *precv_frame) ++{ ++ unsigned int ielen; ++ unsigned char *p; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ WLAN_BSSID_EX *cur = &(pmlmeinfo->network); ++ u8 *pframe = precv_frame->u.hdr.rx_data; ++ uint len = precv_frame->u.hdr.len; ++ u8 is_valid_p2p_probereq = _FALSE; ++ ++#ifdef CONFIG_P2P ++ struct wifidirect_info *pwdinfo = &(padapter->wdinfo); ++ struct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib; ++ ++ if ( !rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE) && ++ !rtw_p2p_chk_state(pwdinfo, P2P_STATE_IDLE) && ++ !rtw_p2p_chk_role(pwdinfo, P2P_ROLE_CLIENT) && ++ !rtw_p2p_chk_state(pwdinfo, P2P_STATE_FIND_PHASE_SEARCH) && ++ !rtw_p2p_chk_state(pwdinfo, P2P_STATE_SCAN) ++ ) ++ { ++ // Commented by Albert 2011/03/17 ++ // mcs_rate = 0 -> CCK 1M rate ++ // mcs_rate = 1 -> CCK 2M rate ++ // mcs_rate = 2 -> CCK 5.5M rate ++ // mcs_rate = 3 -> CCK 11M rate ++ // In the P2P mode, the driver should not support the CCK rate ++ if ( pattrib->mcs_rate > 3 ) ++ { ++ if((is_valid_p2p_probereq = process_probe_req_p2p_ie(pwdinfo, pframe, len)) == _TRUE) ++ { ++ if(rtw_p2p_chk_role(pwdinfo, P2P_ROLE_DEVICE)) ++ { ++ p2p_listen_state_process( padapter, get_sa(pframe)); ++ ++ return _SUCCESS; ++ } ++ ++ if(rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) ++ { ++ goto _continue; ++ } ++ } ++ } ++ } ++ ++_continue: ++#endif //CONFIG_P2P ++ ++ if(check_fwstate(pmlmepriv, WIFI_STATION_STATE)) ++ { ++ return _SUCCESS; ++ } ++ ++ if(check_fwstate(pmlmepriv, _FW_LINKED) == _FALSE && ++ check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE|WIFI_AP_STATE)==_FALSE) ++ { ++ return _SUCCESS; ++ } ++ ++ ++ //DBG_871X("+OnProbeReq\n"); ++ ++ p = rtw_get_ie(pframe + WLAN_HDR_A3_LEN + _PROBEREQ_IE_OFFSET_, _SSID_IE_, (int *)&ielen, ++ len - WLAN_HDR_A3_LEN - _PROBEREQ_IE_OFFSET_); ++ ++ ++ //check (wildcard) SSID ++ if (p != NULL) ++ { ++ if(is_valid_p2p_probereq == _TRUE) ++ { ++ goto _issue_probersp; ++ } ++ ++ if ( (ielen != 0 && _FALSE ==_rtw_memcmp((void *)(p+2), (void *)cur->Ssid.Ssid, cur->Ssid.SsidLength)) ++ || (ielen == 0 && pmlmeinfo->hidden_ssid_mode) ++ ) ++ { ++ return _SUCCESS; ++ } ++ ++_issue_probersp: ++ ++ if(check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE && ++ pmlmepriv->cur_network.join_res == _TRUE) ++ { ++ //DBG_871X("+issue_probersp during ap mode\n"); ++ issue_probersp(padapter, get_sa(pframe), is_valid_p2p_probereq); ++ } ++ ++ } ++ ++ return _SUCCESS; ++ ++} ++ ++unsigned int OnProbeRsp(_adapter *padapter, union recv_frame *precv_frame) ++{ ++ struct sta_info *psta; ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ u8 *pframe = precv_frame->u.hdr.rx_data; ++#ifdef CONFIG_P2P ++ struct wifidirect_info *pwdinfo = &padapter->wdinfo; ++#endif ++ ++ ++#ifdef CONFIG_P2P ++ if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_TX_PROVISION_DIS_REQ)) ++ { ++ if ( _TRUE == pwdinfo->tx_prov_disc_info.benable ) ++ { ++ if( _rtw_memcmp( pwdinfo->tx_prov_disc_info.peerIFAddr, GetAddr2Ptr(pframe), ETH_ALEN ) ) ++ { ++ if(rtw_p2p_chk_role(pwdinfo, P2P_ROLE_CLIENT)) ++ { ++ pwdinfo->tx_prov_disc_info.benable = _FALSE; ++ issue_p2p_provision_request( padapter, ++ pwdinfo->tx_prov_disc_info.peerIFAddr, ++ pwdinfo->tx_prov_disc_info.ssid.Ssid, ++ pwdinfo->tx_prov_disc_info.ssid.SsidLength, ++ pwdinfo->tx_prov_disc_info.peerDevAddr ); ++ } ++ else if ( rtw_p2p_chk_role(pwdinfo, P2P_ROLE_DEVICE) || rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO) ) ++ { ++ pwdinfo->tx_prov_disc_info.benable = _FALSE; ++ issue_p2p_provision_request( padapter, ++ pwdinfo->tx_prov_disc_info.peerIFAddr, ++ NULL, ++ 0, ++ pwdinfo->tx_prov_disc_info.peerDevAddr ); ++ } ++ } ++ } ++ return _SUCCESS; ++ } ++ else if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_GONEGO_ING)) ++ { ++ if ( _TRUE == pwdinfo->nego_req_info.benable ) ++ { ++ DBG_871X( "[%s] P2P State is GONEGO ING!\n", __FUNCTION__ ); ++ if( _rtw_memcmp( pwdinfo->nego_req_info.peerDevAddr, GetAddr2Ptr(pframe), ETH_ALEN ) ) ++ { ++ pwdinfo->nego_req_info.benable = _FALSE; ++ issue_p2p_GO_request( padapter, pwdinfo->nego_req_info.peerDevAddr); ++ } ++ } ++ } ++#endif ++ ++ ++ if (pmlmeext->sitesurvey_res.state == SCAN_PROCESS) ++ { ++ report_survey_event(padapter, precv_frame); ++ return _SUCCESS; ++ } ++ ++ #if 0 //move to validate_recv_mgnt_frame ++ if (_rtw_memcmp(GetAddr3Ptr(pframe), get_my_bssid(&pmlmeinfo->network), ETH_ALEN)) ++ { ++ if (pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS) ++ { ++ if ((psta = rtw_get_stainfo(pstapriv, GetAddr2Ptr(pframe))) != NULL) ++ { ++ psta->sta_stats.rx_mgnt_pkts++; ++ } ++ } ++ } ++ #endif ++ ++ return _SUCCESS; ++ ++} ++ ++unsigned int OnBeacon(_adapter *padapter, union recv_frame *precv_frame) ++{ ++ int cam_idx; ++ struct sta_info *psta; ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ u8 *pframe = precv_frame->u.hdr.rx_data; ++ uint len = precv_frame->u.hdr.len; ++ ++ if (pmlmeext->sitesurvey_res.state == SCAN_PROCESS) ++ { ++ report_survey_event(padapter, precv_frame); ++ return _SUCCESS; ++ } ++ ++ if (_rtw_memcmp(GetAddr3Ptr(pframe), get_my_bssid(&pmlmeinfo->network), ETH_ALEN)) ++ { ++ if (pmlmeinfo->state & WIFI_FW_AUTH_NULL) ++ { ++ //check the vendor of the assoc AP ++ pmlmeinfo->assoc_AP_vendor = check_assoc_AP(pframe+sizeof(struct rtw_ieee80211_hdr_3addr), len-sizeof(struct rtw_ieee80211_hdr_3addr)); ++ ++ //update TSF Value ++ update_TSF(pmlmeext, pframe, len); ++ ++ //start auth ++ start_clnt_auth(padapter); ++ ++ return _SUCCESS; ++ } ++ ++ if(((pmlmeinfo->state&0x03) == WIFI_FW_STATION_STATE) && (pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS)) ++ { ++ if ((psta = rtw_get_stainfo(pstapriv, GetAddr2Ptr(pframe))) != NULL) ++ { ++ #ifdef CONFIG_PATCH_JOIN_WRONG_CHANNEL ++ //Merge from 8712 FW code ++ if (cmp_pkt_chnl_diff(padapter,pframe,len) != 0) ++ { // join wrong channel, deauth and reconnect ++ issue_deauth(padapter, (&(pmlmeinfo->network))->MacAddress, WLAN_REASON_DEAUTH_LEAVING); ++ ++ report_del_sta_event(padapter,(&(pmlmeinfo->network))->MacAddress, WLAN_REASON_JOIN_WRONG_CHANNEL); ++ pmlmeinfo->state &= (~WIFI_FW_ASSOC_SUCCESS); ++ return _SUCCESS; ++ } ++ #endif //CONFIG_PATCH_JOIN_WRONG_CHANNEL ++ ++ //update WMM, ERP in the beacon ++ //todo: the timer is used instead of the number of the beacon received ++ if ((sta_rx_pkts(psta) & 0xf) == 0) ++ { ++ //DBG_871X("update_bcn_info\n"); ++ update_beacon_info(padapter, pframe, len, psta); ++ } ++ ++#ifdef CONFIG_DFS ++ process_csa_ie(padapter, pframe, len); //channel switch announcement ++#endif //CONFIG_DFS ++ ++#ifdef CONFIG_P2P ++ process_p2p_ps_ie(padapter, (pframe + WLAN_HDR_A3_LEN), (len - WLAN_HDR_A3_LEN)); ++#endif //CONFIG_P2P ++ ++ #if 0 //move to validate_recv_mgnt_frame ++ psta->sta_stats.rx_mgnt_pkts++; ++ #endif ++ } ++ } ++ else if((pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE) ++ { ++ if ((psta = rtw_get_stainfo(pstapriv, GetAddr2Ptr(pframe))) != NULL) ++ { ++ //update WMM, ERP in the beacon ++ //todo: the timer is used instead of the number of the beacon received ++ if ((sta_rx_pkts(psta) & 0xf) == 0) ++ { ++ //DBG_871X("update_bcn_info\n"); ++ update_beacon_info(padapter, pframe, len, psta); ++ } ++ ++ #if 0 //move to validate_recv_mgnt_frame ++ psta->sta_stats.rx_mgnt_pkts++; ++ #endif ++ } ++ else ++ { ++ //allocate a new CAM entry for IBSS station ++ if ((cam_idx = allocate_fw_sta_entry(padapter)) == NUM_STA) ++ { ++ goto _END_ONBEACON_; ++ } ++ ++ //get supported rate ++ if (update_sta_support_rate(padapter, (pframe + WLAN_HDR_A3_LEN + _BEACON_IE_OFFSET_), (len - WLAN_HDR_A3_LEN - _BEACON_IE_OFFSET_), cam_idx) == _FAIL) ++ { ++ pmlmeinfo->FW_sta_info[cam_idx].status = 0; ++ goto _END_ONBEACON_; ++ } ++ ++ //update TSF Value ++ update_TSF(pmlmeext, pframe, len); ++ ++ //report sta add event ++ report_add_sta_event(padapter, GetAddr2Ptr(pframe), cam_idx); ++ } ++ } ++ } ++ ++_END_ONBEACON_: ++ ++ return _SUCCESS; ++ ++} ++ ++unsigned int OnAuth(_adapter *padapter, union recv_frame *precv_frame) ++{ ++#ifdef CONFIG_AP_MODE ++ _irqL irqL; ++ unsigned int auth_mode, seq, ie_len; ++ unsigned char *sa, *p; ++ u16 algorithm; ++ int status; ++ static struct sta_info stat; ++ struct sta_info *pstat=NULL; ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ struct security_priv *psecuritypriv = &padapter->securitypriv; ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ u8 *pframe = precv_frame->u.hdr.rx_data; ++ uint len = precv_frame->u.hdr.len; ++ ++ if((pmlmeinfo->state&0x03) != WIFI_FW_AP_STATE) ++ return _FAIL; ++ ++ DBG_871X("+OnAuth\n"); ++ ++ sa = GetAddr2Ptr(pframe); ++ ++ auth_mode = psecuritypriv->dot11AuthAlgrthm; ++ seq = cpu_to_le16(*(unsigned short *)((unsigned int)pframe + WLAN_HDR_A3_LEN + 2)); ++ algorithm = cpu_to_le16(*(unsigned short *)((unsigned int)pframe + WLAN_HDR_A3_LEN)); ++ ++ if (GetPrivacy(pframe)) ++ { ++#if 0 //TODO: SW rtw_wep_decrypt ++ if (SWCRYPTO) ++ { ++ status = rtw_wep_decrypt(priv, pframe, pfrinfo->pktlen, ++ priv->pmib->dot1180211AuthEntry.dot11PrivacyAlgrthm); ++ if (status == FALSE) ++ { ++ SAVE_INT_AND_CLI(flags); ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,"wep-decrypt a Auth frame error!\n"); ++ status = _STATS_CHALLENGE_FAIL_; ++ goto auth_fail; ++ } ++ } ++ ++ seq = cpu_to_le16(*(unsigned short *)((unsigned int)pframe + WLAN_HDR_A3_LEN + 4 + 2)); ++ algorithm = cpu_to_le16(*(unsigned short *)((unsigned int)pframe + WLAN_HDR_A3_LEN + 4)); ++#endif ++ } ++ ++ ++ DBG_871X("auth alg=%x, seq=%X\n", algorithm, seq); ++ ++ if (auth_mode == 2 && ++ psecuritypriv->dot11PrivacyAlgrthm != _WEP40_ && ++ psecuritypriv->dot11PrivacyAlgrthm != _WEP104_) ++ auth_mode = 0; ++ ++ if ((algorithm > 0 && auth_mode == 0) || // rx a shared-key auth but shared not enabled ++ (algorithm == 0 && auth_mode == 1) ) // rx a open-system auth but shared-key is enabled ++ { ++ DBG_871X("auth rejected due to bad alg [alg=%d, auth_mib=%d] %02X%02X%02X%02X%02X%02X\n", ++ algorithm, auth_mode, sa[0], sa[1], sa[2], sa[3], sa[4], sa[5]); ++ ++ status = _STATS_NO_SUPP_ALG_; ++ ++ goto auth_fail; ++ } ++ ++#if 0 //TODO:ACL control ++ phead = &priv->wlan_acl_list; ++ plist = phead->next; ++ //check sa ++ if (acl_mode == 1) // 1: positive check, only those on acl_list can be connected. ++ res = FAIL; ++ else ++ res = SUCCESS; ++ ++ while(plist != phead) ++ { ++ paclnode = list_entry(plist, struct rtw_wlan_acl_node, list); ++ plist = plist->next; ++ if (!memcmp((void *)sa, paclnode->addr, 6)) { ++ if (paclnode->mode & 2) { // deny ++ res = FAIL; ++ break; ++ } ++ else { ++ res = SUCCESS; ++ break; ++ } ++ } ++ } ++ ++ if (res != SUCCESS) { ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,"auth abort because ACL!\n"); ++ return FAIL; ++ } ++#endif ++ ++ pstat = rtw_get_stainfo(pstapriv, sa); ++ if (pstat == NULL) ++ { ++ // allocate a new one ++ DBG_871X("going to alloc stainfo for sa=%02X%02X%02X%02X%02X%02X\n", sa[0],sa[1],sa[2],sa[3],sa[4],sa[5]); ++ pstat = rtw_alloc_stainfo(pstapriv, sa); ++ if (pstat == NULL) ++ { ++ DBG_871X(" Exceed the upper limit of supported clients...\n"); ++ status = _STATS_UNABLE_HANDLE_STA_; ++ goto auth_fail; ++ } ++ ++ pstat->state = WIFI_FW_AUTH_NULL; ++ pstat->auth_seq = 0; ++ ++ //pstat->flags = 0; ++ //pstat->capability = 0; ++ } ++ else ++ { ++ _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL); ++ if(rtw_is_list_empty(&pstat->asoc_list)==_FALSE) ++ { ++ rtw_list_delete(&pstat->asoc_list); ++ if (pstat->expire_to > 0) ++ { ++ //TODO: STA re_auth within expire_to ++ } ++ } ++ _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL); ++ ++ if (seq==1) { ++ //TODO: STA re_auth and auth timeout ++ } ++ } ++ ++ _enter_critical_bh(&pstapriv->auth_list_lock, &irqL); ++ if (rtw_is_list_empty(&pstat->auth_list)) ++ { ++ rtw_list_insert_tail(&pstat->auth_list, &pstapriv->auth_list); ++ } ++ _exit_critical_bh(&pstapriv->auth_list_lock, &irqL); ++ ++ if (pstat->auth_seq == 0) ++ pstat->expire_to = pstapriv->auth_to; ++ ++ if ((pstat->auth_seq + 1) != seq) ++ { ++ DBG_871X("(1)auth rejected because out of seq [rx_seq=%d, exp_seq=%d]!\n", ++ seq, pstat->auth_seq+1); ++ status = _STATS_OUT_OF_AUTH_SEQ_; ++ goto auth_fail; ++ } ++ ++ if (algorithm==0 && (auth_mode == 0 || auth_mode == 2)) ++ { ++ if (seq == 1) ++ { ++ pstat->state &= ~WIFI_FW_AUTH_NULL; ++ pstat->state |= WIFI_FW_AUTH_SUCCESS; ++ pstat->expire_to = pstapriv->assoc_to; ++ pstat->authalg = algorithm; ++ } ++ else ++ { ++ DBG_871X("(2)auth rejected because out of seq [rx_seq=%d, exp_seq=%d]!\n", ++ seq, pstat->auth_seq+1); ++ status = _STATS_OUT_OF_AUTH_SEQ_; ++ goto auth_fail; ++ } ++ } ++ else // shared system or auto authentication ++ { ++ if (seq == 1) ++ { ++ //prepare for the challenging txt... ++ ++ //get_random_bytes((void *)pstat->chg_txt, 128);//TODO: ++ ++ pstat->state &= ~WIFI_FW_AUTH_NULL; ++ pstat->state |= WIFI_FW_AUTH_STATE; ++ pstat->authalg = algorithm; ++ pstat->auth_seq = 2; ++ } ++ else if (seq == 3) ++ { ++ //checking for challenging txt... ++ DBG_871X("checking for challenging txt...\n"); ++ ++ p = rtw_get_ie(pframe + WLAN_HDR_A3_LEN + 4 + _AUTH_IE_OFFSET_ , _CHLGETXT_IE_, (int *)&ie_len, ++ len - WLAN_HDR_A3_LEN - _AUTH_IE_OFFSET_ - 4); ++ ++ if((p==NULL) || (ie_len<=0)) ++ { ++ DBG_871X("auth rejected because challenge failure!(1)\n"); ++ status = _STATS_CHALLENGE_FAIL_; ++ goto auth_fail; ++ } ++ ++ if (_rtw_memcmp((void *)(p + 2), pstat->chg_txt, 128)) ++ { ++ pstat->state &= (~WIFI_FW_AUTH_STATE); ++ pstat->state |= WIFI_FW_AUTH_SUCCESS; ++ // challenging txt is correct... ++ pstat->expire_to = pstapriv->assoc_to; ++ } ++ else ++ { ++ DBG_871X("auth rejected because challenge failure!\n"); ++ status = _STATS_CHALLENGE_FAIL_; ++ goto auth_fail; ++ } ++ } ++ else ++ { ++ DBG_871X("(3)auth rejected because out of seq [rx_seq=%d, exp_seq=%d]!\n", ++ seq, pstat->auth_seq+1); ++ status = _STATS_OUT_OF_AUTH_SEQ_; ++ goto auth_fail; ++ } ++ } ++ ++ ++ // Now, we are going to issue_auth... ++ pstat->auth_seq = seq + 1; ++ ++#ifdef CONFIG_NATIVEAP_MLME ++ issue_auth(padapter, pstat, (unsigned short)(_STATS_SUCCESSFUL_)); ++#endif ++ ++ if (pstat->state & WIFI_FW_AUTH_SUCCESS) ++ pstat->auth_seq = 0; ++ ++ ++ return _SUCCESS; ++ ++auth_fail: ++ ++ if (pstat) ++ { ++ pstat = &stat; ++ _rtw_memset((char *)pstat, '\0', sizeof(stat)); ++ pstat->auth_seq = 2; ++ _rtw_memcpy(pstat->hwaddr, sa, 6); ++ } ++ ++#ifdef CONFIG_NATIVEAP_MLME ++ issue_auth(padapter, pstat, (unsigned short)status); ++#endif ++ ++#endif ++ return _FAIL; ++ ++} ++ ++unsigned int OnAuthClient(_adapter *padapter, union recv_frame *precv_frame) ++{ ++ unsigned int seq, len, status, algthm, offset; ++ unsigned char *p; ++ unsigned int go2asoc = 0; ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ u8 *pframe = precv_frame->u.hdr.rx_data; ++ uint pkt_len = precv_frame->u.hdr.len; ++ ++ DBG_871X("%s\n", __FUNCTION__); ++ ++ //check A1 matches or not ++ if (!_rtw_memcmp(myid(&(padapter->eeprompriv)), get_da(pframe), ETH_ALEN)) ++ return _SUCCESS; ++ ++ if (!(pmlmeinfo->state & WIFI_FW_AUTH_STATE)) ++ return _SUCCESS; ++ ++ offset = (GetPrivacy(pframe))? 4: 0; ++ ++ algthm = le16_to_cpu(*(unsigned short *)((SIZE_PTR)pframe + WLAN_HDR_A3_LEN + offset)); ++ seq = le16_to_cpu(*(unsigned short *)((SIZE_PTR)pframe + WLAN_HDR_A3_LEN + offset + 2)); ++ status = le16_to_cpu(*(unsigned short *)((SIZE_PTR)pframe + WLAN_HDR_A3_LEN + offset + 4)); ++ ++ if (status != 0) ++ { ++ DBG_871X("clnt auth fail, status: %d\n", status); ++ if(status == 13)//&& pmlmeinfo->auth_algo == dot11AuthAlgrthm_Auto) ++ { ++ if(pmlmeinfo->auth_algo == dot11AuthAlgrthm_Shared) ++ pmlmeinfo->auth_algo = dot11AuthAlgrthm_Open; ++ else ++ pmlmeinfo->auth_algo = dot11AuthAlgrthm_Shared; ++ //pmlmeinfo->reauth_count = 0; ++ } ++ ++ set_link_timer(pmlmeext, 1); ++ goto authclnt_fail; ++ } ++ ++ if (seq == 2) ++ { ++ if (pmlmeinfo->auth_algo == dot11AuthAlgrthm_Shared) ++ { ++ // legendary shared system ++ p = rtw_get_ie(pframe + WLAN_HDR_A3_LEN + _AUTH_IE_OFFSET_, _CHLGETXT_IE_, (int *)&len, ++ pkt_len - WLAN_HDR_A3_LEN - _AUTH_IE_OFFSET_); ++ ++ if (p == NULL) ++ { ++ //DBG_8192C("marc: no challenge text?\n"); ++ goto authclnt_fail; ++ } ++ ++ _rtw_memcpy((void *)(pmlmeinfo->chg_txt), (void *)(p + 2), len); ++ pmlmeinfo->auth_seq = 3; ++ issue_auth(padapter, NULL, 0); ++ set_link_timer(pmlmeext, REAUTH_TO); ++ ++ return _SUCCESS; ++ } ++ else ++ { ++ // open system ++ go2asoc = 1; ++ } ++ } ++ else if (seq == 4) ++ { ++ if (pmlmeinfo->auth_algo == dot11AuthAlgrthm_Shared) ++ { ++ go2asoc = 1; ++ } ++ else ++ { ++ goto authclnt_fail; ++ } ++ } ++ else ++ { ++ // this is also illegal ++ //DBG_8192C("marc: clnt auth failed due to illegal seq=%x\n", seq); ++ goto authclnt_fail; ++ } ++ ++ if (go2asoc) ++ { ++ start_clnt_assoc(padapter); ++ return _SUCCESS; ++ } ++ ++authclnt_fail: ++ ++ //pmlmeinfo->state &= ~(WIFI_FW_AUTH_STATE); ++ ++ return _FAIL; ++ ++} ++ ++unsigned int OnAssocReq(_adapter *padapter, union recv_frame *precv_frame) ++{ ++#ifdef CONFIG_AP_MODE ++ _irqL irqL; ++ u16 capab_info, listen_interval; ++ struct ieee802_11_elems elems; ++ struct sta_info *pstat; ++ unsigned char reassoc, *p, *pos, *wpa_ie; ++ unsigned char rsnie_hdr[4]={0x00, 0x50, 0xf2, 0x01}; ++ unsigned char WMM_IE[] = {0x00, 0x50, 0xf2, 0x02, 0x00, 0x01}; ++ int i, ie_len, wpa_ie_len, left; ++ unsigned long flags; ++ unsigned char supportRate[16]; ++ int supportRateNum; ++ unsigned short status = _STATS_SUCCESSFUL_; ++ unsigned short frame_type, ie_offset=0; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct security_priv *psecuritypriv = &padapter->securitypriv; ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ WLAN_BSSID_EX *cur = &(pmlmeinfo->network); ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ u8 *pframe = precv_frame->u.hdr.rx_data; ++ uint pkt_len = precv_frame->u.hdr.len; ++#ifdef CONFIG_P2P ++ struct wifidirect_info *pwdinfo = &(padapter->wdinfo); ++ u8 p2p_status_code = P2P_STATUS_SUCCESS; ++ u8 *p2pie; ++ u32 p2pielen = 0; ++#ifdef CONFIG_WFD ++ u8 wfd_ie[ 128 ] = { 0x00 }; ++ u32 wfd_ielen = 0; ++#endif // CONFIG_WFD ++#endif //CONFIG_P2P ++ ++ if((pmlmeinfo->state&0x03) != WIFI_FW_AP_STATE) ++ return _FAIL; ++ ++ frame_type = GetFrameSubType(pframe); ++ if (frame_type == WIFI_ASSOCREQ) ++ { ++ reassoc = 0; ++ ie_offset = _ASOCREQ_IE_OFFSET_; ++ } ++ else // WIFI_REASSOCREQ ++ { ++ reassoc = 1; ++ ie_offset = _REASOCREQ_IE_OFFSET_; ++ } ++ ++ ++ if (pkt_len < IEEE80211_3ADDR_LEN + ie_offset) { ++ DBG_871X("handle_assoc(reassoc=%d) - too short payload (len=%lu)" ++ "\n", reassoc, (unsigned long)pkt_len); ++ return _FAIL; ++ } ++ ++ pstat = rtw_get_stainfo(pstapriv, GetAddr2Ptr(pframe)); ++ if (pstat == (struct sta_info *)NULL) ++ { ++ status = _RSON_CLS2_; ++ goto asoc_class2_error; ++ } ++ ++ capab_info = RTW_GET_LE16(pframe + WLAN_HDR_A3_LEN); ++ //capab_info = le16_to_cpu(*(unsigned short *)(pframe + WLAN_HDR_A3_LEN)); ++ //listen_interval = le16_to_cpu(*(unsigned short *)(pframe + WLAN_HDR_A3_LEN+2)); ++ listen_interval = RTW_GET_LE16(pframe + WLAN_HDR_A3_LEN+2); ++ ++ left = pkt_len - (IEEE80211_3ADDR_LEN + ie_offset); ++ pos = pframe + (IEEE80211_3ADDR_LEN + ie_offset); ++ ++ ++ DBG_871X("%s\n", __FUNCTION__); ++ ++ // check if this stat has been successfully authenticated/assocated ++ if (!((pstat->state) & WIFI_FW_AUTH_SUCCESS)) ++ { ++ if (!((pstat->state) & WIFI_FW_ASSOC_SUCCESS)) ++ { ++ status = _RSON_CLS2_; ++ goto asoc_class2_error; ++ } ++ else ++ { ++ pstat->state &= (~WIFI_FW_ASSOC_SUCCESS); ++ pstat->state |= WIFI_FW_ASSOC_STATE; ++ } ++ } ++ else ++ { ++ pstat->state &= (~WIFI_FW_AUTH_SUCCESS); ++ pstat->state |= WIFI_FW_ASSOC_STATE; ++ } ++ ++ ++#if 0// todo:tkip_countermeasures ++ if (hapd->tkip_countermeasures) { ++ resp = WLAN_REASON_MICHAEL_MIC_FAILURE; ++ goto fail; ++ } ++#endif ++ ++ pstat->capability = capab_info; ++ ++#if 0//todo: ++ //check listen_interval ++ if (listen_interval > hapd->conf->max_listen_interval) { ++ hostapd_logger(hapd, mgmt->sa, HOSTAPD_MODULE_IEEE80211, ++ HOSTAPD_LEVEL_DEBUG, ++ "Too large Listen Interval (%d)", ++ listen_interval); ++ resp = WLAN_STATUS_ASSOC_DENIED_LISTEN_INT_TOO_LARGE; ++ goto fail; ++ } ++ ++ pstat->listen_interval = listen_interval; ++#endif ++ ++ //now parse all ieee802_11 ie to point to elems ++ if (rtw_ieee802_11_parse_elems(pos, left, &elems, 1) == ParseFailed || ++ !elems.ssid) { ++ DBG_871X("STA " MAC_FMT " sent invalid association request\n", ++ MAC_ARG(pstat->hwaddr)); ++ status = _STATS_FAILURE_; ++ goto OnAssocReqFail; ++ } ++ ++ ++ // now we should check all the fields... ++ // checking SSID ++ p = rtw_get_ie(pframe + WLAN_HDR_A3_LEN + ie_offset, _SSID_IE_, &ie_len, ++ pkt_len - WLAN_HDR_A3_LEN - ie_offset); ++ if (p == NULL) ++ { ++ status = _STATS_FAILURE_; ++ } ++ ++ if (ie_len == 0) // broadcast ssid, however it is not allowed in assocreq ++ status = _STATS_FAILURE_; ++ else ++ { ++ // check if ssid match ++ if (!_rtw_memcmp((void *)(p+2), cur->Ssid.Ssid, cur->Ssid.SsidLength)) ++ status = _STATS_FAILURE_; ++ ++ if (ie_len != cur->Ssid.SsidLength) ++ status = _STATS_FAILURE_; ++ } ++ ++ if(_STATS_SUCCESSFUL_ != status) ++ goto OnAssocReqFail; ++ ++ // check if the supported rate is ok ++ p = rtw_get_ie(pframe + WLAN_HDR_A3_LEN + ie_offset, _SUPPORTEDRATES_IE_, &ie_len, pkt_len - WLAN_HDR_A3_LEN - ie_offset); ++ if (p == NULL) { ++ DBG_871X("Rx a sta assoc-req which supported rate is empty!\n"); ++ // use our own rate set as statoin used ++ //_rtw_memcpy(supportRate, AP_BSSRATE, AP_BSSRATE_LEN); ++ //supportRateNum = AP_BSSRATE_LEN; ++ ++ status = _STATS_FAILURE_; ++ goto OnAssocReqFail; ++ } ++ else { ++ _rtw_memcpy(supportRate, p+2, ie_len); ++ supportRateNum = ie_len; ++ ++ p = rtw_get_ie(pframe + WLAN_HDR_A3_LEN + ie_offset, _EXT_SUPPORTEDRATES_IE_ , &ie_len, ++ pkt_len - WLAN_HDR_A3_LEN - ie_offset); ++ if (p != NULL) { ++ ++ if(supportRateNum<=sizeof(supportRate)) ++ { ++ _rtw_memcpy(supportRate+supportRateNum, p+2, ie_len); ++ supportRateNum += ie_len; ++ } ++ } ++ } ++ ++ //todo: mask supportRate between AP & STA -> move to update raid ++ //get_matched_rate(pmlmeext, supportRate, &supportRateNum, 0); ++ ++ //update station supportRate ++ pstat->bssratelen = supportRateNum; ++ _rtw_memcpy(pstat->bssrateset, supportRate, supportRateNum); ++ ++ ++ //check RSN/WPA/WPS ++ pstat->dot8021xalg = 0; ++ pstat->wpa_psk = 0; ++ pstat->wpa_group_cipher = 0; ++ pstat->wpa2_group_cipher = 0; ++ pstat->wpa_pairwise_cipher = 0; ++ pstat->wpa2_pairwise_cipher = 0; ++ _rtw_memset(pstat->wpa_ie, 0, sizeof(pstat->wpa_ie)); ++ if((psecuritypriv->wpa_psk & BIT(1)) && elems.rsn_ie) { ++ ++ int group_cipher=0, pairwise_cipher=0; ++ ++ wpa_ie = elems.rsn_ie; ++ wpa_ie_len = elems.rsn_ie_len; ++ ++ if(rtw_parse_wpa2_ie(wpa_ie-2, wpa_ie_len+2, &group_cipher, &pairwise_cipher) == _SUCCESS) ++ { ++ pstat->dot8021xalg = 1;//psk, todo:802.1x ++ pstat->wpa_psk |= BIT(1); ++ ++ pstat->wpa2_group_cipher = group_cipher&psecuritypriv->wpa2_group_cipher; ++ pstat->wpa2_pairwise_cipher = pairwise_cipher&psecuritypriv->wpa2_pairwise_cipher; ++ ++ if(!pstat->wpa2_group_cipher) ++ status = WLAN_STATUS_GROUP_CIPHER_NOT_VALID; ++ ++ if(!pstat->wpa2_pairwise_cipher) ++ status = WLAN_STATUS_PAIRWISE_CIPHER_NOT_VALID; ++ } ++ else ++ { ++ status = WLAN_STATUS_INVALID_IE; ++ } ++ ++ } else if ((psecuritypriv->wpa_psk & BIT(0)) && elems.wpa_ie) { ++ ++ int group_cipher=0, pairwise_cipher=0; ++ ++ wpa_ie = elems.wpa_ie; ++ wpa_ie_len = elems.wpa_ie_len; ++ ++ if(rtw_parse_wpa_ie(wpa_ie-2, wpa_ie_len+2, &group_cipher, &pairwise_cipher) == _SUCCESS) ++ { ++ pstat->dot8021xalg = 1;//psk, todo:802.1x ++ pstat->wpa_psk |= BIT(0); ++ ++ pstat->wpa_group_cipher = group_cipher&psecuritypriv->wpa_group_cipher; ++ pstat->wpa_pairwise_cipher = pairwise_cipher&psecuritypriv->wpa_pairwise_cipher; ++ ++ if(!pstat->wpa_group_cipher) ++ status = WLAN_STATUS_GROUP_CIPHER_NOT_VALID; ++ ++ if(!pstat->wpa_pairwise_cipher) ++ status = WLAN_STATUS_PAIRWISE_CIPHER_NOT_VALID; ++ ++ } ++ else ++ { ++ status = WLAN_STATUS_INVALID_IE; ++ } ++ ++ } else { ++ wpa_ie = NULL; ++ wpa_ie_len = 0; ++ } ++ ++ if(_STATS_SUCCESSFUL_ != status) ++ goto OnAssocReqFail; ++ ++ pstat->flags &= ~(WLAN_STA_WPS | WLAN_STA_MAYBE_WPS); ++ //if (hapd->conf->wps_state && wpa_ie == NULL) { //todo: to check ap if supporting WPS ++ if(wpa_ie == NULL) { ++ if (elems.wps_ie) { ++ DBG_871X("STA included WPS IE in " ++ "(Re)Association Request - assume WPS is " ++ "used\n"); ++ pstat->flags |= WLAN_STA_WPS; ++ //wpabuf_free(sta->wps_ie); ++ //sta->wps_ie = wpabuf_alloc_copy(elems.wps_ie + 4, ++ // elems.wps_ie_len - 4); ++ } else { ++ DBG_871X("STA did not include WPA/RSN IE " ++ "in (Re)Association Request - possible WPS " ++ "use\n"); ++ pstat->flags |= WLAN_STA_MAYBE_WPS; ++ } ++ ++ ++ // AP support WPA/RSN, and sta is going to do WPS, but AP is not ready ++ // that the selected registrar of AP is _FLASE ++ if((psecuritypriv->wpa_psk >0) ++ && (pstat->flags & (WLAN_STA_WPS|WLAN_STA_MAYBE_WPS))) ++ { ++ if(pmlmepriv->wps_beacon_ie) ++ { ++ u8 selected_registrar = 0; ++ ++ rtw_get_wps_attr_content(pmlmepriv->wps_beacon_ie, pmlmepriv->wps_beacon_ie_len, WPA_ATTR_SELECTED_REGISTRAR , &selected_registrar, NULL); ++ ++ if(!selected_registrar) ++ { ++ DBG_871X("selected_registrar is _FALSE , or AP is not ready to do WPS\n"); ++ ++ status = _STATS_UNABLE_HANDLE_STA_; ++ ++ goto OnAssocReqFail; ++ } ++ } ++ } ++ ++ } ++ else ++ { ++ int copy_len; ++ ++ if(psecuritypriv->wpa_psk == 0) ++ { ++ DBG_871X("STA " MAC_FMT ": WPA/RSN IE in association " ++ "request, but AP don't support WPA/RSN\n", MAC_ARG(pstat->hwaddr)); ++ ++ status = WLAN_STATUS_INVALID_IE; ++ ++ goto OnAssocReqFail; ++ ++ } ++ ++ if (elems.wps_ie) { ++ DBG_871X("STA included WPS IE in " ++ "(Re)Association Request - WPS is " ++ "used\n"); ++ pstat->flags |= WLAN_STA_WPS; ++ copy_len=0; ++ } ++ else ++ { ++ copy_len = ((wpa_ie_len+2) > sizeof(pstat->wpa_ie)) ? (sizeof(pstat->wpa_ie)):(wpa_ie_len+2); ++ } ++ ++ ++ if(copy_len>0) ++ _rtw_memcpy(pstat->wpa_ie, wpa_ie-2, copy_len); ++ ++ } ++ ++ ++ // check if there is WMM IE & support WWM-PS ++ pstat->flags &= ~WLAN_STA_WME; ++ pstat->qos_option = 0; ++ pstat->qos_info = 0; ++ pstat->has_legacy_ac = _TRUE; ++ pstat->uapsd_vo = 0; ++ pstat->uapsd_vi = 0; ++ pstat->uapsd_be = 0; ++ pstat->uapsd_bk = 0; ++ if (pmlmepriv->qospriv.qos_option) ++ { ++ p = pframe + WLAN_HDR_A3_LEN + ie_offset; ie_len = 0; ++ for (;;) ++ { ++ p = rtw_get_ie(p, _VENDOR_SPECIFIC_IE_, &ie_len, pkt_len - WLAN_HDR_A3_LEN - ie_offset); ++ if (p != NULL) { ++ if (_rtw_memcmp(p+2, WMM_IE, 6)) { ++ ++ pstat->flags |= WLAN_STA_WME; ++ ++ pstat->qos_option = 1; ++ pstat->qos_info = *(p+8); ++ ++ pstat->max_sp_len = (pstat->qos_info>>5)&0x3; ++ ++ if((pstat->qos_info&0xf) !=0xf) ++ pstat->has_legacy_ac = _TRUE; ++ else ++ pstat->has_legacy_ac = _FALSE; ++ ++ if(pstat->qos_info&0xf) ++ { ++ if(pstat->qos_info&BIT(0)) ++ pstat->uapsd_vo = BIT(0)|BIT(1); ++ else ++ pstat->uapsd_vo = 0; ++ ++ if(pstat->qos_info&BIT(1)) ++ pstat->uapsd_vi = BIT(0)|BIT(1); ++ else ++ pstat->uapsd_vi = 0; ++ ++ if(pstat->qos_info&BIT(2)) ++ pstat->uapsd_bk = BIT(0)|BIT(1); ++ else ++ pstat->uapsd_bk = 0; ++ ++ if(pstat->qos_info&BIT(3)) ++ pstat->uapsd_be = BIT(0)|BIT(1); ++ else ++ pstat->uapsd_be = 0; ++ ++ } ++ ++ break; ++ } ++ } ++ else { ++ break; ++ } ++ p = p + ie_len + 2; ++ } ++ } ++ ++ ++#ifdef CONFIG_80211N_HT ++ /* save HT capabilities in the sta object */ ++ _rtw_memset(&pstat->htpriv.ht_cap, 0, sizeof(struct rtw_ieee80211_ht_cap)); ++ if (elems.ht_capabilities && elems.ht_capabilities_len >= sizeof(struct rtw_ieee80211_ht_cap)) ++ { ++ pstat->flags |= WLAN_STA_HT; ++ ++ pstat->flags |= WLAN_STA_WME; ++ ++ _rtw_memcpy(&pstat->htpriv.ht_cap, elems.ht_capabilities, sizeof(struct rtw_ieee80211_ht_cap)); ++ ++ } else ++ pstat->flags &= ~WLAN_STA_HT; ++ ++ ++ if((pmlmepriv->htpriv.ht_option == _FALSE) && (pstat->flags&WLAN_STA_HT)) ++ { ++ status = _STATS_FAILURE_; ++ goto OnAssocReqFail; ++ } ++ ++ ++ if ((pstat->flags & WLAN_STA_HT) && ++ ((pstat->wpa2_pairwise_cipher&WPA_CIPHER_TKIP) || ++ (pstat->wpa_pairwise_cipher&WPA_CIPHER_TKIP))) ++ { ++ DBG_871X("HT: " MAC_FMT " tried to " ++ "use TKIP with HT association\n", MAC_ARG(pstat->hwaddr)); ++ ++ //status = WLAN_STATUS_CIPHER_REJECTED_PER_POLICY; ++ //goto OnAssocReqFail; ++ } ++#endif /* CONFIG_80211N_HT */ ++ ++ // ++ //if (hapd->iface->current_mode->mode == HOSTAPD_MODE_IEEE80211G)//? ++ pstat->flags |= WLAN_STA_NONERP; ++ for (i = 0; i < pstat->bssratelen; i++) { ++ if ((pstat->bssrateset[i] & 0x7f) > 22) { ++ pstat->flags &= ~WLAN_STA_NONERP; ++ break; ++ } ++ } ++ ++ if (pstat->capability & WLAN_CAPABILITY_SHORT_PREAMBLE) ++ pstat->flags |= WLAN_STA_SHORT_PREAMBLE; ++ else ++ pstat->flags &= ~WLAN_STA_SHORT_PREAMBLE; ++ ++ ++ ++ if (status != _STATS_SUCCESSFUL_) ++ goto OnAssocReqFail; ++ ++#ifdef CONFIG_P2P ++ pstat->is_p2p_device = _FALSE; ++ if(rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) ++ { ++ if( (p2pie=rtw_get_p2p_ie(pframe + WLAN_HDR_A3_LEN + ie_offset , pkt_len - WLAN_HDR_A3_LEN - ie_offset , NULL, &p2pielen))) ++ { ++ pstat->is_p2p_device = _TRUE; ++ if((p2p_status_code=(u8)process_assoc_req_p2p_ie(pwdinfo, pframe, pkt_len, pstat))>0) ++ { ++ pstat->p2p_status_code = p2p_status_code; ++ status = _STATS_CAP_FAIL_; ++ goto OnAssocReqFail; ++ } ++ } ++#ifdef CONFIG_WFD ++ if(rtw_get_wfd_ie(pframe + WLAN_HDR_A3_LEN + ie_offset , pkt_len - WLAN_HDR_A3_LEN - ie_offset , wfd_ie, &wfd_ielen )) ++ { ++ u8 attr_content[ 10 ] = { 0x00 }; ++ u32 attr_contentlen = 0; ++ ++ DBG_8192C( "[%s] WFD IE Found!!\n", __FUNCTION__ ); ++ rtw_get_wfd_attr_content( wfd_ie, wfd_ielen, WFD_ATTR_DEVICE_INFO, attr_content, &attr_contentlen); ++ if ( attr_contentlen ) ++ { ++ pwdinfo->wfd_info.peer_rtsp_ctrlport = RTW_GET_BE16( attr_content + 2 ); ++ DBG_8192C( "[%s] Peer PORT NUM = %d\n", __FUNCTION__, pwdinfo->wfd_info.peer_rtsp_ctrlport ); ++ } ++ } ++#endif ++ } ++ pstat->p2p_status_code = p2p_status_code; ++#endif //CONFIG_P2P ++ ++ //TODO: identify_proprietary_vendor_ie(); ++ // Realtek proprietary IE ++ // identify if this is Broadcom sta ++ // identify if this is ralink sta ++ // Customer proprietary IE ++ ++ ++ ++ /* get a unique AID */ ++ if (pstat->aid > 0) { ++ DBG_871X(" old AID %d\n", pstat->aid); ++ } else { ++ for (pstat->aid = 1; pstat->aid <= NUM_STA; pstat->aid++) ++ if (pstapriv->sta_aid[pstat->aid - 1] == NULL) ++ break; ++ ++ //if (pstat->aid > NUM_STA) { ++ if (pstat->aid > pstapriv->max_num_sta) { ++ ++ pstat->aid = 0; ++ ++ DBG_871X(" no room for more AIDs\n"); ++ ++ status = WLAN_STATUS_AP_UNABLE_TO_HANDLE_NEW_STA; ++ ++ goto OnAssocReqFail; ++ ++ ++ } else { ++ pstapriv->sta_aid[pstat->aid - 1] = pstat; ++ DBG_871X("allocate new AID = (%d)\n", pstat->aid); ++ } ++ } ++ ++ ++ pstat->state &= (~WIFI_FW_ASSOC_STATE); ++ pstat->state |= WIFI_FW_ASSOC_SUCCESS; ++ ++ _enter_critical_bh(&pstapriv->auth_list_lock, &irqL); ++ if (!rtw_is_list_empty(&pstat->auth_list)) ++ { ++ rtw_list_delete(&pstat->auth_list); ++ } ++ _exit_critical_bh(&pstapriv->auth_list_lock, &irqL); ++ ++ _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL); ++ if (rtw_is_list_empty(&pstat->asoc_list)) ++ { ++ pstat->expire_to = pstapriv->expire_to; ++ rtw_list_insert_tail(&pstat->asoc_list, &pstapriv->asoc_list); ++ } ++ _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL); ++ ++ // now the station is qualified to join our BSS... ++ if(pstat && (pstat->state & WIFI_FW_ASSOC_SUCCESS) && (_STATS_SUCCESSFUL_==status)) ++ { ++#ifdef CONFIG_NATIVEAP_MLME ++ //.1 bss_cap_update & sta_info_update ++ bss_cap_update(padapter, pstat); ++ sta_info_update(padapter, pstat); ++ ++ //.2 - report to upper layer ++ DBG_871X("indicate_sta_join_event to upper layer - hostapd\n"); ++ { ++#ifdef CONFIG_IOCTL_CFG80211 ++ struct wireless_dev *pwdev = padapter->rtw_wdev; ++ ++ if(pwdev->iftype == NL80211_IFTYPE_AP) ++ { ++ #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) && !defined(CONFIG_CFG80211_FORCE_COMPATIBLE_2_6_37_UNDER) ++ rtw_cfg80211_indicate_sta_assoc(padapter, pframe, pkt_len); ++ #else //(LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) && !defined(CONFIG_CFG80211_FORCE_COMPATIBLE_2_6_37_UNDER) ++ _enter_critical_bh(&pstat->lock, &irqL); ++ if(pstat->passoc_req) ++ { ++ rtw_mfree(pstat->passoc_req, pstat->assoc_req_len); ++ pstat->passoc_req = NULL; ++ pstat->assoc_req_len = 0; ++ } ++ ++ pstat->passoc_req = rtw_zmalloc(pkt_len); ++ if(pstat->passoc_req) ++ { ++ _rtw_memcpy(pstat->passoc_req, pframe, pkt_len); ++ pstat->assoc_req_len = pkt_len; ++ } ++ _exit_critical_bh(&pstat->lock, &irqL); ++ #endif //(LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) && !defined(CONFIG_CFG80211_FORCE_COMPATIBLE_2_6_37_UNDER) ++ } ++ else ++#endif //CONFIG_IOCTL_CFG80211 ++ { ++ rtw_indicate_sta_assoc_event(padapter, pstat); ++ } ++ ++ } ++ ++ ++ //.3-(1) report sta add event ++ report_add_sta_event(padapter, pstat->hwaddr, pstat->aid); ++ ++ if (frame_type == WIFI_ASSOCREQ) ++ issue_asocrsp(padapter, status, pstat, WIFI_ASSOCRSP); ++ else ++ issue_asocrsp(padapter, status, pstat, WIFI_REASSOCRSP); ++ ++#endif ++ } ++ ++ return _SUCCESS; ++ ++asoc_class2_error: ++ ++#ifdef CONFIG_NATIVEAP_MLME ++ issue_deauth(padapter, (void *)GetAddr2Ptr(pframe), status); ++#endif ++ ++ return _FAIL; ++ ++OnAssocReqFail: ++ ++ ++#ifdef CONFIG_NATIVEAP_MLME ++ pstat->aid = 0; ++ if (frame_type == WIFI_ASSOCREQ) ++ issue_asocrsp(padapter, status, pstat, WIFI_ASSOCRSP); ++ else ++ issue_asocrsp(padapter, status, pstat, WIFI_REASSOCRSP); ++#endif ++ ++ ++#endif /* CONFIG_AP_MODE */ ++ ++ return _FAIL; ++ ++} ++ ++unsigned int OnAssocRsp(_adapter *padapter, union recv_frame *precv_frame) ++{ ++ uint i; ++ int res; ++ unsigned short status; ++ PNDIS_802_11_VARIABLE_IEs pIE; ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ //WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network); ++ u8 *pframe = precv_frame->u.hdr.rx_data; ++ uint pkt_len = precv_frame->u.hdr.len; ++ ++ DBG_871X("%s\n", __FUNCTION__); ++ ++ //check A1 matches or not ++ if (!_rtw_memcmp(myid(&(padapter->eeprompriv)), get_da(pframe), ETH_ALEN)) ++ return _SUCCESS; ++ ++ if (!(pmlmeinfo->state & (WIFI_FW_AUTH_SUCCESS | WIFI_FW_ASSOC_STATE))) ++ return _SUCCESS; ++ ++ if (pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS) ++ return _SUCCESS; ++ ++ _cancel_timer_ex(&pmlmeext->link_timer); ++ ++ //status ++ if ((status = le16_to_cpu(*(unsigned short *)(pframe + WLAN_HDR_A3_LEN + 2))) > 0) ++ { ++ DBG_871X("assoc reject, status code: %d\n", status); ++ pmlmeinfo->state = WIFI_FW_NULL_STATE; ++ res = -4; ++ goto report_assoc_result; ++ } ++ ++ //get capabilities ++ pmlmeinfo->capability = le16_to_cpu(*(unsigned short *)(pframe + WLAN_HDR_A3_LEN)); ++ ++ //set slot time ++ pmlmeinfo->slotTime = (pmlmeinfo->capability & BIT(10))? 9: 20; ++ ++ //AID ++ res = pmlmeinfo->aid = (int)(le16_to_cpu(*(unsigned short *)(pframe + WLAN_HDR_A3_LEN + 4))&0x3fff); ++ ++ //following are moved to join event callback function ++ //to handle HT, WMM, rate adaptive, update MAC reg ++ //for not to handle the synchronous IO in the tasklet ++ for (i = (6 + WLAN_HDR_A3_LEN); i < pkt_len;) ++ { ++ pIE = (PNDIS_802_11_VARIABLE_IEs)(pframe + i); ++ ++ switch (pIE->ElementID) ++ { ++ case _VENDOR_SPECIFIC_IE_: ++ if (_rtw_memcmp(pIE->data, WMM_PARA_OUI, 6)) //WMM ++ { ++ WMM_param_handler(padapter, pIE); ++ } ++#ifdef CONFIG_WFD ++ else if ( _rtw_memcmp(pIE->data, WFD_OUI, 4)) //WFD ++ { ++ printk( "[%s] Found WFD IE\n", __FUNCTION__ ); ++ WFD_info_handler( padapter, pIE ); ++ } ++#endif ++ break; ++ ++ case _HT_CAPABILITY_IE_: //HT caps ++ HT_caps_handler(padapter, pIE); ++ break; ++ ++ case _HT_EXTRA_INFO_IE_: //HT info ++ HT_info_handler(padapter, pIE); ++ break; ++ ++ case _ERPINFO_IE_: ++ ERP_IE_handler(padapter, pIE); ++ ++ default: ++ break; ++ } ++ ++ i += (pIE->Length + 2); ++ } ++ ++ pmlmeinfo->state &= (~WIFI_FW_ASSOC_STATE); ++ pmlmeinfo->state |= WIFI_FW_ASSOC_SUCCESS; ++ ++ //Update Basic Rate Table for spec, 2010-12-28 , by thomas ++ UpdateBrateTbl(padapter, pmlmeinfo->network.SupportedRates); ++ ++report_assoc_result: ++ ++ report_join_res(padapter, res); ++ ++ return _SUCCESS; ++} ++ ++unsigned int OnDeAuth(_adapter *padapter, union recv_frame *precv_frame) ++{ ++ unsigned short reason; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ u8 *pframe = precv_frame->u.hdr.rx_data; ++ ++ //check A3 ++ if (!(_rtw_memcmp(GetAddr3Ptr(pframe), get_my_bssid(&pmlmeinfo->network), ETH_ALEN))) ++ return _SUCCESS; ++ ++ reason = le16_to_cpu(*(unsigned short *)(pframe + WLAN_HDR_A3_LEN)); ++ ++ DBG_871X("%s Reason code(%d)\n", __FUNCTION__,reason); ++ ++#ifdef CONFIG_AP_MODE ++ if(check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) ++ { ++ _irqL irqL; ++ struct sta_info *psta; ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ ++ //_enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL); ++ //rtw_free_stainfo(padapter, psta); ++ //_exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL); ++ ++ DBG_871X("%s, STA:" MAC_FMT "\n", __FUNCTION__, MAC_ARG(GetAddr2Ptr(pframe))); ++ ++ psta = rtw_get_stainfo(pstapriv, GetAddr2Ptr(pframe)); ++ if(psta) ++ { ++ _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL); ++ if(rtw_is_list_empty(&psta->asoc_list)==_FALSE) ++ { ++ rtw_list_delete(&psta->asoc_list); ++ ap_free_sta(padapter, psta); ++ } ++ _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL); ++ } ++ ++ return _SUCCESS; ++ } ++ else ++#endif ++ { ++ DBG_871X("%s, STA:" MAC_FMT "\n", __FUNCTION__, MAC_ARG(GetAddr3Ptr(pframe))); ++ ++ receive_disconnect(padapter, GetAddr3Ptr(pframe) ,reason); ++ } ++ pmlmepriv->LinkDetectInfo.bBusyTraffic = _FALSE; ++ return _SUCCESS; ++ ++} ++ ++unsigned int OnDisassoc(_adapter *padapter, union recv_frame *precv_frame) ++{ ++ unsigned short reason; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ u8 *pframe = precv_frame->u.hdr.rx_data; ++ ++ //check A3 ++ if (!(_rtw_memcmp(GetAddr3Ptr(pframe), get_my_bssid(&pmlmeinfo->network), ETH_ALEN))) ++ return _SUCCESS; ++ ++ reason = le16_to_cpu(*(unsigned short *)(pframe + WLAN_HDR_A3_LEN)); ++ ++ DBG_871X("%s Reason code(%d)\n", __FUNCTION__,reason); ++ ++#ifdef CONFIG_AP_MODE ++ if(check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) ++ { ++ _irqL irqL; ++ struct sta_info *psta; ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ ++ //_enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL); ++ //rtw_free_stainfo(padapter, psta); ++ //_exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL); ++ ++ DBG_871X("%s, STA:" MAC_FMT "\n", __FUNCTION__, MAC_ARG(GetAddr2Ptr(pframe))); ++ ++ psta = rtw_get_stainfo(pstapriv, GetAddr2Ptr(pframe)); ++ if(psta) ++ { ++ _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL); ++ if(rtw_is_list_empty(&psta->asoc_list)==_FALSE) ++ { ++ rtw_list_delete(&psta->asoc_list); ++ ap_free_sta(padapter, psta); ++ ++ } ++ _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL); ++ } ++ ++ return _SUCCESS; ++ } ++ else ++#endif ++ { ++ DBG_871X("%s, STA:" MAC_FMT "\n", __FUNCTION__, MAC_ARG(GetAddr3Ptr(pframe))); ++ ++ receive_disconnect(padapter, GetAddr3Ptr(pframe), reason); ++ } ++ pmlmepriv->LinkDetectInfo.bBusyTraffic = _FALSE; ++ return _SUCCESS; ++ ++} ++ ++unsigned int OnAtim(_adapter *padapter, union recv_frame *precv_frame) ++{ ++ DBG_871X("%s\n", __FUNCTION__); ++ return _SUCCESS; ++} ++ ++unsigned int OnAction_qos(_adapter *padapter, union recv_frame *precv_frame) ++{ ++ return _SUCCESS; ++} ++ ++unsigned int OnAction_dls(_adapter *padapter, union recv_frame *precv_frame) ++{ ++ return _SUCCESS; ++} ++ ++unsigned int OnAction_back(_adapter *padapter, union recv_frame *precv_frame) ++{ ++ u8 *addr; ++ struct sta_info *psta=NULL; ++ struct recv_reorder_ctrl *preorder_ctrl; ++ unsigned char *frame_body; ++ unsigned char category, action; ++ unsigned short tid, status, reason_code = 0; ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ u8 *pframe = precv_frame->u.hdr.rx_data; ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ ++ uint len = precv_frame->u.hdr.len; ++ ++ //check RA matches or not ++ if (!_rtw_memcmp(myid(&(padapter->eeprompriv)), GetAddr1Ptr(pframe), ETH_ALEN))//for if1, sta/ap mode ++ return _SUCCESS; ++ ++/* ++ //check A1 matches or not ++ if (!_rtw_memcmp(myid(&(padapter->eeprompriv)), get_da(pframe), ETH_ALEN)) ++ return _SUCCESS; ++*/ ++ DBG_871X("%s\n", __FUNCTION__); ++ ++ if((pmlmeinfo->state&0x03) != WIFI_FW_AP_STATE) ++ if (!(pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS)) ++ return _SUCCESS; ++ ++ addr = GetAddr2Ptr(pframe); ++ psta = rtw_get_stainfo(pstapriv, addr); ++ ++ if(psta==NULL) ++ return _SUCCESS; ++ ++ frame_body = (unsigned char *)(pframe + sizeof(struct rtw_ieee80211_hdr_3addr)); ++ ++ category = frame_body[0]; ++ if (category == RTW_WLAN_CATEGORY_BACK)// representing Block Ack ++ { ++ if (!pmlmeinfo->HT_enable) ++ { ++ return _SUCCESS; ++ } ++ ++ action = frame_body[1]; ++ DBG_871X("%s, action=%d\n", __FUNCTION__, action); ++ switch (action) ++ { ++ case RTW_WLAN_ACTION_ADDBA_REQ: //ADDBA request ++ ++ _rtw_memcpy(&(pmlmeinfo->ADDBA_req), &(frame_body[2]), sizeof(struct ADDBA_request)); ++ //process_addba_req(padapter, (u8*)&(pmlmeinfo->ADDBA_req), GetAddr3Ptr(pframe)); ++ process_addba_req(padapter, (u8*)&(pmlmeinfo->ADDBA_req), addr); ++ ++ if(pmlmeinfo->bAcceptAddbaReq == _TRUE) ++ { ++ issue_action_BA(padapter, addr, RTW_WLAN_ACTION_ADDBA_RESP, 0); ++ } ++ else ++ { ++ issue_action_BA(padapter, addr, RTW_WLAN_ACTION_ADDBA_RESP, 37);//reject ADDBA Req ++ } ++ ++ break; ++ ++ case RTW_WLAN_ACTION_ADDBA_RESP: //ADDBA response ++ ++ //status = frame_body[3] | (frame_body[4] << 8); //endian issue ++ status = RTW_GET_LE16(&frame_body[3]); ++ tid = ((frame_body[5] >> 2) & 0x7); ++ ++ if (status == 0) ++ { //successful ++ DBG_871X("agg_enable for TID=%d\n", tid); ++ psta->htpriv.agg_enable_bitmap |= 1 << tid; ++ psta->htpriv.candidate_tid_bitmap &= ~BIT(tid); ++ } ++ else ++ { ++ psta->htpriv.agg_enable_bitmap &= ~BIT(tid); ++ } ++ ++ //DBG_8192C("marc: ADDBA RSP: %x\n", pmlmeinfo->agg_enable_bitmap); ++ break; ++ ++ case RTW_WLAN_ACTION_DELBA: //DELBA ++ if ((frame_body[3] & BIT(3)) == 0) ++ { ++ psta->htpriv.agg_enable_bitmap &= ~(1 << ((frame_body[3] >> 4) & 0xf)); ++ psta->htpriv.candidate_tid_bitmap &= ~(1 << ((frame_body[3] >> 4) & 0xf)); ++ ++ //reason_code = frame_body[4] | (frame_body[5] << 8); ++ reason_code = RTW_GET_LE16(&frame_body[4]); ++ } ++ else if((frame_body[3] & BIT(3)) == BIT(3)) ++ { ++ tid = (frame_body[3] >> 4) & 0x0F; ++ ++ preorder_ctrl = &psta->recvreorder_ctrl[tid]; ++ preorder_ctrl->enable = _FALSE; ++ preorder_ctrl->indicate_seq = 0xffff; ++ #ifdef DBG_RX_SEQ ++ DBG_871X("DBG_RX_SEQ %s:%d indicate_seq:%u \n", __FUNCTION__, __LINE__, ++ preorder_ctrl->indicate_seq); ++ #endif ++ } ++ ++ DBG_8192C("%s(): DELBA: %x(%x)\n", __FUNCTION__,pmlmeinfo->agg_enable_bitmap, reason_code); ++ //todo: how to notify the host while receiving DELETE BA ++ break; ++ ++ default: ++ break; ++ } ++ } ++ ++ return _SUCCESS; ++} ++ ++#ifdef CONFIG_P2P ++void issue_p2p_GO_request(_adapter *padapter, u8* raddr) ++{ ++ ++ unsigned char category = RTW_WLAN_CATEGORY_PUBLIC; ++ u8 action = P2P_PUB_ACTION_ACTION; ++ u32 p2poui = cpu_to_be32(P2POUI); ++ u8 oui_subtype = P2P_GO_NEGO_REQ; ++ u8 wpsie[ 255 ] = { 0x00 }, p2pie[ 255 ] = { 0x00 }; ++ u8 wpsielen = 0, p2pielen = 0, i; ++ u16 chnum = 0; ++#ifdef CONFIG_WFD ++ u32 wfdielen = 0; ++#endif //CONFIG_WFD ++ ++ struct xmit_frame *pmgntframe; ++ struct pkt_attrib *pattrib; ++ unsigned char *pframe; ++ struct rtw_ieee80211_hdr *pwlanhdr; ++ unsigned short *fctrl; ++ struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); ++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ struct wifidirect_info *pwdinfo = &( padapter->wdinfo); ++ ++ ++ if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL) ++ { ++ return; ++ } ++ ++ DBG_8192C( "[%s] In\n", __FUNCTION__ ); ++ //update attribute ++ pattrib = &pmgntframe->attrib; ++ update_mgntframe_attrib(padapter, pattrib); ++ ++ _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); ++ ++ pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; ++ pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; ++ ++ fctrl = &(pwlanhdr->frame_ctl); ++ *(fctrl) = 0; ++ ++ _rtw_memcpy(pwlanhdr->addr1, raddr, ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr2, myid(&(padapter->eeprompriv)), ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr3, myid(&(padapter->eeprompriv)), ETH_ALEN); ++ ++ SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); ++ pmlmeext->mgnt_seq++; ++ SetFrameSubType(pframe, WIFI_ACTION); ++ ++ pframe += sizeof(struct rtw_ieee80211_hdr_3addr); ++ pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); ++ ++ pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen)); ++ pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen)); ++ pframe = rtw_set_fixed_ie(pframe, 4, (unsigned char *) &(p2poui), &(pattrib->pktlen)); ++ pframe = rtw_set_fixed_ie(pframe, 1, &(oui_subtype), &(pattrib->pktlen)); ++ pwdinfo->negotiation_dialog_token = 1; // Initialize the dialog value ++ pframe = rtw_set_fixed_ie(pframe, 1, &pwdinfo->negotiation_dialog_token, &(pattrib->pktlen)); ++ ++ ++ ++ // WPS Section ++ wpsielen = 0; ++ // WPS OUI ++ *(u32*) ( wpsie ) = cpu_to_be32( WPSOUI ); ++ wpsielen += 4; ++ ++ // WPS version ++ // Type: ++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_ATTR_VER1 ); ++ wpsielen += 2; ++ ++ // Length: ++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( 0x0001 ); ++ wpsielen += 2; ++ ++ // Value: ++ wpsie[wpsielen++] = WPS_VERSION_1; // Version 1.0 ++ ++ // Device Password ID ++ // Type: ++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_ATTR_DEVICE_PWID ); ++ wpsielen += 2; ++ ++ // Length: ++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( 0x0002 ); ++ wpsielen += 2; ++ ++ // Value: ++ ++ if ( pwdinfo->ui_got_wps_info == P2P_GOT_WPSINFO_PEER_DISPLAY_PIN ) ++ { ++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_DPID_USER_SPEC ); ++ } ++ else if ( pwdinfo->ui_got_wps_info == P2P_GOT_WPSINFO_SELF_DISPLAY_PIN ) ++ { ++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_DPID_REGISTRAR_SPEC ); ++ } ++ else if ( pwdinfo->ui_got_wps_info == P2P_GOT_WPSINFO_PBC ) ++ { ++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_DPID_PBC ); ++ } ++ ++ wpsielen += 2; ++ ++ pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, wpsielen, (unsigned char *) wpsie, &pattrib->pktlen ); ++ ++ ++ // P2P IE Section. ++ ++ // P2P OUI ++ p2pielen = 0; ++ p2pie[ p2pielen++ ] = 0x50; ++ p2pie[ p2pielen++ ] = 0x6F; ++ p2pie[ p2pielen++ ] = 0x9A; ++ p2pie[ p2pielen++ ] = 0x09; // WFA P2P v1.0 ++ ++ // Commented by Albert 20110306 ++ // According to the P2P Specification, the group negoitation request frame should contain 9 P2P attributes ++ // 1. P2P Capability ++ // 2. Group Owner Intent ++ // 3. Configuration Timeout ++ // 4. Listen Channel ++ // 5. Extended Listen Timing ++ // 6. Intended P2P Interface Address ++ // 7. Channel List ++ // 8. P2P Device Info ++ // 9. Operating Channel ++ ++ ++ // P2P Capability ++ // Type: ++ p2pie[ p2pielen++ ] = P2P_ATTR_CAPABILITY; ++ ++ // Length: ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0002 ); ++ p2pielen += 2; ++ ++ // Value: ++ // Device Capability Bitmap, 1 byte ++ // Be able to participate in additional P2P Groups and ++ // support the P2P Invitation Procedure ++ p2pie[ p2pielen++ ] = P2P_DEVCAP_INVITATION_PROC; ++ ++ // Group Capability Bitmap, 1 byte ++ p2pie[ p2pielen++ ] = 0x00; ++ ++ // Group Owner Intent ++ // Type: ++ p2pie[ p2pielen++ ] = P2P_ATTR_GO_INTENT; ++ ++ // Length: ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0001 ); ++ p2pielen += 2; ++ ++ // Value: ++ // Todo the tie breaker bit. ++ p2pie[ p2pielen++ ] = ( ( pwdinfo->intent << 1 ) | BIT(0) ); ++ ++ // Configuration Timeout ++ // Type: ++ p2pie[ p2pielen++ ] = P2P_ATTR_CONF_TIMEOUT; ++ ++ // Length: ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0002 ); ++ p2pielen += 2; ++ ++ // Value: ++ p2pie[ p2pielen++ ] = 200; // 2 seconds needed to be the P2P GO ++ p2pie[ p2pielen++ ] = 200; // 2 seconds needed to be the P2P Client ++ ++ ++ // Listen Channel ++ // Type: ++ p2pie[ p2pielen++ ] = P2P_ATTR_LISTEN_CH; ++ ++ // Length: ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0005 ); ++ p2pielen += 2; ++ ++ // Value: ++ // Country String ++ p2pie[ p2pielen++ ] = 'U'; ++ p2pie[ p2pielen++ ] = 'S'; ++ ++ // The third byte should be set to 0x04. ++ // Described in the "Operating Channel Attribute" section. ++ p2pie[ p2pielen++ ] = 0x04; ++ ++ // Operating Class ++ p2pie[ p2pielen++ ] = 0x51; // Copy from SD7 ++ ++ // Channel Number ++ p2pie[ p2pielen++ ] = pwdinfo->listen_channel; // listening channel number ++ ++ ++ // Extended Listen Timing ATTR ++ // Type: ++ p2pie[ p2pielen++ ] = P2P_ATTR_EX_LISTEN_TIMING; ++ ++ // Length: ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0004 ); ++ p2pielen += 2; ++ ++ // Value: ++ // Availability Period ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0xFFFF ); ++ p2pielen += 2; ++ ++ // Availability Interval ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0xFFFF ); ++ p2pielen += 2; ++ ++ ++ // Intended P2P Interface Address ++ // Type: ++ p2pie[ p2pielen++ ] = P2P_ATTR_INTENTED_IF_ADDR; ++ ++ // Length: ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( ETH_ALEN ); ++ p2pielen += 2; ++ ++ // Value: ++ _rtw_memcpy( p2pie + p2pielen, myid( &padapter->eeprompriv ), ETH_ALEN ); ++ p2pielen += ETH_ALEN; ++ ++ ++ // Channel List ++ // Type: ++ p2pie[ p2pielen++ ] = P2P_ATTR_CH_LIST; ++ ++ // Length: ++ chnum = ( u16 ) pmlmeext->max_chan_nums; ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 5 + chnum ); ++ p2pielen += 2; ++ ++ // Value: ++ // Country String ++ p2pie[ p2pielen++ ] = 'U'; ++ p2pie[ p2pielen++ ] = 'S'; ++ ++ // The third byte should be set to 0x04. ++ // Described in the "Operating Channel Attribute" section. ++ p2pie[ p2pielen++ ] = 0x04; ++ ++ // Channel Entry List ++ // Operating Class ++ p2pie[ p2pielen++ ] = 0x51; // Copy from SD7 ++ ++ // Number of Channels ++ // Depends on the channel plan ++ p2pie[ p2pielen++ ] = pmlmeext->max_chan_nums; ++ ++ // Channel List ++ for( i = 0; i < pmlmeext->max_chan_nums; i++ ) ++ { ++ p2pie[ p2pielen++ ] = pmlmeext->channel_set[ i ].ChannelNum; ++ } ++ ++ // Device Info ++ // Type: ++ p2pie[ p2pielen++ ] = P2P_ATTR_DEVICE_INFO; ++ ++ // Length: ++ // 21 -> P2P Device Address (6bytes) + Config Methods (2bytes) + Primary Device Type (8bytes) ++ // + NumofSecondDevType (1byte) + WPS Device Name ID field (2bytes) + WPS Device Name Len field (2bytes) ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 21 + pwdinfo->device_name_len ); ++ p2pielen += 2; ++ ++ // Value: ++ // P2P Device Address ++ _rtw_memcpy( p2pie + p2pielen, myid( &padapter->eeprompriv ), ETH_ALEN ); ++ p2pielen += ETH_ALEN; ++ ++ // Config Method ++ // This field should be big endian. Noted by P2P specification. ++ ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( pwdinfo->supported_wps_cm ); ++ ++ p2pielen += 2; ++ ++ // Primary Device Type ++ // Category ID ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_PDT_CID_RTK_WIDI ); ++ p2pielen += 2; ++ ++ // OUI ++ *(u32*) ( p2pie + p2pielen ) = cpu_to_be32( WPSOUI ); ++ p2pielen += 4; ++ ++ // Sub Category ID ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_PDT_SCID_RTK_DMP ); ++ p2pielen += 2; ++ ++ // Number of Secondary Device Types ++ p2pie[ p2pielen++ ] = 0x00; // No Secondary Device Type List ++ ++ // Device Name ++ // Type: ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_ATTR_DEVICE_NAME ); ++ p2pielen += 2; ++ ++ // Length: ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( pwdinfo->device_name_len ); ++ p2pielen += 2; ++ ++ // Value: ++ _rtw_memcpy( p2pie + p2pielen, pwdinfo->device_name , pwdinfo->device_name_len ); ++ p2pielen += pwdinfo->device_name_len; ++ ++ ++ // Operating Channel ++ // Type: ++ p2pie[ p2pielen++ ] = P2P_ATTR_OPERATING_CH; ++ ++ // Length: ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0005 ); ++ p2pielen += 2; ++ ++ // Value: ++ // Country String ++ p2pie[ p2pielen++ ] = 'U'; ++ p2pie[ p2pielen++ ] = 'S'; ++ ++ // The third byte should be set to 0x04. ++ // Described in the "Operating Channel Attribute" section. ++ p2pie[ p2pielen++ ] = 0x04; ++ ++ // Operating Class ++ p2pie[ p2pielen++ ] = 0x51; // Copy from SD7 ++ ++ // Channel Number ++ p2pie[ p2pielen++ ] = pwdinfo->operating_channel; // operating channel number ++ ++ pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, p2pielen, (unsigned char *) p2pie, &pattrib->pktlen ); ++ ++#ifdef CONFIG_WFD ++ wfdielen = build_nego_req_wfd_ie(pwdinfo, pframe); ++ pframe += wfdielen; ++ pattrib->pktlen += wfdielen; ++#endif //CONFIG_WFD ++ ++ pattrib->last_txcmdsz = pattrib->pktlen; ++ ++ dump_mgntframe(padapter, pmgntframe); ++ ++ return; ++ ++} ++ ++ ++void issue_p2p_GO_response(_adapter *padapter, u8* raddr, u8* frame_body,uint len, u8 result) ++{ ++ ++ unsigned char category = RTW_WLAN_CATEGORY_PUBLIC; ++ u8 action = P2P_PUB_ACTION_ACTION; ++ u32 p2poui = cpu_to_be32(P2POUI); ++ u8 oui_subtype = P2P_GO_NEGO_RESP; ++ u8 wpsie[ 255 ] = { 0x00 }, p2pie[ 255 ] = { 0x00 }; ++ u8 p2pielen = 0, i; ++ uint wpsielen = 0; ++ u16 wps_devicepassword_id = 0x0000; ++ uint wps_devicepassword_id_len = 0; ++ u16 chnum = 0; ++#ifdef CONFIG_WFD ++ u32 wfdielen = 0; ++#endif //CONFIG_WFD ++ ++ struct xmit_frame *pmgntframe; ++ struct pkt_attrib *pattrib; ++ unsigned char *pframe; ++ struct rtw_ieee80211_hdr *pwlanhdr; ++ unsigned short *fctrl; ++ struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); ++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ struct wifidirect_info *pwdinfo = &( padapter->wdinfo); ++ ++ ++ if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL) ++ { ++ return; ++ } ++ ++ DBG_8192C( "[%s] In\n", __FUNCTION__ ); ++ //update attribute ++ pattrib = &pmgntframe->attrib; ++ update_mgntframe_attrib(padapter, pattrib); ++ ++ _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); ++ ++ pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; ++ pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; ++ ++ fctrl = &(pwlanhdr->frame_ctl); ++ *(fctrl) = 0; ++ ++ _rtw_memcpy(pwlanhdr->addr1, raddr, ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr2, myid(&(padapter->eeprompriv)), ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr3, myid(&(padapter->eeprompriv)), ETH_ALEN); ++ ++ SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); ++ pmlmeext->mgnt_seq++; ++ SetFrameSubType(pframe, WIFI_ACTION); ++ ++ pframe += sizeof(struct rtw_ieee80211_hdr_3addr); ++ pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); ++ ++ pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen)); ++ pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen)); ++ pframe = rtw_set_fixed_ie(pframe, 4, (unsigned char *) &(p2poui), &(pattrib->pktlen)); ++ pframe = rtw_set_fixed_ie(pframe, 1, &(oui_subtype), &(pattrib->pktlen)); ++ pwdinfo->negotiation_dialog_token = frame_body[7]; // The Dialog Token of provisioning discovery request frame. ++ pframe = rtw_set_fixed_ie(pframe, 1, &(pwdinfo->negotiation_dialog_token), &(pattrib->pktlen)); ++ ++ // Commented by Albert 20110328 ++ // Try to get the device password ID from the WPS IE of group negotiation request frame ++ // WiFi Direct test plan 5.1.15 ++ rtw_get_wps_ie( frame_body + _PUBLIC_ACTION_IE_OFFSET_, len - _PUBLIC_ACTION_IE_OFFSET_, wpsie, &wpsielen); ++ rtw_get_wps_attr_content( wpsie, wpsielen, WPS_ATTR_DEVICE_PWID, (u8*) &wps_devicepassword_id, &wps_devicepassword_id_len); ++ wps_devicepassword_id = be16_to_cpu( wps_devicepassword_id ); ++ ++ _rtw_memset( wpsie, 0x00, 255 ); ++ wpsielen = 0; ++ ++ // WPS Section ++ wpsielen = 0; ++ // WPS OUI ++ *(u32*) ( wpsie ) = cpu_to_be32( WPSOUI ); ++ wpsielen += 4; ++ ++ // WPS version ++ // Type: ++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_ATTR_VER1 ); ++ wpsielen += 2; ++ ++ // Length: ++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( 0x0001 ); ++ wpsielen += 2; ++ ++ // Value: ++ wpsie[wpsielen++] = WPS_VERSION_1; // Version 1.0 ++ ++ // Device Password ID ++ // Type: ++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_ATTR_DEVICE_PWID ); ++ wpsielen += 2; ++ ++ // Length: ++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( 0x0002 ); ++ wpsielen += 2; ++ ++ // Value: ++ if ( wps_devicepassword_id == WPS_DPID_USER_SPEC ) ++ { ++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_DPID_REGISTRAR_SPEC ); ++ } ++ else if ( wps_devicepassword_id == WPS_DPID_REGISTRAR_SPEC ) ++ { ++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_DPID_USER_SPEC ); ++ } ++ else ++ { ++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_DPID_PBC ); ++ } ++ wpsielen += 2; ++ ++ // Commented by Kurt 20120113 ++ // If some device wants to do p2p handshake without sending prov_disc_req ++ // We have to get peer_req_cm from here. ++ if(_rtw_memcmp( pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, "000", 3) ) ++ { ++ if ( wps_devicepassword_id == WPS_DPID_USER_SPEC ) ++ { ++ _rtw_memcpy( pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, "dis", 3 ); ++ } ++ else if ( wps_devicepassword_id == WPS_DPID_REGISTRAR_SPEC ) ++ { ++ _rtw_memcpy( pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, "pad", 3 ); ++ } ++ else ++ { ++ _rtw_memcpy( pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, "pbc", 3 ); ++ } ++ } ++ ++ pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, wpsielen, (unsigned char *) wpsie, &pattrib->pktlen ); ++ ++ ++ // P2P IE Section. ++ ++ // P2P OUI ++ p2pielen = 0; ++ p2pie[ p2pielen++ ] = 0x50; ++ p2pie[ p2pielen++ ] = 0x6F; ++ p2pie[ p2pielen++ ] = 0x9A; ++ p2pie[ p2pielen++ ] = 0x09; // WFA P2P v1.0 ++ ++ // Commented by Albert 20100908 ++ // According to the P2P Specification, the group negoitation response frame should contain 9 P2P attributes ++ // 1. Status ++ // 2. P2P Capability ++ // 3. Group Owner Intent ++ // 4. Configuration Timeout ++ // 5. Operating Channel ++ // 6. Intended P2P Interface Address ++ // 7. Channel List ++ // 8. Device Info ++ // 9. Group ID ( Only GO ) ++ ++ ++ // ToDo: ++ ++ // P2P Status ++ // Type: ++ p2pie[ p2pielen++ ] = P2P_ATTR_STATUS; ++ ++ // Length: ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0001 ); ++ p2pielen += 2; ++ ++ // Value: ++ p2pie[ p2pielen++ ] = result; ++ ++ // P2P Capability ++ // Type: ++ p2pie[ p2pielen++ ] = P2P_ATTR_CAPABILITY; ++ ++ // Length: ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0002 ); ++ p2pielen += 2; ++ ++ // Value: ++ // Device Capability Bitmap, 1 byte ++ ++ if ( rtw_p2p_chk_role(pwdinfo, P2P_ROLE_CLIENT) ) ++ { ++ // Commented by Albert 2011/03/08 ++ // According to the P2P specification ++ // if the sending device will be client, the P2P Capability should be reserved of group negotation response frame ++ p2pie[ p2pielen++ ] = 0; ++ } ++ else ++ { ++ // Be group owner or meet the error case ++ // Be able to participate in additional P2P Groups and ++ // support the P2P Invitation Procedure ++ p2pie[ p2pielen++ ] = P2P_DEVCAP_INVITATION_PROC; ++ } ++ ++ // Group Capability Bitmap, 1 byte ++ p2pie[ p2pielen++ ] = 0x00; ++ ++ // Group Owner Intent ++ // Type: ++ p2pie[ p2pielen++ ] = P2P_ATTR_GO_INTENT; ++ ++ // Length: ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0001 ); ++ p2pielen += 2; ++ ++ // Value: ++ if ( pwdinfo->peer_intent & 0x01 ) ++ { ++ // Peer's tie breaker bit is 1, our tie breaker bit should be 0 ++ p2pie[ p2pielen++ ] = ( pwdinfo->intent << 1 ); ++ } ++ else ++ { ++ // Peer's tie breaker bit is 0, our tie breaker bit should be 1 ++ p2pie[ p2pielen++ ] = ( ( pwdinfo->intent << 1 ) | BIT(0) ); ++ } ++ ++ ++ // Configuration Timeout ++ // Type: ++ p2pie[ p2pielen++ ] = P2P_ATTR_CONF_TIMEOUT; ++ ++ // Length: ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0002 ); ++ p2pielen += 2; ++ ++ // Value: ++ p2pie[ p2pielen++ ] = 200; // 2 seconds needed to be the P2P GO ++ p2pie[ p2pielen++ ] = 200; // 2 seconds needed to be the P2P Client ++ ++ // Operating Channel ++ // Type: ++ p2pie[ p2pielen++ ] = P2P_ATTR_OPERATING_CH; ++ ++ // Length: ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0005 ); ++ p2pielen += 2; ++ ++ // Value: ++ // Country String ++ p2pie[ p2pielen++ ] = 'U'; ++ p2pie[ p2pielen++ ] = 'S'; ++ ++ // The third byte should be set to 0x04. ++ // Described in the "Operating Channel Attribute" section. ++ p2pie[ p2pielen++ ] = 0x04; ++ ++ // Operating Class ++ p2pie[ p2pielen++ ] = 0x51; // Copy from SD7 ++ ++ // Channel Number ++ p2pie[ p2pielen++ ] = pwdinfo->operating_channel; // operating channel number ++ ++ // Intended P2P Interface Address ++ // Type: ++ p2pie[ p2pielen++ ] = P2P_ATTR_INTENTED_IF_ADDR; ++ ++ // Length: ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( ETH_ALEN ); ++ p2pielen += 2; ++ ++ // Value: ++ _rtw_memcpy( p2pie + p2pielen, myid( &padapter->eeprompriv ), ETH_ALEN ); ++ p2pielen += ETH_ALEN; ++ ++ // Channel List ++ // Type: ++ p2pie[ p2pielen++ ] = P2P_ATTR_CH_LIST; ++ ++ // Length: ++ chnum = ( u16 ) pmlmeext->max_chan_nums; ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 5 + chnum ); ++ p2pielen += 2; ++ ++ // Value: ++ // Country String ++ p2pie[ p2pielen++ ] = 'U'; ++ p2pie[ p2pielen++ ] = 'S'; ++ ++ // The third byte should be set to 0x04. ++ // Described in the "Operating Channel Attribute" section. ++ p2pie[ p2pielen++ ] = 0x04; ++ ++ // Channel Entry List ++ // Operating Class ++ p2pie[ p2pielen++ ] = 0x51; // Copy from SD7 ++ ++ // Number of Channels ++ // Depends on the channel plan ++ p2pie[ p2pielen++ ] = pmlmeext->max_chan_nums; ++ ++ // Channel List ++ for( i = 0; i < pmlmeext->max_chan_nums; i++ ) ++ { ++ p2pie[ p2pielen++ ] = pmlmeext->channel_set[ i ].ChannelNum; ++ } ++ ++ // Device Info ++ // Type: ++ p2pie[ p2pielen++ ] = P2P_ATTR_DEVICE_INFO; ++ ++ // Length: ++ // 21 -> P2P Device Address (6bytes) + Config Methods (2bytes) + Primary Device Type (8bytes) ++ // + NumofSecondDevType (1byte) + WPS Device Name ID field (2bytes) + WPS Device Name Len field (2bytes) ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 21 + pwdinfo->device_name_len ); ++ p2pielen += 2; ++ ++ // Value: ++ // P2P Device Address ++ _rtw_memcpy( p2pie + p2pielen, myid( &padapter->eeprompriv ), ETH_ALEN ); ++ p2pielen += ETH_ALEN; ++ ++ // Config Method ++ // This field should be big endian. Noted by P2P specification. ++ ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( pwdinfo->supported_wps_cm ); ++ ++ p2pielen += 2; ++ ++ // Primary Device Type ++ // Category ID ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_PDT_CID_RTK_WIDI ); ++ p2pielen += 2; ++ ++ // OUI ++ *(u32*) ( p2pie + p2pielen ) = cpu_to_be32( WPSOUI ); ++ p2pielen += 4; ++ ++ // Sub Category ID ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_PDT_SCID_RTK_DMP ); ++ p2pielen += 2; ++ ++ // Number of Secondary Device Types ++ p2pie[ p2pielen++ ] = 0x00; // No Secondary Device Type List ++ ++ // Device Name ++ // Type: ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_ATTR_DEVICE_NAME ); ++ p2pielen += 2; ++ ++ // Length: ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( pwdinfo->device_name_len ); ++ p2pielen += 2; ++ ++ // Value: ++ _rtw_memcpy( p2pie + p2pielen, pwdinfo->device_name , pwdinfo->device_name_len ); ++ p2pielen += pwdinfo->device_name_len; ++ ++ if ( rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO) ) ++ { ++ // Group ID Attribute ++ // Type: ++ p2pie[ p2pielen++ ] = P2P_ATTR_GROUP_ID; ++ ++ // Length: ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( ETH_ALEN + pwdinfo->nego_ssidlen ); ++ p2pielen += 2; ++ ++ // Value: ++ // p2P Device Address ++ _rtw_memcpy( p2pie + p2pielen , pwdinfo->device_addr, ETH_ALEN ); ++ p2pielen += ETH_ALEN; ++ ++ // SSID ++ _rtw_memcpy( p2pie + p2pielen, pwdinfo->nego_ssid, pwdinfo->nego_ssidlen ); ++ p2pielen += pwdinfo->nego_ssidlen; ++ ++ } ++ ++ pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, p2pielen, (unsigned char *) p2pie, &pattrib->pktlen ); ++ ++#ifdef CONFIG_WFD ++ wfdielen = build_nego_resp_wfd_ie(pwdinfo, pframe); ++ pframe += wfdielen; ++ pattrib->pktlen += wfdielen; ++#endif //CONFIG_WFD ++ ++ pattrib->last_txcmdsz = pattrib->pktlen; ++ ++ dump_mgntframe(padapter, pmgntframe); ++ ++ return; ++ ++} ++ ++void issue_p2p_GO_confirm(_adapter *padapter, u8* raddr, u8 result) ++{ ++ ++ unsigned char category = RTW_WLAN_CATEGORY_PUBLIC; ++ u8 action = P2P_PUB_ACTION_ACTION; ++ u32 p2poui = cpu_to_be32(P2POUI); ++ u8 oui_subtype = P2P_GO_NEGO_CONF; ++ u8 wpsie[ 255 ] = { 0x00 }, p2pie[ 255 ] = { 0x00 }; ++ u8 wpsielen = 0, p2pielen = 0; ++#ifdef CONFIG_WFD ++ u32 wfdielen = 0; ++#endif //CONFIG_WFD ++ ++ struct xmit_frame *pmgntframe; ++ struct pkt_attrib *pattrib; ++ unsigned char *pframe; ++ struct rtw_ieee80211_hdr *pwlanhdr; ++ unsigned short *fctrl; ++ struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); ++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ struct wifidirect_info *pwdinfo = &( padapter->wdinfo); ++ ++ ++ if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL) ++ { ++ return; ++ } ++ ++ DBG_8192C( "[%s] In\n", __FUNCTION__ ); ++ //update attribute ++ pattrib = &pmgntframe->attrib; ++ update_mgntframe_attrib(padapter, pattrib); ++ ++ _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); ++ ++ pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; ++ pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; ++ ++ fctrl = &(pwlanhdr->frame_ctl); ++ *(fctrl) = 0; ++ ++ _rtw_memcpy(pwlanhdr->addr1, raddr, ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr2, myid(&(padapter->eeprompriv)), ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr3, myid(&(padapter->eeprompriv)), ETH_ALEN); ++ ++ SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); ++ pmlmeext->mgnt_seq++; ++ SetFrameSubType(pframe, WIFI_ACTION); ++ ++ pframe += sizeof(struct rtw_ieee80211_hdr_3addr); ++ pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); ++ ++ pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen)); ++ pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen)); ++ pframe = rtw_set_fixed_ie(pframe, 4, (unsigned char *) &(p2poui), &(pattrib->pktlen)); ++ pframe = rtw_set_fixed_ie(pframe, 1, &(oui_subtype), &(pattrib->pktlen)); ++ pframe = rtw_set_fixed_ie(pframe, 1, &(pwdinfo->negotiation_dialog_token), &(pattrib->pktlen)); ++ ++ ++ ++ // P2P IE Section. ++ ++ // P2P OUI ++ p2pielen = 0; ++ p2pie[ p2pielen++ ] = 0x50; ++ p2pie[ p2pielen++ ] = 0x6F; ++ p2pie[ p2pielen++ ] = 0x9A; ++ p2pie[ p2pielen++ ] = 0x09; // WFA P2P v1.0 ++ ++ // Commented by Albert 20110306 ++ // According to the P2P Specification, the group negoitation request frame should contain 5 P2P attributes ++ // 1. Status ++ // 2. P2P Capability ++ // 3. Operating Channel ++ // 4. Channel List ++ // 5. Group ID ( if this WiFi is GO ) ++ ++ // P2P Status ++ // Type: ++ p2pie[ p2pielen++ ] = P2P_ATTR_STATUS; ++ ++ // Length: ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0001 ); ++ p2pielen += 2; ++ ++ // Value: ++ p2pie[ p2pielen++ ] = result; ++ ++ // P2P Capability ++ // Type: ++ p2pie[ p2pielen++ ] = P2P_ATTR_CAPABILITY; ++ ++ // Length: ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0002 ); ++ p2pielen += 2; ++ ++ // Value: ++ // Device Capability Bitmap, 1 byte ++ // Be able to participate in additional P2P Groups and ++ // support the P2P Invitation Procedure ++ p2pie[ p2pielen++ ] = P2P_DEVCAP_INVITATION_PROC; ++ ++ // Group Capability Bitmap, 1 byte ++ p2pie[ p2pielen++ ] = 0x00; ++ ++ ++ // Operating Channel ++ // Type: ++ p2pie[ p2pielen++ ] = P2P_ATTR_OPERATING_CH; ++ ++ // Length: ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0005 ); ++ p2pielen += 2; ++ ++ // Value: ++ // Country String ++ p2pie[ p2pielen++ ] = 'U'; ++ p2pie[ p2pielen++ ] = 'S'; ++ ++ // The third byte should be set to 0x04. ++ // Described in the "Operating Channel Attribute" section. ++ p2pie[ p2pielen++ ] = 0x04; ++ ++ // Operating Class ++ p2pie[ p2pielen++ ] = 0x51; // Copy from SD7 ++ ++ if ( rtw_p2p_chk_role(pwdinfo, P2P_ROLE_CLIENT) ) ++ { ++ p2pie[ p2pielen++ ] = pwdinfo->peer_operating_ch; ++ } ++ else ++ { ++ // Channel Number ++ p2pie[ p2pielen++ ] = pwdinfo->operating_channel; // Use the listen channel as the operating channel ++ } ++ ++ ++ // Channel List ++ // Type: ++ p2pie[ p2pielen++ ] = P2P_ATTR_CH_LIST; ++ ++ // Length: ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 5 + pwdinfo->channel_cnt ); ++ p2pielen += 2; ++ ++ // Value: ++ // Country String ++ p2pie[ p2pielen++ ] = 'U'; ++ p2pie[ p2pielen++ ] = 'S'; ++ ++ // The third byte should be set to 0x04. ++ // Described in the "Operating Channel Attribute" section. ++ p2pie[ p2pielen++ ] = 0x04; ++ ++ // Channel Entry List ++ // Operating Class ++ p2pie[ p2pielen++ ] = 0x51; // Copy from SD7 ++ ++ // Number of Channels ++ p2pie[ p2pielen++ ] = pwdinfo->channel_cnt; ++ ++ // Channel List ++ _rtw_memcpy( p2pie + p2pielen, pwdinfo->channel_list, pwdinfo->channel_cnt ); ++ p2pielen += pwdinfo->channel_cnt; ++ ++ if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO) ) ++ { ++ // Group ID Attribute ++ // Type: ++ p2pie[ p2pielen++ ] = P2P_ATTR_GROUP_ID; ++ ++ // Length: ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( ETH_ALEN + pwdinfo->nego_ssidlen ); ++ p2pielen += 2; ++ ++ // Value: ++ // p2P Device Address ++ _rtw_memcpy( p2pie + p2pielen , pwdinfo->device_addr, ETH_ALEN ); ++ p2pielen += ETH_ALEN; ++ ++ // SSID ++ _rtw_memcpy( p2pie + p2pielen, pwdinfo->nego_ssid, pwdinfo->nego_ssidlen ); ++ p2pielen += pwdinfo->nego_ssidlen; ++ } ++ ++ pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, p2pielen, (unsigned char *) p2pie, &pattrib->pktlen ); ++ ++#ifdef CONFIG_WFD ++ wfdielen = build_nego_confirm_wfd_ie(pwdinfo, pframe); ++ pframe += wfdielen; ++ pattrib->pktlen += wfdielen; ++#endif //CONFIG_WFD ++ ++ pattrib->last_txcmdsz = pattrib->pktlen; ++ ++ dump_mgntframe(padapter, pmgntframe); ++ ++ return; ++ ++} ++ ++void issue_p2p_invitation_request(_adapter *padapter, u8* raddr ) ++{ ++ ++ unsigned char category = RTW_WLAN_CATEGORY_PUBLIC; ++ u8 action = P2P_PUB_ACTION_ACTION; ++ u32 p2poui = cpu_to_be32(P2POUI); ++ u8 oui_subtype = P2P_INVIT_REQ; ++ u8 p2pie[ 255 ] = { 0x00 }; ++ u8 p2pielen = 0; ++ u8 dialogToken = 3; ++ ++ struct xmit_frame *pmgntframe; ++ struct pkt_attrib *pattrib; ++ unsigned char *pframe; ++ struct rtw_ieee80211_hdr *pwlanhdr; ++ unsigned short *fctrl; ++ struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); ++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ struct wifidirect_info *pwdinfo = &( padapter->wdinfo); ++ ++ ++ if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL) ++ { ++ return; ++ } ++ ++ //update attribute ++ pattrib = &pmgntframe->attrib; ++ update_mgntframe_attrib(padapter, pattrib); ++ ++ _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); ++ ++ pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; ++ pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; ++ ++ fctrl = &(pwlanhdr->frame_ctl); ++ *(fctrl) = 0; ++ ++ _rtw_memcpy(pwlanhdr->addr1, raddr, ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr2, myid(&(padapter->eeprompriv)), ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr3, raddr, ETH_ALEN); ++ ++ SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); ++ pmlmeext->mgnt_seq++; ++ SetFrameSubType(pframe, WIFI_ACTION); ++ ++ pframe += sizeof(struct rtw_ieee80211_hdr_3addr); ++ pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); ++ ++ pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen)); ++ pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen)); ++ pframe = rtw_set_fixed_ie(pframe, 4, (unsigned char *) &(p2poui), &(pattrib->pktlen)); ++ pframe = rtw_set_fixed_ie(pframe, 1, &(oui_subtype), &(pattrib->pktlen)); ++ pframe = rtw_set_fixed_ie(pframe, 1, &(dialogToken), &(pattrib->pktlen)); ++ ++ // P2P IE Section. ++ ++ // P2P OUI ++ p2pielen = 0; ++ p2pie[ p2pielen++ ] = 0x50; ++ p2pie[ p2pielen++ ] = 0x6F; ++ p2pie[ p2pielen++ ] = 0x9A; ++ p2pie[ p2pielen++ ] = 0x09; // WFA P2P v1.0 ++ ++ // Commented by Albert 20101011 ++ // According to the P2P Specification, the P2P Invitation request frame should contain 7 P2P attributes ++ // 1. Configuration Timeout ++ // 2. Invitation Flags ++ // 3. Operating Channel ( Only GO ) ++ // 4. P2P Group BSSID ( Only GO ) ++ // 5. Channel List ++ // 6. P2P Group ID ++ // 7. P2P Device Info ++ ++ // Configuration Timeout ++ // Type: ++ p2pie[ p2pielen++ ] = P2P_ATTR_CONF_TIMEOUT; ++ ++ // Length: ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0002 ); ++ p2pielen += 2; ++ ++ // Value: ++ p2pie[ p2pielen++ ] = 200; // 2 seconds needed to be the P2P GO ++ p2pie[ p2pielen++ ] = 200; // 2 seconds needed to be the P2P Client ++ ++ // Invitation Flags ++ // Type: ++ p2pie[ p2pielen++ ] = P2P_ATTR_INVITATION_FLAGS; ++ ++ // Length: ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0001 ); ++ p2pielen += 2; ++ ++ // Value: ++ p2pie[ p2pielen++ ] = P2P_INVITATION_FLAGS_PERSISTENT; ++ ++ ++ // Channel List ++ // Type: ++ p2pie[ p2pielen++ ] = P2P_ATTR_CH_LIST; ++ ++ // Length: ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0010 ); ++ p2pielen += 2; ++ ++ // Value: ++ // Country String ++ p2pie[ p2pielen++ ] = 'U'; ++ p2pie[ p2pielen++ ] = 'S'; ++ ++ // The third byte should be set to 0x04. ++ // Described in the "Operating Channel Attribute" section. ++ p2pie[ p2pielen++ ] = 0x04; ++ ++ // Channel Entry List ++ // Operating Class ++ p2pie[ p2pielen++ ] = 0x51; // Copy from SD7 ++ ++ // Number of Channels ++ p2pie[ p2pielen++ ] = 0x0B; // support channel 1 - 11 ++ ++ // Channel List ++ p2pie[ p2pielen++ ] = 0x01; ++ p2pie[ p2pielen++ ] = 0x02; ++ p2pie[ p2pielen++ ] = 0x03; ++ p2pie[ p2pielen++ ] = 0x04; ++ p2pie[ p2pielen++ ] = 0x05; ++ p2pie[ p2pielen++ ] = 0x06; ++ p2pie[ p2pielen++ ] = 0x07; ++ p2pie[ p2pielen++ ] = 0x08; ++ p2pie[ p2pielen++ ] = 0x09; ++ p2pie[ p2pielen++ ] = 0x0A; ++ p2pie[ p2pielen++ ] = 0x0B; ++ ++ // P2P Group ID ++ // Type: ++ p2pie[ p2pielen++ ] = P2P_ATTR_GROUP_ID; ++ ++ // Length: ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 6 + pwdinfo->invitereq_info.ssidlen ); ++ p2pielen += 2; ++ ++ // Value: ++ // P2P Device Address for GO ++ _rtw_memcpy( p2pie + p2pielen, raddr, ETH_ALEN ); ++ p2pielen += ETH_ALEN; ++ ++ // SSID ++ _rtw_memcpy( p2pie + p2pielen, pwdinfo->invitereq_info.ssid, pwdinfo->invitereq_info.ssidlen ); ++ p2pielen += pwdinfo->invitereq_info.ssidlen; ++ ++ ++ // Device Info ++ // Type: ++ p2pie[ p2pielen++ ] = P2P_ATTR_DEVICE_INFO; ++ ++ // Length: ++ // 21 -> P2P Device Address (6bytes) + Config Methods (2bytes) + Primary Device Type (8bytes) ++ // + NumofSecondDevType (1byte) + WPS Device Name ID field (2bytes) + WPS Device Name Len field (2bytes) ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 21 + pwdinfo->device_name_len ); ++ p2pielen += 2; ++ ++ // Value: ++ // P2P Device Address ++ _rtw_memcpy( p2pie + p2pielen, myid( &padapter->eeprompriv ), ETH_ALEN ); ++ p2pielen += ETH_ALEN; ++ ++ // Config Method ++ // This field should be big endian. Noted by P2P specification. ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_CONFIG_METHOD_DISPLAY ); ++ p2pielen += 2; ++ ++ // Primary Device Type ++ // Category ID ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_PDT_CID_RTK_WIDI ); ++ p2pielen += 2; ++ ++ // OUI ++ *(u32*) ( p2pie + p2pielen ) = cpu_to_be32( WPSOUI ); ++ p2pielen += 4; ++ ++ // Sub Category ID ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_PDT_SCID_RTK_DMP ); ++ p2pielen += 2; ++ ++ // Number of Secondary Device Types ++ p2pie[ p2pielen++ ] = 0x00; // No Secondary Device Type List ++ ++ // Device Name ++ // Type: ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_ATTR_DEVICE_NAME ); ++ p2pielen += 2; ++ ++ // Length: ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( pwdinfo->device_name_len ); ++ p2pielen += 2; ++ ++ // Value: ++ _rtw_memcpy( p2pie + p2pielen, pwdinfo->device_name, pwdinfo->device_name_len ); ++ p2pielen += pwdinfo->device_name_len; ++ ++ pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, p2pielen, (unsigned char *) p2pie, &pattrib->pktlen ); ++ ++ ++ pattrib->last_txcmdsz = pattrib->pktlen; ++ ++ dump_mgntframe(padapter, pmgntframe); ++ ++ return; ++ ++} ++ ++void issue_p2p_invitation_response(_adapter *padapter, u8* raddr, u8 dialogToken, u8 success) ++{ ++ ++ unsigned char category = RTW_WLAN_CATEGORY_PUBLIC; ++ u8 action = P2P_PUB_ACTION_ACTION; ++ u32 p2poui = cpu_to_be32(P2POUI); ++ u8 oui_subtype = P2P_INVIT_RESP; ++ u8 p2pie[ 255 ] = { 0x00 }; ++ u8 p2pielen = 0; ++ ++ struct xmit_frame *pmgntframe; ++ struct pkt_attrib *pattrib; ++ unsigned char *pframe; ++ struct rtw_ieee80211_hdr *pwlanhdr; ++ unsigned short *fctrl; ++ struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); ++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ struct wifidirect_info *pwdinfo = &( padapter->wdinfo); ++ ++ ++ if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL) ++ { ++ return; ++ } ++ ++ //update attribute ++ pattrib = &pmgntframe->attrib; ++ update_mgntframe_attrib(padapter, pattrib); ++ ++ _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); ++ ++ pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; ++ pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; ++ ++ fctrl = &(pwlanhdr->frame_ctl); ++ *(fctrl) = 0; ++ ++ _rtw_memcpy(pwlanhdr->addr1, raddr, ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr2, myid(&(padapter->eeprompriv)), ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr3, raddr, ETH_ALEN); ++ ++ SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); ++ pmlmeext->mgnt_seq++; ++ SetFrameSubType(pframe, WIFI_ACTION); ++ ++ pframe += sizeof(struct rtw_ieee80211_hdr_3addr); ++ pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); ++ ++ pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen)); ++ pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen)); ++ pframe = rtw_set_fixed_ie(pframe, 4, (unsigned char *) &(p2poui), &(pattrib->pktlen)); ++ pframe = rtw_set_fixed_ie(pframe, 1, &(oui_subtype), &(pattrib->pktlen)); ++ pframe = rtw_set_fixed_ie(pframe, 1, &(dialogToken), &(pattrib->pktlen)); ++ ++ // P2P IE Section. ++ ++ // P2P OUI ++ p2pielen = 0; ++ p2pie[ p2pielen++ ] = 0x50; ++ p2pie[ p2pielen++ ] = 0x6F; ++ p2pie[ p2pielen++ ] = 0x9A; ++ p2pie[ p2pielen++ ] = 0x09; // WFA P2P v1.0 ++ ++ // Commented by Albert 20101005 ++ // According to the P2P Specification, the P2P Invitation response frame should contain 5 P2P attributes ++ // 1. Status ++ // 2. Configuration Timeout ++ // 3. Operating Channel ( Only GO ) ++ // 4. P2P Group BSSID ( Only GO ) ++ // 5. Channel List ++ ++ // P2P Status ++ // Type: ++ p2pie[ p2pielen++ ] = P2P_ATTR_STATUS; ++ ++ // Length: ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0001 ); ++ p2pielen += 2; ++ ++ // Value: ++ if ( success ) ++ { ++ p2pie[ p2pielen++ ] = P2P_STATUS_SUCCESS; ++ } ++ else ++ { ++ // Sent the event receiving the P2P Invitation Req frame to DMP UI. ++ // DMP had to compare the MAC address to find out the profile. ++ // So, the WiFi driver will send the P2P_STATUS_FAIL_INFO_UNAVAILABLE to NB. ++ // If the UI found the corresponding profile, the WiFi driver sends the P2P Invitation Req ++ // to NB to rebuild the persistent group. ++ p2pie[ p2pielen++ ] = P2P_STATUS_FAIL_INFO_UNAVAILABLE; ++ } ++ ++ // Configuration Timeout ++ // Type: ++ p2pie[ p2pielen++ ] = P2P_ATTR_CONF_TIMEOUT; ++ ++ // Length: ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0002 ); ++ p2pielen += 2; ++ ++ // Value: ++ p2pie[ p2pielen++ ] = 200; // 2 seconds needed to be the P2P GO ++ p2pie[ p2pielen++ ] = 200; // 2 seconds needed to be the P2P Client ++ ++ ++ if ( success ) ++ { ++ // Channel List ++ // Type: ++ p2pie[ p2pielen++ ] = P2P_ATTR_CH_LIST; ++ ++ // Length: ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0010 ); ++ p2pielen += 2; ++ ++ // Value: ++ // Country String ++ p2pie[ p2pielen++ ] = 'U'; ++ p2pie[ p2pielen++ ] = 'S'; ++ ++ // The third byte should be set to 0x04. ++ // Described in the "Operating Channel Attribute" section. ++ p2pie[ p2pielen++ ] = 0x04; ++ ++ // Channel Entry List ++ // Operating Class ++ p2pie[ p2pielen++ ] = 0x51; // Copy from SD7 ++ ++ // Number of Channels ++ p2pie[ p2pielen++ ] = 0x0B; // support channel 1 - 11 ++ ++ // Channel List ++ p2pie[ p2pielen++ ] = 0x01; ++ p2pie[ p2pielen++ ] = 0x02; ++ p2pie[ p2pielen++ ] = 0x03; ++ p2pie[ p2pielen++ ] = 0x04; ++ p2pie[ p2pielen++ ] = 0x05; ++ p2pie[ p2pielen++ ] = 0x06; ++ p2pie[ p2pielen++ ] = 0x07; ++ p2pie[ p2pielen++ ] = 0x08; ++ p2pie[ p2pielen++ ] = 0x09; ++ p2pie[ p2pielen++ ] = 0x0A; ++ p2pie[ p2pielen++ ] = 0x0B; ++ } ++ ++ pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, p2pielen, (unsigned char *) p2pie, &pattrib->pktlen ); ++ ++ ++ pattrib->last_txcmdsz = pattrib->pktlen; ++ ++ dump_mgntframe(padapter, pmgntframe); ++ ++ return; ++ ++} ++ ++void issue_p2p_provision_request(_adapter *padapter, u8* pinterface_raddr, u8* pssid, u8 ussidlen, u8* pdev_raddr ) ++{ ++ unsigned char category = RTW_WLAN_CATEGORY_PUBLIC; ++ u8 action = P2P_PUB_ACTION_ACTION; ++ u8 dialogToken = 1; ++ u32 p2poui = cpu_to_be32(P2POUI); ++ u8 oui_subtype = P2P_PROVISION_DISC_REQ; ++ u8 wpsie[ 100 ] = { 0x00 }; ++ u8 wpsielen = 0; ++ u32 p2pielen = 0; ++#ifdef CONFIG_WFD ++ u32 wfdielen = 0; ++#endif //CONFIG_WFD ++ ++ struct xmit_frame *pmgntframe; ++ struct pkt_attrib *pattrib; ++ unsigned char *pframe; ++ struct rtw_ieee80211_hdr *pwlanhdr; ++ unsigned short *fctrl; ++ struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); ++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ struct wifidirect_info *pwdinfo = &(padapter->wdinfo); ++ ++ ++ if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL) ++ { ++ return; ++ } ++ ++ DBG_8192C( "[%s] In\n", __FUNCTION__ ); ++ //update attribute ++ pattrib = &pmgntframe->attrib; ++ update_mgntframe_attrib(padapter, pattrib); ++ ++ _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); ++ ++ pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; ++ pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; ++ ++ fctrl = &(pwlanhdr->frame_ctl); ++ *(fctrl) = 0; ++ ++ _rtw_memcpy(pwlanhdr->addr1, pinterface_raddr, ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr2, myid(&(padapter->eeprompriv)), ETH_ALEN); ++ //_rtw_memcpy(pwlanhdr->addr3, myid(&(padapter->eeprompriv)), ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr3, pinterface_raddr, ETH_ALEN); ++ ++ SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); ++ pmlmeext->mgnt_seq++; ++ SetFrameSubType(pframe, WIFI_ACTION); ++ ++ pframe += sizeof(struct rtw_ieee80211_hdr_3addr); ++ pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); ++ ++ pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen)); ++ pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen)); ++ pframe = rtw_set_fixed_ie(pframe, 4, (unsigned char *) &(p2poui), &(pattrib->pktlen)); ++ pframe = rtw_set_fixed_ie(pframe, 1, &(oui_subtype), &(pattrib->pktlen)); ++ pframe = rtw_set_fixed_ie(pframe, 1, &(dialogToken), &(pattrib->pktlen)); ++ ++ p2pielen = build_prov_disc_request_p2p_ie( pwdinfo, pframe, pssid, ussidlen, pdev_raddr ); ++ ++ pframe += p2pielen; ++ pattrib->pktlen += p2pielen; ++ ++ wpsielen = 0; ++ // WPS OUI ++ *(u32*) ( wpsie ) = cpu_to_be32( WPSOUI ); ++ wpsielen += 4; ++ ++ // WPS version ++ // Type: ++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_ATTR_VER1 ); ++ wpsielen += 2; ++ ++ // Length: ++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( 0x0001 ); ++ wpsielen += 2; ++ ++ // Value: ++ wpsie[wpsielen++] = WPS_VERSION_1; // Version 1.0 ++ ++ // Config Method ++ // Type: ++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_ATTR_CONF_METHOD ); ++ wpsielen += 2; ++ ++ // Length: ++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( 0x0002 ); ++ wpsielen += 2; ++ ++ // Value: ++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( pwdinfo->tx_prov_disc_info.wps_config_method_request ); ++ wpsielen += 2; ++ ++ pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, wpsielen, (unsigned char *) wpsie, &pattrib->pktlen ); ++ ++ ++#ifdef CONFIG_WFD ++ wfdielen = build_provdisc_req_wfd_ie(pwdinfo, pframe); ++ pframe += wfdielen; ++ pattrib->pktlen += wfdielen; ++#endif //CONFIG_WFD ++ ++ pattrib->last_txcmdsz = pattrib->pktlen; ++ ++ dump_mgntframe(padapter, pmgntframe); ++ ++ return; ++ ++} ++ ++u8 is_matched_in_profilelist( u8* peermacaddr, struct profile_info* profileinfo ) ++{ ++ u8 i, match_result = 0; ++ ++ DBG_8192C( "[%s] peermac = %.2X %.2X %.2X %.2X %.2X %.2X\n", __FUNCTION__, ++ peermacaddr[0], peermacaddr[1],peermacaddr[2],peermacaddr[3],peermacaddr[4],peermacaddr[5]); ++ ++ for( i = 0; i < P2P_MAX_PERSISTENT_GROUP_NUM; i++, profileinfo++ ) ++ { ++ DBG_8192C( "[%s] profileinfo_mac = %.2X %.2X %.2X %.2X %.2X %.2X\n", __FUNCTION__, ++ profileinfo->peermac[0], profileinfo->peermac[1],profileinfo->peermac[2],profileinfo->peermac[3],profileinfo->peermac[4],profileinfo->peermac[5]); ++ if ( _rtw_memcmp( peermacaddr, profileinfo->peermac, ETH_ALEN ) ) ++ { ++ match_result = 1; ++ DBG_8192C( "[%s] Match!\n", __FUNCTION__ ); ++ break; ++ } ++ } ++ ++ return (match_result ); ++} ++ ++void issue_probersp_p2p(_adapter *padapter, unsigned char *da) ++{ ++ struct xmit_frame *pmgntframe; ++ struct pkt_attrib *pattrib; ++ unsigned char *pframe; ++ struct rtw_ieee80211_hdr *pwlanhdr; ++ unsigned short *fctrl; ++ unsigned char *mac; ++ struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); ++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ //WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network); ++ u16 beacon_interval = 100; ++ u16 capInfo = 0; ++ struct wifidirect_info *pwdinfo = &(padapter->wdinfo); ++ u8 wpsie[255] = { 0x00 }; ++ u32 wpsielen = 0, p2pielen = 0; ++#ifdef CONFIG_WFD ++ u32 wfdielen = 0; ++#endif //CONFIG_WFD ++#ifdef CONFIG_IOCTL_CFG80211 ++ struct cfg80211_wifidirect_info *pcfg80211_wdinfo = &padapter->cfg80211_wdinfo; ++ struct ieee80211_channel *ieee_ch = &pcfg80211_wdinfo->remain_on_ch_channel; ++ u8 listen_channel = (u8) ieee80211_frequency_to_channel(ieee_ch->center_freq); ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++#endif //CONFIG_IOCTL_CFG80211 ++ ++ //DBG_871X("%s\n", __FUNCTION__); ++ ++ if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL) ++ { ++ return; ++ } ++ ++ //update attribute ++ pattrib = &pmgntframe->attrib; ++ update_mgntframe_attrib(padapter, pattrib); ++ ++ _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); ++ ++ pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; ++ pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; ++ ++ mac = myid(&(padapter->eeprompriv)); ++ ++ fctrl = &(pwlanhdr->frame_ctl); ++ *(fctrl) = 0; ++ _rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr2, mac, ETH_ALEN); ++ ++ // Use the device address for BSSID field. ++ _rtw_memcpy(pwlanhdr->addr3, mac, ETH_ALEN); ++ ++ SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); ++ pmlmeext->mgnt_seq++; ++ SetFrameSubType(fctrl, WIFI_PROBERSP); ++ ++ pattrib->hdrlen = sizeof(struct rtw_ieee80211_hdr_3addr); ++ pattrib->pktlen = pattrib->hdrlen; ++ pframe += pattrib->hdrlen; ++ ++ //timestamp will be inserted by hardware ++ pframe += 8; ++ pattrib->pktlen += 8; ++ ++ // beacon interval: 2 bytes ++ _rtw_memcpy(pframe, (unsigned char *) &beacon_interval, 2); ++ pframe += 2; ++ pattrib->pktlen += 2; ++ ++ // capability info: 2 bytes ++ // ESS and IBSS bits must be 0 (defined in the 3.1.2.1.1 of WiFi Direct Spec) ++ capInfo |= cap_ShortPremble; ++ capInfo |= cap_ShortSlot; ++ ++ _rtw_memcpy(pframe, (unsigned char *) &capInfo, 2); ++ pframe += 2; ++ pattrib->pktlen += 2; ++ ++ ++ // SSID ++ pframe = rtw_set_ie(pframe, _SSID_IE_, 7, pwdinfo->p2p_wildcard_ssid, &pattrib->pktlen); ++ ++ // supported rates... ++ // Use the OFDM rate in the P2P probe response frame. ( 6(B), 9(B), 12, 18, 24, 36, 48, 54 ) ++ pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_, 8, pwdinfo->support_rate, &pattrib->pktlen); ++ ++ // DS parameter set ++#ifdef CONFIG_IOCTL_CFG80211 ++ if(wdev_to_priv(padapter->rtw_wdev)->p2p_enabled && listen_channel !=0) ++ { ++ pframe = rtw_set_ie(pframe, _DSSET_IE_, 1, (unsigned char *)&listen_channel, &pattrib->pktlen); ++ } ++ else ++#endif //CONFIG_IOCTL_CFG80211 ++ { ++ pframe = rtw_set_ie(pframe, _DSSET_IE_, 1, (unsigned char *)&pwdinfo->listen_channel, &pattrib->pktlen); ++ } ++ ++ ++#ifdef CONFIG_IOCTL_CFG80211 ++ if(wdev_to_priv(padapter->rtw_wdev)->p2p_enabled) ++ { ++ if( pmlmepriv->wps_probe_resp_ie != NULL && pmlmepriv->p2p_probe_resp_ie != NULL ) ++ { ++ //WPS IE ++ _rtw_memcpy(pframe, pmlmepriv->wps_probe_resp_ie, pmlmepriv->wps_probe_resp_ie_len); ++ pattrib->pktlen += pmlmepriv->wps_probe_resp_ie_len; ++ pframe += pmlmepriv->wps_probe_resp_ie_len; ++ ++ //P2P IE ++ _rtw_memcpy(pframe, pmlmepriv->p2p_probe_resp_ie, pmlmepriv->p2p_probe_resp_ie_len); ++ pattrib->pktlen += pmlmepriv->p2p_probe_resp_ie_len; ++ pframe += pmlmepriv->p2p_probe_resp_ie_len; ++ } ++ } ++ else ++#endif //CONFIG_IOCTL_CFG80211 ++ { ++ ++ // Todo: WPS IE ++ // Noted by Albert 20100907 ++ // According to the WPS specification, all the WPS attribute is presented by Big Endian. ++ ++ wpsielen = 0; ++ // WPS OUI ++ *(u32*) ( wpsie ) = cpu_to_be32( WPSOUI ); ++ wpsielen += 4; ++ ++ // WPS version ++ // Type: ++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_ATTR_VER1 ); ++ wpsielen += 2; ++ ++ // Length: ++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( 0x0001 ); ++ wpsielen += 2; ++ ++ // Value: ++ wpsie[wpsielen++] = WPS_VERSION_1; // Version 1.0 ++ ++ // WiFi Simple Config State ++ // Type: ++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_ATTR_SIMPLE_CONF_STATE ); ++ wpsielen += 2; ++ ++ // Length: ++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( 0x0001 ); ++ wpsielen += 2; ++ ++ // Value: ++ wpsie[wpsielen++] = WPS_WSC_STATE_NOT_CONFIG; // Not Configured. ++ ++ // Response Type ++ // Type: ++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_ATTR_RESP_TYPE ); ++ wpsielen += 2; ++ ++ // Length: ++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( 0x0001 ); ++ wpsielen += 2; ++ ++ // Value: ++ wpsie[wpsielen++] = WPS_RESPONSE_TYPE_8021X; ++ ++ // UUID-E ++ // Type: ++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_ATTR_UUID_E ); ++ wpsielen += 2; ++ ++ // Length: ++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( 0x0010 ); ++ wpsielen += 2; ++ ++ // Value: ++ _rtw_memcpy( wpsie + wpsielen, myid( &padapter->eeprompriv ), ETH_ALEN ); ++ wpsielen += 0x10; ++ ++ // Manufacturer ++ // Type: ++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_ATTR_MANUFACTURER ); ++ wpsielen += 2; ++ ++ // Length: ++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( 0x0007 ); ++ wpsielen += 2; ++ ++ // Value: ++ _rtw_memcpy( wpsie + wpsielen, "Realtek", 7 ); ++ wpsielen += 7; ++ ++ // Model Name ++ // Type: ++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_ATTR_MODEL_NAME ); ++ wpsielen += 2; ++ ++ // Length: ++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( 0x0006 ); ++ wpsielen += 2; ++ ++ // Value: ++ _rtw_memcpy( wpsie + wpsielen, "8192CU", 6 ); ++ wpsielen += 6; ++ ++ // Model Number ++ // Type: ++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_ATTR_MODEL_NUMBER ); ++ wpsielen += 2; ++ ++ // Length: ++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( 0x0001 ); ++ wpsielen += 2; ++ ++ // Value: ++ wpsie[ wpsielen++ ] = 0x31; // character 1 ++ ++ // Serial Number ++ // Type: ++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_ATTR_SERIAL_NUMBER ); ++ wpsielen += 2; ++ ++ // Length: ++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( ETH_ALEN ); ++ wpsielen += 2; ++ ++ // Value: ++ _rtw_memcpy( wpsie + wpsielen, "123456" , ETH_ALEN ); ++ wpsielen += ETH_ALEN; ++ ++ // Primary Device Type ++ // Type: ++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_ATTR_PRIMARY_DEV_TYPE ); ++ wpsielen += 2; ++ ++ // Length: ++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( 0x0008 ); ++ wpsielen += 2; ++ ++ // Value: ++ // Category ID ++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_PDT_CID_RTK_WIDI ); ++ wpsielen += 2; ++ ++ // OUI ++ *(u32*) ( wpsie + wpsielen ) = cpu_to_be32( WPSOUI ); ++ wpsielen += 4; ++ ++ // Sub Category ID ++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_PDT_SCID_RTK_DMP ); ++ wpsielen += 2; ++ ++ // Device Name ++ // Type: ++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_ATTR_DEVICE_NAME ); ++ wpsielen += 2; ++ ++ // Length: ++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( pwdinfo->device_name_len ); ++ wpsielen += 2; ++ ++ // Value: ++ _rtw_memcpy( wpsie + wpsielen, pwdinfo->device_name, pwdinfo->device_name_len ); ++ wpsielen += pwdinfo->device_name_len; ++ ++ // Config Method ++ // Type: ++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_ATTR_CONF_METHOD ); ++ wpsielen += 2; ++ ++ // Length: ++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( 0x0002 ); ++ wpsielen += 2; ++ ++ // Value: ++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( pwdinfo->supported_wps_cm ); ++ wpsielen += 2; ++ ++ ++ pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, wpsielen, (unsigned char *) wpsie, &pattrib->pktlen ); ++ ++ ++ p2pielen = build_probe_resp_p2p_ie(pwdinfo, pframe); ++ pframe += p2pielen; ++ pattrib->pktlen += p2pielen; ++ } ++ ++#ifdef CONFIG_WFD ++ wfdielen = build_probe_resp_wfd_ie(pwdinfo, pframe); ++ pframe += wfdielen; ++ pattrib->pktlen += wfdielen; ++#endif //CONFIG_WFD ++ ++ pattrib->last_txcmdsz = pattrib->pktlen; ++ ++ ++ dump_mgntframe(padapter, pmgntframe); ++ ++ return; ++ ++} ++ ++void issue_probereq_p2p(_adapter *padapter) ++{ ++ struct xmit_frame *pmgntframe; ++ struct pkt_attrib *pattrib; ++ unsigned char *pframe; ++ struct rtw_ieee80211_hdr *pwlanhdr; ++ unsigned short *fctrl; ++ unsigned char *mac; ++ unsigned char bssrate[NumRates]; ++ struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); ++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ int bssrate_len = 0; ++ u8 bc_addr[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; ++ struct wifidirect_info *pwdinfo = &(padapter->wdinfo); ++ u8 wpsie[255] = { 0x00 }, p2pie[ 255 ] = { 0x00 }; ++ u16 wpsielen = 0, p2pielen = 0; ++#ifdef CONFIG_WFD ++ u32 wfdielen = 0; ++#endif //CONFIG_WFD ++#ifdef CONFIG_IOCTL_CFG80211 ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++#endif //CONFIG_IOCTL_CFG80211 ++ if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL) ++ { ++ return; ++ } ++ ++ //update attribute ++ pattrib = &pmgntframe->attrib; ++ update_mgntframe_attrib(padapter, pattrib); ++ ++ ++ _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); ++ ++ pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; ++ pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; ++ ++ mac = myid(&(padapter->eeprompriv)); ++ ++ fctrl = &(pwlanhdr->frame_ctl); ++ *(fctrl) = 0; ++ ++ // broadcast probe request frame ++ _rtw_memcpy(pwlanhdr->addr1, bc_addr, ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr3, bc_addr, ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr2, mac, ETH_ALEN); ++ ++ SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); ++ pmlmeext->mgnt_seq++; ++ SetFrameSubType(pframe, WIFI_PROBEREQ); ++ ++ pframe += sizeof (struct rtw_ieee80211_hdr_3addr); ++ pattrib->pktlen = sizeof (struct rtw_ieee80211_hdr_3addr); ++ ++ if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_TX_PROVISION_DIS_REQ)) ++ { ++ pframe = rtw_set_ie(pframe, _SSID_IE_, pwdinfo->tx_prov_disc_info.ssid.SsidLength, pwdinfo->tx_prov_disc_info.ssid.Ssid, &(pattrib->pktlen)); ++ } ++ else ++ { ++ pframe = rtw_set_ie(pframe, _SSID_IE_, P2P_WILDCARD_SSID_LEN, pwdinfo->p2p_wildcard_ssid, &(pattrib->pktlen)); ++ } ++ // Use the OFDM rate in the P2P probe request frame. ( 6(B), 9(B), 12(B), 24(B), 36, 48, 54 ) ++ pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_, 8, pwdinfo->support_rate, &pattrib->pktlen); ++ ++#ifdef CONFIG_IOCTL_CFG80211 ++ if(wdev_to_priv(padapter->rtw_wdev)->p2p_enabled) ++ { ++ if(pmlmepriv->wps_probe_req_ie != NULL && pmlmepriv->p2p_probe_req_ie != NULL_CHIP_TYPE) ++ { ++ //WPS IE ++ _rtw_memcpy(pframe, pmlmepriv->wps_probe_req_ie, pmlmepriv->wps_probe_req_ie_len); ++ pattrib->pktlen += pmlmepriv->wps_probe_req_ie_len; ++ pframe += pmlmepriv->wps_probe_req_ie_len; ++ ++ //P2P IE ++ _rtw_memcpy(pframe, pmlmepriv->p2p_probe_req_ie, pmlmepriv->p2p_probe_req_ie_len); ++ pattrib->pktlen += pmlmepriv->p2p_probe_req_ie_len; ++ pframe += pmlmepriv->p2p_probe_req_ie_len; ++ } ++ } ++ else ++#endif //CONFIG_IOCTL_CFG80211 ++ { ++ ++ // WPS IE ++ // Noted by Albert 20110221 ++ // According to the WPS specification, all the WPS attribute is presented by Big Endian. ++ ++ wpsielen = 0; ++ // WPS OUI ++ *(u32*) ( wpsie ) = cpu_to_be32( WPSOUI ); ++ wpsielen += 4; ++ ++ // WPS version ++ // Type: ++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_ATTR_VER1 ); ++ wpsielen += 2; ++ ++ // Length: ++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( 0x0001 ); ++ wpsielen += 2; ++ ++ // Value: ++ wpsie[wpsielen++] = WPS_VERSION_1; // Version 1.0 ++ ++ // Device Name ++ // Type: ++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_ATTR_DEVICE_NAME ); ++ wpsielen += 2; ++ ++ // Length: ++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( pwdinfo->device_name_len ); ++ wpsielen += 2; ++ ++ // Value: ++ _rtw_memcpy( wpsie + wpsielen, pwdinfo->device_name, pwdinfo->device_name_len ); ++ wpsielen += pwdinfo->device_name_len; ++ ++ // Primary Device Type ++ // Type: ++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_ATTR_PRIMARY_DEV_TYPE ); ++ wpsielen += 2; ++ ++ // Length: ++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( 0x0008 ); ++ wpsielen += 2; ++ ++ // Value: ++ // Category ID ++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_PDT_CID_RTK_WIDI ); ++ wpsielen += 2; ++ ++ // OUI ++ *(u32*) ( wpsie + wpsielen ) = cpu_to_be32( WPSOUI ); ++ wpsielen += 4; ++ ++ // Sub Category ID ++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_PDT_SCID_RTK_DMP ); ++ wpsielen += 2; ++ ++ pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, wpsielen, (unsigned char *) wpsie, &pattrib->pktlen ); ++ ++ // P2P OUI ++ p2pielen = 0; ++ p2pie[ p2pielen++ ] = 0x50; ++ p2pie[ p2pielen++ ] = 0x6F; ++ p2pie[ p2pielen++ ] = 0x9A; ++ p2pie[ p2pielen++ ] = 0x09; // WFA P2P v1.0 ++ ++ // Commented by Albert 20110221 ++ // According to the P2P Specification, the probe request frame should contain 5 P2P attributes ++ // 1. P2P Capability ++ // 2. P2P Device ID if this probe request wants to find the specific P2P device ++ // 3. Listen Channel ++ // 4. Extended Listen Timing ++ // 5. Operating Channel if this WiFi is working as the group owner now ++ ++ // P2P Capability ++ // Type: ++ p2pie[ p2pielen++ ] = P2P_ATTR_CAPABILITY; ++ ++ // Length: ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0002 ); ++ p2pielen += 2; ++ ++ // Value: ++ // Device Capability Bitmap, 1 byte ++ // Be able to participate in additional P2P Groups and ++ // support the P2P Invitation Procedure ++ p2pie[ p2pielen++ ] = P2P_DEVCAP_INVITATION_PROC; ++ ++ // Group Capability Bitmap, 1 byte ++ p2pie[ p2pielen++ ] = 0x00; ++ ++ // Listen Channel ++ // Type: ++ p2pie[ p2pielen++ ] = P2P_ATTR_LISTEN_CH; ++ ++ // Length: ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0005 ); ++ p2pielen += 2; ++ ++ // Value: ++ // Country String ++ p2pie[ p2pielen++ ] = 'U'; ++ p2pie[ p2pielen++ ] = 'S'; ++ ++ // The third byte should be set to 0x04. ++ // Described in the "Operating Channel Attribute" section. ++ p2pie[ p2pielen++ ] = 0x04; ++ ++ // Operating Class ++ p2pie[ p2pielen++ ] = 0x51; // Copy from SD7 ++ ++ // Channel Number ++ p2pie[ p2pielen++ ] = pwdinfo->listen_channel; // listen channel ++ ++ ++ // Extended Listen Timing ++ // Type: ++ p2pie[ p2pielen++ ] = P2P_ATTR_EX_LISTEN_TIMING; ++ ++ // Length: ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0004 ); ++ p2pielen += 2; ++ ++ // Value: ++ // Availability Period ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0xFFFF ); ++ p2pielen += 2; ++ ++ // Availability Interval ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0xFFFF ); ++ p2pielen += 2; ++ ++ if ( rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO) ) ++ { ++ // Operating Channel (if this WiFi is working as the group owner now) ++ // Type: ++ p2pie[ p2pielen++ ] = P2P_ATTR_OPERATING_CH; ++ ++ // Length: ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0005 ); ++ p2pielen += 2; ++ ++ // Value: ++ // Country String ++ p2pie[ p2pielen++ ] = 'U'; ++ p2pie[ p2pielen++ ] = 'S'; ++ ++ // The third byte should be set to 0x04. ++ // Described in the "Operating Channel Attribute" section. ++ p2pie[ p2pielen++ ] = 0x04; ++ ++ // Operating Class ++ p2pie[ p2pielen++ ] = 0x51; // Copy from SD7 ++ ++ // Channel Number ++ p2pie[ p2pielen++ ] = pwdinfo->operating_channel; // operating channel number ++ ++ } ++ ++ pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, p2pielen, (unsigned char *) p2pie, &pattrib->pktlen ); ++ ++ } ++ ++#ifdef CONFIG_WFD ++ wfdielen = build_probe_req_wfd_ie(pwdinfo, pframe); ++ pframe += wfdielen; ++ pattrib->pktlen += wfdielen; ++#endif //CONFIG_WFD ++ ++ pattrib->last_txcmdsz = pattrib->pktlen; ++ ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("issuing probe_req, tx_len=%d\n", pattrib->last_txcmdsz)); ++ ++ dump_mgntframe(padapter, pmgntframe); ++ ++ return; ++} ++ ++#endif //CONFIG_P2P ++ ++unsigned int OnAction_public(_adapter *padapter, union recv_frame *precv_frame) ++{ ++ unsigned char *frame_body; ++ unsigned char category, action; ++ u8 *pframe = precv_frame->u.hdr.rx_data; ++ uint len = precv_frame->u.hdr.len; ++#ifdef CONFIG_P2P ++ u8 *p2p_ie; ++ u32 p2p_ielen, wps_ielen; ++ struct wifidirect_info *pwdinfo = &( padapter->wdinfo ); ++ u8 result = P2P_STATUS_SUCCESS; ++ u8 empty_addr[ETH_ALEN] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; ++#endif //CONFIG_P2P ++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); ++ ++ u16 seq_ctrl = ( (precv_frame->u.hdr.attrib.seq_num&0xffff) << 4) | ++ (precv_frame->u.hdr.attrib.frag_num & 0xf); ++ ++ ++ //check RA matches or not ++ if (!_rtw_memcmp(myid(&(padapter->eeprompriv)), GetAddr1Ptr(pframe), ETH_ALEN))//for if1, sta/ap mode ++ return _SUCCESS; ++ ++ ++ //recv_decache check ++ if(GetRetry(pframe)) ++ { ++ if(seq_ctrl == pmlmeext->action_public_rxseq) ++ { ++ DBG_871X("recv_Action_public_decache, seq_ctrl=0x%x, rxseq=0x%x\n", seq_ctrl, pmlmeext->action_public_rxseq); ++ ++ return _FAIL; ++ } ++ } ++ pmlmeext->action_public_rxseq = seq_ctrl; ++ ++ ++ frame_body = (unsigned char *)(pframe + sizeof(struct rtw_ieee80211_hdr_3addr)); ++ ++ category = frame_body[0]; ++ if(category != RTW_WLAN_CATEGORY_PUBLIC) ++ return _SUCCESS; ++ ++ action = frame_body[ 1 ]; ++ if ( action == ACT_PUBLIC_P2P ) // IEEE 802.11 P2P Public Action usage. ++ { ++#ifdef CONFIG_P2P ++ // Do nothing if the driver doesn't enable the P2P function. ++#ifndef CONFIG_IOCTL_CFG80211 ++ if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE) || rtw_p2p_chk_state(pwdinfo, P2P_STATE_IDLE)) ++ return _SUCCESS; ++#endif //CONFIG_IOCTL_CFG80211 ++ ++ // Commented by Albert 20100908 ++ // Low byte -> High byte is 0x50, 0x6F, 0x9A, 0x09 for P2P OUI. ++ // But the P2POUT is defined as 0x506F9A09 -> should use the cpu_to_be32 ++ if ( cpu_to_be32( *( ( u32* ) ( frame_body + 2 ) ) ) == P2POUI ) ++ { ++#ifdef CONFIG_IOCTL_CFG80211 ++ if(wdev_to_priv(padapter->rtw_wdev)->p2p_enabled) ++ { ++ rtw_cfg80211_rx_p2p_action_public(padapter, pframe, len); ++ } ++ else ++#endif //CONFIG_IOCTL_CFG80211 ++ { ++ len -= sizeof(struct rtw_ieee80211_hdr_3addr); ++ ++ switch( frame_body[ 6 ] )//OUI Subtype ++ { ++ case P2P_GO_NEGO_REQ: ++ { ++ DBG_8192C( "[%s] Got GO Nego Req Frame\n", __FUNCTION__); ++ _rtw_memset( &pwdinfo->groupid_info, 0x00, sizeof( struct group_id_info ) ); ++ ++ if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_GONEGO_FAIL)) ++ { ++ // Commented by Albert 20110526 ++ // In this case, this means the previous nego fail doesn't be reset yet. ++ _cancel_timer_ex( &pwdinfo->restore_p2p_state_timer ); ++ // Restore the previous p2p state ++ rtw_p2p_set_state(pwdinfo, rtw_p2p_pre_state(pwdinfo)); ++ DBG_871X( "[%s] Restore the previous p2p state to %d\n", __FUNCTION__, rtw_p2p_state(pwdinfo) ); ++ } ++ ++ // Commented by Kurt 20110902 ++ //Add if statement to avoid receiving duplicate prov disc req. such that pre_p2p_state would be covered. ++ if(!rtw_p2p_chk_state(pwdinfo, P2P_STATE_GONEGO_ING)) ++ rtw_p2p_set_pre_state(pwdinfo, rtw_p2p_state(pwdinfo)); ++ ++ // Commented by Kurt 20120113 ++ // Get peer_dev_addr here if peer doesn't issue prov_disc frame. ++ if( _rtw_memcmp(pwdinfo->rx_prov_disc_info.peerDevAddr, empty_addr, ETH_ALEN) ); ++ _rtw_memcpy(pwdinfo->rx_prov_disc_info.peerDevAddr, GetAddr2Ptr(pframe), ETH_ALEN); ++ ++ result = process_p2p_group_negotation_req( pwdinfo, frame_body, len ); ++ issue_p2p_GO_response( padapter, GetAddr2Ptr(pframe), frame_body, len, result ); ++ // Commented by Albert 20110718 ++ // No matter negotiating or negotiation failure, the driver should set up the restore P2P state timer. ++ _set_timer( &pwdinfo->restore_p2p_state_timer, 5000 ); ++ break; ++ } ++ case P2P_GO_NEGO_RESP: ++ { ++ DBG_871X( "[%s] Got GO Nego Resp Frame\n", __FUNCTION__); ++ ++ if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_GONEGO_ING)) ++ { ++ // Commented by Albert 20110425 ++ // The restore timer is enabled when issuing the nego request frame of rtw_p2p_connect function. ++ _cancel_timer_ex( &pwdinfo->restore_p2p_state_timer ); ++ result = process_p2p_group_negotation_resp( pwdinfo, frame_body, len); ++ ++ issue_p2p_GO_confirm( pwdinfo->padapter, GetAddr2Ptr(pframe), result); ++ ++ // Reset the dialog token for group negotiation frames. ++ pwdinfo->negotiation_dialog_token = 1; ++ ++ if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_GONEGO_FAIL)) ++ { ++ _set_timer( &pwdinfo->restore_p2p_state_timer, 5000 ); ++ } ++ } ++ else ++ { ++ DBG_8192C( "[%s] Skipped GO Nego Resp Frame (p2p_state != P2P_STATE_GONEGO_ING)\n", __FUNCTION__); ++ } ++ ++ break; ++ } ++ case P2P_GO_NEGO_CONF: ++ { ++ DBG_8192C( "[%s] Got GO Nego Confirm Frame\n", __FUNCTION__); ++ process_p2p_group_negotation_confirm( pwdinfo, frame_body, len); ++ break; ++ } ++ case P2P_INVIT_REQ: ++ { ++ // Added by Albert 2010/10/05 ++ // Received the P2P Invite Request frame. ++ ++ DBG_8192C( "[%s] Got invite request frame!\n", __FUNCTION__ ); ++ if ( (p2p_ie=rtw_get_p2p_ie( frame_body + _PUBLIC_ACTION_IE_OFFSET_, len - _PUBLIC_ACTION_IE_OFFSET_, NULL, &p2p_ielen)) ) ++ { ++ // Parse the necessary information from the P2P Invitation Request frame. ++ // For example: The MAC address of sending this P2P Invitation Request frame. ++ u8 groupid[ 38 ] = { 0x00 }; ++ u32 attr_contentlen = 0; ++ u8 match_result = 0; ++ ++ rtw_get_p2p_attr_content( p2p_ie, p2p_ielen, P2P_ATTR_GROUP_ID, groupid, &attr_contentlen); ++ _rtw_memcpy( pwdinfo->p2p_peer_interface_addr, groupid, ETH_ALEN ); ++ rtw_p2p_set_state(pwdinfo, P2P_STATE_RECV_INVITE_REQ); ++ DBG_871X( "[%s] peer address %.2X %.2X %.2X %.2X %.2X %.2X\n", __FUNCTION__, ++ groupid[0], groupid[1], groupid[2], groupid[3], groupid[4], groupid[5] ); ++ ++ if ( is_matched_in_profilelist( pwdinfo->p2p_peer_interface_addr, &pwdinfo->profileinfo[ 0 ] ) ) ++ { ++ match_result = 1; ++ } ++ else ++ { ++ match_result = 0; ++ } ++ ++ DBG_8192C( "[%s] match_result = %d\n", __FUNCTION__, match_result ); ++ ++ pwdinfo->inviteresp_info.token = frame_body[ 7 ]; ++ issue_p2p_invitation_response( padapter, pwdinfo->p2p_peer_interface_addr, pwdinfo->inviteresp_info.token, match_result ); ++ } ++ ++ break; ++ } ++ case P2P_INVIT_RESP: ++ { ++ u8 attr_content = 0x00; ++ u32 attr_contentlen = 0; ++ ++ DBG_871X( "[%s] Got invite response frame!\n", __FUNCTION__ ); ++ if ( (p2p_ie=rtw_get_p2p_ie( frame_body + _PUBLIC_ACTION_IE_OFFSET_, len - _PUBLIC_ACTION_IE_OFFSET_, NULL, &p2p_ielen)) ) ++ { ++ rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_STATUS, &attr_content, &attr_contentlen); ++ ++ if ( attr_contentlen == 1 ) ++ { ++ DBG_871X( "[%s] Status = %d\n", __FUNCTION__, attr_content ); ++ if ( attr_content == P2P_STATUS_SUCCESS ) ++ { ++ rtw_p2p_set_role(pwdinfo, P2P_ROLE_CLIENT); ++ } ++ else ++ { ++ rtw_p2p_set_role(pwdinfo, P2P_ROLE_DEVICE); ++ } ++ } ++ else ++ { ++ rtw_p2p_set_role(pwdinfo, P2P_ROLE_DEVICE); ++ } ++ } ++ break; ++ } ++ case P2P_DEVDISC_REQ: ++ ++ process_p2p_devdisc_req(pwdinfo, pframe, len); ++ ++ break; ++ ++ case P2P_DEVDISC_RESP: ++ ++ process_p2p_devdisc_resp(pwdinfo, pframe, len); ++ ++ break; ++ ++ case P2P_PROVISION_DISC_REQ: ++ DBG_871X( "[%s] Got Provisioning Discovery Request Frame\n", __FUNCTION__ ); ++ process_p2p_provdisc_req(pwdinfo, pframe, len); ++ _rtw_memcpy(pwdinfo->rx_prov_disc_info.peerDevAddr, GetAddr2Ptr(pframe), ETH_ALEN); ++ ++ //20110902 Kurt ++ //Add the following statement to avoid receiving duplicate prov disc req. such that pre_p2p_state would be covered. ++ if(!rtw_p2p_chk_state(pwdinfo, P2P_STATE_RX_PROVISION_DIS_REQ)) ++ rtw_p2p_set_pre_state(pwdinfo, rtw_p2p_state(pwdinfo)); ++ ++ rtw_p2p_set_state(pwdinfo, P2P_STATE_RX_PROVISION_DIS_REQ); ++ _set_timer( &pwdinfo->restore_p2p_state_timer, P2P_PROVISION_TIMEOUT ); ++ break; ++ ++ case P2P_PROVISION_DISC_RESP: ++ // Commented by Albert 20110707 ++ // Should we check the pwdinfo->tx_prov_disc_info.bsent flag here?? ++ DBG_871X( "[%s] Got Provisioning Discovery Response Frame\n", __FUNCTION__ ); ++ // Commented by Albert 20110426 ++ // The restore timer is enabled when issuing the provisioing request frame in rtw_p2p_prov_disc function. ++ _cancel_timer_ex( &pwdinfo->restore_p2p_state_timer ); ++ rtw_p2p_set_state(pwdinfo, P2P_STATE_RX_PROVISION_DIS_RSP); ++ process_p2p_provdisc_resp(pwdinfo, pframe); ++ _set_timer( &pwdinfo->restore_p2p_state_timer, P2P_PROVISION_TIMEOUT ); ++ break; ++ ++ } ++ } ++ ++ } ++#endif //CONFIG_P2P ++ } ++ ++ return _SUCCESS; ++} ++ ++unsigned int OnAction_ht(_adapter *padapter, union recv_frame *precv_frame) ++{ ++ return _SUCCESS; ++} ++ ++unsigned int OnAction_wmm(_adapter *padapter, union recv_frame *precv_frame) ++{ ++ return _SUCCESS; ++} ++ ++unsigned int OnAction_p2p(_adapter *padapter, union recv_frame *precv_frame) ++{ ++#ifdef CONFIG_P2P ++ u8 *frame_body; ++ u8 category, OUI_Subtype, dialogToken=0; ++ u8 *pframe = precv_frame->u.hdr.rx_data; ++ uint len = precv_frame->u.hdr.len; ++ struct wifidirect_info *pwdinfo = &( padapter->wdinfo ); ++ ++ ++ DBG_871X("%s\n", __FUNCTION__); ++ ++ //check RA matches or not ++ if (!_rtw_memcmp(myid(&(padapter->eeprompriv)), GetAddr1Ptr(pframe), ETH_ALEN))//for if1, sta/ap mode ++ return _SUCCESS; ++ ++ frame_body = (unsigned char *)(pframe + sizeof(struct rtw_ieee80211_hdr_3addr)); ++ ++ category = frame_body[0]; ++ if(category != RTW_WLAN_CATEGORY_P2P) ++ return _SUCCESS; ++ ++ if ( cpu_to_be32( *( ( u32* ) ( frame_body + 1 ) ) ) != P2POUI ) ++ return _SUCCESS; ++ ++#ifdef CONFIG_IOCTL_CFG80211 ++ if(wdev_to_priv(padapter->rtw_wdev)->p2p_enabled) ++ { ++ rtw_cfg80211_rx_action_p2p(padapter, pframe, len); ++ return _SUCCESS; ++ } ++ else ++#endif //CONFIG_IOCTL_CFG80211 ++ { ++ len -= sizeof(struct rtw_ieee80211_hdr_3addr); ++ OUI_Subtype = frame_body[5]; ++ dialogToken = frame_body[6]; ++ ++ switch(OUI_Subtype) ++ { ++ case P2P_NOTICE_OF_ABSENCE: ++ ++ break; ++ ++ case P2P_PRESENCE_REQUEST: ++ ++ process_p2p_presence_req(pwdinfo, pframe, len); ++ ++ break; ++ ++ case P2P_PRESENCE_RESPONSE: ++ ++ break; ++ ++ case P2P_GO_DISC_REQUEST: ++ ++ break; ++ ++ default: ++ break; ++ ++ } ++ } ++ ++#endif //CONFIG_P2P ++ ++ return _SUCCESS; ++ ++} ++ ++unsigned int OnAction(_adapter *padapter, union recv_frame *precv_frame) ++{ ++ int i; ++ unsigned char category; ++ struct action_handler *ptable; ++ unsigned char *frame_body; ++ u8 *pframe = precv_frame->u.hdr.rx_data; ++ ++ frame_body = (unsigned char *)(pframe + sizeof(struct rtw_ieee80211_hdr_3addr)); ++ ++ category = frame_body[0]; ++ ++ for(i = 0; i < sizeof(OnAction_tbl)/sizeof(struct action_handler); i++) ++ { ++ ptable = &OnAction_tbl[i]; ++ ++ if(category == ptable->num) ++ ptable->func(padapter, precv_frame); ++ ++ } ++ ++ return _SUCCESS; ++ ++} ++ ++unsigned int DoReserved(_adapter *padapter, union recv_frame *precv_frame) ++{ ++ u8 *pframe = precv_frame->u.hdr.rx_data; ++ uint len = precv_frame->u.hdr.len; ++ ++ //DBG_871X("rcvd mgt frame(%x, %x)\n", (GetFrameSubType(pframe) >> 4), *(unsigned int *)GetAddr1Ptr(pframe)); ++ return _SUCCESS; ++} ++ ++struct xmit_frame *alloc_mgtxmitframe(struct xmit_priv *pxmitpriv) ++{ ++ struct xmit_frame *pmgntframe; ++ struct xmit_buf *pxmitbuf; ++ ++ if ((pmgntframe = rtw_alloc_xmitframe(pxmitpriv)) == NULL) ++ { ++ DBG_871X("%s, alloc xmitframe fail\n", __FUNCTION__); ++ return NULL; ++ } ++ ++ if ((pxmitbuf = rtw_alloc_xmitbuf_ext(pxmitpriv)) == NULL) ++ { ++ DBG_871X("%s, alloc xmitbuf fail\n", __FUNCTION__); ++ rtw_free_xmitframe_ex(pxmitpriv, pmgntframe); ++ return NULL; ++ } ++ ++ pmgntframe->frame_tag = MGNT_FRAMETAG; ++ ++ pmgntframe->pxmitbuf = pxmitbuf; ++ ++ pmgntframe->buf_addr = pxmitbuf->pbuf; ++ ++ pxmitbuf->priv_data = pmgntframe; ++ ++ return pmgntframe; ++ ++} ++ ++ ++/**************************************************************************** ++ ++Following are some TX fuctions for WiFi MLME ++ ++*****************************************************************************/ ++ ++void update_mgntframe_attrib(_adapter *padapter, struct pkt_attrib *pattrib) ++{ ++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); ++ ++ _rtw_memset((u8 *)(pattrib), 0, sizeof(struct pkt_attrib)); ++ ++ pattrib->hdrlen = 24; ++ pattrib->nr_frags = 1; ++ pattrib->priority = 7; ++ pattrib->mac_id = 0; ++ pattrib->qsel = 0x12; ++ ++ pattrib->pktlen = 0; ++ ++ if(pmlmeext->cur_wireless_mode & WIRELESS_11B) ++ pattrib->raid = 6;//b mode ++ else ++ pattrib->raid = 5;//a/g mode ++ ++ pattrib->encrypt = _NO_PRIVACY_; ++ pattrib->bswenc = _FALSE; ++ ++ pattrib->qos_en = _FALSE; ++ pattrib->ht_en = _FALSE; ++ pattrib->bwmode = HT_CHANNEL_WIDTH_20; ++ pattrib->ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; ++ pattrib->sgi = _FALSE; ++ ++ pattrib->seqnum = pmlmeext->mgnt_seq; ++ ++ pattrib->retry_ctrl = _TRUE; ++ ++} ++ ++void dump_mgntframe(_adapter *padapter, struct xmit_frame *pmgntframe) ++{ ++ if(padapter->bSurpriseRemoved == _TRUE || ++ padapter->bDriverStopped == _TRUE) ++ return; ++ ++ padapter->HalFunc.mgnt_xmit(padapter, pmgntframe); ++} ++ ++//Commented by Kurt ++#ifdef CONFIG_TDLS ++void issue_nulldata_to_TDLS_peer_STA(_adapter *padapter, struct sta_info *ptdls_sta, unsigned int power_mode) ++{ ++ struct xmit_frame *pmgntframe; ++ struct pkt_attrib *pattrib; ++ unsigned char *pframe; ++ struct rtw_ieee80211_hdr *pwlanhdr; ++ unsigned short *fctrl; ++ struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); ++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ ++ if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL) ++ { ++ return; ++ } ++ ++ //update attribute ++ pattrib = &pmgntframe->attrib; ++ update_mgntframe_attrib(padapter, pattrib); ++ ++ _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); ++ ++ pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; ++ pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; ++ ++ fctrl = &(pwlanhdr->frame_ctl); ++ *(fctrl) = 0; ++// SetToDs(fctrl); ++ if (power_mode) ++ { ++ SetPwrMgt(fctrl); ++ } ++ ++ _rtw_memcpy(pwlanhdr->addr1, ptdls_sta->hwaddr, ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr2, myid(&(padapter->eeprompriv)), ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); ++ ++ ptdls_sta->sta_xmitpriv.txseq_tid[pattrib->priority]++; ++ ptdls_sta->sta_xmitpriv.txseq_tid[pattrib->priority] &= 0xFFF; ++ pattrib->seqnum = ptdls_sta->sta_xmitpriv.txseq_tid[pattrib->priority]; ++ SetSeqNum(pwlanhdr, pattrib->seqnum); ++ ++ SetFrameSubType(pframe, WIFI_DATA_NULL); ++ ++ pframe += sizeof(struct rtw_ieee80211_hdr_3addr); ++ pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); ++ ++ pattrib->last_txcmdsz = pattrib->pktlen; ++ dump_mgntframe(padapter, pmgntframe); ++ ++ return; ++} ++ ++s32 update_tdls_attrib(_adapter *padapter, struct pkt_attrib *pattrib) ++{ ++ ++ struct sta_info *psta = NULL; ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ struct security_priv *psecuritypriv = &padapter->securitypriv; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct qos_priv *pqospriv= &pmlmepriv->qospriv; ++ ++ s32 res=_SUCCESS; ++ sint bmcast; ++ ++ bmcast = IS_MCAST(pattrib->ra); ++ ++ psta = rtw_get_stainfo(pstapriv, pattrib->ra); ++ if (psta == NULL) { ++ res =_FAIL; ++ goto exit; ++ } ++ ++ pattrib->mac_id = psta->mac_id; ++ ++ pattrib->psta = psta; ++ ++ pattrib->ack_policy = 0; ++ // get ether_hdr_len ++ pattrib->pkt_hdrlen = ETH_HLEN;//(pattrib->ether_type == 0x8100) ? (14 + 4 ): 14; //vlan tag ++ ++ if (pqospriv->qos_option && psta->qos_option) { ++ pattrib->priority = 1; //tdls management frame should be AC_BK ++ pattrib->hdrlen = WLAN_HDR_A3_QOS_LEN; ++ pattrib->subtype = WIFI_QOS_DATA_TYPE; ++ } else { ++ pattrib->hdrlen = WLAN_HDR_A3_LEN; ++ pattrib->subtype = WIFI_DATA_TYPE; ++ pattrib->priority = 0; ++ } ++ ++ if (psta->ieee8021x_blocked == _TRUE) ++ { ++ pattrib->encrypt = 0; ++ } ++ else ++ { ++ GET_ENCRY_ALGO(psecuritypriv, psta, pattrib->encrypt, bmcast); ++ ++ switch(psecuritypriv->dot11AuthAlgrthm) ++ { ++ case dot11AuthAlgrthm_Open: ++ case dot11AuthAlgrthm_Shared: ++ case dot11AuthAlgrthm_Auto: ++ pattrib->key_idx = (u8)psecuritypriv->dot11PrivacyKeyIndex; ++ break; ++ case dot11AuthAlgrthm_8021X: ++ pattrib->key_idx = 0; ++ break; ++ default: ++ pattrib->key_idx = 0; ++ break; ++ } ++ } ++ ++ switch (pattrib->encrypt) ++ { ++ case _WEP40_: ++ case _WEP104_: ++ pattrib->iv_len = 4; ++ pattrib->icv_len = 4; ++ break; ++ case _TKIP_: ++ pattrib->iv_len = 8; ++ pattrib->icv_len = 4; ++ if(padapter->securitypriv.busetkipkey==_FAIL) ++ { ++ res =_FAIL; ++ goto exit; ++ } ++ break; ++ case _AES_: ++ pattrib->iv_len = 8; ++ pattrib->icv_len = 8; ++ break; ++ default: ++ pattrib->iv_len = 0; ++ pattrib->icv_len = 0; ++ break; ++ } ++ ++ if (pattrib->encrypt && ++ ((padapter->securitypriv.sw_encrypt == _TRUE) || (psecuritypriv->hw_decrypted == _FALSE))) ++ { ++ pattrib->bswenc = _TRUE; ++ } else { ++ pattrib->bswenc = _FALSE; ++ } ++ ++ //qos_en, ht_en, init rate, ,bw, ch_offset, sgi ++ pattrib->qos_en = psta->qos_option; ++ pattrib->ht_en = psta->htpriv.ht_option; ++ pattrib->raid = psta->raid; ++ pattrib->bwmode = psta->htpriv.bwmode; ++ pattrib->ch_offset = psta->htpriv.ch_offset; ++ pattrib->sgi= psta->htpriv.sgi; ++ pattrib->ampdu_en = _FALSE; ++ ++ if(pattrib->ht_en && psta->htpriv.ampdu_enable) ++ { ++ if(psta->htpriv.agg_enable_bitmap & BIT(pattrib->priority)) ++ pattrib->ampdu_en = _TRUE; ++ } ++ ++exit: ++ ++ return res; ++} ++ ++void free_tdls_sta(_adapter *padapter, struct sta_info *ptdls_sta) ++{ ++ struct tdls_info *ptdlsinfo = &padapter->tdlsinfo; ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ _irqL irqL; ++ ++ //free peer sta_info ++ DBG_8192C("Free sta_info\n"); ++ _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL); ++ ptdlsinfo->sta_cnt--; ++ _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL); ++ if( ptdlsinfo->sta_cnt < (NUM_STA - 1 ) ) ++ { ++ ptdlsinfo->sta_maximum = _FALSE; ++ _rtw_memset( &ptdlsinfo->ss_record, 0x00, sizeof(struct tdls_ss_record) ); ++ } ++ //ready to clear cam ++ if(ptdls_sta->cam_entry!=0){ ++ ptdlsinfo->cam_entry_to_clear=ptdls_sta->cam_entry; ++ rtw_setstakey_cmd(padapter, (u8 *)ptdls_sta, _TRUE); ++ } ++ ++ if(ptdlsinfo->sta_cnt==0){ ++ rtw_tdls_cmd(padapter, myid(&(padapter->eeprompriv)), TDLS_RS_RCR); ++ ptdlsinfo->setup_state=UN_TDLS_STATE; ++ } ++ ++ rtw_free_stainfo(padapter, ptdls_sta); ++ ++} ++ ++void issue_tdls_setup_req(_adapter *padapter, u8 *mac_addr) ++{ ++ struct tdls_info *ptdlsinfo = &padapter->tdlsinfo; ++ struct xmit_frame *pmgntframe; ++ struct pkt_attrib *pattrib; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ struct sta_info *ptdls_sta= NULL; ++ _irqL irqL; ++ static u8 dialogtoken = 0; ++ u32 timeout_interval= TPK_RESEND_COUNT * 1000; //retry timer should set at least 301 sec, using TPK_count counting 301 times. ++ ++ if(ptdlsinfo->ap_prohibited == _TRUE) ++ goto exit; ++ ++ if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL) ++ { ++ return; ++ } ++ ++ //update attribute ++ pattrib = &pmgntframe->attrib; ++ ++ pmgntframe->frame_tag = DATA_FRAMETAG; ++ pattrib->ether_type = 0x890d; ++ pattrib->pctrl =0; ++ ++ _rtw_memcpy(pattrib->dst, mac_addr, ETH_ALEN); ++ _rtw_memcpy(pattrib->src, myid(&(padapter->eeprompriv)), ETH_ALEN); ++ ++ _rtw_memcpy(pattrib->ra, get_bssid(pmlmepriv), ETH_ALEN); ++ _rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN); ++ ++ update_tdls_attrib(padapter, pattrib); ++ ++ //init peer sta_info ++ ptdls_sta = rtw_get_stainfo(pstapriv, mac_addr); ++ if(ptdls_sta==NULL) ++ { ++ ptdls_sta = rtw_alloc_stainfo(pstapriv, mac_addr); ++ if(ptdls_sta) ++ { ++ _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL); ++ ptdlsinfo->sta_cnt++; ++ _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL); ++ if( ptdlsinfo->sta_cnt == (NUM_STA - 1) ) ++ { ++ ptdlsinfo->sta_maximum = _TRUE; ++ } ++ } ++ else ++ { ++ rtw_free_xmitbuf(pxmitpriv,pmgntframe->pxmitbuf); ++ rtw_free_xmitframe_ex(pxmitpriv, pmgntframe); ++ goto exit; ++ } ++ } ++ ++ if(ptdls_sta){ ++ ptdls_sta->tdls_sta_state |= TDLS_RESPONDER_STATE; ++ //for tdls; ptdls_sta->aid is used to fill dialogtoken ++ ptdls_sta->dialog = dialogtoken; ++ dialogtoken = (dialogtoken+1)%256; ++ ptdls_sta->TDLS_PeerKey_Lifetime = timeout_interval; ++ _set_timer( &ptdls_sta->handshake_timer, TDLS_HANDSHAKE_TIME ); ++ } ++ ++ pattrib->qsel=pattrib->priority; ++ if(rtw_xmit_tdls_coalesce(padapter, pmgntframe, TDLS_SETUP_REQUEST) !=_SUCCESS ){ ++ rtw_free_xmitbuf(pxmitpriv,pmgntframe->pxmitbuf); ++ rtw_free_xmitframe_ex(pxmitpriv, pmgntframe); ++ goto exit; ++ } ++ rtw_dump_xframe(padapter, pmgntframe); ++ ++exit: ++ ++ return; ++} ++ ++void issue_tdls_teardown(_adapter *padapter, u8 *mac_addr) ++{ ++ struct xmit_frame *pmgntframe; ++ struct pkt_attrib *pattrib; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ struct sta_info *ptdls_sta=NULL; ++ _irqL irqL; ++ ++ ptdls_sta = rtw_get_stainfo(pstapriv, mac_addr); ++ if(ptdls_sta==NULL){ ++ DBG_8192C("issue tdls teardown unsuccessful\n"); ++ return; ++ }else{ ++ ptdls_sta->tdls_sta_state=UN_TDLS_STATE; ++ } ++ ++ if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL) ++ { ++ return; ++ } ++ ++ //update attribute ++ pattrib = &pmgntframe->attrib; ++ ++ pmgntframe->frame_tag = DATA_FRAMETAG; ++ pattrib->ether_type = 0x890d; ++ pattrib->pctrl =0; ++ ++ _rtw_memcpy(pattrib->dst, mac_addr, ETH_ALEN); ++ _rtw_memcpy(pattrib->src, myid(&(padapter->eeprompriv)), ETH_ALEN); ++ ++ _rtw_memcpy(pattrib->ra, get_bssid(pmlmepriv), ETH_ALEN); ++ _rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN); ++ ++ update_tdls_attrib(padapter, pattrib); ++ pattrib->qsel=pattrib->priority; ++ if (rtw_xmit_tdls_coalesce(padapter, pmgntframe, TDLS_TEARDOWN) != _SUCCESS) { ++ rtw_free_xmitbuf(pxmitpriv, pmgntframe->pxmitbuf); ++ rtw_free_xmitframe_ex(pxmitpriv, pmgntframe); ++ goto exit; ++ } ++ rtw_dump_xframe(padapter, pmgntframe); ++ ++ if(ptdls_sta->tdls_sta_state & TDLS_CH_SWITCH_ON_STATE){ ++ ptdls_sta->option =3; ++ rtw_tdls_cmd(padapter, ptdls_sta->hwaddr, TDLS_CS_OFF); ++ } ++ ++ if( ptdls_sta->timer_flag == 1 ) ++ { ++ _enter_critical_bh(&(padapter->tdlsinfo.hdl_lock), &irqL); ++ ptdls_sta->timer_flag = 2; ++ _exit_critical_bh(&(padapter->tdlsinfo.hdl_lock), &irqL); ++ } ++ else ++ rtw_tdls_cmd(padapter, mac_addr, TDLS_FREE_STA ); ++ ++ ++exit: ++ ++ return; ++} ++ ++void issue_tdls_dis_req(_adapter *padapter, u8 *mac_addr) ++{ ++ struct xmit_frame *pmgntframe; ++ struct pkt_attrib *pattrib; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); ++ u8 baddr[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; ++ ++ if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL) ++ { ++ return; ++ } ++ ++ //update attribute ++ pattrib = &pmgntframe->attrib; ++ ++ pmgntframe->frame_tag = DATA_FRAMETAG; ++ pattrib->ether_type = 0x890d; ++ pattrib->pctrl =0; ++ ++ if(mac_addr == NULL) ++ _rtw_memcpy(pattrib->dst, baddr, ETH_ALEN); ++ else ++ _rtw_memcpy(pattrib->dst, mac_addr, ETH_ALEN); ++ ++ _rtw_memcpy(pattrib->src, myid(&(padapter->eeprompriv)), ETH_ALEN); ++ ++ _rtw_memcpy(pattrib->ra, get_bssid(pmlmepriv), ETH_ALEN); ++ _rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN); ++ ++ update_tdls_attrib(padapter, pattrib); ++ pattrib->qsel=pattrib->priority; ++ if (rtw_xmit_tdls_coalesce(padapter, pmgntframe, TDLS_DISCOVERY_REQUEST) != _SUCCESS) { ++ rtw_free_xmitbuf(pxmitpriv, pmgntframe->pxmitbuf); ++ rtw_free_xmitframe_ex(pxmitpriv, pmgntframe); ++ goto exit; ++ } ++ rtw_dump_xframe(padapter, pmgntframe); ++ DBG_8192C("issue tdls dis req\n"); ++ ++exit: ++ ++ return; ++} ++ ++void issue_tdls_setup_rsp(_adapter *padapter, union recv_frame *precv_frame) ++{ ++ struct xmit_frame *pmgntframe; ++ struct pkt_attrib *pattrib; ++ struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); ++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ struct rx_pkt_attrib *rx_pkt_pattrib = &precv_frame->u.hdr.attrib; ++ _irqL irqL; ++ ++ if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL) ++ { ++ return; ++ } ++ ++ //update attribute ++ pattrib = &pmgntframe->attrib; ++ ++ pmgntframe->frame_tag = DATA_FRAMETAG; ++ pattrib->ether_type = 0x890d; ++ pattrib->pctrl =0; ++ ++ _rtw_memcpy(pattrib->dst, rx_pkt_pattrib->src, ETH_ALEN); ++ _rtw_memcpy(pattrib->src, myid(&(padapter->eeprompriv)), ETH_ALEN); ++ ++ _rtw_memcpy(pattrib->ra, rx_pkt_pattrib->bssid, ETH_ALEN); ++ _rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN); ++ ++ update_tdls_attrib(padapter, pattrib); ++ pattrib->qsel=pattrib->priority; ++ if (rtw_xmit_tdls_coalesce(padapter, pmgntframe, TDLS_SETUP_RESPONSE) != _SUCCESS) { ++ rtw_free_xmitbuf(pxmitpriv, pmgntframe->pxmitbuf); ++ rtw_free_xmitframe_ex(pxmitpriv, pmgntframe); ++ goto exit; ++ } ++ rtw_dump_xframe(padapter, pmgntframe); ++ ++exit: ++ ++ return; ++ ++} ++ ++void issue_tdls_setup_cfm(_adapter *padapter, union recv_frame *precv_frame) ++{ ++ struct tdls_info *ptdlsinfo = &padapter->tdlsinfo; ++ struct xmit_frame *pmgntframe; ++ struct pkt_attrib *pattrib; ++ struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); ++ struct sta_info *ptdls_sta=NULL; ++ _irqL irqL; ++ ++ struct rx_pkt_attrib *rx_pkt_pattrib = & precv_frame->u.hdr.attrib; ++ ++ if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL) ++ { ++ return; ++ } ++ ++ //update attribute ++ pattrib = &pmgntframe->attrib; ++ ++ pmgntframe->frame_tag = DATA_FRAMETAG; ++ pattrib->ether_type = 0x890d; ++ pattrib->pctrl =0; ++ ++ _rtw_memcpy(pattrib->dst, rx_pkt_pattrib->src, ETH_ALEN); ++ _rtw_memcpy(pattrib->src, myid(&(padapter->eeprompriv)), ETH_ALEN); ++ ++ _rtw_memcpy(pattrib->ra, rx_pkt_pattrib->bssid, ETH_ALEN); ++ _rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN); ++ ++ update_tdls_attrib(padapter, pattrib); ++ pattrib->qsel=pattrib->priority; ++ if (rtw_xmit_tdls_coalesce(padapter, pmgntframe, TDLS_SETUP_CONFIRM) != _SUCCESS) { ++ rtw_free_xmitbuf(pxmitpriv, pmgntframe->pxmitbuf); ++ rtw_free_xmitframe_ex(pxmitpriv, pmgntframe); ++ goto exit; ++ } ++ ++ rtw_dump_xframe(padapter, pmgntframe); ++ ++exit: ++ ++ return; ++ ++} ++ ++//TDLS Discovery Response frame is a management action frame ++void issue_tdls_dis_rsp(_adapter *padapter, union recv_frame *precv_frame, u8 dialog) ++{ ++ struct xmit_frame *pmgntframe; ++ struct pkt_attrib *pattrib; ++ unsigned char *pframe; ++ struct rtw_ieee80211_hdr *pwlanhdr; ++ unsigned short *fctrl; ++ struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); ++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); ++ ++ struct rx_pkt_attrib *rx_pkt_pattrib = &precv_frame->u.hdr.attrib; ++ ++ if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL) ++ { ++ return; ++ } ++ ++ //update attribute ++ pattrib = &pmgntframe->attrib; ++ update_mgntframe_attrib(padapter, pattrib); ++ ++ _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); ++ ++ pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; ++ pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; ++ ++ fctrl = &(pwlanhdr->frame_ctl); ++ *(fctrl) = 0; ++ ++ // unicast probe request frame ++ _rtw_memcpy(pwlanhdr->addr1, rx_pkt_pattrib->src, ETH_ALEN); ++ _rtw_memcpy(pattrib->dst, pwlanhdr->addr1, ETH_ALEN); ++ ++ _rtw_memcpy(pwlanhdr->addr2, myid(&(padapter->eeprompriv)), ETH_ALEN); ++ _rtw_memcpy(pattrib->src, pwlanhdr->addr2, ETH_ALEN); ++ ++ _rtw_memcpy(pwlanhdr->addr3, rx_pkt_pattrib->bssid, ETH_ALEN); ++ _rtw_memcpy(pattrib->ra, pwlanhdr->addr3, ETH_ALEN); ++ ++ SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); ++ pmlmeext->mgnt_seq++; ++ SetFrameSubType(pframe, WIFI_ACTION); ++ ++ pframe += sizeof (struct rtw_ieee80211_hdr_3addr); ++ pattrib->pktlen = sizeof (struct rtw_ieee80211_hdr_3addr); ++ ++ rtw_tdls_dis_rsp_fr(padapter, pmgntframe, pframe, dialog); ++ ++ pattrib->nr_frags = 1; ++ pattrib->last_txcmdsz = pattrib->pktlen; ++ ++ dump_mgntframe(padapter, pmgntframe); ++ ++ return; ++} ++ ++void issue_tdls_peer_traffic_indication(_adapter *padapter, struct sta_info *ptdls_sta) ++{ ++ struct xmit_frame *pmgntframe; ++ struct pkt_attrib *pattrib; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); ++ ++ static u8 dialogtoken=0; ++ ++ if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL) ++ { ++ return; ++ } ++ ++ //update attribute ++ pattrib = &pmgntframe->attrib; ++ ++ pmgntframe->frame_tag = DATA_FRAMETAG; ++ pattrib->ether_type = 0x890d; ++ pattrib->pctrl =0; ++ ++ _rtw_memcpy(pattrib->dst, ptdls_sta->hwaddr, ETH_ALEN); ++ _rtw_memcpy(pattrib->src, myid(&(padapter->eeprompriv)), ETH_ALEN); ++ ++ _rtw_memcpy(pattrib->ra, get_bssid(pmlmepriv), ETH_ALEN); ++ _rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN); ++ ++ //for tdls; pattrib->nr_frags is used to fill dialogtoken ++ ptdls_sta->dialog = dialogtoken; ++ dialogtoken = (dialogtoken+1)%256; ++ //PTI frame's priority should be AC_VO ++ pattrib->priority = 7; ++ ++ update_tdls_attrib(padapter, pattrib); ++ pattrib->qsel=pattrib->priority; ++ if (rtw_xmit_tdls_coalesce(padapter, pmgntframe, TDLS_PEER_TRAFFIC_INDICATION) != _SUCCESS) { ++ rtw_free_xmitbuf(pxmitpriv, pmgntframe->pxmitbuf); ++ rtw_free_xmitframe_ex(pxmitpriv, pmgntframe); ++ goto exit; ++ } ++ rtw_dump_xframe(padapter, pmgntframe); ++ ++exit: ++ ++ return; ++} ++ ++void issue_tdls_ch_switch_req(_adapter *padapter, u8 *mac_addr) ++{ ++ struct xmit_frame *pmgntframe; ++ struct pkt_attrib *pattrib; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); ++ ++ if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL) ++ { ++ return; ++ } ++ ++ //update attribute ++ pattrib = &pmgntframe->attrib; ++ ++ pmgntframe->frame_tag = DATA_FRAMETAG; ++ pattrib->ether_type = 0x890d; ++ pattrib->pctrl =0; ++ ++ _rtw_memcpy(pattrib->dst, mac_addr, ETH_ALEN); ++ _rtw_memcpy(pattrib->src, myid(&(padapter->eeprompriv)), ETH_ALEN); ++ ++ _rtw_memcpy(pattrib->ra, get_bssid(pmlmepriv), ETH_ALEN); ++ _rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN); ++ ++ update_tdls_attrib(padapter, pattrib); ++ ++ pattrib->qsel=pattrib->priority; ++ if(rtw_xmit_tdls_coalesce(padapter, pmgntframe, TDLS_CHANNEL_SWITCH_REQUEST) !=_SUCCESS ){ ++ rtw_free_xmitbuf(pxmitpriv,pmgntframe->pxmitbuf); ++ rtw_free_xmitframe_ex(pxmitpriv, pmgntframe); ++ goto exit; ++ } ++ rtw_dump_xframe(padapter, pmgntframe); ++ ++exit: ++ ++ return; ++} ++ ++void issue_tdls_ch_switch_rsp(_adapter *padapter, u8 *mac_addr) ++{ ++ struct xmit_frame *pmgntframe; ++ struct pkt_attrib *pattrib; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); ++ ++ _irqL irqL; ++ ++ if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL) ++ { ++ return; ++ } ++ ++ //update attribute ++ pattrib = &pmgntframe->attrib; ++ ++ pmgntframe->frame_tag = DATA_FRAMETAG; ++ pattrib->ether_type = 0x890d; ++ pattrib->pctrl =0; ++ ++ _rtw_memcpy(pattrib->dst, mac_addr, ETH_ALEN); ++ _rtw_memcpy(pattrib->src, myid(&(padapter->eeprompriv)), ETH_ALEN); ++ ++ _rtw_memcpy(pattrib->ra, get_bssid(pmlmepriv), ETH_ALEN); ++ _rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN); ++ ++ update_tdls_attrib(padapter, pattrib); ++ ++ pattrib->qsel=pattrib->priority; ++/* ++ _enter_critical_bh(&pxmitpriv->lock, &irqL); ++ if(xmitframe_enqueue_for_tdls_sleeping_sta(padapter, pmgntframe)==_TRUE){ ++ _exit_critical_bh(&pxmitpriv->lock, &irqL); ++ return _FALSE; ++ } ++*/ ++ if(rtw_xmit_tdls_coalesce(padapter, pmgntframe, TDLS_CHANNEL_SWITCH_RESPONSE) !=_SUCCESS ){ ++ rtw_free_xmitbuf(pxmitpriv,pmgntframe->pxmitbuf); ++ rtw_free_xmitframe_ex(pxmitpriv, pmgntframe); ++ goto exit; ++ } ++ rtw_dump_xframe(padapter, pmgntframe); ++ ++exit: ++ ++ return; ++} ++ ++sint On_TDLS_Dis_Rsp(_adapter *adapter, union recv_frame *precv_frame) ++{ ++ struct sta_info *ptdls_sta = NULL; ++ struct recv_priv *precvpriv = &(adapter->recvpriv); ++ u8 *ptr = precv_frame->u.hdr.rx_data, *psa; ++ struct rx_pkt_attrib *pattrib = &(precv_frame->u.hdr.attrib); ++ struct tdls_info *ptdlsinfo = &(adapter->tdlsinfo); ++ u8 empty_addr[ETH_ALEN] = { 0x00 }; ++ ++ psa = get_sa(ptr); ++ ptdls_sta = rtw_get_stainfo(&(adapter->stapriv), psa); ++ ++ if(ptdls_sta != NULL) ++ { ++ ptdls_sta->tdls_sta_state |= TDLS_ALIVE_STATE; ++ ++ //Record the tdls sta with lowest signal strength ++ if( (ptdlsinfo->sta_maximum == _TRUE) && (ptdls_sta->alive_count >= 1) ) ++ { ++ printk("%s %d\n", __FUNCTION__, __LINE__); ++ if( _rtw_memcmp(ptdlsinfo->ss_record.macaddr, empty_addr, ETH_ALEN) ) ++ { ++ printk("%s %d\n", __FUNCTION__, __LINE__); ++ _rtw_memcpy(ptdlsinfo->ss_record.macaddr, psa, ETH_ALEN); ++ ptdlsinfo->ss_record.signal_strength = pattrib->signal_strength; ++ } ++ else ++ { ++ printk("%s %d\n", __FUNCTION__, __LINE__); ++ if( ptdlsinfo->ss_record.signal_strength < pattrib->signal_strength ) ++ { ++ printk("%s %d\n", __FUNCTION__, __LINE__); ++ _rtw_memcpy(ptdlsinfo->ss_record.macaddr, psa, ETH_ALEN); ++ ptdlsinfo->ss_record.signal_strength = pattrib->signal_strength; ++ } ++ } ++ } ++ ++ } ++ else ++ { ++ if( ptdlsinfo->sta_maximum == _TRUE) ++ { ++ printk("%s %d\n", __FUNCTION__, __LINE__); ++ if( _rtw_memcmp( ptdlsinfo->ss_record.macaddr, empty_addr, ETH_ALEN ) ) ++ { ++ //All traffics are busy, do not set up another direct link. ++ printk("%s %d\n", __FUNCTION__, __LINE__); ++ return _FAIL; ++ } ++ else ++ { ++ if( pattrib->signal_strength > ptdlsinfo->ss_record.signal_strength ) ++ { ++ printk("%s %d\n", __FUNCTION__, __LINE__); ++ issue_tdls_teardown(adapter, ptdlsinfo->ss_record.macaddr); ++ } ++ else ++ { ++ printk("%s %d\n", __FUNCTION__, __LINE__); ++ return _FAIL; ++ } ++ } ++ } ++ ++ if( pattrib->signal_strength + TDLS_SIGNAL_THRESH >= precvpriv->signal_strength ) ++ { ++ issue_tdls_setup_req(adapter, psa); ++ } ++ } ++ ++ return _FAIL; ++} ++ ++#endif ++ ++int update_hidden_ssid(u8 *ies, u32 ies_len, u8 hidden_ssid_mode) ++{ ++ u8 *ssid_ie; ++ sint ssid_len_ori; ++ int len_diff = 0; ++ ++ ssid_ie = rtw_get_ie(ies, WLAN_EID_SSID, &ssid_len_ori, ies_len); ++ ++ //DBG_871X("%s hidden_ssid_mode:%u, ssid_ie:%p, ssid_len_ori:%d\n", __FUNCTION__, hidden_ssid_mode, ssid_ie, ssid_len_ori); ++ ++ if(ssid_ie && ssid_len_ori>0) ++ { ++ switch(hidden_ssid_mode) ++ { ++ case 1: ++ { ++ u8 *next_ie = ssid_ie + 2 + ssid_len_ori; ++ u32 remain_len = 0; ++ ++ remain_len = ies_len -(next_ie-ies); ++ ++ ssid_ie[1] = 0; ++ _rtw_memcpy(ssid_ie+2, next_ie, remain_len); ++ len_diff -= ssid_len_ori; ++ ++ break; ++ } ++ case 2: ++ _rtw_memset(&ssid_ie[2], 0, ssid_len_ori); ++ break; ++ default: ++ break; ++ } ++ } ++ ++ return len_diff; ++} ++ ++void issue_beacon(_adapter *padapter) ++{ ++ _irqL irqL; ++ struct xmit_frame *pmgntframe; ++ struct pkt_attrib *pattrib; ++ unsigned char *pframe; ++ struct rtw_ieee80211_hdr *pwlanhdr; ++ unsigned short *fctrl; ++ unsigned int rate_len; ++ struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network); ++ u8 bc_addr[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; ++#ifdef CONFIG_P2P ++ struct wifidirect_info *pwdinfo = &(padapter->wdinfo); ++#endif //CONFIG_P2P ++ ++ ++ //DBG_871X("%s\n", __FUNCTION__); ++ ++ if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL) ++ { ++ DBG_871X("%s, alloc mgnt frame fail\n", __FUNCTION__); ++ return; ++ } ++ ++ _enter_critical_bh(&pmlmepriv->bcn_update_lock, &irqL); ++ ++ //update attribute ++ pattrib = &pmgntframe->attrib; ++ update_mgntframe_attrib(padapter, pattrib); ++ pattrib->qsel = 0x10; ++ ++ _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); ++ ++ pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; ++ pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; ++ ++ ++ fctrl = &(pwlanhdr->frame_ctl); ++ *(fctrl) = 0; ++ ++ _rtw_memcpy(pwlanhdr->addr1, bc_addr, ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr2, myid(&(padapter->eeprompriv)), ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(cur_network), ETH_ALEN); ++ ++ SetSeqNum(pwlanhdr, 0/*pmlmeext->mgnt_seq*/); ++ //pmlmeext->mgnt_seq++; ++ SetFrameSubType(pframe, WIFI_BEACON); ++ ++ pframe += sizeof(struct rtw_ieee80211_hdr_3addr); ++ pattrib->pktlen = sizeof (struct rtw_ieee80211_hdr_3addr); ++ ++ if( (pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE) ++ { ++ //DBG_871X("ie len=%d\n", cur_network->IELength); ++#ifdef CONFIG_P2P ++ // for P2P : Primary Device Type & Device Name ++ u32 wpsielen=0, insert_len=0; ++ u8 *wpsie=NULL; ++ wpsie = rtw_get_wps_ie(cur_network->IEs+_FIXED_IE_LENGTH_, cur_network->IELength-_FIXED_IE_LENGTH_, NULL, &wpsielen); ++ ++ if(rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO) && wpsie && wpsielen>0) ++ { ++ uint wps_offset, remainder_ielen; ++ u8 *premainder_ie, *pframe_wscie; ++ ++ wps_offset = (uint)(wpsie - cur_network->IEs); ++ ++ premainder_ie = wpsie + wpsielen; ++ ++ remainder_ielen = cur_network->IELength - wps_offset - wpsielen; ++ ++#ifdef CONFIG_IOCTL_CFG80211 ++ if(wdev_to_priv(padapter->rtw_wdev)->p2p_enabled) ++ { ++ if(pmlmepriv->wps_beacon_ie && pmlmepriv->wps_beacon_ie_len>0) ++ { ++ _rtw_memcpy(pframe, cur_network->IEs, wps_offset); ++ pframe += wps_offset; ++ pattrib->pktlen += wps_offset; ++ ++ _rtw_memcpy(pframe, pmlmepriv->wps_beacon_ie, pmlmepriv->wps_beacon_ie_len); ++ ++ pframe += pmlmepriv->wps_beacon_ie_len; ++ pattrib->pktlen += pmlmepriv->wps_beacon_ie_len; ++ ++ //copy remainder_ie to pframe ++ _rtw_memcpy(pframe, premainder_ie, remainder_ielen); ++ pframe += remainder_ielen; ++ pattrib->pktlen += remainder_ielen; ++ ++ } ++ else ++ { ++ _rtw_memcpy(pframe, cur_network->IEs, cur_network->IELength); ++ pframe += cur_network->IELength; ++ pattrib->pktlen += cur_network->IELength; ++ } ++ } ++ else ++#endif //CONFIG_IOCTL_CFG80211 ++ { ++ ++ pframe_wscie = pframe + wps_offset; ++ _rtw_memcpy(pframe, cur_network->IEs, wps_offset+wpsielen); ++ pframe += (wps_offset + wpsielen); ++ pattrib->pktlen += (wps_offset + wpsielen); ++ ++ //now pframe is end of wsc ie, insert Primary Device Type & Device Name ++ // Primary Device Type ++ // Type: ++ *(u16*) ( pframe + insert_len) = cpu_to_be16( WPS_ATTR_PRIMARY_DEV_TYPE ); ++ insert_len += 2; ++ ++ // Length: ++ *(u16*) ( pframe + insert_len ) = cpu_to_be16( 0x0008 ); ++ insert_len += 2; ++ ++ // Value: ++ // Category ID ++ *(u16*) ( pframe + insert_len ) = cpu_to_be16( WPS_PDT_CID_RTK_WIDI ); ++ insert_len += 2; ++ ++ // OUI ++ *(u32*) ( pframe + insert_len ) = cpu_to_be32( WPSOUI ); ++ insert_len += 4; ++ ++ // Sub Category ID ++ *(u16*) ( pframe + insert_len ) = cpu_to_be16( WPS_PDT_SCID_RTK_DMP ); ++ insert_len += 2; ++ ++ ++ // Device Name ++ // Type: ++ *(u16*) ( pframe + insert_len ) = cpu_to_be16( WPS_ATTR_DEVICE_NAME ); ++ insert_len += 2; ++ ++ // Length: ++ *(u16*) ( pframe + insert_len ) = cpu_to_be16( pwdinfo->device_name_len ); ++ insert_len += 2; ++ ++ // Value: ++ _rtw_memcpy( pframe + insert_len, pwdinfo->device_name, pwdinfo->device_name_len ); ++ insert_len += pwdinfo->device_name_len; ++ ++ ++ //update wsc ie length ++ *(pframe_wscie+1) = (wpsielen -2) + insert_len; ++ ++ //pframe move to end ++ pframe+=insert_len; ++ pattrib->pktlen += insert_len; ++ ++ //copy remainder_ie to pframe ++ _rtw_memcpy(pframe, premainder_ie, remainder_ielen); ++ pframe += remainder_ielen; ++ pattrib->pktlen += remainder_ielen; ++ } ++ ++ } ++ else ++#endif //CONFIG_P2P ++ { ++ int len_diff; ++ _rtw_memcpy(pframe, cur_network->IEs, cur_network->IELength); ++ len_diff = update_hidden_ssid( ++ pframe+_BEACON_IE_OFFSET_ ++ , cur_network->IELength-_BEACON_IE_OFFSET_ ++ , pmlmeinfo->hidden_ssid_mode ++ ); ++ pframe += (cur_network->IELength+len_diff); ++ pattrib->pktlen += (cur_network->IELength+len_diff); ++ } ++ ++#ifdef CONFIG_P2P ++ if(rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) ++ { ++ u32 len; ++#ifdef CONFIG_IOCTL_CFG80211 ++ if(wdev_to_priv(padapter->rtw_wdev)->p2p_enabled) ++ { ++ len = pmlmepriv->p2p_beacon_ie_len; ++ if(pmlmepriv->p2p_beacon_ie && len>0) ++ _rtw_memcpy(pframe, pmlmepriv->p2p_beacon_ie, len); ++ } ++ else ++#endif //CONFIG_IOCTL_CFG80211 ++ { ++ len = build_beacon_p2p_ie(pwdinfo, pframe); ++ } ++ ++ ++ pframe += len; ++ pattrib->pktlen += len; ++#ifdef CONFIG_WFD ++ len = build_beacon_wfd_ie( pwdinfo, pframe ); ++ pframe += len; ++ pattrib->pktlen += len; ++#endif //CONFIG_WFD ++ } ++#endif //CONFIG_P2P ++ ++ goto _issue_bcn; ++ ++ } ++ ++ //below for ad-hoc mode ++ ++ //timestamp will be inserted by hardware ++ pframe += 8; ++ pattrib->pktlen += 8; ++ ++ // beacon interval: 2 bytes ++ ++ _rtw_memcpy(pframe, (unsigned char *)(rtw_get_beacon_interval_from_ie(cur_network->IEs)), 2); ++ ++ pframe += 2; ++ pattrib->pktlen += 2; ++ ++ // capability info: 2 bytes ++ ++ _rtw_memcpy(pframe, (unsigned char *)(rtw_get_capability_from_ie(cur_network->IEs)), 2); ++ ++ pframe += 2; ++ pattrib->pktlen += 2; ++ ++ // SSID ++ pframe = rtw_set_ie(pframe, _SSID_IE_, cur_network->Ssid.SsidLength, cur_network->Ssid.Ssid, &pattrib->pktlen); ++ ++ // supported rates... ++ rate_len = rtw_get_rateset_len(cur_network->SupportedRates); ++ pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_, ((rate_len > 8)? 8: rate_len), cur_network->SupportedRates, &pattrib->pktlen); ++ ++ // DS parameter set ++ pframe = rtw_set_ie(pframe, _DSSET_IE_, 1, (unsigned char *)&(cur_network->Configuration.DSConfig), &pattrib->pktlen); ++ ++ //if( (pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE) ++ { ++ u8 erpinfo=0; ++ u32 ATIMWindow; ++ // IBSS Parameter Set... ++ //ATIMWindow = cur->Configuration.ATIMWindow; ++ ATIMWindow = 0; ++ pframe = rtw_set_ie(pframe, _IBSS_PARA_IE_, 2, (unsigned char *)(&ATIMWindow), &pattrib->pktlen); ++ ++ //ERP IE ++ pframe = rtw_set_ie(pframe, _ERPINFO_IE_, 1, &erpinfo, &pattrib->pktlen); ++ } ++ ++ ++ // EXTERNDED SUPPORTED RATE ++ if (rate_len > 8) ++ { ++ pframe = rtw_set_ie(pframe, _EXT_SUPPORTEDRATES_IE_, (rate_len - 8), (cur_network->SupportedRates + 8), &pattrib->pktlen); ++ } ++ ++ ++ //todo:HT for adhoc ++ ++_issue_bcn: ++ ++ pmlmepriv->update_bcn = _FALSE; ++ ++ _exit_critical_bh(&pmlmepriv->bcn_update_lock, &irqL); ++ ++ if ((pattrib->pktlen + TXDESC_SIZE) > 512) ++ { ++ DBG_871X("beacon frame too large\n"); ++ return; ++ } ++ ++ pattrib->last_txcmdsz = pattrib->pktlen; ++ ++ //DBG_871X("issue bcn_sz=%d\n", pattrib->last_txcmdsz); ++ ++ dump_mgntframe(padapter, pmgntframe); ++ ++} ++ ++void issue_probersp(_adapter *padapter, unsigned char *da, u8 is_valid_p2p_probereq) ++{ ++ u8 *pwps_ie; ++ uint wps_ielen; ++ struct xmit_frame *pmgntframe; ++ struct pkt_attrib *pattrib; ++ unsigned char *pframe; ++ struct rtw_ieee80211_hdr *pwlanhdr; ++ unsigned short *fctrl; ++ unsigned char *mac, *bssid; ++ struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network); ++ unsigned int rate_len; ++#ifdef CONFIG_P2P ++ struct wifidirect_info *pwdinfo = &(padapter->wdinfo); ++#ifdef CONFIG_WFD ++ u32 wfdielen = 0; ++#endif //CONFIG_WFD ++#endif //CONFIG_P2P ++ ++ ++ ++ //DBG_871X("%s\n", __FUNCTION__); ++ ++ if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL) ++ { ++ DBG_871X("%s, alloc mgnt frame fail\n", __FUNCTION__); ++ return; ++ } ++ ++ ++ //update attribute ++ pattrib = &pmgntframe->attrib; ++ update_mgntframe_attrib(padapter, pattrib); ++ ++ _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); ++ ++ pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; ++ pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; ++ ++ mac = myid(&(padapter->eeprompriv)); ++ bssid = cur_network->MacAddress; ++ ++ fctrl = &(pwlanhdr->frame_ctl); ++ *(fctrl) = 0; ++ _rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr2, mac, ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr3, bssid, ETH_ALEN); ++ ++ SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); ++ pmlmeext->mgnt_seq++; ++ SetFrameSubType(fctrl, WIFI_PROBERSP); ++ ++ pattrib->hdrlen = sizeof(struct rtw_ieee80211_hdr_3addr); ++ pattrib->pktlen = pattrib->hdrlen; ++ pframe += pattrib->hdrlen; ++ ++ ++ if(cur_network->IELength>MAX_IE_SZ || cur_network->IELength<_FIXED_IE_LENGTH_) ++ return; ++ ++#if defined (CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME) ++ if( (pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE) ++ { ++ pwps_ie = rtw_get_wps_ie(cur_network->IEs+_FIXED_IE_LENGTH_, cur_network->IELength-_FIXED_IE_LENGTH_, NULL, &wps_ielen); ++ ++ //inerset & update wps_probe_resp_ie ++ if((pmlmepriv->wps_probe_resp_ie!=NULL) && pwps_ie && (wps_ielen>0)) ++ { ++ uint wps_offset, remainder_ielen; ++ u8 *premainder_ie; ++ ++ wps_offset = (uint)(pwps_ie - cur_network->IEs); ++ ++ premainder_ie = pwps_ie + wps_ielen; ++ ++ remainder_ielen = cur_network->IELength - wps_offset - wps_ielen; ++ ++ _rtw_memcpy(pframe, cur_network->IEs, wps_offset); ++ pframe += wps_offset; ++ pattrib->pktlen += wps_offset; ++ ++ wps_ielen = (uint)pmlmepriv->wps_probe_resp_ie[1];//to get ie data len ++ if((wps_offset+wps_ielen+2)<=MAX_IE_SZ) ++ { ++ _rtw_memcpy(pframe, pmlmepriv->wps_probe_resp_ie, wps_ielen+2); ++ pframe += wps_ielen+2; ++ pattrib->pktlen += wps_ielen+2; ++ } ++ ++ if((wps_offset+wps_ielen+2+remainder_ielen)<=MAX_IE_SZ) ++ { ++ _rtw_memcpy(pframe, premainder_ie, remainder_ielen); ++ pframe += remainder_ielen; ++ pattrib->pktlen += remainder_ielen; ++ } ++ } ++ else ++ { ++ _rtw_memcpy(pframe, cur_network->IEs, cur_network->IELength); ++ pframe += cur_network->IELength; ++ pattrib->pktlen += cur_network->IELength; ++ } ++ ++ } ++ else ++#endif ++ { ++ ++ //timestamp will be inserted by hardware ++ pframe += 8; ++ pattrib->pktlen += 8; ++ ++ // beacon interval: 2 bytes ++ ++ _rtw_memcpy(pframe, (unsigned char *)(rtw_get_beacon_interval_from_ie(cur_network->IEs)), 2); ++ ++ pframe += 2; ++ pattrib->pktlen += 2; ++ ++ // capability info: 2 bytes ++ ++ _rtw_memcpy(pframe, (unsigned char *)(rtw_get_capability_from_ie(cur_network->IEs)), 2); ++ ++ pframe += 2; ++ pattrib->pktlen += 2; ++ ++ //below for ad-hoc mode ++ ++ // SSID ++ pframe = rtw_set_ie(pframe, _SSID_IE_, cur_network->Ssid.SsidLength, cur_network->Ssid.Ssid, &pattrib->pktlen); ++ ++ // supported rates... ++ rate_len = rtw_get_rateset_len(cur_network->SupportedRates); ++ pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_, ((rate_len > 8)? 8: rate_len), cur_network->SupportedRates, &pattrib->pktlen); ++ ++ // DS parameter set ++ pframe =rtw_set_ie(pframe, _DSSET_IE_, 1, (unsigned char *)&(cur_network->Configuration.DSConfig), &pattrib->pktlen); ++ ++ if( (pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE) ++ { ++ u8 erpinfo=0; ++ u32 ATIMWindow; ++ // IBSS Parameter Set... ++ //ATIMWindow = cur->Configuration.ATIMWindow; ++ ATIMWindow = 0; ++ pframe = rtw_set_ie(pframe, _IBSS_PARA_IE_, 2, (unsigned char *)(&ATIMWindow), &pattrib->pktlen); ++ ++ //ERP IE ++ pframe = rtw_set_ie(pframe, _ERPINFO_IE_, 1, &erpinfo, &pattrib->pktlen); ++ } ++ ++ ++ // EXTERNDED SUPPORTED RATE ++ if (rate_len > 8) ++ { ++ pframe = rtw_set_ie(pframe, _EXT_SUPPORTEDRATES_IE_, (rate_len - 8), (cur_network->SupportedRates + 8), &pattrib->pktlen); ++ } ++ ++ ++ //todo:HT for adhoc ++ ++ } ++ ++#ifdef CONFIG_P2P ++ if(rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO) && is_valid_p2p_probereq) ++ { ++ u32 len; ++#ifdef CONFIG_IOCTL_CFG80211 ++ if(wdev_to_priv(padapter->rtw_wdev)->p2p_enabled) ++ { ++ //if pwdinfo->role == P2P_ROLE_DEVICE will call issue_probersp_p2p() ++ len = pmlmepriv->p2p_go_probe_resp_ie_len; ++ if(pmlmepriv->p2p_go_probe_resp_ie && len>0) ++ _rtw_memcpy(pframe, pmlmepriv->p2p_go_probe_resp_ie, len); ++ } ++ else ++#endif //CONFIG_IOCTL_CFG80211 ++ { ++ len = build_probe_resp_p2p_ie(pwdinfo, pframe); ++ } ++ ++ pframe += len; ++ pattrib->pktlen += len; ++ ++#ifdef CONFIG_WFD ++ wfdielen = build_probe_resp_wfd_ie(pwdinfo, pframe); ++ pframe += wfdielen; ++ pattrib->pktlen += wfdielen; ++#endif //CONFIG_WFD ++ ++ } ++#endif //CONFIG_P2P ++ ++ ++ pattrib->last_txcmdsz = pattrib->pktlen; ++ ++ ++ dump_mgntframe(padapter, pmgntframe); ++ ++ return; ++ ++} ++ ++void issue_probereq(_adapter *padapter, NDIS_802_11_SSID *pssid, u8 blnbc) ++{ ++ struct xmit_frame *pmgntframe; ++ struct pkt_attrib *pattrib; ++ unsigned char *pframe; ++ struct rtw_ieee80211_hdr *pwlanhdr; ++ unsigned short *fctrl; ++ unsigned char *mac; ++ unsigned char bssrate[NumRates]; ++ struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ int bssrate_len = 0; ++ u8 bc_addr[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; ++ ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("+issue_probereq\n")); ++ ++ if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL) ++ { ++ return; ++ } ++ ++ //update attribute ++ pattrib = &pmgntframe->attrib; ++ update_mgntframe_attrib(padapter, pattrib); ++ ++ ++ _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); ++ ++ pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; ++ pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; ++ ++ mac = myid(&(padapter->eeprompriv)); ++ ++ fctrl = &(pwlanhdr->frame_ctl); ++ *(fctrl) = 0; ++ ++ if ( 0 == blnbc ) ++ { ++ // unicast probe request frame ++ _rtw_memcpy(pwlanhdr->addr1, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); ++ } ++ else ++ { ++ // broadcast probe request frame ++ _rtw_memcpy(pwlanhdr->addr1, bc_addr, ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr3, bc_addr, ETH_ALEN); ++ } ++ ++ _rtw_memcpy(pwlanhdr->addr2, mac, ETH_ALEN); ++ ++ SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); ++ pmlmeext->mgnt_seq++; ++ SetFrameSubType(pframe, WIFI_PROBEREQ); ++ ++ pframe += sizeof (struct rtw_ieee80211_hdr_3addr); ++ pattrib->pktlen = sizeof (struct rtw_ieee80211_hdr_3addr); ++ ++ if(pssid) ++ pframe = rtw_set_ie(pframe, _SSID_IE_, pssid->SsidLength, pssid->Ssid, &(pattrib->pktlen)); ++ else ++ pframe = rtw_set_ie(pframe, _SSID_IE_, 0, NULL, &(pattrib->pktlen)); ++ ++ get_rate_set(padapter, bssrate, &bssrate_len); ++ ++ if (bssrate_len > 8) ++ { ++ pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_ , 8, bssrate, &(pattrib->pktlen)); ++ pframe = rtw_set_ie(pframe, _EXT_SUPPORTEDRATES_IE_ , (bssrate_len - 8), (bssrate + 8), &(pattrib->pktlen)); ++ } ++ else ++ { ++ pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_ , bssrate_len , bssrate, &(pattrib->pktlen)); ++ } ++ ++ ++ //add wps_ie for wps2.0 ++ if(pmlmepriv->probereq_wpsie_len>0 && pmlmepriv->probereq_wpsie_lenprobereq_wpsie, pmlmepriv->probereq_wpsie_len); ++ pframe += pmlmepriv->probereq_wpsie_len; ++ pattrib->pktlen += pmlmepriv->probereq_wpsie_len; ++ //pmlmepriv->probereq_wpsie_len = 0 ;//reset to zero ++ } ++ ++ ++ pattrib->last_txcmdsz = pattrib->pktlen; ++ ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("issuing probe_req, tx_len=%d\n", pattrib->last_txcmdsz)); ++ ++ dump_mgntframe(padapter, pmgntframe); ++ ++ return; ++} ++ ++// if psta == NULL, indiate we are station(client) now... ++void issue_auth(_adapter *padapter, struct sta_info *psta, unsigned short status) ++{ ++ struct xmit_frame *pmgntframe; ++ struct pkt_attrib *pattrib; ++ unsigned char *pframe; ++ struct rtw_ieee80211_hdr *pwlanhdr; ++ unsigned short *fctrl; ++ unsigned int val32; ++ unsigned short val16; ++ int use_shared_key = 0; ++ struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); ++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ ++/* ++ if( (psta == NULL) && (pmlmeinfo->auth_seq != 3) ) { ++ // Because of AP's not receiving deauth before ++ // AP may: 1)not response auth or 2)deauth us after link is complete ++ // issue deauth before issuing auth to deal with the situation ++ issue_deauth(padapter, (&(pmlmeinfo->network))->MacAddress, WLAN_REASON_DEAUTH_LEAVING); ++ } ++*/ ++ ++ if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL) ++ { ++ return; ++ } ++ ++ //update attribute ++ pattrib = &pmgntframe->attrib; ++ update_mgntframe_attrib(padapter, pattrib); ++ ++ _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); ++ ++ pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; ++ pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; ++ ++ fctrl = &(pwlanhdr->frame_ctl); ++ *(fctrl) = 0; ++ ++ SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); ++ pmlmeext->mgnt_seq++; ++ SetFrameSubType(pframe, WIFI_AUTH); ++ ++ pframe += sizeof(struct rtw_ieee80211_hdr_3addr); ++ pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); ++ ++ ++ if(psta)// for AP mode ++ { ++#ifdef CONFIG_NATIVEAP_MLME ++ ++ _rtw_memcpy(pwlanhdr->addr1, psta->hwaddr, ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr2, myid(&(padapter->eeprompriv)), ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr3, myid(&(padapter->eeprompriv)), ETH_ALEN); ++ ++ ++ // setting auth algo number ++ val16 = (u16)psta->authalg; ++ ++ if(status != _STATS_SUCCESSFUL_) ++ val16 = 0; ++ ++ if (val16) { ++ val16 = cpu_to_le16(val16); ++ use_shared_key = 1; ++ } ++ ++ pframe = rtw_set_fixed_ie(pframe, _AUTH_ALGM_NUM_, (unsigned char *)&val16, &(pattrib->pktlen)); ++ ++ // setting auth seq number ++ val16 =(u16)psta->auth_seq; ++ val16 = cpu_to_le16(val16); ++ pframe = rtw_set_fixed_ie(pframe, _AUTH_SEQ_NUM_, (unsigned char *)&val16, &(pattrib->pktlen)); ++ ++ // setting status code... ++ val16 = status; ++ val16 = cpu_to_le16(val16); ++ pframe = rtw_set_fixed_ie(pframe, _STATUS_CODE_, (unsigned char *)&val16, &(pattrib->pktlen)); ++ ++ // added challenging text... ++ if ((psta->auth_seq == 2) && (psta->state & WIFI_FW_AUTH_STATE) && (use_shared_key==1)) ++ { ++ pframe = rtw_set_ie(pframe, _CHLGETXT_IE_, 128, psta->chg_txt, &(pattrib->pktlen)); ++ } ++#endif ++ } ++ else ++ { ++ _rtw_memcpy(pwlanhdr->addr1, get_my_bssid(&pmlmeinfo->network), ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr2, myid(&padapter->eeprompriv), ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&pmlmeinfo->network), ETH_ALEN); ++ ++ // setting auth algo number ++ val16 = (pmlmeinfo->auth_algo == dot11AuthAlgrthm_Shared)? 1: 0;// 0:OPEN System, 1:Shared key ++ if (val16) { ++ val16 = cpu_to_le16(val16); ++ use_shared_key = 1; ++ } ++ //DBG_8192C("%s auth_algo= %s auth_seq=%d\n",__FUNCTION__,(pmlmeinfo->auth_algo==0)?"OPEN":"SHARED",pmlmeinfo->auth_seq); ++ ++ //setting IV for auth seq #3 ++ if ((pmlmeinfo->auth_seq == 3) && (pmlmeinfo->state & WIFI_FW_AUTH_STATE) && (use_shared_key==1)) ++ { ++ //DBG_8192C("==> iv(%d),key_index(%d)\n",pmlmeinfo->iv,pmlmeinfo->key_index); ++ val32 = ((pmlmeinfo->iv++) | (pmlmeinfo->key_index << 30)); ++ val32 = cpu_to_le32(val32); ++ pframe = rtw_set_fixed_ie(pframe, 4, (unsigned char *)&val32, &(pattrib->pktlen)); ++ ++ pattrib->iv_len = 4; ++ } ++ ++ pframe = rtw_set_fixed_ie(pframe, _AUTH_ALGM_NUM_, (unsigned char *)&val16, &(pattrib->pktlen)); ++ ++ // setting auth seq number ++ val16 = pmlmeinfo->auth_seq; ++ val16 = cpu_to_le16(val16); ++ pframe = rtw_set_fixed_ie(pframe, _AUTH_SEQ_NUM_, (unsigned char *)&val16, &(pattrib->pktlen)); ++ ++ ++ // setting status code... ++ val16 = status; ++ val16 = cpu_to_le16(val16); ++ pframe = rtw_set_fixed_ie(pframe, _STATUS_CODE_, (unsigned char *)&val16, &(pattrib->pktlen)); ++ ++ // then checking to see if sending challenging text... ++ if ((pmlmeinfo->auth_seq == 3) && (pmlmeinfo->state & WIFI_FW_AUTH_STATE) && (use_shared_key==1)) ++ { ++ pframe = rtw_set_ie(pframe, _CHLGETXT_IE_, 128, pmlmeinfo->chg_txt, &(pattrib->pktlen)); ++ ++ SetPrivacy(fctrl); ++ ++ pattrib->hdrlen = sizeof(struct rtw_ieee80211_hdr_3addr); ++ ++ pattrib->encrypt = _WEP40_; ++ ++ pattrib->icv_len = 4; ++ ++ pattrib->pktlen += pattrib->icv_len; ++ ++ } ++ ++ } ++ ++ pattrib->last_txcmdsz = pattrib->pktlen; ++ ++ rtw_wep_encrypt(padapter, (u8 *)pmgntframe); ++ ++ dump_mgntframe(padapter, pmgntframe); ++ ++ return; ++} ++ ++ ++void issue_asocrsp(_adapter *padapter, unsigned short status, struct sta_info *pstat, int pkt_type) ++{ ++#ifdef CONFIG_AP_MODE ++ struct xmit_frame *pmgntframe; ++ struct rtw_ieee80211_hdr *pwlanhdr; ++ struct pkt_attrib *pattrib; ++ unsigned char *pbuf, *pframe; ++ unsigned short val; ++ unsigned short *fctrl; ++ struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ WLAN_BSSID_EX *pnetwork = &(pmlmeinfo->network); ++ u8 *ie = pnetwork->IEs; ++#ifdef CONFIG_P2P ++ struct wifidirect_info *pwdinfo = &(padapter->wdinfo); ++#ifdef CONFIG_WFD ++ u32 wfdielen = 0; ++#endif //CONFIG_WFD ++ ++#endif //CONFIG_P2P ++ ++ DBG_871X("%s\n", __FUNCTION__); ++ ++ if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL) ++ { ++ return; ++ } ++ ++ //update attribute ++ pattrib = &pmgntframe->attrib; ++ update_mgntframe_attrib(padapter, pattrib); ++ ++ ++ _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); ++ ++ pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; ++ pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; ++ ++ fctrl = &(pwlanhdr->frame_ctl); ++ *(fctrl) = 0; ++ ++ _rtw_memcpy((void *)GetAddr1Ptr(pwlanhdr), pstat->hwaddr, ETH_ALEN); ++ _rtw_memcpy((void *)GetAddr2Ptr(pwlanhdr), myid(&(padapter->eeprompriv)), ETH_ALEN); ++ _rtw_memcpy((void *)GetAddr3Ptr(pwlanhdr), get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); ++ ++ ++ SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); ++ pmlmeext->mgnt_seq++; ++ if ((pkt_type == WIFI_ASSOCRSP) || (pkt_type == WIFI_REASSOCRSP)) ++ SetFrameSubType(pwlanhdr, pkt_type); ++ else ++ return; ++ ++ pattrib->hdrlen = sizeof(struct rtw_ieee80211_hdr_3addr); ++ pattrib->pktlen += pattrib->hdrlen; ++ pframe += pattrib->hdrlen; ++ ++ //capability ++ val = *(unsigned short *)rtw_get_capability_from_ie(ie); ++ ++ pframe = rtw_set_fixed_ie(pframe, _CAPABILITY_ , (unsigned char *)&val, &(pattrib->pktlen)); ++ ++ status = cpu_to_le16(status); ++ pframe = rtw_set_fixed_ie(pframe , _STATUS_CODE_ , (unsigned char *)&status, &(pattrib->pktlen)); ++ ++ val = cpu_to_le16(pstat->aid | BIT(14) | BIT(15)); ++ pframe = rtw_set_fixed_ie(pframe, _ASOC_ID_ , (unsigned char *)&val, &(pattrib->pktlen)); ++ ++ if (pstat->bssratelen <= 8) ++ { ++ pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_, pstat->bssratelen, pstat->bssrateset, &(pattrib->pktlen)); ++ } ++ else ++ { ++ pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_, 8, pstat->bssrateset, &(pattrib->pktlen)); ++ pframe = rtw_set_ie(pframe, _EXT_SUPPORTEDRATES_IE_, (pstat->bssratelen-8), pstat->bssrateset+8, &(pattrib->pktlen)); ++ } ++ ++#ifdef CONFIG_80211N_HT ++ if ((pstat->flags & WLAN_STA_HT) && (pmlmepriv->htpriv.ht_option)) ++ { ++ uint ie_len=0; ++ ++ //FILL HT CAP INFO IE ++ //p = hostapd_eid_ht_capabilities_info(hapd, p); ++ pbuf = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _HT_CAPABILITY_IE_, &ie_len, (pnetwork->IELength - _BEACON_IE_OFFSET_)); ++ if(pbuf && ie_len>0) ++ { ++ _rtw_memcpy(pframe, pbuf, ie_len+2); ++ pframe += (ie_len+2); ++ pattrib->pktlen +=(ie_len+2); ++ } ++ ++ //FILL HT ADD INFO IE ++ //p = hostapd_eid_ht_operation(hapd, p); ++ pbuf = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _HT_ADD_INFO_IE_, &ie_len, (pnetwork->IELength - _BEACON_IE_OFFSET_)); ++ if(pbuf && ie_len>0) ++ { ++ _rtw_memcpy(pframe, pbuf, ie_len+2); ++ pframe += (ie_len+2); ++ pattrib->pktlen +=(ie_len+2); ++ } ++ ++ } ++#endif ++ ++ //FILL WMM IE ++ if ((pstat->flags & WLAN_STA_WME) && (pmlmepriv->qospriv.qos_option)) ++ { ++ uint ie_len=0; ++ unsigned char WMM_PARA_IE[] = {0x00, 0x50, 0xf2, 0x02, 0x01, 0x01}; ++ ++ for (pbuf = ie + _BEACON_IE_OFFSET_; ;pbuf+= (ie_len + 2)) ++ { ++ pbuf = rtw_get_ie(pbuf, _VENDOR_SPECIFIC_IE_, &ie_len, (pnetwork->IELength - _BEACON_IE_OFFSET_ - (ie_len + 2))); ++ if(pbuf && _rtw_memcmp(pbuf+2, WMM_PARA_IE, 6)) ++ { ++ _rtw_memcpy(pframe, pbuf, ie_len+2); ++ pframe += (ie_len+2); ++ pattrib->pktlen +=(ie_len+2); ++ ++ break; ++ } ++ ++ if ((pbuf == NULL) || (ie_len == 0)) ++ { ++ break; ++ } ++ } ++ ++ } ++ ++ ++ if (pmlmeinfo->assoc_AP_vendor == realtekAP) ++ { ++ pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, 6 , REALTEK_96B_IE, &(pattrib->pktlen)); ++ } ++ ++ //add WPS IE ie for wps 2.0 ++ if(pmlmepriv->wps_assoc_resp_ie && pmlmepriv->wps_assoc_resp_ie_len>0) ++ { ++ _rtw_memcpy(pframe, pmlmepriv->wps_assoc_resp_ie, pmlmepriv->wps_assoc_resp_ie_len); ++ ++ pframe += pmlmepriv->wps_assoc_resp_ie_len; ++ pattrib->pktlen += pmlmepriv->wps_assoc_resp_ie_len; ++ } ++ ++#ifdef CONFIG_P2P ++ if(rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO) && (pstat->is_p2p_device == _TRUE)) ++ { ++ u32 len; ++ ++ len = build_assoc_resp_p2p_ie(pwdinfo, pframe, pstat->p2p_status_code); ++ ++ pframe += len; ++ pattrib->pktlen += len; ++ } ++#ifdef CONFIG_WFD ++ wfdielen = build_assoc_resp_wfd_ie(pwdinfo, pframe); ++ pframe += wfdielen; ++ pattrib->pktlen += wfdielen; ++#endif //CONFIG_WFD ++ ++#endif //CONFIG_P2P ++ ++ pattrib->last_txcmdsz = pattrib->pktlen; ++ ++ dump_mgntframe(padapter, pmgntframe); ++ ++#endif ++} ++ ++void issue_assocreq(_adapter *padapter) ++{ ++ struct xmit_frame *pmgntframe; ++ struct pkt_attrib *pattrib; ++ unsigned char *pframe, *p; ++ struct rtw_ieee80211_hdr *pwlanhdr; ++ unsigned short *fctrl; ++ unsigned short val16; ++ unsigned int i, j, ie_len, index=0; ++ unsigned char rf_type, bssrate[NumRates], sta_bssrate[NumRates]; ++ PNDIS_802_11_VARIABLE_IEs pIE; ++ struct registry_priv *pregpriv = &padapter->registrypriv; ++ struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ int bssrate_len = 0, sta_bssrate_len = 0; ++#ifdef CONFIG_P2P ++ struct wifidirect_info *pwdinfo = &(padapter->wdinfo); ++ u8 p2pie[ 255 ] = { 0x00 }; ++ u16 p2pielen = 0; ++#ifdef CONFIG_WFD ++ u32 wfdielen = 0; ++#endif //CONFIG_WFD ++ ++#endif //CONFIG_P2P ++ ++#ifdef CONFIG_DFS ++ u16 cap; ++#endif //CONFIG_DFS ++ ++ if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL) ++ { ++ return; ++ } ++ ++ //update attribute ++ pattrib = &pmgntframe->attrib; ++ update_mgntframe_attrib(padapter, pattrib); ++ ++ ++ _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); ++ ++ pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; ++ pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; ++ ++ fctrl = &(pwlanhdr->frame_ctl); ++ *(fctrl) = 0; ++ _rtw_memcpy(pwlanhdr->addr1, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr2, myid(&(padapter->eeprompriv)), ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); ++ ++ SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); ++ pmlmeext->mgnt_seq++; ++ SetFrameSubType(pframe, WIFI_ASSOCREQ); ++ ++ pframe += sizeof(struct rtw_ieee80211_hdr_3addr); ++ pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); ++ ++ //caps ++ ++#ifdef CONFIG_DFS ++ _rtw_memcpy(&cap, rtw_get_capability_from_ie(pmlmeinfo->network.IEs), 2); ++ cap |= BIT(8); ++ _rtw_memcpy(pframe, &cap, 2); ++#else ++ _rtw_memcpy(pframe, rtw_get_capability_from_ie(pmlmeinfo->network.IEs), 2); ++#endif //CONFIG_DFS ++ ++ pframe += 2; ++ pattrib->pktlen += 2; ++ ++ //listen interval ++ //todo: listen interval for power saving ++ val16 = cpu_to_le16(3); ++ _rtw_memcpy(pframe ,(unsigned char *)&val16, 2); ++ pframe += 2; ++ pattrib->pktlen += 2; ++ ++ //SSID ++ pframe = rtw_set_ie(pframe, _SSID_IE_, pmlmeinfo->network.Ssid.SsidLength, pmlmeinfo->network.Ssid.Ssid, &(pattrib->pktlen)); ++ ++ //supported rate & extended supported rate ++ ++#if 1 // Check if the AP's supported rates are also supported by STA. ++ get_rate_set(padapter, sta_bssrate, &sta_bssrate_len); ++ //DBG_871X("sta_bssrate_len=%d\n", sta_bssrate_len); ++ ++ //for (i = 0; i < sta_bssrate_len; i++) { ++ // DBG_871X("sta_bssrate[%d]=%02X\n", i, sta_bssrate[i]); ++ //} ++ ++ for (i = 0; i < NDIS_802_11_LENGTH_RATES_EX; i++) { ++ if (pmlmeinfo->network.SupportedRates[i] == 0) break; ++ DBG_871X("network.SupportedRates[%d]=%02X\n", i, pmlmeinfo->network.SupportedRates[i]); ++ } ++ ++ ++ for (i = 0; i < NDIS_802_11_LENGTH_RATES_EX; i++) { ++ if (pmlmeinfo->network.SupportedRates[i] == 0) break; ++ ++ ++ // Check if the AP's supported rates are also supported by STA. ++ for (j=0; j < sta_bssrate_len; j++) { ++ // Avoid the proprietary data rate (22Mbps) of Handlink WSG-4000 AP ++ if ( (pmlmeinfo->network.SupportedRates[i]|IEEE80211_BASIC_RATE_MASK) ++ == (sta_bssrate[j]|IEEE80211_BASIC_RATE_MASK)) { ++ //DBG_871X("match i = %d, j=%d\n", i, j); ++ break; ++ } else { ++ //DBG_871X("not match: %02X != %02X\n", (pmlmeinfo->network.SupportedRates[i]|IEEE80211_BASIC_RATE_MASK), (sta_bssrate[j]|IEEE80211_BASIC_RATE_MASK)); ++ } ++ } ++ ++ if (j == sta_bssrate_len) { ++ // the rate is not supported by STA ++ DBG_871X("%s(): the rate[%d]=%02X is not supported by STA!\n",__FUNCTION__, i, pmlmeinfo->network.SupportedRates[i]); ++ } else { ++ // the rate is supported by STA ++ bssrate[index++] = pmlmeinfo->network.SupportedRates[i]; ++ } ++ } ++ ++ bssrate_len = index; ++ DBG_871X("bssrate_len = %d\n", bssrate_len); ++ ++#else // Check if the AP's supported rates are also supported by STA. ++#if 0 ++ get_rate_set(padapter, bssrate, &bssrate_len); ++#else ++ for (bssrate_len = 0; bssrate_len < NumRates; bssrate_len++) { ++ if (pmlmeinfo->network.SupportedRates[bssrate_len] == 0) break; ++ ++ if (pmlmeinfo->network.SupportedRates[bssrate_len] == 0x2C) // Avoid the proprietary data rate (22Mbps) of Handlink WSG-4000 AP ++ break; ++ ++ bssrate[bssrate_len] = pmlmeinfo->network.SupportedRates[bssrate_len]; ++ } ++#endif ++#endif // Check if the AP's supported rates are also supported by STA. ++ ++ if (bssrate_len > 8) ++ { ++ pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_ , 8, bssrate, &(pattrib->pktlen)); ++ pframe = rtw_set_ie(pframe, _EXT_SUPPORTEDRATES_IE_ , (bssrate_len - 8), (bssrate + 8), &(pattrib->pktlen)); ++ } ++ else ++ { ++ pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_ , bssrate_len , bssrate, &(pattrib->pktlen)); ++ } ++ ++ //RSN ++ p = rtw_get_ie((pmlmeinfo->network.IEs + sizeof(NDIS_802_11_FIXED_IEs)), _RSN_IE_2_, &ie_len, (pmlmeinfo->network.IELength - sizeof(NDIS_802_11_FIXED_IEs))); ++ if (p != NULL) ++ { ++ pframe = rtw_set_ie(pframe, _RSN_IE_2_, ie_len, (p + 2), &(pattrib->pktlen)); ++ } ++ ++#ifdef CONFIG_80211N_HT ++ //HT caps ++ if(padapter->mlmepriv.htpriv.ht_option==_TRUE) ++ { ++ p = rtw_get_ie((pmlmeinfo->network.IEs + sizeof(NDIS_802_11_FIXED_IEs)), _HT_CAPABILITY_IE_, &ie_len, (pmlmeinfo->network.IELength - sizeof(NDIS_802_11_FIXED_IEs))); ++ if ((p != NULL) && (!(is_ap_in_tkip(padapter)))) ++ { ++ _rtw_memcpy(&(pmlmeinfo->HT_caps), (p + 2), sizeof(struct HT_caps_element)); ++ ++ //to disable 40M Hz support while gd_bw_40MHz_en = 0 ++ if (pregpriv->cbw40_enable == 0) ++ { ++ pmlmeinfo->HT_caps.HT_cap_element.HT_caps_info &= (~(BIT(6) | BIT(1))); ++ } ++ else ++ { ++ pmlmeinfo->HT_caps.HT_cap_element.HT_caps_info |= BIT(1); ++ } ++ ++ //todo: disable SM power save mode ++ pmlmeinfo->HT_caps.HT_cap_element.HT_caps_info |= 0x000c; ++ ++ padapter->HalFunc.GetHwRegHandler(padapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type)); ++ //switch (pregpriv->rf_config) ++ switch(rf_type) ++ { ++ case RF_1T1R: ++ ++ if(pregpriv->rx_stbc) ++ pmlmeinfo->HT_caps.HT_cap_element.HT_caps_info |= cpu_to_le16(0x0100);//RX STBC One spatial stream ++ ++ _rtw_memcpy(pmlmeinfo->HT_caps.HT_cap_element.MCS_rate, MCS_rate_1R, 16); ++ break; ++ ++ case RF_2T2R: ++ case RF_1T2R: ++ default: ++ ++ if((pregpriv->rx_stbc == 0x3) ||//enable for 2.4/5 GHz ++ ((pmlmeext->cur_wireless_mode & WIRELESS_11_24N) && (pregpriv->rx_stbc == 0x1)) || //enable for 2.4GHz ++ ((pmlmeext->cur_wireless_mode & WIRELESS_11_5N) && (pregpriv->rx_stbc == 0x2))) //enable for 5GHz ++ { ++ DBG_871X("declare supporting RX STBC\n"); ++ pmlmeinfo->HT_caps.HT_cap_element.HT_caps_info |= cpu_to_le16(0x0200);//RX STBC two spatial stream ++ } ++ ++ _rtw_memcpy(pmlmeinfo->HT_caps.HT_cap_element.MCS_rate, MCS_rate_2R, 16); ++ break; ++ ++ } ++ #ifdef RTL8192C_RECONFIG_TO_1T1R ++ { ++ //if(pregpriv->rx_stbc) ++ //pmlmeinfo->HT_caps.u.HT_cap_element.HT_caps_info |= cpu_to_le16(0x0100);//RX STBC One spatial stream ++ ++ _rtw_memcpy(pmlmeinfo->HT_caps.u.HT_cap_element.MCS_rate, MCS_rate_1R, 16); ++ } ++ #endif ++ pmlmeinfo->HT_caps.HT_cap_element.HT_caps_info = cpu_to_le16(pmlmeinfo->HT_caps.HT_cap_element.HT_caps_info); ++ pframe = rtw_set_ie(pframe, _HT_CAPABILITY_IE_, ie_len , (u8 *)(&(pmlmeinfo->HT_caps)), &(pattrib->pktlen)); ++ ++ } ++ } ++#endif ++ ++ //vendor specific IE, such as WPA, WMM, WPS ++ for (i = sizeof(NDIS_802_11_FIXED_IEs); i < pmlmeinfo->network.IELength;) ++ { ++ pIE = (PNDIS_802_11_VARIABLE_IEs)(pmlmeinfo->network.IEs + i); ++ ++ switch (pIE->ElementID) ++ { ++ case _VENDOR_SPECIFIC_IE_: ++ if ((_rtw_memcmp(pIE->data, WPA_OUI, 4)) || ++ (_rtw_memcmp(pIE->data, WMM_OUI, 4)) || ++ (_rtw_memcmp(pIE->data, WPS_OUI, 4))) ++ { ++ //Commented by Kurt 20110629 ++ //In some older APs, WPS handshake ++ //would be fail if we append vender extensions informations to AP ++ if(_rtw_memcmp(pIE->data, WPS_OUI, 4)){ ++ pIE->Length=14; ++ } ++ ++ pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, pIE->Length, pIE->data, &(pattrib->pktlen)); ++ } ++ break; ++ ++ default: ++ break; ++ } ++ ++ i += (pIE->Length + 2); ++ } ++ ++ if (pmlmeinfo->assoc_AP_vendor == realtekAP) ++ { ++ pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, 6 , REALTEK_96B_IE, &(pattrib->pktlen)); ++ } ++ ++#ifdef CONFIG_P2P ++ ++#ifdef CONFIG_IOCTL_CFG80211 ++ if(wdev_to_priv(padapter->rtw_wdev)->p2p_enabled) ++ { ++ if(pmlmepriv->p2p_assoc_req_ie && pmlmepriv->p2p_assoc_req_ie_len>0) ++ { ++ _rtw_memcpy(pframe, pmlmepriv->p2p_assoc_req_ie, pmlmepriv->p2p_assoc_req_ie_len); ++ pframe += pmlmepriv->p2p_assoc_req_ie_len; ++ pattrib->pktlen += pmlmepriv->p2p_assoc_req_ie_len; ++ } ++ } ++ else ++#endif //CONFIG_IOCTL_CFG80211 ++ { ++ if(!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE) && !rtw_p2p_chk_state(pwdinfo, P2P_STATE_IDLE)) ++ { ++ // Should add the P2P IE in the association request frame. ++ // P2P OUI ++ ++ p2pielen = 0; ++ p2pie[ p2pielen++ ] = 0x50; ++ p2pie[ p2pielen++ ] = 0x6F; ++ p2pie[ p2pielen++ ] = 0x9A; ++ p2pie[ p2pielen++ ] = 0x09; // WFA P2P v1.0 ++ ++ // Commented by Albert 20101109 ++ // According to the P2P Specification, the association request frame should contain 3 P2P attributes ++ // 1. P2P Capability ++ // 2. Extended Listen Timing ++ // 3. Device Info ++ // Commented by Albert 20110516 ++ // 4. P2P Interface ++ ++ // P2P Capability ++ // Type: ++ p2pie[ p2pielen++ ] = P2P_ATTR_CAPABILITY; ++ ++ // Length: ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0002 ); ++ p2pielen += 2; ++ ++ // Value: ++ // Device Capability Bitmap, 1 byte ++ // Be able to participate in additional P2P Groups and ++ // support the P2P Invitation Procedure ++ p2pie[ p2pielen++ ] = P2P_DEVCAP_INVITATION_PROC; ++ ++ // Group Capability Bitmap, 1 byte ++ p2pie[ p2pielen++ ] = 0x00; ++ ++ // Extended Listen Timing ++ // Type: ++ p2pie[ p2pielen++ ] = P2P_ATTR_EX_LISTEN_TIMING; ++ ++ // Length: ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0004 ); ++ p2pielen += 2; ++ ++ // Value: ++ // Availability Period ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0xFFFF ); ++ p2pielen += 2; ++ ++ // Availability Interval ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0xFFFF ); ++ p2pielen += 2; ++ ++ // Device Info ++ // Type: ++ p2pie[ p2pielen++ ] = P2P_ATTR_DEVICE_INFO; ++ ++ // Length: ++ // 21 -> P2P Device Address (6bytes) + Config Methods (2bytes) + Primary Device Type (8bytes) ++ // + NumofSecondDevType (1byte) + WPS Device Name ID field (2bytes) + WPS Device Name Len field (2bytes) ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 21 + pwdinfo->device_name_len ); ++ p2pielen += 2; ++ ++ // Value: ++ // P2P Device Address ++ _rtw_memcpy( p2pie + p2pielen, myid( &padapter->eeprompriv ), ETH_ALEN ); ++ p2pielen += ETH_ALEN; ++ ++ // Config Method ++ // This field should be big endian. Noted by P2P specification. ++ if ( ( pwdinfo->ui_got_wps_info == P2P_GOT_WPSINFO_PEER_DISPLAY_PIN ) || ++ ( pwdinfo->ui_got_wps_info == P2P_GOT_WPSINFO_SELF_DISPLAY_PIN ) ) ++ { ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_CONFIG_METHOD_DISPLAY ); ++ } ++ else ++ { ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_CONFIG_METHOD_PBC ); ++ } ++ ++ p2pielen += 2; ++ ++ // Primary Device Type ++ // Category ID ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_PDT_CID_RTK_WIDI ); ++ p2pielen += 2; ++ ++ // OUI ++ *(u32*) ( p2pie + p2pielen ) = cpu_to_be32( WPSOUI ); ++ p2pielen += 4; ++ ++ // Sub Category ID ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_PDT_SCID_RTK_DMP ); ++ p2pielen += 2; ++ ++ // Number of Secondary Device Types ++ p2pie[ p2pielen++ ] = 0x00; // No Secondary Device Type List ++ ++ // Device Name ++ // Type: ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_ATTR_DEVICE_NAME ); ++ p2pielen += 2; ++ ++ // Length: ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_be16( pwdinfo->device_name_len ); ++ p2pielen += 2; ++ ++ // Value: ++ _rtw_memcpy( p2pie + p2pielen, pwdinfo->device_name, pwdinfo->device_name_len ); ++ p2pielen += pwdinfo->device_name_len; ++ ++ // P2P Interface ++ // Type: ++ p2pie[ p2pielen++ ] = P2P_ATTR_INTERFACE; ++ ++ // Length: ++ *(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x000D ); ++ p2pielen += 2; ++ ++ // Value: ++ _rtw_memcpy( p2pie + p2pielen, pwdinfo->device_addr, ETH_ALEN ); // P2P Device Address ++ p2pielen += ETH_ALEN; ++ ++ p2pie[ p2pielen++ ] = 1; // P2P Interface Address Count ++ ++ _rtw_memcpy( p2pie + p2pielen, pwdinfo->device_addr, ETH_ALEN ); // P2P Interface Address List ++ p2pielen += ETH_ALEN; ++ ++ pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, p2pielen, (unsigned char *) p2pie, &pattrib->pktlen ); ++ ++#ifdef CONFIG_WFD ++ wfdielen = build_assoc_req_wfd_ie(pwdinfo, pframe); ++ pframe += wfdielen; ++ pattrib->pktlen += wfdielen; ++#endif //CONFIG_WFD ++ } ++ } ++ ++#ifdef CONFIG_WFD ++ wfdielen = build_assoc_req_wfd_ie(pwdinfo, pframe); ++ pframe += wfdielen; ++ pattrib->pktlen += wfdielen; ++#endif //CONFIG_WFD ++ ++#endif //CONFIG_P2P ++ ++ pattrib->last_txcmdsz = pattrib->pktlen; ++ dump_mgntframe(padapter, pmgntframe); ++ ++ return; ++} ++ ++void issue_nulldata(_adapter *padapter, unsigned int power_mode) ++{ ++ struct xmit_frame *pmgntframe; ++ struct pkt_attrib *pattrib; ++ unsigned char *pframe; ++ struct rtw_ieee80211_hdr *pwlanhdr; ++ unsigned short *fctrl; ++ struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); ++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ ++ //DBG_871X("%s:%d\n", __FUNCTION__, power_mode); ++ ++ if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL) ++ { ++ return; ++ } ++ ++ //update attribute ++ pattrib = &pmgntframe->attrib; ++ update_mgntframe_attrib(padapter, pattrib); ++ pattrib->retry_ctrl = _FALSE; ++ ++ _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); ++ ++ pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; ++ pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; ++ ++ fctrl = &(pwlanhdr->frame_ctl); ++ *(fctrl) = 0; ++ ++ if((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE) ++ { ++ SetFrDs(fctrl); ++ } ++ else if((pmlmeinfo->state&0x03) == WIFI_FW_STATION_STATE) ++ { ++ SetToDs(fctrl); ++ } ++ ++ if (power_mode) ++ { ++ SetPwrMgt(fctrl); ++ } ++ ++ _rtw_memcpy(pwlanhdr->addr1, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr2, myid(&(padapter->eeprompriv)), ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); ++ ++ SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); ++ pmlmeext->mgnt_seq++; ++ SetFrameSubType(pframe, WIFI_DATA_NULL); ++ ++ pframe += sizeof(struct rtw_ieee80211_hdr_3addr); ++ pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); ++ ++ pattrib->last_txcmdsz = pattrib->pktlen; ++ dump_mgntframe(padapter, pmgntframe); ++ ++ return; ++} ++ ++ ++void issue_qos_nulldata(_adapter *padapter, unsigned char *da, u16 tid) ++{ ++ struct xmit_frame *pmgntframe; ++ struct pkt_attrib *pattrib; ++ unsigned char *pframe; ++ struct rtw_ieee80211_hdr *pwlanhdr; ++ unsigned short *fctrl, *qc; ++ struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); ++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ ++ DBG_871X("%s\n", __FUNCTION__); ++ ++ if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL) ++ { ++ return; ++ } ++ ++ //update attribute ++ pattrib = &pmgntframe->attrib; ++ update_mgntframe_attrib(padapter, pattrib); ++ ++ pattrib->hdrlen +=2; ++ pattrib->qos_en = _TRUE; ++ pattrib->eosp = 1; ++ pattrib->ack_policy = 0; ++ pattrib->mdata = 0; ++ ++ _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); ++ ++ pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; ++ pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; ++ ++ fctrl = &(pwlanhdr->frame_ctl); ++ *(fctrl) = 0; ++ ++ if((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE) ++ { ++ SetFrDs(fctrl); ++ } ++ else if((pmlmeinfo->state&0x03) == WIFI_FW_STATION_STATE) ++ { ++ SetToDs(fctrl); ++ } ++ ++ if(pattrib->mdata) ++ SetMData(fctrl); ++ ++ qc = (unsigned short *)(pframe + pattrib->hdrlen - 2); ++ ++ SetPriority(qc, tid); ++ ++ SetEOSP(qc, pattrib->eosp); ++ ++ SetAckpolicy(qc, pattrib->ack_policy); ++ ++ _rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr2, myid(&(padapter->eeprompriv)), ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); ++ ++ SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); ++ pmlmeext->mgnt_seq++; ++ SetFrameSubType(pframe, WIFI_QOS_DATA_NULL); ++ ++ pframe += sizeof(struct rtw_ieee80211_hdr_3addr_qos); ++ pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr_qos); ++ ++ pattrib->last_txcmdsz = pattrib->pktlen; ++ dump_mgntframe(padapter, pmgntframe); ++ ++} ++ ++void issue_deauth(_adapter *padapter, unsigned char *da, unsigned short reason) ++{ ++ struct xmit_frame *pmgntframe; ++ struct pkt_attrib *pattrib; ++ unsigned char *pframe; ++ struct rtw_ieee80211_hdr *pwlanhdr; ++ unsigned short *fctrl; ++ struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); ++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ ++ DBG_871X("%s to "MAC_FMT"\n", __func__, MAC_ARG(da)); ++ ++ if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL) ++ { ++ return; ++ } ++ ++ //update attribute ++ pattrib = &pmgntframe->attrib; ++ update_mgntframe_attrib(padapter, pattrib); ++ pattrib->retry_ctrl = _FALSE; ++ ++ _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); ++ ++ pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; ++ pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; ++ ++ fctrl = &(pwlanhdr->frame_ctl); ++ *(fctrl) = 0; ++ ++ _rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr2, myid(&(padapter->eeprompriv)), ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); ++ ++ SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); ++ pmlmeext->mgnt_seq++; ++ SetFrameSubType(pframe, WIFI_DEAUTH); ++ ++ pframe += sizeof(struct rtw_ieee80211_hdr_3addr); ++ pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); ++ ++ reason = cpu_to_le16(reason); ++ pframe = rtw_set_fixed_ie(pframe, _RSON_CODE_ , (unsigned char *)&reason, &(pattrib->pktlen)); ++ ++ pattrib->last_txcmdsz = pattrib->pktlen; ++ ++ dump_mgntframe(padapter, pmgntframe); ++} ++ ++void issue_action_BA(_adapter *padapter, unsigned char *raddr, unsigned char action, unsigned short status) ++{ ++ u8 category = RTW_WLAN_CATEGORY_BACK; ++ u16 start_seq; ++ u16 BA_para_set; ++ u16 reason_code; ++ u16 BA_timeout_value; ++ u16 BA_starting_seqctrl; ++ struct xmit_frame *pmgntframe; ++ struct pkt_attrib *pattrib; ++ u8 *pframe; ++ struct rtw_ieee80211_hdr *pwlanhdr; ++ u16 *fctrl; ++ struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); ++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ struct sta_info *psta; ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ struct registry_priv *pregpriv = &padapter->registrypriv; ++ ++ ++ DBG_871X("%s, category=%d, action=%d, status=%d\n", __FUNCTION__, category, action, status); ++ ++ if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL) ++ { ++ return; ++ } ++ ++ //update attribute ++ pattrib = &pmgntframe->attrib; ++ update_mgntframe_attrib(padapter, pattrib); ++ ++ _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); ++ ++ pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; ++ pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; ++ ++ fctrl = &(pwlanhdr->frame_ctl); ++ *(fctrl) = 0; ++ ++ //_rtw_memcpy(pwlanhdr->addr1, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr1, raddr, ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr2, myid(&(padapter->eeprompriv)), ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); ++ ++ SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); ++ pmlmeext->mgnt_seq++; ++ SetFrameSubType(pframe, WIFI_ACTION); ++ ++ pframe += sizeof(struct rtw_ieee80211_hdr_3addr); ++ pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); ++ ++ pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen)); ++ pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen)); ++ ++ status = cpu_to_le16(status); ++ ++ ++ if (category == 3) ++ { ++ switch (action) ++ { ++ case 0: //ADDBA req ++ do { ++ pmlmeinfo->dialogToken++; ++ } while (pmlmeinfo->dialogToken == 0); ++ pframe = rtw_set_fixed_ie(pframe, 1, &(pmlmeinfo->dialogToken), &(pattrib->pktlen)); ++ ++ BA_para_set = (0x1002 | ((status & 0xf) << 2)); //immediate ack & 64 buffer size ++ //sys_mib.BA_para_set = 0x0802; //immediate ack & 32 buffer size ++ BA_para_set = cpu_to_le16(BA_para_set); ++ pframe = rtw_set_fixed_ie(pframe, 2, (unsigned char *)(&(BA_para_set)), &(pattrib->pktlen)); ++ ++ //BA_timeout_value = 0xffff;//max: 65535 TUs(~ 65 ms) ++ BA_timeout_value = 5000;//~ 5ms ++ BA_timeout_value = cpu_to_le16(BA_timeout_value); ++ pframe = rtw_set_fixed_ie(pframe, 2, (unsigned char *)(&(BA_timeout_value)), &(pattrib->pktlen)); ++ ++ //if ((psta = rtw_get_stainfo(pstapriv, pmlmeinfo->network.MacAddress)) != NULL) ++ if ((psta = rtw_get_stainfo(pstapriv, raddr)) != NULL) ++ { ++ start_seq = (psta->sta_xmitpriv.txseq_tid[status & 0x07]&0xfff) + 1; ++ ++ DBG_871X("BA_starting_seqctrl = %d for TID=%d\n", start_seq, status & 0x07); ++ ++ psta->BA_starting_seqctrl[status & 0x07] = start_seq; ++ ++ BA_starting_seqctrl = start_seq << 4; ++ } ++ ++ BA_starting_seqctrl = cpu_to_le16(BA_starting_seqctrl); ++ pframe = rtw_set_fixed_ie(pframe, 2, (unsigned char *)(&(BA_starting_seqctrl)), &(pattrib->pktlen)); ++ break; ++ ++ case 1: //ADDBA rsp ++ pframe = rtw_set_fixed_ie(pframe, 1, &(pmlmeinfo->ADDBA_req.dialog_token), &(pattrib->pktlen)); ++ pframe = rtw_set_fixed_ie(pframe, 2, (unsigned char *)(&status), &(pattrib->pktlen)); ++ ++ //BA_para_set = cpu_to_le16((le16_to_cpu(pmlmeinfo->ADDBA_req.BA_para_set) & 0x3f) | 0x1000); //64 buffer size ++ BA_para_set = ((le16_to_cpu(pmlmeinfo->ADDBA_req.BA_para_set) & 0x3f) | 0x1000); //64 buffer size ++ ++ if(pregpriv->ampdu_amsdu==0)//disabled ++ BA_para_set = cpu_to_le16(BA_para_set & ~BIT(0)); ++ else if(pregpriv->ampdu_amsdu==1)//enabled ++ BA_para_set = cpu_to_le16(BA_para_set | BIT(0)); ++ else //auto ++ BA_para_set = cpu_to_le16(BA_para_set); ++ ++ pframe = rtw_set_fixed_ie(pframe, 2, (unsigned char *)(&(BA_para_set)), &(pattrib->pktlen)); ++ pframe = rtw_set_fixed_ie(pframe, 2, (unsigned char *)(&(pmlmeinfo->ADDBA_req.BA_timeout_value)), &(pattrib->pktlen)); ++ break; ++ case 2://DELBA ++ BA_para_set = (status & 0x1F) << 3; ++ BA_para_set = cpu_to_le16(BA_para_set); ++ pframe = rtw_set_fixed_ie(pframe, 2, (unsigned char *)(&(BA_para_set)), &(pattrib->pktlen)); ++ ++ reason_code = 37;//Requested from peer STA as it does not want to use the mechanism ++ reason_code = cpu_to_le16(reason_code); ++ pframe = rtw_set_fixed_ie(pframe, 2, (unsigned char *)(&(reason_code)), &(pattrib->pktlen)); ++ break; ++ default: ++ break; ++ } ++ } ++ ++ pattrib->last_txcmdsz = pattrib->pktlen; ++ ++ dump_mgntframe(padapter, pmgntframe); ++} ++ ++static void issue_action_BSSCoexistPacket(_adapter *padapter) ++{ ++ _irqL irqL; ++ _list *plist, *phead; ++ unsigned char category, action; ++ struct xmit_frame *pmgntframe; ++ struct pkt_attrib *pattrib; ++ unsigned char *pframe; ++ struct rtw_ieee80211_hdr *pwlanhdr; ++ unsigned short *fctrl; ++ struct wlan_network *pnetwork = NULL; ++ struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ _queue *queue = &(pmlmepriv->scanned_queue); ++ u8 InfoContent[16] = {0}; ++ u8 ICS[8][15]; ++ ++ if((pmlmepriv->num_FortyMHzIntolerant==0) || (pmlmepriv->num_sta_no_ht==0)) ++ return; ++ ++ if(_TRUE == pmlmeinfo->bwmode_updated) ++ return; ++ ++ ++ DBG_871X("%s\n", __FUNCTION__); ++ ++ ++ category = RTW_WLAN_CATEGORY_PUBLIC; ++ action = ACT_PUBLIC_BSSCOEXIST; ++ ++ if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL) ++ { ++ return; ++ } ++ ++ //update attribute ++ pattrib = &pmgntframe->attrib; ++ update_mgntframe_attrib(padapter, pattrib); ++ ++ _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); ++ ++ pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; ++ pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; ++ ++ fctrl = &(pwlanhdr->frame_ctl); ++ *(fctrl) = 0; ++ ++ _rtw_memcpy(pwlanhdr->addr1, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr2, myid(&(padapter->eeprompriv)), ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); ++ ++ SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); ++ pmlmeext->mgnt_seq++; ++ SetFrameSubType(pframe, WIFI_ACTION); ++ ++ pframe += sizeof(struct rtw_ieee80211_hdr_3addr); ++ pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); ++ ++ pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen)); ++ pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen)); ++ ++ ++ // ++ if(pmlmepriv->num_FortyMHzIntolerant>0) ++ { ++ u8 iedata=0; ++ ++ iedata |= BIT(2);//20 MHz BSS Width Request ++ ++ pframe = rtw_set_ie(pframe, EID_BSSCoexistence, 1, &iedata, &(pattrib->pktlen)); ++ ++ } ++ ++ ++ // ++ _rtw_memset(ICS, 0, sizeof(ICS)); ++ if(pmlmepriv->num_sta_no_ht>0) ++ { ++ int i; ++ ++ _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); ++ ++ phead = get_list_head(queue); ++ plist = get_next(phead); ++ ++ while(1) ++ { ++ int len; ++ u8 *p; ++ WLAN_BSSID_EX *pbss_network; ++ ++ if (rtw_end_of_queue_search(phead,plist)== _TRUE) ++ break; ++ ++ pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list); ++ ++ plist = get_next(plist); ++ ++ pbss_network = (WLAN_BSSID_EX *)&pnetwork->network; ++ ++ p = rtw_get_ie(pbss_network->IEs + _FIXED_IE_LENGTH_, _HT_CAPABILITY_IE_, &len, pbss_network->IELength - _FIXED_IE_LENGTH_); ++ if((p==NULL) || (len==0))//non-HT ++ { ++ if((pbss_network->Configuration.DSConfig<=0) || (pbss_network->Configuration.DSConfig>14)) ++ continue; ++ ++ ICS[0][pbss_network->Configuration.DSConfig]=1; ++ ++ if(ICS[0][0] == 0) ++ ICS[0][0] = 1; ++ } ++ ++ } ++ ++ _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); ++ ++ ++ for(i= 0;i<8;i++) ++ { ++ if(ICS[i][0] == 1) ++ { ++ int j, k = 0; ++ ++ InfoContent[k] = i; ++ //SET_BSS_INTOLERANT_ELE_REG_CLASS(InfoContent,i); ++ k++; ++ ++ for(j=1;j<=14;j++) ++ { ++ if(ICS[i][j]==1) ++ { ++ if(k<16) ++ { ++ InfoContent[k] = j; //channel number ++ //SET_BSS_INTOLERANT_ELE_CHANNEL(InfoContent+k, j); ++ k++; ++ } ++ } ++ } ++ ++ pframe = rtw_set_ie(pframe, EID_BSSIntolerantChlReport, k, InfoContent, &(pattrib->pktlen)); ++ ++ } ++ ++ } ++ ++ ++ } ++ ++ ++ pattrib->last_txcmdsz = pattrib->pktlen; ++ ++ dump_mgntframe(padapter, pmgntframe); ++ ++} ++ ++unsigned int send_delba(_adapter *padapter, u8 initiator, u8 *addr) ++{ ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ struct sta_info *psta = NULL; ++ //struct recv_reorder_ctrl *preorder_ctrl; ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ u16 tid; ++ ++ if((pmlmeinfo->state&0x03) != WIFI_FW_AP_STATE) ++ if (!(pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS)) ++ return _SUCCESS; ++ ++ psta = rtw_get_stainfo(pstapriv, addr); ++ if(psta==NULL) ++ return _SUCCESS; ++ ++ //DBG_8192C("%s:%s\n", __FUNCTION__, (initiator==0)?"RX_DIR":"TX_DIR"); ++ ++ if(initiator==0) // recipient ++ { ++ for(tid = 0;tidrecvreorder_ctrl[tid].enable == _TRUE) ++ { ++ DBG_8192C("rx agg disable tid(%d)\n",tid); ++ issue_action_BA(padapter, addr, RTW_WLAN_ACTION_DELBA, (((tid <<1) |initiator)&0x1F)); ++ psta->recvreorder_ctrl[tid].enable = _FALSE; ++ psta->recvreorder_ctrl[tid].indicate_seq = 0xffff; ++ #ifdef DBG_RX_SEQ ++ DBG_871X("DBG_RX_SEQ %s:%d indicate_seq:%u \n", __FUNCTION__, __LINE__, ++ psta->recvreorder_ctrl[tid].indicate_seq); ++ #endif ++ } ++ } ++ } ++ else if(initiator == 1)// originator ++ { ++ //DBG_8192C("tx agg_enable_bitmap(0x%08x)\n", psta->htpriv.agg_enable_bitmap); ++ for(tid = 0;tidhtpriv.agg_enable_bitmap & BIT(tid)) ++ { ++ DBG_8192C("tx agg disable tid(%d)\n",tid); ++ issue_action_BA(padapter, addr, RTW_WLAN_ACTION_DELBA, (((tid <<1) |initiator)&0x1F) ); ++ psta->htpriv.agg_enable_bitmap &= ~BIT(tid); ++ psta->htpriv.candidate_tid_bitmap &= ~BIT(tid); ++ ++ } ++ } ++ } ++ ++ return _SUCCESS; ++ ++} ++ ++unsigned int send_beacon(_adapter *padapter) ++{ ++ u8 bxmitok = _FALSE; ++ int retry=0; ++ ++ //DBG_871X("%s\n", __FUNCTION__); ++ ++#ifdef CONFIG_PCI_HCI ++ ++ issue_beacon(padapter); ++ ++ return _SUCCESS; ++ ++#endif ++ ++#ifdef CONFIG_USB_HCI ++ do{ ++ ++ issue_beacon(padapter); ++ ++ padapter->HalFunc.GetHwRegHandler(padapter, HW_VAR_TX_BCN_DONE, (u8 *)(&bxmitok)); ++ ++ }while((_FALSE == bxmitok) &&((retry++)<100 )); ++ ++ if(retry == 100) ++ { ++ DBG_871X("send_beacon, fail!\n"); ++ return _FAIL; ++ } ++ else ++ { ++ return _SUCCESS; ++ } ++#endif ++ ++} ++ ++/**************************************************************************** ++ ++Following are some utitity fuctions for WiFi MLME ++ ++*****************************************************************************/ ++ ++BOOLEAN IsLegal5GChannel( ++ IN PADAPTER Adapter, ++ IN u8 channel) ++{ ++ ++ int i=0; ++ u8 Channel_5G[45] = {36,38,40,42,44,46,48,50,52,54,56,58, ++ 60,62,64,100,102,104,106,108,110,112,114,116,118,120,122, ++ 124,126,128,130,132,134,136,138,140,149,151,153,155,157,159, ++ 161,163,165}; ++ for(i=0;imlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ u32 initialgain = 0; ++#ifdef CONFIG_P2P ++ struct wifidirect_info *pwdinfo= &(padapter->wdinfo); ++ static unsigned char prev_survey_channel = 0; ++ static unsigned int p2p_scan_count = 0; ++#endif //CONFIG_P2P ++ ++#ifdef CONFIG_P2P ++ survey_channel = 0; ++ ScanType = SCAN_PASSIVE; ++ ++ if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_FIND_PHASE_SEARCH)) ++ { ++ if ( pwdinfo->find_phase_state_exchange_cnt != 0 ) ++ { ++ // Commented by Albert 2011/06/03 ++ // The driver is in the find phase, it should go through the social channel. ++ survey_channel = pwdinfo->social_chan[pmlmeext->sitesurvey_res.channel_idx]; ++ ScanType = SCAN_ACTIVE; ++ } ++ else ++ { ++ // Commented by Albert 2011/06/03 ++ // The driver is in the scan phase, it should go through all the channel. ++ survey_channel = pmlmeext->channel_set[pmlmeext->sitesurvey_res.channel_idx].ChannelNum; ++ ScanType = pmlmeext->channel_set[pmlmeext->sitesurvey_res.channel_idx].ScanType; ++ } ++ } ++ else if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE) || rtw_p2p_chk_state(pwdinfo, P2P_STATE_IDLE)) ++ { ++ // Commented by Albert 20110805 ++ // The following code will be executed only when the P2P is disable. ++ survey_channel = pmlmeext->channel_set[pmlmeext->sitesurvey_res.channel_idx].ChannelNum; ++ ScanType = pmlmeext->channel_set[pmlmeext->sitesurvey_res.channel_idx].ScanType; ++ } ++#else ++ { ++ survey_channel = pmlmeext->channel_set[pmlmeext->sitesurvey_res.channel_idx].ChannelNum; ++ ScanType = pmlmeext->channel_set[pmlmeext->sitesurvey_res.channel_idx].ScanType; ++ } ++#endif //CONFIG_P2P ++ ++ if(survey_channel != 0) ++ { ++ ++ //DBG_871X("switching to ch:%d at %dms, %c%c%c\n" ++ // , survey_channel, rtw_get_passing_time_ms(padapter->mlmepriv.scan_start_time) ++ // , ScanType?'A':'P', pmlmeext->sitesurvey_res.scan_mode?'A':'P' ++ // , pmlmeext->sitesurvey_res.ssid[0].SsidLength?'S':' ' ++ //); ++ //PAUSE 4-AC Queue when site_survey ++ //padapter->HalFunc.GetHwRegHandler(padapter, HW_VAR_TXPAUSE, (u8 *)(&val8)); ++ //val8 |= 0x0f; ++ //padapter->HalFunc.SetHwRegHandler(padapter, HW_VAR_TXPAUSE, (u8 *)(&val8)); ++ ++ if(pmlmeext->sitesurvey_res.channel_idx == 0) ++ { ++ set_channel_bwmode(padapter, survey_channel, HAL_PRIME_CHNL_OFFSET_DONT_CARE, HT_CHANNEL_WIDTH_20); ++ } ++ else ++ { ++ SelectChannel(padapter, survey_channel); ++ } ++ ++ ++ if(ScanType == SCAN_ACTIVE) //obey the channel plan setting... ++ { ++ #ifdef CONFIG_P2P ++ if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_SCAN) || ++ rtw_p2p_chk_state(pwdinfo, P2P_STATE_FIND_PHASE_SEARCH) ++ ) ++ { ++ issue_probereq_p2p(padapter); ++ issue_probereq_p2p(padapter); ++ issue_probereq_p2p(padapter); ++ } ++ else ++ #endif //CONFIG_P2P ++ { ++ int i; ++ for(i=0;isitesurvey_res.ssid[i].SsidLength) { ++ //todo: to issue two probe req??? ++ issue_probereq(padapter, &(pmlmeext->sitesurvey_res.ssid[i]),1); ++ //rtw_msleep_os(SURVEY_TO>>1); ++ issue_probereq(padapter, &(pmlmeext->sitesurvey_res.ssid[i]),1); ++ } else { ++ break; ++ } ++ } ++ ++ if(pmlmeext->sitesurvey_res.scan_mode == SCAN_ACTIVE) { ++ //todo: to issue two probe req??? ++ issue_probereq(padapter, NULL, 1); ++ //rtw_msleep_os(SURVEY_TO>>1); ++ issue_probereq(padapter, NULL, 1); ++ } ++ } ++ } ++ ++ set_survey_timer(pmlmeext, pmlmeext->chan_scan_time); ++ ++ } ++ else ++ { ++ ++ // channel number is 0 or this channel is not valid. ++#ifdef CONFIG_P2P ++ if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_SCAN) || rtw_p2p_chk_state(pwdinfo, P2P_STATE_FIND_PHASE_SEARCH)) ++ { ++ #ifdef CONFIG_DBG_P2P ++ DBG_8192C( "[%s] find phase exchange cnt = %d\n", __FUNCTION__, pwdinfo->find_phase_state_exchange_cnt ); ++ #endif ++ } ++ ++ if ( ( rtw_p2p_chk_state(pwdinfo, P2P_STATE_SCAN) || rtw_p2p_chk_state(pwdinfo, P2P_STATE_FIND_PHASE_SEARCH) ) && ++ ( pwdinfo->find_phase_state_exchange_cnt < P2P_FINDPHASE_EX_CNT ) ) ++ { ++ // Set the P2P State to the listen state of find phase and set the current channel to the listen channel ++ set_channel_bwmode(padapter, pwdinfo->listen_channel, HAL_PRIME_CHNL_OFFSET_DONT_CARE, HT_CHANNEL_WIDTH_20); ++ rtw_p2p_set_state(pwdinfo, P2P_STATE_FIND_PHASE_LISTEN); ++ ++ pmlmeext->sitesurvey_res.state = SCAN_DISABLE; ++ ++ _set_timer( &pwdinfo->find_phase_timer, ( u32 ) ( ( u32 ) ( pwdinfo->listen_dwell ) * 100 ) ); ++ } ++ else ++#endif //CONFIG_P2P ++ ++ { ++ ++#ifdef CONFIG_ANTENNA_DIVERSITY ++ // 20100721:Interrupt scan operation here. ++ // For SW antenna diversity before link, it needs to switch to another antenna and scan again. ++ // It compares the scan result and select beter one to do connection. ++ if(padapter->HalFunc.SwAntDivBeforeLinkHandler(padapter)) ++ { ++ pmlmeext->sitesurvey_res.bss_cnt = 0; ++ pmlmeext->sitesurvey_res.channel_idx = -1; ++ pmlmeext->chan_scan_time = SURVEY_TO /2; ++ set_survey_timer(pmlmeext, pmlmeext->chan_scan_time); ++ return; ++ } ++#endif ++ ++#ifdef CONFIG_P2P ++ if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_SCAN) || rtw_p2p_chk_state(pwdinfo, P2P_STATE_FIND_PHASE_SEARCH)) ++ { ++ rtw_p2p_set_state(pwdinfo, P2P_STATE_LISTEN); ++ } ++#endif //CONFIG_P2P ++ ++ pmlmeext->sitesurvey_res.state = SCAN_COMPLETE; ++ ++ //switch back to the original channel ++ //SelectChannel(padapter, pmlmeext->cur_channel, pmlmeext->cur_ch_offset); ++ ++#ifdef CONFIG_P2P ++ if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_GONEGO_OK) ++ && pwdinfo->peer_operating_ch != 0 ++ ) ++ { ++ DBG_8192C( "[%s] In P2P WPS mode, stay in the peer operating channel = %d\n", __FUNCTION__, pwdinfo->peer_operating_ch ); ++ set_channel_bwmode(padapter, pwdinfo->peer_operating_ch, pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode); ++ } ++ else ++#endif //CONFIG_P2P ++ { ++ set_channel_bwmode(padapter, pmlmeext->cur_channel, pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode); ++ } ++ ++ //flush 4-AC Queue after site_survey ++ //val8 = 0; ++ //padapter->HalFunc.SetHwRegHandler(padapter, HW_VAR_TXPAUSE, (u8 *)(&val8)); ++ ++ val8 = 0; ++ padapter->HalFunc.SetHwRegHandler(padapter, HW_VAR_MLME_SITESURVEY, (u8 *)(&val8)); ++ ++ //config MSR ++ Set_NETYPE0_MSR(padapter, (pmlmeinfo->state & 0x3)); ++ ++ initialgain = 0xff; //restore RX GAIN ++ padapter->HalFunc.SetHwRegHandler(padapter, HW_VAR_INITIAL_GAIN, (u8 *)(&initialgain)); ++ //turn on dynamic functions ++ Restore_DM_Func_Flag(padapter); ++ //Switch_DM_Func(padapter, DYNAMIC_FUNC_DIG|DYNAMIC_FUNC_HP|DYNAMIC_FUNC_SS, _TRUE); ++ ++ if (is_client_associated_to_ap(padapter) == _TRUE) ++ { ++ //issue null data ++ issue_nulldata(padapter, 0); ++ } ++ ++ report_surveydone_event(padapter); ++ ++ pmlmeext->chan_scan_time = SURVEY_TO; ++ pmlmeext->sitesurvey_res.state = SCAN_DISABLE; ++ ++ issue_action_BSSCoexistPacket(padapter); ++ issue_action_BSSCoexistPacket(padapter); ++ issue_action_BSSCoexistPacket(padapter); ++ ++ } ++ ++ } ++ ++ return; ++ ++} ++ ++//collect bss info from Beacon and Probe response frames. ++u8 collect_bss_info(_adapter *padapter, union recv_frame *precv_frame, WLAN_BSSID_EX *bssid) ++{ ++ int i; ++ u32 len; ++ u8 *p; ++ u16 val16, subtype; ++ u8 *pframe = precv_frame->u.hdr.rx_data; ++ u32 packet_len = precv_frame->u.hdr.len; ++ struct registry_priv *pregistrypriv = &padapter->registrypriv; ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ ++ len = packet_len - sizeof(struct rtw_ieee80211_hdr_3addr); ++ ++ if (len > MAX_IE_SZ) ++ { ++ //DBG_8192C("IE too long for survey event\n"); ++ return _FAIL; ++ } ++ ++ _rtw_memset(bssid, 0, sizeof(WLAN_BSSID_EX)); ++ ++ subtype = GetFrameSubType(pframe); ++ ++ if(subtype==WIFI_BEACON) ++ bssid->Reserved[0] = 1; ++ else ++ bssid->Reserved[0] = 0; ++ ++ bssid->Length = sizeof(WLAN_BSSID_EX) - MAX_IE_SZ + len; ++ ++ //below is to copy the information element ++ bssid->IELength = len; ++ _rtw_memcpy(bssid->IEs, (pframe + sizeof(struct rtw_ieee80211_hdr_3addr)), bssid->IELength); ++ ++ //get the signal strength ++ bssid->PhyInfo.SignalQuality = precv_frame->u.hdr.attrib.signal_qual;//in percentage ++ bssid->PhyInfo.SignalStrength = precv_frame->u.hdr.attrib.signal_strength;//in percentage ++ bssid->Rssi = precv_frame->u.hdr.attrib.RecvSignalPower; // in dBM.raw data ++ ++#ifdef CONFIG_ANTENNA_DIVERSITY ++ //padapter->HalFunc.GetHwRegHandler(padapter, HW_VAR_CURRENT_ANTENNA, (u8 *)(&bssid->PhyInfo.Optimum_antenna)); ++ padapter->HalFunc.GetHalDefVarHandler(padapter, HAL_DEF_CURRENT_ANTENNA, &bssid->PhyInfo.Optimum_antenna); ++#endif ++ ++ // checking SSID ++ if ((p = rtw_get_ie(bssid->IEs + _FIXED_IE_LENGTH_, _SSID_IE_, &len, bssid->IELength - _FIXED_IE_LENGTH_)) == NULL) ++ { ++ DBG_871X("marc: cannot find SSID for survey event\n"); ++ return _FAIL; ++ } ++ ++ if (*(p + 1)) ++ { ++ _rtw_memcpy(bssid->Ssid.Ssid, (p + 2), *(p + 1)); ++ bssid->Ssid.SsidLength = *(p + 1); ++ } ++ else ++ { ++ bssid->Ssid.SsidLength = 0; ++ } ++ ++ _rtw_memset(bssid->SupportedRates, 0, NDIS_802_11_LENGTH_RATES_EX); ++ ++ //checking rate info... ++ i = 0; ++ p = rtw_get_ie(bssid->IEs + _FIXED_IE_LENGTH_, _SUPPORTEDRATES_IE_, &len, bssid->IELength - _FIXED_IE_LENGTH_); ++ if (p != NULL) ++ { ++ _rtw_memcpy(bssid->SupportedRates, (p + 2), len); ++ i = len; ++ } ++ ++ p = rtw_get_ie(bssid->IEs + _FIXED_IE_LENGTH_, _EXT_SUPPORTEDRATES_IE_, &len, bssid->IELength - _FIXED_IE_LENGTH_); ++ if (p != NULL) ++ { ++ _rtw_memcpy(bssid->SupportedRates + i, (p + 2), len); ++ } ++ ++ //todo: ++#if 0 ++ if (judge_network_type(bssid->SupportedRates, (len + i)) == WIRELESS_11B) ++ { ++ bssid->NetworkTypeInUse = Ndis802_11DS; ++ } ++ else ++#endif ++ { ++ bssid->NetworkTypeInUse = Ndis802_11OFDM24; ++ } ++ ++ // Checking for DSConfig ++ p = rtw_get_ie(bssid->IEs + _FIXED_IE_LENGTH_, _DSSET_IE_, &len, bssid->IELength - _FIXED_IE_LENGTH_); ++ ++ bssid->Configuration.DSConfig = 0; ++ bssid->Configuration.Length = 0; ++ ++ if (p) ++ { ++ bssid->Configuration.DSConfig = *(p + 2); ++ } ++ else ++ {// In 5G, some ap do not have DSSET IE ++ // checking HT info for channel ++ p = rtw_get_ie(bssid->IEs + _FIXED_IE_LENGTH_, _HT_ADD_INFO_IE_, &len, bssid->IELength - _FIXED_IE_LENGTH_); ++ if(p) ++ { ++ struct HT_info_element *HT_info = (struct HT_info_element *)(p + 2); ++ bssid->Configuration.DSConfig = HT_info->primary_channel; ++ } ++ else ++ { // use current channel ++ if (padapter->mlmeextpriv.sitesurvey_res.state == SCAN_PROCESS) ++ bssid->Configuration.DSConfig = padapter->mlmeextpriv.channel_set[padapter->mlmeextpriv.sitesurvey_res.channel_idx].ChannelNum; ++ else ++ bssid->Configuration.DSConfig = padapter->mlmeextpriv.cur_channel; ++ } ++ } ++ ++ _rtw_memcpy(&bssid->Configuration.BeaconPeriod, rtw_get_beacon_interval_from_ie(bssid->IEs), 2); ++ ++ ++ bssid->Configuration.BeaconPeriod = le32_to_cpu(bssid->Configuration.BeaconPeriod); ++ ++ val16 = rtw_get_capability((WLAN_BSSID_EX *)bssid); ++ ++ if (val16 & BIT(0)) ++ { ++ bssid->InfrastructureMode = Ndis802_11Infrastructure; ++ _rtw_memcpy(bssid->MacAddress, GetAddr2Ptr(pframe), ETH_ALEN); ++ } ++ else ++ { ++ bssid->InfrastructureMode = Ndis802_11IBSS; ++ _rtw_memcpy(bssid->MacAddress, GetAddr3Ptr(pframe), ETH_ALEN); ++ } ++ ++ if (val16 & BIT(4)) ++ bssid->Privacy = 1; ++ else ++ bssid->Privacy = 0; ++ ++ bssid->Configuration.ATIMWindow = 0; ++ ++ //20/40 BSS Coexistence check ++ if((pregistrypriv->wifi_spec==1) && (_FALSE == pmlmeinfo->bwmode_updated)) ++ { ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ ++ p = rtw_get_ie(bssid->IEs + _FIXED_IE_LENGTH_, _HT_CAPABILITY_IE_, &len, bssid->IELength - _FIXED_IE_LENGTH_); ++ if(p && len>0) ++ { ++ struct HT_caps_element *pHT_caps; ++ pHT_caps = (struct HT_caps_element *)(p + 2); ++ ++ if(pHT_caps->HT_cap_element.HT_caps_info&BIT(14)) ++ { ++ pmlmepriv->num_FortyMHzIntolerant++; ++ } ++ } ++ else ++ { ++ pmlmepriv->num_sta_no_ht++; ++ } ++ ++ } ++ ++ ++ #if defined(DBG_RX_SIGNAL_DISPLAY_PROCESSING) & 1 ++ if(strcmp(bssid->Ssid.Ssid, DBG_RX_SIGNAL_DISPLAY_SSID_MONITORED) == 0) { ++ DBG_871X("Receiving %s("MAC_FMT", DSConfig:%u) from ch%u with ss:%3u, sq:%3u, RawRSSI:%3ld\n" ++ , bssid->Ssid.Ssid, MAC_ARG(bssid->MacAddress), bssid->Configuration.DSConfig ++ , padapter->mlmeextpriv.channel_set[padapter->mlmeextpriv.sitesurvey_res.channel_idx].ChannelNum ++ , bssid->PhyInfo.SignalStrength, bssid->PhyInfo.SignalQuality, bssid->Rssi ++ ); ++ } ++ #endif ++ ++ // mark bss info receving from nearby channel as SignalQuality 101 ++ if(bssid->Configuration.DSConfig != padapter->mlmeextpriv.channel_set[padapter->mlmeextpriv.sitesurvey_res.channel_idx].ChannelNum) ++ { ++ bssid->PhyInfo.SignalQuality= 101; ++ } ++ ++ return _SUCCESS; ++ ++} ++ ++void start_create_ibss(_adapter* padapter) ++{ ++ unsigned short caps; ++ u32 val32; ++ u8 val8; ++ u8 join_type; ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ WLAN_BSSID_EX *pnetwork = (WLAN_BSSID_EX*)(&(pmlmeinfo->network)); ++ pmlmeext->cur_channel = (u8)pnetwork->Configuration.DSConfig; ++ pmlmeinfo->bcn_interval = get_beacon_interval(pnetwork); ++ ++ //update wireless mode ++ update_wireless_mode(padapter); ++ ++ //udpate capability ++ caps = rtw_get_capability((WLAN_BSSID_EX *)pnetwork); ++ update_capinfo(padapter, caps); ++ if(caps&cap_IBSS)//adhoc master ++ { ++ //set_opmode_cmd(padapter, adhoc);//removed ++ ++ val8 = 0xcf; ++ padapter->HalFunc.SetHwRegHandler(padapter, HW_VAR_SEC_CFG, (u8 *)(&val8)); ++ ++ //switch channel ++ //SelectChannel(padapter, pmlmeext->cur_channel, HAL_PRIME_CHNL_OFFSET_DONT_CARE); ++ set_channel_bwmode(padapter, pmlmeext->cur_channel, HAL_PRIME_CHNL_OFFSET_DONT_CARE, HT_CHANNEL_WIDTH_20); ++ ++ beacon_timing_control(padapter); ++ ++ //set msr to WIFI_FW_ADHOC_STATE ++ pmlmeinfo->state = WIFI_FW_ADHOC_STATE; ++ Set_NETYPE0_MSR(padapter, (pmlmeinfo->state & 0x3)); ++ ++ //issue beacon ++ if(send_beacon(padapter)==_FAIL) ++ { ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_err_,("issuing beacon frame fail....\n")); ++ ++ report_join_res(padapter, -1); ++ pmlmeinfo->state = WIFI_FW_NULL_STATE; ++ } ++ else ++ { ++ padapter->HalFunc.SetHwRegHandler(padapter, HW_VAR_BSSID, padapter->registrypriv.dev_network.MacAddress); ++ join_type = 0; ++ padapter->HalFunc.SetHwRegHandler(padapter, HW_VAR_MLME_JOIN, (u8 *)(&join_type)); ++ ++ report_join_res(padapter, 1); ++ pmlmeinfo->state |= WIFI_FW_ASSOC_SUCCESS; ++ } ++ } ++ else ++ { ++ DBG_871X("start_create_ibss, invalid cap:%x\n", caps); ++ return; ++ } ++ ++} ++ ++void start_clnt_join(_adapter* padapter) ++{ ++ unsigned short caps; ++ u8 val8; ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ WLAN_BSSID_EX *pnetwork = (WLAN_BSSID_EX*)(&(pmlmeinfo->network)); ++ ++ ++ pmlmeext->cur_channel = (u8)pnetwork->Configuration.DSConfig; ++ pmlmeinfo->bcn_interval = get_beacon_interval(pnetwork); ++ ++ //update wireless mode ++ update_wireless_mode(padapter); ++ ++ //udpate capability ++ caps = rtw_get_capability((WLAN_BSSID_EX *)pnetwork); ++ update_capinfo(padapter, caps); ++ if (caps&cap_ESS) ++ { ++ Set_NETYPE0_MSR(padapter, WIFI_FW_STATION_STATE); ++ ++ val8 = (pmlmeinfo->auth_algo == dot11AuthAlgrthm_8021X)? 0xcc: 0xcf; ++ padapter->HalFunc.SetHwRegHandler(padapter, HW_VAR_SEC_CFG, (u8 *)(&val8)); ++ ++ //switch channel ++ set_channel_bwmode(padapter, pmlmeext->cur_channel, pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode); ++ ++ //here wait for receiving the beacon to start auth ++ //and enable a timer ++ set_link_timer(pmlmeext, decide_wait_for_beacon_timeout(pmlmeinfo->bcn_interval)); ++ ++ pmlmeinfo->state = WIFI_FW_AUTH_NULL | WIFI_FW_STATION_STATE; ++ } ++ else if (caps&cap_IBSS) //adhoc client ++ { ++ Set_NETYPE0_MSR(padapter, WIFI_FW_ADHOC_STATE); ++ ++ val8 = 0xcf; ++ padapter->HalFunc.SetHwRegHandler(padapter, HW_VAR_SEC_CFG, (u8 *)(&val8)); ++ ++ //switch channel ++ set_channel_bwmode(padapter, pmlmeext->cur_channel, pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode); ++ ++ beacon_timing_control(padapter); ++ ++ pmlmeinfo->state = WIFI_FW_ADHOC_STATE; ++ ++ report_join_res(padapter, 1); ++ } ++ else ++ { ++ //DBG_8192C("marc: invalid cap:%x\n", caps); ++ return; ++ } ++ ++} ++ ++void start_clnt_auth(_adapter* padapter) ++{ ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ ++ _cancel_timer_ex(&pmlmeext->link_timer); ++ ++ pmlmeinfo->state &= (~WIFI_FW_AUTH_NULL); ++ pmlmeinfo->state |= WIFI_FW_AUTH_STATE; ++ ++ pmlmeinfo->auth_seq = 1; ++ pmlmeinfo->reauth_count = 0; ++ pmlmeinfo->reassoc_count = 0; ++ pmlmeinfo->link_count = 0; ++ ++ ++ // Because of AP's not receiving deauth before ++ // AP may: 1)not response auth or 2)deauth us after link is complete ++ // issue deauth before issuing auth to deal with the situation ++ issue_deauth(padapter, (&(pmlmeinfo->network))->MacAddress, WLAN_REASON_DEAUTH_LEAVING); ++ ++ issue_auth(padapter, NULL, 0); ++ ++ set_link_timer(pmlmeext, REAUTH_TO); ++ ++} ++ ++ ++void start_clnt_assoc(_adapter* padapter) ++{ ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ ++ _cancel_timer_ex(&pmlmeext->link_timer); ++ ++ pmlmeinfo->state &= (~(WIFI_FW_AUTH_NULL | WIFI_FW_AUTH_STATE)); ++ pmlmeinfo->state |= (WIFI_FW_AUTH_SUCCESS | WIFI_FW_ASSOC_STATE); ++ ++ issue_assocreq(padapter); ++ ++ set_link_timer(pmlmeext, REASSOC_TO); ++} ++ ++unsigned int receive_disconnect(_adapter *padapter, unsigned char *MacAddr, unsigned short reason) ++{ ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ ++ //check A3 ++ if (!(_rtw_memcmp(MacAddr, get_my_bssid(&pmlmeinfo->network), ETH_ALEN))) ++ return _SUCCESS; ++ ++ DBG_871X("%s\n", __FUNCTION__); ++ ++ if((pmlmeinfo->state&0x03) == WIFI_FW_STATION_STATE) ++ { ++ if (pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS) ++ { ++ pmlmeinfo->state = WIFI_FW_NULL_STATE; ++ report_del_sta_event(padapter, MacAddr, reason); ++ } ++ else if (pmlmeinfo->state & WIFI_FW_LINKING_STATE) ++ { ++ pmlmeinfo->state = WIFI_FW_NULL_STATE; ++ report_join_res(padapter, -2); ++ } ++ } ++ ++ return _SUCCESS; ++} ++ ++/**************************************************************************** ++ ++Following are the functions to report events ++ ++*****************************************************************************/ ++ ++void report_survey_event(_adapter *padapter, union recv_frame *precv_frame) ++{ ++ struct cmd_obj *pcmd_obj; ++ u8 *pevtcmd; ++ u32 cmdsz; ++ struct survey_event *psurvey_evt; ++ struct C2HEvent_Header *pc2h_evt_hdr; ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct cmd_priv *pcmdpriv = &padapter->cmdpriv; ++ //u8 *pframe = precv_frame->u.hdr.rx_data; ++ //uint len = precv_frame->u.hdr.len; ++ ++ if ((pcmd_obj = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj))) == NULL) ++ { ++ return; ++ } ++ ++ cmdsz = (sizeof(struct survey_event) + sizeof(struct C2HEvent_Header)); ++ if ((pevtcmd = (u8*)rtw_zmalloc(cmdsz)) == NULL) ++ { ++ rtw_mfree((u8 *)pcmd_obj, sizeof(struct cmd_obj)); ++ return; ++ } ++ ++ _rtw_init_listhead(&pcmd_obj->list); ++ ++ pcmd_obj->cmdcode = GEN_CMD_CODE(_Set_MLME_EVT); ++ pcmd_obj->cmdsz = cmdsz; ++ pcmd_obj->parmbuf = pevtcmd; ++ ++ pcmd_obj->rsp = NULL; ++ pcmd_obj->rspsz = 0; ++ ++ pc2h_evt_hdr = (struct C2HEvent_Header*)(pevtcmd); ++ pc2h_evt_hdr->len = sizeof(struct survey_event); ++ pc2h_evt_hdr->ID = GEN_EVT_CODE(_Survey); ++ pc2h_evt_hdr->seq = ATOMIC_INC_RETURN(&pmlmeext->event_seq); ++ ++ psurvey_evt = (struct survey_event*)(pevtcmd + sizeof(struct C2HEvent_Header)); ++ ++ if (collect_bss_info(padapter, precv_frame, (WLAN_BSSID_EX *)&psurvey_evt->bss) == _FAIL) ++ { ++ rtw_mfree((u8 *)pcmd_obj, sizeof(struct cmd_obj)); ++ rtw_mfree((u8 *)pevtcmd, cmdsz); ++ return; ++ } ++ ++ rtw_enqueue_cmd(pcmdpriv, pcmd_obj); ++ ++ pmlmeext->sitesurvey_res.bss_cnt++; ++ ++ return; ++ ++} ++ ++void report_surveydone_event(_adapter *padapter) ++{ ++ struct cmd_obj *pcmd_obj; ++ u8 *pevtcmd; ++ u32 cmdsz; ++ struct surveydone_event *psurveydone_evt; ++ struct C2HEvent_Header *pc2h_evt_hdr; ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct cmd_priv *pcmdpriv = &padapter->cmdpriv; ++ ++ if ((pcmd_obj = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj))) == NULL) ++ { ++ return; ++ } ++ ++ cmdsz = (sizeof(struct surveydone_event) + sizeof(struct C2HEvent_Header)); ++ if ((pevtcmd = (u8*)rtw_zmalloc(cmdsz)) == NULL) ++ { ++ rtw_mfree((u8 *)pcmd_obj, sizeof(struct cmd_obj)); ++ return; ++ } ++ ++ _rtw_init_listhead(&pcmd_obj->list); ++ ++ pcmd_obj->cmdcode = GEN_CMD_CODE(_Set_MLME_EVT); ++ pcmd_obj->cmdsz = cmdsz; ++ pcmd_obj->parmbuf = pevtcmd; ++ ++ pcmd_obj->rsp = NULL; ++ pcmd_obj->rspsz = 0; ++ ++ pc2h_evt_hdr = (struct C2HEvent_Header*)(pevtcmd); ++ pc2h_evt_hdr->len = sizeof(struct surveydone_event); ++ pc2h_evt_hdr->ID = GEN_EVT_CODE(_SurveyDone); ++ pc2h_evt_hdr->seq = ATOMIC_INC_RETURN(&pmlmeext->event_seq); ++ ++ psurveydone_evt = (struct surveydone_event*)(pevtcmd + sizeof(struct C2HEvent_Header)); ++ psurveydone_evt->bss_cnt = pmlmeext->sitesurvey_res.bss_cnt; ++ ++ DBG_871X("survey done event(%x)\n", psurveydone_evt->bss_cnt); ++ ++ rtw_enqueue_cmd(pcmdpriv, pcmd_obj); ++ ++ return; ++ ++} ++ ++void report_join_res(_adapter *padapter, int res) ++{ ++ struct cmd_obj *pcmd_obj; ++ u8 *pevtcmd; ++ u32 cmdsz; ++ struct joinbss_event *pjoinbss_evt; ++ struct C2HEvent_Header *pc2h_evt_hdr; ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ struct cmd_priv *pcmdpriv = &padapter->cmdpriv; ++ ++ if ((pcmd_obj = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj))) == NULL) ++ { ++ return; ++ } ++ ++ cmdsz = (sizeof(struct joinbss_event) + sizeof(struct C2HEvent_Header)); ++ if ((pevtcmd = (u8*)rtw_zmalloc(cmdsz)) == NULL) ++ { ++ rtw_mfree((u8 *)pcmd_obj, sizeof(struct cmd_obj)); ++ return; ++ } ++ ++ _rtw_init_listhead(&pcmd_obj->list); ++ ++ pcmd_obj->cmdcode = GEN_CMD_CODE(_Set_MLME_EVT); ++ pcmd_obj->cmdsz = cmdsz; ++ pcmd_obj->parmbuf = pevtcmd; ++ ++ pcmd_obj->rsp = NULL; ++ pcmd_obj->rspsz = 0; ++ ++ pc2h_evt_hdr = (struct C2HEvent_Header*)(pevtcmd); ++ pc2h_evt_hdr->len = sizeof(struct joinbss_event); ++ pc2h_evt_hdr->ID = GEN_EVT_CODE(_JoinBss); ++ pc2h_evt_hdr->seq = ATOMIC_INC_RETURN(&pmlmeext->event_seq); ++ ++ pjoinbss_evt = (struct joinbss_event*)(pevtcmd + sizeof(struct C2HEvent_Header)); ++ _rtw_memcpy((unsigned char *)(&(pjoinbss_evt->network.network)), &(pmlmeinfo->network), sizeof(WLAN_BSSID_EX)); ++ pjoinbss_evt->network.join_res = pjoinbss_evt->network.aid = res; ++ ++ DBG_871X("report_join_res(%d)\n", res); ++ ++ ++ rtw_joinbss_event_prehandle(padapter, (u8 *)&pjoinbss_evt->network); ++ ++ ++ rtw_enqueue_cmd(pcmdpriv, pcmd_obj); ++ ++ return; ++ ++} ++ ++void report_del_sta_event(_adapter *padapter, unsigned char* MacAddr, unsigned short reason) ++{ ++ struct cmd_obj *pcmd_obj; ++ u8 *pevtcmd; ++ u32 cmdsz; ++ struct stadel_event *pdel_sta_evt; ++ struct C2HEvent_Header *pc2h_evt_hdr; ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ struct cmd_priv *pcmdpriv = &padapter->cmdpriv; ++ ++ if ((pcmd_obj = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj))) == NULL) ++ { ++ return; ++ } ++ ++ cmdsz = (sizeof(struct stadel_event) + sizeof(struct C2HEvent_Header)); ++ if ((pevtcmd = (u8*)rtw_zmalloc(cmdsz)) == NULL) ++ { ++ rtw_mfree((u8 *)pcmd_obj, sizeof(struct cmd_obj)); ++ return; ++ } ++ ++ _rtw_init_listhead(&pcmd_obj->list); ++ ++ pcmd_obj->cmdcode = GEN_CMD_CODE(_Set_MLME_EVT); ++ pcmd_obj->cmdsz = cmdsz; ++ pcmd_obj->parmbuf = pevtcmd; ++ ++ pcmd_obj->rsp = NULL; ++ pcmd_obj->rspsz = 0; ++ ++ pc2h_evt_hdr = (struct C2HEvent_Header*)(pevtcmd); ++ pc2h_evt_hdr->len = sizeof(struct stadel_event); ++ pc2h_evt_hdr->ID = GEN_EVT_CODE(_DelSTA); ++ pc2h_evt_hdr->seq = ATOMIC_INC_RETURN(&pmlmeext->event_seq); ++ ++ pdel_sta_evt = (struct stadel_event*)(pevtcmd + sizeof(struct C2HEvent_Header)); ++ _rtw_memcpy((unsigned char *)(&(pdel_sta_evt->macaddr)), MacAddr, ETH_ALEN); ++ _rtw_memcpy((unsigned char *)(pdel_sta_evt->rsvd),(unsigned char *)(&reason),2); ++ ++ DBG_871X("report_del_sta_event: delete STA\n"); ++ ++ rtw_enqueue_cmd(pcmdpriv, pcmd_obj); ++ ++ return; ++} ++ ++void report_add_sta_event(_adapter *padapter, unsigned char* MacAddr, int cam_idx) ++{ ++ struct cmd_obj *pcmd_obj; ++ u8 *pevtcmd; ++ u32 cmdsz; ++ struct stassoc_event *padd_sta_evt; ++ struct C2HEvent_Header *pc2h_evt_hdr; ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ struct cmd_priv *pcmdpriv = &padapter->cmdpriv; ++ ++ if ((pcmd_obj = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj))) == NULL) ++ { ++ return; ++ } ++ ++ cmdsz = (sizeof(struct stassoc_event) + sizeof(struct C2HEvent_Header)); ++ if ((pevtcmd = (u8*)rtw_zmalloc(cmdsz)) == NULL) ++ { ++ rtw_mfree((u8 *)pcmd_obj, sizeof(struct cmd_obj)); ++ return; ++ } ++ ++ _rtw_init_listhead(&pcmd_obj->list); ++ ++ pcmd_obj->cmdcode = GEN_CMD_CODE(_Set_MLME_EVT); ++ pcmd_obj->cmdsz = cmdsz; ++ pcmd_obj->parmbuf = pevtcmd; ++ ++ pcmd_obj->rsp = NULL; ++ pcmd_obj->rspsz = 0; ++ ++ pc2h_evt_hdr = (struct C2HEvent_Header*)(pevtcmd); ++ pc2h_evt_hdr->len = sizeof(struct stassoc_event); ++ pc2h_evt_hdr->ID = GEN_EVT_CODE(_AddSTA); ++ pc2h_evt_hdr->seq = ATOMIC_INC_RETURN(&pmlmeext->event_seq); ++ ++ padd_sta_evt = (struct stassoc_event*)(pevtcmd + sizeof(struct C2HEvent_Header)); ++ _rtw_memcpy((unsigned char *)(&(padd_sta_evt->macaddr)), MacAddr, ETH_ALEN); ++ padd_sta_evt->cam_id = cam_idx; ++ ++ DBG_871X("report_add_sta_event: add STA\n"); ++ ++ rtw_enqueue_cmd(pcmdpriv, pcmd_obj); ++ ++ return; ++} ++ ++ ++/**************************************************************************** ++ ++Following are the event callback functions ++ ++*****************************************************************************/ ++ ++//for sta/adhoc mode ++void update_sta_info(_adapter *padapter, struct sta_info *psta) ++{ ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ ++ //ERP ++ VCS_update(padapter, psta); ++ ++ ++ //HT ++ if(pmlmepriv->htpriv.ht_option) ++ { ++ psta->htpriv.ht_option = _TRUE; ++ ++ psta->htpriv.ampdu_enable = pmlmepriv->htpriv.ampdu_enable; ++ ++ if (support_short_GI(padapter, &(pmlmeinfo->HT_caps))) ++ psta->htpriv.sgi = _TRUE; ++ ++ psta->qos_option = _TRUE; ++ ++ } ++ else ++ { ++ psta->htpriv.ht_option = _FALSE; ++ ++ psta->htpriv.ampdu_enable = _FALSE; ++ ++ psta->htpriv.sgi = _FALSE; ++ ++ psta->qos_option = _FALSE; ++ ++ } ++ ++ psta->htpriv.bwmode = pmlmeext->cur_bwmode; ++ psta->htpriv.ch_offset = pmlmeext->cur_ch_offset; ++ ++ psta->htpriv.agg_enable_bitmap = 0x0;//reset ++ psta->htpriv.candidate_tid_bitmap = 0x0;//reset ++ ++ ++ //QoS ++ if(pmlmepriv->qospriv.qos_option) ++ psta->qos_option = _TRUE; ++ ++ ++ psta->state = _FW_LINKED; ++ ++} ++ ++u8 null_addr[ETH_ALEN]= {0,0,0,0,0,0}; ++ ++void mlmeext_joinbss_event_callback(_adapter *padapter, int join_res) ++{ ++ struct sta_info *psta, *psta_bmc; ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network); ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ u8 join_type, init_rts_rate; ++ ++ if(join_res < 0) ++ { ++ join_type = 1; ++ padapter->HalFunc.SetHwRegHandler(padapter, HW_VAR_MLME_JOIN, (u8 *)(&join_type)); ++ padapter->HalFunc.SetHwRegHandler(padapter, HW_VAR_BSSID, null_addr); ++ return; ++ } ++ ++ if((pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE) ++ { ++ //for bc/mc ++ psta_bmc = rtw_get_bcmc_stainfo(padapter); ++ if(psta_bmc) ++ { ++ pmlmeinfo->FW_sta_info[psta_bmc->mac_id].psta = psta_bmc; ++ update_bmc_sta_support_rate(padapter, psta_bmc->mac_id); ++ Update_RA_Entry(padapter, psta_bmc->mac_id); ++ } ++ } ++ ++ ++ //turn on dynamic functions ++ Switch_DM_Func(padapter, DYNAMIC_FUNC_DIG|DYNAMIC_FUNC_HP|DYNAMIC_FUNC_SS, _TRUE); ++ ++ // update IOT-releated issue ++ update_IOT_info(padapter); ++ ++ padapter->HalFunc.SetHwRegHandler(padapter, HW_VAR_BASIC_RATE, cur_network->SupportedRates); ++ ++ //BCN interval ++ padapter->HalFunc.SetHwRegHandler(padapter, HW_VAR_BEACON_INTERVAL, (u8 *)(&pmlmeinfo->bcn_interval)); ++ ++ //udpate capability ++ update_capinfo(padapter, pmlmeinfo->capability); ++ ++ //WMM, Update EDCA param ++ WMMOnAssocRsp(padapter); ++ ++ //HT ++ HTOnAssocRsp(padapter); ++ ++ ++ //Set cur_channel&cur_bwmode&cur_ch_offset ++ set_channel_bwmode(padapter, pmlmeext->cur_channel, pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode); ++ ++ ++ psta = rtw_get_stainfo(pstapriv, cur_network->MacAddress); ++ if (psta) //only for infra. mode ++ { ++ pmlmeinfo->FW_sta_info[psta->mac_id].psta = psta; ++ ++ //DBG_871X("set_sta_rate\n"); ++ ++ //set per sta rate after updating HT cap. ++ set_sta_rate(padapter, psta); ++ } ++ ++ join_type = 2; ++ padapter->HalFunc.SetHwRegHandler(padapter, HW_VAR_MLME_JOIN, (u8 *)(&join_type)); ++ ++ if((pmlmeinfo->state&0x03) == WIFI_FW_STATION_STATE) ++ { ++ // correcting TSF ++ correct_TSF(padapter, pmlmeext); ++ ++ //set_link_timer(pmlmeext, DISCONNECT_TO); ++ } ++ ++#ifdef CONFIG_LPS ++ rtw_lps_ctrl_wk_cmd(padapter, LPS_CTRL_CONNECT, 0); ++#endif ++ ++ DBG_871X("=>%s\n", __FUNCTION__); ++ ++} ++ ++void mlmeext_sta_add_event_callback(_adapter *padapter, struct sta_info *psta) ++{ ++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ u8 join_type; ++ ++ DBG_871X("%s\n", __FUNCTION__); ++ ++ if((pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE) ++ { ++ if(pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS)//adhoc master or sta_count>1 ++ { ++ //nothing to do ++ } ++ else//adhoc client ++ { ++ //update TSF Value ++ //update_TSF(pmlmeext, pframe, len); ++ ++ // correcting TSF ++ correct_TSF(padapter, pmlmeext); ++ ++ //start beacon ++ if(send_beacon(padapter)==_FAIL) ++ { ++ pmlmeinfo->FW_sta_info[psta->mac_id].status = 0; ++ ++ pmlmeinfo->state ^= WIFI_FW_ADHOC_STATE; ++ ++ return; ++ } ++ ++ pmlmeinfo->state |= WIFI_FW_ASSOC_SUCCESS; ++ ++ } ++ ++ join_type = 2; ++ padapter->HalFunc.SetHwRegHandler(padapter, HW_VAR_MLME_JOIN, (u8 *)(&join_type)); ++ } ++ ++ pmlmeinfo->FW_sta_info[psta->mac_id].psta = psta; ++ ++ //rate radaptive ++ Update_RA_Entry(padapter, psta->mac_id); ++ ++ //update adhoc sta_info ++ update_sta_info(padapter, psta); ++ ++} ++ ++void mlmeext_sta_del_event_callback(_adapter *padapter) ++{ ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ ++ if (is_client_associated_to_ap(padapter) || is_IBSS_empty(padapter)) ++ { ++ //set_opmode_cmd(padapter, infra_client_with_mlme); ++ ++ //switch to the 20M Hz mode after disconnect ++ pmlmeext->cur_bwmode = HT_CHANNEL_WIDTH_20; ++ pmlmeext->cur_ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; ++ ++ padapter->HalFunc.SetHwRegHandler(padapter, HW_VAR_MLME_DISCONNECT, 0); ++ padapter->HalFunc.SetHwRegHandler(padapter, HW_VAR_BSSID, null_addr); ++ ++ //SelectChannel(padapter, pmlmeext->cur_channel, pmlmeext->cur_ch_offset); ++ set_channel_bwmode(padapter, pmlmeext->cur_channel, pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode); ++ flush_all_cam_entry(padapter); ++ ++ pmlmeinfo->state = WIFI_FW_NULL_STATE; ++ ++ //set MSR to no link state ++ Set_NETYPE0_MSR(padapter, _HW_STATE_NOLINK_); ++ ++ _cancel_timer_ex(&pmlmeext->link_timer); ++ ++ } ++ ++} ++ ++/**************************************************************************** ++ ++Following are the functions for the timer handlers ++ ++*****************************************************************************/ ++ ++void _linked_rx_signal_strehgth_display(_adapter *padapter) ++{ ++ int UndecoratedSmoothedPWDB; ++ DBG_8192C("============ linked status check ===================\n"); ++ DBG_8192C("pathA Rx SNRdb:%d, pathB Rx SNRdb:%d\n",padapter->recvpriv.RxSNRdB[0],padapter->recvpriv.RxSNRdB[1]); ++ DBG_8192C("pathA Rx RSSI:%d,pathB Rx RSSI:%d\n",padapter->recvpriv.RxRssi[0],padapter->recvpriv.RxRssi[1]); ++ ++ DBG_8192C("pathA Rx PWDB:%d\n",padapter->recvpriv.rxpwdb); ++ padapter->HalFunc.GetHalDefVarHandler(padapter, HAL_DEF_UNDERCORATEDSMOOTHEDPWDB, &UndecoratedSmoothedPWDB); ++ DBG_8192C("UndecoratedSmoothedPWDB:%d\n",UndecoratedSmoothedPWDB); ++ DBG_8192C("Rx RSSI:%d\n",padapter->recvpriv.rssi); ++ DBG_8192C("Rx Signal_strength:%d\n",padapter->recvpriv.signal_strength); ++ DBG_8192C("Rx Signal_qual:%d \n",padapter->recvpriv.signal_qual); ++ DBG_8192C("============ linked status check ===================\n"); ++ DBG_8192C(" DIG PATH-A(0x%02x), PATH-B(0x%02x)\n",rtw_read8(padapter,0xc50),rtw_read8(padapter,0xc58)); ++ DBG_8192C(" OFDM -Alarm DA2(0x%04x),DA4(0x%04x),DA6(0x%04x),DA8(0x%04x)\n", ++ rtw_read16(padapter,0xDA2),rtw_read16(padapter,0xDA4),rtw_read16(padapter,0xDA6),rtw_read16(padapter,0xDA8)); ++ ++ DBG_8192C(" CCK -Alarm A5B(0x%02x),A5C(0x%02x)\n",rtw_read8(padapter,0xA5B),rtw_read8(padapter,0xA5C)); ++ DBG_8192C(" FalseAlmCnt_all(%d)\n",padapter->recvpriv.FalseAlmCnt_all); ++} ++ ++void linked_status_chk(_adapter *padapter) ++{ ++ u32 i; ++ struct sta_info *psta; ++ struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); ++ struct recv_priv *precvpriv = &(padapter->recvpriv); ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ struct registry_priv *pregistrypriv = &padapter->registrypriv; ++ ++ if(padapter->bRxRSSIDisplay) ++ _linked_rx_signal_strehgth_display(padapter); ++ ++ if (is_client_associated_to_ap(padapter)) ++ { ++ //linked infrastructure client mode ++ if ((psta = rtw_get_stainfo(pstapriv, pmlmeinfo->network.MacAddress)) != NULL) ++ { ++ #ifdef DBG_EXPIRATION_CHK ++ DBG_871X("%s rx:"STA_PKTS_FMT", BI:%u, retry:%u\n" ++ , __FUNCTION__ ++ , STA_RX_PKTS_ARG(psta) ++ , pmlmeinfo->bcn_interval ++ , pmlmeext->retry ++ ); ++ #endif ++ ++ /*to monitor whether the AP is alive or not*/ ++ if (sta_last_rx_pkts(psta) == sta_rx_pkts(psta)) ++ { ++ // Commented by Albert 2010/07/21 ++ // In this case, there is no any rx packet received by driver. ++ ++ #ifdef DBG_ROAMING_TEST ++ if(pmlmeext->retry<1) ++ #else ++ if(pmlmeext->retry<8)// Alter the retry limit to 8 ++ #endif ++ { ++ if(pmlmeext->retry==0) ++ { ++ #ifdef DBG_CONFIG_ERROR_DETECT ++ if(padapter->HalFunc.sreset_linked_status_check) ++ padapter->HalFunc.sreset_linked_status_check(padapter); ++ #endif ++ ++ // In order to know the AP's current state, try to send the probe request ++ // to trigger the AP to send the probe response. ++ #ifdef CONFIG_P2P ++ if(!rtw_p2p_chk_state(&padapter->wdinfo, P2P_STATE_NONE)) { ++ #ifdef DBG_EXPIRATION_CHK ++ DBG_871X("issue_probereq_p2p to trigger probersp, retry=%d\n", pmlmeext->retry); ++ #endif ++ issue_probereq_p2p(padapter); ++ } else ++ #endif ++ { ++ #ifdef DBG_EXPIRATION_CHK ++ DBG_871X("issue_probereq to trigger probersp, retry=%d\n", pmlmeext->retry); ++ #endif ++ issue_probereq(padapter, &(pmlmeinfo->network.Ssid), 0); ++ issue_probereq(padapter, &(pmlmeinfo->network.Ssid), 0); ++ issue_probereq(padapter, &(pmlmeinfo->network.Ssid), 0); ++ } ++ } ++ ++ pmlmeext->retry++; ++ } ++ else ++ { ++ pmlmeext->retry = 0; ++ DBG_871X("no beacon to call receive_disconnect()\n"); ++ receive_disconnect(padapter, pmlmeinfo->network.MacAddress ++ , 65535// indicate disconnect caused by no rx ++ ); ++ pmlmeinfo->link_count = 0; ++ return; ++ } ++ } ++ else ++ { ++ pmlmeext->retry = 0; ++ sta_update_last_rx_pkts(psta); ++ //set_link_timer(pmlmeext, DISCONNECT_TO); ++ } ++ ++ #ifdef DBG_EXPIRATION_CHK ++ DBG_871X("%s tx_pkts:%llu, link_count:%u\n", __FUNCTION__ ++ , pxmitpriv->tx_pkts ++ , pmlmeinfo->link_count ++ ); ++ #endif ++ ++ /*to send the AP a nulldata if no frame is xmitted in order to keep alive*/ ++ if(pxmitpriv->last_tx_pkts == pxmitpriv->tx_pkts) ++ { ++ if(pmlmeinfo->link_count++ == 0xf) ++ { ++ //DBG_871X("(Interface %d)issue nulldata to keep alive\n",padapter->dvobjpriv.InterfaceNumber); ++ #ifdef DBG_EXPIRATION_CHK ++ DBG_871X("%s issue_nulldata 0\n", __FUNCTION__); ++ #endif ++ issue_nulldata(padapter, 0); ++ pmlmeinfo->link_count = 0; ++ } ++ } ++ else ++ { ++ pxmitpriv->last_tx_pkts = pxmitpriv->tx_pkts; ++ pmlmeinfo->link_count = 0; ++ } ++ ++ } //end of if ((psta = rtw_get_stainfo(pstapriv, passoc_res->network.MacAddress)) != NULL) ++ } ++ else if (is_client_associated_to_ibss(padapter)) ++ { ++ //linked IBSS mode ++ //for each assoc list entry to check the rx pkt counter ++ for (i = IBSS_START_MAC_ID; i < NUM_STA; i++) ++ { ++ if (pmlmeinfo->FW_sta_info[i].status == 1) ++ { ++ psta = pmlmeinfo->FW_sta_info[i].psta; ++ ++ if(NULL==psta) continue; ++ ++ if (pmlmeinfo->FW_sta_info[i].rx_pkt == sta_rx_pkts(psta)) ++ { ++ ++ if(pmlmeinfo->FW_sta_info[i].retry<3) ++ { ++ pmlmeinfo->FW_sta_info[i].retry++; ++ } ++ else ++ { ++ pmlmeinfo->FW_sta_info[i].retry = 0; ++ pmlmeinfo->FW_sta_info[i].status = 0; ++ report_del_sta_event(padapter, psta->hwaddr ++ , 65535// indicate disconnect caused by no rx ++ ); ++ } ++ } ++ else ++ { ++ pmlmeinfo->FW_sta_info[i].retry = 0; ++ pmlmeinfo->FW_sta_info[i].rx_pkt = (u32)sta_rx_pkts(psta); ++ } ++ } ++ } ++ ++ //set_link_timer(pmlmeext, DISCONNECT_TO); ++ ++ } ++ ++} ++ ++void survey_timer_hdl(_adapter *padapter) ++{ ++ struct cmd_obj *ph2c; ++ struct sitesurvey_parm *psurveyPara; ++ struct cmd_priv *pcmdpriv=&padapter->cmdpriv; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++#ifdef CONFIG_P2P ++ struct wifidirect_info *pwdinfo= &(padapter->wdinfo); ++#endif ++ ++ //DBG_8192C("marc: survey timer\n"); ++ ++ //issue rtw_sitesurvey_cmd ++ if (pmlmeext->sitesurvey_res.state > SCAN_START) ++ { ++ if(pmlmeext->sitesurvey_res.state == SCAN_PROCESS) ++ pmlmeext->sitesurvey_res.channel_idx++; ++ ++ if(pmlmeext->scan_abort == _TRUE) ++ { ++ #ifdef CONFIG_P2P ++ if(!rtw_p2p_chk_state(&padapter->wdinfo, P2P_STATE_NONE)) ++ { ++ pwdinfo->find_phase_state_exchange_cnt = P2P_FINDPHASE_EX_CNT; ++ pmlmeext->sitesurvey_res.channel_idx = 3; ++ } ++ else ++ #endif ++ { ++ pmlmeext->sitesurvey_res.channel_idx = pmlmeext->max_chan_nums; ++ } ++ ++ pmlmeext->scan_abort = _FALSE;//reset ++ } ++ ++ if ((ph2c = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj))) == NULL) ++ { ++ goto exit_survey_timer_hdl; ++ } ++ ++ if ((psurveyPara = (struct sitesurvey_parm*)rtw_zmalloc(sizeof(struct sitesurvey_parm))) == NULL) ++ { ++ rtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj)); ++ goto exit_survey_timer_hdl; ++ } ++ ++ init_h2fwcmd_w_parm_no_rsp(ph2c, psurveyPara, GEN_CMD_CODE(_SiteSurvey)); ++ rtw_enqueue_cmd(pcmdpriv, ph2c); ++ } ++ ++ ++exit_survey_timer_hdl: ++ ++ return; ++} ++ ++void link_timer_hdl(_adapter *padapter) ++{ ++ static unsigned int rx_pkt = 0; ++ static u64 tx_cnt = 0; ++ struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ ++ if (pmlmeinfo->state & WIFI_FW_AUTH_NULL) ++ { ++ DBG_871X("link_timer_hdl:no beacon while connecting\n"); ++ pmlmeinfo->state = WIFI_FW_NULL_STATE; ++ report_join_res(padapter, -3); ++ } ++ else if (pmlmeinfo->state & WIFI_FW_AUTH_STATE) ++ { ++ //re-auth timer ++ if (++pmlmeinfo->reauth_count > REAUTH_LIMIT) ++ { ++ //if (pmlmeinfo->auth_algo != dot11AuthAlgrthm_Auto) ++ //{ ++ pmlmeinfo->state = 0; ++ report_join_res(padapter, -1); ++ return; ++ //} ++ //else ++ //{ ++ // pmlmeinfo->auth_algo = dot11AuthAlgrthm_Shared; ++ // pmlmeinfo->reauth_count = 0; ++ //} ++ } ++ ++ DBG_871X("link_timer_hdl: auth timeout and try again\n"); ++ pmlmeinfo->auth_seq = 1; ++ issue_auth(padapter, NULL, 0); ++ set_link_timer(pmlmeext, REAUTH_TO); ++ } ++ else if (pmlmeinfo->state & WIFI_FW_ASSOC_STATE) ++ { ++ //re-assoc timer ++ if (++pmlmeinfo->reassoc_count > REASSOC_LIMIT) ++ { ++ pmlmeinfo->state = WIFI_FW_NULL_STATE; ++ report_join_res(padapter, -2); ++ return; ++ } ++ ++ DBG_871X("link_timer_hdl: assoc timeout and try again\n"); ++ issue_assocreq(padapter); ++ set_link_timer(pmlmeext, REASSOC_TO); ++ } ++#if 0 ++ else if (is_client_associated_to_ap(padapter)) ++ { ++ //linked infrastructure client mode ++ if ((psta = rtw_get_stainfo(pstapriv, pmlmeinfo->network.MacAddress)) != NULL) ++ { ++ /*to monitor whether the AP is alive or not*/ ++ if (rx_pkt == psta->sta_stats.rx_pkts) ++ { ++ receive_disconnect(padapter, pmlmeinfo->network.MacAddress); ++ return; ++ } ++ else ++ { ++ rx_pkt = psta->sta_stats.rx_pkts; ++ set_link_timer(pmlmeext, DISCONNECT_TO); ++ } ++ ++ //update the EDCA paramter according to the Tx/RX mode ++ update_EDCA_param(padapter); ++ ++ /*to send the AP a nulldata if no frame is xmitted in order to keep alive*/ ++ if (pmlmeinfo->link_count++ == 0) ++ { ++ tx_cnt = pxmitpriv->tx_pkts; ++ } ++ else if ((pmlmeinfo->link_count & 0xf) == 0) ++ { ++ if (tx_cnt == pxmitpriv->tx_pkts) ++ { ++ issue_nulldata(padapter, 0); ++ } ++ ++ tx_cnt = pxmitpriv->tx_pkts; ++ } ++ } //end of if ((psta = rtw_get_stainfo(pstapriv, passoc_res->network.MacAddress)) != NULL) ++ } ++ else if (is_client_associated_to_ibss(padapter)) ++ { ++ //linked IBSS mode ++ //for each assoc list entry to check the rx pkt counter ++ for (i = IBSS_START_MAC_ID; i < NUM_STA; i++) ++ { ++ if (pmlmeinfo->FW_sta_info[i].status == 1) ++ { ++ psta = pmlmeinfo->FW_sta_info[i].psta; ++ ++ if (pmlmeinfo->FW_sta_info[i].rx_pkt == psta->sta_stats.rx_pkts) ++ { ++ pmlmeinfo->FW_sta_info[i].status = 0; ++ report_del_sta_event(padapter, psta->hwaddr); ++ } ++ else ++ { ++ pmlmeinfo->FW_sta_info[i].rx_pkt = psta->sta_stats.rx_pkts; ++ } ++ } ++ } ++ ++ set_link_timer(pmlmeext, DISCONNECT_TO); ++ } ++#endif ++ ++ return; ++} ++ ++void addba_timer_hdl(struct sta_info *psta) ++{ ++ u8 bitmap; ++ u16 tid; ++ struct ht_priv *phtpriv; ++ ++ if(!psta) ++ return; ++ ++ phtpriv = &psta->htpriv; ++ ++ if((phtpriv->ht_option==_TRUE) && (phtpriv->ampdu_enable==_TRUE)) ++ { ++ if(phtpriv->candidate_tid_bitmap) ++ phtpriv->candidate_tid_bitmap=0x0; ++ ++ } ++ ++} ++ ++u8 NULL_hdl(_adapter *padapter, u8 *pbuf) ++{ ++ return H2C_SUCCESS; ++} ++ ++u8 setopmode_hdl(_adapter *padapter, u8 *pbuf) ++{ ++ u8 type; ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ struct setopmode_parm *psetop = (struct setopmode_parm *)pbuf; ++ ++ if(psetop->mode == Ndis802_11APMode) ++ { ++ pmlmeinfo->state = WIFI_FW_AP_STATE; ++ type = _HW_STATE_AP_; ++#ifdef CONFIG_NATIVEAP_MLME ++ //start_ap_mode(padapter); ++#endif ++ } ++ else if(psetop->mode == Ndis802_11Infrastructure) ++ { ++ type = _HW_STATE_STATION_; ++ } ++ else if(psetop->mode == Ndis802_11IBSS) ++ { ++ type = _HW_STATE_ADHOC_; ++ } ++ else ++ { ++ type = _HW_STATE_NOLINK_; ++ } ++ ++ padapter->HalFunc.SetHwRegHandler(padapter, HW_VAR_SET_OPMODE, (u8 *)(&type)); ++ //Set_NETYPE0_MSR(padapter, type); ++ ++ return H2C_SUCCESS; ++ ++} ++ ++u8 createbss_hdl(_adapter *padapter, u8 *pbuf) ++{ ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ WLAN_BSSID_EX *pnetwork = (WLAN_BSSID_EX*)(&(pmlmeinfo->network)); ++ struct joinbss_parm *pparm = (struct joinbss_parm *)pbuf; ++ u32 initialgain; ++ ++ ++ if(pparm->network.InfrastructureMode == Ndis802_11APMode) ++ { ++#ifdef CONFIG_AP_MODE ++ ++ if(pmlmeinfo->state == WIFI_FW_AP_STATE) ++ { ++ //todo: ++ return H2C_SUCCESS; ++ } ++#endif ++ } ++ ++ //below is for ad-hoc master ++ if(pparm->network.InfrastructureMode == Ndis802_11IBSS) ++ { ++ rtw_joinbss_reset(padapter); ++ ++ pmlmeext->cur_bwmode = HT_CHANNEL_WIDTH_20; ++ pmlmeext->cur_ch_offset= HAL_PRIME_CHNL_OFFSET_DONT_CARE; ++ pmlmeinfo->ERP_enable = 0; ++ pmlmeinfo->WMM_enable = 0; ++ pmlmeinfo->HT_enable = 0; ++ pmlmeinfo->HT_caps_enable = 0; ++ pmlmeinfo->HT_info_enable = 0; ++ pmlmeinfo->agg_enable_bitmap = 0; ++ pmlmeinfo->candidate_tid_bitmap = 0; ++ ++ //disable dynamic functions, such as high power, DIG ++ Save_DM_Func_Flag(padapter); ++ Switch_DM_Func(padapter, DYNAMIC_FUNC_DISABLE, _FALSE); ++ ++ //config the initial gain under linking, need to write the BB registers ++ initialgain = 0x1E; ++ padapter->HalFunc.SetHwRegHandler(padapter, HW_VAR_INITIAL_GAIN, (u8 *)(&initialgain)); ++ ++ //cancel link timer ++ _cancel_timer_ex(&pmlmeext->link_timer); ++ ++ //clear CAM ++ flush_all_cam_entry(padapter); ++ ++ _rtw_memcpy(pnetwork, pbuf, FIELD_OFFSET(WLAN_BSSID_EX, IELength)); ++ pnetwork->IELength = ((WLAN_BSSID_EX *)pbuf)->IELength; ++ ++ if(pnetwork->IELength>MAX_IE_SZ)//Check pbuf->IELength ++ return H2C_PARAMETERS_ERROR; ++ ++ _rtw_memcpy(pnetwork->IEs, ((WLAN_BSSID_EX *)pbuf)->IEs, pnetwork->IELength); ++ ++ start_create_ibss(padapter); ++ ++ } ++ ++ return H2C_SUCCESS; ++ ++} ++ ++u8 join_cmd_hdl(_adapter *padapter, u8 *pbuf) ++{ ++ u8 join_type; ++ PNDIS_802_11_VARIABLE_IEs pIE; ++ struct registry_priv *pregpriv = &padapter->registrypriv; ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ WLAN_BSSID_EX *pnetwork = (WLAN_BSSID_EX*)(&(pmlmeinfo->network)); ++ struct joinbss_parm *pparm = (struct joinbss_parm *)pbuf; ++ u32 acparm, initialgain, i; ++ ++ //check already connecting to AP or not ++ if (pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS) ++ { ++ if (pmlmeinfo->state & WIFI_FW_STATION_STATE) ++ { ++ issue_deauth(padapter, pnetwork->MacAddress, WLAN_REASON_DEAUTH_LEAVING); ++ } ++ ++ pmlmeinfo->state = WIFI_FW_NULL_STATE; ++ ++ //clear CAM ++ flush_all_cam_entry(padapter); ++ ++ _cancel_timer_ex(&pmlmeext->link_timer); ++ ++ //set MSR to nolink ++ Set_NETYPE0_MSR(padapter, _HW_STATE_NOLINK_); ++ ++ padapter->HalFunc.SetHwRegHandler(padapter, HW_VAR_MLME_DISCONNECT, 0); ++ } ++ ++#ifdef CONFIG_ANTENNA_DIVERSITY ++ rtw_antenna_select_cmd(padapter, pparm->network.PhyInfo.Optimum_antenna, _FALSE); ++#endif ++ ++ rtw_joinbss_reset(padapter); ++ ++ pmlmeext->cur_bwmode = HT_CHANNEL_WIDTH_20; ++ pmlmeext->cur_ch_offset= HAL_PRIME_CHNL_OFFSET_DONT_CARE; ++ pmlmeinfo->ERP_enable = 0; ++ pmlmeinfo->WMM_enable = 0; ++ pmlmeinfo->HT_enable = 0; ++ pmlmeinfo->HT_caps_enable = 0; ++ pmlmeinfo->HT_info_enable = 0; ++ pmlmeinfo->agg_enable_bitmap = 0; ++ pmlmeinfo->candidate_tid_bitmap = 0; ++ pmlmeinfo->bwmode_updated = _FALSE; ++ //pmlmeinfo->assoc_AP_vendor = maxAP; ++ ++ _rtw_memcpy(pnetwork, pbuf, FIELD_OFFSET(WLAN_BSSID_EX, IELength)); ++ pnetwork->IELength = ((WLAN_BSSID_EX *)pbuf)->IELength; ++ ++ if(pnetwork->IELength>MAX_IE_SZ)//Check pbuf->IELength ++ return H2C_PARAMETERS_ERROR; ++ ++ _rtw_memcpy(pnetwork->IEs, ((WLAN_BSSID_EX *)pbuf)->IEs, pnetwork->IELength); ++ ++ //Check AP vendor to move rtw_joinbss_cmd() ++ //pmlmeinfo->assoc_AP_vendor = check_assoc_AP(pnetwork->IEs, pnetwork->IELength); ++ ++ for (i = sizeof(NDIS_802_11_FIXED_IEs); i < pnetwork->IELength;) ++ { ++ pIE = (PNDIS_802_11_VARIABLE_IEs)(pnetwork->IEs + i); ++ ++ switch (pIE->ElementID) ++ { ++ case _VENDOR_SPECIFIC_IE_://Get WMM IE. ++ if ( _rtw_memcmp(pIE->data, WMM_OUI, 4) ) ++ { ++ pmlmeinfo->WMM_enable = 1; ++ } ++ break; ++ ++ case _HT_CAPABILITY_IE_: //Get HT Cap IE. ++ pmlmeinfo->HT_caps_enable = 1; ++ break; ++ ++ case _HT_EXTRA_INFO_IE_: //Get HT Info IE. ++ pmlmeinfo->HT_info_enable = 1; ++ ++ //spec case only for cisco's ap because cisco's ap issue assoc rsp using mcs rate @40MHz or @20MHz ++ //if(pmlmeinfo->assoc_AP_vendor == ciscoAP) ++ { ++ struct HT_info_element *pht_info = (struct HT_info_element *)(pIE->data); ++ ++ if ((pregpriv->cbw40_enable) && (pht_info->infos[0] & BIT(2))) ++ { ++ //switch to the 40M Hz mode according to the AP ++ pmlmeext->cur_bwmode = HT_CHANNEL_WIDTH_40; ++ switch (pht_info->infos[0] & 0x3) ++ { ++ case 1: ++ pmlmeext->cur_ch_offset = HAL_PRIME_CHNL_OFFSET_LOWER; ++ break; ++ ++ case 3: ++ pmlmeext->cur_ch_offset = HAL_PRIME_CHNL_OFFSET_UPPER; ++ break; ++ ++ default: ++ pmlmeext->cur_ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; ++ break; ++ } ++ ++ DBG_871X("set ch/bw before connected\n"); ++ } ++ } ++ break; ++ ++ default: ++ break; ++ } ++ ++ i += (pIE->Length + 2); ++ } ++#if 0 ++ if (padapter->registrypriv.wifi_spec) { ++ // for WiFi test, follow WMM test plan spec ++ acparm = 0x002F431C; // VO ++ padapter->HalFunc.SetHwRegHandler(padapter, HW_VAR_AC_PARAM_VO, (u8 *)(&acparm)); ++ acparm = 0x005E541C; // VI ++ padapter->HalFunc.SetHwRegHandler(padapter, HW_VAR_AC_PARAM_VI, (u8 *)(&acparm)); ++ acparm = 0x0000A525; // BE ++ padapter->HalFunc.SetHwRegHandler(padapter, HW_VAR_AC_PARAM_BE, (u8 *)(&acparm)); ++ acparm = 0x0000A549; // BK ++ padapter->HalFunc.SetHwRegHandler(padapter, HW_VAR_AC_PARAM_BK, (u8 *)(&acparm)); ++ ++ // for WiFi test, mixed mode with intel STA under bg mode throughput issue ++ if (padapter->mlmepriv.htpriv.ht_option == _FALSE){ ++ acparm = 0x00004320; ++ padapter->HalFunc.SetHwRegHandler(padapter, HW_VAR_AC_PARAM_BE, (u8 *)(&acparm)); ++ } ++ } ++ else { ++ acparm = 0x002F3217; // VO ++ padapter->HalFunc.SetHwRegHandler(padapter, HW_VAR_AC_PARAM_VO, (u8 *)(&acparm)); ++ acparm = 0x005E4317; // VI ++ padapter->HalFunc.SetHwRegHandler(padapter, HW_VAR_AC_PARAM_VI, (u8 *)(&acparm)); ++ acparm = 0x00105320; // BE ++ padapter->HalFunc.SetHwRegHandler(padapter, HW_VAR_AC_PARAM_BE, (u8 *)(&acparm)); ++ acparm = 0x0000A444; // BK ++ padapter->HalFunc.SetHwRegHandler(padapter, HW_VAR_AC_PARAM_BK, (u8 *)(&acparm)); ++ } ++#endif ++ //disable dynamic functions, such as high power, DIG ++ //Switch_DM_Func(padapter, DYNAMIC_FUNC_DISABLE, _FALSE); ++ ++ //config the initial gain under linking, need to write the BB registers ++ initialgain = 0x1E; ++ padapter->HalFunc.SetHwRegHandler(padapter, HW_VAR_INITIAL_GAIN, (u8 *)(&initialgain)); ++ ++ padapter->HalFunc.SetHwRegHandler(padapter, HW_VAR_BSSID, pmlmeinfo->network.MacAddress); ++ join_type = 0; ++ padapter->HalFunc.SetHwRegHandler(padapter, HW_VAR_MLME_JOIN, (u8 *)(&join_type)); ++ ++ //cancel link timer ++ _cancel_timer_ex(&pmlmeext->link_timer); ++ ++ start_clnt_join(padapter); ++ ++ return H2C_SUCCESS; ++ ++} ++ ++u8 disconnect_hdl(_adapter *padapter, unsigned char *pbuf) ++{ ++ struct disconnect_parm *pparm = (struct disconnect_parm *)pbuf; ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ WLAN_BSSID_EX *pnetwork = (WLAN_BSSID_EX*)(&(pmlmeinfo->network)); ++ u8 val8; ++ ++ if (is_client_associated_to_ap(padapter)) ++ { ++ issue_deauth(padapter, pnetwork->MacAddress, WLAN_REASON_DEAUTH_LEAVING); ++ } ++ ++ //set_opmode_cmd(padapter, infra_client_with_mlme); ++ ++ pmlmeinfo->state = WIFI_FW_NULL_STATE; ++ ++ //switch to the 20M Hz mode after disconnect ++ pmlmeext->cur_bwmode = HT_CHANNEL_WIDTH_20; ++ pmlmeext->cur_ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; ++ ++ //set MSR to no link state ++ Set_NETYPE0_MSR(padapter, _HW_STATE_NOLINK_); ++ ++ padapter->HalFunc.SetHwRegHandler(padapter, HW_VAR_MLME_DISCONNECT, 0); ++ padapter->HalFunc.SetHwRegHandler(padapter, HW_VAR_BSSID, null_addr); ++ ++ if(((pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE) || ((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE)) ++ { ++ //Stop BCN ++ val8 = 0; ++ padapter->HalFunc.SetHwRegHandler(padapter, HW_VAR_BCN_FUNC, (u8 *)(&val8)); ++ } ++ ++ pmlmeinfo->state = WIFI_FW_NULL_STATE; ++ ++ set_channel_bwmode(padapter, pmlmeext->cur_channel, pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode); ++ ++ flush_all_cam_entry(padapter); ++ ++ _cancel_timer_ex(&pmlmeext->link_timer); ++ ++ return H2C_SUCCESS; ++} ++ ++u8 sitesurvey_cmd_hdl(_adapter *padapter, u8 *pbuf) ++{ ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct sitesurvey_parm *pparm = (struct sitesurvey_parm *)pbuf; ++ u8 val8; ++ u32 initialgain; ++ u32 i; ++ ++#ifdef CONFIG_P2P ++ struct wifidirect_info* pwdinfo = &padapter->wdinfo; ++#endif ++ ++ if (pmlmeext->sitesurvey_res.state == SCAN_DISABLE) ++ { ++ //for first time sitesurvey_cmd ++ pmlmeext->sitesurvey_res.state = SCAN_START; ++ pmlmeext->sitesurvey_res.bss_cnt = 0; ++ pmlmeext->sitesurvey_res.channel_idx = 0; ++ ++ for(i=0;issid[i].SsidLength)) { ++ _rtw_memcpy(pmlmeext->sitesurvey_res.ssid[i].Ssid, pparm->ssid[i].Ssid, IW_ESSID_MAX_SIZE); ++ pmlmeext->sitesurvey_res.ssid[i].SsidLength= le32_to_cpu(pparm->ssid[i].SsidLength); ++ } else { ++ pmlmeext->sitesurvey_res.ssid[i].SsidLength= 0; ++ } ++ } ++ ++ pmlmeext->sitesurvey_res.scan_mode = le32_to_cpu(pparm->scan_mode); ++ ++ //issue null data if associating to the AP ++ if (is_client_associated_to_ap(padapter) == _TRUE) ++ { ++ pmlmeext->sitesurvey_res.state = SCAN_TXNULL; ++ ++ issue_nulldata(padapter, 1); ++ issue_nulldata(padapter, 1); ++ ++ //delay 50ms to protect nulldata(1). ++ set_survey_timer(pmlmeext, 50); ++ ++ return H2C_SUCCESS; ++ } ++ } ++ ++ if ((pmlmeext->sitesurvey_res.state == SCAN_START) || (pmlmeext->sitesurvey_res.state == SCAN_TXNULL)) ++ { ++#ifdef CONFIG_FIND_BEST_CHANNEL ++#if 0 ++ for (i=0; pmlmeext->channel_set[i].ChannelNum !=0; i++) { ++ pmlmeext->channel_set[i].rx_count = 0; ++ } ++#endif ++#endif /* CONFIG_FIND_BEST_CHANNEL */ ++ ++ //disable dynamic functions, such as high power, DIG ++ Save_DM_Func_Flag(padapter); ++ Switch_DM_Func(padapter, DYNAMIC_FUNC_DISABLE, _FALSE); ++ ++ //config the initial gain under scaning, need to write the BB registers ++#ifdef CONFIG_IOCTL_CFG80211 ++ if((wdev_to_priv(padapter->rtw_wdev))->p2p_enabled == _TRUE) ++ initialgain = 0x27; ++ else ++#endif ++ initialgain = 0x17; ++#ifdef CONFIG_P2P ++ if(!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE) && !rtw_p2p_chk_state(pwdinfo, P2P_STATE_IDLE)) ++ initialgain = 0x27; ++#endif //CONFIG_P2P ++ ++ padapter->HalFunc.SetHwRegHandler(padapter, HW_VAR_INITIAL_GAIN, (u8 *)(&initialgain)); ++ ++ //set MSR to no link state ++ Set_NETYPE0_MSR(padapter, _HW_STATE_NOLINK_); ++ ++ val8 = 1; //before site survey ++ padapter->HalFunc.SetHwRegHandler(padapter, HW_VAR_MLME_SITESURVEY, (u8 *)(&val8)); ++ ++ // Commented by Albert 2011/08/05 ++ // The pre_tx_scan_timer_process will issue the scan H2C command. ++ // However, the driver should NOT enter the scanning mode at that time. ++ pmlmeext->sitesurvey_res.state = SCAN_PROCESS; ++ } ++ ++ site_survey(padapter); ++ ++ return H2C_SUCCESS; ++ ++} ++ ++u8 setauth_hdl(_adapter *padapter, unsigned char *pbuf) ++{ ++ struct setauth_parm *pparm = (struct setauth_parm *)pbuf; ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ ++ if (pparm->mode < 4) ++ { ++ pmlmeinfo->auth_algo = pparm->mode; ++ } ++ ++ return H2C_SUCCESS; ++} ++ ++u8 setkey_hdl(_adapter *padapter, u8 *pbuf) ++{ ++ unsigned short ctrl; ++ struct setkey_parm *pparm = (struct setkey_parm *)pbuf; ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ unsigned char null_sta[] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00}; ++ ++ //main tx key for wep. ++ if(pparm->set_tx) ++ pmlmeinfo->key_index = pparm->keyid; ++ ++ //write cam ++ ctrl = BIT(15) | ((pparm->algorithm) << 2) | pparm->keyid; ++ ++ write_cam(padapter, pparm->keyid, ctrl, null_sta, pparm->key); ++ ++ return H2C_SUCCESS; ++} ++ ++u8 set_stakey_hdl(_adapter *padapter, u8 *pbuf) ++{ ++ unsigned short ctrl=0; ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ struct set_stakey_parm *pparm = (struct set_stakey_parm *)pbuf; ++#ifdef CONFIG_TDLS ++ struct tdls_info *ptdlsinfo = &padapter->tdlsinfo; ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ struct sta_info *psta; ++#endif ++ ++ if((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE) ++ { ++ unsigned char cam_id;//cam_entry ++ struct sta_info *psta; ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ ++ psta = rtw_get_stainfo(pstapriv, pparm->addr); ++ if(psta) ++ { ++ ctrl = (BIT(15) | ((pparm->algorithm) << 2)); ++ ++ DBG_8192C("r871x_set_stakey_hdl(): enc_algorithm=%d\n", pparm->algorithm); ++ ++ if((psta->mac_id<1) || (psta->mac_id>(NUM_STA-4))) ++ { ++ DBG_8192C("r871x_set_stakey_hdl():set_stakey failed, mac_id(aid)=%d\n", psta->mac_id); ++ return H2C_REJECTED; ++ } ++ ++ cam_id = (psta->mac_id + 3);//0~3 for default key, cmd_id=macid + 3, macid=aid+1; ++ ++ DBG_8192C("Write CAM, mac_addr=%x:%x:%x:%x:%x:%x, cam_entry=%d\n", pparm->addr[0], ++ pparm->addr[1], pparm->addr[2], pparm->addr[3], pparm->addr[4], ++ pparm->addr[5], cam_id); ++ ++ write_cam(padapter, cam_id, ctrl, pparm->addr, pparm->key); ++ ++ return H2C_SUCCESS_RSP; ++ ++ } ++ else ++ { ++ DBG_8192C("r871x_set_stakey_hdl(): sta has been free\n"); ++ return H2C_REJECTED; ++ } ++ ++ } ++ ++ //below for sta mode ++ ++ ctrl = BIT(15) | ((pparm->algorithm) << 2); ++ ++#ifdef CONFIG_TDLS ++ if(ptdlsinfo->cam_entry_to_clear!=0){ ++ clear_cam_entry(padapter, ptdlsinfo->cam_entry_to_clear); ++ ptdlsinfo->cam_entry_to_clear=0; ++ ++ return H2C_SUCCESS; ++ } ++ ++ psta = rtw_get_stainfo(pstapriv, pparm->addr);//Get TDLS Peer STA ++ if( psta->tdls_sta_state&TDLS_LINKED_STATE ){ ++ write_cam(padapter, psta->cam_entry, ctrl, pparm->addr, pparm->key); ++ } ++ else ++#endif ++ write_cam(padapter, 5, ctrl, pparm->addr, pparm->key); ++ ++ pmlmeinfo->enc_algo = pparm->algorithm; ++ ++ return H2C_SUCCESS; ++} ++ ++u8 add_ba_hdl(_adapter *padapter, unsigned char *pbuf) ++{ ++ struct addBaReq_parm *pparm = (struct addBaReq_parm *)pbuf; ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ ++ struct sta_info *psta = rtw_get_stainfo(&padapter->stapriv, pparm->addr); ++ ++ if(!psta) ++ return H2C_SUCCESS; ++ ++ ++ if (((pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS) && (pmlmeinfo->HT_enable)) || ++ ((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE)) ++ { ++ //pmlmeinfo->ADDBA_retry_count = 0; ++ //pmlmeinfo->candidate_tid_bitmap |= (0x1 << pparm->tid); ++ //psta->htpriv.candidate_tid_bitmap |= BIT(pparm->tid); ++ issue_action_BA(padapter, pparm->addr, RTW_WLAN_ACTION_ADDBA_REQ, (u16)pparm->tid); ++ //_set_timer(&pmlmeext->ADDBA_timer, ADDBA_TO); ++ _set_timer(&psta->addba_retry_timer, ADDBA_TO); ++ } ++ else ++ { ++ psta->htpriv.candidate_tid_bitmap &= ~BIT(pparm->tid); ++ } ++ ++ return H2C_SUCCESS; ++} ++ ++u8 set_tx_beacon_cmd(_adapter* padapter) ++{ ++ struct cmd_obj *ph2c; ++ struct Tx_Beacon_param *ptxBeacon_parm; ++ struct cmd_priv *pcmdpriv = &(padapter->cmdpriv); ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ u8 res = _SUCCESS; ++ int len_diff = 0; ++ ++_func_enter_; ++ ++ if ((ph2c = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj))) == NULL) ++ { ++ res= _FAIL; ++ goto exit; ++ } ++ ++ if ((ptxBeacon_parm = (struct Tx_Beacon_param *)rtw_zmalloc(sizeof(struct Tx_Beacon_param))) == NULL) ++ { ++ rtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj)); ++ res= _FAIL; ++ goto exit; ++ } ++ ++ _rtw_memcpy(&(ptxBeacon_parm->network), &(pmlmeinfo->network), sizeof(WLAN_BSSID_EX)); ++ ++ len_diff = update_hidden_ssid( ++ ptxBeacon_parm->network.IEs+_BEACON_IE_OFFSET_ ++ , ptxBeacon_parm->network.IELength-_BEACON_IE_OFFSET_ ++ , pmlmeinfo->hidden_ssid_mode ++ ); ++ ptxBeacon_parm->network.IELength += len_diff; ++ ++ init_h2fwcmd_w_parm_no_rsp(ph2c, ptxBeacon_parm, GEN_CMD_CODE(_TX_Beacon)); ++ ++ res = rtw_enqueue_cmd(pcmdpriv, ph2c); ++ ++ ++exit: ++ ++_func_exit_; ++ ++ return res; ++} ++ ++ ++u8 mlme_evt_hdl(_adapter *padapter, unsigned char *pbuf) ++{ ++ u8 evt_code, evt_seq; ++ u16 evt_sz; ++ uint *peventbuf; ++ void (*event_callback)(_adapter *dev, u8 *pbuf); ++ struct evt_priv *pevt_priv = &(padapter->evtpriv); ++ ++ peventbuf = (uint*)pbuf; ++ evt_sz = (u16)(*peventbuf&0xffff); ++ evt_seq = (u8)((*peventbuf>>24)&0x7f); ++ evt_code = (u8)((*peventbuf>>16)&0xff); ++ ++ ++ #ifdef CHECK_EVENT_SEQ ++ // checking event sequence... ++ if (evt_seq != (ATOMIC_READ(&pevt_priv->event_seq) & 0x7f) ) ++ { ++ RT_TRACE(_module_rtl871x_cmd_c_,_drv_info_,("Evetn Seq Error! %d vs %d\n", (evt_seq & 0x7f), (ATOMIC_READ(&pevt_priv->event_seq) & 0x7f))); ++ ++ pevt_priv->event_seq = (evt_seq+1)&0x7f; ++ ++ goto _abort_event_; ++ } ++ #endif ++ ++ // checking if event code is valid ++ if (evt_code >= MAX_C2HEVT) ++ { ++ RT_TRACE(_module_rtl871x_cmd_c_,_drv_err_,("\nEvent Code(%d) mismatch!\n", evt_code)); ++ goto _abort_event_; ++ } ++ ++ // checking if event size match the event parm size ++ if ((wlanevents[evt_code].parmsize != 0) && ++ (wlanevents[evt_code].parmsize != evt_sz)) ++ { ++ ++ RT_TRACE(_module_rtl871x_cmd_c_,_drv_err_,("\nEvent(%d) Parm Size mismatch (%d vs %d)!\n", ++ evt_code, wlanevents[evt_code].parmsize, evt_sz)); ++ goto _abort_event_; ++ ++ } ++ ++ ATOMIC_INC(&pevt_priv->event_seq); ++ ++ peventbuf += 2; ++ ++ if(peventbuf) ++ { ++ event_callback = wlanevents[evt_code].event_callback; ++ event_callback(padapter, (u8*)peventbuf); ++ ++ pevt_priv->evt_done_cnt++; ++ } ++ ++ ++_abort_event_: ++ ++ ++ return H2C_SUCCESS; ++ ++} ++ ++u8 h2c_msg_hdl(_adapter *padapter, unsigned char *pbuf) ++{ ++ if(!pbuf) ++ return H2C_PARAMETERS_ERROR; ++ ++ return H2C_SUCCESS; ++} ++ ++ ++u8 tx_beacon_hdl(_adapter *padapter, unsigned char *pbuf) ++{ ++ if(send_beacon(padapter)==_FAIL) ++ { ++ DBG_871X("issue_beacon, fail!\n"); ++ return H2C_PARAMETERS_ERROR; ++ } ++#ifdef CONFIG_AP_MODE ++ else //tx bc/mc frames after update TIM ++ { ++ _irqL irqL; ++ struct sta_info *psta_bmc; ++ _list *xmitframe_plist, *xmitframe_phead; ++ struct xmit_frame *pxmitframe=NULL; ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ ++ //for BC/MC Frames ++ psta_bmc = rtw_get_bcmc_stainfo(padapter); ++ if(!psta_bmc) ++ return H2C_SUCCESS; ++ ++ if((pstapriv->tim_bitmap&BIT(0)) && (psta_bmc->sleepq_len>0)) ++ { ++#ifndef CONFIG_PCI_HCI ++ rtw_msleep_os(10);// 10ms, ATIM(HIQ) Windows ++#endif ++ _enter_critical_bh(&psta_bmc->sleep_q.lock, &irqL); ++ ++ xmitframe_phead = get_list_head(&psta_bmc->sleep_q); ++ xmitframe_plist = get_next(xmitframe_phead); ++ ++ while ((rtw_end_of_queue_search(xmitframe_phead, xmitframe_plist)) == _FALSE) ++ { ++ pxmitframe = LIST_CONTAINOR(xmitframe_plist, struct xmit_frame, list); ++ ++ xmitframe_plist = get_next(xmitframe_plist); ++ ++ rtw_list_delete(&pxmitframe->list); ++ ++ psta_bmc->sleepq_len--; ++ if(psta_bmc->sleepq_len>0) ++ pxmitframe->attrib.mdata = 1; ++ else ++ pxmitframe->attrib.mdata = 0; ++ ++ pxmitframe->attrib.triggered=1; ++ ++ pxmitframe->attrib.qsel = 0x11;//HIQ ++ ++ if(padapter->HalFunc.hal_xmit(padapter, pxmitframe) == _TRUE) ++ { ++ rtw_os_xmit_complete(padapter, pxmitframe); ++ } ++ ++ //pstapriv->tim_bitmap &= ~BIT(0); ++ ++ } ++ ++ _exit_critical_bh(&psta_bmc->sleep_q.lock, &irqL); ++ ++ } ++ ++ } ++#endif ++ ++ return H2C_SUCCESS; ++ ++} ++ ++#ifdef CONFIG_AP_MODE ++ ++void init_mlme_ap_info(_adapter *padapter) ++{ ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ ++ _rtw_spinlock_init(&pmlmepriv->bcn_update_lock); ++ ++ //pmlmeext->bstart_bss = _FALSE; ++ ++ start_ap_mode(padapter); ++} ++ ++void free_mlme_ap_info(_adapter *padapter) ++{ ++ _irqL irqL; ++ struct sta_info *psta=NULL; ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ ++ //stop_ap_mode(padapter); ++ ++ pmlmepriv->update_bcn = _FALSE; ++ pmlmeext->bstart_bss = _FALSE; ++ ++ rtw_sta_flush(padapter); ++ ++ pmlmeinfo->state = _HW_STATE_NOLINK_; ++ ++ //free_assoc_sta_resources ++ rtw_free_all_stainfo(padapter); ++ ++ //free bc/mc sta_info ++ psta = rtw_get_bcmc_stainfo(padapter); ++ _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL); ++ rtw_free_stainfo(padapter, psta); ++ _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL); ++ ++ ++ _rtw_spinlock_free(&pmlmepriv->bcn_update_lock); ++ ++} ++ ++static void update_BCNTIM(_adapter *padapter) ++{ ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ WLAN_BSSID_EX *pnetwork = (WLAN_BSSID_EX *)&pmlmepriv->cur_network.network; ++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ WLAN_BSSID_EX *pnetwork_mlmeext = &(pmlmeinfo->network); ++ unsigned char *src_ie = pnetwork->IEs; ++ unsigned int src_ielen = pnetwork->IELength; ++ unsigned char *dst_ie = pnetwork_mlmeext->IEs; ++ ++ ++ //update TIM IE ++ //if(pstapriv->tim_bitmap) ++ if(_TRUE) ++ { ++ u8 *p, ie_len; ++ u16 tim_bitmap_le; ++ u32 tmp_len, head_len=0; ++ ++ tim_bitmap_le = cpu_to_le16(pstapriv->tim_bitmap); ++ ++ //calucate head_len ++ head_len = _FIXED_IE_LENGTH_; ++ head_len += pnetwork->Ssid.SsidLength + 2; ++ ++ // get supported rates len ++ p = rtw_get_ie(src_ie + _BEACON_IE_OFFSET_, _SUPPORTEDRATES_IE_, &tmp_len, (pnetwork->IELength - _BEACON_IE_OFFSET_)); ++ if (p != NULL) ++ { ++ head_len += tmp_len+2; ++ } ++ ++ //DS Parameter Set IE, len=3 ++ head_len += 3; ++ ++ //copy head offset ++ _rtw_memcpy(dst_ie, src_ie, head_len); ++ ++ ++ //append TIM IE from head_len offset ++ dst_ie+=head_len; ++ ++ *dst_ie++=_TIM_IE_; ++ ++ if((pstapriv->tim_bitmap&0xff00) && (pstapriv->tim_bitmap&0x00fc)) ++ ie_len = 5; ++ else ++ ie_len = 4; ++ ++ *dst_ie++= ie_len; ++ ++ *dst_ie++=0;//DTIM count ++ *dst_ie++=1;//DTIM peroid ++ ++ if(pstapriv->tim_bitmap&BIT(0))//for bc/mc frames ++ *dst_ie++ = BIT(0);//bitmap ctrl ++ else ++ *dst_ie++ = 0; ++ ++ if(ie_len==4) ++ { ++ *dst_ie++ = *(u8*)&tim_bitmap_le; ++ } ++ else if(ie_len==5) ++ { ++ _rtw_memcpy(dst_ie, &tim_bitmap_le, 2); ++ dst_ie+=2; ++ } ++ ++ //copy remainder IE ++ _rtw_memcpy(dst_ie, src_ie+head_len, src_ielen-head_len); ++ ++ //pnetwork_mlmeext->Length += ie_len+2; ++ //pnetwork_mlmeext->IELength += ie_len+2; ++ pnetwork_mlmeext->Length = pnetwork->Length+ie_len+2; ++ pnetwork_mlmeext->IELength = src_ielen+ie_len+2; ++ ++ } ++ else ++ { ++ _rtw_memcpy(dst_ie, src_ie, src_ielen); ++ pnetwork_mlmeext->Length = pnetwork->Length; ++ pnetwork_mlmeext->IELength = src_ielen; ++ } ++ ++#ifdef CONFIG_USB_HCI ++ set_tx_beacon_cmd(padapter); ++#endif ++ ++ ++/* ++ if(send_beacon(padapter)==_FAIL) ++ { ++ DBG_871X("issue_beacon, fail!\n"); ++ } ++*/ ++ ++} ++ ++u8 chk_sta_is_alive(struct sta_info *psta) ++{ ++ u8 ret = _FALSE; ++ #ifdef DBG_EXPIRATION_CHK ++ DBG_871X("sta:"MAC_FMT", rx:"STA_PKTS_FMT", expire_to:%u, %s\n" ++ , MAC_ARG(psta->hwaddr), STA_RX_PKTS_ARG(psta) ++ , psta->expire_to ++ , psta->state&WIFI_SLEEP_STATE?"SLEEP":"" ++ ); ++ #endif ++ ++ //if(sta_last_rx_pkts(psta) == sta_rx_pkts(psta)) ++ if(psta->sta_stats.last_rx_data_pkts == psta->sta_stats.rx_data_pkts) ++ { ++ #if 0 ++ if(psta->state&WIFI_SLEEP_STATE) ++ ret = _TRUE; ++ #endif ++ } ++ else ++ { ++ ret = _TRUE; ++ } ++ ++ sta_update_last_rx_pkts(psta); ++ ++ return ret; ++} ++ ++void expire_timeout_chk(_adapter *padapter) ++{ ++ _irqL irqL; ++ _list *phead, *plist; ++ struct sta_info *psta=NULL; ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ ++ ++ _enter_critical_bh(&pstapriv->auth_list_lock, &irqL); ++ ++ phead = &pstapriv->auth_list; ++ plist = get_next(phead); ++ ++ //check auth_queue ++ while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) ++ { ++ psta = LIST_CONTAINOR(plist, struct sta_info, auth_list); ++ ++ plist = get_next(plist); ++ ++ if(psta->expire_to>0) ++ { ++ psta->expire_to--; ++ if (psta->expire_to == 0) ++ { ++ rtw_list_delete(&psta->auth_list); ++ ++ DBG_871X("auth expire %02X%02X%02X%02X%02X%02X\n", ++ psta->hwaddr[0],psta->hwaddr[1],psta->hwaddr[2],psta->hwaddr[3],psta->hwaddr[4],psta->hwaddr[5]); ++ ++ _exit_critical_bh(&pstapriv->auth_list_lock, &irqL); ++ ++ _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL); ++ rtw_free_stainfo(padapter, psta); ++ _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL); ++ ++ _enter_critical_bh(&pstapriv->auth_list_lock, &irqL); ++ } ++ } ++ ++ } ++ ++ _exit_critical_bh(&pstapriv->auth_list_lock, &irqL); ++ ++ psta = NULL; ++ ++ ++ _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL); ++ ++ phead = &pstapriv->asoc_list; ++ plist = get_next(phead); ++ ++ //check asoc_queue ++ while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) ++ { ++ psta = LIST_CONTAINOR(plist, struct sta_info, asoc_list); ++ ++ plist = get_next(plist); ++ ++ if(chk_sta_is_alive(psta)) ++ { ++ psta->expire_to = pstapriv->expire_to; ++#ifdef CONFIG_TX_MCAST2UNI ++ psta->under_exist_checking = 0; ++#endif // CONFIG_TX_MCAST2UNI ++ } ++ ++ if(psta->expire_to>0) ++ { ++ psta->expire_to--; ++ ++#ifdef CONFIG_TX_MCAST2UNI ++ if ( (psta->flags & WLAN_STA_HT) && (psta->htpriv.agg_enable_bitmap || psta->under_exist_checking) ) { ++ // check sta by delba(addba) for 11n STA ++ // ToDo: use CCX report to check for all STAs ++ DBG_871X("asoc check by DELBA/ADDBA! (pstapriv->expire_to=%d s)(psta->expire_to=%d s), [%02x, %d]\n", pstapriv->expire_to*2, psta->expire_to*2, psta->htpriv.agg_enable_bitmap, psta->under_exist_checking); ++ ++ if ( psta->expire_to <= (pstapriv->expire_to - 50 ) ) { ++ DBG_871X("asoc expire by DELBA/ADDBA! (%d s)\n", (pstapriv->expire_to-psta->expire_to)*2); ++ psta->under_exist_checking = 0; ++ psta->expire_to = 0; ++ } else if ( psta->expire_to <= (pstapriv->expire_to - 3) && (psta->under_exist_checking==0)) { ++ DBG_871X("asoc check by DELBA/ADDBA! (%d s)\n", (pstapriv->expire_to-psta->expire_to)*2); ++ psta->under_exist_checking = 1; ++ //tear down TX AMPDU ++ send_delba(padapter, 1, psta->hwaddr);// // originator ++ psta->htpriv.agg_enable_bitmap = 0x0;//reset ++ psta->htpriv.candidate_tid_bitmap = 0x0;//reset ++ } ++ } ++#endif // CONFIG_TX_MCAST2UNI ++ ++ if (psta->expire_to == 0) ++ { ++ //_irqL irqL; ++ ++ rtw_list_delete(&psta->asoc_list); ++ ++ DBG_871X("asoc expire %02X%02X%02X%02X%02X%02X\n", ++ psta->hwaddr[0],psta->hwaddr[1],psta->hwaddr[2],psta->hwaddr[3],psta->hwaddr[4],psta->hwaddr[5]); ++#if 0 ++ //tear down Rx AMPDU ++ send_delba(padapter, 0, psta->hwaddr);// recipient ++ ++ //tear down TX AMPDU ++ send_delba(padapter, 1, psta->hwaddr);// // originator ++ psta->htpriv.agg_enable_bitmap = 0x0;//reset ++ psta->htpriv.candidate_tid_bitmap = 0x0;//reset ++ ++ issue_deauth(padapter, psta->hwaddr, WLAN_REASON_DEAUTH_LEAVING); ++ ++ _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL); ++ rtw_free_stainfo(padapter, psta); ++ _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL); ++#endif ++ //_exit_critical_bh(&pstapriv->asoc_list_lock, &irqL); ++ ap_free_sta(padapter, psta); ++ //_enter_critical_bh(&pstapriv->asoc_list_lock, &irqL); ++ ++ } ++ else ++ { ++ if(psta->sleepq_len > (NR_XMITFRAME>>3)) ++ { ++ wakeup_sta_to_xmit(padapter, psta); ++ } ++ } ++ ++ } ++ ++ } ++ ++ _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL); ++ ++} ++ ++ ++static void add_RATid(_adapter *padapter, struct sta_info *psta) ++{ ++ int i; ++ u8 rf_type; ++ u32 init_rate=0; ++ unsigned char sta_band = 0, raid, shortGIrate = _FALSE; ++ unsigned char limit; ++ unsigned int tx_ra_bitmap=0; ++ struct ht_priv *psta_ht = NULL; ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ WLAN_BSSID_EX *pcur_network = (WLAN_BSSID_EX *)&pmlmepriv->cur_network.network; ++ ++ ++ if(psta) ++ psta_ht = &psta->htpriv; ++ else ++ return; ++ ++ //b/g mode ra_bitmap ++ for (i=0; ibssrateset); i++) ++ { ++ if (psta->bssrateset[i]) ++ tx_ra_bitmap |= rtw_get_bit_value_from_ieee_value(psta->bssrateset[i]&0x7f); ++ } ++ ++ //n mode ra_bitmap ++ if(psta_ht->ht_option) ++ { ++ padapter->HalFunc.GetHwRegHandler(padapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type)); ++ if(rf_type == RF_2T2R) ++ limit=16;// 2R ++ else ++ limit=8;// 1R ++ ++ for (i=0; iht_cap.supp_mcs_set[i/8] & BIT(i%8)) ++ tx_ra_bitmap |= BIT(i+12); ++ } ++ ++ //max short GI rate ++ shortGIrate = psta_ht->sgi; ++ } ++ ++ ++#if 0//gtest ++ if(get_rf_mimo_mode(padapter) == RTL8712_RF_2T2R) ++ { ++ //is this a 2r STA? ++ if((pstat->tx_ra_bitmap & 0x0ff00000) != 0 && !(priv->pshare->has_2r_sta & BIT(pstat->aid))) ++ { ++ priv->pshare->has_2r_sta |= BIT(pstat->aid); ++ if(rtw_read16(padapter, 0x102501f6) != 0xffff) ++ { ++ rtw_write16(padapter, 0x102501f6, 0xffff); ++ reset_1r_sta_RA(priv, 0xffff); ++ Switch_1SS_Antenna(priv, 3); ++ } ++ } ++ else// bg or 1R STA? ++ { ++ if((priv->pmib->dot11BssType.net_work_type & WIRELESS_11N) && pstat->ht_cap_len && priv->pshare->has_2r_sta == 0) ++ { ++ if(rtw_read16(padapter, 0x102501f6) != 0x7777) ++ { // MCS7 SGI ++ rtw_write16(padapter, 0x102501f6,0x7777); ++ reset_1r_sta_RA(priv, 0x7777); ++ Switch_1SS_Antenna(priv, 2); ++ } ++ } ++ } ++ ++ } ++ ++ if ((pstat->rssi_level < 1) || (pstat->rssi_level > 3)) ++ { ++ if (pstat->rssi >= priv->pshare->rf_ft_var.raGoDownUpper) ++ pstat->rssi_level = 1; ++ else if ((pstat->rssi >= priv->pshare->rf_ft_var.raGoDown20MLower) || ++ ((priv->pshare->is_40m_bw) && (pstat->ht_cap_len) && ++ (pstat->rssi >= priv->pshare->rf_ft_var.raGoDown40MLower) && ++ (pstat->ht_cap_buf.ht_cap_info & cpu_to_le16(_HTCAP_SUPPORT_CH_WDTH_)))) ++ pstat->rssi_level = 2; ++ else ++ pstat->rssi_level = 3; ++ } ++ ++ // rate adaptive by rssi ++ if ((priv->pmib->dot11BssType.net_work_type & WIRELESS_11N) && pstat->ht_cap_len) ++ { ++ if ((get_rf_mimo_mode(priv) == MIMO_1T2R) || (get_rf_mimo_mode(priv) == MIMO_1T1R)) ++ { ++ switch (pstat->rssi_level) { ++ case 1: ++ pstat->tx_ra_bitmap &= 0x100f0000; ++ break; ++ case 2: ++ pstat->tx_ra_bitmap &= 0x100ff000; ++ break; ++ case 3: ++ if (priv->pshare->is_40m_bw) ++ pstat->tx_ra_bitmap &= 0x100ff005; ++ else ++ pstat->tx_ra_bitmap &= 0x100ff001; ++ ++ break; ++ } ++ } ++ else ++ { ++ switch (pstat->rssi_level) { ++ case 1: ++ pstat->tx_ra_bitmap &= 0x1f0f0000; ++ break; ++ case 2: ++ pstat->tx_ra_bitmap &= 0x1f0ff000; ++ break; ++ case 3: ++ if (priv->pshare->is_40m_bw) ++ pstat->tx_ra_bitmap &= 0x000ff005; ++ else ++ pstat->tx_ra_bitmap &= 0x000ff001; ++ ++ break; ++ } ++ ++ // Don't need to mask high rates due to new rate adaptive parameters ++ //if (pstat->is_broadcom_sta) // use MCS12 as the highest rate vs. Broadcom sta ++ // pstat->tx_ra_bitmap &= 0x81ffffff; ++ ++ // NIC driver will report not supporting MCS15 and MCS14 in asoc req ++ //if (pstat->is_rtl8190_sta && !pstat->is_2t_mimo_sta) ++ // pstat->tx_ra_bitmap &= 0x83ffffff; // if Realtek 1x2 sta, don't use MCS15 and MCS14 ++ } ++ } ++ else if ((priv->pmib->dot11BssType.net_work_type & WIRELESS_11G) && isErpSta(pstat)) ++ { ++ switch (pstat->rssi_level) { ++ case 1: ++ pstat->tx_ra_bitmap &= 0x00000f00; ++ break; ++ case 2: ++ pstat->tx_ra_bitmap &= 0x00000ff0; ++ break; ++ case 3: ++ pstat->tx_ra_bitmap &= 0x00000ff5; ++ break; ++ } ++ } ++ else ++ { ++ pstat->tx_ra_bitmap &= 0x0000000d; ++ } ++ ++ // disable tx short GI when station cannot rx MCS15(AP is 2T2R) ++ // disable tx short GI when station cannot rx MCS7 (AP is 1T2R or 1T1R) ++ // if there is only 1r STA and we are 2T2R, DO NOT mask SGI rate ++ if ((!(pstat->tx_ra_bitmap & 0x8000000) && (priv->pshare->has_2r_sta > 0) && (get_rf_mimo_mode(padapter) == RTL8712_RF_2T2R)) || ++ (!(pstat->tx_ra_bitmap & 0x80000) && (get_rf_mimo_mode(padapter) != RTL8712_RF_2T2R))) ++ { ++ pstat->tx_ra_bitmap &= ~BIT(28); ++ } ++#endif ++ ++ if ( pcur_network->Configuration.DSConfig > 14 ) { ++ // 5G band ++ if (tx_ra_bitmap & 0xffff000) ++ sta_band |= WIRELESS_11_5N | WIRELESS_11A; ++ else ++ sta_band |= WIRELESS_11A; ++ } else { ++ if (tx_ra_bitmap & 0xffff000) ++ sta_band |= WIRELESS_11_24N | WIRELESS_11G | WIRELESS_11B; ++ else if (tx_ra_bitmap & 0xff0) ++ sta_band |= WIRELESS_11G |WIRELESS_11B; ++ else ++ sta_band |= WIRELESS_11B; ++ } ++ ++ raid = networktype_to_raid(sta_band); ++ init_rate = get_highest_rate_idx(tx_ra_bitmap&0x0fffffff)&0x3f; ++ ++ if (psta->aid < NUM_STA) ++ { ++ u8 arg = 0; ++#ifdef SUPPORT_64_STA ++ if(psta->mac_id >= FW_CTRL_MACID){ ++ arg = psta->mac_id&0x3f; ++ if (shortGIrate==_TRUE) ++ arg |= BIT(7); ++ switch(raid){ ++ case 0: ++ case 1: ++ case 3: ++ psta->init_rate=19; // N mode ++ break; ++ case 4: ++ case 5: ++ psta->init_rate=11; // G mode ++ break; ++ case 6: ++ psta->init_rate=3; // B mode ++ break; ++ deafult: ++ psta->init_rate=3; // B mode ++ break; ++ ++ } ++ // printk("%s psta->mac_id=%d arg=0x%x\n",__FUNCTION__,psta->mac_id,arg); ++ } ++ else ++#endif // SUPPORT_64_STA ++ { ++ arg = psta->mac_id&0x1f; ++ arg |= BIT(7); ++ if (shortGIrate==_TRUE) ++ arg |= BIT(5); ++ //printk("%s psta->mac_id=%d arg=0x%x\n",__FUNCTION__,psta->mac_id,arg); ++ } ++ tx_ra_bitmap |= ((raid<<28)&0xf0000000); ++ ++ DBG_871X("update raid entry, bitmap=0x%x, arg=0x%x\n", tx_ra_bitmap, arg); ++ ++ //bitmap[0:27] = tx_rate_bitmap ++ //bitmap[28:31]= Rate Adaptive id ++ //arg[0:4] = macid ++ //arg[5] = Short GI ++ padapter->HalFunc.Add_RateATid(padapter, tx_ra_bitmap, arg,psta->mac_id); ++ ++ if (shortGIrate==_TRUE) ++ init_rate |= BIT(6); ++ ++ //set ra_id, init_rate ++ psta->raid = raid; ++ psta->init_rate = init_rate; ++ ++ } ++ else ++ { ++ DBG_871X("station aid %d exceed the max number\n", psta->aid); ++ } ++ ++} ++ ++static void update_bmc_sta(_adapter *padapter) ++{ ++ _irqL irqL; ++ u32 init_rate=0; ++ unsigned char network_type, raid; ++ unsigned short para16; ++ int i, supportRateNum = 0; ++ unsigned int tx_ra_bitmap=0; ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ WLAN_BSSID_EX *pcur_network = (WLAN_BSSID_EX *)&pmlmepriv->cur_network.network; ++ struct sta_info *psta = rtw_get_bcmc_stainfo(padapter); ++ ++ if(psta) ++ { ++ psta->aid = 0;//default set to 0 ++ //psta->mac_id = psta->aid+4; ++ psta->mac_id = psta->aid + 1; ++ ++ psta->qos_option = 0; ++ psta->htpriv.ht_option = _FALSE; ++ ++ psta->ieee8021x_blocked = 0; ++ ++ _rtw_memset((void*)&psta->sta_stats, 0, sizeof(struct stainfo_stats)); ++ ++ //psta->dot118021XPrivacy = _NO_PRIVACY_;//!!! remove it, because it has been set before this. ++ ++ ++ ++ //prepare for add_RATid ++ supportRateNum = rtw_get_rateset_len((u8*)&pcur_network->SupportedRates); ++ network_type = rtw_check_network_type((u8*)&pcur_network->SupportedRates, supportRateNum, 1); ++ ++ _rtw_memcpy(psta->bssrateset, &pcur_network->SupportedRates, supportRateNum); ++ psta->bssratelen = supportRateNum; ++ ++ //b/g mode ra_bitmap ++ for (i=0; ibssrateset[i]) ++ tx_ra_bitmap |= rtw_get_bit_value_from_ieee_value(psta->bssrateset[i]&0x7f); ++ } ++ ++ if ( pcur_network->Configuration.DSConfig > 14 ) { ++ //force to A mode. 5G doesn't support CCK rates ++ network_type = WIRELESS_11A; ++ tx_ra_bitmap = 0x150; // 6, 12, 24 Mbps ++ } else { ++ //force to b mode ++ network_type = WIRELESS_11B; ++ tx_ra_bitmap = 0xf; ++ } ++ ++ //tx_ra_bitmap = update_basic_rate(pcur_network->SupportedRates, supportRateNum); ++ ++ raid = networktype_to_raid(network_type); ++ init_rate = get_highest_rate_idx(tx_ra_bitmap&0x0fffffff)&0x3f; ++ ++ //DBG_871X("Add id %d val %08x to ratr for bmc sta\n", psta->aid, tx_ra_bitmap); ++ ++ //if(pHalData->fw_ractrl == _TRUE) ++ { ++ u8 arg = 0; ++ ++ arg = psta->mac_id&0x1f; ++ ++ arg |= BIT(7); ++ ++ //if (shortGIrate==_TRUE) ++ // arg |= BIT(5); ++ ++ tx_ra_bitmap |= ((raid<<28)&0xf0000000); ++ ++ DBG_871X("update_bmc_sta, mask=0x%x, arg=0x%x\n", tx_ra_bitmap, arg); ++ ++ //bitmap[0:27] = tx_rate_bitmap ++ //bitmap[28:31]= Rate Adaptive id ++ //arg[0:4] = macid ++ //arg[5] = Short GI ++ padapter->HalFunc.Add_RateATid(padapter, tx_ra_bitmap, arg,psta->mac_id ); ++ ++ } ++ ++ //set ra_id, init_rate ++ psta->raid = raid; ++ psta->init_rate = init_rate; ++ ++ _enter_critical_bh(&psta->lock, &irqL); ++ psta->state = _FW_LINKED; ++ _exit_critical_bh(&psta->lock, &irqL); ++ ++ } ++ else ++ { ++ DBG_871X("add_RATid_bmc_sta error!\n"); ++ } ++ ++} ++ ++//notes: ++//AID: 1~MAX for sta and 0 for bc/mc in ap/adhoc mode ++//MAC_ID = AID+1 for sta in ap/adhoc mode ++//MAC_ID = 1 for bc/mc for sta/ap/adhoc ++//MAC_ID = 0 for bssid for sta/ap/adhoc ++//CAM_ID = //0~3 for default key, cmd_id=macid + 3, macid=aid+1; ++ ++void update_sta_info_apmode(_adapter *padapter, struct sta_info *psta) ++{ ++ _irqL irqL; ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ struct security_priv *psecuritypriv = &padapter->securitypriv; ++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); ++ struct ht_priv *phtpriv_ap = &pmlmepriv->htpriv; ++ struct ht_priv *phtpriv_sta = &psta->htpriv; ++ ++ //set intf_tag to if1 ++ //psta->intf_tag = 0; ++ ++ //psta->mac_id = psta->aid+4; ++ psta->mac_id = psta->aid+1; ++ ++ if(psecuritypriv->dot11AuthAlgrthm==dot11AuthAlgrthm_8021X) ++ psta->ieee8021x_blocked = _TRUE; ++ else ++ psta->ieee8021x_blocked = _FALSE; ++ ++ ++ //update sta's cap ++ ++ //ERP ++ VCS_update(padapter, psta); ++ ++ //HT related cap ++ if(phtpriv_sta->ht_option) ++ { ++ //check if sta supports rx ampdu ++ phtpriv_sta->ampdu_enable = phtpriv_ap->ampdu_enable; ++ ++ //check if sta support s Short GI ++ if((phtpriv_sta->ht_cap.cap_info & phtpriv_ap->ht_cap.cap_info) & cpu_to_le16(IEEE80211_HT_CAP_SGI_20|IEEE80211_HT_CAP_SGI_40)) ++ { ++ phtpriv_sta->sgi = _TRUE; ++ } ++ ++ // bwmode ++ if((phtpriv_sta->ht_cap.cap_info & phtpriv_ap->ht_cap.cap_info) & cpu_to_le16(IEEE80211_HT_CAP_SUP_WIDTH)) ++ { ++ //phtpriv_sta->bwmode = HT_CHANNEL_WIDTH_40; ++ phtpriv_sta->bwmode = pmlmeext->cur_bwmode; ++ phtpriv_sta->ch_offset = pmlmeext->cur_ch_offset; ++ ++ } ++ ++ psta->qos_option = _TRUE; ++ ++ } ++ else ++ { ++ phtpriv_sta->ampdu_enable = _FALSE; ++ ++ phtpriv_sta->sgi = _FALSE; ++ phtpriv_sta->bwmode = HT_CHANNEL_WIDTH_20; ++ phtpriv_sta->ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; ++ } ++ ++ //Rx AMPDU ++ send_delba(padapter, 0, psta->hwaddr);// recipient ++ ++ //TX AMPDU ++ send_delba(padapter, 1, psta->hwaddr);// // originator ++ phtpriv_sta->agg_enable_bitmap = 0x0;//reset ++ phtpriv_sta->candidate_tid_bitmap = 0x0;//reset ++ ++ ++ //todo: init other variables ++ ++ _rtw_memset((void*)&psta->sta_stats, 0, sizeof(struct stainfo_stats)); ++ ++ ++ //add ratid ++ //add_RATid(padapter, psta);//move to ap_sta_info_defer_update() ++ ++ ++ _enter_critical_bh(&psta->lock, &irqL); ++ psta->state |= _FW_LINKED; ++ _exit_critical_bh(&psta->lock, &irqL); ++ ++ ++} ++ ++static void update_hw_ht_param(_adapter *padapter) ++{ ++ unsigned char max_AMPDU_len; ++ unsigned char min_MPDU_spacing; ++ struct registry_priv *pregpriv = &padapter->registrypriv; ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ ++ DBG_871X("%s\n", __FUNCTION__); ++ ++ ++ //handle A-MPDU parameter field ++ /* ++ AMPDU_para [1:0]:Max AMPDU Len => 0:8k , 1:16k, 2:32k, 3:64k ++ AMPDU_para [4:2]:Min MPDU Start Spacing ++ */ ++ max_AMPDU_len = pmlmeinfo->HT_caps.HT_cap_element.AMPDU_para & 0x03; ++ ++ min_MPDU_spacing = (pmlmeinfo->HT_caps.HT_cap_element.AMPDU_para & 0x1c) >> 2; ++ ++ padapter->HalFunc.SetHwRegHandler(padapter, HW_VAR_AMPDU_MIN_SPACE, (u8 *)(&min_MPDU_spacing)); ++ ++ padapter->HalFunc.SetHwRegHandler(padapter, HW_VAR_AMPDU_FACTOR, (u8 *)(&max_AMPDU_len)); ++ ++ // ++ // Config SM Power Save setting ++ // ++ pmlmeinfo->SM_PS = (pmlmeinfo->HT_caps.HT_cap_element.HT_caps_info & 0x0C) >> 2; ++ if(pmlmeinfo->SM_PS == WLAN_HT_CAP_SM_PS_STATIC) ++ { ++ /*u8 i; ++ //update the MCS rates ++ for (i = 0; i < 16; i++) ++ { ++ pmlmeinfo->HT_caps.HT_cap_element.MCS_rate[i] &= MCS_rate_1R[i]; ++ }*/ ++ DBG_8192C("%s(): WLAN_HT_CAP_SM_PS_STATIC\n",__FUNCTION__); ++ } ++ ++ // ++ // Config current HT Protection mode. ++ // ++ //pmlmeinfo->HT_protection = pmlmeinfo->HT_info.infos[1] & 0x3; ++ ++} ++ ++static void start_bss_network(_adapter *padapter, u8 *pbuf) ++{ ++ u8 *p; ++ u8 val8, cur_channel, cur_bwmode, cur_ch_offset; ++ u16 bcn_interval; ++ u32 acparm; ++ int ie_len; ++ struct registry_priv *pregpriv = &padapter->registrypriv; ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ struct security_priv* psecuritypriv=&(padapter->securitypriv); ++ WLAN_BSSID_EX *pnetwork = (WLAN_BSSID_EX *)&pmlmepriv->cur_network.network; ++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ WLAN_BSSID_EX *pnetwork_mlmeext = &(pmlmeinfo->network); ++#ifdef CONFIG_P2P ++ struct wifidirect_info *pwdinfo = &(padapter->wdinfo); ++#endif //CONFIG_P2P ++ ++ ++ //DBG_8192C("%s\n", __FUNCTION__); ++ ++ bcn_interval = (u16)pnetwork->Configuration.BeaconPeriod; ++ cur_channel = pnetwork->Configuration.DSConfig; ++ cur_bwmode = HT_CHANNEL_WIDTH_20;; ++ cur_ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; ++ ++ ++ //check if there is wps ie, ++ //if there is wpsie in beacon, the hostapd will update beacon twice when stating hostapd, ++ //and at first time the security ie ( RSN/WPA IE) will not include in beacon. ++ if(NULL == rtw_get_wps_ie(pnetwork->IEs+_FIXED_IE_LENGTH_, pnetwork->IELength-_FIXED_IE_LENGTH_, NULL, NULL)) ++ { ++ pmlmeext->bstart_bss = _TRUE; ++ } ++ ++ //udpate capability ++ update_capinfo(padapter, rtw_get_capability((WLAN_BSSID_EX *)pnetwork)); ++ ++ //todo: update wmm, ht cap ++ //pmlmeinfo->WMM_enable; ++ //pmlmeinfo->HT_enable; ++ if(pmlmepriv->qospriv.qos_option) ++ pmlmeinfo->WMM_enable = _TRUE; ++ ++ if(pmlmepriv->htpriv.ht_option) ++ { ++ pmlmeinfo->WMM_enable = _TRUE; ++ pmlmeinfo->HT_enable = _TRUE; ++ //pmlmeinfo->HT_info_enable = _TRUE; ++ //pmlmeinfo->HT_caps_enable = _TRUE; ++ ++ update_hw_ht_param(padapter); ++ } ++ ++ ++ if(pmlmepriv->cur_network.join_res != _TRUE) //setting only at first time ++ { ++ flush_all_cam_entry(padapter); //clear CAM ++ } ++ ++ //set MSR to AP_Mode ++ Set_NETYPE0_MSR(padapter, _HW_STATE_AP_); ++ ++ //Set BSSID REG ++ padapter->HalFunc.SetHwRegHandler(padapter, HW_VAR_BSSID, pnetwork->MacAddress); ++ ++ //Set EDCA param reg ++ acparm = 0x002F3217; // VO ++ padapter->HalFunc.SetHwRegHandler(padapter, HW_VAR_AC_PARAM_VO, (u8 *)(&acparm)); ++ acparm = 0x005E4317; // VI ++ padapter->HalFunc.SetHwRegHandler(padapter, HW_VAR_AC_PARAM_VI, (u8 *)(&acparm)); ++ //acparm = 0x00105320; // BE ++ acparm = 0x005ea42b; ++ padapter->HalFunc.SetHwRegHandler(padapter, HW_VAR_AC_PARAM_BE, (u8 *)(&acparm)); ++ acparm = 0x0000A444; // BK ++ padapter->HalFunc.SetHwRegHandler(padapter, HW_VAR_AC_PARAM_BK, (u8 *)(&acparm)); ++ ++ //Set Security ++ val8 = (psecuritypriv->dot11AuthAlgrthm == dot11AuthAlgrthm_8021X)? 0xcc: 0xcf; ++ padapter->HalFunc.SetHwRegHandler(padapter, HW_VAR_SEC_CFG, (u8 *)(&val8)); ++ ++ //Beacon Control related register ++ padapter->HalFunc.SetHwRegHandler(padapter, HW_VAR_BEACON_INTERVAL, (u8 *)(&bcn_interval)); ++ ++ ++ UpdateBrateTbl(padapter, pnetwork->SupportedRates); ++ padapter->HalFunc.SetHwRegHandler(padapter, HW_VAR_BASIC_RATE, pnetwork->SupportedRates); ++ ++ if(pmlmepriv->cur_network.join_res != _TRUE) //setting only at first time ++ { ++ u32 initialgain; ++ ++ //disable dynamic functions, such as high power, DIG ++ //Save_DM_Func_Flag(padapter); ++ //Switch_DM_Func(padapter, DYNAMIC_FUNC_DISABLE, _FALSE); ++ ++ //turn on dynamic functions ++ Switch_DM_Func(padapter, DYNAMIC_FUNC_DIG|DYNAMIC_FUNC_HP|DYNAMIC_FUNC_SS, _TRUE); ++ ++ initialgain = 0x30; ++ padapter->HalFunc.SetHwRegHandler(padapter, HW_VAR_INITIAL_GAIN, (u8 *)(&initialgain)); ++ ++ } ++ ++ //set channel, bwmode ++ p = rtw_get_ie((pnetwork->IEs + sizeof(NDIS_802_11_FIXED_IEs)), _HT_ADD_INFO_IE_, &ie_len, (pnetwork->IELength - sizeof(NDIS_802_11_FIXED_IEs))); ++ if( p && ie_len) ++ { ++ struct HT_info_element *pht_info = (struct HT_info_element *)(p+2); ++ ++ if ((pregpriv->cbw40_enable) && (pht_info->infos[0] & BIT(2))) ++ { ++ //switch to the 40M Hz mode ++ //pmlmeext->cur_bwmode = HT_CHANNEL_WIDTH_40; ++ cur_bwmode = HT_CHANNEL_WIDTH_40; ++ switch (pht_info->infos[0] & 0x3) ++ { ++ case 1: ++ //pmlmeext->cur_ch_offset = HAL_PRIME_CHNL_OFFSET_LOWER; ++ cur_ch_offset = HAL_PRIME_CHNL_OFFSET_LOWER; ++ break; ++ ++ case 3: ++ //pmlmeext->cur_ch_offset = HAL_PRIME_CHNL_OFFSET_UPPER; ++ cur_ch_offset = HAL_PRIME_CHNL_OFFSET_UPPER; ++ break; ++ ++ default: ++ //pmlmeext->cur_ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; ++ cur_ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; ++ break; ++ } ++ ++ } ++ ++ } ++ ++ //TODO: need to judge the phy parameters on concurrent mode for single phy ++ //set_channel_bwmode(padapter, pmlmeext->cur_channel, pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode); ++ set_channel_bwmode(padapter, cur_channel, cur_ch_offset, cur_bwmode); ++ ++ DBG_871X("CH=%d, BW=%d, offset=%d\n", cur_channel, cur_bwmode, cur_ch_offset); ++ ++ // ++ pmlmeext->cur_channel = cur_channel; ++ pmlmeext->cur_bwmode = cur_bwmode; ++ pmlmeext->cur_ch_offset = cur_ch_offset; ++ pmlmeext->cur_wireless_mode = pmlmepriv->cur_network.network_type; ++ ++ //update cur_wireless_mode ++ update_wireless_mode(padapter); ++ ++ //let pnetwork_mlmeext == pnetwork_mlme. ++ _rtw_memcpy(pnetwork_mlmeext, pnetwork, pnetwork->Length); ++ ++#ifdef CONFIG_P2P ++ _rtw_memcpy(pwdinfo->p2p_group_ssid, pnetwork->Ssid.Ssid, pnetwork->Ssid.SsidLength); ++ pwdinfo->p2p_group_ssid_len = pnetwork->Ssid.SsidLength; ++#endif //CONFIG_P2P ++ ++ ++ if(_TRUE == pmlmeext->bstart_bss) ++ { ++ update_beacon(padapter, _TIM_IE_, NULL, _FALSE); ++ ++ //issue beacon frame ++ if(send_beacon(padapter)==_FAIL) ++ { ++ DBG_871X("issue_beacon, fail!\n"); ++ } ++ } ++ ++ ++ //update bc/mc sta_info ++ update_bmc_sta(padapter); ++ ++ //pmlmeext->bstart_bss = _TRUE; ++ ++} ++ ++int rtw_check_beacon_data(_adapter *padapter, u8 *pbuf, int len) ++{ ++ int ret=_SUCCESS; ++ u8 *p; ++ u8 *pHT_caps_ie=NULL; ++ u8 *pHT_info_ie=NULL; ++ struct sta_info *psta = NULL; ++ u16 cap, ht_cap=_FALSE; ++ uint ie_len = 0; ++ int group_cipher, pairwise_cipher; ++ u8 channel, network_type, supportRate[NDIS_802_11_LENGTH_RATES_EX]; ++ int supportRateNum = 0; ++ u8 OUI1[] = {0x00, 0x50, 0xf2,0x01}; ++ u8 wps_oui[4]={0x0,0x50,0xf2,0x04}; ++ u8 WMM_PARA_IE[] = {0x00, 0x50, 0xf2, 0x02, 0x01, 0x01}; ++ struct registry_priv *pregistrypriv = &padapter->registrypriv; ++ struct security_priv *psecuritypriv = &padapter->securitypriv; ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ WLAN_BSSID_EX *pbss_network = (WLAN_BSSID_EX *)&pmlmepriv->cur_network.network; ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ u8 *ie = pbss_network->IEs; ++ ++ ++ /* SSID */ ++ /* Supported rates */ ++ /* DS Params */ ++ /* WLAN_EID_COUNTRY */ ++ /* ERP Information element */ ++ /* Extended supported rates */ ++ /* WPA/WPA2 */ ++ /* Wi-Fi Wireless Multimedia Extensions */ ++ /* ht_capab, ht_oper */ ++ /* WPS IE */ ++ ++ DBG_8192C("%s, len=%d\n", __FUNCTION__, len); ++ ++ if(check_fwstate(pmlmepriv, WIFI_AP_STATE) != _TRUE) ++ return _FAIL; ++ ++ ++ if(len>MAX_IE_SZ) ++ return _FAIL; ++ ++ pbss_network->IELength = len; ++ ++ _rtw_memset(ie, 0, MAX_IE_SZ); ++ ++ _rtw_memcpy(ie, pbuf, pbss_network->IELength); ++ ++ ++ if(pbss_network->InfrastructureMode!=Ndis802_11APMode) ++ return _FAIL; ++ ++ pbss_network->Rssi = 0; ++ ++ _rtw_memcpy(pbss_network->MacAddress, myid(&(padapter->eeprompriv)), ETH_ALEN); ++ ++ //beacon interval ++ p = rtw_get_beacon_interval_from_ie(ie);//ie + 8; // 8: TimeStamp, 2: Beacon Interval 2:Capability ++ //pbss_network->Configuration.BeaconPeriod = le16_to_cpu(*(unsigned short*)p); ++ pbss_network->Configuration.BeaconPeriod = RTW_GET_LE16(p); ++ ++ //capability ++ //cap = *(unsigned short *)rtw_get_capability_from_ie(ie); ++ //cap = le16_to_cpu(cap); ++ cap = RTW_GET_LE16(ie); ++ ++ //SSID ++ p = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _SSID_IE_, &ie_len, (pbss_network->IELength -_BEACON_IE_OFFSET_)); ++ if(p && ie_len>0) ++ { ++ _rtw_memset(&pbss_network->Ssid, 0, sizeof(NDIS_802_11_SSID)); ++ _rtw_memcpy(pbss_network->Ssid.Ssid, (p + 2), ie_len); ++ pbss_network->Ssid.SsidLength = ie_len; ++ } ++ ++ //chnnel ++ channel = 0; ++ pbss_network->Configuration.Length = 0; ++ p = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _DSSET_IE_, &ie_len, (pbss_network->IELength - _BEACON_IE_OFFSET_)); ++ if(p && ie_len>0) ++ channel = *(p + 2); ++ ++ pbss_network->Configuration.DSConfig = channel; ++ ++ ++ _rtw_memset(supportRate, 0, NDIS_802_11_LENGTH_RATES_EX); ++ // get supported rates ++ p = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _SUPPORTEDRATES_IE_, &ie_len, (pbss_network->IELength - _BEACON_IE_OFFSET_)); ++ if (p != NULL) ++ { ++ _rtw_memcpy(supportRate, p+2, ie_len); ++ supportRateNum = ie_len; ++ } ++ ++ //get ext_supported rates ++ p = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _EXT_SUPPORTEDRATES_IE_, &ie_len, pbss_network->IELength - _BEACON_IE_OFFSET_); ++ if (p != NULL) ++ { ++ _rtw_memcpy(supportRate+supportRateNum, p+2, ie_len); ++ supportRateNum += ie_len; ++ ++ } ++ ++ network_type = rtw_check_network_type(supportRate, supportRateNum, channel); ++ ++ rtw_set_supported_rate(pbss_network->SupportedRates, network_type); ++ ++ ++ //parsing ERP_IE ++ p = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _ERPINFO_IE_, &ie_len, (pbss_network->IELength - _BEACON_IE_OFFSET_)); ++ if(p && ie_len>0) ++ { ++ ERP_IE_handler(padapter, (PNDIS_802_11_VARIABLE_IEs)p); ++ } ++#ifdef SUPPORT_64_STA ++ //capability ++ p=rtw_get_capability_from_ie(ie); ++ //cap = le16_to_cpu(cap); ++ cap = RTW_GET_LE16(p); ++ //printk("%s cap=0x%x\n",__FUNCTION__,cap); ++ cap &=~BIT(4); ++ //printk("%s cap=0x%x\n",__FUNCTION__,cap); ++ RTW_PUT_LE16(p,cap); ++ cap = RTW_GET_LE16(p); ++ //printk("%s [fin] cap=0x%x\n",__FUNCTION__,cap); ++ pbss_network->Privacy = 0; ++ psecuritypriv->wpa_psk = 0; ++ ++ { ++ u32 i,j; ++ printk(" %s :Dump IEs\n",__FUNCTION__); ++ for(i=0,j=1;iIELength;i++){ ++ printk("0x%.2x:",ie[i]); ++ if( ((j++)%16)==0 ) ++ printk("\n"); ++ } ++ printk("\n"); ++ } ++ p = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _RSN_IE_2_, &ie_len, (pbss_network->IELength - _BEACON_IE_OFFSET_)); ++ if(p && ie_len>0){ ++ //remove wpa2 ie ++ u32 offset=0,remain=0; ++ offset=p-ie; ++ remain= pbss_network->IELength-offset-ie_len-2; ++ DBG_8192C("%s wpa2 ie_len=%d offset=%d remain=%d IELength=%d\n",__FUNCTION__,ie_len,offset,remain,pbss_network->IELength); ++ { ++ u32 i,j; ++ printk(" %s :Dump IEs\n",__FUNCTION__); ++ for(i=0,j=1;iIELength;i++){ ++ printk("0x%.2x:",ie[i]); ++ if((((j++)%16)==0) ) ++ printk("\n"); ++ } ++ DBG_8192C("\n"); ++ } ++ _rtw_memcpy(p,p+ie_len+2,remain); ++ pbss_network->IELength-=(ie_len+2); ++ DBG_8192C("%s wpa2 [fin]ie_len=%d remain=%d IELength=%d\n",__FUNCTION__,ie_len,remain,pbss_network->IELength); ++ { ++ u32 i,j; ++ printk(" %s :Dump IEs\n",__FUNCTION__); ++ for(i=0,j=1;iIELength;i++){ ++ printk("0x%.2x:",ie[i]); ++ if((j++%16)==0 ) ++ printk("\n"); ++ } ++ DBG_8192C("\n"); ++ } ++ } ++ ++ psecuritypriv->dot8021xalg = 0; ++ psecuritypriv->wpa2_group_cipher = _NO_PRIVACY_; ++ psecuritypriv->wpa2_pairwise_cipher = _NO_PRIVACY_; ++ { ++ //remove wpa ie ++ u32 rem=pbss_network->IELength-_BEACON_IE_OFFSET_; ++ p = ie + _BEACON_IE_OFFSET_; ++ ++ DBG_8192C("%s [p]%p id[0x%x] ie[%p] len[%d][_BEACON_IE_OFFSET_]%d [remain]%d \n",__FUNCTION__,p,p[0],ie,p[1],_BEACON_IE_OFFSET_,rem); ++ DBG_8192C("%s id=0x%x len=%d rem=%d next p %p\n",__FUNCTION__,*p,p[1],rem,(p + (p[1]+2))); ++ for (p = ie + _BEACON_IE_OFFSET_;rem>0 ;) ++ { ++ DBG_8192C("%s id=0x%x len=%d rem=%d next p %p\n",__FUNCTION__,*p,p[1],rem,p + (p[1]+2)); ++ if ((p) && (_rtw_memcmp(p+2, OUI1, 4))) ++ { ++ //remove wpa ie ++ u32 remain=0; ++ u8 *ptr; ++ remain= rem-p[1]-2; ++ ptr=p+p[1]+2; ++ DBG_8192C("%s wpa ie_len=%d remain=%d IELength=%d p %p next p %p,%p id 0x%x\n",__FUNCTION__,p[1],remain,pbss_network->IELength,p,p+p[1]+2,ptr,p[p[1]+2]); ++ pbss_network->IELength-=(p[1]+2); ++ _rtw_memcpy(p,ptr,remain); ++ DBG_8192C("%s wpa [fin]ie_len=%d remain=%d IELength=%d\n",__FUNCTION__,p[1],remain,pbss_network->IELength); ++ { ++ u32 i,j; ++ DBG_8192C(" %s :Dump IEs\n",__FUNCTION__); ++ for(i=0,j=1;iIELength;i++){ ++ printk("0x%.2x:",ie[i]); ++ if((j++%16)==0) ++ DBG_8192C("\n"); ++ } ++ DBG_8192C("\n"); ++ } ++ DBG_8192C("%s wpa [fin] ie_len=%d remain=%d IELength=%d\n",__FUNCTION__,ie_len,remain,pbss_network->IELength); ++ rem=remain; ++ }else{ ++ rem -= (p[1]+2); ++ p+=(p[1]+2); ++ } ++ } ++ } ++#else //SUPPORT_64_STA ++ ++ //update privacy/security ++ if (cap & BIT(4)) ++ pbss_network->Privacy = 1; ++ else ++ pbss_network->Privacy = 0; ++ ++ psecuritypriv->wpa_psk = 0; ++ ++ //wpa2 ++ group_cipher = 0; pairwise_cipher = 0; ++ psecuritypriv->wpa2_group_cipher = _NO_PRIVACY_; ++ psecuritypriv->wpa2_pairwise_cipher = _NO_PRIVACY_; ++ p = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _RSN_IE_2_, &ie_len, (pbss_network->IELength - _BEACON_IE_OFFSET_)); ++ if(p && ie_len>0) ++ { ++ if(rtw_parse_wpa2_ie(p, ie_len+2, &group_cipher, &pairwise_cipher) == _SUCCESS) ++ { ++ psecuritypriv->dot11AuthAlgrthm= dot11AuthAlgrthm_8021X; ++ ++ psecuritypriv->dot8021xalg = 1;//psk, todo:802.1x ++ psecuritypriv->wpa_psk |= BIT(1); ++ ++ psecuritypriv->wpa2_group_cipher = group_cipher; ++ psecuritypriv->wpa2_pairwise_cipher = pairwise_cipher; ++#if 0 ++ switch(group_cipher) ++ { ++ case WPA_CIPHER_NONE: ++ psecuritypriv->wpa2_group_cipher = _NO_PRIVACY_; ++ break; ++ case WPA_CIPHER_WEP40: ++ psecuritypriv->wpa2_group_cipher = _WEP40_; ++ break; ++ case WPA_CIPHER_TKIP: ++ psecuritypriv->wpa2_group_cipher = _TKIP_; ++ break; ++ case WPA_CIPHER_CCMP: ++ psecuritypriv->wpa2_group_cipher = _AES_; ++ break; ++ case WPA_CIPHER_WEP104: ++ psecuritypriv->wpa2_group_cipher = _WEP104_; ++ break; ++ } ++ ++ switch(pairwise_cipher) ++ { ++ case WPA_CIPHER_NONE: ++ psecuritypriv->wpa2_pairwise_cipher = _NO_PRIVACY_; ++ break; ++ case WPA_CIPHER_WEP40: ++ psecuritypriv->wpa2_pairwise_cipher = _WEP40_; ++ break; ++ case WPA_CIPHER_TKIP: ++ psecuritypriv->wpa2_pairwise_cipher = _TKIP_; ++ break; ++ case WPA_CIPHER_CCMP: ++ psecuritypriv->wpa2_pairwise_cipher = _AES_; ++ break; ++ case WPA_CIPHER_WEP104: ++ psecuritypriv->wpa2_pairwise_cipher = _WEP104_; ++ break; ++ } ++#endif ++ } ++ ++ } ++ ++ //wpa ++ ie_len = 0; ++ group_cipher = 0; pairwise_cipher = 0; ++ psecuritypriv->wpa_group_cipher = _NO_PRIVACY_; ++ psecuritypriv->wpa_pairwise_cipher = _NO_PRIVACY_; ++ for (p = ie + _BEACON_IE_OFFSET_; ;p += (ie_len + 2)) ++ { ++ p = rtw_get_ie(p, _SSN_IE_1_, &ie_len, (pbss_network->IELength - _BEACON_IE_OFFSET_ - (ie_len + 2))); ++ if ((p) && (_rtw_memcmp(p+2, OUI1, 4))) ++ { ++ if(rtw_parse_wpa_ie(p, ie_len+2, &group_cipher, &pairwise_cipher) == _SUCCESS) ++ { ++ psecuritypriv->dot11AuthAlgrthm= dot11AuthAlgrthm_8021X; ++ ++ psecuritypriv->dot8021xalg = 1;//psk, todo:802.1x ++ ++ psecuritypriv->wpa_psk |= BIT(0); ++ ++ psecuritypriv->wpa_group_cipher = group_cipher; ++ psecuritypriv->wpa_pairwise_cipher = pairwise_cipher; ++ ++#if 0 ++ switch(group_cipher) ++ { ++ case WPA_CIPHER_NONE: ++ psecuritypriv->wpa_group_cipher = _NO_PRIVACY_; ++ break; ++ case WPA_CIPHER_WEP40: ++ psecuritypriv->wpa_group_cipher = _WEP40_; ++ break; ++ case WPA_CIPHER_TKIP: ++ psecuritypriv->wpa_group_cipher = _TKIP_; ++ break; ++ case WPA_CIPHER_CCMP: ++ psecuritypriv->wpa_group_cipher = _AES_; ++ break; ++ case WPA_CIPHER_WEP104: ++ psecuritypriv->wpa_group_cipher = _WEP104_; ++ break; ++ } ++ ++ switch(pairwise_cipher) ++ { ++ case WPA_CIPHER_NONE: ++ psecuritypriv->wpa_pairwise_cipher = _NO_PRIVACY_; ++ break; ++ case WPA_CIPHER_WEP40: ++ psecuritypriv->wpa_pairwise_cipher = _WEP40_; ++ break; ++ case WPA_CIPHER_TKIP: ++ psecuritypriv->wpa_pairwise_cipher = _TKIP_; ++ break; ++ case WPA_CIPHER_CCMP: ++ psecuritypriv->wpa_pairwise_cipher = _AES_; ++ break; ++ case WPA_CIPHER_WEP104: ++ psecuritypriv->wpa_pairwise_cipher = _WEP104_; ++ break; ++ } ++#endif ++ } ++ ++ break; ++ ++ } ++ ++ if ((p == NULL) || (ie_len == 0)) ++ { ++ break; ++ } ++ ++ } ++ ++#endif //SUPPORT_64_STA ++ ++ //wmm ++ ie_len = 0; ++ pmlmepriv->qospriv.qos_option = 0; ++ if(pregistrypriv->wmm_enable) ++ { ++ for (p = ie + _BEACON_IE_OFFSET_; ;p += (ie_len + 2)) ++ { ++ p = rtw_get_ie(p, _VENDOR_SPECIFIC_IE_, &ie_len, (pbss_network->IELength - _BEACON_IE_OFFSET_ - (ie_len + 2))); ++ if((p) && _rtw_memcmp(p+2, WMM_PARA_IE, 6)) ++ { ++ pmlmepriv->qospriv.qos_option = 1; ++ ++ *(p+8) |= BIT(7);//QoS Info, support U-APSD ++ ++ break; ++ } ++ ++ if ((p == NULL) || (ie_len == 0)) ++ { ++ break; ++ } ++ } ++ } ++ ++ //parsing HT_CAP_IE ++ p = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _HT_CAPABILITY_IE_, &ie_len, (pbss_network->IELength - _BEACON_IE_OFFSET_)); ++ if(p && ie_len>0) ++ { ++ u8 rf_type; ++ ++ struct rtw_ieee80211_ht_cap *pht_cap = (struct rtw_ieee80211_ht_cap *)(p+2); ++ ++ pHT_caps_ie=p; ++ ++ ++ ht_cap = _TRUE; ++ network_type |= WIRELESS_11_24N; ++ ++ ++ padapter->HalFunc.GetHwRegHandler(padapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type)); ++ ++ if((psecuritypriv->wpa_pairwise_cipher & WPA_CIPHER_CCMP) || ++ (psecuritypriv->wpa2_pairwise_cipher & WPA_CIPHER_CCMP)) ++ { ++ pht_cap->ampdu_params_info |= (IEEE80211_HT_CAP_AMPDU_DENSITY&(0x07<<2)); ++ } ++ else ++ { ++ pht_cap->ampdu_params_info |= (IEEE80211_HT_CAP_AMPDU_DENSITY&0x00); ++ } ++ ++ ++ if(rf_type == RF_1T1R) ++ { ++ pht_cap->supp_mcs_set[0] = 0xff; ++ pht_cap->supp_mcs_set[1] = 0x0; ++ } ++ ++ _rtw_memcpy(&pmlmepriv->htpriv.ht_cap, p+2, ie_len); ++ ++ } ++ ++ //parsing HT_INFO_IE ++ p = rtw_get_ie(ie + _BEACON_IE_OFFSET_, _HT_ADD_INFO_IE_, &ie_len, (pbss_network->IELength - _BEACON_IE_OFFSET_)); ++ if(p && ie_len>0) ++ { ++ pHT_info_ie=p; ++ } ++ ++ switch(network_type) ++ { ++ case WIRELESS_11B: ++ pbss_network->NetworkTypeInUse = Ndis802_11DS; ++ break; ++ case WIRELESS_11G: ++ case WIRELESS_11BG: ++ case WIRELESS_11G_24N: ++ case WIRELESS_11BG_24N: ++ pbss_network->NetworkTypeInUse = Ndis802_11OFDM24; ++ break; ++ case WIRELESS_11A: ++ pbss_network->NetworkTypeInUse = Ndis802_11OFDM5; ++ break; ++ default : ++ pbss_network->NetworkTypeInUse = Ndis802_11OFDM24; ++ break; ++ } ++ ++ pmlmepriv->cur_network.network_type = network_type; ++ ++ ++ pmlmepriv->htpriv.ht_option = _FALSE; ++#ifdef CONFIG_80211N_HT ++ if( (psecuritypriv->wpa2_pairwise_cipher&WPA_CIPHER_TKIP) || ++ (psecuritypriv->wpa_pairwise_cipher&WPA_CIPHER_TKIP)) ++ { ++ //todo: ++ //ht_cap = _FALSE; ++ } ++ ++ //ht_cap ++ if(pregistrypriv->ht_enable && ht_cap==_TRUE) ++ { ++ pmlmepriv->htpriv.ht_option = _TRUE; ++ pmlmepriv->qospriv.qos_option = 1; ++ ++ if(pregistrypriv->ampdu_enable==1) ++ { ++ pmlmepriv->htpriv.ampdu_enable = _TRUE; ++ } ++ ++ HT_caps_handler(padapter, (PNDIS_802_11_VARIABLE_IEs)pHT_caps_ie); ++ ++ HT_info_handler(padapter, (PNDIS_802_11_VARIABLE_IEs)pHT_info_ie); ++ } ++#endif ++ ++ ++ pbss_network->Length = get_WLAN_BSSID_EX_sz((WLAN_BSSID_EX *)pbss_network); ++ ++ //issue beacon to start bss network ++ start_bss_network(padapter, (u8*)pbss_network); ++ ++ ++ //alloc sta_info for ap itself ++ psta = rtw_get_stainfo(&padapter->stapriv, pbss_network->MacAddress); ++ if(!psta) ++ { ++ psta = rtw_alloc_stainfo(&padapter->stapriv, pbss_network->MacAddress); ++ if (psta == NULL) ++ { ++ return _FAIL; ++ } ++ } ++ ++ rtw_indicate_connect( padapter); ++ ++ pmlmepriv->cur_network.join_res = _TRUE;//for check if already set beacon ++ ++ //update bc/mc sta_info ++ //update_bmc_sta(padapter); ++ ++ return ret; ++ ++} ++ ++#ifdef CONFIG_NATIVEAP_MLME ++ ++static void update_bcn_fixed_ie(_adapter *padapter) ++{ ++ DBG_871X("%s\n", __FUNCTION__); ++ ++} ++ ++static void update_bcn_erpinfo_ie(_adapter *padapter) ++{ ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ ++ DBG_871X("%s\n", __FUNCTION__); ++ ++ if(!pmlmeinfo->ERP_enable) ++ return; ++ ++ ++} ++ ++static void update_bcn_htcap_ie(_adapter *padapter) ++{ ++ DBG_871X("%s\n", __FUNCTION__); ++ ++} ++ ++static void update_bcn_htinfo_ie(_adapter *padapter) ++{ ++ DBG_871X("%s\n", __FUNCTION__); ++ ++} ++ ++static void update_bcn_rsn_ie(_adapter *padapter) ++{ ++ DBG_871X("%s\n", __FUNCTION__); ++ ++} ++ ++static void update_bcn_wpa_ie(_adapter *padapter) ++{ ++ DBG_871X("%s\n", __FUNCTION__); ++ ++} ++ ++static void update_bcn_wmm_ie(_adapter *padapter) ++{ ++ DBG_871X("%s\n", __FUNCTION__); ++ ++} ++ ++static void update_bcn_wps_ie(_adapter *padapter) ++{ ++ int match; ++ u8 *pwps_ie=NULL, *pwps_ie_src, *premainder_ie, *pbackup_remainder_ie=NULL; ++ uint wps_ielen=0, wps_offset, remainder_ielen; ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ WLAN_BSSID_EX *pnetwork = &(pmlmeinfo->network); ++ unsigned char *ie = pnetwork->IEs; ++ u32 ielen = pnetwork->IELength; ++ ++ ++ DBG_871X("%s\n", __FUNCTION__); ++ ++ pwps_ie = rtw_get_wps_ie(ie+_FIXED_IE_LENGTH_, ielen-_FIXED_IE_LENGTH_, NULL, &wps_ielen); ++ ++ if(pwps_ie==NULL || wps_ielen==0) ++ return; ++ ++ wps_offset = (uint)(pwps_ie-ie); ++ ++ premainder_ie = pwps_ie + wps_ielen; ++ ++ remainder_ielen = ielen - wps_offset - wps_ielen; ++ ++ if(remainder_ielen>0) ++ { ++ pbackup_remainder_ie = rtw_malloc(remainder_ielen); ++ if(pbackup_remainder_ie) ++ _rtw_memcpy(pbackup_remainder_ie, premainder_ie, remainder_ielen); ++ } ++ ++ ++ pwps_ie_src = pmlmepriv->wps_beacon_ie; ++ if(pwps_ie_src == NULL) ++ return; ++ ++ ++ wps_ielen = (uint)pwps_ie_src[1];//to get ie data len ++ if((wps_offset+wps_ielen+2+remainder_ielen)<=MAX_IE_SZ) ++ { ++ _rtw_memcpy(pwps_ie, pwps_ie_src, wps_ielen+2); ++ pwps_ie += (wps_ielen+2); ++ ++ if(pbackup_remainder_ie) ++ _rtw_memcpy(pwps_ie, pbackup_remainder_ie, remainder_ielen); ++ ++ //update IELength ++ pnetwork->IELength = wps_offset + (wps_ielen+2) + remainder_ielen; ++ } ++ ++ if(pbackup_remainder_ie) ++ rtw_mfree(pbackup_remainder_ie, remainder_ielen); ++ ++} ++ ++static void update_bcn_p2p_ie(_adapter *padapter) ++{ ++ ++} ++ ++static void update_bcn_vendor_spec_ie(_adapter *padapter, u8*oui) ++{ ++ DBG_871X("%s\n", __FUNCTION__); ++ ++ if(_rtw_memcmp(WPA_OUI, oui, 4)) ++ { ++ update_bcn_wpa_ie(padapter); ++ } ++ else if(_rtw_memcmp(WMM_OUI, oui, 4)) ++ { ++ update_bcn_wmm_ie(padapter); ++ } ++ else if(_rtw_memcmp(WPS_OUI, oui, 4)) ++ { ++ update_bcn_wps_ie(padapter); ++ } ++ else if(_rtw_memcmp(P2P_OUI, oui, 4)) ++ { ++ update_bcn_p2p_ie(padapter); ++ } ++ else ++ { ++ DBG_871X("unknown OUI type!\n"); ++ } ++ ++ ++} ++ ++void update_beacon(_adapter *padapter, u8 ie_id, u8 *oui, u8 tx) ++{ ++ _irqL irqL; ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ ++ //DBG_871X("%s\n", __FUNCTION__); ++ ++ if(_FALSE == pmlmeext->bstart_bss) ++ return; ++ ++ _enter_critical_bh(&pmlmepriv->bcn_update_lock, &irqL); ++ ++ switch(ie_id) ++ { ++ case 0xFF: ++ ++ update_bcn_fixed_ie(padapter);//8: TimeStamp, 2: Beacon Interval 2:Capability ++ ++ break; ++ ++ case _TIM_IE_: ++ ++ update_BCNTIM(padapter); ++ ++ break; ++ ++ case _ERPINFO_IE_: ++ ++ update_bcn_erpinfo_ie(padapter); ++ ++ break; ++ ++ case _HT_CAPABILITY_IE_: ++ ++ update_bcn_htcap_ie(padapter); ++ ++ break; ++ ++ case _RSN_IE_2_: ++ ++ update_bcn_rsn_ie(padapter); ++ ++ break; ++ ++ case _HT_ADD_INFO_IE_: ++ ++ update_bcn_htinfo_ie(padapter); ++ ++ break; ++ ++ case _VENDOR_SPECIFIC_IE_: ++ ++ update_bcn_vendor_spec_ie(padapter, oui); ++ ++ break; ++ ++ default: ++ break; ++ } ++ ++ pmlmepriv->update_bcn = _TRUE; ++ ++ _exit_critical_bh(&pmlmepriv->bcn_update_lock, &irqL); ++ ++#ifdef CONFIG_USB_HCI ++ if(tx) ++ { ++ //send_beacon(padapter);//send_beacon must execute on TSR level ++ set_tx_beacon_cmd(padapter); ++ } ++#else ++ { ++ //PCI will issue beacon when BCN interrupt occurs. ++ } ++#endif ++ ++} ++ ++#ifdef CONFIG_80211N_HT ++ ++/* ++op_mode ++Set to 0 (HT pure) under the followign conditions ++ - all STAs in the BSS are 20/40 MHz HT in 20/40 MHz BSS or ++ - all STAs in the BSS are 20 MHz HT in 20 MHz BSS ++Set to 1 (HT non-member protection) if there may be non-HT STAs ++ in both the primary and the secondary channel ++Set to 2 if only HT STAs are associated in BSS, ++ however and at least one 20 MHz HT STA is associated ++Set to 3 (HT mixed mode) when one or more non-HT STAs are associated ++ (currently non-GF HT station is considered as non-HT STA also) ++*/ ++static int rtw_ht_operation_update(_adapter *padapter) ++{ ++ u16 cur_op_mode, new_op_mode; ++ int op_mode_changes = 0; ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ struct ht_priv *phtpriv_ap = &pmlmepriv->htpriv; ++ ++ if(pmlmepriv->htpriv.ht_option == _TRUE) ++ return 0; ++ ++ //if (!iface->conf->ieee80211n || iface->conf->ht_op_mode_fixed) ++ // return 0; ++ ++ DBG_871X("%s current operation mode=0x%X\n", ++ __FUNCTION__, pmlmepriv->ht_op_mode); ++ ++ if (!(pmlmepriv->ht_op_mode & HT_INFO_OPERATION_MODE_NON_GF_DEVS_PRESENT) ++ && pmlmepriv->num_sta_ht_no_gf) { ++ pmlmepriv->ht_op_mode |= ++ HT_INFO_OPERATION_MODE_NON_GF_DEVS_PRESENT; ++ op_mode_changes++; ++ } else if ((pmlmepriv->ht_op_mode & ++ HT_INFO_OPERATION_MODE_NON_GF_DEVS_PRESENT) && ++ pmlmepriv->num_sta_ht_no_gf == 0) { ++ pmlmepriv->ht_op_mode &= ++ ~HT_INFO_OPERATION_MODE_NON_GF_DEVS_PRESENT; ++ op_mode_changes++; ++ } ++ ++ if (!(pmlmepriv->ht_op_mode & HT_INFO_OPERATION_MODE_NON_HT_STA_PRESENT) && ++ (pmlmepriv->num_sta_no_ht || pmlmepriv->olbc_ht)) { ++ pmlmepriv->ht_op_mode |= HT_INFO_OPERATION_MODE_NON_HT_STA_PRESENT; ++ op_mode_changes++; ++ } else if ((pmlmepriv->ht_op_mode & ++ HT_INFO_OPERATION_MODE_NON_HT_STA_PRESENT) && ++ (pmlmepriv->num_sta_no_ht == 0 && !pmlmepriv->olbc_ht)) { ++ pmlmepriv->ht_op_mode &= ++ ~HT_INFO_OPERATION_MODE_NON_HT_STA_PRESENT; ++ op_mode_changes++; ++ } ++ ++ /* Note: currently we switch to the MIXED op mode if HT non-greenfield ++ * station is associated. Probably it's a theoretical case, since ++ * it looks like all known HT STAs support greenfield. ++ */ ++ new_op_mode = 0; ++ if (pmlmepriv->num_sta_no_ht || ++ (pmlmepriv->ht_op_mode & HT_INFO_OPERATION_MODE_NON_GF_DEVS_PRESENT)) ++ new_op_mode = OP_MODE_MIXED; ++ else if ((phtpriv_ap->ht_cap.cap_info & IEEE80211_HT_CAP_SUP_WIDTH) ++ && pmlmepriv->num_sta_ht_20mhz) ++ new_op_mode = OP_MODE_20MHZ_HT_STA_ASSOCED; ++ else if (pmlmepriv->olbc_ht) ++ new_op_mode = OP_MODE_MAY_BE_LEGACY_STAS; ++ else ++ new_op_mode = OP_MODE_PURE; ++ ++ cur_op_mode = pmlmepriv->ht_op_mode & HT_INFO_OPERATION_MODE_OP_MODE_MASK; ++ if (cur_op_mode != new_op_mode) { ++ pmlmepriv->ht_op_mode &= ~HT_INFO_OPERATION_MODE_OP_MODE_MASK; ++ pmlmepriv->ht_op_mode |= new_op_mode; ++ op_mode_changes++; ++ } ++ ++ DBG_871X("%s new operation mode=0x%X changes=%d\n", ++ __FUNCTION__, pmlmepriv->ht_op_mode, op_mode_changes); ++ ++ return op_mode_changes; ++ ++} ++ ++#endif /* CONFIG_80211N_HT */ ++ ++/* called > TSR LEVEL for USB or SDIO Interface*/ ++void bss_cap_update(_adapter *padapter, struct sta_info *psta) ++{ ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); ++ ++#if 0 ++ if (psta->flags & WLAN_STA_NONERP && !psta->nonerp_set) { ++ psta->nonerp_set = 1; ++ pmlmepriv->num_sta_non_erp++; ++ if (pmlmepriv->num_sta_non_erp == 1) ++ ieee802_11_set_beacons(hapd->iface); ++ } ++#endif ++ ++ if(psta->flags & WLAN_STA_NONERP) ++ { ++ if(!psta->nonerp_set) ++ { ++ psta->nonerp_set = 1; ++ ++ pmlmepriv->num_sta_non_erp++; ++ ++ if (pmlmepriv->num_sta_non_erp == 1) ++ update_beacon(padapter, _ERPINFO_IE_, NULL, _TRUE); ++ } ++ ++ } ++ else ++ { ++ if(psta->nonerp_set) ++ { ++ psta->nonerp_set = 0; ++ ++ pmlmepriv->num_sta_non_erp--; ++ ++ if (pmlmepriv->num_sta_non_erp == 0) ++ update_beacon(padapter, _ERPINFO_IE_, NULL, _TRUE); ++ } ++ ++ } ++ ++ ++#if 0 ++ if (!(psta->capability & WLAN_CAPABILITY_SHORT_SLOT) && ++ !psta->no_short_slot_time_set) { ++ psta->no_short_slot_time_set = 1; ++ pmlmepriv->num_sta_no_short_slot_time++; ++ if ((pmlmeext->cur_wireless_mode > WIRELESS_11B) && ++ (pmlmepriv->num_sta_no_short_slot_time == 1)) ++ ieee802_11_set_beacons(hapd->iface); ++ } ++#endif ++ ++ if(!(psta->capability & WLAN_CAPABILITY_SHORT_SLOT)) ++ { ++ if(!psta->no_short_slot_time_set) ++ { ++ psta->no_short_slot_time_set = 1; ++ ++ pmlmepriv->num_sta_no_short_slot_time++; ++ ++ if ((pmlmeext->cur_wireless_mode > WIRELESS_11B) && ++ (pmlmepriv->num_sta_no_short_slot_time == 1)) ++ update_beacon(padapter, 0xFF, NULL, _TRUE); ++ ++ } ++ } ++ else ++ { ++ if(psta->no_short_slot_time_set) ++ { ++ psta->no_short_slot_time_set = 0; ++ ++ pmlmepriv->num_sta_no_short_slot_time--; ++ ++ if ((pmlmeext->cur_wireless_mode > WIRELESS_11B) && ++ (pmlmepriv->num_sta_no_short_slot_time == 0)) ++ update_beacon(padapter, 0xFF, NULL, _TRUE); ++ } ++ } ++ ++ ++#if 0 ++ if (!(psta->capability & WLAN_CAPABILITY_SHORT_PREAMBLE) && ++ !psta->no_short_preamble_set) { ++ psta->no_short_preamble_set = 1; ++ pmlmepriv->num_sta_no_short_preamble++; ++ if ((pmlmeext->cur_wireless_mode > WIRELESS_11B) && ++ (pmlmepriv->num_sta_no_short_preamble == 1)) ++ ieee802_11_set_beacons(hapd->iface); ++ } ++#endif ++ ++ ++ if(!(psta->flags & WLAN_STA_SHORT_PREAMBLE)) ++ { ++ if(!psta->no_short_preamble_set) ++ { ++ psta->no_short_preamble_set = 1; ++ ++ pmlmepriv->num_sta_no_short_preamble++; ++ ++ if ((pmlmeext->cur_wireless_mode > WIRELESS_11B) && ++ (pmlmepriv->num_sta_no_short_preamble == 1)) ++ update_beacon(padapter, 0xFF, NULL, _TRUE); ++ ++ } ++ } ++ else ++ { ++ if(psta->no_short_preamble_set) ++ { ++ psta->no_short_preamble_set = 0; ++ ++ pmlmepriv->num_sta_no_short_preamble--; ++ ++ if ((pmlmeext->cur_wireless_mode > WIRELESS_11B) && ++ (pmlmepriv->num_sta_no_short_preamble == 0)) ++ update_beacon(padapter, 0xFF, NULL, _TRUE); ++ ++ } ++ } ++ ++ ++#ifdef CONFIG_80211N_HT ++ ++ if (psta->flags & WLAN_STA_HT) ++ { ++ u16 ht_capab = le16_to_cpu(psta->htpriv.ht_cap.cap_info); ++ ++ DBG_871X("HT: STA " MAC_FMT " HT Capabilities " ++ "Info: 0x%04x\n", MAC_ARG(psta->hwaddr), ht_capab); ++ ++ if (psta->no_ht_set) { ++ psta->no_ht_set = 0; ++ pmlmepriv->num_sta_no_ht--; ++ } ++ ++ if ((ht_capab & IEEE80211_HT_CAP_GRN_FLD) == 0) { ++ if (!psta->no_ht_gf_set) { ++ psta->no_ht_gf_set = 1; ++ pmlmepriv->num_sta_ht_no_gf++; ++ } ++ DBG_871X("%s STA " MAC_FMT " - no " ++ "greenfield, num of non-gf stations %d\n", ++ __FUNCTION__, MAC_ARG(psta->hwaddr), ++ pmlmepriv->num_sta_ht_no_gf); ++ } ++ ++ if ((ht_capab & IEEE80211_HT_CAP_SUP_WIDTH) == 0) { ++ if (!psta->ht_20mhz_set) { ++ psta->ht_20mhz_set = 1; ++ pmlmepriv->num_sta_ht_20mhz++; ++ } ++ DBG_871X("%s STA " MAC_FMT " - 20 MHz HT, " ++ "num of 20MHz HT STAs %d\n", ++ __FUNCTION__, MAC_ARG(psta->hwaddr), ++ pmlmepriv->num_sta_ht_20mhz); ++ } ++ ++ } ++ else ++ { ++ if (!psta->no_ht_set) { ++ psta->no_ht_set = 1; ++ pmlmepriv->num_sta_no_ht++; ++ } ++ if(pmlmepriv->htpriv.ht_option == _TRUE) { ++ DBG_871X("%s STA " MAC_FMT ++ " - no HT, num of non-HT stations %d\n", ++ __FUNCTION__, MAC_ARG(psta->hwaddr), ++ pmlmepriv->num_sta_no_ht); ++ } ++ } ++ ++ if (rtw_ht_operation_update(padapter) > 0) ++ { ++ update_beacon(padapter, _HT_CAPABILITY_IE_, NULL, _FALSE); ++ update_beacon(padapter, _HT_ADD_INFO_IE_, NULL, _TRUE); ++ } ++ ++#endif /* CONFIG_80211N_HT */ ++ ++} ++ ++void ap_free_sta(_adapter *padapter, struct sta_info *psta) ++{ ++ _irqL irqL; ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ ++ if(!psta) ++ return; ++ ++ ++ if (psta->nonerp_set) { ++ psta->nonerp_set = 0; ++ pmlmepriv->num_sta_non_erp--; ++ if (pmlmepriv->num_sta_non_erp == 0) ++ update_beacon(padapter, _ERPINFO_IE_, NULL, _TRUE); ++ } ++ ++ if (psta->no_short_slot_time_set) { ++ psta->no_short_slot_time_set = 0; ++ pmlmepriv->num_sta_no_short_slot_time--; ++ if (pmlmeext->cur_wireless_mode > WIRELESS_11B ++ && pmlmepriv->num_sta_no_short_slot_time == 0) ++ update_beacon(padapter, 0xFF, NULL, _TRUE); ++ } ++ ++ if (psta->no_short_preamble_set) { ++ psta->no_short_preamble_set = 0; ++ pmlmepriv->num_sta_no_short_preamble--; ++ if (pmlmeext->cur_wireless_mode > WIRELESS_11B ++ && pmlmepriv->num_sta_no_short_preamble == 0) ++ update_beacon(padapter, 0xFF, NULL, _TRUE); ++ } ++ ++#ifdef CONFIG_80211N_HT ++ ++ if (psta->no_ht_gf_set) { ++ psta->no_ht_gf_set = 0; ++ pmlmepriv->num_sta_ht_no_gf--; ++ } ++ ++ if (psta->no_ht_set) { ++ psta->no_ht_set = 0; ++ pmlmepriv->num_sta_no_ht--; ++ } ++ ++ if (psta->ht_20mhz_set) { ++ psta->ht_20mhz_set = 0; ++ pmlmepriv->num_sta_ht_20mhz--; ++ } ++ ++ if (rtw_ht_operation_update(padapter) > 0) ++ { ++ update_beacon(padapter, _HT_CAPABILITY_IE_, NULL, _FALSE); ++ update_beacon(padapter, _HT_ADD_INFO_IE_, NULL, _TRUE); ++ } ++ ++#endif /* CONFIG_80211N_HT */ ++ ++ ++ //tear down Rx AMPDU ++ send_delba(padapter, 0, psta->hwaddr);// recipient ++ ++ //tear down TX AMPDU ++ send_delba(padapter, 1, psta->hwaddr);// // originator ++ psta->htpriv.agg_enable_bitmap = 0x0;//reset ++ psta->htpriv.candidate_tid_bitmap = 0x0;//reset ++ ++ ++ issue_deauth(padapter, psta->hwaddr, WLAN_REASON_DEAUTH_LEAVING); ++ ++ //report_del_sta_event(padapter, psta->hwaddr, WLAN_REASON_DEAUTH_LEAVING); ++ ++ //clear key ++ //clear_cam_entry(padapter, (psta->mac_id + 3)); ++ ++ { ++ #ifdef CONFIG_IOCTL_CFG80211 ++ struct wireless_dev *pwdev = padapter->rtw_wdev; ++ ++ if(pwdev->iftype == NL80211_IFTYPE_AP) { ++ #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) && !defined(CONFIG_CFG80211_FORCE_COMPATIBLE_2_6_37_UNDER) ++ rtw_cfg80211_indicate_sta_disassoc(padapter, psta->hwaddr, WLAN_REASON_DEAUTH_LEAVING); ++ #else //(LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) && !defined(CONFIG_CFG80211_FORCE_COMPATIBLE_2_6_37_UNDER) ++ report_del_sta_event(padapter, psta->hwaddr, WLAN_REASON_DEAUTH_LEAVING); ++ #endif //(LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) && !defined(CONFIG_CFG80211_FORCE_COMPATIBLE_2_6_37_UNDER) ++ } else ++ #endif //CONFIG_IOCTL_CFG80211 ++ { ++ rtw_indicate_sta_disassoc_event(padapter, psta); ++ } ++ } ++ ++ _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL); ++ rtw_free_stainfo(padapter, psta); ++ _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL); ++ ++ ++} ++ ++int rtw_sta_flush(_adapter *padapter) ++{ ++ _irqL irqL; ++ _list *phead, *plist; ++ int ret=0; ++ struct sta_info *psta = NULL; ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ u8 bc_addr[ETH_ALEN] = {0xff,0xff,0xff,0xff,0xff,0xff}; ++ ++ DBG_871X("%s\n", __FUNCTION__); ++ ++ if((pmlmeinfo->state&0x03) != WIFI_FW_AP_STATE) ++ return ret; ++ ++ ++ _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL); ++ phead = &pstapriv->asoc_list; ++ plist = get_next(phead); ++ ++ //free sta asoc_queue ++ while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) ++ { ++ psta = LIST_CONTAINOR(plist, struct sta_info, asoc_list); ++ ++ plist = get_next(plist); ++ ++ rtw_list_delete(&psta->asoc_list); ++ ++ //_exit_critical_bh(&pstapriv->asoc_list_lock, &irqL); ++ ap_free_sta(padapter, psta); ++ //_enter_critical_bh(&pstapriv->asoc_list_lock, &irqL); ++ } ++ _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL); ++ ++ ++ issue_deauth(padapter, bc_addr, WLAN_REASON_DEAUTH_LEAVING); ++ ++ return ret; ++ ++} ++ ++/* called > TSR LEVEL for USB or SDIO Interface*/ ++void sta_info_update(_adapter *padapter, struct sta_info *psta) ++{ ++ int flags = psta->flags; ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ ++ ++ //update wmm cap. ++ if(WLAN_STA_WME&flags) ++ psta->qos_option = 1; ++ else ++ psta->qos_option = 0; ++ ++ if(pmlmepriv->qospriv.qos_option == 0) ++ psta->qos_option = 0; ++ ++ ++#ifdef CONFIG_80211N_HT ++ //update 802.11n ht cap. ++ if(WLAN_STA_HT&flags) ++ { ++ psta->htpriv.ht_option = _TRUE; ++ psta->qos_option = 1; ++ } ++ else ++ { ++ psta->htpriv.ht_option = _FALSE; ++ } ++ ++ if(pmlmepriv->htpriv.ht_option == _FALSE) ++ psta->htpriv.ht_option = _FALSE; ++#endif ++ ++ ++ update_sta_info_apmode(padapter, psta); ++ ++ ++} ++ ++/* called >= TSR LEVEL for USB or SDIO Interface*/ ++void ap_sta_info_defer_update(_adapter *padapter, struct sta_info *psta) ++{ ++ if(psta->state & _FW_LINKED) ++ { ++ //add ratid ++ add_RATid(padapter, psta); ++ } ++} ++ ++void start_ap_mode(_adapter *padapter) ++{ ++ int i; ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ ++ pmlmepriv->update_bcn = _FALSE; ++ ++ //init_mlme_ap_info(padapter); ++ pmlmeext->bstart_bss = _FALSE; ++ ++ pmlmepriv->num_sta_non_erp = 0; ++ ++ pmlmepriv->num_sta_no_short_slot_time = 0; ++ ++ pmlmepriv->num_sta_no_short_preamble = 0; ++ ++ pmlmepriv->num_sta_ht_no_gf = 0; ++ ++ pmlmepriv->num_sta_no_ht = 0; ++ ++ pmlmepriv->num_sta_ht_20mhz = 0; ++ ++ pmlmepriv->olbc = _FALSE; ++ ++ pmlmepriv->olbc_ht = _FALSE; ++ ++#ifdef CONFIG_80211N_HT ++ pmlmepriv->ht_op_mode = 0; ++#endif ++ ++ for(i=0; ista_aid[i] = NULL; ++ ++ pmlmepriv->wps_beacon_ie = NULL; ++ pmlmepriv->wps_probe_resp_ie = NULL; ++ pmlmepriv->wps_assoc_resp_ie = NULL; ++ ++ pmlmepriv->p2p_beacon_ie = NULL; ++ pmlmepriv->p2p_probe_resp_ie = NULL; ++ ++} ++ ++void stop_ap_mode(_adapter *padapter) ++{ ++ _irqL irqL; ++ //_list *phead, *plist; ++ struct sta_info *psta=NULL; ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ ++ pmlmepriv->update_bcn = _FALSE; ++ pmlmeext->bstart_bss = _FALSE; ++ //_rtw_spinlock_free(&pmlmepriv->bcn_update_lock); ++ ++ //phead = &pstapriv->asoc_list; ++ //plist = get_next(phead); ++ ++ rtw_sta_flush(padapter); ++ ++#if 0 ++ //free sta asoc_queue ++ while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) ++ { ++ psta = LIST_CONTAINOR(plist, struct sta_info, asoc_list); ++ ++ plist = get_next(plist); ++ ++ rtw_list_delete(&psta->asoc_list); ++ ++ //tear down Rx AMPDU ++ send_delba(padapter, 0, psta->hwaddr);// recipient ++ ++ //tear down TX AMPDU ++ send_delba(padapter, 1, psta->hwaddr);// // originator ++ psta->htpriv.agg_enable_bitmap = 0x0;//reset ++ psta->htpriv.candidate_tid_bitmap = 0x0;//reset ++ ++ issue_deauth(padapter, psta->hwaddr, WLAN_REASON_DEAUTH_LEAVING); ++ ++ _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL); ++ rtw_free_stainfo(padapter, psta); ++ _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL); ++ ++ } ++#endif ++ ++ //free_assoc_sta_resources ++ rtw_free_all_stainfo(padapter); ++ ++ psta = rtw_get_bcmc_stainfo(padapter); ++ _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL); ++ rtw_free_stainfo(padapter, psta); ++ _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL); ++ ++ rtw_init_bcmc_stainfo(padapter); ++ ++ rtw_free_mlme_priv_ie_data(pmlmepriv); ++ ++/* ++ if(pmlmepriv->wps_beacon_ie) ++ { ++ rtw_mfree(pmlmepriv->wps_beacon_ie, pmlmepriv->wps_beacon_ie_len); ++ pmlmepriv->wps_beacon_ie = NULL; ++ } ++ ++ if(pmlmepriv->wps_probe_resp_ie) ++ { ++ rtw_mfree(pmlmepriv->wps_probe_resp_ie, pmlmepriv->wps_probe_resp_ie_len); ++ pmlmepriv->wps_probe_resp_ie = NULL; ++ } ++ ++ if(pmlmepriv->wps_assoc_resp_ie) ++ { ++ rtw_mfree(pmlmepriv->wps_assoc_resp_ie, pmlmepriv->wps_assoc_resp_ie_len); ++ pmlmepriv->wps_assoc_resp_ie = NULL; ++ } ++ ++ if(pmlmepriv->p2p_beacon_ie) ++ { ++ rtw_mfree(pmlmepriv->p2p_beacon_ie, pmlmepriv->p2p_beacon_ie_len); ++ pmlmepriv->p2p_beacon_ie = NULL; ++ } ++ ++ if(pmlmepriv->p2p_probe_resp_ie) ++ { ++ rtw_mfree(pmlmepriv->p2p_probe_resp_ie, pmlmepriv->p2p_probe_resp_ie_len); ++ pmlmepriv->p2p_probe_resp_ie = NULL; ++ } ++*/ ++ ++} ++ ++ ++#endif ++ ++#endif ++ ++u8 set_chplan_hdl(_adapter *padapter, unsigned char *pbuf) ++{ ++ struct SetChannelPlan_param *setChannelPlan_param; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ ++ if(!pbuf) ++ return H2C_PARAMETERS_ERROR; ++ ++ setChannelPlan_param = (struct SetChannelPlan_param *)pbuf; ++ ++ pmlmeext->max_chan_nums = init_channel_set(padapter, setChannelPlan_param->channel_plan, pmlmeext->channel_set); ++ ++ return H2C_SUCCESS; ++} ++ ++u8 led_blink_hdl(_adapter *padapter, unsigned char *pbuf) ++{ ++ struct LedBlink_param *ledBlink_param; ++ ++ if(!pbuf) ++ return H2C_PARAMETERS_ERROR; ++ ++ ledBlink_param = (struct LedBlink_param *)pbuf; ++ ++ #ifdef CONFIG_LED_HANDLED_BY_CMD_THREAD ++ BlinkHandler(ledBlink_param->pLed); ++ #endif ++ ++ return H2C_SUCCESS; ++} ++ ++u8 set_csa_hdl(_adapter *padapter, unsigned char *pbuf) ++{ ++#ifdef CONFIG_DFS ++ struct SetChannelSwitch_param *setChannelSwitch_param; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info; ++ u8 new_ch_no; ++ u8 gval8 = 0x00, sval8 = 0xff; ++ ++ if(!pbuf) ++ return H2C_PARAMETERS_ERROR; ++ ++ setChannelSwitch_param = (struct SetChannelSwitch_param *)pbuf; ++ new_ch_no = setChannelSwitch_param->new_ch_no; ++ ++ padapter->HalFunc.GetHwRegHandler(padapter, HW_VAR_TXPAUSE, &gval8); ++ ++ padapter->HalFunc.SetHwRegHandler(padapter, HW_VAR_TXPAUSE, &sval8); ++ ++ DBG_8192C("DFS detected! Swiching channel to %d!\n", new_ch_no); ++ SelectChannel(padapter, new_ch_no); ++ ++ padapter->HalFunc.SetHwRegHandler(padapter, HW_VAR_TXPAUSE, &gval8); ++ ++ rtw_free_network_queue(padapter, _TRUE); ++ rtw_indicate_disconnect(padapter); ++ ++ if ( ((new_ch_no >= 52) && (new_ch_no <= 64)) ||((new_ch_no >= 100) && (new_ch_no <= 140)) ) { ++ DBG_8192C("Switched to DFS band (ch %02x) again!!\n", new_ch_no); ++ } ++ ++ return H2C_SUCCESS; ++#else ++ return H2C_REJECTED; ++#endif //CONFIG_DFS ++ ++} ++ ++// TDLS_WRCR : write RCR DATA BIT ++// TDLS_SD_PTI : issue peer traffic indication ++// TDLS_CS_OFF : go back to the channel linked with AP, terminating channel switch procedure ++// TDLS_INIT_CH_SEN : init channel sensing, receive all data and mgnt frame ++// TDLS_DONE_CH_SEN: channel sensing and report candidate channel ++// TDLS_OFF_CH : first time set channel to off channel ++// TDLS_BASE_CH : go back tp the channel linked with AP when set base channel as target channel ++// TDLS_P_OFF_CH : periodically go to off channel ++// TDLS_P_BASE_CH : periodically go back to base channel ++// TDLS_RS_RCR : restore RCR ++// TDLS_CKALV_PH1 : check alive timer phase1 ++// TDLS_CKALV_PH2 : check alive timer phase2 ++// TDLS_FREE_STA : free tdls sta ++u8 tdls_hdl(_adapter *padapter, unsigned char *pbuf) ++{ ++#ifdef CONFIG_TDLS ++ _irqL irqL; ++ struct tdls_info *ptdlsinfo = &padapter->tdlsinfo; ++ struct TDLSoption_param *TDLSoption; ++ struct sta_info *ptdls_sta; ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info; ++ u8 survey_channel, i, min, option; ++ ++ if(!pbuf) ++ return H2C_PARAMETERS_ERROR; ++ ++ TDLSoption = (struct TDLSoption_param *)pbuf; ++ ++ ptdls_sta = rtw_get_stainfo( &(padapter->stapriv), TDLSoption->addr ); ++ option = TDLSoption->option; ++ ++ if( ptdls_sta == NULL ) ++ { ++ if( option != TDLS_RS_RCR ) ++ return H2C_REJECTED; ++ } ++ ++ //_enter_critical_bh(&(ptdlsinfo->hdl_lock), &irqL); ++ DBG_8192C("[%s] option:%d\n", __FUNCTION__, option); ++ ++ switch(option){ ++ case TDLS_WRCR: ++ //As long as TDLS handshake success, we should set RCR_CBSSID_DATA bit to 0 ++ //such we can receive all kinds of data frames. ++ padapter->HalFunc.SetHwRegHandler(padapter, HW_VAR_TDLS_WRCR, 0); ++ DBG_8192C("wirte REG_RCR, set bit6 off\n"); ++ break; ++ case TDLS_SD_PTI: ++ issue_tdls_peer_traffic_indication(padapter, ptdls_sta); ++ break; ++ case TDLS_CS_OFF: ++ _cancel_timer_ex(&ptdls_sta->base_ch_timer); ++ _cancel_timer_ex(&ptdls_sta->off_ch_timer); ++ SelectChannel(padapter, pmlmeext->cur_channel); ++ ptdls_sta->tdls_sta_state &= ~(TDLS_CH_SWITCH_ON_STATE | ++ TDLS_PEER_AT_OFF_STATE | ++ TDLS_AT_OFF_CH_STATE); ++ DBG_8192C("go back to base channel\n "); ++ issue_nulldata(padapter, 0); ++ break; ++ case TDLS_INIT_CH_SEN: ++ padapter->HalFunc.SetHwRegHandler(padapter, HW_VAR_TDLS_INIT_CH_SEN, 0); ++ pmlmeext->sitesurvey_res.channel_idx = 0; ++ ptdls_sta->option = TDLS_DONE_CH_SEN; ++ rtw_tdls_cmd(padapter, ptdls_sta->hwaddr, TDLS_DONE_CH_SEN); ++ break; ++ case TDLS_DONE_CH_SEN: ++ survey_channel = pmlmeext->channel_set[pmlmeext->sitesurvey_res.channel_idx].ChannelNum; ++ if(survey_channel){ ++ SelectChannel(padapter, survey_channel); ++ ptdlsinfo->cur_channel = survey_channel; ++ pmlmeext->sitesurvey_res.channel_idx++; ++ _set_timer(&ptdls_sta->option_timer, SURVEY_TO); ++ }else{ ++ SelectChannel(padapter, pmlmeext->cur_channel); ++ ++ padapter->HalFunc.SetHwRegHandler(padapter, HW_VAR_TDLS_DONE_CH_SEN, 0); ++ ++ if(ptdlsinfo->ch_sensing==1){ ++ ptdlsinfo->ch_sensing=0; ++ ptdlsinfo->cur_channel=1; ++ min=ptdlsinfo->collect_pkt_num[0]; ++ for(i=1; i ptdlsinfo->collect_pkt_num[i]){ ++ ptdlsinfo->cur_channel=i+1; ++ min=ptdlsinfo->collect_pkt_num[i]; ++ } ++ ptdlsinfo->collect_pkt_num[i]=0; ++ } ++ ptdlsinfo->collect_pkt_num[0]=0; ++ ptdlsinfo->candidate_ch=ptdlsinfo->cur_channel; ++ DBG_8192C("TDLS channel sensing done, candidate channel: %02x\n", ptdlsinfo->candidate_ch); ++ ptdlsinfo->cur_channel=0; ++ ++ } ++ ++ if(ptdls_sta->tdls_sta_state & TDLS_PEER_SLEEP_STATE){ ++ ptdls_sta->tdls_sta_state |= TDLS_APSD_CHSW_STATE; ++ }else{ ++ //send null data with pwrbit==1 before send ch_switching_req to peer STA. ++ issue_nulldata(padapter, 1); ++ ++ ptdls_sta->tdls_sta_state |= TDLS_CH_SW_INITIATOR_STATE; ++ ++ issue_tdls_ch_switch_req(padapter, ptdls_sta->hwaddr); ++ DBG_8192C("issue tdls ch switch req\n"); ++ } ++ } ++ break; ++ case TDLS_OFF_CH: ++ issue_nulldata(padapter, 1); ++ SelectChannel(padapter, ptdls_sta->off_ch); ++ ++ DBG_8192C("change channel to tar ch:%02x\n", ptdls_sta->off_ch); ++ ptdls_sta->tdls_sta_state |= TDLS_AT_OFF_CH_STATE; ++ ptdls_sta->tdls_sta_state &= ~(TDLS_PEER_AT_OFF_STATE); ++ _set_timer(&ptdls_sta->option_timer, (u32)ptdls_sta->ch_switch_time); ++ break; ++ case TDLS_BASE_CH: ++ _cancel_timer_ex(&ptdls_sta->base_ch_timer); ++ _cancel_timer_ex(&ptdls_sta->off_ch_timer); ++ SelectChannel(padapter, pmlmeext->cur_channel); ++ ptdls_sta->tdls_sta_state &= ~(TDLS_CH_SWITCH_ON_STATE | ++ TDLS_PEER_AT_OFF_STATE | ++ TDLS_AT_OFF_CH_STATE); ++ DBG_8192C("go back to base channel\n "); ++ issue_nulldata(padapter, 0); ++ _set_timer(&ptdls_sta->option_timer, (u32)ptdls_sta->ch_switch_time); ++ break; ++ case TDLS_P_OFF_CH: ++ SelectChannel(padapter, pmlmeext->cur_channel); ++ issue_nulldata(padapter, 0); ++ DBG_8192C("change channel to base ch:%02x\n", pmlmeext->cur_channel); ++ ptdls_sta->tdls_sta_state &= ~(TDLS_PEER_AT_OFF_STATE| TDLS_AT_OFF_CH_STATE); ++ _set_timer(&ptdls_sta->off_ch_timer, TDLS_STAY_TIME); ++ break; ++ case TDLS_P_BASE_CH: ++ issue_nulldata(ptdls_sta->padapter, 1); ++ SelectChannel(padapter, ptdls_sta->off_ch); ++ DBG_8192C("change channel to off ch:%02x\n", ptdls_sta->off_ch); ++ ptdls_sta->tdls_sta_state |= TDLS_AT_OFF_CH_STATE; ++ if((ptdls_sta->tdls_sta_state & TDLS_PEER_AT_OFF_STATE) != TDLS_PEER_AT_OFF_STATE){ ++ issue_nulldata_to_TDLS_peer_STA(padapter, ptdls_sta, 0); ++ } ++ _set_timer(&ptdls_sta->base_ch_timer, TDLS_STAY_TIME); ++ break; ++ case TDLS_RS_RCR: ++ padapter->HalFunc.SetHwRegHandler(padapter, HW_VAR_TDLS_RS_RCR, 0); ++ DBG_8192C("wirte REG_RCR, set bit6 on\n"); ++ break; ++ case TDLS_CKALV_PH1: ++ _set_timer(&ptdls_sta->alive_timer2, TDLS_ALIVE_TIMER_PH2); ++ break; ++ case TDLS_CKALV_PH2: ++ _set_timer(&ptdls_sta->alive_timer1, TDLS_ALIVE_TIMER_PH1); ++ break; ++ case TDLS_FREE_STA: ++ free_tdls_sta(padapter, ptdls_sta); ++ break; ++ ++ } ++ ++ //_exit_critical_bh(&(ptdlsinfo->hdl_lock), &irqL); ++ ++ return H2C_SUCCESS; ++#else ++ return H2C_REJECTED; ++#endif //CONFIG_TDLS ++ ++} +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/core/rtw_mp.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/core/rtw_mp.c 2013-07-26 19:36:05.000000000 +0000 +@@ -0,0 +1,1318 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#define _RTW_MP_C_ ++ ++#include ++ ++#ifdef CONFIG_RTL8712 ++#include ++#endif ++#ifdef CONFIG_RTL8192C ++#include ++#endif ++#ifdef CONFIG_RTL8192D ++#include ++#endif ++ ++ ++#ifdef CONFIG_MP_INCLUDED ++ ++u32 read_macreg(_adapter *padapter, u32 addr, u32 sz) ++{ ++ u32 val = 0; ++ ++ switch(sz) ++ { ++ case 1: ++ val = rtw_read8(padapter, addr); ++ break; ++ case 2: ++ val = rtw_read16(padapter, addr); ++ break; ++ case 4: ++ val = rtw_read32(padapter, addr); ++ break; ++ default: ++ val = 0xffffffff; ++ break; ++ } ++ ++ return val; ++ ++} ++ ++void write_macreg(_adapter *padapter, u32 addr, u32 val, u32 sz) ++{ ++ switch(sz) ++ { ++ case 1: ++ rtw_write8(padapter, addr, (u8)val); ++ break; ++ case 2: ++ rtw_write16(padapter, addr, (u16)val); ++ break; ++ case 4: ++ rtw_write32(padapter, addr, val); ++ break; ++ default: ++ break; ++ } ++ ++} ++ ++u32 read_bbreg(_adapter *padapter, u32 addr, u32 bitmask) ++{ ++ return padapter->HalFunc.read_bbreg(padapter, addr, bitmask); ++} ++ ++void write_bbreg(_adapter *padapter, u32 addr, u32 bitmask, u32 val) ++{ ++ padapter->HalFunc.write_bbreg(padapter, addr, bitmask, val); ++} ++ ++u32 _read_rfreg(PADAPTER padapter, u8 rfpath, u32 addr, u32 bitmask) ++{ ++ return padapter->HalFunc.read_rfreg(padapter, (RF90_RADIO_PATH_E)rfpath, addr, bitmask); ++} ++ ++void _write_rfreg(PADAPTER padapter, u8 rfpath, u32 addr, u32 bitmask, u32 val) ++{ ++ padapter->HalFunc.write_rfreg(padapter, (RF90_RADIO_PATH_E)rfpath, addr, bitmask, val); ++} ++ ++u32 read_rfreg(PADAPTER padapter, u8 rfpath, u32 addr) ++{ ++ return _read_rfreg(padapter, (RF90_RADIO_PATH_E)rfpath, addr, bRFRegOffsetMask); ++} ++ ++void write_rfreg(PADAPTER padapter, u8 rfpath, u32 addr, u32 val) ++{ ++ _write_rfreg(padapter, (RF90_RADIO_PATH_E)rfpath, addr, bRFRegOffsetMask, val); ++} ++ ++ ++static void _init_mp_priv_(struct mp_priv *pmp_priv) ++{ ++ WLAN_BSSID_EX *pnetwork; ++ ++ _rtw_memset(pmp_priv, 0, sizeof(struct mp_priv)); ++ ++ pmp_priv->mode = MP_OFF; ++ ++ pmp_priv->channel = 1; ++ pmp_priv->bandwidth = HT_CHANNEL_WIDTH_20; ++ pmp_priv->prime_channel_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; ++ pmp_priv->rateidx = MPT_RATE_1M; ++ pmp_priv->txpoweridx = 0x2A; ++ ++ pmp_priv->antenna_tx = ANTENNA_A; ++ pmp_priv->antenna_rx = ANTENNA_AB; ++ ++ pmp_priv->check_mp_pkt = 0; ++ ++ pmp_priv->tx_pktcount = 0; ++ ++ pmp_priv->rx_pktcount = 0; ++ pmp_priv->rx_crcerrpktcount = 0; ++ ++ pmp_priv->network_macaddr[0] = 0x00; ++ pmp_priv->network_macaddr[1] = 0xE0; ++ pmp_priv->network_macaddr[2] = 0x4C; ++ pmp_priv->network_macaddr[3] = 0x87; ++ pmp_priv->network_macaddr[4] = 0x66; ++ pmp_priv->network_macaddr[5] = 0x55; ++ ++ pnetwork = &pmp_priv->mp_network.network; ++ _rtw_memcpy(pnetwork->MacAddress, pmp_priv->network_macaddr, ETH_ALEN); ++ ++ pnetwork->Ssid.SsidLength = 8; ++ _rtw_memcpy(pnetwork->Ssid.Ssid, "mp_871x", pnetwork->Ssid.SsidLength); ++} ++ ++#ifdef PLATFORM_WINDOWS ++/* ++void mp_wi_callback( ++ IN NDIS_WORK_ITEM* pwk_item, ++ IN PVOID cntx ++ ) ++{ ++ _adapter* padapter =(_adapter *)cntx; ++ struct mp_priv *pmppriv=&padapter->mppriv; ++ struct mp_wi_cntx *pmp_wi_cntx=&pmppriv->wi_cntx; ++ ++ // Execute specified action. ++ if(pmp_wi_cntx->curractfunc != NULL) ++ { ++ LARGE_INTEGER cur_time; ++ ULONGLONG start_time, end_time; ++ NdisGetCurrentSystemTime(&cur_time); // driver version ++ start_time = cur_time.QuadPart/10; // The return value is in microsecond ++ ++ pmp_wi_cntx->curractfunc(padapter); ++ ++ NdisGetCurrentSystemTime(&cur_time); // driver version ++ end_time = cur_time.QuadPart/10; // The return value is in microsecond ++ ++ RT_TRACE(_module_mp_, _drv_info_, ++ ("WorkItemActType: %d, time spent: %I64d us\n", ++ pmp_wi_cntx->param.act_type, (end_time-start_time))); ++ } ++ ++ NdisAcquireSpinLock(&(pmp_wi_cntx->mp_wi_lock)); ++ pmp_wi_cntx->bmp_wi_progress= _FALSE; ++ NdisReleaseSpinLock(&(pmp_wi_cntx->mp_wi_lock)); ++ ++ if (pmp_wi_cntx->bmpdrv_unload) ++ { ++ NdisSetEvent(&(pmp_wi_cntx->mp_wi_evt)); ++ } ++ ++} ++*/ ++ ++static int init_mp_priv_by_os(struct mp_priv *pmp_priv) ++{ ++ struct mp_wi_cntx *pmp_wi_cntx; ++ ++ if (pmp_priv == NULL) return _FAIL; ++ ++ pmp_priv->rx_testcnt = 0; ++ pmp_priv->rx_testcnt1 = 0; ++ pmp_priv->rx_testcnt2 = 0; ++ ++ pmp_priv->tx_testcnt = 0; ++ pmp_priv->tx_testcnt1 = 0; ++ ++ pmp_wi_cntx = &pmp_priv->wi_cntx ++ pmp_wi_cntx->bmpdrv_unload = _FALSE; ++ pmp_wi_cntx->bmp_wi_progress = _FALSE; ++ pmp_wi_cntx->curractfunc = NULL; ++ ++ return _SUCCESS; ++} ++#endif ++ ++#ifdef PLATFORM_LINUX ++static int init_mp_priv_by_os(struct mp_priv *pmp_priv) ++{ ++ int i, res; ++ struct mp_xmit_frame *pmp_xmitframe; ++ ++ if (pmp_priv == NULL) return _FAIL; ++ ++ _rtw_init_queue(&pmp_priv->free_mp_xmitqueue); ++ ++ pmp_priv->pallocated_mp_xmitframe_buf = NULL; ++ pmp_priv->pallocated_mp_xmitframe_buf = rtw_zmalloc(NR_MP_XMITFRAME * sizeof(struct mp_xmit_frame) + 4); ++ if (pmp_priv->pallocated_mp_xmitframe_buf == NULL) { ++ res = _FAIL; ++ goto _exit_init_mp_priv; ++ } ++ ++ pmp_priv->pmp_xmtframe_buf = pmp_priv->pallocated_mp_xmitframe_buf + 4 - ((uint) (pmp_priv->pallocated_mp_xmitframe_buf) & 3); ++ ++ pmp_xmitframe = (struct mp_xmit_frame*)pmp_priv->pmp_xmtframe_buf; ++ ++ for (i = 0; i < NR_MP_XMITFRAME; i++) ++ { ++ _rtw_init_listhead(&pmp_xmitframe->list); ++ rtw_list_insert_tail(&pmp_xmitframe->list, &pmp_priv->free_mp_xmitqueue.queue); ++ ++ pmp_xmitframe->pkt = NULL; ++ pmp_xmitframe->frame_tag = MP_FRAMETAG; ++ pmp_xmitframe->padapter = pmp_priv->papdater; ++ ++ pmp_xmitframe++; ++ } ++ ++ pmp_priv->free_mp_xmitframe_cnt = NR_MP_XMITFRAME; ++ ++ res = _SUCCESS; ++ ++_exit_init_mp_priv: ++ ++ return res; ++} ++#endif ++ ++static void mp_init_xmit_attrib(struct mp_tx *pmptx, PADAPTER padapter) ++{ ++ struct pkt_attrib *pattrib; ++ struct tx_desc *desc; ++ ++ // init xmitframe attribute ++ pattrib = &pmptx->attrib; ++ _rtw_memset(pattrib, 0, sizeof(struct pkt_attrib)); ++ desc = &pmptx->desc; ++ _rtw_memset(desc, 0, TXDESC_SIZE); ++ ++ pattrib->ether_type = 0x8712; ++ //_rtw_memcpy(pattrib->src, padapter->eeprompriv.mac_addr, ETH_ALEN); ++// _rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN); ++ _rtw_memset(pattrib->dst, 0xFF, ETH_ALEN); ++// pattrib->pctrl = 0; ++// pattrib->dhcp_pkt = 0; ++// pattrib->pktlen = 0; ++ pattrib->ack_policy = 0; ++// pattrib->pkt_hdrlen = ETH_HLEN; ++ pattrib->hdrlen = WLAN_HDR_A3_LEN; ++ pattrib->subtype = WIFI_DATA; ++ pattrib->priority = 0; ++ pattrib->qsel = pattrib->priority; ++// do_queue_select(padapter, pattrib); ++ pattrib->nr_frags = 1; ++ pattrib->encrypt = 0; ++ pattrib->bswenc = _FALSE; ++ pattrib->qos_en = _FALSE; ++} ++ ++s32 init_mp_priv(PADAPTER padapter) ++{ ++ struct mp_priv *pmppriv = &padapter->mppriv; ++ ++ _init_mp_priv_(pmppriv); ++ pmppriv->papdater = padapter; ++ ++ pmppriv->tx.stop = 1; ++ mp_init_xmit_attrib(&pmppriv->tx, padapter); ++ ++ switch (padapter->registrypriv.rf_config) { ++ case RF_1T1R: ++ pmppriv->antenna_tx = ANTENNA_A; ++ pmppriv->antenna_rx = ANTENNA_A; ++ break; ++ case RF_1T2R: ++ default: ++ pmppriv->antenna_tx = ANTENNA_A; ++ pmppriv->antenna_rx = ANTENNA_AB; ++ break; ++ case RF_2T2R: ++ case RF_2T2R_GREEN: ++ pmppriv->antenna_tx = ANTENNA_AB; ++ pmppriv->antenna_rx = ANTENNA_AB; ++ break; ++ case RF_2T4R: ++ pmppriv->antenna_tx = ANTENNA_AB; ++ pmppriv->antenna_rx = ANTENNA_ABCD; ++ break; ++ } ++ ++ return _SUCCESS; ++} ++ ++void free_mp_priv(struct mp_priv *pmp_priv) ++{ ++ if (pmp_priv->pallocated_mp_xmitframe_buf) { ++ rtw_mfree(pmp_priv->pallocated_mp_xmitframe_buf, 0); ++ pmp_priv->pallocated_mp_xmitframe_buf = NULL; ++ } ++ pmp_priv->pmp_xmtframe_buf = NULL; ++} ++ ++#ifdef CONFIG_RTL8192C ++#define PHY_IQCalibrate(a,b) rtl8192c_PHY_IQCalibrate(a,b) ++#define PHY_LCCalibrate(a) rtl8192c_PHY_LCCalibrate(a) ++#define dm_CheckTXPowerTracking(a) rtl8192c_dm_CheckTXPowerTracking(a) ++#define PHY_SetRFPathSwitch(a,b) rtl8192c_PHY_SetRFPathSwitch(a,b) ++#endif ++ ++#ifdef CONFIG_RTL8192D ++#define PHY_IQCalibrate(a) rtl8192d_PHY_IQCalibrate(a) ++#define PHY_LCCalibrate(a) rtl8192d_PHY_LCCalibrate(a) ++#define dm_CheckTXPowerTracking(a) rtl8192d_dm_CheckTXPowerTracking(a) ++#define PHY_SetRFPathSwitch(a,b) rtl8192d_PHY_SetRFPathSwitch(a,b) ++#endif ++ ++s32 ++MPT_InitializeAdapter( ++ IN PADAPTER pAdapter, ++ IN u8 Channel ++ ) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); ++ s32 rtStatus = _SUCCESS; ++ PMPT_CONTEXT pMptCtx = &pAdapter->mppriv.MptCtx; ++ u32 tmpRegA, tmpRegC, TempCCk,ledsetting; ++ ++ //------------------------------------------------------------------------- ++ // HW Initialization for 8190 MPT. ++ //------------------------------------------------------------------------- ++ //------------------------------------------------------------------------- ++ // SW Initialization for 8190 MP. ++ //------------------------------------------------------------------------- ++ pMptCtx->bMptDrvUnload = _FALSE; ++ pMptCtx->bMassProdTest = _FALSE; ++ pMptCtx->bMptIndexEven = _TRUE; //default gain index is -6.0db ++ ++ /* Init mpt event. */ ++#if 0 // for Windows ++ NdisInitializeEvent( &(pMptCtx->MptWorkItemEvent) ); ++ NdisAllocateSpinLock( &(pMptCtx->MptWorkItemSpinLock) ); ++ ++ PlatformInitializeWorkItem( ++ Adapter, ++ &(pMptCtx->MptWorkItem), ++ (RT_WORKITEM_CALL_BACK)MPT_WorkItemCallback, ++ (PVOID)Adapter, ++ "MptWorkItem"); ++#endif ++ pMptCtx->bMptWorkItemInProgress = _FALSE; ++ pMptCtx->CurrMptAct = NULL; ++ //------------------------------------------------------------------------- ++ ++#if 1 ++ // Don't accept any packets ++ rtw_write32(pAdapter, REG_RCR, 0); ++#else ++ // Accept CRC error and destination address ++ pHalData->ReceiveConfig |= (RCR_ACRC32|RCR_AAP); ++ rtw_write32(pAdapter, REG_RCR, pHalData->ReceiveConfig); ++#endif ++ ++#if 0 ++ // If EEPROM or EFUSE is empty,we assign as RF 2T2R for MP. ++ if (pHalData->AutoloadFailFlag == TRUE) ++ { ++ pHalData->RF_Type = RF_2T2R; ++ } ++#endif ++ ledsetting = rtw_read32(pAdapter, REG_LEDCFG0); ++ rtw_write32(pAdapter, REG_LEDCFG0, ledsetting & ~LED0DIS); ++ ++#ifdef CONFIG_RTL8192C ++ PHY_IQCalibrate(pAdapter, _FALSE); ++ dm_CheckTXPowerTracking(pAdapter); //trigger thermal meter ++ PHY_LCCalibrate(pAdapter); ++#endif ++ ++#ifdef CONFIG_RTL8192D ++ PHY_IQCalibrate(pAdapter); ++ dm_CheckTXPowerTracking(pAdapter); //trigger thermal meter ++ PHY_LCCalibrate(pAdapter); ++#endif ++ ++#ifdef CONFIG_PCI_HCI ++ PHY_SetRFPathSwitch(pAdapter, 1/*pHalData->bDefaultAntenna*/); //Wifi default use Main ++#else ++ ++#ifdef CONFIG_RTL8192C ++#if 1 ++ if (pHalData->BoardType == BOARD_MINICARD) ++ PHY_SetRFPathSwitch(pAdapter, 1/*pHalData->bDefaultAntenna*/); //default use Main ++#else ++ if(pAdapter->HalFunc.GetInterfaceSelectionHandler(pAdapter) == INTF_SEL2_MINICARD ) ++ PHY_SetRFPathSwitch(Adapter, pAdapter->MgntInfo.bDefaultAntenna); //default use Main ++#endif ++ ++#endif ++ ++#endif ++ ++ pMptCtx->backup0xc50 = (u1Byte)PHY_QueryBBReg(pAdapter, rOFDM0_XAAGCCore1, bMaskByte0); ++ pMptCtx->backup0xc58 = (u1Byte)PHY_QueryBBReg(pAdapter, rOFDM0_XBAGCCore1, bMaskByte0); ++ pMptCtx->backup0xc30 = (u1Byte)PHY_QueryBBReg(pAdapter, rOFDM0_RxDetector1, bMaskByte0); ++ ++ return rtStatus; ++} ++ ++/*----------------------------------------------------------------------------- ++ * Function: MPT_DeInitAdapter() ++ * ++ * Overview: Extra DeInitialization for Mass Production Test. ++ * ++ * Input: PADAPTER pAdapter ++ * ++ * Output: NONE ++ * ++ * Return: NONE ++ * ++ * Revised History: ++ * When Who Remark ++ * 05/08/2007 MHC Create Version 0. ++ * 05/18/2007 MHC Add normal driver MPHalt code. ++ * ++ *---------------------------------------------------------------------------*/ ++VOID ++MPT_DeInitAdapter( ++ IN PADAPTER pAdapter ++ ) ++{ ++ PMPT_CONTEXT pMptCtx = &pAdapter->mppriv.MptCtx; ++ ++ pMptCtx->bMptDrvUnload = _TRUE; ++#if 0 // for Windows ++ PlatformFreeWorkItem( &(pMptCtx->MptWorkItem) ); ++ ++ while(pMptCtx->bMptWorkItemInProgress) ++ { ++ if(NdisWaitEvent(&(pMptCtx->MptWorkItemEvent), 50)) ++ { ++ break; ++ } ++ } ++ NdisFreeSpinLock( &(pMptCtx->MptWorkItemSpinLock) ); ++#endif ++} ++ ++static u8 mpt_ProStartTest(PADAPTER padapter) ++{ ++ PMPT_CONTEXT pMptCtx = &padapter->mppriv.MptCtx; ++ ++ pMptCtx->bMassProdTest = _TRUE; ++ pMptCtx->bStartContTx = _FALSE; ++ pMptCtx->bCckContTx = _FALSE; ++ pMptCtx->bOfdmContTx = _FALSE; ++ pMptCtx->bSingleCarrier = _FALSE; ++ pMptCtx->bCarrierSuppression = _FALSE; ++ pMptCtx->bSingleTone = _FALSE; ++ ++ return _SUCCESS; ++} ++ ++/* ++ * General use ++ */ ++s32 SetPowerTracking(PADAPTER padapter, u8 enable) ++{ ++ ++ Hal_SetPowerTracking( padapter, enable ); ++ return 0; ++} ++ ++void GetPowerTracking(PADAPTER padapter, u8 *enable) ++{ ++ Hal_GetPowerTracking( padapter, enable ); ++} ++ ++static void disable_dm(PADAPTER padapter) ++{ ++ u8 v8; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); ++ struct dm_priv *pdmpriv = &pHalData->dmpriv; ++ ++ ++ //3 1. disable firmware dynamic mechanism ++ // disable Power Training, Rate Adaptive ++ v8 = rtw_read8(padapter, REG_BCN_CTRL); ++ v8 &= ~EN_BCN_FUNCTION; ++ rtw_write8(padapter, REG_BCN_CTRL, v8); ++ ++ //3 2. disable driver dynamic mechanism ++ // disable Dynamic Initial Gain ++ // disable High Power ++ // disable Power Tracking ++ Switch_DM_Func(padapter, DYNAMIC_FUNC_DISABLE, _FALSE); ++ ++ // enable APK, LCK and IQK but disable power tracking ++ pdmpriv->TxPowerTrackControl = _FALSE; ++ Switch_DM_Func(padapter, DYNAMIC_FUNC_SS, _TRUE); ++} ++ ++//This function initializes the DUT to the MP test mode ++s32 mp_start_test(PADAPTER padapter) ++{ ++ WLAN_BSSID_EX bssid; ++ struct sta_info *psta; ++ u32 length; ++ u8 val8; ++ ++ _irqL irqL; ++ s32 res = _SUCCESS; ++ ++ struct mp_priv *pmppriv = &padapter->mppriv; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct wlan_network *tgt_network = &pmlmepriv->cur_network; ++ ++ ++ //3 disable dynamic mechanism ++ disable_dm(padapter); ++ ++ //3 0. update mp_priv ++#if defined (CONFIG_RTL8192C) || defined (CONFIG_RTL8192D) ++ if (padapter->registrypriv.rf_config == RF_819X_MAX_TYPE) { ++// HAL_DATA_TYPE *phal = GET_HAL_DATA(padapter); ++// switch (phal->rf_type) { ++ switch (GET_RF_TYPE(padapter)) { ++ case RF_1T1R: ++ pmppriv->antenna_tx = ANTENNA_A; ++ pmppriv->antenna_rx = ANTENNA_A; ++ break; ++ case RF_1T2R: ++ default: ++ pmppriv->antenna_tx = ANTENNA_A; ++ pmppriv->antenna_rx = ANTENNA_AB; ++ break; ++ case RF_2T2R: ++ case RF_2T2R_GREEN: ++ pmppriv->antenna_tx = ANTENNA_AB; ++ pmppriv->antenna_rx = ANTENNA_AB; ++ break; ++ case RF_2T4R: ++ pmppriv->antenna_tx = ANTENNA_AB; ++ pmppriv->antenna_rx = ANTENNA_ABCD; ++ break; ++ } ++ } ++#endif ++ mpt_ProStartTest(padapter); ++ ++ //3 1. initialize a new WLAN_BSSID_EX ++// _rtw_memset(&bssid, 0, sizeof(WLAN_BSSID_EX)); ++ _rtw_memcpy(bssid.MacAddress, pmppriv->network_macaddr, ETH_ALEN); ++ bssid.Ssid.SsidLength = strlen("mp_pseudo_adhoc"); ++ _rtw_memcpy(bssid.Ssid.Ssid, (u8*)"mp_pseudo_adhoc", bssid.Ssid.SsidLength); ++ bssid.InfrastructureMode = Ndis802_11IBSS; ++ bssid.NetworkTypeInUse = Ndis802_11DS; ++ bssid.IELength = 0; ++ ++ length = get_WLAN_BSSID_EX_sz(&bssid); ++ if (length % 4) ++ bssid.Length = ((length >> 2) + 1) << 2; //round up to multiple of 4 bytes. ++ else ++ bssid.Length = length; ++ ++ _enter_critical_bh(&pmlmepriv->lock, &irqL); ++ ++ if (check_fwstate(pmlmepriv, WIFI_MP_STATE) == _TRUE) ++ goto end_of_mp_start_test; ++ ++ //init mp_start_test status ++ if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) { ++ rtw_disassoc_cmd(padapter); ++ rtw_indicate_disconnect(padapter); ++ rtw_free_assoc_resources(padapter, 1); ++ } ++ pmppriv->prev_fw_state = get_fwstate(pmlmepriv); ++ pmlmepriv->fw_state = WIFI_MP_STATE; ++#if 0 ++ if (pmppriv->mode == _LOOPBOOK_MODE_) { ++ set_fwstate(pmlmepriv, WIFI_MP_LPBK_STATE); //append txdesc ++ RT_TRACE(_module_mp_, _drv_notice_, ("+start mp in Lookback mode\n")); ++ } else { ++ RT_TRACE(_module_mp_, _drv_notice_, ("+start mp in normal mode\n")); ++ } ++#endif ++ set_fwstate(pmlmepriv, _FW_UNDER_LINKING); ++ ++ //3 2. create a new psta for mp driver ++ //clear psta in the cur_network, if any ++ psta = rtw_get_stainfo(&padapter->stapriv, tgt_network->network.MacAddress); ++ if (psta) rtw_free_stainfo(padapter, psta); ++ ++ psta = rtw_alloc_stainfo(&padapter->stapriv, bssid.MacAddress); ++ if (psta == NULL) { ++ RT_TRACE(_module_mp_, _drv_err_, ("mp_start_test: Can't alloc sta_info!\n")); ++ pmlmepriv->fw_state = pmppriv->prev_fw_state; ++ res = _FAIL; ++ goto end_of_mp_start_test; ++ } ++ ++ //3 3. join psudo AdHoc ++ tgt_network->join_res = 1; ++ tgt_network->aid = psta->aid = 1; ++ _rtw_memcpy(&tgt_network->network, &bssid, length); ++ ++ rtw_indicate_connect(padapter); ++ _clr_fwstate_(pmlmepriv, _FW_UNDER_LINKING); ++ ++end_of_mp_start_test: ++ ++ _exit_critical_bh(&pmlmepriv->lock, &irqL); ++ ++ if (res == _SUCCESS) ++ { ++ // set MSR to WIFI_FW_ADHOC_STATE ++#if defined (CONFIG_RTL8192C) || defined (CONFIG_RTL8192D) ++ val8 = rtw_read8(padapter, MSR) & 0xFC; // 0x0102 ++ val8 |= WIFI_FW_ADHOC_STATE; ++ rtw_write8(padapter, MSR, val8); // Link in ad hoc network ++#endif ++ ++#if !defined (CONFIG_RTL8192C) && !defined (CONFIG_RTL8192D) ++ rtw_write8(padapter, MSR, 1); // Link in ad hoc network ++ rtw_write8(padapter, RCR, 0); // RCR : disable all pkt, 0x10250048 ++ rtw_write8(padapter, RCR+2, 0x57); // RCR disable Check BSSID, 0x1025004a ++ ++ // disable RX filter map , mgt frames will put in RX FIFO 0 ++ rtw_write16(padapter, RXFLTMAP0, 0x0); // 0x10250116 ++ ++ val8 = rtw_read8(padapter, EE_9346CR); // 0x1025000A ++ if (!(val8 & _9356SEL))//boot from EFUSE ++ efuse_change_max_size(padapter); ++#endif ++ } ++ ++ return res; ++} ++//------------------------------------------------------------------------------ ++//This function change the DUT from the MP test mode into normal mode ++void mp_stop_test(PADAPTER padapter) ++{ ++ struct mp_priv *pmppriv = &padapter->mppriv; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct wlan_network *tgt_network = &pmlmepriv->cur_network; ++ struct sta_info *psta; ++ ++ _irqL irqL; ++ ++ ++ _enter_critical_bh(&pmlmepriv->lock, &irqL); ++ ++ if (check_fwstate(pmlmepriv, WIFI_MP_STATE) == _FALSE) ++ goto end_of_mp_stop_test; ++ ++ //3 1. disconnect psudo AdHoc ++ rtw_indicate_disconnect(padapter); ++ ++ //3 2. clear psta used in mp test mode. ++// rtw_free_assoc_resources(padapter, 1); ++ psta = rtw_get_stainfo(&padapter->stapriv, tgt_network->network.MacAddress); ++ if (psta) rtw_free_stainfo(padapter, psta); ++ ++ //3 3. return to normal state (default:station mode) ++ pmlmepriv->fw_state = pmppriv->prev_fw_state; // WIFI_STATION_STATE; ++ ++ //flush the cur_network ++ _rtw_memset(tgt_network, 0, sizeof(struct wlan_network)); ++ ++ _clr_fwstate_(pmlmepriv, WIFI_MP_STATE); ++ ++end_of_mp_stop_test: ++ ++ _exit_critical_bh(&pmlmepriv->lock, &irqL); ++} ++/*---------------------------hal\rtl8192c\MPT_Phy.c---------------------------*/ ++#if 0 ++//#ifdef CONFIG_USB_HCI ++static VOID mpt_AdjustRFRegByRateByChan92CU(PADAPTER pAdapter, u8 RateIdx, u8 Channel, u8 BandWidthID) ++{ ++ u8 eRFPath; ++ u32 rfReg0x26; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); ++ ++ ++ if (RateIdx < MPT_RATE_6M) { // CCK rate,for 88cu ++ rfReg0x26 = 0xf400; ++ } ++ else if ((RateIdx >= MPT_RATE_6M) && (RateIdx <= MPT_RATE_54M)) {// OFDM rate,for 88cu ++ if ((4 == Channel) || (8 == Channel) || (12 == Channel)) ++ rfReg0x26 = 0xf000; ++ else if ((5 == Channel) || (7 == Channel) || (13 == Channel) || (14 == Channel)) ++ rfReg0x26 = 0xf400; ++ else ++ rfReg0x26 = 0x4f200; ++ } ++ else if ((RateIdx >= MPT_RATE_MCS0) && (RateIdx <= MPT_RATE_MCS15)) {// MCS 20M ,for 88cu // MCS40M rate,for 88cu ++ ++ if (HT_CHANNEL_WIDTH_20 == BandWidthID) { ++ if ((4 == Channel) || (8 == Channel)) ++ rfReg0x26 = 0xf000; ++ else if ((5 == Channel) || (7 == Channel) || (13 == Channel) || (14 == Channel)) ++ rfReg0x26 = 0xf400; ++ else ++ rfReg0x26 = 0x4f200; ++ } ++ else{ ++ if ((4 == Channel) || (8 == Channel)) ++ rfReg0x26 = 0xf000; ++ else if ((5 == Channel) || (7 == Channel)) ++ rfReg0x26 = 0xf400; ++ else ++ rfReg0x26 = 0x4f200; ++ } ++ } ++ ++// RT_TRACE(COMP_CMD, DBG_LOUD, ("\n mpt_AdjustRFRegByRateByChan92CU():Chan:%d Rate=%d rfReg0x26:0x%08x\n",Channel, RateIdx,rfReg0x26)); ++ for (eRFPath = 0; eRFPath < pHalData->NumTotalRFPath; eRFPath++) { ++ write_rfreg(pAdapter, eRFPath, RF_SYN_G2, rfReg0x26); ++ } ++} ++#endif ++/*----------------------------------------------------------------------------- ++ * Function: mpt_SwitchRfSetting ++ * ++ * Overview: Change RF Setting when we siwthc channel/rate/BW for MP. ++ * ++ * Input: IN PADAPTER pAdapter ++ * ++ * Output: NONE ++ * ++ * Return: NONE ++ * ++ * Revised History: ++ * When Who Remark ++ * 01/08/2009 MHC Suggestion from SD3 Willis for 92S series. ++ * 01/09/2009 MHC Add CCK modification for 40MHZ. Suggestion from SD3. ++ * ++ *---------------------------------------------------------------------------*/ ++static void mpt_SwitchRfSetting(PADAPTER pAdapter) ++{ ++ Hal_mpt_SwitchRfSetting(pAdapter); ++ } ++ ++/*---------------------------hal\rtl8192c\MPT_Phy.c---------------------------*/ ++/*---------------------------hal\rtl8192c\MPT_HelperFunc.c---------------------------*/ ++static void MPT_CCKTxPowerAdjust(PADAPTER Adapter, BOOLEAN bInCH14) ++{ ++ Hal_MPT_CCKTxPowerAdjust(Adapter,bInCH14); ++} ++ ++static void MPT_CCKTxPowerAdjustbyIndex(PADAPTER pAdapter, BOOLEAN beven) ++{ ++ Hal_MPT_CCKTxPowerAdjustbyIndex(pAdapter,beven); ++ } ++ ++/*---------------------------hal\rtl8192c\MPT_HelperFunc.c---------------------------*/ ++ ++/* ++ * SetChannel ++ * Description ++ * Use H2C command to change channel, ++ * not only modify rf register, but also other setting need to be done. ++ */ ++void SetChannel(PADAPTER pAdapter) ++{ ++ Hal_SetChannel(pAdapter); ++ ++} ++ ++/* ++ * Notice ++ * Switch bandwitdth may change center frequency(channel) ++ */ ++void SetBandwidth(PADAPTER pAdapter) ++{ ++ Hal_SetBandwidth(pAdapter); ++ ++} ++ ++static void SetCCKTxPower(PADAPTER pAdapter, u8 *TxPower) ++{ ++ Hal_SetCCKTxPower(pAdapter,TxPower); ++} ++ ++static void SetOFDMTxPower(PADAPTER pAdapter, u8 *TxPower) ++{ ++ Hal_SetOFDMTxPower(pAdapter,TxPower); ++ } ++ ++ ++void SetAntenna(PADAPTER pAdapter) ++ { ++ Hal_SetAntenna(pAdapter); ++} ++ ++void SetAntennaPathPower(PADAPTER pAdapter) ++{ ++ Hal_SetAntennaPathPower(pAdapter); ++} ++ ++void SetTxPower(PADAPTER pAdapter) ++{ ++ Hal_SetTxPower(pAdapter); ++} ++ ++void SetTxAGCOffset(PADAPTER pAdapter, u32 ulTxAGCOffset) ++{ ++ u32 TxAGCOffset_B, TxAGCOffset_C, TxAGCOffset_D,tmpAGC; ++ ++ TxAGCOffset_B = (ulTxAGCOffset&0x000000ff); ++ TxAGCOffset_C = ((ulTxAGCOffset&0x0000ff00)>>8); ++ TxAGCOffset_D = ((ulTxAGCOffset&0x00ff0000)>>16); ++ ++ tmpAGC = (TxAGCOffset_D<<8 | TxAGCOffset_C<<4 | TxAGCOffset_B); ++ write_bbreg(pAdapter, rFPGA0_TxGainStage, ++ (bXBTxAGC|bXCTxAGC|bXDTxAGC), tmpAGC); ++} ++ ++void SetDataRate(PADAPTER pAdapter) ++{ ++ Hal_SetDataRate(pAdapter); ++} ++ ++#if !defined (CONFIG_RTL8192C) && !defined (CONFIG_RTL8192D) ++/*------------------------------Define structure----------------------------*/ ++typedef struct _R_ANTENNA_SELECT_OFDM { ++ u32 r_tx_antenna:4; ++ u32 r_ant_l:4; ++ u32 r_ant_non_ht:4; ++ u32 r_ant_ht1:4; ++ u32 r_ant_ht2:4; ++ u32 r_ant_ht_s1:4; ++ u32 r_ant_non_ht_s1:4; ++ u32 OFDM_TXSC:2; ++ u32 Reserved:2; ++}R_ANTENNA_SELECT_OFDM; ++ ++typedef struct _R_ANTENNA_SELECT_CCK { ++ u8 r_cckrx_enable_2:2; ++ u8 r_cckrx_enable:2; ++ u8 r_ccktx_enable:4; ++}R_ANTENNA_SELECT_CCK; ++#endif ++ ++s32 SetThermalMeter(PADAPTER pAdapter, u8 target_ther) ++{ ++ return Hal_SetThermalMeter( pAdapter, target_ther); ++} ++ ++static void TriggerRFThermalMeter(PADAPTER pAdapter) ++{ ++ Hal_TriggerRFThermalMeter(pAdapter); ++} ++ ++static u8 ReadRFThermalMeter(PADAPTER pAdapter) ++{ ++ return Hal_ReadRFThermalMeter(pAdapter); ++} ++ ++void GetThermalMeter(PADAPTER pAdapter, u8 *value) ++{ ++ Hal_GetThermalMeter(pAdapter,value); ++} ++ ++void SetSingleCarrierTx(PADAPTER pAdapter, u8 bStart) ++{ ++ Hal_SetSingleCarrierTx(pAdapter,bStart); ++} ++ ++void SetSingleToneTx(PADAPTER pAdapter, u8 bStart) ++{ ++ Hal_SetSingleToneTx(pAdapter,bStart); ++} ++ ++void SetCarrierSuppressionTx(PADAPTER pAdapter, u8 bStart) ++{ ++ Hal_SetCarrierSuppressionTx(pAdapter, bStart); ++} ++ ++void SetCCKContinuousTx(PADAPTER pAdapter, u8 bStart) ++{ ++ Hal_SetCCKContinuousTx(pAdapter,bStart); ++ } ++ ++void SetOFDMContinuousTx(PADAPTER pAdapter, u8 bStart) ++{ ++ Hal_SetOFDMContinuousTx( pAdapter, bStart); ++}/* mpt_StartOfdmContTx */ ++ ++void SetContinuousTx(PADAPTER pAdapter, u8 bStart) ++{ ++ Hal_SetContinuousTx(pAdapter,bStart); ++} ++ ++//------------------------------------------------------------------------------ ++void dump_mpframe(_adapter *padapter, struct xmit_frame *pmpframe) ++{ ++ padapter->HalFunc.mgnt_xmit(padapter, pmpframe); ++} ++ ++struct xmit_frame *alloc_mp_xmitframe(struct xmit_priv *pxmitpriv) ++{ ++ struct xmit_frame *pmpframe; ++ struct xmit_buf *pxmitbuf; ++ ++ if ((pmpframe = rtw_alloc_xmitframe(pxmitpriv)) == NULL) ++ { ++ return NULL; ++ } ++ ++ if ((pxmitbuf = rtw_alloc_xmitbuf(pxmitpriv)) == NULL) ++ { ++ rtw_free_xmitframe_ex(pxmitpriv, pmpframe); ++ return NULL; ++ } ++ ++ pmpframe->frame_tag = MP_FRAMETAG; ++ ++ pmpframe->pxmitbuf = pxmitbuf; ++ ++ pmpframe->buf_addr = pxmitbuf->pbuf; ++ ++ pxmitbuf->priv_data = pmpframe; ++ ++ return pmpframe; ++ ++} ++ ++thread_return mp_xmit_packet_thread(thread_context context) ++{ ++ struct xmit_frame *pxmitframe; ++ struct mp_tx *pmptx; ++ struct mp_priv *pmp_priv; ++ struct xmit_priv *pxmitpriv; ++ PADAPTER padapter; ++ ++ pmp_priv = (struct mp_priv *)context; ++ pmptx = &pmp_priv->tx; ++ padapter = pmp_priv->papdater; ++ pxmitpriv = &(padapter->xmitpriv); ++ ++ thread_enter(padapter); ++ ++ //DBG_8192C("%s:pkTx Start\n", __func__); ++ while (1) { ++ pxmitframe = alloc_mp_xmitframe(pxmitpriv); ++ if (pxmitframe == NULL) { ++ if (pmptx->stop || ++ padapter->bSurpriseRemoved || ++ padapter->bDriverStopped) { ++ goto exit; ++ } ++ else { ++ rtw_msleep_os(1); ++ continue; ++ } ++ } ++ ++ _rtw_memcpy((u8 *)(pxmitframe->buf_addr+TXDESC_OFFSET), pmptx->buf, pmptx->write_size); ++ _rtw_memcpy(&(pxmitframe->attrib), &(pmptx->attrib), sizeof(struct pkt_attrib)); ++ ++ dump_mpframe(padapter, pxmitframe); ++ ++ pmptx->sended++; ++ pmp_priv->tx_pktcount++; ++ ++ if (pmptx->stop || ++ padapter->bSurpriseRemoved || ++ padapter->bDriverStopped) ++ goto exit; ++ if ((pmptx->count != 0) && ++ (pmptx->count == pmptx->sended)) ++ goto exit; ++ ++ flush_signals_thread(); ++ } ++ ++exit: ++ //DBG_8192C("%s:pkTx Exit\n", __func__); ++ rtw_mfree(pmptx->pallocated_buf, pmptx->buf_size); ++ pmptx->pallocated_buf = NULL; ++ pmptx->stop = 1; ++ ++ thread_exit(); ++} ++ ++void fill_txdesc_for_mp(PADAPTER padapter, struct tx_desc *ptxdesc) ++{ ++ struct mp_priv *pmp_priv = &padapter->mppriv; ++ _rtw_memcpy(ptxdesc, &(pmp_priv->tx.desc), TXDESC_SIZE); ++} ++ ++void SetPacketTx(PADAPTER padapter) ++{ ++ u8 *ptr, *pkt_start, *pkt_end; ++ u32 pkt_size; ++ struct tx_desc *desc; ++ struct rtw_ieee80211_hdr *hdr; ++ u8 payload; ++ s32 bmcast; ++ struct pkt_attrib *pattrib; ++ struct mp_priv *pmp_priv; ++ ++ ++ pmp_priv = &padapter->mppriv; ++ if (pmp_priv->tx.stop) return; ++ pmp_priv->tx.sended = 0; ++ pmp_priv->tx.stop = 0; ++ pmp_priv->tx_pktcount = 0; ++ ++ //3 1. update_attrib() ++ pattrib = &pmp_priv->tx.attrib; ++ _rtw_memcpy(pattrib->src, padapter->eeprompriv.mac_addr, ETH_ALEN); ++ _rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN); ++ _rtw_memcpy(pattrib->ra, pattrib->dst, ETH_ALEN); ++ bmcast = IS_MCAST(pattrib->ra); ++ if (bmcast) { ++ pattrib->mac_id = 1; ++ pattrib->psta = rtw_get_bcmc_stainfo(padapter); ++ } else { ++ pattrib->mac_id = 0; ++ pattrib->psta = rtw_get_stainfo(&padapter->stapriv, get_bssid(&padapter->mlmepriv)); ++ } ++ ++ pattrib->last_txcmdsz = pattrib->hdrlen + pattrib->pktlen; ++ ++ //3 2. allocate xmit buffer ++ pkt_size = pattrib->last_txcmdsz; ++ ++ if (pmp_priv->tx.pallocated_buf) ++ rtw_mfree(pmp_priv->tx.pallocated_buf, pmp_priv->tx.buf_size); ++ pmp_priv->tx.write_size = pkt_size; ++ pmp_priv->tx.buf_size = pkt_size + XMITBUF_ALIGN_SZ; ++ pmp_priv->tx.pallocated_buf = rtw_zmalloc(pmp_priv->tx.buf_size); ++ if (pmp_priv->tx.pallocated_buf == NULL) { ++ DBG_8192C("%s: malloc(%d) fail!!\n", __func__, pmp_priv->tx.buf_size); ++ return; ++ } ++ pmp_priv->tx.buf = (u8 *)N_BYTE_ALIGMENT((SIZE_PTR)(pmp_priv->tx.pallocated_buf), XMITBUF_ALIGN_SZ); ++ ptr = pmp_priv->tx.buf; ++ ++ desc = &(pmp_priv->tx.desc); ++ _rtw_memset(desc, 0, TXDESC_SIZE); ++ pkt_start = ptr; ++ pkt_end = pkt_start + pkt_size; ++ ++ //3 3. init TX descriptor ++ // offset 0 ++ //desc->txdw0 |= cpu_to_le32(pkt_size & 0x0000FFFF); // packet size ++ //desc->txdw0 |= cpu_to_le32(OWN | FSG | LSG); ++ //desc->txdw0 |= cpu_to_le32(((TXDESC_SIZE + OFFSET_SZ) << OFFSET_SHT) & 0x00FF0000); //32 bytes for TX Desc ++ //if (bmcast) desc->txdw0 |= cpu_to_le32(BMC); // broadcast packet ++ ++ // offset 4 ++ desc->txdw1 |= cpu_to_le32(BK); // don't aggregate(AMPDU) ++ desc->txdw1 |= cpu_to_le32((pattrib->mac_id) & 0x1F); //CAM_ID(MAC_ID) ++ desc->txdw1 |= cpu_to_le32((pattrib->qsel << QSEL_SHT) & 0x00001F00); // Queue Select, TID ++ desc->txdw1 |= cpu_to_le32((pattrib->raid << Rate_ID_SHT) & 0x000F0000); // Rate Adaptive ID ++ ++ // offset 8 ++ // offset 12 ++ //desc->txdw3 |= cpu_to_le32((pattrib->seqnum << SEQ_SHT) & 0xffff0000); ++ ++ // offset 16 ++ //desc->txdw4 |= cpu_to_le32(QoS); ++ desc->txdw4 |= cpu_to_le32(HW_SEQ_EN); ++ desc->txdw4 |= cpu_to_le32(USERATE); ++ desc->txdw4 |= cpu_to_le32(DISDATAFB); ++ ++ if( pmp_priv->preamble ){ ++ if (pmp_priv->rateidx <= MPT_RATE_54M) ++ desc->txdw4 |= cpu_to_le32(DATA_SHORT); // CCK Short Preamble ++ } ++ if (pmp_priv->bandwidth == HT_CHANNEL_WIDTH_40) ++ desc->txdw4 |= cpu_to_le32(DATA_BW); ++ ++ // offset 20 ++ desc->txdw5 |= cpu_to_le32(pmp_priv->rateidx & 0x0000001F); ++ ++ if( pmp_priv->preamble ){ ++ if (pmp_priv->rateidx > MPT_RATE_54M) ++ desc->txdw5 |= cpu_to_le32(SGI); // MCS Short Guard Interval ++ } ++ desc->txdw5 |= cpu_to_le32(0x0001FF00); // DATA/RTS Rate Fallback Limit ++ ++ //3 4. make wlan header, make_wlanhdr() ++ hdr = (struct rtw_ieee80211_hdr *)pkt_start; ++ SetFrameSubType(&hdr->frame_ctl, pattrib->subtype); ++ _rtw_memcpy(hdr->addr1, pattrib->dst, ETH_ALEN); // DA ++ _rtw_memcpy(hdr->addr2, pattrib->src, ETH_ALEN); // SA ++ _rtw_memcpy(hdr->addr3, get_bssid(&padapter->mlmepriv), ETH_ALEN); // RA, BSSID ++ ++ //3 5. make payload ++ ptr = pkt_start + pattrib->hdrlen; ++ ++ switch (pmp_priv->tx.payload) { ++ case 0: ++ payload = 0x00; ++ break; ++ case 1: ++ payload = 0x5a; ++ break; ++ case 2: ++ payload = 0xa5; ++ break; ++ case 3: ++ payload = 0xff; ++ break; ++ default: ++ payload = 0x00; ++ break; ++ } ++ ++ _rtw_memset(ptr, payload, pkt_end - ptr); ++ ++ //3 6. start thread ++ pmp_priv->tx.PktTxThread = kernel_thread(mp_xmit_packet_thread, pmp_priv, CLONE_FS|CLONE_FILES); ++ if(pmp_priv->tx.PktTxThread < 0) ++ DBG_871X("Create PktTx Thread Fail !!!!!\n"); ++ ++} ++ ++void SetPacketRx(PADAPTER pAdapter, u8 bStartRx) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); ++ ++ if(bStartRx) ++ { ++ // Accept CRC error and destination address ++ pHalData->ReceiveConfig |= (RCR_ACRC32|RCR_AAP); ++ rtw_write32(pAdapter, REG_RCR, pHalData->ReceiveConfig); ++ } ++ else ++ { ++ rtw_write32(pAdapter, REG_RCR, 0); ++ } ++} ++ ++void ResetPhyRxPktCount(PADAPTER pAdapter) ++{ ++ u32 i, phyrx_set = 0; ++ ++ for (i = 0; i <= 0xF; i++) { ++ phyrx_set = 0; ++ phyrx_set |= _RXERR_RPT_SEL(i); //select ++ phyrx_set |= RXERR_RPT_RST; // set counter to zero ++ rtw_write32(pAdapter, REG_RXERR_RPT, phyrx_set); ++ } ++} ++ ++static u32 GetPhyRxPktCounts(PADAPTER pAdapter, u32 selbit) ++{ ++ //selection ++ u32 phyrx_set = 0, count = 0; ++ ++ phyrx_set = _RXERR_RPT_SEL(selbit & 0xF); ++ rtw_write32(pAdapter, REG_RXERR_RPT, phyrx_set); ++ ++ //Read packet count ++ count = rtw_read32(pAdapter, REG_RXERR_RPT) & RXERR_COUNTER_MASK; ++ ++ return count; ++} ++ ++u32 GetPhyRxPktReceived(PADAPTER pAdapter) ++{ ++ u32 OFDM_cnt = 0, CCK_cnt = 0, HT_cnt = 0; ++ ++ OFDM_cnt = GetPhyRxPktCounts(pAdapter, RXERR_TYPE_OFDM_MPDU_OK); ++ CCK_cnt = GetPhyRxPktCounts(pAdapter, RXERR_TYPE_CCK_MPDU_OK); ++ HT_cnt = GetPhyRxPktCounts(pAdapter, RXERR_TYPE_HT_MPDU_OK); ++ ++ return OFDM_cnt + CCK_cnt + HT_cnt; ++} ++ ++u32 GetPhyRxPktCRC32Error(PADAPTER pAdapter) ++{ ++ u32 OFDM_cnt = 0, CCK_cnt = 0, HT_cnt = 0; ++ ++ OFDM_cnt = GetPhyRxPktCounts(pAdapter, RXERR_TYPE_OFDM_MPDU_FAIL); ++ CCK_cnt = GetPhyRxPktCounts(pAdapter, RXERR_TYPE_CCK_MPDU_FAIL); ++ HT_cnt = GetPhyRxPktCounts(pAdapter, RXERR_TYPE_HT_MPDU_FAIL); ++ ++ return OFDM_cnt + CCK_cnt + HT_cnt; ++} ++ ++//reg 0x808[9:0]: FFT data x ++//reg 0x808[22]: 0 --> 1 to get 1 FFT data y ++//reg 0x8B4[15:0]: FFT data y report ++static u32 GetPSDData(PADAPTER pAdapter, u32 point) ++{ ++ int psd_val; ++ ++ ++ psd_val = rtw_read32(pAdapter, 0x808); ++ psd_val &= 0xFFBFFC00; ++ psd_val |= point; ++ ++ rtw_write32(pAdapter, 0x808, psd_val); ++ rtw_mdelay_os(1); ++ psd_val |= 0x00400000; ++ ++ rtw_write32(pAdapter, 0x808, psd_val); ++ rtw_mdelay_os(1); ++ psd_val = rtw_read32(pAdapter, 0x8B4); ++ ++ psd_val &= 0x0000FFFF; ++ ++ return psd_val; ++} ++ ++/* ++ * pts start_point_min stop_point_max ++ * 128 64 64 + 128 = 192 ++ * 256 128 128 + 256 = 384 ++ * 512 256 256 + 512 = 768 ++ * 1024 512 512 + 1024 = 1536 ++ * ++ */ ++u32 mp_query_psd(PADAPTER pAdapter, u8 *data) ++{ ++ u8 *val; ++ u32 i, psd_pts=0, psd_start=0, psd_stop=0; ++ u32 psd_data=0; ++ ++ ++ if (!netif_running(pAdapter->pnetdev)) { ++ RT_TRACE(_module_mp_, _drv_warning_, ("mp_query_psd: Fail! interface not opened!\n")); ++ return 0; ++ } ++ ++ if (check_fwstate(&pAdapter->mlmepriv, WIFI_MP_STATE) == _FALSE) { ++ RT_TRACE(_module_mp_, _drv_warning_, ("mp_query_psd: Fail! not in MP mode!\n")); ++ return 0; ++ } ++ ++ if (strlen(data) == 0) { //default value ++ psd_pts = 128; ++ psd_start = 64; ++ psd_stop = 128; ++ } else { ++ sscanf(data, "pts=%d,start=%d,stop=%d", &psd_pts, &psd_start, &psd_stop); ++ } ++ ++ _rtw_memset(data, '\0', sizeof(data)); ++ ++ i = psd_start; ++ while (i < psd_stop) ++ { ++ if (i >= psd_pts) { ++ psd_data = GetPSDData(pAdapter, i-psd_pts); ++ } else { ++ psd_data = GetPSDData(pAdapter, i); ++ } ++ sprintf(data, "%s%x ", data, psd_data); ++ i++; ++ } ++ ++ #ifdef CONFIG_LONG_DELAY_ISSUE ++ rtw_msleep_os(100); ++ #else ++ rtw_mdelay_os(100); ++ #endif ++ ++ return strlen(data)+1; ++} ++ ++ ++u32 rtw_atoi(u8* s) ++{ ++ ++ int num=0,flag=0; ++ int i; ++ for(i=0;i<=strlen(s);i++) ++ { ++ if(s[i] >= '0' && s[i] <= '9') ++ num = num * 10 + s[i] -'0'; ++ else if(s[0] == '-' && i==0) ++ flag =1; ++ else ++ break; ++ } ++ ++ if(flag == 1) ++ num = num * -1; ++ ++ return(num); ++ ++} ++ ++#endif ++ +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/core/rtw_mp_ioctl.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/core/rtw_mp_ioctl.c 2013-07-26 19:36:05.000000000 +0000 +@@ -0,0 +1,2841 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#define _RTW_MP_IOCTL_C_ ++ ++#include ++#include ++#include ++#include ++ ++//#include ++#include ++ ++ ++//**************** oid_rtl_seg_81_85 section start **************** ++NDIS_STATUS oid_rt_wireless_mode_hdl(struct oid_par_priv *poid_par_priv) ++{ ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++_func_enter_; ++ ++ if (poid_par_priv->information_buf_len < sizeof(u8)) ++ return NDIS_STATUS_INVALID_LENGTH; ++ ++ if (poid_par_priv->type_of_oid == SET_OID) { ++ Adapter->registrypriv.wireless_mode = *(u8*)poid_par_priv->information_buf; ++ } else if (poid_par_priv->type_of_oid == QUERY_OID) { ++ *(u8*)poid_par_priv->information_buf = Adapter->registrypriv.wireless_mode; ++ *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; ++ RT_TRACE(_module_mp_, _drv_info_, ("-query Wireless Mode=%d\n", Adapter->registrypriv.wireless_mode)); ++ } else { ++ status = NDIS_STATUS_NOT_ACCEPTED; ++ } ++ ++_func_exit_; ++ ++ return status; ++} ++//**************** oid_rtl_seg_81_87_80 section start **************** ++NDIS_STATUS oid_rt_pro_write_bb_reg_hdl(struct oid_par_priv *poid_par_priv) ++{ ++ _irqL oldirql; ++ struct bb_reg_param *pbbreg; ++ u16 offset; ++ u32 value; ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++_func_enter_; ++ ++ RT_TRACE(_module_mp_, _drv_notice_, ("+oid_rt_pro_write_bb_reg_hdl\n")); ++ ++ if (poid_par_priv->type_of_oid != SET_OID) ++ return NDIS_STATUS_NOT_ACCEPTED; ++ ++ if (poid_par_priv->information_buf_len < sizeof(struct bb_reg_param)) ++ return NDIS_STATUS_INVALID_LENGTH; ++ ++ pbbreg = (struct bb_reg_param *)(poid_par_priv->information_buf); ++ ++ offset = (u16)(pbbreg->offset) & 0xFFF; //0ffset :0x800~0xfff ++ if (offset < BB_REG_BASE_ADDR) offset |= BB_REG_BASE_ADDR; ++ ++ value = pbbreg->value; ++ ++ RT_TRACE(_module_mp_, _drv_notice_, ++ ("oid_rt_pro_write_bb_reg_hdl: offset=0x%03X value=0x%08X\n", ++ offset, value)); ++ ++ _irqlevel_changed_(&oldirql, LOWER); ++ write_bbreg(Adapter, offset, 0xFFFFFFFF, value); ++ _irqlevel_changed_(&oldirql, RAISE); ++ ++_func_exit_; ++ ++ return status; ++} ++//------------------------------------------------------------------------------ ++NDIS_STATUS oid_rt_pro_read_bb_reg_hdl(struct oid_par_priv *poid_par_priv) ++{ ++ _irqL oldirql; ++ struct bb_reg_param *pbbreg; ++ u16 offset; ++ u32 value; ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++_func_enter_; ++ ++ RT_TRACE(_module_mp_, _drv_notice_, ("+oid_rt_pro_read_bb_reg_hdl\n")); ++ ++ if (poid_par_priv->type_of_oid != QUERY_OID) ++ return NDIS_STATUS_NOT_ACCEPTED; ++ ++ if (poid_par_priv->information_buf_len < sizeof(struct bb_reg_param)) ++ return NDIS_STATUS_INVALID_LENGTH; ++ ++ pbbreg = (struct bb_reg_param *)(poid_par_priv->information_buf); ++ ++ offset = (u16)(pbbreg->offset) & 0xFFF; //0ffset :0x800~0xfff ++ if (offset < BB_REG_BASE_ADDR) offset |= BB_REG_BASE_ADDR; ++ ++ _irqlevel_changed_(&oldirql, LOWER); ++ value = read_bbreg(Adapter, offset, 0xFFFFFFFF); ++ _irqlevel_changed_(&oldirql, RAISE); ++ ++ pbbreg->value = value; ++ *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; ++ ++ RT_TRACE(_module_mp_, _drv_notice_, ++ ("-oid_rt_pro_read_bb_reg_hdl: offset=0x%03X value:0x%08X\n", ++ offset, value)); ++_func_exit_; ++ ++ return status; ++} ++//------------------------------------------------------------------------------ ++NDIS_STATUS oid_rt_pro_write_rf_reg_hdl(struct oid_par_priv *poid_par_priv) ++{ ++ _irqL oldirql; ++ struct rf_reg_param *pbbreg; ++ u8 path; ++ u8 offset; ++ u32 value; ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++_func_enter_; ++ ++ RT_TRACE(_module_mp_, _drv_notice_, ("+oid_rt_pro_write_rf_reg_hdl\n")); ++ ++ if (poid_par_priv->type_of_oid != SET_OID) ++ return NDIS_STATUS_NOT_ACCEPTED; ++ ++ if (poid_par_priv->information_buf_len < sizeof(struct rf_reg_param)) ++ return NDIS_STATUS_INVALID_LENGTH; ++ ++ pbbreg = (struct rf_reg_param *)(poid_par_priv->information_buf); ++ ++ if (pbbreg->path >= MAX_RF_PATH_NUMS) ++ return NDIS_STATUS_NOT_ACCEPTED; ++ if (pbbreg->offset > 0xFF) ++ return NDIS_STATUS_NOT_ACCEPTED; ++ if (pbbreg->value > 0xFFFFF) ++ return NDIS_STATUS_NOT_ACCEPTED; ++ ++ path = (u8)pbbreg->path; ++ offset = (u8)pbbreg->offset; ++ value = pbbreg->value; ++ ++ RT_TRACE(_module_mp_, _drv_notice_, ++ ("oid_rt_pro_write_rf_reg_hdl: path=%d offset=0x%02X value=0x%05X\n", ++ path, offset, value)); ++ ++ _irqlevel_changed_(&oldirql, LOWER); ++ write_rfreg(Adapter, path, offset, value); ++ _irqlevel_changed_(&oldirql, RAISE); ++ ++_func_exit_; ++ ++ return status; ++} ++//------------------------------------------------------------------------------ ++NDIS_STATUS oid_rt_pro_read_rf_reg_hdl(struct oid_par_priv *poid_par_priv) ++{ ++ _irqL oldirql; ++ struct rf_reg_param *pbbreg; ++ u8 path; ++ u8 offset; ++ u32 value; ++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ ++_func_enter_; ++ ++ RT_TRACE(_module_mp_, _drv_notice_, ("+oid_rt_pro_read_rf_reg_hdl\n")); ++ ++ if (poid_par_priv->type_of_oid != QUERY_OID) ++ return NDIS_STATUS_NOT_ACCEPTED; ++ ++ if (poid_par_priv->information_buf_len < sizeof(struct rf_reg_param)) ++ return NDIS_STATUS_INVALID_LENGTH; ++ ++ pbbreg = (struct rf_reg_param *)(poid_par_priv->information_buf); ++ ++ if (pbbreg->path >= MAX_RF_PATH_NUMS) ++ return NDIS_STATUS_NOT_ACCEPTED; ++ if (pbbreg->offset > 0xFF) ++ return NDIS_STATUS_NOT_ACCEPTED; ++ ++ path = (u8)pbbreg->path; ++ offset = (u8)pbbreg->offset; ++ ++ _irqlevel_changed_(&oldirql, LOWER); ++ value = read_rfreg(Adapter, path, offset); ++ _irqlevel_changed_(&oldirql, RAISE); ++ ++ pbbreg->value = value; ++ ++ *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; ++ ++ RT_TRACE(_module_mp_, _drv_notice_, ++ ("-oid_rt_pro_read_rf_reg_hdl: path=%d offset=0x%02X value=0x%05X\n", ++ path, offset, value)); ++ ++_func_exit_; ++ ++ return status; ++} ++//**************** oid_rtl_seg_81_87_00 section end**************** ++//------------------------------------------------------------------------------ ++ ++//**************** oid_rtl_seg_81_80_00 section start **************** ++//------------------------------------------------------------------------------ ++NDIS_STATUS oid_rt_pro_set_data_rate_hdl(struct oid_par_priv *poid_par_priv) ++{ ++ _irqL oldirql; ++ u32 ratevalue;//4 ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++_func_enter_; ++ ++ RT_TRACE(_module_mp_, _drv_notice_, ++ ("+oid_rt_pro_set_data_rate_hdl\n")); ++ ++ if (poid_par_priv->type_of_oid != SET_OID) ++ return NDIS_STATUS_NOT_ACCEPTED; ++ ++ if (poid_par_priv->information_buf_len != sizeof(u32)) ++ return NDIS_STATUS_INVALID_LENGTH; ++ ++ ratevalue = *((u32*)poid_par_priv->information_buf);//4 ++ RT_TRACE(_module_mp_, _drv_notice_, ++ ("oid_rt_pro_set_data_rate_hdl: data rate idx=%d\n", ratevalue)); ++ if (ratevalue >= MPT_RATE_LAST) ++ return NDIS_STATUS_INVALID_DATA; ++ ++ Adapter->mppriv.rateidx = ratevalue; ++ ++ _irqlevel_changed_(&oldirql, LOWER); ++ SetDataRate(Adapter); ++ _irqlevel_changed_(&oldirql, RAISE); ++ ++_func_exit_; ++ ++ return status; ++} ++//------------------------------------------------------------------------------ ++NDIS_STATUS oid_rt_pro_start_test_hdl(struct oid_par_priv *poid_par_priv) ++{ ++ _irqL oldirql; ++ u32 mode; ++ u8 val8; ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++_func_enter_; ++ ++ RT_TRACE(_module_mp_, _drv_notice_, ("+oid_rt_pro_start_test_hdl\n")); ++ ++ if (Adapter->registrypriv.mp_mode == 0) ++ return NDIS_STATUS_NOT_ACCEPTED; ++ ++ if (poid_par_priv->type_of_oid != SET_OID) ++ return NDIS_STATUS_NOT_ACCEPTED; ++ ++ _irqlevel_changed_(&oldirql, LOWER); ++ ++ //IQCalibrateBcut(Adapter); ++ ++ mode = *((u32*)poid_par_priv->information_buf); ++ Adapter->mppriv.mode = mode;// 1 for loopback ++ ++ if (mp_start_test(Adapter) == _FAIL) { ++ status = NDIS_STATUS_NOT_ACCEPTED; ++ goto exit; ++ } ++ ++exit: ++ _irqlevel_changed_(&oldirql, RAISE); ++ ++ RT_TRACE(_module_mp_, _drv_notice_, ("-oid_rt_pro_start_test_hdl: mp_mode=%d\n", Adapter->mppriv.mode)); ++ ++_func_exit_; ++ ++ return status; ++} ++//------------------------------------------------------------------------------ ++NDIS_STATUS oid_rt_pro_stop_test_hdl(struct oid_par_priv *poid_par_priv) ++{ ++ _irqL oldirql; ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++_func_enter_; ++ ++ RT_TRACE(_module_mp_, _drv_notice_, ("+Set OID_RT_PRO_STOP_TEST\n")); ++ ++ if (poid_par_priv->type_of_oid != SET_OID) ++ return NDIS_STATUS_NOT_ACCEPTED; ++ ++ _irqlevel_changed_(&oldirql, LOWER); ++ mp_stop_test(Adapter); ++ _irqlevel_changed_(&oldirql, RAISE); ++ ++ RT_TRACE(_module_mp_, _drv_notice_, ("-Set OID_RT_PRO_STOP_TEST\n")); ++ ++_func_exit_; ++ ++ return status; ++} ++//------------------------------------------------------------------------------ ++NDIS_STATUS oid_rt_pro_set_channel_direct_call_hdl(struct oid_par_priv *poid_par_priv) ++{ ++ _irqL oldirql; ++ u32 Channel; ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++_func_enter_; ++ ++ RT_TRACE(_module_mp_, _drv_notice_, ("+oid_rt_pro_set_channel_direct_call_hdl\n")); ++ ++ if (poid_par_priv->information_buf_len != sizeof(u32)) ++ return NDIS_STATUS_INVALID_LENGTH; ++ ++ if (poid_par_priv->type_of_oid == QUERY_OID) { ++ *((u32*)poid_par_priv->information_buf) = Adapter->mppriv.channel; ++ return NDIS_STATUS_SUCCESS; ++ } ++ ++ if (poid_par_priv->type_of_oid != SET_OID) ++ return NDIS_STATUS_NOT_ACCEPTED; ++ ++ Channel = *((u32*)poid_par_priv->information_buf); ++ RT_TRACE(_module_mp_, _drv_notice_, ("oid_rt_pro_set_channel_direct_call_hdl: Channel=%d\n", Channel)); ++ if (Channel > 14) ++ return NDIS_STATUS_NOT_ACCEPTED; ++ Adapter->mppriv.channel = Channel; ++ ++ _irqlevel_changed_(&oldirql, LOWER); ++ SetChannel(Adapter); ++ _irqlevel_changed_(&oldirql, RAISE); ++ ++_func_exit_; ++ ++ return status; ++} ++//------------------------------------------------------------------------------ ++NDIS_STATUS oid_rt_set_bandwidth_hdl(struct oid_par_priv *poid_par_priv) ++{ ++ _irqL oldirql; ++ u16 bandwidth, channel_offset; ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++_func_enter_; ++ ++ RT_TRACE(_module_mp_, _drv_info_, ++ ("+oid_rt_set_bandwidth_hdl\n")); ++ ++ if (poid_par_priv->type_of_oid != SET_OID) ++ return NDIS_STATUS_NOT_ACCEPTED; ++ ++ if (poid_par_priv->information_buf_len < sizeof(u32)) ++ return NDIS_STATUS_INVALID_LENGTH; ++ ++ bandwidth = *((u32*)poid_par_priv->information_buf);//4 ++ if (bandwidth != HT_CHANNEL_WIDTH_40) ++ bandwidth = HT_CHANNEL_WIDTH_20; ++ Adapter->mppriv.bandwidth = (u8)bandwidth; ++ ++ _irqlevel_changed_(&oldirql, LOWER); ++ SetBandwidth(Adapter); ++ _irqlevel_changed_(&oldirql, RAISE); ++ ++ RT_TRACE(_module_mp_, _drv_notice_, ++ ("-oid_rt_set_bandwidth_hdl: bandwidth=%d channel_offset=%d\n", ++ bandwidth, channel_offset)); ++ ++_func_exit_; ++ ++ return status; ++} ++//------------------------------------------------------------------------------ ++NDIS_STATUS oid_rt_pro_set_antenna_bb_hdl(struct oid_par_priv *poid_par_priv) ++{ ++ _irqL oldirql; ++ u32 antenna; ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++_func_enter_; ++ ++ RT_TRACE(_module_mp_, _drv_notice_, ("+oid_rt_pro_set_antenna_bb_hdl\n")); ++ ++ if (poid_par_priv->information_buf_len != sizeof(u32)) ++ return NDIS_STATUS_INVALID_LENGTH; ++ ++ if (poid_par_priv->type_of_oid == SET_OID) ++ { ++ antenna = *(u32*)poid_par_priv->information_buf; ++ ++ Adapter->mppriv.antenna_tx = (u16)((antenna & 0xFFFF0000) >> 16); ++ Adapter->mppriv.antenna_rx = (u16)(antenna & 0x0000FFFF); ++ RT_TRACE(_module_mp_, _drv_notice_, ++ ("oid_rt_pro_set_antenna_bb_hdl: tx_ant=0x%04x rx_ant=0x%04x\n", ++ Adapter->mppriv.antenna_tx, Adapter->mppriv.antenna_rx)); ++ ++ _irqlevel_changed_(&oldirql, LOWER); ++ SetAntenna(Adapter); ++ _irqlevel_changed_(&oldirql, RAISE); ++ } else { ++ antenna = (Adapter->mppriv.antenna_tx << 16)|Adapter->mppriv.antenna_rx; ++ *(u32*)poid_par_priv->information_buf = antenna; ++ } ++ ++_func_exit_; ++ ++ return status; ++} ++ ++NDIS_STATUS oid_rt_pro_set_tx_power_control_hdl(struct oid_par_priv *poid_par_priv) ++{ ++ _irqL oldirql; ++ u32 tx_pwr_idx; ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++_func_enter_; ++ ++ RT_TRACE(_module_mp_, _drv_info_, ("+oid_rt_pro_set_tx_power_control_hdl\n")); ++ ++ if (poid_par_priv->type_of_oid != SET_OID) ++ return NDIS_STATUS_NOT_ACCEPTED; ++ ++ if (poid_par_priv->information_buf_len != sizeof(u32)) ++ return NDIS_STATUS_INVALID_LENGTH; ++ ++ tx_pwr_idx = *((u32*)poid_par_priv->information_buf); ++ if (tx_pwr_idx > MAX_TX_PWR_INDEX_N_MODE) ++ return NDIS_STATUS_NOT_ACCEPTED; ++ ++ Adapter->mppriv.txpoweridx = (u8)tx_pwr_idx; ++ ++ RT_TRACE(_module_mp_, _drv_notice_, ++ ("oid_rt_pro_set_tx_power_control_hdl: idx=0x%2x\n", ++ Adapter->mppriv.txpoweridx)); ++ ++ _irqlevel_changed_(&oldirql, LOWER); ++ SetTxPower(Adapter); ++ _irqlevel_changed_(&oldirql, RAISE); ++ ++_func_exit_; ++ ++ return status; ++} ++ ++//------------------------------------------------------------------------------ ++//**************** oid_rtl_seg_81_80_20 section start **************** ++//------------------------------------------------------------------------------ ++NDIS_STATUS oid_rt_pro_query_tx_packet_sent_hdl(struct oid_par_priv *poid_par_priv) ++{ ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++_func_enter_; ++ ++ if (poid_par_priv->type_of_oid !=QUERY_OID) { ++ status = NDIS_STATUS_NOT_ACCEPTED; ++ return status; ++ } ++ ++ if (poid_par_priv->information_buf_len == sizeof(ULONG)) { ++ *(ULONG*)poid_par_priv->information_buf = Adapter->mppriv.tx_pktcount; ++ *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; ++ } else { ++ status = NDIS_STATUS_INVALID_LENGTH; ++ } ++ ++_func_exit_; ++ ++ return status; ++} ++//------------------------------------------------------------------------------ ++NDIS_STATUS oid_rt_pro_query_rx_packet_received_hdl(struct oid_par_priv *poid_par_priv) ++{ ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++_func_enter_; ++ ++ if (poid_par_priv->type_of_oid != QUERY_OID) { ++ status = NDIS_STATUS_NOT_ACCEPTED; ++ return status; ++ } ++ RT_TRACE(_module_mp_, _drv_alert_, ("===> oid_rt_pro_query_rx_packet_received_hdl.\n")); ++ if (poid_par_priv->information_buf_len == sizeof(ULONG)) { ++ *(ULONG*)poid_par_priv->information_buf = Adapter->mppriv.rx_pktcount; ++ *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; ++ RT_TRACE(_module_mp_, _drv_alert_, ("recv_ok:%d \n",Adapter->mppriv.rx_pktcount)); ++ } else { ++ status = NDIS_STATUS_INVALID_LENGTH; ++ } ++ ++_func_exit_; ++ ++ return status; ++} ++//------------------------------------------------------------------------------ ++NDIS_STATUS oid_rt_pro_query_rx_packet_crc32_error_hdl(struct oid_par_priv *poid_par_priv) ++{ ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++_func_enter_; ++ ++ if (poid_par_priv->type_of_oid != QUERY_OID) { ++ status = NDIS_STATUS_NOT_ACCEPTED; ++ return status; ++ } ++ RT_TRACE(_module_mp_, _drv_alert_, ("===> oid_rt_pro_query_rx_packet_crc32_error_hdl.\n")); ++ if (poid_par_priv->information_buf_len == sizeof(ULONG)) { ++ *(ULONG*)poid_par_priv->information_buf = Adapter->mppriv.rx_crcerrpktcount; ++ *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; ++ RT_TRACE(_module_mp_, _drv_alert_, ("recv_err:%d \n",Adapter->mppriv.rx_crcerrpktcount)); ++ } else { ++ status = NDIS_STATUS_INVALID_LENGTH; ++ } ++ ++_func_exit_; ++ ++ return status; ++} ++//------------------------------------------------------------------------------ ++ ++NDIS_STATUS oid_rt_pro_reset_tx_packet_sent_hdl(struct oid_par_priv *poid_par_priv) ++{ ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++_func_enter_; ++ ++ if (poid_par_priv->type_of_oid != SET_OID) { ++ status = NDIS_STATUS_NOT_ACCEPTED; ++ return status; ++ } ++ ++ RT_TRACE(_module_mp_, _drv_alert_, ("===> oid_rt_pro_reset_tx_packet_sent_hdl.\n")); ++ Adapter->mppriv.tx_pktcount = 0; ++ ++_func_exit_; ++ ++ return status; ++} ++//------------------------------------------------------------------------------ ++NDIS_STATUS oid_rt_pro_reset_rx_packet_received_hdl(struct oid_par_priv *poid_par_priv) ++{ ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++_func_enter_; ++ ++ if (poid_par_priv->type_of_oid != SET_OID) ++ { ++ status = NDIS_STATUS_NOT_ACCEPTED; ++ return status; ++ } ++ ++ if (poid_par_priv->information_buf_len == sizeof(ULONG)) { ++ Adapter->mppriv.rx_pktcount = 0; ++ Adapter->mppriv.rx_crcerrpktcount = 0; ++ } else { ++ status = NDIS_STATUS_INVALID_LENGTH; ++ } ++ ++_func_exit_; ++ ++ return status; ++} ++//------------------------------------------------------------------------------ ++NDIS_STATUS oid_rt_reset_phy_rx_packet_count_hdl(struct oid_par_priv *poid_par_priv) ++{ ++ _irqL oldirql; ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++_func_enter_; ++ ++ if (poid_par_priv->type_of_oid != SET_OID) { ++ status = NDIS_STATUS_NOT_ACCEPTED; ++ return status; ++ } ++ ++ _irqlevel_changed_(&oldirql, LOWER); ++ ResetPhyRxPktCount(Adapter); ++ _irqlevel_changed_(&oldirql, RAISE); ++ ++_func_exit_; ++ ++ return status; ++} ++//------------------------------------------------------------------------------ ++NDIS_STATUS oid_rt_get_phy_rx_packet_received_hdl(struct oid_par_priv *poid_par_priv) ++{ ++ _irqL oldirql; ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++_func_enter_; ++ ++ RT_TRACE(_module_mp_, _drv_info_, ("+oid_rt_get_phy_rx_packet_received_hdl\n")); ++ ++ if (poid_par_priv->type_of_oid != QUERY_OID) ++ return NDIS_STATUS_NOT_ACCEPTED; ++ ++ if (poid_par_priv->information_buf_len != sizeof(ULONG)) ++ return NDIS_STATUS_INVALID_LENGTH; ++ ++ _irqlevel_changed_(&oldirql, LOWER); ++ *(ULONG*)poid_par_priv->information_buf = GetPhyRxPktReceived(Adapter); ++ _irqlevel_changed_(&oldirql, RAISE); ++ ++ *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; ++ ++ RT_TRACE(_module_mp_, _drv_notice_, ("-oid_rt_get_phy_rx_packet_received_hdl: recv_ok=%d\n", *(ULONG*)poid_par_priv->information_buf)); ++ ++_func_exit_; ++ ++ return status; ++} ++//------------------------------------------------------------------------------ ++NDIS_STATUS oid_rt_get_phy_rx_packet_crc32_error_hdl(struct oid_par_priv *poid_par_priv) ++{ ++ _irqL oldirql; ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++_func_enter_; ++ ++ RT_TRACE(_module_mp_, _drv_info_, ("+oid_rt_get_phy_rx_packet_crc32_error_hdl\n")); ++ ++ if (poid_par_priv->type_of_oid != QUERY_OID) ++ return NDIS_STATUS_NOT_ACCEPTED; ++ ++ ++ if (poid_par_priv->information_buf_len != sizeof(ULONG)) ++ return NDIS_STATUS_INVALID_LENGTH; ++ ++ _irqlevel_changed_(&oldirql, LOWER); ++ *(ULONG*)poid_par_priv->information_buf = GetPhyRxPktCRC32Error(Adapter); ++ _irqlevel_changed_(&oldirql, RAISE); ++ ++ *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; ++ ++ RT_TRACE(_module_mp_, _drv_info_, ("-oid_rt_get_phy_rx_packet_crc32_error_hdl: recv_err=%d\n", *(ULONG*)poid_par_priv->information_buf)); ++ ++_func_exit_; ++ ++ return status; ++} ++//**************** oid_rtl_seg_81_80_20 section end **************** ++NDIS_STATUS oid_rt_pro_set_continuous_tx_hdl(struct oid_par_priv *poid_par_priv) ++{ ++ _irqL oldirql; ++ u32 bStartTest; ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++_func_enter_; ++ ++ RT_TRACE(_module_mp_, _drv_notice_, ("+oid_rt_pro_set_continuous_tx_hdl\n")); ++ ++ if (poid_par_priv->type_of_oid != SET_OID) ++ return NDIS_STATUS_NOT_ACCEPTED; ++ ++ bStartTest = *((u32*)poid_par_priv->information_buf); ++ ++ _irqlevel_changed_(&oldirql, LOWER); ++ SetContinuousTx(Adapter,(u8)bStartTest); ++ if (bStartTest) { ++ struct mp_priv *pmp_priv = &Adapter->mppriv; ++ if (pmp_priv->tx.stop == 0) { ++ pmp_priv->tx.stop = 1; ++ DBG_8192C("%s: pkt tx is running...\n", __func__); ++ rtw_msleep_os(5); ++ } ++ pmp_priv->tx.stop = 0; ++ pmp_priv->tx.count = 1; ++ SetPacketTx(Adapter); ++ } ++ _irqlevel_changed_(&oldirql, RAISE); ++ ++_func_exit_; ++ ++ return status; ++} ++ ++NDIS_STATUS oid_rt_pro_set_single_carrier_tx_hdl(struct oid_par_priv *poid_par_priv) ++{ ++ _irqL oldirql; ++ u32 bStartTest; ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++_func_enter_; ++ ++ RT_TRACE(_module_mp_, _drv_alert_, ("+oid_rt_pro_set_single_carrier_tx_hdl\n")); ++ ++ if (poid_par_priv->type_of_oid != SET_OID) ++ return NDIS_STATUS_NOT_ACCEPTED; ++ ++ bStartTest = *((u32*)poid_par_priv->information_buf); ++ ++ _irqlevel_changed_(&oldirql, LOWER); ++ SetSingleCarrierTx(Adapter, (u8)bStartTest); ++ if (bStartTest) { ++ struct mp_priv *pmp_priv = &Adapter->mppriv; ++ if (pmp_priv->tx.stop == 0) { ++ pmp_priv->tx.stop = 1; ++ DBG_8192C("%s: pkt tx is running...\n", __func__); ++ rtw_msleep_os(5); ++ } ++ pmp_priv->tx.stop = 0; ++ pmp_priv->tx.count = 1; ++ SetPacketTx(Adapter); ++ } ++ _irqlevel_changed_(&oldirql, RAISE); ++ ++_func_exit_; ++ ++ return status; ++} ++ ++NDIS_STATUS oid_rt_pro_set_carrier_suppression_tx_hdl(struct oid_par_priv *poid_par_priv) ++{ ++ _irqL oldirql; ++ u32 bStartTest; ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++_func_enter_; ++ ++ RT_TRACE(_module_mp_, _drv_notice_, ("+oid_rt_pro_set_carrier_suppression_tx_hdl\n")); ++ ++ if (poid_par_priv->type_of_oid != SET_OID) ++ return NDIS_STATUS_NOT_ACCEPTED; ++ ++ bStartTest = *((u32*)poid_par_priv->information_buf); ++ ++ _irqlevel_changed_(&oldirql, LOWER); ++ SetCarrierSuppressionTx(Adapter, (u8)bStartTest); ++ if (bStartTest) { ++ struct mp_priv *pmp_priv = &Adapter->mppriv; ++ if (pmp_priv->tx.stop == 0) { ++ pmp_priv->tx.stop = 1; ++ DBG_8192C("%s: pkt tx is running...\n", __func__); ++ rtw_msleep_os(5); ++ } ++ pmp_priv->tx.stop = 0; ++ pmp_priv->tx.count = 1; ++ SetPacketTx(Adapter); ++ } ++ _irqlevel_changed_(&oldirql, RAISE); ++ ++_func_exit_; ++ ++ return status; ++} ++ ++NDIS_STATUS oid_rt_pro_set_single_tone_tx_hdl(struct oid_par_priv *poid_par_priv) ++{ ++ _irqL oldirql; ++ u32 bStartTest; ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++_func_enter_; ++ ++ RT_TRACE(_module_mp_, _drv_alert_, ("+oid_rt_pro_set_single_tone_tx_hdl\n")); ++ ++ if (poid_par_priv->type_of_oid != SET_OID) ++ return NDIS_STATUS_NOT_ACCEPTED; ++ ++ bStartTest = *((u32*)poid_par_priv->information_buf); ++ ++ _irqlevel_changed_(&oldirql, LOWER); ++ SetSingleToneTx(Adapter,(u8)bStartTest); ++ _irqlevel_changed_(&oldirql, RAISE); ++ ++_func_exit_; ++ ++ return status; ++} ++ ++NDIS_STATUS oid_rt_pro_set_modulation_hdl(struct oid_par_priv* poid_par_priv) ++{ ++ return 0; ++} ++ ++NDIS_STATUS oid_rt_pro_trigger_gpio_hdl(struct oid_par_priv *poid_par_priv) ++{ ++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++ _irqL oldirql; ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++_func_enter_; ++ ++ if (poid_par_priv->type_of_oid != SET_OID) ++ return NDIS_STATUS_NOT_ACCEPTED; ++ ++ _irqlevel_changed_(&oldirql, LOWER); ++ Adapter->HalFunc.SetHwRegHandler(Adapter, HW_VAR_TRIGGER_GPIO_0, 0); ++ _irqlevel_changed_(&oldirql, RAISE); ++ ++_func_exit_; ++ ++ return status; ++} ++//**************** oid_rtl_seg_81_80_00 section end **************** ++//------------------------------------------------------------------------------ ++NDIS_STATUS oid_rt_pro8711_join_bss_hdl(struct oid_par_priv *poid_par_priv) ++{ ++#if 0 ++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++ _irqL oldirql; ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ ++ PNDIS_802_11_SSID pssid; ++ ++_func_enter_; ++ ++ if (poid_par_priv->type_of_oid != SET_OID) ++ return NDIS_STATUS_NOT_ACCEPTED; ++ ++ *poid_par_priv->bytes_needed = (u32)sizeof(NDIS_802_11_SSID); ++ *poid_par_priv->bytes_rw = 0; ++ if (poid_par_priv->information_buf_len < *poid_par_priv->bytes_needed) ++ return NDIS_STATUS_INVALID_LENGTH; ++ ++ pssid = (PNDIS_802_11_SSID)poid_par_priv->information_buf; ++ ++ _irqlevel_changed_(&oldirql, LOWER); ++ ++ if (mp_start_joinbss(Adapter, pssid) == _FAIL) ++ status = NDIS_STATUS_NOT_ACCEPTED; ++ ++ _irqlevel_changed_(&oldirql, RAISE); ++ ++ *poid_par_priv->bytes_rw = sizeof(NDIS_802_11_SSID); ++ ++_func_exit_; ++ ++ return status; ++#else ++ return 0; ++#endif ++} ++//------------------------------------------------------------------------------ ++NDIS_STATUS oid_rt_pro_read_register_hdl(struct oid_par_priv *poid_par_priv) ++{ ++ _irqL oldirql; ++ pRW_Reg RegRWStruct; ++ u32 offset, width; ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++_func_enter_; ++ ++ RT_TRACE(_module_mp_, _drv_info_, ++ ("+oid_rt_pro_read_register_hdl\n")); ++ ++ if (poid_par_priv->type_of_oid != QUERY_OID) ++ return NDIS_STATUS_NOT_ACCEPTED; ++ ++ RegRWStruct = (pRW_Reg)poid_par_priv->information_buf; ++ offset = RegRWStruct->offset; ++ width = RegRWStruct->width; ++ ++ if (offset > 0xFFF) ++ return NDIS_STATUS_NOT_ACCEPTED; ++ ++ _irqlevel_changed_(&oldirql, LOWER); ++ ++ switch (width) { ++ case 1: ++ RegRWStruct->value = rtw_read8(Adapter, offset); ++ break; ++ case 2: ++ RegRWStruct->value = rtw_read16(Adapter, offset); ++ break; ++ default: ++ width = 4; ++ RegRWStruct->value = rtw_read32(Adapter, offset); ++ break; ++ } ++ RT_TRACE(_module_mp_, _drv_notice_, ++ ("oid_rt_pro_read_register_hdl: offset:0x%04X value:0x%X\n", ++ offset, RegRWStruct->value)); ++ ++ _irqlevel_changed_(&oldirql, RAISE); ++ ++ *poid_par_priv->bytes_rw = width; ++ ++_func_exit_; ++ ++ return status; ++} ++//------------------------------------------------------------------------------ ++NDIS_STATUS oid_rt_pro_write_register_hdl(struct oid_par_priv *poid_par_priv) ++{ ++ _irqL oldirql; ++ pRW_Reg RegRWStruct; ++ u32 offset, width, value; ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER padapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++_func_enter_; ++ ++ RT_TRACE(_module_mp_, _drv_info_, ++ ("+oid_rt_pro_write_register_hdl\n")); ++ ++ if (poid_par_priv->type_of_oid != SET_OID) ++ return NDIS_STATUS_NOT_ACCEPTED; ++ ++ RegRWStruct = (pRW_Reg)poid_par_priv->information_buf; ++ offset = RegRWStruct->offset; ++ width = RegRWStruct->width; ++ value = RegRWStruct->value; ++ ++ if (offset > 0xFFF) ++ return NDIS_STATUS_NOT_ACCEPTED; ++ ++ _irqlevel_changed_(&oldirql, LOWER); ++ ++ switch (RegRWStruct->width) ++ { ++ case 1: ++ if (value > 0xFF) { ++ status = NDIS_STATUS_NOT_ACCEPTED; ++ break; ++ } ++ rtw_write8(padapter, offset, (u8)value); ++ break; ++ case 2: ++ if (value > 0xFFFF) { ++ status = NDIS_STATUS_NOT_ACCEPTED; ++ break; ++ } ++ rtw_write16(padapter, offset, (u16)value); ++ break; ++ case 4: ++ rtw_write32(padapter, offset, value); ++ break; ++ default: ++ status = NDIS_STATUS_NOT_ACCEPTED; ++ break; ++ } ++ ++ _irqlevel_changed_(&oldirql, RAISE); ++ ++ RT_TRACE(_module_mp_, _drv_info_, ++ ("-oid_rt_pro_write_register_hdl: offset=0x%08X width=%d value=0x%X\n", ++ offset, width, value)); ++ ++_func_exit_; ++ ++ return status; ++} ++//------------------------------------------------------------------------------ ++NDIS_STATUS oid_rt_pro_burst_read_register_hdl(struct oid_par_priv *poid_par_priv) ++{ ++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++ _irqL oldirql; ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ ++ pBurst_RW_Reg pBstRwReg; ++ ++_func_enter_; ++ ++ RT_TRACE(_module_mp_, _drv_notice_, ("+oid_rt_pro_burst_read_register_hdl\n")); ++ ++ if (poid_par_priv->type_of_oid != QUERY_OID) ++ return NDIS_STATUS_NOT_ACCEPTED; ++#if 0 ++ pBstRwReg = (pBurst_RW_Reg)poid_par_priv->information_buf; ++ ++ _irqlevel_changed_(&oldirql, LOWER); ++ rtw_read_mem(Adapter, pBstRwReg->offset, (u32)pBstRwReg->len, pBstRwReg->Data); ++ _irqlevel_changed_(&oldirql,RAISE); ++ ++ *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; ++#endif ++ RT_TRACE(_module_mp_, _drv_info_, ("-oid_rt_pro_burst_read_register_hdl\n")); ++ ++_func_exit_; ++ ++ return status; ++} ++//------------------------------------------------------------------------------ ++NDIS_STATUS oid_rt_pro_burst_write_register_hdl(struct oid_par_priv *poid_par_priv) ++{ ++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++ _irqL oldirql; ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ ++ pBurst_RW_Reg pBstRwReg; ++ ++_func_enter_; ++ ++ RT_TRACE(_module_mp_, _drv_notice_, ("+oid_rt_pro_burst_write_register_hdl\n")); ++ ++ if (poid_par_priv->type_of_oid != SET_OID) ++ return NDIS_STATUS_NOT_ACCEPTED; ++#if 0 ++ pBstRwReg = (pBurst_RW_Reg)poid_par_priv->information_buf; ++ ++ _irqlevel_changed_(&oldirql, LOWER); ++ rtw_write_mem(Adapter, pBstRwReg->offset, (u32)pBstRwReg->len, pBstRwReg->Data); ++ _irqlevel_changed_(&oldirql, RAISE); ++#endif ++ RT_TRACE(_module_mp_, _drv_info_, ("-oid_rt_pro_burst_write_register_hdl\n")); ++ ++_func_exit_; ++ ++ return status; ++} ++//------------------------------------------------------------------------------ ++NDIS_STATUS oid_rt_pro_write_txcmd_hdl(struct oid_par_priv *poid_par_priv) ++{ ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++/* ++ PADAPTER Adapter = (PADAPTER)( poid_par_priv->adapter_context); ++ ++ _irqL oldirql; ++ ++ TX_CMD_Desc *TxCmd_Info; ++ ++_func_enter_; ++ ++ if (poid_par_priv->type_of_oid != SET_OID) ++ return NDIS_STATUS_NOT_ACCEPTED; ++ ++ RT_TRACE(_module_mp_, _drv_info_, ("+Set OID_RT_PRO_WRITE_TXCMD\n")); ++ ++ TxCmd_Info=(TX_CMD_Desc*)poid_par_priv->information_buf; ++ ++ RT_TRACE(_module_mp_, _drv_info_, ("WRITE_TXCMD:Addr=%.8X\n", TxCmd_Info->offset)); ++ RT_TRACE(_module_mp_, _drv_info_, ("WRITE_TXCMD:1.)%.8X\n", (ULONG)TxCmd_Info->TxCMD.value[0])); ++ RT_TRACE(_module_mp_, _drv_info_, ("WRITE_TXCMD:2.)%.8X\n", (ULONG)TxCmd_Info->TxCMD.value[1])); ++ RT_TRACE(_module_mp_, _drv_info_, (("WRITE_TXCMD:3.)%.8X\n", (ULONG)TxCmd_Info->TxCMD.value[2])); ++ RT_TRACE(_module_mp_, _drv_info_, ("WRITE_TXCMD:4.)%.8X\n", (ULONG)TxCmd_Info->TxCMD.value[3])); ++ ++ _irqlevel_changed_(&oldirql, LOWER); ++ ++ rtw_write32(Adapter, TxCmd_Info->offset + 0, (unsigned int)TxCmd_Info->TxCMD.value[0]); ++ rtw_write32(Adapter, TxCmd_Info->offset + 4, (unsigned int)TxCmd_Info->TxCMD.value[1]); ++ ++ _irqlevel_changed_(&oldirql, RAISE); ++*/ ++ ++ RT_TRACE(_module_mp_, _drv_notice_, ++ ("-Set OID_RT_PRO_WRITE_TXCMD: status=0x%08X\n", status)); ++ ++_func_exit_; ++ ++ return status; ++} ++ ++//------------------------------------------------------------------------------ ++NDIS_STATUS oid_rt_pro_read16_eeprom_hdl(struct oid_par_priv *poid_par_priv) ++{ ++ PADAPTER Adapter = (PADAPTER)( poid_par_priv->adapter_context); ++ ++ _irqL oldirql; ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ ++ pEEPROM_RWParam pEEPROM; ++ ++_func_enter_; ++ ++ RT_TRACE(_module_mp_, _drv_info_, ("+Query OID_RT_PRO_READ16_EEPROM\n")); ++ ++ if (poid_par_priv->type_of_oid != QUERY_OID) ++ return NDIS_STATUS_NOT_ACCEPTED; ++#if 0 ++ pEEPROM = (pEEPROM_RWParam)poid_par_priv->information_buf; ++ ++ _irqlevel_changed_(&oldirql, LOWER); ++ pEEPROM->value = eeprom_read16(Adapter, (u16)(pEEPROM->offset >> 1)); ++ _irqlevel_changed_(&oldirql, RAISE); ++ ++ *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; ++ ++ RT_TRACE(_module_mp_, _drv_notice_, ++ ("-Query OID_RT_PRO_READ16_EEPROM: offset=0x%x value=0x%x\n", ++ pEEPROM->offset, pEEPROM->value)); ++#endif ++_func_exit_; ++ ++ return status; ++} ++ ++//------------------------------------------------------------------------------ ++NDIS_STATUS oid_rt_pro_write16_eeprom_hdl (struct oid_par_priv *poid_par_priv) ++{ ++ PADAPTER Adapter = (PADAPTER)( poid_par_priv->adapter_context); ++ ++ _irqL oldirql; ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ ++ pEEPROM_RWParam pEEPROM; ++ ++_func_enter_; ++ ++ RT_TRACE(_module_mp_, _drv_notice_, ("+Set OID_RT_PRO_WRITE16_EEPROM\n")); ++ ++ if (poid_par_priv->type_of_oid != SET_OID) ++ return NDIS_STATUS_NOT_ACCEPTED; ++#if 0 ++ pEEPROM = (pEEPROM_RWParam)poid_par_priv->information_buf; ++ ++ _irqlevel_changed_(&oldirql, LOWER); ++ eeprom_write16(Adapter, (u16)(pEEPROM->offset >> 1), pEEPROM->value); ++ _irqlevel_changed_(&oldirql, RAISE); ++ ++ *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; ++#endif ++_func_exit_; ++ ++ return status; ++} ++//------------------------------------------------------------------------------ ++NDIS_STATUS oid_rt_pro8711_wi_poll_hdl(struct oid_par_priv *poid_par_priv) ++{ ++#if 0 ++ PADAPTER Adapter = (PADAPTER)( poid_par_priv->adapter_context); ++ ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ ++ struct mp_wiparam *pwi_param; ++ ++_func_enter_; ++ ++ if (poid_par_priv->type_of_oid != QUERY_OID) ++ return NDIS_STATUS_NOT_ACCEPTED; ++ ++ if (poid_par_priv->information_buf_len < sizeof(struct mp_wiparam)) ++ return NDIS_STATUS_INVALID_LENGTH; ++ ++ if (Adapter->mppriv.workparam.bcompleted == _FALSE) ++ return NDIS_STATUS_NOT_ACCEPTED; ++ ++ pwi_param = (struct mp_wiparam *)poid_par_priv->information_buf; ++ ++ _rtw_memcpy(pwi_param, &Adapter->mppriv.workparam, sizeof(struct mp_wiparam)); ++ Adapter->mppriv.act_in_progress = _FALSE; ++// RT_TRACE(_module_mp_, _drv_info_, ("rf:%x\n", pwiparam->IoValue)); ++ *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; ++ ++_func_exit_; ++ ++ return status; ++#else ++ return 0; ++#endif ++} ++//------------------------------------------------------------------------------ ++NDIS_STATUS oid_rt_pro8711_pkt_loss_hdl(struct oid_par_priv *poid_par_priv) ++{ ++#if 0 ++ PADAPTER Adapter = (PADAPTER)( poid_par_priv->adapter_context); ++ ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ ++_func_enter_; ++ ++ RT_TRACE(_module_mp_, _drv_notice_, ("+oid_rt_pro8711_pkt_loss_hdl\n")); ++ ++ if (poid_par_priv->type_of_oid != QUERY_OID) ++ return NDIS_STATUS_NOT_ACCEPTED; ++ ++ if (poid_par_priv->information_buf_len < sizeof(uint)*2) { ++ RT_TRACE(_module_mp_, _drv_err_, ("-oid_rt_pro8711_pkt_loss_hdl: buf_len=%d\n", (int)poid_par_priv->information_buf_len)); ++ return NDIS_STATUS_INVALID_LENGTH; ++ } ++ ++ if (*(uint*)poid_par_priv->information_buf == 1)//init==1 ++ Adapter->mppriv.rx_pktloss = 0; ++ ++ *((uint*)poid_par_priv->information_buf+1) = Adapter->mppriv.rx_pktloss; ++ *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; ++ ++_func_exit_; ++ ++ return status; ++#else ++ return 0; ++#endif ++} ++//------------------------------------------------------------------------------ ++NDIS_STATUS oid_rt_rd_attrib_mem_hdl(struct oid_par_priv *poid_par_priv) ++{ ++#if 0 ++ PADAPTER Adapter = (PADAPTER)( poid_par_priv->adapter_context); ++ struct io_queue *pio_queue = (struct io_queue *)Adapter->pio_queue; ++ struct intf_hdl *pintfhdl = &pio_queue->intf; ++ ++ _irqL oldirql; ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ ++#ifdef CONFIG_SDIO_HCI ++ void (*_attrib_read)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem); ++#endif ++ ++_func_enter_; ++ ++ RT_TRACE(_module_mp_, _drv_notice_, ("+Query OID_RT_RD_ATTRIB_MEM\n")); ++ ++ if (poid_par_priv->type_of_oid != QUERY_OID) ++ return NDIS_STATUS_NOT_ACCEPTED; ++ ++#ifdef CONFIG_SDIO_HCI ++ _irqlevel_changed_(&oldirql, LOWER); ++{ ++ u32 *plmem = (u32*)poid_par_priv->information_buf+2; ++ _attrib_read = pintfhdl->io_ops._attrib_read; ++ _attrib_read(pintfhdl, *((u32*)poid_par_priv->information_buf), ++ *((u32*)poid_par_priv->information_buf+1), (u8*)plmem); ++ *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; ++} ++ _irqlevel_changed_(&oldirql, RAISE); ++#endif ++ ++_func_exit_; ++ ++ return status; ++#else ++ return 0; ++#endif ++} ++//------------------------------------------------------------------------------ ++NDIS_STATUS oid_rt_wr_attrib_mem_hdl (struct oid_par_priv *poid_par_priv) ++{ ++#if 0 ++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); ++ struct io_queue *pio_queue = (struct io_queue *)Adapter->pio_queue; ++ struct intf_hdl *pintfhdl = &pio_queue->intf; ++ ++ _irqL oldirql; ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ ++#ifdef CONFIG_SDIO_HCI ++ void (*_attrib_write)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem); ++#endif ++ ++_func_enter_; ++ ++ if (poid_par_priv->type_of_oid != SET_OID) ++ return NDIS_STATUS_NOT_ACCEPTED; ++ ++#ifdef CONFIG_SDIO_HCI ++ _irqlevel_changed_(&oldirql, LOWER); ++{ ++ u32 *plmem = (u32*)poid_par_priv->information_buf + 2; ++ _attrib_write = pintfhdl->io_ops._attrib_write; ++ _attrib_write(pintfhdl, *(u32*)poid_par_priv->information_buf, ++ *((u32*)poid_par_priv->information_buf+1), (u8*)plmem); ++} ++ _irqlevel_changed_(&oldirql, RAISE); ++#endif ++ ++_func_exit_; ++ ++ return status; ++#else ++ return 0; ++#endif ++} ++//------------------------------------------------------------------------------ ++NDIS_STATUS oid_rt_pro_set_rf_intfs_hdl(struct oid_par_priv *poid_par_priv) ++{ ++#if 0 ++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++ _irqL oldirql; ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ ++_func_enter_; ++ ++ RT_TRACE(_module_mp_, _drv_notice_, ("+OID_RT_PRO_SET_RF_INTFS\n")); ++ ++ if (poid_par_priv->type_of_oid != SET_OID) ++ return NDIS_STATUS_NOT_ACCEPTED; ++ ++ _irqlevel_changed_(&oldirql, LOWER); ++ ++ if (rtw_setrfintfs_cmd(Adapter, *(unsigned char*)poid_par_priv->information_buf) == _FAIL) ++ status = NDIS_STATUS_NOT_ACCEPTED; ++ ++ _irqlevel_changed_(&oldirql, RAISE); ++ ++_func_exit_; ++ ++ return status; ++#else ++ return 0; ++#endif ++} ++//------------------------------------------------------------------------------ ++NDIS_STATUS oid_rt_poll_rx_status_hdl(struct oid_par_priv *poid_par_priv) ++{ ++#if 0 ++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ ++_func_enter_; ++ ++ if (poid_par_priv->type_of_oid != QUERY_OID) ++ return NDIS_STATUS_NOT_ACCEPTED; ++ ++ _rtw_memcpy(poid_par_priv->information_buf, (unsigned char*)&Adapter->mppriv.rxstat, sizeof(struct recv_stat)); ++ *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; ++ ++_func_exit_; ++ ++ return status; ++#else ++ return 0; ++#endif ++} ++//------------------------------------------------------------------------------ ++NDIS_STATUS oid_rt_pro_cfg_debug_message_hdl(struct oid_par_priv *poid_par_priv) ++{ ++#if 0 ++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ ++ PCFG_DBG_MSG_STRUCT pdbg_msg; ++ ++_func_enter_; ++ ++// RT_TRACE(0xffffffffff,_drv_alert_,("===> oid_rt_pro_cfg_debug_message_hdl.\n")); ++ ++#if 0//#ifdef CONFIG_DEBUG_RTL871X ++ ++ pdbg_msg = (PCFG_DBG_MSG_STRUCT)(poid_par_priv->information_buf); ++ ++ if (poid_par_priv->type_of_oid == SET_OID) { ++ RT_TRACE(0xffffffffff, _drv_alert_, ++ ("===>Set level :0x%08x, H32:0x%08x L32:0x%08x\n", ++ pdbg_msg->DebugLevel, pdbg_msg->DebugComponent_H32, pdbg_msg->DebugComponent_L32)); ++ ++ GlobalDebugLevel = pdbg_msg->DebugLevel; ++ GlobalDebugComponents = (pdbg_msg->DebugComponent_H32 << 32) | pdbg_msg->DebugComponent_L32; ++ RT_TRACE(0xffffffffff, _drv_alert_, ++ ("===> Set level :0x%08x, component:0x%016x\n", ++ GlobalDebugLevel, (u32)GlobalDebugComponents)); ++ } else { ++ pdbg_msg->DebugLevel = GlobalDebugLevel; ++ pdbg_msg->DebugComponent_H32 = (u32)(GlobalDebugComponents >> 32); ++ pdbg_msg->DebugComponent_L32 = (u32)GlobalDebugComponents; ++ *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; ++ ++ RT_TRACE(0xffffffffff, _drv_alert_, ++ ("===>Query level:0x%08x H32:0x%08x L32:0x%08x\n", ++ (u32)pdbg_msg->DebugLevel, (u32)pdbg_msg->DebugComponent_H32, (u32)pdbg_msg->DebugComponent_L32)); ++ } ++ ++#endif ++ ++_func_exit_; ++ ++ return status; ++#else ++ return 0; ++#endif ++} ++//------------------------------------------------------------------------------ ++NDIS_STATUS oid_rt_pro_set_data_rate_ex_hdl(struct oid_par_priv *poid_par_priv) ++{ ++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++ _irqL oldirql; ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ ++_func_enter_; ++ ++ RT_TRACE(_module_mp_, _drv_notice_, ("+OID_RT_PRO_SET_DATA_RATE_EX\n")); ++ ++ if (poid_par_priv->type_of_oid != SET_OID) ++ return NDIS_STATUS_NOT_ACCEPTED; ++ ++ _irqlevel_changed_(&oldirql, LOWER); ++ ++ if (rtw_setdatarate_cmd(Adapter, poid_par_priv->information_buf) !=_SUCCESS) ++ status = NDIS_STATUS_NOT_ACCEPTED; ++ ++ _irqlevel_changed_(&oldirql, RAISE); ++ ++_func_exit_; ++ ++ return status; ++} ++//----------------------------------------------------------------------------- ++NDIS_STATUS oid_rt_get_thermal_meter_hdl(struct oid_par_priv *poid_par_priv) ++{ ++ _irqL oldirql; ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ u8 thermal = 0; ++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++_func_enter_; ++ ++ RT_TRACE(_module_mp_, _drv_notice_, ("+oid_rt_get_thermal_meter_hdl\n")); ++ ++ if (poid_par_priv->type_of_oid != QUERY_OID) ++ return NDIS_STATUS_NOT_ACCEPTED; ++ ++ if (poid_par_priv->information_buf_len < sizeof(u32)) ++ return NDIS_STATUS_INVALID_LENGTH; ++ ++ _irqlevel_changed_(&oldirql, LOWER); ++ GetThermalMeter(Adapter, &thermal); ++ _irqlevel_changed_(&oldirql, RAISE); ++ ++ *(u32*)poid_par_priv->information_buf = (u32)thermal; ++ *poid_par_priv->bytes_rw = sizeof(u32); ++ ++_func_exit_; ++ ++ return status; ++} ++//----------------------------------------------------------------------------- ++NDIS_STATUS oid_rt_pro_read_tssi_hdl(struct oid_par_priv *poid_par_priv) ++{ ++#if 0 ++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++ _irqL oldirql; ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ ++_func_enter_; ++ ++ RT_TRACE(_module_mp_, _drv_notice_, ("+oid_rt_pro_read_tssi_hdl\n")); ++ ++ if (poid_par_priv->type_of_oid != SET_OID) ++ return NDIS_STATUS_NOT_ACCEPTED; ++ ++ if (Adapter->mppriv.act_in_progress == _TRUE) ++ return NDIS_STATUS_NOT_ACCEPTED; ++ ++ if (poid_par_priv->information_buf_len < sizeof(u8)) ++ return NDIS_STATUS_INVALID_LENGTH; ++ ++ //init workparam ++ Adapter->mppriv.act_in_progress = _TRUE; ++ Adapter->mppriv.workparam.bcompleted = _FALSE; ++ Adapter->mppriv.workparam.act_type = MPT_READ_TSSI; ++ Adapter->mppriv.workparam.io_offset = 0; ++ Adapter->mppriv.workparam.io_value = 0xFFFFFFFF; ++ ++ _irqlevel_changed_(&oldirql, LOWER); ++ ++ if (!rtw_gettssi_cmd(Adapter,0, (u8*)&Adapter->mppriv.workparam.io_value)) ++ status = NDIS_STATUS_NOT_ACCEPTED; ++ ++ _irqlevel_changed_(&oldirql, RAISE); ++ ++_func_exit_; ++ ++ return status; ++#else ++ return 0; ++#endif ++} ++//------------------------------------------------------------------------------ ++NDIS_STATUS oid_rt_pro_set_power_tracking_hdl(struct oid_par_priv *poid_par_priv) ++{ ++ _irqL oldirql; ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++ ++_func_enter_; ++ ++// if (poid_par_priv->type_of_oid != SET_OID) ++// return NDIS_STATUS_NOT_ACCEPTED; ++ ++ if (poid_par_priv->information_buf_len < sizeof(u8)) ++ return NDIS_STATUS_INVALID_LENGTH; ++ ++ _irqlevel_changed_(&oldirql, LOWER); ++ if (poid_par_priv->type_of_oid == SET_OID) { ++ u8 enable; ++ ++ enable = *(u8*)poid_par_priv->information_buf; ++ RT_TRACE(_module_mp_, _drv_notice_, ++ ("+oid_rt_pro_set_power_tracking_hdl: enable=%d\n", enable)); ++ ++ SetPowerTracking(Adapter, enable); ++ } else { ++ GetPowerTracking(Adapter, (u8*)poid_par_priv->information_buf); ++ } ++ _irqlevel_changed_(&oldirql, RAISE); ++ ++_func_exit_; ++ ++ return status; ++} ++//----------------------------------------------------------------------------- ++NDIS_STATUS oid_rt_pro_set_basic_rate_hdl(struct oid_par_priv *poid_par_priv) ++{ ++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++ _irqL oldirql; ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ ++ u32 ratevalue; ++ u8 datarates[NumRates]; ++ int i; ++ ++_func_enter_; ++ ++ RT_TRACE(_module_mp_, _drv_info_, ("+OID_RT_PRO_SET_BASIC_RATE\n")); ++ ++ if (poid_par_priv->type_of_oid != SET_OID) ++ return NDIS_STATUS_NOT_ACCEPTED; ++#if 0 ++ ratevalue = *((u32*)poid_par_priv->information_buf); ++ ++ for (i = 0; i < NumRates; i++) { ++ if (ratevalue == mpdatarate[i]) ++ datarates[i] = mpdatarate[i]; ++ else ++ datarates[i] = 0xff; ++ RT_TRACE(_module_rtl871x_ioctl_c_, _drv_info_, ("basicrate_inx=%d\n", datarates[i])); ++ } ++ ++ _irqlevel_changed_(&oldirql, LOWER); ++ ++ if (rtw_setbasicrate_cmd(Adapter, datarates) != _SUCCESS) ++ status = NDIS_STATUS_NOT_ACCEPTED; ++ ++ _irqlevel_changed_(&oldirql, RAISE); ++#endif ++ RT_TRACE(_module_mp_, _drv_notice_, ++ ("-OID_RT_PRO_SET_BASIC_RATE: status=0x%08X\n", status)); ++ ++_func_exit_; ++ ++ return status; ++} ++//------------------------------------------------------------------------------ ++NDIS_STATUS oid_rt_pro_qry_pwrstate_hdl(struct oid_par_priv *poid_par_priv) ++{ ++#if 0 ++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ ++_func_enter_; ++ ++ if (poid_par_priv->type_of_oid != QUERY_OID) ++ return NDIS_STATUS_NOT_ACCEPTED; ++ ++ if (poid_par_priv->information_buf_len < 8) ++ return NDIS_STATUS_INVALID_LENGTH; ++ ++ *poid_par_priv->bytes_rw = 8; ++ _rtw_memcpy(poid_par_priv->information_buf, &(Adapter->pwrctrlpriv.pwr_mode), 8); ++ *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; ++ ++ RT_TRACE(_module_mp_, _drv_notice_, ++ ("-oid_rt_pro_qry_pwrstate_hdl: pwr_mode=%d smart_ps=%d\n", ++ Adapter->pwrctrlpriv.pwr_mode, Adapter->pwrctrlpriv.smart_ps)); ++ ++_func_exit_; ++ ++ return status; ++#else ++ return 0; ++#endif ++} ++//------------------------------------------------------------------------------ ++NDIS_STATUS oid_rt_pro_set_pwrstate_hdl(struct oid_par_priv *poid_par_priv) ++{ ++#if 0 ++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ ++ uint pwr_mode, smart_ps; ++ ++_func_enter_; ++ ++ RT_TRACE(_module_mp_, _drv_notice_, ("+Set OID_RT_PRO_SET_PWRSTATE\n")); ++ ++ if (poid_par_priv->type_of_oid != SET_OID) ++ return NDIS_STATUS_NOT_ACCEPTED; ++ ++ *poid_par_priv->bytes_rw = 0; ++ *poid_par_priv->bytes_needed = 8; ++ ++ if (poid_par_priv->information_buf_len < 8) ++ return NDIS_STATUS_INVALID_LENGTH; ++ ++ pwr_mode = *(uint *)(poid_par_priv->information_buf); ++ smart_ps = *(uint *)((int)poid_par_priv->information_buf + 4); ++ ++ *poid_par_priv->bytes_rw = 8; ++ ++_func_exit_; ++ ++ return status; ++#else ++ return 0; ++#endif ++} ++//------------------------------------------------------------------------------ ++NDIS_STATUS oid_rt_pro_h2c_set_rate_table_hdl(struct oid_par_priv *poid_par_priv) ++{ ++#if 0 ++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++ _irqL oldirql; ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ ++ struct setratable_parm *prate_table; ++ u8 res; ++ ++_func_enter_; ++ ++ if (poid_par_priv->type_of_oid != SET_OID) ++ return NDIS_STATUS_NOT_ACCEPTED; ++ ++ *poid_par_priv->bytes_needed = sizeof(struct setratable_parm); ++ if (poid_par_priv->information_buf_len < sizeof(struct setratable_parm)) ++ return NDIS_STATUS_INVALID_LENGTH; ++ ++ prate_table = (struct setratable_parm*)poid_par_priv->information_buf; ++ ++ _irqlevel_changed_(&oldirql, LOWER); ++ res = rtw_setrttbl_cmd(Adapter, prate_table); ++ _irqlevel_changed_(&oldirql, RAISE); ++ ++ if (res == _FAIL) ++ status = NDIS_STATUS_FAILURE; ++ ++_func_exit_; ++ ++ return status; ++#else ++ return 0; ++#endif ++} ++//------------------------------------------------------------------------------ ++NDIS_STATUS oid_rt_pro_h2c_get_rate_table_hdl(struct oid_par_priv *poid_par_priv) ++{ ++#if 0 ++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ ++_func_enter_; ++ ++ if (poid_par_priv->type_of_oid != QUERY_OID) ++ return NDIS_STATUS_NOT_ACCEPTED; ++ ++ #if 0 ++ struct mp_wi_cntx *pmp_wi_cntx=&(Adapter->mppriv.wi_cntx); ++ u8 res=_SUCCESS; ++ DEBUG_INFO(("===> Set OID_RT_PRO_H2C_GET_RATE_TABLE.\n")); ++ ++ if(pmp_wi_cntx->bmp_wi_progress ==_TRUE){ ++ DEBUG_ERR(("\n mp workitem is progressing, not allow to set another workitem right now!!!\n")); ++ Status = NDIS_STATUS_NOT_ACCEPTED; ++ break; ++ } ++ else{ ++ pmp_wi_cntx->bmp_wi_progress=_TRUE; ++ pmp_wi_cntx->param.bcompleted=_FALSE; ++ pmp_wi_cntx->param.act_type=MPT_GET_RATE_TABLE; ++ pmp_wi_cntx->param.io_offset=0x0; ++ pmp_wi_cntx->param.bytes_cnt=sizeof(struct getratable_rsp); ++ pmp_wi_cntx->param.io_value=0xffffffff; ++ ++ res=rtw_getrttbl_cmd(Adapter,(struct getratable_rsp *)pmp_wi_cntx->param.data); ++ *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; ++ if(res != _SUCCESS) ++ { ++ Status = NDIS_STATUS_NOT_ACCEPTED; ++ } ++ } ++ DEBUG_INFO(("\n <=== Set OID_RT_PRO_H2C_GET_RATE_TABLE.\n")); ++ #endif ++ ++_func_exit_; ++ ++ return status; ++#else ++ return 0; ++#endif ++} ++ ++//**************** oid_rtl_seg_87_12_00 section start **************** ++NDIS_STATUS oid_rt_pro_encryption_ctrl_hdl(struct oid_par_priv *poid_par_priv) ++{ ++#if 0 ++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); ++ struct security_priv *psecuritypriv = &Adapter->securitypriv; ++ ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ ++ ENCRY_CTRL_STATE encry_mode; ++ ++ ++ *poid_par_priv->bytes_needed = sizeof(u8); ++ if (poid_par_priv->information_buf_len < *poid_par_priv->bytes_needed) ++ return NDIS_STATUS_INVALID_LENGTH; ++ ++ if (poid_par_priv->type_of_oid == SET_OID) ++ { ++ encry_mode = *((u8*)poid_par_priv->information_buf); ++ switch (encry_mode) ++ { ++ case HW_CONTROL: ++ #if 0 ++ Adapter->registrypriv.software_decrypt=_FALSE; ++ Adapter->registrypriv.software_encrypt=_FALSE; ++ #else ++ psecuritypriv->sw_decrypt = _FALSE; ++ psecuritypriv->sw_encrypt = _FALSE; ++ #endif ++ break; ++ case SW_CONTROL: ++ #if 0 ++ Adapter->registrypriv.software_decrypt=_TRUE; ++ Adapter->registrypriv.software_encrypt=_TRUE; ++ #else ++ psecuritypriv->sw_decrypt = _TRUE; ++ psecuritypriv->sw_encrypt = _TRUE; ++ #endif ++ break; ++ case HW_ENCRY_SW_DECRY: ++ #if 0 ++ Adapter->registrypriv.software_decrypt=_TRUE; ++ Adapter->registrypriv.software_encrypt=_FALSE; ++ #else ++ psecuritypriv->sw_decrypt = _TRUE; ++ psecuritypriv->sw_encrypt = _FALSE; ++ #endif ++ break; ++ case SW_ENCRY_HW_DECRY: ++ #if 0 ++ Adapter->registrypriv.software_decrypt=_FALSE; ++ Adapter->registrypriv.software_encrypt=_TRUE; ++ #else ++ psecuritypriv->sw_decrypt = _FALSE; ++ psecuritypriv->sw_encrypt = _TRUE; ++ #endif ++ break; ++ } ++ ++ RT_TRACE(_module_rtl871x_ioctl_c_, _drv_notice_, ++ ("-oid_rt_pro_encryption_ctrl_hdl: SET encry_mode=0x%x sw_encrypt=0x%x sw_decrypt=0x%x\n", ++ encry_mode, psecuritypriv->sw_encrypt, psecuritypriv->sw_decrypt)); ++ } ++ else { ++ #if 0 ++ if (Adapter->registrypriv.software_encrypt == _FALSE) { ++ if (Adapter->registrypriv.software_decrypt == _FALSE) ++ encry_mode = HW_CONTROL; ++ else ++ encry_mode = HW_ENCRY_SW_DECRY; ++ } ++ else { ++ if (Adapter->registrypriv.software_decrypt == _FALSE) ++ encry_mode = SW_ENCRY_HW_DECRY; ++ else ++ encry_mode = SW_CONTROL; ++ } ++ #else ++ ++ if ((psecuritypriv->sw_encrypt == _FALSE) && (psecuritypriv->sw_decrypt == _FALSE)) ++ encry_mode = HW_CONTROL; ++ else if ((psecuritypriv->sw_encrypt == _FALSE) && (psecuritypriv->sw_decrypt == _TRUE)) ++ encry_mode = HW_ENCRY_SW_DECRY; ++ else if ((psecuritypriv->sw_encrypt == _TRUE) && (psecuritypriv->sw_decrypt == _FALSE)) ++ encry_mode = SW_ENCRY_HW_DECRY; ++ else if ((psecuritypriv->sw_encrypt == _TRUE) && (psecuritypriv->sw_decrypt == _TRUE)) ++ encry_mode = SW_CONTROL; ++ ++ #endif ++ ++ *(u8*)poid_par_priv->information_buf = encry_mode; ++ *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; ++ ++ RT_TRACE(_module_mp_, _drv_notice_, ++ ("-oid_rt_pro_encryption_ctrl_hdl: QUERY encry_mode=0x%x\n", ++ encry_mode)); ++ } ++ ++ return status; ++#else ++ return 0; ++#endif ++} ++//------------------------------------------------------------------------------ ++NDIS_STATUS oid_rt_pro_add_sta_info_hdl(struct oid_par_priv *poid_par_priv) ++{ ++#if 0 ++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++ _irqL oldirql; ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ ++ struct sta_info *psta = NULL; ++ UCHAR *macaddr; ++ ++ ++ if (poid_par_priv->type_of_oid != SET_OID) ++ return NDIS_STATUS_NOT_ACCEPTED; ++ ++ *poid_par_priv->bytes_needed = ETH_ALEN; ++ if (poid_par_priv->information_buf_len < *poid_par_priv->bytes_needed) ++ return NDIS_STATUS_INVALID_LENGTH; ++ ++ macaddr = (UCHAR *) poid_par_priv->information_buf ; ++ ++ RT_TRACE(_module_rtl871x_ioctl_c_,_drv_notice_, ++ ("OID_RT_PRO_ADD_STA_INFO: addr="MAC_FMT"\n", MAC_ARG(macaddr) )); ++ ++ _irqlevel_changed_(&oldirql, LOWER); ++ ++ psta = rtw_get_stainfo(&Adapter->stapriv, macaddr); ++ ++ if (psta == NULL) { // the sta have been in sta_info_queue => do nothing ++ psta = rtw_alloc_stainfo(&Adapter->stapriv, macaddr); ++ ++ if (psta == NULL) { ++ RT_TRACE(_module_rtl871x_ioctl_c_,_drv_err_,("Can't alloc sta_info when OID_RT_PRO_ADD_STA_INFO\n")); ++ status = NDIS_STATUS_FAILURE; ++ } ++ } else { //(between drv has received this event before and fw have not yet to set key to CAM_ENTRY) ++ RT_TRACE(_module_rtl871x_ioctl_c_, _drv_err_, ++ ("Error: OID_RT_PRO_ADD_STA_INFO: sta has been in sta_hash_queue \n")); ++ } ++ ++ _irqlevel_changed_(&oldirql, RAISE); ++ ++ return status; ++#else ++ return 0; ++#endif ++} ++//------------------------------------------------------------------------------ ++NDIS_STATUS oid_rt_pro_dele_sta_info_hdl(struct oid_par_priv *poid_par_priv) ++{ ++#if 0 ++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++ _irqL irqL; ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ ++ struct sta_info *psta = NULL; ++ UCHAR *macaddr; ++ ++ ++ if (poid_par_priv->type_of_oid != SET_OID) ++ return NDIS_STATUS_NOT_ACCEPTED; ++ ++ *poid_par_priv->bytes_needed = ETH_ALEN; ++ if (poid_par_priv->information_buf_len < *poid_par_priv->bytes_needed) ++ return NDIS_STATUS_INVALID_LENGTH; ++ ++ macaddr = (UCHAR *) poid_par_priv->information_buf ; ++ RT_TRACE(_module_rtl871x_ioctl_c_,_drv_notice_, ++ ("+OID_RT_PRO_ADD_STA_INFO: addr="MAC_FMT"\n", MAC_ARG(macaddr) )); ++ ++ psta = rtw_get_stainfo(&Adapter->stapriv, macaddr); ++ if (psta != NULL) { ++ _enter_critical(&(Adapter->stapriv.sta_hash_lock), &irqL); ++ rtw_free_stainfo(Adapter, psta); ++ _exit_critical(&(Adapter->stapriv.sta_hash_lock), &irqL); ++ } ++ ++ return status; ++#else ++ return 0; ++#endif ++} ++//------------------------------------------------------------------------------ ++#include ++u32 mp_query_drv_var(_adapter *padapter, u8 offset, u32 var) ++{ ++#if 0 ++#ifdef CONFIG_SDIO_HCI ++ ++ if (offset == 1) { ++ u16 tmp_blk_num; ++ tmp_blk_num = rtw_read16(padapter, SDIO_RX0_RDYBLK_NUM); ++ RT_TRACE(_module_mp_, _drv_err_, ("Query Information, mp_query_drv_var SDIO_RX0_RDYBLK_NUM=0x%x padapter->dvobjpriv.rxblknum=0x%x\n", tmp_blk_num, padapter->dvobjpriv.rxblknum)); ++ if (padapter->dvobjpriv.rxblknum != tmp_blk_num) { ++ RT_TRACE(_module_mp_,_drv_err_, ("Query Information, mp_query_drv_var call recv rx\n")); ++ // sd_recv_rxfifo(padapter); ++ } ++ } ++ ++#if 0 ++ if(offset <=100){ //For setting data rate and query data rate ++ if(offset==100){ //For query data rate ++ RT_TRACE(_module_mp_, _drv_emerg_, ("\n mp_query_drv_var: offset(%d): query rate=0x%.2x \n",offset,padapter->registrypriv.tx_rate)); ++ var=padapter->registrypriv.tx_rate; ++ ++ } ++ else if(offset<0x1d){ //For setting data rate ++ padapter->registrypriv.tx_rate=offset; ++ var=padapter->registrypriv.tx_rate; ++ padapter->registrypriv.use_rate=_TRUE; ++ RT_TRACE(_module_mp_, _drv_emerg_, ("\n mp_query_drv_var: offset(%d): set rate=0x%.2x \n",offset,padapter->registrypriv.tx_rate)); ++ } ++ else{ //not use the data rate ++ padapter->registrypriv.use_rate=_FALSE; ++ RT_TRACE(_module_mp_, _drv_emerg_, ("\n mp_query_drv_var: offset(%d) out of rate range\n",offset)); ++ } ++ } ++ else if (offset<=110){ //for setting debug level ++ RT_TRACE(_module_mp_, _drv_emerg_, (" mp_query_drv_var: offset(%d) for set debug level\n",offset)); ++ if(offset==110){ //For query data rate ++ RT_TRACE(_module_mp_, _drv_emerg_, (" mp_query_drv_var: offset(%d): query dbg level=0x%.2x \n",offset,padapter->registrypriv.dbg_level)); ++ padapter->registrypriv.dbg_level=GlobalDebugLevel; ++ var=padapter->registrypriv.dbg_level; ++ } ++ else if(offset<110 && offset>100){ ++ RT_TRACE(_module_mp_, _drv_emerg_, (" mp_query_drv_var: offset(%d): set dbg level=0x%.2x \n",offset,offset-100)); ++ padapter->registrypriv.dbg_level=GlobalDebugLevel=offset-100; ++ var=padapter->registrypriv.dbg_level; ++ RT_TRACE(_module_mp_, _drv_emerg_, (" mp_query_drv_var(_drv_emerg_): offset(%d): set dbg level=0x%.2x \n",offset,GlobalDebugLevel)); ++ RT_TRACE(_module_mp_, _drv_alert_, (" mp_query_drv_var(_drv_alert_): offset(%d): set dbg level=0x%.2x \n",offset,GlobalDebugLevel)); ++ RT_TRACE(_module_mp_, _drv_crit_, (" mp_query_drv_var(_drv_crit_): offset(%d): set dbg level=0x%.2x \n",offset,GlobalDebugLevel)); ++ RT_TRACE(_module_mp_, _drv_err_, (" mp_query_drv_var(_drv_err_): offset(%d): set dbg level=0x%.2x \n",offset,GlobalDebugLevel)); ++ RT_TRACE(_module_mp_, _drv_warning_, (" mp_query_drv_var(_drv_warning_): offset(%d): set dbg level=0x%.2x \n",offset,GlobalDebugLevel)); ++ RT_TRACE(_module_mp_, _drv_notice_, (" mp_query_drv_var(_drv_notice_): offset(%d): set dbg level=0x%.2x \n",offset,GlobalDebugLevel)); ++ RT_TRACE(_module_mp_, _drv_info_, (" mp_query_drv_var(_drv_info_): offset(%d): set dbg level=0x%.2x \n",offset,GlobalDebugLevel)); ++ RT_TRACE(_module_mp_, _drv_debug_, (" mp_query_drv_var(_drv_debug_): offset(%d): set dbg level=0x%.2x \n",offset,GlobalDebugLevel)); ++ ++ } ++ } ++ else if(offset >110 &&offset <116){ ++ if(115==offset){ ++ RT_TRACE(_module_mp_, _drv_emerg_, (" mp_query_drv_var(_drv_emerg_): offset(%d): query TRX access type: [tx_block_mode=%x,rx_block_mode=%x]\n",\ ++ offset,padapter->dvobjpriv.tx_block_mode,padapter->dvobjpriv.rx_block_mode)); ++ } ++ else { ++ switch(offset){ ++ case 111: ++ padapter->dvobjpriv.tx_block_mode=1; ++ padapter->dvobjpriv.rx_block_mode=1; ++ RT_TRACE(_module_mp_, _drv_emerg_, \ ++ (" mp_query_drv_var(_drv_emerg_): offset(%d): SET TRX access type:(TX block/RX block) [tx_block_mode=%x,rx_block_mode=%x]\n",\ ++ offset,padapter->dvobjpriv.tx_block_mode,padapter->dvobjpriv.rx_block_mode)); ++ break; ++ case 112: ++ padapter->dvobjpriv.tx_block_mode=1; ++ padapter->dvobjpriv.rx_block_mode=0; ++ RT_TRACE(_module_mp_, _drv_emerg_, \ ++ (" mp_query_drv_var(_drv_emerg_): offset(%d): SET TRX access type:(TX block/RX byte) [tx_block_mode=%x,rx_block_mode=%x]\n",\ ++ offset,padapter->dvobjpriv.tx_block_mode,padapter->dvobjpriv.rx_block_mode)); ++ break; ++ case 113: ++ padapter->dvobjpriv.tx_block_mode=0; ++ padapter->dvobjpriv.rx_block_mode=1; ++ RT_TRACE(_module_mp_, _drv_emerg_, \ ++ (" mp_query_drv_var(_drv_emerg_): offset(%d): SET TRX access type:(TX byte/RX block) [tx_block_mode=%x,rx_block_mode=%x]\n",\ ++ offset,padapter->dvobjpriv.tx_block_mode,padapter->dvobjpriv.rx_block_mode)); ++ break; ++ case 114: ++ padapter->dvobjpriv.tx_block_mode=0; ++ padapter->dvobjpriv.rx_block_mode=0; ++ RT_TRACE(_module_mp_, _drv_emerg_, \ ++ (" mp_query_drv_var(_drv_emerg_): offset(%d): SET TRX access type:(TX byte/RX byte) [tx_block_mode=%x,rx_block_mode=%x]\n",\ ++ offset,padapter->dvobjpriv.tx_block_mode,padapter->dvobjpriv.rx_block_mode)); ++ break; ++ default : ++ break; ++ ++ } ++ ++ } ++ ++ } ++ else if(offset>=127){ ++ u64 prnt_dbg_comp; ++ u8 chg_idx; ++ u64 tmp_dbg_comp; ++ chg_idx=offset-0x80; ++ tmp_dbg_comp=BIT(chg_idx); ++ prnt_dbg_comp=padapter->registrypriv.dbg_component= GlobalDebugComponents; ++ RT_TRACE(_module_mp_, _drv_emerg_, (" 1: mp_query_drv_var: offset(%d;0x%x):for dbg conpoment prnt_dbg_comp=0x%.16x GlobalDebugComponents=0x%.16x padapter->registrypriv.dbg_component=0x%.16x\n",offset,offset,prnt_dbg_comp,GlobalDebugComponents,padapter->registrypriv.dbg_component)); ++ if(offset==127){ ++ // prnt_dbg_comp=padapter->registrypriv.dbg_component= GlobalDebugComponents; ++ var=(u32)(padapter->registrypriv.dbg_component); ++ RT_TRACE(0xffffffff, _drv_emerg_, ("2: mp_query_drv_var: offset(%d;0x%x):for query dbg conpoment=0x%x(l) 0x%x(h) GlobalDebugComponents=0x%x(l) 0x%x(h) \n",offset,offset,padapter->registrypriv.dbg_component,prnt_dbg_comp)); ++ prnt_dbg_comp=GlobalDebugComponents; ++ RT_TRACE(0xffffffff, _drv_emerg_, ("2-1: mp_query_drv_var: offset(%d;0x%x):for query dbg conpoment=0x%x(l) 0x%x(h) GlobalDebugComponents=0x%x(l) 0x%x(h)\n",offset,offset,padapter->registrypriv.dbg_component,prnt_dbg_comp)); ++ prnt_dbg_comp=GlobalDebugComponents=padapter->registrypriv.dbg_component; ++ RT_TRACE(0xffffffff, _drv_emerg_, ("2-2: mp_query_drv_var: offset(%d;0x%x):for query dbg conpoment=0x%x(l) 0x%x(h) GlobalDebugComponents=0x%x(l) 0x%x(h)\n",offset,offset,padapter->registrypriv.dbg_component,prnt_dbg_comp)); ++ ++ } ++ else{ ++ RT_TRACE(0xffffffff, _drv_emerg_, ("3: mp_query_drv_var: offset(%d;0x%x):for query dbg conpoment=0x%x(l) 0x%x(h) GlobalDebugComponents=0x%x(l) 0x%x(h) chg_idx=%d\n",offset,offset,padapter->registrypriv.dbg_component,prnt_dbg_comp,chg_idx)); ++ prnt_dbg_comp=GlobalDebugComponents; ++ RT_TRACE(0xffffffff, _drv_emerg_,("3-1: mp_query_drv_var: offset(%d;0x%x):for query dbg conpoment=0x%x(l) 0x%x(h) GlobalDebugComponents=0x%x(l) 0x%x(h) chg_idx=%d\n",offset,offset,padapter->registrypriv.dbg_component,prnt_dbg_comp,chg_idx));// ("3-1: mp_query_drv_var: offset(%d;0x%x):before set dbg conpoment=0x%x chg_idx=%d or0x%x BIT(chg_idx[%d]=0x%x)\n",offset,offset,prnt_dbg_comp,chg_idx,chg_idx,(chg_idx),tmp_dbg_comp) ++ prnt_dbg_comp=GlobalDebugComponents=padapter->registrypriv.dbg_component; ++ RT_TRACE(0xffffffff, _drv_emerg_, ("3-2: mp_query_drv_var: offset(%d;0x%x):for query dbg conpoment=0x%x(l) 0x%x(h) GlobalDebugComponents=0x%x(l) 0x%x(h)\n",offset,offset,padapter->registrypriv.dbg_component,prnt_dbg_comp)); ++ ++ if(GlobalDebugComponents&tmp_dbg_comp){ ++ //this bit is already set, now clear it ++ GlobalDebugComponents=GlobalDebugComponents&(~tmp_dbg_comp); ++ } ++ else{ ++ //this bit is not set, now set it. ++ GlobalDebugComponents =GlobalDebugComponents|tmp_dbg_comp; ++ } ++ RT_TRACE(0xffffffff, _drv_emerg_, ("4: mp_query_drv_var: offset(%d;0x%x):before set dbg conpoment tmp_dbg_comp=0x%x GlobalDebugComponents=0x%x(l) 0x%x(h)",offset,offset,tmp_dbg_comp,prnt_dbg_comp)); ++ prnt_dbg_comp=GlobalDebugComponents; ++ RT_TRACE(0xffffffff, _drv_emerg_, ("4-1: mp_query_drv_var: offset(%d;0x%x):before set dbg conpoment tmp_dbg_comp=0x%x GlobalDebugComponents=0x%x(l) 0x%x(h)",offset,offset,tmp_dbg_comp,prnt_dbg_comp)); ++ ++ RT_TRACE(_module_rtl871x_xmit_c_, _drv_emerg_, ("0: mp_query_drv_var(_module_rtl871x_xmit_c_:0): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n",offset,offset,prnt_dbg_comp)); ++ RT_TRACE(_module_xmit_osdep_c_, _drv_emerg_, ("1: mp_query_drv_var(_module_xmit_osdep_c_:1): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n",offset,offset,GlobalDebugComponents)); ++ RT_TRACE(_module_rtl871x_recv_c_, _drv_emerg_, ("2: mp_query_drv_var(_module_rtl871x_recv_c_:2): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n",offset,offset,GlobalDebugComponents)); ++ RT_TRACE(_module_recv_osdep_c_, _drv_emerg_, ("3: mp_query_drv_var(_module_recv_osdep_c_:3): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n",offset,offset,GlobalDebugComponents)); ++ RT_TRACE(_module_rtl871x_mlme_c_, _drv_emerg_, ("4: mp_query_drv_var(_module_rtl871x_mlme_c_:4): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n",offset,offset,GlobalDebugComponents)); ++ RT_TRACE(_module_mlme_osdep_c_, _drv_emerg_, (" 5:mp_query_drv_var(_module_mlme_osdep_c_:5): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n",offset,offset,GlobalDebugComponents)); ++ RT_TRACE(_module_rtl871x_sta_mgt_c_, _drv_emerg_, ("6: mp_query_drv_var(_module_rtl871x_sta_mgt_c_:6): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n",offset,offset,GlobalDebugComponents)); ++ RT_TRACE(_module_rtl871x_cmd_c_, _drv_emerg_, ("7: mp_query_drv_var(_module_rtl871x_cmd_c_:7): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n",offset,offset,GlobalDebugComponents)); ++ RT_TRACE(_module_cmd_osdep_c_, _drv_emerg_, ("8: mp_query_drv_var(_module_cmd_osdep_c_:8): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n",offset,offset,GlobalDebugComponents)); ++ RT_TRACE(_module_rtl871x_io_c_, _drv_emerg_, ("9: mp_query_drv_var(_module_rtl871x_io_c_:9): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n",offset,offset,GlobalDebugComponents)); ++ RT_TRACE(_module_io_osdep_c_, _drv_emerg_, ("10: mp_query_drv_var(_module_io_osdep_c_:10): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n",offset,offset,GlobalDebugComponents)); ++ RT_TRACE(_module_os_intfs_c_, _drv_emerg_, ("11: mp_query_drv_var(_module_os_intfs_c_:11): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n",offset,offset,GlobalDebugComponents)); ++ RT_TRACE(_module_rtl871x_security_c_, _drv_emerg_, ("12: mp_query_drv_var(_module_rtl871x_security_c_:12): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n",offset,offset,GlobalDebugComponents)); ++ RT_TRACE(_module_rtl871x_eeprom_c_, _drv_emerg_, ("13: mp_query_drv_var(_module_rtl871x_eeprom_c_:13): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n",offset,offset,GlobalDebugComponents)); ++ RT_TRACE(_module_hal_init_c_, _drv_emerg_, ("14: mp_query_drv_var(_module_hal_init_c_:14): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n",offset,offset,GlobalDebugComponents)); ++ RT_TRACE(_module_hci_hal_init_c_, _drv_emerg_, ("15: mp_query_drv_var(_module_hci_hal_init_c_:15): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n",offset,offset,GlobalDebugComponents)); ++ RT_TRACE(_module_rtl871x_ioctl_c_, _drv_emerg_, ("16: mp_query_drv_var(_module_rtl871x_ioctl_c_:16): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n",offset,offset,GlobalDebugComponents)); ++ RT_TRACE(_module_rtl871x_ioctl_set_c_, _drv_emerg_, ("17: mp_query_drv_var(_module_rtl871x_ioctl_set_c_:17): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n",offset,offset,GlobalDebugComponents)); ++ RT_TRACE(_module_rtl871x_ioctl_query_c_, _drv_emerg_, ("18: mp_query_drv_var(_module_rtl871x_ioctl_query_c_:18): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n",offset,offset,GlobalDebugComponents)); ++ RT_TRACE(_module_rtl871x_pwrctrl_c_, _drv_emerg_, ("19: mp_query_drv_var(_module_rtl871x_pwrctrl_c_:19): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n",offset,offset,GlobalDebugComponents)); ++ RT_TRACE(_module_hci_intfs_c_, _drv_emerg_, ("20: mp_query_drv_var(_module_hci_intfs_c_:20): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n",offset,offset,GlobalDebugComponents)); ++ RT_TRACE(_module_hci_ops_c_, _drv_emerg_, ("21: mp_query_drv_var(_module_hci_ops_c_:21): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n",offset,offset,GlobalDebugComponents)); ++ RT_TRACE(_module_osdep_service_c_, _drv_emerg_, ("22: mp_query_drv_var(_module_osdep_service_c_:22): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n",offset,offset,GlobalDebugComponents)); ++ RT_TRACE(_module_mp_, _drv_emerg_, ("23: mp_query_drv_var(_module_mp_:23): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n",offset,offset,GlobalDebugComponents)); ++ RT_TRACE(_module_hci_ops_os_c_, _drv_emerg_, ("24: mp_query_drv_var(_module_hci_ops_os_c_:24): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n",offset,offset,GlobalDebugComponents)); ++ var=(u32)(GlobalDebugComponents); ++ //GlobalDebugComponents=padapter->registrypriv.dbg_component; ++ RT_TRACE(0xffffffff, _drv_emerg_, (" ==mp_query_drv_var(_module_mp_): offset(%d;0x%x):before set dbg conpoment=0x%x(l) 0x%x(h)\n",offset,offset,GlobalDebugComponents)); ++ ++ } ++ } ++ else{ ++ RT_TRACE(_module_mp_, _drv_emerg_, ("\n mp_query_drv_var: offset(%d) >110\n",offset)); ++ } ++#endif ++#endif ++ ++ return var; ++#else ++ return 0; ++#endif ++} ++ ++NDIS_STATUS oid_rt_pro_query_dr_variable_hdl(struct oid_par_priv *poid_par_priv) ++{ ++#if 0 ++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++ _irqL oldirql; ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ ++ DR_VARIABLE_STRUCT *pdrv_var; ++ ++ ++ if (poid_par_priv->type_of_oid != QUERY_OID) ++ return NDIS_STATUS_NOT_ACCEPTED; ++ ++ *poid_par_priv->bytes_needed = sizeof(DR_VARIABLE_STRUCT); ++ if (poid_par_priv->information_buf_len < *poid_par_priv->bytes_needed) ++ return NDIS_STATUS_INVALID_LENGTH; ++ ++ RT_TRACE(_module_mp_, _drv_notice_, ("+Query Information, OID_RT_PRO_QUERY_DR_VARIABLE\n")); ++ ++ pdrv_var = (struct _DR_VARIABLE_STRUCT_ *)poid_par_priv->information_buf; ++ ++ _irqlevel_changed_(&oldirql, LOWER); ++ pdrv_var->variable = mp_query_drv_var(Adapter, pdrv_var->offset, pdrv_var->variable); ++ _irqlevel_changed_(&oldirql, RAISE); ++ ++ *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; ++ ++ RT_TRACE(_module_mp_, _drv_notice_, ++ ("-oid_rt_pro_query_dr_variable_hdl: offset=0x%x valule=0x%x\n", ++ pdrv_var->offset, pdrv_var->variable)); ++ ++ return status; ++#else ++ return 0; ++#endif ++} ++//------------------------------------------------------------------------------ ++NDIS_STATUS oid_rt_pro_rx_packet_type_hdl(struct oid_par_priv *poid_par_priv) ++{ ++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ ++ RT_TRACE(_module_mp_, _drv_err_, ("oid_rt_pro_rx_packet_type_hdl...................\n")); ++#if 0 ++ ++ if (poid_par_priv->information_buf_len < sizeof (UCHAR)) { ++ status = NDIS_STATUS_INVALID_LENGTH; ++ *poid_par_priv->bytes_needed = sizeof(UCHAR); ++ return status; ++ } ++ ++ if (poid_par_priv->type_of_oid == SET_OID) { ++ Adapter->mppriv.rx_with_status = *(UCHAR *) poid_par_priv->information_buf; ++ RT_TRACE(_module_rtl871x_ioctl_c_,_drv_err_, ("Query Information, OID_RT_PRO_RX_PACKET_TYPE:%d \n",\ ++ Adapter->mppriv.rx_with_status)); ++ ++ //*(u32 *)&Adapter->eeprompriv.mac_addr[0]=rtw_read32(Adapter, 0x10250050); ++ //*(u16 *)&Adapter->eeprompriv.mac_addr[4]=rtw_read16(Adapter, 0x10250054); ++ RT_TRACE(_module_rtl871x_ioctl_c_,_drv_err_,("MAC addr=0x%x:0x%x:0x%x:0x%x:0x%x:0x%x \n", ++ Adapter->eeprompriv.mac_addr[0],Adapter->eeprompriv.mac_addr[1],Adapter->eeprompriv.mac_addr[2],\ ++ Adapter->eeprompriv.mac_addr[3],Adapter->eeprompriv.mac_addr[4],Adapter->eeprompriv.mac_addr[5])); ++ ++ } ++ else { ++ *(UCHAR *) poid_par_priv->information_buf = Adapter->mppriv.rx_with_status; ++ *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; ++ ++ RT_TRACE(_module_rtl871x_ioctl_c_,_drv_err_, ("Query Information, OID_RT_PRO_RX_PACKET_TYPE:%d \n", \ ++ Adapter->mppriv.rx_with_status)); ++ ++ //*(u32 *)&Adapter->eeprompriv.mac_addr[0]=rtw_read32(Adapter, 0x10250050); ++ //*(u16 *)&Adapter->eeprompriv.mac_addr[4]=rtw_read16(Adapter, 0x10250054); ++ RT_TRACE(_module_rtl871x_ioctl_c_,_drv_err_,("MAC addr=0x%x:0x%x:0x%x:0x%x:0x%x:0x%x \n", ++ Adapter->eeprompriv.mac_addr[0],Adapter->eeprompriv.mac_addr[1],Adapter->eeprompriv.mac_addr[2],\ ++ Adapter->eeprompriv.mac_addr[3],Adapter->eeprompriv.mac_addr[4],Adapter->eeprompriv.mac_addr[5])); ++ } ++#endif ++ ++ return NDIS_STATUS_SUCCESS; ++} ++//------------------------------------------------------------------------------ ++NDIS_STATUS oid_rt_pro_read_efuse_hdl(struct oid_par_priv *poid_par_priv) ++{ ++ _irqL oldirql; ++ PEFUSE_ACCESS_STRUCT pefuse; ++ u8 *data; ++ u16 addr = 0, cnts = 0, max_available_size = 0; ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++_func_enter_; ++ ++ if (poid_par_priv->type_of_oid != QUERY_OID) ++ return NDIS_STATUS_NOT_ACCEPTED; ++ ++ if (poid_par_priv->information_buf_len < sizeof(EFUSE_ACCESS_STRUCT)) ++ return NDIS_STATUS_INVALID_LENGTH; ++ ++ pefuse = (PEFUSE_ACCESS_STRUCT)poid_par_priv->information_buf; ++ addr = pefuse->start_addr; ++ cnts = pefuse->cnts; ++ data = pefuse->data; ++ ++ RT_TRACE(_module_mp_, _drv_notice_, ++ ("+oid_rt_pro_read_efuse_hd: buf_len=%ld addr=%d cnts=%d\n", ++ poid_par_priv->information_buf_len, addr, cnts)); ++ ++ EFUSE_GetEfuseDefinition(Adapter, EFUSE_WIFI, TYPE_AVAILABLE_EFUSE_BYTES_TOTAL, (PVOID)&max_available_size, _FALSE); ++ ++ if ((addr + cnts) > max_available_size) { ++ RT_TRACE(_module_mp_, _drv_err_, ("!oid_rt_pro_read_efuse_hdl: parameter error!\n")); ++ return NDIS_STATUS_NOT_ACCEPTED; ++ } ++ ++ _irqlevel_changed_(&oldirql, LOWER); ++ if (rtw_efuse_access(Adapter, _FALSE, addr, cnts, data) == _FAIL) { ++ RT_TRACE(_module_mp_, _drv_err_, ("!oid_rt_pro_read_efuse_hdl: rtw_efuse_access FAIL!\n")); ++ status = NDIS_STATUS_FAILURE; ++ } else ++ *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; ++ _irqlevel_changed_(&oldirql, RAISE); ++ ++_func_exit_; ++ ++ return status; ++} ++//------------------------------------------------------------------------------ ++NDIS_STATUS oid_rt_pro_write_efuse_hdl(struct oid_par_priv *poid_par_priv) ++{ ++ ++ _irqL oldirql; ++ PEFUSE_ACCESS_STRUCT pefuse; ++ u8 *data; ++ u16 addr = 0, cnts = 0, max_available_size = 0; ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++ ++_func_enter_; ++ ++ if (poid_par_priv->type_of_oid != SET_OID) ++ return NDIS_STATUS_NOT_ACCEPTED; ++ ++ pefuse = (PEFUSE_ACCESS_STRUCT)poid_par_priv->information_buf; ++ addr = pefuse->start_addr; ++ cnts = pefuse->cnts; ++ data = pefuse->data; ++ ++ RT_TRACE(_module_mp_, _drv_notice_, ++ ("+oid_rt_pro_write_efuse_hdl: buf_len=%ld addr=0x%04x cnts=%d\n", ++ poid_par_priv->information_buf_len, addr, cnts)); ++ ++ EFUSE_GetEfuseDefinition(Adapter, EFUSE_WIFI, TYPE_AVAILABLE_EFUSE_BYTES_TOTAL, (PVOID)&max_available_size, _FALSE); ++ ++ if ((addr + cnts) > max_available_size) { ++ RT_TRACE(_module_mp_, _drv_err_, ("!oid_rt_pro_write_efuse_hdl: parameter error")); ++ return NDIS_STATUS_NOT_ACCEPTED; ++ } ++ ++ _irqlevel_changed_(&oldirql, LOWER); ++ if (rtw_efuse_access(Adapter, _TRUE, addr, cnts, data) == _FAIL) ++ status = NDIS_STATUS_FAILURE; ++ _irqlevel_changed_(&oldirql, RAISE); ++ ++_func_exit_; ++ ++ return status; ++} ++//------------------------------------------------------------------------------ ++NDIS_STATUS oid_rt_pro_rw_efuse_pgpkt_hdl(struct oid_par_priv *poid_par_priv) ++{ ++ _irqL oldirql; ++ PPGPKT_STRUCT ppgpkt; ++ u8 tmpidx; ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++_func_enter_; ++ ++// RT_TRACE(_module_mp_, _drv_info_, ("+oid_rt_pro_rw_efuse_pgpkt_hdl\n")); ++ ++ *poid_par_priv->bytes_rw = 0; ++ ++ if (poid_par_priv->information_buf_len < sizeof(PGPKT_STRUCT)) ++ return NDIS_STATUS_INVALID_LENGTH; ++ ++ ppgpkt = (PPGPKT_STRUCT)poid_par_priv->information_buf; ++ ++ _irqlevel_changed_(&oldirql, LOWER); ++ ++ if (poid_par_priv->type_of_oid == QUERY_OID) ++ { ++ RT_TRACE(_module_mp_, _drv_notice_, ++ ("oid_rt_pro_rw_efuse_pgpkt_hdl: Read offset=0x%x\n",\ ++ ppgpkt->offset)); ++ ++ Efuse_PowerSwitch(Adapter, _FALSE, _TRUE); ++ if (Efuse_PgPacketRead(Adapter, ppgpkt->offset, ppgpkt->data, _FALSE) == _TRUE) ++ *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; ++ else ++ status = NDIS_STATUS_FAILURE; ++ Efuse_PowerSwitch(Adapter, _FALSE, _FALSE); ++ } else { ++ RT_TRACE(_module_mp_, _drv_notice_, ++ ("oid_rt_pro_rw_efuse_pgpkt_hdl: Write offset=0x%x word_en=0x%x\n",\ ++ ppgpkt->offset, ppgpkt->word_en)); ++ ++ Efuse_PowerSwitch(Adapter, _TRUE, _TRUE); ++ if (Efuse_PgPacketWrite(Adapter, ppgpkt->offset, ppgpkt->word_en, ppgpkt->data, _FALSE) == _TRUE) ++ *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; ++ else ++ status = NDIS_STATUS_FAILURE; ++ Efuse_PowerSwitch(Adapter, _TRUE, _FALSE); ++ } ++ ++ _irqlevel_changed_(&oldirql, RAISE); ++ ++ RT_TRACE(_module_mp_, _drv_info_, ++ ("-oid_rt_pro_rw_efuse_pgpkt_hdl: status=0x%08X\n", status)); ++ ++_func_exit_; ++ ++ return status; ++} ++//------------------------------------------------------------------------------ ++NDIS_STATUS oid_rt_get_efuse_current_size_hdl(struct oid_par_priv *poid_par_priv) ++{ ++ _irqL oldirql; ++ u16 size; ++ u8 ret; ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++_func_enter_; ++ ++ if (poid_par_priv->type_of_oid != QUERY_OID) ++ return NDIS_STATUS_NOT_ACCEPTED; ++ ++ if (poid_par_priv->information_buf_len information_buf = size; ++ *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; ++ } else ++ status = NDIS_STATUS_FAILURE; ++ ++_func_exit_; ++ ++ return status; ++} ++//------------------------------------------------------------------------------ ++NDIS_STATUS oid_rt_get_efuse_max_size_hdl(struct oid_par_priv *poid_par_priv) ++{ ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); ++ u16 max_size; ++ ++_func_enter_; ++ ++ if (poid_par_priv->type_of_oid != QUERY_OID) ++ return NDIS_STATUS_NOT_ACCEPTED; ++ ++ if (poid_par_priv->information_buf_len < sizeof(u32)) ++ return NDIS_STATUS_INVALID_LENGTH; ++ ++ *(u32*)poid_par_priv->information_buf = efuse_GetMaxSize(Adapter); ++ *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; ++ ++ RT_TRACE(_module_mp_, _drv_info_, ++ ("-oid_rt_get_efuse_max_size_hdl: size=%d status=0x%08X\n", ++ *(int*)poid_par_priv->information_buf, status)); ++ ++_func_exit_; ++ ++ return status; ++} ++//------------------------------------------------------------------------------ ++NDIS_STATUS oid_rt_pro_efuse_hdl(struct oid_par_priv *poid_par_priv) ++{ ++ NDIS_STATUS status; ++ ++_func_enter_; ++ ++ RT_TRACE(_module_mp_, _drv_info_, ("+oid_rt_pro_efuse_hdl\n")); ++ ++ if (poid_par_priv->type_of_oid == QUERY_OID) ++ status = oid_rt_pro_read_efuse_hdl(poid_par_priv); ++ else ++ status = oid_rt_pro_write_efuse_hdl(poid_par_priv); ++ ++ RT_TRACE(_module_mp_, _drv_info_, ("-oid_rt_pro_efuse_hdl: status=0x%08X\n", status)); ++ ++_func_exit_; ++ ++ return status; ++} ++//------------------------------------------------------------------------------ ++NDIS_STATUS oid_rt_pro_efuse_map_hdl(struct oid_par_priv *poid_par_priv) ++{ ++ _irqL oldirql; ++ u8 *data; ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); ++ u16 mapLen=0; ++ ++_func_enter_; ++ ++ RT_TRACE(_module_mp_, _drv_notice_, ("+oid_rt_pro_efuse_map_hdl\n")); ++ ++ EFUSE_GetEfuseDefinition(Adapter, EFUSE_WIFI, TYPE_EFUSE_MAP_LEN, (PVOID)&mapLen, _FALSE); ++ ++ *poid_par_priv->bytes_rw = 0; ++ ++ if (poid_par_priv->information_buf_len < mapLen) ++ return NDIS_STATUS_INVALID_LENGTH; ++ ++ data = (u8*)poid_par_priv->information_buf; ++ ++ _irqlevel_changed_(&oldirql, LOWER); ++ ++ if (poid_par_priv->type_of_oid == QUERY_OID) ++ { ++ RT_TRACE(_module_mp_, _drv_info_, ++ ("oid_rt_pro_efuse_map_hdl: READ\n")); ++ ++ if (rtw_efuse_map_read(Adapter, 0, mapLen, data) == _SUCCESS) ++ *poid_par_priv->bytes_rw = mapLen; ++ else { ++ RT_TRACE(_module_mp_, _drv_err_, ++ ("oid_rt_pro_efuse_map_hdl: READ fail\n")); ++ status = NDIS_STATUS_FAILURE; ++ } ++ } else { ++ // SET_OID ++ RT_TRACE(_module_mp_, _drv_info_, ++ ("oid_rt_pro_efuse_map_hdl: WRITE\n")); ++ ++ if (rtw_efuse_map_write(Adapter, 0, mapLen, data) == _SUCCESS) ++ *poid_par_priv->bytes_rw = mapLen; ++ else { ++ RT_TRACE(_module_mp_, _drv_err_, ++ ("oid_rt_pro_efuse_map_hdl: WRITE fail\n")); ++ status = NDIS_STATUS_FAILURE; ++ } ++ } ++ ++ _irqlevel_changed_(&oldirql, RAISE); ++ ++ RT_TRACE(_module_mp_, _drv_info_, ++ ("-oid_rt_pro_efuse_map_hdl: status=0x%08X\n", status)); ++ ++_func_exit_; ++ ++ return status; ++} ++ ++NDIS_STATUS oid_rt_set_crystal_cap_hdl(struct oid_par_priv *poid_par_priv) ++{ ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++#if 0 ++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++ _irqL oldirql; ++ ++ u32 crystal_cap = 0; ++ ++_func_enter_; ++ ++ if (poid_par_priv->type_of_oid != SET_OID) ++ return NDIS_STATUS_NOT_ACCEPTED; ++ ++ if (poid_par_priv->information_buf_len information_buf);//4 ++ if (crystal_cap > 0xf) ++ return NDIS_STATUS_NOT_ACCEPTED; ++ ++ Adapter->mppriv.curr_crystalcap = crystal_cap; ++ ++ _irqlevel_changed_(&oldirql,LOWER); ++ SetCrystalCap(Adapter); ++ _irqlevel_changed_(&oldirql,RAISE); ++ ++_func_exit_; ++ ++#endif ++ return status; ++} ++ ++NDIS_STATUS oid_rt_set_rx_packet_type_hdl(struct oid_par_priv *poid_par_priv) ++{ ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); ++ _irqL oldirql; ++ u8 rx_pkt_type; ++ u32 rcr_val32; ++ ++_func_enter_; ++ ++ RT_TRACE(_module_mp_, _drv_notice_, ("+oid_rt_set_rx_packet_type_hdl\n")); ++ ++ if (poid_par_priv->type_of_oid != SET_OID) ++ return NDIS_STATUS_NOT_ACCEPTED; ++ ++ if (poid_par_priv->information_buf_len < sizeof(u8)) ++ return NDIS_STATUS_INVALID_LENGTH; ++ ++ rx_pkt_type = *((u8*)poid_par_priv->information_buf);//4 ++ ++ RT_TRACE(_module_mp_, _drv_info_, ("rx_pkt_type: %x\n",rx_pkt_type )); ++#if 0 ++ _irqlevel_changed_(&oldirql, LOWER); ++#if 0 ++ rcr_val8 = rtw_read8(Adapter, 0x10250048);//RCR ++ rcr_val8 &= ~(RCR_AB|RCR_AM|RCR_APM|RCR_AAP); ++ ++ if(rx_pkt_type == RX_PKT_BROADCAST){ ++ rcr_val8 |= (RCR_AB | RCR_ACRC32 ); ++ } ++ else if(rx_pkt_type == RX_PKT_DEST_ADDR){ ++ rcr_val8 |= (RCR_AAP| RCR_AM |RCR_ACRC32); ++ } ++ else if(rx_pkt_type == RX_PKT_PHY_MATCH){ ++ rcr_val8 |= (RCR_APM|RCR_ACRC32); ++ } ++ else{ ++ rcr_val8 &= ~(RCR_AAP|RCR_APM|RCR_AM|RCR_AB|RCR_ACRC32); ++ } ++ rtw_write8(Adapter, 0x10250048,rcr_val8); ++#else ++ rcr_val32 = rtw_read32(Adapter, RCR);//RCR = 0x10250048 ++ rcr_val32 &= ~(RCR_CBSSID|RCR_AB|RCR_AM|RCR_APM|RCR_AAP); ++#if 0 ++ if(rx_pkt_type == RX_PKT_BROADCAST){ ++ rcr_val32 |= (RCR_AB|RCR_AM|RCR_APM|RCR_AAP|RCR_ACRC32); ++ } ++ else if(rx_pkt_type == RX_PKT_DEST_ADDR){ ++ //rcr_val32 |= (RCR_CBSSID|RCR_AAP|RCR_AM|RCR_ACRC32); ++ rcr_val32 |= (RCR_CBSSID|RCR_APM|RCR_ACRC32); ++ } ++ else if(rx_pkt_type == RX_PKT_PHY_MATCH){ ++ rcr_val32 |= (RCR_APM|RCR_ACRC32); ++ //rcr_val32 |= (RCR_AAP|RCR_ACRC32); ++ } ++ else{ ++ rcr_val32 &= ~(RCR_AAP|RCR_APM|RCR_AM|RCR_AB|RCR_ACRC32); ++ } ++#else ++ switch (rx_pkt_type) ++ { ++ case RX_PKT_BROADCAST : ++ rcr_val32 |= (RCR_AB|RCR_AM|RCR_APM|RCR_AAP|RCR_ACRC32); ++ break; ++ case RX_PKT_DEST_ADDR : ++ rcr_val32 |= (RCR_AB|RCR_AM|RCR_APM|RCR_AAP|RCR_ACRC32); ++ break; ++ case RX_PKT_PHY_MATCH: ++ rcr_val32 |= (RCR_APM|RCR_ACRC32); ++ break; ++ default: ++ rcr_val32 &= ~(RCR_AAP|RCR_APM|RCR_AM|RCR_AB|RCR_ACRC32); ++ break; ++ } ++ ++ if (rx_pkt_type == RX_PKT_DEST_ADDR) { ++ Adapter->mppriv.check_mp_pkt = 1; ++ } else { ++ Adapter->mppriv.check_mp_pkt = 0; ++ } ++#endif ++ rtw_write32(Adapter, RCR, rcr_val32); ++ ++#endif ++ _irqlevel_changed_(&oldirql, RAISE); ++#endif ++_func_exit_; ++ ++ return status; ++} ++ ++NDIS_STATUS oid_rt_pro_set_tx_agc_offset_hdl(struct oid_par_priv *poid_par_priv) ++{ ++#if 0 ++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++ _irqL oldirql; ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ ++ u32 txagc; ++ ++_func_enter_; ++ ++ if (poid_par_priv->type_of_oid != SET_OID) ++ return NDIS_STATUS_NOT_ACCEPTED; ++ ++ if (poid_par_priv->information_buf_len < sizeof(u32)) ++ return NDIS_STATUS_INVALID_LENGTH; ++ ++ txagc = *(u32*)poid_par_priv->information_buf; ++ RT_TRACE(_module_mp_, _drv_info_, ++ ("oid_rt_pro_set_tx_agc_offset_hdl: 0x%08x\n", txagc)); ++ ++ _irqlevel_changed_(&oldirql, LOWER); ++ SetTxAGCOffset(Adapter, txagc); ++ _irqlevel_changed_(&oldirql, RAISE); ++ ++_func_exit_; ++ ++ return status; ++#else ++ return 0; ++#endif ++} ++ ++NDIS_STATUS oid_rt_pro_set_pkt_test_mode_hdl(struct oid_par_priv *poid_par_priv) ++{ ++#if 0 ++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); ++ ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ ++ struct mlme_priv *pmlmepriv = &Adapter->mlmepriv; ++ struct mp_priv *pmppriv = &Adapter->mppriv; ++ u32 type; ++ ++_func_enter_; ++ ++ if (poid_par_priv->type_of_oid != SET_OID) ++ return NDIS_STATUS_NOT_ACCEPTED; ++ ++ if (poid_par_priv->information_buf_len information_buf; ++ ++ if (_LOOPBOOK_MODE_ == type) { ++ pmppriv->mode = type; ++ set_fwstate(pmlmepriv, WIFI_MP_LPBK_STATE); //append txdesc ++ RT_TRACE(_module_mp_, _drv_info_, ("test mode change to loopback mode:0x%08x.\n", get_fwstate(pmlmepriv))); ++ } else if (_2MAC_MODE_ == type){ ++ pmppriv->mode = type; ++ _clr_fwstate_(pmlmepriv, WIFI_MP_LPBK_STATE); ++ RT_TRACE(_module_mp_, _drv_info_, ("test mode change to 2mac mode:0x%08x.\n", get_fwstate(pmlmepriv))); ++ } else ++ status = NDIS_STATUS_NOT_ACCEPTED; ++ ++_func_exit_; ++ ++ return status; ++#else ++ return 0; ++#endif ++} ++ ++unsigned int mp_ioctl_xmit_packet_hdl(struct oid_par_priv *poid_par_priv) ++{ ++ PMP_XMIT_PARM pparm; ++ PADAPTER padapter; ++ struct mp_priv *pmp_priv; ++ struct pkt_attrib *pattrib; ++ ++ RT_TRACE(_module_mp_, _drv_notice_, ("+%s\n", __func__)); ++ ++ pparm = (PMP_XMIT_PARM)poid_par_priv->information_buf; ++ padapter = (PADAPTER)poid_par_priv->adapter_context; ++ pmp_priv = &padapter->mppriv; ++ ++ if (poid_par_priv->type_of_oid == QUERY_OID) { ++ pparm->enable = !pmp_priv->tx.stop; ++ pparm->count = pmp_priv->tx.sended; ++ } else { ++ if (pparm->enable == 0) { ++ pmp_priv->tx.stop = 1; ++ } else if (pmp_priv->tx.stop == 1) { ++ pmp_priv->tx.stop = 0; ++ pmp_priv->tx.count = pparm->count; ++ pmp_priv->tx.payload = pparm->payload_type; ++ pattrib = &pmp_priv->tx.attrib; ++ pattrib->pktlen = pparm->length; ++ _rtw_memcpy(pattrib->dst, pparm->da, ETH_ALEN); ++ SetPacketTx(padapter); ++ } else ++ return NDIS_STATUS_FAILURE; ++ } ++ ++ return NDIS_STATUS_SUCCESS; ++} ++ ++#if 0 ++unsigned int mp_ioctl_xmit_packet_hdl(struct oid_par_priv *poid_par_priv) ++{ ++ unsigned char *pframe, *pmp_pkt; ++ struct ethhdr *pethhdr; ++ struct pkt_attrib *pattrib; ++ struct rtw_ieee80211_hdr *pwlanhdr; ++ unsigned short *fctrl; ++ int llc_sz, payload_len; ++ struct mp_xmit_frame *pxframe= NULL; ++ struct mp_xmit_packet *pmp_xmitpkt = (struct mp_xmit_packet*)param; ++ u8 addr3[] = {0x02, 0xE0, 0x4C, 0x87, 0x66, 0x55}; ++ ++// DBG_8192C("+mp_ioctl_xmit_packet_hdl\n"); ++ ++ pxframe = alloc_mp_xmitframe(&padapter->mppriv); ++ if (pxframe == NULL) ++ { ++ DEBUG_ERR(("Can't alloc pmpframe %d:%s\n", __LINE__, __FILE__)); ++ return -1; ++ } ++ ++ //mp_xmit_pkt ++ payload_len = pmp_xmitpkt->len - 14; ++ pmp_pkt = (unsigned char*)pmp_xmitpkt->mem; ++ pethhdr = (struct ethhdr *)pmp_pkt; ++ ++ //DBG_8192C("payload_len=%d, pkt_mem=0x%x\n", pmp_xmitpkt->len, (void*)pmp_xmitpkt->mem); ++ ++ //DBG_8192C("pxframe=0x%x\n", (void*)pxframe); ++ //DBG_8192C("pxframe->mem=0x%x\n", (void*)pxframe->mem); ++ ++ //update attribute ++ pattrib = &pxframe->attrib; ++ memset((u8 *)(pattrib), 0, sizeof (struct pkt_attrib)); ++ pattrib->pktlen = pmp_xmitpkt->len; ++ pattrib->ether_type = ntohs(pethhdr->h_proto); ++ pattrib->hdrlen = 24; ++ pattrib->nr_frags = 1; ++ pattrib->priority = 0; ++#ifndef CONFIG_MP_LINUX ++ if(IS_MCAST(pethhdr->h_dest)) ++ pattrib->mac_id = 4; ++ else ++ pattrib->mac_id = 5; ++#else ++ pattrib->mac_id = 5; ++#endif ++ ++ // ++ memset(pxframe->mem, 0 , WLANHDR_OFFSET); ++ pframe = (u8 *)(pxframe->mem) + WLANHDR_OFFSET; ++ ++ pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; ++ ++ fctrl = &(pwlanhdr->frame_ctl); ++ *(fctrl) = 0; ++ SetFrameSubType(pframe, WIFI_DATA); ++ ++ _rtw_memcpy(pwlanhdr->addr1, pethhdr->h_dest, ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr2, pethhdr->h_source, ETH_ALEN); ++ ++ _rtw_memcpy(pwlanhdr->addr3, addr3, ETH_ALEN); ++ ++ pwlanhdr->seq_ctl = 0; ++ pframe += pattrib->hdrlen; ++ ++ llc_sz= rtw_put_snap(pframe, pattrib->ether_type); ++ pframe += llc_sz; ++ ++ _rtw_memcpy(pframe, (void*)(pmp_pkt+14), payload_len); ++ ++ pattrib->last_txcmdsz = pattrib->hdrlen + llc_sz + payload_len; ++ ++ DEBUG_INFO(("issuing mp_xmit_frame, tx_len=%d, ether_type=0x%x\n", pattrib->last_txcmdsz, pattrib->ether_type)); ++ xmit_mp_frame(padapter, pxframe); ++ ++ return _SUCCESS; ++} ++#endif ++//------------------------------------------------------------------------------ ++NDIS_STATUS oid_rt_set_power_down_hdl(struct oid_par_priv *poid_par_priv) ++{ ++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ _irqL oldirql; ++ u8 bpwrup; ++ ++_func_enter_; ++ ++ if (poid_par_priv->type_of_oid != SET_OID) { ++ status = NDIS_STATUS_NOT_ACCEPTED; ++ return status; ++ } ++ ++ RT_TRACE(_module_mp_, _drv_info_, ++ ("\n ===> Setoid_rt_set_power_down_hdl.\n")); ++ ++ _irqlevel_changed_(&oldirql, LOWER); ++ ++ bpwrup = *(u8 *)poid_par_priv->information_buf; ++ //CALL the power_down function ++#ifdef PLATFORM_LINUX ++#ifdef CONFIG_SDIO_HCI ++ dev_power_down(Adapter,bpwrup); ++#endif ++#endif ++ _irqlevel_changed_(&oldirql, RAISE); ++ ++ //DEBUG_ERR(("\n <=== Query OID_RT_PRO_READ_REGISTER. ++ // Add:0x%08x Width:%d Value:0x%08x\n",RegRWStruct->offset,RegRWStruct->width,RegRWStruct->value)); ++ ++_func_exit_; ++ ++ return status; ++} ++//------------------------------------------------------------------------------ ++NDIS_STATUS oid_rt_get_power_mode_hdl(struct oid_par_priv *poid_par_priv) ++{ ++#if 0 ++ NDIS_STATUS status = NDIS_STATUS_SUCCESS; ++ PADAPTER Adapter = (PADAPTER)(poid_par_priv->adapter_context); ++// _irqL oldirql; ++ ++_func_enter_; ++ ++ if (poid_par_priv->type_of_oid != QUERY_OID) { ++ status = NDIS_STATUS_NOT_ACCEPTED; ++ return status; ++ } ++ if (poid_par_priv->information_buf_len < sizeof(u32)) { ++ status = NDIS_STATUS_INVALID_LENGTH; ++ return status; ++ } ++ ++ RT_TRACE(_module_mp_, _drv_info_, ++ ("\n ===> oid_rt_get_power_mode_hdl.\n")); ++ ++// _irqlevel_changed_(&oldirql, LOWER); ++ *(int*)poid_par_priv->information_buf = Adapter->registrypriv.low_power ? POWER_LOW : POWER_NORMAL; ++ *poid_par_priv->bytes_rw = poid_par_priv->information_buf_len; ++// _irqlevel_changed_(&oldirql, RAISE); ++ ++_func_exit_; ++ ++ return status; ++#else ++ return 0; ++#endif ++} ++ +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/core/rtw_p2p.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/core/rtw_p2p.c 2013-07-26 19:36:05.000000000 +0000 +@@ -0,0 +1,3498 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#define _RTW_P2P_C_ ++ ++#include ++#include ++#include ++ ++#ifdef CONFIG_P2P ++ ++int is_any_client_associated( _adapter *padapter ) ++{ ++ _irqL irqL; ++ _list *phead, *plist; ++ int intFound = _FALSE; ++ ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ ++ _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL); ++ phead = &pstapriv->asoc_list; ++ plist = get_next(phead); ++ ++ if ( rtw_end_of_queue_search(phead, plist) == _TRUE ) ++ { ++ intFound = _FALSE; ++ } ++ else ++ { ++ intFound = _TRUE; ++ } ++ ++ _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL); ++ ++ return( intFound ); ++ ++} ++ ++static u32 go_add_group_info_attr(struct wifidirect_info *pwdinfo, u8 *pbuf) ++{ ++ _irqL irqL; ++ _list *phead, *plist; ++ u32 len=0; ++ u16 attr_len = 0; ++ u8 tmplen, *pdata_attr, *pstart, *pcur; ++ struct sta_info *psta = NULL; ++ _adapter *padapter = pwdinfo->padapter; ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ ++ DBG_871X("%s\n", __FUNCTION__); ++ ++ pdata_attr = rtw_zmalloc(MAX_P2P_IE_LEN); ++ ++ pstart = pdata_attr; ++ pcur = pdata_attr; ++ ++ _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL); ++ phead = &pstapriv->asoc_list; ++ plist = get_next(phead); ++ ++ //look up sta asoc_queue ++ while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) ++ { ++ psta = LIST_CONTAINOR(plist, struct sta_info, asoc_list); ++ ++ plist = get_next(plist); ++ ++ ++ if(psta->is_p2p_device) ++ { ++ tmplen = 0; ++ ++ pcur++; ++ ++ //P2P device address ++ _rtw_memcpy(pcur, psta->dev_addr, ETH_ALEN); ++ pcur += ETH_ALEN; ++ ++ //P2P interface address ++ _rtw_memcpy(pcur, psta->hwaddr, ETH_ALEN); ++ pcur += ETH_ALEN; ++ ++ *pcur = psta->dev_cap; ++ pcur++; ++ ++ //*(u16*)(pcur) = cpu_to_be16(psta->config_methods); ++ RTW_PUT_BE16(pcur, psta->config_methods); ++ pcur += 2; ++ ++ _rtw_memcpy(pcur, psta->primary_dev_type, 8); ++ pcur += 8; ++ ++ *pcur = psta->num_of_secdev_type; ++ pcur++; ++ ++ _rtw_memcpy(pcur, psta->secdev_types_list, psta->num_of_secdev_type*8); ++ pcur += psta->num_of_secdev_type*8; ++ ++ if(psta->dev_name_len>0) ++ { ++ //*(u16*)(pcur) = cpu_to_be16( WPS_ATTR_DEVICE_NAME ); ++ RTW_PUT_BE16(pcur, WPS_ATTR_DEVICE_NAME); ++ pcur += 2; ++ ++ //*(u16*)(pcur) = cpu_to_be16( psta->dev_name_len ); ++ RTW_PUT_BE16(pcur, psta->dev_name_len); ++ pcur += 2; ++ ++ _rtw_memcpy(pcur, psta->dev_name, psta->dev_name_len); ++ pcur += psta->dev_name_len; ++ } ++ ++ ++ tmplen = (u8)(pcur-pstart); ++ ++ *pstart = (tmplen-1); ++ ++ attr_len += tmplen; ++ ++ //pstart += tmplen; ++ pstart = pcur; ++ ++ } ++ ++ ++ } ++ _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL); ++ ++ if(attr_len>0) ++ { ++ len = rtw_set_p2p_attr_content(pbuf, P2P_ATTR_GROUP_INFO, attr_len, pdata_attr); ++ } ++ ++ rtw_mfree(pdata_attr, MAX_P2P_IE_LEN); ++ ++ return len; ++ ++} ++ ++static void issue_group_disc_req(struct wifidirect_info *pwdinfo, u8 *da) ++{ ++ struct xmit_frame *pmgntframe; ++ struct pkt_attrib *pattrib; ++ unsigned char *pframe; ++ struct rtw_ieee80211_hdr *pwlanhdr; ++ unsigned short *fctrl; ++ _adapter *padapter = pwdinfo->padapter; ++ struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); ++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); ++ unsigned char category = RTW_WLAN_CATEGORY_P2P;//P2P action frame ++ u32 p2poui = cpu_to_be32(P2POUI); ++ u8 oui_subtype = P2P_GO_DISC_REQUEST; ++ u8 dialogToken=0; ++ ++ DBG_871X("[%s]\n", __FUNCTION__); ++ ++ if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL) ++ { ++ return; ++ } ++ ++ //update attribute ++ pattrib = &pmgntframe->attrib; ++ update_mgntframe_attrib(padapter, pattrib); ++ ++ _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); ++ ++ pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; ++ pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; ++ ++ fctrl = &(pwlanhdr->frame_ctl); ++ *(fctrl) = 0; ++ ++ _rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr2, pwdinfo->interface_addr, ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr3, pwdinfo->interface_addr, ETH_ALEN); ++ ++ SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); ++ pmlmeext->mgnt_seq++; ++ SetFrameSubType(pframe, WIFI_ACTION); ++ ++ pframe += sizeof(struct rtw_ieee80211_hdr_3addr); ++ pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); ++ ++ //Build P2P action frame header ++ pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen)); ++ pframe = rtw_set_fixed_ie(pframe, 4, (unsigned char *) &(p2poui), &(pattrib->pktlen)); ++ pframe = rtw_set_fixed_ie(pframe, 1, &(oui_subtype), &(pattrib->pktlen)); ++ pframe = rtw_set_fixed_ie(pframe, 1, &(dialogToken), &(pattrib->pktlen)); ++ ++ //there is no IE in this P2P action frame ++ ++ pattrib->last_txcmdsz = pattrib->pktlen; ++ ++ dump_mgntframe(padapter, pmgntframe); ++ ++} ++ ++static void issue_p2p_devdisc_resp(struct wifidirect_info *pwdinfo, u8 *da, u8 status, u8 dialogToken) ++{ ++ struct xmit_frame *pmgntframe; ++ struct pkt_attrib *pattrib; ++ unsigned char *pframe; ++ struct rtw_ieee80211_hdr *pwlanhdr; ++ unsigned short *fctrl; ++ _adapter *padapter = pwdinfo->padapter; ++ struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); ++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); ++ unsigned char category = RTW_WLAN_CATEGORY_PUBLIC; ++ u8 action = P2P_PUB_ACTION_ACTION; ++ u32 p2poui = cpu_to_be32(P2POUI); ++ u8 oui_subtype = P2P_DEVDISC_RESP; ++ u8 p2pie[8] = { 0x00 }; ++ u32 p2pielen = 0; ++ ++ DBG_871X("[%s]\n", __FUNCTION__); ++ ++ if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL) ++ { ++ return; ++ } ++ ++ //update attribute ++ pattrib = &pmgntframe->attrib; ++ update_mgntframe_attrib(padapter, pattrib); ++ ++ _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); ++ ++ pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; ++ pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; ++ ++ fctrl = &(pwlanhdr->frame_ctl); ++ *(fctrl) = 0; ++ ++ _rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr2, pwdinfo->device_addr, ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr3, pwdinfo->device_addr, ETH_ALEN); ++ ++ SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); ++ pmlmeext->mgnt_seq++; ++ SetFrameSubType(pframe, WIFI_ACTION); ++ ++ pframe += sizeof(struct rtw_ieee80211_hdr_3addr); ++ pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); ++ ++ //Build P2P public action frame header ++ pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen)); ++ pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen)); ++ pframe = rtw_set_fixed_ie(pframe, 4, (unsigned char *) &(p2poui), &(pattrib->pktlen)); ++ pframe = rtw_set_fixed_ie(pframe, 1, &(oui_subtype), &(pattrib->pktlen)); ++ pframe = rtw_set_fixed_ie(pframe, 1, &(dialogToken), &(pattrib->pktlen)); ++ ++ ++ //Build P2P IE ++ // P2P OUI ++ p2pielen = 0; ++ p2pie[ p2pielen++ ] = 0x50; ++ p2pie[ p2pielen++ ] = 0x6F; ++ p2pie[ p2pielen++ ] = 0x9A; ++ p2pie[ p2pielen++ ] = 0x09; // WFA P2P v1.0 ++ ++ // P2P_ATTR_STATUS ++ p2pielen += rtw_set_p2p_attr_content(&p2pie[p2pielen], P2P_ATTR_STATUS, 1, &status); ++ ++ pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, p2pielen, p2pie, &pattrib->pktlen); ++ ++ pattrib->last_txcmdsz = pattrib->pktlen; ++ ++ dump_mgntframe(padapter, pmgntframe); ++ ++} ++ ++static void issue_p2p_provision_resp(struct wifidirect_info *pwdinfo, u8* raddr, u8* frame_body, u16 config_method) ++{ ++ _adapter *padapter = pwdinfo->padapter; ++ unsigned char category = RTW_WLAN_CATEGORY_PUBLIC; ++ u8 action = P2P_PUB_ACTION_ACTION; ++ u8 dialogToken = frame_body[7]; // The Dialog Token of provisioning discovery request frame. ++ u32 p2poui = cpu_to_be32(P2POUI); ++ u8 oui_subtype = P2P_PROVISION_DISC_RESP; ++ u8 wpsie[ 100 ] = { 0x00 }; ++ u8 wpsielen = 0; ++#ifdef CONFIG_WFD ++ u32 wfdielen = 0; ++#endif //CONFIG_WFD ++ ++ struct xmit_frame *pmgntframe; ++ struct pkt_attrib *pattrib; ++ unsigned char *pframe; ++ struct rtw_ieee80211_hdr *pwlanhdr; ++ unsigned short *fctrl; ++ struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); ++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ ++ ++ if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL) ++ { ++ return; ++ } ++ ++ //update attribute ++ pattrib = &pmgntframe->attrib; ++ update_mgntframe_attrib(padapter, pattrib); ++ ++ _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); ++ ++ pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; ++ pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; ++ ++ fctrl = &(pwlanhdr->frame_ctl); ++ *(fctrl) = 0; ++ ++ _rtw_memcpy(pwlanhdr->addr1, raddr, ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr2, myid(&(padapter->eeprompriv)), ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr3, myid(&(padapter->eeprompriv)), ETH_ALEN); ++ ++ SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); ++ pmlmeext->mgnt_seq++; ++ SetFrameSubType(pframe, WIFI_ACTION); ++ ++ pframe += sizeof(struct rtw_ieee80211_hdr_3addr); ++ pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); ++ ++ pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen)); ++ pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen)); ++ pframe = rtw_set_fixed_ie(pframe, 4, (unsigned char *) &(p2poui), &(pattrib->pktlen)); ++ pframe = rtw_set_fixed_ie(pframe, 1, &(oui_subtype), &(pattrib->pktlen)); ++ pframe = rtw_set_fixed_ie(pframe, 1, &(dialogToken), &(pattrib->pktlen)); ++ ++ wpsielen = 0; ++ // WPS OUI ++ //*(u32*) ( wpsie ) = cpu_to_be32( WPSOUI ); ++ RTW_PUT_BE32(wpsie, WPSOUI); ++ wpsielen += 4; ++ ++#if 0 ++ // WPS version ++ // Type: ++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_ATTR_VER1 ); ++ wpsielen += 2; ++ ++ // Length: ++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( 0x0001 ); ++ wpsielen += 2; ++ ++ // Value: ++ wpsie[wpsielen++] = WPS_VERSION_1; // Version 1.0 ++#endif ++ ++ // Config Method ++ // Type: ++ //*(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_ATTR_CONF_METHOD ); ++ RTW_PUT_BE16(wpsie + wpsielen, WPS_ATTR_CONF_METHOD); ++ wpsielen += 2; ++ ++ // Length: ++ //*(u16*) ( wpsie + wpsielen ) = cpu_to_be16( 0x0002 ); ++ RTW_PUT_BE16(wpsie + wpsielen, 0x0002); ++ wpsielen += 2; ++ ++ // Value: ++ //*(u16*) ( wpsie + wpsielen ) = cpu_to_be16( config_method ); ++ RTW_PUT_BE16(wpsie + wpsielen, config_method); ++ wpsielen += 2; ++ ++ pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, wpsielen, (unsigned char *) wpsie, &pattrib->pktlen ); ++ ++#ifdef CONFIG_WFD ++ wfdielen = build_provdisc_resp_wfd_ie(pwdinfo, pframe); ++ pframe += wfdielen; ++ pattrib->pktlen += wfdielen; ++#endif //CONFIG_WFD ++ ++ pattrib->last_txcmdsz = pattrib->pktlen; ++ ++ dump_mgntframe(padapter, pmgntframe); ++ ++ return; ++ ++} ++ ++static void issue_p2p_presence_resp(struct wifidirect_info *pwdinfo, u8 *da, u8 status, u8 dialogToken) ++{ ++ struct xmit_frame *pmgntframe; ++ struct pkt_attrib *pattrib; ++ unsigned char *pframe; ++ struct rtw_ieee80211_hdr *pwlanhdr; ++ unsigned short *fctrl; ++ _adapter *padapter = pwdinfo->padapter; ++ struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); ++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); ++ unsigned char category = RTW_WLAN_CATEGORY_P2P;//P2P action frame ++ u32 p2poui = cpu_to_be32(P2POUI); ++ u8 oui_subtype = P2P_PRESENCE_RESPONSE; ++ u8 p2pie[ MAX_P2P_IE_LEN] = { 0x00 }; ++ u8 noa_attr_content[32] = { 0x00 }; ++ u32 p2pielen = 0; ++ ++ DBG_871X("[%s]\n", __FUNCTION__); ++ ++ if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL) ++ { ++ return; ++ } ++ ++ //update attribute ++ pattrib = &pmgntframe->attrib; ++ update_mgntframe_attrib(padapter, pattrib); ++ ++ _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); ++ ++ pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; ++ pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; ++ ++ fctrl = &(pwlanhdr->frame_ctl); ++ *(fctrl) = 0; ++ ++ _rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr2, pwdinfo->interface_addr, ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr3, pwdinfo->interface_addr, ETH_ALEN); ++ ++ SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); ++ pmlmeext->mgnt_seq++; ++ SetFrameSubType(pframe, WIFI_ACTION); ++ ++ pframe += sizeof(struct rtw_ieee80211_hdr_3addr); ++ pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); ++ ++ //Build P2P action frame header ++ pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen)); ++ pframe = rtw_set_fixed_ie(pframe, 4, (unsigned char *) &(p2poui), &(pattrib->pktlen)); ++ pframe = rtw_set_fixed_ie(pframe, 1, &(oui_subtype), &(pattrib->pktlen)); ++ pframe = rtw_set_fixed_ie(pframe, 1, &(dialogToken), &(pattrib->pktlen)); ++ ++ ++ //Add P2P IE header ++ // P2P OUI ++ p2pielen = 0; ++ p2pie[ p2pielen++ ] = 0x50; ++ p2pie[ p2pielen++ ] = 0x6F; ++ p2pie[ p2pielen++ ] = 0x9A; ++ p2pie[ p2pielen++ ] = 0x09; // WFA P2P v1.0 ++ ++ //Add Status attribute in P2P IE ++ p2pielen += rtw_set_p2p_attr_content(&p2pie[p2pielen], P2P_ATTR_STATUS, 1, &status); ++ ++ //Add NoA attribute in P2P IE ++ noa_attr_content[0] = 0x1;//index ++ noa_attr_content[1] = 0x0;//CTWindow and OppPS Parameters ++ ++ //todo: Notice of Absence Descriptor(s) ++ ++ p2pielen += rtw_set_p2p_attr_content(&p2pie[p2pielen], P2P_ATTR_NOA, 2, noa_attr_content); ++ ++ ++ ++ pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, p2pielen, p2pie, &(pattrib->pktlen)); ++ ++ ++ pattrib->last_txcmdsz = pattrib->pktlen; ++ ++ dump_mgntframe(padapter, pmgntframe); ++ ++} ++ ++u32 build_beacon_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pbuf) ++{ ++ u8 p2pie[ MAX_P2P_IE_LEN] = { 0x00 }; ++ u16 capability=0; ++ u32 len=0, p2pielen = 0; ++ ++ ++ // P2P OUI ++ p2pielen = 0; ++ p2pie[ p2pielen++ ] = 0x50; ++ p2pie[ p2pielen++ ] = 0x6F; ++ p2pie[ p2pielen++ ] = 0x9A; ++ p2pie[ p2pielen++ ] = 0x09; // WFA P2P v1.0 ++ ++ ++ // According to the P2P Specification, the beacon frame should contain 3 P2P attributes ++ // 1. P2P Capability ++ // 2. P2P Device ID ++ // 3. Notice of Absence ( NOA ) ++ ++ // P2P Capability ATTR ++ // Type: ++ // Length: ++ // Value: ++ // Device Capability Bitmap, 1 byte ++ // Be able to participate in additional P2P Groups and ++ // support the P2P Invitation Procedure ++ // Group Capability Bitmap, 1 byte ++ capability = P2P_DEVCAP_INVITATION_PROC|P2P_DEVCAP_CLIENT_DISCOVERABILITY; ++ capability |= ((P2P_GRPCAP_GO | P2P_GRPCAP_INTRABSS) << 8); ++ if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_PROVISIONING_ING)) ++ capability |= (P2P_GRPCAP_GROUP_FORMATION<<8); ++ ++ capability = cpu_to_le16(capability); ++ ++ p2pielen += rtw_set_p2p_attr_content(&p2pie[p2pielen], P2P_ATTR_CAPABILITY, 2, (u8*)&capability); ++ ++ ++ // P2P Device ID ATTR ++ p2pielen += rtw_set_p2p_attr_content(&p2pie[p2pielen], P2P_ATTR_DEVICE_ID, ETH_ALEN, pwdinfo->device_addr); ++ ++ ++ // Notice of Absence ATTR ++ // Type: ++ // Length: ++ // Value: ++ ++ //go_add_noa_attr(pwdinfo); ++ ++ ++ pbuf = rtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, p2pielen, (unsigned char *) p2pie, &len); ++ ++ ++ return len; ++ ++} ++ ++#ifdef CONFIG_WFD ++u32 build_beacon_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf) ++{ ++ u8 wfdie[ MAX_WFD_IE_LEN] = { 0x00 }; ++ u32 len=0, wfdielen = 0; ++ _adapter *padapter = pwdinfo->padapter; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct wifi_display_info* pwfd_info = &padapter->wdinfo.wfd_info; ++ ++ // WFD OUI ++ wfdielen = 0; ++ wfdie[ wfdielen++ ] = 0x50; ++ wfdie[ wfdielen++ ] = 0x6F; ++ wfdie[ wfdielen++ ] = 0x9A; ++ wfdie[ wfdielen++ ] = 0x0A; // WFA WFD v1.0 ++ ++ // Commented by Albert 20110812 ++ // According to the WFD Specification, the beacon frame should contain 4 WFD attributes ++ // 1. WFD Device Information ++ // 2. Associated BSSID ++ // 3. Coupled Sink Information ++ ++ ++ // WFD Device Information ATTR ++ // Type: ++ wfdie[ wfdielen++ ] = WFD_ATTR_DEVICE_INFO; ++ ++ // Length: ++ // Note: In the WFD specification, the size of length field is 2. ++ RTW_PUT_BE16(wfdie + wfdielen, 0x0006); ++ wfdielen += 2; ++ ++ // Value1: ++ // WFD device information ++ ++ if ( rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) ++ { ++ if ( is_any_client_associated( pwdinfo->padapter ) ) ++ { ++ // WFD primary sink + WiFi Direct mode ++ RTW_PUT_BE16(wfdie + wfdielen, 0x0001); ++ } ++ else ++ { ++ // WFD primary sink + available for WFD session + WiFi Direct mode ++ RTW_PUT_BE16(wfdie + wfdielen, 0x0011); ++ } ++ ++ } ++ else ++ { ++ // WFD primary sink + available for WFD session + WiFi Direct mode ++ RTW_PUT_BE16(wfdie + wfdielen, 0x0011); ++ } ++ ++ wfdielen += 2; ++ ++ // Value2: ++ // Session Management Control Port ++ // Default TCP port for RTSP messages is 554 ++ RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->rtsp_ctrlport ); ++ wfdielen += 2; ++ ++ // Value3: ++ // WFD Device Maximum Throughput ++ // 300Mbps is the maximum throughput ++ RTW_PUT_BE16(wfdie + wfdielen, 300); ++ wfdielen += 2; ++ ++ // Associated BSSID ATTR ++ // Type: ++ wfdie[ wfdielen++ ] = WFD_ATTR_ASSOC_BSSID; ++ ++ // Length: ++ // Note: In the WFD specification, the size of length field is 2. ++ RTW_PUT_BE16(wfdie + wfdielen, 0x0006); ++ wfdielen += 2; ++ ++ // Value: ++ // Associated BSSID ++ if ( check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE ) ++ { ++ _rtw_memcpy( wfdie + wfdielen, &pmlmepriv->assoc_bssid[ 0 ], ETH_ALEN ); ++ } ++ else ++ { ++ _rtw_memset( wfdie + wfdielen, 0x00, ETH_ALEN ); ++ } ++ ++ wfdielen += ETH_ALEN; ++ ++ // Coupled Sink Information ATTR ++ // Type: ++ wfdie[ wfdielen++ ] = WFD_ATTR_COUPLED_SINK_INFO; ++ ++ // Length: ++ // Note: In the WFD specification, the size of length field is 2. ++ RTW_PUT_BE16(wfdie + wfdielen, 0x0001); ++ wfdielen += 2; ++ ++ // Value: ++ // Coupled Sink Status bitmap ++ // Not coupled/available for Coupling ++ wfdie[ wfdielen++ ] = 0; ++ ++ pbuf = rtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, wfdielen, (unsigned char *) wfdie, &len); ++ ++ return len; ++ ++} ++ ++u32 build_probe_req_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf) ++{ ++ u8 wfdie[ MAX_WFD_IE_LEN] = { 0x00 }; ++ u32 len=0, wfdielen = 0; ++ _adapter *padapter = pwdinfo->padapter; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct wifi_display_info* pwfd_info = &padapter->wdinfo.wfd_info; ++ ++ // WFD OUI ++ wfdielen = 0; ++ wfdie[ wfdielen++ ] = 0x50; ++ wfdie[ wfdielen++ ] = 0x6F; ++ wfdie[ wfdielen++ ] = 0x9A; ++ wfdie[ wfdielen++ ] = 0x0A; // WFA WFD v1.0 ++ ++ // Commented by Albert 20110812 ++ // According to the WFD Specification, the probe request frame should contain 4 WFD attributes ++ // 1. WFD Device Information ++ // 2. Associated BSSID ++ // 3. Coupled Sink Information ++ ++ ++ // WFD Device Information ATTR ++ // Type: ++ wfdie[ wfdielen++ ] = WFD_ATTR_DEVICE_INFO; ++ ++ // Length: ++ // Note: In the WFD specification, the size of length field is 2. ++ RTW_PUT_BE16(wfdie + wfdielen, 0x0006); ++ wfdielen += 2; ++ ++ // Value1: ++ // WFD device information ++ // WFD primary sink + available for WFD session + WiFi Direct mode ++ RTW_PUT_BE16(wfdie + wfdielen, 0x0011); ++ wfdielen += 2; ++ ++ // Value2: ++ // Session Management Control Port ++ // Default TCP port for RTSP messages is 554 ++ RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->rtsp_ctrlport ); ++ wfdielen += 2; ++ ++ // Value3: ++ // WFD Device Maximum Throughput ++ // 300Mbps is the maximum throughput ++ RTW_PUT_BE16(wfdie + wfdielen, 300); ++ wfdielen += 2; ++ ++ // Associated BSSID ATTR ++ // Type: ++ wfdie[ wfdielen++ ] = WFD_ATTR_ASSOC_BSSID; ++ ++ // Length: ++ // Note: In the WFD specification, the size of length field is 2. ++ RTW_PUT_BE16(wfdie + wfdielen, 0x0006); ++ wfdielen += 2; ++ ++ // Value: ++ // Associated BSSID ++ if ( check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE ) ++ { ++ _rtw_memcpy( wfdie + wfdielen, &pmlmepriv->assoc_bssid[ 0 ], ETH_ALEN ); ++ } ++ else ++ { ++ _rtw_memset( wfdie + wfdielen, 0x00, ETH_ALEN ); ++ } ++ ++ wfdielen += ETH_ALEN; ++ ++ // Coupled Sink Information ATTR ++ // Type: ++ wfdie[ wfdielen++ ] = WFD_ATTR_COUPLED_SINK_INFO; ++ ++ // Length: ++ // Note: In the WFD specification, the size of length field is 2. ++ RTW_PUT_BE16(wfdie + wfdielen, 0x0001); ++ wfdielen += 2; ++ ++ // Value: ++ // Coupled Sink Status bitmap ++ // Not coupled/available for Coupling ++ wfdie[ wfdielen++ ] = 0; ++ ++ pbuf = rtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, wfdielen, (unsigned char *) wfdie, &len); ++ ++ return len; ++ ++} ++ ++u32 build_probe_resp_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf) ++{ ++ u8 wfdie[ MAX_WFD_IE_LEN] = { 0x00 }; ++ u32 len=0, wfdielen = 0; ++ _adapter *padapter = pwdinfo->padapter; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct wifi_display_info* pwfd_info = &padapter->wdinfo.wfd_info; ++ ++ // WFD OUI ++ wfdielen = 0; ++ wfdie[ wfdielen++ ] = 0x50; ++ wfdie[ wfdielen++ ] = 0x6F; ++ wfdie[ wfdielen++ ] = 0x9A; ++ wfdie[ wfdielen++ ] = 0x0A; // WFA WFD v1.0 ++ ++ // Commented by Albert 20110812 ++ // According to the WFD Specification, the probe response frame should contain 4 WFD attributes ++ // 1. WFD Device Information ++ // 2. Associated BSSID ++ // 3. Coupled Sink Information ++ // 4. WFD Session Information ++ ++ ++ // WFD Device Information ATTR ++ // Type: ++ wfdie[ wfdielen++ ] = WFD_ATTR_DEVICE_INFO; ++ ++ // Length: ++ // Note: In the WFD specification, the size of length field is 2. ++ RTW_PUT_BE16(wfdie + wfdielen, 0x0006); ++ wfdielen += 2; ++ ++ // Value1: ++ // WFD device information ++ ++ if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) ++ { ++ if ( is_any_client_associated( pwdinfo->padapter ) ) ++ { ++ // WFD primary sink + WiFi Direct mode ++ RTW_PUT_BE16(wfdie + wfdielen, 0x0001); ++ } ++ else ++ { ++ // WFD primary sink + available for WFD session + WiFi Direct mode ++ RTW_PUT_BE16(wfdie + wfdielen, 0x0011); ++ } ++ ++ } ++ else ++ { ++ // WFD primary sink + available for WFD session + WiFi Direct mode ++ RTW_PUT_BE16(wfdie + wfdielen, 0x0011); ++ } ++ ++ wfdielen += 2; ++ ++ // Value2: ++ // Session Management Control Port ++ // Default TCP port for RTSP messages is 554 ++ RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->rtsp_ctrlport ); ++ wfdielen += 2; ++ ++ // Value3: ++ // WFD Device Maximum Throughput ++ // 300Mbps is the maximum throughput ++ RTW_PUT_BE16(wfdie + wfdielen, 300); ++ wfdielen += 2; ++ ++ // Associated BSSID ATTR ++ // Type: ++ wfdie[ wfdielen++ ] = WFD_ATTR_ASSOC_BSSID; ++ ++ // Length: ++ // Note: In the WFD specification, the size of length field is 2. ++ RTW_PUT_BE16(wfdie + wfdielen, 0x0006); ++ wfdielen += 2; ++ ++ // Value: ++ // Associated BSSID ++ if ( check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE ) ++ { ++ _rtw_memcpy( wfdie + wfdielen, &pmlmepriv->assoc_bssid[ 0 ], ETH_ALEN ); ++ } ++ else ++ { ++ _rtw_memset( wfdie + wfdielen, 0x00, ETH_ALEN ); ++ } ++ ++ wfdielen += ETH_ALEN; ++ ++ // Coupled Sink Information ATTR ++ // Type: ++ wfdie[ wfdielen++ ] = WFD_ATTR_COUPLED_SINK_INFO; ++ ++ // Length: ++ // Note: In the WFD specification, the size of length field is 2. ++ RTW_PUT_BE16(wfdie + wfdielen, 0x0001); ++ wfdielen += 2; ++ ++ // Value: ++ // Coupled Sink Status bitmap ++ // Not coupled/available for Coupling ++ wfdie[ wfdielen++ ] = 0; ++ ++ if ( rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO) ) ++ { ++ // WFD Session Information ATTR ++ // Type: ++ wfdie[ wfdielen++ ] = WFD_ATTR_SESSION_INFO; ++ ++ // Length: ++ // Note: In the WFD specification, the size of length field is 2. ++ RTW_PUT_BE16(wfdie + wfdielen, 0x0000); ++ wfdielen += 2; ++ ++ // Todo: to add the list of WFD device info descriptor in WFD group. ++ ++ } ++ ++ pbuf = rtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, wfdielen, (unsigned char *) wfdie, &len); ++ ++ return len; ++ ++} ++ ++u32 build_assoc_req_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf) ++{ ++ u8 wfdie[ MAX_WFD_IE_LEN] = { 0x00 }; ++ u32 len=0, wfdielen = 0; ++ _adapter *padapter = NULL; ++ struct mlme_priv *pmlmepriv = NULL; ++ struct wifi_display_info *pwfd_info = NULL; ++ ++ // WFD OUI ++ if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE) || rtw_p2p_chk_state(pwdinfo, P2P_STATE_IDLE)) ++ { ++ return 0; ++ } ++ ++ padapter = pwdinfo->padapter; ++ pmlmepriv = &padapter->mlmepriv; ++ pwfd_info = &padapter->wdinfo.wfd_info; ++ ++ wfdielen = 0; ++ wfdie[ wfdielen++ ] = 0x50; ++ wfdie[ wfdielen++ ] = 0x6F; ++ wfdie[ wfdielen++ ] = 0x9A; ++ wfdie[ wfdielen++ ] = 0x0A; // WFA WFD v1.0 ++ ++ // Commented by Albert 20110812 ++ // According to the WFD Specification, the probe request frame should contain 4 WFD attributes ++ // 1. WFD Device Information ++ // 2. Associated BSSID ++ // 3. Coupled Sink Information ++ ++ ++ // WFD Device Information ATTR ++ // Type: ++ wfdie[ wfdielen++ ] = WFD_ATTR_DEVICE_INFO; ++ ++ // Length: ++ // Note: In the WFD specification, the size of length field is 2. ++ RTW_PUT_BE16(wfdie + wfdielen, 0x0006); ++ wfdielen += 2; ++ ++ // Value1: ++ // WFD device information ++ // WFD primary sink + available for WFD session + WiFi Direct mode ++ RTW_PUT_BE16(wfdie + wfdielen, 0x0011); ++ wfdielen += 2; ++ ++ // Value2: ++ // Session Management Control Port ++ // Default TCP port for RTSP messages is 554 ++ RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->rtsp_ctrlport ); ++ wfdielen += 2; ++ ++ // Value3: ++ // WFD Device Maximum Throughput ++ // 300Mbps is the maximum throughput ++ RTW_PUT_BE16(wfdie + wfdielen, 300); ++ wfdielen += 2; ++ ++ // Associated BSSID ATTR ++ // Type: ++ wfdie[ wfdielen++ ] = WFD_ATTR_ASSOC_BSSID; ++ ++ // Length: ++ // Note: In the WFD specification, the size of length field is 2. ++ RTW_PUT_BE16(wfdie + wfdielen, 0x0006); ++ wfdielen += 2; ++ ++ // Value: ++ // Associated BSSID ++ if ( check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE ) ++ { ++ _rtw_memcpy( wfdie + wfdielen, &pmlmepriv->assoc_bssid[ 0 ], ETH_ALEN ); ++ } ++ else ++ { ++ _rtw_memset( wfdie + wfdielen, 0x00, ETH_ALEN ); ++ } ++ ++ wfdielen += ETH_ALEN; ++ ++ // Coupled Sink Information ATTR ++ // Type: ++ wfdie[ wfdielen++ ] = WFD_ATTR_COUPLED_SINK_INFO; ++ ++ // Length: ++ // Note: In the WFD specification, the size of length field is 2. ++ RTW_PUT_BE16(wfdie + wfdielen, 0x0001); ++ wfdielen += 2; ++ ++ // Value: ++ // Coupled Sink Status bitmap ++ // Not coupled/available for Coupling ++ wfdie[ wfdielen++ ] = 0; ++ ++ pbuf = rtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, wfdielen, (unsigned char *) wfdie, &len); ++ ++ return len; ++ ++} ++ ++u32 build_assoc_resp_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf) ++{ ++ u8 wfdie[ MAX_WFD_IE_LEN] = { 0x00 }; ++ u32 len=0, wfdielen = 0; ++ _adapter *padapter = pwdinfo->padapter; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct wifi_display_info* pwfd_info = &padapter->wdinfo.wfd_info; ++ ++ // WFD OUI ++ wfdielen = 0; ++ wfdie[ wfdielen++ ] = 0x50; ++ wfdie[ wfdielen++ ] = 0x6F; ++ wfdie[ wfdielen++ ] = 0x9A; ++ wfdie[ wfdielen++ ] = 0x0A; // WFA WFD v1.0 ++ ++ // Commented by Albert 20110812 ++ // According to the WFD Specification, the probe request frame should contain 4 WFD attributes ++ // 1. WFD Device Information ++ // 2. Associated BSSID ++ // 3. Coupled Sink Information ++ ++ ++ // WFD Device Information ATTR ++ // Type: ++ wfdie[ wfdielen++ ] = WFD_ATTR_DEVICE_INFO; ++ ++ // Length: ++ // Note: In the WFD specification, the size of length field is 2. ++ RTW_PUT_BE16(wfdie + wfdielen, 0x0006); ++ wfdielen += 2; ++ ++ // Value1: ++ // WFD device information ++ // WFD primary sink + available for WFD session + WiFi Direct mode ++ RTW_PUT_BE16(wfdie + wfdielen, 0x0011); ++ wfdielen += 2; ++ ++ // Value2: ++ // Session Management Control Port ++ // Default TCP port for RTSP messages is 554 ++ RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->rtsp_ctrlport ); ++ wfdielen += 2; ++ ++ // Value3: ++ // WFD Device Maximum Throughput ++ // 300Mbps is the maximum throughput ++ RTW_PUT_BE16(wfdie + wfdielen, 300); ++ wfdielen += 2; ++ ++ // Associated BSSID ATTR ++ // Type: ++ wfdie[ wfdielen++ ] = WFD_ATTR_ASSOC_BSSID; ++ ++ // Length: ++ // Note: In the WFD specification, the size of length field is 2. ++ RTW_PUT_BE16(wfdie + wfdielen, 0x0006); ++ wfdielen += 2; ++ ++ // Value: ++ // Associated BSSID ++ if ( check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE ) ++ { ++ _rtw_memcpy( wfdie + wfdielen, &pmlmepriv->assoc_bssid[ 0 ], ETH_ALEN ); ++ } ++ else ++ { ++ _rtw_memset( wfdie + wfdielen, 0x00, ETH_ALEN ); ++ } ++ ++ wfdielen += ETH_ALEN; ++ ++ // Coupled Sink Information ATTR ++ // Type: ++ wfdie[ wfdielen++ ] = WFD_ATTR_COUPLED_SINK_INFO; ++ ++ // Length: ++ // Note: In the WFD specification, the size of length field is 2. ++ RTW_PUT_BE16(wfdie + wfdielen, 0x0001); ++ wfdielen += 2; ++ ++ // Value: ++ // Coupled Sink Status bitmap ++ // Not coupled/available for Coupling ++ wfdie[ wfdielen++ ] = 0; ++ ++ pbuf = rtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, wfdielen, (unsigned char *) wfdie, &len); ++ ++ return len; ++ ++} ++ ++u32 build_nego_req_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf) ++{ ++ u8 wfdie[ MAX_WFD_IE_LEN] = { 0x00 }; ++ u32 len=0, wfdielen = 0; ++ _adapter *padapter = pwdinfo->padapter; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct wifi_display_info* pwfd_info = &padapter->wdinfo.wfd_info; ++ ++ // WFD OUI ++ wfdielen = 0; ++ wfdie[ wfdielen++ ] = 0x50; ++ wfdie[ wfdielen++ ] = 0x6F; ++ wfdie[ wfdielen++ ] = 0x9A; ++ wfdie[ wfdielen++ ] = 0x0A; // WFA WFD v1.0 ++ ++ // Commented by Albert 20110825 ++ // According to the WFD Specification, the negotiation request frame should contain 3 WFD attributes ++ // 1. WFD Device Information ++ // 2. Associated BSSID ( Optional ) ++ // 3. Local IP Adress ( Optional ) ++ ++ ++ // WFD Device Information ATTR ++ // Type: ++ wfdie[ wfdielen++ ] = WFD_ATTR_DEVICE_INFO; ++ ++ // Length: ++ // Note: In the WFD specification, the size of length field is 2. ++ RTW_PUT_BE16(wfdie + wfdielen, 0x0006); ++ wfdielen += 2; ++ ++ // Value1: ++ // WFD device information ++ // WFD primary sink + WiFi Direct mode ++ RTW_PUT_BE16(wfdie + wfdielen, 0x0001); ++ wfdielen += 2; ++ ++ // Value2: ++ // Session Management Control Port ++ // Default TCP port for RTSP messages is 554 ++ RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->rtsp_ctrlport ); ++ wfdielen += 2; ++ ++ // Value3: ++ // WFD Device Maximum Throughput ++ // 300Mbps is the maximum throughput ++ RTW_PUT_BE16(wfdie + wfdielen, 300); ++ wfdielen += 2; ++ ++ // Associated BSSID ATTR ++ // Type: ++ wfdie[ wfdielen++ ] = WFD_ATTR_ASSOC_BSSID; ++ ++ // Length: ++ // Note: In the WFD specification, the size of length field is 2. ++ RTW_PUT_BE16(wfdie + wfdielen, 0x0006); ++ wfdielen += 2; ++ ++ // Value: ++ // Associated BSSID ++ if ( check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE ) ++ { ++ _rtw_memcpy( wfdie + wfdielen, &pmlmepriv->assoc_bssid[ 0 ], ETH_ALEN ); ++ } ++ else ++ { ++ _rtw_memset( wfdie + wfdielen, 0x00, ETH_ALEN ); ++ } ++ ++ wfdielen += ETH_ALEN; ++ ++ // Coupled Sink Information ATTR ++ // Type: ++ wfdie[ wfdielen++ ] = WFD_ATTR_COUPLED_SINK_INFO; ++ ++ // Length: ++ // Note: In the WFD specification, the size of length field is 2. ++ RTW_PUT_BE16(wfdie + wfdielen, 0x0001); ++ wfdielen += 2; ++ ++ // Value: ++ // Coupled Sink Status bitmap ++ // Not coupled/available for Coupling ++ wfdie[ wfdielen++ ] = 0; ++ ++ pbuf = rtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, wfdielen, (unsigned char *) wfdie, &len); ++ ++ return len; ++ ++} ++ ++u32 build_nego_resp_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf) ++{ ++ u8 wfdie[ MAX_WFD_IE_LEN] = { 0x00 }; ++ u32 len=0, wfdielen = 0; ++ _adapter *padapter = pwdinfo->padapter; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct wifi_display_info* pwfd_info = &padapter->wdinfo.wfd_info; ++ ++ // WFD OUI ++ wfdielen = 0; ++ wfdie[ wfdielen++ ] = 0x50; ++ wfdie[ wfdielen++ ] = 0x6F; ++ wfdie[ wfdielen++ ] = 0x9A; ++ wfdie[ wfdielen++ ] = 0x0A; // WFA WFD v1.0 ++ ++ // Commented by Albert 20110825 ++ // According to the WFD Specification, the negotiation request frame should contain 3 WFD attributes ++ // 1. WFD Device Information ++ // 2. Associated BSSID ( Optional ) ++ // 3. Local IP Adress ( Optional ) ++ ++ ++ // WFD Device Information ATTR ++ // Type: ++ wfdie[ wfdielen++ ] = WFD_ATTR_DEVICE_INFO; ++ ++ // Length: ++ // Note: In the WFD specification, the size of length field is 2. ++ RTW_PUT_BE16(wfdie + wfdielen, 0x0006); ++ wfdielen += 2; ++ ++ // Value1: ++ // WFD device information ++ // WFD primary sink + WiFi Direct mode ++ RTW_PUT_BE16(wfdie + wfdielen, 0x0001); ++ wfdielen += 2; ++ ++ // Value2: ++ // Session Management Control Port ++ // Default TCP port for RTSP messages is 554 ++ RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->rtsp_ctrlport ); ++ wfdielen += 2; ++ ++ // Value3: ++ // WFD Device Maximum Throughput ++ // 300Mbps is the maximum throughput ++ RTW_PUT_BE16(wfdie + wfdielen, 300); ++ wfdielen += 2; ++ ++ // Associated BSSID ATTR ++ // Type: ++ wfdie[ wfdielen++ ] = WFD_ATTR_ASSOC_BSSID; ++ ++ // Length: ++ // Note: In the WFD specification, the size of length field is 2. ++ RTW_PUT_BE16(wfdie + wfdielen, 0x0006); ++ wfdielen += 2; ++ ++ // Value: ++ // Associated BSSID ++ if ( check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE ) ++ { ++ _rtw_memcpy( wfdie + wfdielen, &pmlmepriv->assoc_bssid[ 0 ], ETH_ALEN ); ++ } ++ else ++ { ++ _rtw_memset( wfdie + wfdielen, 0x00, ETH_ALEN ); ++ } ++ ++ wfdielen += ETH_ALEN; ++ ++ // Coupled Sink Information ATTR ++ // Type: ++ wfdie[ wfdielen++ ] = WFD_ATTR_COUPLED_SINK_INFO; ++ ++ // Length: ++ // Note: In the WFD specification, the size of length field is 2. ++ RTW_PUT_BE16(wfdie + wfdielen, 0x0001); ++ wfdielen += 2; ++ ++ // Value: ++ // Coupled Sink Status bitmap ++ // Not coupled/available for Coupling ++ wfdie[ wfdielen++ ] = 0; ++ ++ ++ pbuf = rtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, wfdielen, (unsigned char *) wfdie, &len); ++ ++ return len; ++ ++} ++ ++u32 build_nego_confirm_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf) ++{ ++ u8 wfdie[ MAX_WFD_IE_LEN] = { 0x00 }; ++ u32 len=0, wfdielen = 0; ++ _adapter *padapter = pwdinfo->padapter; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct wifi_display_info* pwfd_info = &padapter->wdinfo.wfd_info; ++ ++ // WFD OUI ++ wfdielen = 0; ++ wfdie[ wfdielen++ ] = 0x50; ++ wfdie[ wfdielen++ ] = 0x6F; ++ wfdie[ wfdielen++ ] = 0x9A; ++ wfdie[ wfdielen++ ] = 0x0A; // WFA WFD v1.0 ++ ++ // Commented by Albert 20110825 ++ // According to the WFD Specification, the negotiation request frame should contain 3 WFD attributes ++ // 1. WFD Device Information ++ // 2. Associated BSSID ( Optional ) ++ // 3. Local IP Adress ( Optional ) ++ ++ ++ // WFD Device Information ATTR ++ // Type: ++ wfdie[ wfdielen++ ] = WFD_ATTR_DEVICE_INFO; ++ ++ // Length: ++ // Note: In the WFD specification, the size of length field is 2. ++ RTW_PUT_BE16(wfdie + wfdielen, 0x0006); ++ wfdielen += 2; ++ ++ // Value1: ++ // WFD device information ++ // WFD primary sink + WiFi Direct mode ++ RTW_PUT_BE16(wfdie + wfdielen, 0x0001); ++ wfdielen += 2; ++ ++ // Value2: ++ // Session Management Control Port ++ // Default TCP port for RTSP messages is 554 ++ RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->rtsp_ctrlport ); ++ wfdielen += 2; ++ ++ // Value3: ++ // WFD Device Maximum Throughput ++ // 300Mbps is the maximum throughput ++ RTW_PUT_BE16(wfdie + wfdielen, 300); ++ wfdielen += 2; ++ ++ // Associated BSSID ATTR ++ // Type: ++ wfdie[ wfdielen++ ] = WFD_ATTR_ASSOC_BSSID; ++ ++ // Length: ++ // Note: In the WFD specification, the size of length field is 2. ++ RTW_PUT_BE16(wfdie + wfdielen, 0x0006); ++ wfdielen += 2; ++ ++ // Value: ++ // Associated BSSID ++ if ( check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE ) ++ { ++ _rtw_memcpy( wfdie + wfdielen, &pmlmepriv->assoc_bssid[ 0 ], ETH_ALEN ); ++ } ++ else ++ { ++ _rtw_memset( wfdie + wfdielen, 0x00, ETH_ALEN ); ++ } ++ ++ wfdielen += ETH_ALEN; ++ ++ // Coupled Sink Information ATTR ++ // Type: ++ wfdie[ wfdielen++ ] = WFD_ATTR_COUPLED_SINK_INFO; ++ ++ // Length: ++ // Note: In the WFD specification, the size of length field is 2. ++ RTW_PUT_BE16(wfdie + wfdielen, 0x0001); ++ wfdielen += 2; ++ ++ // Value: ++ // Coupled Sink Status bitmap ++ // Not coupled/available for Coupling ++ wfdie[ wfdielen++ ] = 0; ++ ++ ++ pbuf = rtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, wfdielen, (unsigned char *) wfdie, &len); ++ ++ return len; ++ ++} ++ ++u32 build_provdisc_req_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf) ++{ ++ u8 wfdie[ MAX_WFD_IE_LEN] = { 0x00 }; ++ u32 len=0, wfdielen = 0; ++ _adapter *padapter = pwdinfo->padapter; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct wifi_display_info* pwfd_info = &padapter->wdinfo.wfd_info; ++ ++ // WFD OUI ++ wfdielen = 0; ++ wfdie[ wfdielen++ ] = 0x50; ++ wfdie[ wfdielen++ ] = 0x6F; ++ wfdie[ wfdielen++ ] = 0x9A; ++ wfdie[ wfdielen++ ] = 0x0A; // WFA WFD v1.0 ++ ++ // Commented by Albert 20110825 ++ // According to the WFD Specification, the provision discovery request frame should contain 3 WFD attributes ++ // 1. WFD Device Information ++ // 2. Associated BSSID ( Optional ) ++ // 3. Local IP Adress ( Optional ) ++ ++ ++ // WFD Device Information ATTR ++ // Type: ++ wfdie[ wfdielen++ ] = WFD_ATTR_DEVICE_INFO; ++ ++ // Length: ++ // Note: In the WFD specification, the size of length field is 2. ++ RTW_PUT_BE16(wfdie + wfdielen, 0x0006); ++ wfdielen += 2; ++ ++ // Value1: ++ // WFD device information ++ // WFD primary sink + available for WFD session + WiFi Direct mode ++ RTW_PUT_BE16(wfdie + wfdielen, 0x0011); ++ wfdielen += 2; ++ ++ // Value2: ++ // Session Management Control Port ++ // Default TCP port for RTSP messages is 554 ++ RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->rtsp_ctrlport ); ++ wfdielen += 2; ++ ++ // Value3: ++ // WFD Device Maximum Throughput ++ // 300Mbps is the maximum throughput ++ RTW_PUT_BE16(wfdie + wfdielen, 300); ++ wfdielen += 2; ++ ++ // Associated BSSID ATTR ++ // Type: ++ wfdie[ wfdielen++ ] = WFD_ATTR_ASSOC_BSSID; ++ ++ // Length: ++ // Note: In the WFD specification, the size of length field is 2. ++ RTW_PUT_BE16(wfdie + wfdielen, 0x0006); ++ wfdielen += 2; ++ ++ // Value: ++ // Associated BSSID ++ if ( check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE ) ++ { ++ _rtw_memcpy( wfdie + wfdielen, &pmlmepriv->assoc_bssid[ 0 ], ETH_ALEN ); ++ } ++ else ++ { ++ _rtw_memset( wfdie + wfdielen, 0x00, ETH_ALEN ); ++ } ++ ++ wfdielen += ETH_ALEN; ++ ++ // Coupled Sink Information ATTR ++ // Type: ++ wfdie[ wfdielen++ ] = WFD_ATTR_COUPLED_SINK_INFO; ++ ++ // Length: ++ // Note: In the WFD specification, the size of length field is 2. ++ RTW_PUT_BE16(wfdie + wfdielen, 0x0001); ++ wfdielen += 2; ++ ++ // Value: ++ // Coupled Sink Status bitmap ++ // Not coupled/available for Coupling ++ wfdie[ wfdielen++ ] = 0; ++ ++ ++ pbuf = rtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, wfdielen, (unsigned char *) wfdie, &len); ++ ++ return len; ++ ++} ++ ++u32 build_provdisc_resp_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf) ++{ ++ u8 wfdie[ MAX_WFD_IE_LEN] = { 0x00 }; ++ u32 len=0, wfdielen = 0; ++ _adapter *padapter = pwdinfo->padapter; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct wifi_display_info* pwfd_info = &padapter->wdinfo.wfd_info; ++ ++ // WFD OUI ++ wfdielen = 0; ++ wfdie[ wfdielen++ ] = 0x50; ++ wfdie[ wfdielen++ ] = 0x6F; ++ wfdie[ wfdielen++ ] = 0x9A; ++ wfdie[ wfdielen++ ] = 0x0A; // WFA WFD v1.0 ++ ++ // Commented by Albert 20110825 ++ // According to the WFD Specification, the provision discovery response frame should contain 3 WFD attributes ++ // 1. WFD Device Information ++ // 2. Associated BSSID ( Optional ) ++ // 3. Local IP Adress ( Optional ) ++ ++ ++ // WFD Device Information ATTR ++ // Type: ++ wfdie[ wfdielen++ ] = WFD_ATTR_DEVICE_INFO; ++ ++ // Length: ++ // Note: In the WFD specification, the size of length field is 2. ++ RTW_PUT_BE16(wfdie + wfdielen, 0x0006); ++ wfdielen += 2; ++ ++ // Value1: ++ // WFD device information ++ // WFD primary sink + available for WFD session + WiFi Direct mode ++ RTW_PUT_BE16(wfdie + wfdielen, 0x0011); ++ wfdielen += 2; ++ ++ // Value2: ++ // Session Management Control Port ++ // Default TCP port for RTSP messages is 554 ++ RTW_PUT_BE16(wfdie + wfdielen, pwfd_info->rtsp_ctrlport ); ++ wfdielen += 2; ++ ++ // Value3: ++ // WFD Device Maximum Throughput ++ // 300Mbps is the maximum throughput ++ RTW_PUT_BE16(wfdie + wfdielen, 300); ++ wfdielen += 2; ++ ++ // Associated BSSID ATTR ++ // Type: ++ wfdie[ wfdielen++ ] = WFD_ATTR_ASSOC_BSSID; ++ ++ // Length: ++ // Note: In the WFD specification, the size of length field is 2. ++ RTW_PUT_BE16(wfdie + wfdielen, 0x0006); ++ wfdielen += 2; ++ ++ // Value: ++ // Associated BSSID ++ if ( check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE ) ++ { ++ _rtw_memcpy( wfdie + wfdielen, &pmlmepriv->assoc_bssid[ 0 ], ETH_ALEN ); ++ } ++ else ++ { ++ _rtw_memset( wfdie + wfdielen, 0x00, ETH_ALEN ); ++ } ++ ++ wfdielen += ETH_ALEN; ++ ++ // Coupled Sink Information ATTR ++ // Type: ++ wfdie[ wfdielen++ ] = WFD_ATTR_COUPLED_SINK_INFO; ++ ++ // Length: ++ // Note: In the WFD specification, the size of length field is 2. ++ RTW_PUT_BE16(wfdie + wfdielen, 0x0001); ++ wfdielen += 2; ++ ++ // Value: ++ // Coupled Sink Status bitmap ++ // Not coupled/available for Coupling ++ wfdie[ wfdielen++ ] = 0; ++ ++ pbuf = rtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, wfdielen, (unsigned char *) wfdie, &len); ++ ++ return len; ++ ++} ++ ++ ++#endif //CONFIG_WFD ++ ++u32 build_probe_resp_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pbuf) ++{ ++ u8 p2pie[ MAX_P2P_IE_LEN] = { 0x00 }; ++ u32 len=0, p2pielen = 0; ++ ++ // P2P OUI ++ p2pielen = 0; ++ p2pie[ p2pielen++ ] = 0x50; ++ p2pie[ p2pielen++ ] = 0x6F; ++ p2pie[ p2pielen++ ] = 0x9A; ++ p2pie[ p2pielen++ ] = 0x09; // WFA P2P v1.0 ++ ++ // Commented by Albert 20100907 ++ // According to the P2P Specification, the probe response frame should contain 5 P2P attributes ++ // 1. P2P Capability ++ // 2. Extended Listen Timing ++ // 3. Notice of Absence ( NOA ) ( Only GO needs this ) ++ // 4. Device Info ++ // 5. Group Info ( Only GO need this ) ++ ++ // P2P Capability ATTR ++ // Type: ++ p2pie[ p2pielen++ ] = P2P_ATTR_CAPABILITY; ++ ++ // Length: ++ //*(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0002 ); ++ RTW_PUT_LE16(p2pie + p2pielen, 0x0002); ++ p2pielen += 2; ++ ++ // Value: ++ // Device Capability Bitmap, 1 byte ++ // Be able to participate in additional P2P Groups and ++ // support the P2P Invitation Procedure ++ p2pie[ p2pielen++ ] = P2P_DEVCAP_INVITATION_PROC|P2P_DEVCAP_CLIENT_DISCOVERABILITY; ++ ++ // Group Capability Bitmap, 1 byte ++ if(rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) ++ { ++ p2pie[ p2pielen ] = (P2P_GRPCAP_GO | P2P_GRPCAP_INTRABSS); ++ ++ if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_PROVISIONING_ING)) ++ p2pie[ p2pielen ] |= P2P_GRPCAP_GROUP_FORMATION; ++ ++ p2pielen++; ++ } ++ else if ( rtw_p2p_chk_role(pwdinfo, P2P_ROLE_DEVICE) ) ++ { ++ // Group Capability Bitmap, 1 byte ++ p2pie[ p2pielen++ ] = 0x00; ++ } ++ ++ // Extended Listen Timing ATTR ++ // Type: ++ p2pie[ p2pielen++ ] = P2P_ATTR_EX_LISTEN_TIMING; ++ ++ // Length: ++ //*(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0004 ); ++ RTW_PUT_LE16(p2pie + p2pielen, 0x0004); ++ p2pielen += 2; ++ ++ // Value: ++ // Availability Period ++ //*(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0xFFFF ); ++ RTW_PUT_LE16(p2pie + p2pielen, 0xFFFF); ++ p2pielen += 2; ++ ++ // Availability Interval ++ //*(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0xFFFF ); ++ RTW_PUT_LE16(p2pie + p2pielen, 0xFFFF); ++ p2pielen += 2; ++ ++ ++ // Notice of Absence ATTR ++ // Type: ++ // Length: ++ // Value: ++ if(rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) ++ { ++ //go_add_noa_attr(pwdinfo); ++ } ++ ++ // Device Info ATTR ++ // Type: ++ p2pie[ p2pielen++ ] = P2P_ATTR_DEVICE_INFO; ++ ++ // Length: ++ // 21 -> P2P Device Address (6bytes) + Config Methods (2bytes) + Primary Device Type (8bytes) ++ // + NumofSecondDevType (1byte) + WPS Device Name ID field (2bytes) + WPS Device Name Len field (2bytes) ++ //*(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 21 + pwdinfo->device_name_len ); ++ RTW_PUT_LE16(p2pie + p2pielen, 21 + pwdinfo->device_name_len); ++ p2pielen += 2; ++ ++ // Value: ++ // P2P Device Address ++ _rtw_memcpy( p2pie + p2pielen, pwdinfo->device_addr, ETH_ALEN ); ++ p2pielen += ETH_ALEN; ++ ++ // Config Method ++ // This field should be big endian. Noted by P2P specification. ++ //*(u16*) ( p2pie + p2pielen ) = cpu_to_be16( pwdinfo->supported_wps_cm ); ++ RTW_PUT_BE16(p2pie + p2pielen, pwdinfo->supported_wps_cm); ++ p2pielen += 2; ++ ++ // Primary Device Type ++ // Category ID ++ //*(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_PDT_CID_RTK_WIDI ); ++ RTW_PUT_BE16(p2pie + p2pielen, WPS_PDT_CID_RTK_WIDI); ++ p2pielen += 2; ++ ++ // OUI ++ //*(u32*) ( p2pie + p2pielen ) = cpu_to_be32( WPSOUI ); ++ RTW_PUT_BE32(p2pie + p2pielen, WPSOUI); ++ p2pielen += 4; ++ ++ // Sub Category ID ++ //*(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_PDT_SCID_RTK_DMP ); ++ RTW_PUT_BE16(p2pie + p2pielen, WPS_PDT_SCID_RTK_DMP); ++ p2pielen += 2; ++ ++ // Number of Secondary Device Types ++ p2pie[ p2pielen++ ] = 0x00; // No Secondary Device Type List ++ ++ // Device Name ++ // Type: ++ //*(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_ATTR_DEVICE_NAME ); ++ RTW_PUT_BE16(p2pie + p2pielen, WPS_ATTR_DEVICE_NAME); ++ p2pielen += 2; ++ ++ // Length: ++ //*(u16*) ( p2pie + p2pielen ) = cpu_to_be16( pwdinfo->device_name_len ); ++ RTW_PUT_BE16(p2pie + p2pielen, pwdinfo->device_name_len); ++ p2pielen += 2; ++ ++ // Value: ++ _rtw_memcpy( p2pie + p2pielen, pwdinfo->device_name, pwdinfo->device_name_len ); ++ p2pielen += pwdinfo->device_name_len; ++ ++ ++ // Group Info ATTR ++ // Type: ++ // Length: ++ // Value: ++ if(rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) ++ { ++ p2pielen += go_add_group_info_attr(pwdinfo, p2pie + p2pielen); ++ } ++ ++ ++ pbuf = rtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, p2pielen, (unsigned char *) p2pie, &len); ++ ++ ++ return len; ++ ++} ++ ++u32 build_prov_disc_request_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pbuf, u8* pssid, u8 ussidlen, u8* pdev_raddr ) ++{ ++ u8 p2pie[ MAX_P2P_IE_LEN] = { 0x00 }; ++ u32 len=0, p2pielen = 0; ++ ++ // P2P OUI ++ p2pielen = 0; ++ p2pie[ p2pielen++ ] = 0x50; ++ p2pie[ p2pielen++ ] = 0x6F; ++ p2pie[ p2pielen++ ] = 0x9A; ++ p2pie[ p2pielen++ ] = 0x09; // WFA P2P v1.0 ++ ++ // Commented by Albert 20110301 ++ // According to the P2P Specification, the provision discovery request frame should contain 3 P2P attributes ++ // 1. P2P Capability ++ // 2. Device Info ++ // 3. Group ID ( When joining an operating P2P Group ) ++ ++ // P2P Capability ATTR ++ // Type: ++ p2pie[ p2pielen++ ] = P2P_ATTR_CAPABILITY; ++ ++ // Length: ++ //*(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0002 ); ++ RTW_PUT_LE16(p2pie + p2pielen, 0x0002); ++ p2pielen += 2; ++ ++ // Value: ++ // Device Capability Bitmap, 1 byte ++ // Be able to participate in additional P2P Groups and ++ // support the P2P Invitation Procedure ++ p2pie[ p2pielen++ ] = P2P_DEVCAP_INVITATION_PROC; ++ ++ // Group Capability Bitmap, 1 byte ++ p2pie[ p2pielen++ ] = 0x00; ++ ++ ++ // Device Info ATTR ++ // Type: ++ p2pie[ p2pielen++ ] = P2P_ATTR_DEVICE_INFO; ++ ++ // Length: ++ // 21 -> P2P Device Address (6bytes) + Config Methods (2bytes) + Primary Device Type (8bytes) ++ // + NumofSecondDevType (1byte) + WPS Device Name ID field (2bytes) + WPS Device Name Len field (2bytes) ++ //*(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 21 + pwdinfo->device_name_len ); ++ RTW_PUT_LE16(p2pie + p2pielen, 21 + pwdinfo->device_name_len); ++ p2pielen += 2; ++ ++ // Value: ++ // P2P Device Address ++ _rtw_memcpy( p2pie + p2pielen, pwdinfo->device_addr, ETH_ALEN ); ++ p2pielen += ETH_ALEN; ++ ++ // Config Method ++ // This field should be big endian. Noted by P2P specification. ++ if ( pwdinfo->ui_got_wps_info == P2P_GOT_WPSINFO_PBC ) ++ { ++ //*(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_CONFIG_METHOD_PBC ); ++ RTW_PUT_BE16(p2pie + p2pielen, WPS_CONFIG_METHOD_PBC); ++ } ++ else ++ { ++ //*(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_CONFIG_METHOD_DISPLAY ); ++ RTW_PUT_BE16(p2pie + p2pielen, WPS_CONFIG_METHOD_DISPLAY); ++ } ++ ++ p2pielen += 2; ++ ++ // Primary Device Type ++ // Category ID ++ //*(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_PDT_CID_RTK_WIDI ); ++ RTW_PUT_BE16(p2pie + p2pielen, WPS_PDT_CID_RTK_WIDI); ++ p2pielen += 2; ++ ++ // OUI ++ //*(u32*) ( p2pie + p2pielen ) = cpu_to_be32( WPSOUI ); ++ RTW_PUT_BE32(p2pie + p2pielen, WPSOUI); ++ p2pielen += 4; ++ ++ // Sub Category ID ++ //*(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_PDT_SCID_RTK_DMP ); ++ RTW_PUT_BE16(p2pie + p2pielen, WPS_PDT_SCID_RTK_DMP); ++ p2pielen += 2; ++ ++ // Number of Secondary Device Types ++ p2pie[ p2pielen++ ] = 0x00; // No Secondary Device Type List ++ ++ // Device Name ++ // Type: ++ //*(u16*) ( p2pie + p2pielen ) = cpu_to_be16( WPS_ATTR_DEVICE_NAME ); ++ RTW_PUT_BE16(p2pie + p2pielen, WPS_ATTR_DEVICE_NAME); ++ p2pielen += 2; ++ ++ // Length: ++ //*(u16*) ( p2pie + p2pielen ) = cpu_to_be16( pwdinfo->device_name_len ); ++ RTW_PUT_BE16(p2pie + p2pielen, pwdinfo->device_name_len); ++ p2pielen += 2; ++ ++ // Value: ++ _rtw_memcpy( p2pie + p2pielen, pwdinfo->device_name, pwdinfo->device_name_len ); ++ p2pielen += pwdinfo->device_name_len; ++ ++ if ( rtw_p2p_chk_role(pwdinfo, P2P_ROLE_CLIENT) ) ++ { ++ // Added by Albert 2011/05/19 ++ // In this case, the pdev_raddr is the device address of the group owner. ++ ++ // P2P Group ID ATTR ++ // Type: ++ p2pie[ p2pielen++ ] = P2P_ATTR_GROUP_ID; ++ ++ // Length: ++ //*(u16*) ( p2pie + p2pielen ) = cpu_to_le16( ETH_ALEN + ussidlen ); ++ RTW_PUT_LE16(p2pie + p2pielen, ETH_ALEN + ussidlen); ++ p2pielen += 2; ++ ++ // Value: ++ _rtw_memcpy( p2pie + p2pielen, pdev_raddr, ETH_ALEN ); ++ p2pielen += ETH_ALEN; ++ ++ _rtw_memcpy( p2pie + p2pielen, pssid, ussidlen ); ++ p2pielen += ussidlen; ++ ++ } ++ ++ pbuf = rtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, p2pielen, (unsigned char *) p2pie, &len); ++ ++ ++ return len; ++ ++} ++ ++ ++u32 build_assoc_resp_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pbuf, u8 status_code) ++{ ++ u8 p2pie[ MAX_P2P_IE_LEN] = { 0x00 }; ++ u32 len=0, p2pielen = 0; ++ ++ // P2P OUI ++ p2pielen = 0; ++ p2pie[ p2pielen++ ] = 0x50; ++ p2pie[ p2pielen++ ] = 0x6F; ++ p2pie[ p2pielen++ ] = 0x9A; ++ p2pie[ p2pielen++ ] = 0x09; // WFA P2P v1.0 ++ ++ // According to the P2P Specification, the Association response frame should contain 2 P2P attributes ++ // 1. Status ++ // 2. Extended Listen Timing (optional) ++ ++ ++ // Status ATTR ++ p2pielen += rtw_set_p2p_attr_content(&p2pie[p2pielen], P2P_ATTR_STATUS, 1, &status_code); ++ ++ ++ // Extended Listen Timing ATTR ++ // Type: ++ // Length: ++ // Value: ++ ++ ++ pbuf = rtw_set_ie(pbuf, _VENDOR_SPECIFIC_IE_, p2pielen, (unsigned char *) p2pie, &len); ++ ++ return len; ++ ++} ++ ++u32 build_deauth_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pbuf) ++{ ++ u32 len=0; ++ ++ return len; ++} ++ ++u32 process_probe_req_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pframe, uint len) ++{ ++ u8 *p; ++ u32 ret=_FALSE; ++ u8 *p2pie; ++ u32 p2pielen = 0; ++ int ssid_len=0, rate_cnt = 0; ++ ++ p = rtw_get_ie(pframe + WLAN_HDR_A3_LEN + _PROBEREQ_IE_OFFSET_, _SUPPORTEDRATES_IE_, (int *)&rate_cnt, ++ len - WLAN_HDR_A3_LEN - _PROBEREQ_IE_OFFSET_); ++ ++ if ( rate_cnt <= 4 ) ++ { ++ int i, g_rate =0; ++ ++ for( i = 0; i < rate_cnt; i++ ) ++ { ++ if ( ( ( *( p + 2 + i ) & 0xff ) != 0x02 ) && ++ ( ( *( p + 2 + i ) & 0xff ) != 0x04 ) && ++ ( ( *( p + 2 + i ) & 0xff ) != 0x0B ) && ++ ( ( *( p + 2 + i ) & 0xff ) != 0x16 ) ) ++ { ++ g_rate = 1; ++ } ++ } ++ ++ if ( g_rate == 0 ) ++ { ++ // There is no OFDM rate included in SupportedRates IE of this probe request frame ++ // The driver should response this probe request. ++ return ret; ++ } ++ } ++ else ++ { ++ // rate_cnt > 4 means the SupportRates IE contains the OFDM rate because the count of CCK rates are 4. ++ // We should proceed the following check for this probe request. ++ } ++ ++ // Added comments by Albert 20100906 ++ // There are several items we should check here. ++ // 1. This probe request frame must contain the P2P IE. (Done) ++ // 2. This probe request frame must contain the wildcard SSID. (Done) ++ // 3. Wildcard BSSID. (Todo) ++ // 4. Destination Address. ( Done in mgt_dispatcher function ) ++ // 5. Requested Device Type in WSC IE. (Todo) ++ // 6. Device ID attribute in P2P IE. (Todo) ++ ++ p = rtw_get_ie(pframe + WLAN_HDR_A3_LEN + _PROBEREQ_IE_OFFSET_, _SSID_IE_, (int *)&ssid_len, ++ len - WLAN_HDR_A3_LEN - _PROBEREQ_IE_OFFSET_); ++ ++ if(rtw_p2p_chk_role(pwdinfo, P2P_ROLE_DEVICE) || rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) ++ { ++ if((p2pie=rtw_get_p2p_ie( pframe + WLAN_HDR_A3_LEN + _PROBEREQ_IE_OFFSET_ , len - WLAN_HDR_A3_LEN - _PROBEREQ_IE_OFFSET_ , NULL, &p2pielen))) ++ { ++ if ( (p != NULL) && _rtw_memcmp( ( void * ) ( p+2 ), ( void * ) pwdinfo->p2p_wildcard_ssid , 7 )) ++ { ++ //todo: ++ //Check Requested Device Type attributes in WSC IE. ++ //Check Device ID attribute in P2P IE ++ ++ ret = _TRUE; ++ } ++ } ++ else ++ { ++ //non -p2p device ++ } ++ ++ } ++ ++ ++ return ret; ++ ++} ++ ++u32 process_assoc_req_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pframe, uint len, struct sta_info *psta) ++{ ++ u8 status_code = P2P_STATUS_SUCCESS; ++ u8 *pbuf, *pattr_content=NULL; ++ u32 attr_contentlen = 0; ++ u16 cap_attr=0; ++ unsigned short frame_type, ie_offset=0; ++ u8 * ies; ++ u32 ies_len; ++ u8 * p2p_ie; ++ u32 p2p_ielen = 0; ++ ++ if(!rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) ++ return P2P_STATUS_FAIL_REQUEST_UNABLE; ++ ++ frame_type = GetFrameSubType(pframe); ++ if (frame_type == WIFI_ASSOCREQ) ++ { ++ ie_offset = _ASOCREQ_IE_OFFSET_; ++ } ++ else // WIFI_REASSOCREQ ++ { ++ ie_offset = _REASOCREQ_IE_OFFSET_; ++ } ++ ++ ies = pframe + WLAN_HDR_A3_LEN + ie_offset; ++ ies_len = len - WLAN_HDR_A3_LEN - ie_offset; ++ ++ p2p_ie = rtw_get_p2p_ie(ies , ies_len , NULL, &p2p_ielen); ++ ++ if ( !p2p_ie ) ++ { ++ DBG_8192C( "[%s] P2P IE not Found!!\n", __FUNCTION__ ); ++ status_code = P2P_STATUS_FAIL_INVALID_PARAM; ++ } ++ else ++ { ++ DBG_8192C( "[%s] P2P IE Found!!\n", __FUNCTION__ ); ++ } ++ ++ while ( p2p_ie ) ++ { ++ //Check P2P Capability ATTR ++ if( rtw_get_p2p_attr_content( p2p_ie, p2p_ielen, P2P_ATTR_CAPABILITY, (u8*)&cap_attr, (uint*) &attr_contentlen) ) ++ { ++ DBG_8192C( "[%s] Got P2P Capability Attr!!\n", __FUNCTION__ ); ++ cap_attr = le16_to_cpu(cap_attr); ++ psta->dev_cap = cap_attr&0xff; ++ } ++ ++ //Check Extended Listen Timing ATTR ++ ++ ++ //Check P2P Device Info ATTR ++ if(rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_DEVICE_INFO, NULL, (uint*)&attr_contentlen)) ++ { ++ DBG_8192C( "[%s] Got P2P DEVICE INFO Attr!!\n", __FUNCTION__ ); ++ pattr_content = pbuf = rtw_zmalloc(attr_contentlen); ++ if(pattr_content) ++ { ++ u8 num_of_secdev_type; ++ u16 dev_name_len; ++ ++ ++ rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_DEVICE_INFO , pattr_content, (uint*)&attr_contentlen); ++ ++ _rtw_memcpy(psta->dev_addr, pattr_content, ETH_ALEN);//P2P Device Address ++ ++ pattr_content += ETH_ALEN; ++ ++ _rtw_memcpy(&psta->config_methods, pattr_content, 2);//Config Methods ++ psta->config_methods = be16_to_cpu(psta->config_methods); ++ ++ pattr_content += 2; ++ ++ _rtw_memcpy(psta->primary_dev_type, pattr_content, 8); ++ ++ pattr_content += 8; ++ ++ num_of_secdev_type = *pattr_content; ++ pattr_content += 1; ++ ++ if(num_of_secdev_type==0) ++ { ++ psta->num_of_secdev_type = 0; ++ } ++ else ++ { ++ u32 len; ++ ++ psta->num_of_secdev_type = num_of_secdev_type; ++ ++ len = (sizeof(psta->secdev_types_list)<(num_of_secdev_type*8)) ? (sizeof(psta->secdev_types_list)) : (num_of_secdev_type*8); ++ ++ _rtw_memcpy(psta->secdev_types_list, pattr_content, len); ++ ++ pattr_content += (num_of_secdev_type*8); ++ } ++ ++ ++ //dev_name_len = attr_contentlen - ETH_ALEN - 2 - 8 - 1 - (num_of_secdev_type*8); ++ psta->dev_name_len=0; ++ if(WPS_ATTR_DEVICE_NAME == be16_to_cpu(*(u16*)pattr_content)) ++ { ++ dev_name_len = be16_to_cpu(*(u16*)(pattr_content+2)); ++ ++ psta->dev_name_len = (sizeof(psta->dev_name)dev_name):dev_name_len; ++ ++ _rtw_memcpy(psta->dev_name, pattr_content+4, psta->dev_name_len); ++ } ++ ++ rtw_mfree(pbuf, attr_contentlen); ++ ++ } ++ ++ } ++ ++ //Get the next P2P IE ++ p2p_ie = rtw_get_p2p_ie(p2p_ie+p2p_ielen, ies_len -(p2p_ie -ies + p2p_ielen), NULL, &p2p_ielen); ++ ++ } ++ ++ return status_code; ++ ++} ++ ++u32 process_p2p_devdisc_req(struct wifidirect_info *pwdinfo, u8 *pframe, uint len) ++{ ++ u8 *frame_body; ++ u8 status, dialogToken; ++ struct sta_info *psta = NULL; ++ _adapter *padapter = pwdinfo->padapter; ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ u8 *p2p_ie; ++ u32 p2p_ielen = 0; ++ ++ frame_body = (unsigned char *)(pframe + sizeof(struct rtw_ieee80211_hdr_3addr)); ++ ++ dialogToken = frame_body[7]; ++ status = P2P_STATUS_FAIL_UNKNOWN_P2PGROUP; ++ ++ if ( (p2p_ie=rtw_get_p2p_ie( frame_body + _PUBLIC_ACTION_IE_OFFSET_, len - _PUBLIC_ACTION_IE_OFFSET_, NULL, &p2p_ielen)) ) ++ { ++ u8 groupid[ 38 ] = { 0x00 }; ++ u8 dev_addr[ETH_ALEN] = { 0x00 }; ++ u32 attr_contentlen = 0; ++ ++ if(rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_GROUP_ID, groupid, &attr_contentlen)) ++ { ++ if(_rtw_memcmp(pwdinfo->device_addr, groupid, ETH_ALEN) && ++ _rtw_memcmp(pwdinfo->p2p_group_ssid, groupid+ETH_ALEN, pwdinfo->p2p_group_ssid_len)) ++ { ++ attr_contentlen=0; ++ if(rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_DEVICE_ID, dev_addr, &attr_contentlen)) ++ { ++ _irqL irqL; ++ _list *phead, *plist; ++ ++ _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL); ++ phead = &pstapriv->asoc_list; ++ plist = get_next(phead); ++ ++ //look up sta asoc_queue ++ while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) ++ { ++ psta = LIST_CONTAINOR(plist, struct sta_info, asoc_list); ++ ++ plist = get_next(plist); ++ ++ if(psta->is_p2p_device && (psta->dev_cap&P2P_DEVCAP_CLIENT_DISCOVERABILITY) && ++ _rtw_memcmp(psta->dev_addr, dev_addr, ETH_ALEN)) ++ { ++ ++ //_exit_critical_bh(&pstapriv->asoc_list_lock, &irqL); ++ //issue GO Discoverability Request ++ issue_group_disc_req(pwdinfo, psta->hwaddr); ++ //_enter_critical_bh(&pstapriv->asoc_list_lock, &irqL); ++ ++ status = P2P_STATUS_SUCCESS; ++ ++ break; ++ } ++ else ++ { ++ status = P2P_STATUS_FAIL_INFO_UNAVAILABLE; ++ } ++ ++ } ++ _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL); ++ ++ } ++ else ++ { ++ status = P2P_STATUS_FAIL_INVALID_PARAM; ++ } ++ ++ } ++ else ++ { ++ status = P2P_STATUS_FAIL_INVALID_PARAM; ++ } ++ ++ } ++ ++ } ++ ++ ++ //issue Device Discoverability Response ++ issue_p2p_devdisc_resp(pwdinfo, GetAddr2Ptr(pframe), status, dialogToken); ++ ++ ++ return (status==P2P_STATUS_SUCCESS) ? _TRUE:_FALSE; ++ ++} ++ ++u32 process_p2p_devdisc_resp(struct wifidirect_info *pwdinfo, u8 *pframe, uint len) ++{ ++ return _TRUE; ++} ++ ++u8 process_p2p_provdisc_req(struct wifidirect_info *pwdinfo, u8 *pframe, uint len ) ++{ ++ u8 *frame_body; ++ u8 *wpsie; ++ uint wps_ielen = 0, attr_contentlen = 0; ++ u16 uconfig_method = 0; ++ ++ ++ frame_body = (pframe + sizeof(struct rtw_ieee80211_hdr_3addr)); ++ ++ if ( (wpsie=rtw_get_wps_ie( frame_body + _PUBLIC_ACTION_IE_OFFSET_, len - _PUBLIC_ACTION_IE_OFFSET_, NULL, &wps_ielen)) ) ++ { ++ if ( rtw_get_wps_attr_content( wpsie, wps_ielen, WPS_ATTR_CONF_METHOD , ( u8* ) &uconfig_method, &attr_contentlen) ) ++ { ++ uconfig_method = be16_to_cpu( uconfig_method ); ++ switch( uconfig_method ) ++ { ++ case WPS_CM_DISPLYA: ++ { ++ _rtw_memcpy( pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, "dis", 3 ); ++ break; ++ } ++ case WPS_CM_LABEL: ++ { ++ _rtw_memcpy( pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, "lab", 3 ); ++ break; ++ } ++ case WPS_CM_PUSH_BUTTON: ++ { ++ _rtw_memcpy( pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, "pbc", 3 ); ++ break; ++ } ++ case WPS_CM_KEYPAD: ++ { ++ _rtw_memcpy( pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, "pad", 3 ); ++ break; ++ } ++ } ++ issue_p2p_provision_resp( pwdinfo, GetAddr2Ptr(pframe), frame_body, uconfig_method); ++ } ++ } ++ DBG_8192C( "[%s] config method = %s\n", __FUNCTION__, pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req ); ++ return _TRUE; ++ ++} ++ ++u8 process_p2p_provdisc_resp(struct wifidirect_info *pwdinfo, u8 *pframe) ++{ ++ ++ return _TRUE; ++} ++ ++ ++ ++u8 process_p2p_group_negotation_req( struct wifidirect_info *pwdinfo, u8 *pframe, uint len ) ++{ ++ u8 result = P2P_STATUS_SUCCESS; ++ u32 p2p_ielen = 0, wps_ielen = 0; ++ u8 * ies; ++ u32 ies_len; ++ u8 * p2p_ie; ++ u8 *wpsie; ++ u16 wps_devicepassword_id = 0x0000; ++ uint wps_devicepassword_id_len = 0; ++#ifdef CONFIG_WFD ++ u8 wfd_ie[ 128 ] = { 0x00 }; ++ u32 wfd_ielen = 0; ++#endif // CONFIG_WFD ++ ++ if ( pwdinfo->ui_got_wps_info == P2P_NO_WPSINFO ) ++ { ++ result = P2P_STATUS_FAIL_INFO_UNAVAILABLE; ++ rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_FAIL); ++ return( result ); ++ } ++ ++ if ( (wpsie=rtw_get_wps_ie( pframe + _PUBLIC_ACTION_IE_OFFSET_, len - _PUBLIC_ACTION_IE_OFFSET_, NULL, &wps_ielen)) ) ++ { ++ // Commented by Kurt 20120113 ++ // If some device wants to do p2p handshake without sending prov_disc_req ++ // We have to get peer_req_cm from here. ++ if(_rtw_memcmp( pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, "000", 3) ) ++ { ++ rtw_get_wps_attr_content( wpsie, wps_ielen, WPS_ATTR_DEVICE_PWID, (u8*) &wps_devicepassword_id, &wps_devicepassword_id_len); ++ wps_devicepassword_id = be16_to_cpu( wps_devicepassword_id ); ++ ++ if ( wps_devicepassword_id == WPS_DPID_USER_SPEC ) ++ { ++ _rtw_memcpy( pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, "dis", 3 ); ++ } ++ else if ( wps_devicepassword_id == WPS_DPID_REGISTRAR_SPEC ) ++ { ++ _rtw_memcpy( pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, "pad", 3 ); ++ } ++ else ++ { ++ _rtw_memcpy( pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, "pbc", 3 ); ++ } ++ } ++ } ++ else ++ { ++ DBG_8192C( "[%s] WPS IE not Found!!\n", __FUNCTION__ ); ++ result = P2P_STATUS_FAIL_INCOMPATIBLE_PARAM; ++ rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_FAIL); ++ return( result ); ++ } ++ ++ ies = pframe + _PUBLIC_ACTION_IE_OFFSET_; ++ ies_len = len - _PUBLIC_ACTION_IE_OFFSET_; ++ ++ p2p_ie = rtw_get_p2p_ie( ies, ies_len, NULL, &p2p_ielen ); ++ ++ if ( !p2p_ie ) ++ { ++ DBG_8192C( "[%s] P2P IE not Found!!\n", __FUNCTION__ ); ++ result = P2P_STATUS_FAIL_INCOMPATIBLE_PARAM; ++ rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_FAIL); ++ } ++ ++ while ( p2p_ie ) ++ { ++ u8 attr_content = 0x00; ++ u32 attr_contentlen = 0; ++ ++ rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_ING); ++ ++ if ( rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_GO_INTENT , &attr_content, &attr_contentlen) ) ++ { ++ DBG_8192C( "[%s] GO Intent = %d, tie = %d\n", __FUNCTION__, attr_content >> 1, attr_content & 0x01 ); ++ pwdinfo->peer_intent = attr_content; // include both intent and tie breaker values. ++ ++ if ( pwdinfo->intent == ( pwdinfo->peer_intent >> 1 ) ) ++ { ++ // Try to match the tie breaker value ++ if ( pwdinfo->intent == P2P_MAX_INTENT ) ++ { ++ rtw_p2p_set_role(pwdinfo, P2P_ROLE_DEVICE); ++ result = P2P_STATUS_FAIL_BOTH_GOINTENT_15; ++ } ++ else ++ { ++ if ( attr_content & 0x01 ) ++ { ++ rtw_p2p_set_role(pwdinfo, P2P_ROLE_CLIENT); ++ } ++ else ++ { ++ rtw_p2p_set_role(pwdinfo, P2P_ROLE_GO); ++ } ++ } ++ } ++ else if ( pwdinfo->intent > ( pwdinfo->peer_intent >> 1 ) ) ++ { ++ rtw_p2p_set_role(pwdinfo, P2P_ROLE_GO); ++ } ++ else ++ { ++ rtw_p2p_set_role(pwdinfo, P2P_ROLE_CLIENT); ++ } ++ ++ if(rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) ++ { ++ // Store the group id information. ++ _rtw_memcpy( pwdinfo->groupid_info.go_device_addr, pwdinfo->device_addr, ETH_ALEN ); ++ _rtw_memcpy( pwdinfo->groupid_info.ssid, pwdinfo->nego_ssid, pwdinfo->nego_ssidlen ); ++ } ++ } ++ ++ ++ attr_contentlen = 0; ++ if ( rtw_get_p2p_attr_content( p2p_ie, p2p_ielen, P2P_ATTR_INTENTED_IF_ADDR, pwdinfo->p2p_peer_interface_addr, &attr_contentlen ) ) ++ { ++ if ( attr_contentlen != ETH_ALEN ) ++ { ++ _rtw_memset( pwdinfo->p2p_peer_interface_addr, 0x00, ETH_ALEN ); ++ } ++ } ++ ++ //Get the next P2P IE ++ p2p_ie = rtw_get_p2p_ie(p2p_ie+p2p_ielen, ies_len -(p2p_ie -ies + p2p_ielen), NULL, &p2p_ielen); ++ } ++ ++#ifdef CONFIG_WFD ++ // Added by Albert 20110823 ++ // Try to get the TCP port information when receiving the negotiation request. ++ if ( rtw_get_wfd_ie( pframe + _PUBLIC_ACTION_IE_OFFSET_, len - _PUBLIC_ACTION_IE_OFFSET_, wfd_ie, &wfd_ielen ) ) ++ { ++ u8 attr_content[ 10 ] = { 0x00 }; ++ u32 attr_contentlen = 0; ++ ++ DBG_8192C( "[%s] WFD IE Found!!\n", __FUNCTION__ ); ++ rtw_get_wfd_attr_content( wfd_ie, wfd_ielen, WFD_ATTR_DEVICE_INFO, attr_content, &attr_contentlen); ++ if ( attr_contentlen ) ++ { ++ pwdinfo->wfd_info.peer_rtsp_ctrlport = RTW_GET_BE16( attr_content + 2 ); ++ DBG_8192C( "[%s] Peer PORT NUM = %d\n", __FUNCTION__, pwdinfo->wfd_info.peer_rtsp_ctrlport ); ++ } ++ } ++#endif // CONFIG_WFD ++ ++ return( result ); ++} ++ ++u8 process_p2p_group_negotation_resp( struct wifidirect_info *pwdinfo, u8 *pframe, uint len ) ++{ ++ u8 result = P2P_STATUS_SUCCESS; ++ u32 p2p_ielen, wps_ielen; ++ u8 * ies; ++ u32 ies_len; ++ u8 * p2p_ie; ++#ifdef CONFIG_WFD ++ u8 wfd_ie[ 128 ] = { 0x00 }; ++ u32 wfd_ielen = 0; ++#endif // CONFIG_WFD ++ ++ ies = pframe + _PUBLIC_ACTION_IE_OFFSET_; ++ ies_len = len - _PUBLIC_ACTION_IE_OFFSET_; ++ ++ // Be able to know which one is the P2P GO and which one is P2P client. ++ ++ if ( rtw_get_wps_ie( ies, ies_len, NULL, &wps_ielen) ) ++ { ++ ++ } ++ else ++ { ++ DBG_8192C( "[%s] WPS IE not Found!!\n", __FUNCTION__ ); ++ result = P2P_STATUS_FAIL_INCOMPATIBLE_PARAM; ++ rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_FAIL); ++ } ++ ++ p2p_ie = rtw_get_p2p_ie( ies, ies_len, NULL, &p2p_ielen ); ++ if ( !p2p_ie ) ++ { ++ rtw_p2p_set_role(pwdinfo, P2P_ROLE_DEVICE); ++ rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_FAIL); ++ result = P2P_STATUS_FAIL_INCOMPATIBLE_PARAM; ++ } ++ else ++ { ++ u8 attr_content = 0x00; ++ u32 attr_contentlen = 0; ++ u8 operatingch_info[5] = { 0x00 }; ++ uint ch_cnt = 0; ++ u8 ch_content[50] = { 0x00 }; ++ u8 groupid[ 38 ]; ++ ++ while ( p2p_ie ) // Found the P2P IE. ++ { ++ ++ rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_STATUS, &attr_content, &attr_contentlen); ++ if ( attr_contentlen == 1 ) ++ { ++ DBG_8192C( "[%s] Status = %d\n", __FUNCTION__, attr_content ); ++ if ( attr_content == P2P_STATUS_SUCCESS ) ++ { ++ // Do nothing. ++ } ++ else ++ { ++ rtw_p2p_set_role(pwdinfo, P2P_ROLE_DEVICE); ++ rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_FAIL); ++ result = attr_content; ++ break; ++ } ++ } ++ ++ // Try to get the peer's interface address ++ attr_contentlen = 0; ++ if ( rtw_get_p2p_attr_content( p2p_ie, p2p_ielen, P2P_ATTR_INTENTED_IF_ADDR, pwdinfo->p2p_peer_interface_addr, &attr_contentlen ) ) ++ { ++ if ( attr_contentlen != ETH_ALEN ) ++ { ++ _rtw_memset( pwdinfo->p2p_peer_interface_addr, 0x00, ETH_ALEN ); ++ } ++ } ++ ++ // Try to get the peer's intent and tie breaker value. ++ attr_content = 0x00; ++ attr_contentlen = 0; ++ if ( rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_GO_INTENT , &attr_content, &attr_contentlen) ) ++ { ++ DBG_8192C( "[%s] GO Intent = %d, tie = %d\n", __FUNCTION__, attr_content >> 1, attr_content & 0x01 ); ++ pwdinfo->peer_intent = attr_content; // include both intent and tie breaker values. ++ ++ if ( pwdinfo->intent == ( pwdinfo->peer_intent >> 1 ) ) ++ { ++ // Try to match the tie breaker value ++ if ( pwdinfo->intent == P2P_MAX_INTENT ) ++ { ++ rtw_p2p_set_role(pwdinfo, P2P_ROLE_DEVICE); ++ result = P2P_STATUS_FAIL_BOTH_GOINTENT_15; ++ rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_FAIL); ++ } ++ else ++ { ++ rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_OK); ++ if ( attr_content & 0x01 ) ++ { ++ rtw_p2p_set_role(pwdinfo, P2P_ROLE_CLIENT); ++ } ++ else ++ { ++ rtw_p2p_set_role(pwdinfo, P2P_ROLE_GO); ++ } ++ } ++ } ++ else if ( pwdinfo->intent > ( pwdinfo->peer_intent >> 1 ) ) ++ { ++ rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_OK); ++ rtw_p2p_set_role(pwdinfo, P2P_ROLE_GO); ++ } ++ else ++ { ++ rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_OK); ++ rtw_p2p_set_role(pwdinfo, P2P_ROLE_CLIENT); ++ } ++ ++ if(rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) ++ { ++ // Store the group id information. ++ _rtw_memcpy( pwdinfo->groupid_info.go_device_addr, pwdinfo->device_addr, ETH_ALEN ); ++ _rtw_memcpy( pwdinfo->groupid_info.ssid, pwdinfo->nego_ssid, pwdinfo->nego_ssidlen ); ++ ++ } ++ } ++ ++ // Try to get the operation channel information ++ ++ attr_contentlen = 0; ++ if ( rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_OPERATING_CH, operatingch_info, &attr_contentlen)) ++ { ++ DBG_8192C( "[%s] Peer's operating channel = %d\n", __FUNCTION__, operatingch_info[4] ); ++ pwdinfo->peer_operating_ch = operatingch_info[4]; ++ } ++ ++ // Try to get the channel list information ++ if ( rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_CH_LIST, ch_content, &ch_cnt) ) ++ { ++ pwdinfo->channel_cnt = ch_content[ 4 ]; // Number of Channels ++ _rtw_memcpy( pwdinfo->channel_list, &ch_content[ 5 ], pwdinfo->channel_cnt ); // Channel List ++ DBG_8192C( "[%s] channel count = %d\n", __FUNCTION__, pwdinfo->channel_cnt ); ++ } ++ else ++ { ++ DBG_8192C( "[%s] channel list attribute not found!\n", __FUNCTION__); ++ } ++ ++ // Try to get the group id information if peer is GO ++ attr_contentlen = 0; ++ _rtw_memset( groupid, 0x00, 38 ); ++ if ( rtw_get_p2p_attr_content( p2p_ie, p2p_ielen, P2P_ATTR_GROUP_ID, groupid, &attr_contentlen) ) ++ { ++ _rtw_memcpy( pwdinfo->groupid_info.go_device_addr, &groupid[0], ETH_ALEN ); ++ _rtw_memcpy( pwdinfo->groupid_info.ssid, &groupid[6], attr_contentlen - ETH_ALEN ); ++ } ++ ++ //Get the next P2P IE ++ p2p_ie = rtw_get_p2p_ie(p2p_ie+p2p_ielen, ies_len -(p2p_ie -ies + p2p_ielen), NULL, &p2p_ielen); ++ } ++ ++ } ++ ++#ifdef CONFIG_WFD ++ // Added by Albert 20111122 ++ // Try to get the TCP port information when receiving the negotiation response. ++ if ( rtw_get_wfd_ie( pframe + _PUBLIC_ACTION_IE_OFFSET_, len - _PUBLIC_ACTION_IE_OFFSET_, wfd_ie, &wfd_ielen ) ) ++ { ++ u8 attr_content[ 10 ] = { 0x00 }; ++ u32 attr_contentlen = 0; ++ ++ DBG_8192C( "[%s] WFD IE Found!!\n", __FUNCTION__ ); ++ rtw_get_wfd_attr_content( wfd_ie, wfd_ielen, WFD_ATTR_DEVICE_INFO, attr_content, &attr_contentlen); ++ if ( attr_contentlen ) ++ { ++ pwdinfo->wfd_info.peer_rtsp_ctrlport = RTW_GET_BE16( attr_content + 2 ); ++ DBG_8192C( "[%s] Peer PORT NUM = %d\n", __FUNCTION__, pwdinfo->wfd_info.peer_rtsp_ctrlport ); ++ } ++ } ++#endif // CONFIG_WFD ++ ++ return( result ); ++ ++} ++ ++u8 process_p2p_group_negotation_confirm( struct wifidirect_info *pwdinfo, u8 *pframe, uint len ) ++{ ++ u8 * ies; ++ u32 ies_len; ++ u8 * p2p_ie; ++ u32 p2p_ielen = 0; ++ u8 result = P2P_STATUS_SUCCESS; ++ ++ ies = pframe + _PUBLIC_ACTION_IE_OFFSET_; ++ ies_len = len - _PUBLIC_ACTION_IE_OFFSET_; ++ ++ p2p_ie = rtw_get_p2p_ie( ies, ies_len, NULL, &p2p_ielen ); ++ while ( p2p_ie ) // Found the P2P IE. ++ { ++ u8 attr_content = 0x00, operatingch_info[5] = { 0x00 }; ++ u8 groupid[ 38 ] = { 0x00 }; ++ u32 attr_contentlen = 0; ++ ++ pwdinfo->negotiation_dialog_token = 1; ++ rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_STATUS, &attr_content, &attr_contentlen); ++ if ( attr_contentlen == 1 ) ++ { ++ DBG_8192C( "[%s] Status = %d\n", __FUNCTION__, attr_content ); ++ result = attr_content; ++ ++ if ( attr_content == P2P_STATUS_SUCCESS ) ++ { ++ u8 bcancelled = 0; ++ ++ _cancel_timer( &pwdinfo->restore_p2p_state_timer, &bcancelled ); ++ ++ // Commented by Albert 20100911 ++ // Todo: Need to handle the case which both Intents are the same. ++ rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_OK); ++ if ( ( pwdinfo->intent ) > ( pwdinfo->peer_intent >> 1 ) ) ++ { ++ rtw_p2p_set_role(pwdinfo, P2P_ROLE_GO); ++ } ++ else if ( ( pwdinfo->intent ) < ( pwdinfo->peer_intent >> 1 ) ) ++ { ++ rtw_p2p_set_role(pwdinfo, P2P_ROLE_CLIENT); ++ } ++ else ++ { ++ // Have to compare the Tie Breaker ++ if ( pwdinfo->peer_intent & 0x01 ) ++ { ++ rtw_p2p_set_role(pwdinfo, P2P_ROLE_CLIENT); ++ } ++ else ++ { ++ rtw_p2p_set_role(pwdinfo, P2P_ROLE_GO); ++ } ++ } ++ } ++ else ++ { ++ rtw_p2p_set_role(pwdinfo, P2P_ROLE_DEVICE); ++ rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_FAIL); ++ break; ++ } ++ } ++ ++ // Try to get the group id information ++ attr_contentlen = 0; ++ _rtw_memset( groupid, 0x00, 38 ); ++ if ( rtw_get_p2p_attr_content( p2p_ie, p2p_ielen, P2P_ATTR_GROUP_ID, groupid, &attr_contentlen) ) ++ { ++ DBG_8192C( "[%s] Ssid = %s, ssidlen = %d\n", __FUNCTION__, &groupid[ETH_ALEN], strlen(&groupid[ETH_ALEN]) ); ++ _rtw_memcpy( pwdinfo->groupid_info.go_device_addr, &groupid[0], ETH_ALEN ); ++ _rtw_memcpy( pwdinfo->groupid_info.ssid, &groupid[6], attr_contentlen - ETH_ALEN ); ++ } ++ ++ attr_contentlen = 0; ++ if ( rtw_get_p2p_attr_content(p2p_ie, p2p_ielen, P2P_ATTR_OPERATING_CH, operatingch_info, &attr_contentlen) ) ++ { ++ DBG_8192C( "[%s] Peer's operating channel = %d\n", __FUNCTION__, operatingch_info[4] ); ++ pwdinfo->peer_operating_ch = operatingch_info[4]; ++ } ++ ++ //Get the next P2P IE ++ p2p_ie = rtw_get_p2p_ie(p2p_ie+p2p_ielen, ies_len -(p2p_ie -ies + p2p_ielen), NULL, &p2p_ielen); ++ ++ } ++ ++ return( result ); ++} ++ ++u8 process_p2p_presence_req(struct wifidirect_info *pwdinfo, u8 *pframe, uint len) ++{ ++ u8 *frame_body; ++ u8 dialogToken=0; ++ u8 status = P2P_STATUS_SUCCESS; ++ ++ frame_body = (unsigned char *)(pframe + sizeof(struct rtw_ieee80211_hdr_3addr)); ++ ++ dialogToken = frame_body[6]; ++ ++ //todo: check NoA attribute ++ ++ issue_p2p_presence_resp(pwdinfo, GetAddr2Ptr(pframe), status, dialogToken); ++ ++ return _TRUE; ++} ++ ++void process_p2p_ps_ie(PADAPTER padapter, u8 *IEs, u32 IELength) ++{ ++ u8 * ies; ++ u32 ies_len; ++ u8 * p2p_ie; ++ u32 p2p_ielen = 0; ++ u8 noa_attr[MAX_P2P_IE_LEN] = { 0x00 };// NoA length should be n*(13) + 2 ++ u32 attr_contentlen = 0; ++ ++ struct wifidirect_info *pwdinfo = &( padapter->wdinfo ); ++ u8 find_p2p = _FALSE, find_p2p_ps = _FALSE; ++ u8 noa_offset, noa_num, noa_index; ++ ++_func_enter_; ++ ++ if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) ++ { ++ return; ++ } ++ ++ if(IELength <= _BEACON_IE_OFFSET_) ++ return; ++ ++ ies = IEs + _BEACON_IE_OFFSET_; ++ ies_len = IELength - _BEACON_IE_OFFSET_; ++ ++ p2p_ie = rtw_get_p2p_ie( ies, ies_len, NULL, &p2p_ielen); ++ ++ while(p2p_ie) ++ { ++ find_p2p = _TRUE; ++ // Get Notice of Absence IE. ++ if(rtw_get_p2p_attr_content( p2p_ie, p2p_ielen, P2P_ATTR_NOA, noa_attr, &attr_contentlen)) ++ { ++ find_p2p_ps = _TRUE; ++ noa_index = noa_attr[0]; ++ ++ if( (pwdinfo->p2p_ps_enable == _FALSE) || ++ (noa_index != pwdinfo->noa_index) )// if index change, driver should reconfigure related setting. ++ { ++ pwdinfo->noa_index = noa_index; ++ pwdinfo->opp_ps = noa_attr[1] >> 7; ++ pwdinfo->ctwindow = noa_attr[1] & 0x7F; ++ ++ noa_offset = 2; ++ noa_num = 0; ++ // NoA length should be n*(13) + 2 ++ if(attr_contentlen > 2) ++ { ++ while(noa_offset < attr_contentlen) ++ { ++ //_rtw_memcpy(&wifidirect_info->noa_count[noa_num], &noa_attr[noa_offset], 1); ++ pwdinfo->noa_count[noa_num] = noa_attr[noa_offset]; ++ noa_offset += 1; ++ ++ _rtw_memcpy(&pwdinfo->noa_duration[noa_num], &noa_attr[noa_offset], 4); ++ noa_offset += 4; ++ ++ _rtw_memcpy(&pwdinfo->noa_interval[noa_num], &noa_attr[noa_offset], 4); ++ noa_offset += 4; ++ ++ _rtw_memcpy(&pwdinfo->noa_start_time[noa_num], &noa_attr[noa_offset], 4); ++ noa_offset += 4; ++ ++ noa_num++; ++ } ++ } ++ pwdinfo->noa_num = noa_num; ++ ++ if( pwdinfo->opp_ps == 1 ) ++ { ++ pwdinfo->p2p_ps_enable = _TRUE; ++ // driver should wait LPS for entering CTWindow ++ if(padapter->pwrctrlpriv.bFwCurrentInPSMode == _TRUE) ++ { ++ p2p_ps_wk_cmd(padapter, P2P_PS_ENABLE, 1); ++ } ++ } ++ else if( pwdinfo->noa_num > 0 ) ++ { ++ pwdinfo->p2p_ps_enable = _TRUE; ++ p2p_ps_wk_cmd(padapter, P2P_PS_ENABLE, 1); ++ } ++ else if( pwdinfo->p2p_ps_enable == _TRUE) ++ { ++ p2p_ps_wk_cmd(padapter, P2P_PS_DISABLE, 1); ++ } ++ } ++ ++ break; // find target, just break. ++ } ++ ++ //Get the next P2P IE ++ p2p_ie = rtw_get_p2p_ie(p2p_ie+p2p_ielen, ies_len -(p2p_ie -ies + p2p_ielen), NULL, &p2p_ielen); ++ ++ } ++ ++ if(find_p2p == _TRUE) ++ { ++ if( (pwdinfo->p2p_ps_enable == _TRUE) && (find_p2p_ps == _FALSE) ) ++ { ++ p2p_ps_wk_cmd(padapter, P2P_PS_DISABLE, 1); ++ } ++ } ++ ++_func_exit_; ++} ++ ++void find_phase_handler( _adapter* padapter ) ++{ ++ struct wifidirect_info *pwdinfo = &padapter->wdinfo; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ NDIS_802_11_SSID ssid; ++ _irqL irqL; ++ u8 _status = 0; ++ ++_func_enter_; ++ ++ _rtw_memset((unsigned char*)&ssid, 0, sizeof(NDIS_802_11_SSID)); ++ _rtw_memcpy(ssid.Ssid, pwdinfo->p2p_wildcard_ssid, P2P_WILDCARD_SSID_LEN ); ++ ssid.SsidLength = P2P_WILDCARD_SSID_LEN; ++ ++ rtw_p2p_set_state(pwdinfo, P2P_STATE_FIND_PHASE_SEARCH); ++ ++ _enter_critical_bh(&pmlmepriv->lock, &irqL); ++ _status = rtw_sitesurvey_cmd(padapter, &ssid, 1); ++ _exit_critical_bh(&pmlmepriv->lock, &irqL); ++ ++ ++_func_exit_; ++} ++ ++void restore_p2p_state_handler( _adapter* padapter ) ++{ ++ struct wifidirect_info *pwdinfo = &padapter->wdinfo; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ ++_func_enter_; ++ ++ rtw_p2p_set_state(pwdinfo, rtw_p2p_pre_state(pwdinfo)); ++ if(rtw_p2p_chk_role(pwdinfo, P2P_ROLE_DEVICE)) ++ { ++ // In the P2P client mode, the driver should not switch back to its listen channel ++ // because this P2P client should stay at the operating channel of P2P GO. ++ set_channel_bwmode( padapter, pwdinfo->listen_channel, HAL_PRIME_CHNL_OFFSET_DONT_CARE, HT_CHANNEL_WIDTH_20); ++ } ++_func_exit_; ++} ++ ++void pre_tx_provdisc_handler( _adapter* padapter ) ++{ ++ struct wifidirect_info *pwdinfo = &padapter->wdinfo; ++ u8 val8 = 1; ++_func_enter_; ++ ++ set_channel_bwmode(padapter, pwdinfo->tx_prov_disc_info.peer_channel_num[0], HAL_PRIME_CHNL_OFFSET_DONT_CARE, HT_CHANNEL_WIDTH_20); ++ padapter->HalFunc.SetHwRegHandler(padapter, HW_VAR_MLME_SITESURVEY, (u8 *)(&val8)); ++ issue_probereq_p2p( padapter ); ++ _set_timer( &pwdinfo->pre_tx_scan_timer, P2P_TX_PRESCAN_TIMEOUT ); ++ ++_func_exit_; ++} ++ ++void pre_tx_negoreq_handler( _adapter* padapter ) ++{ ++ struct wifidirect_info *pwdinfo = &padapter->wdinfo; ++ u8 val8 = 1; ++_func_enter_; ++ ++ set_channel_bwmode(padapter, pwdinfo->nego_req_info.peer_channel_num[0], HAL_PRIME_CHNL_OFFSET_DONT_CARE, HT_CHANNEL_WIDTH_20); ++ padapter->HalFunc.SetHwRegHandler(padapter, HW_VAR_MLME_SITESURVEY, (u8 *)(&val8)); ++ issue_probereq_p2p( padapter ); ++ _set_timer( &pwdinfo->pre_tx_scan_timer, P2P_TX_PRESCAN_TIMEOUT ); ++ ++_func_exit_; ++} ++ ++#ifdef CONFIG_IOCTL_CFG80211 ++void ro_ch_handler( _adapter* padapter ) ++{ ++ struct cfg80211_wifidirect_info *pcfg80211_wdinfo = &padapter->cfg80211_wdinfo; ++ struct wifidirect_info *pwdinfo = &padapter->wdinfo; ++ struct pwrctrl_priv *pwrpriv = &padapter->pwrctrlpriv; ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++_func_enter_; ++ ++// if( pcfg80211_wdinfo->restore_channel != pmlmeext->cur_channel ) ++// set_channel_bwmode(padapter, pcfg80211_wdinfo->restore_channel, HAL_PRIME_CHNL_OFFSET_DONT_CARE, HT_CHANNEL_WIDTH_20); ++ ++ #if 0 ++ // Disable P2P Listen State ++ if(!rtw_p2p_chk_role(pwdinfo, P2P_ROLE_CLIENT) && !rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) ++ { ++ if(!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) ++ { ++ _cancel_timer_ex( &pwdinfo->find_phase_timer ); ++ _cancel_timer_ex( &pwdinfo->restore_p2p_state_timer ); ++ _cancel_timer_ex( &pwdinfo->pre_tx_scan_timer); ++ ++ rtw_p2p_set_state(pwdinfo, P2P_STATE_NONE); ++ _rtw_memset(pwdinfo, 0x00, sizeof(struct wifidirect_info)); ++ ++ if(pwrpriv->bips_processing == _FALSE){ ++ rtw_set_pwr_state_check_timer(pwrpriv); ++ } ++ } ++ } ++ else ++ #endif ++ { ++ if( pcfg80211_wdinfo->restore_channel != pmlmeext->cur_channel ) ++ { ++ pmlmeext->cur_channel = pcfg80211_wdinfo->restore_channel; ++ set_channel_bwmode(padapter, pmlmeext->cur_channel, HAL_PRIME_CHNL_OFFSET_DONT_CARE, HT_CHANNEL_WIDTH_20); ++ } ++ ++ rtw_p2p_set_state(pwdinfo, rtw_p2p_pre_state(pwdinfo)); ++#ifdef CONFIG_DEBUG_CFG80211 ++ DBG_871X("%s, role=%d, p2p_state=%d\n", __func__, rtw_p2p_role(pwdinfo), rtw_p2p_state(pwdinfo)); ++#endif ++ } ++ ++ cfg80211_remain_on_channel_expired(pcfg80211_wdinfo->remain_on_ch_dev, ++ pcfg80211_wdinfo->remain_on_ch_cookie, ++ &pcfg80211_wdinfo->remain_on_ch_channel, ++ pcfg80211_wdinfo->remain_on_ch_type, GFP_KERNEL); ++_func_exit_; ++} ++#endif //CONFIG_IOCTL_CFG80211 ++ ++void p2p_protocol_wk_hdl(_adapter *padapter, int intCmdType) ++{ ++ struct wifidirect_info *pwdinfo= &(padapter->wdinfo); ++ ++_func_enter_; ++ ++ switch(intCmdType) ++ { ++ case P2P_FIND_PHASE_WK: ++ { ++ find_phase_handler( padapter ); ++ break; ++ } ++ case P2P_RESTORE_STATE_WK: ++ { ++ restore_p2p_state_handler( padapter ); ++ break; ++ } ++ case P2P_PRE_TX_PROVDISC_PROCESS_WK: ++ { ++ pre_tx_provdisc_handler( padapter ); ++ break; ++ } ++ case P2P_PRE_TX_NEGOREQ_PROCESS_WK: ++ { ++ pre_tx_negoreq_handler( padapter ); ++ break; ++ } ++#ifdef CONFIG_IOCTL_CFG80211 ++ case P2P_RO_CH_WK: ++ { ++ ro_ch_handler( padapter ); ++ break; ++ } ++#endif //CONFIG_IOCTL_CFG80211 ++ } ++ ++_func_exit_; ++} ++ ++ ++ ++void p2p_ps_wk_hdl(_adapter *padapter, u8 p2p_ps_state) ++{ ++ struct pwrctrl_priv *pwrpriv = &padapter->pwrctrlpriv; ++ struct wifidirect_info *pwdinfo= &(padapter->wdinfo); ++ ++_func_enter_; ++ ++ // Pre action for p2p state ++ switch(p2p_ps_state) ++ { ++ case P2P_PS_ENABLE: ++ if( pwdinfo->ctwindow > 0 ) ++ { ++ if(pwrpriv->smart_ps != 0) ++ { ++ pwrpriv->smart_ps = 0; ++ DBG_871X("%s(): Enter CTW, change SmartPS\n", __FUNCTION__); ++ padapter->HalFunc.SetHwRegHandler(padapter, HW_VAR_H2C_FW_PWRMODE, (u8 *)(&(padapter->pwrctrlpriv.pwr_mode))); ++ } ++ } ++ break; ++ default: ++ break; ++ } ++ ++ padapter->HalFunc.SetHwRegHandler(padapter, HW_VAR_H2C_FW_P2P_PS_OFFLOAD, (u8 *)(&p2p_ps_state)); ++ ++ // clear P2P SW status ++ if(p2p_ps_state == P2P_PS_DISABLE) ++ { ++ pwdinfo->noa_index = 0; ++ pwdinfo->ctwindow = 0; ++ pwdinfo->opp_ps = 0; ++ pwdinfo->noa_num = 0; ++ pwdinfo->p2p_ps_enable = _FALSE; ++ if(padapter->pwrctrlpriv.bFwCurrentInPSMode == _TRUE) ++ { ++ if(pwrpriv->smart_ps == 0) ++ { ++ pwrpriv->smart_ps = 2; ++ padapter->HalFunc.SetHwRegHandler(padapter, HW_VAR_H2C_FW_PWRMODE, (u8 *)(&(padapter->pwrctrlpriv.pwr_mode))); ++ } ++ } ++ } ++ ++_func_exit_; ++} ++ ++u8 p2p_ps_wk_cmd(_adapter*padapter, u8 p2p_ps_state, u8 enqueue) ++{ ++ struct cmd_obj *ph2c; ++ struct drvextra_cmd_parm *pdrvextra_cmd_parm; ++ struct wifidirect_info *pwdinfo= &(padapter->wdinfo); ++ struct cmd_priv *pcmdpriv = &padapter->cmdpriv; ++ u8 res = _SUCCESS; ++ ++_func_enter_; ++ ++ if ( rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE) || ++ ( pwdinfo->p2p_ps == p2p_ps_state ) ) ++ { ++ return res; ++ } ++ ++ // driver only perform p2p ps when GO have Opp_Ps or NoA ++ if( pwdinfo->p2p_ps_enable ) ++ { ++ pwdinfo->p2p_ps = p2p_ps_state; ++ ++ if(enqueue) ++ { ++ ph2c = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj)); ++ if(ph2c==NULL){ ++ res= _FAIL; ++ goto exit; ++ } ++ ++ pdrvextra_cmd_parm = (struct drvextra_cmd_parm*)rtw_zmalloc(sizeof(struct drvextra_cmd_parm)); ++ if(pdrvextra_cmd_parm==NULL){ ++ rtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj)); ++ res= _FAIL; ++ goto exit; ++ } ++ ++ pdrvextra_cmd_parm->ec_id = P2P_PS_WK_CID; ++ pdrvextra_cmd_parm->type_size = p2p_ps_state; ++ pdrvextra_cmd_parm->pbuf = NULL; ++ ++ init_h2fwcmd_w_parm_no_rsp(ph2c, pdrvextra_cmd_parm, GEN_CMD_CODE(_Set_Drv_Extra)); ++ ++ res = rtw_enqueue_cmd(pcmdpriv, ph2c); ++ } ++ else ++ { ++ p2p_ps_wk_hdl(padapter, p2p_ps_state); ++ } ++ } ++ ++exit: ++ ++_func_exit_; ++ ++ return res; ++ ++} ++ ++static void restore_p2p_state_timer_process (void *FunctionContext) ++{ ++ _adapter *adapter = (_adapter *)FunctionContext; ++ struct wifidirect_info *pwdinfo = &adapter->wdinfo; ++ ++ if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) ++ return; ++ ++ p2p_protocol_wk_cmd( adapter, P2P_RESTORE_STATE_WK ); ++} ++ ++static void pre_tx_scan_timer_process (void *FunctionContext) ++{ ++ _adapter *adapter = (_adapter *) FunctionContext; ++ struct wifidirect_info *pwdinfo = &adapter->wdinfo; ++ _irqL irqL; ++ struct mlme_priv *pmlmepriv = &adapter->mlmepriv; ++ u8 _status = 0; ++ ++ if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) ++ return; ++ ++ _enter_critical_bh(&pmlmepriv->lock, &irqL); ++ ++ // Commented by Albert 20110805 ++ // Todo: Use the issuing probe request directly instead of using the rtw_sitesurvey_cmd!! ++ ++ if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_TX_PROVISION_DIS_REQ)) ++ { ++ if ( _TRUE == pwdinfo->tx_prov_disc_info.benable ) // the provision discovery request frame is trigger to send or not ++ { ++ p2p_protocol_wk_cmd( adapter, P2P_PRE_TX_PROVDISC_PROCESS_WK ); ++ //issue_probereq_p2p( adapter ); ++ //_set_timer( &pwdinfo->pre_tx_scan_timer, P2P_TX_PRESCAN_TIMEOUT ); ++ } ++ } ++ else if (rtw_p2p_chk_state(pwdinfo, P2P_STATE_GONEGO_ING)) ++ { ++ if ( _TRUE == pwdinfo->nego_req_info.benable ) ++ { ++ p2p_protocol_wk_cmd( adapter, P2P_PRE_TX_NEGOREQ_PROCESS_WK ); ++ //issue_probereq_p2p( adapter ); ++ //_set_timer( &pwdinfo->pre_tx_scan_timer, P2P_TX_PRESCAN_TIMEOUT ); ++ } ++ } ++ else ++ { ++ DBG_8192C( "[%s] p2p_state is %d, ignore!!\n", __FUNCTION__, rtw_p2p_state(pwdinfo) ); ++ } ++ ++ _exit_critical_bh(&pmlmepriv->lock, &irqL); ++} ++ ++static void find_phase_timer_process (void *FunctionContext) ++{ ++ _adapter *adapter = (_adapter *)FunctionContext; ++ struct wifidirect_info *pwdinfo = &adapter->wdinfo; ++ ++ if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) ++ return; ++ ++ adapter->wdinfo.find_phase_state_exchange_cnt++; ++ ++ p2p_protocol_wk_cmd( adapter, P2P_FIND_PHASE_WK ); ++} ++ ++#ifdef CONFIG_IOCTL_CFG80211 ++static void ro_ch_timer_process (void *FunctionContext) ++{ ++ _adapter *adapter = (_adapter *)FunctionContext; ++ ++ //printk("%s \n", __FUNCTION__); ++ ++ p2p_protocol_wk_cmd( adapter, P2P_RO_CH_WK); ++} ++ ++void rtw_init_cfg80211_wifidirect_info( _adapter* padapter) ++{ ++ struct cfg80211_wifidirect_info *pcfg80211_wdinfo = &padapter->cfg80211_wdinfo; ++ ++ _rtw_memset(pcfg80211_wdinfo, 0x00, sizeof(struct cfg80211_wifidirect_info) ); ++ ++ _init_timer( &pcfg80211_wdinfo->remain_on_ch_timer, padapter->pnetdev, ro_ch_timer_process, padapter ); ++} ++#endif //CONFIG_IOCTL_CFG80211 ++ ++void init_wifidirect_info( _adapter* padapter, enum P2P_ROLE role) ++{ ++ struct wifidirect_info *pwdinfo; ++ ++ pwdinfo = &padapter->wdinfo; ++ ++ pwdinfo->padapter = padapter; ++ ++ //init device&interface address ++ _rtw_memcpy(pwdinfo->device_addr, myid(&(padapter->eeprompriv)), ETH_ALEN); ++ _rtw_memcpy(pwdinfo->interface_addr, myid(&(padapter->eeprompriv)), ETH_ALEN); ++ ++ // 1, 6, 11 are the social channel defined in the WiFi Direct specification. ++ pwdinfo->social_chan[0] = 1; ++ pwdinfo->social_chan[1] = 6; ++ pwdinfo->social_chan[2] = 11; ++ pwdinfo->social_chan[3] = 0; // channel 0 for scanning ending in site survey function. ++ ++ // Use the channel 11 as the listen channel ++ pwdinfo->listen_channel = 11; ++ ++ if (role == P2P_ROLE_DEVICE) ++ { ++ rtw_p2p_set_role(pwdinfo, P2P_ROLE_DEVICE); ++ rtw_p2p_set_state(pwdinfo, P2P_STATE_LISTEN); ++ pwdinfo->intent = 1; ++ } ++ else if (role == P2P_ROLE_CLIENT) ++ { ++ rtw_p2p_set_role(pwdinfo, P2P_ROLE_CLIENT); ++ rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_OK); ++ pwdinfo->intent = 1; ++ } ++ else if (role == P2P_ROLE_GO) ++ { ++ rtw_p2p_set_role(pwdinfo, P2P_ROLE_GO); ++ rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_OK); ++ pwdinfo->intent = 15; ++ } ++ ++ //rtw_p2p_set_pre_state(pwdinfo, P2P_STATE_NONE); ++ rtw_p2p_set_pre_state(pwdinfo, P2P_STATE_LISTEN); ++ ++// Use the OFDM rate in the P2P probe response frame. ( 6(B), 9(B), 12, 18, 24, 36, 48, 54 ) ++ pwdinfo->support_rate[0] = 0x8c; // 6(B) ++ pwdinfo->support_rate[1] = 0x92; // 9(B) ++ pwdinfo->support_rate[2] = 0x18; // 12 ++ pwdinfo->support_rate[3] = 0x24; // 18 ++ pwdinfo->support_rate[4] = 0x30; // 24 ++ pwdinfo->support_rate[5] = 0x48; // 36 ++ pwdinfo->support_rate[6] = 0x60; // 48 ++ pwdinfo->support_rate[7] = 0x6c; // 54 ++ ++ _rtw_memcpy( ( void* ) pwdinfo->p2p_wildcard_ssid, "DIRECT-", 7 ); ++ ++ _rtw_memset( pwdinfo->device_name, 0x00, WPS_MAX_DEVICE_NAME_LEN ); ++ _rtw_memcpy( pwdinfo->device_name, "Realtek DMP Device", 18 ); ++ pwdinfo->device_name_len = 18; ++ ++ _rtw_memset( &pwdinfo->invitereq_info, 0x00, sizeof( struct tx_invite_req_info ) ); ++ pwdinfo->invitereq_info.token = 3; // Token used for P2P invitation request frame. ++ pwdinfo->invitereq_info.peer_operation_ch = pwdinfo->listen_channel; ++ ++ _rtw_memset( &pwdinfo->inviteresp_info, 0x00, sizeof( struct tx_invite_resp_info ) ); ++ pwdinfo->inviteresp_info.token = 0; ++ ++ pwdinfo->profileindex = 0; ++ _rtw_memset( &pwdinfo->profileinfo[ 0 ], 0x00, sizeof( struct profile_info ) * P2P_MAX_PERSISTENT_GROUP_NUM ); ++ ++ _init_timer( &pwdinfo->find_phase_timer, padapter->pnetdev, find_phase_timer_process, padapter ); ++ _init_timer( &pwdinfo->restore_p2p_state_timer, padapter->pnetdev, restore_p2p_state_timer_process, padapter ); ++ _init_timer( &pwdinfo->pre_tx_scan_timer, padapter->pnetdev, pre_tx_scan_timer_process, padapter ); ++ ++ pwdinfo->find_phase_state_exchange_cnt = 0; ++ ++ pwdinfo->listen_dwell = ( u8 ) (( rtw_get_current_time() % 3 ) + 1); ++ //DBG_8192C( "[%s] listen_dwell time is %d00ms\n", __FUNCTION__, pwdinfo->listen_dwell ); ++ ++ _rtw_memset( &pwdinfo->tx_prov_disc_info, 0x00, sizeof( struct tx_provdisc_req_info ) ); ++ pwdinfo->tx_prov_disc_info.wps_config_method_request = WPS_CM_NONE; ++ ++ _rtw_memset( &pwdinfo->nego_req_info, 0x00, sizeof( struct tx_nego_req_info ) ); ++ ++ pwdinfo->device_password_id_for_nego = WPS_DPID_PBC; ++ pwdinfo->negotiation_dialog_token = 1; ++ ++ _rtw_memset( pwdinfo->nego_ssid, 0x00, WLAN_SSID_MAXLEN ); ++ pwdinfo->nego_ssidlen = 0; ++ ++ pwdinfo->ui_got_wps_info = P2P_NO_WPSINFO; ++#ifdef CONFIG_WFD ++ pwdinfo->supported_wps_cm = WPS_CONFIG_METHOD_DISPLAY; ++ _rtw_memset( &pwdinfo->wfd_info, 0x00, sizeof( struct wifi_display_info ) ); ++ pwdinfo->wfd_info.rtsp_ctrlport = 554; ++ pwdinfo->wfd_info.peer_rtsp_ctrlport = 0; // Reset to 0 ++#else ++ pwdinfo->supported_wps_cm = WPS_CONFIG_METHOD_DISPLAY | WPS_CONFIG_METHOD_PBC | WPS_CONFIG_METHOD_KEYPAD; ++#endif //CONFIG_WFD ++ pwdinfo->channel_cnt = 0; ++ _rtw_memset( pwdinfo->channel_list, 0x00, 13 ); ++ ++ _rtw_memset( pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, 0x00, 4 ); ++ _rtw_memset( pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req, '0', 3 ); ++ _rtw_memset( &pwdinfo->groupid_info, 0x00, sizeof( struct group_id_info ) ); ++ ++} ++ ++#ifdef CONFIG_IOCTL_CFG80211 ++int rtw_p2p_check_frames(_adapter *padapter, const u8 *buf, u32 len, u8 tx) ++{ ++ int is_p2p_frame = (-1); ++ unsigned char *frame_body; ++ u8 category, action, OUI_Subtype, dialogToken=0; ++ struct rtw_wdev_priv *pwdev_priv = wdev_to_priv(padapter->rtw_wdev); ++ ++ frame_body = (unsigned char *)(buf + sizeof(struct rtw_ieee80211_hdr_3addr)); ++ category = frame_body[0]; ++ //just for check ++ if(category == RTW_WLAN_CATEGORY_PUBLIC) ++ { ++ action = frame_body[ 1 ]; ++ OUI_Subtype = frame_body[ 6 ]; ++ dialogToken = frame_body[7]; ++ ++ if ( action == ACT_PUBLIC_P2P ) ++ { ++#ifdef CONFIG_DEBUG_CFG80211 ++ DBG_871X("ACTION_CATEGORY_PUBLIC: ACT_PUBLIC_P2P, OUI=0x%x, OUI_Subtype=%d, dialogToken=%d\n", ++ cpu_to_be32( *( ( u32* ) ( frame_body + 2 ) ) ), OUI_Subtype, dialogToken); ++#endif ++ ++ is_p2p_frame = OUI_Subtype; ++ ++ switch( OUI_Subtype )//OUI Subtype ++ { ++ case P2P_GO_NEGO_REQ: ++ DBG_871X("RTW_%s:P2P_GO_NEGO_REQ, dialogToken=%d\n", (tx==_TRUE)?"Tx":"Rx", dialogToken); ++ ++ if(tx) ++ { ++ if(pwdev_priv->provdisc_req_issued == _FALSE) ++ rtw_cfg80211_issue_p2p_provision_request(padapter, buf, len); ++ ++ //pwdev_priv->provdisc_req_issued = _FALSE; ++ } ++ ++ break; ++ case P2P_GO_NEGO_RESP: ++ DBG_871X("RTW_%s:P2P_GO_NEGO_RESP, dialogToken=%d\n", (tx==_TRUE)?"Tx":"Rx", dialogToken); ++ ++ if(!tx) ++ pwdev_priv->provdisc_req_issued = _FALSE; ++ ++ break; ++ case P2P_GO_NEGO_CONF: ++ DBG_871X("RTW_%s:P2P_GO_NEGO_CONF, dialogToken=%d\n", (tx==_TRUE)?"Tx":"Rx", dialogToken); ++ break; ++ case P2P_INVIT_REQ: ++ DBG_871X("RTW_%s:P2P_INVIT_REQ, dialogToken=%d\n", (tx==_TRUE)?"Tx":"Rx", dialogToken); ++ break; ++ case P2P_INVIT_RESP: ++ DBG_871X("RTW_%s:P2P_INVIT_RESP, dialogToken=%d\n", (tx==_TRUE)?"Tx":"Rx", dialogToken); ++ break; ++ case P2P_DEVDISC_REQ: ++ DBG_871X("RTW_%s:P2P_DEVDISC_REQ, dialogToken=%d\n", (tx==_TRUE)?"Tx":"Rx", dialogToken); ++ break; ++ case P2P_DEVDISC_RESP: ++ DBG_871X("RTW_%s:P2P_DEVDISC_RESP, dialogToken=%d\n", (tx==_TRUE)?"Tx":"Rx", dialogToken); ++ break; ++ case P2P_PROVISION_DISC_REQ: ++ { ++ size_t frame_body_len = len - sizeof(struct rtw_ieee80211_hdr_3addr); ++ u8 *p2p_ie; ++ uint p2p_ielen = 0; ++ uint contentlen = 0; ++ ++ DBG_871X("RTW_%s:P2P_PROVISION_DISC_REQ, dialogToken=%d\n", (tx==_TRUE)?"Tx":"Rx", dialogToken); ++ ++ //if(tx) ++ { ++ pwdev_priv->provdisc_req_issued = _FALSE; ++ ++ if( (p2p_ie=rtw_get_p2p_ie( frame_body + _PUBLIC_ACTION_IE_OFFSET_, frame_body_len - _PUBLIC_ACTION_IE_OFFSET_, NULL, &p2p_ielen))) ++ { ++ ++ if(rtw_get_p2p_attr_content( p2p_ie, p2p_ielen, P2P_ATTR_GROUP_ID, NULL, &contentlen)) ++ { ++ pwdev_priv->provdisc_req_issued = _FALSE;//case: p2p_client join p2p GO ++ } ++ else ++ { ++ DBG_871X("provdisc_req_issued is _TRUE\n"); ++ pwdev_priv->provdisc_req_issued = _TRUE;//case: p2p_devices connection before Nego req. ++ } ++ ++ } ++ } ++ } ++ break; ++ case P2P_PROVISION_DISC_RESP: ++ DBG_871X("RTW_%s:P2P_PROVISION_DISC_RESP, dialogToken=%d\n", (tx==_TRUE)?"Tx":"Rx", dialogToken); ++ break; ++ default: ++ DBG_871X("RTW_%s:OUI_Subtype=%d, dialogToken=%d\n", (tx==_TRUE)?"Tx":"Rx", OUI_Subtype, dialogToken); ++ break; ++ } ++ ++ } ++ else ++ { ++ DBG_871X("ACTION_CATEGORY_PUBLIC: action=%d, OUI=0x%x, OUI_Subtype=%d, dialogToken=%d\n", ++ action, cpu_to_be32( *( ( u32* ) ( frame_body + 2 ) ) ), OUI_Subtype, dialogToken); ++ } ++ ++ } ++ else if(category == RTW_WLAN_CATEGORY_P2P) ++ { ++ OUI_Subtype = frame_body[5]; ++ dialogToken = frame_body[6]; ++ ++#ifdef CONFIG_DEBUG_CFG80211 ++ DBG_871X("ACTION_CATEGORY_P2P: OUI=0x%x, OUI_Subtype=%d, dialogToken=%d\n", ++ cpu_to_be32( *( ( u32* ) ( frame_body + 1 ) ) ), OUI_Subtype, dialogToken); ++#endif ++ ++ is_p2p_frame = OUI_Subtype; ++ ++ switch(OUI_Subtype) ++ { ++ case P2P_NOTICE_OF_ABSENCE: ++ DBG_871X("RTW_%s:P2P_NOTICE_OF_ABSENCE, dialogToken=%d\n", (tx==_TRUE)?"TX":"RX", dialogToken); ++ break; ++ case P2P_PRESENCE_REQUEST: ++ DBG_871X("RTW_%s:P2P_PRESENCE_REQUEST, dialogToken=%d\n", (tx==_TRUE)?"TX":"RX", dialogToken); ++ break; ++ case P2P_PRESENCE_RESPONSE: ++ DBG_871X("RTW_%s:P2P_PRESENCE_RESPONSE, dialogToken=%d\n", (tx==_TRUE)?"TX":"RX", dialogToken); ++ break; ++ case P2P_GO_DISC_REQUEST: ++ DBG_871X("RTW_%s:P2P_GO_DISC_REQUEST, dialogToken=%d\n", (tx==_TRUE)?"TX":"RX", dialogToken); ++ break; ++ default: ++ DBG_871X("RTW_%s:OUI_Subtype=%d, dialogToken=%d\n", (tx==_TRUE)?"TX":"RX", OUI_Subtype, dialogToken); ++ break; ++ } ++ ++ } ++ else ++ { ++ DBG_871X("%s, action frame category=%d\n", __func__, category); ++ //is_p2p_frame = (-1); ++ } ++ ++ return is_p2p_frame; ++} ++#endif //CONFIG_IOCTL_CFG80211 ++ ++#ifdef CONFIG_DBG_P2P ++char * p2p_role_str[] = { ++ "P2P_ROLE_DISABLE", ++ "P2P_ROLE_DEVICE", ++ "P2P_ROLE_CLIENT", ++ "P2P_ROLE_GO" ++}; ++ ++char * p2p_state_str[] = { ++ "P2P_STATE_NONE", ++ "P2P_STATE_IDLE", ++ "P2P_STATE_LISTEN", ++ "P2P_STATE_SCAN", ++ "P2P_STATE_FIND_PHASE_LISTEN", ++ "P2P_STATE_FIND_PHASE_SEARCH", ++ "P2P_STATE_TX_PROVISION_DIS_REQ", ++ "P2P_STATE_RX_PROVISION_DIS_RSP", ++ "P2P_STATE_RX_PROVISION_DIS_REQ", ++ "P2P_STATE_GONEGO_ING", ++ "P2P_STATE_GONEGO_OK", ++ "P2P_STATE_GONEGO_FAIL", ++ "P2P_STATE_RECV_INVITE_REQ", ++ "P2P_STATE_PROVISIONING_ING", ++ "P2P_STATE_PROVISIONING_DONE" ++}; ++ ++void dbg_rtw_p2p_set_state(struct wifidirect_info *wdinfo, enum P2P_STATE state, const char *caller, int line) ++{ ++ if(!_rtw_p2p_chk_state(wdinfo, state)) { ++ enum P2P_STATE old_state = _rtw_p2p_state(wdinfo); ++ _rtw_p2p_set_state(wdinfo, state); ++ DBG_871X("[CONFIG_DBG_P2P]%s:%d set_state from %s to %s\n", caller, line ++ , p2p_state_str[old_state], p2p_state_str[_rtw_p2p_state(wdinfo)] ++ ); ++ } else { ++ DBG_871X("[CONFIG_DBG_P2P]%s:%d set_state to same state %s\n", caller, line ++ , p2p_state_str[_rtw_p2p_state(wdinfo)] ++ ); ++ } ++} ++void dbg_rtw_p2p_set_pre_state(struct wifidirect_info *wdinfo, enum P2P_STATE state, const char *caller, int line) ++{ ++ if(_rtw_p2p_pre_state(wdinfo) != state) { ++ enum P2P_STATE old_state = _rtw_p2p_pre_state(wdinfo); ++ _rtw_p2p_set_pre_state(wdinfo, state); ++ DBG_871X("[CONFIG_DBG_P2P]%s:%d set_pre_state from %s to %s\n", caller, line ++ , p2p_state_str[old_state], p2p_state_str[_rtw_p2p_pre_state(wdinfo)] ++ ); ++ } else { ++ DBG_871X("[CONFIG_DBG_P2P]%s:%d set_pre_state to same state %s\n", caller, line ++ , p2p_state_str[_rtw_p2p_pre_state(wdinfo)] ++ ); ++ } ++} ++#if 0 ++void dbg_rtw_p2p_restore_state(struct wifidirect_info *wdinfo, const char *caller, int line) ++{ ++ if(wdinfo->pre_p2p_state != -1) { ++ DBG_871X("[CONFIG_DBG_P2P]%s:%d restore from %s to %s\n", caller, line ++ , p2p_state_str[wdinfo->p2p_state], p2p_state_str[wdinfo->pre_p2p_state] ++ ); ++ _rtw_p2p_restore_state(wdinfo); ++ } else { ++ DBG_871X("[CONFIG_DBG_P2P]%s:%d restore no pre state, cur state %s\n", caller, line ++ , p2p_state_str[wdinfo->p2p_state] ++ ); ++ } ++} ++#endif ++void dbg_rtw_p2p_set_role(struct wifidirect_info *wdinfo, enum P2P_ROLE role, const char *caller, int line) ++{ ++ if(wdinfo->role != role) { ++ enum P2P_ROLE old_role = wdinfo->role; ++ _rtw_p2p_set_role(wdinfo, role); ++ DBG_871X("[CONFIG_DBG_P2P]%s:%d set_role from %s to %s\n", caller, line ++ , p2p_role_str[old_role], p2p_role_str[wdinfo->role] ++ ); ++ } else { ++ DBG_871X("[CONFIG_DBG_P2P]%s:%d set_role to same role %s\n", caller, line ++ , p2p_role_str[wdinfo->role] ++ ); ++ } ++} ++#endif //CONFIG_DBG_P2P ++ ++ ++int rtw_p2p_enable(_adapter *padapter, enum P2P_ROLE role) ++{ ++ int ret = _SUCCESS; ++ struct wifidirect_info *pwdinfo= &(padapter->wdinfo); ++ struct pwrctrl_priv *pwrpriv = &padapter->pwrctrlpriv; ++ ++ if (role == P2P_ROLE_DEVICE || role == P2P_ROLE_CLIENT|| role == P2P_ROLE_GO) ++ { ++ u8 channel, ch_offset; ++ u16 bwmode; ++ ++ //leave IPS/Autosuspend ++ if(_FAIL == rtw_pwr_wakeup(padapter)) ++ { ++ ret = _FAIL; ++ goto exit; ++ } ++ ++ #ifdef CONFIG_P2P_AGAINST_NOISE ++ //Sometimes dongle would difficult to receive p2p_probe_req caused by platform noise. Kurt ++ rtw_write8(padapter, 0xc41, 0x42); ++ DBG_8192C("rtw_write8(0x%x)=0x%02x\n", 0xc41, rtw_read8(padapter, 0xc41)); ++ #endif ++ ++ //Enable P2P function ++ init_wifidirect_info(padapter, role); ++ ++ } ++ else if (role == P2P_ROLE_DISABLE) ++ { ++ #ifdef CONFIG_P2P_AGAINST_NOISE ++ rtw_write8(padapter, 0xc41, 0x40); ++ DBG_8192C("rtw_write8(0x%x)=0x%02x\n", 0xc41, rtw_read8(padapter, 0xc41)); ++ #endif ++ ++ //Disable P2P function ++ if(!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) ++ { ++ _cancel_timer_ex( &pwdinfo->find_phase_timer ); ++ _cancel_timer_ex( &pwdinfo->restore_p2p_state_timer ); ++ _cancel_timer_ex( &pwdinfo->pre_tx_scan_timer); ++ rtw_p2p_set_state(pwdinfo, P2P_STATE_NONE); ++ rtw_p2p_set_role(pwdinfo, P2P_ROLE_DISABLE); ++ _rtw_memset(&pwdinfo->rx_prov_disc_info, 0x00, sizeof(struct rx_provdisc_req_info)); ++ } ++ ++ if(pwrpriv->bips_processing == _FALSE){ ++ rtw_set_pwr_state_check_timer(pwrpriv); ++ } ++ } ++ ++exit: ++ return ret; ++} ++ ++#endif //CONFIG_P2P ++ +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/core/rtw_pwrctrl.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/core/rtw_pwrctrl.c 2013-07-26 19:36:05.000000000 +0000 +@@ -0,0 +1,1227 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ++******************************************************************************/ ++#define _RTW_PWRCTRL_C_ ++ ++#include ++#include ++#include ++#include ++ ++#ifdef CONFIG_SDIO_HCI ++#include ++#endif ++ ++#ifdef CONFIG_IPS ++void ips_enter(_adapter * padapter) ++{ ++ struct pwrctrl_priv *pwrpriv = &padapter->pwrctrlpriv; ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ ++ ++ _enter_pwrlock(&pwrpriv->lock); ++ ++ pwrpriv->bips_processing = _TRUE; ++ ++ // syn ips_mode with request ++ pwrpriv->ips_mode = pwrpriv->ips_mode_req; ++ ++ pwrpriv->ips_enter_cnts++; ++ DBG_8192C("==>ips_enter cnts:%d\n",pwrpriv->ips_enter_cnts); ++ ++ if(rf_off == pwrpriv->change_rfpwrstate ) ++ { ++ DBG_8192C("==>power_saving_ctrl_wk_hdl change rf to OFF...LED(0x%08x).... \n\n",rtw_read32(padapter,0x4c)); ++ ++ if(pwrpriv->ips_mode == IPS_LEVEL_2) ++ pwrpriv->bkeepfwalive = _TRUE; ++ ++ rtw_ips_pwr_down(padapter); ++ pwrpriv->rf_pwrstate = rf_off; ++ } ++ pwrpriv->bips_processing = _FALSE; ++ _exit_pwrlock(&pwrpriv->lock); ++ ++} ++ ++int ips_leave(_adapter * padapter) ++{ ++ struct pwrctrl_priv *pwrpriv = &padapter->pwrctrlpriv; ++ struct security_priv* psecuritypriv=&(padapter->securitypriv); ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ int result = _SUCCESS; ++ sint keyid; ++ _enter_pwrlock(&pwrpriv->lock); ++ if((pwrpriv->rf_pwrstate == rf_off) &&(!pwrpriv->bips_processing)) ++ { ++ pwrpriv->change_rfpwrstate = rf_on; ++ pwrpriv->ips_leave_cnts++; ++ DBG_8192C("==>ips_leave cnts:%d\n",pwrpriv->ips_leave_cnts); ++ ++ result = rtw_ips_pwr_up(padapter); ++ pwrpriv->bips_processing = _TRUE; ++ pwrpriv->rf_pwrstate = rf_on; ++ ++ if((_WEP40_ == psecuritypriv->dot11PrivacyAlgrthm) ||(_WEP104_ == psecuritypriv->dot11PrivacyAlgrthm)) ++ { ++ DBG_8192C("==>%s,channel(%d),processing(%x)\n",__FUNCTION__,padapter->mlmeextpriv.cur_channel,pwrpriv->bips_processing); ++ set_channel_bwmode(padapter, padapter->mlmeextpriv.cur_channel, HAL_PRIME_CHNL_OFFSET_DONT_CARE, HT_CHANNEL_WIDTH_20); ++ for(keyid=0;keyid<4;keyid++){ ++ if(pmlmepriv->key_mask & BIT(keyid)){ ++ if(keyid == psecuritypriv->dot11PrivacyKeyIndex) ++ result=rtw_set_key(padapter,psecuritypriv, keyid, 1); ++ else ++ result=rtw_set_key(padapter,psecuritypriv, keyid, 0); ++ } ++ } ++ } ++ ++ DBG_8192C("==> ips_leave.....LED(0x%08x)...\n",rtw_read32(padapter,0x4c)); ++ pwrpriv->bips_processing = _FALSE; ++ ++ pwrpriv->bkeepfwalive = _FALSE; ++ ++ ++ } ++ _exit_pwrlock(&pwrpriv->lock); ++ return result; ++} ++ ++ ++#endif ++ ++#ifdef CONFIG_AUTOSUSPEND ++extern void autosuspend_enter(_adapter* padapter); ++extern int autoresume_enter(_adapter* padapter); ++#endif ++ ++#ifdef SUPPORT_HW_RFOFF_DETECTED ++int rtw_hw_suspend(_adapter *padapter ); ++int rtw_hw_resume(_adapter *padapter); ++#endif ++ ++#ifdef PLATFORM_LINUX ++void rtw_ps_processor(_adapter*padapter) ++{ ++#ifdef CONFIG_P2P ++ struct wifidirect_info *pwdinfo = &( padapter->wdinfo ); ++#endif //CONFIG_P2P ++ struct pwrctrl_priv *pwrpriv = &padapter->pwrctrlpriv; ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ int res; ++ rt_rf_power_state rfpwrstate; ++ ++#ifdef SUPPORT_HW_RFOFF_DETECTED ++ if(pwrpriv->bips_processing == _TRUE) return; ++ ++ //DBG_8192C("==> fw report state(0x%x)\n",rtw_read8(padapter,0x1ca)); ++ if(padapter->pwrctrlpriv.bHWPwrPindetect) ++ { ++ #ifdef CONFIG_AUTOSUSPEND ++ if(padapter->registrypriv.usbss_enable) ++ { ++ if(pwrpriv->rf_pwrstate == rf_on) ++ { ++ if(padapter->net_closed == _TRUE) ++ pwrpriv->ps_flag = _TRUE; ++ ++ rfpwrstate = RfOnOffDetect(padapter); ++ DBG_8192C("@@@@- #1 %s==> rfstate:%s \n",__FUNCTION__,(rfpwrstate==rf_on)?"rf_on":"rf_off"); ++ if(rfpwrstate!= pwrpriv->rf_pwrstate) ++ { ++ if(rfpwrstate == rf_off) ++ { ++ pwrpriv->change_rfpwrstate = rf_off; ++ ++ pwrpriv->bkeepfwalive = _TRUE; ++ pwrpriv->brfoffbyhw = _TRUE; ++ ++ autosuspend_enter(padapter); ++ } ++ } ++ } ++ } ++ else ++ #endif //CONFIG_AUTOSUSPEND ++ { ++ rfpwrstate = RfOnOffDetect(padapter); ++ DBG_8192C("@@@@- #2 %s==> rfstate:%s \n",__FUNCTION__,(rfpwrstate==rf_on)?"rf_on":"rf_off"); ++ ++ if(rfpwrstate!= pwrpriv->rf_pwrstate) ++ { ++ if(rfpwrstate == rf_off) ++ { ++ pwrpriv->change_rfpwrstate = rf_off; ++ pwrpriv->brfoffbyhw = _TRUE; ++ padapter->bCardDisableWOHSM = _TRUE; ++ rtw_hw_suspend(padapter ); ++ } ++ else ++ { ++ pwrpriv->change_rfpwrstate = rf_on; ++ rtw_hw_resume(padapter ); ++ } ++ DBG_8192C("current rf_pwrstate(%s)\n",(pwrpriv->rf_pwrstate == rf_off)?"rf_off":"rf_on"); ++ } ++ } ++ pwrpriv->pwr_state_check_cnts ++; ++ } ++#endif //SUPPORT_HW_RFOFF_DETECTED ++ ++ if( pwrpriv->power_mgnt == PS_MODE_ACTIVE ) return; ++ ++ if((pwrpriv->rf_pwrstate == rf_on) && ((pwrpriv->pwr_state_check_cnts%4)==0)) ++ { ++ if ( (check_fwstate(pmlmepriv, _FW_LINKED|_FW_UNDER_SURVEY|_FW_UNDER_LINKING) == _TRUE) || ++ (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) || ++ (check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE) || ++ (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE) || ++ (padapter->bup == _FALSE) ++ #ifdef CONFIG_P2P ++ || !rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE) ++ #endif //CONFIG_P2P ++ ) ++ { ++ return; ++ } ++ ++ DBG_8192C("==>%s .fw_state(%x)\n",__FUNCTION__,get_fwstate(pmlmepriv)); ++ pwrpriv->change_rfpwrstate = rf_off; ++ ++ #ifdef CONFIG_AUTOSUSPEND ++ if(padapter->registrypriv.usbss_enable) ++ { ++ if(padapter->pwrctrlpriv.bHWPwrPindetect) ++ pwrpriv->bkeepfwalive = _TRUE; ++ ++ if(padapter->net_closed == _TRUE) ++ pwrpriv->ps_flag = _TRUE; ++ ++ padapter->bCardDisableWOHSM = _TRUE; ++ autosuspend_enter(padapter); ++ } ++ else if(padapter->pwrctrlpriv.bHWPwrPindetect) ++ { ++ } ++ else ++ #endif //CONFIG_AUTOSUSPEND ++ { ++ #ifdef CONFIG_IPS ++ ips_enter(padapter); ++ #endif ++ } ++ } ++ ++ ++} ++ ++void pwr_state_check_handler(void *FunctionContext) ++{ ++ _adapter *padapter = (_adapter *)FunctionContext; ++ struct pwrctrl_priv *pwrpriv = &padapter->pwrctrlpriv; ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ struct pwrctrl_priv *pwrctrlpriv = &padapter->pwrctrlpriv; ++#ifdef CONFIG_P2P ++ struct wifidirect_info *pwdinfo = &( padapter->wdinfo ); ++#endif //CONFIG_P2P ++ //DBG_871X("%s\n", __FUNCTION__); ++ ++#ifdef SUPPORT_HW_RFOFF_DETECTED ++ //DBG_8192C("%s...bHWPwrPindetect(%d)\n",__FUNCTION__,padapter->pwrctrlpriv.bHWPwrPindetect); ++ if(padapter->pwrctrlpriv.bHWPwrPindetect) ++ { ++ rtw_ps_cmd(padapter); ++ rtw_set_pwr_state_check_timer(&padapter->pwrctrlpriv); ++ } ++ else ++#endif ++ { ++ //if(padapter->net_closed == _TRUE) return; ++ //DBG_8192C("==>%s .fw_state(%x)\n", __FUNCTION__, get_fwstate(pmlmepriv)); ++ if ( (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) || ++ (check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE) || ++ (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE) || ++ (check_fwstate(pmlmepriv, _FW_LINKED|_FW_UNDER_SURVEY|_FW_UNDER_LINKING) == _TRUE) || ++ (padapter->bup == _FALSE) ++#ifdef CONFIG_P2P ++ || !rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE) ++#endif //CONFIG_P2P ++ ) ++ { ++ //other pwr ctrl.... ++ rtw_set_pwr_state_check_timer(&padapter->pwrctrlpriv); ++ } ++ else ++ { ++ if((pwrpriv->rf_pwrstate == rf_on) &&(_FALSE == pwrpriv->bips_processing)) ++ { ++ pwrpriv->change_rfpwrstate = rf_off; ++ pwrctrlpriv->pwr_state_check_cnts = 0; ++ DBG_8192C("==>pwr_state_check_handler .fw_state(%x)\n",get_fwstate(pmlmepriv)); ++ rtw_ps_cmd(padapter); ++ } ++ ++ } ++ } ++ ++ ++ ++} ++#endif ++ ++ ++#ifdef CONFIG_LPS ++void rtw_set_rpwm(_adapter * padapter, u8 val8) ++{ ++ u8 rpwm; ++ struct pwrctrl_priv *pwrpriv = &padapter->pwrctrlpriv; ++ ++_func_enter_; ++ ++ if(pwrpriv->rpwm == val8){ ++ RT_TRACE(_module_rtl871x_pwrctrl_c_,_drv_err_,("Already set rpwm [%d] ! \n", val8)); ++ return; ++ } ++ ++ if ((padapter->bDriverStopped == _TRUE)||(padapter->bSurpriseRemoved== _TRUE)){ ++ RT_TRACE(_module_rtl871x_xmit_c_,_drv_err_,("rtw_set_rpwm=> bDriverStopped or bSurpriseRemoved \n")); ++ return; ++ } ++ rpwm = val8 |pwrpriv->tog; ++ ++ pwrpriv->rpwm = val8; ++ ++ RT_TRACE(_module_rtl871x_pwrctrl_c_,_drv_err_,("rtw_set_rpwm: value = %x\n", rpwm)); ++ ++ padapter->HalFunc.SetHwRegHandler(padapter, HW_VAR_SET_RPWM, (u8 *)(&rpwm)); ++ ++ pwrpriv->tog += 0x80; ++ ++_func_exit_; ++} ++ ++u8 PS_RDY_CHECK(_adapter * padapter) ++{ ++ u32 curr_time, delta_time; ++ struct pwrctrl_priv *pwrpriv = &padapter->pwrctrlpriv; ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ ++ curr_time = rtw_get_current_time(); ++ ++ delta_time = curr_time -pwrpriv->DelayLPSLastTimeStamp; ++ ++ if(delta_time < LPS_DELAY_TIME) ++ { ++ return _FALSE; ++ } ++ ++ if ( (check_fwstate(pmlmepriv, _FW_LINKED) == _FALSE) || ++ (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) || ++ (check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE) || ++ (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE) ) ++ return _FALSE; ++ ++ if(_TRUE == pwrpriv->bInSuspend ) ++ return _FALSE; ++ ++ if( (padapter->securitypriv.dot11AuthAlgrthm == dot11AuthAlgrthm_8021X) && (padapter->securitypriv.binstallGrpkey == _FALSE) ) ++ { ++ DBG_8192C("Group handshake still in progress !!!\n"); ++ return _FALSE; ++ } ++ ++ return _TRUE; ++} ++ ++void rtw_set_ps_mode(_adapter * padapter, u8 ps_mode, u8 smart_ps) ++{ ++ struct pwrctrl_priv *pwrpriv = &padapter->pwrctrlpriv; ++#ifdef CONFIG_P2P ++ struct wifidirect_info *pwdinfo = &( padapter->wdinfo ); ++#endif //CONFIG_P2P ++ ++_func_enter_; ++ ++ RT_TRACE(_module_rtl871x_pwrctrl_c_,_drv_err_,("========= Power Mode is :%d, Smart_PS = %d\n", ps_mode,smart_ps)); ++ //DBG_8192C("========= Power Mode is :%d, Smart_PS = %d\n", ps_mode,smart_ps); ++ ++ if(ps_mode > PM_Card_Disable) { ++ RT_TRACE(_module_rtl871x_pwrctrl_c_,_drv_err_,("ps_mode:%d error\n", ps_mode)); ++ return; ++ } ++ ++ if((pwrpriv->pwr_mode == ps_mode) && ++ (pwrpriv->smart_ps == smart_ps)){ ++ return; ++ } ++ ++ //if(pwrpriv->pwr_mode == PS_MODE_ACTIVE) ++ if(ps_mode == PS_MODE_ACTIVE) ++ { ++#ifdef CONFIG_P2P ++ if(pwdinfo->opp_ps == 0) ++#endif //CONFIG_P2P ++ { ++ DBG_8192C("rtw_set_ps_mode(): Busy Traffic , Leave 802.11 power save..\n"); ++ pwrpriv->smart_ps = smart_ps; ++ pwrpriv->pwr_mode = ps_mode; ++ rtw_set_rpwm(padapter, PS_STATE_S4); ++ padapter->HalFunc.SetHwRegHandler(padapter, HW_VAR_H2C_FW_PWRMODE, (u8 *)(&ps_mode)); ++ pwrpriv->bFwCurrentInPSMode = _FALSE; ++ } ++ } ++ else ++ { ++ if(PS_RDY_CHECK(padapter)) ++ { ++ DBG_8192C("rtw_set_ps_mode(): Enter 802.11 power save mode...\n"); ++ pwrpriv->smart_ps = smart_ps; ++ pwrpriv->pwr_mode = ps_mode; ++ pwrpriv->bFwCurrentInPSMode = _TRUE; ++ padapter->HalFunc.SetHwRegHandler(padapter, HW_VAR_H2C_FW_PWRMODE, (u8 *)(&ps_mode)); ++#ifdef CONFIG_P2P ++ // Set CTWindow after LPS ++ if(pwdinfo->opp_ps == 1) ++ //if(pwdinfo->p2p_ps_enable == _TRUE) ++ p2p_ps_wk_cmd(padapter, P2P_PS_ENABLE, 0); ++#endif //CONFIG_P2P ++ rtw_set_rpwm(padapter, PS_STATE_S2); ++ } ++ //else ++ //{ ++ // pwrpriv->pwr_mode = PS_MODE_ACTIVE; ++ //} ++ } ++ ++_func_exit_; ++} ++ ++ ++// ++// Description: ++// Enter the leisure power save mode. ++// ++void LPS_Enter(PADAPTER padapter) ++{ ++ struct pwrctrl_priv *pwrpriv = &padapter->pwrctrlpriv; ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ ++_func_enter_; ++ ++// DBG_871X("+LeisurePSEnter\n"); ++ ++ if ( (check_fwstate(pmlmepriv, _FW_LINKED) == _FALSE) || ++ (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY) == _TRUE) || ++ (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) || ++ (check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE) || ++ (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE) ) ++ return; ++ ++ if(_TRUE == pwrpriv->bInSuspend ) ++ return ; ++ ++ if (pwrpriv->bLeisurePs) ++ { ++ // Idle for a while if we connect to AP a while ago. ++ if(pwrpriv->LpsIdleCount >= 2) // 4 Sec ++ { ++ if(pwrpriv->pwr_mode == PS_MODE_ACTIVE) ++ { ++ rtw_set_ps_mode(padapter, pwrpriv->power_mgnt, 2); ++ } ++ } ++ else ++ pwrpriv->LpsIdleCount++; ++ } ++ ++_func_exit_; ++} ++ ++ ++// ++// Description: ++// Leave the leisure power save mode. ++// ++void LPS_Leave(PADAPTER padapter) ++{ ++ struct pwrctrl_priv *pwrpriv = &padapter->pwrctrlpriv; ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ ++_func_enter_; ++ ++ //DBG_8192C("LeisurePSLeave()...\n"); ++ ++ if (pwrpriv->bLeisurePs) ++ { ++ if(pwrpriv->pwr_mode != PS_MODE_ACTIVE) ++ { ++ rtw_set_ps_mode(padapter, PS_MODE_ACTIVE, 0); ++ } ++ } ++ ++_func_exit_; ++} ++ ++#endif ++ ++// ++// Description: Leave all power save mode: LPS, FwLPS, IPS if needed. ++// Move code to function by tynli. 2010.03.26. ++// ++void LeaveAllPowerSaveMode(IN PADAPTER Adapter) ++{ ++ struct mlme_priv *pmlmepriv = &(Adapter->mlmepriv); ++ u32 LPSLeaveTimeOut = 10000; ++ //u32 IPSLeaveTimeOut = 10000; ++ ++_func_enter_; ++ ++ //DBG_8192C("%s.....\n",__FUNCTION__); ++ if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) ++ { //connect ++#ifdef CONFIG_P2P ++ p2p_ps_wk_cmd(Adapter, P2P_PS_DISABLE, 0); ++#endif //CONFIG_P2P ++#ifdef CONFIG_LPS ++ //DBG_8192C("==> leave LPS.......\n"); ++ LPS_Leave(Adapter); ++ ++ if (Adapter->pwrctrlpriv.bLeisurePs) ++ { ++ BOOLEAN bAwake = _TRUE; ++ Adapter->HalFunc.GetHwRegHandler(Adapter, HW_VAR_FWLPS_RF_ON, (u8 *)(&bAwake)); ++ while(!bAwake) ++ { ++ rtw_usleep_os(100); ++ LPSLeaveTimeOut--; ++ if(LPSLeaveTimeOut <= 0) ++ { ++ DBG_8192C("Wait for FW LPS leave too long!!! LPSLeaveTimeOut = %d\n", LPSLeaveTimeOut ); ++ break; ++ } ++ Adapter->HalFunc.GetHwRegHandler(Adapter, HW_VAR_FWLPS_RF_ON, (u8 *)(&bAwake)); ++ } ++ } ++#endif ++ } ++ else ++ { ++ if(Adapter->pwrctrlpriv.rf_pwrstate== rf_off) ++ { ++ #ifdef CONFIG_AUTOSUSPEND ++ if(Adapter->registrypriv.usbss_enable) ++ { ++ #if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,35)) ++ usb_disable_autosuspend(Adapter->dvobjpriv.pusbdev); ++ #elif (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,22) && LINUX_VERSION_CODE<=KERNEL_VERSION(2,6,34)) ++ Adapter->dvobjpriv.pusbdev->autosuspend_disabled = Adapter->bDisableAutosuspend;//autosuspend disabled by the user ++ #endif ++ } ++ else ++ #endif ++ { ++ /* ++ #ifdef CONFIG_IPS ++ if(_FALSE == ips_leave(Adapter)) ++ { ++ DBG_8192C("======> ips_leave fail.............\n"); ++ } ++ #endif ++ */ ++ } ++ } ++ } ++ ++_func_exit_; ++} ++ ++#ifdef CONFIG_PWRCTRL ++ ++/* ++Caller:ISR handler... ++ ++This will be called when CPWM interrupt is up. ++ ++using to update cpwn of drv; and drv willl make a decision to up or down pwr level ++*/ ++void cpwm_int_hdl(_adapter *padapter, struct reportpwrstate_parm *preportpwrstate) ++{ ++ struct pwrctrl_priv *pwrpriv = &(padapter->pwrctrlpriv); ++ struct cmd_priv *pcmdpriv = &(padapter->cmdpriv); ++ struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); ++ ++_func_enter_; ++ ++ if(pwrpriv->cpwm_tog == ((preportpwrstate->state)&0x80)){ ++ RT_TRACE(_module_rtl871x_pwrctrl_c_,_drv_err_,("cpwm_int_hdl : cpwm_tog = %x this time cpwm=0x%x toggle bit didn't change !!!\n",pwrpriv->cpwm_tog ,preportpwrstate->state)); ++ goto exit; ++ } ++ ++ _enter_pwrlock(&pwrpriv->lock); ++ ++ pwrpriv->cpwm = (preportpwrstate->state)&0xf; ++ ++ if(pwrpriv->cpwm >= PS_STATE_S2){ ++ if(pwrpriv->alives & CMD_ALIVE) ++ _rtw_up_sema(&(pcmdpriv->cmd_queue_sema)); ++ ++ if(pwrpriv->alives & XMIT_ALIVE) ++ _rtw_up_sema(&(pxmitpriv->xmit_sema)); ++ } ++ pwrpriv->cpwm_tog= (preportpwrstate->state)&0x80; ++ _exit_pwrlock(&pwrpriv->lock); ++exit: ++ RT_TRACE(_module_rtl871x_pwrctrl_c_,_drv_err_,("cpwm_int_hdl : cpwm = %x !!!\n",pwrpriv->cpwm)); ++ ++_func_exit_; ++ ++} ++ ++ ++__inline static void register_task_alive(struct pwrctrl_priv *pwrctrl, uint tag) ++{ ++_func_enter_; ++ pwrctrl->alives |= tag; ++_func_exit_; ++} ++ ++__inline static void unregister_task_alive(struct pwrctrl_priv *pwrctrl, uint tag) ++{ ++_func_enter_; ++ ++ if (pwrctrl->alives & tag) ++ pwrctrl->alives ^= tag; ++ ++_func_exit_; ++} ++#endif ++ ++#ifdef CONFIG_RESUME_IN_WORKQUEUE ++static void resume_workitem_callback(struct work_struct *work); ++#endif //CONFIG_RESUME_IN_WORKQUEUE ++ ++void rtw_init_pwrctrl_priv(_adapter *padapter) ++{ ++ struct pwrctrl_priv *pwrctrlpriv = &padapter->pwrctrlpriv; ++ ++_func_enter_; ++ ++#ifdef PLATFORM_WINDOWS ++ pwrctrlpriv->pnp_current_pwr_state=NdisDeviceStateD0; ++#endif ++ ++ _init_pwrlock(&pwrctrlpriv->lock); ++ pwrctrlpriv->rf_pwrstate = rf_on; ++ pwrctrlpriv->ips_enter_cnts=0; ++ pwrctrlpriv->ips_leave_cnts=0; ++ ++ pwrctrlpriv->ips_mode = padapter->registrypriv.ips_mode; ++ pwrctrlpriv->ips_mode_req = padapter->registrypriv.ips_mode; ++ ++ pwrctrlpriv->pwr_state_check_interval = 2000; ++ pwrctrlpriv->pwr_state_check_cnts = 0; ++ pwrctrlpriv->bInternalAutoSuspend = _FALSE; ++ pwrctrlpriv->bInSuspend = _FALSE; ++ pwrctrlpriv->bkeepfwalive = _FALSE; ++ ++#ifdef CONFIG_AUTOSUSPEND ++#ifdef SUPPORT_HW_RFOFF_DETECTED ++ pwrctrlpriv->pwr_state_check_interval = (pwrctrlpriv->bHWPwrPindetect) ?1000:2000; ++#endif ++#endif ++ ++ pwrctrlpriv->LpsIdleCount = 0; ++ //pwrctrlpriv->FWCtrlPSMode =padapter->registrypriv.power_mgnt;// PS_MODE_MIN; ++ pwrctrlpriv->power_mgnt =padapter->registrypriv.power_mgnt;// PS_MODE_MIN; ++ pwrctrlpriv->bLeisurePs = (PS_MODE_ACTIVE != pwrctrlpriv->power_mgnt)?_TRUE:_FALSE; ++ ++ pwrctrlpriv->bFwCurrentInPSMode = _FALSE; ++ ++ pwrctrlpriv->cpwm = PS_STATE_S4; ++ ++ pwrctrlpriv->pwr_mode = PS_MODE_ACTIVE; ++ ++ ++ pwrctrlpriv->smart_ps = 0; ++ ++ pwrctrlpriv->tog = 0x80; ++ ++#ifdef PLATFORM_LINUX ++ _init_timer(&(pwrctrlpriv->pwr_state_check_timer), padapter->pnetdev, pwr_state_check_handler, (u8 *)padapter); ++#endif ++ ++ #ifdef CONFIG_RESUME_IN_WORKQUEUE ++ _init_workitem(&pwrctrlpriv->resume_work, resume_workitem_callback, NULL); ++ pwrctrlpriv->rtw_workqueue = create_singlethread_workqueue("rtw_workqueue"); ++ #endif //CONFIG_RESUME_IN_WORKQUEUE ++ ++ #if defined(CONFIG_HAS_EARLYSUSPEND) || defined(CONFIG_ANDROID_POWER) ++ pwrctrlpriv->early_suspend.suspend = NULL; ++ rtw_register_early_suspend(pwrctrlpriv); ++ #endif //CONFIG_HAS_EARLYSUSPEND || CONFIG_ANDROID_POWER ++ ++ ++_func_exit_; ++ ++} ++ ++ ++void rtw_free_pwrctrl_priv(_adapter *adapter) ++{ ++ struct pwrctrl_priv *pwrctrlpriv = &adapter->pwrctrlpriv; ++ ++_func_enter_; ++ ++ //_rtw_memset((unsigned char *)pwrctrlpriv, 0, sizeof(struct pwrctrl_priv)); ++ ++ ++ #ifdef CONFIG_RESUME_IN_WORKQUEUE ++ if (pwrctrlpriv->rtw_workqueue) { ++ flush_workqueue(pwrctrlpriv->rtw_workqueue); ++ destroy_workqueue(pwrctrlpriv->rtw_workqueue); ++ } ++ #endif ++ ++ ++ #if defined(CONFIG_HAS_EARLYSUSPEND) || defined(CONFIG_ANDROID_POWER) ++ rtw_unregister_early_suspend(pwrctrlpriv); ++ #endif //CONFIG_HAS_EARLYSUSPEND || CONFIG_ANDROID_POWER ++ ++ _free_pwrlock(&pwrctrlpriv->lock); ++ ++_func_exit_; ++} ++ ++ ++/* ++Caller: rtw_xmit_thread ++ ++Check if the fw_pwrstate is okay for xmit. ++If not (cpwm is less than P1 state), then the sub-routine ++will raise the cpwm to be greater than or equal to P1. ++ ++Calling Context: Passive ++ ++Return Value: ++ ++_SUCCESS: rtw_xmit_thread can write fifo/txcmd afterwards. ++_FAIL: rtw_xmit_thread can not do anything. ++*/ ++sint rtw_register_tx_alive(_adapter *padapter) ++{ ++ uint res = _SUCCESS; ++ ++#ifdef CONFIG_PWRCTRL ++ ++ struct pwrctrl_priv *pwrctrl = &padapter->pwrctrlpriv; ++ ++_func_enter_; ++ ++ _enter_pwrlock(&pwrctrl->lock); ++ ++ register_task_alive(pwrctrl, XMIT_ALIVE); ++ RT_TRACE(_module_rtl871x_pwrctrl_c_,_drv_err_,("rtw_register_tx_alive: cpwm:%d alives:%x\n", pwrctrl->cpwm, pwrctrl->alives)); ++ ++ if(pwrctrl->cpwm < PS_STATE_S2){ ++ rtw_set_rpwm(padapter, PS_STATE_S3); ++ res = _FAIL; ++ } ++ ++ _exit_pwrlock(&pwrctrl->lock); ++ ++_func_exit_; ++ ++#endif /* CONFIG_PWRCTRL */ ++ ++ return res; ++ ++} ++ ++/* ++Caller: rtw_cmd_thread ++ ++Check if the fw_pwrstate is okay for issuing cmd. ++If not (cpwm should be is less than P2 state), then the sub-routine ++will raise the cpwm to be greater than or equal to P2. ++ ++Calling Context: Passive ++ ++Return Value: ++ ++_SUCCESS: rtw_cmd_thread can issue cmds to firmware afterwards. ++_FAIL: rtw_cmd_thread can not do anything. ++*/ ++sint rtw_register_cmd_alive(_adapter *padapter) ++{ ++ uint res = _SUCCESS; ++ ++#ifdef CONFIG_PWRCTRL ++ ++ struct pwrctrl_priv *pwrctrl = &padapter->pwrctrlpriv; ++ ++_func_enter_; ++ ++ _enter_pwrlock(&pwrctrl->lock); ++ ++ register_task_alive(pwrctrl, CMD_ALIVE); ++ RT_TRACE(_module_rtl871x_pwrctrl_c_,_drv_err_,("rtw_register_cmd_alive: cpwm:%d alives:%x\n", pwrctrl->cpwm, pwrctrl->alives)); ++ ++ if(pwrctrl->cpwm < PS_STATE_S2){ ++ rtw_set_rpwm(padapter, PS_STATE_S3); ++ res = _FAIL; ++ } ++ ++ _exit_pwrlock(&pwrctrl->lock); ++_func_exit_; ++#endif ++ ++ return res; ++} ++ ++ ++/* ++Caller: rx_isr ++ ++Calling Context: Dispatch/ISR ++ ++Return Value: ++ ++*/ ++sint rtw_register_rx_alive(_adapter *padapter) ++{ ++ ++#ifdef CONFIG_PWRCTRL ++ ++ struct pwrctrl_priv *pwrctrl = &padapter->pwrctrlpriv; ++ ++_func_enter_; ++ ++ _enter_pwrlock(&pwrctrl->lock); ++ ++ register_task_alive(pwrctrl, RECV_ALIVE); ++ ++ RT_TRACE(_module_rtl871x_pwrctrl_c_,_drv_err_,("rtw_register_rx_alive: cpwm:%d alives:%x\n", pwrctrl->cpwm, pwrctrl->alives)); ++ ++ _exit_pwrlock(&pwrctrl->lock); ++ ++_func_exit_; ++ ++#endif /*CONFIG_PWRCTRL*/ ++ ++ return _SUCCESS; ++} ++ ++ ++/* ++Caller: evt_isr or evt_thread ++ ++Calling Context: Dispatch/ISR or Passive ++ ++Return Value: ++*/ ++sint rtw_register_evt_alive(_adapter *padapter) ++{ ++ ++#ifdef CONFIG_PWRCTRL ++ ++ struct pwrctrl_priv *pwrctrl = &padapter->pwrctrlpriv; ++ ++_func_enter_; ++ ++ _enter_pwrlock(&pwrctrl->lock); ++ ++ register_task_alive(pwrctrl, EVT_ALIVE); ++ ++ RT_TRACE(_module_rtl871x_pwrctrl_c_,_drv_info_,("rtw_register_evt_alive: cpwm:%d alives:%x\n", pwrctrl->cpwm, pwrctrl->alives)); ++ ++ _exit_pwrlock(&pwrctrl->lock); ++ ++_func_exit_; ++ ++#endif /*CONFIG_PWRCTRL*/ ++ ++ return _SUCCESS; ++} ++ ++ ++/* ++Caller: ISR ++ ++If ISR's txdone, ++No more pkts for TX, ++Then driver shall call this fun. to power down firmware again. ++*/ ++ ++void rtw_unregister_tx_alive(_adapter *padapter) ++{ ++#ifdef CONFIG_PWRCTRL ++ ++ struct pwrctrl_priv *pwrctrl = &padapter->pwrctrlpriv; ++ ++_func_enter_; ++ ++ _enter_pwrlock(&pwrctrl->lock); ++ ++ unregister_task_alive(pwrctrl, XMIT_ALIVE); ++ ++ if((pwrctrl->cpwm > PS_STATE_S2) && (pwrctrl->pwr_mode > PS_MODE_ACTIVE)){ ++ if(pwrctrl->alives == 0){ ++ rtw_set_rpwm(padapter, PS_STATE_S0); ++ } ++ } ++ ++ RT_TRACE(_module_rtl871x_pwrctrl_c_,_drv_err_,("rtw_unregister_tx_alive: cpwm:%d alives:%x\n", pwrctrl->cpwm, pwrctrl->alives)); ++ ++ _exit_pwrlock(&pwrctrl->lock); ++ ++_func_exit_; ++ ++#endif /*CONFIG_PWRCTRL*/ ++} ++ ++/* ++Caller: ISR ++ ++If ISR's txdone, ++No more pkts for TX, ++Then driver shall call this fun. to power down firmware again. ++*/ ++ ++void rtw_unregister_cmd_alive(_adapter *padapter) ++{ ++#ifdef CONFIG_PWRCTRL ++ ++ struct pwrctrl_priv *pwrctrl = &padapter->pwrctrlpriv; ++ ++_func_enter_; ++ ++ _enter_pwrlock(&pwrctrl->lock); ++ ++ unregister_task_alive(pwrctrl, CMD_ALIVE); ++ ++ if((pwrctrl->cpwm > PS_STATE_S2) && (pwrctrl->pwr_mode > PS_MODE_ACTIVE)){ ++ if((pwrctrl->alives == 0)&&(check_fwstate(&padapter->mlmepriv, _FW_UNDER_LINKING)!=_TRUE)){ ++ rtw_set_rpwm(padapter, PS_STATE_S0); ++ } ++ } ++ ++ RT_TRACE(_module_rtl871x_pwrctrl_c_,_drv_err_,("rtw_unregister_cmd_alive: cpwm:%d alives:%x\n", pwrctrl->cpwm, pwrctrl->alives)); ++ ++ _exit_pwrlock(&pwrctrl->lock); ++ ++_func_exit_; ++ ++#endif /*CONFIG_PWRCTRL*/ ++} ++ ++ ++/* ++ ++Caller: ISR ++ ++*/ ++void rtw_unregister_rx_alive(_adapter *padapter) ++{ ++#ifdef CONFIG_PWRCTRL ++ ++ struct pwrctrl_priv *pwrctrl = &padapter->pwrctrlpriv; ++ ++_func_enter_; ++ ++ _enter_pwrlock(&pwrctrl->lock); ++ ++ unregister_task_alive(pwrctrl, RECV_ALIVE); ++ ++ RT_TRACE(_module_rtl871x_pwrctrl_c_,_drv_err_,("rtw_unregister_rx_alive: cpwm:%d alives:%x\n", pwrctrl->cpwm, pwrctrl->alives)); ++ ++ _exit_pwrlock(&pwrctrl->lock); ++ ++_func_exit_; ++ ++#endif ++} ++ ++ ++void rtw_unregister_evt_alive(_adapter *padapter) ++{ ++#ifdef CONFIG_PWRCTRL ++ ++ struct pwrctrl_priv *pwrctrl = &padapter->pwrctrlpriv; ++ ++_func_enter_; ++ ++ _enter_pwrlock(&pwrctrl->lock); ++ ++ unregister_task_alive(pwrctrl, EVT_ALIVE); ++ ++ RT_TRACE(_module_rtl871x_pwrctrl_c_,_drv_err_,("rtw_unregister_evt_alive: cpwm:%d alives:%x\n", pwrctrl->cpwm, pwrctrl->alives)); ++ ++ _exit_pwrlock(&pwrctrl->lock); ++ ++_func_exit_; ++ ++#endif /*CONFIG_PWRCTRL*/ ++} ++ ++#ifdef CONFIG_RESUME_IN_WORKQUEUE ++#ifdef CONFIG_USB_HCI ++extern int rtw_resume_process(struct usb_interface *pusb_intf); ++#endif ++static void resume_workitem_callback(struct work_struct *work) ++{ ++ struct pwrctrl_priv *pwrpriv = container_of(work, struct pwrctrl_priv, resume_work); ++ _adapter *adapter = container_of(pwrpriv, _adapter, pwrctrlpriv); ++ ++ DBG_871X("%s\n",__FUNCTION__); ++ ++ #ifdef CONFIG_USB_HCI ++ rtw_resume_process(adapter->dvobjpriv.pusbintf); ++ #elif defined(CONFIG_PCI_HCI) ++ #endif ++ ++} ++ ++void rtw_resume_in_workqueue(struct pwrctrl_priv *pwrpriv) ++{ ++ // accquire system's suspend lock preventing from falliing asleep while resume in workqueue ++ rtw_lock_suspend(); ++ ++ #if 1 ++ queue_work(pwrpriv->rtw_workqueue, &pwrpriv->resume_work); ++ #else ++ _set_workitem(&pwrpriv->resume_work); ++ #endif ++} ++#endif //CONFIG_RESUME_IN_WORKQUEUE ++ ++#ifdef CONFIG_HAS_EARLYSUSPEND ++#ifdef CONFIG_USB_HCI ++extern int rtw_resume_process(struct usb_interface *pusb_intf); ++#endif ++static void rtw_early_suspend(struct early_suspend *h) ++{ ++ struct pwrctrl_priv *pwrpriv = container_of(h, struct pwrctrl_priv, early_suspend); ++ DBG_871X("%s\n",__FUNCTION__); ++ ++ //jeff: do nothing but set do_late_resume to false ++ pwrpriv->do_late_resume = _FALSE; ++} ++ ++static void rtw_late_resume(struct early_suspend *h) ++{ ++ struct pwrctrl_priv *pwrpriv = container_of(h, struct pwrctrl_priv, early_suspend); ++ _adapter *adapter = container_of(pwrpriv, _adapter, pwrctrlpriv); ++ ++ DBG_871X("%s\n",__FUNCTION__); ++ if(pwrpriv->do_late_resume) { ++ #ifdef CONFIG_USB_HCI ++ rtw_resume_process(adapter->dvobjpriv.pusbintf); ++ pwrpriv->do_late_resume = _FALSE; ++ #elif defined(CONFIG_PCI_HCI) ++ #endif ++ } ++} ++ ++void rtw_register_early_suspend(struct pwrctrl_priv *pwrpriv) ++{ ++ DBG_871X("%s\n", __FUNCTION__); ++ ++ //jeff: set the early suspend level before blank screen, so we wll do late resume after scree is lit ++ pwrpriv->early_suspend.level = EARLY_SUSPEND_LEVEL_BLANK_SCREEN - 20; ++ pwrpriv->early_suspend.suspend = rtw_early_suspend; ++ pwrpriv->early_suspend.resume = rtw_late_resume; ++ register_early_suspend(&pwrpriv->early_suspend); ++ ++ ++} ++ ++void rtw_unregister_early_suspend(struct pwrctrl_priv *pwrpriv) ++{ ++ DBG_871X("%s\n", __FUNCTION__); ++ ++ pwrpriv->do_late_resume = _FALSE; ++ ++ if (pwrpriv->early_suspend.suspend) ++ unregister_early_suspend(&pwrpriv->early_suspend); ++ ++ pwrpriv->early_suspend.suspend = NULL; ++ pwrpriv->early_suspend.resume = NULL; ++} ++#endif //CONFIG_HAS_EARLYSUSPEND ++ ++#ifdef CONFIG_ANDROID_POWER ++#ifdef CONFIG_USB_HCI ++extern int rtw_resume_process(struct usb_interface *pusb_intf); ++#endif ++static void rtw_early_suspend(android_early_suspend_t *h) ++{ ++ struct pwrctrl_priv *pwrpriv = container_of(h, struct pwrctrl_priv, early_suspend); ++ DBG_871X("%s\n",__FUNCTION__); ++ ++ //jeff: do nothing but set do_late_resume to false ++ pwrpriv->do_late_resume = _FALSE; ++} ++ ++static void rtw_late_resume(android_early_suspend_t *h) ++{ ++ struct pwrctrl_priv *pwrpriv = container_of(h, struct pwrctrl_priv, early_suspend); ++ _adapter *adapter = container_of(pwrpriv, _adapter, pwrctrlpriv); ++ ++ DBG_871X("%s\n",__FUNCTION__); ++ if(pwrpriv->do_late_resume) { ++ #ifdef CONFIG_USB_HCI ++ rtw_resume_process(adapter->dvobjpriv.pusbintf); ++ pwrpriv->do_late_resume = _FALSE; ++ #elif defined(CONFIG_PCI_HCI) ++ #endif ++ } ++} ++ ++void rtw_register_early_suspend(struct pwrctrl_priv *pwrpriv) ++{ ++ DBG_871X("%s\n", __FUNCTION__); ++ ++ //jeff: set the early suspend level before blank screen, so we wll do late resume after scree is lit ++ pwrpriv->early_suspend.level = ANDROID_EARLY_SUSPEND_LEVEL_BLANK_SCREEN - 20; ++ pwrpriv->early_suspend.suspend = rtw_early_suspend; ++ pwrpriv->early_suspend.resume = rtw_late_resume; ++ android_register_early_suspend(&pwrpriv->early_suspend); ++} ++ ++void rtw_unregister_early_suspend(struct pwrctrl_priv *pwrpriv) ++{ ++ DBG_871X("%s\n", __FUNCTION__); ++ ++ pwrpriv->do_late_resume = _FALSE; ++ ++ if (pwrpriv->early_suspend.suspend) ++ android_unregister_early_suspend(&pwrpriv->early_suspend); ++ ++ pwrpriv->early_suspend.suspend = NULL; ++ pwrpriv->early_suspend.resume = NULL; ++} ++#endif //CONFIG_ANDROID_POWER ++ ++u8 rtw_interface_ps_func(_adapter *padapter,HAL_INTF_PS_FUNC efunc_id,u8* val) ++{ ++ u8 bResult = _TRUE; ++ if(padapter->HalFunc.interface_ps_func) ++ { ++ bResult = padapter->HalFunc.interface_ps_func(padapter,efunc_id,val); ++ } ++ return bResult; ++} ++ ++/* ++* rtw_pwr_wakeup - Wake the NIC up from: 1)IPS. 2)USB autosuspend ++* @adapter: pointer to _adapter structure ++* ++* Return _SUCCESS or _FAIL ++*/ ++int _rtw_pwr_wakeup(_adapter *padapter, const char *caller) ++{ ++ struct pwrctrl_priv *pwrpriv = &padapter->pwrctrlpriv; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ int ret = _SUCCESS; ++ ++ //System suspend is not allowed to wakeup ++ if((pwrpriv->bInternalAutoSuspend == _FALSE) && (_TRUE == pwrpriv->bInSuspend )){ ++ ret = _FAIL; ++ goto exit; ++ } ++ ++ //I think this should be check in IPS, LPS, autosuspend functions... ++ //if( pwrpriv->power_mgnt == PS_MODE_ACTIVE ) { ++ // goto exit; ++ //} ++ ++ //block??? ++ if((pwrpriv->bInternalAutoSuspend == _TRUE) && (padapter->net_closed == _TRUE)) { ++ ret = _FAIL; ++ goto exit; ++ } ++ ++ //I think this should be check in IPS, LPS, autosuspend functions... ++ if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) ++ { ++ ret = _SUCCESS; ++ goto exit; ++ } ++ ++ if(rf_off == pwrpriv->rf_pwrstate ) ++ { ++#ifdef CONFIG_USB_HCI ++#ifdef CONFIG_AUTOSUSPEND ++ if(pwrpriv->brfoffbyhw==_TRUE) ++ { ++ DBG_8192C("hw still in rf_off state ...........\n"); ++ ret = _FAIL; ++ goto exit; ++ } ++ else if(padapter->registrypriv.usbss_enable) ++ { ++ DBG_8192C("\n %s call autoresume_enter....\n",__FUNCTION__); ++ if(_FAIL == autoresume_enter(padapter)) ++ { ++ DBG_8192C("======> autoresume fail.............\n"); ++ ret = _FAIL; ++ goto exit; ++ } ++ } ++ else ++#endif ++#endif ++ { ++#ifdef CONFIG_IPS ++ DBG_8192C("\n %s call ips_leave....\n",__FUNCTION__); ++ if(_FAIL == ips_leave(padapter)) ++ { ++ DBG_8192C("======> ips_leave fail.............\n"); ++ ret = _FAIL; ++ goto exit; ++ } ++#endif ++ } ++ }else { ++ //Jeff: reset timer to avoid falling ips or selective suspend soon ++ if(pwrpriv->bips_processing == _FALSE) ++ rtw_set_pwr_state_check_timer(pwrpriv); ++ } ++ ++ //TODO: the following checking need to be merged... ++ if(padapter->bDriverStopped ++ || !padapter->bup ++ || !padapter->hw_init_completed ++ ){ ++ DBG_8192C("%s: bDriverStopped=%d, bup=%d, hw_init_completed=%u\n" ++ , caller ++ , padapter->bDriverStopped ++ , padapter->bup ++ , padapter->hw_init_completed); ++ ret= _FALSE; ++ goto exit; ++ } ++ ++exit: ++ return ret; ++ ++} ++ ++ +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/core/rtw_recv.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/core/rtw_recv.c 2013-07-26 19:36:05.000000000 +0000 +@@ -0,0 +1,4597 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++******************************************************************************/ ++#define _RTW_RECV_C_ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#ifdef CONFIG_USB_HCI ++#include ++#endif ++ ++#if defined (PLATFORM_LINUX) && defined (PLATFORM_WINDOWS) ++ ++#error "Shall be Linux or Windows, but not both!\n" ++ ++#endif ++ ++#include ++#include ++ ++#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS ++void rtw_signal_stat_timer_hdl(RTW_TIMER_HDL_ARGS); ++#endif //CONFIG_NEW_SIGNAL_STAT_PROCESS ++ ++ ++void _rtw_init_sta_recv_priv(struct sta_recv_priv *psta_recvpriv) ++{ ++ ++ ++_func_enter_; ++ ++ _rtw_memset((u8 *)psta_recvpriv, 0, sizeof (struct sta_recv_priv)); ++ ++ _rtw_spinlock_init(&psta_recvpriv->lock); ++ ++ //for(i=0; iblk_strms[i]); ++ ++ _rtw_init_queue(&psta_recvpriv->defrag_q); ++ ++_func_exit_; ++ ++} ++ ++sint _rtw_init_recv_priv(struct recv_priv *precvpriv, _adapter *padapter) ++{ ++ sint i; ++ ++ union recv_frame *precvframe; ++ ++ sint res=_SUCCESS; ++ ++_func_enter_; ++ ++ // We don't need to memset padapter->XXX to zero, because adapter is allocated by rtw_zvmalloc(). ++ //_rtw_memset((unsigned char *)precvpriv, 0, sizeof (struct recv_priv)); ++ ++ _rtw_spinlock_init(&precvpriv->lock); ++ ++ _rtw_init_queue(&precvpriv->free_recv_queue); ++ _rtw_init_queue(&precvpriv->recv_pending_queue); ++ ++ precvpriv->adapter = padapter; ++ ++ precvpriv->free_recvframe_cnt = NR_RECVFRAME; ++ ++ rtw_os_recv_resource_init(precvpriv, padapter); ++ ++ precvpriv->pallocated_frame_buf = rtw_zvmalloc(NR_RECVFRAME * sizeof(union recv_frame) + RXFRAME_ALIGN_SZ); ++ ++ if(precvpriv->pallocated_frame_buf==NULL){ ++ res= _FAIL; ++ goto exit; ++ } ++ //_rtw_memset(precvpriv->pallocated_frame_buf, 0, NR_RECVFRAME * sizeof(union recv_frame) + RXFRAME_ALIGN_SZ); ++ ++ precvpriv->precv_frame_buf = (u8 *)N_BYTE_ALIGMENT((SIZE_PTR)(precvpriv->pallocated_frame_buf), RXFRAME_ALIGN_SZ); ++ //precvpriv->precv_frame_buf = precvpriv->pallocated_frame_buf + RXFRAME_ALIGN_SZ - ++ // ((SIZE_PTR) (precvpriv->pallocated_frame_buf) &(RXFRAME_ALIGN_SZ-1)); ++ ++ precvframe = (union recv_frame*) precvpriv->precv_frame_buf; ++ ++ ++ for(i=0; i < NR_RECVFRAME ; i++) ++ { ++ _rtw_init_listhead(&(precvframe->u.list)); ++ ++ rtw_list_insert_tail(&(precvframe->u.list), &(precvpriv->free_recv_queue.queue)); ++ ++ res = rtw_os_recv_resource_alloc(padapter, precvframe); ++ ++ precvframe->u.hdr.adapter =padapter; ++ precvframe++; ++ ++ } ++ ++#ifdef CONFIG_USB_HCI ++ ++ precvpriv->rx_pending_cnt=1; ++ ++ _rtw_init_sema(&precvpriv->allrxreturnevt, 0); ++ ++#endif ++ ++ res = padapter->HalFunc.init_recv_priv(padapter); ++ ++#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS ++ #ifdef PLATFORM_LINUX ++ _init_timer(&precvpriv->signal_stat_timer, padapter->pnetdev, RTW_TIMER_HDL_NAME(signal_stat), padapter); ++ #elif defined(PLATFORM_OS_CE) || defined(PLATFORM_WINDOWS) ++ _init_timer(&precvpriv->signal_stat_timer, padapter->hndis_adapter, RTW_TIMER_HDL_NAME(signal_stat), padapter); ++ #endif ++ ++ precvpriv->signal_stat_sampling_interval = 1000; //ms ++ //precvpriv->signal_stat_converging_constant = 5000; //ms ++ ++ rtw_set_signal_stat_timer(precvpriv); ++#endif //CONFIG_NEW_SIGNAL_STAT_PROCESS ++ ++exit: ++ ++_func_exit_; ++ ++ return res; ++ ++} ++ ++void rtw_mfree_recv_priv_lock(struct recv_priv *precvpriv) ++{ ++ _rtw_spinlock_free(&precvpriv->lock); ++#ifdef CONFIG_RECV_THREAD_MODE ++ _rtw_free_sema(&precvpriv->recv_sema); ++ _rtw_free_sema(&precvpriv->terminate_recvthread_sema); ++#endif ++ ++ _rtw_spinlock_free(&precvpriv->free_recv_queue.lock); ++ _rtw_spinlock_free(&precvpriv->recv_pending_queue.lock); ++ ++ _rtw_spinlock_free(&precvpriv->free_recv_buf_queue.lock); ++ ++#ifdef CONFIG_USE_USB_BUFFER_ALLOC_RX ++ _rtw_spinlock_free(&precvpriv->recv_buf_pending_queue.lock); ++#endif // CONFIG_USE_USB_BUFFER_ALLOC_RX ++} ++ ++void _rtw_free_recv_priv (struct recv_priv *precvpriv) ++{ ++ _adapter *padapter = precvpriv->adapter; ++ ++_func_enter_; ++ ++ rtw_mfree_recv_priv_lock(precvpriv); ++ ++ rtw_os_recv_resource_free(precvpriv); ++ ++ if(precvpriv->pallocated_frame_buf) { ++ rtw_vmfree(precvpriv->pallocated_frame_buf, NR_RECVFRAME * sizeof(union recv_frame) + RXFRAME_ALIGN_SZ); ++ } ++ ++ padapter->HalFunc.free_recv_priv(padapter); ++ ++_func_exit_; ++ ++} ++ ++union recv_frame *rtw_alloc_recvframe (_queue *pfree_recv_queue) ++{ ++ _irqL irqL; ++ union recv_frame *precvframe; ++ _list *plist, *phead; ++ _adapter *padapter; ++ struct recv_priv *precvpriv; ++_func_enter_; ++ ++ _enter_critical_bh(&pfree_recv_queue->lock, &irqL); ++ ++ if(_rtw_queue_empty(pfree_recv_queue) == _TRUE) ++ { ++ precvframe = NULL; ++ } ++ else ++ { ++ phead = get_list_head(pfree_recv_queue); ++ ++ plist = get_next(phead); ++ ++ precvframe = LIST_CONTAINOR(plist, union recv_frame, u); ++ ++ rtw_list_delete(&precvframe->u.hdr.list); ++ padapter=precvframe->u.hdr.adapter; ++ if(padapter !=NULL){ ++ precvpriv=&padapter->recvpriv; ++ if(pfree_recv_queue == &precvpriv->free_recv_queue) ++ precvpriv->free_recvframe_cnt--; ++ } ++ } ++ ++ _exit_critical_bh(&pfree_recv_queue->lock, &irqL); ++ ++_func_exit_; ++ ++ return precvframe; ++ ++} ++ ++ ++void rtw_init_recvframe(union recv_frame *precvframe, struct recv_priv *precvpriv) ++{ ++ struct recv_buf *precvbuf = precvframe->u.hdr.precvbuf; ++ ++ /* Perry: This can be removed */ ++ _rtw_init_listhead(&precvframe->u.hdr.list); ++ ++ precvframe->u.hdr.len=0; ++ ++ ++} ++ ++ ++int rtw_free_recvframe(union recv_frame *precvframe, _queue *pfree_recv_queue) ++{ ++ _irqL irqL; ++ _adapter *padapter=precvframe->u.hdr.adapter; ++ struct recv_priv *precvpriv = &padapter->recvpriv; ++ ++_func_enter_; ++ ++ ++#ifdef PLATFORM_WINDOWS ++ rtw_os_read_port(padapter, precvframe->u.hdr.precvbuf); ++#endif ++ ++#ifdef PLATFORM_LINUX ++ ++ if(precvframe->u.hdr.pkt) ++ { ++ dev_kfree_skb_any(precvframe->u.hdr.pkt);//free skb by driver ++ precvframe->u.hdr.pkt = NULL; ++ } ++ ++#ifdef CONFIG_SDIO_HCI ++{ ++ _irqL irql; ++ struct recv_buf *precvbuf=precvframe->u.hdr.precvbuf; ++ if(precvbuf !=NULL){ ++ _enter_critical_bh(&precvbuf->recvbuf_lock, &irql); ++ ++ precvbuf->ref_cnt--; ++ if(precvbuf->ref_cnt == 0 ){ ++ _enter_critical_bh(&precvpriv->free_recv_buf_queue.lock, &irqL); ++ rtw_list_delete(&(precvbuf->list)); ++ rtw_list_insert_tail(&(precvbuf->list), get_list_head(&precvpriv->free_recv_buf_queue)); ++ precvpriv->free_recv_buf_queue_cnt++; ++ _exit_critical_bh(&precvpriv->free_recv_buf_queue.lock, &irqL); ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_notice_,("rtw_os_read_port: precvbuf=0x%p enqueue:precvpriv->free_recv_buf_queue_cnt=%d\n",precvbuf,precvpriv->free_recv_buf_queue_cnt)); ++ } ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_notice_,("rtw_os_read_port: precvbuf=0x%p enqueue:precvpriv->free_recv_buf_queue_cnt=%d\n",precvbuf,precvpriv->free_recv_buf_queue_cnt)); ++ _exit_critical_bh(&precvbuf->recvbuf_lock, &irql); ++ } ++} ++#endif ++#endif ++ ++ _enter_critical_bh(&pfree_recv_queue->lock, &irqL); ++ ++ rtw_list_delete(&(precvframe->u.hdr.list)); ++ ++ rtw_list_insert_tail(&(precvframe->u.hdr.list), get_list_head(pfree_recv_queue)); ++ ++ if(padapter !=NULL){ ++ if(pfree_recv_queue == &precvpriv->free_recv_queue) ++ precvpriv->free_recvframe_cnt++; ++ } ++ ++ _exit_critical_bh(&pfree_recv_queue->lock, &irqL); ++ ++_func_exit_; ++ ++ return _SUCCESS; ++ ++} ++ ++ ++union recv_frame *rtw_dequeue_recvframe (_queue *queue) ++{ ++ return rtw_alloc_recvframe(queue); ++} ++ ++ ++sint rtw_enqueue_recvframe(union recv_frame *precvframe, _queue *queue) ++{ ++ _irqL irqL; ++ _adapter *padapter=precvframe->u.hdr.adapter; ++ struct recv_priv *precvpriv = &padapter->recvpriv; ++ ++_func_enter_; ++ ++ ++ //_spinlock(&pfree_recv_queue->lock); ++ _enter_critical_bh(&queue->lock, &irqL); ++ ++ //_rtw_init_listhead(&(precvframe->u.hdr.list)); ++ rtw_list_delete(&(precvframe->u.hdr.list)); ++ ++ ++ rtw_list_insert_tail(&(precvframe->u.hdr.list), get_list_head(queue)); ++ ++ if (padapter != NULL) { ++ if (queue == &precvpriv->free_recv_queue) ++ precvpriv->free_recvframe_cnt++; ++ } ++ ++ //_rtw_spinunlock(&pfree_recv_queue->lock); ++ _exit_critical_bh(&queue->lock, &irqL); ++ ++ ++_func_exit_; ++ ++ return _SUCCESS; ++} ++ ++/* ++sint rtw_enqueue_recvframe(union recv_frame *precvframe, _queue *queue) ++{ ++ return rtw_free_recvframe(precvframe, queue); ++} ++*/ ++ ++ ++ ++ ++/* ++caller : defrag ; recvframe_chk_defrag in recv_thread (passive) ++pframequeue: defrag_queue : will be accessed in recv_thread (passive) ++ ++using spinlock to protect ++ ++*/ ++ ++void rtw_free_recvframe_queue(_queue *pframequeue, _queue *pfree_recv_queue) ++{ ++ union recv_frame *precvframe; ++ _list *plist, *phead; ++ ++_func_enter_; ++ _rtw_spinlock(&pframequeue->lock); ++ ++ phead = get_list_head(pframequeue); ++ plist = get_next(phead); ++ ++ while(rtw_end_of_queue_search(phead, plist) == _FALSE) ++ { ++ precvframe = LIST_CONTAINOR(plist, union recv_frame, u); ++ ++ plist = get_next(plist); ++ ++ //rtw_list_delete(&precvframe->u.hdr.list); // will do this in rtw_free_recvframe() ++ ++ rtw_free_recvframe(precvframe, pfree_recv_queue); ++ } ++ ++ _rtw_spinunlock(&pframequeue->lock); ++ ++_func_exit_; ++ ++} ++ ++sint rtw_enqueue_recvbuf(struct recv_buf *precvbuf, _queue *queue) ++{ ++ _irqL irqL; ++ ++ _enter_critical(&queue->lock, &irqL); ++ ++ rtw_list_delete(&precvbuf->list); ++ ++ rtw_list_insert_tail(&precvbuf->list, get_list_head(queue)); ++ ++ _exit_critical(&queue->lock, &irqL); ++ ++ ++ return _SUCCESS; ++ ++} ++ ++struct recv_buf *rtw_dequeue_recvbuf (_queue *queue) ++{ ++ _irqL irqL; ++ struct recv_buf *precvbuf; ++ _list *plist, *phead; ++ ++ _enter_critical(&queue->lock, &irqL); ++ ++ if(_rtw_queue_empty(queue) == _TRUE) ++ { ++ precvbuf = NULL; ++ } ++ else ++ { ++ phead = get_list_head(queue); ++ ++ plist = get_next(phead); ++ ++ precvbuf = LIST_CONTAINOR(plist, struct recv_buf, list); ++ ++ rtw_list_delete(&precvbuf->list); ++ ++ } ++ ++ _exit_critical(&queue->lock, &irqL); ++ ++ ++ return precvbuf; ++ ++} ++ ++static sint recvframe_chkmic(_adapter *adapter, union recv_frame *precvframe){ ++ ++ sint i,res=_SUCCESS; ++ u32 datalen; ++ u8 miccode[8]; ++ u8 bmic_err=_FALSE,brpt_micerror = _TRUE; ++ u8 *pframe, *payload,*pframemic; ++ u8 *mickey,*iv,rxdata_key_idx; ++ struct sta_info *stainfo; ++ struct rx_pkt_attrib *prxattrib=&precvframe->u.hdr.attrib; ++ struct security_priv *psecuritypriv=&adapter->securitypriv; ++ ++ struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++_func_enter_; ++ ++ stainfo=rtw_get_stainfo(&adapter->stapriv ,&prxattrib->ta[0]); ++ ++ if(prxattrib->encrypt ==_TKIP_) ++ { ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("\n recvframe_chkmic:prxattrib->encrypt ==_TKIP_\n")); ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("\n recvframe_chkmic:da=0x%02x:0x%02x:0x%02x:0x%02x:0x%02x:0x%02x\n", ++ prxattrib->ra[0],prxattrib->ra[1],prxattrib->ra[2],prxattrib->ra[3],prxattrib->ra[4],prxattrib->ra[5])); ++ ++ //calculate mic code ++ if(stainfo!= NULL) ++ { ++ if(IS_MCAST(prxattrib->ra)) ++ { ++ //mickey=&psecuritypriv->dot118021XGrprxmickey.skey[0]; ++ //iv = precvframe->u.hdr.rx_data+prxattrib->hdrlen; ++ //rxdata_key_idx =( ((iv[3])>>6)&0x3) ; ++ mickey=&psecuritypriv->dot118021XGrprxmickey[prxattrib->key_index].skey[0]; ++ ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("\n recvframe_chkmic: bcmc key \n")); ++ //DBG_8192C("\n recvframe_chkmic: bcmc key psecuritypriv->dot118021XGrpKeyid(%d),pmlmeinfo->key_index(%d) ,recv key_id(%d)\n", ++ // psecuritypriv->dot118021XGrpKeyid,pmlmeinfo->key_index,rxdata_key_idx); ++ ++ if(psecuritypriv->binstallGrpkey==_FALSE) ++ { ++ res=_FAIL; ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("\n recvframe_chkmic:didn't install group key!!!!!!!!!!\n")); ++ DBG_8192C("\n recvframe_chkmic:didn't install group key!!!!!!!!!!\n"); ++ goto exit; ++ } ++ } ++ else{ ++ mickey=&stainfo->dot11tkiprxmickey.skey[0]; ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("\n recvframe_chkmic: unicast key \n")); ++ } ++ ++ datalen=precvframe->u.hdr.len-prxattrib->hdrlen-prxattrib->iv_len-prxattrib->icv_len-8;//icv_len included the mic code ++ pframe=precvframe->u.hdr.rx_data; ++ payload=pframe+prxattrib->hdrlen+prxattrib->iv_len; ++ ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("\n prxattrib->iv_len=%d prxattrib->icv_len=%d\n",prxattrib->iv_len,prxattrib->icv_len)); ++ ++ //rtw_seccalctkipmic(&stainfo->dot11tkiprxmickey.skey[0],pframe,payload, datalen ,&miccode[0],(unsigned char)prxattrib->priority); //care the length of the data ++ ++ rtw_seccalctkipmic(mickey,pframe,payload, datalen ,&miccode[0],(unsigned char)prxattrib->priority); //care the length of the data ++ ++ pframemic=payload+datalen; ++ ++ bmic_err=_FALSE; ++ ++ for(i=0;i<8;i++){ ++ if(miccode[i] != *(pframemic+i)){ ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("recvframe_chkmic:miccode[%d](%02x) != *(pframemic+%d)(%02x) ",i,miccode[i],i,*(pframemic+i))); ++ bmic_err=_TRUE; ++ } ++ } ++ ++ ++ if(bmic_err==_TRUE){ ++ ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("\n *(pframemic-8)-*(pframemic-1)=0x%02x:0x%02x:0x%02x:0x%02x:0x%02x:0x%02x:0x%02x:0x%02x\n", ++ *(pframemic-8),*(pframemic-7),*(pframemic-6),*(pframemic-5),*(pframemic-4),*(pframemic-3),*(pframemic-2),*(pframemic-1))); ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("\n *(pframemic-16)-*(pframemic-9)=0x%02x:0x%02x:0x%02x:0x%02x:0x%02x:0x%02x:0x%02x:0x%02x\n", ++ *(pframemic-16),*(pframemic-15),*(pframemic-14),*(pframemic-13),*(pframemic-12),*(pframemic-11),*(pframemic-10),*(pframemic-9))); ++ ++ { ++ uint i; ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("\n ======demp packet (len=%d)======\n",precvframe->u.hdr.len)); ++ for(i=0;iu.hdr.len;i=i+8){ ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("0x%02x:0x%02x:0x%02x:0x%02x:0x%02x:0x%02x:0x%02x:0x%02x", ++ *(precvframe->u.hdr.rx_data+i),*(precvframe->u.hdr.rx_data+i+1), ++ *(precvframe->u.hdr.rx_data+i+2),*(precvframe->u.hdr.rx_data+i+3), ++ *(precvframe->u.hdr.rx_data+i+4),*(precvframe->u.hdr.rx_data+i+5), ++ *(precvframe->u.hdr.rx_data+i+6),*(precvframe->u.hdr.rx_data+i+7))); ++ } ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("\n ======demp packet end [len=%d]======\n",precvframe->u.hdr.len)); ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("\n hrdlen=%d, \n",prxattrib->hdrlen)); ++ } ++ ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("ra=0x%.2x 0x%.2x 0x%.2x 0x%.2x 0x%.2x 0x%.2x psecuritypriv->binstallGrpkey=%d ", ++ prxattrib->ra[0],prxattrib->ra[1],prxattrib->ra[2], ++ prxattrib->ra[3],prxattrib->ra[4],prxattrib->ra[5],psecuritypriv->binstallGrpkey)); ++ ++ // double check key_index for some timing issue , ++ // cannot compare with psecuritypriv->dot118021XGrpKeyid also cause timing issue ++ if((IS_MCAST(prxattrib->ra)==_TRUE) && (prxattrib->key_index != pmlmeinfo->key_index )) ++ brpt_micerror = _FALSE; ++ ++ if((prxattrib->bdecrypted ==_TRUE)&& (brpt_micerror == _TRUE)) ++ { ++ rtw_handle_tkip_mic_err(adapter,(u8)IS_MCAST(prxattrib->ra)); ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,(" mic error :prxattrib->bdecrypted=%d ",prxattrib->bdecrypted)); ++ DBG_8192C(" mic error :prxattrib->bdecrypted=%d\n",prxattrib->bdecrypted); ++ } ++ else ++ { ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,(" mic error :prxattrib->bdecrypted=%d ",prxattrib->bdecrypted)); ++ DBG_8192C(" mic error :prxattrib->bdecrypted=%d\n",prxattrib->bdecrypted); ++ } ++ ++ res=_FAIL; ++ ++ } ++ else{ ++ //mic checked ok ++ if((psecuritypriv->bcheck_grpkey ==_FALSE)&&(IS_MCAST(prxattrib->ra)==_TRUE)){ ++ psecuritypriv->bcheck_grpkey =_TRUE; ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("psecuritypriv->bcheck_grpkey =_TRUE")); ++ } ++ } ++ ++ } ++ else ++ { ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("recvframe_chkmic: rtw_get_stainfo==NULL!!!\n")); ++ } ++ ++ recvframe_pull_tail(precvframe, 8); ++ ++ } ++ ++exit: ++ ++_func_exit_; ++ ++ return res; ++ ++} ++ ++//decrypt and set the ivlen,icvlen of the recv_frame ++static union recv_frame * decryptor(_adapter *padapter,union recv_frame *precv_frame) ++{ ++ u32 res=_SUCCESS; ++ ++ struct rx_pkt_attrib *prxattrib = &precv_frame->u.hdr.attrib; ++ struct security_priv *psecuritypriv=&padapter->securitypriv; ++ union recv_frame *return_packet=precv_frame; ++ ++_func_enter_; ++ ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("prxstat->decrypted=%x prxattrib->encrypt = 0x%03x\n",prxattrib->bdecrypted,prxattrib->encrypt)); ++ ++ if(prxattrib->encrypt>0) ++ { ++ u8 *iv = precv_frame->u.hdr.rx_data+prxattrib->hdrlen; ++ prxattrib->key_index = ( ((iv[3])>>6)&0x3) ; ++ ++ if(prxattrib->key_index > WEP_KEYS) ++ { ++ DBG_871X("prxattrib->key_index(%d) > WEP_KEYS \n", prxattrib->key_index); ++ ++ switch(prxattrib->encrypt){ ++ case _WEP40_: ++ case _WEP104_: ++ prxattrib->key_index = psecuritypriv->dot11PrivacyKeyIndex; ++ break; ++ case _TKIP_: ++ case _AES_: ++ default: ++ prxattrib->key_index = psecuritypriv->dot118021XGrpKeyid; ++ break; ++ } ++ } ++ } ++ ++ if((prxattrib->encrypt>0) && ((prxattrib->bdecrypted==0) ||(psecuritypriv->sw_decrypt==_TRUE))) ++ { ++ psecuritypriv->hw_decrypted=_FALSE; ++ ++ #ifdef DBG_RX_DECRYPTOR ++ DBG_871X("prxstat->bdecrypted:%d, prxattrib->encrypt:%d, Setting psecuritypriv->hw_decrypted = %d\n" ++ , prxattrib->bdecrypted ,prxattrib->encrypt, psecuritypriv->hw_decrypted); ++ #endif ++ ++ switch(prxattrib->encrypt){ ++ case _WEP40_: ++ case _WEP104_: ++ rtw_wep_decrypt(padapter, (u8 *)precv_frame); ++ break; ++ case _TKIP_: ++ res = rtw_tkip_decrypt(padapter, (u8 *)precv_frame); ++ break; ++ case _AES_: ++ res = rtw_aes_decrypt(padapter, (u8 * )precv_frame); ++ break; ++ default: ++ break; ++ } ++ } ++ else if(prxattrib->bdecrypted==1 ++ && prxattrib->encrypt >0 ++ && (psecuritypriv->busetkipkey==1 || prxattrib->encrypt !=_TKIP_ ) ++ ) ++ { ++#if 0 ++ if((prxstat->icv==1)&&(prxattrib->encrypt!=_AES_)) ++ { ++ psecuritypriv->hw_decrypted=_FALSE; ++ ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("psecuritypriv->hw_decrypted=_FALSE")); ++ ++ rtw_free_recvframe(precv_frame, &padapter->recvpriv.free_recv_queue); ++ ++ return_packet=NULL; ++ ++ } ++ else ++#endif ++ { ++ psecuritypriv->hw_decrypted=_TRUE; ++ #ifdef DBG_RX_DECRYPTOR ++ DBG_871X("prxstat->bdecrypted:%d, prxattrib->encrypt:%d, Setting psecuritypriv->hw_decrypted = %d\n" ++ , prxattrib->bdecrypted ,prxattrib->encrypt, psecuritypriv->hw_decrypted); ++ #endif ++ ++ } ++ } ++ else { ++ #ifdef DBG_RX_DECRYPTOR ++ DBG_871X("prxstat->bdecrypted:%d, prxattrib->encrypt:%d, psecuritypriv->hw_decrypted:%d\n" ++ , prxattrib->bdecrypted ,prxattrib->encrypt, psecuritypriv->hw_decrypted); ++ #endif ++ } ++ ++ if(res == _FAIL) ++ { ++ rtw_free_recvframe(return_packet,&padapter->recvpriv.free_recv_queue); ++ return_packet = NULL; ++ ++ } ++ //recvframe_chkmic(adapter, precv_frame); //move to recvframme_defrag function ++ ++_func_exit_; ++ ++ return return_packet; ++ ++} ++//###set the security information in the recv_frame ++static union recv_frame * portctrl(_adapter *adapter,union recv_frame * precv_frame) ++{ ++ u8 *psta_addr,*ptr; ++ uint auth_alg; ++ struct recv_frame_hdr *pfhdr; ++ struct sta_info * psta; ++ struct sta_priv *pstapriv ; ++ union recv_frame * prtnframe; ++ u16 ether_type=0; ++ u16 eapol_type = 0x888e;//for Funia BD's WPA issue ++ struct rx_pkt_attrib *pattrib = & precv_frame->u.hdr.attrib; ++ ++_func_enter_; ++ ++ pstapriv = &adapter->stapriv; ++ ptr = get_recvframe_data(precv_frame); ++ pfhdr = &precv_frame->u.hdr; ++ psta_addr = pfhdr->attrib.ta; ++ psta = rtw_get_stainfo(pstapriv, psta_addr); ++ ++ auth_alg = adapter->securitypriv.dot11AuthAlgrthm; ++ ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("########portctrl:adapter->securitypriv.dot11AuthAlgrthm= 0x%d\n",adapter->securitypriv.dot11AuthAlgrthm)); ++ ++ if(auth_alg==2) ++ { ++ if ((psta!=NULL) && (psta->ieee8021x_blocked)) ++ { ++ //blocked ++ //only accept EAPOL frame ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("########portctrl:psta->ieee8021x_blocked==1\n")); ++ ++ prtnframe=precv_frame; ++ ++ //get ether_type ++ ptr=ptr+pfhdr->attrib.hdrlen+pfhdr->attrib.iv_len+LLC_HEADER_SIZE; ++ _rtw_memcpy(ðer_type,ptr, 2); ++ ether_type= ntohs((unsigned short )ether_type); ++ ++ if (ether_type == eapol_type) { ++ prtnframe=precv_frame; ++ } ++ else { ++ //free this frame ++ rtw_free_recvframe(precv_frame, &adapter->recvpriv.free_recv_queue); ++ prtnframe=NULL; ++ } ++ } ++ else ++ { ++ //allowed ++ //check decryption status, and decrypt the frame if needed ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("########portctrl:psta->ieee8021x_blocked==0\n")); ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("portctrl:precv_frame->hdr.attrib.privacy=%x\n",precv_frame->u.hdr.attrib.privacy)); ++ ++ if(pattrib->bdecrypted==0) ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("portctrl:prxstat->decrypted=%x\n", pattrib->bdecrypted)); ++ ++ prtnframe=precv_frame; ++ //check is the EAPOL frame or not (Rekey) ++ if(ether_type == eapol_type){ ++ ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("########portctrl:ether_type == 0x888e\n")); ++ //check Rekey ++ ++ prtnframe=precv_frame; ++ } ++ else{ ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("########portctrl:ether_type = 0x%.4x\n",ether_type)); ++ } ++ } ++ } ++ else ++ { ++ prtnframe=precv_frame; ++ } ++ ++_func_exit_; ++ ++ return prtnframe; ++ ++} ++ ++static sint recv_decache(union recv_frame *precv_frame, u8 bretry, struct stainfo_rxcache *prxcache) ++{ ++ sint tid = precv_frame->u.hdr.attrib.priority; ++ ++ u16 seq_ctrl = ( (precv_frame->u.hdr.attrib.seq_num&0xffff) << 4) | ++ (precv_frame->u.hdr.attrib.frag_num & 0xf); ++ ++_func_enter_; ++ ++ if(tid>15) ++ { ++ RT_TRACE(_module_rtl871x_recv_c_, _drv_notice_, ("recv_decache, (tid>15)! seq_ctrl=0x%x, tid=0x%x\n", seq_ctrl, tid)); ++ ++ return _FAIL; ++ } ++ ++ if(1)//if(bretry) ++ { ++ if(seq_ctrl == prxcache->tid_rxseq[tid]) ++ { ++ RT_TRACE(_module_rtl871x_recv_c_, _drv_notice_, ("recv_decache, seq_ctrl=0x%x, tid=0x%x, tid_rxseq=0x%x\n", seq_ctrl, tid, prxcache->tid_rxseq[tid])); ++ ++ return _FAIL; ++ } ++ } ++ ++ prxcache->tid_rxseq[tid] = seq_ctrl; ++ ++_func_exit_; ++ ++ return _SUCCESS; ++ ++} ++ ++static void process_pwrbit_data(_adapter *padapter, union recv_frame *precv_frame) ++{ ++#ifdef CONFIG_AP_MODE ++ unsigned char pwrbit; ++ u8 *ptr = precv_frame->u.hdr.rx_data; ++ struct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib; ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ struct sta_info *psta=NULL; ++ ++ psta = rtw_get_stainfo(pstapriv, pattrib->src); ++ ++ pwrbit = GetPwrMgt(ptr); ++ ++ if(psta) ++ { ++ if(pwrbit) ++ { ++ if(!(psta->state & WIFI_SLEEP_STATE)) ++ { ++ //psta->state |= WIFI_SLEEP_STATE; ++ //pstapriv->sta_dz_bitmap |= BIT(psta->aid); ++ ++ stop_sta_xmit(padapter, psta); ++ ++ //DBG_871X("to sleep, sta_dz_bitmap=%x\n", pstapriv->sta_dz_bitmap); ++ } ++ } ++ else ++ { ++ if(psta->state & WIFI_SLEEP_STATE) ++ { ++ //psta->state ^= WIFI_SLEEP_STATE; ++ //pstapriv->sta_dz_bitmap &= ~BIT(psta->aid); ++ ++ wakeup_sta_to_xmit(padapter, psta); ++ ++ //DBG_871X("to wakeup, sta_dz_bitmap=%x\n", pstapriv->sta_dz_bitmap); ++ } ++ } ++ ++ } ++ ++#endif ++} ++ ++static void process_wmmps_data(_adapter *padapter, union recv_frame *precv_frame) ++{ ++#ifdef CONFIG_AP_MODE ++ struct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib; ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ struct sta_info *psta=NULL; ++ ++ psta = rtw_get_stainfo(pstapriv, pattrib->src); ++ ++ if(!psta) return; ++ ++#ifdef CONFIG_TDLS ++ if( !(psta->tdls_sta_state & TDLS_LINKED_STATE ) ) ++ { ++#endif //CONFIG_TDLS ++ ++ if(!psta->qos_option) ++ return; ++ ++ if(!(psta->qos_info&0xf)) ++ return; ++ ++#ifdef CONFIG_TDLS ++ } ++#endif //CONFIG_TDLS ++ ++ if(psta->state&WIFI_SLEEP_STATE) ++ { ++ u8 wmmps_ac=0; ++ ++ switch(pattrib->priority) ++ { ++ case 1: ++ case 2: ++ wmmps_ac = psta->uapsd_bk&BIT(1); ++ break; ++ case 4: ++ case 5: ++ wmmps_ac = psta->uapsd_vi&BIT(1); ++ break; ++ case 6: ++ case 7: ++ wmmps_ac = psta->uapsd_vo&BIT(1); ++ break; ++ case 0: ++ case 3: ++ default: ++ wmmps_ac = psta->uapsd_be&BIT(1); ++ break; ++ } ++ ++ if(wmmps_ac) ++ { ++ if(psta->sleepq_ac_len>0) ++ { ++ //process received triggered frame ++ xmit_delivery_enabled_frames(padapter, psta); ++ } ++ else ++ { ++ //issue one qos null frame with More data bit = 0 and the EOSP bit set (=1) ++ issue_qos_nulldata(padapter, psta->hwaddr, (u16)pattrib->priority); ++ } ++ } ++ ++ } ++ ++ ++#endif ++ ++} ++ ++#ifdef CONFIG_TDLS ++sint On_TDLS_Setup_Req(_adapter *adapter, union recv_frame *precv_frame) ++{ ++ struct tdls_info *ptdlsinfo = &adapter->tdlsinfo; ++ u8 *psa, *pmyid; ++ struct sta_info *ptdls_sta= NULL; ++ struct sta_priv *pstapriv = &adapter->stapriv; ++ u8 *ptr = precv_frame->u.hdr.rx_data; ++ struct mlme_priv *pmlmepriv = &(adapter->mlmepriv); ++ struct security_priv *psecuritypriv = &adapter->securitypriv; ++ _irqL irqL; ++ struct rx_pkt_attrib *prx_pkt_attrib = &precv_frame->u.hdr.attrib; ++ u8 *prsnie, *ppairwise_cipher; ++ u8 i, k, pairwise_count; ++ u8 ccmp_have=0, rsnie_have=0; ++ u16 j; ++ u8 SNonce[32]; ++ u32 *timeout_interval; ++ sint parsing_length; //frame body length, without icv_len ++ PNDIS_802_11_VARIABLE_IEs pIE; ++ u8 FIXED_IE = 5; ++ ++ psa = get_sa(ptr); ++ ptdls_sta = rtw_get_stainfo(pstapriv, psa); ++ ++ pmyid=myid(&(adapter->eeprompriv)); ++ ptr +=prx_pkt_attrib->hdrlen + prx_pkt_attrib->iv_len+LLC_HEADER_SIZE+TYPE_LENGTH_FIELD_SIZE+1; ++ parsing_length= ((union recv_frame *)precv_frame)->u.hdr.len ++ -prx_pkt_attrib->hdrlen ++ -prx_pkt_attrib->iv_len ++ -prx_pkt_attrib->icv_len ++ -LLC_HEADER_SIZE ++ -TYPE_LENGTH_FIELD_SIZE ++ -1 ++ -FIXED_IE; ++ ++ if(ptdlsinfo->ap_prohibited == _TRUE) ++ { ++ goto exit; ++ } ++ ++ if(ptdls_sta==NULL ||(ptdls_sta->tdls_sta_state&TDLS_LINKED_STATE) ) ++ { ++ if(ptdls_sta==NULL){ ++ ptdls_sta = rtw_alloc_stainfo(pstapriv, psa); ++ }else{ ++ //If the direct link is already set up ++ //Process as re-setup after tear down ++ DBG_8192C("re-setup a direct link\n"); ++ } ++ ++ if(ptdls_sta) ++ { ++ //copy dialog token ++ ptdls_sta->dialog = *(ptr+2); ++ ++ //parsing information element ++ for(j=FIXED_IE; jElementID) ++ { ++ case _SUPPORTEDRATES_IE_: ++ break; ++ case _COUNTRY_IE_: ++ break; ++ case _EXT_SUPPORTEDRATES_IE_: ++ break; ++ case _SUPPORTED_CH_IE_: ++ break; ++ case _RSN_IE_2_: ++ rsnie_have=1; ++ if(prx_pkt_attrib->encrypt){ ++ prsnie=(u8*)pIE; ++ //check whether initiator STA has CCMP pairwise_cipher. ++ ppairwise_cipher=prsnie+10; ++ _rtw_memcpy(&pairwise_count, (u16*)(ppairwise_cipher-2), 1); ++ for(k=0;kstat_code=72; ++ } ++ } ++ break; ++ case _EXT_CAP_IE_: ++ break; ++ case _VENDOR_SPECIFIC_IE_: ++ break; ++ case _FTIE_: ++ if(prx_pkt_attrib->encrypt) ++ _rtw_memcpy(SNonce, (ptr+j+52), 32); ++ break; ++ case _TIMEOUT_ITVL_IE_: ++ if(prx_pkt_attrib->encrypt) ++ timeout_interval = (u32 *)(ptr+j+3); ++ break; ++ case _RIC_Descriptor_IE_: ++ break; ++ case _HT_CAPABILITY_IE_: ++ break; ++ case EID_BSSCoexistence: ++ break; ++ case _LINK_ID_IE_: ++ if(_rtw_memcmp(get_bssid(pmlmepriv), pIE->data, 6) == _FALSE) ++ { ++ //not in same BSS ++ ptdls_sta->stat_code=7; ++ } ++ break; ++ default: ++ break; ++ } ++ ++ j += (pIE->Length + 2); ++ ++ } ++ ++ //check status code ++ //if responder STA has/hasn't security on AP, but request hasn't/has RSNIE, it should reject ++ if( ++ ( rsnie_have && (prx_pkt_attrib->encrypt) ) ++ || ++ (rsnie_have==0 && (prx_pkt_attrib->encrypt==0) ) ++ ){ ++ ptdls_sta->stat_code=0; ++ }else if(rsnie_have && (prx_pkt_attrib->encrypt==0)){ ++ //security disabled ++ ptdls_sta->stat_code=5; ++ }else if(rsnie_have==0 && (prx_pkt_attrib->encrypt)){ ++ //request haven't RSNIE ++ ptdls_sta->stat_code=38; ++ } ++ ++ ptdls_sta->tdls_sta_state|= TDLS_INITIATOR_STATE; ++ if(prx_pkt_attrib->encrypt){ ++ _rtw_memcpy(ptdls_sta->SNonce, SNonce, 32); ++ _rtw_memcpy(&(ptdls_sta->TDLS_PeerKey_Lifetime), timeout_interval, 4); ++ } ++ _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL); ++ ptdlsinfo->sta_cnt++; ++ _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL); ++ if( ptdlsinfo->sta_cnt == (NUM_STA - 1) ) ++ { ++ ptdlsinfo->sta_maximum = _TRUE; ++ } ++ } ++ else ++ { ++ goto exit; ++ } ++ } ++ //already receiving TDLS setup request ++ else if(ptdls_sta->tdls_sta_state==TDLS_INITIATOR_STATE){ ++ DBG_8192C("receive duplicated TDLS setup request frame in handshaking\n"); ++ goto exit; ++ } ++ //When receiving and sending setup_req to the same link at the same time, STA with higher MAC_addr would be initiator ++ //following is to check out MAC_addr ++ else if(ptdls_sta->tdls_sta_state==TDLS_RESPONDER_STATE){ ++ DBG_8192C("receive setup_req after sending setup_req\n"); ++ for (i=0;i<6;i++){ ++ if(*(pmyid+i)==*(psa+i)){ ++ } ++ else if(*(pmyid+i)>*(psa+i)){ ++ goto exit; ++ }else if(*(pmyid+i)<*(psa+i)){ ++ ptdls_sta->tdls_sta_state=TDLS_INITIATOR_STATE; ++ break; ++ } ++ } ++ } ++ ++ issue_tdls_setup_rsp(adapter, precv_frame); ++ _set_timer( &ptdls_sta->handshake_timer, TDLS_HANDSHAKE_TIME); ++ ++ //status code!=0 ; setup unsuccess ++ if(ptdls_sta->stat_code!=0){ ++ free_tdls_sta(adapter, ptdls_sta); ++ return _FAIL; ++ } ++ ++exit: ++ ++ return _FAIL; ++} ++ ++ ++sint On_TDLS_Setup_Rsp(_adapter *adapter, union recv_frame *precv_frame) ++{ ++ struct tdls_info *ptdlsinfo = &adapter->tdlsinfo; ++ struct sta_info *ptdls_sta= NULL; ++ struct sta_priv *pstapriv = &adapter->stapriv; ++ u8 *ptr = precv_frame->u.hdr.rx_data; ++ _irqL irqL; ++ struct rx_pkt_attrib *prx_pkt_attrib = &precv_frame->u.hdr.attrib; ++ u8 *psa; ++ u16 stat_code; ++ sint parsing_length; //frame body length, without icv_len ++ PNDIS_802_11_VARIABLE_IEs pIE; ++ u8 FIXED_IE =7; ++ u8 *pftie, *ptimeout_ie, *plinkid_ie, *prsnie, *pftie_mic, *ppairwise_cipher; ++ u16 pairwise_count, j, k; ++ u8 verify_ccmp=0; ++ ++ psa = get_sa(ptr); ++ ptdls_sta = rtw_get_stainfo(pstapriv, psa); ++ ++ ptr +=prx_pkt_attrib->hdrlen + prx_pkt_attrib->iv_len+LLC_HEADER_SIZE+TYPE_LENGTH_FIELD_SIZE+1; ++ parsing_length= ((union recv_frame *)precv_frame)->u.hdr.len ++ -prx_pkt_attrib->hdrlen ++ -prx_pkt_attrib->iv_len ++ -prx_pkt_attrib->icv_len ++ -LLC_HEADER_SIZE ++ -TYPE_LENGTH_FIELD_SIZE ++ -1 ++ -FIXED_IE; ++ _rtw_memcpy(&stat_code, ptr+2, 2); ++ ++ if(stat_code!=0){ ++ free_tdls_sta(adapter, ptdls_sta); ++ return _FAIL; ++ } ++ ++ //parsing information element ++ for(j=FIXED_IE; jElementID) ++ { ++ case _SUPPORTEDRATES_IE_: ++ break; ++ case _COUNTRY_IE_: ++ break; ++ case _EXT_SUPPORTEDRATES_IE_: ++ break; ++ case _SUPPORTED_CH_IE_: ++ break; ++ case _RSN_IE_2_: ++ prsnie=(u8*)pIE; ++ //check whether responder STA has CCMP pairwise_cipher. ++ ppairwise_cipher=prsnie+10; ++ _rtw_memcpy(&pairwise_count, (u16*)(ppairwise_cipher-2), 2); ++ for(k=0;kANonce, (ptr+j+20), 32); ++ break; ++ case _TIMEOUT_ITVL_IE_: ++ ptimeout_ie=(u8*)pIE; ++ break; ++ case _RIC_Descriptor_IE_: ++ break; ++ case _HT_CAPABILITY_IE_: ++ break; ++ case EID_BSSCoexistence: ++ break; ++ case _LINK_ID_IE_: ++ plinkid_ie=(u8*)pIE; ++ break; ++ default: ++ break; ++ } ++ ++ j += (pIE->Length + 2); ++ ++ } ++ ++ if(prx_pkt_attrib->encrypt){ ++ if(verify_ccmp==1){ ++ wpa_tdls_generate_tpk(adapter, ptdls_sta); ++ ptdls_sta->stat_code=0; ++ } ++ else{ ++ ptdls_sta->stat_code=72; //invalide contents of RSNIE ++ } ++ }else{ ++ ptdls_sta->stat_code=0; ++ } ++ ++ if(prx_pkt_attrib->encrypt){ ++ if(tdls_verify_mic(ptdls_sta->tpk.kck, 2, plinkid_ie, prsnie, ptimeout_ie, pftie)==0){ //0: Invalid, 1: valid ++ free_tdls_sta(adapter, ptdls_sta); ++ return _FAIL; ++ } ++ } ++ ++ DBG_871X("issue_tdls_setup_cfm\n"); ++ issue_tdls_setup_cfm(adapter, precv_frame); ++ ++ //status code!=0 ; setup unsuccess ++ if(ptdls_sta->stat_code!=0){ ++ free_tdls_sta(adapter, ptdls_sta); ++ return _FAIL; ++ } ++ ++ ptdlsinfo->setup_state = TDLS_LINKED_STATE; ++ ++ ptdls_sta->option=1; ++ rtw_tdls_cmd(adapter, ptdls_sta->hwaddr, TDLS_WRCR); ++ ++ if( ptdls_sta->tdls_sta_state & TDLS_RESPONDER_STATE ) ++ { ++ ptdls_sta->tdls_sta_state |= TDLS_LINKED_STATE; ++ _cancel_timer_ex( &ptdls_sta->handshake_timer); ++#ifdef CONFIG_TDLS_AUTOCHECKALIVE ++ _set_timer( &ptdls_sta->alive_timer1, TDLS_ALIVE_TIMER_PH1); ++#endif //CONFIG_TDLS_AUTOSETUP ++ } ++ ++ if(prx_pkt_attrib->encrypt){ ++ if(ptdls_sta->cam_entry==0){ ++ ptdls_sta->dot118021XPrivacy=_AES_; ++ ptdls_sta->cam_entry=ptdlsinfo->cam_entry_to_write; ++ if(++ptdlsinfo->cam_entry_to_write>31) ++ ptdlsinfo->cam_entry_to_write=6; ++ } ++ rtw_setstakey_cmd(adapter, (u8*)ptdls_sta, _TRUE); ++ } ++ ++ return _FAIL; ++ ++} ++ ++sint On_TDLS_Setup_Cfm(_adapter *adapter, union recv_frame *precv_frame) ++{ ++ struct tdls_info *ptdlsinfo = &adapter->tdlsinfo; ++ struct sta_info *ptdls_sta= NULL; ++ struct sta_priv *pstapriv = &adapter->stapriv; ++ u8 *ptr = precv_frame->u.hdr.rx_data; ++ _irqL irqL; ++ struct rx_pkt_attrib *prx_pkt_attrib = &precv_frame->u.hdr.attrib; ++ u8 *psa; ++ u16 stat_code; ++ sint parsing_length; ++ PNDIS_802_11_VARIABLE_IEs pIE; ++ u8 FIXED_IE =5; ++ u8 *pftie, *ptimeout_ie, *plinkid_ie, *prsnie, *pftie_mic, *ppairwise_cipher; ++ u16 j, pairwise_count; ++ ++ psa = get_sa(ptr); ++ ptdls_sta = rtw_get_stainfo(pstapriv, psa); ++ ++ //[+1]: payload type ++ ptr +=prx_pkt_attrib->hdrlen + prx_pkt_attrib->iv_len+LLC_HEADER_SIZE+TYPE_LENGTH_FIELD_SIZE+1; ++ parsing_length= ((union recv_frame *)precv_frame)->u.hdr.len ++ -prx_pkt_attrib->hdrlen ++ -prx_pkt_attrib->iv_len ++ -prx_pkt_attrib->icv_len ++ -LLC_HEADER_SIZE ++ -TYPE_LENGTH_FIELD_SIZE ++ -1 ++ -FIXED_IE; ++ _rtw_memcpy(&stat_code, ptr+2, 2); ++ ++ if(stat_code!=0){ ++ free_tdls_sta(adapter, ptdls_sta); ++ return _FAIL; ++ } ++ ++ if(prx_pkt_attrib->encrypt){ ++ //parsing information element ++ for(j=FIXED_IE; jElementID) ++ { ++ case _RSN_IE_2_: ++ prsnie=(u8*)pIE; ++ break; ++ case _VENDOR_SPECIFIC_IE_: ++ break; ++ case _FTIE_: ++ pftie=(u8*)pIE; ++ break; ++ case _TIMEOUT_ITVL_IE_: ++ ptimeout_ie=(u8*)pIE; ++ break; ++ case _HT_EXTRA_INFO_IE_: ++ break; ++ case _LINK_ID_IE_: ++ plinkid_ie=(u8*)pIE; ++ break; ++ default: ++ break; ++ } ++ ++ j += (pIE->Length + 2); ++ ++ } ++ ++ //verify mic in FTIE MIC field ++ if(tdls_verify_mic(ptdls_sta->tpk.kck, 3, plinkid_ie, prsnie, ptimeout_ie, pftie)==0){ //0: Invalid, 1: Valid ++ free_tdls_sta(adapter, ptdls_sta); ++ return _FAIL; ++ } ++ ++ } ++ ++ ptdlsinfo->setup_state = TDLS_LINKED_STATE; ++ if( ptdls_sta->tdls_sta_state & TDLS_INITIATOR_STATE ) ++ { ++ ptdls_sta->tdls_sta_state|=TDLS_LINKED_STATE; ++ _cancel_timer_ex( &ptdls_sta->handshake_timer); ++#ifdef CONFIG_TDLS_AUTOCHECKALIVE ++ _set_timer( &ptdls_sta->alive_timer1, TDLS_ALIVE_TIMER_PH1); ++#endif //CONFIG_TDLS_AUTOCHECKALIVE ++ } ++ ++ ptdls_sta->option=1; //write RCR DATA BIT ++ rtw_tdls_cmd(adapter, ptdls_sta->hwaddr, TDLS_WRCR); ++ ++ //Write cam ++ //TDLS encryption(if needed) will always be CCMP ++ if(prx_pkt_attrib->encrypt){ ++ if(ptdls_sta->cam_entry==0){ ++ ptdls_sta->dot118021XPrivacy=_AES_; ++ ptdls_sta->cam_entry=ptdlsinfo->cam_entry_to_write; ++ if(++ptdlsinfo->cam_entry_to_write>31) ++ ptdlsinfo->cam_entry_to_write=6; ++ } ++ rtw_setstakey_cmd(adapter, (u8*)ptdls_sta, _TRUE); ++ } ++ ++ return _FAIL; ++ ++} ++ ++sint On_TDLS_Dis_Req(_adapter *adapter, union recv_frame *precv_frame) ++{ ++ struct rx_pkt_attrib *prx_pkt_attrib = &precv_frame->u.hdr.attrib; ++ struct sta_priv *pstapriv = &adapter->stapriv; ++ struct sta_info *psta_ap; ++ u8 *ptr = precv_frame->u.hdr.rx_data; ++ sint parsing_length; //frame body length, without icv_len ++ PNDIS_802_11_VARIABLE_IEs pIE; ++ u8 FIXED_IE = 3, *dst, *pdialog = NULL; ++ u16 j; ++ ++ ptr +=prx_pkt_attrib->hdrlen + prx_pkt_attrib->iv_len + LLC_HEADER_SIZE+TYPE_LENGTH_FIELD_SIZE + 1; ++ pdialog=ptr+2; ++ ++ parsing_length= ((union recv_frame *)precv_frame)->u.hdr.len ++ -prx_pkt_attrib->hdrlen ++ -prx_pkt_attrib->iv_len ++ -prx_pkt_attrib->icv_len ++ -LLC_HEADER_SIZE ++ -TYPE_LENGTH_FIELD_SIZE ++ -1 ++ -FIXED_IE; ++ ++ //parsing information element ++ for(j=FIXED_IE; jElementID) ++ { ++ case _LINK_ID_IE_: ++ psta_ap = rtw_get_stainfo(pstapriv, pIE->data); ++ if(psta_ap == NULL) ++ { ++ goto exit; ++ } ++ dst = pIE->data + 12; ++ if( (MacAddr_isBcst(dst) == _FALSE) && (_rtw_memcmp(myid(&(adapter->eeprompriv)), dst, 6) == _FALSE) ) ++ { ++ goto exit; ++ } ++ break; ++ default: ++ break; ++ } ++ ++ j += (pIE->Length + 2); ++ ++ } ++ ++ //check frame contents ++ ++ issue_tdls_dis_rsp(adapter, precv_frame, *(pdialog) ); ++ ++exit: ++ ++ return _FAIL; ++ ++} ++ ++sint On_TDLS_Teardown(_adapter *adapter, union recv_frame *precv_frame) ++{ ++ u8 *psa; ++ u8 *ptr = precv_frame->u.hdr.rx_data; ++ struct rx_pkt_attrib *prx_pkt_attrib = &precv_frame->u.hdr.attrib; ++ struct mlme_ext_priv *pmlmeext = &(adapter->mlmeextpriv); ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ struct sta_priv *pstapriv = &adapter->stapriv; ++ struct sta_info *ptdls_sta= NULL; ++ _irqL irqL; ++ ++ psa = get_sa(ptr); ++ ++ ptdls_sta = rtw_get_stainfo(pstapriv, psa); ++ if(ptdls_sta!=NULL){ ++ ++ if(ptdls_sta->tdls_sta_state & TDLS_CH_SWITCH_ON_STATE){ ++ ptdls_sta->option =3; ++ rtw_tdls_cmd(adapter, ptdls_sta->hwaddr, TDLS_CS_OFF); ++ } ++ free_tdls_sta(adapter, ptdls_sta); ++ } ++ ++ return _FAIL; ++ ++} ++ ++u8 TDLS_check_ch_state(uint state){ ++ if( (state & TDLS_CH_SWITCH_ON_STATE) && ++ (state & TDLS_AT_OFF_CH_STATE) && ++ (state & TDLS_PEER_AT_OFF_STATE) ){ ++ ++ if(state & TDLS_PEER_SLEEP_STATE) ++ return 2; //U-APSD + ch. switch ++ else ++ return 1; //ch. switch ++ }else ++ return 0; ++} ++ ++//we process buffered data for 1. U-APSD, 2. ch. switch, 3. U-APSD + ch. switch here ++sint On_TDLS_Peer_Traffic_Rsp(_adapter *adapter, union recv_frame *precv_frame) ++{ ++ struct tdls_info *ptdlsinfo = &adapter->tdlsinfo; ++ struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; ++ struct rx_pkt_attrib *pattrib = & precv_frame->u.hdr.attrib; ++ struct sta_priv *pstapriv = &adapter->stapriv; ++ //get peer sta infomation ++ struct sta_info *ptdls_sta = rtw_get_stainfo(pstapriv, pattrib->src); ++ u8 wmmps_ac=0, state=TDLS_check_ch_state(ptdls_sta->tdls_sta_state); ++ int i; ++ ++ ptdls_sta->sta_stats.rx_data_pkts++; ++ ++ //receive peer traffic response frame, sleeping STA wakes up ++ //ptdls_sta->tdls_sta_state &= ~(TDLS_PEER_SLEEP_STATE); ++ process_wmmps_data( adapter, precv_frame); ++ ++ // if noticed peer STA wakes up by receiving peer traffic response ++ // and we want to do channel swtiching, then we will transmit channel switch request first ++ if(ptdls_sta->tdls_sta_state & TDLS_APSD_CHSW_STATE){ ++ issue_tdls_ch_switch_req(adapter, pattrib->src); ++ ptdls_sta->tdls_sta_state &= ~(TDLS_APSD_CHSW_STATE); ++ return _FAIL; ++ } ++ ++ //check 4-AC queue bit ++ if(ptdls_sta->uapsd_vo || ptdls_sta->uapsd_vi || ptdls_sta->uapsd_be || ptdls_sta->uapsd_bk) ++ wmmps_ac=1; ++ ++ //if it's a direct link and have buffered frame ++ if(ptdls_sta->tdls_sta_state & TDLS_LINKED_STATE){ ++ if(wmmps_ac && state) ++ { ++ _irqL irqL; ++ _list *xmitframe_plist, *xmitframe_phead; ++ struct xmit_frame *pxmitframe=NULL; ++ ++ _enter_critical_bh(&ptdls_sta->sleep_q.lock, &irqL); ++ ++ xmitframe_phead = get_list_head(&ptdls_sta->sleep_q); ++ xmitframe_plist = get_next(xmitframe_phead); ++ ++ //transmit buffered frames ++ while ((rtw_end_of_queue_search(xmitframe_phead, xmitframe_plist)) == _FALSE) ++ { ++ pxmitframe = LIST_CONTAINOR(xmitframe_plist, struct xmit_frame, list); ++ xmitframe_plist = get_next(xmitframe_plist); ++ rtw_list_delete(&pxmitframe->list); ++ ++ ptdls_sta->sleepq_len--; ++ if(ptdls_sta->sleepq_len>0){ ++ pxmitframe->attrib.mdata = 1; ++ pxmitframe->attrib.eosp = 0; ++ }else{ ++ pxmitframe->attrib.mdata = 0; ++ pxmitframe->attrib.eosp = 1; ++ } ++ //pxmitframe->attrib.triggered = 1; //maybe doesn't need in TDLS ++ if(adapter->HalFunc.hal_xmit(adapter, pxmitframe) == _TRUE) ++ { ++ rtw_os_xmit_complete(adapter, pxmitframe); ++ } ++ ++ } ++ ++ if(ptdls_sta->sleepq_len==0) ++ { ++ DBG_871X("no buffered packets to xmit\n"); ++ //on U-APSD + CH. switch state, when there is no buffered date to xmit, ++ // we should go back to base channel ++ if(state==2){ ++ ptdls_sta->option = 3; ++ rtw_tdls_cmd(adapter, ptdls_sta->hwaddr, TDLS_CS_OFF); ++ }else if(ptdls_sta->tdls_sta_state&TDLS_SW_OFF_STATE){ ++ ptdls_sta->tdls_sta_state &= ~(TDLS_SW_OFF_STATE); ++ ptdlsinfo->candidate_ch= pmlmeext->cur_channel; ++ issue_tdls_ch_switch_req(adapter, pattrib->src); ++ DBG_8192C("issue tdls ch switch req back to base channel\n"); ++ } ++ ++ } ++ else ++ { ++ DBG_871X("error!psta->sleepq_len=%d\n", ptdls_sta->sleepq_len); ++ ptdls_sta->sleepq_len=0; ++ } ++ ++ _exit_critical_bh(&ptdls_sta->sleep_q.lock, &irqL); ++ ++ } ++ ++ } ++ ++ return _FAIL; ++} ++ ++sint On_TDLS_Ch_Switch_Req(_adapter *adapter, union recv_frame *precv_frame) ++{ ++ struct sta_info *ptdls_sta= NULL; ++ struct sta_priv *pstapriv = &adapter->stapriv; ++ u8 *ptr = precv_frame->u.hdr.rx_data; ++ struct rx_pkt_attrib *prx_pkt_attrib = &precv_frame->u.hdr.attrib; ++ u8 *psa; ++ sint parsing_length; ++ PNDIS_802_11_VARIABLE_IEs pIE; ++ u8 FIXED_IE =3; ++ u16 j; ++ struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; ++ ++ psa = get_sa(ptr); ++ ptdls_sta = rtw_get_stainfo(pstapriv, psa); ++ ++ //[+1]: payload type ++ ptr +=prx_pkt_attrib->hdrlen + prx_pkt_attrib->iv_len+LLC_HEADER_SIZE+TYPE_LENGTH_FIELD_SIZE+1; ++ parsing_length= ((union recv_frame *)precv_frame)->u.hdr.len ++ -prx_pkt_attrib->hdrlen ++ -prx_pkt_attrib->iv_len ++ -prx_pkt_attrib->icv_len ++ -LLC_HEADER_SIZE ++ -TYPE_LENGTH_FIELD_SIZE ++ -1 ++ -FIXED_IE; ++ ++ ptdls_sta->off_ch = *(ptr+2); ++ ++ //parsing information element ++ for(j=FIXED_IE; jElementID) ++ { ++ case _COUNTRY_IE_: ++ break; ++ case _CH_SWTICH_ANNOUNCE_: ++ break; ++ case _LINK_ID_IE_: ++ break; ++ case _CH_SWITCH_TIMING_: ++ _rtw_memcpy(&ptdls_sta->ch_switch_time, pIE->data, 2); ++ _rtw_memcpy(&ptdls_sta->ch_switch_timeout, pIE->data+2, 2); ++ default: ++ break; ++ } ++ ++ j += (pIE->Length + 2); ++ ++ } ++ ++ //todo: check status ++ ptdls_sta->stat_code=0; ++ ptdls_sta->tdls_sta_state |= TDLS_CH_SWITCH_ON_STATE; ++ ++ issue_nulldata(adapter, 1); ++ ++ issue_tdls_ch_switch_rsp(adapter, psa); ++ ++ DBG_8192C("issue tdls channel switch response\n"); ++ ++ if((ptdls_sta->tdls_sta_state & TDLS_CH_SWITCH_ON_STATE) && ptdls_sta->off_ch==pmlmeext->cur_channel){ ++ DBG_8192C("back to base channel\n"); ++ ptdls_sta->option=7; ++ rtw_tdls_cmd(adapter, ptdls_sta->hwaddr, TDLS_BASE_CH); ++ }else{ ++ ptdls_sta->option=6; ++ rtw_tdls_cmd(adapter, ptdls_sta->hwaddr, TDLS_OFF_CH); ++ } ++ return _FAIL; ++} ++ ++sint On_TDLS_Ch_Switch_Rsp(_adapter *adapter, union recv_frame *precv_frame) ++{ ++ struct sta_info *ptdls_sta= NULL; ++ struct sta_priv *pstapriv = &adapter->stapriv; ++ u8 *ptr = precv_frame->u.hdr.rx_data; ++ struct rx_pkt_attrib *prx_pkt_attrib = &precv_frame->u.hdr.attrib; ++ u8 *psa; ++ sint parsing_length; ++ PNDIS_802_11_VARIABLE_IEs pIE; ++ u8 FIXED_IE =4; ++ u16 stat_code, j, switch_time, switch_timeout; ++ struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; ++ ++ psa = get_sa(ptr); ++ ptdls_sta = rtw_get_stainfo(pstapriv, psa); ++ ++ //if channel switch is running and receiving Unsolicited TDLS Channel Switch Response, ++ //it will go back to base channel and terminate this channel switch procedure ++ if(ptdls_sta->tdls_sta_state & TDLS_CH_SWITCH_ON_STATE ){ ++ if(pmlmeext->cur_channel==ptdls_sta->off_ch){ ++ DBG_8192C("back to base channel\n"); ++ ptdls_sta->option=7; ++ rtw_tdls_cmd(adapter, ptdls_sta->hwaddr, TDLS_OFF_CH); ++ }else{ ++ DBG_8192C("receive unsolicited channel switch response \n"); ++ ptdls_sta->option=3; ++ rtw_tdls_cmd(adapter, ptdls_sta->hwaddr, TDLS_CS_OFF); ++ } ++ return _FAIL; ++ } ++ ++ //avoiding duplicated or unconditional ch. switch. rsp ++ if((ptdls_sta->tdls_sta_state & TDLS_CH_SW_INITIATOR_STATE) != TDLS_CH_SW_INITIATOR_STATE) ++ return _FAIL; ++ ++ //[+1]: payload type ++ ptr +=prx_pkt_attrib->hdrlen + prx_pkt_attrib->iv_len+LLC_HEADER_SIZE+TYPE_LENGTH_FIELD_SIZE+1; ++ parsing_length= ((union recv_frame *)precv_frame)->u.hdr.len ++ -prx_pkt_attrib->hdrlen ++ -prx_pkt_attrib->iv_len ++ -prx_pkt_attrib->icv_len ++ -LLC_HEADER_SIZE ++ -TYPE_LENGTH_FIELD_SIZE ++ -1 ++ -FIXED_IE; ++ ++ _rtw_memcpy(&stat_code, ptr+2, 2); ++ ++ if(stat_code!=0){ ++ return _FAIL; ++ } ++ ++ //parsing information element ++ for(j=FIXED_IE; jElementID) ++ { ++ case _LINK_ID_IE_: ++ break; ++ case _CH_SWITCH_TIMING_: ++ _rtw_memcpy(&switch_time, pIE->data, 2); ++ if(switch_time > ptdls_sta->ch_switch_time) ++ _rtw_memcpy(&ptdls_sta->ch_switch_time, &switch_time, 2); ++ ++ _rtw_memcpy(&switch_timeout, pIE->data+2, 2); ++ if(switch_timeout > ptdls_sta->ch_switch_timeout) ++ _rtw_memcpy(&ptdls_sta->ch_switch_timeout, &switch_timeout, 2); ++ ++ default: ++ break; ++ } ++ ++ j += (pIE->Length + 2); ++ ++ } ++ ++ ptdls_sta->tdls_sta_state &= ~(TDLS_CH_SW_INITIATOR_STATE); ++ ptdls_sta->tdls_sta_state |=TDLS_CH_SWITCH_ON_STATE; ++ ++ //goto set_channel_workitem_callback() ++ ptdls_sta->option=6; ++ rtw_tdls_cmd(adapter, ptdls_sta->hwaddr, TDLS_OFF_CH); ++ ++ return _FAIL; ++} ++ ++sint OnTDLS(_adapter *adapter, union recv_frame *precv_frame) ++{ ++ struct rx_pkt_attrib *pattrib = & precv_frame->u.hdr.attrib; ++ sint ret = _SUCCESS; ++ u8 *paction = get_recvframe_data(precv_frame); ++ ++ //point to action field, [+8]: snap+ether_type, [+1]: payload_type, [+1]: category field ++ paction+=pattrib->hdrlen + pattrib->iv_len+8+1+1; ++ ++ switch(*paction){ ++ case TDLS_SETUP_REQUEST: ++ DBG_871X("recv tdls setup request frame\n"); ++ ret=On_TDLS_Setup_Req(adapter, precv_frame); ++ break; ++ case TDLS_SETUP_RESPONSE: ++ DBG_871X("recv tdls setup response frame\n"); ++ ret=On_TDLS_Setup_Rsp(adapter, precv_frame); ++ break; ++ case TDLS_SETUP_CONFIRM: ++ DBG_871X("recv tdls setup confirm frame\n"); ++ ret=On_TDLS_Setup_Cfm(adapter, precv_frame); ++ break; ++ case TDLS_TEARDOWN: ++ DBG_871X("recv tdls teardown, free sta_info\n"); ++ ret=On_TDLS_Teardown(adapter, precv_frame); ++ break; ++ case TDLS_DISCOVERY_REQUEST: ++ DBG_871X("recv tdls discovery request frame\n"); ++ ret=On_TDLS_Dis_Req(adapter, precv_frame); ++ break; ++ case TDLS_PEER_TRAFFIC_RESPONSE: ++ DBG_871X("recv tdls peer traffic response frame\n"); ++ ret=On_TDLS_Peer_Traffic_Rsp(adapter, precv_frame); ++ break; ++ case TDLS_CHANNEL_SWITCH_REQUEST: ++ DBG_871X("recv tdls channel switch request frame\n"); ++ ret=On_TDLS_Ch_Switch_Req(adapter, precv_frame); ++ break; ++ case TDLS_CHANNEL_SWITCH_RESPONSE: ++ DBG_871X("recv tdls channel switch response frame\n"); ++ ret=On_TDLS_Ch_Switch_Rsp(adapter, precv_frame); ++ break; ++ default: ++ DBG_871X("receive TDLS frame but not supported\n"); ++ ret=_FAIL; ++ break; ++ } ++ ++exit: ++ return ret; ++ ++} ++#endif ++ ++static void count_rx_stats(_adapter *padapter, union recv_frame *prframe, struct sta_info*sta) ++{ ++ int sz; ++ struct sta_info *psta = NULL; ++ struct stainfo_stats *pstats = NULL; ++ struct rx_pkt_attrib *pattrib = & prframe->u.hdr.attrib; ++ struct recv_priv *precvpriv = &padapter->recvpriv; ++ ++ sz = get_recvframe_len(prframe); ++ precvpriv->rx_bytes += sz; ++ ++ padapter->mlmepriv.LinkDetectInfo.NumRxOkInPeriod++; ++ ++ if( (!MacAddr_isBcst(pattrib->dst)) && (!IS_MCAST(pattrib->dst))){ ++ padapter->mlmepriv.LinkDetectInfo.NumRxUnicastOkInPeriod++; ++ } ++ ++ if(sta) ++ psta = sta; ++ else ++ psta = prframe->u.hdr.psta; ++ ++ if(psta) ++ { ++ pstats = &psta->sta_stats; ++ ++ pstats->rx_data_pkts++; ++ pstats->rx_bytes += sz; ++ } ++ ++} ++ ++static sint sta2sta_data_frame( ++ _adapter *adapter, ++ union recv_frame *precv_frame, ++ struct sta_info**psta ++) ++{ ++ u8 *ptr = precv_frame->u.hdr.rx_data; ++ sint ret = _SUCCESS; ++ struct rx_pkt_attrib *pattrib = & precv_frame->u.hdr.attrib; ++ struct sta_priv *pstapriv = &adapter->stapriv; ++ struct security_priv *psecuritypriv = &adapter->securitypriv; ++ struct mlme_priv *pmlmepriv = &adapter->mlmepriv; ++ u8 *mybssid = get_bssid(pmlmepriv); ++ u8 *myhwaddr = myid(&adapter->eeprompriv); ++ u8 * sta_addr = NULL; ++ sint bmcast = IS_MCAST(pattrib->dst); ++ ++#ifdef CONFIG_TDLS ++ struct tdls_info *ptdlsinfo = &adapter->tdlsinfo; ++ struct sta_info *ptdls_sta=NULL; ++ u8 *psnap_type=ptr+pattrib->hdrlen + pattrib->iv_len+SNAP_SIZE; ++ //frame body located after [+2]: ether-type, [+1]: payload type ++ u8 *pframe_body = psnap_type+2+1; ++#endif ++ ++_func_enter_; ++ ++ if ((check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE) || ++ (check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE)) ++ { ++ ++ // filter packets that SA is myself or multicast or broadcast ++ if (_rtw_memcmp(myhwaddr, pattrib->src, ETH_ALEN)){ ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,(" SA==myself \n")); ++ ret= _FAIL; ++ goto exit; ++ } ++ ++ if( (!_rtw_memcmp(myhwaddr, pattrib->dst, ETH_ALEN)) && (!bmcast) ){ ++ ret= _FAIL; ++ goto exit; ++ } ++ ++ if( _rtw_memcmp(pattrib->bssid, "\x0\x0\x0\x0\x0\x0", ETH_ALEN) || ++ _rtw_memcmp(mybssid, "\x0\x0\x0\x0\x0\x0", ETH_ALEN) || ++ (!_rtw_memcmp(pattrib->bssid, mybssid, ETH_ALEN)) ) { ++ ret= _FAIL; ++ goto exit; ++ } ++ ++ sta_addr = pattrib->src; ++ ++ } ++ else if(check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE) ++ { ++#ifdef CONFIG_TDLS ++ ++ //direct link data transfer ++ if(ptdlsinfo->setup_state & TDLS_LINKED_STATE){ ++ ptdls_sta = rtw_get_stainfo(pstapriv, pattrib->src); ++ if(ptdls_sta==NULL) ++ { ++ ret=_FAIL; ++ goto exit; ++ } ++ else if((ptdls_sta->tdls_sta_state&TDLS_LINKED_STATE)==TDLS_LINKED_STATE) ++ { ++ ++ //drop QoS-SubType Data, including QoS NULL, excluding QoS-Data ++ if( (GetFrameSubType(ptr) & WIFI_QOS_DATA_TYPE )== WIFI_QOS_DATA_TYPE) ++ { ++ if(GetFrameSubType(ptr)&(BIT(4)|BIT(5)|BIT(6))) ++ { ++ DBG_871X("drop QoS-Sybtype Data\n"); ++ ret= _FAIL; ++ goto exit; ++ } ++ } ++ // filter packets that SA is myself or multicast or broadcast ++ if (_rtw_memcmp(myhwaddr, pattrib->src, ETH_ALEN)){ ++ ret= _FAIL; ++ goto exit; ++ } ++ // da should be for me ++ if((!_rtw_memcmp(myhwaddr, pattrib->dst, ETH_ALEN))&& (!bmcast)) ++ { ++ ret= _FAIL; ++ goto exit; ++ } ++ // check BSSID ++ if( _rtw_memcmp(pattrib->bssid, "\x0\x0\x0\x0\x0\x0", ETH_ALEN) || ++ _rtw_memcmp(mybssid, "\x0\x0\x0\x0\x0\x0", ETH_ALEN) || ++ (!_rtw_memcmp(pattrib->bssid, mybssid, ETH_ALEN)) ) ++ { ++ ret= _FAIL; ++ goto exit; ++ } ++ ++ //process UAPSD tdls sta ++ process_pwrbit_data(adapter, precv_frame); ++ ++ // if NULL-frame, check pwrbit ++ if ((GetFrameSubType(ptr)) == WIFI_DATA_NULL) ++ { ++ //NULL-frame with pwrbit=1, buffer_STA should buffer frames for sleep_STA ++ if(GetPwrMgt(ptr)) ++ { ++ DBG_871X("TDLS: recv peer null frame with pwr bit 1\n"); ++ ptdls_sta->tdls_sta_state|=TDLS_PEER_SLEEP_STATE; ++ // it would be triggered when we are off channel and receiving NULL DATA ++ // we can confirm that peer STA is at off channel ++ } ++ else if(ptdls_sta->tdls_sta_state&TDLS_CH_SWITCH_ON_STATE) ++ { ++ if((ptdls_sta->tdls_sta_state & TDLS_PEER_AT_OFF_STATE) != TDLS_PEER_AT_OFF_STATE) ++ { ++ issue_nulldata_to_TDLS_peer_STA(adapter, ptdls_sta, 0); ++ ptdls_sta->tdls_sta_state |= TDLS_PEER_AT_OFF_STATE; ++ On_TDLS_Peer_Traffic_Rsp(adapter, precv_frame); ++ } ++ } ++ ++ ret= _FAIL; ++ goto exit; ++ } ++ //receive some of all TDLS management frames, process it at ON_TDLS ++ if((_rtw_memcmp(psnap_type, SNAP_ETH_TYPE_TDLS, 2))){ ++ ret= OnTDLS(adapter, precv_frame); ++ goto exit; ++ } ++ ++ } ++ ++ sta_addr = pattrib->src; ++ ++ } ++ else ++#endif ++ { ++ // For Station mode, sa and bssid should always be BSSID, and DA is my mac-address ++ if(!_rtw_memcmp(pattrib->bssid, pattrib->src, ETH_ALEN) ) ++ { ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("bssid != TA under STATION_MODE; drop pkt\n")); ++ ret= _FAIL; ++ goto exit; ++ } ++ ++ sta_addr = pattrib->bssid; ++ } ++ ++ } ++ else if(check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) ++ { ++ if (bmcast) ++ { ++ // For AP mode, if DA == MCAST, then BSSID should be also MCAST ++ if (!IS_MCAST(pattrib->bssid)){ ++ ret= _FAIL; ++ goto exit; ++ } ++ } ++ else // not mc-frame ++ { ++ // For AP mode, if DA is non-MCAST, then it must be BSSID, and bssid == BSSID ++ if(!_rtw_memcmp(pattrib->bssid, pattrib->dst, ETH_ALEN)) { ++ ret= _FAIL; ++ goto exit; ++ } ++ ++ sta_addr = pattrib->src; ++ } ++ ++ } ++ else if(check_fwstate(pmlmepriv, WIFI_MP_STATE) == _TRUE) ++ { ++ _rtw_memcpy(pattrib->dst, GetAddr1Ptr(ptr), ETH_ALEN); ++ _rtw_memcpy(pattrib->src, GetAddr2Ptr(ptr), ETH_ALEN); ++ _rtw_memcpy(pattrib->bssid, GetAddr3Ptr(ptr), ETH_ALEN); ++ _rtw_memcpy(pattrib->ra, pattrib->dst, ETH_ALEN); ++ _rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN); ++ ++ sta_addr = mybssid; ++ } ++ else ++ { ++ ret = _FAIL; ++ } ++ ++ ++ ++ if(bmcast) ++ *psta = rtw_get_bcmc_stainfo(adapter); ++ else ++ *psta = rtw_get_stainfo(pstapriv, sta_addr); // get ap_info ++ ++ if (*psta == NULL) { ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("can't get psta under sta2sta_data_frame ; drop pkt\n")); ++#ifdef CONFIG_MP_INCLUDED ++ if(check_fwstate(pmlmepriv, WIFI_MP_STATE) == _TRUE) ++ adapter->mppriv.rx_pktloss++; ++#endif ++ ret= _FAIL; ++ goto exit; ++ } ++ ++exit: ++_func_exit_; ++ return ret; ++ ++} ++ ++ ++static sint ap2sta_data_frame( ++ _adapter *adapter, ++ union recv_frame *precv_frame, ++ struct sta_info**psta ) ++{ ++ u8 *ptr = precv_frame->u.hdr.rx_data; ++ struct rx_pkt_attrib *pattrib = & precv_frame->u.hdr.attrib; ++ sint ret = _SUCCESS; ++ struct sta_priv *pstapriv = &adapter->stapriv; ++ struct security_priv *psecuritypriv = &adapter->securitypriv; ++ struct mlme_priv *pmlmepriv = &adapter->mlmepriv; ++ u8 *mybssid = get_bssid(pmlmepriv); ++ u8 *myhwaddr = myid(&adapter->eeprompriv); ++ sint bmcast = IS_MCAST(pattrib->dst); ++ ++_func_enter_; ++ ++ if ((check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE) ++ && (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE ++ || check_fwstate(pmlmepriv, _FW_UNDER_LINKING) == _TRUE ) ++ ) ++ { ++ ++ // if NULL-frame, drop packet ++ if ((GetFrameSubType(ptr)) == WIFI_DATA_NULL) ++ { ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,(" NULL frame \n")); ++ #ifdef DBG_RX_DROP_FRAME ++ DBG_871X("DBG_RX_DROP_FRAME %s NULL frame\n", __FUNCTION__); ++ #endif ++ ret= _FAIL; ++ goto exit; ++ } ++ ++ //drop QoS-SubType Data, including QoS NULL, excluding QoS-Data ++ if( (GetFrameSubType(ptr) & WIFI_QOS_DATA_TYPE )== WIFI_QOS_DATA_TYPE) ++ { ++ if(GetFrameSubType(ptr)&(BIT(4)|BIT(5)|BIT(6))) ++ { ++ #ifdef DBG_RX_DROP_FRAME ++ DBG_871X("DBG_RX_DROP_FRAME %s drop QoS-SubType Data, including QoS NULL, excluding QoS-Data\n", __FUNCTION__); ++ #endif ++ ret= _FAIL; ++ goto exit; ++ } ++ ++ } ++ ++ // filter packets that SA is myself or multicast or broadcast ++ if (_rtw_memcmp(myhwaddr, pattrib->src, ETH_ALEN)){ ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,(" SA==myself \n")); ++ #ifdef DBG_RX_DROP_FRAME ++ DBG_871X("DBG_RX_DROP_FRAME %s SA=%x:%x:%x:%x:%x:%x, myhwaddr= %x:%x:%x:%x:%x:%x\n", __FUNCTION__, ++ pattrib->src[0], pattrib->src[1], pattrib->src[2], ++ pattrib->src[3], pattrib->src[4], pattrib->src[5], ++ *(myhwaddr), *(myhwaddr+1), *(myhwaddr+2), ++ *(myhwaddr+3), *(myhwaddr+4), *(myhwaddr+5)); ++ #endif ++ ret= _FAIL; ++ goto exit; ++ } ++ ++ // da should be for me ++ if((!_rtw_memcmp(myhwaddr, pattrib->dst, ETH_ALEN))&& (!bmcast)) ++ { ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,(" ap2sta_data_frame: compare DA fail; DA= %x:%x:%x:%x:%x:%x \n", ++ pattrib->dst[0], ++ pattrib->dst[1], ++ pattrib->dst[2], ++ pattrib->dst[3], ++ pattrib->dst[4], ++ pattrib->dst[5])); ++ #ifdef DBG_RX_DROP_FRAME ++ DBG_871X("DBG_RX_DROP_FRAME %s compare DA fail; DA= %x:%x:%x:%x:%x:%x \n", __FUNCTION__, ++ pattrib->dst[0],pattrib->dst[1],pattrib->dst[2], ++ pattrib->dst[3],pattrib->dst[4],pattrib->dst[5]); ++ #endif ++ ++ ret= _FAIL; ++ goto exit; ++ } ++ ++ ++ // check BSSID ++ if( _rtw_memcmp(pattrib->bssid, "\x0\x0\x0\x0\x0\x0", ETH_ALEN) || ++ _rtw_memcmp(mybssid, "\x0\x0\x0\x0\x0\x0", ETH_ALEN) || ++ (!_rtw_memcmp(pattrib->bssid, mybssid, ETH_ALEN)) ) ++ { ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,(" ap2sta_data_frame: compare BSSID fail ; BSSID=%x:%x:%x:%x:%x:%x\n", ++ pattrib->bssid[0], ++ pattrib->bssid[1], ++ pattrib->bssid[2], ++ pattrib->bssid[3], ++ pattrib->bssid[4], ++ pattrib->bssid[5])); ++ ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("mybssid= %x:%x:%x:%x:%x:%x\n", ++ mybssid[0], ++ mybssid[1], ++ mybssid[2], ++ mybssid[3], ++ mybssid[4], ++ mybssid[5])); ++ ++ #ifdef DBG_RX_DROP_FRAME ++ DBG_871X("DBG_RX_DROP_FRAME %s compare BSSID fail ; BSSID=%x:%x:%x:%x:%x:%x, mybssid= %x:%x:%x:%x:%x:%x\n", __FUNCTION__, ++ pattrib->bssid[0], pattrib->bssid[1], pattrib->bssid[2], ++ pattrib->bssid[3], pattrib->bssid[4], pattrib->bssid[5], ++ mybssid[0], mybssid[1], mybssid[2], ++ mybssid[3], mybssid[4], mybssid[5]); ++ #endif ++ ++ ret= _FAIL; ++ goto exit; ++ } ++ ++ if(bmcast) ++ *psta = rtw_get_bcmc_stainfo(adapter); ++ else ++ *psta = rtw_get_stainfo(pstapriv, pattrib->bssid); // get ap_info ++ ++ if (*psta == NULL) { ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("ap2sta: can't get psta under STATION_MODE ; drop pkt\n")); ++ #ifdef DBG_RX_DROP_FRAME ++ DBG_871X("DBG_RX_DROP_FRAME %s can't get psta under STATION_MODE ; drop pkt\n", __FUNCTION__); ++ #endif ++ ret= _FAIL; ++ goto exit; ++ } ++ ++ } ++ else if ((check_fwstate(pmlmepriv, WIFI_MP_STATE) == _TRUE) && ++ (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) ) ++ { ++ _rtw_memcpy(pattrib->dst, GetAddr1Ptr(ptr), ETH_ALEN); ++ _rtw_memcpy(pattrib->src, GetAddr2Ptr(ptr), ETH_ALEN); ++ _rtw_memcpy(pattrib->bssid, GetAddr3Ptr(ptr), ETH_ALEN); ++ _rtw_memcpy(pattrib->ra, pattrib->dst, ETH_ALEN); ++ _rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN); ++ ++ // ++ _rtw_memcpy(pattrib->bssid, mybssid, ETH_ALEN); ++ ++ ++ *psta = rtw_get_stainfo(pstapriv, pattrib->bssid); // get sta_info ++ if (*psta == NULL) { ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("can't get psta under MP_MODE ; drop pkt\n")); ++ #ifdef DBG_RX_DROP_FRAME ++ DBG_871X("DBG_RX_DROP_FRAME %s can't get psta under WIFI_MP_STATE ; drop pkt\n", __FUNCTION__); ++ #endif ++ ret= _FAIL; ++ goto exit; ++ } ++ ++ ++ } ++ else ++ { ++ ret = _FAIL; ++ #ifdef DBG_RX_DROP_FRAME ++ DBG_871X("DBG_RX_DROP_FRAME %s fw_state:0x%x\n", __FUNCTION__, get_fwstate(pmlmepriv)); ++ #endif ++ } ++ ++exit: ++ ++_func_exit_; ++ ++ return ret; ++ ++} ++ ++static sint sta2ap_data_frame( ++ _adapter *adapter, ++ union recv_frame *precv_frame, ++ struct sta_info**psta ) ++{ ++ u8 *ptr = precv_frame->u.hdr.rx_data; ++ struct rx_pkt_attrib *pattrib = & precv_frame->u.hdr.attrib; ++ struct sta_priv *pstapriv = &adapter->stapriv; ++ struct security_priv *psecuritypriv = &adapter->securitypriv; ++ struct mlme_priv *pmlmepriv = &adapter->mlmepriv; ++ unsigned char *mybssid = get_bssid(pmlmepriv); ++ sint ret=_SUCCESS; ++ ++_func_enter_; ++ ++ if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) ++ { ++ //For AP mode, RA=BSSID, TX=STA(SRC_ADDR), A3=DST_ADDR ++ if(!_rtw_memcmp(pattrib->bssid, mybssid, ETH_ALEN)) ++ { ++ ret= _FAIL; ++ goto exit; ++ } ++ ++ *psta = rtw_get_stainfo(pstapriv, pattrib->src); ++ ++ if (*psta == NULL) ++ { ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("can't get psta under AP_MODE; drop pkt\n")); ++ ret= _FAIL; ++ goto exit; ++ } ++ ++ ++ process_pwrbit_data(adapter, precv_frame); ++ ++ ++ // if NULL-frame, drop packet ++ if ((GetFrameSubType(ptr)) == WIFI_DATA_NULL) ++ { ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,(" NULL frame \n")); ++ ++ //temporily count it here ++ count_rx_stats(adapter, precv_frame, *psta); ++ ++ //process_null_data(adapter, precv_frame); ++ //process_pwrbit_data(adapter, precv_frame); ++ ++ ++ ret= _FAIL; ++ goto exit; ++ } ++ ++ //drop QoS-SubType Data, including QoS NULL, excluding QoS-Data ++ if( (GetFrameSubType(ptr) & WIFI_QOS_DATA_TYPE )== WIFI_QOS_DATA_TYPE) ++ { ++ ++ if(GetFrameSubType(ptr)==WIFI_QOS_DATA_NULL) ++ { ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,(" QoS NULL frame \n")); ++ ++ //temporily count it here ++ count_rx_stats(adapter, precv_frame, *psta); ++ ++ //process_null_data(adapter, precv_frame); ++ ++ ret= _FAIL; ++ goto exit; ++ } ++ ++ process_wmmps_data(adapter, precv_frame); ++ ++ /* ++ if(GetFrameSubType(ptr)&(BIT(4)|BIT(5)|BIT(6))) ++ { ++ process_null_data(adapter, precv_frame); ++ ret= _FAIL; ++ goto exit; ++ } ++ */ ++ } ++ ++ } ++ ++exit: ++ ++_func_exit_; ++ ++ return ret; ++ ++} ++ ++static sint validate_recv_ctrl_frame(_adapter *padapter, union recv_frame *precv_frame) ++{ ++#ifdef CONFIG_AP_MODE ++ struct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib; ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ u8 *pframe = precv_frame->u.hdr.rx_data; ++ //uint len = precv_frame->u.hdr.len; ++ ++ //DBG_871X("+validate_recv_ctrl_frame\n"); ++ ++ if (GetFrameType(pframe) != WIFI_CTRL_TYPE) ++ { ++ return _FAIL; ++ } ++ ++ //receive the frames that ra(a1) is my address ++ if (!_rtw_memcmp(GetAddr1Ptr(pframe), myid(&padapter->eeprompriv), ETH_ALEN)) ++ { ++ return _FAIL; ++ } ++ ++ //only handle ps-poll ++ if(GetFrameSubType(pframe) == WIFI_PSPOLL) ++ { ++ u16 aid; ++ u8 wmmps_ac=0; ++ struct sta_info *psta=NULL; ++ ++ aid = GetAid(pframe); ++ psta = rtw_get_stainfo(pstapriv, GetAddr2Ptr(pframe)); ++ ++ if((psta==NULL) || (psta->aid!=aid)) ++ { ++ return _FAIL; ++ } ++ ++ //for rx pkt statistics ++ psta->sta_stats.rx_ctrl_pkts++; ++ ++ switch(pattrib->priority) ++ { ++ case 1: ++ case 2: ++ wmmps_ac = psta->uapsd_bk&BIT(0); ++ break; ++ case 4: ++ case 5: ++ wmmps_ac = psta->uapsd_vi&BIT(0); ++ break; ++ case 6: ++ case 7: ++ wmmps_ac = psta->uapsd_vo&BIT(0); ++ break; ++ case 0: ++ case 3: ++ default: ++ wmmps_ac = psta->uapsd_be&BIT(0); ++ break; ++ } ++ ++ if(wmmps_ac) ++ return _FAIL; ++ ++ if((psta->state&WIFI_SLEEP_STATE) && (pstapriv->sta_dz_bitmap&BIT(psta->aid))) ++ { ++ _irqL irqL; ++ _list *xmitframe_plist, *xmitframe_phead; ++ struct xmit_frame *pxmitframe=NULL; ++ ++ _enter_critical_bh(&psta->sleep_q.lock, &irqL); ++ ++ xmitframe_phead = get_list_head(&psta->sleep_q); ++ xmitframe_plist = get_next(xmitframe_phead); ++ ++ if ((rtw_end_of_queue_search(xmitframe_phead, xmitframe_plist)) == _FALSE) ++ { ++ pxmitframe = LIST_CONTAINOR(xmitframe_plist, struct xmit_frame, list); ++ ++ xmitframe_plist = get_next(xmitframe_plist); ++ ++ rtw_list_delete(&pxmitframe->list); ++ ++ psta->sleepq_len--; ++ ++ if(psta->sleepq_len>0) ++ pxmitframe->attrib.mdata = 1; ++ else ++ pxmitframe->attrib.mdata = 0; ++ ++ pxmitframe->attrib.triggered = 1; ++ ++ //DBG_871X("handling ps-poll, q_len=%d, tim=%x\n", psta->sleepq_len, pstapriv->tim_bitmap); ++ ++ if(padapter->HalFunc.hal_xmit(padapter, pxmitframe) == _TRUE) ++ { ++ rtw_os_xmit_complete(padapter, pxmitframe); ++ } ++ ++ if(psta->sleepq_len==0) ++ { ++ pstapriv->tim_bitmap &= ~BIT(psta->aid); ++ ++ //DBG_871X("after handling ps-poll, tim=%x\n", pstapriv->tim_bitmap); ++ ++ //upate BCN for TIM IE ++ //update_BCNTIM(padapter); ++ update_beacon(padapter, _TIM_IE_, NULL, _FALSE); ++ } ++ ++ } ++ else ++ { ++ //DBG_871X("no buffered packets to xmit\n"); ++ if(pstapriv->tim_bitmap&BIT(psta->aid)) ++ { ++ if(psta->sleepq_len==0) ++ { ++ DBG_871X("no buffered packets to xmit\n"); ++ } ++ else ++ { ++ DBG_871X("error!psta->sleepq_len=%d\n", psta->sleepq_len); ++ psta->sleepq_len=0; ++ } ++ ++ pstapriv->tim_bitmap &= ~BIT(psta->aid); ++ ++ //upate BCN for TIM IE ++ //update_BCNTIM(padapter); ++ update_beacon(padapter, _TIM_IE_, NULL, _FALSE); ++ } ++ ++ } ++ ++ _exit_critical_bh(&psta->sleep_q.lock, &irqL); ++ ++ } ++ ++ } ++ ++#endif ++ ++ return _FAIL; ++ ++} ++ ++static sint validate_recv_mgnt_frame(_adapter *adapter, union recv_frame *precv_frame) ++{ ++ struct mlme_priv *pmlmepriv = &adapter->mlmepriv; ++ ++ RT_TRACE(_module_rtl871x_recv_c_, _drv_info_, ("+validate_recv_mgnt_frame\n")); ++ ++#if 0 ++ if(check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) ++ { ++#ifdef CONFIG_NATIVEAP_MLME ++ mgt_dispatcher(adapter, precv_frame); ++#else ++ rtw_hostapd_mlme_rx(adapter, precv_frame); ++#endif ++ } ++ else ++ { ++ mgt_dispatcher(adapter, precv_frame); ++ } ++#endif ++ ++ { ++ //for rx pkt statistics ++ struct sta_info *psta = rtw_get_stainfo(&adapter->stapriv, GetAddr2Ptr(precv_frame->u.hdr.rx_data)); ++ if(psta) ++ psta->sta_stats.rx_mgnt_pkts++; ++ } ++ ++ ++#ifdef CONFIG_INTEL_PROXIM ++ if(adapter->proximity.proxim_on==_TRUE) ++ { ++ struct rx_pkt_attrib * pattrib=&precv_frame->u.hdr.attrib; ++ struct recv_stat* prxstat=( struct recv_stat * ) precv_frame->u.hdr.rx_head ; ++ u8 * pda,*psa,*pbssid,*ptr; ++ ptr=precv_frame->u.hdr.rx_data; ++ pda = get_da(ptr); ++ psa = get_sa(ptr); ++ pbssid = get_hdr_bssid(ptr); ++ ++ ++ _rtw_memcpy(pattrib->dst, pda, ETH_ALEN); ++ _rtw_memcpy(pattrib->src, psa, ETH_ALEN); ++ ++ _rtw_memcpy(pattrib->bssid, pbssid, ETH_ALEN); ++ ++ switch(pattrib->to_fr_ds) ++ { ++ case 0: ++ _rtw_memcpy(pattrib->ra, pda, ETH_ALEN); ++ _rtw_memcpy(pattrib->ta, psa, ETH_ALEN); ++ break; ++ ++ case 1: ++ _rtw_memcpy(pattrib->ra, pda, ETH_ALEN); ++ _rtw_memcpy(pattrib->ta, pbssid, ETH_ALEN); ++ break; ++ ++ case 2: ++ _rtw_memcpy(pattrib->ra, pbssid, ETH_ALEN); ++ _rtw_memcpy(pattrib->ta, psa, ETH_ALEN); ++ break; ++ ++ case 3: ++ _rtw_memcpy(pattrib->ra, GetAddr1Ptr(ptr), ETH_ALEN); ++ _rtw_memcpy(pattrib->ta, GetAddr2Ptr(ptr), ETH_ALEN); ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,(" case 3\n")); ++ break; ++ ++ default: ++ break; ++ ++ } ++ pattrib->priority=0; ++ pattrib->hdrlen = pattrib->to_fr_ds==3 ? 30 : 24; ++ ++ adapter->proximity.proxim_rx(adapter,precv_frame); ++ } ++#endif ++ mgt_dispatcher(adapter, precv_frame); ++ ++ ++ return _SUCCESS; ++ ++} ++ ++ ++static sint validate_recv_data_frame(_adapter *adapter, union recv_frame *precv_frame) ++{ ++ int res; ++ u8 bretry; ++ u8 *psa, *pda, *pbssid; ++ struct sta_info *psta = NULL; ++ u8 *ptr = precv_frame->u.hdr.rx_data; ++ struct rx_pkt_attrib *pattrib = & precv_frame->u.hdr.attrib; ++ struct sta_priv *pstapriv = &adapter->stapriv; ++ struct security_priv *psecuritypriv = &adapter->securitypriv; ++ sint ret = _SUCCESS; ++#ifdef CONFIG_TDLS ++ struct tdls_info *ptdlsinfo = &adapter->tdlsinfo; ++ struct sta_info *ptdls_sta = NULL; ++#endif ++ ++_func_enter_; ++ ++ bretry = GetRetry(ptr); ++ pda = get_da(ptr); ++ psa = get_sa(ptr); ++ pbssid = get_hdr_bssid(ptr); ++ ++ if(pbssid == NULL){ ++ ret= _FAIL; ++ goto exit; ++ } ++ ++ _rtw_memcpy(pattrib->dst, pda, ETH_ALEN); ++ _rtw_memcpy(pattrib->src, psa, ETH_ALEN); ++ ++ _rtw_memcpy(pattrib->bssid, pbssid, ETH_ALEN); ++ ++ switch(pattrib->to_fr_ds) ++ { ++ case 0: ++ _rtw_memcpy(pattrib->ra, pda, ETH_ALEN); ++ _rtw_memcpy(pattrib->ta, psa, ETH_ALEN); ++ res= sta2sta_data_frame(adapter, precv_frame, &psta); ++ break; ++ ++ case 1: ++ _rtw_memcpy(pattrib->ra, pda, ETH_ALEN); ++ _rtw_memcpy(pattrib->ta, pbssid, ETH_ALEN); ++ res= ap2sta_data_frame(adapter, precv_frame, &psta); ++ break; ++ ++ case 2: ++ _rtw_memcpy(pattrib->ra, pbssid, ETH_ALEN); ++ _rtw_memcpy(pattrib->ta, psa, ETH_ALEN); ++ res= sta2ap_data_frame(adapter, precv_frame, &psta); ++ break; ++ ++ case 3: ++ _rtw_memcpy(pattrib->ra, GetAddr1Ptr(ptr), ETH_ALEN); ++ _rtw_memcpy(pattrib->ta, GetAddr2Ptr(ptr), ETH_ALEN); ++ res=_FAIL; ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,(" case 3\n")); ++ break; ++ ++ default: ++ res=_FAIL; ++ break; ++ ++ } ++ ++ if(res==_FAIL){ ++ //RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,(" after to_fr_ds_chk; res = fail \n")); ++ #ifdef DBG_RX_DROP_FRAME ++ DBG_871X("DBG_RX_DROP_FRAME %s case:%d, res:%d\n", __FUNCTION__, pattrib->to_fr_ds, res); ++ #endif ++ ret= res; ++ goto exit; ++ } ++ ++ ++ if(psta==NULL){ ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,(" after to_fr_ds_chk; psta==NULL \n")); ++ ret= _FAIL; ++ goto exit; ++ } ++ ++ //psta->rssi = prxcmd->rssi; ++ //psta->signal_quality= prxcmd->sq; ++ precv_frame->u.hdr.psta = psta; ++ ++ ++ pattrib->amsdu=0; ++ //parsing QC field ++ if(pattrib->qos == 1) ++ { ++ pattrib->priority = GetPriority((ptr + 24)); ++ pattrib->ack_policy =GetAckpolicy((ptr + 24)); ++ pattrib->amsdu = GetAMsdu((ptr + 24)); ++ pattrib->hdrlen = pattrib->to_fr_ds==3 ? 32 : 26; ++ ++ if(pattrib->priority!=0 && pattrib->priority!=3) ++ { ++ adapter->recvpriv.bIsAnyNonBEPkts = _TRUE; ++ } ++ } ++ else ++ { ++ pattrib->priority=0; ++ pattrib->hdrlen = pattrib->to_fr_ds==3 ? 30 : 24; ++ } ++ ++ ++ if(pattrib->order)//HT-CTRL 11n ++ { ++ pattrib->hdrlen += 4; ++ } ++ ++ precv_frame->u.hdr.preorder_ctrl = &psta->recvreorder_ctrl[pattrib->priority]; ++ ++ // decache, drop duplicate recv packets ++ if(recv_decache(precv_frame, bretry, &psta->sta_recvpriv.rxcache) == _FAIL) ++ { ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("decache : drop pkt\n")); ++ ret= _FAIL; ++ goto exit; ++ } ++#ifdef CONFIG_TDLS ++ if(psta->tdls_sta_state & TDLS_LINKED_STATE ) ++ { ++ if(psta->dot118021XPrivacy==_AES_) ++ pattrib->encrypt=psta->dot118021XPrivacy; ++ } ++#endif //CONFIG_TDLS ++ ++ if(pattrib->privacy){ ++ ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("validate_recv_data_frame:pattrib->privacy=%x\n", pattrib->privacy)); ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("\n ^^^^^^^^^^^IS_MCAST(pattrib->ra(0x%02x))=%d^^^^^^^^^^^^^^^6\n", pattrib->ra[0],IS_MCAST(pattrib->ra))); ++ ++#ifdef CONFIG_TDLS ++ if(ptdls_sta==NULL) ++#endif ++ GET_ENCRY_ALGO(psecuritypriv, psta, pattrib->encrypt, IS_MCAST(pattrib->ra)); ++ ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("\n pattrib->encrypt=%d\n",pattrib->encrypt)); ++ ++ SET_ICE_IV_LEN(pattrib->iv_len, pattrib->icv_len, pattrib->encrypt); ++ } ++ else ++ { ++ pattrib->encrypt = 0; ++ pattrib->iv_len = pattrib->icv_len = 0; ++ } ++ ++exit: ++ ++_func_exit_; ++ ++ return ret; ++} ++ ++static sint validate_recv_frame(_adapter *adapter, union recv_frame *precv_frame) ++{ ++ //shall check frame subtype, to / from ds, da, bssid ++ ++ //then call check if rx seq/frag. duplicated. ++ ++ u8 type; ++ u8 subtype; ++ sint retval = _SUCCESS; ++ ++ struct rx_pkt_attrib *pattrib = & precv_frame->u.hdr.attrib; ++ ++ u8 *ptr = precv_frame->u.hdr.rx_data; ++ u8 ver =(unsigned char) (*ptr)&0x3 ; ++#ifdef CONFIG_FIND_BEST_CHANNEL ++ struct mlme_ext_priv *pmlmeext = &adapter->mlmeextpriv; ++#endif ++ ++#ifdef CONFIG_TDLS ++ struct tdls_info *ptdlsinfo = &adapter->tdlsinfo; ++#endif //CONFIG_TDLS ++ ++_func_enter_; ++ ++ ++#ifdef CONFIG_FIND_BEST_CHANNEL ++ if (pmlmeext->sitesurvey_res.state == SCAN_PROCESS) { ++ pmlmeext->channel_set[pmlmeext->sitesurvey_res.channel_idx].rx_count++; ++ } ++#endif ++ ++#ifdef CONFIG_TDLS ++ if(ptdlsinfo->ch_sensing==1 && ptdlsinfo->cur_channel !=0){ ++ ptdlsinfo->collect_pkt_num[ptdlsinfo->cur_channel-1]++; ++ } ++#endif ++ ++#if 0 ++DBG_871X("\n"); ++{ ++ int i; ++ for(i=0; i<64;i=i+8) ++ DBG_871X("%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X:", *(ptr+i), ++ *(ptr+i+1), *(ptr+i+2) ,*(ptr+i+3) ,*(ptr+i+4),*(ptr+i+5), *(ptr+i+6), *(ptr+i+7)); ++ ++} ++DBG_871X("\n"); ++#endif ++ ++ //add version chk ++ if(ver!=0){ ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("validate_recv_data_frame fail! (ver!=0)\n")); ++ retval= _FAIL; ++ goto exit; ++ } ++ ++ type = GetFrameType(ptr); ++ subtype = GetFrameSubType(ptr); //bit(7)~bit(2) ++ ++ pattrib->to_fr_ds = get_tofr_ds(ptr); ++ ++ pattrib->frag_num = GetFragNum(ptr); ++ pattrib->seq_num = GetSequence(ptr); ++ ++ pattrib->pw_save = GetPwrMgt(ptr); ++ pattrib->mfrag = GetMFrag(ptr); ++ pattrib->mdata = GetMData(ptr); ++ pattrib->privacy = GetPrivacy(ptr); ++ pattrib->order = GetOrder(ptr); ++#if 0 //for debug ++ ++if(pHalData->bDumpRxPkt ==1){ ++ int i; ++ DBG_871X("############################# \n"); ++ ++ for(i=0; i<64;i=i+8) ++ DBG_871X("%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X:\n", *(ptr+i), ++ *(ptr+i+1), *(ptr+i+2) ,*(ptr+i+3) ,*(ptr+i+4),*(ptr+i+5), *(ptr+i+6), *(ptr+i+7)); ++ DBG_871X("############################# \n"); ++} ++else if(pHalData->bDumpRxPkt ==2){ ++ if(type== WIFI_MGT_TYPE){ ++ int i; ++ DBG_871X("############################# \n"); ++ ++ for(i=0; i<64;i=i+8) ++ DBG_871X("%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X:\n", *(ptr+i), ++ *(ptr+i+1), *(ptr+i+2) ,*(ptr+i+3) ,*(ptr+i+4),*(ptr+i+5), *(ptr+i+6), *(ptr+i+7)); ++ DBG_871X("############################# \n"); ++ } ++} ++else if(pHalData->bDumpRxPkt ==3){ ++ if(type== WIFI_DATA_TYPE){ ++ int i; ++ DBG_871X("############################# \n"); ++ ++ for(i=0; i<64;i=i+8) ++ DBG_871X("%02X:%02X:%02X:%02X:%02X:%02X:%02X:%02X:\n", *(ptr+i), ++ *(ptr+i+1), *(ptr+i+2) ,*(ptr+i+3) ,*(ptr+i+4),*(ptr+i+5), *(ptr+i+6), *(ptr+i+7)); ++ DBG_871X("############################# \n"); ++ } ++} ++ ++#endif ++ switch (type) ++ { ++ case WIFI_MGT_TYPE: //mgnt ++ retval = validate_recv_mgnt_frame(adapter, precv_frame); ++ if (retval == _FAIL) ++ { ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("validate_recv_mgnt_frame fail\n")); ++ } ++ retval = _FAIL; // only data frame return _SUCCESS ++ break; ++ case WIFI_CTRL_TYPE: //ctrl ++ retval = validate_recv_ctrl_frame(adapter, precv_frame); ++ if (retval == _FAIL) ++ { ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("validate_recv_ctrl_frame fail\n")); ++ } ++ retval = _FAIL; // only data frame return _SUCCESS ++ break; ++ case WIFI_DATA_TYPE: //data ++ rtw_led_control(adapter, LED_CTL_RX); ++ pattrib->qos = (subtype & BIT(7))? 1:0; ++ retval = validate_recv_data_frame(adapter, precv_frame); ++ if (retval == _FAIL) ++ { ++ struct recv_priv *precvpriv = &adapter->recvpriv; ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("validate_recv_data_frame fail\n")); ++ precvpriv->rx_drop++; ++ } ++ break; ++ default: ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("validate_recv_data_frame fail! type=0x%x\n", type)); ++ #ifdef DBG_RX_DROP_FRAME ++ DBG_871X("DBG_RX_DROP_FRAME validate_recv_data_frame fail! type=0x%x\n", type); ++ #endif ++ retval = _FAIL; ++ break; ++ } ++ ++exit: ++ ++_func_exit_; ++ ++ return retval; ++} ++ ++ ++//remove the wlanhdr and add the eth_hdr ++#if 1 ++static sint wlanhdr_to_ethhdr ( union recv_frame *precvframe) ++{ ++ sint rmv_len; ++ u16 eth_type, len; ++ u8 bsnaphdr; ++ u8 *psnap_type; ++ struct ieee80211_snap_hdr *psnap; ++ ++ sint ret=_SUCCESS; ++ _adapter *adapter =precvframe->u.hdr.adapter; ++ struct mlme_priv *pmlmepriv = &adapter->mlmepriv; ++ ++ u8 *ptr = get_recvframe_data(precvframe) ; // point to frame_ctrl field ++ struct rx_pkt_attrib *pattrib = & precvframe->u.hdr.attrib; ++ ++_func_enter_; ++ ++ if(pattrib->encrypt){ ++ recvframe_pull_tail(precvframe, pattrib->icv_len); ++ } ++ ++ psnap=(struct ieee80211_snap_hdr *)(ptr+pattrib->hdrlen + pattrib->iv_len); ++ psnap_type=ptr+pattrib->hdrlen + pattrib->iv_len+SNAP_SIZE; ++ /* convert hdr + possible LLC headers into Ethernet header */ ++ //eth_type = (psnap_type[0] << 8) | psnap_type[1]; ++ if((_rtw_memcmp(psnap, rtw_rfc1042_header, SNAP_SIZE) && ++ (_rtw_memcmp(psnap_type, SNAP_ETH_TYPE_IPX, 2) == _FALSE) && ++ (_rtw_memcmp(psnap_type, SNAP_ETH_TYPE_APPLETALK_AARP, 2)==_FALSE) )|| ++ //eth_type != ETH_P_AARP && eth_type != ETH_P_IPX) || ++ _rtw_memcmp(psnap, rtw_bridge_tunnel_header, SNAP_SIZE)){ ++ /* remove RFC1042 or Bridge-Tunnel encapsulation and replace EtherType */ ++ bsnaphdr = _TRUE; ++ } ++ else { ++ /* Leave Ethernet header part of hdr and full payload */ ++ bsnaphdr = _FALSE; ++ } ++ ++ rmv_len = pattrib->hdrlen + pattrib->iv_len +(bsnaphdr?SNAP_SIZE:0); ++ len = precvframe->u.hdr.len - rmv_len; ++ ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("\n===pattrib->hdrlen: %x, pattrib->iv_len:%x ===\n\n", pattrib->hdrlen, pattrib->iv_len)); ++ ++ if ((check_fwstate(pmlmepriv, WIFI_MP_STATE) == _TRUE)) ++ { ++ ptr += rmv_len ; ++ *ptr = 0x87; ++ *(ptr+1) = 0x12; ++ ++ eth_type = 0x8712; ++ // append rx status for mp test packets ++ ptr = recvframe_pull(precvframe, (rmv_len-sizeof(struct ethhdr)+2)-24); ++ _rtw_memcpy(ptr, get_rxmem(precvframe), 24); ++ ptr+=24; ++ } ++ else { ++ ptr = recvframe_pull(precvframe, (rmv_len-sizeof(struct ethhdr)+ (bsnaphdr?2:0))); ++ } ++ ++ _rtw_memcpy(ptr, pattrib->dst, ETH_ALEN); ++ _rtw_memcpy(ptr+ETH_ALEN, pattrib->src, ETH_ALEN); ++ ++ if(!bsnaphdr) { ++ len = htons(len); ++ _rtw_memcpy(ptr+12, &len, 2); ++ } ++ ++_func_exit_; ++ return ret; ++ ++} ++ ++#else ++ ++sint wlanhdr_to_ethhdr ( union recv_frame *precvframe) ++{ ++ sint rmv_len; ++ u16 eth_type; ++ u8 bsnaphdr; ++ u8 *psnap_type; ++ struct ieee80211_snap_hdr *psnap; ++ ++ sint ret=_SUCCESS; ++ _adapter *adapter =precvframe->u.hdr.adapter; ++ struct mlme_priv *pmlmepriv = &adapter->mlmepriv; ++ ++ u8* ptr = get_recvframe_data(precvframe) ; // point to frame_ctrl field ++ struct rx_pkt_attrib *pattrib = & precvframe->u.hdr.attrib; ++ struct _vlan *pvlan = NULL; ++ ++_func_enter_; ++ ++ psnap=(struct ieee80211_snap_hdr *)(ptr+pattrib->hdrlen + pattrib->iv_len); ++ psnap_type=ptr+pattrib->hdrlen + pattrib->iv_len+SNAP_SIZE; ++ if (psnap->dsap==0xaa && psnap->ssap==0xaa && psnap->ctrl==0x03) ++ { ++ if (_rtw_memcmp(psnap->oui, oui_rfc1042, WLAN_IEEE_OUI_LEN)) ++ bsnaphdr=_TRUE;//wlan_pkt_format = WLAN_PKT_FORMAT_SNAP_RFC1042; ++ else if (_rtw_memcmp(psnap->oui, SNAP_HDR_APPLETALK_DDP, WLAN_IEEE_OUI_LEN) && ++ _rtw_memcmp(psnap_type, SNAP_ETH_TYPE_APPLETALK_DDP, 2) ) ++ bsnaphdr=_TRUE; //wlan_pkt_format = WLAN_PKT_FORMAT_APPLETALK; ++ else if (_rtw_memcmp( psnap->oui, oui_8021h, WLAN_IEEE_OUI_LEN)) ++ bsnaphdr=_TRUE; //wlan_pkt_format = WLAN_PKT_FORMAT_SNAP_TUNNEL; ++ else { ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("drop pkt due to invalid frame format!\n")); ++ ret= _FAIL; ++ goto exit; ++ } ++ ++ } else ++ bsnaphdr=_FALSE;//wlan_pkt_format = WLAN_PKT_FORMAT_OTHERS; ++ ++ rmv_len = pattrib->hdrlen + pattrib->iv_len +(bsnaphdr?SNAP_SIZE:0); ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("===pattrib->hdrlen: %x, pattrib->iv_len:%x ===\n", pattrib->hdrlen, pattrib->iv_len)); ++ ++ if (check_fwstate(pmlmepriv, WIFI_MP_STATE) == _TRUE) ++ { ++ ptr += rmv_len ; ++ *ptr = 0x87; ++ *(ptr+1) = 0x12; ++ ++ //back to original pointer ++ ptr -= rmv_len; ++ } ++ ++ ptr += rmv_len ; ++ ++ _rtw_memcpy(ð_type, ptr, 2); ++ eth_type= ntohs((unsigned short )eth_type); //pattrib->ether_type ++ ptr +=2; ++ ++ if(pattrib->encrypt){ ++ recvframe_pull_tail(precvframe, pattrib->icv_len); ++ } ++ ++ if(eth_type == 0x8100) //vlan ++ { ++ pvlan = (struct _vlan *) ptr; ++ ++ //eth_type = get_vlan_encap_proto(pvlan); ++ //eth_type = pvlan->h_vlan_encapsulated_proto;//? ++ rmv_len += 4; ++ ptr+=4; ++ } ++ ++ if(eth_type==0x0800)//ip ++ { ++ //struct iphdr* piphdr = (struct iphdr*) ptr; ++ //__u8 tos = (unsigned char)(pattrib->priority & 0xff); ++ ++ //piphdr->tos = tos; ++ ++ //if (piphdr->protocol == 0x06) ++ //{ ++ // RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("@@@===recv tcp len:%d @@@===\n", precvframe->u.hdr.len)); ++ //} ++ } ++ else if(eth_type==0x8712)// append rx status for mp test packets ++ { ++ //ptr -= 16; ++ //_rtw_memcpy(ptr, get_rxmem(precvframe), 16); ++ } ++ else ++ { ++#ifdef PLATFORM_OS_XP ++ NDIS_PACKET_8021Q_INFO VlanPriInfo; ++ UINT32 UserPriority = precvframe->u.hdr.attrib.priority; ++ UINT32 VlanID = (pvlan!=NULL ? get_vlan_id(pvlan) : 0 ); ++ ++ VlanPriInfo.Value = // Get current value. ++ NDIS_PER_PACKET_INFO_FROM_PACKET(precvframe->u.hdr.pkt, Ieee8021QInfo); ++ ++ VlanPriInfo.TagHeader.UserPriority = UserPriority; ++ VlanPriInfo.TagHeader.VlanId = VlanID ; ++ ++ VlanPriInfo.TagHeader.CanonicalFormatId = 0; // Should be zero. ++ VlanPriInfo.TagHeader.Reserved = 0; // Should be zero. ++ NDIS_PER_PACKET_INFO_FROM_PACKET(precvframe->u.hdr.pkt, Ieee8021QInfo) = VlanPriInfo.Value; ++#endif ++ } ++ ++ if(eth_type==0x8712)// append rx status for mp test packets ++ { ++ ptr = recvframe_pull(precvframe, (rmv_len-sizeof(struct ethhdr)+2)-24); ++ _rtw_memcpy(ptr, get_rxmem(precvframe), 24); ++ ptr+=24; ++ } ++ else ++ ptr = recvframe_pull(precvframe, (rmv_len-sizeof(struct ethhdr)+2)); ++ ++ _rtw_memcpy(ptr, pattrib->dst, ETH_ALEN); ++ _rtw_memcpy(ptr+ETH_ALEN, pattrib->src, ETH_ALEN); ++ ++ eth_type = htons((unsigned short)eth_type) ; ++ _rtw_memcpy(ptr+12, ð_type, 2); ++ ++exit: ++ ++_func_exit_; ++ ++ return ret; ++} ++#endif ++ ++//perform defrag ++static union recv_frame * recvframe_defrag(_adapter *adapter,_queue *defrag_q) ++{ ++ _list *plist, *phead; ++ u8 *data,wlanhdr_offset; ++ u8 curfragnum; ++ struct recv_frame_hdr *pfhdr,*pnfhdr; ++ union recv_frame* prframe, *pnextrframe; ++ _queue *pfree_recv_queue; ++ ++_func_enter_; ++ ++ curfragnum=0; ++ pfree_recv_queue=&adapter->recvpriv.free_recv_queue; ++ ++ phead = get_list_head(defrag_q); ++ plist = get_next(phead); ++ prframe = LIST_CONTAINOR(plist, union recv_frame, u); ++ pfhdr=&prframe->u.hdr; ++ rtw_list_delete(&(prframe->u.list)); ++ ++ if(curfragnum!=pfhdr->attrib.frag_num) ++ { ++ //the first fragment number must be 0 ++ //free the whole queue ++ rtw_free_recvframe(prframe, pfree_recv_queue); ++ rtw_free_recvframe_queue(defrag_q, pfree_recv_queue); ++ ++ return NULL; ++ } ++ ++ curfragnum++; ++ ++ plist= get_list_head(defrag_q); ++ ++ plist = get_next(plist); ++ ++ data=get_recvframe_data(prframe); ++ ++ while(rtw_end_of_queue_search(phead, plist) == _FALSE) ++ { ++ pnextrframe = LIST_CONTAINOR(plist, union recv_frame , u); ++ pnfhdr=&pnextrframe->u.hdr; ++ ++ ++ //check the fragment sequence (2nd ~n fragment frame) ++ ++ if(curfragnum!=pnfhdr->attrib.frag_num) ++ { ++ //the fragment number must be increasing (after decache) ++ //release the defrag_q & prframe ++ rtw_free_recvframe(prframe, pfree_recv_queue); ++ rtw_free_recvframe_queue(defrag_q, pfree_recv_queue); ++ return NULL; ++ } ++ ++ curfragnum++; ++ ++ //copy the 2nd~n fragment frame's payload to the first fragment ++ //get the 2nd~last fragment frame's payload ++ ++ wlanhdr_offset = pnfhdr->attrib.hdrlen + pnfhdr->attrib.iv_len; ++ ++ recvframe_pull(pnextrframe, wlanhdr_offset); ++ ++ //append to first fragment frame's tail (if privacy frame, pull the ICV) ++ recvframe_pull_tail(prframe, pfhdr->attrib.icv_len); ++ ++ //memcpy ++ _rtw_memcpy(pfhdr->rx_tail, pnfhdr->rx_data, pnfhdr->len); ++ ++ recvframe_put(prframe, pnfhdr->len); ++ ++ pfhdr->attrib.icv_len=pnfhdr->attrib.icv_len; ++ plist = get_next(plist); ++ ++ }; ++ ++ //free the defrag_q queue and return the prframe ++ rtw_free_recvframe_queue(defrag_q, pfree_recv_queue); ++ ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("Performance defrag!!!!!\n")); ++ ++_func_exit_; ++ ++ return prframe; ++} ++ ++ ++//check if need to defrag, if needed queue the frame to defrag_q ++static union recv_frame * recvframe_chk_defrag(_adapter *padapter,union recv_frame* precv_frame) ++{ ++ u8 ismfrag; ++ u8 fragnum; ++ u8 *psta_addr; ++ struct recv_frame_hdr *pfhdr; ++ struct sta_info * psta; ++ struct sta_priv *pstapriv ; ++ _list *phead; ++ union recv_frame* prtnframe=NULL; ++ _queue *pfree_recv_queue, *pdefrag_q; ++ ++_func_enter_; ++ ++ pstapriv = &padapter->stapriv; ++ ++ pfhdr=&precv_frame->u.hdr; ++ ++ pfree_recv_queue=&padapter->recvpriv.free_recv_queue; ++ ++ //need to define struct of wlan header frame ctrl ++ ismfrag= pfhdr->attrib.mfrag; ++ fragnum=pfhdr->attrib.frag_num; ++ ++ psta_addr=pfhdr->attrib.ta; ++ psta=rtw_get_stainfo(pstapriv, psta_addr); ++ if (psta==NULL) ++ pdefrag_q = NULL; ++ else ++ pdefrag_q=&psta->sta_recvpriv.defrag_q; ++ ++ if ((ismfrag==0) && (fragnum==0)) ++ { ++ prtnframe = precv_frame;//isn't a fragment frame ++ } ++ ++ if (ismfrag==1) ++ { ++ //0~(n-1) fragment frame ++ //enqueue to defraf_g ++ if(pdefrag_q != NULL) ++ { ++ if(fragnum==0) ++ { ++ //the first fragment ++ if(_rtw_queue_empty(pdefrag_q) == _FALSE) ++ { ++ //free current defrag_q ++ rtw_free_recvframe_queue(pdefrag_q, pfree_recv_queue); ++ } ++ } ++ ++ ++ //Then enqueue the 0~(n-1) fragment into the defrag_q ++ ++ //_rtw_spinlock(&pdefrag_q->lock); ++ phead = get_list_head(pdefrag_q); ++ rtw_list_insert_tail(&pfhdr->list, phead); ++ //_rtw_spinunlock(&pdefrag_q->lock); ++ ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("Enqueuq: ismfrag = %d, fragnum= %d\n", ismfrag,fragnum)); ++ ++ prtnframe=NULL; ++ ++ } ++ else ++ { ++ //can't find this ta's defrag_queue, so free this recv_frame ++ rtw_free_recvframe(precv_frame, pfree_recv_queue); ++ prtnframe=NULL; ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("Free because pdefrag_q ==NULL: ismfrag = %d, fragnum= %d\n", ismfrag, fragnum)); ++ } ++ ++ } ++ ++ if((ismfrag==0)&&(fragnum!=0)) ++ { ++ //the last fragment frame ++ //enqueue the last fragment ++ if(pdefrag_q != NULL) ++ { ++ //_rtw_spinlock(&pdefrag_q->lock); ++ phead = get_list_head(pdefrag_q); ++ rtw_list_insert_tail(&pfhdr->list,phead); ++ //_rtw_spinunlock(&pdefrag_q->lock); ++ ++ //call recvframe_defrag to defrag ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("defrag: ismfrag = %d, fragnum= %d\n", ismfrag, fragnum)); ++ precv_frame = recvframe_defrag(padapter, pdefrag_q); ++ prtnframe=precv_frame; ++ ++ } ++ else ++ { ++ //can't find this ta's defrag_queue, so free this recv_frame ++ rtw_free_recvframe(precv_frame, pfree_recv_queue); ++ prtnframe=NULL; ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("Free because pdefrag_q ==NULL: ismfrag = %d, fragnum= %d\n", ismfrag,fragnum)); ++ } ++ ++ } ++ ++ ++ if((prtnframe!=NULL)&&(prtnframe->u.hdr.attrib.privacy)) ++ { ++ //after defrag we must check tkip mic code ++ if(recvframe_chkmic(padapter, prtnframe)==_FAIL) ++ { ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("recvframe_chkmic(padapter, prtnframe)==_FAIL\n")); ++ rtw_free_recvframe(prtnframe,pfree_recv_queue); ++ prtnframe=NULL; ++ } ++ } ++ ++_func_exit_; ++ ++ return prtnframe; ++ ++} ++ ++ ++static int amsdu_to_msdu(_adapter *padapter, union recv_frame *prframe) ++{ ++#ifdef PLATFORM_LINUX //for amsdu TP improvement,Creator: Thomas ++ int a_len, padding_len; ++ u16 eth_type, nSubframe_Length; ++ u8 nr_subframes, i; ++ unsigned char *data_ptr, *pdata; ++ struct rx_pkt_attrib *pattrib; ++ _pkt *sub_skb,*subframes[MAX_SUBFRAME_COUNT]; ++ struct recv_priv *precvpriv = &padapter->recvpriv; ++ _queue *pfree_recv_queue = &(precvpriv->free_recv_queue); ++ int ret = _SUCCESS; ++ ++ nr_subframes = 0; ++ ++ pattrib = &prframe->u.hdr.attrib; ++ ++ recvframe_pull(prframe, prframe->u.hdr.attrib.hdrlen); ++ ++ if(prframe->u.hdr.attrib.iv_len >0) ++ { ++ recvframe_pull(prframe, prframe->u.hdr.attrib.iv_len); ++ } ++ ++ a_len = prframe->u.hdr.len; ++ ++ pdata = prframe->u.hdr.rx_data; ++ ++ while(a_len > ETH_HLEN) { ++ ++ /* Offset 12 denote 2 mac address */ ++ //nSubframe_Length = *((u16*)(pdata + 12)); ++ //==m==>change the length order ++ //nSubframe_Length = (nSubframe_Length>>8) + (nSubframe_Length<<8); ++ //nSubframe_Length = ntohs(*((u16*)(pdata + 12))); ++ nSubframe_Length = RTW_GET_BE16(pdata + 12); ++ ++ //ntohs(nSubframe_Length); ++ ++ if( a_len < (ETHERNET_HEADER_SIZE + nSubframe_Length) ) { ++ DBG_8192C("nRemain_Length is %d and nSubframe_Length is : %d\n",a_len,nSubframe_Length); ++ goto exit; ++ } ++ ++ /* move the data point to data content */ ++ pdata += ETH_HLEN; ++ a_len -= ETH_HLEN; ++ ++ /* Allocate new skb for releasing to upper layer */ ++#ifdef CONFIG_SKB_COPY ++ sub_skb = dev_alloc_skb(nSubframe_Length + 12); ++ if(sub_skb) ++ { ++ skb_reserve(sub_skb, 12); ++ data_ptr = (u8 *)skb_put(sub_skb, nSubframe_Length); ++ _rtw_memcpy(data_ptr, pdata, nSubframe_Length); ++ } ++ else ++ { ++#endif // CONFIG_SKB_COPY ++ sub_skb = skb_clone(prframe->u.hdr.pkt, GFP_ATOMIC); ++ if(sub_skb) ++ { ++ sub_skb->data = pdata; ++ sub_skb->len = nSubframe_Length; ++ sub_skb->tail = sub_skb->data + nSubframe_Length; ++ } ++ else ++ { ++ DBG_8192C("skb_clone() Fail!!! , nr_subframes = %d\n",nr_subframes); ++ break; ++ } ++ } ++ ++ //sub_skb->dev = padapter->pnetdev; ++ subframes[nr_subframes++] = sub_skb; ++ if(nr_subframes >= MAX_SUBFRAME_COUNT) { ++ DBG_8192C("ParseSubframe(): Too many Subframes! Packets dropped!\n"); ++ break; ++ } ++ ++ pdata += nSubframe_Length; ++ a_len -= nSubframe_Length; ++ if(a_len != 0) { ++ padding_len = 4 - ((nSubframe_Length + ETH_HLEN) & (4-1)); ++ if(padding_len == 4) { ++ padding_len = 0; ++ } ++ ++ if(a_len < padding_len) { ++ goto exit; ++ } ++ pdata += padding_len; ++ a_len -= padding_len; ++ } ++ } ++ ++ for(i=0; idata[6] << 8) | sub_skb->data[7]; ++ //eth_type = ntohs(*(u16*)&sub_skb->data[6]); ++ eth_type = RTW_GET_BE16(&sub_skb->data[6]); ++ if (sub_skb->len >= 8 && ++ ((_rtw_memcmp(sub_skb->data, rtw_rfc1042_header, SNAP_SIZE) && ++ eth_type != ETH_P_AARP && eth_type != ETH_P_IPX) || ++ _rtw_memcmp(sub_skb->data, rtw_bridge_tunnel_header, SNAP_SIZE) )) { ++ /* remove RFC1042 or Bridge-Tunnel encapsulation and replace EtherType */ ++ skb_pull(sub_skb, SNAP_SIZE); ++ _rtw_memcpy(skb_push(sub_skb, ETH_ALEN), pattrib->src, ETH_ALEN); ++ _rtw_memcpy(skb_push(sub_skb, ETH_ALEN), pattrib->dst, ETH_ALEN); ++ } else { ++ u16 len; ++ /* Leave Ethernet header part of hdr and full payload */ ++ len = htons(sub_skb->len); ++ _rtw_memcpy(skb_push(sub_skb, 2), &len, 2); ++ _rtw_memcpy(skb_push(sub_skb, ETH_ALEN), pattrib->src, ETH_ALEN); ++ _rtw_memcpy(skb_push(sub_skb, ETH_ALEN), pattrib->dst, ETH_ALEN); ++ } ++ ++ /* Indicat the packets to upper layer */ ++ if (sub_skb) { ++ //memset(sub_skb->cb, 0, sizeof(sub_skb->cb)); ++ ++#ifdef CONFIG_BR_EXT ++ // Insert NAT2.5 RX here! ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ void *br_port = NULL; ++ ++#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35)) ++ br_port = padapter->pnetdev->br_port; ++#else // (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35)) ++ rcu_read_lock(); ++ br_port = rcu_dereference(padapter->pnetdev->rx_handler_data); ++ rcu_read_unlock(); ++#endif // (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35)) ++ ++ ++ if( br_port && (check_fwstate(pmlmepriv, WIFI_STATION_STATE|WIFI_ADHOC_STATE) == _TRUE) ) ++ { ++ int nat25_handle_frame(_adapter *priv, struct sk_buff *skb); ++ if (nat25_handle_frame(padapter, sub_skb) == -1) { ++ //priv->ext_stats.rx_data_drops++; ++ //DEBUG_ERR("RX DROP: nat25_handle_frame fail!\n"); ++ //return FAIL; ++ ++#if 1 ++ // bypass this frame to upper layer!! ++#else ++ dev_kfree_skb_any(sub_skb); ++ continue; ++#endif ++ } ++ } ++#endif // CONFIG_BR_EXT ++ ++ sub_skb->protocol = eth_type_trans(sub_skb, padapter->pnetdev); ++ sub_skb->dev = padapter->pnetdev; ++ ++#ifdef CONFIG_TCP_CSUM_OFFLOAD_RX ++ if ( (pattrib->tcpchk_valid == 1) && (pattrib->tcp_chkrpt == 1) ) { ++ sub_skb->ip_summed = CHECKSUM_UNNECESSARY; ++ } else { ++ sub_skb->ip_summed = CHECKSUM_NONE; ++ } ++#else /* !CONFIG_TCP_CSUM_OFFLOAD_RX */ ++ sub_skb->ip_summed = CHECKSUM_NONE; ++#endif ++ ++ netif_rx(sub_skb); ++ } ++ } ++ ++exit: ++ ++ prframe->u.hdr.len=0; ++ rtw_free_recvframe(prframe, pfree_recv_queue);//free this recv_frame ++ ++ return ret; ++#else ++ _irqL irql; ++ unsigned char *ptr, *pdata, *pbuf, *psnap_type; ++ union recv_frame *pnrframe, *pnrframe_new; ++ int a_len, mv_len, padding_len; ++ u16 eth_type, type_len; ++ u8 bsnaphdr; ++ struct ieee80211_snap_hdr *psnap; ++ struct _vlan *pvlan; ++ struct recv_priv *precvpriv = &padapter->recvpriv; ++ _queue *pfree_recv_queue = &(precvpriv->free_recv_queue); ++ int ret = _SUCCESS; ++#ifdef PLATFORM_WINDOWS ++ struct recv_buf *precvbuf = prframe->u.hdr.precvbuf; ++#endif ++ a_len = prframe->u.hdr.len - prframe->u.hdr.attrib.hdrlen; ++ ++ recvframe_pull(prframe, prframe->u.hdr.attrib.hdrlen); ++ ++ if(prframe->u.hdr.attrib.iv_len >0) ++ { ++ recvframe_pull(prframe, prframe->u.hdr.attrib.iv_len); ++ } ++ ++ pdata = prframe->u.hdr.rx_data; ++ ++ prframe->u.hdr.len=0; ++ ++ pnrframe = prframe; ++ ++ ++ do{ ++ ++ mv_len=0; ++ pnrframe->u.hdr.rx_data = pnrframe->u.hdr.rx_tail = pdata; ++ ptr = pdata; ++ ++ ++ _rtw_memcpy(pnrframe->u.hdr.attrib.dst, ptr, ETH_ALEN); ++ ptr+=ETH_ALEN; ++ _rtw_memcpy(pnrframe->u.hdr.attrib.src, ptr, ETH_ALEN); ++ ptr+=ETH_ALEN; ++ ++ _rtw_memcpy(&type_len, ptr, 2); ++ type_len= ntohs((unsigned short )type_len); ++ ptr +=2; ++ mv_len += ETH_HLEN; ++ ++ recvframe_put(pnrframe, type_len+ETH_HLEN);//update tail; ++ ++ if(pnrframe->u.hdr.rx_data >= pnrframe->u.hdr.rx_tail || type_len<8) ++ { ++ //panic("pnrframe->u.hdr.rx_data >= pnrframe->u.hdr.rx_tail || type_len<8\n"); ++ ++ rtw_free_recvframe(pnrframe, pfree_recv_queue); ++ ++ goto exit; ++ } ++ ++ psnap=(struct ieee80211_snap_hdr *)(ptr); ++ psnap_type=ptr+SNAP_SIZE; ++ if (psnap->dsap==0xaa && psnap->ssap==0xaa && psnap->ctrl==0x03) ++ { ++ if ( _rtw_memcmp(psnap->oui, oui_rfc1042, WLAN_IEEE_OUI_LEN)) ++ { ++ bsnaphdr=_TRUE;//wlan_pkt_format = WLAN_PKT_FORMAT_SNAP_RFC1042; ++ } ++ else if (_rtw_memcmp(psnap->oui, SNAP_HDR_APPLETALK_DDP, WLAN_IEEE_OUI_LEN) && ++ _rtw_memcmp(psnap_type, SNAP_ETH_TYPE_APPLETALK_DDP, 2) ) ++ { ++ bsnaphdr=_TRUE; //wlan_pkt_format = WLAN_PKT_FORMAT_APPLETALK; ++ } ++ else if (_rtw_memcmp( psnap->oui, oui_8021h, WLAN_IEEE_OUI_LEN)) ++ { ++ bsnaphdr=_TRUE; //wlan_pkt_format = WLAN_PKT_FORMAT_SNAP_TUNNEL; ++ } ++ else ++ { ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("drop pkt due to invalid frame format!\n")); ++ ++ //KeBugCheckEx(0x87123333, 0xe0, 0x4c, 0x87, 0xdd); ++ ++ //panic("0x87123333, 0xe0, 0x4c, 0x87, 0xdd\n"); ++ ++ rtw_free_recvframe(pnrframe, pfree_recv_queue); ++ ++ goto exit; ++ } ++ ++ } ++ else ++ { ++ bsnaphdr=_FALSE;//wlan_pkt_format = WLAN_PKT_FORMAT_OTHERS; ++ } ++ ++ ptr += (bsnaphdr?SNAP_SIZE:0); ++ _rtw_memcpy(ð_type, ptr, 2); ++ eth_type= ntohs((unsigned short )eth_type); //pattrib->ether_type ++ ++ mv_len+= 2+(bsnaphdr?SNAP_SIZE:0); ++ ptr += 2;//now move to iphdr; ++ ++ pvlan = NULL; ++ if(eth_type == 0x8100) //vlan ++ { ++ pvlan = (struct _vlan *)ptr; ++ ptr+=4; ++ mv_len+=4; ++ } ++ ++ if(eth_type==0x0800)//ip ++ { ++ struct iphdr* piphdr = (struct iphdr*)ptr; ++ ++ ++ if (piphdr->protocol == 0x06) ++ { ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("@@@===recv tcp len:%d @@@===\n", pnrframe->u.hdr.len)); ++ } ++ } ++#ifdef PLATFORM_OS_XP ++ else ++ { ++ NDIS_PACKET_8021Q_INFO VlanPriInfo; ++ UINT32 UserPriority = pnrframe->u.hdr.attrib.priority; ++ UINT32 VlanID = (pvlan!=NULL ? get_vlan_id(pvlan) : 0 ); ++ ++ VlanPriInfo.Value = // Get current value. ++ NDIS_PER_PACKET_INFO_FROM_PACKET(pnrframe->u.hdr.pkt, Ieee8021QInfo); ++ ++ VlanPriInfo.TagHeader.UserPriority = UserPriority; ++ VlanPriInfo.TagHeader.VlanId = VlanID; ++ ++ VlanPriInfo.TagHeader.CanonicalFormatId = 0; // Should be zero. ++ VlanPriInfo.TagHeader.Reserved = 0; // Should be zero. ++ NDIS_PER_PACKET_INFO_FROM_PACKET(pnrframe->u.hdr.pkt, Ieee8021QInfo) = VlanPriInfo.Value; ++ ++ } ++#endif ++ ++ pbuf = recvframe_pull(pnrframe, (mv_len-sizeof(struct ethhdr))); ++ ++ _rtw_memcpy(pbuf, pnrframe->u.hdr.attrib.dst, ETH_ALEN); ++ _rtw_memcpy(pbuf+ETH_ALEN, pnrframe->u.hdr.attrib.src, ETH_ALEN); ++ ++ eth_type = htons((unsigned short)eth_type) ; ++ _rtw_memcpy(pbuf+12, ð_type, 2); ++ ++ padding_len = (4) - ((type_len + ETH_HLEN)&(4-1)); ++ ++ a_len -= (type_len + ETH_HLEN + padding_len) ; ++ ++ ++#if 0 ++ ++ if(a_len > ETH_HLEN) ++ { ++ pnrframe_new = rtw_alloc_recvframe(pfree_recv_queue); ++ if(pnrframe_new) ++ { ++ _pkt *pskb_copy; ++ unsigned int copy_len = pnrframe->u.hdr.len; ++ ++ _rtw_init_listhead(&pnrframe_new->u.hdr.list); ++ ++ #if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18)) // http://www.mail-archive.com/netdev@vger.kernel.org/msg17214.html ++ pskb_copy = dev_alloc_skb(copy_len+64); ++ #else ++ pskb_copy = netdev_alloc_skb(padapter->pnetdev, copy_len + 64); ++ #endif ++ if(pskb_copy==NULL) ++ { ++ DBG_8192C("amsdu_to_msdu:can not all(ocate memory for skb copy\n"); ++ } ++ ++ pnrframe_new->u.hdr.pkt = pskb_copy; ++ ++ _rtw_memcpy(pskb_copy->data, pnrframe->u.hdr.rx_data, copy_len); ++ ++ pnrframe_new->u.hdr.rx_data = pnrframe->u.hdr.rx_data; ++ pnrframe_new->u.hdr.rx_tail = pnrframe->u.hdr.rx_data + copy_len; ++ ++ ++ if ((padapter->bDriverStopped ==_FALSE)&&( padapter->bSurpriseRemoved==_FALSE)) ++ { ++ rtw_recv_indicatepkt(padapter, pnrframe_new);//indicate this recv_frame ++ } ++ else ++ { ++ rtw_free_recvframe(pnrframe_new, pfree_recv_queue);//free this recv_frame ++ } ++ ++ } ++ else ++ { ++ DBG_8192C("amsdu_to_msdu:can not allocate memory for pnrframe_new\n"); ++ } ++ ++ } ++ else ++ { ++ if ((padapter->bDriverStopped ==_FALSE)&&( padapter->bSurpriseRemoved==_FALSE)) ++ { ++ rtw_recv_indicatepkt(padapter, pnrframe);//indicate this recv_frame ++ } ++ else ++ { ++ rtw_free_recvframe(pnrframe, pfree_recv_queue);//free this recv_frame ++ } ++ ++ pnrframe = NULL; ++ ++ } ++ ++#else ++ ++ //padding_len = (4) - ((type_len + ETH_HLEN)&(4-1)); ++ ++ //a_len -= (type_len + ETH_HLEN + padding_len) ; ++ ++ pnrframe_new = NULL; ++ ++ ++ if(a_len > ETH_HLEN) ++ { ++ pnrframe_new = rtw_alloc_recvframe(pfree_recv_queue); ++ ++ if(pnrframe_new) ++ { ++ ++ ++ //pnrframe_new->u.hdr.precvbuf = precvbuf;//precvbuf is assigned before call rtw_init_recvframe() ++ //rtw_init_recvframe(pnrframe_new, precvpriv); ++ { ++ _pkt *pskb = pnrframe->u.hdr.pkt; ++ _rtw_init_listhead(&pnrframe_new->u.hdr.list); ++ ++ pnrframe_new->u.hdr.len=0; ++ ++#ifdef PLATFORM_LINUX ++ if(pskb) ++ { ++ pnrframe_new->u.hdr.pkt = skb_clone(pskb, GFP_ATOMIC); ++ } ++#endif ++ ++ } ++ ++ pdata += (type_len + ETH_HLEN + padding_len); ++ pnrframe_new->u.hdr.rx_head = pnrframe_new->u.hdr.rx_data = pnrframe_new->u.hdr.rx_tail = pdata; ++ pnrframe_new->u.hdr.rx_end = pdata + a_len + padding_len;// ++ ++#ifdef PLATFORM_WINDOWS ++ pnrframe_new->u.hdr.precvbuf=precvbuf; ++ _enter_critical_bh(&precvbuf->recvbuf_lock, &irql); ++ precvbuf->ref_cnt++; ++ _exit_critical_bh(&precvbuf->recvbuf_lock, &irql); ++#endif ++ ++ } ++ else ++ { ++ //panic("pnrframe_new=%x\n", pnrframe_new); ++ } ++ } ++ ++ ++ if ((padapter->bDriverStopped ==_FALSE)&&( padapter->bSurpriseRemoved==_FALSE) ) ++ { ++ rtw_recv_indicatepkt(padapter, pnrframe);//indicate this recv_frame ++ } ++ else ++ { ++ rtw_free_recvframe(pnrframe, pfree_recv_queue);//free this recv_frame ++ } ++ ++ ++ pnrframe = NULL; ++ if(pnrframe_new) ++ { ++ pnrframe = pnrframe_new; ++ } ++ ++ ++#endif ++ ++ }while(pnrframe); ++ ++exit: ++ ++ return ret; ++#endif ++} ++ ++ ++static int check_indicate_seq(struct recv_reorder_ctrl *preorder_ctrl, u16 seq_num) ++{ ++ u8 wsize = preorder_ctrl->wsize_b; ++ u16 wend = (preorder_ctrl->indicate_seq + wsize -1) & 0xFFF;//% 4096; ++ ++ // Rx Reorder initialize condition. ++ if (preorder_ctrl->indicate_seq == 0xFFFF) ++ { ++ preorder_ctrl->indicate_seq = seq_num; ++ #ifdef DBG_RX_SEQ ++ DBG_871X("DBG_RX_SEQ %s:%d init IndicateSeq: %d, NewSeq: %d\n", __FUNCTION__, __LINE__, ++ preorder_ctrl->indicate_seq, seq_num); ++ #endif ++ ++ //DbgPrint("check_indicate_seq, 1st->indicate_seq=%d\n", precvpriv->indicate_seq); ++ } ++ ++ //DbgPrint("enter->check_indicate_seq(): IndicateSeq: %d, NewSeq: %d\n", precvpriv->indicate_seq, seq_num); ++ ++ // Drop out the packet which SeqNum is smaller than WinStart ++ if( SN_LESS(seq_num, preorder_ctrl->indicate_seq) ) ++ { ++ //RT_TRACE(COMP_RX_REORDER, DBG_LOUD, ("CheckRxTsIndicateSeq(): Packet Drop! IndicateSeq: %d, NewSeq: %d\n", pTS->RxIndicateSeq, NewSeqNum)); ++ //DbgPrint("CheckRxTsIndicateSeq(): Packet Drop! IndicateSeq: %d, NewSeq: %d\n", precvpriv->indicate_seq, seq_num); ++ ++ #ifdef DBG_RX_DROP_FRAME ++ DBG_871X("DBG_RX_DROP_FRAME %s IndicateSeq: %d, NewSeq: %d\n", __FUNCTION__, ++ preorder_ctrl->indicate_seq, seq_num); ++ #endif ++ ++ ++ return _FALSE; ++ } ++ ++ // ++ // Sliding window manipulation. Conditions includes: ++ // 1. Incoming SeqNum is equal to WinStart =>Window shift 1 ++ // 2. Incoming SeqNum is larger than the WinEnd => Window shift N ++ // ++ if( SN_EQUAL(seq_num, preorder_ctrl->indicate_seq) ) ++ { ++ preorder_ctrl->indicate_seq = (preorder_ctrl->indicate_seq + 1) & 0xFFF; ++ #ifdef DBG_RX_SEQ ++ DBG_871X("DBG_RX_SEQ %s:%d SN_EQUAL IndicateSeq: %d, NewSeq: %d\n", __FUNCTION__, __LINE__, ++ preorder_ctrl->indicate_seq, seq_num); ++ #endif ++ } ++ else if(SN_LESS(wend, seq_num)) ++ { ++ //RT_TRACE(COMP_RX_REORDER, DBG_LOUD, ("CheckRxTsIndicateSeq(): Window Shift! IndicateSeq: %d, NewSeq: %d\n", pTS->RxIndicateSeq, NewSeqNum)); ++ //DbgPrint("CheckRxTsIndicateSeq(): Window Shift! IndicateSeq: %d, NewSeq: %d\n", precvpriv->indicate_seq, seq_num); ++ ++ // boundary situation, when seq_num cross 0xFFF ++ if(seq_num >= (wsize - 1)) ++ preorder_ctrl->indicate_seq = seq_num + 1 -wsize; ++ else ++ preorder_ctrl->indicate_seq = 0xFFF - (wsize - (seq_num + 1)) + 1; ++ ++ #ifdef DBG_RX_SEQ ++ DBG_871X("DBG_RX_SEQ %s:%d SN_LESS(wend, seq_num) IndicateSeq: %d, NewSeq: %d\n", __FUNCTION__, __LINE__, ++ preorder_ctrl->indicate_seq, seq_num); ++ #endif ++ } ++ ++ //DbgPrint("exit->check_indicate_seq(): IndicateSeq: %d, NewSeq: %d\n", precvpriv->indicate_seq, seq_num); ++ ++ return _TRUE; ++} ++ ++ ++static int enqueue_reorder_recvframe(struct recv_reorder_ctrl *preorder_ctrl, union recv_frame *prframe) ++{ ++ struct rx_pkt_attrib *pattrib = &prframe->u.hdr.attrib; ++ _queue *ppending_recvframe_queue = &preorder_ctrl->pending_recvframe_queue; ++ _list *phead, *plist; ++ union recv_frame *pnextrframe; ++ struct rx_pkt_attrib *pnextattrib; ++ ++ //DbgPrint("+enqueue_reorder_recvframe()\n"); ++ ++ //_enter_critical_ex(&ppending_recvframe_queue->lock, &irql); ++ //_rtw_spinlock_ex(&ppending_recvframe_queue->lock); ++ ++ ++ phead = get_list_head(ppending_recvframe_queue); ++ plist = get_next(phead); ++ ++ while(rtw_end_of_queue_search(phead, plist) == _FALSE) ++ { ++ pnextrframe = LIST_CONTAINOR(plist, union recv_frame, u); ++ pnextattrib = &pnextrframe->u.hdr.attrib; ++ ++ if(SN_LESS(pnextattrib->seq_num, pattrib->seq_num)) ++ { ++ plist = get_next(plist); ++ } ++ else if( SN_EQUAL(pnextattrib->seq_num, pattrib->seq_num)) ++ { ++ //Duplicate entry is found!! Do not insert current entry. ++ //RT_TRACE(COMP_RX_REORDER, DBG_TRACE, ("InsertRxReorderList(): Duplicate packet is dropped!! IndicateSeq: %d, NewSeq: %d\n", pTS->RxIndicateSeq, SeqNum)); ++ ++ //_exit_critical_ex(&ppending_recvframe_queue->lock, &irql); ++ ++ return _FALSE; ++ } ++ else ++ { ++ break; ++ } ++ ++ //DbgPrint("enqueue_reorder_recvframe():while\n"); ++ ++ } ++ ++ ++ //_enter_critical_ex(&ppending_recvframe_queue->lock, &irql); ++ //_rtw_spinlock_ex(&ppending_recvframe_queue->lock); ++ ++ rtw_list_delete(&(prframe->u.hdr.list)); ++ ++ rtw_list_insert_tail(&(prframe->u.hdr.list), plist); ++ ++ //_rtw_spinunlock_ex(&ppending_recvframe_queue->lock); ++ //_exit_critical_ex(&ppending_recvframe_queue->lock, &irql); ++ ++ ++ //RT_TRACE(COMP_RX_REORDER, DBG_TRACE, ("InsertRxReorderList(): Pkt insert into buffer!! IndicateSeq: %d, NewSeq: %d\n", pTS->RxIndicateSeq, SeqNum)); ++ return _TRUE; ++ ++} ++ ++ ++static int recv_indicatepkts_in_order(_adapter *padapter, struct recv_reorder_ctrl *preorder_ctrl, int bforced) ++{ ++ _irqL irql; ++ //u8 bcancelled; ++ _list *phead, *plist; ++ union recv_frame *prframe; ++ struct rx_pkt_attrib *pattrib; ++ //u8 index = 0; ++ int bPktInBuf = _FALSE; ++ struct recv_priv *precvpriv = &padapter->recvpriv; ++ _queue *ppending_recvframe_queue = &preorder_ctrl->pending_recvframe_queue; ++ ++ //DbgPrint("+recv_indicatepkts_in_order\n"); ++ ++ //_enter_critical_ex(&ppending_recvframe_queue->lock, &irql); ++ //_rtw_spinlock_ex(&ppending_recvframe_queue->lock); ++ ++ phead = get_list_head(ppending_recvframe_queue); ++ plist = get_next(phead); ++ ++#if 0 ++ // Check if there is any other indication thread running. ++ if(pTS->RxIndicateState == RXTS_INDICATE_PROCESSING) ++ return; ++#endif ++ ++ // Handling some condition for forced indicate case. ++ if(bforced==_TRUE) ++ { ++ if(rtw_is_list_empty(phead)) ++ { ++ // _exit_critical_ex(&ppending_recvframe_queue->lock, &irql); ++ //_rtw_spinunlock_ex(&ppending_recvframe_queue->lock); ++ return _TRUE; ++ } ++ ++ prframe = LIST_CONTAINOR(plist, union recv_frame, u); ++ pattrib = &prframe->u.hdr.attrib; ++ preorder_ctrl->indicate_seq = pattrib->seq_num; ++ #ifdef DBG_RX_SEQ ++ DBG_871X("DBG_RX_SEQ %s:%d IndicateSeq: %d, NewSeq: %d\n", __FUNCTION__, __LINE__, ++ preorder_ctrl->indicate_seq, pattrib->seq_num); ++ #endif ++ } ++ ++ // Prepare indication list and indication. ++ // Check if there is any packet need indicate. ++ while(!rtw_is_list_empty(phead)) ++ { ++ ++ prframe = LIST_CONTAINOR(plist, union recv_frame, u); ++ pattrib = &prframe->u.hdr.attrib; ++ ++ if(!SN_LESS(preorder_ctrl->indicate_seq, pattrib->seq_num)) ++ { ++ RT_TRACE(_module_rtl871x_recv_c_, _drv_notice_, ++ ("recv_indicatepkts_in_order: indicate=%d seq=%d amsdu=%d\n", ++ preorder_ctrl->indicate_seq, pattrib->seq_num, pattrib->amsdu)); ++ ++#if 0 ++ // This protect buffer from overflow. ++ if(index >= REORDER_WIN_SIZE) ++ { ++ RT_ASSERT(FALSE, ("IndicateRxReorderList(): Buffer overflow!! \n")); ++ bPktInBuf = TRUE; ++ break; ++ } ++#endif ++ ++ plist = get_next(plist); ++ rtw_list_delete(&(prframe->u.hdr.list)); ++ ++ if(SN_EQUAL(preorder_ctrl->indicate_seq, pattrib->seq_num)) ++ { ++ preorder_ctrl->indicate_seq = (preorder_ctrl->indicate_seq + 1) & 0xFFF; ++ #ifdef DBG_RX_SEQ ++ DBG_871X("DBG_RX_SEQ %s:%d IndicateSeq: %d, NewSeq: %d\n", __FUNCTION__, __LINE__, ++ preorder_ctrl->indicate_seq, pattrib->seq_num); ++ #endif ++ } ++ ++#if 0 ++ index++; ++ if(index==1) ++ { ++ //Cancel previous pending timer. ++ //PlatformCancelTimer(Adapter, &pTS->RxPktPendingTimer); ++ if(bforced!=_TRUE) ++ { ++ //DBG_8192C("_cancel_timer(&preorder_ctrl->reordering_ctrl_timer, &bcancelled);\n"); ++ _cancel_timer(&preorder_ctrl->reordering_ctrl_timer, &bcancelled); ++ } ++ } ++#endif ++ ++ //Set this as a lock to make sure that only one thread is indicating packet. ++ //pTS->RxIndicateState = RXTS_INDICATE_PROCESSING; ++ ++ // Indicate packets ++ //RT_ASSERT((index<=REORDER_WIN_SIZE), ("RxReorderIndicatePacket(): Rx Reorder buffer full!! \n")); ++ ++ ++ //indicate this recv_frame ++ //DbgPrint("recv_indicatepkts_in_order, indicate_seq=%d, seq_num=%d\n", precvpriv->indicate_seq, pattrib->seq_num); ++ if(!pattrib->amsdu) ++ { ++ //DBG_8192C("recv_indicatepkts_in_order, amsdu!=1, indicate_seq=%d, seq_num=%d\n", preorder_ctrl->indicate_seq, pattrib->seq_num); ++ ++ if ((padapter->bDriverStopped == _FALSE) && ++ (padapter->bSurpriseRemoved == _FALSE)) ++ { ++ ++ rtw_recv_indicatepkt(padapter, prframe); //indicate this recv_frame ++ ++ } ++ } ++ else if(pattrib->amsdu==1) ++ { ++ if(amsdu_to_msdu(padapter, prframe)!=_SUCCESS) ++ { ++ rtw_free_recvframe(prframe, &precvpriv->free_recv_queue); ++ } ++ } ++ else ++ { ++ //error condition; ++ } ++ ++ ++ //Update local variables. ++ bPktInBuf = _FALSE; ++ ++ } ++ else ++ { ++ bPktInBuf = _TRUE; ++ break; ++ } ++ ++ //DbgPrint("recv_indicatepkts_in_order():while\n"); ++ ++ } ++ ++ //_rtw_spinunlock_ex(&ppending_recvframe_queue->lock); ++ //_exit_critical_ex(&ppending_recvframe_queue->lock, &irql); ++ ++/* ++ //Release the indication lock and set to new indication step. ++ if(bPktInBuf) ++ { ++ // Set new pending timer. ++ //pTS->RxIndicateState = RXTS_INDICATE_REORDER; ++ //PlatformSetTimer(Adapter, &pTS->RxPktPendingTimer, pHTInfo->RxReorderPendingTime); ++ //DBG_8192C("_set_timer(&preorder_ctrl->reordering_ctrl_timer, REORDER_WAIT_TIME)\n"); ++ _set_timer(&preorder_ctrl->reordering_ctrl_timer, REORDER_WAIT_TIME); ++ } ++ else ++ { ++ //pTS->RxIndicateState = RXTS_INDICATE_IDLE; ++ } ++*/ ++ //_exit_critical_ex(&ppending_recvframe_queue->lock, &irql); ++ ++ //return _TRUE; ++ return bPktInBuf; ++ ++} ++ ++ ++static int recv_indicatepkt_reorder(_adapter *padapter, union recv_frame *prframe) ++{ ++ _irqL irql; ++ int retval = _SUCCESS; ++ struct recv_priv *precvpriv = &padapter->recvpriv; ++ struct rx_pkt_attrib *pattrib = &prframe->u.hdr.attrib; ++ struct recv_reorder_ctrl *preorder_ctrl = prframe->u.hdr.preorder_ctrl; ++ _queue *ppending_recvframe_queue = &preorder_ctrl->pending_recvframe_queue; ++ ++ if(!pattrib->amsdu) ++ { ++ //s1. ++ wlanhdr_to_ethhdr(prframe); ++ ++ if(pattrib->qos !=1 /*|| pattrib->priority!=0 || IS_MCAST(pattrib->ra)*/) ++ { ++ if ((padapter->bDriverStopped == _FALSE) && ++ (padapter->bSurpriseRemoved == _FALSE)) ++ { ++ RT_TRACE(_module_rtl871x_recv_c_, _drv_alert_, ("@@@@ recv_indicatepkt_reorder -recv_func recv_indicatepkt\n" )); ++ ++ rtw_recv_indicatepkt(padapter, prframe); ++ return _SUCCESS; ++ ++ } ++ ++ #ifdef DBG_RX_DROP_FRAME ++ DBG_871X("DBG_RX_DROP_FRAME %s pattrib->qos !=1\n", __FUNCTION__); ++ #endif ++ ++ return _FAIL; ++ ++ } ++ ++ if (preorder_ctrl->enable == _FALSE) ++ { ++ //indicate this recv_frame ++ preorder_ctrl->indicate_seq = pattrib->seq_num; ++ #ifdef DBG_RX_SEQ ++ DBG_871X("DBG_RX_SEQ %s:%d IndicateSeq: %d, NewSeq: %d\n", __FUNCTION__, __LINE__, ++ preorder_ctrl->indicate_seq, pattrib->seq_num); ++ #endif ++ ++ rtw_recv_indicatepkt(padapter, prframe); ++ ++ preorder_ctrl->indicate_seq = (preorder_ctrl->indicate_seq + 1)%4096; ++ #ifdef DBG_RX_SEQ ++ DBG_871X("DBG_RX_SEQ %s:%d IndicateSeq: %d, NewSeq: %d\n", __FUNCTION__, __LINE__, ++ preorder_ctrl->indicate_seq, pattrib->seq_num); ++ #endif ++ ++ return _SUCCESS; ++ } ++ ++#ifndef CONFIG_RECV_REORDERING_CTRL ++ //indicate this recv_frame ++ rtw_recv_indicatepkt(padapter, prframe); ++ return _SUCCESS; ++#endif ++ ++ } ++ else if(pattrib->amsdu==1) //temp filter -> means didn't support A-MSDUs in a A-MPDU ++ { ++ if (preorder_ctrl->enable == _FALSE) ++ { ++ preorder_ctrl->indicate_seq = pattrib->seq_num; ++ #ifdef DBG_RX_SEQ ++ DBG_871X("DBG_RX_SEQ %s:%d IndicateSeq: %d, NewSeq: %d\n", __FUNCTION__, __LINE__, ++ preorder_ctrl->indicate_seq, pattrib->seq_num); ++ #endif ++ ++ retval = amsdu_to_msdu(padapter, prframe); ++ ++ preorder_ctrl->indicate_seq = (preorder_ctrl->indicate_seq + 1)%4096; ++ #ifdef DBG_RX_SEQ ++ DBG_871X("DBG_RX_SEQ %s:%d IndicateSeq: %d, NewSeq: %d\n", __FUNCTION__, __LINE__, ++ preorder_ctrl->indicate_seq, pattrib->seq_num); ++ #endif ++ ++ if(retval != _SUCCESS){ ++ #ifdef DBG_RX_DROP_FRAME ++ DBG_871X("DBG_RX_DROP_FRAME %s amsdu_to_msdu fail\n", __FUNCTION__); ++ #endif ++ } ++ ++ return retval; ++ } ++ } ++ else ++ { ++ ++ } ++ ++ _enter_critical_bh(&ppending_recvframe_queue->lock, &irql); ++ ++ RT_TRACE(_module_rtl871x_recv_c_, _drv_notice_, ++ ("recv_indicatepkt_reorder: indicate=%d seq=%d\n", ++ preorder_ctrl->indicate_seq, pattrib->seq_num)); ++ ++ //s2. check if winstart_b(indicate_seq) needs to been updated ++ if(!check_indicate_seq(preorder_ctrl, pattrib->seq_num)) ++ { ++ //pHTInfo->RxReorderDropCounter++; ++ //ReturnRFDList(Adapter, pRfd); ++ //RT_TRACE(COMP_RX_REORDER, DBG_TRACE, ("RxReorderIndicatePacket() ==> Packet Drop!!\n")); ++ //_exit_critical_ex(&ppending_recvframe_queue->lock, &irql); ++ //return _FAIL; ++ ++ #ifdef DBG_RX_DROP_FRAME ++ DBG_871X("DBG_RX_DROP_FRAME %s check_indicate_seq fail\n", __FUNCTION__); ++ #endif ++ goto _err_exit; ++ } ++ ++ ++ //s3. Insert all packet into Reorder Queue to maintain its ordering. ++ if(!enqueue_reorder_recvframe(preorder_ctrl, prframe)) ++ { ++ //DbgPrint("recv_indicatepkt_reorder, enqueue_reorder_recvframe fail!\n"); ++ //_exit_critical_ex(&ppending_recvframe_queue->lock, &irql); ++ //return _FAIL; ++ #ifdef DBG_RX_DROP_FRAME ++ DBG_871X("DBG_RX_DROP_FRAME %s enqueue_reorder_recvframe fail\n", __FUNCTION__); ++ #endif ++ goto _err_exit; ++ } ++ ++ ++ //s4. ++ // Indication process. ++ // After Packet dropping and Sliding Window shifting as above, we can now just indicate the packets ++ // with the SeqNum smaller than latest WinStart and buffer other packets. ++ // ++ // For Rx Reorder condition: ++ // 1. All packets with SeqNum smaller than WinStart => Indicate ++ // 2. All packets with SeqNum larger than or equal to WinStart => Buffer it. ++ // ++ ++ //recv_indicatepkts_in_order(padapter, preorder_ctrl, _TRUE); ++ if(recv_indicatepkts_in_order(padapter, preorder_ctrl, _FALSE)==_TRUE) ++ { ++ _set_timer(&preorder_ctrl->reordering_ctrl_timer, REORDER_WAIT_TIME); ++ _exit_critical_bh(&ppending_recvframe_queue->lock, &irql); ++ } ++ else ++ { ++ _exit_critical_bh(&ppending_recvframe_queue->lock, &irql); ++ _cancel_timer_ex(&preorder_ctrl->reordering_ctrl_timer); ++ } ++ ++ ++ return _SUCCESS; ++ ++_err_exit: ++ ++ _exit_critical_bh(&ppending_recvframe_queue->lock, &irql); ++ ++ return _FAIL; ++} ++ ++ ++void rtw_reordering_ctrl_timeout_handler(void *pcontext) ++{ ++ _irqL irql; ++ struct recv_reorder_ctrl *preorder_ctrl = (struct recv_reorder_ctrl *)pcontext; ++ _adapter *padapter = preorder_ctrl->padapter; ++ _queue *ppending_recvframe_queue = &preorder_ctrl->pending_recvframe_queue; ++ ++ ++ if(padapter->bDriverStopped ||padapter->bSurpriseRemoved) ++ { ++ return; ++ } ++ ++ //DBG_8192C("+rtw_reordering_ctrl_timeout_handler()=>\n"); ++ ++ _enter_critical_bh(&ppending_recvframe_queue->lock, &irql); ++ ++ if(recv_indicatepkts_in_order(padapter, preorder_ctrl, _TRUE)==_TRUE) ++ { ++ _set_timer(&preorder_ctrl->reordering_ctrl_timer, REORDER_WAIT_TIME); ++ } ++ ++ _exit_critical_bh(&ppending_recvframe_queue->lock, &irql); ++ ++} ++ ++ ++static int process_recv_indicatepkts(_adapter *padapter, union recv_frame *prframe) ++{ ++ int retval = _SUCCESS; ++ struct recv_priv *precvpriv = &padapter->recvpriv; ++ struct rx_pkt_attrib *pattrib = &prframe->u.hdr.attrib; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ ++#ifdef CONFIG_80211N_HT ++ ++ struct ht_priv *phtpriv = &pmlmepriv->htpriv; ++ ++ if(phtpriv->ht_option==_TRUE) //B/G/N Mode ++ { ++ //prframe->u.hdr.preorder_ctrl = &precvpriv->recvreorder_ctrl[pattrib->priority]; ++ ++ if(recv_indicatepkt_reorder(padapter, prframe)!=_SUCCESS)// including perform A-MPDU Rx Ordering Buffer Control ++ { ++ #ifdef DBG_RX_DROP_FRAME ++ DBG_871X("DBG_RX_DROP_FRAME %s recv_indicatepkt_reorder error!\n", __FUNCTION__); ++ #endif ++ ++ if ((padapter->bDriverStopped == _FALSE) && ++ (padapter->bSurpriseRemoved == _FALSE)) ++ { ++ retval = _FAIL; ++ return retval; ++ } ++ } ++ } ++ else //B/G mode ++#endif ++ { ++ retval=wlanhdr_to_ethhdr (prframe); ++ if(retval != _SUCCESS) ++ { ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("wlanhdr_to_ethhdr: drop pkt \n")); ++ #ifdef DBG_RX_DROP_FRAME ++ DBG_871X("DBG_RX_DROP_FRAME %s wlanhdr_to_ethhdr error!\n", __FUNCTION__); ++ #endif ++ return retval; ++ } ++ ++ if ((padapter->bDriverStopped ==_FALSE)&&( padapter->bSurpriseRemoved==_FALSE)) ++ { ++ //indicate this recv_frame ++ RT_TRACE(_module_rtl871x_recv_c_, _drv_notice_, ("@@@@ process_recv_indicatepkts- recv_func recv_indicatepkt\n" )); ++ rtw_recv_indicatepkt(padapter, prframe); ++ ++ ++ } ++ else ++ { ++ RT_TRACE(_module_rtl871x_recv_c_, _drv_notice_, ("@@@@ process_recv_indicatepkts- recv_func free_indicatepkt\n" )); ++ ++ RT_TRACE(_module_rtl871x_recv_c_, _drv_notice_, ("recv_func:bDriverStopped(%d) OR bSurpriseRemoved(%d)", padapter->bDriverStopped, padapter->bSurpriseRemoved)); ++ retval = _FAIL; ++ return retval; ++ } ++ ++ } ++ ++ return retval; ++ ++} ++ ++ ++static int recv_func(_adapter *padapter, void *pcontext) ++{ ++ struct rx_pkt_attrib *pattrib; ++ union recv_frame *prframe, *orig_prframe; ++ int retval = _SUCCESS; ++ _queue *pfree_recv_queue = &padapter->recvpriv.free_recv_queue; ++ struct recv_priv *precvpriv = &padapter->recvpriv; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++#ifdef CONFIG_TDLS ++ u8 *psnap_type, *pcategory; ++#endif ++ ++ prframe = (union recv_frame *)pcontext; ++ orig_prframe = prframe; ++ ++ pattrib = &prframe->u.hdr.attrib; ++ ++#ifdef CONFIG_MP_INCLUDED ++ if ((check_fwstate(pmlmepriv, WIFI_MP_STATE) == _TRUE))//&&(padapter->mppriv.check_mp_pkt == 0)) ++ { ++ if (pattrib->crc_err == 1) ++ padapter->mppriv.rx_crcerrpktcount++; ++ else ++ padapter->mppriv.rx_pktcount++; ++ ++ if (check_fwstate(pmlmepriv, WIFI_MP_LPBK_STATE) == _FALSE) { ++ RT_TRACE(_module_rtl871x_recv_c_, _drv_alert_, ("MP - Not in loopback mode , drop pkt \n")); ++ retval = _FAIL; ++ rtw_free_recvframe(orig_prframe, pfree_recv_queue);//free this recv_frame ++ goto _exit_recv_func; ++ } ++ } ++#endif ++ ++ //check the frame crtl field and decache ++ retval = validate_recv_frame(padapter, prframe); ++ if (retval != _SUCCESS) ++ { ++ RT_TRACE(_module_rtl871x_recv_c_, _drv_info_, ("recv_func: validate_recv_frame fail! drop pkt\n")); ++ rtw_free_recvframe(orig_prframe, pfree_recv_queue);//free this recv_frame ++ goto _exit_recv_func; ++ } ++ // DATA FRAME ++ rtw_led_control(padapter, LED_CTL_RX); ++ ++ prframe = decryptor(padapter, prframe); ++ if (prframe == NULL) { ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("decryptor: drop pkt\n")); ++ #ifdef DBG_RX_DROP_FRAME ++ DBG_871X("DBG_RX_DROP_FRAME %s decryptor: drop pkt\n", __FUNCTION__); ++ #endif ++ retval = _FAIL; ++ goto _recv_data_drop; ++ } ++ ++#ifdef CONFIG_TDLS ++ //check TDLS frame ++ psnap_type = get_recvframe_data(orig_prframe); ++ psnap_type+=pattrib->hdrlen + pattrib->iv_len+SNAP_SIZE; ++ //[+2]: ether_type, [+1]: payload type ++ pcategory = psnap_type+2+1; ++ ++ if((_rtw_memcmp(psnap_type, SNAP_ETH_TYPE_TDLS, 2))&&((*pcategory==0x0c))){ ++ retval = OnTDLS(padapter, prframe); //all of functions will return _FAIL ++ goto _recv_data_drop; ++ } ++#endif ++ ++ prframe = recvframe_chk_defrag(padapter, prframe); ++ if(prframe==NULL) { ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("recvframe_chk_defrag: drop pkt\n")); ++ #ifdef DBG_RX_DROP_FRAME ++ DBG_871X("DBG_RX_DROP_FRAME %s recvframe_chk_defrag: drop pkt\n", __FUNCTION__); ++ #endif ++ goto _recv_data_drop; ++ } ++ ++ prframe=portctrl(padapter, prframe); ++ if (prframe == NULL) { ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("portctrl: drop pkt \n")); ++ #ifdef DBG_RX_DROP_FRAME ++ DBG_871X("DBG_RX_DROP_FRAME %s portctrl: drop pkt\n", __FUNCTION__); ++ #endif ++ retval = _FAIL; ++ goto _recv_data_drop; ++ } ++ ++ count_rx_stats(padapter, prframe, NULL); ++ ++#ifdef CONFIG_80211N_HT ++ ++ retval = process_recv_indicatepkts(padapter, prframe); ++ if (retval != _SUCCESS) ++ { ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("recv_func: process_recv_indicatepkts fail! \n")); ++ #ifdef DBG_RX_DROP_FRAME ++ DBG_871X("DBG_RX_DROP_FRAME %s recv_func: process_recv_indicatepkts fail!\n", __FUNCTION__); ++ #endif ++ rtw_free_recvframe(orig_prframe, pfree_recv_queue);//free this recv_frame ++ goto _recv_data_drop; ++ } ++ ++#else ++ ++ if (!pattrib->amsdu) ++ { ++ retval = wlanhdr_to_ethhdr (prframe); ++ if (retval != _SUCCESS) ++ { ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("wlanhdr_to_ethhdr: drop pkt \n")); ++ #ifdef DBG_RX_DROP_FRAME ++ DBG_871X("DBG_RX_DROP_FRAME %s wlanhdr_to_ethhdr: drop pkt\n", __FUNCTION__); ++ #endif ++ rtw_free_recvframe(orig_prframe, pfree_recv_queue);//free this recv_frame ++ goto _recv_data_drop; ++ } ++ ++ if ((padapter->bDriverStopped == _FALSE) && (padapter->bSurpriseRemoved == _FALSE)) ++ { ++ RT_TRACE(_module_rtl871x_recv_c_, _drv_alert_, ("@@@@ recv_func: recv_func rtw_recv_indicatepkt\n" )); ++ //indicate this recv_frame ++ retval = rtw_recv_indicatepkt(padapter, prframe); ++ if (retval != _SUCCESS) ++ { ++ #ifdef DBG_RX_DROP_FRAME ++ DBG_871X("DBG_RX_DROP_FRAME %s rtw_recv_indicatepkt fail!\n", __FUNCTION__); ++ #endif ++ goto _recv_data_drop; ++ } ++ } ++ else ++ { ++ RT_TRACE(_module_rtl871x_recv_c_, _drv_alert_, ("@@@@ recv_func: rtw_free_recvframe\n" )); ++ RT_TRACE(_module_rtl871x_recv_c_, _drv_debug_, ("recv_func:bDriverStopped(%d) OR bSurpriseRemoved(%d)", padapter->bDriverStopped, padapter->bSurpriseRemoved)); ++ #ifdef DBG_RX_DROP_FRAME ++ DBG_871X("DBG_RX_DROP_FRAME %s ecv_func:bDriverStopped(%d) OR bSurpriseRemoved(%d)\n", __FUNCTION__, ++ padapter->bDriverStopped, padapter->bSurpriseRemoved); ++ #endif ++ retval = _FAIL; ++ rtw_free_recvframe(orig_prframe, pfree_recv_queue); //free this recv_frame ++ } ++ ++ } ++ else if(pattrib->amsdu==1) ++ { ++ ++ retval = amsdu_to_msdu(padapter, prframe); ++ if(retval != _SUCCESS) ++ { ++ #ifdef DBG_RX_DROP_FRAME ++ DBG_871X("DBG_RX_DROP_FRAME %s amsdu_to_msdu fail\n", __FUNCTION__); ++ #endif ++ rtw_free_recvframe(orig_prframe, pfree_recv_queue); ++ goto _recv_data_drop; ++ } ++ } ++ else ++ { ++ #ifdef DBG_RX_DROP_FRAME ++ DBG_871X("DBG_RX_DROP_FRAME %s what is this condition??\n", __FUNCTION__); ++ #endif ++ } ++#endif ++_recv_data_drop: ++ precvpriv->rx_drop++; ++ ++_exit_recv_func: ++ ++ return retval; ++} ++ ++ ++s32 rtw_recv_entry(union recv_frame *precvframe) ++{ ++ _adapter *padapter; ++ struct recv_priv *precvpriv; ++ //struct mlme_priv *pmlmepriv ; ++ //struct dvobj_priv *pdev; ++ //u8 *phead, *pdata, *ptail,*pend; ++ ++ //_queue *pfree_recv_queue, *ppending_recv_queue; ++ //u8 blk_mode = _FALSE; ++ s32 ret=_SUCCESS; ++ //struct intf_hdl * pintfhdl; ++ ++_func_enter_; ++ ++// RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("+rtw_recv_entry\n")); ++ ++ padapter = precvframe->u.hdr.adapter; ++ //pintfhdl = &padapter->iopriv.intf; ++ ++ //pdev=&padapter->dvobjpriv; ++ //pmlmepriv = &padapter->mlmepriv; ++ precvpriv = &padapter->recvpriv; ++ //pfree_recv_queue = &precvpriv->free_recv_queue; ++ //ppending_recv_queue = &precvpriv->recv_pending_queue; ++ ++ //phead = precvframe->u.hdr.rx_head; ++ //pdata = precvframe->u.hdr.rx_data; ++ //ptail = precvframe->u.hdr.rx_tail; ++ //pend = precvframe->u.hdr.rx_end; ++ ++ //rtw_led_control(padapter, LED_CTL_RX); ++ ++#ifdef CONFIG_SDIO_HCI ++ if (precvpriv->free_recvframe_cnt <= 1) ++ goto _recv_entry_drop; ++#endif ++ ++#ifdef CONFIG_RECV_THREAD_MODE ++ if (_rtw_queue_empty(ppending_recv_queue) == _TRUE) ++ { ++ //enqueue_recvframe_usb(precvframe, ppending_recv_queue);//enqueue to recv_pending_queue ++ rtw_enqueue_recvframe(precvframe, ppending_recv_queue); ++ _rtw_up_sema(&precvpriv->recv_sema); ++ } ++ else ++ { ++ //enqueue_recvframe_usb(precvframe, ppending_recv_queue);//enqueue to recv_pending_queue ++ rtw_enqueue_recvframe(precvframe, ppending_recv_queue); ++ } ++#else ++ if ((ret = recv_func(padapter, precvframe)) == _FAIL) ++ { ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("rtw_recv_entry: recv_func return fail!!!\n")); ++ goto _recv_entry_drop; ++ } ++#endif ++ ++ precvpriv->rx_pkts++; ++ ++_func_exit_; ++ ++ return ret; ++ ++_recv_entry_drop: ++ ++ ++ //precvpriv->rx_drop++; ++ ++#ifdef CONFIG_MP_INCLUDED ++ padapter->mppriv.rx_pktloss = precvpriv->rx_drop; ++#endif ++ ++ //RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("_recv_entry_drop\n")); ++ ++_func_exit_; ++ ++ return ret; ++} ++ ++#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS ++void rtw_signal_stat_timer_hdl(RTW_TIMER_HDL_ARGS){ ++ _adapter *adapter = (_adapter *)FunctionContext; ++ struct recv_priv *recvpriv = &adapter->recvpriv; ++ ++ u32 tmp_s, tmp_q; ++ u8 avg_signal_strength = 0; ++ u8 avg_signal_qual = 0; ++ u32 num_signal_strength = 0; ++ u32 num_signal_qual = 0; ++ u8 _alpha = 3; // this value is based on converging_constant = 5000 and sampling_interval = 1000 ++ ++ if(adapter->recvpriv.is_signal_dbg) { ++ //update the user specific value, signal_strength_dbg, to signal_strength, rssi ++ adapter->recvpriv.signal_strength= adapter->recvpriv.signal_strength_dbg; ++ adapter->recvpriv.rssi=(s8)translate_percentage_to_dbm((u8)adapter->recvpriv.signal_strength_dbg); ++ } else { ++ ++ if(recvpriv->signal_strength_data.update_req == 0) {// update_req is clear, means we got rx ++ avg_signal_strength = recvpriv->signal_strength_data.avg_val; ++ avg_signal_qual = recvpriv->signal_qual_data.avg_val; ++ } ++ ++ if(recvpriv->signal_qual_data.update_req == 0) {// update_req is clear, means we got rx ++ num_signal_strength = recvpriv->signal_strength_data.total_num; ++ num_signal_qual = recvpriv->signal_qual_data.total_num; ++ } ++ ++ // after avg_vals are accquired, we can re-stat the signal values ++ recvpriv->signal_strength_data.update_req = 1; ++ recvpriv->signal_qual_data.update_req = 1; ++ ++ //update value of signal_strength, rssi, signal_qual ++ if(check_fwstate(&adapter->mlmepriv, _FW_UNDER_SURVEY) == _FALSE) { ++ tmp_s = (avg_signal_strength+(_alpha-1)*recvpriv->signal_strength); ++ if(tmp_s %_alpha) ++ tmp_s = tmp_s/_alpha + 1; ++ else ++ tmp_s = tmp_s/_alpha; ++ if(tmp_s>100) ++ tmp_s = 100; ++ ++ tmp_q = (avg_signal_qual+(_alpha-1)*recvpriv->signal_qual); ++ if(tmp_q %_alpha) ++ tmp_q = tmp_q/_alpha + 1; ++ else ++ tmp_q = tmp_q/_alpha; ++ if(tmp_q>100) ++ tmp_q = 100; ++ ++ recvpriv->signal_strength = tmp_s; ++ recvpriv->rssi = (s8)translate_percentage_to_dbm(tmp_s); ++ recvpriv->signal_qual = tmp_q; ++ ++ #if defined(DBG_RX_SIGNAL_DISPLAY_PROCESSING) && 1 ++ DBG_871X("%s signal_strength:%3u, rssi:%3d, signal_qual:%3u" ++ ", num_signal_strength:%u, num_signal_qual:%u" ++ "\n" ++ , __FUNCTION__ ++ , recvpriv->signal_strength ++ , recvpriv->rssi ++ , recvpriv->signal_qual ++ , num_signal_strength, num_signal_qual ++ ); ++ #endif ++ } ++ } ++ rtw_set_signal_stat_timer(recvpriv); ++ ++} ++#endif //CONFIG_NEW_SIGNAL_STAT_PROCESS ++ ++ ++ +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/core/rtw_rf.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/core/rtw_rf.c 2013-07-26 19:36:05.000000000 +0000 +@@ -0,0 +1,96 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ++******************************************************************************/ ++#define _RTW_RF_C_ ++ ++#include ++#include ++#include ++#include ++#include ++ ++ ++struct ch_freq { ++ u32 channel; ++ u32 frequency; ++}; ++ ++struct ch_freq ch_freq_map[] = { ++ {1, 2412},{2, 2417},{3, 2422},{4, 2427},{5, 2432}, ++ {6, 2437},{7, 2442},{8, 2447},{9, 2452},{10, 2457}, ++ {11, 2462},{12, 2467},{13, 2472},{14, 2484}, ++ /* UNII */ ++ {36, 5180},{40, 5200},{44, 5220},{48, 5240},{52, 5260}, ++ {56, 5280},{60, 5300},{64, 5320},{149, 5745},{153, 5765}, ++ {157, 5785},{161, 5805},{165, 5825},{167, 5835},{169, 5845}, ++ {171, 5855},{173, 5865}, ++ /* HiperLAN2 */ ++ {100, 5500},{104, 5520},{108, 5540},{112, 5560},{116, 5580}, ++ {120, 5600},{124, 5620},{128, 5640},{132, 5660},{136, 5680}, ++ {140, 5700}, ++ /* Japan MMAC */ ++ {34, 5170},{38, 5190},{42, 5210},{46, 5230}, ++ /* Japan */ ++ {184, 4920},{188, 4940},{192, 4960},{196, 4980}, ++ {208, 5040},/* Japan, means J08 */ ++ {212, 5060},/* Japan, means J12 */ ++ {216, 5080},/* Japan, means J16 */ ++}; ++ ++int ch_freq_map_num = (sizeof(ch_freq_map) / sizeof(struct ch_freq)); ++ ++u32 rtw_ch2freq(u32 channel) ++{ ++ u8 i; ++ u32 freq = 0; ++ ++ for (i = 0; i < ch_freq_map_num; i++) ++ { ++ if (channel == ch_freq_map[i].channel) ++ { ++ freq = ch_freq_map[i].frequency; ++ break; ++ } ++ } ++ if (i == ch_freq_map_num) ++ freq = 2412; ++ ++ return freq; ++} ++ ++u32 rtw_freq2ch(u32 freq) ++{ ++ u8 i; ++ u32 ch = 0; ++ ++ for (i = 0; i < ch_freq_map_num; i++) ++ { ++ if (freq == ch_freq_map[i].frequency) ++ { ++ ch = ch_freq_map[i].channel; ++ break; ++ } ++ } ++ if (i == ch_freq_map_num) ++ ch = 1; ++ ++ return ch; ++} ++ +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/core/rtw_security.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/core/rtw_security.c 2013-07-26 19:36:05.000000000 +0000 +@@ -0,0 +1,2831 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ++******************************************************************************/ ++#define _RTW_SECURITY_C_ ++ ++#include ++#include ++#include ++#include ++#include ++ ++ ++//=====WEP related===== ++ ++#define CRC32_POLY 0x04c11db7 ++ ++struct arc4context ++{ ++ u32 x; ++ u32 y; ++ u8 state[256]; ++}; ++ ++ ++static void arcfour_init(struct arc4context *parc4ctx, u8 * key,u32 key_len) ++{ ++ u32 t, u; ++ u32 keyindex; ++ u32 stateindex; ++ u8 * state; ++ u32 counter; ++_func_enter_; ++ state = parc4ctx->state; ++ parc4ctx->x = 0; ++ parc4ctx->y = 0; ++ for (counter = 0; counter < 256; counter++) ++ state[counter] = (u8)counter; ++ keyindex = 0; ++ stateindex = 0; ++ for (counter = 0; counter < 256; counter++) ++ { ++ t = state[counter]; ++ stateindex = (stateindex + key[keyindex] + t) & 0xff; ++ u = state[stateindex]; ++ state[stateindex] = (u8)t; ++ state[counter] = (u8)u; ++ if (++keyindex >= key_len) ++ keyindex = 0; ++ } ++_func_exit_; ++} ++static u32 arcfour_byte( struct arc4context *parc4ctx) ++{ ++ u32 x; ++ u32 y; ++ u32 sx, sy; ++ u8 * state; ++_func_enter_; ++ state = parc4ctx->state; ++ x = (parc4ctx->x + 1) & 0xff; ++ sx = state[x]; ++ y = (sx + parc4ctx->y) & 0xff; ++ sy = state[y]; ++ parc4ctx->x = x; ++ parc4ctx->y = y; ++ state[y] = (u8)sx; ++ state[x] = (u8)sy; ++_func_exit_; ++ return state[(sx + sy) & 0xff]; ++} ++ ++ ++static void arcfour_encrypt( struct arc4context *parc4ctx, ++ u8 * dest, ++ u8 * src, ++ u32 len) ++{ ++ u32 i; ++_func_enter_; ++ for (i = 0; i < len; i++) ++ dest[i] = src[i] ^ (unsigned char)arcfour_byte(parc4ctx); ++_func_exit_; ++} ++ ++static sint bcrc32initialized = 0; ++static u32 crc32_table[256]; ++ ++ ++static u8 crc32_reverseBit( u8 data) ++{ ++ return( (u8)((data<<7)&0x80) | ((data<<5)&0x40) | ((data<<3)&0x20) | ((data<<1)&0x10) | ((data>>1)&0x08) | ((data>>3)&0x04) | ((data>>5)&0x02) | ((data>>7)&0x01) ); ++} ++ ++static void crc32_init(void) ++{ ++_func_enter_; ++ if (bcrc32initialized == 1) ++ goto exit; ++ else{ ++ sint i, j; ++ u32 c; ++ u8 *p=(u8 *)&c, *p1; ++ u8 k; ++ ++ c = 0x12340000; ++ ++ for (i = 0; i < 256; ++i) ++ { ++ k = crc32_reverseBit((u8)i); ++ for (c = ((u32)k) << 24, j = 8; j > 0; --j){ ++ c = c & 0x80000000 ? (c << 1) ^ CRC32_POLY : (c << 1); ++ } ++ p1 = (u8 *)&crc32_table[i]; ++ ++ p1[0] = crc32_reverseBit(p[3]); ++ p1[1] = crc32_reverseBit(p[2]); ++ p1[2] = crc32_reverseBit(p[1]); ++ p1[3] = crc32_reverseBit(p[0]); ++ } ++ bcrc32initialized= 1; ++ } ++exit: ++_func_exit_; ++} ++ ++static u32 getcrc32(u8 *buf, sint len) ++{ ++ u8 *p; ++ u32 crc; ++_func_enter_; ++ if (bcrc32initialized == 0) crc32_init(); ++ ++ crc = 0xffffffff; /* preload shift register, per CRC-32 spec */ ++ ++ for (p = buf; len > 0; ++p, --len) ++ { ++ crc = crc32_table[ (crc ^ *p) & 0xff] ^ (crc >> 8); ++ } ++_func_exit_; ++ return ~crc; /* transmit complement, per CRC-32 spec */ ++} ++ ++ ++/* ++ Need to consider the fragment situation ++*/ ++void rtw_wep_encrypt(_adapter *padapter, u8 *pxmitframe) ++{ // exclude ICV ++ ++ unsigned char crc[4]; ++ struct arc4context mycontext; ++ ++ sint curfragnum,length; ++ u32 keylength; ++ ++ u8 *pframe, *payload,*iv; //,*wepkey ++ u8 wepkey[16]; ++ struct pkt_attrib *pattrib = &((struct xmit_frame*)pxmitframe)->attrib; ++ struct security_priv *psecuritypriv=&padapter->securitypriv; ++ struct xmit_priv *pxmitpriv=&padapter->xmitpriv; ++ ++_func_enter_; ++ ++ ++ if(((struct xmit_frame*)pxmitframe)->buf_addr==NULL) ++ return; ++ ++#ifdef CONFIG_USB_TX_AGGREGATION ++ pframe = ((struct xmit_frame*)pxmitframe)->buf_addr + TXDESC_SIZE + ++ (((struct xmit_frame*)pxmitframe)->pkt_offset * PACKET_OFFSET_SZ); ++#else ++ pframe = ((struct xmit_frame*)pxmitframe)->buf_addr + TXDESC_OFFSET; ++#endif ++ ++ //start to encrypt each fragment ++ if((pattrib->encrypt==_WEP40_)||(pattrib->encrypt==_WEP104_)) ++ { ++ keylength=psecuritypriv->dot11DefKeylen[psecuritypriv->dot11PrivacyKeyIndex]; ++ ++ for(curfragnum=0;curfragnumnr_frags;curfragnum++) ++ { ++ iv=pframe+pattrib->hdrlen; ++ _rtw_memcpy(&wepkey[0], iv, 3); ++ _rtw_memcpy(&wepkey[3], &psecuritypriv->dot11DefKey[psecuritypriv->dot11PrivacyKeyIndex].skey[0],keylength); ++ payload=pframe+pattrib->iv_len+pattrib->hdrlen; ++ ++ if((curfragnum+1)==pattrib->nr_frags) ++ { //the last fragment ++ ++ length=pattrib->last_txcmdsz-pattrib->hdrlen-pattrib->iv_len- pattrib->icv_len; ++ ++ *((unsigned long *)crc)=cpu_to_le32(getcrc32(payload,length)); ++ ++ arcfour_init(&mycontext, wepkey,3+keylength); ++ arcfour_encrypt(&mycontext, payload, payload, length); ++ arcfour_encrypt(&mycontext, payload+length, crc, 4); ++ ++ } ++ else ++ { ++ length=pxmitpriv->frag_len-pattrib->hdrlen-pattrib->iv_len-pattrib->icv_len ; ++ *((unsigned long *)crc)=cpu_to_le32(getcrc32(payload,length)); ++ arcfour_init(&mycontext, wepkey,3+keylength); ++ arcfour_encrypt(&mycontext, payload, payload, length); ++ arcfour_encrypt(&mycontext, payload+length, crc, 4); ++ ++ pframe+=pxmitpriv->frag_len; ++ pframe=(u8 *)RND4((SIZE_PTR)(pframe)); ++ ++ } ++ ++ } ++ ++ } ++ ++_func_exit_; ++ ++} ++ ++void rtw_wep_decrypt(_adapter *padapter, u8 *precvframe) ++{ ++ // exclude ICV ++ u8 crc[4]; ++ struct arc4context mycontext; ++ sint length; ++ u32 keylength; ++ u8 *pframe, *payload,*iv,wepkey[16]; ++ u8 keyindex; ++ struct rx_pkt_attrib *prxattrib = &(((union recv_frame*)precvframe)->u.hdr.attrib); ++ struct security_priv *psecuritypriv=&padapter->securitypriv; ++ ++_func_enter_; ++ ++ pframe=(unsigned char *)((union recv_frame*)precvframe)->u.hdr.rx_data; ++ ++ //start to decrypt recvframe ++ if((prxattrib->encrypt==_WEP40_)||(prxattrib->encrypt==_WEP104_)) ++ { ++ iv=pframe+prxattrib->hdrlen; ++ //keyindex=(iv[3]&0x3); ++ keyindex = prxattrib->key_index; ++ keylength=psecuritypriv->dot11DefKeylen[keyindex]; ++ _rtw_memcpy(&wepkey[0], iv, 3); ++ //_rtw_memcpy(&wepkey[3], &psecuritypriv->dot11DefKey[psecuritypriv->dot11PrivacyKeyIndex].skey[0],keylength); ++ _rtw_memcpy(&wepkey[3], &psecuritypriv->dot11DefKey[keyindex].skey[0],keylength); ++ length= ((union recv_frame *)precvframe)->u.hdr.len-prxattrib->hdrlen-prxattrib->iv_len; ++ ++ payload=pframe+prxattrib->iv_len+prxattrib->hdrlen; ++ ++ //decrypt payload include icv ++ arcfour_init(&mycontext, wepkey,3+keylength); ++ arcfour_encrypt(&mycontext, payload, payload, length); ++ ++ //calculate icv and compare the icv ++ *((unsigned long *)crc)=le32_to_cpu(getcrc32(payload,length-4)); ++ ++ if(crc[3]!=payload[length-1] || crc[2]!=payload[length-2] || crc[1]!=payload[length-3] || crc[0]!=payload[length-4]) ++ { ++ RT_TRACE(_module_rtl871x_security_c_,_drv_err_,("rtw_wep_decrypt:icv error crc[3](%x)!=payload[length-1](%x) || crc[2](%x)!=payload[length-2](%x) || crc[1](%x)!=payload[length-3](%x) || crc[0](%x)!=payload[length-4](%x)\n", ++ crc[3],payload[length-1],crc[2],payload[length-2],crc[1],payload[length-3],crc[0],payload[length-4])); ++ } ++ ++ } ++ ++_func_exit_; ++ ++ return; ++ ++} ++ ++//3 =====TKIP related===== ++ ++static u32 secmicgetuint32( u8 * p ) ++// Convert from Byte[] to Us4Byte32 in a portable way ++{ ++ s32 i; ++ u32 res = 0; ++_func_enter_; ++ for( i=0; i<4; i++ ) ++ { ++ res |= ((u32)(*p++)) << (8*i); ++ } ++_func_exit_; ++ return res; ++} ++ ++static void secmicputuint32( u8 * p, u32 val ) ++// Convert from Us4Byte32 to Byte[] in a portable way ++{ ++ long i; ++_func_enter_; ++ for( i=0; i<4; i++ ) ++ { ++ *p++ = (u8) (val & 0xff); ++ val >>= 8; ++ } ++_func_exit_; ++} ++ ++static void secmicclear(struct mic_data *pmicdata) ++{ ++// Reset the state to the empty message. ++_func_enter_; ++ pmicdata->L = pmicdata->K0; ++ pmicdata->R = pmicdata->K1; ++ pmicdata->nBytesInM = 0; ++ pmicdata->M = 0; ++_func_exit_; ++} ++ ++void rtw_secmicsetkey(struct mic_data *pmicdata, u8 * key ) ++{ ++ // Set the key ++_func_enter_; ++ pmicdata->K0 = secmicgetuint32( key ); ++ pmicdata->K1 = secmicgetuint32( key + 4 ); ++ // and reset the message ++ secmicclear(pmicdata); ++_func_exit_; ++} ++ ++void rtw_secmicappendbyte(struct mic_data *pmicdata, u8 b ) ++{ ++_func_enter_; ++ // Append the byte to our word-sized buffer ++ pmicdata->M |= ((unsigned long)b) << (8*pmicdata->nBytesInM); ++ pmicdata->nBytesInM++; ++ // Process the word if it is full. ++ if( pmicdata->nBytesInM >= 4 ) ++ { ++ pmicdata->L ^= pmicdata->M; ++ pmicdata->R ^= ROL32( pmicdata->L, 17 ); ++ pmicdata->L += pmicdata->R; ++ pmicdata->R ^= ((pmicdata->L & 0xff00ff00) >> 8) | ((pmicdata->L & 0x00ff00ff) << 8); ++ pmicdata->L += pmicdata->R; ++ pmicdata->R ^= ROL32( pmicdata->L, 3 ); ++ pmicdata->L += pmicdata->R; ++ pmicdata->R ^= ROR32( pmicdata->L, 2 ); ++ pmicdata->L += pmicdata->R; ++ // Clear the buffer ++ pmicdata->M = 0; ++ pmicdata->nBytesInM = 0; ++ } ++_func_exit_; ++} ++ ++void rtw_secmicappend(struct mic_data *pmicdata, u8 * src, u32 nbytes ) ++{ ++_func_enter_; ++ // This is simple ++ while( nbytes > 0 ) ++ { ++ rtw_secmicappendbyte(pmicdata, *src++ ); ++ nbytes--; ++ } ++_func_exit_; ++} ++ ++void rtw_secgetmic(struct mic_data *pmicdata, u8 * dst ) ++{ ++_func_enter_; ++ // Append the minimum padding ++ rtw_secmicappendbyte(pmicdata, 0x5a ); ++ rtw_secmicappendbyte(pmicdata, 0 ); ++ rtw_secmicappendbyte(pmicdata, 0 ); ++ rtw_secmicappendbyte(pmicdata, 0 ); ++ rtw_secmicappendbyte(pmicdata, 0 ); ++ // and then zeroes until the length is a multiple of 4 ++ while( pmicdata->nBytesInM != 0 ) ++ { ++ rtw_secmicappendbyte(pmicdata, 0 ); ++ } ++ // The appendByte function has already computed the result. ++ secmicputuint32( dst, pmicdata->L ); ++ secmicputuint32( dst+4, pmicdata->R ); ++ // Reset to the empty message. ++ secmicclear(pmicdata); ++_func_exit_; ++} ++ ++ ++void rtw_seccalctkipmic(u8 * key,u8 *header,u8 *data,u32 data_len,u8 *mic_code, u8 pri) ++{ ++ ++ struct mic_data micdata; ++ u8 priority[4]={0x0,0x0,0x0,0x0}; ++_func_enter_; ++ rtw_secmicsetkey(&micdata, key); ++ priority[0]=pri; ++ ++ /* Michael MIC pseudo header: DA, SA, 3 x 0, Priority */ ++ if(header[1]&1){ //ToDS==1 ++ rtw_secmicappend(&micdata, &header[16], 6); //DA ++ if(header[1]&2) //From Ds==1 ++ rtw_secmicappend(&micdata, &header[24], 6); ++ else ++ rtw_secmicappend(&micdata, &header[10], 6); ++ } ++ else{ //ToDS==0 ++ rtw_secmicappend(&micdata, &header[4], 6); //DA ++ if(header[1]&2) //From Ds==1 ++ rtw_secmicappend(&micdata, &header[16], 6); ++ else ++ rtw_secmicappend(&micdata, &header[10], 6); ++ ++ } ++ rtw_secmicappend(&micdata, &priority[0], 4); ++ ++ ++ rtw_secmicappend(&micdata, data, data_len); ++ ++ rtw_secgetmic(&micdata,mic_code); ++_func_exit_; ++} ++ ++ ++ ++ ++/* macros for extraction/creation of unsigned char/unsigned short values */ ++#define RotR1(v16) ((((v16) >> 1) & 0x7FFF) ^ (((v16) & 1) << 15)) ++#define Lo8(v16) ((u8)( (v16) & 0x00FF)) ++#define Hi8(v16) ((u8)(((v16) >> 8) & 0x00FF)) ++#define Lo16(v32) ((u16)( (v32) & 0xFFFF)) ++#define Hi16(v32) ((u16)(((v32) >>16) & 0xFFFF)) ++#define Mk16(hi,lo) ((lo) ^ (((u16)(hi)) << 8)) ++ ++/* select the Nth 16-bit word of the temporal key unsigned char array TK[] */ ++#define TK16(N) Mk16(tk[2*(N)+1],tk[2*(N)]) ++ ++/* S-box lookup: 16 bits --> 16 bits */ ++#define _S_(v16) (Sbox1[0][Lo8(v16)] ^ Sbox1[1][Hi8(v16)]) ++ ++/* fixed algorithm "parameters" */ ++#define PHASE1_LOOP_CNT 8 /* this needs to be "big enough" */ ++#define TA_SIZE 6 /* 48-bit transmitter address */ ++#define TK_SIZE 16 /* 128-bit temporal key */ ++#define P1K_SIZE 10 /* 80-bit Phase1 key */ ++#define RC4_KEY_SIZE 16 /* 128-bit RC4KEY (104 bits unknown) */ ++ ++ ++/* 2-unsigned char by 2-unsigned char subset of the full AES S-box table */ ++static const unsigned short Sbox1[2][256]= /* Sbox for hash (can be in ROM) */ ++{ { ++ 0xC6A5,0xF884,0xEE99,0xF68D,0xFF0D,0xD6BD,0xDEB1,0x9154, ++ 0x6050,0x0203,0xCEA9,0x567D,0xE719,0xB562,0x4DE6,0xEC9A, ++ 0x8F45,0x1F9D,0x8940,0xFA87,0xEF15,0xB2EB,0x8EC9,0xFB0B, ++ 0x41EC,0xB367,0x5FFD,0x45EA,0x23BF,0x53F7,0xE496,0x9B5B, ++ 0x75C2,0xE11C,0x3DAE,0x4C6A,0x6C5A,0x7E41,0xF502,0x834F, ++ 0x685C,0x51F4,0xD134,0xF908,0xE293,0xAB73,0x6253,0x2A3F, ++ 0x080C,0x9552,0x4665,0x9D5E,0x3028,0x37A1,0x0A0F,0x2FB5, ++ 0x0E09,0x2436,0x1B9B,0xDF3D,0xCD26,0x4E69,0x7FCD,0xEA9F, ++ 0x121B,0x1D9E,0x5874,0x342E,0x362D,0xDCB2,0xB4EE,0x5BFB, ++ 0xA4F6,0x764D,0xB761,0x7DCE,0x527B,0xDD3E,0x5E71,0x1397, ++ 0xA6F5,0xB968,0x0000,0xC12C,0x4060,0xE31F,0x79C8,0xB6ED, ++ 0xD4BE,0x8D46,0x67D9,0x724B,0x94DE,0x98D4,0xB0E8,0x854A, ++ 0xBB6B,0xC52A,0x4FE5,0xED16,0x86C5,0x9AD7,0x6655,0x1194, ++ 0x8ACF,0xE910,0x0406,0xFE81,0xA0F0,0x7844,0x25BA,0x4BE3, ++ 0xA2F3,0x5DFE,0x80C0,0x058A,0x3FAD,0x21BC,0x7048,0xF104, ++ 0x63DF,0x77C1,0xAF75,0x4263,0x2030,0xE51A,0xFD0E,0xBF6D, ++ 0x814C,0x1814,0x2635,0xC32F,0xBEE1,0x35A2,0x88CC,0x2E39, ++ 0x9357,0x55F2,0xFC82,0x7A47,0xC8AC,0xBAE7,0x322B,0xE695, ++ 0xC0A0,0x1998,0x9ED1,0xA37F,0x4466,0x547E,0x3BAB,0x0B83, ++ 0x8CCA,0xC729,0x6BD3,0x283C,0xA779,0xBCE2,0x161D,0xAD76, ++ 0xDB3B,0x6456,0x744E,0x141E,0x92DB,0x0C0A,0x486C,0xB8E4, ++ 0x9F5D,0xBD6E,0x43EF,0xC4A6,0x39A8,0x31A4,0xD337,0xF28B, ++ 0xD532,0x8B43,0x6E59,0xDAB7,0x018C,0xB164,0x9CD2,0x49E0, ++ 0xD8B4,0xACFA,0xF307,0xCF25,0xCAAF,0xF48E,0x47E9,0x1018, ++ 0x6FD5,0xF088,0x4A6F,0x5C72,0x3824,0x57F1,0x73C7,0x9751, ++ 0xCB23,0xA17C,0xE89C,0x3E21,0x96DD,0x61DC,0x0D86,0x0F85, ++ 0xE090,0x7C42,0x71C4,0xCCAA,0x90D8,0x0605,0xF701,0x1C12, ++ 0xC2A3,0x6A5F,0xAEF9,0x69D0,0x1791,0x9958,0x3A27,0x27B9, ++ 0xD938,0xEB13,0x2BB3,0x2233,0xD2BB,0xA970,0x0789,0x33A7, ++ 0x2DB6,0x3C22,0x1592,0xC920,0x8749,0xAAFF,0x5078,0xA57A, ++ 0x038F,0x59F8,0x0980,0x1A17,0x65DA,0xD731,0x84C6,0xD0B8, ++ 0x82C3,0x29B0,0x5A77,0x1E11,0x7BCB,0xA8FC,0x6DD6,0x2C3A, ++ }, ++ ++ ++ { /* second half of table is unsigned char-reversed version of first! */ ++ 0xA5C6,0x84F8,0x99EE,0x8DF6,0x0DFF,0xBDD6,0xB1DE,0x5491, ++ 0x5060,0x0302,0xA9CE,0x7D56,0x19E7,0x62B5,0xE64D,0x9AEC, ++ 0x458F,0x9D1F,0x4089,0x87FA,0x15EF,0xEBB2,0xC98E,0x0BFB, ++ 0xEC41,0x67B3,0xFD5F,0xEA45,0xBF23,0xF753,0x96E4,0x5B9B, ++ 0xC275,0x1CE1,0xAE3D,0x6A4C,0x5A6C,0x417E,0x02F5,0x4F83, ++ 0x5C68,0xF451,0x34D1,0x08F9,0x93E2,0x73AB,0x5362,0x3F2A, ++ 0x0C08,0x5295,0x6546,0x5E9D,0x2830,0xA137,0x0F0A,0xB52F, ++ 0x090E,0x3624,0x9B1B,0x3DDF,0x26CD,0x694E,0xCD7F,0x9FEA, ++ 0x1B12,0x9E1D,0x7458,0x2E34,0x2D36,0xB2DC,0xEEB4,0xFB5B, ++ 0xF6A4,0x4D76,0x61B7,0xCE7D,0x7B52,0x3EDD,0x715E,0x9713, ++ 0xF5A6,0x68B9,0x0000,0x2CC1,0x6040,0x1FE3,0xC879,0xEDB6, ++ 0xBED4,0x468D,0xD967,0x4B72,0xDE94,0xD498,0xE8B0,0x4A85, ++ 0x6BBB,0x2AC5,0xE54F,0x16ED,0xC586,0xD79A,0x5566,0x9411, ++ 0xCF8A,0x10E9,0x0604,0x81FE,0xF0A0,0x4478,0xBA25,0xE34B, ++ 0xF3A2,0xFE5D,0xC080,0x8A05,0xAD3F,0xBC21,0x4870,0x04F1, ++ 0xDF63,0xC177,0x75AF,0x6342,0x3020,0x1AE5,0x0EFD,0x6DBF, ++ 0x4C81,0x1418,0x3526,0x2FC3,0xE1BE,0xA235,0xCC88,0x392E, ++ 0x5793,0xF255,0x82FC,0x477A,0xACC8,0xE7BA,0x2B32,0x95E6, ++ 0xA0C0,0x9819,0xD19E,0x7FA3,0x6644,0x7E54,0xAB3B,0x830B, ++ 0xCA8C,0x29C7,0xD36B,0x3C28,0x79A7,0xE2BC,0x1D16,0x76AD, ++ 0x3BDB,0x5664,0x4E74,0x1E14,0xDB92,0x0A0C,0x6C48,0xE4B8, ++ 0x5D9F,0x6EBD,0xEF43,0xA6C4,0xA839,0xA431,0x37D3,0x8BF2, ++ 0x32D5,0x438B,0x596E,0xB7DA,0x8C01,0x64B1,0xD29C,0xE049, ++ 0xB4D8,0xFAAC,0x07F3,0x25CF,0xAFCA,0x8EF4,0xE947,0x1810, ++ 0xD56F,0x88F0,0x6F4A,0x725C,0x2438,0xF157,0xC773,0x5197, ++ 0x23CB,0x7CA1,0x9CE8,0x213E,0xDD96,0xDC61,0x860D,0x850F, ++ 0x90E0,0x427C,0xC471,0xAACC,0xD890,0x0506,0x01F7,0x121C, ++ 0xA3C2,0x5F6A,0xF9AE,0xD069,0x9117,0x5899,0x273A,0xB927, ++ 0x38D9,0x13EB,0xB32B,0x3322,0xBBD2,0x70A9,0x8907,0xA733, ++ 0xB62D,0x223C,0x9215,0x20C9,0x4987,0xFFAA,0x7850,0x7AA5, ++ 0x8F03,0xF859,0x8009,0x171A,0xDA65,0x31D7,0xC684,0xB8D0, ++ 0xC382,0xB029,0x775A,0x111E,0xCB7B,0xFCA8,0xD66D,0x3A2C, ++ } ++}; ++ ++ /* ++********************************************************************** ++* Routine: Phase 1 -- generate P1K, given TA, TK, IV32 ++* ++* Inputs: ++* tk[] = temporal key [128 bits] ++* ta[] = transmitter's MAC address [ 48 bits] ++* iv32 = upper 32 bits of IV [ 32 bits] ++* Output: ++* p1k[] = Phase 1 key [ 80 bits] ++* ++* Note: ++* This function only needs to be called every 2**16 packets, ++* although in theory it could be called every packet. ++* ++********************************************************************** ++*/ ++static void phase1(u16 *p1k,const u8 *tk,const u8 *ta,u32 iv32) ++{ ++ sint i; ++_func_enter_; ++ /* Initialize the 80 bits of P1K[] from IV32 and TA[0..5] */ ++ p1k[0] = Lo16(iv32); ++ p1k[1] = Hi16(iv32); ++ p1k[2] = Mk16(ta[1],ta[0]); /* use TA[] as little-endian */ ++ p1k[3] = Mk16(ta[3],ta[2]); ++ p1k[4] = Mk16(ta[5],ta[4]); ++ ++ /* Now compute an unbalanced Feistel cipher with 80-bit block */ ++ /* size on the 80-bit block P1K[], using the 128-bit key TK[] */ ++ for (i=0; i < PHASE1_LOOP_CNT ;i++) ++ { /* Each add operation here is mod 2**16 */ ++ p1k[0] += _S_(p1k[4] ^ TK16((i&1)+0)); ++ p1k[1] += _S_(p1k[0] ^ TK16((i&1)+2)); ++ p1k[2] += _S_(p1k[1] ^ TK16((i&1)+4)); ++ p1k[3] += _S_(p1k[2] ^ TK16((i&1)+6)); ++ p1k[4] += _S_(p1k[3] ^ TK16((i&1)+0)); ++ p1k[4] += (unsigned short)i; /* avoid "slide attacks" */ ++ } ++_func_exit_; ++} ++ ++ ++/* ++********************************************************************** ++* Routine: Phase 2 -- generate RC4KEY, given TK, P1K, IV16 ++* ++* Inputs: ++* tk[] = Temporal key [128 bits] ++* p1k[] = Phase 1 output key [ 80 bits] ++* iv16 = low 16 bits of IV counter [ 16 bits] ++* Output: ++* rc4key[] = the key used to encrypt the packet [128 bits] ++* ++* Note: ++* The value {TA,IV32,IV16} for Phase1/Phase2 must be unique ++* across all packets using the same key TK value. Then, for a ++* given value of TK[], this TKIP48 construction guarantees that ++* the final RC4KEY value is unique across all packets. ++* ++* Suggested implementation optimization: if PPK[] is "overlaid" ++* appropriately on RC4KEY[], there is no need for the final ++* for loop below that copies the PPK[] result into RC4KEY[]. ++* ++********************************************************************** ++*/ ++static void phase2(u8 *rc4key,const u8 *tk,const u16 *p1k,u16 iv16) ++{ ++ sint i; ++ u16 PPK[6]; /* temporary key for mixing */ ++_func_enter_; ++ /* Note: all adds in the PPK[] equations below are mod 2**16 */ ++ for (i=0;i<5;i++) PPK[i]=p1k[i]; /* first, copy P1K to PPK */ ++ PPK[5] = p1k[4] +iv16; /* next, add in IV16 */ ++ ++ /* Bijective non-linear mixing of the 96 bits of PPK[0..5] */ ++ PPK[0] += _S_(PPK[5] ^ TK16(0)); /* Mix key in each "round" */ ++ PPK[1] += _S_(PPK[0] ^ TK16(1)); ++ PPK[2] += _S_(PPK[1] ^ TK16(2)); ++ PPK[3] += _S_(PPK[2] ^ TK16(3)); ++ PPK[4] += _S_(PPK[3] ^ TK16(4)); ++ PPK[5] += _S_(PPK[4] ^ TK16(5)); /* Total # S-box lookups == 6 */ ++ ++ /* Final sweep: bijective, "linear". Rotates kill LSB correlations */ ++ PPK[0] += RotR1(PPK[5] ^ TK16(6)); ++ PPK[1] += RotR1(PPK[0] ^ TK16(7)); /* Use all of TK[] in Phase2 */ ++ PPK[2] += RotR1(PPK[1]); ++ PPK[3] += RotR1(PPK[2]); ++ PPK[4] += RotR1(PPK[3]); ++ PPK[5] += RotR1(PPK[4]); ++ /* Note: At this point, for a given key TK[0..15], the 96-bit output */ ++ /* value PPK[0..5] is guaranteed to be unique, as a function */ ++ /* of the 96-bit "input" value {TA,IV32,IV16}. That is, P1K */ ++ /* is now a keyed permutation of {TA,IV32,IV16}. */ ++ ++ /* Set RC4KEY[0..3], which includes "cleartext" portion of RC4 key */ ++ rc4key[0] = Hi8(iv16); /* RC4KEY[0..2] is the WEP IV */ ++ rc4key[1] =(Hi8(iv16) | 0x20) & 0x7F; /* Help avoid weak (FMS) keys */ ++ rc4key[2] = Lo8(iv16); ++ rc4key[3] = Lo8((PPK[5] ^ TK16(0)) >> 1); ++ ++ ++ /* Copy 96 bits of PPK[0..5] to RC4KEY[4..15] (little-endian) */ ++ for (i=0;i<6;i++) ++ { ++ rc4key[4+2*i] = Lo8(PPK[i]); ++ rc4key[5+2*i] = Hi8(PPK[i]); ++ } ++_func_exit_; ++} ++ ++ ++//The hlen isn't include the IV ++u32 rtw_tkip_encrypt(_adapter *padapter, u8 *pxmitframe) ++{ // exclude ICV ++ u16 pnl; ++ u32 pnh; ++ u8 rc4key[16]; ++ u8 ttkey[16]; ++ u8 crc[4]; ++ struct arc4context mycontext; ++ sint curfragnum,length; ++ u32 prwskeylen; ++ ++ u8 *pframe, *payload,*iv,*prwskey; ++ union pn48 dot11txpn; ++ struct sta_info *stainfo; ++ struct pkt_attrib *pattrib = &((struct xmit_frame *)pxmitframe)->attrib; ++ struct security_priv *psecuritypriv=&padapter->securitypriv; ++ struct xmit_priv *pxmitpriv=&padapter->xmitpriv; ++ u32 res=_SUCCESS; ++_func_enter_; ++ ++ if(((struct xmit_frame*)pxmitframe)->buf_addr==NULL) ++ return _FAIL; ++ ++#ifdef CONFIG_USB_TX_AGGREGATION ++ pframe = ((struct xmit_frame*)pxmitframe)->buf_addr + TXDESC_SIZE + ++ (((struct xmit_frame*)pxmitframe)->pkt_offset * PACKET_OFFSET_SZ); ++#else ++ pframe = ((struct xmit_frame*)pxmitframe)->buf_addr + TXDESC_OFFSET; ++#endif ++ ++ //4 start to encrypt each fragment ++ if(pattrib->encrypt==_TKIP_){ ++ ++ if(pattrib->psta) ++ { ++ stainfo = pattrib->psta; ++ } ++ else ++ { ++ stainfo=rtw_get_stainfo(&padapter->stapriv ,&pattrib->ra[0] ); ++ } ++ ++ if (stainfo!=NULL){ ++ RT_TRACE(_module_rtl871x_security_c_,_drv_err_,("rtw_tkip_encrypt: stainfo!=NULL!!!\n")); ++ ++ if(IS_MCAST(pattrib->ra)) ++ { ++ prwskey=psecuritypriv->dot118021XGrpKey[psecuritypriv->dot118021XGrpKeyid].skey; ++ } ++ else ++ { ++ prwskey=&stainfo->dot118021x_UncstKey.skey[0]; ++ } ++ ++ prwskeylen=16; ++ ++ for(curfragnum=0;curfragnumnr_frags;curfragnum++){ ++ iv=pframe+pattrib->hdrlen; ++ payload=pframe+pattrib->iv_len+pattrib->hdrlen; ++ ++ GET_TKIP_PN(iv, dot11txpn); ++ ++ pnl=(u16)(dot11txpn.val); ++ pnh=(u32)(dot11txpn.val>>16); ++ ++ phase1((u16 *)&ttkey[0],prwskey,&pattrib->ta[0],pnh); ++ ++ phase2(&rc4key[0],prwskey,(u16 *)&ttkey[0],pnl); ++ ++ if((curfragnum+1)==pattrib->nr_frags){ //4 the last fragment ++ length=pattrib->last_txcmdsz-pattrib->hdrlen-pattrib->iv_len- pattrib->icv_len; ++ RT_TRACE(_module_rtl871x_security_c_,_drv_info_,("pattrib->iv_len =%x, pattrib->icv_len =%x\n", pattrib->iv_len,pattrib->icv_len)); ++ *((u32 *)crc)=cpu_to_le32(getcrc32(payload,length));/* modified by Amy*/ ++ ++ arcfour_init(&mycontext, rc4key,16); ++ arcfour_encrypt(&mycontext, payload, payload, length); ++ arcfour_encrypt(&mycontext, payload+length, crc, 4); ++ ++ } ++ else{ ++ length=pxmitpriv->frag_len-pattrib->hdrlen-pattrib->iv_len-pattrib->icv_len ; ++ *((u32 *)crc)=cpu_to_le32(getcrc32(payload,length));/* modified by Amy*/ ++ arcfour_init(&mycontext,rc4key,16); ++ arcfour_encrypt(&mycontext, payload, payload, length); ++ arcfour_encrypt(&mycontext, payload+length, crc, 4); ++ ++ pframe+=pxmitpriv->frag_len; ++ pframe=(u8 *)RND4((SIZE_PTR)(pframe)); ++ ++ } ++ } ++ ++ ++ } ++ else{ ++ RT_TRACE(_module_rtl871x_security_c_,_drv_err_,("rtw_tkip_encrypt: stainfo==NULL!!!\n")); ++ res=_FAIL; ++ } ++ ++ } ++_func_exit_; ++ return res; ++ ++} ++ ++ ++//The hlen isn't include the IV ++u32 rtw_tkip_decrypt(_adapter *padapter, u8 *precvframe) ++{ // exclude ICV ++ u16 pnl; ++ u32 pnh; ++ u8 rc4key[16]; ++ u8 ttkey[16]; ++ u8 crc[4]; ++ struct arc4context mycontext; ++ sint length; ++ u32 prwskeylen; ++ ++ u8 *pframe, *payload,*iv,*prwskey; ++ union pn48 dot11txpn; ++ struct sta_info *stainfo; ++ struct rx_pkt_attrib *prxattrib = &((union recv_frame *)precvframe)->u.hdr.attrib; ++ struct security_priv *psecuritypriv=&padapter->securitypriv; ++// struct recv_priv *precvpriv=&padapter->recvpriv; ++ u32 res=_SUCCESS; ++ ++_func_enter_; ++ ++ pframe=(unsigned char *)((union recv_frame*)precvframe)->u.hdr.rx_data; ++ ++ //4 start to decrypt recvframe ++ if(prxattrib->encrypt==_TKIP_){ ++ ++ stainfo=rtw_get_stainfo(&padapter->stapriv ,&prxattrib->ta[0] ); ++ ++ ++ if (stainfo!=NULL){ ++ ++ if(IS_MCAST(prxattrib->ra)) ++ { ++ if(psecuritypriv->binstallGrpkey==_FALSE) ++ { ++ res=_FAIL; ++ DBG_8192C("%s:rx bc/mc packets,but didn't install group key!!!!!!!!!!\n",__FUNCTION__); ++ goto exit; ++ } ++ ++ DBG_871X("rx bc/mc packets, to perform sw rtw_tkip_decrypt\n"); ++ //prwskey = psecuritypriv->dot118021XGrpKey[psecuritypriv->dot118021XGrpKeyid].skey; ++ prwskey = psecuritypriv->dot118021XGrpKey[prxattrib->key_index].skey; ++ prwskeylen=16; ++ } ++ else ++ { ++ RT_TRACE(_module_rtl871x_security_c_,_drv_err_,("rtw_tkip_decrypt: stainfo!=NULL!!!\n")); ++ prwskey=&stainfo->dot118021x_UncstKey.skey[0]; ++ prwskeylen=16; ++ } ++ ++ iv=pframe+prxattrib->hdrlen; ++ payload=pframe+prxattrib->iv_len+prxattrib->hdrlen; ++ length= ((union recv_frame *)precvframe)->u.hdr.len-prxattrib->hdrlen-prxattrib->iv_len; ++ ++ GET_TKIP_PN(iv, dot11txpn); ++ ++ pnl=(u16)(dot11txpn.val); ++ pnh=(u32)(dot11txpn.val>>16); ++ ++ phase1((u16 *)&ttkey[0],prwskey,&prxattrib->ta[0],pnh); ++ phase2(&rc4key[0],prwskey,(unsigned short *)&ttkey[0],pnl); ++ ++ //4 decrypt payload include icv ++ ++ arcfour_init(&mycontext, rc4key,16); ++ arcfour_encrypt(&mycontext, payload, payload, length); ++ ++ *((u32 *)crc)=le32_to_cpu(getcrc32(payload,length-4)); ++ ++ if(crc[3]!=payload[length-1] || crc[2]!=payload[length-2] || crc[1]!=payload[length-3] || crc[0]!=payload[length-4]) ++ { ++ RT_TRACE(_module_rtl871x_security_c_,_drv_err_,("rtw_wep_decrypt:icv error crc[3](%x)!=payload[length-1](%x) || crc[2](%x)!=payload[length-2](%x) || crc[1](%x)!=payload[length-3](%x) || crc[0](%x)!=payload[length-4](%x)\n", ++ crc[3],payload[length-1],crc[2],payload[length-2],crc[1],payload[length-3],crc[0],payload[length-4])); ++ res=_FAIL; ++ } ++ ++ ++ } ++ else{ ++ RT_TRACE(_module_rtl871x_security_c_,_drv_err_,("rtw_tkip_decrypt: stainfo==NULL!!!\n")); ++ res=_FAIL; ++ } ++ ++ } ++_func_exit_; ++exit: ++ return res; ++ ++} ++ ++ ++//3 =====AES related===== ++ ++ ++ ++#define MAX_MSG_SIZE 2048 ++/*****************************/ ++/******** SBOX Table *********/ ++/*****************************/ ++ ++ static u8 sbox_table[256] = ++ { ++ 0x63, 0x7c, 0x77, 0x7b, 0xf2, 0x6b, 0x6f, 0xc5, ++ 0x30, 0x01, 0x67, 0x2b, 0xfe, 0xd7, 0xab, 0x76, ++ 0xca, 0x82, 0xc9, 0x7d, 0xfa, 0x59, 0x47, 0xf0, ++ 0xad, 0xd4, 0xa2, 0xaf, 0x9c, 0xa4, 0x72, 0xc0, ++ 0xb7, 0xfd, 0x93, 0x26, 0x36, 0x3f, 0xf7, 0xcc, ++ 0x34, 0xa5, 0xe5, 0xf1, 0x71, 0xd8, 0x31, 0x15, ++ 0x04, 0xc7, 0x23, 0xc3, 0x18, 0x96, 0x05, 0x9a, ++ 0x07, 0x12, 0x80, 0xe2, 0xeb, 0x27, 0xb2, 0x75, ++ 0x09, 0x83, 0x2c, 0x1a, 0x1b, 0x6e, 0x5a, 0xa0, ++ 0x52, 0x3b, 0xd6, 0xb3, 0x29, 0xe3, 0x2f, 0x84, ++ 0x53, 0xd1, 0x00, 0xed, 0x20, 0xfc, 0xb1, 0x5b, ++ 0x6a, 0xcb, 0xbe, 0x39, 0x4a, 0x4c, 0x58, 0xcf, ++ 0xd0, 0xef, 0xaa, 0xfb, 0x43, 0x4d, 0x33, 0x85, ++ 0x45, 0xf9, 0x02, 0x7f, 0x50, 0x3c, 0x9f, 0xa8, ++ 0x51, 0xa3, 0x40, 0x8f, 0x92, 0x9d, 0x38, 0xf5, ++ 0xbc, 0xb6, 0xda, 0x21, 0x10, 0xff, 0xf3, 0xd2, ++ 0xcd, 0x0c, 0x13, 0xec, 0x5f, 0x97, 0x44, 0x17, ++ 0xc4, 0xa7, 0x7e, 0x3d, 0x64, 0x5d, 0x19, 0x73, ++ 0x60, 0x81, 0x4f, 0xdc, 0x22, 0x2a, 0x90, 0x88, ++ 0x46, 0xee, 0xb8, 0x14, 0xde, 0x5e, 0x0b, 0xdb, ++ 0xe0, 0x32, 0x3a, 0x0a, 0x49, 0x06, 0x24, 0x5c, ++ 0xc2, 0xd3, 0xac, 0x62, 0x91, 0x95, 0xe4, 0x79, ++ 0xe7, 0xc8, 0x37, 0x6d, 0x8d, 0xd5, 0x4e, 0xa9, ++ 0x6c, 0x56, 0xf4, 0xea, 0x65, 0x7a, 0xae, 0x08, ++ 0xba, 0x78, 0x25, 0x2e, 0x1c, 0xa6, 0xb4, 0xc6, ++ 0xe8, 0xdd, 0x74, 0x1f, 0x4b, 0xbd, 0x8b, 0x8a, ++ 0x70, 0x3e, 0xb5, 0x66, 0x48, 0x03, 0xf6, 0x0e, ++ 0x61, 0x35, 0x57, 0xb9, 0x86, 0xc1, 0x1d, 0x9e, ++ 0xe1, 0xf8, 0x98, 0x11, 0x69, 0xd9, 0x8e, 0x94, ++ 0x9b, 0x1e, 0x87, 0xe9, 0xce, 0x55, 0x28, 0xdf, ++ 0x8c, 0xa1, 0x89, 0x0d, 0xbf, 0xe6, 0x42, 0x68, ++ 0x41, 0x99, 0x2d, 0x0f, 0xb0, 0x54, 0xbb, 0x16 ++ }; ++ ++/*****************************/ ++/**** Function Prototypes ****/ ++/*****************************/ ++ ++static void bitwise_xor(u8 *ina, u8 *inb, u8 *out); ++static void construct_mic_iv( ++ u8 *mic_header1, ++ sint qc_exists, ++ sint a4_exists, ++ u8 *mpdu, ++ uint payload_length, ++ u8 * pn_vector); ++static void construct_mic_header1( ++ u8 *mic_header1, ++ sint header_length, ++ u8 *mpdu); ++static void construct_mic_header2( ++ u8 *mic_header2, ++ u8 *mpdu, ++ sint a4_exists, ++ sint qc_exists); ++static void construct_ctr_preload( ++ u8 *ctr_preload, ++ sint a4_exists, ++ sint qc_exists, ++ u8 *mpdu, ++ u8 *pn_vector, ++ sint c); ++static void xor_128(u8 *a, u8 *b, u8 *out); ++static void xor_32(u8 *a, u8 *b, u8 *out); ++static u8 sbox(u8 a); ++static void next_key(u8 *key, sint round); ++static void byte_sub(u8 *in, u8 *out); ++static void shift_row(u8 *in, u8 *out); ++static void mix_column(u8 *in, u8 *out); ++static void add_round_key( u8 *shiftrow_in, ++ u8 *mcol_in, ++ u8 *block_in, ++ sint round, ++ u8 *out); ++static void aes128k128d(u8 *key, u8 *data, u8 *ciphertext); ++ ++ ++/****************************************/ ++/* aes128k128d() */ ++/* Performs a 128 bit AES encrypt with */ ++/* 128 bit data. */ ++/****************************************/ ++static void xor_128(u8 *a, u8 *b, u8 *out) ++{ ++ sint i; ++_func_enter_; ++ for (i=0;i<16; i++) ++ { ++ out[i] = a[i] ^ b[i]; ++ } ++_func_exit_; ++} ++ ++ ++static void xor_32(u8 *a, u8 *b, u8 *out) ++{ ++ sint i; ++_func_enter_; ++ for (i=0;i<4; i++) ++ { ++ out[i] = a[i] ^ b[i]; ++ } ++_func_exit_; ++} ++ ++ ++static u8 sbox(u8 a) ++{ ++ return sbox_table[(sint)a]; ++} ++ ++ ++static void next_key(u8 *key, sint round) ++{ ++ u8 rcon; ++ u8 sbox_key[4]; ++ u8 rcon_table[12] = ++ { ++ 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, ++ 0x1b, 0x36, 0x36, 0x36 ++ }; ++_func_enter_; ++ sbox_key[0] = sbox(key[13]); ++ sbox_key[1] = sbox(key[14]); ++ sbox_key[2] = sbox(key[15]); ++ sbox_key[3] = sbox(key[12]); ++ ++ rcon = rcon_table[round]; ++ ++ xor_32(&key[0], sbox_key, &key[0]); ++ key[0] = key[0] ^ rcon; ++ ++ xor_32(&key[4], &key[0], &key[4]); ++ xor_32(&key[8], &key[4], &key[8]); ++ xor_32(&key[12], &key[8], &key[12]); ++_func_exit_; ++} ++ ++ ++static void byte_sub(u8 *in, u8 *out) ++{ ++ sint i; ++_func_enter_; ++ for (i=0; i< 16; i++) ++ { ++ out[i] = sbox(in[i]); ++ } ++_func_exit_; ++} ++ ++ ++static void shift_row(u8 *in, u8 *out) ++{ ++_func_enter_; ++ out[0] = in[0]; ++ out[1] = in[5]; ++ out[2] = in[10]; ++ out[3] = in[15]; ++ out[4] = in[4]; ++ out[5] = in[9]; ++ out[6] = in[14]; ++ out[7] = in[3]; ++ out[8] = in[8]; ++ out[9] = in[13]; ++ out[10] = in[2]; ++ out[11] = in[7]; ++ out[12] = in[12]; ++ out[13] = in[1]; ++ out[14] = in[6]; ++ out[15] = in[11]; ++_func_exit_; ++} ++ ++ ++static void mix_column(u8 *in, u8 *out) ++{ ++ sint i; ++ u8 add1b[4]; ++ u8 add1bf7[4]; ++ u8 rotl[4]; ++ u8 swap_halfs[4]; ++ u8 andf7[4]; ++ u8 rotr[4]; ++ u8 temp[4]; ++ u8 tempb[4]; ++_func_enter_; ++ for (i=0 ; i<4; i++) ++ { ++ if ((in[i] & 0x80)== 0x80) ++ add1b[i] = 0x1b; ++ else ++ add1b[i] = 0x00; ++ } ++ ++ swap_halfs[0] = in[2]; /* Swap halfs */ ++ swap_halfs[1] = in[3]; ++ swap_halfs[2] = in[0]; ++ swap_halfs[3] = in[1]; ++ ++ rotl[0] = in[3]; /* Rotate left 8 bits */ ++ rotl[1] = in[0]; ++ rotl[2] = in[1]; ++ rotl[3] = in[2]; ++ ++ andf7[0] = in[0] & 0x7f; ++ andf7[1] = in[1] & 0x7f; ++ andf7[2] = in[2] & 0x7f; ++ andf7[3] = in[3] & 0x7f; ++ ++ for (i = 3; i>0; i--) /* logical shift left 1 bit */ ++ { ++ andf7[i] = andf7[i] << 1; ++ if ((andf7[i-1] & 0x80) == 0x80) ++ { ++ andf7[i] = (andf7[i] | 0x01); ++ } ++ } ++ andf7[0] = andf7[0] << 1; ++ andf7[0] = andf7[0] & 0xfe; ++ ++ xor_32(add1b, andf7, add1bf7); ++ ++ xor_32(in, add1bf7, rotr); ++ ++ temp[0] = rotr[0]; /* Rotate right 8 bits */ ++ rotr[0] = rotr[1]; ++ rotr[1] = rotr[2]; ++ rotr[2] = rotr[3]; ++ rotr[3] = temp[0]; ++ ++ xor_32(add1bf7, rotr, temp); ++ xor_32(swap_halfs, rotl,tempb); ++ xor_32(temp, tempb, out); ++_func_exit_; ++} ++ ++ ++static void aes128k128d(u8 *key, u8 *data, u8 *ciphertext) ++{ ++ sint round; ++ sint i; ++ u8 intermediatea[16]; ++ u8 intermediateb[16]; ++ u8 round_key[16]; ++_func_enter_; ++ for(i=0; i<16; i++) round_key[i] = key[i]; ++ ++ for (round = 0; round < 11; round++) ++ { ++ if (round == 0) ++ { ++ xor_128(round_key, data, ciphertext); ++ next_key(round_key, round); ++ } ++ else if (round == 10) ++ { ++ byte_sub(ciphertext, intermediatea); ++ shift_row(intermediatea, intermediateb); ++ xor_128(intermediateb, round_key, ciphertext); ++ } ++ else /* 1 - 9 */ ++ { ++ byte_sub(ciphertext, intermediatea); ++ shift_row(intermediatea, intermediateb); ++ mix_column(&intermediateb[0], &intermediatea[0]); ++ mix_column(&intermediateb[4], &intermediatea[4]); ++ mix_column(&intermediateb[8], &intermediatea[8]); ++ mix_column(&intermediateb[12], &intermediatea[12]); ++ xor_128(intermediatea, round_key, ciphertext); ++ next_key(round_key, round); ++ } ++ } ++_func_exit_; ++} ++ ++ ++/************************************************/ ++/* construct_mic_iv() */ ++/* Builds the MIC IV from header fields and PN */ ++/************************************************/ ++static void construct_mic_iv( ++ u8 *mic_iv, ++ sint qc_exists, ++ sint a4_exists, ++ u8 *mpdu, ++ uint payload_length, ++ u8 *pn_vector ++ ) ++{ ++ sint i; ++_func_enter_; ++ mic_iv[0] = 0x59; ++ if (qc_exists && a4_exists) mic_iv[1] = mpdu[30] & 0x0f; /* QoS_TC */ ++ if (qc_exists && !a4_exists) mic_iv[1] = mpdu[24] & 0x0f; /* mute bits 7-4 */ ++ if (!qc_exists) mic_iv[1] = 0x00; ++ for (i = 2; i < 8; i++) ++ mic_iv[i] = mpdu[i + 8]; /* mic_iv[2:7] = A2[0:5] = mpdu[10:15] */ ++ #ifdef CONSISTENT_PN_ORDER ++ for (i = 8; i < 14; i++) ++ mic_iv[i] = pn_vector[i - 8]; /* mic_iv[8:13] = PN[0:5] */ ++ #else ++ for (i = 8; i < 14; i++) ++ mic_iv[i] = pn_vector[13 - i]; /* mic_iv[8:13] = PN[5:0] */ ++ #endif ++ mic_iv[14] = (unsigned char) (payload_length / 256); ++ mic_iv[15] = (unsigned char) (payload_length % 256); ++_func_exit_; ++} ++ ++ ++/************************************************/ ++/* construct_mic_header1() */ ++/* Builds the first MIC header block from */ ++/* header fields. */ ++/************************************************/ ++static void construct_mic_header1( ++ u8 *mic_header1, ++ sint header_length, ++ u8 *mpdu ++ ) ++{ ++_func_enter_; ++ mic_header1[0] = (u8)((header_length - 2) / 256); ++ mic_header1[1] = (u8)((header_length - 2) % 256); ++ mic_header1[2] = mpdu[0] & 0xcf; /* Mute CF poll & CF ack bits */ ++ mic_header1[3] = mpdu[1] & 0xc7; /* Mute retry, more data and pwr mgt bits */ ++ mic_header1[4] = mpdu[4]; /* A1 */ ++ mic_header1[5] = mpdu[5]; ++ mic_header1[6] = mpdu[6]; ++ mic_header1[7] = mpdu[7]; ++ mic_header1[8] = mpdu[8]; ++ mic_header1[9] = mpdu[9]; ++ mic_header1[10] = mpdu[10]; /* A2 */ ++ mic_header1[11] = mpdu[11]; ++ mic_header1[12] = mpdu[12]; ++ mic_header1[13] = mpdu[13]; ++ mic_header1[14] = mpdu[14]; ++ mic_header1[15] = mpdu[15]; ++_func_exit_; ++} ++ ++ ++/************************************************/ ++/* construct_mic_header2() */ ++/* Builds the last MIC header block from */ ++/* header fields. */ ++/************************************************/ ++static void construct_mic_header2( ++ u8 *mic_header2, ++ u8 *mpdu, ++ sint a4_exists, ++ sint qc_exists ++ ) ++{ ++ sint i; ++_func_enter_; ++ for (i = 0; i<16; i++) mic_header2[i]=0x00; ++ ++ mic_header2[0] = mpdu[16]; /* A3 */ ++ mic_header2[1] = mpdu[17]; ++ mic_header2[2] = mpdu[18]; ++ mic_header2[3] = mpdu[19]; ++ mic_header2[4] = mpdu[20]; ++ mic_header2[5] = mpdu[21]; ++ ++ //mic_header2[6] = mpdu[22] & 0xf0; /* SC */ ++ mic_header2[6] = 0x00; ++ mic_header2[7] = 0x00; /* mpdu[23]; */ ++ ++ ++ if (!qc_exists && a4_exists) ++ { ++ for (i=0;i<6;i++) mic_header2[8+i] = mpdu[24+i]; /* A4 */ ++ ++ } ++ ++ if (qc_exists && !a4_exists) ++ { ++ mic_header2[8] = mpdu[24] & 0x0f; /* mute bits 15 - 4 */ ++ mic_header2[9] = mpdu[25] & 0x00; ++ } ++ ++ if (qc_exists && a4_exists) ++ { ++ for (i=0;i<6;i++) mic_header2[8+i] = mpdu[24+i]; /* A4 */ ++ ++ mic_header2[14] = mpdu[30] & 0x0f; ++ mic_header2[15] = mpdu[31] & 0x00; ++ } ++ ++_func_exit_; ++} ++ ++ ++/************************************************/ ++/* construct_mic_header2() */ ++/* Builds the last MIC header block from */ ++/* header fields. */ ++/************************************************/ ++static void construct_ctr_preload( ++ u8 *ctr_preload, ++ sint a4_exists, ++ sint qc_exists, ++ u8 *mpdu, ++ u8 *pn_vector, ++ sint c ++ ) ++{ ++ sint i = 0; ++_func_enter_; ++ for (i=0; i<16; i++) ctr_preload[i] = 0x00; ++ i = 0; ++ ++ ctr_preload[0] = 0x01; /* flag */ ++ if (qc_exists && a4_exists) ++ ctr_preload[1] = mpdu[30] & 0x0f; /* QoC_Control */ ++ if (qc_exists && !a4_exists) ++ ctr_preload[1] = mpdu[24] & 0x0f; ++ ++ for (i = 2; i < 8; i++) ++ ctr_preload[i] = mpdu[i + 8]; /* ctr_preload[2:7] = A2[0:5] = mpdu[10:15] */ ++ #ifdef CONSISTENT_PN_ORDER ++ for (i = 8; i < 14; i++) ++ ctr_preload[i] = pn_vector[i - 8]; /* ctr_preload[8:13] = PN[0:5] */ ++ #else ++ for (i = 8; i < 14; i++) ++ ctr_preload[i] = pn_vector[13 - i]; /* ctr_preload[8:13] = PN[5:0] */ ++ #endif ++ ctr_preload[14] = (unsigned char) (c / 256); /* Ctr */ ++ ctr_preload[15] = (unsigned char) (c % 256); ++_func_exit_; ++} ++ ++ ++/************************************/ ++/* bitwise_xor() */ ++/* A 128 bit, bitwise exclusive or */ ++/************************************/ ++static void bitwise_xor(u8 *ina, u8 *inb, u8 *out) ++{ ++ sint i; ++_func_enter_; ++ for (i=0; i<16; i++) ++ { ++ out[i] = ina[i] ^ inb[i]; ++ } ++_func_exit_; ++} ++ ++ ++static sint aes_cipher(u8 *key, uint hdrlen, ++ u8 *pframe, uint plen) ++{ ++// /*static*/ unsigned char message[MAX_MSG_SIZE]; ++ uint qc_exists, a4_exists, i, j, payload_remainder, ++ num_blocks, payload_index; ++ ++ u8 pn_vector[6]; ++ u8 mic_iv[16]; ++ u8 mic_header1[16]; ++ u8 mic_header2[16]; ++ u8 ctr_preload[16]; ++ ++ /* Intermediate Buffers */ ++ u8 chain_buffer[16]; ++ u8 aes_out[16]; ++ u8 padded_buffer[16]; ++ u8 mic[8]; ++// uint offset = 0; ++ uint frtype = GetFrameType(pframe); ++ uint frsubtype = GetFrameSubType(pframe); ++ ++_func_enter_; ++ frsubtype=frsubtype>>4; ++ ++ ++ _rtw_memset((void *)mic_iv, 0, 16); ++ _rtw_memset((void *)mic_header1, 0, 16); ++ _rtw_memset((void *)mic_header2, 0, 16); ++ _rtw_memset((void *)ctr_preload, 0, 16); ++ _rtw_memset((void *)chain_buffer, 0, 16); ++ _rtw_memset((void *)aes_out, 0, 16); ++ _rtw_memset((void *)padded_buffer, 0, 16); ++ ++ if ((hdrlen == WLAN_HDR_A3_LEN )||(hdrlen == WLAN_HDR_A3_QOS_LEN)) ++ a4_exists = 0; ++ else ++ a4_exists = 1; ++ ++ if ( ++ (frtype == WIFI_DATA_CFACK) || ++ (frtype == WIFI_DATA_CFPOLL)|| ++ (frtype == WIFI_DATA_CFACKPOLL)) ++ { ++ qc_exists = 1; ++ if(hdrlen != WLAN_HDR_A3_QOS_LEN){ ++ ++ hdrlen += 2; ++ } ++ } ++ else if ( ++ (frsubtype == 0x08) || ++ (frsubtype == 0x09)|| ++ (frsubtype == 0x0a)|| ++ (frsubtype == 0x0b)) ++ { ++ if(hdrlen != WLAN_HDR_A3_QOS_LEN){ ++ ++ hdrlen += 2; ++ } ++ qc_exists = 1; ++ } ++ else ++ qc_exists = 0; ++ ++ pn_vector[0]=pframe[hdrlen]; ++ pn_vector[1]=pframe[hdrlen+1]; ++ pn_vector[2]=pframe[hdrlen+4]; ++ pn_vector[3]=pframe[hdrlen+5]; ++ pn_vector[4]=pframe[hdrlen+6]; ++ pn_vector[5]=pframe[hdrlen+7]; ++ ++ construct_mic_iv( ++ mic_iv, ++ qc_exists, ++ a4_exists, ++ pframe, //message, ++ plen, ++ pn_vector ++ ); ++ ++ construct_mic_header1( ++ mic_header1, ++ hdrlen, ++ pframe //message ++ ); ++ construct_mic_header2( ++ mic_header2, ++ pframe, //message, ++ a4_exists, ++ qc_exists ++ ); ++ ++ ++ payload_remainder = plen % 16; ++ num_blocks = plen / 16; ++ ++ /* Find start of payload */ ++ payload_index = (hdrlen + 8); ++ ++ /* Calculate MIC */ ++ aes128k128d(key, mic_iv, aes_out); ++ bitwise_xor(aes_out, mic_header1, chain_buffer); ++ aes128k128d(key, chain_buffer, aes_out); ++ bitwise_xor(aes_out, mic_header2, chain_buffer); ++ aes128k128d(key, chain_buffer, aes_out); ++ ++ for (i = 0; i < num_blocks; i++) ++ { ++ bitwise_xor(aes_out, &pframe[payload_index], chain_buffer);//bitwise_xor(aes_out, &message[payload_index], chain_buffer); ++ ++ payload_index += 16; ++ aes128k128d(key, chain_buffer, aes_out); ++ } ++ ++ /* Add on the final payload block if it needs padding */ ++ if (payload_remainder > 0) ++ { ++ for (j = 0; j < 16; j++) padded_buffer[j] = 0x00; ++ for (j = 0; j < payload_remainder; j++) ++ { ++ padded_buffer[j] = pframe[payload_index++];//padded_buffer[j] = message[payload_index++]; ++ } ++ bitwise_xor(aes_out, padded_buffer, chain_buffer); ++ aes128k128d(key, chain_buffer, aes_out); ++ ++ } ++ ++ for (j = 0 ; j < 8; j++) mic[j] = aes_out[j]; ++ ++ /* Insert MIC into payload */ ++ for (j = 0; j < 8; j++) ++ pframe[payload_index+j] = mic[j]; //message[payload_index+j] = mic[j]; ++ ++ payload_index = hdrlen + 8; ++ for (i=0; i< num_blocks; i++) ++ { ++ construct_ctr_preload( ++ ctr_preload, ++ a4_exists, ++ qc_exists, ++ pframe, //message, ++ pn_vector, ++ i+1); ++ aes128k128d(key, ctr_preload, aes_out); ++ bitwise_xor(aes_out, &pframe[payload_index], chain_buffer);//bitwise_xor(aes_out, &message[payload_index], chain_buffer); ++ for (j=0; j<16;j++) pframe[payload_index++] = chain_buffer[j];//for (j=0; j<16;j++) message[payload_index++] = chain_buffer[j]; ++ } ++ ++ if (payload_remainder > 0) /* If there is a short final block, then pad it,*/ ++ { /* encrypt it and copy the unpadded part back */ ++ construct_ctr_preload( ++ ctr_preload, ++ a4_exists, ++ qc_exists, ++ pframe, //message, ++ pn_vector, ++ num_blocks+1); ++ ++ for (j = 0; j < 16; j++) padded_buffer[j] = 0x00; ++ for (j = 0; j < payload_remainder; j++) ++ { ++ padded_buffer[j] = pframe[payload_index+j];//padded_buffer[j] = message[payload_index+j]; ++ } ++ aes128k128d(key, ctr_preload, aes_out); ++ bitwise_xor(aes_out, padded_buffer, chain_buffer); ++ for (j=0; jattrib; ++ struct security_priv *psecuritypriv=&padapter->securitypriv; ++ struct xmit_priv *pxmitpriv=&padapter->xmitpriv; ++ ++// uint offset = 0; ++ u32 res=_SUCCESS; ++_func_enter_; ++ ++ if(((struct xmit_frame*)pxmitframe)->buf_addr==NULL) ++ return _FAIL; ++ ++#ifdef CONFIG_USB_TX_AGGREGATION ++ pframe = ((struct xmit_frame*)pxmitframe)->buf_addr + TXDESC_SIZE + ++ (((struct xmit_frame*)pxmitframe)->pkt_offset * PACKET_OFFSET_SZ); ++#else ++ pframe = ((struct xmit_frame*)pxmitframe)->buf_addr + TXDESC_OFFSET; ++#endif ++ ++ //4 start to encrypt each fragment ++ if((pattrib->encrypt==_AES_)){ ++ ++ if(pattrib->psta) ++ { ++ stainfo = pattrib->psta; ++ } ++ else ++ { ++ stainfo=rtw_get_stainfo(&padapter->stapriv ,&pattrib->ra[0] ); ++ } ++ ++ if (stainfo!=NULL){ ++ RT_TRACE(_module_rtl871x_security_c_,_drv_err_,("rtw_aes_encrypt: stainfo!=NULL!!!\n")); ++ ++ if(IS_MCAST(pattrib->ra)) ++ { ++ prwskey=psecuritypriv->dot118021XGrpKey[psecuritypriv->dot118021XGrpKeyid].skey; ++ } ++ else ++ { ++ prwskey=&stainfo->dot118021x_UncstKey.skey[0]; ++ } ++ ++ prwskeylen=16; ++ ++ for(curfragnum=0;curfragnumnr_frags;curfragnum++){ ++ ++ if((curfragnum+1)==pattrib->nr_frags){ //4 the last fragment ++ length=pattrib->last_txcmdsz-pattrib->hdrlen-pattrib->iv_len- pattrib->icv_len; ++ ++ aes_cipher(prwskey,pattrib->hdrlen,pframe, length); ++ } ++ else{ ++ length=pxmitpriv->frag_len-pattrib->hdrlen-pattrib->iv_len-pattrib->icv_len ; ++ ++ aes_cipher(prwskey,pattrib->hdrlen,pframe, length); ++ pframe+=pxmitpriv->frag_len; ++ pframe=(u8*)RND4((SIZE_PTR)(pframe)); ++ ++ } ++ } ++ ++ ++ } ++ else{ ++ RT_TRACE(_module_rtl871x_security_c_,_drv_err_,("rtw_aes_encrypt: stainfo==NULL!!!\n")); ++ res=_FAIL; ++ } ++ ++ } ++ ++ ++ ++_func_exit_; ++ return res; ++} ++ ++static sint aes_decipher(u8 *key, uint hdrlen, ++ u8 *pframe, uint plen) ++{ ++ static u8 message[MAX_MSG_SIZE]; ++ uint qc_exists, a4_exists, i, j, payload_remainder, ++ num_blocks, payload_index; ++ ++ sint res = _SUCCESS; ++ u8 pn_vector[6]; ++ u8 mic_iv[16]; ++ u8 mic_header1[16]; ++ u8 mic_header2[16]; ++ u8 ctr_preload[16]; ++ ++ /* Intermediate Buffers */ ++ u8 chain_buffer[16]; ++ u8 aes_out[16]; ++ u8 padded_buffer[16]; ++ u8 mic[8]; ++ ++ ++// uint offset = 0; ++ uint frtype = GetFrameType(pframe); ++ uint frsubtype = GetFrameSubType(pframe); ++_func_enter_; ++ frsubtype=frsubtype>>4; ++ ++ ++ _rtw_memset((void *)mic_iv, 0, 16); ++ _rtw_memset((void *)mic_header1, 0, 16); ++ _rtw_memset((void *)mic_header2, 0, 16); ++ _rtw_memset((void *)ctr_preload, 0, 16); ++ _rtw_memset((void *)chain_buffer, 0, 16); ++ _rtw_memset((void *)aes_out, 0, 16); ++ _rtw_memset((void *)padded_buffer, 0, 16); ++ ++ //start to decrypt the payload ++ ++ num_blocks = (plen-8) / 16; //(plen including llc, payload_length and mic ) ++ ++ payload_remainder = (plen-8) % 16; ++ ++ pn_vector[0] = pframe[hdrlen]; ++ pn_vector[1] = pframe[hdrlen+1]; ++ pn_vector[2] = pframe[hdrlen+4]; ++ pn_vector[3] = pframe[hdrlen+5]; ++ pn_vector[4] = pframe[hdrlen+6]; ++ pn_vector[5] = pframe[hdrlen+7]; ++ ++ if ((hdrlen == WLAN_HDR_A3_LEN )||(hdrlen == WLAN_HDR_A3_QOS_LEN)) ++ a4_exists = 0; ++ else ++ a4_exists = 1; ++ ++ if ( ++ (frtype == WIFI_DATA_CFACK) || ++ (frtype == WIFI_DATA_CFPOLL)|| ++ (frtype == WIFI_DATA_CFACKPOLL)) ++ { ++ qc_exists = 1; ++ if(hdrlen != WLAN_HDR_A3_QOS_LEN){ ++ ++ hdrlen += 2; ++ } ++ } ++ else if ( ++ (frsubtype == 0x08) || ++ (frsubtype == 0x09)|| ++ (frsubtype == 0x0a)|| ++ (frsubtype == 0x0b)) ++ { ++ if(hdrlen != WLAN_HDR_A3_QOS_LEN){ ++ ++ hdrlen += 2; ++ } ++ qc_exists = 1; ++ } ++ else ++ qc_exists = 0; ++ ++ ++ // now, decrypt pframe with hdrlen offset and plen long ++ ++ payload_index = hdrlen + 8; // 8 is for extiv ++ ++ for (i=0; i< num_blocks; i++) ++ { ++ construct_ctr_preload( ++ ctr_preload, ++ a4_exists, ++ qc_exists, ++ pframe, ++ pn_vector, ++ i+1 ++ ); ++ ++ aes128k128d(key, ctr_preload, aes_out); ++ bitwise_xor(aes_out, &pframe[payload_index], chain_buffer); ++ ++ for (j=0; j<16;j++) pframe[payload_index++] = chain_buffer[j]; ++ } ++ ++ if (payload_remainder > 0) /* If there is a short final block, then pad it,*/ ++ { /* encrypt it and copy the unpadded part back */ ++ construct_ctr_preload( ++ ctr_preload, ++ a4_exists, ++ qc_exists, ++ pframe, ++ pn_vector, ++ num_blocks+1 ++ ); ++ ++ for (j = 0; j < 16; j++) padded_buffer[j] = 0x00; ++ for (j = 0; j < payload_remainder; j++) ++ { ++ padded_buffer[j] = pframe[payload_index+j]; ++ } ++ aes128k128d(key, ctr_preload, aes_out); ++ bitwise_xor(aes_out, padded_buffer, chain_buffer); ++ for (j=0; j 0) ++ { ++ for (j = 0; j < 16; j++) padded_buffer[j] = 0x00; ++ for (j = 0; j < payload_remainder; j++) ++ { ++ padded_buffer[j] = message[payload_index++]; ++ } ++ bitwise_xor(aes_out, padded_buffer, chain_buffer); ++ aes128k128d(key, chain_buffer, aes_out); ++ ++ } ++ ++ for (j = 0 ; j < 8; j++) mic[j] = aes_out[j]; ++ ++ /* Insert MIC into payload */ ++ for (j = 0; j < 8; j++) ++ message[payload_index+j] = mic[j]; ++ ++ payload_index = hdrlen + 8; ++ for (i=0; i< num_blocks; i++) ++ { ++ construct_ctr_preload( ++ ctr_preload, ++ a4_exists, ++ qc_exists, ++ message, ++ pn_vector, ++ i+1); ++ aes128k128d(key, ctr_preload, aes_out); ++ bitwise_xor(aes_out, &message[payload_index], chain_buffer); ++ for (j=0; j<16;j++) message[payload_index++] = chain_buffer[j]; ++ } ++ ++ if (payload_remainder > 0) /* If there is a short final block, then pad it,*/ ++ { /* encrypt it and copy the unpadded part back */ ++ construct_ctr_preload( ++ ctr_preload, ++ a4_exists, ++ qc_exists, ++ message, ++ pn_vector, ++ num_blocks+1); ++ ++ for (j = 0; j < 16; j++) padded_buffer[j] = 0x00; ++ for (j = 0; j < payload_remainder; j++) ++ { ++ padded_buffer[j] = message[payload_index+j]; ++ } ++ aes128k128d(key, ctr_preload, aes_out); ++ bitwise_xor(aes_out, padded_buffer, chain_buffer); ++ for (j=0; ju.hdr.attrib; ++ struct security_priv *psecuritypriv=&padapter->securitypriv; ++// struct recv_priv *precvpriv=&padapter->recvpriv; ++ u32 res=_SUCCESS; ++_func_enter_; ++ pframe=(unsigned char *)((union recv_frame*)precvframe)->u.hdr.rx_data; ++ //4 start to encrypt each fragment ++ if((prxattrib->encrypt==_AES_)){ ++ ++ stainfo=rtw_get_stainfo(&padapter->stapriv ,&prxattrib->ta[0] ); ++ if (stainfo!=NULL){ ++ RT_TRACE(_module_rtl871x_security_c_,_drv_err_,("rtw_aes_decrypt: stainfo!=NULL!!!\n")); ++ ++ if(IS_MCAST(prxattrib->ra)) ++ { ++ if(psecuritypriv->binstallGrpkey==_FALSE) ++ { ++ res=_FAIL; ++ DBG_8192C("%s:rx bc/mc packets,but didn't install group key!!!!!!!!!!\n",__FUNCTION__); ++ goto exit; ++ } ++ ++ DBG_871X("rx bc/mc packets, to perform sw rtw_aes_decrypt\n"); ++ //prwskey = psecuritypriv->dot118021XGrpKey[psecuritypriv->dot118021XGrpKeyid].skey; ++ prwskey = psecuritypriv->dot118021XGrpKey[prxattrib->key_index].skey; ++ prwskeylen=16; ++ } ++ else ++ { ++ prwskey=&stainfo->dot118021x_UncstKey.skey[0]; ++ prwskeylen=16; ++ } ++ ++ length= ((union recv_frame *)precvframe)->u.hdr.len-prxattrib->hdrlen-prxattrib->iv_len; ++ ++ res= aes_decipher(prwskey,prxattrib->hdrlen,pframe, length); ++ ++ ++ } ++ else{ ++ RT_TRACE(_module_rtl871x_security_c_,_drv_err_,("rtw_aes_encrypt: stainfo==NULL!!!\n")); ++ res=_FAIL; ++ } ++ ++ } ++_func_exit_; ++exit: ++ return res; ++} ++ ++/* compress 512-bits */ ++static int sha256_compress(struct sha256_state *md, unsigned char *buf) ++{ ++ u32 S[8], W[64], t0, t1; ++ u32 t; ++ int i; ++ ++ /* copy state into S */ ++ for (i = 0; i < 8; i++) { ++ S[i] = md->state[i]; ++ } ++ ++ /* copy the state into 512-bits into W[0..15] */ ++ for (i = 0; i < 16; i++) ++ W[i] = WPA_GET_BE32(buf + (4 * i)); ++ ++ /* fill W[16..63] */ ++ for (i = 16; i < 64; i++) { ++ W[i] = Gamma1(W[i - 2]) + W[i - 7] + Gamma0(W[i - 15]) + ++ W[i - 16]; ++ } ++ ++ /* Compress */ ++#define RND(a,b,c,d,e,f,g,h,i) \ ++ t0 = h + Sigma1(e) + Ch(e, f, g) + K[i] + W[i]; \ ++ t1 = Sigma0(a) + Maj(a, b, c); \ ++ d += t0; \ ++ h = t0 + t1; ++ ++ for (i = 0; i < 64; ++i) { ++ RND(S[0], S[1], S[2], S[3], S[4], S[5], S[6], S[7], i); ++ t = S[7]; S[7] = S[6]; S[6] = S[5]; S[5] = S[4]; ++ S[4] = S[3]; S[3] = S[2]; S[2] = S[1]; S[1] = S[0]; S[0] = t; ++ } ++ ++ /* feedback */ ++ for (i = 0; i < 8; i++) { ++ md->state[i] = md->state[i] + S[i]; ++ } ++ return 0; ++} ++ ++/* Initialize the hash state */ ++static void sha256_init(struct sha256_state *md) ++{ ++ md->curlen = 0; ++ md->length = 0; ++ md->state[0] = 0x6A09E667UL; ++ md->state[1] = 0xBB67AE85UL; ++ md->state[2] = 0x3C6EF372UL; ++ md->state[3] = 0xA54FF53AUL; ++ md->state[4] = 0x510E527FUL; ++ md->state[5] = 0x9B05688CUL; ++ md->state[6] = 0x1F83D9ABUL; ++ md->state[7] = 0x5BE0CD19UL; ++} ++ ++/** ++ Process a block of memory though the hash ++ @param md The hash state ++ @param in The data to hash ++ @param inlen The length of the data (octets) ++ @return CRYPT_OK if successful ++*/ ++static int sha256_process(struct sha256_state *md, unsigned char *in, ++ unsigned long inlen) ++{ ++ unsigned long n; ++#define block_size 64 ++ ++ if (md->curlen > sizeof(md->buf)) ++ return -1; ++ ++ while (inlen > 0) { ++ if (md->curlen == 0 && inlen >= block_size) { ++ if (sha256_compress(md, (unsigned char *) in) < 0) ++ return -1; ++ md->length += block_size * 8; ++ in += block_size; ++ inlen -= block_size; ++ } else { ++ n = MIN(inlen, (block_size - md->curlen)); ++ _rtw_memcpy(md->buf + md->curlen, in, n); ++ md->curlen += n; ++ in += n; ++ inlen -= n; ++ if (md->curlen == block_size) { ++ if (sha256_compress(md, md->buf) < 0) ++ return -1; ++ md->length += 8 * block_size; ++ md->curlen = 0; ++ } ++ } ++ } ++ ++ return 0; ++} ++ ++ ++/** ++ Terminate the hash to get the digest ++ @param md The hash state ++ @param out [out] The destination of the hash (32 bytes) ++ @return CRYPT_OK if successful ++*/ ++static int sha256_done(struct sha256_state *md, unsigned char *out) ++{ ++ int i; ++ ++ if (md->curlen >= sizeof(md->buf)) ++ return -1; ++ ++ /* increase the length of the message */ ++ md->length += md->curlen * 8; ++ ++ /* append the '1' bit */ ++ md->buf[md->curlen++] = (unsigned char) 0x80; ++ ++ /* if the length is currently above 56 bytes we append zeros ++ * then compress. Then we can fall back to padding zeros and length ++ * encoding like normal. ++ */ ++ if (md->curlen > 56) { ++ while (md->curlen < 64) { ++ md->buf[md->curlen++] = (unsigned char) 0; ++ } ++ sha256_compress(md, md->buf); ++ md->curlen = 0; ++ } ++ ++ /* pad upto 56 bytes of zeroes */ ++ while (md->curlen < 56) { ++ md->buf[md->curlen++] = (unsigned char) 0; ++ } ++ ++ /* store length */ ++ WPA_PUT_BE64(md->buf + 56, md->length); ++ sha256_compress(md, md->buf); ++ ++ /* copy output */ ++ for (i = 0; i < 8; i++) ++ WPA_PUT_BE32(out + (4 * i), md->state[i]); ++ ++ return 0; ++} ++ ++/** ++ * sha256_vector - SHA256 hash for data vector ++ * @num_elem: Number of elements in the data vector ++ * @addr: Pointers to the data areas ++ * @len: Lengths of the data blocks ++ * @mac: Buffer for the hash ++ * Returns: 0 on success, -1 of failure ++ */ ++static int sha256_vector(size_t num_elem, u8 *addr[], size_t *len, ++ u8 *mac) ++{ ++ struct sha256_state ctx; ++ size_t i; ++ ++ sha256_init(&ctx); ++ for (i = 0; i < num_elem; i++) ++ if (sha256_process(&ctx, addr[i], len[i])) ++ return -1; ++ if (sha256_done(&ctx, mac)) ++ return -1; ++ return 0; ++} ++ ++static u8 os_strlen(const char *s) ++{ ++ const char *p = s; ++ while (*p) ++ p++; ++ return p - s; ++} ++ ++static int os_memcmp(void *s1, void *s2, u8 n) ++{ ++ unsigned char *p1 = s1, *p2 = s2; ++ ++ if (n == 0) ++ return 0; ++ ++ while (*p1 == *p2) { ++ p1++; ++ p2++; ++ n--; ++ if (n == 0) ++ return 0; ++ } ++ ++ return *p1 - *p2; ++} ++ ++/** ++ * hmac_sha256_vector - HMAC-SHA256 over data vector (RFC 2104) ++ * @key: Key for HMAC operations ++ * @key_len: Length of the key in bytes ++ * @num_elem: Number of elements in the data vector ++ * @addr: Pointers to the data areas ++ * @len: Lengths of the data blocks ++ * @mac: Buffer for the hash (32 bytes) ++ */ ++static void hmac_sha256_vector(u8 *key, size_t key_len, size_t num_elem, ++ u8 *addr[], size_t *len, u8 *mac) ++{ ++ unsigned char k_pad[64]; /* padding - key XORd with ipad/opad */ ++ unsigned char tk[32]; ++ u8 *_addr[6]; ++ size_t _len[6], i; ++ ++ if (num_elem > 5) { ++ /* ++ * Fixed limit on the number of fragments to avoid having to ++ * allocate memory (which could fail). ++ */ ++ return; ++ } ++ ++ /* if key is longer than 64 bytes reset it to key = SHA256(key) */ ++ if (key_len > 64) { ++ sha256_vector(1, &key, &key_len, tk); ++ key = tk; ++ key_len = 32; ++ } ++ ++ /* the HMAC_SHA256 transform looks like: ++ * ++ * SHA256(K XOR opad, SHA256(K XOR ipad, text)) ++ * ++ * where K is an n byte key ++ * ipad is the byte 0x36 repeated 64 times ++ * opad is the byte 0x5c repeated 64 times ++ * and text is the data being protected */ ++ ++ /* start out by storing key in ipad */ ++ _rtw_memset(k_pad, 0, sizeof(k_pad)); ++ _rtw_memcpy(k_pad, key, key_len); ++ /* XOR key with ipad values */ ++ for (i = 0; i < 64; i++) ++ k_pad[i] ^= 0x36; ++ ++ /* perform inner SHA256 */ ++ _addr[0] = k_pad; ++ _len[0] = 64; ++ for (i = 0; i < num_elem; i++) { ++ _addr[i + 1] = addr[i]; ++ _len[i + 1] = len[i]; ++ } ++ sha256_vector(1 + num_elem, _addr, _len, mac); ++ ++ _rtw_memset(k_pad, 0, sizeof(k_pad)); ++ _rtw_memcpy(k_pad, key, key_len); ++ /* XOR key with opad values */ ++ for (i = 0; i < 64; i++) ++ k_pad[i] ^= 0x5c; ++ ++ /* perform outer SHA256 */ ++ _addr[0] = k_pad; ++ _len[0] = 64; ++ _addr[1] = mac; ++ _len[1] = 32; ++ sha256_vector(2, _addr, _len, mac); ++} ++ ++/** ++ * sha256_prf - SHA256-based Pseudo-Random Function (IEEE 802.11r, 8.5.1.5.2) ++ * @key: Key for PRF ++ * @key_len: Length of the key in bytes ++ * @label: A unique label for each purpose of the PRF ++ * @data: Extra data to bind into the key ++ * @data_len: Length of the data ++ * @buf: Buffer for the generated pseudo-random key ++ * @buf_len: Number of bytes of key to generate ++ * ++ * This function is used to derive new, cryptographically separate keys from a ++ * given key. ++ */ ++static void sha256_prf(u8 *key, size_t key_len, char *label, ++ u8 *data, size_t data_len, u8 *buf, size_t buf_len) ++{ ++ u16 counter = 1; ++ size_t pos, plen; ++ u8 hash[SHA256_MAC_LEN]; ++ u8 *addr[4]; ++ size_t len[4]; ++ u8 counter_le[2], length_le[2]; ++ ++ addr[0] = counter_le; ++ len[0] = 2; ++ addr[1] = (u8 *) label; ++ len[1] = os_strlen(label); ++ addr[2] = data; ++ len[2] = data_len; ++ addr[3] = length_le; ++ len[3] = sizeof(length_le); ++ ++ WPA_PUT_LE16(length_le, buf_len * 8); ++ pos = 0; ++ while (pos < buf_len) { ++ plen = buf_len - pos; ++ WPA_PUT_LE16(counter_le, counter); ++ if (plen >= SHA256_MAC_LEN) { ++ hmac_sha256_vector(key, key_len, 4, addr, len, ++ &buf[pos]); ++ pos += SHA256_MAC_LEN; ++ } else { ++ hmac_sha256_vector(key, key_len, 4, addr, len, hash); ++ _rtw_memcpy(&buf[pos], hash, plen); ++ break; ++ } ++ counter++; ++ } ++} ++ ++/* AES tables*/ ++const u32 Te0[256] = { ++ 0xc66363a5U, 0xf87c7c84U, 0xee777799U, 0xf67b7b8dU, ++ 0xfff2f20dU, 0xd66b6bbdU, 0xde6f6fb1U, 0x91c5c554U, ++ 0x60303050U, 0x02010103U, 0xce6767a9U, 0x562b2b7dU, ++ 0xe7fefe19U, 0xb5d7d762U, 0x4dababe6U, 0xec76769aU, ++ 0x8fcaca45U, 0x1f82829dU, 0x89c9c940U, 0xfa7d7d87U, ++ 0xeffafa15U, 0xb25959ebU, 0x8e4747c9U, 0xfbf0f00bU, ++ 0x41adadecU, 0xb3d4d467U, 0x5fa2a2fdU, 0x45afafeaU, ++ 0x239c9cbfU, 0x53a4a4f7U, 0xe4727296U, 0x9bc0c05bU, ++ 0x75b7b7c2U, 0xe1fdfd1cU, 0x3d9393aeU, 0x4c26266aU, ++ 0x6c36365aU, 0x7e3f3f41U, 0xf5f7f702U, 0x83cccc4fU, ++ 0x6834345cU, 0x51a5a5f4U, 0xd1e5e534U, 0xf9f1f108U, ++ 0xe2717193U, 0xabd8d873U, 0x62313153U, 0x2a15153fU, ++ 0x0804040cU, 0x95c7c752U, 0x46232365U, 0x9dc3c35eU, ++ 0x30181828U, 0x379696a1U, 0x0a05050fU, 0x2f9a9ab5U, ++ 0x0e070709U, 0x24121236U, 0x1b80809bU, 0xdfe2e23dU, ++ 0xcdebeb26U, 0x4e272769U, 0x7fb2b2cdU, 0xea75759fU, ++ 0x1209091bU, 0x1d83839eU, 0x582c2c74U, 0x341a1a2eU, ++ 0x361b1b2dU, 0xdc6e6eb2U, 0xb45a5aeeU, 0x5ba0a0fbU, ++ 0xa45252f6U, 0x763b3b4dU, 0xb7d6d661U, 0x7db3b3ceU, ++ 0x5229297bU, 0xdde3e33eU, 0x5e2f2f71U, 0x13848497U, ++ 0xa65353f5U, 0xb9d1d168U, 0x00000000U, 0xc1eded2cU, ++ 0x40202060U, 0xe3fcfc1fU, 0x79b1b1c8U, 0xb65b5bedU, ++ 0xd46a6abeU, 0x8dcbcb46U, 0x67bebed9U, 0x7239394bU, ++ 0x944a4adeU, 0x984c4cd4U, 0xb05858e8U, 0x85cfcf4aU, ++ 0xbbd0d06bU, 0xc5efef2aU, 0x4faaaae5U, 0xedfbfb16U, ++ 0x864343c5U, 0x9a4d4dd7U, 0x66333355U, 0x11858594U, ++ 0x8a4545cfU, 0xe9f9f910U, 0x04020206U, 0xfe7f7f81U, ++ 0xa05050f0U, 0x783c3c44U, 0x259f9fbaU, 0x4ba8a8e3U, ++ 0xa25151f3U, 0x5da3a3feU, 0x804040c0U, 0x058f8f8aU, ++ 0x3f9292adU, 0x219d9dbcU, 0x70383848U, 0xf1f5f504U, ++ 0x63bcbcdfU, 0x77b6b6c1U, 0xafdada75U, 0x42212163U, ++ 0x20101030U, 0xe5ffff1aU, 0xfdf3f30eU, 0xbfd2d26dU, ++ 0x81cdcd4cU, 0x180c0c14U, 0x26131335U, 0xc3ecec2fU, ++ 0xbe5f5fe1U, 0x359797a2U, 0x884444ccU, 0x2e171739U, ++ 0x93c4c457U, 0x55a7a7f2U, 0xfc7e7e82U, 0x7a3d3d47U, ++ 0xc86464acU, 0xba5d5de7U, 0x3219192bU, 0xe6737395U, ++ 0xc06060a0U, 0x19818198U, 0x9e4f4fd1U, 0xa3dcdc7fU, ++ 0x44222266U, 0x542a2a7eU, 0x3b9090abU, 0x0b888883U, ++ 0x8c4646caU, 0xc7eeee29U, 0x6bb8b8d3U, 0x2814143cU, ++ 0xa7dede79U, 0xbc5e5ee2U, 0x160b0b1dU, 0xaddbdb76U, ++ 0xdbe0e03bU, 0x64323256U, 0x743a3a4eU, 0x140a0a1eU, ++ 0x924949dbU, 0x0c06060aU, 0x4824246cU, 0xb85c5ce4U, ++ 0x9fc2c25dU, 0xbdd3d36eU, 0x43acacefU, 0xc46262a6U, ++ 0x399191a8U, 0x319595a4U, 0xd3e4e437U, 0xf279798bU, ++ 0xd5e7e732U, 0x8bc8c843U, 0x6e373759U, 0xda6d6db7U, ++ 0x018d8d8cU, 0xb1d5d564U, 0x9c4e4ed2U, 0x49a9a9e0U, ++ 0xd86c6cb4U, 0xac5656faU, 0xf3f4f407U, 0xcfeaea25U, ++ 0xca6565afU, 0xf47a7a8eU, 0x47aeaee9U, 0x10080818U, ++ 0x6fbabad5U, 0xf0787888U, 0x4a25256fU, 0x5c2e2e72U, ++ 0x381c1c24U, 0x57a6a6f1U, 0x73b4b4c7U, 0x97c6c651U, ++ 0xcbe8e823U, 0xa1dddd7cU, 0xe874749cU, 0x3e1f1f21U, ++ 0x964b4bddU, 0x61bdbddcU, 0x0d8b8b86U, 0x0f8a8a85U, ++ 0xe0707090U, 0x7c3e3e42U, 0x71b5b5c4U, 0xcc6666aaU, ++ 0x904848d8U, 0x06030305U, 0xf7f6f601U, 0x1c0e0e12U, ++ 0xc26161a3U, 0x6a35355fU, 0xae5757f9U, 0x69b9b9d0U, ++ 0x17868691U, 0x99c1c158U, 0x3a1d1d27U, 0x279e9eb9U, ++ 0xd9e1e138U, 0xebf8f813U, 0x2b9898b3U, 0x22111133U, ++ 0xd26969bbU, 0xa9d9d970U, 0x078e8e89U, 0x339494a7U, ++ 0x2d9b9bb6U, 0x3c1e1e22U, 0x15878792U, 0xc9e9e920U, ++ 0x87cece49U, 0xaa5555ffU, 0x50282878U, 0xa5dfdf7aU, ++ 0x038c8c8fU, 0x59a1a1f8U, 0x09898980U, 0x1a0d0d17U, ++ 0x65bfbfdaU, 0xd7e6e631U, 0x844242c6U, 0xd06868b8U, ++ 0x824141c3U, 0x299999b0U, 0x5a2d2d77U, 0x1e0f0f11U, ++ 0x7bb0b0cbU, 0xa85454fcU, 0x6dbbbbd6U, 0x2c16163aU, ++}; ++const u32 Td0[256] = { ++ 0x51f4a750U, 0x7e416553U, 0x1a17a4c3U, 0x3a275e96U, ++ 0x3bab6bcbU, 0x1f9d45f1U, 0xacfa58abU, 0x4be30393U, ++ 0x2030fa55U, 0xad766df6U, 0x88cc7691U, 0xf5024c25U, ++ 0x4fe5d7fcU, 0xc52acbd7U, 0x26354480U, 0xb562a38fU, ++ 0xdeb15a49U, 0x25ba1b67U, 0x45ea0e98U, 0x5dfec0e1U, ++ 0xc32f7502U, 0x814cf012U, 0x8d4697a3U, 0x6bd3f9c6U, ++ 0x038f5fe7U, 0x15929c95U, 0xbf6d7aebU, 0x955259daU, ++ 0xd4be832dU, 0x587421d3U, 0x49e06929U, 0x8ec9c844U, ++ 0x75c2896aU, 0xf48e7978U, 0x99583e6bU, 0x27b971ddU, ++ 0xbee14fb6U, 0xf088ad17U, 0xc920ac66U, 0x7dce3ab4U, ++ 0x63df4a18U, 0xe51a3182U, 0x97513360U, 0x62537f45U, ++ 0xb16477e0U, 0xbb6bae84U, 0xfe81a01cU, 0xf9082b94U, ++ 0x70486858U, 0x8f45fd19U, 0x94de6c87U, 0x527bf8b7U, ++ 0xab73d323U, 0x724b02e2U, 0xe31f8f57U, 0x6655ab2aU, ++ 0xb2eb2807U, 0x2fb5c203U, 0x86c57b9aU, 0xd33708a5U, ++ 0x302887f2U, 0x23bfa5b2U, 0x02036abaU, 0xed16825cU, ++ 0x8acf1c2bU, 0xa779b492U, 0xf307f2f0U, 0x4e69e2a1U, ++ 0x65daf4cdU, 0x0605bed5U, 0xd134621fU, 0xc4a6fe8aU, ++ 0x342e539dU, 0xa2f355a0U, 0x058ae132U, 0xa4f6eb75U, ++ 0x0b83ec39U, 0x4060efaaU, 0x5e719f06U, 0xbd6e1051U, ++ 0x3e218af9U, 0x96dd063dU, 0xdd3e05aeU, 0x4de6bd46U, ++ 0x91548db5U, 0x71c45d05U, 0x0406d46fU, 0x605015ffU, ++ 0x1998fb24U, 0xd6bde997U, 0x894043ccU, 0x67d99e77U, ++ 0xb0e842bdU, 0x07898b88U, 0xe7195b38U, 0x79c8eedbU, ++ 0xa17c0a47U, 0x7c420fe9U, 0xf8841ec9U, 0x00000000U, ++ 0x09808683U, 0x322bed48U, 0x1e1170acU, 0x6c5a724eU, ++ 0xfd0efffbU, 0x0f853856U, 0x3daed51eU, 0x362d3927U, ++ 0x0a0fd964U, 0x685ca621U, 0x9b5b54d1U, 0x24362e3aU, ++ 0x0c0a67b1U, 0x9357e70fU, 0xb4ee96d2U, 0x1b9b919eU, ++ 0x80c0c54fU, 0x61dc20a2U, 0x5a774b69U, 0x1c121a16U, ++ 0xe293ba0aU, 0xc0a02ae5U, 0x3c22e043U, 0x121b171dU, ++ 0x0e090d0bU, 0xf28bc7adU, 0x2db6a8b9U, 0x141ea9c8U, ++ 0x57f11985U, 0xaf75074cU, 0xee99ddbbU, 0xa37f60fdU, ++ 0xf701269fU, 0x5c72f5bcU, 0x44663bc5U, 0x5bfb7e34U, ++ 0x8b432976U, 0xcb23c6dcU, 0xb6edfc68U, 0xb8e4f163U, ++ 0xd731dccaU, 0x42638510U, 0x13972240U, 0x84c61120U, ++ 0x854a247dU, 0xd2bb3df8U, 0xaef93211U, 0xc729a16dU, ++ 0x1d9e2f4bU, 0xdcb230f3U, 0x0d8652ecU, 0x77c1e3d0U, ++ 0x2bb3166cU, 0xa970b999U, 0x119448faU, 0x47e96422U, ++ 0xa8fc8cc4U, 0xa0f03f1aU, 0x567d2cd8U, 0x223390efU, ++ 0x87494ec7U, 0xd938d1c1U, 0x8ccaa2feU, 0x98d40b36U, ++ 0xa6f581cfU, 0xa57ade28U, 0xdab78e26U, 0x3fadbfa4U, ++ 0x2c3a9de4U, 0x5078920dU, 0x6a5fcc9bU, 0x547e4662U, ++ 0xf68d13c2U, 0x90d8b8e8U, 0x2e39f75eU, 0x82c3aff5U, ++ 0x9f5d80beU, 0x69d0937cU, 0x6fd52da9U, 0xcf2512b3U, ++ 0xc8ac993bU, 0x10187da7U, 0xe89c636eU, 0xdb3bbb7bU, ++ 0xcd267809U, 0x6e5918f4U, 0xec9ab701U, 0x834f9aa8U, ++ 0xe6956e65U, 0xaaffe67eU, 0x21bccf08U, 0xef15e8e6U, ++ 0xbae79bd9U, 0x4a6f36ceU, 0xea9f09d4U, 0x29b07cd6U, ++ 0x31a4b2afU, 0x2a3f2331U, 0xc6a59430U, 0x35a266c0U, ++ 0x744ebc37U, 0xfc82caa6U, 0xe090d0b0U, 0x33a7d815U, ++ 0xf104984aU, 0x41ecdaf7U, 0x7fcd500eU, 0x1791f62fU, ++ 0x764dd68dU, 0x43efb04dU, 0xccaa4d54U, 0xe49604dfU, ++ 0x9ed1b5e3U, 0x4c6a881bU, 0xc12c1fb8U, 0x4665517fU, ++ 0x9d5eea04U, 0x018c355dU, 0xfa877473U, 0xfb0b412eU, ++ 0xb3671d5aU, 0x92dbd252U, 0xe9105633U, 0x6dd64713U, ++ 0x9ad7618cU, 0x37a10c7aU, 0x59f8148eU, 0xeb133c89U, ++ 0xcea927eeU, 0xb761c935U, 0xe11ce5edU, 0x7a47b13cU, ++ 0x9cd2df59U, 0x55f2733fU, 0x1814ce79U, 0x73c737bfU, ++ 0x53f7cdeaU, 0x5ffdaa5bU, 0xdf3d6f14U, 0x7844db86U, ++ 0xcaaff381U, 0xb968c43eU, 0x3824342cU, 0xc2a3405fU, ++ 0x161dc372U, 0xbce2250cU, 0x283c498bU, 0xff0d9541U, ++ 0x39a80171U, 0x080cb3deU, 0xd8b4e49cU, 0x6456c190U, ++ 0x7bcb8461U, 0xd532b670U, 0x486c5c74U, 0xd0b85742U, ++}; ++const u8 Td4s[256] = { ++ 0x52U, 0x09U, 0x6aU, 0xd5U, 0x30U, 0x36U, 0xa5U, 0x38U, ++ 0xbfU, 0x40U, 0xa3U, 0x9eU, 0x81U, 0xf3U, 0xd7U, 0xfbU, ++ 0x7cU, 0xe3U, 0x39U, 0x82U, 0x9bU, 0x2fU, 0xffU, 0x87U, ++ 0x34U, 0x8eU, 0x43U, 0x44U, 0xc4U, 0xdeU, 0xe9U, 0xcbU, ++ 0x54U, 0x7bU, 0x94U, 0x32U, 0xa6U, 0xc2U, 0x23U, 0x3dU, ++ 0xeeU, 0x4cU, 0x95U, 0x0bU, 0x42U, 0xfaU, 0xc3U, 0x4eU, ++ 0x08U, 0x2eU, 0xa1U, 0x66U, 0x28U, 0xd9U, 0x24U, 0xb2U, ++ 0x76U, 0x5bU, 0xa2U, 0x49U, 0x6dU, 0x8bU, 0xd1U, 0x25U, ++ 0x72U, 0xf8U, 0xf6U, 0x64U, 0x86U, 0x68U, 0x98U, 0x16U, ++ 0xd4U, 0xa4U, 0x5cU, 0xccU, 0x5dU, 0x65U, 0xb6U, 0x92U, ++ 0x6cU, 0x70U, 0x48U, 0x50U, 0xfdU, 0xedU, 0xb9U, 0xdaU, ++ 0x5eU, 0x15U, 0x46U, 0x57U, 0xa7U, 0x8dU, 0x9dU, 0x84U, ++ 0x90U, 0xd8U, 0xabU, 0x00U, 0x8cU, 0xbcU, 0xd3U, 0x0aU, ++ 0xf7U, 0xe4U, 0x58U, 0x05U, 0xb8U, 0xb3U, 0x45U, 0x06U, ++ 0xd0U, 0x2cU, 0x1eU, 0x8fU, 0xcaU, 0x3fU, 0x0fU, 0x02U, ++ 0xc1U, 0xafU, 0xbdU, 0x03U, 0x01U, 0x13U, 0x8aU, 0x6bU, ++ 0x3aU, 0x91U, 0x11U, 0x41U, 0x4fU, 0x67U, 0xdcU, 0xeaU, ++ 0x97U, 0xf2U, 0xcfU, 0xceU, 0xf0U, 0xb4U, 0xe6U, 0x73U, ++ 0x96U, 0xacU, 0x74U, 0x22U, 0xe7U, 0xadU, 0x35U, 0x85U, ++ 0xe2U, 0xf9U, 0x37U, 0xe8U, 0x1cU, 0x75U, 0xdfU, 0x6eU, ++ 0x47U, 0xf1U, 0x1aU, 0x71U, 0x1dU, 0x29U, 0xc5U, 0x89U, ++ 0x6fU, 0xb7U, 0x62U, 0x0eU, 0xaaU, 0x18U, 0xbeU, 0x1bU, ++ 0xfcU, 0x56U, 0x3eU, 0x4bU, 0xc6U, 0xd2U, 0x79U, 0x20U, ++ 0x9aU, 0xdbU, 0xc0U, 0xfeU, 0x78U, 0xcdU, 0x5aU, 0xf4U, ++ 0x1fU, 0xddU, 0xa8U, 0x33U, 0x88U, 0x07U, 0xc7U, 0x31U, ++ 0xb1U, 0x12U, 0x10U, 0x59U, 0x27U, 0x80U, 0xecU, 0x5fU, ++ 0x60U, 0x51U, 0x7fU, 0xa9U, 0x19U, 0xb5U, 0x4aU, 0x0dU, ++ 0x2dU, 0xe5U, 0x7aU, 0x9fU, 0x93U, 0xc9U, 0x9cU, 0xefU, ++ 0xa0U, 0xe0U, 0x3bU, 0x4dU, 0xaeU, 0x2aU, 0xf5U, 0xb0U, ++ 0xc8U, 0xebU, 0xbbU, 0x3cU, 0x83U, 0x53U, 0x99U, 0x61U, ++ 0x17U, 0x2bU, 0x04U, 0x7eU, 0xbaU, 0x77U, 0xd6U, 0x26U, ++ 0xe1U, 0x69U, 0x14U, 0x63U, 0x55U, 0x21U, 0x0cU, 0x7dU, ++}; ++const u8 rcons[] = { ++ 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0x1B, 0x36 ++ /* for 128-bit blocks, Rijndael never uses more than 10 rcon values */ ++}; ++ ++/** ++ * Expand the cipher key into the encryption key schedule. ++ * ++ * @return the number of rounds for the given cipher key size. ++ */ ++static void rijndaelKeySetupEnc(u32 rk[/*44*/], const u8 cipherKey[]) ++{ ++ int i; ++ u32 temp; ++ ++ rk[0] = GETU32(cipherKey ); ++ rk[1] = GETU32(cipherKey + 4); ++ rk[2] = GETU32(cipherKey + 8); ++ rk[3] = GETU32(cipherKey + 12); ++ for (i = 0; i < 10; i++) { ++ temp = rk[3]; ++ rk[4] = rk[0] ^ ++ TE421(temp) ^ TE432(temp) ^ TE443(temp) ^ TE414(temp) ^ ++ RCON(i); ++ rk[5] = rk[1] ^ rk[4]; ++ rk[6] = rk[2] ^ rk[5]; ++ rk[7] = rk[3] ^ rk[6]; ++ rk += 4; ++ } ++} ++ ++static void rijndaelEncrypt(u32 rk[/*44*/], u8 pt[16], u8 ct[16]) ++{ ++ u32 s0, s1, s2, s3, t0, t1, t2, t3; ++ int Nr = 10; ++#ifndef FULL_UNROLL ++ int r; ++#endif /* ?FULL_UNROLL */ ++ ++ /* ++ * map byte array block to cipher state ++ * and add initial round key: ++ */ ++ s0 = GETU32(pt ) ^ rk[0]; ++ s1 = GETU32(pt + 4) ^ rk[1]; ++ s2 = GETU32(pt + 8) ^ rk[2]; ++ s3 = GETU32(pt + 12) ^ rk[3]; ++ ++#define ROUND(i,d,s) \ ++d##0 = TE0(s##0) ^ TE1(s##1) ^ TE2(s##2) ^ TE3(s##3) ^ rk[4 * i]; \ ++d##1 = TE0(s##1) ^ TE1(s##2) ^ TE2(s##3) ^ TE3(s##0) ^ rk[4 * i + 1]; \ ++d##2 = TE0(s##2) ^ TE1(s##3) ^ TE2(s##0) ^ TE3(s##1) ^ rk[4 * i + 2]; \ ++d##3 = TE0(s##3) ^ TE1(s##0) ^ TE2(s##1) ^ TE3(s##2) ^ rk[4 * i + 3] ++ ++#ifdef FULL_UNROLL ++ ++ ROUND(1,t,s); ++ ROUND(2,s,t); ++ ROUND(3,t,s); ++ ROUND(4,s,t); ++ ROUND(5,t,s); ++ ROUND(6,s,t); ++ ROUND(7,t,s); ++ ROUND(8,s,t); ++ ROUND(9,t,s); ++ ++ rk += Nr << 2; ++ ++#else /* !FULL_UNROLL */ ++ ++ /* Nr - 1 full rounds: */ ++ r = Nr >> 1; ++ for (;;) { ++ ROUND(1,t,s); ++ rk += 8; ++ if (--r == 0) ++ break; ++ ROUND(0,s,t); ++ } ++ ++#endif /* ?FULL_UNROLL */ ++ ++#undef ROUND ++ ++ /* ++ * apply last round and ++ * map cipher state to byte array block: ++ */ ++ s0 = TE41(t0) ^ TE42(t1) ^ TE43(t2) ^ TE44(t3) ^ rk[0]; ++ PUTU32(ct , s0); ++ s1 = TE41(t1) ^ TE42(t2) ^ TE43(t3) ^ TE44(t0) ^ rk[1]; ++ PUTU32(ct + 4, s1); ++ s2 = TE41(t2) ^ TE42(t3) ^ TE43(t0) ^ TE44(t1) ^ rk[2]; ++ PUTU32(ct + 8, s2); ++ s3 = TE41(t3) ^ TE42(t0) ^ TE43(t1) ^ TE44(t2) ^ rk[3]; ++ PUTU32(ct + 12, s3); ++} ++ ++static void * aes_encrypt_init(u8 *key, size_t len) ++{ ++ u32 *rk; ++ if (len != 16) ++ return NULL; ++ rk = (u32*)rtw_malloc(AES_PRIV_SIZE); ++ if (rk == NULL) ++ return NULL; ++ rijndaelKeySetupEnc(rk, key); ++ return rk; ++} ++ ++static void aes_128_encrypt(void *ctx, u8 *plain, u8 *crypt) ++{ ++ rijndaelEncrypt(ctx, plain, crypt); ++} ++ ++ ++static void gf_mulx(u8 *pad) ++{ ++ int i, carry; ++ ++ carry = pad[0] & 0x80; ++ for (i = 0; i < AES_BLOCK_SIZE - 1; i++) ++ pad[i] = (pad[i] << 1) | (pad[i + 1] >> 7); ++ pad[AES_BLOCK_SIZE - 1] <<= 1; ++ if (carry) ++ pad[AES_BLOCK_SIZE - 1] ^= 0x87; ++} ++ ++static void aes_encrypt_deinit(void *ctx) ++{ ++ _rtw_memset(ctx, 0, AES_PRIV_SIZE); ++ rtw_mfree(ctx, AES_PRIV_SIZE); ++} ++ ++ ++/** ++ * omac1_aes_128_vector - One-Key CBC MAC (OMAC1) hash with AES-128 ++ * @key: 128-bit key for the hash operation ++ * @num_elem: Number of elements in the data vector ++ * @addr: Pointers to the data areas ++ * @len: Lengths of the data blocks ++ * @mac: Buffer for MAC (128 bits, i.e., 16 bytes) ++ * Returns: 0 on success, -1 on failure ++ * ++ * This is a mode for using block cipher (AES in this case) for authentication. ++ * OMAC1 was standardized with the name CMAC by NIST in a Special Publication ++ * (SP) 800-38B. ++ */ ++static int omac1_aes_128_vector(u8 *key, size_t num_elem, ++ u8 *addr[], size_t *len, u8 *mac) ++{ ++ void *ctx; ++ u8 cbc[AES_BLOCK_SIZE], pad[AES_BLOCK_SIZE]; ++ u8 *pos, *end; ++ size_t i, e, left, total_len; ++ ++ ctx = aes_encrypt_init(key, 16); ++ if (ctx == NULL) ++ return -1; ++ _rtw_memset(cbc, 0, AES_BLOCK_SIZE); ++ ++ total_len = 0; ++ for (e = 0; e < num_elem; e++) ++ total_len += len[e]; ++ left = total_len; ++ ++ e = 0; ++ pos = addr[0]; ++ end = pos + len[0]; ++ ++ while (left >= AES_BLOCK_SIZE) { ++ for (i = 0; i < AES_BLOCK_SIZE; i++) { ++ cbc[i] ^= *pos++; ++ if (pos >= end) { ++ e++; ++ pos = addr[e]; ++ end = pos + len[e]; ++ } ++ } ++ if (left > AES_BLOCK_SIZE) ++ aes_128_encrypt(ctx, cbc, cbc); ++ left -= AES_BLOCK_SIZE; ++ } ++ ++ _rtw_memset(pad, 0, AES_BLOCK_SIZE); ++ aes_128_encrypt(ctx, pad, pad); ++ gf_mulx(pad); ++ ++ if (left || total_len == 0) { ++ for (i = 0; i < left; i++) { ++ cbc[i] ^= *pos++; ++ if (pos >= end) { ++ e++; ++ pos = addr[e]; ++ end = pos + len[e]; ++ } ++ } ++ cbc[left] ^= 0x80; ++ gf_mulx(pad); ++ } ++ ++ for (i = 0; i < AES_BLOCK_SIZE; i++) ++ pad[i] ^= cbc[i]; ++ aes_128_encrypt(ctx, pad, mac); ++ aes_encrypt_deinit(ctx); ++ return 0; ++} ++ ++ ++/** ++ * omac1_aes_128 - One-Key CBC MAC (OMAC1) hash with AES-128 (aka AES-CMAC) ++ * @key: 128-bit key for the hash operation ++ * @data: Data buffer for which a MAC is determined ++ * @data_len: Length of data buffer in bytes ++ * @mac: Buffer for MAC (128 bits, i.e., 16 bytes) ++ * Returns: 0 on success, -1 on failure ++ * ++ * This is a mode for using block cipher (AES in this case) for authentication. ++ * OMAC1 was standardized with the name CMAC by NIST in a Special Publication ++ * (SP) 800-38B. ++ */ ++static int omac1_aes_128(u8 *key, u8 *data, size_t data_len, u8 *mac) ++{ ++ return omac1_aes_128_vector(key, 1, &data, &data_len, mac); ++} ++ ++#ifdef CONFIG_TDLS ++void wpa_tdls_generate_tpk(_adapter *padapter, struct sta_info *psta) ++{ ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ u8 *SNonce = psta->SNonce; ++ u8 *ANonce = psta->ANonce; ++ ++ u8 key_input[SHA256_MAC_LEN]; ++ u8 *nonce[2]; ++ size_t len[2]; ++ u8 data[3 * ETH_ALEN]; ++ ++ /* IEEE Std 802.11z-2010 8.5.9.1: ++ * TPK-Key-Input = SHA-256(min(SNonce, ANonce) || max(SNonce, ANonce)) ++ */ ++ len[0] = 32; ++ len[1] = 32; ++ if (os_memcmp(SNonce, ANonce, 32) < 0) { ++ nonce[0] = SNonce; ++ nonce[1] = ANonce; ++ } else { ++ nonce[0] = ANonce; ++ nonce[1] = SNonce; ++ } ++ ++ sha256_vector(2, nonce, len, key_input); ++ ++ /* ++ * TPK-Key-Data = KDF-N_KEY(TPK-Key-Input, "TDLS PMK", ++ * min(MAC_I, MAC_R) || max(MAC_I, MAC_R) || BSSID || N_KEY) ++ * TODO: is N_KEY really included in KDF Context and if so, in which ++ * presentation format (little endian 16-bit?) is it used? It gets ++ * added by the KDF anyway.. ++ */ ++ ++ if (os_memcmp(myid(&(padapter->eeprompriv)), psta->hwaddr, ETH_ALEN) < 0) { ++ _rtw_memcpy(data, myid(&(padapter->eeprompriv)), ETH_ALEN); ++ _rtw_memcpy(data + ETH_ALEN, psta->hwaddr, ETH_ALEN); ++ } else { ++ _rtw_memcpy(data, psta->hwaddr, ETH_ALEN); ++ _rtw_memcpy(data + ETH_ALEN, myid(&(padapter->eeprompriv)), ETH_ALEN); ++ } ++ _rtw_memcpy(data + 2 * ETH_ALEN, get_bssid(pmlmepriv), ETH_ALEN); ++ ++ sha256_prf(key_input, SHA256_MAC_LEN, "TDLS PMK", data, sizeof(data), (u8 *) &psta->tpk, sizeof(psta->tpk)); ++ ++ ++} ++ ++/** ++ * wpa_tdls_ftie_mic - Calculate TDLS FTIE MIC ++ * @kck: TPK-KCK ++ * @lnkid: Pointer to the beginning of Link Identifier IE ++ * @rsnie: Pointer to the beginning of RSN IE used for handshake ++ * @timeoutie: Pointer to the beginning of Timeout IE used for handshake ++ * @ftie: Pointer to the beginning of FT IE ++ * @mic: Pointer for writing MIC ++ * ++ * Calculate MIC for TDLS frame. ++ */ ++int wpa_tdls_ftie_mic(u8 *kck, u8 trans_seq, ++ u8 *lnkid, u8 *rsnie, u8 *timeoutie, u8 *ftie, ++ u8 *mic) ++{ ++ u8 *buf, *pos; ++ struct wpa_tdls_ftie *_ftie; ++ struct wpa_tdls_lnkid *_lnkid; ++ int ret; ++ int len = 2 * ETH_ALEN + 1 + 2 + lnkid[1] + 2 + rsnie[1] + ++ 2 + timeoutie[1] + 2 + ftie[1]; ++ buf = rtw_zmalloc(len); ++ if (!buf) { ++ DBG_8192C("TDLS: No memory for MIC calculation\n"); ++ return -1; ++ } ++ ++ pos = buf; ++ _lnkid = (struct wpa_tdls_lnkid *) lnkid; ++ /* 1) TDLS initiator STA MAC address */ ++ _rtw_memcpy(pos, _lnkid->init_sta, ETH_ALEN); ++ pos += ETH_ALEN; ++ /* 2) TDLS responder STA MAC address */ ++ _rtw_memcpy(pos, _lnkid->resp_sta, ETH_ALEN); ++ pos += ETH_ALEN; ++ /* 3) Transaction Sequence number */ ++ *pos++ = trans_seq; ++ /* 4) Link Identifier IE */ ++ _rtw_memcpy(pos, lnkid, 2 + lnkid[1]); ++ pos += 2 + lnkid[1]; ++ /* 5) RSN IE */ ++ _rtw_memcpy(pos, rsnie, 2 + rsnie[1]); ++ pos += 2 + rsnie[1]; ++ /* 6) Timeout Interval IE */ ++ _rtw_memcpy(pos, timeoutie, 2 + timeoutie[1]); ++ pos += 2 + timeoutie[1]; ++ /* 7) FTIE, with the MIC field of the FTIE set to 0 */ ++ _rtw_memcpy(pos, ftie, 2 + ftie[1]); ++ _ftie = (struct wpa_tdls_ftie *) pos; ++ _rtw_memset(_ftie->mic, 0, TDLS_MIC_LEN); ++ pos += 2 + ftie[1]; ++ ++ ret = omac1_aes_128(kck, buf, pos - buf, mic); ++ rtw_mfree(buf, len); ++ return ret; ++ ++} ++ ++int tdls_verify_mic(u8 *kck, u8 trans_seq, ++ u8 *lnkid, u8 *rsnie, u8 *timeoutie, u8 *ftie) ++{ ++ u8 *buf, *pos; ++ int len; ++ u8 mic[16]; ++ int ret; ++ u8 *rx_ftie, *tmp_ftie; ++ ++ if (lnkid == NULL || rsnie == NULL || ++ timeoutie == NULL || ftie == NULL){ ++ DBG_8192C("pointer fail\n"); ++ return 0; ++ } ++ ++ len = 2 * ETH_ALEN + 1 + 2 + 18 + 2 + *(rsnie+1) + 2 + *(timeoutie+1) + 2 + *(ftie+1); ++ ++ buf = rtw_zmalloc(len); ++ if (buf == NULL) ++ return 0; ++ ++ pos = buf; ++ /* 1) TDLS initiator STA MAC address */ ++ _rtw_memcpy(pos, lnkid + ETH_ALEN + 2, ETH_ALEN); ++ pos += ETH_ALEN; ++ /* 2) TDLS responder STA MAC address */ ++ _rtw_memcpy(pos, lnkid + 2 * ETH_ALEN + 2, ETH_ALEN); ++ pos += ETH_ALEN; ++ /* 3) Transaction Sequence number */ ++ *pos++ = trans_seq; ++ /* 4) Link Identifier IE */ ++ _rtw_memcpy(pos, lnkid, 2 + 18); ++ pos += 2 + 18; ++ /* 5) RSN IE */ ++ _rtw_memcpy(pos, rsnie, 2 + *(rsnie+1)); ++ pos += 2 + *(rsnie+1); ++ /* 6) Timeout Interval IE */ ++ _rtw_memcpy(pos, timeoutie, 2 + *(timeoutie+1)); ++ pos += 2 + *(timeoutie+1); ++ /* 7) FTIE, with the MIC field of the FTIE set to 0 */ ++ _rtw_memcpy(pos, ftie, 2 + *(ftie+1)); ++ pos += 2; ++ tmp_ftie = (u8 *) (pos+2); ++ _rtw_memset(tmp_ftie, 0, 16); ++ pos += *(ftie+1); ++ ++ ret = omac1_aes_128(kck, buf, pos - buf, mic); ++ rtw_mfree(buf, len); ++ if (ret) ++ return 0; ++ rx_ftie = ftie+4; ++ ++ if (os_memcmp(mic, rx_ftie, 16) == 0) { ++ //Valid MIC ++ DBG_8192C( "[%s] Valid MIC\n", __FUNCTION__); ++ return 1; ++ } ++ //Invalid MIC ++ DBG_8192C( "[%s] Invalid MIC\n", __FUNCTION__); ++ return 0; ++ ++} ++#endif ++ ++#ifdef PLATFORM_WINDOWS ++void rtw_use_tkipkey_handler ( ++ IN PVOID SystemSpecific1, ++ IN PVOID FunctionContext, ++ IN PVOID SystemSpecific2, ++ IN PVOID SystemSpecific3 ++ ) ++#endif ++#ifdef PLATFORM_LINUX ++void rtw_use_tkipkey_handler(void *FunctionContext) ++#endif ++{ ++ _adapter *padapter = (_adapter *)FunctionContext; ++ ++ ++_func_enter_; ++ ++ RT_TRACE(_module_rtl871x_security_c_,_drv_err_,("^^^rtw_use_tkipkey_handler ^^^\n")); ++ ++/* ++ if(padapter->bDriverStopped ||padapter->bSurpriseRemoved){ ++ RT_TRACE(_module_rtl871x_security_c_,_drv_err_,("^^^rtw_use_tkipkey_handler (padapter->bDriverStopped %d)(padapter->bSurpriseRemoved %d)^^^\n",padapter->bDriverStopped,padapter->bSurpriseRemoved)); ++ ++ return; ++ } ++ */ ++ ++ padapter->securitypriv.busetkipkey=_TRUE; ++ ++ RT_TRACE(_module_rtl871x_security_c_,_drv_err_,("^^^rtw_use_tkipkey_handler padapter->securitypriv.busetkipkey=%d^^^\n",padapter->securitypriv.busetkipkey)); ++ ++_func_exit_; ++ ++} ++ +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/core/rtw_sta_mgt.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/core/rtw_sta_mgt.c 2013-07-26 19:36:05.000000000 +0000 +@@ -0,0 +1,720 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++******************************************************************************/ ++#define _RTW_STA_MGT_C_ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++ ++#if defined (PLATFORM_LINUX) && defined (PLATFORM_WINDOWS) ++ ++#error "Shall be Linux or Windows, but not both!\n" ++ ++#endif ++ ++#include ++ ++ ++void _rtw_init_stainfo(struct sta_info *psta) ++{ ++ ++_func_enter_; ++ ++ _rtw_memset((u8 *)psta, 0, sizeof (struct sta_info)); ++ ++ _rtw_spinlock_init(&psta->lock); ++ _rtw_init_listhead(&psta->list); ++ _rtw_init_listhead(&psta->hash_list); ++ //_rtw_init_listhead(&psta->asoc_list); ++ //_rtw_init_listhead(&psta->sleep_list); ++ //_rtw_init_listhead(&psta->wakeup_list); ++ ++ _rtw_init_queue(&psta->sleep_q); ++ psta->sleepq_len = 0; ++ ++ _rtw_init_sta_xmit_priv(&psta->sta_xmitpriv); ++ _rtw_init_sta_recv_priv(&psta->sta_recvpriv); ++ ++#ifdef CONFIG_AP_MODE ++ ++ _rtw_init_listhead(&psta->asoc_list); ++ ++ _rtw_init_listhead(&psta->auth_list); ++ ++ psta->expire_to = 0; ++ ++ psta->flags = 0; ++ ++ psta->capability = 0; ++ ++ psta->bpairwise_key_installed = _FALSE; ++ ++ ++#ifdef CONFIG_NATIVEAP_MLME ++ psta->nonerp_set = 0; ++ psta->no_short_slot_time_set = 0; ++ psta->no_short_preamble_set = 0; ++ psta->no_ht_gf_set = 0; ++ psta->no_ht_set = 0; ++ psta->ht_20mhz_set = 0; ++#endif ++ ++#ifdef CONFIG_TX_MCAST2UNI ++ psta->under_exist_checking = 0; ++#endif // CONFIG_TX_MCAST2UNI ++ ++#endif // CONFIG_AP_MODE ++ ++_func_exit_; ++ ++} ++ ++u32 _rtw_init_sta_priv(struct sta_priv *pstapriv) ++{ ++ struct sta_info *psta; ++ s32 i; ++ ++_func_enter_; ++ ++ pstapriv->pallocated_stainfo_buf = rtw_zvmalloc (sizeof(struct sta_info) * NUM_STA+ 4); ++ ++ if(!pstapriv->pallocated_stainfo_buf) ++ return _FAIL; ++ ++ pstapriv->pstainfo_buf = pstapriv->pallocated_stainfo_buf + 4 - ++ ((SIZE_PTR)(pstapriv->pallocated_stainfo_buf ) & 3); ++ ++ _rtw_init_queue(&pstapriv->free_sta_queue); ++ ++ _rtw_spinlock_init(&pstapriv->sta_hash_lock); ++ ++ //_rtw_init_queue(&pstapriv->asoc_q); ++ pstapriv->asoc_sta_count = 0; ++ _rtw_init_queue(&pstapriv->sleep_q); ++ _rtw_init_queue(&pstapriv->wakeup_q); ++ ++ psta = (struct sta_info *)(pstapriv->pstainfo_buf); ++ ++ ++ for(i = 0; i < NUM_STA; i++) ++ { ++ _rtw_init_stainfo(psta); ++ ++ _rtw_init_listhead(&(pstapriv->sta_hash[i])); ++ ++ rtw_list_insert_tail(&psta->list, get_list_head(&pstapriv->free_sta_queue)); ++ ++ psta++; ++ } ++ ++#ifdef CONFIG_AP_MODE ++ ++ pstapriv->sta_dz_bitmap = 0; ++ pstapriv->tim_bitmap = 0; ++ ++ _rtw_init_listhead(&pstapriv->asoc_list); ++ _rtw_init_listhead(&pstapriv->auth_list); ++ ++ _rtw_spinlock_init(&pstapriv->asoc_list_lock); ++ _rtw_spinlock_init(&pstapriv->auth_list_lock); ++ ++ pstapriv->auth_to = 3; // 3*2 = 6 sec ++ pstapriv->assoc_to = 3; ++ //pstapriv->expire_to = 900;// 900*2 = 1800 sec = 30 min, expire after no any traffic. ++ //pstapriv->expire_to = 30;// 30*2 = 60 sec = 1 min, expire after no any traffic. ++ pstapriv->expire_to = 60;// 60*2 = 120 sec = 2 min, expire after no any traffic. ++ ++ pstapriv->max_num_sta = NUM_STA; ++ ++#endif ++ ++_func_exit_; ++ ++ return _SUCCESS; ++ ++} ++ ++void _rtw_free_sta_xmit_priv_lock(struct sta_xmit_priv *psta_xmitpriv) ++{ ++_func_enter_; ++ ++ _rtw_spinlock_free(&psta_xmitpriv->lock); ++ ++ _rtw_spinlock_free(&(psta_xmitpriv->be_q.sta_pending.lock)); ++ _rtw_spinlock_free(&(psta_xmitpriv->bk_q.sta_pending.lock)); ++ _rtw_spinlock_free(&(psta_xmitpriv->vi_q.sta_pending.lock)); ++ _rtw_spinlock_free(&(psta_xmitpriv->vo_q.sta_pending.lock)); ++_func_exit_; ++} ++ ++static void _rtw_free_sta_recv_priv_lock(struct sta_recv_priv *psta_recvpriv) ++{ ++_func_enter_; ++ ++ _rtw_spinlock_free(&psta_recvpriv->lock); ++ ++ _rtw_spinlock_free(&(psta_recvpriv->defrag_q.lock)); ++ ++_func_exit_; ++ ++} ++ ++void rtw_mfree_stainfo(struct sta_info *psta) ++{ ++_func_enter_; ++ ++ if(&psta->lock != NULL) ++ _rtw_spinlock_free(&psta->lock); ++ ++ _rtw_free_sta_xmit_priv_lock(&psta->sta_xmitpriv); ++ _rtw_free_sta_recv_priv_lock(&psta->sta_recvpriv); ++ ++_func_exit_; ++} ++ ++ ++// this function is used to free the memory of lock || sema for all stainfos ++void rtw_mfree_all_stainfo(struct sta_priv *pstapriv ) ++{ ++ _irqL irqL; ++ _list *plist, *phead; ++ struct sta_info *psta = NULL; ++ ++_func_enter_; ++ ++ _enter_critical_bh(&pstapriv->sta_hash_lock, &irqL); ++ ++ phead = get_list_head(&pstapriv->free_sta_queue); ++ plist = get_next(phead); ++ ++ while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) ++ { ++ psta = LIST_CONTAINOR(plist, struct sta_info ,list); ++ plist = get_next(plist); ++ ++ rtw_mfree_stainfo(psta); ++ } ++ ++ _exit_critical_bh(&pstapriv->sta_hash_lock, &irqL); ++ ++_func_exit_; ++ ++} ++ ++ ++void rtw_mfree_sta_priv_lock(struct sta_priv *pstapriv) ++{ ++ rtw_mfree_all_stainfo(pstapriv); //be done before free sta_hash_lock ++ ++ _rtw_spinlock_free(&pstapriv->free_sta_queue.lock); ++ ++ _rtw_spinlock_free(&pstapriv->sta_hash_lock); ++ _rtw_spinlock_free(&pstapriv->wakeup_q.lock); ++ _rtw_spinlock_free(&pstapriv->sleep_q.lock); ++ ++#ifdef CONFIG_AP_MODE ++ _rtw_spinlock_free(&pstapriv->asoc_list_lock); ++ _rtw_spinlock_free(&pstapriv->auth_list_lock); ++#endif ++ ++} ++ ++u32 _rtw_free_sta_priv(struct sta_priv *pstapriv) ++{ ++_func_enter_; ++ if(pstapriv){ ++ rtw_mfree_sta_priv_lock(pstapriv); ++ ++ if(pstapriv->pallocated_stainfo_buf) { ++ rtw_vmfree(pstapriv->pallocated_stainfo_buf, sizeof(struct sta_info)*NUM_STA+4); ++ } ++ } ++ ++_func_exit_; ++ return _SUCCESS; ++} ++ ++ ++//struct sta_info *rtw_alloc_stainfo(_queue *pfree_sta_queue, unsigned char *hwaddr) ++struct sta_info *rtw_alloc_stainfo(struct sta_priv *pstapriv, u8 *hwaddr) ++{ ++ _irqL irqL, irqL2; ++ uint tmp_aid; ++ s32 index; ++ _list *phash_list; ++ struct sta_info *psta; ++ _queue *pfree_sta_queue; ++ struct recv_reorder_ctrl *preorder_ctrl; ++ int i = 0; ++ u16 wRxSeqInitialValue = 0xffff; ++ ++_func_enter_; ++ ++ pfree_sta_queue = &pstapriv->free_sta_queue; ++ ++ _enter_critical_bh(&(pfree_sta_queue->lock), &irqL); ++ ++ if (_rtw_queue_empty(pfree_sta_queue) == _TRUE) ++ { ++ _exit_critical_bh(&(pfree_sta_queue->lock), &irqL); ++ psta = NULL; ++ } ++ else ++ { ++ psta = LIST_CONTAINOR(get_next(&pfree_sta_queue->queue), struct sta_info, list); ++ ++ rtw_list_delete(&(psta->list)); ++ ++ _exit_critical_bh(&(pfree_sta_queue->lock), &irqL); ++ ++ tmp_aid = psta->aid; ++ ++ _rtw_init_stainfo(psta); ++ ++ _rtw_memcpy(psta->hwaddr, hwaddr, ETH_ALEN); ++ ++ index = wifi_mac_hash(hwaddr); ++ ++ RT_TRACE(_module_rtl871x_sta_mgt_c_,_drv_info_,("rtw_alloc_stainfo: index = %x", index)); ++ ++ if(index >= NUM_STA){ ++ RT_TRACE(_module_rtl871x_sta_mgt_c_,_drv_err_,("ERROR=> rtw_alloc_stainfo: index >= NUM_STA")); ++ psta= NULL; ++ goto exit; ++ } ++ phash_list = &(pstapriv->sta_hash[index]); ++ ++ _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL2); ++ ++ rtw_list_insert_tail(&psta->hash_list, phash_list); ++ ++ pstapriv->asoc_sta_count ++ ; ++ ++ _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL2); ++ ++// Commented by Albert 2009/08/13 ++// For the SMC router, the sequence number of first packet of WPS handshake will be 0. ++// In this case, this packet will be dropped by recv_decache function if we use the 0x00 as the default value for tid_rxseq variable. ++// So, we initialize the tid_rxseq variable as the 0xffff. ++ ++ for( i = 0; i < 16; i++ ) ++ { ++ _rtw_memcpy( &psta->sta_recvpriv.rxcache.tid_rxseq[ i ], &wRxSeqInitialValue, 2 ); ++ } ++ ++ RT_TRACE(_module_rtl871x_sta_mgt_c_,_drv_info_,("alloc number_%d stainfo with hwaddr = %x %x %x %x %x %x \n", ++ pstapriv->asoc_sta_count , hwaddr[0], hwaddr[1], hwaddr[2],hwaddr[3],hwaddr[4],hwaddr[5])); ++ ++ init_addba_retry_timer(pstapriv->padapter, psta); ++ ++#ifdef CONFIG_TDLS ++ psta->padapter = pstapriv->padapter; ++ init_TPK_timer(pstapriv->padapter, psta); ++ init_ch_switch_timer(pstapriv->padapter, psta); ++ init_base_ch_timer(pstapriv->padapter, psta); ++ init_off_ch_timer(pstapriv->padapter, psta); ++ init_handshake_timer(pstapriv->padapter, psta); ++ init_tdls_alive_timer(pstapriv->padapter, psta); ++#endif ++ ++ //for A-MPDU Rx reordering buffer control ++ for(i=0; i < 16 ; i++) ++ { ++ preorder_ctrl = &psta->recvreorder_ctrl[i]; ++ ++ preorder_ctrl->padapter = pstapriv->padapter; ++ ++ preorder_ctrl->enable = _FALSE; ++ ++ preorder_ctrl->indicate_seq = 0xffff; ++ #ifdef DBG_RX_SEQ ++ DBG_871X("DBG_RX_SEQ %s:%d IndicateSeq: %d\n", __FUNCTION__, __LINE__, ++ preorder_ctrl->indicate_seq); ++ #endif ++ preorder_ctrl->wend_b= 0xffff; ++ //preorder_ctrl->wsize_b = (NR_RECVBUFF-2); ++ preorder_ctrl->wsize_b = 64;//64; ++ ++ _rtw_init_queue(&preorder_ctrl->pending_recvframe_queue); ++ ++ rtw_init_recv_timer(preorder_ctrl); ++ } ++ ++ ++ //init for DM ++ psta->rssi_stat.UndecoratedSmoothedPWDB = (-1); ++ psta->rssi_stat.UndecoratedSmoothedCCK = (-1); ++ ++ } ++ ++exit: ++ ++_func_exit_; ++ ++ return psta; ++ ++ ++} ++ ++ ++// using pstapriv->sta_hash_lock to protect ++u32 rtw_free_stainfo(_adapter *padapter , struct sta_info *psta) ++{ ++ int i; ++ _irqL irqL0; ++ _queue *pfree_sta_queue; ++ struct recv_reorder_ctrl *preorder_ctrl; ++ struct sta_xmit_priv *pstaxmitpriv; ++ struct xmit_priv *pxmitpriv= &padapter->xmitpriv; ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ ++ ++_func_enter_; ++ ++ if (psta == NULL) ++ goto exit; ++ ++ pfree_sta_queue = &pstapriv->free_sta_queue; ++ ++ ++ pstaxmitpriv = &psta->sta_xmitpriv; ++ ++ //rtw_list_delete(&psta->sleep_list); ++ ++ //rtw_list_delete(&psta->wakeup_list); ++ ++ _enter_critical_bh(&pxmitpriv->lock, &irqL0); ++ ++ rtw_free_xmitframe_queue(pxmitpriv, &psta->sleep_q); ++ psta->sleepq_len = 0; ++ ++ //_enter_critical_bh(&(pxmitpriv->vo_pending.lock), &irqL0); ++ ++ rtw_free_xmitframe_queue( pxmitpriv, &pstaxmitpriv->vo_q.sta_pending); ++ ++ rtw_list_delete(&(pstaxmitpriv->vo_q.tx_pending)); ++ ++ //_exit_critical_bh(&(pxmitpriv->vo_pending.lock), &irqL0); ++ ++ ++ //_enter_critical_bh(&(pxmitpriv->vi_pending.lock), &irqL0); ++ ++ rtw_free_xmitframe_queue( pxmitpriv, &pstaxmitpriv->vi_q.sta_pending); ++ ++ rtw_list_delete(&(pstaxmitpriv->vi_q.tx_pending)); ++ ++ //_exit_critical_bh(&(pxmitpriv->vi_pending.lock), &irqL0); ++ ++ ++ //_enter_critical_bh(&(pxmitpriv->bk_pending.lock), &irqL0); ++ ++ rtw_free_xmitframe_queue( pxmitpriv, &pstaxmitpriv->bk_q.sta_pending); ++ ++ rtw_list_delete(&(pstaxmitpriv->bk_q.tx_pending)); ++ ++ //_exit_critical_bh(&(pxmitpriv->bk_pending.lock), &irqL0); ++ ++ //_enter_critical_bh(&(pxmitpriv->be_pending.lock), &irqL0); ++ ++ rtw_free_xmitframe_queue( pxmitpriv, &pstaxmitpriv->be_q.sta_pending); ++ ++ rtw_list_delete(&(pstaxmitpriv->be_q.tx_pending)); ++ ++ //_exit_critical_bh(&(pxmitpriv->be_pending.lock), &irqL0); ++ ++ _exit_critical_bh(&pxmitpriv->lock, &irqL0); ++ ++ rtw_list_delete(&psta->hash_list); ++ RT_TRACE(_module_rtl871x_sta_mgt_c_,_drv_err_,("\n free number_%d stainfo with hwaddr = 0x%.2x 0x%.2x 0x%.2x 0x%.2x 0x%.2x 0x%.2x \n",pstapriv->asoc_sta_count , psta->hwaddr[0], psta->hwaddr[1], psta->hwaddr[2],psta->hwaddr[3],psta->hwaddr[4],psta->hwaddr[5])); ++ pstapriv->asoc_sta_count --; ++ ++ ++ // re-init sta_info; 20061114 ++ _rtw_init_sta_xmit_priv(&psta->sta_xmitpriv); ++ _rtw_init_sta_recv_priv(&psta->sta_recvpriv); ++ ++ _cancel_timer_ex(&psta->addba_retry_timer); ++ ++#ifdef CONFIG_TDLS ++ _cancel_timer_ex(&psta->TPK_timer); ++ _cancel_timer_ex(&psta->option_timer); ++ _cancel_timer_ex(&psta->base_ch_timer); ++ _cancel_timer_ex(&psta->off_ch_timer); ++ _cancel_timer_ex(&psta->alive_timer1); ++ _cancel_timer_ex(&psta->alive_timer2); ++#endif ++ ++ //for A-MPDU Rx reordering buffer control, cancel reordering_ctrl_timer ++ for(i=0; i < 16 ; i++) ++ { ++ _irqL irqL; ++ _list *phead, *plist; ++ union recv_frame *prframe; ++ _queue *ppending_recvframe_queue; ++ _queue *pfree_recv_queue = &padapter->recvpriv.free_recv_queue; ++ ++ preorder_ctrl = &psta->recvreorder_ctrl[i]; ++ ++ _cancel_timer_ex(&preorder_ctrl->reordering_ctrl_timer); ++ ++ ++ ppending_recvframe_queue = &preorder_ctrl->pending_recvframe_queue; ++ ++ _enter_critical_bh(&ppending_recvframe_queue->lock, &irqL); ++ ++ phead = get_list_head(ppending_recvframe_queue); ++ plist = get_next(phead); ++ ++ while(!rtw_is_list_empty(phead)) ++ { ++ prframe = LIST_CONTAINOR(plist, union recv_frame, u); ++ ++ plist = get_next(plist); ++ ++ rtw_list_delete(&(prframe->u.hdr.list)); ++ ++ rtw_free_recvframe(prframe, pfree_recv_queue); ++ } ++ ++ _exit_critical_bh(&ppending_recvframe_queue->lock, &irqL); ++ ++ } ++ ++ ++#ifdef CONFIG_AP_MODE ++ ++/* ++ _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL0); ++ rtw_list_delete(&psta->asoc_list); ++ _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL0); ++*/ ++ ++ _enter_critical_bh(&pstapriv->auth_list_lock, &irqL0); ++ rtw_list_delete(&psta->auth_list); ++ _exit_critical_bh(&pstapriv->auth_list_lock, &irqL0); ++ ++ psta->expire_to = 0; ++ ++ psta->sleepq_ac_len = 0; ++ psta->qos_info = 0; ++ ++ psta->max_sp_len = 0; ++ psta->uapsd_bk = 0; ++ psta->uapsd_be = 0; ++ psta->uapsd_vi = 0; ++ psta->uapsd_vo = 0; ++ ++ psta->has_legacy_ac = 0; ++ ++#ifdef CONFIG_NATIVEAP_MLME ++ ++ pstapriv->sta_dz_bitmap &=~BIT(psta->aid); ++ pstapriv->tim_bitmap &=~BIT(psta->aid); ++ ++ //rtw_indicate_sta_disassoc_event(padapter, psta); ++ ++ if (pstapriv->sta_aid[psta->aid - 1] == psta) ++ { ++ pstapriv->sta_aid[psta->aid - 1] = NULL; ++ psta->aid = 0; ++ } ++ ++#endif // CONFIG_NATIVEAP_MLME ++ ++#ifdef CONFIG_TX_MCAST2UNI ++ psta->under_exist_checking = 0; ++#endif // CONFIG_TX_MCAST2UNI ++ ++#endif // CONFIG_AP_MODE ++ ++ _enter_critical_bh(&(pfree_sta_queue->lock), &irqL0); ++ rtw_list_insert_tail(&psta->list, get_list_head(pfree_sta_queue)); ++ _exit_critical_bh(&(pfree_sta_queue->lock), &irqL0); ++ ++exit: ++ ++_func_exit_; ++ ++ return _SUCCESS; ++ ++} ++ ++// free all stainfo which in sta_hash[all] ++void rtw_free_all_stainfo(_adapter *padapter) ++{ ++ _irqL irqL; ++ _list *plist, *phead; ++ s32 index; ++ struct sta_info *psta = NULL; ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ struct sta_info* pbcmc_stainfo =rtw_get_bcmc_stainfo( padapter); ++ ++_func_enter_; ++ ++ if(pstapriv->asoc_sta_count==1) ++ goto exit; ++ ++ _enter_critical_bh(&pstapriv->sta_hash_lock, &irqL); ++ ++ for(index=0; index< NUM_STA; index++) ++ { ++ phead = &(pstapriv->sta_hash[index]); ++ plist = get_next(phead); ++ ++ while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) ++ { ++ psta = LIST_CONTAINOR(plist, struct sta_info ,hash_list); ++ ++ plist = get_next(plist); ++ ++ if(pbcmc_stainfo!=psta) ++ rtw_free_stainfo(padapter , psta); ++ ++ } ++ } ++ ++ _exit_critical_bh(&pstapriv->sta_hash_lock, &irqL); ++ ++exit: ++ ++_func_exit_; ++ ++} ++ ++/* any station allocated can be searched by hash list */ ++struct sta_info *rtw_get_stainfo(struct sta_priv *pstapriv, u8 *hwaddr) ++{ ++ ++ _irqL irqL; ++ ++ _list *plist, *phead; ++ ++ struct sta_info *psta = NULL; ++ ++ u32 index; ++ ++ u8 *addr; ++ ++ u8 bc_addr[ETH_ALEN] = {0xff,0xff,0xff,0xff,0xff,0xff}; ++ ++_func_enter_; ++ ++ if(hwaddr==NULL) ++ return NULL; ++ ++ if(IS_MCAST(hwaddr)) ++ { ++ addr = bc_addr; ++ } ++ else ++ { ++ addr = hwaddr; ++ } ++ ++ index = wifi_mac_hash(addr); ++ ++ _enter_critical_bh(&pstapriv->sta_hash_lock, &irqL); ++ ++ phead = &(pstapriv->sta_hash[index]); ++ plist = get_next(phead); ++ ++ ++ while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) ++ { ++ ++ psta = LIST_CONTAINOR(plist, struct sta_info, hash_list); ++ ++ if ((_rtw_memcmp(psta->hwaddr, addr, ETH_ALEN))== _TRUE) ++ { // if found the matched address ++ break; ++ } ++ psta=NULL; ++ plist = get_next(plist); ++ } ++ ++ _exit_critical_bh(&pstapriv->sta_hash_lock, &irqL); ++_func_exit_; ++ return psta; ++ ++} ++ ++u32 rtw_init_bcmc_stainfo(_adapter* padapter) ++{ ++ ++ struct sta_info *psta; ++ struct tx_servq *ptxservq; ++ u32 res=_SUCCESS; ++ NDIS_802_11_MAC_ADDRESS bcast_addr= {0xff,0xff,0xff,0xff,0xff,0xff}; ++ ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ //_queue *pstapending = &padapter->xmitpriv.bm_pending; ++ ++_func_enter_; ++ ++ psta = rtw_alloc_stainfo(pstapriv, bcast_addr); ++ ++ if(psta==NULL){ ++ res=_FAIL; ++ RT_TRACE(_module_rtl871x_sta_mgt_c_,_drv_err_,("rtw_alloc_stainfo fail")); ++ goto exit; ++ } ++ ++ // default broadcast & multicast use macid 1 ++ psta->mac_id = 1; ++ ++ ptxservq= &(psta->sta_xmitpriv.be_q); ++ ++/* ++ _enter_critical(&pstapending->lock, &irqL0); ++ ++ if (rtw_is_list_empty(&ptxservq->tx_pending)) ++ rtw_list_insert_tail(&ptxservq->tx_pending, get_list_head(pstapending)); ++ ++ _exit_critical(&pstapending->lock, &irqL0); ++*/ ++ ++exit: ++_func_exit_; ++ return _SUCCESS; ++ ++} ++ ++ ++struct sta_info* rtw_get_bcmc_stainfo(_adapter* padapter) ++{ ++ struct sta_info *psta; ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ u8 bc_addr[ETH_ALEN] = {0xff,0xff,0xff,0xff,0xff,0xff}; ++_func_enter_; ++ psta = rtw_get_stainfo(pstapriv, bc_addr); ++_func_exit_; ++ return psta; ++ ++} ++ ++u8 rtw_access_ctrl(struct wlan_acl_pool* pacl_list, u8 * mac_addr) ++{ ++ return _TRUE; ++} ++ +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/core/rtw_wlan_util.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/core/rtw_wlan_util.c 2013-07-26 19:36:05.000000000 +0000 +@@ -0,0 +1,1848 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ++******************************************************************************/ ++#define _RTW_WLAN_UTIL_C_ ++ ++#include ++#include ++#include ++#include ++ ++ ++unsigned char ARTHEROS_OUI1[] = {0x00, 0x03, 0x7f}; ++unsigned char ARTHEROS_OUI2[] = {0x00, 0x13, 0x74}; ++ ++unsigned char BROADCOM_OUI1[] = {0x00, 0x10, 0x18}; ++unsigned char BROADCOM_OUI2[] = {0x00, 0x0a, 0xf7}; ++unsigned char BROADCOM_OUI3[] = {0x00, 0x05, 0xb5}; ++ ++unsigned char CISCO_OUI[] = {0x00, 0x40, 0x96}; ++unsigned char MARVELL_OUI[] = {0x00, 0x50, 0x43}; ++unsigned char RALINK_OUI[] = {0x00, 0x0c, 0x43}; ++unsigned char REALTEK_OUI[] = {0x00, 0xe0, 0x4c}; ++unsigned char AIRGOCAP_OUI[] = {0x00, 0x0a, 0xf5}; ++ ++unsigned char REALTEK_96B_IE[] = {0x00, 0xe0, 0x4c, 0x02, 0x01, 0x20}; ++ ++extern unsigned char MCS_rate_2R[16]; ++extern unsigned char MCS_rate_1R[16]; ++extern unsigned char WPA_OUI[]; ++extern unsigned char WPA_TKIP_CIPHER[4]; ++extern unsigned char RSN_TKIP_CIPHER[4]; ++ ++#define R2T_PHY_DELAY (0) ++ ++//#define WAIT_FOR_BCN_TO_MIN (3000) ++#define WAIT_FOR_BCN_TO_MIN (6000) ++#define WAIT_FOR_BCN_TO_MAX (20000) ++ ++ ++int cckrates_included(unsigned char *rate, int ratelen) ++{ ++ int i; ++ ++ for(i = 0; i < ratelen; i++) ++ { ++ if ( (((rate[i]) & 0x7f) == 2) || (((rate[i]) & 0x7f) == 4) || ++ (((rate[i]) & 0x7f) == 11) || (((rate[i]) & 0x7f) == 22) ) ++ return _TRUE; ++ } ++ ++ return _FALSE; ++ ++} ++ ++int cckratesonly_included(unsigned char *rate, int ratelen) ++{ ++ int i; ++ ++ for(i = 0; i < ratelen; i++) ++ { ++ if ( (((rate[i]) & 0x7f) != 2) && (((rate[i]) & 0x7f) != 4) && ++ (((rate[i]) & 0x7f) != 11) && (((rate[i]) & 0x7f) != 22) ) ++ return _FALSE; ++ } ++ ++ return _TRUE; ++} ++ ++unsigned char networktype_to_raid(unsigned char network_type) ++{ ++ unsigned char raid; ++ ++ switch(network_type) ++ { ++ case WIRELESS_11B: ++ raid = 6; ++ break; ++ case WIRELESS_11A: ++ case WIRELESS_11G: ++ raid = 5; ++ break; ++ case WIRELESS_11BG: ++ raid = 4; ++ break; ++ case WIRELESS_11_24N: ++ case WIRELESS_11_5N: ++ raid = 3; ++ break; ++ case WIRELESS_11A_5N: ++ case WIRELESS_11G_24N: ++ raid = 1; ++ break; ++ case WIRELESS_11BG_24N: ++ raid = 0; ++ break; ++ default: ++ raid = 4; ++ break; ++ ++ } ++ ++ return raid; ++ ++} ++ ++int judge_network_type(_adapter *padapter, unsigned char *rate, int ratelen) ++{ ++ int network_type = 0; ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ ++ ++ if(pmlmeext->cur_channel > 14) ++ { ++ if (pmlmeinfo->HT_enable) ++ { ++ network_type = WIRELESS_11_5N; ++ } ++ ++ network_type |= WIRELESS_11A; ++ } ++ else ++ { ++ if (pmlmeinfo->HT_enable) ++ { ++ network_type = WIRELESS_11_24N; ++ } ++ ++ if ((cckratesonly_included(rate, ratelen)) == _TRUE) ++ { ++ network_type |= WIRELESS_11B; ++ } ++ else if((cckrates_included(rate, ratelen)) == _TRUE) ++ { ++ network_type |= WIRELESS_11BG; ++ } ++ else ++ { ++ network_type |= WIRELESS_11G; ++ } ++ } ++ ++ return network_type; ++} ++ ++unsigned char ratetbl_val_2wifirate(unsigned char rate) ++{ ++ unsigned char val = 0; ++ ++ switch (rate & 0x7f) ++ { ++ case 0: ++ val = IEEE80211_CCK_RATE_1MB; ++ break; ++ ++ case 1: ++ val = IEEE80211_CCK_RATE_2MB; ++ break; ++ ++ case 2: ++ val = IEEE80211_CCK_RATE_5MB; ++ break; ++ ++ case 3: ++ val = IEEE80211_CCK_RATE_11MB; ++ break; ++ ++ case 4: ++ val = IEEE80211_OFDM_RATE_6MB; ++ break; ++ ++ case 5: ++ val = IEEE80211_OFDM_RATE_9MB; ++ break; ++ ++ case 6: ++ val = IEEE80211_OFDM_RATE_12MB; ++ break; ++ ++ case 7: ++ val = IEEE80211_OFDM_RATE_18MB; ++ break; ++ ++ case 8: ++ val = IEEE80211_OFDM_RATE_24MB; ++ break; ++ ++ case 9: ++ val = IEEE80211_OFDM_RATE_36MB; ++ break; ++ ++ case 10: ++ val = IEEE80211_OFDM_RATE_48MB; ++ break; ++ ++ case 11: ++ val = IEEE80211_OFDM_RATE_54MB; ++ break; ++ ++ } ++ ++ return val; ++ ++} ++ ++int is_basicrate(_adapter *padapter, unsigned char rate) ++{ ++ int i; ++ unsigned char val; ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ ++ for(i = 0; i < NumRates; i++) ++ { ++ val = pmlmeext->basicrate[i]; ++ ++ if ((val != 0xff) && (val != 0xfe)) ++ { ++ if (rate == ratetbl_val_2wifirate(val)) ++ { ++ return _TRUE; ++ } ++ } ++ } ++ ++ return _FALSE; ++} ++ ++ ++unsigned int ratetbl2rateset(_adapter *padapter, unsigned char *rateset) ++{ ++ int i; ++ unsigned char rate; ++ unsigned int len = 0; ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ ++ for (i = 0; i < NumRates; i++) ++ { ++ rate = pmlmeext->datarate[i]; ++ ++ switch (rate) ++ { ++ case 0xff: ++ return len; ++ ++ case 0xfe: ++ continue; ++ ++ default: ++ rate = ratetbl_val_2wifirate(rate); ++ ++ if (is_basicrate(padapter, rate) == _TRUE) ++ { ++ rate |= IEEE80211_BASIC_RATE_MASK; ++ } ++ ++ rateset[len] = rate; ++ len++; ++ break; ++ } ++ } ++ return len; ++} ++ ++ ++void get_rate_set(_adapter *padapter, unsigned char *pbssrate, int *bssrate_len) ++{ ++ unsigned char supportedrates[NumRates]; ++ ++ _rtw_memset(supportedrates, 0, NumRates); ++ *bssrate_len = ratetbl2rateset(padapter, supportedrates); ++ _rtw_memcpy(pbssrate, supportedrates, *bssrate_len); ++} ++ ++void Save_DM_Func_Flag(_adapter *padapter) ++{ ++ u8 bSaveFlag = _TRUE; ++ ++ padapter->HalFunc.SetHwRegHandler(padapter, HW_VAR_DM_FUNC_OP, (u8 *)(&bSaveFlag)); ++} ++ ++void Restore_DM_Func_Flag(_adapter *padapter) ++{ ++ u8 bSaveFlag = _FALSE; ++ ++ padapter->HalFunc.SetHwRegHandler(padapter, HW_VAR_DM_FUNC_OP, (u8 *)(&bSaveFlag)); ++} ++ ++void Switch_DM_Func(_adapter *padapter, u8 mode, u8 enable) ++{ ++ if(enable == _TRUE) ++ { ++ padapter->HalFunc.SetHwRegHandler(padapter, HW_VAR_DM_FUNC_SET, (u8 *)(&mode)); ++ } ++ else ++ { ++ padapter->HalFunc.SetHwRegHandler(padapter, HW_VAR_DM_FUNC_CLR, (u8 *)(&mode)); ++ } ++ ++#if 0 ++ u8 val8; ++ ++ val8 = rtw_read8(padapter, FW_DYNAMIC_FUN_SWITCH); ++ ++ if(enable == _TRUE) ++ { ++ rtw_write8(padapter, FW_DYNAMIC_FUN_SWITCH, (val8 | mode)); ++ } ++ else ++ { ++ rtw_write8(padapter, FW_DYNAMIC_FUN_SWITCH, (val8 & mode)); ++ } ++#endif ++ ++} ++ ++void Set_NETYPE1_MSR(_adapter *padapter, u8 type) ++{ ++ padapter->HalFunc.SetHwRegHandler(padapter, HW_VAR_MEDIA_STATUS1, (u8 *)(&type)); ++} ++ ++void Set_NETYPE0_MSR(_adapter *padapter, u8 type) ++{ ++ padapter->HalFunc.SetHwRegHandler(padapter, HW_VAR_MEDIA_STATUS, (u8 *)(&type)); ++} ++ ++void SelectChannel(_adapter *padapter, unsigned char channel) ++{ ++ unsigned int scanMode; ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ ++ scanMode = (pmlmeext->sitesurvey_res.scan_mode == SCAN_ACTIVE)? 1: 0;//todo: ++ ++ if(padapter->HalFunc.set_channel_handler) ++ padapter->HalFunc.set_channel_handler(padapter, channel); ++ ++} ++ ++void SetBWMode(_adapter *padapter, unsigned short bwmode, unsigned char channel_offset) ++{ ++ if(padapter->HalFunc.set_bwmode_handler) ++ padapter->HalFunc.set_bwmode_handler(padapter, (HT_CHANNEL_WIDTH)bwmode, channel_offset); ++} ++ ++void set_channel_bwmode(_adapter *padapter, unsigned char channel, unsigned char channel_offset, unsigned short bwmode) ++{ ++ if((bwmode == HT_CHANNEL_WIDTH_20)||(channel_offset == HAL_PRIME_CHNL_OFFSET_DONT_CARE)) ++ { ++ SelectChannel(padapter, channel); ++ } ++ else ++ { ++ //switch to the proper channel ++ if (channel_offset == HAL_PRIME_CHNL_OFFSET_LOWER) ++ { ++ SelectChannel(padapter, channel + 2); ++ } ++ else ++ { ++ SelectChannel(padapter, channel - 2); ++ } ++ } ++ ++ ++ SetBWMode(padapter, bwmode, channel_offset); ++ ++} ++ ++int get_bsstype(unsigned short capability) ++{ ++ if (capability & BIT(0)) ++ { ++ return WIFI_FW_AP_STATE; ++ } ++ else if (capability & BIT(1)) ++ { ++ return WIFI_FW_ADHOC_STATE; ++ } ++ else ++ { ++ return 0; ++ } ++} ++ ++__inline u8 *get_my_bssid(WLAN_BSSID_EX *pnetwork) ++{ ++ return (pnetwork->MacAddress); ++} ++ ++u16 get_beacon_interval(WLAN_BSSID_EX *bss) ++{ ++ unsigned short val; ++ _rtw_memcpy((unsigned char *)&val, rtw_get_beacon_interval_from_ie(bss->IEs), 2); ++ ++ return le16_to_cpu(val); ++ ++} ++ ++int is_client_associated_to_ap(_adapter *padapter) ++{ ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ ++ if ((pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS) && ((pmlmeinfo->state&0x03) == WIFI_FW_STATION_STATE)) ++ { ++ return _TRUE; ++ } ++ else ++ { ++ return _FAIL; ++ } ++} ++ ++int is_client_associated_to_ibss(_adapter *padapter) ++{ ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ ++ if ((pmlmeinfo->state & WIFI_FW_ASSOC_SUCCESS) && ((pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE)) ++ { ++ return _TRUE; ++ } ++ else ++ { ++ return _FAIL; ++ } ++} ++ ++int is_IBSS_empty(_adapter *padapter) ++{ ++ unsigned int i; ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ ++ for (i = IBSS_START_MAC_ID; i < NUM_STA; i++) ++ { ++ if (pmlmeinfo->FW_sta_info[i].status == 1) ++ { ++ return _FAIL; ++ } ++ } ++ ++ return _TRUE; ++ ++} ++ ++unsigned int decide_wait_for_beacon_timeout(unsigned int bcn_interval) ++{ ++ if ((bcn_interval << 2) < WAIT_FOR_BCN_TO_MIN) ++ { ++ return WAIT_FOR_BCN_TO_MIN; ++ } ++ else if ((bcn_interval << 2) > WAIT_FOR_BCN_TO_MAX) ++ { ++ return WAIT_FOR_BCN_TO_MAX; ++ } ++ else ++ { ++ return ((bcn_interval << 2)); ++ } ++} ++ ++void CAM_empty_entry( ++ PADAPTER Adapter, ++ u8 ucIndex ++) ++{ ++ Adapter->HalFunc.SetHwRegHandler(Adapter, HW_VAR_CAM_EMPTY_ENTRY, (u8 *)(&ucIndex)); ++} ++ ++void invalidate_cam_all(_adapter *padapter) ++{ ++ padapter->HalFunc.SetHwRegHandler(padapter, HW_VAR_CAM_INVALID_ALL, 0); ++} ++ ++void write_cam(_adapter *padapter, u8 entry, u16 ctrl, u8 *mac, u8 *key) ++{ ++ unsigned int i, val, addr, cmd; ++ int j; ++ u32 cam_val[2]; ++ ++ addr = entry << 3; ++ ++ for (j = 5; j >= 0; j--) ++ { ++ switch (j) ++ { ++ case 0: ++ val = (ctrl | (mac[0] << 16) | (mac[1] << 24) ); ++ break; ++ ++ case 1: ++ val = (mac[2] | ( mac[3] << 8) | (mac[4] << 16) | (mac[5] << 24)); ++ break; ++ ++ default: ++ i = (j - 2) << 2; ++ val = (key[i] | (key[i+1] << 8) | (key[i+2] << 16) | (key[i+3] << 24)); ++ break; ++ ++ } ++ ++ cam_val[0] = val; ++ cam_val[1] = addr + (unsigned int)j; ++ ++ padapter->HalFunc.SetHwRegHandler(padapter, HW_VAR_CAM_WRITE, (u8 *)cam_val); ++ ++ //rtw_write32(padapter, WCAMI, val); ++ ++ //cmd = CAM_POLLINIG | CAM_WRITE | (addr + j); ++ //rtw_write32(padapter, RWCAM, cmd); ++ ++ //DBG_8192C("%s=> cam write: %x, %x\n",__FUNCTION__, cmd, val); ++ ++ } ++ ++} ++ ++void clear_cam_entry(_adapter *padapter, u8 entry) ++{ ++#if 0 ++ u32 addr, val=0; ++ u32 cam_val[2]; ++ ++ addr = entry << 3; ++ ++ ++ cam_val[0] = val; ++ cam_val[1] = addr + (unsigned int)0; ++ ++ padapter->HalFunc.SetHwRegHandler(padapter, HW_VAR_CAM_WRITE, (u8 *)cam_val); ++ ++ ++ ++ cam_val[0] = val; ++ cam_val[1] = addr + (unsigned int)1; ++ ++ padapter->HalFunc.SetHwRegHandler(padapter, HW_VAR_CAM_WRITE, (u8 *)cam_val); ++#else ++ ++ unsigned char null_sta[] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00}; ++ ++ unsigned char null_key[] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,0x00, 0x00, 0x00, 0x00,0x00, 0x00, 0x00, 0x00}; ++ ++ write_cam(padapter, entry, 0, null_sta, null_key); ++ ++#endif ++} ++ ++int allocate_fw_sta_entry(_adapter *padapter) ++{ ++ unsigned int mac_id; ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ ++ for (mac_id = IBSS_START_MAC_ID; mac_id < NUM_STA; mac_id++) ++ { ++ if (pmlmeinfo->FW_sta_info[mac_id].status == 0) ++ { ++ pmlmeinfo->FW_sta_info[mac_id].status = 1; ++ pmlmeinfo->FW_sta_info[mac_id].retry = 0; ++ break; ++ } ++ } ++ ++ return mac_id; ++} ++ ++void flush_all_cam_entry(_adapter *padapter) ++{ ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++#if 0 ++ unsigned char null_sta[] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00}; ++ unsigned char null_key[] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,0x00, 0x00, 0x00, 0x00,0x00, 0x00, 0x00, 0x00}; ++ ++ for (i = 0; i < NUM_STA; i++) ++ { ++ write_cam(padapter, i, 0, null_sta, null_key); ++ } ++#else ++ padapter->HalFunc.SetHwRegHandler(padapter, HW_VAR_CAM_INVALID_ALL, 0); ++#endif ++ _rtw_memset((u8 *)(pmlmeinfo->FW_sta_info), 0, sizeof(pmlmeinfo->FW_sta_info)); ++} ++ ++#ifdef CONFIG_WFD ++int WFD_info_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE) ++{ ++ struct registry_priv *pregpriv = &padapter->registrypriv; ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ struct wifidirect_info *pwdinfo; ++ u8 wfd_ie[ 128 ] = { 0x00 }; ++ u32 wfd_ielen = 0; ++ ++ ++ pwdinfo = &padapter->wdinfo; ++ if ( rtw_get_wfd_ie( ( u8* ) pIE, pIE->Length, wfd_ie, &wfd_ielen ) ) ++ { ++ u8 attr_content[ 10 ] = { 0x00 }; ++ u32 attr_contentlen = 0; ++ ++ printk( "[%s] Found WFD IE\n", __FUNCTION__ ); ++ rtw_get_wfd_attr_content( wfd_ie, wfd_ielen, WFD_ATTR_DEVICE_INFO, attr_content, &attr_contentlen); ++ if ( attr_contentlen ) ++ { ++ pwdinfo->wfd_info.peer_rtsp_ctrlport = RTW_GET_BE16( attr_content + 2 ); ++ DBG_8192C( "[%s] Peer PORT NUM = %d\n", __FUNCTION__, pwdinfo->wfd_info.peer_rtsp_ctrlport ); ++ return( _TRUE ); ++ } ++ } ++ else ++ { ++ printk( "[%s] NO WFD IE\n", __FUNCTION__ ); ++ ++ } ++ return( _FAIL ); ++} ++#endif ++ ++int WMM_param_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE) ++{ ++ struct registry_priv *pregpriv = &padapter->registrypriv; ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ ++ if(pmlmepriv->qospriv.qos_option==0) ++ { ++ pmlmeinfo->WMM_enable = 0; ++ return _FAIL; ++ } ++ ++ pmlmeinfo->WMM_enable = 1; ++ _rtw_memcpy(&(pmlmeinfo->WMM_param), (pIE->data + 6), sizeof(struct WMM_para_element)); ++ return _TRUE; ++ ++ /*if (pregpriv->wifi_spec == 1) ++ { ++ if (pmlmeinfo->WMM_enable == 1) ++ { ++ //todo: compare the parameter set count & decide wheher to update or not ++ return _FAIL; ++ } ++ else ++ { ++ pmlmeinfo->WMM_enable = 1; ++ _rtw_rtw_memcpy(&(pmlmeinfo->WMM_param), (pIE->data + 6), sizeof(struct WMM_para_element)); ++ return _TRUE; ++ } ++ } ++ else ++ { ++ pmlmeinfo->WMM_enable = 0; ++ return _FAIL; ++ }*/ ++ ++} ++ ++void WMMOnAssocRsp(_adapter *padapter) ++{ ++ u8 ACI, ACM, AIFS, ECWMin, ECWMax, aSifsTime; ++ u8 acm_mask; ++ u16 TXOP; ++ u32 acParm, i; ++ struct registry_priv *pregpriv = &padapter->registrypriv; ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ ++ if (pmlmeinfo->WMM_enable == 0) ++ { ++ padapter->mlmepriv.acm_mask = 0; ++ return; ++ } ++ ++ acm_mask = 0; ++ ++ if( pmlmeext->cur_wireless_mode == WIRELESS_11B) ++ aSifsTime = 10; ++ else ++ aSifsTime = 16; ++ ++ for (i = 0; i < 4; i++) ++ { ++ ACI = (pmlmeinfo->WMM_param.ac_param[i].ACI_AIFSN >> 5) & 0x03; ++ ACM = (pmlmeinfo->WMM_param.ac_param[i].ACI_AIFSN >> 4) & 0x01; ++ ++ //AIFS = AIFSN * slot time + SIFS - r2t phy delay ++ AIFS = (pmlmeinfo->WMM_param.ac_param[i].ACI_AIFSN & 0x0f) * pmlmeinfo->slotTime + aSifsTime; ++ ++ ECWMin = (pmlmeinfo->WMM_param.ac_param[i].CW & 0x0f); ++ ECWMax = (pmlmeinfo->WMM_param.ac_param[i].CW & 0xf0) >> 4; ++ TXOP = le16_to_cpu(pmlmeinfo->WMM_param.ac_param[i].TXOP_limit); ++ ++ acParm = AIFS | (ECWMin << 8) | (ECWMax << 12) | (TXOP << 16); ++ ++ switch (ACI) ++ { ++ case 0x0: ++ padapter->HalFunc.SetHwRegHandler(padapter, HW_VAR_AC_PARAM_BE, (u8 *)(&acParm)); ++ acm_mask |= (ACM? BIT(1):0); ++ break; ++ ++ case 0x1: ++ padapter->HalFunc.SetHwRegHandler(padapter, HW_VAR_AC_PARAM_BK, (u8 *)(&acParm)); ++ //acm_mask |= (ACM? BIT(0):0); ++ break; ++ ++ case 0x2: ++ padapter->HalFunc.SetHwRegHandler(padapter, HW_VAR_AC_PARAM_VI, (u8 *)(&acParm)); ++ acm_mask |= (ACM? BIT(2):0); ++ break; ++ ++ case 0x3: ++ padapter->HalFunc.SetHwRegHandler(padapter, HW_VAR_AC_PARAM_VO, (u8 *)(&acParm)); ++ acm_mask |= (ACM? BIT(3):0); ++ break; ++ } ++ ++ DBG_871X("WMM(%x): %x, %x\n", ACI, ACM, acParm); ++ } ++ ++ if(padapter->registrypriv.acm_method == 1) ++ padapter->HalFunc.SetHwRegHandler(padapter, HW_VAR_ACM_CTRL, (u8 *)(&acm_mask)); ++ else ++ padapter->mlmepriv.acm_mask = acm_mask; ++ ++ return; ++} ++ ++static void bwmode_update_check(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE) ++{ ++ unsigned char new_bwmode; ++ unsigned char new_ch_offset; ++ struct HT_info_element *pHT_info; ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ ++ ++ if(!pIE) ++ return; ++ ++ pHT_info = (struct HT_info_element *)pIE->data; ++ ++ if(pHT_info->infos[0] & BIT(2)) ++ { ++ new_bwmode = HT_CHANNEL_WIDTH_40; ++ switch (pHT_info->infos[0] & 0x3) ++ { ++ case 1: ++ new_ch_offset = HAL_PRIME_CHNL_OFFSET_LOWER; ++ break; ++ ++ case 3: ++ new_ch_offset = HAL_PRIME_CHNL_OFFSET_UPPER; ++ break; ++ ++ default: ++ new_ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; ++ break; ++ } ++ } ++ else ++ { ++ new_bwmode = HT_CHANNEL_WIDTH_20; ++ new_ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; ++ } ++ ++ ++ if((new_bwmode!= pmlmeext->cur_bwmode) || (new_ch_offset!=pmlmeext->cur_ch_offset)) ++ { ++ pmlmeinfo->bwmode_updated = _TRUE; ++ ++ pmlmeext->cur_bwmode = new_bwmode; ++ pmlmeext->cur_ch_offset = new_ch_offset; ++ } ++ else ++ { ++ pmlmeinfo->bwmode_updated = _FALSE; ++ } ++ ++ ++ if(_TRUE == pmlmeinfo->bwmode_updated) ++ { ++ struct sta_info *psta; ++ WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network); ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ ++ //set_channel_bwmode(padapter, pmlmeext->cur_channel, pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode); ++ ++ ++ //update ap's stainfo ++ psta = rtw_get_stainfo(pstapriv, cur_network->MacAddress); ++ if(psta) ++ { ++ struct ht_priv *phtpriv_sta = &psta->htpriv; ++ ++ if(phtpriv_sta->ht_option) ++ { ++ // bwmode ++ phtpriv_sta->bwmode = pmlmeext->cur_bwmode; ++ phtpriv_sta->ch_offset = pmlmeext->cur_ch_offset; ++ } ++ else ++ { ++ phtpriv_sta->bwmode = HT_CHANNEL_WIDTH_20; ++ phtpriv_sta->ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; ++ } ++ ++ } ++ ++ //pmlmeinfo->bwmode_updated = _FALSE;//bwmode_updated done, reset it! ++ ++ } ++ ++} ++ ++void HT_caps_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE) ++{ ++ unsigned int i; ++ u8 rf_type; ++ u8 max_AMPDU_len, min_MPDU_spacing; ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct ht_priv *phtpriv = &pmlmepriv->htpriv; ++ ++ if(pIE==NULL) return; ++ ++ if(phtpriv->ht_option == _FALSE) return; ++ ++ pmlmeinfo->HT_caps_enable = 1; ++ ++ for (i = 0; i < (pIE->Length); i++) ++ { ++ if (i != 2) ++ { ++ // Commented by Albert 2010/07/12 ++ // Got the endian issue here. ++ pmlmeinfo->HT_caps.HT_cap[i] &= (pIE->data[i]); ++ } ++ else ++ { ++ //modify from fw by Thomas 2010/11/17 ++ if ((pmlmeinfo->HT_caps.HT_cap_element.AMPDU_para & 0x3) > (pIE->data[i] & 0x3)) ++ { ++ max_AMPDU_len = (pIE->data[i] & 0x3); ++ } ++ else ++ { ++ max_AMPDU_len = (pmlmeinfo->HT_caps.HT_cap_element.AMPDU_para & 0x3); ++ } ++ ++ if ((pmlmeinfo->HT_caps.HT_cap_element.AMPDU_para & 0x1c) > (pIE->data[i] & 0x1c)) ++ { ++ min_MPDU_spacing = (pmlmeinfo->HT_caps.HT_cap_element.AMPDU_para & 0x1c); ++ } ++ else ++ { ++ min_MPDU_spacing = (pIE->data[i] & 0x1c); ++ } ++ ++ pmlmeinfo->HT_caps.HT_cap_element.AMPDU_para = max_AMPDU_len | min_MPDU_spacing; ++ } ++ } ++ ++ // Commented by Albert 2010/07/12 ++ // Have to handle the endian issue after copying. ++ // HT_ext_caps didn't be used yet. ++ pmlmeinfo->HT_caps.HT_cap_element.HT_caps_info = le16_to_cpu( pmlmeinfo->HT_caps.HT_cap_element.HT_caps_info ); ++ pmlmeinfo->HT_caps.HT_cap_element.HT_ext_caps = le16_to_cpu( pmlmeinfo->HT_caps.HT_cap_element.HT_ext_caps ); ++ ++ padapter->HalFunc.GetHwRegHandler(padapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type)); ++ ++ //update the MCS rates ++ for (i = 0; i < 16; i++) ++ { ++ if((rf_type == RF_1T1R) || (rf_type == RF_1T2R)) ++ { ++ pmlmeinfo->HT_caps.HT_cap_element.MCS_rate[i] &= MCS_rate_1R[i]; ++ } ++ else ++ { ++ pmlmeinfo->HT_caps.HT_cap_element.MCS_rate[i] &= MCS_rate_2R[i]; ++ } ++ #ifdef RTL8192C_RECONFIG_TO_1T1R ++ { ++ pmlmeinfo->HT_caps.HT_cap_element.MCS_rate[i] &= MCS_rate_1R[i]; ++ } ++ #endif ++ } ++ ++ return; ++} ++ ++void HT_info_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE) ++{ ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct ht_priv *phtpriv = &pmlmepriv->htpriv; ++ ++ if(pIE==NULL) return; ++ ++ if(phtpriv->ht_option == _FALSE) return; ++ ++ ++ if(pIE->Length > sizeof(struct HT_info_element)) ++ return; ++ ++ pmlmeinfo->HT_info_enable = 1; ++ _rtw_memcpy(&(pmlmeinfo->HT_info), pIE->data, pIE->Length); ++ ++ return; ++} ++ ++void HTOnAssocRsp(_adapter *padapter) ++{ ++ unsigned char max_AMPDU_len; ++ unsigned char min_MPDU_spacing; ++ //struct registry_priv *pregpriv = &padapter->registrypriv; ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ //WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network); ++ ++ DBG_871X("%s\n", __FUNCTION__); ++ ++ if ((pmlmeinfo->HT_info_enable) && (pmlmeinfo->HT_caps_enable)) ++ { ++ pmlmeinfo->HT_enable = 1; ++ } ++ else ++ { ++ pmlmeinfo->HT_enable = 0; ++ //set_channel_bwmode(padapter, pmlmeext->cur_channel, pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode); ++ return; ++ } ++ ++ //handle A-MPDU parameter field ++ /* ++ AMPDU_para [1:0]:Max AMPDU Len => 0:8k , 1:16k, 2:32k, 3:64k ++ AMPDU_para [4:2]:Min MPDU Start Spacing ++ */ ++ max_AMPDU_len = pmlmeinfo->HT_caps.HT_cap_element.AMPDU_para & 0x03; ++ ++ min_MPDU_spacing = (pmlmeinfo->HT_caps.HT_cap_element.AMPDU_para & 0x1c) >> 2; ++ ++ padapter->HalFunc.SetHwRegHandler(padapter, HW_VAR_AMPDU_MIN_SPACE, (u8 *)(&min_MPDU_spacing)); ++ ++ padapter->HalFunc.SetHwRegHandler(padapter, HW_VAR_AMPDU_FACTOR, (u8 *)(&max_AMPDU_len)); ++ ++#if 0 //move to rtw_update_ht_cap() ++ if ((pregpriv->cbw40_enable) && ++ (pmlmeinfo->HT_caps.HT_cap_element.HT_caps_info & BIT(1)) && ++ (pmlmeinfo->HT_info.infos[0] & BIT(2))) ++ { ++ //switch to the 40M Hz mode accoring to the AP ++ pmlmeext->cur_bwmode = HT_CHANNEL_WIDTH_40; ++ switch ((pmlmeinfo->HT_info.infos[0] & 0x3)) ++ { ++ case HT_EXTCHNL_OFFSET_UPPER: ++ pmlmeext->cur_ch_offset = HAL_PRIME_CHNL_OFFSET_LOWER; ++ break; ++ ++ case HT_EXTCHNL_OFFSET_LOWER: ++ pmlmeext->cur_ch_offset = HAL_PRIME_CHNL_OFFSET_UPPER; ++ break; ++ ++ default: ++ pmlmeext->cur_ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; ++ break; ++ } ++ ++ //SelectChannel(padapter, pmlmeext->cur_channel, pmlmeext->cur_ch_offset); ++ } ++#endif ++ ++ //set_channel_bwmode(padapter, pmlmeext->cur_channel, pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode); ++ ++#if 0 //move to rtw_update_ht_cap() ++ // ++ // Config SM Power Save setting ++ // ++ pmlmeinfo->SM_PS = (pmlmeinfo->HT_caps.HT_cap_element.HT_caps_info & 0x0C) >> 2; ++ if(pmlmeinfo->SM_PS == WLAN_HT_CAP_SM_PS_STATIC) ++ { ++ /*u8 i; ++ //update the MCS rates ++ for (i = 0; i < 16; i++) ++ { ++ pmlmeinfo->HT_caps.HT_cap_element.MCS_rate[i] &= MCS_rate_1R[i]; ++ }*/ ++ DBG_8192C("%s(): WLAN_HT_CAP_SM_PS_STATIC\n",__FUNCTION__); ++ } ++ ++ // ++ // Config current HT Protection mode. ++ // ++ pmlmeinfo->HT_protection = pmlmeinfo->HT_info.infos[1] & 0x3; ++#endif ++ ++} ++ ++void ERP_IE_handler(_adapter *padapter, PNDIS_802_11_VARIABLE_IEs pIE) ++{ ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ ++ if(pIE->Length>1) ++ return; ++ ++ pmlmeinfo->ERP_enable = 1; ++ _rtw_memcpy(&(pmlmeinfo->ERP_IE), pIE->data, pIE->Length); ++} ++ ++void VCS_update(_adapter *padapter, struct sta_info *psta) ++{ ++ struct registry_priv *pregpriv = &padapter->registrypriv; ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ ++ switch (pregpriv->vrtl_carrier_sense)/* 0:off 1:on 2:auto */ ++ { ++ case 0: //off ++ psta->rtsen = 0; ++ psta->cts2self = 0; ++ break; ++ ++ case 1: //on ++ if (pregpriv->vcs_type == 1) /* 1:RTS/CTS 2:CTS to self */ ++ { ++ psta->rtsen = 1; ++ psta->cts2self = 0; ++ } ++ else ++ { ++ psta->rtsen = 0; ++ psta->cts2self = 1; ++ } ++ break; ++ ++ case 2: //auto ++ default: ++ if ((pmlmeinfo->ERP_enable) && (pmlmeinfo->ERP_IE & BIT(1))) ++ { ++ if (pregpriv->vcs_type == 1) ++ { ++ psta->rtsen = 1; ++ psta->cts2self = 0; ++ } ++ else ++ { ++ psta->rtsen = 0; ++ psta->cts2self = 1; ++ } ++ } ++ else ++ { ++ psta->rtsen = 0; ++ psta->cts2self = 0; ++ } ++ break; ++ } ++} ++ ++void update_beacon_info(_adapter *padapter, u8 *pframe, uint pkt_len, struct sta_info *psta) ++{ ++ unsigned int i; ++ unsigned int len; ++ PNDIS_802_11_VARIABLE_IEs pIE; ++ ++#ifdef CONFIG_TDLS ++ struct tdls_info *ptdlsinfo = &padapter->tdlsinfo; ++ u8 tdls_prohibited[] = { 0x00, 0x00, 0x00, 0x00, 0x10 }; //bit(38): TDLS_prohibited ++#endif ++ ++ len = pkt_len - (_BEACON_IE_OFFSET_ + WLAN_HDR_A3_LEN); ++ ++ for (i = 0; i < len;) ++ { ++ pIE = (PNDIS_802_11_VARIABLE_IEs)(pframe + (_BEACON_IE_OFFSET_ + WLAN_HDR_A3_LEN) + i); ++ ++ switch (pIE->ElementID) ++ { ++#if 0 ++ case _VENDOR_SPECIFIC_IE_: ++ //todo: to update WMM paramter set while receiving beacon ++ if (_rtw_memcmp(pIE->data, WMM_PARA_OUI, 6)) //WMM ++ { ++ (WMM_param_handler(padapter, pIE))? WMMOnAssocRsp(padapter): 0; ++ } ++ break; ++#endif ++ ++ case _HT_EXTRA_INFO_IE_: //HT info ++ //HT_info_handler(padapter, pIE); ++ bwmode_update_check(padapter, pIE); ++ break; ++ ++ case _ERPINFO_IE_: ++ ERP_IE_handler(padapter, pIE); ++ VCS_update(padapter, psta); ++ break; ++ ++#ifdef CONFIG_TDLS ++ case _EXT_CAP_IE_: ++ if( _rtw_memcmp(pIE->data, tdls_prohibited, 5) == _TRUE ) ++ ptdlsinfo->ap_prohibited = _TRUE; ++ break; ++#endif ++ default: ++ break; ++ } ++ ++ i += (pIE->Length + 2); ++ } ++} ++ ++#ifdef CONFIG_DFS ++void process_csa_ie(_adapter *padapter, u8 *pframe, uint pkt_len) ++{ ++ unsigned int i; ++ unsigned int len; ++ PNDIS_802_11_VARIABLE_IEs pIE; ++ u8 new_ch_no = 0; ++ ++ len = pkt_len - (_BEACON_IE_OFFSET_ + WLAN_HDR_A3_LEN); ++ ++ for (i = 0; i < len;) ++ { ++ pIE = (PNDIS_802_11_VARIABLE_IEs)(pframe + (_BEACON_IE_OFFSET_ + WLAN_HDR_A3_LEN) + i); ++ ++ switch (pIE->ElementID) ++ { ++ case _CH_SWTICH_ANNOUNCE_: ++ _rtw_memcpy(&new_ch_no, pIE->data+1, 1); ++ rtw_set_csa_cmd(padapter, new_ch_no); ++ break; ++ ++ default: ++ break; ++ } ++ ++ i += (pIE->Length + 2); ++ } ++} ++#endif //CONFIG_DFS ++ ++unsigned int is_ap_in_tkip(_adapter *padapter) ++{ ++ u32 i; ++ PNDIS_802_11_VARIABLE_IEs pIE; ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network); ++ ++ if (rtw_get_capability((WLAN_BSSID_EX *)cur_network) & WLAN_CAPABILITY_PRIVACY) ++ { ++ for (i = sizeof(NDIS_802_11_FIXED_IEs); i < pmlmeinfo->network.IELength;) ++ { ++ pIE = (PNDIS_802_11_VARIABLE_IEs)(pmlmeinfo->network.IEs + i); ++ ++ switch (pIE->ElementID) ++ { ++ case _VENDOR_SPECIFIC_IE_: ++ if ((_rtw_memcmp(pIE->data, WPA_OUI, 4)) && (_rtw_memcmp((pIE->data + 12), WPA_TKIP_CIPHER, 4))) ++ { ++ return _TRUE; ++ } ++ break; ++ ++ case _RSN_IE_2_: ++ if (_rtw_memcmp((pIE->data + 8), RSN_TKIP_CIPHER, 4)) ++ { ++ return _TRUE; ++ } ++ ++ default: ++ break; ++ } ++ ++ i += (pIE->Length + 2); ++ } ++ ++ return _FALSE; ++ } ++ else ++ { ++ return _FALSE; ++ } ++ ++} ++ ++int wifirate2_ratetbl_inx(unsigned char rate) ++{ ++ int inx = 0; ++ rate = rate & 0x7f; ++ ++ switch (rate) ++ { ++ case 54*2: ++ inx = 11; ++ break; ++ ++ case 48*2: ++ inx = 10; ++ break; ++ ++ case 36*2: ++ inx = 9; ++ break; ++ ++ case 24*2: ++ inx = 8; ++ break; ++ ++ case 18*2: ++ inx = 7; ++ break; ++ ++ case 12*2: ++ inx = 6; ++ break; ++ ++ case 9*2: ++ inx = 5; ++ break; ++ ++ case 6*2: ++ inx = 4; ++ break; ++ ++ case 11*2: ++ inx = 3; ++ break; ++ case 11: ++ inx = 2; ++ break; ++ ++ case 2*2: ++ inx = 1; ++ break; ++ ++ case 1*2: ++ inx = 0; ++ break; ++ ++ } ++ return inx; ++} ++ ++unsigned int update_basic_rate(unsigned char *ptn, unsigned int ptn_sz) ++{ ++ unsigned int i, num_of_rate; ++ unsigned int mask = 0; ++ ++ num_of_rate = (ptn_sz > NumRates)? NumRates: ptn_sz; ++ ++ for (i = 0; i < num_of_rate; i++) ++ { ++ if ((*(ptn + i)) & 0x80) ++ { ++ mask |= 0x1 << wifirate2_ratetbl_inx(*(ptn + i)); ++ } ++ } ++ return mask; ++} ++ ++unsigned int update_supported_rate(unsigned char *ptn, unsigned int ptn_sz) ++{ ++ unsigned int i, num_of_rate; ++ unsigned int mask = 0; ++ ++ num_of_rate = (ptn_sz > NumRates)? NumRates: ptn_sz; ++ ++ for (i = 0; i < num_of_rate; i++) ++ { ++ mask |= 0x1 << wifirate2_ratetbl_inx(*(ptn + i)); ++ } ++ ++ return mask; ++} ++ ++unsigned int update_MSC_rate(struct HT_caps_element *pHT_caps) ++{ ++ unsigned int mask = 0; ++ ++ mask = ((pHT_caps->HT_cap_element.MCS_rate[0] << 12) | (pHT_caps->HT_cap_element.MCS_rate[1] << 20)); ++ ++ return mask; ++} ++ ++int support_short_GI(_adapter *padapter, struct HT_caps_element *pHT_caps) ++{ ++ unsigned char bit_offset; ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ ++ if (!(pmlmeinfo->HT_enable)) ++ return _FAIL; ++ ++ if ((pmlmeinfo->assoc_AP_vendor == ralinkAP)) ++ return _FAIL; ++ ++ bit_offset = (pmlmeext->cur_bwmode & HT_CHANNEL_WIDTH_40)? 6: 5; ++ ++ if (pHT_caps->HT_cap_element.HT_caps_info & (0x1 << bit_offset)) ++ { ++ return _SUCCESS; ++ } ++ else ++ { ++ return _FAIL; ++ } ++} ++ ++unsigned char get_highest_rate_idx(u32 mask) ++{ ++ int i; ++ unsigned char rate_idx=0; ++ ++ for(i=27; i>=0; i--) ++ { ++ if(mask & BIT(i)) ++ { ++ rate_idx = i; ++ break; ++ } ++ } ++ ++ return rate_idx; ++} ++ ++unsigned char get_highest_mcs_rate(struct HT_caps_element *pHT_caps) ++{ ++ int i, mcs_rate; ++ ++ mcs_rate = (pHT_caps->HT_cap_element.MCS_rate[0] | (pHT_caps->HT_cap_element.MCS_rate[1] << 8)); ++ ++ for (i = 15; i >= 0; i--) ++ { ++ if (mcs_rate & (0x1 << i)) ++ { ++ break; ++ } ++ } ++ ++ return i; ++} ++ ++void Update_RA_Entry(_adapter *padapter, u32 mac_id) ++{ ++ padapter->HalFunc.UpdateRAMaskHandler(padapter, mac_id); ++} ++ ++void enable_rate_adaptive(_adapter *padapter, u32 mac_id) ++{ ++ Update_RA_Entry(padapter, mac_id); ++} ++ ++void set_sta_rate(_adapter *padapter, struct sta_info *psta) ++{ ++ //rate adaptive ++ enable_rate_adaptive(padapter, psta->mac_id); ++} ++ ++unsigned char check_assoc_AP(u8 *pframe, uint len) ++{ ++ unsigned int i; ++ PNDIS_802_11_VARIABLE_IEs pIE; ++ ++ for (i = sizeof(NDIS_802_11_FIXED_IEs); i < len;) ++ { ++ pIE = (PNDIS_802_11_VARIABLE_IEs)(pframe + i); ++ ++ switch (pIE->ElementID) ++ { ++ case _VENDOR_SPECIFIC_IE_: ++ if ((_rtw_memcmp(pIE->data, ARTHEROS_OUI1, 3)) || (_rtw_memcmp(pIE->data, ARTHEROS_OUI2, 3))) ++ { ++ DBG_871X("link to Artheros AP\n"); ++ return atherosAP; ++ } ++ else if ((_rtw_memcmp(pIE->data, BROADCOM_OUI1, 3)) ++ || (_rtw_memcmp(pIE->data, BROADCOM_OUI2, 3)) ++ || (_rtw_memcmp(pIE->data, BROADCOM_OUI2, 3))) ++ { ++ DBG_871X("link to Broadcom AP\n"); ++ return broadcomAP; ++ } ++ else if (_rtw_memcmp(pIE->data, MARVELL_OUI, 3)) ++ { ++ DBG_871X("link to Marvell AP\n"); ++ return marvellAP; ++ } ++ else if (_rtw_memcmp(pIE->data, RALINK_OUI, 3)) ++ { ++ DBG_871X("link to Ralink AP\n"); ++ return ralinkAP; ++ } ++ else if (_rtw_memcmp(pIE->data, CISCO_OUI, 3)) ++ { ++ DBG_871X("link to Cisco AP\n"); ++ return ciscoAP; ++ } ++ else if (_rtw_memcmp(pIE->data, REALTEK_OUI, 3)) ++ { ++ DBG_871X("link to Realtek 96B\n"); ++ return realtekAP; ++ } ++ else if (_rtw_memcmp(pIE->data, AIRGOCAP_OUI,3)) ++ { ++ DBG_871X("link to Airgo Cap\n"); ++ return airgocapAP; ++ } ++ else ++ { ++ break; ++ } ++ ++ default: ++ break; ++ } ++ ++ i += (pIE->Length + 2); ++ } ++ ++ DBG_871X("link to new AP\n"); ++ return unknownAP; ++} ++ ++void update_IOT_info(_adapter *padapter) ++{ ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ ++ switch (pmlmeinfo->assoc_AP_vendor) ++ { ++ case marvellAP: ++ pmlmeinfo->turboMode_cts2self = 1; ++ pmlmeinfo->turboMode_rtsen = 0; ++ break; ++ ++ case ralinkAP: ++ pmlmeinfo->turboMode_cts2self = 0; ++ pmlmeinfo->turboMode_rtsen = 1; ++ //disable high power ++ Switch_DM_Func(padapter, (~DYNAMIC_FUNC_HP), _FALSE); ++ break; ++ case realtekAP: ++ //rtw_write16(padapter, 0x4cc, 0xffff); ++ //rtw_write16(padapter, 0x546, 0x01c0); ++ //disable high power ++ Switch_DM_Func(padapter, (~DYNAMIC_FUNC_HP), _FALSE); ++ break; ++ default: ++ pmlmeinfo->turboMode_cts2self = 0; ++ pmlmeinfo->turboMode_rtsen = 1; ++ break; ++ } ++ ++} ++ ++void update_capinfo(PADAPTER Adapter, u16 updateCap) ++{ ++ struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ BOOLEAN ShortPreamble; ++ ++ // Check preamble mode, 2005.01.06, by rcnjko. ++ // Mark to update preamble value forever, 2008.03.18 by lanhsin ++ //if( pMgntInfo->RegPreambleMode == PREAMBLE_AUTO ) ++ { ++ ++ if(updateCap & cShortPreamble) ++ { // Short Preamble ++ if(pmlmeinfo->preamble_mode != PREAMBLE_SHORT) // PREAMBLE_LONG or PREAMBLE_AUTO ++ { ++ ShortPreamble = _TRUE; ++ pmlmeinfo->preamble_mode = PREAMBLE_SHORT; ++ Adapter->HalFunc.SetHwRegHandler( Adapter, HW_VAR_ACK_PREAMBLE, (u8 *)&ShortPreamble ); ++ } ++ } ++ else ++ { // Long Preamble ++ if(pmlmeinfo->preamble_mode != PREAMBLE_LONG) // PREAMBLE_SHORT or PREAMBLE_AUTO ++ { ++ ShortPreamble = _FALSE; ++ pmlmeinfo->preamble_mode = PREAMBLE_LONG; ++ Adapter->HalFunc.SetHwRegHandler( Adapter, HW_VAR_ACK_PREAMBLE, (u8 *)&ShortPreamble ); ++ } ++ } ++ } ++ ++ if ( updateCap & cIBSS ) { ++ //Filen: See 802.11-2007 p.91 ++ pmlmeinfo->slotTime = NON_SHORT_SLOT_TIME; ++ } ++ else ++ { ++ //Filen: See 802.11-2007 p.90 ++ if( pmlmeext->cur_wireless_mode & (WIRELESS_11G | WIRELESS_11_24N)) ++ { ++ if( (updateCap & cShortSlotTime) /* && (!(pMgntInfo->pHTInfo->RT2RT_HT_Mode & RT_HT_CAP_USE_LONG_PREAMBLE)) */) ++ { // Short Slot Time ++ if(pmlmeinfo->slotTime != SHORT_SLOT_TIME) ++ { ++ pmlmeinfo->slotTime = SHORT_SLOT_TIME; ++ } ++ } ++ else ++ { // Long Slot Time ++ if(pmlmeinfo->slotTime != NON_SHORT_SLOT_TIME) ++ { ++ pmlmeinfo->slotTime = NON_SHORT_SLOT_TIME; ++ } ++ } ++ } ++ else if( pmlmeext->cur_wireless_mode & (WIRELESS_11A | WIRELESS_11_5N)) ++ { ++ pmlmeinfo->slotTime = SHORT_SLOT_TIME; ++ } ++ else ++ { ++ //B Mode ++ pmlmeinfo->slotTime = NON_SHORT_SLOT_TIME; ++ } ++ } ++ ++ Adapter->HalFunc.SetHwRegHandler( Adapter, HW_VAR_SLOT_TIME, &pmlmeinfo->slotTime ); ++ ++} ++ ++void update_wireless_mode(_adapter *padapter) ++{ ++ int ratelen, network_type = 0; ++ u16 SIFS_Timer; ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network); ++ unsigned char *rate = cur_network->SupportedRates; ++ ++ ratelen = rtw_get_rateset_len(cur_network->SupportedRates); ++ ++ if ((pmlmeinfo->HT_info_enable) && (pmlmeinfo->HT_caps_enable)) ++ { ++ pmlmeinfo->HT_enable = 1; ++ } ++ ++ if(pmlmeext->cur_channel > 14) ++ { ++ if (pmlmeinfo->HT_enable) ++ { ++ network_type = WIRELESS_11_5N; ++ } ++ ++ network_type |= WIRELESS_11A; ++ } ++ else ++ { ++ if (pmlmeinfo->HT_enable) ++ { ++ network_type = WIRELESS_11_24N; ++ } ++ ++ if ((cckratesonly_included(rate, ratelen)) == _TRUE) ++ { ++ network_type |= WIRELESS_11B; ++ } ++ else if((cckrates_included(rate, ratelen)) == _TRUE) ++ { ++ network_type |= WIRELESS_11BG; ++ } ++ else ++ { ++ network_type |= WIRELESS_11G; ++ } ++ } ++ ++ pmlmeext->cur_wireless_mode = network_type & padapter->registrypriv.wireless_mode; ++ if((pmlmeext->cur_wireless_mode==WIRELESS_11G) || ++ (pmlmeext->cur_wireless_mode==WIRELESS_11BG))//WIRELESS_MODE_G) ++ SIFS_Timer = 0x0a0a; ++ else ++ SIFS_Timer = 0x0e0e;//pHalData->SifsTime; ++ padapter->HalFunc.SetHwRegHandler( padapter, HW_VAR_SIFS, (u8 *)&SIFS_Timer); ++ ++} ++ ++ ++void fire_write_MAC_cmd(_adapter *padapter, unsigned int addr, unsigned int value) ++{ ++#if 0 ++ struct cmd_obj *ph2c; ++ struct reg_rw_parm *pwriteMacPara; ++ struct cmd_priv *pcmdpriv = &(padapter->cmdpriv); ++ ++ if ((ph2c = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj))) == NULL) ++ { ++ return; ++ } ++ ++ if ((pwriteMacPara = (struct reg_rw_parm*)rtw_malloc(sizeof(struct reg_rw_parm))) == NULL) ++ { ++ rtw_mfree((unsigned char *)ph2c, sizeof(struct cmd_obj)); ++ return; ++ } ++ ++ pwriteMacPara->rw = 1; ++ pwriteMacPara->addr = addr; ++ pwriteMacPara->value = value; ++ ++ init_h2fwcmd_w_parm_no_rsp(ph2c, pwriteMacPara, GEN_CMD_CODE(_Write_MACREG)); ++ rtw_enqueue_cmd(pcmdpriv, ph2c); ++#endif ++} ++ ++u8 bmc_support_rate_ofdm[4] = ++ {IEEE80211_OFDM_RATE_6MB|IEEE80211_BASIC_RATE_MASK, IEEE80211_OFDM_RATE_12MB|IEEE80211_BASIC_RATE_MASK, ++ IEEE80211_OFDM_RATE_18MB|IEEE80211_BASIC_RATE_MASK, IEEE80211_OFDM_RATE_24MB|IEEE80211_BASIC_RATE_MASK}; ++u8 bmc_support_rate_cck[4] = ++ {IEEE80211_CCK_RATE_1MB|IEEE80211_BASIC_RATE_MASK, IEEE80211_CCK_RATE_2MB|IEEE80211_BASIC_RATE_MASK, ++ IEEE80211_CCK_RATE_5MB|IEEE80211_BASIC_RATE_MASK, IEEE80211_CCK_RATE_11MB|IEEE80211_BASIC_RATE_MASK}; ++ ++void update_bmc_sta_support_rate(_adapter *padapter, u32 mac_id) ++{ ++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ ++ if(pmlmeext->cur_wireless_mode & WIRELESS_11B) ++ { ++ // Only B, B/G, and B/G/N AP could use CCK rate ++ _rtw_memcpy((pmlmeinfo->FW_sta_info[mac_id].SupportedRates), bmc_support_rate_cck, 4); ++ } ++ else ++ { ++ _rtw_memcpy((pmlmeinfo->FW_sta_info[mac_id].SupportedRates), bmc_support_rate_ofdm, 4); ++ } ++} ++ ++int update_sta_support_rate(_adapter *padapter, u8* pvar_ie, uint var_ie_len, int cam_idx) ++{ ++ unsigned int ie_len; ++ PNDIS_802_11_VARIABLE_IEs pIE; ++ int supportRateNum = 0; ++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ ++ pIE = (PNDIS_802_11_VARIABLE_IEs)rtw_get_ie(pvar_ie, _SUPPORTEDRATES_IE_, &ie_len, var_ie_len); ++ if (pIE == NULL) ++ { ++ return _FAIL; ++ } ++ ++ _rtw_memcpy(pmlmeinfo->FW_sta_info[cam_idx].SupportedRates, pIE->data, ie_len); ++ supportRateNum = ie_len; ++ ++ pIE = (PNDIS_802_11_VARIABLE_IEs)rtw_get_ie(pvar_ie, _EXT_SUPPORTEDRATES_IE_, &ie_len, var_ie_len); ++ if (pIE) ++ { ++ _rtw_memcpy((pmlmeinfo->FW_sta_info[cam_idx].SupportedRates + supportRateNum), pIE->data, ie_len); ++ } ++ ++ return _SUCCESS; ++ ++} ++ ++void process_addba_req(_adapter *padapter, u8 *paddba_req, u8 *addr) ++{ ++ struct sta_info *psta; ++ u16 tid, start_seq, param; ++ struct recv_reorder_ctrl *preorder_ctrl; ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ struct ADDBA_request *preq = (struct ADDBA_request*)paddba_req; ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ ++ psta = rtw_get_stainfo(pstapriv, addr); ++ ++ if(psta) ++ { ++ start_seq = le16_to_cpu(preq->BA_starting_seqctrl) >> 4; ++ ++ param = le16_to_cpu(preq->BA_para_set); ++ tid = (param>>2)&0x0f; ++ ++ preorder_ctrl = &psta->recvreorder_ctrl[tid]; ++ ++ #ifdef CONFIG_UPDATE_INDICATE_SEQ_WHILE_PROCESS_ADDBA_REQ ++ preorder_ctrl->indicate_seq = start_seq; ++ #ifdef DBG_RX_SEQ ++ DBG_871X("DBG_RX_SEQ %s:%d IndicateSeq: %d, start_seq: %d\n", __FUNCTION__, __LINE__, ++ preorder_ctrl->indicate_seq, start_seq); ++ #endif ++ #else ++ preorder_ctrl->indicate_seq = 0xffff; ++ #endif ++ ++ preorder_ctrl->enable =(pmlmeinfo->bAcceptAddbaReq == _TRUE)? _TRUE :_FALSE; ++ } ++ ++} ++ ++void update_TSF(struct mlme_ext_priv *pmlmeext, u8 *pframe, uint len) ++{ ++ u8* pIE; ++ u32 *pbuf; ++ ++ pIE = pframe + sizeof(struct rtw_ieee80211_hdr_3addr); ++ pbuf = (u32*)pIE; ++ ++ pmlmeext->TSFValue = le32_to_cpu(*(pbuf+1)); ++ ++ pmlmeext->TSFValue = pmlmeext->TSFValue << 32; ++ ++ pmlmeext->TSFValue |= le32_to_cpu(*pbuf); ++} ++ ++void correct_TSF(_adapter *padapter, struct mlme_ext_priv *pmlmeext) ++{ ++ padapter->HalFunc.SetHwRegHandler(padapter, HW_VAR_CORRECT_TSF, 0); ++} ++ ++void beacon_timing_control(_adapter *padapter) ++{ ++ padapter->HalFunc.SetBeaconRelatedRegistersHandler(padapter); ++} ++ ++#if 0 ++unsigned int setup_beacon_frame(_adapter *padapter, unsigned char *beacon_frame) ++{ ++ unsigned short ATIMWindow; ++ unsigned char *pframe; ++ struct tx_desc *ptxdesc; ++ struct rtw_ieee80211_hdr *pwlanhdr; ++ unsigned short *fctrl; ++ unsigned int rate_len, len = 0; ++ struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); ++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network); ++ u8 bc_addr[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; ++ ++ _rtw_memset(beacon_frame, 0, 256); ++ ++ pframe = beacon_frame + TXDESC_SIZE; ++ ++ pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; ++ ++ fctrl = &(pwlanhdr->frame_ctl); ++ *(fctrl) = 0; ++ ++ _rtw_memcpy(pwlanhdr->addr1, bc_addr, ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr2, myid(&(padapter->eeprompriv)), ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(cur_network), ETH_ALEN); ++ ++ SetFrameSubType(pframe, WIFI_BEACON); ++ ++ pframe += sizeof(struct rtw_ieee80211_hdr_3addr); ++ len = sizeof(struct rtw_ieee80211_hdr_3addr); ++ ++ //timestamp will be inserted by hardware ++ pframe += 8; ++ len += 8; ++ ++ // beacon interval: 2 bytes ++ _rtw_memcpy(pframe, (unsigned char *)(rtw_get_beacon_interval_from_ie(cur_network->IEs)), 2); ++ ++ pframe += 2; ++ len += 2; ++ ++ // capability info: 2 bytes ++ _rtw_memcpy(pframe, (unsigned char *)(rtw_get_capability_from_ie(cur_network->IEs)), 2); ++ ++ pframe += 2; ++ len += 2; ++ ++ // SSID ++ pframe = rtw_set_ie(pframe, _SSID_IE_, cur_network->Ssid.SsidLength, cur_network->Ssid.Ssid, &len); ++ ++ // supported rates... ++ rate_len = rtw_get_rateset_len(cur_network->SupportedRates); ++ pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_, ((rate_len > 8)? 8: rate_len), cur_network->SupportedRates, &len); ++ ++ // DS parameter set ++ pframe = rtw_set_ie(pframe, _DSSET_IE_, 1, (unsigned char *)&(cur_network->Configuration.DSConfig), &len); ++ ++ // IBSS Parameter Set... ++ //ATIMWindow = cur->Configuration.ATIMWindow; ++ ATIMWindow = 0; ++ pframe = rtw_set_ie(pframe, _IBSS_PARA_IE_, 2, (unsigned char *)(&ATIMWindow), &len); ++ ++ //todo: ERP IE ++ ++ // EXTERNDED SUPPORTED RATE ++ if (rate_len > 8) ++ { ++ pframe = rtw_set_ie(pframe, _EXT_SUPPORTEDRATES_IE_, (rate_len - 8), (cur_network->SupportedRates + 8), &len); ++ } ++ ++ if ((len + TXDESC_SIZE) > 256) ++ { ++ //DBG_8192C("marc: beacon frame too large\n"); ++ return 0; ++ } ++ ++ //fill the tx descriptor ++ ptxdesc = (struct tx_desc *)beacon_frame; ++ ++ //offset 0 ++ ptxdesc->txdw0 |= cpu_to_le32(len & 0x0000ffff); ++ ptxdesc->txdw0 |= cpu_to_le32(((TXDESC_SIZE + OFFSET_SZ) << OFFSET_SHT) & 0x00ff0000); //default = 32 bytes for TX Desc ++ ++ //offset 4 ++ ptxdesc->txdw1 |= cpu_to_le32((0x10 << QSEL_SHT) & 0x00001f00); ++ ++ //offset 8 ++ ptxdesc->txdw2 |= cpu_to_le32(BMC); ++ ptxdesc->txdw2 |= cpu_to_le32(BK); ++ ++ //offset 16 ++ ptxdesc->txdw4 = 0x80000000; ++ ++ //offset 20 ++ ptxdesc->txdw5 = 0x00000000; //1M ++ ++ return (len + TXDESC_SIZE); ++} ++#endif ++ +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/core/rtw_xmit.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/core/rtw_xmit.c 2013-07-26 19:36:05.000000000 +0000 +@@ -0,0 +1,4277 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++******************************************************************************/ ++#define _RTW_XMIT_C_ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#ifdef CONFIG_TDLS ++#include ++#endif ++ ++#if defined (PLATFORM_LINUX) && defined (PLATFORM_WINDOWS) ++#error "Shall be Linux or Windows, but not both!\n" ++#endif ++ ++#ifdef PLATFORM_WINDOWS ++#include ++#endif ++ ++#ifdef CONFIG_USB_HCI ++#include ++#endif ++ ++ ++static u8 P802_1H_OUI[P80211_OUI_LEN] = { 0x00, 0x00, 0xf8 }; ++static u8 RFC1042_OUI[P80211_OUI_LEN] = { 0x00, 0x00, 0x00 }; ++ ++#ifdef CONFIG_TDLS ++extern unsigned char MCS_rate_2R[16]; ++extern unsigned char MCS_rate_1R[16]; ++#endif ++ ++static void _init_txservq(struct tx_servq *ptxservq) ++{ ++_func_enter_; ++ _rtw_init_listhead(&ptxservq->tx_pending); ++ _rtw_init_queue(&ptxservq->sta_pending); ++ ptxservq->qcnt = 0; ++_func_exit_; ++} ++ ++ ++void _rtw_init_sta_xmit_priv(struct sta_xmit_priv *psta_xmitpriv) ++{ ++ ++_func_enter_; ++ ++ _rtw_memset((unsigned char *)psta_xmitpriv, 0, sizeof (struct sta_xmit_priv)); ++ ++ _rtw_spinlock_init(&psta_xmitpriv->lock); ++ ++ //for(i = 0 ; i < MAX_NUMBLKS; i++) ++ // _init_txservq(&(psta_xmitpriv->blk_q[i])); ++ ++ _init_txservq(&psta_xmitpriv->be_q); ++ _init_txservq(&psta_xmitpriv->bk_q); ++ _init_txservq(&psta_xmitpriv->vi_q); ++ _init_txservq(&psta_xmitpriv->vo_q); ++ _rtw_init_listhead(&psta_xmitpriv->legacy_dz); ++ _rtw_init_listhead(&psta_xmitpriv->apsd); ++ ++_func_exit_; ++ ++} ++ ++s32 _rtw_init_xmit_priv(struct xmit_priv *pxmitpriv, _adapter *padapter) ++{ ++ int i; ++ struct xmit_buf *pxmitbuf; ++ struct xmit_frame *pxframe; ++ sint res=_SUCCESS; ++ ++_func_enter_; ++ ++ // We don't need to memset padapter->XXX to zero, because adapter is allocated by rtw_zvmalloc(). ++ //_rtw_memset((unsigned char *)pxmitpriv, 0, sizeof(struct xmit_priv)); ++ ++ _rtw_spinlock_init(&pxmitpriv->lock); ++ _rtw_init_sema(&pxmitpriv->xmit_sema, 0); ++ _rtw_init_sema(&pxmitpriv->terminate_xmitthread_sema, 0); ++ ++ ATOMIC_SET(&pxmitpriv->HwRdyXmitData, 1); ++ ++ /* ++ Please insert all the queue initializaiton using _rtw_init_queue below ++ */ ++ ++ pxmitpriv->adapter = padapter; ++ ++ //for(i = 0 ; i < MAX_NUMBLKS; i++) ++ // _rtw_init_queue(&pxmitpriv->blk_strms[i]); ++ ++ _rtw_init_queue(&pxmitpriv->be_pending); ++ _rtw_init_queue(&pxmitpriv->bk_pending); ++ _rtw_init_queue(&pxmitpriv->vi_pending); ++ _rtw_init_queue(&pxmitpriv->vo_pending); ++ _rtw_init_queue(&pxmitpriv->bm_pending); ++ ++ //_rtw_init_queue(&pxmitpriv->legacy_dz_queue); ++ //_rtw_init_queue(&pxmitpriv->apsd_queue); ++ ++ _rtw_init_queue(&pxmitpriv->free_xmit_queue); ++ ++ ++ /* ++ Please allocate memory with the sz = (struct xmit_frame) * NR_XMITFRAME, ++ and initialize free_xmit_frame below. ++ Please also apply free_txobj to link_up all the xmit_frames... ++ */ ++ ++ pxmitpriv->pallocated_frame_buf = rtw_zvmalloc(NR_XMITFRAME * sizeof(struct xmit_frame) + 4); ++ ++ if (pxmitpriv->pallocated_frame_buf == NULL){ ++ pxmitpriv->pxmit_frame_buf =NULL; ++ RT_TRACE(_module_rtl871x_xmit_c_,_drv_err_,("alloc xmit_frame fail!\n")); ++ res= _FAIL; ++ goto exit; ++ } ++ pxmitpriv->pxmit_frame_buf = (u8 *)N_BYTE_ALIGMENT((SIZE_PTR)(pxmitpriv->pallocated_frame_buf), 4); ++ //pxmitpriv->pxmit_frame_buf = pxmitpriv->pallocated_frame_buf + 4 - ++ // ((SIZE_PTR) (pxmitpriv->pallocated_frame_buf) &3); ++ ++ pxframe = (struct xmit_frame*) pxmitpriv->pxmit_frame_buf; ++ ++ for (i = 0; i < NR_XMITFRAME; i++) ++ { ++ _rtw_init_listhead(&(pxframe->list)); ++ ++ pxframe->padapter = padapter; ++ pxframe->frame_tag = NULL_FRAMETAG; ++ ++ pxframe->pkt = NULL; ++ ++ pxframe->buf_addr = NULL; ++ pxframe->pxmitbuf = NULL; ++ ++ rtw_list_insert_tail(&(pxframe->list), &(pxmitpriv->free_xmit_queue.queue)); ++ ++ pxframe++; ++ } ++ ++ pxmitpriv->free_xmitframe_cnt = NR_XMITFRAME; ++ ++ pxmitpriv->frag_len = MAX_FRAG_THRESHOLD; ++ ++ ++ //init xmit_buf ++ _rtw_init_queue(&pxmitpriv->free_xmitbuf_queue); ++ _rtw_init_queue(&pxmitpriv->pending_xmitbuf_queue); ++ ++ pxmitpriv->pallocated_xmitbuf = rtw_zvmalloc(NR_XMITBUFF * sizeof(struct xmit_buf) + 4); ++ ++ if (pxmitpriv->pallocated_xmitbuf == NULL){ ++ RT_TRACE(_module_rtl871x_xmit_c_,_drv_err_,("alloc xmit_buf fail!\n")); ++ res= _FAIL; ++ goto exit; ++ } ++ ++ pxmitpriv->pxmitbuf = (u8 *)N_BYTE_ALIGMENT((SIZE_PTR)(pxmitpriv->pallocated_xmitbuf), 4); ++ //pxmitpriv->pxmitbuf = pxmitpriv->pallocated_xmitbuf + 4 - ++ // ((SIZE_PTR) (pxmitpriv->pallocated_xmitbuf) &3); ++ ++ pxmitbuf = (struct xmit_buf*)pxmitpriv->pxmitbuf; ++ ++ for (i = 0; i < NR_XMITBUFF; i++) ++ { ++ _rtw_init_listhead(&pxmitbuf->list); ++ ++ pxmitbuf->priv_data = NULL; ++ pxmitbuf->padapter = padapter; ++ pxmitbuf->ext_tag = _FALSE; ++ ++/* ++ pxmitbuf->pallocated_buf = rtw_zmalloc(MAX_XMITBUF_SZ + XMITBUF_ALIGN_SZ); ++ if (pxmitbuf->pallocated_buf == NULL) ++ { ++ res = _FAIL; ++ goto exit; ++ } ++ ++ pxmitbuf->pbuf = (u8 *)N_BYTE_ALIGMENT((SIZE_PTR)(pxmitbuf->pallocated_buf), XMITBUF_ALIGN_SZ); ++ //pxmitbuf->pbuf = pxmitbuf->pallocated_buf + XMITBUF_ALIGN_SZ -((SIZE_PTR) (pxmitbuf->pallocated_buf) &(XMITBUF_ALIGN_SZ-1)); ++*/ ++ ++ if((res=rtw_os_xmit_resource_alloc(padapter, pxmitbuf,(MAX_XMITBUF_SZ + XMITBUF_ALIGN_SZ))) == _FAIL) { ++ res= _FAIL; ++ goto exit; ++ } ++ ++ pxmitbuf->flags = XMIT_VO_QUEUE; ++ ++ rtw_list_insert_tail(&pxmitbuf->list, &(pxmitpriv->free_xmitbuf_queue.queue)); ++ #ifdef DBG_XMIT_BUF ++ pxmitbuf->no=i; ++ #endif ++ ++ pxmitbuf++; ++ ++ } ++ ++ pxmitpriv->free_xmitbuf_cnt = NR_XMITBUFF; ++ ++ // Init xmit extension buff ++ _rtw_init_queue(&pxmitpriv->free_xmit_extbuf_queue); ++ ++ pxmitpriv->pallocated_xmit_extbuf = rtw_zvmalloc(NR_XMIT_EXTBUFF * sizeof(struct xmit_buf) + 4); ++ ++ if (pxmitpriv->pallocated_xmit_extbuf == NULL){ ++ RT_TRACE(_module_rtl871x_xmit_c_,_drv_err_,("alloc xmit_extbuf fail!\n")); ++ res= _FAIL; ++ goto exit; ++ } ++ ++ pxmitpriv->pxmit_extbuf = (u8 *)N_BYTE_ALIGMENT((SIZE_PTR)(pxmitpriv->pallocated_xmit_extbuf), 4); ++ ++ pxmitbuf = (struct xmit_buf*)pxmitpriv->pxmit_extbuf; ++ ++ for (i = 0; i < NR_XMIT_EXTBUFF; i++) ++ { ++ _rtw_init_listhead(&pxmitbuf->list); ++ ++ pxmitbuf->priv_data = NULL; ++ pxmitbuf->padapter = padapter; ++ pxmitbuf->ext_tag = _TRUE; ++ ++/* ++ pxmitbuf->pallocated_buf = rtw_zmalloc(MAX_XMIT_EXTBUF_SZ); ++ if (pxmitbuf->pallocated_buf == NULL) ++ { ++ res = _FAIL; ++ goto exit; ++ } ++ ++ pxmitbuf->pbuf = (u8 *)N_BYTE_ALIGMENT((SIZE_PTR)(pxmitbuf->pallocated_buf), 4); ++*/ ++ ++ if((res=rtw_os_xmit_resource_alloc(padapter, pxmitbuf,MAX_XMIT_EXTBUF_SZ + XMITBUF_ALIGN_SZ)) == _FAIL) { ++ res= _FAIL; ++ goto exit; ++ } ++ ++ rtw_list_insert_tail(&pxmitbuf->list, &(pxmitpriv->free_xmit_extbuf_queue.queue)); ++ #ifdef DBG_XMIT_BUF ++ pxmitbuf->no=i; ++ #endif ++ pxmitbuf++; ++ ++ } ++ ++ pxmitpriv->free_xmit_extbuf_cnt = NR_XMIT_EXTBUFF; ++ ++ rtw_alloc_hwxmits(padapter); ++ rtw_init_hwxmits(pxmitpriv->hwxmits, pxmitpriv->hwxmit_entry); ++ ++#ifdef CONFIG_USB_HCI ++ pxmitpriv->txirp_cnt=1; ++ ++ _rtw_init_sema(&(pxmitpriv->tx_retevt), 0); ++ ++ //per AC pending irp ++ pxmitpriv->beq_cnt = 0; ++ pxmitpriv->bkq_cnt = 0; ++ pxmitpriv->viq_cnt = 0; ++ pxmitpriv->voq_cnt = 0; ++#endif ++ ++ if(padapter->HalFunc.init_xmit_priv != NULL) ++ padapter->HalFunc.init_xmit_priv(padapter); ++ ++exit: ++ ++_func_exit_; ++ ++ return res; ++} ++ ++void rtw_mfree_xmit_priv_lock (struct xmit_priv *pxmitpriv) ++{ ++ _rtw_spinlock_free(&pxmitpriv->lock); ++ _rtw_free_sema(&pxmitpriv->xmit_sema); ++ _rtw_free_sema(&pxmitpriv->terminate_xmitthread_sema); ++ ++ _rtw_spinlock_free(&pxmitpriv->be_pending.lock); ++ _rtw_spinlock_free(&pxmitpriv->bk_pending.lock); ++ _rtw_spinlock_free(&pxmitpriv->vi_pending.lock); ++ _rtw_spinlock_free(&pxmitpriv->vo_pending.lock); ++ _rtw_spinlock_free(&pxmitpriv->bm_pending.lock); ++ ++ //_rtw_spinlock_free(&pxmitpriv->legacy_dz_queue.lock); ++ //_rtw_spinlock_free(&pxmitpriv->apsd_queue.lock); ++ ++ _rtw_spinlock_free(&pxmitpriv->free_xmit_queue.lock); ++ _rtw_spinlock_free(&pxmitpriv->free_xmitbuf_queue.lock); ++ _rtw_spinlock_free(&pxmitpriv->pending_xmitbuf_queue.lock); ++} ++ ++ ++void _rtw_free_xmit_priv (struct xmit_priv *pxmitpriv) ++{ ++ int i; ++ _adapter *padapter = pxmitpriv->adapter; ++ struct xmit_frame *pxmitframe = (struct xmit_frame*) pxmitpriv->pxmit_frame_buf; ++ struct xmit_buf *pxmitbuf = (struct xmit_buf *)pxmitpriv->pxmitbuf; ++ ++ _func_enter_; ++ ++ padapter->HalFunc.free_xmit_priv(padapter); ++ ++ rtw_mfree_xmit_priv_lock(pxmitpriv); ++ ++ if(pxmitpriv->pxmit_frame_buf==NULL) ++ goto out; ++ ++ for(i=0; ipallocated_buf) ++ // rtw_mfree(pxmitbuf->pallocated_buf, MAX_XMITBUF_SZ + XMITBUF_ALIGN_SZ); ++ ++ pxmitbuf++; ++ } ++ ++ if(pxmitpriv->pallocated_frame_buf) { ++ rtw_vmfree(pxmitpriv->pallocated_frame_buf, NR_XMITFRAME * sizeof(struct xmit_frame) + 4); ++ } ++ ++ ++ if(pxmitpriv->pallocated_xmitbuf) { ++ rtw_vmfree(pxmitpriv->pallocated_xmitbuf, NR_XMITBUFF * sizeof(struct xmit_buf) + 4); ++ } ++ ++ // free xmit extension buff ++ _rtw_spinlock_free(&pxmitpriv->free_xmit_extbuf_queue.lock); ++ ++ pxmitbuf = (struct xmit_buf *)pxmitpriv->pxmit_extbuf; ++ for(i=0; ipallocated_buf) ++ // rtw_mfree(pxmitbuf->pallocated_buf, MAX_XMIT_EXTBUF_SZ); ++ ++ pxmitbuf++; ++ } ++ ++ if(pxmitpriv->pallocated_xmit_extbuf) { ++ rtw_vmfree(pxmitpriv->pallocated_xmit_extbuf, NR_XMIT_EXTBUFF * sizeof(struct xmit_buf) + 4); ++ } ++ ++ rtw_free_hwxmits(padapter); ++ ++out: ++ ++_func_exit_; ++ ++} ++ ++static void update_attrib_vcs_info(_adapter *padapter, struct xmit_frame *pxmitframe) ++{ ++ u32 sz; ++ struct pkt_attrib *pattrib = &pxmitframe->attrib; ++ struct sta_info *psta = pattrib->psta; ++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ ++ ++ if (pattrib->nr_frags != 1) ++ { ++ sz = padapter->xmitpriv.frag_len; ++ } ++ else //no frag ++ { ++ sz = pattrib->last_txcmdsz; ++ } ++ ++ // (1) RTS_Threshold is compared to the MPDU, not MSDU. ++ // (2) If there are more than one frag in this MSDU, only the first frag uses protection frame. ++ // Other fragments are protected by previous fragment. ++ // So we only need to check the length of first fragment. ++ if(pmlmeext->cur_wireless_mode < WIRELESS_11_24N || padapter->registrypriv.wifi_spec) ++ { ++ if(sz > padapter->registrypriv.rts_thresh) ++ { ++ pattrib->vcs_mode = RTS_CTS; ++ } ++ else ++ { ++ if(psta->rtsen) ++ pattrib->vcs_mode = RTS_CTS; ++ else if(psta->cts2self) ++ pattrib->vcs_mode = CTS_TO_SELF; ++ else ++ pattrib->vcs_mode = NONE_VCS; ++ } ++ } ++ else ++ { ++ while (_TRUE) ++ { ++#if 0 //Todo ++ //check IOT action ++ if(pHTInfo->IOTAction & HT_IOT_ACT_FORCED_CTS2SELF) ++ { ++ pattrib->vcs_mode = CTS_TO_SELF; ++ pattrib->rts_rate = MGN_24M; ++ break; ++ } ++ else if(pHTInfo->IOTAction & (HT_IOT_ACT_FORCED_RTS|HT_IOT_ACT_PURE_N_MODE)) ++ { ++ pattrib->vcs_mode = RTS_CTS; ++ pattrib->rts_rate = MGN_24M; ++ break; ++ } ++#endif ++ ++ //IOT action ++ if((pmlmeinfo->assoc_AP_vendor == atherosAP) && (pattrib->ampdu_en==_TRUE) && ++ (padapter->securitypriv.dot11PrivacyAlgrthm == _AES_ )) ++ { ++ pattrib->vcs_mode = CTS_TO_SELF; ++ break; ++ } ++ ++ ++ //check ERP protection ++ if(psta->rtsen || psta->cts2self) ++ { ++ if(psta->rtsen) ++ pattrib->vcs_mode = RTS_CTS; ++ else if(psta->cts2self) ++ pattrib->vcs_mode = CTS_TO_SELF; ++ ++ break; ++ } ++ ++ //check HT op mode ++ if(pattrib->ht_en) ++ { ++ u8 HTOpMode = pmlmeinfo->HT_protection; ++ if((pmlmeext->cur_bwmode && (HTOpMode == 2 || HTOpMode == 3)) || ++ (!pmlmeext->cur_bwmode && HTOpMode == 3) ) ++ { ++ pattrib->vcs_mode = RTS_CTS; ++ break; ++ } ++ } ++ ++ //check rts ++ if(sz > padapter->registrypriv.rts_thresh) ++ { ++ pattrib->vcs_mode = RTS_CTS; ++ break; ++ } ++ ++ //to do list: check MIMO power save condition. ++ ++ //check AMPDU aggregation for TXOP ++ if(pattrib->ampdu_en==_TRUE) ++ { ++ pattrib->vcs_mode = RTS_CTS; ++ break; ++ } ++ ++ pattrib->vcs_mode = NONE_VCS; ++ break; ++ } ++ } ++ if(padapter->registrypriv.intel_class_mode==1) ++ pattrib->vcs_mode = RTS_CTS; ++} ++ ++static void update_attrib_phy_info(struct pkt_attrib *pattrib, struct sta_info *psta) ++{ ++ /*if(psta->rtsen) ++ pattrib->vcs_mode = RTS_CTS; ++ else if(psta->cts2self) ++ pattrib->vcs_mode = CTS_TO_SELF; ++ else ++ pattrib->vcs_mode = NONE_VCS;*/ ++ ++ pattrib->mdata = 0; ++ pattrib->eosp = 0; ++ pattrib->triggered=0; ++ ++ //qos_en, ht_en, init rate, ,bw, ch_offset, sgi ++ pattrib->qos_en = psta->qos_option; ++ pattrib->ht_en = psta->htpriv.ht_option; ++ pattrib->raid = psta->raid; ++ pattrib->bwmode = psta->htpriv.bwmode; ++ pattrib->ch_offset = psta->htpriv.ch_offset; ++ pattrib->sgi= psta->htpriv.sgi; ++ pattrib->ampdu_en = _FALSE; ++ ++ //if(pattrib->ht_en && psta->htpriv.ampdu_enable) ++ //{ ++ // if(psta->htpriv.agg_enable_bitmap & BIT(pattrib->priority)) ++ // pattrib->ampdu_en = _TRUE; ++ //} ++ ++ ++ pattrib->retry_ctrl = _FALSE; ++ ++} ++ ++static void qos_acm(u8 acm_mask, struct pkt_attrib *pattrib) ++{ ++ switch (pattrib->priority) ++ { ++ case 0: ++ case 3: ++ if(acm_mask & BIT(1)) ++ pattrib->priority = 2; ++ break; ++ case 1: ++ case 2: ++ break; ++ case 4: ++ case 5: ++ if(acm_mask & BIT(2)) ++ pattrib->priority = 3; ++ break; ++ case 6: ++ case 7: ++ if(acm_mask & BIT(3)) ++ pattrib->priority = 5; ++ break; ++ default: ++ DBG_871X("qos_acm(): invalid pattrib->priority: %d!!!\n", pattrib->priority); ++ break; ++ } ++} ++ ++static void set_qos(struct pkt_file *ppktfile, struct pkt_attrib *pattrib) ++{ ++ struct ethhdr etherhdr; ++ struct iphdr ip_hdr; ++ s32 UserPriority = 0; ++ ++ ++ _rtw_open_pktfile(ppktfile->pkt, ppktfile); ++ _rtw_pktfile_read(ppktfile, (unsigned char*)ðerhdr, ETH_HLEN); ++ ++ // get UserPriority from IP hdr ++ if (pattrib->ether_type == 0x0800) { ++ _rtw_pktfile_read(ppktfile, (u8*)&ip_hdr, sizeof(ip_hdr)); ++// UserPriority = (ntohs(ip_hdr.tos) >> 5) & 0x3; ++ UserPriority = ip_hdr.tos >> 5; ++ } else if (pattrib->ether_type == 0x888e) { ++ // "When priority processing of data frames is supported, ++ // a STA's SME should send EAPOL-Key frames at the highest priority." ++ UserPriority = 7; ++ } ++ ++ pattrib->priority = UserPriority; ++ pattrib->hdrlen = WLAN_HDR_A3_QOS_LEN; ++ pattrib->subtype = WIFI_QOS_DATA_TYPE; ++} ++ ++static s32 update_attrib(_adapter *padapter, _pkt *pkt, struct pkt_attrib *pattrib) ++{ ++ uint i; ++ struct pkt_file pktfile; ++ struct sta_info *psta = NULL; ++ struct ethhdr etherhdr; ++ ++ sint bmcast; ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ struct security_priv *psecuritypriv = &padapter->securitypriv; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct qos_priv *pqospriv= &pmlmepriv->qospriv; ++ sint res = _SUCCESS; ++ ++ _func_enter_; ++ ++ _rtw_open_pktfile(pkt, &pktfile); ++ i = _rtw_pktfile_read(&pktfile, (u8*)ðerhdr, ETH_HLEN); ++ ++ pattrib->ether_type = ntohs(etherhdr.h_proto); ++ ++ ++ _rtw_memcpy(pattrib->dst, ðerhdr.h_dest, ETH_ALEN); ++ _rtw_memcpy(pattrib->src, ðerhdr.h_source, ETH_ALEN); ++ ++ pattrib->pctrl = 0; ++ ++ if ((check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE) || ++ (check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE)) { ++ _rtw_memcpy(pattrib->ra, pattrib->dst, ETH_ALEN); ++ _rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN); ++ } ++ else if (check_fwstate(pmlmepriv, WIFI_STATION_STATE)) { ++ _rtw_memcpy(pattrib->ra, get_bssid(pmlmepriv), ETH_ALEN); ++ _rtw_memcpy(pattrib->ta, pattrib->src, ETH_ALEN); ++ } ++ else if (check_fwstate(pmlmepriv, WIFI_AP_STATE)) { ++ _rtw_memcpy(pattrib->ra, pattrib->dst, ETH_ALEN); ++ _rtw_memcpy(pattrib->ta, get_bssid(pmlmepriv), ETH_ALEN); ++ } ++ ++ pattrib->pktlen = pktfile.pkt_len; // rtw_xmitframe_coalesce() overwirte this! ++ ++ if (ETH_P_IP == pattrib->ether_type) ++ { ++ // The following is for DHCP and ARP packet, we use cck1M to tx these packets and let LPS awake some time ++ // to prevent DHCP protocol fail ++ u8 tmp[24]; ++ _rtw_pktfile_read(&pktfile, &tmp[0], 24); ++ pattrib->dhcp_pkt = 0; ++ if (pktfile.pkt_len > 282) {//MINIMUM_DHCP_PACKET_SIZE) { ++ if (ETH_P_IP == pattrib->ether_type) {// IP header ++ if (((tmp[21] == 68) && (tmp[23] == 67)) || ++ ((tmp[21] == 67) && (tmp[23] == 68))) { ++ // 68 : UDP BOOTP client ++ // 67 : UDP BOOTP server ++ RT_TRACE(_module_rtl871x_xmit_c_,_drv_err_,("======================update_attrib: get DHCP Packet \n")); ++ // Use low rate to send DHCP packet. ++ //if(pMgntInfo->IOTAction & HT_IOT_ACT_WA_IOT_Broadcom) ++ //{ ++ // tcb_desc->DataRate = MgntQuery_TxRateExcludeCCKRates(ieee);//0xc;//ofdm 6m ++ // tcb_desc->bTxDisableRateFallBack = false; ++ //} ++ //else ++ // pTcb->DataRate = Adapter->MgntInfo.LowestBasicRate; ++ //RTPRINT(FDM, WA_IOT, ("DHCP TranslateHeader(), pTcb->DataRate = 0x%x\n", pTcb->DataRate)); ++ pattrib->dhcp_pkt = 1; ++ } ++ } ++ } ++ } ++ ++ #ifdef CONFIG_SET_SCAN_DENY_TIMER ++ if ( (pattrib->ether_type == 0x888e) || (pattrib->dhcp_pkt == 1) ) ++ { ++ rtw_set_scan_deny(pmlmepriv, 3000); ++ } ++ #endif ++ ++#ifdef CONFIG_LPS ++ // If EAPOL , ARP , OR DHCP packet, driver must be in active mode. ++ if ( (pattrib->ether_type == 0x0806) || (pattrib->ether_type == 0x888e) || (pattrib->dhcp_pkt == 1) ) ++ { ++ rtw_lps_ctrl_wk_cmd(padapter, LPS_CTRL_SPECIAL_PACKET, 1); ++ } ++#endif ++ ++ bmcast = IS_MCAST(pattrib->ra); ++ ++ // get sta_info ++ if (bmcast) { ++ psta = rtw_get_bcmc_stainfo(padapter); ++ } else { ++ psta = rtw_get_stainfo(pstapriv, pattrib->ra); ++ if (psta == NULL) { // if we cannot get psta => drrp the pkt ++ RT_TRACE(_module_rtl871x_xmit_c_, _drv_alert_, ("\nupdate_attrib => get sta_info fail, ra:" MAC_FMT"\n", MAC_ARG(pattrib->ra))); ++ #ifdef DBG_TX_DROP_FRAME ++ DBG_871X("DBG_TX_DROP_FRAME %s get sta_info fail, ra:" MAC_FMT"\n", __FUNCTION__, MAC_ARG(pattrib->ra)); ++ #endif ++ res =_FAIL; ++ goto exit; ++ } ++ else if((check_fwstate(pmlmepriv, WIFI_AP_STATE)==_TRUE)&&(!(psta->state & _FW_LINKED))) ++ { ++ res =_FAIL; ++ goto exit; ++ } ++ } ++ ++ if (psta) ++ { ++ pattrib->mac_id = psta->mac_id; ++ pattrib->psta = psta; ++ } ++ else ++ { ++ // if we cannot get psta => drop the pkt ++ RT_TRACE(_module_rtl871x_xmit_c_, _drv_alert_, ("\nupdate_attrib => get sta_info fail, ra:" MAC_FMT "\n", MAC_ARG(pattrib->ra))); ++ #ifdef DBG_TX_DROP_FRAME ++ DBG_871X("DBG_TX_DROP_FRAME %s get sta_info fail, ra:" MAC_FMT"\n", __FUNCTION__, MAC_ARG(pattrib->ra)); ++ #endif ++ res = _FAIL; ++ goto exit; ++ } ++ ++ pattrib->ack_policy = 0; ++ // get ether_hdr_len ++ pattrib->pkt_hdrlen = ETH_HLEN;//(pattrib->ether_type == 0x8100) ? (14 + 4 ): 14; //vlan tag ++ ++ pattrib->hdrlen = WLAN_HDR_A3_LEN; ++ pattrib->subtype = WIFI_DATA_TYPE; ++ pattrib->priority = 0; ++ ++ if (check_fwstate(pmlmepriv, WIFI_AP_STATE|WIFI_ADHOC_STATE|WIFI_ADHOC_MASTER_STATE)) ++ { ++ if(psta->qos_option) ++ set_qos(&pktfile, pattrib); ++ } ++ else ++ { ++ if(pqospriv->qos_option) ++ { ++ set_qos(&pktfile, pattrib); ++ if(pmlmepriv->acm_mask != 0) ++ { ++ qos_acm(pmlmepriv->acm_mask, pattrib); ++ } ++ } ++ } ++ ++ //pattrib->priority = 5; //force to used VI queue, for testing ++ ++ if (psta->ieee8021x_blocked == _TRUE) ++ { ++ RT_TRACE(_module_rtl871x_xmit_c_,_drv_err_,("\n psta->ieee8021x_blocked == _TRUE \n")); ++ ++ pattrib->encrypt = 0; ++ ++ if((pattrib->ether_type != 0x888e) && (check_fwstate(pmlmepriv, WIFI_MP_STATE) == _FALSE)) ++ { ++ RT_TRACE(_module_rtl871x_xmit_c_,_drv_err_,("\npsta->ieee8021x_blocked == _TRUE, pattrib->ether_type(%.4x) != 0x888e\n",pattrib->ether_type)); ++ #ifdef DBG_TX_DROP_FRAME ++ DBG_871X("DBG_TX_DROP_FRAME %s psta->ieee8021x_blocked == _TRUE, pattrib->ether_type(%.4x) != 0x888e\n", __FUNCTION__,pattrib->ether_type); ++ #endif ++ res = _FAIL; ++ goto exit; ++ } ++ } ++ else ++ { ++ GET_ENCRY_ALGO(psecuritypriv, psta, pattrib->encrypt, bmcast); ++ ++ switch(psecuritypriv->dot11AuthAlgrthm) ++ { ++ case dot11AuthAlgrthm_Open: ++ case dot11AuthAlgrthm_Shared: ++ case dot11AuthAlgrthm_Auto: ++ pattrib->key_idx = (u8)psecuritypriv->dot11PrivacyKeyIndex; ++ break; ++ case dot11AuthAlgrthm_8021X: ++ if(bmcast) ++ pattrib->key_idx = (u8)psecuritypriv->dot118021XGrpKeyid; ++ else ++ pattrib->key_idx = 0; ++ break; ++ default: ++ pattrib->key_idx = 0; ++ break; ++ } ++ ++ ++ } ++ ++ switch (pattrib->encrypt) ++ { ++ case _WEP40_: ++ case _WEP104_: ++ pattrib->iv_len = 4; ++ pattrib->icv_len = 4; ++ break; ++ ++ case _TKIP_: ++ pattrib->iv_len = 8; ++ pattrib->icv_len = 4; ++ ++ if(padapter->securitypriv.busetkipkey==_FAIL) ++ { ++ RT_TRACE(_module_rtl871x_xmit_c_,_drv_err_,("\npadapter->securitypriv.busetkipkey(%d)==_FAIL drop packet\n", padapter->securitypriv.busetkipkey)); ++ #ifdef DBG_TX_DROP_FRAME ++ DBG_871X("DBG_TX_DROP_FRAME %s padapter->securitypriv.busetkipkey(%d)==_FAIL drop packet\n", __FUNCTION__, padapter->securitypriv.busetkipkey); ++ #endif ++ res =_FAIL; ++ goto exit; ++ } ++ ++ break; ++ case _AES_: ++ RT_TRACE(_module_rtl871x_xmit_c_,_drv_err_,("\n pattrib->encrypt=%d (_AES_)\n",pattrib->encrypt)); ++ pattrib->iv_len = 8; ++ pattrib->icv_len = 8; ++ break; ++ ++ default: ++ pattrib->iv_len = 0; ++ pattrib->icv_len = 0; ++ break; ++ } ++ ++ RT_TRACE(_module_rtl871x_xmit_c_, _drv_info_, ++ ("update_attrib: encrypt=%d securitypriv.sw_encrypt=%d\n", ++ pattrib->encrypt, padapter->securitypriv.sw_encrypt)); ++ ++ if (pattrib->encrypt && ++ ((padapter->securitypriv.sw_encrypt == _TRUE) || (psecuritypriv->hw_decrypted == _FALSE))) ++ { ++ pattrib->bswenc = _TRUE; ++ RT_TRACE(_module_rtl871x_xmit_c_,_drv_err_, ++ ("update_attrib: encrypt=%d securitypriv.hw_decrypted=%d bswenc=_TRUE\n", ++ pattrib->encrypt, padapter->securitypriv.sw_encrypt)); ++ } else { ++ pattrib->bswenc = _FALSE; ++ RT_TRACE(_module_rtl871x_xmit_c_,_drv_info_,("update_attrib: bswenc=_FALSE\n")); ++ } ++ ++ rtw_set_tx_chksum_offload(pkt, pattrib); ++ ++ update_attrib_phy_info(pattrib, psta); ++ ++exit: ++ ++_func_exit_; ++ ++ return res; ++} ++ ++static s32 xmitframe_addmic(_adapter *padapter, struct xmit_frame *pxmitframe){ ++ sint curfragnum,length; ++ u8 *pframe, *payload,mic[8]; ++ struct mic_data micdata; ++ struct sta_info *stainfo; ++ struct qos_priv *pqospriv= &(padapter->mlmepriv.qospriv); ++ struct pkt_attrib *pattrib = &pxmitframe->attrib; ++ struct security_priv *psecuritypriv=&padapter->securitypriv; ++ struct xmit_priv *pxmitpriv=&padapter->xmitpriv; ++ u8 priority[4]={0x0,0x0,0x0,0x0}; ++ sint bmcst = IS_MCAST(pattrib->ra); ++ ++ if(pattrib->psta) ++ { ++ stainfo = pattrib->psta; ++ } ++ else ++ { ++ stainfo=rtw_get_stainfo(&padapter->stapriv ,&pattrib->ra[0]); ++ } ++ ++ ++ ++_func_enter_; ++ ++ if(pattrib->encrypt ==_TKIP_)//if(psecuritypriv->dot11PrivacyAlgrthm==_TKIP_PRIVACY_) ++ { ++ //encode mic code ++ if(stainfo!= NULL){ ++ u8 null_key[16]={0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0}; ++ ++#ifdef CONFIG_USB_TX_AGGREGATION ++ pframe = pxmitframe->buf_addr + TXDESC_SIZE + (pxmitframe->pkt_offset * PACKET_OFFSET_SZ); ++#else ++ pframe = pxmitframe->buf_addr + TXDESC_OFFSET; ++#endif ++ ++ if(bmcst) ++ { ++ if(_rtw_memcmp(psecuritypriv->dot118021XGrptxmickey[psecuritypriv->dot118021XGrpKeyid].skey, null_key, 16)==_TRUE){ ++ //DbgPrint("\nxmitframe_addmic:stainfo->dot11tkiptxmickey==0\n"); ++ //rtw_msleep_os(10); ++ return _FAIL; ++ } ++ //start to calculate the mic code ++ rtw_secmicsetkey(&micdata, psecuritypriv->dot118021XGrptxmickey[psecuritypriv->dot118021XGrpKeyid].skey); ++ } ++ else ++ { ++ if(_rtw_memcmp(&stainfo->dot11tkiptxmickey.skey[0],null_key, 16)==_TRUE){ ++ //DbgPrint("\nxmitframe_addmic:stainfo->dot11tkiptxmickey==0\n"); ++ //rtw_msleep_os(10); ++ return _FAIL; ++ } ++ //start to calculate the mic code ++ rtw_secmicsetkey(&micdata, &stainfo->dot11tkiptxmickey.skey[0]); ++ } ++ ++ if(pframe[1]&1){ //ToDS==1 ++ rtw_secmicappend(&micdata, &pframe[16], 6); //DA ++ if(pframe[1]&2) //From Ds==1 ++ rtw_secmicappend(&micdata, &pframe[24], 6); ++ else ++ rtw_secmicappend(&micdata, &pframe[10], 6); ++ } ++ else{ //ToDS==0 ++ rtw_secmicappend(&micdata, &pframe[4], 6); //DA ++ if(pframe[1]&2) //From Ds==1 ++ rtw_secmicappend(&micdata, &pframe[16], 6); ++ else ++ rtw_secmicappend(&micdata, &pframe[10], 6); ++ ++ } ++ ++ //if(pqospriv->qos_option==1) ++ if(pattrib->qos_en) ++ priority[0]=(u8)pxmitframe->attrib.priority; ++ ++ ++ rtw_secmicappend(&micdata, &priority[0], 4); ++ ++ payload=pframe; ++ ++ for(curfragnum=0;curfragnumnr_frags;curfragnum++){ ++ payload=(u8 *)RND4((SIZE_PTR)(payload)); ++ RT_TRACE(_module_rtl871x_xmit_c_,_drv_err_,("===curfragnum=%d, pframe= 0x%.2x, 0x%.2x, 0x%.2x, 0x%.2x, 0x%.2x, 0x%.2x, 0x%.2x, 0x%.2x,!!!\n", ++ curfragnum,*payload, *(payload+1),*(payload+2),*(payload+3),*(payload+4),*(payload+5),*(payload+6),*(payload+7))); ++ ++ payload=payload+pattrib->hdrlen+pattrib->iv_len; ++ RT_TRACE(_module_rtl871x_xmit_c_,_drv_err_,("curfragnum=%d pattrib->hdrlen=%d pattrib->iv_len=%d",curfragnum,pattrib->hdrlen,pattrib->iv_len)); ++ if((curfragnum+1)==pattrib->nr_frags){ ++ length=pattrib->last_txcmdsz-pattrib->hdrlen-pattrib->iv_len-( (pattrib->bswenc) ? pattrib->icv_len : 0); ++ rtw_secmicappend(&micdata, payload,length); ++ payload=payload+length; ++ } ++ else{ ++ length=pxmitpriv->frag_len-pattrib->hdrlen-pattrib->iv_len-( (pattrib->bswenc) ? pattrib->icv_len : 0); ++ rtw_secmicappend(&micdata, payload, length); ++ payload=payload+length+pattrib->icv_len; ++ RT_TRACE(_module_rtl871x_xmit_c_,_drv_err_,("curfragnum=%d length=%d pattrib->icv_len=%d",curfragnum,length,pattrib->icv_len)); ++ } ++ } ++ rtw_secgetmic(&micdata,&(mic[0])); ++ RT_TRACE(_module_rtl871x_xmit_c_,_drv_err_,("xmitframe_addmic: before add mic code!!!\n")); ++ RT_TRACE(_module_rtl871x_xmit_c_,_drv_err_,("xmitframe_addmic: pattrib->last_txcmdsz=%d!!!\n",pattrib->last_txcmdsz)); ++ RT_TRACE(_module_rtl871x_xmit_c_,_drv_err_,("xmitframe_addmic: mic[0]=0x%.2x ,mic[1]=0x%.2x ,mic[2]=0x%.2x ,mic[3]=0x%.2x \n\ ++ mic[4]=0x%.2x ,mic[5]=0x%.2x ,mic[6]=0x%.2x ,mic[7]=0x%.2x !!!!\n", ++ mic[0],mic[1],mic[2],mic[3],mic[4],mic[5],mic[6],mic[7])); ++ //add mic code and add the mic code length in last_txcmdsz ++ ++ _rtw_memcpy(payload, &(mic[0]),8); ++ pattrib->last_txcmdsz+=8; ++ ++ RT_TRACE(_module_rtl871x_xmit_c_,_drv_info_,("\n ========last pkt========\n")); ++ payload=payload-pattrib->last_txcmdsz+8; ++ for(curfragnum=0;curfragnumlast_txcmdsz;curfragnum=curfragnum+8) ++ RT_TRACE(_module_rtl871x_xmit_c_,_drv_info_,(" %.2x, %.2x, %.2x, %.2x, %.2x, %.2x, %.2x, %.2x ", ++ *(payload+curfragnum), *(payload+curfragnum+1), *(payload+curfragnum+2),*(payload+curfragnum+3), ++ *(payload+curfragnum+4),*(payload+curfragnum+5),*(payload+curfragnum+6),*(payload+curfragnum+7))); ++ } ++ else{ ++ RT_TRACE(_module_rtl871x_xmit_c_,_drv_err_,("xmitframe_addmic: rtw_get_stainfo==NULL!!!\n")); ++ } ++ } ++ ++_func_exit_; ++ ++ return _SUCCESS; ++} ++ ++static s32 xmitframe_swencrypt(_adapter *padapter, struct xmit_frame *pxmitframe){ ++ ++ struct pkt_attrib *pattrib = &pxmitframe->attrib; ++ //struct security_priv *psecuritypriv=&padapter->securitypriv; ++ ++_func_enter_; ++ ++ //if((psecuritypriv->sw_encrypt)||(pattrib->bswenc)) ++ if(pattrib->bswenc) ++ { ++ //DBG_8192C("start xmitframe_swencrypt\n"); ++ RT_TRACE(_module_rtl871x_xmit_c_,_drv_alert_,("### xmitframe_swencrypt\n")); ++ switch(pattrib->encrypt){ ++ case _WEP40_: ++ case _WEP104_: ++ rtw_wep_encrypt(padapter, (u8 *)pxmitframe); ++ break; ++ case _TKIP_: ++ rtw_tkip_encrypt(padapter, (u8 *)pxmitframe); ++ break; ++ case _AES_: ++ rtw_aes_encrypt(padapter, (u8 * )pxmitframe); ++ break; ++ default: ++ break; ++ } ++ ++ } else { ++ RT_TRACE(_module_rtl871x_xmit_c_,_drv_notice_,("### xmitframe_hwencrypt\n")); ++ } ++ ++_func_exit_; ++ ++ return _SUCCESS; ++} ++ ++s32 rtw_make_wlanhdr (_adapter *padapter , u8 *hdr, struct pkt_attrib *pattrib) ++{ ++ u16 *qc; ++ ++ struct rtw_ieee80211_hdr *pwlanhdr = (struct rtw_ieee80211_hdr *)hdr; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct qos_priv *pqospriv = &pmlmepriv->qospriv; ++ u8 qos_option = _FALSE; ++#ifdef CONFIG_TDLS ++ struct tdls_info *ptdlsinfo = &padapter->tdlsinfo; ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ struct sta_info *ptdls_sta=NULL; ++ u8 tdls_seq=0; ++#endif ++ ++//#ifdef CONFIG_PWRCTRL ++// struct pwrctrl_priv *pwrpriv = &(padapter->pwrctrlpriv); ++//#endif ++ ++ sint res = _SUCCESS; ++ u16 *fctrl = &pwlanhdr->frame_ctl; ++ ++ struct sta_info *psta; ++ ++ sint bmcst = IS_MCAST(pattrib->ra); ++ ++_func_enter_; ++ ++ if (pattrib->psta) { ++ psta = pattrib->psta; ++ } else { ++ if(bmcst) { ++ psta = rtw_get_bcmc_stainfo(padapter); ++ } else { ++ psta = rtw_get_stainfo(&padapter->stapriv, pattrib->ra); ++ } ++ } ++ ++ _rtw_memset(hdr, 0, WLANHDR_OFFSET); ++ ++ SetFrameSubType(fctrl, pattrib->subtype); ++ ++ if (pattrib->subtype & WIFI_DATA_TYPE) ++ { ++ if ((check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE)) { ++ //to_ds = 1, fr_ds = 0; ++#ifdef CONFIG_TDLS ++ if((ptdlsinfo->setup_state==TDLS_LINKED_STATE)){ ++ ptdls_sta = rtw_get_stainfo(pstapriv, pattrib->dst); ++ if((ptdls_sta!=NULL)&&((ptdls_sta->tdls_sta_state & TDLS_LINKED_STATE)==TDLS_LINKED_STATE)&&(pattrib->ether_type!=0x0806)){ ++ //TDLS data transfer, ToDS=0, FrDs=0 ++ _rtw_memcpy(pwlanhdr->addr1, pattrib->dst, ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr2, pattrib->src, ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr3, get_bssid(pmlmepriv), ETH_ALEN); ++ tdls_seq=1; ++ }else{ ++ // 1.usual data transfer ++ // 2.Arp pkt will relayed by AP ++ SetToDs(fctrl); ++ _rtw_memcpy(pwlanhdr->addr1, get_bssid(pmlmepriv), ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr2, pattrib->src, ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr3, pattrib->dst, ETH_ALEN); ++ } ++ }else ++#endif ++ { ++ //usual data transfer ++ SetToDs(fctrl); ++ _rtw_memcpy(pwlanhdr->addr1, get_bssid(pmlmepriv), ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr2, pattrib->src, ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr3, pattrib->dst, ETH_ALEN); ++ } ++ ++ if (pqospriv->qos_option) ++ qos_option = _TRUE; ++ ++ } ++ else if ((check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) ) { ++ //to_ds = 0, fr_ds = 1; ++ SetFrDs(fctrl); ++ _rtw_memcpy(pwlanhdr->addr1, pattrib->dst, ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr2, get_bssid(pmlmepriv), ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr3, pattrib->src, ETH_ALEN); ++ ++ if(psta->qos_option) ++ qos_option = _TRUE; ++ } ++ else if ((check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE) || ++ (check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE)) { ++ _rtw_memcpy(pwlanhdr->addr1, pattrib->dst, ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr2, pattrib->src, ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr3, get_bssid(pmlmepriv), ETH_ALEN); ++ ++ if(psta->qos_option) ++ qos_option = _TRUE; ++ } ++ else { ++ RT_TRACE(_module_rtl871x_xmit_c_,_drv_err_,("fw_state:%x is not allowed to xmit frame\n", get_fwstate(pmlmepriv))); ++ res = _FAIL; ++ goto exit; ++ } ++ ++/*#ifdef CONFIG_PWRCTRL ++ if (pwrpriv->cpwm >= FW_PWR1 && !(padapter->mlmepriv.sitesurveyctrl.traffic_busy)) ++ SetPwrMgt(fctrl); ++#else ++ if ((get_fwstate(pmlmepriv)) & WIFI_SLEEP_STATE) ++ SetPwrMgt(fctrl); ++#endif*/ ++ ++ if(pattrib->mdata) ++ SetMData(fctrl); ++ ++ if (pattrib->encrypt) ++ SetPrivacy(fctrl); ++ ++ if (qos_option) ++ { ++ qc = (unsigned short *)(hdr + pattrib->hdrlen - 2); ++ ++ if (pattrib->priority) ++ SetPriority(qc, pattrib->priority); ++ ++ SetEOSP(qc, pattrib->eosp); ++ ++ SetAckpolicy(qc, pattrib->ack_policy); ++ } ++ ++ //TODO: fill HT Control Field ++ ++ //Update Seq Num will be handled by f/w ++ { ++ ++#ifdef CONFIG_TDLS ++ // 1. update seq_num per link by sta_info ++ // 2. rewrite encrypt to _AES_, also rewrite iv_len, icv_len ++ if(tdls_seq==1){ ++ ptdls_sta->sta_xmitpriv.txseq_tid[pattrib->priority]++; ++ ptdls_sta->sta_xmitpriv.txseq_tid[pattrib->priority] &= 0xFFF; ++ ++ pattrib->seqnum = ptdls_sta->sta_xmitpriv.txseq_tid[pattrib->priority]; ++ ++ SetSeqNum(hdr, pattrib->seqnum); ++ ++ if (pattrib->encrypt){ ++ pattrib->encrypt= _AES_; ++ pattrib->iv_len=8; ++ pattrib->icv_len=8; ++ } ++ }else ++#endif ++ if(psta){ ++ psta->sta_xmitpriv.txseq_tid[pattrib->priority]++; ++ psta->sta_xmitpriv.txseq_tid[pattrib->priority] &= 0xFFF; ++ ++ pattrib->seqnum = psta->sta_xmitpriv.txseq_tid[pattrib->priority]; ++ ++ SetSeqNum(hdr, pattrib->seqnum); ++ ++ ++ //check if enable ampdu ++ if(pattrib->ht_en && psta->htpriv.ampdu_enable) ++ { ++ if(psta->htpriv.agg_enable_bitmap & BIT(pattrib->priority)) ++ pattrib->ampdu_en = _TRUE; ++ } ++ ++ //re-check if enable ampdu by BA_starting_seqctrl ++ if(pattrib->ampdu_en == _TRUE) ++ { ++ u16 tx_seq; ++ ++ tx_seq = psta->BA_starting_seqctrl[pattrib->priority & 0x0f]; ++ ++ //check BA_starting_seqctrl ++ if(SN_LESS(pattrib->seqnum, tx_seq)) ++ { ++ //DBG_871X("tx ampdu seqnum(%d) < tx_seq(%d)\n", pattrib->seqnum, tx_seq); ++ pattrib->ampdu_en = _FALSE;//AGG BK ++ } ++ else if(SN_EQUAL(pattrib->seqnum, tx_seq)) ++ { ++ psta->BA_starting_seqctrl[pattrib->priority & 0x0f] = (tx_seq+1)&0xfff; ++ ++ pattrib->ampdu_en = _TRUE;//AGG EN ++ } ++ else ++ { ++ //DBG_871X("tx ampdu over run\n"); ++ psta->BA_starting_seqctrl[pattrib->priority & 0x0f] = (pattrib->seqnum+1)&0xfff; ++ pattrib->ampdu_en = _TRUE;//AGG EN ++ } ++ ++ } ++ ++ } ++ } ++ ++ } ++ else ++ { ++ ++ } ++ ++exit: ++ ++_func_exit_; ++ ++ return res; ++} ++ ++s32 rtw_txframes_pending(_adapter *padapter) ++{ ++ struct xmit_priv *pxmitpriv = &padapter->xmitpriv; ++ ++ return ((_rtw_queue_empty(&pxmitpriv->be_pending) == _FALSE) || ++ (_rtw_queue_empty(&pxmitpriv->bk_pending) == _FALSE) || ++ (_rtw_queue_empty(&pxmitpriv->vi_pending) == _FALSE) || ++ (_rtw_queue_empty(&pxmitpriv->vo_pending) == _FALSE)); ++} ++ ++s32 rtw_txframes_sta_ac_pending(_adapter *padapter, struct pkt_attrib *pattrib) ++{ ++ struct sta_info *psta; ++ struct tx_servq *ptxservq; ++ int priority = pattrib->priority; ++ ++ psta = pattrib->psta; ++ ++ switch(priority) ++ { ++ case 1: ++ case 2: ++ ptxservq = &(psta->sta_xmitpriv.bk_q); ++ break; ++ case 4: ++ case 5: ++ ptxservq = &(psta->sta_xmitpriv.vi_q); ++ break; ++ case 6: ++ case 7: ++ ptxservq = &(psta->sta_xmitpriv.vo_q); ++ break; ++ case 0: ++ case 3: ++ default: ++ ptxservq = &(psta->sta_xmitpriv.be_q); ++ break; ++ ++ } ++ ++ return ptxservq->qcnt; ++} ++ ++#ifdef CONFIG_TDLS ++void rtw_tdls_setup_req_fr(_adapter * padapter, struct xmit_frame * pxmitframe, u8 *pframe) ++{ ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info; ++ struct pkt_attrib *pattrib = &pxmitframe->attrib; ++ struct registry_priv *pregistrypriv = &padapter->registrypriv; ++ struct rtw_ieee80211_ht_cap ht_capie; ++ struct sta_info *ptdls_sta=rtw_get_stainfo( (&padapter->stapriv) , pattrib->dst); ++ ++ u8 payload_type = 0x02; ++ u8 category = RTW_WLAN_CATEGORY_TDLS; ++ u8 action = TDLS_SETUP_REQUEST; ++ u8 bssrate[NDIS_802_11_LENGTH_RATES_EX]; //Use NDIS_802_11_LENGTH_RATES_EX in order to call func.rtw_set_supported_rate ++ int bssrate_len = 0, i = 0 ; ++ u8 more_supportedrates = 0; ++ unsigned int ie_len; ++ u8 *p; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ u8 link_id_addr[18] = {0}; ++ u8 iedata=0; ++ u8 sup_ch[ 30 * 2 ] = {0x00 }, sup_ch_idx = 0, idx_5g = 2; //For supported channel ++ u8 timeout_itvl[5]; //set timeout interval to maximum value ++ u32 time; ++ ++ //SNonce ++ if(pattrib->encrypt){ ++ for(i=0;i<8;i++){ ++ time=rtw_get_current_time(); ++ _rtw_memcpy(&ptdls_sta->SNonce[4*i], (u8 *)&time, 4); ++ } ++ } ++ ++ //payload type ++ pframe = rtw_set_fixed_ie(pframe, 1, &(payload_type), &(pattrib->pktlen)); ++ //category, action, dialog token ++ pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen)); ++ pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen)); ++ pframe = rtw_set_fixed_ie(pframe, 1, &(ptdls_sta->dialog), &(pattrib->pktlen)); ++ ++ //capability ++ _rtw_memcpy(pframe, rtw_get_capability_from_ie(pmlmeinfo->network.IEs), 2); ++ ++ if(pattrib->encrypt) ++ *pframe =*pframe | BIT(4); ++ pframe += 2; ++ pattrib->pktlen += 2; ++ ++ //supported rates ++ rtw_set_supported_rate(bssrate, WIRELESS_11BG_24N); ++ bssrate_len = IEEE80211_CCK_RATE_LEN + IEEE80211_NUM_OFDM_RATESLEN; ++ //for (bssrate_len = 0; bssrate_len < NumRates; bssrate_len++) { ++ // if (pregistrypriv->dev_network.SupportedRates[bssrate_len]== 0) break; ++ // bssrate[bssrate_len] = pregistrypriv->dev_network.SupportedRates[bssrate_len]; ++ //} ++ ++ if (bssrate_len > 8) ++ { ++ pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_ , 8, bssrate, &(pattrib->pktlen)); ++ more_supportedrates = 1; ++ } ++ else ++ { ++ pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_ , bssrate_len , bssrate, &(pattrib->pktlen)); ++ } ++ ++ //country(optional) ++ //extended supported rates ++ if(more_supportedrates==1){ ++ pframe = rtw_set_ie(pframe, _EXT_SUPPORTEDRATES_IE_ , (bssrate_len - 8), (bssrate + 8), &(pattrib->pktlen)); ++ } ++ ++ //supported channels ++ do{ ++ if( pmlmeext->channel_set[sup_ch_idx].ChannelNum == 11 ) ++ { ++ sup_ch[0] = 1; //First channel number ++ sup_ch[1] = pmlmeext->channel_set[sup_ch_idx].ChannelNum; //Number of channel ++ } ++ else if( pmlmeext->channel_set[sup_ch_idx].ChannelNum == 13 ) ++ { ++ sup_ch[0] = 1; ++ sup_ch[1] = pmlmeext->channel_set[sup_ch_idx].ChannelNum;; ++ } ++ else if( pmlmeext->channel_set[sup_ch_idx].ChannelNum > 13 ) ++ { ++ sup_ch[idx_5g++] = pmlmeext->channel_set[sup_ch_idx].ChannelNum; ++ sup_ch[idx_5g++] = 1; ++ } ++ ++ sup_ch_idx++; ++ } ++ while( pmlmeext->channel_set[sup_ch_idx].ChannelNum != 0 ); ++ pframe = rtw_set_ie(pframe, _SUPPORTED_CH_IE_, idx_5g + 2, sup_ch, &(pattrib->pktlen)); ++ ++ //RSNIE ++ if(pattrib->encrypt) ++ pframe = rtw_set_ie(pframe, _RSN_IE_2_, 20, TDLS_RSNIE, &(pattrib->pktlen)); ++ ++ //extended capabilities ++ pframe = rtw_set_ie(pframe, _EXT_CAP_IE_ , 5, TDLS_EXT_CAPIE, &(pattrib->pktlen)); ++ ++ //QoS capability(WMM_IE) ++ pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, 7, TDLS_WMMIE, &(pattrib->pktlen)); ++ ++ //FTIE(optional) ++ if(pattrib->encrypt){ ++ _rtw_memset(pframe, 0, 84); //All fields except SNonce shall be set to 0 ++ _rtw_memset(pframe, _FTIE_, 1); //version ++ _rtw_memset((pframe+1), 82, 1); //length ++ _rtw_memcpy((pframe+52), ptdls_sta->SNonce, 32); ++ pframe += 84; ++ pattrib->pktlen += 84; ++ ++ //Timeout interval ++ timeout_itvl[0]=0x02; ++ _rtw_memcpy(timeout_itvl+1, (u8 *)(&ptdls_sta->TDLS_PeerKey_Lifetime), 4); ++ pframe = rtw_set_ie(pframe, _TIMEOUT_ITVL_IE_, 5, timeout_itvl, &(pattrib->pktlen)); ++ ++ } ++ ++ //Sup_reg_classes(optional) ++ //HT capabilities ++ _rtw_memset(&ht_capie, 0, sizeof(struct rtw_ieee80211_ht_cap)); ++ ++ ht_capie.cap_info = IEEE80211_HT_CAP_SUP_WIDTH |IEEE80211_HT_CAP_SGI_20 |IEEE80211_HT_CAP_SM_PS | ++ IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_TX_STBC |IEEE80211_HT_CAP_DSSSCCK40; ++ ++ { ++ u32 rx_packet_offset, max_recvbuf_sz; ++ padapter->HalFunc.GetHalDefVarHandler(padapter, HAL_DEF_RX_PACKET_OFFSET, &rx_packet_offset); ++ padapter->HalFunc.GetHalDefVarHandler(padapter, HAL_DEF_MAX_RECVBUF_SZ, &max_recvbuf_sz); ++ if(max_recvbuf_sz-rx_packet_offset>(8191-256)) ++ ht_capie.cap_info = ht_capie.cap_info |IEEE80211_HT_CAP_MAX_AMSDU; ++ } ++ ++ ht_capie.ampdu_params_info = (IEEE80211_HT_CAP_AMPDU_FACTOR&0x03); ++ ++ switch(pHalData->rf_type) ++ { ++ case RF_1T1R: ++ ht_capie.cap_info |= 0x0100;//RX STBC One spatial stream ++ _rtw_memcpy(ht_capie.supp_mcs_set, MCS_rate_1R, 16); ++ break; ++ ++ case RF_2T2R: ++ case RF_1T2R: ++ default: ++ ht_capie.cap_info|= 0x0200;//RX STBC two spatial stream ++ _rtw_memcpy(ht_capie.supp_mcs_set, MCS_rate_2R, 16); ++ break; ++ } ++ ++ pframe = rtw_set_ie(pframe, _HT_CAPABILITY_IE_, ++ sizeof(struct rtw_ieee80211_ht_cap), (unsigned char*)&ht_capie, &(pattrib->pktlen)); ++ ++ //20/40 BSS coexistence ++ if(pmlmepriv->num_FortyMHzIntolerant>0) ++ iedata |= BIT(2);//20 MHz BSS Width Request ++ pframe = rtw_set_ie(pframe, EID_BSSCoexistence, 1, &iedata, &(pattrib->pktlen)); ++ ++ //Link identifier ++ _rtw_memcpy(link_id_addr, pattrib->ra, 6); ++ _rtw_memcpy((link_id_addr+6), pattrib->src, 6); ++ _rtw_memcpy((link_id_addr+12), pattrib->dst, 6); ++ pframe = rtw_set_ie(pframe, _LINK_ID_IE_, 18, link_id_addr, &(pattrib->pktlen)); ++ ++} ++ ++void rtw_tdls_setup_rsp_fr(_adapter * padapter, struct xmit_frame * pxmitframe, u8 *pframe) ++{ ++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ struct pkt_attrib *pattrib = &pxmitframe->attrib; ++ struct sta_info *ptdls_sta; ++ struct registry_priv *pregistrypriv = &padapter->registrypriv; ++ struct rtw_ieee80211_ht_cap ht_capie; ++ ++ u8 payload_type = 0x02; ++ unsigned char category = RTW_WLAN_CATEGORY_TDLS; ++ unsigned char action = TDLS_SETUP_RESPONSE; ++ unsigned char bssrate[NDIS_802_11_LENGTH_RATES_EX]; ++ int bssrate_len = 0; ++ u8 more_supportedrates = 0; ++ unsigned int ie_len; ++ unsigned char *p; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ u8 link_id_addr[18] = {0}; ++ u8 sup_ch[ 30 * 2 ] = { 0x00 }, sup_ch_idx = 0, idx_5g = 2; //For supported channel ++ u8 iedata=0; ++ u8 timeout_itvl[5]; //setup response timeout interval will copy from request ++ u8 ANonce[32]; //maybe it can put in ontdls_req ++ u8 k; //for random ANonce ++ u8 *pftie, *ptimeout_ie, *plinkid_ie, *prsnie, *pftie_mic; ++ u32 time; ++ ++ ptdls_sta = rtw_get_stainfo( &(padapter->stapriv) , pattrib->dst); ++ ++ if(ptdls_sta == NULL ) ++ { ++ DBG_8192C("[%s] %d\n", __FUNCTION__, __LINE__); ++ } ++ else ++ DBG_8192C("stat_code:%04x \n", ptdls_sta->stat_code); ++ ++ if(pattrib->encrypt){ ++ for(k=0;k<8;k++){ ++ time=rtw_get_current_time(); ++ _rtw_memcpy(&ptdls_sta->ANonce[4*k], (u8*)&time, 4); ++ } ++ } ++ ++ //payload type ++ pframe = rtw_set_fixed_ie(pframe, 1, &(payload_type), &(pattrib->pktlen)); ++ //category, action, status code ++ pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen)); ++ pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen)); ++ pframe = rtw_set_fixed_ie(pframe, 2, (u8 *)&ptdls_sta->stat_code, &(pattrib->pktlen)); ++ ++ if(ptdls_sta->stat_code!=0) //invalid setup request ++ return; ++ ++ //dialog token ++ pframe = rtw_set_fixed_ie(pframe, 1, &(ptdls_sta->dialog), &(pattrib->pktlen)); ++ ++ //capability ++ _rtw_memcpy(pframe, rtw_get_capability_from_ie(pmlmeinfo->network.IEs), 2); ++ ++ if(pattrib->encrypt ) ++ *pframe =*pframe | BIT(4); ++ pframe += 2; ++ pattrib->pktlen += 2; ++ ++ //supported rates ++ rtw_set_supported_rate(bssrate, WIRELESS_11BG_24N); ++ bssrate_len = IEEE80211_CCK_RATE_LEN + IEEE80211_NUM_OFDM_RATESLEN; ++ //for (bssrate_len = 0; bssrate_len < NumRates; bssrate_len++) { ++ // if (pregistrypriv->dev_network.SupportedRates[bssrate_len]== 0) break; ++ // bssrate[bssrate_len] = pregistrypriv->dev_network.SupportedRates[bssrate_len]; ++ //} ++ ++ if (bssrate_len > 8) ++ { ++ pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_ , 8, bssrate, &(pattrib->pktlen)); ++ more_supportedrates = 1; ++ } ++ else ++ { ++ pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_ , bssrate_len , bssrate, &(pattrib->pktlen)); ++ } ++ ++ //country(optional) ++ //extended supported rates ++ if(more_supportedrates==1){ ++ pframe = rtw_set_ie(pframe, _EXT_SUPPORTEDRATES_IE_ , (bssrate_len - 8), (bssrate + 8), &(pattrib->pktlen)); ++ } ++ ++ //supported channels ++ do{ ++ if( pmlmeext->channel_set[sup_ch_idx].ChannelNum == 11 ) ++ { ++ sup_ch[0] = 1; //First channel number ++ sup_ch[1] = pmlmeext->channel_set[sup_ch_idx].ChannelNum;; //Number of channel ++ } ++ else if( pmlmeext->channel_set[sup_ch_idx].ChannelNum == 13 ) ++ { ++ sup_ch[0] = 1; ++ sup_ch[1] = pmlmeext->channel_set[sup_ch_idx].ChannelNum;; ++ } ++ else if( pmlmeext->channel_set[sup_ch_idx].ChannelNum > 13 ) ++ { ++ sup_ch[idx_5g++] = pmlmeext->channel_set[sup_ch_idx].ChannelNum; ++ sup_ch[idx_5g++] = 1; ++ } ++ ++ sup_ch_idx++; ++ } ++ while( pmlmeext->channel_set[sup_ch_idx].ChannelNum != 0 ); ++ pframe = rtw_set_ie(pframe, _SUPPORTED_CH_IE_, idx_5g + 2, sup_ch, &(pattrib->pktlen)); ++ ++ //RSNIE ++ if(pattrib->encrypt){ ++ prsnie = pframe; ++ pframe = rtw_set_ie(pframe, _RSN_IE_2_, 20, TDLS_RSNIE, &(pattrib->pktlen)); ++ } ++ ++ //extended capabilities ++ pframe = rtw_set_ie(pframe, _EXT_CAP_IE_ , 5, TDLS_EXT_CAPIE, &(pattrib->pktlen)); ++ ++ //QoS capability(WMM_IE) ++ pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, 7, TDLS_WMMIE, &(pattrib->pktlen)); ++ ++ //FTIE(optional) ++ if(pattrib->encrypt){ ++ wpa_tdls_generate_tpk(padapter, ptdls_sta); ++ ++ pftie = pframe; ++ pftie_mic = pframe+4; ++ _rtw_memset(pframe, 0, 84); //All fields except SNonce shall be set to 0 ++ _rtw_memset(pframe, _FTIE_, 1); //version ++ _rtw_memset((pframe+1), 82, 1); //length ++ _rtw_memcpy((pframe+20), ptdls_sta->ANonce, 32); ++ _rtw_memcpy((pframe+52), ptdls_sta->SNonce, 32); ++ pframe += 84; ++ pattrib->pktlen += 84; ++ ++ //Timeout interval ++ ptimeout_ie = pframe; ++ timeout_itvl[0]=0x02; ++ _rtw_memcpy(timeout_itvl+1, (u8 *)(&ptdls_sta->TDLS_PeerKey_Lifetime), 4); ++ pframe = rtw_set_ie(pframe, _TIMEOUT_ITVL_IE_, 5, timeout_itvl, &(pattrib->pktlen)); ++ } ++ ++ //Sup_reg_classes(optional) ++ //HT capabilities ++ _rtw_memset(&ht_capie, 0, sizeof(struct rtw_ieee80211_ht_cap)); ++ ++ ht_capie.cap_info = IEEE80211_HT_CAP_SUP_WIDTH |IEEE80211_HT_CAP_SGI_20 |IEEE80211_HT_CAP_SM_PS | ++ IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_TX_STBC |IEEE80211_HT_CAP_DSSSCCK40; ++ ++ { ++ u32 rx_packet_offset, max_recvbuf_sz; ++ padapter->HalFunc.GetHalDefVarHandler(padapter, HAL_DEF_RX_PACKET_OFFSET, &rx_packet_offset); ++ padapter->HalFunc.GetHalDefVarHandler(padapter, HAL_DEF_MAX_RECVBUF_SZ, &max_recvbuf_sz); ++ if(max_recvbuf_sz-rx_packet_offset>(8191-256)) ++ ht_capie.cap_info = ht_capie.cap_info |IEEE80211_HT_CAP_MAX_AMSDU; ++ } ++ ++ ht_capie.ampdu_params_info = (IEEE80211_HT_CAP_AMPDU_FACTOR&0x03); ++ ++ switch(pHalData->rf_type) ++ { ++ case RF_1T1R: ++ ht_capie.cap_info |= 0x0100;//RX STBC One spatial stream ++ _rtw_memcpy(ht_capie.supp_mcs_set, MCS_rate_1R, 16); ++ break; ++ ++ case RF_2T2R: ++ case RF_1T2R: ++ default: ++ ht_capie.cap_info|= 0x0200;//RX STBC two spatial stream ++ _rtw_memcpy(ht_capie.supp_mcs_set, MCS_rate_2R, 16); ++ break; ++ } ++ ++ pframe = rtw_set_ie(pframe, _HT_CAPABILITY_IE_, ++ sizeof(struct rtw_ieee80211_ht_cap), (unsigned char*)&ht_capie, &(pattrib->pktlen)); ++ ++ //20/40 BSS coexistence ++ if(pmlmepriv->num_FortyMHzIntolerant>0) ++ iedata |= BIT(2);//20 MHz BSS Width Request ++ pframe = rtw_set_ie(pframe, EID_BSSCoexistence, 1, &iedata, &(pattrib->pktlen)); ++ ++ //Link identifier ++ plinkid_ie = pframe; ++ _rtw_memcpy(link_id_addr, pattrib->ra, 6); ++ _rtw_memcpy((link_id_addr+6), pattrib->dst, 6); ++ _rtw_memcpy((link_id_addr+12), pattrib->src, 6); ++ pframe = rtw_set_ie(pframe, _LINK_ID_IE_, 18, link_id_addr, &(pattrib->pktlen)); ++ ++ //fill ftie mic ++ if(pattrib->encrypt) ++ wpa_tdls_ftie_mic(ptdls_sta->tpk.kck, 2, plinkid_ie, prsnie, ptimeout_ie, pftie, pftie_mic); ++ ++} ++ ++void rtw_tdls_setup_cfm_fr(_adapter * padapter, struct xmit_frame * pxmitframe, u8 *pframe) ++{ ++ ++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ struct pkt_attrib *pattrib = &pxmitframe->attrib; ++ struct sta_info *ptdls_sta=rtw_get_stainfo( (&padapter->stapriv) , pattrib->dst); ++ ++ u8 payload_type = 0x02; ++ unsigned char category = RTW_WLAN_CATEGORY_TDLS; ++ unsigned char action = TDLS_SETUP_CONFIRM; ++ u8 more_supportedrates = 0; ++ unsigned int ie_len; ++ unsigned char *p; ++ u8 timeout_itvl[5]; //set timeout interval to maximum value ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ u8 link_id_addr[18] = {0}; ++ u8 *pftie, *ptimeout_ie, *plinkid_ie, *prsnie, *pftie_mic; ++ ++ //payload type ++ pframe = rtw_set_fixed_ie(pframe, 1, &(payload_type), &(pattrib->pktlen)); ++ //category, action, status code, dialog token ++ pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen)); ++ pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen)); ++ pframe = rtw_set_fixed_ie(pframe, 2, (u8 *)&ptdls_sta->stat_code, &(pattrib->pktlen)); ++ pframe = rtw_set_fixed_ie(pframe, 1, &(ptdls_sta->dialog), &(pattrib->pktlen)); ++ ++ if(ptdls_sta->stat_code!=0) //invalid setup request ++ return; ++ ++ //RSNIE ++ if(pattrib->encrypt){ ++ prsnie = pframe; ++ pframe = rtw_set_ie(pframe, _RSN_IE_2_, 20, TDLS_RSNIE, &(pattrib->pktlen)); ++ } ++ ++ //EDCA param set; WMM param ele. ++ if(pattrib->encrypt){ ++ //FTIE ++ pftie = pframe; ++ pftie_mic = pframe+4; ++ _rtw_memset(pframe, 0, 84); //All fields except SNonce shall be set to 0 ++ _rtw_memset(pframe, _FTIE_, 1); //version ++ _rtw_memset((pframe+1), 82, 1); //length ++ _rtw_memcpy((pframe+20), ptdls_sta->ANonce, 32); ++ _rtw_memcpy((pframe+52), ptdls_sta->SNonce, 32); ++ pframe += 84; ++ pattrib->pktlen += 84; ++ ++ //Timeout interval ++ ptimeout_ie = pframe; ++ timeout_itvl[0]=0x02; ++ _rtw_memcpy(timeout_itvl+1, (u8 *)(&ptdls_sta->TDLS_PeerKey_Lifetime), 4); ++ ptdls_sta->TPK_count=0; ++ _set_timer(&ptdls_sta->TPK_timer, ptdls_sta->TDLS_PeerKey_Lifetime/TPK_RESEND_COUNT); ++ pframe = rtw_set_ie(pframe, _TIMEOUT_ITVL_IE_, 5, timeout_itvl, &(pattrib->pktlen)); ++ } ++ ++ //HT operation; todo ++ //Link identifier ++ plinkid_ie = pframe; ++ _rtw_memcpy(link_id_addr, pattrib->ra, 6); ++ _rtw_memcpy((link_id_addr+6), pattrib->src, 6); ++ _rtw_memcpy((link_id_addr+12), pattrib->dst, 6); ++ pframe = rtw_set_ie(pframe, _LINK_ID_IE_, 18, link_id_addr, &(pattrib->pktlen)); ++ ++ //fill ftie mic ++ if(pattrib->encrypt) ++ wpa_tdls_ftie_mic(ptdls_sta->tpk.kck, 3, plinkid_ie, prsnie, ptimeout_ie, pftie, pftie_mic); ++ ++} ++ ++void rtw_tdls_teardown_fr(_adapter * padapter, struct xmit_frame * pxmitframe, u8 *pframe) ++{ ++ ++ struct pkt_attrib *pattrib = &pxmitframe->attrib; ++ u8 payload_type = 0x02; ++ unsigned char category = RTW_WLAN_CATEGORY_TDLS; ++ unsigned char action = TDLS_TEARDOWN; ++ u8 link_id_addr[18] = {0}; ++ ++ struct sta_info *ptdls_sta = rtw_get_stainfo( &(padapter->stapriv) , pattrib->dst); ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ ++ //payload type ++ pframe = rtw_set_fixed_ie(pframe, 1, &(payload_type), &(pattrib->pktlen)); ++ //category, action, reason code ++ pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen)); ++ pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen)); ++ pframe = rtw_set_fixed_ie(pframe, 1, (u8 *)&ptdls_sta->stat_code, &(pattrib->pktlen)); ++ ++ //Link identifier ++ if((ptdls_sta->tdls_sta_state & TDLS_INITIATOR_STATE)==TDLS_INITIATOR_STATE){ ++ _rtw_memcpy(link_id_addr, pattrib->ra, 6); ++ _rtw_memcpy((link_id_addr+6), pattrib->src, 6); ++ _rtw_memcpy((link_id_addr+12), pattrib->dst, 6); ++ }else if((ptdls_sta->tdls_sta_state & TDLS_RESPONDER_STATE)==TDLS_RESPONDER_STATE){ ++ _rtw_memcpy(link_id_addr, pattrib->ra, 6); ++ _rtw_memcpy((link_id_addr+6), pattrib->dst, 6); ++ _rtw_memcpy((link_id_addr+12), pattrib->src, 6); ++ } ++ pframe = rtw_set_ie(pframe, _LINK_ID_IE_, 18, link_id_addr, &(pattrib->pktlen)); ++ ++} ++ ++void rtw_tdls_dis_req_fr(_adapter * padapter, struct xmit_frame * pxmitframe, u8 *pframe) ++{ ++ ++ struct pkt_attrib *pattrib = &pxmitframe->attrib; ++ u8 payload_type = 0x02; ++ u8 category = RTW_WLAN_CATEGORY_TDLS; ++ u8 action = TDLS_DISCOVERY_REQUEST; ++ u8 link_id_addr[18] = {0}; ++ static u8 dialogtoken=0; ++ ++ //payload type ++ pframe = rtw_set_fixed_ie(pframe, 1, &(payload_type), &(pattrib->pktlen)); ++ //category, action, reason code ++ pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen)); ++ pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen)); ++ pframe = rtw_set_fixed_ie(pframe, 1, &(dialogtoken), &(pattrib->pktlen)); ++ dialogtoken = (dialogtoken+1)%256; ++ ++ //Link identifier ++ _rtw_memcpy(link_id_addr, pattrib->ra, 6); ++ _rtw_memcpy((link_id_addr+6), pattrib->src, 6); ++ _rtw_memcpy((link_id_addr+12), pattrib->dst, 6); ++ pframe = rtw_set_ie(pframe, _LINK_ID_IE_, 18, link_id_addr, &(pattrib->pktlen)); ++ ++} ++ ++void rtw_tdls_dis_rsp_fr(_adapter * padapter, struct xmit_frame * pxmitframe, u8 *pframe, u8 dialog) ++{ ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info; ++ struct pkt_attrib *pattrib = &pxmitframe->attrib; ++ struct registry_priv *pregistrypriv = &padapter->registrypriv; ++ struct rtw_ieee80211_ht_cap ht_capie; ++ ++ u8 category = RTW_WLAN_CATEGORY_PUBLIC; ++ u8 action = TDLS_DISCOVERY_RESPONSE; ++ u8 bssrate[NDIS_802_11_LENGTH_RATES_EX]; ++ int bssrate_len = 0; ++ u8 more_supportedrates = 0; ++ u8 *p; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ u8 link_id_addr[18] = {0}; ++ u8 sup_ch[ 30 * 2 ] = {0x00 }, sup_ch_idx = 0, idx_5g = 2; //For supported channel ++ u8 iedata=0; ++ u8 timeout_itvl[5]; //set timeout interval to maximum value ++ u32 timeout_interval= TPK_RESEND_COUNT * 1000; ++ ++ //category, action, dialog token ++ pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen)); ++ pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen)); ++ pframe = rtw_set_fixed_ie(pframe, 1, &(dialog), &(pattrib->pktlen)); ++ ++ //capability ++ _rtw_memcpy(pframe, rtw_get_capability_from_ie(pmlmeinfo->network.IEs), 2); ++ ++ if(pattrib->encrypt) ++ *pframe =*pframe | BIT(4); ++ pframe += 2; ++ pattrib->pktlen += 2; ++ ++ //supported rates ++ rtw_set_supported_rate(bssrate, WIRELESS_11BG_24N); ++ bssrate_len = IEEE80211_CCK_RATE_LEN + IEEE80211_NUM_OFDM_RATESLEN; ++ //for (bssrate_len = 0; bssrate_len < NumRates; bssrate_len++) { ++ // if (pregistrypriv->dev_network.SupportedRates[bssrate_len] == 0) break; ++ // bssrate[bssrate_len] = pregistrypriv->dev_network.SupportedRates[bssrate_len]; ++ //} ++ ++ if (bssrate_len > 8) ++ { ++ pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_ , 8, bssrate, &(pattrib->pktlen)); ++ more_supportedrates = 1; ++ } ++ else ++ { ++ pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_ , bssrate_len , bssrate, &(pattrib->pktlen)); ++ } ++ ++ //extended supported rates ++ if(more_supportedrates==1){ ++ pframe = rtw_set_ie(pframe, _EXT_SUPPORTEDRATES_IE_ , (bssrate_len - 8), (bssrate + 8), &(pattrib->pktlen)); ++ } ++ ++ //supported channels ++ do{ ++ if( pmlmeext->channel_set[sup_ch_idx].ChannelNum == 11 ) ++ { ++ sup_ch[0] = 1; //First channel number ++ sup_ch[1] = pmlmeext->channel_set[sup_ch_idx].ChannelNum;; //Number of channel ++ } ++ else if( pmlmeext->channel_set[sup_ch_idx].ChannelNum == 13 ) ++ { ++ sup_ch[0] = 1; ++ sup_ch[1] = pmlmeext->channel_set[sup_ch_idx].ChannelNum;; ++ } ++ else if( pmlmeext->channel_set[sup_ch_idx].ChannelNum > 13 ) ++ { ++ sup_ch[idx_5g++] = pmlmeext->channel_set[sup_ch_idx].ChannelNum; ++ sup_ch[idx_5g++] = 1; ++ } ++ ++ sup_ch_idx++; ++ } ++ while( pmlmeext->channel_set[sup_ch_idx].ChannelNum != 0 ); ++ pframe = rtw_set_ie(pframe, _SUPPORTED_CH_IE_, idx_5g + 2, sup_ch, &(pattrib->pktlen)); ++ ++ //RSNIE ++ if(pattrib->encrypt) ++ pframe = rtw_set_ie(pframe, _RSN_IE_2_, 20, TDLS_RSNIE, &(pattrib->pktlen)); ++ ++ //extended capability ++ pframe = rtw_set_ie(pframe, _EXT_CAP_IE_ , 5, TDLS_EXT_CAPIE, &(pattrib->pktlen)); ++ ++ //FTIE ++ if(pattrib->encrypt){ ++ _rtw_memset(pframe, 0, 84); //All fields except SNonce shall be set to 0 ++ _rtw_memset(pframe, _FTIE_, 1); //version ++ _rtw_memset((pframe+1), 82, 1); //length ++ pframe += 84; ++ pattrib->pktlen += 84; ++ //Timeout interval ++ timeout_itvl[0]=0x02; ++ _rtw_memcpy(timeout_itvl+1, &timeout_interval, 4); ++ pframe = rtw_set_ie(pframe, _TIMEOUT_ITVL_IE_, 5, timeout_itvl, &(pattrib->pktlen)); ++ ++ } ++ ++ //Sup_reg_classes(optional) ++ //HT capabilities ++ _rtw_memset(&ht_capie, 0, sizeof(struct rtw_ieee80211_ht_cap)); ++ ++ ht_capie.cap_info = IEEE80211_HT_CAP_SUP_WIDTH |IEEE80211_HT_CAP_SGI_20 |IEEE80211_HT_CAP_SM_PS | ++ IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_TX_STBC |IEEE80211_HT_CAP_DSSSCCK40; ++ ++ { ++ u32 rx_packet_offset, max_recvbuf_sz; ++ padapter->HalFunc.GetHalDefVarHandler(padapter, HAL_DEF_RX_PACKET_OFFSET, &rx_packet_offset); ++ padapter->HalFunc.GetHalDefVarHandler(padapter, HAL_DEF_MAX_RECVBUF_SZ, &max_recvbuf_sz); ++ if(max_recvbuf_sz-rx_packet_offset>(8191-256)) ++ ht_capie.cap_info = ht_capie.cap_info |IEEE80211_HT_CAP_MAX_AMSDU; ++ } ++ ++ ht_capie.ampdu_params_info = (IEEE80211_HT_CAP_AMPDU_FACTOR&0x03); ++ ++ switch(pHalData->rf_type) ++ { ++ case RF_1T1R: ++ ht_capie.cap_info |= 0x0100;//RX STBC One spatial stream ++ _rtw_memcpy(ht_capie.supp_mcs_set, MCS_rate_1R, 16); ++ break; ++ ++ case RF_2T2R: ++ case RF_1T2R: ++ default: ++ ht_capie.cap_info|= 0x0200;//RX STBC two spatial stream ++ _rtw_memcpy(ht_capie.supp_mcs_set, MCS_rate_2R, 16); ++ break; ++ } ++ ++ pframe = rtw_set_ie(pframe, _HT_CAPABILITY_IE_, ++ sizeof(struct rtw_ieee80211_ht_cap), (unsigned char*)&ht_capie, &(pattrib->pktlen)); ++ ++ //20/40 BSS coexistence ++ if(pmlmepriv->num_FortyMHzIntolerant>0) ++ iedata |= BIT(2);//20 MHz BSS Width Request ++ pframe = rtw_set_ie(pframe, EID_BSSCoexistence, 1, &iedata, &(pattrib->pktlen)); ++ ++ //Link identifier ++ _rtw_memcpy(link_id_addr, pattrib->ra, 6); ++ _rtw_memcpy((link_id_addr+6), pattrib->dst, 6); ++ _rtw_memcpy((link_id_addr+12), pattrib->src, 6); ++ pframe = rtw_set_ie(pframe, _LINK_ID_IE_, 18, link_id_addr, &(pattrib->pktlen)); ++ ++} ++ ++void rtw_tdls_peer_traffic_indication_fr(_adapter * padapter, struct xmit_frame * pxmitframe, u8 *pframe) ++{ ++ ++ struct pkt_attrib *pattrib = &pxmitframe->attrib; ++ u8 payload_type = 0x02; ++ unsigned char category = RTW_WLAN_CATEGORY_TDLS; ++ unsigned char action = TDLS_PEER_TRAFFIC_INDICATION; ++ ++ u8 link_id_addr[18] = {0}; ++ u8 AC_queue=0; ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ struct sta_info *ptdls_sta = rtw_get_stainfo(pstapriv, pattrib->dst); ++ ++ //payload type ++ pframe = rtw_set_fixed_ie(pframe, 1, &(payload_type), &(pattrib->pktlen)); ++ //category, action, reason code ++ pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen)); ++ pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen)); ++ pframe = rtw_set_fixed_ie(pframe, 1, &(ptdls_sta->dialog), &(pattrib->pktlen)); ++ ++ //Link identifier ++ _rtw_memcpy(link_id_addr, pattrib->ra, 6); ++ _rtw_memcpy((link_id_addr+6), pattrib->src, 6); ++ _rtw_memcpy((link_id_addr+12), pattrib->dst, 6); ++ pframe = rtw_set_ie(pframe, _LINK_ID_IE_, 18, link_id_addr, &(pattrib->pktlen)); ++ ++ //PTI control ++ //PU buffer status ++ if(ptdls_sta->uapsd_bk&BIT(1)) ++ AC_queue=BIT(0); ++ if(ptdls_sta->uapsd_be&BIT(1)) ++ AC_queue=BIT(1); ++ if(ptdls_sta->uapsd_vi&BIT(1)) ++ AC_queue=BIT(2); ++ if(ptdls_sta->uapsd_vo&BIT(1)) ++ AC_queue=BIT(3); ++ pframe = rtw_set_ie(pframe, _PTI_BUFFER_STATUS_, 1, &AC_queue, &(pattrib->pktlen)); ++ ++} ++ ++void rtw_tdls_ch_switch_req_fr(_adapter * padapter, struct xmit_frame * pxmitframe, u8 *pframe) ++{ ++ ++ struct pkt_attrib *pattrib = &pxmitframe->attrib; ++ struct tdls_info *ptdlsinfo = &padapter->tdlsinfo; ++ u8 payload_type = 0x02; ++ unsigned char category = RTW_WLAN_CATEGORY_TDLS; ++ unsigned char action = TDLS_CHANNEL_SWITCH_REQUEST; ++ u8 link_id_addr[18] = {0}; ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ struct sta_info *ptdls_sta = rtw_get_stainfo(pstapriv, pattrib->dst); ++ u8 ch_switch_timing[4] = {0}; ++ u16 switch_time= CH_SWITCH_TIME, switch_timeout=CH_SWITCH_TIMEOUT; ++ ++ //payload type ++ pframe = rtw_set_fixed_ie(pframe, 1, &(payload_type), &(pattrib->pktlen)); ++ //category, action, target_ch ++ pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen)); ++ pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen)); ++ pframe = rtw_set_fixed_ie(pframe, 1, &(ptdlsinfo->candidate_ch), &(pattrib->pktlen)); ++ ++ //Link identifier ++ _rtw_memcpy(link_id_addr, pattrib->ra, 6); ++ _rtw_memcpy((link_id_addr+6), pattrib->src, 6); ++ _rtw_memcpy((link_id_addr+12), pattrib->dst, 6); ++ pframe = rtw_set_ie(pframe, _LINK_ID_IE_, 18, link_id_addr, &(pattrib->pktlen)); ++ ++ //ch switch timing ++ _rtw_memcpy(ch_switch_timing, &switch_time, 2); ++ _rtw_memcpy(ch_switch_timing+2, &switch_timeout, 2); ++ pframe = rtw_set_ie(pframe, _CH_SWITCH_TIMING_, 4, ch_switch_timing, &(pattrib->pktlen)); ++ ++ //update ch switch attrib to sta_info ++ ptdls_sta->off_ch=ptdlsinfo->candidate_ch; ++ ptdls_sta->ch_switch_time=switch_time; ++ ptdls_sta->ch_switch_timeout=switch_timeout; ++ ++} ++ ++void rtw_tdls_ch_switch_rsp_fr(_adapter * padapter, struct xmit_frame * pxmitframe, u8 *pframe) ++{ ++ ++ struct pkt_attrib *pattrib = &pxmitframe->attrib; ++ u8 payload_type = 0x02; ++ unsigned char category = RTW_WLAN_CATEGORY_TDLS; ++ unsigned char action = TDLS_CHANNEL_SWITCH_RESPONSE; ++ u8 link_id_addr[18] = {0}; ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ struct sta_info *ptdls_sta = rtw_get_stainfo(pstapriv, pattrib->dst); ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info; ++ u8 ch_switch_timing[4] = {0}; ++ ++ //payload type ++ pframe = rtw_set_fixed_ie(pframe, 1, &(payload_type), &(pattrib->pktlen)); ++ //category, action, status_code ++ pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen)); ++ pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen)); ++ pframe = rtw_set_fixed_ie(pframe, 2, (u8 *)&ptdls_sta->stat_code, &(pattrib->pktlen)); ++ ++ //Link identifier ++ _rtw_memcpy(link_id_addr, pattrib->ra, 6); ++ _rtw_memcpy((link_id_addr+6), pattrib->src, 6); ++ _rtw_memcpy((link_id_addr+12), pattrib->dst, 6); ++ pframe = rtw_set_ie(pframe, _LINK_ID_IE_, 18, link_id_addr, &(pattrib->pktlen)); ++ ++ //ch switch timing ++ _rtw_memcpy(ch_switch_timing, &ptdls_sta->ch_switch_time, 2); ++ _rtw_memcpy(ch_switch_timing+2, &ptdls_sta->ch_switch_timeout, 2); ++ pframe = rtw_set_ie(pframe, _CH_SWITCH_TIMING_, 4, ch_switch_timing, &(pattrib->pktlen)); ++ ++} ++ ++int rtw_tdls_fr(_adapter * padapter, struct xmit_frame * pxmitframe, u8 *pframe, u8 action) ++{ ++ int res=_SUCCESS; ++ ++ switch(action){ ++ case TDLS_SETUP_REQUEST: ++ rtw_tdls_setup_req_fr(padapter, pxmitframe, pframe); ++ break; ++ case TDLS_SETUP_RESPONSE: ++ rtw_tdls_setup_rsp_fr(padapter, pxmitframe, pframe); ++ break; ++ case TDLS_SETUP_CONFIRM: ++ rtw_tdls_setup_cfm_fr(padapter, pxmitframe, pframe); ++ break; ++ case TDLS_TEARDOWN: ++ rtw_tdls_teardown_fr(padapter, pxmitframe, pframe); ++ break; ++ case TDLS_DISCOVERY_REQUEST: ++ rtw_tdls_dis_req_fr(padapter, pxmitframe, pframe); ++ break; ++ case TDLS_PEER_TRAFFIC_INDICATION: ++ rtw_tdls_peer_traffic_indication_fr(padapter, pxmitframe, pframe); ++ break; ++ case TDLS_CHANNEL_SWITCH_REQUEST: ++ rtw_tdls_ch_switch_req_fr(padapter, pxmitframe, pframe); ++ break; ++ case TDLS_CHANNEL_SWITCH_RESPONSE: ++ rtw_tdls_ch_switch_rsp_fr(padapter, pxmitframe, pframe); ++ break; ++ default: ++ res=_FAIL; ++ break; ++ } ++ ++ return res; ++} ++ ++s32 rtw_make_tdls_wlanhdr (_adapter *padapter , u8 *hdr, struct pkt_attrib *pattrib, u8 action) ++{ ++ u16 *qc; ++ struct rtw_ieee80211_hdr *pwlanhdr = (struct rtw_ieee80211_hdr *)hdr; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct qos_priv *pqospriv = &pmlmepriv->qospriv; ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ struct sta_info *psta=NULL, *ptdls_sta=NULL; ++ u8 tdls_seq=0, baddr[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; ++ ++ sint res = _SUCCESS; ++ u16 *fctrl = &pwlanhdr->frame_ctl; ++ ++_func_enter_; ++ ++ _rtw_memset(hdr, 0, WLANHDR_OFFSET); ++ ++ SetFrameSubType(fctrl, pattrib->subtype); ++ ++ switch(action){ ++ case TDLS_SETUP_REQUEST: ++ case TDLS_SETUP_RESPONSE: ++ case TDLS_SETUP_CONFIRM: ++ case TDLS_TEARDOWN: //directly to peer STA or via AP ++ case TDLS_PEER_TRAFFIC_INDICATION: ++ case TDLS_PEER_PSM_REQUEST: //directly to peer STA or via AP ++ SetToDs(fctrl); ++ _rtw_memcpy(pwlanhdr->addr1, get_bssid(pmlmepriv), ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr2, pattrib->src, ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr3, pattrib->dst, ETH_ALEN); ++ break; ++ case TDLS_CHANNEL_SWITCH_REQUEST: ++ case TDLS_CHANNEL_SWITCH_RESPONSE: ++ case TDLS_PEER_PSM_RESPONSE: ++ case TDLS_PEER_TRAFFIC_RESPONSE: ++ _rtw_memcpy(pwlanhdr->addr1, pattrib->dst, ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr2, pattrib->src, ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr3, get_bssid(pmlmepriv), ETH_ALEN); ++ tdls_seq=1; ++ break; ++ case TDLS_DISCOVERY_REQUEST: //unicast: directly to peer sta, Bcast: via AP ++ if(_rtw_memcmp(pattrib->dst, baddr, 6) ) ++ { ++ SetToDs(fctrl); ++ _rtw_memcpy(pwlanhdr->addr1, get_bssid(pmlmepriv), ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr2, pattrib->src, ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr3, pattrib->dst, ETH_ALEN); ++ } ++ else ++ { ++ _rtw_memcpy(pwlanhdr->addr1, pattrib->dst, ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr2, pattrib->src, ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr3, get_bssid(pmlmepriv), ETH_ALEN); ++ tdls_seq=1; ++ } ++ break; ++ } ++ ++ if (pattrib->encrypt) ++ SetPrivacy(fctrl); ++ ++ if (pqospriv->qos_option) ++ { ++ qc = (unsigned short *)(hdr + pattrib->hdrlen - 2); ++ if (pattrib->priority) ++ SetPriority(qc, pattrib->priority); ++ SetAckpolicy(qc, pattrib->ack_policy); ++ } ++ ++ psta = pattrib->psta; ++ ++ // 1. update seq_num per link by sta_info ++ // 2. rewrite encrypt to _AES_, also rewrite iv_len, icv_len ++ if(tdls_seq==1){ ++ ptdls_sta=rtw_get_stainfo(pstapriv, pattrib->dst); ++ if(ptdls_sta){ ++ ptdls_sta->sta_xmitpriv.txseq_tid[pattrib->priority]++; ++ ptdls_sta->sta_xmitpriv.txseq_tid[pattrib->priority] &= 0xFFF; ++ pattrib->seqnum = ptdls_sta->sta_xmitpriv.txseq_tid[pattrib->priority]; ++ SetSeqNum(hdr, pattrib->seqnum); ++ ++ if (pattrib->encrypt){ ++ pattrib->encrypt= _AES_; ++ pattrib->iv_len=8; ++ pattrib->icv_len=8; ++ } ++ }else{ ++ res=_FAIL; ++ goto exit; ++ } ++ }else if(psta){ ++ psta->sta_xmitpriv.txseq_tid[pattrib->priority]++; ++ psta->sta_xmitpriv.txseq_tid[pattrib->priority] &= 0xFFF; ++ pattrib->seqnum = psta->sta_xmitpriv.txseq_tid[pattrib->priority]; ++ SetSeqNum(hdr, pattrib->seqnum); ++ } ++ ++ ++exit: ++ ++_func_exit_; ++ ++ return res; ++} ++ ++s32 rtw_xmit_tdls_coalesce(_adapter * padapter, struct xmit_frame * pxmitframe, u8 action) ++{ ++ s32 llc_sz; ++ ++ u8 *pframe, *mem_start; ++ ++ struct sta_info *psta; ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct pkt_attrib *pattrib = &pxmitframe->attrib; ++ u8 *pbuf_start; ++ s32 bmcst = IS_MCAST(pattrib->ra); ++ s32 res = _SUCCESS; ++ ++_func_enter_; ++ ++ if (pattrib->psta) { ++ psta = pattrib->psta; ++ } else { ++ if(bmcst) { ++ psta = rtw_get_bcmc_stainfo(padapter); ++ } else { ++ psta = rtw_get_stainfo(&padapter->stapriv, pattrib->ra); ++ } ++ } ++ ++ if(psta==NULL) ++ return _FAIL; ++ ++ if (pxmitframe->buf_addr == NULL) ++ return _FAIL; ++ ++ pbuf_start = pxmitframe->buf_addr; ++ mem_start = pbuf_start + TXDESC_OFFSET; ++ ++ if (rtw_make_tdls_wlanhdr(padapter, mem_start, pattrib, action) == _FAIL) { ++ res = _FAIL; ++ goto exit; ++ } ++ ++ pframe = mem_start; ++ pframe += pattrib->hdrlen; ++ ++ //adding icv, if necessary... ++ if (pattrib->iv_len) ++ { ++ if (psta != NULL) ++ { ++ switch(pattrib->encrypt) ++ { ++ case _WEP40_: ++ case _WEP104_: ++ WEP_IV(pattrib->iv, psta->dot11txpn, pattrib->key_idx); ++ break; ++ case _TKIP_: ++ if(bmcst) ++ TKIP_IV(pattrib->iv, psta->dot11txpn, pattrib->key_idx); ++ else ++ TKIP_IV(pattrib->iv, psta->dot11txpn, 0); ++ break; ++ case _AES_: ++ if(bmcst) ++ AES_IV(pattrib->iv, psta->dot11txpn, pattrib->key_idx); ++ else ++ AES_IV(pattrib->iv, psta->dot11txpn, 0); ++ break; ++ } ++ } ++ ++ _rtw_memcpy(pframe, pattrib->iv, pattrib->iv_len); ++ pframe += pattrib->iv_len; ++ ++ } ++ ++ llc_sz = rtw_put_snap(pframe, pattrib->ether_type); ++ pframe += llc_sz; ++ ++ //pattrib->pktlen will be counted in rtw_tdls_fr ++ pattrib->pktlen = 0; ++ ++ rtw_tdls_fr(padapter, pxmitframe, pframe, action); ++ ++ if ((pattrib->icv_len >0 )&& (pattrib->bswenc)) { ++ pframe += pattrib->pktlen; ++ _rtw_memcpy(pframe, pattrib->icv, pattrib->icv_len); ++ pframe += pattrib->icv_len; ++ } ++ ++ pattrib->nr_frags = 1; ++ pattrib->last_txcmdsz = pattrib->hdrlen + pattrib->iv_len + llc_sz + ++ ((pattrib->bswenc) ? pattrib->icv_len : 0) + pattrib->pktlen; ++ ++ if (xmitframe_addmic(padapter, pxmitframe) == _FAIL) ++ { ++ goto exit; ++ } ++ ++ xmitframe_swencrypt(padapter, pxmitframe); ++ ++ update_attrib_vcs_info(padapter, pxmitframe); ++ ++exit: ++ ++_func_exit_; ++ ++ return res; ++} ++#endif ++ ++/* ++ ++This sub-routine will perform all the following: ++ ++1. remove 802.3 header. ++2. create wlan_header, based on the info in pxmitframe ++3. append sta's iv/ext-iv ++4. append LLC ++5. move frag chunk from pframe to pxmitframe->mem ++6. apply sw-encrypt, if necessary. ++ ++*/ ++s32 rtw_xmitframe_coalesce(_adapter *padapter, _pkt *pkt, struct xmit_frame *pxmitframe) ++{ ++ struct pkt_file pktfile; ++ ++ s32 frg_inx, frg_len, mpdu_len, llc_sz, mem_sz; ++ ++ SIZE_PTR addr; ++ ++ u8 *pframe, *mem_start; ++ ++ struct sta_info *psta; ++ //struct sta_priv *pstapriv = &padapter->stapriv; ++ //struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct xmit_priv *pxmitpriv = &padapter->xmitpriv; ++ ++ struct pkt_attrib *pattrib = &pxmitframe->attrib; ++ ++ u8 *pbuf_start; ++ ++ s32 bmcst = IS_MCAST(pattrib->ra); ++ s32 res = _SUCCESS; ++ ++_func_enter_; ++ ++ if (pattrib->psta) { ++ psta = pattrib->psta; ++ } else { ++ psta = rtw_get_stainfo(&padapter->stapriv, pattrib->ra); ++ } ++ ++ if(psta==NULL) ++ return _FAIL; ++ ++ if (pxmitframe->buf_addr == NULL) ++ return _FAIL; ++ ++ pbuf_start = pxmitframe->buf_addr; ++ ++#ifdef CONFIG_USB_TX_AGGREGATION ++ mem_start = pbuf_start + TXDESC_SIZE + (pxmitframe->pkt_offset * PACKET_OFFSET_SZ); ++#else ++ mem_start = pbuf_start + TXDESC_OFFSET; ++#endif ++ ++ if (rtw_make_wlanhdr(padapter, mem_start, pattrib) == _FAIL) { ++ RT_TRACE(_module_rtl871x_xmit_c_, _drv_err_, ("rtw_xmitframe_coalesce: rtw_make_wlanhdr fail; drop pkt\n")); ++ res = _FAIL; ++ goto exit; ++ } ++ ++ _rtw_open_pktfile(pkt, &pktfile); ++ _rtw_pktfile_read(&pktfile, NULL, pattrib->pkt_hdrlen); ++ ++ pattrib->pktlen = pktfile.pkt_len; ++ ++ frg_inx = 0; ++ frg_len = pxmitpriv->frag_len - 4;//2346-4 = 2342 ++ ++ while (1) ++ { ++ llc_sz = 0; ++ ++ mpdu_len = frg_len; ++ ++ pframe = mem_start; ++ ++ SetMFrag(mem_start); ++ ++ pframe += pattrib->hdrlen; ++ mpdu_len -= pattrib->hdrlen; ++ ++ //adding icv, if necessary... ++ if (pattrib->iv_len) ++ { ++ //if (check_fwstate(pmlmepriv, WIFI_MP_STATE)) ++ // psta = rtw_get_stainfo(pstapriv, get_bssid(pmlmepriv)); ++ //else ++ // psta = rtw_get_stainfo(pstapriv, pattrib->ra); ++ ++ if (psta != NULL) ++ { ++ switch(pattrib->encrypt) ++ { ++ case _WEP40_: ++ case _WEP104_: ++ WEP_IV(pattrib->iv, psta->dot11txpn, pattrib->key_idx); ++ break; ++ case _TKIP_: ++ if(bmcst) ++ TKIP_IV(pattrib->iv, psta->dot11txpn, pattrib->key_idx); ++ else ++ TKIP_IV(pattrib->iv, psta->dot11txpn, 0); ++ break; ++ case _AES_: ++ if(bmcst) ++ AES_IV(pattrib->iv, psta->dot11txpn, pattrib->key_idx); ++ else ++ AES_IV(pattrib->iv, psta->dot11txpn, 0); ++ break; ++ } ++ } ++ ++ _rtw_memcpy(pframe, pattrib->iv, pattrib->iv_len); ++ ++ RT_TRACE(_module_rtl871x_xmit_c_, _drv_notice_, ++ ("rtw_xmitframe_coalesce: keyid=%d pattrib->iv[3]=%.2x pframe=%.2x %.2x %.2x %.2x\n", ++ padapter->securitypriv.dot11PrivacyKeyIndex, pattrib->iv[3], *pframe, *(pframe+1), *(pframe+2), *(pframe+3))); ++ ++ pframe += pattrib->iv_len; ++ ++ mpdu_len -= pattrib->iv_len; ++ } ++ ++ if (frg_inx == 0) { ++ llc_sz = rtw_put_snap(pframe, pattrib->ether_type); ++ pframe += llc_sz; ++ mpdu_len -= llc_sz; ++ } ++ ++ if ((pattrib->icv_len >0) && (pattrib->bswenc)) { ++ mpdu_len -= pattrib->icv_len; ++ } ++ ++ ++ if (bmcst) { ++ // don't do fragment to broadcat/multicast packets ++ mem_sz = _rtw_pktfile_read(&pktfile, pframe, pattrib->pktlen); ++ } else { ++ mem_sz = _rtw_pktfile_read(&pktfile, pframe, mpdu_len); ++ } ++ ++ pframe += mem_sz; ++ ++ if ((pattrib->icv_len >0 )&& (pattrib->bswenc)) { ++ _rtw_memcpy(pframe, pattrib->icv, pattrib->icv_len); ++ pframe += pattrib->icv_len; ++ } ++ ++ frg_inx++; ++ ++ if (bmcst || (rtw_endofpktfile(&pktfile) == _TRUE)) ++ { ++ pattrib->nr_frags = frg_inx; ++ ++ pattrib->last_txcmdsz = pattrib->hdrlen + pattrib->iv_len + ((pattrib->nr_frags==1)? llc_sz:0) + ++ ((pattrib->bswenc) ? pattrib->icv_len : 0) + mem_sz; ++ ++ ClearMFrag(mem_start); ++ ++#ifdef CONFIG_SDIO_HCI ++ RT_TRACE(_module_rtl871x_xmit_c_,_drv_err_,("coalesce: pattrib->last_txcmdsz=%d pxmitframe->pxmitbuf->phead=0x%p pxmitframe->pxmitbuf->ptail=0x%p pxmitframe->pxmitbuf->len=%d\n", pattrib->last_txcmdsz, pxmitframe->pxmitbuf->phead, pxmitframe->pxmitbuf->ptail, pxmitframe->pxmitbuf->len)); ++ pxmitframe->pxmitbuf->ptail = pxmitframe->buf_addr + _RND512(pframe-pxmitframe->buf_addr); ++ pxmitframe->pxmitbuf->len += pxmitframe->pxmitbuf->ptail - pxmitframe->buf_addr;//(pframe-mem_start); ++ RT_TRACE(_module_rtl871x_xmit_c_, _drv_err_, ("coalesce: [2] pattrib->last_txcmdsz=%d pxmitframe->pxmitbuf->ptail=0x%p pxmitframe->pxmitbuf->len=%d\n", pattrib->last_txcmdsz, pxmitframe->pxmitbuf->ptail, pxmitframe->pxmitbuf->len)); ++#endif ++ ++ break; ++ ++ } else { ++ ++#ifdef CONFIG_SDIO_HCI ++ pxmitframe->pxmitbuf->ptail = pxmitframe->buf_addr + _RND512(pframe-pxmitframe->buf_addr); ++ pxmitframe->pxmitbuf->len += pxmitframe->pxmitbuf->ptail - pxmitframe->buf_addr; ++ pframe=pxmitframe->pxmitbuf->ptail; ++#endif ++ } ++ ++ addr = (SIZE_PTR)(pframe); ++ ++ mem_start = (unsigned char *)RND4(addr) + TXDESC_OFFSET; ++ _rtw_memcpy(mem_start, pbuf_start + TXDESC_OFFSET, pattrib->hdrlen); ++ } ++ ++ if (xmitframe_addmic(padapter, pxmitframe) == _FAIL) ++ { ++ RT_TRACE(_module_rtl871x_xmit_c_, _drv_err_, ("xmitframe_addmic(padapter, pxmitframe)==_FAIL\n")); ++ res = _FAIL; ++ goto exit; ++ } ++ ++#ifdef CONFIG_SDIO_HCI ++ fillin_txdesc(padapter, pxmitframe); ++#endif ++ ++ xmitframe_swencrypt(padapter, pxmitframe); ++ ++ if(bmcst == _FALSE) ++ update_attrib_vcs_info(padapter, pxmitframe); ++ else ++ pattrib->vcs_mode = NONE_VCS; ++ ++exit: ++ ++_func_exit_; ++ ++ return res; ++} ++ ++/* Logical Link Control(LLC) SubNetwork Attachment Point(SNAP) header ++ * IEEE LLC/SNAP header contains 8 octets ++ * First 3 octets comprise the LLC portion ++ * SNAP portion, 5 octets, is divided into two fields: ++ * Organizationally Unique Identifier(OUI), 3 octets, ++ * type, defined by that organization, 2 octets. ++ */ ++s32 rtw_put_snap(u8 *data, u16 h_proto) ++{ ++ struct ieee80211_snap_hdr *snap; ++ u8 *oui; ++ ++_func_enter_; ++ ++ snap = (struct ieee80211_snap_hdr *)data; ++ snap->dsap = 0xaa; ++ snap->ssap = 0xaa; ++ snap->ctrl = 0x03; ++ ++ if (h_proto == 0x8137 || h_proto == 0x80f3) ++ oui = P802_1H_OUI; ++ else ++ oui = RFC1042_OUI; ++ ++ snap->oui[0] = oui[0]; ++ snap->oui[1] = oui[1]; ++ snap->oui[2] = oui[2]; ++ ++ *(u16 *)(data + SNAP_SIZE) = htons(h_proto); ++ ++_func_exit_; ++ ++ return SNAP_SIZE + sizeof(u16); ++} ++ ++void rtw_update_protection(_adapter *padapter, u8 *ie, uint ie_len) ++{ ++ ++ uint protection; ++ u8 *perp; ++ sint erp_len; ++ struct xmit_priv *pxmitpriv = &padapter->xmitpriv; ++ struct registry_priv *pregistrypriv = &padapter->registrypriv; ++ ++_func_enter_; ++ ++ switch(pxmitpriv->vcs_setting) ++ { ++ case DISABLE_VCS: ++ pxmitpriv->vcs = NONE_VCS; ++ break; ++ ++ case ENABLE_VCS: ++ break; ++ ++ case AUTO_VCS: ++ default: ++ perp = rtw_get_ie(ie, _ERPINFO_IE_, &erp_len, ie_len); ++ if(perp == NULL) ++ { ++ pxmitpriv->vcs = NONE_VCS; ++ } ++ else ++ { ++ protection = (*(perp + 2)) & BIT(1); ++ if (protection) ++ { ++ if(pregistrypriv->vcs_type == RTS_CTS) ++ pxmitpriv->vcs = RTS_CTS; ++ else ++ pxmitpriv->vcs = CTS_TO_SELF; ++ } ++ else ++ pxmitpriv->vcs = NONE_VCS; ++ } ++ ++ break; ++ ++ } ++ ++_func_exit_; ++ ++} ++ ++void rtw_count_tx_stats(_adapter *padapter, struct xmit_frame *pxmitframe, int sz) ++{ ++ struct sta_info *psta = NULL; ++ struct stainfo_stats *pstats = NULL; ++ struct xmit_priv *pxmitpriv = &padapter->xmitpriv; ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ ++ if((pxmitframe->frame_tag&0x0f) == DATA_FRAMETAG) ++ { ++ pxmitpriv->tx_bytes += sz; ++#ifdef CONFIG_USB_TX_AGGREGATION ++ pmlmepriv->LinkDetectInfo.NumTxOkInPeriod += pxmitframe->agg_num; ++#else ++ pmlmepriv->LinkDetectInfo.NumTxOkInPeriod++; ++#endif ++ ++ psta = pxmitframe->attrib.psta; ++ ++ if(psta) ++ { ++ pstats = &psta->sta_stats; ++#ifdef CONFIG_USB_TX_AGGREGATION ++ pstats->tx_pkts += pxmitframe->agg_num; ++#else ++ pstats->tx_pkts++; ++#endif ++ pstats->tx_bytes += sz; ++ } ++ } ++ ++} ++ ++struct xmit_buf *rtw_alloc_xmitbuf_ext(struct xmit_priv *pxmitpriv) ++{ ++ _irqL irqL; ++ struct xmit_buf *pxmitbuf = NULL; ++ _list *plist, *phead; ++ _queue *pfree_queue = &pxmitpriv->free_xmit_extbuf_queue; ++ ++_func_enter_; ++ ++ _enter_critical(&pfree_queue->lock, &irqL); ++ ++ if(_rtw_queue_empty(pfree_queue) == _TRUE) { ++ pxmitbuf = NULL; ++ } else { ++ ++ phead = get_list_head(pfree_queue); ++ ++ plist = get_next(phead); ++ ++ pxmitbuf = LIST_CONTAINOR(plist, struct xmit_buf, list); ++ ++ rtw_list_delete(&(pxmitbuf->list)); ++ } ++ ++ if (pxmitbuf != NULL) ++ { ++ pxmitpriv->free_xmit_extbuf_cnt--; ++ #ifdef DBG_XMIT_BUF ++ DBG_871X("DBG_XMIT_BUF ALLOC no=%d, free_xmit_extbuf_cnt=%d\n",pxmitbuf->no, pxmitpriv->free_xmit_extbuf_cnt); ++ #endif ++ ++ ++ pxmitbuf->priv_data = NULL; ++ ++#ifdef CONFIG_SDIO_HCI ++ pxmitbuf->len = 0; ++ pxmitbuf->phead = pxmitbuf->pdata = pxmitbuf->ptail = pxmitbuf->pbuf; ++ pxmitbuf->pend = pxmitbuf->pbuf + (MAX_XMIT_EXTBUF_SZ-4); ++#endif ++#ifdef CONFIG_PCI_HCI ++ pxmitbuf->len = 0; ++#endif ++ } ++ ++ _exit_critical(&pfree_queue->lock, &irqL); ++ ++_func_exit_; ++ ++ return pxmitbuf; ++} ++ ++s32 rtw_free_xmitbuf_ext(struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf) ++{ ++ _irqL irqL; ++ _queue *pfree_queue = &pxmitpriv->free_xmit_extbuf_queue; ++ ++_func_enter_; ++ ++ if(pxmitbuf==NULL) ++ { ++ return _FAIL; ++ } ++ ++ _enter_critical(&pfree_queue->lock, &irqL); ++ ++ rtw_list_delete(&pxmitbuf->list); ++ ++ rtw_list_insert_tail(&(pxmitbuf->list), get_list_head(pfree_queue)); ++ pxmitpriv->free_xmit_extbuf_cnt++; ++ #ifdef DBG_XMIT_BUF ++ DBG_871X("DBG_XMIT_BUF FREE no=%d, free_xmit_extbuf_cnt=%d\n",pxmitbuf->no ,pxmitpriv->free_xmit_extbuf_cnt); ++ #endif ++ ++ _exit_critical(&pfree_queue->lock, &irqL); ++ ++_func_exit_; ++ ++ return _SUCCESS; ++} ++ ++struct xmit_buf *rtw_alloc_xmitbuf(struct xmit_priv *pxmitpriv) ++{ ++ _irqL irqL; ++ struct xmit_buf *pxmitbuf = NULL; ++ _list *plist, *phead; ++ _queue *pfree_xmitbuf_queue = &pxmitpriv->free_xmitbuf_queue; ++ ++_func_enter_; ++ ++ //DBG_8192C("+rtw_alloc_xmitbuf\n"); ++ ++ _enter_critical(&pfree_xmitbuf_queue->lock, &irqL); ++ ++ if(_rtw_queue_empty(pfree_xmitbuf_queue) == _TRUE) { ++ pxmitbuf = NULL; ++ } else { ++ ++ phead = get_list_head(pfree_xmitbuf_queue); ++ ++ plist = get_next(phead); ++ ++ pxmitbuf = LIST_CONTAINOR(plist, struct xmit_buf, list); ++ ++ rtw_list_delete(&(pxmitbuf->list)); ++ } ++ ++ if (pxmitbuf != NULL) ++ { ++ pxmitpriv->free_xmitbuf_cnt--; ++ #ifdef DBG_XMIT_BUF ++ DBG_871X("DBG_XMIT_BUF ALLOC no=%d, free_xmitbuf_cnt=%d\n",pxmitbuf->no, pxmitpriv->free_xmitbuf_cnt); ++ #endif ++ //DBG_8192C("alloc, free_xmitbuf_cnt=%d\n", pxmitpriv->free_xmitbuf_cnt); ++ ++ pxmitbuf->priv_data = NULL; ++ ++#ifdef CONFIG_SDIO_HCI ++ pxmitbuf->len = 0; ++ pxmitbuf->phead = pxmitbuf->pdata = pxmitbuf->ptail = pxmitbuf->pbuf; ++ pxmitbuf->pend = pxmitbuf->pbuf + MAX_XMITBUF_SZ; ++#endif ++#ifdef CONFIG_PCI_HCI ++ pxmitbuf->len = 0; ++#endif ++ } ++ #ifdef DBG_XMIT_BUF ++ else ++ { ++ DBG_871X("DBG_XMIT_BUF rtw_alloc_xmitbuf return NULL\n"); ++ } ++ #endif ++ ++ _exit_critical(&pfree_xmitbuf_queue->lock, &irqL); ++ ++_func_exit_; ++ ++ return pxmitbuf; ++} ++ ++s32 rtw_free_xmitbuf(struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf) ++{ ++ _irqL irqL; ++ _queue *pfree_xmitbuf_queue = &pxmitpriv->free_xmitbuf_queue; ++ ++_func_enter_; ++ ++ //DBG_8192C("+rtw_free_xmitbuf\n"); ++ ++ if(pxmitbuf==NULL) ++ { ++ return _FAIL; ++ } ++ ++ if(pxmitbuf->ext_tag) ++ { ++ rtw_free_xmitbuf_ext(pxmitpriv, pxmitbuf); ++ } ++ else ++ { ++ _enter_critical(&pfree_xmitbuf_queue->lock, &irqL); ++ ++ rtw_list_delete(&pxmitbuf->list); ++ ++ rtw_list_insert_tail(&(pxmitbuf->list), get_list_head(pfree_xmitbuf_queue)); ++ ++ pxmitpriv->free_xmitbuf_cnt++; ++ //DBG_8192C("FREE, free_xmitbuf_cnt=%d\n", pxmitpriv->free_xmitbuf_cnt); ++ #ifdef DBG_XMIT_BUF ++ DBG_871X("DBG_XMIT_BUF FREE no=%d, free_xmitbuf_cnt=%d\n",pxmitbuf->no ,pxmitpriv->free_xmitbuf_cnt); ++ #endif ++ _exit_critical(&pfree_xmitbuf_queue->lock, &irqL); ++ } ++ ++_func_exit_; ++ ++ return _SUCCESS; ++} ++ ++/* ++Calling context: ++1. OS_TXENTRY ++2. RXENTRY (rx_thread or RX_ISR/RX_CallBack) ++ ++If we turn on USE_RXTHREAD, then, no need for critical section. ++Otherwise, we must use _enter/_exit critical to protect free_xmit_queue... ++ ++Must be very very cautious... ++ ++*/ ++ ++struct xmit_frame *rtw_alloc_xmitframe(struct xmit_priv *pxmitpriv)//(_queue *pfree_xmit_queue) ++{ ++ /* ++ Please remember to use all the osdep_service api, ++ and lock/unlock or _enter/_exit critical to protect ++ pfree_xmit_queue ++ */ ++ ++ _irqL irqL; ++ struct xmit_frame *pxframe = NULL; ++ _list *plist, *phead; ++ _queue *pfree_xmit_queue = &pxmitpriv->free_xmit_queue; ++ _adapter *padapter = pxmitpriv->adapter; ++ ++_func_enter_; ++ ++ _enter_critical_bh(&pfree_xmit_queue->lock, &irqL); ++ ++ if (_rtw_queue_empty(pfree_xmit_queue) == _TRUE) { ++ RT_TRACE(_module_rtl871x_xmit_c_,_drv_info_,("rtw_alloc_xmitframe:%d\n", pxmitpriv->free_xmitframe_cnt)); ++ pxframe = NULL; ++ } else { ++ phead = get_list_head(pfree_xmit_queue); ++ ++ plist = get_next(phead); ++ ++ pxframe = LIST_CONTAINOR(plist, struct xmit_frame, list); ++ ++ rtw_list_delete(&(pxframe->list)); ++ } ++ ++ if (pxframe != NULL) ++ { ++ pxmitpriv->free_xmitframe_cnt--; ++ ++ RT_TRACE(_module_rtl871x_xmit_c_, _drv_info_, ("rtw_alloc_xmitframe():free_xmitframe_cnt=%d\n", pxmitpriv->free_xmitframe_cnt)); ++ ++ pxframe->buf_addr = NULL; ++ pxframe->pxmitbuf = NULL; ++ ++ _rtw_memset(&pxframe->attrib, 0, sizeof(struct pkt_attrib)); ++ //pxframe->attrib.psta = NULL; ++ ++ pxframe->frame_tag = DATA_FRAMETAG; ++ ++#ifdef CONFIG_USB_HCI ++ pxframe->pkt = NULL; ++ pxframe->pkt_offset = 1;//default use pkt_offset to fill tx desc ++ ++#ifdef CONFIG_USB_TX_AGGREGATION ++ pxframe->agg_num = 1; ++#endif ++ ++#endif //#ifdef CONFIG_USB_HCI ++ ++#ifdef PLATFORM_LINUX ++ if(pxmitpriv->free_xmitframe_cnt==1) ++ { ++ if (!netif_queue_stopped(padapter->pnetdev)) ++ netif_stop_queue(padapter->pnetdev); ++ } ++#endif ++ ++ } ++ ++ _exit_critical_bh(&pfree_xmit_queue->lock, &irqL); ++ ++_func_exit_; ++ ++ return pxframe; ++} ++ ++s32 rtw_free_xmitframe(struct xmit_priv *pxmitpriv, struct xmit_frame *pxmitframe) ++{ ++ _irqL irqL; ++ _queue *pfree_xmit_queue = &pxmitpriv->free_xmit_queue; ++ _adapter *padapter = pxmitpriv->adapter; ++ _pkt *pndis_pkt = NULL; ++ ++_func_enter_; ++ ++ if (pxmitframe == NULL) { ++ RT_TRACE(_module_rtl871x_xmit_c_, _drv_err_, ("======rtw_free_xmitframe():pxmitframe==NULL!!!!!!!!!!\n")); ++ goto exit; ++ } ++ ++ _enter_critical_bh(&pfree_xmit_queue->lock, &irqL); ++ ++ rtw_list_delete(&pxmitframe->list); ++ ++ if (pxmitframe->pkt){ ++ pndis_pkt = pxmitframe->pkt; ++ pxmitframe->pkt = NULL; ++ } ++ ++ rtw_list_insert_tail(&pxmitframe->list, get_list_head(pfree_xmit_queue)); ++ ++ pxmitpriv->free_xmitframe_cnt++; ++ RT_TRACE(_module_rtl871x_xmit_c_, _drv_debug_, ("rtw_free_xmitframe():free_xmitframe_cnt=%d\n", pxmitpriv->free_xmitframe_cnt)); ++ ++ _exit_critical_bh(&pfree_xmit_queue->lock, &irqL); ++ ++ ++ if(pndis_pkt) ++ rtw_os_pkt_complete(padapter, pndis_pkt); ++ ++exit: ++ ++_func_exit_; ++ ++ return _SUCCESS; ++} ++ ++s32 rtw_free_xmitframe_ex(struct xmit_priv *pxmitpriv, struct xmit_frame *pxmitframe) ++{ ++ ++_func_enter_; ++ ++ if(pxmitframe==NULL){ ++ goto exit; ++ } ++ ++ RT_TRACE(_module_rtl871x_xmit_c_, _drv_debug_, ("rtw_free_xmitframe_ex()\n")); ++ ++ rtw_free_xmitframe(pxmitpriv, pxmitframe); ++ ++exit: ++ ++_func_exit_; ++ ++ return _SUCCESS; ++} ++ ++void rtw_free_xmitframe_queue(struct xmit_priv *pxmitpriv, _queue *pframequeue) ++{ ++ _irqL irqL; ++ _list *plist, *phead; ++ struct xmit_frame *pxmitframe; ++ ++_func_enter_; ++ ++ _enter_critical_bh(&(pframequeue->lock), &irqL); ++ ++ phead = get_list_head(pframequeue); ++ plist = get_next(phead); ++ ++ while (rtw_end_of_queue_search(phead, plist) == _FALSE) ++ { ++ ++ pxmitframe = LIST_CONTAINOR(plist, struct xmit_frame, list); ++ ++ plist = get_next(plist); ++ ++ rtw_free_xmitframe(pxmitpriv,pxmitframe); ++ ++ } ++ _exit_critical_bh(&(pframequeue->lock), &irqL); ++ ++_func_exit_; ++} ++ ++s32 rtw_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe) ++{ ++ if (rtw_xmit_classifier(padapter, pxmitframe) == _FAIL) ++ { ++ RT_TRACE(_module_rtl871x_xmit_c_, _drv_err_, ++ ("rtw_xmitframe_enqueue: drop xmit pkt for classifier fail\n")); ++// pxmitframe->pkt = NULL; ++ return _FAIL; ++ } ++ ++ return _SUCCESS; ++} ++ ++static struct xmit_frame *dequeue_one_xmitframe(struct xmit_priv *pxmitpriv, struct hw_xmit *phwxmit, struct tx_servq *ptxservq, _queue *pframe_queue) ++{ ++ _list *xmitframe_plist, *xmitframe_phead; ++ struct xmit_frame *pxmitframe=NULL; ++ ++ xmitframe_phead = get_list_head(pframe_queue); ++ xmitframe_plist = get_next(xmitframe_phead); ++ ++ while ((rtw_end_of_queue_search(xmitframe_phead, xmitframe_plist)) == _FALSE) ++ { ++ pxmitframe = LIST_CONTAINOR(xmitframe_plist, struct xmit_frame, list); ++ ++ xmitframe_plist = get_next(xmitframe_plist); ++ ++/*#ifdef RTK_DMP_PLATFORM ++#ifdef CONFIG_USB_TX_AGGREGATION ++ if((ptxservq->qcnt>0) && (ptxservq->qcnt<=2)) ++ { ++ pxmitframe = NULL; ++ ++ tasklet_schedule(&pxmitpriv->xmit_tasklet); ++ ++ break; ++ } ++#endif ++#endif*/ ++ rtw_list_delete(&pxmitframe->list); ++ ++ ptxservq->qcnt--; ++ ++ //rtw_list_insert_tail(&pxmitframe->list, &phwxmit->pending); ++ ++ //ptxservq->qcnt--; ++ ++ break; ++ ++ pxmitframe = NULL; ++ ++ } ++ ++ return pxmitframe; ++} ++ ++struct xmit_frame* rtw_dequeue_xframe(struct xmit_priv *pxmitpriv, struct hw_xmit *phwxmit_i, sint entry) ++{ ++ _irqL irqL0; ++ _list *sta_plist, *sta_phead; ++ struct hw_xmit *phwxmit; ++ struct tx_servq *ptxservq = NULL; ++ _queue *pframe_queue = NULL; ++ struct xmit_frame *pxmitframe = NULL; ++ _adapter *padapter = pxmitpriv->adapter; ++ struct registry_priv *pregpriv = &padapter->registrypriv; ++ int i, inx[4]; ++#ifdef CONFIG_USB_HCI ++// int j, tmp, acirp_cnt[4]; ++#endif ++ ++_func_enter_; ++ ++ inx[0] = 0; inx[1] = 1; inx[2] = 2; inx[3] = 3; ++ ++ if(pregpriv->wifi_spec==1) ++ { ++ int j, tmp, acirp_cnt[4]; ++#if 0 ++ if(flagsvo, 1->vi, 2->be, 3->bk. ++ acirp_cnt[0] = pxmitpriv->voq_cnt; ++ acirp_cnt[1] = pxmitpriv->viq_cnt; ++ acirp_cnt[2] = pxmitpriv->beq_cnt; ++ acirp_cnt[3] = pxmitpriv->bkq_cnt; ++ ++ for(i=0; i<4; i++) ++ { ++ for(j=i+1; j<4; j++) ++ { ++ if(acirp_cnt[j]lock, &irqL0); ++ ++ for(i = 0; i < entry; i++) ++ { ++ phwxmit = phwxmit_i + inx[i]; ++ ++ //_enter_critical_ex(&phwxmit->sta_queue->lock, &irqL0); ++ ++ sta_phead = get_list_head(phwxmit->sta_queue); ++ sta_plist = get_next(sta_phead); ++ ++ while ((rtw_end_of_queue_search(sta_phead, sta_plist)) == _FALSE) ++ { ++ ++ ptxservq= LIST_CONTAINOR(sta_plist, struct tx_servq, tx_pending); ++ ++ pframe_queue = &ptxservq->sta_pending; ++ ++ pxmitframe = dequeue_one_xmitframe(pxmitpriv, phwxmit, ptxservq, pframe_queue); ++ ++ if(pxmitframe) ++ { ++ phwxmit->accnt--; ++ ++ //Remove sta node when there is no pending packets. ++ if(_rtw_queue_empty(pframe_queue)) //must be done after get_next and before break ++ rtw_list_delete(&ptxservq->tx_pending); ++ ++ //_exit_critical_ex(&phwxmit->sta_queue->lock, &irqL0); ++ ++ goto exit; ++ } ++ ++ sta_plist = get_next(sta_plist); ++ ++ } ++ ++ //_exit_critical_ex(&phwxmit->sta_queue->lock, &irqL0); ++ ++ } ++ ++exit: ++ ++ _exit_critical_bh(&pxmitpriv->lock, &irqL0); ++ ++_func_exit_; ++ ++ return pxmitframe; ++} ++ ++#if 1 ++struct tx_servq *rtw_get_sta_pending(_adapter *padapter, struct sta_info *psta, sint up, u8 *ac) ++{ ++ struct tx_servq *ptxservq; ++ ++_func_enter_; ++ ++ switch (up) ++ { ++ case 1: ++ case 2: ++ ptxservq = &(psta->sta_xmitpriv.bk_q); ++ *(ac) = 3; ++ RT_TRACE(_module_rtl871x_xmit_c_,_drv_info_,("rtw_get_sta_pending : BK \n")); ++ break; ++ ++ case 4: ++ case 5: ++ ptxservq = &(psta->sta_xmitpriv.vi_q); ++ *(ac) = 1; ++ RT_TRACE(_module_rtl871x_xmit_c_,_drv_info_,("rtw_get_sta_pending : VI\n")); ++ break; ++ ++ case 6: ++ case 7: ++ ptxservq = &(psta->sta_xmitpriv.vo_q); ++ *(ac) = 0; ++ RT_TRACE(_module_rtl871x_xmit_c_,_drv_info_,("rtw_get_sta_pending : VO \n")); ++ break; ++ ++ case 0: ++ case 3: ++ default: ++ ptxservq = &(psta->sta_xmitpriv.be_q); ++ *(ac) = 2; ++ RT_TRACE(_module_rtl871x_xmit_c_,_drv_info_,("rtw_get_sta_pending : BE \n")); ++ break; ++ ++ } ++ ++_func_exit_; ++ ++ return ptxservq; ++} ++#else ++__inline static struct tx_servq *rtw_get_sta_pending ++ (_adapter *padapter, _queue **ppstapending, struct sta_info *psta, sint up) ++{ ++ struct tx_servq *ptxservq; ++ struct hw_xmit *phwxmits = padapter->xmitpriv.hwxmits; ++ ++_func_enter_; ++ ++#ifdef CONFIG_RTL8711 ++ ++ if(IS_MCAST(psta->hwaddr)) ++ { ++ ptxservq = &(psta->sta_xmitpriv.be_q); // we will use be_q to queue bc/mc frames in BCMC_stainfo ++ *ppstapending = &padapter->xmitpriv.bm_pending; ++ } ++ else ++#endif ++ { ++ switch (up) ++ { ++ case 1: ++ case 2: ++ ptxservq = &(psta->sta_xmitpriv.bk_q); ++ *ppstapending = &padapter->xmitpriv.bk_pending; ++ (phwxmits+3)->accnt++; ++ RT_TRACE(_module_rtl871x_xmit_c_,_drv_info_,("rtw_get_sta_pending : BK \n")); ++ break; ++ ++ case 4: ++ case 5: ++ ptxservq = &(psta->sta_xmitpriv.vi_q); ++ *ppstapending = &padapter->xmitpriv.vi_pending; ++ (phwxmits+1)->accnt++; ++ RT_TRACE(_module_rtl871x_xmit_c_,_drv_info_,("rtw_get_sta_pending : VI\n")); ++ break; ++ ++ case 6: ++ case 7: ++ ptxservq = &(psta->sta_xmitpriv.vo_q); ++ *ppstapending = &padapter->xmitpriv.vo_pending; ++ (phwxmits+0)->accnt++; ++ RT_TRACE(_module_rtl871x_xmit_c_,_drv_info_,("rtw_get_sta_pending : VO \n")); ++ break; ++ ++ case 0: ++ case 3: ++ default: ++ ptxservq = &(psta->sta_xmitpriv.be_q); ++ *ppstapending = &padapter->xmitpriv.be_pending; ++ (phwxmits+2)->accnt++; ++ RT_TRACE(_module_rtl871x_xmit_c_,_drv_info_,("rtw_get_sta_pending : BE \n")); ++ break; ++ ++ } ++ ++ } ++ ++_func_exit_; ++ ++ return ptxservq; ++} ++#endif ++ ++/* ++ * Will enqueue pxmitframe to the proper queue, ++ * and indicate it to xx_pending list..... ++ */ ++s32 rtw_xmit_classifier(_adapter *padapter, struct xmit_frame *pxmitframe) ++{ ++ //_irqL irqL0; ++ u8 ac_index; ++ struct sta_info *psta; ++ struct tx_servq *ptxservq; ++ struct pkt_attrib *pattrib = &pxmitframe->attrib; ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ struct hw_xmit *phwxmits = padapter->xmitpriv.hwxmits; ++ sint res = _SUCCESS; ++ ++_func_enter_; ++ ++ if (pattrib->psta) { ++ psta = pattrib->psta; ++ } else { ++ psta = rtw_get_stainfo(pstapriv, pattrib->ra); ++ } ++ ++ if (psta == NULL) { ++ res = _FAIL; ++ RT_TRACE(_module_rtl871x_xmit_c_,_drv_err_,("rtw_xmit_classifier: psta == NULL\n")); ++ goto exit; ++ } ++ ++ ptxservq = rtw_get_sta_pending(padapter, psta, pattrib->priority, (u8 *)(&ac_index)); ++ ++ //_enter_critical(&pstapending->lock, &irqL0); ++ ++ if (rtw_is_list_empty(&ptxservq->tx_pending)) { ++ rtw_list_insert_tail(&ptxservq->tx_pending, get_list_head(phwxmits[ac_index].sta_queue)); ++ } ++ ++ //_enter_critical(&ptxservq->sta_pending.lock, &irqL1); ++ ++ rtw_list_insert_tail(&pxmitframe->list, get_list_head(&ptxservq->sta_pending)); ++ ptxservq->qcnt++; ++ phwxmits[ac_index].accnt++; ++ ++ //_exit_critical(&ptxservq->sta_pending.lock, &irqL1); ++ ++ //_exit_critical(&pstapending->lock, &irqL0); ++ ++exit: ++ ++_func_exit_; ++ ++ return res; ++} ++ ++void rtw_alloc_hwxmits(_adapter *padapter) ++{ ++ struct hw_xmit *hwxmits; ++ struct xmit_priv *pxmitpriv = &padapter->xmitpriv; ++ ++ pxmitpriv->hwxmit_entry = HWXMIT_ENTRY; ++ ++ pxmitpriv->hwxmits = (struct hw_xmit *)rtw_zmalloc(sizeof (struct hw_xmit) * pxmitpriv->hwxmit_entry); ++ ++ hwxmits = pxmitpriv->hwxmits; ++ ++ if(pxmitpriv->hwxmit_entry == 5) ++ { ++ //pxmitpriv->bmc_txqueue.head = 0; ++ //hwxmits[0] .phwtxqueue = &pxmitpriv->bmc_txqueue; ++ hwxmits[0] .sta_queue = &pxmitpriv->bm_pending; ++ ++ //pxmitpriv->vo_txqueue.head = 0; ++ //hwxmits[1] .phwtxqueue = &pxmitpriv->vo_txqueue; ++ hwxmits[1] .sta_queue = &pxmitpriv->vo_pending; ++ ++ //pxmitpriv->vi_txqueue.head = 0; ++ //hwxmits[2] .phwtxqueue = &pxmitpriv->vi_txqueue; ++ hwxmits[2] .sta_queue = &pxmitpriv->vi_pending; ++ ++ //pxmitpriv->bk_txqueue.head = 0; ++ //hwxmits[3] .phwtxqueue = &pxmitpriv->bk_txqueue; ++ hwxmits[3] .sta_queue = &pxmitpriv->bk_pending; ++ ++ //pxmitpriv->be_txqueue.head = 0; ++ //hwxmits[4] .phwtxqueue = &pxmitpriv->be_txqueue; ++ hwxmits[4] .sta_queue = &pxmitpriv->be_pending; ++ ++ } ++ else if(pxmitpriv->hwxmit_entry == 4) ++ { ++ ++ //pxmitpriv->vo_txqueue.head = 0; ++ //hwxmits[0] .phwtxqueue = &pxmitpriv->vo_txqueue; ++ hwxmits[0] .sta_queue = &pxmitpriv->vo_pending; ++ ++ //pxmitpriv->vi_txqueue.head = 0; ++ //hwxmits[1] .phwtxqueue = &pxmitpriv->vi_txqueue; ++ hwxmits[1] .sta_queue = &pxmitpriv->vi_pending; ++ ++ //pxmitpriv->be_txqueue.head = 0; ++ //hwxmits[2] .phwtxqueue = &pxmitpriv->be_txqueue; ++ hwxmits[2] .sta_queue = &pxmitpriv->be_pending; ++ ++ //pxmitpriv->bk_txqueue.head = 0; ++ //hwxmits[3] .phwtxqueue = &pxmitpriv->bk_txqueue; ++ hwxmits[3] .sta_queue = &pxmitpriv->bk_pending; ++ } ++ else ++ { ++ ++ ++ } ++ ++ ++} ++ ++void rtw_free_hwxmits(_adapter *padapter) ++{ ++ struct hw_xmit *hwxmits; ++ struct xmit_priv *pxmitpriv = &padapter->xmitpriv; ++ ++ hwxmits = pxmitpriv->hwxmits; ++ if(hwxmits) ++ rtw_mfree((u8 *)hwxmits, (sizeof (struct hw_xmit) * pxmitpriv->hwxmit_entry)); ++} ++ ++void rtw_init_hwxmits(struct hw_xmit *phwxmit, sint entry) ++{ ++ sint i; ++_func_enter_; ++ for(i = 0; i < entry; i++, phwxmit++) ++ { ++ //_rtw_spinlock_init(&phwxmit->xmit_lock); ++ //_rtw_init_listhead(&phwxmit->pending); ++ //phwxmit->txcmdcnt = 0; ++ phwxmit->accnt = 0; ++ } ++_func_exit_; ++} ++ ++ ++ ++#ifdef CONFIG_BR_EXT ++int rtw_br_client_tx(_adapter *padapter, struct sk_buff **pskb) ++{ ++ struct sk_buff *skb = *pskb; ++ struct xmit_priv *pxmitpriv = &padapter->xmitpriv; ++ _irqL irqL; ++ //if(check_fwstate(pmlmepriv, WIFI_STATION_STATE|WIFI_ADHOC_STATE) == _TRUE) ++ { ++ void dhcp_flag_bcast(_adapter *priv, struct sk_buff *skb); ++ int res, is_vlan_tag=0, i, do_nat25=1; ++ unsigned short vlan_hdr=0; ++ void *br_port = NULL; ++ ++ //mac_clone_handle_frame(priv, skb); ++ ++#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35)) ++ br_port = padapter->pnetdev->br_port; ++#else // (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35)) ++ rcu_read_lock(); ++ br_port = rcu_dereference(padapter->pnetdev->rx_handler_data); ++ rcu_read_unlock(); ++#endif // (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35)) ++ _enter_critical_bh(&padapter->br_ext_lock, &irqL); ++ if ( !(skb->data[0] & 1) && ++ br_port && ++ memcmp(skb->data+MACADDRLEN, padapter->br_mac, MACADDRLEN) && ++ *((unsigned short *)(skb->data+MACADDRLEN*2)) != __constant_htons(ETH_P_8021Q) && ++ *((unsigned short *)(skb->data+MACADDRLEN*2)) == __constant_htons(ETH_P_IP) && ++ !memcmp(padapter->scdb_mac, skb->data+MACADDRLEN, MACADDRLEN) && padapter->scdb_entry) { ++ memcpy(skb->data+MACADDRLEN, GET_MY_HWADDR(padapter), MACADDRLEN); ++ padapter->scdb_entry->ageing_timer = jiffies; ++ _exit_critical_bh(&padapter->br_ext_lock, &irqL); ++ } ++ else ++ //if (!priv->pmib->ethBrExtInfo.nat25_disable) ++ { ++// if (priv->dev->br_port && ++// !memcmp(skb->data+MACADDRLEN, priv->br_mac, MACADDRLEN)) { ++#if 1 ++ if (*((unsigned short *)(skb->data+MACADDRLEN*2)) == __constant_htons(ETH_P_8021Q)) { ++ is_vlan_tag = 1; ++ vlan_hdr = *((unsigned short *)(skb->data+MACADDRLEN*2+2)); ++ for (i=0; i<6; i++) ++ *((unsigned short *)(skb->data+MACADDRLEN*2+2-i*2)) = *((unsigned short *)(skb->data+MACADDRLEN*2-2-i*2)); ++ skb_pull(skb, 4); ++ } ++ ++ if (!memcmp(skb->data+MACADDRLEN, padapter->br_mac, MACADDRLEN) && ++ (*((unsigned short *)(skb->data+MACADDRLEN*2)) == __constant_htons(ETH_P_IP))) ++ memcpy(padapter->br_ip, skb->data+WLAN_ETHHDR_LEN+12, 4); ++ ++ if (*((unsigned short *)(skb->data+MACADDRLEN*2)) == __constant_htons(ETH_P_IP)) { ++ if (memcmp(padapter->scdb_mac, skb->data+MACADDRLEN, MACADDRLEN)) { ++ void *scdb_findEntry(_adapter *priv, unsigned char *macAddr, unsigned char *ipAddr); ++ ++ if ((padapter->scdb_entry = (struct nat25_network_db_entry *)scdb_findEntry(padapter, ++ skb->data+MACADDRLEN, skb->data+WLAN_ETHHDR_LEN+12)) != NULL) { ++ memcpy(padapter->scdb_mac, skb->data+MACADDRLEN, MACADDRLEN); ++ memcpy(padapter->scdb_ip, skb->data+WLAN_ETHHDR_LEN+12, 4); ++ padapter->scdb_entry->ageing_timer = jiffies; ++ do_nat25 = 0; ++ } ++ } ++ else { ++ if (padapter->scdb_entry) { ++ padapter->scdb_entry->ageing_timer = jiffies; ++ do_nat25 = 0; ++ } ++ else { ++ memset(padapter->scdb_mac, 0, MACADDRLEN); ++ memset(padapter->scdb_ip, 0, 4); ++ } ++ } ++ } ++ _exit_critical_bh(&padapter->br_ext_lock, &irqL); ++#endif // 1 ++ if (do_nat25) ++ { ++ int nat25_db_handle(_adapter *priv, struct sk_buff *skb, int method); ++ if (nat25_db_handle(padapter, skb, NAT25_CHECK) == 0) { ++ struct sk_buff *newskb; ++ ++ if (is_vlan_tag) { ++ skb_push(skb, 4); ++ for (i=0; i<6; i++) ++ *((unsigned short *)(skb->data+i*2)) = *((unsigned short *)(skb->data+4+i*2)); ++ *((unsigned short *)(skb->data+MACADDRLEN*2)) = __constant_htons(ETH_P_8021Q); ++ *((unsigned short *)(skb->data+MACADDRLEN*2+2)) = vlan_hdr; ++ } ++ ++ newskb = skb_copy(skb, GFP_ATOMIC); ++ if (newskb == NULL) { ++ //priv->ext_stats.tx_drops++; ++ DEBUG_ERR("TX DROP: skb_copy fail!\n"); ++ //goto stop_proc; ++ return -1; ++ } ++ dev_kfree_skb_any(skb); ++ ++ *pskb = skb = newskb; ++ if (is_vlan_tag) { ++ vlan_hdr = *((unsigned short *)(skb->data+MACADDRLEN*2+2)); ++ for (i=0; i<6; i++) ++ *((unsigned short *)(skb->data+MACADDRLEN*2+2-i*2)) = *((unsigned short *)(skb->data+MACADDRLEN*2-2-i*2)); ++ skb_pull(skb, 4); ++ } ++ } ++ ++ if (skb_is_nonlinear(skb)) ++ DEBUG_ERR("%s(): skb_is_nonlinear!!\n", __FUNCTION__); ++ ++ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 18)) ++ res = skb_linearize(skb, GFP_ATOMIC); ++#else // (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 18)) ++ res = skb_linearize(skb); ++#endif // (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 18)) ++ if (res < 0) { ++ DEBUG_ERR("TX DROP: skb_linearize fail!\n"); ++ //goto free_and_stop; ++ return -1; ++ } ++ ++ res = nat25_db_handle(padapter, skb, NAT25_INSERT); ++ if (res < 0) { ++ if (res == -2) { ++ //priv->ext_stats.tx_drops++; ++ DEBUG_ERR("TX DROP: nat25_db_handle fail!\n"); ++ //goto free_and_stop; ++ return -1; ++ ++ } ++ // we just print warning message and let it go ++ DEBUG_WARN("%s()-%d: nat25_db_handle INSERT Warning!\n", __FUNCTION__, __LINE__); ++ //return -1; // return -1 will cause system crash on 2011/08/30! ++ return 0; ++ } ++ } ++ ++ memcpy(skb->data+MACADDRLEN, GET_MY_HWADDR(padapter), MACADDRLEN); ++ ++ dhcp_flag_bcast(padapter, skb); ++ ++ if (is_vlan_tag) { ++ skb_push(skb, 4); ++ for (i=0; i<6; i++) ++ *((unsigned short *)(skb->data+i*2)) = *((unsigned short *)(skb->data+4+i*2)); ++ *((unsigned short *)(skb->data+MACADDRLEN*2)) = __constant_htons(ETH_P_8021Q); ++ *((unsigned short *)(skb->data+MACADDRLEN*2+2)) = vlan_hdr; ++ } ++ } ++#if 0 ++ else{ ++ if (*((unsigned short *)(skb->data+MACADDRLEN*2)) == __constant_htons(ETH_P_8021Q)) { ++ is_vlan_tag = 1; ++ } ++ ++ if(is_vlan_tag){ ++ if(ICMPV6_MCAST_MAC(skb->data) && ICMPV6_PROTO1A_VALN(skb->data)){ ++ memcpy(skb->data+MACADDRLEN, GET_MY_HWADDR(padapter), MACADDRLEN); ++ } ++ }else ++ { ++ if(ICMPV6_MCAST_MAC(skb->data) && ICMPV6_PROTO1A(skb->data)){ ++ memcpy(skb->data+MACADDRLEN, GET_MY_HWADDR(padapter), MACADDRLEN); ++ } ++ } ++ } ++#endif // 0 ++ ++ // check if SA is equal to our MAC ++ if (memcmp(skb->data+MACADDRLEN, GET_MY_HWADDR(padapter), MACADDRLEN)) { ++ //priv->ext_stats.tx_drops++; ++ DEBUG_ERR("TX DROP: untransformed frame SA:%02X%02X%02X%02X%02X%02X!\n", ++ skb->data[6],skb->data[7],skb->data[8],skb->data[9],skb->data[10],skb->data[11]); ++ //goto free_and_stop; ++ return -1; ++ } ++ } ++ return 0; ++} ++#endif // CONFIG_BR_EXT ++ ++static void do_queue_select(_adapter *padapter, struct pkt_attrib *pattrib) ++{ ++ u8 qsel; ++ ++ qsel = pattrib->priority; ++ RT_TRACE(_module_rtl871x_xmit_c_,_drv_info_,("### do_queue_select priority=%d ,qsel = %d\n",pattrib->priority ,qsel)); ++ ++#ifdef CONFIG_CONCURRENT_MODE ++ if (check_fwstate(&padapter->mlmepriv, WIFI_AP_STATE) == _TRUE) ++ qsel = 7;// ++#endif ++ ++ pattrib->qsel = qsel; ++} ++ ++/* ++ * The main transmit(tx) entry ++ * ++ * Return ++ * 1 enqueue ++ * 0 success, hardware will handle this xmit frame(packet) ++ * <0 fail ++ */ ++s32 rtw_xmit(_adapter *padapter, _pkt **ppkt) ++{ ++#ifdef CONFIG_AP_MODE ++ _irqL irqL0; ++#endif ++ struct xmit_priv *pxmitpriv = &padapter->xmitpriv; ++ struct xmit_frame *pxmitframe = NULL; ++#ifdef CONFIG_BR_EXT ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ void *br_port = NULL; ++#endif // CONFIG_BR_EXT ++ ++ s32 res; ++ ++ ++ pxmitframe = rtw_alloc_xmitframe(pxmitpriv); ++ if (pxmitframe == NULL) { ++ RT_TRACE(_module_xmit_osdep_c_, _drv_err_, ("rtw_xmit: no more pxmitframe\n")); ++ #ifdef DBG_TX_DROP_FRAME ++ DBG_871X("DBG_TX_DROP_FRAME %s no more pxmitframe\n", __FUNCTION__); ++ #endif ++ return -1; ++ } ++ ++#ifdef CONFIG_BR_EXT ++ ++#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35)) ++ br_port = padapter->pnetdev->br_port; ++#else // (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35)) ++ rcu_read_lock(); ++ br_port = rcu_dereference(padapter->pnetdev->rx_handler_data); ++ rcu_read_unlock(); ++#endif // (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35)) ++ ++ if( br_port && check_fwstate(pmlmepriv, WIFI_STATION_STATE|WIFI_ADHOC_STATE) == _TRUE) ++ { ++ res = rtw_br_client_tx(padapter, ppkt); ++ if (res == -1) ++ return -1; ++ } ++ ++#endif // CONFIG_BR_EXT ++ ++ res = update_attrib(padapter, *ppkt, &pxmitframe->attrib); ++ if (res == _FAIL) { ++ RT_TRACE(_module_xmit_osdep_c_, _drv_err_, ("rtw_xmit: update attrib fail\n")); ++ #ifdef DBG_TX_DROP_FRAME ++ DBG_871X("DBG_TX_DROP_FRAME %s update attrib fail\n", __FUNCTION__); ++ #endif ++ rtw_free_xmitframe(pxmitpriv, pxmitframe); ++ return -1; ++ } ++ pxmitframe->pkt = *ppkt; ++ ++ rtw_led_control(padapter, LED_CTL_TX); ++ ++ do_queue_select(padapter, &pxmitframe->attrib); ++ ++#ifdef CONFIG_AP_MODE ++ _enter_critical_bh(&pxmitpriv->lock, &irqL0); ++ if(xmitframe_enqueue_for_sleeping_sta(padapter, pxmitframe) == _TRUE) ++ { ++ _exit_critical_bh(&pxmitpriv->lock, &irqL0); ++ return 1; ++ } ++ _exit_critical_bh(&pxmitpriv->lock, &irqL0); ++#endif ++ ++ if (padapter->HalFunc.hal_xmit(padapter, pxmitframe) == _FALSE) ++ return 1; ++ ++ return 0; ++} ++ ++#ifdef CONFIG_TDLS ++void process_enqueue_frame(_adapter *padapter, struct xmit_frame *pxmitframe, struct sta_info *psta) ++{ ++ _irqL irqL; ++ struct sta_info *ptdls_sta=NULL; ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ struct pkt_attrib *pattrib = &pxmitframe->attrib; ++ ptdls_sta=rtw_get_stainfo(pstapriv, pattrib->dst); ++ ++ //enqueue frame for TDLS sleeping STA ++ rtw_list_delete(&pxmitframe->list); ++ _enter_critical_bh(&ptdls_sta->sleep_q.lock, &irqL); ++ rtw_list_insert_tail(&pxmitframe->list, get_list_head(&ptdls_sta->sleep_q)); ++ ptdls_sta->sleepq_len++; ++ ++ //indicate 4-AC queue bit in TDLS peer traffic indication ++ switch(pattrib->priority) ++ { ++ case 1: ++ case 2: ++ ptdls_sta->uapsd_bk = ptdls_sta->uapsd_bk | BIT(0); ++ break; ++ case 4: ++ case 5: ++ ptdls_sta->uapsd_vi = ptdls_sta->uapsd_vi | BIT(0); ++ break; ++ case 6: ++ case 7: ++ ptdls_sta->uapsd_vo = ptdls_sta->uapsd_vo | BIT(0); ++ break; ++ case 0: ++ case 3: ++ default: ++ ptdls_sta->uapsd_be = ptdls_sta->uapsd_be | BIT(0); ++ break; ++ } ++ ++ ptdls_sta->sleepq_ac_len++; ++ ++ _exit_critical_bh(&ptdls_sta->sleep_q.lock, &irqL); ++ ++} ++ ++sint xmitframe_enqueue_for_tdls_sleeping_sta(_adapter *padapter, struct xmit_frame *pxmitframe) ++{ ++ sint ret=_FALSE; ++ ++ _irqL irqL; ++ struct sta_info *ptdls_sta=NULL; ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ struct pkt_attrib *pattrib = &pxmitframe->attrib; ++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); ++ int i; ++ ++ ptdls_sta=rtw_get_stainfo(pstapriv, pattrib->dst); ++ if(ptdls_sta==NULL){ ++ return ret; ++ }else if(ptdls_sta->tdls_sta_state&TDLS_LINKED_STATE){ ++ ++ if(pattrib->triggered==1) ++ { ++ ret = _TRUE; ++ return ret; ++ } ++ ++ _enter_critical_bh(&ptdls_sta->sleep_q.lock, &irqL); ++ ++ if(ptdls_sta->state&WIFI_SLEEP_STATE) ++ { ++ rtw_list_delete(&pxmitframe->list); ++ ++ //_enter_critical_bh(&psta->sleep_q.lock, &irqL); ++ ++ rtw_list_insert_tail(&pxmitframe->list, get_list_head(&ptdls_sta->sleep_q)); ++ ++ ptdls_sta->sleepq_len++; ++ ptdls_sta->sleepq_ac_len++; ++ ++ //indicate 4-AC queue bit in TDLS peer traffic indication ++ switch(pattrib->priority) ++ { ++ case 1: ++ case 2: ++ ptdls_sta->uapsd_bk = ptdls_sta->uapsd_bk | BIT(1); ++ break; ++ case 4: ++ case 5: ++ ptdls_sta->uapsd_vi = ptdls_sta->uapsd_vi | BIT(1); ++ break; ++ case 6: ++ case 7: ++ ptdls_sta->uapsd_vo = ptdls_sta->uapsd_vo | BIT(1); ++ break; ++ case 0: ++ case 3: ++ default: ++ ptdls_sta->uapsd_be = ptdls_sta->uapsd_be | BIT(1); ++ break; ++ } ++ ++ if(ptdls_sta->sleepq_len==1) ++ { ++ //transmit TDLS PTI via AP ++ ptdls_sta->option=2; ++ rtw_tdls_cmd(padapter, ptdls_sta->hwaddr, TDLS_SD_PTI); ++ } ++ ret = _TRUE; ++ ++ } ++ ++ _exit_critical_bh(&ptdls_sta->sleep_q.lock, &irqL); ++ } ++ ++ return ret; ++ ++} ++#endif ++ ++#ifdef CONFIG_AP_MODE ++ ++sint xmitframe_enqueue_for_sleeping_sta(_adapter *padapter, struct xmit_frame *pxmitframe) ++{ ++ _irqL irqL; ++ sint ret=_FALSE; ++ struct sta_info *psta=NULL; ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ struct pkt_attrib *pattrib = &pxmitframe->attrib; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ sint bmcst = IS_MCAST(pattrib->ra); ++#ifdef CONFIG_TDLS ++ struct tdls_info *ptdlsinfo = &padapter->tdlsinfo; ++ ++ if( ptdlsinfo->setup_state & TDLS_LINKED_STATE ) ++ { ++ ret = xmitframe_enqueue_for_tdls_sleeping_sta(padapter, pxmitframe); ++ return ret; ++ } ++#endif //CONFIG_TDLS ++ ++ if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _FALSE) ++ return ret; ++ ++ if(pattrib->psta) ++ { ++ psta = pattrib->psta; ++ } ++ else ++ { ++ psta=rtw_get_stainfo(pstapriv, pattrib->ra); ++ } ++ ++ if(psta==NULL) ++ return ret; ++ ++ if(pattrib->triggered==1) ++ { ++ //DBG_871X("directly xmit pspoll_triggered packet\n"); ++ ++ //pattrib->triggered=0; ++ ++ if(bmcst) ++ pattrib->qsel = 0x11;//HIQ ++ ++ ++ return ret; ++ } ++ ++ ++ if(bmcst) ++ { ++ _enter_critical_bh(&psta->sleep_q.lock, &irqL); ++ ++ if(pstapriv->sta_dz_bitmap)//if anyone sta is in ps mode ++ { ++ //pattrib->qsel = 0x11;//HIQ ++ ++ rtw_list_delete(&pxmitframe->list); ++ ++ //_enter_critical_bh(&psta->sleep_q.lock, &irqL); ++ ++ rtw_list_insert_tail(&pxmitframe->list, get_list_head(&psta->sleep_q)); ++ ++ psta->sleepq_len++; ++ ++ pstapriv->tim_bitmap |= BIT(0);// ++ pstapriv->sta_dz_bitmap |= BIT(0); ++ ++ //DBG_871X("enqueue, sq_len=%d, tim=%x\n", psta->sleepq_len, pstapriv->tim_bitmap); ++ ++ update_beacon(padapter, _TIM_IE_, NULL, _FALSE);//tx bc/mc packets after upate bcn ++ ++ //_exit_critical_bh(&psta->sleep_q.lock, &irqL); ++ ++ ret = _TRUE; ++ ++ } ++ ++ _exit_critical_bh(&psta->sleep_q.lock, &irqL); ++ ++ return ret; ++ ++ } ++ ++ ++ _enter_critical_bh(&psta->sleep_q.lock, &irqL); ++ ++ if(psta->state&WIFI_SLEEP_STATE) ++ { ++ u8 wmmps_ac=0; ++ ++ if(pstapriv->sta_dz_bitmap&BIT(psta->aid)) ++ { ++ rtw_list_delete(&pxmitframe->list); ++ ++ //_enter_critical_bh(&psta->sleep_q.lock, &irqL); ++ ++ rtw_list_insert_tail(&pxmitframe->list, get_list_head(&psta->sleep_q)); ++ ++ psta->sleepq_len++; ++ ++ switch(pattrib->priority) ++ { ++ case 1: ++ case 2: ++ wmmps_ac = psta->uapsd_bk&BIT(0); ++ break; ++ case 4: ++ case 5: ++ wmmps_ac = psta->uapsd_vi&BIT(0); ++ break; ++ case 6: ++ case 7: ++ wmmps_ac = psta->uapsd_vo&BIT(0); ++ break; ++ case 0: ++ case 3: ++ default: ++ wmmps_ac = psta->uapsd_be&BIT(0); ++ break; ++ } ++ ++ if(wmmps_ac) ++ psta->sleepq_ac_len++; ++ ++ if(((psta->has_legacy_ac) && (!wmmps_ac)) ||((!psta->has_legacy_ac)&&(wmmps_ac))) ++ { ++ pstapriv->tim_bitmap |= BIT(psta->aid); ++ ++ //DBG_871X("enqueue, sq_len=%d, tim=%x\n", psta->sleepq_len, pstapriv->tim_bitmap); ++ ++ if(psta->sleepq_len==1) ++ { ++ //DBG_871X("sleepq_len==1, update BCNTIM\n"); ++ //upate BCN for TIM IE ++ update_beacon(padapter, _TIM_IE_, NULL, _FALSE); ++ } ++ } ++ ++ //_exit_critical_bh(&psta->sleep_q.lock, &irqL); ++ ++ //if(psta->sleepq_len > (NR_XMITFRAME>>3)) ++ //{ ++ // wakeup_sta_to_xmit(padapter, psta); ++ //} ++ ++ ret = _TRUE; ++ ++ } ++ ++ } ++ ++ _exit_critical_bh(&psta->sleep_q.lock, &irqL); ++ ++ return ret; ++ ++} ++ ++static void dequeue_xmitframes_to_sleeping_queue(_adapter *padapter, struct sta_info *psta, _queue *pframequeue) ++{ ++ _list *plist, *phead; ++ u8 ac_index; ++ struct tx_servq *ptxservq; ++ struct pkt_attrib *pattrib; ++ struct xmit_frame *pxmitframe; ++ struct hw_xmit *phwxmits = padapter->xmitpriv.hwxmits; ++ ++ phead = get_list_head(pframequeue); ++ plist = get_next(phead); ++ ++ while (rtw_end_of_queue_search(phead, plist) == _FALSE) ++ { ++ pxmitframe = LIST_CONTAINOR(plist, struct xmit_frame, list); ++ ++ plist = get_next(plist); ++ ++ xmitframe_enqueue_for_sleeping_sta(padapter, pxmitframe); ++ ++ pattrib = &pxmitframe->attrib; ++ ++ ptxservq = rtw_get_sta_pending(padapter, psta, pattrib->priority, (u8 *)(&ac_index)); ++ ++ ptxservq->qcnt--; ++ phwxmits[ac_index].accnt--; ++ } ++ ++} ++ ++void stop_sta_xmit(_adapter *padapter, struct sta_info *psta) ++{ ++ _irqL irqL0; ++ struct sta_info *psta_bmc; ++ struct sta_xmit_priv *pstaxmitpriv; ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ struct xmit_priv *pxmitpriv = &padapter->xmitpriv; ++ ++ pstaxmitpriv = &psta->sta_xmitpriv; ++ ++ //for BC/MC Frames ++ psta_bmc = rtw_get_bcmc_stainfo(padapter); ++ ++ ++ _enter_critical_bh(&pxmitpriv->lock, &irqL0); ++ ++ psta->state |= WIFI_SLEEP_STATE; ++ ++#ifdef CONFIG_TDLS ++ if( !(psta->tdls_sta_state & TDLS_LINKED_STATE) ) ++#endif //CONFIG_TDLS ++ pstapriv->sta_dz_bitmap |= BIT(psta->aid); ++ ++ ++ ++ dequeue_xmitframes_to_sleeping_queue(padapter, psta, &pstaxmitpriv->vo_q.sta_pending); ++ rtw_list_delete(&(pstaxmitpriv->vo_q.tx_pending)); ++ ++ ++ dequeue_xmitframes_to_sleeping_queue(padapter, psta, &pstaxmitpriv->vi_q.sta_pending); ++ rtw_list_delete(&(pstaxmitpriv->vi_q.tx_pending)); ++ ++ ++ dequeue_xmitframes_to_sleeping_queue(padapter, psta, &pstaxmitpriv->be_q.sta_pending); ++ rtw_list_delete(&(pstaxmitpriv->be_q.tx_pending)); ++ ++ ++ dequeue_xmitframes_to_sleeping_queue(padapter, psta, &pstaxmitpriv->bk_q.sta_pending); ++ rtw_list_delete(&(pstaxmitpriv->bk_q.tx_pending)); ++ ++#ifdef CONFIG_TDLS ++ if( !(psta->tdls_sta_state & TDLS_LINKED_STATE) ) ++ { ++ if( psta_bmc != NULL ) ++ { ++#endif //CONFIG_TDLS ++ ++ ++ //for BC/MC Frames ++ pstaxmitpriv = &psta_bmc->sta_xmitpriv; ++ dequeue_xmitframes_to_sleeping_queue(padapter, psta_bmc, &pstaxmitpriv->be_q.sta_pending); ++ rtw_list_delete(&(pstaxmitpriv->be_q.tx_pending)); ++ ++ ++#ifdef CONFIG_TDLS ++ } ++ } ++#endif //CONFIG_TDLS ++ _exit_critical_bh(&pxmitpriv->lock, &irqL0); ++ ++ ++} ++ ++void wakeup_sta_to_xmit(_adapter *padapter, struct sta_info *psta) ++{ ++ _irqL irqL; ++ u8 update_mask=0, wmmps_ac=0; ++ struct sta_info *psta_bmc; ++ _list *xmitframe_plist, *xmitframe_phead; ++ struct xmit_frame *pxmitframe=NULL; ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ ++ _enter_critical_bh(&psta->sleep_q.lock, &irqL); ++ ++ xmitframe_phead = get_list_head(&psta->sleep_q); ++ xmitframe_plist = get_next(xmitframe_phead); ++ ++ while ((rtw_end_of_queue_search(xmitframe_phead, xmitframe_plist)) == _FALSE) ++ { ++ pxmitframe = LIST_CONTAINOR(xmitframe_plist, struct xmit_frame, list); ++ ++ xmitframe_plist = get_next(xmitframe_plist); ++ ++ rtw_list_delete(&pxmitframe->list); ++ ++ switch(pxmitframe->attrib.priority) ++ { ++ case 1: ++ case 2: ++ wmmps_ac = psta->uapsd_bk&BIT(1); ++ break; ++ case 4: ++ case 5: ++ wmmps_ac = psta->uapsd_vi&BIT(1); ++ break; ++ case 6: ++ case 7: ++ wmmps_ac = psta->uapsd_vo&BIT(1); ++ break; ++ case 0: ++ case 3: ++ default: ++ wmmps_ac = psta->uapsd_be&BIT(1); ++ break; ++ } ++ ++ psta->sleepq_len--; ++ if(psta->sleepq_len>0) ++ pxmitframe->attrib.mdata = 1; ++ else ++ pxmitframe->attrib.mdata = 0; ++ ++ if(wmmps_ac) ++ { ++ psta->sleepq_ac_len--; ++ if(psta->sleepq_ac_len>0) ++ { ++ pxmitframe->attrib.mdata = 1; ++ pxmitframe->attrib.eosp = 0; ++ } ++ else ++ { ++ pxmitframe->attrib.mdata = 0; ++ pxmitframe->attrib.eosp = 1; ++ } ++ } ++ ++ pxmitframe->attrib.triggered = 1; ++ ++ _exit_critical_bh(&psta->sleep_q.lock, &irqL); ++ if(padapter->HalFunc.hal_xmit(padapter, pxmitframe) == _TRUE) ++ { ++ rtw_os_xmit_complete(padapter, pxmitframe); ++ } ++ _enter_critical_bh(&psta->sleep_q.lock, &irqL); ++ ++ if(psta->sleepq_len==0) ++ { ++#ifdef CONFIG_TDLS ++ if( psta->tdls_sta_state & TDLS_LINKED_STATE ) ++ { ++ if(psta->state&WIFI_SLEEP_STATE) ++ psta->state ^= WIFI_SLEEP_STATE; ++ ++ _exit_critical_bh(&psta->sleep_q.lock, &irqL); ++ return; ++ } ++#endif ++ pstapriv->tim_bitmap &= ~BIT(psta->aid); ++ ++ //DBG_871X("wakeup to xmit, qlen==0, update_BCNTIM, tim=%x\n", pstapriv->tim_bitmap); ++ //upate BCN for TIM IE ++ //update_BCNTIM(padapter); ++ update_mask = BIT(0); ++ ++ if(psta->state&WIFI_SLEEP_STATE) ++ psta->state ^= WIFI_SLEEP_STATE; ++ ++ pstapriv->sta_dz_bitmap &= ~BIT(psta->aid); ++ ++ } ++ ++ } ++ ++ _exit_critical_bh(&psta->sleep_q.lock, &irqL); ++ ++ ++ //for BC/MC Frames ++ psta_bmc = rtw_get_bcmc_stainfo(padapter); ++ if(!psta_bmc) ++ return; ++ ++ if((pstapriv->sta_dz_bitmap&0xfffe) == 0x0)//no any sta in ps mode ++ { ++ _enter_critical_bh(&psta_bmc->sleep_q.lock, &irqL); ++ ++ xmitframe_phead = get_list_head(&psta_bmc->sleep_q); ++ xmitframe_plist = get_next(xmitframe_phead); ++ ++ while ((rtw_end_of_queue_search(xmitframe_phead, xmitframe_plist)) == _FALSE) ++ { ++ pxmitframe = LIST_CONTAINOR(xmitframe_plist, struct xmit_frame, list); ++ ++ xmitframe_plist = get_next(xmitframe_plist); ++ ++ rtw_list_delete(&pxmitframe->list); ++ ++ psta_bmc->sleepq_len--; ++ if(psta_bmc->sleepq_len>0) ++ pxmitframe->attrib.mdata = 1; ++ else ++ pxmitframe->attrib.mdata = 0; ++ ++ ++ pxmitframe->attrib.triggered = 1; ++ ++ _exit_critical_bh(&psta_bmc->sleep_q.lock, &irqL); ++ if(padapter->HalFunc.hal_xmit(padapter, pxmitframe) == _TRUE) ++ { ++ rtw_os_xmit_complete(padapter, pxmitframe); ++ } ++ _enter_critical_bh(&psta_bmc->sleep_q.lock, &irqL); ++ ++ ++ if(psta_bmc->sleepq_len==0) ++ { ++ pstapriv->tim_bitmap &= ~BIT(0); ++ pstapriv->sta_dz_bitmap &= ~BIT(0); ++ ++ //DBG_871X("wakeup to xmit, qlen==0, update_BCNTIM, tim=%x\n", pstapriv->tim_bitmap); ++ //upate BCN for TIM IE ++ //update_BCNTIM(padapter); ++ update_mask |= BIT(1); ++ } ++ ++ } ++ ++ _exit_critical_bh(&psta_bmc->sleep_q.lock, &irqL); ++ ++ } ++ ++ ++ if(update_mask) ++ { ++ //update_BCNTIM(padapter); ++ update_beacon(padapter, _TIM_IE_, NULL, _FALSE); ++ } ++ ++} ++ ++void xmit_delivery_enabled_frames(_adapter *padapter, struct sta_info *psta) ++{ ++ _irqL irqL; ++ u8 wmmps_ac=0; ++ _list *xmitframe_plist, *xmitframe_phead; ++ struct xmit_frame *pxmitframe=NULL; ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ ++ _enter_critical_bh(&psta->sleep_q.lock, &irqL); ++ ++ xmitframe_phead = get_list_head(&psta->sleep_q); ++ xmitframe_plist = get_next(xmitframe_phead); ++ ++ while ((rtw_end_of_queue_search(xmitframe_phead, xmitframe_plist)) == _FALSE) ++ { ++ pxmitframe = LIST_CONTAINOR(xmitframe_plist, struct xmit_frame, list); ++ ++ xmitframe_plist = get_next(xmitframe_plist); ++ ++ switch(pxmitframe->attrib.priority) ++ { ++ case 1: ++ case 2: ++ wmmps_ac = psta->uapsd_bk&BIT(1); ++ break; ++ case 4: ++ case 5: ++ wmmps_ac = psta->uapsd_vi&BIT(1); ++ break; ++ case 6: ++ case 7: ++ wmmps_ac = psta->uapsd_vo&BIT(1); ++ break; ++ case 0: ++ case 3: ++ default: ++ wmmps_ac = psta->uapsd_be&BIT(1); ++ break; ++ } ++ ++ if(!wmmps_ac) ++ continue; ++ ++ rtw_list_delete(&pxmitframe->list); ++ ++ psta->sleepq_len--; ++ psta->sleepq_ac_len--; ++ ++ if(psta->sleepq_ac_len>0) ++ { ++ pxmitframe->attrib.mdata = 1; ++ pxmitframe->attrib.eosp = 0; ++ } ++ else ++ { ++ pxmitframe->attrib.mdata = 0; ++ pxmitframe->attrib.eosp = 1; ++ } ++ ++ pxmitframe->attrib.triggered = 1; ++ ++ if(padapter->HalFunc.hal_xmit(padapter, pxmitframe) == _TRUE) ++ { ++ rtw_os_xmit_complete(padapter, pxmitframe); ++ } ++ ++ if((psta->sleepq_ac_len==0) && (!psta->has_legacy_ac) && (wmmps_ac)) ++ { ++#ifdef CONFIG_TDLS ++ if(psta->tdls_sta_state & TDLS_LINKED_STATE ) ++ { ++ _exit_critical_bh(&psta->sleep_q.lock, &irqL); ++ return; ++ } ++#endif //CONFIG_TDLS ++ pstapriv->tim_bitmap &= ~BIT(psta->aid); ++ ++ //DBG_871X("wakeup to xmit, qlen==0, update_BCNTIM, tim=%x\n", pstapriv->tim_bitmap); ++ //upate BCN for TIM IE ++ //update_BCNTIM(padapter); ++ update_beacon(padapter, _TIM_IE_, NULL, _FALSE); ++ //update_mask = BIT(0); ++ } ++ ++ } ++ ++ _exit_critical_bh(&psta->sleep_q.lock, &irqL); ++ ++} ++ ++#endif ++ +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/hal/hal_init.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/hal/hal_init.c 2013-07-26 19:36:05.000000000 +0000 +@@ -0,0 +1,120 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++ ++#define _HAL_INIT_C_ ++#include ++#include ++#include ++#include ++ ++#include ++ ++#ifdef CONFIG_SDIO_HCI ++ #include ++#elif defined(CONFIG_USB_HCI) ++ #include ++#endif ++ ++void intf_chip_configure(_adapter *padapter) ++{ ++ if(padapter->HalFunc.intf_chip_configure) ++ padapter->HalFunc.intf_chip_configure(padapter); ++} ++ ++void intf_read_chip_info(_adapter *padapter) ++{ ++ if(padapter->HalFunc.read_adapter_info) ++ padapter->HalFunc.read_adapter_info(padapter); ++} ++ ++void intf_read_chip_version(_adapter *padapter) ++{ ++ if(padapter->HalFunc.read_chip_version) ++ padapter->HalFunc.read_chip_version(padapter); ++} ++ ++void rtw_dm_init(_adapter *padapter) ++{ ++ if(padapter->HalFunc.dm_init) ++ padapter->HalFunc.dm_init(padapter); ++} ++ ++void rtw_sw_led_init(_adapter *padapter) ++{ ++ if(padapter->HalFunc.InitSwLeds) ++ padapter->HalFunc.InitSwLeds(padapter); ++} ++ ++void rtw_sw_led_deinit(_adapter *padapter) ++{ ++ if(padapter->HalFunc.DeInitSwLeds) ++ padapter->HalFunc.DeInitSwLeds(padapter); ++} ++ ++uint rtw_hal_init(_adapter *padapter) ++{ ++ uint status = _SUCCESS; ++ ++ padapter->hw_init_completed=_FALSE; ++ ++ status = padapter->HalFunc.hal_init(padapter); ++ ++ if(status == _SUCCESS){ ++ padapter->hw_init_completed = _TRUE; ++ } ++ else{ ++ padapter->hw_init_completed = _FALSE; ++ RT_TRACE(_module_hal_init_c_,_drv_err_,("rtw_hal_init: hal__init fail\n")); ++ } ++ ++ RT_TRACE(_module_hal_init_c_,_drv_err_,("-rtl871x_hal_init:status=0x%x\n",status)); ++ ++ return status; ++ ++} ++ ++uint rtw_hal_deinit(_adapter *padapter) ++{ ++ uint status = _SUCCESS; ++ ++_func_enter_; ++ ++ status = padapter->HalFunc.hal_deinit(padapter); ++ ++ if(status == _SUCCESS){ ++ padapter->hw_init_completed = _FALSE; ++ } ++ else ++ { ++ RT_TRACE(_module_hal_init_c_,_drv_err_,("\n rtw_hal_deinit: hal_init fail\n")); ++ } ++ ++_func_exit_; ++ ++ return status; ++ ++} ++#ifdef DBG_CONFIG_ERROR_DETECT ++void rtw_sreset_init(_adapter *padapter) ++{ ++ if(padapter->HalFunc.sreset_init_value) ++ padapter->HalFunc.sreset_init_value(padapter); ++} ++#endif +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/hal/rtl8192c/rtl8192c_cmd.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/hal/rtl8192c/rtl8192c_cmd.c 2013-07-26 19:36:05.000000000 +0000 +@@ -0,0 +1,1361 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ++******************************************************************************/ ++#define _RTL8192C_CMD_C_ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++ ++#if 0 ++static BOOLEAN ++CheckWriteMSG( ++ IN PADAPTER Adapter, ++ IN u8 BoxNum ++) ++{ ++ u8 valHMETFR; ++ BOOLEAN Result = _FALSE; ++ ++ valHMETFR = rtw_read8(Adapter, REG_HMETFR); ++ ++ //DbgPrint("CheckWriteH2C(): Reg[0x%2x] = %x\n",REG_HMETFR, valHMETFR); ++ ++ if(((valHMETFR>>BoxNum)&BIT0) == 1) ++ Result = _TRUE; ++ ++ return Result; ++ ++} ++ ++static BOOLEAN CheckFwReadLastMSG( ++ IN PADAPTER Adapter, ++ IN u8 BoxNum ++) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ u8 valHMETFR, valMCUTST_1; ++ BOOLEAN Result = _FALSE; ++ ++ valHMETFR = rtw_read8(Adapter, REG_HMETFR); ++ valMCUTST_1 = rtw_read8(Adapter, (REG_MCUTST_1+BoxNum)); ++ ++ //DbgPrint("REG[%x] = %x, REG[%x] = %x\n", ++ // REG_HMETFR, valHMETFR, REG_MCUTST_1+BoxNum, valMCUTST_1 ); ++ ++ // Do not seperate to 91C and 88C, we use the same setting. Suggested by SD4 Filen. 2009.12.03. ++ if(IS_NORMAL_CHIP(pHalData->VersionID)) ++ { ++ if(((valHMETFR>>BoxNum)&BIT0) == 0) ++ Result = _TRUE; ++ } ++ else ++ { ++ if((((valHMETFR>>BoxNum)&BIT0) == 0) && (valMCUTST_1 == 0)) ++ { ++ Result = _TRUE; ++ } ++ } ++ ++ return Result; ++} ++#endif ++ ++ ++#define RTL92C_MAX_H2C_BOX_NUMS 4 ++#define RTL92C_MAX_CMD_LEN 5 ++#define MESSAGE_BOX_SIZE 4 ++#define EX_MESSAGE_BOX_SIZE 2 ++ ++static u8 _is_fw_read_cmd_down(_adapter* padapter, u8 isvern, u8 msgbox_num) ++{ ++ u8 read_down = _FALSE; ++ int retry_cnts = 100; ++ ++ u8 valid; ++ ++// DBG_8192C(" _is_fw_read_cmd_down ,isnormal_chip(%x),reg_1cc(%x),msg_box(%d)...\n",isvern,rtw_read8(padapter,REG_HMETFR),msgbox_num); ++ ++ do{ ++ valid = rtw_read8(padapter,REG_HMETFR) & BIT(msgbox_num); ++ if(isvern){ ++ if(0 == valid ){ ++ read_down = _TRUE; ++ } ++ } ++ else{ ++ if((0 == valid) && (0 == rtw_read8(padapter, REG_MCUTST_1+msgbox_num))){ ++ read_down = _TRUE; ++ } ++ } ++ }while( (!read_down) && (retry_cnts--)); ++ ++ return read_down; ++ ++} ++ ++ ++/***************************************** ++* H2C Msg format : ++*| 31 - 8 |7 | 6 - 0 | ++*| h2c_msg |Ext_bit |CMD_ID | ++* ++******************************************/ ++int rtl8192c_FillH2CCmd(_adapter* padapter, u8 ElementID, u32 CmdLen, u8* pCmdBuffer) ++{ ++#if 1 ++ u8 bcmd_down = _FALSE; ++ int retry_cnts = 100; ++ u8 h2c_box_num; ++ u32 msgbox_addr; ++ u32 msgbox_ex_addr; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); ++ u8 isnchip =IS_NORMAL_CHIP(pHalData->VersionID); ++ u32 h2c_cmd = 0; ++ u16 h2c_cmd_ex = 0; ++ int ret = _FAIL; ++ ++ _func_enter_; ++ ++ if(!pCmdBuffer){ ++ goto exit; ++ } ++ if(CmdLen > RTL92C_MAX_CMD_LEN){ ++ goto exit; ++ } ++ //pay attention to if race condition happened in H2C cmd setting. ++ do{ ++ h2c_box_num = pHalData->LastHMEBoxNum; ++ ++ if(!_is_fw_read_cmd_down(padapter, isnchip, h2c_box_num)){ ++ DBG_8192C(" fw read cmd failed...\n"); ++ goto exit; ++ } ++ ++ if(CmdLen<=3) ++ { ++ _rtw_memcpy((u8*)(&h2c_cmd)+1, pCmdBuffer, CmdLen ); ++ } ++ else{ ++ _rtw_memcpy((u8*)(&h2c_cmd_ex), pCmdBuffer, EX_MESSAGE_BOX_SIZE); ++ _rtw_memcpy((u8*)(&h2c_cmd)+1, pCmdBuffer+2,( CmdLen-EX_MESSAGE_BOX_SIZE)); ++ *(u8*)(&h2c_cmd) |= BIT(7); ++ } ++ ++ *(u8*)(&h2c_cmd) |= ElementID; ++ ++ if(h2c_cmd & BIT(7)){ ++ msgbox_ex_addr = REG_HMEBOX_EXT_0 + (h2c_box_num *EX_MESSAGE_BOX_SIZE); ++ h2c_cmd_ex = cpu_to_le16( h2c_cmd_ex ); ++ rtw_write16(padapter, msgbox_ex_addr, h2c_cmd_ex); ++ } ++ msgbox_addr =REG_HMEBOX_0 + (h2c_box_num *MESSAGE_BOX_SIZE); ++ h2c_cmd = cpu_to_le32( h2c_cmd ); ++ rtw_write32(padapter,msgbox_addr, h2c_cmd); ++ ++ if(!isnchip){//for Test chip ++ if(! (rtw_read8(padapter, REG_HMETFR) & BIT(h2c_box_num))){ ++ DBG_8192C("Chip test - check fw write failed, write again..\n"); ++ continue; ++ } ++ // Fill H2C protection register. ++ rtw_write8(padapter,REG_MCUTST_1+h2c_box_num, 0xFF); ++ } ++ bcmd_down = _TRUE; ++ ++ // DBG_8192C("MSG_BOX:%d,CmdLen(%d), reg:0x%x =>h2c_cmd:0x%x, reg:0x%x =>h2c_cmd_ex:0x%x ..\n" ++ // ,pHalData->LastHMEBoxNum ,CmdLen,msgbox_addr,h2c_cmd,msgbox_ex_addr,h2c_cmd_ex); ++ ++ pHalData->LastHMEBoxNum = (h2c_box_num+1) % RTL92C_MAX_H2C_BOX_NUMS ; ++ ++ }while((!bcmd_down) && (retry_cnts--)); ++/* ++ if(bcmd_down) ++ DBG_8192C("H2C Cmd exe down. \n" ); ++ else ++ DBG_8192C("H2C Cmd exe failed. \n" ); ++*/ ++ ret = _SUCCESS; ++ _func_exit_; ++ ++#else ++ u8 BoxNum; ++ u16 BOXReg, BOXExtReg; ++ u8 BoxContent[4], BoxExtContent[2]; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); ++ u8 BufIndex=0; ++ u8 bWriteSucess = _FALSE; ++ u8 IsFwRead = _FALSE; ++ u8 WaitH2cLimmit = 100; ++ ++ u32 h2c_cmd = 0; ++ u16 h2c_cmd_ex = 0; ++ ++_func_enter_; ++ ++ //DBG_8192C("FillH2CCmd : ElementID=%d \n",ElementID); ++ ++ while(!bWriteSucess) ++ { ++ // 2. Find the last BOX number which has been writen. ++ BoxNum = pHalData->LastHMEBoxNum; ++ switch(BoxNum) ++ { ++ case 0: ++ BOXReg = REG_HMEBOX_0; ++ BOXExtReg = REG_HMEBOX_EXT_0; ++ break; ++ case 1: ++ BOXReg = REG_HMEBOX_1; ++ BOXExtReg = REG_HMEBOX_EXT_1; ++ break; ++ case 2: ++ BOXReg = REG_HMEBOX_2; ++ BOXExtReg = REG_HMEBOX_EXT_2; ++ break; ++ case 3: ++ BOXReg = REG_HMEBOX_3; ++ BOXExtReg = REG_HMEBOX_EXT_3; ++ break; ++ default: ++ break; ++ } ++ ++ // 3. Check if the box content is empty. ++ IsFwRead = CheckFwReadLastMSG(padapter, BoxNum); ++ while(!IsFwRead) ++ { ++ //wait until Fw read ++ WaitH2cLimmit--; ++ if(WaitH2cLimmit == 0) ++ { ++ DBG_8192C("FillH2CCmd92C(): Wating too long for FW read clear HMEBox(%d)!!!\n", BoxNum); ++ break; ++ } ++ rtw_msleep_os(10); //us ++ IsFwRead = CheckFwReadLastMSG(padapter, BoxNum); ++ //U1btmp = PlatformEFIORead1Byte(Adapter, 0x1BF); ++ //RT_TRACE(COMP_CMD, DBG_LOUD, ("FillH2CCmd92C(): Wating for FW read clear HMEBox(%d)!!! 0x1BF = %2x\n", BoxNum, U1btmp)); ++ } ++ ++ // If Fw has not read the last H2C cmd, break and give up this H2C. ++ if(!IsFwRead) ++ { ++ DBG_8192C("FillH2CCmd92C(): Write H2C register BOX[%d] fail!!!!! Fw do not read. \n", BoxNum); ++ break; ++ } ++ ++ // 4. Fill the H2C cmd into box ++ _rtw_memset(BoxContent, 0, sizeof(BoxContent)); ++ _rtw_memset(BoxExtContent, 0, sizeof(BoxExtContent)); ++ ++ BoxContent[0] = ElementID; // Fill element ID ++ ++ //DBG_8192C("FillH2CCmd92C():Write ElementID BOXReg(%4x) = %2x \n", BOXReg, ElementID); ++ ++ switch(CmdLen) ++ { ++ case 1: ++ { ++ BoxContent[0] &= ~(BIT7); ++ _rtw_memcpy((u8*)(BoxContent)+1, pCmdBuffer+BufIndex, 1); ++ rtw_write32(padapter, BOXReg, *((u32*)BoxContent)); ++ h2c_cmd = *((u32*)BoxContent); ++ break; ++ } ++ case 2: ++ { ++ BoxContent[0] &= ~(BIT7); ++ _rtw_memcpy((u8*)(BoxContent)+1, pCmdBuffer+BufIndex, 2); ++ rtw_write32(padapter, BOXReg, *((u32*)BoxContent)); ++ h2c_cmd = *((u32*)BoxContent); ++ break; ++ } ++ case 3: ++ { ++ BoxContent[0] &= ~(BIT7); ++ _rtw_memcpy((u8*)(BoxContent)+1, pCmdBuffer+BufIndex, 3); ++ rtw_write32(padapter, BOXReg, *((u32*)BoxContent)); ++ h2c_cmd = *((u32*)BoxContent); ++ break; ++ } ++ case 4: ++ { ++ BoxContent[0] |= (BIT7); ++ _rtw_memcpy((u8*)(BoxExtContent), pCmdBuffer+BufIndex, 2); ++ _rtw_memcpy((u8*)(BoxContent)+1, pCmdBuffer+BufIndex+2, 2); ++ rtw_write16(padapter, BOXExtReg, *((u16*)BoxExtContent)); ++ rtw_write32(padapter, BOXReg, *((u32*)BoxContent)); ++ h2c_cmd = *((u32*)BoxContent); ++ h2c_cmd_ex = *((u32*)BoxExtContent); ++ break; ++ } ++ case 5: ++ { ++ BoxContent[0] |= (BIT7); ++ _rtw_memcpy((u8*)(BoxExtContent), pCmdBuffer+BufIndex, 2); ++ _rtw_memcpy((u8*)(BoxContent)+1, pCmdBuffer+BufIndex+2, 3); ++ rtw_write16(padapter, BOXExtReg, *((u16*)BoxExtContent)); ++ rtw_write32(padapter, BOXReg, *((u32*)BoxContent)); ++ h2c_cmd = *((u32*)BoxContent); ++ h2c_cmd_ex = *((u32*)BoxExtContent); ++ break; ++ } ++ default: ++ break; ++ ++ } ++ ++ ++ DBG_8192C("MSG_BOX:%d,CmdLen(%d), reg:0x%x =>h2c_cmd:0x%x, reg:0x%x =>h2c_cmd_ex:0x%x ..\n" ++ ,pHalData->LastHMEBoxNum ,CmdLen,BOXReg,h2c_cmd,BOXExtReg,h2c_cmd_ex); ++ ++ //DBG_8192C("FillH2CCmd(): BoxExtContent=0x%x\n", *(u16*)BoxExtContent); ++ //DBG_8192C("FillH2CCmd(): BoxContent=0x%x\n", *(u32*)BoxContent); ++ ++ if(IS_NORMAL_CHIP(pHalData->VersionID)) ++ { ++ // 5. Normal chip does not need to check if the H2C cmd has be written successfully. ++ bWriteSucess = _TRUE; ++ } ++ else ++ { ++ // 5. Check if the H2C cmd has be written successfully. ++ bWriteSucess = CheckWriteMSG(padapter, BoxNum); ++ if(!bWriteSucess) //If not then write again. ++ continue; ++ ++ //6. Fill H2C protection register. ++ ++ rtw_write8(padapter, REG_MCUTST_1+BoxNum, 0xFF); ++ //RT_TRACE(COMP_CMD, DBG_LOUD, ("FillH2CCmd92C():Write Reg(%4x) = 0xFF \n", REG_MCUTST_1+BoxNum)); ++ } ++ ++ // Record the next BoxNum ++ pHalData->LastHMEBoxNum = BoxNum+1; ++ if(pHalData->LastHMEBoxNum == 4) // loop to 0 ++ pHalData->LastHMEBoxNum = 0; ++ ++ //DBG_8192C("FillH2CCmd92C():pHalData->LastHMEBoxNum = %d\n", pHalData->LastHMEBoxNum); ++ ++ } ++ ++_func_exit_; ++ ++#endif ++ ++#ifdef CONFIG_CONCURRENT_MODE ++ //_exit_critical_mutex(padapter->ph2c_fwcmd_mutex, NULL); ++#endif ++exit: ++ return ret; ++ ++} ++ ++u8 rtl8192c_h2c_msg_hdl(_adapter *padapter, unsigned char *pbuf) ++{ ++ u8 ElementID, CmdLen; ++ u8 *pCmdBuffer; ++ struct cmd_msg_parm *pcmdmsg; ++ ++ if(!pbuf) ++ return H2C_PARAMETERS_ERROR; ++ ++ pcmdmsg = (struct cmd_msg_parm*)pbuf; ++ ElementID = pcmdmsg->eid; ++ CmdLen = pcmdmsg->sz; ++ pCmdBuffer = pcmdmsg->buf; ++ ++ rtl8192c_FillH2CCmd(padapter, ElementID, CmdLen, pCmdBuffer); ++ ++ return H2C_SUCCESS; ++} ++ ++#if defined(CONFIG_AUTOSUSPEND) && defined(SUPPORT_HW_RFOFF_DETECTED) ++u8 rtl8192c_set_FwSelectSuspend_cmd(_adapter *padapter ,u8 bfwpoll, u16 period) ++{ ++ u8 res=_SUCCESS; ++ struct H2C_SS_RFOFF_PARAM param; ++ DBG_8192C("==>%s bfwpoll(%x)\n",__FUNCTION__,bfwpoll); ++ param.gpio_period = period;//Polling GPIO_11 period time ++ param.ROFOn = (_TRUE == bfwpoll)?1:0; ++ rtl8192c_FillH2CCmd(padapter, SELECTIVE_SUSPEND_ROF_CMD, sizeof(param), (u8*)(¶m)); ++ return res; ++} ++#endif //CONFIG_AUTOSUSPEND && SUPPORT_HW_RFOFF_DETECTED ++ ++u8 rtl8192c_set_rssi_cmd(_adapter*padapter, u8 *param) ++{ ++ u8 res=_SUCCESS; ++ ++_func_enter_; ++ ++ *((u32*) param ) = cpu_to_le32( *((u32*) param ) ); ++ ++ rtl8192c_FillH2CCmd(padapter, RSSI_SETTING_EID, 3, param); ++ ++_func_exit_; ++ ++ return res; ++} ++ ++u8 rtl8192c_set_raid_cmd(_adapter*padapter, u32 mask, u8 arg) ++{ ++ u8 buf[5]; ++ u8 res=_SUCCESS; ++ ++_func_enter_; ++ ++ _rtw_memset(buf, 0, 5); ++ mask = cpu_to_le32( mask ); ++ _rtw_memcpy(buf, &mask, 4); ++ buf[4] = arg; ++ ++ rtl8192c_FillH2CCmd(padapter, MACID_CONFIG_EID, 5, buf); ++ ++_func_exit_; ++ ++ return res; ++ ++} ++ ++u8 rtl8192c_set_ext_macid_period_cmd(_adapter*padapter, u8 period) ++{ ++ u8 ext_macid_period=0; ++ u8 res=_SUCCESS; ++ ++_func_enter_; ++ ++ ext_macid_period=period; ++ ++ rtl8192c_FillH2CCmd(padapter, EXT_MACID_PERIOD_EID, 1, &ext_macid_period); ++ ++_func_exit_; ++ ++ return res; ++ ++} ++ ++u8 rtl8192c_set_raid64_cmd(_adapter*padapter, u32 mask, u8 arg) ++{ ++ u8 buf[5]; ++ u8 res=_SUCCESS; ++ ++_func_enter_; ++ ++ _rtw_memset(buf, 0, 5); ++ mask = cpu_to_le32( mask ); ++ _rtw_memcpy(buf, &mask, 4); ++ buf[4] = arg; ++ ++ rtl8192c_FillH2CCmd(padapter, MACID64_CONFIG_EID, 5, buf); ++ ++_func_exit_; ++ ++ return res; ++ ++} ++//bitmap[0:27] = tx_rate_bitmap ++//bitmap[28:31]= Rate Adaptive id ++//arg[0:4] = macid ++//arg[5] = Short GI ++void rtl8192c_Add_RateATid(PADAPTER pAdapter, u32 bitmap, u8 arg, u8 mac_id) ++{ ++ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); ++ ++ if(pHalData->fw_ractrl == _TRUE) ++ { ++ DBG_8192C("%s() pHalData->fw_ractrl == _TRUE\n",__FUNCTION__); ++#ifdef SUPPORT_64_STA ++ if(mac_id >=FW_CTRL_MACID){ ++ rtl8192c_set_ext_macid_period_cmd(pAdapter,20); ++ rtl8192c_set_raid64_cmd(pAdapter, bitmap, arg); ++ DBG_8192C("%s() rtl8192c_set_raid64_cmd, bitmap=0x%x, arg =0x%x\n",__FUNCTION__,bitmap,arg); ++ } ++ else ++#endif //SUPPORT_64_STA ++ { ++ rtl8192c_set_raid_cmd(pAdapter, bitmap, arg); ++ DBG_8192C("%s() rtl8192c_set_raid_cmd, bitmap=0x%x, arg =0x%x\n",__FUNCTION__,bitmap,arg); ++ } ++ ++ } ++ else ++ { ++ u8 macid, init_rate, shortGIrate=_FALSE; ++ ++ init_rate = get_highest_rate_idx(bitmap&0x0fffffff)&0x3f; ++ ++ macid = arg&0x1f; ++ ++ shortGIrate = (arg&BIT(5)) ? _TRUE:_FALSE; ++ ++ if (shortGIrate==_TRUE) ++ init_rate |= BIT(6); ++ ++ rtw_write8(pAdapter, (REG_INIDATA_RATE_SEL+macid), (u8)init_rate); ++ } ++ ++} ++ ++void rtl8192c_set_FwPwrMode_cmd(_adapter*padapter, u8 Mode) ++{ ++ SETPWRMODE_PARM H2CSetPwrMode; ++ struct pwrctrl_priv *pwrpriv = &padapter->pwrctrlpriv; ++ ++_func_enter_; ++ ++ DBG_871X("%s(): Mode = %d, SmartPS = %d\n", __FUNCTION__,Mode,pwrpriv->smart_ps); ++ ++ H2CSetPwrMode.Mode = Mode; ++ ++ H2CSetPwrMode.SmartPS = pwrpriv->smart_ps; ++ ++ H2CSetPwrMode.BcnPassTime = 1;//pPSC->RegMaxLPSAwakeIntvl; ++ ++ rtl8192c_FillH2CCmd(padapter, SET_PWRMODE_EID, sizeof(H2CSetPwrMode), (u8 *)&H2CSetPwrMode); ++ ++_func_exit_; ++} ++ ++void ConstructBeacon(_adapter *padapter, u8 *pframe, u32 *pLength) ++{ ++ struct rtw_ieee80211_hdr *pwlanhdr; ++ u16 *fctrl; ++ u32 rate_len, pktlen; ++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network); ++ u8 bc_addr[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; ++ ++ ++ //DBG_871X("%s\n", __FUNCTION__); ++ ++ pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; ++ ++ fctrl = &(pwlanhdr->frame_ctl); ++ *(fctrl) = 0; ++ ++ _rtw_memcpy(pwlanhdr->addr1, bc_addr, ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr2, myid(&(padapter->eeprompriv)), ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(cur_network), ETH_ALEN); ++ ++ SetSeqNum(pwlanhdr, 0/*pmlmeext->mgnt_seq*/); ++ //pmlmeext->mgnt_seq++; ++ SetFrameSubType(pframe, WIFI_BEACON); ++ ++ pframe += sizeof(struct rtw_ieee80211_hdr_3addr); ++ pktlen = sizeof (struct rtw_ieee80211_hdr_3addr); ++ ++ //timestamp will be inserted by hardware ++ pframe += 8; ++ pktlen += 8; ++ ++ // beacon interval: 2 bytes ++ _rtw_memcpy(pframe, (unsigned char *)(rtw_get_beacon_interval_from_ie(cur_network->IEs)), 2); ++ ++ pframe += 2; ++ pktlen += 2; ++ ++ // capability info: 2 bytes ++ _rtw_memcpy(pframe, (unsigned char *)(rtw_get_capability_from_ie(cur_network->IEs)), 2); ++ ++ pframe += 2; ++ pktlen += 2; ++ ++ if( (pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE) ++ { ++ //DBG_871X("ie len=%d\n", cur_network->IELength); ++ pktlen += cur_network->IELength - sizeof(NDIS_802_11_FIXED_IEs); ++ _rtw_memcpy(pframe, cur_network->IEs+sizeof(NDIS_802_11_FIXED_IEs), pktlen); ++ ++ goto _ConstructBeacon; ++ } ++ ++ //below for ad-hoc mode ++ ++ // SSID ++ pframe = rtw_set_ie(pframe, _SSID_IE_, cur_network->Ssid.SsidLength, cur_network->Ssid.Ssid, &pktlen); ++ ++ // supported rates... ++ rate_len = rtw_get_rateset_len(cur_network->SupportedRates); ++ pframe = rtw_set_ie(pframe, _SUPPORTEDRATES_IE_, ((rate_len > 8)? 8: rate_len), cur_network->SupportedRates, &pktlen); ++ ++ // DS parameter set ++ pframe = rtw_set_ie(pframe, _DSSET_IE_, 1, (unsigned char *)&(cur_network->Configuration.DSConfig), &pktlen); ++ ++ if( (pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE) ++ { ++ u32 ATIMWindow; ++ // IBSS Parameter Set... ++ //ATIMWindow = cur->Configuration.ATIMWindow; ++ ATIMWindow = 0; ++ pframe = rtw_set_ie(pframe, _IBSS_PARA_IE_, 2, (unsigned char *)(&ATIMWindow), &pktlen); ++ } ++ ++ ++ //todo: ERP IE ++ ++ ++ // EXTERNDED SUPPORTED RATE ++ if (rate_len > 8) ++ { ++ pframe = rtw_set_ie(pframe, _EXT_SUPPORTEDRATES_IE_, (rate_len - 8), (cur_network->SupportedRates + 8), &pktlen); ++ } ++ ++ ++ //todo:HT for adhoc ++ ++_ConstructBeacon: ++ ++ if ((pktlen + TXDESC_SIZE) > 512) ++ { ++ DBG_871X("beacon frame too large\n"); ++ return; ++ } ++ ++ *pLength = pktlen; ++ ++ //DBG_871X("%s bcn_sz=%d\n", __FUNCTION__, pktlen); ++ ++} ++ ++void ConstructPSPoll(_adapter *padapter, u8 *pframe, u32 *pLength) ++{ ++ struct rtw_ieee80211_hdr *pwlanhdr; ++ u16 *fctrl; ++ u32 pktlen; ++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ ++ //DBG_871X("%s\n", __FUNCTION__); ++ ++ pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; ++ ++ // Frame control. ++ fctrl = &(pwlanhdr->frame_ctl); ++ *(fctrl) = 0; ++ SetPwrMgt(fctrl); ++ SetFrameSubType(pframe, WIFI_PSPOLL); ++ ++ // AID. ++ SetDuration(pframe, (pmlmeinfo->aid | 0xc000)); ++ ++ // BSSID. ++ _rtw_memcpy(pwlanhdr->addr1, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); ++ ++ // TA. ++ _rtw_memcpy(pwlanhdr->addr2, myid(&(padapter->eeprompriv)), ETH_ALEN); ++ ++ *pLength = 16; ++} ++ ++void ConstructNullFunctionData(_adapter *padapter, u8 *pframe, u32 *pLength, u8 *StaAddr, BOOLEAN bForcePowerSave) ++{ ++ struct rtw_ieee80211_hdr *pwlanhdr; ++ u16 *fctrl; ++ u32 pktlen; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct wlan_network *cur_network = &pmlmepriv->cur_network; ++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ ++ //DBG_871X("%s:%d\n", __FUNCTION__, bForcePowerSave); ++ ++ pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; ++ ++ fctrl = &(pwlanhdr->frame_ctl); ++ *(fctrl) = 0; ++ if (bForcePowerSave) ++ { ++ SetPwrMgt(fctrl); ++ } ++ ++ switch(cur_network->network.InfrastructureMode) ++ { ++ case Ndis802_11Infrastructure: ++ SetToDs(fctrl); ++ _rtw_memcpy(pwlanhdr->addr1, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr2, myid(&(padapter->eeprompriv)), ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr3, StaAddr, ETH_ALEN); ++ break; ++ case Ndis802_11APMode: ++ SetFrDs(fctrl); ++ _rtw_memcpy(pwlanhdr->addr1, StaAddr, ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr2, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr3, myid(&(padapter->eeprompriv)), ETH_ALEN); ++ break; ++ case Ndis802_11IBSS: ++ default: ++ _rtw_memcpy(pwlanhdr->addr1, StaAddr, ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr2, myid(&(padapter->eeprompriv)), ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); ++ break; ++ } ++ ++ SetSeqNum(pwlanhdr, 0); ++ ++ SetFrameSubType(pframe, WIFI_DATA_NULL); ++ ++ pframe += sizeof(struct rtw_ieee80211_hdr_3addr); ++ pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); ++ ++ *pLength = pktlen; ++} ++ ++void ConstructProbeRsp(_adapter *padapter, u8 *pframe, u32 *pLength, u8 *StaAddr, BOOLEAN bHideSSID) ++{ ++ struct rtw_ieee80211_hdr *pwlanhdr; ++ u16 *fctrl; ++ u8 *mac, *bssid; ++ u32 pktlen; ++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network); ++ ++ ++ //DBG_871X("%s\n", __FUNCTION__); ++ ++ pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; ++ ++ mac = myid(&(padapter->eeprompriv)); ++ bssid = cur_network->MacAddress; ++ ++ fctrl = &(pwlanhdr->frame_ctl); ++ *(fctrl) = 0; ++ _rtw_memcpy(pwlanhdr->addr1, StaAddr, ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr2, mac, ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr3, bssid, ETH_ALEN); ++ ++ SetSeqNum(pwlanhdr, 0); ++ SetFrameSubType(fctrl, WIFI_PROBERSP); ++ ++ pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); ++ pframe += pktlen; ++ ++ if(cur_network->IELength>MAX_IE_SZ) ++ return; ++ ++ _rtw_memcpy(pframe, cur_network->IEs, cur_network->IELength); ++ pframe += cur_network->IELength; ++ pktlen += cur_network->IELength; ++ ++ *pLength = pktlen; ++} ++ ++// ++// Description: In normal chip, we should send some packet to Hw which will be used by Fw ++// in FW LPS mode. The function is to fill the Tx descriptor of this packets, then ++// Fw can tell Hw to send these packet derectly. ++// Added by tynli. 2009.10.15. ++// ++static VOID ++FillFakeTxDescriptor92C( ++ IN PADAPTER Adapter, ++ IN u8* pDesc, ++ IN u32 BufferLen, ++ IN BOOLEAN IsPsPoll ++) ++{ ++ struct tx_desc *ptxdesc = (struct tx_desc *)pDesc; ++ ++ // Clear all status ++ _rtw_memset(pDesc, 0, 32); ++ ++ //offset 0 ++ ptxdesc->txdw0 |= cpu_to_le32( OWN | FSG | LSG); //own, bFirstSeg, bLastSeg; ++ ++ ptxdesc->txdw0 |= cpu_to_le32(((TXDESC_SIZE+OFFSET_SZ)<txdw0 |= cpu_to_le32(BufferLen&0x0000ffff); // Buffer size + command header ++ ++ //offset 4 ++ ptxdesc->txdw1 |= cpu_to_le32((QSLT_MGNT<txdw1 |= cpu_to_le32(NAVUSEHDR); ++ } ++ else ++ { ++ ptxdesc->txdw4 |= cpu_to_le32(BIT(7)); // Hw set sequence number ++ ptxdesc->txdw3 |= cpu_to_le32((8 <<28)); //set bit3 to 1. Suugested by TimChen. 2009.12.29. ++ } ++ ++ //offset 16 ++ ptxdesc->txdw4 |= cpu_to_le32(BIT(8));//driver uses rate ++ ++#ifdef CONFIG_USB_HCI ++ // USB interface drop packet if the checksum of descriptor isn't correct. ++ // Using this checksum can let hardware recovery from packet bulk out error (e.g. Cancel URC, Bulk out error.). ++ rtl8192cu_cal_txdesc_chksum(ptxdesc); ++#endif ++ ++ //RT_PRINT_DATA(COMP_CMD, DBG_TRACE, "TxFillCmdDesc8192C(): H2C Tx Cmd Content ----->\n", pDesc, TX_DESC_SIZE); ++} ++ ++// To check if reserved page content is destroyed by beacon beacuse beacon is too large. ++// 2010.06.23. Added by tynli. ++VOID ++CheckFwRsvdPageContent( ++ IN PADAPTER Adapter ++) ++{ ++ HAL_DATA_TYPE* pHalData = GET_HAL_DATA(Adapter); ++ u32 MaxBcnPageNum; ++ ++ if(pHalData->FwRsvdPageStartOffset != 0) ++ { ++ /*MaxBcnPageNum = PageNum_128(pMgntInfo->MaxBeaconSize); ++ RT_ASSERT((MaxBcnPageNum <= pHalData->FwRsvdPageStartOffset), ++ ("CheckFwRsvdPageContent(): The reserved page content has been"\ ++ "destroyed by beacon!!! MaxBcnPageNum(%d) FwRsvdPageStartOffset(%d)\n!", ++ MaxBcnPageNum, pHalData->FwRsvdPageStartOffset));*/ ++ } ++} ++ ++// ++// Description: Fill the reserved packets that FW will use to RSVD page. ++// Now we just send 4 types packet to rsvd page. ++// (1)Beacon, (2)Ps-poll, (3)Null data, (4)ProbeRsp. ++// Input: ++// bDLFinished - FALSE: At the first time we will send all the packets as a large packet to Hw, ++// so we need to set the packet length to total lengh. ++// TRUE: At the second time, we should send the first packet (default:beacon) ++// to Hw again and set the lengh in descriptor to the real beacon lengh. ++// 2009.10.15 by tynli. ++static void SetFwRsvdPagePkt(PADAPTER Adapter, BOOLEAN bDLFinished) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ struct xmit_frame *pmgntframe; ++ struct pkt_attrib *pattrib; ++ struct xmit_priv *pxmitpriv = &(Adapter->xmitpriv); ++ struct mlme_ext_priv *pmlmeext = &(Adapter->mlmeextpriv); ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ u32 BeaconLength, ProbeRspLength, PSPollLength, NullFunctionDataLength; ++ u8 *ReservedPagePacket; ++ u8 PageNum=0, U1bTmp, TxDescLen=0, TxDescOffset=0; ++ u16 BufIndex=0; ++ u32 TotalPacketLen; ++ RSVDPAGE_LOC RsvdPageLoc; ++ BOOLEAN bDLOK = _FALSE; ++ ++ DBG_871X("%s\n", __FUNCTION__); ++ ++ ReservedPagePacket = (u8*)rtw_malloc(1000); ++ if(ReservedPagePacket == NULL){ ++ DBG_871X("%s(): alloc ReservedPagePacket fail !!!\n", __FUNCTION__); ++ return; ++ } ++ ++ _rtw_memset(ReservedPagePacket, 0, 1000); ++ ++ TxDescLen = 32;//TX_DESC_SIZE; ++ ++#ifdef CONFIG_USB_HCI ++ BufIndex = TXDESC_OFFSET; ++ TxDescOffset = TxDescLen+8; //Shift index for 8 bytes because the dummy bytes in the first descipstor. ++#else ++ BufIndex = 0; ++ TxDescOffset = 0; ++#endif ++ ++ //(1) beacon ++ ConstructBeacon(Adapter,&ReservedPagePacket[BufIndex],&BeaconLength); ++ ++ //DBG_8192C("SetFwRsvdPagePkt(): HW_VAR_SET_TX_CMD: BCN\n", &ReservedPagePacket[BufIndex], (BeaconLength+BufIndex)); ++ ++//-------------------------------------------------------------------- ++ ++ // When we count the first page size, we need to reserve description size for the RSVD ++ // packet, it will be filled in front of the packet in TXPKTBUF. ++ U1bTmp = (u8)PageNum_128(BeaconLength+TxDescLen); ++ PageNum += U1bTmp; ++ // To reserved 2 pages for beacon buffer. 2010.06.24. ++ if(PageNum == 1) ++ PageNum+=1; ++ pHalData->FwRsvdPageStartOffset = PageNum; ++ ++ BufIndex = (PageNum*128) + TxDescOffset; ++ ++ //(2) ps-poll ++ ConstructPSPoll(Adapter, &ReservedPagePacket[BufIndex],&PSPollLength); ++ ++ FillFakeTxDescriptor92C(Adapter, &ReservedPagePacket[BufIndex-TxDescLen], PSPollLength, _TRUE); ++ ++ //DBG_8192C("SetFwRsvdPagePkt(): HW_VAR_SET_TX_CMD: PS-POLL\n", &ReservedPagePacket[BufIndex-TxDescLen], (PSPollLength+TxDescLen)); ++ ++ RsvdPageLoc.LocPsPoll = PageNum; ++ ++//------------------------------------------------------------------ ++ ++ U1bTmp = (u8)PageNum_128(PSPollLength+TxDescLen); ++ PageNum += U1bTmp; ++ ++ BufIndex = (PageNum*128) + TxDescOffset; ++ ++ //(3) null data ++ ConstructNullFunctionData( ++ Adapter, ++ &ReservedPagePacket[BufIndex], ++ &NullFunctionDataLength, ++ get_my_bssid(&(pmlmeinfo->network)), ++ _FALSE); ++ ++ FillFakeTxDescriptor92C(Adapter, &ReservedPagePacket[BufIndex-TxDescLen], NullFunctionDataLength, _FALSE); ++ ++ RsvdPageLoc.LocNullData = PageNum; ++ ++ //DBG_8192C("SetFwRsvdPagePkt(): HW_VAR_SET_TX_CMD: NULL DATA \n", &ReservedPagePacket[BufIndex-TxDescLen], (NullFunctionDataLength+TxDescLen)); ++//------------------------------------------------------------------ ++ ++ U1bTmp = (u8)PageNum_128(NullFunctionDataLength+TxDescLen); ++ PageNum += U1bTmp; ++ ++ BufIndex = (PageNum*128) + TxDescOffset; ++ ++ //(4) probe response ++ ConstructProbeRsp( ++ Adapter, ++ &ReservedPagePacket[BufIndex], ++ &ProbeRspLength, ++ get_my_bssid(&(pmlmeinfo->network)), ++ _FALSE); ++ ++ FillFakeTxDescriptor92C(Adapter, &ReservedPagePacket[BufIndex-TxDescLen], ProbeRspLength, _FALSE); ++ ++ RsvdPageLoc.LocProbeRsp = PageNum; ++ ++ //DBG_8192C("SetFwRsvdPagePkt(): HW_VAR_SET_TX_CMD: PROBE RSP \n", &ReservedPagePacket[BufIndex-TxDescLen], (ProbeRspLength-TxDescLen)); ++ ++//------------------------------------------------------------------ ++ ++ U1bTmp = (u8)PageNum_128(ProbeRspLength+TxDescLen); ++ ++ PageNum += U1bTmp; ++ ++ TotalPacketLen = (PageNum*128); ++ ++ if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL) ++ { ++ return; ++ } ++ ++ //update attribute ++ pattrib = &pmgntframe->attrib; ++ update_mgntframe_attrib(Adapter, pattrib); ++ pattrib->qsel = 0x10; ++ pattrib->pktlen = pattrib->last_txcmdsz = TotalPacketLen - TxDescLen; ++ _rtw_memcpy(pmgntframe->buf_addr, ReservedPagePacket, TotalPacketLen); ++ ++ Adapter->HalFunc.mgnt_xmit(Adapter, pmgntframe); ++ ++ bDLOK = _TRUE; ++ ++ if(bDLOK) ++ { ++ DBG_871X("Set RSVD page location to Fw.\n"); ++ rtl8192c_FillH2CCmd(Adapter, RSVD_PAGE_EID, sizeof(RsvdPageLoc), (u8 *)&RsvdPageLoc); ++ } ++ ++ rtw_mfree(ReservedPagePacket,1000); ++ ++} ++ ++void rtl8192c_set_FwJoinBssReport_cmd(_adapter* padapter, u8 mstatus) ++{ ++ JOINBSSRPT_PARM JoinBssRptParm; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); ++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ ++_func_enter_; ++ ++ DBG_871X("%s mstatus(%x)\n", __FUNCTION__,mstatus); ++ ++ if(mstatus == 1) ++ { ++ // We should set AID, correct TSF, HW seq enable before set JoinBssReport to Fw in 88/92C. ++ // Suggested by filen. Added by tynli. ++ rtw_write16(padapter, REG_BCN_PSR_RPT, (0xC000|pmlmeinfo->aid)); ++ // Do not set TSF again here or vWiFi beacon DMA INT will not work. ++ //correct_TSF(padapter, pmlmeext); ++ // Hw sequende enable by dedault. 2010.06.23. by tynli. ++ //rtw_write16(padapter, REG_NQOS_SEQ, ((pmlmeext->mgnt_seq+100)&0xFFF)); ++ //rtw_write8(padapter, REG_HWSEQ_CTRL, 0xFF); ++ ++ if(IS_NORMAL_CHIP(pHalData->VersionID)) ++ { ++ BOOLEAN bRecover = _FALSE; ++ ++ //set REG_CR bit 8 ++ //U1bTmp = rtw_read8(padapter, REG_CR+1); ++ rtw_write8(padapter, REG_CR+1, 0x03); ++ ++ // Disable Hw protection for a time which revserd for Hw sending beacon. ++ // Fix download reserved page packet fail that access collision with the protection time. ++ // 2010.05.11. Added by tynli. ++ //SetBcnCtrlReg(padapter, 0, BIT3); ++ //SetBcnCtrlReg(padapter, BIT4, 0); ++ rtw_write8(padapter, REG_BCN_CTRL, rtw_read8(padapter, REG_BCN_CTRL)&(~BIT(3))); ++ rtw_write8(padapter, REG_BCN_CTRL, rtw_read8(padapter, REG_BCN_CTRL)|BIT(4)); ++ ++ // Set FWHW_TXQ_CTRL 0x422[6]=0 to tell Hw the packet is not a real beacon frame. ++ if(pHalData->RegFwHwTxQCtrl&BIT6) ++ bRecover = _TRUE; ++ ++ // To tell Hw the packet is not a real beacon frame. ++ //U1bTmp = rtw_read8(padapter, REG_FWHW_TXQ_CTRL+2); ++ rtw_write8(padapter, REG_FWHW_TXQ_CTRL+2, (pHalData->RegFwHwTxQCtrl&(~BIT6))); ++ pHalData->RegFwHwTxQCtrl &= (~BIT6); ++ SetFwRsvdPagePkt(padapter, 0); ++ ++ // 2010.05.11. Added by tynli. ++ //SetBcnCtrlReg(padapter, BIT3, 0); ++ //SetBcnCtrlReg(padapter, 0, BIT4); ++ rtw_write8(padapter, REG_BCN_CTRL, rtw_read8(padapter, REG_BCN_CTRL)|BIT(3)); ++ rtw_write8(padapter, REG_BCN_CTRL, rtw_read8(padapter, REG_BCN_CTRL)&(~BIT(4))); ++ ++ // To make sure that if there exists an adapter which would like to send beacon. ++ // If exists, the origianl value of 0x422[6] will be 1, we should check this to ++ // prevent from setting 0x422[6] to 0 after download reserved page, or it will cause ++ // the beacon cannot be sent by HW. ++ // 2010.06.23. Added by tynli. ++ if(bRecover) ++ { ++ rtw_write8(padapter, REG_FWHW_TXQ_CTRL+2, (pHalData->RegFwHwTxQCtrl|BIT6)); ++ pHalData->RegFwHwTxQCtrl |= BIT6; ++ } ++ ++ // Clear CR[8] or beacon packet will not be send to TxBuf anymore. ++ rtw_write8(padapter, REG_CR+1, 0x02); ++ } ++ } ++ ++ JoinBssRptParm.OpMode = mstatus; ++ ++ rtl8192c_FillH2CCmd(padapter, JOINBSS_RPT_EID, sizeof(JoinBssRptParm), (u8 *)&JoinBssRptParm); ++ ++_func_exit_; ++} ++ ++#ifdef CONFIG_P2P ++void rtl8192c_set_p2p_ctw_period_cmd(_adapter* padapter, u8 ctwindow) ++{ ++ struct P2P_PS_CTWPeriod_t p2p_ps_ctw; ++ ++ p2p_ps_ctw.CTWPeriod = ctwindow; ++ ++ rtl8192c_FillH2CCmd(padapter, P2P_PS_CTW_CMD_EID, 1, (u8 *)(&p2p_ps_ctw)); ++ ++} ++ ++void rtl8192c_set_p2p_ps_offload_cmd(_adapter* padapter, u8 p2p_ps_state) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); ++ struct pwrctrl_priv *pwrpriv = &padapter->pwrctrlpriv; ++ struct wifidirect_info *pwdinfo = &( padapter->wdinfo ); ++ struct P2P_PS_Offload_t *p2p_ps_offload = &pHalData->p2p_ps_offload; ++ u8 i; ++ u16 ctwindow; ++ u32 start_time, tsf_low; ++ ++_func_enter_; ++ ++ switch(p2p_ps_state) ++ { ++ case P2P_PS_DISABLE: ++ DBG_8192C("P2P_PS_DISABLE \n"); ++ _rtw_memset(p2p_ps_offload, 0 ,1); ++ break; ++ case P2P_PS_ENABLE: ++ DBG_8192C("P2P_PS_ENABLE \n"); ++ // update CTWindow value. ++ if( pwdinfo->ctwindow > 0 ) ++ { ++ p2p_ps_offload->CTWindow_En = 1; ++ ctwindow = pwdinfo->ctwindow; ++ if(IS_HARDWARE_TYPE_8723(padapter)) ++ { ++ //rtw_write16(padapter, REG_ATIMWND, ctwindow); ++ } ++ else ++ { ++ rtl8192c_set_p2p_ctw_period_cmd(padapter, ctwindow); ++ } ++ } ++ ++ // hw only support 2 set of NoA ++ for( i=0 ; inoa_num ; i++) ++ { ++ // To control the register setting for which NOA ++ rtw_write8(padapter, 0x5CF, (i << 4)); ++ if(i == 0) ++ p2p_ps_offload->NoA0_En = 1; ++ else ++ p2p_ps_offload->NoA1_En = 1; ++ ++ // config P2P NoA Descriptor Register ++ rtw_write32(padapter, 0x5E0, pwdinfo->noa_duration[i]); ++ ++ rtw_write32(padapter, 0x5E4, pwdinfo->noa_interval[i]); ++ ++ //Get Current TSF value ++ tsf_low = rtw_read32(padapter, REG_TSFTR); ++ ++ start_time = pwdinfo->noa_start_time[i]; ++ if(pwdinfo->noa_count[i] != 1) ++ { ++ while( start_time <= (tsf_low+(50*1024) ) ) ++ { ++ start_time += pwdinfo->noa_interval[i]; ++ if(pwdinfo->noa_count[i] != 255) ++ pwdinfo->noa_count[i]--; ++ } ++ } ++ //DBG_8192C("%s(): start_time = %x\n",__FUNCTION__,start_time); ++ rtw_write32(padapter, 0x5E8, start_time); ++ ++ rtw_write8(padapter, 0x5EC, pwdinfo->noa_count[i]); ++ } ++ ++ if( (pwdinfo->opp_ps == 1) || (pwdinfo->noa_num > 0) ) ++ { ++ // rst p2p circuit ++ rtw_write8(padapter, REG_DUAL_TSF_RST, BIT(4)); ++ ++ p2p_ps_offload->Offload_En = 1; ++ ++ if(rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) ++ { ++ p2p_ps_offload->role= 1; ++ p2p_ps_offload->AllStaSleep = 0; ++ } ++ else ++ { ++ p2p_ps_offload->role= 0; ++ } ++ ++ p2p_ps_offload->discovery = 0; ++ } ++ break; ++ case P2P_PS_SCAN: ++ DBG_8192C("P2P_PS_SCAN \n"); ++ p2p_ps_offload->discovery = 1; ++ break; ++ case P2P_PS_SCAN_DONE: ++ DBG_8192C("P2P_PS_SCAN_DONE \n"); ++ p2p_ps_offload->discovery = 0; ++ pwdinfo->p2p_ps = P2P_PS_ENABLE; ++ break; ++ default: ++ break; ++ } ++ ++ rtl8192c_FillH2CCmd(padapter, P2P_PS_OFFLOAD_EID, 1, (u8 *)p2p_ps_offload); ++ ++_func_exit_; ++ ++} ++#endif //CONFIG_P2P ++ ++#ifdef CONFIG_IOL ++#include ++int rtl8192c_IOL_exec_cmds_sync(ADAPTER *adapter, struct xmit_frame *xmit_frame, u32 max_wating_ms) ++{ ++ IO_OFFLOAD_LOC IoOffloadLoc; ++ u32 start_time = rtw_get_current_time(); ++ u32 passing_time_ms; ++ u8 polling_ret; ++ int ret = _FAIL; ++ ++ if (rtw_IOL_append_END_cmd(xmit_frame) != _SUCCESS) ++ goto exit; ++ ++ //adapter->HalFunc.mgnt_xmit(adapter, xmit_frame); ++ rtw_dump_xframe_sync(adapter, xmit_frame); ++ ++ IoOffloadLoc.LocCmd = 0; ++ if(_SUCCESS != rtl8192c_FillH2CCmd(adapter, H2C_92C_IO_OFFLOAD, sizeof(IO_OFFLOAD_LOC), (u8 *)&IoOffloadLoc)) ++ goto exit; ++ ++ //polling if the IO offloading is done ++ while( (passing_time_ms=rtw_get_passing_time_ms(start_time)) <= max_wating_ms) { ++ #if 0 //C2H ++ if(0xff == rtw_read8(adapter, REG_C2HEVT_CLEAR)) ++ break; ++ #else// 0x1c3 ++ if(0x00 != (polling_ret=rtw_read8(adapter, 0x1c3))) ++ break; ++ #endif ++ rtw_msleep_os(5); ++ } ++ #if 0 //debug ++ DBG_871X("IOL %s, polling_ret:0x%02x, 0x1c0=0x%08x, 0x1c4=0x%08x, 0x1cc=0x%08x, 0x1e8=0x%08x, 0x130=0x%08x, 0x134=0x%08x\n" ++ , polling_ret==0xff?"success":"error" ++ , polling_ret ++ , rtw_read32(adapter, 0x1c0) ++ , rtw_read32(adapter, 0x1c4) ++ , rtw_read32(adapter, 0x1cc) ++ , rtw_read32(adapter, 0x1e8) ++ , rtw_read32(adapter, 0x130) ++ , rtw_read32(adapter, 0x134) ++ ); ++ rtw_write32(adapter, 0x1c0, 0x0); ++ #endif ++ ++ if(polling_ret == 0xff) ++ ret =_SUCCESS; ++ else { ++ DBG_871X("IOL %s, polling_ret:0x%02x\n" ++ //", 0x1c0=0x%08x, 0x1c4=0x%08x, 0x1cc=0x%08x, 0x1e8=0x%08x, 0x130=0x%08x, 0x134=0x%08x\n" ++ , polling_ret==0xff?"success":"error" ++ , polling_ret ++ //, rtw_read32(adapter, 0x1c0) ++ //, rtw_read32(adapter, 0x1c4) ++ //, rtw_read32(adapter, 0x1cc) ++ //, rtw_read32(adapter, 0x1e8) ++ //, rtw_read32(adapter, 0x130) ++ //, rtw_read32(adapter, 0x134) ++ ); ++ #if 0 //debug ++ rtw_write16(adapter, 0x1c4, 0x0000); ++ rtw_msleep_os(10); ++ DBG_871X("after reset, 0x1c4=0x%08x\n", rtw_read32(adapter, 0x1c4)); ++ #endif ++ ++ } ++ ++ { ++ #if 0 //C2H ++ u32 c2h_evt; ++ int i; ++ c2h_evt = rtw_read32(adapter, REG_C2HEVT_MSG_NORMAL); ++ DBG_871X("%s io-offloading complete, in %ums: 0x%08x\n", __FUNCTION__, passing_time_ms, c2h_evt); ++ rtw_write8(adapter, REG_C2HEVT_CLEAR, 0x0); ++ #else// 0x1c3 ++ DBG_871X("IOL %s complete in %ums\n", __FUNCTION__, passing_time_ms); ++ rtw_write8(adapter, 0x1c3, 0x0); ++ #endif ++ } ++ ++exit: ++ return ret; ++ ++} ++#endif //CONFIG_IOL ++ ++ ++#ifdef CONFIG_WOWLAN ++ ++void rtl8192c_set_wowlan_cmd(_adapter* padapter) ++{ ++ u8 res=_SUCCESS; ++ SETWOWLAN_PARM pwowlan_parm; ++ struct pwrctrl_priv *pwrpriv=&padapter->pwrctrlpriv; ++ ++_func_enter_; ++ ++ pwowlan_parm.mode =0; ++ pwowlan_parm.gpio_index=0; ++ pwowlan_parm.gpio_duration=0; ++ pwowlan_parm.second_mode =0; ++ pwowlan_parm.reserve=0; ++ ++ if(pwrpriv->wowlan_mode ==_TRUE){ ++ pwowlan_parm.mode |=FW_WOWLAN_FUN_EN; ++ //printk("\n %s 1.pwowlan_parm.mode=0x%x \n",__FUNCTION__,pwowlan_parm.mode ); ++ if(pwrpriv->wowlan_pattern ==_TRUE){ ++ pwowlan_parm.mode |= FW_WOWLAN_PATTERN_MATCH; ++ //printk("\n %s 2.pwowlan_parm.mode=0x%x \n",__FUNCTION__,pwowlan_parm.mode ); ++ } ++ if(pwrpriv->wowlan_magic ==_TRUE){ ++ pwowlan_parm.mode |=FW_WOWLAN_MAGIC_PKT; ++ //printk("\n %s 3.pwowlan_parm.mode=0x%x \n",__FUNCTION__,pwowlan_parm.mode ); ++ } ++ if(pwrpriv->wowlan_unicast ==_TRUE){ ++ pwowlan_parm.mode |=FW_WOWLAN_UNICAST; ++ //printk("\n %s 4.pwowlan_parm.mode=0x%x \n",__FUNCTION__,pwowlan_parm.mode ); ++ } ++ //WOWLAN_GPIO_ACTIVE means GPIO high active ++ //pwowlan_parm.mode |=FW_WOWLAN_GPIO_ACTIVE; ++ pwowlan_parm.mode |=FW_WOWLAN_REKEY_WAKEUP; ++ pwowlan_parm.mode |=FW_WOWLAN_DEAUTH_WAKEUP; ++ ++ //GPIO3 ++ pwowlan_parm.gpio_index=3; ++ ++ //duration unit is 64us ++ pwowlan_parm.gpio_duration=0xff; ++ // ++ pwowlan_parm.second_mode|=FW_WOWLAN_GPIO_WAKEUP_EN; ++ //printk("\n %s 5.pwowlan_parm.mode=0x%x \n",__FUNCTION__,pwowlan_parm.mode ); ++ { u8 *ptr=(u8 *)&pwowlan_parm; ++ printk("\n %s H2C_WO_WLAN=%x %02x:%02x:%02x:%02x:%02x \n",__FUNCTION__,H2C_WO_WLAN_CMD,ptr[0],ptr[1],ptr[2],ptr[3],ptr[4] ); ++ } ++ rtl8192c_FillH2CCmd(padapter, H2C_WO_WLAN_CMD, 4, (u8 *)&pwowlan_parm); ++ ++ rtl8192c_set_FwJoinBssReport_cmd( padapter, 1); ++ //keep alive period = 3 * 10 BCN interval ++ pwowlan_parm.mode =3; ++ pwowlan_parm.gpio_index=3; ++ rtl8192c_FillH2CCmd(padapter, KEEP_ALIVE_CONTROL_CMD, 2, (u8 *)&pwowlan_parm); ++ printk("%s after KEEP_ALIVE_CONTROL_CMD register 0x81=%x \n",__FUNCTION__,rtw_read8(padapter, 0x81)); ++ ++ pwowlan_parm.mode =1; ++ pwowlan_parm.gpio_index=0; ++ pwowlan_parm.gpio_duration=0; ++ rtl8192c_FillH2CCmd(padapter, DISCONNECT_DECISION_CTRL_CMD, 3, (u8 *)&pwowlan_parm); ++ printk("%s after DISCONNECT_DECISION_CTRL_CMD register 0x81=%x \n",__FUNCTION__,rtw_read8(padapter, 0x81)); ++ ++ //enable GPIO wakeup ++ pwowlan_parm.mode =1; ++ pwowlan_parm.gpio_index=0; ++ pwowlan_parm.gpio_duration=0; ++ rtl8192c_FillH2CCmd(padapter, REMOTE_WAKE_CTRL_CMD, 3, (u8 *)&pwowlan_parm); ++ } ++ else ++ rtl8192c_FillH2CCmd(padapter, H2C_WO_WLAN_CMD, 3, (u8 *)&pwowlan_parm); ++ ++ ++_func_exit_; ++ ++ return ; ++ ++} ++ ++#endif //CONFIG_WOWLAN ++ ++ ++ ++ ++ ++ +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/hal/rtl8192c/rtl8192c_dm.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/hal/rtl8192c/rtl8192c_dm.c 2013-07-26 19:36:05.000000000 +0000 +@@ -0,0 +1,4753 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++******************************************************************************/ ++//============================================================ ++// Description: ++// ++// This file is for 92CE/92CU dynamic mechanism only ++// ++// ++//============================================================ ++ ++//============================================================ ++// include files ++//============================================================ ++#include ++#include ++#include ++#include ++ ++#include ++ ++//============================================================ ++// Global var ++//============================================================ ++static u32 EDCAParam[maxAP][3] = ++{ // UL DL ++ {0x5ea322, 0x00a630, 0x00a44f}, //atheros AP ++ {0x5ea32b, 0x5ea42b, 0x5e4322}, //broadcom AP ++ {0x3ea430, 0x00a630, 0x3ea44f}, //cisco AP ++ {0x5ea44f, 0x00a44f, 0x5ea42b}, //marvell AP ++ {0x5ea422, 0x00a44f, 0x00a44f}, //ralink AP ++ //{0x5ea44f, 0x5ea44f, 0x5ea44f}, //realtek AP ++ {0xa44f, 0x5ea44f, 0x5e431c}, //realtek AP ++ {0x5ea42b, 0xa630, 0x5e431c}, //airgocap AP ++ {0x5ea42b, 0x5ea42b, 0x5ea42b}, //unknown AP ++// {0x5e4322, 0x00a44f, 0x5ea44f}, //unknown AP ++}; ++ ++ ++/*----------------------------------------------------------------------------- ++ * Function: dm_DIGInit() ++ * ++ * Overview: Set DIG scheme init value. ++ * ++ * Input: NONE ++ * ++ * Output: NONE ++ * ++ * Return: NONE ++ * ++ * Revised History: ++ * When Who Remark ++ * ++ *---------------------------------------------------------------------------*/ ++static void dm_DIGInit( ++ IN PADAPTER pAdapter ++) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); ++ struct dm_priv *pdmpriv = &pHalData->dmpriv; ++ DIG_T *pDigTable = &pdmpriv->DM_DigTable; ++ ++ ++ pDigTable->Dig_Enable_Flag = _TRUE; ++ pDigTable->Dig_Ext_Port_Stage = DIG_EXT_PORT_STAGE_MAX; ++ ++ pDigTable->CurIGValue = 0x20; ++ pDigTable->PreIGValue = 0x0; ++ ++ pDigTable->CurSTAConnectState = pDigTable->PreSTAConnectState = DIG_STA_DISCONNECT; ++ pDigTable->CurMultiSTAConnectState = DIG_MultiSTA_DISCONNECT; ++ ++ pDigTable->RssiLowThresh = DM_DIG_THRESH_LOW; ++ pDigTable->RssiHighThresh = DM_DIG_THRESH_HIGH; ++ ++ pDigTable->FALowThresh = DM_FALSEALARM_THRESH_LOW; ++ pDigTable->FAHighThresh = DM_FALSEALARM_THRESH_HIGH; ++ ++ ++ pDigTable->rx_gain_range_max = DM_DIG_MAX; ++ pDigTable->rx_gain_range_min = DM_DIG_MIN; ++ ++ pDigTable->BackoffVal = DM_DIG_BACKOFF_DEFAULT; ++ pDigTable->BackoffVal_range_max = DM_DIG_BACKOFF_MAX; ++ pDigTable->BackoffVal_range_min = DM_DIG_BACKOFF_MIN; ++ ++ pDigTable->PreCCKPDState = CCK_PD_STAGE_MAX; ++ pDigTable->CurCCKPDState = CCK_PD_STAGE_LowRssi; ++ ++ pDigTable->ForbiddenIGI = DM_DIG_MIN; ++ pDigTable->LargeFAHit = 0; ++ pDigTable->Recover_cnt = 0; ++ pdmpriv->DIG_Dynamic_MIN = 0x25; //for FUNAI_TV ++} ++ ++ ++static u8 dm_initial_gain_MinPWDB( ++ IN PADAPTER pAdapter ++ ) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); ++ struct dm_priv *pdmpriv = &pHalData->dmpriv; ++ DIG_T *pDigTable = &pdmpriv->DM_DigTable; ++ int Rssi_val_min = 0; ++ ++ if((pDigTable->CurMultiSTAConnectState == DIG_MultiSTA_CONNECT) && ++ (pDigTable->CurSTAConnectState == DIG_STA_CONNECT) ) ++ { ++ if(pdmpriv->EntryMinUndecoratedSmoothedPWDB != 0) ++ Rssi_val_min = (pdmpriv->EntryMinUndecoratedSmoothedPWDB > pdmpriv->UndecoratedSmoothedPWDB)? ++ pdmpriv->UndecoratedSmoothedPWDB:pdmpriv->EntryMinUndecoratedSmoothedPWDB; ++ else ++ Rssi_val_min = pdmpriv->UndecoratedSmoothedPWDB; ++ } ++ else if(pDigTable->CurSTAConnectState == DIG_STA_CONNECT || ++ pDigTable->CurSTAConnectState == DIG_STA_BEFORE_CONNECT) ++ Rssi_val_min = pdmpriv->UndecoratedSmoothedPWDB; ++ else if(pDigTable->CurMultiSTAConnectState == DIG_MultiSTA_CONNECT) ++ Rssi_val_min = pdmpriv->EntryMinUndecoratedSmoothedPWDB; ++ ++ //printk("%s CurMultiSTAConnectState(0x%02x) UndecoratedSmoothedPWDB(%d),EntryMinUndecoratedSmoothedPWDB(%d)\n" ++ //,__FUNCTION__,pDigTable->CurSTAConnectState, ++ //pdmpriv->UndecoratedSmoothedPWDB,pdmpriv->EntryMinUndecoratedSmoothedPWDB); ++ ++ return (u8)Rssi_val_min; ++} ++ ++ ++static VOID ++dm_FalseAlarmCounterStatistics( ++ IN PADAPTER Adapter ++ ) ++{ ++ u32 ret_value; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ struct dm_priv *pdmpriv = &pHalData->dmpriv; ++ PFALSE_ALARM_STATISTICS FalseAlmCnt = &(pdmpriv->FalseAlmCnt); ++ ++ ret_value = PHY_QueryBBReg(Adapter, rOFDM_PHYCounter1, bMaskDWord); ++ FalseAlmCnt->Cnt_Parity_Fail = ((ret_value&0xffff0000)>>16); ++ ++ ret_value = PHY_QueryBBReg(Adapter, rOFDM_PHYCounter2, bMaskDWord); ++ FalseAlmCnt->Cnt_Rate_Illegal = (ret_value&0xffff); ++ FalseAlmCnt->Cnt_Crc8_fail = ((ret_value&0xffff0000)>>16); ++ ret_value = PHY_QueryBBReg(Adapter, rOFDM_PHYCounter3, bMaskDWord); ++ FalseAlmCnt->Cnt_Mcs_fail = (ret_value&0xffff); ++ ret_value = PHY_QueryBBReg(Adapter, rOFDM0_FrameSync, bMaskDWord); ++ FalseAlmCnt->Cnt_Fast_Fsync = (ret_value&0xffff); ++ FalseAlmCnt->Cnt_SB_Search_fail = ((ret_value&0xffff0000)>>16); ++ ++ FalseAlmCnt->Cnt_Ofdm_fail = FalseAlmCnt->Cnt_Parity_Fail + FalseAlmCnt->Cnt_Rate_Illegal + ++ FalseAlmCnt->Cnt_Crc8_fail + FalseAlmCnt->Cnt_Mcs_fail+ ++ FalseAlmCnt->Cnt_Fast_Fsync + FalseAlmCnt->Cnt_SB_Search_fail; ++ ++ ++ //hold cck counter ++ PHY_SetBBReg(Adapter, rCCK0_FalseAlarmReport, BIT(14), 1); ++ ++ ret_value = PHY_QueryBBReg(Adapter, rCCK0_FACounterLower, bMaskByte0); ++ FalseAlmCnt->Cnt_Cck_fail = ret_value; ++ ++ ret_value = PHY_QueryBBReg(Adapter, rCCK0_FACounterUpper, bMaskByte3); ++ FalseAlmCnt->Cnt_Cck_fail += (ret_value& 0xff)<<8; ++ ++ FalseAlmCnt->Cnt_all = ( FalseAlmCnt->Cnt_Parity_Fail + ++ FalseAlmCnt->Cnt_Rate_Illegal + ++ FalseAlmCnt->Cnt_Crc8_fail + ++ FalseAlmCnt->Cnt_Mcs_fail + ++ FalseAlmCnt->Cnt_Cck_fail); ++ Adapter->recvpriv.FalseAlmCnt_all = FalseAlmCnt->Cnt_all; ++ //reset false alarm counter registers ++ PHY_SetBBReg(Adapter, rOFDM1_LSTF, 0x08000000, 1); ++ PHY_SetBBReg(Adapter, rOFDM1_LSTF, 0x08000000, 0); ++ //reset cck counter ++ PHY_SetBBReg(Adapter, rCCK0_FalseAlarmReport, 0x0000c000, 0); ++ //enable cck counter ++ PHY_SetBBReg(Adapter, rCCK0_FalseAlarmReport, 0x0000c000, 2); ++ ++ //RT_TRACE( COMP_DIG, DBG_LOUD, ("Cnt_Parity_Fail = %ld, Cnt_Rate_Illegal = %ld, Cnt_Crc8_fail = %ld, Cnt_Mcs_fail = %ld\n", ++ // FalseAlmCnt->Cnt_Parity_Fail, FalseAlmCnt->Cnt_Rate_Illegal, FalseAlmCnt->Cnt_Crc8_fail, FalseAlmCnt->Cnt_Mcs_fail) ); ++ //RT_TRACE( COMP_DIG, DBG_LOUD, ("Cnt_Ofdm_fail = %ld, Cnt_Cck_fail = %ld, Cnt_all = %ld\n", ++ // FalseAlmCnt->Cnt_Ofdm_fail, FalseAlmCnt->Cnt_Cck_fail, FalseAlmCnt->Cnt_all) ); ++ //RT_TRACE( COMP_DIG, DBG_LOUD, ("Cnt_Ofdm_fail = %ld, Cnt_Cck_fail = %ld, Cnt_all = %ld\n", ++ // FalseAlmCnt->Cnt_Ofdm_fail, FalseAlmCnt->Cnt_Cck_fail, FalseAlmCnt->Cnt_all) ); ++} ++ ++ ++static VOID ++DM_Write_DIG( ++ IN PADAPTER pAdapter ++ ) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); ++ struct dm_priv *pdmpriv = &pHalData->dmpriv; ++ DIG_T *pDigTable = &pdmpriv->DM_DigTable; ++ ++ //RT_TRACE( COMP_DIG, DBG_LOUD, ("CurIGValue = 0x%lx, PreIGValue = 0x%lx, BackoffVal = %d\n", ++ // DM_DigTable.CurIGValue, DM_DigTable.PreIGValue, DM_DigTable.BackoffVal)); ++ ++ if (pDigTable->Dig_Enable_Flag == _FALSE) ++ { ++ //RT_TRACE( COMP_DIG, DBG_LOUD, ("DIG is disabled\n")); ++ pDigTable->PreIGValue = 0x17; ++ return; ++ } ++ ++ if(pDigTable->PreIGValue != pDigTable->CurIGValue) ++ { ++ // Set initial gain. ++ //PHY_SetBBReg(pAdapter, rOFDM0_XAAGCCore1, bMaskByte0, pDigTable->CurIGValue); ++ //PHY_SetBBReg(pAdapter, rOFDM0_XBAGCCore1, bMaskByte0, pDigTable->CurIGValue); ++ //printk("%s DIG(0x%02x)\n",__FUNCTION__,pDigTable->CurIGValue); ++ PHY_SetBBReg(pAdapter, rOFDM0_XAAGCCore1, 0x7f, pDigTable->CurIGValue); ++ PHY_SetBBReg(pAdapter, rOFDM0_XBAGCCore1, 0x7f, pDigTable->CurIGValue); ++ pDigTable->PreIGValue = pDigTable->CurIGValue; ++ } ++} ++ ++ ++static VOID ++dm_CtrlInitGainByFA( ++ IN PADAPTER pAdapter ++) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); ++ struct dm_priv *pdmpriv = &pHalData->dmpriv; ++ DIG_T *pDigTable = &pdmpriv->DM_DigTable; ++ PFALSE_ALARM_STATISTICS FalseAlmCnt = &(pdmpriv->FalseAlmCnt); ++ ++ u8 value_IGI = pDigTable->CurIGValue; ++ ++ if(FalseAlmCnt->Cnt_all < DM_DIG_FA_TH0) ++ value_IGI --; ++ else if(FalseAlmCnt->Cnt_all < DM_DIG_FA_TH1) ++ value_IGI += 0; ++ else if(FalseAlmCnt->Cnt_all < DM_DIG_FA_TH2) ++ value_IGI ++; ++ else if(FalseAlmCnt->Cnt_all >= DM_DIG_FA_TH2) ++ value_IGI +=2; ++ ++ if(value_IGI > DM_DIG_FA_UPPER) ++ value_IGI = DM_DIG_FA_UPPER; ++ if(value_IGI < DM_DIG_FA_LOWER) ++ value_IGI = DM_DIG_FA_LOWER; ++ ++ if(FalseAlmCnt->Cnt_all > 10000) ++ value_IGI = DM_DIG_FA_UPPER; ++ ++ pDigTable->CurIGValue = value_IGI; ++ ++ DM_Write_DIG(pAdapter); ++ ++} ++ ++#ifdef CONFIG_SPECIAL_SETTING_FOR_FUNAI_TV ++VOID dm_CtrlInitGainByRssi( IN PADAPTER pAdapter) ++{ ++ ++ u32 isBT; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); ++ struct dm_priv *pdmpriv = &pHalData->dmpriv; ++ DIG_T *pDigTable = &pdmpriv->DM_DigTable; ++ PFALSE_ALARM_STATISTICS FalseAlmCnt = &(pdmpriv->FalseAlmCnt); ++ ++ //modify DIG upper bound ++ if((pDigTable->Rssi_val_min + 20) > DM_DIG_MAX ) ++ pDigTable->rx_gain_range_max = DM_DIG_MAX; ++ else ++ pDigTable->rx_gain_range_max = pDigTable->Rssi_val_min + 20; ++ ++ //modify DIG lower bound ++ if((FalseAlmCnt->Cnt_all > 500)&&(pdmpriv->DIG_Dynamic_MIN < 0x25)) ++ pdmpriv->DIG_Dynamic_MIN++; ++ if((FalseAlmCnt->Cnt_all < 500)&&(pdmpriv->DIG_Dynamic_MIN > DM_DIG_MIN)) ++ pdmpriv->DIG_Dynamic_MIN--; ++ if((pDigTable->Rssi_val_min < 8) && (pdmpriv->DIG_Dynamic_MIN > DM_DIG_MIN)) ++ pdmpriv->DIG_Dynamic_MIN--; ++ ++ //modify DIG lower bound, deal with abnorally large false alarm ++ if(FalseAlmCnt->Cnt_all > 10000) ++ { ++ //RT_TRACE(COMP_DIG, DBG_LOUD, ("dm_DIG(): Abnornally false alarm case. \n")); ++ pDigTable->LargeFAHit++; ++ if(pDigTable->ForbiddenIGI < pDigTable->CurIGValue) ++ { ++ pDigTable->ForbiddenIGI = pDigTable->CurIGValue; ++ pDigTable->LargeFAHit = 1; ++ } ++ if(pDigTable->LargeFAHit >= 3) ++ { ++ if((pDigTable->ForbiddenIGI+1) >pDigTable->rx_gain_range_max) ++ pDigTable->rx_gain_range_min = pDigTable->rx_gain_range_max; ++ else ++ pDigTable->rx_gain_range_min = (pDigTable->ForbiddenIGI + 1); ++ pDigTable->Recover_cnt = 3600; //3600=2hr ++ } ++ } ++ else ++ { ++ //Recovery mechanism for IGI lower bound ++ if(pDigTable->Recover_cnt != 0){ ++ pDigTable->Recover_cnt --; ++ } ++ else ++ { ++ if(pDigTable->LargeFAHit == 0 ) ++ { ++ if((pDigTable->ForbiddenIGI -1) < pdmpriv->DIG_Dynamic_MIN) //DM_DIG_MIN) ++ { ++ pDigTable->ForbiddenIGI = pdmpriv->DIG_Dynamic_MIN; //DM_DIG_MIN; ++ pDigTable->rx_gain_range_min = pdmpriv->DIG_Dynamic_MIN; //DM_DIG_MIN; ++ } ++ else ++ { ++ pDigTable->ForbiddenIGI --; ++ pDigTable->rx_gain_range_min = (pDigTable->ForbiddenIGI + 1); ++ } ++ } ++ else if(pDigTable->LargeFAHit == 3 ) ++ { ++ pDigTable->LargeFAHit = 0; ++ } ++ } ++ } ++ #ifdef CONFIG_USB_HCI ++ if(FalseAlmCnt->Cnt_all < 250) ++ { ++#endif ++ //DBG_8192C("===> dm_CtrlInitGainByRssi, Enter DIG by SS mode\n"); ++ ++ isBT = rtw_read8(pAdapter, 0x4fd) & 0x01; ++ ++ if(!isBT){ ++ ++ if(FalseAlmCnt->Cnt_all > pDigTable->FAHighThresh) ++ { ++ if((pDigTable->BackoffVal -2) < pDigTable->BackoffVal_range_min) ++ pDigTable->BackoffVal = pDigTable->BackoffVal_range_min; ++ else ++ pDigTable->BackoffVal -= 2; ++ } ++ else if(FalseAlmCnt->Cnt_all < pDigTable->FALowThresh) ++ { ++ if((pDigTable->BackoffVal+2) > pDigTable->BackoffVal_range_max) ++ pDigTable->BackoffVal = pDigTable->BackoffVal_range_max; ++ else ++ pDigTable->BackoffVal +=2; ++ } ++ } ++ else ++ pDigTable->BackoffVal = DM_DIG_BACKOFF_DEFAULT; ++ ++ pDigTable->CurIGValue = pDigTable->Rssi_val_min+10-pDigTable->BackoffVal; ++ ++ //DBG_8192C("Rssi_val_min = %x BackoffVal %x\n",pDigTable->Rssi_val_min, pDigTable->BackoffVal); ++#ifdef CONFIG_USB_HCI ++ } ++ else ++ { ++ //DBG_8192C("===> dm_CtrlInitGainByRssi, Enter DIG by FA mode\n"); ++ //DBG_8192C("RSSI = 0x%x", pDigTable->Rssi_val_min); ++ ++ //Adjust initial gain by false alarm ++ if(FalseAlmCnt->Cnt_all > 1000) ++ pDigTable->CurIGValue = pDigTable ->PreIGValue+2; ++ else if (FalseAlmCnt->Cnt_all > 750) ++ pDigTable->CurIGValue = pDigTable->PreIGValue+1; ++ else if(FalseAlmCnt->Cnt_all < 500) ++ pDigTable->CurIGValue = pDigTable->PreIGValue-1; ++ } ++#endif ++ ++ //Check initial gain by upper/lower bound ++ if(pDigTable->CurIGValue >pDigTable->rx_gain_range_max) ++ pDigTable->CurIGValue = pDigTable->rx_gain_range_max; ++ ++ if(pDigTable->CurIGValue < pDigTable->rx_gain_range_min) ++ pDigTable->CurIGValue = pDigTable->rx_gain_range_min; ++ ++ //printk("%s => rx_gain_range_max(0x%02x) rx_gain_range_min(0x%02x)\n",__FUNCTION__, ++ // pDigTable->rx_gain_range_max,pDigTable->rx_gain_range_min); ++ //printk("%s CurIGValue(0x%02x) <====\n",__FUNCTION__,pDigTable->CurIGValue ); ++ ++ DM_Write_DIG(pAdapter); ++ ++} ++#else ++static VOID dm_CtrlInitGainByRssi(IN PADAPTER pAdapter) ++{ ++ u32 isBT; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); ++ struct dm_priv *pdmpriv = &pHalData->dmpriv; ++ DIG_T *pDigTable = &pdmpriv->DM_DigTable; ++ PFALSE_ALARM_STATISTICS FalseAlmCnt = &(pdmpriv->FalseAlmCnt); ++ ++ //modify DIG upper bound ++ if((pDigTable->Rssi_val_min + 20) > DM_DIG_MAX ) ++ pDigTable->rx_gain_range_max = DM_DIG_MAX; ++ else ++ pDigTable->rx_gain_range_max = pDigTable->Rssi_val_min + 20; ++ //printk("%s Rssi_val_min(0x%02x),rx_gain_range_max(0x%02x)\n",__FUNCTION__,pDigTable->Rssi_val_min,pDigTable->rx_gain_range_max); ++ ++ //modify DIG lower bound, deal with abnorally large false alarm ++ if(FalseAlmCnt->Cnt_all > 10000) ++ { ++ //RT_TRACE(COMP_DIG, DBG_LOUD, ("dm_DIG(): Abnornally false alarm case. \n")); ++ ++ pDigTable->LargeFAHit++; ++ if(pDigTable->ForbiddenIGI < pDigTable->CurIGValue) ++ { ++ pDigTable->ForbiddenIGI = pDigTable->CurIGValue; ++ pDigTable->LargeFAHit = 1; ++ } ++ ++ if(pDigTable->LargeFAHit >= 3) ++ { ++ if((pDigTable->ForbiddenIGI+1) > pDigTable->rx_gain_range_max) ++ pDigTable->rx_gain_range_min = pDigTable->rx_gain_range_max; ++ else ++ pDigTable->rx_gain_range_min = (pDigTable->ForbiddenIGI + 1); ++ pDigTable->Recover_cnt = 3600; //3600=2hr ++ } ++ } ++ else ++ { ++ //Recovery mechanism for IGI lower bound ++ if(pDigTable->Recover_cnt != 0) ++ pDigTable->Recover_cnt --; ++ else ++ { ++ if(pDigTable->LargeFAHit == 0 ) ++ { ++ if((pDigTable->ForbiddenIGI -1) < DM_DIG_MIN) ++ { ++ pDigTable->ForbiddenIGI = DM_DIG_MIN; ++ pDigTable->rx_gain_range_min = DM_DIG_MIN; ++ } ++ else ++ { ++ pDigTable->ForbiddenIGI --; ++ pDigTable->rx_gain_range_min = (pDigTable->ForbiddenIGI + 1); ++ } ++ } ++ else if(pDigTable->LargeFAHit == 3 ) ++ { ++ pDigTable->LargeFAHit = 0; ++ } ++ } ++ } ++ ++ //RT_TRACE(COMP_DIG, DBG_LOUD, ("DM_DigTable.ForbiddenIGI = 0x%x, DM_DigTable.LargeFAHit = 0x%x\n",pDigTable->ForbiddenIGI, pDigTable->LargeFAHit)); ++ //RT_TRACE(COMP_DIG, DBG_LOUD, ("DM_DigTable.rx_gain_range_max = 0x%x, DM_DigTable.rx_gain_range_min = 0x%x\n",pDigTable->rx_gain_range_max, pDigTable->rx_gain_range_min)); ++ ++#ifdef CONFIG_USB_HCI ++ if(FalseAlmCnt->Cnt_all < 250) ++ { ++#endif ++ //DBG_8192C("===> dm_CtrlInitGainByRssi, Enter DIG by SS mode\n"); ++ ++ isBT = rtw_read8(pAdapter, 0x4fd) & 0x01; ++ ++ if(!isBT){ ++ ++ if(FalseAlmCnt->Cnt_all > pDigTable->FAHighThresh) ++ { ++ if((pDigTable->BackoffVal -2) < pDigTable->BackoffVal_range_min) ++ pDigTable->BackoffVal = pDigTable->BackoffVal_range_min; ++ else ++ pDigTable->BackoffVal -= 2; ++ } ++ else if(FalseAlmCnt->Cnt_all < pDigTable->FALowThresh) ++ { ++ if((pDigTable->BackoffVal+2) > pDigTable->BackoffVal_range_max) ++ pDigTable->BackoffVal = pDigTable->BackoffVal_range_max; ++ else ++ pDigTable->BackoffVal +=2; ++ } ++ } ++ else ++ pDigTable->BackoffVal = DM_DIG_BACKOFF_DEFAULT; ++ ++ pDigTable->CurIGValue = pDigTable->Rssi_val_min+10-pDigTable->BackoffVal; ++ ++ //DBG_8192C("Rssi_val_min = %x BackoffVal %x\n",pDigTable->Rssi_val_min, pDigTable->BackoffVal); ++#ifdef CONFIG_USB_HCI ++ } ++ else ++ { ++ //DBG_8192C("===> dm_CtrlInitGainByRssi, Enter DIG by FA mode\n"); ++ //DBG_8192C("RSSI = 0x%x", pDigTable->Rssi_val_min); ++ ++ //Adjust initial gain by false alarm ++ if(FalseAlmCnt->Cnt_all > 1000) ++ pDigTable->CurIGValue = pDigTable ->PreIGValue+2; ++ else if (FalseAlmCnt->Cnt_all > 750) ++ pDigTable->CurIGValue = pDigTable->PreIGValue+1; ++ else if(FalseAlmCnt->Cnt_all < 500) ++ pDigTable->CurIGValue = pDigTable->PreIGValue-1; ++ } ++#endif ++ ++ //Check initial gain by upper/lower bound ++ if(pDigTable->CurIGValue >pDigTable->rx_gain_range_max) ++ pDigTable->CurIGValue = pDigTable->rx_gain_range_max; ++ ++ if(pDigTable->CurIGValue < pDigTable->rx_gain_range_min) ++ pDigTable->CurIGValue = pDigTable->rx_gain_range_min; ++ ++ //printk("%s => rx_gain_range_max(0x%02x) rx_gain_range_min(0x%02x)\n",__FUNCTION__, ++ // pDigTable->rx_gain_range_max,pDigTable->rx_gain_range_min); ++ //printk("%s CurIGValue(0x%02x) <====\n",__FUNCTION__,pDigTable->CurIGValue ); ++ ++ DM_Write_DIG(pAdapter); ++ ++} ++#endif ++ ++static VOID ++dm_initial_gain_Multi_STA( ++ IN PADAPTER pAdapter) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); ++ struct dm_priv *pdmpriv = &pHalData->dmpriv; ++ struct mlme_priv *pmlmepriv = &(pAdapter->mlmepriv); ++ DIG_T *pDigTable = &pdmpriv->DM_DigTable; ++ int rssi_strength = pdmpriv->EntryMinUndecoratedSmoothedPWDB; ++ BOOLEAN bMulti_STA = _FALSE; ++ ++ //ADHOC and AP Mode ++ if(check_fwstate(pmlmepriv, WIFI_AP_STATE|WIFI_ADHOC_STATE|WIFI_ADHOC_MASTER_STATE) == _TRUE) ++ { ++ bMulti_STA = _TRUE; ++ } ++ ++ ++ if((bMulti_STA == _FALSE) ++ || (pDigTable->CurSTAConnectState == DIG_STA_DISCONNECT)) ++ { ++ pdmpriv->binitialized = _FALSE; ++ pDigTable->Dig_Ext_Port_Stage = DIG_EXT_PORT_STAGE_MAX; ++ return; ++ } ++ else if(pdmpriv->binitialized == _FALSE) ++ { ++ pdmpriv->binitialized = _TRUE; ++ pDigTable->Dig_Ext_Port_Stage = DIG_EXT_PORT_STAGE_0; ++ pDigTable->CurIGValue = 0x20; ++ DM_Write_DIG(pAdapter); ++ } ++ ++ // Initial gain control by ap mode ++ if(pDigTable->CurMultiSTAConnectState == DIG_MultiSTA_CONNECT) ++ { ++ if ( (rssi_strength < pDigTable->RssiLowThresh) && ++ (pDigTable->Dig_Ext_Port_Stage != DIG_EXT_PORT_STAGE_1)) ++ { ++ // Set to dig value to 0x20 for Luke's opinion after disable dig ++ if(pDigTable->Dig_Ext_Port_Stage == DIG_EXT_PORT_STAGE_2) ++ { ++ pDigTable->CurIGValue = 0x20; ++ DM_Write_DIG(pAdapter); ++ } ++ pDigTable->Dig_Ext_Port_Stage = DIG_EXT_PORT_STAGE_1; ++ } ++ else if (rssi_strength > pDigTable->RssiHighThresh) ++ { ++ pDigTable->Dig_Ext_Port_Stage = DIG_EXT_PORT_STAGE_2; ++ dm_CtrlInitGainByFA(pAdapter); ++ } ++ } ++ else if(pDigTable->Dig_Ext_Port_Stage != DIG_EXT_PORT_STAGE_0) ++ { ++ pDigTable->Dig_Ext_Port_Stage = DIG_EXT_PORT_STAGE_0; ++ pDigTable->CurIGValue = 0x20; ++ DM_Write_DIG(pAdapter); ++ } ++ ++ //RT_TRACE( COMP_DIG, DBG_LOUD, ("CurMultiSTAConnectState = %x Dig_Ext_Port_Stage %x\n", ++ // DM_DigTable.CurMultiSTAConnectState, DM_DigTable.Dig_Ext_Port_Stage)); ++} ++ ++ ++static VOID ++dm_initial_gain_STA( ++ IN PADAPTER pAdapter) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); ++ struct dm_priv *pdmpriv = &pHalData->dmpriv; ++ DIG_T *pDigTable = &pdmpriv->DM_DigTable; ++ ++ //RT_TRACE( COMP_DIG, DBG_LOUD, ("PreSTAConnectState = %x, CurSTAConnectState = %x\n", ++ // DM_DigTable.PreSTAConnectState, DM_DigTable.CurSTAConnectState)); ++ ++ ++ if(pDigTable->PreSTAConnectState == pDigTable->CurSTAConnectState|| ++ pDigTable->CurSTAConnectState == DIG_STA_BEFORE_CONNECT || ++ pDigTable->CurSTAConnectState == DIG_STA_CONNECT) ++ { ++ // beforeconnect -> beforeconnect or connect -> connect ++ // (dis)connect -> beforeconnect ++ // disconnect -> connecct or beforeconnect -> connect ++ if(pDigTable->CurSTAConnectState != DIG_STA_DISCONNECT) ++ { ++ pDigTable->Rssi_val_min = dm_initial_gain_MinPWDB(pAdapter); ++ dm_CtrlInitGainByRssi(pAdapter); ++ } ++#ifdef CONFIG_IOCTL_CFG80211 ++ else if((wdev_to_priv(pAdapter->rtw_wdev))->p2p_enabled == _TRUE) ++ { ++ pDigTable->CurIGValue = 0x30; ++ DM_Write_DIG(pAdapter); ++ } ++#endif ++ } ++ else ++ { ++ // connect -> disconnect or beforeconnect -> disconnect ++ pDigTable->Rssi_val_min = 0; ++ pDigTable->Dig_Ext_Port_Stage = DIG_EXT_PORT_STAGE_MAX; ++ pDigTable->BackoffVal = DM_DIG_BACKOFF_DEFAULT; ++ pDigTable->CurIGValue = 0x20; ++ pDigTable->PreIGValue = 0; ++ DM_Write_DIG(pAdapter); ++ } ++ ++} ++ ++ ++static void dm_CCK_PacketDetectionThresh( ++ IN PADAPTER pAdapter) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); ++ struct dm_priv *pdmpriv = &pHalData->dmpriv; ++ PFALSE_ALARM_STATISTICS FalseAlmCnt = &(pdmpriv->FalseAlmCnt); ++ DIG_T *pDigTable = &pdmpriv->DM_DigTable; ++ ++ if(pDigTable->CurSTAConnectState == DIG_STA_CONNECT) ++ { ++ pDigTable->Rssi_val_min = dm_initial_gain_MinPWDB(pAdapter); ++ if(pDigTable->PreCCKPDState == CCK_PD_STAGE_LowRssi) ++ { ++ if(pDigTable->Rssi_val_min <= 25) ++ pDigTable->CurCCKPDState = CCK_PD_STAGE_LowRssi; ++ else ++ pDigTable->CurCCKPDState = CCK_PD_STAGE_HighRssi; ++ } ++ else{ ++ if(pDigTable->Rssi_val_min <= 20) ++ pDigTable->CurCCKPDState = CCK_PD_STAGE_LowRssi; ++ else ++ pDigTable->CurCCKPDState = CCK_PD_STAGE_HighRssi; ++ } ++ } ++ else ++ pDigTable->CurCCKPDState=CCK_PD_STAGE_MAX; ++ ++ if(pDigTable->PreCCKPDState != pDigTable->CurCCKPDState) ++ { ++ if((pDigTable->CurCCKPDState == CCK_PD_STAGE_LowRssi)|| ++ (pDigTable->CurCCKPDState == CCK_PD_STAGE_MAX)) ++ { ++ PHY_SetBBReg(pAdapter, rCCK0_CCA, bMaskByte2, 0x83); ++ ++ //PHY_SetBBReg(pAdapter, rCCK0_System, bMaskByte1, 0x40); ++ //if(IS_92C_SERIAL(pHalData->VersionID)) ++ //PHY_SetBBReg(pAdapter, rCCK0_FalseAlarmReport , bMaskByte2, 0xd7); ++ } ++ else ++ { ++ PHY_SetBBReg(pAdapter, rCCK0_CCA, bMaskByte2, 0xcd); ++ //PHY_SetBBReg(pAdapter,rCCK0_System, bMaskByte1, 0x47); ++ //if(IS_92C_SERIAL(pHalData->VersionID)) ++ //PHY_SetBBReg(pAdapter, rCCK0_FalseAlarmReport , bMaskByte2, 0xd3); ++ } ++ ++ pDigTable->PreCCKPDState = pDigTable->CurCCKPDState; ++ } ++ ++ //RT_TRACE( COMP_DIG, DBG_LOUD, ("CCKPDStage=%x\n",pDigTable->CurCCKPDState)); ++ //RT_TRACE( COMP_DIG, DBG_LOUD, ("is92C=%x\n",IS_92C_SERIAL(pHalData->VersionID))); ++ ++} ++ ++ ++static void ++dm_CtrlInitGainByTwoPort( ++ IN PADAPTER pAdapter) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); ++ struct dm_priv *pdmpriv = &pHalData->dmpriv; ++ struct mlme_priv *pmlmepriv = &(pAdapter->mlmepriv); ++ DIG_T *pDigTable = &pdmpriv->DM_DigTable; ++ ++ if (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY) == _TRUE) ++ return; ++ ++ // Decide the current status and if modify initial gain or not ++ if (check_fwstate(pmlmepriv, _FW_UNDER_LINKING) == _TRUE) ++ { ++ pDigTable->CurSTAConnectState = DIG_STA_BEFORE_CONNECT; ++ } ++ else if(check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) ++ { ++ pDigTable->CurSTAConnectState = DIG_STA_CONNECT; ++ } ++ else ++ { ++ pDigTable->CurSTAConnectState = DIG_STA_DISCONNECT; ++ } ++ ++ ++ pDigTable->CurMultiSTAConnectState = DIG_MultiSTA_DISCONNECT; ++ if(check_fwstate(pmlmepriv, WIFI_ADHOC_STATE|WIFI_ADHOC_MASTER_STATE) == _TRUE) ++ { ++ if((is_IBSS_empty(pAdapter)==_FAIL) && (pAdapter->stapriv.asoc_sta_count > 2)) ++ pDigTable->CurMultiSTAConnectState = DIG_MultiSTA_CONNECT; ++ } ++ ++ if(check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) ++ { ++ if(pAdapter->stapriv.asoc_sta_count > 2) ++ pDigTable->CurMultiSTAConnectState = DIG_MultiSTA_CONNECT; ++ } ++ ++ ++ dm_initial_gain_STA(pAdapter); ++ dm_initial_gain_Multi_STA(pAdapter); ++ dm_CCK_PacketDetectionThresh(pAdapter); ++ ++ pDigTable->PreSTAConnectState = pDigTable->CurSTAConnectState; ++ ++} ++ ++ ++static void dm_DIG( ++ IN PADAPTER pAdapter) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); ++ struct dm_priv *pdmpriv = &pHalData->dmpriv; ++ DIG_T *pDigTable = &pdmpriv->DM_DigTable; ++ ++ //RTPRINT(FDM, DM_Monitor, ("dm_DIG() ==>\n")); ++ ++ if(pdmpriv->bDMInitialGainEnable == _FALSE) ++ return; ++ ++ //if(pDigTable->Dig_Enable_Flag == _FALSE) ++ // return; ++ ++ if(!(pdmpriv->DMFlag & DYNAMIC_FUNC_DIG)) ++ return; ++ ++ //RTPRINT(FDM, DM_Monitor, ("dm_DIG() progress \n")); ++ ++ dm_CtrlInitGainByTwoPort(pAdapter); ++ ++ //RTPRINT(FDM, DM_Monitor, ("dm_DIG() <==\n")); ++} ++ ++static void dm_SavePowerIndex(IN PADAPTER Adapter) ++{ ++ u8 index; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ struct dm_priv *pdmpriv = &pHalData->dmpriv; ++ u32 Power_Index_REG[6] = {0xc90, 0xc91, 0xc92, 0xc98, 0xc99, 0xc9a}; ++ ++ for(index = 0; index< 6; index++) ++ pdmpriv->PowerIndex_backup[index] = rtw_read8(Adapter, Power_Index_REG[index]); ++} ++ ++static void dm_RestorePowerIndex(IN PADAPTER Adapter) ++{ ++ u8 index; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ struct dm_priv *pdmpriv = &pHalData->dmpriv; ++ u32 Power_Index_REG[6] = {0xc90, 0xc91, 0xc92, 0xc98, 0xc99, 0xc9a}; ++ ++ for(index = 0; index< 6; index++) ++ rtw_write8(Adapter, Power_Index_REG[index], pdmpriv->PowerIndex_backup[index]); ++} ++ ++static void dm_WritePowerIndex( ++ IN PADAPTER Adapter, ++ IN u8 Value) ++{ ++ u8 index; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ u32 Power_Index_REG[6] = {0xc90, 0xc91, 0xc92, 0xc98, 0xc99, 0xc9a}; ++ ++ for(index = 0; index< 6; index++) ++ rtw_write8(Adapter, Power_Index_REG[index], Value); ++} ++ ++static void dm_InitDynamicTxPower(IN PADAPTER Adapter) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ struct dm_priv *pdmpriv = &pHalData->dmpriv; ++ ++#ifdef CONFIG_USB_HCI ++ if(pHalData->BoardType == BOARD_USB_High_PA) ++ { ++ dm_SavePowerIndex(Adapter); ++ pdmpriv->bDynamicTxPowerEnable = _TRUE; ++ } ++ else ++#else ++ pdmpriv->bDynamicTxPowerEnable = _FALSE; ++#endif ++ ++ pdmpriv->LastDTPLvl = TxHighPwrLevel_Normal; ++ pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal; ++} ++ ++ ++static void dm_DynamicTxPower(IN PADAPTER Adapter) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ struct dm_priv *pdmpriv = &pHalData->dmpriv; ++ struct mlme_priv *pmlmepriv = &(Adapter->mlmepriv); ++ struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv; ++ int UndecoratedSmoothedPWDB; ++ ++ if(!pdmpriv->bDynamicTxPowerEnable) ++ return; ++ ++ // If dynamic high power is disabled. ++ if(!(pdmpriv->DMFlag & DYNAMIC_FUNC_HP) ) ++ { ++ pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal; ++ return; ++ } ++ ++ // STA not connected and AP not connected ++ if((check_fwstate(pmlmepriv, _FW_LINKED) != _TRUE) && ++ (pdmpriv->EntryMinUndecoratedSmoothedPWDB == 0)) ++ { ++ //RT_TRACE(COMP_HIPWR, DBG_LOUD, ("Not connected to any \n")); ++ pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal; ++ ++ //the LastDTPlvl should reset when disconnect, ++ //otherwise the tx power level wouldn't change when disconnect and connect again. ++ // Maddest 20091220. ++ pdmpriv->LastDTPLvl=TxHighPwrLevel_Normal; ++ return; ++ } ++ ++ if(check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) // Default port ++ { ++ //todo: AP Mode ++ if ((check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE) || ++ (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE)) ++ { ++ UndecoratedSmoothedPWDB = pdmpriv->EntryMinUndecoratedSmoothedPWDB; ++ //RT_TRACE(COMP_HIPWR, DBG_LOUD, ("AP Client PWDB = 0x%x \n", UndecoratedSmoothedPWDB)); ++ } ++ else ++ { ++ UndecoratedSmoothedPWDB = pdmpriv->UndecoratedSmoothedPWDB; ++ //RT_TRACE(COMP_HIPWR, DBG_LOUD, ("STA Default Port PWDB = 0x%x \n", UndecoratedSmoothedPWDB)); ++ } ++ } ++ else // associated entry pwdb ++ { ++ UndecoratedSmoothedPWDB = pdmpriv->EntryMinUndecoratedSmoothedPWDB; ++ //RT_TRACE(COMP_HIPWR, DBG_LOUD, ("AP Ext Port PWDB = 0x%x \n", UndecoratedSmoothedPWDB)); ++ } ++ ++ if(UndecoratedSmoothedPWDB >= TX_POWER_NEAR_FIELD_THRESH_LVL2) ++ { ++ pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Level2; ++ //RT_TRACE(COMP_HIPWR, DBG_LOUD, ("TxHighPwrLevel_Level1 (TxPwr=0x0)\n")); ++ } ++ else if((UndecoratedSmoothedPWDB < (TX_POWER_NEAR_FIELD_THRESH_LVL2-3)) && ++ (UndecoratedSmoothedPWDB >= TX_POWER_NEAR_FIELD_THRESH_LVL1) ) ++ { ++ pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Level1; ++ //RT_TRACE(COMP_HIPWR, DBG_LOUD, ("TxHighPwrLevel_Level1 (TxPwr=0x10)\n")); ++ } ++ else if(UndecoratedSmoothedPWDB < (TX_POWER_NEAR_FIELD_THRESH_LVL1-5)) ++ { ++ pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal; ++ //RT_TRACE(COMP_HIPWR, DBG_LOUD, ("TxHighPwrLevel_Normal\n")); ++ } ++ ++ if( (pdmpriv->DynamicTxHighPowerLvl != pdmpriv->LastDTPLvl) ) ++ { ++ PHY_SetTxPowerLevel8192C(Adapter, pHalData->CurrentChannel); ++ if(pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Normal) // HP1 -> Normal or HP2 -> Normal ++ dm_RestorePowerIndex(Adapter); ++ else if(pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level1) ++ dm_WritePowerIndex(Adapter, 0x14); ++ else if(pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level2) ++ dm_WritePowerIndex(Adapter, 0x10); ++ } ++ pdmpriv->LastDTPLvl = pdmpriv->DynamicTxHighPowerLvl; ++ ++} ++ ++ ++static VOID ++DM_ChangeDynamicInitGainThresh( ++ IN PADAPTER pAdapter, ++ IN u32 DM_Type, ++ IN u32 DM_Value) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); ++ struct dm_priv *pdmpriv = &pHalData->dmpriv; ++ DIG_T *pDigTable = &pdmpriv->DM_DigTable; ++ ++ if (DM_Type == DIG_TYPE_THRESH_HIGH) ++ { ++ pDigTable->RssiHighThresh = DM_Value; ++ } ++ else if (DM_Type == DIG_TYPE_THRESH_LOW) ++ { ++ pDigTable->RssiLowThresh = DM_Value; ++ } ++ else if (DM_Type == DIG_TYPE_ENABLE) ++ { ++ pDigTable->Dig_Enable_Flag = _TRUE; ++ } ++ else if (DM_Type == DIG_TYPE_DISABLE) ++ { ++ pDigTable->Dig_Enable_Flag = _FALSE; ++ } ++ else if (DM_Type == DIG_TYPE_BACKOFF) ++ { ++ if(DM_Value > 30) ++ DM_Value = 30; ++ pDigTable->BackoffVal = (u8)DM_Value; ++ } ++ else if(DM_Type == DIG_TYPE_RX_GAIN_MIN) ++ { ++ if(DM_Value == 0) ++ DM_Value = 0x1; ++ pDigTable->rx_gain_range_min = (u8)DM_Value; ++ } ++ else if(DM_Type == DIG_TYPE_RX_GAIN_MAX) ++ { ++ if(DM_Value > 0x50) ++ DM_Value = 0x50; ++ pDigTable->rx_gain_range_max = (u8)DM_Value; ++ } ++} /* DM_ChangeDynamicInitGainThresh */ ++ ++ ++static VOID PWDB_Monitor( ++ IN PADAPTER Adapter ++ ) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ struct dm_priv *pdmpriv = &pHalData->dmpriv; ++ int i; ++ int tmpEntryMaxPWDB=0, tmpEntryMinPWDB=0xff; ++ u8 sta_cnt=0; ++ u32 PWDB_rssi[NUM_STA]={0};//[0~15]:MACID, [16~31]:PWDB_rssi ++ ++ if(check_fwstate(&Adapter->mlmepriv, _FW_LINKED) != _TRUE) ++ return; ++ ++ ++ if(check_fwstate(&Adapter->mlmepriv, WIFI_AP_STATE|WIFI_ADHOC_STATE|WIFI_ADHOC_MASTER_STATE) == _TRUE) ++ { ++ _irqL irqL; ++ _list *plist, *phead; ++ struct sta_info *psta; ++ struct sta_priv *pstapriv = &Adapter->stapriv; ++ u8 bcast_addr[ETH_ALEN]= {0xff,0xff,0xff,0xff,0xff,0xff}; ++ ++ _enter_critical_bh(&pstapriv->sta_hash_lock, &irqL); ++ ++ for(i=0; i< NUM_STA; i++) ++ { ++ phead = &(pstapriv->sta_hash[i]); ++ plist = get_next(phead); ++ ++ while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) ++ { ++ psta = LIST_CONTAINOR(plist, struct sta_info, hash_list); ++ ++ plist = get_next(plist); ++ ++ if(_rtw_memcmp(psta ->hwaddr, bcast_addr, ETH_ALEN) || ++ _rtw_memcmp(psta->hwaddr, myid(&Adapter->eeprompriv), ETH_ALEN)) ++ continue; ++ ++ if(psta->state & WIFI_ASOC_STATE) ++ { ++ ++ if(psta->rssi_stat.UndecoratedSmoothedPWDB < tmpEntryMinPWDB) ++ tmpEntryMinPWDB = psta->rssi_stat.UndecoratedSmoothedPWDB; ++ ++ if(psta->rssi_stat.UndecoratedSmoothedPWDB > tmpEntryMaxPWDB) ++ tmpEntryMaxPWDB = psta->rssi_stat.UndecoratedSmoothedPWDB; ++ ++ PWDB_rssi[sta_cnt++] = (psta->mac_id | (psta->rssi_stat.UndecoratedSmoothedPWDB<<16)); ++ } ++ ++ } ++ ++ } ++ ++ _exit_critical_bh(&pstapriv->sta_hash_lock, &irqL); ++ ++ ++ ++ if(pHalData->fw_ractrl == _TRUE) ++ { ++ // Report every sta's RSSI to FW ++ for(i=0; i< sta_cnt; i++) ++ { ++ rtl8192c_set_rssi_cmd(Adapter, (u8*)&PWDB_rssi[i]); ++ } ++ } ++ ++ } ++ ++ ++ ++ if(tmpEntryMaxPWDB != 0) // If associated entry is found ++ { ++ pdmpriv->EntryMaxUndecoratedSmoothedPWDB = tmpEntryMaxPWDB; ++ } ++ else ++ { ++ pdmpriv->EntryMaxUndecoratedSmoothedPWDB = 0; ++ } ++ ++ if(tmpEntryMinPWDB != 0xff) // If associated entry is found ++ { ++ pdmpriv->EntryMinUndecoratedSmoothedPWDB = tmpEntryMinPWDB; ++ } ++ else ++ { ++ pdmpriv->EntryMinUndecoratedSmoothedPWDB = 0; ++ } ++ ++ ++ if(check_fwstate(&Adapter->mlmepriv, WIFI_STATION_STATE) == _TRUE) ++ { ++ ++ if(pHalData->fw_ractrl == _TRUE) ++ { ++ u32 param = (u32)(pdmpriv->UndecoratedSmoothedPWDB<<16); ++ ++ param |= 0;//macid=0 for sta mode; ++ ++ rtl8192c_set_rssi_cmd(Adapter, (u8*)¶m); ++ } ++ } ++ ++} ++ ++ ++static void ++DM_InitEdcaTurbo( ++ IN PADAPTER Adapter ++ ) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ ++ pHalData->bCurrentTurboEDCA = _FALSE; ++ Adapter->recvpriv.bIsAnyNonBEPkts = _FALSE; ++ ++} ++ ++ ++static void ++dm_CheckEdcaTurbo( ++ IN PADAPTER Adapter ++ ) ++{ ++ u32 trafficIndex; ++ u32 edca_param; ++ u64 cur_tx_bytes = 0; ++ u64 cur_rx_bytes = 0; ++ u8 bbtchange = _FALSE; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ struct dm_priv *pdmpriv = &pHalData->dmpriv; ++ struct xmit_priv *pxmitpriv = &(Adapter->xmitpriv); ++ struct recv_priv *precvpriv = &(Adapter->recvpriv); ++ struct registry_priv *pregpriv = &Adapter->registrypriv; ++ struct mlme_ext_priv *pmlmeext = &(Adapter->mlmeextpriv); ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++#ifdef CONFIG_BT_COEXIST ++ struct btcoexist_priv *pbtpriv = &(pHalData->bt_coexist); ++#endif ++ ++ ++ if ((pregpriv->wifi_spec == 1) || (pmlmeinfo->HT_enable == 0)) ++ { ++ goto dm_CheckEdcaTurbo_EXIT; ++ } ++ ++ if (pmlmeinfo->assoc_AP_vendor >= maxAP) ++ { ++ goto dm_CheckEdcaTurbo_EXIT; ++ } ++ ++#ifdef CONFIG_BT_COEXIST ++ if(pbtpriv->BT_Coexist) ++ { ++ if( (pbtpriv->BT_EDCA[UP_LINK]!=0) || (pbtpriv->BT_EDCA[DOWN_LINK]!=0)) ++ { ++ bbtchange = _TRUE; ++ } ++ } ++#endif ++ ++ // Check if the status needs to be changed. ++ if((bbtchange) || (!precvpriv->bIsAnyNonBEPkts) ) ++ { ++ cur_tx_bytes = pxmitpriv->tx_bytes - pxmitpriv->last_tx_bytes; ++ cur_rx_bytes = precvpriv->rx_bytes - precvpriv->last_rx_bytes; ++ ++ //traffic, TX or RX ++ if((pmlmeinfo->assoc_AP_vendor == ralinkAP)||(pmlmeinfo->assoc_AP_vendor == atherosAP)) ++ { ++ if (cur_tx_bytes > (cur_rx_bytes << 2)) ++ { // Uplink TP is present. ++ trafficIndex = UP_LINK; ++ } ++ else ++ { // Balance TP is present. ++ trafficIndex = DOWN_LINK; ++ } ++ } ++ else ++ { ++ if (cur_rx_bytes > (cur_tx_bytes << 2)) ++ { // Downlink TP is present. ++ trafficIndex = DOWN_LINK; ++ } ++ else ++ { // Balance TP is present. ++ trafficIndex = UP_LINK; ++ } ++ } ++ ++ if ((pdmpriv->prv_traffic_idx != trafficIndex) || (!pHalData->bCurrentTurboEDCA)) ++ { ++#ifdef CONFIG_BT_COEXIST ++ if(_TRUE == bbtchange) ++ { ++ edca_param = pbtpriv->BT_EDCA[trafficIndex]; ++ } ++ else ++#endif ++ { ++#if 0 ++ //adjust EDCA parameter for BE queue ++ edca_param = EDCAParam[pmlmeinfo->assoc_AP_vendor][trafficIndex]; ++#else ++ ++ if((pmlmeinfo->assoc_AP_vendor == ciscoAP) && (pmlmeext->cur_wireless_mode & WIRELESS_11_24N)) ++ { ++ edca_param = EDCAParam[pmlmeinfo->assoc_AP_vendor][trafficIndex]; ++ } ++ else ++ { ++ edca_param = EDCAParam[unknownAP][trafficIndex]; ++ } ++#endif ++ } ++ ++#ifdef CONFIG_PCI_HCI ++ if(IS_92C_SERIAL(pHalData->VersionID)) ++ { ++ edca_param = 0x60a42b; ++ } ++ else ++ { ++ edca_param = 0x6ea42b; ++ } ++#endif ++ if(Adapter->registrypriv.intel_class_mode==1) ++ edca_param=0xa44f; ++ rtw_write32(Adapter, REG_EDCA_BE_PARAM, edca_param); ++ ++ pdmpriv->prv_traffic_idx = trafficIndex; ++ } ++ ++ pHalData->bCurrentTurboEDCA = _TRUE; ++ } ++ else ++ { ++ // ++ // Turn Off EDCA turbo here. ++ // Restore original EDCA according to the declaration of AP. ++ // ++ if(pHalData->bCurrentTurboEDCA) ++ { ++ rtw_write32(Adapter, REG_EDCA_BE_PARAM, pHalData->AcParam_BE); ++ pHalData->bCurrentTurboEDCA = _FALSE; ++ } ++ } ++ ++dm_CheckEdcaTurbo_EXIT: ++ // Set variables for next time. ++ precvpriv->bIsAnyNonBEPkts = _FALSE; ++ pxmitpriv->last_tx_bytes = pxmitpriv->tx_bytes; ++ precvpriv->last_rx_bytes = precvpriv->rx_bytes; ++ ++} ++ ++#define DPK_DELTA_MAPPING_NUM 13 ++#define index_mapping_HP_NUM 15 ++//091212 chiyokolin ++static VOID ++dm_TXPowerTrackingCallback_ThermalMeter_92C( ++ IN PADAPTER Adapter) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ struct dm_priv *pdmpriv = &pHalData->dmpriv; ++ u8 ThermalValue = 0, delta, delta_LCK, delta_IQK, delta_HP, TimeOut = 100, ThermalValue_HP_count = 0; ++ u32 ThermalValue_HP = 0; ++ s8 delta_DPK; ++ int ele_A, ele_D, TempCCk, X, value32; ++ int Y, ele_C; ++ s8 OFDM_index[2], CCK_index = 0, OFDM_index_old[2], CCK_index_old = 0, delta_APK; ++ int i = 0, CCKSwingNeedUpdate = 0; ++ BOOLEAN is2T = IS_92C_SERIAL(pHalData->VersionID); ++#if 0 ++//#ifdef CONFIG_MP_INCLUDED ++ PMPT_CONTEXT pMptCtx = &(Adapter->MptCtx); ++ pu1Byte TxPwrLevel = pMptCtx->TxPwrLevel; ++#endif ++ ++ u8 OFDM_min_index = 6, rf; //OFDM BB Swing should be less than +3.0dB, which is required by Arthur ++ u32 DPK_delta_mapping[2][DPK_DELTA_MAPPING_NUM] = { ++ {0x1c, 0x1c, 0x1d, 0x1d, 0x1e, ++ 0x1f, 0x00, 0x00, 0x01, 0x01, ++ 0x02, 0x02, 0x03}, ++ {0x1c, 0x1d, 0x1e, 0x1e, 0x1e, ++ 0x1f, 0x00, 0x00, 0x01, 0x02, ++ 0x02, 0x03, 0x03}}; ++ ++ s8 index_mapping_HP[index_mapping_HP_NUM] = { ++ 0, 1, 3, 4, 6, ++ 7, 9, 10, 12, 13, ++ 15, 16, 18, 19, 21 ++ }; ++ ++ s8 index_HP; ++ ++ pdmpriv->TXPowerTrackingCallbackCnt++; //cosa add for debug ++ pdmpriv->bTXPowerTrackingInit = _TRUE; ++ ++ if(pHalData->CurrentChannel == 14 && !pdmpriv->bCCKinCH14) ++ pdmpriv->bCCKinCH14 = _TRUE; ++ else if(pHalData->CurrentChannel != 14 && pdmpriv->bCCKinCH14) ++ pdmpriv->bCCKinCH14 = _FALSE; ++ ++ //DBG_8192C("===>dm_TXPowerTrackingCallback_ThermalMeter_92C\n"); ++ ++ ThermalValue = (u8)PHY_QueryRFReg(Adapter, RF90_PATH_A, RF_T_METER, 0x1f); // 0x24: RF Reg[4:0] ++ ++ //DBG_8192C("\n\nReadback Thermal Meter = 0x%x pre thermal meter 0x%x EEPROMthermalmeter 0x%x\n",ThermalValue,pdmpriv->ThermalValue, pHalData->EEPROMThermalMeter); ++ ++ rtl8192c_PHY_APCalibrate(Adapter, (ThermalValue - pHalData->EEPROMThermalMeter)); ++ rtl8192c_PHY_DigitalPredistortion(Adapter); ++ ++ if(is2T) ++ rf = 2; ++ else ++ rf = 1; ++ ++ if(ThermalValue) ++ { ++// if(!pHalData->ThermalValue) ++ { ++ //Query OFDM path A default setting ++ ele_D = PHY_QueryBBReg(Adapter, rOFDM0_XATxIQImbalance, bMaskDWord)&bMaskOFDM_D; ++ for(i=0; ibCCKinCH14) ++ { ++ if(_rtw_memcmp((void*)&TempCCk, (void*)&CCKSwingTable_Ch14[i][2], 4)==_TRUE) ++ { ++ CCK_index_old =(u8)i; ++ //DBG_8192C("Initial reg0x%x = 0x%x, CCK_index=0x%x, ch 14 %d\n", rCCK0_TxFilter2, TempCCk, CCK_index_old, pdmpriv->bCCKinCH14); ++ break; ++ } ++ } ++ else ++ { ++ if(_rtw_memcmp((void*)&TempCCk, (void*)&CCKSwingTable_Ch1_Ch13[i][2], 4)==_TRUE) ++ { ++ CCK_index_old =(u8)i; ++ //DBG_8192C("Initial reg0x%x = 0x%x, CCK_index=0x%x, ch14 %d\n", rCCK0_TxFilter2, TempCCk, CCK_index_old, pdmpriv->bCCKinCH14); ++ break; ++ } ++ } ++ } ++ ++ if(!pdmpriv->ThermalValue) ++ { ++ pdmpriv->ThermalValue = pHalData->EEPROMThermalMeter; ++ pdmpriv->ThermalValue_LCK = ThermalValue; ++ pdmpriv->ThermalValue_IQK = ThermalValue; ++ pdmpriv->ThermalValue_DPK = pHalData->EEPROMThermalMeter; ++ ++#ifdef CONFIG_USB_HCI ++ for(i = 0; i < rf; i++) ++ pdmpriv->OFDM_index_HP[i] = pdmpriv->OFDM_index[i] = OFDM_index_old[i]; ++ pdmpriv->CCK_index_HP = pdmpriv->CCK_index = CCK_index_old; ++#else ++ for(i = 0; i < rf; i++) ++ pdmpriv->OFDM_index[i] = OFDM_index_old[i]; ++ pdmpriv->CCK_index = CCK_index_old; ++#endif ++ } ++ ++#ifdef CONFIG_USB_HCI ++ if(pHalData->BoardType == BOARD_USB_High_PA) ++ { ++ pdmpriv->ThermalValue_HP[pdmpriv->ThermalValue_HP_index] = ThermalValue; ++ pdmpriv->ThermalValue_HP_index++; ++ if(pdmpriv->ThermalValue_HP_index == HP_THERMAL_NUM) ++ pdmpriv->ThermalValue_HP_index = 0; ++ ++ for(i = 0; i < HP_THERMAL_NUM; i++) ++ { ++ if(pdmpriv->ThermalValue_HP[i]) ++ { ++ ThermalValue_HP += pdmpriv->ThermalValue_HP[i]; ++ ThermalValue_HP_count++; ++ } ++ } ++ ++ if(ThermalValue_HP_count) ++ ThermalValue = (u8)(ThermalValue_HP / ThermalValue_HP_count); ++ } ++#endif ++ } ++ ++ delta = (ThermalValue > pdmpriv->ThermalValue)?(ThermalValue - pdmpriv->ThermalValue):(pdmpriv->ThermalValue - ThermalValue); ++#ifdef CONFIG_USB_HCI ++ if(pHalData->BoardType == BOARD_USB_High_PA) ++ { ++ if(pdmpriv->bDoneTxpower) ++ delta_HP = (ThermalValue > pdmpriv->ThermalValue)?(ThermalValue - pdmpriv->ThermalValue):(pdmpriv->ThermalValue - ThermalValue); ++ else ++ delta_HP = ThermalValue > pHalData->EEPROMThermalMeter?(ThermalValue - pHalData->EEPROMThermalMeter):(pHalData->EEPROMThermalMeter - ThermalValue); ++ } ++ else ++#endif ++ { ++ delta_HP = 0; ++ } ++ delta_LCK = (ThermalValue > pdmpriv->ThermalValue_LCK)?(ThermalValue - pdmpriv->ThermalValue_LCK):(pdmpriv->ThermalValue_LCK - ThermalValue); ++ delta_IQK = (ThermalValue > pdmpriv->ThermalValue_IQK)?(ThermalValue - pdmpriv->ThermalValue_IQK):(pdmpriv->ThermalValue_IQK - ThermalValue); ++ delta_DPK = pdmpriv->ThermalValue_DPK - ThermalValue; ++ ++ //DBG_8192C("Readback Thermal Meter = 0x%lx pre thermal meter 0x%lx EEPROMthermalmeter 0x%lx delta 0x%lx delta_LCK 0x%lx delta_IQK 0x%lx\n", ThermalValue, pHalData->ThermalValue, pHalData->EEPROMThermalMeter, delta, delta_LCK, delta_IQK); ++ ++ if(delta_LCK > 1) ++ { ++ pdmpriv->ThermalValue_LCK = ThermalValue; ++ rtl8192c_PHY_LCCalibrate(Adapter); ++ } ++ ++ if((delta > 0 || delta_HP > 0) && pdmpriv->TxPowerTrackControl) ++ { ++#ifdef CONFIG_USB_HCI ++ if(pHalData->BoardType == BOARD_USB_High_PA) ++ { ++ pdmpriv->bDoneTxpower = _TRUE; ++ delta_HP = ThermalValue > pHalData->EEPROMThermalMeter?(ThermalValue - pHalData->EEPROMThermalMeter):(pHalData->EEPROMThermalMeter - ThermalValue); ++ ++ if(delta_HP > index_mapping_HP_NUM-1) ++ index_HP = index_mapping_HP[index_mapping_HP_NUM-1]; ++ else ++ index_HP = index_mapping_HP[delta_HP]; ++ ++ if(ThermalValue > pHalData->EEPROMThermalMeter) //set larger Tx power ++ { ++ for(i = 0; i < rf; i++) ++ OFDM_index[i] = pdmpriv->OFDM_index_HP[i] - index_HP; ++ CCK_index = pdmpriv->CCK_index_HP -index_HP; ++ } ++ else ++ { ++ for(i = 0; i < rf; i++) ++ OFDM_index[i] = pdmpriv->OFDM_index_HP[i] + index_HP; ++ CCK_index = pdmpriv->CCK_index_HP + index_HP; ++ } ++ ++ delta_HP = (ThermalValue > pdmpriv->ThermalValue)?(ThermalValue - pdmpriv->ThermalValue):(pdmpriv->ThermalValue - ThermalValue); ++ ++ } ++ else ++#endif ++ { ++ if(ThermalValue > pdmpriv->ThermalValue) ++ { ++ for(i = 0; i < rf; i++) ++ pdmpriv->OFDM_index[i] -= delta; ++ ++ pdmpriv->CCK_index -= delta; ++ } ++ else ++ { ++ for(i = 0; i < rf; i++) ++ pdmpriv->OFDM_index[i] += delta; ++ ++ pdmpriv->CCK_index += delta; ++ } ++ } ++ ++ /* ++ if(is2T) ++ { ++ DBG_8192C("temp OFDM_A_index=0x%x, OFDM_B_index=0x%x, CCK_index=0x%x\n", ++ pdmpriv->OFDM_index[0], pdmpriv->OFDM_index[1], pdmpriv->CCK_index); ++ } ++ else ++ { ++ //DBG_8192C("temp OFDM_A_index=0x%x, CCK_index=0x%x\n",pdmpriv->OFDM_index[0], pdmpriv->CCK_index); ++ } ++ */ ++ ++ //no adjust ++#ifdef CONFIG_USB_HCI ++ if(pHalData->BoardType != BOARD_USB_High_PA) ++#endif ++ { ++ if(ThermalValue > pHalData->EEPROMThermalMeter) ++ { ++ for(i = 0; i < rf; i++) ++ OFDM_index[i] = pdmpriv->OFDM_index[i]+1; ++ CCK_index = pdmpriv->CCK_index+1; ++ } ++ else ++ { ++ for(i = 0; i < rf; i++) ++ OFDM_index[i] = pdmpriv->OFDM_index[i]; ++ CCK_index = pdmpriv->CCK_index; ++ } ++#if 0 ++//#ifdef CONFIG_MP_INCLUDED ++ for(i = 0; i < rf; i++) ++ { ++ if(TxPwrLevel[i] >=0 && TxPwrLevel[i] <=26) ++ { ++ if(ThermalValue > pHalData->EEPROMThermalMeter) ++ { ++ if (delta < 5) ++ OFDM_index[i] -= 1; ++ else ++ OFDM_index[i] -= 2; ++ } ++ else if(delta > 5 && ThermalValue < pHalData->EEPROMThermalMeter) ++ { ++ OFDM_index[i] += 1; ++ } ++ } ++ else if (TxPwrLevel[i] >= 27 && TxPwrLevel[i] <= 32 && ThermalValue > pHalData->EEPROMThermalMeter) ++ { ++ if (delta < 5) ++ OFDM_index[i] -= 1; ++ else ++ OFDM_index[i] -= 2; ++ } ++ else if (TxPwrLevel[i] >= 32 && TxPwrLevel[i] <= 38 && ThermalValue > pHalData->EEPROMThermalMeter && delta > 5) ++ { ++ OFDM_index[i] -= 1; ++ } ++ } ++ ++ { ++ if(TxPwrLevel[i] >=0 && TxPwrLevel[i] <=26) ++ { ++ if(ThermalValue > pHalData->EEPROMThermalMeter) ++ { ++ if (delta < 5) ++ CCK_index -= 1; ++ else ++ CCK_index -= 2; ++ } ++ else if(delta > 5 && ThermalValue < pHalData->EEPROMThermalMeter) ++ { ++ CCK_index += 1; ++ } ++ } ++ else if (TxPwrLevel[i] >= 27 && TxPwrLevel[i] <= 32 && ThermalValue > pHalData->EEPROMThermalMeter) ++ { ++ if (delta < 5) ++ CCK_index -= 1; ++ else ++ CCK_index -= 2; ++ } ++ else if (TxPwrLevel[i] >= 32 && TxPwrLevel[i] <= 38 && ThermalValue > pHalData->EEPROMThermalMeter && delta > 5) ++ { ++ CCK_index -= 1; ++ } ++ } ++#endif ++ } ++ ++ for(i = 0; i < rf; i++) ++ { ++ if(OFDM_index[i] > OFDM_TABLE_SIZE-1) ++ OFDM_index[i] = OFDM_TABLE_SIZE-1; ++ else if (OFDM_index[i] < OFDM_min_index) ++ OFDM_index[i] = OFDM_min_index; ++ } ++ ++ if(CCK_index > CCK_TABLE_SIZE-1) ++ CCK_index = CCK_TABLE_SIZE-1; ++ else if (CCK_index < 0) ++ CCK_index = 0; ++ ++ /* ++ if(is2T) ++ { ++ DBG_8192C("new OFDM_A_index=0x%x, OFDM_B_index=0x%x, CCK_index=0x%x\n", OFDM_index[0], OFDM_index[1], CCK_index); ++ } ++ else ++ { ++ //DBG_8192C("new OFDM_A_index=0x%x, CCK_index=0x%x\n", OFDM_index[0], CCK_index); ++ } ++ */ ++ ++ } ++ ++ if(pdmpriv->TxPowerTrackControl && (delta != 0 || delta_HP != 0)) ++ { ++ //Adujst OFDM Ant_A according to IQK result ++ ele_D = (OFDMSwingTable[(u8)OFDM_index[0]] & 0xFFC00000)>>22; ++ X = pdmpriv->RegE94; ++ Y = pdmpriv->RegE9C; ++ ++ if(X != 0) ++ { ++ if ((X & 0x00000200) != 0) ++ X = X | 0xFFFFFC00; ++ ele_A = ((X * ele_D)>>8)&0x000003FF; ++ ++ //new element C = element D x Y ++ if ((Y & 0x00000200) != 0) ++ Y = Y | 0xFFFFFC00; ++ ele_C = ((Y * ele_D)>>8)&0x000003FF; ++ ++ //wirte new elements A, C, D to regC80 and regC94, element B is always 0 ++ value32 = (ele_D<<22)|((ele_C&0x3F)<<16)|ele_A; ++ PHY_SetBBReg(Adapter, rOFDM0_XATxIQImbalance, bMaskDWord, value32); ++ ++ value32 = (ele_C&0x000003C0)>>6; ++ PHY_SetBBReg(Adapter, rOFDM0_XCTxAFE, bMaskH4Bits, value32); ++ ++ value32 = ((X * ele_D)>>7)&0x01; ++ PHY_SetBBReg(Adapter, rOFDM0_ECCAThreshold, BIT31, value32); ++ ++ value32 = ((Y * ele_D)>>7)&0x01; ++ PHY_SetBBReg(Adapter, rOFDM0_ECCAThreshold, BIT29, value32); ++ ++ } ++ else ++ { ++ PHY_SetBBReg(Adapter, rOFDM0_XATxIQImbalance, bMaskDWord, OFDMSwingTable[(u8)OFDM_index[0]]); ++ PHY_SetBBReg(Adapter, rOFDM0_XCTxAFE, bMaskH4Bits, 0x00); ++ PHY_SetBBReg(Adapter, rOFDM0_ECCAThreshold, BIT31|BIT29, 0x00); ++ } ++ ++ //RTPRINT(FINIT, INIT_IQK, ("TxPwrTracking path A: X = 0x%x, Y = 0x%x ele_A = 0x%x ele_C = 0x%x ele_D = 0x%x\n", X, Y, ele_A, ele_C, ele_D)); ++ ++ //Adjust CCK according to IQK result ++ if(!pdmpriv->bCCKinCH14){ ++ rtw_write8(Adapter, 0xa22, CCKSwingTable_Ch1_Ch13[(u8)CCK_index][0]); ++ rtw_write8(Adapter, 0xa23, CCKSwingTable_Ch1_Ch13[(u8)CCK_index][1]); ++ rtw_write8(Adapter, 0xa24, CCKSwingTable_Ch1_Ch13[(u8)CCK_index][2]); ++ rtw_write8(Adapter, 0xa25, CCKSwingTable_Ch1_Ch13[(u8)CCK_index][3]); ++ rtw_write8(Adapter, 0xa26, CCKSwingTable_Ch1_Ch13[(u8)CCK_index][4]); ++ rtw_write8(Adapter, 0xa27, CCKSwingTable_Ch1_Ch13[(u8)CCK_index][5]); ++ rtw_write8(Adapter, 0xa28, CCKSwingTable_Ch1_Ch13[(u8)CCK_index][6]); ++ rtw_write8(Adapter, 0xa29, CCKSwingTable_Ch1_Ch13[(u8)CCK_index][7]); ++ } ++ else{ ++ rtw_write8(Adapter, 0xa22, CCKSwingTable_Ch14[(u8)CCK_index][0]); ++ rtw_write8(Adapter, 0xa23, CCKSwingTable_Ch14[(u8)CCK_index][1]); ++ rtw_write8(Adapter, 0xa24, CCKSwingTable_Ch14[(u8)CCK_index][2]); ++ rtw_write8(Adapter, 0xa25, CCKSwingTable_Ch14[(u8)CCK_index][3]); ++ rtw_write8(Adapter, 0xa26, CCKSwingTable_Ch14[(u8)CCK_index][4]); ++ rtw_write8(Adapter, 0xa27, CCKSwingTable_Ch14[(u8)CCK_index][5]); ++ rtw_write8(Adapter, 0xa28, CCKSwingTable_Ch14[(u8)CCK_index][6]); ++ rtw_write8(Adapter, 0xa29, CCKSwingTable_Ch14[(u8)CCK_index][7]); ++ } ++ ++ if(is2T) ++ { ++ ele_D = (OFDMSwingTable[(u8)OFDM_index[1]] & 0xFFC00000)>>22; ++ ++ //new element A = element D x X ++ X = pdmpriv->RegEB4; ++ Y = pdmpriv->RegEBC; ++ ++ if(X != 0){ ++ if ((X & 0x00000200) != 0) //consider minus ++ X = X | 0xFFFFFC00; ++ ele_A = ((X * ele_D)>>8)&0x000003FF; ++ ++ //new element C = element D x Y ++ if ((Y & 0x00000200) != 0) ++ Y = Y | 0xFFFFFC00; ++ ele_C = ((Y * ele_D)>>8)&0x00003FF; ++ ++ //wirte new elements A, C, D to regC88 and regC9C, element B is always 0 ++ value32=(ele_D<<22)|((ele_C&0x3F)<<16) |ele_A; ++ PHY_SetBBReg(Adapter, rOFDM0_XBTxIQImbalance, bMaskDWord, value32); ++ ++ value32 = (ele_C&0x000003C0)>>6; ++ PHY_SetBBReg(Adapter, rOFDM0_XDTxAFE, bMaskH4Bits, value32); ++ ++ value32 = ((X * ele_D)>>7)&0x01; ++ PHY_SetBBReg(Adapter, rOFDM0_ECCAThreshold, BIT27, value32); ++ ++ value32 = ((Y * ele_D)>>7)&0x01; ++ PHY_SetBBReg(Adapter, rOFDM0_ECCAThreshold, BIT25, value32); ++ ++ } ++ else{ ++ PHY_SetBBReg(Adapter, rOFDM0_XBTxIQImbalance, bMaskDWord, OFDMSwingTable[(u8)OFDM_index[1]]); ++ PHY_SetBBReg(Adapter, rOFDM0_XDTxAFE, bMaskH4Bits, 0x00); ++ PHY_SetBBReg(Adapter, rOFDM0_ECCAThreshold, BIT27|BIT25, 0x00); ++ } ++ ++ //DBG_8192C("TxPwrTracking path B: X = 0x%x, Y = 0x%x ele_A = 0x%x ele_C = 0x%x ele_D = 0x%x\n", X, Y, ele_A, ele_C, ele_D); ++ } ++ ++ /* ++ DBG_8192C("TxPwrTracking 0xc80 = 0x%x, 0xc94 = 0x%x RF 0x24 = 0x%x\n", \ ++ PHY_QueryBBReg(Adapter, 0xc80, bMaskDWord),\ ++ PHY_QueryBBReg(Adapter, 0xc94, bMaskDWord), \ ++ PHY_QueryRFReg(Adapter, RF90_PATH_A, 0x24, bMaskDWord)); ++ */ ++ } ++ ++#if MP_DRIVER == 1 ++ if(delta_IQK > 1) ++#else ++ if(delta_IQK > 3) ++#endif ++ { ++ pdmpriv->ThermalValue_IQK = ThermalValue; ++ rtl8192c_PHY_IQCalibrate(Adapter,_FALSE); ++ } ++ ++ if(delta_DPK != 0) ++ { ++ delta_DPK = ThermalValue - pHalData->EEPROMThermalMeter; ++ ++ //if(pdmpriv->bDPPathAOK || pdmpriv->bDPPathBOK) ++ // DBG_8192C("TxPwrTracking delata_DPK = %d\n", delta_DPK); ++ ++ if(pdmpriv->bDPPathAOK) ++ PHY_SetBBReg(Adapter, 0xb68, 0x7c00, DPK_delta_mapping[0][((delta_DPK+13)/2)]); ++ if(pdmpriv->bDPPathBOK) ++ PHY_SetBBReg(Adapter, 0xb6c, 0x7c00, DPK_delta_mapping[1][((delta_DPK+13)/2)]); ++ pdmpriv->ThermalValue_DPK = ThermalValue; ++ } ++ ++ //update thermal meter value ++ if(pdmpriv->TxPowerTrackControl) ++ pdmpriv->ThermalValue = ThermalValue; ++ ++ } ++ ++ //DBG_8192C("<===dm_TXPowerTrackingCallback_ThermalMeter_92C\n"); ++ ++ pdmpriv->TXPowercount = 0; ++ ++} ++ ++ ++static VOID ++dm_InitializeTXPowerTracking_ThermalMeter( ++ IN PADAPTER Adapter) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ struct dm_priv *pdmpriv = &pHalData->dmpriv; ++ ++ //pMgntInfo->bTXPowerTracking = _TRUE; ++ pdmpriv->TXPowercount = 0; ++ pdmpriv->bTXPowerTrackingInit = _FALSE; ++ pdmpriv->ThermalValue = 0; ++ ++#if (MP_DRIVER != 1) //for mp driver, turn off txpwrtracking as default ++ pdmpriv->TxPowerTrackControl = _TRUE; ++#endif ++ ++ MSG_8192C("pdmpriv->TxPowerTrackControl = %d\n", pdmpriv->TxPowerTrackControl); ++} ++ ++ ++static VOID ++DM_InitializeTXPowerTracking( ++ IN PADAPTER Adapter) ++{ ++ dm_InitializeTXPowerTracking_ThermalMeter(Adapter); ++} ++ ++// ++// Description: ++// - Dispatch TxPower Tracking direct call ONLY for 92s. ++// - We shall NOT schedule Workitem within PASSIVE LEVEL, which will cause system resource ++// leakage under some platform. ++// ++// Assumption: ++// PASSIVE_LEVEL when this routine is called. ++// ++// Added by Roger, 2009.06.18. ++// ++static VOID ++DM_TXPowerTracking92CDirectCall( ++ IN PADAPTER Adapter) ++{ ++ dm_TXPowerTrackingCallback_ThermalMeter_92C(Adapter); ++} ++ ++static VOID ++dm_CheckTXPowerTracking_ThermalMeter( ++ IN PADAPTER Adapter) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ struct dm_priv *pdmpriv = &pHalData->dmpriv; ++ //u1Byte TxPowerCheckCnt = 5; //10 sec ++ ++ //if(!pMgntInfo->bTXPowerTracking /*|| (!pdmpriv->TxPowerTrackControl && pdmpriv->bAPKdone)*/) ++ if(!(pdmpriv->DMFlag & DYNAMIC_FUNC_SS)) ++ { ++ return; ++ } ++ ++ if(!pdmpriv->TM_Trigger) //at least delay 1 sec ++ { ++ //pHalData->TxPowerCheckCnt++; //cosa add for debug ++ PHY_SetRFReg(Adapter, RF90_PATH_A, RF_T_METER, bRFRegOffsetMask, 0x60); ++ //DBG_8192C("Trigger 92C Thermal Meter!!\n"); ++ ++ pdmpriv->TM_Trigger = 1; ++ return; ++ ++ } ++ else ++ { ++ //DBG_8192C("Schedule TxPowerTracking direct call!!\n"); ++ DM_TXPowerTracking92CDirectCall(Adapter); //Using direct call is instead, added by Roger, 2009.06.18. ++ pdmpriv->TM_Trigger = 0; ++ } ++ ++} ++ ++ ++VOID ++rtl8192c_dm_CheckTXPowerTracking( ++ IN PADAPTER Adapter) ++{ ++ dm_CheckTXPowerTracking_ThermalMeter(Adapter); ++} ++ ++#ifdef CONFIG_BT_COEXIST ++static BOOLEAN BT_BTStateChange(PADAPTER Adapter) ++{ ++ PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); ++ struct btcoexist_priv *pbtpriv = &(pHalData->bt_coexist); ++ struct registry_priv *registry_par = &Adapter->registrypriv; ++ ++ struct mlme_priv *pmlmepriv = &(Adapter->mlmepriv); ++ ++ u32 Polling, Ratio_Tx, Ratio_PRI; ++ u32 BT_Tx, BT_PRI; ++ u8 BT_State; ++ static u8 ServiceTypeCnt = 0; ++ u8 CurServiceType; ++ static u8 LastServiceType = BT_Idle; ++ ++ if(check_fwstate(pmlmepriv, _FW_LINKED) == _FALSE) ++ return _FALSE; ++ ++ BT_State = rtw_read8(Adapter, 0x4fd); ++/* ++ temp = PlatformEFIORead4Byte(Adapter, 0x488); ++ BT_Tx = (u2Byte)(((temp<<8)&0xff00)+((temp>>8)&0xff)); ++ BT_PRI = (u2Byte)(((temp>>8)&0xff00)+((temp>>24)&0xff)); ++ ++ temp = PlatformEFIORead4Byte(Adapter, 0x48c); ++ Polling = ((temp<<8)&0xff000000) + ((temp>>8)&0x00ff0000) + ++ ((temp<<8)&0x0000ff00) + ((temp>>8)&0x000000ff); ++ ++*/ ++ BT_Tx = rtw_read32(Adapter, 0x488); ++ ++ DBG_8192C("Ratio 0x488 =%x\n", BT_Tx); ++ BT_Tx =BT_Tx & 0x00ffffff; ++ //RTPRINT(FBT, BT_TRACE, ("Ratio BT_Tx =%x\n", BT_Tx)); ++ ++ BT_PRI = rtw_read32(Adapter, 0x48c); ++ ++ DBG_8192C("Ratio 0x48c =%x\n", BT_PRI); ++ BT_PRI =BT_PRI & 0x00ffffff; ++ //RTPRINT(FBT, BT_TRACE, ("Ratio BT_PRI =%x\n", BT_PRI)); ++ ++ ++ Polling = rtw_read32(Adapter, 0x490); ++ //RTPRINT(FBT, BT_TRACE, ("Ratio 0x490 =%x\n", Polling)); ++ ++ ++ if(BT_Tx==0xffffffff && BT_PRI==0xffffffff && Polling==0xffffffff && BT_State==0xff) ++ return _FALSE; ++ ++ BT_State &= BIT0; ++ ++ if(BT_State != pbtpriv->BT_CUR_State) ++ { ++ pbtpriv->BT_CUR_State = BT_State; ++ ++ if(registry_par->bt_sco == 3) ++ { ++ ServiceTypeCnt = 0; ++ ++ pbtpriv->BT_Service = BT_Idle; ++ ++ DBG_8192C("BT_%s\n", BT_State?"ON":"OFF"); ++ ++ BT_State = BT_State | ++ ((pbtpriv->BT_Ant_isolation==1)?0:BIT1) |BIT2; ++ ++ rtw_write8(Adapter, 0x4fd, BT_State); ++ DBG_8192C("BT set 0x4fd to %x\n", BT_State); ++ } ++ ++ return _TRUE; ++ } ++ DBG_8192C("bRegBT_Sco = %d\n",registry_par->bt_sco); ++ ++ Ratio_Tx = BT_Tx*1000/Polling; ++ Ratio_PRI = BT_PRI*1000/Polling; ++ ++ pbtpriv->Ratio_Tx=Ratio_Tx; ++ pbtpriv->Ratio_PRI=Ratio_PRI; ++ ++ DBG_8192C("Ratio_Tx=%d\n", Ratio_Tx); ++ DBG_8192C("Ratio_PRI=%d\n", Ratio_PRI); ++ ++ ++ if(BT_State && registry_par->bt_sco==3) ++ { ++ DBG_8192C("bt_sco ==3 Follow Counter\n"); ++// if(BT_Tx==0xffff && BT_PRI==0xffff && Polling==0xffffffff) ++// { ++// ServiceTypeCnt = 0; ++// return FALSE; ++// } ++// else ++ { ++ /* ++ Ratio_Tx = BT_Tx*1000/Polling; ++ Ratio_PRI = BT_PRI*1000/Polling; ++ ++ pHalData->bt_coexist.Ratio_Tx=Ratio_Tx; ++ pHalData->bt_coexist.Ratio_PRI=Ratio_PRI; ++ ++ RTPRINT(FBT, BT_TRACE, ("Ratio_Tx=%d\n", Ratio_Tx)); ++ RTPRINT(FBT, BT_TRACE, ("Ratio_PRI=%d\n", Ratio_PRI)); ++ ++ */ ++ if((Ratio_Tx < 30) && (Ratio_PRI < 30)) ++ CurServiceType = BT_Idle; ++ else if((Ratio_PRI > 110) && (Ratio_PRI < 250)) ++ CurServiceType = BT_SCO; ++ else if((Ratio_Tx >= 200)&&(Ratio_PRI >= 200)) ++ CurServiceType = BT_Busy; ++ else if((Ratio_Tx >=350) && (Ratio_Tx < 500)) ++ CurServiceType = BT_OtherBusy; ++ else if(Ratio_Tx >=500) ++ CurServiceType = BT_PAN; ++ else ++ CurServiceType=BT_OtherAction; ++ } ++ ++/* if(pHalData->bt_coexist.bStopCount) ++ { ++ ServiceTypeCnt=0; ++ pHalData->bt_coexist.bStopCount=FALSE; ++ } ++*/ ++// if(CurServiceType == BT_OtherBusy) ++ { ++ ServiceTypeCnt=2; ++ LastServiceType=CurServiceType; ++ } ++#if 0 ++ else if(CurServiceType == LastServiceType) ++ { ++ if(ServiceTypeCnt<3) ++ ServiceTypeCnt++; ++ } ++ else ++ { ++ ServiceTypeCnt = 0; ++ LastServiceType = CurServiceType; ++ } ++#endif ++ ++ if(ServiceTypeCnt==2) ++ { ++ pbtpriv->BT_Service = LastServiceType; ++ BT_State = BT_State | ++ ((pbtpriv->BT_Ant_isolation==1)?0:BIT1) | ++ //((pbtpriv->BT_Service==BT_SCO)?0:BIT2); ++ ((pbtpriv->BT_Service!=BT_Idle)?0:BIT2); ++ ++ //if(pbtpriv->BT_Service==BT_Busy) ++ // BT_State&= ~(BIT2); ++ ++ if(pbtpriv->BT_Service==BT_SCO) ++ { ++ DBG_8192C("BT TYPE Set to ==> BT_SCO\n"); ++ } ++ else if(pbtpriv->BT_Service==BT_Idle) ++ { ++ DBG_8192C("BT TYPE Set to ==> BT_Idle\n"); ++ } ++ else if(pbtpriv->BT_Service==BT_OtherAction) ++ { ++ DBG_8192C("BT TYPE Set to ==> BT_OtherAction\n"); ++ } ++ else if(pbtpriv->BT_Service==BT_Busy) ++ { ++ DBG_8192C("BT TYPE Set to ==> BT_Busy\n"); ++ } ++ else if(pbtpriv->BT_Service==BT_PAN) ++ { ++ DBG_8192C("BT TYPE Set to ==> BT_PAN\n"); ++ } ++ else ++ { ++ DBG_8192C("BT TYPE Set to ==> BT_OtherBusy\n"); ++ } ++ ++ //Add interrupt migration when bt is not in idel state (no traffic). ++ //suggestion by Victor. ++ if(pbtpriv->BT_Service!=BT_Idle)//EDCA_VI_PARAM modify ++ { ++ ++ rtw_write16(Adapter, 0x504, 0x0ccc); ++ rtw_write8(Adapter, 0x506, 0x54); ++ rtw_write8(Adapter, 0x507, 0x54); ++ ++ } ++ else ++ { ++ rtw_write8(Adapter, 0x506, 0x00); ++ rtw_write8(Adapter, 0x507, 0x00); ++ } ++ ++ rtw_write8(Adapter, 0x4fd, BT_State); ++ DBG_8192C("BT_SCO set 0x4fd to %x\n", BT_State); ++ return _TRUE; ++ } ++ } ++ ++ return _FALSE; ++ ++} ++ ++static BOOLEAN ++BT_WifiConnectChange( ++ IN PADAPTER Adapter ++ ) ++{ ++ struct mlme_priv *pmlmepriv = &(Adapter->mlmepriv); ++// PMGNT_INFO pMgntInfo = &Adapter->MgntInfo; ++ static BOOLEAN bMediaConnect = _FALSE; ++ ++ //if(!pMgntInfo->bMediaConnect || MgntRoamingInProgress(pMgntInfo)) ++ if(check_fwstate(pmlmepriv, _FW_LINKED) == _FALSE) ++ { ++ bMediaConnect = _FALSE; ++ } ++ else ++ { ++ if(!bMediaConnect) ++ { ++ bMediaConnect = _TRUE; ++ return _TRUE; ++ } ++ bMediaConnect = _TRUE; ++ } ++ ++ return _FALSE; ++} ++ ++#define BT_RSSI_STATE_NORMAL_POWER BIT0 ++#define BT_RSSI_STATE_AMDPU_OFF BIT1 ++#define BT_RSSI_STATE_SPECIAL_LOW BIT2 ++#define BT_RSSI_STATE_BG_EDCA_LOW BIT3 ++ ++static s32 GET_UNDECORATED_AVERAGE_RSSI(PADAPTER Adapter) ++{ ++ PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); ++ struct mlme_priv *pmlmepriv = &(Adapter->mlmepriv); ++ struct dm_priv *pdmpriv = &pHalData->dmpriv; ++ s32 average_rssi; ++ ++ if(check_fwstate(pmlmepriv, WIFI_ADHOC_STATE|WIFI_ADHOC_MASTER_STATE|WIFI_AP_STATE)) ++ { ++ average_rssi = pdmpriv->EntryMinUndecoratedSmoothedPWDB; ++ } ++ else ++ { ++ average_rssi = pdmpriv->UndecoratedSmoothedPWDB; ++ } ++ return average_rssi; ++} ++ ++static u8 BT_RssiStateChange( ++ IN PADAPTER Adapter ++ ) ++{ ++ PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); ++ struct mlme_priv *pmlmepriv = &(Adapter->mlmepriv); ++ struct btcoexist_priv *pbtpriv = &(pHalData->bt_coexist); ++ struct dm_priv *pdmpriv = &pHalData->dmpriv; ++ //PMGNT_INFO pMgntInfo = &Adapter->MgntInfo; ++ s32 UndecoratedSmoothedPWDB; ++ u8 CurrBtRssiState = 0x00; ++ ++ ++ ++ ++ //if(pMgntInfo->bMediaConnect) // Default port ++ if(check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) ++ { ++ UndecoratedSmoothedPWDB = GET_UNDECORATED_AVERAGE_RSSI(Adapter); ++ } ++ else // associated entry pwdb ++ { ++ if(pdmpriv->EntryMinUndecoratedSmoothedPWDB == 0) ++ UndecoratedSmoothedPWDB = 100; // No any RSSI information. Assume to be MAX. ++ else ++ UndecoratedSmoothedPWDB = pdmpriv->EntryMinUndecoratedSmoothedPWDB; ++ } ++ ++ // Check RSSI to determine HighPower/NormalPower state for BT coexistence. ++ if(UndecoratedSmoothedPWDB >= 67) ++ CurrBtRssiState &= (~BT_RSSI_STATE_NORMAL_POWER); ++ else if(UndecoratedSmoothedPWDB < 62) ++ CurrBtRssiState |= BT_RSSI_STATE_NORMAL_POWER; ++ ++ // Check RSSI to determine AMPDU setting for BT coexistence. ++ if(UndecoratedSmoothedPWDB >= 40) ++ CurrBtRssiState &= (~BT_RSSI_STATE_AMDPU_OFF); ++ else if(UndecoratedSmoothedPWDB <= 32) ++ CurrBtRssiState |= BT_RSSI_STATE_AMDPU_OFF; ++ ++ // Marked RSSI state. It will be used to determine BT coexistence setting later. ++ if(UndecoratedSmoothedPWDB < 35) ++ CurrBtRssiState |= BT_RSSI_STATE_SPECIAL_LOW; ++ else ++ CurrBtRssiState &= (~BT_RSSI_STATE_SPECIAL_LOW); ++ ++ // Check BT state related to BT_Idle in B/G mode. ++ if(UndecoratedSmoothedPWDB < 15) ++ CurrBtRssiState |= BT_RSSI_STATE_BG_EDCA_LOW; ++ else ++ CurrBtRssiState &= (~BT_RSSI_STATE_BG_EDCA_LOW); ++ ++ if(CurrBtRssiState != pbtpriv->BtRssiState) ++ { ++ pbtpriv->BtRssiState = CurrBtRssiState; ++ return _TRUE; ++ } ++ else ++ { ++ return _FALSE; ++ } ++} ++ ++static void dm_BTCoexist(PADAPTER Adapter ) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ struct dm_priv *pdmpriv = &pHalData->dmpriv; ++ struct mlme_priv *pmlmepriv = &(Adapter->mlmepriv); ++ struct mlme_ext_info *pmlmeinfo = &Adapter->mlmeextpriv.mlmext_info; ++ struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv; ++ ++ struct btcoexist_priv *pbtpriv = &(pHalData->bt_coexist); ++ //PMGNT_INFO pMgntInfo = &Adapter->MgntInfo; ++ //PRT_HIGH_THROUGHPUT pHTInfo = GET_HT_INFO(pMgntInfo); ++ ++ //PRX_TS_RECORD pRxTs = NULL; ++ u8 BT_gpio_mux; ++ ++ BOOLEAN bWifiConnectChange, bBtStateChange,bRssiStateChange; ++ ++ if(pbtpriv->bCOBT == _FALSE) return; ++ ++ if(!( pdmpriv->DMFlag & DYNAMIC_FUNC_BT)) return; ++ ++ if( (pbtpriv->BT_Coexist) &&(pbtpriv->BT_CoexistType == BT_CSR_BC4) && (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _FALSE) ) ++ { ++ bWifiConnectChange = BT_WifiConnectChange(Adapter); ++ bBtStateChange = BT_BTStateChange(Adapter); ++ bRssiStateChange = BT_RssiStateChange(Adapter); ++ ++ DBG_8192C("bWifiConnectChange %d, bBtStateChange %d,bRssiStateChange %d\n", ++ bWifiConnectChange,bBtStateChange,bRssiStateChange); ++ ++ // add by hpfan for debug message ++ BT_gpio_mux = rtw_read8(Adapter, REG_GPIO_MUXCFG); ++ DBG_8192C("BTCoexit Reg_0x40 (%2x)\n", BT_gpio_mux); ++ ++ if( bWifiConnectChange ||bBtStateChange ||bRssiStateChange ) ++ { ++ if(pbtpriv->BT_CUR_State) ++ { ++ ++ // Do not allow receiving A-MPDU aggregation. ++ if(pbtpriv->BT_Ampdu)// 0:Disable BT control A-MPDU, 1:Enable BT control A-MPDU. ++ { ++ ++ if(pmlmeinfo->assoc_AP_vendor == ciscoAP) ++ { ++ if(pbtpriv->BT_Service!=BT_Idle) ++ { ++ if(pmlmeinfo->bAcceptAddbaReq) ++ { ++ DBG_8192C("BT_Disallow AMPDU \n"); ++ pmlmeinfo->bAcceptAddbaReq = _FALSE; ++ send_delba(Adapter,0, get_my_bssid(&(pmlmeinfo->network))); ++ } ++ } ++ else ++ { ++ if(!pmlmeinfo->bAcceptAddbaReq) ++ { ++ DBG_8192C("BT_Allow AMPDU RSSI >=40\n"); ++ pmlmeinfo->bAcceptAddbaReq = _TRUE; ++ } ++ } ++ } ++ else ++ { ++ if(!pmlmeinfo->bAcceptAddbaReq) ++ { ++ DBG_8192C("BT_Allow AMPDU BT Idle\n"); ++ pmlmeinfo->bAcceptAddbaReq = _TRUE; ++ } ++ } ++ } ++ ++#if 0 ++ else if((pHalData->bt_coexist.BT_Service==BT_SCO) || (pHalData->bt_coexist.BT_Service==BT_Busy)) ++ { ++ if(pHalData->bt_coexist.BtRssiState & BT_RSSI_STATE_AMDPU_OFF) ++ { ++ if(pMgntInfo->bBT_Ampdu && pHTInfo->bAcceptAddbaReq) ++ { ++ RTPRINT(FBT, BT_TRACE, ("BT_Disallow AMPDU RSSI <=32\n")); ++ pHTInfo->bAcceptAddbaReq = FALSE; ++ if(GetTs(Adapter, (PTS_COMMON_INFO*)(&pRxTs), pMgntInfo->Bssid, 0, RX_DIR, FALSE)) ++ TsInitDelBA(Adapter, (PTS_COMMON_INFO)pRxTs, RX_DIR); ++ } ++ } ++ else ++ { ++ if(pMgntInfo->bBT_Ampdu && !pHTInfo->bAcceptAddbaReq) ++ { ++ RTPRINT(FBT, BT_TRACE, ("BT_Allow AMPDU RSSI >=40\n")); ++ pHTInfo->bAcceptAddbaReq = TRUE; ++ } ++ } ++ } ++ else ++ { ++ if(pMgntInfo->bBT_Ampdu && !pHTInfo->bAcceptAddbaReq) ++ { ++ RTPRINT(FBT, BT_TRACE, ("BT_Allow AMPDU BT not in SCO or BUSY\n")); ++ pHTInfo->bAcceptAddbaReq = TRUE; ++ } ++ } ++#endif ++ ++ if(pbtpriv->BT_Ant_isolation) ++ { ++ DBG_8192C("BT_IsolationLow\n"); ++ ++// 20100427 Joseph: Do not adjust Rate adaptive for BT coexist suggested by SD3. ++#if 0 ++ RTPRINT(FBT, BT_TRACE, ("BT_Update Rate table\n")); ++ if(pMgntInfo->bUseRAMask) ++ { ++ // 20100407 Joseph: Fix rate adaptive modification for BT coexist. ++ // This fix is not complete yet. It shall also consider VWifi and Adhoc case, ++ // which connect with multiple STAs. ++ Adapter->HalFunc.UpdateHalRAMaskHandler( ++ Adapter, ++ FALSE, ++ 0, ++ NULL, ++ NULL, ++ pMgntInfo->RateAdaptive.RATRState, ++ RAMask_Normal); ++ } ++ else ++ { ++ Adapter->HalFunc.UpdateHalRATRTableHandler( ++ Adapter, ++ &pMgntInfo->dot11OperationalRateSet, ++ pMgntInfo->dot11HTOperationalRateSet,NULL); ++ } ++#endif ++ ++ // 20100415 Joseph: Modify BT coexist mechanism suggested by Yaying. ++ // Now we only enable HW BT coexist when BT in "Busy" state. ++ if(1)//pMgntInfo->LinkDetectInfo.NumRecvDataInPeriod >= 20) ++ { ++ if((pmlmeinfo->assoc_AP_vendor == ciscoAP) && ++ pbtpriv->BT_Service==BT_OtherAction) ++ { ++ DBG_8192C("BT_Turn ON Coexist\n"); ++ rtw_write8(Adapter, REG_GPIO_MUXCFG, 0xa0); ++ } ++ else ++ { ++ if((pbtpriv->BT_Service==BT_Busy) && ++ (pbtpriv->BtRssiState & BT_RSSI_STATE_NORMAL_POWER)) ++ { ++ DBG_8192C("BT_Turn ON Coexist\n"); ++ rtw_write8(Adapter, REG_GPIO_MUXCFG, 0xa0); ++ } ++ else if((pbtpriv->BT_Service==BT_OtherAction) && ++ (pbtpriv->BtRssiState & BT_RSSI_STATE_SPECIAL_LOW)) ++ { ++ DBG_8192C("BT_Turn ON Coexist\n"); ++ rtw_write8(Adapter, REG_GPIO_MUXCFG, 0xa0); ++ } ++ else if(pbtpriv->BT_Service==BT_PAN) ++ { ++ DBG_8192C("BT_Turn ON Coexist\n"); ++ rtw_write8(Adapter, REG_GPIO_MUXCFG, 0x00); ++ } ++ else ++ { ++ DBG_8192C("BT_Turn OFF Coexist\n"); ++ rtw_write8(Adapter, REG_GPIO_MUXCFG, 0x00); ++ } ++ } ++ } ++ else ++ { ++ DBG_8192C("BT: There is no Wifi traffic!! Turn off Coexist\n"); ++ rtw_write8(Adapter, REG_GPIO_MUXCFG, 0x00); ++ } ++ ++ if(1)//pMgntInfo->LinkDetectInfo.NumRecvDataInPeriod >= 20) ++ { ++ if(pbtpriv->BT_Service==BT_PAN) ++ { ++ DBG_8192C("BT_Turn ON Coexist(Reg0x44 = 0x10100)\n"); ++ rtw_write32(Adapter, REG_GPIO_PIN_CTRL, 0x10100); ++ } ++ else ++ { ++ DBG_8192C("BT_Turn OFF Coexist(Reg0x44 = 0x0)\n"); ++ rtw_write32(Adapter, REG_GPIO_PIN_CTRL, 0x0); ++ } ++ } ++ else ++ { ++ DBG_8192C("BT: There is no Wifi traffic!! Turn off Coexist(Reg0x44 = 0x0)\n"); ++ rtw_write32(Adapter, REG_GPIO_PIN_CTRL, 0x0); ++ } ++ ++ // 20100430 Joseph: Integrate the BT coexistence EDCA tuning here. ++ if(pbtpriv->BtRssiState & BT_RSSI_STATE_NORMAL_POWER) ++ { ++ if(pbtpriv->BT_Service==BT_OtherBusy) ++ { ++ //pbtpriv->BtEdcaUL = 0x5ea72b; ++ //pbtpriv->BtEdcaDL = 0x5ea72b; ++ pbtpriv->BT_EDCA[UP_LINK] = 0x5ea72b; ++ pbtpriv->BT_EDCA[DOWN_LINK] = 0x5ea72b; ++ ++ DBG_8192C("BT in BT_OtherBusy state Tx (%d) >350 parameter(0x%x) = 0x%x\n", pbtpriv->Ratio_Tx ,REG_EDCA_BE_PARAM, 0x5ea72b); ++ } ++ else if(pbtpriv->BT_Service==BT_Busy) ++ { ++ //pbtpriv->BtEdcaUL = 0x5eb82f; ++ //pbtpriv->BtEdcaDL = 0x5eb82f; ++ ++ pbtpriv->BT_EDCA[UP_LINK] = 0x5eb82f; ++ pbtpriv->BT_EDCA[DOWN_LINK] = 0x5eb82f; ++ ++ DBG_8192C("BT in BT_Busy state parameter(0x%x) = 0x%x\n", REG_EDCA_BE_PARAM, 0x5eb82f); ++ } ++ else if(pbtpriv->BT_Service==BT_SCO) ++ { ++ if(pbtpriv->Ratio_Tx>160) ++ { ++ //pbtpriv->BtEdcaUL = 0x5ea72f; ++ //pbtpriv->BtEdcaDL = 0x5ea72f; ++ pbtpriv->BT_EDCA[UP_LINK] = 0x5ea72f; ++ pbtpriv->BT_EDCA[DOWN_LINK] = 0x5ea72f; ++ DBG_8192C("BT in BT_SCO state Tx (%d) >160 parameter(0x%x) = 0x%x\n",pbtpriv->Ratio_Tx, REG_EDCA_BE_PARAM, 0x5ea72f); ++ } ++ else ++ { ++ //pbtpriv->BtEdcaUL = 0x5ea32b; ++ //pbtpriv->BtEdcaDL = 0x5ea42b; ++ ++ pbtpriv->BT_EDCA[UP_LINK] = 0x5ea32b; ++ pbtpriv->BT_EDCA[DOWN_LINK] = 0x5ea42b; ++ ++ DBG_8192C("BT in BT_SCO state Tx (%d) <160 parameter(0x%x) = 0x%x\n", pbtpriv->Ratio_Tx,REG_EDCA_BE_PARAM, 0x5ea32f); ++ } ++ } ++ else ++ { ++ // BT coexistence mechanism does not control EDCA parameter. ++ //pbtpriv->BtEdcaUL = 0; ++ //pbtpriv->BtEdcaDL = 0; ++ ++ pbtpriv->BT_EDCA[UP_LINK] = 0; ++ pbtpriv->BT_EDCA[DOWN_LINK] = 0; ++ DBG_8192C("BT in State %d and parameter(0x%x) use original setting.\n",pbtpriv->BT_Service, REG_EDCA_BE_PARAM); ++ } ++ ++ if((pbtpriv->BT_Service!=BT_Idle) && ++ (pmlmeext->cur_wireless_mode == WIRELESS_MODE_G) && ++ (pbtpriv->BtRssiState & BT_RSSI_STATE_BG_EDCA_LOW)) ++ { ++ //pbtpriv->BtEdcaUL = 0x5eb82b; ++ //pbtpriv->BtEdcaDL = 0x5eb82b; ++ ++ pbtpriv->BT_EDCA[UP_LINK] = 0x5eb82b; ++ pbtpriv->BT_EDCA[DOWN_LINK] = 0x5eb82b; ++ ++ DBG_8192C("BT set parameter(0x%x) = 0x%x\n", REG_EDCA_BE_PARAM, 0x5eb82b); ++ } ++ } ++ else ++ { ++ // BT coexistence mechanism does not control EDCA parameter. ++ //pbtpriv->BtEdcaUL = 0; ++ //pbtpriv->BtEdcaDL = 0; ++ ++ pbtpriv->BT_EDCA[UP_LINK] = 0; ++ pbtpriv->BT_EDCA[DOWN_LINK] = 0; ++ } ++ ++ // 20100415 Joseph: Set RF register 0x1E and 0x1F for BT coexist suggested by Yaying. ++ if(pbtpriv->BT_Service!=BT_Idle) ++ { ++ DBG_8192C("BT Set RfReg0x1E[7:4] = 0x%x \n", 0xf); ++ PHY_SetRFReg(Adapter, PathA, 0x1e, 0xf0, 0xf); ++ //RTPRINT(FBT, BT_TRACE, ("BT Set RfReg0x1E[7:4] = 0x%x \n", 0xf)); ++ //PHY_SetRFReg(Adapter, PathA, 0x1f, 0xf0, 0xf); ++ } ++ else ++ { ++ DBG_8192C("BT Set RfReg0x1E[7:4] = 0x%x \n",pbtpriv->BtRfRegOrigin1E); ++ PHY_SetRFReg(Adapter, PathA, 0x1e, 0xf0, pbtpriv->BtRfRegOrigin1E); ++ //RTPRINT(FBT, BT_TRACE, ("BT Set RfReg0x1F[7:4] = 0x%x \n", pHalData->bt_coexist.BtRfRegOrigin1F)); ++ //PHY_SetRFReg(Adapter, PathA, 0x1f, 0xf0, pHalData->bt_coexist.BtRfRegOrigin1F); ++ } ++ } ++ else ++ { ++ DBG_8192C("BT_IsolationHigh\n"); ++ // Do nothing. ++ } ++ } ++ else ++ { ++ ++ if(pbtpriv->BT_Ampdu && !pmlmeinfo->bAcceptAddbaReq) ++ { ++ DBG_8192C("BT_Allow AMPDU bt is off\n"); ++ pmlmeinfo->bAcceptAddbaReq = _TRUE; ++ } ++ ++ DBG_8192C("BT_Turn OFF Coexist bt is off \n"); ++ rtw_write8(Adapter, REG_GPIO_MUXCFG, 0x00); ++ ++ DBG_8192C("BT Set RfReg0x1E[7:4] = 0x%x \n", pbtpriv->BtRfRegOrigin1E); ++ PHY_SetRFReg(Adapter, PathA, 0x1e, 0xf0, pbtpriv->BtRfRegOrigin1E); ++ //RTPRINT(FBT, BT_TRACE, ("BT Set RfReg0x1F[7:4] = 0x%x \n", pHalData->bt_coexist.BtRfRegOrigin1F)); ++ //PHY_SetRFReg(Adapter, PathA, 0x1f, 0xf0, pHalData->bt_coexist.BtRfRegOrigin1F); ++ ++ // BT coexistence mechanism does not control EDCA parameter since BT is disabled. ++ //pbtpriv->BtEdcaUL = 0; ++ //pbtpriv->BtEdcaDL = 0; ++ pbtpriv->BT_EDCA[UP_LINK] = 0; ++ pbtpriv->BT_EDCA[DOWN_LINK] = 0; ++ ++ ++// 20100427 Joseph: Do not adjust Rate adaptive for BT coexist suggested by SD3. ++#if 0 ++ RTPRINT(FBT, BT_TRACE, ("BT_Update Rate table\n")); ++ if(pMgntInfo->bUseRAMask) ++ { ++ // 20100407 Joseph: Fix rate adaptive modification for BT coexist. ++ // This fix is not complete yet. It shall also consider VWifi and Adhoc case, ++ // which connect with multiple STAs. ++ Adapter->HalFunc.UpdateHalRAMaskHandler( ++ Adapter, ++ FALSE, ++ 0, ++ NULL, ++ NULL, ++ pMgntInfo->RateAdaptive.RATRState, ++ RAMask_Normal); ++ } ++ else ++ { ++ Adapter->HalFunc.UpdateHalRATRTableHandler( ++ Adapter, ++ &pMgntInfo->dot11OperationalRateSet, ++ pMgntInfo->dot11HTOperationalRateSet,NULL); ++ } ++#endif ++ } ++ } ++ } ++} ++ ++static void dm_InitBtCoexistDM( PADAPTER Adapter) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ struct btcoexist_priv *pbtpriv = &(pHalData->bt_coexist); ++ ++ if( !pbtpriv->BT_Coexist ) return; ++ ++ pbtpriv->BtRfRegOrigin1E = (u8)PHY_QueryRFReg(Adapter, PathA, 0x1e, 0xf0); ++ pbtpriv->BtRfRegOrigin1F = (u8)PHY_QueryRFReg(Adapter, PathA, 0x1f, 0xf0); ++} ++ ++void rtl8192c_set_dm_bt_coexist(_adapter *padapter, u8 bStart) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ struct btcoexist_priv *pbtpriv = &(pHalData->bt_coexist); ++ ++ pbtpriv->bCOBT = bStart; ++ send_delba(padapter,0, get_my_bssid(&(pmlmeinfo->network))); ++ send_delba(padapter,1, get_my_bssid(&(pmlmeinfo->network))); ++ ++} ++ ++void rtl8192c_issue_delete_ba(_adapter *padapter, u8 dir) ++{ ++ struct mlme_ext_info *pmlmeinfo = &padapter->mlmeextpriv.mlmext_info; ++ DBG_8192C("issue_delete_ba : %s...\n",(dir==0)?"RX_DIR":"TX_DIR"); ++ send_delba(padapter,dir, get_my_bssid(&(pmlmeinfo->network))); ++} ++ ++#endif ++ ++#if 0//def CONFIG_PCI_HCI ++ ++BOOLEAN ++BT_BTStateChange( ++ IN PADAPTER Adapter ++ ) ++{ ++ PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); ++ PMGNT_INFO pMgntInfo = &Adapter->MgntInfo; ++ ++ u4Byte temp, Polling, Ratio_Tx, Ratio_PRI; ++ u4Byte BT_Tx, BT_PRI; ++ u1Byte BT_State; ++ static u1Byte ServiceTypeCnt = 0; ++ u1Byte CurServiceType; ++ static u1Byte LastServiceType = BT_Idle; ++ ++ if(!pMgntInfo->bMediaConnect) ++ return FALSE; ++ ++ BT_State = PlatformEFIORead1Byte(Adapter, 0x4fd); ++/* ++ temp = PlatformEFIORead4Byte(Adapter, 0x488); ++ BT_Tx = (u2Byte)(((temp<<8)&0xff00)+((temp>>8)&0xff)); ++ BT_PRI = (u2Byte)(((temp>>8)&0xff00)+((temp>>24)&0xff)); ++ ++ temp = PlatformEFIORead4Byte(Adapter, 0x48c); ++ Polling = ((temp<<8)&0xff000000) + ((temp>>8)&0x00ff0000) + ++ ((temp<<8)&0x0000ff00) + ((temp>>8)&0x000000ff); ++ ++*/ ++ BT_Tx = PlatformEFIORead4Byte(Adapter, 0x488); ++ ++ RTPRINT(FBT, BT_TRACE, ("Ratio 0x488 =%x\n", BT_Tx)); ++ BT_Tx =BT_Tx & 0x00ffffff; ++ //RTPRINT(FBT, BT_TRACE, ("Ratio BT_Tx =%x\n", BT_Tx)); ++ ++ BT_PRI = PlatformEFIORead4Byte(Adapter, 0x48c); ++ ++ RTPRINT(FBT, BT_TRACE, ("Ratio Ratio 0x48c =%x\n", BT_PRI)); ++ BT_PRI =BT_PRI & 0x00ffffff; ++ //RTPRINT(FBT, BT_TRACE, ("Ratio BT_PRI =%x\n", BT_PRI)); ++ ++ ++ Polling = PlatformEFIORead4Byte(Adapter, 0x490); ++ //RTPRINT(FBT, BT_TRACE, ("Ratio 0x490 =%x\n", Polling)); ++ ++ ++ if(BT_Tx==0xffffffff && BT_PRI==0xffffffff && Polling==0xffffffffff && BT_State==0xff) ++ return FALSE; ++ ++ BT_State &= BIT0; ++ ++ if(BT_State != pHalData->bt_coexist.BT_CUR_State) ++ { ++ pHalData->bt_coexist.BT_CUR_State = BT_State; ++ ++ if(pMgntInfo->bRegBT_Sco == 3) ++ { ++ ServiceTypeCnt = 0; ++ ++ pHalData->bt_coexist.BT_Service = BT_Idle; ++ ++ RTPRINT(FBT, BT_TRACE, ("BT_%s\n", BT_State?"ON":"OFF")); ++ ++ BT_State = BT_State | ++ ((pHalData->bt_coexist.BT_Ant_isolation==1)?0:BIT1) |BIT2; ++ ++ PlatformEFIOWrite1Byte(Adapter, 0x4fd, BT_State); ++ RTPRINT(FBT, BT_TRACE, ("BT set 0x4fd to %x\n", BT_State)); ++ } ++ ++ return TRUE; ++ } ++ RTPRINT(FBT, BT_TRACE, ("bRegBT_Sco %d\n", pMgntInfo->bRegBT_Sco)); ++ ++ Ratio_Tx = BT_Tx*1000/Polling; ++ Ratio_PRI = BT_PRI*1000/Polling; ++ ++ pHalData->bt_coexist.Ratio_Tx=Ratio_Tx; ++ pHalData->bt_coexist.Ratio_PRI=Ratio_PRI; ++ ++ RTPRINT(FBT, BT_TRACE, ("Ratio_Tx=%d\n", Ratio_Tx)); ++ RTPRINT(FBT, BT_TRACE, ("Ratio_PRI=%d\n", Ratio_PRI)); ++ ++ ++ if(BT_State && pMgntInfo->bRegBT_Sco==3) ++ { ++ RTPRINT(FBT, BT_TRACE, ("bRegBT_Sco ==3 Follow Counter\n")); ++// if(BT_Tx==0xffff && BT_PRI==0xffff && Polling==0xffffffff) ++// { ++// ServiceTypeCnt = 0; ++// return FALSE; ++// } ++// else ++ { ++ /* ++ Ratio_Tx = BT_Tx*1000/Polling; ++ Ratio_PRI = BT_PRI*1000/Polling; ++ ++ pHalData->bt_coexist.Ratio_Tx=Ratio_Tx; ++ pHalData->bt_coexist.Ratio_PRI=Ratio_PRI; ++ ++ RTPRINT(FBT, BT_TRACE, ("Ratio_Tx=%d\n", Ratio_Tx)); ++ RTPRINT(FBT, BT_TRACE, ("Ratio_PRI=%d\n", Ratio_PRI)); ++ ++ */ ++ if((Ratio_Tx <= 50) && (Ratio_PRI <= 50)) ++ CurServiceType = BT_Idle; ++ else if((Ratio_PRI > 150) && (Ratio_PRI < 200)) ++ CurServiceType = BT_SCO; ++ else if((Ratio_Tx >= 200)&&(Ratio_PRI >= 200)) ++ CurServiceType = BT_Busy; ++ else if(Ratio_Tx >= 350) ++ CurServiceType = BT_OtherBusy; ++ else ++ CurServiceType=BT_OtherAction; ++ ++ } ++/* if(pHalData->bt_coexist.bStopCount) ++ { ++ ServiceTypeCnt=0; ++ pHalData->bt_coexist.bStopCount=FALSE; ++ } ++*/ ++ if(CurServiceType == BT_OtherBusy) ++ { ++ ServiceTypeCnt=2; ++ LastServiceType=CurServiceType; ++ } ++ else if(CurServiceType == LastServiceType) ++ { ++ if(ServiceTypeCnt<3) ++ ServiceTypeCnt++; ++ } ++ else ++ { ++ ServiceTypeCnt = 0; ++ LastServiceType = CurServiceType; ++ } ++ ++ if(ServiceTypeCnt==2) ++ { ++ pHalData->bt_coexist.BT_Service = LastServiceType; ++ BT_State = BT_State | ++ ((pHalData->bt_coexist.BT_Ant_isolation==1)?0:BIT1) | ++ ((pHalData->bt_coexist.BT_Service==BT_SCO)?0:BIT2); ++ ++ if(pHalData->bt_coexist.BT_Service==BT_Busy) ++ BT_State&= ~(BIT2); ++ ++ if(pHalData->bt_coexist.BT_Service==BT_SCO) ++ { ++ RTPRINT(FBT, BT_TRACE, ("BT TYPE Set to ==> BT_SCO\n")); ++ } ++ else if(pHalData->bt_coexist.BT_Service==BT_Idle) ++ { ++ RTPRINT(FBT, BT_TRACE, ("BT TYPE Set to ==> BT_Idle\n")); ++ } ++ else if(pHalData->bt_coexist.BT_Service==BT_OtherAction) ++ { ++ RTPRINT(FBT, BT_TRACE, ("BT TYPE Set to ==> BT_OtherAction\n")); ++ } ++ else if(pHalData->bt_coexist.BT_Service==BT_Busy) ++ { ++ RTPRINT(FBT, BT_TRACE, ("BT TYPE Set to ==> BT_Busy\n")); ++ } ++ else ++ { ++ RTPRINT(FBT, BT_TRACE, ("BT TYPE Set to ==> BT_OtherBusy\n")); ++ } ++ ++ //Add interrupt migration when bt is not in idel state (no traffic). ++ //suggestion by Victor. ++ if(pHalData->bt_coexist.BT_Service!=BT_Idle) ++ { ++ ++ PlatformEFIOWrite2Byte(Adapter, 0x504, 0x0ccc); ++ PlatformEFIOWrite1Byte(Adapter, 0x506, 0x54); ++ PlatformEFIOWrite1Byte(Adapter, 0x507, 0x54); ++ ++ } ++ else ++ { ++ PlatformEFIOWrite1Byte(Adapter, 0x506, 0x00); ++ PlatformEFIOWrite1Byte(Adapter, 0x507, 0x00); ++ } ++ ++ PlatformEFIOWrite1Byte(Adapter, 0x4fd, BT_State); ++ RTPRINT(FBT, BT_TRACE, ("BT_SCO set 0x4fd to %x\n", BT_State)); ++ return TRUE; ++ } ++ } ++ ++ return FALSE; ++ ++} ++ ++BOOLEAN ++BT_WifiConnectChange( ++ IN PADAPTER Adapter ++ ) ++{ ++ PMGNT_INFO pMgntInfo = &Adapter->MgntInfo; ++ static BOOLEAN bMediaConnect = FALSE; ++ ++ if(!pMgntInfo->bMediaConnect || MgntRoamingInProgress(pMgntInfo)) ++ { ++ bMediaConnect = FALSE; ++ } ++ else ++ { ++ if(!bMediaConnect) ++ { ++ bMediaConnect = TRUE; ++ return TRUE; ++ } ++ bMediaConnect = TRUE; ++ } ++ ++ return FALSE; ++} ++ ++BOOLEAN ++BT_RSSIChangeWithAMPDU( ++ IN PADAPTER Adapter ++ ) ++{ ++ PMGNT_INFO pMgntInfo = &Adapter->MgntInfo; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ ++ if(!Adapter->pNdisCommon->bRegBT_Ampdu || !Adapter->pNdisCommon->bRegAcceptAddbaReq) ++ return FALSE; ++ ++ RTPRINT(FBT, BT_TRACE, ("RSSI is %d\n",pHalData->UndecoratedSmoothedPWDB)); ++ ++ if((pHalData->UndecoratedSmoothedPWDB<=32) && pMgntInfo->pHTInfo->bAcceptAddbaReq) ++ { ++ RTPRINT(FBT, BT_TRACE, ("BT_Disallow AMPDU RSSI <=32 Need change\n")); ++ return TRUE; ++ ++ } ++ else if((pHalData->UndecoratedSmoothedPWDB>=40) && !pMgntInfo->pHTInfo->bAcceptAddbaReq ) ++ { ++ RTPRINT(FBT, BT_TRACE, ("BT_Allow AMPDU RSSI >=40, Need change\n")); ++ return TRUE; ++ } ++ else ++ return FALSE; ++ ++} ++ ++ ++VOID ++dm_BTCoexist( ++ IN PADAPTER Adapter ++ ) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ PMGNT_INFO pMgntInfo = &Adapter->MgntInfo; ++ static u1Byte LastTxPowerLvl = 0xff; ++ PRX_TS_RECORD pRxTs = NULL; ++ ++ BOOLEAN bWifiConnectChange, bBtStateChange,bRSSIChangeWithAMPDU; ++ ++ if( (pHalData->bt_coexist.BluetoothCoexist) && ++ (pHalData->bt_coexist.BT_CoexistType == BT_CSR_BC4) && ++ (!ACTING_AS_AP(Adapter)) ) ++ { ++ bWifiConnectChange = BT_WifiConnectChange(Adapter); ++ bBtStateChange = BT_BTStateChange(Adapter); ++ bRSSIChangeWithAMPDU = BT_RSSIChangeWithAMPDU(Adapter); ++ RTPRINT(FBT, BT_TRACE, ("bWifiConnectChange %d, bBtStateChange %d,LastTxPowerLvl %x, DynamicTxHighPowerLvl %x\n", ++ bWifiConnectChange,bBtStateChange,LastTxPowerLvl,pHalData->DynamicTxHighPowerLvl)); ++ if( bWifiConnectChange ||bBtStateChange || ++ (LastTxPowerLvl != pHalData->DynamicTxHighPowerLvl) ||bRSSIChangeWithAMPDU) ++ { ++ LastTxPowerLvl = pHalData->DynamicTxHighPowerLvl; ++ ++ if(pHalData->bt_coexist.BT_CUR_State) ++ { ++ // Do not allow receiving A-MPDU aggregation. ++ if((pHalData->bt_coexist.BT_Service==BT_SCO) || (pHalData->bt_coexist.BT_Service==BT_Busy)) ++ { ++ if(pHalData->UndecoratedSmoothedPWDB<=32) ++ { ++ if(Adapter->pNdisCommon->bRegBT_Ampdu && Adapter->pNdisCommon->bRegAcceptAddbaReq) ++ { ++ RTPRINT(FBT, BT_TRACE, ("BT_Disallow AMPDU RSSI <=32\n")); ++ pMgntInfo->pHTInfo->bAcceptAddbaReq = FALSE; ++ if(GetTs(Adapter, (PTS_COMMON_INFO*)(&pRxTs), pMgntInfo->Bssid, 0, RX_DIR, FALSE)) ++ TsInitDelBA(Adapter, (PTS_COMMON_INFO)pRxTs, RX_DIR); ++ } ++ } ++ else if(pHalData->UndecoratedSmoothedPWDB>=40) ++ { ++ if(Adapter->pNdisCommon->bRegBT_Ampdu && Adapter->pNdisCommon->bRegAcceptAddbaReq) ++ { ++ RTPRINT(FBT, BT_TRACE, ("BT_Allow AMPDU RSSI >=40\n")); ++ pMgntInfo->pHTInfo->bAcceptAddbaReq = TRUE; ++ } ++ } ++ } ++ else ++ { ++ if(Adapter->pNdisCommon->bRegBT_Ampdu && Adapter->pNdisCommon->bRegAcceptAddbaReq) ++ { ++ RTPRINT(FBT, BT_TRACE, ("BT_Allow AMPDU BT not in SCO or BUSY\n")); ++ pMgntInfo->pHTInfo->bAcceptAddbaReq = TRUE; ++ } ++ } ++ ++ if(pHalData->bt_coexist.BT_Ant_isolation) ++ { ++ RTPRINT(FBT, BT_TRACE, ("BT_IsolationLow\n")); ++ RTPRINT(FBT, BT_TRACE, ("BT_Update Rate table\n")); ++ Adapter->HalFunc.UpdateHalRATRTableHandler( ++ Adapter, ++ &pMgntInfo->dot11OperationalRateSet, ++ pMgntInfo->dot11HTOperationalRateSet,NULL); ++ ++ if(pHalData->bt_coexist.BT_Service==BT_SCO) ++ { ++ ++ RTPRINT(FBT, BT_TRACE, ("BT_Turn OFF Coexist with SCO \n")); ++ PlatformEFIOWrite1Byte(Adapter, REG_GPIO_MUXCFG, 0x14); ++ } ++ else if(pHalData->DynamicTxHighPowerLvl == TxHighPwrLevel_Normal) ++ { ++ RTPRINT(FBT, BT_TRACE, ("BT_Turn ON Coexist\n")); ++ PlatformEFIOWrite1Byte(Adapter, REG_GPIO_MUXCFG, 0xb4); ++ } ++ else ++ { ++ RTPRINT(FBT, BT_TRACE, ("BT_Turn OFF Coexist\n")); ++ PlatformEFIOWrite1Byte(Adapter, REG_GPIO_MUXCFG, 0x14); ++ } ++ } ++ else ++ { ++ RTPRINT(FBT, BT_TRACE, ("BT_IsolationHigh\n")); ++ // Do nothing. ++ } ++ } ++ else ++ { ++ if(Adapter->pNdisCommon->bRegBT_Ampdu && Adapter->pNdisCommon->bRegAcceptAddbaReq) ++ { ++ RTPRINT(FBT, BT_TRACE, ("BT_Allow AMPDU bt is off\n")); ++ pMgntInfo->pHTInfo->bAcceptAddbaReq = TRUE; ++ } ++ ++ RTPRINT(FBT, BT_TRACE, ("BT_Turn OFF Coexist bt is off \n")); ++ PlatformEFIOWrite1Byte(Adapter, REG_GPIO_MUXCFG, 0x14); ++ ++ RTPRINT(FBT, BT_TRACE, ("BT_Update Rate table\n")); ++ Adapter->HalFunc.UpdateHalRATRTableHandler( ++ Adapter, ++ &pMgntInfo->dot11OperationalRateSet, ++ pMgntInfo->dot11HTOperationalRateSet,NULL); ++ } ++ } ++ } ++} ++#endif ++ ++ ++/*----------------------------------------------------------------------------- ++ * Function: dm_CheckRfCtrlGPIO() ++ * ++ * Overview: Copy 8187B template for 9xseries. ++ * ++ * Input: NONE ++ * ++ * Output: NONE ++ * ++ * Return: NONE ++ * ++ * Revised History: ++ * When Who Remark ++ * 01/10/2008 MHC Create Version 0. ++ * ++ *---------------------------------------------------------------------------*/ ++static VOID ++dm_CheckRfCtrlGPIO( ++ IN PADAPTER Adapter ++ ) ++{ ++#if 0 ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++#if defined (CONFIG_USB_HCI) || defined (CONFIG_SDIO_HCI) ++ #ifdef CONFIG_USB_HCI ++ // 2010/08/12 MH Add for CU selective suspend. ++ PRT_USB_DEVICE pDevice = GET_RT_USB_DEVICE(Adapter); ++ #else ++ PRT_SDIO_DEVICE pDevice = GET_RT_SDIO_DEVICE(Adapter); ++ #endif ++#endif ++ ++ if(!Adapter->MgntInfo.PowerSaveControl.bGpioRfSw) ++ return; ++ ++ RTPRINT(FPWR, PWRHW, ("dm_CheckRfCtrlGPIO \n")); ++ ++#if defined (CONFIG_USB_HCI) || defined (CONFIG_SDIO_HCI) ++ // Walk around for DTM test, we will not enable HW - radio on/off because r/w ++ // page 1 register before Lextra bus is enabled cause system fails when resuming ++ // from S4. 20080218, Emily ++ if(Adapter->bInHctTest) ++ return; ++ ++//#if ((HAL_CODE_BASE == RTL8192_S) ) ++ //Adapter->HalFunc.GPIOChangeRFHandler(Adapter, GPIORF_POLLING); ++//#else ++ // 2010/07/27 MH Only Minicard and support selective suspend, we can not turn off all MAC power to ++ // stop 8051. For dongle and minicard, we both support selective suspend mode. ++ //if(pDevice->RegUsbSS && Adapter->HalFunc.GetInterfaceSelectionHandler(Adapter) == INTF_SEL2_MINICARD) ++ ++ // ++ // 2010/08/12 MH We support severl power consumption combination as below. ++ // ++ // Power consumption combination ++ // SS Enable: (LPS disable + IPS + SW/HW radio off) ++ // 1. Dongle + PDN (support HW radio off) ++ // 2. Dongle + Normal (No HW radio off) ++ // 3. MiniCard + PDN (support HW radio off) ++ // 4. MiniCard + Normal (support HW radio off) ++ // ++ // SS Disable: (LPS + IPS + SW/HW radio off) ++ // 1. Dongle + PDN (support HW radio off) ++ // 2. Dongle + Normal (No HW radio off) ++ // 3. MiniCard + PDN (support HW radio off) ++ // 4. MiniCard + Normal (support HW radio off) ++ // ++ // For Power down module detection. We need to read power register no matter ++ // dongle or minicard, we will add the item is the detection method. ++ // ++ // ++ //vivi add du case ++ if ((IS_HARDWARE_TYPE_8192CU(Adapter)||IS_HARDWARE_TYPE_8192DU(Adapter)) ++ && pDevice->RegUsbSS) ++ { ++ RT_TRACE(COMP_RF, DBG_LOUD, ("USB SS Enabled\n")); ++ if (SUPPORT_HW_RADIO_DETECT(Adapter)) ++ { // Support HW radio detection ++ RT_TRACE(COMP_RF, DBG_LOUD, ("USB Card Type 2/3/4 support GPIO Detect\n")); ++ GpioDetectTimerStart(Adapter); ++ } ++ else ++ { // Dongle does not support HW radio detection.?? In the fufure?? ++ RT_TRACE(COMP_RF, DBG_LOUD, ("USB DONGLE Non-GPIO-Detect\n")); ++ } ++ } ++ else if (IS_HARDWARE_TYPE_8192CU(Adapter) || ++ IS_HARDWARE_TYPE_8723U(Adapter)|| ++ IS_HARDWARE_TYPE_8192DU(Adapter) || ++ IS_HARDWARE_TYPE_8723S(Adapter)) ++ { // Not support Selective suspend ++ RT_TRACE(COMP_RF, DBG_LOUD, ("USB SS Disable\n")); ++ if (SUPPORT_HW_RADIO_DETECT(Adapter)) ++ { ++ RT_TRACE(COMP_RF, DBG_LOUD, ("USB Card Type 2/3/4 support GPIO Detect\n")); ++ PlatformScheduleWorkItem( &(pHalData->GPIOChangeRFWorkItem) ); ++ } ++ else ++ { ++ RT_TRACE(COMP_RF, DBG_LOUD, ("USB DONGLE Non-GPIO-Detect\n")); ++ } ++ } ++ else ++ { // CE only support noemal HW radio detection now. Support timers GPIO detection in SE/CU. ++ PlatformScheduleWorkItem( &(pHalData->GPIOChangeRFWorkItem) ); ++ } ++//#endif ++#else if defined CONFIG_PCI_HCI ++ if(Adapter->bInHctTest) ++ return; ++ ++ // CE only support noemal HW radio detection now. We support timers GPIO detection in SE. ++ PlatformScheduleWorkItem( &(pHalData->GPIOChangeRFWorkItem) ); ++#endif ++#endif ++} /* dm_CheckRfCtrlGPIO */ ++ ++static VOID ++dm_InitRateAdaptiveMask( ++ IN PADAPTER Adapter ++ ) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ struct dm_priv *pdmpriv = &pHalData->dmpriv; ++ PRATE_ADAPTIVE pRA = (PRATE_ADAPTIVE)&pdmpriv->RateAdaptive; ++ ++ pRA->RATRState = DM_RATR_STA_INIT; ++ pRA->PreRATRState = DM_RATR_STA_INIT; ++ ++ if (pdmpriv->DM_Type == DM_Type_ByDriver) ++ pdmpriv->bUseRAMask = _TRUE; ++ else ++ pdmpriv->bUseRAMask = _FALSE; ++} ++ ++/*----------------------------------------------------------------------------- ++ * Function: dm_RefreshRateAdaptiveMask() ++ * ++ * Overview: Update rate table mask according to rssi ++ * ++ * Input: NONE ++ * ++ * Output: NONE ++ * ++ * Return: NONE ++ * ++ * Revised History: ++ * When Who Remark ++ * 05/27/2009 hpfan Create Version 0. ++ * ++ *---------------------------------------------------------------------------*/ ++static VOID ++dm_RefreshRateAdaptiveMask( IN PADAPTER pAdapter) ++{ ++#if 0 ++ PADAPTER pTargetAdapter; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); ++ PMGNT_INFO pMgntInfo = &(ADJUST_TO_ADAPTIVE_ADAPTER(pAdapter, TRUE)->MgntInfo); ++ PRATE_ADAPTIVE pRA = (PRATE_ADAPTIVE)&pMgntInfo->RateAdaptive; ++ u4Byte LowRSSIThreshForRA = 0, HighRSSIThreshForRA = 0; ++ ++ if(pAdapter->bDriverStopped) ++ { ++ RT_TRACE(COMP_RATR, DBG_TRACE, ("<---- dm_RefreshRateAdaptiveMask(): driver is going to unload\n")); ++ return; ++ } ++ ++ if(!pMgntInfo->bUseRAMask) ++ { ++ RT_TRACE(COMP_RATR, DBG_LOUD, ("<---- dm_RefreshRateAdaptiveMask(): driver does not control rate adaptive mask\n")); ++ return; ++ } ++ ++ // if default port is connected, update RA table for default port (infrastructure mode only) ++ if(pAdapter->MgntInfo.mAssoc && (!ACTING_AS_AP(pAdapter))) ++ { ++ ++ // decide rastate according to rssi ++ switch (pRA->PreRATRState) ++ { ++ case DM_RATR_STA_HIGH: ++ HighRSSIThreshForRA = 50; ++ LowRSSIThreshForRA = 20; ++ break; ++ ++ case DM_RATR_STA_MIDDLE: ++ HighRSSIThreshForRA = 55; ++ LowRSSIThreshForRA = 20; ++ break; ++ ++ case DM_RATR_STA_LOW: ++ HighRSSIThreshForRA = 50; ++ LowRSSIThreshForRA = 25; ++ break; ++ ++ default: ++ HighRSSIThreshForRA = 50; ++ LowRSSIThreshForRA = 20; ++ break; ++ } ++ ++ if(pHalData->UndecoratedSmoothedPWDB > (s4Byte)HighRSSIThreshForRA) ++ pRA->RATRState = DM_RATR_STA_HIGH; ++ else if(pHalData->UndecoratedSmoothedPWDB > (s4Byte)LowRSSIThreshForRA) ++ pRA->RATRState = DM_RATR_STA_MIDDLE; ++ else ++ pRA->RATRState = DM_RATR_STA_LOW; ++ ++ if(pRA->PreRATRState != pRA->RATRState) ++ { ++ RT_PRINT_ADDR(COMP_RATR, DBG_LOUD, ("Target AP addr : "), pMgntInfo->Bssid); ++ RT_TRACE(COMP_RATR, DBG_LOUD, ("RSSI = %d\n", pHalData->UndecoratedSmoothedPWDB)); ++ RT_TRACE(COMP_RATR, DBG_LOUD, ("RSSI_LEVEL = %d\n", pRA->RATRState)); ++ RT_TRACE(COMP_RATR, DBG_LOUD, ("PreState = %d, CurState = %d\n", pRA->PreRATRState, pRA->RATRState)); ++ pAdapter->HalFunc.UpdateHalRAMaskHandler( ++ pAdapter, ++ FALSE, ++ 0, ++ NULL, ++ NULL, ++ pRA->RATRState); ++ pRA->PreRATRState = pRA->RATRState; ++ } ++ } ++ ++ // ++ // The following part configure AP/VWifi/IBSS rate adaptive mask. ++ // ++ if(ACTING_AS_AP(pAdapter) || ACTING_AS_IBSS(pAdapter)) ++ { ++ pTargetAdapter = pAdapter; ++ } ++ else ++ { ++ pTargetAdapter = ADJUST_TO_ADAPTIVE_ADAPTER(pAdapter, FALSE); ++ if(!ACTING_AS_AP(pTargetAdapter)) ++ pTargetAdapter = NULL; ++ } ++ ++ // if extension port (softap) is started, updaet RA table for more than one clients associate ++ if(pTargetAdapter != NULL) ++ { ++ int i; ++ PRT_WLAN_STA pEntry; ++ PRATE_ADAPTIVE pEntryRA; ++ ++ for(i = 0; i < ASSOCIATE_ENTRY_NUM; i++) ++ { ++ if( pTargetAdapter->MgntInfo.AsocEntry[i].bUsed && pTargetAdapter->MgntInfo.AsocEntry[i].bAssociated) ++ { ++ pEntry = pTargetAdapter->MgntInfo.AsocEntry+i; ++ pEntryRA = &pEntry->RateAdaptive; ++ ++ switch (pEntryRA->PreRATRState) ++ { ++ case DM_RATR_STA_HIGH: ++ { ++ HighRSSIThreshForRA = 50; ++ LowRSSIThreshForRA = 20; ++ } ++ break; ++ ++ case DM_RATR_STA_MIDDLE: ++ { ++ HighRSSIThreshForRA = 55; ++ LowRSSIThreshForRA = 20; ++ } ++ break; ++ ++ case DM_RATR_STA_LOW: ++ { ++ HighRSSIThreshForRA = 50; ++ LowRSSIThreshForRA = 25; ++ } ++ break; ++ ++ default: ++ { ++ HighRSSIThreshForRA = 50; ++ LowRSSIThreshForRA = 20; ++ } ++ } ++ ++ if(pEntry->rssi_stat.UndecoratedSmoothedPWDB > (s4Byte)HighRSSIThreshForRA) ++ pEntryRA->RATRState = DM_RATR_STA_HIGH; ++ else if(pEntry->rssi_stat.UndecoratedSmoothedPWDB > (s4Byte)LowRSSIThreshForRA) ++ pEntryRA->RATRState = DM_RATR_STA_MIDDLE; ++ else ++ pEntryRA->RATRState = DM_RATR_STA_LOW; ++ ++ if(pEntryRA->PreRATRState != pEntryRA->RATRState) ++ { ++ RT_PRINT_ADDR(COMP_RATR, DBG_LOUD, ("AsocEntry addr : "), pEntry->MacAddr); ++ RT_TRACE(COMP_RATR, DBG_LOUD, ("RSSI = %d\n", pEntry->rssi_stat.UndecoratedSmoothedPWDB)); ++ RT_TRACE(COMP_RATR, DBG_LOUD, ("RSSI_LEVEL = %d\n", pEntryRA->RATRState)); ++ RT_TRACE(COMP_RATR, DBG_LOUD, ("PreState = %d, CurState = %d\n", pEntryRA->PreRATRState, pEntryRA->RATRState)); ++ pAdapter->HalFunc.UpdateHalRAMaskHandler( ++ pTargetAdapter, ++ FALSE, ++ pEntry->AID+1, ++ pEntry->MacAddr, ++ pEntry, ++ pEntryRA->RATRState); ++ pEntryRA->PreRATRState = pEntryRA->RATRState; ++ } ++ ++ } ++ } ++ } ++#endif ++} ++ ++static VOID ++dm_CheckProtection( ++ IN PADAPTER Adapter ++ ) ++{ ++#if 0 ++ PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo); ++ u1Byte CurRate, RateThreshold; ++ ++ if(pMgntInfo->pHTInfo->bCurBW40MHz) ++ RateThreshold = MGN_MCS1; ++ else ++ RateThreshold = MGN_MCS3; ++ ++ if(Adapter->TxStats.CurrentInitTxRate <= RateThreshold) ++ { ++ pMgntInfo->bDmDisableProtect = TRUE; ++ DbgPrint("Forced disable protect: %x\n", Adapter->TxStats.CurrentInitTxRate); ++ } ++ else ++ { ++ pMgntInfo->bDmDisableProtect = FALSE; ++ DbgPrint("Enable protect: %x\n", Adapter->TxStats.CurrentInitTxRate); ++ } ++#endif ++} ++ ++static VOID ++dm_CheckStatistics( ++ IN PADAPTER Adapter ++ ) ++{ ++#if 0 ++ if(!Adapter->MgntInfo.bMediaConnect) ++ return; ++ ++ //2008.12.10 tynli Add for getting Current_Tx_Rate_Reg flexibly. ++ Adapter->HalFunc.GetHwRegHandler( Adapter, HW_VAR_INIT_TX_RATE, (pu1Byte)(&Adapter->TxStats.CurrentInitTxRate) ); ++ ++ // Calculate current Tx Rate(Successful transmited!!) ++ ++ // Calculate current Rx Rate(Successful received!!) ++ ++ //for tx tx retry count ++ Adapter->HalFunc.GetHwRegHandler( Adapter, HW_VAR_RETRY_COUNT, (pu1Byte)(&Adapter->TxStats.NumTxRetryCount) ); ++#endif ++} ++ ++static void dm_CheckPbcGPIO(_adapter *padapter) ++{ ++ u8 tmp1byte; ++ u8 bPbcPressed = _FALSE; ++ ++ if(!padapter->registrypriv.hw_wps_pbc) ++ return; ++ ++#ifdef CONFIG_USB_HCI ++ tmp1byte = rtw_read8(padapter, GPIO_IO_SEL); ++ tmp1byte |= (HAL_8192C_HW_GPIO_WPS_BIT); ++ rtw_write8(padapter, GPIO_IO_SEL, tmp1byte); //enable GPIO[2] as output mode ++ ++ tmp1byte &= ~(HAL_8192C_HW_GPIO_WPS_BIT); ++ rtw_write8(padapter, GPIO_IN, tmp1byte); //reset the floating voltage level ++ ++ tmp1byte = rtw_read8(padapter, GPIO_IO_SEL); ++ tmp1byte &= ~(HAL_8192C_HW_GPIO_WPS_BIT); ++ rtw_write8(padapter, GPIO_IO_SEL, tmp1byte); //enable GPIO[2] as input mode ++ ++ tmp1byte =rtw_read8(padapter, GPIO_IN); ++ ++ if (tmp1byte == 0xff) ++ return ; ++ ++ if (tmp1byte&HAL_8192C_HW_GPIO_WPS_BIT) ++ { ++ bPbcPressed = _TRUE; ++ } ++#else ++ tmp1byte = rtw_read8(padapter, GPIO_IN); ++ //RT_TRACE(COMP_IO, DBG_TRACE, ("dm_CheckPbcGPIO - %x\n", tmp1byte)); ++ ++ if (tmp1byte == 0xff || padapter->init_adpt_in_progress) ++ return ; ++ ++ if((tmp1byte&HAL_8192C_HW_GPIO_WPS_BIT)==0) ++ { ++ bPbcPressed = _TRUE; ++ } ++#endif ++ ++ if( _TRUE == bPbcPressed) ++ { ++ // Here we only set bPbcPressed to true ++ // After trigger PBC, the variable will be set to false ++ DBG_8192C("CheckPbcGPIO - PBC is pressed\n"); ++ ++#ifdef RTK_DMP_PLATFORM ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,12)) ++ kobject_uevent(&padapter->pnetdev->dev.kobj, KOBJ_NET_PBC); ++#else ++ kobject_hotplug(&padapter->pnetdev->class_dev.kobj, KOBJ_NET_PBC); ++#endif ++#else ++ ++ if ( padapter->pid[0] == 0 ) ++ { // 0 is the default value and it means the application monitors the HW PBC doesn't privde its pid to driver. ++ return; ++ } ++ ++#ifdef PLATFORM_LINUX ++ rtw_signal_process(padapter->pid[0], SIGUSR1); ++#endif ++#endif ++ } ++} ++ ++#ifdef CONFIG_PCI_HCI ++// ++// Description: ++// Perform interrupt migration dynamically to reduce CPU utilization. ++// ++// Assumption: ++// 1. Do not enable migration under WIFI test. ++// ++// Created by Roger, 2010.03.05. ++// ++VOID ++dm_InterruptMigration( ++ IN PADAPTER Adapter ++ ) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ struct mlme_priv *pmlmepriv = &(Adapter->mlmepriv); ++ BOOLEAN bCurrentIntMt, bCurrentACIntDisable; ++ BOOLEAN IntMtToSet = _FALSE; ++ BOOLEAN ACIntToSet = _FALSE; ++ ++ ++ // Retrieve current interrupt migration and Tx four ACs IMR settings first. ++ bCurrentIntMt = pHalData->bInterruptMigration; ++ bCurrentACIntDisable = pHalData->bDisableTxInt; ++ ++ // ++ // Currently we use busy traffic for reference instead of RxIntOK counts to prevent non-linear Rx statistics ++ // when interrupt migration is set before. 2010.03.05. ++ // ++ if(!Adapter->registrypriv.wifi_spec && ++ (check_fwstate(pmlmepriv, _FW_LINKED)== _TRUE) && ++ pmlmepriv->LinkDetectInfo.bHigherBusyTraffic) ++ { ++ IntMtToSet = _TRUE; ++ ++ // To check whether we should disable Tx interrupt or not. ++ if(pmlmepriv->LinkDetectInfo.bHigherBusyRxTraffic ) ++ ACIntToSet = _TRUE; ++ } ++ ++ //Update current settings. ++ if( bCurrentIntMt != IntMtToSet ){ ++ DBG_8192C("%s(): Update interrrupt migration(%d)\n",__FUNCTION__,IntMtToSet); ++ if(IntMtToSet) ++ { ++ // ++ // Set interrrupt migration timer and corresponging Tx/Rx counter. ++ // timer 25ns*0xfa0=100us for 0xf packets. ++ // 2010.03.05. ++ // ++ rtw_write32(Adapter, REG_INT_MIG, 0xff000fa0);// 0x306:Rx, 0x307:Tx ++ pHalData->bInterruptMigration = IntMtToSet; ++ } ++ else ++ { ++ // Reset all interrupt migration settings. ++ rtw_write32(Adapter, REG_INT_MIG, 0); ++ pHalData->bInterruptMigration = IntMtToSet; ++ } ++ } ++ ++ /*if( bCurrentACIntDisable != ACIntToSet ){ ++ DBG_8192C("%s(): Update AC interrrupt(%d)\n",__FUNCTION__,ACIntToSet); ++ if(ACIntToSet) // Disable four ACs interrupts. ++ { ++ // ++ // Disable VO, VI, BE and BK four AC interrupts to gain more efficient CPU utilization. ++ // When extremely highly Rx OK occurs, we will disable Tx interrupts. ++ // 2010.03.05. ++ // ++ UpdateInterruptMask8192CE( Adapter, 0, RT_AC_INT_MASKS ); ++ pHalData->bDisableTxInt = ACIntToSet; ++ } ++ else// Enable four ACs interrupts. ++ { ++ UpdateInterruptMask8192CE( Adapter, RT_AC_INT_MASKS, 0 ); ++ pHalData->bDisableTxInt = ACIntToSet; ++ } ++ }*/ ++ ++} ++ ++#endif ++ ++// ++// Initialize GPIO setting registers ++// ++static void ++dm_InitGPIOSetting( ++ IN PADAPTER Adapter ++ ) ++{ ++ PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); ++ ++ u8 tmp1byte; ++ ++ tmp1byte = rtw_read8(Adapter, REG_GPIO_MUXCFG); ++ tmp1byte &= (GPIOSEL_GPIO | ~GPIOSEL_ENBT); ++ ++#ifdef CONFIG_BT_COEXIST ++ // UMB-B cut bug. We need to support the modification. ++ if (IS_81xxC_VENDOR_UMC_B_CUT(pHalData->VersionID) && ++ pHalData->bt_coexist.BT_Coexist) ++ { ++ tmp1byte |= (BIT5); ++ } ++#endif ++ rtw_write8(Adapter, REG_GPIO_MUXCFG, tmp1byte); ++ ++} ++ ++static void update_EDCA_param(_adapter *padapter) ++{ ++ u32 trafficIndex; ++ u32 edca_param; ++ u64 cur_tx_bytes = 0; ++ u64 cur_rx_bytes = 0; ++ PHAL_DATA_TYPE pHalData = GET_HAL_DATA(padapter); ++ struct dm_priv *pdmpriv = &pHalData->dmpriv; ++ struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); ++ struct recv_priv *precvpriv = &(padapter->recvpriv); ++ struct registry_priv *pregpriv = &padapter->registrypriv; ++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ ++#ifdef CONFIG_BT_COEXIST ++ struct btcoexist_priv *pbtpriv = &(pHalData->bt_coexist); ++ u8 bbtchange = _FALSE; ++#endif ++ ++ ++ //DBG_871X("%s\n", __FUNCTION__); ++ ++ //associated AP ++ if ((pregpriv->wifi_spec == 1) || (pmlmeinfo->HT_enable == 0)) ++ { ++ return; ++ } ++ ++ if (pmlmeinfo->assoc_AP_vendor >= maxAP) ++ { ++ return; ++ } ++ ++ cur_tx_bytes = pxmitpriv->tx_bytes - pxmitpriv->last_tx_bytes; ++ cur_rx_bytes = precvpriv->rx_bytes - precvpriv->last_rx_bytes; ++ ++ //traffic, TX or RX ++ if((pmlmeinfo->assoc_AP_vendor == ralinkAP)||(pmlmeinfo->assoc_AP_vendor == atherosAP)) ++ { ++ if (cur_tx_bytes > (cur_rx_bytes << 2)) ++ { // Uplink TP is present. ++ trafficIndex = UP_LINK; ++ } ++ else ++ { // Balance TP is present. ++ trafficIndex = DOWN_LINK; ++ } ++ } ++ else ++ { ++ if (cur_rx_bytes > (cur_tx_bytes << 2)) ++ { // Downlink TP is present. ++ trafficIndex = DOWN_LINK; ++ } ++ else ++ { // Balance TP is present. ++ trafficIndex = UP_LINK; ++ } ++ } ++ ++#ifdef CONFIG_BT_COEXIST ++ if(pbtpriv->BT_Coexist) ++ { ++ if( (pbtpriv->BT_EDCA[UP_LINK]!=0) || (pbtpriv->BT_EDCA[DOWN_LINK]!=0)) ++ { ++ bbtchange = _TRUE; ++ } ++ } ++#endif ++ ++ if (pdmpriv->prv_traffic_idx != trafficIndex) ++ { ++#if 0 ++#ifdef CONFIG_BT_COEXIST ++ if(_TRUE == bbtchange) ++ rtw_write32(padapter, REG_EDCA_BE_PARAM, pbtpriv->BT_EDCA[trafficIndex]); ++ else ++#endif ++ //adjust EDCA parameter for BE queue ++ //fire_write_MAC_cmd(padapter, EDCA_BE_PARAM, EDCAParam[pmlmeinfo->assoc_AP_vendor][trafficIndex]); ++ rtw_write32(padapter, REG_EDCA_BE_PARAM, EDCAParam[pmlmeinfo->assoc_AP_vendor][trafficIndex]); ++ ++#else ++ if((pmlmeinfo->assoc_AP_vendor == ciscoAP) && (pmlmeext->cur_wireless_mode & WIRELESS_11_24N)) ++ { ++ edca_param = EDCAParam[pmlmeinfo->assoc_AP_vendor][trafficIndex]; ++ } ++ else if((pmlmeinfo->assoc_AP_vendor == airgocapAP) && ++ ((pmlmeext->cur_wireless_mode == WIRELESS_11G) ||(pmlmeext->cur_wireless_mode == WIRELESS_11BG))) ++ { ++ edca_param = EDCAParam[pmlmeinfo->assoc_AP_vendor][trafficIndex]; ++ } ++ else ++ { ++ edca_param = EDCAParam[unknownAP][trafficIndex]; ++ } ++ ++#ifdef CONFIG_BT_COEXIST ++ if(_TRUE == bbtchange) ++ edca_param = pbtpriv->BT_EDCA[trafficIndex]; ++#endif ++ ++ rtw_write32(padapter, REG_EDCA_BE_PARAM, edca_param); ++#endif ++ pdmpriv->prv_traffic_idx = trafficIndex; ++ } ++ ++//exit_update_EDCA_param: ++ ++ pxmitpriv->last_tx_bytes = pxmitpriv->tx_bytes; ++ precvpriv->last_rx_bytes = precvpriv->rx_bytes; ++ ++ return; ++} ++ ++static void dm_InitDynamicBBPowerSaving( ++ IN PADAPTER Adapter ++ ) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ struct dm_priv *pdmpriv = &pHalData->dmpriv; ++ PS_T *pPSTable = &pdmpriv->DM_PSTable; ++ ++ pPSTable->PreCCAState = CCA_MAX; ++ pPSTable->CurCCAState = CCA_MAX; ++ pPSTable->PreRFState = RF_MAX; ++ pPSTable->CurRFState = RF_MAX; ++ pPSTable->Rssi_val_min = 0; ++} ++ ++static void dm_1R_CCA( ++ IN PADAPTER pAdapter) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); ++ struct dm_priv *pdmpriv = &pHalData->dmpriv; ++ PS_T *pPSTable = &pdmpriv->DM_PSTable; ++ ++ if(pPSTable->Rssi_val_min != 0) ++ { ++ if(pPSTable->PreCCAState == CCA_2R) ++ { ++ if(pPSTable->Rssi_val_min >= 35) ++ pPSTable->CurCCAState = CCA_1R; ++ else ++ pPSTable->CurCCAState = CCA_2R; ++ } ++ else{ ++ if(pPSTable->Rssi_val_min <= 30) ++ pPSTable->CurCCAState = CCA_2R; ++ else ++ pPSTable->CurCCAState = CCA_1R; ++ } ++ } ++ else ++ pPSTable->CurCCAState=CCA_MAX; ++ ++ if(pPSTable->PreCCAState != pPSTable->CurCCAState) ++ { ++ if(pPSTable->CurCCAState == CCA_1R) ++ { ++ if(pHalData->rf_type == RF_2T2R) ++ { ++ PHY_SetBBReg(pAdapter, rOFDM0_TRxPathEnable , bMaskByte0, 0x13); ++ PHY_SetBBReg(pAdapter, 0xe70, bMaskByte3, 0x20); ++ } ++ else ++ { ++ PHY_SetBBReg(pAdapter, rOFDM0_TRxPathEnable , bMaskByte0, 0x23); ++ PHY_SetBBReg(pAdapter, 0xe70, 0x7fc00000, 0x10c); // Set RegE70[30:22] = 9b'100001100 ++ } ++ } ++ else ++ { ++ PHY_SetBBReg(pAdapter, rOFDM0_TRxPathEnable, bMaskByte0, 0x33); ++ PHY_SetBBReg(pAdapter,0xe70, bMaskByte3, 0x63); ++ } ++ pPSTable->PreCCAState = pPSTable->CurCCAState; ++ } ++ //DBG_8192C("dm_1R_CCA(): CCAStage=%x\n", pPSTable->CurCCAState); ++} ++ ++void ++rtl8192c_dm_RF_Saving( ++ IN PADAPTER pAdapter, ++ IN u8 bForceInNormal ++ ) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); ++ struct dm_priv *pdmpriv = &pHalData->dmpriv; ++ PS_T *pPSTable = &pdmpriv->DM_PSTable; ++ ++ if(pAdapter->registrypriv.intel_class_mode==1) ++ return; ++ if(pdmpriv->initialize == 0){ ++ pdmpriv->rf_saving_Reg874 = (PHY_QueryBBReg(pAdapter, rFPGA0_XCD_RFInterfaceSW, bMaskDWord)&0x1CC000)>>14; ++ pdmpriv->rf_saving_RegC70 = (PHY_QueryBBReg(pAdapter, rOFDM0_AGCParameter1, bMaskDWord)&BIT3)>>3; ++ pdmpriv->rf_saving_Reg85C = (PHY_QueryBBReg(pAdapter, rFPGA0_XCD_SwitchControl, bMaskDWord)&0xFF000000)>>24; ++ pdmpriv->rf_saving_RegA74 = (PHY_QueryBBReg(pAdapter, 0xa74, bMaskDWord)&0xF000)>>12; ++ //Reg818 = PHY_QueryBBReg(pAdapter, 0x818, bMaskDWord); ++ pdmpriv->initialize = 1; ++ } ++ ++ if(!bForceInNormal) ++ { ++ if(pPSTable->Rssi_val_min != 0) ++ { ++ ++ if(pPSTable->PreRFState == RF_Normal) ++ { ++ #ifdef CONFIG_SPECIAL_SETTING_FOR_FUNAI_TV ++ if(pPSTable->Rssi_val_min >= 50) ++ #else ++ if(pPSTable->Rssi_val_min >= 30) ++ #endif ++ pPSTable->CurRFState = RF_Save; ++ else ++ pPSTable->CurRFState = RF_Normal; ++ } ++ else{ ++ #ifdef CONFIG_SPECIAL_SETTING_FOR_FUNAI_TV ++ if(pPSTable->Rssi_val_min <= 45) ++ #else ++ if(pPSTable->Rssi_val_min <= 25) ++ #endif ++ pPSTable->CurRFState = RF_Normal; ++ else ++ pPSTable->CurRFState = RF_Save; ++ } ++ } ++ else ++ pPSTable->CurRFState=RF_MAX; ++ } ++ else ++ { ++ pPSTable->CurRFState = RF_Normal; ++ } ++ ++ if(pPSTable->PreRFState != pPSTable->CurRFState) ++ { ++ if(pPSTable->CurRFState == RF_Save) ++ { ++ PHY_SetBBReg(pAdapter, rFPGA0_XCD_RFInterfaceSW , 0x1C0000, 0x2); //Reg874[20:18]=3'b010 ++ PHY_SetBBReg(pAdapter, rOFDM0_AGCParameter1, BIT3, 0); //RegC70[3]=1'b0 ++ PHY_SetBBReg(pAdapter, rFPGA0_XCD_SwitchControl, 0xFF000000, 0x63); //Reg85C[31:24]=0x63 ++ PHY_SetBBReg(pAdapter, rFPGA0_XCD_RFInterfaceSW, 0xC000, 0x2); //Reg874[15:14]=2'b10 ++ PHY_SetBBReg(pAdapter, 0xa74, 0xF000, 0x3); //RegA75[7:4]=0x3 ++ PHY_SetBBReg(pAdapter, 0x818, BIT28, 0x0); //Reg818[28]=1'b0 ++ PHY_SetBBReg(pAdapter, 0x818, BIT28, 0x1); //Reg818[28]=1'b1 ++ DBG_8192C("%s(): RF_Save\n", __FUNCTION__); ++ } ++ else ++ { ++ PHY_SetBBReg(pAdapter, rFPGA0_XCD_RFInterfaceSW , 0x1CC000, pdmpriv->rf_saving_Reg874); ++ PHY_SetBBReg(pAdapter, rOFDM0_AGCParameter1, BIT3, pdmpriv->rf_saving_RegC70); ++ PHY_SetBBReg(pAdapter, rFPGA0_XCD_SwitchControl, 0xFF000000, pdmpriv->rf_saving_Reg85C); ++ PHY_SetBBReg(pAdapter, 0xa74, 0xF000, pdmpriv->rf_saving_RegA74); ++ PHY_SetBBReg(pAdapter, 0x818, BIT28, 0x0); ++ DBG_8192C("%s(): RF_Normal\n", __FUNCTION__); ++ } ++ pPSTable->PreRFState = pPSTable->CurRFState; ++ } ++} ++ ++static void ++dm_DynamicBBPowerSaving( ++IN PADAPTER pAdapter ++ ) ++{ ++ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); ++ struct mlme_priv *pmlmepriv = &pAdapter->mlmepriv; ++ struct dm_priv *pdmpriv = &pHalData->dmpriv; ++ PS_T *pPSTable = &pdmpriv->DM_PSTable; ++ ++ //1 1.Determine the minimum RSSI ++ if((check_fwstate(pmlmepriv, _FW_LINKED) != _TRUE) && ++ (pdmpriv->EntryMinUndecoratedSmoothedPWDB == 0)) ++ { ++ pPSTable->Rssi_val_min = 0; ++ //RT_TRACE(COMP_BB_POWERSAVING, DBG_LOUD, ("Not connected to any \n")); ++ } ++ if(check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) // Default port ++ { ++ //if(ACTING_AS_AP(pAdapter) || pMgntInfo->mIbss) ++ if ((check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE) || ++ (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE)) //todo: AP Mode ++ { ++ pPSTable->Rssi_val_min = pdmpriv->EntryMinUndecoratedSmoothedPWDB; ++ //RT_TRACE(COMP_BB_POWERSAVING, DBG_LOUD, ("AP Client PWDB = 0x%lx \n", pPSTable->Rssi_val_min)); ++ } ++ else ++ { ++ pPSTable->Rssi_val_min = pdmpriv->UndecoratedSmoothedPWDB; ++ //RT_TRACE(COMP_BB_POWERSAVING, DBG_LOUD, ("STA Default Port PWDB = 0x%lx \n", pPSTable->Rssi_val_min)); ++ } ++ } ++ else // associated entry pwdb ++ { ++ pPSTable->Rssi_val_min = pdmpriv->EntryMinUndecoratedSmoothedPWDB; ++ //RT_TRACE(COMP_BB_POWERSAVING, DBG_LOUD, ("AP Ext Port PWDB = 0x%lx \n", pPSTable->Rssi_val_min)); ++ } ++ ++ //1 2.Power Saving for 92C ++ if(IS_92C_SERIAL(pHalData->VersionID)) ++ { ++ //dm_1R_CCA(pAdapter); ++ } ++ ++ // 20100628 Joseph: Turn off BB power save for 88CE because it makesthroughput unstable. ++ // 20100831 Joseph: Turn ON BB power save again after modifying AGC delay from 900ns to 600ns. ++ //1 3.Power Saving for 88C ++ else ++ { ++ rtl8192c_dm_RF_Saving(pAdapter, _FALSE); ++ } ++} ++ ++ ++#ifdef CONFIG_ANTENNA_DIVERSITY ++// Add new function to reset the state of antenna diversity before link. ++// ++void SwAntDivResetBeforeLink8192C(IN PADAPTER Adapter) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ struct dm_priv *pdmpriv = &pHalData->dmpriv; ++ SWAT_T *pDM_SWAT_Table = &pdmpriv->DM_SWAT_Table; ++ ++ pDM_SWAT_Table->SWAS_NoLink_State = 0; ++} ++ ++// Compare RSSI for deciding antenna ++void SwAntDivCompare8192C(PADAPTER Adapter, WLAN_BSSID_EX *dst, WLAN_BSSID_EX *src) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ ++ if((0 != pHalData->AntDivCfg) && (!IS_92C_SERIAL(pHalData->VersionID)) ) ++ { ++ //DBG_8192C("update_network=> orgRSSI(%d)(%d),newRSSI(%d)(%d)\n",dst->Rssi,query_rx_pwr_percentage(dst->Rssi), ++ // src->Rssi,query_rx_pwr_percentage(src->Rssi)); ++ //select optimum_antenna for before linked =>For antenna diversity ++ if(dst->Rssi >= src->Rssi )//keep org parameter ++ { ++ src->Rssi = dst->Rssi; ++ src->PhyInfo.Optimum_antenna = dst->PhyInfo.Optimum_antenna; ++ } ++ } ++} ++ ++// Add new function to reset the state of antenna diversity before link. ++u8 SwAntDivBeforeLink8192C(IN PADAPTER Adapter) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ struct dm_priv *pdmpriv = &pHalData->dmpriv; ++ SWAT_T *pDM_SWAT_Table = &pdmpriv->DM_SWAT_Table; ++ struct mlme_priv *pmlmepriv = &(Adapter->mlmepriv); ++ ++ // Condition that does not need to use antenna diversity. ++ if(IS_92C_SERIAL(pHalData->VersionID) ||(pHalData->AntDivCfg==0)) ++ { ++ //DBG_8192C("SwAntDivBeforeLink8192C(): No AntDiv Mechanism.\n"); ++ return _FALSE; ++ } ++ ++ if(check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) ++ { ++ pDM_SWAT_Table->SWAS_NoLink_State = 0; ++ return _FALSE; ++ } ++ // Since driver is going to set BB register, it shall check if there is another thread controlling BB/RF. ++/* ++ if(pHalData->eRFPowerState!=eRfOn || pMgntInfo->RFChangeInProgress || pMgntInfo->bMediaConnect) ++ { ++ ++ ++ RT_TRACE(COMP_SWAS, DBG_LOUD, ++ ("SwAntDivCheckBeforeLink8192C(): RFChangeInProgress(%x), eRFPowerState(%x)\n", ++ pMgntInfo->RFChangeInProgress, ++ pHalData->eRFPowerState)); ++ ++ pDM_SWAT_Table->SWAS_NoLink_State = 0; ++ ++ return FALSE; ++ } ++*/ ++ ++ if(pDM_SWAT_Table->SWAS_NoLink_State == 0){ ++ //switch channel ++ pDM_SWAT_Table->SWAS_NoLink_State = 1; ++ pDM_SWAT_Table->CurAntenna = (pDM_SWAT_Table->CurAntenna==Antenna_A)?Antenna_B:Antenna_A; ++ ++ //PHY_SetBBReg(Adapter, rFPGA0_XA_RFInterfaceOE, 0x300, pDM_SWAT_Table->CurAntenna); ++ rtw_antenna_select_cmd(Adapter, pDM_SWAT_Table->CurAntenna, _FALSE); ++ //DBG_8192C("%s change antenna to ANT_( %s ).....\n",__FUNCTION__, (pDM_SWAT_Table->CurAntenna==Antenna_A)?"A":"B"); ++ return _TRUE; ++ } ++ else ++ { ++ pDM_SWAT_Table->SWAS_NoLink_State = 0; ++ return _FALSE; ++ } ++ ++ ++ ++} ++#endif ++#ifdef CONFIG_SW_ANTENNA_DIVERSITY ++// ++// 20100514 Luke/Joseph: ++// Add new function to reset antenna diversity state after link. ++// ++void ++SwAntDivRestAfterLink8192C( ++ IN PADAPTER Adapter ++ ) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ struct dm_priv *pdmpriv = &pHalData->dmpriv; ++ SWAT_T *pDM_SWAT_Table = &pdmpriv->DM_SWAT_Table; ++ ++ if(IS_92C_SERIAL(pHalData->VersionID) ||(pHalData->AntDivCfg==0)) ++ return; ++ ++ //DBG_8192C("======> SwAntDivRestAfterLink <========== \n"); ++ pHalData->RSSI_cnt_A= 0; ++ pHalData->RSSI_cnt_B= 0; ++ pHalData->RSSI_test = _FALSE; ++ ++ pDM_SWAT_Table->try_flag = 0xff; ++ pDM_SWAT_Table->RSSI_Trying = 0; ++ pDM_SWAT_Table->SelectAntennaMap=0xAA; ++ pDM_SWAT_Table->CurAntenna = pHalData->CurAntenna; ++ pDM_SWAT_Table->PreAntenna = pHalData->CurAntenna; ++ ++ pdmpriv->lastTxOkCnt=0; ++ pdmpriv->lastRxOkCnt=0; ++ ++ pdmpriv->TXByteCnt_A=0; ++ pdmpriv->TXByteCnt_B=0; ++ pdmpriv->RXByteCnt_A=0; ++ pdmpriv->RXByteCnt_B=0; ++ pdmpriv->DoubleComfirm=0; ++ pdmpriv->TrafficLoad = TRAFFIC_LOW; ++ ++} ++ ++ ++// ++// 20100514 Luke/Joseph: ++// Add new function for antenna diversity after link. ++// This is the main function of antenna diversity after link. ++// This function is called in HalDmWatchDog() and dm_SW_AntennaSwitchCallback(). ++// HalDmWatchDog() calls this function with SWAW_STEP_PEAK to initialize the antenna test. ++// In SWAW_STEP_PEAK, another antenna and a 500ms timer will be set for testing. ++// After 500ms, dm_SW_AntennaSwitchCallback() calls this function to compare the signal just ++// listened on the air with the RSSI of original antenna. ++// It chooses the antenna with better RSSI. ++// There is also a aged policy for error trying. Each error trying will cost more 5 seconds waiting ++// penalty to get next try. ++// ++static VOID ++dm_SW_AntennaSwitch( ++ PADAPTER Adapter, ++ u8 Step ++) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ struct dm_priv *pdmpriv = &pHalData->dmpriv; ++ SWAT_T *pDM_SWAT_Table = &pdmpriv->DM_SWAT_Table; ++ s32 curRSSI=100, RSSI_A, RSSI_B; ++ u64 curTxOkCnt, curRxOkCnt; ++ u64 CurByteCnt = 0, PreByteCnt = 0; ++ u8 nextAntenna = 0; ++ u8 Score_A=0, Score_B=0; ++ u8 i; ++ ++ // Condition that does not need to use antenna diversity. ++ if(IS_92C_SERIAL(pHalData->VersionID) ||(pHalData->AntDivCfg==0)) ++ { ++ //RT_TRACE(COMP_SWAS, DBG_LOUD, ("dm_SW_AntennaSwitch(): No AntDiv Mechanism.\n")); ++ return; ++ } ++ // If dynamic ant_div is disabled. ++ if(!(pdmpriv->DMFlag & DYNAMIC_FUNC_ANT_DIV) ) ++ { ++ return; ++ } ++ ++ if (check_fwstate(&Adapter->mlmepriv, _FW_LINKED) ==_FALSE) ++ return; ++#if 0 //to do ++ // Radio off: Status reset to default and return. ++ if(pHalData->eRFPowerState==eRfOff) ++ { ++ SwAntDivRestAfterLink(Adapter); ++ return; ++ } ++#endif ++ //DBG_8192C("\n............................ %s.........................\n",__FUNCTION__); ++ // Handling step mismatch condition. ++ // Peak step is not finished at last time. Recover the variable and check again. ++ if( Step != pDM_SWAT_Table->try_flag ) ++ { ++ SwAntDivRestAfterLink8192C(Adapter); ++ } ++ ++ ++ if(pDM_SWAT_Table->try_flag == 0xff) ++ { ++#if 0 ++ // Select RSSI checking target ++ if(pMgntInfo->mAssoc && !ACTING_AS_AP(Adapter)) ++ { ++ // Target: Infrastructure mode AP. ++ pHalData->RSSI_target = NULL; ++ RT_TRACE(COMP_SWAS, DBG_LOUD, ("dm_SW_AntennaSwitch(): RSSI_target is DEF AP!\n")); ++ } ++ else ++ { ++ u8 index = 0; ++ PRT_WLAN_STA pEntry = NULL; ++ PADAPTER pTargetAdapter = NULL; ++ ++ if( pMgntInfo->mIbss || ACTING_AS_AP(Adapter) ) ++ { ++ // Target: AP/IBSS peer. ++ pTargetAdapter = Adapter; ++ } ++ else if(ACTING_AS_AP(ADJUST_TO_ADAPTIVE_ADAPTER(Adapter, FALSE))) ++ { ++ // Target: VWIFI peer. ++ pTargetAdapter = ADJUST_TO_ADAPTIVE_ADAPTER(Adapter, FALSE); ++ } ++ ++ if(pTargetAdapter != NULL) ++ { ++ for(index=0; indexbAssociated) ++ break; ++ } ++ } ++ } ++ ++ if(pEntry == NULL) ++ { ++ SwAntDivRestAfterLink(Adapter); ++ RT_TRACE(COMP_SWAS, DBG_LOUD, ("dm_SW_AntennaSwitch(): No Link.\n")); ++ return; ++ } ++ else ++ { ++ pHalData->RSSI_target = pEntry; ++ RT_TRACE(COMP_SWAS, DBG_LOUD, ("dm_SW_AntennaSwitch(): RSSI_target is PEER STA\n")); ++ } ++ } ++ ++ ++#endif ++ ++ pHalData->RSSI_cnt_A= 0; ++ pHalData->RSSI_cnt_B= 0; ++ pDM_SWAT_Table->try_flag = 0; ++ // DBG_8192C("dm_SW_AntennaSwitch(): Set try_flag to 0 prepare for peak!\n"); ++ return; ++ } ++ else ++ { ++ curTxOkCnt = Adapter->xmitpriv.tx_bytes - pdmpriv->lastTxOkCnt; ++ curRxOkCnt = Adapter->recvpriv.rx_bytes - pdmpriv->lastRxOkCnt; ++ ++ pdmpriv->lastTxOkCnt = Adapter->xmitpriv.tx_bytes ; ++ pdmpriv->lastRxOkCnt = Adapter->recvpriv.rx_bytes ; ++ ++ if(pDM_SWAT_Table->try_flag == 1) ++ { ++ if(pDM_SWAT_Table->CurAntenna == Antenna_A) ++ { ++ pdmpriv->TXByteCnt_A += curTxOkCnt; ++ pdmpriv->RXByteCnt_A += curRxOkCnt; ++ //DBG_8192C("##### TXByteCnt_A(%lld) , RXByteCnt_A(%lld) ####\n",pdmpriv->TXByteCnt_A,pdmpriv->RXByteCnt_A); ++ } ++ else ++ { ++ pdmpriv->TXByteCnt_B += curTxOkCnt; ++ pdmpriv->RXByteCnt_B += curRxOkCnt; ++ //DBG_8192C("##### TXByteCnt_B(%lld) , RXByteCnt_B(%lld) ####\n",pdmpriv->TXByteCnt_B,pdmpriv->RXByteCnt_B); ++ } ++ ++ nextAntenna = (pDM_SWAT_Table->CurAntenna == Antenna_A)? Antenna_B : Antenna_A; ++ pDM_SWAT_Table->RSSI_Trying--; ++ //DBG_8192C("RSSI_Trying = %d\n",pDM_SWAT_Table->RSSI_Trying); ++ ++ if(pDM_SWAT_Table->RSSI_Trying == 0) ++ { ++ CurByteCnt = (pDM_SWAT_Table->CurAntenna == Antenna_A)? (pdmpriv->TXByteCnt_A+pdmpriv->RXByteCnt_A) : (pdmpriv->TXByteCnt_B+pdmpriv->RXByteCnt_B); ++ PreByteCnt = (pDM_SWAT_Table->CurAntenna == Antenna_A)? (pdmpriv->TXByteCnt_B+pdmpriv->RXByteCnt_B) : (pdmpriv->TXByteCnt_A+pdmpriv->RXByteCnt_A); ++ ++ //DBG_8192C("CurByteCnt = %lld\n", CurByteCnt); ++ //DBG_8192C("PreByteCnt = %lld\n",PreByteCnt); ++ ++ if(pdmpriv->TrafficLoad == TRAFFIC_HIGH) ++ { ++ PreByteCnt = PreByteCnt*9; //normalize:Cur=90ms:Pre=10ms ++ } ++ else if(pdmpriv->TrafficLoad == TRAFFIC_LOW) ++ { ++ //CurByteCnt = CurByteCnt/2; ++ CurByteCnt = CurByteCnt>>1;//normalize:100ms:50ms ++ } ++ ++ ++ //DBG_8192C("After DIV=>CurByteCnt = %lld\n", CurByteCnt); ++ //DBG_8192C("PreByteCnt = %lld\n",PreByteCnt); ++ ++ if(pHalData->RSSI_cnt_A > 0) ++ RSSI_A = pHalData->RSSI_sum_A/pHalData->RSSI_cnt_A; ++ else ++ RSSI_A = 0; ++ if(pHalData->RSSI_cnt_B > 0) ++ RSSI_B = pHalData->RSSI_sum_B/pHalData->RSSI_cnt_B; ++ else ++ RSSI_B = 0; ++ ++ curRSSI = (pDM_SWAT_Table->CurAntenna == Antenna_A)? RSSI_A : RSSI_B; ++ pDM_SWAT_Table->PreRSSI = (pDM_SWAT_Table->CurAntenna == Antenna_A)? RSSI_B : RSSI_A; ++ //DBG_8192C("Luke:PreRSSI = %d, CurRSSI = %d\n",pDM_SWAT_Table->PreRSSI, curRSSI); ++ //DBG_8192C("SWAS: preAntenna= %s, curAntenna= %s \n", ++ //(pDM_SWAT_Table->PreAntenna == Antenna_A?"A":"B"), (pDM_SWAT_Table->CurAntenna == Antenna_A?"A":"B")); ++ //DBG_8192C("Luke:RSSI_A= %d, RSSI_cnt_A = %d, RSSI_B= %d, RSSI_cnt_B = %d\n", ++ //RSSI_A, pHalData->RSSI_cnt_A, RSSI_B, pHalData->RSSI_cnt_B); ++ } ++ ++ } ++ else ++ { ++ ++ if(pHalData->RSSI_cnt_A > 0) ++ RSSI_A = pHalData->RSSI_sum_A/pHalData->RSSI_cnt_A; ++ else ++ RSSI_A = 0; ++ if(pHalData->RSSI_cnt_B > 0) ++ RSSI_B = pHalData->RSSI_sum_B/pHalData->RSSI_cnt_B; ++ else ++ RSSI_B = 0; ++ curRSSI = (pDM_SWAT_Table->CurAntenna == Antenna_A)? RSSI_A : RSSI_B; ++ pDM_SWAT_Table->PreRSSI = (pDM_SWAT_Table->PreAntenna == Antenna_A)? RSSI_A : RSSI_B; ++ //DBG_8192C("Ekul:PreRSSI = %d, CurRSSI = %d\n", pDM_SWAT_Table->PreRSSI, curRSSI); ++ //DBG_8192C("SWAS: preAntenna= %s, curAntenna= %s \n", ++ //(pDM_SWAT_Table->PreAntenna == Antenna_A?"A":"B"), (pDM_SWAT_Table->CurAntenna == Antenna_A?"A":"B")); ++ ++ //DBG_8192C("Ekul:RSSI_A= %d, RSSI_cnt_A = %d, RSSI_B= %d, RSSI_cnt_B = %d\n", ++ // RSSI_A, pHalData->RSSI_cnt_A, RSSI_B, pHalData->RSSI_cnt_B); ++ //RT_TRACE(COMP_SWAS, DBG_LOUD, ("Ekul:curTxOkCnt = %d\n", curTxOkCnt)); ++ //RT_TRACE(COMP_SWAS, DBG_LOUD, ("Ekul:curRxOkCnt = %d\n", curRxOkCnt)); ++ } ++ ++ //1 Trying State ++ if((pDM_SWAT_Table->try_flag == 1)&&(pDM_SWAT_Table->RSSI_Trying == 0)) ++ { ++ ++ if(pDM_SWAT_Table->TestMode == TP_MODE) ++ { ++ //DBG_8192C("SWAS: TestMode = TP_MODE\n"); ++ //DBG_8192C("TRY:CurByteCnt = %lld\n", CurByteCnt); ++ //DBG_8192C("TRY:PreByteCnt = %lld\n",PreByteCnt); ++ if(CurByteCnt < PreByteCnt) ++ { ++ if(pDM_SWAT_Table->CurAntenna == Antenna_A) ++ pDM_SWAT_Table->SelectAntennaMap=pDM_SWAT_Table->SelectAntennaMap<<1; ++ else ++ pDM_SWAT_Table->SelectAntennaMap=(pDM_SWAT_Table->SelectAntennaMap<<1)+1; ++ } ++ else ++ { ++ if(pDM_SWAT_Table->CurAntenna == Antenna_A) ++ pDM_SWAT_Table->SelectAntennaMap=(pDM_SWAT_Table->SelectAntennaMap<<1)+1; ++ else ++ pDM_SWAT_Table->SelectAntennaMap=pDM_SWAT_Table->SelectAntennaMap<<1; ++ } ++ for (i= 0; i<8; i++) ++ { ++ if(((pDM_SWAT_Table->SelectAntennaMap>>i)&BIT0) == 1) ++ Score_A++; ++ else ++ Score_B++; ++ } ++ //DBG_8192C("SelectAntennaMap=%x\n ",pDM_SWAT_Table->SelectAntennaMap); ++ //DBG_8192C("Score_A=%d, Score_B=%d\n", Score_A, Score_B); ++ ++ if(pDM_SWAT_Table->CurAntenna == Antenna_A) ++ { ++ nextAntenna = (Score_A > Score_B)?Antenna_A:Antenna_B; ++ } ++ else ++ { ++ nextAntenna = (Score_B > Score_A)?Antenna_B:Antenna_A; ++ } ++ //RT_TRACE(COMP_SWAS, DBG_LOUD, ("nextAntenna=%s\n",(nextAntenna==Antenna_A)?"A":"B")); ++ //RT_TRACE(COMP_SWAS, DBG_LOUD, ("preAntenna= %s, curAntenna= %s \n", ++ //(DM_SWAT_Table.PreAntenna == Antenna_A?"A":"B"), (DM_SWAT_Table.CurAntenna == Antenna_A?"A":"B"))); ++ ++ if(nextAntenna != pDM_SWAT_Table->CurAntenna) ++ { ++ //DBG_8192C("SWAS: Switch back to another antenna\n"); ++ } ++ else ++ { ++ //DBG_8192C("SWAS: current anntena is good\n"); ++ } ++ } ++ ++ if(pDM_SWAT_Table->TestMode == RSSI_MODE) ++ { ++ //DBG_8192C("SWAS: TestMode = RSSI_MODE\n"); ++ pDM_SWAT_Table->SelectAntennaMap=0xAA; ++ if(curRSSI < pDM_SWAT_Table->PreRSSI) //Current antenna is worse than previous antenna ++ { ++ //DBG_8192C("SWAS: Switch back to another antenna\n"); ++ nextAntenna = (pDM_SWAT_Table->CurAntenna == Antenna_A)? Antenna_B : Antenna_A; ++ } ++ else // current anntena is good ++ { ++ nextAntenna = pDM_SWAT_Table->CurAntenna; ++ //DBG_8192C("SWAS: current anntena is good\n"); ++ } ++ } ++ pDM_SWAT_Table->try_flag = 0; ++ pHalData->RSSI_test = _FALSE; ++ pHalData->RSSI_sum_A = 0; ++ pHalData->RSSI_cnt_A = 0; ++ pHalData->RSSI_sum_B = 0; ++ pHalData->RSSI_cnt_B = 0; ++ pdmpriv->TXByteCnt_A = 0; ++ pdmpriv->TXByteCnt_B = 0; ++ pdmpriv->RXByteCnt_A = 0; ++ pdmpriv->RXByteCnt_B = 0; ++ ++ } ++ ++ //1 Normal State ++ else if(pDM_SWAT_Table->try_flag == 0) ++ { ++ if(pdmpriv->TrafficLoad == TRAFFIC_HIGH) ++ { ++ if(((curTxOkCnt+curRxOkCnt)>>1) > 1875000) ++ pdmpriv->TrafficLoad = TRAFFIC_HIGH; ++ else ++ pdmpriv->TrafficLoad = TRAFFIC_LOW; ++ } ++ else if(pdmpriv->TrafficLoad == TRAFFIC_LOW) ++ { ++ if(((curTxOkCnt+curRxOkCnt)>>1) > 1875000) ++ pdmpriv->TrafficLoad = TRAFFIC_HIGH; ++ else ++ pdmpriv->TrafficLoad = TRAFFIC_LOW; ++ } ++ if(pdmpriv->TrafficLoad == TRAFFIC_HIGH) ++ pDM_SWAT_Table->bTriggerAntennaSwitch = 0; ++ //DBG_8192C("Normal:TrafficLoad = %lld\n", curTxOkCnt+curRxOkCnt); ++ ++ //Prepare To Try Antenna ++ nextAntenna = (pDM_SWAT_Table->CurAntenna == Antenna_A)? Antenna_B : Antenna_A; ++ pDM_SWAT_Table->try_flag = 1; ++ pHalData->RSSI_test = _TRUE; ++ if((curRxOkCnt+curTxOkCnt) > 1000) ++ { ++ pDM_SWAT_Table->RSSI_Trying = 4; ++ pDM_SWAT_Table->TestMode = TP_MODE; ++ } ++ else ++ { ++ pDM_SWAT_Table->RSSI_Trying = 2; ++ pDM_SWAT_Table->TestMode = RSSI_MODE; ++ ++ } ++ //DBG_8192C("SWAS: Normal State -> Begin Trying! TestMode=%s\n",(pDM_SWAT_Table->TestMode == TP_MODE)?"TP":"RSSI"); ++ ++ ++ pHalData->RSSI_sum_A = 0; ++ pHalData->RSSI_cnt_A = 0; ++ pHalData->RSSI_sum_B = 0; ++ pHalData->RSSI_cnt_B = 0; ++ } ++ } ++ ++ //1 4.Change TRX antenna ++ if(nextAntenna != pDM_SWAT_Table->CurAntenna) ++ { ++ //DBG_8192C("@@@@@@@@ SWAS: Change TX Antenna!\n "); ++ rtw_antenna_select_cmd(Adapter, nextAntenna, 1); ++ } ++ ++ //1 5.Reset Statistics ++ pDM_SWAT_Table->PreAntenna = pDM_SWAT_Table->CurAntenna; ++ pDM_SWAT_Table->CurAntenna = nextAntenna; ++ pDM_SWAT_Table->PreRSSI = curRSSI; ++ ++ ++ //1 6.Set next timer ++ ++ if(pDM_SWAT_Table->RSSI_Trying == 0) ++ return; ++ ++ if(pDM_SWAT_Table->RSSI_Trying%2 == 0) ++ { ++ if(pDM_SWAT_Table->TestMode == TP_MODE) ++ { ++ if(pdmpriv->TrafficLoad == TRAFFIC_HIGH) ++ { ++ _set_timer(&pdmpriv->SwAntennaSwitchTimer,10 ); //ms ++ //DBG_8192C("dm_SW_AntennaSwitch(): Test another antenna for 10 ms\n"); ++ } ++ else if(pdmpriv->TrafficLoad == TRAFFIC_LOW) ++ { ++ _set_timer(&pdmpriv->SwAntennaSwitchTimer, 50 ); //ms ++ //DBG_8192C("dm_SW_AntennaSwitch(): Test another antenna for 50 ms\n"); ++ } ++ } ++ else ++ { ++ _set_timer(&pdmpriv->SwAntennaSwitchTimer, 500 ); //ms ++ //DBG_8192C("dm_SW_AntennaSwitch(): Test another antenna for 500 ms\n"); ++ } ++ } ++ else ++ { ++ if(pDM_SWAT_Table->TestMode == TP_MODE) ++ { ++ if(pdmpriv->TrafficLoad == TRAFFIC_HIGH) ++ _set_timer(&pdmpriv->SwAntennaSwitchTimer,90 ); //ms ++ else if(pdmpriv->TrafficLoad == TRAFFIC_LOW) ++ _set_timer(&pdmpriv->SwAntennaSwitchTimer,100 ); //ms ++ } ++ else ++ { ++ _set_timer(&pdmpriv->SwAntennaSwitchTimer,500 ); //ms ++ //DBG_8192C("dm_SW_AntennaSwitch(): Test another antenna for 500 ms\n"); ++ } ++ } ++ ++// RT_TRACE(COMP_SWAS, DBG_LOUD, ("SWAS: -----The End-----\n ")); ++ ++} ++ ++// ++// 20100514 Luke/Joseph: ++// Callback function for 500ms antenna test trying. ++// ++static void dm_SW_AntennaSwitchCallback(void *FunctionContext) ++{ ++ _adapter *padapter = (_adapter *)FunctionContext; ++ ++ if(padapter->net_closed == _TRUE) ++ return; ++ // Only ++ dm_SW_AntennaSwitch(padapter, SWAW_STEP_DETERMINE); ++} ++ ++ ++// ++// 20100722 ++// This function is used to gather the RSSI information for antenna testing. ++// It selects the RSSI of the peer STA that we want to know. ++// ++void SwAntDivRSSICheck8192C(_adapter *padapter ,u32 RxPWDBAll) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct dm_priv *pdmpriv = &pHalData->dmpriv; ++ ++ SWAT_T *pDM_SWAT_Table = &pdmpriv->DM_SWAT_Table; ++ ++ if(IS_92C_SERIAL(pHalData->VersionID) ||pHalData->AntDivCfg==0) ++ return; ++ ++ if(check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) ++ { ++ if(pDM_SWAT_Table->CurAntenna == Antenna_A) ++ { ++ pHalData->RSSI_sum_A += RxPWDBAll; ++ pHalData->RSSI_cnt_A++; ++ } ++ else ++ { ++ pHalData->RSSI_sum_B+= RxPWDBAll; ++ pHalData->RSSI_cnt_B++; ++ ++ } ++ //DBG_8192C("%s Ant_(%s),RSSI_sum(%d),RSSI_cnt(%d)\n",__FUNCTION__,(2==pHalData->CurAntenna)?"A":"B",pHalData->RSSI_sum,pHalData->RSSI_cnt); ++ } ++ ++} ++ ++ ++ ++static VOID ++dm_SW_AntennaSwitchInit( ++ IN PADAPTER Adapter ++ ) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ struct dm_priv *pdmpriv = &pHalData->dmpriv; ++ SWAT_T *pDM_SWAT_Table = &pdmpriv->DM_SWAT_Table; ++ ++ pHalData->RSSI_sum_A = 0; ++ pHalData->RSSI_sum_B = 0; ++ pHalData->RSSI_cnt_A = 0; ++ pHalData->RSSI_cnt_B = 0; ++ ++ pDM_SWAT_Table->CurAntenna = pHalData->CurAntenna; ++ pDM_SWAT_Table->PreAntenna = pHalData->CurAntenna; ++ pDM_SWAT_Table->try_flag = 0xff; ++ pDM_SWAT_Table->PreRSSI = 0; ++ pDM_SWAT_Table->bTriggerAntennaSwitch = 0; ++ pDM_SWAT_Table->SelectAntennaMap=0xAA; ++ ++ // Move the timer initialization to InitializeVariables function. ++ //PlatformInitializeTimer(Adapter, &pMgntInfo->SwAntennaSwitchTimer, (RT_TIMER_CALL_BACK)dm_SW_AntennaSwitchCallback, NULL, "SwAntennaSwitchTimer"); ++} ++ ++#endif ++ ++//#define RSSI_CCK 0 ++//#define RSSI_OFDM 1 ++static void dm_RSSIMonitorInit( ++ IN PADAPTER Adapter ++) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ struct dm_priv *pdmpriv = &pHalData->dmpriv; ++ pdmpriv->OFDM_Pkt_Cnt = 0; ++ pdmpriv->RSSI_Select = RSSI_DEFAULT; ++} ++ ++static void dm_RSSIMonitorCheck( ++ IN PADAPTER Adapter ++) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ struct dm_priv *pdmpriv = &pHalData->dmpriv; ++ struct mlme_priv *pmlmepriv = &Adapter->mlmepriv; ++ ++ if(check_fwstate(pmlmepriv, _FW_LINKED) == _FALSE) ++ return; ++ ++ if(check_fwstate(pmlmepriv, WIFI_AP_STATE |WIFI_ADHOC_STATE) == _TRUE ) ++ { ++ if(Adapter->stapriv.asoc_sta_count < 2) ++ return; ++ } ++ ++ if(pdmpriv->OFDM_Pkt_Cnt == 0) ++ pdmpriv->RSSI_Select = RSSI_CCK; ++ else ++ pdmpriv->RSSI_Select = RSSI_OFDM; ++ ++ pdmpriv->OFDM_Pkt_Cnt = 0; ++ //DBG_8192C("RSSI_Select=%s OFDM_Pkt_Cnt(%d)\n", ++ //(pdmpriv->RSSI_Select == RSSI_OFDM)?"RSSI_OFDM":"RSSI_CCK", ++ //pdmpriv->OFDM_Pkt_Cnt); ++} ++ ++//============================================================ ++// functions ++//============================================================ ++void rtl8192c_init_dm_priv(IN PADAPTER Adapter) ++{ ++ PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); ++ struct dm_priv *pdmpriv = &pHalData->dmpriv; ++ ++ _rtw_memset(pdmpriv, 0, sizeof(struct dm_priv)); ++ ++#ifdef CONFIG_SW_ANTENNA_DIVERSITY ++ _init_timer(&(pdmpriv->SwAntennaSwitchTimer), Adapter->pnetdev , dm_SW_AntennaSwitchCallback, Adapter); ++#endif ++} ++ ++void rtl8192c_deinit_dm_priv(IN PADAPTER Adapter) ++{ ++ PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); ++ struct dm_priv *pdmpriv = &pHalData->dmpriv; ++ ++#ifdef CONFIG_SW_ANTENNA_DIVERSITY ++ _cancel_timer_ex(&pdmpriv->SwAntennaSwitchTimer); ++#endif ++} ++#ifdef CONFIG_HW_ANTENNA_DIVERSITY ++void dm_InitHybridAntDiv(IN PADAPTER Adapter) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ ++ if(IS_92C_SERIAL(pHalData->VersionID) ||pHalData->AntDivCfg==0) ++ return; ++ ++ //Set OFDM HW RX Antenna Diversity ++ PHY_SetBBReg(Adapter,0xc50, BIT7, 1); //Enable Hardware antenna switch ++ PHY_SetBBReg(Adapter,0x870, BIT9|BIT8, 0); //Enable hardware control of "ANT_SEL" & "ANT_SELB" ++ PHY_SetBBReg(Adapter,0xCA4, BIT11, 0); //Switch to another antenna by checking pwdb threshold ++ PHY_SetBBReg(Adapter,0xCA4, 0x7FF, 0x080); //Pwdb threshold=8dB ++ PHY_SetBBReg(Adapter,0xC54, BIT23, 1); //Decide final antenna by comparing 2 antennas' pwdb ++ PHY_SetBBReg(Adapter,0x874, BIT23, 0); //No update ANTSEL during GNT_BT=1 ++ PHY_SetBBReg(Adapter,0x80C, BIT21, 1); //TX atenna selection from tx_info ++ //Set CCK HW RX Antenna Diversity ++ PHY_SetBBReg(Adapter,0xA00, BIT15, 1);//Enable antenna diversity ++ PHY_SetBBReg(Adapter,0xA0C, BIT4, 0); //Antenna diversity decision period = 32 sample ++ PHY_SetBBReg(Adapter,0xA0C, 0xf, 0xf); //Threshold for antenna diversity. Check another antenna power if input power < ANT_lim*4 ++ PHY_SetBBReg(Adapter,0xA10, BIT13, 1); //polarity ana_A=1 and ana_B=0 ++ PHY_SetBBReg(Adapter,0xA14, 0x1f, 0x8); //default antenna power = inpwr*(0.5 + r_ant_step/16) ++ ++ pHalData->CCK_Ant1_Cnt = 0; ++ pHalData->CCK_Ant2_Cnt = 0; ++ pHalData->OFDM_Ant1_Cnt = 0; ++ pHalData->OFDM_Ant2_Cnt = 0; ++} ++ ++ ++#define RxDefaultAnt1 0x65a9 ++#define RxDefaultAnt2 0x569a ++ ++void dm_SelectRXDefault(IN PADAPTER Adapter) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ ++ if(IS_92C_SERIAL(pHalData->VersionID) ||pHalData->AntDivCfg==0) ++ return; ++ ++ //DbgPrint(" Ant1_Cnt=%d, Ant2_Cnt=%d\n", pHalData->Ant1_Cnt, pHalData->Ant2_Cnt); ++ //DBG_8192C(" CCK_Ant1_Cnt = %d, CCK_Ant2_Cnt = %d\n", pHalData->CCK_Ant1_Cnt, pHalData->CCK_Ant2_Cnt); ++ //DBG_8192C(" OFDM_Ant1_Cnt = %d, OFDM_Ant2_Cnt = %d\n", pHalData->OFDM_Ant1_Cnt, pHalData->OFDM_Ant2_Cnt); ++ if((pHalData->OFDM_Ant1_Cnt == 0) && (pHalData->OFDM_Ant2_Cnt == 0)) ++ { ++ if((pHalData->CCK_Ant1_Cnt + pHalData->CCK_Ant2_Cnt) >=10 ) ++ { ++ if(pHalData->CCK_Ant1_Cnt > (5*pHalData->CCK_Ant2_Cnt)) ++ { ++ DBG_8192C(" RX Default = Ant1\n"); ++ PHY_SetBBReg(Adapter, 0x858, 0xFFFF, RxDefaultAnt1); ++ } ++ else if(pHalData->CCK_Ant2_Cnt > (5*pHalData->CCK_Ant1_Cnt)) ++ { ++ DBG_8192C(" RX Default = Ant2\n"); ++ PHY_SetBBReg(Adapter, 0x858, 0xFFFF, RxDefaultAnt2); ++ } ++ else if(pHalData->CCK_Ant1_Cnt > pHalData->CCK_Ant2_Cnt) ++ { ++ DBG_8192C(" RX Default = Ant2\n"); ++ PHY_SetBBReg(Adapter, 0x858, 0xFFFF, RxDefaultAnt2); ++ } ++ else ++ { ++ DBG_8192C(" RX Default = Ant1\n"); ++ PHY_SetBBReg(Adapter, 0x858, 0xFFFF, RxDefaultAnt1); ++ } ++ pHalData->CCK_Ant1_Cnt = 0; ++ pHalData->CCK_Ant2_Cnt = 0; ++ pHalData->OFDM_Ant1_Cnt = 0; ++ pHalData->OFDM_Ant2_Cnt = 0; ++ } ++ } ++ else ++ { ++ if(pHalData->OFDM_Ant1_Cnt > pHalData->OFDM_Ant2_Cnt) ++ { ++ DBG_8192C(" RX Default = Ant1\n"); ++ PHY_SetBBReg(Adapter, 0x858, 0xFFFF, RxDefaultAnt1); ++ } ++ else ++ { ++ DBG_8192C(" RX Default = Ant2\n"); ++ PHY_SetBBReg(Adapter, 0x858, 0xFFFF, RxDefaultAnt2); ++ } ++ pHalData->CCK_Ant1_Cnt = 0; ++ pHalData->CCK_Ant2_Cnt = 0; ++ pHalData->OFDM_Ant1_Cnt = 0; ++ pHalData->OFDM_Ant2_Cnt = 0; ++ } ++ ++ ++} ++ ++#endif ++ ++void ++rtl8192c_InitHalDm( ++ IN PADAPTER Adapter ++ ) ++{ ++ PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); ++ struct dm_priv *pdmpriv = &pHalData->dmpriv; ++ u8 i; ++ ++#ifdef CONFIG_USB_HCI ++ dm_InitGPIOSetting(Adapter); ++#endif ++ ++ pdmpriv->DM_Type = DM_Type_ByDriver; ++ pdmpriv->DMFlag = DYNAMIC_FUNC_DISABLE; ++ pdmpriv->UndecoratedSmoothedPWDB = (-1); ++ pdmpriv->UndecoratedSmoothedCCK = (-1); ++ ++ ++ //.1 DIG INIT ++ pdmpriv->bDMInitialGainEnable = _TRUE; ++ pdmpriv->DMFlag |= DYNAMIC_FUNC_DIG; ++ dm_DIGInit(Adapter); ++ ++ //.2 DynamicTxPower INIT ++ pdmpriv->DMFlag |= DYNAMIC_FUNC_HP; ++ dm_InitDynamicTxPower(Adapter); ++ ++ //.3 ++ DM_InitEdcaTurbo(Adapter); ++ ++ //.4 RateAdaptive INIT ++ dm_InitRateAdaptiveMask(Adapter); ++ ++ //.5 Tx Power Tracking Init. ++ pdmpriv->DMFlag |= DYNAMIC_FUNC_SS; ++ DM_InitializeTXPowerTracking(Adapter); ++ ++#ifdef CONFIG_BT_COEXIST ++ pdmpriv->DMFlag |= DYNAMIC_FUNC_BT; ++ dm_InitBtCoexistDM(Adapter); ++#endif ++ ++ dm_InitDynamicBBPowerSaving(Adapter); ++ ++#ifdef CONFIG_SW_ANTENNA_DIVERSITY ++ pdmpriv->DMFlag |= DYNAMIC_FUNC_ANT_DIV; ++ dm_SW_AntennaSwitchInit(Adapter); ++#endif ++ ++#ifdef CONFIG_HW_ANTENNA_DIVERSITY ++ pdmpriv->DMFlag |= DYNAMIC_FUNC_ANT_DIV; ++ dm_InitHybridAntDiv(Adapter); ++#endif ++ ++ dm_RSSIMonitorInit(Adapter); ++ ++ pdmpriv->DMFlag_tmp = pdmpriv->DMFlag; ++ ++ // Save REG_INIDATA_RATE_SEL value for TXDESC. ++ for(i = 0 ; i<32 ; i++) ++ { ++ pdmpriv->INIDATA_RATE[i] = rtw_read8(Adapter, REG_INIDATA_RATE_SEL+i) & 0x3f; ++ } ++} ++VOID ++rtl8192c_HalDmPollingC2HEvt( ++ IN PADAPTER padapter ++ ) ++{ ++ u8 trigger=0,evt_id=0,evt_len=0,idx=0,tmp8=0,evt_seq=0; ++ u8 evt_buf[15]; ++ ++ trigger=rtw_read8(padapter,REG_C2HEVT_CLEAR); ++ while (trigger ==0xFF) ++ { ++ tmp8=rtw_read8(padapter,REG_C2HEVT_MSG_NORMAL); ++ evt_id=tmp8&0xf; ++ evt_len=(tmp8&0xf0)>>4; ++ evt_seq=rtw_read8(padapter,REG_C2HEVT_MSG_NORMAL+1); ++ DBG_8192C(" %s evt_id =0x%x evt_len=0x%x evt_seq=0x%x\n",__FUNCTION__,evt_id,evt_len,evt_seq); ++ for(idx=0;idxstapriv; ++ struct sta_info *psta=NULL; ++ DBG_8192C(" %s mac_id=%d\n",__FUNCTION__,mac_id); ++ for(idx=0;idxsta_aid[mac_id-2+idx]; ++ if(psta !=NULL){ ++ psta->init_rate=evt_buf[idx]; ++ DBG_8192C(" %s mac_id=%d psta->init_rate=0x%x\n",__FUNCTION__,mac_id,psta->init_rate); ++ } ++ } ++ ++ } ++ default: ++ DBG_8192C(" %s evt_id =0x%x evt_len=0x%x\n",__FUNCTION__,evt_id,evt_len); ++ } ++ rtw_write8(padapter, REG_C2HEVT_CLEAR,0x0); ++ rtw_mdelay_os(1); ++ trigger=rtw_read8(padapter,REG_C2HEVT_CLEAR); ++ } ++ //DBG_8192C(" %s End\n",__FUNCTION__); ++} ++VOID ++rtl8192c_HalDmWatchDog( ++ IN PADAPTER Adapter ++ ) ++{ ++ BOOLEAN bFwCurrentInPSMode = _FALSE; ++ BOOLEAN bFwPSAwake = _TRUE; ++ PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); ++ struct dm_priv *pdmpriv = &pHalData->dmpriv; ++ ++ ++#ifdef CONFIG_LPS ++ bFwCurrentInPSMode = Adapter->pwrctrlpriv.bFwCurrentInPSMode; ++ Adapter->HalFunc.GetHwRegHandler(Adapter, HW_VAR_FWLPS_RF_ON, (u8 *)(&bFwPSAwake)); ++#endif ++ ++#ifdef CONFIG_P2P ++ // Fw is under p2p powersaving mode, driver should stop dynamic mechanism. ++ // modifed by thomas. 2011.06.11. ++ if(Adapter->wdinfo.p2p_ps_enable) ++ bFwPSAwake = _FALSE; ++#endif //CONFIG_P2P ++ ++ // Stop dynamic mechanism when: ++ // 1. RF is OFF. (No need to do DM.) ++ // 2. Fw is under power saving mode for FwLPS. (Prevent from SW/FW I/O racing.) ++ // 3. IPS workitem is scheduled. (Prevent from IPS sequence to be swapped with DM. ++ // Sometimes DM execution time is longer than 100ms such that the assertion ++ // in MgntActSet_RF_State() called by InactivePsWorkItem will be triggered by ++ // wating to long for RFChangeInProgress.) ++ // 4. RFChangeInProgress is TRUE. (Prevent from broken by IPS/HW/SW Rf off.) ++ // Noted by tynli. 2010.06.01. ++ //if(rfState == eRfOn) ++ if( (Adapter->hw_init_completed == _TRUE) ++ && ((!bFwCurrentInPSMode) && bFwPSAwake)) ++ { ++ // ++ // Calculate Tx/Rx statistics. ++ // ++ dm_CheckStatistics(Adapter); ++ ++ // ++ // For PWDB monitor and record some value for later use. ++ // ++ PWDB_Monitor(Adapter); ++ ++ // ++ // Dynamic Initial Gain mechanism. ++ // ++ ++ dm_RSSIMonitorCheck(Adapter); ++ ++ dm_FalseAlarmCounterStatistics(Adapter); ++ dm_DIG(Adapter); ++ ++ // ++ //Dynamic BB Power Saving Mechanism ++ // ++ dm_DynamicBBPowerSaving(Adapter); ++ ++ // ++ // Dynamic Tx Power mechanism. ++ // ++ dm_DynamicTxPower(Adapter); ++ ++ // ++ // Tx Power Tracking. ++ // ++ rtl8192c_dm_CheckTXPowerTracking(Adapter); ++ ++ // ++ // Rate Adaptive by Rx Signal Strength mechanism. ++ // ++ dm_RefreshRateAdaptiveMask(Adapter); ++ ++#ifdef CONFIG_BT_COEXIST ++ //BT-Coexist ++ dm_BTCoexist(Adapter); ++#endif ++ ++ // EDCA turbo ++ //update the EDCA paramter according to the Tx/RX mode ++ //update_EDCA_param(Adapter); ++ dm_CheckEdcaTurbo(Adapter); ++ ++ // ++ // Dynamically switch RTS/CTS protection. ++ // ++ //dm_CheckProtection(Adapter); ++ ++#ifdef CONFIG_SW_ANTENNA_DIVERSITY ++ // ++ // Software Antenna diversity ++ // ++ dm_SW_AntennaSwitch(Adapter, SWAW_STEP_PEAK); ++#endif ++ ++#ifdef CONFIG_HW_ANTENNA_DIVERSITY ++ //Hybrid Antenna Diversity ++ dm_SelectRXDefault(Adapter); ++#endif ++ ++#ifdef CONFIG_PCI_HCI ++ // 20100630 Joseph: Disable Interrupt Migration mechanism temporarily because it degrades Rx throughput. ++ // Tx Migration settings. ++ //dm_InterruptMigration(Adapter); ++ ++ //if(Adapter->HalFunc.TxCheckStuckHandler(Adapter)) ++ // PlatformScheduleWorkItem(&(GET_HAL_DATA(Adapter)->HalResetWorkItem)); ++#endif ++ ++#ifdef SUPPORT_64_STA ++ rtl8192c_HalDmPollingC2HEvt(Adapter); ++#endif //SUPPORT_64_STA ++ // Read REG_INIDATA_RATE_SEL value for TXDESC. ++ if(check_fwstate(&Adapter->mlmepriv, WIFI_STATION_STATE) == _TRUE) ++ { ++ pdmpriv->INIDATA_RATE[0] = rtw_read8(Adapter, REG_INIDATA_RATE_SEL) & 0x3f; ++ } ++ else ++ { ++ u8 i; ++ for(i=1 ;( i < (Adapter->stapriv.asoc_sta_count + 1))&&(i INIDATA_RATE[i] = rtw_read8(Adapter, (REG_INIDATA_RATE_SEL+i)) & 0x3f; ++ } ++ } ++ } ++ ++ // Check GPIO to determine current RF on/off and Pbc status. ++ // Check Hardware Radio ON/OFF or not ++ //if(Adapter->MgntInfo.PowerSaveControl.bGpioRfSw) ++ //{ ++ //RTPRINT(FPWR, PWRHW, ("dm_CheckRfCtrlGPIO \n")); ++ // dm_CheckRfCtrlGPIO(Adapter); ++ //} ++ ++#ifdef CONFIG_PCI_HCI ++ if(pHalData->bGpioHwWpsPbc) ++#endif ++ { ++ dm_CheckPbcGPIO(Adapter); // Add by hpfan 2008-03-11 ++ } ++ ++} ++ +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/hal/rtl8192c/rtl8192c_hal_init.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/hal/rtl8192c/rtl8192c_hal_init.c 2013-07-26 19:36:05.000000000 +0000 +@@ -0,0 +1,3642 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ *******************************************************************************/ ++ ++#define _RTL8192C_HAL_INIT_C_ ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#ifdef CONFIG_USB_HCI ++#include ++#endif ++ ++#ifdef CONFIG_PCI_HCI ++#include ++#endif ++ ++static BOOLEAN ++hal_EfusePgPacketWrite2ByteHeader( ++ IN PADAPTER pAdapter, ++ IN u8 efuseType, ++ IN u16 *pAddr, ++ IN PPGPKT_STRUCT pTargetPkt, ++ IN BOOLEAN bPseudoTest); ++static BOOLEAN ++hal_EfusePgPacketWrite1ByteHeader( ++ IN PADAPTER pAdapter, ++ IN u8 efuseType, ++ IN u16 *pAddr, ++ IN PPGPKT_STRUCT pTargetPkt, ++ IN BOOLEAN bPseudoTest); ++static BOOLEAN ++hal_EfusePgPacketWriteData( ++ IN PADAPTER pAdapter, ++ IN u8 efuseType, ++ IN u16 *pAddr, ++ IN PPGPKT_STRUCT pTargetPkt, ++ IN BOOLEAN bPseudoTest); ++static BOOLEAN ++hal_EfusePgPacketWrite_BT( ++ IN PADAPTER pAdapter, ++ IN u8 offset, ++ IN u8 word_en, ++ IN u8 *pData, ++ IN BOOLEAN bPseudoTest); ++ ++static VOID ++_FWDownloadEnable( ++ IN PADAPTER Adapter, ++ IN BOOLEAN enable ++ ) ++{ ++ u8 tmp; ++ ++ if(enable) ++ { ++ #ifdef DBG_SHOW_MCUFWDL_BEFORE_51_ENABLE ++ { ++ u8 val; ++ if( (val=rtw_read8(Adapter, REG_MCUFWDL))) ++ DBG_871X("DBG_SHOW_MCUFWDL_BEFORE_51_ENABLE %s:%d REG_MCUFWDL:0x%02x\n", __FUNCTION__, __LINE__, val); ++ } ++ #endif ++ ++ // 8051 enable ++ tmp = rtw_read8(Adapter, REG_SYS_FUNC_EN+1); ++ rtw_write8(Adapter, REG_SYS_FUNC_EN+1, tmp|0x04); ++ ++ // MCU firmware download enable. ++ tmp = rtw_read8(Adapter, REG_MCUFWDL); ++ rtw_write8(Adapter, REG_MCUFWDL, tmp|0x01); ++ ++ // 8051 reset ++ tmp = rtw_read8(Adapter, REG_MCUFWDL+2); ++ rtw_write8(Adapter, REG_MCUFWDL+2, tmp&0xf7); ++ } ++ else ++ { ++ // MCU firmware download enable. ++ tmp = rtw_read8(Adapter, REG_MCUFWDL); ++ rtw_write8(Adapter, REG_MCUFWDL, tmp&0xfe); ++ ++ // Reserved for fw extension. ++ //rtw_write8(Adapter, REG_MCUFWDL+1, 0x00); ++ } ++} ++ ++ ++#define MAX_REG_BOLCK_SIZE 196 ++#define MIN_REG_BOLCK_SIZE 8 ++ ++static int ++_BlockWrite( ++ IN PADAPTER Adapter, ++ IN PVOID buffer, ++ IN u32 size ++ ) ++{ ++ int ret = _SUCCESS; ++ ++#ifdef CONFIG_PCI_HCI ++ u32 blockSize = sizeof(u32); // Use 4-byte write to download FW ++ u8 *bufferPtr = (u8 *)buffer; ++ u32 *pu4BytePtr = (u32 *)buffer; ++ u32 i, offset, blockCount, remainSize; ++ ++ blockCount = size / blockSize; ++ remainSize = size % blockSize; ++ ++ for(i = 0 ; i < blockCount ; i++){ ++ offset = i * blockSize; ++ rtw_write32(Adapter, (FW_8192C_START_ADDRESS + offset), *(pu4BytePtr + i)); ++ } ++ ++ if(remainSize){ ++ offset = blockCount * blockSize; ++ bufferPtr += offset; ++ ++ for(i = 0 ; i < remainSize ; i++){ ++ rtw_write8(Adapter, (FW_8192C_START_ADDRESS + offset + i), *(bufferPtr + i)); ++ } ++ } ++#else ++ ++#ifdef SUPPORTED_BLOCK_IO ++ u32 blockSize = MAX_REG_BOLCK_SIZE; // Use 196-byte write to download FW ++ u32 blockSize2 = MIN_REG_BOLCK_SIZE; ++#else ++ u32 blockSize = sizeof(u32); // Use 4-byte write to download FW ++ u32* pu4BytePtr = (u32*)buffer; ++ u32 blockSize2 = sizeof(u8); ++#endif ++ u8* bufferPtr = (u8*)buffer; ++ u32 i, offset = 0, offset2, blockCount, remainSize, remainSize2; ++ ++ blockCount = size / blockSize; ++ remainSize = size % blockSize; ++ ++ for(i = 0 ; i < blockCount ; i++){ ++ offset = i * blockSize; ++ #ifdef SUPPORTED_BLOCK_IO ++ ret = rtw_writeN(Adapter, (FW_8192C_START_ADDRESS + offset), blockSize, (bufferPtr + offset)); ++ #else ++ ret = rtw_write32(Adapter, (FW_8192C_START_ADDRESS + offset), le32_to_cpu(*(pu4BytePtr + i))); ++ #endif ++ ++ if(ret == _FAIL) ++ goto exit; ++ } ++ ++ if(remainSize){ ++ #if defined(SUPPORTED_BLOCK_IO) && defined(DBG_BLOCK_WRITE_ISSUE) //Can this be enabled? ++ offset = blockCount * blockSize; ++ ret = rtw_writeN(Adapter, (FW_8192C_START_ADDRESS + offset), remainSize, (bufferPtr + offset)); ++ goto exit; ++ #endif ++ offset2 = blockCount * blockSize; ++ blockCount = remainSize / blockSize2; ++ remainSize2 = remainSize % blockSize2; ++ ++ for(i = 0 ; i < blockCount ; i++){ ++ offset = offset2 + i * blockSize2; ++ #ifdef SUPPORTED_BLOCK_IO ++ ret = rtw_writeN(Adapter, (FW_8192C_START_ADDRESS + offset), blockSize2, (bufferPtr + offset)); ++ #else ++ ret = rtw_write8(Adapter, (FW_8192C_START_ADDRESS + offset ), *(bufferPtr + offset)); ++ #endif ++ ++ if(ret == _FAIL) ++ goto exit; ++ } ++ ++ if(remainSize2) ++ { ++ offset += blockSize2; ++ bufferPtr += offset; ++ ++ for(i = 0 ; i < remainSize2 ; i++){ ++ ret = rtw_write8(Adapter, (FW_8192C_START_ADDRESS + offset + i), *(bufferPtr + i)); ++ ++ if(ret == _FAIL) ++ goto exit; ++ } ++ } ++ } ++#endif ++ ++exit: ++ return ret; ++} ++ ++static int ++_PageWrite( ++ IN PADAPTER Adapter, ++ IN u32 page, ++ IN PVOID buffer, ++ IN u32 size ++ ) ++{ ++ u8 value8; ++ u8 u8Page = (u8) (page & 0x07) ; ++ ++ value8 = (rtw_read8(Adapter, REG_MCUFWDL+2)& 0xF8 ) | u8Page ; ++ rtw_write8(Adapter, REG_MCUFWDL+2,value8); ++ return _BlockWrite(Adapter,buffer,size); ++} ++ ++static VOID ++_FillDummy( ++ u8* pFwBuf, ++ u32* pFwLen ++ ) ++{ ++ u32 FwLen = *pFwLen; ++ u8 remain = (u8)(FwLen%4); ++ remain = (remain==0)?0:(4-remain); ++ ++ while(remain>0) ++ { ++ pFwBuf[FwLen] = 0; ++ FwLen++; ++ remain--; ++ } ++ ++ *pFwLen = FwLen; ++} ++ ++static int ++_WriteFW( ++ IN PADAPTER Adapter, ++ IN PVOID buffer, ++ IN u32 size ++ ) ++{ ++ // Since we need dynamic decide method of dwonload fw, so we call this function to get chip version. ++ // We can remove _ReadChipVersion from ReadAdapterInfo8192C later. ++ ++ int ret = _SUCCESS; ++ BOOLEAN isNormalChip; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ ++ isNormalChip = IS_NORMAL_CHIP(pHalData->VersionID); ++ ++ if(isNormalChip){ ++ u32 pageNums,remainSize ; ++ u32 page,offset; ++ u8* bufferPtr = (u8*)buffer; ++ ++#ifdef CONFIG_PCI_HCI ++ // 20100120 Joseph: Add for 88CE normal chip. ++ // Fill in zero to make firmware image to dword alignment. ++ _FillDummy(bufferPtr, &size); ++#endif ++ ++ pageNums = size / MAX_PAGE_SIZE ; ++ //RT_ASSERT((pageNums <= 4), ("Page numbers should not greater then 4 \n")); ++ remainSize = size % MAX_PAGE_SIZE; ++ ++ for(page = 0; page < pageNums; page++){ ++ offset = page *MAX_PAGE_SIZE; ++ ret = _PageWrite(Adapter,page, (bufferPtr+offset),MAX_PAGE_SIZE); ++ ++ if(ret == _FAIL) ++ goto exit; ++ } ++ if(remainSize){ ++ offset = pageNums *MAX_PAGE_SIZE; ++ page = pageNums; ++ ret = _PageWrite(Adapter,page, (bufferPtr+offset),remainSize); ++ ++ if(ret == _FAIL) ++ goto exit; ++ } ++ //RT_TRACE(COMP_INIT, DBG_LOUD, ("_WriteFW Done- for Normal chip.\n")); ++ } ++ else { ++ ret = _BlockWrite(Adapter,buffer,size); ++ ++ if(ret == _FAIL) ++ goto exit; ++ //RT_TRACE(COMP_INIT, DBG_LOUD, ("_WriteFW Done- for Test chip.\n")); ++ } ++ ++exit: ++ return ret; ++} ++ ++static int _FWFreeToGo( ++ IN PADAPTER Adapter ++ ) ++{ ++ u32 counter = 0; ++ u32 value32; ++ u8 value8; ++ u32 restarted = _FALSE; ++ ++ // polling CheckSum report ++ do{ ++ value32 = rtw_read32(Adapter, REG_MCUFWDL); ++ }while((counter ++ < POLLING_READY_TIMEOUT_COUNT) && (!(value32 & FWDL_ChkSum_rpt))); ++ ++ if(counter >= POLLING_READY_TIMEOUT_COUNT){ ++ DBG_8192C("chksum report faill ! REG_MCUFWDL:0x%08x\n",value32); ++ return _FAIL; ++ } else { ++ //DBG_8192C("chksum report success ! REG_MCUFWDL:0x%08x, counter:%u\n",value32, counter); ++ } ++ //RT_TRACE(COMP_INIT, DBG_LOUD, ("Checksum report OK ! REG_MCUFWDL:0x%08x .\n",value32)); ++ ++ ++ value8 = rtw_read8(Adapter, REG_MCUFWDL); ++ value8 |= MCUFWDL_RDY; ++ value8 &= ~WINTINI_RDY; ++ rtw_write8(Adapter, REG_MCUFWDL, value8); ++ ++ ++POLLING_FW_READY: ++ // polling for FW ready ++ counter = 0; ++ do ++ { ++ if(rtw_read32(Adapter, REG_MCUFWDL) & WINTINI_RDY){ ++ //RT_TRACE(COMP_INIT, DBG_SERIOUS, ("Polling FW ready success!! REG_MCUFWDL:0x%08x .\n",PlatformIORead4Byte(Adapter, REG_MCUFWDL)) ); ++ return _SUCCESS; ++ } ++ rtw_udelay_os(5); ++ }while(counter++ < POLLING_READY_TIMEOUT_COUNT); ++ ++ DBG_8192C("Polling FW ready fail!! REG_MCUFWDL:0x%08x .\n", rtw_read32(Adapter, REG_MCUFWDL)); ++ ++ if(restarted == _FALSE) { ++ u8 tmp = rtw_read8(Adapter, REG_SYS_FUNC_EN+1); ++ DBG_8192C("Reset 51 write8 REG_SYS_FUNC_EN:0x%04x\n", tmp & ~BIT2); ++ rtw_write8(Adapter, REG_SYS_FUNC_EN+1, tmp & ~BIT2); ++ DBG_8192C("Reset 51 write8 REG_SYS_FUNC_EN:0x%04x\n", tmp|BIT2); ++ rtw_write8(Adapter, REG_SYS_FUNC_EN+1, tmp|BIT2); ++ restarted = _TRUE; ++ goto POLLING_FW_READY; ++ } ++ ++ ++ return _FAIL; ++ ++} ++ ++ ++VOID ++rtl8192c_FirmwareSelfReset( ++ IN PADAPTER Adapter ++) ++{ ++ u8 u1bTmp; ++ u8 Delay = 100; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ ++ if((pHalData->FirmwareVersion > 0x21) || ++ (pHalData->FirmwareVersion == 0x21 && ++ pHalData->FirmwareSubVersion >= 0x01)) // after 88C Fw v33.1 ++ { ++ //0x1cf=0x20. Inform 8051 to reset. 2009.12.25. tynli_test ++ rtw_write8(Adapter, REG_HMETFR+3, 0x20); ++ ++ u1bTmp = rtw_read8(Adapter, REG_SYS_FUNC_EN+1); ++ while(u1bTmp&BIT2) ++ { ++ Delay--; ++ if(Delay == 0) ++ break; ++ rtw_udelay_os(50); ++ u1bTmp = rtw_read8(Adapter, REG_SYS_FUNC_EN+1); ++ } ++ ++ if((u1bTmp&BIT2) && (Delay == 0)) ++ { ++ DBG_8192C("FirmwareDownload92C():fw reset by itself Fail!!!!!! 0x03 = %x\n", u1bTmp); ++ //RT_ASSERT(FALSE, ("PowerOffAdapter8192CE(): 0x03 = %x\n", u1bTmp)); ++ #ifdef DBG_SHOW_MCUFWDL_BEFORE_51_ENABLE ++ { ++ u8 val; ++ if( (val=rtw_read8(Adapter, REG_MCUFWDL))) ++ DBG_871X("DBG_SHOW_MCUFWDL_BEFORE_51_ENABLE %s:%d REG_MCUFWDL:0x%02x\n", __FUNCTION__, __LINE__, val); ++ } ++ #endif ++ rtw_write8(Adapter,REG_SYS_FUNC_EN+1,(rtw_read8(Adapter, REG_SYS_FUNC_EN+1)&~BIT2)); ++ } ++ ++ DBG_8192C("%s =====> 8051 reset success (%d) .\n", __FUNCTION__ ,Delay); ++ } ++} ++ ++#ifdef CONFIG_FILE_FWIMG ++extern char *rtw_fw_file_path; ++u8 FwBuffer8192C[FW_8192C_SIZE]; ++#endif //CONFIG_FILE_FWIMG ++// ++// Description: ++// Download 8192C firmware code. ++// ++// ++int FirmwareDownload92C( ++ IN PADAPTER Adapter, ++ IN BOOLEAN bUsedWoWLANFw ++) ++{ ++ int rtStatus = _SUCCESS; ++ u8 writeFW_retry = 0; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ s8 R92CFwImageFileName_TSMC[] ={RTL8192C_FW_TSMC_IMG}; ++ s8 R92CFwImageFileName_UMC[] ={RTL8192C_FW_UMC_IMG}; ++ s8 R92CFwImageFileName_UMC_B[] ={RTL8192C_FW_UMC_B_IMG}; ++#ifdef CONFIG_WOWLAN ++ s8 R92CFwImageFileName_TSMC_WW[] ={RTL8192C_FW_TSMC_WW_IMG}; ++ s8 R92CFwImageFileName_UMC_WW[] ={RTL8192C_FW_UMC_WW_IMG}; ++ s8 R92CFwImageFileName_UMC_B_WW[] ={RTL8192C_FW_UMC_B_WW_IMG}; ++#endif ++ ++ //s8 R8723FwImageFileName_UMC[] ={RTL8723_FW_UMC_IMG}; ++ u8* FwImage = NULL; ++ u32 FwImageLen = 0; ++ char* pFwImageFileName; ++#ifdef CONFIG_WOWLAN ++ u8* FwImageWoWLAN; ++ u32 FwImageWoWLANLen; ++ char* pFwImageFileName_WoWLAN; ++#endif ++ u8* pucMappedFile = NULL; ++ //vivi, merge 92c and 92s into one driver, 20090817 ++ //vivi modify this temply, consider it later!!!!!!!! ++ //PRT_FIRMWARE pFirmware = GET_FIRMWARE_819X(Adapter); ++ //PRT_FIRMWARE_92C pFirmware = GET_FIRMWARE_8192C(Adapter); ++ PRT_FIRMWARE_92C pFirmware = NULL; ++ PRT_8192C_FIRMWARE_HDR pFwHdr = NULL; ++ u8 *pFirmwareBuf; ++ u32 FirmwareLen; ++ ++ pFirmware = (PRT_FIRMWARE_92C)rtw_zvmalloc(sizeof(RT_FIRMWARE_92C)); ++ ++ if(!pFirmware) ++ { ++ rtStatus = _FAIL; ++ goto Exit; ++ } ++ ++ if(IS_NORMAL_CHIP(pHalData->VersionID)) ++ { ++ if(IS_VENDOR_UMC_A_CUT(pHalData->VersionID) && !IS_92C_SERIAL(pHalData->VersionID)) ++ { ++ pFwImageFileName = R92CFwImageFileName_UMC; ++ FwImage = Rtl819XFwUMCACutImageArray; ++ FwImageLen = UMCACutImgArrayLength; ++#ifdef CONFIG_WOWLAN ++ pFwImageFileName_WoWLAN = R92CFwImageFileName_UMC_WW; ++ FwImageWoWLAN= Rtl8192C_FwUMCWWImageArray; ++ FwImageWoWLANLen =UMCACutWWImgArrayLength ; ++#endif ++ DBG_8192C(" ===> FirmwareDownload91C() fw:Rtl819XFwImageArray_UMC\n"); ++ } ++ else if(IS_81xxC_VENDOR_UMC_B_CUT(pHalData->VersionID)) ++ { ++ // The ROM code of UMC B-cut Fw is the same as TSMC. by tynli. 2011.01.14. ++ pFwImageFileName = R92CFwImageFileName_UMC_B; ++ FwImage = Rtl819XFwUMCBCutImageArray; ++ FwImageLen = UMCBCutImgArrayLength; ++#ifdef CONFIG_WOWLAN ++ pFwImageFileName_WoWLAN = R92CFwImageFileName_UMC_B_WW; ++ FwImageWoWLAN= Rtl8192C_FwUMCBCutWWImageArray; ++ FwImageWoWLANLen =UMCBCutWWImgArrayLength ; ++#endif ++ ++ DBG_8192C(" ===> FirmwareDownload91C() fw:Rtl819XFwImageArray_UMC_B\n"); ++ } ++ else ++ { ++ pFwImageFileName = R92CFwImageFileName_TSMC; ++ FwImage = Rtl819XFwTSMCImageArray; ++ FwImageLen = TSMCImgArrayLength; ++#ifdef CONFIG_WOWLAN ++ pFwImageFileName_WoWLAN = R92CFwImageFileName_TSMC_WW; ++ FwImageWoWLAN= Rtl8192C_FwTSMCWWImageArray; ++ FwImageWoWLANLen =TSMCWWImgArrayLength ; ++#endif ++ DBG_8192C(" ===> FirmwareDownload91C() fw:Rtl819XFwImageArray_TSMC\n"); ++ } ++ } ++ else ++ { ++ #if 0 ++ pFwImageFileName = TestChipFwFile; ++ FwImage = Rtl8192CTestFwImg; ++ FwImageLen = Rtl8192CTestFwImgLen; ++ RT_TRACE(COMP_INIT, DBG_LOUD, (" ===> FirmwareDownload91C() fw:Rtl8192CTestFwImg\n")); ++ #endif ++ } ++ ++ //RT_TRACE(COMP_INIT, DBG_LOUD, (" ===> FirmwareDownload91C() fw:%s\n", pFwImageFileName)); ++ ++ #ifdef CONFIG_FILE_FWIMG ++ if(rtw_is_file_readable(rtw_fw_file_path) == _TRUE) ++ { ++ DBG_871X("%s accquire FW from file:%s\n", __FUNCTION__, rtw_fw_file_path); ++ pFirmware->eFWSource = FW_SOURCE_IMG_FILE; // We should decided by Reg. ++ } ++ else ++ #endif //CONFIG_FILE_FWIMG ++ { ++ DBG_871X("%s accquire FW from embedded image\n", __FUNCTION__); ++ pFirmware->eFWSource = FW_SOURCE_HEADER_FILE; ++ } ++ ++ ++ switch(pFirmware->eFWSource) ++ { ++ case FW_SOURCE_IMG_FILE: ++ ++ #ifdef CONFIG_FILE_FWIMG ++ rtStatus = rtw_retrive_from_file(rtw_fw_file_path, FwBuffer8192C, FW_8192C_SIZE); ++ pFirmware->ulFwLength = rtStatus>=0?rtStatus:0; ++ pFirmware->szFwBuffer = FwBuffer8192C; ++ #endif //CONFIG_FILE_FWIMG ++ ++ if(pFirmware->ulFwLength <= 0) ++ { ++ rtStatus = _FAIL; ++ goto Exit; ++ } ++ break; ++ case FW_SOURCE_HEADER_FILE: ++ if(FwImageLen > FW_8192C_SIZE){ ++ rtStatus = _FAIL; ++ //RT_TRACE(COMP_INIT, DBG_SERIOUS, ("Firmware size exceed 0x%X. Check it.\n", FW_8192C_SIZE) ); ++ DBG_871X("Firmware size exceed 0x%X. Check it.\n", FW_8192C_SIZE); ++ goto Exit; ++ } ++ ++ pFirmware->szFwBuffer = FwImage; ++ pFirmware->ulFwLength = FwImageLen; ++#ifdef CONFIG_WOWLAN ++ { ++ pFirmware->szWoWLANFwBuffer=FwImageWoWLAN; ++ pFirmware->ulWoWLANFwLength = FwImageWoWLANLen; ++ } ++#endif ++ ++ break; ++ } ++ ++#ifdef CONFIG_WOWLAN ++ if(bUsedWoWLANFw) { ++ pFirmwareBuf = pFirmware->szWoWLANFwBuffer; ++ FirmwareLen = pFirmware->ulWoWLANFwLength; ++ pFwHdr = (PRT_8192C_FIRMWARE_HDR)pFirmware->szWoWLANFwBuffer; ++ } ++ else ++#endif ++ { ++ #ifdef DBG_FW_STORE_FILE_PATH //used to store firmware to file... ++ if(pFirmware->ulFwLength > 0) ++ { ++ rtw_store_to_file(DBG_FW_STORE_FILE_PATH, pFirmware->szFwBuffer, pFirmware->ulFwLength); ++ } ++ #endif ++ ++ ++ ++ ++ pFirmwareBuf = pFirmware->szFwBuffer; ++ FirmwareLen = pFirmware->ulFwLength; ++ ++ // To Check Fw header. Added by tynli. 2009.12.04. ++ pFwHdr = (PRT_8192C_FIRMWARE_HDR)pFirmware->szFwBuffer; ++ } ++ pHalData->FirmwareVersion = le16_to_cpu(pFwHdr->Version); ++ pHalData->FirmwareSubVersion = le16_to_cpu(pFwHdr->Subversion); ++ ++ //RT_TRACE(COMP_INIT, DBG_LOUD, (" FirmwareVersion(%#x), Signature(%#x)\n", ++ // Adapter->MgntInfo.FirmwareVersion, pFwHdr->Signature)); ++ ++ DBG_8192C("fw_ver=v%d, fw_subver=%d, sig=0x%x\n", ++ pHalData->FirmwareVersion, pHalData->FirmwareSubVersion, le16_to_cpu(pFwHdr->Signature)&0xFFF0); ++ ++ if(IS_FW_HEADER_EXIST(pFwHdr)) ++ { ++ //RT_TRACE(COMP_INIT, DBG_LOUD,("Shift 32 bytes for FW header!!\n")); ++ pFirmwareBuf = pFirmwareBuf + 32; ++ FirmwareLen = FirmwareLen -32; ++ } ++ ++ // Suggested by Filen. If 8051 is running in RAM code, driver should inform Fw to reset by itself, ++ // or it will cause download Fw fail. 2010.02.01. by tynli. ++ if(rtw_read8(Adapter, REG_MCUFWDL)&BIT7) //8051 RAM code ++ { ++ rtl8192c_FirmwareSelfReset(Adapter); ++ rtw_write8(Adapter, REG_MCUFWDL, 0x00); ++ } ++ ++ ++ _FWDownloadEnable(Adapter, _TRUE); ++ while(1) { ++ u8 tmp8; ++ tmp8 = rtw_read8(Adapter, REG_MCUFWDL); ++ ++ //reset the FWDL chksum ++ rtw_write8(Adapter, REG_MCUFWDL, tmp8|FWDL_ChkSum_rpt); ++ ++ //tmp8 = rtw_read8(Adapter, REG_MCUFWDL); ++ //DBG_8192C("Before _WriteFW, REG_MCUFWDL:0x%02x, writeFW_retry:%u\n", tmp8, writeFW_retry); ++ ++ rtStatus = _WriteFW(Adapter, pFirmwareBuf, FirmwareLen); ++ ++ //tmp8 = rtw_read8(Adapter, REG_MCUFWDL); ++ //DBG_8192C("After _WriteFW, REG_MCUFWDL:0x%02x, rtStatus:%d\n", tmp8, rtStatus); ++ ++ if(rtStatus == _SUCCESS || ++writeFW_retry>3) ++ break; ++ } ++ _FWDownloadEnable(Adapter, _FALSE); ++ if(_SUCCESS != rtStatus){ ++ DBG_8192C("DL Firmware failed!\n"); ++ goto Exit; ++ } ++ ++ rtStatus = _FWFreeToGo(Adapter); ++ if(_SUCCESS != rtStatus){ ++ DBG_8192C("DL Firmware failed!\n"); ++ goto Exit; ++ } ++ //RT_TRACE(COMP_INIT, DBG_LOUD, (" Firmware is ready to run!\n")); ++ ++Exit: ++ ++ if(pFirmware) { ++ rtw_vmfree((u8*)pFirmware, sizeof(RT_FIRMWARE_92C)); ++ } ++ ++ //RT_TRACE(COMP_INIT, DBG_LOUD, (" <=== FirmwareDownload91C()\n")); ++ return rtStatus; ++ ++} ++ ++VOID ++InitializeFirmwareVars92C( ++ IN PADAPTER Adapter ++) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ ++ // Init Fw LPS related. ++ Adapter->pwrctrlpriv.bFwCurrentInPSMode = _FALSE; ++ ++ //Init H2C counter. by tynli. 2009.12.09. ++ pHalData->LastHMEBoxNum = 0; ++} ++ ++ ++//=========================================== ++ ++// ++// Description: Prepare some information to Fw for WoWLAN. ++// (1) Download wowlan Fw. ++// (2) Download RSVD page packets. ++// (3) Enable AP offload if needed. ++// ++// 2011.04.12 by tynli. ++// ++VOID ++SetFwRelatedForWoWLAN8192CU( ++ IN PADAPTER padapter, ++ IN u8 bHostIsGoingtoSleep ++) ++{ ++ int status=_FAIL; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); ++ u8 bRecover = _FALSE; ++ ++ if(bHostIsGoingtoSleep) ++ { ++ // ++ // 1. Before WoWLAN we need to re-download WoWLAN Fw. ++ // ++ status = FirmwareDownload92C(padapter, bHostIsGoingtoSleep); ++ if(status != _SUCCESS) ++ { ++ DBG_8192C("ConfigFwRelatedForWoWLAN8192CU(): Re-Download Firmware failed!!\n"); ++ return; ++ } ++ else ++ { ++ DBG_8192C("ConfigFwRelatedForWoWLAN8192CU(): Re-Download Firmware Success !!\n"); ++ } ++ ++ // ++ // 2. Re-Init the variables about Fw related setting. ++ // ++ InitializeFirmwareVars92C(padapter); ++ ++ ++ } ++} ++ ++ ++#ifdef CONFIG_BT_COEXIST ++static void _update_bt_param(_adapter *padapter) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); ++ struct btcoexist_priv *pbtpriv = &(pHalData->bt_coexist); ++ struct registry_priv *registry_par = &padapter->registrypriv; ++ ++ if(2 != registry_par->bt_iso) ++ pbtpriv->BT_Ant_isolation = registry_par->bt_iso;// 0:Low, 1:High, 2:From Efuse ++ ++ if(registry_par->bt_sco == 1) // 0:Idle, 1:None-SCO, 2:SCO, 3:From Counter, 4.Busy, 5.OtherBusy ++ pbtpriv->BT_Service = BT_OtherAction; ++ else if(registry_par->bt_sco==2) ++ pbtpriv->BT_Service = BT_SCO; ++ else if(registry_par->bt_sco==4) ++ pbtpriv->BT_Service = BT_Busy; ++ else if(registry_par->bt_sco==5) ++ pbtpriv->BT_Service = BT_OtherBusy; ++ else ++ pbtpriv->BT_Service = BT_Idle; ++ ++ pbtpriv->BT_Ampdu = registry_par->bt_ampdu; ++ pbtpriv->bCOBT = _TRUE; ++#if 1 ++ DBG_8192C("BT Coexistance = %s\n", (pbtpriv->BT_Coexist==_TRUE)?"enable":"disable"); ++ if(pbtpriv->BT_Coexist) ++ { ++ if(pbtpriv->BT_Ant_Num == Ant_x2) ++ { ++ DBG_8192C("BlueTooth BT_Ant_Num = Antx2\n"); ++ } ++ else if(pbtpriv->BT_Ant_Num == Ant_x1) ++ { ++ DBG_8192C("BlueTooth BT_Ant_Num = Antx1\n"); ++ } ++ switch(pbtpriv->BT_CoexistType) ++ { ++ case BT_2Wire: ++ DBG_8192C("BlueTooth BT_CoexistType = BT_2Wire\n"); ++ break; ++ case BT_ISSC_3Wire: ++ DBG_8192C("BlueTooth BT_CoexistType = BT_ISSC_3Wire\n"); ++ break; ++ case BT_Accel: ++ DBG_8192C("BlueTooth BT_CoexistType = BT_Accel\n"); ++ break; ++ case BT_CSR_BC4: ++ DBG_8192C("BlueTooth BT_CoexistType = BT_CSR_BC4\n"); ++ break; ++ case BT_RTL8756: ++ DBG_8192C("BlueTooth BT_CoexistType = BT_RTL8756\n"); ++ break; ++ default: ++ DBG_8192C("BlueTooth BT_CoexistType = Unknown\n"); ++ break; ++ } ++ DBG_8192C("BlueTooth BT_Ant_isolation = %d\n", pbtpriv->BT_Ant_isolation); ++ ++ ++ switch(pbtpriv->BT_Service) ++ { ++ case BT_OtherAction: ++ DBG_8192C("BlueTooth BT_Service = BT_OtherAction\n"); ++ break; ++ case BT_SCO: ++ DBG_8192C("BlueTooth BT_Service = BT_SCO\n"); ++ break; ++ case BT_Busy: ++ DBG_8192C("BlueTooth BT_Service = BT_Busy\n"); ++ break; ++ case BT_OtherBusy: ++ DBG_8192C("BlueTooth BT_Service = BT_OtherBusy\n"); ++ break; ++ default: ++ DBG_8192C("BlueTooth BT_Service = BT_Idle\n"); ++ break; ++ } ++ ++ DBG_8192C("BT_RadioSharedType = 0x%x\n", pbtpriv->BT_RadioSharedType); ++ } ++#endif ++ ++} ++ ++ ++#define GET_BT_COEXIST(priv) (&priv->bt_coexist) ++ ++void rtl8192c_ReadBluetoothCoexistInfo( ++ IN PADAPTER Adapter, ++ IN u8* PROMContent, ++ IN BOOLEAN AutoloadFail ++ ) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ BOOLEAN isNormal = IS_NORMAL_CHIP(pHalData->VersionID); ++ struct btcoexist_priv *pbtpriv = &(pHalData->bt_coexist); ++ u8 rf_opt4; ++ ++ if(AutoloadFail){ ++ pbtpriv->BT_Coexist = _FALSE; ++ pbtpriv->BT_CoexistType= BT_2Wire; ++ pbtpriv->BT_Ant_Num = Ant_x2; ++ pbtpriv->BT_Ant_isolation= 0; ++ pbtpriv->BT_RadioSharedType = BT_Radio_Shared; ++ return; ++ } ++ ++ if(isNormal) ++ { ++ pbtpriv->BT_Coexist = (((PROMContent[EEPROM_RF_OPT1]&BOARD_TYPE_NORMAL_MASK)>>5) == BOARD_USB_COMBO)?_TRUE:_FALSE; // bit [7:5] ++ rf_opt4 = PROMContent[EEPROM_RF_OPT4]; ++ pbtpriv->BT_CoexistType = ((rf_opt4&0xe)>>1); // bit [3:1] ++ pbtpriv->BT_Ant_Num = (rf_opt4&0x1); // bit [0] ++ pbtpriv->BT_Ant_isolation = ((rf_opt4&0x10)>>4); // bit [4] ++ pbtpriv->BT_RadioSharedType = ((rf_opt4&0x20)>>5); // bit [5] ++ } ++ else ++ { ++ pbtpriv->BT_Coexist = (PROMContent[EEPROM_RF_OPT4] >> 4) ? _TRUE : _FALSE; ++ } ++ _update_bt_param(Adapter); ++ ++} ++#endif ++ ++VERSION_8192C ++rtl8192c_ReadChipVersion( ++ IN PADAPTER Adapter ++ ) ++{ ++ u32 value32; ++ //VERSION_8192C version; ++ u32 ChipVersion=0; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ ++ value32 = rtw_read32(Adapter, REG_SYS_CFG); ++ ++ if (value32 & TRP_VAUX_EN) ++ { ++#if 0 ++ // Test chip. ++ if(IS_HARDWARE_TYPE_8723(Adapter)) { ++ ChipVersion |= ((value32 & VENDOR_ID) ? CHIP_VENDOR_UMC : 0); ++ ChipVersion |= ((value32 & BT_FUNC) ? CHIP_8723: 0); // RTL8723 with BT function. ++ } ++ else { ++ version = (value32 & TYPE_ID) ?VERSION_TEST_CHIP_92C :VERSION_TEST_CHIP_88C; ++ } ++#else ++ // tynli_test. 2011.01.10. ++ if(IS_HARDWARE_TYPE_8192C(Adapter)) ++ { ++ ChipVersion = (value32 & TYPE_ID) ? VERSION_TEST_CHIP_92C : VERSION_TEST_CHIP_88C; ++ } ++ else ++ { ++ ChipVersion |= ((value32 & VENDOR_ID) ? CHIP_VENDOR_UMC : 0); ++ ChipVersion |= ((value32 & BT_FUNC) ? CHIP_8723: 0); // RTL8723 with BT function. ++ } ++#endif ++ } ++ else ++ { ++#if 0 ++ // Normal mass production chip. ++ ChipVersion = NORMAL_CHIP; ++#if !RTL8723_FPGA_TRUE_PHY_VERIFICATION ++ ChipVersion |= ((value32 & TYPE_ID) ? CHIP_92C : 0); ++#endif ++ ChipVersion |= ((value32 & VENDOR_ID) ? CHIP_VENDOR_UMC : 0); ++ ChipVersion |= ((value32 & BT_FUNC) ? CHIP_8723: 0); // RTL8723 with BT function. ++ if(IS_8723_SERIES(ChipVersion)) ++ { ++ if(IS_VENDOR_UMC(ChipVersion)) ++ ChipVersion |= ((value32 & CHIP_VER_RTL_MASK) ? CHIP_VENDOR_UMC_B_CUT : 0); ++ } ++ else ++ { ++ // Mark out by tynli. UMC B-cut IC will not set the SYS_CFG[19] to UMC ++ // because we do not want the custmor to know. 2011.01.11. ++ //if(IS_VENDOR_UMC(ChipVersion)) ++ { ++ // To check the value of B-cut. by tynli. 2011.01.11. ++ u1bTmp = (u1Byte)((value32 & CHIP_VER_RTL_MASK)>>12); ++ if(u1bTmp == 1) ++ { // B-cut ++ ChipVersion |= CHIP_VENDOR_UMC_B_CUT; ++ } ++ } ++ } ++#else ++ // Normal mass production chip. ++ ChipVersion = NORMAL_CHIP; ++//#if !RTL8723_FPGA_TRUE_PHY_VERIFICATION ++ ChipVersion |= ((value32 & TYPE_ID) ? RF_TYPE_2T2R : 0); //92c ++//#endif ++ ChipVersion |= ((value32 & VENDOR_ID) ? CHIP_VENDOR_UMC : 0); ++ ChipVersion |= ((value32 & BT_FUNC) ? CHIP_8723: 0); // RTL8723 with BT function. ++ if(IS_HARDWARE_TYPE_8192C(Adapter)) ++ { ++ // 88/92C UMC B-cut IC will not set the SYS_CFG[19] to UMC ++ // because we do not want the custmor to know. by tynli. 2011.01.17. ++ //MSG_8192C("mask result = 0x%x is_UMC %d chipversion 0x%x\n", (value32 & CHIP_VER_RTL_MASK), IS_CHIP_VENDOR_UMC(ChipVersion), ChipVersion); ++ if((!IS_CHIP_VENDOR_UMC(ChipVersion) )&& (value32 & CHIP_VER_RTL_MASK)) ++ { ++ //MSG_8192C("chip mask result = 0x%x\n", ((value32 & CHIP_VER_RTL_MASK) | CHIP_VENDOR_UMC)); ++ ChipVersion |= ((value32 & CHIP_VER_RTL_MASK) | CHIP_VENDOR_UMC); // IC version (CUT) ++ //MSG_8192C("chip version = 0x%x\n", ChipVersion); ++ } ++ } ++ else ++ { ++ if(IS_CHIP_VENDOR_UMC(ChipVersion)) ++ ChipVersion |= ((value32 & CHIP_VER_RTL_MASK)); // IC version (CUT) ++ } ++ ++ if(IS_92C_SERIAL(ChipVersion)) ++ { ++ value32 = rtw_read32(Adapter, REG_HPON_FSM); ++ ChipVersion |= ((CHIP_BONDING_IDENTIFIER(value32) == CHIP_BONDING_92C_1T2R) ? RF_TYPE_1T2R : 0); ++ } ++ else if(IS_8723_SERIES(ChipVersion)) ++ { ++ //RT_ASSERT(IS_HARDWARE_TYPE_8723(Adapter), ("Incorrect chip version!!\n")); ++ value32 = rtw_read32(Adapter, REG_GPIO_OUTSTS); ++ ChipVersion |= ((value32 & RF_RL_ID)>>20); //ROM code version. ++ } ++#endif ++ ++ } ++ ++ //version = (VERSION_8192C)ChipVersion; ++ ++ // For multi-function consideration. Added by Roger, 2010.10.06. ++ if(IS_8723_SERIES(ChipVersion)) ++ { ++ pHalData->MultiFunc = RT_MULTI_FUNC_NONE; ++ value32 = rtw_read32(Adapter, REG_MULTI_FUNC_CTRL); ++ pHalData->MultiFunc =(RT_MULTI_FUNC) (pHalData->MultiFunc| ((value32 & WL_FUNC_EN) ? RT_MULTI_FUNC_WIFI : 0) ); ++ pHalData->MultiFunc =(RT_MULTI_FUNC) (pHalData->MultiFunc| ((value32 & BT_FUNC_EN) ? RT_MULTI_FUNC_BT : 0) ); ++ pHalData->MultiFunc =(RT_MULTI_FUNC) (pHalData->MultiFunc| ((value32 & GPS_FUNC_EN) ? RT_MULTI_FUNC_GPS : 0) ); ++ pHalData->PolarityCtl = ((value32 & WL_HWPDN_SL) ? RT_POLARITY_HIGH_ACT : RT_POLARITY_LOW_ACT); ++ //MSG_8192C("ReadChipVersion(): MultiFunc(%x), PolarityCtl(%x) \n", pHalData->MultiFunc, pHalData->PolarityCtl); ++ ++ //For regulator mode. by tynli. 2011.01.14 ++ pHalData->RegulatorMode = ((value32 & TRP_BT_EN) ? RT_LDO_REGULATOR : RT_SWITCHING_REGULATOR); ++ //MSG_8192C("ReadChipVersion(): RegulatorMode(%x) \n", pHalData->RegulatorMode); ++ } ++ ++//#if DBG ++#if 1 ++ switch(ChipVersion) ++ { ++ case VERSION_NORMAL_TSMC_CHIP_92C_1T2R: ++ MSG_8192C("Chip Version ID: VERSION_NORMAL_TSMC_CHIP_92C_1T2R.\n"); ++ break; ++ case VERSION_NORMAL_TSMC_CHIP_92C: ++ MSG_8192C("Chip Version ID: VERSION_NORMAL_TSMC_CHIP_92C.\n"); ++ break; ++ case VERSION_NORMAL_TSMC_CHIP_88C: ++ MSG_8192C("Chip Version ID: VERSION_NORMAL_TSMC_CHIP_88C.\n"); ++ break; ++ case VERSION_NORMAL_UMC_CHIP_92C_1T2R_A_CUT: ++ MSG_8192C("Chip Version ID: VERSION_NORMAL_UMC_CHIP_92C_1T2R_A_CUT.\n"); ++ break; ++ case VERSION_NORMAL_UMC_CHIP_92C_A_CUT: ++ MSG_8192C("Chip Version ID: VERSION_NORMAL_UMC_CHIP_92C_A_CUT.\n"); ++ break; ++ case VERSION_NORMAL_UMC_CHIP_88C_A_CUT: ++ MSG_8192C("Chip Version ID: VERSION_NORMAL_UMC_CHIP_88C_A_CUT.\n"); ++ break; ++ case VERSION_NORMAL_UMC_CHIP_92C_1T2R_B_CUT: ++ MSG_8192C("Chip Version ID: VERSION_NORMAL_UMC_CHIP_92C_1T2R_B_CUT.\n"); ++ break; ++ case VERSION_NORMAL_UMC_CHIP_92C_B_CUT: ++ MSG_8192C("Chip Version ID: VERSION_NORMAL_UMC_CHIP_92C_B_CUT.\n"); ++ break; ++ case VERSION_NORMAL_UMC_CHIP_88C_B_CUT: ++ MSG_8192C("Chip Version ID: VERSION_NORMAL_UMC_CHIP_88C_B_CUT.\n"); ++ break; ++ case VERSION_TEST_CHIP_92C: ++ MSG_8192C("Chip Version ID: VERSION_TEST_CHIP_92C.\n"); ++ break; ++ case VERSION_TEST_CHIP_88C: ++ MSG_8192C("Chip Version ID: VERSION_TEST_CHIP_88C.\n"); ++ break; ++ case VERSION_TEST_UMC_CHIP_8723: ++ MSG_8192C("Chip Version ID: VERSION_TEST_UMC_CHIP_8723.\n"); ++ break; ++ case VERSION_NORMAL_UMC_CHIP_8723_1T1R_A_CUT: ++ MSG_8192C("Chip Version ID: VERSION_NORMA_UMC_CHIP_8723_1T1R_A_CUT.\n"); ++ break; ++ case VERSION_NORMAL_UMC_CHIP_8723_1T1R_B_CUT: ++ MSG_8192C("Chip Version ID: VERSION_NORMA_UMC_CHIP_8723_1T1R_B_CUT.\n"); ++ break; ++ default: ++ MSG_8192C("Chip Version ID: ???????????????.\n"); ++ break; ++ } ++#endif ++ ++ pHalData->VersionID = ChipVersion; ++ ++ if(IS_1T2R(ChipVersion)) ++ pHalData->rf_type = RF_1T2R; ++ else if(IS_2T2R(ChipVersion)) ++ pHalData->rf_type = RF_2T2R; ++ else if(IS_8723_SERIES(ChipVersion)) ++ pHalData->rf_type = RF_1T1R; ++ else ++ pHalData->rf_type = RF_1T1R; ++ ++ MSG_8192C("RF_Type is %x!!\n", pHalData->rf_type); ++ ++ return ChipVersion; ++} ++ ++ ++RT_CHANNEL_DOMAIN ++_HalMapChannelPlan8192C( ++ IN PADAPTER Adapter, ++ IN u8 HalChannelPlan ++ ) ++{ ++ RT_CHANNEL_DOMAIN rtChannelDomain; ++ ++ switch(HalChannelPlan) ++ { ++#if 0 /* Not using EEPROM_CHANNEL_PLAN directly */ ++ case EEPROM_CHANNEL_PLAN_GLOBAL_DOMAIN: ++ rtChannelDomain = RT_CHANNEL_DOMAIN_GLOBAL_DOAMIN; ++ break; ++ case EEPROM_CHANNEL_PLAN_WORLD_WIDE_13: ++ rtChannelDomain = RT_CHANNEL_DOMAIN_WORLD_WIDE_13; ++ break; ++#endif /* Not using EEPROM_CHANNEL_PLAN directly */ ++ default: ++ if(HalChannelPlan == 0xFF) ++ rtChannelDomain = RT_CHANNEL_DOMAIN_WORLD_WIDE_13; ++ else ++ rtChannelDomain = (RT_CHANNEL_DOMAIN)HalChannelPlan; ++ break; ++ } ++ ++ return rtChannelDomain; ++ ++} ++ ++u8 GetEEPROMSize8192C(PADAPTER Adapter) ++{ ++ u8 size = 0; ++ u32 curRCR; ++ ++ curRCR = rtw_read16(Adapter, REG_9346CR); ++ size = (curRCR & BOOT_FROM_EEPROM) ? 6 : 4; // 6: EEPROM used is 93C46, 4: boot from E-Fuse. ++ ++ MSG_8192C("EEPROM type is %s\n", size==4 ? "E-FUSE" : "93C46"); ++ ++ return size; ++} ++ ++void rtl8192c_HalSetBrateCfg( ++ IN PADAPTER Adapter, ++ IN u8 *mBratesOS, ++ OUT u16 *pBrateCfg ++) ++{ ++ u8 is_brate; ++ u8 i; ++ u8 brate; ++ ++ for(i=0;i rtl8192c_free_hal_data =====\n"); ++ ++ if(padapter->HalData) ++ rtw_mfree(padapter->HalData, sizeof(HAL_DATA_TYPE)); ++ DBG_8192C("<===== rtl8192c_free_hal_data =====\n"); ++ ++_func_exit_; ++} ++ ++//=========================================================== ++// Efuse related code ++//=========================================================== ++enum{ ++ VOLTAGE_V25 = 0x03, ++ LDOE25_SHIFT = 28 , ++ }; ++ ++static VOID ++hal_EfusePowerSwitch_RTL8192C( ++ IN PADAPTER pAdapter, ++ IN u8 bWrite, ++ IN u8 PwrState) ++{ ++ u8 tempval; ++ u16 tmpV16; ++ ++ if (PwrState == _TRUE) ++ { ++ // 1.2V Power: From VDDON with Power Cut(0x0000h[15]), defualt valid ++ tmpV16 = rtw_read16(pAdapter,REG_SYS_ISO_CTRL); ++ if( ! (tmpV16 & PWC_EV12V ) ){ ++ tmpV16 |= PWC_EV12V ; ++ rtw_write16(pAdapter,REG_SYS_ISO_CTRL,tmpV16); ++ } ++ // Reset: 0x0000h[28], default valid ++ tmpV16 = rtw_read16(pAdapter,REG_SYS_FUNC_EN); ++ if( !(tmpV16 & FEN_ELDR) ){ ++ tmpV16 |= FEN_ELDR ; ++ rtw_write16(pAdapter,REG_SYS_FUNC_EN,tmpV16); ++ } ++ ++ // Clock: Gated(0x0008h[5]) 8M(0x0008h[1]) clock from ANA, default valid ++ tmpV16 = rtw_read16(pAdapter,REG_SYS_CLKR); ++ if( (!(tmpV16 & LOADER_CLK_EN) ) ||(!(tmpV16 & ANA8M) ) ){ ++ tmpV16 |= (LOADER_CLK_EN |ANA8M ) ; ++ rtw_write16(pAdapter,REG_SYS_CLKR,tmpV16); ++ } ++ ++ if(bWrite == _TRUE) ++ { ++ // Enable LDO 2.5V before read/write action ++ tempval = rtw_read8(pAdapter, EFUSE_TEST+3); ++ tempval &= 0x0F; ++ tempval |= (VOLTAGE_V25 << 4); ++ rtw_write8(pAdapter, EFUSE_TEST+3, (tempval | 0x80)); ++ } ++ } ++ else ++ { ++ if(bWrite == _TRUE){ ++ // Disable LDO 2.5V after read/write action ++ tempval = rtw_read8(pAdapter, EFUSE_TEST+3); ++ rtw_write8(pAdapter, EFUSE_TEST+3, (tempval & 0x7F)); ++ } ++ } ++} ++ ++static VOID ++hal_EfusePowerSwitch_RTL8723( ++ IN PADAPTER pAdapter, ++ IN u8 bWrite, ++ IN u8 PwrState) ++{ ++ u8 tempval; ++ u16 tmpV16; ++ ++ if (PwrState == _TRUE) ++ { ++ rtw_write8(pAdapter, REG_EFUSE_ACCESS, EFUSE_ACCESS_ON); ++ ++ // 1.2V Power: From VDDON with Power Cut(0x0000h[15]), defualt valid ++ tmpV16 = rtw_read16(pAdapter,REG_SYS_ISO_CTRL); ++ if( ! (tmpV16 & PWC_EV12V ) ){ ++ tmpV16 |= PWC_EV12V ; ++ rtw_write16(pAdapter,REG_SYS_ISO_CTRL,tmpV16); ++ } ++ // Reset: 0x0000h[28], default valid ++ tmpV16 = rtw_read16(pAdapter,REG_SYS_FUNC_EN); ++ if( !(tmpV16 & FEN_ELDR) ){ ++ tmpV16 |= FEN_ELDR ; ++ rtw_write16(pAdapter,REG_SYS_FUNC_EN,tmpV16); ++ } ++ ++ // Clock: Gated(0x0008h[5]) 8M(0x0008h[1]) clock from ANA, default valid ++ tmpV16 = rtw_read16(pAdapter,REG_SYS_CLKR); ++ if( (!(tmpV16 & LOADER_CLK_EN) ) ||(!(tmpV16 & ANA8M) ) ){ ++ tmpV16 |= (LOADER_CLK_EN |ANA8M ) ; ++ rtw_write16(pAdapter,REG_SYS_CLKR,tmpV16); ++ } ++ ++ if(bWrite == _TRUE) ++ { ++ // Enable LDO 2.5V before read/write action ++ tempval = rtw_read8(pAdapter, EFUSE_TEST+3); ++ tempval &= 0x0F; ++ tempval |= (VOLTAGE_V25 << 4); ++ rtw_write8(pAdapter, EFUSE_TEST+3, (tempval | 0x80)); ++ } ++ } ++ else ++ { ++ rtw_write8(pAdapter, REG_EFUSE_ACCESS, EFUSE_ACCESS_OFF); ++ ++ if(bWrite == _TRUE){ ++ // Disable LDO 2.5V after read/write action ++ tempval = rtw_read8(pAdapter, EFUSE_TEST+3); ++ rtw_write8(pAdapter, EFUSE_TEST+3, (tempval & 0x7F)); ++ } ++ } ++} ++ ++static VOID ++rtl8192c_EfusePowerSwitch( ++ IN PADAPTER pAdapter, ++ IN u8 bWrite, ++ IN u8 PwrState) ++{ ++ if(IS_HARDWARE_TYPE_8192C(pAdapter)) ++ { ++ hal_EfusePowerSwitch_RTL8192C(pAdapter, bWrite, PwrState); ++ } ++ else if(IS_HARDWARE_TYPE_8723(pAdapter)) ++ { ++ hal_EfusePowerSwitch_RTL8723(pAdapter, bWrite, PwrState); ++ } ++} ++ ++static VOID ++ReadEFuse_RTL8192C( ++ PADAPTER Adapter, ++ u16 _offset, ++ u16 _size_byte, ++ u8 *pbuf, ++ IN BOOLEAN bPseudoTest ++ ) ++{ ++ u8 efuseTbl[EFUSE_MAP_LEN]; ++ u8 rtemp8[1]; ++ u16 eFuse_Addr = 0; ++ u8 offset, wren; ++ u16 i, j; ++ u16 eFuseWord[EFUSE_MAX_SECTION][EFUSE_MAX_WORD_UNIT]; ++ u16 efuse_utilized = 0; ++ u8 efuse_usage = 0; ++ ++ // ++ // Do NOT excess total size of EFuse table. Added by Roger, 2008.11.10. ++ // ++ if((_offset + _size_byte)>EFUSE_MAP_LEN) ++ {// total E-Fuse table is 128bytes ++ //DBG_8192C("ReadEFuse_RTL8192C(): Invalid offset(%#x) with read bytes(%#x)!!\n",_offset, _size_byte); ++ return; ++ } ++ ++ // 0. Refresh efuse init map as all oxFF. ++ for (i = 0; i < EFUSE_MAX_SECTION; i++) ++ for (j = 0; j < EFUSE_MAX_WORD_UNIT; j++) ++ eFuseWord[i][j] = 0xFFFF; ++ ++ ++ // ++ // 1. Read the first byte to check if efuse is empty!!! ++ // ++ // ++ ReadEFuseByte(Adapter, eFuse_Addr, rtemp8, bPseudoTest); ++ if(*rtemp8 != 0xFF) ++ { ++ efuse_utilized++; ++ //RTPRINT(FEEPROM, EFUSE_READ_ALL, ("Addr=%d\n", eFuse_Addr)); ++ eFuse_Addr++; ++ } ++ ++ // ++ // 2. Read real efuse content. Filter PG header and every section data. ++ // ++ while((*rtemp8 != 0xFF) && (eFuse_Addr < EFUSE_REAL_CONTENT_LEN)) ++ { ++ // Check PG header for section num. ++ offset = ((*rtemp8 >> 4) & 0x0f); ++ ++ if(offset < EFUSE_MAX_SECTION) ++ { ++ // Get word enable value from PG header ++ wren = (*rtemp8 & 0x0f); ++ //RTPRINT(FEEPROM, EFUSE_READ_ALL, ("Offset-%d Worden=%x\n", offset, wren)); ++ ++ for(i=0; i= EFUSE_REAL_CONTENT_LEN) ++ break; ++ ++ //RTPRINT(FEEPROM, EFUSE_READ_ALL, ("Addr=%d\n", eFuse_Addr)); ++ ReadEFuseByte(Adapter, eFuse_Addr, rtemp8, bPseudoTest); eFuse_Addr++; ++ efuse_utilized++; ++ eFuseWord[offset][i] |= (((u16)*rtemp8 << 8) & 0xff00); ++ ++ if(eFuse_Addr >= EFUSE_REAL_CONTENT_LEN) ++ break; ++ } ++ ++ wren >>= 1; ++ ++ } ++ } ++ ++ //RTPRINT(FEEPROM, EFUSE_READ_ALL, ("Addr=%d\n", eFuse_Addr)); ++ // Read next PG header ++ ReadEFuseByte(Adapter, eFuse_Addr, rtemp8, bPseudoTest); ++ if(*rtemp8 != 0xFF && (eFuse_Addr < 512)) ++ { ++ efuse_utilized++; ++ eFuse_Addr++; ++ } ++ } ++ ++ // ++ // 3. Collect 16 sections and 4 word unit into Efuse map. ++ // ++ for(i=0; i> 8) & 0xff); ++ } ++ } ++ ++ // ++ // 4. Copy from Efuse map to output pointer memory!!! ++ // ++ for(i=0; i<_size_byte; i++) ++ { ++ pbuf[i] = efuseTbl[_offset+i]; ++ } ++ ++ // ++ // 5. Calculate Efuse utilization. ++ // ++ efuse_usage = (u8)((efuse_utilized*100)/EFUSE_REAL_CONTENT_LEN); ++ Adapter->HalFunc.SetHwRegHandler(Adapter, HW_VAR_EFUSE_BYTES, (u8 *)&efuse_utilized); ++ //Adapter->HalFunc.SetHwRegHandler(Adapter, HW_VAR_EFUSE_USAGE, (pu1Byte)&efuse_usage); ++} ++ ++static VOID ++ReadEFuse_RTL8723( ++ PADAPTER Adapter, ++ u16 _offset, ++ u16 _size_byte, ++ u8 *pbuf, ++ IN BOOLEAN bPseudoTest ++ ) ++{ ++ u8 efuseTbl[EFUSE_MAP_LEN_8723]; ++ u16 eFuse_Addr = 0; ++ u8 offset = 0, wden = 0; ++ u16 i, j; ++ u16 eFuseWord[EFUSE_MAX_SECTION_8723][EFUSE_MAX_WORD_UNIT]; ++ u16 efuse_utilized = 0; ++ u8 efuse_usage = 0; ++ u8 offset_2_0=0; ++ u8 efuseHeader=0, efuseExtHdr=0, efuseData=0; ++ // ++ // Do NOT excess total size of EFuse table. Added by Roger, 2008.11.10. ++ // ++ if((_offset + _size_byte)>EFUSE_MAP_LEN_8723) ++ { ++ //RT_TRACE(COMP_EFUSE, DBG_LOUD, ("ReadEFuse_RTL8723(): Invalid offset(%#x) with read bytes(%#x)!!\n",_offset, _size_byte)); ++ return; ++ } ++ ++ // 0. Refresh efuse init map as all oxFF. ++ for (i = 0; i < EFUSE_MAX_SECTION_8723; i++) ++ for (j = 0; j < EFUSE_MAX_WORD_UNIT; j++) ++ eFuseWord[i][j] = 0xFFFF; ++ ++ // ++ // 1. Read the first byte to check if efuse is empty!!! ++ // ++ // ++ ReadEFuseByte(Adapter, eFuse_Addr++, &efuseHeader, bPseudoTest); ++ ++ if(efuseHeader != 0xFF) ++ { ++ efuse_utilized++; ++ } ++ else ++ { ++ //RTPRINT(FEEPROM, EFUSE_READ_ALL, ("EFUSE is empty\n")); ++ return; ++ } ++ ++ ++ // ++ // 2. Read real efuse content. Filter PG header and every section data. ++ // ++ while((efuseHeader != 0xFF) && AVAILABLE_EFUSE_ADDR(eFuse_Addr)) ++ { ++ //RTPRINT(FEEPROM, EFUSE_READ_ALL, ("efuse[%d]=%x\n", eFuse_Addr-1, efuseHeader)); ++ ++ // Check PG header for section num. ++ if(EXT_HEADER(efuseHeader)) //extended header ++ { ++ offset_2_0 = GET_HDR_OFFSET_2_0(efuseHeader); ++ //RTPRINT(FEEPROM, EFUSE_READ_ALL, ("extended header offset_2_0=%x\n", offset_2_0)); ++ ++ ReadEFuseByte(Adapter, eFuse_Addr++, &efuseExtHdr, bPseudoTest); ++ ++ //RTPRINT(FEEPROM, EFUSE_READ_ALL, ("efuse[%d]=%x\n", eFuse_Addr-1, efuseExtHdr)); ++ ++ if(efuseExtHdr != 0xff) ++ { ++ efuse_utilized++; ++ if(ALL_WORDS_DISABLED(efuseExtHdr)) ++ { ++ ReadEFuseByte(Adapter, eFuse_Addr++, &efuseHeader, bPseudoTest); ++ if(efuseHeader != 0xff) ++ { ++ efuse_utilized++; ++ } ++ continue; ++ } ++ else ++ { ++ offset = ((efuseExtHdr & 0xF0) >> 1) | offset_2_0; ++ wden = (efuseExtHdr & 0x0F); ++ } ++ } ++ else ++ { ++ //RTPRINT(FEEPROM, EFUSE_READ_ALL, ("Error condition, extended = 0xff\n")); ++ // We should handle this condition. ++ } ++ } ++ else ++ { ++ offset = ((efuseHeader >> 4) & 0x0f); ++ wden = (efuseHeader & 0x0f); ++ } ++ ++ if(offset < EFUSE_MAX_SECTION_8723) ++ { ++ // Get word enable value from PG header ++ //RTPRINT(FEEPROM, EFUSE_READ_ALL, ("Offset-%d Worden=%x\n", offset, wden)); ++ ++ for(i=0; i> 8) & 0xff); ++ } ++ } ++ ++ // ++ // 4. Copy from Efuse map to output pointer memory!!! ++ // ++ for(i=0; i<_size_byte; i++) ++ { ++ pbuf[i] = efuseTbl[_offset+i]; ++ } ++ ++ // ++ // 5. Calculate Efuse utilization. ++ // ++ efuse_usage = (u8)((efuse_utilized*100)/EFUSE_REAL_CONTENT_LEN); ++ Adapter->HalFunc.SetHwRegHandler(Adapter, HW_VAR_EFUSE_BYTES, (u8 *)&efuse_utilized); ++ //Adapter->HalFunc.SetHwRegHandler(Adapter, HW_VAR_EFUSE_USAGE, (pu1Byte)&efuse_usage); ++} ++ ++static BOOLEAN ++Hal_EfuseSwitchToBank( ++ IN PADAPTER pAdapter, ++ IN u8 bank, ++ IN BOOLEAN bPseudoTest ++ ) ++{ ++ BOOLEAN bRet = _FALSE; ++ u32 value32=0; ++ ++ //RTPRINT(FEEPROM, EFUSE_PG, ("Efuse switch bank to %d\n", bank)); ++ if(bPseudoTest) ++ { ++ fakeEfuseBank = bank; ++ bRet = _TRUE; ++ } ++ else ++ { ++ if(IS_HARDWARE_TYPE_8723(pAdapter) && ++ INCLUDE_MULTI_FUNC_BT(pAdapter)) ++ { ++ value32 = rtw_read32(pAdapter, EFUSE_TEST); ++ bRet = _TRUE; ++ switch(bank) ++ { ++ case 0: ++ value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_WIFI_SEL_0); ++ break; ++ case 1: ++ value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_BT_SEL_0); ++ break; ++ case 2: ++ value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_BT_SEL_1); ++ break; ++ case 3: ++ value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_BT_SEL_2); ++ break; ++ default: ++ value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_WIFI_SEL_0); ++ bRet = _FALSE; ++ break; ++ } ++ rtw_write32(pAdapter, EFUSE_TEST, value32); ++ } ++ else ++ bRet = _TRUE; ++ } ++ return bRet; ++} ++ ++static VOID ++ReadEFuse_BT( ++ PADAPTER Adapter, ++ u16 _offset, ++ u16 _size_byte, ++ u8 *pbuf, ++ IN BOOLEAN bPseudoTest ++ ) ++{ ++ u8 *efuseTbl; ++ u16 eFuse_Addr = 0; ++ u8 offset = 0, wden = 0; ++ u16 i, j; ++ u16 **eFuseWord; ++ u16 efuse_utilized = 0; ++ u8 efuse_usage = 0; ++ u8 offset_2_0=0; ++ u8 efuseHeader=0, efuseExtHdr=0, efuseData=0; ++ u8 bank=0; ++ BOOLEAN bCheckNextBank=_FALSE; ++ ++ efuseTbl = rtw_malloc(EFUSE_BT_MAP_LEN); ++ if(efuseTbl == NULL){ ++ DBG_8192C("efuseTbl malloc fail !\n"); ++ return; ++ } ++ ++ eFuseWord = (u16 **)rtw_zmalloc(sizeof(u16 *)*EFUSE_BT_MAX_SECTION); ++ if(eFuseWord == NULL){ ++ DBG_8192C("eFuseWord malloc fail !\n"); ++ return; ++ } ++ else{ ++ for(i=0;iEFUSE_BT_MAP_LEN) ++ { ++ //RT_TRACE(COMP_EFUSE, DBG_LOUD, ("ReadEFuse_BT(): Invalid offset(%#x) with read bytes(%#x)!!\n",_offset, _size_byte)); ++ return; ++ } ++ ++ // 0. Refresh efuse init map as all oxFF. ++ for (i = 0; i < EFUSE_BT_MAX_SECTION; i++) ++ for (j = 0; j < EFUSE_MAX_WORD_UNIT; j++) ++ eFuseWord[i][j] = 0xFFFF; ++ ++ for(bank=1; bank> 1) | offset_2_0; ++ wden = (efuseExtHdr & 0x0F); ++ } ++ } ++ else ++ { ++ //RTPRINT(FEEPROM, EFUSE_READ_ALL, ("Error condition, extended = 0xff\n")); ++ // We should handle this condition. ++ } ++ } ++ else ++ { ++ offset = ((efuseHeader >> 4) & 0x0f); ++ wden = (efuseHeader & 0x0f); ++ } ++ ++ if(offset < EFUSE_BT_MAX_SECTION) ++ { ++ // Get word enable value from PG header ++ //RTPRINT(FEEPROM, EFUSE_READ_ALL, ("Offset-%d Worden=%x\n", offset, wden)); ++ ++ for(i=0; i= EFUSE_REAL_CONTENT_LEN) ++ bCheckNextBank = _TRUE; ++ else ++ bCheckNextBank = _FALSE; ++ } ++ } ++ if(!bCheckNextBank) ++ { ++ //RTPRINT(FEEPROM, EFUSE_READ_ALL, ("Stop to check next bank\n")); ++ break; ++ } ++ } ++ ++ // switch bank back to bank 0 for later BT and wifi use. ++ Hal_EfuseSwitchToBank(Adapter, 0, bPseudoTest); ++ ++ // ++ // 3. Collect 16 sections and 4 word unit into Efuse map. ++ // ++ for(i=0; i> 8) & 0xff); ++ } ++ } ++ ++ // ++ // 4. Copy from Efuse map to output pointer memory!!! ++ // ++ for(i=0; i<_size_byte; i++) ++ { ++ pbuf[i] = efuseTbl[_offset+i]; ++ } ++ ++ // ++ // 5. Calculate Efuse utilization. ++ // ++ efuse_usage = (u8)((efuse_utilized*100)/EFUSE_BT_REAL_CONTENT_LEN); ++ if(bPseudoTest) ++ { ++ fakeBTEfuseUsedBytes = (EFUSE_REAL_CONTENT_LEN*(bank-1))+eFuse_Addr-1; ++ } ++ else ++ { ++ BTEfuseUsedBytes = (EFUSE_REAL_CONTENT_LEN*(bank-1))+eFuse_Addr-1; ++ } ++ ++ for(i=0;i>4) & 0x0F; ++ hworden = efuse_data & 0x0F; ++ word_cnts = Efuse_CalculateWordCnts(hworden); ++ //read next header ++ efuse_addr = efuse_addr + (word_cnts*2)+1; ++ } ++ else ++ { ++ bContinual = _FALSE ; ++ } ++ } ++ ++ return efuse_addr; ++} ++ ++static u16 ++Hal_EfuseGetCurrentSize_BT(IN PADAPTER pAdapter, ++ IN BOOLEAN bPseudoTest) ++{ ++ int bContinual = _TRUE; ++ u16 efuse_addr = 0; ++ u8 hoffset=0,hworden=0; ++ u8 efuse_data,word_cnts=0; ++ u8 bank=0, startBank=0; ++ u16 retU2=0; ++ u32 total_efuse_used=0; ++ ++ if(bPseudoTest) ++ { ++ efuse_addr = (u16)((fakeBTEfuseUsedBytes%EFUSE_REAL_CONTENT_LEN)); ++ startBank = (u8)(1+(fakeBTEfuseUsedBytes/EFUSE_REAL_CONTENT_LEN)); ++ } ++ else ++ { ++ efuse_addr = (u16)((BTEfuseUsedBytes%EFUSE_REAL_CONTENT_LEN)); ++ startBank = (u8)(1+(BTEfuseUsedBytes/EFUSE_REAL_CONTENT_LEN)); ++ } ++ ++ if((startBank < 1) || (startBank >= EFUSE_MAX_BANK)) ++ DBG_8192C("Error, bank error, bank=%d\n", bank); ++ ++ //RTPRINT(FEEPROM, EFUSE_PG, ("Hal_EfuseGetCurrentSize_BT(), start bank=%d, start_efuse_addr = %d\n", startBank, efuse_addr)); ++ ++ for(bank=startBank; bank> 5) | ((efuse_data & 0xF0) >> 1); ++ hworden = efuse_data & 0x0F; ++ } ++ } ++ else ++ { ++ hoffset = (efuse_data>>4) & 0x0F; ++ hworden = efuse_data & 0x0F; ++ } ++ word_cnts = Efuse_CalculateWordCnts(hworden); ++ //read next header ++ efuse_addr = efuse_addr + (word_cnts*2)+1; ++ } ++ else ++ { ++ bContinual = _FALSE ; ++ } ++ } ++ ++ // Check if we need to check next bank efuse ++ if(efuse_addr < (EFUSE_REAL_CONTENT_LEN-EFUSE_PROTECT_BYTES_BANK)) ++ { ++ break;// don't need to check next bank. ++ } ++ } ++ ++ retU2 = ((bank-1)*EFUSE_REAL_CONTENT_LEN)+efuse_addr; ++ if(bPseudoTest) ++ { ++ fakeBTEfuseUsedBytes = retU2; ++ //RTPRINT(FEEPROM, EFUSE_PG, ("Hal_EfuseGetCurrentSize_BT(), return %d\n", fakeBTEfuseUsedBytes)); ++ } ++ else ++ { ++ BTEfuseUsedBytes = retU2; ++ //RTPRINT(FEEPROM, EFUSE_PG, ("Hal_EfuseGetCurrentSize_BT(), return %d\n", BTEfuseUsedBytes)); ++ } ++ ++ return retU2; ++} ++ ++ ++static u16 ++hal_EfuseGetCurrentSize_8723(IN PADAPTER pAdapter, ++ IN BOOLEAN bPseudoTest) ++{ ++ int bContinual = _TRUE; ++ ++ u16 efuse_addr = 0; ++ u8 hoffset=0,hworden=0; ++ u8 efuse_data,word_cnts=0; ++ ++ if(bPseudoTest) ++ { ++ efuse_addr = (u16)(fakeEfuseUsedBytes); ++ } ++ else ++ { ++ pAdapter->HalFunc.GetHwRegHandler(pAdapter, HW_VAR_EFUSE_BYTES, (u8 *)&efuse_addr); ++ } ++ //RTPRINT(FEEPROM, EFUSE_PG, ("hal_EfuseGetCurrentSize_8723(), start_efuse_addr = %d\n", efuse_addr)); ++ ++ while ( bContinual && ++ efuse_OneByteRead(pAdapter, efuse_addr ,&efuse_data, bPseudoTest) && ++ AVAILABLE_EFUSE_ADDR(efuse_addr)) ++ { ++ if(efuse_data!=0xFF) ++ { ++ if((efuse_data&0x1F) == 0x0F) //extended header ++ { ++ hoffset = efuse_data; ++ efuse_addr++; ++ efuse_OneByteRead(pAdapter, efuse_addr ,&efuse_data, bPseudoTest); ++ if((efuse_data & 0x0F) == 0x0F) ++ { ++ efuse_addr++; ++ continue; ++ } ++ else ++ { ++ hoffset = ((hoffset & 0xE0) >> 5) | ((efuse_data & 0xF0) >> 1); ++ hworden = efuse_data & 0x0F; ++ } ++ } ++ else ++ { ++ hoffset = (efuse_data>>4) & 0x0F; ++ hworden = efuse_data & 0x0F; ++ } ++ word_cnts = Efuse_CalculateWordCnts(hworden); ++ //read next header ++ efuse_addr = efuse_addr + (word_cnts*2)+1; ++ } ++ else ++ { ++ bContinual = _FALSE ; ++ } ++ } ++ ++ if(bPseudoTest) ++ { ++ fakeEfuseUsedBytes = efuse_addr; ++ //RTPRINT(FEEPROM, EFUSE_PG, ("hal_EfuseGetCurrentSize_8723(), return %d\n", fakeEfuseUsedBytes)); ++ } ++ else ++ { ++ pAdapter->HalFunc.SetHwRegHandler(pAdapter, HW_VAR_EFUSE_BYTES, (u8 *)&efuse_addr); ++ //RTPRINT(FEEPROM, EFUSE_PG, ("hal_EfuseGetCurrentSize_8723(), return %d\n", efuse_addr)); ++ } ++ ++ return efuse_addr; ++} ++ ++static u16 ++Hal_EfuseGetCurrentSize_Pseudo(IN PADAPTER pAdapter, ++ IN BOOLEAN bPseudoTest) ++{ ++ u16 ret=0; ++ ++ ret = hal_EfuseGetCurrentSize_8723(pAdapter, bPseudoTest); ++ ++ return ret; ++} ++ ++static u16 ++rtl8192c_EfuseGetCurrentSize( ++ IN PADAPTER pAdapter, ++ IN u8 efuseType, ++ IN BOOLEAN bPseudoTest) ++{ ++ u16 ret=0; ++ ++ if(efuseType == EFUSE_WIFI) ++ { ++ if(bPseudoTest) ++ { ++ ret = Hal_EfuseGetCurrentSize_Pseudo(pAdapter, bPseudoTest); ++ } ++ else ++ { ++ if(IS_HARDWARE_TYPE_8192C(pAdapter)) ++ { ++ ret = hal_EfuseGetCurrentSize_8192C(pAdapter, bPseudoTest); ++ } ++ else if(IS_HARDWARE_TYPE_8723(pAdapter)) ++ { ++ ret = hal_EfuseGetCurrentSize_8723(pAdapter, bPseudoTest); ++ } ++ } ++ } ++ else ++ { ++ ret = Hal_EfuseGetCurrentSize_BT(pAdapter, bPseudoTest); ++ } ++ ++ return ret; ++} ++ ++static int ++hal_EfusePgPacketRead_8192C( IN PADAPTER pAdapter, ++ IN u8 offset, ++ IN u8 *data, ++ IN BOOLEAN bPseudoTest) ++{ ++ u8 ReadState = PG_STATE_HEADER; ++ ++ int bContinual = _TRUE; ++ int bDataEmpty = _TRUE ; ++ ++ u8 efuse_data,word_cnts=0; ++ u16 efuse_addr = 0; ++ u8 hoffset=0,hworden=0; ++ u8 tmpidx=0; ++ u8 tmpdata[8]; ++ ++ if(data==NULL) return _FALSE; ++ if(offset>15) return _FALSE; ++ ++ ++ _rtw_memset((PVOID)data, 0xff, sizeof(u8)*PGPKT_DATA_SIZE); ++ _rtw_memset((PVOID)tmpdata, 0xff, sizeof(u8)*PGPKT_DATA_SIZE); ++ ++ // ++ // Efuse has been pre-programmed dummy 5Bytes at the end of Efuse by CP. ++ // Skip dummy parts to prevent unexpected data read from Efuse. ++ // By pass right now. 2009.02.19. ++ // ++ while(bContinual && (efuse_addr < EFUSE_REAL_CONTENT_LEN) ) ++ { ++ //------- Header Read ------------- ++ if(ReadState & PG_STATE_HEADER) ++ { ++ if(efuse_OneByteRead(pAdapter, efuse_addr ,&efuse_data, bPseudoTest)&&(efuse_data!=0xFF)){ ++ hoffset = (efuse_data>>4) & 0x0F; ++ hworden = efuse_data & 0x0F; ++ word_cnts = Efuse_CalculateWordCnts(hworden); ++ bDataEmpty = _TRUE ; ++ ++ if(hoffset==offset){ ++ for(tmpidx = 0;tmpidx< word_cnts*2 ;tmpidx++){ ++ if(efuse_OneByteRead(pAdapter, efuse_addr+1+tmpidx ,&efuse_data, bPseudoTest) ){ ++ tmpdata[tmpidx] = efuse_data; ++ if(efuse_data!=0xff){ ++ bDataEmpty = _FALSE; ++ } ++ } ++ } ++ if(bDataEmpty==_FALSE){ ++ ReadState = PG_STATE_DATA; ++ }else{//read next header ++ efuse_addr = efuse_addr + (word_cnts*2)+1; ++ ReadState = PG_STATE_HEADER; ++ } ++ } ++ else{//read next header ++ efuse_addr = efuse_addr + (word_cnts*2)+1; ++ ReadState = PG_STATE_HEADER; ++ } ++ ++ } ++ else{ ++ bContinual = _FALSE ; ++ } ++ } ++ //------- Data section Read ------------- ++ else if(ReadState & PG_STATE_DATA) ++ { ++ efuse_WordEnableDataRead(hworden,tmpdata,data); ++ efuse_addr = efuse_addr + (word_cnts*2)+1; ++ ReadState = PG_STATE_HEADER; ++ } ++ ++ } ++ ++ if( (data[0]==0xff) &&(data[1]==0xff) && (data[2]==0xff) && (data[3]==0xff) && ++ (data[4]==0xff) &&(data[5]==0xff) && (data[6]==0xff) && (data[7]==0xff)) ++ return _FALSE; ++ else ++ return _TRUE; ++ ++} ++ ++static int ++hal_EfusePgPacketRead_8723( IN PADAPTER pAdapter, ++ IN u8 offset, ++ IN u8 *data, ++ IN BOOLEAN bPseudoTest) ++{ ++ u8 ReadState = PG_STATE_HEADER; ++ ++ int bContinual = _TRUE; ++ int bDataEmpty = _TRUE ; ++ ++ u8 efuse_data,word_cnts=0; ++ u16 efuse_addr = 0; ++ u8 hoffset=0,hworden=0; ++ u8 tmpidx=0; ++ u8 tmpdata[8]; ++ u8 max_section=0; ++ u8 tmp_header = 0; ++ ++ EFUSE_GetEfuseDefinition(pAdapter, EFUSE_WIFI, TYPE_EFUSE_MAX_SECTION, (PVOID)&max_section, bPseudoTest); ++ ++ if(data==NULL) ++ return _FALSE; ++ if(offset>max_section) ++ return _FALSE; ++ ++ _rtw_memset((PVOID)data, 0xff, sizeof(u8)*PGPKT_DATA_SIZE); ++ _rtw_memset((PVOID)tmpdata, 0xff, sizeof(u8)*PGPKT_DATA_SIZE); ++ ++ ++ // ++ // Efuse has been pre-programmed dummy 5Bytes at the end of Efuse by CP. ++ // Skip dummy parts to prevent unexpected data read from Efuse. ++ // By pass right now. 2009.02.19. ++ // ++ while(bContinual && AVAILABLE_EFUSE_ADDR(efuse_addr) ) ++ { ++ //------- Header Read ------------- ++ if(ReadState & PG_STATE_HEADER) ++ { ++ if(efuse_OneByteRead(pAdapter, efuse_addr ,&efuse_data, bPseudoTest)&&(efuse_data!=0xFF)) ++ { ++ if(EXT_HEADER(efuse_data)) ++ { ++ tmp_header = efuse_data; ++ efuse_addr++; ++ efuse_OneByteRead(pAdapter, efuse_addr ,&efuse_data, bPseudoTest); ++ if(!ALL_WORDS_DISABLED(efuse_data)) ++ { ++ hoffset = ((tmp_header & 0xE0) >> 5) | ((efuse_data & 0xF0) >> 1); ++ hworden = efuse_data & 0x0F; ++ } ++ else ++ { ++ DBG_8192C("Error, All words disabled\n"); ++ efuse_addr++; ++ continue; ++ } ++ } ++ else ++ { ++ hoffset = (efuse_data>>4) & 0x0F; ++ hworden = efuse_data & 0x0F; ++ } ++ word_cnts = Efuse_CalculateWordCnts(hworden); ++ bDataEmpty = _TRUE ; ++ ++ if(hoffset==offset) ++ { ++ for(tmpidx = 0;tmpidx< word_cnts*2 ;tmpidx++) ++ { ++ if(efuse_OneByteRead(pAdapter, efuse_addr+1+tmpidx ,&efuse_data, bPseudoTest) ) ++ { ++ tmpdata[tmpidx] = efuse_data; ++ if(efuse_data!=0xff) ++ { ++ bDataEmpty = _FALSE; ++ } ++ } ++ } ++ if(bDataEmpty==_FALSE){ ++ ReadState = PG_STATE_DATA; ++ }else{//read next header ++ efuse_addr = efuse_addr + (word_cnts*2)+1; ++ ReadState = PG_STATE_HEADER; ++ } ++ } ++ else{//read next header ++ efuse_addr = efuse_addr + (word_cnts*2)+1; ++ ReadState = PG_STATE_HEADER; ++ } ++ ++ } ++ else{ ++ bContinual = _FALSE ; ++ } ++ } ++ //------- Data section Read ------------- ++ else if(ReadState & PG_STATE_DATA) ++ { ++ efuse_WordEnableDataRead(hworden,tmpdata,data); ++ efuse_addr = efuse_addr + (word_cnts*2)+1; ++ ReadState = PG_STATE_HEADER; ++ } ++ ++ } ++ ++ if( (data[0]==0xff) &&(data[1]==0xff) && (data[2]==0xff) && (data[3]==0xff) && ++ (data[4]==0xff) &&(data[5]==0xff) && (data[6]==0xff) && (data[7]==0xff)) ++ return _FALSE; ++ else ++ return _TRUE; ++ ++} ++ ++static int ++Hal_EfusePgPacketRead( IN PADAPTER pAdapter, ++ IN u8 offset, ++ IN u8 *data, ++ IN BOOLEAN bPseudoTest) ++{ ++ int ret=0; ++ ++ if(IS_HARDWARE_TYPE_8192C(pAdapter)) ++ { ++ ret = hal_EfusePgPacketRead_8192C(pAdapter, offset, data, bPseudoTest); ++ } ++ else if(IS_HARDWARE_TYPE_8723(pAdapter)) ++ { ++ ret = hal_EfusePgPacketRead_8723(pAdapter, offset, data, bPseudoTest); ++ } ++ ++ return ret; ++} ++ ++static int ++Hal_EfusePgPacketRead_Pseudo( IN PADAPTER pAdapter, ++ IN u8 offset, ++ IN u8 *data, ++ IN BOOLEAN bPseudoTest) ++{ ++ int ret=0; ++ ++ ret = hal_EfusePgPacketRead_8723(pAdapter, offset, data, bPseudoTest); ++ ++ return ret; ++} ++ ++static int ++rtl8192c_Efuse_PgPacketRead( IN PADAPTER pAdapter, ++ IN u8 offset, ++ IN u8 *data, ++ IN BOOLEAN bPseudoTest) ++{ ++ int ret=0; ++ ++ if(bPseudoTest) ++ { ++ ret = Hal_EfusePgPacketRead_Pseudo(pAdapter, offset, data, bPseudoTest); ++ } ++ else ++ { ++ ret = Hal_EfusePgPacketRead(pAdapter, offset, data, bPseudoTest); ++ } ++ ++ return ret; ++} ++ ++static BOOLEAN ++hal_EfuseFixHeaderProcess( ++ IN PADAPTER pAdapter, ++ IN u8 efuseType, ++ IN PPGPKT_STRUCT pFixPkt, ++ IN u16 *pAddr, ++ IN BOOLEAN bPseudoTest ++) ++{ ++ u8 originaldata[8], badworden=0; ++ u16 efuse_addr=*pAddr; ++ u32 PgWriteSuccess=0; ++ ++ _rtw_memset((PVOID)originaldata, 0xff, 8); ++ ++ if(Efuse_PgPacketRead(pAdapter, pFixPkt->offset, originaldata, bPseudoTest)) ++ { //check if data exist ++ badworden = Efuse_WordEnableDataWrite(pAdapter, efuse_addr+1, pFixPkt->word_en, originaldata, bPseudoTest); ++ ++ if(badworden != 0xf) // write fail ++ { ++ if(efuseType == EFUSE_WIFI) ++ PgWriteSuccess = Efuse_PgPacketWrite(pAdapter, pFixPkt->offset, badworden, originaldata, bPseudoTest); ++ else ++ PgWriteSuccess = hal_EfusePgPacketWrite_BT(pAdapter, pFixPkt->offset, badworden, originaldata, bPseudoTest); ++ if(!PgWriteSuccess) ++ return _FALSE; ++ else ++ efuse_addr = Efuse_GetCurrentSize(pAdapter, efuseType, bPseudoTest); ++ } ++ else ++ { ++ efuse_addr = efuse_addr + (pFixPkt->word_cnts*2) +1; ++ } ++ } ++ else ++ { ++ efuse_addr = efuse_addr + (pFixPkt->word_cnts*2) +1; ++ } ++ *pAddr = efuse_addr; ++ return _TRUE; ++} ++ ++static BOOLEAN ++hal_EfusePgPacketWrite2ByteHeader( ++ IN PADAPTER pAdapter, ++ IN u8 efuseType, ++ IN u16 *pAddr, ++ IN PPGPKT_STRUCT pTargetPkt, ++ IN BOOLEAN bPseudoTest) ++{ ++ BOOLEAN bRet=_FALSE, bContinual=_TRUE; ++ u16 efuse_addr=*pAddr, efuse_max_available_len=0; ++ u8 pg_header=0, tmp_header=0, pg_header_temp=0; ++ u8 repeatcnt=0; ++ ++ //RTPRINT(FEEPROM, EFUSE_PG, ("Wirte 2byte header\n")); ++ EFUSE_GetEfuseDefinition(pAdapter, efuseType, TYPE_AVAILABLE_EFUSE_BYTES_BANK, (PVOID)&efuse_max_available_len, bPseudoTest); ++ ++ while(efuse_addr < efuse_max_available_len) ++ { ++ pg_header = ((pTargetPkt->offset & 0x07) << 5) | 0x0F; ++ //RTPRINT(FEEPROM, EFUSE_PG, ("pg_header = 0x%x\n", pg_header)); ++ efuse_OneByteWrite(pAdapter, efuse_addr, pg_header, bPseudoTest); ++ efuse_OneByteRead(pAdapter, efuse_addr, &tmp_header, bPseudoTest); ++ ++ while(tmp_header == 0xFF) ++ { ++ if(repeatcnt++ > EFUSE_REPEAT_THRESHOLD_) ++ { ++ //RTPRINT(FEEPROM, EFUSE_PG, ("Repeat over limit for pg_header!!\n")); ++ return _FALSE; ++ } ++ ++ efuse_OneByteWrite(pAdapter, efuse_addr, pg_header, bPseudoTest); ++ efuse_OneByteRead(pAdapter, efuse_addr, &tmp_header, bPseudoTest); ++ } ++ ++ //to write ext_header ++ if(tmp_header == pg_header) ++ { ++ efuse_addr++; ++ pg_header_temp = pg_header; ++ pg_header = ((pTargetPkt->offset & 0x78) << 1) | pTargetPkt->word_en; ++ ++ efuse_OneByteWrite(pAdapter, efuse_addr, pg_header, bPseudoTest); ++ efuse_OneByteRead(pAdapter, efuse_addr, &tmp_header, bPseudoTest); ++ ++ while(tmp_header == 0xFF) ++ { ++ if(repeatcnt++ > EFUSE_REPEAT_THRESHOLD_) ++ { ++ //RTPRINT(FEEPROM, EFUSE_PG, ("Repeat over limit for ext_header!!\n")); ++ return _FALSE; ++ } ++ ++ efuse_OneByteWrite(pAdapter, efuse_addr, pg_header, bPseudoTest); ++ efuse_OneByteRead(pAdapter, efuse_addr, &tmp_header, bPseudoTest); ++ } ++ ++ if((tmp_header & 0x0F) == 0x0F) //word_en PG fail ++ { ++ if(repeatcnt++ > EFUSE_REPEAT_THRESHOLD_) ++ { ++ //RTPRINT(FEEPROM, EFUSE_PG, ("Repeat over limit for word_en!!\n")); ++ return _FALSE; ++ } ++ else ++ { ++ efuse_addr++; ++ continue; ++ } ++ } ++ else if(pg_header != tmp_header) //offset PG fail ++ { ++ PGPKT_STRUCT fixPkt; ++ //RTPRINT(FEEPROM, EFUSE_PG, ("Error condition for offset PG fail, need to cover the existed data\n")); ++ fixPkt.offset = ((pg_header_temp & 0xE0) >> 5) | ((tmp_header & 0xF0) >> 1); ++ fixPkt.word_en = tmp_header & 0x0F; ++ fixPkt.word_cnts = Efuse_CalculateWordCnts(fixPkt.word_en); ++ if(!hal_EfuseFixHeaderProcess(pAdapter, efuseType, &fixPkt, &efuse_addr, bPseudoTest)) ++ return _FALSE; ++ } ++ else ++ { ++ bRet = _TRUE; ++ break; ++ } ++ } ++ else if ((tmp_header & 0x1F) == 0x0F) //wrong extended header ++ { ++ efuse_addr+=2; ++ continue; ++ } ++ } ++ ++ *pAddr = efuse_addr; ++ return bRet; ++} ++ ++static BOOLEAN ++hal_EfusePgPacketWrite1ByteHeader( ++ IN PADAPTER pAdapter, ++ IN u8 efuseType, ++ IN u16 *pAddr, ++ IN PPGPKT_STRUCT pTargetPkt, ++ IN BOOLEAN bPseudoTest) ++{ ++ BOOLEAN bRet=_FALSE; ++ u8 pg_header=0, tmp_header=0; ++ u16 efuse_addr=*pAddr; ++ u8 repeatcnt=0; ++ ++ //RTPRINT(FEEPROM, EFUSE_PG, ("Wirte 1byte header\n")); ++ pg_header = ((pTargetPkt->offset << 4) & 0xf0) |pTargetPkt->word_en; ++ ++ efuse_OneByteWrite(pAdapter, efuse_addr, pg_header, bPseudoTest); ++ efuse_OneByteRead(pAdapter, efuse_addr, &tmp_header, bPseudoTest); ++ ++ while(tmp_header == 0xFF) ++ { ++ if(repeatcnt++ > EFUSE_REPEAT_THRESHOLD_) ++ { ++ return _FALSE; ++ } ++ efuse_OneByteWrite(pAdapter,efuse_addr, pg_header, bPseudoTest); ++ efuse_OneByteRead(pAdapter,efuse_addr, &tmp_header, bPseudoTest); ++ } ++ ++ if(pg_header == tmp_header) ++ { ++ bRet = _TRUE; ++ } ++ else ++ { ++ PGPKT_STRUCT fixPkt; ++ //RTPRINT(FEEPROM, EFUSE_PG, ("Error condition for fixed PG packet, need to cover the existed data\n")); ++ fixPkt.offset = (tmp_header>>4) & 0x0F; ++ fixPkt.word_en = tmp_header & 0x0F; ++ fixPkt.word_cnts = Efuse_CalculateWordCnts(fixPkt.word_en); ++ if(!hal_EfuseFixHeaderProcess(pAdapter, efuseType, &fixPkt, &efuse_addr, bPseudoTest)) ++ return _FALSE; ++ } ++ ++ *pAddr = efuse_addr; ++ return bRet; ++} ++ ++static BOOLEAN ++hal_EfusePgPacketWriteData( ++ IN PADAPTER pAdapter, ++ IN u8 efuseType, ++ IN u16 *pAddr, ++ IN PPGPKT_STRUCT pTargetPkt, ++ IN BOOLEAN bPseudoTest) ++{ ++ BOOLEAN bRet=_FALSE; ++ u16 efuse_addr=*pAddr; ++ u8 badworden=0; ++ u32 PgWriteSuccess=0; ++ ++ badworden = 0x0f; ++ badworden = Efuse_WordEnableDataWrite(pAdapter, efuse_addr+1, pTargetPkt->word_en, pTargetPkt->data, bPseudoTest); ++ if(badworden == 0x0F) ++ { ++ // write ok ++ //RTPRINT(FEEPROM, EFUSE_PG, ("hal_EfusePgPacketWriteData ok!!\n")); ++ return _TRUE; ++ } ++ else ++ { ++ //RTPRINT(FEEPROM, EFUSE_PG, ("hal_EfusePgPacketWriteData Fail!!\n")); ++ //reorganize other pg packet ++ if(efuseType == EFUSE_WIFI) ++ PgWriteSuccess = Efuse_PgPacketWrite(pAdapter, pTargetPkt->offset, badworden, pTargetPkt->data, bPseudoTest); ++ else ++ PgWriteSuccess = hal_EfusePgPacketWrite_BT(pAdapter, pTargetPkt->offset, badworden, pTargetPkt->data, bPseudoTest); ++ if(!PgWriteSuccess) ++ return _FALSE; ++ else ++ return _TRUE; ++ } ++ ++ return bRet; ++} ++ ++static BOOLEAN ++hal_EfusePgPacketWriteHeader( ++ IN PADAPTER pAdapter, ++ IN u8 efuseType, ++ IN u16 *pAddr, ++ IN PPGPKT_STRUCT pTargetPkt, ++ IN BOOLEAN bPseudoTest) ++{ ++ BOOLEAN bRet=_FALSE; ++ ++ if(pTargetPkt->offset >= EFUSE_MAX_SECTION_BASE) ++ { ++ bRet = hal_EfusePgPacketWrite2ByteHeader(pAdapter, efuseType, pAddr, pTargetPkt, bPseudoTest); ++ } ++ else ++ { ++ bRet = hal_EfusePgPacketWrite1ByteHeader(pAdapter, efuseType, pAddr, pTargetPkt, bPseudoTest); ++ } ++ ++ return bRet; ++} ++ ++static BOOLEAN ++hal_EfusePgCheckAvailableAddr( ++ IN PADAPTER pAdapter, ++ IN u8 efuseType, ++ IN BOOLEAN bPseudoTest ++ ) ++{ ++ u16 efuse_max_available_len=0; ++ ++ EFUSE_GetEfuseDefinition(pAdapter, efuseType, TYPE_AVAILABLE_EFUSE_BYTES_TOTAL, (PVOID)&efuse_max_available_len, bPseudoTest); ++ //RTPRINT(FEEPROM, EFUSE_PG, ("efuse_max_available_len = %d\n", efuse_max_available_len)); ++ ++ if(Efuse_GetCurrentSize(pAdapter, efuseType, bPseudoTest) >= efuse_max_available_len) ++ { ++ //RTPRINT(FEEPROM, EFUSE_PG, ("hal_EfusePgCheckAvailableAddr error!!\n")); ++ return _FALSE; ++ } ++ return _TRUE; ++} ++ ++static VOID ++hal_EfuseConstructPGPkt( ++ IN u8 offset, ++ IN u8 word_en, ++ IN u8 *pData, ++ IN PPGPKT_STRUCT pTargetPkt ++ ++) ++{ ++ _rtw_memset((PVOID)pTargetPkt->data, 0xFF, sizeof(u8)*8); ++ pTargetPkt->offset = offset; ++ pTargetPkt->word_en= word_en; ++ efuse_WordEnableDataRead(word_en, pData, pTargetPkt->data); ++ pTargetPkt->word_cnts = Efuse_CalculateWordCnts(pTargetPkt->word_en); ++ ++ //RTPRINT(FEEPROM, EFUSE_PG, ("hal_EfuseConstructPGPkt(), targetPkt, offset=%d, word_en=0x%x, word_cnts=%d\n", pTargetPkt->offset, pTargetPkt->word_en, pTargetPkt->word_cnts)); ++} ++ ++static BOOLEAN ++hal_EfuseCheckIfDatafollowed( ++ IN PADAPTER pAdapter, ++ IN u8 word_cnts, ++ IN u16 startAddr, ++ IN BOOLEAN bPseudoTest ++ ) ++{ ++ BOOLEAN bRet=_FALSE; ++ u8 i, efuse_data; ++ ++ for(i=0; i<(word_cnts*2) ; i++) ++ { ++ if(efuse_OneByteRead(pAdapter, (startAddr+i) ,&efuse_data, bPseudoTest)&&(efuse_data != 0xFF)) ++ bRet = _TRUE; ++ } ++ ++ return bRet; ++} ++ ++static BOOLEAN ++wordEnMatched( ++ IN PPGPKT_STRUCT pTargetPkt, ++ IN PPGPKT_STRUCT pCurPkt, ++ IN u8 *pWden ++) ++{ ++ u8 match_word_en = 0x0F; // default all words are disabled ++ u8 i; ++ ++ // check if the same words are enabled both target and current PG packet ++ if( ((pTargetPkt->word_en & BIT0) == 0) && ++ ((pCurPkt->word_en & BIT0) == 0) ) ++ { ++ match_word_en &= ~BIT0; // enable word 0 ++ } ++ if( ((pTargetPkt->word_en & BIT1) == 0) && ++ ((pCurPkt->word_en & BIT1) == 0) ) ++ { ++ match_word_en &= ~BIT1; // enable word 1 ++ } ++ if( ((pTargetPkt->word_en & BIT2) == 0) && ++ ((pCurPkt->word_en & BIT2) == 0) ) ++ { ++ match_word_en &= ~BIT2; // enable word 2 ++ } ++ if( ((pTargetPkt->word_en & BIT3) == 0) && ++ ((pCurPkt->word_en & BIT3) == 0) ) ++ { ++ match_word_en &= ~BIT3; // enable word 3 ++ } ++ ++ *pWden = match_word_en; ++ ++ if(match_word_en != 0xf) ++ return _TRUE; ++ else ++ return _FALSE; ++} ++ ++static BOOLEAN ++hal_EfusePartialWriteCheck( ++ IN PADAPTER pAdapter, ++ IN u8 efuseType, ++ IN u16 *pAddr, ++ IN PPGPKT_STRUCT pTargetPkt, ++ IN BOOLEAN bPseudoTest ++ ) ++{ ++ BOOLEAN bRet=_FALSE; ++ u8 i, efuse_data=0, cur_header=0; ++ u8 new_wden=0, matched_wden=0, badworden=0; ++ u16 startAddr=0, efuse_max_available_len=0, efuse_max=0; ++ PGPKT_STRUCT curPkt; ++ ++ EFUSE_GetEfuseDefinition(pAdapter, efuseType, TYPE_AVAILABLE_EFUSE_BYTES_BANK, (PVOID)&efuse_max_available_len, bPseudoTest); ++ EFUSE_GetEfuseDefinition(pAdapter, efuseType, TYPE_EFUSE_REAL_CONTENT_LEN, (PVOID)&efuse_max, bPseudoTest); ++ ++ if(efuseType == EFUSE_WIFI) ++ { ++ if(bPseudoTest) ++ { ++ startAddr = (u16)(fakeEfuseUsedBytes%EFUSE_REAL_CONTENT_LEN); ++ } ++ else ++ { ++ pAdapter->HalFunc.GetHwRegHandler(pAdapter, HW_VAR_EFUSE_BYTES, (u8 *)&startAddr); ++ startAddr%=EFUSE_REAL_CONTENT_LEN; ++ } ++ } ++ else ++ { ++ if(bPseudoTest) ++ { ++ startAddr = (u16)(fakeBTEfuseUsedBytes%EFUSE_REAL_CONTENT_LEN); ++ } ++ else ++ { ++ startAddr = (u16)(BTEfuseUsedBytes%EFUSE_REAL_CONTENT_LEN); ++ } ++ } ++ //RTPRINT(FEEPROM, EFUSE_PG, ("hal_EfusePartialWriteCheck(), startAddr=%d\n", startAddr)); ++ ++ while(1) ++ { ++ if(startAddr >= efuse_max_available_len) ++ { ++ bRet = _FALSE; ++ break; ++ } ++ ++ if(efuse_OneByteRead(pAdapter, startAddr, &efuse_data, bPseudoTest) && (efuse_data!=0xFF)) ++ { ++ if(EXT_HEADER(efuse_data)) ++ { ++ cur_header = efuse_data; ++ startAddr++; ++ efuse_OneByteRead(pAdapter, startAddr, &efuse_data, bPseudoTest); ++ if(ALL_WORDS_DISABLED(efuse_data)) ++ { ++ //RTPRINT(FEEPROM, EFUSE_PG, ("Error condition, all words disabled")); ++ bRet = _FALSE; ++ break; ++ } ++ else ++ { ++ curPkt.offset = ((cur_header & 0xE0) >> 5) | ((efuse_data & 0xF0) >> 1); ++ curPkt.word_en = efuse_data & 0x0F; ++ } ++ } ++ else ++ { ++ cur_header = efuse_data; ++ curPkt.offset = (cur_header>>4) & 0x0F; ++ curPkt.word_en = cur_header & 0x0F; ++ } ++ ++ curPkt.word_cnts = Efuse_CalculateWordCnts(curPkt.word_en); ++ // if same header is found but no data followed ++ // write some part of data followed by the header. ++ if( (curPkt.offset == pTargetPkt->offset) && ++ (!hal_EfuseCheckIfDatafollowed(pAdapter, curPkt.word_cnts, startAddr+1, bPseudoTest)) && ++ wordEnMatched(pTargetPkt, &curPkt, &matched_wden) ) ++ { ++ //RTPRINT(FEEPROM, EFUSE_PG, ("Need to partial write data by the previous wrote header\n")); ++ // Here to write partial data ++ badworden = Efuse_WordEnableDataWrite(pAdapter, startAddr+1, matched_wden, pTargetPkt->data, bPseudoTest); ++ if(badworden != 0x0F) ++ { ++ u32 PgWriteSuccess=0; ++ // if write fail on some words, write these bad words again ++ if(efuseType == EFUSE_WIFI) ++ PgWriteSuccess = Efuse_PgPacketWrite(pAdapter, pTargetPkt->offset, badworden, pTargetPkt->data, bPseudoTest); ++ else ++ PgWriteSuccess = hal_EfusePgPacketWrite_BT(pAdapter, pTargetPkt->offset, badworden, pTargetPkt->data, bPseudoTest); ++ ++ if(!PgWriteSuccess) ++ { ++ bRet = _FALSE; // write fail, return ++ break; ++ } ++ } ++ // partial write ok, update the target packet for later use ++ for(i=0; i<4; i++) ++ { ++ if((matched_wden & (0x1<word_en |= (0x1<word_cnts = Efuse_CalculateWordCnts(pTargetPkt->word_en); ++ } ++ // read from next header ++ startAddr = startAddr + (curPkt.word_cnts*2) +1; ++ } ++ else ++ { ++ // not used header, 0xff ++ *pAddr = startAddr; ++ //RTPRINT(FEEPROM, EFUSE_PG, ("Started from unused header offset=%d\n", startAddr)); ++ bRet = _TRUE; ++ break; ++ } ++ } ++ return bRet; ++} ++ ++static BOOLEAN ++hal_EfusePgPacketWrite_BT( ++ IN PADAPTER pAdapter, ++ IN u8 offset, ++ IN u8 word_en, ++ IN u8 *pData, ++ IN BOOLEAN bPseudoTest ++ ) ++{ ++ PGPKT_STRUCT targetPkt; ++ u16 startAddr=0; ++ u8 efuseType=EFUSE_BT; ++ ++ if(!hal_EfusePgCheckAvailableAddr(pAdapter, efuseType, bPseudoTest)) ++ return _FALSE; ++ ++ hal_EfuseConstructPGPkt(offset, word_en, pData, &targetPkt); ++ ++ if(!hal_EfusePartialWriteCheck(pAdapter, efuseType, &startAddr, &targetPkt, bPseudoTest)) ++ return _FALSE; ++ ++ if(!hal_EfusePgPacketWriteHeader(pAdapter, efuseType, &startAddr, &targetPkt, bPseudoTest)) ++ return _FALSE; ++ ++ if(!hal_EfusePgPacketWriteData(pAdapter, efuseType, &startAddr, &targetPkt, bPseudoTest)) ++ return _FALSE; ++ ++ return _TRUE; ++} ++ ++static BOOLEAN ++hal_EfusePgPacketWrite_8723( ++ IN PADAPTER pAdapter, ++ IN u8 offset, ++ IN u8 word_en, ++ IN u8 *pData, ++ IN BOOLEAN bPseudoTest ++ ) ++{ ++ PGPKT_STRUCT targetPkt; ++ u16 startAddr=0; ++ u8 efuseType=EFUSE_WIFI; ++ ++ if(!hal_EfusePgCheckAvailableAddr(pAdapter, efuseType, bPseudoTest)) ++ return _FALSE; ++ ++ hal_EfuseConstructPGPkt(offset, word_en, pData, &targetPkt); ++ ++ if(!hal_EfusePartialWriteCheck(pAdapter, efuseType, &startAddr, &targetPkt, bPseudoTest)) ++ return _FALSE; ++ ++ if(!hal_EfusePgPacketWriteHeader(pAdapter, efuseType, &startAddr, &targetPkt, bPseudoTest)) ++ return _FALSE; ++ ++ if(!hal_EfusePgPacketWriteData(pAdapter, efuseType, &startAddr, &targetPkt, bPseudoTest)) ++ return _FALSE; ++ ++ return _TRUE; ++} ++ ++static int ++hal_EfusePgPacketWrite_8192C(IN PADAPTER pAdapter, ++ IN u8 offset, ++ IN u8 word_en, ++ IN u8 *data, ++ IN BOOLEAN bPseudoTest) ++{ ++ u8 WriteState = PG_STATE_HEADER; ++ ++ int bContinual = _TRUE,bDataEmpty=_TRUE, bResult = _TRUE; ++ u16 efuse_addr = 0; ++ u8 efuse_data; ++ ++ u8 pg_header = 0; ++ ++ u8 tmp_word_cnts=0,target_word_cnts=0; ++ u8 tmp_header,match_word_en,tmp_word_en; ++ ++ PGPKT_STRUCT target_pkt; ++ PGPKT_STRUCT tmp_pkt; ++ ++ u8 originaldata[sizeof(u8)*8]; ++ u8 tmpindex = 0,badworden = 0x0F; ++ ++ static int repeat_times = 0; ++ u8 efuseType=EFUSE_WIFI; ++ ++ // ++ // Efuse has been pre-programmed dummy 5Bytes at the end of Efuse by CP. ++ // So we have to prevent unexpected data string connection, which will cause ++ // incorrect data auto-load from HW. The total size is equal or smaller than 498bytes ++ // (i.e., offset 0~497, and dummy 1bytes) expected after CP test. ++ // 2009.02.19. ++ // ++ if( Efuse_GetCurrentSize(pAdapter, efuseType, bPseudoTest) >= (EFUSE_REAL_CONTENT_LEN-EFUSE_OOB_PROTECT_BYTES)) ++ { ++ //RTPRINT(FEEPROM, EFUSE_PG, ("hal_EfusePgPacketWrite_8192C(), over size\n")); ++ return _FALSE; ++ } ++ ++ // Init the 8 bytes content as 0xff ++ target_pkt.offset = offset; ++ target_pkt.word_en= word_en; ++ ++ _rtw_memset((PVOID)target_pkt.data, 0xFF, sizeof(u8)*8); ++ ++ efuse_WordEnableDataRead(word_en,data,target_pkt.data); ++ target_word_cnts = Efuse_CalculateWordCnts(target_pkt.word_en); ++ ++ //efuse_reg_ctrl(pAdapter,_TRUE);//power on ++ //RTPRINT(FEEPROM, EFUSE_PG, ("EFUSE Power ON\n")); ++ ++ // ++ // Efuse has been pre-programmed dummy 5Bytes at the end of Efuse by CP. ++ // So we have to prevent unexpected data string connection, which will cause ++ // incorrect data auto-load from HW. Dummy 1bytes is additional. ++ // 2009.02.19. ++ // ++ while( bContinual && (efuse_addr < (EFUSE_REAL_CONTENT_LEN-EFUSE_OOB_PROTECT_BYTES)) ) ++ { ++ ++ if(WriteState==PG_STATE_HEADER) ++ { ++ bDataEmpty=_TRUE; ++ badworden = 0x0F; ++ //************ so ******************* ++ //RTPRINT(FEEPROM, EFUSE_PG, ("EFUSE PG_STATE_HEADER\n")); ++ if ( efuse_OneByteRead(pAdapter, efuse_addr ,&efuse_data, bPseudoTest) && ++ (efuse_data!=0xFF)) ++ { ++ tmp_header = efuse_data; ++ ++ tmp_pkt.offset = (tmp_header>>4) & 0x0F; ++ tmp_pkt.word_en = tmp_header & 0x0F; ++ tmp_word_cnts = Efuse_CalculateWordCnts(tmp_pkt.word_en); ++ ++ //************ so-1 ******************* ++ if(tmp_pkt.offset != target_pkt.offset) ++ { ++ efuse_addr = efuse_addr + (tmp_word_cnts*2) +1; //Next pg_packet ++ #if (EFUSE_ERROE_HANDLE == 1) ++ WriteState = PG_STATE_HEADER; ++ #endif ++ } ++ else ++ { ++ //************ so-2 ******************* ++ for(tmpindex=0 ; tmpindex<(tmp_word_cnts*2) ; tmpindex++) ++ { ++ if(efuse_OneByteRead(pAdapter, (efuse_addr+1+tmpindex) ,&efuse_data, bPseudoTest)&&(efuse_data != 0xFF)){ ++ bDataEmpty = _FALSE; ++ } ++ } ++ //************ so-2-1 ******************* ++ if(bDataEmpty == _FALSE) ++ { ++ efuse_addr = efuse_addr + (tmp_word_cnts*2) +1; //Next pg_packet ++ #if (EFUSE_ERROE_HANDLE == 1) ++ WriteState=PG_STATE_HEADER; ++ #endif ++ } ++ else ++ {//************ so-2-2 ******************* ++ match_word_en = 0x0F; ++ if( !( (target_pkt.word_en&BIT0)|(tmp_pkt.word_en&BIT0) )) ++ { ++ match_word_en &= (~BIT0); ++ } ++ if( !( (target_pkt.word_en&BIT1)|(tmp_pkt.word_en&BIT1) )) ++ { ++ match_word_en &= (~BIT1); ++ } ++ if( !( (target_pkt.word_en&BIT2)|(tmp_pkt.word_en&BIT2) )) ++ { ++ match_word_en &= (~BIT2); ++ } ++ if( !( (target_pkt.word_en&BIT3)|(tmp_pkt.word_en&BIT3) )) ++ { ++ match_word_en &= (~BIT3); ++ } ++ ++ //************ so-2-2-A ******************* ++ if((match_word_en&0x0F)!=0x0F) ++ { ++ badworden = Efuse_WordEnableDataWrite(pAdapter,efuse_addr+1, tmp_pkt.word_en ,target_pkt.data, bPseudoTest); ++ ++ //************ so-2-2-A-1 ******************* ++ //############################ ++ if(0x0F != (badworden&0x0F)) ++ { ++ u8 reorg_offset = offset; ++ u8 reorg_worden=badworden; ++ Efuse_PgPacketWrite(pAdapter,reorg_offset,reorg_worden,originaldata, bPseudoTest); ++ } ++ //############################ ++ ++ tmp_word_en = 0x0F; ++ if( (target_pkt.word_en&BIT0)^(match_word_en&BIT0) ) ++ { ++ tmp_word_en &= (~BIT0); ++ } ++ if( (target_pkt.word_en&BIT1)^(match_word_en&BIT1) ) ++ { ++ tmp_word_en &= (~BIT1); ++ } ++ if( (target_pkt.word_en&BIT2)^(match_word_en&BIT2) ) ++ { ++ tmp_word_en &= (~BIT2); ++ } ++ if( (target_pkt.word_en&BIT3)^(match_word_en&BIT3) ) ++ { ++ tmp_word_en &=(~BIT3); ++ } ++ ++ //************ so-2-2-A-2 ******************* ++ if((tmp_word_en&0x0F)!=0x0F){ ++ //reorganize other pg packet ++ //efuse_addr = efuse_addr + (2*tmp_word_cnts) +1;//next pg packet addr ++ efuse_addr = Efuse_GetCurrentSize(pAdapter, efuseType, bPseudoTest); ++ //=========================== ++ target_pkt.offset = offset; ++ target_pkt.word_en= tmp_word_en; ++ //=========================== ++ }else{ ++ bContinual = _FALSE; ++ } ++ #if (EFUSE_ERROE_HANDLE == 1) ++ WriteState=PG_STATE_HEADER; ++ repeat_times++; ++ if(repeat_times>EFUSE_REPEAT_THRESHOLD_){ ++ bContinual = _FALSE; ++ bResult = _FALSE; ++ } ++ #endif ++ } ++ else{//************ so-2-2-B ******************* ++ //reorganize other pg packet ++ efuse_addr = efuse_addr + (2*tmp_word_cnts) +1;//next pg packet addr ++ //=========================== ++ target_pkt.offset = offset; ++ target_pkt.word_en= target_pkt.word_en; ++ //=========================== ++ #if (EFUSE_ERROE_HANDLE == 1) ++ WriteState=PG_STATE_HEADER; ++ #endif ++ } ++ } ++ } ++ //RTPRINT(FEEPROM, EFUSE_PG, ("EFUSE PG_STATE_HEADER-1\n")); ++ } ++ else //************ s1: header == oxff ******************* ++ { ++ pg_header = ((target_pkt.offset << 4)&0xf0) |target_pkt.word_en; ++ ++ efuse_OneByteWrite(pAdapter,efuse_addr, pg_header, bPseudoTest); ++ efuse_OneByteRead(pAdapter,efuse_addr, &tmp_header, bPseudoTest); ++ ++ if(tmp_header == pg_header) ++ { //************ s1-1******************* ++ WriteState = PG_STATE_DATA; ++ } ++ #if (EFUSE_ERROE_HANDLE == 1) ++ else if(tmp_header == 0xFF){//************ s1-3: if Write or read func doesn't work ******************* ++ //efuse_addr doesn't change ++ WriteState = PG_STATE_HEADER; ++ repeat_times++; ++ if(repeat_times>EFUSE_REPEAT_THRESHOLD_){ ++ bContinual = _FALSE; ++ bResult = _FALSE; ++ } ++ } ++ #endif ++ else ++ {//************ s1-2 : fixed the header procedure ******************* ++ tmp_pkt.offset = (tmp_header>>4) & 0x0F; ++ tmp_pkt.word_en= tmp_header & 0x0F; ++ tmp_word_cnts = Efuse_CalculateWordCnts(tmp_pkt.word_en); ++ ++ //************ s1-2-A :cover the exist data ******************* ++ //memset(originaldata,0xff,sizeof(UINT8)*8); ++ _rtw_memset((PVOID)originaldata, 0xff, sizeof(u8)*8); ++ ++ if(Efuse_PgPacketRead( pAdapter, tmp_pkt.offset,originaldata, bPseudoTest)) ++ { //check if data exist ++ //efuse_reg_ctrl(pAdapter,_TRUE);//power on ++ badworden = Efuse_WordEnableDataWrite(pAdapter,efuse_addr+1,tmp_pkt.word_en,originaldata, bPseudoTest); ++ //############################ ++ if(0x0F != (badworden&0x0F)) ++ { ++ u8 reorg_offset = tmp_pkt.offset; ++ u8 reorg_worden=badworden; ++ Efuse_PgPacketWrite(pAdapter,reorg_offset,reorg_worden,originaldata, bPseudoTest); ++ efuse_addr = Efuse_GetCurrentSize(pAdapter, efuseType, bPseudoTest); ++ } ++ //############################ ++ else{ ++ efuse_addr = efuse_addr + (tmp_word_cnts*2) +1; //Next pg_packet ++ } ++ } ++ //************ s1-2-B: wrong address******************* ++ else ++ { ++ efuse_addr = efuse_addr + (tmp_word_cnts*2) +1; //Next pg_packet ++ } ++ ++ #if (EFUSE_ERROE_HANDLE == 1) ++ WriteState=PG_STATE_HEADER; ++ repeat_times++; ++ if(repeat_times>EFUSE_REPEAT_THRESHOLD_){ ++ bContinual = _FALSE; ++ bResult = _FALSE; ++ } ++ #endif ++ ++ //RTPRINT(FEEPROM, EFUSE_PG, ("EFUSE PG_STATE_HEADER-2\n")); ++ } ++ ++ } ++ ++ } ++ //write data state ++ else if(WriteState==PG_STATE_DATA) ++ { //************ s1-1 ******************* ++ //RTPRINT(FEEPROM, EFUSE_PG, ("EFUSE PG_STATE_DATA\n")); ++ badworden = 0x0f; ++ badworden = Efuse_WordEnableDataWrite(pAdapter,efuse_addr+1,target_pkt.word_en,target_pkt.data, bPseudoTest); ++ if((badworden&0x0F)==0x0F) ++ { //************ s1-1-A ******************* ++ bContinual = _FALSE; ++ } ++ else ++ {//reorganize other pg packet //************ s1-1-B ******************* ++ efuse_addr = efuse_addr + (2*target_word_cnts) +1;//next pg packet addr ++ ++ //=========================== ++ target_pkt.offset = offset; ++ target_pkt.word_en= badworden; ++ target_word_cnts = Efuse_CalculateWordCnts(target_pkt.word_en); ++ //=========================== ++ #if (EFUSE_ERROE_HANDLE == 1) ++ WriteState=PG_STATE_HEADER; ++ repeat_times++; ++ if(repeat_times>EFUSE_REPEAT_THRESHOLD_){ ++ bContinual = _FALSE; ++ bResult = _FALSE; ++ } ++ #endif ++ //RTPRINT(FEEPROM, EFUSE_PG, ("EFUSE PG_STATE_HEADER-3\n")); ++ } ++ } ++ } ++ ++ if(efuse_addr >= (EFUSE_REAL_CONTENT_LEN-EFUSE_OOB_PROTECT_BYTES)) ++ { ++ //RT_TRACE(COMP_EFUSE, DBG_LOUD, ("hal_EfusePgPacketWrite_8192C(): efuse_addr(%#x) Out of size!!\n", efuse_addr)); ++ } ++ //efuse_reg_ctrl(pAdapter,_FALSE);//power off ++ ++ return _TRUE; ++} ++ ++static int ++Hal_EfusePgPacketWrite_Pseudo(IN PADAPTER pAdapter, ++ IN u8 offset, ++ IN u8 word_en, ++ IN u8 *data, ++ IN BOOLEAN bPseudoTest) ++{ ++ int ret; ++ ++ ret = hal_EfusePgPacketWrite_8723(pAdapter, offset, word_en, data, bPseudoTest); ++ ++ return ret; ++} ++ ++static int ++Hal_EfusePgPacketWrite(IN PADAPTER pAdapter, ++ IN u8 offset, ++ IN u8 word_en, ++ IN u8 *data, ++ IN BOOLEAN bPseudoTest) ++{ ++ int ret=0; ++ ++ if(IS_HARDWARE_TYPE_8192C(pAdapter)) ++ { ++ ret = hal_EfusePgPacketWrite_8192C(pAdapter, offset, word_en, data, bPseudoTest); ++ } ++ else if(IS_HARDWARE_TYPE_8723(pAdapter)) ++ { ++ ret = hal_EfusePgPacketWrite_8723(pAdapter, offset, word_en, data, bPseudoTest); ++ } ++ ++ return ret; ++} ++ ++static int ++rtl8192c_Efuse_PgPacketWrite(IN PADAPTER pAdapter, ++ IN u8 offset, ++ IN u8 word_en, ++ IN u8 *data, ++ IN BOOLEAN bPseudoTest) ++{ ++ int ret; ++ ++ if(bPseudoTest) ++ { ++ ret = Hal_EfusePgPacketWrite_Pseudo(pAdapter, offset, word_en, data, bPseudoTest); ++ } ++ else ++ { ++ ret = Hal_EfusePgPacketWrite(pAdapter, offset, word_en, data, bPseudoTest); ++ } ++ return ret; ++} ++ ++VOID ++rtl8192c_EfuseParseIDCode( ++ IN PADAPTER pAdapter, ++ IN u8 *hwinfo ++ ) ++{ ++ EEPROM_EFUSE_PRIV *pEEPROM = GET_EEPROM_EFUSE_PRIV(pAdapter); ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); ++ u16 i,EEPROMId; ++ ++ // Checl 0x8129 again for making sure autoload status!! ++ EEPROMId = *((u16 *)&hwinfo[0]); ++ if( le16_to_cpu(EEPROMId) != RTL_EEPROM_ID) ++ { ++ DBG_8192C("EEPROM ID(%#x) is invalid!!\n", EEPROMId); ++ pEEPROM->bautoload_fail_flag = _TRUE; ++ } ++ else ++ { ++ pEEPROM->bautoload_fail_flag = _FALSE; ++ } ++ ++ //RT_TRACE(COMP_INIT, DBG_LOUD, ("EEPROM ID = 0x%4x\n", EEPROMId)); ++} ++ ++void rtl8192c_read_chip_version(PADAPTER pAdapter) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); ++ pHalData->VersionID = rtl8192c_ReadChipVersion(pAdapter); ++} ++ ++void rtl8192c_set_hal_ops(struct hal_ops *pHalFunc) ++{ ++ pHalFunc->free_hal_data = &rtl8192c_free_hal_data; ++ ++ pHalFunc->dm_init = &rtl8192c_init_dm_priv; ++ pHalFunc->dm_deinit = &rtl8192c_deinit_dm_priv; ++ pHalFunc->read_chip_version = &rtl8192c_read_chip_version; ++ ++ pHalFunc->set_bwmode_handler = &PHY_SetBWMode8192C; ++ pHalFunc->set_channel_handler = &PHY_SwChnl8192C; ++ ++ pHalFunc->hal_dm_watchdog = &rtl8192c_HalDmWatchDog; ++ ++ pHalFunc->Add_RateATid = &rtl8192c_Add_RateATid; ++ ++#ifdef CONFIG_ANTENNA_DIVERSITY ++ pHalFunc->SwAntDivBeforeLinkHandler = &SwAntDivBeforeLink8192C; ++ pHalFunc->SwAntDivCompareHandler = &SwAntDivCompare8192C; ++#endif ++ ++ pHalFunc->read_bbreg = &rtl8192c_PHY_QueryBBReg; ++ pHalFunc->write_bbreg = &rtl8192c_PHY_SetBBReg; ++ pHalFunc->read_rfreg = &rtl8192c_PHY_QueryRFReg; ++ pHalFunc->write_rfreg = &rtl8192c_PHY_SetRFReg; ++ ++ //Efuse related function ++ pHalFunc->EfusePowerSwitch = &rtl8192c_EfusePowerSwitch; ++ pHalFunc->ReadEFuse = &rtl8192c_ReadEFuse; ++ pHalFunc->EFUSEGetEfuseDefinition = &rtl8192c_EFUSE_GetEfuseDefinition; ++ pHalFunc->EfuseGetCurrentSize = &rtl8192c_EfuseGetCurrentSize; ++ pHalFunc->Efuse_PgPacketRead = &rtl8192c_Efuse_PgPacketRead; ++ pHalFunc->Efuse_PgPacketWrite = &rtl8192c_Efuse_PgPacketWrite; ++ pHalFunc->Efuse_WordEnableDataWrite = &rtl8192c_Efuse_WordEnableDataWrite; ++ ++#ifdef DBG_CONFIG_ERROR_DETECT ++ pHalFunc->sreset_init_value = &rtl8192c_sreset_init_value; ++ pHalFunc->sreset_reset_value = &rtl8192c_sreset_reset_value; ++ pHalFunc->silentreset = &rtl8192c_silentreset_for_specific_platform; ++ pHalFunc->sreset_xmit_status_check = &rtl8192c_sreset_xmit_status_check; ++ pHalFunc->sreset_linked_status_check = &rtl8192c_sreset_linked_status_check; ++ pHalFunc->sreset_get_wifi_status = &rtl8192c_sreset_get_wifi_status; ++#endif ++ ++#ifdef CONFIG_IOL ++ pHalFunc->IOL_exec_cmds_sync = &rtl8192c_IOL_exec_cmds_sync; ++#endif ++} ++ +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/hal/rtl8192c/rtl8192c_mp.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/hal/rtl8192c/rtl8192c_mp.c 2013-07-26 19:36:05.000000000 +0000 +@@ -0,0 +1,1230 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#define _RTL8192C_MP_C_ ++#ifdef CONFIG_MP_INCLUDED ++ ++#include ++#include ++ ++#ifdef CONFIG_RTL8192C ++#include ++#endif ++ ++ ++ ++s32 Hal_SetPowerTracking(PADAPTER padapter, u8 enable) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); ++ struct dm_priv *pdmpriv = &pHalData->dmpriv; ++ ++ ++ if (!netif_running(padapter->pnetdev)) { ++ RT_TRACE(_module_mp_, _drv_warning_, ("SetPowerTracking! Fail: interface not opened!\n")); ++ return _FAIL; ++ } ++ ++ if (check_fwstate(&padapter->mlmepriv, WIFI_MP_STATE) == _FALSE) { ++ RT_TRACE(_module_mp_, _drv_warning_, ("SetPowerTracking! Fail: not in MP mode!\n")); ++ return _FAIL; ++ } ++ ++ if (enable) ++ pdmpriv->TxPowerTrackControl = _TRUE; ++ else ++ pdmpriv->TxPowerTrackControl = _FALSE; ++ ++ return _SUCCESS; ++} ++ ++void Hal_GetPowerTracking(PADAPTER padapter, u8 *enable) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); ++ struct dm_priv *pdmpriv = &pHalData->dmpriv; ++ ++ ++ *enable = pdmpriv->TxPowerTrackControl; ++} ++ ++static void Hal_disable_dm(PADAPTER padapter) ++{ ++ u8 v8; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); ++ struct dm_priv *pdmpriv = &pHalData->dmpriv; ++ ++ ++ //3 1. disable firmware dynamic mechanism ++ // disable Power Training, Rate Adaptive ++ v8 = rtw_read8(padapter, REG_BCN_CTRL); ++ v8 &= ~EN_BCN_FUNCTION; ++ rtw_write8(padapter, REG_BCN_CTRL, v8); ++ ++ //3 2. disable driver dynamic mechanism ++ // disable Dynamic Initial Gain ++ // disable High Power ++ // disable Power Tracking ++ Switch_DM_Func(padapter, DYNAMIC_FUNC_DISABLE, _FALSE); ++ ++ // enable APK, LCK and IQK but disable power tracking ++ pdmpriv->TxPowerTrackControl = _FALSE; ++ Switch_DM_Func(padapter, DYNAMIC_FUNC_SS, _TRUE); ++} ++ ++/*----------------------------------------------------------------------------- ++ * Function: mpt_SwitchRfSetting ++ * ++ * Overview: Change RF Setting when we siwthc channel/rate/BW for MP. ++ * ++ * Input: IN PADAPTER pAdapter ++ * ++ * Output: NONE ++ * ++ * Return: NONE ++ * ++ * Revised History: ++ * When Who Remark ++ * 01/08/2009 MHC Suggestion from SD3 Willis for 92S series. ++ * 01/09/2009 MHC Add CCK modification for 40MHZ. Suggestion from SD3. ++ * ++ *---------------------------------------------------------------------------*/ ++void Hal_mpt_SwitchRfSetting(PADAPTER pAdapter) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); ++ struct mp_priv *pmp = &pAdapter->mppriv; ++ u8 ChannelToSw = pmp->channel, eRFPath = RF90_PATH_A; ++ u8 ulRateIdx = pmp->rateidx; ++ u8 ulbandwidth = pmp->bandwidth; ++ PMPT_CONTEXT pMptCtx = &(pAdapter->mppriv.MptCtx); ++ BOOLEAN bInteralPA = _FALSE; ++ u32 value = 0; ++ ++#ifdef CONFIG_USB_HCI ++ if (IS_92C_SERIAL(pHalData->VersionID)) ++ { ++ //92CE-VAU (92cu mCard) ++ if( BOARD_MINICARD == pHalData->BoardType) ++ { ++ if (ulRateIdx < MPT_RATE_6M) // CCK rate ++ { ++ write_rfreg(pAdapter, 0, RF_SYN_G2, 0x0F400); ++ } ++ else //OFDM~MCS rate ++ { ++ write_rfreg(pAdapter, 0, RF_SYN_G2, 0x4F000); ++ } ++ } ++ else //92CU dongle ++ { ++ if (ulRateIdx < MPT_RATE_6M) // CCK rate ++ { ++ write_rfreg(pAdapter, 0, RF_SYN_G2, 0x0F400); ++ } ++ else if (ChannelToSw & BIT0) // OFDM rate, odd number channel ++ { ++ write_rfreg(pAdapter, 0, RF_SYN_G2, 0x4F200); ++ } ++ else if (ChannelToSw == 4) // OFDM rate, even number channel ++ { ++ write_rfreg(pAdapter, 0, RF_SYN_G2, 0x28200); ++ write_rfreg(pAdapter, 0, RF_SYN_G6, 0xe0004); ++ write_rfreg(pAdapter, 0, RF_SYN_G7, 0x709); ++ rtw_msleep_os(1); ++ write_rfreg(pAdapter, 0, RF_SYN_G7, 0x4B333); ++ } ++ else if(ChannelToSw == 10) // OFDM rate, even number channel ++ { ++ write_rfreg(pAdapter, 0, RF_SYN_G2, 0x28000); ++ write_rfreg(pAdapter, 0, RF_SYN_G6, 0xe000A); ++ write_rfreg(pAdapter, 0, RF_SYN_G7, 0x709); ++ rtw_msleep_os(1); ++ write_rfreg(pAdapter, 0, RF_SYN_G7, 0x7B333); ++ } ++ else if(ChannelToSw == 12) // OFDM rate, even number channel ++ { ++ write_rfreg(pAdapter, 0, RF_SYN_G2, 0x28200); ++ write_rfreg(pAdapter, 0, RF_SYN_G6, 0xe000C); ++ write_rfreg(pAdapter, 0, RF_SYN_G7, 0x50B); ++ rtw_msleep_os(1); ++ write_rfreg(pAdapter, 0, RF_SYN_G7, 0x4B333); ++ } ++ else ++ { ++ write_rfreg(pAdapter, 0, RF_SYN_G2, 0x4F200); ++ } ++ } ++ } ++ else //88cu ++ { ++ ++ //mcard interface ++ ++ if( BOARD_MINICARD == pHalData->BoardType) ++ { ++ if (ulRateIdx < MPT_RATE_6M) // CCK rate ++ { ++ write_rfreg(pAdapter, 0, RF_SYN_G2, 0x0F400); ++ } ++ else //OFDM~MCS rate ++ { ++ write_rfreg(pAdapter, 0, RF_SYN_G2, 0x4F200); ++ } ++ ++ if(ChannelToSw == 6 || ChannelToSw == 8) ++ { ++ write_bbreg(pAdapter, rOFDM0_XAAGCCore1, bMaskByte0, 0x22); ++ write_bbreg(pAdapter, rOFDM0_XBAGCCore1, bMaskByte0, 0x22); ++ write_bbreg(pAdapter, rOFDM0_RxDetector1, bMaskByte0, 0x4F); ++ } ++ else ++ { ++ write_bbreg(pAdapter, rOFDM0_XAAGCCore1, bMaskByte0, 0x20); ++ write_bbreg(pAdapter, rOFDM0_XBAGCCore1, bMaskByte0, 0x20); ++ write_bbreg(pAdapter, rOFDM0_RxDetector1, bMaskByte0, pMptCtx->backup0xc30); ++ } ++ } ++ else ++ { ++ if (ulRateIdx < MPT_RATE_6M) // CCK rate ++ { ++ write_rfreg(pAdapter, 0, RF_SYN_G2, 0x0F400); ++ } ++ else if (ChannelToSw & BIT0) // OFDM rate, odd number channel ++ { ++ write_rfreg(pAdapter, 0, RF_SYN_G2, 0x4F200); ++ } ++ else ++ { ++ write_rfreg(pAdapter, 0, RF_SYN_G2, 0x4F000); ++ } ++ } ++ } ++ ++#else //PCI_INTERFACE ++ ++ if (ulRateIdx < MPT_RATE_6M) // CCK rate ++ { ++ write_rfreg(pAdapter, 0, RF_SYN_G2, 0x0F400); ++ } ++ else //OFDM~MCS rate ++ { ++ write_rfreg(pAdapter, 0, RF_SYN_G2, 0x4F000); ++ } ++ //88CE ++ if(!IS_92C_SERIAL(pHalData->VersionID)) ++ { ++ if(ChannelToSw == 6 || ChannelToSw == 8) ++ { ++ write_bbreg(pAdapter, rOFDM0_XAAGCCore1, bMaskByte0, 0x22); ++ write_bbreg(pAdapter, rOFDM0_XBAGCCore1, bMaskByte0, 0x22); ++ write_bbreg(pAdapter, rOFDM0_RxDetector1, bMaskByte0, 0x4F); ++ } ++ else ++ { ++ write_bbreg(pAdapter, rOFDM0_XAAGCCore1, bMaskByte0, pMptCtx->backup0xc50); ++ write_bbreg(pAdapter, rOFDM0_XBAGCCore1, bMaskByte0, pMptCtx->backup0xc58); ++ write_bbreg(pAdapter, rOFDM0_RxDetector1, bMaskByte0, pMptCtx->backup0xc30); ++ } ++ } ++ ++#endif //CONFIG_USB_HCI ++ ++ ++} ++/*---------------------------hal\rtl8192c\MPT_Phy.c---------------------------*/ ++ ++/*---------------------------hal\rtl8192c\MPT_HelperFunc.c---------------------------*/ ++void Hal_MPT_CCKTxPowerAdjust(PADAPTER Adapter, BOOLEAN bInCH14) ++{ ++ u32 TempVal = 0, TempVal2 = 0, TempVal3 = 0; ++ u32 CurrCCKSwingVal = 0, CCKSwingIndex = 12; ++ u8 i; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ ++ ++ // get current cck swing value and check 0xa22 & 0xa23 later to match the table. ++ CurrCCKSwingVal = read_bbreg(Adapter, rCCK0_TxFilter1, bMaskHWord); ++ ++ if (!bInCH14) ++ { ++ // Readback the current bb cck swing value and compare with the table to ++ // get the current swing index ++ for (i = 0; i < CCK_TABLE_SIZE; i++) ++ { ++ if (((CurrCCKSwingVal&0xff) == (u32)CCKSwingTable_Ch1_Ch13[i][0]) && ++ (((CurrCCKSwingVal&0xff00)>>8) == (u32)CCKSwingTable_Ch1_Ch13[i][1])) ++ { ++ CCKSwingIndex = i; ++// RT_TRACE(COMP_INIT, DBG_LOUD,("Ch1~13, Current reg0x%x = 0x%lx, CCKSwingIndex=0x%x\n", ++// (rCCK0_TxFilter1+2), CurrCCKSwingVal, CCKSwingIndex)); ++ break; ++ } ++ } ++ ++ //Write 0xa22 0xa23 ++ TempVal = CCKSwingTable_Ch1_Ch13[CCKSwingIndex][0] + ++ (CCKSwingTable_Ch1_Ch13[CCKSwingIndex][1]<<8) ; ++ ++ ++ //Write 0xa24 ~ 0xa27 ++ TempVal2 = 0; ++ TempVal2 = CCKSwingTable_Ch1_Ch13[CCKSwingIndex][2] + ++ (CCKSwingTable_Ch1_Ch13[CCKSwingIndex][3]<<8) + ++ (CCKSwingTable_Ch1_Ch13[CCKSwingIndex][4]<<16 )+ ++ (CCKSwingTable_Ch1_Ch13[CCKSwingIndex][5]<<24); ++ ++ //Write 0xa28 0xa29 ++ TempVal3 = 0; ++ TempVal3 = CCKSwingTable_Ch1_Ch13[CCKSwingIndex][6] + ++ (CCKSwingTable_Ch1_Ch13[CCKSwingIndex][7]<<8) ; ++ } ++ else ++ { ++ for (i = 0; i < CCK_TABLE_SIZE; i++) ++ { ++ if (((CurrCCKSwingVal&0xff) == (u32)CCKSwingTable_Ch14[i][0]) && ++ (((CurrCCKSwingVal&0xff00)>>8) == (u32)CCKSwingTable_Ch14[i][1])) ++ { ++ CCKSwingIndex = i; ++// RT_TRACE(COMP_INIT, DBG_LOUD,("Ch14, Current reg0x%x = 0x%lx, CCKSwingIndex=0x%x\n", ++// (rCCK0_TxFilter1+2), CurrCCKSwingVal, CCKSwingIndex)); ++ break; ++ } ++ } ++ ++ //Write 0xa22 0xa23 ++ TempVal = CCKSwingTable_Ch14[CCKSwingIndex][0] + ++ (CCKSwingTable_Ch14[CCKSwingIndex][1]<<8) ; ++ ++ //Write 0xa24 ~ 0xa27 ++ TempVal2 = 0; ++ TempVal2 = CCKSwingTable_Ch14[CCKSwingIndex][2] + ++ (CCKSwingTable_Ch14[CCKSwingIndex][3]<<8) + ++ (CCKSwingTable_Ch14[CCKSwingIndex][4]<<16 )+ ++ (CCKSwingTable_Ch14[CCKSwingIndex][5]<<24); ++ ++ //Write 0xa28 0xa29 ++ TempVal3 = 0; ++ TempVal3 = CCKSwingTable_Ch14[CCKSwingIndex][6] + ++ (CCKSwingTable_Ch14[CCKSwingIndex][7]<<8) ; ++ } ++ ++ write_bbreg(Adapter, rCCK0_TxFilter1, bMaskHWord, TempVal); ++ write_bbreg(Adapter, rCCK0_TxFilter2, bMaskDWord, TempVal2); ++ write_bbreg(Adapter, rCCK0_DebugPort, bMaskLWord, TempVal3); ++} ++ ++void Hal_MPT_CCKTxPowerAdjustbyIndex(PADAPTER pAdapter, BOOLEAN beven) ++{ ++ s32 TempCCk; ++ u8 CCK_index, CCK_index_old; ++ u8 Action = 0; //0: no action, 1: even->odd, 2:odd->even ++ u8 TimeOut = 100; ++ s32 i = 0; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); ++ PMPT_CONTEXT pMptCtx = &pAdapter->mppriv.MptCtx; ++ ++ ++ if (!IS_92C_SERIAL(pHalData->VersionID) || !IS_NORMAL_CHIP(pHalData->VersionID)) ++ return; ++#if 0 ++ while(PlatformAtomicExchange(&Adapter->IntrCCKRefCount, TRUE) == TRUE) ++ { ++ PlatformSleepUs(100); ++ TimeOut--; ++ if(TimeOut <= 0) ++ { ++ RTPRINT(FINIT, INIT_TxPower, ++ ("!!!MPT_CCKTxPowerAdjustbyIndex Wait for check CCK gain index too long!!!\n" )); ++ break; ++ } ++ } ++#endif ++ if (beven && !pMptCtx->bMptIndexEven) //odd->even ++ { ++ Action = 2; ++ pMptCtx->bMptIndexEven = _TRUE; ++ } ++ else if (!beven && pMptCtx->bMptIndexEven) //even->odd ++ { ++ Action = 1; ++ pMptCtx->bMptIndexEven = _FALSE; ++ } ++ ++ if (Action != 0) ++ { ++ //Query CCK default setting From 0xa24 ++ TempCCk = read_bbreg(pAdapter, rCCK0_TxFilter2, bMaskDWord) & bMaskCCK; ++ for (i = 0; i < CCK_TABLE_SIZE; i++) ++ { ++ if (pHalData->dmpriv.bCCKinCH14) ++ { ++ if (_rtw_memcmp((void*)&TempCCk, (void*)&CCKSwingTable_Ch14[i][2], 4) == _TRUE) ++ { ++ CCK_index_old = (u8) i; ++// RTPRINT(FINIT, INIT_TxPower,("MPT_CCKTxPowerAdjustbyIndex: Initial reg0x%x = 0x%lx, CCK_index=0x%x, ch 14 %d\n", ++// rCCK0_TxFilter2, TempCCk, CCK_index_old, pHalData->bCCKinCH14)); ++ break; ++ } ++ } ++ else ++ { ++ if (_rtw_memcmp((void*)&TempCCk, (void*)&CCKSwingTable_Ch1_Ch13[i][2], 4) == _TRUE) ++ { ++ CCK_index_old = (u8) i; ++// RTPRINT(FINIT, INIT_TxPower,("MPT_CCKTxPowerAdjustbyIndex: Initial reg0x%x = 0x%lx, CCK_index=0x%x, ch14 %d\n", ++// rCCK0_TxFilter2, TempCCk, CCK_index_old, pHalData->bCCKinCH14)); ++ break; ++ } ++ } ++ } ++ ++ if (Action == 1) ++ CCK_index = CCK_index_old - 1; ++ else ++ CCK_index = CCK_index_old + 1; ++ ++// RTPRINT(FINIT, INIT_TxPower,("MPT_CCKTxPowerAdjustbyIndex: new CCK_index=0x%x\n", ++// CCK_index)); ++ ++ //Adjust CCK according to gain index ++ if (!pHalData->dmpriv.bCCKinCH14) { ++ rtw_write8(pAdapter, 0xa22, CCKSwingTable_Ch1_Ch13[CCK_index][0]); ++ rtw_write8(pAdapter, 0xa23, CCKSwingTable_Ch1_Ch13[CCK_index][1]); ++ rtw_write8(pAdapter, 0xa24, CCKSwingTable_Ch1_Ch13[CCK_index][2]); ++ rtw_write8(pAdapter, 0xa25, CCKSwingTable_Ch1_Ch13[CCK_index][3]); ++ rtw_write8(pAdapter, 0xa26, CCKSwingTable_Ch1_Ch13[CCK_index][4]); ++ rtw_write8(pAdapter, 0xa27, CCKSwingTable_Ch1_Ch13[CCK_index][5]); ++ rtw_write8(pAdapter, 0xa28, CCKSwingTable_Ch1_Ch13[CCK_index][6]); ++ rtw_write8(pAdapter, 0xa29, CCKSwingTable_Ch1_Ch13[CCK_index][7]); ++ } else { ++ rtw_write8(pAdapter, 0xa22, CCKSwingTable_Ch14[CCK_index][0]); ++ rtw_write8(pAdapter, 0xa23, CCKSwingTable_Ch14[CCK_index][1]); ++ rtw_write8(pAdapter, 0xa24, CCKSwingTable_Ch14[CCK_index][2]); ++ rtw_write8(pAdapter, 0xa25, CCKSwingTable_Ch14[CCK_index][3]); ++ rtw_write8(pAdapter, 0xa26, CCKSwingTable_Ch14[CCK_index][4]); ++ rtw_write8(pAdapter, 0xa27, CCKSwingTable_Ch14[CCK_index][5]); ++ rtw_write8(pAdapter, 0xa28, CCKSwingTable_Ch14[CCK_index][6]); ++ rtw_write8(pAdapter, 0xa29, CCKSwingTable_Ch14[CCK_index][7]); ++ } ++ } ++#if 0 ++ RTPRINT(FINIT, INIT_TxPower, ++ ("MPT_CCKTxPowerAdjustbyIndex 0xa20=%x\n", PlatformEFIORead4Byte(Adapter, 0xa20))); ++ ++ PlatformAtomicExchange(&Adapter->IntrCCKRefCount, FALSE); ++#endif ++} ++/*---------------------------hal\rtl8192c\MPT_HelperFunc.c---------------------------*/ ++ ++/* ++ * SetChannel ++ * Description ++ * Use H2C command to change channel, ++ * not only modify rf register, but also other setting need to be done. ++ */ ++void Hal_SetChannel(PADAPTER pAdapter) ++{ ++#if 0 ++ struct mp_priv *pmp = &pAdapter->mppriv; ++ ++// SelectChannel(pAdapter, pmp->channel); ++ set_channel_bwmode(pAdapter, pmp->channel, pmp->channel_offset, pmp->bandwidth); ++#else ++ u8 eRFPath; ++ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); ++ struct mp_priv *pmp = &pAdapter->mppriv; ++ u8 channel = pmp->channel; ++ u8 bandwidth = pmp->bandwidth; ++ u8 rate = pmp->rateidx; ++ ++ ++ // set RF channel register ++ for (eRFPath = 0; eRFPath < pHalData->NumTotalRFPath; eRFPath++) ++ { ++ if(IS_HARDWARE_TYPE_8192D(pAdapter)) ++ _write_rfreg(pAdapter, (RF90_RADIO_PATH_E)eRFPath, rRfChannel, 0xFF, channel); ++ else ++ _write_rfreg(pAdapter, eRFPath, rRfChannel, 0x3FF, channel); ++ } ++ Hal_mpt_SwitchRfSetting(pAdapter); ++ ++ SelectChannel(pAdapter, channel); ++ ++ if (pHalData->CurrentChannel == 14 && !pHalData->dmpriv.bCCKinCH14) { ++ pHalData->dmpriv.bCCKinCH14 = _TRUE; ++ Hal_MPT_CCKTxPowerAdjust(pAdapter, pHalData->dmpriv.bCCKinCH14); ++ } ++ else if (pHalData->CurrentChannel != 14 && pHalData->dmpriv.bCCKinCH14) { ++ pHalData->dmpriv.bCCKinCH14 = _FALSE; ++ Hal_MPT_CCKTxPowerAdjust(pAdapter, pHalData->dmpriv.bCCKinCH14); ++ } ++#if 0 ++//#ifdef CONFIG_USB_HCI ++ // Georgia add 2009-11-17, suggested by Edlu , for 8188CU ,46 PIN ++ if (!IS_92C_SERIAL(pHalData->VersionID) && !IS_NORMAL_CHIP(pHalData->VersionID)) { ++ mpt_AdjustRFRegByRateByChan92CU(pAdapter, rate, pHalData->CurrentChannel, bandwidth); ++ } ++#endif ++ ++#endif ++} ++ ++/* ++ * Notice ++ * Switch bandwitdth may change center frequency(channel) ++ */ ++void Hal_SetBandwidth(PADAPTER pAdapter) ++{ ++ struct mp_priv *pmp = &pAdapter->mppriv; ++ ++ ++ SetBWMode(pAdapter, pmp->bandwidth, pmp->prime_channel_offset); ++ Hal_mpt_SwitchRfSetting(pAdapter); ++} ++ ++void Hal_SetCCKTxPower(PADAPTER pAdapter, u8 *TxPower) ++{ ++ u32 tmpval = 0; ++ ++ ++ // rf-A cck tx power ++ write_bbreg(pAdapter, rTxAGC_A_CCK1_Mcs32, bMaskByte1, TxPower[RF_PATH_A]); ++ tmpval = (TxPower[RF_PATH_A]<<16) | (TxPower[RF_PATH_A]<<8) | TxPower[RF_PATH_A]; ++ write_bbreg(pAdapter, rTxAGC_B_CCK11_A_CCK2_11, 0xffffff00, tmpval); ++ ++ // rf-B cck tx power ++ write_bbreg(pAdapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte0, TxPower[RF_PATH_B]); ++ tmpval = (TxPower[RF_PATH_B]<<16) | (TxPower[RF_PATH_B]<<8) | TxPower[RF_PATH_B]; ++ write_bbreg(pAdapter, rTxAGC_B_CCK1_55_Mcs32, 0xffffff00, tmpval); ++ ++ RT_TRACE(_module_mp_, _drv_notice_, ++ ("-SetCCKTxPower: A[0x%02x] B[0x%02x]\n", ++ TxPower[RF_PATH_A], TxPower[RF_PATH_B])); ++} ++ ++void Hal_SetOFDMTxPower(PADAPTER pAdapter, u8 *TxPower) ++{ ++ u32 TxAGC = 0; ++ u8 tmpval = 0; ++ PMPT_CONTEXT pMptCtx = &pAdapter->mppriv.MptCtx; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); ++ ++ ++ // HT Tx-rf(A) ++ tmpval = TxPower[RF_PATH_A]; ++ TxAGC = (tmpval<<24) | (tmpval<<16) | (tmpval<<8) | tmpval; ++ ++ write_bbreg(pAdapter, rTxAGC_A_Rate18_06, bMaskDWord, TxAGC); ++ write_bbreg(pAdapter, rTxAGC_A_Rate54_24, bMaskDWord, TxAGC); ++ write_bbreg(pAdapter, rTxAGC_A_Mcs03_Mcs00, bMaskDWord, TxAGC); ++ write_bbreg(pAdapter, rTxAGC_A_Mcs07_Mcs04, bMaskDWord, TxAGC); ++ write_bbreg(pAdapter, rTxAGC_A_Mcs11_Mcs08, bMaskDWord, TxAGC); ++ write_bbreg(pAdapter, rTxAGC_A_Mcs15_Mcs12, bMaskDWord, TxAGC); ++ ++ if (pHalData->dmpriv.bAPKdone && !IS_NORMAL_CHIP(pHalData->VersionID)) ++ { ++ if (tmpval > pMptCtx->APK_bound[RF_PATH_A]) ++ write_rfreg(pAdapter, RF_PATH_A, 0xe, pHalData->dmpriv.APKoutput[0][0]); ++ else ++ write_rfreg(pAdapter, RF_PATH_A, 0xe, pHalData->dmpriv.APKoutput[0][1]); ++ } ++ ++ // HT Tx-rf(B) ++ tmpval = TxPower[RF_PATH_B]; ++ TxAGC = (tmpval<<24) | (tmpval<<16) | (tmpval<<8) | tmpval; ++ ++ write_bbreg(pAdapter, rTxAGC_B_Rate18_06, bMaskDWord, TxAGC); ++ write_bbreg(pAdapter, rTxAGC_B_Rate54_24, bMaskDWord, TxAGC); ++ write_bbreg(pAdapter, rTxAGC_B_Mcs03_Mcs00, bMaskDWord, TxAGC); ++ write_bbreg(pAdapter, rTxAGC_B_Mcs07_Mcs04, bMaskDWord, TxAGC); ++ write_bbreg(pAdapter, rTxAGC_B_Mcs11_Mcs08, bMaskDWord, TxAGC); ++ write_bbreg(pAdapter, rTxAGC_B_Mcs15_Mcs12, bMaskDWord, TxAGC); ++ ++ if (pHalData->dmpriv.bAPKdone && !IS_NORMAL_CHIP(pHalData->VersionID)) ++ { ++ if (tmpval > pMptCtx->APK_bound[RF_PATH_B]) ++ write_rfreg(pAdapter, RF_PATH_B, 0xe, pHalData->dmpriv.APKoutput[1][0]); ++ else ++ write_rfreg(pAdapter, RF_PATH_B, 0xe, pHalData->dmpriv.APKoutput[1][1]); ++ } ++ ++ RT_TRACE(_module_mp_, _drv_notice_, ++ ("-SetOFDMTxPower: A[0x%02x] B[0x%02x]\n", ++ TxPower[RF_PATH_A], TxPower[RF_PATH_B])); ++} ++ ++void Hal_SetAntennaPathPower(PADAPTER pAdapter) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); ++ u8 TxPowerLevel[MAX_RF_PATH_NUMS]; ++ u8 rfPath; ++ ++ TxPowerLevel[RF_PATH_A] = pAdapter->mppriv.txpoweridx; ++ TxPowerLevel[RF_PATH_B] = pAdapter->mppriv.txpoweridx_b; ++ ++ switch (pAdapter->mppriv.antenna_tx) ++ { ++ case ANTENNA_A: ++ default: ++ rfPath = RF_PATH_A; ++ break; ++ case ANTENNA_B: ++ rfPath = RF_PATH_B; ++ break; ++ case ANTENNA_C: ++ rfPath = RF_PATH_C; ++ break; ++ } ++ ++ switch (pHalData->rf_chip) ++ { ++ case RF_8225: ++ case RF_8256: ++ case RF_6052: ++ Hal_SetCCKTxPower(pAdapter, TxPowerLevel); ++ if (pAdapter->mppriv.rateidx < MPT_RATE_6M) // CCK rate ++ Hal_MPT_CCKTxPowerAdjustbyIndex(pAdapter, TxPowerLevel[rfPath]%2 == 0); ++ Hal_SetOFDMTxPower(pAdapter, TxPowerLevel); ++ break; ++ ++ default: ++ break; ++ } ++} ++ ++void Hal_SetTxPower(PADAPTER pAdapter) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); ++ u8 TxPower = pAdapter->mppriv.txpoweridx; ++ u8 TxPowerLevel[MAX_RF_PATH_NUMS]; ++ u8 rf, rfPath; ++ ++ for (rf = 0; rf < MAX_RF_PATH_NUMS; rf++) { ++ TxPowerLevel[rf] = TxPower; ++ } ++ ++ switch (pAdapter->mppriv.antenna_tx) ++ { ++ case ANTENNA_A: ++ default: ++ rfPath = RF_PATH_A; ++ break; ++ case ANTENNA_B: ++ rfPath = RF_PATH_B; ++ break; ++ case ANTENNA_C: ++ rfPath = RF_PATH_C; ++ break; ++ } ++ ++ switch (pHalData->rf_chip) ++ { ++ // 2008/09/12 MH Test only !! We enable the TX power tracking for MP!!!!! ++ // We should call normal driver API later!! ++ case RF_8225: ++ case RF_8256: ++ case RF_6052: ++ Hal_SetCCKTxPower(pAdapter, TxPowerLevel); ++ if (pAdapter->mppriv.rateidx < MPT_RATE_6M) // CCK rate ++ Hal_MPT_CCKTxPowerAdjustbyIndex(pAdapter, TxPowerLevel[rfPath]%2 == 0); ++ Hal_SetOFDMTxPower(pAdapter, TxPowerLevel); ++ break; ++ ++ default: ++ break; ++ } ++ ++// SetCCKTxPower(pAdapter, TxPower); ++// SetOFDMTxPower(pAdapter, TxPower); ++} ++ ++void Hal_SetTxAGCOffset(PADAPTER pAdapter, u32 ulTxAGCOffset) ++{ ++ u32 TxAGCOffset_B, TxAGCOffset_C, TxAGCOffset_D,tmpAGC; ++ ++ TxAGCOffset_B = (ulTxAGCOffset&0x000000ff); ++ TxAGCOffset_C = ((ulTxAGCOffset&0x0000ff00)>>8); ++ TxAGCOffset_D = ((ulTxAGCOffset&0x00ff0000)>>16); ++ ++ tmpAGC = (TxAGCOffset_D<<8 | TxAGCOffset_C<<4 | TxAGCOffset_B); ++ write_bbreg(pAdapter, rFPGA0_TxGainStage, ++ (bXBTxAGC|bXCTxAGC|bXDTxAGC), tmpAGC); ++} ++ ++void Hal_SetDataRate(PADAPTER pAdapter) ++{ ++ Hal_mpt_SwitchRfSetting(pAdapter); ++} ++ ++#if !defined (CONFIG_RTL8192C) && !defined (CONFIG_RTL8192D) ++/*------------------------------Define structure----------------------------*/ ++typedef struct _R_ANTENNA_SELECT_OFDM { ++ u32 r_tx_antenna:4; ++ u32 r_ant_l:4; ++ u32 r_ant_non_ht:4; ++ u32 r_ant_ht1:4; ++ u32 r_ant_ht2:4; ++ u32 r_ant_ht_s1:4; ++ u32 r_ant_non_ht_s1:4; ++ u32 OFDM_TXSC:2; ++ u32 Reserved:2; ++}R_ANTENNA_SELECT_OFDM; ++ ++typedef struct _R_ANTENNA_SELECT_CCK { ++ u8 r_cckrx_enable_2:2; ++ u8 r_cckrx_enable:2; ++ u8 r_ccktx_enable:4; ++}R_ANTENNA_SELECT_CCK; ++#endif ++ ++void Hal_SetAntenna(PADAPTER pAdapter) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); ++ ++ R_ANTENNA_SELECT_OFDM *p_ofdm_tx; /* OFDM Tx register */ ++ R_ANTENNA_SELECT_CCK *p_cck_txrx; ++ ++ u8 r_rx_antenna_ofdm = 0, r_ant_select_cck_val = 0; ++ u8 chgTx = 0, chgRx = 0; ++ u32 r_ant_sel_cck_val = 0, r_ant_select_ofdm_val = 0, r_ofdm_tx_en_val = 0; ++ ++ ++ p_ofdm_tx = (R_ANTENNA_SELECT_OFDM *)&r_ant_select_ofdm_val; ++ p_cck_txrx = (R_ANTENNA_SELECT_CCK *)&r_ant_select_cck_val; ++ ++ p_ofdm_tx->r_ant_ht1 = 0x1; ++ p_ofdm_tx->r_ant_ht2 = 0x2; // Second TX RF path is A ++ p_ofdm_tx->r_ant_non_ht = 0x3; // 0x1+0x2=0x3 ++ ++ switch (pAdapter->mppriv.antenna_tx) ++ { ++ case ANTENNA_A: ++ p_ofdm_tx->r_tx_antenna = 0x1; ++ r_ofdm_tx_en_val = 0x1; ++ p_ofdm_tx->r_ant_l = 0x1; ++ p_ofdm_tx->r_ant_ht_s1 = 0x1; ++ p_ofdm_tx->r_ant_non_ht_s1 = 0x1; ++ p_cck_txrx->r_ccktx_enable = 0x8; ++ chgTx = 1; ++ ++ // From SD3 Willis suggestion !!! Set RF A=TX and B as standby ++// if (IS_HARDWARE_TYPE_8192S(pAdapter)) ++ { ++ write_bbreg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 2); ++ write_bbreg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 1); ++ r_ofdm_tx_en_val = 0x3; ++ ++ // Power save ++ //cosa r_ant_select_ofdm_val = 0x11111111; ++ ++ // We need to close RFB by SW control ++ if (pHalData->rf_type == RF_2T2R) ++ { ++ PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 0); ++ PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 1); ++ PHY_SetBBReg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT10, 0); ++ PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT1, 1); ++ PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT17, 0); ++ } ++ } ++ break; ++ ++ case ANTENNA_B: ++ p_ofdm_tx->r_tx_antenna = 0x2; ++ r_ofdm_tx_en_val = 0x2; ++ p_ofdm_tx->r_ant_l = 0x2; ++ p_ofdm_tx->r_ant_ht_s1 = 0x2; ++ p_ofdm_tx->r_ant_non_ht_s1 = 0x2; ++ p_cck_txrx->r_ccktx_enable = 0x4; ++ chgTx = 1; ++ ++ // From SD3 Willis suggestion !!! Set RF A as standby ++ //if (IS_HARDWARE_TYPE_8192S(pAdapter)) ++ { ++ PHY_SetBBReg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 1); ++ PHY_SetBBReg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 2); ++// r_ofdm_tx_en_val = 0x3; ++ ++ // Power save ++ //cosa r_ant_select_ofdm_val = 0x22222222; ++ ++ // 2008/10/31 MH From SD3 Willi's suggestion. We must read RF 1T table. ++ // 2009/01/08 MH From Sd3 Willis. We need to close RFA by SW control ++ if (pHalData->rf_type == RF_2T2R || pHalData->rf_type == RF_1T2R) ++ { ++ PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 1); ++ PHY_SetBBReg(pAdapter, rFPGA0_XA_RFInterfaceOE, BIT10, 0); ++ PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 0); ++// PHY_SetBBReg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT10, 0); ++ PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT1, 0); ++ PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT17, 1); ++ } ++ } ++ break; ++ ++ case ANTENNA_AB: // For 8192S ++ p_ofdm_tx->r_tx_antenna = 0x3; ++ r_ofdm_tx_en_val = 0x3; ++ p_ofdm_tx->r_ant_l = 0x3; ++ p_ofdm_tx->r_ant_ht_s1 = 0x3; ++ p_ofdm_tx->r_ant_non_ht_s1 = 0x3; ++ p_cck_txrx->r_ccktx_enable = 0xC; ++ chgTx = 1; ++ ++ // From SD3 Willis suggestion !!! Set RF B as standby ++ //if (IS_HARDWARE_TYPE_8192S(pAdapter)) ++ { ++ PHY_SetBBReg(pAdapter, rFPGA0_XA_HSSIParameter2, 0xe, 2); ++ PHY_SetBBReg(pAdapter, rFPGA0_XB_HSSIParameter2, 0xe, 2); ++ ++ // Disable Power save ++ //cosa r_ant_select_ofdm_val = 0x3321333; ++#if 0 ++ // 2008/10/31 MH From SD3 Willi's suggestion. We must read RFA 2T table. ++ if ((pHalData->VersionID == VERSION_8192S_ACUT)) // For RTL8192SU A-Cut only, by Roger, 2008.11.07. ++ { ++ mpt_RFConfigFromPreParaArrary(pAdapter, 1, RF90_PATH_A); ++ } ++#endif ++ // 2009/01/08 MH From Sd3 Willis. We need to enable RFA/B by SW control ++ if (pHalData->rf_type == RF_2T2R) ++ { ++ PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 0); ++ PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 0); ++// PHY_SetBBReg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT10, 0); ++ PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT1, 1); ++ PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT17, 1); ++ } ++ } ++ break; ++ ++ default: ++ break; ++ } ++ ++ // ++ // r_rx_antenna_ofdm, bit0=A, bit1=B, bit2=C, bit3=D ++ // r_cckrx_enable : CCK default, 0=A, 1=B, 2=C, 3=D ++ // r_cckrx_enable_2 : CCK option, 0=A, 1=B, 2=C, 3=D ++ // ++ switch (pAdapter->mppriv.antenna_rx) ++ { ++ case ANTENNA_A: ++ r_rx_antenna_ofdm = 0x1; // A ++ p_cck_txrx->r_cckrx_enable = 0x0; // default: A ++ p_cck_txrx->r_cckrx_enable_2 = 0x0; // option: A ++ chgRx = 1; ++ break; ++ ++ case ANTENNA_B: ++ r_rx_antenna_ofdm = 0x2; // B ++ p_cck_txrx->r_cckrx_enable = 0x1; // default: B ++ p_cck_txrx->r_cckrx_enable_2 = 0x1; // option: B ++ chgRx = 1; ++ break; ++ ++ case ANTENNA_AB: ++ r_rx_antenna_ofdm = 0x3; // AB ++ p_cck_txrx->r_cckrx_enable = 0x0; // default:A ++ p_cck_txrx->r_cckrx_enable_2 = 0x1; // option:B ++ chgRx = 1; ++ break; ++ ++ default: ++ break; ++ } ++ ++ if (chgTx && chgRx) ++ { ++ switch(pHalData->rf_chip) ++ { ++ case RF_8225: ++ case RF_8256: ++ case RF_6052: ++ //r_ant_sel_cck_val = r_ant_select_cck_val; ++ PHY_SetBBReg(pAdapter, rFPGA1_TxInfo, 0x7fffffff, r_ant_select_ofdm_val); //OFDM Tx ++ PHY_SetBBReg(pAdapter, rFPGA0_TxInfo, 0x0000000f, r_ofdm_tx_en_val); //OFDM Tx ++ PHY_SetBBReg(pAdapter, rOFDM0_TRxPathEnable, 0x0000000f, r_rx_antenna_ofdm); //OFDM Rx ++ PHY_SetBBReg(pAdapter, rOFDM1_TRxPathEnable, 0x0000000f, r_rx_antenna_ofdm); //OFDM Rx ++ PHY_SetBBReg(pAdapter, rCCK0_AFESetting, bMaskByte3, r_ant_select_cck_val);//r_ant_sel_cck_val); //CCK TxRx ++ ++ break; ++ ++ default: ++ break; ++ } ++ } ++ ++ RT_TRACE(_module_mp_, _drv_notice_, ("-SwitchAntenna: finished\n")); ++} ++ ++s32 Hal_SetThermalMeter(PADAPTER pAdapter, u8 target_ther) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); ++ ++ ++ if (!netif_running(pAdapter->pnetdev)) { ++ RT_TRACE(_module_mp_, _drv_warning_, ("SetThermalMeter! Fail: interface not opened!\n")); ++ return _FAIL; ++ } ++ ++ if (check_fwstate(&pAdapter->mlmepriv, WIFI_MP_STATE) == _FALSE) { ++ RT_TRACE(_module_mp_, _drv_warning_, ("SetThermalMeter: Fail! not in MP mode!\n")); ++ return _FAIL; ++ } ++ ++ target_ther &= 0xff; ++ if (target_ther < 0x07) ++ target_ther = 0x07; ++ else if (target_ther > 0x1d) ++ target_ther = 0x1d; ++ ++ pHalData->EEPROMThermalMeter = target_ther; ++ ++ return _SUCCESS; ++} ++ ++void Hal_TriggerRFThermalMeter(PADAPTER pAdapter) ++{ ++ ++ write_rfreg(pAdapter, RF_PATH_A, RF_T_METER, 0x60); // 0x24: RF Reg[6:5] ++ ++// RT_TRACE(_module_mp_,_drv_alert_, ("TriggerRFThermalMeter() finished.\n" )); ++} ++ ++u8 Hal_ReadRFThermalMeter(PADAPTER pAdapter) ++{ ++ u32 ThermalValue = 0; ++ ++ ThermalValue = _read_rfreg(pAdapter, RF_PATH_A, RF_T_METER, 0x1F); // 0x24: RF Reg[4:0] ++// RT_TRACE(_module_mp_, _drv_alert_, ("ThermalValue = 0x%x\n", ThermalValue)); ++ return (u8)ThermalValue; ++} ++ ++void Hal_GetThermalMeter(PADAPTER pAdapter, u8 *value) ++{ ++#if 0 ++ fw_cmd(pAdapter, IOCMD_GET_THERMAL_METER); ++ rtw_msleep_os(1000); ++ fw_cmd_data(pAdapter, value, 1); ++ *value &= 0xFF; ++#else ++ ++ Hal_TriggerRFThermalMeter(pAdapter); ++ rtw_msleep_os(1000); ++ *value = Hal_ReadRFThermalMeter(pAdapter); ++#endif ++} ++ ++void Hal_SetSingleCarrierTx(PADAPTER pAdapter, u8 bStart) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); ++ pAdapter->mppriv.MptCtx.bSingleCarrier = bStart; ++ if (bStart)// Start Single Carrier. ++ { ++ RT_TRACE(_module_mp_,_drv_alert_, ("SetSingleCarrierTx: test start\n")); ++ // 1. if OFDM block on? ++ if(!read_bbreg(pAdapter, rFPGA0_RFMOD, bOFDMEn)) ++ write_bbreg(pAdapter, rFPGA0_RFMOD, bOFDMEn, bEnable);//set OFDM block on ++ ++ { ++ // 2. set CCK test mode off, set to CCK normal mode ++ write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, bDisable); ++ // 3. turn on scramble setting ++ write_bbreg(pAdapter, rCCK0_System, bCCKScramble, bEnable); ++ } ++ // 4. Turn On Single Carrier Tx and turn off the other test modes. ++ write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bDisable); ++ write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bEnable); ++ write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable); ++#ifdef CONFIG_RTL8192C ++ // 5. Disable TX power saving at STF & LLTF ++ write_bbreg(pAdapter, rOFDM1_LSTF, BIT22, 1); ++#endif ++ } ++ else// Stop Single Carrier. ++ { ++ RT_TRACE(_module_mp_,_drv_alert_, ("SetSingleCarrierTx: test stop\n")); ++ ++ // Turn off all test modes. ++ write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bDisable); ++ write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bDisable); ++ write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable); ++#ifdef CONFIG_RTL8192C ++ // Cancel disable TX power saving at STF&LLTF ++ write_bbreg(pAdapter, rOFDM1_LSTF, BIT22, 0); ++#endif ++ //Delay 10 ms //delay_ms(10); ++ rtw_msleep_os(10); ++ ++ //BB Reset ++ write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x0); ++ write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x1); ++ } ++} ++ ++ ++void Hal_SetSingleToneTx(PADAPTER pAdapter, u8 bStart) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); ++ BOOLEAN is92C = IS_92C_SERIAL(pHalData->VersionID); ++ ++ u8 rfPath; ++ ++ switch (pAdapter->mppriv.antenna_tx) ++ { ++ case ANTENNA_A: ++ default: ++ rfPath = RF_PATH_A; ++ break; ++ case ANTENNA_B: ++ rfPath = RF_PATH_B; ++ break; ++ case ANTENNA_C: ++ rfPath = RF_PATH_C; ++ break; ++ } ++ ++ pAdapter->mppriv.MptCtx.bSingleTone = bStart; ++ if (bStart)// Start Single Tone. ++ { ++ RT_TRACE(_module_mp_,_drv_alert_, ("SetSingleToneTx: test start\n")); ++ write_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn, 0x0); ++ write_bbreg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 0x0); ++ ++ if (is92C) ++ { ++ _write_rfreg(pAdapter, RF_PATH_A, 0x21, BIT19, 0x01); ++ rtw_usleep_os(100); ++ if (rfPath == RF_PATH_A) ++ write_rfreg(pAdapter, RF_PATH_B, 0x00, 0x10000); // PAD all on. ++ else if (rfPath == RF_PATH_B) ++ write_rfreg(pAdapter, RF_PATH_A, 0x00, 0x10000); // PAD all on. ++ } else { ++ write_rfreg(pAdapter, rfPath, 0x21, 0xd4000); ++ rtw_usleep_os(100); ++ } ++ ++ write_rfreg(pAdapter, rfPath, 0x00, 0x2001f); // PAD all on. ++ rtw_usleep_os(100); ++ } ++ else// Stop Single Tone. ++ { ++ RT_TRACE(_module_mp_,_drv_alert_, ("SetSingleToneTx: test stop\n")); ++ write_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn, 0x1); ++ write_bbreg(pAdapter, rFPGA0_RFMOD, bOFDMEn, 0x1); ++ ++ if (is92C) { ++ _write_rfreg(pAdapter, RF_PATH_A, 0x21, BIT19, 0x00); ++ rtw_usleep_os(100); ++ write_rfreg(pAdapter, RF_PATH_A, 0x00, 0x32d75); // PAD all on. ++ write_rfreg(pAdapter, RF_PATH_B, 0x00, 0x32d75); // PAD all on. ++ rtw_usleep_os(100); ++ } else { ++ write_rfreg(pAdapter, rfPath, 0x21, 0x54000); ++ rtw_usleep_os(100); ++ ++ write_rfreg(pAdapter, rfPath, 0x00, 0x30000); // PAD all on. ++ rtw_usleep_os(100); ++ } ++ } ++ ++} ++ ++ ++void Hal_SetCarrierSuppressionTx(PADAPTER pAdapter, u8 bStart) ++{ ++ pAdapter->mppriv.MptCtx.bCarrierSuppression = bStart; ++ if (bStart) // Start Carrier Suppression. ++ { ++ RT_TRACE(_module_mp_,_drv_alert_, ("SetCarrierSuppressionTx: test start\n")); ++ //if(pMgntInfo->dot11CurrentWirelessMode == WIRELESS_MODE_B) ++ if (pAdapter->mppriv.rateidx <= MPT_RATE_11M) ++ { ++ // 1. if CCK block on? ++ if(!read_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn)) ++ write_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn, bEnable);//set CCK block on ++ ++ //Turn Off All Test Mode ++ write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bDisable); ++ write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bDisable); ++ write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable); ++ ++ write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x2); //transmit mode ++ write_bbreg(pAdapter, rCCK0_System, bCCKScramble, 0x0); //turn off scramble setting ++ ++ //Set CCK Tx Test Rate ++ //PHY_SetBBReg(pAdapter, rCCK0_System, bCCKTxRate, pMgntInfo->ForcedDataRate); ++ write_bbreg(pAdapter, rCCK0_System, bCCKTxRate, 0x0); //Set FTxRate to 1Mbps ++ } ++ } ++ else// Stop Carrier Suppression. ++ { ++ RT_TRACE(_module_mp_,_drv_alert_, ("SetCarrierSuppressionTx: test stop\n")); ++ //if(pMgntInfo->dot11CurrentWirelessMode == WIRELESS_MODE_B) ++ if (pAdapter->mppriv.rateidx <= MPT_RATE_11M ) { ++ write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x0); //normal mode ++ write_bbreg(pAdapter, rCCK0_System, bCCKScramble, 0x1); //turn on scramble setting ++ ++ //BB Reset ++ write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x0); ++ write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x1); ++ } ++ } ++ //DbgPrint("\n MPT_ProSetCarrierSupp() is finished. \n"); ++} ++ ++void Hal_SetCCKContinuousTx(PADAPTER pAdapter, u8 bStart) ++{ ++ u32 cckrate; ++ ++ if (bStart) ++ { ++ RT_TRACE(_module_mp_, _drv_alert_, ++ ("SetCCKContinuousTx: test start\n")); ++ ++ // 1. if CCK block on? ++ if(!read_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn)) ++ write_bbreg(pAdapter, rFPGA0_RFMOD, bCCKEn, bEnable);//set CCK block on ++ ++ //Turn Off All Test Mode ++ write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bDisable); ++ write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bDisable); ++ write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable); ++ //Set CCK Tx Test Rate ++ #if 0 ++ switch(pAdapter->mppriv.rateidx) ++ { ++ case 2: ++ cckrate = 0; ++ break; ++ case 4: ++ cckrate = 1; ++ break; ++ case 11: ++ cckrate = 2; ++ break; ++ case 22: ++ cckrate = 3; ++ break; ++ default: ++ cckrate = 0; ++ break; ++ } ++ #else ++ cckrate = pAdapter->mppriv.rateidx; ++ #endif ++ write_bbreg(pAdapter, rCCK0_System, bCCKTxRate, cckrate); ++ write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x2); //transmit mode ++ write_bbreg(pAdapter, rCCK0_System, bCCKScramble, bEnable); //turn on scramble setting ++ ++#ifdef CONFIG_RTL8192C ++ // Patch for CCK 11M waveform ++ if (cckrate == MPT_RATE_1M) ++ write_bbreg(pAdapter, 0xA71, BIT(6), bDisable); ++ else ++ write_bbreg(pAdapter, 0xA71, BIT(6), bEnable); ++#endif ++ ++ } ++ else { ++ RT_TRACE(_module_mp_, _drv_info_, ++ ("SetCCKContinuousTx: test stop\n")); ++ ++ write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, 0x0); //normal mode ++ write_bbreg(pAdapter, rCCK0_System, bCCKScramble, bEnable); //turn on scramble setting ++ ++ //BB Reset ++ write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x0); ++ write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x1); ++ } ++ ++ pAdapter->mppriv.MptCtx.bCckContTx = bStart; ++ pAdapter->mppriv.MptCtx.bOfdmContTx = _FALSE; ++}/* mpt_StartCckContTx */ ++ ++void Hal_SetOFDMContinuousTx(PADAPTER pAdapter, u8 bStart) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); ++ ++ if (bStart) { ++ RT_TRACE(_module_mp_, _drv_info_, ("SetOFDMContinuousTx: test start\n")); ++ // 1. if OFDM block on? ++ if(!read_bbreg(pAdapter, rFPGA0_RFMOD, bOFDMEn)) ++ write_bbreg(pAdapter, rFPGA0_RFMOD, bOFDMEn, bEnable);//set OFDM block on ++ { ++ ++ // 2. set CCK test mode off, set to CCK normal mode ++ write_bbreg(pAdapter, rCCK0_System, bCCKBBMode, bDisable); ++ ++ // 3. turn on scramble setting ++ write_bbreg(pAdapter, rCCK0_System, bCCKScramble, bEnable); ++ } ++ // 4. Turn On Continue Tx and turn off the other test modes. ++ write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bEnable); ++ write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bDisable); ++ write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable); ++ } else { ++ RT_TRACE(_module_mp_,_drv_info_, ("SetOFDMContinuousTx: test stop\n")); ++ write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMContinueTx, bDisable); ++ write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleCarrier, bDisable); ++ write_bbreg(pAdapter, rOFDM1_LSTF, bOFDMSingleTone, bDisable); ++ //Delay 10 ms ++ rtw_msleep_os(10); ++ //BB Reset ++ write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x0); ++ write_bbreg(pAdapter, rPMAC_Reset, bBBResetB, 0x1); ++ } ++ ++ pAdapter->mppriv.MptCtx.bCckContTx = _FALSE; ++ pAdapter->mppriv.MptCtx.bOfdmContTx = bStart; ++}/* mpt_StartOfdmContTx */ ++ ++void Hal_SetContinuousTx(PADAPTER pAdapter, u8 bStart) ++{ ++#if 0 ++ // ADC turn off [bit24-21] adc port0 ~ port1 ++ if (bStart) { ++ write_bbreg(pAdapter, rRx_Wait_CCCA, read_bbreg(pAdapter, rRx_Wait_CCCA) & 0xFE1FFFFF); ++ rtw_usleep_os(100); ++ } ++#endif ++ RT_TRACE(_module_mp_, _drv_info_, ++ ("SetContinuousTx: rate:%d\n", pAdapter->mppriv.rateidx)); ++ ++ pAdapter->mppriv.MptCtx.bStartContTx = bStart; ++ if (pAdapter->mppriv.rateidx <= MPT_RATE_11M) ++ { ++ Hal_SetCCKContinuousTx(pAdapter, bStart); ++ } ++ else if ((pAdapter->mppriv.rateidx >= MPT_RATE_6M) && ++ (pAdapter->mppriv.rateidx <= MPT_RATE_MCS15)) ++ { ++ Hal_SetOFDMContinuousTx(pAdapter, bStart); ++ } ++#if 0 ++ // ADC turn on [bit24-21] adc port0 ~ port1 ++ if (!bStart) { ++ write_bbreg(pAdapter, rRx_Wait_CCCA, read_bbreg(pAdapter, rRx_Wait_CCCA) | 0x01E00000); ++ } ++#endif ++} ++ ++#endif // CONFIG_MP_INCLUDE +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/hal/rtl8192c/rtl8192c_phycfg.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/hal/rtl8192c/rtl8192c_phycfg.c 2013-07-26 19:36:05.000000000 +0000 +@@ -0,0 +1,5583 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ++******************************************************************************/ ++/****************************************************************************** ++ ++ Module: rtl8192c_phycfg.c ++ ++ Note: Merge 92SE/SU PHY config as below ++ 1. BB register R/W API ++ 2. RF register R/W API ++ 3. Initial BB/RF/MAC config by reading BB/MAC/RF txt. ++ 3. Power setting API ++ 4. Channel switch API ++ 5. Initial gain switch API. ++ 6. Other BB/MAC/RF API. ++ ++ Function: PHY: Extern function, phy: local function ++ ++ Export: PHY_FunctionName ++ ++ Abbrev: NONE ++ ++ History: ++ Data Who Remark ++ 08/08/2008 MHC 1. Port from 9x series phycfg.c ++ 2. Reorganize code arch and ad description. ++ 3. Collect similar function. ++ 4. Seperate extern/local API. ++ 08/12/2008 MHC We must merge or move USB PHY relative function later. ++ 10/07/2008 MHC Add IQ calibration for PHY.(Only 1T2R mode now!!!) ++ 11/06/2008 MHC Add TX Power index PG file to config in 0xExx register ++ area to map with EEPROM/EFUSE tx pwr index. ++ ++******************************************************************************/ ++#define _HAL_8192C_PHYCFG_C_ ++ ++#include ++#include ++#include ++#include ++ ++#ifdef CONFIG_IOL ++#include ++#endif ++ ++#include ++ ++ ++/*---------------------------Define Local Constant---------------------------*/ ++/* Channel switch:The size of command tables for switch channel*/ ++#define MAX_PRECMD_CNT 16 ++#define MAX_RFDEPENDCMD_CNT 16 ++#define MAX_POSTCMD_CNT 16 ++ ++#define MAX_DOZE_WAITING_TIMES_9x 64 ++ ++/*---------------------------Define Local Constant---------------------------*/ ++ ++ ++/*------------------------Define global variable-----------------------------*/ ++ ++/*------------------------Define local variable------------------------------*/ ++ ++ ++/*--------------------Define export function prototype-----------------------*/ ++// Please refer to header file ++/*--------------------Define export function prototype-----------------------*/ ++ ++/*----------------------------Function Body----------------------------------*/ ++// ++// 1. BB register R/W API ++// ++ ++/** ++* Function: phy_CalculateBitShift ++* ++* OverView: Get shifted position of the BitMask ++* ++* Input: ++* u4Byte BitMask, ++* ++* Output: none ++* Return: u4Byte Return the shift bit bit position of the mask ++*/ ++static u32 ++phy_CalculateBitShift( ++ u32 BitMask ++ ) ++{ ++ u32 i; ++ ++ for(i=0; i<=31; i++) ++ { ++ if ( ((BitMask>>i) & 0x1 ) == 1) ++ break; ++ } ++ ++ return (i); ++} ++ ++ ++/** ++* Function: PHY_QueryBBReg ++* ++* OverView: Read "sepcific bits" from BB register ++* ++* Input: ++* PADAPTER Adapter, ++* u4Byte RegAddr, //The target address to be readback ++* u4Byte BitMask //The target bit position in the target address ++* //to be readback ++* Output: None ++* Return: u4Byte Data //The readback register value ++* Note: This function is equal to "GetRegSetting" in PHY programming guide ++*/ ++u32 ++rtl8192c_PHY_QueryBBReg( ++ IN PADAPTER Adapter, ++ IN u32 RegAddr, ++ IN u32 BitMask ++ ) ++{ ++ u32 ReturnValue = 0, OriginalValue, BitShift; ++ u16 BBWaitCounter = 0; ++ ++#if (DISABLE_BB_RF == 1) ++ return 0; ++#endif ++ ++ //RT_TRACE(COMP_RF, DBG_TRACE, ("--->PHY_QueryBBReg(): RegAddr(%#lx), BitMask(%#lx)\n", RegAddr, BitMask)); ++ ++ OriginalValue = rtw_read32(Adapter, RegAddr); ++ BitShift = phy_CalculateBitShift(BitMask); ++ ReturnValue = (OriginalValue & BitMask) >> BitShift; ++ ++ //RTPRINT(FPHY, PHY_BBR, ("BBR MASK=0x%lx Addr[0x%lx]=0x%lx\n", BitMask, RegAddr, OriginalValue)); ++ //RT_TRACE(COMP_RF, DBG_TRACE, ("<---PHY_QueryBBReg(): RegAddr(%#lx), BitMask(%#lx), OriginalValue(%#lx)\n", RegAddr, BitMask, OriginalValue)); ++ ++ return (ReturnValue); ++ ++} ++ ++ ++/** ++* Function: PHY_SetBBReg ++* ++* OverView: Write "Specific bits" to BB register (page 8~) ++* ++* Input: ++* PADAPTER Adapter, ++* u4Byte RegAddr, //The target address to be modified ++* u4Byte BitMask //The target bit position in the target address ++* //to be modified ++* u4Byte Data //The new register value in the target bit position ++* //of the target address ++* ++* Output: None ++* Return: None ++* Note: This function is equal to "PutRegSetting" in PHY programming guide ++*/ ++ ++VOID ++rtl8192c_PHY_SetBBReg( ++ IN PADAPTER Adapter, ++ IN u32 RegAddr, ++ IN u32 BitMask, ++ IN u32 Data ++ ) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ //u16 BBWaitCounter = 0; ++ u32 OriginalValue, BitShift; ++ ++#if (DISABLE_BB_RF == 1) ++ return; ++#endif ++ ++ //RT_TRACE(COMP_RF, DBG_TRACE, ("--->PHY_SetBBReg(): RegAddr(%#lx), BitMask(%#lx), Data(%#lx)\n", RegAddr, BitMask, Data)); ++ ++ if(BitMask!= bMaskDWord){//if not "double word" write ++ OriginalValue = rtw_read32(Adapter, RegAddr); ++ BitShift = phy_CalculateBitShift(BitMask); ++ Data = ((OriginalValue & (~BitMask)) | (Data << BitShift)); ++ } ++ ++ rtw_write32(Adapter, RegAddr, Data); ++ ++ //RTPRINT(FPHY, PHY_BBW, ("BBW MASK=0x%lx Addr[0x%lx]=0x%lx\n", BitMask, RegAddr, Data)); ++ //RT_TRACE(COMP_RF, DBG_TRACE, ("<---PHY_SetBBReg(): RegAddr(%#lx), BitMask(%#lx), Data(%#lx)\n", RegAddr, BitMask, Data)); ++ ++} ++ ++ ++// ++// 2. RF register R/W API ++// ++ ++/*----------------------------------------------------------------------------- ++ * Function: phy_FwRFSerialRead() ++ * ++ * Overview: We support firmware to execute RF-R/W. ++ * ++ * Input: NONE ++ * ++ * Output: NONE ++ * ++ * Return: NONE ++ * ++ * Revised History: ++ * When Who Remark ++ * 01/21/2008 MHC Create Version 0. ++ * ++ *---------------------------------------------------------------------------*/ ++static u32 ++phy_FwRFSerialRead( ++ IN PADAPTER Adapter, ++ IN RF90_RADIO_PATH_E eRFPath, ++ IN u32 Offset ) ++{ ++ u32 retValue = 0; ++ //RT_ASSERT(FALSE,("deprecate!\n")); ++ return (retValue); ++ ++} /* phy_FwRFSerialRead */ ++ ++ ++/*----------------------------------------------------------------------------- ++ * Function: phy_FwRFSerialWrite() ++ * ++ * Overview: We support firmware to execute RF-R/W. ++ * ++ * Input: NONE ++ * ++ * Output: NONE ++ * ++ * Return: NONE ++ * ++ * Revised History: ++ * When Who Remark ++ * 01/21/2008 MHC Create Version 0. ++ * ++ *---------------------------------------------------------------------------*/ ++static VOID ++phy_FwRFSerialWrite( ++ IN PADAPTER Adapter, ++ IN RF90_RADIO_PATH_E eRFPath, ++ IN u32 Offset, ++ IN u32 Data ) ++{ ++ //RT_ASSERT(FALSE,("deprecate!\n")); ++} ++ ++ ++/** ++* Function: phy_RFSerialRead ++* ++* OverView: Read regster from RF chips ++* ++* Input: ++* PADAPTER Adapter, ++* RF90_RADIO_PATH_E eRFPath, //Radio path of A/B/C/D ++* u4Byte Offset, //The target address to be read ++* ++* Output: None ++* Return: u4Byte reback value ++* Note: Threre are three types of serial operations: ++* 1. Software serial write ++* 2. Hardware LSSI-Low Speed Serial Interface ++* 3. Hardware HSSI-High speed ++* serial write. Driver need to implement (1) and (2). ++* This function is equal to the combination of RF_ReadReg() and RFLSSIRead() ++*/ ++static u32 ++phy_RFSerialRead( ++ IN PADAPTER Adapter, ++ IN RF90_RADIO_PATH_E eRFPath, ++ IN u32 Offset ++ ) ++{ ++ u32 retValue = 0; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ BB_REGISTER_DEFINITION_T *pPhyReg = &pHalData->PHYRegDef[eRFPath]; ++ u32 NewOffset; ++ u32 tmplong,tmplong2; ++ u8 RfPiEnable=0; ++#if 0 ++ if(pHalData->RFChipID == RF_8225 && Offset > 0x24) //36 valid regs ++ return retValue; ++ if(pHalData->RFChipID == RF_8256 && Offset > 0x2D) //45 valid regs ++ return retValue; ++#endif ++ // ++ // Make sure RF register offset is correct ++ // ++ Offset &= 0x3f; ++ ++ // ++ // Switch page for 8256 RF IC ++ // ++ NewOffset = Offset; ++ ++ // 2009/06/17 MH We can not execute IO for power save or other accident mode. ++ //if(RT_CANNOT_IO(Adapter)) ++ //{ ++ // RTPRINT(FPHY, PHY_RFR, ("phy_RFSerialRead return all one\n")); ++ // return 0xFFFFFFFF; ++ //} ++ ++ // For 92S LSSI Read RFLSSIRead ++ // For RF A/B write 0x824/82c(does not work in the future) ++ // We must use 0x824 for RF A and B to execute read trigger ++ tmplong = PHY_QueryBBReg(Adapter, rFPGA0_XA_HSSIParameter2, bMaskDWord); ++ if(eRFPath == RF90_PATH_A) ++ tmplong2 = tmplong; ++ else ++ tmplong2 = PHY_QueryBBReg(Adapter, pPhyReg->rfHSSIPara2, bMaskDWord); ++ ++ tmplong2 = (tmplong2 & (~bLSSIReadAddress)) | (NewOffset<<23) | bLSSIReadEdge; //T65 RF ++ ++ PHY_SetBBReg(Adapter, rFPGA0_XA_HSSIParameter2, bMaskDWord, tmplong&(~bLSSIReadEdge)); ++ rtw_udelay_os(10);// PlatformStallExecution(10); ++ ++ PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, bMaskDWord, tmplong2); ++ rtw_udelay_os(100);//PlatformStallExecution(100); ++ ++ PHY_SetBBReg(Adapter, rFPGA0_XA_HSSIParameter2, bMaskDWord, tmplong|bLSSIReadEdge); ++ rtw_udelay_os(10);//PlatformStallExecution(10); ++ ++ if(eRFPath == RF90_PATH_A) ++ RfPiEnable = (u8)PHY_QueryBBReg(Adapter, rFPGA0_XA_HSSIParameter1, BIT8); ++ else if(eRFPath == RF90_PATH_B) ++ RfPiEnable = (u8)PHY_QueryBBReg(Adapter, rFPGA0_XB_HSSIParameter1, BIT8); ++ ++ if(RfPiEnable) ++ { // Read from BBreg8b8, 12 bits for 8190, 20bits for T65 RF ++ retValue = PHY_QueryBBReg(Adapter, pPhyReg->rfLSSIReadBackPi, bLSSIReadBackData); ++ //DBG_8192C("Readback from RF-PI : 0x%x\n", retValue); ++ } ++ else ++ { //Read from BBreg8a0, 12 bits for 8190, 20 bits for T65 RF ++ retValue = PHY_QueryBBReg(Adapter, pPhyReg->rfLSSIReadBack, bLSSIReadBackData); ++ //DBG_8192C("Readback from RF-SI : 0x%x\n", retValue); ++ } ++ //DBG_8192C("RFR-%d Addr[0x%x]=0x%x\n", eRFPath, pPhyReg->rfLSSIReadBack, retValue); ++ ++ return retValue; ++ ++} ++ ++ ++ ++/** ++* Function: phy_RFSerialWrite ++* ++* OverView: Write data to RF register (page 8~) ++* ++* Input: ++* PADAPTER Adapter, ++* RF90_RADIO_PATH_E eRFPath, //Radio path of A/B/C/D ++* u4Byte Offset, //The target address to be read ++* u4Byte Data //The new register Data in the target bit position ++* //of the target to be read ++* ++* Output: None ++* Return: None ++* Note: Threre are three types of serial operations: ++* 1. Software serial write ++* 2. Hardware LSSI-Low Speed Serial Interface ++* 3. Hardware HSSI-High speed ++* serial write. Driver need to implement (1) and (2). ++* This function is equal to the combination of RF_ReadReg() and RFLSSIRead() ++ * ++ * Note: For RF8256 only ++ * The total count of RTL8256(Zebra4) register is around 36 bit it only employs ++ * 4-bit RF address. RTL8256 uses "register mode control bit" (Reg00[12], Reg00[10]) ++ * to access register address bigger than 0xf. See "Appendix-4 in PHY Configuration ++ * programming guide" for more details. ++ * Thus, we define a sub-finction for RTL8526 register address conversion ++ * =========================================================== ++ * Register Mode RegCTL[1] RegCTL[0] Note ++ * (Reg00[12]) (Reg00[10]) ++ * =========================================================== ++ * Reg_Mode0 0 x Reg 0 ~15(0x0 ~ 0xf) ++ * ------------------------------------------------------------------ ++ * Reg_Mode1 1 0 Reg 16 ~30(0x1 ~ 0xf) ++ * ------------------------------------------------------------------ ++ * Reg_Mode2 1 1 Reg 31 ~ 45(0x1 ~ 0xf) ++ * ------------------------------------------------------------------ ++ * ++ * 2008/09/02 MH Add 92S RF definition ++ * ++ * ++ * ++*/ ++static VOID ++phy_RFSerialWrite( ++ IN PADAPTER Adapter, ++ IN RF90_RADIO_PATH_E eRFPath, ++ IN u32 Offset, ++ IN u32 Data ++ ) ++{ ++ u32 DataAndAddr = 0; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ BB_REGISTER_DEFINITION_T *pPhyReg = &pHalData->PHYRegDef[eRFPath]; ++ u32 NewOffset; ++ ++#if 0 ++ // We should check valid regs for RF_6052 case. ++ if(pHalData->RFChipID == RF_8225 && Offset > 0x24) //36 valid regs ++ return; ++ if(pHalData->RFChipID == RF_8256 && Offset > 0x2D) //45 valid regs ++ return; ++#endif ++ ++ // 2009/06/17 MH We can not execute IO for power save or other accident mode. ++ //if(RT_CANNOT_IO(Adapter)) ++ //{ ++ // RTPRINT(FPHY, PHY_RFW, ("phy_RFSerialWrite stop\n")); ++ // return; ++ //} ++ ++ Offset &= 0x3f; ++ ++ // ++ // Shadow Update ++ // ++ //PHY_RFShadowWrite(Adapter, eRFPath, Offset, Data); ++ ++ // ++ // Switch page for 8256 RF IC ++ // ++ NewOffset = Offset; ++ ++ // ++ // Put write addr in [5:0] and write data in [31:16] ++ // ++ //DataAndAddr = (Data<<16) | (NewOffset&0x3f); ++ DataAndAddr = ((NewOffset<<20) | (Data&0x000fffff)) & 0x0fffffff; // T65 RF ++ ++ // ++ // Write Operation ++ // ++ PHY_SetBBReg(Adapter, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr); ++ //RTPRINT(FPHY, PHY_RFW, ("RFW-%d Addr[0x%lx]=0x%lx\n", eRFPath, pPhyReg->rf3wireOffset, DataAndAddr)); ++ ++} ++ ++ ++/** ++* Function: PHY_QueryRFReg ++* ++* OverView: Query "Specific bits" to RF register (page 8~) ++* ++* Input: ++* PADAPTER Adapter, ++* RF90_RADIO_PATH_E eRFPath, //Radio path of A/B/C/D ++* u4Byte RegAddr, //The target address to be read ++* u4Byte BitMask //The target bit position in the target address ++* //to be read ++* ++* Output: None ++* Return: u4Byte Readback value ++* Note: This function is equal to "GetRFRegSetting" in PHY programming guide ++*/ ++u32 ++rtl8192c_PHY_QueryRFReg( ++ IN PADAPTER Adapter, ++ IN RF90_RADIO_PATH_E eRFPath, ++ IN u32 RegAddr, ++ IN u32 BitMask ++ ) ++{ ++ u32 Original_Value, Readback_Value, BitShift; ++ //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ //u8 RFWaitCounter = 0; ++ //_irqL irqL; ++ ++#if (DISABLE_BB_RF == 1) ++ return 0; ++#endif ++ ++ //RT_TRACE(COMP_RF, DBG_TRACE, ("--->PHY_QueryRFReg(): RegAddr(%#lx), eRFPath(%#x), BitMask(%#lx)\n", RegAddr, eRFPath,BitMask)); ++ ++#ifdef CONFIG_USB_HCI ++ //PlatformAcquireMutex(&pHalData->mxRFOperate); ++#else ++ //_enter_critical(&pHalData->rf_lock, &irqL); ++#endif ++ ++ ++ Original_Value = phy_RFSerialRead(Adapter, eRFPath, RegAddr); ++ ++ BitShift = phy_CalculateBitShift(BitMask); ++ Readback_Value = (Original_Value & BitMask) >> BitShift; ++ ++#ifdef CONFIG_USB_HCI ++ //PlatformReleaseMutex(&pHalData->mxRFOperate); ++#else ++ //_exit_critical(&pHalData->rf_lock, &irqL); ++#endif ++ ++ ++ //RTPRINT(FPHY, PHY_RFR, ("RFR-%d MASK=0x%lx Addr[0x%lx]=0x%lx\n", eRFPath, BitMask, RegAddr, Original_Value));//BitMask(%#lx),BitMask, ++ //RT_TRACE(COMP_RF, DBG_TRACE, ("<---PHY_QueryRFReg(): RegAddr(%#lx), eRFPath(%#x), Original_Value(%#lx)\n", ++ // RegAddr, eRFPath, Original_Value)); ++ ++ return (Readback_Value); ++} ++ ++/** ++* Function: PHY_SetRFReg ++* ++* OverView: Write "Specific bits" to RF register (page 8~) ++* ++* Input: ++* PADAPTER Adapter, ++* RF90_RADIO_PATH_E eRFPath, //Radio path of A/B/C/D ++* u4Byte RegAddr, //The target address to be modified ++* u4Byte BitMask //The target bit position in the target address ++* //to be modified ++* u4Byte Data //The new register Data in the target bit position ++* //of the target address ++* ++* Output: None ++* Return: None ++* Note: This function is equal to "PutRFRegSetting" in PHY programming guide ++*/ ++VOID ++rtl8192c_PHY_SetRFReg( ++ IN PADAPTER Adapter, ++ IN RF90_RADIO_PATH_E eRFPath, ++ IN u32 RegAddr, ++ IN u32 BitMask, ++ IN u32 Data ++ ) ++{ ++ ++ //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ //u1Byte RFWaitCounter = 0; ++ u32 Original_Value, BitShift; ++ //_irqL irqL; ++ ++#if (DISABLE_BB_RF == 1) ++ return; ++#endif ++ ++ //RT_TRACE(COMP_RF, DBG_TRACE, ("--->PHY_SetRFReg(): RegAddr(%#lx), BitMask(%#lx), Data(%#lx), eRFPath(%#x)\n", ++ // RegAddr, BitMask, Data, eRFPath)); ++ //RTPRINT(FINIT, INIT_RF, ("PHY_SetRFReg(): RegAddr(%#lx), BitMask(%#lx), Data(%#lx), eRFPath(%#x)\n", ++ // RegAddr, BitMask, Data, eRFPath)); ++ ++ ++#ifdef CONFIG_USB_HCI ++ //PlatformAcquireMutex(&pHalData->mxRFOperate); ++#else ++ //_enter_critical(&pHalData->rf_lock, &irqL); ++#endif ++ ++ ++ // RF data is 12 bits only ++ if (BitMask != bRFRegOffsetMask) ++ { ++ Original_Value = phy_RFSerialRead(Adapter, eRFPath, RegAddr); ++ BitShift = phy_CalculateBitShift(BitMask); ++ Data = ((Original_Value & (~BitMask)) | (Data<< BitShift)); ++ } ++ ++ phy_RFSerialWrite(Adapter, eRFPath, RegAddr, Data); ++ ++ ++ ++#ifdef CONFIG_USB_HCI ++ //PlatformReleaseMutex(&pHalData->mxRFOperate); ++#else ++ //_exit_critical(&pHalData->rf_lock, &irqL); ++#endif ++ ++ //PHY_QueryRFReg(Adapter,eRFPath,RegAddr,BitMask); ++ //RT_TRACE(COMP_RF, DBG_TRACE, ("<---PHY_SetRFReg(): RegAddr(%#lx), BitMask(%#lx), Data(%#lx), eRFPath(%#x)\n", ++ // RegAddr, BitMask, Data, eRFPath)); ++ ++} ++ ++ ++// ++// 3. Initial MAC/BB/RF config by reading MAC/BB/RF txt. ++// ++ ++/*----------------------------------------------------------------------------- ++ * Function: phy_ConfigMACWithParaFile() ++ * ++ * Overview: This function read BB parameters from general file format, and do register ++ * Read/Write ++ * ++ * Input: PADAPTER Adapter ++ * ps1Byte pFileName ++ * ++ * Output: NONE ++ * ++ * Return: RT_STATUS_SUCCESS: configuration file exist ++ * ++ * Note: The format of MACPHY_REG.txt is different from PHY and RF. ++ * [Register][Mask][Value] ++ *---------------------------------------------------------------------------*/ ++static int ++phy_ConfigMACWithParaFile( ++ IN PADAPTER Adapter, ++ IN u8* pFileName ++) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ ++ int rtStatus = _SUCCESS; ++ ++ return rtStatus; ++} ++ ++/*----------------------------------------------------------------------------- ++ * Function: phy_ConfigMACWithHeaderFile() ++ * ++ * Overview: This function read BB parameters from Header file we gen, and do register ++ * Read/Write ++ * ++ * Input: PADAPTER Adapter ++ * ps1Byte pFileName ++ * ++ * Output: NONE ++ * ++ * Return: RT_STATUS_SUCCESS: configuration file exist ++ * ++ * Note: The format of MACPHY_REG.txt is different from PHY and RF. ++ * [Register][Mask][Value] ++ *---------------------------------------------------------------------------*/ ++static int ++phy_ConfigMACWithHeaderFile( ++ IN PADAPTER Adapter ++) ++{ ++ u32 i = 0; ++ u32 ArrayLength = 0; ++ u32* ptrArray; ++ //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ ++ //2008.11.06 Modified by tynli. ++ //RT_TRACE(COMP_INIT, DBG_LOUD, ("Read Rtl819XMACPHY_Array\n")); ++ ArrayLength = MAC_2T_ArrayLength; ++ ptrArray = Rtl819XMAC_Array; ++ ++#ifdef CONFIG_IOL_MAC ++ if(rtw_IOL_applied(Adapter)) ++ { ++ struct xmit_frame *xmit_frame; ++ if((xmit_frame=rtw_IOL_accquire_xmit_frame(Adapter)) == NULL) ++ return _FAIL; ++ ++ for(i = 0 ;i < ArrayLength;i=i+2){ // Add by tynli for 2 column ++ rtw_IOL_append_WB_cmd(xmit_frame, ptrArray[i], (u8)ptrArray[i+1]); ++ } ++ ++ return rtw_IOL_exec_cmds_sync(Adapter, xmit_frame, 1000); ++ } ++ else ++#endif ++ { ++ for(i = 0 ;i < ArrayLength;i=i+2){ // Add by tynli for 2 column ++ rtw_write8(Adapter, ptrArray[i], (u8)ptrArray[i+1]); ++ } ++ } ++ ++ return _SUCCESS; ++ ++} ++ ++ ++/*----------------------------------------------------------------------------- ++ * Function: PHY_MACConfig8192C ++ * ++ * Overview: Condig MAC by header file or parameter file. ++ * ++ * Input: NONE ++ * ++ * Output: NONE ++ * ++ * Return: NONE ++ * ++ * Revised History: ++ * When Who Remark ++ * 08/12/2008 MHC Create Version 0. ++ * ++ *---------------------------------------------------------------------------*/ ++int ++PHY_MACConfig8192C( ++ IN PADAPTER Adapter ++ ) ++{ ++ int rtStatus = _SUCCESS; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ s8 *pszMACRegFile; ++ s8 sz88CMACRegFile[] = RTL8188C_PHY_MACREG; ++ s8 sz92CMACRegFile[] = RTL8192C_PHY_MACREG; ++ BOOLEAN isNormal = IS_NORMAL_CHIP(pHalData->VersionID); ++ BOOLEAN is92C = IS_92C_SERIAL(pHalData->VersionID); ++ ++ if(isNormal) ++ { ++ if(is92C) ++ pszMACRegFile = sz92CMACRegFile; ++ else ++ pszMACRegFile = sz88CMACRegFile; ++ } ++ else ++ { ++ //pszMACRegFile = TestMacRegFile; ++ } ++ ++ // ++ // Config MAC ++ // ++#ifdef CONFIG_EMBEDDED_FWIMG ++ rtStatus = phy_ConfigMACWithHeaderFile(Adapter); ++#else ++ ++ // Not make sure EEPROM, add later ++ //RT_TRACE(COMP_INIT, DBG_LOUD, ("Read MACREG.txt\n")); ++ rtStatus = phy_ConfigMACWithParaFile(Adapter, pszMACRegFile); ++#endif ++ ++#ifdef CONFIG_PCI_HCI ++ //this switching setting cause some 8192cu hw have redownload fw fail issue ++ //improve 2-stream TX EVM by Jenyu ++ if(isNormal && is92C) ++ rtw_write8(Adapter, REG_SPS0_CTRL+3,0x71); ++#endif ++ ++ ++ // 2010.07.13 AMPDU aggregation number 9 ++ //rtw_write16(Adapter, REG_MAX_AGGR_NUM, MAX_AGGR_NUM); ++ rtw_write8(Adapter, REG_MAX_AGGR_NUM, 0x0A); //By tynli. 2010.11.18. ++#ifdef CONFIG_USB_HCI ++ if(is92C && (BOARD_USB_DONGLE == pHalData->BoardType)) ++ rtw_write8(Adapter, 0x40,0x04); ++#endif ++ ++ return rtStatus; ++ ++} ++ ++ ++/** ++* Function: phy_InitBBRFRegisterDefinition ++* ++* OverView: Initialize Register definition offset for Radio Path A/B/C/D ++* ++* Input: ++* PADAPTER Adapter, ++* ++* Output: None ++* Return: None ++* Note: The initialization value is constant and it should never be changes ++*/ ++static VOID ++phy_InitBBRFRegisterDefinition( ++ IN PADAPTER Adapter ++) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ ++ // RF Interface Sowrtware Control ++ pHalData->PHYRegDef[RF90_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW; // 16 LSBs if read 32-bit from 0x870 ++ pHalData->PHYRegDef[RF90_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW; // 16 MSBs if read 32-bit from 0x870 (16-bit for 0x872) ++ pHalData->PHYRegDef[RF90_PATH_C].rfintfs = rFPGA0_XCD_RFInterfaceSW;// 16 LSBs if read 32-bit from 0x874 ++ pHalData->PHYRegDef[RF90_PATH_D].rfintfs = rFPGA0_XCD_RFInterfaceSW;// 16 MSBs if read 32-bit from 0x874 (16-bit for 0x876) ++ ++ // RF Interface Readback Value ++ pHalData->PHYRegDef[RF90_PATH_A].rfintfi = rFPGA0_XAB_RFInterfaceRB; // 16 LSBs if read 32-bit from 0x8E0 ++ pHalData->PHYRegDef[RF90_PATH_B].rfintfi = rFPGA0_XAB_RFInterfaceRB;// 16 MSBs if read 32-bit from 0x8E0 (16-bit for 0x8E2) ++ pHalData->PHYRegDef[RF90_PATH_C].rfintfi = rFPGA0_XCD_RFInterfaceRB;// 16 LSBs if read 32-bit from 0x8E4 ++ pHalData->PHYRegDef[RF90_PATH_D].rfintfi = rFPGA0_XCD_RFInterfaceRB;// 16 MSBs if read 32-bit from 0x8E4 (16-bit for 0x8E6) ++ ++ // RF Interface Output (and Enable) ++ pHalData->PHYRegDef[RF90_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE; // 16 LSBs if read 32-bit from 0x860 ++ pHalData->PHYRegDef[RF90_PATH_B].rfintfo = rFPGA0_XB_RFInterfaceOE; // 16 LSBs if read 32-bit from 0x864 ++ ++ // RF Interface (Output and) Enable ++ pHalData->PHYRegDef[RF90_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE; // 16 MSBs if read 32-bit from 0x860 (16-bit for 0x862) ++ pHalData->PHYRegDef[RF90_PATH_B].rfintfe = rFPGA0_XB_RFInterfaceOE; // 16 MSBs if read 32-bit from 0x864 (16-bit for 0x866) ++ ++ //Addr of LSSI. Wirte RF register by driver ++ pHalData->PHYRegDef[RF90_PATH_A].rf3wireOffset = rFPGA0_XA_LSSIParameter; //LSSI Parameter ++ pHalData->PHYRegDef[RF90_PATH_B].rf3wireOffset = rFPGA0_XB_LSSIParameter; ++ ++ // RF parameter ++ pHalData->PHYRegDef[RF90_PATH_A].rfLSSI_Select = rFPGA0_XAB_RFParameter; //BB Band Select ++ pHalData->PHYRegDef[RF90_PATH_B].rfLSSI_Select = rFPGA0_XAB_RFParameter; ++ pHalData->PHYRegDef[RF90_PATH_C].rfLSSI_Select = rFPGA0_XCD_RFParameter; ++ pHalData->PHYRegDef[RF90_PATH_D].rfLSSI_Select = rFPGA0_XCD_RFParameter; ++ ++ // Tx AGC Gain Stage (same for all path. Should we remove this?) ++ pHalData->PHYRegDef[RF90_PATH_A].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage ++ pHalData->PHYRegDef[RF90_PATH_B].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage ++ pHalData->PHYRegDef[RF90_PATH_C].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage ++ pHalData->PHYRegDef[RF90_PATH_D].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage ++ ++ // Tranceiver A~D HSSI Parameter-1 ++ pHalData->PHYRegDef[RF90_PATH_A].rfHSSIPara1 = rFPGA0_XA_HSSIParameter1; //wire control parameter1 ++ pHalData->PHYRegDef[RF90_PATH_B].rfHSSIPara1 = rFPGA0_XB_HSSIParameter1; //wire control parameter1 ++ ++ // Tranceiver A~D HSSI Parameter-2 ++ pHalData->PHYRegDef[RF90_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2; //wire control parameter2 ++ pHalData->PHYRegDef[RF90_PATH_B].rfHSSIPara2 = rFPGA0_XB_HSSIParameter2; //wire control parameter2 ++ ++ // RF switch Control ++ pHalData->PHYRegDef[RF90_PATH_A].rfSwitchControl = rFPGA0_XAB_SwitchControl; //TR/Ant switch control ++ pHalData->PHYRegDef[RF90_PATH_B].rfSwitchControl = rFPGA0_XAB_SwitchControl; ++ pHalData->PHYRegDef[RF90_PATH_C].rfSwitchControl = rFPGA0_XCD_SwitchControl; ++ pHalData->PHYRegDef[RF90_PATH_D].rfSwitchControl = rFPGA0_XCD_SwitchControl; ++ ++ // AGC control 1 ++ pHalData->PHYRegDef[RF90_PATH_A].rfAGCControl1 = rOFDM0_XAAGCCore1; ++ pHalData->PHYRegDef[RF90_PATH_B].rfAGCControl1 = rOFDM0_XBAGCCore1; ++ pHalData->PHYRegDef[RF90_PATH_C].rfAGCControl1 = rOFDM0_XCAGCCore1; ++ pHalData->PHYRegDef[RF90_PATH_D].rfAGCControl1 = rOFDM0_XDAGCCore1; ++ ++ // AGC control 2 ++ pHalData->PHYRegDef[RF90_PATH_A].rfAGCControl2 = rOFDM0_XAAGCCore2; ++ pHalData->PHYRegDef[RF90_PATH_B].rfAGCControl2 = rOFDM0_XBAGCCore2; ++ pHalData->PHYRegDef[RF90_PATH_C].rfAGCControl2 = rOFDM0_XCAGCCore2; ++ pHalData->PHYRegDef[RF90_PATH_D].rfAGCControl2 = rOFDM0_XDAGCCore2; ++ ++ // RX AFE control 1 ++ pHalData->PHYRegDef[RF90_PATH_A].rfRxIQImbalance = rOFDM0_XARxIQImbalance; ++ pHalData->PHYRegDef[RF90_PATH_B].rfRxIQImbalance = rOFDM0_XBRxIQImbalance; ++ pHalData->PHYRegDef[RF90_PATH_C].rfRxIQImbalance = rOFDM0_XCRxIQImbalance; ++ pHalData->PHYRegDef[RF90_PATH_D].rfRxIQImbalance = rOFDM0_XDRxIQImbalance; ++ ++ // RX AFE control 1 ++ pHalData->PHYRegDef[RF90_PATH_A].rfRxAFE = rOFDM0_XARxAFE; ++ pHalData->PHYRegDef[RF90_PATH_B].rfRxAFE = rOFDM0_XBRxAFE; ++ pHalData->PHYRegDef[RF90_PATH_C].rfRxAFE = rOFDM0_XCRxAFE; ++ pHalData->PHYRegDef[RF90_PATH_D].rfRxAFE = rOFDM0_XDRxAFE; ++ ++ // Tx AFE control 1 ++ pHalData->PHYRegDef[RF90_PATH_A].rfTxIQImbalance = rOFDM0_XATxIQImbalance; ++ pHalData->PHYRegDef[RF90_PATH_B].rfTxIQImbalance = rOFDM0_XBTxIQImbalance; ++ pHalData->PHYRegDef[RF90_PATH_C].rfTxIQImbalance = rOFDM0_XCTxIQImbalance; ++ pHalData->PHYRegDef[RF90_PATH_D].rfTxIQImbalance = rOFDM0_XDTxIQImbalance; ++ ++ // Tx AFE control 2 ++ pHalData->PHYRegDef[RF90_PATH_A].rfTxAFE = rOFDM0_XATxAFE; ++ pHalData->PHYRegDef[RF90_PATH_B].rfTxAFE = rOFDM0_XBTxAFE; ++ pHalData->PHYRegDef[RF90_PATH_C].rfTxAFE = rOFDM0_XCTxAFE; ++ pHalData->PHYRegDef[RF90_PATH_D].rfTxAFE = rOFDM0_XDTxAFE; ++ ++ // Tranceiver LSSI Readback SI mode ++ pHalData->PHYRegDef[RF90_PATH_A].rfLSSIReadBack = rFPGA0_XA_LSSIReadBack; ++ pHalData->PHYRegDef[RF90_PATH_B].rfLSSIReadBack = rFPGA0_XB_LSSIReadBack; ++ pHalData->PHYRegDef[RF90_PATH_C].rfLSSIReadBack = rFPGA0_XC_LSSIReadBack; ++ pHalData->PHYRegDef[RF90_PATH_D].rfLSSIReadBack = rFPGA0_XD_LSSIReadBack; ++ ++ // Tranceiver LSSI Readback PI mode ++ pHalData->PHYRegDef[RF90_PATH_A].rfLSSIReadBackPi = TransceiverA_HSPI_Readback; ++ pHalData->PHYRegDef[RF90_PATH_B].rfLSSIReadBackPi = TransceiverB_HSPI_Readback; ++ //pHalData->PHYRegDef[RF90_PATH_C].rfLSSIReadBackPi = rFPGA0_XC_LSSIReadBack; ++ //pHalData->PHYRegDef[RF90_PATH_D].rfLSSIReadBackPi = rFPGA0_XD_LSSIReadBack; ++ ++} ++ ++ ++/*----------------------------------------------------------------------------- ++ * Function: phy_ConfigBBWithParaFile() ++ * ++ * Overview: This function read BB parameters from general file format, and do register ++ * Read/Write ++ * ++ * Input: PADAPTER Adapter ++ * ps1Byte pFileName ++ * ++ * Output: NONE ++ * ++ * Return: RT_STATUS_SUCCESS: configuration file exist ++ * 2008/11/06 MH For 92S we do not support silent reset now. Disable ++ * parameter file compare!!!!!!?? ++ * ++ *---------------------------------------------------------------------------*/ ++static int ++phy_ConfigBBWithParaFile( ++ IN PADAPTER Adapter, ++ IN u8* pFileName ++) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ ++ int rtStatus = _SUCCESS; ++ ++ return rtStatus; ++} ++ ++ ++ ++//**************************************** ++// The following is for High Power PA ++//**************************************** ++VOID ++phy_ConfigBBExternalPA( ++ IN PADAPTER Adapter ++) ++{ ++#ifdef CONFIG_USB_HCI ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ u16 i=0; ++ u32 temp=0; ++ ++ if(!pHalData->ExternalPA) ++ { ++ return; ++ } ++ ++ // 2010/10/19 MH According to Jenyu/EEChou 's opinion, we need not to execute the ++ // same code as SU. It is already updated in PHY_REG_1T_HP.txt. ++#if 0 ++ PHY_SetBBReg(Adapter, 0xee8, BIT28, 1); ++ temp = PHY_QueryBBReg(Adapter, 0x860, bMaskDWord); ++ temp |= (BIT26|BIT21|BIT10|BIT5); ++ PHY_SetBBReg(Adapter, 0x860, bMaskDWord, temp); ++ PHY_SetBBReg(Adapter, 0x870, BIT10, 0); ++ PHY_SetBBReg(Adapter, 0xc80, bMaskDWord, 0x20000080); ++ PHY_SetBBReg(Adapter, 0xc88, bMaskDWord, 0x40000100); ++#endif ++ ++#endif ++} ++ ++/*----------------------------------------------------------------------------- ++ * Function: phy_ConfigBBWithHeaderFile() ++ * ++ * Overview: This function read BB parameters from general file format, and do register ++ * Read/Write ++ * ++ * Input: PADAPTER Adapter ++ * u1Byte ConfigType 0 => PHY_CONFIG ++ * 1 =>AGC_TAB ++ * ++ * Output: NONE ++ * ++ * Return: RT_STATUS_SUCCESS: configuration file exist ++ * ++ *---------------------------------------------------------------------------*/ ++static int ++phy_ConfigBBWithHeaderFile( ++ IN PADAPTER Adapter, ++ IN u8 ConfigType ++) ++{ ++ int i; ++ u32* Rtl819XPHY_REGArray_Table; ++ u32* Rtl819XAGCTAB_Array_Table; ++ u16 PHY_REGArrayLen, AGCTAB_ArrayLen; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ int ret = _SUCCESS; ++ ++ // ++ // 2009.11.24. Modified by tynli. ++ // ++ if(IS_92C_SERIAL(pHalData->VersionID)) ++ { ++ if(IS_NORMAL_CHIP(pHalData->VersionID)) ++ { ++ AGCTAB_ArrayLen = AGCTAB_2TArrayLength; ++ Rtl819XAGCTAB_Array_Table = Rtl819XAGCTAB_2TArray; ++ PHY_REGArrayLen = PHY_REG_2TArrayLength; ++ Rtl819XPHY_REGArray_Table = Rtl819XPHY_REG_2TArray; ++#ifdef CONFIG_USB_HCI ++ if(pHalData->BoardType == BOARD_MINICARD ) ++ { ++ PHY_REGArrayLen = PHY_REG_2T_mCardArrayLength; ++ Rtl819XPHY_REGArray_Table = Rtl819XPHY_REG_2T_mCardArray; ++ } ++#endif ++ } ++ else ++ { ++ DBG_8192C(" ===> phy_ConfigBBWithHeaderFile(): do not support test chip\n"); ++ ret = _FAIL; ++ goto exit; ++ } ++ } ++ else ++ { ++ if(IS_NORMAL_CHIP(pHalData->VersionID)) ++ { ++ AGCTAB_ArrayLen = AGCTAB_1TArrayLength; ++ Rtl819XAGCTAB_Array_Table = Rtl819XAGCTAB_1TArray; ++ PHY_REGArrayLen = PHY_REG_1TArrayLength; ++ Rtl819XPHY_REGArray_Table = Rtl819XPHY_REG_1TArray; ++#ifdef CONFIG_USB_HCI ++ if(pHalData->BoardType == BOARD_MINICARD ) ++ { ++ PHY_REGArrayLen = PHY_REG_1T_mCardArrayLength; ++ Rtl819XPHY_REGArray_Table = Rtl819XPHY_REG_1T_mCardArray; ++ } ++ else if(pHalData->BoardType == BOARD_USB_High_PA) ++ { ++ AGCTAB_ArrayLen = AGCTAB_1T_HPArrayLength; ++ Rtl819XAGCTAB_Array_Table = Rtl819XAGCTAB_1T_HPArray; ++ PHY_REGArrayLen = PHY_REG_1T_HPArrayLength; ++ Rtl819XPHY_REGArray_Table = Rtl819XPHY_REG_1T_HPArray; ++ } ++#endif ++ } ++ else ++ { ++ DBG_8192C(" ===> phy_ConfigBBWithHeaderFile(): do not support test chip\n"); ++ ret = _FAIL; ++ goto exit; ++ } ++ } ++ ++ if(ConfigType == BaseBand_Config_PHY_REG) ++ { ++ #ifdef CONFIG_IOL_BB_PHY_REG ++ if(rtw_IOL_applied(Adapter)) ++ { ++ struct xmit_frame *xmit_frame; ++ u32 tmp_value; ++ ++ if((xmit_frame=rtw_IOL_accquire_xmit_frame(Adapter)) == NULL) { ++ ret = _FAIL; ++ goto exit; ++ } ++ ++ for(i=0;iMCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][0] = Data; ++ //RT_TRACE(COMP_INIT, DBG_TRACE, ("MCSTxPowerLevelOriginalOffset[%d][0] = 0x%lx\n", pHalData->pwrGroupCnt, ++ // pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][0])); ++ } ++ if(RegAddr == rTxAGC_A_Rate54_24) ++ { ++ pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][1] = Data; ++ //RT_TRACE(COMP_INIT, DBG_TRACE, ("MCSTxPowerLevelOriginalOffset[%d][1] = 0x%lx\n", pHalData->pwrGroupCnt, ++ // pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][1])); ++ } ++ if(RegAddr == rTxAGC_A_CCK1_Mcs32) ++ { ++ pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][6] = Data; ++ //RT_TRACE(COMP_INIT, DBG_TRACE, ("MCSTxPowerLevelOriginalOffset[%d][6] = 0x%lx\n", pHalData->pwrGroupCnt, ++ // pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][6])); ++ } ++ if(RegAddr == rTxAGC_B_CCK11_A_CCK2_11 && BitMask == 0xffffff00) ++ { ++ pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][7] = Data; ++ //RT_TRACE(COMP_INIT, DBG_TRACE, ("MCSTxPowerLevelOriginalOffset[%d][7] = 0x%lx\n", pHalData->pwrGroupCnt, ++ // pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][7])); ++ } ++ if(RegAddr == rTxAGC_A_Mcs03_Mcs00) ++ { ++ pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][2] = Data; ++ //RT_TRACE(COMP_INIT, DBG_TRACE, ("MCSTxPowerLevelOriginalOffset[%d][2] = 0x%lx\n", pHalData->pwrGroupCnt, ++ // pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][2])); ++ } ++ if(RegAddr == rTxAGC_A_Mcs07_Mcs04) ++ { ++ pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][3] = Data; ++ //RT_TRACE(COMP_INIT, DBG_TRACE, ("MCSTxPowerLevelOriginalOffset[%d][3] = 0x%lx\n", pHalData->pwrGroupCnt, ++ // pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][3])); ++ } ++ if(RegAddr == rTxAGC_A_Mcs11_Mcs08) ++ { ++ pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][4] = Data; ++ //RT_TRACE(COMP_INIT, DBG_TRACE, ("MCSTxPowerLevelOriginalOffset[%d][4] = 0x%lx\n", pHalData->pwrGroupCnt, ++ // pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][4])); ++ } ++ if(RegAddr == rTxAGC_A_Mcs15_Mcs12) ++ { ++ pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][5] = Data; ++ //RT_TRACE(COMP_INIT, DBG_TRACE, ("MCSTxPowerLevelOriginalOffset[%d][5] = 0x%lx\n", pHalData->pwrGroupCnt, ++ // pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][5])); ++ } ++ if(RegAddr == rTxAGC_B_Rate18_06) ++ { ++ pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][8] = Data; ++ //RT_TRACE(COMP_INIT, DBG_TRACE, ("MCSTxPowerLevelOriginalOffset[%d][8] = 0x%lx\n", pHalData->pwrGroupCnt, ++ // pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][8])); ++ } ++ if(RegAddr == rTxAGC_B_Rate54_24) ++ { ++ pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][9] = Data; ++ //RT_TRACE(COMP_INIT, DBG_TRACE, ("MCSTxPowerLevelOriginalOffset[%d][9] = 0x%lx\n", pHalData->pwrGroupCnt, ++ // pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][9])); ++ } ++ if(RegAddr == rTxAGC_B_CCK1_55_Mcs32) ++ { ++ pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][14] = Data; ++ //RT_TRACE(COMP_INIT, DBG_TRACE, ("MCSTxPowerLevelOriginalOffset[%d][14] = 0x%lx\n", pHalData->pwrGroupCnt, ++ // pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][14])); ++ } ++ if(RegAddr == rTxAGC_B_CCK11_A_CCK2_11 && BitMask == 0x000000ff) ++ { ++ pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][15] = Data; ++ //RT_TRACE(COMP_INIT, DBG_TRACE, ("MCSTxPowerLevelOriginalOffset[%d][15] = 0x%lx\n", pHalData->pwrGroupCnt, ++ // pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][15])); ++ } ++ if(RegAddr == rTxAGC_B_Mcs03_Mcs00) ++ { ++ pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][10] = Data; ++ //RT_TRACE(COMP_INIT, DBG_TRACE, ("MCSTxPowerLevelOriginalOffset[%d][10] = 0x%lx\n", pHalData->pwrGroupCnt, ++ // pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][10])); ++ } ++ if(RegAddr == rTxAGC_B_Mcs07_Mcs04) ++ { ++ pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][11] = Data; ++ //RT_TRACE(COMP_INIT, DBG_TRACE, ("MCSTxPowerLevelOriginalOffset[%d][11] = 0x%lx\n", pHalData->pwrGroupCnt, ++ // pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][11])); ++ } ++ if(RegAddr == rTxAGC_B_Mcs11_Mcs08) ++ { ++ pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][12] = Data; ++ //RT_TRACE(COMP_INIT, DBG_TRACE, ("MCSTxPowerLevelOriginalOffset[%d][12] = 0x%lx\n", pHalData->pwrGroupCnt, ++ // pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][12])); ++ } ++ if(RegAddr == rTxAGC_B_Mcs15_Mcs12) ++ { ++ pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][13] = Data; ++ //RT_TRACE(COMP_INIT, DBG_TRACE, ("MCSTxPowerLevelOriginalOffset[%d][13] = 0x%lx\n", pHalData->pwrGroupCnt, ++ // pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][13])); ++ pHalData->pwrGroupCnt++; ++ } ++} ++/*----------------------------------------------------------------------------- ++ * Function: phy_ConfigBBWithPgParaFile ++ * ++ * Overview: ++ * ++ * Input: NONE ++ * ++ * Output: NONE ++ * ++ * Return: NONE ++ * ++ * Revised History: ++ * When Who Remark ++ * 11/06/2008 MHC Create Version 0. ++ * 2009/07/29 tynli (porting from 92SE branch)2009/03/11 Add copy parameter file to buffer for silent reset ++ *---------------------------------------------------------------------------*/ ++static int ++phy_ConfigBBWithPgParaFile( ++ IN PADAPTER Adapter, ++ IN u8* pFileName) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ ++ int rtStatus = _SUCCESS; ++ ++ ++ return rtStatus; ++ ++} /* phy_ConfigBBWithPgParaFile */ ++ ++ ++/*----------------------------------------------------------------------------- ++ * Function: phy_ConfigBBWithPgHeaderFile ++ * ++ * Overview: Config PHY_REG_PG array ++ * ++ * Input: NONE ++ * ++ * Output: NONE ++ * ++ * Return: NONE ++ * ++ * Revised History: ++ * When Who Remark ++ * 11/06/2008 MHC Add later!!!!!!.. Please modify for new files!!!! ++ * 11/10/2008 tynli Modify to mew files. ++ *---------------------------------------------------------------------------*/ ++static int ++phy_ConfigBBWithPgHeaderFile( ++ IN PADAPTER Adapter, ++ IN u8 ConfigType) ++{ ++ int i; ++ u32* Rtl819XPHY_REGArray_Table_PG; ++ u16 PHY_REGArrayPGLen; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ ++ // Default: pHalData->RF_Type = RF_2T2R. ++ if(IS_NORMAL_CHIP(pHalData->VersionID)) ++ { ++ PHY_REGArrayPGLen = PHY_REG_Array_PGLength; ++ Rtl819XPHY_REGArray_Table_PG = Rtl819XPHY_REG_Array_PG; ++ ++#ifdef CONFIG_USB_HCI ++// 2010/10/19 Chiyoko According to Alex/Willson opinion, VAU/dongle can share the same PHY_REG_PG.txt ++/* ++ if(pHalData->BoardType == BOARD_MINICARD ) ++ { ++ PHY_REGArrayPGLen = PHY_REG_Array_PG_mCardLength; ++ Rtl819XPHY_REGArray_Table_PG = Rtl819XPHY_REG_Array_PG_mCard; ++ } ++ else */if(pHalData->BoardType ==BOARD_USB_High_PA ) ++ { ++ PHY_REGArrayPGLen = PHY_REG_Array_PG_HPLength; ++ Rtl819XPHY_REGArray_Table_PG = Rtl819XPHY_REG_Array_PG_HP; ++ } ++#endif ++ } ++ else ++ { ++ DBG_8192C(" ===> phy_ConfigBBWithPgHeaderFile(): do not support test chip\n"); ++ return _FAIL; ++ } ++ ++ if(ConfigType == BaseBand_Config_PHY_REG) ++ { ++ for(i=0;iBufOfLines), ++ MAX_LINES_HWCONFIG_TXT, ++ MAX_BYTES_LINE_HWCONFIG_TXT, ++ &nLinesRead ++ ); ++ if(rtStatus == RT_STATUS_SUCCESS) ++ { ++ PlatformMoveMemory(pHalData->BufOfLines6, pHalData->BufOfLines, nLinesRead*MAX_BYTES_LINE_HWCONFIG_TXT); ++ pHalData->nLinesRead6 = nLinesRead; ++ } ++ else ++ { ++ // Temporarily skip PHY_REG_MP.txt if file does not exist. ++ pHalData->nLinesRead6 = 0; ++ RT_TRACE(COMP_INIT, DBG_LOUD, ("No matched file \r\n")); ++ return RT_STATUS_SUCCESS; ++ } ++ } ++ else ++ { ++ PlatformMoveMemory(pHalData->BufOfLines, pHalData->BufOfLines6, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT); ++ nLinesRead = pHalData->nLinesRead6; ++ rtStatus = RT_STATUS_SUCCESS; ++ } ++ ++ ++ if(rtStatus == RT_STATUS_SUCCESS) ++ { ++ RT_TRACE(COMP_INIT, DBG_LOUD, ("phy_ConfigBBWithMpParaFile(): read %s ok\n", pFileName)); ++ ++ for(ithLine = 0; ithLine < nLinesRead; ithLine++) ++ { ++ szLine = pHalData->BufOfLines[ithLine]; ++ ++ if(!IsCommentString(szLine)) ++ { ++ // Get 1st hex value as register offset. ++ if(GetHexValueFromString(szLine, &u4bRegOffset, &u4bMove)) ++ { ++ if(u4bRegOffset == 0xff) ++ { // Ending. ++ break; ++ } ++ else if (u4bRegOffset == 0xfe) ++ delay_ms(50); ++ else if (u4bRegOffset == 0xfd) ++ delay_ms(5); ++ else if (u4bRegOffset == 0xfc) ++ delay_ms(1); ++ else if (u4bRegOffset == 0xfb) ++ PlatformStallExecution(50); ++ else if (u4bRegOffset == 0xfa) ++ PlatformStallExecution(5); ++ else if (u4bRegOffset == 0xf9) ++ PlatformStallExecution(1); ++ ++ // Get 2nd hex value as register value. ++ szLine += u4bMove; ++ if(GetHexValueFromString(szLine, &u4bRegValue, &u4bMove)) ++ { ++ RT_TRACE(COMP_FPGA, DBG_TRACE, ("[ADDR]%03lX=%08lX\n", u4bRegOffset, u4bRegValue)); ++ PHY_SetBBReg(Adapter, u4bRegOffset, bMaskDWord, u4bRegValue); ++ ++ // Add 1us delay between BB/RF register setting. ++ PlatformStallExecution(1); ++ } ++ } ++ } ++ } ++ } ++ else ++ { ++ RT_TRACE(COMP_INIT, DBG_LOUD, ("phy_ConfigBBWithMpParaFile(): Failed%s\n", pFileName)); ++ } ++#endif ++ ++ return rtStatus; ++} ++ ++/*----------------------------------------------------------------------------- ++ * Function: phy_ConfigBBWithMpHeaderFile ++ * ++ * Overview: Config PHY_REG_MP array ++ * ++ * Input: NONE ++ * ++ * Output: NONE ++ * ++ * Return: NONE ++ * ++ * Revised History: ++ * When Who Remark ++ * 02/04/2010 chiyokolin Modify to new files. ++ *---------------------------------------------------------------------------*/ ++static int ++phy_ConfigBBWithMpHeaderFile( ++ IN PADAPTER Adapter, ++ IN u1Byte ConfigType) ++{ ++ int i; ++ u32* Rtl8192CPHY_REGArray_Table_MP; ++ u16 PHY_REGArrayMPLen; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ ++ PHY_REGArrayMPLen = PHY_REG_Array_MPLength; ++ Rtl8192CPHY_REGArray_Table_MP = Rtl819XPHY_REG_Array_MP; ++ ++ if(ConfigType == BaseBand_Config_PHY_REG) ++ { ++ for(i=0;iphy_BB8192S_Config_ParaFile\n")); ++ ++ if(IS_92C_SERIAL(pHalData->VersionID)){ ++ pszBBRegFile=(u8*)&sz92CBBRegFile ; ++ pszAGCTableFile =(u8*)&sz92CAGCTableFile; ++ } ++ else{ ++ pszBBRegFile=(u8*)&sz88CBBRegFile ; ++ pszAGCTableFile =(u8*)&sz88CAGCTableFile; ++ } ++ ++ // ++ // 1. Read PHY_REG.TXT BB INIT!! ++ // We will seperate as 88C / 92C according to chip version ++ // ++#ifdef CONFIG_EMBEDDED_FWIMG ++ rtStatus = phy_ConfigBBWithHeaderFile(Adapter, BaseBand_Config_PHY_REG); ++#else ++ // No matter what kind of CHIP we always read PHY_REG.txt. We must copy different ++ // type of parameter files to phy_reg.txt at first. ++ rtStatus = phy_ConfigBBWithParaFile(Adapter,pszBBRegFile); ++#endif ++ ++ if(rtStatus != _SUCCESS){ ++ //RT_TRACE(COMP_INIT, DBG_SERIOUS, ("phy_BB8192S_Config_ParaFile():Write BB Reg Fail!!")); ++ goto phy_BB8190_Config_ParaFile_Fail; ++ } ++ ++#if MP_DRIVER == 1 ++ // ++ // 1.1 Read PHY_REG_MP.TXT BB INIT!! ++ // We will seperate as 88C / 92C according to chip version ++ // ++#ifdef CONFIG_EMBEDDED_FWIMG ++ rtStatus = phy_ConfigBBWithMpHeaderFile(Adapter, BaseBand_Config_PHY_REG); ++#else ++ // No matter what kind of CHIP we always read PHY_REG.txt. We must copy different ++ // type of parameter files to phy_reg.txt at first. ++ rtStatus = phy_ConfigBBWithMpParaFile(Adapter, pszBBRegMpFile); ++#endif ++ ++ if(rtStatus != _SUCCESS){ ++// RT_TRACE(COMP_INIT, DBG_SERIOUS, ("phy_BB8192S_Config_ParaFile():Write BB Reg MP Fail!!")); ++ goto phy_BB8190_Config_ParaFile_Fail; ++ } ++#endif // #if (MP_DRIVER == 1) ++ ++ // ++ // 20100318 Joseph: Config 2T2R to 1T2R if necessary. ++ // ++ if(pHalData->rf_type == RF_1T2R) ++ { ++ phy_BB8192C_Config_1T(Adapter); ++ DBG_8192C("phy_BB8192C_Config_ParaFile():Config to 1T!!\n"); ++ } ++ ++ // ++ // 2. If EEPROM or EFUSE autoload OK, We must config by PHY_REG_PG.txt ++ // ++ if (pEEPROM->bautoload_fail_flag == _FALSE) ++ { ++ pHalData->pwrGroupCnt = 0; ++ ++#ifdef CONFIG_EMBEDDED_FWIMG ++ rtStatus = phy_ConfigBBWithPgHeaderFile(Adapter, BaseBand_Config_PHY_REG); ++#else ++ rtStatus = phy_ConfigBBWithPgParaFile(Adapter, (u8*)&szBBRegPgFile); ++#endif ++ } ++ ++ if(rtStatus != _SUCCESS){ ++ //RT_TRACE(COMP_INIT, DBG_SERIOUS, ("phy_BB8192S_Config_ParaFile():BB_PG Reg Fail!!")); ++ goto phy_BB8190_Config_ParaFile_Fail; ++ } ++ ++ // ++ // 3. BB AGC table Initialization ++ // ++#ifdef CONFIG_EMBEDDED_FWIMG ++ rtStatus = phy_ConfigBBWithHeaderFile(Adapter, BaseBand_Config_AGC_TAB); ++#else ++ //RT_TRACE(COMP_INIT, DBG_LOUD, ("phy_BB8192S_Config_ParaFile AGC_TAB.txt\n")); ++ rtStatus = phy_ConfigBBWithParaFile(Adapter, pszAGCTableFile); ++#endif ++ ++ if(rtStatus != _SUCCESS){ ++ //RT_TRACE(COMP_FPGA, DBG_SERIOUS, ("phy_BB8192S_Config_ParaFile():AGC Table Fail\n")); ++ goto phy_BB8190_Config_ParaFile_Fail; ++ } ++ ++ // Check if the CCK HighPower is turned ON. ++ // This is used to calculate PWDB. ++ pHalData->bCckHighPower = (BOOLEAN)(PHY_QueryBBReg(Adapter, rFPGA0_XA_HSSIParameter2, 0x200)); ++ ++phy_BB8190_Config_ParaFile_Fail: ++ ++ return rtStatus; ++} ++ ++ ++int ++PHY_BBConfig8192C( ++ IN PADAPTER Adapter ++ ) ++{ ++ int rtStatus = _SUCCESS; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ u32 RegVal; ++ u8 TmpU1B=0; ++ u8 value8; ++ ++ phy_InitBBRFRegisterDefinition(Adapter); ++ ++ if(IS_HARDWARE_TYPE_8723(Adapter)) ++ { ++ // Suggested by Scott. tynli_test. 2010.12.30. ++ //1. 0x28[1] = 1 ++ TmpU1B = rtw_read8(Adapter, REG_AFE_PLL_CTRL); ++ rtw_udelay_os(2); ++ rtw_write8(Adapter, REG_AFE_PLL_CTRL, (TmpU1B|BIT1)); ++ rtw_udelay_os(2); ++ ++ //2. 0x29[7:0] = 0xFF ++ rtw_write8(Adapter, REG_AFE_PLL_CTRL+1, 0xff); ++ rtw_udelay_os(2); ++ ++ //3. 0x02[1:0] = 2b'11 ++ TmpU1B = rtw_read8(Adapter, REG_SYS_FUNC_EN); ++ rtw_write8(Adapter, REG_SYS_FUNC_EN, (TmpU1B|FEN_BB_GLB_RSTn|FEN_BBRSTB)); ++ ++ //4. 0x25[6] = 0 ++ TmpU1B = rtw_read8(Adapter, REG_AFE_XTAL_CTRL+1); ++ rtw_write8(Adapter, REG_AFE_XTAL_CTRL+1, (TmpU1B&(~BIT6))); ++ ++ //5. 0x24[20] = 0 //Advised by SD3 Alex Wang. 2011.02.09. ++ TmpU1B = rtw_read8(Adapter, REG_AFE_XTAL_CTRL+2); ++ rtw_write8(Adapter, REG_AFE_XTAL_CTRL+2, (TmpU1B&(~BIT4))); ++ ++ //6. 0x1f[7:0] = 0x07 ++ rtw_write8(Adapter, REG_RF_CTRL, 0x07); ++ } ++ else ++ { ++ // Enable BB and RF ++ RegVal = rtw_read16(Adapter, REG_SYS_FUNC_EN); ++ rtw_write16(Adapter, REG_SYS_FUNC_EN, (u16)(RegVal|BIT13|BIT0|BIT1)); ++ ++ // 20090923 Joseph: Advised by Steven and Jenyu. Power sequence before init RF. ++ rtw_write8(Adapter, REG_AFE_PLL_CTRL, 0x83); ++ rtw_write8(Adapter, REG_AFE_PLL_CTRL+1, 0xdb); ++ ++ rtw_write8(Adapter, REG_RF_CTRL, RF_EN|RF_RSTB|RF_SDMRSTB); ++ ++#ifdef CONFIG_USB_HCI ++ rtw_write8(Adapter, REG_SYS_FUNC_EN, FEN_USBA | FEN_USBD | FEN_BB_GLB_RSTn | FEN_BBRSTB); ++#else ++ rtw_write8(Adapter, REG_SYS_FUNC_EN, FEN_PPLL|FEN_PCIEA|FEN_DIO_PCIE|FEN_BB_GLB_RSTn|FEN_BBRSTB); ++#endif ++ ++ // 2009/10/21 by SD1 Jong. Modified by tynli. Not in Documented in V8.1. ++ if(!IS_NORMAL_CHIP(pHalData->VersionID)) ++ { ++#ifdef CONFIG_USB_HCI ++ rtw_write8(Adapter, REG_LDOHCI12_CTRL, 0x1f); ++#else ++ rtw_write8(Adapter, REG_LDOHCI12_CTRL, 0x1b); ++#endif ++ } ++ else ++ { ++#ifdef CONFIG_USB_HCI ++ //To Fix MAC loopback mode fail. Suggested by SD4 Johnny. 2010.03.23. ++ rtw_write8(Adapter, REG_LDOHCI12_CTRL, 0x0f); ++ rtw_write8(Adapter, 0x15, 0xe9); ++#endif ++ } ++ ++ rtw_write8(Adapter, REG_AFE_XTAL_CTRL+1, 0x80); ++ ++#ifdef CONFIG_PCI_HCI ++ // Force use left antenna by default for 88C. ++ // if(!IS_92C_SERIAL(pHalData->VersionID) || IS_92C_1T2R(pHalData->VersionID)) ++ if(Adapter->ledpriv.LedStrategy != SW_LED_MODE10) ++ { ++ RegVal = rtw_read32(Adapter, REG_LEDCFG0); ++ rtw_write32(Adapter, REG_LEDCFG0, RegVal|BIT23); ++ } ++#endif ++ } ++ ++ // ++ // Config BB and AGC ++ // ++ rtStatus = phy_BB8192C_Config_ParaFile(Adapter); ++#if 0 ++ switch(Adapter->MgntInfo.bRegHwParaFile) ++ { ++ case 0: ++ phy_BB8190_Config_HardCode(Adapter); ++ break; ++ ++ case 1: ++ rtStatus = phy_BB8192C_Config_ParaFile(Adapter); ++ break; ++ ++ case 2: ++ // Partial Modify. ++ phy_BB8190_Config_HardCode(Adapter); ++ phy_BB8192C_Config_ParaFile(Adapter); ++ break; ++ ++ default: ++ phy_BB8190_Config_HardCode(Adapter); ++ break; ++ } ++#endif ++#ifdef CONFIG_USB_HCI ++ if(IS_HARDWARE_TYPE_8192CU(Adapter)&&IS_81xxC_VENDOR_UMC_B_CUT(pHalData->VersionID) ++ &&(pHalData->BoardType == BOARD_USB_High_PA)) ++ rtw_write8(Adapter, 0xc72, 0x50); ++#endif ++ ++ // For fix 8723 WL_TRSW bug. Suggested by Scott. 2011.01.24. ++ if(IS_HARDWARE_TYPE_8723(Adapter)) ++ { ++ if(!IS_NORMAL_CHIP(pHalData->VersionID)) ++ { ++ // 1. 0x40[2] = 1 ++ value8 = rtw_read8(Adapter, REG_GPIO_MUXCFG); ++ rtw_write8(Adapter, REG_GPIO_MUXCFG, (value8|BIT2)); ++ ++ // 2. 0x804[14] = 0 // BB disable TRSW control, enable SW control ++ PHY_SetBBReg(Adapter, rFPGA0_TxInfo, BIT14, 0x0); ++ ++ // 3. 0x870[6:5] = 2'b11 ++ PHY_SetBBReg(Adapter, rFPGA0_XAB_RFInterfaceSW, (BIT5|BIT6), 0x3); ++ ++ // 4. 0x860[6:5] = 2'b00 // BB SW control TRSW pin output level ++ PHY_SetBBReg(Adapter, rFPGA0_XA_RFInterfaceOE, (BIT5|BIT6), 0x0); ++ } ++ } ++#if 0 ++ // Check BB/RF confiuration setting. ++ // We only need to configure RF which is turned on. ++ PathMap = (u1Byte)(PHY_QueryBBReg(Adapter, rFPGA0_TxInfo, 0xf) | ++ PHY_QueryBBReg(Adapter, rOFDM0_TRxPathEnable, 0xf)); ++ pHalData->RF_PathMap = PathMap; ++ for(index = 0; index<4; index++) ++ { ++ if((PathMap>>index)&0x1) ++ rf_num++; ++ } ++ ++ if((GET_RF_TYPE(Adapter) ==RF_1T1R && rf_num!=1) || ++ (GET_RF_TYPE(Adapter)==RF_1T2R && rf_num!=2) || ++ (GET_RF_TYPE(Adapter)==RF_2T2R && rf_num!=2) || ++ (GET_RF_TYPE(Adapter)==RF_2T2R_GREEN && rf_num!=2) || ++ (GET_RF_TYPE(Adapter)==RF_2T4R && rf_num!=4)) ++ { ++ RT_TRACE( ++ COMP_INIT, ++ DBG_LOUD, ++ ("PHY_BBConfig8192C: RF_Type(%x) does not match RF_Num(%x)!!\n", pHalData->RF_Type, rf_num)); ++ } ++#endif ++ ++ return rtStatus; ++} ++ ++ ++int ++PHY_RFConfig8192C( ++ IN PADAPTER Adapter ++ ) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ int rtStatus = _SUCCESS; ++ ++ // ++ // RF config ++ // ++ rtStatus = PHY_RF6052_Config8192C(Adapter); ++#if 0 ++ switch(pHalData->rf_chip) ++ { ++ case RF_6052: ++ rtStatus = PHY_RF6052_Config(Adapter); ++ break; ++ case RF_8225: ++ rtStatus = PHY_RF8225_Config(Adapter); ++ break; ++ case RF_8256: ++ rtStatus = PHY_RF8256_Config(Adapter); ++ break; ++ case RF_8258: ++ break; ++ case RF_PSEUDO_11N: ++ rtStatus = PHY_RF8225_Config(Adapter); ++ break; ++ default: //for MacOs Warning: "RF_TYPE_MIN" not handled in switch ++ break; ++ } ++#endif ++ return rtStatus; ++} ++ ++ ++/*----------------------------------------------------------------------------- ++ * Function: PHY_ConfigRFWithParaFile() ++ * ++ * Overview: This function read RF parameters from general file format, and do RF 3-wire ++ * ++ * Input: PADAPTER Adapter ++ * ps1Byte pFileName ++ * RF90_RADIO_PATH_E eRFPath ++ * ++ * Output: NONE ++ * ++ * Return: RT_STATUS_SUCCESS: configuration file exist ++ * ++ * Note: Delay may be required for RF configuration ++ *---------------------------------------------------------------------------*/ ++int ++rtl8192c_PHY_ConfigRFWithParaFile( ++ IN PADAPTER Adapter, ++ IN u8* pFileName, ++ RF90_RADIO_PATH_E eRFPath ++) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ ++ int rtStatus = _SUCCESS; ++ ++ ++ return rtStatus; ++ ++} ++ ++//**************************************** ++// The following is for High Power PA ++//**************************************** ++#define HighPowerRadioAArrayLen 22 ++//This is for High power PA ++u32 Rtl8192S_HighPower_RadioA_Array[HighPowerRadioAArrayLen] = { ++0x013,0x00029ea4, ++0x013,0x00025e74, ++0x013,0x00020ea4, ++0x013,0x0001ced0, ++0x013,0x00019f40, ++0x013,0x00014e70, ++0x013,0x000106a0, ++0x013,0x0000c670, ++0x013,0x000082a0, ++0x013,0x00004270, ++0x013,0x00000240, ++}; ++ ++int ++PHY_ConfigRFExternalPA( ++ IN PADAPTER Adapter, ++ RF90_RADIO_PATH_E eRFPath ++) ++{ ++ int rtStatus = _SUCCESS; ++#ifdef CONFIG_USB_HCI ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ u16 i=0; ++ ++ if(!pHalData->ExternalPA) ++ { ++ return rtStatus; ++ } ++ ++ // 2010/10/19 MH According to Jenyu/EEChou 's opinion, we need not to execute the ++ // same code as SU. It is already updated in radio_a_1T_HP.txt. ++#if 0 ++ //add for SU High Power PA ++ for(i = 0;iVersionID)) ++ { ++ if(IS_NORMAL_CHIP(pHalData->VersionID)) ++ { ++ RadioA_ArrayLen = RadioA_2TArrayLength; ++ Rtl819XRadioA_Array_Table = Rtl819XRadioA_2TArray; ++ RadioB_ArrayLen = RadioB_2TArrayLength; ++ Rtl819XRadioB_Array_Table = Rtl819XRadioB_2TArray; ++ } ++ else ++ { ++ rtStatus = _FAIL; ++ goto exit; ++ } ++ } ++ else ++ { ++ if(IS_NORMAL_CHIP(pHalData->VersionID)) ++ { ++ RadioA_ArrayLen = RadioA_1TArrayLength; ++ Rtl819XRadioA_Array_Table = Rtl819XRadioA_1TArray; ++ RadioB_ArrayLen = RadioB_1TArrayLength; ++ Rtl819XRadioB_Array_Table = Rtl819XRadioB_1TArray; ++#ifdef CONFIG_USB_HCI ++ if( BOARD_MINICARD == pHalData->BoardType ) ++ { ++ RadioA_ArrayLen = RadioA_1T_mCardArrayLength; ++ Rtl819XRadioA_Array_Table = Rtl819XRadioA_1T_mCardArray; ++ RadioB_ArrayLen = RadioB_1T_mCardArrayLength; ++ Rtl819XRadioB_Array_Table = Rtl819XRadioB_1T_mCardArray; ++ } ++ else if( BOARD_USB_High_PA == pHalData->BoardType ) ++ { ++ RadioA_ArrayLen = RadioA_1T_HPArrayLength; ++ Rtl819XRadioA_Array_Table = Rtl819XRadioA_1T_HPArray; ++ } ++#endif ++ } ++ else ++ { ++ rtStatus = _FAIL; ++ goto exit; ++ } ++ } ++ ++ switch(eRFPath){ ++ case RF90_PATH_A: ++ #ifdef CONFIG_IOL_RF_RF90_PATH_A ++ if(rtw_IOL_applied(Adapter)) ++ { ++ struct xmit_frame *xmit_frame; ++ if((xmit_frame=rtw_IOL_accquire_xmit_frame(Adapter)) == NULL) { ++ rtStatus = _FAIL; ++ goto exit; ++ } ++ ++ for(i = 0;iPHYRegDef[eRFPath]; ++ u32 NewOffset = 0; ++ u32 DataAndAddr = 0; ++ ++ NewOffset = Rtl819XRadioA_Array_Table[i] & 0x3f; ++ DataAndAddr = ((NewOffset<<20) | (Rtl819XRadioA_Array_Table[i+1]&0x000fffff)) & 0x0fffffff; // T65 RF ++ rtw_IOL_append_WD_cmd(xmit_frame, pPhyReg->rf3wireOffset, DataAndAddr); ++ } ++ } ++ rtStatus = rtw_IOL_exec_cmds_sync(Adapter, xmit_frame, 1000); ++ } ++ else ++ #endif ++ { ++ for(i = 0;iPHYRegDef[eRFPath]; ++ u32 NewOffset = 0; ++ u32 DataAndAddr = 0; ++ ++ NewOffset = Rtl819XRadioB_Array_Table[i] & 0x3f; ++ DataAndAddr = ((NewOffset<<20) | (Rtl819XRadioB_Array_Table[i+1]&0x000fffff)) & 0x0fffffff; // T65 RF ++ rtw_IOL_append_WD_cmd(xmit_frame, pPhyReg->rf3wireOffset, DataAndAddr); ++ } ++ } ++ rtStatus = rtw_IOL_exec_cmds_sync(Adapter, xmit_frame, 1000); ++ } ++ else ++ #endif ++ { ++ for(i = 0;i actually we call PlatformStallExecution()) to do NdisStallExecution() ++ // [busy wait] instead of NdisMSleep(). So we acquire RT_INITIAL_SPINLOCK ++ // to run at Dispatch level to achive it. ++ //cosa PlatformAcquireSpinLock(Adapter, RT_INITIAL_SPINLOCK); ++ WriteData[i] &= 0xfff; ++ PHY_SetRFReg(Adapter, eRFPath, WriteAddr[HW90_BLOCK_RF], bRFRegOffsetMask, WriteData[i]); ++ // TODO: we should not delay for such a long time. Ask SD3 ++ rtw_mdelay_os(10); ++ ulRegRead = PHY_QueryRFReg(Adapter, eRFPath, WriteAddr[HW90_BLOCK_RF], bMaskDWord); ++ rtw_mdelay_os(10); ++ //cosa PlatformReleaseSpinLock(Adapter, RT_INITIAL_SPINLOCK); ++ break; ++ ++ default: ++ rtStatus = _FAIL; ++ break; ++ } ++ ++ ++ // ++ // Check whether readback data is correct ++ // ++ if(ulRegRead != WriteData[i]) ++ { ++ //RT_TRACE(COMP_FPGA, DBG_LOUD, ("ulRegRead: %lx, WriteData: %lx \n", ulRegRead, WriteData[i])); ++ rtStatus = _FAIL; ++ break; ++ } ++ } ++ ++ return rtStatus; ++} ++ ++ ++VOID ++rtl8192c_PHY_GetHWRegOriginalValue( ++ IN PADAPTER Adapter ++ ) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ ++ // read rx initial gain ++ pHalData->DefaultInitialGain[0] = (u8)PHY_QueryBBReg(Adapter, rOFDM0_XAAGCCore1, bMaskByte0); ++ pHalData->DefaultInitialGain[1] = (u8)PHY_QueryBBReg(Adapter, rOFDM0_XBAGCCore1, bMaskByte0); ++ pHalData->DefaultInitialGain[2] = (u8)PHY_QueryBBReg(Adapter, rOFDM0_XCAGCCore1, bMaskByte0); ++ pHalData->DefaultInitialGain[3] = (u8)PHY_QueryBBReg(Adapter, rOFDM0_XDAGCCore1, bMaskByte0); ++ //RT_TRACE(COMP_INIT, DBG_LOUD, ++ //("Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x) \n", ++ //pHalData->DefaultInitialGain[0], pHalData->DefaultInitialGain[1], ++ //pHalData->DefaultInitialGain[2], pHalData->DefaultInitialGain[3])); ++ ++ // read framesync ++ pHalData->framesync = (u8)PHY_QueryBBReg(Adapter, rOFDM0_RxDetector3, bMaskByte0); ++ pHalData->framesyncC34 = PHY_QueryBBReg(Adapter, rOFDM0_RxDetector2, bMaskDWord); ++ //RT_TRACE(COMP_INIT, DBG_LOUD, ("Default framesync (0x%x) = 0x%x \n", ++ // rOFDM0_RxDetector3, pHalData->framesync)); ++} ++ ++ ++// ++// Description: ++// Map dBm into Tx power index according to ++// current HW model, for example, RF and PA, and ++// current wireless mode. ++// By Bruce, 2008-01-29. ++// ++static u8 ++phy_DbmToTxPwrIdx( ++ IN PADAPTER Adapter, ++ IN WIRELESS_MODE WirelessMode, ++ IN int PowerInDbm ++ ) ++{ ++ u8 TxPwrIdx = 0; ++ int Offset = 0; ++ ++ ++ // ++ // Tested by MP, we found that CCK Index 0 equals to 8dbm, OFDM legacy equals to ++ // 3dbm, and OFDM HT equals to 0dbm repectively. ++ // Note: ++ // The mapping may be different by different NICs. Do not use this formula for what needs accurate result. ++ // By Bruce, 2008-01-29. ++ // ++ switch(WirelessMode) ++ { ++ case WIRELESS_MODE_B: ++ Offset = -7; ++ break; ++ ++ case WIRELESS_MODE_G: ++ case WIRELESS_MODE_N_24G: ++ Offset = -8; ++ break; ++ default: ++ Offset = -8; ++ break; ++ } ++ ++ if((PowerInDbm - Offset) > 0) ++ { ++ TxPwrIdx = (u8)((PowerInDbm - Offset) * 2); ++ } ++ else ++ { ++ TxPwrIdx = 0; ++ } ++ ++ // Tx Power Index is too large. ++ if(TxPwrIdx > MAX_TXPWR_IDX_NMODE_92S) ++ TxPwrIdx = MAX_TXPWR_IDX_NMODE_92S; ++ ++ return TxPwrIdx; ++} ++ ++// ++// Description: ++// Map Tx power index into dBm according to ++// current HW model, for example, RF and PA, and ++// current wireless mode. ++// By Bruce, 2008-01-29. ++// ++int ++phy_TxPwrIdxToDbm( ++ IN PADAPTER Adapter, ++ IN WIRELESS_MODE WirelessMode, ++ IN u8 TxPwrIdx ++ ) ++{ ++ int Offset = 0; ++ int PwrOutDbm = 0; ++ ++ // ++ // Tested by MP, we found that CCK Index 0 equals to -7dbm, OFDM legacy equals to -8dbm. ++ // Note: ++ // The mapping may be different by different NICs. Do not use this formula for what needs accurate result. ++ // By Bruce, 2008-01-29. ++ // ++ switch(WirelessMode) ++ { ++ case WIRELESS_MODE_B: ++ Offset = -7; ++ break; ++ ++ case WIRELESS_MODE_G: ++ case WIRELESS_MODE_N_24G: ++ Offset = -8; ++ default: ++ Offset = -8; ++ break; ++ } ++ ++ PwrOutDbm = TxPwrIdx / 2 + Offset; // Discard the decimal part. ++ ++ return PwrOutDbm; ++} ++ ++ ++/*----------------------------------------------------------------------------- ++ * Function: GetTxPowerLevel8190() ++ * ++ * Overview: This function is export to "common" moudule ++ * ++ * Input: PADAPTER Adapter ++ * psByte Power Level ++ * ++ * Output: NONE ++ * ++ * Return: NONE ++ * ++ *---------------------------------------------------------------------------*/ ++VOID ++PHY_GetTxPowerLevel8192C( ++ IN PADAPTER Adapter, ++ OUT u32* powerlevel ++ ) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ u8 TxPwrLevel = 0; ++ int TxPwrDbm; ++ ++ // ++ // Because the Tx power indexes are different, we report the maximum of them to ++ // meet the CCX TPC request. By Bruce, 2008-01-31. ++ // ++ ++ // CCK ++ TxPwrLevel = pHalData->CurrentCckTxPwrIdx; ++ TxPwrDbm = phy_TxPwrIdxToDbm(Adapter, WIRELESS_MODE_B, TxPwrLevel); ++ ++ // Legacy OFDM ++ TxPwrLevel = pHalData->CurrentOfdm24GTxPwrIdx + pHalData->LegacyHTTxPowerDiff; ++ ++ // Compare with Legacy OFDM Tx power. ++ if(phy_TxPwrIdxToDbm(Adapter, WIRELESS_MODE_G, TxPwrLevel) > TxPwrDbm) ++ TxPwrDbm = phy_TxPwrIdxToDbm(Adapter, WIRELESS_MODE_G, TxPwrLevel); ++ ++ // HT OFDM ++ TxPwrLevel = pHalData->CurrentOfdm24GTxPwrIdx; ++ ++ // Compare with HT OFDM Tx power. ++ if(phy_TxPwrIdxToDbm(Adapter, WIRELESS_MODE_N_24G, TxPwrLevel) > TxPwrDbm) ++ TxPwrDbm = phy_TxPwrIdxToDbm(Adapter, WIRELESS_MODE_N_24G, TxPwrLevel); ++ ++ *powerlevel = TxPwrDbm; ++} ++ ++ ++static void getTxPowerIndex( ++ IN PADAPTER Adapter, ++ IN u8 channel, ++ IN OUT u8* cckPowerLevel, ++ IN OUT u8* ofdmPowerLevel ++ ) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ u8 index = (channel -1); ++ // 1. CCK ++ cckPowerLevel[RF90_PATH_A] = pHalData->TxPwrLevelCck[RF90_PATH_A][index]; //RF-A ++ cckPowerLevel[RF90_PATH_B] = pHalData->TxPwrLevelCck[RF90_PATH_B][index]; //RF-B ++ ++ // 2. OFDM for 1S or 2S ++ if (GET_RF_TYPE(Adapter) == RF_1T2R || GET_RF_TYPE(Adapter) == RF_1T1R) ++ { ++ // Read HT 40 OFDM TX power ++ ofdmPowerLevel[RF90_PATH_A] = pHalData->TxPwrLevelHT40_1S[RF90_PATH_A][index]; ++ ofdmPowerLevel[RF90_PATH_B] = pHalData->TxPwrLevelHT40_1S[RF90_PATH_B][index]; ++ } ++ else if (GET_RF_TYPE(Adapter) == RF_2T2R) ++ { ++ // Read HT 40 OFDM TX power ++ ofdmPowerLevel[RF90_PATH_A] = pHalData->TxPwrLevelHT40_2S[RF90_PATH_A][index]; ++ ofdmPowerLevel[RF90_PATH_B] = pHalData->TxPwrLevelHT40_2S[RF90_PATH_B][index]; ++ } ++ //RTPRINT(FPHY, PHY_TXPWR, ("Channel-%d, set tx power index !!\n", channel)); ++} ++ ++static void ccxPowerIndexCheck( ++ IN PADAPTER Adapter, ++ IN u8 channel, ++ IN OUT u8* cckPowerLevel, ++ IN OUT u8* ofdmPowerLevel ++ ) ++{ ++#if 0 ++ PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo); ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ PRT_CCX_INFO pCcxInfo = GET_CCX_INFO(pMgntInfo); ++ ++ // ++ // CCX 2 S31, AP control of client transmit power: ++ // 1. We shall not exceed Cell Power Limit as possible as we can. ++ // 2. Tolerance is +/- 5dB. ++ // 3. 802.11h Power Contraint takes higher precedence over CCX Cell Power Limit. ++ // ++ // TODO: ++ // 1. 802.11h power contraint ++ // ++ // 071011, by rcnjko. ++ // ++ if( pMgntInfo->OpMode == RT_OP_MODE_INFRASTRUCTURE && ++ pMgntInfo->mAssoc && ++ pCcxInfo->bUpdateCcxPwr && ++ pCcxInfo->bWithCcxCellPwr && ++ channel == pMgntInfo->dot11CurrentChannelNumber) ++ { ++ u1Byte CckCellPwrIdx = phy_DbmToTxPwrIdx(Adapter, WIRELESS_MODE_B, pCcxInfo->CcxCellPwr); ++ u1Byte LegacyOfdmCellPwrIdx = phy_DbmToTxPwrIdx(Adapter, WIRELESS_MODE_G, pCcxInfo->CcxCellPwr); ++ u1Byte OfdmCellPwrIdx = phy_DbmToTxPwrIdx(Adapter, WIRELESS_MODE_N_24G, pCcxInfo->CcxCellPwr); ++ ++ RT_TRACE(COMP_TXAGC, DBG_LOUD, ++ ("CCX Cell Limit: %d dbm => CCK Tx power index : %d, Legacy OFDM Tx power index : %d, OFDM Tx power index: %d\n", ++ pCcxInfo->CcxCellPwr, CckCellPwrIdx, LegacyOfdmCellPwrIdx, OfdmCellPwrIdx)); ++ RT_TRACE(COMP_TXAGC, DBG_LOUD, ++ ("EEPROM channel(%d) => CCK Tx power index: %d, Legacy OFDM Tx power index : %d, OFDM Tx power index: %d\n", ++ channel, cckPowerLevel[0], ofdmPowerLevel[0] + pHalData->LegacyHTTxPowerDiff, ofdmPowerLevel[0])); ++ ++ // CCK ++ if(cckPowerLevel[0] > CckCellPwrIdx) ++ cckPowerLevel[0] = CckCellPwrIdx; ++ // Legacy OFDM, HT OFDM ++ if(ofdmPowerLevel[0] + pHalData->LegacyHTTxPowerDiff > LegacyOfdmCellPwrIdx) ++ { ++ if((OfdmCellPwrIdx - pHalData->LegacyHTTxPowerDiff) > 0) ++ { ++ ofdmPowerLevel[0] = OfdmCellPwrIdx - pHalData->LegacyHTTxPowerDiff; ++ } ++ else ++ { ++ ofdmPowerLevel[0] = 0; ++ } ++ } ++ ++ RT_TRACE(COMP_TXAGC, DBG_LOUD, ++ ("Altered CCK Tx power index : %d, Legacy OFDM Tx power index: %d, OFDM Tx power index: %d\n", ++ cckPowerLevel[0], ofdmPowerLevel[0] + pHalData->LegacyHTTxPowerDiff, ofdmPowerLevel[0])); ++ } ++ ++ pHalData->CurrentCckTxPwrIdx = cckPowerLevel[0]; ++ pHalData->CurrentOfdm24GTxPwrIdx = ofdmPowerLevel[0]; ++ ++ RT_TRACE(COMP_TXAGC, DBG_LOUD, ++ ("PHY_SetTxPowerLevel8192S(): CCK Tx power index : %d, Legacy OFDM Tx power index: %d, OFDM Tx power index: %d\n", ++ cckPowerLevel[0], ofdmPowerLevel[0] + pHalData->LegacyHTTxPowerDiff, ofdmPowerLevel[0])); ++#endif ++} ++/*----------------------------------------------------------------------------- ++ * Function: SetTxPowerLevel8190() ++ * ++ * Overview: This function is export to "HalCommon" moudule ++ * We must consider RF path later!!!!!!! ++ * ++ * Input: PADAPTER Adapter ++ * u1Byte channel ++ * ++ * Output: NONE ++ * ++ * Return: NONE ++ * 2008/11/04 MHC We remove EEPROM_93C56. ++ * We need to move CCX relative code to independet file. ++ * 2009/01/21 MHC Support new EEPROM format from SD3 requirement. ++ * ++ *---------------------------------------------------------------------------*/ ++VOID ++PHY_SetTxPowerLevel8192C( ++ IN PADAPTER Adapter, ++ IN u8 channel ++ ) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ u8 cckPowerLevel[2], ofdmPowerLevel[2]; // [0]:RF-A, [1]:RF-B ++ ++#if(MP_DRIVER == 1) ++ return; ++#endif ++ ++ if(pHalData->bTXPowerDataReadFromEEPORM == _FALSE) ++ return; ++ ++ getTxPowerIndex(Adapter, channel, &cckPowerLevel[0], &ofdmPowerLevel[0]); ++ //RTPRINT(FPHY, PHY_TXPWR, ("Channel-%d, cckPowerLevel (A / B) = 0x%x / 0x%x, ofdmPowerLevel (A / B) = 0x%x / 0x%x\n", ++ // channel, cckPowerLevel[0], cckPowerLevel[1], ofdmPowerLevel[0], ofdmPowerLevel[1])); ++ ++ ccxPowerIndexCheck(Adapter, channel, &cckPowerLevel[0], &ofdmPowerLevel[0]); ++ ++ rtl8192c_PHY_RF6052SetCckTxPower(Adapter, &cckPowerLevel[0]); ++ rtl8192c_PHY_RF6052SetOFDMTxPower(Adapter, &ofdmPowerLevel[0], channel); ++ ++#if 0 ++ switch(pHalData->rf_chip) ++ { ++ case RF_8225: ++ PHY_SetRF8225CckTxPower(Adapter, cckPowerLevel[0]); ++ PHY_SetRF8225OfdmTxPower(Adapter, ofdmPowerLevel[0]); ++ break; ++ ++ case RF_8256: ++ PHY_SetRF8256CCKTxPower(Adapter, cckPowerLevel[0]); ++ PHY_SetRF8256OFDMTxPower(Adapter, ofdmPowerLevel[0]); ++ break; ++ ++ case RF_6052: ++ PHY_RF6052SetCckTxPower(Adapter, &cckPowerLevel[0]); ++ PHY_RF6052SetOFDMTxPower(Adapter, &ofdmPowerLevel[0], channel); ++ break; ++ ++ case RF_8258: ++ break; ++ } ++#endif ++ ++} ++ ++ ++// ++// Description: ++// Update transmit power level of all channel supported. ++// ++// TODO: ++// A mode. ++// By Bruce, 2008-02-04. ++// ++BOOLEAN ++PHY_UpdateTxPowerDbm8192C( ++ IN PADAPTER Adapter, ++ IN int powerInDbm ++ ) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ u8 idx; ++ u8 rf_path; ++ ++ // TODO: A mode Tx power. ++ u8 CckTxPwrIdx = phy_DbmToTxPwrIdx(Adapter, WIRELESS_MODE_B, powerInDbm); ++ u8 OfdmTxPwrIdx = phy_DbmToTxPwrIdx(Adapter, WIRELESS_MODE_N_24G, powerInDbm); ++ ++ if(OfdmTxPwrIdx - pHalData->LegacyHTTxPowerDiff > 0) ++ OfdmTxPwrIdx -= pHalData->LegacyHTTxPowerDiff; ++ else ++ OfdmTxPwrIdx = 0; ++ ++ //RT_TRACE(COMP_TXAGC, DBG_LOUD, ("PHY_UpdateTxPowerDbm8192S(): %ld dBm , CckTxPwrIdx = %d, OfdmTxPwrIdx = %d\n", powerInDbm, CckTxPwrIdx, OfdmTxPwrIdx)); ++ ++ for(idx = 0; idx < 14; idx++) ++ { ++ for (rf_path = 0; rf_path < 2; rf_path++) ++ { ++ pHalData->TxPwrLevelCck[rf_path][idx] = CckTxPwrIdx; ++ pHalData->TxPwrLevelHT40_1S[rf_path][idx] = ++ pHalData->TxPwrLevelHT40_2S[rf_path][idx] = OfdmTxPwrIdx; ++ } ++ } ++ ++ //Adapter->HalFunc.SetTxPowerLevelHandler(Adapter, pHalData->CurrentChannel);//gtest:todo ++ ++ return _TRUE; ++} ++ ++ ++/* ++ Description: ++ When beacon interval is changed, the values of the ++ hw registers should be modified. ++ By tynli, 2008.10.24. ++ ++*/ ++ ++ ++void ++rtl8192c_PHY_SetBeaconHwReg( ++ IN PADAPTER Adapter, ++ IN u16 BeaconInterval ++ ) ++{ ++ ++} ++ ++ ++VOID ++PHY_ScanOperationBackup8192C( ++ IN PADAPTER Adapter, ++ IN u8 Operation ++ ) ++{ ++#if 0 ++ IO_TYPE IoType; ++ ++ if(!Adapter->bDriverStopped) ++ { ++ switch(Operation) ++ { ++ case SCAN_OPT_BACKUP: ++ IoType = IO_CMD_PAUSE_DM_BY_SCAN; ++ Adapter->HalFunc.SetHwRegHandler(Adapter,HW_VAR_IO_CMD, (pu1Byte)&IoType); ++ ++ break; ++ ++ case SCAN_OPT_RESTORE: ++ IoType = IO_CMD_RESUME_DM_BY_SCAN; ++ Adapter->HalFunc.SetHwRegHandler(Adapter,HW_VAR_IO_CMD, (pu1Byte)&IoType); ++ break; ++ ++ default: ++ RT_TRACE(COMP_SCAN, DBG_LOUD, ("Unknown Scan Backup Operation. \n")); ++ break; ++ } ++ } ++#endif ++} ++ ++/*----------------------------------------------------------------------------- ++ * Function: PHY_SetBWModeCallback8192C() ++ * ++ * Overview: Timer callback function for SetSetBWMode ++ * ++ * Input: PRT_TIMER pTimer ++ * ++ * Output: NONE ++ * ++ * Return: NONE ++ * ++ * Note: (1) We do not take j mode into consideration now ++ * (2) Will two workitem of "switch channel" and "switch channel bandwidth" run ++ * concurrently? ++ *---------------------------------------------------------------------------*/ ++static VOID ++_PHY_SetBWMode92C( ++ IN PADAPTER Adapter ++) ++{ ++// PADAPTER Adapter = (PADAPTER)pTimer->Adapter; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ u8 regBwOpMode; ++ u8 regRRSR_RSC; ++ ++ //return; ++ ++ // Added it for 20/40 mhz switch time evaluation by guangan 070531 ++ //u4Byte NowL, NowH; ++ //u8Byte BeginTime, EndTime; ++ ++ /*RT_TRACE(COMP_SCAN, DBG_LOUD, ("==>PHY_SetBWModeCallback8192C() Switch to %s bandwidth\n", \ ++ pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_20?"20MHz":"40MHz"))*/ ++ ++ if(pHalData->rf_chip == RF_PSEUDO_11N) ++ { ++ //pHalData->SetBWModeInProgress= _FALSE; ++ return; ++ } ++ ++ // There is no 40MHz mode in RF_8225. ++ if(pHalData->rf_chip==RF_8225) ++ return; ++ ++ if(Adapter->bDriverStopped) ++ return; ++ ++ // Added it for 20/40 mhz switch time evaluation by guangan 070531 ++ //NowL = PlatformEFIORead4Byte(Adapter, TSFR); ++ //NowH = PlatformEFIORead4Byte(Adapter, TSFR+4); ++ //BeginTime = ((u8Byte)NowH << 32) + NowL; ++ ++ //3// ++ //3//<1>Set MAC register ++ //3// ++ //Adapter->HalFunc.SetBWModeHandler(); ++ ++ regBwOpMode = rtw_read8(Adapter, REG_BWOPMODE); ++ regRRSR_RSC = rtw_read8(Adapter, REG_RRSR+2); ++ //regBwOpMode = Adapter->HalFunc.GetHwRegHandler(Adapter,HW_VAR_BWMODE,(pu1Byte)®BwOpMode); ++ ++ switch(pHalData->CurrentChannelBW) ++ { ++ case HT_CHANNEL_WIDTH_20: ++ regBwOpMode |= BW_OPMODE_20MHZ; ++ // 2007/02/07 Mark by Emily becasue we have not verify whether this register works ++ rtw_write8(Adapter, REG_BWOPMODE, regBwOpMode); ++ break; ++ ++ case HT_CHANNEL_WIDTH_40: ++ regBwOpMode &= ~BW_OPMODE_20MHZ; ++ // 2007/02/07 Mark by Emily becasue we have not verify whether this register works ++ rtw_write8(Adapter, REG_BWOPMODE, regBwOpMode); ++ ++ regRRSR_RSC = (regRRSR_RSC&0x90) |(pHalData->nCur40MhzPrimeSC<<5); ++ rtw_write8(Adapter, REG_RRSR+2, regRRSR_RSC); ++ break; ++ ++ default: ++ /*RT_TRACE(COMP_DBG, DBG_LOUD, ("PHY_SetBWModeCallback8192C(): ++ unknown Bandwidth: %#X\n",pHalData->CurrentChannelBW));*/ ++ break; ++ } ++ ++ //3// ++ //3//<2>Set PHY related register ++ //3// ++ switch(pHalData->CurrentChannelBW) ++ { ++ /* 20 MHz channel*/ ++ case HT_CHANNEL_WIDTH_20: ++ PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bRFMOD, 0x0); ++ PHY_SetBBReg(Adapter, rFPGA1_RFMOD, bRFMOD, 0x0); ++ PHY_SetBBReg(Adapter, rFPGA0_AnalogParameter2, BIT10, 1); ++ ++ break; ++ ++ ++ /* 40 MHz channel*/ ++ case HT_CHANNEL_WIDTH_40: ++ PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bRFMOD, 0x1); ++ PHY_SetBBReg(Adapter, rFPGA1_RFMOD, bRFMOD, 0x1); ++ ++ // Set Control channel to upper or lower. These settings are required only for 40MHz ++ PHY_SetBBReg(Adapter, rCCK0_System, bCCKSideBand, (pHalData->nCur40MhzPrimeSC>>1)); ++ PHY_SetBBReg(Adapter, rOFDM1_LSTF, 0xC00, pHalData->nCur40MhzPrimeSC); ++ PHY_SetBBReg(Adapter, rFPGA0_AnalogParameter2, BIT10, 0); ++ ++ PHY_SetBBReg(Adapter, 0x818, (BIT26|BIT27), (pHalData->nCur40MhzPrimeSC==HAL_PRIME_CHNL_OFFSET_LOWER)?2:1); ++ ++ break; ++ ++ ++ ++ default: ++ /*RT_TRACE(COMP_DBG, DBG_LOUD, ("PHY_SetBWModeCallback8192C(): unknown Bandwidth: %#X\n"\ ++ ,pHalData->CurrentChannelBW));*/ ++ break; ++ ++ } ++ //Skip over setting of J-mode in BB register here. Default value is "None J mode". Emily 20070315 ++ ++ // Added it for 20/40 mhz switch time evaluation by guangan 070531 ++ //NowL = PlatformEFIORead4Byte(Adapter, TSFR); ++ //NowH = PlatformEFIORead4Byte(Adapter, TSFR+4); ++ //EndTime = ((u8Byte)NowH << 32) + NowL; ++ //RT_TRACE(COMP_SCAN, DBG_LOUD, ("SetBWModeCallback8190Pci: time of SetBWMode = %I64d us!\n", (EndTime - BeginTime))); ++ ++ //3<3>Set RF related register ++ switch(pHalData->rf_chip) ++ { ++ case RF_8225: ++ //PHY_SetRF8225Bandwidth(Adapter, pHalData->CurrentChannelBW); ++ break; ++ ++ case RF_8256: ++ // Please implement this function in Hal8190PciPhy8256.c ++ //PHY_SetRF8256Bandwidth(Adapter, pHalData->CurrentChannelBW); ++ break; ++ ++ case RF_8258: ++ // Please implement this function in Hal8190PciPhy8258.c ++ // PHY_SetRF8258Bandwidth(); ++ break; ++ ++ case RF_PSEUDO_11N: ++ // Do Nothing ++ break; ++ ++ case RF_6052: ++ rtl8192c_PHY_RF6052SetBandwidth(Adapter, pHalData->CurrentChannelBW); ++ break; ++ ++ default: ++ //RT_ASSERT(FALSE, ("Unknown RFChipID: %d\n", pHalData->RFChipID)); ++ break; ++ } ++ ++ //pHalData->SetBWModeInProgress= FALSE; ++ ++ //RT_TRACE(COMP_SCAN, DBG_LOUD, ("<==PHY_SetBWModeCallback8192C() \n" )); ++} ++ ++ ++ /*----------------------------------------------------------------------------- ++ * Function: SetBWMode8190Pci() ++ * ++ * Overview: This function is export to "HalCommon" moudule ++ * ++ * Input: PADAPTER Adapter ++ * HT_CHANNEL_WIDTH Bandwidth //20M or 40M ++ * ++ * Output: NONE ++ * ++ * Return: NONE ++ * ++ * Note: We do not take j mode into consideration now ++ *---------------------------------------------------------------------------*/ ++VOID ++PHY_SetBWMode8192C( ++ IN PADAPTER Adapter, ++ IN HT_CHANNEL_WIDTH Bandwidth, // 20M or 40M ++ IN unsigned char Offset // Upper, Lower, or Don't care ++) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ HT_CHANNEL_WIDTH tmpBW= pHalData->CurrentChannelBW; ++ // Modified it for 20/40 mhz switch by guangan 070531 ++ //PMGNT_INFO pMgntInfo=&Adapter->MgntInfo; ++ ++ //return; ++ ++ //if(pHalData->SwChnlInProgress) ++// if(pMgntInfo->bScanInProgress) ++// { ++// RT_TRACE(COMP_SCAN, DBG_LOUD, ("PHY_SetBWMode8192C() %s Exit because bScanInProgress!\n", ++// Bandwidth == HT_CHANNEL_WIDTH_20?"20MHz":"40MHz")); ++// return; ++// } ++ ++// if(pHalData->SetBWModeInProgress) ++// { ++// // Modified it for 20/40 mhz switch by guangan 070531 ++// RT_TRACE(COMP_SCAN, DBG_LOUD, ("PHY_SetBWMode8192C() %s cancel last timer because SetBWModeInProgress!\n", ++// Bandwidth == HT_CHANNEL_WIDTH_20?"20MHz":"40MHz")); ++// PlatformCancelTimer(Adapter, &pHalData->SetBWModeTimer); ++// //return; ++// } ++ ++ //if(pHalData->SetBWModeInProgress) ++ // return; ++ ++ //pHalData->SetBWModeInProgress= TRUE; ++ ++ pHalData->CurrentChannelBW = Bandwidth; ++ ++#if 0 ++ if(Offset==HT_EXTCHNL_OFFSET_LOWER) ++ pHalData->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_UPPER; ++ else if(Offset==HT_EXTCHNL_OFFSET_UPPER) ++ pHalData->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_LOWER; ++ else ++ pHalData->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_DONT_CARE; ++#else ++ pHalData->nCur40MhzPrimeSC = Offset; ++#endif ++ ++ if((!Adapter->bDriverStopped) && (!Adapter->bSurpriseRemoved)) ++ { ++#ifdef USE_WORKITEM ++ //PlatformScheduleWorkItem(&(pHalData->SetBWModeWorkItem)); ++#else ++ #if 0 ++ //PlatformSetTimer(Adapter, &(pHalData->SetBWModeTimer), 0); ++ #else ++ _PHY_SetBWMode92C(Adapter); ++ #endif ++#endif ++ } ++ else ++ { ++ //RT_TRACE(COMP_SCAN, DBG_LOUD, ("PHY_SetBWMode8192C() SetBWModeInProgress FALSE driver sleep or unload\n")); ++ //pHalData->SetBWModeInProgress= FALSE; ++ pHalData->CurrentChannelBW = tmpBW; ++ } ++ ++} ++ ++ ++static void _PHY_SwChnl8192C(PADAPTER Adapter, u8 channel) ++{ ++ u8 eRFPath; ++ u32 param1, param2; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ ++ //s1. pre common command - CmdID_SetTxPowerLevel ++ PHY_SetTxPowerLevel8192C(Adapter, channel); ++ ++ //s2. RF dependent command - CmdID_RF_WriteReg, param1=RF_CHNLBW, param2=channel ++ param1 = RF_CHNLBW; ++ param2 = channel; ++ for(eRFPath = 0; eRFPath NumTotalRFPath; eRFPath++) ++ { ++ pHalData->RfRegChnlVal[eRFPath] = ((pHalData->RfRegChnlVal[eRFPath] & 0xfffffc00) | param2); ++ PHY_SetRFReg(Adapter, (RF90_RADIO_PATH_E)eRFPath, param1, bRFRegOffsetMask, pHalData->RfRegChnlVal[eRFPath]); ++ } ++ ++ ++ //s3. post common command - CmdID_End, None ++ ++} ++ ++VOID ++PHY_SwChnl8192C( // Call after initialization ++ IN PADAPTER Adapter, ++ IN u8 channel ++ ) ++{ ++ //PADAPTER Adapter = ADJUST_TO_ADAPTIVE_ADAPTER(pAdapter, _TRUE); ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ u8 tmpchannel = pHalData->CurrentChannel; ++ BOOLEAN bResult = _TRUE; ++ ++ if(pHalData->rf_chip == RF_PSEUDO_11N) ++ { ++ //pHalData->SwChnlInProgress=FALSE; ++ return; //return immediately if it is peudo-phy ++ } ++ ++ //if(pHalData->SwChnlInProgress) ++ // return; ++ ++ //if(pHalData->SetBWModeInProgress) ++ // return; ++ ++ //-------------------------------------------- ++ switch(pHalData->CurrentWirelessMode) ++ { ++ case WIRELESS_MODE_A: ++ case WIRELESS_MODE_N_5G: ++ //RT_ASSERT((channel>14), ("WIRELESS_MODE_A but channel<=14")); ++ break; ++ ++ case WIRELESS_MODE_B: ++ //RT_ASSERT((channel<=14), ("WIRELESS_MODE_B but channel>14")); ++ break; ++ ++ case WIRELESS_MODE_G: ++ case WIRELESS_MODE_N_24G: ++ //RT_ASSERT((channel<=14), ("WIRELESS_MODE_G but channel>14")); ++ break; ++ ++ default: ++ //RT_ASSERT(FALSE, ("Invalid WirelessMode(%#x)!!\n", pHalData->CurrentWirelessMode)); ++ break; ++ } ++ //-------------------------------------------- ++ ++ //pHalData->SwChnlInProgress = TRUE; ++ if(channel == 0) ++ channel = 1; ++ ++ pHalData->CurrentChannel=channel; ++ ++ //pHalData->SwChnlStage=0; ++ //pHalData->SwChnlStep=0; ++ ++ if((!Adapter->bDriverStopped) && (!Adapter->bSurpriseRemoved)) ++ { ++#ifdef USE_WORKITEM ++ //bResult = PlatformScheduleWorkItem(&(pHalData->SwChnlWorkItem)); ++#else ++ #if 0 ++ //PlatformSetTimer(Adapter, &(pHalData->SwChnlTimer), 0); ++ #else ++ _PHY_SwChnl8192C(Adapter, channel); ++ #endif ++#endif ++ if(bResult) ++ { ++ //RT_TRACE(COMP_SCAN, DBG_LOUD, ("PHY_SwChnl8192C SwChnlInProgress TRUE schdule workitem done\n")); ++ } ++ else ++ { ++ //RT_TRACE(COMP_SCAN, DBG_LOUD, ("PHY_SwChnl8192C SwChnlInProgress FALSE schdule workitem error\n")); ++ //if(IS_HARDWARE_TYPE_8192SU(Adapter)) ++ //{ ++ // pHalData->SwChnlInProgress = FALSE; ++ pHalData->CurrentChannel = tmpchannel; ++ //} ++ } ++ ++ } ++ else ++ { ++ //RT_TRACE(COMP_SCAN, DBG_LOUD, ("PHY_SwChnl8192C SwChnlInProgress FALSE driver sleep or unload\n")); ++ //if(IS_HARDWARE_TYPE_8192SU(Adapter)) ++ //{ ++ // pHalData->SwChnlInProgress = FALSE; ++ pHalData->CurrentChannel = tmpchannel; ++ //} ++ } ++} ++ ++ ++static BOOLEAN ++phy_SwChnlStepByStep( ++ IN PADAPTER Adapter, ++ IN u8 channel, ++ IN u8 *stage, ++ IN u8 *step, ++ OUT u32 *delay ++ ) ++{ ++#if 0 ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ PCHANNEL_ACCESS_SETTING pChnlAccessSetting; ++ SwChnlCmd PreCommonCmd[MAX_PRECMD_CNT]; ++ u4Byte PreCommonCmdCnt; ++ SwChnlCmd PostCommonCmd[MAX_POSTCMD_CNT]; ++ u4Byte PostCommonCmdCnt; ++ SwChnlCmd RfDependCmd[MAX_RFDEPENDCMD_CNT]; ++ u4Byte RfDependCmdCnt; ++ SwChnlCmd *CurrentCmd; ++ u1Byte eRFPath; ++ u4Byte RfTXPowerCtrl; ++ BOOLEAN bAdjRfTXPowerCtrl = _FALSE; ++ ++ ++ RT_ASSERT((Adapter != NULL), ("Adapter should not be NULL\n")); ++#if(MP_DRIVER != 1) ++ RT_ASSERT(IsLegalChannel(Adapter, channel), ("illegal channel: %d\n", channel)); ++#endif ++ RT_ASSERT((pHalData != NULL), ("pHalData should not be NULL\n")); ++ ++ pChnlAccessSetting = &Adapter->MgntInfo.Info8185.ChannelAccessSetting; ++ RT_ASSERT((pChnlAccessSetting != NULL), ("pChnlAccessSetting should not be NULL\n")); ++ ++ //for(eRFPath = RF90_PATH_A; eRFPath NumTotalRFPath; eRFPath++) ++ //for(eRFPath = 0; eRFPath NumTotalRFPath; eRFPath++) ++ //{ ++ // <1> Fill up pre common command. ++ PreCommonCmdCnt = 0; ++ phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++, MAX_PRECMD_CNT, ++ CmdID_SetTxPowerLevel, 0, 0, 0); ++ phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++, MAX_PRECMD_CNT, ++ CmdID_End, 0, 0, 0); ++ ++ // <2> Fill up post common command. ++ PostCommonCmdCnt = 0; ++ ++ phy_SetSwChnlCmdArray(PostCommonCmd, PostCommonCmdCnt++, MAX_POSTCMD_CNT, ++ CmdID_End, 0, 0, 0); ++ ++ // <3> Fill up RF dependent command. ++ RfDependCmdCnt = 0; ++ switch( pHalData->RFChipID ) ++ { ++ case RF_8225: ++ RT_ASSERT((channel >= 1 && channel <= 14), ("illegal channel for Zebra: %d\n", channel)); ++ // 2008/09/04 MH Change channel. ++ if(channel==14) channel++; ++ phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT, ++ CmdID_RF_WriteReg, rZebra1_Channel, (0x10+channel-1), 10); ++ phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT, ++ CmdID_End, 0, 0, 0); ++ break; ++ ++ case RF_8256: ++ // TEST!! This is not the table for 8256!! ++ RT_ASSERT((channel >= 1 && channel <= 14), ("illegal channel for Zebra: %d\n", channel)); ++ phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT, ++ CmdID_RF_WriteReg, rRfChannel, channel, 10); ++ phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT, ++ CmdID_End, 0, 0, 0); ++ break; ++ ++ case RF_6052: ++ RT_ASSERT((channel >= 1 && channel <= 14), ("illegal channel for Zebra: %d\n", channel)); ++ phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT, ++ CmdID_RF_WriteReg, RF_CHNLBW, channel, 10); ++ phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT, ++ CmdID_End, 0, 0, 0); ++ ++ break; ++ ++ case RF_8258: ++ break; ++ ++ // For FPGA two MAC verification ++ case RF_PSEUDO_11N: ++ return TRUE; ++ default: ++ RT_ASSERT(FALSE, ("Unknown RFChipID: %d\n", pHalData->RFChipID)); ++ return FALSE; ++ break; ++ } ++ ++ ++ do{ ++ switch(*stage) ++ { ++ case 0: ++ CurrentCmd=&PreCommonCmd[*step]; ++ break; ++ case 1: ++ CurrentCmd=&RfDependCmd[*step]; ++ break; ++ case 2: ++ CurrentCmd=&PostCommonCmd[*step]; ++ break; ++ } ++ ++ if(CurrentCmd->CmdID==CmdID_End) ++ { ++ if((*stage)==2) ++ { ++ return TRUE; ++ } ++ else ++ { ++ (*stage)++; ++ (*step)=0; ++ continue; ++ } ++ } ++ ++ switch(CurrentCmd->CmdID) ++ { ++ case CmdID_SetTxPowerLevel: ++ PHY_SetTxPowerLevel8192C(Adapter,channel); ++ break; ++ case CmdID_WritePortUlong: ++ PlatformEFIOWrite4Byte(Adapter, CurrentCmd->Para1, CurrentCmd->Para2); ++ break; ++ case CmdID_WritePortUshort: ++ PlatformEFIOWrite2Byte(Adapter, CurrentCmd->Para1, (u2Byte)CurrentCmd->Para2); ++ break; ++ case CmdID_WritePortUchar: ++ PlatformEFIOWrite1Byte(Adapter, CurrentCmd->Para1, (u1Byte)CurrentCmd->Para2); ++ break; ++ case CmdID_RF_WriteReg: // Only modify channel for the register now !!!!! ++ for(eRFPath = 0; eRFPath NumTotalRFPath; eRFPath++) ++ { ++#if 1 ++ pHalData->RfRegChnlVal[eRFPath] = ((pHalData->RfRegChnlVal[eRFPath] & 0xfffffc00) | CurrentCmd->Para2); ++ PHY_SetRFReg(Adapter, (RF90_RADIO_PATH_E)eRFPath, CurrentCmd->Para1, bRFRegOffsetMask, pHalData->RfRegChnlVal[eRFPath]); ++#else ++ PHY_SetRFReg(Adapter, (RF90_RADIO_PATH_E)eRFPath, CurrentCmd->Para1, bRFRegOffsetMask, (CurrentCmd->Para2)); ++#endif ++ } ++ break; ++ } ++ ++ break; ++ }while(TRUE); ++ //cosa }/*for(Number of RF paths)*/ ++ ++ (*delay)=CurrentCmd->msDelay; ++ (*step)++; ++ return FALSE; ++#endif ++ return _TRUE; ++} ++ ++ ++static BOOLEAN ++phy_SetSwChnlCmdArray( ++ SwChnlCmd* CmdTable, ++ u32 CmdTableIdx, ++ u32 CmdTableSz, ++ SwChnlCmdID CmdID, ++ u32 Para1, ++ u32 Para2, ++ u32 msDelay ++ ) ++{ ++ SwChnlCmd* pCmd; ++ ++ if(CmdTable == NULL) ++ { ++ //RT_ASSERT(FALSE, ("phy_SetSwChnlCmdArray(): CmdTable cannot be NULL.\n")); ++ return _FALSE; ++ } ++ if(CmdTableIdx >= CmdTableSz) ++ { ++ //RT_ASSERT(FALSE, ++ // ("phy_SetSwChnlCmdArray(): Access invalid index, please check size of the table, CmdTableIdx:%ld, CmdTableSz:%ld\n", ++ // CmdTableIdx, CmdTableSz)); ++ return _FALSE; ++ } ++ ++ pCmd = CmdTable + CmdTableIdx; ++ pCmd->CmdID = CmdID; ++ pCmd->Para1 = Para1; ++ pCmd->Para2 = Para2; ++ pCmd->msDelay = msDelay; ++ ++ return _TRUE; ++} ++ ++ ++static void ++phy_FinishSwChnlNow( // We should not call this function directly ++ IN PADAPTER Adapter, ++ IN u8 channel ++ ) ++{ ++#if 0 ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ u32 delay; ++ ++ while(!phy_SwChnlStepByStep(Adapter,channel,&pHalData->SwChnlStage,&pHalData->SwChnlStep,&delay)) ++ { ++ if(delay>0) ++ rtw_mdelay_os(delay); ++ } ++#endif ++} ++ ++ ++ ++// ++// Description: ++// Switch channel synchronously. Called by SwChnlByDelayHandler. ++// ++// Implemented by Bruce, 2008-02-14. ++// The following procedure is operted according to SwChanlCallback8190Pci(). ++// However, this procedure is performed synchronously which should be running under ++// passive level. ++// ++VOID ++PHY_SwChnlPhy8192C( // Only called during initialize ++ IN PADAPTER Adapter, ++ IN u8 channel ++ ) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ ++ //RT_TRACE(COMP_SCAN | COMP_RM, DBG_LOUD, ("==>PHY_SwChnlPhy8192S(), switch from channel %d to channel %d.\n", pHalData->CurrentChannel, channel)); ++ ++ // Cannot IO. ++ //if(RT_CANNOT_IO(Adapter)) ++ // return; ++ ++ // Channel Switching is in progress. ++ //if(pHalData->SwChnlInProgress) ++ // return; ++ ++ //return immediately if it is peudo-phy ++ if(pHalData->rf_chip == RF_PSEUDO_11N) ++ { ++ //pHalData->SwChnlInProgress=FALSE; ++ return; ++ } ++ ++ //pHalData->SwChnlInProgress = TRUE; ++ if( channel == 0) ++ channel = 1; ++ ++ pHalData->CurrentChannel=channel; ++ ++ //pHalData->SwChnlStage = 0; ++ //pHalData->SwChnlStep = 0; ++ ++ phy_FinishSwChnlNow(Adapter,channel); ++ ++ //pHalData->SwChnlInProgress = FALSE; ++} ++ ++ ++// ++// Description: ++// Configure H/W functionality to enable/disable Monitor mode. ++// Note, because we possibly need to configure BB and RF in this function, ++// so caller should in PASSIVE_LEVEL. 080118, by rcnjko. ++// ++VOID ++PHY_SetMonitorMode8192C( ++ IN PADAPTER pAdapter, ++ IN BOOLEAN bEnableMonitorMode ++ ) ++{ ++#if 0 ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); ++ BOOLEAN bFilterOutNonAssociatedBSSID = FALSE; ++ ++ //2 Note: we may need to stop antenna diversity. ++ if(bEnableMonitorMode) ++ { ++ bFilterOutNonAssociatedBSSID = FALSE; ++ RT_TRACE(COMP_RM, DBG_LOUD, ("PHY_SetMonitorMode8192S(): enable monitor mode\n")); ++ ++ pHalData->bInMonitorMode = TRUE; ++ pAdapter->HalFunc.AllowAllDestAddrHandler(pAdapter, TRUE, TRUE); ++ pAdapter->HalFunc.SetHwRegHandler(pAdapter, HW_VAR_CHECK_BSSID, (pu1Byte)&bFilterOutNonAssociatedBSSID); ++ } ++ else ++ { ++ bFilterOutNonAssociatedBSSID = TRUE; ++ RT_TRACE(COMP_RM, DBG_LOUD, ("PHY_SetMonitorMode8192S(): disable monitor mode\n")); ++ ++ pAdapter->HalFunc.AllowAllDestAddrHandler(pAdapter, FALSE, TRUE); ++ pHalData->bInMonitorMode = FALSE; ++ pAdapter->HalFunc.SetHwRegHandler(pAdapter, HW_VAR_CHECK_BSSID, (pu1Byte)&bFilterOutNonAssociatedBSSID); ++ } ++#endif ++} ++ ++ ++/*----------------------------------------------------------------------------- ++ * Function: PHYCheckIsLegalRfPath8190Pci() ++ * ++ * Overview: Check different RF type to execute legal judgement. If RF Path is illegal ++ * We will return false. ++ * ++ * Input: NONE ++ * ++ * Output: NONE ++ * ++ * Return: NONE ++ * ++ * Revised History: ++ * When Who Remark ++ * 11/15/2007 MHC Create Version 0. ++ * ++ *---------------------------------------------------------------------------*/ ++BOOLEAN ++PHY_CheckIsLegalRfPath8192C( ++ IN PADAPTER pAdapter, ++ IN u32 eRFPath) ++{ ++// HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); ++ BOOLEAN rtValue = _TRUE; ++ ++ // NOt check RF Path now.! ++#if 0 ++ if (pHalData->RF_Type == RF_1T2R && eRFPath != RF90_PATH_A) ++ { ++ rtValue = FALSE; ++ } ++ if (pHalData->RF_Type == RF_1T2R && eRFPath != RF90_PATH_A) ++ { ++ ++ } ++#endif ++ return rtValue; ++ ++} /* PHY_CheckIsLegalRfPath8192C */ ++ ++//------------------------------------------------------------------------- ++// ++// IQK ++// ++//------------------------------------------------------------------------- ++#define MAX_TOLERANCE 5 ++#define IQK_DELAY_TIME 1 //ms ++ ++static u8 //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK ++_PHY_PathA_IQK( ++ IN PADAPTER pAdapter, ++ IN BOOLEAN configPathB ++ ) ++{ ++ u32 regEAC, regE94, regE9C, regEA4; ++ u8 result = 0x00; ++ ++ //RTPRINT(FINIT, INIT_IQK, ("Path A IQK!\n")); ++ ++ //path-A IQK setting ++ //RTPRINT(FINIT, INIT_IQK, ("Path-A IQK setting!\n")); ++ PHY_SetBBReg(pAdapter, 0xe30, bMaskDWord, 0x10008c1f); ++ PHY_SetBBReg(pAdapter, 0xe34, bMaskDWord, 0x10008c1f); ++ PHY_SetBBReg(pAdapter, 0xe38, bMaskDWord, 0x82140102); ++ ++ PHY_SetBBReg(pAdapter, 0xe3c, bMaskDWord, configPathB ? 0x28160202 : 0x28160502); ++ ++#if 1 ++ //path-B IQK setting ++ if(configPathB) ++ { ++ PHY_SetBBReg(pAdapter, 0xe50, bMaskDWord, 0x10008c22); ++ PHY_SetBBReg(pAdapter, 0xe54, bMaskDWord, 0x10008c22); ++ PHY_SetBBReg(pAdapter, 0xe58, bMaskDWord, 0x82140102); ++ PHY_SetBBReg(pAdapter, 0xe5c, bMaskDWord, 0x28160202); ++ } ++#endif ++ //LO calibration setting ++ //RTPRINT(FINIT, INIT_IQK, ("LO calibration setting!\n")); ++ PHY_SetBBReg(pAdapter, 0xe4c, bMaskDWord, 0x001028d1); ++ ++ //One shot, path A LOK & IQK ++ //RTPRINT(FINIT, INIT_IQK, ("One shot, path A LOK & IQK!\n")); ++ PHY_SetBBReg(pAdapter, 0xe48, bMaskDWord, 0xf9000000); ++ PHY_SetBBReg(pAdapter, 0xe48, bMaskDWord, 0xf8000000); ++ ++ // delay x ms ++ //RTPRINT(FINIT, INIT_IQK, ("Delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME)); ++ rtw_udelay_os(IQK_DELAY_TIME*1000);//PlatformStallExecution(IQK_DELAY_TIME*1000); ++ ++ // Check failed ++ regEAC = PHY_QueryBBReg(pAdapter, 0xeac, bMaskDWord); ++ //RTPRINT(FINIT, INIT_IQK, ("0xeac = 0x%x\n", regEAC)); ++ regE94 = PHY_QueryBBReg(pAdapter, 0xe94, bMaskDWord); ++ //RTPRINT(FINIT, INIT_IQK, ("0xe94 = 0x%x\n", regE94)); ++ regE9C= PHY_QueryBBReg(pAdapter, 0xe9c, bMaskDWord); ++ //RTPRINT(FINIT, INIT_IQK, ("0xe9c = 0x%x\n", regE9C)); ++ regEA4= PHY_QueryBBReg(pAdapter, 0xea4, bMaskDWord); ++ //RTPRINT(FINIT, INIT_IQK, ("0xea4 = 0x%x\n", regEA4)); ++ ++ if(!(regEAC & BIT28) && ++ (((regE94 & 0x03FF0000)>>16) != 0x142) && ++ (((regE9C & 0x03FF0000)>>16) != 0x42) ) ++ result |= 0x01; ++ else //if Tx not OK, ignore Rx ++ return result; ++ ++ if(!(regEAC & BIT27) && //if Tx is OK, check whether Rx is OK ++ (((regEA4 & 0x03FF0000)>>16) != 0x132) && ++ (((regEAC & 0x03FF0000)>>16) != 0x36)) ++ result |= 0x02; ++ else ++ DBG_8192C("Path A Rx IQK fail!!\n"); ++ ++ return result; ++ ++ ++} ++ ++static u8 //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK ++_PHY_PathB_IQK( ++ IN PADAPTER pAdapter ++ ) ++{ ++ u32 regEAC, regEB4, regEBC, regEC4, regECC; ++ u8 result = 0x00; ++ //RTPRINT(FINIT, INIT_IQK, ("Path B IQK!\n")); ++#if 0 ++ //path-B IQK setting ++ RTPRINT(FINIT, INIT_IQK, ("Path-B IQK setting!\n")); ++ PHY_SetBBReg(pAdapter, 0xe50, bMaskDWord, 0x10008c22); ++ PHY_SetBBReg(pAdapter, 0xe54, bMaskDWord, 0x10008c22); ++ PHY_SetBBReg(pAdapter, 0xe58, bMaskDWord, 0x82140102); ++ PHY_SetBBReg(pAdapter, 0xe5c, bMaskDWord, 0x28160202); ++ ++ //LO calibration setting ++ RTPRINT(FINIT, INIT_IQK, ("LO calibration setting!\n")); ++ PHY_SetBBReg(pAdapter, 0xe4c, bMaskDWord, 0x001028d1); ++#endif ++ //One shot, path B LOK & IQK ++ //RTPRINT(FINIT, INIT_IQK, ("One shot, path A LOK & IQK!\n")); ++ PHY_SetBBReg(pAdapter, 0xe60, bMaskDWord, 0x00000002); ++ PHY_SetBBReg(pAdapter, 0xe60, bMaskDWord, 0x00000000); ++ ++ // delay x ms ++ //RTPRINT(FINIT, INIT_IQK, ("Delay %d ms for One shot, path B LOK & IQK.\n", IQK_DELAY_TIME)); ++ rtw_udelay_os(IQK_DELAY_TIME*1000);//PlatformStallExecution(IQK_DELAY_TIME*1000); ++ ++ // Check failed ++ regEAC = PHY_QueryBBReg(pAdapter, 0xeac, bMaskDWord); ++ //RTPRINT(FINIT, INIT_IQK, ("0xeac = 0x%x\n", regEAC)); ++ regEB4 = PHY_QueryBBReg(pAdapter, 0xeb4, bMaskDWord); ++ //RTPRINT(FINIT, INIT_IQK, ("0xeb4 = 0x%x\n", regEB4)); ++ regEBC= PHY_QueryBBReg(pAdapter, 0xebc, bMaskDWord); ++ //RTPRINT(FINIT, INIT_IQK, ("0xebc = 0x%x\n", regEBC)); ++ regEC4= PHY_QueryBBReg(pAdapter, 0xec4, bMaskDWord); ++ //RTPRINT(FINIT, INIT_IQK, ("0xec4 = 0x%x\n", regEC4)); ++ regECC= PHY_QueryBBReg(pAdapter, 0xecc, bMaskDWord); ++ //RTPRINT(FINIT, INIT_IQK, ("0xecc = 0x%x\n", regECC)); ++ ++ if(!(regEAC & BIT31) && ++ (((regEB4 & 0x03FF0000)>>16) != 0x142) && ++ (((regEBC & 0x03FF0000)>>16) != 0x42)) ++ result |= 0x01; ++ else ++ return result; ++ ++ if(!(regEAC & BIT30) && ++ (((regEC4 & 0x03FF0000)>>16) != 0x132) && ++ (((regECC & 0x03FF0000)>>16) != 0x36)) ++ result |= 0x02; ++ else ++ DBG_8192C("Path B Rx IQK fail!!\n"); ++ ++ ++ return result; ++ ++} ++ ++static VOID ++_PHY_PathAFillIQKMatrix( ++ IN PADAPTER pAdapter, ++ IN BOOLEAN bIQKOK, ++ IN int result[][8], ++ IN u8 final_candidate, ++ IN BOOLEAN bTxOnly ++ ) ++{ ++ u32 Oldval_0, X, TX0_A, reg; ++ int Y, TX0_C; ++ ++ DBG_8192C("Path A IQ Calibration %s !\n",(bIQKOK)?"Success":"Failed"); ++ ++ if(final_candidate == 0xFF) ++ return; ++ else if(bIQKOK) ++ { ++ Oldval_0 = (PHY_QueryBBReg(pAdapter, rOFDM0_XATxIQImbalance, bMaskDWord) >> 22) & 0x3FF; ++ ++ X = result[final_candidate][0]; ++ if ((X & 0x00000200) != 0) ++ X = X | 0xFFFFFC00; ++ TX0_A = (X * Oldval_0) >> 8; ++ //RTPRINT(FINIT, INIT_IQK, ("X = 0x%lx, TX0_A = 0x%lx, Oldval_0 0x%lx\n", X, TX0_A, Oldval_0)); ++ PHY_SetBBReg(pAdapter, rOFDM0_XATxIQImbalance, 0x3FF, TX0_A); ++ PHY_SetBBReg(pAdapter, rOFDM0_ECCAThreshold, BIT(31), ((X* Oldval_0>>7) & 0x1)); ++ ++ Y = result[final_candidate][1]; ++ if ((Y & 0x00000200) != 0) ++ Y = Y | 0xFFFFFC00; ++ TX0_C = (Y * Oldval_0) >> 8; ++ //RTPRINT(FINIT, INIT_IQK, ("Y = 0x%lx, TX = 0x%lx\n", Y, TX0_C)); ++ PHY_SetBBReg(pAdapter, rOFDM0_XCTxAFE, 0xF0000000, ((TX0_C&0x3C0)>>6)); ++ PHY_SetBBReg(pAdapter, rOFDM0_XATxIQImbalance, 0x003F0000, (TX0_C&0x3F)); ++ PHY_SetBBReg(pAdapter, rOFDM0_ECCAThreshold, BIT(29), ((Y* Oldval_0>>7) & 0x1)); ++ ++ if(bTxOnly) ++ { ++ DBG_8192C("_PHY_PathAFillIQKMatrix only Tx OK\n"); ++ return; ++ } ++ ++ reg = result[final_candidate][2]; ++ PHY_SetBBReg(pAdapter, rOFDM0_XARxIQImbalance, 0x3FF, reg); ++ ++ reg = result[final_candidate][3] & 0x3F; ++ PHY_SetBBReg(pAdapter, rOFDM0_XARxIQImbalance, 0xFC00, reg); ++ ++ reg = (result[final_candidate][3] >> 6) & 0xF; ++ PHY_SetBBReg(pAdapter, 0xca0, 0xF0000000, reg); ++ } ++} ++ ++static VOID ++_PHY_PathBFillIQKMatrix( ++ IN PADAPTER pAdapter, ++ IN BOOLEAN bIQKOK, ++ IN int result[][8], ++ IN u8 final_candidate, ++ IN BOOLEAN bTxOnly //do Tx only ++ ) ++{ ++ u32 Oldval_1, X, TX1_A, reg; ++ int Y, TX1_C; ++ ++ DBG_8192C("Path B IQ Calibration %s !\n",(bIQKOK)?"Success":"Failed"); ++ ++ if(final_candidate == 0xFF) ++ return; ++ else if(bIQKOK) ++ { ++ Oldval_1 = (PHY_QueryBBReg(pAdapter, rOFDM0_XBTxIQImbalance, bMaskDWord) >> 22) & 0x3FF; ++ ++ X = result[final_candidate][4]; ++ if ((X & 0x00000200) != 0) ++ X = X | 0xFFFFFC00; ++ TX1_A = (X * Oldval_1) >> 8; ++ //RTPRINT(FINIT, INIT_IQK, ("X = 0x%lx, TX1_A = 0x%lx\n", X, TX1_A)); ++ PHY_SetBBReg(pAdapter, rOFDM0_XBTxIQImbalance, 0x3FF, TX1_A); ++ PHY_SetBBReg(pAdapter, rOFDM0_ECCAThreshold, BIT(27), ((X* Oldval_1>>7) & 0x1)); ++ ++ Y = result[final_candidate][5]; ++ if ((Y & 0x00000200) != 0) ++ Y = Y | 0xFFFFFC00; ++ TX1_C = (Y * Oldval_1) >> 8; ++ //RTPRINT(FINIT, INIT_IQK, ("Y = 0x%lx, TX1_C = 0x%lx\n", Y, TX1_C)); ++ PHY_SetBBReg(pAdapter, rOFDM0_XDTxAFE, 0xF0000000, ((TX1_C&0x3C0)>>6)); ++ PHY_SetBBReg(pAdapter, rOFDM0_XBTxIQImbalance, 0x003F0000, (TX1_C&0x3F)); ++ PHY_SetBBReg(pAdapter, rOFDM0_ECCAThreshold, BIT(25), ((Y* Oldval_1>>7) & 0x1)); ++ ++ if(bTxOnly) ++ return; ++ ++ reg = result[final_candidate][6]; ++ PHY_SetBBReg(pAdapter, rOFDM0_XBRxIQImbalance, 0x3FF, reg); ++ ++ reg = result[final_candidate][7] & 0x3F; ++ PHY_SetBBReg(pAdapter, rOFDM0_XBRxIQImbalance, 0xFC00, reg); ++ ++ reg = (result[final_candidate][7] >> 6) & 0xF; ++ PHY_SetBBReg(pAdapter, rOFDM0_AGCRSSITable, 0x0000F000, reg); ++ } ++} ++ ++static VOID ++_PHY_SaveADDARegisters( ++ IN PADAPTER pAdapter, ++ IN u32* ADDAReg, ++ IN u32* ADDABackup, ++ IN u32 RegisterNum ++ ) ++{ ++ u32 i; ++ ++ //RTPRINT(FINIT, INIT_IQK, ("Save ADDA parameters.\n")); ++ for( i = 0 ; i < RegisterNum ; i++){ ++ ADDABackup[i] = PHY_QueryBBReg(pAdapter, ADDAReg[i], bMaskDWord); ++ } ++} ++ ++static VOID ++_PHY_SaveMACRegisters( ++ IN PADAPTER pAdapter, ++ IN u32* MACReg, ++ IN u32* MACBackup ++ ) ++{ ++ u32 i; ++ ++ //RTPRINT(FINIT, INIT_IQK, ("Save MAC parameters.\n")); ++ for( i = 0 ; i < (IQK_MAC_REG_NUM - 1); i++){ ++ MACBackup[i] =rtw_read8(pAdapter, MACReg[i]); ++ } ++ MACBackup[i] = rtw_read32(pAdapter, MACReg[i]); ++ ++} ++ ++static VOID ++_PHY_ReloadADDARegisters( ++ IN PADAPTER pAdapter, ++ IN u32* ADDAReg, ++ IN u32* ADDABackup, ++ IN u32 RegiesterNum ++ ) ++{ ++ u32 i; ++ ++ //RTPRINT(FINIT, INIT_IQK, ("Reload ADDA power saving parameters !\n")); ++ for(i = 0 ; i < RegiesterNum ; i++){ ++ PHY_SetBBReg(pAdapter, ADDAReg[i], bMaskDWord, ADDABackup[i]); ++ } ++} ++ ++static VOID ++_PHY_ReloadMACRegisters( ++ IN PADAPTER pAdapter, ++ IN u32* MACReg, ++ IN u32* MACBackup ++ ) ++{ ++ u32 i; ++ ++ //RTPRINT(FINIT, INIT_IQK, ("Reload MAC parameters !\n")); ++ for(i = 0 ; i < (IQK_MAC_REG_NUM - 1); i++){ ++ rtw_write8(pAdapter, MACReg[i], (u8)MACBackup[i]); ++ } ++ rtw_write32(pAdapter, MACReg[i], MACBackup[i]); ++} ++ ++static VOID ++_PHY_PathADDAOn( ++ IN PADAPTER pAdapter, ++ IN u32* ADDAReg, ++ IN BOOLEAN isPathAOn, ++ IN BOOLEAN is2T ++ ) ++{ ++ u32 pathOn; ++ u32 i; ++ ++ //RTPRINT(FINIT, INIT_IQK, ("ADDA ON.\n")); ++ ++ pathOn = isPathAOn ? 0x04db25a4 : 0x0b1b25a4; ++ if(_FALSE == is2T){ ++ pathOn = 0x0bdb25a0; ++ PHY_SetBBReg(pAdapter, ADDAReg[0], bMaskDWord, 0x0b1b25a0); ++ } ++ else{ ++ PHY_SetBBReg(pAdapter, ADDAReg[0], bMaskDWord, pathOn); ++ } ++ ++ for( i = 1 ; i < IQK_ADDA_REG_NUM ; i++){ ++ PHY_SetBBReg(pAdapter, ADDAReg[i], bMaskDWord, pathOn); ++ } ++ ++} ++ ++static VOID ++_PHY_MACSettingCalibration( ++ IN PADAPTER pAdapter, ++ IN u32* MACReg, ++ IN u32* MACBackup ++ ) ++{ ++ u32 i = 0; ++ ++ //RTPRINT(FINIT, INIT_IQK, ("MAC settings for Calibration.\n")); ++ ++ rtw_write8(pAdapter, MACReg[i], 0x3F); ++ ++ for(i = 1 ; i < (IQK_MAC_REG_NUM - 1); i++){ ++ rtw_write8(pAdapter, MACReg[i], (u8)(MACBackup[i]&(~BIT3))); ++ } ++ rtw_write8(pAdapter, MACReg[i], (u8)(MACBackup[i]&(~BIT5))); ++ ++} ++ ++static VOID ++_PHY_PathAStandBy( ++ IN PADAPTER pAdapter ++ ) ++{ ++ //RTPRINT(FINIT, INIT_IQK, ("Path-A standby mode!\n")); ++ ++ PHY_SetBBReg(pAdapter, 0xe28, bMaskDWord, 0x0); ++ PHY_SetBBReg(pAdapter, 0x840, bMaskDWord, 0x00010000); ++ PHY_SetBBReg(pAdapter, 0xe28, bMaskDWord, 0x80800000); ++} ++ ++static VOID ++_PHY_PIModeSwitch( ++ IN PADAPTER pAdapter, ++ IN BOOLEAN PIMode ++ ) ++{ ++ u32 mode; ++ ++ //RTPRINT(FINIT, INIT_IQK, ("BB Switch to %s mode!\n", (PIMode ? "PI" : "SI"))); ++ ++ mode = PIMode ? 0x01000100 : 0x01000000; ++ PHY_SetBBReg(pAdapter, 0x820, bMaskDWord, mode); ++ PHY_SetBBReg(pAdapter, 0x828, bMaskDWord, mode); ++} ++ ++/* ++return _FALSE => do IQK again ++*/ ++static BOOLEAN ++_PHY_SimularityCompare( ++ IN PADAPTER pAdapter, ++ IN int result[][8], ++ IN u8 c1, ++ IN u8 c2 ++ ) ++{ ++ u32 i, j, diff, SimularityBitMap, bound = 0; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); ++ u8 final_candidate[2] = {0xFF, 0xFF}; //for path A and path B ++ BOOLEAN bResult = _TRUE, is2T = IS_92C_SERIAL( pHalData->VersionID); ++ ++ if(is2T) ++ bound = 8; ++ else ++ bound = 4; ++ ++ SimularityBitMap = 0; ++ ++ for( i = 0; i < bound; i++ ) ++ { ++ diff = (result[c1][i] > result[c2][i]) ? (result[c1][i] - result[c2][i]) : (result[c2][i] - result[c1][i]); ++ if (diff > MAX_TOLERANCE) ++ { ++ if((i == 2 || i == 6) && !SimularityBitMap) ++ { ++ if(result[c1][i]+result[c1][i+1] == 0) ++ final_candidate[(i/4)] = c2; ++ else if (result[c2][i]+result[c2][i+1] == 0) ++ final_candidate[(i/4)] = c1; ++ else ++ SimularityBitMap = SimularityBitMap|(1<dmpriv; ++ u32 i; ++ u8 PathAOK, PathBOK; ++ u32 ADDA_REG[IQK_ADDA_REG_NUM] = { 0x85c, 0xe6c, 0xe70, 0xe74, ++ 0xe78, 0xe7c, 0xe80, 0xe84, ++ 0xe88, 0xe8c, 0xed0, 0xed4, ++ 0xed8, 0xedc, 0xee0, 0xeec }; ++ ++ u32 IQK_MAC_REG[IQK_MAC_REG_NUM] = {0x522, 0x550, 0x551,0x040}; ++ ++ u32 IQK_BB_REG[IQK_BB_REG_NUM] = { ++ 0xc04, 0xc08, 0x874, 0xb68, 0xb6c, ++ 0x870, 0x860, 0x864, 0x800 ++ }; ++ ++#if MP_DRIVER ++ const u32 retryCount = 9; ++#else ++ const u32 retryCount = 2; ++#endif ++ ++ // Note: IQ calibration must be performed after loading ++ // PHY_REG.txt , and radio_a, radio_b.txt ++ ++ u32 bbvalue; ++ BOOLEAN isNormal = IS_NORMAL_CHIP(pHalData->VersionID); ++ ++ if(t==0) ++ { ++ bbvalue = PHY_QueryBBReg(pAdapter, 0x800, bMaskDWord); ++ //RTPRINT(FINIT, INIT_IQK, ("PHY_IQCalibrate()==>0x%08lx\n",bbvalue)); ++ ++ //RTPRINT(FINIT, INIT_IQK, ("IQ Calibration for %s\n", (is2T ? "2T2R" : "1T1R"))); ++ ++ // Save ADDA parameters, turn Path A ADDA on ++ _PHY_SaveADDARegisters(pAdapter, ADDA_REG, pdmpriv->ADDA_backup,IQK_ADDA_REG_NUM); ++ _PHY_SaveMACRegisters(pAdapter, IQK_MAC_REG, pdmpriv->IQK_MAC_backup); ++ _PHY_SaveADDARegisters(pAdapter, IQK_BB_REG, pdmpriv->IQK_BB_backup, IQK_BB_REG_NUM); ++ } ++ _PHY_PathADDAOn(pAdapter, ADDA_REG, _TRUE, is2T); ++ ++ if(t==0) ++ { ++ pdmpriv->bRfPiEnable = (u8)PHY_QueryBBReg(pAdapter, rFPGA0_XA_HSSIParameter1, BIT(8)); ++ } ++ ++ if(!pdmpriv->bRfPiEnable){ ++ // Switch BB to PI mode to do IQ Calibration. ++ _PHY_PIModeSwitch(pAdapter, _TRUE); ++ } ++ ++ PHY_SetBBReg(pAdapter, 0x800, BIT24, 0x00); ++ PHY_SetBBReg(pAdapter, 0xc04, bMaskDWord, 0x03a05600); ++ PHY_SetBBReg(pAdapter, 0xc08, bMaskDWord, 0x000800e4); ++ PHY_SetBBReg(pAdapter, 0x874, bMaskDWord, 0x22204000); ++ PHY_SetBBReg(pAdapter, 0x870, BIT10, 0x01); ++ PHY_SetBBReg(pAdapter, 0x870, BIT26, 0x01); ++ PHY_SetBBReg(pAdapter, 0x860, BIT10, 0x00); ++ PHY_SetBBReg(pAdapter, 0x864, BIT10, 0x00); ++ ++ if(is2T) ++ { ++ PHY_SetBBReg(pAdapter, 0x840, bMaskDWord, 0x00010000); ++ PHY_SetBBReg(pAdapter, 0x844, bMaskDWord, 0x00010000); ++ } ++ ++ //MAC settings ++ _PHY_MACSettingCalibration(pAdapter, IQK_MAC_REG, pdmpriv->IQK_MAC_backup); ++ ++ //Page B init ++ if(isNormal) ++ PHY_SetBBReg(pAdapter, 0xb68, bMaskDWord, 0x00080000); ++ else ++ PHY_SetBBReg(pAdapter, 0xb68, bMaskDWord, 0x0f600000); ++ ++ if(is2T) ++ { ++ if(isNormal) ++ PHY_SetBBReg(pAdapter, 0xb6c, bMaskDWord, 0x00080000); ++ else ++ PHY_SetBBReg(pAdapter, 0xb6c, bMaskDWord, 0x0f600000); ++ } ++ ++ // IQ calibration setting ++ //RTPRINT(FINIT, INIT_IQK, ("IQK setting!\n")); ++ PHY_SetBBReg(pAdapter, 0xe28, bMaskDWord, 0x80800000); ++ PHY_SetBBReg(pAdapter, 0xe40, bMaskDWord, 0x01007c00); ++ PHY_SetBBReg(pAdapter, 0xe44, bMaskDWord, 0x01004800); ++ ++ for(i = 0 ; i < retryCount ; i++){ ++ PathAOK = _PHY_PathA_IQK(pAdapter, is2T); ++ if(PathAOK == 0x03){ ++ DBG_8192C("Path A IQK Success!!\n"); ++ result[t][0] = (PHY_QueryBBReg(pAdapter, 0xe94, bMaskDWord)&0x3FF0000)>>16; ++ result[t][1] = (PHY_QueryBBReg(pAdapter, 0xe9c, bMaskDWord)&0x3FF0000)>>16; ++ result[t][2] = (PHY_QueryBBReg(pAdapter, 0xea4, bMaskDWord)&0x3FF0000)>>16; ++ result[t][3] = (PHY_QueryBBReg(pAdapter, 0xeac, bMaskDWord)&0x3FF0000)>>16; ++ break; ++ } ++ else if (i == (retryCount-1) && PathAOK == 0x01) //Tx IQK OK ++ { ++ DBG_8192C("Path A IQK Only Tx Success!!\n"); ++ ++ result[t][0] = (PHY_QueryBBReg(pAdapter, 0xe94, bMaskDWord)&0x3FF0000)>>16; ++ result[t][1] = (PHY_QueryBBReg(pAdapter, 0xe9c, bMaskDWord)&0x3FF0000)>>16; ++ } ++ } ++ ++ if(0x00 == PathAOK){ ++ DBG_8192C("Path A IQK failed!!\n"); ++ } ++ ++ if(is2T){ ++ _PHY_PathAStandBy(pAdapter); ++ ++ // Turn Path B ADDA on ++ _PHY_PathADDAOn(pAdapter, ADDA_REG, _FALSE, is2T); ++ ++ for(i = 0 ; i < retryCount ; i++){ ++ PathBOK = _PHY_PathB_IQK(pAdapter); ++ if(PathBOK == 0x03){ ++ DBG_8192C("Path B IQK Success!!\n"); ++ result[t][4] = (PHY_QueryBBReg(pAdapter, 0xeb4, bMaskDWord)&0x3FF0000)>>16; ++ result[t][5] = (PHY_QueryBBReg(pAdapter, 0xebc, bMaskDWord)&0x3FF0000)>>16; ++ result[t][6] = (PHY_QueryBBReg(pAdapter, 0xec4, bMaskDWord)&0x3FF0000)>>16; ++ result[t][7] = (PHY_QueryBBReg(pAdapter, 0xecc, bMaskDWord)&0x3FF0000)>>16; ++ break; ++ } ++ else if (i == (retryCount - 1) && PathBOK == 0x01) //Tx IQK OK ++ { ++ DBG_8192C("Path B Only Tx IQK Success!!\n"); ++ result[t][4] = (PHY_QueryBBReg(pAdapter, 0xeb4, bMaskDWord)&0x3FF0000)>>16; ++ result[t][5] = (PHY_QueryBBReg(pAdapter, 0xebc, bMaskDWord)&0x3FF0000)>>16; ++ } ++ } ++ ++ if(0x00 == PathBOK){ ++ DBG_8192C("Path B IQK failed!!\n"); ++ } ++ } ++ ++ //Back to BB mode, load original value ++ //RTPRINT(FINIT, INIT_IQK, ("IQK:Back to BB mode, load original value!\n")); ++ PHY_SetBBReg(pAdapter, 0xe28, bMaskDWord, 0); ++ ++ if(t!=0) ++ { ++ if(!pdmpriv->bRfPiEnable){ ++ // Switch back BB to SI mode after finish IQ Calibration. ++ _PHY_PIModeSwitch(pAdapter, _FALSE); ++ } ++ ++ // Reload ADDA power saving parameters ++ _PHY_ReloadADDARegisters(pAdapter, ADDA_REG, pdmpriv->ADDA_backup, IQK_ADDA_REG_NUM); ++ ++ // Reload MAC parameters ++ _PHY_ReloadMACRegisters(pAdapter, IQK_MAC_REG, pdmpriv->IQK_MAC_backup); ++ ++ // Reload BB parameters ++ _PHY_ReloadADDARegisters(pAdapter, IQK_BB_REG, pdmpriv->IQK_BB_backup, IQK_BB_REG_NUM); ++ ++ // Restore RX initial gain ++ PHY_SetBBReg(pAdapter, 0x840, bMaskDWord, 0x00032ed3); ++ if(is2T){ ++ PHY_SetBBReg(pAdapter, 0x844, bMaskDWord, 0x00032ed3); ++ } ++ ++ //load 0xe30 IQC default value ++ PHY_SetBBReg(pAdapter, 0xe30, bMaskDWord, 0x01008c00); ++ PHY_SetBBReg(pAdapter, 0xe34, bMaskDWord, 0x01008c00); ++ ++ } ++ //RTPRINT(FINIT, INIT_IQK, ("_PHY_IQCalibrate() <==\n")); ++ ++} ++ ++ ++static VOID ++_PHY_LCCalibrate( ++ IN PADAPTER pAdapter, ++ IN BOOLEAN is2T ++ ) ++{ ++ u8 tmpReg; ++ u32 RF_Amode = 0, RF_Bmode = 0, LC_Cal; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); ++ BOOLEAN isNormal = IS_NORMAL_CHIP(pHalData->VersionID); ++ ++ //Check continuous TX and Packet TX ++ tmpReg = rtw_read8(pAdapter, 0xd03); ++ ++ if((tmpReg&0x70) != 0) //Deal with contisuous TX case ++ rtw_write8(pAdapter, 0xd03, tmpReg&0x8F); //disable all continuous TX ++ else // Deal with Packet TX case ++ rtw_write8(pAdapter, REG_TXPAUSE, 0xFF); // block all queues ++ ++ if((tmpReg&0x70) != 0) ++ { ++ //1. Read original RF mode ++ //Path-A ++ RF_Amode = PHY_QueryRFReg(pAdapter, RF90_PATH_A, 0x00, bMask12Bits); ++ ++ //Path-B ++ if(is2T) ++ RF_Bmode = PHY_QueryRFReg(pAdapter, RF90_PATH_B, 0x00, bMask12Bits); ++ ++ //2. Set RF mode = standby mode ++ //Path-A ++ PHY_SetRFReg(pAdapter, RF90_PATH_A, 0x00, bMask12Bits, (RF_Amode&0x8FFFF)|0x10000); ++ ++ //Path-B ++ if(is2T) ++ PHY_SetRFReg(pAdapter, RF90_PATH_B, 0x00, bMask12Bits, (RF_Bmode&0x8FFFF)|0x10000); ++ } ++ ++ //3. Read RF reg18 ++ LC_Cal = PHY_QueryRFReg(pAdapter, RF90_PATH_A, 0x18, bMask12Bits); ++ ++ //4. Set LC calibration begin ++ PHY_SetRFReg(pAdapter, RF90_PATH_A, 0x18, bMask12Bits, LC_Cal|0x08000); ++ ++ if(isNormal) { ++ #ifdef CONFIG_LONG_DELAY_ISSUE ++ rtw_msleep_os(100); ++ #else ++ rtw_mdelay_os(100); ++ #endif ++ } ++ else ++ rtw_mdelay_os(3); ++ ++ //Restore original situation ++ if((tmpReg&0x70) != 0) //Deal with contisuous TX case ++ { ++ //Path-A ++ rtw_write8(pAdapter, 0xd03, tmpReg); ++ PHY_SetRFReg(pAdapter, RF90_PATH_A, 0x00, bMask12Bits, RF_Amode); ++ ++ //Path-B ++ if(is2T) ++ PHY_SetRFReg(pAdapter, RF90_PATH_B, 0x00, bMask12Bits, RF_Bmode); ++ } ++ else // Deal with Packet TX case ++ { ++ rtw_write8(pAdapter, REG_TXPAUSE, 0x00); ++ } ++ ++} ++ ++ ++//Analog Pre-distortion calibration ++#define APK_BB_REG_NUM 8 ++#define APK_CURVE_REG_NUM 4 ++#define PATH_NUM 2 ++ ++static VOID ++_PHY_APCalibrate( ++ IN PADAPTER pAdapter, ++ IN char delta, ++ IN BOOLEAN is2T ++ ) ++{ ++#if 1//(PLATFORM == PLATFORM_WINDOWS)//??? ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); ++ struct dm_priv *pdmpriv = &pHalData->dmpriv; ++ ++ u32 regD[PATH_NUM]; ++ u32 tmpReg, index, offset, path, i, pathbound = PATH_NUM, apkbound; ++ ++ u32 BB_backup[APK_BB_REG_NUM]; ++ u32 BB_REG[APK_BB_REG_NUM] = { ++ 0x904, 0xc04, 0x800, 0xc08, 0x874, ++ 0x870, 0x860, 0x864 }; ++ u32 BB_AP_MODE[APK_BB_REG_NUM] = { ++ 0x00000020, 0x00a05430, 0x02040000, ++ 0x000800e4, 0x00204000 }; ++ u32 BB_normal_AP_MODE[APK_BB_REG_NUM] = { ++ 0x00000020, 0x00a05430, 0x02040000, ++ 0x000800e4, 0x22204000 }; ++ ++ u32 AFE_backup[IQK_ADDA_REG_NUM]; ++ u32 AFE_REG[IQK_ADDA_REG_NUM] = { ++ 0x85c, 0xe6c, 0xe70, 0xe74, 0xe78, ++ 0xe7c, 0xe80, 0xe84, 0xe88, 0xe8c, ++ 0xed0, 0xed4, 0xed8, 0xedc, 0xee0, ++ 0xeec}; ++ ++ u32 MAC_backup[IQK_MAC_REG_NUM]; ++ u32 MAC_REG[IQK_MAC_REG_NUM] = { ++ 0x522, 0x550, 0x551, 0x040}; ++ ++ u32 APK_RF_init_value[PATH_NUM][APK_BB_REG_NUM] = { ++ {0x0852c, 0x1852c, 0x5852c, 0x1852c, 0x5852c}, ++ {0x2852e, 0x0852e, 0x3852e, 0x0852e, 0x0852e} ++ }; ++ ++ u32 APK_normal_RF_init_value[PATH_NUM][APK_BB_REG_NUM] = { ++ {0x0852c, 0x0a52c, 0x3a52c, 0x5a52c, 0x5a52c}, //path settings equal to path b settings ++ {0x0852c, 0x0a52c, 0x5a52c, 0x5a52c, 0x5a52c} ++ }; ++ ++ u32 APK_RF_value_0[PATH_NUM][APK_BB_REG_NUM] = { ++ {0x52019, 0x52014, 0x52013, 0x5200f, 0x5208d}, ++ {0x5201a, 0x52019, 0x52016, 0x52033, 0x52050} ++ }; ++ ++ u32 APK_normal_RF_value_0[PATH_NUM][APK_BB_REG_NUM] = { ++ {0x52019, 0x52017, 0x52010, 0x5200d, 0x5206a}, //path settings equal to path b settings ++ {0x52019, 0x52017, 0x52010, 0x5200d, 0x5206a} ++ }; ++ ++ u32 APK_RF_value_A[PATH_NUM][APK_BB_REG_NUM] = { ++ {0x1adb0, 0x1adb0, 0x1ada0, 0x1ad90, 0x1ad80}, ++ {0x00fb0, 0x00fb0, 0x00fa0, 0x00f90, 0x00f80} ++ }; ++ ++ u32 AFE_on_off[PATH_NUM] = { ++ 0x04db25a4, 0x0b1b25a4}; //path A on path B off / path A off path B on ++ ++ u32 APK_offset[PATH_NUM] = { ++ 0xb68, 0xb6c}; ++ ++ u32 APK_normal_offset[PATH_NUM] = { ++ 0xb28, 0xb98}; ++ ++ u32 APK_value[PATH_NUM] = { ++ 0x92fc0000, 0x12fc0000}; ++ ++ u32 APK_normal_value[PATH_NUM] = { ++ 0x92680000, 0x12680000}; ++ ++ char APK_delta_mapping[APK_BB_REG_NUM][13] = { ++ {-4, -3, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6}, ++ {-4, -3, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6}, ++ {-6, -4, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6}, ++ {-1, -1, -1, -1, -1, -1, 0, 1, 2, 3, 4, 5, 6}, ++ {-11, -9, -7, -5, -3, -1, 0, 0, 0, 0, 0, 0, 0} ++ }; ++ ++ u32 APK_normal_setting_value_1[13] = { ++ 0x01017018, 0xf7ed8f84, 0x1b1a1816, 0x2522201e, 0x322e2b28, ++ 0x433f3a36, 0x5b544e49, 0x7b726a62, 0xa69a8f84, 0xdfcfc0b3, ++ 0x12680000, 0x00880000, 0x00880000 ++ }; ++ ++ u32 APK_normal_setting_value_2[16] = { ++ 0x01c7021d, 0x01670183, 0x01000123, 0x00bf00e2, 0x008d00a3, ++ 0x0068007b, 0x004d0059, 0x003a0042, 0x002b0031, 0x001f0025, ++ 0x0017001b, 0x00110014, 0x000c000f, 0x0009000b, 0x00070008, ++ 0x00050006 ++ }; ++ ++ u32 APK_result[PATH_NUM][APK_BB_REG_NUM]; //val_1_1a, val_1_2a, val_2a, val_3a, val_4a ++ u32 AP_curve[PATH_NUM][APK_CURVE_REG_NUM]; ++ ++ int BB_offset, delta_V, delta_offset; ++ ++ BOOLEAN isNormal = IS_NORMAL_CHIP(pHalData->VersionID); ++ ++#if (MP_DRIVER == 1) ++ PMPT_CONTEXT pMptCtx = &pAdapter->mppriv.MptCtx; ++ ++ pMptCtx->APK_bound[0] = 45; ++ pMptCtx->APK_bound[1] = 52; ++#endif ++ ++ //RTPRINT(FINIT, INIT_IQK, ("==>PHY_APCalibrate() delta %d\n", delta)); ++ ++ //RTPRINT(FINIT, INIT_IQK, ("AP Calibration for %s %s\n", (is2T ? "2T2R" : "1T1R"), (isNormal ? "Normal chip" : "Test chip"))); ++ ++ if(!is2T) ++ pathbound = 1; ++ ++ //2 FOR NORMAL CHIP SETTINGS ++ if(isNormal) ++ { ++// Temporarily do not allow normal driver to do the following settings because these offset ++// and value will cause RF internal PA to be unpredictably disabled by HW, such that RF Tx signal ++// will disappear after disable/enable card many times on 88CU. RF SD and DD have not find the ++// root cause, so we remove these actions temporarily. Added by tynli and SD3 Allen. 2010.05.31. ++#if (MP_DRIVER != 1) ++ return; ++#endif ++ ++ //settings adjust for normal chip ++ for(index = 0; index < PATH_NUM; index ++) ++ { ++ APK_offset[index] = APK_normal_offset[index]; ++ APK_value[index] = APK_normal_value[index]; ++ AFE_on_off[index] = 0x6fdb25a4; ++ } ++ ++ for(index = 0; index < APK_BB_REG_NUM; index ++) ++ { ++ for(path = 0; path < pathbound; path++) ++ { ++ APK_RF_init_value[path][index] = APK_normal_RF_init_value[path][index]; ++ APK_RF_value_0[path][index] = APK_normal_RF_value_0[path][index]; ++ } ++ BB_AP_MODE[index] = BB_normal_AP_MODE[index]; ++ } ++ ++ apkbound = 6; ++ } ++ else ++ { ++ PHY_SetBBReg(pAdapter, 0xb68, bMaskDWord, 0x0fe00000); ++ if(is2T) ++ PHY_SetBBReg(pAdapter, 0xb68, bMaskDWord, 0x0fe00000); ++ apkbound = 12; ++ } ++ ++ //save BB default value ++ for(index = 0; index < APK_BB_REG_NUM ; index++) ++ { ++ if(index == 0 && isNormal) //skip ++ continue; ++ BB_backup[index] = PHY_QueryBBReg(pAdapter, BB_REG[index], bMaskDWord); ++ } ++ ++ //save MAC default value ++ _PHY_SaveMACRegisters(pAdapter, MAC_REG, MAC_backup); ++ ++ //save AFE default value ++ _PHY_SaveADDARegisters(pAdapter, AFE_REG, AFE_backup,16); ++ ++ for(path = 0; path < pathbound; path++) ++ { ++ //save old AP curve ++ if(isNormal) ++ { ++ if(path == RF90_PATH_A) ++ { ++ //path A APK ++ //load APK setting ++ //path-A ++ offset = 0xb00; ++ for(index = 0; index < 11; index ++) ++ { ++ PHY_SetBBReg(pAdapter, offset, bMaskDWord, APK_normal_setting_value_1[index]); ++ //RTPRINT(FINIT, INIT_IQK, ("PHY_APCalibrate() offset 0x%x value 0x%x\n", offset, PHY_QueryBBReg(pAdapter, offset, bMaskDWord))); ++ ++ offset += 0x04; ++ } ++ ++ PHY_SetBBReg(pAdapter, 0xb98, bMaskDWord, 0x12680000); ++ ++ offset = 0xb68; ++ for(; index < 13; index ++) ++ { ++ PHY_SetBBReg(pAdapter, offset, bMaskDWord, APK_normal_setting_value_1[index]); ++ //RTPRINT(FINIT, INIT_IQK, ("PHY_APCalibrate() offset 0x%x value 0x%x\n", offset, PHY_QueryBBReg(pAdapter, offset, bMaskDWord))); ++ ++ offset += 0x04; ++ } ++ ++ //page-B1 ++ PHY_SetBBReg(pAdapter, 0xe28, bMaskDWord, 0x40000000); ++ ++ //path A ++ offset = 0xb00; ++ for(index = 0; index < 16; index++) ++ { ++ PHY_SetBBReg(pAdapter, offset, bMaskDWord, APK_normal_setting_value_2[index]); ++ //RTPRINT(FINIT, INIT_IQK, ("PHY_APCalibrate() offset 0x%x value 0x%x\n", offset, PHY_QueryBBReg(pAdapter, offset, bMaskDWord))); ++ ++ offset += 0x04; ++ } ++ PHY_SetBBReg(pAdapter, 0xe28, bMaskDWord, 0x00000000); ++ } ++ else if(path == RF90_PATH_B) ++ { ++ //path B APK ++ //load APK setting ++ //path-B ++ offset = 0xb70; ++ for(index = 0; index < 10; index ++) ++ { ++ PHY_SetBBReg(pAdapter, offset, bMaskDWord, APK_normal_setting_value_1[index]); ++ //RTPRINT(FINIT, INIT_IQK, ("PHY_APCalibrate() offset 0x%x value 0x%x\n", offset, PHY_QueryBBReg(pAdapter, offset, bMaskDWord))); ++ ++ offset += 0x04; ++ } ++ PHY_SetBBReg(pAdapter, 0xb28, bMaskDWord, 0x12680000); ++ ++ PHY_SetBBReg(pAdapter, 0xb98, bMaskDWord, 0x12680000); ++ ++ offset = 0xb68; ++ index = 11; ++ for(; index < 13; index ++) //offset 0xb68, 0xb6c ++ { ++ PHY_SetBBReg(pAdapter, offset, bMaskDWord, APK_normal_setting_value_1[index]); ++ //RTPRINT(FINIT, INIT_IQK, ("PHY_APCalibrate() offset 0x%x value 0x%x\n", offset, PHY_QueryBBReg(pAdapter, offset, bMaskDWord))); ++ ++ offset += 0x04; ++ } ++ ++ //page-B1 ++ PHY_SetBBReg(pAdapter, 0xe28, bMaskDWord, 0x40000000); ++ ++ //path B ++ offset = 0xb60; ++ for(index = 0; index < 16; index++) ++ { ++ PHY_SetBBReg(pAdapter, offset, bMaskDWord, APK_normal_setting_value_2[index]); ++ //RTPRINT(FINIT, INIT_IQK, ("PHY_APCalibrate() offset 0x%x value 0x%x\n", offset, PHY_QueryBBReg(pAdapter, offset, bMaskDWord))); ++ ++ offset += 0x04; ++ } ++ PHY_SetBBReg(pAdapter, 0xe28, bMaskDWord, 0x00000000); ++ } ++ ++#if 0 ++ tmpReg = PHY_QueryRFReg(pAdapter, (RF90_RADIO_PATH_E)path, 0x3, bMaskDWord); ++ AP_curve[path][0] = tmpReg & 0x1F; //[4:0] ++ ++ tmpReg = PHY_QueryRFReg(pAdapter, (RF90_RADIO_PATH_E)path, 0x4, bMaskDWord); ++ AP_curve[path][1] = (tmpReg & 0xF8000) >> 15; //[19:15] ++ AP_curve[path][2] = (tmpReg & 0x7C00) >> 10; //[14:10] ++ AP_curve[path][3] = (tmpReg & 0x3E0) >> 5; //[9:5] ++#endif ++ } ++ else ++ { ++ tmpReg = PHY_QueryRFReg(pAdapter, (RF90_RADIO_PATH_E)path, 0xe, bMaskDWord); ++ ++ AP_curve[path][0] = (tmpReg & 0xF8000) >> 15; //[19:15] ++ AP_curve[path][1] = (tmpReg & 0x7C00) >> 10; //[14:10] ++ AP_curve[path][2] = (tmpReg & 0x3E0) >> 5; //[9:5] ++ AP_curve[path][3] = tmpReg & 0x1F; //[4:0] ++ } ++ ++ //save RF default value ++ regD[path] = PHY_QueryRFReg(pAdapter, (RF90_RADIO_PATH_E)path, 0xd, bMaskDWord); ++ ++ //Path A AFE all on, path B AFE All off or vise versa ++ for(index = 0; index < IQK_ADDA_REG_NUM ; index++) ++ PHY_SetBBReg(pAdapter, AFE_REG[index], bMaskDWord, AFE_on_off[path]); ++ //RTPRINT(FINIT, INIT_IQK, ("PHY_APCalibrate() offset 0xe70 %x\n", PHY_QueryBBReg(pAdapter, 0xe70, bMaskDWord))); ++ ++ //BB to AP mode ++ if(path == 0) ++ { ++ for(index = 0; index < APK_BB_REG_NUM ; index++) ++ { ++ if(index == 0 && isNormal) //skip ++ continue; ++ else if (index < 5) ++ PHY_SetBBReg(pAdapter, BB_REG[index], bMaskDWord, BB_AP_MODE[index]); ++ else if (BB_REG[index] == 0x870) ++ PHY_SetBBReg(pAdapter, BB_REG[index], bMaskDWord, BB_backup[index]|BIT10|BIT26); ++ else ++ PHY_SetBBReg(pAdapter, BB_REG[index], BIT10, 0x0); ++ } ++ PHY_SetBBReg(pAdapter, 0xe30, bMaskDWord, 0x01008c00); ++ PHY_SetBBReg(pAdapter, 0xe34, bMaskDWord, 0x01008c00); ++ } ++ else //path B ++ { ++ PHY_SetBBReg(pAdapter, 0xe50, bMaskDWord, 0x01008c00); ++ PHY_SetBBReg(pAdapter, 0xe54, bMaskDWord, 0x01008c00); ++ } ++ ++ //RTPRINT(FINIT, INIT_IQK, ("PHY_APCalibrate() offset 0x800 %x\n", PHY_QueryBBReg(pAdapter, 0x800, bMaskDWord))); ++ ++ //MAC settings ++ _PHY_MACSettingCalibration(pAdapter, MAC_REG, MAC_backup); ++ ++ if(path == RF90_PATH_A) //Path B to standby mode ++ { ++ PHY_SetRFReg(pAdapter, RF90_PATH_B, 0x0, bMaskDWord, 0x10000); ++ } ++ else //Path A to standby mode ++ { ++ PHY_SetRFReg(pAdapter, RF90_PATH_A, 0x00, bMaskDWord, 0x10000); ++ PHY_SetRFReg(pAdapter, RF90_PATH_A, 0x10, bMaskDWord, 0x1000f); ++ PHY_SetRFReg(pAdapter, RF90_PATH_A, 0x11, bMaskDWord, 0x20103); ++ } ++ ++ delta_offset = ((delta+14)/2); ++ if(delta_offset < 0) ++ delta_offset = 0; ++ else if (delta_offset > 12) ++ delta_offset = 12; ++ ++ //AP calibration ++ for(index = 0; index < APK_BB_REG_NUM; index++) ++ { ++ if(index != 1 && isNormal) //only DO PA11+PAD01001, AP RF setting ++ continue; ++ ++ tmpReg = APK_RF_init_value[path][index]; ++#if 1 ++ if(!pdmpriv->bAPKThermalMeterIgnore) ++ { ++ BB_offset = (tmpReg & 0xF0000) >> 16; ++ ++ if(!(tmpReg & BIT15)) //sign bit 0 ++ { ++ BB_offset = -BB_offset; ++ } ++ ++ delta_V = APK_delta_mapping[index][delta_offset]; ++ ++ BB_offset += delta_V; ++ ++ //RTPRINT(FINIT, INIT_IQK, ("PHY_APCalibrate() APK num %d delta_V %d delta_offset %d\n", index, delta_V, delta_offset)); ++ ++ if(BB_offset < 0) ++ { ++ tmpReg = tmpReg & (~BIT15); ++ BB_offset = -BB_offset; ++ } ++ else ++ { ++ tmpReg = tmpReg | BIT15; ++ } ++ tmpReg = (tmpReg & 0xFFF0FFFF) | (BB_offset << 16); ++ } ++#endif ++ PHY_SetRFReg(pAdapter, (RF90_RADIO_PATH_E)path, 0xc, bMaskDWord, 0x8992e); ++ //RTPRINT(FINIT, INIT_IQK, ("PHY_APCalibrate() offset 0xc %x\n", PHY_QueryRFReg(pAdapter, (RF90_RADIO_PATH_E)path, 0xc, bMaskDWord))); ++ PHY_SetRFReg(pAdapter, (RF90_RADIO_PATH_E)path, 0x0, bMaskDWord, APK_RF_value_0[path][index]); ++ //RTPRINT(FINIT, INIT_IQK, ("PHY_APCalibrate() offset 0x0 %x\n", PHY_QueryRFReg(pAdapter, (RF90_RADIO_PATH_E)path, 0x0, bMaskDWord))); ++ PHY_SetRFReg(pAdapter, (RF90_RADIO_PATH_E)path, 0xd, bMaskDWord, tmpReg); ++ //RTPRINT(FINIT, INIT_IQK, ("PHY_APCalibrate() offset 0xd %x\n", PHY_QueryRFReg(pAdapter, (RF90_RADIO_PATH_E)path, 0xd, bMaskDWord))); ++ if(!isNormal) ++ { ++ PHY_SetRFReg(pAdapter, (RF90_RADIO_PATH_E)path, 0xa, bMaskDWord, APK_RF_value_A[path][index]); ++ //RTPRINT(FINIT, INIT_IQK, ("PHY_APCalibrate() offset 0xa %x\n", PHY_QueryRFReg(pAdapter, (RF90_RADIO_PATH_E)path, 0xa, bMaskDWord))); ++ } ++ ++ // PA11+PAD01111, one shot ++ i = 0; ++ do ++ { ++ PHY_SetBBReg(pAdapter, 0xe28, bMaskDWord, 0x80000000); ++ { ++ PHY_SetBBReg(pAdapter, APK_offset[path], bMaskDWord, APK_value[0]); ++ //RTPRINT(FINIT, INIT_IQK, ("PHY_APCalibrate() offset 0x%x value 0x%x\n", APK_offset[path], PHY_QueryBBReg(pAdapter, APK_offset[path], bMaskDWord))); ++ rtw_mdelay_os(3); ++ PHY_SetBBReg(pAdapter, APK_offset[path], bMaskDWord, APK_value[1]); ++ //RTPRINT(FINIT, INIT_IQK, ("PHY_APCalibrate() offset 0x%x value 0x%x\n", APK_offset[path], PHY_QueryBBReg(pAdapter, APK_offset[path], bMaskDWord))); ++ if(isNormal) { ++ #ifdef CONFIG_LONG_DELAY_ISSUE ++ rtw_msleep_os(20); ++ #else ++ rtw_mdelay_os(20); ++ #endif ++ } ++ else ++ rtw_mdelay_os(3); ++ } ++ PHY_SetBBReg(pAdapter, 0xe28, bMaskDWord, 0x00000000); ++ ++ if(!isNormal) ++ { ++ tmpReg = PHY_QueryRFReg(pAdapter, (RF90_RADIO_PATH_E)path, 0xb, bMaskDWord); ++ tmpReg = (tmpReg & 0x3E00) >> 9; ++ } ++ else ++ { ++ if(path == RF90_PATH_A) ++ tmpReg = PHY_QueryBBReg(pAdapter, 0xbd8, 0x03E00000); ++ else ++ tmpReg = PHY_QueryBBReg(pAdapter, 0xbd8, 0xF8000000); ++ } ++ //RTPRINT(FINIT, INIT_IQK, ("PHY_APCalibrate() offset 0xbd8[25:21] %x\n", tmpReg)); ++ ++ i++; ++ } ++ while(tmpReg > apkbound && i < 4); ++ ++ APK_result[path][index] = tmpReg; ++ } ++ } ++ ++ //reload MAC default value ++ _PHY_ReloadMACRegisters(pAdapter, MAC_REG, MAC_backup); ++ ++ //reload BB default value ++ for(index = 0; index < APK_BB_REG_NUM ; index++) ++ { ++ if(index == 0 && isNormal) //skip ++ continue; ++ PHY_SetBBReg(pAdapter, BB_REG[index], bMaskDWord, BB_backup[index]); ++ } ++ ++ //reload AFE default value ++ _PHY_ReloadADDARegisters(pAdapter, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM); ++ ++ //reload RF path default value ++ for(path = 0; path < pathbound; path++) ++ { ++ PHY_SetRFReg(pAdapter, (RF90_RADIO_PATH_E)path, 0xd, bMaskDWord, regD[path]); ++ if(path == RF90_PATH_B) ++ { ++ PHY_SetRFReg(pAdapter, RF90_PATH_A, 0x10, bMaskDWord, 0x1000f); ++ PHY_SetRFReg(pAdapter, RF90_PATH_A, 0x11, bMaskDWord, 0x20101); ++ } ++#if 1 ++ if(!isNormal) ++ { ++ for(index = 0; index < APK_BB_REG_NUM ; index++) ++ { ++ if(APK_result[path][index] > 12) ++ APK_result[path][index] = AP_curve[path][index-1]; ++ //RTPRINT(FINIT, INIT_IQK, ("apk result %d 0x%x \t", index, APK_result[path][index])); ++ } ++ } ++ else ++ { //note no index == 0 ++ if (APK_result[path][1] > 6) ++ APK_result[path][1] = 6; ++ //RTPRINT(FINIT, INIT_IQK, ("apk path %d result %d 0x%x \t", path, 1, APK_result[path][1])); ++ ++#if 0 ++ if(APK_result[path][2] < 2) ++ APK_result[path][2] = 2; ++ else if (APK_result[path][2] > 6) ++ APK_result[path][2] = 6; ++ RTPRINT(FINIT, INIT_IQK, ("apk result %d 0x%x \t", 2, APK_result[path][2])); ++ ++ if(APK_result[path][3] < 2) ++ APK_result[path][3] = 2; ++ else if (APK_result[path][3] > 6) ++ APK_result[path][3] = 6; ++ RTPRINT(FINIT, INIT_IQK, ("apk result %d 0x%x \t", 3, APK_result[path][3])); ++ ++ if(APK_result[path][4] < 5) ++ APK_result[path][4] = 5; ++ else if (APK_result[path][4] > 9) ++ APK_result[path][4] = 9; ++ RTPRINT(FINIT, INIT_IQK, ("apk result %d 0x%x \t", 4, APK_result[path][4])); ++#endif ++ ++ } ++#endif ++ } ++ ++ //RTPRINT(FINIT, INIT_IQK, ("\n")); ++ ++ ++ for(path = 0; path < pathbound; path++) ++ { ++ if(isNormal) ++ { ++ PHY_SetRFReg(pAdapter, (RF90_RADIO_PATH_E)path, 0x3, bMaskDWord, ++ ((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (APK_result[path][1] << 5) | APK_result[path][1])); ++ if(path == RF90_PATH_A) ++ PHY_SetRFReg(pAdapter, (RF90_RADIO_PATH_E)path, 0x4, bMaskDWord, ++ ((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (0x00 << 5) | 0x05)); ++ else ++ PHY_SetRFReg(pAdapter, (RF90_RADIO_PATH_E)path, 0x4, bMaskDWord, ++ ((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (0x02 << 5) | 0x05)); ++ PHY_SetRFReg(pAdapter, (RF90_RADIO_PATH_E)path, 0xe, bMaskDWord, ++ ((0x08 << 15) | (0x08 << 10) | (0x08 << 5) | 0x08)); ++ } ++ else ++ { ++ for(index = 0; index < 2; index++) ++ pdmpriv->APKoutput[path][index] = ((APK_result[path][index] << 15) | (APK_result[path][2] << 10) | (APK_result[path][3] << 5) | APK_result[path][4]); ++ ++#if (MP_DRIVER == 1) ++ if(pMptCtx->TxPwrLevel[path] > pMptCtx->APK_bound[path]) ++ { ++ PHY_SetRFReg(pAdapter, (RF90_RADIO_PATH_E)path, 0xe, bMaskDWord, ++ pdmpriv->APKoutput[path][0]); ++ } ++ else ++ { ++ PHY_SetRFReg(pAdapter, (RF90_RADIO_PATH_E)path, 0xe, bMaskDWord, ++ pdmpriv->APKoutput[path][1]); ++ } ++#else ++ PHY_SetRFReg(pAdapter, (RF90_RADIO_PATH_E)path, 0xe, bMaskDWord, ++ pdmpriv->APKoutput[path][0]); ++#endif ++ } ++ } ++ ++ pdmpriv->bAPKdone = _TRUE; ++ ++ //RTPRINT(FINIT, INIT_IQK, ("<==PHY_APCalibrate()\n")); ++#endif ++} ++ ++ ++#define DP_BB_REG_NUM 7 ++#define DP_RF_REG_NUM 1 ++#define DP_RETRY_LIMIT 10 ++#define DP_PATH_NUM 2 ++#define DP_DPK_NUM 3 ++#define DP_DPK_VALUE_NUM 2 ++ ++//digital predistortion ++static VOID ++_PHY_DigitalPredistortion( ++ IN PADAPTER pAdapter, ++ IN BOOLEAN is2T ++ ) ++{ ++#if 1//(PLATFORM == PLATFORM_WINDOWS) ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); ++ struct dm_priv *pdmpriv = &pHalData->dmpriv; ++ ++ u32 tmpReg, tmpReg2, index, offset, path, i, pathbound = PATH_NUM; ++ u32 AFE_backup[IQK_ADDA_REG_NUM]; ++ u32 AFE_REG[IQK_ADDA_REG_NUM] = { ++ 0x85c, 0xe6c, 0xe70, 0xe74, 0xe78, ++ 0xe7c, 0xe80, 0xe84, 0xe88, 0xe8c, ++ 0xed0, 0xed4, 0xed8, 0xedc, 0xee0, ++ 0xeec}; ++ ++ u32 BB_backup[DP_BB_REG_NUM]; ++ u32 BB_REG[DP_BB_REG_NUM] = { ++ 0xc04, 0x800, 0xc08, 0x874, ++ 0x870, 0x860, 0x864}; ++ u32 BB_settings[DP_BB_REG_NUM] = { ++ 0x00a05430, 0x02040000, 0x000800e4, 0x22208000, ++ 0x0, 0x0, 0x0}; ++ ++ u32 RF_backup[DP_PATH_NUM][DP_RF_REG_NUM]; ++ u32 RF_REG[DP_RF_REG_NUM] = { ++ 0x0d}; ++ ++ u32 MAC_backup[IQK_MAC_REG_NUM]; ++ u32 MAC_REG[IQK_MAC_REG_NUM] = { ++ 0x522, 0x550, 0x551, 0x040}; ++ ++ u32 Tx_AGC[DP_DPK_NUM][DP_DPK_VALUE_NUM] = { ++ {0x1e1e1e1e, 0x03901e1e}, ++ {0x18181818, 0x03901818}, ++ {0x0e0e0e0e, 0x03900e0e} ++ }; ++ ++// u32 RF_PATHA_backup[DP_RF_REG_NUM]; ++// u32 RF_REG_PATHA[DP_RF_REG_NUM] = { ++// 0x00, 0x10, 0x11}; ++ ++ u32 Reg800, Reg874, Regc04, Regc08, Reg040; ++ ++ u32 AFE_on_off[PATH_NUM] = { ++ 0x04db25a4, 0x0b1b25a4}; //path A on path B off / path A off path B on ++ ++ u32 RetryCount = 0; ++ ++ BOOLEAN isNormal = IS_NORMAL_CHIP(pHalData->VersionID); ++ ++ //DBG_8192C("==>_PHY_DigitalPredistortion()\n"); ++ ++ //DBG_8192C("_PHY_DigitalPredistortion for %s %s\n", (is2T ? "2T2R" : "1T1R"), (isNormal ? "Normal chip" : "Test chip")); ++ ++ if(!isNormal) ++ return; ++ ++ //save BB default value ++ for(index=0; index tx_agc 1f ~11 ++ // PA gain = 11 & PAD2 => tx_agc 10~0e ++ // PA gain = 01 => tx_agc 0b~0d ++ // PA gain = 00 => tx_agc 0a~00 ++ PHY_SetBBReg(pAdapter, 0xe28, bMaskDWord, 0x40000000); ++ PHY_SetBBReg(pAdapter, 0xbc0, bMaskDWord, 0x0005361f); ++ PHY_SetBBReg(pAdapter, 0xe28, bMaskDWord, 0x00000000); ++ ++ //do inner loopback DPK 3 times ++ for(i = 0; i < 3; i++) ++ { ++ //PA gain = 11 & PAD2 => tx_agc = 0x0f/0x0c/0x07 ++ for(index = 0; index < 3; index++) ++ PHY_SetBBReg(pAdapter, 0xe00+index*4, bMaskDWord, Tx_AGC[i][0]); ++ PHY_SetBBReg(pAdapter, 0xe00+index*4, bMaskDWord, Tx_AGC[i][1]); ++ for(index = 0; index < 4; index++) ++ PHY_SetBBReg(pAdapter, 0xe10+index*4, bMaskDWord, Tx_AGC[i][0]); ++ ++ // PAGE_B for Path-A inner loopback DPK setting ++ PHY_SetBBReg(pAdapter, 0xb00, bMaskDWord, 0x02097098); ++ PHY_SetBBReg(pAdapter, 0xb04, bMaskDWord, 0xf76d9f84); ++ PHY_SetBBReg(pAdapter, 0xb28, bMaskDWord, 0x0004ab87); ++ PHY_SetBBReg(pAdapter, 0xb68, bMaskDWord, 0x00880000); ++ ++ //----send one shot signal----// ++ // Path A ++ PHY_SetBBReg(pAdapter, 0xb28, bMaskDWord, 0x80047788); ++ rtw_mdelay_os(1); ++ PHY_SetBBReg(pAdapter, 0xb28, bMaskDWord, 0x00047788); ++ #ifdef CONFIG_LONG_DELAY_ISSUE ++ rtw_msleep_os(50); ++ #else ++ rtw_mdelay_os(50); ++ #endif ++ } ++ ++ //PA gain = 11 => tx_agc = 1a ++ for(index = 0; index < 3; index++) ++ PHY_SetBBReg(pAdapter, 0xe00+index*4, bMaskDWord, 0x34343434); ++ PHY_SetBBReg(pAdapter, 0xe08+index*4, bMaskDWord, 0x03903434); ++ for(index = 0; index < 4; index++) ++ PHY_SetBBReg(pAdapter, 0xe10+index*4, bMaskDWord, 0x34343434); ++ ++ //==================================== ++ // PAGE_B for Path-A DPK setting ++ //==================================== ++ // open inner loopback @ b00[19]:10 od 0xb00 0x01097018 ++ PHY_SetBBReg(pAdapter, 0xb00, bMaskDWord, 0x02017098); ++ PHY_SetBBReg(pAdapter, 0xb04, bMaskDWord, 0xf76d9f84); ++ PHY_SetBBReg(pAdapter, 0xb28, bMaskDWord, 0x0004ab87); ++ PHY_SetBBReg(pAdapter, 0xb68, bMaskDWord, 0x00880000); ++ ++ //rf_lpbk_setup ++ //1.rf 00:5205a, rf 0d:0e52c ++ PHY_SetRFReg(pAdapter, RF90_PATH_A, 0x0c, bMaskDWord, 0x8992b); ++ PHY_SetRFReg(pAdapter, RF90_PATH_A, 0x0d, bMaskDWord, 0x0e52c); ++ PHY_SetRFReg(pAdapter, RF90_PATH_A, 0x00, bMaskDWord, 0x5205a ); ++ ++ //----send one shot signal----// ++ // Path A ++ PHY_SetBBReg(pAdapter, 0xb28, bMaskDWord, 0x800477c0); ++ rtw_mdelay_os(1); ++ PHY_SetBBReg(pAdapter, 0xb28, bMaskDWord, 0x000477c0); ++ #ifdef CONFIG_LONG_DELAY_ISSUE ++ rtw_msleep_os(50); ++ #else ++ rtw_mdelay_os(50); ++ #endif ++ ++ while(RetryCount < DP_RETRY_LIMIT && !pdmpriv->bDPPathAOK) ++ { ++ //----read back measurement results----// ++ PHY_SetBBReg(pAdapter, 0xb00, bMaskDWord, 0x0c297018); ++ tmpReg = PHY_QueryBBReg(pAdapter, 0xbe0, bMaskDWord); ++ rtw_mdelay_os(10); ++ PHY_SetBBReg(pAdapter, 0xb00, bMaskDWord, 0x0c29701f); ++ tmpReg2 = PHY_QueryBBReg(pAdapter, 0xbe8, bMaskDWord); ++ rtw_mdelay_os(10); ++ ++ tmpReg = (tmpReg & bMaskHWord) >> 16; ++ tmpReg2 = (tmpReg2 & bMaskHWord) >> 16; ++ if(tmpReg < 0xf0 || tmpReg > 0x105 || tmpReg2 > 0xff ) ++ { ++ PHY_SetBBReg(pAdapter, 0xb00, bMaskDWord, 0x02017098); ++ ++ PHY_SetBBReg(pAdapter, 0xe28, bMaskDWord, 0x80000000); ++ PHY_SetBBReg(pAdapter, 0xe28, bMaskDWord, 0x00000000); ++ rtw_mdelay_os(1); ++ PHY_SetBBReg(pAdapter, 0xb28, bMaskDWord, 0x800477c0); ++ rtw_mdelay_os(1); ++ PHY_SetBBReg(pAdapter, 0xb28, bMaskDWord, 0x000477c0); ++ #ifdef CONFIG_LONG_DELAY_ISSUE ++ rtw_msleep_os(50); ++ #else ++ rtw_mdelay_os(50); ++ #endif ++ RetryCount++; ++ DBG_8192C("path A DPK RetryCount %d 0xbe0[31:16] %x 0xbe8[31:16] %x\n", RetryCount, tmpReg, tmpReg2); ++ } ++ else ++ { ++ DBG_8192C("path A DPK Sucess\n"); ++ pdmpriv->bDPPathAOK = _TRUE; ++ break; ++ } ++ } ++ RetryCount = 0; ++ ++ //DPP path A ++ if(pdmpriv->bDPPathAOK) ++ { ++ // DP settings ++ PHY_SetBBReg(pAdapter, 0xb00, bMaskDWord, 0x01017098); ++ PHY_SetBBReg(pAdapter, 0xb04, bMaskDWord, 0x776d9f84); ++ PHY_SetBBReg(pAdapter, 0xb28, bMaskDWord, 0x0004ab87); ++ PHY_SetBBReg(pAdapter, 0xb68, bMaskDWord, 0x00880000); ++ PHY_SetBBReg(pAdapter, 0xe28, bMaskDWord, 0x40000000); ++ ++ for(i=0xb00; i<=0xb3c; i+=4) ++ { ++ PHY_SetBBReg(pAdapter, i, bMaskDWord, 0x40004000); ++ //DBG_8192C("path A ofsset = 0x%x\n", i); ++ } ++ ++ //pwsf ++ PHY_SetBBReg(pAdapter, 0xb40, bMaskDWord, 0x40404040); ++ PHY_SetBBReg(pAdapter, 0xb44, bMaskDWord, 0x28324040); ++ PHY_SetBBReg(pAdapter, 0xb48, bMaskDWord, 0x10141920); ++ ++ for(i=0xb4c; i<=0xb5c; i+=4) ++ { ++ PHY_SetBBReg(pAdapter, i, bMaskDWord, 0x0c0c0c0c); ++ } ++ ++ //TX_AGC boundary ++ PHY_SetBBReg(pAdapter, 0xbc0, bMaskDWord, 0x0005361f); ++ PHY_SetBBReg(pAdapter, 0xe28, bMaskDWord, 0x00000000); ++ } ++ else ++ { ++ PHY_SetBBReg(pAdapter, 0xb00, bMaskDWord, 0x00000000); ++ PHY_SetBBReg(pAdapter, 0xb04, bMaskDWord, 0x00000000); ++ } ++ ++ //DPK path B ++ if(is2T) ++ { ++ //Path A to standby mode ++ PHY_SetRFReg(pAdapter, RF90_PATH_A, RF_AC, bMaskDWord, 0x10000); ++ ++ // LUTs => tx_agc ++ // PA gain = 11 & PAD1, => tx_agc 1f ~11 ++ // PA gain = 11 & PAD2, => tx_agc 10 ~0e ++ // PA gain = 01 => tx_agc 0b ~0d ++ // PA gain = 00 => tx_agc 0a ~00 ++ PHY_SetBBReg(pAdapter, 0xe28, bMaskDWord, 0x40000000); ++ PHY_SetBBReg(pAdapter, 0xbc4, bMaskDWord, 0x0005361f); ++ PHY_SetBBReg(pAdapter, 0xe28, bMaskDWord, 0x00000000); ++ ++ //do inner loopback DPK 3 times ++ for(i = 0; i < 3; i++) ++ { ++ //PA gain = 11 & PAD2 => tx_agc = 0x0f/0x0c/0x07 ++ for(index = 0; index < 4; index++) ++ PHY_SetBBReg(pAdapter, 0x830+index*4, bMaskDWord, Tx_AGC[i][0]); ++ for(index = 0; index < 2; index++) ++ PHY_SetBBReg(pAdapter, 0x848+index*4, bMaskDWord, Tx_AGC[i][0]); ++ for(index = 0; index < 2; index++) ++ PHY_SetBBReg(pAdapter, 0x868+index*4, bMaskDWord, Tx_AGC[i][0]); ++ ++ // PAGE_B for Path-A inner loopback DPK setting ++ PHY_SetBBReg(pAdapter, 0xb70, bMaskDWord, 0x02097098); ++ PHY_SetBBReg(pAdapter, 0xb74, bMaskDWord, 0xf76d9f84); ++ PHY_SetBBReg(pAdapter, 0xb98, bMaskDWord, 0x0004ab87); ++ PHY_SetBBReg(pAdapter, 0xb6c, bMaskDWord, 0x00880000); ++ ++ //----send one shot signal----// ++ // Path B ++ PHY_SetBBReg(pAdapter, 0xb98, bMaskDWord, 0x80047788); ++ rtw_mdelay_os(1); ++ PHY_SetBBReg(pAdapter, 0xb98, bMaskDWord, 0x00047788); ++ #ifdef CONFIG_LONG_DELAY_ISSUE ++ rtw_msleep_os(50); ++ #else ++ rtw_mdelay_os(50); ++ #endif ++ } ++ ++ // PA gain = 11 => tx_agc = 1a ++ for(index = 0; index < 4; index++) ++ PHY_SetBBReg(pAdapter, 0x830+index*4, bMaskDWord, 0x34343434); ++ for(index = 0; index < 2; index++) ++ PHY_SetBBReg(pAdapter, 0x848+index*4, bMaskDWord, 0x34343434); ++ for(index = 0; index < 2; index++) ++ PHY_SetBBReg(pAdapter, 0x868+index*4, bMaskDWord, 0x34343434); ++ ++ // PAGE_B for Path-B DPK setting ++ PHY_SetBBReg(pAdapter, 0xb70, bMaskDWord, 0x02017098); ++ PHY_SetBBReg(pAdapter, 0xb74, bMaskDWord, 0xf76d9f84); ++ PHY_SetBBReg(pAdapter, 0xb98, bMaskDWord, 0x0004ab87); ++ PHY_SetBBReg(pAdapter, 0xb6c, bMaskDWord, 0x00880000); ++ ++ // RF lpbk switches on ++ PHY_SetBBReg(pAdapter, 0x840, bMaskDWord, 0x0101000f); ++ PHY_SetBBReg(pAdapter, 0x840, bMaskDWord, 0x01120103); ++ ++ //Path-B RF lpbk ++ PHY_SetRFReg(pAdapter, RF90_PATH_B, 0x0c, bMaskDWord, 0x8992b); ++ PHY_SetRFReg(pAdapter, RF90_PATH_B, 0x0d, bMaskDWord, 0x0e52c); ++ PHY_SetRFReg(pAdapter, RF90_PATH_B, RF_AC, bMaskDWord, 0x5205a); ++ ++ //----send one shot signal----// ++ PHY_SetBBReg(pAdapter, 0xb98, bMaskDWord, 0x800477c0); ++ rtw_mdelay_os(1); ++ PHY_SetBBReg(pAdapter, 0xb98, bMaskDWord, 0x000477c0); ++ #ifdef CONFIG_LONG_DELAY_ISSUE ++ rtw_msleep_os(50); ++ #else ++ rtw_mdelay_os(50); ++ #endif ++ ++ while(RetryCount < DP_RETRY_LIMIT && !pdmpriv->bDPPathBOK) ++ { ++ //----read back measurement results----// ++ PHY_SetBBReg(pAdapter, 0xb70, bMaskDWord, 0x0c297018); ++ tmpReg = PHY_QueryBBReg(pAdapter, 0xbf0, bMaskDWord); ++ PHY_SetBBReg(pAdapter, 0xb70, bMaskDWord, 0x0c29701f); ++ tmpReg2 = PHY_QueryBBReg(pAdapter, 0xbf8, bMaskDWord); ++ ++ tmpReg = (tmpReg & bMaskHWord) >> 16; ++ tmpReg2 = (tmpReg2 & bMaskHWord) >> 16; ++ ++ if(tmpReg < 0xf0 || tmpReg > 0x105 || tmpReg2 > 0xff) ++ { ++ PHY_SetBBReg(pAdapter, 0xb70, bMaskDWord, 0x02017098); ++ ++ PHY_SetBBReg(pAdapter, 0xe28, bMaskDWord, 0x80000000); ++ PHY_SetBBReg(pAdapter, 0xe28, bMaskDWord, 0x00000000); ++ rtw_mdelay_os(1); ++ PHY_SetBBReg(pAdapter, 0xb98, bMaskDWord, 0x800477c0); ++ rtw_mdelay_os(1); ++ PHY_SetBBReg(pAdapter, 0xb98, bMaskDWord, 0x000477c0); ++ #ifdef CONFIG_LONG_DELAY_ISSUE ++ rtw_msleep_os(50); ++ #else ++ rtw_mdelay_os(50); ++ #endif ++ RetryCount++; ++ DBG_8192C("path B DPK RetryCount %d 0xbf0[31:16] %x, 0xbf8[31:16] %x\n", RetryCount , tmpReg, tmpReg2); ++ } ++ else ++ { ++ DBG_8192C("path B DPK Success\n"); ++ pdmpriv->bDPPathBOK = _TRUE; ++ break; ++ } ++ } ++ ++ //DPP path B ++ if(pdmpriv->bDPPathBOK) ++ { ++ // DP setting ++ // LUT by SRAM ++ PHY_SetBBReg(pAdapter, 0xb70, bMaskDWord, 0x01017098); ++ PHY_SetBBReg(pAdapter, 0xb74, bMaskDWord, 0x776d9f84); ++ PHY_SetBBReg(pAdapter, 0xb98, bMaskDWord, 0x0004ab87); ++ PHY_SetBBReg(pAdapter, 0xb6c, bMaskDWord, 0x00880000); ++ ++ PHY_SetBBReg(pAdapter, 0xe28, bMaskDWord, 0x40000000); ++ for(i=0xb60; i<=0xb9c; i+=4) ++ { ++ PHY_SetBBReg(pAdapter, i, bMaskDWord, 0x40004000); ++ //DBG_8192C("path B ofsset = 0x%x\n", i); ++ } ++ ++ // PWSF ++ PHY_SetBBReg(pAdapter, 0xba0, bMaskDWord, 0x40404040); ++ PHY_SetBBReg(pAdapter, 0xba4, bMaskDWord, 0x28324050); ++ PHY_SetBBReg(pAdapter, 0xba8, bMaskDWord, 0x0c141920); ++ ++ for(i=0xbac; i<=0xbbc; i+=4) ++ { ++ PHY_SetBBReg(pAdapter, i, bMaskDWord, 0x0c0c0c0c); ++ } ++ ++ // tx_agc boundary ++ PHY_SetBBReg(pAdapter, 0xbc4, bMaskDWord, 0x0005361f); ++ PHY_SetBBReg(pAdapter, 0xe28, bMaskDWord, 0x00000000); ++ ++ } ++ else ++ { ++ PHY_SetBBReg(pAdapter, 0xb70, bMaskDWord, 0x00000000); ++ PHY_SetBBReg(pAdapter, 0xb74, bMaskDWord, 0x00000000); ++ } ++ } ++ ++ //reload BB default value ++ for(index=0; indexbDPdone = _TRUE; ++ //DBG_8192C("<==_PHY_DigitalPredistortion()\n"); ++#endif ++} ++ ++ ++static VOID _PHY_SetRFPathSwitch( ++ IN PADAPTER pAdapter, ++ IN BOOLEAN bMain, ++ IN BOOLEAN is2T ++ ) ++{ ++ u8 u1bTmp; ++ ++ if(!pAdapter->hw_init_completed) ++ { ++ u1bTmp = rtw_read8(pAdapter, REG_LEDCFG2) | BIT7; ++ rtw_write8(pAdapter, REG_LEDCFG2, u1bTmp); ++ //PHY_SetBBReg(pAdapter, REG_LEDCFG0, BIT23, 0x01); ++ PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT13, 0x01); ++ } ++ ++ if(is2T) ++ { ++ if(bMain) ++ PHY_SetBBReg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT5|BIT6, 0x1); //92C_Path_A ++ else ++ PHY_SetBBReg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT5|BIT6, 0x2); //BT ++ } ++ else ++ { ++ ++ if(bMain) ++ PHY_SetBBReg(pAdapter, rFPGA0_XA_RFInterfaceOE, 0x300, 0x2); //Main ++ else ++ PHY_SetBBReg(pAdapter, rFPGA0_XA_RFInterfaceOE, 0x300, 0x1); //Aux ++ } ++ ++} ++ ++//return value TRUE => Main; FALSE => Aux ++ ++static BOOLEAN _PHY_QueryRFPathSwitch( ++ IN PADAPTER pAdapter, ++ IN BOOLEAN is2T ++ ) ++{ ++// if(is2T) ++// return _TRUE; ++ ++ if(!pAdapter->hw_init_completed) ++ { ++ PHY_SetBBReg(pAdapter, REG_LEDCFG0, BIT23, 0x01); ++ PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT13, 0x01); ++ } ++ ++ if(is2T) ++ { ++ if(PHY_QueryBBReg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT5|BIT6) == 0x01) ++ return _TRUE; ++ else ++ return _FALSE; ++ } ++ else ++ { ++ if(PHY_QueryBBReg(pAdapter, rFPGA0_XA_RFInterfaceOE, 0x300) == 0x02) ++ return _TRUE; ++ else ++ return _FALSE; ++ } ++} ++ ++ ++static VOID ++_PHY_DumpRFReg(IN PADAPTER pAdapter) ++{ ++ u32 rfRegValue,rfRegOffset; ++ ++ //RTPRINT(FINIT, INIT_RF, ("PHY_DumpRFReg()====>\n")); ++ ++ for(rfRegOffset = 0x00;rfRegOffset<=0x30;rfRegOffset++){ ++ rfRegValue = PHY_QueryRFReg(pAdapter,RF90_PATH_A, rfRegOffset, bMaskDWord); ++ //RTPRINT(FINIT, INIT_RF, (" 0x%02x = 0x%08x\n",rfRegOffset,rfRegValue)); ++ } ++ //RTPRINT(FINIT, INIT_RF, ("<===== PHY_DumpRFReg()\n")); ++} ++ ++ ++VOID ++rtl8192c_PHY_IQCalibrate( ++ IN PADAPTER pAdapter, ++ IN BOOLEAN bReCovery ++ ) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); ++ struct dm_priv *pdmpriv = &pHalData->dmpriv; ++ u32 IQK_BB_REG[9] = { ++ rOFDM0_XARxIQImbalance, rOFDM0_XBRxIQImbalance, rOFDM0_ECCAThreshold, rOFDM0_AGCRSSITable, ++ rOFDM0_XATxIQImbalance, rOFDM0_XBTxIQImbalance, rOFDM0_XCTxAFE, rOFDM0_XDTxAFE, rOFDM0_RxIQExtAnta}; ++ int result[4][8]; //last is final result ++ u8 i, final_candidate; ++ BOOLEAN bPathAOK, bPathBOK; ++ int RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC, RegTmp = 0; ++ BOOLEAN is12simular, is13simular, is23simular; ++ ++ ++#if (MP_DRIVER == 1) ++ //ignore IQK when continuous Tx ++ if (pAdapter->mppriv.MptCtx.bStartContTx == _TRUE) ++ return; ++ if (pAdapter->mppriv.MptCtx.bCarrierSuppression == _TRUE) ++ return; ++ if (pAdapter->mppriv.MptCtx.bSingleCarrier == _TRUE) ++ return; ++ if (pAdapter->mppriv.MptCtx.bSingleTone == _TRUE) ++ return; ++#endif ++ ++#if DISABLE_BB_RF ++ return; ++#endif ++ ++ if(bReCovery) ++ { ++ _PHY_ReloadADDARegisters(pAdapter, IQK_BB_REG, pdmpriv->IQK_BB_backup_recover, 9); ++ return; ++ } ++ DBG_8192C("IQK:Start!!!\n"); ++ ++ for(i = 0; i < 8; i++) ++ { ++ result[0][i] = 0; ++ result[1][i] = 0; ++ result[2][i] = 0; ++ result[3][i] = 0; ++ } ++ final_candidate = 0xff; ++ bPathAOK = _FALSE; ++ bPathBOK = _FALSE; ++ is12simular = _FALSE; ++ is23simular = _FALSE; ++ is13simular = _FALSE; ++ ++ for (i=0; i<3; i++) ++ { ++ if(IS_92C_SERIAL( pHalData->VersionID)){ ++ _PHY_IQCalibrate(pAdapter, result, i, _TRUE); ++ //_PHY_DumpRFReg(pAdapter); ++ } ++ else{ ++ // For 88C 1T1R ++ _PHY_IQCalibrate(pAdapter, result, i, _FALSE); ++ } ++ ++ if(i == 1) ++ { ++ is12simular = _PHY_SimularityCompare(pAdapter, result, 0, 1); ++ if(is12simular) ++ { ++ final_candidate = 0; ++ break; ++ } ++ } ++ ++ if(i == 2) ++ { ++ is13simular = _PHY_SimularityCompare(pAdapter, result, 0, 2); ++ if(is13simular) ++ { ++ final_candidate = 0; ++ break; ++ } ++ ++ is23simular = _PHY_SimularityCompare(pAdapter, result, 1, 2); ++ if(is23simular) ++ final_candidate = 1; ++ else ++ { ++ for(i = 0; i < 8; i++) ++ RegTmp += result[3][i]; ++ ++ if(RegTmp != 0) ++ final_candidate = 3; ++ else ++ final_candidate = 0xFF; ++ } ++ } ++ } ++ ++ for (i=0; i<4; i++) ++ { ++ RegE94 = result[i][0]; ++ RegE9C = result[i][1]; ++ RegEA4 = result[i][2]; ++ RegEAC = result[i][3]; ++ RegEB4 = result[i][4]; ++ RegEBC = result[i][5]; ++ RegEC4 = result[i][6]; ++ RegECC = result[i][7]; ++ //RTPRINT(FINIT, INIT_IQK, ("IQK: RegE94=%lx RegE9C=%lx RegEA4=%lx RegEAC=%lx RegEB4=%lx RegEBC=%lx RegEC4=%lx RegECC=%lx\n ", RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC)); ++ } ++ ++ if(final_candidate != 0xff) ++ { ++ pdmpriv->RegE94 = RegE94 = result[final_candidate][0]; ++ pdmpriv->RegE9C = RegE9C = result[final_candidate][1]; ++ RegEA4 = result[final_candidate][2]; ++ RegEAC = result[final_candidate][3]; ++ pdmpriv->RegEB4 = RegEB4 = result[final_candidate][4]; ++ pdmpriv->RegEBC = RegEBC = result[final_candidate][5]; ++ RegEC4 = result[final_candidate][6]; ++ RegECC = result[final_candidate][7]; ++ DBG_8192C("IQK: final_candidate is %x\n", final_candidate); ++ DBG_8192C("IQK: RegE94=%x RegE9C=%x RegEA4=%x RegEAC=%x RegEB4=%x RegEBC=%x RegEC4=%x RegECC=%x\n ", RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC); ++ bPathAOK = bPathBOK = _TRUE; ++ } ++ else ++ { ++ ++ #if 0 ++ DBG_871X("%s do _PHY_ReloadADDARegisters\n"); ++ _PHY_ReloadADDARegisters(pAdapter, IQK_BB_REG, pdmpriv->IQK_BB_backup_recover, 9); ++ return; ++ #else ++ pdmpriv->RegE94 = pdmpriv->RegEB4 = 0x100; //X default value ++ pdmpriv->RegE9C = pdmpriv->RegEBC = 0x0; //Y default value ++ #endif ++ } ++ ++ if((RegE94 != 0)/*&&(RegEA4 != 0)*/) ++ _PHY_PathAFillIQKMatrix(pAdapter, bPathAOK, result, final_candidate, (RegEA4 == 0)); ++ ++ if(IS_92C_SERIAL( pHalData->VersionID)){ ++ if((RegEB4 != 0)/*&&(RegEC4 != 0)*/) ++ _PHY_PathBFillIQKMatrix(pAdapter, bPathBOK, result, final_candidate, (RegEC4 == 0)); ++ } ++ ++ _PHY_SaveADDARegisters(pAdapter, IQK_BB_REG, pdmpriv->IQK_BB_backup_recover, 9); ++ ++} ++ ++ ++VOID ++rtl8192c_PHY_LCCalibrate( ++ IN PADAPTER pAdapter ++ ) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); ++ ++ ++#if (MP_DRIVER == 1) ++ // ignore LCK when continuous Tx ++ if (pAdapter->mppriv.MptCtx.bStartContTx == _TRUE) ++ return; ++ if (pAdapter->mppriv.MptCtx.bCarrierSuppression == _TRUE) ++ return; ++ if (pAdapter->mppriv.MptCtx.bSingleCarrier == _TRUE) ++ return; ++ if (pAdapter->mppriv.MptCtx.bSingleTone == _TRUE) ++ return; ++#endif ++ ++#if DISABLE_BB_RF ++ return; ++#endif ++ ++ if(IS_92C_SERIAL( pHalData->VersionID)){ ++ _PHY_LCCalibrate(pAdapter, _TRUE); ++ } ++ else{ ++ // For 88C 1T1R ++ _PHY_LCCalibrate(pAdapter, _FALSE); ++ } ++} ++ ++VOID ++rtl8192c_PHY_APCalibrate( ++ IN PADAPTER pAdapter, ++ IN char delta ++ ) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); ++ struct dm_priv *pdmpriv = &pHalData->dmpriv; ++ ++#if DISABLE_BB_RF ++ return; ++#endif ++ ++ if(pdmpriv->bAPKdone) ++ return; ++ ++// if(IS_NORMAL_CHIP(pHalData->VersionID)) ++// return; ++ ++ if(IS_92C_SERIAL( pHalData->VersionID)){ ++ _PHY_APCalibrate(pAdapter, delta, _TRUE); ++ } ++ else{ ++ // For 88C 1T1R ++ _PHY_APCalibrate(pAdapter, delta, _FALSE); ++ } ++} ++ ++VOID ++rtl8192c_PHY_DigitalPredistortion( ++ IN PADAPTER pAdapter ++ ) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); ++ struct dm_priv *pdmpriv = &pHalData->dmpriv; ++ ++#if DISABLE_BB_RF ++ return; ++#endif ++ ++ return; ++ ++ if(pdmpriv->bDPdone) ++ return; ++ ++ if(IS_92C_SERIAL( pHalData->VersionID)){ ++ _PHY_DigitalPredistortion(pAdapter, _TRUE); ++ } ++ else{ ++ // For 88C 1T1R ++ _PHY_DigitalPredistortion(pAdapter, _FALSE); ++ } ++} ++ ++VOID rtl8192c_PHY_SetRFPathSwitch( ++ IN PADAPTER pAdapter, ++ IN BOOLEAN bMain ++ ) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); ++ ++#if DISABLE_BB_RF ++ return; ++#endif ++ ++ if(IS_92C_SERIAL( pHalData->VersionID)){ ++ _PHY_SetRFPathSwitch(pAdapter, bMain, _TRUE); ++ } ++ else{ ++ // For 88C 1T1R ++ _PHY_SetRFPathSwitch(pAdapter, bMain, _FALSE); ++ } ++} ++ ++// ++// Move from phycfg.c to gen.c to be code independent later ++// ++//-------------------------Move to other DIR later----------------------------*/ ++#ifdef CONFIG_USB_HCI ++ ++// ++// Description: ++// To dump all Tx FIFO LLT related link-list table. ++// Added by Roger, 2009.03.10. ++// ++VOID ++DumpBBDbgPort_92CU( ++ IN PADAPTER Adapter ++ ) ++{ ++ ++ //RT_TRACE(COMP_SEND, DBG_WARNING, ("\n>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n")); ++ //RT_TRACE(COMP_SEND, DBG_WARNING, ("BaseBand Debug Ports:\n")); ++ ++ PHY_SetBBReg(Adapter, 0x0908, 0xffff, 0x0000); ++ //RT_TRACE(COMP_SEND, DBG_WARNING, ("Offset[%x]: %x\n", 0xdf4, PHY_QueryBBReg(Adapter, 0x0df4, bMaskDWord))); ++ ++ PHY_SetBBReg(Adapter, 0x0908, 0xffff, 0x0803); ++ //RT_TRACE(COMP_SEND, DBG_WARNING, ("Offset[%x]: %x\n", 0xdf4, PHY_QueryBBReg(Adapter, 0x0df4, bMaskDWord))); ++ ++ PHY_SetBBReg(Adapter, 0x0908, 0xffff, 0x0a06); ++ //RT_TRACE(COMP_SEND, DBG_WARNING, ("Offset[%x]: %x\n", 0xdf4, PHY_QueryBBReg(Adapter, 0x0df4, bMaskDWord))); ++ ++ PHY_SetBBReg(Adapter, 0x0908, 0xffff, 0x0007); ++ //RT_TRACE(COMP_SEND, DBG_WARNING, ("Offset[%x]: %x\n", 0xdf4, PHY_QueryBBReg(Adapter, 0x0df4, bMaskDWord))); ++ ++ PHY_SetBBReg(Adapter, 0x0908, 0xffff, 0x0100); ++ PHY_SetBBReg(Adapter, 0x0a28, 0x00ff0000, 0x000f0000); ++ //RT_TRACE(COMP_SEND, DBG_WARNING, ("Offset[%x]: %x\n", 0xdf4, PHY_QueryBBReg(Adapter, 0x0df4, bMaskDWord))); ++ ++ PHY_SetBBReg(Adapter, 0x0908, 0xffff, 0x0100); ++ PHY_SetBBReg(Adapter, 0x0a28, 0x00ff0000, 0x00150000); ++ //RT_TRACE(COMP_SEND, DBG_WARNING, ("Offset[%x]: %x\n", 0xdf4, PHY_QueryBBReg(Adapter, 0x0df4, bMaskDWord))); ++ ++ //RT_TRACE(COMP_SEND, DBG_WARNING, ("Offset[%x]: %x\n", 0x800, PHY_QueryBBReg(Adapter, 0x0800, bMaskDWord))); ++ //RT_TRACE(COMP_SEND, DBG_WARNING, ("Offset[%x]: %x\n", 0x900, PHY_QueryBBReg(Adapter, 0x0900, bMaskDWord))); ++ //RT_TRACE(COMP_SEND, DBG_WARNING, ("Offset[%x]: %x\n", 0xa00, PHY_QueryBBReg(Adapter, 0x0a00, bMaskDWord))); ++ //RT_TRACE(COMP_SEND, DBG_WARNING, ("Offset[%x]: %x\n", 0xa54, PHY_QueryBBReg(Adapter, 0x0a54, bMaskDWord))); ++ //RT_TRACE(COMP_SEND, DBG_WARNING, ("Offset[%x]: %x\n", 0xa58, PHY_QueryBBReg(Adapter, 0x0a58, bMaskDWord))); ++ ++} ++#endif ++ +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/hal/rtl8192c/rtl8192c_rf6052.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/hal/rtl8192c/rtl8192c_rf6052.c 2013-07-26 19:36:05.000000000 +0000 +@@ -0,0 +1,1047 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ++******************************************************************************/ ++/****************************************************************************** ++ * ++ * ++ * Module: rtl8192c_rf6052.c ( Source C File) ++ * ++ * Note: Provide RF 6052 series relative API. ++ * ++ * Function: ++ * ++ * Export: ++ * ++ * Abbrev: ++ * ++ * History: ++ * Data Who Remark ++ * ++ * 09/25/2008 MHC Create initial version. ++ * 11/05/2008 MHC Add API for tw power setting. ++ * ++ * ++******************************************************************************/ ++ ++#define _RTL8192C_RF6052_C_ ++ ++#include ++#include ++#include ++#include ++ ++#include ++ ++/*---------------------------Define Local Constant---------------------------*/ ++// Define local structure for debug!!!!! ++typedef struct RF_Shadow_Compare_Map { ++ // Shadow register value ++ u32 Value; ++ // Compare or not flag ++ u8 Compare; ++ // Record If it had ever modified unpredicted ++ u8 ErrorOrNot; ++ // Recorver Flag ++ u8 Recorver; ++ // ++ u8 Driver_Write; ++}RF_SHADOW_T; ++/*---------------------------Define Local Constant---------------------------*/ ++ ++ ++/*------------------------Define global variable-----------------------------*/ ++/*------------------------Define global variable-----------------------------*/ ++ ++ ++/*------------------------Define local variable------------------------------*/ ++// 2008/11/20 MH For Debug only, RF ++//static RF_SHADOW_T RF_Shadow[RF6052_MAX_PATH][RF6052_MAX_REG] = {0}; ++static RF_SHADOW_T RF_Shadow[RF6052_MAX_PATH][RF6052_MAX_REG]; ++/*------------------------Define local variable------------------------------*/ ++ ++ ++/*----------------------------------------------------------------------------- ++ * Function: RF_ChangeTxPath ++ * ++ * Overview: For RL6052, we must change some RF settign for 1T or 2T. ++ * ++ * Input: u2Byte DataRate // 0x80-8f, 0x90-9f ++ * ++ * Output: NONE ++ * ++ * Return: NONE ++ * ++ * Revised History: ++ * When Who Remark ++ * 09/25/2008 MHC Create Version 0. ++ * Firmwaer support the utility later. ++ * ++ *---------------------------------------------------------------------------*/ ++void rtl8192c_RF_ChangeTxPath( IN PADAPTER Adapter, ++ IN u16 DataRate) ++{ ++// We do not support gain table change inACUT now !!!! Delete later !!! ++#if 0//(RTL92SE_FPGA_VERIFY == 0) ++ static u1Byte RF_Path_Type = 2; // 1 = 1T 2= 2T ++ static u4Byte tx_gain_tbl1[6] ++ = {0x17f50, 0x11f40, 0x0cf30, 0x08720, 0x04310, 0x00100}; ++ static u4Byte tx_gain_tbl2[6] ++ = {0x15ea0, 0x10e90, 0x0c680, 0x08250, 0x04040, 0x00030}; ++ u1Byte i; ++ ++ if (RF_Path_Type == 2 && (DataRate&0xF) <= 0x7) ++ { ++ // Set TX SYNC power G2G3 loop filter ++ PHY_SetRFReg(Adapter, (RF90_RADIO_PATH_E)RF90_PATH_A, ++ RF_TXPA_G2, bRFRegOffsetMask, 0x0f000); ++ PHY_SetRFReg(Adapter, (RF90_RADIO_PATH_E)RF90_PATH_A, ++ RF_TXPA_G3, bRFRegOffsetMask, 0xeacf1); ++ ++ // Change TX AGC gain table ++ for (i = 0; i < 6; i++) ++ PHY_SetRFReg(Adapter, (RF90_RADIO_PATH_E)RF90_PATH_A, ++ RF_TX_AGC, bRFRegOffsetMask, tx_gain_tbl1[i]); ++ ++ // Set PA to high value ++ PHY_SetRFReg(Adapter, (RF90_RADIO_PATH_E)RF90_PATH_A, ++ RF_TXPA_G2, bRFRegOffsetMask, 0x01e39); ++ } ++ else if (RF_Path_Type == 1 && (DataRate&0xF) >= 0x8) ++ { ++ // Set TX SYNC power G2G3 loop filter ++ PHY_SetRFReg(Adapter, (RF90_RADIO_PATH_E)RF90_PATH_A, ++ RF_TXPA_G2, bRFRegOffsetMask, 0x04440); ++ PHY_SetRFReg(Adapter, (RF90_RADIO_PATH_E)RF90_PATH_A, ++ RF_TXPA_G3, bRFRegOffsetMask, 0xea4f1); ++ ++ // Change TX AGC gain table ++ for (i = 0; i < 6; i++) ++ PHY_SetRFReg(Adapter, (RF90_RADIO_PATH_E)RF90_PATH_A, ++ RF_TX_AGC, bRFRegOffsetMask, tx_gain_tbl2[i]); ++ ++ // Set PA low gain ++ PHY_SetRFReg(Adapter, (RF90_RADIO_PATH_E)RF90_PATH_A, ++ RF_TXPA_G2, bRFRegOffsetMask, 0x01e19); ++ } ++#endif ++ ++} /* RF_ChangeTxPath */ ++ ++ ++/*----------------------------------------------------------------------------- ++ * Function: PHY_RF6052SetBandwidth() ++ * ++ * Overview: This function is called by SetBWModeCallback8190Pci() only ++ * ++ * Input: PADAPTER Adapter ++ * WIRELESS_BANDWIDTH_E Bandwidth //20M or 40M ++ * ++ * Output: NONE ++ * ++ * Return: NONE ++ * ++ * Note: For RF type 0222D ++ *---------------------------------------------------------------------------*/ ++VOID ++rtl8192c_PHY_RF6052SetBandwidth( ++ IN PADAPTER Adapter, ++ IN HT_CHANNEL_WIDTH Bandwidth) //20M or 40M ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ ++ switch(Bandwidth) ++ { ++ case HT_CHANNEL_WIDTH_20: ++ pHalData->RfRegChnlVal[0] = ((pHalData->RfRegChnlVal[0] & 0xfffff3ff) | 0x0400); ++ PHY_SetRFReg(Adapter, RF90_PATH_A, RF_CHNLBW, bRFRegOffsetMask, pHalData->RfRegChnlVal[0]); ++ break; ++ ++ case HT_CHANNEL_WIDTH_40: ++ pHalData->RfRegChnlVal[0] = ((pHalData->RfRegChnlVal[0] & 0xfffff3ff)); ++ PHY_SetRFReg(Adapter, RF90_PATH_A, RF_CHNLBW, bRFRegOffsetMask, pHalData->RfRegChnlVal[0]); ++ break; ++ ++ default: ++ //RT_TRACE(COMP_DBG, DBG_LOUD, ("PHY_SetRF8225Bandwidth(): unknown Bandwidth: %#X\n",Bandwidth )); ++ break; ++ } ++ ++} ++ ++ ++/*----------------------------------------------------------------------------- ++ * Function: PHY_RF6052SetCckTxPower ++ * ++ * Overview: ++ * ++ * Input: NONE ++ * ++ * Output: NONE ++ * ++ * Return: NONE ++ * ++ * Revised History: ++ * When Who Remark ++ * 11/05/2008 MHC Simulate 8192series.. ++ * ++ *---------------------------------------------------------------------------*/ ++ ++VOID ++rtl8192c_PHY_RF6052SetCckTxPower( ++ IN PADAPTER Adapter, ++ IN u8* pPowerlevel) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ struct mlme_priv *pmlmepriv = &Adapter->mlmepriv; ++ struct dm_priv *pdmpriv = &pHalData->dmpriv; ++ struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv; ++ //PMGNT_INFO pMgntInfo=&Adapter->MgntInfo; ++ u32 TxAGC[2]={0, 0}, tmpval=0; ++ BOOLEAN TurboScanOff = _FALSE; ++ u8 idx1, idx2; ++ u8* ptr; ++ ++ // 2010/10/18 MH Accorsing to SD3 eechou's suggestion, we need to disable turbo scan for RU. ++ // Otherwise, external PA will be broken if power index > 0x20. ++#ifdef CONFIG_USB_HCI ++ if (pHalData->EEPROMRegulatory != 0 || pHalData->ExternalPA) ++#else ++ if (pHalData->EEPROMRegulatory != 0) ++#endif ++ { ++ //DbgPrint("TurboScanOff=1 EEPROMRegulatory=%d ExternalPA=%d\n", pHalData->EEPROMRegulatory, pHalData->ExternalPA); ++ TurboScanOff = _TRUE; ++ } ++ ++ if(pmlmeext->sitesurvey_res.state == SCAN_PROCESS) ++ { ++ TxAGC[RF90_PATH_A] = 0x3f3f3f3f; ++ TxAGC[RF90_PATH_B] = 0x3f3f3f3f; ++ ++ TurboScanOff = _TRUE;//disable turbo scan ++ ++ if(TurboScanOff) ++ { ++ for(idx1=RF90_PATH_A; idx1<=RF90_PATH_B; idx1++) ++ { ++ TxAGC[idx1] = ++ pPowerlevel[idx1] | (pPowerlevel[idx1]<<8) | ++ (pPowerlevel[idx1]<<16) | (pPowerlevel[idx1]<<24); ++#ifdef CONFIG_USB_HCI ++ // 2010/10/18 MH For external PA module. We need to limit power index to be less than 0x20. ++ if (TxAGC[idx1] > 0x20 && pHalData->ExternalPA) ++ TxAGC[idx1] = 0x20; ++#endif ++ } ++ } ++ } ++ else ++ { ++// 20100427 Joseph: Driver dynamic Tx power shall not affect Tx power. It shall be determined by power training mechanism. ++// Currently, we cannot fully disable driver dynamic tx power mechanism because it is referenced by BT coexist mechanism. ++// In the future, two mechanism shall be separated from each other and maintained independantly. Thanks for Lanhsin's reminder. ++ if(pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level1) ++ { ++ TxAGC[RF90_PATH_A] = 0x10101010; ++ TxAGC[RF90_PATH_B] = 0x10101010; ++ } ++ else if(pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level2) ++ { ++ TxAGC[RF90_PATH_A] = 0x00000000; ++ TxAGC[RF90_PATH_B] = 0x00000000; ++ } ++ else ++ { ++ for(idx1=RF90_PATH_A; idx1<=RF90_PATH_B; idx1++) ++ { ++ TxAGC[idx1] = ++ pPowerlevel[idx1] | (pPowerlevel[idx1]<<8) | ++ (pPowerlevel[idx1]<<16) | (pPowerlevel[idx1]<<24); ++ } ++ ++ if(pHalData->EEPROMRegulatory==0) ++ { ++ tmpval = (pHalData->MCSTxPowerLevelOriginalOffset[0][6]) + ++ (pHalData->MCSTxPowerLevelOriginalOffset[0][7]<<8); ++ TxAGC[RF90_PATH_A] += tmpval; ++ ++ tmpval = (pHalData->MCSTxPowerLevelOriginalOffset[0][14]) + ++ (pHalData->MCSTxPowerLevelOriginalOffset[0][15]<<24); ++ TxAGC[RF90_PATH_B] += tmpval; ++ } ++ } ++ } ++ ++ for(idx1=RF90_PATH_A; idx1<=RF90_PATH_B; idx1++) ++ { ++ ptr = (u8*)(&(TxAGC[idx1])); ++ for(idx2=0; idx2<4; idx2++) ++ { ++ if(*ptr > RF6052_MAX_TX_PWR) ++ *ptr = RF6052_MAX_TX_PWR; ++ ptr++; ++ } ++ } ++ ++ // rf-A cck tx power ++ tmpval = TxAGC[RF90_PATH_A]&0xff; ++ PHY_SetBBReg(Adapter, rTxAGC_A_CCK1_Mcs32, bMaskByte1, tmpval); ++ //RTPRINT(FPHY, PHY_TXPWR, ("CCK PWR 1M (rf-A) = 0x%x (reg 0x%x)\n", tmpval, rTxAGC_A_CCK1_Mcs32)); ++ tmpval = TxAGC[RF90_PATH_A]>>8; ++ PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, 0xffffff00, tmpval); ++ //RTPRINT(FPHY, PHY_TXPWR, ("CCK PWR 2~11M (rf-A) = 0x%x (reg 0x%x)\n", tmpval, rTxAGC_B_CCK11_A_CCK2_11)); ++ ++ // rf-B cck tx power ++ tmpval = TxAGC[RF90_PATH_B]>>24; ++ PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte0, tmpval); ++ //RTPRINT(FPHY, PHY_TXPWR, ("CCK PWR 11M (rf-B) = 0x%x (reg 0x%x)\n", tmpval, rTxAGC_B_CCK11_A_CCK2_11)); ++ tmpval = TxAGC[RF90_PATH_B]&0x00ffffff; ++ PHY_SetBBReg(Adapter, rTxAGC_B_CCK1_55_Mcs32, 0xffffff00, tmpval); ++ //RTPRINT(FPHY, PHY_TXPWR, ("CCK PWR 1~5.5M (rf-B) = 0x%x (reg 0x%x)\n", ++ // tmpval, rTxAGC_B_CCK1_55_Mcs32)); ++ ++} /* PHY_RF6052SetCckTxPower */ ++ ++// ++// powerbase0 for OFDM rates ++// powerbase1 for HT MCS rates ++// ++static void getPowerBase( ++ IN PADAPTER Adapter, ++ IN u8* pPowerLevel, ++ IN u8 Channel, ++ IN OUT u32* OfdmBase, ++ IN OUT u32* MCSBase ++ ) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ u32 powerBase0, powerBase1; ++ u8 Legacy_pwrdiff=0, HT20_pwrdiff=0; ++ u8 i, powerlevel[2]; ++ ++ for(i=0; i<2; i++) ++ { ++ powerlevel[i] = pPowerLevel[i]; ++ Legacy_pwrdiff = pHalData->TxPwrLegacyHtDiff[i][Channel-1]; ++ powerBase0 = powerlevel[i] + Legacy_pwrdiff; ++ ++ powerBase0 = (powerBase0<<24) | (powerBase0<<16) |(powerBase0<<8) |powerBase0; ++ *(OfdmBase+i) = powerBase0; ++ //RTPRINT(FPHY, PHY_TXPWR, (" [OFDM power base index rf(%c) = 0x%x]\n", ((i==0)?'A':'B'), *(OfdmBase+i))); ++ } ++ ++ for(i=0; i<2; i++) ++ { ++ //Check HT20 to HT40 diff ++ if(pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_20) ++ { ++ HT20_pwrdiff = pHalData->TxPwrHt20Diff[i][Channel-1]; ++ powerlevel[i] += HT20_pwrdiff; ++ } ++ powerBase1 = powerlevel[i]; ++ powerBase1 = (powerBase1<<24) | (powerBase1<<16) |(powerBase1<<8) |powerBase1; ++ *(MCSBase+i) = powerBase1; ++ //RTPRINT(FPHY, PHY_TXPWR, (" [MCS power base index rf(%c) = 0x%x]\n", ((i==0)?'A':'B'), *(MCSBase+i))); ++ } ++} ++ ++static void getTxPowerWriteValByRegulatory( ++ IN PADAPTER Adapter, ++ IN u8 Channel, ++ IN u8 index, ++ IN u32* powerBase0, ++ IN u32* powerBase1, ++ OUT u32* pOutWriteVal ++ ) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ struct dm_priv *pdmpriv = &pHalData->dmpriv; ++ u8 i, chnlGroup, pwr_diff_limit[4]; ++ u32 writeVal, customer_limit, rf; ++ ++ // ++ // Index 0 & 1= legacy OFDM, 2-5=HT_MCS rate ++ // ++ for(rf=0; rf<2; rf++) ++ { ++ switch(pHalData->EEPROMRegulatory) ++ { ++ case 0: // Realtek better performance ++ // increase power diff defined by Realtek for large power ++ chnlGroup = 0; ++ //RTPRINT(FPHY, PHY_TXPWR, ("MCSTxPowerLevelOriginalOffset[%d][%d] = 0x%x\n", ++ // chnlGroup, index, pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)])); ++ writeVal = pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)] + ++ ((index<2)?powerBase0[rf]:powerBase1[rf]); ++ //RTPRINT(FPHY, PHY_TXPWR, ("RTK better performance, writeVal(%c) = 0x%x\n", ((rf==0)?'A':'B'), writeVal)); ++ break; ++ case 1: // Realtek regulatory ++ // increase power diff defined by Realtek for regulatory ++ { ++ if(pHalData->pwrGroupCnt == 1) ++ chnlGroup = 0; ++ if(pHalData->pwrGroupCnt >= 3) ++ { ++ if(Channel <= 3) ++ chnlGroup = 0; ++ else if(Channel >= 4 && Channel <= 9) ++ chnlGroup = 1; ++ else if(Channel > 9) ++ chnlGroup = 2; ++ ++ if(pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_20) ++ chnlGroup++; ++ else ++ chnlGroup+=4; ++ } ++ //RTPRINT(FPHY, PHY_TXPWR, ("MCSTxPowerLevelOriginalOffset[%d][%d] = 0x%x\n", ++ //chnlGroup, index, pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)])); ++ writeVal = pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)] + ++ ((index<2)?powerBase0[rf]:powerBase1[rf]); ++ //RTPRINT(FPHY, PHY_TXPWR, ("Realtek regulatory, 20MHz, writeVal(%c) = 0x%x\n", ((rf==0)?'A':'B'), writeVal)); ++ } ++ break; ++ case 2: // Better regulatory ++ // don't increase any power diff ++ writeVal = ((index<2)?powerBase0[rf]:powerBase1[rf]); ++ //RTPRINT(FPHY, PHY_TXPWR, ("Better regulatory, writeVal(%c) = 0x%x\n", ((rf==0)?'A':'B'), writeVal)); ++ break; ++ case 3: // Customer defined power diff. ++ // increase power diff defined by customer. ++ chnlGroup = 0; ++ //RTPRINT(FPHY, PHY_TXPWR, ("MCSTxPowerLevelOriginalOffset[%d][%d] = 0x%x\n", ++ // chnlGroup, index, pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)])); ++ ++ if (pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_40) ++ { ++ //RTPRINT(FPHY, PHY_TXPWR, ("customer's limit, 40MHz rf(%c) = 0x%x\n", ++ // ((rf==0)?'A':'B'), pHalData->PwrGroupHT40[rf][Channel-1])); ++ } ++ else ++ { ++ //RTPRINT(FPHY, PHY_TXPWR, ("customer's limit, 20MHz rf(%c) = 0x%x\n", ++ // ((rf==0)?'A':'B'), pHalData->PwrGroupHT20[rf][Channel-1])); ++ } ++ for (i=0; i<4; i++) ++ { ++ pwr_diff_limit[i] = (u8)((pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)]&(0x7f<<(i*8)))>>(i*8)); ++ if (pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_40) ++ { ++ if(pwr_diff_limit[i] > pHalData->PwrGroupHT40[rf][Channel-1]) ++ pwr_diff_limit[i] = pHalData->PwrGroupHT40[rf][Channel-1]; ++ } ++ else ++ { ++ if(pwr_diff_limit[i] > pHalData->PwrGroupHT20[rf][Channel-1]) ++ pwr_diff_limit[i] = pHalData->PwrGroupHT20[rf][Channel-1]; ++ } ++ } ++ customer_limit = (pwr_diff_limit[3]<<24) | (pwr_diff_limit[2]<<16) | ++ (pwr_diff_limit[1]<<8) | (pwr_diff_limit[0]); ++ //RTPRINT(FPHY, PHY_TXPWR, ("Customer's limit rf(%c) = 0x%x\n", ((rf==0)?'A':'B'), customer_limit)); ++ ++ writeVal = customer_limit + ((index<2)?powerBase0[rf]:powerBase1[rf]); ++ //RTPRINT(FPHY, PHY_TXPWR, ("Customer, writeVal rf(%c)= 0x%x\n", ((rf==0)?'A':'B'), writeVal)); ++ break; ++ default: ++ chnlGroup = 0; ++ writeVal = pHalData->MCSTxPowerLevelOriginalOffset[chnlGroup][index+(rf?8:0)] + ++ ((index<2)?powerBase0[rf]:powerBase1[rf]); ++ //RTPRINT(FPHY, PHY_TXPWR, ("RTK better performance, writeVal rf(%c) = 0x%x\n", ((rf==0)?'A':'B'), writeVal)); ++ break; ++ } ++ ++// 20100427 Joseph: Driver dynamic Tx power shall not affect Tx power. It shall be determined by power training mechanism. ++// Currently, we cannot fully disable driver dynamic tx power mechanism because it is referenced by BT coexist mechanism. ++// In the future, two mechanism shall be separated from each other and maintained independantly. Thanks for Lanhsin's reminder. ++ ++ if(pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level1) ++ writeVal = 0x14141414; ++ else if(pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level2) ++ writeVal = 0x00000000; ++ ++ ++ // 20100628 Joseph: High power mode for BT-Coexist mechanism. ++ // This mechanism is only applied when Driver-Highpower-Mechanism is OFF. ++ if(pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_BT1) ++ { ++ //RTPRINT(FBT, BT_TRACE, ("Tx Power (-6)\n")); ++ writeVal = writeVal - 0x06060606; ++ } ++ else if(pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_BT2) ++ { ++ //RTPRINT(FBT, BT_TRACE, ("Tx Power (-0)\n")); ++ writeVal = writeVal; ++ } ++ *(pOutWriteVal+rf) = writeVal; ++ } ++} ++ ++static void writeOFDMPowerReg( ++ IN PADAPTER Adapter, ++ IN u8 index, ++ IN u32* pValue ++ ) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ u16 RegOffset_A[6] = { rTxAGC_A_Rate18_06, rTxAGC_A_Rate54_24, ++ rTxAGC_A_Mcs03_Mcs00, rTxAGC_A_Mcs07_Mcs04, ++ rTxAGC_A_Mcs11_Mcs08, rTxAGC_A_Mcs15_Mcs12}; ++ u16 RegOffset_B[6] = { rTxAGC_B_Rate18_06, rTxAGC_B_Rate54_24, ++ rTxAGC_B_Mcs03_Mcs00, rTxAGC_B_Mcs07_Mcs04, ++ rTxAGC_B_Mcs11_Mcs08, rTxAGC_B_Mcs15_Mcs12}; ++ u8 i, rf, pwr_val[4]; ++ u32 writeVal; ++ u16 RegOffset; ++ ++ for(rf=0; rf<2; rf++) ++ { ++ writeVal = pValue[rf]; ++ for(i=0; i<4; i++) ++ { ++ pwr_val[i] = (u8)((writeVal & (0x7f<<(i*8)))>>(i*8)); ++ if (pwr_val[i] > RF6052_MAX_TX_PWR) ++ pwr_val[i] = RF6052_MAX_TX_PWR; ++ } ++ writeVal = (pwr_val[3]<<24) | (pwr_val[2]<<16) |(pwr_val[1]<<8) |pwr_val[0]; ++ ++ if(rf == 0) ++ RegOffset = RegOffset_A[index]; ++ else ++ RegOffset = RegOffset_B[index]; ++ ++ PHY_SetBBReg(Adapter, RegOffset, bMaskDWord, writeVal); ++ //RTPRINT(FPHY, PHY_TXPWR, ("Set 0x%x = %08x\n", RegOffset, writeVal)); ++ ++ // 201005115 Joseph: Set Tx Power diff for Tx power training mechanism. ++ if(((pHalData->rf_type == RF_2T2R) && ++ (RegOffset == rTxAGC_A_Mcs15_Mcs12 || RegOffset == rTxAGC_B_Mcs15_Mcs12))|| ++ ((pHalData->rf_type != RF_2T2R) && ++ (RegOffset == rTxAGC_A_Mcs07_Mcs04 || RegOffset == rTxAGC_B_Mcs07_Mcs04)) ) ++ { ++ writeVal = pwr_val[3]; ++ if(RegOffset == rTxAGC_A_Mcs15_Mcs12 || RegOffset == rTxAGC_A_Mcs07_Mcs04) ++ RegOffset = 0xc90; ++ if(RegOffset == rTxAGC_B_Mcs15_Mcs12 || RegOffset == rTxAGC_B_Mcs07_Mcs04) ++ RegOffset = 0xc98; ++ for(i=0; i<3; i++) ++ { ++ if(i!=2) ++ writeVal = (writeVal>8)?(writeVal-8):0; ++ else ++ writeVal = (writeVal>6)?(writeVal-6):0; ++ rtw_write8(Adapter, (u32)(RegOffset+i), (u8)writeVal); ++ } ++ } ++ } ++} ++/*----------------------------------------------------------------------------- ++ * Function: PHY_RF6052SetOFDMTxPower ++ * ++ * Overview: For legacy and HY OFDM, we must read EEPROM TX power index for ++ * different channel and read original value in TX power register area from ++ * 0xe00. We increase offset and original value to be correct tx pwr. ++ * ++ * Input: NONE ++ * ++ * Output: NONE ++ * ++ * Return: NONE ++ * ++ * Revised History: ++ * When Who Remark ++ * 11/05/2008 MHC Simulate 8192 series method. ++ * 01/06/2009 MHC 1. Prevent Path B tx power overflow or underflow dure to ++ * A/B pwr difference or legacy/HT pwr diff. ++ * 2. We concern with path B legacy/HT OFDM difference. ++ * 01/22/2009 MHC Support new EPRO format from SD3. ++ * ++ *---------------------------------------------------------------------------*/ ++VOID ++rtl8192c_PHY_RF6052SetOFDMTxPower( ++ IN PADAPTER Adapter, ++ IN u8* pPowerLevel, ++ IN u8 Channel) ++{ ++ //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ u32 writeVal[2], powerBase0[2], powerBase1[2]; ++ u8 index = 0; ++ ++ getPowerBase(Adapter, pPowerLevel, Channel, &powerBase0[0], &powerBase1[0]); ++ ++ for(index=0; index<6; index++) ++ { ++ getTxPowerWriteValByRegulatory(Adapter, Channel, index, ++ &powerBase0[0], &powerBase1[0], &writeVal[0]); ++ ++ writeOFDMPowerReg(Adapter, index, &writeVal[0]); ++ } ++ ++} ++ ++ ++static VOID ++phy_RF6052_Config_HardCode( ++ IN PADAPTER Adapter ++ ) ++{ ++ ++ // Set Default Bandwidth to 20M ++ //Adapter->HalFunc .SetBWModeHandler(Adapter, HT_CHANNEL_WIDTH_20); ++ ++ // TODO: Set Default Channel to channel one for RTL8225 ++ ++} ++ ++static int ++phy_RF6052_Config_ParaFile( ++ IN PADAPTER Adapter ++ ) ++{ ++ u32 u4RegValue; ++ u8 eRFPath; ++ BB_REGISTER_DEFINITION_T *pPhyReg; ++ ++ int rtStatus = _SUCCESS; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ static char sz88CRadioAFile[] = RTL8188C_PHY_RADIO_A; ++ static char sz88CRadioBFile[] = RTL8188C_PHY_RADIO_B; ++#ifdef CONFIG_USB_HCI ++ static char sz88CRadioAFile_mCard[] = RTL8188C_PHY_RADIO_A_mCard; ++ static char sz88CRadioBFile_mCard[] = RTL8188C_PHY_RADIO_B_mCard; ++ static char sz88CRadioAFile_HP[] = RTL8188C_PHY_RADIO_A_HP; ++#endif ++ static char sz92CRadioAFile[] = RTL8192C_PHY_RADIO_A; ++ static char sz92CRadioBFile[] = RTL8192C_PHY_RADIO_B; ++ static char sz8723RadioAFile[] = RTL8723_PHY_RADIO_A; ++ static char sz8723RadioBFile[] = RTL8723_PHY_RADIO_B; ++ char *pszRadioAFile, *pszRadioBFile; ++ ++ ++ if(IS_HARDWARE_TYPE_8192C(Adapter)) ++ { ++ if(IS_92C_SERIAL( pHalData->VersionID))// 88c's IPA is different from 92c's ++ { ++ if(IS_NORMAL_CHIP(pHalData->VersionID)) ++ { ++ pszRadioAFile = sz92CRadioAFile; ++ pszRadioBFile = sz92CRadioBFile; ++ } ++ else ++ { ++ rtStatus = _FAIL; ++ return rtStatus; ++ } ++ } ++ else ++ { ++ if(IS_NORMAL_CHIP(pHalData->VersionID)) ++ { ++ pszRadioAFile = sz88CRadioAFile; ++ pszRadioBFile = sz88CRadioBFile; ++#ifdef CONFIG_USB_HCI ++ if( BOARD_MINICARD == pHalData->BoardType) ++ { ++ pszRadioAFile = sz88CRadioAFile_mCard; ++ pszRadioBFile = sz88CRadioBFile_mCard; ++ } ++ else if( BOARD_USB_High_PA == pHalData->BoardType) ++ { ++ pszRadioAFile = sz88CRadioAFile_HP; ++ } ++#endif ++ } ++ else ++ { ++ rtStatus = _FAIL; ++ return rtStatus; ++ } ++ } ++ } ++ else if(IS_HARDWARE_TYPE_8723(Adapter)) ++ { ++ pszRadioAFile = sz8723RadioAFile; ++ pszRadioBFile = sz8723RadioBFile; ++ } ++ ++ //3//----------------------------------------------------------------- ++ //3// <2> Initialize RF ++ //3//----------------------------------------------------------------- ++ //for(eRFPath = RF90_PATH_A; eRFPath NumTotalRFPath; eRFPath++) ++ for(eRFPath = 0; eRFPath NumTotalRFPath; eRFPath++) ++ { ++ ++ pPhyReg = &pHalData->PHYRegDef[eRFPath]; ++ ++ /*----Store original RFENV control type----*/ ++ switch(eRFPath) ++ { ++ case RF90_PATH_A: ++ case RF90_PATH_C: ++ u4RegValue = PHY_QueryBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV); ++ break; ++ case RF90_PATH_B : ++ case RF90_PATH_D: ++ u4RegValue = PHY_QueryBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV<<16); ++ break; ++ } ++ ++ /*----Set RF_ENV enable----*/ ++ PHY_SetBBReg(Adapter, pPhyReg->rfintfe, bRFSI_RFENV<<16, 0x1); ++ rtw_udelay_os(1);//PlatformStallExecution(1); ++ ++ /*----Set RF_ENV output high----*/ ++ PHY_SetBBReg(Adapter, pPhyReg->rfintfo, bRFSI_RFENV, 0x1); ++ rtw_udelay_os(1);//PlatformStallExecution(1); ++ ++ /* Set bit number of Address and Data for RF register */ ++ PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, b3WireAddressLength, 0x0); // Set 1 to 4 bits for 8255 ++ rtw_udelay_os(1);//PlatformStallExecution(1); ++ ++ PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, b3WireDataLength, 0x0); // Set 0 to 12 bits for 8255 ++ rtw_udelay_os(1);//PlatformStallExecution(1); ++ ++ /*----Initialize RF fom connfiguration file----*/ ++ switch(eRFPath) ++ { ++ case RF90_PATH_A: ++#ifdef CONFIG_EMBEDDED_FWIMG ++ rtStatus= rtl8192c_PHY_ConfigRFWithHeaderFile(Adapter,(RF90_RADIO_PATH_E)eRFPath); ++#else ++ rtStatus = rtl8192c_PHY_ConfigRFWithParaFile(Adapter, pszRadioAFile, (RF90_RADIO_PATH_E)eRFPath); ++#endif ++ break; ++ case RF90_PATH_B: ++#ifdef CONFIG_EMBEDDED_FWIMG ++ rtStatus = rtl8192c_PHY_ConfigRFWithHeaderFile(Adapter,(RF90_RADIO_PATH_E)eRFPath); ++#else ++ rtStatus = rtl8192c_PHY_ConfigRFWithParaFile(Adapter, pszRadioBFile, (RF90_RADIO_PATH_E)eRFPath); ++#endif ++ break; ++ case RF90_PATH_C: ++ break; ++ case RF90_PATH_D: ++ break; ++ } ++ ++ /*----Restore RFENV control type----*/; ++ switch(eRFPath) ++ { ++ case RF90_PATH_A: ++ case RF90_PATH_C: ++ PHY_SetBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV, u4RegValue); ++ break; ++ case RF90_PATH_B : ++ case RF90_PATH_D: ++ PHY_SetBBReg(Adapter, pPhyReg->rfintfs, bRFSI_RFENV<<16, u4RegValue); ++ break; ++ } ++ ++ if(rtStatus != _SUCCESS){ ++ //RT_TRACE(COMP_FPGA, DBG_LOUD, ("phy_RF6052_Config_ParaFile():Radio[%d] Fail!!", eRFPath)); ++ goto phy_RF6052_Config_ParaFile_Fail; ++ } ++ ++ } ++ ++ //RT_TRACE(COMP_INIT, DBG_LOUD, ("<---phy_RF6052_Config_ParaFile()\n")); ++ return rtStatus; ++ ++phy_RF6052_Config_ParaFile_Fail: ++ return rtStatus; ++} ++ ++ ++int ++PHY_RF6052_Config8192C( ++ IN PADAPTER Adapter) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ int rtStatus = _SUCCESS; ++ ++ // ++ // Initialize general global value ++ // ++ // TODO: Extend RF_PATH_C and RF_PATH_D in the future ++ if(pHalData->rf_type == RF_1T1R) ++ pHalData->NumTotalRFPath = 1; ++ else ++ pHalData->NumTotalRFPath = 2; ++ ++ // ++ // Config BB and RF ++ // ++ rtStatus = phy_RF6052_Config_ParaFile(Adapter); ++#if 0 ++ switch( Adapter->MgntInfo.bRegHwParaFile ) ++ { ++ case 0: ++ phy_RF6052_Config_HardCode(Adapter); ++ break; ++ ++ case 1: ++ rtStatus = phy_RF6052_Config_ParaFile(Adapter); ++ break; ++ ++ case 2: ++ // Partial Modify. ++ phy_RF6052_Config_HardCode(Adapter); ++ phy_RF6052_Config_ParaFile(Adapter); ++ break; ++ ++ default: ++ phy_RF6052_Config_HardCode(Adapter); ++ break; ++ } ++#endif ++ return rtStatus; ++ ++} ++ ++ ++// ++// ==> RF shadow Operation API Code Section!!! ++// ++/*----------------------------------------------------------------------------- ++ * Function: PHY_RFShadowRead ++ * PHY_RFShadowWrite ++ * PHY_RFShadowCompare ++ * PHY_RFShadowRecorver ++ * PHY_RFShadowCompareAll ++ * PHY_RFShadowRecorverAll ++ * PHY_RFShadowCompareFlagSet ++ * PHY_RFShadowRecorverFlagSet ++ * ++ * Overview: When we set RF register, we must write shadow at first. ++ * When we are running, we must compare shadow abd locate error addr. ++ * Decide to recorver or not. ++ * ++ * Input: NONE ++ * ++ * Output: NONE ++ * ++ * Return: NONE ++ * ++ * Revised History: ++ * When Who Remark ++ * 11/20/2008 MHC Create Version 0. ++ * ++ *---------------------------------------------------------------------------*/ ++u32 ++PHY_RFShadowRead( ++ IN PADAPTER Adapter, ++ IN RF90_RADIO_PATH_E eRFPath, ++ IN u32 Offset) ++{ ++ return RF_Shadow[eRFPath][Offset].Value; ++ ++} /* PHY_RFShadowRead */ ++ ++ ++VOID ++PHY_RFShadowWrite( ++ IN PADAPTER Adapter, ++ IN RF90_RADIO_PATH_E eRFPath, ++ IN u32 Offset, ++ IN u32 Data) ++{ ++ RF_Shadow[eRFPath][Offset].Value = (Data & bRFRegOffsetMask); ++ RF_Shadow[eRFPath][Offset].Driver_Write = _TRUE; ++ ++} /* PHY_RFShadowWrite */ ++ ++ ++BOOLEAN ++PHY_RFShadowCompare( ++ IN PADAPTER Adapter, ++ IN RF90_RADIO_PATH_E eRFPath, ++ IN u32 Offset) ++{ ++ u32 reg; ++ // Check if we need to check the register ++ if (RF_Shadow[eRFPath][Offset].Compare == _TRUE) ++ { ++ reg = PHY_QueryRFReg(Adapter, eRFPath, Offset, bRFRegOffsetMask); ++ // Compare shadow and real rf register for 20bits!! ++ if (RF_Shadow[eRFPath][Offset].Value != reg) ++ { ++ // Locate error position. ++ RF_Shadow[eRFPath][Offset].ErrorOrNot = _TRUE; ++ //RT_TRACE(COMP_INIT, DBG_LOUD, ++ //("PHY_RFShadowCompare RF-%d Addr%02lx Err = %05lx\n", ++ //eRFPath, Offset, reg)); ++ } ++ return RF_Shadow[eRFPath][Offset].ErrorOrNot ; ++ } ++ return _FALSE; ++} /* PHY_RFShadowCompare */ ++ ++ ++VOID ++PHY_RFShadowRecorver( ++ IN PADAPTER Adapter, ++ IN RF90_RADIO_PATH_E eRFPath, ++ IN u32 Offset) ++{ ++ // Check if the address is error ++ if (RF_Shadow[eRFPath][Offset].ErrorOrNot == _TRUE) ++ { ++ // Check if we need to recorver the register. ++ if (RF_Shadow[eRFPath][Offset].Recorver == _TRUE) ++ { ++ PHY_SetRFReg(Adapter, eRFPath, Offset, bRFRegOffsetMask, ++ RF_Shadow[eRFPath][Offset].Value); ++ //RT_TRACE(COMP_INIT, DBG_LOUD, ++ //("PHY_RFShadowRecorver RF-%d Addr%02lx=%05lx", ++ //eRFPath, Offset, RF_Shadow[eRFPath][Offset].Value)); ++ } ++ } ++ ++} /* PHY_RFShadowRecorver */ ++ ++ ++VOID ++PHY_RFShadowCompareAll( ++ IN PADAPTER Adapter) ++{ ++ u32 eRFPath; ++ u32 Offset; ++ ++ for (eRFPath = 0; eRFPath < RF6052_MAX_PATH; eRFPath++) ++ { ++ for (Offset = 0; Offset <= RF6052_MAX_REG; Offset++) ++ { ++ PHY_RFShadowCompare(Adapter, (RF90_RADIO_PATH_E)eRFPath, Offset); ++ } ++ } ++ ++} /* PHY_RFShadowCompareAll */ ++ ++ ++VOID ++PHY_RFShadowRecorverAll( ++ IN PADAPTER Adapter) ++{ ++ u32 eRFPath; ++ u32 Offset; ++ ++ for (eRFPath = 0; eRFPath < RF6052_MAX_PATH; eRFPath++) ++ { ++ for (Offset = 0; Offset <= RF6052_MAX_REG; Offset++) ++ { ++ PHY_RFShadowRecorver(Adapter, (RF90_RADIO_PATH_E)eRFPath, Offset); ++ } ++ } ++ ++} /* PHY_RFShadowRecorverAll */ ++ ++ ++VOID ++PHY_RFShadowCompareFlagSet( ++ IN PADAPTER Adapter, ++ IN RF90_RADIO_PATH_E eRFPath, ++ IN u32 Offset, ++ IN u8 Type) ++{ ++ // Set True or False!!! ++ RF_Shadow[eRFPath][Offset].Compare = Type; ++ ++} /* PHY_RFShadowCompareFlagSet */ ++ ++ ++VOID ++PHY_RFShadowRecorverFlagSet( ++ IN PADAPTER Adapter, ++ IN RF90_RADIO_PATH_E eRFPath, ++ IN u32 Offset, ++ IN u8 Type) ++{ ++ // Set True or False!!! ++ RF_Shadow[eRFPath][Offset].Recorver= Type; ++ ++} /* PHY_RFShadowRecorverFlagSet */ ++ ++ ++VOID ++PHY_RFShadowCompareFlagSetAll( ++ IN PADAPTER Adapter) ++{ ++ u32 eRFPath; ++ u32 Offset; ++ ++ for (eRFPath = 0; eRFPath < RF6052_MAX_PATH; eRFPath++) ++ { ++ for (Offset = 0; Offset <= RF6052_MAX_REG; Offset++) ++ { ++ // 2008/11/20 MH For S3S4 test, we only check reg 26/27 now!!!! ++ if (Offset != 0x26 && Offset != 0x27) ++ PHY_RFShadowCompareFlagSet(Adapter, (RF90_RADIO_PATH_E)eRFPath, Offset, _FALSE); ++ else ++ PHY_RFShadowCompareFlagSet(Adapter, (RF90_RADIO_PATH_E)eRFPath, Offset, _TRUE); ++ } ++ } ++ ++} /* PHY_RFShadowCompareFlagSetAll */ ++ ++ ++VOID ++PHY_RFShadowRecorverFlagSetAll( ++ IN PADAPTER Adapter) ++{ ++ u32 eRFPath; ++ u32 Offset; ++ ++ for (eRFPath = 0; eRFPath < RF6052_MAX_PATH; eRFPath++) ++ { ++ for (Offset = 0; Offset <= RF6052_MAX_REG; Offset++) ++ { ++ // 2008/11/20 MH For S3S4 test, we only check reg 26/27 now!!!! ++ if (Offset != 0x26 && Offset != 0x27) ++ PHY_RFShadowRecorverFlagSet(Adapter, (RF90_RADIO_PATH_E)eRFPath, Offset, _FALSE); ++ else ++ PHY_RFShadowRecorverFlagSet(Adapter, (RF90_RADIO_PATH_E)eRFPath, Offset, _TRUE); ++ } ++ } ++ ++} /* PHY_RFShadowCompareFlagSetAll */ ++ ++VOID ++PHY_RFShadowRefresh( ++ IN PADAPTER Adapter) ++{ ++ u32 eRFPath; ++ u32 Offset; ++ ++ for (eRFPath = 0; eRFPath < RF6052_MAX_PATH; eRFPath++) ++ { ++ for (Offset = 0; Offset <= RF6052_MAX_REG; Offset++) ++ { ++ RF_Shadow[eRFPath][Offset].Value = 0; ++ RF_Shadow[eRFPath][Offset].Compare = _FALSE; ++ RF_Shadow[eRFPath][Offset].Recorver = _FALSE; ++ RF_Shadow[eRFPath][Offset].ErrorOrNot = _FALSE; ++ RF_Shadow[eRFPath][Offset].Driver_Write = _FALSE; ++ } ++ } ++ ++} /* PHY_RFShadowRead */ ++ ++/* End of HalRf6052.c */ ++ +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/hal/rtl8192c/rtl8192c_rxdesc.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/hal/rtl8192c/rtl8192c_rxdesc.c 2013-07-26 19:36:05.000000000 +0000 +@@ -0,0 +1,767 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++******************************************************************************/ ++#define _RTL8192C_REDESC_C_ ++#include ++#include ++#include ++#include ++ ++static u8 evm_db2percentage(s8 value) ++{ ++ // ++ // -33dB~0dB to 0%~99% ++ // ++ s8 ret_val; ++ ++ ret_val = value; ++ //ret_val /= 2; ++ ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("EVMdbToPercentage92S Value=%d / %x \n", ret_val, ret_val)); ++ ++ if(ret_val >= 0) ++ ret_val = 0; ++ if(ret_val <= -33) ++ ret_val = -33; ++ ++ ret_val = 0 - ret_val; ++ ret_val*=3; ++ ++ if(ret_val == 99) ++ ret_val = 100; ++ ++ return(ret_val); ++} ++ ++ ++static s32 signal_scale_mapping(_adapter *padapter, s32 cur_sig ) ++{ ++ s32 ret_sig; ++ ++#ifdef CONFIG_USB_HCI ++ if(cur_sig >= 51 && cur_sig <= 100) ++ { ++ ret_sig = 100; ++ } ++ else if(cur_sig >= 41 && cur_sig <= 50) ++ { ++ ret_sig = 80 + ((cur_sig - 40)*2); ++ } ++ else if(cur_sig >= 31 && cur_sig <= 40) ++ { ++ ret_sig = 66 + (cur_sig - 30); ++ } ++ else if(cur_sig >= 21 && cur_sig <= 30) ++ { ++ ret_sig = 54 + (cur_sig - 20); ++ } ++ else if(cur_sig >= 10 && cur_sig <= 20) ++ { ++ ret_sig = 42 + (((cur_sig - 10) * 2) / 3); ++ } ++ else if(cur_sig >= 5 && cur_sig <= 9) ++ { ++ ret_sig = 22 + (((cur_sig - 5) * 3) / 2); ++ } ++ else if(cur_sig >= 1 && cur_sig <= 4) ++ { ++ ret_sig = 6 + (((cur_sig - 1) * 3) / 2); ++ } ++ else ++ { ++ ret_sig = cur_sig; ++ } ++#else ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); ++ ++ if(pHalData->CustomerID == RT_CID_819x_Lenovo) ++ { ++ // Step 1. Scale mapping. ++ // 20100611 Joseph: Re-tunning RSSI presentation for Lenovo. ++ // 20100426 Joseph: Modify Signal strength mapping. ++ // This modification makes the RSSI indication similar to Intel solution. ++ // 20100414 Joseph: Tunning RSSI for Lenovo according to RTL8191SE. ++ if(cur_sig >= 54 && cur_sig <= 100) ++ { ++ ret_sig = 100; ++ } ++ else if(cur_sig>=42 && cur_sig <= 53 ) ++ { ++ ret_sig = 95; ++ } ++ else if(cur_sig>=36 && cur_sig <= 41 ) ++ { ++ ret_sig = 74 + ((cur_sig - 36) *20)/6; ++ } ++ else if(cur_sig>=33 && cur_sig <= 35 ) ++ { ++ ret_sig = 65 + ((cur_sig - 33) *8)/2; ++ } ++ else if(cur_sig>=18 && cur_sig <= 32 ) ++ { ++ ret_sig = 62 + ((cur_sig - 18) *2)/15; ++ } ++ else if(cur_sig>=15 && cur_sig <= 17 ) ++ { ++ ret_sig = 33 + ((cur_sig - 15) *28)/2; ++ } ++ else if(cur_sig>=10 && cur_sig <= 14 ) ++ { ++ ret_sig = 39; ++ } ++ else if(cur_sig>=8 && cur_sig <= 9 ) ++ { ++ ret_sig = 33; ++ } ++ else if(cur_sig <= 8 ) ++ { ++ ret_sig = 19; ++ } ++ } ++ else ++ { ++ // Step 1. Scale mapping. ++ if(cur_sig >= 61 && cur_sig <= 100) ++ { ++ ret_sig = 90 + ((cur_sig - 60) / 4); ++ } ++ else if(cur_sig >= 41 && cur_sig <= 60) ++ { ++ ret_sig = 78 + ((cur_sig - 40) / 2); ++ } ++ else if(cur_sig >= 31 && cur_sig <= 40) ++ { ++ ret_sig = 66 + (cur_sig - 30); ++ } ++ else if(cur_sig >= 21 && cur_sig <= 30) ++ { ++ ret_sig = 54 + (cur_sig - 20); ++ } ++ else if(cur_sig >= 5 && cur_sig <= 20) ++ { ++ ret_sig = 42 + (((cur_sig - 5) * 2) / 3); ++ } ++ else if(cur_sig == 4) ++ { ++ ret_sig = 36; ++ } ++ else if(cur_sig == 3) ++ { ++ ret_sig = 27; ++ } ++ else if(cur_sig == 2) ++ { ++ ret_sig = 18; ++ } ++ else if(cur_sig == 1) ++ { ++ ret_sig = 9; ++ } ++ else ++ { ++ ret_sig = cur_sig; ++ } ++ } ++#endif ++ ++ return ret_sig; ++} ++ ++ ++static s32 translate2dbm(u8 signal_strength_idx) ++{ ++ s32 signal_power; // in dBm. ++ ++ ++ // Translate to dBm (x=0.5y-95). ++ signal_power = (s32)((signal_strength_idx + 1) >> 1); ++ signal_power -= 95; ++ ++ return signal_power; ++} ++ ++void rtl8192c_query_rx_phy_status(union recv_frame *prframe, struct phy_stat *pphy_stat) ++{ ++ PHY_STS_OFDM_8192CD_T *pOfdm_buf; ++ PHY_STS_CCK_8192CD_T *pCck_buf; ++ u8 i, max_spatial_stream, evm; ++ s8 rx_pwr[4], rx_pwr_all = 0; ++ u8 pwdb_all; ++ u32 rssi,total_rssi=0; ++ u8 bcck_rate=0, rf_rx_num = 0, cck_highpwr = 0; ++ _adapter *padapter = prframe->u.hdr.adapter; ++ struct rx_pkt_attrib *pattrib = &prframe->u.hdr.attrib; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); ++ struct dm_priv *pdmpriv = &pHalData->dmpriv; ++ u8 tmp_rxsnr; ++ s8 rx_snrX; ++ ++#ifdef CONFIG_HW_ANTENNA_DIVERSITY ++ PHY_RX_DRIVER_INFO_8192CD *pDrvInfo = ((PHY_RX_DRIVER_INFO_8192CD *)pphy_stat); ++ u8 bant1_sel = (pDrvInfo->ANTSEL == 1)?_TRUE:_FALSE; ++#endif ++ ++ // Record it for next packet processing ++ bcck_rate=(pattrib->mcs_rate<=3? 1:0); ++ ++ if(bcck_rate) //CCK ++ { ++ u8 report; ++#ifdef CONFIG_HW_ANTENNA_DIVERSITY ++ if(bant1_sel == _TRUE) ++ pHalData->CCK_Ant1_Cnt++; ++ else ++ pHalData->CCK_Ant2_Cnt++; ++#endif ++ ++ // CCK Driver info Structure is not the same as OFDM packet. ++ pCck_buf = (PHY_STS_CCK_8192CD_T *)pphy_stat; ++ //Adapter->RxStats.NumQryPhyStatusCCK++; ++ ++ // ++ // (1)Hardware does not provide RSSI for CCK ++ // (2)PWDB, Average PWDB cacluated by hardware (for rate adaptive) ++ // ++ ++ if(padapter->pwrctrlpriv.rf_pwrstate == rf_on) ++ cck_highpwr = (u8)pHalData->bCckHighPower; ++ else ++ cck_highpwr = _FALSE; ++ ++ if(!cck_highpwr) ++ { ++ report = pCck_buf->cck_agc_rpt&0xc0; ++ report = report>>6; ++ switch(report) ++ { ++ // 03312009 modified by cosa ++ // Modify the RF RNA gain value to -40, -20, -2, 14 by Jenyu's suggestion ++ // Note: different RF with the different RNA gain. ++ case 0x3: ++ rx_pwr_all = (-46) - (pCck_buf->cck_agc_rpt & 0x3e); ++ break; ++ case 0x2: ++ rx_pwr_all = (-26) - (pCck_buf->cck_agc_rpt & 0x3e); ++ break; ++ case 0x1: ++ rx_pwr_all = (-12) - (pCck_buf->cck_agc_rpt & 0x3e); ++ break; ++ case 0x0: ++ rx_pwr_all = (16) - (pCck_buf->cck_agc_rpt & 0x3e); ++ break; ++ } ++ } ++ else ++ { ++ report = pCck_buf->cck_agc_rpt & 0x60; ++ report = report>>5; ++ switch(report) ++ { ++ case 0x3: ++ rx_pwr_all = (-46) - ((pCck_buf->cck_agc_rpt & 0x1f)<<1) ; ++ break; ++ case 0x2: ++ rx_pwr_all = (-26)- ((pCck_buf->cck_agc_rpt & 0x1f)<<1); ++ break; ++ case 0x1: ++ rx_pwr_all = (-12) - ((pCck_buf->cck_agc_rpt & 0x1f)<<1) ; ++ break; ++ case 0x0: ++ rx_pwr_all = (16) - ((pCck_buf->cck_agc_rpt & 0x1f)<<1) ; ++ break; ++ } ++ } ++ ++ pwdb_all= query_rx_pwr_percentage(rx_pwr_all); ++ if(pHalData->CustomerID == RT_CID_819x_Lenovo) ++ { ++ // CCK gain is smaller than OFDM/MCS gain, ++ // so we add gain diff by experiences, the val is 6 ++ pwdb_all+=6; ++ if(pwdb_all > 100) ++ pwdb_all = 100; ++ // modify the offset to make the same gain index with OFDM. ++ if(pwdb_all > 34 && pwdb_all <= 42) ++ pwdb_all -= 2; ++ else if(pwdb_all > 26 && pwdb_all <= 34) ++ pwdb_all -= 6; ++ else if(pwdb_all > 14 && pwdb_all <= 26) ++ pwdb_all -= 8; ++ else if(pwdb_all > 4 && pwdb_all <= 14) ++ pwdb_all -= 4; ++ } ++ ++ pattrib->RxPWDBAll = pwdb_all; //for DIG/rate adaptive ++ pattrib->RecvSignalPower = rx_pwr_all; //dBM ++ padapter->recvpriv.rxpwdb = rx_pwr_all; ++ // ++ // (3) Get Signal Quality (EVM) ++ // ++ //if(bPacketMatchBSSID) ++ { ++ u8 sq; ++ ++ if(pHalData->CustomerID == RT_CID_819x_Lenovo) ++ { ++ // mapping to 5 bars for vista signal strength ++ // signal quality in driver will be displayed to signal strength ++ // in vista. ++ if(pwdb_all >= 50) ++ sq = 100; ++ else if(pwdb_all >= 35 && pwdb_all < 50) ++ sq = 80; ++ else if(pwdb_all >= 22 && pwdb_all < 35) ++ sq = 60; ++ else if(pwdb_all >= 18 && pwdb_all < 22) ++ sq = 40; ++ else ++ sq = 20; ++ } ++ else ++ { ++ if(pwdb_all> 40) ++ { ++ sq = 100; ++ } ++ else ++ { ++ sq = pCck_buf->SQ_rpt; ++ ++ if(pCck_buf->SQ_rpt > 64) ++ sq = 0; ++ else if (pCck_buf->SQ_rpt < 20) ++ sq= 100; ++ else ++ sq = ((64-sq) * 100) / 44; ++ ++ } ++ } ++ ++ pattrib->signal_qual=sq; ++ pattrib->rx_mimo_signal_qual[0]=sq; ++ pattrib->rx_mimo_signal_qual[1]=(-1); ++ } ++ ++ } ++ else //OFDM/HT ++ { ++#ifdef CONFIG_HW_ANTENNA_DIVERSITY ++ if(bant1_sel == _TRUE) ++ pHalData->OFDM_Ant1_Cnt++; ++ else ++ pHalData->OFDM_Ant2_Cnt++; ++#endif ++ pdmpriv->OFDM_Pkt_Cnt++; ++ ++ pOfdm_buf = (PHY_STS_OFDM_8192CD_T *)pphy_stat; ++ ++ // ++ // (1)Get RSSI per-path ++ // ++ for(i=0; iNumTotalRFPath; i++) ++ { ++ // 2008/01/30 MH we will judge RF RX path now. ++ if (pHalData->bRFPathRxEnable[i]) ++ rf_rx_num++; ++ //else ++ //continue; ++ ++ rx_pwr[i] = ((pOfdm_buf->trsw_gain_X[i]&0x3F)*2) - 110; ++ pattrib->rx_rssi[i]=query_rx_pwr_percentage(rx_pwr[i]); ++ /* Translate DBM to percentage. */ ++ rssi=query_rx_pwr_percentage(rx_pwr[i]); ++ total_rssi += rssi; ++ ++ RT_TRACE(_module_rtl871x_recv_c_, _drv_err_, ("RF-%d RXPWR=%x RSSI=%d\n", i, rx_pwr[i], rssi)); ++ ++ //Get Rx snr value in DB ++ tmp_rxsnr = pOfdm_buf->rxsnr_X[i]; ++ rx_snrX = (s8)(tmp_rxsnr); ++ rx_snrX >>= 1; ++ padapter->recvpriv.RxSNRdB[i] = (int)rx_snrX; ++ pattrib->rx_snr[i]=pOfdm_buf->rxsnr_X[i]; ++ /* Record Signal Strength for next packet */ ++ //if(bPacketMatchBSSID) ++ { ++ //pRfd->Status.RxMIMOSignalStrength[i] =(u1Byte) RSSI; ++ ++ //The following is for lenovo signal strength in vista ++ if(pHalData->CustomerID == RT_CID_819x_Lenovo) ++ { ++ u8 sq; ++ ++ if(i == 0) ++ { ++ // mapping to 5 bars for vista signal strength ++ // signal quality in driver will be displayed to signal strength ++ // in vista. ++ if(rssi >= 50) ++ sq = 100; ++ else if(rssi >= 35 && rssi < 50) ++ sq = 80; ++ else if(rssi >= 22 && rssi < 35) ++ sq = 60; ++ else if(rssi >= 18 && rssi < 22) ++ sq = 40; ++ else ++ sq = 20; ++ //DbgPrint("ofdm/mcs RSSI=%d\n", RSSI); ++ //pRfd->Status.SignalQuality = SQ; ++ //DbgPrint("ofdm/mcs SQ = %d\n", pRfd->Status.SignalQuality); ++ } ++ } ++ } ++ } ++ ++ ++ // ++ // (2)PWDB, Average PWDB cacluated by hardware (for rate adaptive),average ++ // ++ rx_pwr_all = (((pOfdm_buf->pwdb_all ) >> 1 )& 0x7f) -110;//for OFDM Average RSSI ++ pwdb_all = query_rx_pwr_percentage(rx_pwr_all); ++ ++ RT_TRACE(_module_rtl871x_recv_c_, _drv_err_, ("PWDB_ALL=%d\n", pwdb_all)); ++ ++ pattrib->RxPWDBAll = pwdb_all; //for DIG/rate adaptive ++ pattrib->RecvSignalPower = rx_pwr_all;//dBM ++ padapter->recvpriv.rxpwdb = rx_pwr_all; ++ // ++ // (3)EVM of HT rate ++ // ++ if(pHalData->CustomerID != RT_CID_819x_Lenovo) ++ { ++ if(pattrib->rxht && pattrib->mcs_rate >=20 && pattrib->mcs_rate<=27) ++ max_spatial_stream = 2; //both spatial stream make sense ++ else ++ max_spatial_stream = 1; //only spatial stream 1 makes sense ++ ++ for(i=0; i>= 1" because the compilor of free build environment ++ // fill most significant bit to "zero" when doing shifting operation which may change a negative ++ // value to positive one, then the dbm value (which is supposed to be negative) is not correct anymore. ++ evm = evm_db2percentage( (pOfdm_buf->rxevm_X[i]/*/ 2*/));//dbm ++ ++ RT_TRACE(_module_rtl871x_recv_c_, _drv_err_, ("RXRATE=%x RXEVM=%x EVM=%s%d\n", ++ pattrib->mcs_rate, pOfdm_buf->rxevm_X[i], "%",evm)); ++ ++ //if(bPacketMatchBSSID) ++ { ++ if(i==0) // Fill value in RFD, Get the first spatial stream only ++ { ++ pattrib->signal_qual = (u8)(evm & 0xff); ++ } ++ pattrib->rx_mimo_signal_qual[i] = (u8)(evm & 0xff); ++ } ++ } ++ ++ } ++ ++ // ++ // 4. Record rx statistics for debug ++ // ++ ++ } ++ ++ ++ //UI BSS List signal strength(in percentage), make it good looking, from 0~100. ++ //It is assigned to the BSS List in GetValueFromBeaconOrProbeRsp(). ++ if(bcck_rate) ++ { ++ pattrib->signal_strength=(u8)signal_scale_mapping(padapter, pwdb_all); ++ } ++ else ++ { ++ if (rf_rx_num != 0) ++ { ++ pattrib->signal_strength= (u8)(signal_scale_mapping(padapter, total_rssi/=rf_rx_num)); ++ } ++ } ++ //DBG_8192C("%s,rx_pwr_all(%d),RxPWDBAll(%d)\n",__FUNCTION__,rx_pwr_all,pattrib->RxPWDBAll); ++ ++} ++ ++ ++static void process_rssi(_adapter *padapter,union recv_frame *prframe) ++{ ++ u32 last_rssi, tmp_val; ++ struct rx_pkt_attrib *pattrib = &prframe->u.hdr.attrib; ++#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS ++ struct signal_stat * signal_stat = &padapter->recvpriv.signal_strength_data; ++#endif //CONFIG_NEW_SIGNAL_STAT_PROCESS ++ ++ //DBG_8192C("process_rssi=> pattrib->rssil(%d) signal_strength(%d)\n ",pattrib->RecvSignalPower,pattrib->signal_strength); ++ //if(pRfd->Status.bPacketToSelf || pRfd->Status.bPacketBeacon) ++ { ++ ++ #ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS ++ if(signal_stat->update_req) { ++ signal_stat->total_num = 0; ++ signal_stat->total_val = 0; ++ signal_stat->update_req = 0; ++ } ++ ++ signal_stat->total_num++; ++ signal_stat->total_val += pattrib->signal_strength; ++ signal_stat->avg_val = signal_stat->total_val / signal_stat->total_num; ++ #else //CONFIG_NEW_SIGNAL_STAT_PROCESS ++ ++ //Adapter->RxStats.RssiCalculateCnt++; //For antenna Test ++ if(padapter->recvpriv.signal_strength_data.total_num++ >= PHY_RSSI_SLID_WIN_MAX) ++ { ++ padapter->recvpriv.signal_strength_data.total_num = PHY_RSSI_SLID_WIN_MAX; ++ last_rssi = padapter->recvpriv.signal_strength_data.elements[padapter->recvpriv.signal_strength_data.index]; ++ padapter->recvpriv.signal_strength_data.total_val -= last_rssi; ++ } ++ padapter->recvpriv.signal_strength_data.total_val +=pattrib->signal_strength; ++ ++ padapter->recvpriv.signal_strength_data.elements[padapter->recvpriv.signal_strength_data.index++] = pattrib->signal_strength; ++ if(padapter->recvpriv.signal_strength_data.index >= PHY_RSSI_SLID_WIN_MAX) ++ padapter->recvpriv.signal_strength_data.index = 0; ++ ++ ++ tmp_val = padapter->recvpriv.signal_strength_data.total_val/padapter->recvpriv.signal_strength_data.total_num; ++ ++ if(padapter->recvpriv.is_signal_dbg) { ++ padapter->recvpriv.signal_strength= padapter->recvpriv.signal_strength_dbg; ++ padapter->recvpriv.rssi=(s8)translate2dbm((u8)padapter->recvpriv.signal_strength_dbg); ++ } else { ++ padapter->recvpriv.signal_strength= tmp_val; ++ padapter->recvpriv.rssi=(s8)translate2dbm((u8)tmp_val); ++ } ++ ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("UI RSSI = %d, ui_rssi.TotalVal = %d, ui_rssi.TotalNum = %d\n", tmp_val, padapter->recvpriv.signal_strength_data.total_val,padapter->recvpriv.signal_strength_data.total_num)); ++ #endif //CONFIG_NEW_SIGNAL_STAT_PROCESS ++ } ++ ++}// Process_UI_RSSI_8192C ++ ++ ++static void process_PWDB(_adapter *padapter, union recv_frame *prframe) ++{ ++ int UndecoratedSmoothedPWDB; ++ int UndecoratedSmoothedCCK; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); ++ struct dm_priv *pdmpriv = &pHalData->dmpriv; ++ struct rx_pkt_attrib *pattrib= &prframe->u.hdr.attrib; ++ struct sta_info *psta = prframe->u.hdr.psta; ++ u8 isCCKrate=(pattrib->mcs_rate<=3? 1:0); ++ ++ ++ if(psta) ++ { ++ UndecoratedSmoothedPWDB = psta->rssi_stat.UndecoratedSmoothedPWDB; ++ UndecoratedSmoothedCCK = psta->rssi_stat.UndecoratedSmoothedCCK; ++ } ++ else ++ { ++ UndecoratedSmoothedPWDB = pdmpriv->UndecoratedSmoothedPWDB; ++ UndecoratedSmoothedCCK = pdmpriv->UndecoratedSmoothedCCK; ++ } ++ ++ //if(pRfd->Status.bPacketToSelf || pRfd->Status.bPacketBeacon) ++ ++ if(!isCCKrate) ++ { ++ // Process OFDM RSSI ++ if(UndecoratedSmoothedPWDB < 0) // initialize ++ { ++ UndecoratedSmoothedPWDB = pattrib->RxPWDBAll; ++ } ++ ++ if(pattrib->RxPWDBAll > (u32)UndecoratedSmoothedPWDB) ++ { ++ UndecoratedSmoothedPWDB = ++ ( ((UndecoratedSmoothedPWDB)*(Rx_Smooth_Factor-1)) + ++ (pattrib->RxPWDBAll)) /(Rx_Smooth_Factor); ++ ++ UndecoratedSmoothedPWDB = UndecoratedSmoothedPWDB + 1; ++ } ++ else ++ { ++ UndecoratedSmoothedPWDB = ++ ( ((UndecoratedSmoothedPWDB)*(Rx_Smooth_Factor-1)) + ++ (pattrib->RxPWDBAll)) /(Rx_Smooth_Factor); ++ } ++ } ++ else ++ { ++ // Process CCK RSSI ++ if(UndecoratedSmoothedCCK < 0) // initialize ++ { ++ UndecoratedSmoothedCCK = pattrib->RxPWDBAll; ++ } ++ ++ if(pattrib->RxPWDBAll > (u32)UndecoratedSmoothedCCK) ++ { ++ UndecoratedSmoothedCCK = ++ ( ((UndecoratedSmoothedCCK)*(Rx_Smooth_Factor-1)) + ++ (pattrib->RxPWDBAll)) /(Rx_Smooth_Factor); ++ ++ UndecoratedSmoothedCCK = UndecoratedSmoothedCCK + 1; ++ } ++ else ++ { ++ UndecoratedSmoothedCCK = ++ ( ((UndecoratedSmoothedCCK)*(Rx_Smooth_Factor-1)) + ++ (pattrib->RxPWDBAll)) /(Rx_Smooth_Factor); ++ } ++ } ++ ++ ++ if(psta) ++ { ++ //psta->UndecoratedSmoothedPWDB = UndecoratedSmoothedPWDB;//todo: ++ pdmpriv->UndecoratedSmoothedPWDB = UndecoratedSmoothedPWDB; ++ ++ if(pdmpriv->RSSI_Select == RSSI_OFDM){ ++ psta->rssi_stat.UndecoratedSmoothedPWDB = UndecoratedSmoothedPWDB; ++ } ++ else if(pdmpriv->RSSI_Select == RSSI_CCK){ ++ psta->rssi_stat.UndecoratedSmoothedPWDB = UndecoratedSmoothedCCK; ++ } ++ else{ ++ if(UndecoratedSmoothedPWDB <0 ) ++ pdmpriv->UndecoratedSmoothedPWDB = UndecoratedSmoothedCCK; ++ else ++ pdmpriv->UndecoratedSmoothedPWDB = UndecoratedSmoothedPWDB; ++ } ++ psta->rssi_stat.UndecoratedSmoothedCCK = UndecoratedSmoothedCCK; ++ } ++ else ++ { ++ //pdmpriv->UndecoratedSmoothedPWDB = UndecoratedSmoothedPWDB; ++ ++ if(pdmpriv->RSSI_Select == RSSI_OFDM){ ++ pdmpriv->UndecoratedSmoothedPWDB = UndecoratedSmoothedPWDB; ++ } ++ else if(pdmpriv->RSSI_Select == RSSI_CCK){ ++ pdmpriv->UndecoratedSmoothedPWDB = UndecoratedSmoothedCCK; ++ } ++ else { ++ if(UndecoratedSmoothedPWDB <0 ) ++ pdmpriv->UndecoratedSmoothedPWDB = UndecoratedSmoothedCCK; ++ else ++ pdmpriv->UndecoratedSmoothedPWDB = UndecoratedSmoothedPWDB; ++ ++ } ++ pdmpriv->UndecoratedSmoothedCCK = UndecoratedSmoothedCCK; ++ } ++ ++ //UpdateRxSignalStatistics8192C(padapter, prframe); ++ ++} ++ ++ ++static void process_link_qual(_adapter *padapter,union recv_frame *prframe) ++{ ++ u32 last_evm=0, tmpVal; ++ struct rx_pkt_attrib *pattrib; ++#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS ++ struct signal_stat * signal_stat; ++#endif //CONFIG_NEW_SIGNAL_STAT_PROCESS ++ ++ if(prframe == NULL || padapter==NULL){ ++ return; ++ } ++ ++ pattrib = &prframe->u.hdr.attrib; ++#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS ++ signal_stat = &padapter->recvpriv.signal_qual_data; ++#endif //CONFIG_NEW_SIGNAL_STAT_PROCESS ++ ++ //DBG_8192C("process_link_qual=> pattrib->signal_qual(%d)\n ",pattrib->signal_qual); ++ ++#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS ++ if(signal_stat->update_req) { ++ signal_stat->total_num = 0; ++ signal_stat->total_val = 0; ++ signal_stat->update_req = 0; ++ } ++ ++ signal_stat->total_num++; ++ signal_stat->total_val += pattrib->signal_qual; ++ signal_stat->avg_val = signal_stat->total_val / signal_stat->total_num; ++ ++#else //CONFIG_NEW_SIGNAL_STAT_PROCESS ++ if(pattrib->signal_qual != 0) ++ { ++ // ++ // 1. Record the general EVM to the sliding window. ++ // ++ if(padapter->recvpriv.signal_qual_data.total_num++ >= PHY_LINKQUALITY_SLID_WIN_MAX) ++ { ++ padapter->recvpriv.signal_qual_data.total_num = PHY_LINKQUALITY_SLID_WIN_MAX; ++ last_evm = padapter->recvpriv.signal_qual_data.elements[padapter->recvpriv.signal_qual_data.index]; ++ padapter->recvpriv.signal_qual_data.total_val -= last_evm; ++ } ++ padapter->recvpriv.signal_qual_data.total_val += pattrib->signal_qual; ++ ++ padapter->recvpriv.signal_qual_data.elements[padapter->recvpriv.signal_qual_data.index++] = pattrib->signal_qual; ++ if(padapter->recvpriv.signal_qual_data.index >= PHY_LINKQUALITY_SLID_WIN_MAX) ++ padapter->recvpriv.signal_qual_data.index = 0; ++ ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("Total SQ=%d pattrib->signal_qual= %d\n", padapter->recvpriv.signal_qual_data.total_val, pattrib->signal_qual)); ++ ++ // <1> Showed on UI for user, in percentage. ++ tmpVal = padapter->recvpriv.signal_qual_data.total_val/padapter->recvpriv.signal_qual_data.total_num; ++ padapter->recvpriv.signal_qual=(u8)tmpVal; ++ ++ } ++ else ++ { ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,(" pattrib->signal_qual =%d\n", pattrib->signal_qual)); ++ } ++#endif //CONFIG_NEW_SIGNAL_STAT_PROCESS ++ ++}// Process_UiLinkQuality8192S ++ ++ ++//void rtl8192c_process_phy_info(_adapter *padapter, union recv_frame *prframe) ++void rtl8192c_process_phy_info(_adapter *padapter, void *prframe) ++{ ++ union recv_frame *precvframe = (union recv_frame *)prframe; ++ ++#ifdef CONFIG_SW_ANTENNA_DIVERSITY ++ // If we switch to the antenna for testing, the signal strength ++ // of the packets in this time shall not be counted into total receiving power. ++ // This prevents error counting Rx signal strength and affecting other dynamic mechanism. ++ ++ // Select the packets to do RSSI checking for antenna switching. ++ SwAntDivRSSICheck8192C(padapter, precvframe->u.hdr.attrib.RxPWDBAll); ++ ++ if(GET_HAL_DATA(padapter)->RSSI_test == _TRUE) ++ return; ++#endif ++ // ++ // Check RSSI ++ // ++ process_rssi(padapter, precvframe); ++ // ++ // Check PWDB. ++ // ++ process_PWDB(padapter, precvframe); ++ // ++ // Check EVM ++ // ++ process_link_qual(padapter, precvframe); ++ ++} ++ ++ +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/hal/rtl8192c/rtl8192c_sreset.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/hal/rtl8192c/rtl8192c_sreset.c 2013-07-26 19:36:05.000000000 +0000 +@@ -0,0 +1,293 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ++******************************************************************************/ ++#include ++#include ++#ifdef DBG_CONFIG_ERROR_DETECT ++extern void rtw_cancel_all_timer(_adapter *padapter); ++ ++void rtl8192c_sreset_init_value(_adapter *padapter) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); ++ struct sreset_priv *psrtpriv = &pHalData->srestpriv; ++ ++ _rtw_mutex_init(&psrtpriv->silentreset_mutex ); ++ psrtpriv->silent_reset_inprogress = _FALSE; ++ psrtpriv->Wifi_Error_Status = WIFI_STATUS_SUCCESS; ++ psrtpriv->last_tx_time =0; ++ psrtpriv->last_tx_complete_time =0; ++} ++void rtl8192c_sreset_reset_value(_adapter *padapter) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); ++ struct sreset_priv *psrtpriv = &pHalData->srestpriv; ++ psrtpriv->silent_reset_inprogress = _FALSE; ++ psrtpriv->Wifi_Error_Status = WIFI_STATUS_SUCCESS; ++ psrtpriv->last_tx_time =0; ++ psrtpriv->last_tx_complete_time =0; ++} ++ ++static void _restore_security_setting(_adapter *padapter) ++{ ++ u8 EntryId = 0; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct sta_priv * pstapriv = &padapter->stapriv; ++ struct sta_info *psta; ++ struct security_priv* psecuritypriv=&(padapter->securitypriv); ++ struct mlme_ext_info *pmlmeinfo = &padapter->mlmeextpriv.mlmext_info; ++ ++ (pmlmeinfo->auth_algo == dot11AuthAlgrthm_8021X) ++ ? rtw_write8(padapter, REG_SECCFG, 0xcc) ++ : rtw_write8(padapter, REG_SECCFG, 0xcf); ++ ++ if ( ( padapter->securitypriv.dot11PrivacyAlgrthm == _WEP40_ ) || ++ ( padapter->securitypriv.dot11PrivacyAlgrthm == _WEP104_ )) ++ { ++ ++ for(EntryId=0; EntryId<4; EntryId++) ++ { ++ if(EntryId == psecuritypriv->dot11PrivacyKeyIndex) ++ rtw_set_key(padapter,&padapter->securitypriv, EntryId, 1); ++ else ++ rtw_set_key(padapter,&padapter->securitypriv, EntryId, 0); ++ } ++ ++ } ++ else if((padapter->securitypriv.dot11PrivacyAlgrthm == _TKIP_) || ++ (padapter->securitypriv.dot11PrivacyAlgrthm == _AES_)) ++ { ++ psta = rtw_get_stainfo(pstapriv, get_bssid(pmlmepriv)); ++ if (psta == NULL) { ++ //DEBUG_ERR( ("Set wpa_set_encryption: Obtain Sta_info fail \n")); ++ } ++ else ++ { ++ //pairwise key ++ rtw_setstakey_cmd(padapter, (unsigned char *)psta, _TRUE); ++ //group key ++ rtw_set_key(padapter,&padapter->securitypriv,padapter->securitypriv.dot118021XGrpKeyid, 0); ++ } ++ } ++ ++} ++ ++static void _restore_network_status(_adapter *padapter) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ WLAN_BSSID_EX *pnetwork = (WLAN_BSSID_EX*)(&(pmlmeinfo->network)); ++ unsigned short caps; ++ u8 join_type; ++#if 1 ++ ++ //======================================================= ++ // reset related register of Beacon control ++ ++ //set MSR to nolink ++ Set_NETYPE0_MSR(padapter, _HW_STATE_NOLINK_); ++ // reject all data frame ++ rtw_write16(padapter, REG_RXFLTMAP2,0x00); ++ //reset TSF ++ rtw_write8(padapter, REG_DUAL_TSF_RST, (BIT(0)|BIT(1))); ++ ++ //disable update TSF ++ if(IS_NORMAL_CHIP(pHalData->VersionID)) ++ rtw_write8(padapter, REG_BCN_CTRL, rtw_read8(padapter, REG_BCN_CTRL)|BIT(4)); ++ else ++ rtw_write8(padapter, REG_BCN_CTRL, rtw_read8(padapter, REG_BCN_CTRL)|BIT(4)|BIT(5)); ++ ++ //======================================================= ++ rtw_joinbss_reset(padapter); ++ set_channel_bwmode(padapter, pmlmeext->cur_channel, pmlmeext->cur_ch_offset, pmlmeext->cur_bwmode); ++ //pmlmeinfo->assoc_AP_vendor = maxAP; ++ ++ if (padapter->registrypriv.wifi_spec) { ++ // for WiFi test, follow WMM test plan spec ++ rtw_write32(padapter, REG_EDCA_VO_PARAM, 0x002F431C); ++ rtw_write32(padapter, REG_EDCA_VI_PARAM, 0x005E541C); ++ rtw_write32(padapter, REG_EDCA_BE_PARAM, 0x0000A525); ++ rtw_write32(padapter, REG_EDCA_BK_PARAM, 0x0000A549); ++ ++ // for WiFi test, mixed mode with intel STA under bg mode throughput issue ++ if (padapter->mlmepriv.htpriv.ht_option == 0) ++ rtw_write32(padapter, REG_EDCA_BE_PARAM, 0x00004320); ++ ++ } else { ++ rtw_write32(padapter, REG_EDCA_VO_PARAM, 0x002F3217); ++ rtw_write32(padapter, REG_EDCA_VI_PARAM, 0x005E4317); ++ rtw_write32(padapter, REG_EDCA_BE_PARAM, 0x00105320); ++ rtw_write32(padapter, REG_EDCA_BK_PARAM, 0x0000A444); ++ } ++ ++ //disable dynamic functions, such as high power, DIG ++ //Switch_DM_Func(padapter, DYNAMIC_FUNC_DISABLE, _FALSE); ++#endif ++ ++ padapter->HalFunc.SetHwRegHandler(padapter, HW_VAR_BSSID, pmlmeinfo->network.MacAddress); ++ join_type = 0; ++ padapter->HalFunc.SetHwRegHandler(padapter, HW_VAR_MLME_JOIN, (u8 *)(&join_type)); ++ ++ Set_NETYPE0_MSR(padapter, (pmlmeinfo->state & 0x3)); ++ ++ mlmeext_joinbss_event_callback(padapter, 1); ++ //restore Sequence No. ++ rtw_write8(padapter,0x4dc,padapter->xmitpriv.nqos_ssn); ++} ++void rtl8192c_silentreset_for_specific_platform(_adapter *padapter) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); ++ struct sreset_priv *psrtpriv = &pHalData->srestpriv; ++ ++ struct pwrctrl_priv *pwrpriv = &padapter->pwrctrlpriv; ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ struct xmit_priv *pxmitpriv = &padapter->xmitpriv; ++ _irqL irqL; ++ ++#ifdef DBG_CONFIG_ERROR_RESET ++ ++ DBG_871X("%s\n", __FUNCTION__); ++ ++ psrtpriv->Wifi_Error_Status = WIFI_STATUS_SUCCESS; ++ ++ if (!netif_queue_stopped(padapter->pnetdev)) ++ netif_stop_queue(padapter->pnetdev); ++ ++ rtw_cancel_all_timer(padapter); ++ tasklet_kill(&pxmitpriv->xmit_tasklet); ++ ++ _enter_critical_mutex(&psrtpriv->silentreset_mutex, &irqL); ++ psrtpriv->silent_reset_inprogress = _TRUE; ++ pwrpriv->change_rfpwrstate = rf_off; ++#ifdef CONFIG_IPS ++ ips_enter(padapter); ++ ips_leave(padapter); ++#endif ++ if(check_fwstate(pmlmepriv, _FW_LINKED)== _TRUE) ++ { ++ _restore_network_status(padapter); ++ _restore_security_setting(padapter); ++ } ++ ++ _clr_fwstate_(pmlmepriv, _FW_UNDER_SURVEY | _FW_UNDER_LINKING); ++ ++ psrtpriv->silent_reset_inprogress = _FALSE; ++ _exit_critical_mutex(&psrtpriv->silentreset_mutex, &irqL); ++ ++ tasklet_hi_schedule(&pxmitpriv->xmit_tasklet); ++ _set_timer(&padapter->mlmepriv.dynamic_chk_timer, 2000); ++ ++ if (netif_queue_stopped(padapter->pnetdev)) ++ netif_wake_queue(padapter->pnetdev); ++#endif ++} ++ ++void rtl8192c_sreset_xmit_status_check(_adapter *padapter) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); ++ struct sreset_priv *psrtpriv = &pHalData->srestpriv; ++ ++ unsigned long current_time; ++ struct xmit_priv *pxmitpriv = &padapter->xmitpriv; ++ unsigned int diff_time; ++ u32 txdma_status; ++ if( (txdma_status=rtw_read32(padapter, REG_TXDMA_STATUS)) !=0x00){ ++ DBG_871X("%s REG_TXDMA_STATUS:0x%08x\n", __FUNCTION__, txdma_status); ++ rtl8192c_silentreset_for_specific_platform(padapter); ++ } ++ ++ //total xmit irp = 4 ++ //DBG_8192C("==>%s free_xmitbuf_cnt(%d),txirp_cnt(%d)\n",__FUNCTION__,pxmitpriv->free_xmitbuf_cnt,pxmitpriv->txirp_cnt); ++ //if(pxmitpriv->txirp_cnt == NR_XMITBUFF+1) ++ current_time = rtw_get_current_time(); ++ if(0==pxmitpriv->free_xmitbuf_cnt) ++ { ++ diff_time = jiffies_to_msecs(current_time - psrtpriv->last_tx_time); ++ ++ if(diff_time > 2000){ ++ if(psrtpriv->last_tx_complete_time==0){ ++ psrtpriv->last_tx_complete_time = current_time; ++ } ++ else{ ++ diff_time = jiffies_to_msecs(current_time - psrtpriv->last_tx_complete_time); ++ if(diff_time > 4000){ ++ //padapter->Wifi_Error_Status = WIFI_TX_HANG; ++ DBG_8192C("%s tx hang\n", __FUNCTION__); ++ rtl8192c_silentreset_for_specific_platform(padapter); ++ } ++ } ++ } ++ } ++} ++void rtl8192c_sreset_linked_status_check(_adapter *padapter) ++{ ++ u32 regc50,regc58,reg824,reg800; ++ regc50 = rtw_read32(padapter,0xc50); ++ regc58 = rtw_read32(padapter,0xc58); ++ reg824 = rtw_read32(padapter,0x824); ++ reg800 = rtw_read32(padapter,0x800); ++ if( ((regc50&0xFFFFFF00)!= 0x69543400)|| ++ ((regc58&0xFFFFFF00)!= 0x69543400)|| ++ (((reg824&0xFFFFFF00)!= 0x00390000)&&(((reg824&0xFFFFFF00)!= 0x80390000)))|| ++ ( ((reg800&0xFFFFFF00)!= 0x03040000)&&((reg800&0xFFFFFF00)!= 0x83040000))) ++ { ++ DBG_8192C("%s regc50:0x%08x, regc58:0x%08x, reg824:0x%08x, reg800:0x%08x,\n", __FUNCTION__, ++ regc50, regc58, reg824, reg800); ++ rtl8192c_silentreset_for_specific_platform(padapter); ++ } ++} ++ ++#ifdef DBG_CONFIG_ERROR_DETECT ++u8 rtl8192c_sreset_get_wifi_status(_adapter *padapter) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); ++ struct sreset_priv *psrtpriv = &pHalData->srestpriv; ++ ++ u8 status = WIFI_STATUS_SUCCESS; ++ u32 val32 = 0; ++ _irqL irqL; ++ if(psrtpriv->silent_reset_inprogress == _TRUE) ++ { ++ return status; ++ } ++ val32 =rtw_read32(padapter,REG_TXDMA_STATUS); ++ if(val32==0xeaeaeaea){ ++ psrtpriv->Wifi_Error_Status = WIFI_IF_NOT_EXIST; ++ } ++ else if(val32!=0){ ++ DBG_8192C("txdmastatu(%x)\n",val32); ++ psrtpriv->Wifi_Error_Status = WIFI_MAC_TXDMA_ERROR; ++ } ++ ++ if(WIFI_STATUS_SUCCESS !=psrtpriv->Wifi_Error_Status) ++ { ++ DBG_8192C("==>%s error_status(0x%x) \n",__FUNCTION__,psrtpriv->Wifi_Error_Status); ++ status = (psrtpriv->Wifi_Error_Status &( ~(USB_READ_PORT_FAIL|USB_WRITE_PORT_FAIL))); ++ } ++ DBG_8192C("==> %s wifi_status(0x%x)\n",__FUNCTION__,status); ++ ++ //status restore ++ psrtpriv->Wifi_Error_Status = WIFI_STATUS_SUCCESS; ++ ++ return status; ++} ++#endif ++ ++#endif +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/hal/rtl8192c/usb/Hal8192CUHWImg.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/hal/rtl8192c/usb/Hal8192CUHWImg.c 2013-07-26 19:36:05.000000000 +0000 +@@ -0,0 +1,9662 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++ ++/*Created on 2011/ 6/15, 5:45*/ ++ ++#include ++#include "Hal8192CUHWImg.h" ++ ++#ifdef CONFIG_BT_COEXISTENCE ++// =================== v79 TSMC COMMON 2011-10-06 ======================= ++u8 Rtl8192CUFwTSMCImgArray[TSMCImgArrayLength] = { ++0xc1,0x88,0x02,0x00,0x4f,0x00,0x00,0x00,0x0a,0x06,0x18,0x02,0x58,0x3f,0x00,0x00, ++0x61,0x80,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x02,0x43,0xba,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x02,0x5a,0x45,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x02,0x5f,0xfb,0x00,0x00,0x00,0x00,0x00,0xa1,0xdf,0x00,0x00,0x00, ++0x05,0x04,0x03,0x02,0x00,0x03,0x06,0x05,0x04,0x03,0x00,0x04,0x06,0x05,0x04,0x02, ++0x00,0x04,0x08,0x07,0x06,0x04,0x00,0x06,0x0a,0x09,0x08,0x06,0x00,0x08,0x0a,0x09, ++0x08,0x04,0x00,0x08,0x0a,0x09,0x08,0x02,0x00,0x08,0x0a,0x09,0x08,0x00,0x00,0x08, ++0x12,0x11,0x10,0x08,0x00,0x10,0x1a,0x19,0x18,0x10,0x00,0x18,0x22,0x21,0x20,0x18, ++0x00,0x20,0x22,0x21,0x20,0x10,0x00,0x20,0x22,0x21,0x20,0x08,0x00,0x20,0x22,0x21, ++0x1c,0x08,0x00,0x20,0x22,0x21,0x14,0x08,0x00,0x20,0x22,0x20,0x18,0x08,0x00,0x20, ++0x31,0x30,0x20,0x10,0x00,0x30,0x31,0x30,0x18,0x00,0x00,0x30,0x31,0x2f,0x10,0x10, ++0x00,0x30,0x31,0x2c,0x10,0x10,0x00,0x30,0x31,0x28,0x10,0x00,0x00,0x30,0x31,0x20, ++0x10,0x00,0x00,0x30,0x31,0x10,0x10,0x00,0x00,0x30,0x04,0x04,0x04,0x05,0x04,0x04, ++0x04,0x05,0x05,0x05,0x06,0x06,0x04,0x04,0x04,0x05,0x05,0x05,0x06,0x06,0x04,0x04, ++0x05,0x05,0x05,0x05,0x06,0x06,0x04,0x04,0x05,0x05,0x05,0x05,0x06,0x07,0x0a,0x0b, ++0x0d,0x10,0x04,0x05,0x05,0x06,0x06,0x09,0x0c,0x11,0x08,0x08,0x09,0x09,0x0a,0x0c, ++0x10,0x11,0x04,0x04,0x04,0x05,0x04,0x04,0x05,0x07,0x07,0x07,0x08,0x0a,0x04,0x04, ++0x04,0x04,0x06,0x0a,0x0b,0x0d,0x05,0x05,0x07,0x07,0x08,0x0b,0x0d,0x0f,0x04,0x04, ++0x04,0x05,0x07,0x07,0x09,0x09,0x0c,0x0e,0x10,0x12,0x04,0x04,0x05,0x05,0x06,0x0a, ++0x11,0x13,0x09,0x09,0x09,0x09,0x0c,0x0e,0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x24,0x26,0x2a,0x18,0x1a,0x1d,0x1f,0x21,0x27,0x29,0x2a,0x00,0x00, ++0x00,0x1f,0x23,0x28,0x2a,0x2c,0x00,0x04,0x00,0x04,0x00,0x08,0x00,0x10,0x00,0x18, ++0x00,0x24,0x00,0x30,0x00,0x48,0x00,0x60,0x00,0x90,0x00,0xc0,0x00,0xd8,0x00,0x50, ++0x00,0x78,0x00,0xa0,0x00,0xc8,0x01,0x40,0x01,0x90,0x01,0xe0,0x02,0x30,0x01,0x2c, ++0x01,0x40,0x01,0xe0,0x02,0xd0,0x03,0xe8,0x04,0xb0,0x06,0x40,0x07,0xd0,0x00,0x02, ++0x00,0x02,0x00,0x04,0x00,0x08,0x00,0x0c,0x00,0x12,0x00,0x18,0x00,0x24,0x00,0x30, ++0x00,0x48,0x00,0x60,0x00,0x6c,0x00,0x28,0x00,0x3c,0x00,0x50,0x00,0x64,0x00,0xa0, ++0x00,0xc8,0x00,0xf0,0x01,0x18,0x00,0x64,0x00,0xa0,0x00,0xf0,0x01,0x68,0x01,0xf4, ++0x02,0x58,0x03,0x20,0x03,0xe8,0x02,0x02,0x02,0x02,0x02,0x02,0x03,0x03,0x04,0x04, ++0x05,0x07,0x04,0x04,0x07,0x0a,0x0a,0x0c,0x0c,0x12,0x05,0x07,0x07,0x08,0x0b,0x12, ++0x24,0x3c,0x01,0x01,0x01,0x01,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x01,0x02, ++0x03,0x04,0x05,0x06,0x07,0x08,0x05,0x06,0x07,0x08,0x09,0x0a,0x0b,0x0c,0x20,0x1e, ++0x1c,0x18,0x10,0x18,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0xbb,0x01,0x0c,0xe5,0x82,0x29,0xf5,0x82,0xe5,0x83,0x3a,0xf5,0x83,0xe0,0x22,0x50, ++0x06,0xe9,0x25,0x82,0xf8,0xe6,0x22,0xbb,0xfe,0x06,0xe9,0x25,0x82,0xf8,0xe2,0x22, ++0xe5,0x82,0x29,0xf5,0x82,0xe5,0x83,0x3a,0xf5,0x83,0xe4,0x93,0x22,0xbb,0x01,0x06, ++0x89,0x82,0x8a,0x83,0xf0,0x22,0x50,0x02,0xf7,0x22,0xbb,0xfe,0x01,0xf3,0x22,0xf8, ++0xbb,0x01,0x0d,0xe5,0x82,0x29,0xf5,0x82,0xe5,0x83,0x3a,0xf5,0x83,0xe8,0xf0,0x22, ++0x50,0x06,0xe9,0x25,0x82,0xc8,0xf6,0x22,0xbb,0xfe,0x05,0xe9,0x25,0x82,0xc8,0xf2, ++0x22,0xc5,0xf0,0xf8,0xa3,0xe0,0x28,0xf0,0xc5,0xf0,0xf8,0xe5,0x82,0x15,0x82,0x70, ++0x02,0x15,0x83,0xe0,0x38,0xf0,0x22,0xbb,0x01,0x0a,0x89,0x82,0x8a,0x83,0xe0,0xf5, ++0xf0,0xa3,0xe0,0x22,0x50,0x06,0x87,0xf0,0x09,0xe7,0x19,0x22,0xbb,0xfe,0x07,0xe3, ++0xf5,0xf0,0x09,0xe3,0x19,0x22,0x89,0x82,0x8a,0x83,0xe4,0x93,0xf5,0xf0,0x74,0x01, ++0x93,0x22,0xbb,0x01,0x10,0xe5,0x82,0x29,0xf5,0x82,0xe5,0x83,0x3a,0xf5,0x83,0xe0, ++0xf5,0xf0,0xa3,0xe0,0x22,0x50,0x09,0xe9,0x25,0x82,0xf8,0x86,0xf0,0x08,0xe6,0x22, ++0xbb,0xfe,0x0a,0xe9,0x25,0x82,0xf8,0xe2,0xf5,0xf0,0x08,0xe2,0x22,0xe5,0x83,0x2a, ++0xf5,0x83,0xe9,0x93,0xf5,0xf0,0xa3,0xe9,0x93,0x22,0xbb,0x01,0x0a,0x89,0x82,0x8a, ++0x83,0xf0,0xe5,0xf0,0xa3,0xf0,0x22,0x50,0x06,0xf7,0x09,0xa7,0xf0,0x19,0x22,0xbb, ++0xfe,0x06,0xf3,0xe5,0xf0,0x09,0xf3,0x19,0x22,0xf8,0xbb,0x01,0x11,0xe5,0x82,0x29, ++0xf5,0x82,0xe5,0x83,0x3a,0xf5,0x83,0xe8,0xf0,0xe5,0xf0,0xa3,0xf0,0x22,0x50,0x09, ++0xe9,0x25,0x82,0xc8,0xf6,0x08,0xa6,0xf0,0x22,0xbb,0xfe,0x09,0xe9,0x25,0x82,0xc8, ++0xf2,0xe5,0xf0,0x08,0xf2,0x22,0xef,0x4b,0xff,0xee,0x4a,0xfe,0xed,0x49,0xfd,0xec, ++0x48,0xfc,0x22,0xe0,0xfc,0xa3,0xe0,0xfd,0xa3,0xe0,0xfe,0xa3,0xe0,0xff,0x22,0xa4, ++0x25,0x82,0xf5,0x82,0xe5,0xf0,0x35,0x83,0xf5,0x83,0x22,0xe0,0xfb,0xa3,0xe0,0xfa, ++0xa3,0xe0,0xf9,0x22,0xf8,0xe0,0xfb,0xa3,0xa3,0xe0,0xf9,0x25,0xf0,0xf0,0xe5,0x82, ++0x15,0x82,0x70,0x02,0x15,0x83,0xe0,0xfa,0x38,0xf0,0x22,0xeb,0xf0,0xa3,0xea,0xf0, ++0xa3,0xe9,0xf0,0x22,0xd0,0x83,0xd0,0x82,0xf8,0xe4,0x93,0x70,0x12,0x74,0x01,0x93, ++0x70,0x0d,0xa3,0xa3,0x93,0xf8,0x74,0x01,0x93,0xf5,0x82,0x88,0x83,0xe4,0x73,0x74, ++0x02,0x93,0x68,0x60,0xef,0xa3,0xa3,0xa3,0x80,0xdf,0x02,0x43,0xf8,0x02,0x50,0xa9, ++0xe4,0x93,0xa3,0xf8,0xe4,0x93,0xa3,0x40,0x03,0xf6,0x80,0x01,0xf2,0x08,0xdf,0xf4, ++0x80,0x29,0xe4,0x93,0xa3,0xf8,0x54,0x07,0x24,0x0c,0xc8,0xc3,0x33,0xc4,0x54,0x0f, ++0x44,0x20,0xc8,0x83,0x40,0x04,0xf4,0x56,0x80,0x01,0x46,0xf6,0xdf,0xe4,0x80,0x0b, ++0x01,0x02,0x04,0x08,0x10,0x20,0x40,0x80,0x90,0x44,0x3d,0xe4,0x7e,0x01,0x93,0x60, ++0xbc,0xa3,0xff,0x54,0x3f,0x30,0xe5,0x09,0x54,0x1f,0xfe,0xe4,0x93,0xa3,0x60,0x01, ++0x0e,0xcf,0x54,0xc0,0x25,0xe0,0x60,0xa8,0x40,0xb8,0xe4,0x93,0xa3,0xfa,0xe4,0x93, ++0xa3,0xf8,0xe4,0x93,0xa3,0xc8,0xc5,0x82,0xc8,0xca,0xc5,0x83,0xca,0xf0,0xa3,0xc8, ++0xc5,0x82,0xc8,0xca,0xc5,0x83,0xca,0xdf,0xe9,0xde,0xe7,0x80,0xbe,0x41,0x9e,0x66, ++0x00,0x41,0x9e,0xae,0x00,0x41,0x9e,0x4d,0x80,0x41,0x9e,0x4e,0x80,0x41,0x9e,0xb0, ++0x00,0x00,0xf0,0x90,0x9e,0x57,0xe0,0x90,0x9e,0x8a,0xf0,0xe4,0xfb,0xfd,0x7f,0x54, ++0x7e,0x01,0xd3,0x10,0xaf,0x01,0xc3,0xc0,0xd0,0x90,0x9e,0x88,0xeb,0xf0,0xa3,0xe0, ++0xfb,0xa3,0xe0,0xf5,0x44,0xe4,0xf5,0x45,0x12,0x35,0xab,0xd0,0xd0,0x92,0xaf,0x22, ++0x90,0x01,0x5f,0xe4,0xf0,0x90,0x01,0x3c,0x74,0x08,0xf0,0xe4,0x90,0x9e,0x89,0xf0, ++0x90,0x9e,0x55,0xe0,0x90,0x9e,0x8a,0xf0,0xe4,0xfb,0xfd,0x7f,0x5c,0x7e,0x01,0x91, ++0x62,0x90,0x01,0x5f,0x74,0x05,0xf0,0x90,0x06,0x92,0x74,0x02,0xf0,0x90,0x9e,0x5c, ++0x14,0xf0,0x90,0x9e,0x5e,0xe0,0x54,0x0f,0xc3,0x94,0x0c,0x50,0x02,0xf1,0x16,0x22, ++0x8f,0x82,0x8e,0x83,0xa3,0xa3,0xa3,0xe4,0xf0,0x22,0xe4,0xf5,0x22,0x7f,0x60,0x7e, ++0x01,0x80,0xed,0x90,0x9e,0x60,0xe0,0xff,0x7d,0x01,0xe1,0x1a,0xb1,0xb1,0xbf,0x01, ++0x0f,0x90,0x9e,0x68,0xe0,0xff,0xe4,0xfd,0xf1,0xfe,0x90,0x04,0x1f,0x74,0x20,0xf0, ++0x22,0x90,0x01,0xca,0xe5,0x25,0xf0,0xef,0x60,0x03,0x12,0x4f,0x2a,0x22,0x22,0x22, ++0x22,0x22,0x00,0x02,0x60,0x8d,0x02,0x60,0x94,0xd3,0x10,0xaf,0x01,0xc3,0xc0,0xd0, ++0x8b,0x1b,0x8a,0x1c,0x89,0x1d,0x90,0x9e,0x8b,0x71,0x8b,0xab,0x1e,0xaa,0x1f,0xa9, ++0x20,0x90,0x9e,0x8e,0x71,0x8b,0xaf,0x21,0x15,0x21,0xef,0x60,0x1b,0x90,0x9e,0x8e, ++0xe4,0x75,0xf0,0x01,0x71,0x74,0x12,0x29,0xd9,0xff,0x90,0x9e,0x8b,0xe4,0x75,0xf0, ++0x01,0x71,0x74,0xef,0x51,0x4d,0x80,0xde,0xab,0x1b,0xaa,0x1c,0xa9,0x1d,0xd0,0xd0, ++0x92,0xaf,0x22,0x90,0x06,0xa9,0xe0,0xf5,0x50,0x54,0xc0,0x70,0x0d,0x90,0x9e,0x63, ++0xe0,0x54,0xfe,0xf0,0xe0,0x54,0xfd,0xf0,0x91,0xd3,0xe5,0x50,0x30,0xe6,0x17,0x90, ++0x9e,0x63,0xe0,0x44,0x01,0xf0,0x90,0x9e,0x61,0xe0,0x64,0x02,0x60,0x04,0x91,0xdc, ++0x80,0x0b,0x91,0x80,0x80,0x07,0x90,0x9e,0x63,0xe0,0x54,0xfe,0xf0,0xe5,0x50,0x90, ++0x9e,0x63,0x30,0xe7,0x17,0xe0,0x44,0x02,0xf0,0xe4,0x90,0x9e,0x89,0x91,0x52,0x90, ++0x01,0x57,0x74,0x05,0xf0,0x90,0x9e,0x62,0x74,0x01,0xf0,0x22,0xe0,0x54,0xfd,0xf0, ++0x22,0xd3,0x10,0xaf,0x01,0xc3,0xc0,0xd0,0x90,0x04,0x1d,0xe0,0x60,0x1a,0x90,0x05, ++0x22,0xe0,0x54,0x90,0x60,0x07,0x90,0x01,0xc6,0xe0,0x44,0x40,0xf0,0x90,0x01,0xc7, ++0xe0,0x30,0xe1,0xe4,0x7f,0x00,0x80,0x02,0x7f,0x01,0xd0,0xd0,0x92,0xaf,0x22,0xc0, ++0xe0,0xc0,0xf0,0xc0,0x83,0xc0,0x82,0xc0,0xd0,0x75,0xd0,0x00,0xc0,0x00,0xc0,0x01, ++0xc0,0x02,0xc0,0x03,0xc0,0x04,0xc0,0x05,0xc0,0x06,0xc0,0x07,0x90,0x01,0xc4,0x74, ++0xdf,0xf0,0x74,0x45,0xa3,0xf0,0x53,0x91,0xdf,0x90,0x01,0x3c,0xe0,0x55,0x30,0xf5, ++0x34,0xa3,0xe0,0x55,0x31,0xf5,0x35,0xa3,0xe0,0x55,0x32,0xf5,0x36,0xa3,0xe0,0x55, ++0x33,0xf5,0x37,0xe5,0x34,0x30,0xe0,0x06,0x90,0x01,0x3c,0x74,0x01,0xf0,0xe5,0x34, ++0x30,0xe1,0x08,0x90,0x01,0x3c,0x74,0x02,0xf0,0xf1,0xbc,0xe5,0x34,0x30,0xe2,0x38, ++0x90,0x01,0x3c,0x74,0x04,0xf0,0x90,0x06,0x92,0xe0,0x30,0xe0,0x24,0x90,0x9e,0x89, ++0xe4,0xf0,0x90,0x9e,0x55,0xe0,0x90,0x9e,0x8a,0xf0,0xe4,0xfb,0xfd,0x7f,0x58,0x7e, ++0x01,0x91,0x62,0x90,0x01,0x5b,0x74,0x05,0xf0,0x90,0x06,0x92,0x74,0x01,0xf0,0x80, ++0x07,0x90,0x9e,0x5d,0xe4,0xf0,0x91,0xd3,0xe5,0x34,0x30,0xe3,0x38,0x90,0x01,0x3c, ++0x74,0x08,0xf0,0x90,0x06,0x92,0xe0,0x30,0xe1,0x24,0x90,0x9e,0x89,0xe4,0xf0,0x90, ++0x9e,0x55,0xe0,0x90,0x9e,0x8a,0xf0,0xe4,0xfb,0xfd,0x7f,0x5c,0x7e,0x01,0x91,0x62, ++0x90,0x01,0x5f,0x74,0x05,0xf0,0x90,0x06,0x92,0x74,0x02,0xf0,0x80,0x07,0x90,0x9e, ++0x5c,0xe4,0xf0,0x91,0xd3,0xe5,0x34,0x30,0xe4,0x09,0x90,0x01,0x3c,0x74,0x10,0xf0, ++0x12,0x4d,0xe2,0xe5,0x34,0x30,0xe5,0x09,0x90,0x01,0x3c,0x74,0x20,0xf0,0x12,0x4e, ++0x25,0xe5,0x35,0x30,0xe0,0x1a,0x90,0x01,0x3d,0x74,0x01,0xf0,0x90,0x01,0x2f,0xe0, ++0x44,0x7f,0xf0,0x90,0x00,0x83,0xe0,0x90,0x9e,0x60,0xf0,0x12,0x64,0xa1,0x91,0xd3, ++0x74,0xdf,0x04,0x90,0x01,0xc4,0xf0,0x74,0x45,0xa3,0xf0,0xd0,0x07,0xd0,0x06,0xd0, ++0x05,0xd0,0x04,0xd0,0x03,0xd0,0x02,0xd0,0x01,0xd0,0x00,0xd0,0xd0,0xd0,0x82,0xd0, ++0x83,0xd0,0xf0,0xd0,0xe0,0x32,0x7d,0x01,0x7f,0x0c,0x8f,0x71,0x8d,0x72,0xe5,0x71, ++0x54,0x0f,0xff,0x90,0x9e,0x5e,0xe0,0x54,0x0f,0x6f,0x60,0x72,0xe5,0x71,0x30,0xe2, ++0x2b,0x90,0x9e,0x5e,0xe0,0x20,0xe2,0x05,0x7f,0x01,0x12,0x63,0x92,0x90,0x9e,0x5e, ++0xe0,0x30,0xe3,0x07,0xe5,0x71,0x20,0xe3,0x02,0x80,0x54,0x90,0x9e,0x5e,0xe0,0x20, ++0xe3,0x4c,0xe5,0x71,0x30,0xe3,0x47,0xaf,0x72,0x02,0x63,0x2e,0x90,0x9e,0x5e,0xe0, ++0x54,0x0f,0xff,0xbf,0x0c,0x0d,0xe5,0x71,0x20,0xe3,0x08,0x12,0x5e,0xf1,0xef,0x60, ++0x2d,0xf1,0x9f,0x90,0x9e,0x5e,0xe0,0x54,0x0f,0xff,0xbf,0x04,0x0e,0xe5,0x71,0x20, ++0xe2,0x09,0x12,0x62,0x50,0xef,0x60,0x16,0x12,0x48,0xaa,0x90,0x9e,0x5e,0xe0,0x54, ++0x0f,0xff,0xbf,0x02,0x09,0x12,0x62,0xbb,0xef,0x60,0x03,0x12,0x64,0x87,0x22,0x90, ++0x06,0x04,0xe0,0x44,0x40,0xf0,0xe5,0x73,0xb4,0x01,0x05,0x7f,0x01,0x12,0x63,0x4d, ++0x90,0x9e,0x5e,0xe0,0x54,0xf0,0xf0,0xe0,0x44,0x04,0xf0,0x22,0x90,0x9e,0x62,0xe0, ++0x60,0x0e,0xe4,0xf0,0xa3,0xe0,0x54,0xfd,0xf0,0xe0,0x54,0x07,0x70,0x2b,0x80,0x27, ++0x90,0x9e,0x51,0xe0,0x04,0xf0,0x90,0x9e,0x63,0xe0,0x54,0xef,0xf0,0x90,0x9e,0x56, ++0xe0,0xff,0x90,0x9e,0x51,0xe0,0xd3,0x9f,0x40,0x0d,0xe5,0x73,0xb4,0x01,0x0a,0xa3, ++0xe0,0x70,0x06,0xe0,0x04,0xf0,0x22,0x91,0xd3,0x22,0xe0,0xff,0x7d,0x01,0x90,0x9e, ++0x9c,0xef,0xf0,0xa3,0xed,0xf0,0xe4,0xa3,0xf0,0xa3,0xf0,0xe5,0x74,0x60,0x04,0xe4, ++0xff,0x11,0x8f,0x90,0x9e,0x9c,0xe0,0x30,0xe0,0x09,0x90,0x9e,0x9e,0xe4,0xf0,0xa3, ++0x74,0x80,0xf0,0x90,0x9e,0x9c,0xe0,0xff,0xc3,0x13,0x90,0xfd,0x10,0xf0,0x90,0x04, ++0x25,0xef,0xf0,0x90,0x9e,0x9d,0xe0,0x60,0x1f,0xa3,0xa3,0xe0,0xff,0x24,0x0f,0xf5, ++0x82,0xe4,0x34,0xfc,0xf5,0x83,0xe0,0x44,0x80,0xf0,0x74,0x10,0x2f,0xf5,0x82,0xe4, ++0x34,0xfc,0xf5,0x83,0xe0,0x44,0x80,0xf0,0x90,0x9e,0x9e,0xa3,0xe0,0xff,0xfd,0x24, ++0x08,0xf5,0x82,0xe4,0x34,0xfc,0xf5,0x83,0xe4,0xf0,0x74,0x09,0x2d,0xf5,0x82,0xe4, ++0x34,0xfc,0xf5,0x83,0xe0,0x54,0xf0,0xf0,0x74,0x21,0x2f,0xf5,0x82,0xe4,0x34,0xfc, ++0xf5,0x83,0xe0,0x54,0xf7,0xf0,0x90,0x9e,0x9e,0xe0,0xfe,0xa3,0xe0,0xff,0x22,0xef, ++0x60,0x0b,0x90,0x9e,0x77,0xe0,0xb4,0x01,0x10,0xe4,0xff,0x80,0x09,0x90,0x9e,0x77, ++0xe0,0xb4,0x01,0x05,0x7f,0x01,0x12,0x77,0x66,0x22,0x90,0x01,0x37,0x74,0x02,0xf0, ++0x90,0x05,0x22,0x74,0xff,0xf0,0x12,0x77,0x1c,0xef,0x70,0x06,0x90,0x01,0xc8,0x74, ++0xfd,0xf0,0x7d,0x02,0x7f,0x03,0x12,0x36,0xe6,0xe5,0x74,0x60,0x04,0x7f,0x01,0x11, ++0x8f,0x11,0xdf,0x90,0x9e,0x5e,0xe0,0x54,0xf0,0xf0,0xe0,0x44,0x02,0xf0,0x22,0x7f, ++0x78,0x7e,0x08,0x12,0x27,0xde,0x90,0x9d,0xff,0x12,0x2a,0x7f,0x7f,0x04,0x7e,0x0c, ++0x12,0x27,0xde,0x90,0x9e,0x03,0x12,0x2a,0x7f,0x7f,0x00,0x7e,0x08,0x12,0x27,0xde, ++0x90,0x9e,0x07,0x12,0x2a,0x7f,0x90,0x9e,0x77,0xe0,0x90,0x9d,0xff,0xb4,0x01,0x0d, ++0x12,0x43,0x53,0xef,0x54,0xc7,0xff,0xed,0x54,0xc7,0xfd,0x80,0x07,0x12,0x43,0x53, ++0xef,0x54,0xc7,0xff,0xec,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0x78,0x7e,0x08,0x12, ++0x2f,0xd9,0x90,0x9e,0x03,0x12,0x43,0x53,0xef,0x54,0x0f,0xff,0xec,0x90,0x80,0x85, ++0x12,0x2a,0x7f,0x7f,0x04,0x7e,0x0c,0x12,0x2f,0xd9,0x90,0x9e,0x07,0x12,0x43,0x53, ++0xef,0x44,0x02,0xff,0xec,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0x00,0x7e,0x08,0x12, ++0x2f,0xd9,0x7f,0x70,0x7e,0x0e,0x12,0x27,0xde,0x90,0x9e,0x0b,0x12,0x2a,0x7f,0x90, ++0x80,0x85,0x12,0x2a,0x8b,0x00,0x1b,0x25,0xa0,0x7f,0x70,0x7e,0x0e,0x12,0x2f,0xd9, ++0x90,0x80,0x59,0x12,0x2a,0x8b,0x00,0x00,0x00,0x00,0xe4,0xfd,0xff,0x12,0x34,0x81, ++0x90,0x9e,0x77,0xe0,0xb4,0x01,0x11,0x90,0x80,0x59,0x12,0x2a,0x8b,0x00,0x00,0x00, ++0x00,0xe4,0xfd,0x7f,0x01,0x12,0x34,0x81,0x90,0x00,0x11,0xe0,0x54,0xf6,0xf0,0x80, ++0x08,0xf4,0xff,0x90,0x00,0x43,0xe0,0x5f,0xf0,0xd3,0x10,0xaf,0x01,0xc3,0xc0,0xd0, ++0x7f,0x10,0xdf,0xfe,0xd0,0xd0,0x92,0xaf,0x22,0xd3,0x10,0xaf,0x01,0xc3,0xc0,0xd0, ++0x90,0x9e,0xad,0xed,0xf0,0x90,0x9e,0xac,0xef,0xf0,0xd3,0x94,0x07,0x50,0x63,0xe0, ++0xff,0x74,0x01,0xa8,0x07,0x08,0x80,0x02,0xc3,0x33,0xd8,0xfc,0xf4,0xff,0x90,0x00, ++0x47,0xe0,0x5f,0xf0,0x31,0xb9,0x90,0x9e,0xac,0xe0,0xff,0x74,0x01,0xa8,0x07,0x08, ++0x80,0x02,0xc3,0x33,0xd8,0xfc,0xff,0x90,0x00,0x46,0xe0,0x4f,0xf0,0x31,0xb9,0x90, ++0x9e,0xad,0xe0,0x60,0x16,0x90,0x9e,0xac,0xe0,0xff,0x74,0x01,0xa8,0x07,0x08,0x80, ++0x02,0xc3,0x33,0xd8,0xfc,0xff,0x90,0x00,0x45,0x80,0x66,0x90,0x9e,0xac,0xe0,0xff, ++0x74,0x01,0xa8,0x07,0x08,0x80,0x02,0xc3,0x33,0xd8,0xfc,0xf4,0xff,0x90,0x00,0x45, ++0x80,0x6b,0x90,0x9e,0xac,0xe0,0x24,0xf8,0xf0,0xe0,0xff,0x74,0x01,0xa8,0x07,0x08, ++0x80,0x02,0xc3,0x33,0xd8,0xfc,0xc4,0x54,0xf0,0x31,0xb1,0x90,0x9e,0xac,0xe0,0xff, ++0x74,0x01,0xa8,0x07,0x08,0x80,0x02,0xc3,0x33,0xd8,0xfc,0xff,0x90,0x00,0x43,0xe0, ++0x4f,0xf0,0x31,0xb9,0x90,0x9e,0xad,0xe0,0x60,0x1b,0x90,0x9e,0xac,0xe0,0xff,0x74, ++0x01,0xa8,0x07,0x08,0x80,0x02,0xc3,0x33,0xd8,0xfc,0xc4,0x54,0xf0,0xff,0x90,0x00, ++0x42,0xe0,0x4f,0x80,0x1a,0x90,0x9e,0xac,0xe0,0xff,0x74,0x01,0xa8,0x07,0x08,0x80, ++0x02,0xc3,0x33,0xd8,0xfc,0xc4,0x54,0xf0,0xf4,0xff,0x90,0x00,0x42,0xe0,0x5f,0xf0, ++0x31,0xb9,0xd0,0xd0,0x92,0xaf,0x22,0xf0,0x90,0x00,0x45,0xe0,0x54,0xfe,0xfd,0x7f, ++0x45,0xd3,0x10,0xaf,0x01,0xc3,0xc0,0xd0,0x8f,0x82,0x75,0x83,0x00,0xed,0xf0,0x31, ++0xb9,0xd0,0xd0,0x92,0xaf,0x22,0xef,0x14,0x60,0x30,0x14,0x60,0x66,0x24,0x02,0x60, ++0x02,0x61,0x7d,0x90,0x9e,0x1a,0x74,0x02,0xf0,0x90,0x00,0x48,0xe0,0x44,0x0c,0xfd, ++0x7f,0x48,0x51,0xc1,0x90,0x00,0x47,0xe0,0x44,0x08,0xfd,0x7f,0x47,0x51,0xc1,0x90, ++0x00,0x45,0xe0,0x44,0x10,0xfd,0x7f,0x45,0x80,0x71,0xe4,0x90,0x9e,0x1a,0xf0,0x90, ++0x9e,0x16,0x12,0x43,0x53,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0x80,0x7e,0x08,0x12, ++0x2f,0xd9,0x90,0x00,0x45,0xe0,0x44,0xef,0xfd,0x7f,0x45,0x51,0xc1,0x90,0x00,0x45, ++0xe0,0x54,0xef,0xfd,0x7f,0x45,0x51,0xc1,0x90,0x00,0x46,0xe0,0x44,0x10,0xfd,0x7f, ++0x46,0x80,0x38,0x90,0x9e,0x1a,0x74,0x01,0xf0,0x90,0x9e,0x20,0x12,0x43,0x53,0x90, ++0x80,0x85,0x12,0x2a,0x7f,0x7f,0x80,0x7e,0x08,0x12,0x2f,0xd9,0x90,0x00,0x45,0xe0, ++0x44,0x20,0xfd,0x7f,0x45,0x51,0xc1,0x90,0x00,0x45,0xe0,0x44,0x10,0xfd,0x7f,0x45, ++0x51,0xc1,0x90,0x00,0x46,0xe0,0x44,0x10,0xfd,0x7f,0x46,0x51,0xc1,0x22,0x90,0x00, ++0x02,0x12,0x42,0x20,0x90,0x9e,0x1c,0xf0,0x90,0x00,0x01,0x12,0x42,0x20,0x25,0xe0, ++0x25,0xe0,0x90,0x9e,0x1b,0xf0,0x12,0x29,0xd9,0x25,0xe0,0x25,0xe0,0x90,0x9e,0x1f, ++0xf0,0x90,0x05,0x60,0xe0,0x90,0x9e,0x2a,0xf0,0x90,0x05,0x61,0xe0,0x90,0x9e,0x2b, ++0xf0,0x90,0x05,0x62,0xe0,0x90,0x9e,0x2c,0xf0,0x90,0x05,0x63,0xe0,0x90,0x9e,0x2d, ++0xf0,0xa2,0xaf,0xe4,0x33,0x90,0x9e,0x3f,0xf0,0xc2,0xaf,0x90,0x9e,0x1b,0xe0,0xff, ++0xd1,0xd8,0x90,0x9e,0x3f,0xe0,0x24,0xff,0x92,0xaf,0x90,0x9e,0x1c,0xe0,0x70,0x02, ++0x81,0x84,0x90,0x9e,0x1b,0xe0,0x70,0x02,0x81,0x84,0x90,0x9e,0x1f,0xe0,0x70,0x02, ++0x81,0x84,0xa2,0xaf,0xe4,0x33,0x90,0x9e,0x3f,0xf0,0xc2,0xaf,0x90,0x9e,0x2e,0x74, ++0x01,0xf0,0x90,0x9e,0x3f,0xe0,0x24,0xff,0x92,0xaf,0x51,0xb8,0x90,0x00,0x46,0xe0, ++0x44,0x01,0xfd,0x7f,0x46,0x51,0xc1,0x90,0x9e,0x14,0xe0,0x60,0x15,0x90,0x9e,0x20, ++0x12,0x43,0x53,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0x80,0x7e,0x08,0x12,0x2f,0xd9, ++0x80,0x06,0x90,0x05,0x22,0x74,0x7f,0xf0,0x90,0x00,0x45,0xe0,0x54,0xef,0xfd,0x7f, ++0x45,0x51,0xc1,0x90,0x05,0x87,0xe0,0x64,0x80,0xf0,0x90,0x9e,0x2a,0xe0,0x90,0x05, ++0x84,0xf0,0x90,0x9e,0x2b,0xe0,0x90,0x05,0x85,0xf0,0x90,0x9e,0x2c,0xe0,0x90,0x05, ++0x86,0xf0,0x90,0x9e,0x2d,0xe0,0x90,0x05,0x87,0xf0,0xa2,0xaf,0xe4,0x33,0x90,0x9e, ++0x3f,0xf0,0xc2,0xaf,0x90,0x01,0x3c,0xe0,0x44,0x20,0xf0,0x7d,0x20,0xe4,0xff,0x12, ++0x37,0x00,0x80,0x2b,0x90,0x9e,0x1c,0xe0,0x70,0x2d,0x90,0x9e,0x2e,0x51,0xb7,0x90, ++0x00,0x46,0xe0,0x54,0xfe,0xfd,0x7f,0x46,0x51,0xc1,0x90,0x05,0x22,0xe4,0xf0,0xa2, ++0xaf,0x33,0x90,0x9e,0x3f,0xf0,0xc2,0xaf,0x7d,0x20,0xe4,0xff,0x12,0x36,0x92,0x90, ++0x9e,0x3f,0xe0,0x24,0xff,0x92,0xaf,0x22,0x8b,0x59,0x8a,0x5a,0x89,0x5b,0x90,0x00, ++0x02,0x12,0x42,0x20,0x90,0x9e,0x1d,0xf0,0xe0,0x30,0xe0,0x4b,0x90,0x9e,0x14,0x74, ++0x01,0xf0,0x7f,0x80,0x7e,0x08,0x12,0x27,0xde,0x90,0x9e,0x16,0x12,0x2a,0x7f,0xab, ++0x59,0xaa,0x5a,0xa9,0x5b,0x90,0x00,0x01,0x12,0x42,0x20,0xff,0xe4,0xfc,0xfd,0xfe, ++0x78,0x1a,0x12,0x2a,0x6c,0xa8,0x04,0xa9,0x05,0xaa,0x06,0xab,0x07,0x90,0x9e,0x16, ++0x12,0x43,0x53,0xec,0x54,0x03,0xfc,0x12,0x43,0x46,0x90,0x9e,0x20,0x12,0x2a,0x7f, ++0x90,0x05,0x22,0xe4,0xf0,0x80,0x2d,0xe4,0x90,0x9e,0x14,0xf0,0x7f,0x80,0x7e,0x08, ++0x12,0x27,0xde,0xec,0x54,0x03,0xfc,0xec,0x44,0xc0,0xfc,0x90,0x9e,0x16,0x12,0x2a, ++0x7f,0x90,0x9e,0x16,0x12,0x43,0x53,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0x80,0x7e, ++0x08,0x12,0x2f,0xd9,0x90,0x9e,0x1d,0xe0,0x30,0xe1,0x19,0x7d,0x0c,0x7f,0x47,0x51, ++0xc1,0x90,0x00,0x48,0xe0,0x44,0x0c,0xfd,0x7f,0x48,0x51,0xc1,0x90,0x00,0x46,0xe0, ++0x44,0x10,0x80,0x1c,0x90,0x00,0x47,0xe0,0x54,0xf3,0xfd,0x7f,0x47,0x51,0xc1,0x90, ++0x00,0x48,0xe0,0x54,0xf3,0xfd,0x7f,0x48,0x51,0xc1,0x90,0x00,0x46,0xe0,0x54,0xef, ++0xfd,0x7f,0x46,0x51,0xc1,0xe4,0x90,0x9e,0x1a,0xf0,0x22,0x90,0x01,0x3c,0x74,0xff, ++0xf0,0xa3,0xf0,0xa3,0xf0,0x90,0x01,0x34,0xf0,0xa3,0xf0,0xa3,0xf0,0xa3,0xf0,0xfd, ++0x7f,0x54,0x51,0xc1,0x7d,0xff,0x7f,0x55,0x51,0xc1,0x7d,0xff,0x7f,0x56,0x51,0xc1, ++0x7d,0xff,0x7f,0x57,0x41,0xc1,0x90,0x01,0x30,0xe4,0xf0,0xa3,0xf0,0xa3,0xf0,0xa3, ++0xf0,0x90,0x01,0x38,0xf0,0xa3,0xf0,0xa3,0xf0,0xa3,0xf0,0xfd,0x7f,0x50,0x51,0xc1, ++0xe4,0xfd,0x7f,0x51,0x51,0xc1,0xe4,0xfd,0x7f,0x52,0x51,0xc1,0xe4,0xfd,0x7f,0x53, ++0x41,0xc1,0xe5,0x22,0x64,0x01,0x70,0x3c,0xf1,0xbe,0xbf,0x01,0x05,0x7f,0x01,0x12, ++0x44,0xf1,0x90,0x00,0x46,0xe0,0x44,0x04,0xfd,0x7f,0x46,0x51,0xc1,0x90,0x00,0x44, ++0xe0,0x54,0xfb,0xfd,0x7f,0x44,0x51,0xc1,0x90,0x00,0x46,0xe0,0x54,0xfb,0xfd,0x7f, ++0x46,0x51,0xc1,0x7f,0x02,0xf1,0xea,0x8f,0x26,0x90,0x01,0xc9,0xe5,0x26,0xf0,0xb4, ++0x01,0x02,0xf1,0x2a,0x22,0x90,0x9e,0x1c,0xe0,0x64,0x01,0x60,0x02,0xc1,0xd7,0x90, ++0x00,0x46,0xe0,0x44,0x01,0xfd,0x7f,0x46,0x51,0xc1,0x90,0x9e,0x2e,0xe0,0x70,0x31, ++0x90,0x9e,0x14,0xe0,0x60,0x15,0x90,0x9e,0x20,0x12,0x43,0x53,0x90,0x80,0x85,0x12, ++0x2a,0x7f,0x7f,0x80,0x7e,0x08,0x12,0x2f,0xd9,0x80,0x06,0x90,0x05,0x22,0x74,0x7f, ++0xf0,0x90,0x9e,0x1b,0xe0,0xff,0xd1,0xd8,0x90,0x9e,0x2e,0x74,0x01,0x51,0xb7,0x80, ++0x3f,0x90,0x9e,0x2e,0xe0,0x64,0x01,0x70,0x37,0x90,0x9e,0x1f,0xe0,0xff,0xd1,0xd8, ++0xe4,0x90,0x9e,0x2e,0xf0,0x90,0x00,0x45,0xe0,0x44,0x01,0xfd,0x7f,0x45,0x51,0xc1, ++0x90,0x9e,0x14,0xe0,0x60,0x15,0x90,0x9e,0x16,0x12,0x43,0x53,0x90,0x80,0x85,0x12, ++0x2a,0x7f,0x7f,0x80,0x7e,0x08,0x12,0x2f,0xd9,0x80,0x05,0x90,0x05,0x22,0xe4,0xf0, ++0x90,0x05,0x87,0xe0,0x64,0x80,0xf0,0x90,0x9e,0x2a,0xe0,0x90,0x05,0x84,0xf0,0x90, ++0x9e,0x2b,0xe0,0x90,0x05,0x85,0xf0,0x90,0x9e,0x2c,0xe0,0x90,0x05,0x86,0xf0,0x90, ++0x9e,0x2d,0xe0,0x90,0x05,0x87,0xf0,0x22,0x90,0x05,0x60,0xe0,0x90,0x9e,0x2a,0xf0, ++0x90,0x05,0x61,0xe0,0x90,0x9e,0x2b,0xf0,0x90,0x05,0x62,0xe0,0x90,0x9e,0x2c,0xf0, ++0x90,0x05,0x63,0xe0,0x90,0x9e,0x2d,0xf0,0xc3,0x74,0xff,0x9f,0xfe,0x90,0x9e,0x2b, ++0xe0,0xd3,0x9e,0x40,0x1e,0xe0,0x2f,0xf0,0xa3,0xe0,0xb4,0xff,0x0f,0xe4,0xf0,0xa3, ++0xe0,0xb4,0xff,0x03,0xe4,0xf0,0x22,0x90,0x9e,0x2d,0x80,0x03,0x90,0x9e,0x2c,0xe0, ++0x04,0xf0,0x22,0x90,0x9e,0x2b,0xe0,0x2f,0xf0,0x22,0x90,0x00,0x49,0xe0,0x90,0x9e, ++0xb1,0xf0,0xe0,0x54,0x0f,0xf0,0x44,0xf0,0xfd,0x7f,0x49,0x51,0xc1,0x90,0x9e,0xb1, ++0xe0,0x44,0xb0,0xfd,0x7f,0x49,0x41,0xc1,0x8e,0x59,0x8f,0x5a,0x8b,0x5b,0x8a,0x5c, ++0x89,0x5d,0xe4,0x90,0x9e,0x34,0xf0,0xef,0x90,0x00,0x31,0xf0,0x31,0xb9,0xe5,0x59, ++0x54,0x03,0xff,0x90,0x00,0x32,0xe0,0x54,0xfc,0x4f,0xf0,0x31,0xb9,0x90,0x00,0x33, ++0xe0,0x54,0x7f,0xf0,0x31,0xb9,0x90,0x00,0x33,0xe0,0x20,0xe7,0x0e,0x90,0x9e,0x34, ++0xe0,0xc3,0x94,0x64,0x50,0x05,0xe0,0x04,0xf0,0x80,0xeb,0x90,0x9e,0x34,0xe0,0xc3, ++0x94,0x64,0x50,0x10,0x90,0x00,0x30,0xe0,0xab,0x5b,0xaa,0x5c,0xa9,0x5d,0x12,0x42, ++0x4d,0x7f,0x01,0x22,0x7f,0x00,0x22,0x12,0x45,0xb1,0xbf,0x01,0x10,0x90,0x02,0x09, ++0xe0,0xff,0x7d,0x01,0x12,0x47,0xfe,0x90,0x04,0x1f,0x74,0x20,0xf0,0x22,0x7f,0x0b, ++0xf1,0xea,0xef,0x65,0x25,0x60,0x10,0xe5,0x25,0xb4,0x01,0x05,0xe4,0xf5,0x25,0x80, ++0x03,0x75,0x25,0x01,0x7f,0x01,0x22,0x7f,0x00,0x22,0xe4,0x90,0x9e,0x74,0xf0,0x90, ++0x00,0x80,0xe0,0x44,0x80,0xfd,0x7f,0x80,0x41,0xc1,0xd3,0x10,0xaf,0x01,0xc3,0xc0, ++0xd0,0x90,0x9e,0xb2,0xef,0xf0,0xd3,0x94,0x07,0x50,0x47,0xe0,0xff,0x74,0x01,0xa8, ++0x07,0x08,0x80,0x02,0xc3,0x33,0xd8,0xfc,0xf4,0xff,0x90,0x00,0x46,0xe0,0x5f,0xf0, ++0x12,0x49,0xb9,0x90,0x9e,0xb2,0xe0,0xfd,0x74,0x01,0x7e,0x00,0xa8,0x05,0x08,0x80, ++0x05,0xc3,0x33,0xce,0x33,0xce,0xd8,0xf9,0xff,0x90,0x00,0x44,0xe0,0xfb,0xe4,0xfe, ++0xef,0x5b,0xa8,0x05,0x08,0x80,0x06,0xce,0xa2,0xe7,0x13,0xce,0x13,0xd8,0xf8,0xff, ++0x80,0x44,0x90,0x9e,0xb2,0xe0,0x24,0xf8,0xf0,0xe0,0xff,0x74,0x01,0xa8,0x07,0x08, ++0x80,0x02,0xc3,0x33,0xd8,0xfc,0x12,0x49,0xb1,0x90,0x9e,0xb2,0xe0,0xfd,0x74,0x01, ++0x7e,0x00,0xa8,0x05,0x08,0x80,0x05,0xc3,0x33,0xce,0x33,0xce,0xd8,0xf9,0xff,0x90, ++0x00,0x42,0xe0,0xfb,0xe4,0xfe,0xef,0x5b,0xa8,0x05,0x08,0x80,0x06,0xce,0xa2,0xe7, ++0x13,0xce,0x13,0xd8,0xf8,0xff,0xd0,0xd0,0x92,0xaf,0x22,0x75,0x28,0x33,0xe4,0xf5, ++0x29,0x75,0x2a,0x03,0xf5,0x2b,0x90,0x01,0x30,0xe5,0x28,0xf0,0xa3,0xe5,0x29,0xf0, ++0xa3,0xe5,0x2a,0xf0,0xa3,0xe5,0x2b,0xf0,0x22,0xe4,0x90,0x9e,0x31,0xf0,0xa3,0xf0, ++0x75,0x8e,0x02,0x12,0x4f,0xda,0x12,0x5f,0xa9,0x12,0x5f,0xbc,0xe4,0xf5,0x12,0x12, ++0x6f,0xa1,0x12,0x77,0x5d,0x12,0x60,0x9b,0x12,0x32,0x3d,0x12,0x77,0x18,0x11,0x8b, ++0x90,0x00,0xf3,0xe0,0x30,0xe2,0x0d,0x90,0x05,0x41,0x74,0x10,0xf0,0x90,0x05,0x5a, ++0xf0,0xa3,0xe4,0xf0,0x12,0x5f,0xf4,0x12,0x5f,0x91,0x12,0x44,0xfe,0x12,0x7d,0x1d, ++0x90,0x9e,0x33,0xe5,0xd9,0xf0,0x12,0x4d,0x8b,0xc2,0xaf,0x90,0x00,0x80,0xe0,0x44, ++0x40,0xf0,0x12,0x49,0xb9,0x75,0xe8,0x03,0x43,0xa8,0x85,0xd2,0xaf,0x90,0x01,0xbe, ++0xe0,0x04,0xf0,0x90,0x01,0xc0,0xe0,0x04,0xf0,0x90,0x9e,0x31,0xe0,0x64,0x01,0xf0, ++0x24,0xa9,0x90,0x01,0xc4,0xf0,0x74,0x50,0xa3,0xf0,0xe5,0x12,0x30,0xe4,0x09,0xc2, ++0xaf,0x53,0x12,0xef,0xd2,0xaf,0x31,0x8e,0xe5,0x12,0x30,0xe6,0x17,0xc2,0xaf,0x53, ++0x12,0xbf,0xd2,0xaf,0x12,0x69,0x51,0x90,0x9e,0x1e,0xe0,0xff,0x60,0x03,0xb4,0x01, ++0x03,0x12,0x7d,0x7b,0x90,0x9e,0x1e,0xe0,0x70,0x03,0x12,0x7e,0x7e,0x31,0x61,0x80, ++0xb8,0x90,0x06,0x34,0xe0,0x60,0x26,0x14,0x70,0x1b,0x7b,0x01,0x7a,0x06,0x79,0x35, ++0x7f,0xf9,0x7e,0x01,0x12,0x4f,0x48,0xbf,0x01,0x09,0x90,0x06,0x35,0xe0,0x54,0x0f, ++0xf0,0x80,0x05,0x80,0x00,0x02,0x77,0x0a,0xe4,0x90,0x06,0x34,0xf0,0x22,0x90,0x01, ++0xcc,0xe0,0x54,0x0f,0x90,0x9e,0x34,0xf0,0x90,0x9e,0x34,0xe0,0xfd,0x70,0x02,0x41, ++0xcf,0x90,0x9e,0xae,0xe0,0xff,0x74,0x01,0x7e,0x00,0xa8,0x07,0x08,0x80,0x05,0xc3, ++0x33,0xce,0x33,0xce,0xd8,0xf9,0xff,0xef,0x5d,0x70,0x02,0x41,0xc8,0x90,0x9e,0xae, ++0xe0,0x75,0xf0,0x04,0x90,0x01,0xd0,0x12,0x43,0x5f,0xe0,0x90,0x9e,0x35,0xf0,0x75, ++0x1e,0x01,0x75,0x1f,0x9e,0x75,0x20,0x35,0x75,0x21,0x01,0x7b,0x01,0x7a,0x9e,0x79, ++0x36,0x12,0x45,0x09,0x90,0x9e,0x36,0xe0,0xff,0xc4,0x13,0x13,0x13,0x54,0x01,0x90, ++0x9e,0xae,0x30,0xe0,0x59,0xe0,0x75,0xf0,0x02,0x90,0x00,0x88,0x12,0x43,0x5f,0xe0, ++0x90,0x9e,0x37,0xf0,0x90,0x9e,0xae,0xe0,0x75,0xf0,0x02,0x90,0x00,0x89,0x12,0x43, ++0x5f,0xe0,0x90,0x9e,0x38,0xf0,0x90,0x9e,0xae,0xe0,0x75,0xf0,0x04,0x90,0x01,0xd1, ++0x12,0x43,0x5f,0xe0,0x90,0x9e,0x39,0xf0,0x90,0x9e,0xae,0xe0,0x75,0xf0,0x04,0x90, ++0x01,0xd2,0x12,0x43,0x5f,0xe0,0x90,0x9e,0x3a,0xf0,0x90,0x9e,0xae,0xe0,0x75,0xf0, ++0x04,0x90,0x01,0xd3,0x12,0x43,0x5f,0xe0,0x90,0x9e,0x3b,0xf0,0x80,0x33,0xe0,0x75, ++0xf0,0x04,0x90,0x01,0xd1,0x12,0x43,0x5f,0xe0,0x90,0x9e,0x37,0xf0,0x90,0x9e,0xae, ++0xe0,0x75,0xf0,0x04,0x90,0x01,0xd2,0x12,0x43,0x5f,0xe0,0x90,0x9e,0x38,0xf0,0x90, ++0x9e,0xae,0xe0,0x75,0xf0,0x04,0x90,0x01,0xd3,0x12,0x43,0x5f,0xe0,0x90,0x9e,0x39, ++0xf0,0xef,0x54,0x7f,0xff,0x7b,0x01,0x7a,0x9e,0x79,0x37,0x51,0xd0,0x90,0x9e,0x34, ++0xe0,0xff,0x90,0x9e,0xae,0xe0,0xfe,0x74,0x01,0xa8,0x06,0x08,0x80,0x02,0xc3,0x33, ++0xd8,0xfc,0xf4,0x5f,0x90,0x9e,0x34,0xf0,0x90,0x9e,0xae,0xe0,0xff,0x74,0x01,0xa8, ++0x07,0x08,0x80,0x02,0xc3,0x33,0xd8,0xfc,0x90,0x01,0xcc,0xf0,0x90,0x9e,0xae,0xe0, ++0x04,0xf0,0xe0,0x54,0x03,0xf0,0x21,0x98,0x90,0x01,0xc6,0xe0,0x44,0x02,0xf0,0x22, ++0x90,0x9e,0x3c,0x12,0x43,0x8b,0xef,0x12,0x43,0x94,0x53,0x0b,0x01,0x53,0x14,0x02, ++0x53,0x2f,0x03,0x53,0x38,0x05,0x53,0x41,0x06,0x53,0x8f,0x07,0x53,0x49,0x09,0x53, ++0x52,0x0c,0x53,0x5b,0x0d,0x53,0x64,0x0e,0x53,0x6d,0x1b,0x53,0x76,0x1c,0x53,0x7f, ++0x2c,0x53,0x1d,0x2d,0x53,0x26,0x2e,0x00,0x00,0x53,0x88,0x90,0x9e,0x3c,0x12,0x43, ++0x6b,0x02,0x61,0x9d,0x90,0x9e,0x3c,0x12,0x43,0x6b,0x02,0x71,0xc4,0x90,0x9e,0x3c, ++0x12,0x43,0x6b,0x02,0x71,0xca,0x90,0x9e,0x3c,0x12,0x43,0x6b,0x02,0x72,0x12,0x90, ++0x9e,0x3c,0x12,0x43,0x6b,0x02,0x72,0x40,0x90,0x9e,0x3c,0x12,0x43,0x6b,0x02,0x71, ++0x74,0x90,0x9e,0x3c,0x12,0x43,0x6b,0x80,0x47,0x90,0x9e,0x3c,0x12,0x43,0x6b,0x02, ++0x72,0x88,0x90,0x9e,0x3c,0x12,0x43,0x6b,0x02,0x4b,0x7e,0x90,0x9e,0x3c,0x12,0x43, ++0x6b,0x02,0x7c,0xea,0x90,0x9e,0x3c,0x12,0x43,0x6b,0x02,0x4c,0xb8,0x90,0x9e,0x3c, ++0x12,0x43,0x6b,0x02,0x71,0xbc,0x90,0x9e,0x3c,0x12,0x43,0x6b,0x02,0x71,0xa3,0x90, ++0x9e,0x3c,0x12,0x43,0x6b,0x02,0x75,0xea,0x90,0x01,0xc6,0xe0,0x44,0x01,0xf0,0x22, ++0x90,0x00,0x04,0x12,0x42,0x20,0xff,0x54,0x1f,0xfe,0xef,0x54,0x20,0xc4,0x13,0x54, ++0x07,0xfd,0xaf,0x06,0x90,0x9e,0x3f,0xef,0xf0,0xa3,0xed,0xf0,0xa3,0x12,0x43,0x8b, ++0x90,0x9e,0x41,0x12,0x43,0x6b,0x90,0x00,0x03,0x12,0x42,0x20,0x54,0xf0,0xc4,0x54, ++0x0f,0x90,0x9e,0x44,0xf0,0x90,0x00,0x04,0x12,0x42,0x20,0x54,0x40,0xc4,0x13,0x13, ++0x54,0x03,0x90,0x9e,0x45,0xf0,0x90,0x9e,0x3f,0xe0,0xff,0x75,0xf0,0x09,0x90,0x96, ++0x46,0x12,0x43,0x5f,0xad,0x82,0xac,0x83,0x90,0x9e,0x46,0xec,0xf0,0xa3,0xed,0xf0, ++0xef,0x75,0xf0,0x09,0xa4,0x24,0x44,0xf9,0x74,0x96,0x35,0xf0,0xfa,0x7b,0x01,0xa3, ++0x12,0x43,0x8b,0x90,0x9e,0x41,0x12,0x43,0x6b,0x90,0x00,0x03,0x12,0x42,0x20,0x54, ++0x0f,0xff,0x90,0x9e,0x48,0x12,0x43,0x6b,0xef,0x12,0x42,0x4d,0x90,0x9e,0x41,0x12, ++0x43,0x6b,0x90,0x00,0x02,0x12,0x42,0x20,0xff,0x90,0x9e,0x48,0x12,0x43,0x6b,0x90, ++0x00,0x01,0xef,0x12,0x42,0x5f,0x90,0x9e,0x41,0x12,0x43,0x6b,0x90,0x00,0x01,0x12, ++0x42,0x20,0xff,0x90,0x9e,0x46,0xe0,0xfc,0xa3,0xe0,0xfd,0xf5,0x82,0x8c,0x83,0xef, ++0xf0,0x12,0x29,0xd9,0x8d,0x82,0x8c,0x83,0xa3,0xf0,0x90,0x9e,0x44,0xe0,0xfe,0x90, ++0x9e,0x3f,0xe0,0xff,0x24,0x82,0xf5,0x82,0xe4,0x34,0x95,0xf5,0x83,0xee,0xf0,0x90, ++0x9e,0x40,0xe0,0xfe,0x75,0xf0,0x09,0xef,0x90,0x96,0x4a,0x12,0x43,0x5f,0xee,0xf0, ++0x75,0xf0,0x09,0xef,0x90,0x96,0x4b,0x12,0x43,0x5f,0x74,0x01,0xf0,0x90,0x9e,0x45, ++0xe0,0xfe,0x75,0xf0,0x09,0xef,0x90,0x96,0x4c,0x12,0x43,0x5f,0xee,0xf0,0x8f,0x59, ++0xef,0x25,0xe0,0x24,0xc6,0xf5,0x82,0xe4,0x34,0x9b,0xaf,0x82,0xf5,0x5b,0x8f,0x5c, ++0xe5,0x59,0x75,0xf0,0x02,0xa4,0x24,0x02,0xf9,0x74,0x95,0x35,0xf0,0x75,0x5d,0x01, ++0xf5,0x5e,0x89,0x5f,0x75,0xf0,0x09,0xe5,0x59,0x90,0x96,0x46,0x12,0x43,0x5f,0xaf, ++0x82,0x85,0x83,0x60,0x8f,0x61,0xe5,0x59,0x75,0xf0,0x09,0xa4,0x24,0x44,0xf9,0x74, ++0x96,0x35,0xf0,0x75,0x62,0x01,0xf5,0x63,0x89,0x64,0x74,0x82,0x25,0x59,0xf5,0x82, ++0xe4,0x34,0x95,0xf5,0x83,0xe0,0x12,0x43,0x94,0x55,0x1e,0x00,0x55,0x33,0x01,0x55, ++0x48,0x02,0x55,0x5d,0x03,0x55,0x86,0x04,0x55,0x9b,0x05,0x55,0xb0,0x06,0x55,0xd6, ++0x0c,0x56,0x03,0x0d,0x56,0x30,0x0e,0x56,0x5d,0x0f,0x00,0x00,0x56,0x91,0xe5,0x59, ++0x25,0xe0,0x24,0xc6,0xf5,0x82,0xe4,0x34,0x9b,0xf5,0x83,0x74,0xf0,0xf0,0xa3,0x74, ++0x15,0x80,0x3c,0xe5,0x59,0x25,0xe0,0x24,0xc6,0xf5,0x82,0xe4,0x34,0x9b,0xf5,0x83, ++0x74,0xf0,0xf0,0xa3,0x74,0x10,0x80,0x27,0xe5,0x59,0x25,0xe0,0x24,0xc6,0xf5,0x82, ++0xe4,0x34,0x9b,0xf5,0x83,0x74,0xf0,0xf0,0xa3,0x74,0x05,0x80,0x12,0xe5,0x59,0x25, ++0xe0,0x24,0xc6,0xf5,0x82,0xe4,0x34,0x9b,0xf5,0x83,0x74,0xf0,0xf0,0xa3,0xe4,0xf0, ++0xe5,0x59,0x25,0xe0,0x24,0x02,0xf5,0x82,0xe4,0x34,0x95,0xf5,0x83,0x74,0x0f,0xf0, ++0xa3,0x74,0x8f,0xf0,0xc1,0x91,0xe5,0x59,0x25,0xe0,0x24,0xc6,0xf5,0x82,0xe4,0x34, ++0x9b,0xf5,0x83,0x74,0x0f,0xf0,0xa3,0x74,0xf5,0x80,0x27,0xe5,0x59,0x25,0xe0,0x24, ++0xc6,0xf5,0x82,0xe4,0x34,0x9b,0xf5,0x83,0x74,0x0f,0xf0,0xa3,0x74,0xf0,0x80,0x12, ++0xe5,0x59,0x25,0xe0,0x24,0xc6,0xf5,0x82,0xe4,0x34,0x9b,0xf5,0x83,0xe4,0xf0,0xa3, ++0x74,0x0d,0xf0,0xe5,0x59,0x25,0xe0,0x24,0x02,0xf5,0x82,0xe4,0x34,0x95,0xf5,0x83, ++0xe4,0xf0,0xa3,0xf0,0xc1,0x91,0x90,0x04,0x47,0xe0,0xab,0x5d,0xaa,0x5e,0xa9,0x5f, ++0x12,0x42,0x4d,0x90,0x04,0x46,0xe0,0xab,0x5d,0xaa,0x5e,0xa9,0x5f,0x90,0x00,0x01, ++0x12,0x42,0x5f,0x90,0x04,0x45,0xe0,0x85,0x5c,0x82,0x85,0x5b,0x83,0xf0,0x90,0x04, ++0x44,0xc1,0x88,0x90,0x04,0x4b,0xe0,0xab,0x5d,0xaa,0x5e,0xa9,0x5f,0x12,0x42,0x4d, ++0x90,0x04,0x4a,0xe0,0xab,0x5d,0xaa,0x5e,0xa9,0x5f,0x90,0x00,0x01,0x12,0x42,0x5f, ++0x90,0x04,0x49,0xe0,0x85,0x5c,0x82,0x85,0x5b,0x83,0xf0,0x90,0x04,0x48,0x80,0x58, ++0x90,0x04,0x4f,0xe0,0xab,0x5d,0xaa,0x5e,0xa9,0x5f,0x12,0x42,0x4d,0x90,0x04,0x4e, ++0xe0,0xab,0x5d,0xaa,0x5e,0xa9,0x5f,0x90,0x00,0x01,0x12,0x42,0x5f,0x90,0x04,0x4d, ++0xe0,0x85,0x5c,0x82,0x85,0x5b,0x83,0xf0,0x90,0x04,0x4c,0x80,0x2b,0x90,0x04,0x53, ++0xe0,0xab,0x5d,0xaa,0x5e,0xa9,0x5f,0x12,0x42,0x4d,0x90,0x04,0x52,0xe0,0xab,0x5d, ++0xaa,0x5e,0xa9,0x5f,0x90,0x00,0x01,0x12,0x42,0x5f,0x90,0x04,0x51,0xe0,0x85,0x5c, ++0x82,0x85,0x5b,0x83,0xf0,0x90,0x04,0x50,0xe0,0x85,0x5c,0x82,0x85,0x5b,0x83,0xa3, ++0xf0,0xab,0x5d,0xaa,0x5e,0xa9,0x5f,0xc0,0x03,0xc0,0x02,0xc0,0x01,0x12,0x29,0xd9, ++0xff,0xab,0x62,0xaa,0x63,0xa9,0x64,0x12,0x29,0xd9,0x5f,0xd0,0x01,0xd0,0x02,0xd0, ++0x03,0x12,0x42,0x4d,0xab,0x5d,0xe5,0x5f,0x24,0x01,0xf9,0xe4,0x35,0x5e,0xfa,0xc0, ++0x03,0xc0,0x02,0xc0,0x01,0x12,0x29,0xd9,0xff,0xab,0x62,0xaa,0x63,0xa9,0x64,0x90, ++0x00,0x01,0x12,0x42,0x20,0x5f,0xd0,0x01,0xd0,0x02,0xd0,0x03,0x12,0x42,0x4d,0x85, ++0x5c,0x82,0x85,0x5b,0x83,0xc0,0x83,0xc0,0x82,0xe0,0xff,0x85,0x61,0x82,0x85,0x60, ++0x83,0xe0,0xfe,0xef,0x5e,0xd0,0x82,0xd0,0x83,0xf0,0x85,0x5c,0x82,0x85,0x5b,0x83, ++0xa3,0xc0,0x83,0xc0,0x82,0xe0,0xff,0x85,0x61,0x82,0x85,0x60,0x83,0xa3,0xe0,0xfe, ++0xef,0x5e,0xd0,0x82,0xd0,0x83,0xf0,0xe5,0x59,0x25,0xe0,0x24,0x02,0xf5,0x82,0xe4, ++0x34,0x95,0xf5,0x83,0xe0,0xfe,0xa3,0xe0,0x4e,0x60,0x3b,0x75,0x5a,0x0b,0x74,0x01, ++0x7e,0x00,0xa8,0x5a,0x08,0x80,0x05,0xc3,0x33,0xce,0x33,0xce,0xd8,0xf9,0xff,0xe5, ++0x59,0x25,0xe0,0x24,0x02,0xf5,0x82,0xe4,0x34,0x95,0xf5,0x83,0xe0,0x5e,0xfe,0xa3, ++0xe0,0x5f,0x4e,0x60,0x06,0xe5,0x5a,0x24,0x10,0x80,0x5d,0x15,0x5a,0xe5,0x5a,0xc3, ++0x94,0x00,0x50,0xca,0x80,0x56,0xe5,0x59,0x25,0xe0,0x24,0xc6,0xf5,0x82,0xe4,0x34, ++0x9b,0xf5,0x83,0xe0,0xfe,0xa3,0xe0,0x4e,0x60,0x3d,0x75,0x5a,0x0f,0x74,0x01,0x7e, ++0x00,0xa8,0x5a,0x08,0x80,0x05,0xc3,0x33,0xce,0x33,0xce,0xd8,0xf9,0xff,0xe5,0x59, ++0x25,0xe0,0x24,0xc6,0xf5,0x82,0xe4,0x34,0x9b,0xf5,0x83,0xe0,0x5e,0xfe,0xa3,0xe0, ++0x5f,0x4e,0x60,0x08,0x90,0x9e,0x4b,0xe5,0x5a,0xf0,0x80,0x10,0x15,0x5a,0xe5,0x5a, ++0xc3,0x94,0x00,0x50,0xc8,0x80,0x05,0xe4,0x90,0x9e,0x4b,0xf0,0xe5,0x59,0x25,0xe0, ++0x24,0xc6,0xf5,0x82,0xe4,0x34,0x9b,0xf5,0x83,0xe0,0xfe,0xa3,0xe0,0x4e,0x60,0x3b, ++0xe4,0xf5,0x5a,0x74,0x01,0x7e,0x00,0xa8,0x5a,0x08,0x80,0x05,0xc3,0x33,0xce,0x33, ++0xce,0xd8,0xf9,0xff,0xe5,0x59,0x25,0xe0,0x24,0xc6,0xf5,0x82,0xe4,0x34,0x9b,0xf5, ++0x83,0xe0,0x5e,0xfe,0xa3,0xe0,0x5f,0x4e,0x60,0x08,0x90,0x9e,0x4c,0xe5,0x5a,0xf0, ++0x80,0x5b,0x05,0x5a,0xe5,0x5a,0xb4,0x10,0xca,0x80,0x52,0xe5,0x59,0x25,0xe0,0x24, ++0x02,0xf5,0x82,0xe4,0x34,0x95,0xf5,0x83,0xe0,0xfe,0xa3,0xe0,0x4e,0x60,0x39,0xe4, ++0xf5,0x5a,0x74,0x01,0x7e,0x00,0xa8,0x5a,0x08,0x80,0x05,0xc3,0x33,0xce,0x33,0xce, ++0xd8,0xf9,0xff,0xe5,0x59,0x25,0xe0,0x24,0x02,0xf5,0x82,0xe4,0x34,0x95,0xf5,0x83, ++0xe0,0x5e,0xfe,0xa3,0xe0,0x5f,0x4e,0x60,0x06,0xe5,0x5a,0x24,0x10,0x80,0x0a,0x05, ++0x5a,0xe5,0x5a,0xb4,0x0c,0xcc,0x80,0x05,0xe4,0x90,0x9e,0x4c,0xf0,0x90,0x9e,0x4b, ++0xe0,0xff,0x75,0xf0,0x09,0xe5,0x59,0x90,0x96,0x48,0x12,0x43,0x5f,0xef,0xf0,0x90, ++0x9e,0x4c,0xe0,0xfe,0x75,0xf0,0x09,0xe5,0x59,0x90,0x96,0x49,0x12,0x43,0x5f,0xee, ++0xf0,0x74,0x84,0x25,0x59,0xf5,0x82,0xe4,0x34,0x04,0xf5,0x83,0xe0,0xd3,0x9f,0x40, ++0x05,0x90,0x9e,0x4b,0x11,0xe0,0x74,0x84,0x25,0x59,0xf5,0x82,0xe4,0x34,0x04,0xf5, ++0x83,0xe0,0xff,0x90,0x9e,0x4c,0xe0,0xfe,0xef,0xc3,0x9e,0x50,0x02,0x11,0xe0,0x90, ++0x9e,0x4b,0xe0,0xff,0xd3,0x94,0x13,0x40,0x07,0x90,0x96,0x43,0x74,0x03,0xf0,0x22, ++0xef,0xd3,0x94,0x0b,0x40,0x07,0x90,0x96,0x43,0x74,0x02,0xf0,0x22,0xef,0xd3,0x94, ++0x03,0x40,0x07,0x90,0x96,0x43,0x74,0x01,0xf0,0x22,0xe4,0x90,0x96,0x43,0xf0,0x22, ++0xe0,0xfd,0x74,0x26,0x25,0x59,0xf5,0x82,0xe4,0x34,0x9d,0xf5,0x83,0xed,0xf0,0xaf, ++0x59,0xd3,0x10,0xaf,0x01,0xc3,0xc0,0xd0,0xef,0xc3,0x94,0x20,0x50,0x0e,0x74,0x84, ++0x2f,0xf5,0x82,0xe4,0x34,0x04,0xf5,0x83,0xed,0xf0,0x80,0x29,0x74,0xa6,0x2f,0xf5, ++0x82,0xe4,0x34,0x9c,0xf5,0x83,0xed,0xf0,0x90,0x9e,0x78,0xef,0xf0,0x24,0xa6,0xf5, ++0x82,0xe4,0x34,0x9c,0xf5,0x83,0xe0,0x90,0x9e,0x79,0xf0,0x7b,0x01,0x7a,0x9e,0x79, ++0x78,0x7d,0x02,0x31,0x3a,0xd0,0xd0,0x92,0xaf,0x22,0xd3,0x10,0xaf,0x01,0xc3,0xc0, ++0xd0,0x90,0x9e,0x97,0x12,0x43,0x8b,0x90,0x9e,0x9a,0xe0,0x54,0xf0,0x44,0x06,0xff, ++0xf0,0xed,0x54,0x0f,0xc4,0x54,0xf0,0xfe,0xef,0x54,0x0f,0x4e,0xf0,0x90,0x9e,0x97, ++0x12,0x43,0x6b,0x90,0x9e,0x94,0x12,0x43,0x8b,0x7b,0x01,0x7a,0x9e,0x79,0x9a,0xd1, ++0x14,0xd0,0xd0,0x92,0xaf,0x22,0x8f,0x50,0x8d,0x51,0xe5,0x51,0x54,0x1f,0xf5,0x56, ++0x74,0x01,0x2f,0xf5,0x82,0xe4,0x34,0x94,0xf5,0x83,0xe0,0xf5,0x54,0x90,0x04,0xfd, ++0xe0,0xb4,0x01,0x05,0x75,0x57,0x03,0x80,0x03,0x75,0x57,0x01,0xeb,0xc3,0x95,0x57, ++0x40,0x04,0xaf,0x50,0x80,0x33,0xe5,0x54,0x25,0x53,0xf5,0x55,0xe5,0x56,0x90,0x41, ++0xd6,0x93,0xff,0xe5,0x55,0xd3,0x9f,0x74,0x01,0x40,0x11,0x25,0x50,0xf5,0x82,0xe4, ++0x34,0x94,0xf5,0x83,0xe4,0xf0,0xad,0x51,0xaf,0x50,0x01,0xf1,0x25,0x50,0xf5,0x82, ++0xe4,0x34,0x94,0xf5,0x83,0xe5,0x55,0xf0,0x22,0xad,0x07,0x75,0xf0,0x09,0xed,0x90, ++0x96,0x48,0x12,0x43,0x5f,0xe0,0xff,0x74,0x67,0x2d,0xf5,0x82,0xe4,0x34,0x9d,0xf5, ++0x83,0xe0,0x54,0x1f,0xf5,0x58,0xd3,0x9f,0x40,0x02,0x8f,0x58,0xe5,0x58,0x25,0xe0, ++0x24,0x9e,0xf5,0x82,0xe4,0x34,0x41,0xf5,0x83,0xe4,0x93,0xfe,0x74,0x01,0x93,0xff, ++0xe5,0x58,0x25,0xe0,0x24,0x66,0xf5,0x82,0xe4,0x34,0x41,0xf5,0x83,0x74,0x01,0x93, ++0x2f,0xff,0xe4,0x93,0x3e,0xc3,0x13,0xfe,0xef,0x13,0xff,0xed,0x25,0xe0,0x24,0xc2, ++0xf5,0x82,0xe4,0x34,0x95,0xf5,0x83,0xee,0xf0,0xa3,0xef,0xf0,0xaf,0x05,0xad,0x58, ++0x11,0xf1,0xaf,0x58,0x22,0xc0,0xe0,0xc0,0xf0,0xc0,0x83,0xc0,0x82,0xc0,0xd0,0x75, ++0xd0,0x00,0xc0,0x00,0xc0,0x01,0xc0,0x02,0xc0,0x03,0xc0,0x04,0xc0,0x05,0xc0,0x06, ++0xc0,0x07,0x90,0x01,0xc4,0x74,0x45,0xf0,0x74,0x5a,0xa3,0xf0,0x90,0x01,0x34,0xe0, ++0x55,0x28,0xf5,0x2c,0x90,0x01,0x36,0xe0,0x55,0x2a,0xf5,0x2e,0xa3,0xe0,0x55,0x2b, ++0xf5,0x2f,0xe5,0x2c,0x20,0xe0,0x02,0x61,0xe1,0x90,0x01,0x34,0x74,0x01,0xf0,0x85, ++0xd1,0x08,0x85,0xd2,0x09,0x85,0xd3,0x0a,0x85,0xd4,0x0b,0x85,0xd5,0x0c,0x85,0xd6, ++0x0d,0x85,0xd7,0x0e,0x85,0xd9,0x0f,0xe5,0x0f,0x54,0x40,0xc3,0x13,0xff,0xe5,0x0e, ++0x54,0x20,0x6f,0x70,0x02,0x61,0x93,0xe5,0x0f,0x30,0xe5,0x02,0x61,0x93,0xe5,0x0d, ++0x54,0x3f,0xf5,0x4d,0xe5,0x08,0x54,0x3f,0xf5,0x4e,0xe5,0x0c,0x54,0x1f,0xff,0xe5, ++0x4d,0x25,0xe0,0x24,0xc4,0xf5,0x82,0xe4,0x34,0x99,0xf5,0x83,0xe4,0x8f,0xf0,0x12, ++0x42,0x81,0xe5,0x0e,0x54,0x1f,0xff,0xe5,0x4d,0x25,0xe0,0x24,0x80,0xf5,0x82,0xe4, ++0x34,0x93,0xf5,0x83,0xe4,0x8f,0xf0,0x12,0x42,0x81,0xe5,0x4e,0xd3,0x94,0x04,0x40, ++0x03,0x75,0x4e,0x04,0x75,0xf0,0x0a,0xe5,0x4d,0x90,0x90,0x00,0x12,0x43,0x5f,0x75, ++0xf0,0x02,0xe5,0x4e,0x12,0x43,0x5f,0xe0,0xfe,0xa3,0xe0,0xff,0xe5,0x0e,0x54,0x1f, ++0x2f,0xff,0xe4,0x3e,0xfe,0x75,0xf0,0x0a,0xe5,0x4d,0x90,0x90,0x00,0x12,0x43,0x5f, ++0x75,0xf0,0x02,0xe5,0x4e,0x12,0x43,0x5f,0xee,0xf0,0xa3,0xef,0xf0,0xe5,0x0f,0x20, ++0xe6,0x23,0xe5,0x0e,0x54,0x1f,0xff,0xe5,0x4d,0x25,0xe0,0x24,0xc4,0xf5,0x82,0xe4, ++0x34,0x98,0xf5,0x83,0xe4,0x8f,0xf0,0x12,0x42,0x81,0xe5,0x0a,0x30,0xe7,0x34,0xaf, ++0x4d,0x31,0xd9,0x80,0x2e,0xe5,0x0e,0x54,0x1f,0xff,0xe5,0x4d,0x25,0xe0,0x24,0x44, ++0xf5,0x82,0xe4,0x34,0x99,0xf5,0x83,0xe4,0x8f,0xf0,0x12,0x42,0x81,0xe5,0x0a,0x30, ++0xe7,0x11,0xe5,0x0a,0x54,0x7f,0xfd,0xe5,0x0e,0x54,0x1f,0xf5,0x53,0xab,0x4e,0xaf, ++0x4d,0x31,0x76,0xe5,0x74,0x14,0x24,0xfd,0x50,0x02,0x80,0x45,0x90,0x9e,0x61,0xe0, ++0x60,0x37,0x90,0x01,0x5b,0xe4,0xf0,0x90,0x01,0x3c,0x74,0x04,0xf0,0xd1,0x05,0xef, ++0x64,0x01,0x70,0x2d,0x90,0x9e,0x55,0xe0,0xf5,0x44,0x75,0x45,0x00,0xe4,0xfb,0xfd, ++0x7f,0x58,0x7e,0x01,0x12,0x35,0xab,0x90,0x01,0x5b,0x74,0x05,0xf0,0x90,0x06,0x92, ++0x74,0x01,0xf0,0x90,0x9e,0x5d,0xf0,0x80,0x08,0xd1,0x05,0xbf,0x01,0x03,0x12,0x44, ++0xd3,0xe5,0x2c,0x30,0xe1,0x20,0x90,0x01,0x34,0x74,0x02,0xf0,0x85,0xd1,0x13,0x85, ++0xd2,0x14,0x85,0xd3,0x15,0x85,0xd4,0x16,0x85,0xd5,0x17,0x85,0xd6,0x18,0x85,0xd7, ++0x19,0x85,0xd9,0x1a,0xd1,0x9c,0xe5,0x2c,0x30,0xe3,0x06,0x90,0x01,0x34,0x74,0x08, ++0xf0,0xe5,0x2c,0x30,0xe4,0x09,0x90,0x01,0x34,0x74,0x10,0xf0,0x43,0x12,0x10,0xe5, ++0x2c,0x30,0xe5,0x26,0x90,0x01,0xcf,0xe0,0x30,0xe5,0x1f,0xe0,0x54,0xdf,0xf0,0x90, ++0x01,0x34,0x74,0x20,0xf0,0x75,0xa8,0x00,0x75,0xe8,0x00,0x12,0x4d,0xb6,0x90,0x00, ++0x03,0xe0,0x54,0xfb,0xf0,0x12,0x49,0xb9,0x80,0xfe,0xe5,0x2c,0x30,0xe6,0x06,0x90, ++0x01,0x34,0x74,0x40,0xf0,0xe5,0x2e,0x30,0xe1,0x3c,0x90,0x01,0x36,0x74,0x02,0xf0, ++0x43,0x12,0x40,0x90,0x01,0x02,0xe0,0x54,0x03,0x64,0x01,0x70,0x29,0x90,0x01,0x37, ++0xe0,0x30,0xe0,0x0a,0x74,0x01,0xf0,0x90,0x9e,0x66,0xe4,0xf0,0x80,0x18,0x90,0x9e, ++0x66,0xe0,0x04,0xf0,0xe0,0xc3,0x94,0x0a,0x40,0x0c,0xe4,0xf0,0x90,0x04,0x19,0xe0, ++0x30,0xe0,0x03,0x12,0x4f,0xa7,0xe5,0x2e,0x30,0xe0,0x12,0x90,0x9e,0x76,0x74,0x01, ++0xf0,0x90,0x01,0x36,0xf0,0x12,0x64,0xfe,0x90,0x9e,0x76,0xe4,0xf0,0xe5,0x2e,0x30, ++0xe2,0x78,0x90,0x01,0x36,0x74,0x04,0xf0,0x90,0x01,0xbd,0xe0,0x04,0xf0,0xe5,0x73, ++0x64,0x01,0x70,0x66,0xe5,0x74,0x60,0x62,0xe5,0x74,0x64,0x02,0x60,0x06,0xe5,0x74, ++0x64,0x05,0x70,0x27,0x90,0x06,0xab,0xe0,0x90,0x9e,0x50,0xf0,0x90,0x06,0xaa,0xe0, ++0x90,0x9e,0x5f,0xf0,0x90,0x9e,0x50,0xe0,0x70,0x07,0x90,0x9e,0x5f,0xe0,0xff,0x80, ++0x05,0x90,0x9e,0x50,0xe0,0xff,0x90,0x9e,0x50,0xef,0xf0,0x90,0x9e,0x52,0xe0,0x60, ++0x03,0xe0,0x14,0xf0,0x90,0x9e,0x51,0xe4,0xf0,0x90,0x01,0x57,0xf0,0x90,0x01,0x3c, ++0x74,0x02,0xf0,0x90,0x9e,0x63,0xe0,0x54,0xfd,0xf0,0xe0,0x54,0xef,0xf0,0xe5,0x74, ++0x14,0x24,0xfd,0x50,0x02,0x80,0x03,0x12,0x45,0x53,0xe5,0x2e,0x30,0xe3,0x28,0x90, ++0x01,0x36,0x74,0x08,0xf0,0xe5,0x73,0x64,0x01,0x70,0x1c,0xe5,0x74,0x60,0x18,0x90, ++0x01,0x57,0xe4,0xf0,0x90,0x01,0x3c,0x74,0x02,0xf0,0x90,0x9e,0x89,0xe4,0x12,0x44, ++0x52,0x90,0x01,0x57,0x74,0x05,0xf0,0xe5,0x2e,0x30,0xe4,0x2f,0x90,0x01,0x36,0x74, ++0x10,0xf0,0xe5,0x73,0x64,0x01,0x70,0x23,0xe5,0x74,0x60,0x1f,0x90,0x01,0x57,0xe4, ++0xf0,0x90,0x01,0x3c,0x74,0x02,0xf0,0x90,0x9e,0x62,0xe4,0xf0,0x90,0x9e,0x63,0xe0, ++0x54,0xfd,0xf0,0xe0,0x54,0x07,0x70,0x03,0x12,0x44,0xd3,0xe5,0x2e,0x30,0xe5,0x1f, ++0x90,0x01,0x36,0x74,0x20,0xf0,0xe5,0x73,0xb4,0x01,0x14,0xe5,0x74,0x60,0x10,0x90, ++0x9e,0x61,0xe0,0x64,0x02,0x60,0x05,0x12,0x44,0xdc,0x80,0x03,0x12,0x44,0x80,0xe5, ++0x2e,0x30,0xe6,0x1e,0x90,0x01,0x36,0x74,0x40,0xf0,0xe5,0x73,0xb4,0x01,0x13,0xe5, ++0x74,0x60,0x0f,0x90,0x9e,0x63,0xe0,0x54,0xfe,0xf0,0xe0,0x54,0x07,0x70,0x03,0x12, ++0x44,0xd3,0xe5,0x2f,0x30,0xe1,0x08,0x90,0x01,0x37,0x74,0x02,0xf0,0xd1,0xbd,0x74, ++0x45,0x04,0x90,0x01,0xc4,0xf0,0x74,0x5a,0xa3,0xf0,0xd0,0x07,0xd0,0x06,0xd0,0x05, ++0xd0,0x04,0xd0,0x03,0xd0,0x02,0xd0,0x01,0xd0,0x00,0xd0,0xd0,0xd0,0x82,0xd0,0x83, ++0xd0,0xf0,0xd0,0xe0,0x32,0x90,0x04,0x1b,0xe0,0x54,0x7f,0x64,0x7f,0x7f,0x01,0x60, ++0x02,0x7f,0x00,0x22,0xd3,0x10,0xaf,0x01,0xc3,0xc0,0xd0,0x90,0x9e,0x91,0x12,0x43, ++0x8b,0x90,0x9e,0x75,0xe0,0x64,0x02,0x60,0x6e,0x90,0x9e,0x75,0xe0,0x64,0x01,0x70, ++0x66,0x90,0x9e,0xb0,0xe0,0xff,0x04,0xf0,0x90,0x9e,0x91,0x12,0x43,0x6b,0x90,0x00, ++0x01,0xef,0x12,0x42,0x5f,0x7f,0xaf,0x7e,0x01,0xf1,0x3b,0xef,0x60,0x49,0x90,0x9e, ++0x91,0x12,0x43,0x6b,0x8b,0x1e,0x8a,0x1f,0x89,0x20,0x75,0x21,0x02,0x7b,0x01,0x7a, ++0x01,0x79,0xa0,0x12,0x45,0x09,0x90,0x9e,0x94,0x12,0x43,0x6b,0x8b,0x1e,0x8a,0x1f, ++0x89,0x20,0x90,0x9e,0x91,0x12,0x43,0x6b,0x12,0x29,0xd9,0xff,0xc4,0x54,0x0f,0xf5, ++0x21,0x7b,0x01,0x7a,0x01,0x79,0xa2,0x12,0x45,0x09,0x90,0x01,0xaf,0x74,0xff,0xf0, ++0x90,0x01,0xcb,0xe0,0x64,0x80,0xf0,0xd0,0xd0,0x92,0xaf,0x22,0x90,0x9e,0x2f,0xe0, ++0x54,0xf0,0x44,0x03,0xf0,0x54,0x0f,0x44,0x80,0xf0,0x7b,0x00,0x7a,0x00,0x79,0x13, ++0x90,0x9e,0x94,0x12,0x43,0x8b,0x0b,0x7a,0x9e,0x79,0x2f,0xc1,0x14,0x7d,0x02,0x7f, ++0x03,0x12,0x36,0x75,0xe5,0x74,0x14,0x24,0xfd,0x50,0x02,0x80,0x23,0x90,0x9e,0x61, ++0xe0,0x60,0x06,0x7d,0x01,0x7f,0x0c,0x80,0x0f,0x90,0x9e,0x5e,0xe0,0x54,0x0f,0xc3, ++0x94,0x04,0x50,0x07,0x7d,0x01,0x7f,0x04,0x12,0x47,0x1a,0xe4,0xff,0x12,0x48,0x8f, ++0x22,0xd1,0x05,0xef,0x64,0x01,0x60,0x08,0x90,0x01,0xb9,0x74,0x01,0xf0,0x80,0x32, ++0x90,0x9e,0x5d,0xe0,0x60,0x08,0x90,0x01,0xb9,0x74,0x02,0xf0,0x80,0x24,0x90,0x9e, ++0x5c,0xe0,0x60,0x08,0x90,0x01,0xb9,0x74,0x04,0xf0,0x80,0x16,0x90,0x9e,0x60,0xe0, ++0x54,0x0f,0xd3,0x94,0x04,0x40,0x08,0x90,0x01,0xb9,0x74,0x08,0xf0,0x80,0x03,0x7f, ++0x01,0x22,0x90,0x01,0xb8,0x74,0x08,0xf0,0x7f,0x00,0x22,0xd3,0x10,0xaf,0x01,0xc3, ++0xc0,0xd0,0x90,0x9e,0xa0,0xee,0xf0,0xa3,0xef,0xf0,0xe4,0xa3,0xf0,0xa3,0xf0,0x90, ++0x9e,0xa0,0xe0,0xfe,0xa3,0xe0,0xf5,0x82,0x8e,0x83,0xe0,0x60,0x2d,0xc3,0x90,0x9e, ++0xa3,0xe0,0x94,0xe8,0x90,0x9e,0xa2,0xe0,0x94,0x03,0x40,0x0b,0x90,0x01,0xc6,0xe0, ++0x44,0x10,0xf0,0x7f,0x00,0x80,0x15,0x90,0x9e,0xa2,0xe4,0x75,0xf0,0x01,0x12,0x42, ++0x81,0x7f,0x0a,0x7e,0x00,0x12,0x37,0x54,0x80,0xc5,0x7f,0x01,0xd0,0xd0,0x92,0xaf, ++0x22,0x75,0x30,0x1f,0x75,0x31,0x01,0xe4,0xf5,0x32,0x90,0x01,0x38,0xe5,0x30,0xf0, ++0xa3,0xe5,0x31,0xf0,0xa3,0xe5,0x32,0xf0,0x22,0x90,0x00,0x02,0xe0,0x54,0xe0,0x90, ++0x9e,0x75,0x60,0x04,0x74,0x01,0xf0,0x22,0x74,0x02,0xf0,0x22,0x90,0x00,0xf3,0xe0, ++0x30,0xe3,0x08,0x90,0x9e,0x77,0x74,0x01,0xf0,0x80,0x05,0xe4,0x90,0x9e,0x77,0xf0, ++0x90,0x9e,0x77,0xe0,0xb4,0x01,0x12,0x90,0x00,0xf2,0xe0,0x30,0xe7,0x0b,0x90,0x9e, ++0x64,0x74,0xfd,0xf0,0xa3,0x74,0x33,0xf0,0x22,0x90,0x9e,0x64,0x74,0xfd,0xf0,0xa3, ++0x74,0x2f,0xf0,0x22,0x90,0x01,0x64,0x74,0xa0,0xf0,0x22,0xc0,0xe0,0xc0,0xf0,0xc0, ++0x83,0xc0,0x82,0xc0,0xd0,0x75,0xd0,0x00,0xc0,0x00,0xc0,0x01,0xc0,0x02,0xc0,0x03, ++0xc0,0x04,0xc0,0x05,0xc0,0x06,0xc0,0x07,0x90,0x01,0xc4,0x74,0xfb,0xf0,0x74,0x5f, ++0xa3,0xf0,0x53,0x91,0xef,0x90,0x00,0x51,0xe0,0xff,0x90,0x00,0x55,0xe0,0x5f,0xf5, ++0x3d,0xe5,0x3d,0x30,0xe6,0x18,0x74,0x40,0xf0,0x90,0x9e,0x1d,0xe0,0x54,0x03,0xff, ++0xbf,0x03,0x0b,0x90,0x9e,0x1a,0xe0,0x60,0x05,0x7f,0x01,0x12,0x4a,0xd6,0xe5,0x3d, ++0x30,0xe7,0x15,0x90,0x00,0x55,0x74,0x80,0xf0,0x90,0x9e,0x1d,0xe0,0x54,0x03,0xff, ++0xbf,0x03,0x05,0x7f,0x02,0x12,0x4a,0xd6,0x90,0x01,0xc4,0x74,0xfb,0xf0,0x74,0x5f, ++0xa3,0xf0,0xd0,0x07,0xd0,0x06,0xd0,0x05,0xd0,0x04,0xd0,0x03,0xd0,0x02,0xd0,0x01, ++0xd0,0x00,0xd0,0xd0,0xd0,0x82,0xd0,0x83,0xd0,0xf0,0xd0,0xe0,0x32,0x8f,0x6b,0x8c, ++0x6c,0x8d,0x6d,0x22,0x8f,0x6e,0x8c,0x6f,0x8d,0x70,0x22,0xe4,0xf5,0x73,0x90,0x9e, ++0x63,0xf0,0xf5,0x74,0x90,0x9e,0x60,0x74,0x0c,0xf0,0x90,0x9e,0x5e,0xf0,0xe4,0x90, ++0x9e,0x61,0xf0,0x90,0x9e,0x5d,0xf0,0x90,0x9e,0x5c,0xf0,0x90,0x9e,0x5f,0x04,0xf0, ++0x90,0x9e,0x50,0xf0,0xe4,0x90,0x9e,0x62,0xf0,0x90,0x9e,0x52,0xf0,0x90,0x9e,0x5a, ++0x74,0x07,0xf0,0xe4,0x90,0x9e,0x51,0xf0,0x90,0x9e,0x58,0xf0,0xa3,0x74,0x02,0xf0, ++0x90,0x9e,0x56,0x14,0xf0,0xa3,0x74,0x03,0xf0,0x90,0x9e,0x55,0x74,0x14,0xf0,0x90, ++0x9e,0x5b,0x74,0x05,0xf0,0xe4,0x90,0x9e,0x54,0xf0,0x90,0x9e,0x4f,0xf0,0x90,0x9e, ++0x76,0xf0,0x22,0xe4,0x90,0x9e,0x62,0xf0,0x90,0x9e,0x51,0xf0,0x90,0x9e,0x63,0xf0, ++0x22,0x8b,0x59,0x8a,0x5a,0x89,0x5b,0x31,0x03,0xab,0x59,0xaa,0x5a,0xa9,0x5b,0x12, ++0x29,0xd9,0xf5,0x74,0x14,0x60,0x0e,0x14,0x60,0x1e,0x14,0x60,0x2f,0x24,0x03,0x70, ++0x40,0x7f,0x01,0x80,0x3a,0xab,0x59,0xaa,0x5a,0xa9,0x5b,0x90,0x00,0x02,0x12,0x42, ++0x20,0xfd,0xe4,0xff,0x31,0x72,0x80,0x27,0xab,0x59,0xaa,0x5a,0xa9,0x5b,0x90,0x00, ++0x02,0x12,0x42,0x20,0xfd,0x7f,0x01,0x31,0x72,0x1f,0x80,0x13,0xab,0x59,0xaa,0x5a, ++0xa9,0x5b,0x90,0x00,0x02,0x12,0x42,0x20,0xfd,0x7f,0x02,0x31,0x72,0xe4,0xff,0x31, ++0xc6,0x22,0xef,0x24,0xfe,0x60,0x0b,0x04,0x70,0x22,0x90,0x9e,0x5f,0x74,0x01,0xf0, ++0x80,0x16,0xed,0x70,0x0a,0x90,0x9e,0x5b,0xe0,0x90,0x9e,0x5f,0xf0,0x80,0x05,0x90, ++0x9e,0x5f,0xed,0xf0,0x90,0x9e,0x5f,0xe0,0x90,0x9e,0x50,0xf0,0x22,0xd3,0x10,0xaf, ++0x01,0xc3,0xc0,0xd0,0x90,0x00,0x01,0x12,0x42,0x20,0x90,0x9e,0x61,0xf0,0x90,0x00, ++0x03,0x12,0x42,0x20,0x90,0x9e,0x4f,0xf0,0x12,0x29,0xd9,0x65,0x74,0x60,0x02,0x31, ++0x11,0xd0,0xd0,0x92,0xaf,0x22,0xef,0x64,0x01,0x70,0x30,0x7d,0x7c,0x7f,0x02,0x12, ++0x36,0x75,0x7d,0x02,0x7f,0x03,0x12,0x36,0x75,0x90,0x01,0x57,0xe4,0xf0,0x90,0x01, ++0x3c,0x74,0x02,0xf0,0x12,0x47,0x16,0xe4,0xff,0x12,0x48,0x8f,0x90,0x06,0x04,0xe0, ++0x54,0x7f,0xf0,0x90,0x06,0x0a,0xe0,0x54,0xf8,0xf0,0x22,0x90,0x01,0x36,0x74,0x7c, ++0xf0,0xa3,0x74,0x02,0xf0,0x7d,0x7c,0xff,0x12,0x36,0xe6,0x7d,0x02,0x7f,0x03,0x12, ++0x36,0xe6,0x90,0x06,0x04,0xe0,0x44,0x80,0xf0,0x90,0x06,0x0a,0xe0,0x44,0x07,0xf0, ++0x90,0x9e,0x58,0xe0,0xa3,0xe0,0x90,0x05,0x58,0xf0,0xe5,0x73,0x30,0xe0,0x1b,0x90, ++0x9e,0x52,0xe0,0x70,0x1a,0xe0,0x04,0xf0,0x90,0x9e,0x5e,0xe0,0x54,0x0f,0xc3,0x94, ++0x04,0x50,0x0c,0x7d,0x01,0x7f,0x04,0x02,0x47,0x1a,0xe4,0x90,0x9e,0x52,0xf0,0x22, ++0x12,0x5e,0x05,0xef,0x64,0x01,0x60,0x08,0x90,0x01,0xb9,0x74,0x01,0xf0,0x80,0x52, ++0x90,0x9e,0x63,0xe0,0x54,0x03,0x60,0x08,0x90,0x01,0xb9,0x74,0x02,0xf0,0x80,0x42, ++0x90,0x9e,0x60,0xe0,0x54,0x0f,0xd3,0x94,0x02,0x40,0x08,0x90,0x01,0xb9,0x74,0x04, ++0xf0,0x80,0x2f,0x90,0x9e,0x63,0xe0,0x30,0xe2,0x08,0x90,0x01,0xb9,0x74,0x08,0xf0, ++0x80,0x20,0x90,0x9e,0x63,0xe0,0x30,0xe4,0x08,0x90,0x01,0xb9,0x74,0x10,0xf0,0x80, ++0x11,0x90,0x9e,0x52,0xe0,0x60,0x08,0x90,0x01,0xb9,0x74,0x20,0xf0,0x80,0x03,0x7f, ++0x01,0x22,0x90,0x01,0xb8,0x74,0x04,0xf0,0x7f,0x00,0x22,0xe5,0x12,0x60,0x08,0x90, ++0x01,0xb9,0x74,0x01,0xf0,0x80,0x5e,0x90,0x9e,0x60,0xe0,0x54,0x0f,0xd3,0x94,0x01, ++0x40,0x08,0x90,0x01,0xb9,0x74,0x02,0xf0,0x80,0x4b,0x90,0x02,0x87,0xe0,0x60,0x08, ++0x90,0x01,0xb9,0x74,0x04,0xf0,0x80,0x3d,0x90,0x9e,0x75,0xe0,0xb4,0x02,0x10,0x90, ++0x9e,0x64,0xe0,0xfe,0xa3,0xe0,0xf5,0x82,0x8e,0x83,0xe0,0x60,0x17,0x80,0x26,0x90, ++0x9e,0x75,0xe0,0xb4,0x01,0x0e,0x90,0x01,0xaf,0xe0,0x60,0x08,0x90,0x01,0xb9,0x74, ++0x08,0xf0,0x80,0x11,0x90,0x9e,0x54,0xe0,0x70,0x08,0x90,0x01,0xb9,0x74,0x10,0xf0, ++0x80,0x03,0x7f,0x01,0x22,0x90,0x01,0xb8,0x74,0x02,0xf0,0x7f,0x00,0x22,0x90,0x06, ++0x04,0xe0,0x54,0xbf,0xf0,0xef,0x60,0x09,0xe5,0x73,0xb4,0x01,0x04,0xe4,0xff,0x71, ++0x4d,0x90,0x9e,0x5e,0xe0,0x54,0xf0,0xf0,0xe0,0x44,0x0c,0xf0,0x22,0x8f,0x76,0x90, ++0x9e,0x5e,0xe0,0x90,0x01,0xc1,0xf0,0xa3,0xe5,0x12,0xf0,0x12,0x45,0xb1,0xef,0x64, ++0x01,0x70,0x2e,0x90,0x9e,0x69,0x12,0x47,0xfa,0xe5,0x76,0x60,0x10,0x74,0x21,0x2f, ++0xf5,0x82,0xe4,0x34,0xfc,0xf5,0x83,0xe0,0x44,0x10,0xf0,0x80,0x0e,0x74,0x21,0x2f, ++0xf5,0x82,0xe4,0x34,0xfc,0xf5,0x83,0xe0,0x54,0xef,0xf0,0x90,0x04,0x1f,0x74,0x20, ++0xf0,0x22,0x90,0x9e,0xaf,0xef,0xf0,0x71,0xb0,0x90,0x9e,0xaf,0xe0,0x60,0x05,0x90, ++0x05,0x22,0xe4,0xf0,0x90,0x9e,0x5e,0xe0,0x54,0xf0,0xf0,0xe0,0x44,0x04,0xf0,0x22, ++0x90,0x00,0x11,0xe0,0x44,0x09,0xf0,0x12,0x49,0xb9,0x90,0x9d,0xff,0x12,0x43,0x53, ++0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0x78,0x7e,0x08,0x12,0x2f,0xd9,0x90,0x9e,0x03, ++0x12,0x43,0x53,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0x04,0x7e,0x0c,0x12,0x2f,0xd9, ++0x90,0x9e,0x07,0x12,0x43,0x53,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0x00,0x7e,0x08, ++0x12,0x2f,0xd9,0x90,0x9e,0x0b,0x12,0x43,0x53,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f, ++0x70,0x7e,0x0e,0x12,0x2f,0xd9,0x90,0x80,0x59,0x12,0x2a,0x8b,0x00,0x03,0x2d,0x95, ++0xe4,0xfd,0xff,0x12,0x34,0x81,0x90,0x9e,0x77,0xe0,0xb4,0x01,0x11,0x90,0x80,0x59, ++0x12,0x2a,0x8b,0x00,0x03,0x2d,0x95,0xe4,0xfd,0x7f,0x01,0x12,0x34,0x81,0x22,0x8f, ++0x27,0xe4,0x90,0x9e,0xa8,0xf0,0xa3,0xf0,0x90,0x01,0x09,0xe0,0x7f,0x00,0x30,0xe7, ++0x02,0x7f,0x01,0xef,0x65,0x27,0x60,0x3e,0xc3,0x90,0x9e,0xa9,0xe0,0x94,0x88,0x90, ++0x9e,0xa8,0xe0,0x94,0x13,0x40,0x08,0x90,0x01,0xc6,0xe0,0x44,0x80,0xf0,0x22,0x90, ++0x9e,0xa8,0xe4,0x75,0xf0,0x01,0x12,0x42,0x81,0x7f,0x14,0x7e,0x00,0x12,0x37,0x54, ++0xd3,0x90,0x9e,0xa9,0xe0,0x94,0x32,0x90,0x9e,0xa8,0xe0,0x94,0x00,0x40,0xb9,0x90, ++0x01,0xc7,0xe0,0x30,0xe0,0xb2,0x22,0x90,0x9e,0x5e,0xe0,0x54,0xf0,0xf0,0xe0,0x44, ++0x01,0xf0,0x12,0x44,0xff,0x12,0x45,0x00,0xe0,0x54,0xf0,0xf0,0xe0,0x44,0x02,0xf0, ++0x22,0x90,0x9e,0x60,0xe0,0x30,0xe6,0x1c,0xe0,0x54,0x0f,0xff,0x90,0x9e,0x4e,0xe0, ++0xfe,0x4f,0x90,0x01,0x2f,0xf0,0xee,0x64,0x80,0x90,0x9e,0x4e,0xf0,0x90,0x9e,0x60, ++0xe0,0x54,0xbf,0xf0,0x22,0x8f,0x75,0x12,0x45,0xb1,0xef,0x64,0x01,0x70,0x2e,0x90, ++0x9e,0x6a,0x12,0x47,0xfa,0xe5,0x75,0x60,0x10,0x74,0x21,0x2f,0xf5,0x82,0xe4,0x34, ++0xfc,0xf5,0x83,0xe0,0x44,0x10,0xf0,0x80,0x0e,0x74,0x21,0x2f,0xf5,0x82,0xe4,0x34, ++0xfc,0xf5,0x83,0xe0,0x54,0xef,0xf0,0x90,0x04,0x1f,0x74,0x20,0xf0,0x22,0xe4,0x90, ++0x9e,0x2f,0xf0,0xe5,0x74,0x60,0x6a,0xe5,0x73,0x64,0x01,0x70,0x64,0xe5,0x74,0x14, ++0x60,0x29,0x24,0xfd,0x60,0x25,0x24,0x02,0x24,0xfb,0x50,0x02,0x80,0x23,0x90,0x9e, ++0x50,0xe0,0x14,0xf0,0xe0,0x60,0x04,0xa3,0xe0,0x60,0x16,0x90,0x9e,0x50,0xe0,0x70, ++0x0a,0x90,0x9e,0x5f,0xe0,0x90,0x9e,0x50,0xf0,0x80,0x00,0x90,0x9e,0x2f,0x74,0x01, ++0xf0,0x90,0x9e,0x2f,0xe0,0x60,0x2a,0x90,0x9e,0x63,0xe0,0x44,0x10,0xf0,0xe4,0x90, ++0x9e,0x89,0xf0,0x90,0x9e,0x5a,0x12,0x44,0x56,0x90,0x01,0x57,0x74,0x05,0xf0,0x90, ++0x9e,0x5e,0xe0,0x54,0x0f,0xc3,0x94,0x04,0x50,0x07,0x7d,0x01,0x7f,0x04,0x12,0x47, ++0x1a,0x22,0xef,0xc3,0x94,0x20,0x50,0x39,0xef,0x30,0xe0,0x17,0xed,0xc4,0x54,0xf0, ++0xfd,0xef,0xc3,0x13,0xfe,0x24,0xa4,0xf5,0x82,0xe4,0x34,0x04,0xf5,0x83,0xe0,0x54, ++0x0f,0x80,0x10,0xef,0xc3,0x13,0xfe,0x24,0xa4,0xf5,0x82,0xe4,0x34,0x04,0xf5,0x83, ++0xe0,0x54,0xf0,0xf0,0x74,0xa4,0x2e,0xf5,0x82,0xe4,0x34,0x04,0xf5,0x83,0xe0,0x4d, ++0xf0,0x22,0xad,0x07,0xed,0xc3,0x94,0x20,0x50,0x0d,0x74,0x84,0x2d,0xf5,0x82,0xe4, ++0x34,0x04,0xf5,0x83,0xe0,0x80,0x0b,0x74,0xa6,0x2d,0xf5,0x82,0xe4,0x34,0x9c,0xf5, ++0x83,0xe0,0x54,0x7f,0xf5,0x64,0xe5,0x64,0x54,0x1f,0xfc,0x75,0xf0,0x09,0xed,0x90, ++0x96,0x48,0x12,0x43,0x5f,0xe0,0xff,0x90,0x9e,0x3e,0xf0,0xed,0x25,0xe0,0x24,0x02, ++0xf5,0x82,0xe4,0x34,0x95,0xf5,0x83,0xe0,0xfb,0xa3,0xe0,0x90,0x9e,0x3f,0xcb,0xf0, ++0xa3,0xeb,0xf0,0xed,0x25,0xe0,0x24,0xc6,0xf5,0x82,0xe4,0x34,0x9b,0xf5,0x83,0xe0, ++0xfb,0xa3,0xe0,0x90,0x9e,0x41,0xcb,0xf0,0xa3,0xeb,0xf0,0xec,0x25,0xe0,0x24,0x66, ++0xf5,0x82,0xe4,0x34,0x41,0xf5,0x83,0xe4,0x93,0xfa,0x74,0x01,0x93,0xfb,0xed,0x25, ++0xe0,0x24,0xc2,0xf5,0x82,0xe4,0x34,0x95,0xf5,0x83,0xea,0xf0,0xa3,0xeb,0xf0,0xec, ++0xc3,0x9f,0x40,0x02,0xc1,0xc9,0x74,0x67,0x2d,0xf5,0x82,0xe4,0x34,0x9d,0xf5,0x83, ++0xec,0xf0,0x04,0xfb,0x90,0x9e,0x3e,0xe0,0xff,0xeb,0xd3,0x9f,0x40,0x02,0xc1,0xfa, ++0xeb,0xc3,0x94,0x10,0x40,0x21,0xeb,0x24,0xf0,0xff,0x74,0x01,0x7e,0x00,0xa8,0x07, ++0x08,0x80,0x05,0xc3,0x33,0xce,0x33,0xce,0xd8,0xf9,0xff,0x90,0x9e,0x3f,0xe0,0x5e, ++0xfe,0xa3,0xe0,0x5f,0x4e,0x70,0x23,0xeb,0xc3,0x94,0x10,0x50,0x39,0x74,0x01,0x7e, ++0x00,0xa8,0x03,0x08,0x80,0x05,0xc3,0x33,0xce,0x33,0xce,0xd8,0xf9,0xff,0x90,0x9e, ++0x41,0xe0,0x5e,0xfe,0xa3,0xe0,0x5f,0x4e,0x60,0x1c,0xeb,0x64,0x13,0x60,0x08,0xeb, ++0x64,0x12,0x60,0x03,0xbb,0x11,0x09,0x90,0x9e,0x3f,0xe0,0x30,0xe0,0x02,0x7b,0x18, ++0xac,0x03,0x8c,0x64,0x80,0x34,0x0b,0x80,0x8b,0x90,0x9e,0x3e,0xe0,0xfb,0x6c,0x70, ++0x69,0x74,0x67,0x2d,0xf5,0x82,0xe4,0x34,0x9d,0xf5,0x83,0xec,0xf0,0x75,0xf0,0x09, ++0xed,0x90,0x96,0x4a,0x12,0x43,0x5f,0xe0,0xb4,0x01,0x0c,0xe5,0x64,0x20,0xe6,0x07, ++0xec,0x44,0x40,0xf5,0x64,0x80,0x03,0xaf,0x64,0x22,0xec,0x25,0xe0,0x24,0x9e,0xf5, ++0x82,0xe4,0x34,0x41,0xf5,0x83,0xe4,0x93,0xfe,0x74,0x01,0x93,0xff,0xec,0x25,0xe0, ++0x24,0x66,0xf5,0x82,0xe4,0x34,0x41,0xf5,0x83,0x74,0x01,0x93,0x2f,0xff,0xe4,0x93, ++0x3e,0xc3,0x13,0xfe,0xef,0x13,0xff,0xed,0x25,0xe0,0x24,0xc2,0xf5,0x82,0xe4,0x34, ++0x95,0xf5,0x83,0xee,0xf0,0xa3,0xef,0xf0,0x80,0x5b,0xec,0xd3,0x9b,0x40,0x56,0x90, ++0x9e,0x3e,0xe0,0xff,0x74,0x67,0x2d,0xf5,0x82,0xe4,0x34,0x9d,0xf5,0x83,0xef,0xf0, ++0xac,0x07,0x8f,0x64,0xec,0x25,0xe0,0x24,0x9e,0xf5,0x82,0xe4,0x34,0x41,0xf5,0x83, ++0xe4,0x93,0xfe,0x74,0x01,0x93,0xff,0xec,0x25,0xe0,0x24,0x66,0xf5,0x82,0xe4,0x34, ++0x41,0xf5,0x83,0x74,0x01,0x93,0x2f,0xff,0xe4,0x93,0x3e,0xc3,0x13,0xfe,0xef,0x13, ++0xff,0xed,0x25,0xe0,0x24,0xc2,0xf5,0x82,0xe4,0x34,0x95,0xf5,0x83,0xee,0xf0,0xa3, ++0xef,0xf0,0xaf,0x64,0x22,0x74,0x01,0x2d,0xf5,0x82,0xe4,0x34,0x94,0xf5,0x83,0xe4, ++0xf0,0xaf,0x05,0xe5,0x64,0x44,0x80,0xfd,0x12,0x58,0xf1,0xe5,0x64,0x44,0x80,0xff, ++0x22,0xac,0x07,0xec,0xc3,0x94,0x20,0x50,0x0d,0x74,0x84,0x2c,0xf5,0x82,0xe4,0x34, ++0x04,0xf5,0x83,0xe0,0x80,0x0b,0x74,0xa6,0x2c,0xf5,0x82,0xe4,0x34,0x9c,0xf5,0x83, ++0xe0,0x54,0x7f,0xf5,0x64,0xe5,0x64,0x54,0x1f,0xff,0x90,0x9e,0x40,0xf0,0x75,0xf0, ++0x09,0xec,0x90,0x96,0x49,0x12,0x43,0x5f,0xe0,0x90,0x9e,0x42,0xf0,0x75,0xf0,0x09, ++0xec,0x90,0x96,0x48,0x12,0x43,0x5f,0xe0,0xfe,0x90,0x9e,0x43,0xf0,0xec,0x25,0xe0, ++0x24,0xc6,0xf5,0x82,0xe4,0x34,0x9b,0xf5,0x83,0xe0,0xfb,0xa3,0xe0,0x90,0x9e,0x44, ++0xcb,0xf0,0xa3,0xeb,0xf0,0xec,0x25,0xe0,0x24,0x02,0xf5,0x82,0xe4,0x34,0x95,0xf5, ++0x83,0xe0,0xfb,0xa3,0xe0,0x90,0x9e,0x46,0xcb,0xf0,0xa3,0xeb,0xf0,0xef,0xd3,0x9e, ++0x40,0x0a,0x90,0x9e,0x43,0xe0,0x90,0x9e,0x40,0xf0,0xf5,0x64,0xed,0x70,0x02,0x21, ++0x07,0x90,0x9e,0x41,0xed,0xf0,0xe5,0x64,0x30,0xe6,0x0a,0x90,0x9e,0x40,0xe0,0xf5, ++0x64,0xa3,0xe0,0x14,0xf0,0x90,0x9e,0x41,0xe0,0x70,0x02,0x21,0x07,0x90,0x9e,0x40, ++0xe0,0xff,0xd3,0x94,0x00,0x50,0x02,0x21,0x07,0xe4,0x90,0x9e,0x3f,0xf0,0xef,0x14, ++0x90,0x9e,0x3e,0xf0,0x90,0x9e,0x42,0xe0,0xfd,0x90,0x9e,0x3e,0xe0,0xff,0xd3,0x9d, ++0x40,0x6b,0xef,0x94,0x10,0x40,0x21,0xef,0x24,0xf0,0xff,0x74,0x01,0x7e,0x00,0xa8, ++0x07,0x08,0x80,0x05,0xc3,0x33,0xce,0x33,0xce,0xd8,0xf9,0xff,0x90,0x9e,0x46,0xe0, ++0x5e,0xfe,0xa3,0xe0,0x5f,0x4e,0x70,0x27,0x90,0x9e,0x3e,0xe0,0xff,0xc3,0x94,0x10, ++0x50,0x33,0x74,0x01,0x7e,0x00,0xa8,0x07,0x08,0x80,0x05,0xc3,0x33,0xce,0x33,0xce, ++0xd8,0xf9,0xff,0x90,0x9e,0x44,0xe0,0x5e,0xfe,0xa3,0xe0,0x5f,0x4e,0x60,0x16,0x90, ++0x9e,0x3e,0xe0,0xf5,0x64,0xa3,0xe0,0x04,0xf0,0x90,0x9e,0x41,0xe0,0xff,0x90,0x9e, ++0x3f,0xe0,0x6f,0x60,0x08,0x90,0x9e,0x3e,0xe0,0x14,0xf0,0x80,0x87,0x90,0x9e,0x41, ++0xe0,0xff,0x90,0x9e,0x3f,0xe0,0xc3,0x9f,0x50,0x0d,0x90,0x9e,0x3e,0xe0,0xb5,0x05, ++0x06,0x90,0x9e,0x42,0xe0,0xf5,0x64,0xe5,0x64,0x25,0xe0,0x24,0x9e,0xf5,0x82,0xe4, ++0x34,0x41,0xf5,0x83,0xe4,0x93,0xfe,0x74,0x01,0x93,0xff,0xe5,0x64,0x25,0xe0,0x24, ++0x66,0xf5,0x82,0xe4,0x34,0x41,0xf5,0x83,0x74,0x01,0x93,0x2f,0xff,0xe4,0x93,0x3e, ++0xc3,0x13,0xfe,0xef,0x13,0xff,0xec,0x25,0xe0,0x24,0xc2,0xf5,0x82,0xe4,0x34,0x95, ++0xf5,0x83,0xee,0xf0,0xa3,0xef,0xf0,0xaf,0x04,0xad,0x64,0x12,0x58,0xf1,0xaf,0x64, ++0x22,0xe4,0xf5,0x59,0xe5,0x59,0xb4,0x20,0x14,0x90,0x9a,0xc5,0xe0,0x04,0xf0,0x90, ++0x95,0x01,0xe0,0xff,0x90,0x9a,0xc5,0xe0,0xb5,0x07,0x02,0xe4,0xf0,0x75,0xf0,0x09, ++0xe5,0x59,0x90,0x96,0x4b,0x12,0x43,0x5f,0xe0,0x64,0x01,0x60,0x02,0xe1,0x95,0xe5, ++0x59,0x25,0xe0,0x24,0x80,0xf5,0x82,0xe4,0x34,0x93,0xf5,0x83,0xe0,0xfe,0xa3,0xe0, ++0xd3,0x94,0x00,0xee,0x94,0x00,0x50,0x02,0xe1,0x95,0xe5,0x59,0x94,0x20,0x40,0x08, ++0x90,0x9a,0xc5,0xe0,0x60,0x02,0xe1,0xa0,0xe5,0x59,0x75,0xf0,0x0a,0xa4,0x24,0x00, ++0xf9,0x74,0x90,0x35,0xf0,0x75,0x5e,0x01,0xf5,0x5f,0x89,0x60,0xe5,0x59,0x25,0xe0, ++0x24,0x80,0xf5,0x82,0xe4,0x34,0x93,0xf5,0x83,0xe0,0xff,0xa3,0xe0,0x90,0x9e,0x38, ++0xcf,0xf0,0xa3,0xef,0xf0,0xe5,0x59,0x25,0xe0,0x24,0xc4,0xf5,0x82,0xe4,0x34,0x98, ++0xf5,0x83,0xe0,0xff,0xa3,0xe0,0x90,0x9e,0x3a,0xcf,0xf0,0xa3,0xef,0xf0,0xe5,0x59, ++0xc3,0x94,0x20,0x50,0x14,0x74,0x84,0x25,0x59,0xf5,0x82,0xe4,0x34,0x04,0xf5,0x83, ++0xe0,0x54,0x3f,0x90,0x9e,0x34,0xf0,0x80,0x12,0x74,0xa6,0x25,0x59,0xf5,0x82,0xe4, ++0x34,0x9c,0xf5,0x83,0xe0,0x54,0x3f,0x90,0x9e,0x34,0xf0,0x90,0x9e,0x34,0xe0,0xfe, ++0x54,0x1f,0xa3,0xf0,0x75,0xf0,0x09,0xe5,0x59,0x90,0x96,0x48,0x12,0x43,0x5f,0xe0, ++0x90,0x9e,0x3d,0xf0,0x74,0xe6,0x25,0x59,0xf5,0x82,0xe4,0x34,0x9c,0xf5,0x83,0xe0, ++0xc3,0x94,0x05,0x40,0x02,0x81,0x6e,0x90,0x9e,0x3d,0xe0,0xff,0x90,0x9e,0x35,0xe0, ++0x9f,0x40,0x13,0x90,0x9e,0x3d,0xe0,0x90,0x9e,0x35,0xf0,0xee,0x54,0x40,0xfe,0x90, ++0x9e,0x34,0xf0,0xef,0x4e,0xf0,0x90,0x04,0xfd,0xe0,0x64,0x01,0x70,0x29,0x90,0x9e, ++0x35,0xe0,0xff,0x90,0x41,0x4a,0x93,0xfe,0x74,0x44,0x25,0x59,0xf5,0x82,0xe4,0x34, ++0x9a,0xf5,0x83,0xe0,0xc3,0x9e,0x40,0x06,0xef,0x90,0x40,0xda,0x80,0x30,0x90,0x9e, ++0x35,0xe0,0x90,0x40,0xf6,0x80,0x27,0x90,0x9e,0x35,0xe0,0xff,0x90,0x41,0x4a,0x93, ++0xfe,0x74,0x44,0x25,0x59,0xf5,0x82,0xe4,0x34,0x9a,0xf5,0x83,0xe0,0xc3,0x9e,0x40, ++0x06,0xef,0x90,0x41,0x12,0x80,0x07,0x90,0x9e,0x35,0xe0,0x90,0x41,0x2e,0x93,0x90, ++0x9e,0x3c,0xf0,0x90,0x9e,0x3c,0xe0,0x75,0xf0,0x06,0xa4,0x24,0x50,0xf9,0x74,0x40, ++0x35,0xf0,0x75,0x5b,0xff,0xf5,0x5c,0x89,0x5d,0x90,0x9e,0x34,0xe0,0x90,0x41,0xf2, ++0x93,0xff,0xd3,0x90,0x9e,0x3b,0xe0,0x9f,0x90,0x9e,0x3a,0xe0,0x94,0x00,0x40,0x09, ++0xe4,0xfd,0xaf,0x59,0x12,0x67,0xb1,0xe1,0x2c,0xe5,0x59,0x25,0xe0,0x24,0xc2,0xf5, ++0x82,0xe4,0x34,0x95,0xf5,0x83,0xe0,0xf5,0x61,0xa3,0xe0,0xf5,0x62,0xab,0x5b,0xaa, ++0x5c,0xa9,0x5d,0x12,0x29,0xd9,0xff,0x7e,0x00,0xab,0x5e,0xaa,0x5f,0xa9,0x60,0x12, ++0x42,0x97,0xfd,0xac,0xf0,0x12,0x29,0xf2,0xef,0x25,0x62,0xf5,0x62,0xee,0x35,0x61, ++0xf5,0x61,0xab,0x5b,0xaa,0x5c,0xa9,0x5d,0x90,0x00,0x01,0x12,0x42,0x20,0xff,0x7e, ++0x00,0xab,0x5e,0xaa,0x5f,0xa9,0x60,0x90,0x00,0x02,0x12,0x42,0xc2,0xfd,0xac,0xf0, ++0x12,0x29,0xf2,0xef,0x25,0x62,0xf5,0x62,0xee,0x35,0x61,0xf5,0x61,0xab,0x5b,0xaa, ++0x5c,0xa9,0x5d,0x90,0x00,0x02,0x12,0x42,0x20,0xff,0x7e,0x00,0xab,0x5e,0xaa,0x5f, ++0xa9,0x60,0x90,0x00,0x04,0x12,0x42,0xc2,0xfd,0xac,0xf0,0x12,0x29,0xf2,0xef,0x25, ++0x62,0xf5,0x62,0xee,0x35,0x61,0xf5,0x61,0xab,0x5b,0xaa,0x5c,0xa9,0x5d,0x90,0x00, ++0x03,0x12,0x42,0x20,0xff,0x7e,0x00,0xab,0x5e,0xaa,0x5f,0xa9,0x60,0x90,0x00,0x06, ++0x12,0x42,0xc2,0xfd,0xac,0xf0,0x12,0x29,0xf2,0xef,0x25,0x62,0xf5,0x62,0xee,0x35, ++0x61,0xf5,0x61,0xab,0x5b,0xaa,0x5c,0xa9,0x5d,0x90,0x00,0x04,0x12,0x42,0x20,0xff, ++0x7e,0x00,0xab,0x5e,0xaa,0x5f,0xa9,0x60,0x90,0x00,0x08,0x12,0x42,0xc2,0xfd,0xac, ++0xf0,0x12,0x29,0xf2,0xef,0x25,0x62,0xf5,0x62,0xee,0x35,0x61,0xf5,0x61,0xab,0x5b, ++0xaa,0x5c,0xa9,0x5d,0x90,0x00,0x05,0x12,0x42,0x20,0xff,0x7e,0x00,0x90,0x9e,0x38, ++0xe0,0xfc,0xa3,0xe0,0xfd,0x12,0x29,0xf2,0xd3,0xe5,0x62,0x9f,0xe5,0x61,0x9e,0x40, ++0x0c,0xe5,0x62,0x9f,0xf5,0x62,0xe5,0x61,0x9e,0xf5,0x61,0x80,0x05,0xe4,0xf5,0x61, ++0xf5,0x62,0xe5,0x59,0x25,0xe0,0x24,0xc2,0xf5,0x82,0xe4,0x34,0x95,0xf5,0x83,0xe5, ++0x61,0xf0,0xa3,0xe5,0x62,0xf0,0x90,0x9e,0x34,0xe0,0x25,0xe0,0x24,0x66,0xf5,0x82, ++0xe4,0x34,0x41,0xf5,0x83,0xc3,0x74,0x01,0x93,0x95,0x62,0xe4,0x93,0x95,0x61,0x50, ++0x07,0xaf,0x59,0x12,0x65,0xb2,0xe1,0x00,0x90,0x9e,0x34,0xe0,0x25,0xe0,0x24,0x9e, ++0xf5,0x82,0xe4,0x34,0x41,0xf5,0x83,0xd3,0x74,0x01,0x93,0x95,0x62,0xe4,0x93,0x95, ++0x61,0x50,0x02,0xe1,0x00,0x7d,0x01,0xaf,0x59,0x12,0x67,0xb1,0xe1,0x00,0x74,0xe6, ++0x25,0x59,0xf5,0x82,0xe4,0x34,0x9c,0xf5,0x83,0xe0,0xfc,0x64,0x05,0x60,0x02,0xc1, ++0x09,0x90,0x96,0x43,0xe0,0xff,0xb4,0x03,0x0b,0x90,0x9e,0x35,0xe0,0xc3,0x94,0x19, ++0x40,0x3d,0x80,0x2e,0xef,0xb4,0x02,0x0b,0x90,0x9e,0x35,0xe0,0xc3,0x94,0x11,0x40, ++0x2e,0x80,0x1f,0x90,0x96,0x43,0xe0,0xff,0xb4,0x01,0x0b,0x90,0x9e,0x35,0xe0,0xc3, ++0x94,0x0a,0x40,0x1b,0x80,0x0c,0xef,0x70,0x11,0x90,0x9e,0x35,0xe0,0xc3,0x94,0x03, ++0x40,0x0d,0x90,0x9a,0x84,0x74,0x01,0xf0,0x80,0x05,0xe4,0x90,0x9a,0x84,0xf0,0x74, ++0x84,0x25,0x59,0xf5,0x82,0xe4,0x34,0x98,0xf5,0x83,0xe0,0xf5,0x63,0x74,0x44,0x25, ++0x59,0xf5,0x82,0xe4,0x34,0x9a,0xf5,0x83,0xe0,0xff,0xc3,0x94,0x30,0x50,0x02,0xa1, ++0xb6,0x90,0x9a,0x84,0xe0,0x64,0x01,0x60,0x02,0xa1,0xb6,0x74,0x85,0x25,0x59,0xf5, ++0x82,0xe4,0x34,0x9a,0xf5,0x83,0xe0,0x64,0x0a,0x60,0x51,0xef,0x24,0x05,0xff,0xe4, ++0x33,0xfe,0x74,0x41,0x25,0x59,0xf5,0x82,0xe4,0x34,0x94,0xf5,0x83,0xe0,0xfd,0xd3, ++0x9f,0xee,0x64,0x80,0xf8,0x74,0x80,0x98,0x50,0x32,0xed,0x24,0x05,0xff,0xe4,0x33, ++0xfe,0x74,0x44,0x25,0x59,0xf5,0x82,0xe4,0x34,0x9a,0xf5,0x83,0xe0,0xd3,0x9f,0xee, ++0x64,0x80,0xf8,0x74,0x80,0x98,0x50,0x14,0x74,0x26,0x25,0x59,0xf5,0x82,0xe4,0x34, ++0x9d,0xf5,0x83,0xe0,0xff,0x90,0x9e,0x35,0xe0,0x6f,0x60,0x3d,0x74,0x44,0x25,0x59, ++0xf5,0x82,0xe4,0x34,0x9a,0xf5,0x83,0xe0,0xff,0xd3,0x94,0x42,0x40,0x05,0x75,0x63, ++0x05,0x80,0x0e,0xef,0xd3,0x94,0x39,0x40,0x05,0x75,0x63,0x03,0x80,0x03,0x75,0x63, ++0x01,0x74,0x41,0x25,0x59,0xf5,0x82,0xe4,0x34,0x94,0xf5,0x83,0xef,0xf0,0x74,0x85, ++0x25,0x59,0xf5,0x82,0xe4,0x34,0x9a,0x80,0x29,0x74,0xe6,0x25,0x59,0xf5,0x82,0xe4, ++0x34,0x9c,0xf5,0x83,0xe4,0xf0,0x74,0x85,0x25,0x59,0xf5,0x82,0xe4,0x34,0x9a,0xf5, ++0x83,0xe0,0x04,0xf0,0x80,0x10,0xe4,0xf5,0x63,0x74,0xe6,0x25,0x59,0xf5,0x82,0xe4, ++0x34,0x9c,0xf5,0x83,0xe4,0xf0,0x90,0x9e,0x35,0xe0,0xff,0x74,0x26,0x25,0x59,0xf5, ++0x82,0xe4,0x34,0x9d,0xf5,0x83,0xef,0xf0,0x74,0x84,0x25,0x59,0xf5,0x82,0xe4,0x34, ++0x98,0xf5,0x83,0xe5,0x63,0xf0,0x75,0xf0,0x09,0xe5,0x59,0x90,0x96,0x4c,0x12,0x43, ++0x5f,0xe0,0xb4,0x01,0x10,0xe4,0xf5,0x63,0x74,0xe6,0x25,0x59,0xf5,0x82,0xe4,0x34, ++0x9c,0xf5,0x83,0xe4,0xf0,0xad,0x63,0xc1,0xfb,0xec,0x64,0x06,0x60,0x02,0xe1,0x00, ++0xf5,0x61,0xf5,0x62,0x90,0x42,0x13,0x93,0xff,0x7e,0x00,0x90,0x9e,0x38,0xe0,0xfc, ++0xa3,0xe0,0xfd,0x12,0x29,0xf2,0x90,0x9e,0x36,0xee,0xf0,0xa3,0xef,0xf0,0x74,0x84, ++0x25,0x59,0xf5,0x82,0xe4,0x34,0x98,0xf5,0x83,0xe0,0xf5,0x63,0xe4,0xf5,0x5a,0xab, ++0x5e,0xaa,0x5f,0xa9,0x60,0x75,0xf0,0x02,0xe5,0x5a,0xa4,0xf5,0x82,0x85,0xf0,0x83, ++0x12,0x42,0xc2,0xfd,0xac,0xf0,0xe5,0x5a,0x90,0x42,0x0e,0x93,0xff,0x7e,0x00,0x12, ++0x29,0xf2,0xef,0x25,0x62,0xf5,0x62,0xee,0x35,0x61,0xf5,0x61,0xc3,0x90,0x9e,0x37, ++0xe0,0x95,0x62,0x90,0x9e,0x36,0xe0,0x95,0x61,0x40,0x07,0x05,0x5a,0xe5,0x5a,0xb4, ++0x05,0xbd,0xe5,0x5a,0xc3,0x13,0xf5,0x5a,0xe5,0x63,0xb4,0x01,0x06,0xe5,0x5a,0x70, ++0x46,0x80,0x13,0xe5,0x63,0xb4,0x03,0x15,0xe5,0x5a,0x70,0x05,0x75,0x63,0x03,0x80, ++0x39,0xe5,0x5a,0xb4,0x01,0x05,0x75,0x63,0x01,0x80,0x2f,0x80,0x2a,0xe5,0x63,0xb4, ++0x05,0x28,0xe5,0x5a,0x70,0x05,0x75,0x63,0x05,0x80,0x0d,0xe5,0x5a,0xb4,0x01,0x05, ++0x75,0x63,0x03,0x80,0x03,0x75,0x63,0x01,0xd3,0x90,0x9e,0x3b,0xe0,0x94,0x03,0x90, ++0x9e,0x3a,0xe0,0x94,0x00,0x40,0x03,0xe4,0xf5,0x63,0xd3,0x90,0x9e,0x3b,0xe0,0x94, ++0x03,0x90,0x9e,0x3a,0xe0,0x94,0x00,0x40,0x03,0xe4,0xf5,0x63,0x74,0x84,0x25,0x59, ++0xf5,0x82,0xe4,0x34,0x98,0xf5,0x83,0xe5,0x63,0xf0,0xfd,0xaf,0x59,0x12,0x65,0x72, ++0x74,0xe6,0x25,0x59,0xf5,0x82,0xe4,0x34,0x9c,0xf5,0x83,0xe0,0xd3,0x94,0x05,0x74, ++0xe6,0x50,0x0e,0x25,0x59,0xf5,0x82,0xe4,0x34,0x9c,0xf5,0x83,0xe0,0x04,0xf0,0x80, ++0x0b,0x25,0x59,0xf5,0x82,0xe4,0x34,0x9c,0xf5,0x83,0xe4,0xf0,0xab,0x5e,0xaa,0x5f, ++0xa9,0x60,0xe4,0xf5,0xf0,0x12,0x42,0xfa,0xab,0x5e,0xaa,0x5f,0xa9,0x60,0x90,0x00, ++0x02,0xe4,0xf5,0xf0,0x12,0x43,0x19,0x90,0x00,0x04,0xe4,0xf5,0xf0,0x12,0x43,0x19, ++0x90,0x00,0x06,0xe4,0xf5,0xf0,0x12,0x43,0x19,0x90,0x00,0x08,0xe4,0xf5,0xf0,0x12, ++0x43,0x19,0xe5,0x59,0x25,0xe0,0x24,0x80,0xf5,0x82,0xe4,0x34,0x93,0xf5,0x83,0xe4, ++0xf0,0xa3,0xf0,0xe5,0x59,0x25,0xe0,0x24,0xc4,0xf5,0x82,0xe4,0x34,0x98,0xf5,0x83, ++0xe4,0xf0,0xa3,0xf0,0xe5,0x59,0x25,0xe0,0x24,0x44,0xf5,0x82,0xe4,0x34,0x99,0xf5, ++0x83,0xe4,0xf0,0xa3,0xf0,0x05,0x59,0xe5,0x59,0xc3,0x94,0x40,0x50,0x02,0x21,0x54, ++0x22,0x90,0x04,0x44,0x74,0x11,0xf0,0xa3,0x74,0xf0,0xf0,0xa3,0x74,0x0f,0xf0,0xa3, ++0xe4,0xf0,0xfd,0x74,0xa4,0x2d,0xf5,0x82,0xe4,0x34,0x04,0xf5,0x83,0xe4,0xf0,0x0d, ++0xbd,0x10,0xf0,0xe4,0x90,0x9a,0xc5,0xf0,0x90,0x95,0x01,0x04,0xf0,0xe4,0xfd,0x75, ++0xf0,0x0a,0xed,0x90,0x90,0x00,0x12,0x43,0x5f,0xe4,0xf0,0xa3,0xf0,0x75,0xf0,0x0a, ++0xed,0x90,0x90,0x02,0x12,0x43,0x5f,0xe4,0xf0,0xa3,0xf0,0x75,0xf0,0x0a,0xed,0x90, ++0x90,0x04,0x12,0x43,0x5f,0xe4,0xf0,0xa3,0xf0,0x75,0xf0,0x0a,0xed,0x90,0x90,0x06, ++0x12,0x43,0x5f,0xe4,0xf0,0xa3,0xf0,0x75,0xf0,0x0a,0xed,0x90,0x90,0x08,0x12,0x43, ++0x5f,0xe4,0xf0,0xa3,0xf0,0x74,0x26,0x2d,0xf5,0x82,0xe4,0x34,0x9d,0xf5,0x83,0x74, ++0x13,0xf0,0x74,0x85,0x2d,0xf5,0x82,0xe4,0x34,0x9a,0xf5,0x83,0xe4,0xf0,0x74,0x84, ++0x2d,0xf5,0x82,0xe4,0x34,0x98,0xf5,0x83,0xe4,0xf0,0xed,0x25,0xe0,0x24,0x80,0xf5, ++0x82,0xe4,0x34,0x93,0xf5,0x83,0xe4,0xf0,0xa3,0xf0,0xed,0x25,0xe0,0x24,0xc4,0xf5, ++0x82,0xe4,0x34,0x98,0xf5,0x83,0xe4,0xf0,0xa3,0xf0,0xed,0x25,0xe0,0x24,0xc4,0xf5, ++0x82,0xe4,0x34,0x99,0xf5,0x83,0xe4,0xf0,0xa3,0xf0,0xed,0x25,0xe0,0x24,0x44,0xf5, ++0x82,0xe4,0x34,0x99,0xf5,0x83,0xe4,0xf0,0xa3,0xf0,0xed,0x25,0xe0,0x24,0xc6,0xf5, ++0x82,0xe4,0x34,0x9a,0xf5,0x83,0xe4,0xf0,0xa3,0xf0,0xed,0x25,0xe0,0x24,0x46,0xf5, ++0x82,0xe4,0x34,0x9b,0xf5,0x83,0xe4,0xf0,0xa3,0xf0,0x74,0x86,0x2d,0xf5,0x82,0xe4, ++0x34,0x9c,0xf5,0x83,0xe4,0xf0,0x74,0x46,0x2d,0xf5,0x82,0xe4,0x34,0x9c,0xf5,0x83, ++0xe4,0xf0,0x74,0xe6,0x2d,0xf5,0x82,0xe4,0x34,0x9c,0xf5,0x83,0xe4,0xf0,0x90,0x41, ++0xc4,0x93,0xfe,0x74,0x01,0x93,0xff,0x90,0x41,0x8c,0x74,0x01,0x93,0x2f,0xff,0xe4, ++0x93,0x3e,0xc3,0x13,0xfe,0xef,0x13,0xff,0xed,0x25,0xe0,0x24,0xc2,0xf5,0x82,0xe4, ++0x34,0x95,0xf5,0x83,0xee,0xf0,0xa3,0xef,0xf0,0x75,0xf0,0x09,0xed,0x90,0x96,0x4b, ++0x12,0x43,0x5f,0x74,0x01,0xf0,0x75,0xf0,0x09,0xed,0x90,0x96,0x4a,0x12,0x43,0x5f, ++0x74,0x01,0xf0,0x74,0x82,0x2d,0xf5,0x82,0xe4,0x34,0x95,0xf5,0x83,0x74,0x0c,0xf0, ++0x75,0xf0,0x09,0xed,0x90,0x96,0x46,0x12,0x43,0x5f,0x74,0xff,0xf0,0xa3,0xf0,0x75, ++0xf0,0x09,0xed,0x90,0x96,0x44,0x12,0x43,0x5f,0xe4,0xf0,0xa3,0x74,0x0f,0xf0,0x75, ++0xf0,0x09,0xed,0x90,0x96,0x48,0x12,0x43,0x5f,0x74,0x13,0xf0,0x75,0xf0,0x09,0xed, ++0x90,0x96,0x49,0x12,0x43,0x5f,0xe4,0xf0,0xed,0xc3,0x94,0x20,0x50,0x0f,0x74,0x84, ++0x2d,0xf5,0x82,0xe4,0x34,0x04,0xf5,0x83,0x74,0x13,0xf0,0x80,0x0d,0x74,0xa6,0x2d, ++0xf5,0x82,0xe4,0x34,0x9c,0xf5,0x83,0x74,0x13,0xf0,0x0d,0xed,0x64,0x40,0x60,0x03, ++0x02,0x6f,0xcf,0x22,0x12,0x29,0xd9,0xf5,0x59,0xc3,0x94,0x40,0x50,0x15,0x90,0x00, ++0x02,0x12,0x42,0x20,0xff,0x74,0x44,0x25,0x59,0xf5,0x82,0xe4,0x34,0x9a,0xf5,0x83, ++0xef,0xf0,0x22,0xe5,0x59,0xb4,0x40,0x0a,0x90,0x00,0x02,0x12,0x42,0x20,0x90,0x96, ++0x42,0xf0,0x22,0x90,0x00,0x04,0x12,0x42,0x20,0xff,0x54,0x3f,0xfe,0xef,0x54,0x80, ++0xc4,0x13,0x13,0x13,0x54,0x01,0xfd,0xaf,0x06,0x02,0x53,0xa4,0x12,0x29,0xd9,0x90, ++0x95,0x01,0xf0,0x22,0x12,0x29,0xd9,0xf5,0x73,0x22,0x90,0x00,0x02,0x12,0x42,0x20, ++0xff,0x30,0xe0,0x25,0x12,0x29,0xd9,0x90,0x9e,0x56,0xf0,0x90,0x00,0x01,0x12,0x42, ++0x20,0x90,0x9e,0x57,0xf0,0xef,0xc3,0x13,0x54,0x7f,0x90,0x9e,0x55,0xf0,0x90,0x00, ++0x03,0x12,0x42,0x20,0x90,0x9e,0x5b,0xf0,0x22,0x90,0x9e,0x56,0x74,0x01,0xf0,0x90, ++0x9e,0x57,0x74,0x03,0xf0,0x90,0x9e,0x55,0x74,0x14,0xf0,0x90,0x9e,0x5b,0x74,0x05, ++0xf0,0x22,0x12,0x29,0xd9,0x30,0xe0,0x18,0xc3,0x13,0x54,0x7f,0x90,0x9e,0x5a,0xf0, ++0x90,0x00,0x01,0x12,0x42,0x20,0xff,0x90,0x9e,0x58,0xe4,0xf0,0xa3,0xef,0xf0,0x22, ++0x90,0x9e,0x5a,0x74,0x07,0xf0,0x90,0x9e,0x58,0xe4,0xf0,0xa3,0x74,0x02,0xf0,0x22, ++0x90,0x02,0x09,0xe0,0xfd,0x12,0x29,0xd9,0xfe,0xaf,0x05,0xed,0x2e,0x90,0x9e,0x67, ++0xf0,0x90,0x00,0x01,0x12,0x42,0x20,0xff,0xed,0x2f,0x90,0x9e,0x68,0xf0,0x90,0x00, ++0x02,0x12,0x42,0x20,0xff,0xed,0x2f,0x90,0x9e,0x69,0xf0,0x90,0x00,0x03,0x12,0x42, ++0x20,0xff,0xed,0x2f,0x90,0x9e,0x6a,0xf0,0x90,0x00,0x04,0x12,0x42,0x20,0xff,0xae, ++0x05,0xed,0x2f,0x90,0x9e,0x6b,0xf0,0x22,0xd3,0x10,0xaf,0x01,0xc3,0xc0,0xd0,0x90, ++0x9e,0x3f,0x12,0x43,0x8b,0x90,0x9e,0x3f,0x12,0x43,0x6b,0x90,0x00,0x01,0x12,0x42, ++0xc2,0xfa,0xe5,0xf0,0x24,0x00,0xff,0xe4,0x3a,0xfe,0x90,0x9e,0x3f,0x12,0x43,0x6b, ++0x90,0x00,0x01,0xee,0x8f,0xf0,0x12,0x43,0x19,0x12,0x29,0xd9,0xff,0x60,0x2c,0xb5, ++0x22,0x16,0x90,0x9e,0x3f,0x12,0x43,0x6b,0x90,0x00,0x01,0x12,0x42,0xc2,0x65,0x24, ++0x70,0x04,0xe5,0x23,0x65,0xf0,0x60,0x23,0x90,0x9e,0x3f,0x12,0x43,0x6b,0x90,0x00, ++0x01,0x12,0x42,0xc2,0xff,0xae,0xf0,0x71,0x00,0x80,0x10,0x90,0x9e,0x3f,0x12,0x43, ++0x6b,0x12,0x29,0xd9,0x65,0x22,0x60,0x03,0x12,0x44,0xca,0xd0,0xd0,0x92,0xaf,0x22, ++0x90,0x9e,0x42,0xee,0xf0,0xa3,0xef,0xf0,0x75,0x22,0x01,0x8e,0x23,0xf5,0x24,0xe4, ++0xfd,0x7f,0x0b,0x71,0x44,0xe4,0xfd,0x7f,0x02,0x71,0x44,0x12,0x4f,0xbe,0xe4,0xff, ++0x12,0x44,0xf1,0xe4,0xf5,0x26,0x90,0x01,0xc9,0xe5,0x26,0xf0,0x90,0x9e,0x42,0xe0, ++0xfc,0xa3,0xe0,0xfd,0xec,0xfb,0x8d,0x44,0xe4,0xf5,0x45,0x7d,0x01,0x7f,0x60,0x7e, ++0x01,0x02,0x35,0xab,0xd3,0x10,0xaf,0x01,0xc3,0xc0,0xd0,0x90,0x9e,0x45,0xed,0xf0, ++0x90,0x9e,0x44,0xef,0xf0,0xd3,0x94,0x07,0x50,0x4f,0xa3,0xe0,0x70,0x1a,0x90,0x9e, ++0x44,0xe0,0xff,0x74,0x01,0xa8,0x07,0x08,0x80,0x02,0xc3,0x33,0xd8,0xfc,0xf4,0xff, ++0x90,0x00,0x47,0xe0,0x5f,0xf0,0x80,0x17,0x90,0x9e,0x44,0xe0,0xff,0x74,0x01,0xa8, ++0x07,0x08,0x80,0x02,0xc3,0x33,0xd8,0xfc,0xff,0x90,0x00,0x47,0xe0,0x4f,0xf0,0x12, ++0x49,0xb9,0x90,0x9e,0x44,0xe0,0xff,0x74,0x01,0xa8,0x07,0x08,0x80,0x02,0xc3,0x33, ++0xd8,0xfc,0xf4,0xff,0x90,0x00,0x46,0x80,0x5a,0x90,0x9e,0x44,0xe0,0x24,0xf8,0xf0, ++0xa3,0xe0,0x70,0x1d,0x90,0x9e,0x44,0xe0,0xff,0x74,0x01,0xa8,0x07,0x08,0x80,0x02, ++0xc3,0x33,0xd8,0xfc,0xc4,0x54,0xf0,0xf4,0xff,0x90,0x00,0x43,0xe0,0x5f,0xf0,0x80, ++0x1a,0x90,0x9e,0x44,0xe0,0xff,0x74,0x01,0xa8,0x07,0x08,0x80,0x02,0xc3,0x33,0xd8, ++0xfc,0xc4,0x54,0xf0,0xff,0x90,0x00,0x43,0xe0,0x4f,0xf0,0x12,0x49,0xb9,0x90,0x9e, ++0x44,0xe0,0xff,0x74,0x01,0xa8,0x07,0x08,0x80,0x02,0xc3,0x33,0xd8,0xfc,0xf4,0xff, ++0x90,0x00,0x43,0xe0,0x5f,0xf0,0x12,0x49,0xb9,0xd0,0xd0,0x92,0xaf,0x22,0xd3,0x10, ++0xaf,0x01,0xc3,0xc0,0xd0,0x90,0x9e,0x6d,0xe0,0x90,0x9e,0x40,0xf0,0x90,0x9e,0x6e, ++0xe0,0xf5,0x64,0xa3,0xe0,0xf5,0x65,0xe4,0xf5,0x61,0x74,0x70,0x25,0x61,0xf5,0x82, ++0xe4,0x34,0x9e,0xf5,0x83,0xe0,0xff,0x74,0x66,0x25,0x61,0xf8,0xa6,0x07,0x05,0x61, ++0xe5,0x61,0xb4,0x04,0xe5,0x90,0x9e,0x40,0xe0,0x12,0x43,0x94,0x74,0x6b,0x00,0x75, ++0x93,0x01,0x74,0x71,0x02,0x74,0x71,0x03,0x74,0x71,0x04,0x75,0x93,0x05,0x75,0x63, ++0x80,0x75,0x79,0x81,0x75,0x93,0x82,0x00,0x00,0x75,0x8f,0xaf,0x69,0xb1,0x9a,0xa1, ++0x93,0x90,0x9e,0x40,0xe0,0xff,0xb4,0x02,0x08,0x90,0x9e,0x3f,0x74,0x01,0xf0,0x80, ++0x0f,0xef,0x90,0x9e,0x3f,0xb4,0x03,0x05,0x74,0x02,0xf0,0x80,0x03,0x74,0x04,0xf0, ++0xc3,0xe5,0x64,0x94,0x08,0x50,0x49,0xe4,0xf5,0x61,0x90,0x9e,0x3f,0xe0,0xff,0xe5, ++0x61,0xc3,0x9f,0x40,0x02,0xa1,0x93,0xc3,0xe5,0x64,0x94,0x01,0x50,0x14,0xe5,0x61, ++0x25,0x65,0xff,0xc3,0x74,0x03,0x95,0x61,0x24,0x66,0xf8,0xe6,0xfd,0x12,0x4a,0xc1, ++0x80,0x1a,0xc3,0x74,0x03,0x95,0x61,0x24,0x66,0xf8,0xe6,0xff,0xe5,0x61,0x7c,0x00, ++0x25,0x65,0xfd,0xec,0x35,0x64,0x8d,0x82,0xf5,0x83,0xef,0xf0,0x05,0x61,0x80,0xba, ++0xc3,0xe5,0x64,0x94,0x10,0x40,0x02,0xa1,0x93,0x90,0x9e,0x40,0xe0,0x64,0x04,0x60, ++0x02,0xa1,0x93,0xaf,0x67,0xfc,0xfd,0xfe,0x78,0x10,0x12,0x2a,0x6c,0xc0,0x04,0xc0, ++0x05,0xc0,0x06,0xc0,0x07,0xaf,0x66,0xe4,0xfc,0xfd,0xfe,0x78,0x18,0x12,0x2a,0x6c, ++0xd0,0x03,0xd0,0x02,0xd0,0x01,0xd0,0x00,0x12,0x43,0x46,0xc0,0x04,0xc0,0x05,0xc0, ++0x06,0xc0,0x07,0xaf,0x68,0xe4,0xfc,0xfd,0xfe,0x78,0x08,0x12,0x2a,0x6c,0xd0,0x03, ++0xd0,0x02,0xd0,0x01,0xd0,0x00,0x12,0x43,0x46,0xa8,0x04,0xa9,0x05,0xaa,0x06,0xab, ++0x07,0xaf,0x69,0xe4,0xfc,0xfd,0xfe,0x12,0x43,0x46,0xa3,0x12,0x2a,0x7f,0x90,0x9e, ++0x41,0x12,0x43,0x53,0x90,0x80,0x85,0x12,0x2a,0x7f,0xaf,0x65,0xae,0x64,0x12,0x2f, ++0xd9,0x80,0x30,0xe5,0x68,0x7f,0x00,0xfe,0xef,0x25,0x69,0xf5,0x63,0xe4,0x3e,0xf5, ++0x62,0xaf,0x63,0xfe,0x12,0x37,0x54,0x80,0x1a,0xe5,0x68,0x7f,0x00,0xfe,0xef,0x25, ++0x69,0xf5,0x63,0xe4,0x3e,0xf5,0x62,0xaf,0x63,0xfe,0x12,0x36,0xcb,0x80,0x04,0x7f, ++0x00,0x80,0x02,0x7f,0x01,0xd0,0xd0,0x92,0xaf,0x22,0x8f,0x6a,0xe4,0x90,0x9e,0x45, ++0xf0,0xe5,0x6a,0x14,0xfe,0x90,0x9e,0x45,0xe0,0xff,0xc3,0x9e,0x50,0x0e,0xef,0x04, ++0xfd,0x12,0x34,0xb7,0x90,0x9e,0x45,0xe0,0x04,0xf0,0x80,0xe5,0xe5,0x6a,0x14,0xff, ++0x7d,0xff,0x12,0x34,0xb7,0x90,0x9e,0x45,0xe5,0x6a,0xf0,0x90,0x9e,0x45,0xe0,0xc3, ++0x94,0xff,0x50,0x0f,0xe0,0xff,0x04,0xfd,0x12,0x34,0xb7,0x90,0x9e,0x45,0xe0,0x04, ++0xf0,0x80,0xe8,0xad,0x6a,0x7f,0xff,0x02,0x34,0xb7,0xd3,0x10,0xaf,0x01,0xc3,0xc0, ++0xd0,0xe4,0xf5,0x5b,0x75,0x5c,0x04,0xf5,0x5d,0xf5,0x5f,0xf5,0x60,0x90,0x02,0x09, ++0xe0,0xff,0x12,0x29,0xd9,0xfe,0xef,0x2e,0xf5,0x5e,0x30,0xe0,0x08,0x75,0x59,0x00, ++0x75,0x5a,0x80,0x80,0x05,0xe4,0xf5,0x59,0xf5,0x5a,0xe5,0x5e,0xc3,0x13,0x90,0xfd, ++0x10,0xf0,0x74,0x20,0x25,0x5b,0xf5,0x5b,0xad,0x5a,0xe5,0x5b,0x2d,0xff,0x24,0x01, ++0xf5,0x82,0xe4,0x34,0xfc,0xf5,0x83,0xe0,0x90,0x9e,0x6d,0xf0,0x74,0x02,0x2f,0xf5, ++0x82,0xe4,0x34,0xfc,0xf5,0x83,0xe0,0xfe,0xe5,0x5b,0x2d,0x24,0x03,0xf5,0x82,0xe4, ++0x34,0xfc,0xf5,0x83,0xe0,0x24,0x00,0xff,0xe4,0x3e,0x90,0x9e,0x6e,0xf0,0xa3,0xef, ++0xf0,0x7f,0x04,0xe5,0x5b,0x25,0x5a,0x2f,0x24,0x00,0xf5,0x82,0xe4,0x34,0xfc,0xf5, ++0x83,0xe0,0xfe,0x74,0x6c,0x2f,0xf5,0x82,0xe4,0x34,0x9e,0xf5,0x83,0xee,0xf0,0x0f, ++0xbf,0x08,0xe0,0x91,0x0e,0xef,0x70,0x3f,0x90,0x01,0xc3,0xe0,0x60,0x25,0xc3,0xe5, ++0x60,0x94,0xe8,0xe5,0x5f,0x94,0x03,0x40,0x09,0x90,0x01,0xc6,0xe0,0x44,0x10,0xf0, ++0x80,0x63,0x05,0x60,0xe5,0x60,0x70,0x02,0x05,0x5f,0x7f,0x0a,0x7e,0x00,0x12,0x37, ++0x54,0x80,0xd5,0x90,0x01,0xc6,0xe0,0x90,0x01,0xc3,0x30,0xe2,0x05,0x74,0xfe,0xf0, ++0x80,0x43,0x74,0xff,0xf0,0x80,0x3e,0xe5,0x5b,0xb4,0x78,0x23,0xe4,0xf5,0x5b,0x05, ++0x5e,0xe5,0x5a,0x64,0x80,0x45,0x59,0x70,0x06,0xf5,0x59,0xf5,0x5a,0x80,0x06,0x75, ++0x59,0x00,0x75,0x5a,0x80,0xe5,0x5e,0xc3,0x13,0x90,0xfd,0x10,0xf0,0x80,0x06,0x74, ++0x08,0x25,0x5b,0xf5,0x5b,0xe5,0x5d,0x15,0x5d,0x70,0x02,0x15,0x5c,0xe5,0x5d,0x45, ++0x5c,0x60,0x02,0xc1,0x28,0xd0,0xd0,0x92,0xaf,0x22,0x90,0x06,0x34,0x74,0xff,0xf0, ++0xe4,0xa3,0xf0,0xa3,0xf0,0xa3,0xf0,0x22,0xe4,0xf5,0x25,0x22,0xe4,0x90,0x9e,0xaa, ++0xf0,0xa3,0xf0,0x90,0x05,0xf8,0xe0,0x70,0x0f,0xa3,0xe0,0x70,0x0b,0xa3,0xe0,0x70, ++0x07,0xa3,0xe0,0x70,0x03,0x7f,0x01,0x22,0xd3,0x90,0x9e,0xab,0xe0,0x94,0xe8,0x90, ++0x9e,0xaa,0xe0,0x94,0x03,0x40,0x03,0x7f,0x00,0x22,0x7f,0x32,0x7e,0x00,0x12,0x37, ++0x54,0x90,0x9e,0xaa,0xe4,0x75,0xf0,0x01,0x12,0x42,0x81,0x80,0xc6,0x90,0x9e,0x77, ++0xe0,0x90,0x9e,0x0f,0xf0,0x22,0xef,0x70,0x03,0x02,0x79,0x1e,0x90,0x9e,0x0f,0xe0, ++0x60,0x03,0x02,0x7c,0xe9,0x90,0x9d,0xfb,0x12,0x43,0x53,0x90,0x80,0x85,0x12,0x2a, ++0x7f,0x7f,0x8c,0x7e,0x08,0x12,0x2f,0xd9,0x90,0x9d,0xa7,0x12,0x43,0x53,0x90,0x80, ++0x85,0x12,0x2a,0x7f,0x7f,0x44,0x7e,0x08,0x12,0x2f,0xd9,0x90,0x9d,0xab,0x12,0x43, ++0x53,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0x5c,0x7e,0x08,0x12,0x2f,0xd9,0x90,0x9d, ++0xaf,0x12,0x43,0x53,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0x6c,0x7e,0x0e,0x12,0x2f, ++0xd9,0x90,0x9d,0xb3,0x12,0x43,0x53,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0x70,0x7e, ++0x0e,0x12,0x2f,0xd9,0x90,0x9d,0xb7,0x12,0x43,0x53,0x90,0x80,0x85,0x12,0x2a,0x7f, ++0x7f,0x74,0x7e,0x0e,0x12,0x2f,0xd9,0x90,0x9d,0xbb,0x12,0x43,0x53,0x90,0x80,0x85, ++0x12,0x2a,0x7f,0x7f,0x78,0x7e,0x0e,0x12,0x2f,0xd9,0x90,0x9d,0xbf,0x12,0x43,0x53, ++0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0x7c,0x7e,0x0e,0x12,0x2f,0xd9,0x90,0x9d,0xc3, ++0x12,0x43,0x53,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0x80,0x7e,0x0e,0x12,0x2f,0xd9, ++0x90,0x9d,0xc7,0x12,0x43,0x53,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0x84,0x7e,0x0e, ++0x12,0x2f,0xd9,0x90,0x9d,0xcb,0x12,0x43,0x53,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f, ++0x88,0x7e,0x0e,0x12,0x2f,0xd9,0x90,0x9d,0xcf,0x12,0x43,0x53,0x90,0x80,0x85,0x12, ++0x2a,0x7f,0x7f,0x8c,0x7e,0x0e,0x12,0x2f,0xd9,0x90,0x9d,0xd3,0x12,0x43,0x53,0x90, ++0x80,0x85,0x12,0x2a,0x7f,0x7f,0xd0,0x7e,0x0e,0x12,0x2f,0xd9,0x90,0x9d,0xd7,0x12, ++0x43,0x53,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0xd4,0x7e,0x0e,0x12,0x2f,0xd9,0x90, ++0x9d,0xdb,0x12,0x43,0x53,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0xd8,0x7e,0x0e,0x12, ++0x2f,0xd9,0x90,0x9d,0xdf,0x12,0x43,0x53,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0xdc, ++0x7e,0x0e,0x12,0x2f,0xd9,0x90,0x9d,0xe3,0x12,0x43,0x53,0x90,0x80,0x85,0x12,0x2a, ++0x7f,0x7f,0xe0,0x7e,0x0e,0x12,0x2f,0xd9,0x90,0x9d,0xe7,0x12,0x43,0x53,0x90,0x80, ++0x85,0x12,0x2a,0x7f,0x7f,0xec,0x7e,0x0e,0x12,0x2f,0xd9,0x90,0x9d,0xeb,0x12,0x43, ++0x53,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0x04,0x7e,0x0c,0x12,0x2f,0xd9,0x90,0x9d, ++0xef,0x12,0x43,0x53,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0x04,0x7e,0x0d,0x12,0x2f, ++0xd9,0x90,0x9d,0xf3,0x12,0x43,0x53,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0x0c,0x7e, ++0x09,0x12,0x2f,0xd9,0x90,0x9d,0xf7,0x12,0x43,0x53,0x90,0x80,0x85,0x12,0x2a,0x7f, ++0x7f,0x04,0x7e,0x08,0x12,0x2f,0xd9,0x90,0x9e,0x0f,0x74,0x01,0xf0,0x22,0x90,0x9e, ++0x0f,0xe0,0x64,0x01,0x60,0x02,0x81,0xe9,0x7f,0x8c,0x7e,0x08,0x12,0x27,0xde,0x90, ++0x9d,0xfb,0x12,0x2a,0x7f,0x7f,0x44,0x7e,0x08,0x12,0x27,0xde,0x90,0x9d,0xa7,0x12, ++0x2a,0x7f,0x7f,0x5c,0x7e,0x08,0x12,0x27,0xde,0x90,0x9d,0xab,0x12,0x2a,0x7f,0x7f, ++0x6c,0x7e,0x0e,0x12,0x27,0xde,0x90,0x9d,0xaf,0x12,0x2a,0x7f,0x7f,0x70,0x7e,0x0e, ++0x12,0x27,0xde,0x90,0x9d,0xb3,0x12,0x2a,0x7f,0x7f,0x74,0x7e,0x0e,0x12,0x27,0xde, ++0x90,0x9d,0xb7,0x12,0x2a,0x7f,0x7f,0x78,0x7e,0x0e,0x12,0x27,0xde,0x90,0x9d,0xbb, ++0x12,0x2a,0x7f,0x7f,0x7c,0x7e,0x0e,0x12,0x27,0xde,0x90,0x9d,0xbf,0x12,0x2a,0x7f, ++0x7f,0x80,0x7e,0x0e,0x12,0x27,0xde,0x90,0x9d,0xc3,0x12,0x2a,0x7f,0x7f,0x84,0x7e, ++0x0e,0x12,0x27,0xde,0x90,0x9d,0xc7,0x12,0x2a,0x7f,0x7f,0x88,0x7e,0x0e,0x12,0x27, ++0xde,0x90,0x9d,0xcb,0x12,0x2a,0x7f,0x7f,0x8c,0x7e,0x0e,0x12,0x27,0xde,0x90,0x9d, ++0xcf,0x12,0x2a,0x7f,0x7f,0xd0,0x7e,0x0e,0x12,0x27,0xde,0x90,0x9d,0xd3,0x12,0x2a, ++0x7f,0x7f,0xd4,0x7e,0x0e,0x12,0x27,0xde,0x90,0x9d,0xd7,0x12,0x2a,0x7f,0x7f,0xd8, ++0x7e,0x0e,0x12,0x27,0xde,0x90,0x9d,0xdb,0x12,0x2a,0x7f,0x7f,0xdc,0x7e,0x0e,0x12, ++0x27,0xde,0x90,0x9d,0xdf,0x12,0x2a,0x7f,0x7f,0xe0,0x7e,0x0e,0x12,0x27,0xde,0x90, ++0x9d,0xe3,0x12,0x2a,0x7f,0x7f,0xec,0x7e,0x0e,0x12,0x27,0xde,0x90,0x9d,0xe7,0x12, ++0x2a,0x7f,0x7f,0x04,0x7e,0x0c,0x12,0x27,0xde,0x90,0x9d,0xeb,0x12,0x2a,0x7f,0x7f, ++0x04,0x7e,0x0d,0x12,0x27,0xde,0x90,0x9d,0xef,0x12,0x2a,0x7f,0x7f,0x0c,0x7e,0x09, ++0x12,0x27,0xde,0x90,0x9d,0xf3,0x12,0x2a,0x7f,0x7f,0x04,0x7e,0x08,0x12,0x27,0xde, ++0x90,0x9d,0xf7,0x12,0x2a,0x7f,0x7f,0x8c,0x7e,0x08,0x12,0x27,0xde,0x90,0x9e,0xa4, ++0x12,0x2a,0x7f,0x90,0x9e,0xa4,0x12,0x43,0x53,0xed,0x44,0xc0,0xfd,0xec,0x90,0x9e, ++0xa4,0x12,0x2a,0x7f,0x90,0x9e,0xa4,0x12,0x43,0x53,0x90,0x80,0x85,0x12,0x2a,0x7f, ++0x7f,0x8c,0x7e,0x08,0x12,0x2f,0xd9,0x90,0x80,0x85,0x12,0x2a,0x8b,0x00,0x01,0x00, ++0x00,0x7f,0x44,0x7e,0x08,0x12,0x2f,0xd9,0x90,0x80,0x85,0x12,0x2a,0x8b,0x00,0xdb, ++0x25,0xa4,0x7f,0x5c,0x7e,0x08,0x12,0x2f,0xd9,0x90,0x80,0x85,0x12,0x2a,0x8b,0x20, ++0xdb,0x25,0xa4,0x7f,0x6c,0x7e,0x0e,0x12,0x2f,0xd9,0x90,0x80,0x85,0x12,0x2a,0x8b, ++0x20,0xdb,0x25,0xa4,0x7f,0x70,0x7e,0x0e,0x12,0x2f,0xd9,0x90,0x80,0x85,0x12,0x2a, ++0x8b,0x04,0x1b,0x25,0xa4,0x7f,0x74,0x7e,0x0e,0x12,0x2f,0xd9,0x90,0x80,0x85,0x12, ++0x2a,0x8b,0x04,0x1b,0x25,0xa4,0x7f,0x78,0x7e,0x0e,0x12,0x2f,0xd9,0x90,0x80,0x85, ++0x12,0x2a,0x8b,0x04,0x1b,0x25,0xa4,0x7f,0x7c,0x7e,0x0e,0x12,0x2f,0xd9,0x90,0x80, ++0x85,0x12,0x2a,0x8b,0x04,0x1b,0x25,0xa4,0x7f,0x80,0x7e,0x0e,0x12,0x2f,0xd9,0x90, ++0x80,0x85,0x12,0x2a,0x8b,0x63,0xdb,0x25,0xa4,0x7f,0x84,0x7e,0x0e,0x12,0x2f,0xd9, ++0x90,0x80,0x85,0x12,0x2a,0x8b,0x04,0x1b,0x25,0xa4,0x7f,0x88,0x7e,0x0e,0x12,0x2f, ++0xd9,0x90,0x80,0x85,0x12,0x2a,0x8b,0x20,0xdb,0x25,0xa4,0x7f,0x8c,0x7e,0x0e,0x12, ++0x2f,0xd9,0x90,0x80,0x85,0x12,0x2a,0x8b,0x20,0xdb,0x25,0xa4,0x7f,0xd0,0x7e,0x0e, ++0x12,0x2f,0xd9,0x90,0x80,0x85,0x12,0x2a,0x8b,0x20,0xdb,0x25,0xa4,0x7f,0xd4,0x7e, ++0x0e,0x12,0x2f,0xd9,0x90,0x80,0x85,0x12,0x2a,0x8b,0x20,0xdb,0x25,0xa4,0x7f,0xd8, ++0x7e,0x0e,0x12,0x2f,0xd9,0x90,0x80,0x85,0x12,0x2a,0x8b,0x00,0x1b,0x25,0xa4,0x7f, ++0xdc,0x7e,0x0e,0x12,0x2f,0xd9,0x90,0x80,0x85,0x12,0x2a,0x8b,0x00,0x1b,0x25,0xa4, ++0x7f,0xe0,0x7e,0x0e,0x12,0x2f,0xd9,0x90,0x80,0x85,0x12,0x2a,0x8b,0x24,0xdb,0x25, ++0xa4,0x7f,0xec,0x7e,0x0e,0x12,0x2f,0xd9,0x7f,0x04,0x7e,0x0c,0x12,0x27,0xde,0x90, ++0x9e,0xa4,0x12,0x2a,0x7f,0x90,0x9e,0xa4,0x12,0x43,0x53,0xe4,0xff,0xec,0x90,0x9e, ++0xa4,0x12,0x2a,0x7f,0x90,0x9e,0xa4,0x12,0x43,0x53,0xef,0x44,0x11,0xff,0xec,0x90, ++0x9e,0xa4,0x12,0x2a,0x7f,0x90,0x9e,0xa4,0x12,0x43,0x53,0x90,0x80,0x85,0x12,0x2a, ++0x7f,0x7f,0x04,0x7e,0x0c,0x12,0x2f,0xd9,0x7f,0x04,0x7e,0x0d,0x12,0x27,0xde,0x90, ++0x9e,0xa4,0x12,0x2a,0x7f,0x90,0x9e,0xa4,0x12,0x43,0x53,0xef,0x54,0xf0,0xff,0xec, ++0x90,0x9e,0xa4,0x12,0x2a,0x7f,0x90,0x9e,0xa4,0x12,0x43,0x53,0xef,0x44,0x01,0xff, ++0xec,0x90,0x9e,0xa4,0x12,0x2a,0x7f,0x90,0x9e,0xa4,0x12,0x43,0x53,0x90,0x80,0x85, ++0x12,0x2a,0x7f,0x7f,0x04,0x7e,0x0d,0x12,0x2f,0xd9,0x7f,0x0c,0x7e,0x09,0x12,0x27, ++0xde,0x90,0x9e,0xa4,0x12,0x2a,0x7f,0x90,0x9e,0xa4,0x12,0x43,0x53,0xe4,0xff,0xec, ++0x90,0x9e,0xa4,0x12,0x2a,0x7f,0x90,0x9e,0xa4,0x12,0x43,0x53,0xef,0x44,0x11,0xff, ++0xec,0x90,0x9e,0xa4,0x12,0x2a,0x7f,0x90,0x9e,0xa4,0x12,0x43,0x53,0x90,0x80,0x85, ++0x12,0x2a,0x7f,0x7f,0x0c,0x7e,0x09,0x12,0x2f,0xd9,0x7f,0x0c,0x7e,0x09,0x12,0x27, ++0xde,0x90,0x9e,0xa4,0x12,0x2a,0x7f,0x90,0x9e,0xa4,0x12,0x43,0x53,0xed,0x54,0x0f, ++0xfd,0xec,0x54,0xf0,0xfc,0x90,0x9e,0xa4,0x12,0x2a,0x7f,0x90,0x9e,0xa4,0x12,0x43, ++0x53,0xed,0x44,0x10,0xfd,0xec,0x44,0x01,0xfc,0x90,0x9e,0xa4,0x12,0x2a,0x7f,0x90, ++0x9e,0xa4,0x12,0x43,0x53,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0x0c,0x7e,0x09,0x12, ++0x2f,0xd9,0x7f,0x04,0x7e,0x08,0x12,0x27,0xde,0x90,0x9e,0xa4,0x12,0x2a,0x7f,0x90, ++0x9e,0xa4,0x12,0x43,0x53,0xef,0x54,0xf0,0xff,0xec,0x90,0x9e,0xa4,0x12,0x2a,0x7f, ++0x90,0x9e,0xa4,0x12,0x43,0x53,0xef,0x44,0x01,0xff,0xec,0x90,0x9e,0xa4,0x12,0x2a, ++0x7f,0x90,0x9e,0xa4,0x12,0x43,0x53,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0x04,0x7e, ++0x08,0x12,0x2f,0xd9,0xe4,0x90,0x9e,0x0f,0xf0,0x22,0x90,0x00,0x02,0x12,0x42,0x20, ++0x90,0x9e,0x1e,0xf0,0xe0,0x60,0x04,0xe0,0xf4,0x70,0x21,0xa2,0xaf,0xe4,0x33,0xf5, ++0x59,0xc2,0xaf,0x90,0x00,0x47,0xe0,0x54,0xfb,0xfd,0x7f,0x47,0x12,0x4a,0xc1,0x7d, ++0x40,0x7f,0x01,0x12,0x36,0xaf,0xe5,0x59,0x24,0xff,0x92,0xaf,0x22,0xe4,0xfd,0x7f, ++0x45,0x12,0x4a,0xc1,0x90,0x04,0xfd,0xe4,0xf0,0xa3,0xf0,0x90,0x9e,0x1e,0xf0,0x90, ++0x9e,0x24,0xf0,0x90,0x9e,0x27,0xf0,0x90,0x9e,0x25,0xf0,0x90,0x9e,0x28,0xf0,0x90, ++0x9e,0x26,0xf0,0x90,0x9e,0x29,0xf0,0x90,0x9e,0x10,0x04,0xf0,0xe4,0xa3,0xf0,0xa3, ++0xf0,0xa3,0xf0,0x90,0x9e,0x15,0xf0,0x90,0x9e,0x1a,0xf0,0x90,0x9e,0x1c,0xf0,0x90, ++0x9e,0x2e,0xf0,0x90,0x9e,0x1f,0xf0,0x90,0x9e,0x1b,0xf0,0x90,0x9e,0x14,0xf0,0x90, ++0x00,0x51,0xe0,0x44,0xc0,0xfd,0x7f,0x51,0x02,0x4a,0xc1,0x90,0x9e,0x15,0xe0,0xc3, ++0x94,0x14,0x50,0x05,0xe0,0x04,0xf0,0xc1,0x33,0x90,0x9e,0x15,0xe0,0x64,0x14,0x60, ++0x02,0xc1,0x33,0x90,0x9e,0x24,0xe0,0x70,0x25,0x90,0x9e,0x27,0xe0,0x70,0x1f,0x90, ++0x9e,0x25,0xe0,0x70,0x19,0x90,0x9e,0x28,0xe0,0x70,0x13,0x90,0x9e,0x26,0xe0,0x70, ++0x0d,0x90,0x9e,0x29,0xe0,0x70,0x07,0x90,0x04,0xfd,0xe0,0x54,0xfe,0xf0,0x90,0x9e, ++0x24,0xe0,0x90,0x04,0x44,0xf0,0x90,0x9e,0x25,0xe0,0x90,0x04,0x45,0xf0,0x90,0x9e, ++0x26,0xe0,0x90,0x04,0x46,0xf0,0xa3,0xe4,0xf0,0x90,0x9e,0x27,0xe0,0x90,0x04,0x48, ++0xf0,0x90,0x9e,0x28,0xe0,0x90,0x04,0x49,0xf0,0x90,0x9e,0x29,0xe0,0x90,0x04,0x4a, ++0xf0,0xa3,0xe4,0xf0,0x90,0x9e,0x10,0xe0,0x90,0x04,0x4c,0xf0,0x90,0x9e,0x11,0xe0, ++0x90,0x04,0x4d,0xf0,0x90,0x9e,0x12,0xe0,0x90,0x04,0x4e,0xf0,0x90,0x9e,0x13,0xe0, ++0x90,0x04,0x4f,0xf0,0xe4,0x90,0x9e,0x15,0xf0,0x90,0x9e,0x10,0x04,0xf0,0xe4,0xa3, ++0xf0,0xa3,0xf0,0xa3,0xf0,0x90,0x9e,0x24,0xf0,0xa3,0xf0,0xa3,0xf0,0xa3,0xf0,0xa3, ++0xf0,0xa3,0xf0,0x90,0x05,0x60,0xe0,0x90,0x9e,0x34,0xf0,0x90,0x05,0x61,0xe0,0x90, ++0x9e,0x35,0xf0,0x90,0x05,0x62,0xe0,0x90,0x9e,0x36,0xf0,0x90,0x05,0x63,0xe0,0x90, ++0x9e,0x37,0xf0,0x90,0x9e,0x2d,0xe0,0xff,0x90,0x9e,0x37,0xe0,0xfe,0xd3,0x9f,0x50, ++0x0b,0x90,0x9e,0x2d,0xe0,0xc3,0x9e,0xd3,0x94,0x01,0x40,0x11,0x90,0x9e,0x1b,0xe0, ++0xb4,0x01,0x02,0x80,0x03,0x90,0x9e,0x1f,0xe0,0xff,0x12,0x4e,0xd8,0x22,0x90,0x9e, ++0x2e,0xe0,0x64,0x01,0x60,0x08,0x90,0x9e,0x1c,0xe0,0x60,0x02,0xe1,0x55,0x90,0x9e, ++0x10,0xe0,0xc3,0x94,0xff,0x50,0x05,0xe0,0x04,0xf0,0x80,0x3b,0x90,0x9e,0x11,0xe0, ++0xc3,0x94,0xff,0x50,0x06,0xe0,0x04,0xf0,0xe4,0x80,0x28,0x90,0x9e,0x12,0xe0,0xc3, ++0x94,0xff,0x50,0x0a,0xe0,0x04,0xf0,0xe4,0x90,0x9e,0x11,0xf0,0x80,0x15,0x90,0x9e, ++0x13,0xe0,0xc3,0x94,0xff,0x50,0x10,0xe0,0x04,0xf0,0xe4,0x90,0x9e,0x12,0xf0,0x90, ++0x9e,0x11,0xf0,0x90,0x9e,0x10,0xf0,0x90,0x00,0x44,0xe0,0x54,0x0c,0x60,0x76,0xe0, ++0x30,0xe2,0x32,0x90,0x9e,0x24,0xe0,0xc3,0x94,0xff,0x50,0x05,0xe0,0x04,0xf0,0x80, ++0x24,0x90,0x9e,0x25,0xe0,0xc3,0x94,0xff,0x50,0x06,0xe0,0x04,0xf0,0xe4,0x80,0x11, ++0x90,0x9e,0x26,0xe0,0xc3,0x94,0xff,0x50,0x0c,0xe0,0x04,0xf0,0xe4,0x90,0x9e,0x25, ++0xf0,0x90,0x9e,0x24,0xf0,0x90,0x00,0x44,0xe0,0x30,0xe3,0x32,0x90,0x9e,0x27,0xe0, ++0xc3,0x94,0xff,0x50,0x05,0xe0,0x04,0xf0,0x80,0x24,0x90,0x9e,0x28,0xe0,0xc3,0x94, ++0xff,0x50,0x06,0xe0,0x04,0xf0,0xe4,0x80,0x11,0x90,0x9e,0x29,0xe0,0xc3,0x94,0xff, ++0x50,0x0c,0xe0,0x04,0xf0,0xe4,0x90,0x9e,0x28,0xf0,0x90,0x9e,0x27,0xf0,0x90,0x04, ++0xfd,0xe0,0x44,0x01,0xf0,0x22,0x3a,0x01,}; ++ ++// =================== v79 UMC A Cut COMMON 2011-10-06 ===================== ++u8 Rtl8192CUFwUMCACutImgArray[UMCACutImgArrayLength] = { ++0xc1,0x88,0x02,0x00,0x4f,0x00,0x00,0x00,0x0a,0x06,0x18,0x09,0x58,0x3f,0x01,0x00, ++0x61,0x80,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x02,0x43,0xba,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x02,0x5a,0x45,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x02,0x5f,0xfb,0x00,0x00,0x00,0x00,0x00,0xa1,0xdf,0x00,0x00,0x00, ++0x05,0x04,0x03,0x02,0x00,0x03,0x06,0x05,0x04,0x03,0x00,0x04,0x06,0x05,0x04,0x02, ++0x00,0x04,0x08,0x07,0x06,0x04,0x00,0x06,0x0a,0x09,0x08,0x06,0x00,0x08,0x0a,0x09, ++0x08,0x04,0x00,0x08,0x0a,0x09,0x08,0x02,0x00,0x08,0x0a,0x09,0x08,0x00,0x00,0x08, ++0x12,0x11,0x10,0x08,0x00,0x10,0x1a,0x19,0x18,0x10,0x00,0x18,0x22,0x21,0x20,0x18, ++0x00,0x20,0x22,0x21,0x20,0x10,0x00,0x20,0x22,0x21,0x20,0x08,0x00,0x20,0x22,0x21, ++0x1c,0x08,0x00,0x20,0x22,0x21,0x14,0x08,0x00,0x20,0x22,0x20,0x18,0x08,0x00,0x20, ++0x31,0x30,0x20,0x10,0x00,0x30,0x31,0x30,0x18,0x00,0x00,0x30,0x31,0x2f,0x10,0x10, ++0x00,0x30,0x31,0x2c,0x10,0x10,0x00,0x30,0x31,0x28,0x10,0x00,0x00,0x30,0x31,0x20, ++0x10,0x00,0x00,0x30,0x31,0x10,0x10,0x00,0x00,0x30,0x04,0x04,0x04,0x05,0x04,0x04, ++0x04,0x05,0x05,0x05,0x06,0x06,0x04,0x04,0x04,0x05,0x05,0x05,0x06,0x06,0x04,0x04, ++0x05,0x05,0x05,0x05,0x06,0x06,0x04,0x04,0x05,0x05,0x05,0x05,0x06,0x07,0x0a,0x0b, ++0x0d,0x10,0x04,0x05,0x05,0x06,0x06,0x09,0x0c,0x11,0x08,0x08,0x09,0x09,0x0a,0x0c, ++0x10,0x11,0x04,0x04,0x04,0x05,0x04,0x04,0x05,0x07,0x07,0x07,0x08,0x0a,0x04,0x04, ++0x04,0x04,0x06,0x0a,0x0b,0x0d,0x05,0x05,0x07,0x07,0x08,0x0b,0x0d,0x0f,0x04,0x04, ++0x04,0x05,0x07,0x07,0x09,0x09,0x0c,0x0e,0x10,0x12,0x04,0x04,0x05,0x05,0x06,0x0a, ++0x11,0x13,0x09,0x09,0x09,0x09,0x0c,0x0e,0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x24,0x26,0x2a,0x18,0x1a,0x1d,0x1f,0x21,0x27,0x29,0x2a,0x00,0x00, ++0x00,0x1f,0x23,0x28,0x2a,0x2c,0x00,0x04,0x00,0x04,0x00,0x08,0x00,0x10,0x00,0x18, ++0x00,0x24,0x00,0x30,0x00,0x48,0x00,0x60,0x00,0x90,0x00,0xc0,0x00,0xd8,0x00,0x50, ++0x00,0x78,0x00,0xa0,0x00,0xc8,0x01,0x40,0x01,0x90,0x01,0xe0,0x02,0x30,0x01,0x2c, ++0x01,0x40,0x01,0xe0,0x02,0xd0,0x03,0xe8,0x04,0xb0,0x06,0x40,0x07,0xd0,0x00,0x02, ++0x00,0x02,0x00,0x04,0x00,0x08,0x00,0x0c,0x00,0x12,0x00,0x18,0x00,0x24,0x00,0x30, ++0x00,0x48,0x00,0x60,0x00,0x6c,0x00,0x28,0x00,0x3c,0x00,0x50,0x00,0x64,0x00,0xa0, ++0x00,0xc8,0x00,0xf0,0x01,0x18,0x00,0x64,0x00,0xa0,0x00,0xf0,0x01,0x68,0x01,0xf4, ++0x02,0x58,0x03,0x20,0x03,0xe8,0x02,0x02,0x02,0x02,0x02,0x02,0x03,0x03,0x04,0x04, ++0x05,0x07,0x04,0x04,0x07,0x0a,0x0a,0x0c,0x0c,0x12,0x05,0x07,0x07,0x08,0x0b,0x12, ++0x24,0x3c,0x01,0x01,0x01,0x01,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x01,0x02, ++0x03,0x04,0x05,0x06,0x07,0x08,0x05,0x06,0x07,0x08,0x09,0x0a,0x0b,0x0c,0x20,0x1e, ++0x1c,0x18,0x10,0x18,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0xbb,0x01,0x0c,0xe5,0x82,0x29,0xf5,0x82,0xe5,0x83,0x3a,0xf5,0x83,0xe0,0x22,0x50, ++0x06,0xe9,0x25,0x82,0xf8,0xe6,0x22,0xbb,0xfe,0x06,0xe9,0x25,0x82,0xf8,0xe2,0x22, ++0xe5,0x82,0x29,0xf5,0x82,0xe5,0x83,0x3a,0xf5,0x83,0xe4,0x93,0x22,0xbb,0x01,0x06, ++0x89,0x82,0x8a,0x83,0xf0,0x22,0x50,0x02,0xf7,0x22,0xbb,0xfe,0x01,0xf3,0x22,0xf8, ++0xbb,0x01,0x0d,0xe5,0x82,0x29,0xf5,0x82,0xe5,0x83,0x3a,0xf5,0x83,0xe8,0xf0,0x22, ++0x50,0x06,0xe9,0x25,0x82,0xc8,0xf6,0x22,0xbb,0xfe,0x05,0xe9,0x25,0x82,0xc8,0xf2, ++0x22,0xc5,0xf0,0xf8,0xa3,0xe0,0x28,0xf0,0xc5,0xf0,0xf8,0xe5,0x82,0x15,0x82,0x70, ++0x02,0x15,0x83,0xe0,0x38,0xf0,0x22,0xbb,0x01,0x0a,0x89,0x82,0x8a,0x83,0xe0,0xf5, ++0xf0,0xa3,0xe0,0x22,0x50,0x06,0x87,0xf0,0x09,0xe7,0x19,0x22,0xbb,0xfe,0x07,0xe3, ++0xf5,0xf0,0x09,0xe3,0x19,0x22,0x89,0x82,0x8a,0x83,0xe4,0x93,0xf5,0xf0,0x74,0x01, ++0x93,0x22,0xbb,0x01,0x10,0xe5,0x82,0x29,0xf5,0x82,0xe5,0x83,0x3a,0xf5,0x83,0xe0, ++0xf5,0xf0,0xa3,0xe0,0x22,0x50,0x09,0xe9,0x25,0x82,0xf8,0x86,0xf0,0x08,0xe6,0x22, ++0xbb,0xfe,0x0a,0xe9,0x25,0x82,0xf8,0xe2,0xf5,0xf0,0x08,0xe2,0x22,0xe5,0x83,0x2a, ++0xf5,0x83,0xe9,0x93,0xf5,0xf0,0xa3,0xe9,0x93,0x22,0xbb,0x01,0x0a,0x89,0x82,0x8a, ++0x83,0xf0,0xe5,0xf0,0xa3,0xf0,0x22,0x50,0x06,0xf7,0x09,0xa7,0xf0,0x19,0x22,0xbb, ++0xfe,0x06,0xf3,0xe5,0xf0,0x09,0xf3,0x19,0x22,0xf8,0xbb,0x01,0x11,0xe5,0x82,0x29, ++0xf5,0x82,0xe5,0x83,0x3a,0xf5,0x83,0xe8,0xf0,0xe5,0xf0,0xa3,0xf0,0x22,0x50,0x09, ++0xe9,0x25,0x82,0xc8,0xf6,0x08,0xa6,0xf0,0x22,0xbb,0xfe,0x09,0xe9,0x25,0x82,0xc8, ++0xf2,0xe5,0xf0,0x08,0xf2,0x22,0xef,0x4b,0xff,0xee,0x4a,0xfe,0xed,0x49,0xfd,0xec, ++0x48,0xfc,0x22,0xe0,0xfc,0xa3,0xe0,0xfd,0xa3,0xe0,0xfe,0xa3,0xe0,0xff,0x22,0xa4, ++0x25,0x82,0xf5,0x82,0xe5,0xf0,0x35,0x83,0xf5,0x83,0x22,0xe0,0xfb,0xa3,0xe0,0xfa, ++0xa3,0xe0,0xf9,0x22,0xf8,0xe0,0xfb,0xa3,0xa3,0xe0,0xf9,0x25,0xf0,0xf0,0xe5,0x82, ++0x15,0x82,0x70,0x02,0x15,0x83,0xe0,0xfa,0x38,0xf0,0x22,0xeb,0xf0,0xa3,0xea,0xf0, ++0xa3,0xe9,0xf0,0x22,0xd0,0x83,0xd0,0x82,0xf8,0xe4,0x93,0x70,0x12,0x74,0x01,0x93, ++0x70,0x0d,0xa3,0xa3,0x93,0xf8,0x74,0x01,0x93,0xf5,0x82,0x88,0x83,0xe4,0x73,0x74, ++0x02,0x93,0x68,0x60,0xef,0xa3,0xa3,0xa3,0x80,0xdf,0x02,0x43,0xf8,0x02,0x50,0xa9, ++0xe4,0x93,0xa3,0xf8,0xe4,0x93,0xa3,0x40,0x03,0xf6,0x80,0x01,0xf2,0x08,0xdf,0xf4, ++0x80,0x29,0xe4,0x93,0xa3,0xf8,0x54,0x07,0x24,0x0c,0xc8,0xc3,0x33,0xc4,0x54,0x0f, ++0x44,0x20,0xc8,0x83,0x40,0x04,0xf4,0x56,0x80,0x01,0x46,0xf6,0xdf,0xe4,0x80,0x0b, ++0x01,0x02,0x04,0x08,0x10,0x20,0x40,0x80,0x90,0x44,0x3d,0xe4,0x7e,0x01,0x93,0x60, ++0xbc,0xa3,0xff,0x54,0x3f,0x30,0xe5,0x09,0x54,0x1f,0xfe,0xe4,0x93,0xa3,0x60,0x01, ++0x0e,0xcf,0x54,0xc0,0x25,0xe0,0x60,0xa8,0x40,0xb8,0xe4,0x93,0xa3,0xfa,0xe4,0x93, ++0xa3,0xf8,0xe4,0x93,0xa3,0xc8,0xc5,0x82,0xc8,0xca,0xc5,0x83,0xca,0xf0,0xa3,0xc8, ++0xc5,0x82,0xc8,0xca,0xc5,0x83,0xca,0xdf,0xe9,0xde,0xe7,0x80,0xbe,0x41,0x9e,0x66, ++0x00,0x41,0x9e,0xae,0x00,0x41,0x9e,0x4d,0x80,0x41,0x9e,0x4e,0x80,0x41,0x9e,0xb0, ++0x00,0x00,0xf0,0x90,0x9e,0x57,0xe0,0x90,0x9e,0x8a,0xf0,0xe4,0xfb,0xfd,0x7f,0x54, ++0x7e,0x01,0xd3,0x10,0xaf,0x01,0xc3,0xc0,0xd0,0x90,0x9e,0x88,0xeb,0xf0,0xa3,0xe0, ++0xfb,0xa3,0xe0,0xf5,0x44,0xe4,0xf5,0x45,0x12,0x30,0x62,0xd0,0xd0,0x92,0xaf,0x22, ++0x90,0x01,0x5f,0xe4,0xf0,0x90,0x01,0x3c,0x74,0x08,0xf0,0xe4,0x90,0x9e,0x89,0xf0, ++0x90,0x9e,0x55,0xe0,0x90,0x9e,0x8a,0xf0,0xe4,0xfb,0xfd,0x7f,0x5c,0x7e,0x01,0x91, ++0x62,0x90,0x01,0x5f,0x74,0x05,0xf0,0x90,0x06,0x92,0x74,0x02,0xf0,0x90,0x9e,0x5c, ++0x14,0xf0,0x90,0x9e,0x5e,0xe0,0x54,0x0f,0xc3,0x94,0x0c,0x50,0x02,0xf1,0x16,0x22, ++0x8f,0x82,0x8e,0x83,0xa3,0xa3,0xa3,0xe4,0xf0,0x22,0xe4,0xf5,0x22,0x7f,0x60,0x7e, ++0x01,0x80,0xed,0x90,0x9e,0x60,0xe0,0xff,0x7d,0x01,0xe1,0x1a,0xb1,0xb1,0xbf,0x01, ++0x0f,0x90,0x9e,0x68,0xe0,0xff,0xe4,0xfd,0xf1,0xfe,0x90,0x04,0x1f,0x74,0x20,0xf0, ++0x22,0x90,0x01,0xca,0xe5,0x25,0xf0,0xef,0x60,0x03,0x12,0x4f,0x2a,0x22,0x22,0x22, ++0x22,0x22,0x00,0x02,0x60,0x8d,0x02,0x60,0x94,0xd3,0x10,0xaf,0x01,0xc3,0xc0,0xd0, ++0x8b,0x1b,0x8a,0x1c,0x89,0x1d,0x90,0x9e,0x8b,0x71,0x8b,0xab,0x1e,0xaa,0x1f,0xa9, ++0x20,0x90,0x9e,0x8e,0x71,0x8b,0xaf,0x21,0x15,0x21,0xef,0x60,0x1b,0x90,0x9e,0x8e, ++0xe4,0x75,0xf0,0x01,0x71,0x74,0x12,0x24,0x62,0xff,0x90,0x9e,0x8b,0xe4,0x75,0xf0, ++0x01,0x71,0x74,0xef,0x51,0x4d,0x80,0xde,0xab,0x1b,0xaa,0x1c,0xa9,0x1d,0xd0,0xd0, ++0x92,0xaf,0x22,0x90,0x06,0xa9,0xe0,0xf5,0x50,0x54,0xc0,0x70,0x0d,0x90,0x9e,0x63, ++0xe0,0x54,0xfe,0xf0,0xe0,0x54,0xfd,0xf0,0x91,0xd3,0xe5,0x50,0x30,0xe6,0x17,0x90, ++0x9e,0x63,0xe0,0x44,0x01,0xf0,0x90,0x9e,0x61,0xe0,0x64,0x02,0x60,0x04,0x91,0xdc, ++0x80,0x0b,0x91,0x80,0x80,0x07,0x90,0x9e,0x63,0xe0,0x54,0xfe,0xf0,0xe5,0x50,0x90, ++0x9e,0x63,0x30,0xe7,0x17,0xe0,0x44,0x02,0xf0,0xe4,0x90,0x9e,0x89,0x91,0x52,0x90, ++0x01,0x57,0x74,0x05,0xf0,0x90,0x9e,0x62,0x74,0x01,0xf0,0x22,0xe0,0x54,0xfd,0xf0, ++0x22,0xd3,0x10,0xaf,0x01,0xc3,0xc0,0xd0,0x90,0x04,0x1d,0xe0,0x60,0x1a,0x90,0x05, ++0x22,0xe0,0x54,0x90,0x60,0x07,0x90,0x01,0xc6,0xe0,0x44,0x40,0xf0,0x90,0x01,0xc7, ++0xe0,0x30,0xe1,0xe4,0x7f,0x00,0x80,0x02,0x7f,0x01,0xd0,0xd0,0x92,0xaf,0x22,0xc0, ++0xe0,0xc0,0xf0,0xc0,0x83,0xc0,0x82,0xc0,0xd0,0x75,0xd0,0x00,0xc0,0x00,0xc0,0x01, ++0xc0,0x02,0xc0,0x03,0xc0,0x04,0xc0,0x05,0xc0,0x06,0xc0,0x07,0x90,0x01,0xc4,0x74, ++0xdf,0xf0,0x74,0x45,0xa3,0xf0,0x53,0x91,0xdf,0x90,0x01,0x3c,0xe0,0x55,0x30,0xf5, ++0x34,0xa3,0xe0,0x55,0x31,0xf5,0x35,0xa3,0xe0,0x55,0x32,0xf5,0x36,0xa3,0xe0,0x55, ++0x33,0xf5,0x37,0xe5,0x34,0x30,0xe0,0x06,0x90,0x01,0x3c,0x74,0x01,0xf0,0xe5,0x34, ++0x30,0xe1,0x08,0x90,0x01,0x3c,0x74,0x02,0xf0,0xf1,0xbc,0xe5,0x34,0x30,0xe2,0x38, ++0x90,0x01,0x3c,0x74,0x04,0xf0,0x90,0x06,0x92,0xe0,0x30,0xe0,0x24,0x90,0x9e,0x89, ++0xe4,0xf0,0x90,0x9e,0x55,0xe0,0x90,0x9e,0x8a,0xf0,0xe4,0xfb,0xfd,0x7f,0x58,0x7e, ++0x01,0x91,0x62,0x90,0x01,0x5b,0x74,0x05,0xf0,0x90,0x06,0x92,0x74,0x01,0xf0,0x80, ++0x07,0x90,0x9e,0x5d,0xe4,0xf0,0x91,0xd3,0xe5,0x34,0x30,0xe3,0x38,0x90,0x01,0x3c, ++0x74,0x08,0xf0,0x90,0x06,0x92,0xe0,0x30,0xe1,0x24,0x90,0x9e,0x89,0xe4,0xf0,0x90, ++0x9e,0x55,0xe0,0x90,0x9e,0x8a,0xf0,0xe4,0xfb,0xfd,0x7f,0x5c,0x7e,0x01,0x91,0x62, ++0x90,0x01,0x5f,0x74,0x05,0xf0,0x90,0x06,0x92,0x74,0x02,0xf0,0x80,0x07,0x90,0x9e, ++0x5c,0xe4,0xf0,0x91,0xd3,0xe5,0x34,0x30,0xe4,0x09,0x90,0x01,0x3c,0x74,0x10,0xf0, ++0x12,0x4d,0xe2,0xe5,0x34,0x30,0xe5,0x09,0x90,0x01,0x3c,0x74,0x20,0xf0,0x12,0x4e, ++0x25,0xe5,0x35,0x30,0xe0,0x1a,0x90,0x01,0x3d,0x74,0x01,0xf0,0x90,0x01,0x2f,0xe0, ++0x44,0x7f,0xf0,0x90,0x00,0x83,0xe0,0x90,0x9e,0x60,0xf0,0x12,0x64,0xa1,0x91,0xd3, ++0x74,0xdf,0x04,0x90,0x01,0xc4,0xf0,0x74,0x45,0xa3,0xf0,0xd0,0x07,0xd0,0x06,0xd0, ++0x05,0xd0,0x04,0xd0,0x03,0xd0,0x02,0xd0,0x01,0xd0,0x00,0xd0,0xd0,0xd0,0x82,0xd0, ++0x83,0xd0,0xf0,0xd0,0xe0,0x32,0x7d,0x01,0x7f,0x0c,0x8f,0x71,0x8d,0x72,0xe5,0x71, ++0x54,0x0f,0xff,0x90,0x9e,0x5e,0xe0,0x54,0x0f,0x6f,0x60,0x72,0xe5,0x71,0x30,0xe2, ++0x2b,0x90,0x9e,0x5e,0xe0,0x20,0xe2,0x05,0x7f,0x01,0x12,0x63,0x92,0x90,0x9e,0x5e, ++0xe0,0x30,0xe3,0x07,0xe5,0x71,0x20,0xe3,0x02,0x80,0x54,0x90,0x9e,0x5e,0xe0,0x20, ++0xe3,0x4c,0xe5,0x71,0x30,0xe3,0x47,0xaf,0x72,0x02,0x63,0x2e,0x90,0x9e,0x5e,0xe0, ++0x54,0x0f,0xff,0xbf,0x0c,0x0d,0xe5,0x71,0x20,0xe3,0x08,0x12,0x5e,0xf1,0xef,0x60, ++0x2d,0xf1,0x9f,0x90,0x9e,0x5e,0xe0,0x54,0x0f,0xff,0xbf,0x04,0x0e,0xe5,0x71,0x20, ++0xe2,0x09,0x12,0x62,0x50,0xef,0x60,0x16,0x12,0x48,0xaa,0x90,0x9e,0x5e,0xe0,0x54, ++0x0f,0xff,0xbf,0x02,0x09,0x12,0x62,0xbb,0xef,0x60,0x03,0x12,0x64,0x87,0x22,0x90, ++0x06,0x04,0xe0,0x44,0x40,0xf0,0xe5,0x73,0xb4,0x01,0x05,0x7f,0x01,0x12,0x63,0x4d, ++0x90,0x9e,0x5e,0xe0,0x54,0xf0,0xf0,0xe0,0x44,0x04,0xf0,0x22,0x90,0x9e,0x62,0xe0, ++0x60,0x0e,0xe4,0xf0,0xa3,0xe0,0x54,0xfd,0xf0,0xe0,0x54,0x07,0x70,0x2b,0x80,0x27, ++0x90,0x9e,0x51,0xe0,0x04,0xf0,0x90,0x9e,0x63,0xe0,0x54,0xef,0xf0,0x90,0x9e,0x56, ++0xe0,0xff,0x90,0x9e,0x51,0xe0,0xd3,0x9f,0x40,0x0d,0xe5,0x73,0xb4,0x01,0x0a,0xa3, ++0xe0,0x70,0x06,0xe0,0x04,0xf0,0x22,0x91,0xd3,0x22,0xe0,0xff,0x7d,0x01,0x90,0x9e, ++0x9c,0xef,0xf0,0xa3,0xed,0xf0,0xe4,0xa3,0xf0,0xa3,0xf0,0xe5,0x74,0x60,0x04,0xe4, ++0xff,0x11,0x8f,0x90,0x9e,0x9c,0xe0,0x30,0xe0,0x09,0x90,0x9e,0x9e,0xe4,0xf0,0xa3, ++0x74,0x80,0xf0,0x90,0x9e,0x9c,0xe0,0xff,0xc3,0x13,0x90,0xfd,0x10,0xf0,0x90,0x04, ++0x25,0xef,0xf0,0x90,0x9e,0x9d,0xe0,0x60,0x1f,0xa3,0xa3,0xe0,0xff,0x24,0x0f,0xf5, ++0x82,0xe4,0x34,0xfc,0xf5,0x83,0xe0,0x44,0x80,0xf0,0x74,0x10,0x2f,0xf5,0x82,0xe4, ++0x34,0xfc,0xf5,0x83,0xe0,0x44,0x80,0xf0,0x90,0x9e,0x9e,0xa3,0xe0,0xff,0xfd,0x24, ++0x08,0xf5,0x82,0xe4,0x34,0xfc,0xf5,0x83,0xe4,0xf0,0x74,0x09,0x2d,0xf5,0x82,0xe4, ++0x34,0xfc,0xf5,0x83,0xe0,0x54,0xf0,0xf0,0x74,0x21,0x2f,0xf5,0x82,0xe4,0x34,0xfc, ++0xf5,0x83,0xe0,0x54,0xf7,0xf0,0x90,0x9e,0x9e,0xe0,0xfe,0xa3,0xe0,0xff,0x22,0xef, ++0x60,0x0b,0x90,0x9e,0x77,0xe0,0xb4,0x01,0x10,0xe4,0xff,0x80,0x09,0x90,0x9e,0x77, ++0xe0,0xb4,0x01,0x05,0x7f,0x01,0x12,0x77,0x66,0x22,0x90,0x01,0x37,0x74,0x02,0xf0, ++0x90,0x05,0x22,0x74,0xff,0xf0,0x12,0x77,0x1c,0xef,0x70,0x06,0x90,0x01,0xc8,0x74, ++0xfd,0xf0,0x7d,0x02,0x7f,0x03,0x12,0x31,0x9d,0xe5,0x74,0x60,0x04,0x7f,0x01,0x11, ++0x8f,0x11,0xdf,0x90,0x9e,0x5e,0xe0,0x54,0xf0,0xf0,0xe0,0x44,0x02,0xf0,0x22,0x7f, ++0x78,0x7e,0x08,0x12,0x22,0x65,0x90,0x9d,0xff,0x12,0x25,0x08,0x7f,0x04,0x7e,0x0c, ++0x12,0x22,0x65,0x90,0x9e,0x03,0x12,0x25,0x08,0x7f,0x00,0x7e,0x08,0x12,0x22,0x65, ++0x90,0x9e,0x07,0x12,0x25,0x08,0x90,0x9e,0x77,0xe0,0x90,0x9d,0xff,0xb4,0x01,0x0d, ++0x12,0x43,0x53,0xef,0x54,0xc7,0xff,0xed,0x54,0xc7,0xfd,0x80,0x07,0x12,0x43,0x53, ++0xef,0x54,0xc7,0xff,0xec,0x90,0x80,0x96,0x12,0x25,0x08,0x7f,0x78,0x7e,0x08,0x12, ++0x2b,0x08,0x90,0x9e,0x03,0x12,0x43,0x53,0xef,0x54,0x0f,0xff,0xec,0x90,0x80,0x96, ++0x12,0x25,0x08,0x7f,0x04,0x7e,0x0c,0x12,0x2b,0x08,0x90,0x9e,0x07,0x12,0x43,0x53, ++0xef,0x44,0x02,0xff,0xec,0x90,0x80,0x96,0x12,0x25,0x08,0x7f,0x00,0x7e,0x08,0x12, ++0x2b,0x08,0x7f,0x70,0x7e,0x0e,0x12,0x22,0x65,0x90,0x9e,0x0b,0x12,0x25,0x08,0x90, ++0x80,0x96,0x12,0x25,0x14,0x00,0x1b,0x25,0xa0,0x7f,0x70,0x7e,0x0e,0x12,0x2b,0x08, ++0x90,0x80,0x68,0x12,0x25,0x14,0x00,0x00,0x00,0x00,0xe4,0xfd,0xff,0x12,0x30,0x2c, ++0x90,0x9e,0x77,0xe0,0xb4,0x01,0x11,0x90,0x80,0x68,0x12,0x25,0x14,0x00,0x00,0x00, ++0x00,0xe4,0xfd,0x7f,0x01,0x12,0x30,0x2c,0x90,0x00,0x11,0xe0,0x54,0xf6,0xf0,0x80, ++0x08,0xf4,0xff,0x90,0x00,0x43,0xe0,0x5f,0xf0,0xd3,0x10,0xaf,0x01,0xc3,0xc0,0xd0, ++0x7f,0x10,0xdf,0xfe,0xd0,0xd0,0x92,0xaf,0x22,0xd3,0x10,0xaf,0x01,0xc3,0xc0,0xd0, ++0x90,0x9e,0xad,0xed,0xf0,0x90,0x9e,0xac,0xef,0xf0,0xd3,0x94,0x07,0x50,0x63,0xe0, ++0xff,0x74,0x01,0xa8,0x07,0x08,0x80,0x02,0xc3,0x33,0xd8,0xfc,0xf4,0xff,0x90,0x00, ++0x47,0xe0,0x5f,0xf0,0x31,0xb9,0x90,0x9e,0xac,0xe0,0xff,0x74,0x01,0xa8,0x07,0x08, ++0x80,0x02,0xc3,0x33,0xd8,0xfc,0xff,0x90,0x00,0x46,0xe0,0x4f,0xf0,0x31,0xb9,0x90, ++0x9e,0xad,0xe0,0x60,0x16,0x90,0x9e,0xac,0xe0,0xff,0x74,0x01,0xa8,0x07,0x08,0x80, ++0x02,0xc3,0x33,0xd8,0xfc,0xff,0x90,0x00,0x45,0x80,0x66,0x90,0x9e,0xac,0xe0,0xff, ++0x74,0x01,0xa8,0x07,0x08,0x80,0x02,0xc3,0x33,0xd8,0xfc,0xf4,0xff,0x90,0x00,0x45, ++0x80,0x6b,0x90,0x9e,0xac,0xe0,0x24,0xf8,0xf0,0xe0,0xff,0x74,0x01,0xa8,0x07,0x08, ++0x80,0x02,0xc3,0x33,0xd8,0xfc,0xc4,0x54,0xf0,0x31,0xb1,0x90,0x9e,0xac,0xe0,0xff, ++0x74,0x01,0xa8,0x07,0x08,0x80,0x02,0xc3,0x33,0xd8,0xfc,0xff,0x90,0x00,0x43,0xe0, ++0x4f,0xf0,0x31,0xb9,0x90,0x9e,0xad,0xe0,0x60,0x1b,0x90,0x9e,0xac,0xe0,0xff,0x74, ++0x01,0xa8,0x07,0x08,0x80,0x02,0xc3,0x33,0xd8,0xfc,0xc4,0x54,0xf0,0xff,0x90,0x00, ++0x42,0xe0,0x4f,0x80,0x1a,0x90,0x9e,0xac,0xe0,0xff,0x74,0x01,0xa8,0x07,0x08,0x80, ++0x02,0xc3,0x33,0xd8,0xfc,0xc4,0x54,0xf0,0xf4,0xff,0x90,0x00,0x42,0xe0,0x5f,0xf0, ++0x31,0xb9,0xd0,0xd0,0x92,0xaf,0x22,0xf0,0x90,0x00,0x45,0xe0,0x54,0xfe,0xfd,0x7f, ++0x45,0xd3,0x10,0xaf,0x01,0xc3,0xc0,0xd0,0x8f,0x82,0x75,0x83,0x00,0xed,0xf0,0x31, ++0xb9,0xd0,0xd0,0x92,0xaf,0x22,0xef,0x14,0x60,0x30,0x14,0x60,0x66,0x24,0x02,0x60, ++0x02,0x61,0x7d,0x90,0x9e,0x1a,0x74,0x02,0xf0,0x90,0x00,0x48,0xe0,0x44,0x0c,0xfd, ++0x7f,0x48,0x51,0xc1,0x90,0x00,0x47,0xe0,0x44,0x08,0xfd,0x7f,0x47,0x51,0xc1,0x90, ++0x00,0x45,0xe0,0x44,0x10,0xfd,0x7f,0x45,0x80,0x71,0xe4,0x90,0x9e,0x1a,0xf0,0x90, ++0x9e,0x16,0x12,0x43,0x53,0x90,0x80,0x96,0x12,0x25,0x08,0x7f,0x80,0x7e,0x08,0x12, ++0x2b,0x08,0x90,0x00,0x45,0xe0,0x44,0xef,0xfd,0x7f,0x45,0x51,0xc1,0x90,0x00,0x45, ++0xe0,0x54,0xef,0xfd,0x7f,0x45,0x51,0xc1,0x90,0x00,0x46,0xe0,0x44,0x10,0xfd,0x7f, ++0x46,0x80,0x38,0x90,0x9e,0x1a,0x74,0x01,0xf0,0x90,0x9e,0x20,0x12,0x43,0x53,0x90, ++0x80,0x96,0x12,0x25,0x08,0x7f,0x80,0x7e,0x08,0x12,0x2b,0x08,0x90,0x00,0x45,0xe0, ++0x44,0x20,0xfd,0x7f,0x45,0x51,0xc1,0x90,0x00,0x45,0xe0,0x44,0x10,0xfd,0x7f,0x45, ++0x51,0xc1,0x90,0x00,0x46,0xe0,0x44,0x10,0xfd,0x7f,0x46,0x51,0xc1,0x22,0x90,0x00, ++0x02,0x12,0x42,0x20,0x90,0x9e,0x1c,0xf0,0x90,0x00,0x01,0x12,0x42,0x20,0x25,0xe0, ++0x25,0xe0,0x90,0x9e,0x1b,0xf0,0x12,0x24,0x62,0x25,0xe0,0x25,0xe0,0x90,0x9e,0x1f, ++0xf0,0x90,0x05,0x60,0xe0,0x90,0x9e,0x2a,0xf0,0x90,0x05,0x61,0xe0,0x90,0x9e,0x2b, ++0xf0,0x90,0x05,0x62,0xe0,0x90,0x9e,0x2c,0xf0,0x90,0x05,0x63,0xe0,0x90,0x9e,0x2d, ++0xf0,0xa2,0xaf,0xe4,0x33,0x90,0x9e,0x3f,0xf0,0xc2,0xaf,0x90,0x9e,0x1b,0xe0,0xff, ++0xd1,0xd8,0x90,0x9e,0x3f,0xe0,0x24,0xff,0x92,0xaf,0x90,0x9e,0x1c,0xe0,0x70,0x02, ++0x81,0x84,0x90,0x9e,0x1b,0xe0,0x70,0x02,0x81,0x84,0x90,0x9e,0x1f,0xe0,0x70,0x02, ++0x81,0x84,0xa2,0xaf,0xe4,0x33,0x90,0x9e,0x3f,0xf0,0xc2,0xaf,0x90,0x9e,0x2e,0x74, ++0x01,0xf0,0x90,0x9e,0x3f,0xe0,0x24,0xff,0x92,0xaf,0x51,0xb8,0x90,0x00,0x46,0xe0, ++0x44,0x01,0xfd,0x7f,0x46,0x51,0xc1,0x90,0x9e,0x14,0xe0,0x60,0x15,0x90,0x9e,0x20, ++0x12,0x43,0x53,0x90,0x80,0x96,0x12,0x25,0x08,0x7f,0x80,0x7e,0x08,0x12,0x2b,0x08, ++0x80,0x06,0x90,0x05,0x22,0x74,0x7f,0xf0,0x90,0x00,0x45,0xe0,0x54,0xef,0xfd,0x7f, ++0x45,0x51,0xc1,0x90,0x05,0x87,0xe0,0x64,0x80,0xf0,0x90,0x9e,0x2a,0xe0,0x90,0x05, ++0x84,0xf0,0x90,0x9e,0x2b,0xe0,0x90,0x05,0x85,0xf0,0x90,0x9e,0x2c,0xe0,0x90,0x05, ++0x86,0xf0,0x90,0x9e,0x2d,0xe0,0x90,0x05,0x87,0xf0,0xa2,0xaf,0xe4,0x33,0x90,0x9e, ++0x3f,0xf0,0xc2,0xaf,0x90,0x01,0x3c,0xe0,0x44,0x20,0xf0,0x7d,0x20,0xe4,0xff,0x12, ++0x31,0xb7,0x80,0x2b,0x90,0x9e,0x1c,0xe0,0x70,0x2d,0x90,0x9e,0x2e,0x51,0xb7,0x90, ++0x00,0x46,0xe0,0x54,0xfe,0xfd,0x7f,0x46,0x51,0xc1,0x90,0x05,0x22,0xe4,0xf0,0xa2, ++0xaf,0x33,0x90,0x9e,0x3f,0xf0,0xc2,0xaf,0x7d,0x20,0xe4,0xff,0x12,0x31,0x49,0x90, ++0x9e,0x3f,0xe0,0x24,0xff,0x92,0xaf,0x22,0x8b,0x59,0x8a,0x5a,0x89,0x5b,0x90,0x00, ++0x02,0x12,0x42,0x20,0x90,0x9e,0x1d,0xf0,0xe0,0x30,0xe0,0x4b,0x90,0x9e,0x14,0x74, ++0x01,0xf0,0x7f,0x80,0x7e,0x08,0x12,0x22,0x65,0x90,0x9e,0x16,0x12,0x25,0x08,0xab, ++0x59,0xaa,0x5a,0xa9,0x5b,0x90,0x00,0x01,0x12,0x42,0x20,0xff,0xe4,0xfc,0xfd,0xfe, ++0x78,0x1a,0x12,0x24,0xf5,0xa8,0x04,0xa9,0x05,0xaa,0x06,0xab,0x07,0x90,0x9e,0x16, ++0x12,0x43,0x53,0xec,0x54,0x03,0xfc,0x12,0x43,0x46,0x90,0x9e,0x20,0x12,0x25,0x08, ++0x90,0x05,0x22,0xe4,0xf0,0x80,0x2d,0xe4,0x90,0x9e,0x14,0xf0,0x7f,0x80,0x7e,0x08, ++0x12,0x22,0x65,0xec,0x54,0x03,0xfc,0xec,0x44,0xc0,0xfc,0x90,0x9e,0x16,0x12,0x25, ++0x08,0x90,0x9e,0x16,0x12,0x43,0x53,0x90,0x80,0x96,0x12,0x25,0x08,0x7f,0x80,0x7e, ++0x08,0x12,0x2b,0x08,0x90,0x9e,0x1d,0xe0,0x30,0xe1,0x19,0x7d,0x0c,0x7f,0x47,0x51, ++0xc1,0x90,0x00,0x48,0xe0,0x44,0x0c,0xfd,0x7f,0x48,0x51,0xc1,0x90,0x00,0x46,0xe0, ++0x44,0x10,0x80,0x1c,0x90,0x00,0x47,0xe0,0x54,0xf3,0xfd,0x7f,0x47,0x51,0xc1,0x90, ++0x00,0x48,0xe0,0x54,0xf3,0xfd,0x7f,0x48,0x51,0xc1,0x90,0x00,0x46,0xe0,0x54,0xef, ++0xfd,0x7f,0x46,0x51,0xc1,0xe4,0x90,0x9e,0x1a,0xf0,0x22,0x90,0x01,0x3c,0x74,0xff, ++0xf0,0xa3,0xf0,0xa3,0xf0,0x90,0x01,0x34,0xf0,0xa3,0xf0,0xa3,0xf0,0xa3,0xf0,0xfd, ++0x7f,0x54,0x51,0xc1,0x7d,0xff,0x7f,0x55,0x51,0xc1,0x7d,0xff,0x7f,0x56,0x51,0xc1, ++0x7d,0xff,0x7f,0x57,0x41,0xc1,0x90,0x01,0x30,0xe4,0xf0,0xa3,0xf0,0xa3,0xf0,0xa3, ++0xf0,0x90,0x01,0x38,0xf0,0xa3,0xf0,0xa3,0xf0,0xa3,0xf0,0xfd,0x7f,0x50,0x51,0xc1, ++0xe4,0xfd,0x7f,0x51,0x51,0xc1,0xe4,0xfd,0x7f,0x52,0x51,0xc1,0xe4,0xfd,0x7f,0x53, ++0x41,0xc1,0xe5,0x22,0x64,0x01,0x70,0x3c,0xf1,0xbe,0xbf,0x01,0x05,0x7f,0x01,0x12, ++0x44,0xf1,0x90,0x00,0x46,0xe0,0x44,0x04,0xfd,0x7f,0x46,0x51,0xc1,0x90,0x00,0x44, ++0xe0,0x54,0xfb,0xfd,0x7f,0x44,0x51,0xc1,0x90,0x00,0x46,0xe0,0x54,0xfb,0xfd,0x7f, ++0x46,0x51,0xc1,0x7f,0x02,0xf1,0xea,0x8f,0x26,0x90,0x01,0xc9,0xe5,0x26,0xf0,0xb4, ++0x01,0x02,0xf1,0x2a,0x22,0x90,0x9e,0x1c,0xe0,0x64,0x01,0x60,0x02,0xc1,0xd7,0x90, ++0x00,0x46,0xe0,0x44,0x01,0xfd,0x7f,0x46,0x51,0xc1,0x90,0x9e,0x2e,0xe0,0x70,0x31, ++0x90,0x9e,0x14,0xe0,0x60,0x15,0x90,0x9e,0x20,0x12,0x43,0x53,0x90,0x80,0x96,0x12, ++0x25,0x08,0x7f,0x80,0x7e,0x08,0x12,0x2b,0x08,0x80,0x06,0x90,0x05,0x22,0x74,0x7f, ++0xf0,0x90,0x9e,0x1b,0xe0,0xff,0xd1,0xd8,0x90,0x9e,0x2e,0x74,0x01,0x51,0xb7,0x80, ++0x3f,0x90,0x9e,0x2e,0xe0,0x64,0x01,0x70,0x37,0x90,0x9e,0x1f,0xe0,0xff,0xd1,0xd8, ++0xe4,0x90,0x9e,0x2e,0xf0,0x90,0x00,0x45,0xe0,0x44,0x01,0xfd,0x7f,0x45,0x51,0xc1, ++0x90,0x9e,0x14,0xe0,0x60,0x15,0x90,0x9e,0x16,0x12,0x43,0x53,0x90,0x80,0x96,0x12, ++0x25,0x08,0x7f,0x80,0x7e,0x08,0x12,0x2b,0x08,0x80,0x05,0x90,0x05,0x22,0xe4,0xf0, ++0x90,0x05,0x87,0xe0,0x64,0x80,0xf0,0x90,0x9e,0x2a,0xe0,0x90,0x05,0x84,0xf0,0x90, ++0x9e,0x2b,0xe0,0x90,0x05,0x85,0xf0,0x90,0x9e,0x2c,0xe0,0x90,0x05,0x86,0xf0,0x90, ++0x9e,0x2d,0xe0,0x90,0x05,0x87,0xf0,0x22,0x90,0x05,0x60,0xe0,0x90,0x9e,0x2a,0xf0, ++0x90,0x05,0x61,0xe0,0x90,0x9e,0x2b,0xf0,0x90,0x05,0x62,0xe0,0x90,0x9e,0x2c,0xf0, ++0x90,0x05,0x63,0xe0,0x90,0x9e,0x2d,0xf0,0xc3,0x74,0xff,0x9f,0xfe,0x90,0x9e,0x2b, ++0xe0,0xd3,0x9e,0x40,0x1e,0xe0,0x2f,0xf0,0xa3,0xe0,0xb4,0xff,0x0f,0xe4,0xf0,0xa3, ++0xe0,0xb4,0xff,0x03,0xe4,0xf0,0x22,0x90,0x9e,0x2d,0x80,0x03,0x90,0x9e,0x2c,0xe0, ++0x04,0xf0,0x22,0x90,0x9e,0x2b,0xe0,0x2f,0xf0,0x22,0x90,0x00,0x49,0xe0,0x90,0x9e, ++0xb1,0xf0,0xe0,0x54,0x0f,0xf0,0x44,0xf0,0xfd,0x7f,0x49,0x51,0xc1,0x90,0x9e,0xb1, ++0xe0,0x44,0xb0,0xfd,0x7f,0x49,0x41,0xc1,0x8e,0x59,0x8f,0x5a,0x8b,0x5b,0x8a,0x5c, ++0x89,0x5d,0xe4,0x90,0x9e,0x34,0xf0,0xef,0x90,0x00,0x31,0xf0,0x31,0xb9,0xe5,0x59, ++0x54,0x03,0xff,0x90,0x00,0x32,0xe0,0x54,0xfc,0x4f,0xf0,0x31,0xb9,0x90,0x00,0x33, ++0xe0,0x54,0x7f,0xf0,0x31,0xb9,0x90,0x00,0x33,0xe0,0x20,0xe7,0x0e,0x90,0x9e,0x34, ++0xe0,0xc3,0x94,0x64,0x50,0x05,0xe0,0x04,0xf0,0x80,0xeb,0x90,0x9e,0x34,0xe0,0xc3, ++0x94,0x64,0x50,0x10,0x90,0x00,0x30,0xe0,0xab,0x5b,0xaa,0x5c,0xa9,0x5d,0x12,0x42, ++0x4d,0x7f,0x01,0x22,0x7f,0x00,0x22,0x12,0x45,0xb1,0xbf,0x01,0x10,0x90,0x02,0x09, ++0xe0,0xff,0x7d,0x01,0x12,0x47,0xfe,0x90,0x04,0x1f,0x74,0x20,0xf0,0x22,0x7f,0x0b, ++0xf1,0xea,0xef,0x65,0x25,0x60,0x10,0xe5,0x25,0xb4,0x01,0x05,0xe4,0xf5,0x25,0x80, ++0x03,0x75,0x25,0x01,0x7f,0x01,0x22,0x7f,0x00,0x22,0xe4,0x90,0x9e,0x74,0xf0,0x90, ++0x00,0x80,0xe0,0x44,0x80,0xfd,0x7f,0x80,0x41,0xc1,0xd3,0x10,0xaf,0x01,0xc3,0xc0, ++0xd0,0x90,0x9e,0xb2,0xef,0xf0,0xd3,0x94,0x07,0x50,0x47,0xe0,0xff,0x74,0x01,0xa8, ++0x07,0x08,0x80,0x02,0xc3,0x33,0xd8,0xfc,0xf4,0xff,0x90,0x00,0x46,0xe0,0x5f,0xf0, ++0x12,0x49,0xb9,0x90,0x9e,0xb2,0xe0,0xfd,0x74,0x01,0x7e,0x00,0xa8,0x05,0x08,0x80, ++0x05,0xc3,0x33,0xce,0x33,0xce,0xd8,0xf9,0xff,0x90,0x00,0x44,0xe0,0xfb,0xe4,0xfe, ++0xef,0x5b,0xa8,0x05,0x08,0x80,0x06,0xce,0xa2,0xe7,0x13,0xce,0x13,0xd8,0xf8,0xff, ++0x80,0x44,0x90,0x9e,0xb2,0xe0,0x24,0xf8,0xf0,0xe0,0xff,0x74,0x01,0xa8,0x07,0x08, ++0x80,0x02,0xc3,0x33,0xd8,0xfc,0x12,0x49,0xb1,0x90,0x9e,0xb2,0xe0,0xfd,0x74,0x01, ++0x7e,0x00,0xa8,0x05,0x08,0x80,0x05,0xc3,0x33,0xce,0x33,0xce,0xd8,0xf9,0xff,0x90, ++0x00,0x42,0xe0,0xfb,0xe4,0xfe,0xef,0x5b,0xa8,0x05,0x08,0x80,0x06,0xce,0xa2,0xe7, ++0x13,0xce,0x13,0xd8,0xf8,0xff,0xd0,0xd0,0x92,0xaf,0x22,0x75,0x28,0x33,0xe4,0xf5, ++0x29,0x75,0x2a,0x03,0xf5,0x2b,0x90,0x01,0x30,0xe5,0x28,0xf0,0xa3,0xe5,0x29,0xf0, ++0xa3,0xe5,0x2a,0xf0,0xa3,0xe5,0x2b,0xf0,0x22,0xe4,0x90,0x9e,0x31,0xf0,0xa3,0xf0, ++0x75,0x8e,0x02,0x12,0x4f,0xda,0x12,0x5f,0xa9,0x12,0x5f,0xbc,0xe4,0xf5,0x12,0x12, ++0x6f,0xa1,0x12,0x77,0x5d,0x12,0x60,0x9b,0x12,0x2e,0x01,0x12,0x77,0x18,0x11,0x8b, ++0x90,0x00,0xf3,0xe0,0x30,0xe2,0x0d,0x90,0x05,0x41,0x74,0x10,0xf0,0x90,0x05,0x5a, ++0xf0,0xa3,0xe4,0xf0,0x12,0x5f,0xf4,0x12,0x5f,0x91,0x12,0x44,0xfe,0x12,0x7d,0x1d, ++0x90,0x9e,0x33,0xe5,0xd9,0xf0,0x12,0x4d,0x8b,0xc2,0xaf,0x90,0x00,0x80,0xe0,0x44, ++0x40,0xf0,0x12,0x49,0xb9,0x75,0xe8,0x03,0x43,0xa8,0x85,0xd2,0xaf,0x90,0x01,0xbe, ++0xe0,0x04,0xf0,0x90,0x01,0xc0,0xe0,0x04,0xf0,0x90,0x9e,0x31,0xe0,0x64,0x01,0xf0, ++0x24,0xa9,0x90,0x01,0xc4,0xf0,0x74,0x50,0xa3,0xf0,0xe5,0x12,0x30,0xe4,0x09,0xc2, ++0xaf,0x53,0x12,0xef,0xd2,0xaf,0x31,0x8e,0xe5,0x12,0x30,0xe6,0x17,0xc2,0xaf,0x53, ++0x12,0xbf,0xd2,0xaf,0x12,0x69,0x51,0x90,0x9e,0x1e,0xe0,0xff,0x60,0x03,0xb4,0x01, ++0x03,0x12,0x7d,0x7b,0x90,0x9e,0x1e,0xe0,0x70,0x03,0x12,0x7e,0x7e,0x31,0x61,0x80, ++0xb8,0x90,0x06,0x34,0xe0,0x60,0x26,0x14,0x70,0x1b,0x7b,0x01,0x7a,0x06,0x79,0x35, ++0x7f,0xf9,0x7e,0x01,0x12,0x4f,0x48,0xbf,0x01,0x09,0x90,0x06,0x35,0xe0,0x54,0x0f, ++0xf0,0x80,0x05,0x80,0x00,0x02,0x77,0x0a,0xe4,0x90,0x06,0x34,0xf0,0x22,0x90,0x01, ++0xcc,0xe0,0x54,0x0f,0x90,0x9e,0x34,0xf0,0x90,0x9e,0x34,0xe0,0xfd,0x70,0x02,0x41, ++0xcf,0x90,0x9e,0xae,0xe0,0xff,0x74,0x01,0x7e,0x00,0xa8,0x07,0x08,0x80,0x05,0xc3, ++0x33,0xce,0x33,0xce,0xd8,0xf9,0xff,0xef,0x5d,0x70,0x02,0x41,0xc8,0x90,0x9e,0xae, ++0xe0,0x75,0xf0,0x04,0x90,0x01,0xd0,0x12,0x43,0x5f,0xe0,0x90,0x9e,0x35,0xf0,0x75, ++0x1e,0x01,0x75,0x1f,0x9e,0x75,0x20,0x35,0x75,0x21,0x01,0x7b,0x01,0x7a,0x9e,0x79, ++0x36,0x12,0x45,0x09,0x90,0x9e,0x36,0xe0,0xff,0xc4,0x13,0x13,0x13,0x54,0x01,0x90, ++0x9e,0xae,0x30,0xe0,0x59,0xe0,0x75,0xf0,0x02,0x90,0x00,0x88,0x12,0x43,0x5f,0xe0, ++0x90,0x9e,0x37,0xf0,0x90,0x9e,0xae,0xe0,0x75,0xf0,0x02,0x90,0x00,0x89,0x12,0x43, ++0x5f,0xe0,0x90,0x9e,0x38,0xf0,0x90,0x9e,0xae,0xe0,0x75,0xf0,0x04,0x90,0x01,0xd1, ++0x12,0x43,0x5f,0xe0,0x90,0x9e,0x39,0xf0,0x90,0x9e,0xae,0xe0,0x75,0xf0,0x04,0x90, ++0x01,0xd2,0x12,0x43,0x5f,0xe0,0x90,0x9e,0x3a,0xf0,0x90,0x9e,0xae,0xe0,0x75,0xf0, ++0x04,0x90,0x01,0xd3,0x12,0x43,0x5f,0xe0,0x90,0x9e,0x3b,0xf0,0x80,0x33,0xe0,0x75, ++0xf0,0x04,0x90,0x01,0xd1,0x12,0x43,0x5f,0xe0,0x90,0x9e,0x37,0xf0,0x90,0x9e,0xae, ++0xe0,0x75,0xf0,0x04,0x90,0x01,0xd2,0x12,0x43,0x5f,0xe0,0x90,0x9e,0x38,0xf0,0x90, ++0x9e,0xae,0xe0,0x75,0xf0,0x04,0x90,0x01,0xd3,0x12,0x43,0x5f,0xe0,0x90,0x9e,0x39, ++0xf0,0xef,0x54,0x7f,0xff,0x7b,0x01,0x7a,0x9e,0x79,0x37,0x51,0xd0,0x90,0x9e,0x34, ++0xe0,0xff,0x90,0x9e,0xae,0xe0,0xfe,0x74,0x01,0xa8,0x06,0x08,0x80,0x02,0xc3,0x33, ++0xd8,0xfc,0xf4,0x5f,0x90,0x9e,0x34,0xf0,0x90,0x9e,0xae,0xe0,0xff,0x74,0x01,0xa8, ++0x07,0x08,0x80,0x02,0xc3,0x33,0xd8,0xfc,0x90,0x01,0xcc,0xf0,0x90,0x9e,0xae,0xe0, ++0x04,0xf0,0xe0,0x54,0x03,0xf0,0x21,0x98,0x90,0x01,0xc6,0xe0,0x44,0x02,0xf0,0x22, ++0x90,0x9e,0x3c,0x12,0x43,0x8b,0xef,0x12,0x43,0x94,0x53,0x0b,0x01,0x53,0x14,0x02, ++0x53,0x2f,0x03,0x53,0x38,0x05,0x53,0x41,0x06,0x53,0x8f,0x07,0x53,0x49,0x09,0x53, ++0x52,0x0c,0x53,0x5b,0x0d,0x53,0x64,0x0e,0x53,0x6d,0x1b,0x53,0x76,0x1c,0x53,0x7f, ++0x2c,0x53,0x1d,0x2d,0x53,0x26,0x2e,0x00,0x00,0x53,0x88,0x90,0x9e,0x3c,0x12,0x43, ++0x6b,0x02,0x61,0x9d,0x90,0x9e,0x3c,0x12,0x43,0x6b,0x02,0x71,0xc4,0x90,0x9e,0x3c, ++0x12,0x43,0x6b,0x02,0x71,0xca,0x90,0x9e,0x3c,0x12,0x43,0x6b,0x02,0x72,0x12,0x90, ++0x9e,0x3c,0x12,0x43,0x6b,0x02,0x72,0x40,0x90,0x9e,0x3c,0x12,0x43,0x6b,0x02,0x71, ++0x74,0x90,0x9e,0x3c,0x12,0x43,0x6b,0x80,0x47,0x90,0x9e,0x3c,0x12,0x43,0x6b,0x02, ++0x72,0x88,0x90,0x9e,0x3c,0x12,0x43,0x6b,0x02,0x4b,0x7e,0x90,0x9e,0x3c,0x12,0x43, ++0x6b,0x02,0x7c,0xea,0x90,0x9e,0x3c,0x12,0x43,0x6b,0x02,0x4c,0xb8,0x90,0x9e,0x3c, ++0x12,0x43,0x6b,0x02,0x71,0xbc,0x90,0x9e,0x3c,0x12,0x43,0x6b,0x02,0x71,0xa3,0x90, ++0x9e,0x3c,0x12,0x43,0x6b,0x02,0x75,0xea,0x90,0x01,0xc6,0xe0,0x44,0x01,0xf0,0x22, ++0x90,0x00,0x04,0x12,0x42,0x20,0xff,0x54,0x1f,0xfe,0xef,0x54,0x20,0xc4,0x13,0x54, ++0x07,0xfd,0xaf,0x06,0x90,0x9e,0x3f,0xef,0xf0,0xa3,0xed,0xf0,0xa3,0x12,0x43,0x8b, ++0x90,0x9e,0x41,0x12,0x43,0x6b,0x90,0x00,0x03,0x12,0x42,0x20,0x54,0xf0,0xc4,0x54, ++0x0f,0x90,0x9e,0x44,0xf0,0x90,0x00,0x04,0x12,0x42,0x20,0x54,0x40,0xc4,0x13,0x13, ++0x54,0x03,0x90,0x9e,0x45,0xf0,0x90,0x9e,0x3f,0xe0,0xff,0x75,0xf0,0x09,0x90,0x96, ++0x46,0x12,0x43,0x5f,0xad,0x82,0xac,0x83,0x90,0x9e,0x46,0xec,0xf0,0xa3,0xed,0xf0, ++0xef,0x75,0xf0,0x09,0xa4,0x24,0x44,0xf9,0x74,0x96,0x35,0xf0,0xfa,0x7b,0x01,0xa3, ++0x12,0x43,0x8b,0x90,0x9e,0x41,0x12,0x43,0x6b,0x90,0x00,0x03,0x12,0x42,0x20,0x54, ++0x0f,0xff,0x90,0x9e,0x48,0x12,0x43,0x6b,0xef,0x12,0x42,0x4d,0x90,0x9e,0x41,0x12, ++0x43,0x6b,0x90,0x00,0x02,0x12,0x42,0x20,0xff,0x90,0x9e,0x48,0x12,0x43,0x6b,0x90, ++0x00,0x01,0xef,0x12,0x42,0x5f,0x90,0x9e,0x41,0x12,0x43,0x6b,0x90,0x00,0x01,0x12, ++0x42,0x20,0xff,0x90,0x9e,0x46,0xe0,0xfc,0xa3,0xe0,0xfd,0xf5,0x82,0x8c,0x83,0xef, ++0xf0,0x12,0x24,0x62,0x8d,0x82,0x8c,0x83,0xa3,0xf0,0x90,0x9e,0x44,0xe0,0xfe,0x90, ++0x9e,0x3f,0xe0,0xff,0x24,0x82,0xf5,0x82,0xe4,0x34,0x95,0xf5,0x83,0xee,0xf0,0x90, ++0x9e,0x40,0xe0,0xfe,0x75,0xf0,0x09,0xef,0x90,0x96,0x4a,0x12,0x43,0x5f,0xee,0xf0, ++0x75,0xf0,0x09,0xef,0x90,0x96,0x4b,0x12,0x43,0x5f,0x74,0x01,0xf0,0x90,0x9e,0x45, ++0xe0,0xfe,0x75,0xf0,0x09,0xef,0x90,0x96,0x4c,0x12,0x43,0x5f,0xee,0xf0,0x8f,0x59, ++0xef,0x25,0xe0,0x24,0xc6,0xf5,0x82,0xe4,0x34,0x9b,0xaf,0x82,0xf5,0x5b,0x8f,0x5c, ++0xe5,0x59,0x75,0xf0,0x02,0xa4,0x24,0x02,0xf9,0x74,0x95,0x35,0xf0,0x75,0x5d,0x01, ++0xf5,0x5e,0x89,0x5f,0x75,0xf0,0x09,0xe5,0x59,0x90,0x96,0x46,0x12,0x43,0x5f,0xaf, ++0x82,0x85,0x83,0x60,0x8f,0x61,0xe5,0x59,0x75,0xf0,0x09,0xa4,0x24,0x44,0xf9,0x74, ++0x96,0x35,0xf0,0x75,0x62,0x01,0xf5,0x63,0x89,0x64,0x74,0x82,0x25,0x59,0xf5,0x82, ++0xe4,0x34,0x95,0xf5,0x83,0xe0,0x12,0x43,0x94,0x55,0x1e,0x00,0x55,0x33,0x01,0x55, ++0x48,0x02,0x55,0x5d,0x03,0x55,0x86,0x04,0x55,0x9b,0x05,0x55,0xb0,0x06,0x55,0xd6, ++0x0c,0x56,0x03,0x0d,0x56,0x30,0x0e,0x56,0x5d,0x0f,0x00,0x00,0x56,0x91,0xe5,0x59, ++0x25,0xe0,0x24,0xc6,0xf5,0x82,0xe4,0x34,0x9b,0xf5,0x83,0x74,0xf0,0xf0,0xa3,0x74, ++0x15,0x80,0x3c,0xe5,0x59,0x25,0xe0,0x24,0xc6,0xf5,0x82,0xe4,0x34,0x9b,0xf5,0x83, ++0x74,0xf0,0xf0,0xa3,0x74,0x10,0x80,0x27,0xe5,0x59,0x25,0xe0,0x24,0xc6,0xf5,0x82, ++0xe4,0x34,0x9b,0xf5,0x83,0x74,0xf0,0xf0,0xa3,0x74,0x05,0x80,0x12,0xe5,0x59,0x25, ++0xe0,0x24,0xc6,0xf5,0x82,0xe4,0x34,0x9b,0xf5,0x83,0x74,0xf0,0xf0,0xa3,0xe4,0xf0, ++0xe5,0x59,0x25,0xe0,0x24,0x02,0xf5,0x82,0xe4,0x34,0x95,0xf5,0x83,0x74,0x0f,0xf0, ++0xa3,0x74,0x8f,0xf0,0xc1,0x91,0xe5,0x59,0x25,0xe0,0x24,0xc6,0xf5,0x82,0xe4,0x34, ++0x9b,0xf5,0x83,0x74,0x0f,0xf0,0xa3,0x74,0xf5,0x80,0x27,0xe5,0x59,0x25,0xe0,0x24, ++0xc6,0xf5,0x82,0xe4,0x34,0x9b,0xf5,0x83,0x74,0x0f,0xf0,0xa3,0x74,0xf0,0x80,0x12, ++0xe5,0x59,0x25,0xe0,0x24,0xc6,0xf5,0x82,0xe4,0x34,0x9b,0xf5,0x83,0xe4,0xf0,0xa3, ++0x74,0x0d,0xf0,0xe5,0x59,0x25,0xe0,0x24,0x02,0xf5,0x82,0xe4,0x34,0x95,0xf5,0x83, ++0xe4,0xf0,0xa3,0xf0,0xc1,0x91,0x90,0x04,0x47,0xe0,0xab,0x5d,0xaa,0x5e,0xa9,0x5f, ++0x12,0x42,0x4d,0x90,0x04,0x46,0xe0,0xab,0x5d,0xaa,0x5e,0xa9,0x5f,0x90,0x00,0x01, ++0x12,0x42,0x5f,0x90,0x04,0x45,0xe0,0x85,0x5c,0x82,0x85,0x5b,0x83,0xf0,0x90,0x04, ++0x44,0xc1,0x88,0x90,0x04,0x4b,0xe0,0xab,0x5d,0xaa,0x5e,0xa9,0x5f,0x12,0x42,0x4d, ++0x90,0x04,0x4a,0xe0,0xab,0x5d,0xaa,0x5e,0xa9,0x5f,0x90,0x00,0x01,0x12,0x42,0x5f, ++0x90,0x04,0x49,0xe0,0x85,0x5c,0x82,0x85,0x5b,0x83,0xf0,0x90,0x04,0x48,0x80,0x58, ++0x90,0x04,0x4f,0xe0,0xab,0x5d,0xaa,0x5e,0xa9,0x5f,0x12,0x42,0x4d,0x90,0x04,0x4e, ++0xe0,0xab,0x5d,0xaa,0x5e,0xa9,0x5f,0x90,0x00,0x01,0x12,0x42,0x5f,0x90,0x04,0x4d, ++0xe0,0x85,0x5c,0x82,0x85,0x5b,0x83,0xf0,0x90,0x04,0x4c,0x80,0x2b,0x90,0x04,0x53, ++0xe0,0xab,0x5d,0xaa,0x5e,0xa9,0x5f,0x12,0x42,0x4d,0x90,0x04,0x52,0xe0,0xab,0x5d, ++0xaa,0x5e,0xa9,0x5f,0x90,0x00,0x01,0x12,0x42,0x5f,0x90,0x04,0x51,0xe0,0x85,0x5c, ++0x82,0x85,0x5b,0x83,0xf0,0x90,0x04,0x50,0xe0,0x85,0x5c,0x82,0x85,0x5b,0x83,0xa3, ++0xf0,0xab,0x5d,0xaa,0x5e,0xa9,0x5f,0xc0,0x03,0xc0,0x02,0xc0,0x01,0x12,0x24,0x62, ++0xff,0xab,0x62,0xaa,0x63,0xa9,0x64,0x12,0x24,0x62,0x5f,0xd0,0x01,0xd0,0x02,0xd0, ++0x03,0x12,0x42,0x4d,0xab,0x5d,0xe5,0x5f,0x24,0x01,0xf9,0xe4,0x35,0x5e,0xfa,0xc0, ++0x03,0xc0,0x02,0xc0,0x01,0x12,0x24,0x62,0xff,0xab,0x62,0xaa,0x63,0xa9,0x64,0x90, ++0x00,0x01,0x12,0x42,0x20,0x5f,0xd0,0x01,0xd0,0x02,0xd0,0x03,0x12,0x42,0x4d,0x85, ++0x5c,0x82,0x85,0x5b,0x83,0xc0,0x83,0xc0,0x82,0xe0,0xff,0x85,0x61,0x82,0x85,0x60, ++0x83,0xe0,0xfe,0xef,0x5e,0xd0,0x82,0xd0,0x83,0xf0,0x85,0x5c,0x82,0x85,0x5b,0x83, ++0xa3,0xc0,0x83,0xc0,0x82,0xe0,0xff,0x85,0x61,0x82,0x85,0x60,0x83,0xa3,0xe0,0xfe, ++0xef,0x5e,0xd0,0x82,0xd0,0x83,0xf0,0xe5,0x59,0x25,0xe0,0x24,0x02,0xf5,0x82,0xe4, ++0x34,0x95,0xf5,0x83,0xe0,0xfe,0xa3,0xe0,0x4e,0x60,0x3b,0x75,0x5a,0x0b,0x74,0x01, ++0x7e,0x00,0xa8,0x5a,0x08,0x80,0x05,0xc3,0x33,0xce,0x33,0xce,0xd8,0xf9,0xff,0xe5, ++0x59,0x25,0xe0,0x24,0x02,0xf5,0x82,0xe4,0x34,0x95,0xf5,0x83,0xe0,0x5e,0xfe,0xa3, ++0xe0,0x5f,0x4e,0x60,0x06,0xe5,0x5a,0x24,0x10,0x80,0x5d,0x15,0x5a,0xe5,0x5a,0xc3, ++0x94,0x00,0x50,0xca,0x80,0x56,0xe5,0x59,0x25,0xe0,0x24,0xc6,0xf5,0x82,0xe4,0x34, ++0x9b,0xf5,0x83,0xe0,0xfe,0xa3,0xe0,0x4e,0x60,0x3d,0x75,0x5a,0x0f,0x74,0x01,0x7e, ++0x00,0xa8,0x5a,0x08,0x80,0x05,0xc3,0x33,0xce,0x33,0xce,0xd8,0xf9,0xff,0xe5,0x59, ++0x25,0xe0,0x24,0xc6,0xf5,0x82,0xe4,0x34,0x9b,0xf5,0x83,0xe0,0x5e,0xfe,0xa3,0xe0, ++0x5f,0x4e,0x60,0x08,0x90,0x9e,0x4b,0xe5,0x5a,0xf0,0x80,0x10,0x15,0x5a,0xe5,0x5a, ++0xc3,0x94,0x00,0x50,0xc8,0x80,0x05,0xe4,0x90,0x9e,0x4b,0xf0,0xe5,0x59,0x25,0xe0, ++0x24,0xc6,0xf5,0x82,0xe4,0x34,0x9b,0xf5,0x83,0xe0,0xfe,0xa3,0xe0,0x4e,0x60,0x3b, ++0xe4,0xf5,0x5a,0x74,0x01,0x7e,0x00,0xa8,0x5a,0x08,0x80,0x05,0xc3,0x33,0xce,0x33, ++0xce,0xd8,0xf9,0xff,0xe5,0x59,0x25,0xe0,0x24,0xc6,0xf5,0x82,0xe4,0x34,0x9b,0xf5, ++0x83,0xe0,0x5e,0xfe,0xa3,0xe0,0x5f,0x4e,0x60,0x08,0x90,0x9e,0x4c,0xe5,0x5a,0xf0, ++0x80,0x5b,0x05,0x5a,0xe5,0x5a,0xb4,0x10,0xca,0x80,0x52,0xe5,0x59,0x25,0xe0,0x24, ++0x02,0xf5,0x82,0xe4,0x34,0x95,0xf5,0x83,0xe0,0xfe,0xa3,0xe0,0x4e,0x60,0x39,0xe4, ++0xf5,0x5a,0x74,0x01,0x7e,0x00,0xa8,0x5a,0x08,0x80,0x05,0xc3,0x33,0xce,0x33,0xce, ++0xd8,0xf9,0xff,0xe5,0x59,0x25,0xe0,0x24,0x02,0xf5,0x82,0xe4,0x34,0x95,0xf5,0x83, ++0xe0,0x5e,0xfe,0xa3,0xe0,0x5f,0x4e,0x60,0x06,0xe5,0x5a,0x24,0x10,0x80,0x0a,0x05, ++0x5a,0xe5,0x5a,0xb4,0x0c,0xcc,0x80,0x05,0xe4,0x90,0x9e,0x4c,0xf0,0x90,0x9e,0x4b, ++0xe0,0xff,0x75,0xf0,0x09,0xe5,0x59,0x90,0x96,0x48,0x12,0x43,0x5f,0xef,0xf0,0x90, ++0x9e,0x4c,0xe0,0xfe,0x75,0xf0,0x09,0xe5,0x59,0x90,0x96,0x49,0x12,0x43,0x5f,0xee, ++0xf0,0x74,0x84,0x25,0x59,0xf5,0x82,0xe4,0x34,0x04,0xf5,0x83,0xe0,0xd3,0x9f,0x40, ++0x05,0x90,0x9e,0x4b,0x11,0xe0,0x74,0x84,0x25,0x59,0xf5,0x82,0xe4,0x34,0x04,0xf5, ++0x83,0xe0,0xff,0x90,0x9e,0x4c,0xe0,0xfe,0xef,0xc3,0x9e,0x50,0x02,0x11,0xe0,0x90, ++0x9e,0x4b,0xe0,0xff,0xd3,0x94,0x13,0x40,0x07,0x90,0x96,0x43,0x74,0x03,0xf0,0x22, ++0xef,0xd3,0x94,0x0b,0x40,0x07,0x90,0x96,0x43,0x74,0x02,0xf0,0x22,0xef,0xd3,0x94, ++0x03,0x40,0x07,0x90,0x96,0x43,0x74,0x01,0xf0,0x22,0xe4,0x90,0x96,0x43,0xf0,0x22, ++0xe0,0xfd,0x74,0x26,0x25,0x59,0xf5,0x82,0xe4,0x34,0x9d,0xf5,0x83,0xed,0xf0,0xaf, ++0x59,0xd3,0x10,0xaf,0x01,0xc3,0xc0,0xd0,0xef,0xc3,0x94,0x20,0x50,0x0e,0x74,0x84, ++0x2f,0xf5,0x82,0xe4,0x34,0x04,0xf5,0x83,0xed,0xf0,0x80,0x29,0x74,0xa6,0x2f,0xf5, ++0x82,0xe4,0x34,0x9c,0xf5,0x83,0xed,0xf0,0x90,0x9e,0x78,0xef,0xf0,0x24,0xa6,0xf5, ++0x82,0xe4,0x34,0x9c,0xf5,0x83,0xe0,0x90,0x9e,0x79,0xf0,0x7b,0x01,0x7a,0x9e,0x79, ++0x78,0x7d,0x02,0x31,0x3a,0xd0,0xd0,0x92,0xaf,0x22,0xd3,0x10,0xaf,0x01,0xc3,0xc0, ++0xd0,0x90,0x9e,0x97,0x12,0x43,0x8b,0x90,0x9e,0x9a,0xe0,0x54,0xf0,0x44,0x06,0xff, ++0xf0,0xed,0x54,0x0f,0xc4,0x54,0xf0,0xfe,0xef,0x54,0x0f,0x4e,0xf0,0x90,0x9e,0x97, ++0x12,0x43,0x6b,0x90,0x9e,0x94,0x12,0x43,0x8b,0x7b,0x01,0x7a,0x9e,0x79,0x9a,0xd1, ++0x14,0xd0,0xd0,0x92,0xaf,0x22,0x8f,0x50,0x8d,0x51,0xe5,0x51,0x54,0x1f,0xf5,0x56, ++0x74,0x01,0x2f,0xf5,0x82,0xe4,0x34,0x94,0xf5,0x83,0xe0,0xf5,0x54,0x90,0x04,0xfd, ++0xe0,0xb4,0x01,0x05,0x75,0x57,0x03,0x80,0x03,0x75,0x57,0x01,0xeb,0xc3,0x95,0x57, ++0x40,0x04,0xaf,0x50,0x80,0x33,0xe5,0x54,0x25,0x53,0xf5,0x55,0xe5,0x56,0x90,0x41, ++0xd6,0x93,0xff,0xe5,0x55,0xd3,0x9f,0x74,0x01,0x40,0x11,0x25,0x50,0xf5,0x82,0xe4, ++0x34,0x94,0xf5,0x83,0xe4,0xf0,0xad,0x51,0xaf,0x50,0x01,0xf1,0x25,0x50,0xf5,0x82, ++0xe4,0x34,0x94,0xf5,0x83,0xe5,0x55,0xf0,0x22,0xad,0x07,0x75,0xf0,0x09,0xed,0x90, ++0x96,0x48,0x12,0x43,0x5f,0xe0,0xff,0x74,0x67,0x2d,0xf5,0x82,0xe4,0x34,0x9d,0xf5, ++0x83,0xe0,0x54,0x1f,0xf5,0x58,0xd3,0x9f,0x40,0x02,0x8f,0x58,0xe5,0x58,0x25,0xe0, ++0x24,0x9e,0xf5,0x82,0xe4,0x34,0x41,0xf5,0x83,0xe4,0x93,0xfe,0x74,0x01,0x93,0xff, ++0xe5,0x58,0x25,0xe0,0x24,0x66,0xf5,0x82,0xe4,0x34,0x41,0xf5,0x83,0x74,0x01,0x93, ++0x2f,0xff,0xe4,0x93,0x3e,0xc3,0x13,0xfe,0xef,0x13,0xff,0xed,0x25,0xe0,0x24,0xc2, ++0xf5,0x82,0xe4,0x34,0x95,0xf5,0x83,0xee,0xf0,0xa3,0xef,0xf0,0xaf,0x05,0xad,0x58, ++0x11,0xf1,0xaf,0x58,0x22,0xc0,0xe0,0xc0,0xf0,0xc0,0x83,0xc0,0x82,0xc0,0xd0,0x75, ++0xd0,0x00,0xc0,0x00,0xc0,0x01,0xc0,0x02,0xc0,0x03,0xc0,0x04,0xc0,0x05,0xc0,0x06, ++0xc0,0x07,0x90,0x01,0xc4,0x74,0x45,0xf0,0x74,0x5a,0xa3,0xf0,0x90,0x01,0x34,0xe0, ++0x55,0x28,0xf5,0x2c,0x90,0x01,0x36,0xe0,0x55,0x2a,0xf5,0x2e,0xa3,0xe0,0x55,0x2b, ++0xf5,0x2f,0xe5,0x2c,0x20,0xe0,0x02,0x61,0xe1,0x90,0x01,0x34,0x74,0x01,0xf0,0x85, ++0xd1,0x08,0x85,0xd2,0x09,0x85,0xd3,0x0a,0x85,0xd4,0x0b,0x85,0xd5,0x0c,0x85,0xd6, ++0x0d,0x85,0xd7,0x0e,0x85,0xd9,0x0f,0xe5,0x0f,0x54,0x40,0xc3,0x13,0xff,0xe5,0x0e, ++0x54,0x20,0x6f,0x70,0x02,0x61,0x93,0xe5,0x0f,0x30,0xe5,0x02,0x61,0x93,0xe5,0x0d, ++0x54,0x3f,0xf5,0x4d,0xe5,0x08,0x54,0x3f,0xf5,0x4e,0xe5,0x0c,0x54,0x1f,0xff,0xe5, ++0x4d,0x25,0xe0,0x24,0xc4,0xf5,0x82,0xe4,0x34,0x99,0xf5,0x83,0xe4,0x8f,0xf0,0x12, ++0x42,0x81,0xe5,0x0e,0x54,0x1f,0xff,0xe5,0x4d,0x25,0xe0,0x24,0x80,0xf5,0x82,0xe4, ++0x34,0x93,0xf5,0x83,0xe4,0x8f,0xf0,0x12,0x42,0x81,0xe5,0x4e,0xd3,0x94,0x04,0x40, ++0x03,0x75,0x4e,0x04,0x75,0xf0,0x0a,0xe5,0x4d,0x90,0x90,0x00,0x12,0x43,0x5f,0x75, ++0xf0,0x02,0xe5,0x4e,0x12,0x43,0x5f,0xe0,0xfe,0xa3,0xe0,0xff,0xe5,0x0e,0x54,0x1f, ++0x2f,0xff,0xe4,0x3e,0xfe,0x75,0xf0,0x0a,0xe5,0x4d,0x90,0x90,0x00,0x12,0x43,0x5f, ++0x75,0xf0,0x02,0xe5,0x4e,0x12,0x43,0x5f,0xee,0xf0,0xa3,0xef,0xf0,0xe5,0x0f,0x20, ++0xe6,0x23,0xe5,0x0e,0x54,0x1f,0xff,0xe5,0x4d,0x25,0xe0,0x24,0xc4,0xf5,0x82,0xe4, ++0x34,0x98,0xf5,0x83,0xe4,0x8f,0xf0,0x12,0x42,0x81,0xe5,0x0a,0x30,0xe7,0x34,0xaf, ++0x4d,0x31,0xd9,0x80,0x2e,0xe5,0x0e,0x54,0x1f,0xff,0xe5,0x4d,0x25,0xe0,0x24,0x44, ++0xf5,0x82,0xe4,0x34,0x99,0xf5,0x83,0xe4,0x8f,0xf0,0x12,0x42,0x81,0xe5,0x0a,0x30, ++0xe7,0x11,0xe5,0x0a,0x54,0x7f,0xfd,0xe5,0x0e,0x54,0x1f,0xf5,0x53,0xab,0x4e,0xaf, ++0x4d,0x31,0x76,0xe5,0x74,0x14,0x24,0xfd,0x50,0x02,0x80,0x45,0x90,0x9e,0x61,0xe0, ++0x60,0x37,0x90,0x01,0x5b,0xe4,0xf0,0x90,0x01,0x3c,0x74,0x04,0xf0,0xd1,0x05,0xef, ++0x64,0x01,0x70,0x2d,0x90,0x9e,0x55,0xe0,0xf5,0x44,0x75,0x45,0x00,0xe4,0xfb,0xfd, ++0x7f,0x58,0x7e,0x01,0x12,0x30,0x62,0x90,0x01,0x5b,0x74,0x05,0xf0,0x90,0x06,0x92, ++0x74,0x01,0xf0,0x90,0x9e,0x5d,0xf0,0x80,0x08,0xd1,0x05,0xbf,0x01,0x03,0x12,0x44, ++0xd3,0xe5,0x2c,0x30,0xe1,0x20,0x90,0x01,0x34,0x74,0x02,0xf0,0x85,0xd1,0x13,0x85, ++0xd2,0x14,0x85,0xd3,0x15,0x85,0xd4,0x16,0x85,0xd5,0x17,0x85,0xd6,0x18,0x85,0xd7, ++0x19,0x85,0xd9,0x1a,0xd1,0x9c,0xe5,0x2c,0x30,0xe3,0x06,0x90,0x01,0x34,0x74,0x08, ++0xf0,0xe5,0x2c,0x30,0xe4,0x09,0x90,0x01,0x34,0x74,0x10,0xf0,0x43,0x12,0x10,0xe5, ++0x2c,0x30,0xe5,0x26,0x90,0x01,0xcf,0xe0,0x30,0xe5,0x1f,0xe0,0x54,0xdf,0xf0,0x90, ++0x01,0x34,0x74,0x20,0xf0,0x75,0xa8,0x00,0x75,0xe8,0x00,0x12,0x4d,0xb6,0x90,0x00, ++0x03,0xe0,0x54,0xfb,0xf0,0x12,0x49,0xb9,0x80,0xfe,0xe5,0x2c,0x30,0xe6,0x06,0x90, ++0x01,0x34,0x74,0x40,0xf0,0xe5,0x2e,0x30,0xe1,0x3c,0x90,0x01,0x36,0x74,0x02,0xf0, ++0x43,0x12,0x40,0x90,0x01,0x02,0xe0,0x54,0x03,0x64,0x01,0x70,0x29,0x90,0x01,0x37, ++0xe0,0x30,0xe0,0x0a,0x74,0x01,0xf0,0x90,0x9e,0x66,0xe4,0xf0,0x80,0x18,0x90,0x9e, ++0x66,0xe0,0x04,0xf0,0xe0,0xc3,0x94,0x0a,0x40,0x0c,0xe4,0xf0,0x90,0x04,0x19,0xe0, ++0x30,0xe0,0x03,0x12,0x4f,0xa7,0xe5,0x2e,0x30,0xe0,0x12,0x90,0x9e,0x76,0x74,0x01, ++0xf0,0x90,0x01,0x36,0xf0,0x12,0x64,0xfe,0x90,0x9e,0x76,0xe4,0xf0,0xe5,0x2e,0x30, ++0xe2,0x78,0x90,0x01,0x36,0x74,0x04,0xf0,0x90,0x01,0xbd,0xe0,0x04,0xf0,0xe5,0x73, ++0x64,0x01,0x70,0x66,0xe5,0x74,0x60,0x62,0xe5,0x74,0x64,0x02,0x60,0x06,0xe5,0x74, ++0x64,0x05,0x70,0x27,0x90,0x06,0xab,0xe0,0x90,0x9e,0x50,0xf0,0x90,0x06,0xaa,0xe0, ++0x90,0x9e,0x5f,0xf0,0x90,0x9e,0x50,0xe0,0x70,0x07,0x90,0x9e,0x5f,0xe0,0xff,0x80, ++0x05,0x90,0x9e,0x50,0xe0,0xff,0x90,0x9e,0x50,0xef,0xf0,0x90,0x9e,0x52,0xe0,0x60, ++0x03,0xe0,0x14,0xf0,0x90,0x9e,0x51,0xe4,0xf0,0x90,0x01,0x57,0xf0,0x90,0x01,0x3c, ++0x74,0x02,0xf0,0x90,0x9e,0x63,0xe0,0x54,0xfd,0xf0,0xe0,0x54,0xef,0xf0,0xe5,0x74, ++0x14,0x24,0xfd,0x50,0x02,0x80,0x03,0x12,0x45,0x53,0xe5,0x2e,0x30,0xe3,0x28,0x90, ++0x01,0x36,0x74,0x08,0xf0,0xe5,0x73,0x64,0x01,0x70,0x1c,0xe5,0x74,0x60,0x18,0x90, ++0x01,0x57,0xe4,0xf0,0x90,0x01,0x3c,0x74,0x02,0xf0,0x90,0x9e,0x89,0xe4,0x12,0x44, ++0x52,0x90,0x01,0x57,0x74,0x05,0xf0,0xe5,0x2e,0x30,0xe4,0x2f,0x90,0x01,0x36,0x74, ++0x10,0xf0,0xe5,0x73,0x64,0x01,0x70,0x23,0xe5,0x74,0x60,0x1f,0x90,0x01,0x57,0xe4, ++0xf0,0x90,0x01,0x3c,0x74,0x02,0xf0,0x90,0x9e,0x62,0xe4,0xf0,0x90,0x9e,0x63,0xe0, ++0x54,0xfd,0xf0,0xe0,0x54,0x07,0x70,0x03,0x12,0x44,0xd3,0xe5,0x2e,0x30,0xe5,0x1f, ++0x90,0x01,0x36,0x74,0x20,0xf0,0xe5,0x73,0xb4,0x01,0x14,0xe5,0x74,0x60,0x10,0x90, ++0x9e,0x61,0xe0,0x64,0x02,0x60,0x05,0x12,0x44,0xdc,0x80,0x03,0x12,0x44,0x80,0xe5, ++0x2e,0x30,0xe6,0x1e,0x90,0x01,0x36,0x74,0x40,0xf0,0xe5,0x73,0xb4,0x01,0x13,0xe5, ++0x74,0x60,0x0f,0x90,0x9e,0x63,0xe0,0x54,0xfe,0xf0,0xe0,0x54,0x07,0x70,0x03,0x12, ++0x44,0xd3,0xe5,0x2f,0x30,0xe1,0x08,0x90,0x01,0x37,0x74,0x02,0xf0,0xd1,0xbd,0x74, ++0x45,0x04,0x90,0x01,0xc4,0xf0,0x74,0x5a,0xa3,0xf0,0xd0,0x07,0xd0,0x06,0xd0,0x05, ++0xd0,0x04,0xd0,0x03,0xd0,0x02,0xd0,0x01,0xd0,0x00,0xd0,0xd0,0xd0,0x82,0xd0,0x83, ++0xd0,0xf0,0xd0,0xe0,0x32,0x90,0x04,0x1b,0xe0,0x54,0x7f,0x64,0x7f,0x7f,0x01,0x60, ++0x02,0x7f,0x00,0x22,0xd3,0x10,0xaf,0x01,0xc3,0xc0,0xd0,0x90,0x9e,0x91,0x12,0x43, ++0x8b,0x90,0x9e,0x75,0xe0,0x64,0x02,0x60,0x6e,0x90,0x9e,0x75,0xe0,0x64,0x01,0x70, ++0x66,0x90,0x9e,0xb0,0xe0,0xff,0x04,0xf0,0x90,0x9e,0x91,0x12,0x43,0x6b,0x90,0x00, ++0x01,0xef,0x12,0x42,0x5f,0x7f,0xaf,0x7e,0x01,0xf1,0x3b,0xef,0x60,0x49,0x90,0x9e, ++0x91,0x12,0x43,0x6b,0x8b,0x1e,0x8a,0x1f,0x89,0x20,0x75,0x21,0x02,0x7b,0x01,0x7a, ++0x01,0x79,0xa0,0x12,0x45,0x09,0x90,0x9e,0x94,0x12,0x43,0x6b,0x8b,0x1e,0x8a,0x1f, ++0x89,0x20,0x90,0x9e,0x91,0x12,0x43,0x6b,0x12,0x24,0x62,0xff,0xc4,0x54,0x0f,0xf5, ++0x21,0x7b,0x01,0x7a,0x01,0x79,0xa2,0x12,0x45,0x09,0x90,0x01,0xaf,0x74,0xff,0xf0, ++0x90,0x01,0xcb,0xe0,0x64,0x80,0xf0,0xd0,0xd0,0x92,0xaf,0x22,0x90,0x9e,0x2f,0xe0, ++0x54,0xf0,0x44,0x03,0xf0,0x54,0x0f,0x44,0x80,0xf0,0x7b,0x00,0x7a,0x00,0x79,0x13, ++0x90,0x9e,0x94,0x12,0x43,0x8b,0x0b,0x7a,0x9e,0x79,0x2f,0xc1,0x14,0x7d,0x02,0x7f, ++0x03,0x12,0x31,0x2c,0xe5,0x74,0x14,0x24,0xfd,0x50,0x02,0x80,0x23,0x90,0x9e,0x61, ++0xe0,0x60,0x06,0x7d,0x01,0x7f,0x0c,0x80,0x0f,0x90,0x9e,0x5e,0xe0,0x54,0x0f,0xc3, ++0x94,0x04,0x50,0x07,0x7d,0x01,0x7f,0x04,0x12,0x47,0x1a,0xe4,0xff,0x12,0x48,0x8f, ++0x22,0xd1,0x05,0xef,0x64,0x01,0x60,0x08,0x90,0x01,0xb9,0x74,0x01,0xf0,0x80,0x32, ++0x90,0x9e,0x5d,0xe0,0x60,0x08,0x90,0x01,0xb9,0x74,0x02,0xf0,0x80,0x24,0x90,0x9e, ++0x5c,0xe0,0x60,0x08,0x90,0x01,0xb9,0x74,0x04,0xf0,0x80,0x16,0x90,0x9e,0x60,0xe0, ++0x54,0x0f,0xd3,0x94,0x04,0x40,0x08,0x90,0x01,0xb9,0x74,0x08,0xf0,0x80,0x03,0x7f, ++0x01,0x22,0x90,0x01,0xb8,0x74,0x08,0xf0,0x7f,0x00,0x22,0xd3,0x10,0xaf,0x01,0xc3, ++0xc0,0xd0,0x90,0x9e,0xa0,0xee,0xf0,0xa3,0xef,0xf0,0xe4,0xa3,0xf0,0xa3,0xf0,0x90, ++0x9e,0xa0,0xe0,0xfe,0xa3,0xe0,0xf5,0x82,0x8e,0x83,0xe0,0x60,0x2d,0xc3,0x90,0x9e, ++0xa3,0xe0,0x94,0xe8,0x90,0x9e,0xa2,0xe0,0x94,0x03,0x40,0x0b,0x90,0x01,0xc6,0xe0, ++0x44,0x10,0xf0,0x7f,0x00,0x80,0x15,0x90,0x9e,0xa2,0xe4,0x75,0xf0,0x01,0x12,0x42, ++0x81,0x7f,0x0a,0x7e,0x00,0x12,0x32,0x15,0x80,0xc5,0x7f,0x01,0xd0,0xd0,0x92,0xaf, ++0x22,0x75,0x30,0x1f,0x75,0x31,0x01,0xe4,0xf5,0x32,0x90,0x01,0x38,0xe5,0x30,0xf0, ++0xa3,0xe5,0x31,0xf0,0xa3,0xe5,0x32,0xf0,0x22,0x90,0x00,0x02,0xe0,0x54,0xe0,0x90, ++0x9e,0x75,0x60,0x04,0x74,0x01,0xf0,0x22,0x74,0x02,0xf0,0x22,0x90,0x00,0xf3,0xe0, ++0x30,0xe3,0x08,0x90,0x9e,0x77,0x74,0x01,0xf0,0x80,0x05,0xe4,0x90,0x9e,0x77,0xf0, ++0x90,0x9e,0x77,0xe0,0xb4,0x01,0x12,0x90,0x00,0xf2,0xe0,0x30,0xe7,0x0b,0x90,0x9e, ++0x64,0x74,0xfd,0xf0,0xa3,0x74,0x33,0xf0,0x22,0x90,0x9e,0x64,0x74,0xfd,0xf0,0xa3, ++0x74,0x2f,0xf0,0x22,0x90,0x01,0x64,0x74,0xa0,0xf0,0x22,0xc0,0xe0,0xc0,0xf0,0xc0, ++0x83,0xc0,0x82,0xc0,0xd0,0x75,0xd0,0x00,0xc0,0x00,0xc0,0x01,0xc0,0x02,0xc0,0x03, ++0xc0,0x04,0xc0,0x05,0xc0,0x06,0xc0,0x07,0x90,0x01,0xc4,0x74,0xfb,0xf0,0x74,0x5f, ++0xa3,0xf0,0x53,0x91,0xef,0x90,0x00,0x51,0xe0,0xff,0x90,0x00,0x55,0xe0,0x5f,0xf5, ++0x3d,0xe5,0x3d,0x30,0xe6,0x18,0x74,0x40,0xf0,0x90,0x9e,0x1d,0xe0,0x54,0x03,0xff, ++0xbf,0x03,0x0b,0x90,0x9e,0x1a,0xe0,0x60,0x05,0x7f,0x01,0x12,0x4a,0xd6,0xe5,0x3d, ++0x30,0xe7,0x15,0x90,0x00,0x55,0x74,0x80,0xf0,0x90,0x9e,0x1d,0xe0,0x54,0x03,0xff, ++0xbf,0x03,0x05,0x7f,0x02,0x12,0x4a,0xd6,0x90,0x01,0xc4,0x74,0xfb,0xf0,0x74,0x5f, ++0xa3,0xf0,0xd0,0x07,0xd0,0x06,0xd0,0x05,0xd0,0x04,0xd0,0x03,0xd0,0x02,0xd0,0x01, ++0xd0,0x00,0xd0,0xd0,0xd0,0x82,0xd0,0x83,0xd0,0xf0,0xd0,0xe0,0x32,0x8f,0x6b,0x8c, ++0x6c,0x8d,0x6d,0x22,0x8f,0x6e,0x8c,0x6f,0x8d,0x70,0x22,0xe4,0xf5,0x73,0x90,0x9e, ++0x63,0xf0,0xf5,0x74,0x90,0x9e,0x60,0x74,0x0c,0xf0,0x90,0x9e,0x5e,0xf0,0xe4,0x90, ++0x9e,0x61,0xf0,0x90,0x9e,0x5d,0xf0,0x90,0x9e,0x5c,0xf0,0x90,0x9e,0x5f,0x04,0xf0, ++0x90,0x9e,0x50,0xf0,0xe4,0x90,0x9e,0x62,0xf0,0x90,0x9e,0x52,0xf0,0x90,0x9e,0x5a, ++0x74,0x07,0xf0,0xe4,0x90,0x9e,0x51,0xf0,0x90,0x9e,0x58,0xf0,0xa3,0x74,0x02,0xf0, ++0x90,0x9e,0x56,0x14,0xf0,0xa3,0x74,0x03,0xf0,0x90,0x9e,0x55,0x74,0x14,0xf0,0x90, ++0x9e,0x5b,0x74,0x05,0xf0,0xe4,0x90,0x9e,0x54,0xf0,0x90,0x9e,0x4f,0xf0,0x90,0x9e, ++0x76,0xf0,0x22,0xe4,0x90,0x9e,0x62,0xf0,0x90,0x9e,0x51,0xf0,0x90,0x9e,0x63,0xf0, ++0x22,0x8b,0x59,0x8a,0x5a,0x89,0x5b,0x31,0x03,0xab,0x59,0xaa,0x5a,0xa9,0x5b,0x12, ++0x24,0x62,0xf5,0x74,0x14,0x60,0x0e,0x14,0x60,0x1e,0x14,0x60,0x2f,0x24,0x03,0x70, ++0x40,0x7f,0x01,0x80,0x3a,0xab,0x59,0xaa,0x5a,0xa9,0x5b,0x90,0x00,0x02,0x12,0x42, ++0x20,0xfd,0xe4,0xff,0x31,0x72,0x80,0x27,0xab,0x59,0xaa,0x5a,0xa9,0x5b,0x90,0x00, ++0x02,0x12,0x42,0x20,0xfd,0x7f,0x01,0x31,0x72,0x1f,0x80,0x13,0xab,0x59,0xaa,0x5a, ++0xa9,0x5b,0x90,0x00,0x02,0x12,0x42,0x20,0xfd,0x7f,0x02,0x31,0x72,0xe4,0xff,0x31, ++0xc6,0x22,0xef,0x24,0xfe,0x60,0x0b,0x04,0x70,0x22,0x90,0x9e,0x5f,0x74,0x01,0xf0, ++0x80,0x16,0xed,0x70,0x0a,0x90,0x9e,0x5b,0xe0,0x90,0x9e,0x5f,0xf0,0x80,0x05,0x90, ++0x9e,0x5f,0xed,0xf0,0x90,0x9e,0x5f,0xe0,0x90,0x9e,0x50,0xf0,0x22,0xd3,0x10,0xaf, ++0x01,0xc3,0xc0,0xd0,0x90,0x00,0x01,0x12,0x42,0x20,0x90,0x9e,0x61,0xf0,0x90,0x00, ++0x03,0x12,0x42,0x20,0x90,0x9e,0x4f,0xf0,0x12,0x24,0x62,0x65,0x74,0x60,0x02,0x31, ++0x11,0xd0,0xd0,0x92,0xaf,0x22,0xef,0x64,0x01,0x70,0x30,0x7d,0x7c,0x7f,0x02,0x12, ++0x31,0x2c,0x7d,0x02,0x7f,0x03,0x12,0x31,0x2c,0x90,0x01,0x57,0xe4,0xf0,0x90,0x01, ++0x3c,0x74,0x02,0xf0,0x12,0x47,0x16,0xe4,0xff,0x12,0x48,0x8f,0x90,0x06,0x04,0xe0, ++0x54,0x7f,0xf0,0x90,0x06,0x0a,0xe0,0x54,0xf8,0xf0,0x22,0x90,0x01,0x36,0x74,0x7c, ++0xf0,0xa3,0x74,0x02,0xf0,0x7d,0x7c,0xff,0x12,0x31,0x9d,0x7d,0x02,0x7f,0x03,0x12, ++0x31,0x9d,0x90,0x06,0x04,0xe0,0x44,0x80,0xf0,0x90,0x06,0x0a,0xe0,0x44,0x07,0xf0, ++0x90,0x9e,0x58,0xe0,0xa3,0xe0,0x90,0x05,0x58,0xf0,0xe5,0x73,0x30,0xe0,0x1b,0x90, ++0x9e,0x52,0xe0,0x70,0x1a,0xe0,0x04,0xf0,0x90,0x9e,0x5e,0xe0,0x54,0x0f,0xc3,0x94, ++0x04,0x50,0x0c,0x7d,0x01,0x7f,0x04,0x02,0x47,0x1a,0xe4,0x90,0x9e,0x52,0xf0,0x22, ++0x12,0x5e,0x05,0xef,0x64,0x01,0x60,0x08,0x90,0x01,0xb9,0x74,0x01,0xf0,0x80,0x52, ++0x90,0x9e,0x63,0xe0,0x54,0x03,0x60,0x08,0x90,0x01,0xb9,0x74,0x02,0xf0,0x80,0x42, ++0x90,0x9e,0x60,0xe0,0x54,0x0f,0xd3,0x94,0x02,0x40,0x08,0x90,0x01,0xb9,0x74,0x04, ++0xf0,0x80,0x2f,0x90,0x9e,0x63,0xe0,0x30,0xe2,0x08,0x90,0x01,0xb9,0x74,0x08,0xf0, ++0x80,0x20,0x90,0x9e,0x63,0xe0,0x30,0xe4,0x08,0x90,0x01,0xb9,0x74,0x10,0xf0,0x80, ++0x11,0x90,0x9e,0x52,0xe0,0x60,0x08,0x90,0x01,0xb9,0x74,0x20,0xf0,0x80,0x03,0x7f, ++0x01,0x22,0x90,0x01,0xb8,0x74,0x04,0xf0,0x7f,0x00,0x22,0xe5,0x12,0x60,0x08,0x90, ++0x01,0xb9,0x74,0x01,0xf0,0x80,0x5e,0x90,0x9e,0x60,0xe0,0x54,0x0f,0xd3,0x94,0x01, ++0x40,0x08,0x90,0x01,0xb9,0x74,0x02,0xf0,0x80,0x4b,0x90,0x02,0x87,0xe0,0x60,0x08, ++0x90,0x01,0xb9,0x74,0x04,0xf0,0x80,0x3d,0x90,0x9e,0x75,0xe0,0xb4,0x02,0x10,0x90, ++0x9e,0x64,0xe0,0xfe,0xa3,0xe0,0xf5,0x82,0x8e,0x83,0xe0,0x60,0x17,0x80,0x26,0x90, ++0x9e,0x75,0xe0,0xb4,0x01,0x0e,0x90,0x01,0xaf,0xe0,0x60,0x08,0x90,0x01,0xb9,0x74, ++0x08,0xf0,0x80,0x11,0x90,0x9e,0x54,0xe0,0x70,0x08,0x90,0x01,0xb9,0x74,0x10,0xf0, ++0x80,0x03,0x7f,0x01,0x22,0x90,0x01,0xb8,0x74,0x02,0xf0,0x7f,0x00,0x22,0x90,0x06, ++0x04,0xe0,0x54,0xbf,0xf0,0xef,0x60,0x09,0xe5,0x73,0xb4,0x01,0x04,0xe4,0xff,0x71, ++0x4d,0x90,0x9e,0x5e,0xe0,0x54,0xf0,0xf0,0xe0,0x44,0x0c,0xf0,0x22,0x8f,0x76,0x90, ++0x9e,0x5e,0xe0,0x90,0x01,0xc1,0xf0,0xa3,0xe5,0x12,0xf0,0x12,0x45,0xb1,0xef,0x64, ++0x01,0x70,0x2e,0x90,0x9e,0x69,0x12,0x47,0xfa,0xe5,0x76,0x60,0x10,0x74,0x21,0x2f, ++0xf5,0x82,0xe4,0x34,0xfc,0xf5,0x83,0xe0,0x44,0x10,0xf0,0x80,0x0e,0x74,0x21,0x2f, ++0xf5,0x82,0xe4,0x34,0xfc,0xf5,0x83,0xe0,0x54,0xef,0xf0,0x90,0x04,0x1f,0x74,0x20, ++0xf0,0x22,0x90,0x9e,0xaf,0xef,0xf0,0x71,0xb0,0x90,0x9e,0xaf,0xe0,0x60,0x05,0x90, ++0x05,0x22,0xe4,0xf0,0x90,0x9e,0x5e,0xe0,0x54,0xf0,0xf0,0xe0,0x44,0x04,0xf0,0x22, ++0x90,0x00,0x11,0xe0,0x44,0x09,0xf0,0x12,0x49,0xb9,0x90,0x9d,0xff,0x12,0x43,0x53, ++0x90,0x80,0x96,0x12,0x25,0x08,0x7f,0x78,0x7e,0x08,0x12,0x2b,0x08,0x90,0x9e,0x03, ++0x12,0x43,0x53,0x90,0x80,0x96,0x12,0x25,0x08,0x7f,0x04,0x7e,0x0c,0x12,0x2b,0x08, ++0x90,0x9e,0x07,0x12,0x43,0x53,0x90,0x80,0x96,0x12,0x25,0x08,0x7f,0x00,0x7e,0x08, ++0x12,0x2b,0x08,0x90,0x9e,0x0b,0x12,0x43,0x53,0x90,0x80,0x96,0x12,0x25,0x08,0x7f, ++0x70,0x7e,0x0e,0x12,0x2b,0x08,0x90,0x80,0x68,0x12,0x25,0x14,0x00,0x03,0x2d,0x95, ++0xe4,0xfd,0xff,0x12,0x30,0x2c,0x90,0x9e,0x77,0xe0,0xb4,0x01,0x11,0x90,0x80,0x68, ++0x12,0x25,0x14,0x00,0x03,0x2d,0x95,0xe4,0xfd,0x7f,0x01,0x12,0x30,0x2c,0x22,0x8f, ++0x27,0xe4,0x90,0x9e,0xa8,0xf0,0xa3,0xf0,0x90,0x01,0x09,0xe0,0x7f,0x00,0x30,0xe7, ++0x02,0x7f,0x01,0xef,0x65,0x27,0x60,0x3e,0xc3,0x90,0x9e,0xa9,0xe0,0x94,0x88,0x90, ++0x9e,0xa8,0xe0,0x94,0x13,0x40,0x08,0x90,0x01,0xc6,0xe0,0x44,0x80,0xf0,0x22,0x90, ++0x9e,0xa8,0xe4,0x75,0xf0,0x01,0x12,0x42,0x81,0x7f,0x14,0x7e,0x00,0x12,0x32,0x15, ++0xd3,0x90,0x9e,0xa9,0xe0,0x94,0x32,0x90,0x9e,0xa8,0xe0,0x94,0x00,0x40,0xb9,0x90, ++0x01,0xc7,0xe0,0x30,0xe0,0xb2,0x22,0x90,0x9e,0x5e,0xe0,0x54,0xf0,0xf0,0xe0,0x44, ++0x01,0xf0,0x12,0x44,0xff,0x12,0x45,0x00,0xe0,0x54,0xf0,0xf0,0xe0,0x44,0x02,0xf0, ++0x22,0x90,0x9e,0x60,0xe0,0x30,0xe6,0x1c,0xe0,0x54,0x0f,0xff,0x90,0x9e,0x4e,0xe0, ++0xfe,0x4f,0x90,0x01,0x2f,0xf0,0xee,0x64,0x80,0x90,0x9e,0x4e,0xf0,0x90,0x9e,0x60, ++0xe0,0x54,0xbf,0xf0,0x22,0x8f,0x75,0x12,0x45,0xb1,0xef,0x64,0x01,0x70,0x2e,0x90, ++0x9e,0x6a,0x12,0x47,0xfa,0xe5,0x75,0x60,0x10,0x74,0x21,0x2f,0xf5,0x82,0xe4,0x34, ++0xfc,0xf5,0x83,0xe0,0x44,0x10,0xf0,0x80,0x0e,0x74,0x21,0x2f,0xf5,0x82,0xe4,0x34, ++0xfc,0xf5,0x83,0xe0,0x54,0xef,0xf0,0x90,0x04,0x1f,0x74,0x20,0xf0,0x22,0xe4,0x90, ++0x9e,0x2f,0xf0,0xe5,0x74,0x60,0x6a,0xe5,0x73,0x64,0x01,0x70,0x64,0xe5,0x74,0x14, ++0x60,0x29,0x24,0xfd,0x60,0x25,0x24,0x02,0x24,0xfb,0x50,0x02,0x80,0x23,0x90,0x9e, ++0x50,0xe0,0x14,0xf0,0xe0,0x60,0x04,0xa3,0xe0,0x60,0x16,0x90,0x9e,0x50,0xe0,0x70, ++0x0a,0x90,0x9e,0x5f,0xe0,0x90,0x9e,0x50,0xf0,0x80,0x00,0x90,0x9e,0x2f,0x74,0x01, ++0xf0,0x90,0x9e,0x2f,0xe0,0x60,0x2a,0x90,0x9e,0x63,0xe0,0x44,0x10,0xf0,0xe4,0x90, ++0x9e,0x89,0xf0,0x90,0x9e,0x5a,0x12,0x44,0x56,0x90,0x01,0x57,0x74,0x05,0xf0,0x90, ++0x9e,0x5e,0xe0,0x54,0x0f,0xc3,0x94,0x04,0x50,0x07,0x7d,0x01,0x7f,0x04,0x12,0x47, ++0x1a,0x22,0xef,0xc3,0x94,0x20,0x50,0x39,0xef,0x30,0xe0,0x17,0xed,0xc4,0x54,0xf0, ++0xfd,0xef,0xc3,0x13,0xfe,0x24,0xa4,0xf5,0x82,0xe4,0x34,0x04,0xf5,0x83,0xe0,0x54, ++0x0f,0x80,0x10,0xef,0xc3,0x13,0xfe,0x24,0xa4,0xf5,0x82,0xe4,0x34,0x04,0xf5,0x83, ++0xe0,0x54,0xf0,0xf0,0x74,0xa4,0x2e,0xf5,0x82,0xe4,0x34,0x04,0xf5,0x83,0xe0,0x4d, ++0xf0,0x22,0xad,0x07,0xed,0xc3,0x94,0x20,0x50,0x0d,0x74,0x84,0x2d,0xf5,0x82,0xe4, ++0x34,0x04,0xf5,0x83,0xe0,0x80,0x0b,0x74,0xa6,0x2d,0xf5,0x82,0xe4,0x34,0x9c,0xf5, ++0x83,0xe0,0x54,0x7f,0xf5,0x64,0xe5,0x64,0x54,0x1f,0xfc,0x75,0xf0,0x09,0xed,0x90, ++0x96,0x48,0x12,0x43,0x5f,0xe0,0xff,0x90,0x9e,0x3e,0xf0,0xed,0x25,0xe0,0x24,0x02, ++0xf5,0x82,0xe4,0x34,0x95,0xf5,0x83,0xe0,0xfb,0xa3,0xe0,0x90,0x9e,0x3f,0xcb,0xf0, ++0xa3,0xeb,0xf0,0xed,0x25,0xe0,0x24,0xc6,0xf5,0x82,0xe4,0x34,0x9b,0xf5,0x83,0xe0, ++0xfb,0xa3,0xe0,0x90,0x9e,0x41,0xcb,0xf0,0xa3,0xeb,0xf0,0xec,0x25,0xe0,0x24,0x66, ++0xf5,0x82,0xe4,0x34,0x41,0xf5,0x83,0xe4,0x93,0xfa,0x74,0x01,0x93,0xfb,0xed,0x25, ++0xe0,0x24,0xc2,0xf5,0x82,0xe4,0x34,0x95,0xf5,0x83,0xea,0xf0,0xa3,0xeb,0xf0,0xec, ++0xc3,0x9f,0x40,0x02,0xc1,0xc9,0x74,0x67,0x2d,0xf5,0x82,0xe4,0x34,0x9d,0xf5,0x83, ++0xec,0xf0,0x04,0xfb,0x90,0x9e,0x3e,0xe0,0xff,0xeb,0xd3,0x9f,0x40,0x02,0xc1,0xfa, ++0xeb,0xc3,0x94,0x10,0x40,0x21,0xeb,0x24,0xf0,0xff,0x74,0x01,0x7e,0x00,0xa8,0x07, ++0x08,0x80,0x05,0xc3,0x33,0xce,0x33,0xce,0xd8,0xf9,0xff,0x90,0x9e,0x3f,0xe0,0x5e, ++0xfe,0xa3,0xe0,0x5f,0x4e,0x70,0x23,0xeb,0xc3,0x94,0x10,0x50,0x39,0x74,0x01,0x7e, ++0x00,0xa8,0x03,0x08,0x80,0x05,0xc3,0x33,0xce,0x33,0xce,0xd8,0xf9,0xff,0x90,0x9e, ++0x41,0xe0,0x5e,0xfe,0xa3,0xe0,0x5f,0x4e,0x60,0x1c,0xeb,0x64,0x13,0x60,0x08,0xeb, ++0x64,0x12,0x60,0x03,0xbb,0x11,0x09,0x90,0x9e,0x3f,0xe0,0x30,0xe0,0x02,0x7b,0x18, ++0xac,0x03,0x8c,0x64,0x80,0x34,0x0b,0x80,0x8b,0x90,0x9e,0x3e,0xe0,0xfb,0x6c,0x70, ++0x69,0x74,0x67,0x2d,0xf5,0x82,0xe4,0x34,0x9d,0xf5,0x83,0xec,0xf0,0x75,0xf0,0x09, ++0xed,0x90,0x96,0x4a,0x12,0x43,0x5f,0xe0,0xb4,0x01,0x0c,0xe5,0x64,0x20,0xe6,0x07, ++0xec,0x44,0x40,0xf5,0x64,0x80,0x03,0xaf,0x64,0x22,0xec,0x25,0xe0,0x24,0x9e,0xf5, ++0x82,0xe4,0x34,0x41,0xf5,0x83,0xe4,0x93,0xfe,0x74,0x01,0x93,0xff,0xec,0x25,0xe0, ++0x24,0x66,0xf5,0x82,0xe4,0x34,0x41,0xf5,0x83,0x74,0x01,0x93,0x2f,0xff,0xe4,0x93, ++0x3e,0xc3,0x13,0xfe,0xef,0x13,0xff,0xed,0x25,0xe0,0x24,0xc2,0xf5,0x82,0xe4,0x34, ++0x95,0xf5,0x83,0xee,0xf0,0xa3,0xef,0xf0,0x80,0x5b,0xec,0xd3,0x9b,0x40,0x56,0x90, ++0x9e,0x3e,0xe0,0xff,0x74,0x67,0x2d,0xf5,0x82,0xe4,0x34,0x9d,0xf5,0x83,0xef,0xf0, ++0xac,0x07,0x8f,0x64,0xec,0x25,0xe0,0x24,0x9e,0xf5,0x82,0xe4,0x34,0x41,0xf5,0x83, ++0xe4,0x93,0xfe,0x74,0x01,0x93,0xff,0xec,0x25,0xe0,0x24,0x66,0xf5,0x82,0xe4,0x34, ++0x41,0xf5,0x83,0x74,0x01,0x93,0x2f,0xff,0xe4,0x93,0x3e,0xc3,0x13,0xfe,0xef,0x13, ++0xff,0xed,0x25,0xe0,0x24,0xc2,0xf5,0x82,0xe4,0x34,0x95,0xf5,0x83,0xee,0xf0,0xa3, ++0xef,0xf0,0xaf,0x64,0x22,0x74,0x01,0x2d,0xf5,0x82,0xe4,0x34,0x94,0xf5,0x83,0xe4, ++0xf0,0xaf,0x05,0xe5,0x64,0x44,0x80,0xfd,0x12,0x58,0xf1,0xe5,0x64,0x44,0x80,0xff, ++0x22,0xac,0x07,0xec,0xc3,0x94,0x20,0x50,0x0d,0x74,0x84,0x2c,0xf5,0x82,0xe4,0x34, ++0x04,0xf5,0x83,0xe0,0x80,0x0b,0x74,0xa6,0x2c,0xf5,0x82,0xe4,0x34,0x9c,0xf5,0x83, ++0xe0,0x54,0x7f,0xf5,0x64,0xe5,0x64,0x54,0x1f,0xff,0x90,0x9e,0x40,0xf0,0x75,0xf0, ++0x09,0xec,0x90,0x96,0x49,0x12,0x43,0x5f,0xe0,0x90,0x9e,0x42,0xf0,0x75,0xf0,0x09, ++0xec,0x90,0x96,0x48,0x12,0x43,0x5f,0xe0,0xfe,0x90,0x9e,0x43,0xf0,0xec,0x25,0xe0, ++0x24,0xc6,0xf5,0x82,0xe4,0x34,0x9b,0xf5,0x83,0xe0,0xfb,0xa3,0xe0,0x90,0x9e,0x44, ++0xcb,0xf0,0xa3,0xeb,0xf0,0xec,0x25,0xe0,0x24,0x02,0xf5,0x82,0xe4,0x34,0x95,0xf5, ++0x83,0xe0,0xfb,0xa3,0xe0,0x90,0x9e,0x46,0xcb,0xf0,0xa3,0xeb,0xf0,0xef,0xd3,0x9e, ++0x40,0x0a,0x90,0x9e,0x43,0xe0,0x90,0x9e,0x40,0xf0,0xf5,0x64,0xed,0x70,0x02,0x21, ++0x07,0x90,0x9e,0x41,0xed,0xf0,0xe5,0x64,0x30,0xe6,0x0a,0x90,0x9e,0x40,0xe0,0xf5, ++0x64,0xa3,0xe0,0x14,0xf0,0x90,0x9e,0x41,0xe0,0x70,0x02,0x21,0x07,0x90,0x9e,0x40, ++0xe0,0xff,0xd3,0x94,0x00,0x50,0x02,0x21,0x07,0xe4,0x90,0x9e,0x3f,0xf0,0xef,0x14, ++0x90,0x9e,0x3e,0xf0,0x90,0x9e,0x42,0xe0,0xfd,0x90,0x9e,0x3e,0xe0,0xff,0xd3,0x9d, ++0x40,0x6b,0xef,0x94,0x10,0x40,0x21,0xef,0x24,0xf0,0xff,0x74,0x01,0x7e,0x00,0xa8, ++0x07,0x08,0x80,0x05,0xc3,0x33,0xce,0x33,0xce,0xd8,0xf9,0xff,0x90,0x9e,0x46,0xe0, ++0x5e,0xfe,0xa3,0xe0,0x5f,0x4e,0x70,0x27,0x90,0x9e,0x3e,0xe0,0xff,0xc3,0x94,0x10, ++0x50,0x33,0x74,0x01,0x7e,0x00,0xa8,0x07,0x08,0x80,0x05,0xc3,0x33,0xce,0x33,0xce, ++0xd8,0xf9,0xff,0x90,0x9e,0x44,0xe0,0x5e,0xfe,0xa3,0xe0,0x5f,0x4e,0x60,0x16,0x90, ++0x9e,0x3e,0xe0,0xf5,0x64,0xa3,0xe0,0x04,0xf0,0x90,0x9e,0x41,0xe0,0xff,0x90,0x9e, ++0x3f,0xe0,0x6f,0x60,0x08,0x90,0x9e,0x3e,0xe0,0x14,0xf0,0x80,0x87,0x90,0x9e,0x41, ++0xe0,0xff,0x90,0x9e,0x3f,0xe0,0xc3,0x9f,0x50,0x0d,0x90,0x9e,0x3e,0xe0,0xb5,0x05, ++0x06,0x90,0x9e,0x42,0xe0,0xf5,0x64,0xe5,0x64,0x25,0xe0,0x24,0x9e,0xf5,0x82,0xe4, ++0x34,0x41,0xf5,0x83,0xe4,0x93,0xfe,0x74,0x01,0x93,0xff,0xe5,0x64,0x25,0xe0,0x24, ++0x66,0xf5,0x82,0xe4,0x34,0x41,0xf5,0x83,0x74,0x01,0x93,0x2f,0xff,0xe4,0x93,0x3e, ++0xc3,0x13,0xfe,0xef,0x13,0xff,0xec,0x25,0xe0,0x24,0xc2,0xf5,0x82,0xe4,0x34,0x95, ++0xf5,0x83,0xee,0xf0,0xa3,0xef,0xf0,0xaf,0x04,0xad,0x64,0x12,0x58,0xf1,0xaf,0x64, ++0x22,0xe4,0xf5,0x59,0xe5,0x59,0xb4,0x20,0x14,0x90,0x9a,0xc5,0xe0,0x04,0xf0,0x90, ++0x95,0x01,0xe0,0xff,0x90,0x9a,0xc5,0xe0,0xb5,0x07,0x02,0xe4,0xf0,0x75,0xf0,0x09, ++0xe5,0x59,0x90,0x96,0x4b,0x12,0x43,0x5f,0xe0,0x64,0x01,0x60,0x02,0xe1,0x95,0xe5, ++0x59,0x25,0xe0,0x24,0x80,0xf5,0x82,0xe4,0x34,0x93,0xf5,0x83,0xe0,0xfe,0xa3,0xe0, ++0xd3,0x94,0x00,0xee,0x94,0x00,0x50,0x02,0xe1,0x95,0xe5,0x59,0x94,0x20,0x40,0x08, ++0x90,0x9a,0xc5,0xe0,0x60,0x02,0xe1,0xa0,0xe5,0x59,0x75,0xf0,0x0a,0xa4,0x24,0x00, ++0xf9,0x74,0x90,0x35,0xf0,0x75,0x5e,0x01,0xf5,0x5f,0x89,0x60,0xe5,0x59,0x25,0xe0, ++0x24,0x80,0xf5,0x82,0xe4,0x34,0x93,0xf5,0x83,0xe0,0xff,0xa3,0xe0,0x90,0x9e,0x38, ++0xcf,0xf0,0xa3,0xef,0xf0,0xe5,0x59,0x25,0xe0,0x24,0xc4,0xf5,0x82,0xe4,0x34,0x98, ++0xf5,0x83,0xe0,0xff,0xa3,0xe0,0x90,0x9e,0x3a,0xcf,0xf0,0xa3,0xef,0xf0,0xe5,0x59, ++0xc3,0x94,0x20,0x50,0x14,0x74,0x84,0x25,0x59,0xf5,0x82,0xe4,0x34,0x04,0xf5,0x83, ++0xe0,0x54,0x3f,0x90,0x9e,0x34,0xf0,0x80,0x12,0x74,0xa6,0x25,0x59,0xf5,0x82,0xe4, ++0x34,0x9c,0xf5,0x83,0xe0,0x54,0x3f,0x90,0x9e,0x34,0xf0,0x90,0x9e,0x34,0xe0,0xfe, ++0x54,0x1f,0xa3,0xf0,0x75,0xf0,0x09,0xe5,0x59,0x90,0x96,0x48,0x12,0x43,0x5f,0xe0, ++0x90,0x9e,0x3d,0xf0,0x74,0xe6,0x25,0x59,0xf5,0x82,0xe4,0x34,0x9c,0xf5,0x83,0xe0, ++0xc3,0x94,0x05,0x40,0x02,0x81,0x6e,0x90,0x9e,0x3d,0xe0,0xff,0x90,0x9e,0x35,0xe0, ++0x9f,0x40,0x13,0x90,0x9e,0x3d,0xe0,0x90,0x9e,0x35,0xf0,0xee,0x54,0x40,0xfe,0x90, ++0x9e,0x34,0xf0,0xef,0x4e,0xf0,0x90,0x04,0xfd,0xe0,0x64,0x01,0x70,0x29,0x90,0x9e, ++0x35,0xe0,0xff,0x90,0x41,0x4a,0x93,0xfe,0x74,0x44,0x25,0x59,0xf5,0x82,0xe4,0x34, ++0x9a,0xf5,0x83,0xe0,0xc3,0x9e,0x40,0x06,0xef,0x90,0x40,0xda,0x80,0x30,0x90,0x9e, ++0x35,0xe0,0x90,0x40,0xf6,0x80,0x27,0x90,0x9e,0x35,0xe0,0xff,0x90,0x41,0x4a,0x93, ++0xfe,0x74,0x44,0x25,0x59,0xf5,0x82,0xe4,0x34,0x9a,0xf5,0x83,0xe0,0xc3,0x9e,0x40, ++0x06,0xef,0x90,0x41,0x12,0x80,0x07,0x90,0x9e,0x35,0xe0,0x90,0x41,0x2e,0x93,0x90, ++0x9e,0x3c,0xf0,0x90,0x9e,0x3c,0xe0,0x75,0xf0,0x06,0xa4,0x24,0x50,0xf9,0x74,0x40, ++0x35,0xf0,0x75,0x5b,0xff,0xf5,0x5c,0x89,0x5d,0x90,0x9e,0x34,0xe0,0x90,0x41,0xf2, ++0x93,0xff,0xd3,0x90,0x9e,0x3b,0xe0,0x9f,0x90,0x9e,0x3a,0xe0,0x94,0x00,0x40,0x09, ++0xe4,0xfd,0xaf,0x59,0x12,0x67,0xb1,0xe1,0x2c,0xe5,0x59,0x25,0xe0,0x24,0xc2,0xf5, ++0x82,0xe4,0x34,0x95,0xf5,0x83,0xe0,0xf5,0x61,0xa3,0xe0,0xf5,0x62,0xab,0x5b,0xaa, ++0x5c,0xa9,0x5d,0x12,0x24,0x62,0xff,0x7e,0x00,0xab,0x5e,0xaa,0x5f,0xa9,0x60,0x12, ++0x42,0x97,0xfd,0xac,0xf0,0x12,0x24,0x7b,0xef,0x25,0x62,0xf5,0x62,0xee,0x35,0x61, ++0xf5,0x61,0xab,0x5b,0xaa,0x5c,0xa9,0x5d,0x90,0x00,0x01,0x12,0x42,0x20,0xff,0x7e, ++0x00,0xab,0x5e,0xaa,0x5f,0xa9,0x60,0x90,0x00,0x02,0x12,0x42,0xc2,0xfd,0xac,0xf0, ++0x12,0x24,0x7b,0xef,0x25,0x62,0xf5,0x62,0xee,0x35,0x61,0xf5,0x61,0xab,0x5b,0xaa, ++0x5c,0xa9,0x5d,0x90,0x00,0x02,0x12,0x42,0x20,0xff,0x7e,0x00,0xab,0x5e,0xaa,0x5f, ++0xa9,0x60,0x90,0x00,0x04,0x12,0x42,0xc2,0xfd,0xac,0xf0,0x12,0x24,0x7b,0xef,0x25, ++0x62,0xf5,0x62,0xee,0x35,0x61,0xf5,0x61,0xab,0x5b,0xaa,0x5c,0xa9,0x5d,0x90,0x00, ++0x03,0x12,0x42,0x20,0xff,0x7e,0x00,0xab,0x5e,0xaa,0x5f,0xa9,0x60,0x90,0x00,0x06, ++0x12,0x42,0xc2,0xfd,0xac,0xf0,0x12,0x24,0x7b,0xef,0x25,0x62,0xf5,0x62,0xee,0x35, ++0x61,0xf5,0x61,0xab,0x5b,0xaa,0x5c,0xa9,0x5d,0x90,0x00,0x04,0x12,0x42,0x20,0xff, ++0x7e,0x00,0xab,0x5e,0xaa,0x5f,0xa9,0x60,0x90,0x00,0x08,0x12,0x42,0xc2,0xfd,0xac, ++0xf0,0x12,0x24,0x7b,0xef,0x25,0x62,0xf5,0x62,0xee,0x35,0x61,0xf5,0x61,0xab,0x5b, ++0xaa,0x5c,0xa9,0x5d,0x90,0x00,0x05,0x12,0x42,0x20,0xff,0x7e,0x00,0x90,0x9e,0x38, ++0xe0,0xfc,0xa3,0xe0,0xfd,0x12,0x24,0x7b,0xd3,0xe5,0x62,0x9f,0xe5,0x61,0x9e,0x40, ++0x0c,0xe5,0x62,0x9f,0xf5,0x62,0xe5,0x61,0x9e,0xf5,0x61,0x80,0x05,0xe4,0xf5,0x61, ++0xf5,0x62,0xe5,0x59,0x25,0xe0,0x24,0xc2,0xf5,0x82,0xe4,0x34,0x95,0xf5,0x83,0xe5, ++0x61,0xf0,0xa3,0xe5,0x62,0xf0,0x90,0x9e,0x34,0xe0,0x25,0xe0,0x24,0x66,0xf5,0x82, ++0xe4,0x34,0x41,0xf5,0x83,0xc3,0x74,0x01,0x93,0x95,0x62,0xe4,0x93,0x95,0x61,0x50, ++0x07,0xaf,0x59,0x12,0x65,0xb2,0xe1,0x00,0x90,0x9e,0x34,0xe0,0x25,0xe0,0x24,0x9e, ++0xf5,0x82,0xe4,0x34,0x41,0xf5,0x83,0xd3,0x74,0x01,0x93,0x95,0x62,0xe4,0x93,0x95, ++0x61,0x50,0x02,0xe1,0x00,0x7d,0x01,0xaf,0x59,0x12,0x67,0xb1,0xe1,0x00,0x74,0xe6, ++0x25,0x59,0xf5,0x82,0xe4,0x34,0x9c,0xf5,0x83,0xe0,0xfc,0x64,0x05,0x60,0x02,0xc1, ++0x09,0x90,0x96,0x43,0xe0,0xff,0xb4,0x03,0x0b,0x90,0x9e,0x35,0xe0,0xc3,0x94,0x19, ++0x40,0x3d,0x80,0x2e,0xef,0xb4,0x02,0x0b,0x90,0x9e,0x35,0xe0,0xc3,0x94,0x11,0x40, ++0x2e,0x80,0x1f,0x90,0x96,0x43,0xe0,0xff,0xb4,0x01,0x0b,0x90,0x9e,0x35,0xe0,0xc3, ++0x94,0x0a,0x40,0x1b,0x80,0x0c,0xef,0x70,0x11,0x90,0x9e,0x35,0xe0,0xc3,0x94,0x03, ++0x40,0x0d,0x90,0x9a,0x84,0x74,0x01,0xf0,0x80,0x05,0xe4,0x90,0x9a,0x84,0xf0,0x74, ++0x84,0x25,0x59,0xf5,0x82,0xe4,0x34,0x98,0xf5,0x83,0xe0,0xf5,0x63,0x74,0x44,0x25, ++0x59,0xf5,0x82,0xe4,0x34,0x9a,0xf5,0x83,0xe0,0xff,0xc3,0x94,0x30,0x50,0x02,0xa1, ++0xb6,0x90,0x9a,0x84,0xe0,0x64,0x01,0x60,0x02,0xa1,0xb6,0x74,0x85,0x25,0x59,0xf5, ++0x82,0xe4,0x34,0x9a,0xf5,0x83,0xe0,0x64,0x0a,0x60,0x51,0xef,0x24,0x05,0xff,0xe4, ++0x33,0xfe,0x74,0x41,0x25,0x59,0xf5,0x82,0xe4,0x34,0x94,0xf5,0x83,0xe0,0xfd,0xd3, ++0x9f,0xee,0x64,0x80,0xf8,0x74,0x80,0x98,0x50,0x32,0xed,0x24,0x05,0xff,0xe4,0x33, ++0xfe,0x74,0x44,0x25,0x59,0xf5,0x82,0xe4,0x34,0x9a,0xf5,0x83,0xe0,0xd3,0x9f,0xee, ++0x64,0x80,0xf8,0x74,0x80,0x98,0x50,0x14,0x74,0x26,0x25,0x59,0xf5,0x82,0xe4,0x34, ++0x9d,0xf5,0x83,0xe0,0xff,0x90,0x9e,0x35,0xe0,0x6f,0x60,0x3d,0x74,0x44,0x25,0x59, ++0xf5,0x82,0xe4,0x34,0x9a,0xf5,0x83,0xe0,0xff,0xd3,0x94,0x42,0x40,0x05,0x75,0x63, ++0x05,0x80,0x0e,0xef,0xd3,0x94,0x39,0x40,0x05,0x75,0x63,0x03,0x80,0x03,0x75,0x63, ++0x01,0x74,0x41,0x25,0x59,0xf5,0x82,0xe4,0x34,0x94,0xf5,0x83,0xef,0xf0,0x74,0x85, ++0x25,0x59,0xf5,0x82,0xe4,0x34,0x9a,0x80,0x29,0x74,0xe6,0x25,0x59,0xf5,0x82,0xe4, ++0x34,0x9c,0xf5,0x83,0xe4,0xf0,0x74,0x85,0x25,0x59,0xf5,0x82,0xe4,0x34,0x9a,0xf5, ++0x83,0xe0,0x04,0xf0,0x80,0x10,0xe4,0xf5,0x63,0x74,0xe6,0x25,0x59,0xf5,0x82,0xe4, ++0x34,0x9c,0xf5,0x83,0xe4,0xf0,0x90,0x9e,0x35,0xe0,0xff,0x74,0x26,0x25,0x59,0xf5, ++0x82,0xe4,0x34,0x9d,0xf5,0x83,0xef,0xf0,0x74,0x84,0x25,0x59,0xf5,0x82,0xe4,0x34, ++0x98,0xf5,0x83,0xe5,0x63,0xf0,0x75,0xf0,0x09,0xe5,0x59,0x90,0x96,0x4c,0x12,0x43, ++0x5f,0xe0,0xb4,0x01,0x10,0xe4,0xf5,0x63,0x74,0xe6,0x25,0x59,0xf5,0x82,0xe4,0x34, ++0x9c,0xf5,0x83,0xe4,0xf0,0xad,0x63,0xc1,0xfb,0xec,0x64,0x06,0x60,0x02,0xe1,0x00, ++0xf5,0x61,0xf5,0x62,0x90,0x42,0x13,0x93,0xff,0x7e,0x00,0x90,0x9e,0x38,0xe0,0xfc, ++0xa3,0xe0,0xfd,0x12,0x24,0x7b,0x90,0x9e,0x36,0xee,0xf0,0xa3,0xef,0xf0,0x74,0x84, ++0x25,0x59,0xf5,0x82,0xe4,0x34,0x98,0xf5,0x83,0xe0,0xf5,0x63,0xe4,0xf5,0x5a,0xab, ++0x5e,0xaa,0x5f,0xa9,0x60,0x75,0xf0,0x02,0xe5,0x5a,0xa4,0xf5,0x82,0x85,0xf0,0x83, ++0x12,0x42,0xc2,0xfd,0xac,0xf0,0xe5,0x5a,0x90,0x42,0x0e,0x93,0xff,0x7e,0x00,0x12, ++0x24,0x7b,0xef,0x25,0x62,0xf5,0x62,0xee,0x35,0x61,0xf5,0x61,0xc3,0x90,0x9e,0x37, ++0xe0,0x95,0x62,0x90,0x9e,0x36,0xe0,0x95,0x61,0x40,0x07,0x05,0x5a,0xe5,0x5a,0xb4, ++0x05,0xbd,0xe5,0x5a,0xc3,0x13,0xf5,0x5a,0xe5,0x63,0xb4,0x01,0x06,0xe5,0x5a,0x70, ++0x46,0x80,0x13,0xe5,0x63,0xb4,0x03,0x15,0xe5,0x5a,0x70,0x05,0x75,0x63,0x03,0x80, ++0x39,0xe5,0x5a,0xb4,0x01,0x05,0x75,0x63,0x01,0x80,0x2f,0x80,0x2a,0xe5,0x63,0xb4, ++0x05,0x28,0xe5,0x5a,0x70,0x05,0x75,0x63,0x05,0x80,0x0d,0xe5,0x5a,0xb4,0x01,0x05, ++0x75,0x63,0x03,0x80,0x03,0x75,0x63,0x01,0xd3,0x90,0x9e,0x3b,0xe0,0x94,0x03,0x90, ++0x9e,0x3a,0xe0,0x94,0x00,0x40,0x03,0xe4,0xf5,0x63,0xd3,0x90,0x9e,0x3b,0xe0,0x94, ++0x03,0x90,0x9e,0x3a,0xe0,0x94,0x00,0x40,0x03,0xe4,0xf5,0x63,0x74,0x84,0x25,0x59, ++0xf5,0x82,0xe4,0x34,0x98,0xf5,0x83,0xe5,0x63,0xf0,0xfd,0xaf,0x59,0x12,0x65,0x72, ++0x74,0xe6,0x25,0x59,0xf5,0x82,0xe4,0x34,0x9c,0xf5,0x83,0xe0,0xd3,0x94,0x05,0x74, ++0xe6,0x50,0x0e,0x25,0x59,0xf5,0x82,0xe4,0x34,0x9c,0xf5,0x83,0xe0,0x04,0xf0,0x80, ++0x0b,0x25,0x59,0xf5,0x82,0xe4,0x34,0x9c,0xf5,0x83,0xe4,0xf0,0xab,0x5e,0xaa,0x5f, ++0xa9,0x60,0xe4,0xf5,0xf0,0x12,0x42,0xfa,0xab,0x5e,0xaa,0x5f,0xa9,0x60,0x90,0x00, ++0x02,0xe4,0xf5,0xf0,0x12,0x43,0x19,0x90,0x00,0x04,0xe4,0xf5,0xf0,0x12,0x43,0x19, ++0x90,0x00,0x06,0xe4,0xf5,0xf0,0x12,0x43,0x19,0x90,0x00,0x08,0xe4,0xf5,0xf0,0x12, ++0x43,0x19,0xe5,0x59,0x25,0xe0,0x24,0x80,0xf5,0x82,0xe4,0x34,0x93,0xf5,0x83,0xe4, ++0xf0,0xa3,0xf0,0xe5,0x59,0x25,0xe0,0x24,0xc4,0xf5,0x82,0xe4,0x34,0x98,0xf5,0x83, ++0xe4,0xf0,0xa3,0xf0,0xe5,0x59,0x25,0xe0,0x24,0x44,0xf5,0x82,0xe4,0x34,0x99,0xf5, ++0x83,0xe4,0xf0,0xa3,0xf0,0x05,0x59,0xe5,0x59,0xc3,0x94,0x40,0x50,0x02,0x21,0x54, ++0x22,0x90,0x04,0x44,0x74,0x11,0xf0,0xa3,0x74,0xf0,0xf0,0xa3,0x74,0x0f,0xf0,0xa3, ++0xe4,0xf0,0xfd,0x74,0xa4,0x2d,0xf5,0x82,0xe4,0x34,0x04,0xf5,0x83,0xe4,0xf0,0x0d, ++0xbd,0x10,0xf0,0xe4,0x90,0x9a,0xc5,0xf0,0x90,0x95,0x01,0x04,0xf0,0xe4,0xfd,0x75, ++0xf0,0x0a,0xed,0x90,0x90,0x00,0x12,0x43,0x5f,0xe4,0xf0,0xa3,0xf0,0x75,0xf0,0x0a, ++0xed,0x90,0x90,0x02,0x12,0x43,0x5f,0xe4,0xf0,0xa3,0xf0,0x75,0xf0,0x0a,0xed,0x90, ++0x90,0x04,0x12,0x43,0x5f,0xe4,0xf0,0xa3,0xf0,0x75,0xf0,0x0a,0xed,0x90,0x90,0x06, ++0x12,0x43,0x5f,0xe4,0xf0,0xa3,0xf0,0x75,0xf0,0x0a,0xed,0x90,0x90,0x08,0x12,0x43, ++0x5f,0xe4,0xf0,0xa3,0xf0,0x74,0x26,0x2d,0xf5,0x82,0xe4,0x34,0x9d,0xf5,0x83,0x74, ++0x13,0xf0,0x74,0x85,0x2d,0xf5,0x82,0xe4,0x34,0x9a,0xf5,0x83,0xe4,0xf0,0x74,0x84, ++0x2d,0xf5,0x82,0xe4,0x34,0x98,0xf5,0x83,0xe4,0xf0,0xed,0x25,0xe0,0x24,0x80,0xf5, ++0x82,0xe4,0x34,0x93,0xf5,0x83,0xe4,0xf0,0xa3,0xf0,0xed,0x25,0xe0,0x24,0xc4,0xf5, ++0x82,0xe4,0x34,0x98,0xf5,0x83,0xe4,0xf0,0xa3,0xf0,0xed,0x25,0xe0,0x24,0xc4,0xf5, ++0x82,0xe4,0x34,0x99,0xf5,0x83,0xe4,0xf0,0xa3,0xf0,0xed,0x25,0xe0,0x24,0x44,0xf5, ++0x82,0xe4,0x34,0x99,0xf5,0x83,0xe4,0xf0,0xa3,0xf0,0xed,0x25,0xe0,0x24,0xc6,0xf5, ++0x82,0xe4,0x34,0x9a,0xf5,0x83,0xe4,0xf0,0xa3,0xf0,0xed,0x25,0xe0,0x24,0x46,0xf5, ++0x82,0xe4,0x34,0x9b,0xf5,0x83,0xe4,0xf0,0xa3,0xf0,0x74,0x86,0x2d,0xf5,0x82,0xe4, ++0x34,0x9c,0xf5,0x83,0xe4,0xf0,0x74,0x46,0x2d,0xf5,0x82,0xe4,0x34,0x9c,0xf5,0x83, ++0xe4,0xf0,0x74,0xe6,0x2d,0xf5,0x82,0xe4,0x34,0x9c,0xf5,0x83,0xe4,0xf0,0x90,0x41, ++0xc4,0x93,0xfe,0x74,0x01,0x93,0xff,0x90,0x41,0x8c,0x74,0x01,0x93,0x2f,0xff,0xe4, ++0x93,0x3e,0xc3,0x13,0xfe,0xef,0x13,0xff,0xed,0x25,0xe0,0x24,0xc2,0xf5,0x82,0xe4, ++0x34,0x95,0xf5,0x83,0xee,0xf0,0xa3,0xef,0xf0,0x75,0xf0,0x09,0xed,0x90,0x96,0x4b, ++0x12,0x43,0x5f,0x74,0x01,0xf0,0x75,0xf0,0x09,0xed,0x90,0x96,0x4a,0x12,0x43,0x5f, ++0x74,0x01,0xf0,0x74,0x82,0x2d,0xf5,0x82,0xe4,0x34,0x95,0xf5,0x83,0x74,0x0c,0xf0, ++0x75,0xf0,0x09,0xed,0x90,0x96,0x46,0x12,0x43,0x5f,0x74,0xff,0xf0,0xa3,0xf0,0x75, ++0xf0,0x09,0xed,0x90,0x96,0x44,0x12,0x43,0x5f,0xe4,0xf0,0xa3,0x74,0x0f,0xf0,0x75, ++0xf0,0x09,0xed,0x90,0x96,0x48,0x12,0x43,0x5f,0x74,0x13,0xf0,0x75,0xf0,0x09,0xed, ++0x90,0x96,0x49,0x12,0x43,0x5f,0xe4,0xf0,0xed,0xc3,0x94,0x20,0x50,0x0f,0x74,0x84, ++0x2d,0xf5,0x82,0xe4,0x34,0x04,0xf5,0x83,0x74,0x13,0xf0,0x80,0x0d,0x74,0xa6,0x2d, ++0xf5,0x82,0xe4,0x34,0x9c,0xf5,0x83,0x74,0x13,0xf0,0x0d,0xed,0x64,0x40,0x60,0x03, ++0x02,0x6f,0xcf,0x22,0x12,0x24,0x62,0xf5,0x59,0xc3,0x94,0x40,0x50,0x15,0x90,0x00, ++0x02,0x12,0x42,0x20,0xff,0x74,0x44,0x25,0x59,0xf5,0x82,0xe4,0x34,0x9a,0xf5,0x83, ++0xef,0xf0,0x22,0xe5,0x59,0xb4,0x40,0x0a,0x90,0x00,0x02,0x12,0x42,0x20,0x90,0x96, ++0x42,0xf0,0x22,0x90,0x00,0x04,0x12,0x42,0x20,0xff,0x54,0x3f,0xfe,0xef,0x54,0x80, ++0xc4,0x13,0x13,0x13,0x54,0x01,0xfd,0xaf,0x06,0x02,0x53,0xa4,0x12,0x24,0x62,0x90, ++0x95,0x01,0xf0,0x22,0x12,0x24,0x62,0xf5,0x73,0x22,0x90,0x00,0x02,0x12,0x42,0x20, ++0xff,0x30,0xe0,0x25,0x12,0x24,0x62,0x90,0x9e,0x56,0xf0,0x90,0x00,0x01,0x12,0x42, ++0x20,0x90,0x9e,0x57,0xf0,0xef,0xc3,0x13,0x54,0x7f,0x90,0x9e,0x55,0xf0,0x90,0x00, ++0x03,0x12,0x42,0x20,0x90,0x9e,0x5b,0xf0,0x22,0x90,0x9e,0x56,0x74,0x01,0xf0,0x90, ++0x9e,0x57,0x74,0x03,0xf0,0x90,0x9e,0x55,0x74,0x14,0xf0,0x90,0x9e,0x5b,0x74,0x05, ++0xf0,0x22,0x12,0x24,0x62,0x30,0xe0,0x18,0xc3,0x13,0x54,0x7f,0x90,0x9e,0x5a,0xf0, ++0x90,0x00,0x01,0x12,0x42,0x20,0xff,0x90,0x9e,0x58,0xe4,0xf0,0xa3,0xef,0xf0,0x22, ++0x90,0x9e,0x5a,0x74,0x07,0xf0,0x90,0x9e,0x58,0xe4,0xf0,0xa3,0x74,0x02,0xf0,0x22, ++0x90,0x02,0x09,0xe0,0xfd,0x12,0x24,0x62,0xfe,0xaf,0x05,0xed,0x2e,0x90,0x9e,0x67, ++0xf0,0x90,0x00,0x01,0x12,0x42,0x20,0xff,0xed,0x2f,0x90,0x9e,0x68,0xf0,0x90,0x00, ++0x02,0x12,0x42,0x20,0xff,0xed,0x2f,0x90,0x9e,0x69,0xf0,0x90,0x00,0x03,0x12,0x42, ++0x20,0xff,0xed,0x2f,0x90,0x9e,0x6a,0xf0,0x90,0x00,0x04,0x12,0x42,0x20,0xff,0xae, ++0x05,0xed,0x2f,0x90,0x9e,0x6b,0xf0,0x22,0xd3,0x10,0xaf,0x01,0xc3,0xc0,0xd0,0x90, ++0x9e,0x3f,0x12,0x43,0x8b,0x90,0x9e,0x3f,0x12,0x43,0x6b,0x90,0x00,0x01,0x12,0x42, ++0xc2,0xfa,0xe5,0xf0,0x24,0x00,0xff,0xe4,0x3a,0xfe,0x90,0x9e,0x3f,0x12,0x43,0x6b, ++0x90,0x00,0x01,0xee,0x8f,0xf0,0x12,0x43,0x19,0x12,0x24,0x62,0xff,0x60,0x2c,0xb5, ++0x22,0x16,0x90,0x9e,0x3f,0x12,0x43,0x6b,0x90,0x00,0x01,0x12,0x42,0xc2,0x65,0x24, ++0x70,0x04,0xe5,0x23,0x65,0xf0,0x60,0x23,0x90,0x9e,0x3f,0x12,0x43,0x6b,0x90,0x00, ++0x01,0x12,0x42,0xc2,0xff,0xae,0xf0,0x71,0x00,0x80,0x10,0x90,0x9e,0x3f,0x12,0x43, ++0x6b,0x12,0x24,0x62,0x65,0x22,0x60,0x03,0x12,0x44,0xca,0xd0,0xd0,0x92,0xaf,0x22, ++0x90,0x9e,0x42,0xee,0xf0,0xa3,0xef,0xf0,0x75,0x22,0x01,0x8e,0x23,0xf5,0x24,0xe4, ++0xfd,0x7f,0x0b,0x71,0x44,0xe4,0xfd,0x7f,0x02,0x71,0x44,0x12,0x4f,0xbe,0xe4,0xff, ++0x12,0x44,0xf1,0xe4,0xf5,0x26,0x90,0x01,0xc9,0xe5,0x26,0xf0,0x90,0x9e,0x42,0xe0, ++0xfc,0xa3,0xe0,0xfd,0xec,0xfb,0x8d,0x44,0xe4,0xf5,0x45,0x7d,0x01,0x7f,0x60,0x7e, ++0x01,0x02,0x30,0x62,0xd3,0x10,0xaf,0x01,0xc3,0xc0,0xd0,0x90,0x9e,0x45,0xed,0xf0, ++0x90,0x9e,0x44,0xef,0xf0,0xd3,0x94,0x07,0x50,0x4f,0xa3,0xe0,0x70,0x1a,0x90,0x9e, ++0x44,0xe0,0xff,0x74,0x01,0xa8,0x07,0x08,0x80,0x02,0xc3,0x33,0xd8,0xfc,0xf4,0xff, ++0x90,0x00,0x47,0xe0,0x5f,0xf0,0x80,0x17,0x90,0x9e,0x44,0xe0,0xff,0x74,0x01,0xa8, ++0x07,0x08,0x80,0x02,0xc3,0x33,0xd8,0xfc,0xff,0x90,0x00,0x47,0xe0,0x4f,0xf0,0x12, ++0x49,0xb9,0x90,0x9e,0x44,0xe0,0xff,0x74,0x01,0xa8,0x07,0x08,0x80,0x02,0xc3,0x33, ++0xd8,0xfc,0xf4,0xff,0x90,0x00,0x46,0x80,0x5a,0x90,0x9e,0x44,0xe0,0x24,0xf8,0xf0, ++0xa3,0xe0,0x70,0x1d,0x90,0x9e,0x44,0xe0,0xff,0x74,0x01,0xa8,0x07,0x08,0x80,0x02, ++0xc3,0x33,0xd8,0xfc,0xc4,0x54,0xf0,0xf4,0xff,0x90,0x00,0x43,0xe0,0x5f,0xf0,0x80, ++0x1a,0x90,0x9e,0x44,0xe0,0xff,0x74,0x01,0xa8,0x07,0x08,0x80,0x02,0xc3,0x33,0xd8, ++0xfc,0xc4,0x54,0xf0,0xff,0x90,0x00,0x43,0xe0,0x4f,0xf0,0x12,0x49,0xb9,0x90,0x9e, ++0x44,0xe0,0xff,0x74,0x01,0xa8,0x07,0x08,0x80,0x02,0xc3,0x33,0xd8,0xfc,0xf4,0xff, ++0x90,0x00,0x43,0xe0,0x5f,0xf0,0x12,0x49,0xb9,0xd0,0xd0,0x92,0xaf,0x22,0xd3,0x10, ++0xaf,0x01,0xc3,0xc0,0xd0,0x90,0x9e,0x6d,0xe0,0x90,0x9e,0x40,0xf0,0x90,0x9e,0x6e, ++0xe0,0xf5,0x64,0xa3,0xe0,0xf5,0x65,0xe4,0xf5,0x61,0x74,0x70,0x25,0x61,0xf5,0x82, ++0xe4,0x34,0x9e,0xf5,0x83,0xe0,0xff,0x74,0x66,0x25,0x61,0xf8,0xa6,0x07,0x05,0x61, ++0xe5,0x61,0xb4,0x04,0xe5,0x90,0x9e,0x40,0xe0,0x12,0x43,0x94,0x74,0x6b,0x00,0x75, ++0x93,0x01,0x74,0x71,0x02,0x74,0x71,0x03,0x74,0x71,0x04,0x75,0x93,0x05,0x75,0x63, ++0x80,0x75,0x79,0x81,0x75,0x93,0x82,0x00,0x00,0x75,0x8f,0xaf,0x69,0xb1,0x9a,0xa1, ++0x93,0x90,0x9e,0x40,0xe0,0xff,0xb4,0x02,0x08,0x90,0x9e,0x3f,0x74,0x01,0xf0,0x80, ++0x0f,0xef,0x90,0x9e,0x3f,0xb4,0x03,0x05,0x74,0x02,0xf0,0x80,0x03,0x74,0x04,0xf0, ++0xc3,0xe5,0x64,0x94,0x08,0x50,0x49,0xe4,0xf5,0x61,0x90,0x9e,0x3f,0xe0,0xff,0xe5, ++0x61,0xc3,0x9f,0x40,0x02,0xa1,0x93,0xc3,0xe5,0x64,0x94,0x01,0x50,0x14,0xe5,0x61, ++0x25,0x65,0xff,0xc3,0x74,0x03,0x95,0x61,0x24,0x66,0xf8,0xe6,0xfd,0x12,0x4a,0xc1, ++0x80,0x1a,0xc3,0x74,0x03,0x95,0x61,0x24,0x66,0xf8,0xe6,0xff,0xe5,0x61,0x7c,0x00, ++0x25,0x65,0xfd,0xec,0x35,0x64,0x8d,0x82,0xf5,0x83,0xef,0xf0,0x05,0x61,0x80,0xba, ++0xc3,0xe5,0x64,0x94,0x10,0x40,0x02,0xa1,0x93,0x90,0x9e,0x40,0xe0,0x64,0x04,0x60, ++0x02,0xa1,0x93,0xaf,0x67,0xfc,0xfd,0xfe,0x78,0x10,0x12,0x24,0xf5,0xc0,0x04,0xc0, ++0x05,0xc0,0x06,0xc0,0x07,0xaf,0x66,0xe4,0xfc,0xfd,0xfe,0x78,0x18,0x12,0x24,0xf5, ++0xd0,0x03,0xd0,0x02,0xd0,0x01,0xd0,0x00,0x12,0x43,0x46,0xc0,0x04,0xc0,0x05,0xc0, ++0x06,0xc0,0x07,0xaf,0x68,0xe4,0xfc,0xfd,0xfe,0x78,0x08,0x12,0x24,0xf5,0xd0,0x03, ++0xd0,0x02,0xd0,0x01,0xd0,0x00,0x12,0x43,0x46,0xa8,0x04,0xa9,0x05,0xaa,0x06,0xab, ++0x07,0xaf,0x69,0xe4,0xfc,0xfd,0xfe,0x12,0x43,0x46,0xa3,0x12,0x25,0x08,0x90,0x9e, ++0x41,0x12,0x43,0x53,0x90,0x80,0x96,0x12,0x25,0x08,0xaf,0x65,0xae,0x64,0x12,0x2b, ++0x08,0x80,0x30,0xe5,0x68,0x7f,0x00,0xfe,0xef,0x25,0x69,0xf5,0x63,0xe4,0x3e,0xf5, ++0x62,0xaf,0x63,0xfe,0x12,0x32,0x15,0x80,0x1a,0xe5,0x68,0x7f,0x00,0xfe,0xef,0x25, ++0x69,0xf5,0x63,0xe4,0x3e,0xf5,0x62,0xaf,0x63,0xfe,0x12,0x31,0x82,0x80,0x04,0x7f, ++0x00,0x80,0x02,0x7f,0x01,0xd0,0xd0,0x92,0xaf,0x22,0x8f,0x6a,0xe4,0x90,0x9e,0x45, ++0xf0,0xe5,0x6a,0x14,0xfe,0x90,0x9e,0x45,0xe0,0xff,0xc3,0x9e,0x50,0x0e,0xef,0x04, ++0xfd,0x12,0x2d,0x4d,0x90,0x9e,0x45,0xe0,0x04,0xf0,0x80,0xe5,0xe5,0x6a,0x14,0xff, ++0x7d,0xff,0x12,0x2d,0x4d,0x90,0x9e,0x45,0xe5,0x6a,0xf0,0x90,0x9e,0x45,0xe0,0xc3, ++0x94,0xff,0x50,0x0f,0xe0,0xff,0x04,0xfd,0x12,0x2d,0x4d,0x90,0x9e,0x45,0xe0,0x04, ++0xf0,0x80,0xe8,0xad,0x6a,0x7f,0xff,0x02,0x2d,0x4d,0xd3,0x10,0xaf,0x01,0xc3,0xc0, ++0xd0,0xe4,0xf5,0x5b,0x75,0x5c,0x04,0xf5,0x5d,0xf5,0x5f,0xf5,0x60,0x90,0x02,0x09, ++0xe0,0xff,0x12,0x24,0x62,0xfe,0xef,0x2e,0xf5,0x5e,0x30,0xe0,0x08,0x75,0x59,0x00, ++0x75,0x5a,0x80,0x80,0x05,0xe4,0xf5,0x59,0xf5,0x5a,0xe5,0x5e,0xc3,0x13,0x90,0xfd, ++0x10,0xf0,0x74,0x20,0x25,0x5b,0xf5,0x5b,0xad,0x5a,0xe5,0x5b,0x2d,0xff,0x24,0x01, ++0xf5,0x82,0xe4,0x34,0xfc,0xf5,0x83,0xe0,0x90,0x9e,0x6d,0xf0,0x74,0x02,0x2f,0xf5, ++0x82,0xe4,0x34,0xfc,0xf5,0x83,0xe0,0xfe,0xe5,0x5b,0x2d,0x24,0x03,0xf5,0x82,0xe4, ++0x34,0xfc,0xf5,0x83,0xe0,0x24,0x00,0xff,0xe4,0x3e,0x90,0x9e,0x6e,0xf0,0xa3,0xef, ++0xf0,0x7f,0x04,0xe5,0x5b,0x25,0x5a,0x2f,0x24,0x00,0xf5,0x82,0xe4,0x34,0xfc,0xf5, ++0x83,0xe0,0xfe,0x74,0x6c,0x2f,0xf5,0x82,0xe4,0x34,0x9e,0xf5,0x83,0xee,0xf0,0x0f, ++0xbf,0x08,0xe0,0x91,0x0e,0xef,0x70,0x3f,0x90,0x01,0xc3,0xe0,0x60,0x25,0xc3,0xe5, ++0x60,0x94,0xe8,0xe5,0x5f,0x94,0x03,0x40,0x09,0x90,0x01,0xc6,0xe0,0x44,0x10,0xf0, ++0x80,0x63,0x05,0x60,0xe5,0x60,0x70,0x02,0x05,0x5f,0x7f,0x0a,0x7e,0x00,0x12,0x32, ++0x15,0x80,0xd5,0x90,0x01,0xc6,0xe0,0x90,0x01,0xc3,0x30,0xe2,0x05,0x74,0xfe,0xf0, ++0x80,0x43,0x74,0xff,0xf0,0x80,0x3e,0xe5,0x5b,0xb4,0x78,0x23,0xe4,0xf5,0x5b,0x05, ++0x5e,0xe5,0x5a,0x64,0x80,0x45,0x59,0x70,0x06,0xf5,0x59,0xf5,0x5a,0x80,0x06,0x75, ++0x59,0x00,0x75,0x5a,0x80,0xe5,0x5e,0xc3,0x13,0x90,0xfd,0x10,0xf0,0x80,0x06,0x74, ++0x08,0x25,0x5b,0xf5,0x5b,0xe5,0x5d,0x15,0x5d,0x70,0x02,0x15,0x5c,0xe5,0x5d,0x45, ++0x5c,0x60,0x02,0xc1,0x28,0xd0,0xd0,0x92,0xaf,0x22,0x90,0x06,0x34,0x74,0xff,0xf0, ++0xe4,0xa3,0xf0,0xa3,0xf0,0xa3,0xf0,0x22,0xe4,0xf5,0x25,0x22,0xe4,0x90,0x9e,0xaa, ++0xf0,0xa3,0xf0,0x90,0x05,0xf8,0xe0,0x70,0x0f,0xa3,0xe0,0x70,0x0b,0xa3,0xe0,0x70, ++0x07,0xa3,0xe0,0x70,0x03,0x7f,0x01,0x22,0xd3,0x90,0x9e,0xab,0xe0,0x94,0xe8,0x90, ++0x9e,0xaa,0xe0,0x94,0x03,0x40,0x03,0x7f,0x00,0x22,0x7f,0x32,0x7e,0x00,0x12,0x32, ++0x15,0x90,0x9e,0xaa,0xe4,0x75,0xf0,0x01,0x12,0x42,0x81,0x80,0xc6,0x90,0x9e,0x77, ++0xe0,0x90,0x9e,0x0f,0xf0,0x22,0xef,0x70,0x03,0x02,0x79,0x1e,0x90,0x9e,0x0f,0xe0, ++0x60,0x03,0x02,0x7c,0xe9,0x90,0x9d,0xfb,0x12,0x43,0x53,0x90,0x80,0x96,0x12,0x25, ++0x08,0x7f,0x8c,0x7e,0x08,0x12,0x2b,0x08,0x90,0x9d,0xa7,0x12,0x43,0x53,0x90,0x80, ++0x96,0x12,0x25,0x08,0x7f,0x44,0x7e,0x08,0x12,0x2b,0x08,0x90,0x9d,0xab,0x12,0x43, ++0x53,0x90,0x80,0x96,0x12,0x25,0x08,0x7f,0x5c,0x7e,0x08,0x12,0x2b,0x08,0x90,0x9d, ++0xaf,0x12,0x43,0x53,0x90,0x80,0x96,0x12,0x25,0x08,0x7f,0x6c,0x7e,0x0e,0x12,0x2b, ++0x08,0x90,0x9d,0xb3,0x12,0x43,0x53,0x90,0x80,0x96,0x12,0x25,0x08,0x7f,0x70,0x7e, ++0x0e,0x12,0x2b,0x08,0x90,0x9d,0xb7,0x12,0x43,0x53,0x90,0x80,0x96,0x12,0x25,0x08, ++0x7f,0x74,0x7e,0x0e,0x12,0x2b,0x08,0x90,0x9d,0xbb,0x12,0x43,0x53,0x90,0x80,0x96, ++0x12,0x25,0x08,0x7f,0x78,0x7e,0x0e,0x12,0x2b,0x08,0x90,0x9d,0xbf,0x12,0x43,0x53, ++0x90,0x80,0x96,0x12,0x25,0x08,0x7f,0x7c,0x7e,0x0e,0x12,0x2b,0x08,0x90,0x9d,0xc3, ++0x12,0x43,0x53,0x90,0x80,0x96,0x12,0x25,0x08,0x7f,0x80,0x7e,0x0e,0x12,0x2b,0x08, ++0x90,0x9d,0xc7,0x12,0x43,0x53,0x90,0x80,0x96,0x12,0x25,0x08,0x7f,0x84,0x7e,0x0e, ++0x12,0x2b,0x08,0x90,0x9d,0xcb,0x12,0x43,0x53,0x90,0x80,0x96,0x12,0x25,0x08,0x7f, ++0x88,0x7e,0x0e,0x12,0x2b,0x08,0x90,0x9d,0xcf,0x12,0x43,0x53,0x90,0x80,0x96,0x12, ++0x25,0x08,0x7f,0x8c,0x7e,0x0e,0x12,0x2b,0x08,0x90,0x9d,0xd3,0x12,0x43,0x53,0x90, ++0x80,0x96,0x12,0x25,0x08,0x7f,0xd0,0x7e,0x0e,0x12,0x2b,0x08,0x90,0x9d,0xd7,0x12, ++0x43,0x53,0x90,0x80,0x96,0x12,0x25,0x08,0x7f,0xd4,0x7e,0x0e,0x12,0x2b,0x08,0x90, ++0x9d,0xdb,0x12,0x43,0x53,0x90,0x80,0x96,0x12,0x25,0x08,0x7f,0xd8,0x7e,0x0e,0x12, ++0x2b,0x08,0x90,0x9d,0xdf,0x12,0x43,0x53,0x90,0x80,0x96,0x12,0x25,0x08,0x7f,0xdc, ++0x7e,0x0e,0x12,0x2b,0x08,0x90,0x9d,0xe3,0x12,0x43,0x53,0x90,0x80,0x96,0x12,0x25, ++0x08,0x7f,0xe0,0x7e,0x0e,0x12,0x2b,0x08,0x90,0x9d,0xe7,0x12,0x43,0x53,0x90,0x80, ++0x96,0x12,0x25,0x08,0x7f,0xec,0x7e,0x0e,0x12,0x2b,0x08,0x90,0x9d,0xeb,0x12,0x43, ++0x53,0x90,0x80,0x96,0x12,0x25,0x08,0x7f,0x04,0x7e,0x0c,0x12,0x2b,0x08,0x90,0x9d, ++0xef,0x12,0x43,0x53,0x90,0x80,0x96,0x12,0x25,0x08,0x7f,0x04,0x7e,0x0d,0x12,0x2b, ++0x08,0x90,0x9d,0xf3,0x12,0x43,0x53,0x90,0x80,0x96,0x12,0x25,0x08,0x7f,0x0c,0x7e, ++0x09,0x12,0x2b,0x08,0x90,0x9d,0xf7,0x12,0x43,0x53,0x90,0x80,0x96,0x12,0x25,0x08, ++0x7f,0x04,0x7e,0x08,0x12,0x2b,0x08,0x90,0x9e,0x0f,0x74,0x01,0xf0,0x22,0x90,0x9e, ++0x0f,0xe0,0x64,0x01,0x60,0x02,0x81,0xe9,0x7f,0x8c,0x7e,0x08,0x12,0x22,0x65,0x90, ++0x9d,0xfb,0x12,0x25,0x08,0x7f,0x44,0x7e,0x08,0x12,0x22,0x65,0x90,0x9d,0xa7,0x12, ++0x25,0x08,0x7f,0x5c,0x7e,0x08,0x12,0x22,0x65,0x90,0x9d,0xab,0x12,0x25,0x08,0x7f, ++0x6c,0x7e,0x0e,0x12,0x22,0x65,0x90,0x9d,0xaf,0x12,0x25,0x08,0x7f,0x70,0x7e,0x0e, ++0x12,0x22,0x65,0x90,0x9d,0xb3,0x12,0x25,0x08,0x7f,0x74,0x7e,0x0e,0x12,0x22,0x65, ++0x90,0x9d,0xb7,0x12,0x25,0x08,0x7f,0x78,0x7e,0x0e,0x12,0x22,0x65,0x90,0x9d,0xbb, ++0x12,0x25,0x08,0x7f,0x7c,0x7e,0x0e,0x12,0x22,0x65,0x90,0x9d,0xbf,0x12,0x25,0x08, ++0x7f,0x80,0x7e,0x0e,0x12,0x22,0x65,0x90,0x9d,0xc3,0x12,0x25,0x08,0x7f,0x84,0x7e, ++0x0e,0x12,0x22,0x65,0x90,0x9d,0xc7,0x12,0x25,0x08,0x7f,0x88,0x7e,0x0e,0x12,0x22, ++0x65,0x90,0x9d,0xcb,0x12,0x25,0x08,0x7f,0x8c,0x7e,0x0e,0x12,0x22,0x65,0x90,0x9d, ++0xcf,0x12,0x25,0x08,0x7f,0xd0,0x7e,0x0e,0x12,0x22,0x65,0x90,0x9d,0xd3,0x12,0x25, ++0x08,0x7f,0xd4,0x7e,0x0e,0x12,0x22,0x65,0x90,0x9d,0xd7,0x12,0x25,0x08,0x7f,0xd8, ++0x7e,0x0e,0x12,0x22,0x65,0x90,0x9d,0xdb,0x12,0x25,0x08,0x7f,0xdc,0x7e,0x0e,0x12, ++0x22,0x65,0x90,0x9d,0xdf,0x12,0x25,0x08,0x7f,0xe0,0x7e,0x0e,0x12,0x22,0x65,0x90, ++0x9d,0xe3,0x12,0x25,0x08,0x7f,0xec,0x7e,0x0e,0x12,0x22,0x65,0x90,0x9d,0xe7,0x12, ++0x25,0x08,0x7f,0x04,0x7e,0x0c,0x12,0x22,0x65,0x90,0x9d,0xeb,0x12,0x25,0x08,0x7f, ++0x04,0x7e,0x0d,0x12,0x22,0x65,0x90,0x9d,0xef,0x12,0x25,0x08,0x7f,0x0c,0x7e,0x09, ++0x12,0x22,0x65,0x90,0x9d,0xf3,0x12,0x25,0x08,0x7f,0x04,0x7e,0x08,0x12,0x22,0x65, ++0x90,0x9d,0xf7,0x12,0x25,0x08,0x7f,0x8c,0x7e,0x08,0x12,0x22,0x65,0x90,0x9e,0xa4, ++0x12,0x25,0x08,0x90,0x9e,0xa4,0x12,0x43,0x53,0xed,0x44,0xc0,0xfd,0xec,0x90,0x9e, ++0xa4,0x12,0x25,0x08,0x90,0x9e,0xa4,0x12,0x43,0x53,0x90,0x80,0x96,0x12,0x25,0x08, ++0x7f,0x8c,0x7e,0x08,0x12,0x2b,0x08,0x90,0x80,0x96,0x12,0x25,0x14,0x00,0x01,0x00, ++0x00,0x7f,0x44,0x7e,0x08,0x12,0x2b,0x08,0x90,0x80,0x96,0x12,0x25,0x14,0x00,0xdb, ++0x25,0xa4,0x7f,0x5c,0x7e,0x08,0x12,0x2b,0x08,0x90,0x80,0x96,0x12,0x25,0x14,0x20, ++0xdb,0x25,0xa4,0x7f,0x6c,0x7e,0x0e,0x12,0x2b,0x08,0x90,0x80,0x96,0x12,0x25,0x14, ++0x20,0xdb,0x25,0xa4,0x7f,0x70,0x7e,0x0e,0x12,0x2b,0x08,0x90,0x80,0x96,0x12,0x25, ++0x14,0x04,0x1b,0x25,0xa4,0x7f,0x74,0x7e,0x0e,0x12,0x2b,0x08,0x90,0x80,0x96,0x12, ++0x25,0x14,0x04,0x1b,0x25,0xa4,0x7f,0x78,0x7e,0x0e,0x12,0x2b,0x08,0x90,0x80,0x96, ++0x12,0x25,0x14,0x04,0x1b,0x25,0xa4,0x7f,0x7c,0x7e,0x0e,0x12,0x2b,0x08,0x90,0x80, ++0x96,0x12,0x25,0x14,0x04,0x1b,0x25,0xa4,0x7f,0x80,0x7e,0x0e,0x12,0x2b,0x08,0x90, ++0x80,0x96,0x12,0x25,0x14,0x63,0xdb,0x25,0xa4,0x7f,0x84,0x7e,0x0e,0x12,0x2b,0x08, ++0x90,0x80,0x96,0x12,0x25,0x14,0x04,0x1b,0x25,0xa4,0x7f,0x88,0x7e,0x0e,0x12,0x2b, ++0x08,0x90,0x80,0x96,0x12,0x25,0x14,0x20,0xdb,0x25,0xa4,0x7f,0x8c,0x7e,0x0e,0x12, ++0x2b,0x08,0x90,0x80,0x96,0x12,0x25,0x14,0x20,0xdb,0x25,0xa4,0x7f,0xd0,0x7e,0x0e, ++0x12,0x2b,0x08,0x90,0x80,0x96,0x12,0x25,0x14,0x20,0xdb,0x25,0xa4,0x7f,0xd4,0x7e, ++0x0e,0x12,0x2b,0x08,0x90,0x80,0x96,0x12,0x25,0x14,0x20,0xdb,0x25,0xa4,0x7f,0xd8, ++0x7e,0x0e,0x12,0x2b,0x08,0x90,0x80,0x96,0x12,0x25,0x14,0x00,0x1b,0x25,0xa4,0x7f, ++0xdc,0x7e,0x0e,0x12,0x2b,0x08,0x90,0x80,0x96,0x12,0x25,0x14,0x00,0x1b,0x25,0xa4, ++0x7f,0xe0,0x7e,0x0e,0x12,0x2b,0x08,0x90,0x80,0x96,0x12,0x25,0x14,0x24,0xdb,0x25, ++0xa4,0x7f,0xec,0x7e,0x0e,0x12,0x2b,0x08,0x7f,0x04,0x7e,0x0c,0x12,0x22,0x65,0x90, ++0x9e,0xa4,0x12,0x25,0x08,0x90,0x9e,0xa4,0x12,0x43,0x53,0xe4,0xff,0xec,0x90,0x9e, ++0xa4,0x12,0x25,0x08,0x90,0x9e,0xa4,0x12,0x43,0x53,0xef,0x44,0x11,0xff,0xec,0x90, ++0x9e,0xa4,0x12,0x25,0x08,0x90,0x9e,0xa4,0x12,0x43,0x53,0x90,0x80,0x96,0x12,0x25, ++0x08,0x7f,0x04,0x7e,0x0c,0x12,0x2b,0x08,0x7f,0x04,0x7e,0x0d,0x12,0x22,0x65,0x90, ++0x9e,0xa4,0x12,0x25,0x08,0x90,0x9e,0xa4,0x12,0x43,0x53,0xef,0x54,0xf0,0xff,0xec, ++0x90,0x9e,0xa4,0x12,0x25,0x08,0x90,0x9e,0xa4,0x12,0x43,0x53,0xef,0x44,0x01,0xff, ++0xec,0x90,0x9e,0xa4,0x12,0x25,0x08,0x90,0x9e,0xa4,0x12,0x43,0x53,0x90,0x80,0x96, ++0x12,0x25,0x08,0x7f,0x04,0x7e,0x0d,0x12,0x2b,0x08,0x7f,0x0c,0x7e,0x09,0x12,0x22, ++0x65,0x90,0x9e,0xa4,0x12,0x25,0x08,0x90,0x9e,0xa4,0x12,0x43,0x53,0xe4,0xff,0xec, ++0x90,0x9e,0xa4,0x12,0x25,0x08,0x90,0x9e,0xa4,0x12,0x43,0x53,0xef,0x44,0x11,0xff, ++0xec,0x90,0x9e,0xa4,0x12,0x25,0x08,0x90,0x9e,0xa4,0x12,0x43,0x53,0x90,0x80,0x96, ++0x12,0x25,0x08,0x7f,0x0c,0x7e,0x09,0x12,0x2b,0x08,0x7f,0x0c,0x7e,0x09,0x12,0x22, ++0x65,0x90,0x9e,0xa4,0x12,0x25,0x08,0x90,0x9e,0xa4,0x12,0x43,0x53,0xed,0x54,0x0f, ++0xfd,0xec,0x54,0xf0,0xfc,0x90,0x9e,0xa4,0x12,0x25,0x08,0x90,0x9e,0xa4,0x12,0x43, ++0x53,0xed,0x44,0x10,0xfd,0xec,0x44,0x01,0xfc,0x90,0x9e,0xa4,0x12,0x25,0x08,0x90, ++0x9e,0xa4,0x12,0x43,0x53,0x90,0x80,0x96,0x12,0x25,0x08,0x7f,0x0c,0x7e,0x09,0x12, ++0x2b,0x08,0x7f,0x04,0x7e,0x08,0x12,0x22,0x65,0x90,0x9e,0xa4,0x12,0x25,0x08,0x90, ++0x9e,0xa4,0x12,0x43,0x53,0xef,0x54,0xf0,0xff,0xec,0x90,0x9e,0xa4,0x12,0x25,0x08, ++0x90,0x9e,0xa4,0x12,0x43,0x53,0xef,0x44,0x01,0xff,0xec,0x90,0x9e,0xa4,0x12,0x25, ++0x08,0x90,0x9e,0xa4,0x12,0x43,0x53,0x90,0x80,0x96,0x12,0x25,0x08,0x7f,0x04,0x7e, ++0x08,0x12,0x2b,0x08,0xe4,0x90,0x9e,0x0f,0xf0,0x22,0x90,0x00,0x02,0x12,0x42,0x20, ++0x90,0x9e,0x1e,0xf0,0xe0,0x60,0x04,0xe0,0xf4,0x70,0x21,0xa2,0xaf,0xe4,0x33,0xf5, ++0x59,0xc2,0xaf,0x90,0x00,0x47,0xe0,0x54,0xfb,0xfd,0x7f,0x47,0x12,0x4a,0xc1,0x7d, ++0x40,0x7f,0x01,0x12,0x31,0x66,0xe5,0x59,0x24,0xff,0x92,0xaf,0x22,0xe4,0xfd,0x7f, ++0x45,0x12,0x4a,0xc1,0x90,0x04,0xfd,0xe4,0xf0,0xa3,0xf0,0x90,0x9e,0x1e,0xf0,0x90, ++0x9e,0x24,0xf0,0x90,0x9e,0x27,0xf0,0x90,0x9e,0x25,0xf0,0x90,0x9e,0x28,0xf0,0x90, ++0x9e,0x26,0xf0,0x90,0x9e,0x29,0xf0,0x90,0x9e,0x10,0x04,0xf0,0xe4,0xa3,0xf0,0xa3, ++0xf0,0xa3,0xf0,0x90,0x9e,0x15,0xf0,0x90,0x9e,0x1a,0xf0,0x90,0x9e,0x1c,0xf0,0x90, ++0x9e,0x2e,0xf0,0x90,0x9e,0x1f,0xf0,0x90,0x9e,0x1b,0xf0,0x90,0x9e,0x14,0xf0,0x90, ++0x00,0x51,0xe0,0x44,0xc0,0xfd,0x7f,0x51,0x02,0x4a,0xc1,0x90,0x9e,0x15,0xe0,0xc3, ++0x94,0x14,0x50,0x05,0xe0,0x04,0xf0,0xc1,0x33,0x90,0x9e,0x15,0xe0,0x64,0x14,0x60, ++0x02,0xc1,0x33,0x90,0x9e,0x24,0xe0,0x70,0x25,0x90,0x9e,0x27,0xe0,0x70,0x1f,0x90, ++0x9e,0x25,0xe0,0x70,0x19,0x90,0x9e,0x28,0xe0,0x70,0x13,0x90,0x9e,0x26,0xe0,0x70, ++0x0d,0x90,0x9e,0x29,0xe0,0x70,0x07,0x90,0x04,0xfd,0xe0,0x54,0xfe,0xf0,0x90,0x9e, ++0x24,0xe0,0x90,0x04,0x44,0xf0,0x90,0x9e,0x25,0xe0,0x90,0x04,0x45,0xf0,0x90,0x9e, ++0x26,0xe0,0x90,0x04,0x46,0xf0,0xa3,0xe4,0xf0,0x90,0x9e,0x27,0xe0,0x90,0x04,0x48, ++0xf0,0x90,0x9e,0x28,0xe0,0x90,0x04,0x49,0xf0,0x90,0x9e,0x29,0xe0,0x90,0x04,0x4a, ++0xf0,0xa3,0xe4,0xf0,0x90,0x9e,0x10,0xe0,0x90,0x04,0x4c,0xf0,0x90,0x9e,0x11,0xe0, ++0x90,0x04,0x4d,0xf0,0x90,0x9e,0x12,0xe0,0x90,0x04,0x4e,0xf0,0x90,0x9e,0x13,0xe0, ++0x90,0x04,0x4f,0xf0,0xe4,0x90,0x9e,0x15,0xf0,0x90,0x9e,0x10,0x04,0xf0,0xe4,0xa3, ++0xf0,0xa3,0xf0,0xa3,0xf0,0x90,0x9e,0x24,0xf0,0xa3,0xf0,0xa3,0xf0,0xa3,0xf0,0xa3, ++0xf0,0xa3,0xf0,0x90,0x05,0x60,0xe0,0x90,0x9e,0x34,0xf0,0x90,0x05,0x61,0xe0,0x90, ++0x9e,0x35,0xf0,0x90,0x05,0x62,0xe0,0x90,0x9e,0x36,0xf0,0x90,0x05,0x63,0xe0,0x90, ++0x9e,0x37,0xf0,0x90,0x9e,0x2d,0xe0,0xff,0x90,0x9e,0x37,0xe0,0xfe,0xd3,0x9f,0x50, ++0x0b,0x90,0x9e,0x2d,0xe0,0xc3,0x9e,0xd3,0x94,0x01,0x40,0x11,0x90,0x9e,0x1b,0xe0, ++0xb4,0x01,0x02,0x80,0x03,0x90,0x9e,0x1f,0xe0,0xff,0x12,0x4e,0xd8,0x22,0x90,0x9e, ++0x2e,0xe0,0x64,0x01,0x60,0x08,0x90,0x9e,0x1c,0xe0,0x60,0x02,0xe1,0x55,0x90,0x9e, ++0x10,0xe0,0xc3,0x94,0xff,0x50,0x05,0xe0,0x04,0xf0,0x80,0x3b,0x90,0x9e,0x11,0xe0, ++0xc3,0x94,0xff,0x50,0x06,0xe0,0x04,0xf0,0xe4,0x80,0x28,0x90,0x9e,0x12,0xe0,0xc3, ++0x94,0xff,0x50,0x0a,0xe0,0x04,0xf0,0xe4,0x90,0x9e,0x11,0xf0,0x80,0x15,0x90,0x9e, ++0x13,0xe0,0xc3,0x94,0xff,0x50,0x10,0xe0,0x04,0xf0,0xe4,0x90,0x9e,0x12,0xf0,0x90, ++0x9e,0x11,0xf0,0x90,0x9e,0x10,0xf0,0x90,0x00,0x44,0xe0,0x54,0x0c,0x60,0x76,0xe0, ++0x30,0xe2,0x32,0x90,0x9e,0x24,0xe0,0xc3,0x94,0xff,0x50,0x05,0xe0,0x04,0xf0,0x80, ++0x24,0x90,0x9e,0x25,0xe0,0xc3,0x94,0xff,0x50,0x06,0xe0,0x04,0xf0,0xe4,0x80,0x11, ++0x90,0x9e,0x26,0xe0,0xc3,0x94,0xff,0x50,0x0c,0xe0,0x04,0xf0,0xe4,0x90,0x9e,0x25, ++0xf0,0x90,0x9e,0x24,0xf0,0x90,0x00,0x44,0xe0,0x30,0xe3,0x32,0x90,0x9e,0x27,0xe0, ++0xc3,0x94,0xff,0x50,0x05,0xe0,0x04,0xf0,0x80,0x24,0x90,0x9e,0x28,0xe0,0xc3,0x94, ++0xff,0x50,0x06,0xe0,0x04,0xf0,0xe4,0x80,0x11,0x90,0x9e,0x29,0xe0,0xc3,0x94,0xff, ++0x50,0x0c,0xe0,0x04,0xf0,0xe4,0x90,0x9e,0x28,0xf0,0x90,0x9e,0x27,0xf0,0x90,0x04, ++0xfd,0xe0,0x44,0x01,0xf0,0x22,0xf5,0x67,}; ++ ++// =================== v79 UMC B Cut COMMON 2011-10-06 ===================== ++u8 Rtl8192CUFwUMCBCutImgArray[UMCBCutImgArrayLength] = { ++0xc2,0x88,0x02,0x00,0x4f,0x00,0x00,0x00,0x0a,0x06,0x18,0x11,0x5e,0x3f,0x01,0x00, ++0x61,0x80,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x02,0x43,0xba,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x02,0x49,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x02,0x5f,0x7b,0x00,0x00,0x00,0x00,0x00,0xa1,0xdf,0x00,0x00,0x00, ++0x05,0x04,0x03,0x02,0x00,0x03,0x06,0x05,0x04,0x03,0x00,0x04,0x06,0x05,0x04,0x02, ++0x00,0x04,0x08,0x07,0x06,0x04,0x00,0x06,0x0a,0x09,0x08,0x06,0x00,0x08,0x0a,0x09, ++0x08,0x04,0x00,0x08,0x0a,0x09,0x08,0x02,0x00,0x08,0x0a,0x09,0x08,0x00,0x00,0x08, ++0x12,0x11,0x10,0x08,0x00,0x10,0x1a,0x19,0x18,0x10,0x00,0x18,0x22,0x21,0x20,0x18, ++0x00,0x20,0x22,0x21,0x20,0x10,0x00,0x20,0x22,0x21,0x20,0x08,0x00,0x20,0x22,0x21, ++0x1c,0x08,0x00,0x20,0x22,0x21,0x14,0x08,0x00,0x20,0x22,0x20,0x18,0x08,0x00,0x20, ++0x31,0x30,0x20,0x10,0x00,0x30,0x31,0x30,0x18,0x00,0x00,0x30,0x31,0x2f,0x10,0x10, ++0x00,0x30,0x31,0x2c,0x10,0x10,0x00,0x30,0x31,0x28,0x10,0x00,0x00,0x30,0x31,0x20, ++0x10,0x00,0x00,0x30,0x31,0x10,0x10,0x00,0x00,0x30,0x04,0x04,0x04,0x05,0x04,0x04, ++0x04,0x05,0x05,0x05,0x06,0x06,0x04,0x04,0x04,0x05,0x05,0x05,0x06,0x06,0x04,0x04, ++0x05,0x05,0x05,0x05,0x06,0x06,0x04,0x04,0x05,0x05,0x05,0x05,0x06,0x07,0x0a,0x0b, ++0x0d,0x10,0x04,0x05,0x05,0x06,0x06,0x09,0x0c,0x11,0x08,0x08,0x09,0x09,0x0a,0x0c, ++0x10,0x11,0x04,0x04,0x04,0x05,0x04,0x04,0x05,0x07,0x07,0x07,0x08,0x0a,0x04,0x04, ++0x04,0x04,0x06,0x0a,0x0b,0x0d,0x05,0x05,0x07,0x07,0x08,0x0b,0x0d,0x0f,0x04,0x04, ++0x04,0x05,0x07,0x07,0x09,0x09,0x0c,0x0e,0x10,0x12,0x04,0x04,0x05,0x05,0x06,0x0a, ++0x11,0x13,0x09,0x09,0x09,0x09,0x0c,0x0e,0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x24,0x26,0x2a,0x18,0x1a,0x1d,0x1f,0x21,0x27,0x29,0x2a,0x00,0x00, ++0x00,0x1f,0x23,0x28,0x2a,0x2c,0x00,0x04,0x00,0x04,0x00,0x08,0x00,0x10,0x00,0x18, ++0x00,0x24,0x00,0x30,0x00,0x48,0x00,0x60,0x00,0x90,0x00,0xc0,0x00,0xd8,0x00,0x50, ++0x00,0x78,0x00,0xa0,0x00,0xc8,0x01,0x40,0x01,0x90,0x01,0xe0,0x02,0x30,0x01,0x2c, ++0x01,0x40,0x01,0xe0,0x02,0xd0,0x03,0xe8,0x04,0xb0,0x06,0x40,0x07,0xd0,0x00,0x02, ++0x00,0x02,0x00,0x04,0x00,0x08,0x00,0x0c,0x00,0x12,0x00,0x18,0x00,0x24,0x00,0x30, ++0x00,0x48,0x00,0x60,0x00,0x6c,0x00,0x28,0x00,0x3c,0x00,0x50,0x00,0x64,0x00,0xa0, ++0x00,0xc8,0x00,0xf0,0x01,0x18,0x00,0x64,0x00,0xa0,0x00,0xf0,0x01,0x68,0x01,0xf4, ++0x02,0x58,0x03,0x20,0x03,0xe8,0x02,0x02,0x02,0x02,0x02,0x02,0x03,0x03,0x04,0x04, ++0x05,0x07,0x04,0x04,0x07,0x0a,0x0a,0x0c,0x0c,0x12,0x05,0x07,0x07,0x08,0x0b,0x12, ++0x24,0x3c,0x01,0x01,0x01,0x01,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x01,0x02, ++0x03,0x04,0x05,0x06,0x07,0x08,0x05,0x06,0x07,0x08,0x09,0x0a,0x0b,0x0c,0x20,0x1e, ++0x1c,0x18,0x10,0x18,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0xbb,0x01,0x0c,0xe5,0x82,0x29,0xf5,0x82,0xe5,0x83,0x3a,0xf5,0x83,0xe0,0x22,0x50, ++0x06,0xe9,0x25,0x82,0xf8,0xe6,0x22,0xbb,0xfe,0x06,0xe9,0x25,0x82,0xf8,0xe2,0x22, ++0xe5,0x82,0x29,0xf5,0x82,0xe5,0x83,0x3a,0xf5,0x83,0xe4,0x93,0x22,0xbb,0x01,0x06, ++0x89,0x82,0x8a,0x83,0xf0,0x22,0x50,0x02,0xf7,0x22,0xbb,0xfe,0x01,0xf3,0x22,0xf8, ++0xbb,0x01,0x0d,0xe5,0x82,0x29,0xf5,0x82,0xe5,0x83,0x3a,0xf5,0x83,0xe8,0xf0,0x22, ++0x50,0x06,0xe9,0x25,0x82,0xc8,0xf6,0x22,0xbb,0xfe,0x05,0xe9,0x25,0x82,0xc8,0xf2, ++0x22,0xc5,0xf0,0xf8,0xa3,0xe0,0x28,0xf0,0xc5,0xf0,0xf8,0xe5,0x82,0x15,0x82,0x70, ++0x02,0x15,0x83,0xe0,0x38,0xf0,0x22,0xbb,0x01,0x0a,0x89,0x82,0x8a,0x83,0xe0,0xf5, ++0xf0,0xa3,0xe0,0x22,0x50,0x06,0x87,0xf0,0x09,0xe7,0x19,0x22,0xbb,0xfe,0x07,0xe3, ++0xf5,0xf0,0x09,0xe3,0x19,0x22,0x89,0x82,0x8a,0x83,0xe4,0x93,0xf5,0xf0,0x74,0x01, ++0x93,0x22,0xbb,0x01,0x10,0xe5,0x82,0x29,0xf5,0x82,0xe5,0x83,0x3a,0xf5,0x83,0xe0, ++0xf5,0xf0,0xa3,0xe0,0x22,0x50,0x09,0xe9,0x25,0x82,0xf8,0x86,0xf0,0x08,0xe6,0x22, ++0xbb,0xfe,0x0a,0xe9,0x25,0x82,0xf8,0xe2,0xf5,0xf0,0x08,0xe2,0x22,0xe5,0x83,0x2a, ++0xf5,0x83,0xe9,0x93,0xf5,0xf0,0xa3,0xe9,0x93,0x22,0xbb,0x01,0x0a,0x89,0x82,0x8a, ++0x83,0xf0,0xe5,0xf0,0xa3,0xf0,0x22,0x50,0x06,0xf7,0x09,0xa7,0xf0,0x19,0x22,0xbb, ++0xfe,0x06,0xf3,0xe5,0xf0,0x09,0xf3,0x19,0x22,0xf8,0xbb,0x01,0x11,0xe5,0x82,0x29, ++0xf5,0x82,0xe5,0x83,0x3a,0xf5,0x83,0xe8,0xf0,0xe5,0xf0,0xa3,0xf0,0x22,0x50,0x09, ++0xe9,0x25,0x82,0xc8,0xf6,0x08,0xa6,0xf0,0x22,0xbb,0xfe,0x09,0xe9,0x25,0x82,0xc8, ++0xf2,0xe5,0xf0,0x08,0xf2,0x22,0xef,0x4b,0xff,0xee,0x4a,0xfe,0xed,0x49,0xfd,0xec, ++0x48,0xfc,0x22,0xe0,0xfc,0xa3,0xe0,0xfd,0xa3,0xe0,0xfe,0xa3,0xe0,0xff,0x22,0xa4, ++0x25,0x82,0xf5,0x82,0xe5,0xf0,0x35,0x83,0xf5,0x83,0x22,0xe0,0xfb,0xa3,0xe0,0xfa, ++0xa3,0xe0,0xf9,0x22,0xf8,0xe0,0xfb,0xa3,0xa3,0xe0,0xf9,0x25,0xf0,0xf0,0xe5,0x82, ++0x15,0x82,0x70,0x02,0x15,0x83,0xe0,0xfa,0x38,0xf0,0x22,0xeb,0xf0,0xa3,0xea,0xf0, ++0xa3,0xe9,0xf0,0x22,0xd0,0x83,0xd0,0x82,0xf8,0xe4,0x93,0x70,0x12,0x74,0x01,0x93, ++0x70,0x0d,0xa3,0xa3,0x93,0xf8,0x74,0x01,0x93,0xf5,0x82,0x88,0x83,0xe4,0x73,0x74, ++0x02,0x93,0x68,0x60,0xef,0xa3,0xa3,0xa3,0x80,0xdf,0x02,0x43,0xf8,0x02,0x50,0x31, ++0xe4,0x93,0xa3,0xf8,0xe4,0x93,0xa3,0x40,0x03,0xf6,0x80,0x01,0xf2,0x08,0xdf,0xf4, ++0x80,0x29,0xe4,0x93,0xa3,0xf8,0x54,0x07,0x24,0x0c,0xc8,0xc3,0x33,0xc4,0x54,0x0f, ++0x44,0x20,0xc8,0x83,0x40,0x04,0xf4,0x56,0x80,0x01,0x46,0xf6,0xdf,0xe4,0x80,0x0b, ++0x01,0x02,0x04,0x08,0x10,0x20,0x40,0x80,0x90,0x44,0x3d,0xe4,0x7e,0x01,0x93,0x60, ++0xbc,0xa3,0xff,0x54,0x3f,0x30,0xe5,0x09,0x54,0x1f,0xfe,0xe4,0x93,0xa3,0x60,0x01, ++0x0e,0xcf,0x54,0xc0,0x25,0xe0,0x60,0xa8,0x40,0xb8,0xe4,0x93,0xa3,0xfa,0xe4,0x93, ++0xa3,0xf8,0xe4,0x93,0xa3,0xc8,0xc5,0x82,0xc8,0xca,0xc5,0x83,0xca,0xf0,0xa3,0xc8, ++0xc5,0x82,0xc8,0xca,0xc5,0x83,0xca,0xdf,0xe9,0xde,0xe7,0x80,0xbe,0x41,0x9e,0x66, ++0x00,0x41,0x9e,0xae,0x00,0x41,0x9e,0x4d,0x80,0x41,0x9e,0x4e,0x80,0x41,0x9e,0xb0, ++0x00,0x00,0xf0,0x90,0x9e,0x57,0xe0,0x90,0x9e,0x8a,0xf0,0xe4,0xfb,0xfd,0x7f,0x54, ++0x7e,0x01,0xd3,0x10,0xaf,0x01,0xc3,0xc0,0xd0,0x90,0x9e,0x88,0xeb,0xf0,0xa3,0xe0, ++0xfb,0xa3,0xe0,0xf5,0x44,0xe4,0xf5,0x45,0x12,0x35,0xab,0xd0,0xd0,0x92,0xaf,0x22, ++0x90,0x01,0x5f,0xe4,0xf0,0x90,0x01,0x3c,0x74,0x08,0xf0,0xe4,0x90,0x9e,0x89,0xf0, ++0x90,0x9e,0x55,0xe0,0x90,0x9e,0x8a,0xf0,0xe4,0xfb,0xfd,0x7f,0x5c,0x7e,0x01,0x91, ++0x62,0x90,0x01,0x5f,0x74,0x05,0xf0,0x90,0x06,0x92,0x74,0x02,0xf0,0x90,0x9e,0x5c, ++0x14,0xf0,0x90,0x9e,0x5e,0xe0,0x54,0x0f,0xc3,0x94,0x0c,0x50,0x02,0xf1,0x16,0x22, ++0x8f,0x82,0x8e,0x83,0xa3,0xa3,0xa3,0xe4,0xf0,0x22,0xe4,0xf5,0x22,0x7f,0x60,0x7e, ++0x01,0x80,0xed,0x90,0x9e,0x60,0xe0,0xff,0x7d,0x01,0xe1,0x1a,0xb1,0xb1,0xbf,0x01, ++0x0f,0x90,0x9e,0x68,0xe0,0xff,0xe4,0xfd,0xf1,0xfe,0x90,0x04,0x1f,0x74,0x20,0xf0, ++0x22,0x90,0x04,0x1b,0xe0,0x54,0x7f,0x64,0x7f,0x7f,0x01,0x60,0x02,0x7f,0x00,0x22, ++0x22,0x22,0x22,0x02,0x60,0x0d,0x02,0x60,0x14,0xd3,0x10,0xaf,0x01,0xc3,0xc0,0xd0, ++0x8b,0x1b,0x8a,0x1c,0x89,0x1d,0x90,0x9e,0x8b,0x71,0x8b,0xab,0x1e,0xaa,0x1f,0xa9, ++0x20,0x90,0x9e,0x8e,0x71,0x8b,0xaf,0x21,0x15,0x21,0xef,0x60,0x1b,0x90,0x9e,0x8e, ++0xe4,0x75,0xf0,0x01,0x71,0x74,0x12,0x29,0xd9,0xff,0x90,0x9e,0x8b,0xe4,0x75,0xf0, ++0x01,0x71,0x74,0xef,0x51,0x4d,0x80,0xde,0xab,0x1b,0xaa,0x1c,0xa9,0x1d,0xd0,0xd0, ++0x92,0xaf,0x22,0x90,0x06,0xa9,0xe0,0xf5,0x50,0x54,0xc0,0x70,0x0d,0x90,0x9e,0x63, ++0xe0,0x54,0xfe,0xf0,0xe0,0x54,0xfd,0xf0,0x91,0xd3,0xe5,0x50,0x30,0xe6,0x17,0x90, ++0x9e,0x63,0xe0,0x44,0x01,0xf0,0x90,0x9e,0x61,0xe0,0x64,0x02,0x60,0x04,0x91,0xdc, ++0x80,0x0b,0x91,0x80,0x80,0x07,0x90,0x9e,0x63,0xe0,0x54,0xfe,0xf0,0xe5,0x50,0x90, ++0x9e,0x63,0x30,0xe7,0x17,0xe0,0x44,0x02,0xf0,0xe4,0x90,0x9e,0x89,0x91,0x52,0x90, ++0x01,0x57,0x74,0x05,0xf0,0x90,0x9e,0x62,0x74,0x01,0xf0,0x22,0xe0,0x54,0xfd,0xf0, ++0x22,0xd3,0x10,0xaf,0x01,0xc3,0xc0,0xd0,0x90,0x04,0x1d,0xe0,0x60,0x1a,0x90,0x05, ++0x22,0xe0,0x54,0x90,0x60,0x07,0x90,0x01,0xc6,0xe0,0x44,0x40,0xf0,0x90,0x01,0xc7, ++0xe0,0x30,0xe1,0xe4,0x7f,0x00,0x80,0x02,0x7f,0x01,0xd0,0xd0,0x92,0xaf,0x22,0xc0, ++0xe0,0xc0,0xf0,0xc0,0x83,0xc0,0x82,0xc0,0xd0,0x75,0xd0,0x00,0xc0,0x00,0xc0,0x01, ++0xc0,0x02,0xc0,0x03,0xc0,0x04,0xc0,0x05,0xc0,0x06,0xc0,0x07,0x90,0x01,0xc4,0x74, ++0xdf,0xf0,0x74,0x45,0xa3,0xf0,0x53,0x91,0xdf,0x90,0x01,0x3c,0xe0,0x55,0x30,0xf5, ++0x34,0xa3,0xe0,0x55,0x31,0xf5,0x35,0xa3,0xe0,0x55,0x32,0xf5,0x36,0xa3,0xe0,0x55, ++0x33,0xf5,0x37,0xe5,0x34,0x30,0xe0,0x06,0x90,0x01,0x3c,0x74,0x01,0xf0,0xe5,0x34, ++0x30,0xe1,0x08,0x90,0x01,0x3c,0x74,0x02,0xf0,0xf1,0xbc,0xe5,0x34,0x30,0xe2,0x38, ++0x90,0x01,0x3c,0x74,0x04,0xf0,0x90,0x06,0x92,0xe0,0x30,0xe0,0x24,0x90,0x9e,0x89, ++0xe4,0xf0,0x90,0x9e,0x55,0xe0,0x90,0x9e,0x8a,0xf0,0xe4,0xfb,0xfd,0x7f,0x58,0x7e, ++0x01,0x91,0x62,0x90,0x01,0x5b,0x74,0x05,0xf0,0x90,0x06,0x92,0x74,0x01,0xf0,0x80, ++0x07,0x90,0x9e,0x5d,0xe4,0xf0,0x91,0xd3,0xe5,0x34,0x30,0xe3,0x38,0x90,0x01,0x3c, ++0x74,0x08,0xf0,0x90,0x06,0x92,0xe0,0x30,0xe1,0x24,0x90,0x9e,0x89,0xe4,0xf0,0x90, ++0x9e,0x55,0xe0,0x90,0x9e,0x8a,0xf0,0xe4,0xfb,0xfd,0x7f,0x5c,0x7e,0x01,0x91,0x62, ++0x90,0x01,0x5f,0x74,0x05,0xf0,0x90,0x06,0x92,0x74,0x02,0xf0,0x80,0x07,0x90,0x9e, ++0x5c,0xe4,0xf0,0x91,0xd3,0xe5,0x34,0x30,0xe4,0x09,0x90,0x01,0x3c,0x74,0x10,0xf0, ++0x12,0x71,0xa3,0xe5,0x34,0x30,0xe5,0x09,0x90,0x01,0x3c,0x74,0x20,0xf0,0x12,0x52, ++0x69,0xe5,0x35,0x30,0xe0,0x1a,0x90,0x01,0x3d,0x74,0x01,0xf0,0x90,0x01,0x2f,0xe0, ++0x44,0x7f,0xf0,0x90,0x00,0x83,0xe0,0x90,0x9e,0x60,0xf0,0x12,0x63,0xac,0x91,0xd3, ++0x74,0xdf,0x04,0x90,0x01,0xc4,0xf0,0x74,0x45,0xa3,0xf0,0xd0,0x07,0xd0,0x06,0xd0, ++0x05,0xd0,0x04,0xd0,0x03,0xd0,0x02,0xd0,0x01,0xd0,0x00,0xd0,0xd0,0xd0,0x82,0xd0, ++0x83,0xd0,0xf0,0xd0,0xe0,0x32,0x7d,0x01,0x7f,0x0c,0x8f,0x71,0x8d,0x72,0xe5,0x71, ++0x54,0x0f,0xff,0x90,0x9e,0x5e,0xe0,0x54,0x0f,0x6f,0x60,0x72,0xe5,0x71,0x30,0xe2, ++0x2b,0x90,0x9e,0x5e,0xe0,0x20,0xe2,0x05,0x7f,0x01,0x12,0x62,0xa7,0x90,0x9e,0x5e, ++0xe0,0x30,0xe3,0x07,0xe5,0x71,0x20,0xe3,0x02,0x80,0x54,0x90,0x9e,0x5e,0xe0,0x20, ++0xe3,0x4c,0xe5,0x71,0x30,0xe3,0x47,0xaf,0x72,0x02,0x62,0x43,0x90,0x9e,0x5e,0xe0, ++0x54,0x0f,0xff,0xbf,0x0c,0x0d,0xe5,0x71,0x20,0xe3,0x08,0x12,0x4c,0xd5,0xef,0x60, ++0x2d,0xf1,0x9f,0x90,0x9e,0x5e,0xe0,0x54,0x0f,0xff,0xbf,0x04,0x0e,0xe5,0x71,0x20, ++0xe2,0x09,0x12,0x5e,0x8f,0xef,0x60,0x16,0x12,0x48,0xaa,0x90,0x9e,0x5e,0xe0,0x54, ++0x0f,0xff,0xbf,0x02,0x09,0x12,0x61,0xd0,0xef,0x60,0x03,0x12,0x63,0x92,0x22,0x90, ++0x06,0x04,0xe0,0x44,0x40,0xf0,0xe5,0x73,0xb4,0x01,0x05,0x7f,0x01,0x12,0x62,0x62, ++0x90,0x9e,0x5e,0xe0,0x54,0xf0,0xf0,0xe0,0x44,0x04,0xf0,0x22,0x90,0x9e,0x62,0xe0, ++0x60,0x0e,0xe4,0xf0,0xa3,0xe0,0x54,0xfd,0xf0,0xe0,0x54,0x07,0x70,0x2b,0x80,0x27, ++0x90,0x9e,0x51,0xe0,0x04,0xf0,0x90,0x9e,0x63,0xe0,0x54,0xef,0xf0,0x90,0x9e,0x56, ++0xe0,0xff,0x90,0x9e,0x51,0xe0,0xd3,0x9f,0x40,0x0d,0xe5,0x73,0xb4,0x01,0x0a,0xa3, ++0xe0,0x70,0x06,0xe0,0x04,0xf0,0x22,0x91,0xd3,0x22,0xe0,0xff,0x7d,0x01,0x90,0x9e, ++0x9c,0xef,0xf0,0xa3,0xed,0xf0,0xe4,0xa3,0xf0,0xa3,0xf0,0xe5,0x74,0x60,0x04,0xe4, ++0xff,0x11,0x8f,0x90,0x9e,0x9c,0xe0,0x30,0xe0,0x09,0x90,0x9e,0x9e,0xe4,0xf0,0xa3, ++0x74,0x80,0xf0,0x90,0x9e,0x9c,0xe0,0xff,0xc3,0x13,0x90,0xfd,0x10,0xf0,0x90,0x04, ++0x25,0xef,0xf0,0x90,0x9e,0x9d,0xe0,0x60,0x1f,0xa3,0xa3,0xe0,0xff,0x24,0x0f,0xf5, ++0x82,0xe4,0x34,0xfc,0xf5,0x83,0xe0,0x44,0x80,0xf0,0x74,0x10,0x2f,0xf5,0x82,0xe4, ++0x34,0xfc,0xf5,0x83,0xe0,0x44,0x80,0xf0,0x90,0x9e,0x9e,0xa3,0xe0,0xff,0xfd,0x24, ++0x08,0xf5,0x82,0xe4,0x34,0xfc,0xf5,0x83,0xe4,0xf0,0x74,0x09,0x2d,0xf5,0x82,0xe4, ++0x34,0xfc,0xf5,0x83,0xe0,0x54,0xf0,0xf0,0x74,0x21,0x2f,0xf5,0x82,0xe4,0x34,0xfc, ++0xf5,0x83,0xe0,0x54,0xf7,0xf0,0x90,0x9e,0x9e,0xe0,0xfe,0xa3,0xe0,0xff,0x22,0xef, ++0x60,0x0b,0x90,0x9e,0x77,0xe0,0xb4,0x01,0x10,0xe4,0xff,0x80,0x09,0x90,0x9e,0x77, ++0xe0,0xb4,0x01,0x05,0x7f,0x01,0x12,0x77,0x2e,0x22,0x90,0x01,0x37,0x74,0x02,0xf0, ++0x90,0x05,0x22,0x74,0xff,0xf0,0x12,0x76,0x1a,0xef,0x70,0x06,0x90,0x01,0xc8,0x74, ++0xfd,0xf0,0x7d,0x02,0x7f,0x03,0x12,0x36,0xe6,0xe5,0x74,0x60,0x04,0x7f,0x01,0x11, ++0x8f,0x12,0x76,0x5b,0x90,0x9e,0x5e,0xe0,0x54,0xf0,0xf0,0xe0,0x44,0x02,0xf0,0x22, ++0x7d,0x02,0x7f,0x03,0x12,0x36,0x75,0xe5,0x74,0x14,0x24,0xfd,0x50,0x02,0x80,0x22, ++0x90,0x9e,0x61,0xe0,0x60,0x06,0x7d,0x01,0x7f,0x0c,0x80,0x0f,0x90,0x9e,0x5e,0xe0, ++0x54,0x0f,0xc3,0x94,0x04,0x50,0x07,0x7d,0x01,0x7f,0x04,0x12,0x47,0x1a,0xe4,0xff, ++0x11,0x8f,0x22,0xc0,0xe0,0xc0,0xf0,0xc0,0x83,0xc0,0x82,0xc0,0xd0,0x75,0xd0,0x00, ++0xc0,0x00,0xc0,0x01,0xc0,0x02,0xc0,0x03,0xc0,0x04,0xc0,0x05,0xc0,0x06,0xc0,0x07, ++0x90,0x01,0xc4,0x74,0x13,0xf0,0x74,0x49,0xa3,0xf0,0x90,0x01,0x34,0xe0,0x55,0x28, ++0xf5,0x2c,0x90,0x01,0x36,0xe0,0x55,0x2a,0xf5,0x2e,0xa3,0xe0,0x55,0x2b,0xf5,0x2f, ++0xe5,0x2c,0x20,0xe0,0x02,0x41,0xb3,0x90,0x01,0x34,0x74,0x01,0xf0,0x85,0xd1,0x08, ++0x85,0xd2,0x09,0x85,0xd3,0x0a,0x85,0xd4,0x0b,0x85,0xd5,0x0c,0x85,0xd6,0x0d,0x85, ++0xd7,0x0e,0x85,0xd9,0x0f,0xe5,0x0f,0x54,0x40,0xc3,0x13,0xff,0xe5,0x0e,0x54,0x20, ++0x6f,0x70,0x02,0x41,0x63,0xe5,0x0f,0x30,0xe5,0x02,0x41,0x63,0xe5,0x0d,0x54,0x3f, ++0xf5,0x4d,0xe5,0x08,0x54,0x3f,0xf5,0x4e,0xe5,0x0c,0x54,0x1f,0xff,0xe5,0x4d,0x25, ++0xe0,0x24,0xc4,0xf5,0x82,0xe4,0x34,0x99,0xf5,0x83,0xe4,0x8f,0xf0,0x12,0x42,0x81, ++0xe5,0x0e,0x54,0x1f,0xff,0xe5,0x4d,0x25,0xe0,0x24,0x80,0xf5,0x82,0xe4,0x34,0x93, ++0xf5,0x83,0xe4,0x8f,0xf0,0x12,0x42,0x81,0xe5,0x4e,0xd3,0x94,0x04,0x40,0x03,0x75, ++0x4e,0x04,0x75,0xf0,0x0a,0xe5,0x4d,0x90,0x90,0x00,0x12,0x43,0x5f,0x75,0xf0,0x02, ++0xe5,0x4e,0x12,0x43,0x5f,0xe0,0xfe,0xa3,0xe0,0xff,0xe5,0x0e,0x54,0x1f,0x2f,0xff, ++0xe4,0x3e,0xfe,0x75,0xf0,0x0a,0xe5,0x4d,0x90,0x90,0x00,0x12,0x43,0x5f,0x75,0xf0, ++0x02,0xe5,0x4e,0x12,0x43,0x5f,0xee,0xf0,0xa3,0xef,0xf0,0xe5,0x0f,0x20,0xe6,0x24, ++0xe5,0x0e,0x54,0x1f,0xff,0xe5,0x4d,0x25,0xe0,0x24,0xc4,0xf5,0x82,0xe4,0x34,0x98, ++0xf5,0x83,0xe4,0x8f,0xf0,0x12,0x42,0x81,0xe5,0x0a,0x30,0xe7,0x36,0xaf,0x4d,0x12, ++0x5b,0x6d,0x80,0x2f,0xe5,0x0e,0x54,0x1f,0xff,0xe5,0x4d,0x25,0xe0,0x24,0x44,0xf5, ++0x82,0xe4,0x34,0x99,0xf5,0x83,0xe4,0x8f,0xf0,0x12,0x42,0x81,0xe5,0x0a,0x30,0xe7, ++0x12,0xe5,0x0a,0x54,0x7f,0xfd,0xe5,0x0e,0x54,0x1f,0xf5,0x53,0xab,0x4e,0xaf,0x4d, ++0x12,0x5b,0x0a,0xe5,0x74,0x14,0x24,0xfd,0x50,0x02,0x80,0x47,0x90,0x9e,0x61,0xe0, ++0x60,0x38,0x90,0x01,0x5b,0xe4,0xf0,0x90,0x01,0x3c,0x74,0x04,0xf0,0x12,0x44,0xf1, ++0xef,0x64,0x01,0x70,0x2e,0x90,0x9e,0x55,0xe0,0xf5,0x44,0x75,0x45,0x00,0xe4,0xfb, ++0xfd,0x7f,0x58,0x7e,0x01,0x12,0x35,0xab,0x90,0x01,0x5b,0x74,0x05,0xf0,0x90,0x06, ++0x92,0x74,0x01,0xf0,0x90,0x9e,0x5d,0xf0,0x80,0x09,0x12,0x44,0xf1,0xbf,0x01,0x03, ++0x12,0x44,0xd3,0xe5,0x2c,0x30,0xe1,0x21,0x90,0x01,0x34,0x74,0x02,0xf0,0x85,0xd1, ++0x13,0x85,0xd2,0x14,0x85,0xd3,0x15,0x85,0xd4,0x16,0x85,0xd5,0x17,0x85,0xd6,0x18, ++0x85,0xd7,0x19,0x85,0xd9,0x1a,0x12,0x5c,0x61,0xe5,0x2c,0x30,0xe3,0x06,0x90,0x01, ++0x34,0x74,0x08,0xf0,0xe5,0x2c,0x30,0xe4,0x09,0x90,0x01,0x34,0x74,0x10,0xf0,0x43, ++0x12,0x10,0xe5,0x2c,0x30,0xe5,0x24,0x90,0x01,0xcf,0xe0,0x30,0xe5,0x1d,0xe0,0x54, ++0xdf,0xf0,0x90,0x01,0x34,0x74,0x20,0xf0,0x75,0xa8,0x00,0x75,0xe8,0x00,0xd1,0xed, ++0x90,0x00,0x03,0xe0,0x54,0xfb,0xf0,0xb1,0x28,0x80,0xfe,0xe5,0x2c,0x30,0xe6,0x06, ++0x90,0x01,0x34,0x74,0x40,0xf0,0xe5,0x2e,0x30,0xe1,0x3b,0x90,0x01,0x36,0x74,0x02, ++0xf0,0x43,0x12,0x40,0x90,0x01,0x02,0xe0,0x54,0x03,0x64,0x01,0x70,0x28,0x90,0x01, ++0x37,0xe0,0x30,0xe0,0x0a,0x74,0x01,0xf0,0x90,0x9e,0x66,0xe4,0xf0,0x80,0x17,0x90, ++0x9e,0x66,0xe0,0x04,0xf0,0xe0,0xc3,0x94,0x0a,0x40,0x0b,0xe4,0xf0,0x90,0x04,0x19, ++0xe0,0x30,0xe0,0x02,0xf1,0xfc,0xe5,0x2e,0x30,0xe0,0x12,0x90,0x9e,0x76,0x74,0x01, ++0xf0,0x90,0x01,0x36,0xf0,0x12,0x64,0x09,0x90,0x9e,0x76,0xe4,0xf0,0xe5,0x2e,0x30, ++0xe2,0x78,0x90,0x01,0x36,0x74,0x04,0xf0,0x90,0x01,0xbd,0xe0,0x04,0xf0,0xe5,0x73, ++0x64,0x01,0x70,0x66,0xe5,0x74,0x60,0x62,0xe5,0x74,0x64,0x02,0x60,0x06,0xe5,0x74, ++0x64,0x05,0x70,0x27,0x90,0x06,0xab,0xe0,0x90,0x9e,0x50,0xf0,0x90,0x06,0xaa,0xe0, ++0x90,0x9e,0x5f,0xf0,0x90,0x9e,0x50,0xe0,0x70,0x07,0x90,0x9e,0x5f,0xe0,0xff,0x80, ++0x05,0x90,0x9e,0x50,0xe0,0xff,0x90,0x9e,0x50,0xef,0xf0,0x90,0x9e,0x52,0xe0,0x60, ++0x03,0xe0,0x14,0xf0,0x90,0x9e,0x51,0xe4,0xf0,0x90,0x01,0x57,0xf0,0x90,0x01,0x3c, ++0x74,0x02,0xf0,0x90,0x9e,0x63,0xe0,0x54,0xfd,0xf0,0xe0,0x54,0xef,0xf0,0xe5,0x74, ++0x14,0x24,0xfd,0x50,0x02,0x80,0x03,0x12,0x45,0x53,0xe5,0x2e,0x30,0xe3,0x28,0x90, ++0x01,0x36,0x74,0x08,0xf0,0xe5,0x73,0x64,0x01,0x70,0x1c,0xe5,0x74,0x60,0x18,0x90, ++0x01,0x57,0xe4,0xf0,0x90,0x01,0x3c,0x74,0x02,0xf0,0x90,0x9e,0x89,0xe4,0x12,0x44, ++0x52,0x90,0x01,0x57,0x74,0x05,0xf0,0xe5,0x2e,0x30,0xe4,0x2f,0x90,0x01,0x36,0x74, ++0x10,0xf0,0xe5,0x73,0x64,0x01,0x70,0x23,0xe5,0x74,0x60,0x1f,0x90,0x01,0x57,0xe4, ++0xf0,0x90,0x01,0x3c,0x74,0x02,0xf0,0x90,0x9e,0x62,0xe4,0xf0,0x90,0x9e,0x63,0xe0, ++0x54,0xfd,0xf0,0xe0,0x54,0x07,0x70,0x03,0x12,0x44,0xd3,0xe5,0x2e,0x30,0xe5,0x1f, ++0x90,0x01,0x36,0x74,0x20,0xf0,0xe5,0x73,0xb4,0x01,0x14,0xe5,0x74,0x60,0x10,0x90, ++0x9e,0x61,0xe0,0x64,0x02,0x60,0x05,0x12,0x44,0xdc,0x80,0x03,0x12,0x44,0x80,0xe5, ++0x2e,0x30,0xe6,0x1e,0x90,0x01,0x36,0x74,0x40,0xf0,0xe5,0x73,0xb4,0x01,0x13,0xe5, ++0x74,0x60,0x0f,0x90,0x9e,0x63,0xe0,0x54,0xfe,0xf0,0xe0,0x54,0x07,0x70,0x03,0x12, ++0x44,0xd3,0xe5,0x2f,0x30,0xe1,0x08,0x90,0x01,0x37,0x74,0x02,0xf0,0x11,0xe0,0x74, ++0x13,0x04,0x90,0x01,0xc4,0xf0,0x74,0x49,0xa3,0xf0,0xd0,0x07,0xd0,0x06,0xd0,0x05, ++0xd0,0x04,0xd0,0x03,0xd0,0x02,0xd0,0x01,0xd0,0x00,0xd0,0xd0,0xd0,0x82,0xd0,0x83, ++0xd0,0xf0,0xd0,0xe0,0x32,0x12,0x44,0xf1,0xef,0x64,0x01,0x60,0x08,0x90,0x01,0xb9, ++0x74,0x01,0xf0,0x80,0x32,0x90,0x9e,0x5d,0xe0,0x60,0x08,0x90,0x01,0xb9,0x74,0x02, ++0xf0,0x80,0x24,0x90,0x9e,0x5c,0xe0,0x60,0x08,0x90,0x01,0xb9,0x74,0x04,0xf0,0x80, ++0x16,0x90,0x9e,0x60,0xe0,0x54,0x0f,0xd3,0x94,0x04,0x40,0x08,0x90,0x01,0xb9,0x74, ++0x08,0xf0,0x80,0x03,0x7f,0x01,0x22,0x90,0x01,0xb8,0x74,0x08,0xf0,0x7f,0x00,0x22, ++0xf4,0xff,0x90,0x00,0x43,0xe0,0x5f,0xf0,0xd3,0x10,0xaf,0x01,0xc3,0xc0,0xd0,0x7f, ++0x10,0xdf,0xfe,0xd0,0xd0,0x92,0xaf,0x22,0xd3,0x10,0xaf,0x01,0xc3,0xc0,0xd0,0x90, ++0x9e,0xad,0xed,0xf0,0x90,0x9e,0xac,0xef,0xf0,0xd3,0x94,0x07,0x50,0x63,0xe0,0xff, ++0x74,0x01,0xa8,0x07,0x08,0x80,0x02,0xc3,0x33,0xd8,0xfc,0xf4,0xff,0x90,0x00,0x47, ++0xe0,0x5f,0xf0,0xb1,0x28,0x90,0x9e,0xac,0xe0,0xff,0x74,0x01,0xa8,0x07,0x08,0x80, ++0x02,0xc3,0x33,0xd8,0xfc,0xff,0x90,0x00,0x46,0xe0,0x4f,0xf0,0xb1,0x28,0x90,0x9e, ++0xad,0xe0,0x60,0x16,0x90,0x9e,0xac,0xe0,0xff,0x74,0x01,0xa8,0x07,0x08,0x80,0x02, ++0xc3,0x33,0xd8,0xfc,0xff,0x90,0x00,0x45,0x80,0x66,0x90,0x9e,0xac,0xe0,0xff,0x74, ++0x01,0xa8,0x07,0x08,0x80,0x02,0xc3,0x33,0xd8,0xfc,0xf4,0xff,0x90,0x00,0x45,0x80, ++0x6b,0x90,0x9e,0xac,0xe0,0x24,0xf8,0xf0,0xe0,0xff,0x74,0x01,0xa8,0x07,0x08,0x80, ++0x02,0xc3,0x33,0xd8,0xfc,0xc4,0x54,0xf0,0xb1,0x20,0x90,0x9e,0xac,0xe0,0xff,0x74, ++0x01,0xa8,0x07,0x08,0x80,0x02,0xc3,0x33,0xd8,0xfc,0xff,0x90,0x00,0x43,0xe0,0x4f, ++0xf0,0xb1,0x28,0x90,0x9e,0xad,0xe0,0x60,0x1b,0x90,0x9e,0xac,0xe0,0xff,0x74,0x01, ++0xa8,0x07,0x08,0x80,0x02,0xc3,0x33,0xd8,0xfc,0xc4,0x54,0xf0,0xff,0x90,0x00,0x42, ++0xe0,0x4f,0x80,0x1a,0x90,0x9e,0xac,0xe0,0xff,0x74,0x01,0xa8,0x07,0x08,0x80,0x02, ++0xc3,0x33,0xd8,0xfc,0xc4,0x54,0xf0,0xf4,0xff,0x90,0x00,0x42,0xe0,0x5f,0xf0,0xb1, ++0x28,0xd0,0xd0,0x92,0xaf,0x22,0xf0,0x90,0x00,0x45,0xe0,0x54,0xfe,0xfd,0x7f,0x45, ++0xd3,0x10,0xaf,0x01,0xc3,0xc0,0xd0,0x8f,0x82,0x75,0x83,0x00,0xed,0xf0,0xb1,0x28, ++0xd0,0xd0,0x92,0xaf,0x22,0xef,0x14,0x60,0x30,0x14,0x60,0x66,0x24,0x02,0x60,0x02, ++0xc1,0xec,0x90,0x9e,0x1a,0x74,0x02,0xf0,0x90,0x00,0x48,0xe0,0x44,0x0c,0xfd,0x7f, ++0x48,0xd1,0x30,0x90,0x00,0x47,0xe0,0x44,0x08,0xfd,0x7f,0x47,0xd1,0x30,0x90,0x00, ++0x45,0xe0,0x44,0x10,0xfd,0x7f,0x45,0x80,0x71,0xe4,0x90,0x9e,0x1a,0xf0,0x90,0x9e, ++0x16,0x12,0x43,0x53,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0x80,0x7e,0x08,0x12,0x2f, ++0xd9,0x90,0x00,0x45,0xe0,0x44,0xef,0xfd,0x7f,0x45,0xd1,0x30,0x90,0x00,0x45,0xe0, ++0x54,0xef,0xfd,0x7f,0x45,0xd1,0x30,0x90,0x00,0x46,0xe0,0x44,0x10,0xfd,0x7f,0x46, ++0x80,0x38,0x90,0x9e,0x1a,0x74,0x01,0xf0,0x90,0x9e,0x20,0x12,0x43,0x53,0x90,0x80, ++0x85,0x12,0x2a,0x7f,0x7f,0x80,0x7e,0x08,0x12,0x2f,0xd9,0x90,0x00,0x45,0xe0,0x44, ++0x20,0xfd,0x7f,0x45,0xd1,0x30,0x90,0x00,0x45,0xe0,0x44,0x10,0xfd,0x7f,0x45,0xd1, ++0x30,0x90,0x00,0x46,0xe0,0x44,0x10,0xfd,0x7f,0x46,0xd1,0x30,0x22,0x90,0x01,0x30, ++0xe4,0xf0,0xa3,0xf0,0xa3,0xf0,0xa3,0xf0,0x90,0x01,0x38,0xf0,0xa3,0xf0,0xa3,0xf0, ++0xa3,0xf0,0xfd,0x7f,0x50,0xd1,0x30,0xe4,0xfd,0x7f,0x51,0xd1,0x30,0xe4,0xfd,0x7f, ++0x52,0xd1,0x30,0xe4,0xfd,0x7f,0x53,0xc1,0x30,0x8b,0x59,0x8a,0x5a,0x89,0x5b,0x90, ++0x00,0x02,0x12,0x42,0x20,0x90,0x9e,0x1d,0xf0,0xe0,0x30,0xe0,0x4b,0x90,0x9e,0x14, ++0x74,0x01,0xf0,0x7f,0x80,0x7e,0x08,0x12,0x27,0xde,0x90,0x9e,0x16,0x12,0x2a,0x7f, ++0xab,0x59,0xaa,0x5a,0xa9,0x5b,0x90,0x00,0x01,0x12,0x42,0x20,0xff,0xe4,0xfc,0xfd, ++0xfe,0x78,0x1a,0x12,0x2a,0x6c,0xa8,0x04,0xa9,0x05,0xaa,0x06,0xab,0x07,0x90,0x9e, ++0x16,0x12,0x43,0x53,0xec,0x54,0x03,0xfc,0x12,0x43,0x46,0x90,0x9e,0x20,0x12,0x2a, ++0x7f,0x90,0x05,0x22,0xe4,0xf0,0x80,0x2d,0xe4,0x90,0x9e,0x14,0xf0,0x7f,0x80,0x7e, ++0x08,0x12,0x27,0xde,0xec,0x54,0x03,0xfc,0xec,0x44,0xc0,0xfc,0x90,0x9e,0x16,0x12, ++0x2a,0x7f,0x90,0x9e,0x16,0x12,0x43,0x53,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0x80, ++0x7e,0x08,0x12,0x2f,0xd9,0x90,0x9e,0x1d,0xe0,0x30,0xe1,0x19,0x7d,0x0c,0x7f,0x47, ++0xd1,0x30,0x90,0x00,0x48,0xe0,0x44,0x0c,0xfd,0x7f,0x48,0xd1,0x30,0x90,0x00,0x46, ++0xe0,0x44,0x10,0x80,0x1c,0x90,0x00,0x47,0xe0,0x54,0xf3,0xfd,0x7f,0x47,0xd1,0x30, ++0x90,0x00,0x48,0xe0,0x54,0xf3,0xfd,0x7f,0x48,0xd1,0x30,0x90,0x00,0x46,0xe0,0x54, ++0xef,0xfd,0x7f,0x46,0xd1,0x30,0xe4,0x90,0x9e,0x1a,0xf0,0x22,0xe4,0x90,0x9e,0x74, ++0xf0,0x90,0x00,0x80,0xe0,0x44,0x80,0xfd,0x7f,0x80,0xc1,0x30,0x12,0x45,0xb1,0xbf, ++0x01,0x10,0x90,0x02,0x09,0xe0,0xff,0x7d,0x01,0x12,0x47,0xfe,0x90,0x04,0x1f,0x74, ++0x20,0xf0,0x22,0x75,0x28,0x33,0xe4,0xf5,0x29,0x75,0x2a,0x03,0xf5,0x2b,0x90,0x01, ++0x30,0xe5,0x28,0xf0,0xa3,0xe5,0x29,0xf0,0xa3,0xe5,0x2a,0xf0,0xa3,0xe5,0x2b,0xf0, ++0x22,0xe4,0x90,0x9e,0x31,0xf0,0xa3,0xf0,0x75,0x8e,0x02,0x12,0x4f,0xec,0x12,0x5f, ++0x29,0x12,0x5f,0x3c,0xe4,0xf5,0x12,0x12,0x6d,0x11,0x12,0x77,0x25,0x12,0x60,0x1b, ++0x12,0x32,0x3d,0x12,0x76,0x16,0x11,0x13,0x90,0x00,0xf3,0xe0,0x30,0xe2,0x0d,0x90, ++0x05,0x41,0x74,0x10,0xf0,0x90,0x05,0x5a,0xf0,0xa3,0xe4,0xf0,0x12,0x5f,0x74,0x12, ++0x5e,0x77,0x12,0x45,0x00,0x12,0x7c,0xe5,0x90,0x9e,0x33,0xe5,0xd9,0xf0,0x12,0x5e, ++0xfa,0xc2,0xaf,0x90,0x00,0x80,0xe0,0x44,0x40,0xf0,0x12,0x4d,0x28,0x75,0xe8,0x03, ++0x43,0xa8,0x85,0xd2,0xaf,0x90,0x01,0xbe,0xe0,0x04,0xf0,0x90,0x01,0xc0,0xe0,0x04, ++0xf0,0x90,0x9e,0x31,0xe0,0x64,0x01,0xf0,0x24,0x31,0x90,0x01,0xc4,0xf0,0x74,0x50, ++0xa3,0xf0,0xe5,0x12,0x30,0xe4,0x09,0xc2,0xaf,0x53,0x12,0xef,0xd2,0xaf,0x71,0x1f, ++0xe5,0x12,0x30,0xe6,0x16,0xc2,0xaf,0x53,0x12,0xbf,0xd2,0xaf,0x12,0x66,0xbc,0x90, ++0x9e,0x1e,0xe0,0xff,0x60,0x03,0xb4,0x01,0x02,0x31,0x15,0x90,0x9e,0x1e,0xe0,0x70, ++0x03,0x12,0x7d,0x43,0x11,0xe8,0x80,0xb9,0x90,0x06,0x34,0xe0,0x60,0x26,0x14,0x70, ++0x1b,0x7b,0x01,0x7a,0x06,0x79,0x35,0x7f,0xf9,0x7e,0x01,0x12,0x75,0xb4,0xbf,0x01, ++0x09,0x90,0x06,0x35,0xe0,0x54,0x0f,0xf0,0x80,0x05,0x80,0x00,0x02,0x75,0xa5,0xe4, ++0x90,0x06,0x34,0xf0,0x22,0x90,0x9e,0x15,0xe0,0xc3,0x94,0x14,0x50,0x05,0xe0,0x04, ++0xf0,0x21,0xcd,0x90,0x9e,0x15,0xe0,0x64,0x14,0x60,0x02,0x21,0xcd,0x90,0x9e,0x24, ++0xe0,0x70,0x25,0x90,0x9e,0x27,0xe0,0x70,0x1f,0x90,0x9e,0x25,0xe0,0x70,0x19,0x90, ++0x9e,0x28,0xe0,0x70,0x13,0x90,0x9e,0x26,0xe0,0x70,0x0d,0x90,0x9e,0x29,0xe0,0x70, ++0x07,0x90,0x04,0xfd,0xe0,0x54,0xfe,0xf0,0x90,0x9e,0x24,0xe0,0x90,0x04,0x44,0xf0, ++0x90,0x9e,0x25,0xe0,0x90,0x04,0x45,0xf0,0x90,0x9e,0x26,0xe0,0x90,0x04,0x46,0xf0, ++0xa3,0xe4,0xf0,0x90,0x9e,0x27,0xe0,0x90,0x04,0x48,0xf0,0x90,0x9e,0x28,0xe0,0x90, ++0x04,0x49,0xf0,0x90,0x9e,0x29,0xe0,0x90,0x04,0x4a,0xf0,0xa3,0xe4,0xf0,0x90,0x9e, ++0x10,0xe0,0x90,0x04,0x4c,0xf0,0x90,0x9e,0x11,0xe0,0x90,0x04,0x4d,0xf0,0x90,0x9e, ++0x12,0xe0,0x90,0x04,0x4e,0xf0,0x90,0x9e,0x13,0xe0,0x90,0x04,0x4f,0xf0,0xe4,0x90, ++0x9e,0x15,0xf0,0x90,0x9e,0x10,0x04,0xf0,0xe4,0xa3,0xf0,0xa3,0xf0,0xa3,0xf0,0x90, ++0x9e,0x24,0xf0,0xa3,0xf0,0xa3,0xf0,0xa3,0xf0,0xa3,0xf0,0xa3,0xf0,0x90,0x05,0x60, ++0xe0,0x90,0x9e,0x34,0xf0,0x90,0x05,0x61,0xe0,0x90,0x9e,0x35,0xf0,0x90,0x05,0x62, ++0xe0,0x90,0x9e,0x36,0xf0,0x90,0x05,0x63,0xe0,0x90,0x9e,0x37,0xf0,0x90,0x9e,0x2d, ++0xe0,0xff,0x90,0x9e,0x37,0xe0,0xfe,0xd3,0x9f,0x50,0x0b,0x90,0x9e,0x2d,0xe0,0xc3, ++0x9e,0xd3,0x94,0x01,0x40,0x10,0x90,0x9e,0x1b,0xe0,0xb4,0x01,0x02,0x80,0x03,0x90, ++0x9e,0x1f,0xe0,0xff,0x51,0x17,0x22,0x90,0x05,0x60,0xe0,0x90,0x9e,0x2a,0xf0,0x90, ++0x05,0x61,0xe0,0x90,0x9e,0x2b,0xf0,0x90,0x05,0x62,0xe0,0x90,0x9e,0x2c,0xf0,0x90, ++0x05,0x63,0xe0,0x90,0x9e,0x2d,0xf0,0xc3,0x74,0xff,0x9f,0xfe,0x90,0x9e,0x2b,0xe0, ++0xd3,0x9e,0x40,0x1e,0xe0,0x2f,0xf0,0xa3,0xe0,0xb4,0xff,0x0f,0xe4,0xf0,0xa3,0xe0, ++0xb4,0xff,0x03,0xe4,0xf0,0x22,0x90,0x9e,0x2d,0x80,0x03,0x90,0x9e,0x2c,0xe0,0x04, ++0xf0,0x22,0x90,0x9e,0x2b,0xe0,0x2f,0xf0,0x22,0x90,0x9e,0x1c,0xe0,0x64,0x01,0x60, ++0x02,0x61,0x1e,0x90,0x00,0x46,0xe0,0x44,0x01,0xfd,0x7f,0x46,0x12,0x4e,0x30,0x90, ++0x9e,0x2e,0xe0,0x70,0x32,0x90,0x9e,0x14,0xe0,0x60,0x15,0x90,0x9e,0x20,0x12,0x43, ++0x53,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0x80,0x7e,0x08,0x12,0x2f,0xd9,0x80,0x06, ++0x90,0x05,0x22,0x74,0x7f,0xf0,0x90,0x9e,0x1b,0xe0,0xff,0x51,0x17,0x90,0x9e,0x2e, ++0x74,0x01,0x12,0x4e,0x26,0x80,0x40,0x90,0x9e,0x2e,0xe0,0x64,0x01,0x70,0x38,0x90, ++0x9e,0x1f,0xe0,0xff,0x51,0x17,0xe4,0x90,0x9e,0x2e,0xf0,0x90,0x00,0x45,0xe0,0x44, ++0x01,0xfd,0x7f,0x45,0x12,0x4e,0x30,0x90,0x9e,0x14,0xe0,0x60,0x15,0x90,0x9e,0x16, ++0x12,0x43,0x53,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0x80,0x7e,0x08,0x12,0x2f,0xd9, ++0x80,0x05,0x90,0x05,0x22,0xe4,0xf0,0x90,0x05,0x87,0xe0,0x64,0x80,0xf0,0x90,0x9e, ++0x2a,0xe0,0x90,0x05,0x84,0xf0,0x90,0x9e,0x2b,0xe0,0x90,0x05,0x85,0xf0,0x90,0x9e, ++0x2c,0xe0,0x90,0x05,0x86,0xf0,0x90,0x9e,0x2d,0xe0,0x90,0x05,0x87,0xf0,0x22,0x90, ++0x01,0xcc,0xe0,0x54,0x0f,0x90,0x9e,0x34,0xf0,0x90,0x9e,0x34,0xe0,0xfd,0x70,0x02, ++0x81,0x60,0x90,0x9e,0xae,0xe0,0xff,0x74,0x01,0x7e,0x00,0xa8,0x07,0x08,0x80,0x05, ++0xc3,0x33,0xce,0x33,0xce,0xd8,0xf9,0xff,0xef,0x5d,0x70,0x02,0x81,0x59,0x90,0x9e, ++0xae,0xe0,0x75,0xf0,0x04,0x90,0x01,0xd0,0x12,0x43,0x5f,0xe0,0x90,0x9e,0x35,0xf0, ++0x75,0x1e,0x01,0x75,0x1f,0x9e,0x75,0x20,0x35,0x75,0x21,0x01,0x7b,0x01,0x7a,0x9e, ++0x79,0x36,0x12,0x45,0x09,0x90,0x9e,0x36,0xe0,0xff,0xc4,0x13,0x13,0x13,0x54,0x01, ++0x90,0x9e,0xae,0x30,0xe0,0x59,0xe0,0x75,0xf0,0x02,0x90,0x00,0x88,0x12,0x43,0x5f, ++0xe0,0x90,0x9e,0x37,0xf0,0x90,0x9e,0xae,0xe0,0x75,0xf0,0x02,0x90,0x00,0x89,0x12, ++0x43,0x5f,0xe0,0x90,0x9e,0x38,0xf0,0x90,0x9e,0xae,0xe0,0x75,0xf0,0x04,0x90,0x01, ++0xd1,0x12,0x43,0x5f,0xe0,0x90,0x9e,0x39,0xf0,0x90,0x9e,0xae,0xe0,0x75,0xf0,0x04, ++0x90,0x01,0xd2,0x12,0x43,0x5f,0xe0,0x90,0x9e,0x3a,0xf0,0x90,0x9e,0xae,0xe0,0x75, ++0xf0,0x04,0x90,0x01,0xd3,0x12,0x43,0x5f,0xe0,0x90,0x9e,0x3b,0xf0,0x80,0x33,0xe0, ++0x75,0xf0,0x04,0x90,0x01,0xd1,0x12,0x43,0x5f,0xe0,0x90,0x9e,0x37,0xf0,0x90,0x9e, ++0xae,0xe0,0x75,0xf0,0x04,0x90,0x01,0xd2,0x12,0x43,0x5f,0xe0,0x90,0x9e,0x38,0xf0, ++0x90,0x9e,0xae,0xe0,0x75,0xf0,0x04,0x90,0x01,0xd3,0x12,0x43,0x5f,0xe0,0x90,0x9e, ++0x39,0xf0,0xef,0x54,0x7f,0xff,0x7b,0x01,0x7a,0x9e,0x79,0x37,0x91,0x61,0x90,0x9e, ++0x34,0xe0,0xff,0x90,0x9e,0xae,0xe0,0xfe,0x74,0x01,0xa8,0x06,0x08,0x80,0x02,0xc3, ++0x33,0xd8,0xfc,0xf4,0x5f,0x90,0x9e,0x34,0xf0,0x90,0x9e,0xae,0xe0,0xff,0x74,0x01, ++0xa8,0x07,0x08,0x80,0x02,0xc3,0x33,0xd8,0xfc,0x90,0x01,0xcc,0xf0,0x90,0x9e,0xae, ++0xe0,0x04,0xf0,0xe0,0x54,0x03,0xf0,0x61,0x29,0x90,0x01,0xc6,0xe0,0x44,0x02,0xf0, ++0x22,0x90,0x9e,0x3c,0x12,0x43,0x8b,0xef,0x12,0x43,0x94,0x54,0x9c,0x01,0x54,0xa5, ++0x02,0x54,0xc0,0x03,0x54,0xc9,0x05,0x54,0xd2,0x06,0x55,0x20,0x07,0x54,0xda,0x09, ++0x54,0xe3,0x0c,0x54,0xec,0x0d,0x54,0xf5,0x0e,0x54,0xfe,0x1b,0x55,0x07,0x1c,0x55, ++0x10,0x2c,0x54,0xae,0x2d,0x54,0xb7,0x2e,0x00,0x00,0x55,0x19,0x90,0x9e,0x3c,0x12, ++0x43,0x6b,0x02,0x61,0x1d,0x90,0x9e,0x3c,0x12,0x43,0x6b,0x02,0x6f,0x33,0x90,0x9e, ++0x3c,0x12,0x43,0x6b,0x02,0x6f,0x39,0x90,0x9e,0x3c,0x12,0x43,0x6b,0x02,0x6f,0x81, ++0x90,0x9e,0x3c,0x12,0x43,0x6b,0x02,0x6f,0xaf,0x90,0x9e,0x3c,0x12,0x43,0x6b,0x02, ++0x6e,0xe3,0x90,0x9e,0x3c,0x12,0x43,0x6b,0x80,0x47,0x90,0x9e,0x3c,0x12,0x43,0x6b, ++0x02,0x6f,0xf7,0x90,0x9e,0x3c,0x12,0x43,0x6b,0x02,0x7e,0x1b,0x90,0x9e,0x3c,0x12, ++0x43,0x6b,0x02,0x7c,0xb2,0x90,0x9e,0x3c,0x12,0x43,0x6b,0x02,0x4f,0x19,0x90,0x9e, ++0x3c,0x12,0x43,0x6b,0x02,0x6f,0x2b,0x90,0x9e,0x3c,0x12,0x43,0x6b,0x02,0x6f,0x12, ++0x90,0x9e,0x3c,0x12,0x43,0x6b,0x02,0x74,0x85,0x90,0x01,0xc6,0xe0,0x44,0x01,0xf0, ++0x22,0x90,0x00,0x04,0x12,0x42,0x20,0xff,0x54,0x1f,0xfe,0xef,0x54,0x20,0xc4,0x13, ++0x54,0x07,0xfd,0xaf,0x06,0x90,0x9e,0x3f,0xef,0xf0,0xa3,0xed,0xf0,0xa3,0x12,0x43, ++0x8b,0x90,0x9e,0x41,0x12,0x43,0x6b,0x90,0x00,0x03,0x12,0x42,0x20,0x54,0xf0,0xc4, ++0x54,0x0f,0x90,0x9e,0x44,0xf0,0x90,0x00,0x04,0x12,0x42,0x20,0x54,0x40,0xc4,0x13, ++0x13,0x54,0x03,0x90,0x9e,0x45,0xf0,0x90,0x9e,0x3f,0xe0,0xff,0x75,0xf0,0x09,0x90, ++0x96,0x46,0x12,0x43,0x5f,0xad,0x82,0xac,0x83,0x90,0x9e,0x46,0xec,0xf0,0xa3,0xed, ++0xf0,0xef,0x75,0xf0,0x09,0xa4,0x24,0x44,0xf9,0x74,0x96,0x35,0xf0,0xfa,0x7b,0x01, ++0xa3,0x12,0x43,0x8b,0x90,0x9e,0x41,0x12,0x43,0x6b,0x90,0x00,0x03,0x12,0x42,0x20, ++0x54,0x0f,0xff,0x90,0x9e,0x48,0x12,0x43,0x6b,0xef,0x12,0x42,0x4d,0x90,0x9e,0x41, ++0x12,0x43,0x6b,0x90,0x00,0x02,0x12,0x42,0x20,0xff,0x90,0x9e,0x48,0x12,0x43,0x6b, ++0x90,0x00,0x01,0xef,0x12,0x42,0x5f,0x90,0x9e,0x41,0x12,0x43,0x6b,0x90,0x00,0x01, ++0x12,0x42,0x20,0xff,0x90,0x9e,0x46,0xe0,0xfc,0xa3,0xe0,0xfd,0xf5,0x82,0x8c,0x83, ++0xef,0xf0,0x12,0x29,0xd9,0x8d,0x82,0x8c,0x83,0xa3,0xf0,0x90,0x9e,0x44,0xe0,0xfe, ++0x90,0x9e,0x3f,0xe0,0xff,0x24,0x82,0xf5,0x82,0xe4,0x34,0x95,0xf5,0x83,0xee,0xf0, ++0x90,0x9e,0x40,0xe0,0xfe,0x75,0xf0,0x09,0xef,0x90,0x96,0x4a,0x12,0x43,0x5f,0xee, ++0xf0,0x75,0xf0,0x09,0xef,0x90,0x96,0x4b,0x12,0x43,0x5f,0x74,0x01,0xf0,0x90,0x9e, ++0x45,0xe0,0xfe,0x75,0xf0,0x09,0xef,0x90,0x96,0x4c,0x12,0x43,0x5f,0xee,0xf0,0x8f, ++0x59,0xef,0x25,0xe0,0x24,0xc6,0xf5,0x82,0xe4,0x34,0x9b,0xaf,0x82,0xf5,0x5b,0x8f, ++0x5c,0xe5,0x59,0x75,0xf0,0x02,0xa4,0x24,0x02,0xf9,0x74,0x95,0x35,0xf0,0x75,0x5d, ++0x01,0xf5,0x5e,0x89,0x5f,0x75,0xf0,0x09,0xe5,0x59,0x90,0x96,0x46,0x12,0x43,0x5f, ++0xaf,0x82,0x85,0x83,0x60,0x8f,0x61,0xe5,0x59,0x75,0xf0,0x09,0xa4,0x24,0x44,0xf9, ++0x74,0x96,0x35,0xf0,0x75,0x62,0x01,0xf5,0x63,0x89,0x64,0x74,0x82,0x25,0x59,0xf5, ++0x82,0xe4,0x34,0x95,0xf5,0x83,0xe0,0x12,0x43,0x94,0x56,0xaf,0x00,0x56,0xc4,0x01, ++0x56,0xd9,0x02,0x56,0xee,0x03,0x57,0x18,0x04,0x57,0x2d,0x05,0x57,0x42,0x06,0x57, ++0x69,0x0c,0x57,0x97,0x0d,0x57,0xc4,0x0e,0x57,0xf1,0x0f,0x00,0x00,0x58,0x25,0xe5, ++0x59,0x25,0xe0,0x24,0xc6,0xf5,0x82,0xe4,0x34,0x9b,0xf5,0x83,0x74,0xf0,0xf0,0xa3, ++0x74,0x15,0x80,0x3c,0xe5,0x59,0x25,0xe0,0x24,0xc6,0xf5,0x82,0xe4,0x34,0x9b,0xf5, ++0x83,0x74,0xf0,0xf0,0xa3,0x74,0x10,0x80,0x27,0xe5,0x59,0x25,0xe0,0x24,0xc6,0xf5, ++0x82,0xe4,0x34,0x9b,0xf5,0x83,0x74,0xf0,0xf0,0xa3,0x74,0x05,0x80,0x12,0xe5,0x59, ++0x25,0xe0,0x24,0xc6,0xf5,0x82,0xe4,0x34,0x9b,0xf5,0x83,0x74,0xf0,0xf0,0xa3,0xe4, ++0xf0,0xe5,0x59,0x25,0xe0,0x24,0x02,0xf5,0x82,0xe4,0x34,0x95,0xf5,0x83,0x74,0x0f, ++0xf0,0xa3,0x74,0x8f,0xf0,0x02,0x58,0x25,0xe5,0x59,0x25,0xe0,0x24,0xc6,0xf5,0x82, ++0xe4,0x34,0x9b,0xf5,0x83,0x74,0x0f,0xf0,0xa3,0x74,0xf5,0x80,0x27,0xe5,0x59,0x25, ++0xe0,0x24,0xc6,0xf5,0x82,0xe4,0x34,0x9b,0xf5,0x83,0x74,0x0f,0xf0,0xa3,0x74,0xf0, ++0x80,0x12,0xe5,0x59,0x25,0xe0,0x24,0xc6,0xf5,0x82,0xe4,0x34,0x9b,0xf5,0x83,0xe4, ++0xf0,0xa3,0x74,0x0d,0xf0,0xe5,0x59,0x25,0xe0,0x24,0x02,0xf5,0x82,0xe4,0x34,0x95, ++0xf5,0x83,0xe4,0xf0,0xa3,0xf0,0x02,0x58,0x25,0x90,0x04,0x47,0xe0,0xab,0x5d,0xaa, ++0x5e,0xa9,0x5f,0x12,0x42,0x4d,0x90,0x04,0x46,0xe0,0xab,0x5d,0xaa,0x5e,0xa9,0x5f, ++0x90,0x00,0x01,0x12,0x42,0x5f,0x90,0x04,0x45,0xe0,0x85,0x5c,0x82,0x85,0x5b,0x83, ++0xf0,0x90,0x04,0x44,0x02,0x58,0x1c,0x90,0x04,0x4b,0xe0,0xab,0x5d,0xaa,0x5e,0xa9, ++0x5f,0x12,0x42,0x4d,0x90,0x04,0x4a,0xe0,0xab,0x5d,0xaa,0x5e,0xa9,0x5f,0x90,0x00, ++0x01,0x12,0x42,0x5f,0x90,0x04,0x49,0xe0,0x85,0x5c,0x82,0x85,0x5b,0x83,0xf0,0x90, ++0x04,0x48,0x80,0x58,0x90,0x04,0x4f,0xe0,0xab,0x5d,0xaa,0x5e,0xa9,0x5f,0x12,0x42, ++0x4d,0x90,0x04,0x4e,0xe0,0xab,0x5d,0xaa,0x5e,0xa9,0x5f,0x90,0x00,0x01,0x12,0x42, ++0x5f,0x90,0x04,0x4d,0xe0,0x85,0x5c,0x82,0x85,0x5b,0x83,0xf0,0x90,0x04,0x4c,0x80, ++0x2b,0x90,0x04,0x53,0xe0,0xab,0x5d,0xaa,0x5e,0xa9,0x5f,0x12,0x42,0x4d,0x90,0x04, ++0x52,0xe0,0xab,0x5d,0xaa,0x5e,0xa9,0x5f,0x90,0x00,0x01,0x12,0x42,0x5f,0x90,0x04, ++0x51,0xe0,0x85,0x5c,0x82,0x85,0x5b,0x83,0xf0,0x90,0x04,0x50,0xe0,0x85,0x5c,0x82, ++0x85,0x5b,0x83,0xa3,0xf0,0xab,0x5d,0xaa,0x5e,0xa9,0x5f,0xc0,0x03,0xc0,0x02,0xc0, ++0x01,0x12,0x29,0xd9,0xff,0xab,0x62,0xaa,0x63,0xa9,0x64,0x12,0x29,0xd9,0x5f,0xd0, ++0x01,0xd0,0x02,0xd0,0x03,0x12,0x42,0x4d,0xab,0x5d,0xe5,0x5f,0x24,0x01,0xf9,0xe4, ++0x35,0x5e,0xfa,0xc0,0x03,0xc0,0x02,0xc0,0x01,0x12,0x29,0xd9,0xff,0xab,0x62,0xaa, ++0x63,0xa9,0x64,0x90,0x00,0x01,0x12,0x42,0x20,0x5f,0xd0,0x01,0xd0,0x02,0xd0,0x03, ++0x12,0x42,0x4d,0x85,0x5c,0x82,0x85,0x5b,0x83,0xc0,0x83,0xc0,0x82,0xe0,0xff,0x85, ++0x61,0x82,0x85,0x60,0x83,0xe0,0xfe,0xef,0x5e,0xd0,0x82,0xd0,0x83,0xf0,0x85,0x5c, ++0x82,0x85,0x5b,0x83,0xa3,0xc0,0x83,0xc0,0x82,0xe0,0xff,0x85,0x61,0x82,0x85,0x60, ++0x83,0xa3,0xe0,0xfe,0xef,0x5e,0xd0,0x82,0xd0,0x83,0xf0,0xe5,0x59,0x25,0xe0,0x24, ++0x02,0xf5,0x82,0xe4,0x34,0x95,0xf5,0x83,0xe0,0xfe,0xa3,0xe0,0x4e,0x60,0x3b,0x75, ++0x5a,0x0b,0x74,0x01,0x7e,0x00,0xa8,0x5a,0x08,0x80,0x05,0xc3,0x33,0xce,0x33,0xce, ++0xd8,0xf9,0xff,0xe5,0x59,0x25,0xe0,0x24,0x02,0xf5,0x82,0xe4,0x34,0x95,0xf5,0x83, ++0xe0,0x5e,0xfe,0xa3,0xe0,0x5f,0x4e,0x60,0x06,0xe5,0x5a,0x24,0x10,0x80,0x5d,0x15, ++0x5a,0xe5,0x5a,0xc3,0x94,0x00,0x50,0xca,0x80,0x56,0xe5,0x59,0x25,0xe0,0x24,0xc6, ++0xf5,0x82,0xe4,0x34,0x9b,0xf5,0x83,0xe0,0xfe,0xa3,0xe0,0x4e,0x60,0x3d,0x75,0x5a, ++0x0f,0x74,0x01,0x7e,0x00,0xa8,0x5a,0x08,0x80,0x05,0xc3,0x33,0xce,0x33,0xce,0xd8, ++0xf9,0xff,0xe5,0x59,0x25,0xe0,0x24,0xc6,0xf5,0x82,0xe4,0x34,0x9b,0xf5,0x83,0xe0, ++0x5e,0xfe,0xa3,0xe0,0x5f,0x4e,0x60,0x08,0x90,0x9e,0x4b,0xe5,0x5a,0xf0,0x80,0x10, ++0x15,0x5a,0xe5,0x5a,0xc3,0x94,0x00,0x50,0xc8,0x80,0x05,0xe4,0x90,0x9e,0x4b,0xf0, ++0xe5,0x59,0x25,0xe0,0x24,0xc6,0xf5,0x82,0xe4,0x34,0x9b,0xf5,0x83,0xe0,0xfe,0xa3, ++0xe0,0x4e,0x60,0x3b,0xe4,0xf5,0x5a,0x74,0x01,0x7e,0x00,0xa8,0x5a,0x08,0x80,0x05, ++0xc3,0x33,0xce,0x33,0xce,0xd8,0xf9,0xff,0xe5,0x59,0x25,0xe0,0x24,0xc6,0xf5,0x82, ++0xe4,0x34,0x9b,0xf5,0x83,0xe0,0x5e,0xfe,0xa3,0xe0,0x5f,0x4e,0x60,0x08,0x90,0x9e, ++0x4c,0xe5,0x5a,0xf0,0x80,0x5b,0x05,0x5a,0xe5,0x5a,0xb4,0x10,0xca,0x80,0x52,0xe5, ++0x59,0x25,0xe0,0x24,0x02,0xf5,0x82,0xe4,0x34,0x95,0xf5,0x83,0xe0,0xfe,0xa3,0xe0, ++0x4e,0x60,0x39,0xe4,0xf5,0x5a,0x74,0x01,0x7e,0x00,0xa8,0x5a,0x08,0x80,0x05,0xc3, ++0x33,0xce,0x33,0xce,0xd8,0xf9,0xff,0xe5,0x59,0x25,0xe0,0x24,0x02,0xf5,0x82,0xe4, ++0x34,0x95,0xf5,0x83,0xe0,0x5e,0xfe,0xa3,0xe0,0x5f,0x4e,0x60,0x06,0xe5,0x5a,0x24, ++0x10,0x80,0x0a,0x05,0x5a,0xe5,0x5a,0xb4,0x0c,0xcc,0x80,0x05,0xe4,0x90,0x9e,0x4c, ++0xf0,0x90,0x9e,0x4b,0xe0,0xff,0x75,0xf0,0x09,0xe5,0x59,0x90,0x96,0x48,0x12,0x43, ++0x5f,0xef,0xf0,0x90,0x9e,0x4c,0xe0,0xfe,0x75,0xf0,0x09,0xe5,0x59,0x90,0x96,0x49, ++0x12,0x43,0x5f,0xee,0xf0,0x74,0x84,0x25,0x59,0xf5,0x82,0xe4,0x34,0x04,0xf5,0x83, ++0xe0,0xd3,0x9f,0x40,0x05,0x90,0x9e,0x4b,0x51,0x74,0x74,0x84,0x25,0x59,0xf5,0x82, ++0xe4,0x34,0x04,0xf5,0x83,0xe0,0xff,0x90,0x9e,0x4c,0xe0,0xfe,0xef,0xc3,0x9e,0x50, ++0x02,0x51,0x74,0x90,0x9e,0x4b,0xe0,0xff,0xd3,0x94,0x13,0x40,0x07,0x90,0x96,0x43, ++0x74,0x03,0xf0,0x22,0xef,0xd3,0x94,0x0b,0x40,0x07,0x90,0x96,0x43,0x74,0x02,0xf0, ++0x22,0xef,0xd3,0x94,0x03,0x40,0x07,0x90,0x96,0x43,0x74,0x01,0xf0,0x22,0xe4,0x90, ++0x96,0x43,0xf0,0x22,0xe0,0xfd,0x74,0x26,0x25,0x59,0xf5,0x82,0xe4,0x34,0x9d,0xf5, ++0x83,0xed,0xf0,0xaf,0x59,0xd3,0x10,0xaf,0x01,0xc3,0xc0,0xd0,0xef,0xc3,0x94,0x20, ++0x50,0x0e,0x74,0x84,0x2f,0xf5,0x82,0xe4,0x34,0x04,0xf5,0x83,0xed,0xf0,0x80,0x29, ++0x74,0xa6,0x2f,0xf5,0x82,0xe4,0x34,0x9c,0xf5,0x83,0xed,0xf0,0x90,0x9e,0x78,0xef, ++0xf0,0x24,0xa6,0xf5,0x82,0xe4,0x34,0x9c,0xf5,0x83,0xe0,0x90,0x9e,0x79,0xf0,0x7b, ++0x01,0x7a,0x9e,0x79,0x78,0x7d,0x02,0x51,0xce,0xd0,0xd0,0x92,0xaf,0x22,0xd3,0x10, ++0xaf,0x01,0xc3,0xc0,0xd0,0x90,0x9e,0x97,0x12,0x43,0x8b,0x90,0x9e,0x9a,0xe0,0x54, ++0xf0,0x44,0x06,0xff,0xf0,0xed,0x54,0x0f,0xc4,0x54,0xf0,0xfe,0xef,0x54,0x0f,0x4e, ++0xf0,0x90,0x9e,0x97,0x12,0x43,0x6b,0x90,0x9e,0x94,0x12,0x43,0x8b,0x7b,0x01,0x7a, ++0x9e,0x79,0x9a,0x71,0xd9,0xd0,0xd0,0x92,0xaf,0x22,0x8f,0x50,0x8d,0x51,0xe5,0x51, ++0x54,0x1f,0xf5,0x56,0x74,0x01,0x2f,0xf5,0x82,0xe4,0x34,0x94,0xf5,0x83,0xe0,0xf5, ++0x54,0x90,0x04,0xfd,0xe0,0xb4,0x01,0x05,0x75,0x57,0x03,0x80,0x03,0x75,0x57,0x01, ++0xeb,0xc3,0x95,0x57,0x40,0x04,0xaf,0x50,0x80,0x33,0xe5,0x54,0x25,0x53,0xf5,0x55, ++0xe5,0x56,0x90,0x41,0xd6,0x93,0xff,0xe5,0x55,0xd3,0x9f,0x74,0x01,0x40,0x11,0x25, ++0x50,0xf5,0x82,0xe4,0x34,0x94,0xf5,0x83,0xe4,0xf0,0xad,0x51,0xaf,0x50,0x41,0x85, ++0x25,0x50,0xf5,0x82,0xe4,0x34,0x94,0xf5,0x83,0xe5,0x55,0xf0,0x22,0xad,0x07,0x75, ++0xf0,0x09,0xed,0x90,0x96,0x48,0x12,0x43,0x5f,0xe0,0xff,0x74,0x67,0x2d,0xf5,0x82, ++0xe4,0x34,0x9d,0xf5,0x83,0xe0,0x54,0x1f,0xf5,0x58,0xd3,0x9f,0x40,0x02,0x8f,0x58, ++0xe5,0x58,0x25,0xe0,0x24,0x9e,0xf5,0x82,0xe4,0x34,0x41,0xf5,0x83,0xe4,0x93,0xfe, ++0x74,0x01,0x93,0xff,0xe5,0x58,0x25,0xe0,0x24,0x66,0xf5,0x82,0xe4,0x34,0x41,0xf5, ++0x83,0x74,0x01,0x93,0x2f,0xff,0xe4,0x93,0x3e,0xc3,0x13,0xfe,0xef,0x13,0xff,0xed, ++0x25,0xe0,0x24,0xc2,0xf5,0x82,0xe4,0x34,0x95,0xf5,0x83,0xee,0xf0,0xa3,0xef,0xf0, ++0xaf,0x05,0xad,0x58,0x51,0x85,0xaf,0x58,0x22,0xd3,0x10,0xaf,0x01,0xc3,0xc0,0xd0, ++0x90,0x9e,0x91,0x12,0x43,0x8b,0x90,0x9e,0x75,0xe0,0x64,0x02,0x60,0x6e,0x90,0x9e, ++0x75,0xe0,0x64,0x01,0x70,0x66,0x90,0x9e,0xb0,0xe0,0xff,0x04,0xf0,0x90,0x9e,0x91, ++0x12,0x43,0x6b,0x90,0x00,0x01,0xef,0x12,0x42,0x5f,0x7f,0xaf,0x7e,0x01,0x91,0x82, ++0xef,0x60,0x49,0x90,0x9e,0x91,0x12,0x43,0x6b,0x8b,0x1e,0x8a,0x1f,0x89,0x20,0x75, ++0x21,0x02,0x7b,0x01,0x7a,0x01,0x79,0xa0,0x12,0x45,0x09,0x90,0x9e,0x94,0x12,0x43, ++0x6b,0x8b,0x1e,0x8a,0x1f,0x89,0x20,0x90,0x9e,0x91,0x12,0x43,0x6b,0x12,0x29,0xd9, ++0xff,0xc4,0x54,0x0f,0xf5,0x21,0x7b,0x01,0x7a,0x01,0x79,0xa2,0x12,0x45,0x09,0x90, ++0x01,0xaf,0x74,0xff,0xf0,0x90,0x01,0xcb,0xe0,0x64,0x80,0xf0,0xd0,0xd0,0x92,0xaf, ++0x22,0x90,0x9e,0x2f,0xe0,0x54,0xf0,0x44,0x03,0xf0,0x54,0x0f,0x44,0x80,0xf0,0x7b, ++0x00,0x7a,0x00,0x79,0x13,0x90,0x9e,0x94,0x12,0x43,0x8b,0x0b,0x7a,0x9e,0x79,0x2f, ++0x61,0xd9,0xd3,0x10,0xaf,0x01,0xc3,0xc0,0xd0,0x90,0x9e,0xa0,0xee,0xf0,0xa3,0xef, ++0xf0,0xe4,0xa3,0xf0,0xa3,0xf0,0x90,0x9e,0xa0,0xe0,0xfe,0xa3,0xe0,0xf5,0x82,0x8e, ++0x83,0xe0,0x60,0x2d,0xc3,0x90,0x9e,0xa3,0xe0,0x94,0xe8,0x90,0x9e,0xa2,0xe0,0x94, ++0x03,0x40,0x0b,0x90,0x01,0xc6,0xe0,0x44,0x10,0xf0,0x7f,0x00,0x80,0x15,0x90,0x9e, ++0xa2,0xe4,0x75,0xf0,0x01,0x12,0x42,0x81,0x7f,0x0a,0x7e,0x00,0x12,0x37,0x54,0x80, ++0xc5,0x7f,0x01,0xd0,0xd0,0x92,0xaf,0x22,0xac,0x07,0xec,0xc3,0x94,0x20,0x50,0x0d, ++0x74,0x84,0x2c,0xf5,0x82,0xe4,0x34,0x04,0xf5,0x83,0xe0,0x80,0x0b,0x74,0xa6,0x2c, ++0xf5,0x82,0xe4,0x34,0x9c,0xf5,0x83,0xe0,0x54,0x7f,0xf5,0x64,0xe5,0x64,0x54,0x1f, ++0xff,0x90,0x9e,0x40,0xf0,0x75,0xf0,0x09,0xec,0x90,0x96,0x49,0x12,0x43,0x5f,0xe0, ++0x90,0x9e,0x42,0xf0,0x75,0xf0,0x09,0xec,0x90,0x96,0x48,0x12,0x43,0x5f,0xe0,0xfe, ++0x90,0x9e,0x43,0xf0,0xec,0x25,0xe0,0x24,0xc6,0xf5,0x82,0xe4,0x34,0x9b,0xf5,0x83, ++0xe0,0xfb,0xa3,0xe0,0x90,0x9e,0x44,0xcb,0xf0,0xa3,0xeb,0xf0,0xec,0x25,0xe0,0x24, ++0x02,0xf5,0x82,0xe4,0x34,0x95,0xf5,0x83,0xe0,0xfb,0xa3,0xe0,0x90,0x9e,0x46,0xcb, ++0xf0,0xa3,0xeb,0xf0,0xef,0xd3,0x9e,0x40,0x0a,0x90,0x9e,0x43,0xe0,0x90,0x9e,0x40, ++0xf0,0xf5,0x64,0xed,0x70,0x02,0xc1,0x2e,0x90,0x9e,0x41,0xed,0xf0,0xe5,0x64,0x30, ++0xe6,0x0a,0x90,0x9e,0x40,0xe0,0xf5,0x64,0xa3,0xe0,0x14,0xf0,0x90,0x9e,0x41,0xe0, ++0x70,0x02,0xc1,0x2e,0x90,0x9e,0x40,0xe0,0xff,0xd3,0x94,0x00,0x50,0x02,0xc1,0x2e, ++0xe4,0x90,0x9e,0x3f,0xf0,0xef,0x14,0x90,0x9e,0x3e,0xf0,0x90,0x9e,0x42,0xe0,0xfd, ++0x90,0x9e,0x3e,0xe0,0xff,0xd3,0x9d,0x40,0x6b,0xef,0x94,0x10,0x40,0x21,0xef,0x24, ++0xf0,0xff,0x74,0x01,0x7e,0x00,0xa8,0x07,0x08,0x80,0x05,0xc3,0x33,0xce,0x33,0xce, ++0xd8,0xf9,0xff,0x90,0x9e,0x46,0xe0,0x5e,0xfe,0xa3,0xe0,0x5f,0x4e,0x70,0x27,0x90, ++0x9e,0x3e,0xe0,0xff,0xc3,0x94,0x10,0x50,0x33,0x74,0x01,0x7e,0x00,0xa8,0x07,0x08, ++0x80,0x05,0xc3,0x33,0xce,0x33,0xce,0xd8,0xf9,0xff,0x90,0x9e,0x44,0xe0,0x5e,0xfe, ++0xa3,0xe0,0x5f,0x4e,0x60,0x16,0x90,0x9e,0x3e,0xe0,0xf5,0x64,0xa3,0xe0,0x04,0xf0, ++0x90,0x9e,0x41,0xe0,0xff,0x90,0x9e,0x3f,0xe0,0x6f,0x60,0x08,0x90,0x9e,0x3e,0xe0, ++0x14,0xf0,0x80,0x87,0x90,0x9e,0x41,0xe0,0xff,0x90,0x9e,0x3f,0xe0,0xc3,0x9f,0x50, ++0x0d,0x90,0x9e,0x3e,0xe0,0xb5,0x05,0x06,0x90,0x9e,0x42,0xe0,0xf5,0x64,0xe5,0x64, ++0x25,0xe0,0x24,0x9e,0xf5,0x82,0xe4,0x34,0x41,0xf5,0x83,0xe4,0x93,0xfe,0x74,0x01, ++0x93,0xff,0xe5,0x64,0x25,0xe0,0x24,0x66,0xf5,0x82,0xe4,0x34,0x41,0xf5,0x83,0x74, ++0x01,0x93,0x2f,0xff,0xe4,0x93,0x3e,0xc3,0x13,0xfe,0xef,0x13,0xff,0xec,0x25,0xe0, ++0x24,0xc2,0xf5,0x82,0xe4,0x34,0x95,0xf5,0x83,0xee,0xf0,0xa3,0xef,0xf0,0xaf,0x04, ++0xad,0x64,0x51,0x85,0xaf,0x64,0x22,0x75,0x30,0x1f,0x75,0x31,0x01,0xe4,0xf5,0x32, ++0x90,0x01,0x38,0xe5,0x30,0xf0,0xa3,0xe5,0x31,0xf0,0xa3,0xe5,0x32,0xf0,0x22,0x12, ++0x44,0xf1,0xef,0x64,0x01,0x60,0x08,0x90,0x01,0xb9,0x74,0x01,0xf0,0x80,0x52,0x90, ++0x9e,0x63,0xe0,0x54,0x03,0x60,0x08,0x90,0x01,0xb9,0x74,0x02,0xf0,0x80,0x42,0x90, ++0x9e,0x60,0xe0,0x54,0x0f,0xd3,0x94,0x02,0x40,0x08,0x90,0x01,0xb9,0x74,0x04,0xf0, ++0x80,0x2f,0x90,0x9e,0x63,0xe0,0x30,0xe2,0x08,0x90,0x01,0xb9,0x74,0x08,0xf0,0x80, ++0x20,0x90,0x9e,0x63,0xe0,0x30,0xe4,0x08,0x90,0x01,0xb9,0x74,0x10,0xf0,0x80,0x11, ++0x90,0x9e,0x52,0xe0,0x60,0x08,0x90,0x01,0xb9,0x74,0x20,0xf0,0x80,0x03,0x7f,0x01, ++0x22,0x90,0x01,0xb8,0x74,0x04,0xf0,0x7f,0x00,0x22,0x90,0x01,0x3c,0x74,0xff,0xf0, ++0xa3,0xf0,0xa3,0xf0,0x90,0x01,0x34,0xf0,0xa3,0xf0,0xa3,0xf0,0xa3,0xf0,0xfd,0x7f, ++0x54,0x12,0x4e,0x30,0x7d,0xff,0x7f,0x55,0x12,0x4e,0x30,0x7d,0xff,0x7f,0x56,0x12, ++0x4e,0x30,0x7d,0xff,0x7f,0x57,0x02,0x4e,0x30,0x90,0x00,0x02,0xe0,0x54,0xe0,0x90, ++0x9e,0x75,0x60,0x04,0x74,0x01,0xf0,0x22,0x74,0x02,0xf0,0x22,0x90,0x00,0xf3,0xe0, ++0x30,0xe3,0x08,0x90,0x9e,0x77,0x74,0x01,0xf0,0x80,0x05,0xe4,0x90,0x9e,0x77,0xf0, ++0x90,0x9e,0x77,0xe0,0xb4,0x01,0x12,0x90,0x00,0xf2,0xe0,0x30,0xe7,0x0b,0x90,0x9e, ++0x64,0x74,0xfd,0xf0,0xa3,0x74,0x33,0xf0,0x22,0x90,0x9e,0x64,0x74,0xfd,0xf0,0xa3, ++0x74,0x2f,0xf0,0x22,0x90,0x01,0x64,0x74,0xa0,0xf0,0x22,0xc0,0xe0,0xc0,0xf0,0xc0, ++0x83,0xc0,0x82,0xc0,0xd0,0x75,0xd0,0x00,0xc0,0x00,0xc0,0x01,0xc0,0x02,0xc0,0x03, ++0xc0,0x04,0xc0,0x05,0xc0,0x06,0xc0,0x07,0x90,0x01,0xc4,0x74,0x7b,0xf0,0x74,0x5f, ++0xa3,0xf0,0x53,0x91,0xef,0x90,0x00,0x51,0xe0,0xff,0x90,0x00,0x55,0xe0,0x5f,0xf5, ++0x3d,0xe5,0x3d,0x30,0xe6,0x18,0x74,0x40,0xf0,0x90,0x9e,0x1d,0xe0,0x54,0x03,0xff, ++0xbf,0x03,0x0b,0x90,0x9e,0x1a,0xe0,0x60,0x05,0x7f,0x01,0x12,0x4e,0x45,0xe5,0x3d, ++0x30,0xe7,0x15,0x90,0x00,0x55,0x74,0x80,0xf0,0x90,0x9e,0x1d,0xe0,0x54,0x03,0xff, ++0xbf,0x03,0x05,0x7f,0x02,0x12,0x4e,0x45,0x90,0x01,0xc4,0x74,0x7b,0xf0,0x74,0x5f, ++0xa3,0xf0,0xd0,0x07,0xd0,0x06,0xd0,0x05,0xd0,0x04,0xd0,0x03,0xd0,0x02,0xd0,0x01, ++0xd0,0x00,0xd0,0xd0,0xd0,0x82,0xd0,0x83,0xd0,0xf0,0xd0,0xe0,0x32,0x8f,0x6b,0x8c, ++0x6c,0x8d,0x6d,0x22,0x8f,0x6e,0x8c,0x6f,0x8d,0x70,0x22,0xe4,0xf5,0x73,0x90,0x9e, ++0x63,0xf0,0xf5,0x74,0x90,0x9e,0x60,0x74,0x0c,0xf0,0x90,0x9e,0x5e,0xf0,0xe4,0x90, ++0x9e,0x61,0xf0,0x90,0x9e,0x5d,0xf0,0x90,0x9e,0x5c,0xf0,0x90,0x9e,0x5f,0x04,0xf0, ++0x90,0x9e,0x50,0xf0,0xe4,0x90,0x9e,0x62,0xf0,0x90,0x9e,0x52,0xf0,0x90,0x9e,0x5a, ++0x74,0x07,0xf0,0xe4,0x90,0x9e,0x51,0xf0,0x90,0x9e,0x58,0xf0,0xa3,0x74,0x02,0xf0, ++0x90,0x9e,0x56,0x14,0xf0,0xa3,0x74,0x03,0xf0,0x90,0x9e,0x55,0x74,0x14,0xf0,0x90, ++0x9e,0x5b,0x74,0x05,0xf0,0xe4,0x90,0x9e,0x54,0xf0,0x90,0x9e,0x4f,0xf0,0x90,0x9e, ++0x76,0xf0,0x22,0xe4,0x90,0x9e,0x62,0xf0,0x90,0x9e,0x51,0xf0,0x90,0x9e,0x63,0xf0, ++0x22,0x8b,0x59,0x8a,0x5a,0x89,0x5b,0x11,0x83,0xab,0x59,0xaa,0x5a,0xa9,0x5b,0x12, ++0x29,0xd9,0xf5,0x74,0x14,0x60,0x0e,0x14,0x60,0x1e,0x14,0x60,0x2f,0x24,0x03,0x70, ++0x40,0x7f,0x01,0x80,0x3a,0xab,0x59,0xaa,0x5a,0xa9,0x5b,0x90,0x00,0x02,0x12,0x42, ++0x20,0xfd,0xe4,0xff,0x11,0xf2,0x80,0x27,0xab,0x59,0xaa,0x5a,0xa9,0x5b,0x90,0x00, ++0x02,0x12,0x42,0x20,0xfd,0x7f,0x01,0x11,0xf2,0x1f,0x80,0x13,0xab,0x59,0xaa,0x5a, ++0xa9,0x5b,0x90,0x00,0x02,0x12,0x42,0x20,0xfd,0x7f,0x02,0x11,0xf2,0xe4,0xff,0x31, ++0x46,0x22,0xef,0x24,0xfe,0x60,0x0b,0x04,0x70,0x22,0x90,0x9e,0x5f,0x74,0x01,0xf0, ++0x80,0x16,0xed,0x70,0x0a,0x90,0x9e,0x5b,0xe0,0x90,0x9e,0x5f,0xf0,0x80,0x05,0x90, ++0x9e,0x5f,0xed,0xf0,0x90,0x9e,0x5f,0xe0,0x90,0x9e,0x50,0xf0,0x22,0xd3,0x10,0xaf, ++0x01,0xc3,0xc0,0xd0,0x90,0x00,0x01,0x12,0x42,0x20,0x90,0x9e,0x61,0xf0,0x90,0x00, ++0x03,0x12,0x42,0x20,0x90,0x9e,0x4f,0xf0,0x12,0x29,0xd9,0x65,0x74,0x60,0x02,0x11, ++0x91,0xd0,0xd0,0x92,0xaf,0x22,0xef,0x64,0x01,0x70,0x30,0x7d,0x7c,0x7f,0x02,0x12, ++0x36,0x75,0x7d,0x02,0x7f,0x03,0x12,0x36,0x75,0x90,0x01,0x57,0xe4,0xf0,0x90,0x01, ++0x3c,0x74,0x02,0xf0,0x12,0x47,0x16,0xe4,0xff,0x12,0x48,0x8f,0x90,0x06,0x04,0xe0, ++0x54,0x7f,0xf0,0x90,0x06,0x0a,0xe0,0x54,0xf8,0xf0,0x22,0x90,0x01,0x36,0x74,0x7c, ++0xf0,0xa3,0x74,0x02,0xf0,0x7d,0x7c,0xff,0x12,0x36,0xe6,0x7d,0x02,0x7f,0x03,0x12, ++0x36,0xe6,0x90,0x06,0x04,0xe0,0x44,0x80,0xf0,0x90,0x06,0x0a,0xe0,0x44,0x07,0xf0, ++0x90,0x9e,0x58,0xe0,0xa3,0xe0,0x90,0x05,0x58,0xf0,0xe5,0x73,0x30,0xe0,0x1b,0x90, ++0x9e,0x52,0xe0,0x70,0x1a,0xe0,0x04,0xf0,0x90,0x9e,0x5e,0xe0,0x54,0x0f,0xc3,0x94, ++0x04,0x50,0x0c,0x7d,0x01,0x7f,0x04,0x02,0x47,0x1a,0xe4,0x90,0x9e,0x52,0xf0,0x22, ++0xe5,0x12,0x60,0x08,0x90,0x01,0xb9,0x74,0x01,0xf0,0x80,0x5e,0x90,0x9e,0x60,0xe0, ++0x54,0x0f,0xd3,0x94,0x01,0x40,0x08,0x90,0x01,0xb9,0x74,0x02,0xf0,0x80,0x4b,0x90, ++0x02,0x87,0xe0,0x60,0x08,0x90,0x01,0xb9,0x74,0x04,0xf0,0x80,0x3d,0x90,0x9e,0x75, ++0xe0,0xb4,0x02,0x10,0x90,0x9e,0x64,0xe0,0xfe,0xa3,0xe0,0xf5,0x82,0x8e,0x83,0xe0, ++0x60,0x17,0x80,0x26,0x90,0x9e,0x75,0xe0,0xb4,0x01,0x0e,0x90,0x01,0xaf,0xe0,0x60, ++0x08,0x90,0x01,0xb9,0x74,0x08,0xf0,0x80,0x11,0x90,0x9e,0x54,0xe0,0x70,0x08,0x90, ++0x01,0xb9,0x74,0x10,0xf0,0x80,0x03,0x7f,0x01,0x22,0x90,0x01,0xb8,0x74,0x02,0xf0, ++0x7f,0x00,0x22,0x90,0x06,0x04,0xe0,0x54,0xbf,0xf0,0xef,0x60,0x09,0xe5,0x73,0xb4, ++0x01,0x04,0xe4,0xff,0x51,0x62,0x90,0x9e,0x5e,0xe0,0x54,0xf0,0xf0,0xe0,0x44,0x0c, ++0xf0,0x22,0x8f,0x76,0x90,0x9e,0x5e,0xe0,0x90,0x01,0xc1,0xf0,0xa3,0xe5,0x12,0xf0, ++0x12,0x45,0xb1,0xef,0x64,0x01,0x70,0x2e,0x90,0x9e,0x69,0x12,0x47,0xfa,0xe5,0x76, ++0x60,0x10,0x74,0x21,0x2f,0xf5,0x82,0xe4,0x34,0xfc,0xf5,0x83,0xe0,0x44,0x10,0xf0, ++0x80,0x0e,0x74,0x21,0x2f,0xf5,0x82,0xe4,0x34,0xfc,0xf5,0x83,0xe0,0x54,0xef,0xf0, ++0x90,0x04,0x1f,0x74,0x20,0xf0,0x22,0x90,0x9e,0xaf,0xef,0xf0,0x51,0xc5,0x90,0x9e, ++0xaf,0xe0,0x60,0x05,0x90,0x05,0x22,0xe4,0xf0,0x90,0x9e,0x5e,0xe0,0x54,0xf0,0xf0, ++0xe0,0x44,0x04,0xf0,0x22,0x90,0x9d,0xff,0x12,0x43,0x53,0x90,0x80,0x85,0x12,0x2a, ++0x7f,0x7f,0x78,0x7e,0x08,0x12,0x2f,0xd9,0x90,0x9e,0x03,0x12,0x43,0x53,0x90,0x80, ++0x85,0x12,0x2a,0x7f,0x7f,0x04,0x7e,0x0c,0x12,0x2f,0xd9,0x90,0x9e,0x07,0x12,0x43, ++0x53,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0x00,0x7e,0x08,0x12,0x2f,0xd9,0x90,0x9e, ++0x0b,0x12,0x43,0x53,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0x70,0x7e,0x0e,0x12,0x2f, ++0xd9,0x90,0x80,0x59,0x12,0x2a,0x8b,0x00,0x03,0x2d,0x95,0xe4,0xfd,0xff,0x12,0x34, ++0x81,0x90,0x9e,0x77,0xe0,0xb4,0x01,0x11,0x90,0x80,0x59,0x12,0x2a,0x8b,0x00,0x03, ++0x2d,0x95,0xe4,0xfd,0x7f,0x01,0x12,0x34,0x81,0x22,0x8f,0x27,0xe4,0x90,0x9e,0xa8, ++0xf0,0xa3,0xf0,0x90,0x01,0x09,0xe0,0x7f,0x00,0x30,0xe7,0x02,0x7f,0x01,0xef,0x65, ++0x27,0x60,0x3e,0xc3,0x90,0x9e,0xa9,0xe0,0x94,0x88,0x90,0x9e,0xa8,0xe0,0x94,0x13, ++0x40,0x08,0x90,0x01,0xc6,0xe0,0x44,0x80,0xf0,0x22,0x90,0x9e,0xa8,0xe4,0x75,0xf0, ++0x01,0x12,0x42,0x81,0x7f,0x14,0x7e,0x00,0x12,0x37,0x54,0xd3,0x90,0x9e,0xa9,0xe0, ++0x94,0x32,0x90,0x9e,0xa8,0xe0,0x94,0x00,0x40,0xb9,0x90,0x01,0xc7,0xe0,0x30,0xe0, ++0xb2,0x22,0x90,0x9e,0x5e,0xe0,0x54,0xf0,0xf0,0xe0,0x44,0x01,0xf0,0x12,0x45,0x01, ++0x12,0x45,0x02,0xe0,0x54,0xf0,0xf0,0xe0,0x44,0x02,0xf0,0x22,0x90,0x9e,0x60,0xe0, ++0x30,0xe6,0x1c,0xe0,0x54,0x0f,0xff,0x90,0x9e,0x4e,0xe0,0xfe,0x4f,0x90,0x01,0x2f, ++0xf0,0xee,0x64,0x80,0x90,0x9e,0x4e,0xf0,0x90,0x9e,0x60,0xe0,0x54,0xbf,0xf0,0x22, ++0x8f,0x75,0x12,0x45,0xb1,0xef,0x64,0x01,0x70,0x2e,0x90,0x9e,0x6a,0x12,0x47,0xfa, ++0xe5,0x75,0x60,0x10,0x74,0x21,0x2f,0xf5,0x82,0xe4,0x34,0xfc,0xf5,0x83,0xe0,0x44, ++0x10,0xf0,0x80,0x0e,0x74,0x21,0x2f,0xf5,0x82,0xe4,0x34,0xfc,0xf5,0x83,0xe0,0x54, ++0xef,0xf0,0x90,0x04,0x1f,0x74,0x20,0xf0,0x22,0xe4,0x90,0x9e,0x2f,0xf0,0xe5,0x74, ++0x60,0x6a,0xe5,0x73,0x64,0x01,0x70,0x64,0xe5,0x74,0x14,0x60,0x29,0x24,0xfd,0x60, ++0x25,0x24,0x02,0x24,0xfb,0x50,0x02,0x80,0x23,0x90,0x9e,0x50,0xe0,0x14,0xf0,0xe0, ++0x60,0x04,0xa3,0xe0,0x60,0x16,0x90,0x9e,0x50,0xe0,0x70,0x0a,0x90,0x9e,0x5f,0xe0, ++0x90,0x9e,0x50,0xf0,0x80,0x00,0x90,0x9e,0x2f,0x74,0x01,0xf0,0x90,0x9e,0x2f,0xe0, ++0x60,0x2a,0x90,0x9e,0x63,0xe0,0x44,0x10,0xf0,0xe4,0x90,0x9e,0x89,0xf0,0x90,0x9e, ++0x5a,0x12,0x44,0x56,0x90,0x01,0x57,0x74,0x05,0xf0,0x90,0x9e,0x5e,0xe0,0x54,0x0f, ++0xc3,0x94,0x04,0x50,0x07,0x7d,0x01,0x7f,0x04,0x12,0x47,0x1a,0x22,0xef,0xc3,0x94, ++0x20,0x50,0x39,0xef,0x30,0xe0,0x17,0xed,0xc4,0x54,0xf0,0xfd,0xef,0xc3,0x13,0xfe, ++0x24,0xa4,0xf5,0x82,0xe4,0x34,0x04,0xf5,0x83,0xe0,0x54,0x0f,0x80,0x10,0xef,0xc3, ++0x13,0xfe,0x24,0xa4,0xf5,0x82,0xe4,0x34,0x04,0xf5,0x83,0xe0,0x54,0xf0,0xf0,0x74, ++0xa4,0x2e,0xf5,0x82,0xe4,0x34,0x04,0xf5,0x83,0xe0,0x4d,0xf0,0x22,0xad,0x07,0xed, ++0xc3,0x94,0x20,0x50,0x0d,0x74,0x84,0x2d,0xf5,0x82,0xe4,0x34,0x04,0xf5,0x83,0xe0, ++0x80,0x0b,0x74,0xa6,0x2d,0xf5,0x82,0xe4,0x34,0x9c,0xf5,0x83,0xe0,0x54,0x7f,0xf5, ++0x64,0xe5,0x64,0x54,0x1f,0xfc,0x75,0xf0,0x09,0xed,0x90,0x96,0x48,0x12,0x43,0x5f, ++0xe0,0xff,0x90,0x9e,0x3e,0xf0,0xed,0x25,0xe0,0x24,0x02,0xf5,0x82,0xe4,0x34,0x95, ++0xf5,0x83,0xe0,0xfb,0xa3,0xe0,0x90,0x9e,0x3f,0xcb,0xf0,0xa3,0xeb,0xf0,0xed,0x25, ++0xe0,0x24,0xc6,0xf5,0x82,0xe4,0x34,0x9b,0xf5,0x83,0xe0,0xfb,0xa3,0xe0,0x90,0x9e, ++0x41,0xcb,0xf0,0xa3,0xeb,0xf0,0xec,0x25,0xe0,0x24,0x66,0xf5,0x82,0xe4,0x34,0x41, ++0xf5,0x83,0xe4,0x93,0xfa,0x74,0x01,0x93,0xfb,0xed,0x25,0xe0,0x24,0xc2,0xf5,0x82, ++0xe4,0x34,0x95,0xf5,0x83,0xea,0xf0,0xa3,0xeb,0xf0,0xec,0xc3,0x9f,0x40,0x02,0xa1, ++0xd4,0x74,0x67,0x2d,0xf5,0x82,0xe4,0x34,0x9d,0xf5,0x83,0xec,0xf0,0x04,0xfb,0x90, ++0x9e,0x3e,0xe0,0xff,0xeb,0xd3,0x9f,0x40,0x02,0xc1,0x05,0xeb,0xc3,0x94,0x10,0x40, ++0x21,0xeb,0x24,0xf0,0xff,0x74,0x01,0x7e,0x00,0xa8,0x07,0x08,0x80,0x05,0xc3,0x33, ++0xce,0x33,0xce,0xd8,0xf9,0xff,0x90,0x9e,0x3f,0xe0,0x5e,0xfe,0xa3,0xe0,0x5f,0x4e, ++0x70,0x23,0xeb,0xc3,0x94,0x10,0x50,0x39,0x74,0x01,0x7e,0x00,0xa8,0x03,0x08,0x80, ++0x05,0xc3,0x33,0xce,0x33,0xce,0xd8,0xf9,0xff,0x90,0x9e,0x41,0xe0,0x5e,0xfe,0xa3, ++0xe0,0x5f,0x4e,0x60,0x1c,0xeb,0x64,0x13,0x60,0x08,0xeb,0x64,0x12,0x60,0x03,0xbb, ++0x11,0x09,0x90,0x9e,0x3f,0xe0,0x30,0xe0,0x02,0x7b,0x18,0xac,0x03,0x8c,0x64,0x80, ++0x34,0x0b,0x80,0x8b,0x90,0x9e,0x3e,0xe0,0xfb,0x6c,0x70,0x69,0x74,0x67,0x2d,0xf5, ++0x82,0xe4,0x34,0x9d,0xf5,0x83,0xec,0xf0,0x75,0xf0,0x09,0xed,0x90,0x96,0x4a,0x12, ++0x43,0x5f,0xe0,0xb4,0x01,0x0c,0xe5,0x64,0x20,0xe6,0x07,0xec,0x44,0x40,0xf5,0x64, ++0x80,0x03,0xaf,0x64,0x22,0xec,0x25,0xe0,0x24,0x9e,0xf5,0x82,0xe4,0x34,0x41,0xf5, ++0x83,0xe4,0x93,0xfe,0x74,0x01,0x93,0xff,0xec,0x25,0xe0,0x24,0x66,0xf5,0x82,0xe4, ++0x34,0x41,0xf5,0x83,0x74,0x01,0x93,0x2f,0xff,0xe4,0x93,0x3e,0xc3,0x13,0xfe,0xef, ++0x13,0xff,0xed,0x25,0xe0,0x24,0xc2,0xf5,0x82,0xe4,0x34,0x95,0xf5,0x83,0xee,0xf0, ++0xa3,0xef,0xf0,0x80,0x5b,0xec,0xd3,0x9b,0x40,0x56,0x90,0x9e,0x3e,0xe0,0xff,0x74, ++0x67,0x2d,0xf5,0x82,0xe4,0x34,0x9d,0xf5,0x83,0xef,0xf0,0xac,0x07,0x8f,0x64,0xec, ++0x25,0xe0,0x24,0x9e,0xf5,0x82,0xe4,0x34,0x41,0xf5,0x83,0xe4,0x93,0xfe,0x74,0x01, ++0x93,0xff,0xec,0x25,0xe0,0x24,0x66,0xf5,0x82,0xe4,0x34,0x41,0xf5,0x83,0x74,0x01, ++0x93,0x2f,0xff,0xe4,0x93,0x3e,0xc3,0x13,0xfe,0xef,0x13,0xff,0xed,0x25,0xe0,0x24, ++0xc2,0xf5,0x82,0xe4,0x34,0x95,0xf5,0x83,0xee,0xf0,0xa3,0xef,0xf0,0xaf,0x64,0x22, ++0x74,0x01,0x2d,0xf5,0x82,0xe4,0x34,0x94,0xf5,0x83,0xe4,0xf0,0xaf,0x05,0xe5,0x64, ++0x44,0x80,0xfd,0x12,0x5a,0x85,0xe5,0x64,0x44,0x80,0xff,0x22,0xe4,0xf5,0x59,0xe5, ++0x59,0xb4,0x20,0x14,0x90,0x9a,0xc5,0xe0,0x04,0xf0,0x90,0x95,0x01,0xe0,0xff,0x90, ++0x9a,0xc5,0xe0,0xb5,0x07,0x02,0xe4,0xf0,0x75,0xf0,0x09,0xe5,0x59,0x90,0x96,0x4b, ++0x12,0x43,0x5f,0xe0,0x64,0x01,0x60,0x03,0x02,0x6d,0x04,0xe5,0x59,0x25,0xe0,0x24, ++0x80,0xf5,0x82,0xe4,0x34,0x93,0xf5,0x83,0xe0,0xfe,0xa3,0xe0,0xd3,0x94,0x00,0xee, ++0x94,0x00,0x50,0x03,0x02,0x6d,0x04,0xe5,0x59,0x94,0x20,0x40,0x09,0x90,0x9a,0xc5, ++0xe0,0x60,0x03,0x02,0x6d,0x10,0xe5,0x59,0x75,0xf0,0x0a,0xa4,0x24,0x00,0xf9,0x74, ++0x90,0x35,0xf0,0x75,0x5e,0x01,0xf5,0x5f,0x89,0x60,0xe5,0x59,0x25,0xe0,0x24,0x80, ++0xf5,0x82,0xe4,0x34,0x93,0xf5,0x83,0xe0,0xff,0xa3,0xe0,0x90,0x9e,0x38,0xcf,0xf0, ++0xa3,0xef,0xf0,0xe5,0x59,0x25,0xe0,0x24,0xc4,0xf5,0x82,0xe4,0x34,0x98,0xf5,0x83, ++0xe0,0xff,0xa3,0xe0,0x90,0x9e,0x3a,0xcf,0xf0,0xa3,0xef,0xf0,0xe5,0x59,0xc3,0x94, ++0x20,0x50,0x14,0x74,0x84,0x25,0x59,0xf5,0x82,0xe4,0x34,0x04,0xf5,0x83,0xe0,0x54, ++0x3f,0x90,0x9e,0x34,0xf0,0x80,0x12,0x74,0xa6,0x25,0x59,0xf5,0x82,0xe4,0x34,0x9c, ++0xf5,0x83,0xe0,0x54,0x3f,0x90,0x9e,0x34,0xf0,0x90,0x9e,0x34,0xe0,0xfe,0x54,0x1f, ++0xa3,0xf0,0x75,0xf0,0x09,0xe5,0x59,0x90,0x96,0x48,0x12,0x43,0x5f,0xe0,0x90,0x9e, ++0x3d,0xf0,0x74,0xe6,0x25,0x59,0xf5,0x82,0xe4,0x34,0x9c,0xf5,0x83,0xe0,0xc3,0x94, ++0x05,0x40,0x03,0x02,0x69,0xdd,0x90,0x9e,0x3d,0xe0,0xff,0x90,0x9e,0x35,0xe0,0x9f, ++0x40,0x13,0x90,0x9e,0x3d,0xe0,0x90,0x9e,0x35,0xf0,0xee,0x54,0x40,0xfe,0x90,0x9e, ++0x34,0xf0,0xef,0x4e,0xf0,0x90,0x04,0xfd,0xe0,0x64,0x01,0x70,0x29,0x90,0x9e,0x35, ++0xe0,0xff,0x90,0x41,0x4a,0x93,0xfe,0x74,0x44,0x25,0x59,0xf5,0x82,0xe4,0x34,0x9a, ++0xf5,0x83,0xe0,0xc3,0x9e,0x40,0x06,0xef,0x90,0x40,0xda,0x80,0x30,0x90,0x9e,0x35, ++0xe0,0x90,0x40,0xf6,0x80,0x27,0x90,0x9e,0x35,0xe0,0xff,0x90,0x41,0x4a,0x93,0xfe, ++0x74,0x44,0x25,0x59,0xf5,0x82,0xe4,0x34,0x9a,0xf5,0x83,0xe0,0xc3,0x9e,0x40,0x06, ++0xef,0x90,0x41,0x12,0x80,0x07,0x90,0x9e,0x35,0xe0,0x90,0x41,0x2e,0x93,0x90,0x9e, ++0x3c,0xf0,0x90,0x9e,0x3c,0xe0,0x75,0xf0,0x06,0xa4,0x24,0x50,0xf9,0x74,0x40,0x35, ++0xf0,0x75,0x5b,0xff,0xf5,0x5c,0x89,0x5d,0x90,0x9e,0x34,0xe0,0x90,0x41,0xf2,0x93, ++0xff,0xd3,0x90,0x9e,0x3b,0xe0,0x9f,0x90,0x9e,0x3a,0xe0,0x94,0x00,0x40,0x09,0xe4, ++0xfd,0xaf,0x59,0x12,0x5c,0xd8,0x81,0x9b,0xe5,0x59,0x25,0xe0,0x24,0xc2,0xf5,0x82, ++0xe4,0x34,0x95,0xf5,0x83,0xe0,0xf5,0x61,0xa3,0xe0,0xf5,0x62,0xab,0x5b,0xaa,0x5c, ++0xa9,0x5d,0x12,0x29,0xd9,0xff,0x7e,0x00,0xab,0x5e,0xaa,0x5f,0xa9,0x60,0x12,0x42, ++0x97,0xfd,0xac,0xf0,0x12,0x29,0xf2,0xef,0x25,0x62,0xf5,0x62,0xee,0x35,0x61,0xf5, ++0x61,0xab,0x5b,0xaa,0x5c,0xa9,0x5d,0x90,0x00,0x01,0x12,0x42,0x20,0xff,0x7e,0x00, ++0xab,0x5e,0xaa,0x5f,0xa9,0x60,0x90,0x00,0x02,0x12,0x42,0xc2,0xfd,0xac,0xf0,0x12, ++0x29,0xf2,0xef,0x25,0x62,0xf5,0x62,0xee,0x35,0x61,0xf5,0x61,0xab,0x5b,0xaa,0x5c, ++0xa9,0x5d,0x90,0x00,0x02,0x12,0x42,0x20,0xff,0x7e,0x00,0xab,0x5e,0xaa,0x5f,0xa9, ++0x60,0x90,0x00,0x04,0x12,0x42,0xc2,0xfd,0xac,0xf0,0x12,0x29,0xf2,0xef,0x25,0x62, ++0xf5,0x62,0xee,0x35,0x61,0xf5,0x61,0xab,0x5b,0xaa,0x5c,0xa9,0x5d,0x90,0x00,0x03, ++0x12,0x42,0x20,0xff,0x7e,0x00,0xab,0x5e,0xaa,0x5f,0xa9,0x60,0x90,0x00,0x06,0x12, ++0x42,0xc2,0xfd,0xac,0xf0,0x12,0x29,0xf2,0xef,0x25,0x62,0xf5,0x62,0xee,0x35,0x61, ++0xf5,0x61,0xab,0x5b,0xaa,0x5c,0xa9,0x5d,0x90,0x00,0x04,0x12,0x42,0x20,0xff,0x7e, ++0x00,0xab,0x5e,0xaa,0x5f,0xa9,0x60,0x90,0x00,0x08,0x12,0x42,0xc2,0xfd,0xac,0xf0, ++0x12,0x29,0xf2,0xef,0x25,0x62,0xf5,0x62,0xee,0x35,0x61,0xf5,0x61,0xab,0x5b,0xaa, ++0x5c,0xa9,0x5d,0x90,0x00,0x05,0x12,0x42,0x20,0xff,0x7e,0x00,0x90,0x9e,0x38,0xe0, ++0xfc,0xa3,0xe0,0xfd,0x12,0x29,0xf2,0xd3,0xe5,0x62,0x9f,0xe5,0x61,0x9e,0x40,0x0c, ++0xe5,0x62,0x9f,0xf5,0x62,0xe5,0x61,0x9e,0xf5,0x61,0x80,0x05,0xe4,0xf5,0x61,0xf5, ++0x62,0xe5,0x59,0x25,0xe0,0x24,0xc2,0xf5,0x82,0xe4,0x34,0x95,0xf5,0x83,0xe5,0x61, ++0xf0,0xa3,0xe5,0x62,0xf0,0x90,0x9e,0x34,0xe0,0x25,0xe0,0x24,0x66,0xf5,0x82,0xe4, ++0x34,0x41,0xf5,0x83,0xc3,0x74,0x01,0x93,0x95,0x62,0xe4,0x93,0x95,0x61,0x50,0x07, ++0xaf,0x59,0x12,0x64,0xbd,0x81,0x6f,0x90,0x9e,0x34,0xe0,0x25,0xe0,0x24,0x9e,0xf5, ++0x82,0xe4,0x34,0x41,0xf5,0x83,0xd3,0x74,0x01,0x93,0x95,0x62,0xe4,0x93,0x95,0x61, ++0x50,0x02,0x81,0x6f,0x7d,0x01,0xaf,0x59,0x12,0x5c,0xd8,0x81,0x6f,0x74,0xe6,0x25, ++0x59,0xf5,0x82,0xe4,0x34,0x9c,0xf5,0x83,0xe0,0xfc,0x64,0x05,0x60,0x02,0x61,0x78, ++0x90,0x96,0x43,0xe0,0xff,0xb4,0x03,0x0b,0x90,0x9e,0x35,0xe0,0xc3,0x94,0x19,0x40, ++0x3d,0x80,0x2e,0xef,0xb4,0x02,0x0b,0x90,0x9e,0x35,0xe0,0xc3,0x94,0x11,0x40,0x2e, ++0x80,0x1f,0x90,0x96,0x43,0xe0,0xff,0xb4,0x01,0x0b,0x90,0x9e,0x35,0xe0,0xc3,0x94, ++0x0a,0x40,0x1b,0x80,0x0c,0xef,0x70,0x11,0x90,0x9e,0x35,0xe0,0xc3,0x94,0x03,0x40, ++0x0d,0x90,0x9a,0x84,0x74,0x01,0xf0,0x80,0x05,0xe4,0x90,0x9a,0x84,0xf0,0x74,0x84, ++0x25,0x59,0xf5,0x82,0xe4,0x34,0x98,0xf5,0x83,0xe0,0xf5,0x63,0x74,0x44,0x25,0x59, ++0xf5,0x82,0xe4,0x34,0x9a,0xf5,0x83,0xe0,0xff,0xc3,0x94,0x30,0x50,0x02,0x61,0x25, ++0x90,0x9a,0x84,0xe0,0x64,0x01,0x60,0x02,0x61,0x25,0x74,0x85,0x25,0x59,0xf5,0x82, ++0xe4,0x34,0x9a,0xf5,0x83,0xe0,0x64,0x0a,0x60,0x51,0xef,0x24,0x05,0xff,0xe4,0x33, ++0xfe,0x74,0x41,0x25,0x59,0xf5,0x82,0xe4,0x34,0x94,0xf5,0x83,0xe0,0xfd,0xd3,0x9f, ++0xee,0x64,0x80,0xf8,0x74,0x80,0x98,0x50,0x32,0xed,0x24,0x05,0xff,0xe4,0x33,0xfe, ++0x74,0x44,0x25,0x59,0xf5,0x82,0xe4,0x34,0x9a,0xf5,0x83,0xe0,0xd3,0x9f,0xee,0x64, ++0x80,0xf8,0x74,0x80,0x98,0x50,0x14,0x74,0x26,0x25,0x59,0xf5,0x82,0xe4,0x34,0x9d, ++0xf5,0x83,0xe0,0xff,0x90,0x9e,0x35,0xe0,0x6f,0x60,0x3d,0x74,0x44,0x25,0x59,0xf5, ++0x82,0xe4,0x34,0x9a,0xf5,0x83,0xe0,0xff,0xd3,0x94,0x42,0x40,0x05,0x75,0x63,0x05, ++0x80,0x0e,0xef,0xd3,0x94,0x39,0x40,0x05,0x75,0x63,0x03,0x80,0x03,0x75,0x63,0x01, ++0x74,0x41,0x25,0x59,0xf5,0x82,0xe4,0x34,0x94,0xf5,0x83,0xef,0xf0,0x74,0x85,0x25, ++0x59,0xf5,0x82,0xe4,0x34,0x9a,0x80,0x29,0x74,0xe6,0x25,0x59,0xf5,0x82,0xe4,0x34, ++0x9c,0xf5,0x83,0xe4,0xf0,0x74,0x85,0x25,0x59,0xf5,0x82,0xe4,0x34,0x9a,0xf5,0x83, ++0xe0,0x04,0xf0,0x80,0x10,0xe4,0xf5,0x63,0x74,0xe6,0x25,0x59,0xf5,0x82,0xe4,0x34, ++0x9c,0xf5,0x83,0xe4,0xf0,0x90,0x9e,0x35,0xe0,0xff,0x74,0x26,0x25,0x59,0xf5,0x82, ++0xe4,0x34,0x9d,0xf5,0x83,0xef,0xf0,0x74,0x84,0x25,0x59,0xf5,0x82,0xe4,0x34,0x98, ++0xf5,0x83,0xe5,0x63,0xf0,0x75,0xf0,0x09,0xe5,0x59,0x90,0x96,0x4c,0x12,0x43,0x5f, ++0xe0,0xb4,0x01,0x10,0xe4,0xf5,0x63,0x74,0xe6,0x25,0x59,0xf5,0x82,0xe4,0x34,0x9c, ++0xf5,0x83,0xe4,0xf0,0xad,0x63,0x81,0x6a,0xec,0x64,0x06,0x60,0x02,0x81,0x6f,0xf5, ++0x61,0xf5,0x62,0x90,0x42,0x13,0x93,0xff,0x7e,0x00,0x90,0x9e,0x38,0xe0,0xfc,0xa3, ++0xe0,0xfd,0x12,0x29,0xf2,0x90,0x9e,0x36,0xee,0xf0,0xa3,0xef,0xf0,0x74,0x84,0x25, ++0x59,0xf5,0x82,0xe4,0x34,0x98,0xf5,0x83,0xe0,0xf5,0x63,0xe4,0xf5,0x5a,0xab,0x5e, ++0xaa,0x5f,0xa9,0x60,0x75,0xf0,0x02,0xe5,0x5a,0xa4,0xf5,0x82,0x85,0xf0,0x83,0x12, ++0x42,0xc2,0xfd,0xac,0xf0,0xe5,0x5a,0x90,0x42,0x0e,0x93,0xff,0x7e,0x00,0x12,0x29, ++0xf2,0xef,0x25,0x62,0xf5,0x62,0xee,0x35,0x61,0xf5,0x61,0xc3,0x90,0x9e,0x37,0xe0, ++0x95,0x62,0x90,0x9e,0x36,0xe0,0x95,0x61,0x40,0x07,0x05,0x5a,0xe5,0x5a,0xb4,0x05, ++0xbd,0xe5,0x5a,0xc3,0x13,0xf5,0x5a,0xe5,0x63,0xb4,0x01,0x06,0xe5,0x5a,0x70,0x46, ++0x80,0x13,0xe5,0x63,0xb4,0x03,0x15,0xe5,0x5a,0x70,0x05,0x75,0x63,0x03,0x80,0x39, ++0xe5,0x5a,0xb4,0x01,0x05,0x75,0x63,0x01,0x80,0x2f,0x80,0x2a,0xe5,0x63,0xb4,0x05, ++0x28,0xe5,0x5a,0x70,0x05,0x75,0x63,0x05,0x80,0x0d,0xe5,0x5a,0xb4,0x01,0x05,0x75, ++0x63,0x03,0x80,0x03,0x75,0x63,0x01,0xd3,0x90,0x9e,0x3b,0xe0,0x94,0x03,0x90,0x9e, ++0x3a,0xe0,0x94,0x00,0x40,0x03,0xe4,0xf5,0x63,0xd3,0x90,0x9e,0x3b,0xe0,0x94,0x03, ++0x90,0x9e,0x3a,0xe0,0x94,0x00,0x40,0x03,0xe4,0xf5,0x63,0x74,0x84,0x25,0x59,0xf5, ++0x82,0xe4,0x34,0x98,0xf5,0x83,0xe5,0x63,0xf0,0xfd,0xaf,0x59,0x12,0x64,0x7d,0x74, ++0xe6,0x25,0x59,0xf5,0x82,0xe4,0x34,0x9c,0xf5,0x83,0xe0,0xd3,0x94,0x05,0x74,0xe6, ++0x50,0x0e,0x25,0x59,0xf5,0x82,0xe4,0x34,0x9c,0xf5,0x83,0xe0,0x04,0xf0,0x80,0x0b, ++0x25,0x59,0xf5,0x82,0xe4,0x34,0x9c,0xf5,0x83,0xe4,0xf0,0xab,0x5e,0xaa,0x5f,0xa9, ++0x60,0xe4,0xf5,0xf0,0x12,0x42,0xfa,0xab,0x5e,0xaa,0x5f,0xa9,0x60,0x90,0x00,0x02, ++0xe4,0xf5,0xf0,0x12,0x43,0x19,0x90,0x00,0x04,0xe4,0xf5,0xf0,0x12,0x43,0x19,0x90, ++0x00,0x06,0xe4,0xf5,0xf0,0x12,0x43,0x19,0x90,0x00,0x08,0xe4,0xf5,0xf0,0x12,0x43, ++0x19,0xe5,0x59,0x25,0xe0,0x24,0x80,0xf5,0x82,0xe4,0x34,0x93,0xf5,0x83,0xe4,0xf0, ++0xa3,0xf0,0xe5,0x59,0x25,0xe0,0x24,0xc4,0xf5,0x82,0xe4,0x34,0x98,0xf5,0x83,0xe4, ++0xf0,0xa3,0xf0,0xe5,0x59,0x25,0xe0,0x24,0x44,0xf5,0x82,0xe4,0x34,0x99,0xf5,0x83, ++0xe4,0xf0,0xa3,0xf0,0x05,0x59,0xe5,0x59,0xc3,0x94,0x40,0x50,0x03,0x02,0x66,0xbf, ++0x22,0x90,0x04,0x44,0x74,0x11,0xf0,0xa3,0x74,0xf0,0xf0,0xa3,0x74,0x0f,0xf0,0xa3, ++0xe4,0xf0,0xfd,0x74,0xa4,0x2d,0xf5,0x82,0xe4,0x34,0x04,0xf5,0x83,0xe4,0xf0,0x0d, ++0xbd,0x10,0xf0,0xe4,0x90,0x9a,0xc5,0xf0,0x90,0x95,0x01,0x04,0xf0,0xe4,0xfd,0x75, ++0xf0,0x0a,0xed,0x90,0x90,0x00,0x12,0x43,0x5f,0xe4,0xf0,0xa3,0xf0,0x75,0xf0,0x0a, ++0xed,0x90,0x90,0x02,0x12,0x43,0x5f,0xe4,0xf0,0xa3,0xf0,0x75,0xf0,0x0a,0xed,0x90, ++0x90,0x04,0x12,0x43,0x5f,0xe4,0xf0,0xa3,0xf0,0x75,0xf0,0x0a,0xed,0x90,0x90,0x06, ++0x12,0x43,0x5f,0xe4,0xf0,0xa3,0xf0,0x75,0xf0,0x0a,0xed,0x90,0x90,0x08,0x12,0x43, ++0x5f,0xe4,0xf0,0xa3,0xf0,0x74,0x26,0x2d,0xf5,0x82,0xe4,0x34,0x9d,0xf5,0x83,0x74, ++0x13,0xf0,0x74,0x85,0x2d,0xf5,0x82,0xe4,0x34,0x9a,0xf5,0x83,0xe4,0xf0,0x74,0x84, ++0x2d,0xf5,0x82,0xe4,0x34,0x98,0xf5,0x83,0xe4,0xf0,0xed,0x25,0xe0,0x24,0x80,0xf5, ++0x82,0xe4,0x34,0x93,0xf5,0x83,0xe4,0xf0,0xa3,0xf0,0xed,0x25,0xe0,0x24,0xc4,0xf5, ++0x82,0xe4,0x34,0x98,0xf5,0x83,0xe4,0xf0,0xa3,0xf0,0xed,0x25,0xe0,0x24,0xc4,0xf5, ++0x82,0xe4,0x34,0x99,0xf5,0x83,0xe4,0xf0,0xa3,0xf0,0xed,0x25,0xe0,0x24,0x44,0xf5, ++0x82,0xe4,0x34,0x99,0xf5,0x83,0xe4,0xf0,0xa3,0xf0,0xed,0x25,0xe0,0x24,0xc6,0xf5, ++0x82,0xe4,0x34,0x9a,0xf5,0x83,0xe4,0xf0,0xa3,0xf0,0xed,0x25,0xe0,0x24,0x46,0xf5, ++0x82,0xe4,0x34,0x9b,0xf5,0x83,0xe4,0xf0,0xa3,0xf0,0x74,0x86,0x2d,0xf5,0x82,0xe4, ++0x34,0x9c,0xf5,0x83,0xe4,0xf0,0x74,0x46,0x2d,0xf5,0x82,0xe4,0x34,0x9c,0xf5,0x83, ++0xe4,0xf0,0x74,0xe6,0x2d,0xf5,0x82,0xe4,0x34,0x9c,0xf5,0x83,0xe4,0xf0,0x90,0x41, ++0xc4,0x93,0xfe,0x74,0x01,0x93,0xff,0x90,0x41,0x8c,0x74,0x01,0x93,0x2f,0xff,0xe4, ++0x93,0x3e,0xc3,0x13,0xfe,0xef,0x13,0xff,0xed,0x25,0xe0,0x24,0xc2,0xf5,0x82,0xe4, ++0x34,0x95,0xf5,0x83,0xee,0xf0,0xa3,0xef,0xf0,0x75,0xf0,0x09,0xed,0x90,0x96,0x4b, ++0x12,0x43,0x5f,0x74,0x01,0xf0,0x75,0xf0,0x09,0xed,0x90,0x96,0x4a,0x12,0x43,0x5f, ++0x74,0x01,0xf0,0x74,0x82,0x2d,0xf5,0x82,0xe4,0x34,0x95,0xf5,0x83,0x74,0x0c,0xf0, ++0x75,0xf0,0x09,0xed,0x90,0x96,0x46,0x12,0x43,0x5f,0x74,0xff,0xf0,0xa3,0xf0,0x75, ++0xf0,0x09,0xed,0x90,0x96,0x44,0x12,0x43,0x5f,0xe4,0xf0,0xa3,0x74,0x0f,0xf0,0x75, ++0xf0,0x09,0xed,0x90,0x96,0x48,0x12,0x43,0x5f,0x74,0x13,0xf0,0x75,0xf0,0x09,0xed, ++0x90,0x96,0x49,0x12,0x43,0x5f,0xe4,0xf0,0xed,0xc3,0x94,0x20,0x50,0x0f,0x74,0x84, ++0x2d,0xf5,0x82,0xe4,0x34,0x04,0xf5,0x83,0x74,0x13,0xf0,0x80,0x0d,0x74,0xa6,0x2d, ++0xf5,0x82,0xe4,0x34,0x9c,0xf5,0x83,0x74,0x13,0xf0,0x0d,0xed,0x64,0x40,0x60,0x02, ++0xa1,0x3f,0x22,0x12,0x29,0xd9,0xf5,0x59,0xc3,0x94,0x40,0x50,0x15,0x90,0x00,0x02, ++0x12,0x42,0x20,0xff,0x74,0x44,0x25,0x59,0xf5,0x82,0xe4,0x34,0x9a,0xf5,0x83,0xef, ++0xf0,0x22,0xe5,0x59,0xb4,0x40,0x0a,0x90,0x00,0x02,0x12,0x42,0x20,0x90,0x96,0x42, ++0xf0,0x22,0x90,0x00,0x04,0x12,0x42,0x20,0xff,0x54,0x3f,0xfe,0xef,0x54,0x80,0xc4, ++0x13,0x13,0x13,0x54,0x01,0xfd,0xaf,0x06,0x02,0x55,0x35,0x12,0x29,0xd9,0x90,0x95, ++0x01,0xf0,0x22,0x12,0x29,0xd9,0xf5,0x73,0x22,0x90,0x00,0x02,0x12,0x42,0x20,0xff, ++0x30,0xe0,0x25,0x12,0x29,0xd9,0x90,0x9e,0x56,0xf0,0x90,0x00,0x01,0x12,0x42,0x20, ++0x90,0x9e,0x57,0xf0,0xef,0xc3,0x13,0x54,0x7f,0x90,0x9e,0x55,0xf0,0x90,0x00,0x03, ++0x12,0x42,0x20,0x90,0x9e,0x5b,0xf0,0x22,0x90,0x9e,0x56,0x74,0x01,0xf0,0x90,0x9e, ++0x57,0x74,0x03,0xf0,0x90,0x9e,0x55,0x74,0x14,0xf0,0x90,0x9e,0x5b,0x74,0x05,0xf0, ++0x22,0x12,0x29,0xd9,0x30,0xe0,0x18,0xc3,0x13,0x54,0x7f,0x90,0x9e,0x5a,0xf0,0x90, ++0x00,0x01,0x12,0x42,0x20,0xff,0x90,0x9e,0x58,0xe4,0xf0,0xa3,0xef,0xf0,0x22,0x90, ++0x9e,0x5a,0x74,0x07,0xf0,0x90,0x9e,0x58,0xe4,0xf0,0xa3,0x74,0x02,0xf0,0x22,0x90, ++0x02,0x09,0xe0,0xfd,0x12,0x29,0xd9,0xfe,0xaf,0x05,0xed,0x2e,0x90,0x9e,0x67,0xf0, ++0x90,0x00,0x01,0x12,0x42,0x20,0xff,0xed,0x2f,0x90,0x9e,0x68,0xf0,0x90,0x00,0x02, ++0x12,0x42,0x20,0xff,0xed,0x2f,0x90,0x9e,0x69,0xf0,0x90,0x00,0x03,0x12,0x42,0x20, ++0xff,0xed,0x2f,0x90,0x9e,0x6a,0xf0,0x90,0x00,0x04,0x12,0x42,0x20,0xff,0xae,0x05, ++0xed,0x2f,0x90,0x9e,0x6b,0xf0,0x22,0xd3,0x10,0xaf,0x01,0xc3,0xc0,0xd0,0x90,0x9e, ++0x3f,0x12,0x43,0x8b,0x90,0x9e,0x3f,0x12,0x43,0x6b,0x90,0x00,0x01,0x12,0x42,0xc2, ++0xfa,0xe5,0xf0,0x24,0x00,0xff,0xe4,0x3a,0xfe,0x90,0x9e,0x3f,0x12,0x43,0x6b,0x90, ++0x00,0x01,0xee,0x8f,0xf0,0x12,0x43,0x19,0x12,0x29,0xd9,0xff,0x60,0x2c,0xb5,0x22, ++0x16,0x90,0x9e,0x3f,0x12,0x43,0x6b,0x90,0x00,0x01,0x12,0x42,0xc2,0x65,0x24,0x70, ++0x04,0xe5,0x23,0x65,0xf0,0x60,0x23,0x90,0x9e,0x3f,0x12,0x43,0x6b,0x90,0x00,0x01, ++0x12,0x42,0xc2,0xff,0xae,0xf0,0x11,0x6f,0x80,0x10,0x90,0x9e,0x3f,0x12,0x43,0x6b, ++0x12,0x29,0xd9,0x65,0x22,0x60,0x03,0x12,0x44,0xca,0xd0,0xd0,0x92,0xaf,0x22,0x90, ++0x9e,0x42,0xee,0xf0,0xa3,0xef,0xf0,0x75,0x22,0x01,0x8e,0x23,0xf5,0x24,0xe4,0xfd, ++0x7f,0x0b,0x11,0xb1,0xe4,0xfd,0x7f,0x02,0x11,0xb1,0x31,0x87,0xe4,0xff,0x31,0x7b, ++0xe4,0xf5,0x26,0x90,0x01,0xc9,0xe5,0x26,0xf0,0x90,0x9e,0x42,0xe0,0xfc,0xa3,0xe0, ++0xfd,0xec,0xfb,0x8d,0x44,0xe4,0xf5,0x45,0x7d,0x01,0x7f,0x60,0x7e,0x01,0x02,0x35, ++0xab,0xd3,0x10,0xaf,0x01,0xc3,0xc0,0xd0,0x90,0x9e,0x45,0xed,0xf0,0x90,0x9e,0x44, ++0xef,0xf0,0xd3,0x94,0x07,0x50,0x4f,0xa3,0xe0,0x70,0x1a,0x90,0x9e,0x44,0xe0,0xff, ++0x74,0x01,0xa8,0x07,0x08,0x80,0x02,0xc3,0x33,0xd8,0xfc,0xf4,0xff,0x90,0x00,0x47, ++0xe0,0x5f,0xf0,0x80,0x17,0x90,0x9e,0x44,0xe0,0xff,0x74,0x01,0xa8,0x07,0x08,0x80, ++0x02,0xc3,0x33,0xd8,0xfc,0xff,0x90,0x00,0x47,0xe0,0x4f,0xf0,0x12,0x4d,0x28,0x90, ++0x9e,0x44,0xe0,0xff,0x74,0x01,0xa8,0x07,0x08,0x80,0x02,0xc3,0x33,0xd8,0xfc,0xf4, ++0xff,0x90,0x00,0x46,0x80,0x5a,0x90,0x9e,0x44,0xe0,0x24,0xf8,0xf0,0xa3,0xe0,0x70, ++0x1d,0x90,0x9e,0x44,0xe0,0xff,0x74,0x01,0xa8,0x07,0x08,0x80,0x02,0xc3,0x33,0xd8, ++0xfc,0xc4,0x54,0xf0,0xf4,0xff,0x90,0x00,0x43,0xe0,0x5f,0xf0,0x80,0x1a,0x90,0x9e, ++0x44,0xe0,0xff,0x74,0x01,0xa8,0x07,0x08,0x80,0x02,0xc3,0x33,0xd8,0xfc,0xc4,0x54, ++0xf0,0xff,0x90,0x00,0x43,0xe0,0x4f,0xf0,0x12,0x4d,0x28,0x90,0x9e,0x44,0xe0,0xff, ++0x74,0x01,0xa8,0x07,0x08,0x80,0x02,0xc3,0x33,0xd8,0xfc,0xf4,0xff,0x90,0x00,0x43, ++0xe0,0x5f,0xf0,0x12,0x4d,0x28,0xd0,0xd0,0x92,0xaf,0x22,0x90,0x01,0xca,0xe5,0x25, ++0xf0,0xef,0x60,0x02,0x31,0xe8,0x22,0x7f,0x0b,0x51,0x08,0xef,0x65,0x25,0x60,0x10, ++0xe5,0x25,0xb4,0x01,0x05,0xe4,0xf5,0x25,0x80,0x03,0x75,0x25,0x01,0x7f,0x01,0x22, ++0x7f,0x00,0x22,0xe5,0x22,0x64,0x01,0x70,0x3e,0x31,0x87,0xbf,0x01,0x04,0x7f,0x01, ++0x31,0x7b,0x90,0x00,0x46,0xe0,0x44,0x04,0xfd,0x7f,0x46,0x12,0x4e,0x30,0x90,0x00, ++0x44,0xe0,0x54,0xfb,0xfd,0x7f,0x44,0x12,0x4e,0x30,0x90,0x00,0x46,0xe0,0x54,0xfb, ++0xfd,0x7f,0x46,0x12,0x4e,0x30,0x7f,0x02,0x51,0x08,0x8f,0x26,0x90,0x01,0xc9,0xe5, ++0x26,0xf0,0xb4,0x01,0x02,0x31,0xe8,0x22,0x90,0x00,0x49,0xe0,0x90,0x9e,0xb1,0xf0, ++0xe0,0x54,0x0f,0xf0,0x44,0xf0,0xfd,0x7f,0x49,0x12,0x4e,0x30,0x90,0x9e,0xb1,0xe0, ++0x44,0xb0,0xfd,0x7f,0x49,0x02,0x4e,0x30,0xd3,0x10,0xaf,0x01,0xc3,0xc0,0xd0,0x90, ++0x9e,0xb2,0xef,0xf0,0xd3,0x94,0x07,0x50,0x47,0xe0,0xff,0x74,0x01,0xa8,0x07,0x08, ++0x80,0x02,0xc3,0x33,0xd8,0xfc,0xf4,0xff,0x90,0x00,0x46,0xe0,0x5f,0xf0,0x12,0x4d, ++0x28,0x90,0x9e,0xb2,0xe0,0xfd,0x74,0x01,0x7e,0x00,0xa8,0x05,0x08,0x80,0x05,0xc3, ++0x33,0xce,0x33,0xce,0xd8,0xf9,0xff,0x90,0x00,0x44,0xe0,0xfb,0xe4,0xfe,0xef,0x5b, ++0xa8,0x05,0x08,0x80,0x06,0xce,0xa2,0xe7,0x13,0xce,0x13,0xd8,0xf8,0xff,0x80,0x44, ++0x90,0x9e,0xb2,0xe0,0x24,0xf8,0xf0,0xe0,0xff,0x74,0x01,0xa8,0x07,0x08,0x80,0x02, ++0xc3,0x33,0xd8,0xfc,0x12,0x4d,0x20,0x90,0x9e,0xb2,0xe0,0xfd,0x74,0x01,0x7e,0x00, ++0xa8,0x05,0x08,0x80,0x05,0xc3,0x33,0xce,0x33,0xce,0xd8,0xf9,0xff,0x90,0x00,0x42, ++0xe0,0xfb,0xe4,0xfe,0xef,0x5b,0xa8,0x05,0x08,0x80,0x06,0xce,0xa2,0xe7,0x13,0xce, ++0x13,0xd8,0xf8,0xff,0xd0,0xd0,0x92,0xaf,0x22,0xd3,0x10,0xaf,0x01,0xc3,0xc0,0xd0, ++0x90,0x9e,0x6d,0xe0,0x90,0x9e,0x40,0xf0,0x90,0x9e,0x6e,0xe0,0xf5,0x64,0xa3,0xe0, ++0xf5,0x65,0xe4,0xf5,0x61,0x74,0x70,0x25,0x61,0xf5,0x82,0xe4,0x34,0x9e,0xf5,0x83, ++0xe0,0xff,0x74,0x66,0x25,0x61,0xf8,0xa6,0x07,0x05,0x61,0xe5,0x61,0xb4,0x04,0xe5, ++0x90,0x9e,0x40,0xe0,0x12,0x43,0x94,0x73,0x06,0x00,0x74,0x2e,0x01,0x73,0x0c,0x02, ++0x73,0x0c,0x03,0x73,0x0c,0x04,0x74,0x2e,0x05,0x73,0xfe,0x80,0x74,0x14,0x81,0x74, ++0x2e,0x82,0x00,0x00,0x74,0x2a,0xaf,0x69,0x91,0x35,0x81,0x2e,0x90,0x9e,0x40,0xe0, ++0xff,0xb4,0x02,0x08,0x90,0x9e,0x3f,0x74,0x01,0xf0,0x80,0x0f,0xef,0x90,0x9e,0x3f, ++0xb4,0x03,0x05,0x74,0x02,0xf0,0x80,0x03,0x74,0x04,0xf0,0xc3,0xe5,0x64,0x94,0x08, ++0x50,0x49,0xe4,0xf5,0x61,0x90,0x9e,0x3f,0xe0,0xff,0xe5,0x61,0xc3,0x9f,0x40,0x02, ++0x81,0x2e,0xc3,0xe5,0x64,0x94,0x01,0x50,0x14,0xe5,0x61,0x25,0x65,0xff,0xc3,0x74, ++0x03,0x95,0x61,0x24,0x66,0xf8,0xe6,0xfd,0x12,0x4e,0x30,0x80,0x1a,0xc3,0x74,0x03, ++0x95,0x61,0x24,0x66,0xf8,0xe6,0xff,0xe5,0x61,0x7c,0x00,0x25,0x65,0xfd,0xec,0x35, ++0x64,0x8d,0x82,0xf5,0x83,0xef,0xf0,0x05,0x61,0x80,0xba,0xc3,0xe5,0x64,0x94,0x10, ++0x40,0x02,0x81,0x2e,0x90,0x9e,0x40,0xe0,0x64,0x04,0x60,0x02,0x81,0x2e,0xaf,0x67, ++0xfc,0xfd,0xfe,0x78,0x10,0x12,0x2a,0x6c,0xc0,0x04,0xc0,0x05,0xc0,0x06,0xc0,0x07, ++0xaf,0x66,0xe4,0xfc,0xfd,0xfe,0x78,0x18,0x12,0x2a,0x6c,0xd0,0x03,0xd0,0x02,0xd0, ++0x01,0xd0,0x00,0x12,0x43,0x46,0xc0,0x04,0xc0,0x05,0xc0,0x06,0xc0,0x07,0xaf,0x68, ++0xe4,0xfc,0xfd,0xfe,0x78,0x08,0x12,0x2a,0x6c,0xd0,0x03,0xd0,0x02,0xd0,0x01,0xd0, ++0x00,0x12,0x43,0x46,0xa8,0x04,0xa9,0x05,0xaa,0x06,0xab,0x07,0xaf,0x69,0xe4,0xfc, ++0xfd,0xfe,0x12,0x43,0x46,0xa3,0x12,0x2a,0x7f,0x90,0x9e,0x41,0x12,0x43,0x53,0x90, ++0x80,0x85,0x12,0x2a,0x7f,0xaf,0x65,0xae,0x64,0x12,0x2f,0xd9,0x80,0x30,0xe5,0x68, ++0x7f,0x00,0xfe,0xef,0x25,0x69,0xf5,0x63,0xe4,0x3e,0xf5,0x62,0xaf,0x63,0xfe,0x12, ++0x37,0x54,0x80,0x1a,0xe5,0x68,0x7f,0x00,0xfe,0xef,0x25,0x69,0xf5,0x63,0xe4,0x3e, ++0xf5,0x62,0xaf,0x63,0xfe,0x12,0x36,0xcb,0x80,0x04,0x7f,0x00,0x80,0x02,0x7f,0x01, ++0xd0,0xd0,0x92,0xaf,0x22,0x8f,0x6a,0xe4,0x90,0x9e,0x45,0xf0,0xe5,0x6a,0x14,0xfe, ++0x90,0x9e,0x45,0xe0,0xff,0xc3,0x9e,0x50,0x0e,0xef,0x04,0xfd,0x12,0x34,0xb7,0x90, ++0x9e,0x45,0xe0,0x04,0xf0,0x80,0xe5,0xe5,0x6a,0x14,0xff,0x7d,0xff,0x12,0x34,0xb7, ++0x90,0x9e,0x45,0xe5,0x6a,0xf0,0x90,0x9e,0x45,0xe0,0xc3,0x94,0xff,0x50,0x0f,0xe0, ++0xff,0x04,0xfd,0x12,0x34,0xb7,0x90,0x9e,0x45,0xe0,0x04,0xf0,0x80,0xe8,0xad,0x6a, ++0x7f,0xff,0x02,0x34,0xb7,0xd3,0x10,0xaf,0x01,0xc3,0xc0,0xd0,0xe4,0xf5,0x5b,0x75, ++0x5c,0x04,0xf5,0x5d,0xf5,0x5f,0xf5,0x60,0x90,0x02,0x09,0xe0,0xff,0x12,0x29,0xd9, ++0xfe,0xef,0x2e,0xf5,0x5e,0x30,0xe0,0x08,0x75,0x59,0x00,0x75,0x5a,0x80,0x80,0x05, ++0xe4,0xf5,0x59,0xf5,0x5a,0xe5,0x5e,0xc3,0x13,0x90,0xfd,0x10,0xf0,0x74,0x20,0x25, ++0x5b,0xf5,0x5b,0xad,0x5a,0xe5,0x5b,0x2d,0xff,0x24,0x01,0xf5,0x82,0xe4,0x34,0xfc, ++0xf5,0x83,0xe0,0x90,0x9e,0x6d,0xf0,0x74,0x02,0x2f,0xf5,0x82,0xe4,0x34,0xfc,0xf5, ++0x83,0xe0,0xfe,0xe5,0x5b,0x2d,0x24,0x03,0xf5,0x82,0xe4,0x34,0xfc,0xf5,0x83,0xe0, ++0x24,0x00,0xff,0xe4,0x3e,0x90,0x9e,0x6e,0xf0,0xa3,0xef,0xf0,0x7f,0x04,0xe5,0x5b, ++0x25,0x5a,0x2f,0x24,0x00,0xf5,0x82,0xe4,0x34,0xfc,0xf5,0x83,0xe0,0xfe,0x74,0x6c, ++0x2f,0xf5,0x82,0xe4,0x34,0x9e,0xf5,0x83,0xee,0xf0,0x0f,0xbf,0x08,0xe0,0x51,0xa9, ++0xef,0x70,0x3f,0x90,0x01,0xc3,0xe0,0x60,0x25,0xc3,0xe5,0x60,0x94,0xe8,0xe5,0x5f, ++0x94,0x03,0x40,0x09,0x90,0x01,0xc6,0xe0,0x44,0x10,0xf0,0x80,0x63,0x05,0x60,0xe5, ++0x60,0x70,0x02,0x05,0x5f,0x7f,0x0a,0x7e,0x00,0x12,0x37,0x54,0x80,0xd5,0x90,0x01, ++0xc6,0xe0,0x90,0x01,0xc3,0x30,0xe2,0x05,0x74,0xfe,0xf0,0x80,0x43,0x74,0xff,0xf0, ++0x80,0x3e,0xe5,0x5b,0xb4,0x78,0x23,0xe4,0xf5,0x5b,0x05,0x5e,0xe5,0x5a,0x64,0x80, ++0x45,0x59,0x70,0x06,0xf5,0x59,0xf5,0x5a,0x80,0x06,0x75,0x59,0x00,0x75,0x5a,0x80, ++0xe5,0x5e,0xc3,0x13,0x90,0xfd,0x10,0xf0,0x80,0x06,0x74,0x08,0x25,0x5b,0xf5,0x5b, ++0xe5,0x5d,0x15,0x5d,0x70,0x02,0x15,0x5c,0xe5,0x5d,0x45,0x5c,0x60,0x02,0x81,0xc3, ++0xd0,0xd0,0x92,0xaf,0x22,0x90,0x06,0x34,0x74,0xff,0xf0,0xe4,0xa3,0xf0,0xa3,0xf0, ++0xa3,0xf0,0x22,0x22,0x8e,0x59,0x8f,0x5a,0x8b,0x5b,0x8a,0x5c,0x89,0x5d,0xe4,0x90, ++0x9e,0x34,0xf0,0xef,0x90,0x00,0x31,0xf0,0x12,0x4d,0x28,0xe5,0x59,0x54,0x03,0xff, ++0x90,0x00,0x32,0xe0,0x54,0xfc,0x4f,0xf0,0x12,0x4d,0x28,0x90,0x00,0x33,0xe0,0x54, ++0x7f,0xf0,0x12,0x4d,0x28,0x90,0x00,0x33,0xe0,0x20,0xe7,0x0e,0x90,0x9e,0x34,0xe0, ++0xc3,0x94,0x64,0x50,0x05,0xe0,0x04,0xf0,0x80,0xeb,0x90,0x9e,0x34,0xe0,0xc3,0x94, ++0x64,0x50,0x10,0x90,0x00,0x30,0xe0,0xab,0x5b,0xaa,0x5c,0xa9,0x5d,0x12,0x42,0x4d, ++0x7f,0x01,0x22,0x7f,0x00,0x22,0xe4,0xf5,0x25,0x22,0xe4,0x90,0x9e,0xaa,0xf0,0xa3, ++0xf0,0x90,0x05,0xf8,0xe0,0x70,0x0f,0xa3,0xe0,0x70,0x0b,0xa3,0xe0,0x70,0x07,0xa3, ++0xe0,0x70,0x03,0x7f,0x01,0x22,0xd3,0x90,0x9e,0xab,0xe0,0x94,0xe8,0x90,0x9e,0xaa, ++0xe0,0x94,0x03,0x40,0x03,0x7f,0x00,0x22,0x7f,0x32,0x7e,0x00,0x12,0x37,0x54,0x90, ++0x9e,0xaa,0xe4,0x75,0xf0,0x01,0x12,0x42,0x81,0x80,0xc6,0x7f,0x78,0x7e,0x08,0x12, ++0x27,0xde,0x90,0x9d,0xff,0x12,0x2a,0x7f,0x7f,0x04,0x7e,0x0c,0x12,0x27,0xde,0x90, ++0x9e,0x03,0x12,0x2a,0x7f,0x7f,0x00,0x7e,0x08,0x12,0x27,0xde,0x90,0x9e,0x07,0x12, ++0x2a,0x7f,0x90,0x9e,0x77,0xe0,0x90,0x9d,0xff,0xb4,0x01,0x0d,0x12,0x43,0x53,0xef, ++0x54,0xc7,0xff,0xed,0x54,0xc7,0xfd,0x80,0x07,0x12,0x43,0x53,0xef,0x54,0xc7,0xff, ++0xec,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0x78,0x7e,0x08,0x12,0x2f,0xd9,0x90,0x9e, ++0x03,0x12,0x43,0x53,0xef,0x54,0x0f,0xff,0xec,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f, ++0x04,0x7e,0x0c,0x12,0x2f,0xd9,0x90,0x9e,0x07,0x12,0x43,0x53,0xef,0x44,0x02,0xff, ++0xec,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0x00,0x7e,0x08,0x12,0x2f,0xd9,0x7f,0x70, ++0x7e,0x0e,0x12,0x27,0xde,0x90,0x9e,0x0b,0x12,0x2a,0x7f,0x90,0x80,0x85,0x12,0x2a, ++0x8b,0x00,0x1b,0x25,0xa0,0x7f,0x70,0x7e,0x0e,0x12,0x2f,0xd9,0x90,0x80,0x59,0x12, ++0x2a,0x8b,0x00,0x00,0x00,0x00,0xe4,0xfd,0xff,0x12,0x34,0x81,0x90,0x9e,0x77,0xe0, ++0xb4,0x01,0x11,0x90,0x80,0x59,0x12,0x2a,0x8b,0x00,0x00,0x00,0x00,0xe4,0xfd,0x7f, ++0x01,0x12,0x34,0x81,0x22,0x90,0x9e,0x77,0xe0,0x90,0x9e,0x0f,0xf0,0x22,0xef,0x70, ++0x03,0x02,0x78,0xe6,0x90,0x9e,0x0f,0xe0,0x60,0x03,0x02,0x7c,0xb1,0x90,0x9d,0xfb, ++0x12,0x43,0x53,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0x8c,0x7e,0x08,0x12,0x2f,0xd9, ++0x90,0x9d,0xa7,0x12,0x43,0x53,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0x44,0x7e,0x08, ++0x12,0x2f,0xd9,0x90,0x9d,0xab,0x12,0x43,0x53,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f, ++0x5c,0x7e,0x08,0x12,0x2f,0xd9,0x90,0x9d,0xaf,0x12,0x43,0x53,0x90,0x80,0x85,0x12, ++0x2a,0x7f,0x7f,0x6c,0x7e,0x0e,0x12,0x2f,0xd9,0x90,0x9d,0xb3,0x12,0x43,0x53,0x90, ++0x80,0x85,0x12,0x2a,0x7f,0x7f,0x70,0x7e,0x0e,0x12,0x2f,0xd9,0x90,0x9d,0xb7,0x12, ++0x43,0x53,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0x74,0x7e,0x0e,0x12,0x2f,0xd9,0x90, ++0x9d,0xbb,0x12,0x43,0x53,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0x78,0x7e,0x0e,0x12, ++0x2f,0xd9,0x90,0x9d,0xbf,0x12,0x43,0x53,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0x7c, ++0x7e,0x0e,0x12,0x2f,0xd9,0x90,0x9d,0xc3,0x12,0x43,0x53,0x90,0x80,0x85,0x12,0x2a, ++0x7f,0x7f,0x80,0x7e,0x0e,0x12,0x2f,0xd9,0x90,0x9d,0xc7,0x12,0x43,0x53,0x90,0x80, ++0x85,0x12,0x2a,0x7f,0x7f,0x84,0x7e,0x0e,0x12,0x2f,0xd9,0x90,0x9d,0xcb,0x12,0x43, ++0x53,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0x88,0x7e,0x0e,0x12,0x2f,0xd9,0x90,0x9d, ++0xcf,0x12,0x43,0x53,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0x8c,0x7e,0x0e,0x12,0x2f, ++0xd9,0x90,0x9d,0xd3,0x12,0x43,0x53,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0xd0,0x7e, ++0x0e,0x12,0x2f,0xd9,0x90,0x9d,0xd7,0x12,0x43,0x53,0x90,0x80,0x85,0x12,0x2a,0x7f, ++0x7f,0xd4,0x7e,0x0e,0x12,0x2f,0xd9,0x90,0x9d,0xdb,0x12,0x43,0x53,0x90,0x80,0x85, ++0x12,0x2a,0x7f,0x7f,0xd8,0x7e,0x0e,0x12,0x2f,0xd9,0x90,0x9d,0xdf,0x12,0x43,0x53, ++0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0xdc,0x7e,0x0e,0x12,0x2f,0xd9,0x90,0x9d,0xe3, ++0x12,0x43,0x53,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0xe0,0x7e,0x0e,0x12,0x2f,0xd9, ++0x90,0x9d,0xe7,0x12,0x43,0x53,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0xec,0x7e,0x0e, ++0x12,0x2f,0xd9,0x90,0x9d,0xeb,0x12,0x43,0x53,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f, ++0x04,0x7e,0x0c,0x12,0x2f,0xd9,0x90,0x9d,0xef,0x12,0x43,0x53,0x90,0x80,0x85,0x12, ++0x2a,0x7f,0x7f,0x04,0x7e,0x0d,0x12,0x2f,0xd9,0x90,0x9d,0xf3,0x12,0x43,0x53,0x90, ++0x80,0x85,0x12,0x2a,0x7f,0x7f,0x0c,0x7e,0x09,0x12,0x2f,0xd9,0x90,0x9d,0xf7,0x12, ++0x43,0x53,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0x04,0x7e,0x08,0x12,0x2f,0xd9,0x90, ++0x9e,0x0f,0x74,0x01,0xf0,0x22,0x90,0x9e,0x0f,0xe0,0x64,0x01,0x60,0x02,0x81,0xb1, ++0x7f,0x8c,0x7e,0x08,0x12,0x27,0xde,0x90,0x9d,0xfb,0x12,0x2a,0x7f,0x7f,0x44,0x7e, ++0x08,0x12,0x27,0xde,0x90,0x9d,0xa7,0x12,0x2a,0x7f,0x7f,0x5c,0x7e,0x08,0x12,0x27, ++0xde,0x90,0x9d,0xab,0x12,0x2a,0x7f,0x7f,0x6c,0x7e,0x0e,0x12,0x27,0xde,0x90,0x9d, ++0xaf,0x12,0x2a,0x7f,0x7f,0x70,0x7e,0x0e,0x12,0x27,0xde,0x90,0x9d,0xb3,0x12,0x2a, ++0x7f,0x7f,0x74,0x7e,0x0e,0x12,0x27,0xde,0x90,0x9d,0xb7,0x12,0x2a,0x7f,0x7f,0x78, ++0x7e,0x0e,0x12,0x27,0xde,0x90,0x9d,0xbb,0x12,0x2a,0x7f,0x7f,0x7c,0x7e,0x0e,0x12, ++0x27,0xde,0x90,0x9d,0xbf,0x12,0x2a,0x7f,0x7f,0x80,0x7e,0x0e,0x12,0x27,0xde,0x90, ++0x9d,0xc3,0x12,0x2a,0x7f,0x7f,0x84,0x7e,0x0e,0x12,0x27,0xde,0x90,0x9d,0xc7,0x12, ++0x2a,0x7f,0x7f,0x88,0x7e,0x0e,0x12,0x27,0xde,0x90,0x9d,0xcb,0x12,0x2a,0x7f,0x7f, ++0x8c,0x7e,0x0e,0x12,0x27,0xde,0x90,0x9d,0xcf,0x12,0x2a,0x7f,0x7f,0xd0,0x7e,0x0e, ++0x12,0x27,0xde,0x90,0x9d,0xd3,0x12,0x2a,0x7f,0x7f,0xd4,0x7e,0x0e,0x12,0x27,0xde, ++0x90,0x9d,0xd7,0x12,0x2a,0x7f,0x7f,0xd8,0x7e,0x0e,0x12,0x27,0xde,0x90,0x9d,0xdb, ++0x12,0x2a,0x7f,0x7f,0xdc,0x7e,0x0e,0x12,0x27,0xde,0x90,0x9d,0xdf,0x12,0x2a,0x7f, ++0x7f,0xe0,0x7e,0x0e,0x12,0x27,0xde,0x90,0x9d,0xe3,0x12,0x2a,0x7f,0x7f,0xec,0x7e, ++0x0e,0x12,0x27,0xde,0x90,0x9d,0xe7,0x12,0x2a,0x7f,0x7f,0x04,0x7e,0x0c,0x12,0x27, ++0xde,0x90,0x9d,0xeb,0x12,0x2a,0x7f,0x7f,0x04,0x7e,0x0d,0x12,0x27,0xde,0x90,0x9d, ++0xef,0x12,0x2a,0x7f,0x7f,0x0c,0x7e,0x09,0x12,0x27,0xde,0x90,0x9d,0xf3,0x12,0x2a, ++0x7f,0x7f,0x04,0x7e,0x08,0x12,0x27,0xde,0x90,0x9d,0xf7,0x12,0x2a,0x7f,0x7f,0x8c, ++0x7e,0x08,0x12,0x27,0xde,0x90,0x9e,0xa4,0x12,0x2a,0x7f,0x90,0x9e,0xa4,0x12,0x43, ++0x53,0xed,0x44,0xc0,0xfd,0xec,0x90,0x9e,0xa4,0x12,0x2a,0x7f,0x90,0x9e,0xa4,0x12, ++0x43,0x53,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0x8c,0x7e,0x08,0x12,0x2f,0xd9,0x90, ++0x80,0x85,0x12,0x2a,0x8b,0x00,0x01,0x00,0x00,0x7f,0x44,0x7e,0x08,0x12,0x2f,0xd9, ++0x90,0x80,0x85,0x12,0x2a,0x8b,0x00,0xdb,0x25,0xa4,0x7f,0x5c,0x7e,0x08,0x12,0x2f, ++0xd9,0x90,0x80,0x85,0x12,0x2a,0x8b,0x20,0xdb,0x25,0xa4,0x7f,0x6c,0x7e,0x0e,0x12, ++0x2f,0xd9,0x90,0x80,0x85,0x12,0x2a,0x8b,0x20,0xdb,0x25,0xa4,0x7f,0x70,0x7e,0x0e, ++0x12,0x2f,0xd9,0x90,0x80,0x85,0x12,0x2a,0x8b,0x04,0x1b,0x25,0xa4,0x7f,0x74,0x7e, ++0x0e,0x12,0x2f,0xd9,0x90,0x80,0x85,0x12,0x2a,0x8b,0x04,0x1b,0x25,0xa4,0x7f,0x78, ++0x7e,0x0e,0x12,0x2f,0xd9,0x90,0x80,0x85,0x12,0x2a,0x8b,0x04,0x1b,0x25,0xa4,0x7f, ++0x7c,0x7e,0x0e,0x12,0x2f,0xd9,0x90,0x80,0x85,0x12,0x2a,0x8b,0x04,0x1b,0x25,0xa4, ++0x7f,0x80,0x7e,0x0e,0x12,0x2f,0xd9,0x90,0x80,0x85,0x12,0x2a,0x8b,0x63,0xdb,0x25, ++0xa4,0x7f,0x84,0x7e,0x0e,0x12,0x2f,0xd9,0x90,0x80,0x85,0x12,0x2a,0x8b,0x04,0x1b, ++0x25,0xa4,0x7f,0x88,0x7e,0x0e,0x12,0x2f,0xd9,0x90,0x80,0x85,0x12,0x2a,0x8b,0x20, ++0xdb,0x25,0xa4,0x7f,0x8c,0x7e,0x0e,0x12,0x2f,0xd9,0x90,0x80,0x85,0x12,0x2a,0x8b, ++0x20,0xdb,0x25,0xa4,0x7f,0xd0,0x7e,0x0e,0x12,0x2f,0xd9,0x90,0x80,0x85,0x12,0x2a, ++0x8b,0x20,0xdb,0x25,0xa4,0x7f,0xd4,0x7e,0x0e,0x12,0x2f,0xd9,0x90,0x80,0x85,0x12, ++0x2a,0x8b,0x20,0xdb,0x25,0xa4,0x7f,0xd8,0x7e,0x0e,0x12,0x2f,0xd9,0x90,0x80,0x85, ++0x12,0x2a,0x8b,0x00,0x1b,0x25,0xa4,0x7f,0xdc,0x7e,0x0e,0x12,0x2f,0xd9,0x90,0x80, ++0x85,0x12,0x2a,0x8b,0x00,0x1b,0x25,0xa4,0x7f,0xe0,0x7e,0x0e,0x12,0x2f,0xd9,0x90, ++0x80,0x85,0x12,0x2a,0x8b,0x24,0xdb,0x25,0xa4,0x7f,0xec,0x7e,0x0e,0x12,0x2f,0xd9, ++0x7f,0x04,0x7e,0x0c,0x12,0x27,0xde,0x90,0x9e,0xa4,0x12,0x2a,0x7f,0x90,0x9e,0xa4, ++0x12,0x43,0x53,0xe4,0xff,0xec,0x90,0x9e,0xa4,0x12,0x2a,0x7f,0x90,0x9e,0xa4,0x12, ++0x43,0x53,0xef,0x44,0x11,0xff,0xec,0x90,0x9e,0xa4,0x12,0x2a,0x7f,0x90,0x9e,0xa4, ++0x12,0x43,0x53,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0x04,0x7e,0x0c,0x12,0x2f,0xd9, ++0x7f,0x04,0x7e,0x0d,0x12,0x27,0xde,0x90,0x9e,0xa4,0x12,0x2a,0x7f,0x90,0x9e,0xa4, ++0x12,0x43,0x53,0xef,0x54,0xf0,0xff,0xec,0x90,0x9e,0xa4,0x12,0x2a,0x7f,0x90,0x9e, ++0xa4,0x12,0x43,0x53,0xef,0x44,0x01,0xff,0xec,0x90,0x9e,0xa4,0x12,0x2a,0x7f,0x90, ++0x9e,0xa4,0x12,0x43,0x53,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0x04,0x7e,0x0d,0x12, ++0x2f,0xd9,0x7f,0x0c,0x7e,0x09,0x12,0x27,0xde,0x90,0x9e,0xa4,0x12,0x2a,0x7f,0x90, ++0x9e,0xa4,0x12,0x43,0x53,0xe4,0xff,0xec,0x90,0x9e,0xa4,0x12,0x2a,0x7f,0x90,0x9e, ++0xa4,0x12,0x43,0x53,0xef,0x44,0x11,0xff,0xec,0x90,0x9e,0xa4,0x12,0x2a,0x7f,0x90, ++0x9e,0xa4,0x12,0x43,0x53,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0x0c,0x7e,0x09,0x12, ++0x2f,0xd9,0x7f,0x0c,0x7e,0x09,0x12,0x27,0xde,0x90,0x9e,0xa4,0x12,0x2a,0x7f,0x90, ++0x9e,0xa4,0x12,0x43,0x53,0xed,0x54,0x0f,0xfd,0xec,0x54,0xf0,0xfc,0x90,0x9e,0xa4, ++0x12,0x2a,0x7f,0x90,0x9e,0xa4,0x12,0x43,0x53,0xed,0x44,0x10,0xfd,0xec,0x44,0x01, ++0xfc,0x90,0x9e,0xa4,0x12,0x2a,0x7f,0x90,0x9e,0xa4,0x12,0x43,0x53,0x90,0x80,0x85, ++0x12,0x2a,0x7f,0x7f,0x0c,0x7e,0x09,0x12,0x2f,0xd9,0x7f,0x04,0x7e,0x08,0x12,0x27, ++0xde,0x90,0x9e,0xa4,0x12,0x2a,0x7f,0x90,0x9e,0xa4,0x12,0x43,0x53,0xef,0x54,0xf0, ++0xff,0xec,0x90,0x9e,0xa4,0x12,0x2a,0x7f,0x90,0x9e,0xa4,0x12,0x43,0x53,0xef,0x44, ++0x01,0xff,0xec,0x90,0x9e,0xa4,0x12,0x2a,0x7f,0x90,0x9e,0xa4,0x12,0x43,0x53,0x90, ++0x80,0x85,0x12,0x2a,0x7f,0x7f,0x04,0x7e,0x08,0x12,0x2f,0xd9,0xe4,0x90,0x9e,0x0f, ++0xf0,0x22,0x90,0x00,0x02,0x12,0x42,0x20,0x90,0x9e,0x1e,0xf0,0xe0,0x60,0x04,0xe0, ++0xf4,0x70,0x21,0xa2,0xaf,0xe4,0x33,0xf5,0x59,0xc2,0xaf,0x90,0x00,0x47,0xe0,0x54, ++0xfb,0xfd,0x7f,0x47,0x12,0x4e,0x30,0x7d,0x40,0x7f,0x01,0x12,0x36,0xaf,0xe5,0x59, ++0x24,0xff,0x92,0xaf,0x22,0xe4,0xfd,0x7f,0x45,0x12,0x4e,0x30,0x90,0x04,0xfd,0xe4, ++0xf0,0xa3,0xf0,0x90,0x9e,0x1e,0xf0,0x90,0x9e,0x24,0xf0,0x90,0x9e,0x27,0xf0,0x90, ++0x9e,0x25,0xf0,0x90,0x9e,0x28,0xf0,0x90,0x9e,0x26,0xf0,0x90,0x9e,0x29,0xf0,0x90, ++0x9e,0x10,0x04,0xf0,0xe4,0xa3,0xf0,0xa3,0xf0,0xa3,0xf0,0x90,0x9e,0x15,0xf0,0x90, ++0x9e,0x1a,0xf0,0x90,0x9e,0x1c,0xf0,0x90,0x9e,0x2e,0xf0,0x90,0x9e,0x1f,0xf0,0x90, ++0x9e,0x1b,0xf0,0x90,0x9e,0x14,0xf0,0x90,0x00,0x51,0xe0,0x44,0xc0,0xfd,0x7f,0x51, ++0x02,0x4e,0x30,0x90,0x9e,0x2e,0xe0,0x64,0x01,0x60,0x08,0x90,0x9e,0x1c,0xe0,0x60, ++0x02,0xc1,0x1a,0x90,0x9e,0x10,0xe0,0xc3,0x94,0xff,0x50,0x05,0xe0,0x04,0xf0,0x80, ++0x3b,0x90,0x9e,0x11,0xe0,0xc3,0x94,0xff,0x50,0x06,0xe0,0x04,0xf0,0xe4,0x80,0x28, ++0x90,0x9e,0x12,0xe0,0xc3,0x94,0xff,0x50,0x0a,0xe0,0x04,0xf0,0xe4,0x90,0x9e,0x11, ++0xf0,0x80,0x15,0x90,0x9e,0x13,0xe0,0xc3,0x94,0xff,0x50,0x10,0xe0,0x04,0xf0,0xe4, ++0x90,0x9e,0x12,0xf0,0x90,0x9e,0x11,0xf0,0x90,0x9e,0x10,0xf0,0x90,0x00,0x44,0xe0, ++0x54,0x0c,0x60,0x76,0xe0,0x30,0xe2,0x32,0x90,0x9e,0x24,0xe0,0xc3,0x94,0xff,0x50, ++0x05,0xe0,0x04,0xf0,0x80,0x24,0x90,0x9e,0x25,0xe0,0xc3,0x94,0xff,0x50,0x06,0xe0, ++0x04,0xf0,0xe4,0x80,0x11,0x90,0x9e,0x26,0xe0,0xc3,0x94,0xff,0x50,0x0c,0xe0,0x04, ++0xf0,0xe4,0x90,0x9e,0x25,0xf0,0x90,0x9e,0x24,0xf0,0x90,0x00,0x44,0xe0,0x30,0xe3, ++0x32,0x90,0x9e,0x27,0xe0,0xc3,0x94,0xff,0x50,0x05,0xe0,0x04,0xf0,0x80,0x24,0x90, ++0x9e,0x28,0xe0,0xc3,0x94,0xff,0x50,0x06,0xe0,0x04,0xf0,0xe4,0x80,0x11,0x90,0x9e, ++0x29,0xe0,0xc3,0x94,0xff,0x50,0x0c,0xe0,0x04,0xf0,0xe4,0x90,0x9e,0x28,0xf0,0x90, ++0x9e,0x27,0xf0,0x90,0x04,0xfd,0xe0,0x44,0x01,0xf0,0x22,0x90,0x00,0x02,0x12,0x42, ++0x20,0x90,0x9e,0x1c,0xf0,0x90,0x00,0x01,0x12,0x42,0x20,0x25,0xe0,0x25,0xe0,0x90, ++0x9e,0x1b,0xf0,0x12,0x29,0xd9,0x25,0xe0,0x25,0xe0,0x90,0x9e,0x1f,0xf0,0x90,0x05, ++0x60,0xe0,0x90,0x9e,0x2a,0xf0,0x90,0x05,0x61,0xe0,0x90,0x9e,0x2b,0xf0,0x90,0x05, ++0x62,0xe0,0x90,0x9e,0x2c,0xf0,0x90,0x05,0x63,0xe0,0x90,0x9e,0x2d,0xf0,0xa2,0xaf, ++0xe4,0x33,0x90,0x9e,0x3f,0xf0,0xc2,0xaf,0x90,0x9e,0x1b,0xe0,0xff,0x12,0x52,0x17, ++0x90,0x9e,0x3f,0xe0,0x24,0xff,0x92,0xaf,0x90,0x9e,0x1c,0xe0,0x70,0x02,0xe1,0x25, ++0x90,0x9e,0x1b,0xe0,0x70,0x02,0xe1,0x25,0x90,0x9e,0x1f,0xe0,0x70,0x02,0xe1,0x25, ++0xa2,0xaf,0xe4,0x33,0x90,0x9e,0x3f,0xf0,0xc2,0xaf,0x90,0x9e,0x2e,0x74,0x01,0xf0, ++0x90,0x9e,0x3f,0xe0,0x24,0xff,0x92,0xaf,0x12,0x4e,0x27,0x90,0x00,0x46,0xe0,0x44, ++0x01,0xfd,0x7f,0x46,0x12,0x4e,0x30,0x90,0x9e,0x14,0xe0,0x60,0x15,0x90,0x9e,0x20, ++0x12,0x43,0x53,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0x80,0x7e,0x08,0x12,0x2f,0xd9, ++0x80,0x06,0x90,0x05,0x22,0x74,0x7f,0xf0,0x90,0x00,0x45,0xe0,0x54,0xef,0xfd,0x7f, ++0x45,0x12,0x4e,0x30,0x90,0x05,0x87,0xe0,0x64,0x80,0xf0,0x90,0x9e,0x2a,0xe0,0x90, ++0x05,0x84,0xf0,0x90,0x9e,0x2b,0xe0,0x90,0x05,0x85,0xf0,0x90,0x9e,0x2c,0xe0,0x90, ++0x05,0x86,0xf0,0x90,0x9e,0x2d,0xe0,0x90,0x05,0x87,0xf0,0xa2,0xaf,0xe4,0x33,0x90, ++0x9e,0x3f,0xf0,0xc2,0xaf,0x90,0x01,0x3c,0xe0,0x44,0x20,0xf0,0x7d,0x20,0xe4,0xff, ++0x12,0x37,0x00,0x80,0x2d,0x90,0x9e,0x1c,0xe0,0x70,0x2f,0x90,0x9e,0x2e,0x12,0x4e, ++0x26,0x90,0x00,0x46,0xe0,0x54,0xfe,0xfd,0x7f,0x46,0x12,0x4e,0x30,0x90,0x05,0x22, ++0xe4,0xf0,0xa2,0xaf,0x33,0x90,0x9e,0x3f,0xf0,0xc2,0xaf,0x7d,0x20,0xe4,0xff,0x12, ++0x36,0x92,0x90,0x9e,0x3f,0xe0,0x24,0xff,0x92,0xaf,0x22,0x00,0x0e,0x56,}; ++#else ++ ++ ++// =================== v80 TSMC COMMON 2011-12-14 ======================= ++u8 Rtl8192CUFwTSMCImgArray[TSMCImgArrayLength] = { ++0xc1,0x88,0x02,0x00,0x50,0x00,0x00,0x00,0x12,0x14,0x15,0x52,0xd4,0x3e,0x00,0x00, ++0x25,0x86,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x02,0x43,0xba,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x02,0x48,0x79,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x02,0x5e,0xff,0x00,0x00,0x00,0x00,0x00,0xa1,0xd4,0x00,0x00,0x00, ++0x05,0x04,0x03,0x02,0x00,0x03,0x06,0x05,0x04,0x03,0x00,0x04,0x06,0x05,0x04,0x02, ++0x00,0x04,0x08,0x07,0x06,0x04,0x00,0x06,0x0a,0x09,0x08,0x06,0x00,0x08,0x0a,0x09, ++0x08,0x04,0x00,0x08,0x0a,0x09,0x08,0x02,0x00,0x08,0x0a,0x09,0x08,0x00,0x00,0x08, ++0x12,0x11,0x10,0x08,0x00,0x10,0x1a,0x19,0x18,0x10,0x00,0x18,0x22,0x21,0x20,0x18, ++0x00,0x20,0x22,0x21,0x20,0x10,0x00,0x20,0x22,0x21,0x20,0x08,0x00,0x20,0x22,0x21, ++0x1c,0x08,0x00,0x20,0x22,0x21,0x14,0x08,0x00,0x20,0x22,0x20,0x18,0x08,0x00,0x20, ++0x31,0x30,0x20,0x10,0x00,0x30,0x31,0x30,0x18,0x00,0x00,0x30,0x31,0x2f,0x10,0x10, ++0x00,0x30,0x31,0x2c,0x10,0x10,0x00,0x30,0x31,0x28,0x10,0x00,0x00,0x30,0x31,0x20, ++0x10,0x00,0x00,0x30,0x31,0x10,0x10,0x00,0x00,0x30,0x04,0x04,0x04,0x05,0x04,0x04, ++0x04,0x05,0x05,0x05,0x06,0x06,0x04,0x04,0x04,0x05,0x05,0x05,0x06,0x06,0x04,0x04, ++0x05,0x05,0x05,0x05,0x06,0x06,0x04,0x04,0x05,0x05,0x05,0x05,0x06,0x07,0x0a,0x0b, ++0x0d,0x10,0x04,0x05,0x05,0x06,0x06,0x09,0x0c,0x11,0x08,0x08,0x09,0x09,0x0a,0x0c, ++0x10,0x11,0x04,0x04,0x04,0x05,0x04,0x04,0x05,0x07,0x07,0x07,0x08,0x0a,0x04,0x04, ++0x04,0x04,0x06,0x0a,0x0b,0x0d,0x05,0x05,0x07,0x07,0x08,0x0b,0x0d,0x0f,0x04,0x04, ++0x04,0x05,0x07,0x07,0x09,0x09,0x0c,0x0e,0x10,0x12,0x04,0x04,0x05,0x05,0x06,0x0a, ++0x11,0x13,0x09,0x09,0x09,0x09,0x0c,0x0e,0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x24,0x26,0x2a,0x18,0x1a,0x1d,0x1f,0x21,0x27,0x29,0x2a,0x00,0x00, ++0x00,0x1f,0x23,0x28,0x2a,0x2c,0x00,0x04,0x00,0x04,0x00,0x08,0x00,0x10,0x00,0x18, ++0x00,0x24,0x00,0x30,0x00,0x48,0x00,0x60,0x00,0x90,0x00,0xc0,0x00,0xd8,0x00,0x50, ++0x00,0x78,0x00,0xa0,0x00,0xc8,0x01,0x40,0x01,0x90,0x01,0xe0,0x02,0x30,0x01,0x2c, ++0x01,0x40,0x01,0xe0,0x02,0xd0,0x03,0xe8,0x04,0xb0,0x06,0x40,0x07,0xd0,0x00,0x02, ++0x00,0x02,0x00,0x04,0x00,0x08,0x00,0x0c,0x00,0x12,0x00,0x18,0x00,0x24,0x00,0x30, ++0x00,0x48,0x00,0x60,0x00,0x6c,0x00,0x28,0x00,0x3c,0x00,0x50,0x00,0x64,0x00,0xa0, ++0x00,0xc8,0x00,0xf0,0x01,0x18,0x00,0x64,0x00,0xa0,0x00,0xf0,0x01,0x68,0x01,0xf4, ++0x02,0x58,0x03,0x20,0x03,0xe8,0x02,0x02,0x02,0x02,0x02,0x02,0x03,0x03,0x04,0x04, ++0x05,0x07,0x04,0x04,0x07,0x0a,0x0a,0x0c,0x0c,0x12,0x05,0x07,0x07,0x08,0x0b,0x12, ++0x24,0x3c,0x01,0x01,0x01,0x01,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x01,0x02, ++0x03,0x04,0x05,0x06,0x07,0x08,0x05,0x06,0x07,0x08,0x09,0x0a,0x0b,0x0c,0x20,0x1e, ++0x1c,0x18,0x10,0x18,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0xbb,0x01,0x0c,0xe5,0x82,0x29,0xf5,0x82,0xe5,0x83,0x3a,0xf5,0x83,0xe0,0x22,0x50, ++0x06,0xe9,0x25,0x82,0xf8,0xe6,0x22,0xbb,0xfe,0x06,0xe9,0x25,0x82,0xf8,0xe2,0x22, ++0xe5,0x82,0x29,0xf5,0x82,0xe5,0x83,0x3a,0xf5,0x83,0xe4,0x93,0x22,0xbb,0x01,0x06, ++0x89,0x82,0x8a,0x83,0xf0,0x22,0x50,0x02,0xf7,0x22,0xbb,0xfe,0x01,0xf3,0x22,0xf8, ++0xbb,0x01,0x0d,0xe5,0x82,0x29,0xf5,0x82,0xe5,0x83,0x3a,0xf5,0x83,0xe8,0xf0,0x22, ++0x50,0x06,0xe9,0x25,0x82,0xc8,0xf6,0x22,0xbb,0xfe,0x05,0xe9,0x25,0x82,0xc8,0xf2, ++0x22,0xc5,0xf0,0xf8,0xa3,0xe0,0x28,0xf0,0xc5,0xf0,0xf8,0xe5,0x82,0x15,0x82,0x70, ++0x02,0x15,0x83,0xe0,0x38,0xf0,0x22,0xbb,0x01,0x0a,0x89,0x82,0x8a,0x83,0xe0,0xf5, ++0xf0,0xa3,0xe0,0x22,0x50,0x06,0x87,0xf0,0x09,0xe7,0x19,0x22,0xbb,0xfe,0x07,0xe3, ++0xf5,0xf0,0x09,0xe3,0x19,0x22,0x89,0x82,0x8a,0x83,0xe4,0x93,0xf5,0xf0,0x74,0x01, ++0x93,0x22,0xbb,0x01,0x10,0xe5,0x82,0x29,0xf5,0x82,0xe5,0x83,0x3a,0xf5,0x83,0xe0, ++0xf5,0xf0,0xa3,0xe0,0x22,0x50,0x09,0xe9,0x25,0x82,0xf8,0x86,0xf0,0x08,0xe6,0x22, ++0xbb,0xfe,0x0a,0xe9,0x25,0x82,0xf8,0xe2,0xf5,0xf0,0x08,0xe2,0x22,0xe5,0x83,0x2a, ++0xf5,0x83,0xe9,0x93,0xf5,0xf0,0xa3,0xe9,0x93,0x22,0xbb,0x01,0x0a,0x89,0x82,0x8a, ++0x83,0xf0,0xe5,0xf0,0xa3,0xf0,0x22,0x50,0x06,0xf7,0x09,0xa7,0xf0,0x19,0x22,0xbb, ++0xfe,0x06,0xf3,0xe5,0xf0,0x09,0xf3,0x19,0x22,0xf8,0xbb,0x01,0x11,0xe5,0x82,0x29, ++0xf5,0x82,0xe5,0x83,0x3a,0xf5,0x83,0xe8,0xf0,0xe5,0xf0,0xa3,0xf0,0x22,0x50,0x09, ++0xe9,0x25,0x82,0xc8,0xf6,0x08,0xa6,0xf0,0x22,0xbb,0xfe,0x09,0xe9,0x25,0x82,0xc8, ++0xf2,0xe5,0xf0,0x08,0xf2,0x22,0xef,0x4b,0xff,0xee,0x4a,0xfe,0xed,0x49,0xfd,0xec, ++0x48,0xfc,0x22,0xe0,0xfc,0xa3,0xe0,0xfd,0xa3,0xe0,0xfe,0xa3,0xe0,0xff,0x22,0xa4, ++0x25,0x82,0xf5,0x82,0xe5,0xf0,0x35,0x83,0xf5,0x83,0x22,0xe0,0xfb,0xa3,0xe0,0xfa, ++0xa3,0xe0,0xf9,0x22,0xf8,0xe0,0xfb,0xa3,0xa3,0xe0,0xf9,0x25,0xf0,0xf0,0xe5,0x82, ++0x15,0x82,0x70,0x02,0x15,0x83,0xe0,0xfa,0x38,0xf0,0x22,0xeb,0xf0,0xa3,0xea,0xf0, ++0xa3,0xe9,0xf0,0x22,0xd0,0x83,0xd0,0x82,0xf8,0xe4,0x93,0x70,0x12,0x74,0x01,0x93, ++0x70,0x0d,0xa3,0xa3,0x93,0xf8,0x74,0x01,0x93,0xf5,0x82,0x88,0x83,0xe4,0x73,0x74, ++0x02,0x93,0x68,0x60,0xef,0xa3,0xa3,0xa3,0x80,0xdf,0x02,0x43,0xf8,0x02,0x50,0x2e, ++0xe4,0x93,0xa3,0xf8,0xe4,0x93,0xa3,0x40,0x03,0xf6,0x80,0x01,0xf2,0x08,0xdf,0xf4, ++0x80,0x29,0xe4,0x93,0xa3,0xf8,0x54,0x07,0x24,0x0c,0xc8,0xc3,0x33,0xc4,0x54,0x0f, ++0x44,0x20,0xc8,0x83,0x40,0x04,0xf4,0x56,0x80,0x01,0x46,0xf6,0xdf,0xe4,0x80,0x0b, ++0x01,0x02,0x04,0x08,0x10,0x20,0x40,0x80,0x90,0x44,0x3d,0xe4,0x7e,0x01,0x93,0x60, ++0xbc,0xa3,0xff,0x54,0x3f,0x30,0xe5,0x09,0x54,0x1f,0xfe,0xe4,0x93,0xa3,0x60,0x01, ++0x0e,0xcf,0x54,0xc0,0x25,0xe0,0x60,0xa8,0x40,0xb8,0xe4,0x93,0xa3,0xfa,0xe4,0x93, ++0xa3,0xf8,0xe4,0x93,0xa3,0xc8,0xc5,0x82,0xc8,0xca,0xc5,0x83,0xca,0xf0,0xa3,0xc8, ++0xc5,0x82,0xc8,0xca,0xc5,0x83,0xca,0xdf,0xe9,0xde,0xe7,0x80,0xbe,0x41,0x9e,0x4f, ++0x00,0x41,0x9e,0xad,0x00,0x41,0x9e,0x61,0x80,0x41,0x9e,0x62,0x80,0x41,0x9e,0xaf, ++0x00,0x00,0xf0,0x90,0x9e,0x6b,0xe0,0x90,0x9e,0x87,0xf0,0xe4,0xfb,0xfd,0x7f,0x54, ++0x7e,0x01,0xd3,0x10,0xaf,0x01,0xc3,0xc0,0xd0,0x90,0x9e,0x85,0xeb,0xf0,0xa3,0xe0, ++0xfb,0xa3,0xe0,0xf5,0x44,0xe4,0xf5,0x45,0x12,0x35,0xab,0xd0,0xd0,0x92,0xaf,0x22, ++0x90,0x01,0x5f,0xe4,0xf0,0x90,0x01,0x3c,0x74,0x08,0xf0,0xe4,0x90,0x9e,0x86,0xf0, ++0x90,0x9e,0x69,0xe0,0x90,0x9e,0x87,0xf0,0xe4,0xfb,0xfd,0x7f,0x5c,0x7e,0x01,0x91, ++0x62,0x90,0x01,0x5f,0x74,0x05,0xf0,0x90,0x06,0x92,0x74,0x02,0xf0,0x90,0x9e,0x70, ++0x14,0xf0,0xe5,0x23,0x54,0x0f,0xc3,0x94,0x0c,0x50,0x02,0xf1,0x2b,0x22,0x8f,0x82, ++0x8e,0x83,0xa3,0xa3,0xa3,0xe4,0xf0,0x22,0xe4,0xf5,0x71,0x7f,0x60,0x7e,0x01,0x80, ++0xed,0x7d,0x01,0xaf,0x24,0xe1,0x2f,0xb1,0xa6,0xbf,0x01,0x0f,0x90,0x9e,0x51,0xe0, ++0xff,0xe4,0xfd,0xf1,0xd0,0x90,0x04,0x1f,0x74,0x20,0xf0,0x22,0x53,0x23,0xf0,0x43, ++0x23,0x01,0x91,0xfd,0x91,0xfe,0x53,0x23,0xf0,0x43,0x23,0x02,0x22,0x22,0x22,0x22, ++0x22,0x00,0x00,0x02,0x5f,0x91,0x02,0x5f,0x98,0xd3,0x10,0xaf,0x01,0xc3,0xc0,0xd0, ++0x8b,0x1b,0x8a,0x1c,0x89,0x1d,0x90,0x9e,0x88,0x71,0x8b,0xab,0x1e,0xaa,0x1f,0xa9, ++0x20,0x90,0x9e,0x8b,0x71,0x8b,0xaf,0x21,0x15,0x21,0xef,0x60,0x1b,0x90,0x9e,0x8b, ++0xe4,0x75,0xf0,0x01,0x71,0x74,0x12,0x29,0xd9,0xff,0x90,0x9e,0x88,0xe4,0x75,0xf0, ++0x01,0x71,0x74,0xef,0x51,0x4d,0x80,0xde,0xab,0x1b,0xaa,0x1c,0xa9,0x1d,0xd0,0xd0, ++0x92,0xaf,0x22,0x90,0x06,0xa9,0xe0,0x90,0x9e,0x2f,0xf0,0xe0,0x54,0xc0,0x70,0x08, ++0x53,0x26,0xfe,0x53,0x26,0xfd,0x91,0xd1,0x90,0x9e,0x2f,0xe0,0x30,0xe6,0x13,0x43, ++0x26,0x01,0x90,0x9e,0x73,0xe0,0x64,0x02,0x60,0x04,0x91,0xd7,0x80,0x07,0x91,0x80, ++0x80,0x03,0x53,0x26,0xfe,0x90,0x9e,0x2f,0xe0,0x30,0xe7,0x16,0x43,0x26,0x02,0xe4, ++0x90,0x9e,0x86,0x91,0x52,0x90,0x01,0x57,0x74,0x05,0xf0,0x90,0x9e,0x74,0x74,0x01, ++0xf0,0x22,0x53,0x26,0xfd,0x22,0xd3,0x10,0xaf,0x01,0xc3,0xc0,0xd0,0x90,0x04,0x1d, ++0xe0,0x60,0x1a,0x90,0x05,0x22,0xe0,0x54,0x90,0x60,0x07,0x90,0x01,0xc6,0xe0,0x44, ++0x40,0xf0,0x90,0x01,0xc7,0xe0,0x30,0xe1,0xe4,0x7f,0x00,0x80,0x02,0x7f,0x01,0xd0, ++0xd0,0x92,0xaf,0x22,0xc0,0xe0,0xc0,0xf0,0xc0,0x83,0xc0,0x82,0xc0,0xd0,0x75,0xd0, ++0x00,0xc0,0x00,0xc0,0x01,0xc0,0x02,0xc0,0x03,0xc0,0x04,0xc0,0x05,0xc0,0x06,0xc0, ++0x07,0x90,0x01,0xc4,0x74,0xd4,0xf0,0x74,0x45,0xa3,0xf0,0x53,0x91,0xdf,0x90,0x01, ++0x3c,0xe0,0x55,0x30,0xf5,0x34,0xa3,0xe0,0x55,0x31,0xf5,0x35,0xa3,0xe0,0x55,0x32, ++0xf5,0x36,0xa3,0xe0,0x55,0x33,0xf5,0x37,0xe5,0x34,0x30,0xe0,0x06,0x90,0x01,0x3c, ++0x74,0x01,0xf0,0xe5,0x34,0x30,0xe1,0x09,0x90,0x01,0x3c,0x74,0x02,0xf0,0x12,0x66, ++0x09,0xe5,0x34,0x30,0xe2,0x38,0x90,0x01,0x3c,0x74,0x04,0xf0,0x90,0x06,0x92,0xe0, ++0x30,0xe0,0x24,0x90,0x9e,0x86,0xe4,0xf0,0x90,0x9e,0x69,0xe0,0x90,0x9e,0x87,0xf0, ++0xe4,0xfb,0xfd,0x7f,0x58,0x7e,0x01,0x91,0x62,0x90,0x01,0x5b,0x74,0x05,0xf0,0x90, ++0x06,0x92,0x74,0x01,0xf0,0x80,0x07,0x90,0x9e,0x71,0xe4,0xf0,0x91,0xd1,0xe5,0x34, ++0x30,0xe3,0x38,0x90,0x01,0x3c,0x74,0x08,0xf0,0x90,0x06,0x92,0xe0,0x30,0xe1,0x24, ++0x90,0x9e,0x86,0xe4,0xf0,0x90,0x9e,0x69,0xe0,0x90,0x9e,0x87,0xf0,0xe4,0xfb,0xfd, ++0x7f,0x5c,0x7e,0x01,0x91,0x62,0x90,0x01,0x5f,0x74,0x05,0xf0,0x90,0x06,0x92,0x74, ++0x02,0xf0,0x80,0x07,0x90,0x9e,0x70,0xe4,0xf0,0x91,0xd1,0xe5,0x34,0x30,0xe4,0x09, ++0x90,0x01,0x3c,0x74,0x10,0xf0,0x12,0x73,0x66,0xe5,0x34,0x30,0xe5,0x09,0x90,0x01, ++0x3c,0x74,0x20,0xf0,0x12,0x52,0x64,0xe5,0x35,0x30,0xe0,0x18,0x90,0x01,0x3d,0x74, ++0x01,0xf0,0x90,0x01,0x2f,0xe0,0x44,0x7f,0xf0,0x90,0x00,0x83,0xe0,0xf5,0x24,0x12, ++0x64,0xe3,0x91,0xd1,0xe5,0x35,0x30,0xe2,0x06,0x90,0x01,0x3d,0x74,0x04,0xf0,0xe5, ++0x36,0x30,0xe0,0x06,0x90,0x01,0x3e,0x74,0x01,0xf0,0xe5,0x36,0x30,0xe1,0x06,0x90, ++0x01,0x3e,0x74,0x02,0xf0,0x74,0xd4,0x04,0x90,0x01,0xc4,0xf0,0x74,0x45,0xa3,0xf0, ++0xd0,0x07,0xd0,0x06,0xd0,0x05,0xd0,0x04,0xd0,0x03,0xd0,0x02,0xd0,0x01,0xd0,0x00, ++0xd0,0xd0,0xd0,0x82,0xd0,0x83,0xd0,0xf0,0xd0,0xe0,0x32,0x7d,0x01,0x7f,0x0c,0x90, ++0x9e,0xa6,0xed,0xf0,0x90,0x9e,0xa5,0xef,0xf0,0x54,0x0f,0xff,0xe5,0x23,0x54,0x0f, ++0x6f,0x60,0x70,0x90,0x9e,0xa5,0xe0,0x30,0xe2,0x2a,0xe5,0x23,0x20,0xe2,0x05,0x7f, ++0x01,0x12,0x63,0xf3,0xe5,0x23,0x30,0xe3,0x09,0x90,0x9e,0xa5,0xe0,0x20,0xe3,0x02, ++0x80,0x52,0xe5,0x23,0x20,0xe3,0x4c,0x90,0x9e,0xa5,0xe0,0x30,0xe3,0x45,0xa3,0xe0, ++0xff,0x02,0x5e,0x95,0xe5,0x23,0x54,0x0f,0xff,0xbf,0x0c,0x0f,0x90,0x9e,0xa5,0xe0, ++0x20,0xe3,0x08,0x12,0x62,0xd7,0xef,0x60,0x2a,0xf1,0xb4,0xe5,0x23,0x54,0x0f,0xff, ++0xbf,0x04,0x10,0x90,0x9e,0xa5,0xe0,0x20,0xe2,0x09,0x12,0x63,0x20,0xef,0x60,0x13, ++0x12,0x61,0x3a,0xe5,0x23,0x54,0x0f,0xff,0xbf,0x02,0x08,0x12,0x63,0x83,0xef,0x60, ++0x02,0x91,0xec,0x22,0x90,0x06,0x04,0xe0,0x44,0x40,0xf0,0xe5,0x22,0xb4,0x01,0x05, ++0x7f,0x01,0x12,0x5e,0x5c,0x53,0x23,0xf0,0x43,0x23,0x04,0x22,0xe0,0xff,0x7d,0x01, ++0x90,0x9e,0x99,0xef,0xf0,0xa3,0xed,0xf0,0xe4,0xa3,0xf0,0xa3,0xf0,0xe5,0x25,0x60, ++0x05,0xe4,0xff,0x12,0x61,0x1f,0x90,0x9e,0x99,0xe0,0x30,0xe0,0x09,0x90,0x9e,0x9b, ++0xe4,0xf0,0xa3,0x74,0x80,0xf0,0x90,0x9e,0x99,0xe0,0xff,0xc3,0x13,0x90,0xfd,0x10, ++0xf0,0x90,0x04,0x25,0xef,0xf0,0x90,0x9e,0x9a,0xe0,0x60,0x1f,0xa3,0xa3,0xe0,0xff, ++0x24,0x0f,0xf5,0x82,0xe4,0x34,0xfc,0xf5,0x83,0xe0,0x44,0x80,0xf0,0x74,0x10,0x2f, ++0xf5,0x82,0xe4,0x34,0xfc,0xf5,0x83,0xe0,0x44,0x80,0xf0,0x90,0x9e,0x9b,0xa3,0xe0, ++0xff,0xfd,0x24,0x08,0xf5,0x82,0xe4,0x34,0xfc,0xf5,0x83,0xe4,0xf0,0x74,0x09,0x2d, ++0xf5,0x82,0xe4,0x34,0xfc,0xf5,0x83,0xe0,0x54,0xf0,0xf0,0x74,0x21,0x2f,0xf5,0x82, ++0xe4,0x34,0xfc,0xf5,0x83,0xe0,0x54,0xf7,0xf0,0x90,0x9e,0x9b,0xe0,0xfe,0xa3,0xe0, ++0xff,0x22,0x12,0x45,0xa6,0xbf,0x01,0x10,0x90,0x02,0x09,0xe0,0xff,0x7d,0x01,0x12, ++0x47,0xd0,0x90,0x04,0x1f,0x74,0x20,0xf0,0x22,0xc0,0xe0,0xc0,0xf0,0xc0,0x83,0xc0, ++0x82,0xc0,0xd0,0x75,0xd0,0x00,0xc0,0x00,0xc0,0x01,0xc0,0x02,0xc0,0x03,0xc0,0x04, ++0xc0,0x05,0xc0,0x06,0xc0,0x07,0x90,0x01,0xc4,0x74,0x79,0xf0,0x74,0x48,0xa3,0xf0, ++0x90,0x01,0x34,0xe0,0x55,0x28,0xf5,0x2c,0x90,0x01,0x36,0xe0,0x55,0x2a,0xf5,0x2e, ++0xa3,0xe0,0x55,0x2b,0xf5,0x2f,0xe5,0x2c,0x20,0xe0,0x02,0x41,0x17,0x90,0x01,0x34, ++0x74,0x01,0xf0,0x85,0xd1,0x08,0x85,0xd2,0x09,0x85,0xd3,0x0a,0x85,0xd4,0x0b,0x85, ++0xd5,0x0c,0x85,0xd6,0x0d,0x85,0xd7,0x0e,0x85,0xd9,0x0f,0xe5,0x0f,0x54,0x40,0xc3, ++0x13,0xff,0xe5,0x0e,0x54,0x20,0x6f,0x70,0x02,0x21,0xc9,0xe5,0x0f,0x30,0xe5,0x02, ++0x21,0xc9,0xe5,0x0d,0x54,0x3f,0xf5,0x4d,0xe5,0x08,0x54,0x3f,0xf5,0x4e,0xe5,0x0c, ++0x54,0x1f,0xff,0xe5,0x4d,0x25,0xe0,0x24,0xc4,0xf5,0x82,0xe4,0x34,0x99,0xf5,0x83, ++0xe4,0x8f,0xf0,0x12,0x42,0x81,0xe5,0x0e,0x54,0x1f,0xff,0xe5,0x4d,0x25,0xe0,0x24, ++0x80,0xf5,0x82,0xe4,0x34,0x93,0xf5,0x83,0xe4,0x8f,0xf0,0x12,0x42,0x81,0xe5,0x4e, ++0xd3,0x94,0x04,0x40,0x03,0x75,0x4e,0x04,0x75,0xf0,0x0a,0xe5,0x4d,0x90,0x90,0x00, ++0x12,0x43,0x5f,0x75,0xf0,0x02,0xe5,0x4e,0x12,0x43,0x5f,0xe0,0xfe,0xa3,0xe0,0xff, ++0xe5,0x0e,0x54,0x1f,0x2f,0xff,0xe4,0x3e,0xfe,0x75,0xf0,0x0a,0xe5,0x4d,0x90,0x90, ++0x00,0x12,0x43,0x5f,0x75,0xf0,0x02,0xe5,0x4e,0x12,0x43,0x5f,0xee,0xf0,0xa3,0xef, ++0xf0,0xe5,0x0f,0x20,0xe6,0x24,0xe5,0x0e,0x54,0x1f,0xff,0xe5,0x4d,0x25,0xe0,0x24, ++0xc4,0xf5,0x82,0xe4,0x34,0x98,0xf5,0x83,0xe4,0x8f,0xf0,0x12,0x42,0x81,0xe5,0x0a, ++0x30,0xe7,0x36,0xaf,0x4d,0x12,0x5b,0x68,0x80,0x2f,0xe5,0x0e,0x54,0x1f,0xff,0xe5, ++0x4d,0x25,0xe0,0x24,0x44,0xf5,0x82,0xe4,0x34,0x99,0xf5,0x83,0xe4,0x8f,0xf0,0x12, ++0x42,0x81,0xe5,0x0a,0x30,0xe7,0x12,0xe5,0x0a,0x54,0x7f,0xfd,0xe5,0x0e,0x54,0x1f, ++0xf5,0x53,0xab,0x4e,0xaf,0x4d,0x12,0x5b,0x05,0xe5,0x25,0x14,0x24,0xfd,0x50,0x02, ++0x80,0x45,0x90,0x9e,0x73,0xe0,0x60,0x37,0x90,0x01,0x5b,0xe4,0xf0,0x90,0x01,0x3c, ++0x74,0x04,0xf0,0x71,0xc4,0xef,0x64,0x01,0x70,0x2d,0x90,0x9e,0x69,0xe0,0xf5,0x44, ++0x75,0x45,0x00,0xe4,0xfb,0xfd,0x7f,0x58,0x7e,0x01,0x12,0x35,0xab,0x90,0x01,0x5b, ++0x74,0x05,0xf0,0x90,0x06,0x92,0x74,0x01,0xf0,0x90,0x9e,0x71,0xf0,0x80,0x08,0x71, ++0xc4,0xbf,0x01,0x03,0x12,0x44,0xd1,0xe5,0x2c,0x30,0xe1,0x21,0x90,0x01,0x34,0x74, ++0x02,0xf0,0x85,0xd1,0x13,0x85,0xd2,0x14,0x85,0xd3,0x15,0x85,0xd4,0x16,0x85,0xd5, ++0x17,0x85,0xd6,0x18,0x85,0xd7,0x19,0x85,0xd9,0x1a,0x12,0x5c,0x46,0xe5,0x2c,0x30, ++0xe3,0x06,0x90,0x01,0x34,0x74,0x08,0xf0,0xe5,0x2c,0x30,0xe4,0x09,0x90,0x01,0x34, ++0x74,0x10,0xf0,0x43,0x12,0x10,0xe5,0x2c,0x30,0xe5,0x24,0x90,0x01,0xcf,0xe0,0x30, ++0xe5,0x1d,0xe0,0x54,0xdf,0xf0,0x90,0x01,0x34,0x74,0x20,0xf0,0x75,0xa8,0x00,0x75, ++0xe8,0x00,0xd1,0xdb,0x90,0x00,0x03,0xe0,0x54,0xfb,0xf0,0x71,0xdb,0x80,0xfe,0xe5, ++0x2c,0x30,0xe6,0x06,0x90,0x01,0x34,0x74,0x40,0xf0,0xe5,0x2e,0x30,0xe0,0x12,0x90, ++0x9e,0x5f,0x74,0x01,0xf0,0x90,0x01,0x36,0xf0,0x12,0x65,0xa3,0x90,0x9e,0x5f,0xe4, ++0xf0,0xe5,0x2e,0x30,0xe1,0x3b,0x90,0x01,0x36,0x74,0x02,0xf0,0x43,0x12,0x40,0x90, ++0x01,0x02,0xe0,0x54,0x03,0x64,0x01,0x70,0x28,0x90,0x01,0x37,0xe0,0x30,0xe0,0x0a, ++0x74,0x01,0xf0,0x90,0x9e,0x4f,0xe4,0xf0,0x80,0x17,0x90,0x9e,0x4f,0xe0,0x04,0xf0, ++0xe0,0xc3,0x94,0x0a,0x40,0x0b,0xe4,0xf0,0x90,0x04,0x19,0xe0,0x30,0xe0,0x02,0x11, ++0x62,0xe5,0x2e,0x30,0xe2,0x09,0x90,0x01,0x36,0x74,0x04,0xf0,0x12,0x65,0x3b,0xe5, ++0x2e,0x30,0xe3,0x28,0x90,0x01,0x36,0x74,0x08,0xf0,0xe5,0x22,0x64,0x01,0x70,0x1c, ++0xe5,0x25,0x60,0x18,0x90,0x01,0x57,0xe4,0xf0,0x90,0x01,0x3c,0x74,0x02,0xf0,0x90, ++0x9e,0x86,0xe4,0x12,0x44,0x52,0x90,0x01,0x57,0x74,0x05,0xf0,0xe5,0x2e,0x30,0xe4, ++0x2b,0x90,0x01,0x36,0x74,0x10,0xf0,0xe5,0x22,0xb4,0x01,0x20,0xe5,0x25,0x60,0x1c, ++0x90,0x01,0x57,0xe4,0xf0,0x90,0x01,0x3c,0x74,0x02,0xf0,0x90,0x9e,0x74,0xe4,0xf0, ++0x53,0x26,0xfd,0xe5,0x26,0x54,0x07,0x70,0x03,0x12,0x44,0xd1,0xe5,0x2e,0x30,0xe5, ++0x1f,0x90,0x01,0x36,0x74,0x20,0xf0,0xe5,0x22,0xb4,0x01,0x14,0xe5,0x25,0x60,0x10, ++0x90,0x9e,0x73,0xe0,0x64,0x02,0x60,0x05,0x12,0x44,0xd7,0x80,0x03,0x12,0x44,0x80, ++0xe5,0x2e,0x30,0xe6,0x1b,0x90,0x01,0x36,0x74,0x40,0xf0,0xe5,0x22,0xb4,0x01,0x10, ++0xe5,0x25,0x60,0x0c,0x53,0x26,0xfe,0xe5,0x26,0x54,0x07,0x70,0x03,0x12,0x44,0xd1, ++0xe5,0x2f,0x30,0xe1,0x09,0x90,0x01,0x37,0x74,0x02,0xf0,0x12,0x61,0x92,0x74,0x79, ++0x04,0x90,0x01,0xc4,0xf0,0x74,0x48,0xa3,0xf0,0xd0,0x07,0xd0,0x06,0xd0,0x05,0xd0, ++0x04,0xd0,0x03,0xd0,0x02,0xd0,0x01,0xd0,0x00,0xd0,0xd0,0xd0,0x82,0xd0,0x83,0xd0, ++0xf0,0xd0,0xe0,0x32,0x90,0x04,0x1b,0xe0,0x54,0x7f,0x64,0x7f,0x7f,0x01,0x60,0x02, ++0x7f,0x00,0x22,0xf4,0xff,0x90,0x00,0x43,0xe0,0x5f,0xf0,0xd3,0x10,0xaf,0x01,0xc3, ++0xc0,0xd0,0x7f,0x10,0xdf,0xfe,0xd0,0xd0,0x92,0xaf,0x22,0xd3,0x10,0xaf,0x01,0xc3, ++0xc0,0xd0,0x90,0x9e,0xac,0xed,0xf0,0x90,0x9e,0xab,0xef,0xf0,0xd3,0x94,0x07,0x50, ++0x63,0xe0,0xff,0x74,0x01,0xa8,0x07,0x08,0x80,0x02,0xc3,0x33,0xd8,0xfc,0xf4,0xff, ++0x90,0x00,0x47,0xe0,0x5f,0xf0,0x71,0xdb,0x90,0x9e,0xab,0xe0,0xff,0x74,0x01,0xa8, ++0x07,0x08,0x80,0x02,0xc3,0x33,0xd8,0xfc,0xff,0x90,0x00,0x46,0xe0,0x4f,0xf0,0x71, ++0xdb,0x90,0x9e,0xac,0xe0,0x60,0x16,0x90,0x9e,0xab,0xe0,0xff,0x74,0x01,0xa8,0x07, ++0x08,0x80,0x02,0xc3,0x33,0xd8,0xfc,0xff,0x90,0x00,0x45,0x80,0x66,0x90,0x9e,0xab, ++0xe0,0xff,0x74,0x01,0xa8,0x07,0x08,0x80,0x02,0xc3,0x33,0xd8,0xfc,0xf4,0xff,0x90, ++0x00,0x45,0x80,0x6b,0x90,0x9e,0xab,0xe0,0x24,0xf8,0xf0,0xe0,0xff,0x74,0x01,0xa8, ++0x07,0x08,0x80,0x02,0xc3,0x33,0xd8,0xfc,0xc4,0x54,0xf0,0x71,0xd3,0x90,0x9e,0xab, ++0xe0,0xff,0x74,0x01,0xa8,0x07,0x08,0x80,0x02,0xc3,0x33,0xd8,0xfc,0xff,0x90,0x00, ++0x43,0xe0,0x4f,0xf0,0x71,0xdb,0x90,0x9e,0xac,0xe0,0x60,0x1b,0x90,0x9e,0xab,0xe0, ++0xff,0x74,0x01,0xa8,0x07,0x08,0x80,0x02,0xc3,0x33,0xd8,0xfc,0xc4,0x54,0xf0,0xff, ++0x90,0x00,0x42,0xe0,0x4f,0x80,0x1a,0x90,0x9e,0xab,0xe0,0xff,0x74,0x01,0xa8,0x07, ++0x08,0x80,0x02,0xc3,0x33,0xd8,0xfc,0xc4,0x54,0xf0,0xf4,0xff,0x90,0x00,0x42,0xe0, ++0x5f,0xf0,0x71,0xdb,0xd0,0xd0,0x92,0xaf,0x22,0xf0,0x90,0x00,0x45,0xe0,0x54,0xfe, ++0xfd,0x7f,0x45,0xd3,0x10,0xaf,0x01,0xc3,0xc0,0xd0,0x8f,0x82,0x75,0x83,0x00,0xed, ++0xf0,0x71,0xdb,0xd0,0xd0,0x92,0xaf,0x22,0xef,0x14,0x60,0x30,0x14,0x60,0x66,0x24, ++0x02,0x60,0x02,0xa1,0x9f,0x90,0x9e,0x1a,0x74,0x02,0xf0,0x90,0x00,0x48,0xe0,0x44, ++0x0c,0xfd,0x7f,0x48,0x91,0xe3,0x90,0x00,0x47,0xe0,0x44,0x08,0xfd,0x7f,0x47,0x91, ++0xe3,0x90,0x00,0x45,0xe0,0x44,0x10,0xfd,0x7f,0x45,0x80,0x71,0xe4,0x90,0x9e,0x1a, ++0xf0,0x90,0x9e,0x16,0x12,0x43,0x53,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0x80,0x7e, ++0x08,0x12,0x2f,0xd9,0x90,0x00,0x45,0xe0,0x44,0xef,0xfd,0x7f,0x45,0x91,0xe3,0x90, ++0x00,0x45,0xe0,0x54,0xef,0xfd,0x7f,0x45,0x91,0xe3,0x90,0x00,0x46,0xe0,0x44,0x10, ++0xfd,0x7f,0x46,0x80,0x38,0x90,0x9e,0x1a,0x74,0x01,0xf0,0x90,0x9e,0x20,0x12,0x43, ++0x53,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0x80,0x7e,0x08,0x12,0x2f,0xd9,0x90,0x00, ++0x45,0xe0,0x44,0x20,0xfd,0x7f,0x45,0x91,0xe3,0x90,0x00,0x45,0xe0,0x44,0x10,0xfd, ++0x7f,0x45,0x91,0xe3,0x90,0x00,0x46,0xe0,0x44,0x10,0xfd,0x7f,0x46,0x91,0xe3,0x22, ++0x90,0x00,0x02,0x12,0x42,0x20,0x90,0x9e,0x1c,0xf0,0x90,0x00,0x01,0x12,0x42,0x20, ++0x25,0xe0,0x25,0xe0,0x90,0x9e,0x1b,0xf0,0x12,0x29,0xd9,0x25,0xe0,0x25,0xe0,0x90, ++0x9e,0x1f,0xf0,0x90,0x05,0x60,0xe0,0x90,0x9e,0x2a,0xf0,0x90,0x05,0x61,0xe0,0x90, ++0x9e,0x2b,0xf0,0x90,0x05,0x62,0xe0,0x90,0x9e,0x2c,0xf0,0x90,0x05,0x63,0xe0,0x90, ++0x9e,0x2d,0xf0,0xa2,0xaf,0xe4,0x33,0x90,0x9e,0x3f,0xf0,0xc2,0xaf,0x90,0x9e,0x1b, ++0xe0,0xff,0x12,0x52,0x12,0x90,0x9e,0x3f,0xe0,0x24,0xff,0x92,0xaf,0x90,0x9e,0x1c, ++0xe0,0x70,0x02,0xc1,0xa7,0x90,0x9e,0x1b,0xe0,0x70,0x02,0xc1,0xa7,0x90,0x9e,0x1f, ++0xe0,0x70,0x02,0xc1,0xa7,0xa2,0xaf,0xe4,0x33,0x90,0x9e,0x3f,0xf0,0xc2,0xaf,0x90, ++0x9e,0x2e,0x74,0x01,0xf0,0x90,0x9e,0x3f,0xe0,0x24,0xff,0x92,0xaf,0x91,0xda,0x90, ++0x00,0x46,0xe0,0x44,0x01,0xfd,0x7f,0x46,0x91,0xe3,0x90,0x9e,0x14,0xe0,0x60,0x15, ++0x90,0x9e,0x20,0x12,0x43,0x53,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0x80,0x7e,0x08, ++0x12,0x2f,0xd9,0x80,0x06,0x90,0x05,0x22,0x74,0x7f,0xf0,0x90,0x00,0x45,0xe0,0x54, ++0xef,0xfd,0x7f,0x45,0x91,0xe3,0x90,0x05,0x87,0xe0,0x64,0x80,0xf0,0x90,0x9e,0x2a, ++0xe0,0x90,0x05,0x84,0xf0,0x90,0x9e,0x2b,0xe0,0x90,0x05,0x85,0xf0,0x90,0x9e,0x2c, ++0xe0,0x90,0x05,0x86,0xf0,0x90,0x9e,0x2d,0xe0,0x90,0x05,0x87,0xf0,0xa2,0xaf,0xe4, ++0x33,0x90,0x9e,0x3f,0xf0,0xc2,0xaf,0x90,0x01,0x3c,0xe0,0x44,0x20,0xf0,0x7d,0x20, ++0xe4,0xff,0x12,0x37,0x00,0x80,0x2b,0x90,0x9e,0x1c,0xe0,0x70,0x2d,0x90,0x9e,0x2e, ++0x91,0xd9,0x90,0x00,0x46,0xe0,0x54,0xfe,0xfd,0x7f,0x46,0x91,0xe3,0x90,0x05,0x22, ++0xe4,0xf0,0xa2,0xaf,0x33,0x90,0x9e,0x3f,0xf0,0xc2,0xaf,0x7d,0x20,0xe4,0xff,0x12, ++0x36,0x92,0x90,0x9e,0x3f,0xe0,0x24,0xff,0x92,0xaf,0x22,0x90,0x01,0x30,0xe4,0xf0, ++0xa3,0xf0,0xa3,0xf0,0xa3,0xf0,0x90,0x01,0x38,0xf0,0xa3,0xf0,0xa3,0xf0,0xa3,0xf0, ++0xfd,0x7f,0x50,0x91,0xe3,0xe4,0xfd,0x7f,0x51,0x91,0xe3,0xe4,0xfd,0x7f,0x52,0x91, ++0xe3,0xe4,0xfd,0x7f,0x53,0x81,0xe3,0x8b,0x59,0x8a,0x5a,0x89,0x5b,0x90,0x00,0x02, ++0x12,0x42,0x20,0x90,0x9e,0x1d,0xf0,0xe0,0x30,0xe0,0x4b,0x90,0x9e,0x14,0x74,0x01, ++0xf0,0x7f,0x80,0x7e,0x08,0x12,0x27,0xde,0x90,0x9e,0x16,0x12,0x2a,0x7f,0xab,0x59, ++0xaa,0x5a,0xa9,0x5b,0x90,0x00,0x01,0x12,0x42,0x20,0xff,0xe4,0xfc,0xfd,0xfe,0x78, ++0x1a,0x12,0x2a,0x6c,0xa8,0x04,0xa9,0x05,0xaa,0x06,0xab,0x07,0x90,0x9e,0x16,0x12, ++0x43,0x53,0xec,0x54,0x03,0xfc,0x12,0x43,0x46,0x90,0x9e,0x20,0x12,0x2a,0x7f,0x90, ++0x05,0x22,0xe4,0xf0,0x80,0x2d,0xe4,0x90,0x9e,0x14,0xf0,0x7f,0x80,0x7e,0x08,0x12, ++0x27,0xde,0xec,0x54,0x03,0xfc,0xec,0x44,0xc0,0xfc,0x90,0x9e,0x16,0x12,0x2a,0x7f, ++0x90,0x9e,0x16,0x12,0x43,0x53,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0x80,0x7e,0x08, ++0x12,0x2f,0xd9,0x90,0x9e,0x1d,0xe0,0x30,0xe1,0x19,0x7d,0x0c,0x7f,0x47,0x91,0xe3, ++0x90,0x00,0x48,0xe0,0x44,0x0c,0xfd,0x7f,0x48,0x91,0xe3,0x90,0x00,0x46,0xe0,0x44, ++0x10,0x80,0x1c,0x90,0x00,0x47,0xe0,0x54,0xf3,0xfd,0x7f,0x47,0x91,0xe3,0x90,0x00, ++0x48,0xe0,0x54,0xf3,0xfd,0x7f,0x48,0x91,0xe3,0x90,0x00,0x46,0xe0,0x54,0xef,0xfd, ++0x7f,0x46,0x91,0xe3,0xe4,0x90,0x9e,0x1a,0xf0,0x22,0x90,0x00,0x49,0xe0,0x90,0x9e, ++0xb0,0xf0,0xe0,0x54,0x0f,0xf0,0x44,0xf0,0xfd,0x7f,0x49,0x91,0xe3,0x90,0x9e,0xb0, ++0xe0,0x44,0xb0,0xfd,0x7f,0x49,0x81,0xe3,0x75,0x28,0x33,0xe4,0xf5,0x29,0x75,0x2a, ++0x07,0xf5,0x2b,0x90,0x01,0x30,0xe5,0x28,0xf0,0xa3,0xe5,0x29,0xf0,0xa3,0xe5,0x2a, ++0xf0,0xa3,0xe5,0x2b,0xf0,0x22,0x75,0x30,0x1f,0x75,0x31,0x01,0xe4,0xf5,0x32,0x90, ++0x01,0x38,0xe5,0x30,0xf0,0xa3,0xe5,0x31,0xf0,0xa3,0xe5,0x32,0xf0,0x22,0xe4,0x90, ++0x9e,0x31,0xf0,0xa3,0xf0,0x75,0x8e,0x02,0x12,0x77,0x64,0x12,0x5e,0xde,0x90,0x9e, ++0x5e,0xef,0xf0,0x12,0x5e,0xeb,0x90,0x9e,0x60,0xef,0xf0,0xe4,0xf5,0x12,0x12,0x6e, ++0xdf,0x12,0x77,0xdb,0x12,0x5f,0x9f,0x12,0x32,0x3d,0x12,0x77,0xd7,0x12,0x4f,0xf8, ++0x90,0x00,0xf3,0xe0,0x30,0xe2,0x0d,0x90,0x05,0x41,0x74,0x10,0xf0,0x90,0x05,0x5a, ++0xf0,0xa3,0xe4,0xf0,0x12,0x5e,0xf8,0x11,0x16,0x12,0x44,0xff,0x12,0x7d,0x9b,0x90, ++0x9e,0x33,0xe5,0xd9,0xf0,0x12,0x5e,0xaf,0xc2,0xaf,0x90,0x00,0x80,0xe0,0x44,0x40, ++0xf0,0x12,0x4b,0xdb,0x75,0xe8,0x03,0x43,0xa8,0x85,0xd2,0xaf,0x90,0x9e,0x31,0xe0, ++0x64,0x01,0xf0,0x24,0x2e,0x90,0x01,0xc4,0xf0,0x74,0x50,0xa3,0xf0,0xe5,0x12,0x30, ++0xe4,0x09,0xc2,0xaf,0x53,0x12,0xef,0xd2,0xaf,0x71,0x1a,0xe5,0x12,0x30,0xe6,0x16, ++0xc2,0xaf,0x53,0x12,0xbf,0xd2,0xaf,0x12,0x68,0x8d,0x90,0x9e,0x1e,0xe0,0xff,0x60, ++0x03,0xb4,0x01,0x02,0x31,0x10,0x90,0x9e,0x1e,0xe0,0x70,0x03,0x12,0x7d,0xf9,0x11, ++0xe3,0x80,0xb9,0x90,0x06,0x34,0xe0,0x60,0x26,0x14,0x70,0x1b,0x7b,0x01,0x7a,0x06, ++0x79,0x35,0x7f,0xf9,0x7e,0x01,0x12,0x77,0x75,0xbf,0x01,0x09,0x90,0x06,0x35,0xe0, ++0x54,0x0f,0xf0,0x80,0x05,0x80,0x00,0x02,0x77,0x56,0xe4,0x90,0x06,0x34,0xf0,0x22, ++0x90,0x9e,0x15,0xe0,0xc3,0x94,0x14,0x50,0x05,0xe0,0x04,0xf0,0x21,0xc8,0x90,0x9e, ++0x15,0xe0,0x64,0x14,0x60,0x02,0x21,0xc8,0x90,0x9e,0x24,0xe0,0x70,0x25,0x90,0x9e, ++0x27,0xe0,0x70,0x1f,0x90,0x9e,0x25,0xe0,0x70,0x19,0x90,0x9e,0x28,0xe0,0x70,0x13, ++0x90,0x9e,0x26,0xe0,0x70,0x0d,0x90,0x9e,0x29,0xe0,0x70,0x07,0x90,0x04,0xfd,0xe0, ++0x54,0xfe,0xf0,0x90,0x9e,0x24,0xe0,0x90,0x04,0x44,0xf0,0x90,0x9e,0x25,0xe0,0x90, ++0x04,0x45,0xf0,0x90,0x9e,0x26,0xe0,0x90,0x04,0x46,0xf0,0xa3,0xe4,0xf0,0x90,0x9e, ++0x27,0xe0,0x90,0x04,0x48,0xf0,0x90,0x9e,0x28,0xe0,0x90,0x04,0x49,0xf0,0x90,0x9e, ++0x29,0xe0,0x90,0x04,0x4a,0xf0,0xa3,0xe4,0xf0,0x90,0x9e,0x10,0xe0,0x90,0x04,0x4c, ++0xf0,0x90,0x9e,0x11,0xe0,0x90,0x04,0x4d,0xf0,0x90,0x9e,0x12,0xe0,0x90,0x04,0x4e, ++0xf0,0x90,0x9e,0x13,0xe0,0x90,0x04,0x4f,0xf0,0xe4,0x90,0x9e,0x15,0xf0,0x90,0x9e, ++0x10,0x04,0xf0,0xe4,0xa3,0xf0,0xa3,0xf0,0xa3,0xf0,0x90,0x9e,0x24,0xf0,0xa3,0xf0, ++0xa3,0xf0,0xa3,0xf0,0xa3,0xf0,0xa3,0xf0,0x90,0x05,0x60,0xe0,0x90,0x9e,0x34,0xf0, ++0x90,0x05,0x61,0xe0,0x90,0x9e,0x35,0xf0,0x90,0x05,0x62,0xe0,0x90,0x9e,0x36,0xf0, ++0x90,0x05,0x63,0xe0,0x90,0x9e,0x37,0xf0,0x90,0x9e,0x2d,0xe0,0xff,0x90,0x9e,0x37, ++0xe0,0xfe,0xd3,0x9f,0x50,0x0b,0x90,0x9e,0x2d,0xe0,0xc3,0x9e,0xd3,0x94,0x01,0x40, ++0x10,0x90,0x9e,0x1b,0xe0,0xb4,0x01,0x02,0x80,0x03,0x90,0x9e,0x1f,0xe0,0xff,0x51, ++0x12,0x22,0x90,0x05,0x60,0xe0,0x90,0x9e,0x2a,0xf0,0x90,0x05,0x61,0xe0,0x90,0x9e, ++0x2b,0xf0,0x90,0x05,0x62,0xe0,0x90,0x9e,0x2c,0xf0,0x90,0x05,0x63,0xe0,0x90,0x9e, ++0x2d,0xf0,0xc3,0x74,0xff,0x9f,0xfe,0x90,0x9e,0x2b,0xe0,0xd3,0x9e,0x40,0x1e,0xe0, ++0x2f,0xf0,0xa3,0xe0,0xb4,0xff,0x0f,0xe4,0xf0,0xa3,0xe0,0xb4,0xff,0x03,0xe4,0xf0, ++0x22,0x90,0x9e,0x2d,0x80,0x03,0x90,0x9e,0x2c,0xe0,0x04,0xf0,0x22,0x90,0x9e,0x2b, ++0xe0,0x2f,0xf0,0x22,0x90,0x9e,0x1c,0xe0,0x64,0x01,0x60,0x02,0x61,0x19,0x90,0x00, ++0x46,0xe0,0x44,0x01,0xfd,0x7f,0x46,0x12,0x4c,0xe3,0x90,0x9e,0x2e,0xe0,0x70,0x32, ++0x90,0x9e,0x14,0xe0,0x60,0x15,0x90,0x9e,0x20,0x12,0x43,0x53,0x90,0x80,0x85,0x12, ++0x2a,0x7f,0x7f,0x80,0x7e,0x08,0x12,0x2f,0xd9,0x80,0x06,0x90,0x05,0x22,0x74,0x7f, ++0xf0,0x90,0x9e,0x1b,0xe0,0xff,0x51,0x12,0x90,0x9e,0x2e,0x74,0x01,0x12,0x4c,0xd9, ++0x80,0x40,0x90,0x9e,0x2e,0xe0,0x64,0x01,0x70,0x38,0x90,0x9e,0x1f,0xe0,0xff,0x51, ++0x12,0xe4,0x90,0x9e,0x2e,0xf0,0x90,0x00,0x45,0xe0,0x44,0x01,0xfd,0x7f,0x45,0x12, ++0x4c,0xe3,0x90,0x9e,0x14,0xe0,0x60,0x15,0x90,0x9e,0x16,0x12,0x43,0x53,0x90,0x80, ++0x85,0x12,0x2a,0x7f,0x7f,0x80,0x7e,0x08,0x12,0x2f,0xd9,0x80,0x05,0x90,0x05,0x22, ++0xe4,0xf0,0x90,0x05,0x87,0xe0,0x64,0x80,0xf0,0x90,0x9e,0x2a,0xe0,0x90,0x05,0x84, ++0xf0,0x90,0x9e,0x2b,0xe0,0x90,0x05,0x85,0xf0,0x90,0x9e,0x2c,0xe0,0x90,0x05,0x86, ++0xf0,0x90,0x9e,0x2d,0xe0,0x90,0x05,0x87,0xf0,0x22,0x90,0x01,0xcc,0xe0,0x54,0x0f, ++0x90,0x9e,0x34,0xf0,0x90,0x9e,0x34,0xe0,0xfd,0x70,0x02,0x81,0x5b,0x90,0x9e,0xad, ++0xe0,0xff,0x74,0x01,0x7e,0x00,0xa8,0x07,0x08,0x80,0x05,0xc3,0x33,0xce,0x33,0xce, ++0xd8,0xf9,0xff,0xef,0x5d,0x70,0x02,0x81,0x54,0x90,0x9e,0xad,0xe0,0x75,0xf0,0x04, ++0x90,0x01,0xd0,0x12,0x43,0x5f,0xe0,0x90,0x9e,0x35,0xf0,0x75,0x1e,0x01,0x75,0x1f, ++0x9e,0x75,0x20,0x35,0x75,0x21,0x01,0x7b,0x01,0x7a,0x9e,0x79,0x36,0x12,0x45,0x09, ++0x90,0x9e,0x36,0xe0,0xff,0xc4,0x13,0x13,0x13,0x54,0x01,0x90,0x9e,0xad,0x30,0xe0, ++0x59,0xe0,0x75,0xf0,0x02,0x90,0x00,0x88,0x12,0x43,0x5f,0xe0,0x90,0x9e,0x37,0xf0, ++0x90,0x9e,0xad,0xe0,0x75,0xf0,0x02,0x90,0x00,0x89,0x12,0x43,0x5f,0xe0,0x90,0x9e, ++0x38,0xf0,0x90,0x9e,0xad,0xe0,0x75,0xf0,0x04,0x90,0x01,0xd1,0x12,0x43,0x5f,0xe0, ++0x90,0x9e,0x39,0xf0,0x90,0x9e,0xad,0xe0,0x75,0xf0,0x04,0x90,0x01,0xd2,0x12,0x43, ++0x5f,0xe0,0x90,0x9e,0x3a,0xf0,0x90,0x9e,0xad,0xe0,0x75,0xf0,0x04,0x90,0x01,0xd3, ++0x12,0x43,0x5f,0xe0,0x90,0x9e,0x3b,0xf0,0x80,0x33,0xe0,0x75,0xf0,0x04,0x90,0x01, ++0xd1,0x12,0x43,0x5f,0xe0,0x90,0x9e,0x37,0xf0,0x90,0x9e,0xad,0xe0,0x75,0xf0,0x04, ++0x90,0x01,0xd2,0x12,0x43,0x5f,0xe0,0x90,0x9e,0x38,0xf0,0x90,0x9e,0xad,0xe0,0x75, ++0xf0,0x04,0x90,0x01,0xd3,0x12,0x43,0x5f,0xe0,0x90,0x9e,0x39,0xf0,0xef,0x54,0x7f, ++0xff,0x7b,0x01,0x7a,0x9e,0x79,0x37,0x91,0x5c,0x90,0x9e,0x34,0xe0,0xff,0x90,0x9e, ++0xad,0xe0,0xfe,0x74,0x01,0xa8,0x06,0x08,0x80,0x02,0xc3,0x33,0xd8,0xfc,0xf4,0x5f, ++0x90,0x9e,0x34,0xf0,0x90,0x9e,0xad,0xe0,0xff,0x74,0x01,0xa8,0x07,0x08,0x80,0x02, ++0xc3,0x33,0xd8,0xfc,0x90,0x01,0xcc,0xf0,0x90,0x9e,0xad,0xe0,0x04,0xf0,0xe0,0x54, ++0x03,0xf0,0x61,0x24,0x90,0x01,0xc6,0xe0,0x44,0x02,0xf0,0x22,0x90,0x9e,0x3c,0x12, ++0x43,0x8b,0xef,0x12,0x43,0x94,0x54,0x97,0x01,0x54,0xa0,0x02,0x54,0xbb,0x03,0x54, ++0xc4,0x05,0x54,0xcd,0x06,0x55,0x1b,0x07,0x54,0xd5,0x09,0x54,0xde,0x0c,0x54,0xe7, ++0x0d,0x54,0xf0,0x0e,0x54,0xf9,0x1b,0x55,0x02,0x1c,0x55,0x0b,0x2c,0x54,0xa9,0x2d, ++0x54,0xb2,0x2e,0x00,0x00,0x55,0x14,0x90,0x9e,0x3c,0x12,0x43,0x6b,0x02,0x61,0x69, ++0x90,0x9e,0x3c,0x12,0x43,0x6b,0x02,0x71,0x02,0x90,0x9e,0x3c,0x12,0x43,0x6b,0x02, ++0x71,0x08,0x90,0x9e,0x3c,0x12,0x43,0x6b,0x02,0x71,0x50,0x90,0x9e,0x3c,0x12,0x43, ++0x6b,0x02,0x71,0x7e,0x90,0x9e,0x3c,0x12,0x43,0x6b,0x02,0x70,0xb2,0x90,0x9e,0x3c, ++0x12,0x43,0x6b,0x80,0x47,0x90,0x9e,0x3c,0x12,0x43,0x6b,0x02,0x71,0xc6,0x90,0x9e, ++0x3c,0x12,0x43,0x6b,0x02,0x4d,0xa0,0x90,0x9e,0x3c,0x12,0x43,0x6b,0x02,0x7d,0x68, ++0x90,0x9e,0x3c,0x12,0x43,0x6b,0x02,0x4f,0x07,0x90,0x9e,0x3c,0x12,0x43,0x6b,0x02, ++0x70,0xfa,0x90,0x9e,0x3c,0x12,0x43,0x6b,0x02,0x70,0xe1,0x90,0x9e,0x3c,0x12,0x43, ++0x6b,0x02,0x76,0x36,0x90,0x01,0xc6,0xe0,0x44,0x01,0xf0,0x22,0x90,0x00,0x04,0x12, ++0x42,0x20,0xff,0x54,0x1f,0xfe,0xef,0x54,0x20,0xc4,0x13,0x54,0x07,0xfd,0xaf,0x06, ++0x90,0x9e,0x3f,0xef,0xf0,0xa3,0xed,0xf0,0xa3,0x12,0x43,0x8b,0x90,0x9e,0x41,0x12, ++0x43,0x6b,0x90,0x00,0x03,0x12,0x42,0x20,0x54,0xf0,0xc4,0x54,0x0f,0x90,0x9e,0x44, ++0xf0,0x90,0x00,0x04,0x12,0x42,0x20,0x54,0x40,0xc4,0x13,0x13,0x54,0x03,0x90,0x9e, ++0x45,0xf0,0x90,0x9e,0x3f,0xe0,0xff,0x75,0xf0,0x09,0x90,0x96,0x46,0x12,0x43,0x5f, ++0xad,0x82,0xac,0x83,0x90,0x9e,0x46,0xec,0xf0,0xa3,0xed,0xf0,0xef,0x75,0xf0,0x09, ++0xa4,0x24,0x44,0xf9,0x74,0x96,0x35,0xf0,0xfa,0x7b,0x01,0xa3,0x12,0x43,0x8b,0x90, ++0x9e,0x41,0x12,0x43,0x6b,0x90,0x00,0x03,0x12,0x42,0x20,0x54,0x0f,0xff,0x90,0x9e, ++0x48,0x12,0x43,0x6b,0xef,0x12,0x42,0x4d,0x90,0x9e,0x41,0x12,0x43,0x6b,0x90,0x00, ++0x02,0x12,0x42,0x20,0xff,0x90,0x9e,0x48,0x12,0x43,0x6b,0x90,0x00,0x01,0xef,0x12, ++0x42,0x5f,0x90,0x9e,0x41,0x12,0x43,0x6b,0x90,0x00,0x01,0x12,0x42,0x20,0xff,0x90, ++0x9e,0x46,0xe0,0xfc,0xa3,0xe0,0xfd,0xf5,0x82,0x8c,0x83,0xef,0xf0,0x12,0x29,0xd9, ++0x8d,0x82,0x8c,0x83,0xa3,0xf0,0x90,0x9e,0x44,0xe0,0xfe,0x90,0x9e,0x3f,0xe0,0xff, ++0x24,0x82,0xf5,0x82,0xe4,0x34,0x95,0xf5,0x83,0xee,0xf0,0x90,0x9e,0x40,0xe0,0xfe, ++0x75,0xf0,0x09,0xef,0x90,0x96,0x4a,0x12,0x43,0x5f,0xee,0xf0,0x75,0xf0,0x09,0xef, ++0x90,0x96,0x4b,0x12,0x43,0x5f,0x74,0x01,0xf0,0x90,0x9e,0x45,0xe0,0xfe,0x75,0xf0, ++0x09,0xef,0x90,0x96,0x4c,0x12,0x43,0x5f,0xee,0xf0,0x8f,0x59,0xef,0x25,0xe0,0x24, ++0xc6,0xf5,0x82,0xe4,0x34,0x9b,0xaf,0x82,0xf5,0x5b,0x8f,0x5c,0xe5,0x59,0x75,0xf0, ++0x02,0xa4,0x24,0x02,0xf9,0x74,0x95,0x35,0xf0,0x75,0x5d,0x01,0xf5,0x5e,0x89,0x5f, ++0x75,0xf0,0x09,0xe5,0x59,0x90,0x96,0x46,0x12,0x43,0x5f,0xaf,0x82,0x85,0x83,0x60, ++0x8f,0x61,0xe5,0x59,0x75,0xf0,0x09,0xa4,0x24,0x44,0xf9,0x74,0x96,0x35,0xf0,0x75, ++0x62,0x01,0xf5,0x63,0x89,0x64,0x74,0x82,0x25,0x59,0xf5,0x82,0xe4,0x34,0x95,0xf5, ++0x83,0xe0,0x12,0x43,0x94,0x56,0xaa,0x00,0x56,0xbf,0x01,0x56,0xd4,0x02,0x56,0xe9, ++0x03,0x57,0x13,0x04,0x57,0x28,0x05,0x57,0x3d,0x06,0x57,0x64,0x0c,0x57,0x92,0x0d, ++0x57,0xbf,0x0e,0x57,0xec,0x0f,0x00,0x00,0x58,0x20,0xe5,0x59,0x25,0xe0,0x24,0xc6, ++0xf5,0x82,0xe4,0x34,0x9b,0xf5,0x83,0x74,0xf0,0xf0,0xa3,0x74,0x15,0x80,0x3c,0xe5, ++0x59,0x25,0xe0,0x24,0xc6,0xf5,0x82,0xe4,0x34,0x9b,0xf5,0x83,0x74,0xf0,0xf0,0xa3, ++0x74,0x10,0x80,0x27,0xe5,0x59,0x25,0xe0,0x24,0xc6,0xf5,0x82,0xe4,0x34,0x9b,0xf5, ++0x83,0x74,0xf0,0xf0,0xa3,0x74,0x05,0x80,0x12,0xe5,0x59,0x25,0xe0,0x24,0xc6,0xf5, ++0x82,0xe4,0x34,0x9b,0xf5,0x83,0x74,0xf0,0xf0,0xa3,0xe4,0xf0,0xe5,0x59,0x25,0xe0, ++0x24,0x02,0xf5,0x82,0xe4,0x34,0x95,0xf5,0x83,0x74,0x0f,0xf0,0xa3,0x74,0x8f,0xf0, ++0x02,0x58,0x20,0xe5,0x59,0x25,0xe0,0x24,0xc6,0xf5,0x82,0xe4,0x34,0x9b,0xf5,0x83, ++0x74,0x0f,0xf0,0xa3,0x74,0xf5,0x80,0x27,0xe5,0x59,0x25,0xe0,0x24,0xc6,0xf5,0x82, ++0xe4,0x34,0x9b,0xf5,0x83,0x74,0x0f,0xf0,0xa3,0x74,0xf0,0x80,0x12,0xe5,0x59,0x25, ++0xe0,0x24,0xc6,0xf5,0x82,0xe4,0x34,0x9b,0xf5,0x83,0xe4,0xf0,0xa3,0x74,0x0d,0xf0, ++0xe5,0x59,0x25,0xe0,0x24,0x02,0xf5,0x82,0xe4,0x34,0x95,0xf5,0x83,0xe4,0xf0,0xa3, ++0xf0,0x02,0x58,0x20,0x90,0x04,0x47,0xe0,0xab,0x5d,0xaa,0x5e,0xa9,0x5f,0x12,0x42, ++0x4d,0x90,0x04,0x46,0xe0,0xab,0x5d,0xaa,0x5e,0xa9,0x5f,0x90,0x00,0x01,0x12,0x42, ++0x5f,0x90,0x04,0x45,0xe0,0x85,0x5c,0x82,0x85,0x5b,0x83,0xf0,0x90,0x04,0x44,0x02, ++0x58,0x17,0x90,0x04,0x4b,0xe0,0xab,0x5d,0xaa,0x5e,0xa9,0x5f,0x12,0x42,0x4d,0x90, ++0x04,0x4a,0xe0,0xab,0x5d,0xaa,0x5e,0xa9,0x5f,0x90,0x00,0x01,0x12,0x42,0x5f,0x90, ++0x04,0x49,0xe0,0x85,0x5c,0x82,0x85,0x5b,0x83,0xf0,0x90,0x04,0x48,0x80,0x58,0x90, ++0x04,0x4f,0xe0,0xab,0x5d,0xaa,0x5e,0xa9,0x5f,0x12,0x42,0x4d,0x90,0x04,0x4e,0xe0, ++0xab,0x5d,0xaa,0x5e,0xa9,0x5f,0x90,0x00,0x01,0x12,0x42,0x5f,0x90,0x04,0x4d,0xe0, ++0x85,0x5c,0x82,0x85,0x5b,0x83,0xf0,0x90,0x04,0x4c,0x80,0x2b,0x90,0x04,0x53,0xe0, ++0xab,0x5d,0xaa,0x5e,0xa9,0x5f,0x12,0x42,0x4d,0x90,0x04,0x52,0xe0,0xab,0x5d,0xaa, ++0x5e,0xa9,0x5f,0x90,0x00,0x01,0x12,0x42,0x5f,0x90,0x04,0x51,0xe0,0x85,0x5c,0x82, ++0x85,0x5b,0x83,0xf0,0x90,0x04,0x50,0xe0,0x85,0x5c,0x82,0x85,0x5b,0x83,0xa3,0xf0, ++0xab,0x5d,0xaa,0x5e,0xa9,0x5f,0xc0,0x03,0xc0,0x02,0xc0,0x01,0x12,0x29,0xd9,0xff, ++0xab,0x62,0xaa,0x63,0xa9,0x64,0x12,0x29,0xd9,0x5f,0xd0,0x01,0xd0,0x02,0xd0,0x03, ++0x12,0x42,0x4d,0xab,0x5d,0xe5,0x5f,0x24,0x01,0xf9,0xe4,0x35,0x5e,0xfa,0xc0,0x03, ++0xc0,0x02,0xc0,0x01,0x12,0x29,0xd9,0xff,0xab,0x62,0xaa,0x63,0xa9,0x64,0x90,0x00, ++0x01,0x12,0x42,0x20,0x5f,0xd0,0x01,0xd0,0x02,0xd0,0x03,0x12,0x42,0x4d,0x85,0x5c, ++0x82,0x85,0x5b,0x83,0xc0,0x83,0xc0,0x82,0xe0,0xff,0x85,0x61,0x82,0x85,0x60,0x83, ++0xe0,0xfe,0xef,0x5e,0xd0,0x82,0xd0,0x83,0xf0,0x85,0x5c,0x82,0x85,0x5b,0x83,0xa3, ++0xc0,0x83,0xc0,0x82,0xe0,0xff,0x85,0x61,0x82,0x85,0x60,0x83,0xa3,0xe0,0xfe,0xef, ++0x5e,0xd0,0x82,0xd0,0x83,0xf0,0xe5,0x59,0x25,0xe0,0x24,0x02,0xf5,0x82,0xe4,0x34, ++0x95,0xf5,0x83,0xe0,0xfe,0xa3,0xe0,0x4e,0x60,0x3b,0x75,0x5a,0x0b,0x74,0x01,0x7e, ++0x00,0xa8,0x5a,0x08,0x80,0x05,0xc3,0x33,0xce,0x33,0xce,0xd8,0xf9,0xff,0xe5,0x59, ++0x25,0xe0,0x24,0x02,0xf5,0x82,0xe4,0x34,0x95,0xf5,0x83,0xe0,0x5e,0xfe,0xa3,0xe0, ++0x5f,0x4e,0x60,0x06,0xe5,0x5a,0x24,0x10,0x80,0x5d,0x15,0x5a,0xe5,0x5a,0xc3,0x94, ++0x00,0x50,0xca,0x80,0x56,0xe5,0x59,0x25,0xe0,0x24,0xc6,0xf5,0x82,0xe4,0x34,0x9b, ++0xf5,0x83,0xe0,0xfe,0xa3,0xe0,0x4e,0x60,0x3d,0x75,0x5a,0x0f,0x74,0x01,0x7e,0x00, ++0xa8,0x5a,0x08,0x80,0x05,0xc3,0x33,0xce,0x33,0xce,0xd8,0xf9,0xff,0xe5,0x59,0x25, ++0xe0,0x24,0xc6,0xf5,0x82,0xe4,0x34,0x9b,0xf5,0x83,0xe0,0x5e,0xfe,0xa3,0xe0,0x5f, ++0x4e,0x60,0x08,0x90,0x9e,0x4b,0xe5,0x5a,0xf0,0x80,0x10,0x15,0x5a,0xe5,0x5a,0xc3, ++0x94,0x00,0x50,0xc8,0x80,0x05,0xe4,0x90,0x9e,0x4b,0xf0,0xe5,0x59,0x25,0xe0,0x24, ++0xc6,0xf5,0x82,0xe4,0x34,0x9b,0xf5,0x83,0xe0,0xfe,0xa3,0xe0,0x4e,0x60,0x3b,0xe4, ++0xf5,0x5a,0x74,0x01,0x7e,0x00,0xa8,0x5a,0x08,0x80,0x05,0xc3,0x33,0xce,0x33,0xce, ++0xd8,0xf9,0xff,0xe5,0x59,0x25,0xe0,0x24,0xc6,0xf5,0x82,0xe4,0x34,0x9b,0xf5,0x83, ++0xe0,0x5e,0xfe,0xa3,0xe0,0x5f,0x4e,0x60,0x08,0x90,0x9e,0x4c,0xe5,0x5a,0xf0,0x80, ++0x5b,0x05,0x5a,0xe5,0x5a,0xb4,0x10,0xca,0x80,0x52,0xe5,0x59,0x25,0xe0,0x24,0x02, ++0xf5,0x82,0xe4,0x34,0x95,0xf5,0x83,0xe0,0xfe,0xa3,0xe0,0x4e,0x60,0x39,0xe4,0xf5, ++0x5a,0x74,0x01,0x7e,0x00,0xa8,0x5a,0x08,0x80,0x05,0xc3,0x33,0xce,0x33,0xce,0xd8, ++0xf9,0xff,0xe5,0x59,0x25,0xe0,0x24,0x02,0xf5,0x82,0xe4,0x34,0x95,0xf5,0x83,0xe0, ++0x5e,0xfe,0xa3,0xe0,0x5f,0x4e,0x60,0x06,0xe5,0x5a,0x24,0x10,0x80,0x0a,0x05,0x5a, ++0xe5,0x5a,0xb4,0x0c,0xcc,0x80,0x05,0xe4,0x90,0x9e,0x4c,0xf0,0x90,0x9e,0x4b,0xe0, ++0xff,0x75,0xf0,0x09,0xe5,0x59,0x90,0x96,0x48,0x12,0x43,0x5f,0xef,0xf0,0x90,0x9e, ++0x4c,0xe0,0xfe,0x75,0xf0,0x09,0xe5,0x59,0x90,0x96,0x49,0x12,0x43,0x5f,0xee,0xf0, ++0x74,0x84,0x25,0x59,0xf5,0x82,0xe4,0x34,0x04,0xf5,0x83,0xe0,0xd3,0x9f,0x40,0x05, ++0x90,0x9e,0x4b,0x51,0x6f,0x74,0x84,0x25,0x59,0xf5,0x82,0xe4,0x34,0x04,0xf5,0x83, ++0xe0,0xff,0x90,0x9e,0x4c,0xe0,0xfe,0xef,0xc3,0x9e,0x50,0x02,0x51,0x6f,0x90,0x9e, ++0x4b,0xe0,0xff,0xd3,0x94,0x13,0x40,0x07,0x90,0x96,0x43,0x74,0x03,0xf0,0x22,0xef, ++0xd3,0x94,0x0b,0x40,0x07,0x90,0x96,0x43,0x74,0x02,0xf0,0x22,0xef,0xd3,0x94,0x03, ++0x40,0x07,0x90,0x96,0x43,0x74,0x01,0xf0,0x22,0xe4,0x90,0x96,0x43,0xf0,0x22,0xe0, ++0xfd,0x74,0x26,0x25,0x59,0xf5,0x82,0xe4,0x34,0x9d,0xf5,0x83,0xed,0xf0,0xaf,0x59, ++0xd3,0x10,0xaf,0x01,0xc3,0xc0,0xd0,0xef,0xc3,0x94,0x20,0x50,0x0e,0x74,0x84,0x2f, ++0xf5,0x82,0xe4,0x34,0x04,0xf5,0x83,0xed,0xf0,0x80,0x29,0x74,0xa6,0x2f,0xf5,0x82, ++0xe4,0x34,0x9c,0xf5,0x83,0xed,0xf0,0x90,0x9e,0x75,0xef,0xf0,0x24,0xa6,0xf5,0x82, ++0xe4,0x34,0x9c,0xf5,0x83,0xe0,0x90,0x9e,0x76,0xf0,0x7b,0x01,0x7a,0x9e,0x79,0x75, ++0x7d,0x02,0x51,0xc9,0xd0,0xd0,0x92,0xaf,0x22,0xd3,0x10,0xaf,0x01,0xc3,0xc0,0xd0, ++0x90,0x9e,0x94,0x12,0x43,0x8b,0x90,0x9e,0x97,0xe0,0x54,0xf0,0x44,0x06,0xff,0xf0, ++0xed,0x54,0x0f,0xc4,0x54,0xf0,0xfe,0xef,0x54,0x0f,0x4e,0xf0,0x90,0x9e,0x94,0x12, ++0x43,0x6b,0x90,0x9e,0x91,0x12,0x43,0x8b,0x7b,0x01,0x7a,0x9e,0x79,0x97,0x71,0xd4, ++0xd0,0xd0,0x92,0xaf,0x22,0x8f,0x50,0x8d,0x51,0xe5,0x51,0x54,0x1f,0xf5,0x56,0x74, ++0x01,0x2f,0xf5,0x82,0xe4,0x34,0x94,0xf5,0x83,0xe0,0xf5,0x54,0x90,0x04,0xfd,0xe0, ++0xb4,0x01,0x05,0x75,0x57,0x03,0x80,0x03,0x75,0x57,0x01,0xeb,0xc3,0x95,0x57,0x40, ++0x04,0xaf,0x50,0x80,0x33,0xe5,0x54,0x25,0x53,0xf5,0x55,0xe5,0x56,0x90,0x41,0xd6, ++0x93,0xff,0xe5,0x55,0xd3,0x9f,0x74,0x01,0x40,0x11,0x25,0x50,0xf5,0x82,0xe4,0x34, ++0x94,0xf5,0x83,0xe4,0xf0,0xad,0x51,0xaf,0x50,0x41,0x80,0x25,0x50,0xf5,0x82,0xe4, ++0x34,0x94,0xf5,0x83,0xe5,0x55,0xf0,0x22,0xad,0x07,0x75,0xf0,0x09,0xed,0x90,0x96, ++0x48,0x12,0x43,0x5f,0xe0,0xff,0x74,0x67,0x2d,0xf5,0x82,0xe4,0x34,0x9d,0xf5,0x83, ++0xe0,0x54,0x1f,0xf5,0x58,0xd3,0x9f,0x40,0x02,0x8f,0x58,0xe5,0x58,0x25,0xe0,0x24, ++0x9e,0xf5,0x82,0xe4,0x34,0x41,0xf5,0x83,0xe4,0x93,0xfe,0x74,0x01,0x93,0xff,0xe5, ++0x58,0x25,0xe0,0x24,0x66,0xf5,0x82,0xe4,0x34,0x41,0xf5,0x83,0x74,0x01,0x93,0x2f, ++0xff,0xe4,0x93,0x3e,0xc3,0x13,0xfe,0xef,0x13,0xff,0xed,0x25,0xe0,0x24,0xc2,0xf5, ++0x82,0xe4,0x34,0x95,0xf5,0x83,0xee,0xf0,0xa3,0xef,0xf0,0xaf,0x05,0xad,0x58,0x51, ++0x80,0xaf,0x58,0x22,0xd3,0x10,0xaf,0x01,0xc3,0xc0,0xd0,0x90,0x9e,0x8e,0x12,0x43, ++0x8b,0x90,0x9e,0xaf,0xe0,0xff,0x04,0xf0,0x90,0x00,0x01,0xef,0x12,0x42,0x5f,0x7f, ++0xaf,0x7e,0x01,0x91,0x67,0xef,0x60,0x49,0x90,0x9e,0x8e,0x12,0x43,0x6b,0x8b,0x1e, ++0x8a,0x1f,0x89,0x20,0x75,0x21,0x02,0x7b,0x01,0x7a,0x01,0x79,0xa0,0x12,0x45,0x09, ++0x90,0x9e,0x91,0x12,0x43,0x6b,0x8b,0x1e,0x8a,0x1f,0x89,0x20,0x90,0x9e,0x8e,0x12, ++0x43,0x6b,0x12,0x29,0xd9,0xff,0xc4,0x54,0x0f,0xf5,0x21,0x7b,0x01,0x7a,0x01,0x79, ++0xa2,0x12,0x45,0x09,0x90,0x01,0xaf,0x74,0xff,0xf0,0x90,0x01,0xcb,0xe0,0x64,0x80, ++0xf0,0xd0,0xd0,0x92,0xaf,0x22,0x90,0x9e,0x2f,0xe0,0x54,0xf0,0x44,0x03,0xf0,0x54, ++0x0f,0x44,0x80,0xf0,0x7b,0x00,0x7a,0x00,0x79,0x13,0x90,0x9e,0x91,0x12,0x43,0x8b, ++0x0b,0x7a,0x9e,0x79,0x2f,0x61,0xd4,0xd3,0x10,0xaf,0x01,0xc3,0xc0,0xd0,0x90,0x9e, ++0x9d,0xee,0xf0,0xa3,0xef,0xf0,0xe4,0xa3,0xf0,0xa3,0xf0,0x90,0x9e,0x9d,0xe0,0xfe, ++0xa3,0xe0,0xf5,0x82,0x8e,0x83,0xe0,0x60,0x2d,0xc3,0x90,0x9e,0xa0,0xe0,0x94,0xe8, ++0x90,0x9e,0x9f,0xe0,0x94,0x03,0x40,0x0b,0x90,0x01,0xc6,0xe0,0x44,0x10,0xf0,0x7f, ++0x00,0x80,0x15,0x90,0x9e,0x9f,0xe4,0x75,0xf0,0x01,0x12,0x42,0x81,0x7f,0x0a,0x7e, ++0x00,0x12,0x37,0x54,0x80,0xc5,0x7f,0x01,0xd0,0xd0,0x92,0xaf,0x22,0xac,0x07,0xec, ++0xc3,0x94,0x20,0x50,0x0d,0x74,0x84,0x2c,0xf5,0x82,0xe4,0x34,0x04,0xf5,0x83,0xe0, ++0x80,0x0b,0x74,0xa6,0x2c,0xf5,0x82,0xe4,0x34,0x9c,0xf5,0x83,0xe0,0x54,0x7f,0xf5, ++0x64,0xe5,0x64,0x54,0x1f,0xff,0x90,0x9e,0x40,0xf0,0x75,0xf0,0x09,0xec,0x90,0x96, ++0x49,0x12,0x43,0x5f,0xe0,0x90,0x9e,0x42,0xf0,0x75,0xf0,0x09,0xec,0x90,0x96,0x48, ++0x12,0x43,0x5f,0xe0,0xfe,0x90,0x9e,0x43,0xf0,0xec,0x25,0xe0,0x24,0xc6,0xf5,0x82, ++0xe4,0x34,0x9b,0xf5,0x83,0xe0,0xfb,0xa3,0xe0,0x90,0x9e,0x44,0xcb,0xf0,0xa3,0xeb, ++0xf0,0xec,0x25,0xe0,0x24,0x02,0xf5,0x82,0xe4,0x34,0x95,0xf5,0x83,0xe0,0xfb,0xa3, ++0xe0,0x90,0x9e,0x46,0xcb,0xf0,0xa3,0xeb,0xf0,0xef,0xd3,0x9e,0x40,0x0a,0x90,0x9e, ++0x43,0xe0,0x90,0x9e,0x40,0xf0,0xf5,0x64,0xed,0x70,0x02,0xc1,0x13,0x90,0x9e,0x41, ++0xed,0xf0,0xe5,0x64,0x30,0xe6,0x0a,0x90,0x9e,0x40,0xe0,0xf5,0x64,0xa3,0xe0,0x14, ++0xf0,0x90,0x9e,0x41,0xe0,0x70,0x02,0xc1,0x13,0x90,0x9e,0x40,0xe0,0xff,0xd3,0x94, ++0x00,0x50,0x02,0xc1,0x13,0xe4,0x90,0x9e,0x3f,0xf0,0xef,0x14,0x90,0x9e,0x3e,0xf0, ++0x90,0x9e,0x42,0xe0,0xfd,0x90,0x9e,0x3e,0xe0,0xff,0xd3,0x9d,0x40,0x6b,0xef,0x94, ++0x10,0x40,0x21,0xef,0x24,0xf0,0xff,0x74,0x01,0x7e,0x00,0xa8,0x07,0x08,0x80,0x05, ++0xc3,0x33,0xce,0x33,0xce,0xd8,0xf9,0xff,0x90,0x9e,0x46,0xe0,0x5e,0xfe,0xa3,0xe0, ++0x5f,0x4e,0x70,0x27,0x90,0x9e,0x3e,0xe0,0xff,0xc3,0x94,0x10,0x50,0x33,0x74,0x01, ++0x7e,0x00,0xa8,0x07,0x08,0x80,0x05,0xc3,0x33,0xce,0x33,0xce,0xd8,0xf9,0xff,0x90, ++0x9e,0x44,0xe0,0x5e,0xfe,0xa3,0xe0,0x5f,0x4e,0x60,0x16,0x90,0x9e,0x3e,0xe0,0xf5, ++0x64,0xa3,0xe0,0x04,0xf0,0x90,0x9e,0x41,0xe0,0xff,0x90,0x9e,0x3f,0xe0,0x6f,0x60, ++0x08,0x90,0x9e,0x3e,0xe0,0x14,0xf0,0x80,0x87,0x90,0x9e,0x41,0xe0,0xff,0x90,0x9e, ++0x3f,0xe0,0xc3,0x9f,0x50,0x0d,0x90,0x9e,0x3e,0xe0,0xb5,0x05,0x06,0x90,0x9e,0x42, ++0xe0,0xf5,0x64,0xe5,0x64,0x25,0xe0,0x24,0x9e,0xf5,0x82,0xe4,0x34,0x41,0xf5,0x83, ++0xe4,0x93,0xfe,0x74,0x01,0x93,0xff,0xe5,0x64,0x25,0xe0,0x24,0x66,0xf5,0x82,0xe4, ++0x34,0x41,0xf5,0x83,0x74,0x01,0x93,0x2f,0xff,0xe4,0x93,0x3e,0xc3,0x13,0xfe,0xef, ++0x13,0xff,0xec,0x25,0xe0,0x24,0xc2,0xf5,0x82,0xe4,0x34,0x95,0xf5,0x83,0xee,0xf0, ++0xa3,0xef,0xf0,0xaf,0x04,0xad,0x64,0x51,0x80,0xaf,0x64,0x22,0x8f,0x77,0x12,0x45, ++0xa6,0xef,0x64,0x01,0x70,0x2e,0x90,0x9e,0x52,0x12,0x47,0xcc,0xe5,0x77,0x60,0x10, ++0x74,0x21,0x2f,0xf5,0x82,0xe4,0x34,0xfc,0xf5,0x83,0xe0,0x44,0x10,0xf0,0x80,0x0e, ++0x74,0x21,0x2f,0xf5,0x82,0xe4,0x34,0xfc,0xf5,0x83,0xe0,0x54,0xef,0xf0,0x90,0x04, ++0x1f,0x74,0x20,0xf0,0x22,0x90,0x06,0x04,0xe0,0x54,0xbf,0xf0,0xef,0x60,0x09,0xe5, ++0x22,0xb4,0x01,0x04,0xe4,0xff,0xd1,0x5c,0x53,0x23,0xf0,0x43,0x23,0x0c,0x22,0x90, ++0x01,0x3c,0x74,0xff,0xf0,0xa3,0xf0,0xa3,0xf0,0x90,0x01,0x34,0xf0,0xa3,0xf0,0xa3, ++0xf0,0xa3,0xf0,0xfd,0x7f,0x54,0x12,0x4c,0xe3,0x7d,0xff,0x7f,0x55,0x12,0x4c,0xe3, ++0x7d,0xff,0x7f,0x56,0x12,0x4c,0xe3,0x7d,0xff,0x7f,0x57,0x02,0x4c,0xe3,0x90,0x00, ++0x02,0xe0,0x54,0xe0,0x7f,0x01,0x60,0x02,0x7f,0x00,0x22,0x90,0x00,0xf3,0xe0,0x7f, ++0x00,0x30,0xe3,0x03,0x7f,0x01,0x22,0x22,0x90,0x01,0x64,0x74,0xa0,0xf0,0x22,0xc0, ++0xe0,0xc0,0xf0,0xc0,0x83,0xc0,0x82,0xc0,0xd0,0x75,0xd0,0x00,0xc0,0x00,0xc0,0x01, ++0xc0,0x02,0xc0,0x03,0xc0,0x04,0xc0,0x05,0xc0,0x06,0xc0,0x07,0x90,0x01,0xc4,0x74, ++0xff,0xf0,0x74,0x5e,0xa3,0xf0,0x53,0x91,0xef,0x90,0x00,0x51,0xe0,0xff,0x90,0x00, ++0x55,0xe0,0x5f,0xf5,0x3d,0xe5,0x3d,0x30,0xe6,0x18,0x74,0x40,0xf0,0x90,0x9e,0x1d, ++0xe0,0x54,0x03,0xff,0xbf,0x03,0x0b,0x90,0x9e,0x1a,0xe0,0x60,0x05,0x7f,0x01,0x12, ++0x4c,0xf8,0xe5,0x3d,0x30,0xe7,0x15,0x90,0x00,0x55,0x74,0x80,0xf0,0x90,0x9e,0x1d, ++0xe0,0x54,0x03,0xff,0xbf,0x03,0x05,0x7f,0x02,0x12,0x4c,0xf8,0x90,0x01,0xc4,0x74, ++0xff,0xf0,0x74,0x5e,0xa3,0xf0,0xd0,0x07,0xd0,0x06,0xd0,0x05,0xd0,0x04,0xd0,0x03, ++0xd0,0x02,0xd0,0x01,0xd0,0x00,0xd0,0xd0,0xd0,0x82,0xd0,0x83,0xd0,0xf0,0xd0,0xe0, ++0x32,0x8f,0x6b,0x8c,0x6c,0x8d,0x6d,0x22,0x8f,0x6e,0x8c,0x6f,0x8d,0x70,0x22,0xe4, ++0xf5,0x22,0xf5,0x26,0xf5,0x25,0x75,0x24,0x0c,0x75,0x23,0x0c,0x90,0x9e,0x73,0xf0, ++0x90,0x9e,0x71,0xf0,0x90,0x9e,0x70,0xf0,0x90,0x9e,0x72,0x04,0xf0,0x90,0x9e,0x64, ++0xf0,0xe4,0x90,0x9e,0x74,0xf0,0x90,0x9e,0x66,0xf0,0x90,0x9e,0x6e,0x74,0x07,0xf0, ++0xe4,0x90,0x9e,0x65,0xf0,0x90,0x9e,0x6c,0xf0,0xa3,0x74,0x02,0xf0,0x90,0x9e,0x6a, ++0x14,0xf0,0xa3,0x74,0x03,0xf0,0x90,0x9e,0x69,0x74,0x14,0xf0,0x90,0x9e,0x6f,0x74, ++0x05,0xf0,0xe4,0x90,0x9e,0x68,0xf0,0x90,0x9e,0x63,0xf0,0x90,0x9e,0x5f,0xf0,0x22, ++0xe4,0x90,0x9e,0x74,0xf0,0x90,0x9e,0x65,0xf0,0xf5,0x26,0x22,0x8b,0x59,0x8a,0x5a, ++0x89,0x5b,0x11,0x00,0xab,0x59,0xaa,0x5a,0xa9,0x5b,0x12,0x29,0xd9,0xf5,0x25,0x14, ++0x60,0x0e,0x14,0x60,0x1e,0x14,0x60,0x2f,0x24,0x03,0x70,0x40,0x7f,0x01,0x80,0x3a, ++0xab,0x59,0xaa,0x5a,0xa9,0x5b,0x90,0x00,0x02,0x12,0x42,0x20,0xfd,0xe4,0xff,0x11, ++0x6d,0x80,0x27,0xab,0x59,0xaa,0x5a,0xa9,0x5b,0x90,0x00,0x02,0x12,0x42,0x20,0xfd, ++0x7f,0x01,0x11,0x6d,0x1f,0x80,0x13,0xab,0x59,0xaa,0x5a,0xa9,0x5b,0x90,0x00,0x02, ++0x12,0x42,0x20,0xfd,0x7f,0x02,0x11,0x6d,0xe4,0xff,0x11,0x98,0x22,0xef,0x24,0xfe, ++0x60,0x0b,0x04,0x70,0x22,0x90,0x9e,0x72,0x74,0x01,0xf0,0x80,0x16,0xed,0x70,0x0a, ++0x90,0x9e,0x6f,0xe0,0x90,0x9e,0x72,0xf0,0x80,0x05,0x90,0x9e,0x72,0xed,0xf0,0x90, ++0x9e,0x72,0xe0,0x90,0x9e,0x64,0xf0,0x22,0xef,0x64,0x01,0x70,0x2f,0x7d,0x7c,0x7f, ++0x02,0x12,0x36,0x75,0x7d,0x02,0x7f,0x03,0x12,0x36,0x75,0x90,0x01,0x57,0xe4,0xf0, ++0x90,0x01,0x3c,0x74,0x02,0xf0,0x12,0x47,0x2b,0xe4,0xff,0x31,0x1f,0x90,0x06,0x04, ++0xe0,0x54,0x7f,0xf0,0x90,0x06,0x0a,0xe0,0x54,0xf8,0xf0,0x22,0x90,0x01,0x36,0x74, ++0x7c,0xf0,0xa3,0x74,0x02,0xf0,0x7d,0x7c,0xff,0x12,0x36,0xe6,0x7d,0x02,0x7f,0x03, ++0x12,0x36,0xe6,0x90,0x06,0x04,0xe0,0x44,0x80,0xf0,0x90,0x06,0x0a,0xe0,0x44,0x07, ++0xf0,0x90,0x9e,0x6c,0xe0,0xa3,0xe0,0x90,0x05,0x58,0xf0,0xe5,0x22,0x30,0xe0,0x19, ++0x90,0x9e,0x66,0xe0,0x70,0x18,0xe0,0x04,0xf0,0xe5,0x23,0x54,0x0f,0xc3,0x94,0x04, ++0x50,0x0c,0x7d,0x01,0x7f,0x04,0x02,0x47,0x2f,0xe4,0x90,0x9e,0x66,0xf0,0x22,0xef, ++0x60,0x0b,0x90,0x9e,0x60,0xe0,0xb4,0x01,0x10,0xe4,0xff,0x80,0x09,0x90,0x9e,0x60, ++0xe0,0xb4,0x01,0x05,0x7f,0x01,0x12,0x77,0xe4,0x22,0x90,0x01,0x37,0x74,0x02,0xf0, ++0x90,0x05,0x22,0x74,0xff,0xf0,0x31,0xc3,0xef,0x70,0x06,0x90,0x01,0xc8,0x74,0xfd, ++0xf0,0x7d,0x02,0x7f,0x03,0x12,0x36,0xe6,0xe5,0x25,0x60,0x04,0x7f,0x01,0x31,0x1f, ++0x51,0x04,0x53,0x23,0xf0,0x43,0x23,0x02,0x22,0xd3,0x10,0xaf,0x01,0xc3,0xc0,0xd0, ++0x90,0x00,0x01,0x12,0x42,0x20,0x90,0x9e,0x73,0xf0,0x90,0x00,0x03,0x12,0x42,0x20, ++0x90,0x9e,0x63,0xf0,0x12,0x29,0xd9,0x65,0x25,0x60,0x02,0x11,0x0c,0xd0,0xd0,0x92, ++0xaf,0x22,0x7d,0x02,0x7f,0x03,0x12,0x36,0x75,0xe5,0x25,0x14,0x24,0xfd,0x50,0x02, ++0x80,0x20,0x90,0x9e,0x73,0xe0,0x60,0x06,0x7d,0x01,0x7f,0x0c,0x80,0x0d,0xe5,0x23, ++0x54,0x0f,0xc3,0x94,0x04,0x50,0x07,0x7d,0x01,0x7f,0x04,0x12,0x47,0x2f,0xe4,0xff, ++0x31,0x1f,0x22,0xe4,0x90,0x9e,0xa9,0xf0,0xa3,0xf0,0x90,0x05,0xf8,0xe0,0x70,0x0f, ++0xa3,0xe0,0x70,0x0b,0xa3,0xe0,0x70,0x07,0xa3,0xe0,0x70,0x03,0x7f,0x01,0x22,0xd3, ++0x90,0x9e,0xaa,0xe0,0x94,0xe8,0x90,0x9e,0xa9,0xe0,0x94,0x03,0x40,0x03,0x7f,0x00, ++0x22,0x7f,0x32,0x7e,0x00,0x12,0x37,0x54,0x90,0x9e,0xa9,0xe4,0x75,0xf0,0x01,0x12, ++0x42,0x81,0x80,0xc6,0x7f,0x78,0x7e,0x08,0x12,0x27,0xde,0x90,0x9d,0xff,0x12,0x2a, ++0x7f,0x7f,0x04,0x7e,0x0c,0x12,0x27,0xde,0x90,0x9e,0x03,0x12,0x2a,0x7f,0x7f,0x00, ++0x7e,0x08,0x12,0x27,0xde,0x90,0x9e,0x07,0x12,0x2a,0x7f,0x90,0x9e,0x60,0xe0,0x90, ++0x9d,0xff,0xb4,0x01,0x0d,0x12,0x43,0x53,0xef,0x54,0xc7,0xff,0xed,0x54,0xc7,0xfd, ++0x80,0x07,0x12,0x43,0x53,0xef,0x54,0xc7,0xff,0xec,0x90,0x80,0x85,0x12,0x2a,0x7f, ++0x7f,0x78,0x7e,0x08,0x12,0x2f,0xd9,0x90,0x9e,0x03,0x12,0x43,0x53,0xef,0x54,0x0f, ++0xff,0xec,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0x04,0x7e,0x0c,0x12,0x2f,0xd9,0x90, ++0x9e,0x07,0x12,0x43,0x53,0xef,0x44,0x02,0xff,0xec,0x90,0x80,0x85,0x12,0x2a,0x7f, ++0x7f,0x00,0x7e,0x08,0x12,0x2f,0xd9,0x7f,0x70,0x7e,0x0e,0x12,0x27,0xde,0x90,0x9e, ++0x0b,0x12,0x2a,0x7f,0x90,0x80,0x85,0x12,0x2a,0x8b,0x00,0x1b,0x25,0xa0,0x7f,0x70, ++0x7e,0x0e,0x12,0x2f,0xd9,0x90,0x80,0x59,0x12,0x2a,0x8b,0x00,0x00,0x00,0x00,0xe4, ++0xfd,0xff,0x12,0x34,0x81,0x90,0x9e,0x60,0xe0,0xb4,0x01,0x11,0x90,0x80,0x59,0x12, ++0x2a,0x8b,0x00,0x00,0x00,0x00,0xe4,0xfd,0x7f,0x01,0x12,0x34,0x81,0x90,0x00,0x11, ++0xe0,0x54,0xf6,0xf0,0x02,0x4b,0xdb,0x12,0x4b,0xc4,0xef,0x64,0x01,0x60,0x08,0x90, ++0x01,0xb9,0x74,0x01,0xf0,0x80,0x30,0x90,0x9e,0x71,0xe0,0x60,0x08,0x90,0x01,0xb9, ++0x74,0x02,0xf0,0x80,0x22,0x90,0x9e,0x70,0xe0,0x60,0x08,0x90,0x01,0xb9,0x74,0x04, ++0xf0,0x80,0x14,0xe5,0x24,0x54,0x0f,0xd3,0x94,0x04,0x40,0x08,0x90,0x01,0xb9,0x74, ++0x08,0xf0,0x80,0x03,0x7f,0x01,0x22,0x90,0x01,0xb8,0x74,0x08,0xf0,0x7f,0x00,0x22, ++0x12,0x4b,0xc4,0xef,0x64,0x01,0x60,0x08,0x90,0x01,0xb9,0x74,0x01,0xf0,0x80,0x4a, ++0xe5,0x26,0x54,0x03,0x60,0x08,0x90,0x01,0xb9,0x74,0x02,0xf0,0x80,0x3c,0xe5,0x24, ++0x54,0x0f,0xd3,0x94,0x02,0x40,0x08,0x90,0x01,0xb9,0x74,0x04,0xf0,0x80,0x2b,0xe5, ++0x26,0x30,0xe2,0x08,0x90,0x01,0xb9,0x74,0x08,0xf0,0x80,0x1e,0xe5,0x26,0x30,0xe4, ++0x08,0x90,0x01,0xb9,0x74,0x10,0xf0,0x80,0x11,0x90,0x9e,0x66,0xe0,0x60,0x08,0x90, ++0x01,0xb9,0x74,0x20,0xf0,0x80,0x03,0x7f,0x01,0x22,0x90,0x01,0xb8,0x74,0x04,0xf0, ++0x7f,0x00,0x22,0xe5,0x12,0x60,0x08,0x90,0x01,0xb9,0x74,0x01,0xf0,0x80,0x5b,0xe5, ++0x24,0x54,0x0f,0xd3,0x94,0x01,0x40,0x08,0x90,0x01,0xb9,0x74,0x02,0xf0,0x80,0x4a, ++0x90,0x02,0x87,0xe0,0x60,0x08,0x90,0x01,0xb9,0x74,0x04,0xf0,0x80,0x3c,0x90,0x9e, ++0x5e,0xe0,0xb4,0x01,0x10,0x90,0x9e,0x4d,0xe0,0xfe,0xa3,0xe0,0xf5,0x82,0x8e,0x83, ++0xe0,0x60,0x16,0x80,0x25,0x90,0x9e,0x5e,0xe0,0x70,0x0e,0x90,0x01,0xaf,0xe0,0x60, ++0x08,0x90,0x01,0xb9,0x74,0x08,0xf0,0x80,0x11,0x90,0x9e,0x68,0xe0,0x70,0x08,0x90, ++0x01,0xb9,0x74,0x10,0xf0,0x80,0x03,0x7f,0x01,0x22,0x90,0x01,0xb8,0x74,0x02,0xf0, ++0x7f,0x00,0x22,0x90,0x9e,0xae,0xef,0xf0,0x91,0x0c,0x90,0x9e,0xae,0xe0,0x60,0x05, ++0x90,0x05,0x22,0xe4,0xf0,0x53,0x23,0xf0,0x43,0x23,0x04,0x22,0x90,0x00,0x11,0xe0, ++0x44,0x09,0xf0,0x12,0x4b,0xdb,0x90,0x9d,0xff,0x12,0x43,0x53,0x90,0x80,0x85,0x12, ++0x2a,0x7f,0x7f,0x78,0x7e,0x08,0x12,0x2f,0xd9,0x90,0x9e,0x03,0x12,0x43,0x53,0x90, ++0x80,0x85,0x12,0x2a,0x7f,0x7f,0x04,0x7e,0x0c,0x12,0x2f,0xd9,0x90,0x9e,0x07,0x12, ++0x43,0x53,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0x00,0x7e,0x08,0x12,0x2f,0xd9,0x90, ++0x9e,0x0b,0x12,0x43,0x53,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0x70,0x7e,0x0e,0x12, ++0x2f,0xd9,0x90,0x80,0x59,0x12,0x2a,0x8b,0x00,0x03,0x2d,0x95,0xe4,0xfd,0xff,0x12, ++0x34,0x81,0x90,0x9e,0x60,0xe0,0xb4,0x01,0x11,0x90,0x80,0x59,0x12,0x2a,0x8b,0x00, ++0x03,0x2d,0x95,0xe4,0xfd,0x7f,0x01,0x12,0x34,0x81,0x22,0x8f,0x27,0xe4,0x90,0x9e, ++0xa7,0xf0,0xa3,0xf0,0x90,0x01,0x09,0xe0,0x7f,0x00,0x30,0xe7,0x02,0x7f,0x01,0xef, ++0x65,0x27,0x60,0x3e,0xc3,0x90,0x9e,0xa8,0xe0,0x94,0x88,0x90,0x9e,0xa7,0xe0,0x94, ++0x13,0x40,0x08,0x90,0x01,0xc6,0xe0,0x44,0x80,0xf0,0x22,0x90,0x9e,0xa7,0xe4,0x75, ++0xf0,0x01,0x12,0x42,0x81,0x7f,0x14,0x7e,0x00,0x12,0x37,0x54,0xd3,0x90,0x9e,0xa8, ++0xe0,0x94,0x32,0x90,0x9e,0xa7,0xe0,0x94,0x00,0x40,0xb9,0x90,0x01,0xc7,0xe0,0x30, ++0xe0,0xb2,0x22,0xe5,0x24,0x30,0xe6,0x19,0xe5,0x24,0x54,0x0f,0xff,0x90,0x9e,0x62, ++0xe0,0xfe,0x4f,0x90,0x01,0x2f,0xf0,0xee,0x64,0x80,0x90,0x9e,0x62,0xf0,0x53,0x24, ++0xbf,0x22,0x8f,0x76,0x12,0x45,0xa6,0xef,0x64,0x01,0x70,0x2e,0x90,0x9e,0x53,0x12, ++0x47,0xcc,0xe5,0x76,0x60,0x10,0x74,0x21,0x2f,0xf5,0x82,0xe4,0x34,0xfc,0xf5,0x83, ++0xe0,0x44,0x10,0xf0,0x80,0x0e,0x74,0x21,0x2f,0xf5,0x82,0xe4,0x34,0xfc,0xf5,0x83, ++0xe0,0x54,0xef,0xf0,0x90,0x04,0x1f,0x74,0x20,0xf0,0x22,0xe5,0x22,0x64,0x01,0x70, ++0x61,0xe5,0x25,0x60,0x5d,0xe5,0x25,0x64,0x02,0x60,0x06,0xe5,0x25,0x64,0x05,0x70, ++0x27,0x90,0x06,0xab,0xe0,0x90,0x9e,0x64,0xf0,0x90,0x06,0xaa,0xe0,0x90,0x9e,0x72, ++0xf0,0x90,0x9e,0x64,0xe0,0x70,0x07,0x90,0x9e,0x72,0xe0,0xff,0x80,0x05,0x90,0x9e, ++0x64,0xe0,0xff,0x90,0x9e,0x64,0xef,0xf0,0x90,0x9e,0x66,0xe0,0x60,0x03,0xe0,0x14, ++0xf0,0xe4,0x90,0x9e,0x65,0xf0,0x90,0x01,0x57,0xf0,0x90,0x01,0x3c,0x74,0x02,0xf0, ++0x53,0x26,0xfd,0x53,0x26,0xef,0xe5,0x25,0x14,0x24,0xfd,0x50,0x02,0x80,0x03,0x12, ++0x45,0x53,0x22,0xe4,0xff,0xe5,0x25,0x60,0x5f,0xe5,0x22,0x64,0x01,0x70,0x59,0xe5, ++0x25,0x14,0x60,0x2b,0x24,0xfd,0x60,0x27,0x24,0x02,0x24,0xfb,0x50,0x02,0x80,0x21, ++0x90,0x9e,0x64,0xe0,0x14,0xf0,0xe0,0x60,0x04,0xa3,0xe0,0x60,0x14,0x90,0x9e,0x64, ++0xe0,0x70,0x08,0x90,0x9e,0x72,0xe0,0x90,0x9e,0x64,0xf0,0x7f,0x01,0x80,0x02,0x7f, ++0x01,0xef,0x60,0x24,0x43,0x26,0x10,0xe4,0x90,0x9e,0x86,0xf0,0x90,0x9e,0x6e,0x12, ++0x44,0x56,0x90,0x01,0x57,0x74,0x05,0xf0,0xe5,0x23,0x54,0x0f,0xc3,0x94,0x04,0x50, ++0x07,0x7d,0x01,0x7f,0x04,0x12,0x47,0x2f,0x22,0xe5,0x25,0x60,0x39,0x90,0x9e,0x74, ++0xe0,0x60,0x0d,0xe4,0xf0,0x53,0x26,0xfd,0xe5,0x26,0x54,0x07,0x70,0x28,0x80,0x23, ++0x90,0x9e,0x65,0xe0,0x04,0xf0,0x53,0x26,0xef,0x90,0x9e,0x6a,0xe0,0xff,0x90,0x9e, ++0x65,0xe0,0xd3,0x9f,0x40,0x0d,0xe5,0x22,0xb4,0x01,0x0b,0xa3,0xe0,0x70,0x07,0xe0, ++0x04,0xf0,0x22,0x12,0x44,0xd1,0x22,0xef,0xc3,0x94,0x20,0x50,0x39,0xef,0x30,0xe0, ++0x17,0xed,0xc4,0x54,0xf0,0xfd,0xef,0xc3,0x13,0xfe,0x24,0xa4,0xf5,0x82,0xe4,0x34, ++0x04,0xf5,0x83,0xe0,0x54,0x0f,0x80,0x10,0xef,0xc3,0x13,0xfe,0x24,0xa4,0xf5,0x82, ++0xe4,0x34,0x04,0xf5,0x83,0xe0,0x54,0xf0,0xf0,0x74,0xa4,0x2e,0xf5,0x82,0xe4,0x34, ++0x04,0xf5,0x83,0xe0,0x4d,0xf0,0x22,0xad,0x07,0xed,0xc3,0x94,0x20,0x50,0x0d,0x74, ++0x84,0x2d,0xf5,0x82,0xe4,0x34,0x04,0xf5,0x83,0xe0,0x80,0x0b,0x74,0xa6,0x2d,0xf5, ++0x82,0xe4,0x34,0x9c,0xf5,0x83,0xe0,0x54,0x7f,0xf5,0x64,0xe5,0x64,0x54,0x1f,0xfc, ++0x75,0xf0,0x09,0xed,0x90,0x96,0x48,0x12,0x43,0x5f,0xe0,0xff,0x90,0x9e,0x3e,0xf0, ++0xed,0x25,0xe0,0x24,0x02,0xf5,0x82,0xe4,0x34,0x95,0xf5,0x83,0xe0,0xfb,0xa3,0xe0, ++0x90,0x9e,0x3f,0xcb,0xf0,0xa3,0xeb,0xf0,0xed,0x25,0xe0,0x24,0xc6,0xf5,0x82,0xe4, ++0x34,0x9b,0xf5,0x83,0xe0,0xfb,0xa3,0xe0,0x90,0x9e,0x41,0xcb,0xf0,0xa3,0xeb,0xf0, ++0xec,0x25,0xe0,0x24,0x66,0xf5,0x82,0xe4,0x34,0x41,0xf5,0x83,0xe4,0x93,0xfa,0x74, ++0x01,0x93,0xfb,0xed,0x25,0xe0,0x24,0xc2,0xf5,0x82,0xe4,0x34,0x95,0xf5,0x83,0xea, ++0xf0,0xa3,0xeb,0xf0,0xec,0xc3,0x9f,0x40,0x02,0xe1,0xa5,0x74,0x67,0x2d,0xf5,0x82, ++0xe4,0x34,0x9d,0xf5,0x83,0xec,0xf0,0x04,0xfb,0x90,0x9e,0x3e,0xe0,0xff,0xeb,0xd3, ++0x9f,0x40,0x02,0xe1,0xd6,0xeb,0xc3,0x94,0x10,0x40,0x21,0xeb,0x24,0xf0,0xff,0x74, ++0x01,0x7e,0x00,0xa8,0x07,0x08,0x80,0x05,0xc3,0x33,0xce,0x33,0xce,0xd8,0xf9,0xff, ++0x90,0x9e,0x3f,0xe0,0x5e,0xfe,0xa3,0xe0,0x5f,0x4e,0x70,0x23,0xeb,0xc3,0x94,0x10, ++0x50,0x40,0x74,0x01,0x7e,0x00,0xa8,0x03,0x08,0x80,0x05,0xc3,0x33,0xce,0x33,0xce, ++0xd8,0xf9,0xff,0x90,0x9e,0x41,0xe0,0x5e,0xfe,0xa3,0xe0,0x5f,0x4e,0x60,0x23,0xbb, ++0x11,0x09,0x90,0x9e,0x40,0xe0,0x30,0xe7,0x02,0x7b,0x17,0xeb,0x64,0x13,0x60,0x03, ++0xbb,0x12,0x09,0x90,0x9e,0x3f,0xe0,0x30,0xe0,0x02,0x7b,0x18,0xac,0x03,0x8c,0x64, ++0x80,0x34,0x0b,0x80,0x84,0x90,0x9e,0x3e,0xe0,0xfb,0x6c,0x70,0x69,0x74,0x67,0x2d, ++0xf5,0x82,0xe4,0x34,0x9d,0xf5,0x83,0xec,0xf0,0x75,0xf0,0x09,0xed,0x90,0x96,0x4a, ++0x12,0x43,0x5f,0xe0,0xb4,0x01,0x0c,0xe5,0x64,0x20,0xe6,0x07,0xec,0x44,0x40,0xf5, ++0x64,0x80,0x03,0xaf,0x64,0x22,0xec,0x25,0xe0,0x24,0x9e,0xf5,0x82,0xe4,0x34,0x41, ++0xf5,0x83,0xe4,0x93,0xfe,0x74,0x01,0x93,0xff,0xec,0x25,0xe0,0x24,0x66,0xf5,0x82, ++0xe4,0x34,0x41,0xf5,0x83,0x74,0x01,0x93,0x2f,0xff,0xe4,0x93,0x3e,0xc3,0x13,0xfe, ++0xef,0x13,0xff,0xed,0x25,0xe0,0x24,0xc2,0xf5,0x82,0xe4,0x34,0x95,0xf5,0x83,0xee, ++0xf0,0xa3,0xef,0xf0,0x80,0x5b,0xec,0xd3,0x9b,0x40,0x56,0x90,0x9e,0x3e,0xe0,0xff, ++0x74,0x67,0x2d,0xf5,0x82,0xe4,0x34,0x9d,0xf5,0x83,0xef,0xf0,0xac,0x07,0x8f,0x64, ++0xec,0x25,0xe0,0x24,0x9e,0xf5,0x82,0xe4,0x34,0x41,0xf5,0x83,0xe4,0x93,0xfe,0x74, ++0x01,0x93,0xff,0xec,0x25,0xe0,0x24,0x66,0xf5,0x82,0xe4,0x34,0x41,0xf5,0x83,0x74, ++0x01,0x93,0x2f,0xff,0xe4,0x93,0x3e,0xc3,0x13,0xfe,0xef,0x13,0xff,0xed,0x25,0xe0, ++0x24,0xc2,0xf5,0x82,0xe4,0x34,0x95,0xf5,0x83,0xee,0xf0,0xa3,0xef,0xf0,0xaf,0x64, ++0x22,0x74,0x01,0x2d,0xf5,0x82,0xe4,0x34,0x94,0xf5,0x83,0xe4,0xf0,0xaf,0x05,0xe5, ++0x64,0x44,0x80,0xfd,0x12,0x5a,0x80,0xe5,0x64,0x44,0x80,0xff,0x22,0xe4,0xf5,0x59, ++0xe5,0x59,0xb4,0x20,0x14,0x90,0x9a,0xc5,0xe0,0x04,0xf0,0x90,0x95,0x01,0xe0,0xff, ++0x90,0x9a,0xc5,0xe0,0xb5,0x07,0x02,0xe4,0xf0,0x75,0xf0,0x09,0xe5,0x59,0x90,0x96, ++0x4b,0x12,0x43,0x5f,0xe0,0x64,0x01,0x60,0x02,0xc1,0xd3,0xe5,0x59,0x25,0xe0,0x24, ++0x80,0xf5,0x82,0xe4,0x34,0x93,0xf5,0x83,0xe0,0xfe,0xa3,0xe0,0xd3,0x94,0x00,0xee, ++0x94,0x00,0x50,0x02,0xc1,0xd3,0xe5,0x59,0x94,0x20,0x40,0x08,0x90,0x9a,0xc5,0xe0, ++0x60,0x02,0xc1,0xde,0xe5,0x59,0x75,0xf0,0x0a,0xa4,0x24,0x00,0xf9,0x74,0x90,0x35, ++0xf0,0x75,0x5e,0x01,0xf5,0x5f,0x89,0x60,0xe5,0x59,0x25,0xe0,0x24,0x80,0xf5,0x82, ++0xe4,0x34,0x93,0xf5,0x83,0xe0,0xff,0xa3,0xe0,0x90,0x9e,0x38,0xcf,0xf0,0xa3,0xef, ++0xf0,0xe5,0x59,0x25,0xe0,0x24,0xc4,0xf5,0x82,0xe4,0x34,0x98,0xf5,0x83,0xe0,0xff, ++0xa3,0xe0,0x90,0x9e,0x3a,0xcf,0xf0,0xa3,0xef,0xf0,0xe5,0x59,0xc3,0x94,0x20,0x50, ++0x14,0x74,0x84,0x25,0x59,0xf5,0x82,0xe4,0x34,0x04,0xf5,0x83,0xe0,0x54,0x3f,0x90, ++0x9e,0x34,0xf0,0x80,0x12,0x74,0xa6,0x25,0x59,0xf5,0x82,0xe4,0x34,0x9c,0xf5,0x83, ++0xe0,0x54,0x3f,0x90,0x9e,0x34,0xf0,0x90,0x9e,0x34,0xe0,0xfe,0x54,0x1f,0xa3,0xf0, ++0x75,0xf0,0x09,0xe5,0x59,0x90,0x96,0x48,0x12,0x43,0x5f,0xe0,0x90,0x9e,0x3d,0xf0, ++0x74,0xe6,0x25,0x59,0xf5,0x82,0xe4,0x34,0x9c,0xf5,0x83,0xe0,0xc3,0x94,0x05,0x40, ++0x02,0x61,0xac,0x90,0x9e,0x3d,0xe0,0xff,0x90,0x9e,0x35,0xe0,0x9f,0x40,0x13,0x90, ++0x9e,0x3d,0xe0,0x90,0x9e,0x35,0xf0,0xee,0x54,0x40,0xfe,0x90,0x9e,0x34,0xf0,0xef, ++0x4e,0xf0,0x90,0x04,0xfd,0xe0,0x54,0x05,0x64,0x01,0x70,0x29,0x90,0x9e,0x35,0xe0, ++0xff,0x90,0x41,0x4a,0x93,0xfe,0x74,0x44,0x25,0x59,0xf5,0x82,0xe4,0x34,0x9a,0xf5, ++0x83,0xe0,0xc3,0x9e,0x40,0x06,0xef,0x90,0x40,0xda,0x80,0x30,0x90,0x9e,0x35,0xe0, ++0x90,0x40,0xf6,0x80,0x27,0x90,0x9e,0x35,0xe0,0xff,0x90,0x41,0x4a,0x93,0xfe,0x74, ++0x44,0x25,0x59,0xf5,0x82,0xe4,0x34,0x9a,0xf5,0x83,0xe0,0xc3,0x9e,0x40,0x06,0xef, ++0x90,0x41,0x12,0x80,0x07,0x90,0x9e,0x35,0xe0,0x90,0x41,0x2e,0x93,0x90,0x9e,0x3c, ++0xf0,0x90,0x9e,0x3c,0xe0,0x75,0xf0,0x06,0xa4,0x24,0x50,0xf9,0x74,0x40,0x35,0xf0, ++0x75,0x5b,0xff,0xf5,0x5c,0x89,0x5d,0x90,0x9e,0x34,0xe0,0x90,0x41,0xf2,0x93,0xff, ++0xd3,0x90,0x9e,0x3b,0xe0,0x9f,0x90,0x9e,0x3a,0xe0,0x94,0x00,0x40,0x09,0xe4,0xfd, ++0xaf,0x59,0x12,0x5c,0xbd,0xc1,0x6a,0xe5,0x59,0x25,0xe0,0x24,0xc2,0xf5,0x82,0xe4, ++0x34,0x95,0xf5,0x83,0xe0,0xf5,0x61,0xa3,0xe0,0xf5,0x62,0xab,0x5b,0xaa,0x5c,0xa9, ++0x5d,0x12,0x29,0xd9,0xff,0x7e,0x00,0xab,0x5e,0xaa,0x5f,0xa9,0x60,0x12,0x42,0x97, ++0xfd,0xac,0xf0,0x12,0x29,0xf2,0xef,0x25,0x62,0xf5,0x62,0xee,0x35,0x61,0xf5,0x61, ++0xab,0x5b,0xaa,0x5c,0xa9,0x5d,0x90,0x00,0x01,0x12,0x42,0x20,0xff,0x7e,0x00,0xab, ++0x5e,0xaa,0x5f,0xa9,0x60,0x90,0x00,0x02,0x12,0x42,0xc2,0xfd,0xac,0xf0,0x12,0x29, ++0xf2,0xef,0x25,0x62,0xf5,0x62,0xee,0x35,0x61,0xf5,0x61,0xab,0x5b,0xaa,0x5c,0xa9, ++0x5d,0x90,0x00,0x02,0x12,0x42,0x20,0xff,0x7e,0x00,0xab,0x5e,0xaa,0x5f,0xa9,0x60, ++0x90,0x00,0x04,0x12,0x42,0xc2,0xfd,0xac,0xf0,0x12,0x29,0xf2,0xef,0x25,0x62,0xf5, ++0x62,0xee,0x35,0x61,0xf5,0x61,0xab,0x5b,0xaa,0x5c,0xa9,0x5d,0x90,0x00,0x03,0x12, ++0x42,0x20,0xff,0x7e,0x00,0xab,0x5e,0xaa,0x5f,0xa9,0x60,0x90,0x00,0x06,0x12,0x42, ++0xc2,0xfd,0xac,0xf0,0x12,0x29,0xf2,0xef,0x25,0x62,0xf5,0x62,0xee,0x35,0x61,0xf5, ++0x61,0xab,0x5b,0xaa,0x5c,0xa9,0x5d,0x90,0x00,0x04,0x12,0x42,0x20,0xff,0x7e,0x00, ++0xab,0x5e,0xaa,0x5f,0xa9,0x60,0x90,0x00,0x08,0x12,0x42,0xc2,0xfd,0xac,0xf0,0x12, ++0x29,0xf2,0xef,0x25,0x62,0xf5,0x62,0xee,0x35,0x61,0xf5,0x61,0xab,0x5b,0xaa,0x5c, ++0xa9,0x5d,0x90,0x00,0x05,0x12,0x42,0x20,0xff,0x7e,0x00,0x90,0x9e,0x38,0xe0,0xfc, ++0xa3,0xe0,0xfd,0x12,0x29,0xf2,0xd3,0xe5,0x62,0x9f,0xe5,0x61,0x9e,0x40,0x0c,0xe5, ++0x62,0x9f,0xf5,0x62,0xe5,0x61,0x9e,0xf5,0x61,0x80,0x05,0xe4,0xf5,0x61,0xf5,0x62, ++0xe5,0x59,0x25,0xe0,0x24,0xc2,0xf5,0x82,0xe4,0x34,0x95,0xf5,0x83,0xe5,0x61,0xf0, ++0xa3,0xe5,0x62,0xf0,0x90,0x9e,0x34,0xe0,0x25,0xe0,0x24,0x66,0xf5,0x82,0xe4,0x34, ++0x41,0xf5,0x83,0xc3,0x74,0x01,0x93,0x95,0x62,0xe4,0x93,0x95,0x61,0x50,0x07,0xaf, ++0x59,0x12,0x66,0x87,0xc1,0x3e,0x90,0x9e,0x34,0xe0,0x25,0xe0,0x24,0x9e,0xf5,0x82, ++0xe4,0x34,0x41,0xf5,0x83,0xd3,0x74,0x01,0x93,0x95,0x62,0xe4,0x93,0x95,0x61,0x50, ++0x02,0xc1,0x3e,0x7d,0x01,0xaf,0x59,0x12,0x5c,0xbd,0xc1,0x3e,0x74,0xe6,0x25,0x59, ++0xf5,0x82,0xe4,0x34,0x9c,0xf5,0x83,0xe0,0xfc,0x64,0x05,0x60,0x02,0xa1,0x47,0x90, ++0x96,0x43,0xe0,0xff,0xb4,0x03,0x0b,0x90,0x9e,0x35,0xe0,0xc3,0x94,0x19,0x40,0x3d, ++0x80,0x2e,0xef,0xb4,0x02,0x0b,0x90,0x9e,0x35,0xe0,0xc3,0x94,0x11,0x40,0x2e,0x80, ++0x1f,0x90,0x96,0x43,0xe0,0xff,0xb4,0x01,0x0b,0x90,0x9e,0x35,0xe0,0xc3,0x94,0x0a, ++0x40,0x1b,0x80,0x0c,0xef,0x70,0x11,0x90,0x9e,0x35,0xe0,0xc3,0x94,0x03,0x40,0x0d, ++0x90,0x9a,0x84,0x74,0x01,0xf0,0x80,0x05,0xe4,0x90,0x9a,0x84,0xf0,0x74,0x84,0x25, ++0x59,0xf5,0x82,0xe4,0x34,0x98,0xf5,0x83,0xe0,0xf5,0x63,0x74,0x44,0x25,0x59,0xf5, ++0x82,0xe4,0x34,0x9a,0xf5,0x83,0xe0,0xff,0xc3,0x94,0x30,0x50,0x02,0x81,0xf4,0x90, ++0x9a,0x84,0xe0,0x64,0x01,0x60,0x02,0x81,0xf4,0x74,0x85,0x25,0x59,0xf5,0x82,0xe4, ++0x34,0x9a,0xf5,0x83,0xe0,0x64,0x0a,0x60,0x51,0xef,0x24,0x05,0xff,0xe4,0x33,0xfe, ++0x74,0x41,0x25,0x59,0xf5,0x82,0xe4,0x34,0x94,0xf5,0x83,0xe0,0xfd,0xd3,0x9f,0xee, ++0x64,0x80,0xf8,0x74,0x80,0x98,0x50,0x32,0xed,0x24,0x05,0xff,0xe4,0x33,0xfe,0x74, ++0x44,0x25,0x59,0xf5,0x82,0xe4,0x34,0x9a,0xf5,0x83,0xe0,0xd3,0x9f,0xee,0x64,0x80, ++0xf8,0x74,0x80,0x98,0x50,0x14,0x74,0x26,0x25,0x59,0xf5,0x82,0xe4,0x34,0x9d,0xf5, ++0x83,0xe0,0xff,0x90,0x9e,0x35,0xe0,0x6f,0x60,0x3d,0x74,0x44,0x25,0x59,0xf5,0x82, ++0xe4,0x34,0x9a,0xf5,0x83,0xe0,0xff,0xd3,0x94,0x42,0x40,0x05,0x75,0x63,0x05,0x80, ++0x0e,0xef,0xd3,0x94,0x39,0x40,0x05,0x75,0x63,0x03,0x80,0x03,0x75,0x63,0x01,0x74, ++0x41,0x25,0x59,0xf5,0x82,0xe4,0x34,0x94,0xf5,0x83,0xef,0xf0,0x74,0x85,0x25,0x59, ++0xf5,0x82,0xe4,0x34,0x9a,0x80,0x29,0x74,0xe6,0x25,0x59,0xf5,0x82,0xe4,0x34,0x9c, ++0xf5,0x83,0xe4,0xf0,0x74,0x85,0x25,0x59,0xf5,0x82,0xe4,0x34,0x9a,0xf5,0x83,0xe0, ++0x04,0xf0,0x80,0x10,0xe4,0xf5,0x63,0x74,0xe6,0x25,0x59,0xf5,0x82,0xe4,0x34,0x9c, ++0xf5,0x83,0xe4,0xf0,0x90,0x9e,0x35,0xe0,0xff,0x74,0x26,0x25,0x59,0xf5,0x82,0xe4, ++0x34,0x9d,0xf5,0x83,0xef,0xf0,0x74,0x84,0x25,0x59,0xf5,0x82,0xe4,0x34,0x98,0xf5, ++0x83,0xe5,0x63,0xf0,0x75,0xf0,0x09,0xe5,0x59,0x90,0x96,0x4c,0x12,0x43,0x5f,0xe0, ++0xb4,0x01,0x10,0xe4,0xf5,0x63,0x74,0xe6,0x25,0x59,0xf5,0x82,0xe4,0x34,0x9c,0xf5, ++0x83,0xe4,0xf0,0xad,0x63,0xc1,0x39,0xec,0x64,0x06,0x60,0x02,0xc1,0x3e,0xf5,0x61, ++0xf5,0x62,0x90,0x42,0x13,0x93,0xff,0x7e,0x00,0x90,0x9e,0x38,0xe0,0xfc,0xa3,0xe0, ++0xfd,0x12,0x29,0xf2,0x90,0x9e,0x36,0xee,0xf0,0xa3,0xef,0xf0,0x74,0x84,0x25,0x59, ++0xf5,0x82,0xe4,0x34,0x98,0xf5,0x83,0xe0,0xf5,0x63,0xe4,0xf5,0x5a,0xab,0x5e,0xaa, ++0x5f,0xa9,0x60,0x75,0xf0,0x02,0xe5,0x5a,0xa4,0xf5,0x82,0x85,0xf0,0x83,0x12,0x42, ++0xc2,0xfd,0xac,0xf0,0xe5,0x5a,0x90,0x42,0x0e,0x93,0xff,0x7e,0x00,0x12,0x29,0xf2, ++0xef,0x25,0x62,0xf5,0x62,0xee,0x35,0x61,0xf5,0x61,0xc3,0x90,0x9e,0x37,0xe0,0x95, ++0x62,0x90,0x9e,0x36,0xe0,0x95,0x61,0x40,0x07,0x05,0x5a,0xe5,0x5a,0xb4,0x05,0xbd, ++0xe5,0x5a,0xc3,0x13,0xf5,0x5a,0xe5,0x63,0xb4,0x01,0x06,0xe5,0x5a,0x70,0x46,0x80, ++0x13,0xe5,0x63,0xb4,0x03,0x15,0xe5,0x5a,0x70,0x05,0x75,0x63,0x03,0x80,0x39,0xe5, ++0x5a,0xb4,0x01,0x05,0x75,0x63,0x01,0x80,0x2f,0x80,0x2a,0xe5,0x63,0xb4,0x05,0x28, ++0xe5,0x5a,0x70,0x05,0x75,0x63,0x05,0x80,0x0d,0xe5,0x5a,0xb4,0x01,0x05,0x75,0x63, ++0x03,0x80,0x03,0x75,0x63,0x01,0xd3,0x90,0x9e,0x3b,0xe0,0x94,0x03,0x90,0x9e,0x3a, ++0xe0,0x94,0x00,0x40,0x03,0xe4,0xf5,0x63,0xd3,0x90,0x9e,0x3b,0xe0,0x94,0x03,0x90, ++0x9e,0x3a,0xe0,0x94,0x00,0x40,0x03,0xe4,0xf5,0x63,0x74,0x84,0x25,0x59,0xf5,0x82, ++0xe4,0x34,0x98,0xf5,0x83,0xe5,0x63,0xf0,0xfd,0xaf,0x59,0x12,0x66,0x47,0x74,0xe6, ++0x25,0x59,0xf5,0x82,0xe4,0x34,0x9c,0xf5,0x83,0xe0,0xd3,0x94,0x05,0x74,0xe6,0x50, ++0x0e,0x25,0x59,0xf5,0x82,0xe4,0x34,0x9c,0xf5,0x83,0xe0,0x04,0xf0,0x80,0x0b,0x25, ++0x59,0xf5,0x82,0xe4,0x34,0x9c,0xf5,0x83,0xe4,0xf0,0xab,0x5e,0xaa,0x5f,0xa9,0x60, ++0xe4,0xf5,0xf0,0x12,0x42,0xfa,0xab,0x5e,0xaa,0x5f,0xa9,0x60,0x90,0x00,0x02,0xe4, ++0xf5,0xf0,0x12,0x43,0x19,0x90,0x00,0x04,0xe4,0xf5,0xf0,0x12,0x43,0x19,0x90,0x00, ++0x06,0xe4,0xf5,0xf0,0x12,0x43,0x19,0x90,0x00,0x08,0xe4,0xf5,0xf0,0x12,0x43,0x19, ++0xe5,0x59,0x25,0xe0,0x24,0x80,0xf5,0x82,0xe4,0x34,0x93,0xf5,0x83,0xe4,0xf0,0xa3, ++0xf0,0xe5,0x59,0x25,0xe0,0x24,0xc4,0xf5,0x82,0xe4,0x34,0x98,0xf5,0x83,0xe4,0xf0, ++0xa3,0xf0,0xe5,0x59,0x25,0xe0,0x24,0x44,0xf5,0x82,0xe4,0x34,0x99,0xf5,0x83,0xe4, ++0xf0,0xa3,0xf0,0x05,0x59,0xe5,0x59,0xc3,0x94,0x40,0x50,0x02,0x01,0x90,0x22,0x90, ++0x04,0x44,0x74,0x11,0xf0,0xa3,0x74,0xf0,0xf0,0xa3,0x74,0x0f,0xf0,0xa3,0xe4,0xf0, ++0xfd,0x74,0xa4,0x2d,0xf5,0x82,0xe4,0x34,0x04,0xf5,0x83,0xe4,0xf0,0x0d,0xbd,0x10, ++0xf0,0xe4,0x90,0x9a,0xc5,0xf0,0x90,0x95,0x01,0x04,0xf0,0xe4,0xfd,0x75,0xf0,0x0a, ++0xed,0x90,0x90,0x00,0x12,0x43,0x5f,0xe4,0xf0,0xa3,0xf0,0x75,0xf0,0x0a,0xed,0x90, ++0x90,0x02,0x12,0x43,0x5f,0xe4,0xf0,0xa3,0xf0,0x75,0xf0,0x0a,0xed,0x90,0x90,0x04, ++0x12,0x43,0x5f,0xe4,0xf0,0xa3,0xf0,0x75,0xf0,0x0a,0xed,0x90,0x90,0x06,0x12,0x43, ++0x5f,0xe4,0xf0,0xa3,0xf0,0x75,0xf0,0x0a,0xed,0x90,0x90,0x08,0x12,0x43,0x5f,0xe4, ++0xf0,0xa3,0xf0,0x74,0x26,0x2d,0xf5,0x82,0xe4,0x34,0x9d,0xf5,0x83,0x74,0x13,0xf0, ++0x74,0x85,0x2d,0xf5,0x82,0xe4,0x34,0x9a,0xf5,0x83,0xe4,0xf0,0x74,0x84,0x2d,0xf5, ++0x82,0xe4,0x34,0x98,0xf5,0x83,0xe4,0xf0,0xed,0x25,0xe0,0x24,0x80,0xf5,0x82,0xe4, ++0x34,0x93,0xf5,0x83,0xe4,0xf0,0xa3,0xf0,0xed,0x25,0xe0,0x24,0xc4,0xf5,0x82,0xe4, ++0x34,0x98,0xf5,0x83,0xe4,0xf0,0xa3,0xf0,0xed,0x25,0xe0,0x24,0xc4,0xf5,0x82,0xe4, ++0x34,0x99,0xf5,0x83,0xe4,0xf0,0xa3,0xf0,0xed,0x25,0xe0,0x24,0x44,0xf5,0x82,0xe4, ++0x34,0x99,0xf5,0x83,0xe4,0xf0,0xa3,0xf0,0xed,0x25,0xe0,0x24,0xc6,0xf5,0x82,0xe4, ++0x34,0x9a,0xf5,0x83,0xe4,0xf0,0xa3,0xf0,0xed,0x25,0xe0,0x24,0x46,0xf5,0x82,0xe4, ++0x34,0x9b,0xf5,0x83,0xe4,0xf0,0xa3,0xf0,0x74,0x86,0x2d,0xf5,0x82,0xe4,0x34,0x9c, ++0xf5,0x83,0xe4,0xf0,0x74,0x46,0x2d,0xf5,0x82,0xe4,0x34,0x9c,0xf5,0x83,0xe4,0xf0, ++0x74,0xe6,0x2d,0xf5,0x82,0xe4,0x34,0x9c,0xf5,0x83,0xe4,0xf0,0x90,0x41,0xc4,0x93, ++0xfe,0x74,0x01,0x93,0xff,0x90,0x41,0x8c,0x74,0x01,0x93,0x2f,0xff,0xe4,0x93,0x3e, ++0xc3,0x13,0xfe,0xef,0x13,0xff,0xed,0x25,0xe0,0x24,0xc2,0xf5,0x82,0xe4,0x34,0x95, ++0xf5,0x83,0xee,0xf0,0xa3,0xef,0xf0,0x75,0xf0,0x09,0xed,0x90,0x96,0x4b,0x12,0x43, ++0x5f,0x74,0x01,0xf0,0x75,0xf0,0x09,0xed,0x90,0x96,0x4a,0x12,0x43,0x5f,0x74,0x01, ++0xf0,0x74,0x82,0x2d,0xf5,0x82,0xe4,0x34,0x95,0xf5,0x83,0x74,0x0c,0xf0,0x75,0xf0, ++0x09,0xed,0x90,0x96,0x46,0x12,0x43,0x5f,0x74,0xff,0xf0,0xa3,0xf0,0x75,0xf0,0x09, ++0xed,0x90,0x96,0x44,0x12,0x43,0x5f,0xe4,0xf0,0xa3,0x74,0x0f,0xf0,0x75,0xf0,0x09, ++0xed,0x90,0x96,0x48,0x12,0x43,0x5f,0x74,0x13,0xf0,0x75,0xf0,0x09,0xed,0x90,0x96, ++0x49,0x12,0x43,0x5f,0xe4,0xf0,0xed,0xc3,0x94,0x20,0x50,0x0f,0x74,0x84,0x2d,0xf5, ++0x82,0xe4,0x34,0x04,0xf5,0x83,0x74,0x13,0xf0,0x80,0x0d,0x74,0xa6,0x2d,0xf5,0x82, ++0xe4,0x34,0x9c,0xf5,0x83,0x74,0x13,0xf0,0x0d,0xed,0x64,0x40,0x60,0x03,0x02,0x6f, ++0x0d,0x22,0x12,0x29,0xd9,0xf5,0x59,0xc3,0x94,0x40,0x50,0x15,0x90,0x00,0x02,0x12, ++0x42,0x20,0xff,0x74,0x44,0x25,0x59,0xf5,0x82,0xe4,0x34,0x9a,0xf5,0x83,0xef,0xf0, ++0x22,0xe5,0x59,0xb4,0x40,0x0a,0x90,0x00,0x02,0x12,0x42,0x20,0x90,0x96,0x42,0xf0, ++0x22,0x90,0x00,0x04,0x12,0x42,0x20,0xff,0x54,0x3f,0xfe,0xef,0x54,0x80,0xc4,0x13, ++0x13,0x13,0x54,0x01,0xfd,0xaf,0x06,0x02,0x55,0x30,0x12,0x29,0xd9,0x90,0x95,0x01, ++0xf0,0x22,0x12,0x29,0xd9,0xf5,0x22,0x22,0x90,0x00,0x02,0x12,0x42,0x20,0xff,0x30, ++0xe0,0x25,0x12,0x29,0xd9,0x90,0x9e,0x6a,0xf0,0x90,0x00,0x01,0x12,0x42,0x20,0x90, ++0x9e,0x6b,0xf0,0xef,0xc3,0x13,0x54,0x7f,0x90,0x9e,0x69,0xf0,0x90,0x00,0x03,0x12, ++0x42,0x20,0x90,0x9e,0x6f,0xf0,0x22,0x90,0x9e,0x6a,0x74,0x01,0xf0,0x90,0x9e,0x6b, ++0x74,0x03,0xf0,0x90,0x9e,0x69,0x74,0x14,0xf0,0x90,0x9e,0x6f,0x74,0x05,0xf0,0x22, ++0x12,0x29,0xd9,0x30,0xe0,0x18,0xc3,0x13,0x54,0x7f,0x90,0x9e,0x6e,0xf0,0x90,0x00, ++0x01,0x12,0x42,0x20,0xff,0x90,0x9e,0x6c,0xe4,0xf0,0xa3,0xef,0xf0,0x22,0x90,0x9e, ++0x6e,0x74,0x07,0xf0,0x90,0x9e,0x6c,0xe4,0xf0,0xa3,0x74,0x02,0xf0,0x22,0x90,0x02, ++0x09,0xe0,0xfd,0x12,0x29,0xd9,0xfe,0xaf,0x05,0xed,0x2e,0x90,0x9e,0x50,0xf0,0x90, ++0x00,0x01,0x12,0x42,0x20,0xff,0xed,0x2f,0x90,0x9e,0x51,0xf0,0x90,0x00,0x02,0x12, ++0x42,0x20,0xff,0xed,0x2f,0x90,0x9e,0x52,0xf0,0x90,0x00,0x03,0x12,0x42,0x20,0xff, ++0xed,0x2f,0x90,0x9e,0x53,0xf0,0x90,0x00,0x04,0x12,0x42,0x20,0xff,0xae,0x05,0xed, ++0x2f,0x90,0x9e,0x54,0xf0,0x22,0xd3,0x10,0xaf,0x01,0xc3,0xc0,0xd0,0x90,0x9e,0x3f, ++0x12,0x43,0x8b,0x90,0x9e,0x3f,0x12,0x43,0x6b,0x90,0x00,0x01,0x12,0x42,0xc2,0xfa, ++0xe5,0xf0,0x24,0x00,0xff,0xe4,0x3a,0xfe,0x90,0x9e,0x3f,0x12,0x43,0x6b,0x90,0x00, ++0x01,0xee,0x8f,0xf0,0x12,0x43,0x19,0x12,0x29,0xd9,0xff,0x60,0x2c,0xb5,0x71,0x16, ++0x90,0x9e,0x3f,0x12,0x43,0x6b,0x90,0x00,0x01,0x12,0x42,0xc2,0x65,0x73,0x70,0x04, ++0xe5,0x72,0x65,0xf0,0x60,0x23,0x90,0x9e,0x3f,0x12,0x43,0x6b,0x90,0x00,0x01,0x12, ++0x42,0xc2,0xff,0xae,0xf0,0x51,0x3e,0x80,0x10,0x90,0x9e,0x3f,0x12,0x43,0x6b,0x12, ++0x29,0xd9,0x65,0x71,0x60,0x03,0x12,0x44,0xc8,0xd0,0xd0,0x92,0xaf,0x22,0x90,0x9e, ++0x42,0xee,0xf0,0xa3,0xef,0xf0,0x75,0x71,0x01,0x8e,0x72,0xf5,0x73,0xe4,0xfd,0x7f, ++0x0b,0x51,0x80,0xe4,0xfd,0x7f,0x02,0x51,0x80,0x71,0x4a,0xe4,0xff,0x71,0xac,0xe4, ++0xf5,0x75,0x90,0x01,0xc9,0xe5,0x75,0xf0,0x90,0x9e,0x42,0xe0,0xfc,0xa3,0xe0,0xfd, ++0xec,0xfb,0x8d,0x44,0xe4,0xf5,0x45,0x7d,0x01,0x7f,0x60,0x7e,0x01,0x02,0x35,0xab, ++0xd3,0x10,0xaf,0x01,0xc3,0xc0,0xd0,0x90,0x9e,0x45,0xed,0xf0,0x90,0x9e,0x44,0xef, ++0xf0,0xd3,0x94,0x07,0x50,0x4f,0xa3,0xe0,0x70,0x1a,0x90,0x9e,0x44,0xe0,0xff,0x74, ++0x01,0xa8,0x07,0x08,0x80,0x02,0xc3,0x33,0xd8,0xfc,0xf4,0xff,0x90,0x00,0x47,0xe0, ++0x5f,0xf0,0x80,0x17,0x90,0x9e,0x44,0xe0,0xff,0x74,0x01,0xa8,0x07,0x08,0x80,0x02, ++0xc3,0x33,0xd8,0xfc,0xff,0x90,0x00,0x47,0xe0,0x4f,0xf0,0x12,0x4b,0xdb,0x90,0x9e, ++0x44,0xe0,0xff,0x74,0x01,0xa8,0x07,0x08,0x80,0x02,0xc3,0x33,0xd8,0xfc,0xf4,0xff, ++0x90,0x00,0x46,0x80,0x5a,0x90,0x9e,0x44,0xe0,0x24,0xf8,0xf0,0xa3,0xe0,0x70,0x1d, ++0x90,0x9e,0x44,0xe0,0xff,0x74,0x01,0xa8,0x07,0x08,0x80,0x02,0xc3,0x33,0xd8,0xfc, ++0xc4,0x54,0xf0,0xf4,0xff,0x90,0x00,0x43,0xe0,0x5f,0xf0,0x80,0x1a,0x90,0x9e,0x44, ++0xe0,0xff,0x74,0x01,0xa8,0x07,0x08,0x80,0x02,0xc3,0x33,0xd8,0xfc,0xc4,0x54,0xf0, ++0xff,0x90,0x00,0x43,0xe0,0x4f,0xf0,0x12,0x4b,0xdb,0x90,0x9e,0x44,0xe0,0xff,0x74, ++0x01,0xa8,0x07,0x08,0x80,0x02,0xc3,0x33,0xd8,0xfc,0xf4,0xff,0x90,0x00,0x43,0xe0, ++0x5f,0xf0,0x12,0x4b,0xdb,0xd0,0xd0,0x92,0xaf,0x22,0x7f,0x0b,0x71,0xb9,0xef,0x65, ++0x74,0x60,0x10,0xe5,0x74,0xb4,0x01,0x05,0xe4,0xf5,0x74,0x80,0x03,0x75,0x74,0x01, ++0x7f,0x01,0x22,0x7f,0x00,0x22,0xe5,0x71,0x64,0x01,0x70,0x3f,0x71,0x4a,0xbf,0x01, ++0x04,0x7f,0x01,0x71,0xac,0x90,0x00,0x46,0xe0,0x44,0x04,0xfd,0x7f,0x46,0x12,0x4c, ++0xe3,0x90,0x00,0x44,0xe0,0x54,0xfb,0xfd,0x7f,0x44,0x12,0x4c,0xe3,0x90,0x00,0x46, ++0xe0,0x54,0xfb,0xfd,0x7f,0x46,0x12,0x4c,0xe3,0x7f,0x02,0x71,0xb9,0x8f,0x75,0x90, ++0x01,0xc9,0xe5,0x75,0xf0,0xb4,0x01,0x03,0x12,0x4f,0xda,0x22,0x90,0x01,0xca,0xe5, ++0x74,0xf0,0xef,0x60,0x03,0x12,0x4f,0xda,0x22,0xd3,0x10,0xaf,0x01,0xc3,0xc0,0xd0, ++0x90,0x9e,0xb1,0xef,0xf0,0xd3,0x94,0x07,0x50,0x47,0xe0,0xff,0x74,0x01,0xa8,0x07, ++0x08,0x80,0x02,0xc3,0x33,0xd8,0xfc,0xf4,0xff,0x90,0x00,0x46,0xe0,0x5f,0xf0,0x12, ++0x4b,0xdb,0x90,0x9e,0xb1,0xe0,0xfd,0x74,0x01,0x7e,0x00,0xa8,0x05,0x08,0x80,0x05, ++0xc3,0x33,0xce,0x33,0xce,0xd8,0xf9,0xff,0x90,0x00,0x44,0xe0,0xfb,0xe4,0xfe,0xef, ++0x5b,0xa8,0x05,0x08,0x80,0x06,0xce,0xa2,0xe7,0x13,0xce,0x13,0xd8,0xf8,0xff,0x80, ++0x44,0x90,0x9e,0xb1,0xe0,0x24,0xf8,0xf0,0xe0,0xff,0x74,0x01,0xa8,0x07,0x08,0x80, ++0x02,0xc3,0x33,0xd8,0xfc,0x12,0x4b,0xd3,0x90,0x9e,0xb1,0xe0,0xfd,0x74,0x01,0x7e, ++0x00,0xa8,0x05,0x08,0x80,0x05,0xc3,0x33,0xce,0x33,0xce,0xd8,0xf9,0xff,0x90,0x00, ++0x42,0xe0,0xfb,0xe4,0xfe,0xef,0x5b,0xa8,0x05,0x08,0x80,0x06,0xce,0xa2,0xe7,0x13, ++0xce,0x13,0xd8,0xf8,0xff,0xd0,0xd0,0x92,0xaf,0x22,0xd3,0x10,0xaf,0x01,0xc3,0xc0, ++0xd0,0x90,0x9e,0x56,0xe0,0x90,0x9e,0x40,0xf0,0x90,0x9e,0x57,0xe0,0xf5,0x64,0xa3, ++0xe0,0xf5,0x65,0xe4,0xf5,0x61,0x74,0x59,0x25,0x61,0xf5,0x82,0xe4,0x34,0x9e,0xf5, ++0x83,0xe0,0xff,0x74,0x66,0x25,0x61,0xf8,0xa6,0x07,0x05,0x61,0xe5,0x61,0xb4,0x04, ++0xe5,0x90,0x9e,0x40,0xe0,0x12,0x43,0x94,0x74,0xb7,0x00,0x75,0xdf,0x01,0x74,0xbd, ++0x02,0x74,0xbd,0x03,0x74,0xbd,0x04,0x75,0xdf,0x05,0x75,0xaf,0x80,0x75,0xc5,0x81, ++0x75,0xdf,0x82,0x00,0x00,0x75,0xdb,0xaf,0x69,0xb1,0xe6,0xa1,0xdf,0x90,0x9e,0x40, ++0xe0,0xff,0xb4,0x02,0x08,0x90,0x9e,0x3f,0x74,0x01,0xf0,0x80,0x0f,0xef,0x90,0x9e, ++0x3f,0xb4,0x03,0x05,0x74,0x02,0xf0,0x80,0x03,0x74,0x04,0xf0,0xc3,0xe5,0x64,0x94, ++0x08,0x50,0x49,0xe4,0xf5,0x61,0x90,0x9e,0x3f,0xe0,0xff,0xe5,0x61,0xc3,0x9f,0x40, ++0x02,0xa1,0xdf,0xc3,0xe5,0x64,0x94,0x01,0x50,0x14,0xe5,0x61,0x25,0x65,0xff,0xc3, ++0x74,0x03,0x95,0x61,0x24,0x66,0xf8,0xe6,0xfd,0x12,0x4c,0xe3,0x80,0x1a,0xc3,0x74, ++0x03,0x95,0x61,0x24,0x66,0xf8,0xe6,0xff,0xe5,0x61,0x7c,0x00,0x25,0x65,0xfd,0xec, ++0x35,0x64,0x8d,0x82,0xf5,0x83,0xef,0xf0,0x05,0x61,0x80,0xba,0xc3,0xe5,0x64,0x94, ++0x10,0x40,0x02,0xa1,0xdf,0x90,0x9e,0x40,0xe0,0x64,0x04,0x60,0x02,0xa1,0xdf,0xaf, ++0x67,0xfc,0xfd,0xfe,0x78,0x10,0x12,0x2a,0x6c,0xc0,0x04,0xc0,0x05,0xc0,0x06,0xc0, ++0x07,0xaf,0x66,0xe4,0xfc,0xfd,0xfe,0x78,0x18,0x12,0x2a,0x6c,0xd0,0x03,0xd0,0x02, ++0xd0,0x01,0xd0,0x00,0x12,0x43,0x46,0xc0,0x04,0xc0,0x05,0xc0,0x06,0xc0,0x07,0xaf, ++0x68,0xe4,0xfc,0xfd,0xfe,0x78,0x08,0x12,0x2a,0x6c,0xd0,0x03,0xd0,0x02,0xd0,0x01, ++0xd0,0x00,0x12,0x43,0x46,0xa8,0x04,0xa9,0x05,0xaa,0x06,0xab,0x07,0xaf,0x69,0xe4, ++0xfc,0xfd,0xfe,0x12,0x43,0x46,0xa3,0x12,0x2a,0x7f,0x90,0x9e,0x41,0x12,0x43,0x53, ++0x90,0x80,0x85,0x12,0x2a,0x7f,0xaf,0x65,0xae,0x64,0x12,0x2f,0xd9,0x80,0x30,0xe5, ++0x68,0x7f,0x00,0xfe,0xef,0x25,0x69,0xf5,0x63,0xe4,0x3e,0xf5,0x62,0xaf,0x63,0xfe, ++0x12,0x37,0x54,0x80,0x1a,0xe5,0x68,0x7f,0x00,0xfe,0xef,0x25,0x69,0xf5,0x63,0xe4, ++0x3e,0xf5,0x62,0xaf,0x63,0xfe,0x12,0x36,0xcb,0x80,0x04,0x7f,0x00,0x80,0x02,0x7f, ++0x01,0xd0,0xd0,0x92,0xaf,0x22,0x8f,0x6a,0xe4,0x90,0x9e,0x45,0xf0,0xe5,0x6a,0x14, ++0xfe,0x90,0x9e,0x45,0xe0,0xff,0xc3,0x9e,0x50,0x0e,0xef,0x04,0xfd,0x12,0x34,0xb7, ++0x90,0x9e,0x45,0xe0,0x04,0xf0,0x80,0xe5,0xe5,0x6a,0x14,0xff,0x7d,0xff,0x12,0x34, ++0xb7,0x90,0x9e,0x45,0xe5,0x6a,0xf0,0x90,0x9e,0x45,0xe0,0xc3,0x94,0xff,0x50,0x0f, ++0xe0,0xff,0x04,0xfd,0x12,0x34,0xb7,0x90,0x9e,0x45,0xe0,0x04,0xf0,0x80,0xe8,0xad, ++0x6a,0x7f,0xff,0x02,0x34,0xb7,0xd3,0x10,0xaf,0x01,0xc3,0xc0,0xd0,0xe4,0xf5,0x5b, ++0x75,0x5c,0x04,0xf5,0x5d,0xf5,0x5f,0xf5,0x60,0x90,0x02,0x09,0xe0,0xff,0x12,0x29, ++0xd9,0xfe,0xef,0x2e,0xf5,0x5e,0x30,0xe0,0x08,0x75,0x59,0x00,0x75,0x5a,0x80,0x80, ++0x05,0xe4,0xf5,0x59,0xf5,0x5a,0xe5,0x5e,0xc3,0x13,0x90,0xfd,0x10,0xf0,0x74,0x20, ++0x25,0x5b,0xf5,0x5b,0xad,0x5a,0xe5,0x5b,0x2d,0xff,0x24,0x01,0xf5,0x82,0xe4,0x34, ++0xfc,0xf5,0x83,0xe0,0x90,0x9e,0x56,0xf0,0x74,0x02,0x2f,0xf5,0x82,0xe4,0x34,0xfc, ++0xf5,0x83,0xe0,0xfe,0xe5,0x5b,0x2d,0x24,0x03,0xf5,0x82,0xe4,0x34,0xfc,0xf5,0x83, ++0xe0,0x24,0x00,0xff,0xe4,0x3e,0x90,0x9e,0x57,0xf0,0xa3,0xef,0xf0,0x7f,0x04,0xe5, ++0x5b,0x25,0x5a,0x2f,0x24,0x00,0xf5,0x82,0xe4,0x34,0xfc,0xf5,0x83,0xe0,0xfe,0x74, ++0x55,0x2f,0xf5,0x82,0xe4,0x34,0x9e,0xf5,0x83,0xee,0xf0,0x0f,0xbf,0x08,0xe0,0x91, ++0x5a,0xef,0x70,0x3f,0x90,0x01,0xc3,0xe0,0x60,0x25,0xc3,0xe5,0x60,0x94,0xe8,0xe5, ++0x5f,0x94,0x03,0x40,0x09,0x90,0x01,0xc6,0xe0,0x44,0x10,0xf0,0x80,0x63,0x05,0x60, ++0xe5,0x60,0x70,0x02,0x05,0x5f,0x7f,0x0a,0x7e,0x00,0x12,0x37,0x54,0x80,0xd5,0x90, ++0x01,0xc6,0xe0,0x90,0x01,0xc3,0x30,0xe2,0x05,0x74,0xfe,0xf0,0x80,0x43,0x74,0xff, ++0xf0,0x80,0x3e,0xe5,0x5b,0xb4,0x78,0x23,0xe4,0xf5,0x5b,0x05,0x5e,0xe5,0x5a,0x64, ++0x80,0x45,0x59,0x70,0x06,0xf5,0x59,0xf5,0x5a,0x80,0x06,0x75,0x59,0x00,0x75,0x5a, ++0x80,0xe5,0x5e,0xc3,0x13,0x90,0xfd,0x10,0xf0,0x80,0x06,0x74,0x08,0x25,0x5b,0xf5, ++0x5b,0xe5,0x5d,0x15,0x5d,0x70,0x02,0x15,0x5c,0xe5,0x5d,0x45,0x5c,0x60,0x02,0xc1, ++0x74,0xd0,0xd0,0x92,0xaf,0x22,0x90,0x06,0x34,0x74,0xff,0xf0,0xe4,0xa3,0xf0,0xa3, ++0xf0,0xa3,0xf0,0x22,0xe4,0x90,0x9e,0x5d,0xf0,0x90,0x00,0x80,0xe0,0x44,0x80,0xfd, ++0x7f,0x80,0x02,0x4c,0xe3,0x8e,0x59,0x8f,0x5a,0x8b,0x5b,0x8a,0x5c,0x89,0x5d,0xe4, ++0x90,0x9e,0x34,0xf0,0xef,0x90,0x00,0x31,0xf0,0x12,0x4b,0xdb,0xe5,0x59,0x54,0x03, ++0xff,0x90,0x00,0x32,0xe0,0x54,0xfc,0x4f,0xf0,0x12,0x4b,0xdb,0x90,0x00,0x33,0xe0, ++0x54,0x7f,0xf0,0x12,0x4b,0xdb,0x90,0x00,0x33,0xe0,0x20,0xe7,0x0e,0x90,0x9e,0x34, ++0xe0,0xc3,0x94,0x64,0x50,0x05,0xe0,0x04,0xf0,0x80,0xeb,0x90,0x9e,0x34,0xe0,0xc3, ++0x94,0x64,0x50,0x10,0x90,0x00,0x30,0xe0,0xab,0x5b,0xaa,0x5c,0xa9,0x5d,0x12,0x42, ++0x4d,0x7f,0x01,0x22,0x7f,0x00,0x22,0xe4,0xf5,0x74,0x22,0x90,0x9e,0x60,0xe0,0x90, ++0x9e,0x0f,0xf0,0x22,0xef,0x70,0x03,0x02,0x79,0x9c,0x90,0x9e,0x0f,0xe0,0x60,0x03, ++0x02,0x7d,0x67,0x90,0x9d,0xfb,0x12,0x43,0x53,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f, ++0x8c,0x7e,0x08,0x12,0x2f,0xd9,0x90,0x9d,0xa7,0x12,0x43,0x53,0x90,0x80,0x85,0x12, ++0x2a,0x7f,0x7f,0x44,0x7e,0x08,0x12,0x2f,0xd9,0x90,0x9d,0xab,0x12,0x43,0x53,0x90, ++0x80,0x85,0x12,0x2a,0x7f,0x7f,0x5c,0x7e,0x08,0x12,0x2f,0xd9,0x90,0x9d,0xaf,0x12, ++0x43,0x53,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0x6c,0x7e,0x0e,0x12,0x2f,0xd9,0x90, ++0x9d,0xb3,0x12,0x43,0x53,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0x70,0x7e,0x0e,0x12, ++0x2f,0xd9,0x90,0x9d,0xb7,0x12,0x43,0x53,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0x74, ++0x7e,0x0e,0x12,0x2f,0xd9,0x90,0x9d,0xbb,0x12,0x43,0x53,0x90,0x80,0x85,0x12,0x2a, ++0x7f,0x7f,0x78,0x7e,0x0e,0x12,0x2f,0xd9,0x90,0x9d,0xbf,0x12,0x43,0x53,0x90,0x80, ++0x85,0x12,0x2a,0x7f,0x7f,0x7c,0x7e,0x0e,0x12,0x2f,0xd9,0x90,0x9d,0xc3,0x12,0x43, ++0x53,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0x80,0x7e,0x0e,0x12,0x2f,0xd9,0x90,0x9d, ++0xc7,0x12,0x43,0x53,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0x84,0x7e,0x0e,0x12,0x2f, ++0xd9,0x90,0x9d,0xcb,0x12,0x43,0x53,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0x88,0x7e, ++0x0e,0x12,0x2f,0xd9,0x90,0x9d,0xcf,0x12,0x43,0x53,0x90,0x80,0x85,0x12,0x2a,0x7f, ++0x7f,0x8c,0x7e,0x0e,0x12,0x2f,0xd9,0x90,0x9d,0xd3,0x12,0x43,0x53,0x90,0x80,0x85, ++0x12,0x2a,0x7f,0x7f,0xd0,0x7e,0x0e,0x12,0x2f,0xd9,0x90,0x9d,0xd7,0x12,0x43,0x53, ++0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0xd4,0x7e,0x0e,0x12,0x2f,0xd9,0x90,0x9d,0xdb, ++0x12,0x43,0x53,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0xd8,0x7e,0x0e,0x12,0x2f,0xd9, ++0x90,0x9d,0xdf,0x12,0x43,0x53,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0xdc,0x7e,0x0e, ++0x12,0x2f,0xd9,0x90,0x9d,0xe3,0x12,0x43,0x53,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f, ++0xe0,0x7e,0x0e,0x12,0x2f,0xd9,0x90,0x9d,0xe7,0x12,0x43,0x53,0x90,0x80,0x85,0x12, ++0x2a,0x7f,0x7f,0xec,0x7e,0x0e,0x12,0x2f,0xd9,0x90,0x9d,0xeb,0x12,0x43,0x53,0x90, ++0x80,0x85,0x12,0x2a,0x7f,0x7f,0x04,0x7e,0x0c,0x12,0x2f,0xd9,0x90,0x9d,0xef,0x12, ++0x43,0x53,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0x04,0x7e,0x0d,0x12,0x2f,0xd9,0x90, ++0x9d,0xf3,0x12,0x43,0x53,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0x0c,0x7e,0x09,0x12, ++0x2f,0xd9,0x90,0x9d,0xf7,0x12,0x43,0x53,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0x04, ++0x7e,0x08,0x12,0x2f,0xd9,0x90,0x9e,0x0f,0x74,0x01,0xf0,0x22,0x90,0x9e,0x0f,0xe0, ++0x64,0x01,0x60,0x02,0xa1,0x67,0x7f,0x8c,0x7e,0x08,0x12,0x27,0xde,0x90,0x9d,0xfb, ++0x12,0x2a,0x7f,0x7f,0x44,0x7e,0x08,0x12,0x27,0xde,0x90,0x9d,0xa7,0x12,0x2a,0x7f, ++0x7f,0x5c,0x7e,0x08,0x12,0x27,0xde,0x90,0x9d,0xab,0x12,0x2a,0x7f,0x7f,0x6c,0x7e, ++0x0e,0x12,0x27,0xde,0x90,0x9d,0xaf,0x12,0x2a,0x7f,0x7f,0x70,0x7e,0x0e,0x12,0x27, ++0xde,0x90,0x9d,0xb3,0x12,0x2a,0x7f,0x7f,0x74,0x7e,0x0e,0x12,0x27,0xde,0x90,0x9d, ++0xb7,0x12,0x2a,0x7f,0x7f,0x78,0x7e,0x0e,0x12,0x27,0xde,0x90,0x9d,0xbb,0x12,0x2a, ++0x7f,0x7f,0x7c,0x7e,0x0e,0x12,0x27,0xde,0x90,0x9d,0xbf,0x12,0x2a,0x7f,0x7f,0x80, ++0x7e,0x0e,0x12,0x27,0xde,0x90,0x9d,0xc3,0x12,0x2a,0x7f,0x7f,0x84,0x7e,0x0e,0x12, ++0x27,0xde,0x90,0x9d,0xc7,0x12,0x2a,0x7f,0x7f,0x88,0x7e,0x0e,0x12,0x27,0xde,0x90, ++0x9d,0xcb,0x12,0x2a,0x7f,0x7f,0x8c,0x7e,0x0e,0x12,0x27,0xde,0x90,0x9d,0xcf,0x12, ++0x2a,0x7f,0x7f,0xd0,0x7e,0x0e,0x12,0x27,0xde,0x90,0x9d,0xd3,0x12,0x2a,0x7f,0x7f, ++0xd4,0x7e,0x0e,0x12,0x27,0xde,0x90,0x9d,0xd7,0x12,0x2a,0x7f,0x7f,0xd8,0x7e,0x0e, ++0x12,0x27,0xde,0x90,0x9d,0xdb,0x12,0x2a,0x7f,0x7f,0xdc,0x7e,0x0e,0x12,0x27,0xde, ++0x90,0x9d,0xdf,0x12,0x2a,0x7f,0x7f,0xe0,0x7e,0x0e,0x12,0x27,0xde,0x90,0x9d,0xe3, ++0x12,0x2a,0x7f,0x7f,0xec,0x7e,0x0e,0x12,0x27,0xde,0x90,0x9d,0xe7,0x12,0x2a,0x7f, ++0x7f,0x04,0x7e,0x0c,0x12,0x27,0xde,0x90,0x9d,0xeb,0x12,0x2a,0x7f,0x7f,0x04,0x7e, ++0x0d,0x12,0x27,0xde,0x90,0x9d,0xef,0x12,0x2a,0x7f,0x7f,0x0c,0x7e,0x09,0x12,0x27, ++0xde,0x90,0x9d,0xf3,0x12,0x2a,0x7f,0x7f,0x04,0x7e,0x08,0x12,0x27,0xde,0x90,0x9d, ++0xf7,0x12,0x2a,0x7f,0x7f,0x8c,0x7e,0x08,0x12,0x27,0xde,0x90,0x9e,0xa1,0x12,0x2a, ++0x7f,0x90,0x9e,0xa1,0x12,0x43,0x53,0xed,0x44,0xc0,0xfd,0xec,0x90,0x9e,0xa1,0x12, ++0x2a,0x7f,0x90,0x9e,0xa1,0x12,0x43,0x53,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0x8c, ++0x7e,0x08,0x12,0x2f,0xd9,0x90,0x80,0x85,0x12,0x2a,0x8b,0x00,0x01,0x00,0x00,0x7f, ++0x44,0x7e,0x08,0x12,0x2f,0xd9,0x90,0x80,0x85,0x12,0x2a,0x8b,0x00,0xdb,0x25,0xa4, ++0x7f,0x5c,0x7e,0x08,0x12,0x2f,0xd9,0x90,0x80,0x85,0x12,0x2a,0x8b,0x20,0xdb,0x25, ++0xa4,0x7f,0x6c,0x7e,0x0e,0x12,0x2f,0xd9,0x90,0x80,0x85,0x12,0x2a,0x8b,0x20,0xdb, ++0x25,0xa4,0x7f,0x70,0x7e,0x0e,0x12,0x2f,0xd9,0x90,0x80,0x85,0x12,0x2a,0x8b,0x04, ++0x1b,0x25,0xa4,0x7f,0x74,0x7e,0x0e,0x12,0x2f,0xd9,0x90,0x80,0x85,0x12,0x2a,0x8b, ++0x04,0x1b,0x25,0xa4,0x7f,0x78,0x7e,0x0e,0x12,0x2f,0xd9,0x90,0x80,0x85,0x12,0x2a, ++0x8b,0x04,0x1b,0x25,0xa4,0x7f,0x7c,0x7e,0x0e,0x12,0x2f,0xd9,0x90,0x80,0x85,0x12, ++0x2a,0x8b,0x04,0x1b,0x25,0xa4,0x7f,0x80,0x7e,0x0e,0x12,0x2f,0xd9,0x90,0x80,0x85, ++0x12,0x2a,0x8b,0x63,0xdb,0x25,0xa4,0x7f,0x84,0x7e,0x0e,0x12,0x2f,0xd9,0x90,0x80, ++0x85,0x12,0x2a,0x8b,0x04,0x1b,0x25,0xa4,0x7f,0x88,0x7e,0x0e,0x12,0x2f,0xd9,0x90, ++0x80,0x85,0x12,0x2a,0x8b,0x20,0xdb,0x25,0xa4,0x7f,0x8c,0x7e,0x0e,0x12,0x2f,0xd9, ++0x90,0x80,0x85,0x12,0x2a,0x8b,0x20,0xdb,0x25,0xa4,0x7f,0xd0,0x7e,0x0e,0x12,0x2f, ++0xd9,0x90,0x80,0x85,0x12,0x2a,0x8b,0x20,0xdb,0x25,0xa4,0x7f,0xd4,0x7e,0x0e,0x12, ++0x2f,0xd9,0x90,0x80,0x85,0x12,0x2a,0x8b,0x20,0xdb,0x25,0xa4,0x7f,0xd8,0x7e,0x0e, ++0x12,0x2f,0xd9,0x90,0x80,0x85,0x12,0x2a,0x8b,0x00,0x1b,0x25,0xa4,0x7f,0xdc,0x7e, ++0x0e,0x12,0x2f,0xd9,0x90,0x80,0x85,0x12,0x2a,0x8b,0x00,0x1b,0x25,0xa4,0x7f,0xe0, ++0x7e,0x0e,0x12,0x2f,0xd9,0x90,0x80,0x85,0x12,0x2a,0x8b,0x24,0xdb,0x25,0xa4,0x7f, ++0xec,0x7e,0x0e,0x12,0x2f,0xd9,0x7f,0x04,0x7e,0x0c,0x12,0x27,0xde,0x90,0x9e,0xa1, ++0x12,0x2a,0x7f,0x90,0x9e,0xa1,0x12,0x43,0x53,0xe4,0xff,0xec,0x90,0x9e,0xa1,0x12, ++0x2a,0x7f,0x90,0x9e,0xa1,0x12,0x43,0x53,0xef,0x44,0x11,0xff,0xec,0x90,0x9e,0xa1, ++0x12,0x2a,0x7f,0x90,0x9e,0xa1,0x12,0x43,0x53,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f, ++0x04,0x7e,0x0c,0x12,0x2f,0xd9,0x7f,0x04,0x7e,0x0d,0x12,0x27,0xde,0x90,0x9e,0xa1, ++0x12,0x2a,0x7f,0x90,0x9e,0xa1,0x12,0x43,0x53,0xef,0x54,0xf0,0xff,0xec,0x90,0x9e, ++0xa1,0x12,0x2a,0x7f,0x90,0x9e,0xa1,0x12,0x43,0x53,0xef,0x44,0x01,0xff,0xec,0x90, ++0x9e,0xa1,0x12,0x2a,0x7f,0x90,0x9e,0xa1,0x12,0x43,0x53,0x90,0x80,0x85,0x12,0x2a, ++0x7f,0x7f,0x04,0x7e,0x0d,0x12,0x2f,0xd9,0x7f,0x0c,0x7e,0x09,0x12,0x27,0xde,0x90, ++0x9e,0xa1,0x12,0x2a,0x7f,0x90,0x9e,0xa1,0x12,0x43,0x53,0xe4,0xff,0xec,0x90,0x9e, ++0xa1,0x12,0x2a,0x7f,0x90,0x9e,0xa1,0x12,0x43,0x53,0xef,0x44,0x11,0xff,0xec,0x90, ++0x9e,0xa1,0x12,0x2a,0x7f,0x90,0x9e,0xa1,0x12,0x43,0x53,0x90,0x80,0x85,0x12,0x2a, ++0x7f,0x7f,0x0c,0x7e,0x09,0x12,0x2f,0xd9,0x7f,0x0c,0x7e,0x09,0x12,0x27,0xde,0x90, ++0x9e,0xa1,0x12,0x2a,0x7f,0x90,0x9e,0xa1,0x12,0x43,0x53,0xed,0x54,0x0f,0xfd,0xec, ++0x54,0xf0,0xfc,0x90,0x9e,0xa1,0x12,0x2a,0x7f,0x90,0x9e,0xa1,0x12,0x43,0x53,0xed, ++0x44,0x10,0xfd,0xec,0x44,0x01,0xfc,0x90,0x9e,0xa1,0x12,0x2a,0x7f,0x90,0x9e,0xa1, ++0x12,0x43,0x53,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0x0c,0x7e,0x09,0x12,0x2f,0xd9, ++0x7f,0x04,0x7e,0x08,0x12,0x27,0xde,0x90,0x9e,0xa1,0x12,0x2a,0x7f,0x90,0x9e,0xa1, ++0x12,0x43,0x53,0xef,0x54,0xf0,0xff,0xec,0x90,0x9e,0xa1,0x12,0x2a,0x7f,0x90,0x9e, ++0xa1,0x12,0x43,0x53,0xef,0x44,0x01,0xff,0xec,0x90,0x9e,0xa1,0x12,0x2a,0x7f,0x90, ++0x9e,0xa1,0x12,0x43,0x53,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0x04,0x7e,0x08,0x12, ++0x2f,0xd9,0xe4,0x90,0x9e,0x0f,0xf0,0x22,0x90,0x00,0x02,0x12,0x42,0x20,0x90,0x9e, ++0x1e,0xf0,0xe0,0x60,0x04,0xe0,0xf4,0x70,0x21,0xa2,0xaf,0xe4,0x33,0xf5,0x59,0xc2, ++0xaf,0x90,0x00,0x47,0xe0,0x54,0xfb,0xfd,0x7f,0x47,0x12,0x4c,0xe3,0x7d,0x40,0x7f, ++0x01,0x12,0x36,0xaf,0xe5,0x59,0x24,0xff,0x92,0xaf,0x22,0xe4,0xfd,0x7f,0x45,0x12, ++0x4c,0xe3,0x90,0x04,0xfd,0xe4,0xf0,0xa3,0xf0,0x90,0x9e,0x1e,0xf0,0x90,0x9e,0x24, ++0xf0,0x90,0x9e,0x27,0xf0,0x90,0x9e,0x25,0xf0,0x90,0x9e,0x28,0xf0,0x90,0x9e,0x26, ++0xf0,0x90,0x9e,0x29,0xf0,0x90,0x9e,0x10,0x04,0xf0,0xe4,0xa3,0xf0,0xa3,0xf0,0xa3, ++0xf0,0x90,0x9e,0x15,0xf0,0x90,0x9e,0x1a,0xf0,0x90,0x9e,0x1c,0xf0,0x90,0x9e,0x2e, ++0xf0,0x90,0x9e,0x1f,0xf0,0x90,0x9e,0x1b,0xf0,0x90,0x9e,0x14,0xf0,0x90,0x00,0x51, ++0xe0,0x44,0xc0,0xfd,0x7f,0x51,0x02,0x4c,0xe3,0x90,0x9e,0x2e,0xe0,0x64,0x01,0x60, ++0x08,0x90,0x9e,0x1c,0xe0,0x60,0x02,0xc1,0xd0,0x90,0x9e,0x10,0xe0,0xc3,0x94,0xff, ++0x50,0x05,0xe0,0x04,0xf0,0x80,0x3b,0x90,0x9e,0x11,0xe0,0xc3,0x94,0xff,0x50,0x06, ++0xe0,0x04,0xf0,0xe4,0x80,0x28,0x90,0x9e,0x12,0xe0,0xc3,0x94,0xff,0x50,0x0a,0xe0, ++0x04,0xf0,0xe4,0x90,0x9e,0x11,0xf0,0x80,0x15,0x90,0x9e,0x13,0xe0,0xc3,0x94,0xff, ++0x50,0x10,0xe0,0x04,0xf0,0xe4,0x90,0x9e,0x12,0xf0,0x90,0x9e,0x11,0xf0,0x90,0x9e, ++0x10,0xf0,0x90,0x00,0x44,0xe0,0x54,0x0c,0x60,0x76,0xe0,0x30,0xe2,0x32,0x90,0x9e, ++0x24,0xe0,0xc3,0x94,0xff,0x50,0x05,0xe0,0x04,0xf0,0x80,0x24,0x90,0x9e,0x25,0xe0, ++0xc3,0x94,0xff,0x50,0x06,0xe0,0x04,0xf0,0xe4,0x80,0x11,0x90,0x9e,0x26,0xe0,0xc3, ++0x94,0xff,0x50,0x0c,0xe0,0x04,0xf0,0xe4,0x90,0x9e,0x25,0xf0,0x90,0x9e,0x24,0xf0, ++0x90,0x00,0x44,0xe0,0x30,0xe3,0x32,0x90,0x9e,0x27,0xe0,0xc3,0x94,0xff,0x50,0x05, ++0xe0,0x04,0xf0,0x80,0x24,0x90,0x9e,0x28,0xe0,0xc3,0x94,0xff,0x50,0x06,0xe0,0x04, ++0xf0,0xe4,0x80,0x11,0x90,0x9e,0x29,0xe0,0xc3,0x94,0xff,0x50,0x0c,0xe0,0x04,0xf0, ++0xe4,0x90,0x9e,0x28,0xf0,0x90,0x9e,0x27,0xf0,0x90,0x04,0xfd,0xe0,0x44,0x01,0xf0, ++0x22,0x00,0x89,0xad,}; ++ ++// =================== v80 UMC A Cut COMMON 2011-12-14 ===================== ++u8 Rtl8192CUFwUMCACutImgArray[UMCACutImgArrayLength] = { ++0xc1,0x88,0x02,0x00,0x50,0x00,0x00,0x00,0x12,0x14,0x16,0x08,0xd4,0x3e,0x01,0x00, ++0x25,0x86,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x02,0x43,0xba,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x02,0x48,0x79,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x02,0x5e,0xff,0x00,0x00,0x00,0x00,0x00,0xa1,0xd4,0x00,0x00,0x00, ++0x05,0x04,0x03,0x02,0x00,0x03,0x06,0x05,0x04,0x03,0x00,0x04,0x06,0x05,0x04,0x02, ++0x00,0x04,0x08,0x07,0x06,0x04,0x00,0x06,0x0a,0x09,0x08,0x06,0x00,0x08,0x0a,0x09, ++0x08,0x04,0x00,0x08,0x0a,0x09,0x08,0x02,0x00,0x08,0x0a,0x09,0x08,0x00,0x00,0x08, ++0x12,0x11,0x10,0x08,0x00,0x10,0x1a,0x19,0x18,0x10,0x00,0x18,0x22,0x21,0x20,0x18, ++0x00,0x20,0x22,0x21,0x20,0x10,0x00,0x20,0x22,0x21,0x20,0x08,0x00,0x20,0x22,0x21, ++0x1c,0x08,0x00,0x20,0x22,0x21,0x14,0x08,0x00,0x20,0x22,0x20,0x18,0x08,0x00,0x20, ++0x31,0x30,0x20,0x10,0x00,0x30,0x31,0x30,0x18,0x00,0x00,0x30,0x31,0x2f,0x10,0x10, ++0x00,0x30,0x31,0x2c,0x10,0x10,0x00,0x30,0x31,0x28,0x10,0x00,0x00,0x30,0x31,0x20, ++0x10,0x00,0x00,0x30,0x31,0x10,0x10,0x00,0x00,0x30,0x04,0x04,0x04,0x05,0x04,0x04, ++0x04,0x05,0x05,0x05,0x06,0x06,0x04,0x04,0x04,0x05,0x05,0x05,0x06,0x06,0x04,0x04, ++0x05,0x05,0x05,0x05,0x06,0x06,0x04,0x04,0x05,0x05,0x05,0x05,0x06,0x07,0x0a,0x0b, ++0x0d,0x10,0x04,0x05,0x05,0x06,0x06,0x09,0x0c,0x11,0x08,0x08,0x09,0x09,0x0a,0x0c, ++0x10,0x11,0x04,0x04,0x04,0x05,0x04,0x04,0x05,0x07,0x07,0x07,0x08,0x0a,0x04,0x04, ++0x04,0x04,0x06,0x0a,0x0b,0x0d,0x05,0x05,0x07,0x07,0x08,0x0b,0x0d,0x0f,0x04,0x04, ++0x04,0x05,0x07,0x07,0x09,0x09,0x0c,0x0e,0x10,0x12,0x04,0x04,0x05,0x05,0x06,0x0a, ++0x11,0x13,0x09,0x09,0x09,0x09,0x0c,0x0e,0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x24,0x26,0x2a,0x18,0x1a,0x1d,0x1f,0x21,0x27,0x29,0x2a,0x00,0x00, ++0x00,0x1f,0x23,0x28,0x2a,0x2c,0x00,0x04,0x00,0x04,0x00,0x08,0x00,0x10,0x00,0x18, ++0x00,0x24,0x00,0x30,0x00,0x48,0x00,0x60,0x00,0x90,0x00,0xc0,0x00,0xd8,0x00,0x50, ++0x00,0x78,0x00,0xa0,0x00,0xc8,0x01,0x40,0x01,0x90,0x01,0xe0,0x02,0x30,0x01,0x2c, ++0x01,0x40,0x01,0xe0,0x02,0xd0,0x03,0xe8,0x04,0xb0,0x06,0x40,0x07,0xd0,0x00,0x02, ++0x00,0x02,0x00,0x04,0x00,0x08,0x00,0x0c,0x00,0x12,0x00,0x18,0x00,0x24,0x00,0x30, ++0x00,0x48,0x00,0x60,0x00,0x6c,0x00,0x28,0x00,0x3c,0x00,0x50,0x00,0x64,0x00,0xa0, ++0x00,0xc8,0x00,0xf0,0x01,0x18,0x00,0x64,0x00,0xa0,0x00,0xf0,0x01,0x68,0x01,0xf4, ++0x02,0x58,0x03,0x20,0x03,0xe8,0x02,0x02,0x02,0x02,0x02,0x02,0x03,0x03,0x04,0x04, ++0x05,0x07,0x04,0x04,0x07,0x0a,0x0a,0x0c,0x0c,0x12,0x05,0x07,0x07,0x08,0x0b,0x12, ++0x24,0x3c,0x01,0x01,0x01,0x01,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x01,0x02, ++0x03,0x04,0x05,0x06,0x07,0x08,0x05,0x06,0x07,0x08,0x09,0x0a,0x0b,0x0c,0x20,0x1e, ++0x1c,0x18,0x10,0x18,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0xbb,0x01,0x0c,0xe5,0x82,0x29,0xf5,0x82,0xe5,0x83,0x3a,0xf5,0x83,0xe0,0x22,0x50, ++0x06,0xe9,0x25,0x82,0xf8,0xe6,0x22,0xbb,0xfe,0x06,0xe9,0x25,0x82,0xf8,0xe2,0x22, ++0xe5,0x82,0x29,0xf5,0x82,0xe5,0x83,0x3a,0xf5,0x83,0xe4,0x93,0x22,0xbb,0x01,0x06, ++0x89,0x82,0x8a,0x83,0xf0,0x22,0x50,0x02,0xf7,0x22,0xbb,0xfe,0x01,0xf3,0x22,0xf8, ++0xbb,0x01,0x0d,0xe5,0x82,0x29,0xf5,0x82,0xe5,0x83,0x3a,0xf5,0x83,0xe8,0xf0,0x22, ++0x50,0x06,0xe9,0x25,0x82,0xc8,0xf6,0x22,0xbb,0xfe,0x05,0xe9,0x25,0x82,0xc8,0xf2, ++0x22,0xc5,0xf0,0xf8,0xa3,0xe0,0x28,0xf0,0xc5,0xf0,0xf8,0xe5,0x82,0x15,0x82,0x70, ++0x02,0x15,0x83,0xe0,0x38,0xf0,0x22,0xbb,0x01,0x0a,0x89,0x82,0x8a,0x83,0xe0,0xf5, ++0xf0,0xa3,0xe0,0x22,0x50,0x06,0x87,0xf0,0x09,0xe7,0x19,0x22,0xbb,0xfe,0x07,0xe3, ++0xf5,0xf0,0x09,0xe3,0x19,0x22,0x89,0x82,0x8a,0x83,0xe4,0x93,0xf5,0xf0,0x74,0x01, ++0x93,0x22,0xbb,0x01,0x10,0xe5,0x82,0x29,0xf5,0x82,0xe5,0x83,0x3a,0xf5,0x83,0xe0, ++0xf5,0xf0,0xa3,0xe0,0x22,0x50,0x09,0xe9,0x25,0x82,0xf8,0x86,0xf0,0x08,0xe6,0x22, ++0xbb,0xfe,0x0a,0xe9,0x25,0x82,0xf8,0xe2,0xf5,0xf0,0x08,0xe2,0x22,0xe5,0x83,0x2a, ++0xf5,0x83,0xe9,0x93,0xf5,0xf0,0xa3,0xe9,0x93,0x22,0xbb,0x01,0x0a,0x89,0x82,0x8a, ++0x83,0xf0,0xe5,0xf0,0xa3,0xf0,0x22,0x50,0x06,0xf7,0x09,0xa7,0xf0,0x19,0x22,0xbb, ++0xfe,0x06,0xf3,0xe5,0xf0,0x09,0xf3,0x19,0x22,0xf8,0xbb,0x01,0x11,0xe5,0x82,0x29, ++0xf5,0x82,0xe5,0x83,0x3a,0xf5,0x83,0xe8,0xf0,0xe5,0xf0,0xa3,0xf0,0x22,0x50,0x09, ++0xe9,0x25,0x82,0xc8,0xf6,0x08,0xa6,0xf0,0x22,0xbb,0xfe,0x09,0xe9,0x25,0x82,0xc8, ++0xf2,0xe5,0xf0,0x08,0xf2,0x22,0xef,0x4b,0xff,0xee,0x4a,0xfe,0xed,0x49,0xfd,0xec, ++0x48,0xfc,0x22,0xe0,0xfc,0xa3,0xe0,0xfd,0xa3,0xe0,0xfe,0xa3,0xe0,0xff,0x22,0xa4, ++0x25,0x82,0xf5,0x82,0xe5,0xf0,0x35,0x83,0xf5,0x83,0x22,0xe0,0xfb,0xa3,0xe0,0xfa, ++0xa3,0xe0,0xf9,0x22,0xf8,0xe0,0xfb,0xa3,0xa3,0xe0,0xf9,0x25,0xf0,0xf0,0xe5,0x82, ++0x15,0x82,0x70,0x02,0x15,0x83,0xe0,0xfa,0x38,0xf0,0x22,0xeb,0xf0,0xa3,0xea,0xf0, ++0xa3,0xe9,0xf0,0x22,0xd0,0x83,0xd0,0x82,0xf8,0xe4,0x93,0x70,0x12,0x74,0x01,0x93, ++0x70,0x0d,0xa3,0xa3,0x93,0xf8,0x74,0x01,0x93,0xf5,0x82,0x88,0x83,0xe4,0x73,0x74, ++0x02,0x93,0x68,0x60,0xef,0xa3,0xa3,0xa3,0x80,0xdf,0x02,0x43,0xf8,0x02,0x50,0x2e, ++0xe4,0x93,0xa3,0xf8,0xe4,0x93,0xa3,0x40,0x03,0xf6,0x80,0x01,0xf2,0x08,0xdf,0xf4, ++0x80,0x29,0xe4,0x93,0xa3,0xf8,0x54,0x07,0x24,0x0c,0xc8,0xc3,0x33,0xc4,0x54,0x0f, ++0x44,0x20,0xc8,0x83,0x40,0x04,0xf4,0x56,0x80,0x01,0x46,0xf6,0xdf,0xe4,0x80,0x0b, ++0x01,0x02,0x04,0x08,0x10,0x20,0x40,0x80,0x90,0x44,0x3d,0xe4,0x7e,0x01,0x93,0x60, ++0xbc,0xa3,0xff,0x54,0x3f,0x30,0xe5,0x09,0x54,0x1f,0xfe,0xe4,0x93,0xa3,0x60,0x01, ++0x0e,0xcf,0x54,0xc0,0x25,0xe0,0x60,0xa8,0x40,0xb8,0xe4,0x93,0xa3,0xfa,0xe4,0x93, ++0xa3,0xf8,0xe4,0x93,0xa3,0xc8,0xc5,0x82,0xc8,0xca,0xc5,0x83,0xca,0xf0,0xa3,0xc8, ++0xc5,0x82,0xc8,0xca,0xc5,0x83,0xca,0xdf,0xe9,0xde,0xe7,0x80,0xbe,0x41,0x9e,0x4f, ++0x00,0x41,0x9e,0xad,0x00,0x41,0x9e,0x61,0x80,0x41,0x9e,0x62,0x80,0x41,0x9e,0xaf, ++0x00,0x00,0xf0,0x90,0x9e,0x6b,0xe0,0x90,0x9e,0x87,0xf0,0xe4,0xfb,0xfd,0x7f,0x54, ++0x7e,0x01,0xd3,0x10,0xaf,0x01,0xc3,0xc0,0xd0,0x90,0x9e,0x85,0xeb,0xf0,0xa3,0xe0, ++0xfb,0xa3,0xe0,0xf5,0x44,0xe4,0xf5,0x45,0x12,0x30,0x62,0xd0,0xd0,0x92,0xaf,0x22, ++0x90,0x01,0x5f,0xe4,0xf0,0x90,0x01,0x3c,0x74,0x08,0xf0,0xe4,0x90,0x9e,0x86,0xf0, ++0x90,0x9e,0x69,0xe0,0x90,0x9e,0x87,0xf0,0xe4,0xfb,0xfd,0x7f,0x5c,0x7e,0x01,0x91, ++0x62,0x90,0x01,0x5f,0x74,0x05,0xf0,0x90,0x06,0x92,0x74,0x02,0xf0,0x90,0x9e,0x70, ++0x14,0xf0,0xe5,0x23,0x54,0x0f,0xc3,0x94,0x0c,0x50,0x02,0xf1,0x2b,0x22,0x8f,0x82, ++0x8e,0x83,0xa3,0xa3,0xa3,0xe4,0xf0,0x22,0xe4,0xf5,0x71,0x7f,0x60,0x7e,0x01,0x80, ++0xed,0x7d,0x01,0xaf,0x24,0xe1,0x2f,0xb1,0xa6,0xbf,0x01,0x0f,0x90,0x9e,0x51,0xe0, ++0xff,0xe4,0xfd,0xf1,0xd0,0x90,0x04,0x1f,0x74,0x20,0xf0,0x22,0x53,0x23,0xf0,0x43, ++0x23,0x01,0x91,0xfd,0x91,0xfe,0x53,0x23,0xf0,0x43,0x23,0x02,0x22,0x22,0x22,0x22, ++0x22,0x00,0x00,0x02,0x5f,0x91,0x02,0x5f,0x98,0xd3,0x10,0xaf,0x01,0xc3,0xc0,0xd0, ++0x8b,0x1b,0x8a,0x1c,0x89,0x1d,0x90,0x9e,0x88,0x71,0x8b,0xab,0x1e,0xaa,0x1f,0xa9, ++0x20,0x90,0x9e,0x8b,0x71,0x8b,0xaf,0x21,0x15,0x21,0xef,0x60,0x1b,0x90,0x9e,0x8b, ++0xe4,0x75,0xf0,0x01,0x71,0x74,0x12,0x24,0x62,0xff,0x90,0x9e,0x88,0xe4,0x75,0xf0, ++0x01,0x71,0x74,0xef,0x51,0x4d,0x80,0xde,0xab,0x1b,0xaa,0x1c,0xa9,0x1d,0xd0,0xd0, ++0x92,0xaf,0x22,0x90,0x06,0xa9,0xe0,0x90,0x9e,0x2f,0xf0,0xe0,0x54,0xc0,0x70,0x08, ++0x53,0x26,0xfe,0x53,0x26,0xfd,0x91,0xd1,0x90,0x9e,0x2f,0xe0,0x30,0xe6,0x13,0x43, ++0x26,0x01,0x90,0x9e,0x73,0xe0,0x64,0x02,0x60,0x04,0x91,0xd7,0x80,0x07,0x91,0x80, ++0x80,0x03,0x53,0x26,0xfe,0x90,0x9e,0x2f,0xe0,0x30,0xe7,0x16,0x43,0x26,0x02,0xe4, ++0x90,0x9e,0x86,0x91,0x52,0x90,0x01,0x57,0x74,0x05,0xf0,0x90,0x9e,0x74,0x74,0x01, ++0xf0,0x22,0x53,0x26,0xfd,0x22,0xd3,0x10,0xaf,0x01,0xc3,0xc0,0xd0,0x90,0x04,0x1d, ++0xe0,0x60,0x1a,0x90,0x05,0x22,0xe0,0x54,0x90,0x60,0x07,0x90,0x01,0xc6,0xe0,0x44, ++0x40,0xf0,0x90,0x01,0xc7,0xe0,0x30,0xe1,0xe4,0x7f,0x00,0x80,0x02,0x7f,0x01,0xd0, ++0xd0,0x92,0xaf,0x22,0xc0,0xe0,0xc0,0xf0,0xc0,0x83,0xc0,0x82,0xc0,0xd0,0x75,0xd0, ++0x00,0xc0,0x00,0xc0,0x01,0xc0,0x02,0xc0,0x03,0xc0,0x04,0xc0,0x05,0xc0,0x06,0xc0, ++0x07,0x90,0x01,0xc4,0x74,0xd4,0xf0,0x74,0x45,0xa3,0xf0,0x53,0x91,0xdf,0x90,0x01, ++0x3c,0xe0,0x55,0x30,0xf5,0x34,0xa3,0xe0,0x55,0x31,0xf5,0x35,0xa3,0xe0,0x55,0x32, ++0xf5,0x36,0xa3,0xe0,0x55,0x33,0xf5,0x37,0xe5,0x34,0x30,0xe0,0x06,0x90,0x01,0x3c, ++0x74,0x01,0xf0,0xe5,0x34,0x30,0xe1,0x09,0x90,0x01,0x3c,0x74,0x02,0xf0,0x12,0x66, ++0x09,0xe5,0x34,0x30,0xe2,0x38,0x90,0x01,0x3c,0x74,0x04,0xf0,0x90,0x06,0x92,0xe0, ++0x30,0xe0,0x24,0x90,0x9e,0x86,0xe4,0xf0,0x90,0x9e,0x69,0xe0,0x90,0x9e,0x87,0xf0, ++0xe4,0xfb,0xfd,0x7f,0x58,0x7e,0x01,0x91,0x62,0x90,0x01,0x5b,0x74,0x05,0xf0,0x90, ++0x06,0x92,0x74,0x01,0xf0,0x80,0x07,0x90,0x9e,0x71,0xe4,0xf0,0x91,0xd1,0xe5,0x34, ++0x30,0xe3,0x38,0x90,0x01,0x3c,0x74,0x08,0xf0,0x90,0x06,0x92,0xe0,0x30,0xe1,0x24, ++0x90,0x9e,0x86,0xe4,0xf0,0x90,0x9e,0x69,0xe0,0x90,0x9e,0x87,0xf0,0xe4,0xfb,0xfd, ++0x7f,0x5c,0x7e,0x01,0x91,0x62,0x90,0x01,0x5f,0x74,0x05,0xf0,0x90,0x06,0x92,0x74, ++0x02,0xf0,0x80,0x07,0x90,0x9e,0x70,0xe4,0xf0,0x91,0xd1,0xe5,0x34,0x30,0xe4,0x09, ++0x90,0x01,0x3c,0x74,0x10,0xf0,0x12,0x73,0x66,0xe5,0x34,0x30,0xe5,0x09,0x90,0x01, ++0x3c,0x74,0x20,0xf0,0x12,0x52,0x64,0xe5,0x35,0x30,0xe0,0x18,0x90,0x01,0x3d,0x74, ++0x01,0xf0,0x90,0x01,0x2f,0xe0,0x44,0x7f,0xf0,0x90,0x00,0x83,0xe0,0xf5,0x24,0x12, ++0x64,0xe3,0x91,0xd1,0xe5,0x35,0x30,0xe2,0x06,0x90,0x01,0x3d,0x74,0x04,0xf0,0xe5, ++0x36,0x30,0xe0,0x06,0x90,0x01,0x3e,0x74,0x01,0xf0,0xe5,0x36,0x30,0xe1,0x06,0x90, ++0x01,0x3e,0x74,0x02,0xf0,0x74,0xd4,0x04,0x90,0x01,0xc4,0xf0,0x74,0x45,0xa3,0xf0, ++0xd0,0x07,0xd0,0x06,0xd0,0x05,0xd0,0x04,0xd0,0x03,0xd0,0x02,0xd0,0x01,0xd0,0x00, ++0xd0,0xd0,0xd0,0x82,0xd0,0x83,0xd0,0xf0,0xd0,0xe0,0x32,0x7d,0x01,0x7f,0x0c,0x90, ++0x9e,0xa6,0xed,0xf0,0x90,0x9e,0xa5,0xef,0xf0,0x54,0x0f,0xff,0xe5,0x23,0x54,0x0f, ++0x6f,0x60,0x70,0x90,0x9e,0xa5,0xe0,0x30,0xe2,0x2a,0xe5,0x23,0x20,0xe2,0x05,0x7f, ++0x01,0x12,0x63,0xf3,0xe5,0x23,0x30,0xe3,0x09,0x90,0x9e,0xa5,0xe0,0x20,0xe3,0x02, ++0x80,0x52,0xe5,0x23,0x20,0xe3,0x4c,0x90,0x9e,0xa5,0xe0,0x30,0xe3,0x45,0xa3,0xe0, ++0xff,0x02,0x5e,0x95,0xe5,0x23,0x54,0x0f,0xff,0xbf,0x0c,0x0f,0x90,0x9e,0xa5,0xe0, ++0x20,0xe3,0x08,0x12,0x62,0xd7,0xef,0x60,0x2a,0xf1,0xb4,0xe5,0x23,0x54,0x0f,0xff, ++0xbf,0x04,0x10,0x90,0x9e,0xa5,0xe0,0x20,0xe2,0x09,0x12,0x63,0x20,0xef,0x60,0x13, ++0x12,0x61,0x3a,0xe5,0x23,0x54,0x0f,0xff,0xbf,0x02,0x08,0x12,0x63,0x83,0xef,0x60, ++0x02,0x91,0xec,0x22,0x90,0x06,0x04,0xe0,0x44,0x40,0xf0,0xe5,0x22,0xb4,0x01,0x05, ++0x7f,0x01,0x12,0x5e,0x5c,0x53,0x23,0xf0,0x43,0x23,0x04,0x22,0xe0,0xff,0x7d,0x01, ++0x90,0x9e,0x99,0xef,0xf0,0xa3,0xed,0xf0,0xe4,0xa3,0xf0,0xa3,0xf0,0xe5,0x25,0x60, ++0x05,0xe4,0xff,0x12,0x61,0x1f,0x90,0x9e,0x99,0xe0,0x30,0xe0,0x09,0x90,0x9e,0x9b, ++0xe4,0xf0,0xa3,0x74,0x80,0xf0,0x90,0x9e,0x99,0xe0,0xff,0xc3,0x13,0x90,0xfd,0x10, ++0xf0,0x90,0x04,0x25,0xef,0xf0,0x90,0x9e,0x9a,0xe0,0x60,0x1f,0xa3,0xa3,0xe0,0xff, ++0x24,0x0f,0xf5,0x82,0xe4,0x34,0xfc,0xf5,0x83,0xe0,0x44,0x80,0xf0,0x74,0x10,0x2f, ++0xf5,0x82,0xe4,0x34,0xfc,0xf5,0x83,0xe0,0x44,0x80,0xf0,0x90,0x9e,0x9b,0xa3,0xe0, ++0xff,0xfd,0x24,0x08,0xf5,0x82,0xe4,0x34,0xfc,0xf5,0x83,0xe4,0xf0,0x74,0x09,0x2d, ++0xf5,0x82,0xe4,0x34,0xfc,0xf5,0x83,0xe0,0x54,0xf0,0xf0,0x74,0x21,0x2f,0xf5,0x82, ++0xe4,0x34,0xfc,0xf5,0x83,0xe0,0x54,0xf7,0xf0,0x90,0x9e,0x9b,0xe0,0xfe,0xa3,0xe0, ++0xff,0x22,0x12,0x45,0xa6,0xbf,0x01,0x10,0x90,0x02,0x09,0xe0,0xff,0x7d,0x01,0x12, ++0x47,0xd0,0x90,0x04,0x1f,0x74,0x20,0xf0,0x22,0xc0,0xe0,0xc0,0xf0,0xc0,0x83,0xc0, ++0x82,0xc0,0xd0,0x75,0xd0,0x00,0xc0,0x00,0xc0,0x01,0xc0,0x02,0xc0,0x03,0xc0,0x04, ++0xc0,0x05,0xc0,0x06,0xc0,0x07,0x90,0x01,0xc4,0x74,0x79,0xf0,0x74,0x48,0xa3,0xf0, ++0x90,0x01,0x34,0xe0,0x55,0x28,0xf5,0x2c,0x90,0x01,0x36,0xe0,0x55,0x2a,0xf5,0x2e, ++0xa3,0xe0,0x55,0x2b,0xf5,0x2f,0xe5,0x2c,0x20,0xe0,0x02,0x41,0x17,0x90,0x01,0x34, ++0x74,0x01,0xf0,0x85,0xd1,0x08,0x85,0xd2,0x09,0x85,0xd3,0x0a,0x85,0xd4,0x0b,0x85, ++0xd5,0x0c,0x85,0xd6,0x0d,0x85,0xd7,0x0e,0x85,0xd9,0x0f,0xe5,0x0f,0x54,0x40,0xc3, ++0x13,0xff,0xe5,0x0e,0x54,0x20,0x6f,0x70,0x02,0x21,0xc9,0xe5,0x0f,0x30,0xe5,0x02, ++0x21,0xc9,0xe5,0x0d,0x54,0x3f,0xf5,0x4d,0xe5,0x08,0x54,0x3f,0xf5,0x4e,0xe5,0x0c, ++0x54,0x1f,0xff,0xe5,0x4d,0x25,0xe0,0x24,0xc4,0xf5,0x82,0xe4,0x34,0x99,0xf5,0x83, ++0xe4,0x8f,0xf0,0x12,0x42,0x81,0xe5,0x0e,0x54,0x1f,0xff,0xe5,0x4d,0x25,0xe0,0x24, ++0x80,0xf5,0x82,0xe4,0x34,0x93,0xf5,0x83,0xe4,0x8f,0xf0,0x12,0x42,0x81,0xe5,0x4e, ++0xd3,0x94,0x04,0x40,0x03,0x75,0x4e,0x04,0x75,0xf0,0x0a,0xe5,0x4d,0x90,0x90,0x00, ++0x12,0x43,0x5f,0x75,0xf0,0x02,0xe5,0x4e,0x12,0x43,0x5f,0xe0,0xfe,0xa3,0xe0,0xff, ++0xe5,0x0e,0x54,0x1f,0x2f,0xff,0xe4,0x3e,0xfe,0x75,0xf0,0x0a,0xe5,0x4d,0x90,0x90, ++0x00,0x12,0x43,0x5f,0x75,0xf0,0x02,0xe5,0x4e,0x12,0x43,0x5f,0xee,0xf0,0xa3,0xef, ++0xf0,0xe5,0x0f,0x20,0xe6,0x24,0xe5,0x0e,0x54,0x1f,0xff,0xe5,0x4d,0x25,0xe0,0x24, ++0xc4,0xf5,0x82,0xe4,0x34,0x98,0xf5,0x83,0xe4,0x8f,0xf0,0x12,0x42,0x81,0xe5,0x0a, ++0x30,0xe7,0x36,0xaf,0x4d,0x12,0x5b,0x68,0x80,0x2f,0xe5,0x0e,0x54,0x1f,0xff,0xe5, ++0x4d,0x25,0xe0,0x24,0x44,0xf5,0x82,0xe4,0x34,0x99,0xf5,0x83,0xe4,0x8f,0xf0,0x12, ++0x42,0x81,0xe5,0x0a,0x30,0xe7,0x12,0xe5,0x0a,0x54,0x7f,0xfd,0xe5,0x0e,0x54,0x1f, ++0xf5,0x53,0xab,0x4e,0xaf,0x4d,0x12,0x5b,0x05,0xe5,0x25,0x14,0x24,0xfd,0x50,0x02, ++0x80,0x45,0x90,0x9e,0x73,0xe0,0x60,0x37,0x90,0x01,0x5b,0xe4,0xf0,0x90,0x01,0x3c, ++0x74,0x04,0xf0,0x71,0xc4,0xef,0x64,0x01,0x70,0x2d,0x90,0x9e,0x69,0xe0,0xf5,0x44, ++0x75,0x45,0x00,0xe4,0xfb,0xfd,0x7f,0x58,0x7e,0x01,0x12,0x30,0x62,0x90,0x01,0x5b, ++0x74,0x05,0xf0,0x90,0x06,0x92,0x74,0x01,0xf0,0x90,0x9e,0x71,0xf0,0x80,0x08,0x71, ++0xc4,0xbf,0x01,0x03,0x12,0x44,0xd1,0xe5,0x2c,0x30,0xe1,0x21,0x90,0x01,0x34,0x74, ++0x02,0xf0,0x85,0xd1,0x13,0x85,0xd2,0x14,0x85,0xd3,0x15,0x85,0xd4,0x16,0x85,0xd5, ++0x17,0x85,0xd6,0x18,0x85,0xd7,0x19,0x85,0xd9,0x1a,0x12,0x5c,0x46,0xe5,0x2c,0x30, ++0xe3,0x06,0x90,0x01,0x34,0x74,0x08,0xf0,0xe5,0x2c,0x30,0xe4,0x09,0x90,0x01,0x34, ++0x74,0x10,0xf0,0x43,0x12,0x10,0xe5,0x2c,0x30,0xe5,0x24,0x90,0x01,0xcf,0xe0,0x30, ++0xe5,0x1d,0xe0,0x54,0xdf,0xf0,0x90,0x01,0x34,0x74,0x20,0xf0,0x75,0xa8,0x00,0x75, ++0xe8,0x00,0xd1,0xdb,0x90,0x00,0x03,0xe0,0x54,0xfb,0xf0,0x71,0xdb,0x80,0xfe,0xe5, ++0x2c,0x30,0xe6,0x06,0x90,0x01,0x34,0x74,0x40,0xf0,0xe5,0x2e,0x30,0xe0,0x12,0x90, ++0x9e,0x5f,0x74,0x01,0xf0,0x90,0x01,0x36,0xf0,0x12,0x65,0xa3,0x90,0x9e,0x5f,0xe4, ++0xf0,0xe5,0x2e,0x30,0xe1,0x3b,0x90,0x01,0x36,0x74,0x02,0xf0,0x43,0x12,0x40,0x90, ++0x01,0x02,0xe0,0x54,0x03,0x64,0x01,0x70,0x28,0x90,0x01,0x37,0xe0,0x30,0xe0,0x0a, ++0x74,0x01,0xf0,0x90,0x9e,0x4f,0xe4,0xf0,0x80,0x17,0x90,0x9e,0x4f,0xe0,0x04,0xf0, ++0xe0,0xc3,0x94,0x0a,0x40,0x0b,0xe4,0xf0,0x90,0x04,0x19,0xe0,0x30,0xe0,0x02,0x11, ++0x62,0xe5,0x2e,0x30,0xe2,0x09,0x90,0x01,0x36,0x74,0x04,0xf0,0x12,0x65,0x3b,0xe5, ++0x2e,0x30,0xe3,0x28,0x90,0x01,0x36,0x74,0x08,0xf0,0xe5,0x22,0x64,0x01,0x70,0x1c, ++0xe5,0x25,0x60,0x18,0x90,0x01,0x57,0xe4,0xf0,0x90,0x01,0x3c,0x74,0x02,0xf0,0x90, ++0x9e,0x86,0xe4,0x12,0x44,0x52,0x90,0x01,0x57,0x74,0x05,0xf0,0xe5,0x2e,0x30,0xe4, ++0x2b,0x90,0x01,0x36,0x74,0x10,0xf0,0xe5,0x22,0xb4,0x01,0x20,0xe5,0x25,0x60,0x1c, ++0x90,0x01,0x57,0xe4,0xf0,0x90,0x01,0x3c,0x74,0x02,0xf0,0x90,0x9e,0x74,0xe4,0xf0, ++0x53,0x26,0xfd,0xe5,0x26,0x54,0x07,0x70,0x03,0x12,0x44,0xd1,0xe5,0x2e,0x30,0xe5, ++0x1f,0x90,0x01,0x36,0x74,0x20,0xf0,0xe5,0x22,0xb4,0x01,0x14,0xe5,0x25,0x60,0x10, ++0x90,0x9e,0x73,0xe0,0x64,0x02,0x60,0x05,0x12,0x44,0xd7,0x80,0x03,0x12,0x44,0x80, ++0xe5,0x2e,0x30,0xe6,0x1b,0x90,0x01,0x36,0x74,0x40,0xf0,0xe5,0x22,0xb4,0x01,0x10, ++0xe5,0x25,0x60,0x0c,0x53,0x26,0xfe,0xe5,0x26,0x54,0x07,0x70,0x03,0x12,0x44,0xd1, ++0xe5,0x2f,0x30,0xe1,0x09,0x90,0x01,0x37,0x74,0x02,0xf0,0x12,0x61,0x92,0x74,0x79, ++0x04,0x90,0x01,0xc4,0xf0,0x74,0x48,0xa3,0xf0,0xd0,0x07,0xd0,0x06,0xd0,0x05,0xd0, ++0x04,0xd0,0x03,0xd0,0x02,0xd0,0x01,0xd0,0x00,0xd0,0xd0,0xd0,0x82,0xd0,0x83,0xd0, ++0xf0,0xd0,0xe0,0x32,0x90,0x04,0x1b,0xe0,0x54,0x7f,0x64,0x7f,0x7f,0x01,0x60,0x02, ++0x7f,0x00,0x22,0xf4,0xff,0x90,0x00,0x43,0xe0,0x5f,0xf0,0xd3,0x10,0xaf,0x01,0xc3, ++0xc0,0xd0,0x7f,0x10,0xdf,0xfe,0xd0,0xd0,0x92,0xaf,0x22,0xd3,0x10,0xaf,0x01,0xc3, ++0xc0,0xd0,0x90,0x9e,0xac,0xed,0xf0,0x90,0x9e,0xab,0xef,0xf0,0xd3,0x94,0x07,0x50, ++0x63,0xe0,0xff,0x74,0x01,0xa8,0x07,0x08,0x80,0x02,0xc3,0x33,0xd8,0xfc,0xf4,0xff, ++0x90,0x00,0x47,0xe0,0x5f,0xf0,0x71,0xdb,0x90,0x9e,0xab,0xe0,0xff,0x74,0x01,0xa8, ++0x07,0x08,0x80,0x02,0xc3,0x33,0xd8,0xfc,0xff,0x90,0x00,0x46,0xe0,0x4f,0xf0,0x71, ++0xdb,0x90,0x9e,0xac,0xe0,0x60,0x16,0x90,0x9e,0xab,0xe0,0xff,0x74,0x01,0xa8,0x07, ++0x08,0x80,0x02,0xc3,0x33,0xd8,0xfc,0xff,0x90,0x00,0x45,0x80,0x66,0x90,0x9e,0xab, ++0xe0,0xff,0x74,0x01,0xa8,0x07,0x08,0x80,0x02,0xc3,0x33,0xd8,0xfc,0xf4,0xff,0x90, ++0x00,0x45,0x80,0x6b,0x90,0x9e,0xab,0xe0,0x24,0xf8,0xf0,0xe0,0xff,0x74,0x01,0xa8, ++0x07,0x08,0x80,0x02,0xc3,0x33,0xd8,0xfc,0xc4,0x54,0xf0,0x71,0xd3,0x90,0x9e,0xab, ++0xe0,0xff,0x74,0x01,0xa8,0x07,0x08,0x80,0x02,0xc3,0x33,0xd8,0xfc,0xff,0x90,0x00, ++0x43,0xe0,0x4f,0xf0,0x71,0xdb,0x90,0x9e,0xac,0xe0,0x60,0x1b,0x90,0x9e,0xab,0xe0, ++0xff,0x74,0x01,0xa8,0x07,0x08,0x80,0x02,0xc3,0x33,0xd8,0xfc,0xc4,0x54,0xf0,0xff, ++0x90,0x00,0x42,0xe0,0x4f,0x80,0x1a,0x90,0x9e,0xab,0xe0,0xff,0x74,0x01,0xa8,0x07, ++0x08,0x80,0x02,0xc3,0x33,0xd8,0xfc,0xc4,0x54,0xf0,0xf4,0xff,0x90,0x00,0x42,0xe0, ++0x5f,0xf0,0x71,0xdb,0xd0,0xd0,0x92,0xaf,0x22,0xf0,0x90,0x00,0x45,0xe0,0x54,0xfe, ++0xfd,0x7f,0x45,0xd3,0x10,0xaf,0x01,0xc3,0xc0,0xd0,0x8f,0x82,0x75,0x83,0x00,0xed, ++0xf0,0x71,0xdb,0xd0,0xd0,0x92,0xaf,0x22,0xef,0x14,0x60,0x30,0x14,0x60,0x66,0x24, ++0x02,0x60,0x02,0xa1,0x9f,0x90,0x9e,0x1a,0x74,0x02,0xf0,0x90,0x00,0x48,0xe0,0x44, ++0x0c,0xfd,0x7f,0x48,0x91,0xe3,0x90,0x00,0x47,0xe0,0x44,0x08,0xfd,0x7f,0x47,0x91, ++0xe3,0x90,0x00,0x45,0xe0,0x44,0x10,0xfd,0x7f,0x45,0x80,0x71,0xe4,0x90,0x9e,0x1a, ++0xf0,0x90,0x9e,0x16,0x12,0x43,0x53,0x90,0x80,0x96,0x12,0x25,0x08,0x7f,0x80,0x7e, ++0x08,0x12,0x2b,0x08,0x90,0x00,0x45,0xe0,0x44,0xef,0xfd,0x7f,0x45,0x91,0xe3,0x90, ++0x00,0x45,0xe0,0x54,0xef,0xfd,0x7f,0x45,0x91,0xe3,0x90,0x00,0x46,0xe0,0x44,0x10, ++0xfd,0x7f,0x46,0x80,0x38,0x90,0x9e,0x1a,0x74,0x01,0xf0,0x90,0x9e,0x20,0x12,0x43, ++0x53,0x90,0x80,0x96,0x12,0x25,0x08,0x7f,0x80,0x7e,0x08,0x12,0x2b,0x08,0x90,0x00, ++0x45,0xe0,0x44,0x20,0xfd,0x7f,0x45,0x91,0xe3,0x90,0x00,0x45,0xe0,0x44,0x10,0xfd, ++0x7f,0x45,0x91,0xe3,0x90,0x00,0x46,0xe0,0x44,0x10,0xfd,0x7f,0x46,0x91,0xe3,0x22, ++0x90,0x00,0x02,0x12,0x42,0x20,0x90,0x9e,0x1c,0xf0,0x90,0x00,0x01,0x12,0x42,0x20, ++0x25,0xe0,0x25,0xe0,0x90,0x9e,0x1b,0xf0,0x12,0x24,0x62,0x25,0xe0,0x25,0xe0,0x90, ++0x9e,0x1f,0xf0,0x90,0x05,0x60,0xe0,0x90,0x9e,0x2a,0xf0,0x90,0x05,0x61,0xe0,0x90, ++0x9e,0x2b,0xf0,0x90,0x05,0x62,0xe0,0x90,0x9e,0x2c,0xf0,0x90,0x05,0x63,0xe0,0x90, ++0x9e,0x2d,0xf0,0xa2,0xaf,0xe4,0x33,0x90,0x9e,0x3f,0xf0,0xc2,0xaf,0x90,0x9e,0x1b, ++0xe0,0xff,0x12,0x52,0x12,0x90,0x9e,0x3f,0xe0,0x24,0xff,0x92,0xaf,0x90,0x9e,0x1c, ++0xe0,0x70,0x02,0xc1,0xa7,0x90,0x9e,0x1b,0xe0,0x70,0x02,0xc1,0xa7,0x90,0x9e,0x1f, ++0xe0,0x70,0x02,0xc1,0xa7,0xa2,0xaf,0xe4,0x33,0x90,0x9e,0x3f,0xf0,0xc2,0xaf,0x90, ++0x9e,0x2e,0x74,0x01,0xf0,0x90,0x9e,0x3f,0xe0,0x24,0xff,0x92,0xaf,0x91,0xda,0x90, ++0x00,0x46,0xe0,0x44,0x01,0xfd,0x7f,0x46,0x91,0xe3,0x90,0x9e,0x14,0xe0,0x60,0x15, ++0x90,0x9e,0x20,0x12,0x43,0x53,0x90,0x80,0x96,0x12,0x25,0x08,0x7f,0x80,0x7e,0x08, ++0x12,0x2b,0x08,0x80,0x06,0x90,0x05,0x22,0x74,0x7f,0xf0,0x90,0x00,0x45,0xe0,0x54, ++0xef,0xfd,0x7f,0x45,0x91,0xe3,0x90,0x05,0x87,0xe0,0x64,0x80,0xf0,0x90,0x9e,0x2a, ++0xe0,0x90,0x05,0x84,0xf0,0x90,0x9e,0x2b,0xe0,0x90,0x05,0x85,0xf0,0x90,0x9e,0x2c, ++0xe0,0x90,0x05,0x86,0xf0,0x90,0x9e,0x2d,0xe0,0x90,0x05,0x87,0xf0,0xa2,0xaf,0xe4, ++0x33,0x90,0x9e,0x3f,0xf0,0xc2,0xaf,0x90,0x01,0x3c,0xe0,0x44,0x20,0xf0,0x7d,0x20, ++0xe4,0xff,0x12,0x31,0xb7,0x80,0x2b,0x90,0x9e,0x1c,0xe0,0x70,0x2d,0x90,0x9e,0x2e, ++0x91,0xd9,0x90,0x00,0x46,0xe0,0x54,0xfe,0xfd,0x7f,0x46,0x91,0xe3,0x90,0x05,0x22, ++0xe4,0xf0,0xa2,0xaf,0x33,0x90,0x9e,0x3f,0xf0,0xc2,0xaf,0x7d,0x20,0xe4,0xff,0x12, ++0x31,0x49,0x90,0x9e,0x3f,0xe0,0x24,0xff,0x92,0xaf,0x22,0x90,0x01,0x30,0xe4,0xf0, ++0xa3,0xf0,0xa3,0xf0,0xa3,0xf0,0x90,0x01,0x38,0xf0,0xa3,0xf0,0xa3,0xf0,0xa3,0xf0, ++0xfd,0x7f,0x50,0x91,0xe3,0xe4,0xfd,0x7f,0x51,0x91,0xe3,0xe4,0xfd,0x7f,0x52,0x91, ++0xe3,0xe4,0xfd,0x7f,0x53,0x81,0xe3,0x8b,0x59,0x8a,0x5a,0x89,0x5b,0x90,0x00,0x02, ++0x12,0x42,0x20,0x90,0x9e,0x1d,0xf0,0xe0,0x30,0xe0,0x4b,0x90,0x9e,0x14,0x74,0x01, ++0xf0,0x7f,0x80,0x7e,0x08,0x12,0x22,0x65,0x90,0x9e,0x16,0x12,0x25,0x08,0xab,0x59, ++0xaa,0x5a,0xa9,0x5b,0x90,0x00,0x01,0x12,0x42,0x20,0xff,0xe4,0xfc,0xfd,0xfe,0x78, ++0x1a,0x12,0x24,0xf5,0xa8,0x04,0xa9,0x05,0xaa,0x06,0xab,0x07,0x90,0x9e,0x16,0x12, ++0x43,0x53,0xec,0x54,0x03,0xfc,0x12,0x43,0x46,0x90,0x9e,0x20,0x12,0x25,0x08,0x90, ++0x05,0x22,0xe4,0xf0,0x80,0x2d,0xe4,0x90,0x9e,0x14,0xf0,0x7f,0x80,0x7e,0x08,0x12, ++0x22,0x65,0xec,0x54,0x03,0xfc,0xec,0x44,0xc0,0xfc,0x90,0x9e,0x16,0x12,0x25,0x08, ++0x90,0x9e,0x16,0x12,0x43,0x53,0x90,0x80,0x96,0x12,0x25,0x08,0x7f,0x80,0x7e,0x08, ++0x12,0x2b,0x08,0x90,0x9e,0x1d,0xe0,0x30,0xe1,0x19,0x7d,0x0c,0x7f,0x47,0x91,0xe3, ++0x90,0x00,0x48,0xe0,0x44,0x0c,0xfd,0x7f,0x48,0x91,0xe3,0x90,0x00,0x46,0xe0,0x44, ++0x10,0x80,0x1c,0x90,0x00,0x47,0xe0,0x54,0xf3,0xfd,0x7f,0x47,0x91,0xe3,0x90,0x00, ++0x48,0xe0,0x54,0xf3,0xfd,0x7f,0x48,0x91,0xe3,0x90,0x00,0x46,0xe0,0x54,0xef,0xfd, ++0x7f,0x46,0x91,0xe3,0xe4,0x90,0x9e,0x1a,0xf0,0x22,0x90,0x00,0x49,0xe0,0x90,0x9e, ++0xb0,0xf0,0xe0,0x54,0x0f,0xf0,0x44,0xf0,0xfd,0x7f,0x49,0x91,0xe3,0x90,0x9e,0xb0, ++0xe0,0x44,0xb0,0xfd,0x7f,0x49,0x81,0xe3,0x75,0x28,0x33,0xe4,0xf5,0x29,0x75,0x2a, ++0x07,0xf5,0x2b,0x90,0x01,0x30,0xe5,0x28,0xf0,0xa3,0xe5,0x29,0xf0,0xa3,0xe5,0x2a, ++0xf0,0xa3,0xe5,0x2b,0xf0,0x22,0x75,0x30,0x1f,0x75,0x31,0x01,0xe4,0xf5,0x32,0x90, ++0x01,0x38,0xe5,0x30,0xf0,0xa3,0xe5,0x31,0xf0,0xa3,0xe5,0x32,0xf0,0x22,0xe4,0x90, ++0x9e,0x31,0xf0,0xa3,0xf0,0x75,0x8e,0x02,0x12,0x77,0x64,0x12,0x5e,0xde,0x90,0x9e, ++0x5e,0xef,0xf0,0x12,0x5e,0xeb,0x90,0x9e,0x60,0xef,0xf0,0xe4,0xf5,0x12,0x12,0x6e, ++0xdf,0x12,0x77,0xdb,0x12,0x5f,0x9f,0x12,0x2e,0x01,0x12,0x77,0xd7,0x12,0x4f,0xf8, ++0x90,0x00,0xf3,0xe0,0x30,0xe2,0x0d,0x90,0x05,0x41,0x74,0x10,0xf0,0x90,0x05,0x5a, ++0xf0,0xa3,0xe4,0xf0,0x12,0x5e,0xf8,0x11,0x16,0x12,0x44,0xff,0x12,0x7d,0x9b,0x90, ++0x9e,0x33,0xe5,0xd9,0xf0,0x12,0x5e,0xaf,0xc2,0xaf,0x90,0x00,0x80,0xe0,0x44,0x40, ++0xf0,0x12,0x4b,0xdb,0x75,0xe8,0x03,0x43,0xa8,0x85,0xd2,0xaf,0x90,0x9e,0x31,0xe0, ++0x64,0x01,0xf0,0x24,0x2e,0x90,0x01,0xc4,0xf0,0x74,0x50,0xa3,0xf0,0xe5,0x12,0x30, ++0xe4,0x09,0xc2,0xaf,0x53,0x12,0xef,0xd2,0xaf,0x71,0x1a,0xe5,0x12,0x30,0xe6,0x16, ++0xc2,0xaf,0x53,0x12,0xbf,0xd2,0xaf,0x12,0x68,0x8d,0x90,0x9e,0x1e,0xe0,0xff,0x60, ++0x03,0xb4,0x01,0x02,0x31,0x10,0x90,0x9e,0x1e,0xe0,0x70,0x03,0x12,0x7d,0xf9,0x11, ++0xe3,0x80,0xb9,0x90,0x06,0x34,0xe0,0x60,0x26,0x14,0x70,0x1b,0x7b,0x01,0x7a,0x06, ++0x79,0x35,0x7f,0xf9,0x7e,0x01,0x12,0x77,0x75,0xbf,0x01,0x09,0x90,0x06,0x35,0xe0, ++0x54,0x0f,0xf0,0x80,0x05,0x80,0x00,0x02,0x77,0x56,0xe4,0x90,0x06,0x34,0xf0,0x22, ++0x90,0x9e,0x15,0xe0,0xc3,0x94,0x14,0x50,0x05,0xe0,0x04,0xf0,0x21,0xc8,0x90,0x9e, ++0x15,0xe0,0x64,0x14,0x60,0x02,0x21,0xc8,0x90,0x9e,0x24,0xe0,0x70,0x25,0x90,0x9e, ++0x27,0xe0,0x70,0x1f,0x90,0x9e,0x25,0xe0,0x70,0x19,0x90,0x9e,0x28,0xe0,0x70,0x13, ++0x90,0x9e,0x26,0xe0,0x70,0x0d,0x90,0x9e,0x29,0xe0,0x70,0x07,0x90,0x04,0xfd,0xe0, ++0x54,0xfe,0xf0,0x90,0x9e,0x24,0xe0,0x90,0x04,0x44,0xf0,0x90,0x9e,0x25,0xe0,0x90, ++0x04,0x45,0xf0,0x90,0x9e,0x26,0xe0,0x90,0x04,0x46,0xf0,0xa3,0xe4,0xf0,0x90,0x9e, ++0x27,0xe0,0x90,0x04,0x48,0xf0,0x90,0x9e,0x28,0xe0,0x90,0x04,0x49,0xf0,0x90,0x9e, ++0x29,0xe0,0x90,0x04,0x4a,0xf0,0xa3,0xe4,0xf0,0x90,0x9e,0x10,0xe0,0x90,0x04,0x4c, ++0xf0,0x90,0x9e,0x11,0xe0,0x90,0x04,0x4d,0xf0,0x90,0x9e,0x12,0xe0,0x90,0x04,0x4e, ++0xf0,0x90,0x9e,0x13,0xe0,0x90,0x04,0x4f,0xf0,0xe4,0x90,0x9e,0x15,0xf0,0x90,0x9e, ++0x10,0x04,0xf0,0xe4,0xa3,0xf0,0xa3,0xf0,0xa3,0xf0,0x90,0x9e,0x24,0xf0,0xa3,0xf0, ++0xa3,0xf0,0xa3,0xf0,0xa3,0xf0,0xa3,0xf0,0x90,0x05,0x60,0xe0,0x90,0x9e,0x34,0xf0, ++0x90,0x05,0x61,0xe0,0x90,0x9e,0x35,0xf0,0x90,0x05,0x62,0xe0,0x90,0x9e,0x36,0xf0, ++0x90,0x05,0x63,0xe0,0x90,0x9e,0x37,0xf0,0x90,0x9e,0x2d,0xe0,0xff,0x90,0x9e,0x37, ++0xe0,0xfe,0xd3,0x9f,0x50,0x0b,0x90,0x9e,0x2d,0xe0,0xc3,0x9e,0xd3,0x94,0x01,0x40, ++0x10,0x90,0x9e,0x1b,0xe0,0xb4,0x01,0x02,0x80,0x03,0x90,0x9e,0x1f,0xe0,0xff,0x51, ++0x12,0x22,0x90,0x05,0x60,0xe0,0x90,0x9e,0x2a,0xf0,0x90,0x05,0x61,0xe0,0x90,0x9e, ++0x2b,0xf0,0x90,0x05,0x62,0xe0,0x90,0x9e,0x2c,0xf0,0x90,0x05,0x63,0xe0,0x90,0x9e, ++0x2d,0xf0,0xc3,0x74,0xff,0x9f,0xfe,0x90,0x9e,0x2b,0xe0,0xd3,0x9e,0x40,0x1e,0xe0, ++0x2f,0xf0,0xa3,0xe0,0xb4,0xff,0x0f,0xe4,0xf0,0xa3,0xe0,0xb4,0xff,0x03,0xe4,0xf0, ++0x22,0x90,0x9e,0x2d,0x80,0x03,0x90,0x9e,0x2c,0xe0,0x04,0xf0,0x22,0x90,0x9e,0x2b, ++0xe0,0x2f,0xf0,0x22,0x90,0x9e,0x1c,0xe0,0x64,0x01,0x60,0x02,0x61,0x19,0x90,0x00, ++0x46,0xe0,0x44,0x01,0xfd,0x7f,0x46,0x12,0x4c,0xe3,0x90,0x9e,0x2e,0xe0,0x70,0x32, ++0x90,0x9e,0x14,0xe0,0x60,0x15,0x90,0x9e,0x20,0x12,0x43,0x53,0x90,0x80,0x96,0x12, ++0x25,0x08,0x7f,0x80,0x7e,0x08,0x12,0x2b,0x08,0x80,0x06,0x90,0x05,0x22,0x74,0x7f, ++0xf0,0x90,0x9e,0x1b,0xe0,0xff,0x51,0x12,0x90,0x9e,0x2e,0x74,0x01,0x12,0x4c,0xd9, ++0x80,0x40,0x90,0x9e,0x2e,0xe0,0x64,0x01,0x70,0x38,0x90,0x9e,0x1f,0xe0,0xff,0x51, ++0x12,0xe4,0x90,0x9e,0x2e,0xf0,0x90,0x00,0x45,0xe0,0x44,0x01,0xfd,0x7f,0x45,0x12, ++0x4c,0xe3,0x90,0x9e,0x14,0xe0,0x60,0x15,0x90,0x9e,0x16,0x12,0x43,0x53,0x90,0x80, ++0x96,0x12,0x25,0x08,0x7f,0x80,0x7e,0x08,0x12,0x2b,0x08,0x80,0x05,0x90,0x05,0x22, ++0xe4,0xf0,0x90,0x05,0x87,0xe0,0x64,0x80,0xf0,0x90,0x9e,0x2a,0xe0,0x90,0x05,0x84, ++0xf0,0x90,0x9e,0x2b,0xe0,0x90,0x05,0x85,0xf0,0x90,0x9e,0x2c,0xe0,0x90,0x05,0x86, ++0xf0,0x90,0x9e,0x2d,0xe0,0x90,0x05,0x87,0xf0,0x22,0x90,0x01,0xcc,0xe0,0x54,0x0f, ++0x90,0x9e,0x34,0xf0,0x90,0x9e,0x34,0xe0,0xfd,0x70,0x02,0x81,0x5b,0x90,0x9e,0xad, ++0xe0,0xff,0x74,0x01,0x7e,0x00,0xa8,0x07,0x08,0x80,0x05,0xc3,0x33,0xce,0x33,0xce, ++0xd8,0xf9,0xff,0xef,0x5d,0x70,0x02,0x81,0x54,0x90,0x9e,0xad,0xe0,0x75,0xf0,0x04, ++0x90,0x01,0xd0,0x12,0x43,0x5f,0xe0,0x90,0x9e,0x35,0xf0,0x75,0x1e,0x01,0x75,0x1f, ++0x9e,0x75,0x20,0x35,0x75,0x21,0x01,0x7b,0x01,0x7a,0x9e,0x79,0x36,0x12,0x45,0x09, ++0x90,0x9e,0x36,0xe0,0xff,0xc4,0x13,0x13,0x13,0x54,0x01,0x90,0x9e,0xad,0x30,0xe0, ++0x59,0xe0,0x75,0xf0,0x02,0x90,0x00,0x88,0x12,0x43,0x5f,0xe0,0x90,0x9e,0x37,0xf0, ++0x90,0x9e,0xad,0xe0,0x75,0xf0,0x02,0x90,0x00,0x89,0x12,0x43,0x5f,0xe0,0x90,0x9e, ++0x38,0xf0,0x90,0x9e,0xad,0xe0,0x75,0xf0,0x04,0x90,0x01,0xd1,0x12,0x43,0x5f,0xe0, ++0x90,0x9e,0x39,0xf0,0x90,0x9e,0xad,0xe0,0x75,0xf0,0x04,0x90,0x01,0xd2,0x12,0x43, ++0x5f,0xe0,0x90,0x9e,0x3a,0xf0,0x90,0x9e,0xad,0xe0,0x75,0xf0,0x04,0x90,0x01,0xd3, ++0x12,0x43,0x5f,0xe0,0x90,0x9e,0x3b,0xf0,0x80,0x33,0xe0,0x75,0xf0,0x04,0x90,0x01, ++0xd1,0x12,0x43,0x5f,0xe0,0x90,0x9e,0x37,0xf0,0x90,0x9e,0xad,0xe0,0x75,0xf0,0x04, ++0x90,0x01,0xd2,0x12,0x43,0x5f,0xe0,0x90,0x9e,0x38,0xf0,0x90,0x9e,0xad,0xe0,0x75, ++0xf0,0x04,0x90,0x01,0xd3,0x12,0x43,0x5f,0xe0,0x90,0x9e,0x39,0xf0,0xef,0x54,0x7f, ++0xff,0x7b,0x01,0x7a,0x9e,0x79,0x37,0x91,0x5c,0x90,0x9e,0x34,0xe0,0xff,0x90,0x9e, ++0xad,0xe0,0xfe,0x74,0x01,0xa8,0x06,0x08,0x80,0x02,0xc3,0x33,0xd8,0xfc,0xf4,0x5f, ++0x90,0x9e,0x34,0xf0,0x90,0x9e,0xad,0xe0,0xff,0x74,0x01,0xa8,0x07,0x08,0x80,0x02, ++0xc3,0x33,0xd8,0xfc,0x90,0x01,0xcc,0xf0,0x90,0x9e,0xad,0xe0,0x04,0xf0,0xe0,0x54, ++0x03,0xf0,0x61,0x24,0x90,0x01,0xc6,0xe0,0x44,0x02,0xf0,0x22,0x90,0x9e,0x3c,0x12, ++0x43,0x8b,0xef,0x12,0x43,0x94,0x54,0x97,0x01,0x54,0xa0,0x02,0x54,0xbb,0x03,0x54, ++0xc4,0x05,0x54,0xcd,0x06,0x55,0x1b,0x07,0x54,0xd5,0x09,0x54,0xde,0x0c,0x54,0xe7, ++0x0d,0x54,0xf0,0x0e,0x54,0xf9,0x1b,0x55,0x02,0x1c,0x55,0x0b,0x2c,0x54,0xa9,0x2d, ++0x54,0xb2,0x2e,0x00,0x00,0x55,0x14,0x90,0x9e,0x3c,0x12,0x43,0x6b,0x02,0x61,0x69, ++0x90,0x9e,0x3c,0x12,0x43,0x6b,0x02,0x71,0x02,0x90,0x9e,0x3c,0x12,0x43,0x6b,0x02, ++0x71,0x08,0x90,0x9e,0x3c,0x12,0x43,0x6b,0x02,0x71,0x50,0x90,0x9e,0x3c,0x12,0x43, ++0x6b,0x02,0x71,0x7e,0x90,0x9e,0x3c,0x12,0x43,0x6b,0x02,0x70,0xb2,0x90,0x9e,0x3c, ++0x12,0x43,0x6b,0x80,0x47,0x90,0x9e,0x3c,0x12,0x43,0x6b,0x02,0x71,0xc6,0x90,0x9e, ++0x3c,0x12,0x43,0x6b,0x02,0x4d,0xa0,0x90,0x9e,0x3c,0x12,0x43,0x6b,0x02,0x7d,0x68, ++0x90,0x9e,0x3c,0x12,0x43,0x6b,0x02,0x4f,0x07,0x90,0x9e,0x3c,0x12,0x43,0x6b,0x02, ++0x70,0xfa,0x90,0x9e,0x3c,0x12,0x43,0x6b,0x02,0x70,0xe1,0x90,0x9e,0x3c,0x12,0x43, ++0x6b,0x02,0x76,0x36,0x90,0x01,0xc6,0xe0,0x44,0x01,0xf0,0x22,0x90,0x00,0x04,0x12, ++0x42,0x20,0xff,0x54,0x1f,0xfe,0xef,0x54,0x20,0xc4,0x13,0x54,0x07,0xfd,0xaf,0x06, ++0x90,0x9e,0x3f,0xef,0xf0,0xa3,0xed,0xf0,0xa3,0x12,0x43,0x8b,0x90,0x9e,0x41,0x12, ++0x43,0x6b,0x90,0x00,0x03,0x12,0x42,0x20,0x54,0xf0,0xc4,0x54,0x0f,0x90,0x9e,0x44, ++0xf0,0x90,0x00,0x04,0x12,0x42,0x20,0x54,0x40,0xc4,0x13,0x13,0x54,0x03,0x90,0x9e, ++0x45,0xf0,0x90,0x9e,0x3f,0xe0,0xff,0x75,0xf0,0x09,0x90,0x96,0x46,0x12,0x43,0x5f, ++0xad,0x82,0xac,0x83,0x90,0x9e,0x46,0xec,0xf0,0xa3,0xed,0xf0,0xef,0x75,0xf0,0x09, ++0xa4,0x24,0x44,0xf9,0x74,0x96,0x35,0xf0,0xfa,0x7b,0x01,0xa3,0x12,0x43,0x8b,0x90, ++0x9e,0x41,0x12,0x43,0x6b,0x90,0x00,0x03,0x12,0x42,0x20,0x54,0x0f,0xff,0x90,0x9e, ++0x48,0x12,0x43,0x6b,0xef,0x12,0x42,0x4d,0x90,0x9e,0x41,0x12,0x43,0x6b,0x90,0x00, ++0x02,0x12,0x42,0x20,0xff,0x90,0x9e,0x48,0x12,0x43,0x6b,0x90,0x00,0x01,0xef,0x12, ++0x42,0x5f,0x90,0x9e,0x41,0x12,0x43,0x6b,0x90,0x00,0x01,0x12,0x42,0x20,0xff,0x90, ++0x9e,0x46,0xe0,0xfc,0xa3,0xe0,0xfd,0xf5,0x82,0x8c,0x83,0xef,0xf0,0x12,0x24,0x62, ++0x8d,0x82,0x8c,0x83,0xa3,0xf0,0x90,0x9e,0x44,0xe0,0xfe,0x90,0x9e,0x3f,0xe0,0xff, ++0x24,0x82,0xf5,0x82,0xe4,0x34,0x95,0xf5,0x83,0xee,0xf0,0x90,0x9e,0x40,0xe0,0xfe, ++0x75,0xf0,0x09,0xef,0x90,0x96,0x4a,0x12,0x43,0x5f,0xee,0xf0,0x75,0xf0,0x09,0xef, ++0x90,0x96,0x4b,0x12,0x43,0x5f,0x74,0x01,0xf0,0x90,0x9e,0x45,0xe0,0xfe,0x75,0xf0, ++0x09,0xef,0x90,0x96,0x4c,0x12,0x43,0x5f,0xee,0xf0,0x8f,0x59,0xef,0x25,0xe0,0x24, ++0xc6,0xf5,0x82,0xe4,0x34,0x9b,0xaf,0x82,0xf5,0x5b,0x8f,0x5c,0xe5,0x59,0x75,0xf0, ++0x02,0xa4,0x24,0x02,0xf9,0x74,0x95,0x35,0xf0,0x75,0x5d,0x01,0xf5,0x5e,0x89,0x5f, ++0x75,0xf0,0x09,0xe5,0x59,0x90,0x96,0x46,0x12,0x43,0x5f,0xaf,0x82,0x85,0x83,0x60, ++0x8f,0x61,0xe5,0x59,0x75,0xf0,0x09,0xa4,0x24,0x44,0xf9,0x74,0x96,0x35,0xf0,0x75, ++0x62,0x01,0xf5,0x63,0x89,0x64,0x74,0x82,0x25,0x59,0xf5,0x82,0xe4,0x34,0x95,0xf5, ++0x83,0xe0,0x12,0x43,0x94,0x56,0xaa,0x00,0x56,0xbf,0x01,0x56,0xd4,0x02,0x56,0xe9, ++0x03,0x57,0x13,0x04,0x57,0x28,0x05,0x57,0x3d,0x06,0x57,0x64,0x0c,0x57,0x92,0x0d, ++0x57,0xbf,0x0e,0x57,0xec,0x0f,0x00,0x00,0x58,0x20,0xe5,0x59,0x25,0xe0,0x24,0xc6, ++0xf5,0x82,0xe4,0x34,0x9b,0xf5,0x83,0x74,0xf0,0xf0,0xa3,0x74,0x15,0x80,0x3c,0xe5, ++0x59,0x25,0xe0,0x24,0xc6,0xf5,0x82,0xe4,0x34,0x9b,0xf5,0x83,0x74,0xf0,0xf0,0xa3, ++0x74,0x10,0x80,0x27,0xe5,0x59,0x25,0xe0,0x24,0xc6,0xf5,0x82,0xe4,0x34,0x9b,0xf5, ++0x83,0x74,0xf0,0xf0,0xa3,0x74,0x05,0x80,0x12,0xe5,0x59,0x25,0xe0,0x24,0xc6,0xf5, ++0x82,0xe4,0x34,0x9b,0xf5,0x83,0x74,0xf0,0xf0,0xa3,0xe4,0xf0,0xe5,0x59,0x25,0xe0, ++0x24,0x02,0xf5,0x82,0xe4,0x34,0x95,0xf5,0x83,0x74,0x0f,0xf0,0xa3,0x74,0x8f,0xf0, ++0x02,0x58,0x20,0xe5,0x59,0x25,0xe0,0x24,0xc6,0xf5,0x82,0xe4,0x34,0x9b,0xf5,0x83, ++0x74,0x0f,0xf0,0xa3,0x74,0xf5,0x80,0x27,0xe5,0x59,0x25,0xe0,0x24,0xc6,0xf5,0x82, ++0xe4,0x34,0x9b,0xf5,0x83,0x74,0x0f,0xf0,0xa3,0x74,0xf0,0x80,0x12,0xe5,0x59,0x25, ++0xe0,0x24,0xc6,0xf5,0x82,0xe4,0x34,0x9b,0xf5,0x83,0xe4,0xf0,0xa3,0x74,0x0d,0xf0, ++0xe5,0x59,0x25,0xe0,0x24,0x02,0xf5,0x82,0xe4,0x34,0x95,0xf5,0x83,0xe4,0xf0,0xa3, ++0xf0,0x02,0x58,0x20,0x90,0x04,0x47,0xe0,0xab,0x5d,0xaa,0x5e,0xa9,0x5f,0x12,0x42, ++0x4d,0x90,0x04,0x46,0xe0,0xab,0x5d,0xaa,0x5e,0xa9,0x5f,0x90,0x00,0x01,0x12,0x42, ++0x5f,0x90,0x04,0x45,0xe0,0x85,0x5c,0x82,0x85,0x5b,0x83,0xf0,0x90,0x04,0x44,0x02, ++0x58,0x17,0x90,0x04,0x4b,0xe0,0xab,0x5d,0xaa,0x5e,0xa9,0x5f,0x12,0x42,0x4d,0x90, ++0x04,0x4a,0xe0,0xab,0x5d,0xaa,0x5e,0xa9,0x5f,0x90,0x00,0x01,0x12,0x42,0x5f,0x90, ++0x04,0x49,0xe0,0x85,0x5c,0x82,0x85,0x5b,0x83,0xf0,0x90,0x04,0x48,0x80,0x58,0x90, ++0x04,0x4f,0xe0,0xab,0x5d,0xaa,0x5e,0xa9,0x5f,0x12,0x42,0x4d,0x90,0x04,0x4e,0xe0, ++0xab,0x5d,0xaa,0x5e,0xa9,0x5f,0x90,0x00,0x01,0x12,0x42,0x5f,0x90,0x04,0x4d,0xe0, ++0x85,0x5c,0x82,0x85,0x5b,0x83,0xf0,0x90,0x04,0x4c,0x80,0x2b,0x90,0x04,0x53,0xe0, ++0xab,0x5d,0xaa,0x5e,0xa9,0x5f,0x12,0x42,0x4d,0x90,0x04,0x52,0xe0,0xab,0x5d,0xaa, ++0x5e,0xa9,0x5f,0x90,0x00,0x01,0x12,0x42,0x5f,0x90,0x04,0x51,0xe0,0x85,0x5c,0x82, ++0x85,0x5b,0x83,0xf0,0x90,0x04,0x50,0xe0,0x85,0x5c,0x82,0x85,0x5b,0x83,0xa3,0xf0, ++0xab,0x5d,0xaa,0x5e,0xa9,0x5f,0xc0,0x03,0xc0,0x02,0xc0,0x01,0x12,0x24,0x62,0xff, ++0xab,0x62,0xaa,0x63,0xa9,0x64,0x12,0x24,0x62,0x5f,0xd0,0x01,0xd0,0x02,0xd0,0x03, ++0x12,0x42,0x4d,0xab,0x5d,0xe5,0x5f,0x24,0x01,0xf9,0xe4,0x35,0x5e,0xfa,0xc0,0x03, ++0xc0,0x02,0xc0,0x01,0x12,0x24,0x62,0xff,0xab,0x62,0xaa,0x63,0xa9,0x64,0x90,0x00, ++0x01,0x12,0x42,0x20,0x5f,0xd0,0x01,0xd0,0x02,0xd0,0x03,0x12,0x42,0x4d,0x85,0x5c, ++0x82,0x85,0x5b,0x83,0xc0,0x83,0xc0,0x82,0xe0,0xff,0x85,0x61,0x82,0x85,0x60,0x83, ++0xe0,0xfe,0xef,0x5e,0xd0,0x82,0xd0,0x83,0xf0,0x85,0x5c,0x82,0x85,0x5b,0x83,0xa3, ++0xc0,0x83,0xc0,0x82,0xe0,0xff,0x85,0x61,0x82,0x85,0x60,0x83,0xa3,0xe0,0xfe,0xef, ++0x5e,0xd0,0x82,0xd0,0x83,0xf0,0xe5,0x59,0x25,0xe0,0x24,0x02,0xf5,0x82,0xe4,0x34, ++0x95,0xf5,0x83,0xe0,0xfe,0xa3,0xe0,0x4e,0x60,0x3b,0x75,0x5a,0x0b,0x74,0x01,0x7e, ++0x00,0xa8,0x5a,0x08,0x80,0x05,0xc3,0x33,0xce,0x33,0xce,0xd8,0xf9,0xff,0xe5,0x59, ++0x25,0xe0,0x24,0x02,0xf5,0x82,0xe4,0x34,0x95,0xf5,0x83,0xe0,0x5e,0xfe,0xa3,0xe0, ++0x5f,0x4e,0x60,0x06,0xe5,0x5a,0x24,0x10,0x80,0x5d,0x15,0x5a,0xe5,0x5a,0xc3,0x94, ++0x00,0x50,0xca,0x80,0x56,0xe5,0x59,0x25,0xe0,0x24,0xc6,0xf5,0x82,0xe4,0x34,0x9b, ++0xf5,0x83,0xe0,0xfe,0xa3,0xe0,0x4e,0x60,0x3d,0x75,0x5a,0x0f,0x74,0x01,0x7e,0x00, ++0xa8,0x5a,0x08,0x80,0x05,0xc3,0x33,0xce,0x33,0xce,0xd8,0xf9,0xff,0xe5,0x59,0x25, ++0xe0,0x24,0xc6,0xf5,0x82,0xe4,0x34,0x9b,0xf5,0x83,0xe0,0x5e,0xfe,0xa3,0xe0,0x5f, ++0x4e,0x60,0x08,0x90,0x9e,0x4b,0xe5,0x5a,0xf0,0x80,0x10,0x15,0x5a,0xe5,0x5a,0xc3, ++0x94,0x00,0x50,0xc8,0x80,0x05,0xe4,0x90,0x9e,0x4b,0xf0,0xe5,0x59,0x25,0xe0,0x24, ++0xc6,0xf5,0x82,0xe4,0x34,0x9b,0xf5,0x83,0xe0,0xfe,0xa3,0xe0,0x4e,0x60,0x3b,0xe4, ++0xf5,0x5a,0x74,0x01,0x7e,0x00,0xa8,0x5a,0x08,0x80,0x05,0xc3,0x33,0xce,0x33,0xce, ++0xd8,0xf9,0xff,0xe5,0x59,0x25,0xe0,0x24,0xc6,0xf5,0x82,0xe4,0x34,0x9b,0xf5,0x83, ++0xe0,0x5e,0xfe,0xa3,0xe0,0x5f,0x4e,0x60,0x08,0x90,0x9e,0x4c,0xe5,0x5a,0xf0,0x80, ++0x5b,0x05,0x5a,0xe5,0x5a,0xb4,0x10,0xca,0x80,0x52,0xe5,0x59,0x25,0xe0,0x24,0x02, ++0xf5,0x82,0xe4,0x34,0x95,0xf5,0x83,0xe0,0xfe,0xa3,0xe0,0x4e,0x60,0x39,0xe4,0xf5, ++0x5a,0x74,0x01,0x7e,0x00,0xa8,0x5a,0x08,0x80,0x05,0xc3,0x33,0xce,0x33,0xce,0xd8, ++0xf9,0xff,0xe5,0x59,0x25,0xe0,0x24,0x02,0xf5,0x82,0xe4,0x34,0x95,0xf5,0x83,0xe0, ++0x5e,0xfe,0xa3,0xe0,0x5f,0x4e,0x60,0x06,0xe5,0x5a,0x24,0x10,0x80,0x0a,0x05,0x5a, ++0xe5,0x5a,0xb4,0x0c,0xcc,0x80,0x05,0xe4,0x90,0x9e,0x4c,0xf0,0x90,0x9e,0x4b,0xe0, ++0xff,0x75,0xf0,0x09,0xe5,0x59,0x90,0x96,0x48,0x12,0x43,0x5f,0xef,0xf0,0x90,0x9e, ++0x4c,0xe0,0xfe,0x75,0xf0,0x09,0xe5,0x59,0x90,0x96,0x49,0x12,0x43,0x5f,0xee,0xf0, ++0x74,0x84,0x25,0x59,0xf5,0x82,0xe4,0x34,0x04,0xf5,0x83,0xe0,0xd3,0x9f,0x40,0x05, ++0x90,0x9e,0x4b,0x51,0x6f,0x74,0x84,0x25,0x59,0xf5,0x82,0xe4,0x34,0x04,0xf5,0x83, ++0xe0,0xff,0x90,0x9e,0x4c,0xe0,0xfe,0xef,0xc3,0x9e,0x50,0x02,0x51,0x6f,0x90,0x9e, ++0x4b,0xe0,0xff,0xd3,0x94,0x13,0x40,0x07,0x90,0x96,0x43,0x74,0x03,0xf0,0x22,0xef, ++0xd3,0x94,0x0b,0x40,0x07,0x90,0x96,0x43,0x74,0x02,0xf0,0x22,0xef,0xd3,0x94,0x03, ++0x40,0x07,0x90,0x96,0x43,0x74,0x01,0xf0,0x22,0xe4,0x90,0x96,0x43,0xf0,0x22,0xe0, ++0xfd,0x74,0x26,0x25,0x59,0xf5,0x82,0xe4,0x34,0x9d,0xf5,0x83,0xed,0xf0,0xaf,0x59, ++0xd3,0x10,0xaf,0x01,0xc3,0xc0,0xd0,0xef,0xc3,0x94,0x20,0x50,0x0e,0x74,0x84,0x2f, ++0xf5,0x82,0xe4,0x34,0x04,0xf5,0x83,0xed,0xf0,0x80,0x29,0x74,0xa6,0x2f,0xf5,0x82, ++0xe4,0x34,0x9c,0xf5,0x83,0xed,0xf0,0x90,0x9e,0x75,0xef,0xf0,0x24,0xa6,0xf5,0x82, ++0xe4,0x34,0x9c,0xf5,0x83,0xe0,0x90,0x9e,0x76,0xf0,0x7b,0x01,0x7a,0x9e,0x79,0x75, ++0x7d,0x02,0x51,0xc9,0xd0,0xd0,0x92,0xaf,0x22,0xd3,0x10,0xaf,0x01,0xc3,0xc0,0xd0, ++0x90,0x9e,0x94,0x12,0x43,0x8b,0x90,0x9e,0x97,0xe0,0x54,0xf0,0x44,0x06,0xff,0xf0, ++0xed,0x54,0x0f,0xc4,0x54,0xf0,0xfe,0xef,0x54,0x0f,0x4e,0xf0,0x90,0x9e,0x94,0x12, ++0x43,0x6b,0x90,0x9e,0x91,0x12,0x43,0x8b,0x7b,0x01,0x7a,0x9e,0x79,0x97,0x71,0xd4, ++0xd0,0xd0,0x92,0xaf,0x22,0x8f,0x50,0x8d,0x51,0xe5,0x51,0x54,0x1f,0xf5,0x56,0x74, ++0x01,0x2f,0xf5,0x82,0xe4,0x34,0x94,0xf5,0x83,0xe0,0xf5,0x54,0x90,0x04,0xfd,0xe0, ++0xb4,0x01,0x05,0x75,0x57,0x03,0x80,0x03,0x75,0x57,0x01,0xeb,0xc3,0x95,0x57,0x40, ++0x04,0xaf,0x50,0x80,0x33,0xe5,0x54,0x25,0x53,0xf5,0x55,0xe5,0x56,0x90,0x41,0xd6, ++0x93,0xff,0xe5,0x55,0xd3,0x9f,0x74,0x01,0x40,0x11,0x25,0x50,0xf5,0x82,0xe4,0x34, ++0x94,0xf5,0x83,0xe4,0xf0,0xad,0x51,0xaf,0x50,0x41,0x80,0x25,0x50,0xf5,0x82,0xe4, ++0x34,0x94,0xf5,0x83,0xe5,0x55,0xf0,0x22,0xad,0x07,0x75,0xf0,0x09,0xed,0x90,0x96, ++0x48,0x12,0x43,0x5f,0xe0,0xff,0x74,0x67,0x2d,0xf5,0x82,0xe4,0x34,0x9d,0xf5,0x83, ++0xe0,0x54,0x1f,0xf5,0x58,0xd3,0x9f,0x40,0x02,0x8f,0x58,0xe5,0x58,0x25,0xe0,0x24, ++0x9e,0xf5,0x82,0xe4,0x34,0x41,0xf5,0x83,0xe4,0x93,0xfe,0x74,0x01,0x93,0xff,0xe5, ++0x58,0x25,0xe0,0x24,0x66,0xf5,0x82,0xe4,0x34,0x41,0xf5,0x83,0x74,0x01,0x93,0x2f, ++0xff,0xe4,0x93,0x3e,0xc3,0x13,0xfe,0xef,0x13,0xff,0xed,0x25,0xe0,0x24,0xc2,0xf5, ++0x82,0xe4,0x34,0x95,0xf5,0x83,0xee,0xf0,0xa3,0xef,0xf0,0xaf,0x05,0xad,0x58,0x51, ++0x80,0xaf,0x58,0x22,0xd3,0x10,0xaf,0x01,0xc3,0xc0,0xd0,0x90,0x9e,0x8e,0x12,0x43, ++0x8b,0x90,0x9e,0xaf,0xe0,0xff,0x04,0xf0,0x90,0x00,0x01,0xef,0x12,0x42,0x5f,0x7f, ++0xaf,0x7e,0x01,0x91,0x67,0xef,0x60,0x49,0x90,0x9e,0x8e,0x12,0x43,0x6b,0x8b,0x1e, ++0x8a,0x1f,0x89,0x20,0x75,0x21,0x02,0x7b,0x01,0x7a,0x01,0x79,0xa0,0x12,0x45,0x09, ++0x90,0x9e,0x91,0x12,0x43,0x6b,0x8b,0x1e,0x8a,0x1f,0x89,0x20,0x90,0x9e,0x8e,0x12, ++0x43,0x6b,0x12,0x24,0x62,0xff,0xc4,0x54,0x0f,0xf5,0x21,0x7b,0x01,0x7a,0x01,0x79, ++0xa2,0x12,0x45,0x09,0x90,0x01,0xaf,0x74,0xff,0xf0,0x90,0x01,0xcb,0xe0,0x64,0x80, ++0xf0,0xd0,0xd0,0x92,0xaf,0x22,0x90,0x9e,0x2f,0xe0,0x54,0xf0,0x44,0x03,0xf0,0x54, ++0x0f,0x44,0x80,0xf0,0x7b,0x00,0x7a,0x00,0x79,0x13,0x90,0x9e,0x91,0x12,0x43,0x8b, ++0x0b,0x7a,0x9e,0x79,0x2f,0x61,0xd4,0xd3,0x10,0xaf,0x01,0xc3,0xc0,0xd0,0x90,0x9e, ++0x9d,0xee,0xf0,0xa3,0xef,0xf0,0xe4,0xa3,0xf0,0xa3,0xf0,0x90,0x9e,0x9d,0xe0,0xfe, ++0xa3,0xe0,0xf5,0x82,0x8e,0x83,0xe0,0x60,0x2d,0xc3,0x90,0x9e,0xa0,0xe0,0x94,0xe8, ++0x90,0x9e,0x9f,0xe0,0x94,0x03,0x40,0x0b,0x90,0x01,0xc6,0xe0,0x44,0x10,0xf0,0x7f, ++0x00,0x80,0x15,0x90,0x9e,0x9f,0xe4,0x75,0xf0,0x01,0x12,0x42,0x81,0x7f,0x0a,0x7e, ++0x00,0x12,0x32,0x15,0x80,0xc5,0x7f,0x01,0xd0,0xd0,0x92,0xaf,0x22,0xac,0x07,0xec, ++0xc3,0x94,0x20,0x50,0x0d,0x74,0x84,0x2c,0xf5,0x82,0xe4,0x34,0x04,0xf5,0x83,0xe0, ++0x80,0x0b,0x74,0xa6,0x2c,0xf5,0x82,0xe4,0x34,0x9c,0xf5,0x83,0xe0,0x54,0x7f,0xf5, ++0x64,0xe5,0x64,0x54,0x1f,0xff,0x90,0x9e,0x40,0xf0,0x75,0xf0,0x09,0xec,0x90,0x96, ++0x49,0x12,0x43,0x5f,0xe0,0x90,0x9e,0x42,0xf0,0x75,0xf0,0x09,0xec,0x90,0x96,0x48, ++0x12,0x43,0x5f,0xe0,0xfe,0x90,0x9e,0x43,0xf0,0xec,0x25,0xe0,0x24,0xc6,0xf5,0x82, ++0xe4,0x34,0x9b,0xf5,0x83,0xe0,0xfb,0xa3,0xe0,0x90,0x9e,0x44,0xcb,0xf0,0xa3,0xeb, ++0xf0,0xec,0x25,0xe0,0x24,0x02,0xf5,0x82,0xe4,0x34,0x95,0xf5,0x83,0xe0,0xfb,0xa3, ++0xe0,0x90,0x9e,0x46,0xcb,0xf0,0xa3,0xeb,0xf0,0xef,0xd3,0x9e,0x40,0x0a,0x90,0x9e, ++0x43,0xe0,0x90,0x9e,0x40,0xf0,0xf5,0x64,0xed,0x70,0x02,0xc1,0x13,0x90,0x9e,0x41, ++0xed,0xf0,0xe5,0x64,0x30,0xe6,0x0a,0x90,0x9e,0x40,0xe0,0xf5,0x64,0xa3,0xe0,0x14, ++0xf0,0x90,0x9e,0x41,0xe0,0x70,0x02,0xc1,0x13,0x90,0x9e,0x40,0xe0,0xff,0xd3,0x94, ++0x00,0x50,0x02,0xc1,0x13,0xe4,0x90,0x9e,0x3f,0xf0,0xef,0x14,0x90,0x9e,0x3e,0xf0, ++0x90,0x9e,0x42,0xe0,0xfd,0x90,0x9e,0x3e,0xe0,0xff,0xd3,0x9d,0x40,0x6b,0xef,0x94, ++0x10,0x40,0x21,0xef,0x24,0xf0,0xff,0x74,0x01,0x7e,0x00,0xa8,0x07,0x08,0x80,0x05, ++0xc3,0x33,0xce,0x33,0xce,0xd8,0xf9,0xff,0x90,0x9e,0x46,0xe0,0x5e,0xfe,0xa3,0xe0, ++0x5f,0x4e,0x70,0x27,0x90,0x9e,0x3e,0xe0,0xff,0xc3,0x94,0x10,0x50,0x33,0x74,0x01, ++0x7e,0x00,0xa8,0x07,0x08,0x80,0x05,0xc3,0x33,0xce,0x33,0xce,0xd8,0xf9,0xff,0x90, ++0x9e,0x44,0xe0,0x5e,0xfe,0xa3,0xe0,0x5f,0x4e,0x60,0x16,0x90,0x9e,0x3e,0xe0,0xf5, ++0x64,0xa3,0xe0,0x04,0xf0,0x90,0x9e,0x41,0xe0,0xff,0x90,0x9e,0x3f,0xe0,0x6f,0x60, ++0x08,0x90,0x9e,0x3e,0xe0,0x14,0xf0,0x80,0x87,0x90,0x9e,0x41,0xe0,0xff,0x90,0x9e, ++0x3f,0xe0,0xc3,0x9f,0x50,0x0d,0x90,0x9e,0x3e,0xe0,0xb5,0x05,0x06,0x90,0x9e,0x42, ++0xe0,0xf5,0x64,0xe5,0x64,0x25,0xe0,0x24,0x9e,0xf5,0x82,0xe4,0x34,0x41,0xf5,0x83, ++0xe4,0x93,0xfe,0x74,0x01,0x93,0xff,0xe5,0x64,0x25,0xe0,0x24,0x66,0xf5,0x82,0xe4, ++0x34,0x41,0xf5,0x83,0x74,0x01,0x93,0x2f,0xff,0xe4,0x93,0x3e,0xc3,0x13,0xfe,0xef, ++0x13,0xff,0xec,0x25,0xe0,0x24,0xc2,0xf5,0x82,0xe4,0x34,0x95,0xf5,0x83,0xee,0xf0, ++0xa3,0xef,0xf0,0xaf,0x04,0xad,0x64,0x51,0x80,0xaf,0x64,0x22,0x8f,0x77,0x12,0x45, ++0xa6,0xef,0x64,0x01,0x70,0x2e,0x90,0x9e,0x52,0x12,0x47,0xcc,0xe5,0x77,0x60,0x10, ++0x74,0x21,0x2f,0xf5,0x82,0xe4,0x34,0xfc,0xf5,0x83,0xe0,0x44,0x10,0xf0,0x80,0x0e, ++0x74,0x21,0x2f,0xf5,0x82,0xe4,0x34,0xfc,0xf5,0x83,0xe0,0x54,0xef,0xf0,0x90,0x04, ++0x1f,0x74,0x20,0xf0,0x22,0x90,0x06,0x04,0xe0,0x54,0xbf,0xf0,0xef,0x60,0x09,0xe5, ++0x22,0xb4,0x01,0x04,0xe4,0xff,0xd1,0x5c,0x53,0x23,0xf0,0x43,0x23,0x0c,0x22,0x90, ++0x01,0x3c,0x74,0xff,0xf0,0xa3,0xf0,0xa3,0xf0,0x90,0x01,0x34,0xf0,0xa3,0xf0,0xa3, ++0xf0,0xa3,0xf0,0xfd,0x7f,0x54,0x12,0x4c,0xe3,0x7d,0xff,0x7f,0x55,0x12,0x4c,0xe3, ++0x7d,0xff,0x7f,0x56,0x12,0x4c,0xe3,0x7d,0xff,0x7f,0x57,0x02,0x4c,0xe3,0x90,0x00, ++0x02,0xe0,0x54,0xe0,0x7f,0x01,0x60,0x02,0x7f,0x00,0x22,0x90,0x00,0xf3,0xe0,0x7f, ++0x00,0x30,0xe3,0x03,0x7f,0x01,0x22,0x22,0x90,0x01,0x64,0x74,0xa0,0xf0,0x22,0xc0, ++0xe0,0xc0,0xf0,0xc0,0x83,0xc0,0x82,0xc0,0xd0,0x75,0xd0,0x00,0xc0,0x00,0xc0,0x01, ++0xc0,0x02,0xc0,0x03,0xc0,0x04,0xc0,0x05,0xc0,0x06,0xc0,0x07,0x90,0x01,0xc4,0x74, ++0xff,0xf0,0x74,0x5e,0xa3,0xf0,0x53,0x91,0xef,0x90,0x00,0x51,0xe0,0xff,0x90,0x00, ++0x55,0xe0,0x5f,0xf5,0x3d,0xe5,0x3d,0x30,0xe6,0x18,0x74,0x40,0xf0,0x90,0x9e,0x1d, ++0xe0,0x54,0x03,0xff,0xbf,0x03,0x0b,0x90,0x9e,0x1a,0xe0,0x60,0x05,0x7f,0x01,0x12, ++0x4c,0xf8,0xe5,0x3d,0x30,0xe7,0x15,0x90,0x00,0x55,0x74,0x80,0xf0,0x90,0x9e,0x1d, ++0xe0,0x54,0x03,0xff,0xbf,0x03,0x05,0x7f,0x02,0x12,0x4c,0xf8,0x90,0x01,0xc4,0x74, ++0xff,0xf0,0x74,0x5e,0xa3,0xf0,0xd0,0x07,0xd0,0x06,0xd0,0x05,0xd0,0x04,0xd0,0x03, ++0xd0,0x02,0xd0,0x01,0xd0,0x00,0xd0,0xd0,0xd0,0x82,0xd0,0x83,0xd0,0xf0,0xd0,0xe0, ++0x32,0x8f,0x6b,0x8c,0x6c,0x8d,0x6d,0x22,0x8f,0x6e,0x8c,0x6f,0x8d,0x70,0x22,0xe4, ++0xf5,0x22,0xf5,0x26,0xf5,0x25,0x75,0x24,0x0c,0x75,0x23,0x0c,0x90,0x9e,0x73,0xf0, ++0x90,0x9e,0x71,0xf0,0x90,0x9e,0x70,0xf0,0x90,0x9e,0x72,0x04,0xf0,0x90,0x9e,0x64, ++0xf0,0xe4,0x90,0x9e,0x74,0xf0,0x90,0x9e,0x66,0xf0,0x90,0x9e,0x6e,0x74,0x07,0xf0, ++0xe4,0x90,0x9e,0x65,0xf0,0x90,0x9e,0x6c,0xf0,0xa3,0x74,0x02,0xf0,0x90,0x9e,0x6a, ++0x14,0xf0,0xa3,0x74,0x03,0xf0,0x90,0x9e,0x69,0x74,0x14,0xf0,0x90,0x9e,0x6f,0x74, ++0x05,0xf0,0xe4,0x90,0x9e,0x68,0xf0,0x90,0x9e,0x63,0xf0,0x90,0x9e,0x5f,0xf0,0x22, ++0xe4,0x90,0x9e,0x74,0xf0,0x90,0x9e,0x65,0xf0,0xf5,0x26,0x22,0x8b,0x59,0x8a,0x5a, ++0x89,0x5b,0x11,0x00,0xab,0x59,0xaa,0x5a,0xa9,0x5b,0x12,0x24,0x62,0xf5,0x25,0x14, ++0x60,0x0e,0x14,0x60,0x1e,0x14,0x60,0x2f,0x24,0x03,0x70,0x40,0x7f,0x01,0x80,0x3a, ++0xab,0x59,0xaa,0x5a,0xa9,0x5b,0x90,0x00,0x02,0x12,0x42,0x20,0xfd,0xe4,0xff,0x11, ++0x6d,0x80,0x27,0xab,0x59,0xaa,0x5a,0xa9,0x5b,0x90,0x00,0x02,0x12,0x42,0x20,0xfd, ++0x7f,0x01,0x11,0x6d,0x1f,0x80,0x13,0xab,0x59,0xaa,0x5a,0xa9,0x5b,0x90,0x00,0x02, ++0x12,0x42,0x20,0xfd,0x7f,0x02,0x11,0x6d,0xe4,0xff,0x11,0x98,0x22,0xef,0x24,0xfe, ++0x60,0x0b,0x04,0x70,0x22,0x90,0x9e,0x72,0x74,0x01,0xf0,0x80,0x16,0xed,0x70,0x0a, ++0x90,0x9e,0x6f,0xe0,0x90,0x9e,0x72,0xf0,0x80,0x05,0x90,0x9e,0x72,0xed,0xf0,0x90, ++0x9e,0x72,0xe0,0x90,0x9e,0x64,0xf0,0x22,0xef,0x64,0x01,0x70,0x2f,0x7d,0x7c,0x7f, ++0x02,0x12,0x31,0x2c,0x7d,0x02,0x7f,0x03,0x12,0x31,0x2c,0x90,0x01,0x57,0xe4,0xf0, ++0x90,0x01,0x3c,0x74,0x02,0xf0,0x12,0x47,0x2b,0xe4,0xff,0x31,0x1f,0x90,0x06,0x04, ++0xe0,0x54,0x7f,0xf0,0x90,0x06,0x0a,0xe0,0x54,0xf8,0xf0,0x22,0x90,0x01,0x36,0x74, ++0x7c,0xf0,0xa3,0x74,0x02,0xf0,0x7d,0x7c,0xff,0x12,0x31,0x9d,0x7d,0x02,0x7f,0x03, ++0x12,0x31,0x9d,0x90,0x06,0x04,0xe0,0x44,0x80,0xf0,0x90,0x06,0x0a,0xe0,0x44,0x07, ++0xf0,0x90,0x9e,0x6c,0xe0,0xa3,0xe0,0x90,0x05,0x58,0xf0,0xe5,0x22,0x30,0xe0,0x19, ++0x90,0x9e,0x66,0xe0,0x70,0x18,0xe0,0x04,0xf0,0xe5,0x23,0x54,0x0f,0xc3,0x94,0x04, ++0x50,0x0c,0x7d,0x01,0x7f,0x04,0x02,0x47,0x2f,0xe4,0x90,0x9e,0x66,0xf0,0x22,0xef, ++0x60,0x0b,0x90,0x9e,0x60,0xe0,0xb4,0x01,0x10,0xe4,0xff,0x80,0x09,0x90,0x9e,0x60, ++0xe0,0xb4,0x01,0x05,0x7f,0x01,0x12,0x77,0xe4,0x22,0x90,0x01,0x37,0x74,0x02,0xf0, ++0x90,0x05,0x22,0x74,0xff,0xf0,0x31,0xc3,0xef,0x70,0x06,0x90,0x01,0xc8,0x74,0xfd, ++0xf0,0x7d,0x02,0x7f,0x03,0x12,0x31,0x9d,0xe5,0x25,0x60,0x04,0x7f,0x01,0x31,0x1f, ++0x51,0x04,0x53,0x23,0xf0,0x43,0x23,0x02,0x22,0xd3,0x10,0xaf,0x01,0xc3,0xc0,0xd0, ++0x90,0x00,0x01,0x12,0x42,0x20,0x90,0x9e,0x73,0xf0,0x90,0x00,0x03,0x12,0x42,0x20, ++0x90,0x9e,0x63,0xf0,0x12,0x24,0x62,0x65,0x25,0x60,0x02,0x11,0x0c,0xd0,0xd0,0x92, ++0xaf,0x22,0x7d,0x02,0x7f,0x03,0x12,0x31,0x2c,0xe5,0x25,0x14,0x24,0xfd,0x50,0x02, ++0x80,0x20,0x90,0x9e,0x73,0xe0,0x60,0x06,0x7d,0x01,0x7f,0x0c,0x80,0x0d,0xe5,0x23, ++0x54,0x0f,0xc3,0x94,0x04,0x50,0x07,0x7d,0x01,0x7f,0x04,0x12,0x47,0x2f,0xe4,0xff, ++0x31,0x1f,0x22,0xe4,0x90,0x9e,0xa9,0xf0,0xa3,0xf0,0x90,0x05,0xf8,0xe0,0x70,0x0f, ++0xa3,0xe0,0x70,0x0b,0xa3,0xe0,0x70,0x07,0xa3,0xe0,0x70,0x03,0x7f,0x01,0x22,0xd3, ++0x90,0x9e,0xaa,0xe0,0x94,0xe8,0x90,0x9e,0xa9,0xe0,0x94,0x03,0x40,0x03,0x7f,0x00, ++0x22,0x7f,0x32,0x7e,0x00,0x12,0x32,0x15,0x90,0x9e,0xa9,0xe4,0x75,0xf0,0x01,0x12, ++0x42,0x81,0x80,0xc6,0x7f,0x78,0x7e,0x08,0x12,0x22,0x65,0x90,0x9d,0xff,0x12,0x25, ++0x08,0x7f,0x04,0x7e,0x0c,0x12,0x22,0x65,0x90,0x9e,0x03,0x12,0x25,0x08,0x7f,0x00, ++0x7e,0x08,0x12,0x22,0x65,0x90,0x9e,0x07,0x12,0x25,0x08,0x90,0x9e,0x60,0xe0,0x90, ++0x9d,0xff,0xb4,0x01,0x0d,0x12,0x43,0x53,0xef,0x54,0xc7,0xff,0xed,0x54,0xc7,0xfd, ++0x80,0x07,0x12,0x43,0x53,0xef,0x54,0xc7,0xff,0xec,0x90,0x80,0x96,0x12,0x25,0x08, ++0x7f,0x78,0x7e,0x08,0x12,0x2b,0x08,0x90,0x9e,0x03,0x12,0x43,0x53,0xef,0x54,0x0f, ++0xff,0xec,0x90,0x80,0x96,0x12,0x25,0x08,0x7f,0x04,0x7e,0x0c,0x12,0x2b,0x08,0x90, ++0x9e,0x07,0x12,0x43,0x53,0xef,0x44,0x02,0xff,0xec,0x90,0x80,0x96,0x12,0x25,0x08, ++0x7f,0x00,0x7e,0x08,0x12,0x2b,0x08,0x7f,0x70,0x7e,0x0e,0x12,0x22,0x65,0x90,0x9e, ++0x0b,0x12,0x25,0x08,0x90,0x80,0x96,0x12,0x25,0x14,0x00,0x1b,0x25,0xa0,0x7f,0x70, ++0x7e,0x0e,0x12,0x2b,0x08,0x90,0x80,0x68,0x12,0x25,0x14,0x00,0x00,0x00,0x00,0xe4, ++0xfd,0xff,0x12,0x30,0x2c,0x90,0x9e,0x60,0xe0,0xb4,0x01,0x11,0x90,0x80,0x68,0x12, ++0x25,0x14,0x00,0x00,0x00,0x00,0xe4,0xfd,0x7f,0x01,0x12,0x30,0x2c,0x90,0x00,0x11, ++0xe0,0x54,0xf6,0xf0,0x02,0x4b,0xdb,0x12,0x4b,0xc4,0xef,0x64,0x01,0x60,0x08,0x90, ++0x01,0xb9,0x74,0x01,0xf0,0x80,0x30,0x90,0x9e,0x71,0xe0,0x60,0x08,0x90,0x01,0xb9, ++0x74,0x02,0xf0,0x80,0x22,0x90,0x9e,0x70,0xe0,0x60,0x08,0x90,0x01,0xb9,0x74,0x04, ++0xf0,0x80,0x14,0xe5,0x24,0x54,0x0f,0xd3,0x94,0x04,0x40,0x08,0x90,0x01,0xb9,0x74, ++0x08,0xf0,0x80,0x03,0x7f,0x01,0x22,0x90,0x01,0xb8,0x74,0x08,0xf0,0x7f,0x00,0x22, ++0x12,0x4b,0xc4,0xef,0x64,0x01,0x60,0x08,0x90,0x01,0xb9,0x74,0x01,0xf0,0x80,0x4a, ++0xe5,0x26,0x54,0x03,0x60,0x08,0x90,0x01,0xb9,0x74,0x02,0xf0,0x80,0x3c,0xe5,0x24, ++0x54,0x0f,0xd3,0x94,0x02,0x40,0x08,0x90,0x01,0xb9,0x74,0x04,0xf0,0x80,0x2b,0xe5, ++0x26,0x30,0xe2,0x08,0x90,0x01,0xb9,0x74,0x08,0xf0,0x80,0x1e,0xe5,0x26,0x30,0xe4, ++0x08,0x90,0x01,0xb9,0x74,0x10,0xf0,0x80,0x11,0x90,0x9e,0x66,0xe0,0x60,0x08,0x90, ++0x01,0xb9,0x74,0x20,0xf0,0x80,0x03,0x7f,0x01,0x22,0x90,0x01,0xb8,0x74,0x04,0xf0, ++0x7f,0x00,0x22,0xe5,0x12,0x60,0x08,0x90,0x01,0xb9,0x74,0x01,0xf0,0x80,0x5b,0xe5, ++0x24,0x54,0x0f,0xd3,0x94,0x01,0x40,0x08,0x90,0x01,0xb9,0x74,0x02,0xf0,0x80,0x4a, ++0x90,0x02,0x87,0xe0,0x60,0x08,0x90,0x01,0xb9,0x74,0x04,0xf0,0x80,0x3c,0x90,0x9e, ++0x5e,0xe0,0xb4,0x01,0x10,0x90,0x9e,0x4d,0xe0,0xfe,0xa3,0xe0,0xf5,0x82,0x8e,0x83, ++0xe0,0x60,0x16,0x80,0x25,0x90,0x9e,0x5e,0xe0,0x70,0x0e,0x90,0x01,0xaf,0xe0,0x60, ++0x08,0x90,0x01,0xb9,0x74,0x08,0xf0,0x80,0x11,0x90,0x9e,0x68,0xe0,0x70,0x08,0x90, ++0x01,0xb9,0x74,0x10,0xf0,0x80,0x03,0x7f,0x01,0x22,0x90,0x01,0xb8,0x74,0x02,0xf0, ++0x7f,0x00,0x22,0x90,0x9e,0xae,0xef,0xf0,0x91,0x0c,0x90,0x9e,0xae,0xe0,0x60,0x05, ++0x90,0x05,0x22,0xe4,0xf0,0x53,0x23,0xf0,0x43,0x23,0x04,0x22,0x90,0x00,0x11,0xe0, ++0x44,0x09,0xf0,0x12,0x4b,0xdb,0x90,0x9d,0xff,0x12,0x43,0x53,0x90,0x80,0x96,0x12, ++0x25,0x08,0x7f,0x78,0x7e,0x08,0x12,0x2b,0x08,0x90,0x9e,0x03,0x12,0x43,0x53,0x90, ++0x80,0x96,0x12,0x25,0x08,0x7f,0x04,0x7e,0x0c,0x12,0x2b,0x08,0x90,0x9e,0x07,0x12, ++0x43,0x53,0x90,0x80,0x96,0x12,0x25,0x08,0x7f,0x00,0x7e,0x08,0x12,0x2b,0x08,0x90, ++0x9e,0x0b,0x12,0x43,0x53,0x90,0x80,0x96,0x12,0x25,0x08,0x7f,0x70,0x7e,0x0e,0x12, ++0x2b,0x08,0x90,0x80,0x68,0x12,0x25,0x14,0x00,0x03,0x2d,0x95,0xe4,0xfd,0xff,0x12, ++0x30,0x2c,0x90,0x9e,0x60,0xe0,0xb4,0x01,0x11,0x90,0x80,0x68,0x12,0x25,0x14,0x00, ++0x03,0x2d,0x95,0xe4,0xfd,0x7f,0x01,0x12,0x30,0x2c,0x22,0x8f,0x27,0xe4,0x90,0x9e, ++0xa7,0xf0,0xa3,0xf0,0x90,0x01,0x09,0xe0,0x7f,0x00,0x30,0xe7,0x02,0x7f,0x01,0xef, ++0x65,0x27,0x60,0x3e,0xc3,0x90,0x9e,0xa8,0xe0,0x94,0x88,0x90,0x9e,0xa7,0xe0,0x94, ++0x13,0x40,0x08,0x90,0x01,0xc6,0xe0,0x44,0x80,0xf0,0x22,0x90,0x9e,0xa7,0xe4,0x75, ++0xf0,0x01,0x12,0x42,0x81,0x7f,0x14,0x7e,0x00,0x12,0x32,0x15,0xd3,0x90,0x9e,0xa8, ++0xe0,0x94,0x32,0x90,0x9e,0xa7,0xe0,0x94,0x00,0x40,0xb9,0x90,0x01,0xc7,0xe0,0x30, ++0xe0,0xb2,0x22,0xe5,0x24,0x30,0xe6,0x19,0xe5,0x24,0x54,0x0f,0xff,0x90,0x9e,0x62, ++0xe0,0xfe,0x4f,0x90,0x01,0x2f,0xf0,0xee,0x64,0x80,0x90,0x9e,0x62,0xf0,0x53,0x24, ++0xbf,0x22,0x8f,0x76,0x12,0x45,0xa6,0xef,0x64,0x01,0x70,0x2e,0x90,0x9e,0x53,0x12, ++0x47,0xcc,0xe5,0x76,0x60,0x10,0x74,0x21,0x2f,0xf5,0x82,0xe4,0x34,0xfc,0xf5,0x83, ++0xe0,0x44,0x10,0xf0,0x80,0x0e,0x74,0x21,0x2f,0xf5,0x82,0xe4,0x34,0xfc,0xf5,0x83, ++0xe0,0x54,0xef,0xf0,0x90,0x04,0x1f,0x74,0x20,0xf0,0x22,0xe5,0x22,0x64,0x01,0x70, ++0x61,0xe5,0x25,0x60,0x5d,0xe5,0x25,0x64,0x02,0x60,0x06,0xe5,0x25,0x64,0x05,0x70, ++0x27,0x90,0x06,0xab,0xe0,0x90,0x9e,0x64,0xf0,0x90,0x06,0xaa,0xe0,0x90,0x9e,0x72, ++0xf0,0x90,0x9e,0x64,0xe0,0x70,0x07,0x90,0x9e,0x72,0xe0,0xff,0x80,0x05,0x90,0x9e, ++0x64,0xe0,0xff,0x90,0x9e,0x64,0xef,0xf0,0x90,0x9e,0x66,0xe0,0x60,0x03,0xe0,0x14, ++0xf0,0xe4,0x90,0x9e,0x65,0xf0,0x90,0x01,0x57,0xf0,0x90,0x01,0x3c,0x74,0x02,0xf0, ++0x53,0x26,0xfd,0x53,0x26,0xef,0xe5,0x25,0x14,0x24,0xfd,0x50,0x02,0x80,0x03,0x12, ++0x45,0x53,0x22,0xe4,0xff,0xe5,0x25,0x60,0x5f,0xe5,0x22,0x64,0x01,0x70,0x59,0xe5, ++0x25,0x14,0x60,0x2b,0x24,0xfd,0x60,0x27,0x24,0x02,0x24,0xfb,0x50,0x02,0x80,0x21, ++0x90,0x9e,0x64,0xe0,0x14,0xf0,0xe0,0x60,0x04,0xa3,0xe0,0x60,0x14,0x90,0x9e,0x64, ++0xe0,0x70,0x08,0x90,0x9e,0x72,0xe0,0x90,0x9e,0x64,0xf0,0x7f,0x01,0x80,0x02,0x7f, ++0x01,0xef,0x60,0x24,0x43,0x26,0x10,0xe4,0x90,0x9e,0x86,0xf0,0x90,0x9e,0x6e,0x12, ++0x44,0x56,0x90,0x01,0x57,0x74,0x05,0xf0,0xe5,0x23,0x54,0x0f,0xc3,0x94,0x04,0x50, ++0x07,0x7d,0x01,0x7f,0x04,0x12,0x47,0x2f,0x22,0xe5,0x25,0x60,0x39,0x90,0x9e,0x74, ++0xe0,0x60,0x0d,0xe4,0xf0,0x53,0x26,0xfd,0xe5,0x26,0x54,0x07,0x70,0x28,0x80,0x23, ++0x90,0x9e,0x65,0xe0,0x04,0xf0,0x53,0x26,0xef,0x90,0x9e,0x6a,0xe0,0xff,0x90,0x9e, ++0x65,0xe0,0xd3,0x9f,0x40,0x0d,0xe5,0x22,0xb4,0x01,0x0b,0xa3,0xe0,0x70,0x07,0xe0, ++0x04,0xf0,0x22,0x12,0x44,0xd1,0x22,0xef,0xc3,0x94,0x20,0x50,0x39,0xef,0x30,0xe0, ++0x17,0xed,0xc4,0x54,0xf0,0xfd,0xef,0xc3,0x13,0xfe,0x24,0xa4,0xf5,0x82,0xe4,0x34, ++0x04,0xf5,0x83,0xe0,0x54,0x0f,0x80,0x10,0xef,0xc3,0x13,0xfe,0x24,0xa4,0xf5,0x82, ++0xe4,0x34,0x04,0xf5,0x83,0xe0,0x54,0xf0,0xf0,0x74,0xa4,0x2e,0xf5,0x82,0xe4,0x34, ++0x04,0xf5,0x83,0xe0,0x4d,0xf0,0x22,0xad,0x07,0xed,0xc3,0x94,0x20,0x50,0x0d,0x74, ++0x84,0x2d,0xf5,0x82,0xe4,0x34,0x04,0xf5,0x83,0xe0,0x80,0x0b,0x74,0xa6,0x2d,0xf5, ++0x82,0xe4,0x34,0x9c,0xf5,0x83,0xe0,0x54,0x7f,0xf5,0x64,0xe5,0x64,0x54,0x1f,0xfc, ++0x75,0xf0,0x09,0xed,0x90,0x96,0x48,0x12,0x43,0x5f,0xe0,0xff,0x90,0x9e,0x3e,0xf0, ++0xed,0x25,0xe0,0x24,0x02,0xf5,0x82,0xe4,0x34,0x95,0xf5,0x83,0xe0,0xfb,0xa3,0xe0, ++0x90,0x9e,0x3f,0xcb,0xf0,0xa3,0xeb,0xf0,0xed,0x25,0xe0,0x24,0xc6,0xf5,0x82,0xe4, ++0x34,0x9b,0xf5,0x83,0xe0,0xfb,0xa3,0xe0,0x90,0x9e,0x41,0xcb,0xf0,0xa3,0xeb,0xf0, ++0xec,0x25,0xe0,0x24,0x66,0xf5,0x82,0xe4,0x34,0x41,0xf5,0x83,0xe4,0x93,0xfa,0x74, ++0x01,0x93,0xfb,0xed,0x25,0xe0,0x24,0xc2,0xf5,0x82,0xe4,0x34,0x95,0xf5,0x83,0xea, ++0xf0,0xa3,0xeb,0xf0,0xec,0xc3,0x9f,0x40,0x02,0xe1,0xa5,0x74,0x67,0x2d,0xf5,0x82, ++0xe4,0x34,0x9d,0xf5,0x83,0xec,0xf0,0x04,0xfb,0x90,0x9e,0x3e,0xe0,0xff,0xeb,0xd3, ++0x9f,0x40,0x02,0xe1,0xd6,0xeb,0xc3,0x94,0x10,0x40,0x21,0xeb,0x24,0xf0,0xff,0x74, ++0x01,0x7e,0x00,0xa8,0x07,0x08,0x80,0x05,0xc3,0x33,0xce,0x33,0xce,0xd8,0xf9,0xff, ++0x90,0x9e,0x3f,0xe0,0x5e,0xfe,0xa3,0xe0,0x5f,0x4e,0x70,0x23,0xeb,0xc3,0x94,0x10, ++0x50,0x40,0x74,0x01,0x7e,0x00,0xa8,0x03,0x08,0x80,0x05,0xc3,0x33,0xce,0x33,0xce, ++0xd8,0xf9,0xff,0x90,0x9e,0x41,0xe0,0x5e,0xfe,0xa3,0xe0,0x5f,0x4e,0x60,0x23,0xbb, ++0x11,0x09,0x90,0x9e,0x40,0xe0,0x30,0xe7,0x02,0x7b,0x17,0xeb,0x64,0x13,0x60,0x03, ++0xbb,0x12,0x09,0x90,0x9e,0x3f,0xe0,0x30,0xe0,0x02,0x7b,0x18,0xac,0x03,0x8c,0x64, ++0x80,0x34,0x0b,0x80,0x84,0x90,0x9e,0x3e,0xe0,0xfb,0x6c,0x70,0x69,0x74,0x67,0x2d, ++0xf5,0x82,0xe4,0x34,0x9d,0xf5,0x83,0xec,0xf0,0x75,0xf0,0x09,0xed,0x90,0x96,0x4a, ++0x12,0x43,0x5f,0xe0,0xb4,0x01,0x0c,0xe5,0x64,0x20,0xe6,0x07,0xec,0x44,0x40,0xf5, ++0x64,0x80,0x03,0xaf,0x64,0x22,0xec,0x25,0xe0,0x24,0x9e,0xf5,0x82,0xe4,0x34,0x41, ++0xf5,0x83,0xe4,0x93,0xfe,0x74,0x01,0x93,0xff,0xec,0x25,0xe0,0x24,0x66,0xf5,0x82, ++0xe4,0x34,0x41,0xf5,0x83,0x74,0x01,0x93,0x2f,0xff,0xe4,0x93,0x3e,0xc3,0x13,0xfe, ++0xef,0x13,0xff,0xed,0x25,0xe0,0x24,0xc2,0xf5,0x82,0xe4,0x34,0x95,0xf5,0x83,0xee, ++0xf0,0xa3,0xef,0xf0,0x80,0x5b,0xec,0xd3,0x9b,0x40,0x56,0x90,0x9e,0x3e,0xe0,0xff, ++0x74,0x67,0x2d,0xf5,0x82,0xe4,0x34,0x9d,0xf5,0x83,0xef,0xf0,0xac,0x07,0x8f,0x64, ++0xec,0x25,0xe0,0x24,0x9e,0xf5,0x82,0xe4,0x34,0x41,0xf5,0x83,0xe4,0x93,0xfe,0x74, ++0x01,0x93,0xff,0xec,0x25,0xe0,0x24,0x66,0xf5,0x82,0xe4,0x34,0x41,0xf5,0x83,0x74, ++0x01,0x93,0x2f,0xff,0xe4,0x93,0x3e,0xc3,0x13,0xfe,0xef,0x13,0xff,0xed,0x25,0xe0, ++0x24,0xc2,0xf5,0x82,0xe4,0x34,0x95,0xf5,0x83,0xee,0xf0,0xa3,0xef,0xf0,0xaf,0x64, ++0x22,0x74,0x01,0x2d,0xf5,0x82,0xe4,0x34,0x94,0xf5,0x83,0xe4,0xf0,0xaf,0x05,0xe5, ++0x64,0x44,0x80,0xfd,0x12,0x5a,0x80,0xe5,0x64,0x44,0x80,0xff,0x22,0xe4,0xf5,0x59, ++0xe5,0x59,0xb4,0x20,0x14,0x90,0x9a,0xc5,0xe0,0x04,0xf0,0x90,0x95,0x01,0xe0,0xff, ++0x90,0x9a,0xc5,0xe0,0xb5,0x07,0x02,0xe4,0xf0,0x75,0xf0,0x09,0xe5,0x59,0x90,0x96, ++0x4b,0x12,0x43,0x5f,0xe0,0x64,0x01,0x60,0x02,0xc1,0xd3,0xe5,0x59,0x25,0xe0,0x24, ++0x80,0xf5,0x82,0xe4,0x34,0x93,0xf5,0x83,0xe0,0xfe,0xa3,0xe0,0xd3,0x94,0x00,0xee, ++0x94,0x00,0x50,0x02,0xc1,0xd3,0xe5,0x59,0x94,0x20,0x40,0x08,0x90,0x9a,0xc5,0xe0, ++0x60,0x02,0xc1,0xde,0xe5,0x59,0x75,0xf0,0x0a,0xa4,0x24,0x00,0xf9,0x74,0x90,0x35, ++0xf0,0x75,0x5e,0x01,0xf5,0x5f,0x89,0x60,0xe5,0x59,0x25,0xe0,0x24,0x80,0xf5,0x82, ++0xe4,0x34,0x93,0xf5,0x83,0xe0,0xff,0xa3,0xe0,0x90,0x9e,0x38,0xcf,0xf0,0xa3,0xef, ++0xf0,0xe5,0x59,0x25,0xe0,0x24,0xc4,0xf5,0x82,0xe4,0x34,0x98,0xf5,0x83,0xe0,0xff, ++0xa3,0xe0,0x90,0x9e,0x3a,0xcf,0xf0,0xa3,0xef,0xf0,0xe5,0x59,0xc3,0x94,0x20,0x50, ++0x14,0x74,0x84,0x25,0x59,0xf5,0x82,0xe4,0x34,0x04,0xf5,0x83,0xe0,0x54,0x3f,0x90, ++0x9e,0x34,0xf0,0x80,0x12,0x74,0xa6,0x25,0x59,0xf5,0x82,0xe4,0x34,0x9c,0xf5,0x83, ++0xe0,0x54,0x3f,0x90,0x9e,0x34,0xf0,0x90,0x9e,0x34,0xe0,0xfe,0x54,0x1f,0xa3,0xf0, ++0x75,0xf0,0x09,0xe5,0x59,0x90,0x96,0x48,0x12,0x43,0x5f,0xe0,0x90,0x9e,0x3d,0xf0, ++0x74,0xe6,0x25,0x59,0xf5,0x82,0xe4,0x34,0x9c,0xf5,0x83,0xe0,0xc3,0x94,0x05,0x40, ++0x02,0x61,0xac,0x90,0x9e,0x3d,0xe0,0xff,0x90,0x9e,0x35,0xe0,0x9f,0x40,0x13,0x90, ++0x9e,0x3d,0xe0,0x90,0x9e,0x35,0xf0,0xee,0x54,0x40,0xfe,0x90,0x9e,0x34,0xf0,0xef, ++0x4e,0xf0,0x90,0x04,0xfd,0xe0,0x54,0x05,0x64,0x01,0x70,0x29,0x90,0x9e,0x35,0xe0, ++0xff,0x90,0x41,0x4a,0x93,0xfe,0x74,0x44,0x25,0x59,0xf5,0x82,0xe4,0x34,0x9a,0xf5, ++0x83,0xe0,0xc3,0x9e,0x40,0x06,0xef,0x90,0x40,0xda,0x80,0x30,0x90,0x9e,0x35,0xe0, ++0x90,0x40,0xf6,0x80,0x27,0x90,0x9e,0x35,0xe0,0xff,0x90,0x41,0x4a,0x93,0xfe,0x74, ++0x44,0x25,0x59,0xf5,0x82,0xe4,0x34,0x9a,0xf5,0x83,0xe0,0xc3,0x9e,0x40,0x06,0xef, ++0x90,0x41,0x12,0x80,0x07,0x90,0x9e,0x35,0xe0,0x90,0x41,0x2e,0x93,0x90,0x9e,0x3c, ++0xf0,0x90,0x9e,0x3c,0xe0,0x75,0xf0,0x06,0xa4,0x24,0x50,0xf9,0x74,0x40,0x35,0xf0, ++0x75,0x5b,0xff,0xf5,0x5c,0x89,0x5d,0x90,0x9e,0x34,0xe0,0x90,0x41,0xf2,0x93,0xff, ++0xd3,0x90,0x9e,0x3b,0xe0,0x9f,0x90,0x9e,0x3a,0xe0,0x94,0x00,0x40,0x09,0xe4,0xfd, ++0xaf,0x59,0x12,0x5c,0xbd,0xc1,0x6a,0xe5,0x59,0x25,0xe0,0x24,0xc2,0xf5,0x82,0xe4, ++0x34,0x95,0xf5,0x83,0xe0,0xf5,0x61,0xa3,0xe0,0xf5,0x62,0xab,0x5b,0xaa,0x5c,0xa9, ++0x5d,0x12,0x24,0x62,0xff,0x7e,0x00,0xab,0x5e,0xaa,0x5f,0xa9,0x60,0x12,0x42,0x97, ++0xfd,0xac,0xf0,0x12,0x24,0x7b,0xef,0x25,0x62,0xf5,0x62,0xee,0x35,0x61,0xf5,0x61, ++0xab,0x5b,0xaa,0x5c,0xa9,0x5d,0x90,0x00,0x01,0x12,0x42,0x20,0xff,0x7e,0x00,0xab, ++0x5e,0xaa,0x5f,0xa9,0x60,0x90,0x00,0x02,0x12,0x42,0xc2,0xfd,0xac,0xf0,0x12,0x24, ++0x7b,0xef,0x25,0x62,0xf5,0x62,0xee,0x35,0x61,0xf5,0x61,0xab,0x5b,0xaa,0x5c,0xa9, ++0x5d,0x90,0x00,0x02,0x12,0x42,0x20,0xff,0x7e,0x00,0xab,0x5e,0xaa,0x5f,0xa9,0x60, ++0x90,0x00,0x04,0x12,0x42,0xc2,0xfd,0xac,0xf0,0x12,0x24,0x7b,0xef,0x25,0x62,0xf5, ++0x62,0xee,0x35,0x61,0xf5,0x61,0xab,0x5b,0xaa,0x5c,0xa9,0x5d,0x90,0x00,0x03,0x12, ++0x42,0x20,0xff,0x7e,0x00,0xab,0x5e,0xaa,0x5f,0xa9,0x60,0x90,0x00,0x06,0x12,0x42, ++0xc2,0xfd,0xac,0xf0,0x12,0x24,0x7b,0xef,0x25,0x62,0xf5,0x62,0xee,0x35,0x61,0xf5, ++0x61,0xab,0x5b,0xaa,0x5c,0xa9,0x5d,0x90,0x00,0x04,0x12,0x42,0x20,0xff,0x7e,0x00, ++0xab,0x5e,0xaa,0x5f,0xa9,0x60,0x90,0x00,0x08,0x12,0x42,0xc2,0xfd,0xac,0xf0,0x12, ++0x24,0x7b,0xef,0x25,0x62,0xf5,0x62,0xee,0x35,0x61,0xf5,0x61,0xab,0x5b,0xaa,0x5c, ++0xa9,0x5d,0x90,0x00,0x05,0x12,0x42,0x20,0xff,0x7e,0x00,0x90,0x9e,0x38,0xe0,0xfc, ++0xa3,0xe0,0xfd,0x12,0x24,0x7b,0xd3,0xe5,0x62,0x9f,0xe5,0x61,0x9e,0x40,0x0c,0xe5, ++0x62,0x9f,0xf5,0x62,0xe5,0x61,0x9e,0xf5,0x61,0x80,0x05,0xe4,0xf5,0x61,0xf5,0x62, ++0xe5,0x59,0x25,0xe0,0x24,0xc2,0xf5,0x82,0xe4,0x34,0x95,0xf5,0x83,0xe5,0x61,0xf0, ++0xa3,0xe5,0x62,0xf0,0x90,0x9e,0x34,0xe0,0x25,0xe0,0x24,0x66,0xf5,0x82,0xe4,0x34, ++0x41,0xf5,0x83,0xc3,0x74,0x01,0x93,0x95,0x62,0xe4,0x93,0x95,0x61,0x50,0x07,0xaf, ++0x59,0x12,0x66,0x87,0xc1,0x3e,0x90,0x9e,0x34,0xe0,0x25,0xe0,0x24,0x9e,0xf5,0x82, ++0xe4,0x34,0x41,0xf5,0x83,0xd3,0x74,0x01,0x93,0x95,0x62,0xe4,0x93,0x95,0x61,0x50, ++0x02,0xc1,0x3e,0x7d,0x01,0xaf,0x59,0x12,0x5c,0xbd,0xc1,0x3e,0x74,0xe6,0x25,0x59, ++0xf5,0x82,0xe4,0x34,0x9c,0xf5,0x83,0xe0,0xfc,0x64,0x05,0x60,0x02,0xa1,0x47,0x90, ++0x96,0x43,0xe0,0xff,0xb4,0x03,0x0b,0x90,0x9e,0x35,0xe0,0xc3,0x94,0x19,0x40,0x3d, ++0x80,0x2e,0xef,0xb4,0x02,0x0b,0x90,0x9e,0x35,0xe0,0xc3,0x94,0x11,0x40,0x2e,0x80, ++0x1f,0x90,0x96,0x43,0xe0,0xff,0xb4,0x01,0x0b,0x90,0x9e,0x35,0xe0,0xc3,0x94,0x0a, ++0x40,0x1b,0x80,0x0c,0xef,0x70,0x11,0x90,0x9e,0x35,0xe0,0xc3,0x94,0x03,0x40,0x0d, ++0x90,0x9a,0x84,0x74,0x01,0xf0,0x80,0x05,0xe4,0x90,0x9a,0x84,0xf0,0x74,0x84,0x25, ++0x59,0xf5,0x82,0xe4,0x34,0x98,0xf5,0x83,0xe0,0xf5,0x63,0x74,0x44,0x25,0x59,0xf5, ++0x82,0xe4,0x34,0x9a,0xf5,0x83,0xe0,0xff,0xc3,0x94,0x30,0x50,0x02,0x81,0xf4,0x90, ++0x9a,0x84,0xe0,0x64,0x01,0x60,0x02,0x81,0xf4,0x74,0x85,0x25,0x59,0xf5,0x82,0xe4, ++0x34,0x9a,0xf5,0x83,0xe0,0x64,0x0a,0x60,0x51,0xef,0x24,0x05,0xff,0xe4,0x33,0xfe, ++0x74,0x41,0x25,0x59,0xf5,0x82,0xe4,0x34,0x94,0xf5,0x83,0xe0,0xfd,0xd3,0x9f,0xee, ++0x64,0x80,0xf8,0x74,0x80,0x98,0x50,0x32,0xed,0x24,0x05,0xff,0xe4,0x33,0xfe,0x74, ++0x44,0x25,0x59,0xf5,0x82,0xe4,0x34,0x9a,0xf5,0x83,0xe0,0xd3,0x9f,0xee,0x64,0x80, ++0xf8,0x74,0x80,0x98,0x50,0x14,0x74,0x26,0x25,0x59,0xf5,0x82,0xe4,0x34,0x9d,0xf5, ++0x83,0xe0,0xff,0x90,0x9e,0x35,0xe0,0x6f,0x60,0x3d,0x74,0x44,0x25,0x59,0xf5,0x82, ++0xe4,0x34,0x9a,0xf5,0x83,0xe0,0xff,0xd3,0x94,0x42,0x40,0x05,0x75,0x63,0x05,0x80, ++0x0e,0xef,0xd3,0x94,0x39,0x40,0x05,0x75,0x63,0x03,0x80,0x03,0x75,0x63,0x01,0x74, ++0x41,0x25,0x59,0xf5,0x82,0xe4,0x34,0x94,0xf5,0x83,0xef,0xf0,0x74,0x85,0x25,0x59, ++0xf5,0x82,0xe4,0x34,0x9a,0x80,0x29,0x74,0xe6,0x25,0x59,0xf5,0x82,0xe4,0x34,0x9c, ++0xf5,0x83,0xe4,0xf0,0x74,0x85,0x25,0x59,0xf5,0x82,0xe4,0x34,0x9a,0xf5,0x83,0xe0, ++0x04,0xf0,0x80,0x10,0xe4,0xf5,0x63,0x74,0xe6,0x25,0x59,0xf5,0x82,0xe4,0x34,0x9c, ++0xf5,0x83,0xe4,0xf0,0x90,0x9e,0x35,0xe0,0xff,0x74,0x26,0x25,0x59,0xf5,0x82,0xe4, ++0x34,0x9d,0xf5,0x83,0xef,0xf0,0x74,0x84,0x25,0x59,0xf5,0x82,0xe4,0x34,0x98,0xf5, ++0x83,0xe5,0x63,0xf0,0x75,0xf0,0x09,0xe5,0x59,0x90,0x96,0x4c,0x12,0x43,0x5f,0xe0, ++0xb4,0x01,0x10,0xe4,0xf5,0x63,0x74,0xe6,0x25,0x59,0xf5,0x82,0xe4,0x34,0x9c,0xf5, ++0x83,0xe4,0xf0,0xad,0x63,0xc1,0x39,0xec,0x64,0x06,0x60,0x02,0xc1,0x3e,0xf5,0x61, ++0xf5,0x62,0x90,0x42,0x13,0x93,0xff,0x7e,0x00,0x90,0x9e,0x38,0xe0,0xfc,0xa3,0xe0, ++0xfd,0x12,0x24,0x7b,0x90,0x9e,0x36,0xee,0xf0,0xa3,0xef,0xf0,0x74,0x84,0x25,0x59, ++0xf5,0x82,0xe4,0x34,0x98,0xf5,0x83,0xe0,0xf5,0x63,0xe4,0xf5,0x5a,0xab,0x5e,0xaa, ++0x5f,0xa9,0x60,0x75,0xf0,0x02,0xe5,0x5a,0xa4,0xf5,0x82,0x85,0xf0,0x83,0x12,0x42, ++0xc2,0xfd,0xac,0xf0,0xe5,0x5a,0x90,0x42,0x0e,0x93,0xff,0x7e,0x00,0x12,0x24,0x7b, ++0xef,0x25,0x62,0xf5,0x62,0xee,0x35,0x61,0xf5,0x61,0xc3,0x90,0x9e,0x37,0xe0,0x95, ++0x62,0x90,0x9e,0x36,0xe0,0x95,0x61,0x40,0x07,0x05,0x5a,0xe5,0x5a,0xb4,0x05,0xbd, ++0xe5,0x5a,0xc3,0x13,0xf5,0x5a,0xe5,0x63,0xb4,0x01,0x06,0xe5,0x5a,0x70,0x46,0x80, ++0x13,0xe5,0x63,0xb4,0x03,0x15,0xe5,0x5a,0x70,0x05,0x75,0x63,0x03,0x80,0x39,0xe5, ++0x5a,0xb4,0x01,0x05,0x75,0x63,0x01,0x80,0x2f,0x80,0x2a,0xe5,0x63,0xb4,0x05,0x28, ++0xe5,0x5a,0x70,0x05,0x75,0x63,0x05,0x80,0x0d,0xe5,0x5a,0xb4,0x01,0x05,0x75,0x63, ++0x03,0x80,0x03,0x75,0x63,0x01,0xd3,0x90,0x9e,0x3b,0xe0,0x94,0x03,0x90,0x9e,0x3a, ++0xe0,0x94,0x00,0x40,0x03,0xe4,0xf5,0x63,0xd3,0x90,0x9e,0x3b,0xe0,0x94,0x03,0x90, ++0x9e,0x3a,0xe0,0x94,0x00,0x40,0x03,0xe4,0xf5,0x63,0x74,0x84,0x25,0x59,0xf5,0x82, ++0xe4,0x34,0x98,0xf5,0x83,0xe5,0x63,0xf0,0xfd,0xaf,0x59,0x12,0x66,0x47,0x74,0xe6, ++0x25,0x59,0xf5,0x82,0xe4,0x34,0x9c,0xf5,0x83,0xe0,0xd3,0x94,0x05,0x74,0xe6,0x50, ++0x0e,0x25,0x59,0xf5,0x82,0xe4,0x34,0x9c,0xf5,0x83,0xe0,0x04,0xf0,0x80,0x0b,0x25, ++0x59,0xf5,0x82,0xe4,0x34,0x9c,0xf5,0x83,0xe4,0xf0,0xab,0x5e,0xaa,0x5f,0xa9,0x60, ++0xe4,0xf5,0xf0,0x12,0x42,0xfa,0xab,0x5e,0xaa,0x5f,0xa9,0x60,0x90,0x00,0x02,0xe4, ++0xf5,0xf0,0x12,0x43,0x19,0x90,0x00,0x04,0xe4,0xf5,0xf0,0x12,0x43,0x19,0x90,0x00, ++0x06,0xe4,0xf5,0xf0,0x12,0x43,0x19,0x90,0x00,0x08,0xe4,0xf5,0xf0,0x12,0x43,0x19, ++0xe5,0x59,0x25,0xe0,0x24,0x80,0xf5,0x82,0xe4,0x34,0x93,0xf5,0x83,0xe4,0xf0,0xa3, ++0xf0,0xe5,0x59,0x25,0xe0,0x24,0xc4,0xf5,0x82,0xe4,0x34,0x98,0xf5,0x83,0xe4,0xf0, ++0xa3,0xf0,0xe5,0x59,0x25,0xe0,0x24,0x44,0xf5,0x82,0xe4,0x34,0x99,0xf5,0x83,0xe4, ++0xf0,0xa3,0xf0,0x05,0x59,0xe5,0x59,0xc3,0x94,0x40,0x50,0x02,0x01,0x90,0x22,0x90, ++0x04,0x44,0x74,0x11,0xf0,0xa3,0x74,0xf0,0xf0,0xa3,0x74,0x0f,0xf0,0xa3,0xe4,0xf0, ++0xfd,0x74,0xa4,0x2d,0xf5,0x82,0xe4,0x34,0x04,0xf5,0x83,0xe4,0xf0,0x0d,0xbd,0x10, ++0xf0,0xe4,0x90,0x9a,0xc5,0xf0,0x90,0x95,0x01,0x04,0xf0,0xe4,0xfd,0x75,0xf0,0x0a, ++0xed,0x90,0x90,0x00,0x12,0x43,0x5f,0xe4,0xf0,0xa3,0xf0,0x75,0xf0,0x0a,0xed,0x90, ++0x90,0x02,0x12,0x43,0x5f,0xe4,0xf0,0xa3,0xf0,0x75,0xf0,0x0a,0xed,0x90,0x90,0x04, ++0x12,0x43,0x5f,0xe4,0xf0,0xa3,0xf0,0x75,0xf0,0x0a,0xed,0x90,0x90,0x06,0x12,0x43, ++0x5f,0xe4,0xf0,0xa3,0xf0,0x75,0xf0,0x0a,0xed,0x90,0x90,0x08,0x12,0x43,0x5f,0xe4, ++0xf0,0xa3,0xf0,0x74,0x26,0x2d,0xf5,0x82,0xe4,0x34,0x9d,0xf5,0x83,0x74,0x13,0xf0, ++0x74,0x85,0x2d,0xf5,0x82,0xe4,0x34,0x9a,0xf5,0x83,0xe4,0xf0,0x74,0x84,0x2d,0xf5, ++0x82,0xe4,0x34,0x98,0xf5,0x83,0xe4,0xf0,0xed,0x25,0xe0,0x24,0x80,0xf5,0x82,0xe4, ++0x34,0x93,0xf5,0x83,0xe4,0xf0,0xa3,0xf0,0xed,0x25,0xe0,0x24,0xc4,0xf5,0x82,0xe4, ++0x34,0x98,0xf5,0x83,0xe4,0xf0,0xa3,0xf0,0xed,0x25,0xe0,0x24,0xc4,0xf5,0x82,0xe4, ++0x34,0x99,0xf5,0x83,0xe4,0xf0,0xa3,0xf0,0xed,0x25,0xe0,0x24,0x44,0xf5,0x82,0xe4, ++0x34,0x99,0xf5,0x83,0xe4,0xf0,0xa3,0xf0,0xed,0x25,0xe0,0x24,0xc6,0xf5,0x82,0xe4, ++0x34,0x9a,0xf5,0x83,0xe4,0xf0,0xa3,0xf0,0xed,0x25,0xe0,0x24,0x46,0xf5,0x82,0xe4, ++0x34,0x9b,0xf5,0x83,0xe4,0xf0,0xa3,0xf0,0x74,0x86,0x2d,0xf5,0x82,0xe4,0x34,0x9c, ++0xf5,0x83,0xe4,0xf0,0x74,0x46,0x2d,0xf5,0x82,0xe4,0x34,0x9c,0xf5,0x83,0xe4,0xf0, ++0x74,0xe6,0x2d,0xf5,0x82,0xe4,0x34,0x9c,0xf5,0x83,0xe4,0xf0,0x90,0x41,0xc4,0x93, ++0xfe,0x74,0x01,0x93,0xff,0x90,0x41,0x8c,0x74,0x01,0x93,0x2f,0xff,0xe4,0x93,0x3e, ++0xc3,0x13,0xfe,0xef,0x13,0xff,0xed,0x25,0xe0,0x24,0xc2,0xf5,0x82,0xe4,0x34,0x95, ++0xf5,0x83,0xee,0xf0,0xa3,0xef,0xf0,0x75,0xf0,0x09,0xed,0x90,0x96,0x4b,0x12,0x43, ++0x5f,0x74,0x01,0xf0,0x75,0xf0,0x09,0xed,0x90,0x96,0x4a,0x12,0x43,0x5f,0x74,0x01, ++0xf0,0x74,0x82,0x2d,0xf5,0x82,0xe4,0x34,0x95,0xf5,0x83,0x74,0x0c,0xf0,0x75,0xf0, ++0x09,0xed,0x90,0x96,0x46,0x12,0x43,0x5f,0x74,0xff,0xf0,0xa3,0xf0,0x75,0xf0,0x09, ++0xed,0x90,0x96,0x44,0x12,0x43,0x5f,0xe4,0xf0,0xa3,0x74,0x0f,0xf0,0x75,0xf0,0x09, ++0xed,0x90,0x96,0x48,0x12,0x43,0x5f,0x74,0x13,0xf0,0x75,0xf0,0x09,0xed,0x90,0x96, ++0x49,0x12,0x43,0x5f,0xe4,0xf0,0xed,0xc3,0x94,0x20,0x50,0x0f,0x74,0x84,0x2d,0xf5, ++0x82,0xe4,0x34,0x04,0xf5,0x83,0x74,0x13,0xf0,0x80,0x0d,0x74,0xa6,0x2d,0xf5,0x82, ++0xe4,0x34,0x9c,0xf5,0x83,0x74,0x13,0xf0,0x0d,0xed,0x64,0x40,0x60,0x03,0x02,0x6f, ++0x0d,0x22,0x12,0x24,0x62,0xf5,0x59,0xc3,0x94,0x40,0x50,0x15,0x90,0x00,0x02,0x12, ++0x42,0x20,0xff,0x74,0x44,0x25,0x59,0xf5,0x82,0xe4,0x34,0x9a,0xf5,0x83,0xef,0xf0, ++0x22,0xe5,0x59,0xb4,0x40,0x0a,0x90,0x00,0x02,0x12,0x42,0x20,0x90,0x96,0x42,0xf0, ++0x22,0x90,0x00,0x04,0x12,0x42,0x20,0xff,0x54,0x3f,0xfe,0xef,0x54,0x80,0xc4,0x13, ++0x13,0x13,0x54,0x01,0xfd,0xaf,0x06,0x02,0x55,0x30,0x12,0x24,0x62,0x90,0x95,0x01, ++0xf0,0x22,0x12,0x24,0x62,0xf5,0x22,0x22,0x90,0x00,0x02,0x12,0x42,0x20,0xff,0x30, ++0xe0,0x25,0x12,0x24,0x62,0x90,0x9e,0x6a,0xf0,0x90,0x00,0x01,0x12,0x42,0x20,0x90, ++0x9e,0x6b,0xf0,0xef,0xc3,0x13,0x54,0x7f,0x90,0x9e,0x69,0xf0,0x90,0x00,0x03,0x12, ++0x42,0x20,0x90,0x9e,0x6f,0xf0,0x22,0x90,0x9e,0x6a,0x74,0x01,0xf0,0x90,0x9e,0x6b, ++0x74,0x03,0xf0,0x90,0x9e,0x69,0x74,0x14,0xf0,0x90,0x9e,0x6f,0x74,0x05,0xf0,0x22, ++0x12,0x24,0x62,0x30,0xe0,0x18,0xc3,0x13,0x54,0x7f,0x90,0x9e,0x6e,0xf0,0x90,0x00, ++0x01,0x12,0x42,0x20,0xff,0x90,0x9e,0x6c,0xe4,0xf0,0xa3,0xef,0xf0,0x22,0x90,0x9e, ++0x6e,0x74,0x07,0xf0,0x90,0x9e,0x6c,0xe4,0xf0,0xa3,0x74,0x02,0xf0,0x22,0x90,0x02, ++0x09,0xe0,0xfd,0x12,0x24,0x62,0xfe,0xaf,0x05,0xed,0x2e,0x90,0x9e,0x50,0xf0,0x90, ++0x00,0x01,0x12,0x42,0x20,0xff,0xed,0x2f,0x90,0x9e,0x51,0xf0,0x90,0x00,0x02,0x12, ++0x42,0x20,0xff,0xed,0x2f,0x90,0x9e,0x52,0xf0,0x90,0x00,0x03,0x12,0x42,0x20,0xff, ++0xed,0x2f,0x90,0x9e,0x53,0xf0,0x90,0x00,0x04,0x12,0x42,0x20,0xff,0xae,0x05,0xed, ++0x2f,0x90,0x9e,0x54,0xf0,0x22,0xd3,0x10,0xaf,0x01,0xc3,0xc0,0xd0,0x90,0x9e,0x3f, ++0x12,0x43,0x8b,0x90,0x9e,0x3f,0x12,0x43,0x6b,0x90,0x00,0x01,0x12,0x42,0xc2,0xfa, ++0xe5,0xf0,0x24,0x00,0xff,0xe4,0x3a,0xfe,0x90,0x9e,0x3f,0x12,0x43,0x6b,0x90,0x00, ++0x01,0xee,0x8f,0xf0,0x12,0x43,0x19,0x12,0x24,0x62,0xff,0x60,0x2c,0xb5,0x71,0x16, ++0x90,0x9e,0x3f,0x12,0x43,0x6b,0x90,0x00,0x01,0x12,0x42,0xc2,0x65,0x73,0x70,0x04, ++0xe5,0x72,0x65,0xf0,0x60,0x23,0x90,0x9e,0x3f,0x12,0x43,0x6b,0x90,0x00,0x01,0x12, ++0x42,0xc2,0xff,0xae,0xf0,0x51,0x3e,0x80,0x10,0x90,0x9e,0x3f,0x12,0x43,0x6b,0x12, ++0x24,0x62,0x65,0x71,0x60,0x03,0x12,0x44,0xc8,0xd0,0xd0,0x92,0xaf,0x22,0x90,0x9e, ++0x42,0xee,0xf0,0xa3,0xef,0xf0,0x75,0x71,0x01,0x8e,0x72,0xf5,0x73,0xe4,0xfd,0x7f, ++0x0b,0x51,0x80,0xe4,0xfd,0x7f,0x02,0x51,0x80,0x71,0x4a,0xe4,0xff,0x71,0xac,0xe4, ++0xf5,0x75,0x90,0x01,0xc9,0xe5,0x75,0xf0,0x90,0x9e,0x42,0xe0,0xfc,0xa3,0xe0,0xfd, ++0xec,0xfb,0x8d,0x44,0xe4,0xf5,0x45,0x7d,0x01,0x7f,0x60,0x7e,0x01,0x02,0x30,0x62, ++0xd3,0x10,0xaf,0x01,0xc3,0xc0,0xd0,0x90,0x9e,0x45,0xed,0xf0,0x90,0x9e,0x44,0xef, ++0xf0,0xd3,0x94,0x07,0x50,0x4f,0xa3,0xe0,0x70,0x1a,0x90,0x9e,0x44,0xe0,0xff,0x74, ++0x01,0xa8,0x07,0x08,0x80,0x02,0xc3,0x33,0xd8,0xfc,0xf4,0xff,0x90,0x00,0x47,0xe0, ++0x5f,0xf0,0x80,0x17,0x90,0x9e,0x44,0xe0,0xff,0x74,0x01,0xa8,0x07,0x08,0x80,0x02, ++0xc3,0x33,0xd8,0xfc,0xff,0x90,0x00,0x47,0xe0,0x4f,0xf0,0x12,0x4b,0xdb,0x90,0x9e, ++0x44,0xe0,0xff,0x74,0x01,0xa8,0x07,0x08,0x80,0x02,0xc3,0x33,0xd8,0xfc,0xf4,0xff, ++0x90,0x00,0x46,0x80,0x5a,0x90,0x9e,0x44,0xe0,0x24,0xf8,0xf0,0xa3,0xe0,0x70,0x1d, ++0x90,0x9e,0x44,0xe0,0xff,0x74,0x01,0xa8,0x07,0x08,0x80,0x02,0xc3,0x33,0xd8,0xfc, ++0xc4,0x54,0xf0,0xf4,0xff,0x90,0x00,0x43,0xe0,0x5f,0xf0,0x80,0x1a,0x90,0x9e,0x44, ++0xe0,0xff,0x74,0x01,0xa8,0x07,0x08,0x80,0x02,0xc3,0x33,0xd8,0xfc,0xc4,0x54,0xf0, ++0xff,0x90,0x00,0x43,0xe0,0x4f,0xf0,0x12,0x4b,0xdb,0x90,0x9e,0x44,0xe0,0xff,0x74, ++0x01,0xa8,0x07,0x08,0x80,0x02,0xc3,0x33,0xd8,0xfc,0xf4,0xff,0x90,0x00,0x43,0xe0, ++0x5f,0xf0,0x12,0x4b,0xdb,0xd0,0xd0,0x92,0xaf,0x22,0x7f,0x0b,0x71,0xb9,0xef,0x65, ++0x74,0x60,0x10,0xe5,0x74,0xb4,0x01,0x05,0xe4,0xf5,0x74,0x80,0x03,0x75,0x74,0x01, ++0x7f,0x01,0x22,0x7f,0x00,0x22,0xe5,0x71,0x64,0x01,0x70,0x3f,0x71,0x4a,0xbf,0x01, ++0x04,0x7f,0x01,0x71,0xac,0x90,0x00,0x46,0xe0,0x44,0x04,0xfd,0x7f,0x46,0x12,0x4c, ++0xe3,0x90,0x00,0x44,0xe0,0x54,0xfb,0xfd,0x7f,0x44,0x12,0x4c,0xe3,0x90,0x00,0x46, ++0xe0,0x54,0xfb,0xfd,0x7f,0x46,0x12,0x4c,0xe3,0x7f,0x02,0x71,0xb9,0x8f,0x75,0x90, ++0x01,0xc9,0xe5,0x75,0xf0,0xb4,0x01,0x03,0x12,0x4f,0xda,0x22,0x90,0x01,0xca,0xe5, ++0x74,0xf0,0xef,0x60,0x03,0x12,0x4f,0xda,0x22,0xd3,0x10,0xaf,0x01,0xc3,0xc0,0xd0, ++0x90,0x9e,0xb1,0xef,0xf0,0xd3,0x94,0x07,0x50,0x47,0xe0,0xff,0x74,0x01,0xa8,0x07, ++0x08,0x80,0x02,0xc3,0x33,0xd8,0xfc,0xf4,0xff,0x90,0x00,0x46,0xe0,0x5f,0xf0,0x12, ++0x4b,0xdb,0x90,0x9e,0xb1,0xe0,0xfd,0x74,0x01,0x7e,0x00,0xa8,0x05,0x08,0x80,0x05, ++0xc3,0x33,0xce,0x33,0xce,0xd8,0xf9,0xff,0x90,0x00,0x44,0xe0,0xfb,0xe4,0xfe,0xef, ++0x5b,0xa8,0x05,0x08,0x80,0x06,0xce,0xa2,0xe7,0x13,0xce,0x13,0xd8,0xf8,0xff,0x80, ++0x44,0x90,0x9e,0xb1,0xe0,0x24,0xf8,0xf0,0xe0,0xff,0x74,0x01,0xa8,0x07,0x08,0x80, ++0x02,0xc3,0x33,0xd8,0xfc,0x12,0x4b,0xd3,0x90,0x9e,0xb1,0xe0,0xfd,0x74,0x01,0x7e, ++0x00,0xa8,0x05,0x08,0x80,0x05,0xc3,0x33,0xce,0x33,0xce,0xd8,0xf9,0xff,0x90,0x00, ++0x42,0xe0,0xfb,0xe4,0xfe,0xef,0x5b,0xa8,0x05,0x08,0x80,0x06,0xce,0xa2,0xe7,0x13, ++0xce,0x13,0xd8,0xf8,0xff,0xd0,0xd0,0x92,0xaf,0x22,0xd3,0x10,0xaf,0x01,0xc3,0xc0, ++0xd0,0x90,0x9e,0x56,0xe0,0x90,0x9e,0x40,0xf0,0x90,0x9e,0x57,0xe0,0xf5,0x64,0xa3, ++0xe0,0xf5,0x65,0xe4,0xf5,0x61,0x74,0x59,0x25,0x61,0xf5,0x82,0xe4,0x34,0x9e,0xf5, ++0x83,0xe0,0xff,0x74,0x66,0x25,0x61,0xf8,0xa6,0x07,0x05,0x61,0xe5,0x61,0xb4,0x04, ++0xe5,0x90,0x9e,0x40,0xe0,0x12,0x43,0x94,0x74,0xb7,0x00,0x75,0xdf,0x01,0x74,0xbd, ++0x02,0x74,0xbd,0x03,0x74,0xbd,0x04,0x75,0xdf,0x05,0x75,0xaf,0x80,0x75,0xc5,0x81, ++0x75,0xdf,0x82,0x00,0x00,0x75,0xdb,0xaf,0x69,0xb1,0xe6,0xa1,0xdf,0x90,0x9e,0x40, ++0xe0,0xff,0xb4,0x02,0x08,0x90,0x9e,0x3f,0x74,0x01,0xf0,0x80,0x0f,0xef,0x90,0x9e, ++0x3f,0xb4,0x03,0x05,0x74,0x02,0xf0,0x80,0x03,0x74,0x04,0xf0,0xc3,0xe5,0x64,0x94, ++0x08,0x50,0x49,0xe4,0xf5,0x61,0x90,0x9e,0x3f,0xe0,0xff,0xe5,0x61,0xc3,0x9f,0x40, ++0x02,0xa1,0xdf,0xc3,0xe5,0x64,0x94,0x01,0x50,0x14,0xe5,0x61,0x25,0x65,0xff,0xc3, ++0x74,0x03,0x95,0x61,0x24,0x66,0xf8,0xe6,0xfd,0x12,0x4c,0xe3,0x80,0x1a,0xc3,0x74, ++0x03,0x95,0x61,0x24,0x66,0xf8,0xe6,0xff,0xe5,0x61,0x7c,0x00,0x25,0x65,0xfd,0xec, ++0x35,0x64,0x8d,0x82,0xf5,0x83,0xef,0xf0,0x05,0x61,0x80,0xba,0xc3,0xe5,0x64,0x94, ++0x10,0x40,0x02,0xa1,0xdf,0x90,0x9e,0x40,0xe0,0x64,0x04,0x60,0x02,0xa1,0xdf,0xaf, ++0x67,0xfc,0xfd,0xfe,0x78,0x10,0x12,0x24,0xf5,0xc0,0x04,0xc0,0x05,0xc0,0x06,0xc0, ++0x07,0xaf,0x66,0xe4,0xfc,0xfd,0xfe,0x78,0x18,0x12,0x24,0xf5,0xd0,0x03,0xd0,0x02, ++0xd0,0x01,0xd0,0x00,0x12,0x43,0x46,0xc0,0x04,0xc0,0x05,0xc0,0x06,0xc0,0x07,0xaf, ++0x68,0xe4,0xfc,0xfd,0xfe,0x78,0x08,0x12,0x24,0xf5,0xd0,0x03,0xd0,0x02,0xd0,0x01, ++0xd0,0x00,0x12,0x43,0x46,0xa8,0x04,0xa9,0x05,0xaa,0x06,0xab,0x07,0xaf,0x69,0xe4, ++0xfc,0xfd,0xfe,0x12,0x43,0x46,0xa3,0x12,0x25,0x08,0x90,0x9e,0x41,0x12,0x43,0x53, ++0x90,0x80,0x96,0x12,0x25,0x08,0xaf,0x65,0xae,0x64,0x12,0x2b,0x08,0x80,0x30,0xe5, ++0x68,0x7f,0x00,0xfe,0xef,0x25,0x69,0xf5,0x63,0xe4,0x3e,0xf5,0x62,0xaf,0x63,0xfe, ++0x12,0x32,0x15,0x80,0x1a,0xe5,0x68,0x7f,0x00,0xfe,0xef,0x25,0x69,0xf5,0x63,0xe4, ++0x3e,0xf5,0x62,0xaf,0x63,0xfe,0x12,0x31,0x82,0x80,0x04,0x7f,0x00,0x80,0x02,0x7f, ++0x01,0xd0,0xd0,0x92,0xaf,0x22,0x8f,0x6a,0xe4,0x90,0x9e,0x45,0xf0,0xe5,0x6a,0x14, ++0xfe,0x90,0x9e,0x45,0xe0,0xff,0xc3,0x9e,0x50,0x0e,0xef,0x04,0xfd,0x12,0x2d,0x4d, ++0x90,0x9e,0x45,0xe0,0x04,0xf0,0x80,0xe5,0xe5,0x6a,0x14,0xff,0x7d,0xff,0x12,0x2d, ++0x4d,0x90,0x9e,0x45,0xe5,0x6a,0xf0,0x90,0x9e,0x45,0xe0,0xc3,0x94,0xff,0x50,0x0f, ++0xe0,0xff,0x04,0xfd,0x12,0x2d,0x4d,0x90,0x9e,0x45,0xe0,0x04,0xf0,0x80,0xe8,0xad, ++0x6a,0x7f,0xff,0x02,0x2d,0x4d,0xd3,0x10,0xaf,0x01,0xc3,0xc0,0xd0,0xe4,0xf5,0x5b, ++0x75,0x5c,0x04,0xf5,0x5d,0xf5,0x5f,0xf5,0x60,0x90,0x02,0x09,0xe0,0xff,0x12,0x24, ++0x62,0xfe,0xef,0x2e,0xf5,0x5e,0x30,0xe0,0x08,0x75,0x59,0x00,0x75,0x5a,0x80,0x80, ++0x05,0xe4,0xf5,0x59,0xf5,0x5a,0xe5,0x5e,0xc3,0x13,0x90,0xfd,0x10,0xf0,0x74,0x20, ++0x25,0x5b,0xf5,0x5b,0xad,0x5a,0xe5,0x5b,0x2d,0xff,0x24,0x01,0xf5,0x82,0xe4,0x34, ++0xfc,0xf5,0x83,0xe0,0x90,0x9e,0x56,0xf0,0x74,0x02,0x2f,0xf5,0x82,0xe4,0x34,0xfc, ++0xf5,0x83,0xe0,0xfe,0xe5,0x5b,0x2d,0x24,0x03,0xf5,0x82,0xe4,0x34,0xfc,0xf5,0x83, ++0xe0,0x24,0x00,0xff,0xe4,0x3e,0x90,0x9e,0x57,0xf0,0xa3,0xef,0xf0,0x7f,0x04,0xe5, ++0x5b,0x25,0x5a,0x2f,0x24,0x00,0xf5,0x82,0xe4,0x34,0xfc,0xf5,0x83,0xe0,0xfe,0x74, ++0x55,0x2f,0xf5,0x82,0xe4,0x34,0x9e,0xf5,0x83,0xee,0xf0,0x0f,0xbf,0x08,0xe0,0x91, ++0x5a,0xef,0x70,0x3f,0x90,0x01,0xc3,0xe0,0x60,0x25,0xc3,0xe5,0x60,0x94,0xe8,0xe5, ++0x5f,0x94,0x03,0x40,0x09,0x90,0x01,0xc6,0xe0,0x44,0x10,0xf0,0x80,0x63,0x05,0x60, ++0xe5,0x60,0x70,0x02,0x05,0x5f,0x7f,0x0a,0x7e,0x00,0x12,0x32,0x15,0x80,0xd5,0x90, ++0x01,0xc6,0xe0,0x90,0x01,0xc3,0x30,0xe2,0x05,0x74,0xfe,0xf0,0x80,0x43,0x74,0xff, ++0xf0,0x80,0x3e,0xe5,0x5b,0xb4,0x78,0x23,0xe4,0xf5,0x5b,0x05,0x5e,0xe5,0x5a,0x64, ++0x80,0x45,0x59,0x70,0x06,0xf5,0x59,0xf5,0x5a,0x80,0x06,0x75,0x59,0x00,0x75,0x5a, ++0x80,0xe5,0x5e,0xc3,0x13,0x90,0xfd,0x10,0xf0,0x80,0x06,0x74,0x08,0x25,0x5b,0xf5, ++0x5b,0xe5,0x5d,0x15,0x5d,0x70,0x02,0x15,0x5c,0xe5,0x5d,0x45,0x5c,0x60,0x02,0xc1, ++0x74,0xd0,0xd0,0x92,0xaf,0x22,0x90,0x06,0x34,0x74,0xff,0xf0,0xe4,0xa3,0xf0,0xa3, ++0xf0,0xa3,0xf0,0x22,0xe4,0x90,0x9e,0x5d,0xf0,0x90,0x00,0x80,0xe0,0x44,0x80,0xfd, ++0x7f,0x80,0x02,0x4c,0xe3,0x8e,0x59,0x8f,0x5a,0x8b,0x5b,0x8a,0x5c,0x89,0x5d,0xe4, ++0x90,0x9e,0x34,0xf0,0xef,0x90,0x00,0x31,0xf0,0x12,0x4b,0xdb,0xe5,0x59,0x54,0x03, ++0xff,0x90,0x00,0x32,0xe0,0x54,0xfc,0x4f,0xf0,0x12,0x4b,0xdb,0x90,0x00,0x33,0xe0, ++0x54,0x7f,0xf0,0x12,0x4b,0xdb,0x90,0x00,0x33,0xe0,0x20,0xe7,0x0e,0x90,0x9e,0x34, ++0xe0,0xc3,0x94,0x64,0x50,0x05,0xe0,0x04,0xf0,0x80,0xeb,0x90,0x9e,0x34,0xe0,0xc3, ++0x94,0x64,0x50,0x10,0x90,0x00,0x30,0xe0,0xab,0x5b,0xaa,0x5c,0xa9,0x5d,0x12,0x42, ++0x4d,0x7f,0x01,0x22,0x7f,0x00,0x22,0xe4,0xf5,0x74,0x22,0x90,0x9e,0x60,0xe0,0x90, ++0x9e,0x0f,0xf0,0x22,0xef,0x70,0x03,0x02,0x79,0x9c,0x90,0x9e,0x0f,0xe0,0x60,0x03, ++0x02,0x7d,0x67,0x90,0x9d,0xfb,0x12,0x43,0x53,0x90,0x80,0x96,0x12,0x25,0x08,0x7f, ++0x8c,0x7e,0x08,0x12,0x2b,0x08,0x90,0x9d,0xa7,0x12,0x43,0x53,0x90,0x80,0x96,0x12, ++0x25,0x08,0x7f,0x44,0x7e,0x08,0x12,0x2b,0x08,0x90,0x9d,0xab,0x12,0x43,0x53,0x90, ++0x80,0x96,0x12,0x25,0x08,0x7f,0x5c,0x7e,0x08,0x12,0x2b,0x08,0x90,0x9d,0xaf,0x12, ++0x43,0x53,0x90,0x80,0x96,0x12,0x25,0x08,0x7f,0x6c,0x7e,0x0e,0x12,0x2b,0x08,0x90, ++0x9d,0xb3,0x12,0x43,0x53,0x90,0x80,0x96,0x12,0x25,0x08,0x7f,0x70,0x7e,0x0e,0x12, ++0x2b,0x08,0x90,0x9d,0xb7,0x12,0x43,0x53,0x90,0x80,0x96,0x12,0x25,0x08,0x7f,0x74, ++0x7e,0x0e,0x12,0x2b,0x08,0x90,0x9d,0xbb,0x12,0x43,0x53,0x90,0x80,0x96,0x12,0x25, ++0x08,0x7f,0x78,0x7e,0x0e,0x12,0x2b,0x08,0x90,0x9d,0xbf,0x12,0x43,0x53,0x90,0x80, ++0x96,0x12,0x25,0x08,0x7f,0x7c,0x7e,0x0e,0x12,0x2b,0x08,0x90,0x9d,0xc3,0x12,0x43, ++0x53,0x90,0x80,0x96,0x12,0x25,0x08,0x7f,0x80,0x7e,0x0e,0x12,0x2b,0x08,0x90,0x9d, ++0xc7,0x12,0x43,0x53,0x90,0x80,0x96,0x12,0x25,0x08,0x7f,0x84,0x7e,0x0e,0x12,0x2b, ++0x08,0x90,0x9d,0xcb,0x12,0x43,0x53,0x90,0x80,0x96,0x12,0x25,0x08,0x7f,0x88,0x7e, ++0x0e,0x12,0x2b,0x08,0x90,0x9d,0xcf,0x12,0x43,0x53,0x90,0x80,0x96,0x12,0x25,0x08, ++0x7f,0x8c,0x7e,0x0e,0x12,0x2b,0x08,0x90,0x9d,0xd3,0x12,0x43,0x53,0x90,0x80,0x96, ++0x12,0x25,0x08,0x7f,0xd0,0x7e,0x0e,0x12,0x2b,0x08,0x90,0x9d,0xd7,0x12,0x43,0x53, ++0x90,0x80,0x96,0x12,0x25,0x08,0x7f,0xd4,0x7e,0x0e,0x12,0x2b,0x08,0x90,0x9d,0xdb, ++0x12,0x43,0x53,0x90,0x80,0x96,0x12,0x25,0x08,0x7f,0xd8,0x7e,0x0e,0x12,0x2b,0x08, ++0x90,0x9d,0xdf,0x12,0x43,0x53,0x90,0x80,0x96,0x12,0x25,0x08,0x7f,0xdc,0x7e,0x0e, ++0x12,0x2b,0x08,0x90,0x9d,0xe3,0x12,0x43,0x53,0x90,0x80,0x96,0x12,0x25,0x08,0x7f, ++0xe0,0x7e,0x0e,0x12,0x2b,0x08,0x90,0x9d,0xe7,0x12,0x43,0x53,0x90,0x80,0x96,0x12, ++0x25,0x08,0x7f,0xec,0x7e,0x0e,0x12,0x2b,0x08,0x90,0x9d,0xeb,0x12,0x43,0x53,0x90, ++0x80,0x96,0x12,0x25,0x08,0x7f,0x04,0x7e,0x0c,0x12,0x2b,0x08,0x90,0x9d,0xef,0x12, ++0x43,0x53,0x90,0x80,0x96,0x12,0x25,0x08,0x7f,0x04,0x7e,0x0d,0x12,0x2b,0x08,0x90, ++0x9d,0xf3,0x12,0x43,0x53,0x90,0x80,0x96,0x12,0x25,0x08,0x7f,0x0c,0x7e,0x09,0x12, ++0x2b,0x08,0x90,0x9d,0xf7,0x12,0x43,0x53,0x90,0x80,0x96,0x12,0x25,0x08,0x7f,0x04, ++0x7e,0x08,0x12,0x2b,0x08,0x90,0x9e,0x0f,0x74,0x01,0xf0,0x22,0x90,0x9e,0x0f,0xe0, ++0x64,0x01,0x60,0x02,0xa1,0x67,0x7f,0x8c,0x7e,0x08,0x12,0x22,0x65,0x90,0x9d,0xfb, ++0x12,0x25,0x08,0x7f,0x44,0x7e,0x08,0x12,0x22,0x65,0x90,0x9d,0xa7,0x12,0x25,0x08, ++0x7f,0x5c,0x7e,0x08,0x12,0x22,0x65,0x90,0x9d,0xab,0x12,0x25,0x08,0x7f,0x6c,0x7e, ++0x0e,0x12,0x22,0x65,0x90,0x9d,0xaf,0x12,0x25,0x08,0x7f,0x70,0x7e,0x0e,0x12,0x22, ++0x65,0x90,0x9d,0xb3,0x12,0x25,0x08,0x7f,0x74,0x7e,0x0e,0x12,0x22,0x65,0x90,0x9d, ++0xb7,0x12,0x25,0x08,0x7f,0x78,0x7e,0x0e,0x12,0x22,0x65,0x90,0x9d,0xbb,0x12,0x25, ++0x08,0x7f,0x7c,0x7e,0x0e,0x12,0x22,0x65,0x90,0x9d,0xbf,0x12,0x25,0x08,0x7f,0x80, ++0x7e,0x0e,0x12,0x22,0x65,0x90,0x9d,0xc3,0x12,0x25,0x08,0x7f,0x84,0x7e,0x0e,0x12, ++0x22,0x65,0x90,0x9d,0xc7,0x12,0x25,0x08,0x7f,0x88,0x7e,0x0e,0x12,0x22,0x65,0x90, ++0x9d,0xcb,0x12,0x25,0x08,0x7f,0x8c,0x7e,0x0e,0x12,0x22,0x65,0x90,0x9d,0xcf,0x12, ++0x25,0x08,0x7f,0xd0,0x7e,0x0e,0x12,0x22,0x65,0x90,0x9d,0xd3,0x12,0x25,0x08,0x7f, ++0xd4,0x7e,0x0e,0x12,0x22,0x65,0x90,0x9d,0xd7,0x12,0x25,0x08,0x7f,0xd8,0x7e,0x0e, ++0x12,0x22,0x65,0x90,0x9d,0xdb,0x12,0x25,0x08,0x7f,0xdc,0x7e,0x0e,0x12,0x22,0x65, ++0x90,0x9d,0xdf,0x12,0x25,0x08,0x7f,0xe0,0x7e,0x0e,0x12,0x22,0x65,0x90,0x9d,0xe3, ++0x12,0x25,0x08,0x7f,0xec,0x7e,0x0e,0x12,0x22,0x65,0x90,0x9d,0xe7,0x12,0x25,0x08, ++0x7f,0x04,0x7e,0x0c,0x12,0x22,0x65,0x90,0x9d,0xeb,0x12,0x25,0x08,0x7f,0x04,0x7e, ++0x0d,0x12,0x22,0x65,0x90,0x9d,0xef,0x12,0x25,0x08,0x7f,0x0c,0x7e,0x09,0x12,0x22, ++0x65,0x90,0x9d,0xf3,0x12,0x25,0x08,0x7f,0x04,0x7e,0x08,0x12,0x22,0x65,0x90,0x9d, ++0xf7,0x12,0x25,0x08,0x7f,0x8c,0x7e,0x08,0x12,0x22,0x65,0x90,0x9e,0xa1,0x12,0x25, ++0x08,0x90,0x9e,0xa1,0x12,0x43,0x53,0xed,0x44,0xc0,0xfd,0xec,0x90,0x9e,0xa1,0x12, ++0x25,0x08,0x90,0x9e,0xa1,0x12,0x43,0x53,0x90,0x80,0x96,0x12,0x25,0x08,0x7f,0x8c, ++0x7e,0x08,0x12,0x2b,0x08,0x90,0x80,0x96,0x12,0x25,0x14,0x00,0x01,0x00,0x00,0x7f, ++0x44,0x7e,0x08,0x12,0x2b,0x08,0x90,0x80,0x96,0x12,0x25,0x14,0x00,0xdb,0x25,0xa4, ++0x7f,0x5c,0x7e,0x08,0x12,0x2b,0x08,0x90,0x80,0x96,0x12,0x25,0x14,0x20,0xdb,0x25, ++0xa4,0x7f,0x6c,0x7e,0x0e,0x12,0x2b,0x08,0x90,0x80,0x96,0x12,0x25,0x14,0x20,0xdb, ++0x25,0xa4,0x7f,0x70,0x7e,0x0e,0x12,0x2b,0x08,0x90,0x80,0x96,0x12,0x25,0x14,0x04, ++0x1b,0x25,0xa4,0x7f,0x74,0x7e,0x0e,0x12,0x2b,0x08,0x90,0x80,0x96,0x12,0x25,0x14, ++0x04,0x1b,0x25,0xa4,0x7f,0x78,0x7e,0x0e,0x12,0x2b,0x08,0x90,0x80,0x96,0x12,0x25, ++0x14,0x04,0x1b,0x25,0xa4,0x7f,0x7c,0x7e,0x0e,0x12,0x2b,0x08,0x90,0x80,0x96,0x12, ++0x25,0x14,0x04,0x1b,0x25,0xa4,0x7f,0x80,0x7e,0x0e,0x12,0x2b,0x08,0x90,0x80,0x96, ++0x12,0x25,0x14,0x63,0xdb,0x25,0xa4,0x7f,0x84,0x7e,0x0e,0x12,0x2b,0x08,0x90,0x80, ++0x96,0x12,0x25,0x14,0x04,0x1b,0x25,0xa4,0x7f,0x88,0x7e,0x0e,0x12,0x2b,0x08,0x90, ++0x80,0x96,0x12,0x25,0x14,0x20,0xdb,0x25,0xa4,0x7f,0x8c,0x7e,0x0e,0x12,0x2b,0x08, ++0x90,0x80,0x96,0x12,0x25,0x14,0x20,0xdb,0x25,0xa4,0x7f,0xd0,0x7e,0x0e,0x12,0x2b, ++0x08,0x90,0x80,0x96,0x12,0x25,0x14,0x20,0xdb,0x25,0xa4,0x7f,0xd4,0x7e,0x0e,0x12, ++0x2b,0x08,0x90,0x80,0x96,0x12,0x25,0x14,0x20,0xdb,0x25,0xa4,0x7f,0xd8,0x7e,0x0e, ++0x12,0x2b,0x08,0x90,0x80,0x96,0x12,0x25,0x14,0x00,0x1b,0x25,0xa4,0x7f,0xdc,0x7e, ++0x0e,0x12,0x2b,0x08,0x90,0x80,0x96,0x12,0x25,0x14,0x00,0x1b,0x25,0xa4,0x7f,0xe0, ++0x7e,0x0e,0x12,0x2b,0x08,0x90,0x80,0x96,0x12,0x25,0x14,0x24,0xdb,0x25,0xa4,0x7f, ++0xec,0x7e,0x0e,0x12,0x2b,0x08,0x7f,0x04,0x7e,0x0c,0x12,0x22,0x65,0x90,0x9e,0xa1, ++0x12,0x25,0x08,0x90,0x9e,0xa1,0x12,0x43,0x53,0xe4,0xff,0xec,0x90,0x9e,0xa1,0x12, ++0x25,0x08,0x90,0x9e,0xa1,0x12,0x43,0x53,0xef,0x44,0x11,0xff,0xec,0x90,0x9e,0xa1, ++0x12,0x25,0x08,0x90,0x9e,0xa1,0x12,0x43,0x53,0x90,0x80,0x96,0x12,0x25,0x08,0x7f, ++0x04,0x7e,0x0c,0x12,0x2b,0x08,0x7f,0x04,0x7e,0x0d,0x12,0x22,0x65,0x90,0x9e,0xa1, ++0x12,0x25,0x08,0x90,0x9e,0xa1,0x12,0x43,0x53,0xef,0x54,0xf0,0xff,0xec,0x90,0x9e, ++0xa1,0x12,0x25,0x08,0x90,0x9e,0xa1,0x12,0x43,0x53,0xef,0x44,0x01,0xff,0xec,0x90, ++0x9e,0xa1,0x12,0x25,0x08,0x90,0x9e,0xa1,0x12,0x43,0x53,0x90,0x80,0x96,0x12,0x25, ++0x08,0x7f,0x04,0x7e,0x0d,0x12,0x2b,0x08,0x7f,0x0c,0x7e,0x09,0x12,0x22,0x65,0x90, ++0x9e,0xa1,0x12,0x25,0x08,0x90,0x9e,0xa1,0x12,0x43,0x53,0xe4,0xff,0xec,0x90,0x9e, ++0xa1,0x12,0x25,0x08,0x90,0x9e,0xa1,0x12,0x43,0x53,0xef,0x44,0x11,0xff,0xec,0x90, ++0x9e,0xa1,0x12,0x25,0x08,0x90,0x9e,0xa1,0x12,0x43,0x53,0x90,0x80,0x96,0x12,0x25, ++0x08,0x7f,0x0c,0x7e,0x09,0x12,0x2b,0x08,0x7f,0x0c,0x7e,0x09,0x12,0x22,0x65,0x90, ++0x9e,0xa1,0x12,0x25,0x08,0x90,0x9e,0xa1,0x12,0x43,0x53,0xed,0x54,0x0f,0xfd,0xec, ++0x54,0xf0,0xfc,0x90,0x9e,0xa1,0x12,0x25,0x08,0x90,0x9e,0xa1,0x12,0x43,0x53,0xed, ++0x44,0x10,0xfd,0xec,0x44,0x01,0xfc,0x90,0x9e,0xa1,0x12,0x25,0x08,0x90,0x9e,0xa1, ++0x12,0x43,0x53,0x90,0x80,0x96,0x12,0x25,0x08,0x7f,0x0c,0x7e,0x09,0x12,0x2b,0x08, ++0x7f,0x04,0x7e,0x08,0x12,0x22,0x65,0x90,0x9e,0xa1,0x12,0x25,0x08,0x90,0x9e,0xa1, ++0x12,0x43,0x53,0xef,0x54,0xf0,0xff,0xec,0x90,0x9e,0xa1,0x12,0x25,0x08,0x90,0x9e, ++0xa1,0x12,0x43,0x53,0xef,0x44,0x01,0xff,0xec,0x90,0x9e,0xa1,0x12,0x25,0x08,0x90, ++0x9e,0xa1,0x12,0x43,0x53,0x90,0x80,0x96,0x12,0x25,0x08,0x7f,0x04,0x7e,0x08,0x12, ++0x2b,0x08,0xe4,0x90,0x9e,0x0f,0xf0,0x22,0x90,0x00,0x02,0x12,0x42,0x20,0x90,0x9e, ++0x1e,0xf0,0xe0,0x60,0x04,0xe0,0xf4,0x70,0x21,0xa2,0xaf,0xe4,0x33,0xf5,0x59,0xc2, ++0xaf,0x90,0x00,0x47,0xe0,0x54,0xfb,0xfd,0x7f,0x47,0x12,0x4c,0xe3,0x7d,0x40,0x7f, ++0x01,0x12,0x31,0x66,0xe5,0x59,0x24,0xff,0x92,0xaf,0x22,0xe4,0xfd,0x7f,0x45,0x12, ++0x4c,0xe3,0x90,0x04,0xfd,0xe4,0xf0,0xa3,0xf0,0x90,0x9e,0x1e,0xf0,0x90,0x9e,0x24, ++0xf0,0x90,0x9e,0x27,0xf0,0x90,0x9e,0x25,0xf0,0x90,0x9e,0x28,0xf0,0x90,0x9e,0x26, ++0xf0,0x90,0x9e,0x29,0xf0,0x90,0x9e,0x10,0x04,0xf0,0xe4,0xa3,0xf0,0xa3,0xf0,0xa3, ++0xf0,0x90,0x9e,0x15,0xf0,0x90,0x9e,0x1a,0xf0,0x90,0x9e,0x1c,0xf0,0x90,0x9e,0x2e, ++0xf0,0x90,0x9e,0x1f,0xf0,0x90,0x9e,0x1b,0xf0,0x90,0x9e,0x14,0xf0,0x90,0x00,0x51, ++0xe0,0x44,0xc0,0xfd,0x7f,0x51,0x02,0x4c,0xe3,0x90,0x9e,0x2e,0xe0,0x64,0x01,0x60, ++0x08,0x90,0x9e,0x1c,0xe0,0x60,0x02,0xc1,0xd0,0x90,0x9e,0x10,0xe0,0xc3,0x94,0xff, ++0x50,0x05,0xe0,0x04,0xf0,0x80,0x3b,0x90,0x9e,0x11,0xe0,0xc3,0x94,0xff,0x50,0x06, ++0xe0,0x04,0xf0,0xe4,0x80,0x28,0x90,0x9e,0x12,0xe0,0xc3,0x94,0xff,0x50,0x0a,0xe0, ++0x04,0xf0,0xe4,0x90,0x9e,0x11,0xf0,0x80,0x15,0x90,0x9e,0x13,0xe0,0xc3,0x94,0xff, ++0x50,0x10,0xe0,0x04,0xf0,0xe4,0x90,0x9e,0x12,0xf0,0x90,0x9e,0x11,0xf0,0x90,0x9e, ++0x10,0xf0,0x90,0x00,0x44,0xe0,0x54,0x0c,0x60,0x76,0xe0,0x30,0xe2,0x32,0x90,0x9e, ++0x24,0xe0,0xc3,0x94,0xff,0x50,0x05,0xe0,0x04,0xf0,0x80,0x24,0x90,0x9e,0x25,0xe0, ++0xc3,0x94,0xff,0x50,0x06,0xe0,0x04,0xf0,0xe4,0x80,0x11,0x90,0x9e,0x26,0xe0,0xc3, ++0x94,0xff,0x50,0x0c,0xe0,0x04,0xf0,0xe4,0x90,0x9e,0x25,0xf0,0x90,0x9e,0x24,0xf0, ++0x90,0x00,0x44,0xe0,0x30,0xe3,0x32,0x90,0x9e,0x27,0xe0,0xc3,0x94,0xff,0x50,0x05, ++0xe0,0x04,0xf0,0x80,0x24,0x90,0x9e,0x28,0xe0,0xc3,0x94,0xff,0x50,0x06,0xe0,0x04, ++0xf0,0xe4,0x80,0x11,0x90,0x9e,0x29,0xe0,0xc3,0x94,0xff,0x50,0x0c,0xe0,0x04,0xf0, ++0xe4,0x90,0x9e,0x28,0xf0,0x90,0x9e,0x27,0xf0,0x90,0x04,0xfd,0xe0,0x44,0x01,0xf0, ++0x22,0x00,0x6a,0xe7,}; ++ ++// =================== v80 UMC B Cut COMMON 2011-12-14 ===================== ++u8 Rtl8192CUFwUMCBCutImgArray[UMCBCutImgArrayLength] = { ++0xc2,0x88,0x02,0x00,0x50,0x00,0x00,0x00,0x12,0x14,0x16,0x10,0xc0,0x3e,0x01,0x00, ++0x25,0x86,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x02,0x43,0xba,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x02,0x48,0x79,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x02,0x5e,0xff,0x00,0x00,0x00,0x00,0x00,0xa1,0xd4,0x00,0x00,0x00, ++0x05,0x04,0x03,0x02,0x00,0x03,0x06,0x05,0x04,0x03,0x00,0x04,0x06,0x05,0x04,0x02, ++0x00,0x04,0x08,0x07,0x06,0x04,0x00,0x06,0x0a,0x09,0x08,0x06,0x00,0x08,0x0a,0x09, ++0x08,0x04,0x00,0x08,0x0a,0x09,0x08,0x02,0x00,0x08,0x0a,0x09,0x08,0x00,0x00,0x08, ++0x12,0x11,0x10,0x08,0x00,0x10,0x1a,0x19,0x18,0x10,0x00,0x18,0x22,0x21,0x20,0x18, ++0x00,0x20,0x22,0x21,0x20,0x10,0x00,0x20,0x22,0x21,0x20,0x08,0x00,0x20,0x22,0x21, ++0x1c,0x08,0x00,0x20,0x22,0x21,0x14,0x08,0x00,0x20,0x22,0x20,0x18,0x08,0x00,0x20, ++0x31,0x30,0x20,0x10,0x00,0x30,0x31,0x30,0x18,0x00,0x00,0x30,0x31,0x2f,0x10,0x10, ++0x00,0x30,0x31,0x2c,0x10,0x10,0x00,0x30,0x31,0x28,0x10,0x00,0x00,0x30,0x31,0x20, ++0x10,0x00,0x00,0x30,0x31,0x10,0x10,0x00,0x00,0x30,0x04,0x04,0x04,0x05,0x04,0x04, ++0x04,0x05,0x05,0x05,0x06,0x06,0x04,0x04,0x04,0x05,0x05,0x05,0x06,0x06,0x04,0x04, ++0x05,0x05,0x05,0x05,0x06,0x06,0x04,0x04,0x05,0x05,0x05,0x05,0x06,0x07,0x0a,0x0b, ++0x0d,0x10,0x04,0x05,0x05,0x06,0x06,0x09,0x0c,0x11,0x08,0x08,0x09,0x09,0x0a,0x0c, ++0x10,0x11,0x04,0x04,0x04,0x05,0x04,0x04,0x05,0x07,0x07,0x07,0x08,0x0a,0x04,0x04, ++0x04,0x04,0x06,0x0a,0x0b,0x0d,0x05,0x05,0x07,0x07,0x08,0x0b,0x0d,0x0f,0x04,0x04, ++0x04,0x05,0x07,0x07,0x09,0x09,0x0c,0x0e,0x10,0x12,0x04,0x04,0x05,0x05,0x06,0x0a, ++0x11,0x13,0x09,0x09,0x09,0x09,0x0c,0x0e,0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x24,0x26,0x2a,0x18,0x1a,0x1d,0x1f,0x21,0x27,0x29,0x2a,0x00,0x00, ++0x00,0x1f,0x23,0x28,0x2a,0x2c,0x00,0x04,0x00,0x04,0x00,0x08,0x00,0x10,0x00,0x18, ++0x00,0x24,0x00,0x30,0x00,0x48,0x00,0x60,0x00,0x90,0x00,0xc0,0x00,0xd8,0x00,0x50, ++0x00,0x78,0x00,0xa0,0x00,0xc8,0x01,0x40,0x01,0x90,0x01,0xe0,0x02,0x30,0x01,0x2c, ++0x01,0x40,0x01,0xe0,0x02,0xd0,0x03,0xe8,0x04,0xb0,0x06,0x40,0x07,0xd0,0x00,0x02, ++0x00,0x02,0x00,0x04,0x00,0x08,0x00,0x0c,0x00,0x12,0x00,0x18,0x00,0x24,0x00,0x30, ++0x00,0x48,0x00,0x60,0x00,0x6c,0x00,0x28,0x00,0x3c,0x00,0x50,0x00,0x64,0x00,0xa0, ++0x00,0xc8,0x00,0xf0,0x01,0x18,0x00,0x64,0x00,0xa0,0x00,0xf0,0x01,0x68,0x01,0xf4, ++0x02,0x58,0x03,0x20,0x03,0xe8,0x02,0x02,0x02,0x02,0x02,0x02,0x03,0x03,0x04,0x04, ++0x05,0x07,0x04,0x04,0x07,0x0a,0x0a,0x0c,0x0c,0x12,0x05,0x07,0x07,0x08,0x0b,0x12, ++0x24,0x3c,0x01,0x01,0x01,0x01,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x01,0x02, ++0x03,0x04,0x05,0x06,0x07,0x08,0x05,0x06,0x07,0x08,0x09,0x0a,0x0b,0x0c,0x20,0x1e, ++0x1c,0x18,0x10,0x18,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0xbb,0x01,0x0c,0xe5,0x82,0x29,0xf5,0x82,0xe5,0x83,0x3a,0xf5,0x83,0xe0,0x22,0x50, ++0x06,0xe9,0x25,0x82,0xf8,0xe6,0x22,0xbb,0xfe,0x06,0xe9,0x25,0x82,0xf8,0xe2,0x22, ++0xe5,0x82,0x29,0xf5,0x82,0xe5,0x83,0x3a,0xf5,0x83,0xe4,0x93,0x22,0xbb,0x01,0x06, ++0x89,0x82,0x8a,0x83,0xf0,0x22,0x50,0x02,0xf7,0x22,0xbb,0xfe,0x01,0xf3,0x22,0xf8, ++0xbb,0x01,0x0d,0xe5,0x82,0x29,0xf5,0x82,0xe5,0x83,0x3a,0xf5,0x83,0xe8,0xf0,0x22, ++0x50,0x06,0xe9,0x25,0x82,0xc8,0xf6,0x22,0xbb,0xfe,0x05,0xe9,0x25,0x82,0xc8,0xf2, ++0x22,0xc5,0xf0,0xf8,0xa3,0xe0,0x28,0xf0,0xc5,0xf0,0xf8,0xe5,0x82,0x15,0x82,0x70, ++0x02,0x15,0x83,0xe0,0x38,0xf0,0x22,0xbb,0x01,0x0a,0x89,0x82,0x8a,0x83,0xe0,0xf5, ++0xf0,0xa3,0xe0,0x22,0x50,0x06,0x87,0xf0,0x09,0xe7,0x19,0x22,0xbb,0xfe,0x07,0xe3, ++0xf5,0xf0,0x09,0xe3,0x19,0x22,0x89,0x82,0x8a,0x83,0xe4,0x93,0xf5,0xf0,0x74,0x01, ++0x93,0x22,0xbb,0x01,0x10,0xe5,0x82,0x29,0xf5,0x82,0xe5,0x83,0x3a,0xf5,0x83,0xe0, ++0xf5,0xf0,0xa3,0xe0,0x22,0x50,0x09,0xe9,0x25,0x82,0xf8,0x86,0xf0,0x08,0xe6,0x22, ++0xbb,0xfe,0x0a,0xe9,0x25,0x82,0xf8,0xe2,0xf5,0xf0,0x08,0xe2,0x22,0xe5,0x83,0x2a, ++0xf5,0x83,0xe9,0x93,0xf5,0xf0,0xa3,0xe9,0x93,0x22,0xbb,0x01,0x0a,0x89,0x82,0x8a, ++0x83,0xf0,0xe5,0xf0,0xa3,0xf0,0x22,0x50,0x06,0xf7,0x09,0xa7,0xf0,0x19,0x22,0xbb, ++0xfe,0x06,0xf3,0xe5,0xf0,0x09,0xf3,0x19,0x22,0xf8,0xbb,0x01,0x11,0xe5,0x82,0x29, ++0xf5,0x82,0xe5,0x83,0x3a,0xf5,0x83,0xe8,0xf0,0xe5,0xf0,0xa3,0xf0,0x22,0x50,0x09, ++0xe9,0x25,0x82,0xc8,0xf6,0x08,0xa6,0xf0,0x22,0xbb,0xfe,0x09,0xe9,0x25,0x82,0xc8, ++0xf2,0xe5,0xf0,0x08,0xf2,0x22,0xef,0x4b,0xff,0xee,0x4a,0xfe,0xed,0x49,0xfd,0xec, ++0x48,0xfc,0x22,0xe0,0xfc,0xa3,0xe0,0xfd,0xa3,0xe0,0xfe,0xa3,0xe0,0xff,0x22,0xa4, ++0x25,0x82,0xf5,0x82,0xe5,0xf0,0x35,0x83,0xf5,0x83,0x22,0xe0,0xfb,0xa3,0xe0,0xfa, ++0xa3,0xe0,0xf9,0x22,0xf8,0xe0,0xfb,0xa3,0xa3,0xe0,0xf9,0x25,0xf0,0xf0,0xe5,0x82, ++0x15,0x82,0x70,0x02,0x15,0x83,0xe0,0xfa,0x38,0xf0,0x22,0xeb,0xf0,0xa3,0xea,0xf0, ++0xa3,0xe9,0xf0,0x22,0xd0,0x83,0xd0,0x82,0xf8,0xe4,0x93,0x70,0x12,0x74,0x01,0x93, ++0x70,0x0d,0xa3,0xa3,0x93,0xf8,0x74,0x01,0x93,0xf5,0x82,0x88,0x83,0xe4,0x73,0x74, ++0x02,0x93,0x68,0x60,0xef,0xa3,0xa3,0xa3,0x80,0xdf,0x02,0x43,0xf8,0x02,0x50,0x2e, ++0xe4,0x93,0xa3,0xf8,0xe4,0x93,0xa3,0x40,0x03,0xf6,0x80,0x01,0xf2,0x08,0xdf,0xf4, ++0x80,0x29,0xe4,0x93,0xa3,0xf8,0x54,0x07,0x24,0x0c,0xc8,0xc3,0x33,0xc4,0x54,0x0f, ++0x44,0x20,0xc8,0x83,0x40,0x04,0xf4,0x56,0x80,0x01,0x46,0xf6,0xdf,0xe4,0x80,0x0b, ++0x01,0x02,0x04,0x08,0x10,0x20,0x40,0x80,0x90,0x44,0x3d,0xe4,0x7e,0x01,0x93,0x60, ++0xbc,0xa3,0xff,0x54,0x3f,0x30,0xe5,0x09,0x54,0x1f,0xfe,0xe4,0x93,0xa3,0x60,0x01, ++0x0e,0xcf,0x54,0xc0,0x25,0xe0,0x60,0xa8,0x40,0xb8,0xe4,0x93,0xa3,0xfa,0xe4,0x93, ++0xa3,0xf8,0xe4,0x93,0xa3,0xc8,0xc5,0x82,0xc8,0xca,0xc5,0x83,0xca,0xf0,0xa3,0xc8, ++0xc5,0x82,0xc8,0xca,0xc5,0x83,0xca,0xdf,0xe9,0xde,0xe7,0x80,0xbe,0x41,0x9e,0x4f, ++0x00,0x41,0x9e,0xad,0x00,0x41,0x9e,0x61,0x80,0x41,0x9e,0x62,0x80,0x41,0x9e,0xaf, ++0x00,0x00,0xf0,0x90,0x9e,0x6b,0xe0,0x90,0x9e,0x87,0xf0,0xe4,0xfb,0xfd,0x7f,0x54, ++0x7e,0x01,0xd3,0x10,0xaf,0x01,0xc3,0xc0,0xd0,0x90,0x9e,0x85,0xeb,0xf0,0xa3,0xe0, ++0xfb,0xa3,0xe0,0xf5,0x44,0xe4,0xf5,0x45,0x12,0x35,0xab,0xd0,0xd0,0x92,0xaf,0x22, ++0x90,0x01,0x5f,0xe4,0xf0,0x90,0x01,0x3c,0x74,0x08,0xf0,0xe4,0x90,0x9e,0x86,0xf0, ++0x90,0x9e,0x69,0xe0,0x90,0x9e,0x87,0xf0,0xe4,0xfb,0xfd,0x7f,0x5c,0x7e,0x01,0x91, ++0x62,0x90,0x01,0x5f,0x74,0x05,0xf0,0x90,0x06,0x92,0x74,0x02,0xf0,0x90,0x9e,0x70, ++0x14,0xf0,0xe5,0x23,0x54,0x0f,0xc3,0x94,0x0c,0x50,0x02,0xf1,0x2b,0x22,0x8f,0x82, ++0x8e,0x83,0xa3,0xa3,0xa3,0xe4,0xf0,0x22,0xe4,0xf5,0x71,0x7f,0x60,0x7e,0x01,0x80, ++0xed,0x7d,0x01,0xaf,0x24,0xe1,0x2f,0xb1,0xa6,0xbf,0x01,0x0f,0x90,0x9e,0x51,0xe0, ++0xff,0xe4,0xfd,0xf1,0xd0,0x90,0x04,0x1f,0x74,0x20,0xf0,0x22,0x53,0x23,0xf0,0x43, ++0x23,0x01,0x91,0xfd,0x91,0xfe,0x53,0x23,0xf0,0x43,0x23,0x02,0x22,0x22,0x22,0x22, ++0x22,0x00,0x00,0x02,0x5f,0x91,0x02,0x5f,0x98,0xd3,0x10,0xaf,0x01,0xc3,0xc0,0xd0, ++0x8b,0x1b,0x8a,0x1c,0x89,0x1d,0x90,0x9e,0x88,0x71,0x8b,0xab,0x1e,0xaa,0x1f,0xa9, ++0x20,0x90,0x9e,0x8b,0x71,0x8b,0xaf,0x21,0x15,0x21,0xef,0x60,0x1b,0x90,0x9e,0x8b, ++0xe4,0x75,0xf0,0x01,0x71,0x74,0x12,0x29,0xd9,0xff,0x90,0x9e,0x88,0xe4,0x75,0xf0, ++0x01,0x71,0x74,0xef,0x51,0x4d,0x80,0xde,0xab,0x1b,0xaa,0x1c,0xa9,0x1d,0xd0,0xd0, ++0x92,0xaf,0x22,0x90,0x06,0xa9,0xe0,0x90,0x9e,0x2f,0xf0,0xe0,0x54,0xc0,0x70,0x08, ++0x53,0x26,0xfe,0x53,0x26,0xfd,0x91,0xd1,0x90,0x9e,0x2f,0xe0,0x30,0xe6,0x13,0x43, ++0x26,0x01,0x90,0x9e,0x73,0xe0,0x64,0x02,0x60,0x04,0x91,0xd7,0x80,0x07,0x91,0x80, ++0x80,0x03,0x53,0x26,0xfe,0x90,0x9e,0x2f,0xe0,0x30,0xe7,0x16,0x43,0x26,0x02,0xe4, ++0x90,0x9e,0x86,0x91,0x52,0x90,0x01,0x57,0x74,0x05,0xf0,0x90,0x9e,0x74,0x74,0x01, ++0xf0,0x22,0x53,0x26,0xfd,0x22,0xd3,0x10,0xaf,0x01,0xc3,0xc0,0xd0,0x90,0x04,0x1d, ++0xe0,0x60,0x1a,0x90,0x05,0x22,0xe0,0x54,0x90,0x60,0x07,0x90,0x01,0xc6,0xe0,0x44, ++0x40,0xf0,0x90,0x01,0xc7,0xe0,0x30,0xe1,0xe4,0x7f,0x00,0x80,0x02,0x7f,0x01,0xd0, ++0xd0,0x92,0xaf,0x22,0xc0,0xe0,0xc0,0xf0,0xc0,0x83,0xc0,0x82,0xc0,0xd0,0x75,0xd0, ++0x00,0xc0,0x00,0xc0,0x01,0xc0,0x02,0xc0,0x03,0xc0,0x04,0xc0,0x05,0xc0,0x06,0xc0, ++0x07,0x90,0x01,0xc4,0x74,0xd4,0xf0,0x74,0x45,0xa3,0xf0,0x53,0x91,0xdf,0x90,0x01, ++0x3c,0xe0,0x55,0x30,0xf5,0x34,0xa3,0xe0,0x55,0x31,0xf5,0x35,0xa3,0xe0,0x55,0x32, ++0xf5,0x36,0xa3,0xe0,0x55,0x33,0xf5,0x37,0xe5,0x34,0x30,0xe0,0x06,0x90,0x01,0x3c, ++0x74,0x01,0xf0,0xe5,0x34,0x30,0xe1,0x09,0x90,0x01,0x3c,0x74,0x02,0xf0,0x12,0x65, ++0xf6,0xe5,0x34,0x30,0xe2,0x38,0x90,0x01,0x3c,0x74,0x04,0xf0,0x90,0x06,0x92,0xe0, ++0x30,0xe0,0x24,0x90,0x9e,0x86,0xe4,0xf0,0x90,0x9e,0x69,0xe0,0x90,0x9e,0x87,0xf0, ++0xe4,0xfb,0xfd,0x7f,0x58,0x7e,0x01,0x91,0x62,0x90,0x01,0x5b,0x74,0x05,0xf0,0x90, ++0x06,0x92,0x74,0x01,0xf0,0x80,0x07,0x90,0x9e,0x71,0xe4,0xf0,0x91,0xd1,0xe5,0x34, ++0x30,0xe3,0x38,0x90,0x01,0x3c,0x74,0x08,0xf0,0x90,0x06,0x92,0xe0,0x30,0xe1,0x24, ++0x90,0x9e,0x86,0xe4,0xf0,0x90,0x9e,0x69,0xe0,0x90,0x9e,0x87,0xf0,0xe4,0xfb,0xfd, ++0x7f,0x5c,0x7e,0x01,0x91,0x62,0x90,0x01,0x5f,0x74,0x05,0xf0,0x90,0x06,0x92,0x74, ++0x02,0xf0,0x80,0x07,0x90,0x9e,0x70,0xe4,0xf0,0x91,0xd1,0xe5,0x34,0x30,0xe4,0x09, ++0x90,0x01,0x3c,0x74,0x10,0xf0,0x12,0x73,0x53,0xe5,0x34,0x30,0xe5,0x09,0x90,0x01, ++0x3c,0x74,0x20,0xf0,0x12,0x52,0x64,0xe5,0x35,0x30,0xe0,0x18,0x90,0x01,0x3d,0x74, ++0x01,0xf0,0x90,0x01,0x2f,0xe0,0x44,0x7f,0xf0,0x90,0x00,0x83,0xe0,0xf5,0x24,0x12, ++0x64,0xd0,0x91,0xd1,0xe5,0x35,0x30,0xe2,0x06,0x90,0x01,0x3d,0x74,0x04,0xf0,0xe5, ++0x36,0x30,0xe0,0x06,0x90,0x01,0x3e,0x74,0x01,0xf0,0xe5,0x36,0x30,0xe1,0x06,0x90, ++0x01,0x3e,0x74,0x02,0xf0,0x74,0xd4,0x04,0x90,0x01,0xc4,0xf0,0x74,0x45,0xa3,0xf0, ++0xd0,0x07,0xd0,0x06,0xd0,0x05,0xd0,0x04,0xd0,0x03,0xd0,0x02,0xd0,0x01,0xd0,0x00, ++0xd0,0xd0,0xd0,0x82,0xd0,0x83,0xd0,0xf0,0xd0,0xe0,0x32,0x7d,0x01,0x7f,0x0c,0x90, ++0x9e,0xa6,0xed,0xf0,0x90,0x9e,0xa5,0xef,0xf0,0x54,0x0f,0xff,0xe5,0x23,0x54,0x0f, ++0x6f,0x60,0x70,0x90,0x9e,0xa5,0xe0,0x30,0xe2,0x2a,0xe5,0x23,0x20,0xe2,0x05,0x7f, ++0x01,0x12,0x63,0xea,0xe5,0x23,0x30,0xe3,0x09,0x90,0x9e,0xa5,0xe0,0x20,0xe3,0x02, ++0x80,0x52,0xe5,0x23,0x20,0xe3,0x4c,0x90,0x9e,0xa5,0xe0,0x30,0xe3,0x45,0xa3,0xe0, ++0xff,0x02,0x5e,0x95,0xe5,0x23,0x54,0x0f,0xff,0xbf,0x0c,0x0f,0x90,0x9e,0xa5,0xe0, ++0x20,0xe3,0x08,0x12,0x62,0xce,0xef,0x60,0x2a,0xf1,0xb4,0xe5,0x23,0x54,0x0f,0xff, ++0xbf,0x04,0x10,0x90,0x9e,0xa5,0xe0,0x20,0xe2,0x09,0x12,0x63,0x17,0xef,0x60,0x13, ++0x12,0x61,0x3a,0xe5,0x23,0x54,0x0f,0xff,0xbf,0x02,0x08,0x12,0x63,0x7a,0xef,0x60, ++0x02,0x91,0xec,0x22,0x90,0x06,0x04,0xe0,0x44,0x40,0xf0,0xe5,0x22,0xb4,0x01,0x05, ++0x7f,0x01,0x12,0x5e,0x5c,0x53,0x23,0xf0,0x43,0x23,0x04,0x22,0xe0,0xff,0x7d,0x01, ++0x90,0x9e,0x99,0xef,0xf0,0xa3,0xed,0xf0,0xe4,0xa3,0xf0,0xa3,0xf0,0xe5,0x25,0x60, ++0x05,0xe4,0xff,0x12,0x61,0x1f,0x90,0x9e,0x99,0xe0,0x30,0xe0,0x09,0x90,0x9e,0x9b, ++0xe4,0xf0,0xa3,0x74,0x80,0xf0,0x90,0x9e,0x99,0xe0,0xff,0xc3,0x13,0x90,0xfd,0x10, ++0xf0,0x90,0x04,0x25,0xef,0xf0,0x90,0x9e,0x9a,0xe0,0x60,0x1f,0xa3,0xa3,0xe0,0xff, ++0x24,0x0f,0xf5,0x82,0xe4,0x34,0xfc,0xf5,0x83,0xe0,0x44,0x80,0xf0,0x74,0x10,0x2f, ++0xf5,0x82,0xe4,0x34,0xfc,0xf5,0x83,0xe0,0x44,0x80,0xf0,0x90,0x9e,0x9b,0xa3,0xe0, ++0xff,0xfd,0x24,0x08,0xf5,0x82,0xe4,0x34,0xfc,0xf5,0x83,0xe4,0xf0,0x74,0x09,0x2d, ++0xf5,0x82,0xe4,0x34,0xfc,0xf5,0x83,0xe0,0x54,0xf0,0xf0,0x74,0x21,0x2f,0xf5,0x82, ++0xe4,0x34,0xfc,0xf5,0x83,0xe0,0x54,0xf7,0xf0,0x90,0x9e,0x9b,0xe0,0xfe,0xa3,0xe0, ++0xff,0x22,0x12,0x45,0xa6,0xbf,0x01,0x10,0x90,0x02,0x09,0xe0,0xff,0x7d,0x01,0x12, ++0x47,0xd0,0x90,0x04,0x1f,0x74,0x20,0xf0,0x22,0xc0,0xe0,0xc0,0xf0,0xc0,0x83,0xc0, ++0x82,0xc0,0xd0,0x75,0xd0,0x00,0xc0,0x00,0xc0,0x01,0xc0,0x02,0xc0,0x03,0xc0,0x04, ++0xc0,0x05,0xc0,0x06,0xc0,0x07,0x90,0x01,0xc4,0x74,0x79,0xf0,0x74,0x48,0xa3,0xf0, ++0x90,0x01,0x34,0xe0,0x55,0x28,0xf5,0x2c,0x90,0x01,0x36,0xe0,0x55,0x2a,0xf5,0x2e, ++0xa3,0xe0,0x55,0x2b,0xf5,0x2f,0xe5,0x2c,0x20,0xe0,0x02,0x41,0x17,0x90,0x01,0x34, ++0x74,0x01,0xf0,0x85,0xd1,0x08,0x85,0xd2,0x09,0x85,0xd3,0x0a,0x85,0xd4,0x0b,0x85, ++0xd5,0x0c,0x85,0xd6,0x0d,0x85,0xd7,0x0e,0x85,0xd9,0x0f,0xe5,0x0f,0x54,0x40,0xc3, ++0x13,0xff,0xe5,0x0e,0x54,0x20,0x6f,0x70,0x02,0x21,0xc9,0xe5,0x0f,0x30,0xe5,0x02, ++0x21,0xc9,0xe5,0x0d,0x54,0x3f,0xf5,0x4d,0xe5,0x08,0x54,0x3f,0xf5,0x4e,0xe5,0x0c, ++0x54,0x1f,0xff,0xe5,0x4d,0x25,0xe0,0x24,0xc4,0xf5,0x82,0xe4,0x34,0x99,0xf5,0x83, ++0xe4,0x8f,0xf0,0x12,0x42,0x81,0xe5,0x0e,0x54,0x1f,0xff,0xe5,0x4d,0x25,0xe0,0x24, ++0x80,0xf5,0x82,0xe4,0x34,0x93,0xf5,0x83,0xe4,0x8f,0xf0,0x12,0x42,0x81,0xe5,0x4e, ++0xd3,0x94,0x04,0x40,0x03,0x75,0x4e,0x04,0x75,0xf0,0x0a,0xe5,0x4d,0x90,0x90,0x00, ++0x12,0x43,0x5f,0x75,0xf0,0x02,0xe5,0x4e,0x12,0x43,0x5f,0xe0,0xfe,0xa3,0xe0,0xff, ++0xe5,0x0e,0x54,0x1f,0x2f,0xff,0xe4,0x3e,0xfe,0x75,0xf0,0x0a,0xe5,0x4d,0x90,0x90, ++0x00,0x12,0x43,0x5f,0x75,0xf0,0x02,0xe5,0x4e,0x12,0x43,0x5f,0xee,0xf0,0xa3,0xef, ++0xf0,0xe5,0x0f,0x20,0xe6,0x24,0xe5,0x0e,0x54,0x1f,0xff,0xe5,0x4d,0x25,0xe0,0x24, ++0xc4,0xf5,0x82,0xe4,0x34,0x98,0xf5,0x83,0xe4,0x8f,0xf0,0x12,0x42,0x81,0xe5,0x0a, ++0x30,0xe7,0x36,0xaf,0x4d,0x12,0x5b,0x68,0x80,0x2f,0xe5,0x0e,0x54,0x1f,0xff,0xe5, ++0x4d,0x25,0xe0,0x24,0x44,0xf5,0x82,0xe4,0x34,0x99,0xf5,0x83,0xe4,0x8f,0xf0,0x12, ++0x42,0x81,0xe5,0x0a,0x30,0xe7,0x12,0xe5,0x0a,0x54,0x7f,0xfd,0xe5,0x0e,0x54,0x1f, ++0xf5,0x53,0xab,0x4e,0xaf,0x4d,0x12,0x5b,0x05,0xe5,0x25,0x14,0x24,0xfd,0x50,0x02, ++0x80,0x45,0x90,0x9e,0x73,0xe0,0x60,0x37,0x90,0x01,0x5b,0xe4,0xf0,0x90,0x01,0x3c, ++0x74,0x04,0xf0,0x71,0xc4,0xef,0x64,0x01,0x70,0x2d,0x90,0x9e,0x69,0xe0,0xf5,0x44, ++0x75,0x45,0x00,0xe4,0xfb,0xfd,0x7f,0x58,0x7e,0x01,0x12,0x35,0xab,0x90,0x01,0x5b, ++0x74,0x05,0xf0,0x90,0x06,0x92,0x74,0x01,0xf0,0x90,0x9e,0x71,0xf0,0x80,0x08,0x71, ++0xc4,0xbf,0x01,0x03,0x12,0x44,0xd1,0xe5,0x2c,0x30,0xe1,0x21,0x90,0x01,0x34,0x74, ++0x02,0xf0,0x85,0xd1,0x13,0x85,0xd2,0x14,0x85,0xd3,0x15,0x85,0xd4,0x16,0x85,0xd5, ++0x17,0x85,0xd6,0x18,0x85,0xd7,0x19,0x85,0xd9,0x1a,0x12,0x5c,0x46,0xe5,0x2c,0x30, ++0xe3,0x06,0x90,0x01,0x34,0x74,0x08,0xf0,0xe5,0x2c,0x30,0xe4,0x09,0x90,0x01,0x34, ++0x74,0x10,0xf0,0x43,0x12,0x10,0xe5,0x2c,0x30,0xe5,0x24,0x90,0x01,0xcf,0xe0,0x30, ++0xe5,0x1d,0xe0,0x54,0xdf,0xf0,0x90,0x01,0x34,0x74,0x20,0xf0,0x75,0xa8,0x00,0x75, ++0xe8,0x00,0xd1,0xdb,0x90,0x00,0x03,0xe0,0x54,0xfb,0xf0,0x71,0xdb,0x80,0xfe,0xe5, ++0x2c,0x30,0xe6,0x06,0x90,0x01,0x34,0x74,0x40,0xf0,0xe5,0x2e,0x30,0xe0,0x12,0x90, ++0x9e,0x5f,0x74,0x01,0xf0,0x90,0x01,0x36,0xf0,0x12,0x65,0x90,0x90,0x9e,0x5f,0xe4, ++0xf0,0xe5,0x2e,0x30,0xe1,0x3b,0x90,0x01,0x36,0x74,0x02,0xf0,0x43,0x12,0x40,0x90, ++0x01,0x02,0xe0,0x54,0x03,0x64,0x01,0x70,0x28,0x90,0x01,0x37,0xe0,0x30,0xe0,0x0a, ++0x74,0x01,0xf0,0x90,0x9e,0x4f,0xe4,0xf0,0x80,0x17,0x90,0x9e,0x4f,0xe0,0x04,0xf0, ++0xe0,0xc3,0x94,0x0a,0x40,0x0b,0xe4,0xf0,0x90,0x04,0x19,0xe0,0x30,0xe0,0x02,0x11, ++0x62,0xe5,0x2e,0x30,0xe2,0x09,0x90,0x01,0x36,0x74,0x04,0xf0,0x12,0x65,0x28,0xe5, ++0x2e,0x30,0xe3,0x28,0x90,0x01,0x36,0x74,0x08,0xf0,0xe5,0x22,0x64,0x01,0x70,0x1c, ++0xe5,0x25,0x60,0x18,0x90,0x01,0x57,0xe4,0xf0,0x90,0x01,0x3c,0x74,0x02,0xf0,0x90, ++0x9e,0x86,0xe4,0x12,0x44,0x52,0x90,0x01,0x57,0x74,0x05,0xf0,0xe5,0x2e,0x30,0xe4, ++0x2b,0x90,0x01,0x36,0x74,0x10,0xf0,0xe5,0x22,0xb4,0x01,0x20,0xe5,0x25,0x60,0x1c, ++0x90,0x01,0x57,0xe4,0xf0,0x90,0x01,0x3c,0x74,0x02,0xf0,0x90,0x9e,0x74,0xe4,0xf0, ++0x53,0x26,0xfd,0xe5,0x26,0x54,0x07,0x70,0x03,0x12,0x44,0xd1,0xe5,0x2e,0x30,0xe5, ++0x1f,0x90,0x01,0x36,0x74,0x20,0xf0,0xe5,0x22,0xb4,0x01,0x14,0xe5,0x25,0x60,0x10, ++0x90,0x9e,0x73,0xe0,0x64,0x02,0x60,0x05,0x12,0x44,0xd7,0x80,0x03,0x12,0x44,0x80, ++0xe5,0x2e,0x30,0xe6,0x1b,0x90,0x01,0x36,0x74,0x40,0xf0,0xe5,0x22,0xb4,0x01,0x10, ++0xe5,0x25,0x60,0x0c,0x53,0x26,0xfe,0xe5,0x26,0x54,0x07,0x70,0x03,0x12,0x44,0xd1, ++0xe5,0x2f,0x30,0xe1,0x09,0x90,0x01,0x37,0x74,0x02,0xf0,0x12,0x61,0x92,0x74,0x79, ++0x04,0x90,0x01,0xc4,0xf0,0x74,0x48,0xa3,0xf0,0xd0,0x07,0xd0,0x06,0xd0,0x05,0xd0, ++0x04,0xd0,0x03,0xd0,0x02,0xd0,0x01,0xd0,0x00,0xd0,0xd0,0xd0,0x82,0xd0,0x83,0xd0, ++0xf0,0xd0,0xe0,0x32,0x90,0x04,0x1b,0xe0,0x54,0x7f,0x64,0x7f,0x7f,0x01,0x60,0x02, ++0x7f,0x00,0x22,0xf4,0xff,0x90,0x00,0x43,0xe0,0x5f,0xf0,0xd3,0x10,0xaf,0x01,0xc3, ++0xc0,0xd0,0x7f,0x10,0xdf,0xfe,0xd0,0xd0,0x92,0xaf,0x22,0xd3,0x10,0xaf,0x01,0xc3, ++0xc0,0xd0,0x90,0x9e,0xac,0xed,0xf0,0x90,0x9e,0xab,0xef,0xf0,0xd3,0x94,0x07,0x50, ++0x63,0xe0,0xff,0x74,0x01,0xa8,0x07,0x08,0x80,0x02,0xc3,0x33,0xd8,0xfc,0xf4,0xff, ++0x90,0x00,0x47,0xe0,0x5f,0xf0,0x71,0xdb,0x90,0x9e,0xab,0xe0,0xff,0x74,0x01,0xa8, ++0x07,0x08,0x80,0x02,0xc3,0x33,0xd8,0xfc,0xff,0x90,0x00,0x46,0xe0,0x4f,0xf0,0x71, ++0xdb,0x90,0x9e,0xac,0xe0,0x60,0x16,0x90,0x9e,0xab,0xe0,0xff,0x74,0x01,0xa8,0x07, ++0x08,0x80,0x02,0xc3,0x33,0xd8,0xfc,0xff,0x90,0x00,0x45,0x80,0x66,0x90,0x9e,0xab, ++0xe0,0xff,0x74,0x01,0xa8,0x07,0x08,0x80,0x02,0xc3,0x33,0xd8,0xfc,0xf4,0xff,0x90, ++0x00,0x45,0x80,0x6b,0x90,0x9e,0xab,0xe0,0x24,0xf8,0xf0,0xe0,0xff,0x74,0x01,0xa8, ++0x07,0x08,0x80,0x02,0xc3,0x33,0xd8,0xfc,0xc4,0x54,0xf0,0x71,0xd3,0x90,0x9e,0xab, ++0xe0,0xff,0x74,0x01,0xa8,0x07,0x08,0x80,0x02,0xc3,0x33,0xd8,0xfc,0xff,0x90,0x00, ++0x43,0xe0,0x4f,0xf0,0x71,0xdb,0x90,0x9e,0xac,0xe0,0x60,0x1b,0x90,0x9e,0xab,0xe0, ++0xff,0x74,0x01,0xa8,0x07,0x08,0x80,0x02,0xc3,0x33,0xd8,0xfc,0xc4,0x54,0xf0,0xff, ++0x90,0x00,0x42,0xe0,0x4f,0x80,0x1a,0x90,0x9e,0xab,0xe0,0xff,0x74,0x01,0xa8,0x07, ++0x08,0x80,0x02,0xc3,0x33,0xd8,0xfc,0xc4,0x54,0xf0,0xf4,0xff,0x90,0x00,0x42,0xe0, ++0x5f,0xf0,0x71,0xdb,0xd0,0xd0,0x92,0xaf,0x22,0xf0,0x90,0x00,0x45,0xe0,0x54,0xfe, ++0xfd,0x7f,0x45,0xd3,0x10,0xaf,0x01,0xc3,0xc0,0xd0,0x8f,0x82,0x75,0x83,0x00,0xed, ++0xf0,0x71,0xdb,0xd0,0xd0,0x92,0xaf,0x22,0xef,0x14,0x60,0x30,0x14,0x60,0x66,0x24, ++0x02,0x60,0x02,0xa1,0x9f,0x90,0x9e,0x1a,0x74,0x02,0xf0,0x90,0x00,0x48,0xe0,0x44, ++0x0c,0xfd,0x7f,0x48,0x91,0xe3,0x90,0x00,0x47,0xe0,0x44,0x08,0xfd,0x7f,0x47,0x91, ++0xe3,0x90,0x00,0x45,0xe0,0x44,0x10,0xfd,0x7f,0x45,0x80,0x71,0xe4,0x90,0x9e,0x1a, ++0xf0,0x90,0x9e,0x16,0x12,0x43,0x53,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0x80,0x7e, ++0x08,0x12,0x2f,0xd9,0x90,0x00,0x45,0xe0,0x44,0xef,0xfd,0x7f,0x45,0x91,0xe3,0x90, ++0x00,0x45,0xe0,0x54,0xef,0xfd,0x7f,0x45,0x91,0xe3,0x90,0x00,0x46,0xe0,0x44,0x10, ++0xfd,0x7f,0x46,0x80,0x38,0x90,0x9e,0x1a,0x74,0x01,0xf0,0x90,0x9e,0x20,0x12,0x43, ++0x53,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0x80,0x7e,0x08,0x12,0x2f,0xd9,0x90,0x00, ++0x45,0xe0,0x44,0x20,0xfd,0x7f,0x45,0x91,0xe3,0x90,0x00,0x45,0xe0,0x44,0x10,0xfd, ++0x7f,0x45,0x91,0xe3,0x90,0x00,0x46,0xe0,0x44,0x10,0xfd,0x7f,0x46,0x91,0xe3,0x22, ++0x90,0x00,0x02,0x12,0x42,0x20,0x90,0x9e,0x1c,0xf0,0x90,0x00,0x01,0x12,0x42,0x20, ++0x25,0xe0,0x25,0xe0,0x90,0x9e,0x1b,0xf0,0x12,0x29,0xd9,0x25,0xe0,0x25,0xe0,0x90, ++0x9e,0x1f,0xf0,0x90,0x05,0x60,0xe0,0x90,0x9e,0x2a,0xf0,0x90,0x05,0x61,0xe0,0x90, ++0x9e,0x2b,0xf0,0x90,0x05,0x62,0xe0,0x90,0x9e,0x2c,0xf0,0x90,0x05,0x63,0xe0,0x90, ++0x9e,0x2d,0xf0,0xa2,0xaf,0xe4,0x33,0x90,0x9e,0x3f,0xf0,0xc2,0xaf,0x90,0x9e,0x1b, ++0xe0,0xff,0x12,0x52,0x12,0x90,0x9e,0x3f,0xe0,0x24,0xff,0x92,0xaf,0x90,0x9e,0x1c, ++0xe0,0x70,0x02,0xc1,0xa7,0x90,0x9e,0x1b,0xe0,0x70,0x02,0xc1,0xa7,0x90,0x9e,0x1f, ++0xe0,0x70,0x02,0xc1,0xa7,0xa2,0xaf,0xe4,0x33,0x90,0x9e,0x3f,0xf0,0xc2,0xaf,0x90, ++0x9e,0x2e,0x74,0x01,0xf0,0x90,0x9e,0x3f,0xe0,0x24,0xff,0x92,0xaf,0x91,0xda,0x90, ++0x00,0x46,0xe0,0x44,0x01,0xfd,0x7f,0x46,0x91,0xe3,0x90,0x9e,0x14,0xe0,0x60,0x15, ++0x90,0x9e,0x20,0x12,0x43,0x53,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0x80,0x7e,0x08, ++0x12,0x2f,0xd9,0x80,0x06,0x90,0x05,0x22,0x74,0x7f,0xf0,0x90,0x00,0x45,0xe0,0x54, ++0xef,0xfd,0x7f,0x45,0x91,0xe3,0x90,0x05,0x87,0xe0,0x64,0x80,0xf0,0x90,0x9e,0x2a, ++0xe0,0x90,0x05,0x84,0xf0,0x90,0x9e,0x2b,0xe0,0x90,0x05,0x85,0xf0,0x90,0x9e,0x2c, ++0xe0,0x90,0x05,0x86,0xf0,0x90,0x9e,0x2d,0xe0,0x90,0x05,0x87,0xf0,0xa2,0xaf,0xe4, ++0x33,0x90,0x9e,0x3f,0xf0,0xc2,0xaf,0x90,0x01,0x3c,0xe0,0x44,0x20,0xf0,0x7d,0x20, ++0xe4,0xff,0x12,0x37,0x00,0x80,0x2b,0x90,0x9e,0x1c,0xe0,0x70,0x2d,0x90,0x9e,0x2e, ++0x91,0xd9,0x90,0x00,0x46,0xe0,0x54,0xfe,0xfd,0x7f,0x46,0x91,0xe3,0x90,0x05,0x22, ++0xe4,0xf0,0xa2,0xaf,0x33,0x90,0x9e,0x3f,0xf0,0xc2,0xaf,0x7d,0x20,0xe4,0xff,0x12, ++0x36,0x92,0x90,0x9e,0x3f,0xe0,0x24,0xff,0x92,0xaf,0x22,0x90,0x01,0x30,0xe4,0xf0, ++0xa3,0xf0,0xa3,0xf0,0xa3,0xf0,0x90,0x01,0x38,0xf0,0xa3,0xf0,0xa3,0xf0,0xa3,0xf0, ++0xfd,0x7f,0x50,0x91,0xe3,0xe4,0xfd,0x7f,0x51,0x91,0xe3,0xe4,0xfd,0x7f,0x52,0x91, ++0xe3,0xe4,0xfd,0x7f,0x53,0x81,0xe3,0x8b,0x59,0x8a,0x5a,0x89,0x5b,0x90,0x00,0x02, ++0x12,0x42,0x20,0x90,0x9e,0x1d,0xf0,0xe0,0x30,0xe0,0x4b,0x90,0x9e,0x14,0x74,0x01, ++0xf0,0x7f,0x80,0x7e,0x08,0x12,0x27,0xde,0x90,0x9e,0x16,0x12,0x2a,0x7f,0xab,0x59, ++0xaa,0x5a,0xa9,0x5b,0x90,0x00,0x01,0x12,0x42,0x20,0xff,0xe4,0xfc,0xfd,0xfe,0x78, ++0x1a,0x12,0x2a,0x6c,0xa8,0x04,0xa9,0x05,0xaa,0x06,0xab,0x07,0x90,0x9e,0x16,0x12, ++0x43,0x53,0xec,0x54,0x03,0xfc,0x12,0x43,0x46,0x90,0x9e,0x20,0x12,0x2a,0x7f,0x90, ++0x05,0x22,0xe4,0xf0,0x80,0x2d,0xe4,0x90,0x9e,0x14,0xf0,0x7f,0x80,0x7e,0x08,0x12, ++0x27,0xde,0xec,0x54,0x03,0xfc,0xec,0x44,0xc0,0xfc,0x90,0x9e,0x16,0x12,0x2a,0x7f, ++0x90,0x9e,0x16,0x12,0x43,0x53,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0x80,0x7e,0x08, ++0x12,0x2f,0xd9,0x90,0x9e,0x1d,0xe0,0x30,0xe1,0x19,0x7d,0x0c,0x7f,0x47,0x91,0xe3, ++0x90,0x00,0x48,0xe0,0x44,0x0c,0xfd,0x7f,0x48,0x91,0xe3,0x90,0x00,0x46,0xe0,0x44, ++0x10,0x80,0x1c,0x90,0x00,0x47,0xe0,0x54,0xf3,0xfd,0x7f,0x47,0x91,0xe3,0x90,0x00, ++0x48,0xe0,0x54,0xf3,0xfd,0x7f,0x48,0x91,0xe3,0x90,0x00,0x46,0xe0,0x54,0xef,0xfd, ++0x7f,0x46,0x91,0xe3,0xe4,0x90,0x9e,0x1a,0xf0,0x22,0x90,0x00,0x49,0xe0,0x90,0x9e, ++0xb0,0xf0,0xe0,0x54,0x0f,0xf0,0x44,0xf0,0xfd,0x7f,0x49,0x91,0xe3,0x90,0x9e,0xb0, ++0xe0,0x44,0xb0,0xfd,0x7f,0x49,0x81,0xe3,0x75,0x28,0x33,0xe4,0xf5,0x29,0x75,0x2a, ++0x07,0xf5,0x2b,0x90,0x01,0x30,0xe5,0x28,0xf0,0xa3,0xe5,0x29,0xf0,0xa3,0xe5,0x2a, ++0xf0,0xa3,0xe5,0x2b,0xf0,0x22,0x75,0x30,0x1f,0x75,0x31,0x01,0xe4,0xf5,0x32,0x90, ++0x01,0x38,0xe5,0x30,0xf0,0xa3,0xe5,0x31,0xf0,0xa3,0xe5,0x32,0xf0,0x22,0xe4,0x90, ++0x9e,0x31,0xf0,0xa3,0xf0,0x75,0x8e,0x02,0x12,0x77,0x51,0x12,0x5e,0xde,0x90,0x9e, ++0x5e,0xef,0xf0,0x12,0x5e,0xeb,0x90,0x9e,0x60,0xef,0xf0,0xe4,0xf5,0x12,0x12,0x6e, ++0xcc,0x12,0x77,0xc8,0x12,0x5f,0x9f,0x12,0x32,0x3d,0x12,0x77,0xc4,0x12,0x4f,0xf8, ++0x90,0x00,0xf3,0xe0,0x30,0xe2,0x0d,0x90,0x05,0x41,0x74,0x10,0xf0,0x90,0x05,0x5a, ++0xf0,0xa3,0xe4,0xf0,0x12,0x5e,0xf8,0x11,0x16,0x12,0x44,0xff,0x12,0x7d,0x88,0x90, ++0x9e,0x33,0xe5,0xd9,0xf0,0x12,0x5e,0xaf,0xc2,0xaf,0x90,0x00,0x80,0xe0,0x44,0x40, ++0xf0,0x12,0x4b,0xdb,0x75,0xe8,0x03,0x43,0xa8,0x85,0xd2,0xaf,0x90,0x9e,0x31,0xe0, ++0x64,0x01,0xf0,0x24,0x2e,0x90,0x01,0xc4,0xf0,0x74,0x50,0xa3,0xf0,0xe5,0x12,0x30, ++0xe4,0x09,0xc2,0xaf,0x53,0x12,0xef,0xd2,0xaf,0x71,0x1a,0xe5,0x12,0x30,0xe6,0x16, ++0xc2,0xaf,0x53,0x12,0xbf,0xd2,0xaf,0x12,0x68,0x7a,0x90,0x9e,0x1e,0xe0,0xff,0x60, ++0x03,0xb4,0x01,0x02,0x31,0x10,0x90,0x9e,0x1e,0xe0,0x70,0x03,0x12,0x7d,0xe6,0x11, ++0xe3,0x80,0xb9,0x90,0x06,0x34,0xe0,0x60,0x26,0x14,0x70,0x1b,0x7b,0x01,0x7a,0x06, ++0x79,0x35,0x7f,0xf9,0x7e,0x01,0x12,0x77,0x62,0xbf,0x01,0x09,0x90,0x06,0x35,0xe0, ++0x54,0x0f,0xf0,0x80,0x05,0x80,0x00,0x02,0x77,0x43,0xe4,0x90,0x06,0x34,0xf0,0x22, ++0x90,0x9e,0x15,0xe0,0xc3,0x94,0x14,0x50,0x05,0xe0,0x04,0xf0,0x21,0xc8,0x90,0x9e, ++0x15,0xe0,0x64,0x14,0x60,0x02,0x21,0xc8,0x90,0x9e,0x24,0xe0,0x70,0x25,0x90,0x9e, ++0x27,0xe0,0x70,0x1f,0x90,0x9e,0x25,0xe0,0x70,0x19,0x90,0x9e,0x28,0xe0,0x70,0x13, ++0x90,0x9e,0x26,0xe0,0x70,0x0d,0x90,0x9e,0x29,0xe0,0x70,0x07,0x90,0x04,0xfd,0xe0, ++0x54,0xfe,0xf0,0x90,0x9e,0x24,0xe0,0x90,0x04,0x44,0xf0,0x90,0x9e,0x25,0xe0,0x90, ++0x04,0x45,0xf0,0x90,0x9e,0x26,0xe0,0x90,0x04,0x46,0xf0,0xa3,0xe4,0xf0,0x90,0x9e, ++0x27,0xe0,0x90,0x04,0x48,0xf0,0x90,0x9e,0x28,0xe0,0x90,0x04,0x49,0xf0,0x90,0x9e, ++0x29,0xe0,0x90,0x04,0x4a,0xf0,0xa3,0xe4,0xf0,0x90,0x9e,0x10,0xe0,0x90,0x04,0x4c, ++0xf0,0x90,0x9e,0x11,0xe0,0x90,0x04,0x4d,0xf0,0x90,0x9e,0x12,0xe0,0x90,0x04,0x4e, ++0xf0,0x90,0x9e,0x13,0xe0,0x90,0x04,0x4f,0xf0,0xe4,0x90,0x9e,0x15,0xf0,0x90,0x9e, ++0x10,0x04,0xf0,0xe4,0xa3,0xf0,0xa3,0xf0,0xa3,0xf0,0x90,0x9e,0x24,0xf0,0xa3,0xf0, ++0xa3,0xf0,0xa3,0xf0,0xa3,0xf0,0xa3,0xf0,0x90,0x05,0x60,0xe0,0x90,0x9e,0x34,0xf0, ++0x90,0x05,0x61,0xe0,0x90,0x9e,0x35,0xf0,0x90,0x05,0x62,0xe0,0x90,0x9e,0x36,0xf0, ++0x90,0x05,0x63,0xe0,0x90,0x9e,0x37,0xf0,0x90,0x9e,0x2d,0xe0,0xff,0x90,0x9e,0x37, ++0xe0,0xfe,0xd3,0x9f,0x50,0x0b,0x90,0x9e,0x2d,0xe0,0xc3,0x9e,0xd3,0x94,0x01,0x40, ++0x10,0x90,0x9e,0x1b,0xe0,0xb4,0x01,0x02,0x80,0x03,0x90,0x9e,0x1f,0xe0,0xff,0x51, ++0x12,0x22,0x90,0x05,0x60,0xe0,0x90,0x9e,0x2a,0xf0,0x90,0x05,0x61,0xe0,0x90,0x9e, ++0x2b,0xf0,0x90,0x05,0x62,0xe0,0x90,0x9e,0x2c,0xf0,0x90,0x05,0x63,0xe0,0x90,0x9e, ++0x2d,0xf0,0xc3,0x74,0xff,0x9f,0xfe,0x90,0x9e,0x2b,0xe0,0xd3,0x9e,0x40,0x1e,0xe0, ++0x2f,0xf0,0xa3,0xe0,0xb4,0xff,0x0f,0xe4,0xf0,0xa3,0xe0,0xb4,0xff,0x03,0xe4,0xf0, ++0x22,0x90,0x9e,0x2d,0x80,0x03,0x90,0x9e,0x2c,0xe0,0x04,0xf0,0x22,0x90,0x9e,0x2b, ++0xe0,0x2f,0xf0,0x22,0x90,0x9e,0x1c,0xe0,0x64,0x01,0x60,0x02,0x61,0x19,0x90,0x00, ++0x46,0xe0,0x44,0x01,0xfd,0x7f,0x46,0x12,0x4c,0xe3,0x90,0x9e,0x2e,0xe0,0x70,0x32, ++0x90,0x9e,0x14,0xe0,0x60,0x15,0x90,0x9e,0x20,0x12,0x43,0x53,0x90,0x80,0x85,0x12, ++0x2a,0x7f,0x7f,0x80,0x7e,0x08,0x12,0x2f,0xd9,0x80,0x06,0x90,0x05,0x22,0x74,0x7f, ++0xf0,0x90,0x9e,0x1b,0xe0,0xff,0x51,0x12,0x90,0x9e,0x2e,0x74,0x01,0x12,0x4c,0xd9, ++0x80,0x40,0x90,0x9e,0x2e,0xe0,0x64,0x01,0x70,0x38,0x90,0x9e,0x1f,0xe0,0xff,0x51, ++0x12,0xe4,0x90,0x9e,0x2e,0xf0,0x90,0x00,0x45,0xe0,0x44,0x01,0xfd,0x7f,0x45,0x12, ++0x4c,0xe3,0x90,0x9e,0x14,0xe0,0x60,0x15,0x90,0x9e,0x16,0x12,0x43,0x53,0x90,0x80, ++0x85,0x12,0x2a,0x7f,0x7f,0x80,0x7e,0x08,0x12,0x2f,0xd9,0x80,0x05,0x90,0x05,0x22, ++0xe4,0xf0,0x90,0x05,0x87,0xe0,0x64,0x80,0xf0,0x90,0x9e,0x2a,0xe0,0x90,0x05,0x84, ++0xf0,0x90,0x9e,0x2b,0xe0,0x90,0x05,0x85,0xf0,0x90,0x9e,0x2c,0xe0,0x90,0x05,0x86, ++0xf0,0x90,0x9e,0x2d,0xe0,0x90,0x05,0x87,0xf0,0x22,0x90,0x01,0xcc,0xe0,0x54,0x0f, ++0x90,0x9e,0x34,0xf0,0x90,0x9e,0x34,0xe0,0xfd,0x70,0x02,0x81,0x5b,0x90,0x9e,0xad, ++0xe0,0xff,0x74,0x01,0x7e,0x00,0xa8,0x07,0x08,0x80,0x05,0xc3,0x33,0xce,0x33,0xce, ++0xd8,0xf9,0xff,0xef,0x5d,0x70,0x02,0x81,0x54,0x90,0x9e,0xad,0xe0,0x75,0xf0,0x04, ++0x90,0x01,0xd0,0x12,0x43,0x5f,0xe0,0x90,0x9e,0x35,0xf0,0x75,0x1e,0x01,0x75,0x1f, ++0x9e,0x75,0x20,0x35,0x75,0x21,0x01,0x7b,0x01,0x7a,0x9e,0x79,0x36,0x12,0x45,0x09, ++0x90,0x9e,0x36,0xe0,0xff,0xc4,0x13,0x13,0x13,0x54,0x01,0x90,0x9e,0xad,0x30,0xe0, ++0x59,0xe0,0x75,0xf0,0x02,0x90,0x00,0x88,0x12,0x43,0x5f,0xe0,0x90,0x9e,0x37,0xf0, ++0x90,0x9e,0xad,0xe0,0x75,0xf0,0x02,0x90,0x00,0x89,0x12,0x43,0x5f,0xe0,0x90,0x9e, ++0x38,0xf0,0x90,0x9e,0xad,0xe0,0x75,0xf0,0x04,0x90,0x01,0xd1,0x12,0x43,0x5f,0xe0, ++0x90,0x9e,0x39,0xf0,0x90,0x9e,0xad,0xe0,0x75,0xf0,0x04,0x90,0x01,0xd2,0x12,0x43, ++0x5f,0xe0,0x90,0x9e,0x3a,0xf0,0x90,0x9e,0xad,0xe0,0x75,0xf0,0x04,0x90,0x01,0xd3, ++0x12,0x43,0x5f,0xe0,0x90,0x9e,0x3b,0xf0,0x80,0x33,0xe0,0x75,0xf0,0x04,0x90,0x01, ++0xd1,0x12,0x43,0x5f,0xe0,0x90,0x9e,0x37,0xf0,0x90,0x9e,0xad,0xe0,0x75,0xf0,0x04, ++0x90,0x01,0xd2,0x12,0x43,0x5f,0xe0,0x90,0x9e,0x38,0xf0,0x90,0x9e,0xad,0xe0,0x75, ++0xf0,0x04,0x90,0x01,0xd3,0x12,0x43,0x5f,0xe0,0x90,0x9e,0x39,0xf0,0xef,0x54,0x7f, ++0xff,0x7b,0x01,0x7a,0x9e,0x79,0x37,0x91,0x5c,0x90,0x9e,0x34,0xe0,0xff,0x90,0x9e, ++0xad,0xe0,0xfe,0x74,0x01,0xa8,0x06,0x08,0x80,0x02,0xc3,0x33,0xd8,0xfc,0xf4,0x5f, ++0x90,0x9e,0x34,0xf0,0x90,0x9e,0xad,0xe0,0xff,0x74,0x01,0xa8,0x07,0x08,0x80,0x02, ++0xc3,0x33,0xd8,0xfc,0x90,0x01,0xcc,0xf0,0x90,0x9e,0xad,0xe0,0x04,0xf0,0xe0,0x54, ++0x03,0xf0,0x61,0x24,0x90,0x01,0xc6,0xe0,0x44,0x02,0xf0,0x22,0x90,0x9e,0x3c,0x12, ++0x43,0x8b,0xef,0x12,0x43,0x94,0x54,0x97,0x01,0x54,0xa0,0x02,0x54,0xbb,0x03,0x54, ++0xc4,0x05,0x54,0xcd,0x06,0x55,0x1b,0x07,0x54,0xd5,0x09,0x54,0xde,0x0c,0x54,0xe7, ++0x0d,0x54,0xf0,0x0e,0x54,0xf9,0x1b,0x55,0x02,0x1c,0x55,0x0b,0x2c,0x54,0xa9,0x2d, ++0x54,0xb2,0x2e,0x00,0x00,0x55,0x14,0x90,0x9e,0x3c,0x12,0x43,0x6b,0x02,0x61,0x69, ++0x90,0x9e,0x3c,0x12,0x43,0x6b,0x02,0x70,0xef,0x90,0x9e,0x3c,0x12,0x43,0x6b,0x02, ++0x70,0xf5,0x90,0x9e,0x3c,0x12,0x43,0x6b,0x02,0x71,0x3d,0x90,0x9e,0x3c,0x12,0x43, ++0x6b,0x02,0x71,0x6b,0x90,0x9e,0x3c,0x12,0x43,0x6b,0x02,0x70,0x9f,0x90,0x9e,0x3c, ++0x12,0x43,0x6b,0x80,0x47,0x90,0x9e,0x3c,0x12,0x43,0x6b,0x02,0x71,0xb3,0x90,0x9e, ++0x3c,0x12,0x43,0x6b,0x02,0x4d,0xa0,0x90,0x9e,0x3c,0x12,0x43,0x6b,0x02,0x7d,0x55, ++0x90,0x9e,0x3c,0x12,0x43,0x6b,0x02,0x4f,0x07,0x90,0x9e,0x3c,0x12,0x43,0x6b,0x02, ++0x70,0xe7,0x90,0x9e,0x3c,0x12,0x43,0x6b,0x02,0x70,0xce,0x90,0x9e,0x3c,0x12,0x43, ++0x6b,0x02,0x76,0x23,0x90,0x01,0xc6,0xe0,0x44,0x01,0xf0,0x22,0x90,0x00,0x04,0x12, ++0x42,0x20,0xff,0x54,0x1f,0xfe,0xef,0x54,0x20,0xc4,0x13,0x54,0x07,0xfd,0xaf,0x06, ++0x90,0x9e,0x3f,0xef,0xf0,0xa3,0xed,0xf0,0xa3,0x12,0x43,0x8b,0x90,0x9e,0x41,0x12, ++0x43,0x6b,0x90,0x00,0x03,0x12,0x42,0x20,0x54,0xf0,0xc4,0x54,0x0f,0x90,0x9e,0x44, ++0xf0,0x90,0x00,0x04,0x12,0x42,0x20,0x54,0x40,0xc4,0x13,0x13,0x54,0x03,0x90,0x9e, ++0x45,0xf0,0x90,0x9e,0x3f,0xe0,0xff,0x75,0xf0,0x09,0x90,0x96,0x46,0x12,0x43,0x5f, ++0xad,0x82,0xac,0x83,0x90,0x9e,0x46,0xec,0xf0,0xa3,0xed,0xf0,0xef,0x75,0xf0,0x09, ++0xa4,0x24,0x44,0xf9,0x74,0x96,0x35,0xf0,0xfa,0x7b,0x01,0xa3,0x12,0x43,0x8b,0x90, ++0x9e,0x41,0x12,0x43,0x6b,0x90,0x00,0x03,0x12,0x42,0x20,0x54,0x0f,0xff,0x90,0x9e, ++0x48,0x12,0x43,0x6b,0xef,0x12,0x42,0x4d,0x90,0x9e,0x41,0x12,0x43,0x6b,0x90,0x00, ++0x02,0x12,0x42,0x20,0xff,0x90,0x9e,0x48,0x12,0x43,0x6b,0x90,0x00,0x01,0xef,0x12, ++0x42,0x5f,0x90,0x9e,0x41,0x12,0x43,0x6b,0x90,0x00,0x01,0x12,0x42,0x20,0xff,0x90, ++0x9e,0x46,0xe0,0xfc,0xa3,0xe0,0xfd,0xf5,0x82,0x8c,0x83,0xef,0xf0,0x12,0x29,0xd9, ++0x8d,0x82,0x8c,0x83,0xa3,0xf0,0x90,0x9e,0x44,0xe0,0xfe,0x90,0x9e,0x3f,0xe0,0xff, ++0x24,0x82,0xf5,0x82,0xe4,0x34,0x95,0xf5,0x83,0xee,0xf0,0x90,0x9e,0x40,0xe0,0xfe, ++0x75,0xf0,0x09,0xef,0x90,0x96,0x4a,0x12,0x43,0x5f,0xee,0xf0,0x75,0xf0,0x09,0xef, ++0x90,0x96,0x4b,0x12,0x43,0x5f,0x74,0x01,0xf0,0x90,0x9e,0x45,0xe0,0xfe,0x75,0xf0, ++0x09,0xef,0x90,0x96,0x4c,0x12,0x43,0x5f,0xee,0xf0,0x8f,0x59,0xef,0x25,0xe0,0x24, ++0xc6,0xf5,0x82,0xe4,0x34,0x9b,0xaf,0x82,0xf5,0x5b,0x8f,0x5c,0xe5,0x59,0x75,0xf0, ++0x02,0xa4,0x24,0x02,0xf9,0x74,0x95,0x35,0xf0,0x75,0x5d,0x01,0xf5,0x5e,0x89,0x5f, ++0x75,0xf0,0x09,0xe5,0x59,0x90,0x96,0x46,0x12,0x43,0x5f,0xaf,0x82,0x85,0x83,0x60, ++0x8f,0x61,0xe5,0x59,0x75,0xf0,0x09,0xa4,0x24,0x44,0xf9,0x74,0x96,0x35,0xf0,0x75, ++0x62,0x01,0xf5,0x63,0x89,0x64,0x74,0x82,0x25,0x59,0xf5,0x82,0xe4,0x34,0x95,0xf5, ++0x83,0xe0,0x12,0x43,0x94,0x56,0xaa,0x00,0x56,0xbf,0x01,0x56,0xd4,0x02,0x56,0xe9, ++0x03,0x57,0x13,0x04,0x57,0x28,0x05,0x57,0x3d,0x06,0x57,0x64,0x0c,0x57,0x92,0x0d, ++0x57,0xbf,0x0e,0x57,0xec,0x0f,0x00,0x00,0x58,0x20,0xe5,0x59,0x25,0xe0,0x24,0xc6, ++0xf5,0x82,0xe4,0x34,0x9b,0xf5,0x83,0x74,0xf0,0xf0,0xa3,0x74,0x15,0x80,0x3c,0xe5, ++0x59,0x25,0xe0,0x24,0xc6,0xf5,0x82,0xe4,0x34,0x9b,0xf5,0x83,0x74,0xf0,0xf0,0xa3, ++0x74,0x10,0x80,0x27,0xe5,0x59,0x25,0xe0,0x24,0xc6,0xf5,0x82,0xe4,0x34,0x9b,0xf5, ++0x83,0x74,0xf0,0xf0,0xa3,0x74,0x05,0x80,0x12,0xe5,0x59,0x25,0xe0,0x24,0xc6,0xf5, ++0x82,0xe4,0x34,0x9b,0xf5,0x83,0x74,0xf0,0xf0,0xa3,0xe4,0xf0,0xe5,0x59,0x25,0xe0, ++0x24,0x02,0xf5,0x82,0xe4,0x34,0x95,0xf5,0x83,0x74,0x0f,0xf0,0xa3,0x74,0x8f,0xf0, ++0x02,0x58,0x20,0xe5,0x59,0x25,0xe0,0x24,0xc6,0xf5,0x82,0xe4,0x34,0x9b,0xf5,0x83, ++0x74,0x0f,0xf0,0xa3,0x74,0xf5,0x80,0x27,0xe5,0x59,0x25,0xe0,0x24,0xc6,0xf5,0x82, ++0xe4,0x34,0x9b,0xf5,0x83,0x74,0x0f,0xf0,0xa3,0x74,0xf0,0x80,0x12,0xe5,0x59,0x25, ++0xe0,0x24,0xc6,0xf5,0x82,0xe4,0x34,0x9b,0xf5,0x83,0xe4,0xf0,0xa3,0x74,0x0d,0xf0, ++0xe5,0x59,0x25,0xe0,0x24,0x02,0xf5,0x82,0xe4,0x34,0x95,0xf5,0x83,0xe4,0xf0,0xa3, ++0xf0,0x02,0x58,0x20,0x90,0x04,0x47,0xe0,0xab,0x5d,0xaa,0x5e,0xa9,0x5f,0x12,0x42, ++0x4d,0x90,0x04,0x46,0xe0,0xab,0x5d,0xaa,0x5e,0xa9,0x5f,0x90,0x00,0x01,0x12,0x42, ++0x5f,0x90,0x04,0x45,0xe0,0x85,0x5c,0x82,0x85,0x5b,0x83,0xf0,0x90,0x04,0x44,0x02, ++0x58,0x17,0x90,0x04,0x4b,0xe0,0xab,0x5d,0xaa,0x5e,0xa9,0x5f,0x12,0x42,0x4d,0x90, ++0x04,0x4a,0xe0,0xab,0x5d,0xaa,0x5e,0xa9,0x5f,0x90,0x00,0x01,0x12,0x42,0x5f,0x90, ++0x04,0x49,0xe0,0x85,0x5c,0x82,0x85,0x5b,0x83,0xf0,0x90,0x04,0x48,0x80,0x58,0x90, ++0x04,0x4f,0xe0,0xab,0x5d,0xaa,0x5e,0xa9,0x5f,0x12,0x42,0x4d,0x90,0x04,0x4e,0xe0, ++0xab,0x5d,0xaa,0x5e,0xa9,0x5f,0x90,0x00,0x01,0x12,0x42,0x5f,0x90,0x04,0x4d,0xe0, ++0x85,0x5c,0x82,0x85,0x5b,0x83,0xf0,0x90,0x04,0x4c,0x80,0x2b,0x90,0x04,0x53,0xe0, ++0xab,0x5d,0xaa,0x5e,0xa9,0x5f,0x12,0x42,0x4d,0x90,0x04,0x52,0xe0,0xab,0x5d,0xaa, ++0x5e,0xa9,0x5f,0x90,0x00,0x01,0x12,0x42,0x5f,0x90,0x04,0x51,0xe0,0x85,0x5c,0x82, ++0x85,0x5b,0x83,0xf0,0x90,0x04,0x50,0xe0,0x85,0x5c,0x82,0x85,0x5b,0x83,0xa3,0xf0, ++0xab,0x5d,0xaa,0x5e,0xa9,0x5f,0xc0,0x03,0xc0,0x02,0xc0,0x01,0x12,0x29,0xd9,0xff, ++0xab,0x62,0xaa,0x63,0xa9,0x64,0x12,0x29,0xd9,0x5f,0xd0,0x01,0xd0,0x02,0xd0,0x03, ++0x12,0x42,0x4d,0xab,0x5d,0xe5,0x5f,0x24,0x01,0xf9,0xe4,0x35,0x5e,0xfa,0xc0,0x03, ++0xc0,0x02,0xc0,0x01,0x12,0x29,0xd9,0xff,0xab,0x62,0xaa,0x63,0xa9,0x64,0x90,0x00, ++0x01,0x12,0x42,0x20,0x5f,0xd0,0x01,0xd0,0x02,0xd0,0x03,0x12,0x42,0x4d,0x85,0x5c, ++0x82,0x85,0x5b,0x83,0xc0,0x83,0xc0,0x82,0xe0,0xff,0x85,0x61,0x82,0x85,0x60,0x83, ++0xe0,0xfe,0xef,0x5e,0xd0,0x82,0xd0,0x83,0xf0,0x85,0x5c,0x82,0x85,0x5b,0x83,0xa3, ++0xc0,0x83,0xc0,0x82,0xe0,0xff,0x85,0x61,0x82,0x85,0x60,0x83,0xa3,0xe0,0xfe,0xef, ++0x5e,0xd0,0x82,0xd0,0x83,0xf0,0xe5,0x59,0x25,0xe0,0x24,0x02,0xf5,0x82,0xe4,0x34, ++0x95,0xf5,0x83,0xe0,0xfe,0xa3,0xe0,0x4e,0x60,0x3b,0x75,0x5a,0x0b,0x74,0x01,0x7e, ++0x00,0xa8,0x5a,0x08,0x80,0x05,0xc3,0x33,0xce,0x33,0xce,0xd8,0xf9,0xff,0xe5,0x59, ++0x25,0xe0,0x24,0x02,0xf5,0x82,0xe4,0x34,0x95,0xf5,0x83,0xe0,0x5e,0xfe,0xa3,0xe0, ++0x5f,0x4e,0x60,0x06,0xe5,0x5a,0x24,0x10,0x80,0x5d,0x15,0x5a,0xe5,0x5a,0xc3,0x94, ++0x00,0x50,0xca,0x80,0x56,0xe5,0x59,0x25,0xe0,0x24,0xc6,0xf5,0x82,0xe4,0x34,0x9b, ++0xf5,0x83,0xe0,0xfe,0xa3,0xe0,0x4e,0x60,0x3d,0x75,0x5a,0x0f,0x74,0x01,0x7e,0x00, ++0xa8,0x5a,0x08,0x80,0x05,0xc3,0x33,0xce,0x33,0xce,0xd8,0xf9,0xff,0xe5,0x59,0x25, ++0xe0,0x24,0xc6,0xf5,0x82,0xe4,0x34,0x9b,0xf5,0x83,0xe0,0x5e,0xfe,0xa3,0xe0,0x5f, ++0x4e,0x60,0x08,0x90,0x9e,0x4b,0xe5,0x5a,0xf0,0x80,0x10,0x15,0x5a,0xe5,0x5a,0xc3, ++0x94,0x00,0x50,0xc8,0x80,0x05,0xe4,0x90,0x9e,0x4b,0xf0,0xe5,0x59,0x25,0xe0,0x24, ++0xc6,0xf5,0x82,0xe4,0x34,0x9b,0xf5,0x83,0xe0,0xfe,0xa3,0xe0,0x4e,0x60,0x3b,0xe4, ++0xf5,0x5a,0x74,0x01,0x7e,0x00,0xa8,0x5a,0x08,0x80,0x05,0xc3,0x33,0xce,0x33,0xce, ++0xd8,0xf9,0xff,0xe5,0x59,0x25,0xe0,0x24,0xc6,0xf5,0x82,0xe4,0x34,0x9b,0xf5,0x83, ++0xe0,0x5e,0xfe,0xa3,0xe0,0x5f,0x4e,0x60,0x08,0x90,0x9e,0x4c,0xe5,0x5a,0xf0,0x80, ++0x5b,0x05,0x5a,0xe5,0x5a,0xb4,0x10,0xca,0x80,0x52,0xe5,0x59,0x25,0xe0,0x24,0x02, ++0xf5,0x82,0xe4,0x34,0x95,0xf5,0x83,0xe0,0xfe,0xa3,0xe0,0x4e,0x60,0x39,0xe4,0xf5, ++0x5a,0x74,0x01,0x7e,0x00,0xa8,0x5a,0x08,0x80,0x05,0xc3,0x33,0xce,0x33,0xce,0xd8, ++0xf9,0xff,0xe5,0x59,0x25,0xe0,0x24,0x02,0xf5,0x82,0xe4,0x34,0x95,0xf5,0x83,0xe0, ++0x5e,0xfe,0xa3,0xe0,0x5f,0x4e,0x60,0x06,0xe5,0x5a,0x24,0x10,0x80,0x0a,0x05,0x5a, ++0xe5,0x5a,0xb4,0x0c,0xcc,0x80,0x05,0xe4,0x90,0x9e,0x4c,0xf0,0x90,0x9e,0x4b,0xe0, ++0xff,0x75,0xf0,0x09,0xe5,0x59,0x90,0x96,0x48,0x12,0x43,0x5f,0xef,0xf0,0x90,0x9e, ++0x4c,0xe0,0xfe,0x75,0xf0,0x09,0xe5,0x59,0x90,0x96,0x49,0x12,0x43,0x5f,0xee,0xf0, ++0x74,0x84,0x25,0x59,0xf5,0x82,0xe4,0x34,0x04,0xf5,0x83,0xe0,0xd3,0x9f,0x40,0x05, ++0x90,0x9e,0x4b,0x51,0x6f,0x74,0x84,0x25,0x59,0xf5,0x82,0xe4,0x34,0x04,0xf5,0x83, ++0xe0,0xff,0x90,0x9e,0x4c,0xe0,0xfe,0xef,0xc3,0x9e,0x50,0x02,0x51,0x6f,0x90,0x9e, ++0x4b,0xe0,0xff,0xd3,0x94,0x13,0x40,0x07,0x90,0x96,0x43,0x74,0x03,0xf0,0x22,0xef, ++0xd3,0x94,0x0b,0x40,0x07,0x90,0x96,0x43,0x74,0x02,0xf0,0x22,0xef,0xd3,0x94,0x03, ++0x40,0x07,0x90,0x96,0x43,0x74,0x01,0xf0,0x22,0xe4,0x90,0x96,0x43,0xf0,0x22,0xe0, ++0xfd,0x74,0x26,0x25,0x59,0xf5,0x82,0xe4,0x34,0x9d,0xf5,0x83,0xed,0xf0,0xaf,0x59, ++0xd3,0x10,0xaf,0x01,0xc3,0xc0,0xd0,0xef,0xc3,0x94,0x20,0x50,0x0e,0x74,0x84,0x2f, ++0xf5,0x82,0xe4,0x34,0x04,0xf5,0x83,0xed,0xf0,0x80,0x29,0x74,0xa6,0x2f,0xf5,0x82, ++0xe4,0x34,0x9c,0xf5,0x83,0xed,0xf0,0x90,0x9e,0x75,0xef,0xf0,0x24,0xa6,0xf5,0x82, ++0xe4,0x34,0x9c,0xf5,0x83,0xe0,0x90,0x9e,0x76,0xf0,0x7b,0x01,0x7a,0x9e,0x79,0x75, ++0x7d,0x02,0x51,0xc9,0xd0,0xd0,0x92,0xaf,0x22,0xd3,0x10,0xaf,0x01,0xc3,0xc0,0xd0, ++0x90,0x9e,0x94,0x12,0x43,0x8b,0x90,0x9e,0x97,0xe0,0x54,0xf0,0x44,0x06,0xff,0xf0, ++0xed,0x54,0x0f,0xc4,0x54,0xf0,0xfe,0xef,0x54,0x0f,0x4e,0xf0,0x90,0x9e,0x94,0x12, ++0x43,0x6b,0x90,0x9e,0x91,0x12,0x43,0x8b,0x7b,0x01,0x7a,0x9e,0x79,0x97,0x71,0xd4, ++0xd0,0xd0,0x92,0xaf,0x22,0x8f,0x50,0x8d,0x51,0xe5,0x51,0x54,0x1f,0xf5,0x56,0x74, ++0x01,0x2f,0xf5,0x82,0xe4,0x34,0x94,0xf5,0x83,0xe0,0xf5,0x54,0x90,0x04,0xfd,0xe0, ++0xb4,0x01,0x05,0x75,0x57,0x03,0x80,0x03,0x75,0x57,0x01,0xeb,0xc3,0x95,0x57,0x40, ++0x04,0xaf,0x50,0x80,0x33,0xe5,0x54,0x25,0x53,0xf5,0x55,0xe5,0x56,0x90,0x41,0xd6, ++0x93,0xff,0xe5,0x55,0xd3,0x9f,0x74,0x01,0x40,0x11,0x25,0x50,0xf5,0x82,0xe4,0x34, ++0x94,0xf5,0x83,0xe4,0xf0,0xad,0x51,0xaf,0x50,0x41,0x80,0x25,0x50,0xf5,0x82,0xe4, ++0x34,0x94,0xf5,0x83,0xe5,0x55,0xf0,0x22,0xad,0x07,0x75,0xf0,0x09,0xed,0x90,0x96, ++0x48,0x12,0x43,0x5f,0xe0,0xff,0x74,0x67,0x2d,0xf5,0x82,0xe4,0x34,0x9d,0xf5,0x83, ++0xe0,0x54,0x1f,0xf5,0x58,0xd3,0x9f,0x40,0x02,0x8f,0x58,0xe5,0x58,0x25,0xe0,0x24, ++0x9e,0xf5,0x82,0xe4,0x34,0x41,0xf5,0x83,0xe4,0x93,0xfe,0x74,0x01,0x93,0xff,0xe5, ++0x58,0x25,0xe0,0x24,0x66,0xf5,0x82,0xe4,0x34,0x41,0xf5,0x83,0x74,0x01,0x93,0x2f, ++0xff,0xe4,0x93,0x3e,0xc3,0x13,0xfe,0xef,0x13,0xff,0xed,0x25,0xe0,0x24,0xc2,0xf5, ++0x82,0xe4,0x34,0x95,0xf5,0x83,0xee,0xf0,0xa3,0xef,0xf0,0xaf,0x05,0xad,0x58,0x51, ++0x80,0xaf,0x58,0x22,0xd3,0x10,0xaf,0x01,0xc3,0xc0,0xd0,0x90,0x9e,0x8e,0x12,0x43, ++0x8b,0x90,0x9e,0xaf,0xe0,0xff,0x04,0xf0,0x90,0x00,0x01,0xef,0x12,0x42,0x5f,0x7f, ++0xaf,0x7e,0x01,0x91,0x67,0xef,0x60,0x49,0x90,0x9e,0x8e,0x12,0x43,0x6b,0x8b,0x1e, ++0x8a,0x1f,0x89,0x20,0x75,0x21,0x02,0x7b,0x01,0x7a,0x01,0x79,0xa0,0x12,0x45,0x09, ++0x90,0x9e,0x91,0x12,0x43,0x6b,0x8b,0x1e,0x8a,0x1f,0x89,0x20,0x90,0x9e,0x8e,0x12, ++0x43,0x6b,0x12,0x29,0xd9,0xff,0xc4,0x54,0x0f,0xf5,0x21,0x7b,0x01,0x7a,0x01,0x79, ++0xa2,0x12,0x45,0x09,0x90,0x01,0xaf,0x74,0xff,0xf0,0x90,0x01,0xcb,0xe0,0x64,0x80, ++0xf0,0xd0,0xd0,0x92,0xaf,0x22,0x90,0x9e,0x2f,0xe0,0x54,0xf0,0x44,0x03,0xf0,0x54, ++0x0f,0x44,0x80,0xf0,0x7b,0x00,0x7a,0x00,0x79,0x13,0x90,0x9e,0x91,0x12,0x43,0x8b, ++0x0b,0x7a,0x9e,0x79,0x2f,0x61,0xd4,0xd3,0x10,0xaf,0x01,0xc3,0xc0,0xd0,0x90,0x9e, ++0x9d,0xee,0xf0,0xa3,0xef,0xf0,0xe4,0xa3,0xf0,0xa3,0xf0,0x90,0x9e,0x9d,0xe0,0xfe, ++0xa3,0xe0,0xf5,0x82,0x8e,0x83,0xe0,0x60,0x2d,0xc3,0x90,0x9e,0xa0,0xe0,0x94,0xe8, ++0x90,0x9e,0x9f,0xe0,0x94,0x03,0x40,0x0b,0x90,0x01,0xc6,0xe0,0x44,0x10,0xf0,0x7f, ++0x00,0x80,0x15,0x90,0x9e,0x9f,0xe4,0x75,0xf0,0x01,0x12,0x42,0x81,0x7f,0x0a,0x7e, ++0x00,0x12,0x37,0x54,0x80,0xc5,0x7f,0x01,0xd0,0xd0,0x92,0xaf,0x22,0xac,0x07,0xec, ++0xc3,0x94,0x20,0x50,0x0d,0x74,0x84,0x2c,0xf5,0x82,0xe4,0x34,0x04,0xf5,0x83,0xe0, ++0x80,0x0b,0x74,0xa6,0x2c,0xf5,0x82,0xe4,0x34,0x9c,0xf5,0x83,0xe0,0x54,0x7f,0xf5, ++0x64,0xe5,0x64,0x54,0x1f,0xff,0x90,0x9e,0x40,0xf0,0x75,0xf0,0x09,0xec,0x90,0x96, ++0x49,0x12,0x43,0x5f,0xe0,0x90,0x9e,0x42,0xf0,0x75,0xf0,0x09,0xec,0x90,0x96,0x48, ++0x12,0x43,0x5f,0xe0,0xfe,0x90,0x9e,0x43,0xf0,0xec,0x25,0xe0,0x24,0xc6,0xf5,0x82, ++0xe4,0x34,0x9b,0xf5,0x83,0xe0,0xfb,0xa3,0xe0,0x90,0x9e,0x44,0xcb,0xf0,0xa3,0xeb, ++0xf0,0xec,0x25,0xe0,0x24,0x02,0xf5,0x82,0xe4,0x34,0x95,0xf5,0x83,0xe0,0xfb,0xa3, ++0xe0,0x90,0x9e,0x46,0xcb,0xf0,0xa3,0xeb,0xf0,0xef,0xd3,0x9e,0x40,0x0a,0x90,0x9e, ++0x43,0xe0,0x90,0x9e,0x40,0xf0,0xf5,0x64,0xed,0x70,0x02,0xc1,0x13,0x90,0x9e,0x41, ++0xed,0xf0,0xe5,0x64,0x30,0xe6,0x0a,0x90,0x9e,0x40,0xe0,0xf5,0x64,0xa3,0xe0,0x14, ++0xf0,0x90,0x9e,0x41,0xe0,0x70,0x02,0xc1,0x13,0x90,0x9e,0x40,0xe0,0xff,0xd3,0x94, ++0x00,0x50,0x02,0xc1,0x13,0xe4,0x90,0x9e,0x3f,0xf0,0xef,0x14,0x90,0x9e,0x3e,0xf0, ++0x90,0x9e,0x42,0xe0,0xfd,0x90,0x9e,0x3e,0xe0,0xff,0xd3,0x9d,0x40,0x6b,0xef,0x94, ++0x10,0x40,0x21,0xef,0x24,0xf0,0xff,0x74,0x01,0x7e,0x00,0xa8,0x07,0x08,0x80,0x05, ++0xc3,0x33,0xce,0x33,0xce,0xd8,0xf9,0xff,0x90,0x9e,0x46,0xe0,0x5e,0xfe,0xa3,0xe0, ++0x5f,0x4e,0x70,0x27,0x90,0x9e,0x3e,0xe0,0xff,0xc3,0x94,0x10,0x50,0x33,0x74,0x01, ++0x7e,0x00,0xa8,0x07,0x08,0x80,0x05,0xc3,0x33,0xce,0x33,0xce,0xd8,0xf9,0xff,0x90, ++0x9e,0x44,0xe0,0x5e,0xfe,0xa3,0xe0,0x5f,0x4e,0x60,0x16,0x90,0x9e,0x3e,0xe0,0xf5, ++0x64,0xa3,0xe0,0x04,0xf0,0x90,0x9e,0x41,0xe0,0xff,0x90,0x9e,0x3f,0xe0,0x6f,0x60, ++0x08,0x90,0x9e,0x3e,0xe0,0x14,0xf0,0x80,0x87,0x90,0x9e,0x41,0xe0,0xff,0x90,0x9e, ++0x3f,0xe0,0xc3,0x9f,0x50,0x0d,0x90,0x9e,0x3e,0xe0,0xb5,0x05,0x06,0x90,0x9e,0x42, ++0xe0,0xf5,0x64,0xe5,0x64,0x25,0xe0,0x24,0x9e,0xf5,0x82,0xe4,0x34,0x41,0xf5,0x83, ++0xe4,0x93,0xfe,0x74,0x01,0x93,0xff,0xe5,0x64,0x25,0xe0,0x24,0x66,0xf5,0x82,0xe4, ++0x34,0x41,0xf5,0x83,0x74,0x01,0x93,0x2f,0xff,0xe4,0x93,0x3e,0xc3,0x13,0xfe,0xef, ++0x13,0xff,0xec,0x25,0xe0,0x24,0xc2,0xf5,0x82,0xe4,0x34,0x95,0xf5,0x83,0xee,0xf0, ++0xa3,0xef,0xf0,0xaf,0x04,0xad,0x64,0x51,0x80,0xaf,0x64,0x22,0x8f,0x77,0x12,0x45, ++0xa6,0xef,0x64,0x01,0x70,0x2e,0x90,0x9e,0x52,0x12,0x47,0xcc,0xe5,0x77,0x60,0x10, ++0x74,0x21,0x2f,0xf5,0x82,0xe4,0x34,0xfc,0xf5,0x83,0xe0,0x44,0x10,0xf0,0x80,0x0e, ++0x74,0x21,0x2f,0xf5,0x82,0xe4,0x34,0xfc,0xf5,0x83,0xe0,0x54,0xef,0xf0,0x90,0x04, ++0x1f,0x74,0x20,0xf0,0x22,0x90,0x06,0x04,0xe0,0x54,0xbf,0xf0,0xef,0x60,0x09,0xe5, ++0x22,0xb4,0x01,0x04,0xe4,0xff,0xd1,0x5c,0x53,0x23,0xf0,0x43,0x23,0x0c,0x22,0x90, ++0x01,0x3c,0x74,0xff,0xf0,0xa3,0xf0,0xa3,0xf0,0x90,0x01,0x34,0xf0,0xa3,0xf0,0xa3, ++0xf0,0xa3,0xf0,0xfd,0x7f,0x54,0x12,0x4c,0xe3,0x7d,0xff,0x7f,0x55,0x12,0x4c,0xe3, ++0x7d,0xff,0x7f,0x56,0x12,0x4c,0xe3,0x7d,0xff,0x7f,0x57,0x02,0x4c,0xe3,0x90,0x00, ++0x02,0xe0,0x54,0xe0,0x7f,0x01,0x60,0x02,0x7f,0x00,0x22,0x90,0x00,0xf3,0xe0,0x7f, ++0x00,0x30,0xe3,0x03,0x7f,0x01,0x22,0x22,0x90,0x01,0x64,0x74,0xa0,0xf0,0x22,0xc0, ++0xe0,0xc0,0xf0,0xc0,0x83,0xc0,0x82,0xc0,0xd0,0x75,0xd0,0x00,0xc0,0x00,0xc0,0x01, ++0xc0,0x02,0xc0,0x03,0xc0,0x04,0xc0,0x05,0xc0,0x06,0xc0,0x07,0x90,0x01,0xc4,0x74, ++0xff,0xf0,0x74,0x5e,0xa3,0xf0,0x53,0x91,0xef,0x90,0x00,0x51,0xe0,0xff,0x90,0x00, ++0x55,0xe0,0x5f,0xf5,0x3d,0xe5,0x3d,0x30,0xe6,0x18,0x74,0x40,0xf0,0x90,0x9e,0x1d, ++0xe0,0x54,0x03,0xff,0xbf,0x03,0x0b,0x90,0x9e,0x1a,0xe0,0x60,0x05,0x7f,0x01,0x12, ++0x4c,0xf8,0xe5,0x3d,0x30,0xe7,0x15,0x90,0x00,0x55,0x74,0x80,0xf0,0x90,0x9e,0x1d, ++0xe0,0x54,0x03,0xff,0xbf,0x03,0x05,0x7f,0x02,0x12,0x4c,0xf8,0x90,0x01,0xc4,0x74, ++0xff,0xf0,0x74,0x5e,0xa3,0xf0,0xd0,0x07,0xd0,0x06,0xd0,0x05,0xd0,0x04,0xd0,0x03, ++0xd0,0x02,0xd0,0x01,0xd0,0x00,0xd0,0xd0,0xd0,0x82,0xd0,0x83,0xd0,0xf0,0xd0,0xe0, ++0x32,0x8f,0x6b,0x8c,0x6c,0x8d,0x6d,0x22,0x8f,0x6e,0x8c,0x6f,0x8d,0x70,0x22,0xe4, ++0xf5,0x22,0xf5,0x26,0xf5,0x25,0x75,0x24,0x0c,0x75,0x23,0x0c,0x90,0x9e,0x73,0xf0, ++0x90,0x9e,0x71,0xf0,0x90,0x9e,0x70,0xf0,0x90,0x9e,0x72,0x04,0xf0,0x90,0x9e,0x64, ++0xf0,0xe4,0x90,0x9e,0x74,0xf0,0x90,0x9e,0x66,0xf0,0x90,0x9e,0x6e,0x74,0x07,0xf0, ++0xe4,0x90,0x9e,0x65,0xf0,0x90,0x9e,0x6c,0xf0,0xa3,0x74,0x02,0xf0,0x90,0x9e,0x6a, ++0x14,0xf0,0xa3,0x74,0x03,0xf0,0x90,0x9e,0x69,0x74,0x14,0xf0,0x90,0x9e,0x6f,0x74, ++0x05,0xf0,0xe4,0x90,0x9e,0x68,0xf0,0x90,0x9e,0x63,0xf0,0x90,0x9e,0x5f,0xf0,0x22, ++0xe4,0x90,0x9e,0x74,0xf0,0x90,0x9e,0x65,0xf0,0xf5,0x26,0x22,0x8b,0x59,0x8a,0x5a, ++0x89,0x5b,0x11,0x00,0xab,0x59,0xaa,0x5a,0xa9,0x5b,0x12,0x29,0xd9,0xf5,0x25,0x14, ++0x60,0x0e,0x14,0x60,0x1e,0x14,0x60,0x2f,0x24,0x03,0x70,0x40,0x7f,0x01,0x80,0x3a, ++0xab,0x59,0xaa,0x5a,0xa9,0x5b,0x90,0x00,0x02,0x12,0x42,0x20,0xfd,0xe4,0xff,0x11, ++0x6d,0x80,0x27,0xab,0x59,0xaa,0x5a,0xa9,0x5b,0x90,0x00,0x02,0x12,0x42,0x20,0xfd, ++0x7f,0x01,0x11,0x6d,0x1f,0x80,0x13,0xab,0x59,0xaa,0x5a,0xa9,0x5b,0x90,0x00,0x02, ++0x12,0x42,0x20,0xfd,0x7f,0x02,0x11,0x6d,0xe4,0xff,0x11,0x98,0x22,0xef,0x24,0xfe, ++0x60,0x0b,0x04,0x70,0x22,0x90,0x9e,0x72,0x74,0x01,0xf0,0x80,0x16,0xed,0x70,0x0a, ++0x90,0x9e,0x6f,0xe0,0x90,0x9e,0x72,0xf0,0x80,0x05,0x90,0x9e,0x72,0xed,0xf0,0x90, ++0x9e,0x72,0xe0,0x90,0x9e,0x64,0xf0,0x22,0xef,0x64,0x01,0x70,0x2f,0x7d,0x7c,0x7f, ++0x02,0x12,0x36,0x75,0x7d,0x02,0x7f,0x03,0x12,0x36,0x75,0x90,0x01,0x57,0xe4,0xf0, ++0x90,0x01,0x3c,0x74,0x02,0xf0,0x12,0x47,0x2b,0xe4,0xff,0x31,0x1f,0x90,0x06,0x04, ++0xe0,0x54,0x7f,0xf0,0x90,0x06,0x0a,0xe0,0x54,0xf8,0xf0,0x22,0x90,0x01,0x36,0x74, ++0x7c,0xf0,0xa3,0x74,0x02,0xf0,0x7d,0x7c,0xff,0x12,0x36,0xe6,0x7d,0x02,0x7f,0x03, ++0x12,0x36,0xe6,0x90,0x06,0x04,0xe0,0x44,0x80,0xf0,0x90,0x06,0x0a,0xe0,0x44,0x07, ++0xf0,0x90,0x9e,0x6c,0xe0,0xa3,0xe0,0x90,0x05,0x58,0xf0,0xe5,0x22,0x30,0xe0,0x19, ++0x90,0x9e,0x66,0xe0,0x70,0x18,0xe0,0x04,0xf0,0xe5,0x23,0x54,0x0f,0xc3,0x94,0x04, ++0x50,0x0c,0x7d,0x01,0x7f,0x04,0x02,0x47,0x2f,0xe4,0x90,0x9e,0x66,0xf0,0x22,0xef, ++0x60,0x0b,0x90,0x9e,0x60,0xe0,0xb4,0x01,0x10,0xe4,0xff,0x80,0x09,0x90,0x9e,0x60, ++0xe0,0xb4,0x01,0x05,0x7f,0x01,0x12,0x77,0xd1,0x22,0x90,0x01,0x37,0x74,0x02,0xf0, ++0x90,0x05,0x22,0x74,0xff,0xf0,0x31,0xc3,0xef,0x70,0x06,0x90,0x01,0xc8,0x74,0xfd, ++0xf0,0x7d,0x02,0x7f,0x03,0x12,0x36,0xe6,0xe5,0x25,0x60,0x04,0x7f,0x01,0x31,0x1f, ++0x51,0x04,0x53,0x23,0xf0,0x43,0x23,0x02,0x22,0xd3,0x10,0xaf,0x01,0xc3,0xc0,0xd0, ++0x90,0x00,0x01,0x12,0x42,0x20,0x90,0x9e,0x73,0xf0,0x90,0x00,0x03,0x12,0x42,0x20, ++0x90,0x9e,0x63,0xf0,0x12,0x29,0xd9,0x65,0x25,0x60,0x02,0x11,0x0c,0xd0,0xd0,0x92, ++0xaf,0x22,0x7d,0x02,0x7f,0x03,0x12,0x36,0x75,0xe5,0x25,0x14,0x24,0xfd,0x50,0x02, ++0x80,0x20,0x90,0x9e,0x73,0xe0,0x60,0x06,0x7d,0x01,0x7f,0x0c,0x80,0x0d,0xe5,0x23, ++0x54,0x0f,0xc3,0x94,0x04,0x50,0x07,0x7d,0x01,0x7f,0x04,0x12,0x47,0x2f,0xe4,0xff, ++0x31,0x1f,0x22,0xe4,0x90,0x9e,0xa9,0xf0,0xa3,0xf0,0x90,0x05,0xf8,0xe0,0x70,0x0f, ++0xa3,0xe0,0x70,0x0b,0xa3,0xe0,0x70,0x07,0xa3,0xe0,0x70,0x03,0x7f,0x01,0x22,0xd3, ++0x90,0x9e,0xaa,0xe0,0x94,0xe8,0x90,0x9e,0xa9,0xe0,0x94,0x03,0x40,0x03,0x7f,0x00, ++0x22,0x7f,0x32,0x7e,0x00,0x12,0x37,0x54,0x90,0x9e,0xa9,0xe4,0x75,0xf0,0x01,0x12, ++0x42,0x81,0x80,0xc6,0x7f,0x78,0x7e,0x08,0x12,0x27,0xde,0x90,0x9d,0xff,0x12,0x2a, ++0x7f,0x7f,0x04,0x7e,0x0c,0x12,0x27,0xde,0x90,0x9e,0x03,0x12,0x2a,0x7f,0x7f,0x00, ++0x7e,0x08,0x12,0x27,0xde,0x90,0x9e,0x07,0x12,0x2a,0x7f,0x90,0x9e,0x60,0xe0,0x90, ++0x9d,0xff,0xb4,0x01,0x0d,0x12,0x43,0x53,0xef,0x54,0xc7,0xff,0xed,0x54,0xc7,0xfd, ++0x80,0x07,0x12,0x43,0x53,0xef,0x54,0xc7,0xff,0xec,0x90,0x80,0x85,0x12,0x2a,0x7f, ++0x7f,0x78,0x7e,0x08,0x12,0x2f,0xd9,0x90,0x9e,0x03,0x12,0x43,0x53,0xef,0x54,0x0f, ++0xff,0xec,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0x04,0x7e,0x0c,0x12,0x2f,0xd9,0x90, ++0x9e,0x07,0x12,0x43,0x53,0xef,0x44,0x02,0xff,0xec,0x90,0x80,0x85,0x12,0x2a,0x7f, ++0x7f,0x00,0x7e,0x08,0x12,0x2f,0xd9,0x7f,0x70,0x7e,0x0e,0x12,0x27,0xde,0x90,0x9e, ++0x0b,0x12,0x2a,0x7f,0x90,0x80,0x85,0x12,0x2a,0x8b,0x00,0x1b,0x25,0xa0,0x7f,0x70, ++0x7e,0x0e,0x12,0x2f,0xd9,0x90,0x80,0x59,0x12,0x2a,0x8b,0x00,0x00,0x00,0x00,0xe4, ++0xfd,0xff,0x12,0x34,0x81,0x90,0x9e,0x60,0xe0,0xb4,0x01,0x11,0x90,0x80,0x59,0x12, ++0x2a,0x8b,0x00,0x00,0x00,0x00,0xe4,0xfd,0x7f,0x01,0x12,0x34,0x81,0x22,0x12,0x4b, ++0xc4,0xef,0x64,0x01,0x60,0x08,0x90,0x01,0xb9,0x74,0x01,0xf0,0x80,0x30,0x90,0x9e, ++0x71,0xe0,0x60,0x08,0x90,0x01,0xb9,0x74,0x02,0xf0,0x80,0x22,0x90,0x9e,0x70,0xe0, ++0x60,0x08,0x90,0x01,0xb9,0x74,0x04,0xf0,0x80,0x14,0xe5,0x24,0x54,0x0f,0xd3,0x94, ++0x04,0x40,0x08,0x90,0x01,0xb9,0x74,0x08,0xf0,0x80,0x03,0x7f,0x01,0x22,0x90,0x01, ++0xb8,0x74,0x08,0xf0,0x7f,0x00,0x22,0x12,0x4b,0xc4,0xef,0x64,0x01,0x60,0x08,0x90, ++0x01,0xb9,0x74,0x01,0xf0,0x80,0x4a,0xe5,0x26,0x54,0x03,0x60,0x08,0x90,0x01,0xb9, ++0x74,0x02,0xf0,0x80,0x3c,0xe5,0x24,0x54,0x0f,0xd3,0x94,0x02,0x40,0x08,0x90,0x01, ++0xb9,0x74,0x04,0xf0,0x80,0x2b,0xe5,0x26,0x30,0xe2,0x08,0x90,0x01,0xb9,0x74,0x08, ++0xf0,0x80,0x1e,0xe5,0x26,0x30,0xe4,0x08,0x90,0x01,0xb9,0x74,0x10,0xf0,0x80,0x11, ++0x90,0x9e,0x66,0xe0,0x60,0x08,0x90,0x01,0xb9,0x74,0x20,0xf0,0x80,0x03,0x7f,0x01, ++0x22,0x90,0x01,0xb8,0x74,0x04,0xf0,0x7f,0x00,0x22,0xe5,0x12,0x60,0x08,0x90,0x01, ++0xb9,0x74,0x01,0xf0,0x80,0x5b,0xe5,0x24,0x54,0x0f,0xd3,0x94,0x01,0x40,0x08,0x90, ++0x01,0xb9,0x74,0x02,0xf0,0x80,0x4a,0x90,0x02,0x87,0xe0,0x60,0x08,0x90,0x01,0xb9, ++0x74,0x04,0xf0,0x80,0x3c,0x90,0x9e,0x5e,0xe0,0xb4,0x01,0x10,0x90,0x9e,0x4d,0xe0, ++0xfe,0xa3,0xe0,0xf5,0x82,0x8e,0x83,0xe0,0x60,0x16,0x80,0x25,0x90,0x9e,0x5e,0xe0, ++0x70,0x0e,0x90,0x01,0xaf,0xe0,0x60,0x08,0x90,0x01,0xb9,0x74,0x08,0xf0,0x80,0x11, ++0x90,0x9e,0x68,0xe0,0x70,0x08,0x90,0x01,0xb9,0x74,0x10,0xf0,0x80,0x03,0x7f,0x01, ++0x22,0x90,0x01,0xb8,0x74,0x02,0xf0,0x7f,0x00,0x22,0x90,0x9e,0xae,0xef,0xf0,0x91, ++0x03,0x90,0x9e,0xae,0xe0,0x60,0x05,0x90,0x05,0x22,0xe4,0xf0,0x53,0x23,0xf0,0x43, ++0x23,0x04,0x22,0x90,0x9d,0xff,0x12,0x43,0x53,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f, ++0x78,0x7e,0x08,0x12,0x2f,0xd9,0x90,0x9e,0x03,0x12,0x43,0x53,0x90,0x80,0x85,0x12, ++0x2a,0x7f,0x7f,0x04,0x7e,0x0c,0x12,0x2f,0xd9,0x90,0x9e,0x07,0x12,0x43,0x53,0x90, ++0x80,0x85,0x12,0x2a,0x7f,0x7f,0x00,0x7e,0x08,0x12,0x2f,0xd9,0x90,0x9e,0x0b,0x12, ++0x43,0x53,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0x70,0x7e,0x0e,0x12,0x2f,0xd9,0x90, ++0x80,0x59,0x12,0x2a,0x8b,0x00,0x03,0x2d,0x95,0xe4,0xfd,0xff,0x12,0x34,0x81,0x90, ++0x9e,0x60,0xe0,0xb4,0x01,0x11,0x90,0x80,0x59,0x12,0x2a,0x8b,0x00,0x03,0x2d,0x95, ++0xe4,0xfd,0x7f,0x01,0x12,0x34,0x81,0x22,0x8f,0x27,0xe4,0x90,0x9e,0xa7,0xf0,0xa3, ++0xf0,0x90,0x01,0x09,0xe0,0x7f,0x00,0x30,0xe7,0x02,0x7f,0x01,0xef,0x65,0x27,0x60, ++0x3e,0xc3,0x90,0x9e,0xa8,0xe0,0x94,0x88,0x90,0x9e,0xa7,0xe0,0x94,0x13,0x40,0x08, ++0x90,0x01,0xc6,0xe0,0x44,0x80,0xf0,0x22,0x90,0x9e,0xa7,0xe4,0x75,0xf0,0x01,0x12, ++0x42,0x81,0x7f,0x14,0x7e,0x00,0x12,0x37,0x54,0xd3,0x90,0x9e,0xa8,0xe0,0x94,0x32, ++0x90,0x9e,0xa7,0xe0,0x94,0x00,0x40,0xb9,0x90,0x01,0xc7,0xe0,0x30,0xe0,0xb2,0x22, ++0xe5,0x24,0x30,0xe6,0x19,0xe5,0x24,0x54,0x0f,0xff,0x90,0x9e,0x62,0xe0,0xfe,0x4f, ++0x90,0x01,0x2f,0xf0,0xee,0x64,0x80,0x90,0x9e,0x62,0xf0,0x53,0x24,0xbf,0x22,0x8f, ++0x76,0x12,0x45,0xa6,0xef,0x64,0x01,0x70,0x2e,0x90,0x9e,0x53,0x12,0x47,0xcc,0xe5, ++0x76,0x60,0x10,0x74,0x21,0x2f,0xf5,0x82,0xe4,0x34,0xfc,0xf5,0x83,0xe0,0x44,0x10, ++0xf0,0x80,0x0e,0x74,0x21,0x2f,0xf5,0x82,0xe4,0x34,0xfc,0xf5,0x83,0xe0,0x54,0xef, ++0xf0,0x90,0x04,0x1f,0x74,0x20,0xf0,0x22,0xe5,0x22,0x64,0x01,0x70,0x61,0xe5,0x25, ++0x60,0x5d,0xe5,0x25,0x64,0x02,0x60,0x06,0xe5,0x25,0x64,0x05,0x70,0x27,0x90,0x06, ++0xab,0xe0,0x90,0x9e,0x64,0xf0,0x90,0x06,0xaa,0xe0,0x90,0x9e,0x72,0xf0,0x90,0x9e, ++0x64,0xe0,0x70,0x07,0x90,0x9e,0x72,0xe0,0xff,0x80,0x05,0x90,0x9e,0x64,0xe0,0xff, ++0x90,0x9e,0x64,0xef,0xf0,0x90,0x9e,0x66,0xe0,0x60,0x03,0xe0,0x14,0xf0,0xe4,0x90, ++0x9e,0x65,0xf0,0x90,0x01,0x57,0xf0,0x90,0x01,0x3c,0x74,0x02,0xf0,0x53,0x26,0xfd, ++0x53,0x26,0xef,0xe5,0x25,0x14,0x24,0xfd,0x50,0x02,0x80,0x03,0x12,0x45,0x53,0x22, ++0xe4,0xff,0xe5,0x25,0x60,0x5f,0xe5,0x22,0x64,0x01,0x70,0x59,0xe5,0x25,0x14,0x60, ++0x2b,0x24,0xfd,0x60,0x27,0x24,0x02,0x24,0xfb,0x50,0x02,0x80,0x21,0x90,0x9e,0x64, ++0xe0,0x14,0xf0,0xe0,0x60,0x04,0xa3,0xe0,0x60,0x14,0x90,0x9e,0x64,0xe0,0x70,0x08, ++0x90,0x9e,0x72,0xe0,0x90,0x9e,0x64,0xf0,0x7f,0x01,0x80,0x02,0x7f,0x01,0xef,0x60, ++0x24,0x43,0x26,0x10,0xe4,0x90,0x9e,0x86,0xf0,0x90,0x9e,0x6e,0x12,0x44,0x56,0x90, ++0x01,0x57,0x74,0x05,0xf0,0xe5,0x23,0x54,0x0f,0xc3,0x94,0x04,0x50,0x07,0x7d,0x01, ++0x7f,0x04,0x12,0x47,0x2f,0x22,0xe5,0x25,0x60,0x39,0x90,0x9e,0x74,0xe0,0x60,0x0d, ++0xe4,0xf0,0x53,0x26,0xfd,0xe5,0x26,0x54,0x07,0x70,0x28,0x80,0x23,0x90,0x9e,0x65, ++0xe0,0x04,0xf0,0x53,0x26,0xef,0x90,0x9e,0x6a,0xe0,0xff,0x90,0x9e,0x65,0xe0,0xd3, ++0x9f,0x40,0x0d,0xe5,0x22,0xb4,0x01,0x0b,0xa3,0xe0,0x70,0x07,0xe0,0x04,0xf0,0x22, ++0x12,0x44,0xd1,0x22,0xef,0xc3,0x94,0x20,0x50,0x39,0xef,0x30,0xe0,0x17,0xed,0xc4, ++0x54,0xf0,0xfd,0xef,0xc3,0x13,0xfe,0x24,0xa4,0xf5,0x82,0xe4,0x34,0x04,0xf5,0x83, ++0xe0,0x54,0x0f,0x80,0x10,0xef,0xc3,0x13,0xfe,0x24,0xa4,0xf5,0x82,0xe4,0x34,0x04, ++0xf5,0x83,0xe0,0x54,0xf0,0xf0,0x74,0xa4,0x2e,0xf5,0x82,0xe4,0x34,0x04,0xf5,0x83, ++0xe0,0x4d,0xf0,0x22,0xad,0x07,0xed,0xc3,0x94,0x20,0x50,0x0d,0x74,0x84,0x2d,0xf5, ++0x82,0xe4,0x34,0x04,0xf5,0x83,0xe0,0x80,0x0b,0x74,0xa6,0x2d,0xf5,0x82,0xe4,0x34, ++0x9c,0xf5,0x83,0xe0,0x54,0x7f,0xf5,0x64,0xe5,0x64,0x54,0x1f,0xfc,0x75,0xf0,0x09, ++0xed,0x90,0x96,0x48,0x12,0x43,0x5f,0xe0,0xff,0x90,0x9e,0x3e,0xf0,0xed,0x25,0xe0, ++0x24,0x02,0xf5,0x82,0xe4,0x34,0x95,0xf5,0x83,0xe0,0xfb,0xa3,0xe0,0x90,0x9e,0x3f, ++0xcb,0xf0,0xa3,0xeb,0xf0,0xed,0x25,0xe0,0x24,0xc6,0xf5,0x82,0xe4,0x34,0x9b,0xf5, ++0x83,0xe0,0xfb,0xa3,0xe0,0x90,0x9e,0x41,0xcb,0xf0,0xa3,0xeb,0xf0,0xec,0x25,0xe0, ++0x24,0x66,0xf5,0x82,0xe4,0x34,0x41,0xf5,0x83,0xe4,0x93,0xfa,0x74,0x01,0x93,0xfb, ++0xed,0x25,0xe0,0x24,0xc2,0xf5,0x82,0xe4,0x34,0x95,0xf5,0x83,0xea,0xf0,0xa3,0xeb, ++0xf0,0xec,0xc3,0x9f,0x40,0x02,0xe1,0x92,0x74,0x67,0x2d,0xf5,0x82,0xe4,0x34,0x9d, ++0xf5,0x83,0xec,0xf0,0x04,0xfb,0x90,0x9e,0x3e,0xe0,0xff,0xeb,0xd3,0x9f,0x40,0x02, ++0xe1,0xc3,0xeb,0xc3,0x94,0x10,0x40,0x21,0xeb,0x24,0xf0,0xff,0x74,0x01,0x7e,0x00, ++0xa8,0x07,0x08,0x80,0x05,0xc3,0x33,0xce,0x33,0xce,0xd8,0xf9,0xff,0x90,0x9e,0x3f, ++0xe0,0x5e,0xfe,0xa3,0xe0,0x5f,0x4e,0x70,0x23,0xeb,0xc3,0x94,0x10,0x50,0x40,0x74, ++0x01,0x7e,0x00,0xa8,0x03,0x08,0x80,0x05,0xc3,0x33,0xce,0x33,0xce,0xd8,0xf9,0xff, ++0x90,0x9e,0x41,0xe0,0x5e,0xfe,0xa3,0xe0,0x5f,0x4e,0x60,0x23,0xbb,0x11,0x09,0x90, ++0x9e,0x40,0xe0,0x30,0xe7,0x02,0x7b,0x17,0xeb,0x64,0x13,0x60,0x03,0xbb,0x12,0x09, ++0x90,0x9e,0x3f,0xe0,0x30,0xe0,0x02,0x7b,0x18,0xac,0x03,0x8c,0x64,0x80,0x34,0x0b, ++0x80,0x84,0x90,0x9e,0x3e,0xe0,0xfb,0x6c,0x70,0x69,0x74,0x67,0x2d,0xf5,0x82,0xe4, ++0x34,0x9d,0xf5,0x83,0xec,0xf0,0x75,0xf0,0x09,0xed,0x90,0x96,0x4a,0x12,0x43,0x5f, ++0xe0,0xb4,0x01,0x0c,0xe5,0x64,0x20,0xe6,0x07,0xec,0x44,0x40,0xf5,0x64,0x80,0x03, ++0xaf,0x64,0x22,0xec,0x25,0xe0,0x24,0x9e,0xf5,0x82,0xe4,0x34,0x41,0xf5,0x83,0xe4, ++0x93,0xfe,0x74,0x01,0x93,0xff,0xec,0x25,0xe0,0x24,0x66,0xf5,0x82,0xe4,0x34,0x41, ++0xf5,0x83,0x74,0x01,0x93,0x2f,0xff,0xe4,0x93,0x3e,0xc3,0x13,0xfe,0xef,0x13,0xff, ++0xed,0x25,0xe0,0x24,0xc2,0xf5,0x82,0xe4,0x34,0x95,0xf5,0x83,0xee,0xf0,0xa3,0xef, ++0xf0,0x80,0x5b,0xec,0xd3,0x9b,0x40,0x56,0x90,0x9e,0x3e,0xe0,0xff,0x74,0x67,0x2d, ++0xf5,0x82,0xe4,0x34,0x9d,0xf5,0x83,0xef,0xf0,0xac,0x07,0x8f,0x64,0xec,0x25,0xe0, ++0x24,0x9e,0xf5,0x82,0xe4,0x34,0x41,0xf5,0x83,0xe4,0x93,0xfe,0x74,0x01,0x93,0xff, ++0xec,0x25,0xe0,0x24,0x66,0xf5,0x82,0xe4,0x34,0x41,0xf5,0x83,0x74,0x01,0x93,0x2f, ++0xff,0xe4,0x93,0x3e,0xc3,0x13,0xfe,0xef,0x13,0xff,0xed,0x25,0xe0,0x24,0xc2,0xf5, ++0x82,0xe4,0x34,0x95,0xf5,0x83,0xee,0xf0,0xa3,0xef,0xf0,0xaf,0x64,0x22,0x74,0x01, ++0x2d,0xf5,0x82,0xe4,0x34,0x94,0xf5,0x83,0xe4,0xf0,0xaf,0x05,0xe5,0x64,0x44,0x80, ++0xfd,0x12,0x5a,0x80,0xe5,0x64,0x44,0x80,0xff,0x22,0xe4,0xf5,0x59,0xe5,0x59,0xb4, ++0x20,0x14,0x90,0x9a,0xc5,0xe0,0x04,0xf0,0x90,0x95,0x01,0xe0,0xff,0x90,0x9a,0xc5, ++0xe0,0xb5,0x07,0x02,0xe4,0xf0,0x75,0xf0,0x09,0xe5,0x59,0x90,0x96,0x4b,0x12,0x43, ++0x5f,0xe0,0x64,0x01,0x60,0x02,0xc1,0xc0,0xe5,0x59,0x25,0xe0,0x24,0x80,0xf5,0x82, ++0xe4,0x34,0x93,0xf5,0x83,0xe0,0xfe,0xa3,0xe0,0xd3,0x94,0x00,0xee,0x94,0x00,0x50, ++0x02,0xc1,0xc0,0xe5,0x59,0x94,0x20,0x40,0x08,0x90,0x9a,0xc5,0xe0,0x60,0x02,0xc1, ++0xcb,0xe5,0x59,0x75,0xf0,0x0a,0xa4,0x24,0x00,0xf9,0x74,0x90,0x35,0xf0,0x75,0x5e, ++0x01,0xf5,0x5f,0x89,0x60,0xe5,0x59,0x25,0xe0,0x24,0x80,0xf5,0x82,0xe4,0x34,0x93, ++0xf5,0x83,0xe0,0xff,0xa3,0xe0,0x90,0x9e,0x38,0xcf,0xf0,0xa3,0xef,0xf0,0xe5,0x59, ++0x25,0xe0,0x24,0xc4,0xf5,0x82,0xe4,0x34,0x98,0xf5,0x83,0xe0,0xff,0xa3,0xe0,0x90, ++0x9e,0x3a,0xcf,0xf0,0xa3,0xef,0xf0,0xe5,0x59,0xc3,0x94,0x20,0x50,0x14,0x74,0x84, ++0x25,0x59,0xf5,0x82,0xe4,0x34,0x04,0xf5,0x83,0xe0,0x54,0x3f,0x90,0x9e,0x34,0xf0, ++0x80,0x12,0x74,0xa6,0x25,0x59,0xf5,0x82,0xe4,0x34,0x9c,0xf5,0x83,0xe0,0x54,0x3f, ++0x90,0x9e,0x34,0xf0,0x90,0x9e,0x34,0xe0,0xfe,0x54,0x1f,0xa3,0xf0,0x75,0xf0,0x09, ++0xe5,0x59,0x90,0x96,0x48,0x12,0x43,0x5f,0xe0,0x90,0x9e,0x3d,0xf0,0x74,0xe6,0x25, ++0x59,0xf5,0x82,0xe4,0x34,0x9c,0xf5,0x83,0xe0,0xc3,0x94,0x05,0x40,0x02,0x61,0x99, ++0x90,0x9e,0x3d,0xe0,0xff,0x90,0x9e,0x35,0xe0,0x9f,0x40,0x13,0x90,0x9e,0x3d,0xe0, ++0x90,0x9e,0x35,0xf0,0xee,0x54,0x40,0xfe,0x90,0x9e,0x34,0xf0,0xef,0x4e,0xf0,0x90, ++0x04,0xfd,0xe0,0x54,0x05,0x64,0x01,0x70,0x29,0x90,0x9e,0x35,0xe0,0xff,0x90,0x41, ++0x4a,0x93,0xfe,0x74,0x44,0x25,0x59,0xf5,0x82,0xe4,0x34,0x9a,0xf5,0x83,0xe0,0xc3, ++0x9e,0x40,0x06,0xef,0x90,0x40,0xda,0x80,0x30,0x90,0x9e,0x35,0xe0,0x90,0x40,0xf6, ++0x80,0x27,0x90,0x9e,0x35,0xe0,0xff,0x90,0x41,0x4a,0x93,0xfe,0x74,0x44,0x25,0x59, ++0xf5,0x82,0xe4,0x34,0x9a,0xf5,0x83,0xe0,0xc3,0x9e,0x40,0x06,0xef,0x90,0x41,0x12, ++0x80,0x07,0x90,0x9e,0x35,0xe0,0x90,0x41,0x2e,0x93,0x90,0x9e,0x3c,0xf0,0x90,0x9e, ++0x3c,0xe0,0x75,0xf0,0x06,0xa4,0x24,0x50,0xf9,0x74,0x40,0x35,0xf0,0x75,0x5b,0xff, ++0xf5,0x5c,0x89,0x5d,0x90,0x9e,0x34,0xe0,0x90,0x41,0xf2,0x93,0xff,0xd3,0x90,0x9e, ++0x3b,0xe0,0x9f,0x90,0x9e,0x3a,0xe0,0x94,0x00,0x40,0x09,0xe4,0xfd,0xaf,0x59,0x12, ++0x5c,0xbd,0xc1,0x57,0xe5,0x59,0x25,0xe0,0x24,0xc2,0xf5,0x82,0xe4,0x34,0x95,0xf5, ++0x83,0xe0,0xf5,0x61,0xa3,0xe0,0xf5,0x62,0xab,0x5b,0xaa,0x5c,0xa9,0x5d,0x12,0x29, ++0xd9,0xff,0x7e,0x00,0xab,0x5e,0xaa,0x5f,0xa9,0x60,0x12,0x42,0x97,0xfd,0xac,0xf0, ++0x12,0x29,0xf2,0xef,0x25,0x62,0xf5,0x62,0xee,0x35,0x61,0xf5,0x61,0xab,0x5b,0xaa, ++0x5c,0xa9,0x5d,0x90,0x00,0x01,0x12,0x42,0x20,0xff,0x7e,0x00,0xab,0x5e,0xaa,0x5f, ++0xa9,0x60,0x90,0x00,0x02,0x12,0x42,0xc2,0xfd,0xac,0xf0,0x12,0x29,0xf2,0xef,0x25, ++0x62,0xf5,0x62,0xee,0x35,0x61,0xf5,0x61,0xab,0x5b,0xaa,0x5c,0xa9,0x5d,0x90,0x00, ++0x02,0x12,0x42,0x20,0xff,0x7e,0x00,0xab,0x5e,0xaa,0x5f,0xa9,0x60,0x90,0x00,0x04, ++0x12,0x42,0xc2,0xfd,0xac,0xf0,0x12,0x29,0xf2,0xef,0x25,0x62,0xf5,0x62,0xee,0x35, ++0x61,0xf5,0x61,0xab,0x5b,0xaa,0x5c,0xa9,0x5d,0x90,0x00,0x03,0x12,0x42,0x20,0xff, ++0x7e,0x00,0xab,0x5e,0xaa,0x5f,0xa9,0x60,0x90,0x00,0x06,0x12,0x42,0xc2,0xfd,0xac, ++0xf0,0x12,0x29,0xf2,0xef,0x25,0x62,0xf5,0x62,0xee,0x35,0x61,0xf5,0x61,0xab,0x5b, ++0xaa,0x5c,0xa9,0x5d,0x90,0x00,0x04,0x12,0x42,0x20,0xff,0x7e,0x00,0xab,0x5e,0xaa, ++0x5f,0xa9,0x60,0x90,0x00,0x08,0x12,0x42,0xc2,0xfd,0xac,0xf0,0x12,0x29,0xf2,0xef, ++0x25,0x62,0xf5,0x62,0xee,0x35,0x61,0xf5,0x61,0xab,0x5b,0xaa,0x5c,0xa9,0x5d,0x90, ++0x00,0x05,0x12,0x42,0x20,0xff,0x7e,0x00,0x90,0x9e,0x38,0xe0,0xfc,0xa3,0xe0,0xfd, ++0x12,0x29,0xf2,0xd3,0xe5,0x62,0x9f,0xe5,0x61,0x9e,0x40,0x0c,0xe5,0x62,0x9f,0xf5, ++0x62,0xe5,0x61,0x9e,0xf5,0x61,0x80,0x05,0xe4,0xf5,0x61,0xf5,0x62,0xe5,0x59,0x25, ++0xe0,0x24,0xc2,0xf5,0x82,0xe4,0x34,0x95,0xf5,0x83,0xe5,0x61,0xf0,0xa3,0xe5,0x62, ++0xf0,0x90,0x9e,0x34,0xe0,0x25,0xe0,0x24,0x66,0xf5,0x82,0xe4,0x34,0x41,0xf5,0x83, ++0xc3,0x74,0x01,0x93,0x95,0x62,0xe4,0x93,0x95,0x61,0x50,0x07,0xaf,0x59,0x12,0x66, ++0x74,0xc1,0x2b,0x90,0x9e,0x34,0xe0,0x25,0xe0,0x24,0x9e,0xf5,0x82,0xe4,0x34,0x41, ++0xf5,0x83,0xd3,0x74,0x01,0x93,0x95,0x62,0xe4,0x93,0x95,0x61,0x50,0x02,0xc1,0x2b, ++0x7d,0x01,0xaf,0x59,0x12,0x5c,0xbd,0xc1,0x2b,0x74,0xe6,0x25,0x59,0xf5,0x82,0xe4, ++0x34,0x9c,0xf5,0x83,0xe0,0xfc,0x64,0x05,0x60,0x02,0xa1,0x34,0x90,0x96,0x43,0xe0, ++0xff,0xb4,0x03,0x0b,0x90,0x9e,0x35,0xe0,0xc3,0x94,0x19,0x40,0x3d,0x80,0x2e,0xef, ++0xb4,0x02,0x0b,0x90,0x9e,0x35,0xe0,0xc3,0x94,0x11,0x40,0x2e,0x80,0x1f,0x90,0x96, ++0x43,0xe0,0xff,0xb4,0x01,0x0b,0x90,0x9e,0x35,0xe0,0xc3,0x94,0x0a,0x40,0x1b,0x80, ++0x0c,0xef,0x70,0x11,0x90,0x9e,0x35,0xe0,0xc3,0x94,0x03,0x40,0x0d,0x90,0x9a,0x84, ++0x74,0x01,0xf0,0x80,0x05,0xe4,0x90,0x9a,0x84,0xf0,0x74,0x84,0x25,0x59,0xf5,0x82, ++0xe4,0x34,0x98,0xf5,0x83,0xe0,0xf5,0x63,0x74,0x44,0x25,0x59,0xf5,0x82,0xe4,0x34, ++0x9a,0xf5,0x83,0xe0,0xff,0xc3,0x94,0x30,0x50,0x02,0x81,0xe1,0x90,0x9a,0x84,0xe0, ++0x64,0x01,0x60,0x02,0x81,0xe1,0x74,0x85,0x25,0x59,0xf5,0x82,0xe4,0x34,0x9a,0xf5, ++0x83,0xe0,0x64,0x0a,0x60,0x51,0xef,0x24,0x05,0xff,0xe4,0x33,0xfe,0x74,0x41,0x25, ++0x59,0xf5,0x82,0xe4,0x34,0x94,0xf5,0x83,0xe0,0xfd,0xd3,0x9f,0xee,0x64,0x80,0xf8, ++0x74,0x80,0x98,0x50,0x32,0xed,0x24,0x05,0xff,0xe4,0x33,0xfe,0x74,0x44,0x25,0x59, ++0xf5,0x82,0xe4,0x34,0x9a,0xf5,0x83,0xe0,0xd3,0x9f,0xee,0x64,0x80,0xf8,0x74,0x80, ++0x98,0x50,0x14,0x74,0x26,0x25,0x59,0xf5,0x82,0xe4,0x34,0x9d,0xf5,0x83,0xe0,0xff, ++0x90,0x9e,0x35,0xe0,0x6f,0x60,0x3d,0x74,0x44,0x25,0x59,0xf5,0x82,0xe4,0x34,0x9a, ++0xf5,0x83,0xe0,0xff,0xd3,0x94,0x42,0x40,0x05,0x75,0x63,0x05,0x80,0x0e,0xef,0xd3, ++0x94,0x39,0x40,0x05,0x75,0x63,0x03,0x80,0x03,0x75,0x63,0x01,0x74,0x41,0x25,0x59, ++0xf5,0x82,0xe4,0x34,0x94,0xf5,0x83,0xef,0xf0,0x74,0x85,0x25,0x59,0xf5,0x82,0xe4, ++0x34,0x9a,0x80,0x29,0x74,0xe6,0x25,0x59,0xf5,0x82,0xe4,0x34,0x9c,0xf5,0x83,0xe4, ++0xf0,0x74,0x85,0x25,0x59,0xf5,0x82,0xe4,0x34,0x9a,0xf5,0x83,0xe0,0x04,0xf0,0x80, ++0x10,0xe4,0xf5,0x63,0x74,0xe6,0x25,0x59,0xf5,0x82,0xe4,0x34,0x9c,0xf5,0x83,0xe4, ++0xf0,0x90,0x9e,0x35,0xe0,0xff,0x74,0x26,0x25,0x59,0xf5,0x82,0xe4,0x34,0x9d,0xf5, ++0x83,0xef,0xf0,0x74,0x84,0x25,0x59,0xf5,0x82,0xe4,0x34,0x98,0xf5,0x83,0xe5,0x63, ++0xf0,0x75,0xf0,0x09,0xe5,0x59,0x90,0x96,0x4c,0x12,0x43,0x5f,0xe0,0xb4,0x01,0x10, ++0xe4,0xf5,0x63,0x74,0xe6,0x25,0x59,0xf5,0x82,0xe4,0x34,0x9c,0xf5,0x83,0xe4,0xf0, ++0xad,0x63,0xc1,0x26,0xec,0x64,0x06,0x60,0x02,0xc1,0x2b,0xf5,0x61,0xf5,0x62,0x90, ++0x42,0x13,0x93,0xff,0x7e,0x00,0x90,0x9e,0x38,0xe0,0xfc,0xa3,0xe0,0xfd,0x12,0x29, ++0xf2,0x90,0x9e,0x36,0xee,0xf0,0xa3,0xef,0xf0,0x74,0x84,0x25,0x59,0xf5,0x82,0xe4, ++0x34,0x98,0xf5,0x83,0xe0,0xf5,0x63,0xe4,0xf5,0x5a,0xab,0x5e,0xaa,0x5f,0xa9,0x60, ++0x75,0xf0,0x02,0xe5,0x5a,0xa4,0xf5,0x82,0x85,0xf0,0x83,0x12,0x42,0xc2,0xfd,0xac, ++0xf0,0xe5,0x5a,0x90,0x42,0x0e,0x93,0xff,0x7e,0x00,0x12,0x29,0xf2,0xef,0x25,0x62, ++0xf5,0x62,0xee,0x35,0x61,0xf5,0x61,0xc3,0x90,0x9e,0x37,0xe0,0x95,0x62,0x90,0x9e, ++0x36,0xe0,0x95,0x61,0x40,0x07,0x05,0x5a,0xe5,0x5a,0xb4,0x05,0xbd,0xe5,0x5a,0xc3, ++0x13,0xf5,0x5a,0xe5,0x63,0xb4,0x01,0x06,0xe5,0x5a,0x70,0x46,0x80,0x13,0xe5,0x63, ++0xb4,0x03,0x15,0xe5,0x5a,0x70,0x05,0x75,0x63,0x03,0x80,0x39,0xe5,0x5a,0xb4,0x01, ++0x05,0x75,0x63,0x01,0x80,0x2f,0x80,0x2a,0xe5,0x63,0xb4,0x05,0x28,0xe5,0x5a,0x70, ++0x05,0x75,0x63,0x05,0x80,0x0d,0xe5,0x5a,0xb4,0x01,0x05,0x75,0x63,0x03,0x80,0x03, ++0x75,0x63,0x01,0xd3,0x90,0x9e,0x3b,0xe0,0x94,0x03,0x90,0x9e,0x3a,0xe0,0x94,0x00, ++0x40,0x03,0xe4,0xf5,0x63,0xd3,0x90,0x9e,0x3b,0xe0,0x94,0x03,0x90,0x9e,0x3a,0xe0, ++0x94,0x00,0x40,0x03,0xe4,0xf5,0x63,0x74,0x84,0x25,0x59,0xf5,0x82,0xe4,0x34,0x98, ++0xf5,0x83,0xe5,0x63,0xf0,0xfd,0xaf,0x59,0x12,0x66,0x34,0x74,0xe6,0x25,0x59,0xf5, ++0x82,0xe4,0x34,0x9c,0xf5,0x83,0xe0,0xd3,0x94,0x05,0x74,0xe6,0x50,0x0e,0x25,0x59, ++0xf5,0x82,0xe4,0x34,0x9c,0xf5,0x83,0xe0,0x04,0xf0,0x80,0x0b,0x25,0x59,0xf5,0x82, ++0xe4,0x34,0x9c,0xf5,0x83,0xe4,0xf0,0xab,0x5e,0xaa,0x5f,0xa9,0x60,0xe4,0xf5,0xf0, ++0x12,0x42,0xfa,0xab,0x5e,0xaa,0x5f,0xa9,0x60,0x90,0x00,0x02,0xe4,0xf5,0xf0,0x12, ++0x43,0x19,0x90,0x00,0x04,0xe4,0xf5,0xf0,0x12,0x43,0x19,0x90,0x00,0x06,0xe4,0xf5, ++0xf0,0x12,0x43,0x19,0x90,0x00,0x08,0xe4,0xf5,0xf0,0x12,0x43,0x19,0xe5,0x59,0x25, ++0xe0,0x24,0x80,0xf5,0x82,0xe4,0x34,0x93,0xf5,0x83,0xe4,0xf0,0xa3,0xf0,0xe5,0x59, ++0x25,0xe0,0x24,0xc4,0xf5,0x82,0xe4,0x34,0x98,0xf5,0x83,0xe4,0xf0,0xa3,0xf0,0xe5, ++0x59,0x25,0xe0,0x24,0x44,0xf5,0x82,0xe4,0x34,0x99,0xf5,0x83,0xe4,0xf0,0xa3,0xf0, ++0x05,0x59,0xe5,0x59,0xc3,0x94,0x40,0x50,0x02,0x01,0x7d,0x22,0x90,0x04,0x44,0x74, ++0x11,0xf0,0xa3,0x74,0xf0,0xf0,0xa3,0x74,0x0f,0xf0,0xa3,0xe4,0xf0,0xfd,0x74,0xa4, ++0x2d,0xf5,0x82,0xe4,0x34,0x04,0xf5,0x83,0xe4,0xf0,0x0d,0xbd,0x10,0xf0,0xe4,0x90, ++0x9a,0xc5,0xf0,0x90,0x95,0x01,0x04,0xf0,0xe4,0xfd,0x75,0xf0,0x0a,0xed,0x90,0x90, ++0x00,0x12,0x43,0x5f,0xe4,0xf0,0xa3,0xf0,0x75,0xf0,0x0a,0xed,0x90,0x90,0x02,0x12, ++0x43,0x5f,0xe4,0xf0,0xa3,0xf0,0x75,0xf0,0x0a,0xed,0x90,0x90,0x04,0x12,0x43,0x5f, ++0xe4,0xf0,0xa3,0xf0,0x75,0xf0,0x0a,0xed,0x90,0x90,0x06,0x12,0x43,0x5f,0xe4,0xf0, ++0xa3,0xf0,0x75,0xf0,0x0a,0xed,0x90,0x90,0x08,0x12,0x43,0x5f,0xe4,0xf0,0xa3,0xf0, ++0x74,0x26,0x2d,0xf5,0x82,0xe4,0x34,0x9d,0xf5,0x83,0x74,0x13,0xf0,0x74,0x85,0x2d, ++0xf5,0x82,0xe4,0x34,0x9a,0xf5,0x83,0xe4,0xf0,0x74,0x84,0x2d,0xf5,0x82,0xe4,0x34, ++0x98,0xf5,0x83,0xe4,0xf0,0xed,0x25,0xe0,0x24,0x80,0xf5,0x82,0xe4,0x34,0x93,0xf5, ++0x83,0xe4,0xf0,0xa3,0xf0,0xed,0x25,0xe0,0x24,0xc4,0xf5,0x82,0xe4,0x34,0x98,0xf5, ++0x83,0xe4,0xf0,0xa3,0xf0,0xed,0x25,0xe0,0x24,0xc4,0xf5,0x82,0xe4,0x34,0x99,0xf5, ++0x83,0xe4,0xf0,0xa3,0xf0,0xed,0x25,0xe0,0x24,0x44,0xf5,0x82,0xe4,0x34,0x99,0xf5, ++0x83,0xe4,0xf0,0xa3,0xf0,0xed,0x25,0xe0,0x24,0xc6,0xf5,0x82,0xe4,0x34,0x9a,0xf5, ++0x83,0xe4,0xf0,0xa3,0xf0,0xed,0x25,0xe0,0x24,0x46,0xf5,0x82,0xe4,0x34,0x9b,0xf5, ++0x83,0xe4,0xf0,0xa3,0xf0,0x74,0x86,0x2d,0xf5,0x82,0xe4,0x34,0x9c,0xf5,0x83,0xe4, ++0xf0,0x74,0x46,0x2d,0xf5,0x82,0xe4,0x34,0x9c,0xf5,0x83,0xe4,0xf0,0x74,0xe6,0x2d, ++0xf5,0x82,0xe4,0x34,0x9c,0xf5,0x83,0xe4,0xf0,0x90,0x41,0xc4,0x93,0xfe,0x74,0x01, ++0x93,0xff,0x90,0x41,0x8c,0x74,0x01,0x93,0x2f,0xff,0xe4,0x93,0x3e,0xc3,0x13,0xfe, ++0xef,0x13,0xff,0xed,0x25,0xe0,0x24,0xc2,0xf5,0x82,0xe4,0x34,0x95,0xf5,0x83,0xee, ++0xf0,0xa3,0xef,0xf0,0x75,0xf0,0x09,0xed,0x90,0x96,0x4b,0x12,0x43,0x5f,0x74,0x01, ++0xf0,0x75,0xf0,0x09,0xed,0x90,0x96,0x4a,0x12,0x43,0x5f,0x74,0x01,0xf0,0x74,0x82, ++0x2d,0xf5,0x82,0xe4,0x34,0x95,0xf5,0x83,0x74,0x0c,0xf0,0x75,0xf0,0x09,0xed,0x90, ++0x96,0x46,0x12,0x43,0x5f,0x74,0xff,0xf0,0xa3,0xf0,0x75,0xf0,0x09,0xed,0x90,0x96, ++0x44,0x12,0x43,0x5f,0xe4,0xf0,0xa3,0x74,0x0f,0xf0,0x75,0xf0,0x09,0xed,0x90,0x96, ++0x48,0x12,0x43,0x5f,0x74,0x13,0xf0,0x75,0xf0,0x09,0xed,0x90,0x96,0x49,0x12,0x43, ++0x5f,0xe4,0xf0,0xed,0xc3,0x94,0x20,0x50,0x0f,0x74,0x84,0x2d,0xf5,0x82,0xe4,0x34, ++0x04,0xf5,0x83,0x74,0x13,0xf0,0x80,0x0d,0x74,0xa6,0x2d,0xf5,0x82,0xe4,0x34,0x9c, ++0xf5,0x83,0x74,0x13,0xf0,0x0d,0xed,0x64,0x40,0x60,0x03,0x02,0x6e,0xfa,0x22,0x12, ++0x29,0xd9,0xf5,0x59,0xc3,0x94,0x40,0x50,0x15,0x90,0x00,0x02,0x12,0x42,0x20,0xff, ++0x74,0x44,0x25,0x59,0xf5,0x82,0xe4,0x34,0x9a,0xf5,0x83,0xef,0xf0,0x22,0xe5,0x59, ++0xb4,0x40,0x0a,0x90,0x00,0x02,0x12,0x42,0x20,0x90,0x96,0x42,0xf0,0x22,0x90,0x00, ++0x04,0x12,0x42,0x20,0xff,0x54,0x3f,0xfe,0xef,0x54,0x80,0xc4,0x13,0x13,0x13,0x54, ++0x01,0xfd,0xaf,0x06,0x02,0x55,0x30,0x12,0x29,0xd9,0x90,0x95,0x01,0xf0,0x22,0x12, ++0x29,0xd9,0xf5,0x22,0x22,0x90,0x00,0x02,0x12,0x42,0x20,0xff,0x30,0xe0,0x25,0x12, ++0x29,0xd9,0x90,0x9e,0x6a,0xf0,0x90,0x00,0x01,0x12,0x42,0x20,0x90,0x9e,0x6b,0xf0, ++0xef,0xc3,0x13,0x54,0x7f,0x90,0x9e,0x69,0xf0,0x90,0x00,0x03,0x12,0x42,0x20,0x90, ++0x9e,0x6f,0xf0,0x22,0x90,0x9e,0x6a,0x74,0x01,0xf0,0x90,0x9e,0x6b,0x74,0x03,0xf0, ++0x90,0x9e,0x69,0x74,0x14,0xf0,0x90,0x9e,0x6f,0x74,0x05,0xf0,0x22,0x12,0x29,0xd9, ++0x30,0xe0,0x18,0xc3,0x13,0x54,0x7f,0x90,0x9e,0x6e,0xf0,0x90,0x00,0x01,0x12,0x42, ++0x20,0xff,0x90,0x9e,0x6c,0xe4,0xf0,0xa3,0xef,0xf0,0x22,0x90,0x9e,0x6e,0x74,0x07, ++0xf0,0x90,0x9e,0x6c,0xe4,0xf0,0xa3,0x74,0x02,0xf0,0x22,0x90,0x02,0x09,0xe0,0xfd, ++0x12,0x29,0xd9,0xfe,0xaf,0x05,0xed,0x2e,0x90,0x9e,0x50,0xf0,0x90,0x00,0x01,0x12, ++0x42,0x20,0xff,0xed,0x2f,0x90,0x9e,0x51,0xf0,0x90,0x00,0x02,0x12,0x42,0x20,0xff, ++0xed,0x2f,0x90,0x9e,0x52,0xf0,0x90,0x00,0x03,0x12,0x42,0x20,0xff,0xed,0x2f,0x90, ++0x9e,0x53,0xf0,0x90,0x00,0x04,0x12,0x42,0x20,0xff,0xae,0x05,0xed,0x2f,0x90,0x9e, ++0x54,0xf0,0x22,0xd3,0x10,0xaf,0x01,0xc3,0xc0,0xd0,0x90,0x9e,0x3f,0x12,0x43,0x8b, ++0x90,0x9e,0x3f,0x12,0x43,0x6b,0x90,0x00,0x01,0x12,0x42,0xc2,0xfa,0xe5,0xf0,0x24, ++0x00,0xff,0xe4,0x3a,0xfe,0x90,0x9e,0x3f,0x12,0x43,0x6b,0x90,0x00,0x01,0xee,0x8f, ++0xf0,0x12,0x43,0x19,0x12,0x29,0xd9,0xff,0x60,0x2c,0xb5,0x71,0x16,0x90,0x9e,0x3f, ++0x12,0x43,0x6b,0x90,0x00,0x01,0x12,0x42,0xc2,0x65,0x73,0x70,0x04,0xe5,0x72,0x65, ++0xf0,0x60,0x23,0x90,0x9e,0x3f,0x12,0x43,0x6b,0x90,0x00,0x01,0x12,0x42,0xc2,0xff, ++0xae,0xf0,0x51,0x2b,0x80,0x10,0x90,0x9e,0x3f,0x12,0x43,0x6b,0x12,0x29,0xd9,0x65, ++0x71,0x60,0x03,0x12,0x44,0xc8,0xd0,0xd0,0x92,0xaf,0x22,0x90,0x9e,0x42,0xee,0xf0, ++0xa3,0xef,0xf0,0x75,0x71,0x01,0x8e,0x72,0xf5,0x73,0xe4,0xfd,0x7f,0x0b,0x51,0x6d, ++0xe4,0xfd,0x7f,0x02,0x51,0x6d,0x71,0x37,0xe4,0xff,0x71,0x99,0xe4,0xf5,0x75,0x90, ++0x01,0xc9,0xe5,0x75,0xf0,0x90,0x9e,0x42,0xe0,0xfc,0xa3,0xe0,0xfd,0xec,0xfb,0x8d, ++0x44,0xe4,0xf5,0x45,0x7d,0x01,0x7f,0x60,0x7e,0x01,0x02,0x35,0xab,0xd3,0x10,0xaf, ++0x01,0xc3,0xc0,0xd0,0x90,0x9e,0x45,0xed,0xf0,0x90,0x9e,0x44,0xef,0xf0,0xd3,0x94, ++0x07,0x50,0x4f,0xa3,0xe0,0x70,0x1a,0x90,0x9e,0x44,0xe0,0xff,0x74,0x01,0xa8,0x07, ++0x08,0x80,0x02,0xc3,0x33,0xd8,0xfc,0xf4,0xff,0x90,0x00,0x47,0xe0,0x5f,0xf0,0x80, ++0x17,0x90,0x9e,0x44,0xe0,0xff,0x74,0x01,0xa8,0x07,0x08,0x80,0x02,0xc3,0x33,0xd8, ++0xfc,0xff,0x90,0x00,0x47,0xe0,0x4f,0xf0,0x12,0x4b,0xdb,0x90,0x9e,0x44,0xe0,0xff, ++0x74,0x01,0xa8,0x07,0x08,0x80,0x02,0xc3,0x33,0xd8,0xfc,0xf4,0xff,0x90,0x00,0x46, ++0x80,0x5a,0x90,0x9e,0x44,0xe0,0x24,0xf8,0xf0,0xa3,0xe0,0x70,0x1d,0x90,0x9e,0x44, ++0xe0,0xff,0x74,0x01,0xa8,0x07,0x08,0x80,0x02,0xc3,0x33,0xd8,0xfc,0xc4,0x54,0xf0, ++0xf4,0xff,0x90,0x00,0x43,0xe0,0x5f,0xf0,0x80,0x1a,0x90,0x9e,0x44,0xe0,0xff,0x74, ++0x01,0xa8,0x07,0x08,0x80,0x02,0xc3,0x33,0xd8,0xfc,0xc4,0x54,0xf0,0xff,0x90,0x00, ++0x43,0xe0,0x4f,0xf0,0x12,0x4b,0xdb,0x90,0x9e,0x44,0xe0,0xff,0x74,0x01,0xa8,0x07, ++0x08,0x80,0x02,0xc3,0x33,0xd8,0xfc,0xf4,0xff,0x90,0x00,0x43,0xe0,0x5f,0xf0,0x12, ++0x4b,0xdb,0xd0,0xd0,0x92,0xaf,0x22,0x7f,0x0b,0x71,0xa6,0xef,0x65,0x74,0x60,0x10, ++0xe5,0x74,0xb4,0x01,0x05,0xe4,0xf5,0x74,0x80,0x03,0x75,0x74,0x01,0x7f,0x01,0x22, ++0x7f,0x00,0x22,0xe5,0x71,0x64,0x01,0x70,0x3f,0x71,0x37,0xbf,0x01,0x04,0x7f,0x01, ++0x71,0x99,0x90,0x00,0x46,0xe0,0x44,0x04,0xfd,0x7f,0x46,0x12,0x4c,0xe3,0x90,0x00, ++0x44,0xe0,0x54,0xfb,0xfd,0x7f,0x44,0x12,0x4c,0xe3,0x90,0x00,0x46,0xe0,0x54,0xfb, ++0xfd,0x7f,0x46,0x12,0x4c,0xe3,0x7f,0x02,0x71,0xa6,0x8f,0x75,0x90,0x01,0xc9,0xe5, ++0x75,0xf0,0xb4,0x01,0x03,0x12,0x4f,0xda,0x22,0x90,0x01,0xca,0xe5,0x74,0xf0,0xef, ++0x60,0x03,0x12,0x4f,0xda,0x22,0xd3,0x10,0xaf,0x01,0xc3,0xc0,0xd0,0x90,0x9e,0xb1, ++0xef,0xf0,0xd3,0x94,0x07,0x50,0x47,0xe0,0xff,0x74,0x01,0xa8,0x07,0x08,0x80,0x02, ++0xc3,0x33,0xd8,0xfc,0xf4,0xff,0x90,0x00,0x46,0xe0,0x5f,0xf0,0x12,0x4b,0xdb,0x90, ++0x9e,0xb1,0xe0,0xfd,0x74,0x01,0x7e,0x00,0xa8,0x05,0x08,0x80,0x05,0xc3,0x33,0xce, ++0x33,0xce,0xd8,0xf9,0xff,0x90,0x00,0x44,0xe0,0xfb,0xe4,0xfe,0xef,0x5b,0xa8,0x05, ++0x08,0x80,0x06,0xce,0xa2,0xe7,0x13,0xce,0x13,0xd8,0xf8,0xff,0x80,0x44,0x90,0x9e, ++0xb1,0xe0,0x24,0xf8,0xf0,0xe0,0xff,0x74,0x01,0xa8,0x07,0x08,0x80,0x02,0xc3,0x33, ++0xd8,0xfc,0x12,0x4b,0xd3,0x90,0x9e,0xb1,0xe0,0xfd,0x74,0x01,0x7e,0x00,0xa8,0x05, ++0x08,0x80,0x05,0xc3,0x33,0xce,0x33,0xce,0xd8,0xf9,0xff,0x90,0x00,0x42,0xe0,0xfb, ++0xe4,0xfe,0xef,0x5b,0xa8,0x05,0x08,0x80,0x06,0xce,0xa2,0xe7,0x13,0xce,0x13,0xd8, ++0xf8,0xff,0xd0,0xd0,0x92,0xaf,0x22,0xd3,0x10,0xaf,0x01,0xc3,0xc0,0xd0,0x90,0x9e, ++0x56,0xe0,0x90,0x9e,0x40,0xf0,0x90,0x9e,0x57,0xe0,0xf5,0x64,0xa3,0xe0,0xf5,0x65, ++0xe4,0xf5,0x61,0x74,0x59,0x25,0x61,0xf5,0x82,0xe4,0x34,0x9e,0xf5,0x83,0xe0,0xff, ++0x74,0x66,0x25,0x61,0xf8,0xa6,0x07,0x05,0x61,0xe5,0x61,0xb4,0x04,0xe5,0x90,0x9e, ++0x40,0xe0,0x12,0x43,0x94,0x74,0xa4,0x00,0x75,0xcc,0x01,0x74,0xaa,0x02,0x74,0xaa, ++0x03,0x74,0xaa,0x04,0x75,0xcc,0x05,0x75,0x9c,0x80,0x75,0xb2,0x81,0x75,0xcc,0x82, ++0x00,0x00,0x75,0xc8,0xaf,0x69,0xb1,0xd3,0xa1,0xcc,0x90,0x9e,0x40,0xe0,0xff,0xb4, ++0x02,0x08,0x90,0x9e,0x3f,0x74,0x01,0xf0,0x80,0x0f,0xef,0x90,0x9e,0x3f,0xb4,0x03, ++0x05,0x74,0x02,0xf0,0x80,0x03,0x74,0x04,0xf0,0xc3,0xe5,0x64,0x94,0x08,0x50,0x49, ++0xe4,0xf5,0x61,0x90,0x9e,0x3f,0xe0,0xff,0xe5,0x61,0xc3,0x9f,0x40,0x02,0xa1,0xcc, ++0xc3,0xe5,0x64,0x94,0x01,0x50,0x14,0xe5,0x61,0x25,0x65,0xff,0xc3,0x74,0x03,0x95, ++0x61,0x24,0x66,0xf8,0xe6,0xfd,0x12,0x4c,0xe3,0x80,0x1a,0xc3,0x74,0x03,0x95,0x61, ++0x24,0x66,0xf8,0xe6,0xff,0xe5,0x61,0x7c,0x00,0x25,0x65,0xfd,0xec,0x35,0x64,0x8d, ++0x82,0xf5,0x83,0xef,0xf0,0x05,0x61,0x80,0xba,0xc3,0xe5,0x64,0x94,0x10,0x40,0x02, ++0xa1,0xcc,0x90,0x9e,0x40,0xe0,0x64,0x04,0x60,0x02,0xa1,0xcc,0xaf,0x67,0xfc,0xfd, ++0xfe,0x78,0x10,0x12,0x2a,0x6c,0xc0,0x04,0xc0,0x05,0xc0,0x06,0xc0,0x07,0xaf,0x66, ++0xe4,0xfc,0xfd,0xfe,0x78,0x18,0x12,0x2a,0x6c,0xd0,0x03,0xd0,0x02,0xd0,0x01,0xd0, ++0x00,0x12,0x43,0x46,0xc0,0x04,0xc0,0x05,0xc0,0x06,0xc0,0x07,0xaf,0x68,0xe4,0xfc, ++0xfd,0xfe,0x78,0x08,0x12,0x2a,0x6c,0xd0,0x03,0xd0,0x02,0xd0,0x01,0xd0,0x00,0x12, ++0x43,0x46,0xa8,0x04,0xa9,0x05,0xaa,0x06,0xab,0x07,0xaf,0x69,0xe4,0xfc,0xfd,0xfe, ++0x12,0x43,0x46,0xa3,0x12,0x2a,0x7f,0x90,0x9e,0x41,0x12,0x43,0x53,0x90,0x80,0x85, ++0x12,0x2a,0x7f,0xaf,0x65,0xae,0x64,0x12,0x2f,0xd9,0x80,0x30,0xe5,0x68,0x7f,0x00, ++0xfe,0xef,0x25,0x69,0xf5,0x63,0xe4,0x3e,0xf5,0x62,0xaf,0x63,0xfe,0x12,0x37,0x54, ++0x80,0x1a,0xe5,0x68,0x7f,0x00,0xfe,0xef,0x25,0x69,0xf5,0x63,0xe4,0x3e,0xf5,0x62, ++0xaf,0x63,0xfe,0x12,0x36,0xcb,0x80,0x04,0x7f,0x00,0x80,0x02,0x7f,0x01,0xd0,0xd0, ++0x92,0xaf,0x22,0x8f,0x6a,0xe4,0x90,0x9e,0x45,0xf0,0xe5,0x6a,0x14,0xfe,0x90,0x9e, ++0x45,0xe0,0xff,0xc3,0x9e,0x50,0x0e,0xef,0x04,0xfd,0x12,0x34,0xb7,0x90,0x9e,0x45, ++0xe0,0x04,0xf0,0x80,0xe5,0xe5,0x6a,0x14,0xff,0x7d,0xff,0x12,0x34,0xb7,0x90,0x9e, ++0x45,0xe5,0x6a,0xf0,0x90,0x9e,0x45,0xe0,0xc3,0x94,0xff,0x50,0x0f,0xe0,0xff,0x04, ++0xfd,0x12,0x34,0xb7,0x90,0x9e,0x45,0xe0,0x04,0xf0,0x80,0xe8,0xad,0x6a,0x7f,0xff, ++0x02,0x34,0xb7,0xd3,0x10,0xaf,0x01,0xc3,0xc0,0xd0,0xe4,0xf5,0x5b,0x75,0x5c,0x04, ++0xf5,0x5d,0xf5,0x5f,0xf5,0x60,0x90,0x02,0x09,0xe0,0xff,0x12,0x29,0xd9,0xfe,0xef, ++0x2e,0xf5,0x5e,0x30,0xe0,0x08,0x75,0x59,0x00,0x75,0x5a,0x80,0x80,0x05,0xe4,0xf5, ++0x59,0xf5,0x5a,0xe5,0x5e,0xc3,0x13,0x90,0xfd,0x10,0xf0,0x74,0x20,0x25,0x5b,0xf5, ++0x5b,0xad,0x5a,0xe5,0x5b,0x2d,0xff,0x24,0x01,0xf5,0x82,0xe4,0x34,0xfc,0xf5,0x83, ++0xe0,0x90,0x9e,0x56,0xf0,0x74,0x02,0x2f,0xf5,0x82,0xe4,0x34,0xfc,0xf5,0x83,0xe0, ++0xfe,0xe5,0x5b,0x2d,0x24,0x03,0xf5,0x82,0xe4,0x34,0xfc,0xf5,0x83,0xe0,0x24,0x00, ++0xff,0xe4,0x3e,0x90,0x9e,0x57,0xf0,0xa3,0xef,0xf0,0x7f,0x04,0xe5,0x5b,0x25,0x5a, ++0x2f,0x24,0x00,0xf5,0x82,0xe4,0x34,0xfc,0xf5,0x83,0xe0,0xfe,0x74,0x55,0x2f,0xf5, ++0x82,0xe4,0x34,0x9e,0xf5,0x83,0xee,0xf0,0x0f,0xbf,0x08,0xe0,0x91,0x47,0xef,0x70, ++0x3f,0x90,0x01,0xc3,0xe0,0x60,0x25,0xc3,0xe5,0x60,0x94,0xe8,0xe5,0x5f,0x94,0x03, ++0x40,0x09,0x90,0x01,0xc6,0xe0,0x44,0x10,0xf0,0x80,0x63,0x05,0x60,0xe5,0x60,0x70, ++0x02,0x05,0x5f,0x7f,0x0a,0x7e,0x00,0x12,0x37,0x54,0x80,0xd5,0x90,0x01,0xc6,0xe0, ++0x90,0x01,0xc3,0x30,0xe2,0x05,0x74,0xfe,0xf0,0x80,0x43,0x74,0xff,0xf0,0x80,0x3e, ++0xe5,0x5b,0xb4,0x78,0x23,0xe4,0xf5,0x5b,0x05,0x5e,0xe5,0x5a,0x64,0x80,0x45,0x59, ++0x70,0x06,0xf5,0x59,0xf5,0x5a,0x80,0x06,0x75,0x59,0x00,0x75,0x5a,0x80,0xe5,0x5e, ++0xc3,0x13,0x90,0xfd,0x10,0xf0,0x80,0x06,0x74,0x08,0x25,0x5b,0xf5,0x5b,0xe5,0x5d, ++0x15,0x5d,0x70,0x02,0x15,0x5c,0xe5,0x5d,0x45,0x5c,0x60,0x02,0xc1,0x61,0xd0,0xd0, ++0x92,0xaf,0x22,0x90,0x06,0x34,0x74,0xff,0xf0,0xe4,0xa3,0xf0,0xa3,0xf0,0xa3,0xf0, ++0x22,0xe4,0x90,0x9e,0x5d,0xf0,0x90,0x00,0x80,0xe0,0x44,0x80,0xfd,0x7f,0x80,0x02, ++0x4c,0xe3,0x8e,0x59,0x8f,0x5a,0x8b,0x5b,0x8a,0x5c,0x89,0x5d,0xe4,0x90,0x9e,0x34, ++0xf0,0xef,0x90,0x00,0x31,0xf0,0x12,0x4b,0xdb,0xe5,0x59,0x54,0x03,0xff,0x90,0x00, ++0x32,0xe0,0x54,0xfc,0x4f,0xf0,0x12,0x4b,0xdb,0x90,0x00,0x33,0xe0,0x54,0x7f,0xf0, ++0x12,0x4b,0xdb,0x90,0x00,0x33,0xe0,0x20,0xe7,0x0e,0x90,0x9e,0x34,0xe0,0xc3,0x94, ++0x64,0x50,0x05,0xe0,0x04,0xf0,0x80,0xeb,0x90,0x9e,0x34,0xe0,0xc3,0x94,0x64,0x50, ++0x10,0x90,0x00,0x30,0xe0,0xab,0x5b,0xaa,0x5c,0xa9,0x5d,0x12,0x42,0x4d,0x7f,0x01, ++0x22,0x7f,0x00,0x22,0xe4,0xf5,0x74,0x22,0x90,0x9e,0x60,0xe0,0x90,0x9e,0x0f,0xf0, ++0x22,0xef,0x70,0x03,0x02,0x79,0x89,0x90,0x9e,0x0f,0xe0,0x60,0x03,0x02,0x7d,0x54, ++0x90,0x9d,0xfb,0x12,0x43,0x53,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0x8c,0x7e,0x08, ++0x12,0x2f,0xd9,0x90,0x9d,0xa7,0x12,0x43,0x53,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f, ++0x44,0x7e,0x08,0x12,0x2f,0xd9,0x90,0x9d,0xab,0x12,0x43,0x53,0x90,0x80,0x85,0x12, ++0x2a,0x7f,0x7f,0x5c,0x7e,0x08,0x12,0x2f,0xd9,0x90,0x9d,0xaf,0x12,0x43,0x53,0x90, ++0x80,0x85,0x12,0x2a,0x7f,0x7f,0x6c,0x7e,0x0e,0x12,0x2f,0xd9,0x90,0x9d,0xb3,0x12, ++0x43,0x53,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0x70,0x7e,0x0e,0x12,0x2f,0xd9,0x90, ++0x9d,0xb7,0x12,0x43,0x53,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0x74,0x7e,0x0e,0x12, ++0x2f,0xd9,0x90,0x9d,0xbb,0x12,0x43,0x53,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0x78, ++0x7e,0x0e,0x12,0x2f,0xd9,0x90,0x9d,0xbf,0x12,0x43,0x53,0x90,0x80,0x85,0x12,0x2a, ++0x7f,0x7f,0x7c,0x7e,0x0e,0x12,0x2f,0xd9,0x90,0x9d,0xc3,0x12,0x43,0x53,0x90,0x80, ++0x85,0x12,0x2a,0x7f,0x7f,0x80,0x7e,0x0e,0x12,0x2f,0xd9,0x90,0x9d,0xc7,0x12,0x43, ++0x53,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0x84,0x7e,0x0e,0x12,0x2f,0xd9,0x90,0x9d, ++0xcb,0x12,0x43,0x53,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0x88,0x7e,0x0e,0x12,0x2f, ++0xd9,0x90,0x9d,0xcf,0x12,0x43,0x53,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0x8c,0x7e, ++0x0e,0x12,0x2f,0xd9,0x90,0x9d,0xd3,0x12,0x43,0x53,0x90,0x80,0x85,0x12,0x2a,0x7f, ++0x7f,0xd0,0x7e,0x0e,0x12,0x2f,0xd9,0x90,0x9d,0xd7,0x12,0x43,0x53,0x90,0x80,0x85, ++0x12,0x2a,0x7f,0x7f,0xd4,0x7e,0x0e,0x12,0x2f,0xd9,0x90,0x9d,0xdb,0x12,0x43,0x53, ++0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0xd8,0x7e,0x0e,0x12,0x2f,0xd9,0x90,0x9d,0xdf, ++0x12,0x43,0x53,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0xdc,0x7e,0x0e,0x12,0x2f,0xd9, ++0x90,0x9d,0xe3,0x12,0x43,0x53,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0xe0,0x7e,0x0e, ++0x12,0x2f,0xd9,0x90,0x9d,0xe7,0x12,0x43,0x53,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f, ++0xec,0x7e,0x0e,0x12,0x2f,0xd9,0x90,0x9d,0xeb,0x12,0x43,0x53,0x90,0x80,0x85,0x12, ++0x2a,0x7f,0x7f,0x04,0x7e,0x0c,0x12,0x2f,0xd9,0x90,0x9d,0xef,0x12,0x43,0x53,0x90, ++0x80,0x85,0x12,0x2a,0x7f,0x7f,0x04,0x7e,0x0d,0x12,0x2f,0xd9,0x90,0x9d,0xf3,0x12, ++0x43,0x53,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0x0c,0x7e,0x09,0x12,0x2f,0xd9,0x90, ++0x9d,0xf7,0x12,0x43,0x53,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0x04,0x7e,0x08,0x12, ++0x2f,0xd9,0x90,0x9e,0x0f,0x74,0x01,0xf0,0x22,0x90,0x9e,0x0f,0xe0,0x64,0x01,0x60, ++0x02,0xa1,0x54,0x7f,0x8c,0x7e,0x08,0x12,0x27,0xde,0x90,0x9d,0xfb,0x12,0x2a,0x7f, ++0x7f,0x44,0x7e,0x08,0x12,0x27,0xde,0x90,0x9d,0xa7,0x12,0x2a,0x7f,0x7f,0x5c,0x7e, ++0x08,0x12,0x27,0xde,0x90,0x9d,0xab,0x12,0x2a,0x7f,0x7f,0x6c,0x7e,0x0e,0x12,0x27, ++0xde,0x90,0x9d,0xaf,0x12,0x2a,0x7f,0x7f,0x70,0x7e,0x0e,0x12,0x27,0xde,0x90,0x9d, ++0xb3,0x12,0x2a,0x7f,0x7f,0x74,0x7e,0x0e,0x12,0x27,0xde,0x90,0x9d,0xb7,0x12,0x2a, ++0x7f,0x7f,0x78,0x7e,0x0e,0x12,0x27,0xde,0x90,0x9d,0xbb,0x12,0x2a,0x7f,0x7f,0x7c, ++0x7e,0x0e,0x12,0x27,0xde,0x90,0x9d,0xbf,0x12,0x2a,0x7f,0x7f,0x80,0x7e,0x0e,0x12, ++0x27,0xde,0x90,0x9d,0xc3,0x12,0x2a,0x7f,0x7f,0x84,0x7e,0x0e,0x12,0x27,0xde,0x90, ++0x9d,0xc7,0x12,0x2a,0x7f,0x7f,0x88,0x7e,0x0e,0x12,0x27,0xde,0x90,0x9d,0xcb,0x12, ++0x2a,0x7f,0x7f,0x8c,0x7e,0x0e,0x12,0x27,0xde,0x90,0x9d,0xcf,0x12,0x2a,0x7f,0x7f, ++0xd0,0x7e,0x0e,0x12,0x27,0xde,0x90,0x9d,0xd3,0x12,0x2a,0x7f,0x7f,0xd4,0x7e,0x0e, ++0x12,0x27,0xde,0x90,0x9d,0xd7,0x12,0x2a,0x7f,0x7f,0xd8,0x7e,0x0e,0x12,0x27,0xde, ++0x90,0x9d,0xdb,0x12,0x2a,0x7f,0x7f,0xdc,0x7e,0x0e,0x12,0x27,0xde,0x90,0x9d,0xdf, ++0x12,0x2a,0x7f,0x7f,0xe0,0x7e,0x0e,0x12,0x27,0xde,0x90,0x9d,0xe3,0x12,0x2a,0x7f, ++0x7f,0xec,0x7e,0x0e,0x12,0x27,0xde,0x90,0x9d,0xe7,0x12,0x2a,0x7f,0x7f,0x04,0x7e, ++0x0c,0x12,0x27,0xde,0x90,0x9d,0xeb,0x12,0x2a,0x7f,0x7f,0x04,0x7e,0x0d,0x12,0x27, ++0xde,0x90,0x9d,0xef,0x12,0x2a,0x7f,0x7f,0x0c,0x7e,0x09,0x12,0x27,0xde,0x90,0x9d, ++0xf3,0x12,0x2a,0x7f,0x7f,0x04,0x7e,0x08,0x12,0x27,0xde,0x90,0x9d,0xf7,0x12,0x2a, ++0x7f,0x7f,0x8c,0x7e,0x08,0x12,0x27,0xde,0x90,0x9e,0xa1,0x12,0x2a,0x7f,0x90,0x9e, ++0xa1,0x12,0x43,0x53,0xed,0x44,0xc0,0xfd,0xec,0x90,0x9e,0xa1,0x12,0x2a,0x7f,0x90, ++0x9e,0xa1,0x12,0x43,0x53,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0x8c,0x7e,0x08,0x12, ++0x2f,0xd9,0x90,0x80,0x85,0x12,0x2a,0x8b,0x00,0x01,0x00,0x00,0x7f,0x44,0x7e,0x08, ++0x12,0x2f,0xd9,0x90,0x80,0x85,0x12,0x2a,0x8b,0x00,0xdb,0x25,0xa4,0x7f,0x5c,0x7e, ++0x08,0x12,0x2f,0xd9,0x90,0x80,0x85,0x12,0x2a,0x8b,0x20,0xdb,0x25,0xa4,0x7f,0x6c, ++0x7e,0x0e,0x12,0x2f,0xd9,0x90,0x80,0x85,0x12,0x2a,0x8b,0x20,0xdb,0x25,0xa4,0x7f, ++0x70,0x7e,0x0e,0x12,0x2f,0xd9,0x90,0x80,0x85,0x12,0x2a,0x8b,0x04,0x1b,0x25,0xa4, ++0x7f,0x74,0x7e,0x0e,0x12,0x2f,0xd9,0x90,0x80,0x85,0x12,0x2a,0x8b,0x04,0x1b,0x25, ++0xa4,0x7f,0x78,0x7e,0x0e,0x12,0x2f,0xd9,0x90,0x80,0x85,0x12,0x2a,0x8b,0x04,0x1b, ++0x25,0xa4,0x7f,0x7c,0x7e,0x0e,0x12,0x2f,0xd9,0x90,0x80,0x85,0x12,0x2a,0x8b,0x04, ++0x1b,0x25,0xa4,0x7f,0x80,0x7e,0x0e,0x12,0x2f,0xd9,0x90,0x80,0x85,0x12,0x2a,0x8b, ++0x63,0xdb,0x25,0xa4,0x7f,0x84,0x7e,0x0e,0x12,0x2f,0xd9,0x90,0x80,0x85,0x12,0x2a, ++0x8b,0x04,0x1b,0x25,0xa4,0x7f,0x88,0x7e,0x0e,0x12,0x2f,0xd9,0x90,0x80,0x85,0x12, ++0x2a,0x8b,0x20,0xdb,0x25,0xa4,0x7f,0x8c,0x7e,0x0e,0x12,0x2f,0xd9,0x90,0x80,0x85, ++0x12,0x2a,0x8b,0x20,0xdb,0x25,0xa4,0x7f,0xd0,0x7e,0x0e,0x12,0x2f,0xd9,0x90,0x80, ++0x85,0x12,0x2a,0x8b,0x20,0xdb,0x25,0xa4,0x7f,0xd4,0x7e,0x0e,0x12,0x2f,0xd9,0x90, ++0x80,0x85,0x12,0x2a,0x8b,0x20,0xdb,0x25,0xa4,0x7f,0xd8,0x7e,0x0e,0x12,0x2f,0xd9, ++0x90,0x80,0x85,0x12,0x2a,0x8b,0x00,0x1b,0x25,0xa4,0x7f,0xdc,0x7e,0x0e,0x12,0x2f, ++0xd9,0x90,0x80,0x85,0x12,0x2a,0x8b,0x00,0x1b,0x25,0xa4,0x7f,0xe0,0x7e,0x0e,0x12, ++0x2f,0xd9,0x90,0x80,0x85,0x12,0x2a,0x8b,0x24,0xdb,0x25,0xa4,0x7f,0xec,0x7e,0x0e, ++0x12,0x2f,0xd9,0x7f,0x04,0x7e,0x0c,0x12,0x27,0xde,0x90,0x9e,0xa1,0x12,0x2a,0x7f, ++0x90,0x9e,0xa1,0x12,0x43,0x53,0xe4,0xff,0xec,0x90,0x9e,0xa1,0x12,0x2a,0x7f,0x90, ++0x9e,0xa1,0x12,0x43,0x53,0xef,0x44,0x11,0xff,0xec,0x90,0x9e,0xa1,0x12,0x2a,0x7f, ++0x90,0x9e,0xa1,0x12,0x43,0x53,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0x04,0x7e,0x0c, ++0x12,0x2f,0xd9,0x7f,0x04,0x7e,0x0d,0x12,0x27,0xde,0x90,0x9e,0xa1,0x12,0x2a,0x7f, ++0x90,0x9e,0xa1,0x12,0x43,0x53,0xef,0x54,0xf0,0xff,0xec,0x90,0x9e,0xa1,0x12,0x2a, ++0x7f,0x90,0x9e,0xa1,0x12,0x43,0x53,0xef,0x44,0x01,0xff,0xec,0x90,0x9e,0xa1,0x12, ++0x2a,0x7f,0x90,0x9e,0xa1,0x12,0x43,0x53,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0x04, ++0x7e,0x0d,0x12,0x2f,0xd9,0x7f,0x0c,0x7e,0x09,0x12,0x27,0xde,0x90,0x9e,0xa1,0x12, ++0x2a,0x7f,0x90,0x9e,0xa1,0x12,0x43,0x53,0xe4,0xff,0xec,0x90,0x9e,0xa1,0x12,0x2a, ++0x7f,0x90,0x9e,0xa1,0x12,0x43,0x53,0xef,0x44,0x11,0xff,0xec,0x90,0x9e,0xa1,0x12, ++0x2a,0x7f,0x90,0x9e,0xa1,0x12,0x43,0x53,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0x0c, ++0x7e,0x09,0x12,0x2f,0xd9,0x7f,0x0c,0x7e,0x09,0x12,0x27,0xde,0x90,0x9e,0xa1,0x12, ++0x2a,0x7f,0x90,0x9e,0xa1,0x12,0x43,0x53,0xed,0x54,0x0f,0xfd,0xec,0x54,0xf0,0xfc, ++0x90,0x9e,0xa1,0x12,0x2a,0x7f,0x90,0x9e,0xa1,0x12,0x43,0x53,0xed,0x44,0x10,0xfd, ++0xec,0x44,0x01,0xfc,0x90,0x9e,0xa1,0x12,0x2a,0x7f,0x90,0x9e,0xa1,0x12,0x43,0x53, ++0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0x0c,0x7e,0x09,0x12,0x2f,0xd9,0x7f,0x04,0x7e, ++0x08,0x12,0x27,0xde,0x90,0x9e,0xa1,0x12,0x2a,0x7f,0x90,0x9e,0xa1,0x12,0x43,0x53, ++0xef,0x54,0xf0,0xff,0xec,0x90,0x9e,0xa1,0x12,0x2a,0x7f,0x90,0x9e,0xa1,0x12,0x43, ++0x53,0xef,0x44,0x01,0xff,0xec,0x90,0x9e,0xa1,0x12,0x2a,0x7f,0x90,0x9e,0xa1,0x12, ++0x43,0x53,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0x04,0x7e,0x08,0x12,0x2f,0xd9,0xe4, ++0x90,0x9e,0x0f,0xf0,0x22,0x90,0x00,0x02,0x12,0x42,0x20,0x90,0x9e,0x1e,0xf0,0xe0, ++0x60,0x04,0xe0,0xf4,0x70,0x21,0xa2,0xaf,0xe4,0x33,0xf5,0x59,0xc2,0xaf,0x90,0x00, ++0x47,0xe0,0x54,0xfb,0xfd,0x7f,0x47,0x12,0x4c,0xe3,0x7d,0x40,0x7f,0x01,0x12,0x36, ++0xaf,0xe5,0x59,0x24,0xff,0x92,0xaf,0x22,0xe4,0xfd,0x7f,0x45,0x12,0x4c,0xe3,0x90, ++0x04,0xfd,0xe4,0xf0,0xa3,0xf0,0x90,0x9e,0x1e,0xf0,0x90,0x9e,0x24,0xf0,0x90,0x9e, ++0x27,0xf0,0x90,0x9e,0x25,0xf0,0x90,0x9e,0x28,0xf0,0x90,0x9e,0x26,0xf0,0x90,0x9e, ++0x29,0xf0,0x90,0x9e,0x10,0x04,0xf0,0xe4,0xa3,0xf0,0xa3,0xf0,0xa3,0xf0,0x90,0x9e, ++0x15,0xf0,0x90,0x9e,0x1a,0xf0,0x90,0x9e,0x1c,0xf0,0x90,0x9e,0x2e,0xf0,0x90,0x9e, ++0x1f,0xf0,0x90,0x9e,0x1b,0xf0,0x90,0x9e,0x14,0xf0,0x90,0x00,0x51,0xe0,0x44,0xc0, ++0xfd,0x7f,0x51,0x02,0x4c,0xe3,0x90,0x9e,0x2e,0xe0,0x64,0x01,0x60,0x08,0x90,0x9e, ++0x1c,0xe0,0x60,0x02,0xc1,0xbd,0x90,0x9e,0x10,0xe0,0xc3,0x94,0xff,0x50,0x05,0xe0, ++0x04,0xf0,0x80,0x3b,0x90,0x9e,0x11,0xe0,0xc3,0x94,0xff,0x50,0x06,0xe0,0x04,0xf0, ++0xe4,0x80,0x28,0x90,0x9e,0x12,0xe0,0xc3,0x94,0xff,0x50,0x0a,0xe0,0x04,0xf0,0xe4, ++0x90,0x9e,0x11,0xf0,0x80,0x15,0x90,0x9e,0x13,0xe0,0xc3,0x94,0xff,0x50,0x10,0xe0, ++0x04,0xf0,0xe4,0x90,0x9e,0x12,0xf0,0x90,0x9e,0x11,0xf0,0x90,0x9e,0x10,0xf0,0x90, ++0x00,0x44,0xe0,0x54,0x0c,0x60,0x76,0xe0,0x30,0xe2,0x32,0x90,0x9e,0x24,0xe0,0xc3, ++0x94,0xff,0x50,0x05,0xe0,0x04,0xf0,0x80,0x24,0x90,0x9e,0x25,0xe0,0xc3,0x94,0xff, ++0x50,0x06,0xe0,0x04,0xf0,0xe4,0x80,0x11,0x90,0x9e,0x26,0xe0,0xc3,0x94,0xff,0x50, ++0x0c,0xe0,0x04,0xf0,0xe4,0x90,0x9e,0x25,0xf0,0x90,0x9e,0x24,0xf0,0x90,0x00,0x44, ++0xe0,0x30,0xe3,0x32,0x90,0x9e,0x27,0xe0,0xc3,0x94,0xff,0x50,0x05,0xe0,0x04,0xf0, ++0x80,0x24,0x90,0x9e,0x28,0xe0,0xc3,0x94,0xff,0x50,0x06,0xe0,0x04,0xf0,0xe4,0x80, ++0x11,0x90,0x9e,0x29,0xe0,0xc3,0x94,0xff,0x50,0x0c,0xe0,0x04,0xf0,0xe4,0x90,0x9e, ++0x28,0xf0,0x90,0x9e,0x27,0xf0,0x90,0x04,0xfd,0xe0,0x44,0x01,0xf0,0x22,0x17,0xed, ++}; ++ ++#endif ++ ++// ===================8723========================================= ++u8 Rtl8192CUFwUMC8723ImgArray[UMC8723ImgArrayLength] = { ++0xc1,0x88,0x02,0x00,0x39,0x00,0x01,0x00,0x09,0x09,0x16,0x47,0x80,0x3f,0x00,0x00, ++0x29,0x29,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x02,0x74,0xc9,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x02,0x59,0xd0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x02,0x73,0xab,0x00,0x00,0x00,0x00,0x00,0x02,0x67,0xfe,0x00,0x00, ++0x05,0x04,0x03,0x02,0x00,0x03,0x06,0x05,0x04,0x03,0x00,0x04,0x06,0x05,0x04,0x02, ++0x00,0x04,0x08,0x07,0x06,0x04,0x00,0x06,0x0a,0x09,0x08,0x06,0x00,0x08,0x0a,0x09, ++0x08,0x04,0x00,0x08,0x0a,0x09,0x08,0x02,0x00,0x08,0x0a,0x09,0x08,0x00,0x00,0x08, ++0x12,0x11,0x10,0x08,0x00,0x10,0x1a,0x19,0x18,0x10,0x00,0x18,0x22,0x21,0x20,0x18, ++0x00,0x20,0x22,0x21,0x20,0x10,0x00,0x20,0x22,0x21,0x20,0x08,0x00,0x20,0x22,0x21, ++0x1c,0x08,0x00,0x20,0x22,0x21,0x14,0x08,0x00,0x20,0x22,0x20,0x18,0x08,0x00,0x20, ++0x31,0x30,0x20,0x10,0x00,0x30,0x31,0x30,0x18,0x00,0x00,0x30,0x31,0x2f,0x10,0x10, ++0x00,0x30,0x31,0x2c,0x10,0x10,0x00,0x30,0x31,0x28,0x10,0x00,0x00,0x30,0x31,0x20, ++0x10,0x00,0x00,0x30,0x31,0x10,0x10,0x00,0x00,0x30,0x05,0x05,0x05,0x05,0x05,0x05, ++0x05,0x07,0x07,0x07,0x08,0x0a,0x05,0x05,0x05,0x07,0x07,0x0a,0x0d,0x0e,0x05,0x05, ++0x07,0x07,0x08,0x0c,0x14,0x14,0x05,0x05,0x05,0x05,0x09,0x09,0x09,0x09,0x0c,0x0e, ++0x13,0x13,0x09,0x09,0x0a,0x0b,0x0d,0x11,0x13,0x13,0x09,0x09,0x09,0x09,0x0c,0x14, ++0x15,0x15,0x05,0x05,0x05,0x05,0x05,0x05,0x05,0x06,0x06,0x06,0x06,0x06,0x05,0x05, ++0x05,0x06,0x06,0x06,0x06,0x06,0x05,0x05,0x06,0x06,0x06,0x06,0x06,0x06,0x05,0x05, ++0x05,0x05,0x09,0x09,0x09,0x09,0x0b,0x0d,0x10,0x12,0x05,0x09,0x0a,0x0c,0x0d,0x0e, ++0x10,0x12,0x09,0x09,0x0e,0x0e,0x10,0x10,0x12,0x12,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x24,0x26,0x2a,0x18,0x1a,0x1d,0x1f,0x21,0x27,0x29,0x2a,0x00,0x00, ++0x00,0x1f,0x23,0x28,0x2a,0x2c,0x00,0x04,0x00,0x04,0x00,0x08,0x00,0x10,0x00,0x18, ++0x00,0x24,0x00,0x30,0x00,0x48,0x00,0x60,0x00,0x90,0x00,0xc0,0x00,0xd8,0x00,0x50, ++0x00,0x78,0x00,0xa0,0x00,0xc8,0x01,0x40,0x01,0x90,0x01,0xe0,0x02,0x30,0x01,0x2c, ++0x01,0x40,0x01,0xe0,0x02,0xd0,0x03,0xe8,0x04,0xb0,0x06,0x40,0x07,0xd0,0x00,0x02, ++0x00,0x02,0x00,0x04,0x00,0x08,0x00,0x0c,0x00,0x12,0x00,0x18,0x00,0x24,0x00,0x30, ++0x00,0x48,0x00,0x60,0x00,0x6c,0x00,0x28,0x00,0x3c,0x00,0x50,0x00,0x64,0x00,0xa0, ++0x00,0xc8,0x00,0xf0,0x01,0x18,0x00,0x64,0x00,0xa0,0x00,0xf0,0x01,0x68,0x01,0xf4, ++0x02,0x58,0x03,0x20,0x03,0xe8,0x00,0x00,0x00,0x00,0x01,0x02,0x03,0x04,0x05,0x06, ++0x07,0x08,0x01,0x02,0x03,0x04,0x08,0x0f,0x23,0x3c,0x05,0x06,0x07,0x0f,0x19,0x32, ++0x4b,0x64,0x01,0x01,0x01,0x01,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x01,0x02, ++0x03,0x04,0x05,0x06,0x07,0x08,0x05,0x06,0x07,0x08,0x09,0x0a,0x0b,0x0c,0x22,0x1f, ++0x1e,0x18,0x00,0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x8f,0x17,0x74,0x42,0x90,0x01,0xc4,0xf0,0xa3,0x74,0x20,0xf0,0x74,0x84,0x25,0x17, ++0xf5,0x82,0xe4,0x34,0x04,0xf5,0x83,0xe0,0x54,0x7f,0x90,0x97,0x54,0xf0,0xe0,0xfb, ++0x54,0x1f,0xff,0xa3,0xf0,0xe5,0x17,0x75,0xf0,0x08,0xa4,0x24,0x67,0xf5,0x82,0xe4, ++0x34,0x93,0xf5,0x83,0xe0,0xfe,0x90,0x97,0x57,0xf0,0xe5,0x17,0x25,0xe0,0x24,0x81, ++0xf5,0x82,0xe4,0x34,0x92,0xf5,0x83,0xe0,0xfd,0xa3,0xe0,0x90,0x97,0x58,0xcd,0xf0, ++0xa3,0xed,0xf0,0xe5,0x17,0x25,0xe0,0x24,0xe4,0xf5,0x82,0xe4,0x34,0x95,0xf5,0x83, ++0xe0,0xfd,0xa3,0xe0,0x90,0x97,0x5a,0xcd,0xf0,0xa3,0xed,0xf0,0xef,0xc3,0x9e,0x40, ++0x03,0x02,0x43,0x56,0x90,0x01,0xc5,0x74,0x20,0xf0,0x90,0x97,0x55,0xe0,0xff,0x74, ++0xa5,0x25,0x17,0xf5,0x82,0xe4,0x34,0x96,0xf5,0x83,0xef,0xf0,0xef,0x04,0x90,0x97, ++0x56,0xf0,0x90,0x97,0x57,0xe0,0xff,0x90,0x97,0x56,0xe0,0xfe,0xd3,0x9f,0x40,0x03, ++0x02,0x43,0xa0,0xee,0xc3,0x94,0x10,0x40,0x21,0xee,0x24,0xf0,0xff,0x74,0x01,0x7e, ++0x00,0xa8,0x07,0x08,0x80,0x05,0xc3,0x33,0xce,0x33,0xce,0xd8,0xf9,0xff,0x90,0x97, ++0x58,0xe0,0x5e,0xfe,0xa3,0xe0,0x5f,0x4e,0x70,0x27,0x90,0x97,0x56,0xe0,0xff,0xc3, ++0x94,0x10,0x50,0x59,0x74,0x01,0x7e,0x00,0xa8,0x07,0x08,0x80,0x05,0xc3,0x33,0xce, ++0x33,0xce,0xd8,0xf9,0xff,0x90,0x97,0x5a,0xe0,0x5e,0xfe,0xa3,0xe0,0x5f,0x4e,0x60, ++0x3c,0x90,0x97,0x56,0xe0,0xb4,0x11,0x0d,0x90,0x97,0x59,0xe0,0x30,0xe7,0x06,0x90, ++0x97,0x56,0x74,0x17,0xf0,0x90,0x97,0x56,0xe0,0xff,0x64,0x13,0x60,0x04,0xef,0xb4, ++0x12,0x0d,0x90,0x97,0x58,0xe0,0x30,0xe0,0x06,0x90,0x97,0x56,0x74,0x18,0xf0,0x90, ++0x97,0x56,0xe0,0x90,0x97,0x55,0xf0,0x90,0x97,0x54,0xf0,0x80,0x53,0x90,0x97,0x56, ++0xe0,0x04,0xf0,0x02,0x42,0xb2,0x90,0x97,0x57,0xe0,0xf9,0x90,0x97,0x55,0xe0,0xff, ++0x69,0x60,0x03,0x02,0x43,0xe8,0x90,0x01,0xc5,0x74,0x40,0xf0,0x74,0xa5,0x25,0x17, ++0xf5,0x82,0xe4,0x34,0x96,0xf5,0x83,0xef,0xf0,0xe5,0x17,0x75,0xf0,0x08,0xa4,0x24, ++0x69,0xf5,0x82,0xe4,0x34,0x93,0xf5,0x83,0xe0,0xb4,0x01,0x14,0xeb,0x30,0xe6,0x06, ++0x90,0x97,0x54,0xe0,0xff,0x22,0x90,0x97,0x55,0xe0,0x44,0x40,0x90,0x97,0x54,0xf0, ++0x90,0x97,0x55,0xe0,0xff,0x25,0xe0,0x24,0x9e,0xf5,0x82,0xe4,0x34,0x41,0xf5,0x83, ++0xe4,0x93,0xfc,0x74,0x01,0x93,0xfd,0xef,0x25,0xe0,0x24,0x66,0xf5,0x82,0xe4,0x34, ++0x41,0xf5,0x83,0x74,0x01,0x93,0x2d,0xff,0xe4,0x93,0x3c,0xc3,0x13,0xfe,0xef,0x13, ++0xff,0xe4,0xfc,0xfd,0xe5,0x17,0x25,0xe0,0x25,0xe0,0x24,0xe1,0xf5,0x82,0xe4,0x34, ++0x92,0xf5,0x83,0x12,0x1d,0xa9,0x80,0x71,0x90,0x97,0x55,0xe0,0xd3,0x99,0x40,0x69, ++0x90,0x01,0xc5,0x74,0x60,0xf0,0x90,0x97,0x57,0xe0,0xff,0x74,0xa5,0x25,0x17,0xf5, ++0x82,0xe4,0x34,0x96,0xf5,0x83,0xef,0xf0,0x90,0x97,0x55,0xef,0xf0,0x90,0x97,0x54, ++0xf0,0xfb,0xa3,0xe0,0xff,0x25,0xe0,0x24,0x9e,0xf5,0x82,0xe4,0x34,0x41,0xf5,0x83, ++0xe4,0x93,0xfc,0x74,0x01,0x93,0xfd,0xef,0x25,0xe0,0x24,0x66,0xf5,0x82,0xe4,0x34, ++0x41,0xf5,0x83,0x74,0x01,0x93,0x2d,0xff,0xe4,0x93,0x3c,0xc3,0x13,0xfe,0xef,0x13, ++0xff,0xe4,0xfc,0xfd,0xe5,0x17,0x25,0xe0,0x25,0xe0,0x24,0xe1,0xf5,0x82,0xe4,0x34, ++0x92,0xf5,0x83,0x12,0x1d,0xa9,0xaf,0x03,0x22,0x74,0x01,0x25,0x17,0xf5,0x82,0xe4, ++0x34,0x92,0xf5,0x83,0xe4,0xf0,0x90,0x97,0x54,0xe0,0x44,0x80,0xff,0x74,0x84,0x25, ++0x17,0xf5,0x82,0xe4,0x34,0x04,0xf5,0x83,0xef,0xf0,0x22,0xef,0x14,0x60,0x20,0x14, ++0x60,0x4b,0x24,0x02,0x70,0x78,0x90,0x97,0x69,0x74,0x02,0xf0,0x90,0x00,0x48,0xe0, ++0x44,0x0c,0xf0,0x90,0x00,0x47,0xe0,0x44,0x08,0xf0,0x90,0x00,0x45,0x80,0x5b,0xe4, ++0x90,0x97,0x69,0xf0,0x90,0x97,0x65,0xe0,0xfc,0xa3,0xe0,0xfd,0xa3,0xe0,0xfe,0xa3, ++0xe0,0xff,0x90,0x81,0x56,0x12,0x1d,0xa9,0x7f,0x80,0x7e,0x08,0x12,0x33,0xd8,0x90, ++0x00,0x45,0xe0,0x44,0xef,0xf0,0xe0,0x54,0xef,0xf0,0xa3,0x80,0x2d,0x90,0x97,0x69, ++0x74,0x01,0xf0,0x90,0x97,0x6f,0xe0,0xfc,0xa3,0xe0,0xfd,0xa3,0xe0,0xfe,0xa3,0xe0, ++0xff,0x90,0x81,0x56,0x12,0x1d,0xa9,0x7f,0x80,0x7e,0x08,0x12,0x33,0xd8,0x90,0x00, ++0x45,0xe0,0x44,0x20,0xf0,0xe0,0x44,0x10,0xf0,0xa3,0xe0,0x44,0x10,0xf0,0x22,0xe4, ++0xf5,0x61,0x22,0x02,0x7f,0x69,0x02,0x7f,0x70,0x74,0x45,0x90,0x01,0xc4,0xf0,0xa3, ++0x74,0x09,0xf0,0xe4,0x90,0x97,0x3a,0xf0,0x90,0x97,0x3a,0xe0,0xff,0xc3,0x94,0x20, ++0x40,0x03,0x02,0x4e,0x3a,0xef,0x75,0xf0,0x08,0xa4,0x24,0x6a,0xf5,0x82,0xe4,0x34, ++0x93,0xf5,0x83,0xe0,0x64,0x01,0x60,0x03,0x02,0x4e,0x31,0x90,0x97,0x3a,0xe0,0x25, ++0xe0,0x24,0xc0,0xf5,0x82,0xe4,0x34,0x91,0xf5,0x83,0xe0,0xfc,0xa3,0xe0,0xd3,0x94, ++0x00,0xec,0x94,0x00,0x50,0x03,0x02,0x4e,0x31,0xef,0x75,0xf0,0x0a,0xa4,0x24,0x00, ++0xf9,0x74,0x90,0x35,0xf0,0xfa,0x7b,0x01,0x8b,0x13,0xf5,0x14,0x89,0x15,0x90,0x97, ++0x3a,0xe0,0x25,0xe0,0x24,0xc0,0xf5,0x82,0xe4,0x34,0x91,0xf5,0x83,0xe0,0xfd,0xa3, ++0xe0,0x90,0x97,0x46,0xcd,0xf0,0xa3,0xed,0xf0,0xef,0x25,0xe0,0x24,0x63,0xf5,0x82, ++0xe4,0x34,0x94,0xf5,0x83,0xe0,0xff,0xa3,0xe0,0x90,0x97,0x48,0xcf,0xf0,0xa3,0xef, ++0xf0,0x90,0x00,0x02,0x12,0x66,0x20,0xff,0xae,0xf0,0x12,0x65,0xf5,0x2f,0xff,0xe5, ++0xf0,0x3e,0x90,0x97,0x4f,0xf0,0xa3,0xef,0xf0,0x90,0x00,0x06,0x12,0x66,0x20,0xff, ++0xae,0xf0,0x90,0x00,0x04,0x12,0x66,0x20,0x2f,0xff,0xe5,0xf0,0x3e,0x90,0x97,0x4d, ++0xf0,0xa3,0xef,0xf0,0x90,0x00,0x08,0x12,0x66,0x20,0xff,0x90,0x97,0x4b,0xe5,0xf0, ++0xf0,0xa3,0xef,0xf0,0x90,0x97,0x3a,0xe0,0xfe,0x24,0x84,0xf5,0x82,0xe4,0x34,0x04, ++0xf5,0x83,0xe0,0x54,0x3f,0x90,0x97,0x3c,0xf0,0xe0,0xfd,0x54,0x1f,0xa3,0xf0,0xee, ++0x75,0xf0,0x08,0xa4,0x24,0x67,0xf5,0x82,0xe4,0x34,0x93,0xf5,0x83,0xe0,0x90,0x97, ++0x51,0xf0,0x90,0x97,0x3a,0xe0,0xfb,0x24,0x64,0xf5,0x82,0xe4,0x34,0x96,0xf5,0x83, ++0xe0,0xc3,0x94,0x05,0x40,0x03,0x02,0x49,0xc2,0x90,0x97,0x51,0xe0,0xfe,0x90,0x97, ++0x3d,0xe0,0x9e,0x40,0x13,0x90,0x97,0x51,0xe0,0x90,0x97,0x3d,0xf0,0xed,0x54,0x40, ++0xfd,0x90,0x97,0x3c,0xf0,0xee,0x4d,0xf0,0x90,0x04,0xfd,0xe0,0x64,0x01,0x70,0x28, ++0x90,0x97,0x3d,0xe0,0xff,0x90,0x41,0x4a,0x93,0xfe,0x74,0x23,0x2b,0xf5,0x82,0xe4, ++0x34,0x95,0xf5,0x83,0xe0,0xc3,0x9e,0x40,0x06,0xef,0x90,0x41,0x12,0x80,0x32,0x90, ++0x97,0x3d,0xe0,0x90,0x41,0x2e,0x80,0x29,0x90,0x97,0x3d,0xe0,0xff,0x90,0x41,0x4a, ++0x93,0xfe,0x90,0x97,0x3a,0xe0,0x24,0x23,0xf5,0x82,0xe4,0x34,0x95,0xf5,0x83,0xe0, ++0xc3,0x9e,0x40,0x06,0xef,0x90,0x40,0xda,0x80,0x07,0x90,0x97,0x3d,0xe0,0x90,0x40, ++0xf6,0x93,0x90,0x97,0x4a,0xf0,0x90,0x97,0x4a,0xe0,0x75,0xf0,0x06,0xa4,0x24,0x50, ++0xf9,0x74,0x40,0x35,0xf0,0x75,0x10,0xff,0xf5,0x11,0x89,0x12,0x90,0x97,0x3c,0xe0, ++0x90,0x41,0xf2,0x93,0xff,0xd3,0x90,0x97,0x49,0xe0,0x9f,0x90,0x97,0x48,0xe0,0x94, ++0x00,0x40,0x0d,0x90,0x97,0x3a,0xe0,0xff,0xe4,0xfd,0x12,0x5f,0x6d,0x02,0x4d,0xc7, ++0x90,0x97,0x3a,0xe0,0x25,0xe0,0x25,0xe0,0x24,0xe1,0xf5,0x82,0xe4,0x34,0x92,0xf5, ++0x83,0xe0,0xfc,0xa3,0xe0,0xfd,0xa3,0xe0,0xfe,0xa3,0xe0,0xff,0x90,0x97,0x3e,0x12, ++0x1d,0xa9,0x90,0x97,0x3e,0xe0,0xf8,0xa3,0xe0,0xf9,0xa3,0xe0,0xfa,0xa3,0xe0,0xfb, ++0xc0,0x00,0xc0,0x01,0xc0,0x02,0xc0,0x03,0xab,0x10,0xaa,0x11,0xa9,0x12,0x12,0x1c, ++0xd6,0xff,0x7e,0x00,0xab,0x13,0xaa,0x14,0xa9,0x15,0x12,0x65,0xf5,0xfd,0xac,0xf0, ++0x12,0x1d,0x1c,0xe4,0xfc,0xfd,0xd0,0x03,0xd0,0x02,0xd0,0x01,0xd0,0x00,0xeb,0x2f, ++0xff,0xea,0x3e,0xfe,0xed,0x39,0xfd,0xec,0x38,0xfc,0x90,0x97,0x3e,0x12,0x1d,0xa9, ++0x90,0x97,0x3e,0xe0,0xf8,0xa3,0xe0,0xf9,0xa3,0xe0,0xfa,0xa3,0xe0,0xfb,0xc0,0x00, ++0xc0,0x01,0xc0,0x02,0xc0,0x03,0xab,0x10,0xaa,0x11,0xa9,0x12,0x90,0x00,0x01,0x12, ++0x1c,0xef,0xff,0x7e,0x00,0xab,0x13,0xaa,0x14,0xa9,0x15,0x90,0x00,0x02,0x12,0x66, ++0x20,0xfd,0xac,0xf0,0x12,0x1d,0x1c,0xe4,0xfc,0xfd,0xd0,0x03,0xd0,0x02,0xd0,0x01, ++0xd0,0x00,0xeb,0x2f,0xff,0xea,0x3e,0xfe,0xed,0x39,0xfd,0xec,0x38,0xfc,0x90,0x97, ++0x3e,0x12,0x1d,0xa9,0x90,0x97,0x3e,0xe0,0xf8,0xa3,0xe0,0xf9,0xa3,0xe0,0xfa,0xa3, ++0xe0,0xfb,0xc0,0x00,0xc0,0x01,0xc0,0x02,0xc0,0x03,0xab,0x10,0xaa,0x11,0xa9,0x12, ++0x90,0x00,0x02,0x12,0x1c,0xef,0xff,0x7e,0x00,0xab,0x13,0xaa,0x14,0xa9,0x15,0x90, ++0x00,0x04,0x12,0x66,0x20,0xfd,0xac,0xf0,0x12,0x1d,0x1c,0xe4,0xfc,0xfd,0xd0,0x03, ++0xd0,0x02,0xd0,0x01,0xd0,0x00,0xeb,0x2f,0xff,0xea,0x3e,0xfe,0xed,0x39,0xfd,0xec, ++0x38,0xfc,0x90,0x97,0x3e,0x12,0x1d,0xa9,0x90,0x97,0x3e,0xe0,0xf8,0xa3,0xe0,0xf9, ++0xa3,0xe0,0xfa,0xa3,0xe0,0xfb,0xc0,0x00,0xc0,0x01,0xc0,0x02,0xc0,0x03,0xab,0x10, ++0xaa,0x11,0xa9,0x12,0x90,0x00,0x03,0x12,0x1c,0xef,0xff,0x7e,0x00,0xab,0x13,0xaa, ++0x14,0xa9,0x15,0x90,0x00,0x06,0x12,0x66,0x20,0xfd,0xac,0xf0,0x12,0x1d,0x1c,0xe4, ++0xfc,0xfd,0xd0,0x03,0xd0,0x02,0xd0,0x01,0xd0,0x00,0xeb,0x2f,0xff,0xea,0x3e,0xfe, ++0xed,0x39,0xfd,0xec,0x38,0xfc,0x90,0x97,0x3e,0x12,0x1d,0xa9,0x90,0x97,0x3e,0xe0, ++0xf8,0xa3,0xe0,0xf9,0xa3,0xe0,0xfa,0xa3,0xe0,0xfb,0xc0,0x00,0xc0,0x01,0xc0,0x02, ++0xc0,0x03,0xab,0x10,0xaa,0x11,0xa9,0x12,0x90,0x00,0x04,0x12,0x1c,0xef,0xff,0x7e, ++0x00,0xab,0x13,0xaa,0x14,0xa9,0x15,0x90,0x00,0x08,0x12,0x66,0x20,0xfd,0xac,0xf0, ++0x12,0x1d,0x1c,0xe4,0xfc,0xfd,0xd0,0x03,0xd0,0x02,0xd0,0x01,0xd0,0x00,0xeb,0x2f, ++0xff,0xea,0x3e,0xfe,0xed,0x39,0xfd,0xec,0x38,0xfc,0x90,0x97,0x3e,0x12,0x1d,0xa9, ++0xab,0x10,0xaa,0x11,0xa9,0x12,0x90,0x00,0x05,0x12,0x1c,0xef,0xff,0x7e,0x00,0x90, ++0x97,0x46,0xe0,0xfc,0xa3,0xe0,0xfd,0x12,0x1d,0x1c,0xe4,0xfc,0xfd,0x90,0x97,0x3e, ++0xe0,0xf8,0xa3,0xe0,0xf9,0xa3,0xe0,0xfa,0xa3,0xe0,0xfb,0xd3,0x12,0x66,0xa4,0x90, ++0x97,0x3e,0x40,0x50,0xe0,0xfc,0xa3,0xe0,0xfd,0xa3,0xe0,0xfe,0xa3,0xe0,0xff,0xc0, ++0x04,0xc0,0x05,0xc0,0x06,0xc0,0x07,0xab,0x10,0xaa,0x11,0xa9,0x12,0x90,0x00,0x05, ++0x12,0x1c,0xef,0xff,0x7e,0x00,0x90,0x97,0x46,0xe0,0xfc,0xa3,0xe0,0xfd,0x12,0x1d, ++0x1c,0xab,0x07,0xaa,0x06,0xd0,0x07,0xd0,0x06,0xd0,0x05,0xd0,0x04,0xc3,0xef,0x9b, ++0xff,0xee,0x9a,0xfe,0xed,0x94,0x00,0xfd,0xec,0x94,0x00,0xfc,0x90,0x97,0x3e,0x12, ++0x1d,0xa9,0x80,0x07,0x12,0x1d,0xb5,0x00,0x00,0x00,0x00,0x90,0x97,0x3e,0xe0,0xfc, ++0xa3,0xe0,0xfd,0xa3,0xe0,0xfe,0xa3,0xe0,0xff,0x90,0x97,0x3a,0xe0,0x25,0xe0,0x25, ++0xe0,0x24,0xe1,0xf5,0x82,0xe4,0x34,0x92,0xf5,0x83,0x12,0x1d,0xa9,0x90,0x97,0x3c, ++0xe0,0x25,0xe0,0x24,0x66,0xf5,0x82,0xe4,0x34,0x41,0xf5,0x83,0xe4,0x93,0xfe,0x74, ++0x01,0x93,0xff,0xe4,0xfc,0xfd,0x90,0x97,0x3e,0xe0,0xf8,0xa3,0xe0,0xf9,0xa3,0xe0, ++0xfa,0xa3,0xe0,0xfb,0xd3,0x12,0x66,0xa4,0x40,0x0b,0x90,0x97,0x3a,0xe0,0xff,0x12, ++0x42,0x20,0x02,0x4d,0x3e,0x90,0x97,0x3c,0xe0,0x25,0xe0,0x24,0x9e,0xf5,0x82,0xe4, ++0x34,0x41,0xf5,0x83,0xe4,0x93,0xfe,0x74,0x01,0x93,0xff,0xe4,0xfc,0xfd,0x90,0x97, ++0x3e,0xe0,0xf8,0xa3,0xe0,0xf9,0xa3,0xe0,0xfa,0xa3,0xe0,0xfb,0xc3,0x12,0x66,0xa4, ++0x40,0x03,0x02,0x4d,0x3e,0x90,0x97,0x3a,0xe0,0xff,0x7d,0x01,0x12,0x5f,0x6d,0x02, ++0x4d,0x3e,0x90,0x97,0x3a,0xe0,0xff,0x24,0x64,0xf5,0x82,0xe4,0x34,0x96,0xf5,0x83, ++0xe0,0x64,0x05,0x60,0x03,0x02,0x4b,0x8e,0x90,0x04,0xb3,0xe0,0x64,0x01,0x70,0x03, ++0x02,0x4b,0x8e,0x90,0x93,0x62,0xe0,0xfe,0xb4,0x03,0x0b,0x90,0x97,0x3d,0xe0,0xc3, ++0x94,0x19,0x40,0x3d,0x80,0x2e,0xee,0xb4,0x02,0x0b,0x90,0x97,0x3d,0xe0,0xc3,0x94, ++0x11,0x40,0x2e,0x80,0x1f,0x90,0x93,0x62,0xe0,0xfe,0xb4,0x01,0x0b,0x90,0x97,0x3d, ++0xe0,0xc3,0x94,0x0a,0x40,0x1b,0x80,0x0c,0xee,0x70,0x11,0x90,0x97,0x3d,0xe0,0xc3, ++0x94,0x03,0x40,0x0d,0x90,0x95,0x43,0x74,0x01,0xf0,0x80,0x05,0xe4,0x90,0x95,0x43, ++0xf0,0x74,0x23,0x2f,0xf5,0x82,0xe4,0x34,0x95,0xf5,0x83,0xe0,0xff,0xc3,0x94,0x30, ++0x50,0x03,0x02,0x4b,0x2d,0x90,0x95,0x43,0xe0,0x64,0x01,0x60,0x03,0x02,0x4b,0x2d, ++0x90,0x97,0x3a,0xe0,0x24,0x44,0xf5,0x82,0xe4,0x34,0x95,0xf5,0x83,0xe0,0x64,0x0a, ++0x60,0x56,0x90,0x97,0x3a,0xe0,0xfe,0xef,0x24,0x05,0xfd,0xe4,0x33,0xfc,0x74,0x21, ++0x2e,0xf5,0x82,0xe4,0x34,0x92,0xf5,0x83,0xe0,0xff,0xd3,0x9d,0xec,0x64,0x80,0xf8, ++0x74,0x80,0x98,0x50,0x33,0xef,0x24,0x05,0xfd,0xe4,0x33,0xfc,0x74,0x23,0x2e,0xf5, ++0x82,0xe4,0x34,0x95,0xf5,0x83,0xe0,0xd3,0x9d,0xec,0x64,0x80,0xf8,0x74,0x80,0x98, ++0x50,0x16,0x90,0x97,0x3a,0xe0,0x24,0x84,0xf5,0x82,0xe4,0x34,0x96,0xf5,0x83,0xe0, ++0xff,0x90,0x97,0x3d,0xe0,0x6f,0x60,0x56,0x90,0x97,0x3a,0xe0,0x24,0x23,0xf5,0x82, ++0xe4,0x34,0x95,0xf5,0x83,0xe0,0xff,0xd3,0x94,0x46,0x40,0x08,0x90,0x97,0x52,0x74, ++0x05,0xf0,0x80,0x11,0xef,0xd3,0x94,0x3c,0x90,0x97,0x52,0x40,0x05,0x74,0x03,0xf0, ++0x80,0x03,0x74,0x01,0xf0,0x90,0x97,0x3a,0xe0,0xff,0x24,0x23,0xf5,0x82,0xe4,0x34, ++0x95,0xf5,0x83,0xe0,0xfe,0x74,0x21,0x2f,0xf5,0x82,0xe4,0x34,0x92,0xf5,0x83,0xee, ++0xf0,0x90,0x97,0x3a,0xe0,0x24,0x44,0xf5,0x82,0xe4,0x34,0x95,0x80,0x2f,0x90,0x97, ++0x3a,0xe0,0xff,0x24,0x64,0xf5,0x82,0xe4,0x34,0x96,0xf5,0x83,0xe4,0xf0,0x74,0x44, ++0x2f,0xf5,0x82,0xe4,0x34,0x95,0xf5,0x83,0xe0,0x04,0xf0,0x80,0x14,0xe4,0x90,0x97, ++0x52,0xf0,0x90,0x97,0x3a,0xe0,0x24,0x64,0xf5,0x82,0xe4,0x34,0x96,0xf5,0x83,0xe4, ++0xf0,0x90,0x97,0x3d,0xe0,0xff,0x90,0x97,0x3a,0xe0,0xfe,0x24,0x84,0xf5,0x82,0xe4, ++0x34,0x96,0xf5,0x83,0xef,0xf0,0xee,0x30,0xe0,0x1e,0x90,0x97,0x52,0xe0,0xc4,0x54, ++0xf0,0xf0,0x90,0x97,0x3a,0xe0,0xc3,0x13,0xff,0x24,0xa4,0xf5,0x82,0xe4,0x34,0x04, ++0xf5,0x83,0xe0,0x54,0x0f,0x02,0x4d,0x21,0x90,0x97,0x3a,0xe0,0xc3,0x13,0xff,0x24, ++0xa4,0xf5,0x82,0xe4,0x34,0x04,0xf5,0x83,0xe0,0x54,0xf0,0x02,0x4d,0x21,0x90,0x97, ++0x3a,0xe0,0x24,0x64,0xf5,0x82,0xe4,0x34,0x96,0xf5,0x83,0xe0,0x64,0x06,0x60,0x03, ++0x02,0x4d,0x3e,0x90,0x04,0xb3,0xe0,0x64,0x01,0x70,0x03,0x02,0x4d,0x3e,0x90,0x97, ++0x3e,0x12,0x1d,0xb5,0x00,0x00,0x00,0x00,0x90,0x42,0x13,0xe4,0x93,0xff,0x7e,0x00, ++0x90,0x97,0x46,0xe0,0xfc,0xa3,0xe0,0xfd,0x12,0x1d,0x1c,0xe4,0xfc,0xfd,0x90,0x97, ++0x42,0x12,0x1d,0xa9,0xe4,0x90,0x97,0x3b,0xf0,0x90,0x97,0x3e,0xe0,0xf8,0xa3,0xe0, ++0xf9,0xa3,0xe0,0xfa,0xa3,0xe0,0xfb,0xc0,0x00,0xc0,0x01,0xc0,0x02,0xc0,0x03,0xab, ++0x13,0xaa,0x14,0xa9,0x15,0x90,0x97,0x3b,0xe0,0xff,0x75,0xf0,0x02,0xa4,0xf5,0x82, ++0x85,0xf0,0x83,0x12,0x66,0x20,0xfd,0xac,0xf0,0xef,0x90,0x42,0x0e,0x93,0xff,0x7e, ++0x00,0x12,0x1d,0x1c,0xe4,0xfc,0xfd,0xd0,0x03,0xd0,0x02,0xd0,0x01,0xd0,0x00,0xeb, ++0x2f,0xff,0xea,0x3e,0xfe,0xed,0x39,0xfd,0xec,0x38,0xfc,0x90,0x97,0x3e,0x12,0x1d, ++0xa9,0x90,0x97,0x42,0xe0,0xfc,0xa3,0xe0,0xfd,0xa3,0xe0,0xfe,0xa3,0xe0,0xff,0x90, ++0x97,0x3e,0xe0,0xf8,0xa3,0xe0,0xf9,0xa3,0xe0,0xfa,0xa3,0xe0,0xfb,0xd3,0x12,0x66, ++0xa4,0x50,0x0e,0x90,0x97,0x3b,0xe0,0x04,0xf0,0xe0,0x64,0x05,0x60,0x03,0x02,0x4b, ++0xd9,0x90,0x97,0x3b,0xe0,0xc3,0x13,0xf0,0x90,0x97,0x52,0xe0,0xff,0xb4,0x01,0x0d, ++0x90,0x97,0x3b,0xe0,0x70,0x5d,0x90,0x97,0x52,0x04,0xf0,0x80,0x5b,0xef,0xb4,0x03, ++0x1d,0x90,0x97,0x3b,0xe0,0xff,0x70,0x08,0x90,0x97,0x52,0x74,0x03,0xf0,0x80,0x48, ++0xef,0xb4,0x01,0x08,0x90,0x97,0x52,0x74,0x01,0xf0,0x80,0x3c,0x80,0x35,0x90,0x97, ++0x52,0xe0,0x64,0x05,0x70,0x32,0x90,0x97,0x3b,0xe0,0xff,0x70,0x08,0x90,0x97,0x52, ++0x74,0x05,0xf0,0x80,0x0f,0xef,0x90,0x97,0x52,0xb4,0x01,0x05,0x74,0x03,0xf0,0x80, ++0x03,0x74,0x01,0xf0,0xd3,0x90,0x97,0x49,0xe0,0x94,0x03,0x90,0x97,0x48,0xe0,0x94, ++0x00,0x40,0x05,0xe4,0x90,0x97,0x52,0xf0,0xd3,0x90,0x97,0x49,0xe0,0x94,0x03,0x90, ++0x97,0x48,0xe0,0x94,0x00,0x40,0x05,0xe4,0x90,0x97,0x52,0xf0,0x90,0x97,0x3a,0xe0, ++0xff,0x30,0xe0,0x1a,0x90,0x97,0x52,0xe0,0xc4,0x54,0xf0,0xf0,0xef,0xc3,0x13,0xff, ++0x24,0xa4,0xf5,0x82,0xe4,0x34,0x04,0xf5,0x83,0xe0,0x54,0x0f,0x80,0x13,0x90,0x97, ++0x3a,0xe0,0xc3,0x13,0xff,0x24,0xa4,0xf5,0x82,0xe4,0x34,0x04,0xf5,0x83,0xe0,0x54, ++0xf0,0xf0,0x74,0xa4,0x2f,0xf5,0x82,0xe4,0x34,0x04,0xf5,0x83,0xc0,0x83,0xc0,0x82, ++0xe0,0xff,0x90,0x97,0x52,0xe0,0xfe,0xef,0x4e,0xd0,0x82,0xd0,0x83,0xf0,0x90,0x97, ++0x3a,0xe0,0xff,0x24,0x64,0xf5,0x82,0xe4,0x34,0x96,0xf5,0x83,0xe0,0xd3,0x94,0x05, ++0x50,0x0f,0x74,0x64,0x2f,0xf5,0x82,0xe4,0x34,0x96,0xf5,0x83,0xe0,0x04,0xf0,0x80, ++0x0f,0x90,0x97,0x3a,0xe0,0x24,0x64,0xf5,0x82,0xe4,0x34,0x96,0xf5,0x83,0xe4,0xf0, ++0x90,0x97,0x3a,0xe0,0xff,0x24,0x84,0xf5,0x82,0xe4,0x34,0x04,0xf5,0x83,0xe0,0x54, ++0x1f,0xc3,0x94,0x09,0x50,0x05,0x90,0x92,0x00,0x80,0x11,0x74,0x84,0x2f,0xf5,0x82, ++0xe4,0x34,0x04,0xf5,0x83,0xe0,0x90,0x92,0x00,0x20,0xe2,0x05,0x74,0x08,0xf0,0x80, ++0x03,0x74,0x04,0xf0,0x90,0x97,0x3a,0xe0,0x60,0x0d,0x90,0x96,0xa4,0xe0,0xff,0x90, ++0x92,0x00,0xe0,0xc3,0x9f,0x50,0x08,0x90,0x92,0x00,0xe0,0x90,0x96,0xa4,0xf0,0x90, ++0x96,0xa4,0xe0,0x90,0x04,0x80,0xf0,0xab,0x13,0xaa,0x14,0xa9,0x15,0xe4,0xf5,0xf0, ++0x12,0x66,0x58,0xab,0x13,0xaa,0x14,0xa9,0x15,0x90,0x00,0x02,0xe4,0xf5,0xf0,0x12, ++0x66,0x77,0x90,0x00,0x04,0xe4,0xf5,0xf0,0x12,0x66,0x77,0x90,0x00,0x06,0xe4,0xf5, ++0xf0,0x12,0x66,0x77,0x90,0x00,0x08,0xe4,0xf5,0xf0,0x12,0x66,0x77,0x90,0x97,0x3a, ++0xe0,0xff,0x25,0xe0,0x24,0xc0,0xf5,0x82,0xe4,0x34,0x91,0xf5,0x83,0xe4,0xf0,0xa3, ++0xf0,0xef,0x25,0xe0,0x24,0x63,0xf5,0x82,0xe4,0x34,0x94,0xf5,0x83,0xe4,0xf0,0xa3, ++0xf0,0xef,0x25,0xe0,0x24,0xa3,0xf5,0x82,0xe4,0x34,0x94,0xf5,0x83,0xe4,0xf0,0xa3, ++0xf0,0x90,0x97,0x3a,0xe0,0x04,0xf0,0x02,0x45,0x18,0x22,0xef,0x70,0x03,0x02,0x50, ++0xa3,0x90,0x97,0x2d,0xe0,0x60,0x03,0x02,0x54,0xe5,0x90,0x97,0x19,0xe0,0xfc,0xa3, ++0xe0,0xfd,0xa3,0xe0,0xfe,0xa3,0xe0,0xff,0x90,0x81,0x56,0x12,0x1d,0xa9,0x7f,0x8c, ++0x7e,0x08,0x12,0x33,0xd8,0x90,0x96,0xc5,0xe0,0xfc,0xa3,0xe0,0xfd,0xa3,0xe0,0xfe, ++0xa3,0xe0,0xff,0x90,0x81,0x56,0x12,0x1d,0xa9,0x7f,0x44,0x7e,0x08,0x12,0x33,0xd8, ++0x90,0x96,0xc9,0xe0,0xfc,0xa3,0xe0,0xfd,0xa3,0xe0,0xfe,0xa3,0xe0,0xff,0x90,0x81, ++0x56,0x12,0x1d,0xa9,0x7f,0x5c,0x7e,0x08,0x12,0x33,0xd8,0x90,0x96,0xcd,0xe0,0xfc, ++0xa3,0xe0,0xfd,0xa3,0xe0,0xfe,0xa3,0xe0,0xff,0x90,0x81,0x56,0x12,0x1d,0xa9,0x7f, ++0x6c,0x7e,0x0e,0x12,0x33,0xd8,0x90,0x96,0xd1,0xe0,0xfc,0xa3,0xe0,0xfd,0xa3,0xe0, ++0xfe,0xa3,0xe0,0xff,0x90,0x81,0x56,0x12,0x1d,0xa9,0x7f,0x70,0x7e,0x0e,0x12,0x33, ++0xd8,0x90,0x96,0xd5,0xe0,0xfc,0xa3,0xe0,0xfd,0xa3,0xe0,0xfe,0xa3,0xe0,0xff,0x90, ++0x81,0x56,0x12,0x1d,0xa9,0x7f,0x74,0x7e,0x0e,0x12,0x33,0xd8,0x90,0x96,0xd9,0xe0, ++0xfc,0xa3,0xe0,0xfd,0xa3,0xe0,0xfe,0xa3,0xe0,0xff,0x90,0x81,0x56,0x12,0x1d,0xa9, ++0x7f,0x78,0x7e,0x0e,0x12,0x33,0xd8,0x90,0x96,0xdd,0xe0,0xfc,0xa3,0xe0,0xfd,0xa3, ++0xe0,0xfe,0xa3,0xe0,0xff,0x90,0x81,0x56,0x12,0x1d,0xa9,0x7f,0x7c,0x7e,0x0e,0x12, ++0x33,0xd8,0x90,0x96,0xe1,0xe0,0xfc,0xa3,0xe0,0xfd,0xa3,0xe0,0xfe,0xa3,0xe0,0xff, ++0x90,0x81,0x56,0x12,0x1d,0xa9,0x7f,0x80,0x7e,0x0e,0x12,0x33,0xd8,0x90,0x96,0xe5, ++0xe0,0xfc,0xa3,0xe0,0xfd,0xa3,0xe0,0xfe,0xa3,0xe0,0xff,0x90,0x81,0x56,0x12,0x1d, ++0xa9,0x7f,0x84,0x7e,0x0e,0x12,0x33,0xd8,0x90,0x96,0xe9,0xe0,0xfc,0xa3,0xe0,0xfd, ++0xa3,0xe0,0xfe,0xa3,0xe0,0xff,0x90,0x81,0x56,0x12,0x1d,0xa9,0x7f,0x88,0x7e,0x0e, ++0x12,0x33,0xd8,0x90,0x96,0xed,0xe0,0xfc,0xa3,0xe0,0xfd,0xa3,0xe0,0xfe,0xa3,0xe0, ++0xff,0x90,0x81,0x56,0x12,0x1d,0xa9,0x7f,0x8c,0x7e,0x0e,0x12,0x33,0xd8,0x90,0x96, ++0xf1,0xe0,0xfc,0xa3,0xe0,0xfd,0xa3,0xe0,0xfe,0xa3,0xe0,0xff,0x90,0x81,0x56,0x12, ++0x1d,0xa9,0x7f,0xd0,0x7e,0x0e,0x12,0x33,0xd8,0x90,0x96,0xf5,0xe0,0xfc,0xa3,0xe0, ++0xfd,0xa3,0xe0,0xfe,0xa3,0xe0,0xff,0x90,0x81,0x56,0x12,0x1d,0xa9,0x7f,0xd4,0x7e, ++0x0e,0x12,0x33,0xd8,0x90,0x96,0xf9,0xe0,0xfc,0xa3,0xe0,0xfd,0xa3,0xe0,0xfe,0xa3, ++0xe0,0xff,0x90,0x81,0x56,0x12,0x1d,0xa9,0x7f,0xd8,0x7e,0x0e,0x12,0x33,0xd8,0x90, ++0x96,0xfd,0xe0,0xfc,0xa3,0xe0,0xfd,0xa3,0xe0,0xfe,0xa3,0xe0,0xff,0x90,0x81,0x56, ++0x12,0x1d,0xa9,0x7f,0xdc,0x7e,0x0e,0x12,0x33,0xd8,0x90,0x97,0x01,0xe0,0xfc,0xa3, ++0xe0,0xfd,0xa3,0xe0,0xfe,0xa3,0xe0,0xff,0x90,0x81,0x56,0x12,0x1d,0xa9,0x7f,0xe0, ++0x7e,0x0e,0x12,0x33,0xd8,0x90,0x97,0x05,0xe0,0xfc,0xa3,0xe0,0xfd,0xa3,0xe0,0xfe, ++0xa3,0xe0,0xff,0x90,0x81,0x56,0x12,0x1d,0xa9,0x7f,0xec,0x7e,0x0e,0x12,0x33,0xd8, ++0x90,0x97,0x09,0xe0,0xfc,0xa3,0xe0,0xfd,0xa3,0xe0,0xfe,0xa3,0xe0,0xff,0x90,0x81, ++0x56,0x12,0x1d,0xa9,0x7f,0x04,0x7e,0x0c,0x12,0x33,0xd8,0x90,0x97,0x0d,0xe0,0xfc, ++0xa3,0xe0,0xfd,0xa3,0xe0,0xfe,0xa3,0xe0,0xff,0x90,0x81,0x56,0x12,0x1d,0xa9,0x7f, ++0x04,0x7e,0x0d,0x12,0x33,0xd8,0x90,0x97,0x11,0xe0,0xfc,0xa3,0xe0,0xfd,0xa3,0xe0, ++0xfe,0xa3,0xe0,0xff,0x90,0x81,0x56,0x12,0x1d,0xa9,0x7f,0x0c,0x7e,0x09,0x12,0x33, ++0xd8,0x90,0x97,0x15,0xe0,0xfc,0xa3,0xe0,0xfd,0xa3,0xe0,0xfe,0xa3,0xe0,0xff,0x90, ++0x81,0x56,0x12,0x1d,0xa9,0x7f,0x04,0x7e,0x08,0x12,0x33,0xd8,0x90,0x97,0x2d,0x74, ++0x01,0xf0,0x22,0x90,0x97,0x2d,0xe0,0x64,0x01,0x60,0x03,0x02,0x54,0xe5,0x7f,0x8c, ++0x7e,0x08,0x12,0x2b,0x13,0x90,0x97,0x19,0x12,0x1d,0xa9,0x7f,0x44,0x7e,0x08,0x12, ++0x2b,0x13,0x90,0x96,0xc5,0x12,0x1d,0xa9,0x7f,0x5c,0x7e,0x08,0x12,0x2b,0x13,0x90, ++0x96,0xc9,0x12,0x1d,0xa9,0x7f,0x6c,0x7e,0x0e,0x12,0x2b,0x13,0x90,0x96,0xcd,0x12, ++0x1d,0xa9,0x7f,0x70,0x7e,0x0e,0x12,0x2b,0x13,0x90,0x96,0xd1,0x12,0x1d,0xa9,0x7f, ++0x74,0x7e,0x0e,0x12,0x2b,0x13,0x90,0x96,0xd5,0x12,0x1d,0xa9,0x7f,0x78,0x7e,0x0e, ++0x12,0x2b,0x13,0x90,0x96,0xd9,0x12,0x1d,0xa9,0x7f,0x7c,0x7e,0x0e,0x12,0x2b,0x13, ++0x90,0x96,0xdd,0x12,0x1d,0xa9,0x7f,0x80,0x7e,0x0e,0x12,0x2b,0x13,0x90,0x96,0xe1, ++0x12,0x1d,0xa9,0x7f,0x84,0x7e,0x0e,0x12,0x2b,0x13,0x90,0x96,0xe5,0x12,0x1d,0xa9, ++0x7f,0x88,0x7e,0x0e,0x12,0x2b,0x13,0x90,0x96,0xe9,0x12,0x1d,0xa9,0x7f,0x8c,0x7e, ++0x0e,0x12,0x2b,0x13,0x90,0x96,0xed,0x12,0x1d,0xa9,0x7f,0xd0,0x7e,0x0e,0x12,0x2b, ++0x13,0x90,0x96,0xf1,0x12,0x1d,0xa9,0x7f,0xd4,0x7e,0x0e,0x12,0x2b,0x13,0x90,0x96, ++0xf5,0x12,0x1d,0xa9,0x7f,0xd8,0x7e,0x0e,0x12,0x2b,0x13,0x90,0x96,0xf9,0x12,0x1d, ++0xa9,0x7f,0xdc,0x7e,0x0e,0x12,0x2b,0x13,0x90,0x96,0xfd,0x12,0x1d,0xa9,0x7f,0xe0, ++0x7e,0x0e,0x12,0x2b,0x13,0x90,0x97,0x01,0x12,0x1d,0xa9,0x7f,0xec,0x7e,0x0e,0x12, ++0x2b,0x13,0x90,0x97,0x05,0x12,0x1d,0xa9,0x7f,0x04,0x7e,0x0c,0x12,0x2b,0x13,0x90, ++0x97,0x09,0x12,0x1d,0xa9,0x7f,0x04,0x7e,0x0d,0x12,0x2b,0x13,0x90,0x97,0x0d,0x12, ++0x1d,0xa9,0x7f,0x0c,0x7e,0x09,0x12,0x2b,0x13,0x90,0x97,0x11,0x12,0x1d,0xa9,0x7f, ++0x04,0x7e,0x08,0x12,0x2b,0x13,0x90,0x97,0x15,0x12,0x1d,0xa9,0x7f,0x8c,0x7e,0x08, ++0x12,0x2b,0x13,0x90,0x97,0xa3,0x12,0x1d,0xa9,0x90,0x97,0xa3,0xe0,0xfc,0xa3,0xe0, ++0xfd,0xa3,0xe0,0xfe,0xa3,0xe0,0xff,0xed,0x44,0xc0,0xfd,0xec,0x90,0x97,0xa3,0x12, ++0x1d,0xa9,0x90,0x97,0xa3,0xe0,0xfc,0xa3,0xe0,0xfd,0xa3,0xe0,0xfe,0xa3,0xe0,0xff, ++0x90,0x81,0x56,0x12,0x1d,0xa9,0x7f,0x8c,0x7e,0x08,0x12,0x33,0xd8,0x90,0x81,0x56, ++0x12,0x1d,0xb5,0x00,0x01,0x00,0x00,0x7f,0x44,0x7e,0x08,0x12,0x33,0xd8,0x90,0x81, ++0x56,0x12,0x1d,0xb5,0x00,0xdb,0x25,0xa4,0x7f,0x5c,0x7e,0x08,0x12,0x33,0xd8,0x90, ++0x81,0x56,0x12,0x1d,0xb5,0x20,0xdb,0x25,0xa4,0x7f,0x6c,0x7e,0x0e,0x12,0x33,0xd8, ++0x90,0x81,0x56,0x12,0x1d,0xb5,0x20,0xdb,0x25,0xa4,0x7f,0x70,0x7e,0x0e,0x12,0x33, ++0xd8,0x90,0x81,0x56,0x12,0x1d,0xb5,0x04,0x1b,0x25,0xa4,0x7f,0x74,0x7e,0x0e,0x12, ++0x33,0xd8,0x90,0x81,0x56,0x12,0x1d,0xb5,0x04,0x1b,0x25,0xa4,0x7f,0x78,0x7e,0x0e, ++0x12,0x33,0xd8,0x90,0x81,0x56,0x12,0x1d,0xb5,0x04,0x1b,0x25,0xa4,0x7f,0x7c,0x7e, ++0x0e,0x12,0x33,0xd8,0x90,0x81,0x56,0x12,0x1d,0xb5,0x04,0x1b,0x25,0xa4,0x7f,0x80, ++0x7e,0x0e,0x12,0x33,0xd8,0x90,0x81,0x56,0x12,0x1d,0xb5,0x63,0xdb,0x25,0xa4,0x7f, ++0x84,0x7e,0x0e,0x12,0x33,0xd8,0x90,0x81,0x56,0x12,0x1d,0xb5,0x04,0x1b,0x25,0xa4, ++0x7f,0x88,0x7e,0x0e,0x12,0x33,0xd8,0x90,0x81,0x56,0x12,0x1d,0xb5,0x20,0xdb,0x25, ++0xa4,0x7f,0x8c,0x7e,0x0e,0x12,0x33,0xd8,0x90,0x81,0x56,0x12,0x1d,0xb5,0x20,0xdb, ++0x25,0xa4,0x7f,0xd0,0x7e,0x0e,0x12,0x33,0xd8,0x90,0x81,0x56,0x12,0x1d,0xb5,0x20, ++0xdb,0x25,0xa4,0x7f,0xd4,0x7e,0x0e,0x12,0x33,0xd8,0x90,0x81,0x56,0x12,0x1d,0xb5, ++0x20,0xdb,0x25,0xa4,0x7f,0xd8,0x7e,0x0e,0x12,0x33,0xd8,0x90,0x81,0x56,0x12,0x1d, ++0xb5,0x00,0x1b,0x25,0xa4,0x7f,0xdc,0x7e,0x0e,0x12,0x33,0xd8,0x90,0x81,0x56,0x12, ++0x1d,0xb5,0x00,0x1b,0x25,0xa4,0x7f,0xe0,0x7e,0x0e,0x12,0x33,0xd8,0x90,0x81,0x56, ++0x12,0x1d,0xb5,0x24,0xdb,0x25,0xa4,0x7f,0xec,0x7e,0x0e,0x12,0x33,0xd8,0x7f,0x04, ++0x7e,0x0c,0x12,0x2b,0x13,0x90,0x97,0xa3,0x12,0x1d,0xa9,0x90,0x97,0xa3,0xe0,0xfc, ++0xa3,0xe0,0xfd,0xa3,0xe0,0xfe,0xe4,0xff,0xec,0x90,0x97,0xa3,0x12,0x1d,0xa9,0x90, ++0x97,0xa3,0xe0,0xfc,0xa3,0xe0,0xfd,0xa3,0xe0,0xfe,0xa3,0xe0,0x44,0x11,0xff,0xec, ++0x90,0x97,0xa3,0x12,0x1d,0xa9,0x90,0x97,0xa3,0xe0,0xfc,0xa3,0xe0,0xfd,0xa3,0xe0, ++0xfe,0xa3,0xe0,0xff,0x90,0x81,0x56,0x12,0x1d,0xa9,0x7f,0x04,0x7e,0x0c,0x12,0x33, ++0xd8,0x7f,0x04,0x7e,0x0d,0x12,0x2b,0x13,0x90,0x97,0xa3,0x12,0x1d,0xa9,0x90,0x97, ++0xa3,0xe0,0xfc,0xa3,0xe0,0xfd,0xa3,0xe0,0xfe,0xa3,0xe0,0x54,0xf0,0xff,0xec,0x90, ++0x97,0xa3,0x12,0x1d,0xa9,0x90,0x97,0xa3,0xe0,0xfc,0xa3,0xe0,0xfd,0xa3,0xe0,0xfe, ++0xa3,0xe0,0x44,0x01,0xff,0xec,0x90,0x97,0xa3,0x12,0x1d,0xa9,0x90,0x97,0xa3,0xe0, ++0xfc,0xa3,0xe0,0xfd,0xa3,0xe0,0xfe,0xa3,0xe0,0xff,0x90,0x81,0x56,0x12,0x1d,0xa9, ++0x7f,0x04,0x7e,0x0d,0x12,0x33,0xd8,0x7f,0x0c,0x7e,0x09,0x12,0x2b,0x13,0x90,0x97, ++0xa3,0x12,0x1d,0xa9,0x90,0x97,0xa3,0xe0,0xfc,0xa3,0xe0,0xfd,0xa3,0xe0,0xfe,0xe4, ++0xff,0xec,0x90,0x97,0xa3,0x12,0x1d,0xa9,0x90,0x97,0xa3,0xe0,0xfc,0xa3,0xe0,0xfd, ++0xa3,0xe0,0xfe,0xa3,0xe0,0x44,0x11,0xff,0xec,0x90,0x97,0xa3,0x12,0x1d,0xa9,0x90, ++0x97,0xa3,0xe0,0xfc,0xa3,0xe0,0xfd,0xa3,0xe0,0xfe,0xa3,0xe0,0xff,0x90,0x81,0x56, ++0x12,0x1d,0xa9,0x7f,0x0c,0x7e,0x09,0x12,0x33,0xd8,0x7f,0x0c,0x7e,0x09,0x12,0x2b, ++0x13,0x90,0x97,0xa3,0x12,0x1d,0xa9,0x90,0x97,0xa3,0xe0,0xfc,0xa3,0xe0,0xfd,0xa3, ++0xe0,0xfe,0xa3,0xe0,0xff,0xed,0x54,0x0f,0xfd,0xec,0x54,0xf0,0xfc,0x90,0x97,0xa3, ++0x12,0x1d,0xa9,0x90,0x97,0xa3,0xe0,0xfc,0xa3,0xe0,0xfd,0xa3,0xe0,0xfe,0xa3,0xe0, ++0xff,0xed,0x44,0x10,0xfd,0xec,0x44,0x01,0xfc,0x90,0x97,0xa3,0x12,0x1d,0xa9,0x90, ++0x97,0xa3,0xe0,0xfc,0xa3,0xe0,0xfd,0xa3,0xe0,0xfe,0xa3,0xe0,0xff,0x90,0x81,0x56, ++0x12,0x1d,0xa9,0x7f,0x0c,0x7e,0x09,0x12,0x33,0xd8,0x7f,0x04,0x7e,0x08,0x12,0x2b, ++0x13,0x90,0x97,0xa3,0x12,0x1d,0xa9,0x90,0x97,0xa3,0xe0,0xfc,0xa3,0xe0,0xfd,0xa3, ++0xe0,0xfe,0xa3,0xe0,0x54,0xf0,0xff,0xec,0x90,0x97,0xa3,0x12,0x1d,0xa9,0x90,0x97, ++0xa3,0xe0,0xfc,0xa3,0xe0,0xfd,0xa3,0xe0,0xfe,0xa3,0xe0,0x44,0x01,0xff,0xec,0x90, ++0x97,0xa3,0x12,0x1d,0xa9,0x90,0x97,0xa3,0xe0,0xfc,0xa3,0xe0,0xfd,0xa3,0xe0,0xfe, ++0xa3,0xe0,0xff,0x90,0x81,0x56,0x12,0x1d,0xa9,0x7f,0x04,0x7e,0x08,0x12,0x33,0xd8, ++0xe4,0x90,0x97,0x2d,0xf0,0x22,0x8f,0x10,0xef,0x25,0xe0,0x24,0xe4,0xf5,0x82,0xe4, ++0x34,0x95,0xaf,0x82,0xf5,0x11,0x8f,0x12,0xe5,0x10,0x75,0xf0,0x02,0xa4,0x24,0x81, ++0xf9,0x74,0x92,0x35,0xf0,0x75,0x13,0x01,0xf5,0x14,0x89,0x15,0xe5,0x10,0x75,0xf0, ++0x08,0xa4,0x24,0x65,0xf5,0x82,0xe4,0x34,0x93,0xaf,0x82,0xf5,0x16,0x8f,0x17,0xe5, ++0x10,0x75,0xf0,0x08,0xa4,0x24,0x63,0xf9,0x74,0x93,0x35,0xf0,0x75,0x18,0x01,0xf5, ++0x19,0x89,0x1a,0x74,0xc1,0x25,0x10,0xf5,0x82,0xe4,0x34,0x92,0xf5,0x83,0xe0,0x12, ++0x66,0xc1,0x55,0x67,0x00,0x55,0x7c,0x01,0x55,0x91,0x02,0x55,0xa6,0x03,0x55,0xd0, ++0x04,0x55,0xe5,0x05,0x55,0xfa,0x06,0x56,0x21,0x0c,0x56,0x4f,0x0d,0x56,0x7c,0x0e, ++0x56,0xa9,0x0f,0x00,0x00,0x56,0xdd,0xe5,0x10,0x25,0xe0,0x24,0xe4,0xf5,0x82,0xe4, ++0x34,0x95,0xf5,0x83,0x74,0xf0,0xf0,0xa3,0x74,0x15,0x80,0x3c,0xe5,0x10,0x25,0xe0, ++0x24,0xe4,0xf5,0x82,0xe4,0x34,0x95,0xf5,0x83,0x74,0xf0,0xf0,0xa3,0x74,0x10,0x80, ++0x27,0xe5,0x10,0x25,0xe0,0x24,0xe4,0xf5,0x82,0xe4,0x34,0x95,0xf5,0x83,0x74,0xf0, ++0xf0,0xa3,0x74,0x05,0x80,0x12,0xe5,0x10,0x25,0xe0,0x24,0xe4,0xf5,0x82,0xe4,0x34, ++0x95,0xf5,0x83,0x74,0xf0,0xf0,0xa3,0xe4,0xf0,0xe5,0x10,0x25,0xe0,0x24,0x81,0xf5, ++0x82,0xe4,0x34,0x92,0xf5,0x83,0x74,0x0f,0xf0,0xa3,0x74,0x8f,0xf0,0x02,0x56,0xdd, ++0xe5,0x10,0x25,0xe0,0x24,0xe4,0xf5,0x82,0xe4,0x34,0x95,0xf5,0x83,0x74,0x0f,0xf0, ++0xa3,0x74,0xf5,0x80,0x27,0xe5,0x10,0x25,0xe0,0x24,0xe4,0xf5,0x82,0xe4,0x34,0x95, ++0xf5,0x83,0x74,0x0f,0xf0,0xa3,0x74,0xf0,0x80,0x12,0xe5,0x10,0x25,0xe0,0x24,0xe4, ++0xf5,0x82,0xe4,0x34,0x95,0xf5,0x83,0xe4,0xf0,0xa3,0x74,0x0d,0xf0,0xe5,0x10,0x25, ++0xe0,0x24,0x81,0xf5,0x82,0xe4,0x34,0x92,0xf5,0x83,0xe4,0xf0,0xa3,0xf0,0x02,0x56, ++0xdd,0x90,0x04,0x47,0xe0,0xab,0x13,0xaa,0x14,0xa9,0x15,0x12,0x65,0x95,0x90,0x04, ++0x46,0xe0,0xab,0x13,0xaa,0x14,0xa9,0x15,0x90,0x00,0x01,0x12,0x65,0xa7,0x90,0x04, ++0x45,0xe0,0x85,0x12,0x82,0x85,0x11,0x83,0xf0,0x90,0x04,0x44,0x02,0x56,0xd4,0x90, ++0x04,0x4b,0xe0,0xab,0x13,0xaa,0x14,0xa9,0x15,0x12,0x65,0x95,0x90,0x04,0x4a,0xe0, ++0xab,0x13,0xaa,0x14,0xa9,0x15,0x90,0x00,0x01,0x12,0x65,0xa7,0x90,0x04,0x49,0xe0, ++0x85,0x12,0x82,0x85,0x11,0x83,0xf0,0x90,0x04,0x48,0x80,0x58,0x90,0x04,0x4f,0xe0, ++0xab,0x13,0xaa,0x14,0xa9,0x15,0x12,0x65,0x95,0x90,0x04,0x4e,0xe0,0xab,0x13,0xaa, ++0x14,0xa9,0x15,0x90,0x00,0x01,0x12,0x65,0xa7,0x90,0x04,0x4d,0xe0,0x85,0x12,0x82, ++0x85,0x11,0x83,0xf0,0x90,0x04,0x4c,0x80,0x2b,0x90,0x04,0x53,0xe0,0xab,0x13,0xaa, ++0x14,0xa9,0x15,0x12,0x65,0x95,0x90,0x04,0x52,0xe0,0xab,0x13,0xaa,0x14,0xa9,0x15, ++0x90,0x00,0x01,0x12,0x65,0xa7,0x90,0x04,0x51,0xe0,0x85,0x12,0x82,0x85,0x11,0x83, ++0xf0,0x90,0x04,0x50,0xe0,0x85,0x12,0x82,0x85,0x11,0x83,0xa3,0xf0,0xab,0x13,0xaa, ++0x14,0xa9,0x15,0xc0,0x03,0xc0,0x02,0xc0,0x01,0x12,0x1c,0xd6,0xff,0xab,0x18,0xaa, ++0x19,0xa9,0x1a,0x12,0x1c,0xd6,0x5f,0xd0,0x01,0xd0,0x02,0xd0,0x03,0x12,0x65,0x95, ++0xab,0x13,0xe5,0x15,0x24,0x01,0xf9,0xe4,0x35,0x14,0xfa,0xc0,0x03,0xc0,0x02,0xc0, ++0x01,0x12,0x1c,0xd6,0xff,0xab,0x18,0xaa,0x19,0xa9,0x1a,0x90,0x00,0x01,0x12,0x1c, ++0xef,0x5f,0xd0,0x01,0xd0,0x02,0xd0,0x03,0x12,0x65,0x95,0x85,0x12,0x82,0x85,0x11, ++0x83,0xc0,0x83,0xc0,0x82,0xe0,0xff,0x85,0x17,0x82,0x85,0x16,0x83,0xe0,0xfe,0xef, ++0x5e,0xd0,0x82,0xd0,0x83,0xf0,0x85,0x12,0x82,0x85,0x11,0x83,0xa3,0xc0,0x83,0xc0, ++0x82,0xe0,0xff,0x85,0x17,0x82,0x85,0x16,0x83,0xa3,0xe0,0xfe,0xef,0x5e,0xd0,0x82, ++0xd0,0x83,0xf0,0xe5,0x10,0x25,0xe0,0x24,0x81,0xf5,0x82,0xe4,0x34,0x92,0xf5,0x83, ++0xe0,0xfe,0xa3,0xe0,0x4e,0x60,0x4c,0x90,0x97,0x51,0x74,0x0b,0xf0,0x90,0x97,0x51, ++0xe0,0xff,0xc3,0x94,0x00,0x50,0x03,0x02,0x58,0x23,0x74,0x01,0x7e,0x00,0xa8,0x07, ++0x08,0x80,0x05,0xc3,0x33,0xce,0x33,0xce,0xd8,0xf9,0xff,0xe5,0x10,0x25,0xe0,0x24, ++0x81,0xf5,0x82,0xe4,0x34,0x92,0xf5,0x83,0xe0,0x5e,0xfe,0xa3,0xe0,0x5f,0x4e,0x60, ++0x0a,0x90,0x97,0x51,0xe0,0x24,0x10,0xa3,0xf0,0x80,0x68,0x90,0x97,0x51,0xe0,0x14, ++0xf0,0x80,0xba,0xe5,0x10,0x25,0xe0,0x24,0xe4,0xf5,0x82,0xe4,0x34,0x95,0xf5,0x83, ++0xe0,0xfe,0xa3,0xe0,0x4e,0x60,0x47,0x90,0x97,0x51,0x74,0x0f,0xf0,0x90,0x97,0x51, ++0xe0,0xff,0xc3,0x94,0x00,0x40,0x3c,0x74,0x01,0x7e,0x00,0xa8,0x07,0x08,0x80,0x05, ++0xc3,0x33,0xce,0x33,0xce,0xd8,0xf9,0xff,0xe5,0x10,0x25,0xe0,0x24,0xe4,0xf5,0x82, ++0xe4,0x34,0x95,0xf5,0x83,0xe0,0x5e,0xfe,0xa3,0xe0,0x5f,0x4e,0x60,0x08,0x90,0x97, ++0x51,0xe0,0xa3,0xf0,0x80,0x0d,0x90,0x97,0x51,0xe0,0x14,0xf0,0x80,0xbf,0xe4,0x90, ++0x97,0x52,0xf0,0xe5,0x10,0x25,0xe0,0x24,0xe4,0xf5,0x82,0xe4,0x34,0x95,0xf5,0x83, ++0xe0,0xfe,0xa3,0xe0,0x4e,0x60,0x47,0xe4,0x90,0x97,0x51,0xf0,0x90,0x97,0x51,0xe0, ++0xff,0xc3,0x94,0x10,0x40,0x03,0x02,0x58,0xdd,0x74,0x01,0x7e,0x00,0xa8,0x07,0x08, ++0x80,0x05,0xc3,0x33,0xce,0x33,0xce,0xd8,0xf9,0xff,0xe5,0x10,0x25,0xe0,0x24,0xe4, ++0xf5,0x82,0xe4,0x34,0x95,0xf5,0x83,0xe0,0x5e,0xfe,0xa3,0xe0,0x5f,0x4e,0x60,0x06, ++0x90,0x97,0x51,0xe0,0x80,0x63,0x90,0x97,0x51,0xe0,0x04,0xf0,0x80,0xbe,0xe5,0x10, ++0x25,0xe0,0x24,0x81,0xf5,0x82,0xe4,0x34,0x92,0xf5,0x83,0xe0,0xfe,0xa3,0xe0,0x4e, ++0x60,0x46,0xe4,0x90,0x97,0x51,0xf0,0x90,0x97,0x51,0xe0,0xff,0xc3,0x94,0x0c,0x50, ++0x3c,0x74,0x01,0x7e,0x00,0xa8,0x07,0x08,0x80,0x05,0xc3,0x33,0xce,0x33,0xce,0xd8, ++0xf9,0xff,0xe5,0x10,0x25,0xe0,0x24,0x81,0xf5,0x82,0xe4,0x34,0x92,0xf5,0x83,0xe0, ++0x5e,0xfe,0xa3,0xe0,0x5f,0x4e,0x60,0x08,0x90,0x97,0x51,0xe0,0x24,0x10,0x80,0x09, ++0x90,0x97,0x51,0xe0,0x04,0xf0,0x80,0xbf,0xe4,0x90,0x97,0x53,0xf0,0x90,0x97,0x52, ++0xe0,0xff,0xe5,0x10,0x75,0xf0,0x08,0xa4,0x24,0x67,0xf5,0x82,0xe4,0x34,0x93,0xf5, ++0x83,0xef,0xf0,0x90,0x97,0x53,0xe0,0xfe,0xe5,0x10,0x75,0xf0,0x08,0xa4,0x24,0x68, ++0xf5,0x82,0xe4,0x34,0x93,0xf5,0x83,0xee,0xf0,0x74,0x84,0x25,0x10,0xf5,0x82,0xe4, ++0x34,0x04,0xf5,0x83,0xe0,0xd3,0x9f,0x40,0x1f,0x90,0x97,0x52,0xe0,0xff,0x74,0x84, ++0x25,0x10,0xf5,0x82,0xe4,0x34,0x96,0xf5,0x83,0xef,0xf0,0x74,0x84,0x25,0x10,0xf5, ++0x82,0xe4,0x34,0x04,0xf5,0x83,0xef,0xf0,0x90,0x97,0x52,0xe0,0xff,0xd3,0x94,0x13, ++0x40,0x08,0x90,0x93,0x62,0x74,0x03,0xf0,0x80,0x21,0xef,0xd3,0x94,0x0b,0x40,0x08, ++0x90,0x93,0x62,0x74,0x02,0xf0,0x80,0x13,0xef,0xd3,0x94,0x03,0x40,0x08,0x90,0x93, ++0x62,0x74,0x01,0xf0,0x80,0x05,0xe4,0x90,0x93,0x62,0xf0,0x90,0x93,0x62,0xe0,0x90, ++0x04,0xb1,0xf0,0xe5,0x10,0x25,0xe0,0x24,0xe4,0xf5,0x82,0xe4,0x34,0x95,0xf5,0x83, ++0xe0,0xff,0xa3,0xe0,0x90,0x04,0x9c,0xcf,0xf0,0xa3,0xef,0xf0,0xe5,0x10,0x25,0xe0, ++0x24,0x81,0xf5,0x82,0xe4,0x34,0x92,0xf5,0x83,0xe0,0xff,0xa3,0xe0,0x90,0x04,0x9e, ++0xcf,0xf0,0xa3,0xef,0xf0,0xe5,0x10,0x75,0xf0,0x08,0xa4,0x24,0x69,0xf5,0x82,0xe4, ++0x34,0x93,0xf5,0x83,0xe0,0xc4,0x33,0x54,0xe0,0x45,0x10,0x90,0x04,0xa0,0xf0,0x74, ++0xc1,0x25,0x10,0xf5,0x82,0xe4,0x34,0x92,0xf5,0x83,0xe0,0x90,0x04,0xa1,0xf0,0x22, ++0xc0,0xe0,0xc0,0xf0,0xc0,0x83,0xc0,0x82,0xc0,0xd0,0x75,0xd0,0x00,0xc0,0x00,0xc0, ++0x01,0xc0,0x02,0xc0,0x03,0xc0,0x04,0xc0,0x05,0xc0,0x06,0xc0,0x07,0x90,0x01,0xc4, ++0x74,0xd0,0xf0,0x74,0x59,0xa3,0xf0,0x90,0x01,0x37,0xe0,0x55,0x2b,0xf5,0x2f,0x90, ++0x01,0x34,0xe0,0x55,0x28,0xf5,0x2c,0x90,0x01,0x36,0xe0,0x55,0x2a,0xf5,0x2e,0xe5, ++0x2c,0x20,0xe0,0x03,0x02,0x5b,0x82,0x90,0x01,0x34,0x74,0x01,0xf0,0x85,0xd1,0x4d, ++0x85,0xd2,0x4e,0x85,0xd3,0x4f,0x85,0xd4,0x50,0x85,0xd5,0x51,0x85,0xd6,0x52,0x85, ++0xd7,0x53,0x85,0xd9,0x54,0xe5,0x54,0x54,0x40,0xc3,0x13,0xff,0xe5,0x53,0x54,0x20, ++0x6f,0x70,0x03,0x02,0x5b,0x2f,0xe5,0x54,0x30,0xe5,0x03,0x02,0x5b,0x2f,0xe5,0x52, ++0x54,0x1f,0xf5,0x08,0xe5,0x4d,0x54,0x3f,0xf5,0x09,0xe5,0x51,0x54,0x1f,0xff,0xe5, ++0x08,0x25,0xe0,0x24,0xe3,0xf5,0x82,0xe4,0x34,0x94,0xf5,0x83,0xe4,0x8f,0xf0,0x12, ++0x65,0xc9,0xe5,0x53,0x54,0x1f,0xff,0xe5,0x08,0x25,0xe0,0x24,0xc0,0xf5,0x82,0xe4, ++0x34,0x91,0xf5,0x83,0xe4,0x8f,0xf0,0x12,0x65,0xc9,0xe5,0x09,0xd3,0x94,0x04,0x40, ++0x03,0x75,0x09,0x04,0x75,0xf0,0x0a,0xe5,0x08,0xa4,0x24,0x00,0xf5,0x82,0xe5,0xf0, ++0x34,0x90,0xf5,0x83,0x75,0xf0,0x02,0xe5,0x09,0x12,0x66,0xb5,0xe0,0xfe,0xa3,0xe0, ++0xff,0xe5,0x53,0x54,0x1f,0x2f,0xff,0xe4,0x3e,0xfe,0x75,0xf0,0x0a,0xe5,0x08,0xa4, ++0x24,0x00,0xf5,0x82,0xe5,0xf0,0x34,0x90,0xf5,0x83,0x75,0xf0,0x02,0xe5,0x09,0x12, ++0x66,0xb5,0xee,0xf0,0xa3,0xef,0xf0,0xe5,0x54,0x20,0xe6,0x24,0xe5,0x53,0x54,0x1f, ++0xff,0xe5,0x08,0x25,0xe0,0x24,0x63,0xf5,0x82,0xe4,0x34,0x94,0xf5,0x83,0xe4,0x8f, ++0xf0,0x12,0x65,0xc9,0xe5,0x4f,0x30,0xe7,0x36,0xaf,0x08,0x12,0x75,0x4c,0x80,0x2f, ++0xe5,0x53,0x54,0x1f,0xff,0xe5,0x08,0x25,0xe0,0x24,0xa3,0xf5,0x82,0xe4,0x34,0x94, ++0xf5,0x83,0xe4,0x8f,0xf0,0x12,0x65,0xc9,0xe5,0x4f,0x30,0xe7,0x12,0xe5,0x4f,0x54, ++0x7f,0xfd,0xe5,0x53,0x54,0x1f,0xf5,0x0d,0xab,0x09,0xaf,0x08,0x12,0x76,0x52,0xe5, ++0x65,0x60,0x4f,0x90,0x97,0x8d,0xe0,0x60,0x35,0x90,0x01,0x5b,0xe4,0xf0,0x90,0x01, ++0x3c,0x74,0x04,0xf0,0x90,0x04,0x1b,0xe0,0x54,0x7f,0x64,0x7f,0x70,0x34,0x75,0x48, ++0x14,0xf5,0x49,0xfb,0xfd,0x7f,0x58,0x7e,0x01,0x12,0x38,0xec,0x90,0x01,0x5b,0x74, ++0x05,0xf0,0x90,0x06,0x92,0x74,0x01,0xf0,0x90,0x97,0x87,0xf0,0x80,0x14,0x90,0x04, ++0x1b,0xe0,0x54,0x7f,0xff,0xbf,0x7f,0x0a,0x90,0x97,0x8b,0xe0,0xff,0x7d,0x01,0x12, ++0x6e,0xda,0xe5,0x2c,0x30,0xe1,0x21,0x90,0x01,0x34,0x74,0x02,0xf0,0x85,0xd1,0x56, ++0x85,0xd2,0x57,0x85,0xd3,0x58,0x85,0xd4,0x59,0x85,0xd5,0x5a,0x85,0xd6,0x5b,0x85, ++0xd7,0x5c,0x85,0xd9,0x5d,0x12,0x7d,0xc4,0xe5,0x2c,0x30,0xe3,0x06,0x90,0x01,0x34, ++0x74,0x08,0xf0,0xe5,0x2c,0x30,0xe4,0x09,0x90,0x01,0x34,0x74,0x10,0xf0,0x43,0x55, ++0x10,0xe5,0x2c,0x30,0xe5,0x21,0x90,0x01,0xcf,0xe0,0x30,0xe5,0x1a,0xe0,0x54,0xdf, ++0xf0,0x90,0x01,0x34,0x74,0x20,0xf0,0x90,0x00,0x03,0xe0,0x54,0xfb,0xf0,0x7f,0x10, ++0x7e,0x00,0x12,0x3a,0xa8,0x80,0xfe,0xe5,0x2c,0x30,0xe6,0x06,0x90,0x01,0x34,0x74, ++0x40,0xf0,0xe5,0x2e,0x30,0xe1,0x09,0x90,0x01,0x36,0x74,0x02,0xf0,0x43,0x55,0x40, ++0xe5,0x2e,0x30,0xe0,0x09,0x90,0x01,0x36,0x74,0x01,0xf0,0x12,0x76,0xd3,0xe5,0x2e, ++0x30,0xe2,0x63,0x90,0x01,0x36,0x74,0x04,0xf0,0xe5,0x64,0x64,0x01,0x70,0x57,0xe5, ++0x65,0x60,0x53,0xe5,0x65,0x64,0x02,0x70,0x27,0x90,0x06,0xab,0xe0,0x90,0x97,0x7f, ++0xf0,0x90,0x06,0xaa,0xe0,0x90,0x97,0x8a,0xf0,0x90,0x97,0x7f,0xe0,0x70,0x07,0x90, ++0x97,0x8a,0xe0,0xff,0x80,0x05,0x90,0x97,0x7f,0xe0,0xff,0x90,0x97,0x7f,0xef,0xf0, ++0x90,0x97,0x81,0xe0,0x60,0x03,0xe0,0x14,0xf0,0x90,0x97,0x80,0xe4,0xf0,0x90,0x01, ++0x57,0xf0,0x90,0x01,0x3c,0x74,0x02,0xf0,0x90,0x97,0x8f,0xe0,0x54,0xfd,0xf0,0xe0, ++0x54,0xef,0xf0,0x12,0x77,0x49,0xe5,0x2e,0x30,0xe3,0x31,0x90,0x01,0x36,0x74,0x08, ++0xf0,0xe5,0x64,0x64,0x01,0x70,0x25,0xe5,0x65,0x60,0x21,0x90,0x01,0x57,0xe4,0xf0, ++0x90,0x01,0x3c,0x74,0x02,0xf0,0x75,0x48,0x03,0x75,0x49,0x00,0xe4,0xfb,0xfd,0x7f, ++0x54,0x7e,0x01,0x12,0x38,0xec,0x90,0x01,0x57,0x74,0x05,0xf0,0xe5,0x2e,0x30,0xe4, ++0x3a,0x90,0x01,0x36,0x74,0x10,0xf0,0xe5,0x64,0x64,0x01,0x70,0x2e,0xe5,0x65,0x60, ++0x2a,0x90,0x01,0x57,0xe4,0xf0,0x90,0x01,0x3c,0x74,0x02,0xf0,0x90,0x97,0x8e,0xe4, ++0xf0,0x90,0x97,0x8f,0xe0,0x54,0xfd,0xf0,0xe0,0x54,0x03,0x70,0x0e,0x90,0x97,0x89, ++0xf0,0x90,0x97,0x8b,0xe0,0xff,0x7d,0x01,0x12,0x6e,0xda,0xe5,0x2e,0x30,0xe5,0x12, ++0x90,0x01,0x36,0x74,0x20,0xf0,0xe5,0x64,0xb4,0x01,0x07,0xe5,0x65,0x60,0x03,0x12, ++0x7e,0x7e,0xe5,0x2e,0x30,0xe6,0x2a,0x90,0x01,0x36,0x74,0x40,0xf0,0xe5,0x64,0x64, ++0x01,0x70,0x1e,0xe5,0x65,0x60,0x1a,0x90,0x97,0x8f,0xe0,0x54,0xfe,0xf0,0xe0,0x54, ++0x03,0x70,0x0e,0x90,0x97,0x89,0xf0,0x90,0x97,0x8b,0xe0,0xff,0x7d,0x01,0x12,0x6e, ++0xda,0xe5,0x2f,0x30,0xe1,0x09,0x90,0x01,0x37,0x74,0x02,0xf0,0x12,0x7c,0xe8,0x74, ++0xd0,0x04,0x90,0x01,0xc4,0xf0,0x74,0x59,0xa3,0xf0,0xd0,0x07,0xd0,0x06,0xd0,0x05, ++0xd0,0x04,0xd0,0x03,0xd0,0x02,0xd0,0x01,0xd0,0x00,0xd0,0xd0,0xd0,0x82,0xd0,0x83, ++0xd0,0xf0,0xd0,0xe0,0x32,0x74,0x5d,0x90,0x01,0xc4,0xf0,0xa3,0x74,0x65,0xf0,0x90, ++0x04,0x44,0x74,0x11,0xf0,0xa3,0x74,0xf0,0xf0,0xa3,0x74,0x0f,0xf0,0xa3,0xe4,0xf0, ++0x90,0x97,0x3a,0xf0,0x90,0x97,0x3a,0xe0,0xff,0xc3,0x94,0x10,0x50,0x14,0x74,0xa4, ++0x2f,0xf5,0x82,0xe4,0x34,0x04,0xf5,0x83,0xe4,0xf0,0x90,0x97,0x3a,0xe0,0x04,0xf0, ++0x80,0xe2,0xe4,0x90,0x97,0x3a,0xf0,0x90,0x97,0x3a,0xe0,0xfb,0xc3,0x94,0x20,0x40, ++0x03,0x02,0x5f,0x6c,0xe0,0xff,0x75,0xf0,0x0a,0xa4,0x24,0x00,0xf5,0x82,0xe5,0xf0, ++0x34,0x90,0xf5,0x83,0xe4,0xf0,0xa3,0xf0,0x75,0xf0,0x0a,0xef,0xa4,0x24,0x02,0xf5, ++0x82,0xe5,0xf0,0x34,0x90,0xf5,0x83,0xe4,0xf0,0xa3,0xf0,0x75,0xf0,0x0a,0xef,0xa4, ++0x24,0x04,0xf5,0x82,0xe5,0xf0,0x34,0x90,0xf5,0x83,0xe4,0xf0,0xa3,0xf0,0x75,0xf0, ++0x0a,0xef,0xa4,0x24,0x06,0xf5,0x82,0xe5,0xf0,0x34,0x90,0xf5,0x83,0xe4,0xf0,0xa3, ++0xf0,0x75,0xf0,0x0a,0xef,0xa4,0x24,0x08,0xf5,0x82,0xe5,0xf0,0x34,0x90,0xf5,0x83, ++0xe4,0xf0,0xa3,0xf0,0x74,0x84,0x2f,0xf5,0x82,0xe4,0x34,0x96,0xf5,0x83,0x74,0x13, ++0xf0,0x74,0x44,0x2f,0xf5,0x82,0xe4,0x34,0x95,0xf5,0x83,0xe4,0xf0,0xef,0x25,0xe0, ++0x24,0xc0,0xf5,0x82,0xe4,0x34,0x91,0xf5,0x83,0xe4,0xf0,0xa3,0xf0,0xef,0x25,0xe0, ++0x24,0x63,0xf5,0x82,0xe4,0x34,0x94,0xf5,0x83,0xe4,0xf0,0xa3,0xf0,0xef,0x25,0xe0, ++0x24,0xe3,0xf5,0x82,0xe4,0x34,0x94,0xf5,0x83,0xe4,0xf0,0xa3,0xf0,0xef,0x25,0xe0, ++0x24,0xa3,0xf5,0x82,0xe4,0x34,0x94,0xf5,0x83,0xe4,0xf0,0xa3,0xf0,0xef,0x25,0xe0, ++0x24,0x64,0xf5,0x82,0xe4,0x34,0x95,0xf5,0x83,0xe4,0xf0,0xa3,0xf0,0xef,0x25,0xe0, ++0x24,0xa4,0xf5,0x82,0xe4,0x34,0x95,0xf5,0x83,0xe4,0xf0,0xa3,0xf0,0x74,0x44,0x2f, ++0xf5,0x82,0xe4,0x34,0x96,0xf5,0x83,0xe4,0xf0,0x74,0x24,0x2f,0xf5,0x82,0xe4,0x34, ++0x96,0xf5,0x83,0xe4,0xf0,0x74,0x64,0x2f,0xf5,0x82,0xe4,0x34,0x96,0xf5,0x83,0xe4, ++0xf0,0x90,0x41,0xc4,0x93,0xfe,0x74,0x01,0x93,0xff,0x90,0x41,0x8c,0x74,0x01,0x93, ++0x2f,0xff,0xe4,0x93,0x3e,0xc3,0x13,0xfe,0xef,0x13,0xff,0xe4,0xfc,0xfd,0xeb,0x25, ++0xe0,0x25,0xe0,0x24,0xe1,0xf5,0x82,0xe4,0x34,0x92,0xf5,0x83,0x12,0x1d,0xa9,0xeb, ++0x75,0xf0,0x08,0xa4,0x24,0x6a,0xf5,0x82,0xe4,0x34,0x93,0xf5,0x83,0x74,0x01,0xf0, ++0xeb,0x75,0xf0,0x08,0xa4,0x24,0x69,0xf5,0x82,0xe4,0x34,0x93,0xf5,0x83,0x74,0x01, ++0xf0,0x74,0xc1,0x2b,0xf5,0x82,0xe4,0x34,0x92,0xf5,0x83,0x74,0x0c,0xf0,0xeb,0x75, ++0xf0,0x08,0xa4,0x24,0x65,0xf5,0x82,0xe4,0x34,0x93,0xf5,0x83,0x74,0xff,0xf0,0xa3, ++0xf0,0xeb,0x75,0xf0,0x08,0xa4,0x24,0x63,0xf5,0x82,0xe4,0x34,0x93,0xf5,0x83,0xe4, ++0xf0,0xa3,0x74,0x0f,0xf0,0xeb,0x75,0xf0,0x08,0xa4,0x24,0x67,0xf5,0x82,0xe4,0x34, ++0x93,0xf5,0x83,0x74,0x13,0xf0,0xeb,0x75,0xf0,0x08,0xa4,0x24,0x68,0xf5,0x82,0xe4, ++0x34,0x93,0xf5,0x83,0xe4,0xf0,0x74,0x84,0x2b,0xf5,0x82,0xe4,0x34,0x04,0xf5,0x83, ++0x74,0x13,0xf0,0x90,0x97,0x3a,0xe0,0x04,0xf0,0x02,0x5d,0xa7,0x22,0x8f,0x17,0x74, ++0x5f,0x90,0x01,0xc4,0xf0,0xa3,0x74,0x6d,0xf0,0x74,0x84,0x25,0x17,0xf5,0x82,0xe4, ++0x34,0x04,0xf5,0x83,0xe0,0x54,0x7f,0x90,0x97,0x54,0xf0,0xe0,0x54,0x1f,0xff,0x90, ++0x97,0x57,0xf0,0xe5,0x17,0x75,0xf0,0x08,0xa4,0x24,0x68,0xf5,0x82,0xe4,0x34,0x93, ++0xf5,0x83,0xe0,0x90,0x97,0x59,0xf0,0xe5,0x17,0x75,0xf0,0x08,0xa4,0x24,0x67,0xf5, ++0x82,0xe4,0x34,0x93,0xf5,0x83,0xe0,0xfe,0x90,0x97,0x5a,0xf0,0xe5,0x17,0x25,0xe0, ++0x24,0xe4,0xf5,0x82,0xe4,0x34,0x95,0xf5,0x83,0xe0,0xfb,0xa3,0xe0,0x90,0x97,0x5b, ++0xcb,0xf0,0xa3,0xeb,0xf0,0xe5,0x17,0x25,0xe0,0x24,0x81,0xf5,0x82,0xe4,0x34,0x92, ++0xf5,0x83,0xe0,0xfb,0xa3,0xe0,0x90,0x97,0x5d,0xcb,0xf0,0xa3,0xeb,0xf0,0xef,0xd3, ++0x9e,0x40,0x0c,0x90,0x97,0x5a,0xe0,0x90,0x97,0x57,0xf0,0x90,0x97,0x54,0xf0,0xed, ++0x70,0x03,0x02,0x60,0xd9,0x90,0x97,0x58,0xed,0xf0,0x90,0x97,0x54,0xe0,0x30,0xe6, ++0x0e,0x90,0x97,0x57,0xe0,0x90,0x97,0x54,0xf0,0x90,0x97,0x58,0xe0,0x14,0xf0,0x90, ++0x97,0x58,0xe0,0x70,0x03,0x02,0x60,0xd9,0x90,0x97,0x57,0xe0,0xff,0xd3,0x94,0x00, ++0x50,0x03,0x02,0x60,0xd9,0xe4,0x90,0x97,0x56,0xf0,0xef,0x14,0x90,0x97,0x55,0xf0, ++0x90,0x97,0x59,0xe0,0xfd,0x90,0x97,0x55,0xe0,0xff,0xd3,0x9d,0x40,0x6f,0xef,0x94, ++0x10,0x40,0x21,0xef,0x24,0xf0,0xff,0x74,0x01,0x7e,0x00,0xa8,0x07,0x08,0x80,0x05, ++0xc3,0x33,0xce,0x33,0xce,0xd8,0xf9,0xff,0x90,0x97,0x5d,0xe0,0x5e,0xfe,0xa3,0xe0, ++0x5f,0x4e,0x70,0x27,0x90,0x97,0x55,0xe0,0xff,0xc3,0x94,0x10,0x50,0x37,0x74,0x01, ++0x7e,0x00,0xa8,0x07,0x08,0x80,0x05,0xc3,0x33,0xce,0x33,0xce,0xd8,0xf9,0xff,0x90, ++0x97,0x5b,0xe0,0x5e,0xfe,0xa3,0xe0,0x5f,0x4e,0x60,0x1a,0x90,0x97,0x55,0xe0,0x90, ++0x97,0x54,0xf0,0x90,0x97,0x56,0xe0,0x04,0xf0,0x90,0x97,0x58,0xe0,0xff,0x90,0x97, ++0x56,0xe0,0x6f,0x60,0x08,0x90,0x97,0x55,0xe0,0x14,0xf0,0x80,0x83,0x90,0x97,0x58, ++0xe0,0xff,0x90,0x97,0x56,0xe0,0xc3,0x9f,0x50,0x0f,0x90,0x97,0x55,0xe0,0xb5,0x05, ++0x08,0x90,0x97,0x59,0xe0,0x90,0x97,0x54,0xf0,0x90,0x97,0x54,0xe0,0xff,0x25,0xe0, ++0x24,0x9e,0xf5,0x82,0xe4,0x34,0x41,0xf5,0x83,0xe4,0x93,0xfc,0x74,0x01,0x93,0xfd, ++0xef,0x25,0xe0,0x24,0x66,0xf5,0x82,0xe4,0x34,0x41,0xf5,0x83,0x74,0x01,0x93,0x2d, ++0xff,0xe4,0x93,0x3c,0xc3,0x13,0xfe,0xef,0x13,0xff,0xe4,0xfc,0xfd,0xe5,0x17,0x25, ++0xe0,0x25,0xe0,0x24,0xe1,0xf5,0x82,0xe4,0x34,0x92,0xf5,0x83,0x12,0x1d,0xa9,0x90, ++0x97,0x54,0xe0,0xff,0x74,0x84,0x25,0x17,0xf5,0x82,0xe4,0x34,0x04,0xf5,0x83,0xef, ++0xf0,0x22,0x90,0x01,0xc4,0x74,0x32,0xf0,0x74,0x61,0xa3,0xf0,0x90,0x01,0xcc,0xe0, ++0x54,0x0f,0x90,0x97,0x3a,0xf0,0x90,0x97,0x3a,0xe0,0xfd,0x70,0x03,0x02,0x62,0xd2, ++0x90,0x97,0xb1,0xe0,0xff,0x74,0x01,0x7e,0x00,0xa8,0x07,0x08,0x80,0x05,0xc3,0x33, ++0xce,0x33,0xce,0xd8,0xf9,0xff,0xef,0x5d,0x70,0x03,0x02,0x62,0xb3,0x90,0x97,0xb1, ++0xe0,0x75,0xf0,0x04,0xa4,0x24,0xd0,0xf5,0x82,0xe5,0xf0,0x34,0x01,0xf5,0x83,0xe0, ++0x90,0x97,0x3b,0xf0,0xa2,0xaf,0xe4,0x33,0xa3,0xf0,0xc2,0xaf,0x75,0x24,0x01,0x75, ++0x25,0x97,0x75,0x26,0x3b,0x75,0x27,0x01,0x7b,0x01,0x7a,0x97,0x79,0x3d,0x12,0x79, ++0x27,0x90,0x97,0x3c,0xe0,0x24,0xff,0x92,0xaf,0xa3,0xe0,0xff,0xc4,0x13,0x13,0x13, ++0x54,0x01,0x90,0x97,0xb1,0x30,0xe0,0x70,0xe0,0x75,0xf0,0x02,0xa4,0x24,0x88,0xf5, ++0x82,0xe4,0x35,0xf0,0xf5,0x83,0xe0,0x90,0x97,0x3e,0xf0,0x90,0x97,0xb1,0xe0,0x75, ++0xf0,0x02,0xa4,0x24,0x89,0xf5,0x82,0xe4,0x35,0xf0,0xf5,0x83,0xe0,0x90,0x97,0x3f, ++0xf0,0x90,0x97,0xb1,0xe0,0x75,0xf0,0x04,0xa4,0x24,0xd1,0xf5,0x82,0xe5,0xf0,0x34, ++0x01,0xf5,0x83,0xe0,0x90,0x97,0x40,0xf0,0x90,0x97,0xb1,0xe0,0x75,0xf0,0x04,0xa4, ++0x24,0xd2,0xf5,0x82,0xe5,0xf0,0x34,0x01,0xf5,0x83,0xe0,0x90,0x97,0x41,0xf0,0x90, ++0x97,0xb1,0xe0,0x75,0xf0,0x04,0xa4,0x24,0xd3,0xf5,0x82,0xe5,0xf0,0x34,0x01,0xf5, ++0x83,0xe0,0x90,0x97,0x42,0xf0,0x80,0x42,0xe0,0x75,0xf0,0x04,0xa4,0x24,0xd1,0xf5, ++0x82,0xe5,0xf0,0x34,0x01,0xf5,0x83,0xe0,0x90,0x97,0x3e,0xf0,0x90,0x97,0xb1,0xe0, ++0x75,0xf0,0x04,0xa4,0x24,0xd2,0xf5,0x82,0xe5,0xf0,0x34,0x01,0xf5,0x83,0xe0,0x90, ++0x97,0x3f,0xf0,0x90,0x97,0xb1,0xe0,0x75,0xf0,0x04,0xa4,0x24,0xd3,0xf5,0x82,0xe5, ++0xf0,0x34,0x01,0xf5,0x83,0xe0,0x90,0x97,0x40,0xf0,0xef,0x54,0x7f,0xff,0x7b,0x01, ++0x7a,0x97,0x79,0x3e,0x12,0x6e,0x02,0x90,0x97,0x3a,0xe0,0xff,0x90,0x97,0xb1,0xe0, ++0xfe,0x74,0x01,0xa8,0x06,0x08,0x80,0x02,0xc3,0x33,0xd8,0xfc,0xf4,0x5f,0x90,0x97, ++0x3a,0xf0,0x90,0x97,0xb1,0xe0,0xff,0x74,0x01,0xa8,0x07,0x08,0x80,0x02,0xc3,0x33, ++0xd8,0xfc,0x90,0x01,0xcc,0xf0,0x90,0x97,0xb1,0xe0,0x04,0xf0,0xe0,0x54,0x03,0xf0, ++0x02,0x61,0x46,0xc2,0xaf,0x74,0x32,0x04,0x90,0x01,0xc4,0xf0,0x74,0x61,0xa3,0xf0, ++0x90,0x97,0x3a,0xe0,0x90,0x01,0xc6,0xf0,0x90,0x97,0xb1,0xe0,0x90,0x01,0xc7,0xf0, ++0x80,0xfe,0x22,0xe4,0x90,0x97,0x37,0xf0,0xa3,0xf0,0x12,0x7a,0x6c,0x90,0x00,0x02, ++0xe0,0x54,0xe0,0x90,0x97,0x96,0x60,0x05,0x74,0x01,0xf0,0x80,0x03,0x74,0x02,0xf0, ++0x90,0x00,0xf3,0xe0,0x30,0xe3,0x08,0x90,0x97,0x97,0x74,0x01,0xf0,0x80,0x05,0xe4, ++0x90,0x97,0x97,0xf0,0x90,0x97,0x97,0xe0,0xb4,0x01,0x13,0x90,0x00,0xf2,0xe0,0x30, ++0xe7,0x0c,0x90,0x97,0x90,0x74,0xfd,0xf0,0xa3,0x74,0x33,0xf0,0x80,0x0a,0x90,0x97, ++0x90,0x74,0xfd,0xf0,0xa3,0x74,0x2f,0xf0,0xe4,0xf5,0x55,0x12,0x5d,0x65,0x12,0x7f, ++0x60,0x12,0x79,0xce,0x12,0x36,0xd1,0x12,0x44,0xff,0x75,0x28,0x33,0xe4,0xf5,0x29, ++0x75,0x2a,0x02,0xf5,0x2b,0x90,0x01,0x30,0xe5,0x28,0xf0,0xa3,0xe5,0x29,0xf0,0xa3, ++0xe5,0x2a,0xf0,0xa3,0xe5,0x2b,0xf0,0x90,0x00,0xf3,0xe0,0x30,0xe2,0x0d,0x90,0x05, ++0x41,0x74,0x10,0xf0,0x90,0x05,0x5a,0xf0,0xa3,0xe4,0xf0,0x90,0x01,0x64,0x74,0xa0, ++0xf0,0x75,0x48,0xff,0xe4,0xf5,0x49,0xfb,0x7d,0x01,0x7f,0x50,0x7e,0x01,0x12,0x38, ++0xec,0x75,0x30,0x1f,0x75,0x31,0x01,0xe4,0xf5,0x32,0x90,0x01,0x38,0xe5,0x30,0xf0, ++0xa3,0xe5,0x31,0xf0,0xa3,0xe5,0x32,0xf0,0x12,0x78,0xd0,0x90,0x97,0x39,0xe5,0xd9, ++0xf0,0x90,0x01,0x3c,0x74,0xff,0xf0,0xa3,0xf0,0xa3,0xf0,0x90,0x01,0x34,0xf0,0xa3, ++0xf0,0xa3,0xf0,0xa3,0xf0,0xc2,0xaf,0x90,0x00,0x80,0xe0,0x44,0x40,0xf0,0x7f,0x10, ++0x7e,0x00,0x12,0x3a,0xa8,0x75,0xe8,0x03,0x43,0xa8,0x85,0xd2,0xaf,0x90,0x01,0xc0, ++0xe4,0xf0,0xa3,0xf0,0xa3,0xf0,0xa3,0xf0,0x90,0x01,0xc6,0xf0,0xa3,0xf0,0x90,0x97, ++0x37,0xe0,0x64,0x01,0xf0,0x24,0xd3,0x90,0x01,0xc4,0xf0,0x74,0x62,0xa3,0xf0,0xe5, ++0x55,0x30,0xe6,0x17,0xc2,0xaf,0x53,0x55,0xbf,0xd2,0xaf,0x12,0x45,0x09,0x90,0x97, ++0x6d,0xe0,0xff,0x60,0x03,0xb4,0x01,0x03,0x12,0x6a,0x1f,0xe5,0x55,0x30,0xe7,0x07, ++0xc2,0xaf,0x53,0x55,0x7f,0xd2,0xaf,0xe5,0x55,0x30,0xe4,0x0a,0xc2,0xaf,0x53,0x55, ++0xef,0xd2,0xaf,0x12,0x61,0x32,0x90,0x97,0x6d,0xe0,0x70,0x03,0x12,0x6d,0x29,0x12, ++0x7d,0x45,0x80,0xaa,0x90,0x00,0x02,0x12,0x1c,0xef,0x90,0x97,0x6b,0xf0,0x90,0x00, ++0x01,0x12,0x1c,0xef,0x25,0xe0,0x25,0xe0,0x90,0x97,0x6a,0xf0,0x12,0x1c,0xd6,0x25, ++0xe0,0x25,0xe0,0x90,0x97,0x6e,0xf0,0x90,0x97,0x6b,0xe0,0x90,0x04,0x98,0xf0,0x90, ++0x97,0x6a,0xe0,0x13,0x13,0x54,0x3f,0x90,0x04,0x99,0xf0,0x90,0x97,0x6e,0xe0,0x13, ++0x13,0x54,0x3f,0x90,0x04,0x9a,0xf0,0x90,0x05,0x60,0xe0,0x90,0x97,0x79,0xf0,0x90, ++0x05,0x61,0xe0,0x90,0x97,0x7a,0xf0,0x90,0x05,0x62,0xe0,0x90,0x97,0x7b,0xf0,0x90, ++0x05,0x63,0xe0,0x90,0x97,0x7c,0xf0,0xa2,0xaf,0xe4,0x33,0x90,0x97,0x49,0xf0,0xc2, ++0xaf,0x90,0x97,0x6a,0xe0,0xff,0x12,0x79,0x7c,0x90,0x97,0x49,0xe0,0x24,0xff,0x92, ++0xaf,0x90,0x97,0x6b,0xe0,0x70,0x03,0x02,0x65,0x61,0x90,0x97,0x6a,0xe0,0x70,0x03, ++0x02,0x65,0x61,0x90,0x97,0x6e,0xe0,0x70,0x03,0x02,0x65,0x61,0xa2,0xaf,0xe4,0x33, ++0x90,0x97,0x49,0xf0,0xc2,0xaf,0x90,0x97,0x7d,0x74,0x01,0xf0,0x90,0x97,0x49,0xe0, ++0x24,0xff,0x92,0xaf,0x90,0x00,0x45,0xe0,0x54,0xfe,0xf0,0xa3,0xe0,0x44,0x01,0xf0, ++0x90,0x97,0x63,0xe0,0x60,0x1d,0x90,0x97,0x6f,0xe0,0xfc,0xa3,0xe0,0xfd,0xa3,0xe0, ++0xfe,0xa3,0xe0,0xff,0x90,0x81,0x56,0x12,0x1d,0xa9,0x7f,0x80,0x7e,0x08,0x12,0x33, ++0xd8,0x80,0x06,0x90,0x05,0x22,0x74,0x7f,0xf0,0x90,0x00,0x45,0xe0,0x54,0xef,0xf0, ++0x90,0x05,0x87,0xe0,0x64,0x80,0xf0,0x90,0x97,0x79,0xe0,0x90,0x05,0x84,0xf0,0x90, ++0x97,0x7a,0xe0,0x90,0x05,0x85,0xf0,0x90,0x97,0x7b,0xe0,0x90,0x05,0x86,0xf0,0x90, ++0x97,0x7c,0xe0,0x90,0x05,0x87,0xf0,0xa2,0xaf,0xe4,0x33,0x90,0x97,0x49,0xf0,0xc2, ++0xaf,0x90,0x01,0x3c,0xe0,0x44,0x20,0xf0,0x7d,0x20,0xe4,0xff,0x12,0x3a,0x49,0x80, ++0x2b,0x90,0x97,0x6b,0xe0,0x70,0x2d,0x90,0x97,0x7d,0xf0,0x90,0x00,0x45,0xe0,0x54, ++0xfe,0xf0,0xa3,0xe0,0x54,0xfe,0xf0,0x90,0x05,0x22,0xe4,0xf0,0xa2,0xaf,0x33,0x90, ++0x97,0x49,0xf0,0xc2,0xaf,0x7d,0x20,0xe4,0xff,0x12,0x39,0xdb,0x90,0x97,0x49,0xe0, ++0x24,0xff,0x92,0xaf,0x22,0xbb,0x01,0x06,0x89,0x82,0x8a,0x83,0xf0,0x22,0x50,0x02, ++0xf7,0x22,0xbb,0xfe,0x01,0xf3,0x22,0xf8,0xbb,0x01,0x0d,0xe5,0x82,0x29,0xf5,0x82, ++0xe5,0x83,0x3a,0xf5,0x83,0xe8,0xf0,0x22,0x50,0x06,0xe9,0x25,0x82,0xc8,0xf6,0x22, ++0xbb,0xfe,0x05,0xe9,0x25,0x82,0xc8,0xf2,0x22,0xc5,0xf0,0xf8,0xa3,0xe0,0x28,0xf0, ++0xc5,0xf0,0xf8,0xe5,0x82,0x15,0x82,0x70,0x02,0x15,0x83,0xe0,0x38,0xf0,0x22,0xa3, ++0xf8,0xe0,0xc5,0xf0,0x25,0xf0,0xf0,0xe5,0x82,0x15,0x82,0x70,0x02,0x15,0x83,0xe0, ++0xc8,0x38,0xf0,0xe8,0x22,0xbb,0x01,0x0a,0x89,0x82,0x8a,0x83,0xe0,0xf5,0xf0,0xa3, ++0xe0,0x22,0x50,0x06,0x87,0xf0,0x09,0xe7,0x19,0x22,0xbb,0xfe,0x07,0xe3,0xf5,0xf0, ++0x09,0xe3,0x19,0x22,0x89,0x82,0x8a,0x83,0xe4,0x93,0xf5,0xf0,0x74,0x01,0x93,0x22, ++0xbb,0x01,0x10,0xe5,0x82,0x29,0xf5,0x82,0xe5,0x83,0x3a,0xf5,0x83,0xe0,0xf5,0xf0, ++0xa3,0xe0,0x22,0x50,0x09,0xe9,0x25,0x82,0xf8,0x86,0xf0,0x08,0xe6,0x22,0xbb,0xfe, ++0x0a,0xe9,0x25,0x82,0xf8,0xe2,0xf5,0xf0,0x08,0xe2,0x22,0xe5,0x83,0x2a,0xf5,0x83, ++0xe9,0x93,0xf5,0xf0,0xa3,0xe9,0x93,0x22,0xbb,0x01,0x0a,0x89,0x82,0x8a,0x83,0xf0, ++0xe5,0xf0,0xa3,0xf0,0x22,0x50,0x06,0xf7,0x09,0xa7,0xf0,0x19,0x22,0xbb,0xfe,0x06, ++0xf3,0xe5,0xf0,0x09,0xf3,0x19,0x22,0xf8,0xbb,0x01,0x11,0xe5,0x82,0x29,0xf5,0x82, ++0xe5,0x83,0x3a,0xf5,0x83,0xe8,0xf0,0xe5,0xf0,0xa3,0xf0,0x22,0x50,0x09,0xe9,0x25, ++0x82,0xc8,0xf6,0x08,0xa6,0xf0,0x22,0xbb,0xfe,0x09,0xe9,0x25,0x82,0xc8,0xf2,0xe5, ++0xf0,0x08,0xf2,0x22,0xeb,0x9f,0xf5,0xf0,0xea,0x9e,0x42,0xf0,0xe9,0x9d,0x42,0xf0, ++0xe8,0x9c,0x45,0xf0,0x22,0xa4,0x25,0x82,0xf5,0x82,0xe5,0xf0,0x35,0x83,0xf5,0x83, ++0x22,0xd0,0x83,0xd0,0x82,0xf8,0xe4,0x93,0x70,0x12,0x74,0x01,0x93,0x70,0x0d,0xa3, ++0xa3,0x93,0xf8,0x74,0x01,0x93,0xf5,0x82,0x88,0x83,0xe4,0x73,0x74,0x02,0x93,0x68, ++0x60,0xef,0xa3,0xa3,0xa3,0x80,0xdf,0x90,0x97,0x46,0xeb,0xf0,0xa3,0xea,0xf0,0xa3, ++0xe9,0xf0,0x90,0x97,0x46,0xe0,0xfb,0xa3,0xe0,0xfa,0xa3,0xe0,0xf9,0x90,0x00,0x04, ++0x12,0x1c,0xef,0xff,0x54,0x1f,0x90,0x97,0x49,0xf0,0x90,0x00,0x03,0x12,0x1c,0xef, ++0x54,0xf0,0xc4,0x54,0x0f,0x90,0x97,0x4a,0xf0,0xef,0x54,0x20,0xc4,0x13,0x54,0x07, ++0xa3,0xf0,0x90,0x97,0x49,0xe0,0xff,0x75,0xf0,0x08,0xa4,0x24,0x65,0xf5,0x82,0xe4, ++0x34,0x93,0xad,0x82,0x90,0x97,0x4c,0xf0,0xa3,0xed,0xf0,0xef,0x75,0xf0,0x08,0xa4, ++0x24,0x63,0xf9,0x74,0x93,0x35,0xf0,0xfa,0xa3,0x74,0x01,0xf0,0xa3,0xea,0xf0,0xa3, ++0xe9,0xf0,0x90,0x97,0x46,0xa3,0xe0,0xfa,0xa3,0xe0,0xf9,0x90,0x00,0x03,0x12,0x1c, ++0xef,0x54,0x0f,0xff,0x90,0x97,0x4e,0xe0,0xfb,0xa3,0xe0,0xfa,0xa3,0xe0,0xf9,0xef, ++0x12,0x65,0x95,0x90,0x97,0x46,0xe0,0xfb,0xa3,0xe0,0xfa,0xa3,0xe0,0xf9,0x90,0x00, ++0x02,0x12,0x1c,0xef,0xff,0x90,0x97,0x4e,0xe0,0xfb,0xa3,0xe0,0xfa,0xa3,0xe0,0xf9, ++0x90,0x00,0x01,0xef,0x12,0x65,0xa7,0x90,0x97,0x46,0xe0,0xfb,0xa3,0xe0,0xfa,0xa3, ++0xe0,0xf9,0x90,0x00,0x01,0x12,0x1c,0xef,0xff,0x90,0x97,0x4c,0xe0,0xfc,0xa3,0xe0, ++0xfd,0xf5,0x82,0x8c,0x83,0xef,0xf0,0x12,0x1c,0xd6,0x8d,0x82,0x8c,0x83,0xa3,0xf0, ++0x90,0x97,0x4a,0xe0,0xfe,0x90,0x97,0x49,0xe0,0xff,0x24,0xc1,0xf5,0x82,0xe4,0x34, ++0x92,0xf5,0x83,0xee,0xf0,0x90,0x97,0x4b,0xe0,0xfe,0xef,0x75,0xf0,0x08,0xa4,0x24, ++0x69,0xf5,0x82,0xe4,0x34,0x93,0xf5,0x83,0xee,0xf0,0xef,0x75,0xf0,0x08,0xa4,0x24, ++0x6a,0xf5,0x82,0xe4,0x34,0x93,0xf5,0x83,0x74,0x01,0xf0,0x02,0x54,0xe6,0xc0,0xe0, ++0xc0,0xf0,0xc0,0x83,0xc0,0x82,0xc0,0xd0,0x75,0xd0,0x00,0xc0,0x00,0xc0,0x01,0xc0, ++0x02,0xc0,0x03,0xc0,0x04,0xc0,0x05,0xc0,0x06,0xc0,0x07,0x90,0x01,0xc4,0x74,0xfe, ++0xf0,0x74,0x67,0xa3,0xf0,0x53,0x91,0xdf,0x90,0x01,0x3c,0xe0,0x55,0x30,0xf5,0x34, ++0xa3,0xe0,0x55,0x31,0xf5,0x35,0xa3,0xe0,0x55,0x32,0xf5,0x36,0xe5,0x34,0x30,0xe0, ++0x0f,0x90,0x01,0x3c,0x74,0x01,0xf0,0x90,0x01,0x53,0x74,0x07,0xf0,0x43,0x55,0x80, ++0xe5,0x34,0x30,0xe1,0x09,0x90,0x01,0x3c,0x74,0x02,0xf0,0x12,0x7b,0x00,0xe5,0x34, ++0x30,0xe2,0x3a,0x90,0x01,0x3c,0x74,0x04,0xf0,0x90,0x06,0x92,0xe0,0x30,0xe0,0x1e, ++0x75,0x48,0x14,0x75,0x49,0x00,0xe4,0xfb,0xfd,0x7f,0x58,0x7e,0x01,0x12,0x38,0xec, ++0x90,0x01,0x5b,0x74,0x05,0xf0,0x90,0x06,0x92,0x74,0x01,0xf0,0x80,0x0f,0x90,0x97, ++0x87,0xe4,0xf0,0x90,0x97,0x8b,0xe0,0xff,0x7d,0x01,0x12,0x6e,0xda,0xe5,0x34,0x30, ++0xe3,0x06,0x90,0x01,0x3c,0x74,0x08,0xf0,0xe5,0x34,0x30,0xe4,0x09,0x90,0x01,0x3c, ++0x74,0x10,0xf0,0x12,0x7e,0xdf,0xe5,0x34,0x30,0xe5,0x09,0x90,0x01,0x3c,0x74,0x20, ++0xf0,0x12,0x6f,0xa2,0xe5,0x35,0x30,0xe0,0x15,0x90,0x01,0x3d,0x74,0x01,0xf0,0x90, ++0x00,0x83,0xe0,0x90,0x97,0x8b,0xf0,0xe0,0xff,0x7d,0x01,0x12,0x6e,0xda,0xe5,0x36, ++0x30,0xe3,0x06,0x90,0x01,0x3e,0x74,0x08,0xf0,0x74,0xfe,0x04,0x90,0x01,0xc4,0xf0, ++0x74,0x67,0xa3,0xf0,0xd0,0x07,0xd0,0x06,0xd0,0x05,0xd0,0x04,0xd0,0x03,0xd0,0x02, ++0xd0,0x01,0xd0,0x00,0xd0,0xd0,0xd0,0x82,0xd0,0x83,0xd0,0xf0,0xd0,0xe0,0x32,0x8b, ++0x10,0x8a,0x11,0x89,0x12,0x90,0x00,0x02,0x12,0x1c,0xef,0x90,0x97,0x6c,0xf0,0xe0, ++0x90,0x04,0x94,0xf0,0x90,0x00,0x01,0x12,0x1c,0xef,0x90,0x04,0x95,0xf0,0x90,0x97, ++0x6c,0xe0,0x30,0xe0,0x74,0x90,0x97,0x63,0x74,0x01,0xf0,0x7f,0x80,0x7e,0x08,0x12, ++0x2b,0x13,0x90,0x97,0x65,0x12,0x1d,0xa9,0xab,0x10,0xaa,0x11,0xa9,0x12,0x90,0x00, ++0x01,0x12,0x1c,0xef,0xff,0xe4,0xfc,0xfd,0xfe,0x78,0x1a,0x12,0x1d,0x96,0xa8,0x04, ++0xa9,0x05,0xaa,0x06,0xab,0x07,0x90,0x97,0x65,0xe0,0xfc,0xa3,0xe0,0xfd,0xa3,0xe0, ++0xfe,0xa3,0xe0,0xff,0xec,0x54,0x03,0xfc,0xeb,0x4f,0xff,0xea,0x4e,0xfe,0xe9,0x4d, ++0xfd,0xe8,0x4c,0xfc,0x90,0x97,0x6f,0x12,0x1d,0xa9,0x90,0x05,0x22,0xe4,0xf0,0x90, ++0x97,0x6f,0xe0,0xfc,0xa3,0xe0,0xfd,0xa3,0xe0,0xfe,0xa3,0xe0,0xff,0x78,0x18,0x12, ++0x1d,0x83,0x90,0x04,0x96,0xef,0xf0,0x80,0x45,0xe4,0x90,0x97,0x63,0xf0,0x7f,0x80, ++0x7e,0x08,0x12,0x2b,0x13,0x90,0x97,0x65,0x12,0x1d,0xa9,0x90,0x97,0x65,0xe0,0xfc, ++0xa3,0xe0,0xfd,0xa3,0xe0,0xfe,0xa3,0xe0,0xff,0xec,0x44,0xc0,0xfc,0x90,0x97,0x65, ++0x12,0x1d,0xa9,0x90,0x97,0x65,0xe0,0xfc,0xa3,0xe0,0xfd,0xa3,0xe0,0xfe,0xa3,0xe0, ++0xff,0x90,0x81,0x56,0x12,0x1d,0xa9,0x7f,0x80,0x7e,0x08,0x12,0x33,0xd8,0x90,0x97, ++0x6c,0xe0,0x90,0x00,0x47,0x30,0xe1,0x11,0x74,0x0c,0xf0,0xa3,0xe0,0x44,0x0c,0xf0, ++0x90,0x00,0x46,0xe0,0x44,0x10,0xf0,0x80,0x10,0xe0,0x54,0xf3,0xf0,0xa3,0xe0,0x54, ++0xf3,0xf0,0x90,0x00,0x46,0xe0,0x54,0xef,0xf0,0xe4,0x90,0x97,0x69,0xf0,0x22,0x90, ++0x97,0x64,0xe0,0xc3,0x94,0x14,0x50,0x06,0xe0,0x04,0xf0,0x02,0x6a,0xd9,0x90,0x97, ++0x64,0xe0,0x64,0x14,0x60,0x03,0x02,0x6a,0xd9,0x90,0x97,0x73,0xe0,0x70,0x25,0x90, ++0x97,0x76,0xe0,0x70,0x1f,0x90,0x97,0x74,0xe0,0x70,0x19,0x90,0x97,0x77,0xe0,0x70, ++0x13,0x90,0x97,0x75,0xe0,0x70,0x0d,0x90,0x97,0x78,0xe0,0x70,0x07,0x90,0x04,0xfd, ++0xe0,0x54,0xfe,0xf0,0x90,0x97,0x73,0xe0,0x90,0x04,0x88,0xf0,0x90,0x97,0x74,0xe0, ++0x90,0x04,0x89,0xf0,0x90,0x97,0x75,0xe0,0x90,0x04,0x8a,0xf0,0xa3,0xe4,0xf0,0x90, ++0x97,0x76,0xe0,0x90,0x04,0x8c,0xf0,0x90,0x97,0x77,0xe0,0x90,0x04,0x8d,0xf0,0x90, ++0x97,0x78,0xe0,0x90,0x04,0x8e,0xf0,0xa3,0xe4,0xf0,0x90,0x97,0x5f,0xe0,0x90,0x04, ++0x90,0xf0,0x90,0x97,0x60,0xe0,0x90,0x04,0x91,0xf0,0x90,0x97,0x61,0xe0,0x90,0x04, ++0x92,0xf0,0x90,0x97,0x62,0xe0,0x90,0x04,0x93,0xf0,0xe4,0x90,0x97,0x64,0xf0,0x90, ++0x97,0x5f,0x04,0xf0,0xe4,0xa3,0xf0,0xa3,0xf0,0xa3,0xf0,0x90,0x97,0x73,0xf0,0xa3, ++0xf0,0xa3,0xf0,0xa3,0xf0,0xa3,0xf0,0xa3,0xf0,0x90,0x97,0x64,0xe0,0x90,0x04,0x97, ++0xf0,0x90,0x05,0x60,0xe0,0x90,0x97,0x3a,0xf0,0x90,0x05,0x61,0xe0,0x90,0x97,0x3b, ++0xf0,0x90,0x05,0x62,0xe0,0x90,0x97,0x3c,0xf0,0x90,0x05,0x63,0xe0,0x90,0x97,0x3d, ++0xf0,0x90,0x97,0x7c,0xe0,0xff,0x90,0x97,0x3d,0xe0,0xfe,0xd3,0x9f,0x50,0x0b,0x90, ++0x97,0x7c,0xe0,0xc3,0x9e,0xd3,0x94,0x01,0x40,0x11,0x90,0x97,0x6a,0xe0,0xb4,0x01, ++0x02,0x80,0x03,0x90,0x97,0x6e,0xe0,0xff,0x12,0x79,0x7c,0x22,0x90,0x97,0xb0,0xed, ++0xf0,0x90,0x97,0xaf,0xef,0xf0,0xd3,0x94,0x07,0x50,0x6d,0xe0,0xff,0x74,0x01,0xa8, ++0x07,0x08,0x80,0x02,0xc3,0x33,0xd8,0xfc,0xf4,0xff,0x90,0x00,0x47,0xe0,0x5f,0xf0, ++0x7f,0x10,0x7e,0x00,0x12,0x3a,0xa8,0x90,0x97,0xaf,0xe0,0xff,0x74,0x01,0xa8,0x07, ++0x08,0x80,0x02,0xc3,0x33,0xd8,0xfc,0xff,0x90,0x00,0x46,0xe0,0x4f,0xf0,0x7f,0x10, ++0x7e,0x00,0x12,0x3a,0xa8,0x90,0x97,0xb0,0xe0,0x60,0x16,0x90,0x97,0xaf,0xe0,0xff, ++0x74,0x01,0xa8,0x07,0x08,0x80,0x02,0xc3,0x33,0xd8,0xfc,0xff,0x90,0x00,0x45,0x80, ++0x78,0x90,0x97,0xaf,0xe0,0xff,0x74,0x01,0xa8,0x07,0x08,0x80,0x02,0xc3,0x33,0xd8, ++0xfc,0xf4,0xff,0x90,0x00,0x45,0x80,0x7d,0x90,0x97,0xaf,0xe0,0x24,0xf8,0xf0,0xe0, ++0xff,0x74,0x01,0xa8,0x07,0x08,0x80,0x02,0xc3,0x33,0xd8,0xfc,0xc4,0x54,0xf0,0xf4, ++0xff,0x90,0x00,0x43,0xe0,0x5f,0xf0,0x7f,0x10,0x7e,0x00,0x12,0x3a,0xa8,0x90,0x97, ++0xaf,0xe0,0xff,0x74,0x01,0xa8,0x07,0x08,0x80,0x02,0xc3,0x33,0xd8,0xfc,0xff,0x90, ++0x00,0x43,0xe0,0x4f,0xf0,0x7f,0x10,0x7e,0x00,0x12,0x3a,0xa8,0x90,0x97,0xb0,0xe0, ++0x60,0x1b,0x90,0x97,0xaf,0xe0,0xff,0x74,0x01,0xa8,0x07,0x08,0x80,0x02,0xc3,0x33, ++0xd8,0xfc,0xc4,0x54,0xf0,0xff,0x90,0x00,0x42,0xe0,0x4f,0x80,0x1a,0x90,0x97,0xaf, ++0xe0,0xff,0x74,0x01,0xa8,0x07,0x08,0x80,0x02,0xc3,0x33,0xd8,0xfc,0xc4,0x54,0xf0, ++0xf4,0xff,0x90,0x00,0x42,0xe0,0x5f,0xf0,0x7f,0x10,0x7e,0x00,0x12,0x3a,0xa8,0x22, ++0x90,0x01,0xc4,0x74,0x30,0xf0,0x74,0x6c,0xa3,0xf0,0x7f,0x78,0x7e,0x08,0x12,0x2b, ++0x13,0x90,0x97,0x1d,0x12,0x1d,0xa9,0x7f,0x04,0x7e,0x0c,0x12,0x2b,0x13,0x90,0x97, ++0x21,0x12,0x1d,0xa9,0x7f,0x00,0x7e,0x08,0x12,0x2b,0x13,0x90,0x97,0x25,0x12,0x1d, ++0xa9,0x90,0x97,0x97,0xe0,0x90,0x97,0x1d,0xb4,0x01,0x13,0xe0,0xfc,0xa3,0xe0,0xfd, ++0xa3,0xe0,0xfe,0xa3,0xe0,0x54,0xc7,0xff,0xed,0x54,0xc7,0xfd,0x80,0x0d,0xe0,0xfc, ++0xa3,0xe0,0xfd,0xa3,0xe0,0xfe,0xa3,0xe0,0x54,0xc7,0xff,0xec,0x90,0x81,0x56,0x12, ++0x1d,0xa9,0x7f,0x78,0x7e,0x08,0x12,0x33,0xd8,0x90,0x97,0x21,0xe0,0xfc,0xa3,0xe0, ++0xfd,0xa3,0xe0,0xfe,0xa3,0xe0,0x54,0x0f,0xff,0xec,0x90,0x81,0x56,0x12,0x1d,0xa9, ++0x7f,0x04,0x7e,0x0c,0x12,0x33,0xd8,0x90,0x97,0x25,0xe0,0xfc,0xa3,0xe0,0xfd,0xa3, ++0xe0,0xfe,0xa3,0xe0,0x44,0x02,0xff,0xec,0x90,0x81,0x56,0x12,0x1d,0xa9,0x7f,0x00, ++0x7e,0x08,0x12,0x33,0xd8,0x7f,0x70,0x7e,0x0e,0x12,0x2b,0x13,0x90,0x97,0x29,0x12, ++0x1d,0xa9,0x90,0x81,0x56,0x12,0x1d,0xb5,0x00,0x1b,0x25,0xa0,0x7f,0x70,0x7e,0x0e, ++0x12,0x33,0xd8,0x90,0x81,0x24,0x12,0x1d,0xb5,0x00,0x00,0x00,0x00,0xe4,0xfd,0xff, ++0x12,0x38,0xb6,0x90,0x97,0x97,0xe0,0xb4,0x01,0x11,0x90,0x81,0x24,0x12,0x1d,0xb5, ++0x00,0x00,0x00,0x00,0xe4,0xfd,0x7f,0x01,0x12,0x38,0xb6,0x90,0x00,0x11,0xe0,0x54, ++0xf6,0xf0,0x7f,0x10,0x7e,0x00,0x02,0x3a,0xa8,0x90,0x97,0x7d,0xe0,0x64,0x01,0x60, ++0x09,0x90,0x97,0x6b,0xe0,0x60,0x03,0x02,0x6e,0x01,0x90,0x97,0x5f,0xe0,0xc3,0x94, ++0xff,0x50,0x05,0xe0,0x04,0xf0,0x80,0x3b,0x90,0x97,0x60,0xe0,0xc3,0x94,0xff,0x50, ++0x06,0xe0,0x04,0xf0,0xe4,0x80,0x28,0x90,0x97,0x61,0xe0,0xc3,0x94,0xff,0x50,0x0a, ++0xe0,0x04,0xf0,0xe4,0x90,0x97,0x60,0xf0,0x80,0x15,0x90,0x97,0x62,0xe0,0xc3,0x94, ++0xff,0x50,0x10,0xe0,0x04,0xf0,0xe4,0x90,0x97,0x61,0xf0,0x90,0x97,0x60,0xf0,0x90, ++0x97,0x5f,0xf0,0x90,0x00,0x44,0xe0,0x54,0x0c,0x60,0x76,0xe0,0x30,0xe2,0x32,0x90, ++0x97,0x73,0xe0,0xc3,0x94,0xff,0x50,0x05,0xe0,0x04,0xf0,0x80,0x24,0x90,0x97,0x74, ++0xe0,0xc3,0x94,0xff,0x50,0x06,0xe0,0x04,0xf0,0xe4,0x80,0x11,0x90,0x97,0x75,0xe0, ++0xc3,0x94,0xff,0x50,0x0c,0xe0,0x04,0xf0,0xe4,0x90,0x97,0x74,0xf0,0x90,0x97,0x73, ++0xf0,0x90,0x00,0x44,0xe0,0x30,0xe3,0x32,0x90,0x97,0x76,0xe0,0xc3,0x94,0xff,0x50, ++0x05,0xe0,0x04,0xf0,0x80,0x24,0x90,0x97,0x77,0xe0,0xc3,0x94,0xff,0x50,0x06,0xe0, ++0x04,0xf0,0xe4,0x80,0x11,0x90,0x97,0x78,0xe0,0xc3,0x94,0xff,0x50,0x0c,0xe0,0x04, ++0xf0,0xe4,0x90,0x97,0x77,0xf0,0x90,0x97,0x76,0xf0,0x90,0x04,0xfd,0xe0,0x44,0x01, ++0xf0,0x22,0x90,0x97,0x43,0xeb,0xf0,0xa3,0xea,0xf0,0xa3,0xe9,0xf0,0xad,0x07,0x90, ++0x01,0xc4,0x74,0x02,0xf0,0x74,0x6e,0xa3,0xf0,0xed,0x12,0x66,0xc1,0x6e,0x3f,0x01, ++0x6e,0x4d,0x02,0x6e,0x5b,0x03,0x6e,0x69,0x05,0x6e,0x77,0x06,0x6e,0x85,0x07,0x6e, ++0x93,0x09,0x6e,0xa1,0x0c,0x6e,0xaf,0x0d,0x6e,0xbd,0x0e,0x00,0x00,0x6e,0xcb,0x90, ++0x97,0x43,0xe0,0xfb,0xa3,0xe0,0xfa,0xa3,0xe0,0xf9,0x02,0x7d,0x9d,0x90,0x97,0x43, ++0xe0,0xfb,0xa3,0xe0,0xfa,0xa3,0xe0,0xf9,0x02,0x7f,0x77,0x90,0x97,0x43,0xe0,0xfb, ++0xa3,0xe0,0xfa,0xa3,0xe0,0xf9,0x02,0x7d,0x17,0x90,0x97,0x43,0xe0,0xfb,0xa3,0xe0, ++0xfa,0xa3,0xe0,0xf9,0x02,0x7c,0x0b,0x90,0x97,0x43,0xe0,0xfb,0xa3,0xe0,0xfa,0xa3, ++0xe0,0xf9,0x02,0x66,0xe7,0x90,0x97,0x43,0xe0,0xfb,0xa3,0xe0,0xfa,0xa3,0xe0,0xf9, ++0x02,0x7f,0x28,0x90,0x97,0x43,0xe0,0xfb,0xa3,0xe0,0xfa,0xa3,0xe0,0xf9,0x02,0x73, ++0x14,0x90,0x97,0x43,0xe0,0xfb,0xa3,0xe0,0xfa,0xa3,0xe0,0xf9,0x02,0x64,0x34,0x90, ++0x97,0x43,0xe0,0xfb,0xa3,0xe0,0xfa,0xa3,0xe0,0xf9,0x02,0x7c,0x7e,0x90,0x97,0x43, ++0xe0,0xfb,0xa3,0xe0,0xfa,0xa3,0xe0,0xf9,0x02,0x69,0x0f,0xc2,0xaf,0x74,0x02,0x04, ++0x90,0x01,0xc4,0xf0,0x74,0x6e,0xa3,0xf0,0x80,0xfe,0x8f,0x62,0x8d,0x63,0x90,0x01, ++0xc4,0x74,0xda,0xf0,0x74,0x6e,0xa3,0xf0,0xe5,0x62,0x54,0x0f,0xff,0x90,0x97,0x88, ++0xe0,0x54,0x0f,0x6f,0x60,0x78,0xe5,0x62,0x30,0xe2,0x30,0x90,0x97,0x88,0xe0,0x20, ++0xe2,0x05,0x7f,0x01,0x12,0x7e,0x08,0x90,0x97,0x88,0xe0,0x30,0xe3,0x0a,0xe5,0x62, ++0x20,0xe3,0x05,0x12,0x7e,0x27,0x80,0x56,0x90,0x97,0x88,0xe0,0x20,0xe3,0x4f,0xe5, ++0x62,0x30,0xe3,0x4a,0xaf,0x63,0x12,0x7d,0xe8,0x80,0x43,0x90,0x97,0x88,0xe0,0x54, ++0x0f,0xff,0xbf,0x0c,0x0e,0xe5,0x62,0x20,0xe3,0x09,0x12,0x7d,0x72,0xef,0x60,0x2e, ++0x12,0x7e,0x27,0x90,0x97,0x88,0xe0,0x54,0x0f,0xff,0xbf,0x04,0x0e,0xe5,0x62,0x20, ++0xe2,0x09,0x12,0x7b,0x8a,0xef,0x60,0x16,0x12,0x7c,0x47,0x90,0x97,0x88,0xe0,0x54, ++0x0f,0xff,0xbf,0x02,0x09,0x12,0x7a,0xb8,0xef,0x60,0x03,0x12,0x7e,0x44,0x90,0x97, ++0x88,0xe0,0x54,0x0f,0xff,0x90,0x97,0x8b,0xe0,0x54,0x0f,0x6f,0x70,0x23,0xe0,0x30, ++0xe6,0x1f,0x90,0x97,0x88,0xe0,0x54,0x0f,0xff,0x90,0x97,0x7e,0xe0,0xfe,0x4f,0x90, ++0x01,0x2f,0xf0,0xee,0x64,0x80,0x90,0x97,0x7e,0xf0,0x90,0x97,0x8b,0xe0,0x54,0xbf, ++0xf0,0x22,0x90,0x97,0x6b,0xe0,0x64,0x01,0x60,0x03,0x02,0x70,0x65,0x90,0x00,0x46, ++0xe0,0x44,0x01,0xf0,0x90,0x97,0x7d,0xe0,0x70,0x40,0x90,0x97,0x63,0xe0,0x60,0x1d, ++0x90,0x97,0x6f,0xe0,0xfc,0xa3,0xe0,0xfd,0xa3,0xe0,0xfe,0xa3,0xe0,0xff,0x90,0x81, ++0x56,0x12,0x1d,0xa9,0x7f,0x80,0x7e,0x08,0x12,0x33,0xd8,0x80,0x06,0x90,0x05,0x22, ++0x74,0x7f,0xf0,0x90,0x97,0x6a,0xe0,0xff,0x12,0x79,0x7c,0x90,0x97,0x7d,0x74,0x01, ++0xf0,0x90,0x00,0x45,0xe0,0x54,0xfe,0xf0,0x80,0x44,0x90,0x97,0x7d,0xe0,0x64,0x01, ++0x70,0x3c,0x90,0x97,0x6e,0xe0,0xff,0x12,0x79,0x7c,0xe4,0x90,0x97,0x7d,0xf0,0x90, ++0x00,0x45,0xe0,0x44,0x01,0xf0,0x90,0x97,0x63,0xe0,0x60,0x1d,0x90,0x97,0x65,0xe0, ++0xfc,0xa3,0xe0,0xfd,0xa3,0xe0,0xfe,0xa3,0xe0,0xff,0x90,0x81,0x56,0x12,0x1d,0xa9, ++0x7f,0x80,0x7e,0x08,0x12,0x33,0xd8,0x80,0x05,0x90,0x05,0x22,0xe4,0xf0,0x90,0x05, ++0x87,0xe0,0x64,0x80,0xf0,0x90,0x97,0x79,0xe0,0x90,0x05,0x84,0xf0,0x90,0x97,0x7a, ++0xe0,0x90,0x05,0x85,0xf0,0x90,0x97,0x7b,0xe0,0x90,0x05,0x86,0xf0,0x90,0x97,0x7c, ++0xe0,0x90,0x05,0x87,0xf0,0x22,0x90,0x97,0x30,0xeb,0xf0,0xa3,0xea,0xf0,0xa3,0xe9, ++0xf0,0x90,0x97,0x96,0xe0,0x64,0x02,0x70,0x03,0x02,0x71,0x1b,0x90,0x01,0xaf,0xe0, ++0x60,0x09,0x90,0x01,0xc7,0xe0,0x04,0xf0,0xf0,0x80,0xf1,0x90,0x97,0xb3,0xe0,0xff, ++0x04,0xf0,0x90,0x97,0x30,0xe0,0xfb,0xa3,0xe0,0xfa,0xa3,0xe0,0xf9,0x90,0x00,0x01, ++0xef,0x12,0x65,0xa7,0xa2,0xaf,0xe4,0x33,0x90,0x97,0x36,0xf0,0xc2,0xaf,0x90,0x97, ++0x30,0xe0,0xfb,0xa3,0xe0,0xfa,0xa3,0xe0,0x8b,0x24,0x8a,0x25,0xf5,0x26,0x75,0x27, ++0x02,0x7b,0x01,0x7a,0x01,0x79,0xa0,0x12,0x79,0x27,0x90,0x97,0x36,0xe0,0x24,0xff, ++0x92,0xaf,0xa2,0xaf,0xe4,0x33,0xf0,0xc2,0xaf,0x90,0x97,0x33,0xe0,0xfb,0xa3,0xe0, ++0xfa,0xa3,0xe0,0x8b,0x24,0x8a,0x25,0xf5,0x26,0x90,0x97,0x30,0xe0,0xfb,0xa3,0xe0, ++0xfa,0xa3,0xe0,0xf9,0x12,0x1c,0xd6,0xff,0xc4,0x54,0x0f,0xf5,0x27,0x7b,0x01,0x7a, ++0x01,0x79,0xa2,0x12,0x79,0x27,0x90,0x97,0x36,0xe0,0x24,0xff,0x92,0xaf,0x90,0x01, ++0xaf,0x74,0xff,0xf0,0x90,0x01,0xcb,0xe0,0x64,0x80,0xf0,0x22,0x90,0x01,0xc4,0x74, ++0x1c,0xf0,0x74,0x71,0xa3,0xf0,0x90,0x00,0x11,0xe0,0x44,0x09,0xf0,0x7f,0x10,0x7e, ++0x00,0x12,0x3a,0xa8,0x90,0x97,0x1d,0xe0,0xfc,0xa3,0xe0,0xfd,0xa3,0xe0,0xfe,0xa3, ++0xe0,0xff,0x90,0x81,0x56,0x12,0x1d,0xa9,0x7f,0x78,0x7e,0x08,0x12,0x33,0xd8,0x90, ++0x97,0x21,0xe0,0xfc,0xa3,0xe0,0xfd,0xa3,0xe0,0xfe,0xa3,0xe0,0xff,0x90,0x81,0x56, ++0x12,0x1d,0xa9,0x7f,0x04,0x7e,0x0c,0x12,0x33,0xd8,0x90,0x97,0x25,0xe0,0xfc,0xa3, ++0xe0,0xfd,0xa3,0xe0,0xfe,0xa3,0xe0,0xff,0x90,0x81,0x56,0x12,0x1d,0xa9,0x7f,0x00, ++0x7e,0x08,0x12,0x33,0xd8,0x90,0x97,0x29,0xe0,0xfc,0xa3,0xe0,0xfd,0xa3,0xe0,0xfe, ++0xa3,0xe0,0xff,0x90,0x81,0x56,0x12,0x1d,0xa9,0x7f,0x70,0x7e,0x0e,0x12,0x33,0xd8, ++0x90,0x81,0x24,0x12,0x1d,0xb5,0x00,0x03,0x2d,0x95,0xe4,0xfd,0xff,0x12,0x38,0xb6, ++0x90,0x97,0x97,0xe0,0xb4,0x01,0x11,0x90,0x81,0x24,0x12,0x1d,0xb5,0x00,0x03,0x2d, ++0x95,0xe4,0xfd,0x7f,0x01,0x12,0x38,0xb6,0x22,0x90,0x97,0x9e,0xef,0xf0,0xa3,0xed, ++0xf0,0xe4,0xa3,0xf0,0xa3,0xf0,0xe5,0x65,0x60,0x05,0xe4,0xff,0x12,0x7e,0x99,0x90, ++0x97,0x9e,0xe0,0x30,0xe0,0x09,0x90,0x97,0xa0,0xe4,0xf0,0xa3,0x74,0x80,0xf0,0x90, ++0x04,0x1d,0xe0,0x60,0x1d,0x90,0x05,0x22,0xe0,0x90,0x97,0xa2,0xf0,0xe0,0xff,0x54, ++0x90,0x60,0xec,0x90,0x01,0xc8,0x74,0xfc,0xf0,0xef,0x54,0x6f,0x90,0x05,0x22,0xf0, ++0x80,0xdd,0x90,0x97,0x9e,0xe0,0xff,0xc3,0x13,0x90,0xfd,0x10,0xf0,0x90,0x04,0x25, ++0xef,0xf0,0x90,0x97,0x9f,0xe0,0x60,0x10,0xa3,0xa3,0xe0,0x24,0x10,0xf5,0x82,0xe4, ++0x34,0xfc,0xf5,0x83,0xe0,0x44,0x80,0xf0,0x90,0x97,0xa0,0xa3,0xe0,0xff,0xfd,0x24, ++0x08,0xf5,0x82,0xe4,0x34,0xfc,0xf5,0x83,0xe4,0xf0,0x74,0x09,0x2d,0xf5,0x82,0xe4, ++0x34,0xfc,0xf5,0x83,0xe0,0x54,0xf0,0xf0,0x74,0x21,0x2f,0xf5,0x82,0xe4,0x34,0xfc, ++0xf5,0x83,0xe0,0x54,0xf7,0xf0,0x90,0x97,0xa0,0xe0,0xfe,0xa3,0xe0,0xff,0x22,0x90, ++0x97,0xb5,0xef,0xf0,0xd3,0x94,0x07,0x50,0x4a,0xe0,0xff,0x74,0x01,0xa8,0x07,0x08, ++0x80,0x02,0xc3,0x33,0xd8,0xfc,0xf4,0xff,0x90,0x00,0x46,0xe0,0x5f,0xf0,0x7f,0x10, ++0x7e,0x00,0x12,0x3a,0xa8,0x90,0x97,0xb5,0xe0,0xfd,0x74,0x01,0x7e,0x00,0xa8,0x05, ++0x08,0x80,0x05,0xc3,0x33,0xce,0x33,0xce,0xd8,0xf9,0xff,0x90,0x00,0x44,0xe0,0xfb, ++0xe4,0xfe,0xef,0x5b,0xa8,0x05,0x08,0x80,0x06,0xce,0xa2,0xe7,0x13,0xce,0x13,0xd8, ++0xf8,0xff,0x22,0x90,0x97,0xb5,0xe0,0x24,0xf8,0xf0,0xe0,0xff,0x74,0x01,0xa8,0x07, ++0x08,0x80,0x02,0xc3,0x33,0xd8,0xfc,0xf4,0xff,0x90,0x00,0x43,0xe0,0x5f,0xf0,0x7f, ++0x10,0x7e,0x00,0x12,0x3a,0xa8,0x90,0x97,0xb5,0xe0,0xfd,0x74,0x01,0x7e,0x00,0xa8, ++0x05,0x08,0x80,0x05,0xc3,0x33,0xce,0x33,0xce,0xd8,0xf9,0xff,0x90,0x00,0x42,0xe0, ++0xfb,0xe4,0xfe,0xef,0x5b,0xa8,0x05,0x08,0x80,0x06,0xce,0xa2,0xe7,0x13,0xce,0x13, ++0xd8,0xf8,0xff,0x22,0x90,0x97,0x46,0xeb,0xf0,0xa3,0xea,0xf0,0xa3,0xe9,0xf0,0xa2, ++0xaf,0xe4,0x33,0xa3,0xf0,0xc2,0xaf,0x90,0x97,0x46,0xe0,0xfb,0xa3,0xe0,0xfa,0xa3, ++0xe0,0xf9,0x90,0x00,0x01,0x12,0x66,0x20,0xfa,0xe5,0xf0,0x24,0x00,0xff,0xe4,0x3a, ++0xfe,0x90,0x97,0x46,0xa3,0xe0,0xfa,0x90,0x00,0x01,0xee,0x8f,0xf0,0x12,0x66,0x77, ++0x12,0x1c,0xd6,0xff,0x60,0x37,0xb5,0x5e,0x1b,0x90,0x97,0x46,0xe0,0xfb,0xa3,0xe0, ++0xfa,0xa3,0xe0,0xf9,0x90,0x00,0x01,0x12,0x66,0x20,0x65,0x60,0x70,0x04,0xe5,0x5f, ++0x65,0xf0,0x60,0x2e,0x90,0x97,0x46,0xe0,0xfb,0xa3,0xe0,0xfa,0xa3,0xe0,0xf9,0x90, ++0x00,0x01,0x12,0x66,0x20,0xff,0xae,0xf0,0x12,0x7c,0xb4,0x80,0x15,0x90,0x97,0x46, ++0xe0,0xfb,0xa3,0xe0,0xfa,0xa3,0xe0,0xf9,0x12,0x1c,0xd6,0x65,0x5e,0x60,0x03,0x12, ++0x7f,0x56,0x90,0x97,0x49,0xe0,0x24,0xff,0x92,0xaf,0x22,0xc0,0xe0,0xc0,0xf0,0xc0, ++0x83,0xc0,0x82,0xc0,0xd0,0x75,0xd0,0x00,0xc0,0x00,0xc0,0x01,0xc0,0x02,0xc0,0x03, ++0xc0,0x04,0xc0,0x05,0xc0,0x06,0xc0,0x07,0x90,0x01,0xc4,0x74,0xab,0xf0,0x74,0x73, ++0xa3,0xf0,0x53,0x91,0xef,0x90,0x00,0x51,0xe0,0xff,0x90,0x00,0x55,0xe0,0x5f,0xf5, ++0x3d,0xe5,0x3d,0x30,0xe6,0x18,0x74,0x40,0xf0,0x90,0x97,0x6c,0xe0,0x54,0x03,0xff, ++0xbf,0x03,0x0b,0x90,0x97,0x69,0xe0,0x60,0x05,0x7f,0x01,0x12,0x44,0x7b,0xe5,0x3d, ++0x30,0xe7,0x15,0x90,0x00,0x55,0x74,0x80,0xf0,0x90,0x97,0x6c,0xe0,0x54,0x03,0xff, ++0xbf,0x03,0x05,0x7f,0x02,0x12,0x44,0x7b,0x90,0x01,0xc4,0x74,0xab,0xf0,0x74,0x73, ++0xa3,0xf0,0xd0,0x07,0xd0,0x06,0xd0,0x05,0xd0,0x04,0xd0,0x03,0xd0,0x02,0xd0,0x01, ++0xd0,0x00,0xd0,0xd0,0xd0,0x82,0xd0,0x83,0xd0,0xf0,0xd0,0xe0,0x32,0xef,0x60,0x34, ++0x7d,0x7d,0x7f,0x02,0x12,0x39,0xbe,0x7d,0x02,0x7f,0x03,0x12,0x39,0xbe,0x90,0x01, ++0x57,0xe4,0xf0,0x90,0x01,0x3c,0x74,0x02,0xf0,0x7d,0x01,0x7f,0x0c,0x12,0x6e,0xda, ++0xe4,0xff,0x12,0x7e,0x99,0x90,0x06,0x04,0xe0,0x54,0x7f,0xf0,0x90,0x06,0x0a,0xe0, ++0x54,0xf8,0xf0,0x22,0x90,0x01,0x36,0x74,0x7d,0xf0,0xa3,0x74,0x02,0xf0,0x7d,0x7d, ++0xff,0x12,0x3a,0x2f,0x7d,0x02,0x7f,0x03,0x12,0x3a,0x2f,0x90,0x06,0x04,0xe0,0x44, ++0x80,0xf0,0x90,0x06,0x0a,0xe0,0x44,0x07,0xf0,0x90,0x97,0x83,0xe0,0xa3,0xe0,0x90, ++0x05,0x58,0xf0,0xe5,0x64,0x30,0xe0,0x1b,0x90,0x97,0x81,0xe0,0x70,0x1a,0xe0,0x04, ++0xf0,0x90,0x97,0x88,0xe0,0x54,0x0f,0xc3,0x94,0x04,0x50,0x0c,0x7d,0x01,0x7f,0x04, ++0x02,0x6e,0xda,0xe4,0x90,0x97,0x81,0xf0,0x22,0x02,0x75,0x07,0x02,0x62,0xd3,0xe4, ++0x93,0xa3,0xf8,0xe4,0x93,0xa3,0x40,0x03,0xf6,0x80,0x01,0xf2,0x08,0xdf,0xf4,0x80, ++0x29,0xe4,0x93,0xa3,0xf8,0x54,0x07,0x24,0x0c,0xc8,0xc3,0x33,0xc4,0x54,0x0f,0x44, ++0x20,0xc8,0x83,0x40,0x04,0xf4,0x56,0x80,0x01,0x46,0xf6,0xdf,0xe4,0x80,0x0b,0x01, ++0x02,0x04,0x08,0x10,0x20,0x40,0x80,0x90,0x7f,0x0e,0xe4,0x7e,0x01,0x93,0x60,0xbc, ++0xa3,0xff,0x54,0x3f,0x30,0xe5,0x09,0x54,0x1f,0xfe,0xe4,0x93,0xa3,0x60,0x01,0x0e, ++0xcf,0x54,0xc0,0x25,0xe0,0x60,0xa8,0x40,0xb8,0xe4,0x93,0xa3,0xfa,0xe4,0x93,0xa3, ++0xf8,0xe4,0x93,0xa3,0xc8,0xc5,0x82,0xc8,0xca,0xc5,0x83,0xca,0xf0,0xa3,0xc8,0xc5, ++0x82,0xc8,0xca,0xc5,0x83,0xca,0xdf,0xe9,0xde,0xe7,0x80,0xbe,0x8f,0x0f,0x74,0x75, ++0x90,0x01,0xc4,0xf0,0xa3,0x74,0x4c,0xf0,0xe5,0x0f,0x75,0xf0,0x08,0xa4,0x24,0x67, ++0xf5,0x82,0xe4,0x34,0x93,0xf5,0x83,0xe0,0xff,0x74,0xa5,0x25,0x0f,0xf5,0x82,0xe4, ++0x34,0x96,0xf5,0x83,0xe0,0x54,0x1f,0xfb,0xd3,0x9f,0x40,0x02,0xab,0x07,0xeb,0x25, ++0xe0,0x24,0x9e,0xf5,0x82,0xe4,0x34,0x41,0xf5,0x83,0xe4,0x93,0xfe,0x74,0x01,0x93, ++0xff,0xeb,0x25,0xe0,0x24,0x66,0xf5,0x82,0xe4,0x34,0x41,0xf5,0x83,0x74,0x01,0x93, ++0x2f,0xff,0xe4,0x93,0x3e,0xc3,0x13,0xfe,0xef,0x13,0xff,0xe4,0xfc,0xfd,0xe5,0x0f, ++0x25,0xe0,0x25,0xe0,0x24,0xe1,0xf5,0x82,0xe4,0x34,0x92,0xf5,0x83,0x12,0x1d,0xa9, ++0x74,0x84,0x25,0x0f,0xf5,0x82,0xe4,0x34,0x04,0xf5,0x83,0xeb,0xf0,0xff,0x22,0x90, ++0x97,0x4c,0xef,0xf0,0xd3,0x94,0x07,0x50,0x33,0xe0,0xff,0x74,0x01,0xa8,0x07,0x08, ++0x80,0x02,0xc3,0x33,0xd8,0xfc,0xf4,0xff,0x90,0x00,0x47,0xe0,0x5f,0xf0,0x7f,0x10, ++0x7e,0x00,0x12,0x3a,0xa8,0x90,0x97,0x4c,0xe0,0xff,0x74,0x01,0xa8,0x07,0x08,0x80, ++0x02,0xc3,0x33,0xd8,0xfc,0xf4,0xff,0x90,0x00,0x46,0x80,0x3b,0x90,0x97,0x4c,0xe0, ++0x24,0xf8,0xf0,0xe0,0xff,0x74,0x01,0xa8,0x07,0x08,0x80,0x02,0xc3,0x33,0xd8,0xfc, ++0xc4,0x54,0xf0,0xf4,0xff,0x90,0x00,0x43,0xe0,0x5f,0xf0,0x7f,0x10,0x7e,0x00,0x12, ++0x3a,0xa8,0x90,0x97,0x4c,0xe0,0xff,0x74,0x01,0xa8,0x07,0x08,0x80,0x02,0xc3,0x33, ++0xd8,0xfc,0xf4,0xff,0x90,0x00,0x43,0xe0,0x5f,0xf0,0x7f,0x10,0x7e,0x00,0x12,0x3a, ++0xa8,0x22,0x8f,0x0a,0x8d,0x0b,0xad,0x03,0x74,0x76,0x90,0x01,0xc4,0xf0,0xa3,0x74, ++0x52,0xf0,0xe5,0x0b,0x54,0x1f,0xf9,0x74,0x01,0x25,0x0a,0xf5,0x82,0xe4,0x34,0x92, ++0xf5,0x83,0xe0,0xff,0x90,0x04,0xfd,0xe0,0xb4,0x01,0x05,0x75,0x0e,0x03,0x80,0x03, ++0x75,0x0e,0x01,0xed,0xd3,0x95,0x0e,0x40,0x05,0xaf,0x0a,0x02,0x75,0x4c,0x90,0x01, ++0xc5,0x74,0x20,0xf0,0xe5,0x0d,0x2f,0xff,0xe9,0x90,0x41,0xd6,0x93,0xfe,0xef,0xd3, ++0x9e,0x40,0x22,0x90,0x01,0xc5,0x74,0x40,0xf0,0x74,0x01,0x25,0x0a,0xf5,0x82,0xe4, ++0x34,0x92,0xf5,0x83,0xe4,0xf0,0x74,0x84,0x25,0x0a,0xf5,0x82,0xe4,0x34,0x04,0xf5, ++0x83,0xe5,0x0b,0xf0,0x22,0x74,0x01,0x25,0x0a,0xf5,0x82,0xe4,0x34,0x92,0xf5,0x83, ++0xef,0xf0,0x22,0xe4,0x90,0x97,0x2e,0xf0,0xe5,0x65,0x60,0x6c,0xe5,0x64,0x64,0x01, ++0x70,0x66,0xe5,0x65,0x64,0x02,0x60,0x06,0xe5,0x65,0x64,0x03,0x70,0x1d,0x90,0x97, ++0x7f,0xe0,0x14,0xf0,0xe0,0x60,0x04,0xa3,0xe0,0x60,0x16,0x90,0x97,0x7f,0xe0,0x70, ++0x0a,0x90,0x97,0x8a,0xe0,0x90,0x97,0x7f,0xf0,0x80,0x00,0x90,0x97,0x2e,0x74,0x01, ++0xf0,0x90,0x97,0x2e,0xe0,0x60,0x31,0x90,0x97,0x8f,0xe0,0x44,0x10,0xf0,0x90,0x97, ++0x85,0xe0,0xf5,0x48,0xe4,0xf5,0x49,0xfb,0xfd,0x7f,0x54,0x7e,0x01,0x12,0x38,0xec, ++0x90,0x01,0x57,0x74,0x05,0xf0,0x90,0x97,0x88,0xe0,0x54,0x0f,0xc3,0x94,0x04,0x50, ++0x07,0x7d,0x01,0x7f,0x04,0x12,0x6e,0xda,0x22,0x90,0x06,0xa9,0xe0,0xf5,0x0a,0x54, ++0xc0,0x70,0x0e,0x90,0x97,0x89,0xf0,0x90,0x97,0x8b,0xe0,0xff,0x7d,0x01,0x02,0x6e, ++0xda,0xe5,0x0a,0x30,0xe6,0x12,0x90,0x97,0x89,0x74,0x01,0xf0,0x90,0x97,0x8f,0xe0, ++0x44,0x01,0xf0,0x12,0x7e,0x7e,0x80,0x07,0x90,0x97,0x8f,0xe0,0x54,0xfe,0xf0,0xe5, ++0x0a,0x30,0xe7,0x29,0x90,0x97,0x89,0x74,0x01,0xf0,0x90,0x97,0x8f,0xe0,0x44,0x02, ++0xf0,0x75,0x48,0x03,0xe4,0xf5,0x49,0xfb,0xfd,0x7f,0x54,0x7e,0x01,0x12,0x38,0xec, ++0x90,0x01,0x57,0x74,0x05,0xf0,0x90,0x97,0x8e,0x74,0x01,0xf0,0x22,0x90,0x97,0x8f, ++0xe0,0x54,0xfd,0xf0,0x22,0x90,0x00,0x2b,0xe0,0x44,0x01,0xf0,0x7f,0xe8,0x7e,0x03, ++0x12,0x3a,0xa8,0x90,0x00,0x08,0xe0,0x44,0x10,0xf0,0x7f,0x10,0x7e,0x00,0x12,0x3a, ++0xa8,0x90,0x00,0x09,0xe0,0x54,0xf7,0xf0,0x7f,0x10,0x7e,0x00,0x12,0x3a,0xa8,0x90, ++0x00,0x28,0xe0,0x54,0xfe,0xf0,0x7f,0x10,0x7e,0x00,0x12,0x3a,0xa8,0x90,0x00,0x20, ++0xe0,0x54,0xfe,0xf0,0x7f,0x10,0x7e,0x00,0x12,0x3a,0xa8,0x90,0x00,0x25,0xe0,0x44, ++0x40,0xf0,0x7f,0x10,0x7e,0x00,0x12,0x3a,0xa8,0x90,0x00,0x09,0xe0,0x54,0xef,0xf0, ++0x7f,0x10,0x7e,0x00,0x02,0x3a,0xa8,0x8b,0x10,0x8a,0x11,0x89,0x12,0x12,0x7e,0xcd, ++0xab,0x10,0xaa,0x11,0xa9,0x12,0x12,0x1c,0xd6,0xf5,0x65,0x14,0x60,0x0e,0x14,0x60, ++0x0f,0x14,0x60,0x1a,0x24,0x03,0x70,0x3c,0x7f,0x01,0x80,0x35,0xe4,0xff,0x80,0x31, ++0x90,0x97,0x8a,0x74,0x01,0xf0,0x90,0x97,0x7f,0xf0,0xe4,0xff,0x80,0x23,0xab,0x10, ++0xaa,0x11,0xa9,0x12,0x90,0x00,0x02,0x12,0x1c,0xef,0xff,0x90,0x97,0x8a,0x70,0x05, ++0x74,0x05,0xf0,0x80,0x02,0xef,0xf0,0x90,0x97,0x8a,0xe0,0x90,0x97,0x7f,0xf0,0xe4, ++0xff,0x12,0x74,0x3d,0x22,0x90,0x00,0x25,0xe0,0x54,0xbf,0xf0,0x7f,0x10,0x7e,0x00, ++0x12,0x3a,0xa8,0x90,0x00,0x20,0xe0,0x44,0x01,0xf0,0x7f,0x10,0x7e,0x00,0x12,0x3a, ++0xa8,0x90,0x00,0x28,0xe0,0x44,0x01,0xf0,0x7f,0x10,0x7e,0x00,0x12,0x3a,0xa8,0x90, ++0x00,0xf0,0xe0,0x30,0xe1,0xf9,0x90,0x00,0x09,0xe0,0x44,0x08,0xf0,0x7f,0x10,0x7e, ++0x00,0x12,0x3a,0xa8,0x90,0x00,0x08,0xe0,0x54,0xef,0xf0,0x7f,0x10,0x7e,0x00,0x12, ++0x3a,0xa8,0x90,0x00,0x2b,0xe0,0x54,0xfe,0xf0,0x7f,0xe8,0x7e,0x03,0x02,0x3a,0xa8, ++0x90,0x00,0x45,0xe4,0xf0,0x90,0x04,0xfd,0xf0,0xa3,0xf0,0x90,0x97,0x6d,0xf0,0x90, ++0x97,0x73,0xf0,0x90,0x97,0x76,0xf0,0x90,0x97,0x74,0xf0,0x90,0x97,0x77,0xf0,0x90, ++0x97,0x75,0xf0,0x90,0x97,0x78,0xf0,0x90,0x97,0x5f,0x04,0xf0,0xe4,0xa3,0xf0,0xa3, ++0xf0,0xa3,0xf0,0x90,0x97,0x64,0xf0,0x90,0x97,0x69,0xf0,0x90,0x97,0x6b,0xf0,0x90, ++0x97,0x7d,0xf0,0x90,0x97,0x6e,0xf0,0x90,0x97,0x6a,0xf0,0x90,0x97,0x63,0xf0,0x90, ++0x00,0x51,0xe0,0x44,0xc0,0xf0,0x22,0x8b,0x21,0x8a,0x22,0x89,0x23,0x90,0x97,0x98, ++0xeb,0xf0,0xa3,0xea,0xf0,0xa3,0xe9,0xf0,0xa3,0xe5,0x24,0xf0,0xa3,0xe5,0x25,0xf0, ++0xa3,0xe5,0x26,0xf0,0xaf,0x27,0x15,0x27,0xef,0x60,0x2a,0x90,0x97,0x9b,0xe0,0xfb, ++0xa3,0xe4,0x75,0xf0,0x01,0x12,0x65,0xdf,0xa9,0xf0,0xfa,0x12,0x1c,0xd6,0xff,0x90, ++0x97,0x98,0xe0,0xfb,0xa3,0xe4,0x75,0xf0,0x01,0x12,0x65,0xdf,0xa9,0xf0,0xfa,0xef, ++0x12,0x65,0x95,0x80,0xcf,0xab,0x21,0xaa,0x22,0xa9,0x23,0x22,0x90,0x05,0x60,0xe0, ++0x90,0x97,0x79,0xf0,0x90,0x05,0x61,0xe0,0x90,0x97,0x7a,0xf0,0x90,0x05,0x62,0xe0, ++0x90,0x97,0x7b,0xf0,0x90,0x05,0x63,0xe0,0x90,0x97,0x7c,0xf0,0xc3,0x74,0xff,0x9f, ++0xfe,0x90,0x97,0x7a,0xe0,0xd3,0x9e,0x40,0x1e,0xe0,0x2f,0xf0,0xa3,0xe0,0xb4,0xff, ++0x0f,0xe4,0xf0,0xa3,0xe0,0xb4,0xff,0x03,0xe4,0xf0,0x22,0x90,0x97,0x7c,0x80,0x03, ++0x90,0x97,0x7b,0xe0,0x04,0xf0,0x22,0x90,0x97,0x7a,0xe0,0x2f,0xf0,0x22,0xe4,0xf5, ++0x64,0x90,0x97,0x8f,0xf0,0xf5,0x65,0x90,0x97,0x8b,0x74,0x0c,0xf0,0x90,0x97,0x88, ++0xf0,0xe4,0x90,0x97,0x8d,0xf0,0x90,0x97,0x87,0xf0,0x90,0x97,0x86,0xf0,0x90,0x97, ++0x8a,0x04,0xf0,0x90,0x97,0x7f,0xf0,0xe4,0x90,0x97,0x8e,0xf0,0x90,0x97,0x89,0xf0, ++0x90,0x97,0x81,0xf0,0x90,0x97,0x85,0x74,0x07,0xf0,0xe4,0x90,0x97,0x80,0xf0,0x90, ++0x97,0x83,0xf0,0xa3,0x74,0x02,0xf0,0xe4,0x90,0x97,0x8c,0xf0,0x22,0xe4,0x90,0x97, ++0xad,0xf0,0xa3,0xf0,0x90,0x01,0xc4,0x74,0x1d,0xf0,0x74,0x7a,0xa3,0xf0,0x90,0x05, ++0xf8,0xe0,0x70,0x0f,0xa3,0xe0,0x70,0x0b,0xa3,0xe0,0x70,0x07,0xa3,0xe0,0x70,0x03, ++0x7f,0x01,0x22,0xd3,0x90,0x97,0xae,0xe0,0x94,0xe8,0x90,0x97,0xad,0xe0,0x94,0x03, ++0x40,0x03,0x7f,0x00,0x22,0x7f,0x32,0x7e,0x00,0x12,0x3a,0xa8,0x90,0x97,0xae,0xe0, ++0x04,0xf0,0x70,0xca,0x90,0x97,0xad,0xe0,0x04,0xf0,0x80,0xc2,0xe4,0x90,0x97,0x95, ++0xf0,0xa2,0xaf,0x33,0x90,0x97,0x3b,0xf0,0x90,0x00,0x80,0xe0,0x20,0xe1,0x1a,0x12, ++0x3a,0xbe,0x12,0x3a,0xbe,0x90,0x97,0x3a,0xe0,0x64,0x01,0xf0,0xe0,0x24,0x6c,0x90, ++0x01,0xc4,0xf0,0x74,0x7a,0xa3,0xf0,0x80,0xdf,0x90,0x06,0x30,0x74,0x01,0xf0,0xc2, ++0xaf,0x90,0x00,0x80,0xe0,0x44,0x80,0xf0,0x7f,0x10,0x7e,0x00,0x12,0x3a,0xa8,0x90, ++0x97,0x3b,0xe0,0x24,0xff,0x92,0xaf,0x22,0x90,0x01,0xc4,0x74,0xb8,0xf0,0x74,0x7a, ++0xa3,0xf0,0xe5,0x55,0x70,0x37,0x90,0x97,0x8b,0xe0,0x54,0x0f,0xd3,0x94,0x01,0x50, ++0x2c,0x90,0x02,0x87,0xe0,0x70,0x26,0x90,0x97,0x96,0xe0,0xb4,0x02,0x10,0x90,0x97, ++0x90,0xe0,0xfe,0xa3,0xe0,0xf5,0x82,0x8e,0x83,0xe0,0x60,0x08,0x80,0x0f,0x90,0x01, ++0xaf,0xe0,0x70,0x09,0x90,0x97,0x8c,0xe0,0x60,0x03,0x7f,0x01,0x22,0x7f,0x00,0x22, ++0x90,0x97,0x8e,0xe0,0x60,0x12,0xe4,0xf0,0xa3,0xe0,0x54,0xfd,0xf0,0xe0,0x54,0x03, ++0x70,0x33,0x90,0x97,0x89,0xf0,0x80,0x23,0x90,0x97,0x80,0xe0,0x04,0xf0,0x90,0x97, ++0x8f,0xe0,0x54,0xef,0xf0,0x90,0x97,0x80,0xe0,0xd3,0x94,0x01,0x40,0x0d,0xe5,0x64, ++0xb4,0x01,0x12,0xa3,0xe0,0x70,0x0e,0xe0,0x04,0xf0,0x22,0x90,0x97,0x8b,0xe0,0xff, ++0x7d,0x01,0x12,0x6e,0xda,0x22,0xe4,0x90,0x97,0x3a,0xf0,0xef,0x90,0x00,0x31,0xf0, ++0xee,0x54,0x03,0xff,0xa3,0xe0,0x54,0xfc,0x4f,0xf0,0xa3,0xe0,0x54,0x7f,0xf0,0x90, ++0x00,0x30,0xe0,0x20,0xe7,0x0e,0x90,0x97,0x3a,0xe0,0xc3,0x94,0x64,0x50,0x05,0xe0, ++0x04,0xf0,0x80,0xeb,0x90,0x97,0x3a,0xe0,0xc3,0x94,0x64,0x50,0x0a,0x90,0x00,0x30, ++0xe0,0x12,0x65,0x95,0x7f,0x01,0x22,0x7f,0x00,0x22,0x90,0x01,0xc4,0x74,0x8a,0xf0, ++0x74,0x7b,0xa3,0xf0,0x90,0x04,0x1b,0xe0,0x54,0x7f,0x64,0x7f,0x70,0x2b,0x90,0x97, ++0x89,0xe0,0x64,0x01,0x60,0x23,0x90,0x97,0x8b,0xe0,0x54,0x0f,0xd3,0x94,0x02,0x50, ++0x18,0x90,0x97,0x8f,0xe0,0x20,0xe4,0x11,0x90,0x97,0x87,0xe0,0x64,0x01,0x60,0x09, ++0x90,0x97,0x81,0xe0,0x70,0x03,0x7f,0x01,0x22,0x7f,0x00,0x22,0x8f,0x66,0x90,0x01, ++0xc4,0x74,0xcc,0xf0,0x74,0x7b,0xa3,0xf0,0x90,0x97,0x94,0xe0,0xff,0x7d,0x01,0x12, ++0x71,0xc9,0xe5,0x66,0x60,0x10,0x74,0x21,0x2f,0xf5,0x82,0xe4,0x34,0xfc,0xf5,0x83, ++0xe0,0x44,0x10,0xf0,0x80,0x0e,0x74,0x21,0x2f,0xf5,0x82,0xe4,0x34,0xfc,0xf5,0x83, ++0xe0,0x54,0xef,0xf0,0x90,0x04,0x1f,0x74,0x01,0xf0,0x22,0x12,0x1c,0xd6,0xff,0xc3, ++0x94,0x20,0x50,0x15,0x90,0x00,0x02,0x12,0x1c,0xef,0xfe,0x74,0x23,0x2f,0xf5,0x82, ++0xe4,0x34,0x95,0xf5,0x83,0xee,0xf0,0x80,0x0e,0xef,0xb4,0x20,0x0a,0x90,0x00,0x02, ++0x12,0x1c,0xef,0x90,0x93,0x61,0xf0,0x74,0x23,0x2f,0xf5,0x82,0xe4,0x34,0x95,0xf5, ++0x83,0xe0,0x90,0x04,0xb2,0xf0,0x22,0x90,0x01,0x37,0x74,0x02,0xf0,0x90,0x05,0x22, ++0x74,0xff,0xf0,0x12,0x7a,0x1d,0xef,0x70,0x06,0x90,0x01,0xc8,0x74,0xfd,0xf0,0x7d, ++0x02,0x7f,0x03,0x12,0x3a,0x2f,0xe5,0x65,0x60,0x05,0x7f,0x01,0x12,0x7e,0x99,0x12, ++0x6c,0x30,0x90,0x97,0x88,0xe0,0x54,0xf0,0xf0,0xe0,0x44,0x02,0xf0,0x22,0x90,0x00, ++0x02,0x12,0x1c,0xef,0x90,0x97,0x6d,0xf0,0xe0,0x90,0x04,0x9b,0xf0,0x90,0x97,0x6d, ++0xe0,0x60,0x04,0xe0,0xb4,0xff,0x1c,0xa2,0xaf,0xe4,0x33,0xf5,0x10,0xc2,0xaf,0x90, ++0x00,0x47,0xe0,0x54,0xfb,0xf0,0x7d,0x40,0x7f,0x01,0x12,0x39,0xf8,0xe5,0x10,0x24, ++0xff,0x92,0xaf,0x22,0x90,0x97,0x4a,0xee,0xf0,0xa3,0xef,0xf0,0x75,0x5e,0x01,0x8e, ++0x5f,0xf5,0x60,0x7f,0x0b,0x12,0x75,0xcf,0x12,0x7e,0x61,0xe4,0xff,0x12,0x7f,0x1b, ++0x90,0x97,0x4a,0xe0,0xfc,0xa3,0xe0,0xfd,0xec,0xfb,0x8d,0x48,0xe4,0xf5,0x49,0x7d, ++0x01,0x7f,0x60,0x7e,0x01,0x02,0x38,0xec,0x7d,0x02,0x7f,0x03,0x12,0x39,0xbe,0xe5, ++0x65,0x60,0x23,0x90,0x97,0x8d,0xe0,0x60,0x06,0x7d,0x01,0x7f,0x0c,0x80,0x0f,0x90, ++0x97,0x88,0xe0,0x54,0x0f,0xc3,0x94,0x04,0x50,0x07,0x7d,0x01,0x7f,0x04,0x12,0x6e, ++0xda,0xe4,0xff,0x12,0x7e,0x99,0x22,0x90,0x02,0x09,0xe0,0xfd,0x12,0x1c,0xd6,0xfe, ++0xaf,0x05,0xed,0x2e,0x90,0x97,0x92,0xf0,0x90,0x00,0x01,0x12,0x1c,0xef,0xff,0xed, ++0x2f,0x90,0x97,0x93,0xf0,0x90,0x00,0x02,0x12,0x1c,0xef,0xff,0xae,0x05,0xed,0x2f, ++0x90,0x97,0x94,0xf0,0x22,0x90,0x06,0x34,0xe0,0x60,0x26,0x14,0x70,0x1b,0x7b,0x01, ++0x7a,0x06,0x79,0x35,0x7f,0xf9,0x7e,0x01,0x12,0x7b,0x46,0xbf,0x01,0x09,0x90,0x06, ++0x35,0xe0,0x54,0x0f,0xf0,0x80,0x05,0x80,0x00,0x02,0x7f,0x00,0xe4,0x90,0x06,0x34, ++0xf0,0x22,0x90,0x01,0xc4,0x74,0x72,0xf0,0x74,0x7d,0xa3,0xf0,0x90,0x04,0x1b,0xe0, ++0x54,0x7f,0xff,0xbf,0x7f,0x14,0x90,0x97,0x87,0xe0,0x70,0x0e,0x90,0x97,0x8b,0xe0, ++0x54,0x0f,0xd3,0x94,0x04,0x50,0x03,0x7f,0x01,0x22,0x7f,0x00,0x22,0x90,0x00,0x01, ++0x12,0x1c,0xef,0x90,0x97,0x8d,0xf0,0x12,0x1c,0xd6,0x65,0x65,0x60,0x15,0xa2,0xaf, ++0xe4,0x33,0x90,0x97,0x46,0xf0,0xc2,0xaf,0x12,0x78,0x17,0x90,0x97,0x46,0xe0,0x24, ++0xff,0x92,0xaf,0x22,0x90,0x97,0x2e,0xe0,0x54,0xf0,0x44,0x03,0xf0,0x54,0x0f,0x44, ++0x80,0xf0,0x90,0x97,0x33,0xe4,0xf0,0xa3,0x74,0x00,0xf0,0xa3,0x74,0x56,0xf0,0x7b, ++0x01,0x7a,0x97,0x79,0x2e,0x02,0x70,0x66,0x90,0x06,0x04,0xe0,0x54,0xbf,0xf0,0xef, ++0x60,0x0a,0xe5,0x64,0xb4,0x01,0x05,0xe4,0xff,0x12,0x7b,0xcc,0x90,0x97,0x88,0xe0, ++0x54,0xf0,0xf0,0xe0,0x44,0x0c,0xf0,0x22,0x90,0x97,0xb2,0xef,0xf0,0x12,0x71,0x1c, ++0x90,0x97,0xb2,0xe0,0x60,0x05,0x90,0x05,0x22,0xe4,0xf0,0x90,0x97,0x88,0xe0,0x54, ++0xf0,0xf0,0xe0,0x44,0x04,0xf0,0x22,0x90,0x06,0x04,0xe0,0x44,0x40,0xf0,0xe5,0x64, ++0xb4,0x01,0x05,0x7f,0x01,0x12,0x7b,0xcc,0x90,0x97,0x88,0xe0,0x54,0xf0,0xf0,0xe0, ++0x44,0x04,0xf0,0x22,0x90,0x97,0x88,0xe0,0x54,0xf0,0xf0,0xe0,0x44,0x01,0xf0,0x12, ++0x77,0xb5,0x12,0x78,0x75,0x90,0x97,0x88,0xe0,0x54,0xf0,0xf0,0xe0,0x44,0x02,0xf0, ++0x22,0x7f,0x0b,0x12,0x72,0x6f,0xef,0x65,0x61,0x60,0x10,0xe5,0x61,0xb4,0x01,0x05, ++0xe4,0xf5,0x61,0x80,0x03,0x75,0x61,0x01,0x7f,0x01,0x22,0x7f,0x00,0x22,0x90,0x01, ++0xc4,0x74,0x7e,0xf0,0x74,0x7e,0xa3,0xf0,0x90,0x97,0x93,0xe0,0xff,0xe4,0xfd,0x12, ++0x71,0xc9,0x90,0x04,0x1f,0x74,0x01,0xf0,0x22,0xef,0x60,0x0b,0x90,0x97,0x97,0xe0, ++0xb4,0x01,0x10,0xe4,0xff,0x80,0x09,0x90,0x97,0x97,0xe0,0xb4,0x01,0x05,0x7f,0x01, ++0x12,0x4e,0x3b,0x22,0x90,0x00,0x49,0xe0,0x90,0x97,0xb4,0xf0,0xe0,0x54,0x0f,0xf0, ++0xe0,0xff,0x44,0xf0,0x90,0x00,0x49,0xf0,0xef,0x44,0xb0,0xf0,0x22,0xe4,0x90,0x97, ++0x8e,0xf0,0x90,0x97,0x80,0xf0,0x90,0x97,0x89,0xf0,0x90,0x97,0x8f,0xf0,0x22,0xe5, ++0x5e,0xb4,0x01,0x0b,0x12,0x7e,0x61,0xbf,0x01,0x05,0x7f,0x01,0x12,0x7f,0x1b,0x22, ++0x90,0x09,0x28,0xef,0xf0,0xa3,0xf0,0xa3,0xf0,0xa3,0xf0,0xa3,0xf0,0xa3,0xf0,0x22, ++0x90,0x06,0x34,0x74,0xff,0xf0,0xe4,0xa3,0xf0,0xa3,0xf0,0xa3,0xf0,0x22,0x41,0x97, ++0xb1,0x00,0x41,0x97,0x7e,0x80,0x41,0x97,0xb3,0x00,0x00,0x90,0x01,0xca,0xe5,0x61, ++0xf0,0xef,0x60,0x03,0x12,0x7e,0xb4,0x22,0x90,0x97,0x46,0xeb,0xf0,0xa3,0xea,0xf0, ++0xa3,0xe9,0xf0,0x22,0x90,0x97,0xa7,0xeb,0xf0,0xa3,0xea,0xf0,0xa3,0xe9,0xf0,0x22, ++0x90,0x97,0xaa,0xeb,0xf0,0xa3,0xea,0xf0,0xa3,0xe9,0xf0,0x22,0x8f,0x82,0x8e,0x83, ++0xa3,0xa3,0xa3,0xe4,0xf0,0x22,0xe4,0xf5,0x5e,0x7f,0x60,0x7e,0x01,0x02,0x7f,0x4c, ++0x90,0x97,0x97,0xe0,0x90,0x97,0x2d,0xf0,0x22,0x8f,0x1b,0x8c,0x1c,0x8d,0x1d,0x22, ++0x8f,0x1e,0x8c,0x1f,0x8d,0x20,0x22,0x12,0x1c,0xd6,0xf5,0x64,0x22,0x22,0x52,0x09, ++}; ++ ++u32 Rtl8192CUPHY_REG_2TArray[PHY_REG_2TArrayLength] = { ++0x024,0x0011800f, ++0x028,0x00ffdb83, ++0x800,0x80040002, ++0x804,0x00000003, ++0x808,0x0000fc00, ++0x80c,0x0000000a, ++0x810,0x10005388, ++0x814,0x020c3d10, ++0x818,0x02200385, ++0x81c,0x00000000, ++0x820,0x01000100, ++0x824,0x00390004, ++0x828,0x01000100, ++0x82c,0x00390004, ++0x830,0x27272727, ++0x834,0x27272727, ++0x838,0x27272727, ++0x83c,0x27272727, ++0x840,0x00010000, ++0x844,0x00010000, ++0x848,0x27272727, ++0x84c,0x27272727, ++0x850,0x00000000, ++0x854,0x00000000, ++0x858,0x569a569a, ++0x85c,0x0c1b25a4, ++0x860,0x66e60230, ++0x864,0x061f0130, ++0x868,0x27272727, ++0x86c,0x2b2b2b27, ++0x870,0x07000700, ++0x874,0x22184000, ++0x878,0x08080808, ++0x87c,0x00000000, ++0x880,0xc0083070, ++0x884,0x000004d5, ++0x888,0x00000000, ++0x88c,0xcc0000c0, ++0x890,0x00000800, ++0x894,0xfffffffe, ++0x898,0x40302010, ++0x89c,0x00706050, ++0x900,0x00000000, ++0x904,0x00000023, ++0x908,0x00000000, ++0x90c,0x81121313, ++0xa00,0x00d047c8, ++0xa04,0x80ff000c, ++0xa08,0x8c838300, ++0xa0c,0x2e68120f, ++0xa10,0x9500bb78, ++0xa14,0x11144028, ++0xa18,0x00881117, ++0xa1c,0x89140f00, ++0xa20,0x1a1b0000, ++0xa24,0x090e1317, ++0xa28,0x00000204, ++0xa2c,0x00d30000, ++0xa70,0x101fbf00, ++0xa74,0x00000007, ++0xc00,0x48071d40, ++0xc04,0x03a05633, ++0xc08,0x000000e4, ++0xc0c,0x6c6c6c6c, ++0xc10,0x08800000, ++0xc14,0x40000100, ++0xc18,0x08800000, ++0xc1c,0x40000100, ++0xc20,0x00000000, ++0xc24,0x00000000, ++0xc28,0x00000000, ++0xc2c,0x00000000, ++0xc30,0x69e9ac44, ++0xc34,0x469652cf, ++0xc38,0x49795994, ++0xc3c,0x0a97971c, ++0xc40,0x1f7c403f, ++0xc44,0x000100b7, ++0xc48,0xec020107, ++0xc4c,0x007f037f, ++0xc50,0x6954341e, ++0xc54,0x43bc0094, ++0xc58,0x6954341e, ++0xc5c,0x433c0094, ++0xc60,0x00000000, ++0xc64,0x5116848b, ++0xc68,0x47c00bff, ++0xc6c,0x00000036, ++0xc70,0x2c7f000d, ++0xc74,0x0186115b, ++0xc78,0x0000001f, ++0xc7c,0x00b99612, ++0xc80,0x40000100, ++0xc84,0x20f60000, ++0xc88,0x40000100, ++0xc8c,0x20200000, ++0xc90,0x00121820, ++0xc94,0x00000000, ++0xc98,0x00121820, ++0xc9c,0x00007f7f, ++0xca0,0x00000000, ++0xca4,0x00000080, ++0xca8,0x00000000, ++0xcac,0x00000000, ++0xcb0,0x00000000, ++0xcb4,0x00000000, ++0xcb8,0x00000000, ++0xcbc,0x28000000, ++0xcc0,0x00000000, ++0xcc4,0x00000000, ++0xcc8,0x00000000, ++0xccc,0x00000000, ++0xcd0,0x00000000, ++0xcd4,0x00000000, ++0xcd8,0x64b22427, ++0xcdc,0x00766932, ++0xce0,0x00222222, ++0xce4,0x00000000, ++0xce8,0x37644302, ++0xcec,0x2f97d40c, ++0xd00,0x00080740, ++0xd04,0x00020403, ++0xd08,0x0000907f, ++0xd0c,0x20010201, ++0xd10,0xa0633333, ++0xd14,0x3333bc43, ++0xd18,0x7a8f5b6b, ++0xd2c,0xcc979975, ++0xd30,0x00000000, ++0xd34,0x80608000, ++0xd38,0x00000000, ++0xd3c,0x00027293, ++0xd40,0x00000000, ++0xd44,0x00000000, ++0xd48,0x00000000, ++0xd4c,0x00000000, ++0xd50,0x6437140a, ++0xd54,0x00000000, ++0xd58,0x00000000, ++0xd5c,0x30032064, ++0xd60,0x4653de68, ++0xd64,0x04518a3c, ++0xd68,0x00002101, ++0xd6c,0x2a201c16, ++0xd70,0x1812362e, ++0xd74,0x322c2220, ++0xd78,0x000e3c24, ++0xe00,0x2a2a2a2a, ++0xe04,0x2a2a2a2a, ++0xe08,0x03902a2a, ++0xe10,0x2a2a2a2a, ++0xe14,0x2a2a2a2a, ++0xe18,0x2a2a2a2a, ++0xe1c,0x2a2a2a2a, ++0xe28,0x00000000, ++0xe30,0x1000dc1f, ++0xe34,0x10008c1f, ++0xe38,0x02140102, ++0xe3c,0x681604c2, ++0xe40,0x01007c00, ++0xe44,0x01004800, ++0xe48,0xfb000000, ++0xe4c,0x000028d1, ++0xe50,0x1000dc1f, ++0xe54,0x10008c1f, ++0xe58,0x02140102, ++0xe5c,0x28160d05, ++0xe60,0x00000010, ++0xe68,0x001b25a4, ++0xe6c,0x63db25a4, ++0xe70,0x63db25a4, ++0xe74,0x0c1b25a4, ++0xe78,0x0c1b25a4, ++0xe7c,0x0c1b25a4, ++0xe80,0x0c1b25a4, ++0xe84,0x63db25a4, ++0xe88,0x0c1b25a4, ++0xe8c,0x63db25a4, ++0xed0,0x63db25a4, ++0xed4,0x63db25a4, ++0xed8,0x63db25a4, ++0xedc,0x001b25a4, ++0xee0,0x001b25a4, ++0xeec,0x6fdb25a4, ++0xf14,0x00000003, ++0xf4c,0x00000000, ++0xf00,0x00000300, ++}; ++ ++u32 Rtl8192CUPHY_REG_1TArray[PHY_REG_1TArrayLength] = { ++0x024,0x0011800f, ++0x028,0x00ffdb83, ++0x800,0x80040000, ++0x804,0x00000001, ++0x808,0x0000fc00, ++0x80c,0x0000000a, ++0x810,0x10005388, ++0x814,0x020c3d10, ++0x818,0x02200385, ++0x81c,0x00000000, ++0x820,0x01000100, ++0x824,0x00390004, ++0x828,0x00000000, ++0x82c,0x00000000, ++0x830,0x00000000, ++0x834,0x00000000, ++0x838,0x00000000, ++0x83c,0x00000000, ++0x840,0x00010000, ++0x844,0x00000000, ++0x848,0x00000000, ++0x84c,0x00000000, ++0x850,0x00000000, ++0x854,0x00000000, ++0x858,0x569a569a, ++0x85c,0x001b25a4, ++0x860,0x66e60230, ++0x864,0x061f0130, ++0x868,0x00000000, ++0x86c,0x32323200, ++0x870,0x07000700, ++0x874,0x22004000, ++0x878,0x00000808, ++0x87c,0x00000000, ++0x880,0xc0083070, ++0x884,0x000004d5, ++0x888,0x00000000, ++0x88c,0xccc000c0, ++0x890,0x00000800, ++0x894,0xfffffffe, ++0x898,0x40302010, ++0x89c,0x00706050, ++0x900,0x00000000, ++0x904,0x00000023, ++0x908,0x00000000, ++0x90c,0x81121111, ++0xa00,0x00d047c8, ++0xa04,0x80ff000c, ++0xa08,0x8c838300, ++0xa0c,0x2e68120f, ++0xa10,0x9500bb78, ++0xa14,0x11144028, ++0xa18,0x00881117, ++0xa1c,0x89140f00, ++0xa20,0x1a1b0000, ++0xa24,0x090e1317, ++0xa28,0x00000204, ++0xa2c,0x00d30000, ++0xa70,0x101fbf00, ++0xa74,0x00000007, ++0xc00,0x48071d40, ++0xc04,0x03a05611, ++0xc08,0x000000e4, ++0xc0c,0x6c6c6c6c, ++0xc10,0x08800000, ++0xc14,0x40000100, ++0xc18,0x08800000, ++0xc1c,0x40000100, ++0xc20,0x00000000, ++0xc24,0x00000000, ++0xc28,0x00000000, ++0xc2c,0x00000000, ++0xc30,0x69e9ac44, ++0xc34,0x469652cf, ++0xc38,0x49795994, ++0xc3c,0x0a97971c, ++0xc40,0x1f7c403f, ++0xc44,0x000100b7, ++0xc48,0xec020107, ++0xc4c,0x007f037f, ++0xc50,0x6954341e, ++0xc54,0x43bc0094, ++0xc58,0x6954341e, ++0xc5c,0x433c0094, ++0xc60,0x00000000, ++0xc64,0x5116848b, ++0xc68,0x47c00bff, ++0xc6c,0x00000036, ++0xc70,0x2c7f000d, ++0xc74,0x018610db, ++0xc78,0x0000001f, ++0xc7c,0x00b91612, ++0xc80,0x40000100, ++0xc84,0x20f60000, ++0xc88,0x40000100, ++0xc8c,0x20200000, ++0xc90,0x00121820, ++0xc94,0x00000000, ++0xc98,0x00121820, ++0xc9c,0x00007f7f, ++0xca0,0x00000000, ++0xca4,0x00000080, ++0xca8,0x00000000, ++0xcac,0x00000000, ++0xcb0,0x00000000, ++0xcb4,0x00000000, ++0xcb8,0x00000000, ++0xcbc,0x28000000, ++0xcc0,0x00000000, ++0xcc4,0x00000000, ++0xcc8,0x00000000, ++0xccc,0x00000000, ++0xcd0,0x00000000, ++0xcd4,0x00000000, ++0xcd8,0x64b22427, ++0xcdc,0x00766932, ++0xce0,0x00222222, ++0xce4,0x00000000, ++0xce8,0x37644302, ++0xcec,0x2f97d40c, ++0xd00,0x00080740, ++0xd04,0x00020401, ++0xd08,0x0000907f, ++0xd0c,0x20010201, ++0xd10,0xa0633333, ++0xd14,0x3333bc43, ++0xd18,0x7a8f5b6b, ++0xd2c,0xcc979975, ++0xd30,0x00000000, ++0xd34,0x80608000, ++0xd38,0x00000000, ++0xd3c,0x00027293, ++0xd40,0x00000000, ++0xd44,0x00000000, ++0xd48,0x00000000, ++0xd4c,0x00000000, ++0xd50,0x6437140a, ++0xd54,0x00000000, ++0xd58,0x00000000, ++0xd5c,0x30032064, ++0xd60,0x4653de68, ++0xd64,0x04518a3c, ++0xd68,0x00002101, ++0xd6c,0x2a201c16, ++0xd70,0x1812362e, ++0xd74,0x322c2220, ++0xd78,0x000e3c24, ++0xe00,0x2a2a2a2a, ++0xe04,0x2a2a2a2a, ++0xe08,0x03902a2a, ++0xe10,0x2a2a2a2a, ++0xe14,0x2a2a2a2a, ++0xe18,0x2a2a2a2a, ++0xe1c,0x2a2a2a2a, ++0xe28,0x00000000, ++0xe30,0x1000dc1f, ++0xe34,0x10008c1f, ++0xe38,0x02140102, ++0xe3c,0x681604c2, ++0xe40,0x01007c00, ++0xe44,0x01004800, ++0xe48,0xfb000000, ++0xe4c,0x000028d1, ++0xe50,0x1000dc1f, ++0xe54,0x10008c1f, ++0xe58,0x02140102, ++0xe5c,0x28160d05, ++0xe60,0x00000008, ++0xe68,0x001b25a4, ++0xe6c,0x631b25a0, ++0xe70,0x631b25a0, ++0xe74,0x081b25a0, ++0xe78,0x081b25a0, ++0xe7c,0x081b25a0, ++0xe80,0x081b25a0, ++0xe84,0x631b25a0, ++0xe88,0x081b25a0, ++0xe8c,0x631b25a0, ++0xed0,0x631b25a0, ++0xed4,0x631b25a0, ++0xed8,0x631b25a0, ++0xedc,0x001b25a0, ++0xee0,0x001b25a0, ++0xeec,0x6b1b25a0, ++0xf14,0x00000003, ++0xf4c,0x00000000, ++0xf00,0x00000300, ++}; ++ ++u32 Rtl8192CUPHY_ChangeTo_1T1RArray[PHY_ChangeTo_1T1RArrayLength] = { ++0x0, }; ++ ++u32 Rtl8192CUPHY_ChangeTo_1T2RArray[PHY_ChangeTo_1T2RArrayLength] = { ++0x0, }; ++ ++u32 Rtl8192CUPHY_ChangeTo_2T2RArray[PHY_ChangeTo_2T2RArrayLength] = { ++0x0, }; ++ ++u32 Rtl8192CUPHY_REG_Array_PG[PHY_REG_Array_PGLength] = { ++0xe00,0xffffffff,0x07090c0c, ++0xe04,0xffffffff,0x01020405, ++0xe08,0x0000ff00,0x00000000, ++0x86c,0xffffff00,0x00000000, ++0xe10,0xffffffff,0x0b0c0c0e, ++0xe14,0xffffffff,0x01030506, ++0xe18,0xffffffff,0x0b0c0d0e, ++0xe1c,0xffffffff,0x01030509, ++0x830,0xffffffff,0x07090c0c, ++0x834,0xffffffff,0x01020405, ++0x838,0xffffff00,0x00000000, ++0x86c,0x000000ff,0x00000000, ++0x83c,0xffffffff,0x0b0c0d0e, ++0x848,0xffffffff,0x01030509, ++0x84c,0xffffffff,0x0b0c0d0e, ++0x868,0xffffffff,0x01030509, ++0xe00,0xffffffff,0x00000000, ++0xe04,0xffffffff,0x00000000, ++0xe08,0x0000ff00,0x00000000, ++0x86c,0xffffff00,0x00000000, ++0xe10,0xffffffff,0x00000000, ++0xe14,0xffffffff,0x00000000, ++0xe18,0xffffffff,0x00000000, ++0xe1c,0xffffffff,0x00000000, ++0x830,0xffffffff,0x00000000, ++0x834,0xffffffff,0x00000000, ++0x838,0xffffff00,0x00000000, ++0x86c,0x000000ff,0x00000000, ++0x83c,0xffffffff,0x00000000, ++0x848,0xffffffff,0x00000000, ++0x84c,0xffffffff,0x00000000, ++0x868,0xffffffff,0x00000000, ++0xe00,0xffffffff,0x04040404, ++0xe04,0xffffffff,0x00020204, ++0xe08,0x0000ff00,0x00000000, ++0x86c,0xffffff00,0x00000000, ++0xe10,0xffffffff,0x06060606, ++0xe14,0xffffffff,0x00020406, ++0xe18,0xffffffff,0x00000000, ++0xe1c,0xffffffff,0x00000000, ++0x830,0xffffffff,0x04040404, ++0x834,0xffffffff,0x00020204, ++0x838,0xffffff00,0x00000000, ++0x86c,0x000000ff,0x00000000, ++0x83c,0xffffffff,0x06060606, ++0x848,0xffffffff,0x00020406, ++0x84c,0xffffffff,0x00000000, ++0x868,0xffffffff,0x00000000, ++0xe00,0xffffffff,0x00000000, ++0xe04,0xffffffff,0x00000000, ++0xe08,0x0000ff00,0x00000000, ++0x86c,0xffffff00,0x00000000, ++0xe10,0xffffffff,0x00000000, ++0xe14,0xffffffff,0x00000000, ++0xe18,0xffffffff,0x00000000, ++0xe1c,0xffffffff,0x00000000, ++0x830,0xffffffff,0x00000000, ++0x834,0xffffffff,0x00000000, ++0x838,0xffffff00,0x00000000, ++0x86c,0x000000ff,0x00000000, ++0x83c,0xffffffff,0x00000000, ++0x848,0xffffffff,0x00000000, ++0x84c,0xffffffff,0x00000000, ++0x868,0xffffffff,0x00000000, ++0xe00,0xffffffff,0x00000000, ++0xe04,0xffffffff,0x00000000, ++0xe08,0x0000ff00,0x00000000, ++0x86c,0xffffff00,0x00000000, ++0xe10,0xffffffff,0x00000000, ++0xe14,0xffffffff,0x00000000, ++0xe18,0xffffffff,0x00000000, ++0xe1c,0xffffffff,0x00000000, ++0x830,0xffffffff,0x00000000, ++0x834,0xffffffff,0x00000000, ++0x838,0xffffff00,0x00000000, ++0x86c,0x000000ff,0x00000000, ++0x83c,0xffffffff,0x00000000, ++0x848,0xffffffff,0x00000000, ++0x84c,0xffffffff,0x00000000, ++0x868,0xffffffff,0x00000000, ++0xe00,0xffffffff,0x04040404, ++0xe04,0xffffffff,0x00020204, ++0xe08,0x0000ff00,0x00000000, ++0x86c,0xffffff00,0x00000000, ++0xe10,0xffffffff,0x00000000, ++0xe14,0xffffffff,0x00000000, ++0xe18,0xffffffff,0x00000000, ++0xe1c,0xffffffff,0x00000000, ++0x830,0xffffffff,0x04040404, ++0x834,0xffffffff,0x00020204, ++0x838,0xffffff00,0x00000000, ++0x86c,0x000000ff,0x00000000, ++0x83c,0xffffffff,0x00000000, ++0x848,0xffffffff,0x00000000, ++0x84c,0xffffffff,0x00000000, ++0x868,0xffffffff,0x00000000, ++0xe00,0xffffffff,0x00000000, ++0xe04,0xffffffff,0x00000000, ++0xe08,0x0000ff00,0x00000000, ++0x86c,0xffffff00,0x00000000, ++0xe10,0xffffffff,0x00000000, ++0xe14,0xffffffff,0x00000000, ++0xe18,0xffffffff,0x00000000, ++0xe1c,0xffffffff,0x00000000, ++0x830,0xffffffff,0x00000000, ++0x834,0xffffffff,0x00000000, ++0x838,0xffffff00,0x00000000, ++0x86c,0x000000ff,0x00000000, ++0x83c,0xffffffff,0x00000000, ++0x848,0xffffffff,0x00000000, ++0x84c,0xffffffff,0x00000000, ++0x868,0xffffffff,0x00000000, ++}; ++ ++u32 Rtl8192CUPHY_REG_Array_PG_mCard[PHY_REG_Array_PG_mCardLength] = { ++0xe00,0xffffffff,0x0a0c0c0c, ++0xe04,0xffffffff,0x02040608, ++0xe08,0x0000ff00,0x00000000, ++0x86c,0xffffff00,0x00000000, ++0xe10,0xffffffff,0x0a0c0d0e, ++0xe14,0xffffffff,0x02040608, ++0xe18,0xffffffff,0x0a0c0d0e, ++0xe1c,0xffffffff,0x02040608, ++0x830,0xffffffff,0x0a0c0c0c, ++0x834,0xffffffff,0x02040608, ++0x838,0xffffff00,0x00000000, ++0x86c,0x000000ff,0x00000000, ++0x83c,0xffffffff,0x0a0c0d0e, ++0x848,0xffffffff,0x02040608, ++0x84c,0xffffffff,0x0a0c0d0e, ++0x868,0xffffffff,0x02040608, ++0xe00,0xffffffff,0x00000000, ++0xe04,0xffffffff,0x00000000, ++0xe08,0x0000ff00,0x00000000, ++0x86c,0xffffff00,0x00000000, ++0xe10,0xffffffff,0x00000000, ++0xe14,0xffffffff,0x00000000, ++0xe18,0xffffffff,0x00000000, ++0xe1c,0xffffffff,0x00000000, ++0x830,0xffffffff,0x00000000, ++0x834,0xffffffff,0x00000000, ++0x838,0xffffff00,0x00000000, ++0x86c,0x000000ff,0x00000000, ++0x83c,0xffffffff,0x00000000, ++0x848,0xffffffff,0x00000000, ++0x84c,0xffffffff,0x00000000, ++0x868,0xffffffff,0x00000000, ++0xe00,0xffffffff,0x04040404, ++0xe04,0xffffffff,0x00020204, ++0xe08,0x0000ff00,0x00000000, ++0x86c,0xffffff00,0x00000000, ++0xe10,0xffffffff,0x06060606, ++0xe14,0xffffffff,0x00020406, ++0xe18,0xffffffff,0x00000000, ++0xe1c,0xffffffff,0x00000000, ++0x830,0xffffffff,0x04040404, ++0x834,0xffffffff,0x00020204, ++0x838,0xffffff00,0x00000000, ++0x86c,0x000000ff,0x00000000, ++0x83c,0xffffffff,0x06060606, ++0x848,0xffffffff,0x00020406, ++0x84c,0xffffffff,0x00000000, ++0x868,0xffffffff,0x00000000, ++0xe00,0xffffffff,0x00000000, ++0xe04,0xffffffff,0x00000000, ++0xe08,0x0000ff00,0x00000000, ++0x86c,0xffffff00,0x00000000, ++0xe10,0xffffffff,0x00000000, ++0xe14,0xffffffff,0x00000000, ++0xe18,0xffffffff,0x00000000, ++0xe1c,0xffffffff,0x00000000, ++0x830,0xffffffff,0x00000000, ++0x834,0xffffffff,0x00000000, ++0x838,0xffffff00,0x00000000, ++0x86c,0x000000ff,0x00000000, ++0x83c,0xffffffff,0x00000000, ++0x848,0xffffffff,0x00000000, ++0x84c,0xffffffff,0x00000000, ++0x868,0xffffffff,0x00000000, ++0xe00,0xffffffff,0x00000000, ++0xe04,0xffffffff,0x00000000, ++0xe08,0x0000ff00,0x00000000, ++0x86c,0xffffff00,0x00000000, ++0xe10,0xffffffff,0x00000000, ++0xe14,0xffffffff,0x00000000, ++0xe18,0xffffffff,0x00000000, ++0xe1c,0xffffffff,0x00000000, ++0x830,0xffffffff,0x00000000, ++0x834,0xffffffff,0x00000000, ++0x838,0xffffff00,0x00000000, ++0x86c,0x000000ff,0x00000000, ++0x83c,0xffffffff,0x00000000, ++0x848,0xffffffff,0x00000000, ++0x84c,0xffffffff,0x00000000, ++0x868,0xffffffff,0x00000000, ++0xe00,0xffffffff,0x04040404, ++0xe04,0xffffffff,0x00020204, ++0xe08,0x0000ff00,0x00000000, ++0x86c,0xffffff00,0x00000000, ++0xe10,0xffffffff,0x00000000, ++0xe14,0xffffffff,0x00000000, ++0xe18,0xffffffff,0x00000000, ++0xe1c,0xffffffff,0x00000000, ++0x830,0xffffffff,0x04040404, ++0x834,0xffffffff,0x00020204, ++0x838,0xffffff00,0x00000000, ++0x86c,0x000000ff,0x00000000, ++0x83c,0xffffffff,0x00000000, ++0x848,0xffffffff,0x00000000, ++0x84c,0xffffffff,0x00000000, ++0x868,0xffffffff,0x00000000, ++0xe00,0xffffffff,0x00000000, ++0xe04,0xffffffff,0x00000000, ++0xe08,0x0000ff00,0x00000000, ++0x86c,0xffffff00,0x00000000, ++0xe10,0xffffffff,0x00000000, ++0xe14,0xffffffff,0x00000000, ++0xe18,0xffffffff,0x00000000, ++0xe1c,0xffffffff,0x00000000, ++0x830,0xffffffff,0x00000000, ++0x834,0xffffffff,0x00000000, ++0x838,0xffffff00,0x00000000, ++0x86c,0x000000ff,0x00000000, ++0x83c,0xffffffff,0x00000000, ++0x848,0xffffffff,0x00000000, ++0x84c,0xffffffff,0x00000000, ++0x868,0xffffffff,0x00000000, ++}; ++ ++u32 Rtl8192CUPHY_REG_Array_MP[PHY_REG_Array_MPLength] = { ++0xc30,0x69e9ac4a, ++0xc3c,0x0a979718, ++}; ++ ++u32 Rtl8192CUPHY_REG_1T_HPArray[PHY_REG_1T_HPArrayLength] = { ++0x024,0x0011800f, ++0x028,0x00ffdb83, ++0x040,0x000c0004, ++0x800,0x80040000, ++0x804,0x00000001, ++0x808,0x0000fc00, ++0x80c,0x0000000a, ++0x810,0x10005388, ++0x814,0x020c3d10, ++0x818,0x02200385, ++0x81c,0x00000000, ++0x820,0x01000100, ++0x824,0x00390204, ++0x828,0x00000000, ++0x82c,0x00000000, ++0x830,0x00000000, ++0x834,0x00000000, ++0x838,0x00000000, ++0x83c,0x00000000, ++0x840,0x00010000, ++0x844,0x00000000, ++0x848,0x00000000, ++0x84c,0x00000000, ++0x850,0x00000000, ++0x854,0x00000000, ++0x858,0x569a569a, ++0x85c,0x001b25a4, ++0x860,0x66e60230, ++0x864,0x061f0130, ++0x868,0x00000000, ++0x86c,0x20202000, ++0x870,0x03000300, ++0x874,0x22004000, ++0x878,0x00000808, ++0x87c,0x00ffc3f1, ++0x880,0xc0083070, ++0x884,0x000004d5, ++0x888,0x00000000, ++0x88c,0xccc000c0, ++0x890,0x00000800, ++0x894,0xfffffffe, ++0x898,0x40302010, ++0x89c,0x00706050, ++0x900,0x00000000, ++0x904,0x00000023, ++0x908,0x00000000, ++0x90c,0x81121111, ++0xa00,0x00d047c8, ++0xa04,0x80ff000c, ++0xa08,0x8c838300, ++0xa0c,0x2e68120f, ++0xa10,0x9500bb78, ++0xa14,0x11144028, ++0xa18,0x00881117, ++0xa1c,0x89140f00, ++0xa20,0x15160000, ++0xa24,0x070b0f12, ++0xa28,0x00000104, ++0xa2c,0x00d30000, ++0xa70,0x101fbf00, ++0xa74,0x00000007, ++0xc00,0x48071d40, ++0xc04,0x03a05611, ++0xc08,0x000000e4, ++0xc0c,0x6c6c6c6c, ++0xc10,0x08800000, ++0xc14,0x40000100, ++0xc18,0x08800000, ++0xc1c,0x40000100, ++0xc20,0x00000000, ++0xc24,0x00000000, ++0xc28,0x00000000, ++0xc2c,0x00000000, ++0xc30,0x69e9ac44, ++0xc34,0x469652cf, ++0xc38,0x49795994, ++0xc3c,0x0a97971c, ++0xc40,0x1f7c403f, ++0xc44,0x000100b7, ++0xc48,0xec020107, ++0xc4c,0x007f037f, ++0xc50,0x6954342e, ++0xc54,0x43bc0094, ++0xc58,0x6954342f, ++0xc5c,0x433c0094, ++0xc60,0x00000000, ++0xc64,0x5116848b, ++0xc68,0x47c00bff, ++0xc6c,0x00000036, ++0xc70,0x2c46000d, ++0xc74,0x018610db, ++0xc78,0x0000001f, ++0xc7c,0x00b91612, ++0xc80,0x24000090, ++0xc84,0x20f60000, ++0xc88,0x24000090, ++0xc8c,0x20200000, ++0xc90,0x00121820, ++0xc94,0x00000000, ++0xc98,0x00121820, ++0xc9c,0x00007f7f, ++0xca0,0x00000000, ++0xca4,0x00000080, ++0xca8,0x00000000, ++0xcac,0x00000000, ++0xcb0,0x00000000, ++0xcb4,0x00000000, ++0xcb8,0x00000000, ++0xcbc,0x28000000, ++0xcc0,0x00000000, ++0xcc4,0x00000000, ++0xcc8,0x00000000, ++0xccc,0x00000000, ++0xcd0,0x00000000, ++0xcd4,0x00000000, ++0xcd8,0x64b22427, ++0xcdc,0x00766932, ++0xce0,0x00222222, ++0xce4,0x00000000, ++0xce8,0x37644302, ++0xcec,0x2f97d40c, ++0xd00,0x00080740, ++0xd04,0x00020401, ++0xd08,0x0000907f, ++0xd0c,0x20010201, ++0xd10,0xa0633333, ++0xd14,0x3333bc43, ++0xd18,0x7a8f5b6b, ++0xd2c,0xcc979975, ++0xd30,0x00000000, ++0xd34,0x80608000, ++0xd38,0x00000000, ++0xd3c,0x00027293, ++0xd40,0x00000000, ++0xd44,0x00000000, ++0xd48,0x00000000, ++0xd4c,0x00000000, ++0xd50,0x6437140a, ++0xd54,0x00000000, ++0xd58,0x00000000, ++0xd5c,0x30032064, ++0xd60,0x4653de68, ++0xd64,0x04518a3c, ++0xd68,0x00002101, ++0xd6c,0x2a201c16, ++0xd70,0x1812362e, ++0xd74,0x322c2220, ++0xd78,0x000e3c24, ++0xe00,0x24242424, ++0xe04,0x24242424, ++0xe08,0x03902024, ++0xe10,0x24242424, ++0xe14,0x24242424, ++0xe18,0x24242424, ++0xe1c,0x24242424, ++0xe28,0x00000000, ++0xe30,0x1000dc1f, ++0xe34,0x10008c1f, ++0xe38,0x02140102, ++0xe3c,0x681604c2, ++0xe40,0x01007c00, ++0xe44,0x01004800, ++0xe48,0xfb000000, ++0xe4c,0x000028d1, ++0xe50,0x1000dc1f, ++0xe54,0x10008c1f, ++0xe58,0x02140102, ++0xe5c,0x28160d05, ++0xe60,0x00000008, ++0xe68,0x001b25a4, ++0xe6c,0x631b25a0, ++0xe70,0x631b25a0, ++0xe74,0x081b25a0, ++0xe78,0x081b25a0, ++0xe7c,0x081b25a0, ++0xe80,0x081b25a0, ++0xe84,0x631b25a0, ++0xe88,0x081b25a0, ++0xe8c,0x631b25a0, ++0xed0,0x631b25a0, ++0xed4,0x631b25a0, ++0xed8,0x631b25a0, ++0xedc,0x001b25a0, ++0xee0,0x001b25a0, ++0xeec,0x6b1b25a0, ++0xee8,0x31555448, ++0xf14,0x00000003, ++0xf4c,0x00000000, ++0xf00,0x00000300, ++}; ++ ++u32 Rtl8192CUPHY_REG_1T_mCardArray[PHY_REG_1T_mCardArrayLength] = { ++0x024,0x0011800d, ++0x028,0x00ffdb83, ++0x800,0x80040000, ++0x804,0x00000001, ++0x808,0x0000fc00, ++0x80c,0x0000000a, ++0x810,0x10005388, ++0x814,0x020c3d10, ++0x818,0x02200385, ++0x81c,0x00000000, ++0x820,0x01000100, ++0x824,0x00390004, ++0x828,0x00000000, ++0x82c,0x00000000, ++0x830,0x00000000, ++0x834,0x00000000, ++0x838,0x00000000, ++0x83c,0x00000000, ++0x840,0x00010000, ++0x844,0x00000000, ++0x848,0x00000000, ++0x84c,0x00000000, ++0x850,0x00000000, ++0x854,0x00000000, ++0x858,0x569a569a, ++0x85c,0x001b25a4, ++0x860,0x66e60230, ++0x864,0x061f0130, ++0x868,0x00000000, ++0x86c,0x32323200, ++0x870,0x07000700, ++0x874,0x22004000, ++0x878,0x00000808, ++0x87c,0x00000000, ++0x880,0xc0083070, ++0x884,0x000004d5, ++0x888,0x00000000, ++0x88c,0xccc000c0, ++0x890,0x00000800, ++0x894,0xfffffffe, ++0x898,0x40302010, ++0x89c,0x00706050, ++0x900,0x00000000, ++0x904,0x00000023, ++0x908,0x00000000, ++0x90c,0x81121111, ++0xa00,0x00d047c8, ++0xa04,0x80ff000c, ++0xa08,0x8c838300, ++0xa0c,0x2e68120f, ++0xa10,0x9500bb78, ++0xa14,0x11144028, ++0xa18,0x00881117, ++0xa1c,0x89140f00, ++0xa20,0x1a1b0000, ++0xa24,0x090e1317, ++0xa28,0x00000204, ++0xa2c,0x00d30000, ++0xa70,0x101fbf00, ++0xa74,0x00000007, ++0xc00,0x48071d40, ++0xc04,0x03a05611, ++0xc08,0x000000e4, ++0xc0c,0x6c6c6c6c, ++0xc10,0x08800000, ++0xc14,0x40000100, ++0xc18,0x08800000, ++0xc1c,0x40000100, ++0xc20,0x00000000, ++0xc24,0x00000000, ++0xc28,0x00000000, ++0xc2c,0x00000000, ++0xc30,0x69e9ac44, ++0xc34,0x469652cf, ++0xc38,0x49795994, ++0xc3c,0x0a97971c, ++0xc40,0x1f7c403f, ++0xc44,0x000100b7, ++0xc48,0xec020107, ++0xc4c,0x007f037f, ++0xc50,0x6954341e, ++0xc54,0x43bc0094, ++0xc58,0x6954341e, ++0xc5c,0x433c0094, ++0xc60,0x00000000, ++0xc64,0x5116848b, ++0xc68,0x47c00bff, ++0xc6c,0x00000036, ++0xc70,0x2c7f000d, ++0xc74,0x018610db, ++0xc78,0x0000001f, ++0xc7c,0x00b91612, ++0xc80,0x40000100, ++0xc84,0x20f60000, ++0xc88,0x40000100, ++0xc8c,0x20200000, ++0xc90,0x00121820, ++0xc94,0x00000000, ++0xc98,0x00121820, ++0xc9c,0x00007f7f, ++0xca0,0x00000000, ++0xca4,0x00000080, ++0xca8,0x00000000, ++0xcac,0x00000000, ++0xcb0,0x00000000, ++0xcb4,0x00000000, ++0xcb8,0x00000000, ++0xcbc,0x28000000, ++0xcc0,0x00000000, ++0xcc4,0x00000000, ++0xcc8,0x00000000, ++0xccc,0x00000000, ++0xcd0,0x00000000, ++0xcd4,0x00000000, ++0xcd8,0x64b22427, ++0xcdc,0x00766932, ++0xce0,0x00222222, ++0xce4,0x00000000, ++0xce8,0x37644302, ++0xcec,0x2f97d40c, ++0xd00,0x00080740, ++0xd04,0x00020401, ++0xd08,0x0000907f, ++0xd0c,0x20010201, ++0xd10,0xa0633333, ++0xd14,0x3333bc43, ++0xd18,0x7a8f5b6b, ++0xd2c,0xcc979975, ++0xd30,0x00000000, ++0xd34,0x80608000, ++0xd38,0x00000000, ++0xd3c,0x00027293, ++0xd40,0x00000000, ++0xd44,0x00000000, ++0xd48,0x00000000, ++0xd4c,0x00000000, ++0xd50,0x6437140a, ++0xd54,0x00000000, ++0xd58,0x00000000, ++0xd5c,0x30032064, ++0xd60,0x4653de68, ++0xd64,0x04518a3c, ++0xd68,0x00002101, ++0xd6c,0x2a201c16, ++0xd70,0x1812362e, ++0xd74,0x322c2220, ++0xd78,0x000e3c24, ++0xe00,0x2a2a2a2a, ++0xe04,0x2a2a2a2a, ++0xe08,0x03902a2a, ++0xe10,0x2a2a2a2a, ++0xe14,0x2a2a2a2a, ++0xe18,0x2a2a2a2a, ++0xe1c,0x2a2a2a2a, ++0xe28,0x00000000, ++0xe30,0x1000dc1f, ++0xe34,0x10008c1f, ++0xe38,0x02140102, ++0xe3c,0x681604c2, ++0xe40,0x01007c00, ++0xe44,0x01004800, ++0xe48,0xfb000000, ++0xe4c,0x000028d1, ++0xe50,0x1000dc1f, ++0xe54,0x10008c1f, ++0xe58,0x02140102, ++0xe5c,0x28160d05, ++0xe60,0x00000008, ++0xe68,0x001b25a4, ++0xe6c,0x631b25a0, ++0xe70,0x631b25a0, ++0xe74,0x081b25a0, ++0xe78,0x081b25a0, ++0xe7c,0x081b25a0, ++0xe80,0x081b25a0, ++0xe84,0x631b25a0, ++0xe88,0x081b25a0, ++0xe8c,0x631b25a0, ++0xed0,0x631b25a0, ++0xed4,0x631b25a0, ++0xed8,0x631b25a0, ++0xedc,0x001b25a0, ++0xee0,0x001b25a0, ++0xeec,0x6b1b25a0, ++0xf14,0x00000003, ++0xf4c,0x00000000, ++0xf00,0x00000300, ++}; ++ ++u32 Rtl8192CUPHY_REG_2T_mCardArray[PHY_REG_2T_mCardArrayLength] = { ++0x024,0x0011800d, ++0x028,0x00ffdb83, ++0x800,0x80040002, ++0x804,0x00000003, ++0x808,0x0000fc00, ++0x80c,0x0000000a, ++0x810,0x10005388, ++0x814,0x020c3d10, ++0x818,0x02200385, ++0x81c,0x00000000, ++0x820,0x01000100, ++0x824,0x00390004, ++0x828,0x01000100, ++0x82c,0x00390004, ++0x830,0x27272727, ++0x834,0x27272727, ++0x838,0x27272727, ++0x83c,0x27272727, ++0x840,0x00010000, ++0x844,0x00010000, ++0x848,0x27272727, ++0x84c,0x27272727, ++0x850,0x00000000, ++0x854,0x00000000, ++0x858,0x569a569a, ++0x85c,0x0c1b25a4, ++0x860,0x66e60230, ++0x864,0x061f0130, ++0x868,0x27272727, ++0x86c,0x2b2b2b27, ++0x870,0x07000700, ++0x874,0x22184000, ++0x878,0x08080808, ++0x87c,0x00000000, ++0x880,0xc0083070, ++0x884,0x000004d5, ++0x888,0x00000000, ++0x88c,0xcc0000c0, ++0x890,0x00000800, ++0x894,0xfffffffe, ++0x898,0x40302010, ++0x89c,0x00706050, ++0x900,0x00000000, ++0x904,0x00000023, ++0x908,0x00000000, ++0x90c,0x81121313, ++0xa00,0x00d047c8, ++0xa04,0x80ff000c, ++0xa08,0x8c838300, ++0xa0c,0x2e68120f, ++0xa10,0x9500bb78, ++0xa14,0x11144028, ++0xa18,0x00881117, ++0xa1c,0x89140f00, ++0xa20,0x1a1b0000, ++0xa24,0x090e1317, ++0xa28,0x00000204, ++0xa2c,0x00d30000, ++0xa70,0x101fbf00, ++0xa74,0x00000007, ++0xc00,0x48071d40, ++0xc04,0x03a05633, ++0xc08,0x000000e4, ++0xc0c,0x6c6c6c6c, ++0xc10,0x08800000, ++0xc14,0x40000100, ++0xc18,0x08800000, ++0xc1c,0x40000100, ++0xc20,0x00000000, ++0xc24,0x00000000, ++0xc28,0x00000000, ++0xc2c,0x00000000, ++0xc30,0x69e9ac44, ++0xc34,0x469652cf, ++0xc38,0x49795994, ++0xc3c,0x0a97971c, ++0xc40,0x1f7c403f, ++0xc44,0x000100b7, ++0xc48,0xec020107, ++0xc4c,0x007f037f, ++0xc50,0x6954341e, ++0xc54,0x43bc0094, ++0xc58,0x6954341e, ++0xc5c,0x433c0094, ++0xc60,0x00000000, ++0xc64,0x5116848b, ++0xc68,0x47c00bff, ++0xc6c,0x00000036, ++0xc70,0x2c7f000d, ++0xc74,0x018610db, ++0xc78,0x0000001f, ++0xc7c,0x00b91612, ++0xc80,0x40000100, ++0xc84,0x20f60000, ++0xc88,0x40000100, ++0xc8c,0x20200000, ++0xc90,0x00121820, ++0xc94,0x00000000, ++0xc98,0x00121820, ++0xc9c,0x00007f7f, ++0xca0,0x00000000, ++0xca4,0x00000080, ++0xca8,0x00000000, ++0xcac,0x00000000, ++0xcb0,0x00000000, ++0xcb4,0x00000000, ++0xcb8,0x00000000, ++0xcbc,0x28000000, ++0xcc0,0x00000000, ++0xcc4,0x00000000, ++0xcc8,0x00000000, ++0xccc,0x00000000, ++0xcd0,0x00000000, ++0xcd4,0x00000000, ++0xcd8,0x64b22427, ++0xcdc,0x00766932, ++0xce0,0x00222222, ++0xce4,0x00000000, ++0xce8,0x37644302, ++0xcec,0x2f97d40c, ++0xd00,0x00080740, ++0xd04,0x00020403, ++0xd08,0x0000907f, ++0xd0c,0x20010201, ++0xd10,0xa0633333, ++0xd14,0x3333bc43, ++0xd18,0x7a8f5b6b, ++0xd2c,0xcc979975, ++0xd30,0x00000000, ++0xd34,0x80608000, ++0xd38,0x00000000, ++0xd3c,0x00027293, ++0xd40,0x00000000, ++0xd44,0x00000000, ++0xd48,0x00000000, ++0xd4c,0x00000000, ++0xd50,0x6437140a, ++0xd54,0x00000000, ++0xd58,0x00000000, ++0xd5c,0x30032064, ++0xd60,0x4653de68, ++0xd64,0x04518a3c, ++0xd68,0x00002101, ++0xd6c,0x2a201c16, ++0xd70,0x1812362e, ++0xd74,0x322c2220, ++0xd78,0x000e3c24, ++0xe00,0x2a2a2a2a, ++0xe04,0x2a2a2a2a, ++0xe08,0x03902a2a, ++0xe10,0x2a2a2a2a, ++0xe14,0x2a2a2a2a, ++0xe18,0x2a2a2a2a, ++0xe1c,0x2a2a2a2a, ++0xe28,0x00000000, ++0xe30,0x1000dc1f, ++0xe34,0x10008c1f, ++0xe38,0x02140102, ++0xe3c,0x681604c2, ++0xe40,0x01007c00, ++0xe44,0x01004800, ++0xe48,0xfb000000, ++0xe4c,0x000028d1, ++0xe50,0x1000dc1f, ++0xe54,0x10008c1f, ++0xe58,0x02140102, ++0xe5c,0x28160d05, ++0xe60,0x00000010, ++0xe68,0x001b25a4, ++0xe6c,0x63db25a4, ++0xe70,0x63db25a4, ++0xe74,0x0c1b25a4, ++0xe78,0x0c1b25a4, ++0xe7c,0x0c1b25a4, ++0xe80,0x0c1b25a4, ++0xe84,0x63db25a4, ++0xe88,0x0c1b25a4, ++0xe8c,0x63db25a4, ++0xed0,0x63db25a4, ++0xed4,0x63db25a4, ++0xed8,0x63db25a4, ++0xedc,0x001b25a4, ++0xee0,0x001b25a4, ++0xeec,0x6fdb25a4, ++0xf14,0x00000003, ++0xf4c,0x00000000, ++0xf00,0x00000300, ++}; ++ ++u32 Rtl8192CUPHY_REG_Array_PG_HP[PHY_REG_Array_PG_HPLength] = { ++0xe00,0xffffffff,0x06080808, ++0xe04,0xffffffff,0x00040406, ++0xe08,0x0000ff00,0x00000000, ++0x86c,0xffffff00,0x00000000, ++0xe10,0xffffffff,0x04060608, ++0xe14,0xffffffff,0x00020204, ++0xe18,0xffffffff,0x04060608, ++0xe1c,0xffffffff,0x00020204, ++0x830,0xffffffff,0x06080808, ++0x834,0xffffffff,0x00040406, ++0x838,0xffffff00,0x00000000, ++0x86c,0x000000ff,0x00000000, ++0x83c,0xffffffff,0x04060608, ++0x848,0xffffffff,0x00020204, ++0x84c,0xffffffff,0x04060608, ++0x868,0xffffffff,0x00020204, ++0xe00,0xffffffff,0x00000000, ++0xe04,0xffffffff,0x00000000, ++0xe08,0x0000ff00,0x00000000, ++0x86c,0xffffff00,0x00000000, ++0xe10,0xffffffff,0x00000000, ++0xe14,0xffffffff,0x00000000, ++0xe18,0xffffffff,0x00000000, ++0xe1c,0xffffffff,0x00000000, ++0x830,0xffffffff,0x00000000, ++0x834,0xffffffff,0x00000000, ++0x838,0xffffff00,0x00000000, ++0x86c,0x000000ff,0x00000000, ++0x83c,0xffffffff,0x00000000, ++0x848,0xffffffff,0x00000000, ++0x84c,0xffffffff,0x00000000, ++0x868,0xffffffff,0x00000000, ++0xe00,0xffffffff,0x00000000, ++0xe04,0xffffffff,0x00000000, ++0xe08,0x0000ff00,0x00000000, ++0x86c,0xffffff00,0x00000000, ++0xe10,0xffffffff,0x00000000, ++0xe14,0xffffffff,0x00000000, ++0xe18,0xffffffff,0x00000000, ++0xe1c,0xffffffff,0x00000000, ++0x830,0xffffffff,0x00000000, ++0x834,0xffffffff,0x00000000, ++0x838,0xffffff00,0x00000000, ++0x86c,0x000000ff,0x00000000, ++0x83c,0xffffffff,0x00000000, ++0x848,0xffffffff,0x00000000, ++0x84c,0xffffffff,0x00000000, ++0x868,0xffffffff,0x00000000, ++0xe00,0xffffffff,0x00000000, ++0xe04,0xffffffff,0x00000000, ++0xe08,0x0000ff00,0x00000000, ++0x86c,0xffffff00,0x00000000, ++0xe10,0xffffffff,0x00000000, ++0xe14,0xffffffff,0x00000000, ++0xe18,0xffffffff,0x00000000, ++0xe1c,0xffffffff,0x00000000, ++0x830,0xffffffff,0x00000000, ++0x834,0xffffffff,0x00000000, ++0x838,0xffffff00,0x00000000, ++0x86c,0x000000ff,0x00000000, ++0x83c,0xffffffff,0x00000000, ++0x848,0xffffffff,0x00000000, ++0x84c,0xffffffff,0x00000000, ++0x868,0xffffffff,0x00000000, ++0xe00,0xffffffff,0x00000000, ++0xe04,0xffffffff,0x00000000, ++0xe08,0x0000ff00,0x00000000, ++0x86c,0xffffff00,0x00000000, ++0xe10,0xffffffff,0x00000000, ++0xe14,0xffffffff,0x00000000, ++0xe18,0xffffffff,0x00000000, ++0xe1c,0xffffffff,0x00000000, ++0x830,0xffffffff,0x00000000, ++0x834,0xffffffff,0x00000000, ++0x838,0xffffff00,0x00000000, ++0x86c,0x000000ff,0x00000000, ++0x83c,0xffffffff,0x00000000, ++0x848,0xffffffff,0x00000000, ++0x84c,0xffffffff,0x00000000, ++0x868,0xffffffff,0x00000000, ++0xe00,0xffffffff,0x00000000, ++0xe04,0xffffffff,0x00000000, ++0xe08,0x0000ff00,0x00000000, ++0x86c,0xffffff00,0x00000000, ++0xe10,0xffffffff,0x00000000, ++0xe14,0xffffffff,0x00000000, ++0xe18,0xffffffff,0x00000000, ++0xe1c,0xffffffff,0x00000000, ++0x830,0xffffffff,0x00000000, ++0x834,0xffffffff,0x00000000, ++0x838,0xffffff00,0x00000000, ++0x86c,0x000000ff,0x00000000, ++0x83c,0xffffffff,0x00000000, ++0x848,0xffffffff,0x00000000, ++0x84c,0xffffffff,0x00000000, ++0x868,0xffffffff,0x00000000, ++0xe00,0xffffffff,0x00000000, ++0xe04,0xffffffff,0x00000000, ++0xe08,0x0000ff00,0x00000000, ++0x86c,0xffffff00,0x00000000, ++0xe10,0xffffffff,0x00000000, ++0xe14,0xffffffff,0x00000000, ++0xe18,0xffffffff,0x00000000, ++0xe1c,0xffffffff,0x00000000, ++0x830,0xffffffff,0x00000000, ++0x834,0xffffffff,0x00000000, ++0x838,0xffffff00,0x00000000, ++0x86c,0x000000ff,0x00000000, ++0x83c,0xffffffff,0x00000000, ++0x848,0xffffffff,0x00000000, ++0x84c,0xffffffff,0x00000000, ++0x868,0xffffffff,0x00000000, ++}; ++ ++u32 Rtl8192CURadioA_2TArray[RadioA_2TArrayLength] = { ++0x000,0x00030159, ++0x001,0x00031284, ++0x002,0x00098000, ++0x003,0x00018c63, ++0x004,0x000210e7, ++0x009,0x0002044f, ++0x00a,0x0001adb1, ++0x00b,0x00054867, ++0x00c,0x0008992e, ++0x00d,0x0000e52c, ++0x00e,0x00039ce7, ++0x00f,0x00000451, ++0x019,0x00000000, ++0x01a,0x00010255, ++0x01b,0x00060a00, ++0x01c,0x000fc378, ++0x01d,0x000a1250, ++0x01e,0x0004445f, ++0x01f,0x00080001, ++0x020,0x0000b614, ++0x021,0x0006c000, ++0x022,0x00000000, ++0x023,0x00001558, ++0x024,0x00000060, ++0x025,0x00000483, ++0x026,0x0004f000, ++0x027,0x000ec7d9, ++0x028,0x000577c0, ++0x029,0x00004783, ++0x02a,0x00000001, ++0x02b,0x00021334, ++0x02a,0x00000000, ++0x02b,0x00000054, ++0x02a,0x00000001, ++0x02b,0x00000808, ++0x02b,0x00053333, ++0x02c,0x0000000c, ++0x02a,0x00000002, ++0x02b,0x00000808, ++0x02b,0x0005b333, ++0x02c,0x0000000d, ++0x02a,0x00000003, ++0x02b,0x00000808, ++0x02b,0x00063333, ++0x02c,0x0000000d, ++0x02a,0x00000004, ++0x02b,0x00000808, ++0x02b,0x0006b333, ++0x02c,0x0000000d, ++0x02a,0x00000005, ++0x02b,0x00000808, ++0x02b,0x00073333, ++0x02c,0x0000000d, ++0x02a,0x00000006, ++0x02b,0x00000709, ++0x02b,0x0005b333, ++0x02c,0x0000000d, ++0x02a,0x00000007, ++0x02b,0x00000709, ++0x02b,0x00063333, ++0x02c,0x0000000d, ++0x02a,0x00000008, ++0x02b,0x0000060a, ++0x02b,0x0004b333, ++0x02c,0x0000000d, ++0x02a,0x00000009, ++0x02b,0x0000060a, ++0x02b,0x00053333, ++0x02c,0x0000000d, ++0x02a,0x0000000a, ++0x02b,0x0000060a, ++0x02b,0x0005b333, ++0x02c,0x0000000d, ++0x02a,0x0000000b, ++0x02b,0x0000060a, ++0x02b,0x00063333, ++0x02c,0x0000000d, ++0x02a,0x0000000c, ++0x02b,0x0000060a, ++0x02b,0x0006b333, ++0x02c,0x0000000d, ++0x02a,0x0000000d, ++0x02b,0x0000060a, ++0x02b,0x00073333, ++0x02c,0x0000000d, ++0x02a,0x0000000e, ++0x02b,0x0000050b, ++0x02b,0x00066666, ++0x02c,0x0000001a, ++0x02a,0x000e0000, ++0x010,0x0004000f, ++0x011,0x000e31fc, ++0x010,0x0006000f, ++0x011,0x000ff9f8, ++0x010,0x0002000f, ++0x011,0x000203f9, ++0x010,0x0003000f, ++0x011,0x000ff500, ++0x010,0x00000000, ++0x011,0x00000000, ++0x010,0x0008000f, ++0x011,0x0003f100, ++0x010,0x0009000f, ++0x011,0x00023100, ++0x012,0x00032000, ++0x012,0x00071000, ++0x012,0x000b0000, ++0x012,0x000fc000, ++0x013,0x000287b3, ++0x013,0x000244b7, ++0x013,0x000204ab, ++0x013,0x0001c49f, ++0x013,0x00018493, ++0x013,0x0001429b, ++0x013,0x00010299, ++0x013,0x0000c29c, ++0x013,0x000081a0, ++0x013,0x000040ac, ++0x013,0x00000020, ++0x014,0x0001944c, ++0x014,0x00059444, ++0x014,0x0009944c, ++0x014,0x000d9444, ++0x015,0x0000f424, ++0x015,0x0004f424, ++0x015,0x0008f424, ++0x015,0x000cf424, ++0x016,0x000e0330, ++0x016,0x000a0330, ++0x016,0x00060330, ++0x016,0x00020330, ++0x000,0x00010159, ++0x018,0x0000f401, ++0x0fe,0x00000000, ++0x0fe,0x00000000, ++0x01f,0x00080003, ++0x0fe,0x00000000, ++0x0fe,0x00000000, ++0x01e,0x00044457, ++0x01f,0x00080000, ++0x000,0x00030159, ++}; ++ ++u32 Rtl8192CURadioB_2TArray[RadioB_2TArrayLength] = { ++0x000,0x00030159, ++0x001,0x00031284, ++0x002,0x00098000, ++0x003,0x00018c63, ++0x004,0x000210e7, ++0x009,0x0002044f, ++0x00a,0x0001adb1, ++0x00b,0x00054867, ++0x00c,0x0008992e, ++0x00d,0x0000e52c, ++0x00e,0x00039ce7, ++0x00f,0x00000451, ++0x012,0x00032000, ++0x012,0x00071000, ++0x012,0x000b0000, ++0x012,0x000fc000, ++0x013,0x000287af, ++0x013,0x000244b7, ++0x013,0x000204ab, ++0x013,0x0001c49f, ++0x013,0x00018493, ++0x013,0x00014297, ++0x013,0x00010295, ++0x013,0x0000c298, ++0x013,0x0000819c, ++0x013,0x000040a8, ++0x013,0x0000001c, ++0x014,0x0001944c, ++0x014,0x00059444, ++0x014,0x0009944c, ++0x014,0x000d9444, ++0x015,0x0000f424, ++0x015,0x0004f424, ++0x015,0x0008f424, ++0x015,0x000cf424, ++0x016,0x000e0330, ++0x016,0x000a0330, ++0x016,0x00060330, ++0x016,0x00020330, ++}; ++ ++u32 Rtl8192CURadioA_1TArray[RadioA_1TArrayLength] = { ++0x000,0x00030159, ++0x001,0x00031284, ++0x002,0x00098000, ++0x003,0x00018c63, ++0x004,0x000210e7, ++0x009,0x0002044f, ++0x00a,0x0001adb1, ++0x00b,0x00054867, ++0x00c,0x0008992e, ++0x00d,0x0000e52c, ++0x00e,0x00039ce7, ++0x00f,0x00000451, ++0x019,0x00000000, ++0x01a,0x00010255, ++0x01b,0x00060a00, ++0x01c,0x000fc378, ++0x01d,0x000a1250, ++0x01e,0x0004445f, ++0x01f,0x00080001, ++0x020,0x0000b614, ++0x021,0x0006c000, ++0x022,0x00000000, ++0x023,0x00001558, ++0x024,0x00000060, ++0x025,0x00000483, ++0x026,0x0004f000, ++0x027,0x000ec7d9, ++0x028,0x000577c0, ++0x029,0x00004783, ++0x02a,0x00000001, ++0x02b,0x00021334, ++0x02a,0x00000000, ++0x02b,0x00000054, ++0x02a,0x00000001, ++0x02b,0x00000808, ++0x02b,0x00053333, ++0x02c,0x0000000c, ++0x02a,0x00000002, ++0x02b,0x00000808, ++0x02b,0x0005b333, ++0x02c,0x0000000d, ++0x02a,0x00000003, ++0x02b,0x00000808, ++0x02b,0x00063333, ++0x02c,0x0000000d, ++0x02a,0x00000004, ++0x02b,0x00000808, ++0x02b,0x0006b333, ++0x02c,0x0000000d, ++0x02a,0x00000005, ++0x02b,0x00000808, ++0x02b,0x00073333, ++0x02c,0x0000000d, ++0x02a,0x00000006, ++0x02b,0x00000709, ++0x02b,0x0005b333, ++0x02c,0x0000000d, ++0x02a,0x00000007, ++0x02b,0x00000709, ++0x02b,0x00063333, ++0x02c,0x0000000d, ++0x02a,0x00000008, ++0x02b,0x0000060a, ++0x02b,0x0004b333, ++0x02c,0x0000000d, ++0x02a,0x00000009, ++0x02b,0x0000060a, ++0x02b,0x00053333, ++0x02c,0x0000000d, ++0x02a,0x0000000a, ++0x02b,0x0000060a, ++0x02b,0x0005b333, ++0x02c,0x0000000d, ++0x02a,0x0000000b, ++0x02b,0x0000060a, ++0x02b,0x00063333, ++0x02c,0x0000000d, ++0x02a,0x0000000c, ++0x02b,0x0000060a, ++0x02b,0x0006b333, ++0x02c,0x0000000d, ++0x02a,0x0000000d, ++0x02b,0x0000060a, ++0x02b,0x00073333, ++0x02c,0x0000000d, ++0x02a,0x0000000e, ++0x02b,0x0000050b, ++0x02b,0x00066666, ++0x02c,0x0000001a, ++0x02a,0x000e0000, ++0x010,0x0004000f, ++0x011,0x000e31fc, ++0x010,0x0006000f, ++0x011,0x000ff9f8, ++0x010,0x0002000f, ++0x011,0x000203f9, ++0x010,0x0003000f, ++0x011,0x000ff500, ++0x010,0x00000000, ++0x011,0x00000000, ++0x010,0x0008000f, ++0x011,0x0003f100, ++0x010,0x0009000f, ++0x011,0x00023100, ++0x012,0x00032000, ++0x012,0x00071000, ++0x012,0x000b0000, ++0x012,0x000fc000, ++0x013,0x000287b3, ++0x013,0x000244b7, ++0x013,0x000204ab, ++0x013,0x0001c49f, ++0x013,0x00018493, ++0x013,0x0001429b, ++0x013,0x00010299, ++0x013,0x0000c29c, ++0x013,0x000081a0, ++0x013,0x000040ac, ++0x013,0x00000020, ++0x014,0x0001944c, ++0x014,0x00059444, ++0x014,0x0009944c, ++0x014,0x000d9444, ++0x015,0x0000f405, ++0x015,0x0004f405, ++0x015,0x0008f405, ++0x015,0x000cf405, ++0x016,0x000e0330, ++0x016,0x000a0330, ++0x016,0x00060330, ++0x016,0x00020330, ++0x000,0x00010159, ++0x018,0x0000f401, ++0x0fe,0x00000000, ++0x0fe,0x00000000, ++0x01f,0x00080003, ++0x0fe,0x00000000, ++0x0fe,0x00000000, ++0x01e,0x00044457, ++0x01f,0x00080000, ++0x000,0x00030159, ++}; ++ ++u32 Rtl8192CURadioB_1TArray[RadioB_1TArrayLength] = { ++0x0, }; ++ ++ ++u32 Rtl8192CURadioA_1T_mCardArray[RadioA_1T_mCardArrayLength] = { ++0x000,0x00030159, ++0x001,0x00031284, ++0x002,0x00098000, ++0x003,0x00018c63, ++0x004,0x000210e7, ++0x009,0x0002044f, ++0x00a,0x0001adb1, ++0x00b,0x00054867, ++0x00c,0x0008992e, ++0x00d,0x0000e52c, ++0x00e,0x00039ce7, ++0x00f,0x00000451, ++0x019,0x00000000, ++0x01a,0x00010255, ++0x01b,0x00060a00, ++0x01c,0x000fc378, ++0x01d,0x000a1250, ++0x01e,0x0004445f, ++0x01f,0x00080001, ++0x020,0x0000b614, ++0x021,0x0006c000, ++0x022,0x00000000, ++0x023,0x00001558, ++0x024,0x00000060, ++0x025,0x00000483, ++0x026,0x0004f200, ++0x027,0x000ec7d9, ++0x028,0x000577c0, ++0x029,0x00004783, ++0x02a,0x00000001, ++0x02b,0x00021334, ++0x02a,0x00000000, ++0x02b,0x00000054, ++0x02a,0x00000001, ++0x02b,0x00000808, ++0x02b,0x00053333, ++0x02c,0x0000000c, ++0x02a,0x00000002, ++0x02b,0x00000808, ++0x02b,0x0005b333, ++0x02c,0x0000000d, ++0x02a,0x00000003, ++0x02b,0x00000808, ++0x02b,0x00063333, ++0x02c,0x0000000d, ++0x02a,0x00000004, ++0x02b,0x00000808, ++0x02b,0x0006b333, ++0x02c,0x0000000d, ++0x02a,0x00000005, ++0x02b,0x00000808, ++0x02b,0x00073333, ++0x02c,0x0000000d, ++0x02a,0x00000006, ++0x02b,0x00000709, ++0x02b,0x0005b333, ++0x02c,0x0000000d, ++0x02a,0x00000007, ++0x02b,0x00000709, ++0x02b,0x00063333, ++0x02c,0x0000000d, ++0x02a,0x00000008, ++0x02b,0x0000060a, ++0x02b,0x0004b333, ++0x02c,0x0000000d, ++0x02a,0x00000009, ++0x02b,0x0000060a, ++0x02b,0x00053333, ++0x02c,0x0000000d, ++0x02a,0x0000000a, ++0x02b,0x0000060a, ++0x02b,0x0005b333, ++0x02c,0x0000000d, ++0x02a,0x0000000b, ++0x02b,0x0000060a, ++0x02b,0x00063333, ++0x02c,0x0000000d, ++0x02a,0x0000000c, ++0x02b,0x0000060a, ++0x02b,0x0006b333, ++0x02c,0x0000000d, ++0x02a,0x0000000d, ++0x02b,0x0000060a, ++0x02b,0x00073333, ++0x02c,0x0000000d, ++0x02a,0x0000000e, ++0x02b,0x0000050b, ++0x02b,0x00066666, ++0x02c,0x0000001a, ++0x02a,0x000e0000, ++0x010,0x0004000f, ++0x011,0x000e31fc, ++0x010,0x0006000f, ++0x011,0x000ff9f8, ++0x010,0x0002000f, ++0x011,0x000203f9, ++0x010,0x0003000f, ++0x011,0x000ff500, ++0x010,0x00000000, ++0x011,0x00000000, ++0x010,0x0008000f, ++0x011,0x0003f100, ++0x010,0x0009000f, ++0x011,0x00023100, ++0x012,0x00032000, ++0x012,0x00071000, ++0x012,0x000b0000, ++0x012,0x000fc000, ++0x013,0x000287b3, ++0x013,0x000244b7, ++0x013,0x000204ab, ++0x013,0x0001c49f, ++0x013,0x00018493, ++0x013,0x0001429b, ++0x013,0x00010299, ++0x013,0x0000c29c, ++0x013,0x000081a0, ++0x013,0x000040ac, ++0x013,0x00000020, ++0x014,0x0001944c, ++0x014,0x00059444, ++0x014,0x0009944c, ++0x014,0x000d9444, ++0x015,0x0000f424, ++0x015,0x0004f424, ++0x015,0x0008f424, ++0x015,0x000cf424, ++0x016,0x000e0330, ++0x016,0x000a0330, ++0x016,0x00060330, ++0x016,0x00020330, ++0x000,0x00010159, ++0x018,0x0000f401, ++0x0fe,0x00000000, ++0x0fe,0x00000000, ++0x01f,0x00080003, ++0x0fe,0x00000000, ++0x0fe,0x00000000, ++0x01e,0x00044457, ++0x01f,0x00080000, ++0x000,0x00030159, ++}; ++ ++u32 Rtl8192CURadioB_1T_mCardArray[RadioB_1T_mCardArrayLength] = { ++0x0, }; ++ ++u32 Rtl8192CURadioA_1T_HPArray[RadioA_1T_HPArrayLength] = { ++0x000,0x00030159, ++0x001,0x00031284, ++0x002,0x00098000, ++0x003,0x00018c63, ++0x004,0x000210e7, ++0x009,0x0002044f, ++0x00a,0x0001adb0, ++0x00b,0x00054867, ++0x00c,0x0008992e, ++0x00d,0x0000e529, ++0x00e,0x00039ce7, ++0x00f,0x00000451, ++0x019,0x00000000, ++0x01a,0x00000255, ++0x01b,0x00060a00, ++0x01c,0x000fc378, ++0x01d,0x000a1250, ++0x01e,0x0004445f, ++0x01f,0x00080001, ++0x020,0x0000b614, ++0x021,0x0006c000, ++0x022,0x0000083c, ++0x023,0x00001558, ++0x024,0x00000060, ++0x025,0x00000483, ++0x026,0x0004f000, ++0x027,0x000ec7d9, ++0x028,0x000977c0, ++0x029,0x00004783, ++0x02a,0x00000001, ++0x02b,0x00021334, ++0x02a,0x00000000, ++0x02b,0x00000054, ++0x02a,0x00000001, ++0x02b,0x00000808, ++0x02b,0x00053333, ++0x02c,0x0000000c, ++0x02a,0x00000002, ++0x02b,0x00000808, ++0x02b,0x0005b333, ++0x02c,0x0000000d, ++0x02a,0x00000003, ++0x02b,0x00000808, ++0x02b,0x00063333, ++0x02c,0x0000000d, ++0x02a,0x00000004, ++0x02b,0x00000808, ++0x02b,0x0006b333, ++0x02c,0x0000000d, ++0x02a,0x00000005, ++0x02b,0x00000808, ++0x02b,0x00073333, ++0x02c,0x0000000d, ++0x02a,0x00000006, ++0x02b,0x00000709, ++0x02b,0x0005b333, ++0x02c,0x0000000d, ++0x02a,0x00000007, ++0x02b,0x00000709, ++0x02b,0x00063333, ++0x02c,0x0000000d, ++0x02a,0x00000008, ++0x02b,0x0000060a, ++0x02b,0x0004b333, ++0x02c,0x0000000d, ++0x02a,0x00000009, ++0x02b,0x0000060a, ++0x02b,0x00053333, ++0x02c,0x0000000d, ++0x02a,0x0000000a, ++0x02b,0x0000060a, ++0x02b,0x0005b333, ++0x02c,0x0000000d, ++0x02a,0x0000000b, ++0x02b,0x0000060a, ++0x02b,0x00063333, ++0x02c,0x0000000d, ++0x02a,0x0000000c, ++0x02b,0x0000060a, ++0x02b,0x0006b333, ++0x02c,0x0000000d, ++0x02a,0x0000000d, ++0x02b,0x0000060a, ++0x02b,0x00073333, ++0x02c,0x0000000d, ++0x02a,0x0000000e, ++0x02b,0x0000050b, ++0x02b,0x00066666, ++0x02c,0x0000001a, ++0x02a,0x000e0000, ++0x010,0x0004000f, ++0x011,0x000e31fc, ++0x010,0x0006000f, ++0x011,0x000ff9f8, ++0x010,0x0002000f, ++0x011,0x000203f9, ++0x010,0x0003000f, ++0x011,0x000ff500, ++0x010,0x00000000, ++0x011,0x00000000, ++0x010,0x0008000f, ++0x011,0x0003f100, ++0x010,0x0009000f, ++0x011,0x00023100, ++0x012,0x000d8000, ++0x012,0x00090000, ++0x012,0x00051000, ++0x012,0x00012000, ++0x013,0x00028fb4, ++0x013,0x00024fa8, ++0x013,0x000207a4, ++0x013,0x0001c798, ++0x013,0x000183a4, ++0x013,0x00014398, ++0x013,0x000101a4, ++0x013,0x0000c198, ++0x013,0x000080a4, ++0x013,0x00004098, ++0x013,0x00000000, ++0x014,0x0001944c, ++0x014,0x00059444, ++0x014,0x0009944c, ++0x014,0x000d9444, ++0x015,0x0000f405, ++0x015,0x0004f405, ++0x015,0x0008f405, ++0x015,0x000cf405, ++0x016,0x000e0330, ++0x016,0x000a0330, ++0x016,0x00060330, ++0x016,0x00020330, ++0x000,0x00010159, ++0x018,0x0000f401, ++0x0fe,0x00000000, ++0x0fe,0x00000000, ++0x01f,0x00080003, ++0x0fe,0x00000000, ++0x0fe,0x00000000, ++0x01e,0x00044457, ++0x01f,0x00080000, ++0x000,0x00030159, ++}; ++ ++u32 Rtl8192CURadioB_GM_Array[RadioB_GM_ArrayLength] = { ++0x0, }; ++ ++// MAC reg V13 - 2010-12-07 ++u32 Rtl8192CUMAC_2T_Array[MAC_2T_ArrayLength] = { ++0x420,0x00000080, ++0x423,0x00000000, ++0x430,0x00000000, ++0x431,0x00000000, ++0x432,0x00000000, ++0x433,0x00000001, ++0x434,0x00000004, ++0x435,0x00000005, ++0x436,0x00000006, ++0x437,0x00000007, ++0x438,0x00000000, ++0x439,0x00000000, ++0x43a,0x00000000, ++0x43b,0x00000001, ++0x43c,0x00000004, ++0x43d,0x00000005, ++0x43e,0x00000006, ++0x43f,0x00000007, ++0x440,0x0000005d, ++0x441,0x00000001, ++0x442,0x00000000, ++0x444,0x00000015, ++0x445,0x000000f0, ++0x446,0x0000000f, ++0x447,0x00000000, ++0x458,0x00000041, ++0x459,0x000000a8, ++0x45a,0x00000072, ++0x45b,0x000000b9, ++0x460,0x00000066, ++0x461,0x00000066, ++0x462,0x00000008, ++0x463,0x00000003, ++0x4c8,0x000000ff, ++0x4c9,0x00000008, ++0x4cc,0x000000ff, ++0x4cd,0x000000ff, ++0x4ce,0x00000001, ++0x500,0x00000026, ++0x501,0x000000a2, ++0x502,0x0000002f, ++0x503,0x00000000, ++0x504,0x00000028, ++0x505,0x000000a3, ++0x506,0x0000005e, ++0x507,0x00000000, ++0x508,0x0000002b, ++0x509,0x000000a4, ++0x50a,0x0000005e, ++0x50b,0x00000000, ++0x50c,0x0000004f, ++0x50d,0x000000a4, ++0x50e,0x00000000, ++0x50f,0x00000000, ++0x512,0x0000001c, ++0x514,0x0000000a, ++0x515,0x00000010, ++0x516,0x0000000a, ++0x517,0x00000010, ++0x51a,0x00000016, ++0x524,0x0000000f, ++0x525,0x0000004f, ++0x546,0x00000040, ++0x547,0x00000000, ++0x550,0x00000010, ++0x551,0x00000010, ++0x559,0x00000002, ++0x55a,0x00000002, ++0x55d,0x000000ff, ++0x605,0x00000030, ++0x608,0x0000000e, ++0x609,0x0000002a, ++0x652,0x00000020, ++0x63c,0x0000000a, ++0x63d,0x0000000e, ++0x63e,0x0000000a, ++0x63f,0x0000000e, ++0x66e,0x00000005, ++0x700,0x00000021, ++0x701,0x00000043, ++0x702,0x00000065, ++0x703,0x00000087, ++0x708,0x00000021, ++0x709,0x00000043, ++0x70a,0x00000065, ++0x70b,0x00000087, ++}; ++ ++u32 Rtl8192CUMACPHY_Array_PG[MACPHY_Array_PGLength] = { ++0x0, }; ++ ++u32 Rtl8192CUAGCTAB_2TArray[AGCTAB_2TArrayLength] = { ++0xc78,0x7b000001, ++0xc78,0x7b010001, ++0xc78,0x7b020001, ++0xc78,0x7b030001, ++0xc78,0x7b040001, ++0xc78,0x7b050001, ++0xc78,0x7a060001, ++0xc78,0x79070001, ++0xc78,0x78080001, ++0xc78,0x77090001, ++0xc78,0x760a0001, ++0xc78,0x750b0001, ++0xc78,0x740c0001, ++0xc78,0x730d0001, ++0xc78,0x720e0001, ++0xc78,0x710f0001, ++0xc78,0x70100001, ++0xc78,0x6f110001, ++0xc78,0x6e120001, ++0xc78,0x6d130001, ++0xc78,0x6c140001, ++0xc78,0x6b150001, ++0xc78,0x6a160001, ++0xc78,0x69170001, ++0xc78,0x68180001, ++0xc78,0x67190001, ++0xc78,0x661a0001, ++0xc78,0x651b0001, ++0xc78,0x641c0001, ++0xc78,0x631d0001, ++0xc78,0x621e0001, ++0xc78,0x611f0001, ++0xc78,0x60200001, ++0xc78,0x49210001, ++0xc78,0x48220001, ++0xc78,0x47230001, ++0xc78,0x46240001, ++0xc78,0x45250001, ++0xc78,0x44260001, ++0xc78,0x43270001, ++0xc78,0x42280001, ++0xc78,0x41290001, ++0xc78,0x402a0001, ++0xc78,0x262b0001, ++0xc78,0x252c0001, ++0xc78,0x242d0001, ++0xc78,0x232e0001, ++0xc78,0x222f0001, ++0xc78,0x21300001, ++0xc78,0x20310001, ++0xc78,0x06320001, ++0xc78,0x05330001, ++0xc78,0x04340001, ++0xc78,0x03350001, ++0xc78,0x02360001, ++0xc78,0x01370001, ++0xc78,0x00380001, ++0xc78,0x00390001, ++0xc78,0x003a0001, ++0xc78,0x003b0001, ++0xc78,0x003c0001, ++0xc78,0x003d0001, ++0xc78,0x003e0001, ++0xc78,0x003f0001, ++0xc78,0x7b400001, ++0xc78,0x7b410001, ++0xc78,0x7b420001, ++0xc78,0x7b430001, ++0xc78,0x7b440001, ++0xc78,0x7b450001, ++0xc78,0x7a460001, ++0xc78,0x79470001, ++0xc78,0x78480001, ++0xc78,0x77490001, ++0xc78,0x764a0001, ++0xc78,0x754b0001, ++0xc78,0x744c0001, ++0xc78,0x734d0001, ++0xc78,0x724e0001, ++0xc78,0x714f0001, ++0xc78,0x70500001, ++0xc78,0x6f510001, ++0xc78,0x6e520001, ++0xc78,0x6d530001, ++0xc78,0x6c540001, ++0xc78,0x6b550001, ++0xc78,0x6a560001, ++0xc78,0x69570001, ++0xc78,0x68580001, ++0xc78,0x67590001, ++0xc78,0x665a0001, ++0xc78,0x655b0001, ++0xc78,0x645c0001, ++0xc78,0x635d0001, ++0xc78,0x625e0001, ++0xc78,0x615f0001, ++0xc78,0x60600001, ++0xc78,0x49610001, ++0xc78,0x48620001, ++0xc78,0x47630001, ++0xc78,0x46640001, ++0xc78,0x45650001, ++0xc78,0x44660001, ++0xc78,0x43670001, ++0xc78,0x42680001, ++0xc78,0x41690001, ++0xc78,0x406a0001, ++0xc78,0x266b0001, ++0xc78,0x256c0001, ++0xc78,0x246d0001, ++0xc78,0x236e0001, ++0xc78,0x226f0001, ++0xc78,0x21700001, ++0xc78,0x20710001, ++0xc78,0x06720001, ++0xc78,0x05730001, ++0xc78,0x04740001, ++0xc78,0x03750001, ++0xc78,0x02760001, ++0xc78,0x01770001, ++0xc78,0x00780001, ++0xc78,0x00790001, ++0xc78,0x007a0001, ++0xc78,0x007b0001, ++0xc78,0x007c0001, ++0xc78,0x007d0001, ++0xc78,0x007e0001, ++0xc78,0x007f0001, ++0xc78,0x3800001e, ++0xc78,0x3801001e, ++0xc78,0x3802001e, ++0xc78,0x3803001e, ++0xc78,0x3804001e, ++0xc78,0x3805001e, ++0xc78,0x3806001e, ++0xc78,0x3807001e, ++0xc78,0x3808001e, ++0xc78,0x3c09001e, ++0xc78,0x3e0a001e, ++0xc78,0x400b001e, ++0xc78,0x440c001e, ++0xc78,0x480d001e, ++0xc78,0x4c0e001e, ++0xc78,0x500f001e, ++0xc78,0x5210001e, ++0xc78,0x5611001e, ++0xc78,0x5a12001e, ++0xc78,0x5e13001e, ++0xc78,0x6014001e, ++0xc78,0x6015001e, ++0xc78,0x6016001e, ++0xc78,0x6217001e, ++0xc78,0x6218001e, ++0xc78,0x6219001e, ++0xc78,0x621a001e, ++0xc78,0x621b001e, ++0xc78,0x621c001e, ++0xc78,0x621d001e, ++0xc78,0x621e001e, ++0xc78,0x621f001e, ++}; ++ ++u32 Rtl8192CUAGCTAB_1TArray[AGCTAB_1TArrayLength] = { ++0xc78,0x7b000001, ++0xc78,0x7b010001, ++0xc78,0x7b020001, ++0xc78,0x7b030001, ++0xc78,0x7b040001, ++0xc78,0x7b050001, ++0xc78,0x7a060001, ++0xc78,0x79070001, ++0xc78,0x78080001, ++0xc78,0x77090001, ++0xc78,0x760a0001, ++0xc78,0x750b0001, ++0xc78,0x740c0001, ++0xc78,0x730d0001, ++0xc78,0x720e0001, ++0xc78,0x710f0001, ++0xc78,0x70100001, ++0xc78,0x6f110001, ++0xc78,0x6e120001, ++0xc78,0x6d130001, ++0xc78,0x6c140001, ++0xc78,0x6b150001, ++0xc78,0x6a160001, ++0xc78,0x69170001, ++0xc78,0x68180001, ++0xc78,0x67190001, ++0xc78,0x661a0001, ++0xc78,0x651b0001, ++0xc78,0x641c0001, ++0xc78,0x631d0001, ++0xc78,0x621e0001, ++0xc78,0x611f0001, ++0xc78,0x60200001, ++0xc78,0x49210001, ++0xc78,0x48220001, ++0xc78,0x47230001, ++0xc78,0x46240001, ++0xc78,0x45250001, ++0xc78,0x44260001, ++0xc78,0x43270001, ++0xc78,0x42280001, ++0xc78,0x41290001, ++0xc78,0x402a0001, ++0xc78,0x262b0001, ++0xc78,0x252c0001, ++0xc78,0x242d0001, ++0xc78,0x232e0001, ++0xc78,0x222f0001, ++0xc78,0x21300001, ++0xc78,0x20310001, ++0xc78,0x06320001, ++0xc78,0x05330001, ++0xc78,0x04340001, ++0xc78,0x03350001, ++0xc78,0x02360001, ++0xc78,0x01370001, ++0xc78,0x00380001, ++0xc78,0x00390001, ++0xc78,0x003a0001, ++0xc78,0x003b0001, ++0xc78,0x003c0001, ++0xc78,0x003d0001, ++0xc78,0x003e0001, ++0xc78,0x003f0001, ++0xc78,0x7b400001, ++0xc78,0x7b410001, ++0xc78,0x7b420001, ++0xc78,0x7b430001, ++0xc78,0x7b440001, ++0xc78,0x7b450001, ++0xc78,0x7a460001, ++0xc78,0x79470001, ++0xc78,0x78480001, ++0xc78,0x77490001, ++0xc78,0x764a0001, ++0xc78,0x754b0001, ++0xc78,0x744c0001, ++0xc78,0x734d0001, ++0xc78,0x724e0001, ++0xc78,0x714f0001, ++0xc78,0x70500001, ++0xc78,0x6f510001, ++0xc78,0x6e520001, ++0xc78,0x6d530001, ++0xc78,0x6c540001, ++0xc78,0x6b550001, ++0xc78,0x6a560001, ++0xc78,0x69570001, ++0xc78,0x68580001, ++0xc78,0x67590001, ++0xc78,0x665a0001, ++0xc78,0x655b0001, ++0xc78,0x645c0001, ++0xc78,0x635d0001, ++0xc78,0x625e0001, ++0xc78,0x615f0001, ++0xc78,0x60600001, ++0xc78,0x49610001, ++0xc78,0x48620001, ++0xc78,0x47630001, ++0xc78,0x46640001, ++0xc78,0x45650001, ++0xc78,0x44660001, ++0xc78,0x43670001, ++0xc78,0x42680001, ++0xc78,0x41690001, ++0xc78,0x406a0001, ++0xc78,0x266b0001, ++0xc78,0x256c0001, ++0xc78,0x246d0001, ++0xc78,0x236e0001, ++0xc78,0x226f0001, ++0xc78,0x21700001, ++0xc78,0x20710001, ++0xc78,0x06720001, ++0xc78,0x05730001, ++0xc78,0x04740001, ++0xc78,0x03750001, ++0xc78,0x02760001, ++0xc78,0x01770001, ++0xc78,0x00780001, ++0xc78,0x00790001, ++0xc78,0x007a0001, ++0xc78,0x007b0001, ++0xc78,0x007c0001, ++0xc78,0x007d0001, ++0xc78,0x007e0001, ++0xc78,0x007f0001, ++0xc78,0x3800001e, ++0xc78,0x3801001e, ++0xc78,0x3802001e, ++0xc78,0x3803001e, ++0xc78,0x3804001e, ++0xc78,0x3805001e, ++0xc78,0x3806001e, ++0xc78,0x3807001e, ++0xc78,0x3808001e, ++0xc78,0x3c09001e, ++0xc78,0x3e0a001e, ++0xc78,0x400b001e, ++0xc78,0x440c001e, ++0xc78,0x480d001e, ++0xc78,0x4c0e001e, ++0xc78,0x500f001e, ++0xc78,0x5210001e, ++0xc78,0x5611001e, ++0xc78,0x5a12001e, ++0xc78,0x5e13001e, ++0xc78,0x6014001e, ++0xc78,0x6015001e, ++0xc78,0x6016001e, ++0xc78,0x6217001e, ++0xc78,0x6218001e, ++0xc78,0x6219001e, ++0xc78,0x621a001e, ++0xc78,0x621b001e, ++0xc78,0x621c001e, ++0xc78,0x621d001e, ++0xc78,0x621e001e, ++0xc78,0x621f001e, ++}; ++ ++u32 Rtl8192CUAGCTAB_1T_HPArray[AGCTAB_1T_HPArrayLength] = { ++0xc78,0x7b000001, ++0xc78,0x7b010001, ++0xc78,0x7b020001, ++0xc78,0x7b030001, ++0xc78,0x7b040001, ++0xc78,0x7b050001, ++0xc78,0x7b060001, ++0xc78,0x7b070001, ++0xc78,0x7b080001, ++0xc78,0x7a090001, ++0xc78,0x790a0001, ++0xc78,0x780b0001, ++0xc78,0x770c0001, ++0xc78,0x760d0001, ++0xc78,0x750e0001, ++0xc78,0x740f0001, ++0xc78,0x73100001, ++0xc78,0x72110001, ++0xc78,0x71120001, ++0xc78,0x70130001, ++0xc78,0x6f140001, ++0xc78,0x6e150001, ++0xc78,0x6d160001, ++0xc78,0x6c170001, ++0xc78,0x6b180001, ++0xc78,0x6a190001, ++0xc78,0x691a0001, ++0xc78,0x681b0001, ++0xc78,0x671c0001, ++0xc78,0x661d0001, ++0xc78,0x651e0001, ++0xc78,0x641f0001, ++0xc78,0x63200001, ++0xc78,0x62210001, ++0xc78,0x61220001, ++0xc78,0x60230001, ++0xc78,0x46240001, ++0xc78,0x45250001, ++0xc78,0x44260001, ++0xc78,0x43270001, ++0xc78,0x42280001, ++0xc78,0x41290001, ++0xc78,0x402a0001, ++0xc78,0x262b0001, ++0xc78,0x252c0001, ++0xc78,0x242d0001, ++0xc78,0x232e0001, ++0xc78,0x222f0001, ++0xc78,0x21300001, ++0xc78,0x20310001, ++0xc78,0x06320001, ++0xc78,0x05330001, ++0xc78,0x04340001, ++0xc78,0x03350001, ++0xc78,0x02360001, ++0xc78,0x01370001, ++0xc78,0x00380001, ++0xc78,0x00390001, ++0xc78,0x003a0001, ++0xc78,0x003b0001, ++0xc78,0x003c0001, ++0xc78,0x003d0001, ++0xc78,0x003e0001, ++0xc78,0x003f0001, ++0xc78,0x7b400001, ++0xc78,0x7b410001, ++0xc78,0x7b420001, ++0xc78,0x7b430001, ++0xc78,0x7b440001, ++0xc78,0x7b450001, ++0xc78,0x7b460001, ++0xc78,0x7b470001, ++0xc78,0x7b480001, ++0xc78,0x7a490001, ++0xc78,0x794a0001, ++0xc78,0x784b0001, ++0xc78,0x774c0001, ++0xc78,0x764d0001, ++0xc78,0x754e0001, ++0xc78,0x744f0001, ++0xc78,0x73500001, ++0xc78,0x72510001, ++0xc78,0x71520001, ++0xc78,0x70530001, ++0xc78,0x6f540001, ++0xc78,0x6e550001, ++0xc78,0x6d560001, ++0xc78,0x6c570001, ++0xc78,0x6b580001, ++0xc78,0x6a590001, ++0xc78,0x695a0001, ++0xc78,0x685b0001, ++0xc78,0x675c0001, ++0xc78,0x665d0001, ++0xc78,0x655e0001, ++0xc78,0x645f0001, ++0xc78,0x63600001, ++0xc78,0x62610001, ++0xc78,0x61620001, ++0xc78,0x60630001, ++0xc78,0x46640001, ++0xc78,0x45650001, ++0xc78,0x44660001, ++0xc78,0x43670001, ++0xc78,0x42680001, ++0xc78,0x41690001, ++0xc78,0x406a0001, ++0xc78,0x266b0001, ++0xc78,0x256c0001, ++0xc78,0x246d0001, ++0xc78,0x236e0001, ++0xc78,0x226f0001, ++0xc78,0x21700001, ++0xc78,0x20710001, ++0xc78,0x06720001, ++0xc78,0x05730001, ++0xc78,0x04740001, ++0xc78,0x03750001, ++0xc78,0x02760001, ++0xc78,0x01770001, ++0xc78,0x00780001, ++0xc78,0x00790001, ++0xc78,0x007a0001, ++0xc78,0x007b0001, ++0xc78,0x007c0001, ++0xc78,0x007d0001, ++0xc78,0x007e0001, ++0xc78,0x007f0001, ++0xc78,0x3800001e, ++0xc78,0x3801001e, ++0xc78,0x3802001e, ++0xc78,0x3803001e, ++0xc78,0x3804001e, ++0xc78,0x3805001e, ++0xc78,0x3806001e, ++0xc78,0x3807001e, ++0xc78,0x3808001e, ++0xc78,0x3c09001e, ++0xc78,0x3e0a001e, ++0xc78,0x400b001e, ++0xc78,0x440c001e, ++0xc78,0x480d001e, ++0xc78,0x4c0e001e, ++0xc78,0x500f001e, ++0xc78,0x5210001e, ++0xc78,0x5611001e, ++0xc78,0x5a12001e, ++0xc78,0x5e13001e, ++0xc78,0x6014001e, ++0xc78,0x6015001e, ++0xc78,0x6016001e, ++0xc78,0x6217001e, ++0xc78,0x6218001e, ++0xc78,0x6219001e, ++0xc78,0x621a001e, ++0xc78,0x621b001e, ++0xc78,0x621c001e, ++0xc78,0x621d001e, ++0xc78,0x621e001e, ++0xc78,0x621f001e, ++}; ++ +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/hal/rtl8192c/usb/Hal8192CUHWImg_wowlan.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/hal/rtl8192c/usb/Hal8192CUHWImg_wowlan.c 2013-07-26 19:36:05.000000000 +0000 +@@ -0,0 +1,2564 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++/*Created on 2011/11/ 8, 14:15*/ ++ ++#include ++#include "Hal8192CUHWImg_wowlan.h" ++ ++ ++u8 Rtl8192CUFwTSMCWWImgArray[TSMCWWImgArrayLength] = { ++0xc1,0x88,0x02,0x00,0x51,0x00,0x00,0x00,0x03,0x23,0x16,0x43,0x72,0x34,0x00,0x00, ++0x58,0x92,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x02,0x43,0x9d,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x02,0x57,0xcb,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x02,0x5c,0xb6,0x00,0x00,0x00,0x00,0x00,0x02,0x5d,0x99,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0xbb,0x01,0x0c,0xe5,0x82,0x29,0xf5,0x82,0xe5,0x83,0x3a,0xf5,0x83,0xe0,0x22,0x50, ++0x06,0xe9,0x25,0x82,0xf8,0xe6,0x22,0xbb,0xfe,0x06,0xe9,0x25,0x82,0xf8,0xe2,0x22, ++0xe5,0x82,0x29,0xf5,0x82,0xe5,0x83,0x3a,0xf5,0x83,0xe4,0x93,0x22,0xbb,0x01,0x06, ++0x89,0x82,0x8a,0x83,0xf0,0x22,0x50,0x02,0xf7,0x22,0xbb,0xfe,0x01,0xf3,0x22,0xf8, ++0xbb,0x01,0x0d,0xe5,0x82,0x29,0xf5,0x82,0xe5,0x83,0x3a,0xf5,0x83,0xe8,0xf0,0x22, ++0x50,0x06,0xe9,0x25,0x82,0xc8,0xf6,0x22,0xbb,0xfe,0x05,0xe9,0x25,0x82,0xc8,0xf2, ++0x22,0xc5,0xf0,0xf8,0xa3,0xe0,0x28,0xf0,0xc5,0xf0,0xf8,0xe5,0x82,0x15,0x82,0x70, ++0x02,0x15,0x83,0xe0,0x38,0xf0,0x22,0xbb,0x01,0x10,0xe5,0x82,0x29,0xf5,0x82,0xe5, ++0x83,0x3a,0xf5,0x83,0xe0,0xf5,0xf0,0xa3,0xe0,0x22,0x50,0x09,0xe9,0x25,0x82,0xf8, ++0x86,0xf0,0x08,0xe6,0x22,0xbb,0xfe,0x0a,0xe9,0x25,0x82,0xf8,0xe2,0xf5,0xf0,0x08, ++0xe2,0x22,0xe5,0x83,0x2a,0xf5,0x83,0xe9,0x93,0xf5,0xf0,0xa3,0xe9,0x93,0x22,0xf8, ++0xbb,0x01,0x11,0xe5,0x82,0x29,0xf5,0x82,0xe5,0x83,0x3a,0xf5,0x83,0xe8,0xf0,0xe5, ++0xf0,0xa3,0xf0,0x22,0x50,0x09,0xe9,0x25,0x82,0xc8,0xf6,0x08,0xa6,0xf0,0x22,0xbb, ++0xfe,0x09,0xe9,0x25,0x82,0xc8,0xf2,0xe5,0xf0,0x08,0xf2,0x22,0xef,0x4b,0xff,0xee, ++0x4a,0xfe,0xed,0x49,0xfd,0xec,0x48,0xfc,0x22,0xe0,0xfc,0xa3,0xe0,0xfd,0xa3,0xe0, ++0xfe,0xa3,0xe0,0xff,0x22,0xa4,0x25,0x82,0xf5,0x82,0xe5,0xf0,0x35,0x83,0xf5,0x83, ++0x22,0xe0,0xfb,0xa3,0xe0,0xfa,0xa3,0xe0,0xf9,0x22,0xf8,0xe0,0xfb,0xa3,0xa3,0xe0, ++0xf9,0x25,0xf0,0xf0,0xe5,0x82,0x15,0x82,0x70,0x02,0x15,0x83,0xe0,0xfa,0x38,0xf0, ++0x22,0xeb,0xf0,0xa3,0xea,0xf0,0xa3,0xe9,0xf0,0x22,0xd0,0x83,0xd0,0x82,0xf8,0xe4, ++0x93,0x70,0x12,0x74,0x01,0x93,0x70,0x0d,0xa3,0xa3,0x93,0xf8,0x74,0x01,0x93,0xf5, ++0x82,0x88,0x83,0xe4,0x73,0x74,0x02,0x93,0x68,0x60,0xef,0xa3,0xa3,0xa3,0x80,0xdf, ++0xd0,0x83,0xd0,0x82,0xf8,0xe4,0x93,0x70,0x12,0x74,0x01,0x93,0x70,0x0d,0xa3,0xa3, ++0x93,0xf8,0x74,0x01,0x93,0xf5,0x82,0x88,0x83,0xe4,0x73,0x74,0x02,0x93,0xb5,0xf0, ++0x06,0x74,0x03,0x93,0x68,0x60,0xe9,0xa3,0xa3,0xa3,0xa3,0x80,0xd8,0x02,0x43,0xdb, ++0x02,0x50,0x2a,0xe4,0x93,0xa3,0xf8,0xe4,0x93,0xa3,0x40,0x03,0xf6,0x80,0x01,0xf2, ++0x08,0xdf,0xf4,0x80,0x29,0xe4,0x93,0xa3,0xf8,0x54,0x07,0x24,0x0c,0xc8,0xc3,0x33, ++0xc4,0x54,0x0f,0x44,0x20,0xc8,0x83,0x40,0x04,0xf4,0x56,0x80,0x01,0x46,0xf6,0xdf, ++0xe4,0x80,0x0b,0x01,0x02,0x04,0x08,0x10,0x20,0x40,0x80,0x90,0x44,0x20,0xe4,0x7e, ++0x01,0x93,0x60,0xbc,0xa3,0xff,0x54,0x3f,0x30,0xe5,0x09,0x54,0x1f,0xfe,0xe4,0x93, ++0xa3,0x60,0x01,0x0e,0xcf,0x54,0xc0,0x25,0xe0,0x60,0xa8,0x40,0xb8,0xe4,0x93,0xa3, ++0xfa,0xe4,0x93,0xa3,0xf8,0xe4,0x93,0xa3,0xc8,0xc5,0x82,0xc8,0xca,0xc5,0x83,0xca, ++0xf0,0xa3,0xc8,0xc5,0x82,0xc8,0xca,0xc5,0x83,0xca,0xdf,0xe9,0xde,0xe7,0x80,0xbe, ++0x41,0x91,0x40,0x00,0x41,0x91,0x9c,0x00,0x41,0x91,0x23,0x80,0x41,0x91,0x24,0x80, ++0x41,0x91,0x9e,0x00,0x41,0x91,0x52,0x00,0x41,0x91,0x93,0x00,0x41,0x91,0x91,0x00, ++0x41,0x91,0x90,0x00,0x41,0x91,0x92,0x00,0x00,0xf0,0x90,0x91,0x30,0xe0,0x90,0x91, ++0x67,0xf0,0xe4,0xfb,0xfd,0x7f,0x54,0x7e,0x01,0xd3,0x10,0xaf,0x01,0xc3,0xc0,0xd0, ++0x90,0x91,0x65,0xeb,0xf0,0xa3,0xe0,0xfb,0xa3,0xe0,0xf5,0x44,0xe4,0xf5,0x45,0x12, ++0x35,0xab,0xd0,0xd0,0x92,0xaf,0x22,0x90,0x01,0x5f,0xe4,0xf0,0x90,0x01,0x3c,0x74, ++0x08,0xf0,0xe4,0x90,0x91,0x66,0xf0,0x90,0x91,0x2d,0xe0,0x90,0x91,0x67,0xf0,0xe4, ++0xfb,0xfd,0x7f,0x5c,0x7e,0x01,0x91,0x59,0x90,0x01,0x5f,0x74,0x05,0xf0,0x90,0x06, ++0x92,0x74,0x02,0xf0,0x90,0x91,0x36,0x14,0xf0,0xe5,0x6e,0x54,0x0f,0xc3,0x94,0x0c, ++0x50,0x02,0xf1,0x23,0x22,0x90,0x02,0x84,0xef,0xf0,0xa3,0xee,0xf0,0xa3,0x74,0x05, ++0xf0,0x22,0x7d,0x01,0xaf,0x6f,0xe1,0x27,0xf1,0xe6,0xbf,0x01,0x10,0x90,0x91,0x42, ++0xe0,0xff,0xe4,0xfd,0x12,0x48,0x22,0x90,0x04,0x1f,0x74,0x20,0xf0,0x22,0x8f,0x82, ++0x8e,0x83,0xa3,0xa3,0xa3,0xe4,0xf0,0x22,0xe4,0xf5,0x72,0x7f,0x60,0x7e,0x01,0x80, ++0xed,0x7f,0x00,0x22,0x90,0x91,0x53,0xe0,0x54,0xfe,0xf0,0x02,0x50,0xd6,0x22,0xe4, ++0xf5,0x75,0x22,0x02,0x5f,0xe2,0x02,0x5f,0xe9,0xef,0x8e,0xf0,0x71,0x70,0x45,0x26, ++0x00,0x40,0x45,0x4e,0x00,0x80,0x45,0x79,0x01,0x00,0x45,0x8d,0x02,0x00,0x45,0xa5, ++0x04,0x00,0x00,0x00,0x45,0xc2,0xed,0x54,0x3f,0x70,0x04,0xfe,0xff,0x80,0x04,0x7e, ++0x00,0x7f,0x40,0xef,0x2d,0xff,0xee,0x3c,0xfe,0xef,0x78,0x06,0xce,0xc3,0x13,0xce, ++0x13,0xd8,0xf9,0x78,0x06,0xc3,0x33,0xce,0x33,0xce,0xd8,0xf9,0x80,0x26,0xed,0x54, ++0x7f,0x70,0x04,0xfe,0xff,0x80,0x04,0x7e,0x00,0x7f,0x80,0xef,0x2d,0xff,0xee,0x3c, ++0xfe,0xef,0x78,0x07,0xce,0xc3,0x13,0xce,0x13,0xd8,0xf9,0x78,0x07,0xc3,0x33,0xce, ++0x33,0xce,0xd8,0xf9,0xfd,0xac,0x06,0x80,0x49,0xed,0x70,0x04,0xfe,0xff,0x80,0x04, ++0x7e,0x01,0x7f,0x00,0xef,0x2d,0xee,0x3c,0x7d,0x00,0xfc,0x80,0x35,0xec,0x54,0x01, ++0x4d,0x70,0x04,0xfe,0xff,0x80,0x04,0x7e,0x02,0x7f,0x00,0xef,0x2d,0xee,0x3c,0xc3, ++0x13,0x7d,0x00,0x80,0x1a,0xec,0x54,0x03,0x4d,0x70,0x04,0xfe,0xff,0x80,0x04,0x7e, ++0x04,0x7f,0x00,0xef,0x2d,0xee,0x3c,0x13,0x13,0x54,0x3f,0x7d,0x00,0x25,0xe0,0x25, ++0xe0,0xfc,0xae,0x04,0xaf,0x05,0x22,0x90,0x91,0x09,0x12,0x2a,0x8b,0x00,0x00,0x00, ++0x00,0x90,0x06,0xa9,0xe0,0x90,0x91,0x08,0xf0,0xe0,0x54,0xc0,0x70,0x0a,0x53,0x71, ++0xfe,0x53,0x71,0xfd,0x91,0xc2,0x80,0x47,0x90,0x91,0x26,0xe0,0x60,0x41,0x90,0x91, ++0x38,0xe0,0x70,0x3b,0x90,0x91,0x38,0x74,0x01,0xf0,0x7f,0x00,0x7e,0x08,0x12,0x27, ++0xde,0x90,0x91,0x09,0x12,0x2a,0x7f,0x90,0x91,0x09,0x71,0x09,0xec,0x44,0x02,0xfc, ++0x90,0x91,0x09,0x12,0x2a,0x7f,0x90,0x91,0x09,0x71,0x09,0x90,0x80,0x85,0x12,0x2a, ++0x7f,0x7f,0x00,0x7e,0x08,0x12,0x2f,0xd9,0x90,0x02,0x86,0xe0,0x54,0xfb,0xf0,0x90, ++0x91,0x08,0xe0,0x30,0xe6,0x13,0x43,0x71,0x01,0x90,0x91,0x3b,0xe0,0x64,0x02,0x60, ++0x04,0x91,0xc8,0x80,0x07,0x91,0x77,0x80,0x03,0x53,0x71,0xfe,0x90,0x91,0x08,0xe0, ++0x30,0xe7,0x16,0x43,0x71,0x02,0xe4,0x90,0x91,0x66,0x91,0x49,0x90,0x01,0x57,0x74, ++0x05,0xf0,0x90,0x91,0x3c,0x74,0x01,0xf0,0x22,0x53,0x71,0xfd,0x22,0xd3,0x10,0xaf, ++0x01,0xc3,0xc0,0xd0,0x8b,0x60,0x8a,0x61,0x89,0x62,0x90,0x91,0x68,0x71,0x41,0xab, ++0x63,0xaa,0x64,0xa9,0x65,0x90,0x91,0x6b,0x71,0x41,0xaf,0x66,0x15,0x66,0xef,0x60, ++0x1b,0x90,0x91,0x6b,0xe4,0x75,0xf0,0x01,0x71,0x2a,0x12,0x29,0xd9,0xff,0x90,0x91, ++0x68,0xe4,0x75,0xf0,0x01,0x71,0x2a,0xef,0x51,0x4d,0x80,0xde,0xab,0x60,0xaa,0x61, ++0xa9,0x62,0xd0,0xd0,0x92,0xaf,0x22,0xd3,0x10,0xaf,0x01,0xc3,0xc0,0xd0,0x90,0x91, ++0x6e,0x71,0x41,0x90,0x91,0x9e,0xe0,0xff,0x04,0xf0,0x90,0x00,0x01,0xef,0x51,0x5f, ++0x7f,0xaf,0x7e,0x01,0x12,0x64,0x1c,0xef,0x60,0x44,0x90,0x91,0x6e,0x71,0x21,0x8b, ++0x63,0x8a,0x64,0x89,0x65,0x75,0x66,0x02,0x7b,0x01,0x7a,0x01,0x79,0xa0,0xd1,0x6d, ++0x90,0x91,0x71,0x71,0x21,0x8b,0x63,0x8a,0x64,0x89,0x65,0x90,0x91,0x6e,0x71,0x21, ++0x12,0x29,0xd9,0xff,0xc4,0x54,0x0f,0xf5,0x66,0x7b,0x01,0x7a,0x01,0x79,0xa2,0xd1, ++0x6d,0x90,0x01,0xaf,0x74,0xff,0xf0,0x90,0x01,0xcb,0xe0,0x64,0x80,0xf0,0xd0,0xd0, ++0x92,0xaf,0x22,0x7d,0x01,0x7f,0x0c,0x90,0x91,0x95,0xed,0xf0,0x90,0x91,0x94,0xef, ++0xf0,0x54,0x0f,0xff,0xe5,0x6e,0x54,0x0f,0x6f,0x60,0x76,0x90,0x91,0x94,0xe0,0x30, ++0xe2,0x30,0xe5,0x6e,0x20,0xe2,0x05,0x7f,0x01,0x12,0x62,0x65,0xe5,0x6e,0x30,0xe3, ++0x0f,0x90,0x91,0x94,0xe0,0x20,0xe3,0x08,0x12,0x5a,0x3f,0xef,0x60,0x53,0x80,0x52, ++0xe5,0x6e,0x20,0xe3,0x4c,0x90,0x91,0x94,0xe0,0x30,0xe3,0x45,0xa3,0xe0,0xff,0x02, ++0x62,0x4a,0xe5,0x6e,0x54,0x0f,0xff,0xbf,0x0c,0x0f,0x90,0x91,0x94,0xe0,0x20,0xe3, ++0x08,0x12,0x5a,0x3f,0xef,0x60,0x2a,0xf1,0xb2,0xe5,0x6e,0x54,0x0f,0xff,0xbf,0x04, ++0x10,0x90,0x91,0x94,0xe0,0x20,0xe2,0x09,0x12,0x5b,0xb3,0xef,0x60,0x13,0x12,0x48, ++0xce,0xe5,0x6e,0x54,0x0f,0xff,0xbf,0x02,0x08,0x91,0xf1,0xef,0x60,0x03,0x12,0x63, ++0x56,0x22,0x90,0x06,0x04,0xe0,0x44,0x40,0xf0,0xe5,0x6d,0xb4,0x01,0x04,0x7f,0x01, ++0xf1,0xc9,0x53,0x6e,0xf0,0x43,0x6e,0x04,0x22,0x8f,0x67,0xf1,0xe6,0xbf,0x01,0x15, ++0x90,0x91,0x43,0x12,0x48,0x1e,0xad,0x07,0xac,0x06,0xaf,0x67,0x12,0x61,0xa3,0x90, ++0x04,0x1f,0x74,0x20,0xf0,0x22,0xd3,0x10,0xaf,0x01,0xc3,0xc0,0xd0,0x90,0x01,0xc4, ++0x74,0xe6,0xf0,0x74,0x47,0xa3,0xf0,0x90,0x04,0x1d,0xe0,0x60,0x1a,0x90,0x05,0x22, ++0xe0,0x54,0x90,0x60,0x07,0x90,0x01,0xc6,0xe0,0x44,0x40,0xf0,0x90,0x01,0xc7,0xe0, ++0x30,0xe1,0xe4,0x7f,0x00,0x80,0x02,0x7f,0x01,0xd0,0xd0,0x92,0xaf,0x22,0xe0,0xff, ++0x7d,0x01,0x90,0x91,0x74,0xef,0xf0,0xa3,0xed,0xf0,0xe4,0xa3,0xf0,0xa3,0xf0,0xe5, ++0x70,0x60,0x04,0xe4,0xff,0x11,0xb3,0x90,0x91,0x74,0xe0,0x30,0xe0,0x09,0x90,0x91, ++0x76,0xe4,0xf0,0xa3,0x74,0x80,0xf0,0x90,0x91,0x74,0xe0,0xff,0xc3,0x13,0x90,0xfd, ++0x10,0xf0,0x90,0x04,0x25,0xef,0xf0,0x90,0x91,0x75,0xe0,0x60,0x1f,0xa3,0xa3,0xe0, ++0xff,0x24,0x0f,0xf5,0x82,0xe4,0x34,0xfc,0xf5,0x83,0xe0,0x44,0x80,0xf0,0x74,0x10, ++0x2f,0xf5,0x82,0xe4,0x34,0xfc,0xf5,0x83,0xe0,0x44,0x80,0xf0,0x90,0x91,0x76,0xa3, ++0xe0,0xff,0xfd,0x24,0x08,0xf5,0x82,0xe4,0x34,0xfc,0xf5,0x83,0xe4,0xf0,0x74,0x09, ++0x2d,0xf5,0x82,0xe4,0x34,0xfc,0xf5,0x83,0xe0,0x54,0xf0,0xf0,0x74,0x21,0x2f,0xf5, ++0x82,0xe4,0x34,0xfc,0xf5,0x83,0xe0,0x54,0xf7,0xf0,0x90,0x91,0x76,0xe0,0xfe,0xa3, ++0xe0,0xff,0x22,0xef,0x60,0x0b,0x90,0x91,0x51,0xe0,0xb4,0x01,0x10,0xe4,0xff,0x80, ++0x09,0x90,0x91,0x51,0xe0,0xb4,0x01,0x05,0x7f,0x01,0x12,0x68,0x87,0x22,0x90,0x01, ++0x37,0x74,0x02,0xf0,0x90,0x05,0x22,0x74,0xff,0xf0,0x12,0x68,0x46,0xef,0x70,0x06, ++0x90,0x01,0xc8,0x74,0xfd,0xf0,0x7d,0x02,0x7f,0x03,0x12,0x36,0xe6,0xe5,0x70,0x60, ++0x04,0x7f,0x01,0x11,0xb3,0x51,0x0c,0x53,0x6e,0xf0,0x43,0x6e,0x02,0x22,0xef,0x64, ++0x01,0x70,0x42,0x7d,0x78,0x7f,0x02,0x12,0x36,0x75,0x7d,0x02,0x7f,0x03,0x12,0x36, ++0x75,0x90,0x01,0x36,0x74,0x03,0xf0,0xfd,0x7f,0x02,0x12,0x36,0xe6,0x7d,0x10,0x7f, ++0x03,0x12,0x36,0x92,0x90,0x01,0x57,0xe4,0xf0,0x90,0x01,0x3c,0x74,0x02,0xf0,0x12, ++0x47,0x23,0xe4,0xff,0x11,0xb3,0x90,0x06,0x04,0xe0,0x54,0x7f,0xf0,0x90,0x06,0x0a, ++0xe0,0x54,0xf8,0xf0,0x22,0x90,0x01,0x36,0x74,0x7b,0xf0,0xa3,0x74,0x02,0xf0,0x7d, ++0x7b,0xff,0x12,0x36,0xe6,0x7d,0x02,0x7f,0x03,0x12,0x36,0xe6,0x7d,0x10,0x7f,0x03, ++0x12,0x36,0x92,0x90,0x06,0x04,0xe0,0x44,0x80,0xf0,0x90,0x06,0x0a,0xe0,0x44,0x07, ++0xf0,0x12,0x64,0x11,0xe5,0x6d,0x20,0xe0,0x05,0xe4,0x90,0x91,0x29,0xf0,0x22,0x8b, ++0x0e,0x8a,0x0f,0x89,0x10,0x12,0x62,0x3e,0xab,0x0e,0xaa,0x0f,0xa9,0x10,0x12,0x29, ++0xd9,0xf5,0x70,0x14,0x60,0x0e,0x14,0x60,0x1e,0x14,0x60,0x2f,0x24,0x03,0x70,0x40, ++0x7f,0x01,0x80,0x3a,0xab,0x0e,0xaa,0x0f,0xa9,0x10,0x90,0x00,0x02,0x12,0x42,0x20, ++0xfd,0xe4,0xff,0x31,0xe1,0x80,0x27,0xab,0x0e,0xaa,0x0f,0xa9,0x10,0x90,0x00,0x02, ++0x12,0x42,0x20,0xfd,0x7f,0x01,0x31,0xe1,0x1f,0x80,0x13,0xab,0x0e,0xaa,0x0f,0xa9, ++0x10,0x90,0x00,0x02,0x12,0x42,0x20,0xfd,0x7f,0x02,0x31,0xe1,0xe4,0xff,0x11,0xfe, ++0x22,0xef,0x24,0xfe,0x60,0x0b,0x04,0x70,0x22,0x90,0x91,0x39,0x74,0x01,0xf0,0x80, ++0x16,0xed,0x70,0x0a,0x90,0x91,0x35,0xe0,0x90,0x91,0x39,0xf0,0x80,0x05,0x90,0x91, ++0x39,0xed,0xf0,0x90,0x91,0x39,0xe0,0x90,0x91,0x27,0xf0,0x22,0x7f,0x78,0x7e,0x08, ++0x12,0x27,0xde,0x90,0x90,0xd8,0x12,0x2a,0x7f,0x7f,0x04,0x7e,0x0c,0x12,0x27,0xde, ++0x90,0x90,0xdc,0x12,0x2a,0x7f,0x7f,0x00,0x7e,0x08,0x12,0x27,0xde,0x90,0x90,0xe0, ++0x12,0x2a,0x7f,0x90,0x91,0x51,0xe0,0x90,0x90,0xd8,0xb4,0x01,0x0d,0x12,0x43,0x09, ++0xef,0x54,0xc7,0xff,0xed,0x54,0xc7,0xfd,0x80,0x07,0x12,0x43,0x09,0xef,0x54,0xc7, ++0xff,0xec,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0x78,0x7e,0x08,0x12,0x2f,0xd9,0x90, ++0x90,0xdc,0x12,0x43,0x09,0xef,0x54,0x0f,0xff,0xec,0x90,0x80,0x85,0x12,0x2a,0x7f, ++0x7f,0x04,0x7e,0x0c,0x12,0x2f,0xd9,0x90,0x90,0xe0,0x12,0x43,0x09,0xef,0x44,0x02, ++0xff,0xec,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0x00,0x7e,0x08,0x12,0x2f,0xd9,0x7f, ++0x70,0x7e,0x0e,0x12,0x27,0xde,0x90,0x90,0xe4,0x12,0x2a,0x7f,0x90,0x80,0x85,0x12, ++0x2a,0x8b,0x00,0x1b,0x25,0xa0,0x7f,0x70,0x7e,0x0e,0x12,0x2f,0xd9,0x90,0x80,0x59, ++0x12,0x2a,0x8b,0x00,0x00,0x00,0x00,0xe4,0xfd,0xff,0x12,0x34,0x81,0x90,0x91,0x51, ++0xe0,0xb4,0x01,0x11,0x90,0x80,0x59,0x12,0x2a,0x8b,0x00,0x00,0x00,0x00,0xe4,0xfd, ++0x7f,0x01,0x12,0x34,0x81,0x90,0x00,0x11,0xe0,0x54,0xf6,0xf0,0x80,0x08,0xf4,0xff, ++0x90,0x00,0x43,0xe0,0x5f,0xf0,0xd3,0x10,0xaf,0x01,0xc3,0xc0,0xd0,0x7f,0x10,0xdf, ++0xfe,0xd0,0xd0,0x92,0xaf,0x22,0xd3,0x10,0xaf,0x01,0xc3,0xc0,0xd0,0x90,0x91,0x9b, ++0xed,0xf0,0x90,0x91,0x9a,0xef,0xf0,0xd3,0x94,0x07,0x50,0x63,0xe0,0xff,0x74,0x01, ++0xa8,0x07,0x08,0x80,0x02,0xc3,0x33,0xd8,0xfc,0xf4,0xff,0x90,0x00,0x47,0xe0,0x5f, ++0xf0,0x51,0xe6,0x90,0x91,0x9a,0xe0,0xff,0x74,0x01,0xa8,0x07,0x08,0x80,0x02,0xc3, ++0x33,0xd8,0xfc,0xff,0x90,0x00,0x46,0xe0,0x4f,0xf0,0x51,0xe6,0x90,0x91,0x9b,0xe0, ++0x60,0x16,0x90,0x91,0x9a,0xe0,0xff,0x74,0x01,0xa8,0x07,0x08,0x80,0x02,0xc3,0x33, ++0xd8,0xfc,0xff,0x90,0x00,0x45,0x80,0x66,0x90,0x91,0x9a,0xe0,0xff,0x74,0x01,0xa8, ++0x07,0x08,0x80,0x02,0xc3,0x33,0xd8,0xfc,0xf4,0xff,0x90,0x00,0x45,0x80,0x6b,0x90, ++0x91,0x9a,0xe0,0x24,0xf8,0xf0,0xe0,0xff,0x74,0x01,0xa8,0x07,0x08,0x80,0x02,0xc3, ++0x33,0xd8,0xfc,0xc4,0x54,0xf0,0x51,0xde,0x90,0x91,0x9a,0xe0,0xff,0x74,0x01,0xa8, ++0x07,0x08,0x80,0x02,0xc3,0x33,0xd8,0xfc,0xff,0x90,0x00,0x43,0xe0,0x4f,0xf0,0x51, ++0xe6,0x90,0x91,0x9b,0xe0,0x60,0x1b,0x90,0x91,0x9a,0xe0,0xff,0x74,0x01,0xa8,0x07, ++0x08,0x80,0x02,0xc3,0x33,0xd8,0xfc,0xc4,0x54,0xf0,0xff,0x90,0x00,0x42,0xe0,0x4f, ++0x80,0x1a,0x90,0x91,0x9a,0xe0,0xff,0x74,0x01,0xa8,0x07,0x08,0x80,0x02,0xc3,0x33, ++0xd8,0xfc,0xc4,0x54,0xf0,0xf4,0xff,0x90,0x00,0x42,0xe0,0x5f,0xf0,0x51,0xe6,0xd0, ++0xd0,0x92,0xaf,0x22,0xf0,0x90,0x00,0x45,0xe0,0x54,0xfe,0xfd,0x7f,0x45,0xd3,0x10, ++0xaf,0x01,0xc3,0xc0,0xd0,0x8f,0x82,0x75,0x83,0x00,0xed,0xf0,0x51,0xe6,0xd0,0xd0, ++0x92,0xaf,0x22,0xef,0x14,0x60,0x30,0x14,0x60,0x66,0x24,0x02,0x60,0x02,0x81,0xaa, ++0x90,0x90,0xf3,0x74,0x02,0xf0,0x90,0x00,0x48,0xe0,0x44,0x0c,0xfd,0x7f,0x48,0x71, ++0xee,0x90,0x00,0x47,0xe0,0x44,0x08,0xfd,0x7f,0x47,0x71,0xee,0x90,0x00,0x45,0xe0, ++0x44,0x10,0xfd,0x7f,0x45,0x80,0x71,0xe4,0x90,0x90,0xf3,0xf0,0x90,0x90,0xef,0x12, ++0x43,0x09,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0x80,0x7e,0x08,0x12,0x2f,0xd9,0x90, ++0x00,0x45,0xe0,0x44,0xef,0xfd,0x7f,0x45,0x71,0xee,0x90,0x00,0x45,0xe0,0x54,0xef, ++0xfd,0x7f,0x45,0x71,0xee,0x90,0x00,0x46,0xe0,0x44,0x10,0xfd,0x7f,0x46,0x80,0x38, ++0x90,0x90,0xf3,0x74,0x01,0xf0,0x90,0x90,0xf9,0x12,0x43,0x09,0x90,0x80,0x85,0x12, ++0x2a,0x7f,0x7f,0x80,0x7e,0x08,0x12,0x2f,0xd9,0x90,0x00,0x45,0xe0,0x44,0x20,0xfd, ++0x7f,0x45,0x71,0xee,0x90,0x00,0x45,0xe0,0x44,0x10,0xfd,0x7f,0x45,0x71,0xee,0x90, ++0x00,0x46,0xe0,0x44,0x10,0xfd,0x7f,0x46,0x71,0xee,0x22,0x90,0x00,0x02,0x12,0x42, ++0x20,0x90,0x90,0xf5,0xf0,0x90,0x00,0x01,0x12,0x42,0x20,0x25,0xe0,0x25,0xe0,0x90, ++0x90,0xf4,0xf0,0x12,0x29,0xd9,0x25,0xe0,0x25,0xe0,0x90,0x90,0xf8,0xf0,0x90,0x05, ++0x60,0xe0,0x90,0x91,0x03,0xf0,0x90,0x05,0x61,0xe0,0x90,0x91,0x04,0xf0,0x90,0x05, ++0x62,0xe0,0x90,0x91,0x05,0xf0,0x90,0x05,0x63,0xe0,0x90,0x91,0x06,0xf0,0xa2,0xaf, ++0xe4,0x33,0x90,0x91,0x1c,0xf0,0xc2,0xaf,0x90,0x90,0xf4,0xe0,0xff,0x12,0x6e,0x67, ++0x90,0x91,0x1c,0xe0,0x24,0xff,0x92,0xaf,0x90,0x90,0xf5,0xe0,0x70,0x02,0xa1,0xb2, ++0x90,0x90,0xf4,0xe0,0x70,0x02,0xa1,0xb2,0x90,0x90,0xf8,0xe0,0x70,0x02,0xa1,0xb2, ++0xa2,0xaf,0xe4,0x33,0x90,0x91,0x1c,0xf0,0xc2,0xaf,0x90,0x91,0x07,0x74,0x01,0xf0, ++0x90,0x91,0x1c,0xe0,0x24,0xff,0x92,0xaf,0x71,0xe5,0x90,0x00,0x46,0xe0,0x44,0x01, ++0xfd,0x7f,0x46,0x71,0xee,0x90,0x90,0xed,0xe0,0x60,0x15,0x90,0x90,0xf9,0x12,0x43, ++0x09,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0x80,0x7e,0x08,0x12,0x2f,0xd9,0x80,0x06, ++0x90,0x05,0x22,0x74,0x7f,0xf0,0x90,0x00,0x45,0xe0,0x54,0xef,0xfd,0x7f,0x45,0x71, ++0xee,0x90,0x05,0x87,0xe0,0x64,0x80,0xf0,0x90,0x91,0x03,0xe0,0x90,0x05,0x84,0xf0, ++0x90,0x91,0x04,0xe0,0x90,0x05,0x85,0xf0,0x90,0x91,0x05,0xe0,0x90,0x05,0x86,0xf0, ++0x90,0x91,0x06,0xe0,0x90,0x05,0x87,0xf0,0xa2,0xaf,0xe4,0x33,0x90,0x91,0x1c,0xf0, ++0xc2,0xaf,0x90,0x01,0x3c,0xe0,0x44,0x20,0xf0,0x7d,0x20,0xe4,0xff,0x12,0x37,0x00, ++0x80,0x2b,0x90,0x90,0xf5,0xe0,0x70,0x2d,0x90,0x91,0x07,0x71,0xe4,0x90,0x00,0x46, ++0xe0,0x54,0xfe,0xfd,0x7f,0x46,0x71,0xee,0x90,0x05,0x22,0xe4,0xf0,0xa2,0xaf,0x33, ++0x90,0x91,0x1c,0xf0,0xc2,0xaf,0x7d,0x20,0xe4,0xff,0x12,0x36,0x92,0x90,0x91,0x1c, ++0xe0,0x24,0xff,0x92,0xaf,0x22,0x8b,0x0e,0x8a,0x0f,0x89,0x10,0x90,0x00,0x02,0x12, ++0x42,0x20,0x90,0x90,0xf6,0xf0,0xe0,0x30,0xe0,0x4b,0x90,0x90,0xed,0x74,0x01,0xf0, ++0x7f,0x80,0x7e,0x08,0x12,0x27,0xde,0x90,0x90,0xef,0x12,0x2a,0x7f,0xab,0x0e,0xaa, ++0x0f,0xa9,0x10,0x90,0x00,0x01,0x12,0x42,0x20,0xff,0xe4,0xfc,0xfd,0xfe,0x78,0x1a, ++0x12,0x2a,0x6c,0xa8,0x04,0xa9,0x05,0xaa,0x06,0xab,0x07,0x90,0x90,0xef,0x12,0x43, ++0x09,0xec,0x54,0x03,0xfc,0x12,0x42,0xfc,0x90,0x90,0xf9,0x12,0x2a,0x7f,0x90,0x05, ++0x22,0xe4,0xf0,0x80,0x2d,0xe4,0x90,0x90,0xed,0xf0,0x7f,0x80,0x7e,0x08,0x12,0x27, ++0xde,0xec,0x54,0x03,0xfc,0xec,0x44,0xc0,0xfc,0x90,0x90,0xef,0x12,0x2a,0x7f,0x90, ++0x90,0xef,0x12,0x43,0x09,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0x80,0x7e,0x08,0x12, ++0x2f,0xd9,0x90,0x90,0xf6,0xe0,0x30,0xe1,0x19,0x7d,0x0c,0x7f,0x47,0x71,0xee,0x90, ++0x00,0x48,0xe0,0x44,0x0c,0xfd,0x7f,0x48,0x71,0xee,0x90,0x00,0x46,0xe0,0x44,0x10, ++0x80,0x1c,0x90,0x00,0x47,0xe0,0x54,0xf3,0xfd,0x7f,0x47,0x71,0xee,0x90,0x00,0x48, ++0xe0,0x54,0xf3,0xfd,0x7f,0x48,0x71,0xee,0x90,0x00,0x46,0xe0,0x54,0xef,0xfd,0x7f, ++0x46,0x71,0xee,0xe4,0x90,0x90,0xf3,0xf0,0x22,0x90,0x01,0x3c,0x74,0xff,0xf0,0xa3, ++0xf0,0xa3,0xf0,0x90,0x01,0x34,0xf0,0xa3,0xf0,0xa3,0xf0,0xa3,0xf0,0xfd,0x7f,0x54, ++0x71,0xee,0x7d,0xff,0x7f,0x55,0x71,0xee,0x7d,0xff,0x7f,0x56,0x71,0xee,0x7d,0xff, ++0x7f,0x57,0x61,0xee,0x90,0x01,0x30,0xe4,0xf0,0xa3,0xf0,0xa3,0xf0,0xa3,0xf0,0x90, ++0x01,0x38,0xf0,0xa3,0xf0,0xa3,0xf0,0xa3,0xf0,0xfd,0x7f,0x50,0x71,0xee,0xe4,0xfd, ++0x7f,0x51,0x71,0xee,0xe4,0xfd,0x7f,0x52,0x71,0xee,0xe4,0xfd,0x7f,0x53,0x61,0xee, ++0xd3,0x10,0xaf,0x01,0xc3,0xc0,0xd0,0x90,0x91,0x22,0xed,0xf0,0x90,0x91,0x21,0xef, ++0xf0,0xd3,0x94,0x07,0x50,0x4e,0xa3,0xe0,0x70,0x1a,0x90,0x91,0x21,0xe0,0xff,0x74, ++0x01,0xa8,0x07,0x08,0x80,0x02,0xc3,0x33,0xd8,0xfc,0xf4,0xff,0x90,0x00,0x47,0xe0, ++0x5f,0xf0,0x80,0x17,0x90,0x91,0x21,0xe0,0xff,0x74,0x01,0xa8,0x07,0x08,0x80,0x02, ++0xc3,0x33,0xd8,0xfc,0xff,0x90,0x00,0x47,0xe0,0x4f,0xf0,0x51,0xe6,0x90,0x91,0x21, ++0xe0,0xff,0x74,0x01,0xa8,0x07,0x08,0x80,0x02,0xc3,0x33,0xd8,0xfc,0xf4,0xff,0x90, ++0x00,0x46,0x80,0x59,0x90,0x91,0x21,0xe0,0x24,0xf8,0xf0,0xa3,0xe0,0x70,0x1d,0x90, ++0x91,0x21,0xe0,0xff,0x74,0x01,0xa8,0x07,0x08,0x80,0x02,0xc3,0x33,0xd8,0xfc,0xc4, ++0x54,0xf0,0xf4,0xff,0x90,0x00,0x43,0xe0,0x5f,0xf0,0x80,0x1a,0x90,0x91,0x21,0xe0, ++0xff,0x74,0x01,0xa8,0x07,0x08,0x80,0x02,0xc3,0x33,0xd8,0xfc,0xc4,0x54,0xf0,0xff, ++0x90,0x00,0x43,0xe0,0x4f,0xf0,0x51,0xe6,0x90,0x91,0x21,0xe0,0xff,0x74,0x01,0xa8, ++0x07,0x08,0x80,0x02,0xc3,0x33,0xd8,0xfc,0xf4,0xff,0x90,0x00,0x43,0xe0,0x5f,0xf0, ++0x51,0xe6,0xd0,0xd0,0x92,0xaf,0x22,0x90,0x00,0x49,0xe0,0x90,0x91,0x9f,0xf0,0xe0, ++0x54,0x0f,0xf0,0x44,0xf0,0xfd,0x7f,0x49,0x71,0xee,0x90,0x91,0x9f,0xe0,0x44,0xb0, ++0xfd,0x7f,0x49,0x61,0xee,0x12,0x47,0xe6,0xbf,0x01,0x10,0x90,0x02,0x09,0xe0,0xff, ++0x7d,0x01,0x12,0x48,0x22,0x90,0x04,0x1f,0x74,0x20,0xf0,0x22,0x75,0x28,0x33,0xe4, ++0xf5,0x29,0x75,0x2a,0x07,0xf5,0x2b,0x90,0x01,0x30,0xe5,0x28,0xf0,0xa3,0xe5,0x29, ++0xf0,0xa3,0xe5,0x2a,0xf0,0xa3,0xe5,0x2b,0xf0,0x22,0xe4,0x90,0x91,0x0e,0xf0,0xa3, ++0xf0,0x75,0x8e,0x02,0xf1,0x25,0xd1,0xe8,0x90,0x91,0x4f,0xef,0xf0,0xf1,0x0b,0x90, ++0x91,0x51,0xef,0xf0,0xf1,0x60,0x90,0x91,0x3d,0xee,0xf0,0xa3,0xef,0xf0,0xe4,0xf5, ++0x57,0xf1,0x02,0x12,0x61,0xc4,0x12,0x32,0x3d,0x12,0x44,0xff,0x11,0x0c,0xf1,0x36, ++0xd1,0xfb,0xd1,0xd0,0x12,0x44,0xfe,0x31,0x13,0x12,0x44,0xf4,0x12,0x6e,0x09,0x90, ++0x91,0x10,0xe5,0xd9,0xf0,0x12,0x4e,0xb9,0xc2,0xaf,0x90,0x00,0x80,0xe0,0x44,0x40, ++0xf0,0x12,0x4a,0xe6,0x75,0xe8,0x03,0x43,0xa8,0x85,0xd2,0xaf,0x90,0x91,0x0e,0xe0, ++0x64,0x01,0xf0,0x24,0x2a,0x90,0x01,0xc4,0xf0,0x74,0x50,0xa3,0xf0,0xe5,0x57,0x30, ++0xe2,0x10,0x12,0x5f,0xf0,0xbf,0x01,0x0a,0xc2,0xaf,0x53,0x57,0xfb,0xd2,0xaf,0x12, ++0x71,0x97,0xe5,0x57,0x30,0xe4,0x0a,0xc2,0xaf,0x53,0x57,0xef,0xd2,0xaf,0x12,0x60, ++0x2d,0x90,0x90,0xf7,0xe0,0x70,0x03,0x12,0x70,0x74,0x11,0xe7,0x90,0x91,0x3f,0xe0, ++0x90,0x01,0xba,0xf0,0x80,0xb6,0xe4,0x90,0x91,0x55,0xf0,0x90,0x91,0x53,0xe0,0x54, ++0x7f,0xf0,0xa3,0x74,0x0a,0xf0,0x22,0x90,0x06,0x34,0xe0,0x60,0x25,0x14,0x70,0x1b, ++0x7b,0x01,0x7a,0x06,0x79,0x35,0x7f,0xf9,0x7e,0x01,0x12,0x67,0xe4,0xbf,0x01,0x09, ++0x90,0x06,0x35,0xe0,0x54,0x0f,0xf0,0x80,0x04,0x80,0x00,0xe1,0x17,0xe4,0x90,0x06, ++0x34,0xf0,0x22,0x90,0x91,0x56,0xe0,0x54,0xfe,0xf0,0xe0,0x54,0x7f,0xf0,0x90,0x01, ++0x17,0xe0,0xfe,0x90,0x01,0x16,0xe0,0x7c,0x00,0x24,0x00,0xff,0xec,0x3e,0x90,0x91, ++0x5c,0xf0,0xa3,0xef,0xf0,0x90,0x01,0x04,0xe0,0x54,0x0f,0x90,0x91,0x1c,0xf0,0xe0, ++0xff,0x74,0x40,0x7e,0x00,0xa8,0x07,0x08,0x80,0x05,0xc3,0x33,0xce,0x33,0xce,0xd8, ++0xf9,0x90,0x91,0x5b,0xf0,0xee,0x90,0x91,0x5a,0xf0,0x90,0x91,0x5e,0xe0,0x54,0xfe, ++0xf0,0xe0,0x54,0xfd,0xf0,0xe0,0x54,0xfb,0xf0,0xe0,0x54,0xf7,0xf0,0xe0,0x54,0xef, ++0xf0,0xe0,0x54,0xdf,0xf0,0xe0,0x54,0xbf,0xf0,0xe0,0x54,0x7f,0xf0,0xe4,0xa3,0xf0, ++0xa3,0xf0,0xa3,0xe0,0x54,0xfe,0xf0,0xe0,0x54,0xfd,0xf0,0xe0,0x54,0xf7,0xf0,0x22, ++0xd3,0x10,0xaf,0x01,0xc3,0xc0,0xd0,0x12,0x29,0xd9,0x54,0x01,0xff,0x90,0x91,0x56, ++0xe0,0x54,0xfe,0x4f,0xf0,0x90,0x00,0x01,0x12,0x42,0x20,0x90,0x91,0x57,0xf0,0x90, ++0x00,0x02,0x12,0x42,0x20,0x90,0x91,0x58,0xf0,0x90,0x91,0x56,0xe0,0x30,0xe0,0x1a, ++0x90,0x06,0x09,0xe0,0x54,0xfe,0xf0,0x90,0x02,0x86,0xe0,0x44,0x04,0xf0,0x43,0x57, ++0x04,0x7d,0x08,0xe4,0xff,0x12,0x36,0xe6,0x80,0x12,0x7d,0x08,0xe4,0xff,0x12,0x36, ++0x75,0x90,0x02,0x86,0xe0,0x54,0xfb,0xf0,0x31,0xf1,0x31,0x13,0xd0,0xd0,0x92,0xaf, ++0x22,0x90,0x06,0x90,0xe4,0xf0,0x21,0x5a,0x90,0x91,0x19,0x12,0x43,0x41,0xef,0x12, ++0x43,0x4a,0x52,0x30,0x01,0x52,0x39,0x02,0x52,0x5b,0x03,0x52,0x64,0x09,0x52,0x6c, ++0x0c,0x52,0x75,0x0d,0x52,0x7d,0x0e,0x52,0x8e,0x1a,0x52,0x96,0x2c,0x52,0x41,0x2d, ++0x52,0x4a,0x2e,0x52,0x9e,0x30,0x52,0x53,0x3b,0x52,0x86,0x3c,0x00,0x00,0x52,0xa6, ++0x90,0x91,0x19,0x12,0x43,0x21,0x02,0x64,0x72,0x90,0x91,0x19,0x12,0x43,0x21,0xc1, ++0xf5,0x90,0x91,0x19,0x12,0x43,0x21,0x02,0x65,0x8d,0x90,0x91,0x19,0x12,0x43,0x21, ++0x02,0x65,0xd5,0x90,0x91,0x19,0x12,0x43,0x21,0xe1,0x4b,0x90,0x91,0x19,0x12,0x43, ++0x21,0x02,0x66,0x0e,0x90,0x91,0x19,0x12,0x43,0x21,0x80,0x42,0x90,0x91,0x19,0x12, ++0x43,0x21,0x02,0x4c,0xab,0x90,0x91,0x19,0x12,0x43,0x21,0xe1,0x98,0x90,0x91,0x19, ++0x12,0x43,0x21,0x02,0x4d,0xe6,0x90,0x91,0x19,0x12,0x43,0x21,0x21,0x90,0x90,0x91, ++0x19,0x12,0x43,0x21,0xa1,0x9b,0x90,0x91,0x19,0x12,0x43,0x21,0x81,0x7a,0x90,0x91, ++0x19,0x12,0x43,0x21,0xe1,0x78,0x90,0x01,0xc6,0xe0,0x44,0x01,0xf0,0x22,0xd3,0x10, ++0xaf,0x01,0xc3,0xc0,0xd0,0x90,0x91,0x1c,0x12,0x43,0x41,0x90,0x91,0x1c,0x12,0x43, ++0x21,0x90,0x00,0x01,0x12,0x42,0x97,0xfa,0xe5,0xf0,0x24,0x00,0xff,0xe4,0x3a,0xfe, ++0x90,0x91,0x1c,0x12,0x43,0x21,0x90,0x00,0x01,0xee,0x8f,0xf0,0x12,0x42,0xcf,0x12, ++0x29,0xd9,0xff,0x60,0x2c,0xb5,0x72,0x16,0x90,0x91,0x1c,0x12,0x43,0x21,0x90,0x00, ++0x01,0x12,0x42,0x97,0x65,0x74,0x70,0x04,0xe5,0x73,0x65,0xf0,0x60,0x23,0x90,0x91, ++0x1c,0x12,0x43,0x21,0x90,0x00,0x01,0x12,0x42,0x97,0xff,0xae,0xf0,0x71,0x26,0x80, ++0x10,0x90,0x91,0x1c,0x12,0x43,0x21,0x12,0x29,0xd9,0x65,0x72,0x60,0x03,0x12,0x44, ++0xe8,0xd0,0xd0,0x92,0xaf,0x22,0x90,0x91,0x1f,0xee,0xf0,0xa3,0xef,0xf0,0x75,0x72, ++0x01,0x8e,0x73,0xf5,0x74,0xe4,0xfd,0x7f,0x0b,0x12,0x4f,0x10,0xe4,0xfd,0x7f,0x02, ++0x12,0x4f,0x10,0x71,0x6a,0xe4,0xff,0x71,0xcc,0xe4,0xf5,0x76,0x90,0x01,0xc9,0xe5, ++0x76,0xf0,0x90,0x91,0x1f,0xe0,0xfc,0xa3,0xe0,0xfd,0xec,0xfb,0x8d,0x44,0xe4,0xf5, ++0x45,0x7d,0x01,0x7f,0x60,0x7e,0x01,0x02,0x35,0xab,0x7f,0x0b,0x71,0xd9,0xef,0x65, ++0x75,0x60,0x10,0xe5,0x75,0xb4,0x01,0x05,0xe4,0xf5,0x75,0x80,0x03,0x75,0x75,0x01, ++0x7f,0x01,0x22,0x7f,0x00,0x22,0xe5,0x72,0x64,0x01,0x70,0x3f,0x71,0x6a,0xbf,0x01, ++0x04,0x7f,0x01,0x71,0xcc,0x90,0x00,0x46,0xe0,0x44,0x04,0xfd,0x7f,0x46,0x12,0x4b, ++0xee,0x90,0x00,0x44,0xe0,0x54,0xfb,0xfd,0x7f,0x44,0x12,0x4b,0xee,0x90,0x00,0x46, ++0xe0,0x54,0xfb,0xfd,0x7f,0x46,0x12,0x4b,0xee,0x7f,0x02,0x71,0xd9,0x8f,0x76,0x90, ++0x01,0xc9,0xe5,0x76,0xf0,0xb4,0x01,0x03,0x12,0x4f,0xd7,0x22,0x90,0x01,0xca,0xe5, ++0x75,0xf0,0xef,0x60,0x03,0x12,0x4f,0xd7,0x22,0xd3,0x10,0xaf,0x01,0xc3,0xc0,0xd0, ++0x90,0x91,0xa0,0xef,0xf0,0xd3,0x94,0x07,0x50,0x47,0xe0,0xff,0x74,0x01,0xa8,0x07, ++0x08,0x80,0x02,0xc3,0x33,0xd8,0xfc,0xf4,0xff,0x90,0x00,0x46,0xe0,0x5f,0xf0,0x12, ++0x4a,0xe6,0x90,0x91,0xa0,0xe0,0xfd,0x74,0x01,0x7e,0x00,0xa8,0x05,0x08,0x80,0x05, ++0xc3,0x33,0xce,0x33,0xce,0xd8,0xf9,0xff,0x90,0x00,0x44,0xe0,0xfb,0xe4,0xfe,0xef, ++0x5b,0xa8,0x05,0x08,0x80,0x06,0xce,0xa2,0xe7,0x13,0xce,0x13,0xd8,0xf8,0xff,0x80, ++0x44,0x90,0x91,0xa0,0xe0,0x24,0xf8,0xf0,0xe0,0xff,0x74,0x01,0xa8,0x07,0x08,0x80, ++0x02,0xc3,0x33,0xd8,0xfc,0x12,0x4a,0xde,0x90,0x91,0xa0,0xe0,0xfd,0x74,0x01,0x7e, ++0x00,0xa8,0x05,0x08,0x80,0x05,0xc3,0x33,0xce,0x33,0xce,0xd8,0xf9,0xff,0x90,0x00, ++0x42,0xe0,0xfb,0xe4,0xfe,0xef,0x5b,0xa8,0x05,0x08,0x80,0x06,0xce,0xa2,0xe7,0x13, ++0xce,0x13,0xd8,0xf8,0xff,0xd0,0xd0,0x92,0xaf,0x22,0xd3,0x10,0xaf,0x01,0xc3,0xc0, ++0xd0,0xe4,0xf5,0x10,0x75,0x11,0x04,0xf5,0x12,0xf5,0x14,0xf5,0x15,0x90,0x02,0x09, ++0xe0,0xff,0x12,0x29,0xd9,0xfe,0xef,0x2e,0xf5,0x13,0x30,0xe0,0x08,0x75,0x0e,0x00, ++0x75,0x0f,0x80,0x80,0x05,0xe4,0xf5,0x0e,0xf5,0x0f,0xe5,0x13,0xc3,0x13,0x90,0xfd, ++0x10,0xf0,0x74,0x20,0x25,0x10,0xf5,0x10,0xad,0x0f,0xe5,0x10,0x2d,0xff,0x24,0x01, ++0xf5,0x82,0xe4,0x34,0xfc,0xf5,0x83,0xe0,0x90,0x91,0x47,0xf0,0x74,0x02,0x2f,0xf5, ++0x82,0xe4,0x34,0xfc,0xf5,0x83,0xe0,0xfe,0xe5,0x10,0x2d,0x24,0x03,0xf5,0x82,0xe4, ++0x34,0xfc,0xf5,0x83,0xe0,0x24,0x00,0xff,0xe4,0x3e,0x90,0x91,0x48,0xf0,0xa3,0xef, ++0xf0,0x7f,0x04,0xe5,0x10,0x25,0x0f,0x2f,0x24,0x00,0xf5,0x82,0xe4,0x34,0xfc,0xf5, ++0x83,0xe0,0xfe,0x74,0x46,0x2f,0xf5,0x82,0xe4,0x34,0x91,0xf5,0x83,0xee,0xf0,0x0f, ++0xbf,0x08,0xe0,0x12,0x66,0x56,0xef,0x70,0x3f,0x90,0x01,0xc3,0xe0,0x60,0x25,0xc3, ++0xe5,0x15,0x94,0xe8,0xe5,0x14,0x94,0x03,0x40,0x09,0x90,0x01,0xc6,0xe0,0x44,0x10, ++0xf0,0x80,0x63,0x05,0x15,0xe5,0x15,0x70,0x02,0x05,0x14,0x7f,0x0a,0x7e,0x00,0x12, ++0x37,0x54,0x80,0xd5,0x90,0x01,0xc6,0xe0,0x90,0x01,0xc3,0x30,0xe2,0x05,0x74,0xfe, ++0xf0,0x80,0x43,0x74,0xff,0xf0,0x80,0x3e,0xe5,0x10,0xb4,0x78,0x23,0xe4,0xf5,0x10, ++0x05,0x13,0xe5,0x0f,0x64,0x80,0x45,0x0e,0x70,0x06,0xf5,0x0e,0xf5,0x0f,0x80,0x06, ++0x75,0x0e,0x00,0x75,0x0f,0x80,0xe5,0x13,0xc3,0x13,0x90,0xfd,0x10,0xf0,0x80,0x06, ++0x74,0x08,0x25,0x10,0xf5,0x10,0xe5,0x12,0x15,0x12,0x70,0x02,0x15,0x11,0xe5,0x12, ++0x45,0x11,0x60,0x02,0x81,0xb8,0xd0,0xd0,0x92,0xaf,0x22,0x90,0x91,0x1c,0x12,0x43, ++0x41,0x12,0x29,0xd9,0xff,0x54,0x01,0xfe,0x90,0x91,0x5e,0xe0,0x54,0xfe,0x4e,0xf0, ++0xef,0x54,0x04,0xff,0xe0,0x54,0xfb,0x4f,0xf0,0x12,0x29,0xd9,0xff,0x54,0x02,0xfe, ++0x90,0x91,0x5e,0xe0,0x54,0xfd,0x4e,0xf0,0xef,0x54,0x08,0xff,0xe0,0x54,0xf7,0x4f, ++0xf0,0x12,0x29,0xd9,0xff,0x54,0x10,0xfe,0x90,0x91,0x5e,0xe0,0x54,0xef,0x4e,0xf0, ++0xef,0x54,0x20,0xff,0xe0,0x54,0xdf,0x4f,0xf0,0x12,0x29,0xd9,0xff,0x54,0x40,0xfe, ++0x90,0x91,0x5e,0xe0,0x54,0xbf,0x4e,0xf0,0xef,0x54,0x80,0xff,0xe0,0x54,0x7f,0x4f, ++0xf0,0x90,0x00,0x02,0x12,0x42,0x20,0x90,0x91,0x60,0xf0,0x90,0x00,0x01,0x12,0x42, ++0x20,0x90,0x91,0x5f,0xf0,0x90,0x00,0x03,0x12,0x42,0x20,0xff,0x54,0x01,0xfe,0x90, ++0x91,0x61,0xe0,0x54,0xfe,0x4e,0xf0,0xef,0x54,0x02,0xff,0xe0,0x54,0xfd,0x4f,0xf0, ++0x90,0x00,0x03,0x12,0x42,0x20,0x54,0x04,0xff,0x90,0x91,0x61,0xe0,0x54,0xfb,0x4f, ++0xf0,0x90,0x91,0x5e,0xe0,0x54,0x01,0x90,0x01,0xb8,0xf0,0x90,0x91,0x5e,0xe0,0xff, ++0xc4,0x13,0x54,0x01,0x90,0x01,0xb9,0xf0,0x90,0x91,0x61,0xe0,0x54,0x01,0x90,0x01, ++0xba,0xf0,0xa3,0x74,0xff,0xf0,0x12,0x29,0xd9,0x20,0xe0,0x02,0x21,0xf1,0xe4,0xfd, ++0x7f,0x81,0x12,0x4b,0xee,0x90,0x91,0x1c,0x12,0x43,0x21,0x12,0x29,0xd9,0xff,0xc3, ++0x13,0x30,0xe0,0x07,0x90,0x06,0x90,0xe0,0x44,0x02,0xf0,0xef,0x13,0x13,0x54,0x3f, ++0x30,0xe0,0x07,0x90,0x06,0x90,0xe0,0x44,0x04,0xf0,0x12,0x29,0xd9,0x13,0x13,0x13, ++0x54,0x1f,0x30,0xe0,0x07,0x90,0x06,0x90,0xe0,0x44,0x08,0xf0,0x90,0x91,0x61,0xe0, ++0x30,0xe0,0x1c,0x90,0x91,0x5e,0xe0,0xc4,0x13,0x54,0x07,0x30,0xe0,0x07,0xa3,0xe0, ++0xff,0xe4,0xfd,0x80,0x07,0x90,0x91,0x5f,0xe0,0xff,0x7d,0x01,0x12,0x4a,0xf6,0x22, ++0x75,0x30,0x1f,0x75,0x31,0x01,0xe4,0xf5,0x32,0x90,0x01,0x38,0xe5,0x30,0xf0,0xa3, ++0xe5,0x31,0xf0,0xa3,0xe5,0x32,0xf0,0x22,0x90,0x00,0x02,0xe0,0x54,0xe0,0x7f,0x01, ++0x60,0x02,0x7f,0x00,0x22,0x12,0x29,0xd9,0xf5,0x6d,0x22,0x90,0x01,0x64,0x74,0xa0, ++0xf0,0x22,0x90,0x91,0x51,0xe0,0x90,0x90,0xe8,0xf0,0x22,0x90,0x00,0xf3,0xe0,0x7f, ++0x00,0x30,0xe3,0x02,0x7f,0x01,0x22,0x90,0x06,0x34,0x74,0xff,0xf0,0xe4,0xa3,0xf0, ++0xa3,0xf0,0xa3,0xf0,0x22,0xe4,0x90,0x91,0x4e,0xf0,0x90,0x00,0x80,0xe0,0x44,0x80, ++0xfd,0x7f,0x80,0x02,0x4b,0xee,0x90,0x00,0xf3,0xe0,0x30,0xe2,0x0d,0x90,0x05,0x41, ++0x74,0x10,0xf0,0x90,0x05,0x5a,0xf0,0xa3,0xe4,0xf0,0x22,0x12,0x29,0xd9,0x60,0x02, ++0x80,0x01,0xe4,0x90,0x91,0x31,0xf0,0x90,0x91,0x31,0xe0,0x90,0x01,0xe7,0xf0,0x22, ++0x90,0x91,0x51,0xe0,0xb4,0x01,0x0c,0x90,0x00,0xf2,0xe0,0x30,0xe7,0x05,0x7e,0xfd, ++0x7f,0x33,0x22,0x7e,0xfd,0x7f,0x2f,0x22,0x12,0x29,0xd9,0xff,0x54,0x01,0xfe,0x90, ++0x91,0x53,0xe0,0x54,0xfe,0x4e,0xf0,0xef,0xc3,0x13,0x30,0xe0,0x0a,0x90,0x00,0x01, ++0x12,0x42,0x20,0x90,0x91,0x54,0xf0,0x22,0x90,0x00,0x02,0x12,0x42,0x20,0x90,0x90, ++0xf7,0xf0,0xe0,0x60,0x04,0xe0,0xf4,0x70,0x21,0xa2,0xaf,0xe4,0x33,0xf5,0x0e,0xc2, ++0xaf,0x90,0x00,0x47,0xe0,0x54,0xfb,0xfd,0x7f,0x47,0x12,0x4b,0xee,0x7d,0x40,0x7f, ++0x01,0x12,0x36,0xaf,0xe5,0x0e,0x24,0xff,0x92,0xaf,0x22,0xc0,0xe0,0xc0,0xf0,0xc0, ++0x83,0xc0,0x82,0xc0,0xd0,0x75,0xd0,0x00,0xc0,0x00,0xc0,0x01,0xc0,0x02,0xc0,0x03, ++0xc0,0x04,0xc0,0x05,0xc0,0x06,0xc0,0x07,0x90,0x01,0xc4,0x74,0xcb,0xf0,0x74,0x57, ++0xa3,0xf0,0x90,0x01,0x34,0xe0,0x55,0x28,0xf5,0x2c,0x90,0x01,0x36,0xe0,0x55,0x2a, ++0xf5,0x2e,0xa3,0xe0,0x55,0x2b,0xf5,0x2f,0xe5,0x2c,0x30,0xe0,0x5a,0x90,0x01,0x34, ++0x74,0x01,0xf0,0x85,0xd9,0x54,0xe5,0x70,0x14,0x24,0xfd,0x50,0x02,0x80,0x48,0x90, ++0x91,0x3b,0xe0,0x60,0x3a,0x90,0x01,0x5b,0xe4,0xf0,0x90,0x01,0x3c,0x74,0x04,0xf0, ++0x51,0x30,0xef,0x64,0x01,0x70,0x30,0x90,0x91,0x66,0xf0,0x90,0x91,0x2d,0xe0,0x90, ++0x91,0x67,0xf0,0xe4,0xfb,0xfd,0x7f,0x58,0x7e,0x01,0x12,0x44,0x59,0x90,0x01,0x5b, ++0x74,0x05,0xf0,0x90,0x06,0x92,0x74,0x01,0xf0,0x90,0x91,0x37,0xf0,0x80,0x08,0x51, ++0x30,0xbf,0x01,0x03,0x12,0x44,0xc2,0xe5,0x2c,0x30,0xe1,0x20,0x90,0x01,0x34,0x74, ++0x02,0xf0,0x85,0xd1,0x58,0x85,0xd2,0x59,0x85,0xd3,0x5a,0x85,0xd4,0x5b,0x85,0xd5, ++0x5c,0x85,0xd6,0x5d,0x85,0xd7,0x5e,0x85,0xd9,0x5f,0x71,0x5c,0xe5,0x2c,0x30,0xe3, ++0x10,0x90,0x01,0x34,0x74,0x08,0xf0,0x90,0x91,0x56,0xe0,0x30,0xe0,0x03,0x43,0x57, ++0x04,0xe5,0x2c,0x30,0xe4,0x09,0x90,0x01,0x34,0x74,0x10,0xf0,0x43,0x57,0x10,0xe5, ++0x2c,0x30,0xe5,0x26,0x90,0x01,0xcf,0xe0,0x30,0xe5,0x1f,0xe0,0x54,0xdf,0xf0,0x90, ++0x01,0x34,0x74,0x20,0xf0,0x75,0xa8,0x00,0x75,0xe8,0x00,0x12,0x4e,0xe4,0x90,0x00, ++0x03,0xe0,0x54,0xfb,0xf0,0x12,0x4a,0xe6,0x80,0xfe,0xe5,0x2c,0x30,0xe6,0x06,0x90, ++0x01,0x34,0x74,0x40,0xf0,0xe5,0x2e,0x30,0xe0,0x13,0x90,0x91,0x50,0x74,0x01,0xf0, ++0x90,0x01,0x36,0xf0,0x91,0x23,0x51,0x87,0x90,0x91,0x50,0xe4,0xf0,0xe5,0x2e,0x30, ++0xe1,0x3c,0x90,0x01,0x36,0x74,0x02,0xf0,0x43,0x57,0x40,0x90,0x01,0x02,0xe0,0x54, ++0x03,0x64,0x01,0x70,0x29,0x90,0x01,0x37,0xe0,0x30,0xe0,0x0a,0x74,0x01,0xf0,0x90, ++0x91,0x40,0xe4,0xf0,0x80,0x18,0x90,0x91,0x40,0xe0,0x04,0xf0,0xe0,0xc3,0x94,0x0a, ++0x40,0x0c,0xe4,0xf0,0x90,0x04,0x19,0xe0,0x30,0xe0,0x03,0x12,0x4f,0xf5,0xe5,0x2e, ++0x30,0xe2,0x19,0x90,0x01,0x36,0x74,0x04,0xf0,0x90,0x91,0x3a,0xe4,0xf0,0x90,0x05, ++0x58,0x74,0x03,0xf0,0x51,0xd8,0x90,0x91,0x3f,0xe0,0x04,0xf0,0xe5,0x2e,0x30,0xe3, ++0x28,0x90,0x01,0x36,0x74,0x08,0xf0,0xe5,0x6d,0x64,0x01,0x70,0x1c,0xe5,0x70,0x60, ++0x18,0x90,0x01,0x57,0xe4,0xf0,0x90,0x01,0x3c,0x74,0x02,0xf0,0x90,0x91,0x66,0xe4, ++0x12,0x44,0x49,0x90,0x01,0x57,0x74,0x05,0xf0,0xe5,0x2e,0x30,0xe4,0x2b,0x90,0x01, ++0x36,0x74,0x10,0xf0,0xe5,0x6d,0xb4,0x01,0x20,0xe5,0x70,0x60,0x1c,0x90,0x01,0x57, ++0xe4,0xf0,0x90,0x01,0x3c,0x74,0x02,0xf0,0x90,0x91,0x3c,0xe4,0xf0,0x53,0x71,0xfd, ++0xe5,0x71,0x54,0x07,0x70,0x03,0x12,0x44,0xc2,0xe5,0x2e,0x30,0xe5,0x1f,0x90,0x01, ++0x36,0x74,0x20,0xf0,0xe5,0x6d,0xb4,0x01,0x14,0xe5,0x70,0x60,0x10,0x90,0x91,0x3b, ++0xe0,0x64,0x02,0x60,0x05,0x12,0x44,0xc8,0x80,0x03,0x12,0x44,0x77,0xe5,0x2e,0x30, ++0xe6,0x1b,0x90,0x01,0x36,0x74,0x40,0xf0,0xe5,0x6d,0xb4,0x01,0x10,0xe5,0x70,0x60, ++0x0c,0x53,0x71,0xfe,0xe5,0x71,0x54,0x07,0x70,0x03,0x12,0x44,0xc2,0xe5,0x2f,0x30, ++0xe1,0x08,0x90,0x01,0x37,0x74,0x02,0xf0,0x71,0x7e,0x74,0xcb,0x04,0x90,0x01,0xc4, ++0xf0,0x74,0x57,0xa3,0xf0,0xd0,0x07,0xd0,0x06,0xd0,0x05,0xd0,0x04,0xd0,0x03,0xd0, ++0x02,0xd0,0x01,0xd0,0x00,0xd0,0xd0,0xd0,0x82,0xd0,0x83,0xd0,0xf0,0xd0,0xe0,0x32, ++0x90,0x04,0x1b,0xe0,0x54,0x7f,0x64,0x7f,0x7f,0x01,0x60,0x02,0x7f,0x00,0x22,0x51, ++0x30,0xef,0x64,0x01,0x60,0x08,0x90,0x01,0xb9,0x74,0x01,0xf0,0x80,0x30,0x90,0x91, ++0x37,0xe0,0x60,0x08,0x90,0x01,0xb9,0x74,0x02,0xf0,0x80,0x22,0x90,0x91,0x36,0xe0, ++0x60,0x08,0x90,0x01,0xb9,0x74,0x04,0xf0,0x80,0x14,0xe5,0x6f,0x54,0x0f,0xd3,0x94, ++0x04,0x40,0x08,0x90,0x01,0xb9,0x74,0x08,0xf0,0x80,0x03,0x7f,0x01,0x22,0x90,0x01, ++0xb8,0x74,0x08,0xf0,0x7f,0x00,0x22,0x90,0x91,0x53,0xe0,0x30,0xe0,0x49,0xe5,0x6d, ++0x64,0x01,0x70,0x43,0x90,0x91,0x52,0xe0,0x04,0xf0,0xe5,0x70,0x64,0x03,0x60,0x05, ++0xe5,0x70,0xb4,0x06,0x0d,0x90,0x91,0x52,0xe0,0xff,0x74,0x01,0xd3,0x9f,0x50,0x14, ++0x80,0x07,0x90,0x91,0x52,0xe0,0xb4,0x0a,0x0b,0x90,0x91,0x55,0xe0,0x04,0xf0,0xe4, ++0x90,0x91,0x52,0xf0,0x90,0x91,0x55,0xe0,0xff,0x90,0x91,0x54,0xe0,0xb5,0x07,0x07, ++0x71,0x4e,0xe4,0x90,0x91,0x55,0xf0,0x22,0xe5,0x6d,0x64,0x01,0x70,0x63,0xe5,0x70, ++0x60,0x5f,0xe5,0x70,0x64,0x02,0x60,0x06,0xe5,0x70,0x64,0x05,0x70,0x27,0x90,0x06, ++0xab,0xe0,0x90,0x91,0x27,0xf0,0x90,0x06,0xaa,0xe0,0x90,0x91,0x39,0xf0,0x90,0x91, ++0x27,0xe0,0x70,0x07,0x90,0x91,0x39,0xe0,0xff,0x80,0x05,0x90,0x91,0x27,0xe0,0xff, ++0x90,0x91,0x27,0xef,0xf0,0x90,0x91,0x29,0xe0,0x60,0x03,0xe0,0x14,0xf0,0xe4,0x90, ++0x91,0x28,0xf0,0x90,0x01,0x57,0xf0,0x90,0x01,0x3c,0x74,0x02,0xf0,0x53,0x71,0xfd, ++0x53,0x71,0xef,0xe5,0x70,0x14,0x24,0xfd,0x50,0x02,0x80,0x03,0x12,0x45,0xc7,0x71, ++0x42,0x22,0xd3,0x10,0xaf,0x01,0xc3,0xc0,0xd0,0xd0,0xd0,0x92,0xaf,0x22,0xe5,0x6e, ++0x30,0xe3,0x04,0xe4,0xff,0x80,0x02,0x7f,0x01,0x02,0x47,0xc9,0x90,0x91,0x08,0xe0, ++0x54,0xf0,0x44,0x03,0xf0,0x54,0x0f,0x44,0x80,0xf0,0x7b,0x00,0x7a,0x00,0x79,0x58, ++0x90,0x91,0x71,0x12,0x43,0x41,0x0b,0x7a,0x91,0x79,0x08,0x02,0x46,0xb7,0x90,0x91, ++0x80,0x12,0x2a,0x8b,0x00,0x00,0x00,0x00,0xe5,0x70,0x14,0x24,0xfd,0x50,0x02,0x80, ++0x21,0x90,0x91,0x3b,0xe0,0x60,0x06,0x7d,0x01,0x7f,0x0c,0x80,0x0d,0xe5,0x6e,0x54, ++0x0f,0xc3,0x94,0x04,0x50,0x07,0x7d,0x01,0x7f,0x04,0x12,0x47,0x27,0xe4,0xff,0x12, ++0x48,0xb3,0x22,0x51,0x30,0xef,0x64,0x01,0x60,0x08,0x90,0x01,0xb9,0x74,0x01,0xf0, ++0x80,0x58,0xe5,0x71,0x54,0x03,0x60,0x08,0x90,0x01,0xb9,0x74,0x02,0xf0,0x80,0x4a, ++0xe5,0x6f,0x54,0x0f,0xd3,0x94,0x02,0x40,0x08,0x90,0x01,0xb9,0x74,0x04,0xf0,0x80, ++0x39,0xe5,0x71,0x30,0xe2,0x08,0x90,0x01,0xb9,0x74,0x08,0xf0,0x80,0x2c,0xe5,0x71, ++0x30,0xe4,0x08,0x90,0x01,0xb9,0x74,0x10,0xf0,0x80,0x1f,0x90,0x91,0x29,0xe0,0x60, ++0x08,0x90,0x01,0xb9,0x74,0x20,0xf0,0x80,0x11,0x90,0x91,0x31,0xe0,0x60,0x08,0x90, ++0x01,0xb9,0x74,0x80,0xf0,0x80,0x03,0x7f,0x01,0x22,0x90,0x01,0xb8,0x74,0x04,0xf0, ++0x7f,0x00,0x22,0xe4,0xfb,0x90,0x91,0x78,0x12,0x2a,0x8b,0x00,0x00,0x00,0x00,0xe5, ++0x70,0x70,0x02,0x81,0xb5,0xe5,0x6d,0x64,0x01,0x70,0x7a,0xe5,0x70,0x14,0x60,0x2b, ++0x24,0xfd,0x60,0x27,0x24,0x02,0x24,0xfb,0x50,0x02,0x80,0x21,0x90,0x91,0x27,0xe0, ++0x14,0xf0,0xe0,0x60,0x04,0xa3,0xe0,0x60,0x14,0x90,0x91,0x27,0xe0,0x70,0x08,0x90, ++0x91,0x39,0xe0,0x90,0x91,0x27,0xf0,0x7b,0x01,0x80,0x02,0x7b,0x01,0xeb,0x60,0x45, ++0x43,0x71,0x10,0xe4,0x90,0x91,0x66,0xf0,0x90,0x91,0x3a,0xe0,0x75,0xf0,0x05,0xa4, ++0xff,0x90,0x91,0x34,0xe0,0x2f,0x12,0x44,0x4e,0x90,0x01,0x57,0x74,0x05,0xf0,0xe5, ++0x6e,0x54,0x0f,0xc3,0x94,0x04,0x50,0x07,0x7d,0x01,0x7f,0x04,0x12,0x47,0x27,0x90, ++0x91,0x2e,0xe0,0x60,0x10,0x90,0x91,0x2c,0xe0,0x90,0x07,0x78,0x60,0x04,0x74,0x0d, ++0xf0,0x22,0x74,0x09,0xf0,0x22,0xc0,0xe0,0xc0,0xf0,0xc0,0x83,0xc0,0x82,0xc0,0xd0, ++0x75,0xd0,0x00,0xc0,0x00,0xc0,0x01,0xc0,0x02,0xc0,0x03,0xc0,0x04,0xc0,0x05,0xc0, ++0x06,0xc0,0x07,0x90,0x01,0xc4,0x74,0xb6,0xf0,0x74,0x5c,0xa3,0xf0,0x53,0x91,0xef, ++0x90,0x00,0x51,0xe0,0xff,0x90,0x00,0x55,0xe0,0x5f,0xf5,0x3d,0x90,0x00,0x52,0xe0, ++0xff,0x90,0x00,0x56,0xe0,0x5f,0xf5,0x3e,0xe5,0x3d,0x30,0xe4,0x06,0x90,0x00,0x55, ++0x74,0x10,0xf0,0xe5,0x3d,0x30,0xe5,0x06,0x90,0x00,0x55,0x74,0x20,0xf0,0xe5,0x3d, ++0x30,0xe6,0x1b,0x90,0x00,0x55,0x74,0x40,0xf0,0x90,0x90,0xf6,0xe0,0x54,0x03,0xff, ++0xbf,0x03,0x0b,0x90,0x90,0xf3,0xe0,0x60,0x05,0x7f,0x01,0x12,0x4c,0x03,0xe5,0x3d, ++0x30,0xe7,0x15,0x90,0x00,0x55,0x74,0x80,0xf0,0x90,0x90,0xf6,0xe0,0x54,0x03,0xff, ++0xbf,0x03,0x05,0x7f,0x02,0x12,0x4c,0x03,0xe5,0x3e,0x30,0xe0,0x06,0x90,0x00,0x56, ++0x74,0x01,0xf0,0xe5,0x3e,0x30,0xe1,0x06,0x90,0x00,0x56,0x74,0x02,0xf0,0xe5,0x3e, ++0x30,0xe2,0x06,0x90,0x00,0x56,0x74,0x04,0xf0,0xe5,0x3e,0x30,0xe3,0x06,0x90,0x00, ++0x56,0x74,0x08,0xf0,0x90,0x01,0xc4,0x74,0xb6,0xf0,0x74,0x5c,0xa3,0xf0,0xd0,0x07, ++0xd0,0x06,0xd0,0x05,0xd0,0x04,0xd0,0x03,0xd0,0x02,0xd0,0x01,0xd0,0x00,0xd0,0xd0, ++0xd0,0x82,0xd0,0x83,0xd0,0xf0,0xd0,0xe0,0x32,0xc0,0xe0,0xc0,0xf0,0xc0,0x83,0xc0, ++0x82,0xc0,0xd0,0x75,0xd0,0x00,0xc0,0x00,0xc0,0x01,0xc0,0x02,0xc0,0x03,0xc0,0x04, ++0xc0,0x05,0xc0,0x06,0xc0,0x07,0x75,0x0d,0x00,0x90,0x01,0xc4,0x74,0x99,0xf0,0x74, ++0x5d,0xa3,0xf0,0x53,0x91,0xdf,0x90,0x01,0x3c,0xe0,0x55,0x30,0xf5,0x34,0xa3,0xe0, ++0x55,0x31,0xf5,0x35,0xa3,0xe0,0x55,0x32,0xf5,0x36,0xa3,0xe0,0x55,0x33,0xf5,0x37, ++0xe5,0x34,0x30,0xe0,0x06,0x90,0x01,0x3c,0x74,0x01,0xf0,0xe5,0x34,0x30,0xe1,0x08, ++0x90,0x01,0x3c,0x74,0x02,0xf0,0xf1,0x57,0xe5,0x34,0x30,0xe2,0x3a,0x90,0x01,0x3c, ++0x74,0x04,0xf0,0x90,0x06,0x92,0xe0,0x30,0xe0,0x25,0x90,0x91,0x66,0xe4,0xf0,0x90, ++0x91,0x2d,0xe0,0x90,0x91,0x67,0xf0,0xe4,0xfb,0xfd,0x7f,0x58,0x7e,0x01,0x12,0x44, ++0x59,0x90,0x01,0x5b,0x74,0x05,0xf0,0x90,0x06,0x92,0x74,0x01,0xf0,0x80,0x08,0x90, ++0x91,0x37,0xe4,0xf0,0x12,0x44,0xc2,0xe5,0x34,0x30,0xe3,0x3a,0x90,0x01,0x3c,0x74, ++0x08,0xf0,0x90,0x06,0x92,0xe0,0x30,0xe1,0x25,0x90,0x91,0x66,0xe4,0xf0,0x90,0x91, ++0x2d,0xe0,0x90,0x91,0x67,0xf0,0xe4,0xfb,0xfd,0x7f,0x5c,0x7e,0x01,0x12,0x44,0x59, ++0x90,0x01,0x5f,0x74,0x05,0xf0,0x90,0x06,0x92,0x74,0x02,0xf0,0x80,0x08,0x90,0x91, ++0x36,0xe4,0xf0,0x12,0x44,0xc2,0xe5,0x34,0x30,0xe4,0x09,0x90,0x01,0x3c,0x74,0x10, ++0xf0,0x12,0x53,0x86,0xe5,0x34,0x30,0xe5,0x09,0x90,0x01,0x3c,0x74,0x20,0xf0,0x12, ++0x6e,0xb9,0xe5,0x35,0x30,0xe0,0x5a,0x90,0x01,0x3d,0x74,0x01,0xf0,0x90,0x01,0x2f, ++0xe0,0x44,0x7f,0xf0,0x90,0x00,0x83,0xe0,0x54,0x0f,0xf5,0x0d,0xb4,0x01,0x02,0x80, ++0x1c,0xe5,0x0d,0xb4,0x02,0x05,0x90,0x00,0x83,0x80,0x12,0xe5,0x0d,0xb4,0x04,0x05, ++0x90,0x00,0x83,0x80,0x08,0xe5,0x0d,0xb4,0x0c,0x08,0x90,0x00,0x83,0xe0,0xf5,0x6f, ++0x80,0x06,0x90,0x01,0xbe,0xe0,0x04,0xf0,0x90,0x01,0xbb,0xe5,0x6f,0xf0,0xe5,0x6f, ++0x30,0xe0,0x03,0xa3,0x80,0x03,0x90,0x01,0xbd,0xe0,0x04,0xf0,0xf1,0x38,0x12,0x44, ++0xc2,0xe5,0x35,0x30,0xe2,0x06,0x90,0x01,0x3d,0x74,0x04,0xf0,0xe5,0x36,0x30,0xe0, ++0x06,0x90,0x01,0x3e,0x74,0x01,0xf0,0xe5,0x36,0x30,0xe1,0x06,0x90,0x01,0x3e,0x74, ++0x02,0xf0,0x74,0x99,0x04,0x90,0x01,0xc4,0xf0,0x74,0x5d,0xa3,0xf0,0xd0,0x07,0xd0, ++0x06,0xd0,0x05,0xd0,0x04,0xd0,0x03,0xd0,0x02,0xd0,0x01,0xd0,0x00,0xd0,0xd0,0xd0, ++0x82,0xd0,0x83,0xd0,0xf0,0xd0,0xe0,0x32,0xe5,0x6f,0x30,0xe6,0x19,0xe5,0x6f,0x54, ++0x0f,0xff,0x90,0x91,0x24,0xe0,0xfe,0x4f,0x90,0x01,0x2f,0xf0,0xee,0x64,0x80,0x90, ++0x91,0x24,0xf0,0x53,0x6f,0xbf,0x22,0xe4,0x90,0x91,0x0d,0xf0,0xe5,0x70,0x70,0x02, ++0xe1,0xe1,0x90,0x91,0x3c,0xe0,0x60,0x0d,0xe4,0xf0,0x53,0x71,0xfd,0xe5,0x71,0x54, ++0x07,0x70,0x6e,0x80,0x69,0x90,0x91,0x28,0xe0,0x04,0xf0,0x53,0x71,0xef,0x90,0x91, ++0x3a,0xe0,0x04,0xf0,0x90,0x91,0x0d,0xe0,0xf9,0xff,0x7e,0x00,0x24,0x01,0xfd,0xee, ++0x33,0xfc,0x90,0x91,0x3a,0xe0,0xb5,0x05,0x06,0xe4,0xb5,0x04,0x02,0x80,0x12,0xef, ++0x24,0x02,0xff,0xe4,0x3e,0xfe,0x90,0x91,0x3a,0xe0,0xb5,0x07,0x0a,0xe4,0xb5,0x06, ++0x06,0x90,0x05,0x58,0xe0,0x04,0xf0,0xe9,0xff,0x90,0x91,0x2f,0xe0,0x2f,0xff,0xe4, ++0x33,0xfe,0x90,0x91,0x28,0xe0,0xd3,0x9f,0xee,0x64,0x80,0xf8,0x74,0x80,0x98,0x40, ++0x0d,0xe5,0x6d,0xb4,0x01,0x0b,0xa3,0xe0,0x70,0x07,0xe0,0x04,0xf0,0x22,0x12,0x44, ++0xc2,0x22,0x8f,0x20,0x8c,0x21,0x8d,0x22,0x22,0x8f,0x23,0x8c,0x24,0x8d,0x25,0x22, ++0xe4,0x90,0x91,0x11,0xf0,0xa3,0xf0,0x90,0x02,0x86,0xe0,0x20,0xe1,0x2c,0xc3,0x90, ++0x91,0x12,0xe0,0x94,0x20,0x90,0x91,0x11,0xe0,0x94,0x03,0x40,0x0a,0x90,0x01,0xc6, ++0xe0,0x44,0x20,0xf0,0x7f,0x00,0x22,0x90,0x91,0x11,0xe4,0x75,0xf0,0x01,0x12,0x42, ++0x81,0x7f,0x01,0x7e,0x00,0x12,0x37,0x54,0x80,0xcd,0x7f,0x01,0x22,0x90,0x01,0xcc, ++0xe0,0x54,0x0f,0x90,0x91,0x11,0xf0,0x90,0x91,0x11,0xe0,0xfd,0x70,0x02,0x21,0x6f, ++0x90,0x91,0x9c,0xe0,0xff,0x74,0x01,0x7e,0x00,0xa8,0x07,0x08,0x80,0x05,0xc3,0x33, ++0xce,0x33,0xce,0xd8,0xf9,0xff,0xef,0x5d,0x70,0x02,0x21,0x68,0x90,0x91,0x9c,0xe0, ++0x75,0xf0,0x04,0x90,0x01,0xd0,0x12,0x43,0x15,0xe0,0x90,0x91,0x12,0xf0,0x75,0x63, ++0x01,0x75,0x64,0x91,0x75,0x65,0x12,0x75,0x66,0x01,0x7b,0x01,0x7a,0x91,0x79,0x13, ++0x12,0x46,0x6d,0x90,0x91,0x13,0xe0,0xff,0xc4,0x13,0x13,0x13,0x54,0x01,0x90,0x91, ++0x9c,0x30,0xe0,0x59,0xe0,0x75,0xf0,0x02,0x90,0x00,0x88,0x12,0x43,0x15,0xe0,0x90, ++0x91,0x14,0xf0,0x90,0x91,0x9c,0xe0,0x75,0xf0,0x02,0x90,0x00,0x89,0x12,0x43,0x15, ++0xe0,0x90,0x91,0x15,0xf0,0x90,0x91,0x9c,0xe0,0x75,0xf0,0x04,0x90,0x01,0xd1,0x12, ++0x43,0x15,0xe0,0x90,0x91,0x16,0xf0,0x90,0x91,0x9c,0xe0,0x75,0xf0,0x04,0x90,0x01, ++0xd2,0x12,0x43,0x15,0xe0,0x90,0x91,0x17,0xf0,0x90,0x91,0x9c,0xe0,0x75,0xf0,0x04, ++0x90,0x01,0xd3,0x12,0x43,0x15,0xe0,0x90,0x91,0x18,0xf0,0x80,0x33,0xe0,0x75,0xf0, ++0x04,0x90,0x01,0xd1,0x12,0x43,0x15,0xe0,0x90,0x91,0x14,0xf0,0x90,0x91,0x9c,0xe0, ++0x75,0xf0,0x04,0x90,0x01,0xd2,0x12,0x43,0x15,0xe0,0x90,0x91,0x15,0xf0,0x90,0x91, ++0x9c,0xe0,0x75,0xf0,0x04,0x90,0x01,0xd3,0x12,0x43,0x15,0xe0,0x90,0x91,0x16,0xf0, ++0xef,0x54,0x7f,0xff,0x7b,0x01,0x7a,0x91,0x79,0x14,0x12,0x51,0xf8,0x90,0x91,0x11, ++0xe0,0xff,0x90,0x91,0x9c,0xe0,0xfe,0x74,0x01,0xa8,0x06,0x08,0x80,0x02,0xc3,0x33, ++0xd8,0xfc,0xf4,0x5f,0x90,0x91,0x11,0xf0,0x90,0x91,0x9c,0xe0,0xff,0x74,0x01,0xa8, ++0x07,0x08,0x80,0x02,0xc3,0x33,0xd8,0xfc,0x90,0x01,0xcc,0xf0,0x90,0x91,0x9c,0xe0, ++0x04,0xf0,0xe0,0x54,0x03,0xf0,0x01,0x37,0x90,0x01,0xc6,0xe0,0x44,0x02,0xf0,0x22, ++0xad,0x07,0x74,0x11,0x2d,0xf5,0x82,0xe4,0x34,0xfc,0xf5,0x83,0xe0,0x44,0x01,0xf0, ++0x90,0x04,0x80,0xe0,0x54,0x0f,0xfc,0x74,0x14,0x2d,0xf5,0x82,0xe4,0x34,0xfc,0xf5, ++0x83,0xe0,0x54,0xc0,0x4c,0xfd,0x74,0x14,0x2f,0xf5,0x82,0xe4,0x34,0xfc,0xf5,0x83, ++0xed,0xf0,0x22,0xef,0x60,0x0f,0x74,0x21,0x2d,0xf5,0x82,0xe4,0x34,0xfc,0xf5,0x83, ++0xe0,0x44,0x10,0xf0,0x22,0x74,0x21,0x2d,0xf5,0x82,0xe4,0x34,0xfc,0xf5,0x83,0xe0, ++0x54,0xef,0xf0,0x22,0xe4,0xf5,0x6d,0xf5,0x71,0xf5,0x70,0x75,0x6f,0x0c,0x75,0x6e, ++0x0c,0x90,0x91,0x3b,0xf0,0x90,0x91,0x37,0xf0,0x90,0x91,0x36,0xf0,0x90,0x91,0x39, ++0x04,0xf0,0x90,0x91,0x27,0xf0,0xe4,0x90,0x91,0x3c,0xf0,0x90,0x91,0x29,0xf0,0x90, ++0x91,0x34,0x74,0x07,0xf0,0xe4,0x90,0x91,0x28,0xf0,0x90,0x91,0x32,0xf0,0xa3,0x74, ++0x03,0xf0,0x90,0x91,0x2f,0x74,0x0a,0xf0,0xa3,0x74,0x05,0xf0,0x90,0x91,0x2d,0x74, ++0x14,0xf0,0x90,0x91,0x35,0x74,0x05,0xf0,0xe4,0x90,0x91,0x2b,0xf0,0x90,0x91,0x25, ++0xf0,0x90,0x91,0x50,0xf0,0x90,0x91,0x31,0xf0,0x90,0x91,0x3a,0xf0,0x90,0x91,0x26, ++0xf0,0x90,0x91,0x38,0xf0,0x90,0x91,0x2e,0xf0,0x90,0x91,0x2c,0xf0,0x22,0xe4,0x90, ++0x91,0x3c,0xf0,0x90,0x91,0x28,0xf0,0xf5,0x71,0x22,0x90,0x06,0x04,0xe0,0x54,0xbf, ++0xf0,0xef,0x60,0x0a,0xe5,0x6d,0xb4,0x01,0x05,0xe4,0xff,0x12,0x47,0xc9,0x53,0x6e, ++0xf0,0x43,0x6e,0x0c,0x22,0x90,0x91,0x9d,0xef,0xf0,0x51,0x7e,0x90,0x91,0x9d,0xe0, ++0x60,0x05,0x90,0x05,0x22,0xe4,0xf0,0x53,0x6e,0xf0,0x43,0x6e,0x04,0x22,0x90,0x00, ++0x11,0xe0,0x44,0x09,0xf0,0x12,0x4a,0xe6,0x90,0x90,0xd8,0x12,0x43,0x09,0x90,0x80, ++0x85,0x12,0x2a,0x7f,0x7f,0x78,0x7e,0x08,0x12,0x2f,0xd9,0x90,0x90,0xdc,0x12,0x43, ++0x09,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0x04,0x7e,0x0c,0x12,0x2f,0xd9,0x90,0x90, ++0xe0,0x12,0x43,0x09,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0x00,0x7e,0x08,0x12,0x2f, ++0xd9,0x90,0x90,0xe4,0x12,0x43,0x09,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0x70,0x7e, ++0x0e,0x12,0x2f,0xd9,0x90,0x80,0x59,0x12,0x2a,0x8b,0x00,0x03,0x2d,0x95,0xe4,0xfd, ++0xff,0x12,0x34,0x81,0x90,0x91,0x51,0xe0,0xb4,0x01,0x11,0x90,0x80,0x59,0x12,0x2a, ++0x8b,0x00,0x03,0x2d,0x95,0xe4,0xfd,0x7f,0x01,0x12,0x34,0x81,0x22,0x8f,0x77,0xe4, ++0x90,0x91,0x96,0xf0,0xa3,0xf0,0x90,0x01,0x09,0xe0,0x7f,0x00,0x30,0xe7,0x02,0x7f, ++0x01,0xef,0x65,0x77,0x60,0x3e,0xc3,0x90,0x91,0x97,0xe0,0x94,0x88,0x90,0x91,0x96, ++0xe0,0x94,0x13,0x40,0x08,0x90,0x01,0xc6,0xe0,0x44,0x80,0xf0,0x22,0x90,0x91,0x96, ++0xe4,0x75,0xf0,0x01,0x12,0x42,0x81,0x7f,0x14,0x7e,0x00,0x12,0x37,0x54,0xd3,0x90, ++0x91,0x97,0xe0,0x94,0x32,0x90,0x91,0x96,0xe0,0x94,0x00,0x40,0xb9,0x90,0x01,0xc7, ++0xe0,0x30,0xe0,0xb2,0x22,0x22,0x53,0x6e,0xf0,0x43,0x6e,0x01,0x71,0x55,0x71,0x67, ++0x53,0x6e,0xf0,0x43,0x6e,0x02,0x22,0x22,0x8f,0x78,0x12,0x47,0xe6,0xef,0x64,0x01, ++0x70,0x2e,0x90,0x91,0x44,0x12,0x48,0x1e,0xe5,0x78,0x60,0x10,0x74,0x21,0x2f,0xf5, ++0x82,0xe4,0x34,0xfc,0xf5,0x83,0xe0,0x44,0x10,0xf0,0x80,0x0e,0x74,0x21,0x2f,0xf5, ++0x82,0xe4,0x34,0xfc,0xf5,0x83,0xe0,0x54,0xef,0xf0,0x90,0x04,0x1f,0x74,0x20,0xf0, ++0x22,0xe4,0xfb,0x90,0x91,0x7c,0x12,0x2a,0x8b,0x00,0x00,0x00,0x00,0xe5,0x70,0x60, ++0x5f,0xe5,0x6d,0x64,0x01,0x70,0x59,0x0b,0x90,0x91,0x27,0xf0,0x04,0x60,0x51,0x43, ++0x71,0x10,0xe4,0x90,0x91,0x66,0xf0,0x90,0x91,0x3a,0xe0,0x75,0xf0,0x05,0xa4,0xff, ++0x90,0x91,0x34,0xe0,0x2f,0x90,0x91,0x67,0xf0,0xe4,0x1b,0x12,0x44,0x54,0x90,0x01, ++0x57,0x74,0x05,0xf0,0xe5,0x6e,0x54,0x0f,0xc3,0x94,0x04,0x50,0x07,0x7d,0x01,0x7f, ++0x04,0x12,0x47,0x27,0x90,0x91,0x2e,0xe0,0x60,0x11,0x90,0x91,0x2c,0xe0,0x90,0x07, ++0x78,0x60,0x05,0x74,0x0d,0xf0,0x80,0x03,0x74,0x09,0xf0,0x90,0x05,0x22,0xe4,0xf0, ++0x22,0x90,0x91,0x32,0xe0,0xa3,0xe0,0x90,0x05,0x58,0xf0,0x22,0xd3,0x10,0xaf,0x01, ++0xc3,0xc0,0xd0,0x90,0x91,0x84,0xee,0xf0,0xa3,0xef,0xf0,0xe4,0xa3,0xf0,0xa3,0xf0, ++0x90,0x91,0x84,0xe0,0xfe,0xa3,0xe0,0xf5,0x82,0x8e,0x83,0xe0,0x60,0x2d,0xc3,0x90, ++0x91,0x87,0xe0,0x94,0xe8,0x90,0x91,0x86,0xe0,0x94,0x03,0x40,0x0b,0x90,0x01,0xc6, ++0xe0,0x44,0x10,0xf0,0x7f,0x00,0x80,0x15,0x90,0x91,0x86,0xe4,0x75,0xf0,0x01,0x12, ++0x42,0x81,0x7f,0x0a,0x7e,0x00,0x12,0x37,0x54,0x80,0xc5,0x7f,0x01,0xd0,0xd0,0x92, ++0xaf,0x22,0xd3,0x10,0xaf,0x01,0xc3,0xc0,0xd0,0x90,0x91,0x1c,0x12,0x43,0x41,0x90, ++0x91,0x1f,0x12,0x2a,0x8b,0x00,0x00,0x00,0x00,0x90,0x91,0x1c,0x12,0x43,0x21,0x90, ++0x00,0x01,0x12,0x42,0x20,0x90,0x91,0x3b,0xf0,0x90,0x00,0x03,0x12,0x42,0x20,0x90, ++0x91,0x25,0xf0,0x90,0x00,0x04,0x12,0x42,0x20,0xff,0x54,0x01,0x90,0x91,0x26,0xf0, ++0xef,0xc3,0x13,0x54,0x01,0x90,0x91,0x2e,0xf0,0x90,0x00,0x04,0x12,0x42,0x20,0xff, ++0x13,0x13,0x54,0x01,0x90,0x91,0x2c,0xf0,0x90,0x91,0x2e,0xe0,0x90,0x91,0x1f,0x70, ++0x26,0x12,0x2a,0x8b,0x00,0x00,0x02,0x10,0x90,0x91,0x1f,0x12,0x43,0x09,0x90,0x80, ++0x85,0x12,0x2a,0x7f,0x7f,0x60,0x7e,0x08,0x12,0x2f,0xd9,0x90,0x91,0x1f,0x12,0x2a, ++0x8b,0x00,0x00,0x03,0x10,0x80,0x24,0x12,0x2a,0x8b,0x00,0x00,0x01,0x10,0x90,0x91, ++0x1f,0x12,0x43,0x09,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0x60,0x7e,0x08,0x12,0x2f, ++0xd9,0x90,0x91,0x1f,0x12,0x2a,0x8b,0x00,0x00,0x03,0x00,0x90,0x91,0x1f,0x12,0x43, ++0x09,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0x70,0x7e,0x08,0x12,0x2f,0xd9,0x90,0x91, ++0x26,0xe0,0x70,0x3d,0x90,0x91,0x38,0x74,0x01,0xf0,0x7f,0x00,0x7e,0x08,0x12,0x27, ++0xde,0x90,0x91,0x1f,0x12,0x2a,0x7f,0x90,0x91,0x1f,0x12,0x43,0x09,0xec,0x44,0x02, ++0xfc,0x90,0x91,0x1f,0x12,0x2a,0x7f,0x90,0x91,0x1f,0x12,0x43,0x09,0x90,0x80,0x85, ++0x12,0x2a,0x7f,0x7f,0x00,0x7e,0x08,0x12,0x2f,0xd9,0x90,0x02,0x86,0xe0,0x54,0xfb, ++0xf0,0x90,0x91,0x1c,0x12,0x43,0x21,0x12,0x49,0x7f,0x90,0x01,0xe5,0xe5,0x70,0xf0, ++0x90,0x91,0x3b,0xe0,0x90,0x01,0xe6,0xf0,0xd0,0xd0,0x92,0xaf,0x22,0x90,0x00,0x02, ++0x12,0x42,0x20,0xff,0x30,0xe0,0x25,0x12,0x29,0xd9,0x90,0x91,0x2f,0xf0,0x90,0x00, ++0x01,0x12,0x42,0x20,0x90,0x91,0x30,0xf0,0xef,0xc3,0x13,0x54,0x7f,0x90,0x91,0x2d, ++0xf0,0x90,0x00,0x03,0x12,0x42,0x20,0x90,0x91,0x35,0xf0,0x22,0x90,0x91,0x2f,0x74, ++0x0a,0xf0,0x90,0x91,0x30,0x74,0x05,0xf0,0x90,0x91,0x2d,0x74,0x14,0xf0,0x90,0x91, ++0x35,0x74,0x05,0xf0,0x22,0x12,0x29,0xd9,0x30,0xe0,0x19,0xc3,0x13,0x54,0x7f,0x90, ++0x91,0x34,0xf0,0x90,0x00,0x01,0x12,0x42,0x20,0xff,0x90,0x91,0x32,0xe4,0xf0,0xa3, ++0xef,0xf0,0x80,0x0f,0x90,0x91,0x34,0x74,0x07,0xf0,0x90,0x91,0x32,0xe4,0xf0,0xa3, ++0x74,0x03,0xf0,0x90,0x91,0x32,0xe0,0xa3,0xe0,0x90,0x05,0x58,0xf0,0x22,0x90,0x02, ++0x09,0xe0,0xfd,0x12,0x29,0xd9,0xfe,0xaf,0x05,0xed,0x2e,0x90,0x91,0x41,0xf0,0x90, ++0x00,0x01,0x12,0x42,0x20,0xff,0xed,0x2f,0x90,0x91,0x42,0xf0,0x90,0x00,0x02,0x12, ++0x42,0x20,0xff,0xed,0x2f,0x90,0x91,0x43,0xf0,0x90,0x00,0x03,0x12,0x42,0x20,0xff, ++0xed,0x2f,0x90,0x91,0x44,0xf0,0x90,0x00,0x04,0x12,0x42,0x20,0xff,0xae,0x05,0xed, ++0x2f,0x90,0x91,0x45,0xf0,0x22,0xd3,0x10,0xaf,0x01,0xc3,0xc0,0xd0,0x90,0x91,0x47, ++0xe0,0x90,0x91,0x1d,0xf0,0x90,0x91,0x48,0xe0,0xf5,0x19,0xa3,0xe0,0xf5,0x1a,0xe4, ++0xf5,0x16,0x74,0x4a,0x25,0x16,0xf5,0x82,0xe4,0x34,0x91,0xf5,0x83,0xe0,0xff,0x74, ++0x1b,0x25,0x16,0xf8,0xa6,0x07,0x05,0x16,0xe5,0x16,0xb4,0x04,0xe5,0x90,0x91,0x1d, ++0xe0,0x12,0x43,0x4a,0x66,0xb3,0x00,0x67,0xdc,0x01,0x66,0xba,0x02,0x66,0xba,0x03, ++0x66,0xba,0x04,0x67,0xdc,0x05,0x67,0xac,0x80,0x67,0xc2,0x81,0x67,0xdc,0x82,0x00, ++0x00,0x67,0xd8,0xaf,0x1e,0x12,0x73,0xea,0xe1,0xdc,0x90,0x91,0x1d,0xe0,0xff,0xb4, ++0x02,0x08,0x90,0x91,0x1c,0x74,0x01,0xf0,0x80,0x0f,0xef,0x90,0x91,0x1c,0xb4,0x03, ++0x05,0x74,0x02,0xf0,0x80,0x03,0x74,0x04,0xf0,0xc3,0xe5,0x19,0x94,0x08,0x50,0x49, ++0xe4,0xf5,0x16,0x90,0x91,0x1c,0xe0,0xff,0xe5,0x16,0xc3,0x9f,0x40,0x02,0xe1,0xdc, ++0xc3,0xe5,0x19,0x94,0x01,0x50,0x14,0xe5,0x16,0x25,0x1a,0xff,0xc3,0x74,0x03,0x95, ++0x16,0x24,0x1b,0xf8,0xe6,0xfd,0x12,0x4b,0xee,0x80,0x1a,0xc3,0x74,0x03,0x95,0x16, ++0x24,0x1b,0xf8,0xe6,0xff,0xe5,0x16,0x7c,0x00,0x25,0x1a,0xfd,0xec,0x35,0x19,0x8d, ++0x82,0xf5,0x83,0xef,0xf0,0x05,0x16,0x80,0xba,0xc3,0xe5,0x19,0x94,0x10,0x40,0x02, ++0xe1,0xdc,0x90,0x91,0x1d,0xe0,0x64,0x04,0x60,0x02,0xe1,0xdc,0xaf,0x1c,0xfc,0xfd, ++0xfe,0x78,0x10,0x12,0x2a,0x6c,0xc0,0x04,0xc0,0x05,0xc0,0x06,0xc0,0x07,0xaf,0x1b, ++0xe4,0xfc,0xfd,0xfe,0x78,0x18,0x12,0x2a,0x6c,0xd0,0x03,0xd0,0x02,0xd0,0x01,0xd0, ++0x00,0x12,0x42,0xfc,0xc0,0x04,0xc0,0x05,0xc0,0x06,0xc0,0x07,0xaf,0x1d,0xe4,0xfc, ++0xfd,0xfe,0x78,0x08,0x12,0x2a,0x6c,0xd0,0x03,0xd0,0x02,0xd0,0x01,0xd0,0x00,0x12, ++0x42,0xfc,0xa8,0x04,0xa9,0x05,0xaa,0x06,0xab,0x07,0xaf,0x1e,0xe4,0xfc,0xfd,0xfe, ++0x12,0x42,0xfc,0xa3,0x12,0x2a,0x7f,0x90,0x91,0x1e,0x12,0x43,0x09,0x90,0x80,0x85, ++0x12,0x2a,0x7f,0xaf,0x1a,0xae,0x19,0x12,0x2f,0xd9,0x80,0x30,0xe5,0x1d,0x7f,0x00, ++0xfe,0xef,0x25,0x1e,0xf5,0x18,0xe4,0x3e,0xf5,0x17,0xaf,0x18,0xfe,0x12,0x37,0x54, ++0x80,0x1a,0xe5,0x1d,0x7f,0x00,0xfe,0xef,0x25,0x1e,0xf5,0x18,0xe4,0x3e,0xf5,0x17, ++0xaf,0x18,0xfe,0x12,0x36,0xcb,0x80,0x04,0x7f,0x00,0x80,0x02,0x7f,0x01,0xd0,0xd0, ++0x92,0xaf,0x22,0x22,0x8e,0x0e,0x8f,0x0f,0x8b,0x10,0x8a,0x11,0x89,0x12,0xe4,0x90, ++0x91,0x11,0xf0,0xef,0x90,0x00,0x31,0xf0,0x12,0x4a,0xe6,0xe5,0x0e,0x54,0x03,0xff, ++0x90,0x00,0x32,0xe0,0x54,0xfc,0x4f,0xf0,0x12,0x4a,0xe6,0x90,0x00,0x33,0xe0,0x54, ++0x7f,0xf0,0x12,0x4a,0xe6,0x90,0x00,0x33,0xe0,0x20,0xe7,0x0e,0x90,0x91,0x11,0xe0, ++0xc3,0x94,0x64,0x50,0x05,0xe0,0x04,0xf0,0x80,0xeb,0x90,0x91,0x11,0xe0,0xc3,0x94, ++0x64,0x50,0x10,0x90,0x00,0x30,0xe0,0xab,0x10,0xaa,0x11,0xa9,0x12,0x12,0x42,0x4d, ++0x7f,0x01,0x22,0x7f,0x00,0x22,0xe4,0x90,0x91,0x98,0xf0,0xa3,0xf0,0x90,0x05,0xf8, ++0xe0,0x70,0x0f,0xa3,0xe0,0x70,0x0b,0xa3,0xe0,0x70,0x07,0xa3,0xe0,0x70,0x03,0x7f, ++0x01,0x22,0xd3,0x90,0x91,0x99,0xe0,0x94,0xe8,0x90,0x91,0x98,0xe0,0x94,0x03,0x40, ++0x03,0x7f,0x00,0x22,0x7f,0x32,0x7e,0x00,0x12,0x37,0x54,0x90,0x91,0x98,0xe4,0x75, ++0xf0,0x01,0x12,0x42,0x81,0x80,0xc6,0xef,0x70,0x02,0x41,0x3d,0x90,0x90,0xe8,0xe0, ++0x60,0x02,0xc1,0x08,0x90,0x90,0xd4,0x12,0x43,0x09,0x90,0x80,0x85,0x12,0x2a,0x7f, ++0x7f,0x8c,0x7e,0x08,0x12,0x2f,0xd9,0x90,0x90,0x80,0x12,0x43,0x09,0x90,0x80,0x85, ++0x12,0x2a,0x7f,0x7f,0x44,0x7e,0x08,0x12,0x2f,0xd9,0x90,0x90,0x84,0x12,0x43,0x09, ++0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0x5c,0x7e,0x08,0x12,0x2f,0xd9,0x90,0x90,0x88, ++0x12,0x43,0x09,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0x6c,0x7e,0x0e,0x12,0x2f,0xd9, ++0x90,0x90,0x8c,0x12,0x43,0x09,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0x70,0x7e,0x0e, ++0x12,0x2f,0xd9,0x90,0x90,0x90,0x12,0x43,0x09,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f, ++0x74,0x7e,0x0e,0x12,0x2f,0xd9,0x90,0x90,0x94,0x12,0x43,0x09,0x90,0x80,0x85,0x12, ++0x2a,0x7f,0x7f,0x78,0x7e,0x0e,0x12,0x2f,0xd9,0x90,0x90,0x98,0x12,0x43,0x09,0x90, ++0x80,0x85,0x12,0x2a,0x7f,0x7f,0x7c,0x7e,0x0e,0x12,0x2f,0xd9,0x90,0x90,0x9c,0x12, ++0x43,0x09,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0x80,0x7e,0x0e,0x12,0x2f,0xd9,0x90, ++0x90,0xa0,0x12,0x43,0x09,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0x84,0x7e,0x0e,0x12, ++0x2f,0xd9,0x90,0x90,0xa4,0x12,0x43,0x09,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0x88, ++0x7e,0x0e,0x12,0x2f,0xd9,0x90,0x90,0xa8,0x12,0x43,0x09,0x90,0x80,0x85,0x12,0x2a, ++0x7f,0x7f,0x8c,0x7e,0x0e,0x12,0x2f,0xd9,0x90,0x90,0xac,0x12,0x43,0x09,0x90,0x80, ++0x85,0x12,0x2a,0x7f,0x7f,0xd0,0x7e,0x0e,0x12,0x2f,0xd9,0x90,0x90,0xb0,0x12,0x43, ++0x09,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0xd4,0x7e,0x0e,0x12,0x2f,0xd9,0x90,0x90, ++0xb4,0x12,0x43,0x09,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0xd8,0x7e,0x0e,0x12,0x2f, ++0xd9,0x90,0x90,0xb8,0x12,0x43,0x09,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0xdc,0x7e, ++0x0e,0x12,0x2f,0xd9,0x90,0x90,0xbc,0x12,0x43,0x09,0x90,0x80,0x85,0x12,0x2a,0x7f, ++0x7f,0xe0,0x7e,0x0e,0x12,0x2f,0xd9,0x90,0x90,0xc0,0x12,0x43,0x09,0x90,0x80,0x85, ++0x12,0x2a,0x7f,0x7f,0xec,0x7e,0x0e,0x12,0x2f,0xd9,0x90,0x90,0xc4,0x12,0x43,0x09, ++0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0x04,0x7e,0x0c,0x12,0x2f,0xd9,0x90,0x90,0xc8, ++0x12,0x43,0x09,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0x04,0x7e,0x0d,0x12,0x2f,0xd9, ++0x90,0x90,0xcc,0x12,0x43,0x09,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0x0c,0x7e,0x09, ++0x12,0x2f,0xd9,0x90,0x90,0xd0,0x12,0x43,0x09,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f, ++0x04,0x7e,0x08,0x12,0x2f,0xd9,0x90,0x90,0xe8,0x74,0x01,0xf0,0x22,0x90,0x90,0xe8, ++0xe0,0x64,0x01,0x60,0x02,0xc1,0x08,0x7f,0x8c,0x7e,0x08,0x12,0x27,0xde,0x90,0x90, ++0xd4,0x12,0x2a,0x7f,0x7f,0x44,0x7e,0x08,0x12,0x27,0xde,0x90,0x90,0x80,0x12,0x2a, ++0x7f,0x7f,0x5c,0x7e,0x08,0x12,0x27,0xde,0x90,0x90,0x84,0x12,0x2a,0x7f,0x7f,0x6c, ++0x7e,0x0e,0x12,0x27,0xde,0x90,0x90,0x88,0x12,0x2a,0x7f,0x7f,0x70,0x7e,0x0e,0x12, ++0x27,0xde,0x90,0x90,0x8c,0x12,0x2a,0x7f,0x7f,0x74,0x7e,0x0e,0x12,0x27,0xde,0x90, ++0x90,0x90,0x12,0x2a,0x7f,0x7f,0x78,0x7e,0x0e,0x12,0x27,0xde,0x90,0x90,0x94,0x12, ++0x2a,0x7f,0x7f,0x7c,0x7e,0x0e,0x12,0x27,0xde,0x90,0x90,0x98,0x12,0x2a,0x7f,0x7f, ++0x80,0x7e,0x0e,0x12,0x27,0xde,0x90,0x90,0x9c,0x12,0x2a,0x7f,0x7f,0x84,0x7e,0x0e, ++0x12,0x27,0xde,0x90,0x90,0xa0,0x12,0x2a,0x7f,0x7f,0x88,0x7e,0x0e,0x12,0x27,0xde, ++0x90,0x90,0xa4,0x12,0x2a,0x7f,0x7f,0x8c,0x7e,0x0e,0x12,0x27,0xde,0x90,0x90,0xa8, ++0x12,0x2a,0x7f,0x7f,0xd0,0x7e,0x0e,0x12,0x27,0xde,0x90,0x90,0xac,0x12,0x2a,0x7f, ++0x7f,0xd4,0x7e,0x0e,0x12,0x27,0xde,0x90,0x90,0xb0,0x12,0x2a,0x7f,0x7f,0xd8,0x7e, ++0x0e,0x12,0x27,0xde,0x90,0x90,0xb4,0x12,0x2a,0x7f,0x7f,0xdc,0x7e,0x0e,0x12,0x27, ++0xde,0x90,0x90,0xb8,0x12,0x2a,0x7f,0x7f,0xe0,0x7e,0x0e,0x12,0x27,0xde,0x90,0x90, ++0xbc,0x12,0x2a,0x7f,0x7f,0xec,0x7e,0x0e,0x12,0x27,0xde,0x90,0x90,0xc0,0x12,0x2a, ++0x7f,0x7f,0x04,0x7e,0x0c,0x12,0x27,0xde,0x90,0x90,0xc4,0x12,0x2a,0x7f,0x7f,0x04, ++0x7e,0x0d,0x12,0x27,0xde,0x90,0x90,0xc8,0x12,0x2a,0x7f,0x7f,0x0c,0x7e,0x09,0x12, ++0x27,0xde,0x90,0x90,0xcc,0x12,0x2a,0x7f,0x7f,0x04,0x7e,0x08,0x12,0x27,0xde,0x90, ++0x90,0xd0,0x12,0x2a,0x7f,0x7f,0x8c,0x7e,0x08,0x12,0x27,0xde,0x90,0x91,0x88,0x12, ++0x2a,0x7f,0x90,0x91,0x88,0x12,0x43,0x09,0xed,0x44,0xc0,0xfd,0xec,0x90,0x91,0x88, ++0x12,0x2a,0x7f,0x90,0x91,0x88,0x12,0x43,0x09,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f, ++0x8c,0x7e,0x08,0x12,0x2f,0xd9,0x90,0x80,0x85,0x12,0x2a,0x8b,0x00,0x01,0x00,0x00, ++0x7f,0x44,0x7e,0x08,0x12,0x2f,0xd9,0x90,0x80,0x85,0x12,0x2a,0x8b,0x00,0xdb,0x25, ++0xa4,0x7f,0x5c,0x7e,0x08,0x12,0x2f,0xd9,0x90,0x80,0x85,0x12,0x2a,0x8b,0x20,0xdb, ++0x25,0xa4,0x7f,0x6c,0x7e,0x0e,0x12,0x2f,0xd9,0x90,0x80,0x85,0x12,0x2a,0x8b,0x20, ++0xdb,0x25,0xa4,0x7f,0x70,0x7e,0x0e,0x12,0x2f,0xd9,0x90,0x80,0x85,0x12,0x2a,0x8b, ++0x04,0x1b,0x25,0xa4,0x7f,0x74,0x7e,0x0e,0x12,0x2f,0xd9,0x90,0x80,0x85,0x12,0x2a, ++0x8b,0x04,0x1b,0x25,0xa4,0x7f,0x78,0x7e,0x0e,0x12,0x2f,0xd9,0x90,0x80,0x85,0x12, ++0x2a,0x8b,0x04,0x1b,0x25,0xa4,0x7f,0x7c,0x7e,0x0e,0x12,0x2f,0xd9,0x90,0x80,0x85, ++0x12,0x2a,0x8b,0x04,0x1b,0x25,0xa4,0x7f,0x80,0x7e,0x0e,0x12,0x2f,0xd9,0x90,0x80, ++0x85,0x12,0x2a,0x8b,0x63,0xdb,0x25,0xa4,0x7f,0x84,0x7e,0x0e,0x12,0x2f,0xd9,0x90, ++0x80,0x85,0x12,0x2a,0x8b,0x04,0x1b,0x25,0xa4,0x7f,0x88,0x7e,0x0e,0x12,0x2f,0xd9, ++0x90,0x80,0x85,0x12,0x2a,0x8b,0x20,0xdb,0x25,0xa4,0x7f,0x8c,0x7e,0x0e,0x12,0x2f, ++0xd9,0x90,0x80,0x85,0x12,0x2a,0x8b,0x20,0xdb,0x25,0xa4,0x7f,0xd0,0x7e,0x0e,0x12, ++0x2f,0xd9,0x90,0x80,0x85,0x12,0x2a,0x8b,0x20,0xdb,0x25,0xa4,0x7f,0xd4,0x7e,0x0e, ++0x12,0x2f,0xd9,0x90,0x80,0x85,0x12,0x2a,0x8b,0x20,0xdb,0x25,0xa4,0x7f,0xd8,0x7e, ++0x0e,0x12,0x2f,0xd9,0x90,0x80,0x85,0x12,0x2a,0x8b,0x00,0x1b,0x25,0xa4,0x7f,0xdc, ++0x7e,0x0e,0x12,0x2f,0xd9,0x90,0x80,0x85,0x12,0x2a,0x8b,0x00,0x1b,0x25,0xa4,0x7f, ++0xe0,0x7e,0x0e,0x12,0x2f,0xd9,0x90,0x80,0x85,0x12,0x2a,0x8b,0x24,0xdb,0x25,0xa4, ++0x7f,0xec,0x7e,0x0e,0x12,0x2f,0xd9,0x7f,0x04,0x7e,0x0c,0x12,0x27,0xde,0x90,0x91, ++0x88,0x12,0x2a,0x7f,0x90,0x91,0x88,0x12,0x43,0x09,0xe4,0xff,0xec,0x90,0x91,0x88, ++0x12,0x2a,0x7f,0x90,0x91,0x88,0x12,0x43,0x09,0xef,0x44,0x11,0xff,0xec,0x90,0x91, ++0x88,0x12,0x2a,0x7f,0x90,0x91,0x88,0x12,0x43,0x09,0x90,0x80,0x85,0x12,0x2a,0x7f, ++0x7f,0x04,0x7e,0x0c,0x12,0x2f,0xd9,0x7f,0x04,0x7e,0x0d,0x12,0x27,0xde,0x90,0x91, ++0x88,0x12,0x2a,0x7f,0x90,0x91,0x88,0x12,0x43,0x09,0xef,0x54,0xf0,0xff,0xec,0x90, ++0x91,0x88,0x12,0x2a,0x7f,0x90,0x91,0x88,0x12,0x43,0x09,0xef,0x44,0x01,0xff,0xec, ++0x90,0x91,0x88,0x12,0x2a,0x7f,0x90,0x91,0x88,0x12,0x43,0x09,0x90,0x80,0x85,0x12, ++0x2a,0x7f,0x7f,0x04,0x7e,0x0d,0x12,0x2f,0xd9,0x7f,0x0c,0x7e,0x09,0x12,0x27,0xde, ++0x90,0x91,0x88,0x12,0x2a,0x7f,0x90,0x91,0x88,0x12,0x43,0x09,0xe4,0xff,0xec,0x90, ++0x91,0x88,0x12,0x2a,0x7f,0x90,0x91,0x88,0x12,0x43,0x09,0xef,0x44,0x11,0xff,0xec, ++0x90,0x91,0x88,0x12,0x2a,0x7f,0x90,0x91,0x88,0x12,0x43,0x09,0x90,0x80,0x85,0x12, ++0x2a,0x7f,0x7f,0x0c,0x7e,0x09,0x12,0x2f,0xd9,0x7f,0x0c,0x7e,0x09,0x12,0x27,0xde, ++0x90,0x91,0x88,0x12,0x2a,0x7f,0x90,0x91,0x88,0x12,0x43,0x09,0xed,0x54,0x0f,0xfd, ++0xec,0x54,0xf0,0xfc,0x90,0x91,0x88,0x12,0x2a,0x7f,0x90,0x91,0x88,0x12,0x43,0x09, ++0xed,0x44,0x10,0xfd,0xec,0x44,0x01,0xfc,0x90,0x91,0x88,0x12,0x2a,0x7f,0x90,0x91, ++0x88,0x12,0x43,0x09,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0x0c,0x7e,0x09,0x12,0x2f, ++0xd9,0x7f,0x04,0x7e,0x08,0x12,0x27,0xde,0x90,0x91,0x88,0x12,0x2a,0x7f,0x90,0x91, ++0x88,0x12,0x43,0x09,0xef,0x54,0xf0,0xff,0xec,0x90,0x91,0x88,0x12,0x2a,0x7f,0x90, ++0x91,0x88,0x12,0x43,0x09,0xef,0x44,0x01,0xff,0xec,0x90,0x91,0x88,0x12,0x2a,0x7f, ++0x90,0x91,0x88,0x12,0x43,0x09,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0x04,0x7e,0x08, ++0x12,0x2f,0xd9,0xe4,0x90,0x90,0xe8,0xf0,0x22,0xe4,0xfd,0x7f,0x45,0x12,0x4b,0xee, ++0x90,0x04,0xfd,0xe4,0xf0,0xa3,0xf0,0x90,0x90,0xf7,0xf0,0x90,0x90,0xfd,0xf0,0x90, ++0x91,0x00,0xf0,0x90,0x90,0xfe,0xf0,0x90,0x91,0x01,0xf0,0x90,0x90,0xff,0xf0,0x90, ++0x91,0x02,0xf0,0x90,0x90,0xe9,0x04,0xf0,0xe4,0xa3,0xf0,0xa3,0xf0,0xa3,0xf0,0x90, ++0x90,0xee,0xf0,0x90,0x90,0xf3,0xf0,0x90,0x90,0xf5,0xf0,0x90,0x91,0x07,0xf0,0x90, ++0x90,0xf8,0xf0,0x90,0x90,0xf4,0xf0,0x90,0x90,0xed,0xf0,0x90,0x00,0x51,0xe0,0x44, ++0xc0,0xfd,0x7f,0x51,0x02,0x4b,0xee,0x90,0x05,0x60,0xe0,0x90,0x91,0x03,0xf0,0x90, ++0x05,0x61,0xe0,0x90,0x91,0x04,0xf0,0x90,0x05,0x62,0xe0,0x90,0x91,0x05,0xf0,0x90, ++0x05,0x63,0xe0,0x90,0x91,0x06,0xf0,0xc3,0x74,0xff,0x9f,0xfe,0x90,0x91,0x04,0xe0, ++0xd3,0x9e,0x40,0x1e,0xe0,0x2f,0xf0,0xa3,0xe0,0xb4,0xff,0x0f,0xe4,0xf0,0xa3,0xe0, ++0xb4,0xff,0x03,0xe4,0xf0,0x22,0x90,0x91,0x06,0x80,0x03,0x90,0x91,0x05,0xe0,0x04, ++0xf0,0x22,0x90,0x91,0x04,0xe0,0x2f,0xf0,0x22,0x90,0x90,0xf5,0xe0,0x64,0x01,0x60, ++0x02,0xe1,0x6e,0x90,0x00,0x46,0xe0,0x44,0x01,0xfd,0x7f,0x46,0x12,0x4b,0xee,0x90, ++0x91,0x07,0xe0,0x70,0x32,0x90,0x90,0xed,0xe0,0x60,0x15,0x90,0x90,0xf9,0x12,0x43, ++0x09,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0x80,0x7e,0x08,0x12,0x2f,0xd9,0x80,0x06, ++0x90,0x05,0x22,0x74,0x7f,0xf0,0x90,0x90,0xf4,0xe0,0xff,0xd1,0x67,0x90,0x91,0x07, ++0x74,0x01,0x12,0x4b,0xe4,0x80,0x40,0x90,0x91,0x07,0xe0,0x64,0x01,0x70,0x38,0x90, ++0x90,0xf8,0xe0,0xff,0xd1,0x67,0xe4,0x90,0x91,0x07,0xf0,0x90,0x00,0x45,0xe0,0x44, ++0x01,0xfd,0x7f,0x45,0x12,0x4b,0xee,0x90,0x90,0xed,0xe0,0x60,0x15,0x90,0x90,0xef, ++0x12,0x43,0x09,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0x80,0x7e,0x08,0x12,0x2f,0xd9, ++0x80,0x05,0x90,0x05,0x22,0xe4,0xf0,0x90,0x05,0x87,0xe0,0x64,0x80,0xf0,0x90,0x91, ++0x03,0xe0,0x90,0x05,0x84,0xf0,0x90,0x91,0x04,0xe0,0x90,0x05,0x85,0xf0,0x90,0x91, ++0x05,0xe0,0x90,0x05,0x86,0xf0,0x90,0x91,0x06,0xe0,0x90,0x05,0x87,0xf0,0x22,0x90, ++0x90,0xee,0xe0,0xc3,0x94,0x14,0x50,0x06,0xe0,0x04,0xf0,0x02,0x70,0x29,0x90,0x90, ++0xee,0xe0,0x64,0x14,0x60,0x03,0x02,0x70,0x29,0x90,0x90,0xfd,0xe0,0x70,0x25,0x90, ++0x91,0x00,0xe0,0x70,0x1f,0x90,0x90,0xfe,0xe0,0x70,0x19,0x90,0x91,0x01,0xe0,0x70, ++0x13,0x90,0x90,0xff,0xe0,0x70,0x0d,0x90,0x91,0x02,0xe0,0x70,0x07,0x90,0x04,0xfd, ++0xe0,0x54,0xfe,0xf0,0x90,0x90,0xfd,0xe0,0x90,0x04,0x44,0xf0,0x90,0x90,0xfe,0xe0, ++0x90,0x04,0x45,0xf0,0x90,0x90,0xff,0xe0,0x90,0x04,0x46,0xf0,0xa3,0xe4,0xf0,0x90, ++0x91,0x00,0xe0,0x90,0x04,0x48,0xf0,0x90,0x91,0x01,0xe0,0x90,0x04,0x49,0xf0,0x90, ++0x91,0x02,0xe0,0x90,0x04,0x4a,0xf0,0xa3,0xe4,0xf0,0x90,0x90,0xe9,0xe0,0x90,0x04, ++0x4c,0xf0,0x90,0x90,0xea,0xe0,0x90,0x04,0x4d,0xf0,0x90,0x90,0xeb,0xe0,0x90,0x04, ++0x4e,0xf0,0x90,0x90,0xec,0xe0,0x90,0x04,0x4f,0xf0,0xe4,0x90,0x90,0xee,0xf0,0x90, ++0x90,0xe9,0x04,0xf0,0xe4,0xa3,0xf0,0xa3,0xf0,0xa3,0xf0,0x90,0x90,0xfd,0xf0,0xa3, ++0xf0,0xa3,0xf0,0xa3,0xf0,0xa3,0xf0,0xa3,0xf0,0x90,0x05,0x60,0xe0,0x90,0x91,0x8c, ++0xf0,0x90,0x05,0x61,0xe0,0x90,0x91,0x8d,0xf0,0x90,0x05,0x62,0xe0,0x90,0x91,0x8e, ++0xf0,0x90,0x05,0x63,0xe0,0x90,0x91,0x8f,0xf0,0x90,0x91,0x06,0xe0,0xff,0x90,0x91, ++0x8f,0xe0,0xfe,0xd3,0x9f,0x50,0x0b,0x90,0x91,0x06,0xe0,0xc3,0x9e,0xd3,0x94,0x01, ++0x40,0x11,0x90,0x90,0xf4,0xe0,0xb4,0x01,0x02,0x80,0x03,0x90,0x90,0xf8,0xe0,0xff, ++0x12,0x6e,0x67,0x22,0x90,0x91,0x07,0xe0,0x64,0x01,0x60,0x08,0x90,0x90,0xf5,0xe0, ++0x60,0x02,0x21,0x4b,0x90,0x90,0xe9,0xe0,0xc3,0x94,0xff,0x50,0x05,0xe0,0x04,0xf0, ++0x80,0x3b,0x90,0x90,0xea,0xe0,0xc3,0x94,0xff,0x50,0x06,0xe0,0x04,0xf0,0xe4,0x80, ++0x28,0x90,0x90,0xeb,0xe0,0xc3,0x94,0xff,0x50,0x0a,0xe0,0x04,0xf0,0xe4,0x90,0x90, ++0xea,0xf0,0x80,0x15,0x90,0x90,0xec,0xe0,0xc3,0x94,0xff,0x50,0x10,0xe0,0x04,0xf0, ++0xe4,0x90,0x90,0xeb,0xf0,0x90,0x90,0xea,0xf0,0x90,0x90,0xe9,0xf0,0x90,0x00,0x44, ++0xe0,0x54,0x0c,0x60,0x76,0xe0,0x30,0xe2,0x32,0x90,0x90,0xfd,0xe0,0xc3,0x94,0xff, ++0x50,0x05,0xe0,0x04,0xf0,0x80,0x24,0x90,0x90,0xfe,0xe0,0xc3,0x94,0xff,0x50,0x06, ++0xe0,0x04,0xf0,0xe4,0x80,0x11,0x90,0x90,0xff,0xe0,0xc3,0x94,0xff,0x50,0x0c,0xe0, ++0x04,0xf0,0xe4,0x90,0x90,0xfe,0xf0,0x90,0x90,0xfd,0xf0,0x90,0x00,0x44,0xe0,0x30, ++0xe3,0x32,0x90,0x91,0x00,0xe0,0xc3,0x94,0xff,0x50,0x05,0xe0,0x04,0xf0,0x80,0x24, ++0x90,0x91,0x01,0xe0,0xc3,0x94,0xff,0x50,0x06,0xe0,0x04,0xf0,0xe4,0x80,0x11,0x90, ++0x91,0x02,0xe0,0xc3,0x94,0xff,0x50,0x0c,0xe0,0x04,0xf0,0xe4,0x90,0x91,0x01,0xf0, ++0x90,0x91,0x00,0xf0,0x90,0x04,0xfd,0xe0,0x44,0x01,0xf0,0x22,0x90,0x06,0x90,0xe0, ++0x44,0x01,0xf0,0x90,0x91,0x61,0xe0,0x30,0xe0,0x3c,0x90,0x91,0x5f,0xe0,0xff,0x90, ++0x91,0x5e,0xe0,0xfe,0xc4,0x13,0x54,0x01,0xfd,0x12,0x4a,0xf6,0x90,0x91,0x60,0xe0, ++0x75,0xf0,0x20,0xa4,0xff,0xae,0xf0,0x12,0x37,0x54,0x90,0x91,0x5e,0xe0,0xc4,0x13, ++0x54,0x07,0x30,0xe0,0x07,0xa3,0xe0,0xff,0xe4,0xfd,0x80,0x07,0x90,0x91,0x5f,0xe0, ++0xff,0x7d,0x01,0x12,0x4a,0xf6,0x22,0xd3,0x10,0xaf,0x01,0xc3,0xc0,0xd0,0xe4,0x90, ++0x91,0x19,0xf0,0xa3,0x74,0x08,0xf0,0xa3,0xf0,0xe4,0xa3,0xf0,0x90,0x01,0x1f,0xe0, ++0xfe,0x90,0x01,0x1e,0xe0,0x7c,0x00,0x24,0x00,0xff,0xec,0x3e,0x90,0x91,0x11,0xf0, ++0xa3,0xef,0xf0,0x90,0x02,0x87,0xe0,0x90,0x91,0x18,0xf0,0x90,0x91,0x56,0xe0,0x20, ++0xe0,0x02,0x61,0xc4,0xe4,0x90,0x91,0x17,0xf0,0x90,0x91,0x18,0xe0,0xff,0x90,0x91, ++0x17,0xe0,0xc3,0x9f,0x40,0x02,0x61,0xc4,0x90,0x91,0x11,0xe0,0xfc,0xa3,0xe0,0xfd, ++0xec,0xff,0x90,0xfd,0x11,0xf0,0x90,0x91,0x1c,0xef,0xf0,0x74,0x02,0x2d,0xf5,0x82, ++0xe4,0x34,0xfb,0xf5,0x83,0xe0,0x54,0x0f,0xfc,0x33,0x33,0x33,0x54,0xf8,0xff,0xed, ++0x24,0x18,0x2f,0x90,0x91,0x15,0xf0,0xe0,0x24,0x00,0xf5,0x82,0xe4,0x34,0xfb,0xf5, ++0x83,0xe0,0x54,0xfc,0x90,0x91,0x16,0xf0,0x74,0x01,0x2d,0xf5,0x82,0xe4,0x34,0xfb, ++0xf5,0x83,0xe0,0xfe,0x74,0x00,0x2d,0xf5,0x82,0xe4,0x34,0xfb,0xf5,0x83,0xe0,0x7a, ++0x00,0x24,0x00,0xff,0xea,0x3e,0x54,0x3f,0xab,0x07,0xfa,0x90,0x91,0x13,0xf0,0xa3, ++0xeb,0xf0,0xaf,0x04,0xef,0x75,0xf0,0x08,0xa4,0x24,0x18,0xff,0xe4,0x35,0xf0,0xfe, ++0xef,0x2b,0xfb,0xee,0x3a,0xfa,0x90,0x91,0x5a,0xe0,0xfe,0xa3,0xe0,0xff,0xad,0x03, ++0xac,0x02,0x12,0x45,0x09,0xaa,0x06,0xab,0x07,0x90,0x91,0x15,0xe0,0x24,0x00,0xf5, ++0x82,0xe4,0x34,0xfb,0xf5,0x83,0xe0,0x30,0xe7,0x08,0x90,0x91,0x19,0x74,0x02,0xf0, ++0x80,0x05,0xe4,0x90,0x91,0x19,0xf0,0xaf,0x03,0x90,0x91,0x11,0xea,0x8f,0xf0,0x12, ++0x42,0x81,0x90,0x91,0x5c,0xe0,0xfe,0xa3,0xe0,0xff,0x90,0x91,0x11,0xe0,0xfc,0xa3, ++0xe0,0xfd,0xd3,0x9f,0xec,0x9e,0x40,0x1b,0x90,0x91,0x5d,0xe0,0x24,0x01,0xff,0x90, ++0x91,0x5c,0xe0,0x34,0x00,0xfe,0xc3,0xed,0x9f,0xff,0xec,0x9e,0x90,0x91,0x11,0xf0, ++0xa3,0xef,0xf0,0x90,0x91,0x16,0xe0,0xff,0x24,0x40,0x60,0x04,0x24,0x20,0x70,0x27, ++0x90,0x91,0x5e,0xe0,0xfe,0xc4,0x13,0x13,0x13,0x54,0x01,0x20,0xe0,0x02,0x61,0x9c, ++0xef,0x90,0x00,0x81,0xb4,0xa0,0x05,0xe0,0x44,0x04,0x80,0x03,0xe0,0x44,0x08,0xfd, ++0x7f,0x81,0x12,0x4b,0xee,0x61,0x95,0x90,0x91,0x5e,0xe0,0xc4,0x13,0x13,0x54,0x03, ++0x20,0xe0,0x02,0x61,0x9c,0x90,0x91,0x15,0xe0,0xff,0x24,0x00,0xf5,0x82,0xe4,0x34, ++0xfb,0xf5,0x83,0xe0,0x54,0x0c,0x64,0x08,0x70,0x72,0x90,0x91,0x19,0xe0,0xfe,0xef, ++0x2e,0xff,0xa3,0xe0,0x2f,0xff,0x24,0x1e,0xf5,0x82,0xe4,0x34,0xfb,0xf5,0x83,0xe0, ++0x64,0x88,0x70,0x58,0x74,0x1f,0x2f,0xf5,0x82,0xe4,0x34,0xfb,0xf5,0x83,0xe0,0x64, ++0x8e,0x70,0x49,0x90,0x91,0x19,0xe0,0xff,0x90,0x91,0x15,0xe0,0x2f,0xff,0x90,0x91, ++0x1a,0xe0,0x2f,0xff,0xa3,0xe0,0x2f,0xff,0x24,0x19,0xf5,0x82,0xe4,0x34,0xfb,0xf5, ++0x83,0xe0,0x64,0x03,0x70,0x26,0x74,0x1e,0x2f,0xf5,0x82,0xe4,0x34,0xfb,0xf5,0x83, ++0xe0,0x90,0x00,0x81,0x30,0xe3,0x05,0xe0,0x44,0x01,0x80,0x03,0xe0,0x44,0x02,0xfd, ++0x7f,0x81,0x12,0x4b,0xee,0x90,0x91,0x56,0xe0,0x44,0x80,0xf0,0x90,0x91,0x56,0xe0, ++0xff,0xc4,0x13,0x13,0x13,0x54,0x01,0x30,0xe0,0x02,0x31,0x4c,0x71,0xc9,0xbf,0x01, ++0x13,0x90,0x91,0x11,0xe0,0xfe,0xa3,0xe0,0xff,0x12,0x44,0xb5,0x90,0x91,0x17,0xe0, ++0x04,0xf0,0x21,0xd9,0xd0,0xd0,0x92,0xaf,0x22,0x90,0x91,0x56,0xe0,0xc4,0x13,0x13, ++0x13,0x54,0x01,0x30,0xe0,0x11,0xe0,0x44,0x80,0xf0,0x90,0x91,0x5e,0xe0,0xc4,0x54, ++0x0f,0x20,0xe0,0x03,0x7f,0x00,0x22,0x7f,0x01,0x22,0x8f,0x1f,0xe4,0x90,0x91,0x22, ++0xf0,0xe5,0x1f,0x14,0xfe,0x90,0x91,0x22,0xe0,0xff,0xc3,0x9e,0x50,0x0e,0xef,0x04, ++0xfd,0x12,0x34,0xb7,0x90,0x91,0x22,0xe0,0x04,0xf0,0x80,0xe5,0xe5,0x1f,0x14,0xff, ++0x7d,0xff,0x12,0x34,0xb7,0x90,0x91,0x22,0xe5,0x1f,0xf0,0x90,0x91,0x22,0xe0,0xc3, ++0x94,0xff,0x50,0x0f,0xe0,0xff,0x04,0xfd,0x12,0x34,0xb7,0x90,0x91,0x22,0xe0,0x04, ++0xf0,0x80,0xe8,0xad,0x1f,0x7f,0xff,0x02,0x34,0xb7,0xc3,0xee,0x94,0x01,0x40,0x0a, ++0x0d,0xed,0x13,0x90,0xfd,0x10,0xf0,0xe4,0x2f,0xff,0x22,0xc3,0xee,0x94,0x01,0x40, ++0x1e,0x90,0xfd,0x11,0xe0,0xb5,0x05,0x14,0x90,0x01,0x17,0xe0,0xb5,0x05,0x07,0x90, ++0xfd,0x11,0xe4,0xf0,0x80,0x06,0xed,0x04,0x90,0xfd,0x11,0xf0,0xe4,0x2f,0xff,0x22, ++0x0f,0x75,}; ++ ++u8 Rtl8192CUFwUMCACutWWImgArray[UMCACutWWImgArrayLength] = { ++0xc1,0x88,0x02,0x00,0x51,0x00,0x00,0x00,0x03,0x23,0x16,0x44,0x72,0x34,0x01,0x00, ++0x58,0x92,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x02,0x43,0x9d,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x02,0x57,0xcb,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x02,0x5c,0xb6,0x00,0x00,0x00,0x00,0x00,0x02,0x5d,0x99,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0xbb,0x01,0x0c,0xe5,0x82,0x29,0xf5,0x82,0xe5,0x83,0x3a,0xf5,0x83,0xe0,0x22,0x50, ++0x06,0xe9,0x25,0x82,0xf8,0xe6,0x22,0xbb,0xfe,0x06,0xe9,0x25,0x82,0xf8,0xe2,0x22, ++0xe5,0x82,0x29,0xf5,0x82,0xe5,0x83,0x3a,0xf5,0x83,0xe4,0x93,0x22,0xbb,0x01,0x06, ++0x89,0x82,0x8a,0x83,0xf0,0x22,0x50,0x02,0xf7,0x22,0xbb,0xfe,0x01,0xf3,0x22,0xf8, ++0xbb,0x01,0x0d,0xe5,0x82,0x29,0xf5,0x82,0xe5,0x83,0x3a,0xf5,0x83,0xe8,0xf0,0x22, ++0x50,0x06,0xe9,0x25,0x82,0xc8,0xf6,0x22,0xbb,0xfe,0x05,0xe9,0x25,0x82,0xc8,0xf2, ++0x22,0xc5,0xf0,0xf8,0xa3,0xe0,0x28,0xf0,0xc5,0xf0,0xf8,0xe5,0x82,0x15,0x82,0x70, ++0x02,0x15,0x83,0xe0,0x38,0xf0,0x22,0xbb,0x01,0x10,0xe5,0x82,0x29,0xf5,0x82,0xe5, ++0x83,0x3a,0xf5,0x83,0xe0,0xf5,0xf0,0xa3,0xe0,0x22,0x50,0x09,0xe9,0x25,0x82,0xf8, ++0x86,0xf0,0x08,0xe6,0x22,0xbb,0xfe,0x0a,0xe9,0x25,0x82,0xf8,0xe2,0xf5,0xf0,0x08, ++0xe2,0x22,0xe5,0x83,0x2a,0xf5,0x83,0xe9,0x93,0xf5,0xf0,0xa3,0xe9,0x93,0x22,0xf8, ++0xbb,0x01,0x11,0xe5,0x82,0x29,0xf5,0x82,0xe5,0x83,0x3a,0xf5,0x83,0xe8,0xf0,0xe5, ++0xf0,0xa3,0xf0,0x22,0x50,0x09,0xe9,0x25,0x82,0xc8,0xf6,0x08,0xa6,0xf0,0x22,0xbb, ++0xfe,0x09,0xe9,0x25,0x82,0xc8,0xf2,0xe5,0xf0,0x08,0xf2,0x22,0xef,0x4b,0xff,0xee, ++0x4a,0xfe,0xed,0x49,0xfd,0xec,0x48,0xfc,0x22,0xe0,0xfc,0xa3,0xe0,0xfd,0xa3,0xe0, ++0xfe,0xa3,0xe0,0xff,0x22,0xa4,0x25,0x82,0xf5,0x82,0xe5,0xf0,0x35,0x83,0xf5,0x83, ++0x22,0xe0,0xfb,0xa3,0xe0,0xfa,0xa3,0xe0,0xf9,0x22,0xf8,0xe0,0xfb,0xa3,0xa3,0xe0, ++0xf9,0x25,0xf0,0xf0,0xe5,0x82,0x15,0x82,0x70,0x02,0x15,0x83,0xe0,0xfa,0x38,0xf0, ++0x22,0xeb,0xf0,0xa3,0xea,0xf0,0xa3,0xe9,0xf0,0x22,0xd0,0x83,0xd0,0x82,0xf8,0xe4, ++0x93,0x70,0x12,0x74,0x01,0x93,0x70,0x0d,0xa3,0xa3,0x93,0xf8,0x74,0x01,0x93,0xf5, ++0x82,0x88,0x83,0xe4,0x73,0x74,0x02,0x93,0x68,0x60,0xef,0xa3,0xa3,0xa3,0x80,0xdf, ++0xd0,0x83,0xd0,0x82,0xf8,0xe4,0x93,0x70,0x12,0x74,0x01,0x93,0x70,0x0d,0xa3,0xa3, ++0x93,0xf8,0x74,0x01,0x93,0xf5,0x82,0x88,0x83,0xe4,0x73,0x74,0x02,0x93,0xb5,0xf0, ++0x06,0x74,0x03,0x93,0x68,0x60,0xe9,0xa3,0xa3,0xa3,0xa3,0x80,0xd8,0x02,0x43,0xdb, ++0x02,0x50,0x2a,0xe4,0x93,0xa3,0xf8,0xe4,0x93,0xa3,0x40,0x03,0xf6,0x80,0x01,0xf2, ++0x08,0xdf,0xf4,0x80,0x29,0xe4,0x93,0xa3,0xf8,0x54,0x07,0x24,0x0c,0xc8,0xc3,0x33, ++0xc4,0x54,0x0f,0x44,0x20,0xc8,0x83,0x40,0x04,0xf4,0x56,0x80,0x01,0x46,0xf6,0xdf, ++0xe4,0x80,0x0b,0x01,0x02,0x04,0x08,0x10,0x20,0x40,0x80,0x90,0x44,0x20,0xe4,0x7e, ++0x01,0x93,0x60,0xbc,0xa3,0xff,0x54,0x3f,0x30,0xe5,0x09,0x54,0x1f,0xfe,0xe4,0x93, ++0xa3,0x60,0x01,0x0e,0xcf,0x54,0xc0,0x25,0xe0,0x60,0xa8,0x40,0xb8,0xe4,0x93,0xa3, ++0xfa,0xe4,0x93,0xa3,0xf8,0xe4,0x93,0xa3,0xc8,0xc5,0x82,0xc8,0xca,0xc5,0x83,0xca, ++0xf0,0xa3,0xc8,0xc5,0x82,0xc8,0xca,0xc5,0x83,0xca,0xdf,0xe9,0xde,0xe7,0x80,0xbe, ++0x41,0x91,0x40,0x00,0x41,0x91,0x9c,0x00,0x41,0x91,0x23,0x80,0x41,0x91,0x24,0x80, ++0x41,0x91,0x9e,0x00,0x41,0x91,0x52,0x00,0x41,0x91,0x93,0x00,0x41,0x91,0x91,0x00, ++0x41,0x91,0x90,0x00,0x41,0x91,0x92,0x00,0x00,0xf0,0x90,0x91,0x30,0xe0,0x90,0x91, ++0x67,0xf0,0xe4,0xfb,0xfd,0x7f,0x54,0x7e,0x01,0xd3,0x10,0xaf,0x01,0xc3,0xc0,0xd0, ++0x90,0x91,0x65,0xeb,0xf0,0xa3,0xe0,0xfb,0xa3,0xe0,0xf5,0x44,0xe4,0xf5,0x45,0x12, ++0x30,0x62,0xd0,0xd0,0x92,0xaf,0x22,0x90,0x01,0x5f,0xe4,0xf0,0x90,0x01,0x3c,0x74, ++0x08,0xf0,0xe4,0x90,0x91,0x66,0xf0,0x90,0x91,0x2d,0xe0,0x90,0x91,0x67,0xf0,0xe4, ++0xfb,0xfd,0x7f,0x5c,0x7e,0x01,0x91,0x59,0x90,0x01,0x5f,0x74,0x05,0xf0,0x90,0x06, ++0x92,0x74,0x02,0xf0,0x90,0x91,0x36,0x14,0xf0,0xe5,0x6e,0x54,0x0f,0xc3,0x94,0x0c, ++0x50,0x02,0xf1,0x23,0x22,0x90,0x02,0x84,0xef,0xf0,0xa3,0xee,0xf0,0xa3,0x74,0x05, ++0xf0,0x22,0x7d,0x01,0xaf,0x6f,0xe1,0x27,0xf1,0xe6,0xbf,0x01,0x10,0x90,0x91,0x42, ++0xe0,0xff,0xe4,0xfd,0x12,0x48,0x22,0x90,0x04,0x1f,0x74,0x20,0xf0,0x22,0x8f,0x82, ++0x8e,0x83,0xa3,0xa3,0xa3,0xe4,0xf0,0x22,0xe4,0xf5,0x72,0x7f,0x60,0x7e,0x01,0x80, ++0xed,0x7f,0x00,0x22,0x90,0x91,0x53,0xe0,0x54,0xfe,0xf0,0x02,0x50,0xd6,0x22,0xe4, ++0xf5,0x75,0x22,0x02,0x5f,0xe2,0x02,0x5f,0xe9,0xef,0x8e,0xf0,0x71,0x70,0x45,0x26, ++0x00,0x40,0x45,0x4e,0x00,0x80,0x45,0x79,0x01,0x00,0x45,0x8d,0x02,0x00,0x45,0xa5, ++0x04,0x00,0x00,0x00,0x45,0xc2,0xed,0x54,0x3f,0x70,0x04,0xfe,0xff,0x80,0x04,0x7e, ++0x00,0x7f,0x40,0xef,0x2d,0xff,0xee,0x3c,0xfe,0xef,0x78,0x06,0xce,0xc3,0x13,0xce, ++0x13,0xd8,0xf9,0x78,0x06,0xc3,0x33,0xce,0x33,0xce,0xd8,0xf9,0x80,0x26,0xed,0x54, ++0x7f,0x70,0x04,0xfe,0xff,0x80,0x04,0x7e,0x00,0x7f,0x80,0xef,0x2d,0xff,0xee,0x3c, ++0xfe,0xef,0x78,0x07,0xce,0xc3,0x13,0xce,0x13,0xd8,0xf9,0x78,0x07,0xc3,0x33,0xce, ++0x33,0xce,0xd8,0xf9,0xfd,0xac,0x06,0x80,0x49,0xed,0x70,0x04,0xfe,0xff,0x80,0x04, ++0x7e,0x01,0x7f,0x00,0xef,0x2d,0xee,0x3c,0x7d,0x00,0xfc,0x80,0x35,0xec,0x54,0x01, ++0x4d,0x70,0x04,0xfe,0xff,0x80,0x04,0x7e,0x02,0x7f,0x00,0xef,0x2d,0xee,0x3c,0xc3, ++0x13,0x7d,0x00,0x80,0x1a,0xec,0x54,0x03,0x4d,0x70,0x04,0xfe,0xff,0x80,0x04,0x7e, ++0x04,0x7f,0x00,0xef,0x2d,0xee,0x3c,0x13,0x13,0x54,0x3f,0x7d,0x00,0x25,0xe0,0x25, ++0xe0,0xfc,0xae,0x04,0xaf,0x05,0x22,0x90,0x91,0x09,0x12,0x25,0x14,0x00,0x00,0x00, ++0x00,0x90,0x06,0xa9,0xe0,0x90,0x91,0x08,0xf0,0xe0,0x54,0xc0,0x70,0x0a,0x53,0x71, ++0xfe,0x53,0x71,0xfd,0x91,0xc2,0x80,0x47,0x90,0x91,0x26,0xe0,0x60,0x41,0x90,0x91, ++0x38,0xe0,0x70,0x3b,0x90,0x91,0x38,0x74,0x01,0xf0,0x7f,0x00,0x7e,0x08,0x12,0x22, ++0x65,0x90,0x91,0x09,0x12,0x25,0x08,0x90,0x91,0x09,0x71,0x09,0xec,0x44,0x02,0xfc, ++0x90,0x91,0x09,0x12,0x25,0x08,0x90,0x91,0x09,0x71,0x09,0x90,0x80,0x96,0x12,0x25, ++0x08,0x7f,0x00,0x7e,0x08,0x12,0x2b,0x08,0x90,0x02,0x86,0xe0,0x54,0xfb,0xf0,0x90, ++0x91,0x08,0xe0,0x30,0xe6,0x13,0x43,0x71,0x01,0x90,0x91,0x3b,0xe0,0x64,0x02,0x60, ++0x04,0x91,0xc8,0x80,0x07,0x91,0x77,0x80,0x03,0x53,0x71,0xfe,0x90,0x91,0x08,0xe0, ++0x30,0xe7,0x16,0x43,0x71,0x02,0xe4,0x90,0x91,0x66,0x91,0x49,0x90,0x01,0x57,0x74, ++0x05,0xf0,0x90,0x91,0x3c,0x74,0x01,0xf0,0x22,0x53,0x71,0xfd,0x22,0xd3,0x10,0xaf, ++0x01,0xc3,0xc0,0xd0,0x8b,0x60,0x8a,0x61,0x89,0x62,0x90,0x91,0x68,0x71,0x41,0xab, ++0x63,0xaa,0x64,0xa9,0x65,0x90,0x91,0x6b,0x71,0x41,0xaf,0x66,0x15,0x66,0xef,0x60, ++0x1b,0x90,0x91,0x6b,0xe4,0x75,0xf0,0x01,0x71,0x2a,0x12,0x24,0x62,0xff,0x90,0x91, ++0x68,0xe4,0x75,0xf0,0x01,0x71,0x2a,0xef,0x51,0x4d,0x80,0xde,0xab,0x60,0xaa,0x61, ++0xa9,0x62,0xd0,0xd0,0x92,0xaf,0x22,0xd3,0x10,0xaf,0x01,0xc3,0xc0,0xd0,0x90,0x91, ++0x6e,0x71,0x41,0x90,0x91,0x9e,0xe0,0xff,0x04,0xf0,0x90,0x00,0x01,0xef,0x51,0x5f, ++0x7f,0xaf,0x7e,0x01,0x12,0x64,0x1c,0xef,0x60,0x44,0x90,0x91,0x6e,0x71,0x21,0x8b, ++0x63,0x8a,0x64,0x89,0x65,0x75,0x66,0x02,0x7b,0x01,0x7a,0x01,0x79,0xa0,0xd1,0x6d, ++0x90,0x91,0x71,0x71,0x21,0x8b,0x63,0x8a,0x64,0x89,0x65,0x90,0x91,0x6e,0x71,0x21, ++0x12,0x24,0x62,0xff,0xc4,0x54,0x0f,0xf5,0x66,0x7b,0x01,0x7a,0x01,0x79,0xa2,0xd1, ++0x6d,0x90,0x01,0xaf,0x74,0xff,0xf0,0x90,0x01,0xcb,0xe0,0x64,0x80,0xf0,0xd0,0xd0, ++0x92,0xaf,0x22,0x7d,0x01,0x7f,0x0c,0x90,0x91,0x95,0xed,0xf0,0x90,0x91,0x94,0xef, ++0xf0,0x54,0x0f,0xff,0xe5,0x6e,0x54,0x0f,0x6f,0x60,0x76,0x90,0x91,0x94,0xe0,0x30, ++0xe2,0x30,0xe5,0x6e,0x20,0xe2,0x05,0x7f,0x01,0x12,0x62,0x65,0xe5,0x6e,0x30,0xe3, ++0x0f,0x90,0x91,0x94,0xe0,0x20,0xe3,0x08,0x12,0x5a,0x3f,0xef,0x60,0x53,0x80,0x52, ++0xe5,0x6e,0x20,0xe3,0x4c,0x90,0x91,0x94,0xe0,0x30,0xe3,0x45,0xa3,0xe0,0xff,0x02, ++0x62,0x4a,0xe5,0x6e,0x54,0x0f,0xff,0xbf,0x0c,0x0f,0x90,0x91,0x94,0xe0,0x20,0xe3, ++0x08,0x12,0x5a,0x3f,0xef,0x60,0x2a,0xf1,0xb2,0xe5,0x6e,0x54,0x0f,0xff,0xbf,0x04, ++0x10,0x90,0x91,0x94,0xe0,0x20,0xe2,0x09,0x12,0x5b,0xb3,0xef,0x60,0x13,0x12,0x48, ++0xce,0xe5,0x6e,0x54,0x0f,0xff,0xbf,0x02,0x08,0x91,0xf1,0xef,0x60,0x03,0x12,0x63, ++0x56,0x22,0x90,0x06,0x04,0xe0,0x44,0x40,0xf0,0xe5,0x6d,0xb4,0x01,0x04,0x7f,0x01, ++0xf1,0xc9,0x53,0x6e,0xf0,0x43,0x6e,0x04,0x22,0x8f,0x67,0xf1,0xe6,0xbf,0x01,0x15, ++0x90,0x91,0x43,0x12,0x48,0x1e,0xad,0x07,0xac,0x06,0xaf,0x67,0x12,0x61,0xa3,0x90, ++0x04,0x1f,0x74,0x20,0xf0,0x22,0xd3,0x10,0xaf,0x01,0xc3,0xc0,0xd0,0x90,0x01,0xc4, ++0x74,0xe6,0xf0,0x74,0x47,0xa3,0xf0,0x90,0x04,0x1d,0xe0,0x60,0x1a,0x90,0x05,0x22, ++0xe0,0x54,0x90,0x60,0x07,0x90,0x01,0xc6,0xe0,0x44,0x40,0xf0,0x90,0x01,0xc7,0xe0, ++0x30,0xe1,0xe4,0x7f,0x00,0x80,0x02,0x7f,0x01,0xd0,0xd0,0x92,0xaf,0x22,0xe0,0xff, ++0x7d,0x01,0x90,0x91,0x74,0xef,0xf0,0xa3,0xed,0xf0,0xe4,0xa3,0xf0,0xa3,0xf0,0xe5, ++0x70,0x60,0x04,0xe4,0xff,0x11,0xb3,0x90,0x91,0x74,0xe0,0x30,0xe0,0x09,0x90,0x91, ++0x76,0xe4,0xf0,0xa3,0x74,0x80,0xf0,0x90,0x91,0x74,0xe0,0xff,0xc3,0x13,0x90,0xfd, ++0x10,0xf0,0x90,0x04,0x25,0xef,0xf0,0x90,0x91,0x75,0xe0,0x60,0x1f,0xa3,0xa3,0xe0, ++0xff,0x24,0x0f,0xf5,0x82,0xe4,0x34,0xfc,0xf5,0x83,0xe0,0x44,0x80,0xf0,0x74,0x10, ++0x2f,0xf5,0x82,0xe4,0x34,0xfc,0xf5,0x83,0xe0,0x44,0x80,0xf0,0x90,0x91,0x76,0xa3, ++0xe0,0xff,0xfd,0x24,0x08,0xf5,0x82,0xe4,0x34,0xfc,0xf5,0x83,0xe4,0xf0,0x74,0x09, ++0x2d,0xf5,0x82,0xe4,0x34,0xfc,0xf5,0x83,0xe0,0x54,0xf0,0xf0,0x74,0x21,0x2f,0xf5, ++0x82,0xe4,0x34,0xfc,0xf5,0x83,0xe0,0x54,0xf7,0xf0,0x90,0x91,0x76,0xe0,0xfe,0xa3, ++0xe0,0xff,0x22,0xef,0x60,0x0b,0x90,0x91,0x51,0xe0,0xb4,0x01,0x10,0xe4,0xff,0x80, ++0x09,0x90,0x91,0x51,0xe0,0xb4,0x01,0x05,0x7f,0x01,0x12,0x68,0x87,0x22,0x90,0x01, ++0x37,0x74,0x02,0xf0,0x90,0x05,0x22,0x74,0xff,0xf0,0x12,0x68,0x46,0xef,0x70,0x06, ++0x90,0x01,0xc8,0x74,0xfd,0xf0,0x7d,0x02,0x7f,0x03,0x12,0x31,0x9d,0xe5,0x70,0x60, ++0x04,0x7f,0x01,0x11,0xb3,0x51,0x0c,0x53,0x6e,0xf0,0x43,0x6e,0x02,0x22,0xef,0x64, ++0x01,0x70,0x42,0x7d,0x78,0x7f,0x02,0x12,0x31,0x2c,0x7d,0x02,0x7f,0x03,0x12,0x31, ++0x2c,0x90,0x01,0x36,0x74,0x03,0xf0,0xfd,0x7f,0x02,0x12,0x31,0x9d,0x7d,0x10,0x7f, ++0x03,0x12,0x31,0x49,0x90,0x01,0x57,0xe4,0xf0,0x90,0x01,0x3c,0x74,0x02,0xf0,0x12, ++0x47,0x23,0xe4,0xff,0x11,0xb3,0x90,0x06,0x04,0xe0,0x54,0x7f,0xf0,0x90,0x06,0x0a, ++0xe0,0x54,0xf8,0xf0,0x22,0x90,0x01,0x36,0x74,0x7b,0xf0,0xa3,0x74,0x02,0xf0,0x7d, ++0x7b,0xff,0x12,0x31,0x9d,0x7d,0x02,0x7f,0x03,0x12,0x31,0x9d,0x7d,0x10,0x7f,0x03, ++0x12,0x31,0x49,0x90,0x06,0x04,0xe0,0x44,0x80,0xf0,0x90,0x06,0x0a,0xe0,0x44,0x07, ++0xf0,0x12,0x64,0x11,0xe5,0x6d,0x20,0xe0,0x05,0xe4,0x90,0x91,0x29,0xf0,0x22,0x8b, ++0x0e,0x8a,0x0f,0x89,0x10,0x12,0x62,0x3e,0xab,0x0e,0xaa,0x0f,0xa9,0x10,0x12,0x24, ++0x62,0xf5,0x70,0x14,0x60,0x0e,0x14,0x60,0x1e,0x14,0x60,0x2f,0x24,0x03,0x70,0x40, ++0x7f,0x01,0x80,0x3a,0xab,0x0e,0xaa,0x0f,0xa9,0x10,0x90,0x00,0x02,0x12,0x42,0x20, ++0xfd,0xe4,0xff,0x31,0xe1,0x80,0x27,0xab,0x0e,0xaa,0x0f,0xa9,0x10,0x90,0x00,0x02, ++0x12,0x42,0x20,0xfd,0x7f,0x01,0x31,0xe1,0x1f,0x80,0x13,0xab,0x0e,0xaa,0x0f,0xa9, ++0x10,0x90,0x00,0x02,0x12,0x42,0x20,0xfd,0x7f,0x02,0x31,0xe1,0xe4,0xff,0x11,0xfe, ++0x22,0xef,0x24,0xfe,0x60,0x0b,0x04,0x70,0x22,0x90,0x91,0x39,0x74,0x01,0xf0,0x80, ++0x16,0xed,0x70,0x0a,0x90,0x91,0x35,0xe0,0x90,0x91,0x39,0xf0,0x80,0x05,0x90,0x91, ++0x39,0xed,0xf0,0x90,0x91,0x39,0xe0,0x90,0x91,0x27,0xf0,0x22,0x7f,0x78,0x7e,0x08, ++0x12,0x22,0x65,0x90,0x90,0xd8,0x12,0x25,0x08,0x7f,0x04,0x7e,0x0c,0x12,0x22,0x65, ++0x90,0x90,0xdc,0x12,0x25,0x08,0x7f,0x00,0x7e,0x08,0x12,0x22,0x65,0x90,0x90,0xe0, ++0x12,0x25,0x08,0x90,0x91,0x51,0xe0,0x90,0x90,0xd8,0xb4,0x01,0x0d,0x12,0x43,0x09, ++0xef,0x54,0xc7,0xff,0xed,0x54,0xc7,0xfd,0x80,0x07,0x12,0x43,0x09,0xef,0x54,0xc7, ++0xff,0xec,0x90,0x80,0x96,0x12,0x25,0x08,0x7f,0x78,0x7e,0x08,0x12,0x2b,0x08,0x90, ++0x90,0xdc,0x12,0x43,0x09,0xef,0x54,0x0f,0xff,0xec,0x90,0x80,0x96,0x12,0x25,0x08, ++0x7f,0x04,0x7e,0x0c,0x12,0x2b,0x08,0x90,0x90,0xe0,0x12,0x43,0x09,0xef,0x44,0x02, ++0xff,0xec,0x90,0x80,0x96,0x12,0x25,0x08,0x7f,0x00,0x7e,0x08,0x12,0x2b,0x08,0x7f, ++0x70,0x7e,0x0e,0x12,0x22,0x65,0x90,0x90,0xe4,0x12,0x25,0x08,0x90,0x80,0x96,0x12, ++0x25,0x14,0x00,0x1b,0x25,0xa0,0x7f,0x70,0x7e,0x0e,0x12,0x2b,0x08,0x90,0x80,0x68, ++0x12,0x25,0x14,0x00,0x00,0x00,0x00,0xe4,0xfd,0xff,0x12,0x30,0x2c,0x90,0x91,0x51, ++0xe0,0xb4,0x01,0x11,0x90,0x80,0x68,0x12,0x25,0x14,0x00,0x00,0x00,0x00,0xe4,0xfd, ++0x7f,0x01,0x12,0x30,0x2c,0x90,0x00,0x11,0xe0,0x54,0xf6,0xf0,0x80,0x08,0xf4,0xff, ++0x90,0x00,0x43,0xe0,0x5f,0xf0,0xd3,0x10,0xaf,0x01,0xc3,0xc0,0xd0,0x7f,0x10,0xdf, ++0xfe,0xd0,0xd0,0x92,0xaf,0x22,0xd3,0x10,0xaf,0x01,0xc3,0xc0,0xd0,0x90,0x91,0x9b, ++0xed,0xf0,0x90,0x91,0x9a,0xef,0xf0,0xd3,0x94,0x07,0x50,0x63,0xe0,0xff,0x74,0x01, ++0xa8,0x07,0x08,0x80,0x02,0xc3,0x33,0xd8,0xfc,0xf4,0xff,0x90,0x00,0x47,0xe0,0x5f, ++0xf0,0x51,0xe6,0x90,0x91,0x9a,0xe0,0xff,0x74,0x01,0xa8,0x07,0x08,0x80,0x02,0xc3, ++0x33,0xd8,0xfc,0xff,0x90,0x00,0x46,0xe0,0x4f,0xf0,0x51,0xe6,0x90,0x91,0x9b,0xe0, ++0x60,0x16,0x90,0x91,0x9a,0xe0,0xff,0x74,0x01,0xa8,0x07,0x08,0x80,0x02,0xc3,0x33, ++0xd8,0xfc,0xff,0x90,0x00,0x45,0x80,0x66,0x90,0x91,0x9a,0xe0,0xff,0x74,0x01,0xa8, ++0x07,0x08,0x80,0x02,0xc3,0x33,0xd8,0xfc,0xf4,0xff,0x90,0x00,0x45,0x80,0x6b,0x90, ++0x91,0x9a,0xe0,0x24,0xf8,0xf0,0xe0,0xff,0x74,0x01,0xa8,0x07,0x08,0x80,0x02,0xc3, ++0x33,0xd8,0xfc,0xc4,0x54,0xf0,0x51,0xde,0x90,0x91,0x9a,0xe0,0xff,0x74,0x01,0xa8, ++0x07,0x08,0x80,0x02,0xc3,0x33,0xd8,0xfc,0xff,0x90,0x00,0x43,0xe0,0x4f,0xf0,0x51, ++0xe6,0x90,0x91,0x9b,0xe0,0x60,0x1b,0x90,0x91,0x9a,0xe0,0xff,0x74,0x01,0xa8,0x07, ++0x08,0x80,0x02,0xc3,0x33,0xd8,0xfc,0xc4,0x54,0xf0,0xff,0x90,0x00,0x42,0xe0,0x4f, ++0x80,0x1a,0x90,0x91,0x9a,0xe0,0xff,0x74,0x01,0xa8,0x07,0x08,0x80,0x02,0xc3,0x33, ++0xd8,0xfc,0xc4,0x54,0xf0,0xf4,0xff,0x90,0x00,0x42,0xe0,0x5f,0xf0,0x51,0xe6,0xd0, ++0xd0,0x92,0xaf,0x22,0xf0,0x90,0x00,0x45,0xe0,0x54,0xfe,0xfd,0x7f,0x45,0xd3,0x10, ++0xaf,0x01,0xc3,0xc0,0xd0,0x8f,0x82,0x75,0x83,0x00,0xed,0xf0,0x51,0xe6,0xd0,0xd0, ++0x92,0xaf,0x22,0xef,0x14,0x60,0x30,0x14,0x60,0x66,0x24,0x02,0x60,0x02,0x81,0xaa, ++0x90,0x90,0xf3,0x74,0x02,0xf0,0x90,0x00,0x48,0xe0,0x44,0x0c,0xfd,0x7f,0x48,0x71, ++0xee,0x90,0x00,0x47,0xe0,0x44,0x08,0xfd,0x7f,0x47,0x71,0xee,0x90,0x00,0x45,0xe0, ++0x44,0x10,0xfd,0x7f,0x45,0x80,0x71,0xe4,0x90,0x90,0xf3,0xf0,0x90,0x90,0xef,0x12, ++0x43,0x09,0x90,0x80,0x96,0x12,0x25,0x08,0x7f,0x80,0x7e,0x08,0x12,0x2b,0x08,0x90, ++0x00,0x45,0xe0,0x44,0xef,0xfd,0x7f,0x45,0x71,0xee,0x90,0x00,0x45,0xe0,0x54,0xef, ++0xfd,0x7f,0x45,0x71,0xee,0x90,0x00,0x46,0xe0,0x44,0x10,0xfd,0x7f,0x46,0x80,0x38, ++0x90,0x90,0xf3,0x74,0x01,0xf0,0x90,0x90,0xf9,0x12,0x43,0x09,0x90,0x80,0x96,0x12, ++0x25,0x08,0x7f,0x80,0x7e,0x08,0x12,0x2b,0x08,0x90,0x00,0x45,0xe0,0x44,0x20,0xfd, ++0x7f,0x45,0x71,0xee,0x90,0x00,0x45,0xe0,0x44,0x10,0xfd,0x7f,0x45,0x71,0xee,0x90, ++0x00,0x46,0xe0,0x44,0x10,0xfd,0x7f,0x46,0x71,0xee,0x22,0x90,0x00,0x02,0x12,0x42, ++0x20,0x90,0x90,0xf5,0xf0,0x90,0x00,0x01,0x12,0x42,0x20,0x25,0xe0,0x25,0xe0,0x90, ++0x90,0xf4,0xf0,0x12,0x24,0x62,0x25,0xe0,0x25,0xe0,0x90,0x90,0xf8,0xf0,0x90,0x05, ++0x60,0xe0,0x90,0x91,0x03,0xf0,0x90,0x05,0x61,0xe0,0x90,0x91,0x04,0xf0,0x90,0x05, ++0x62,0xe0,0x90,0x91,0x05,0xf0,0x90,0x05,0x63,0xe0,0x90,0x91,0x06,0xf0,0xa2,0xaf, ++0xe4,0x33,0x90,0x91,0x1c,0xf0,0xc2,0xaf,0x90,0x90,0xf4,0xe0,0xff,0x12,0x6e,0x67, ++0x90,0x91,0x1c,0xe0,0x24,0xff,0x92,0xaf,0x90,0x90,0xf5,0xe0,0x70,0x02,0xa1,0xb2, ++0x90,0x90,0xf4,0xe0,0x70,0x02,0xa1,0xb2,0x90,0x90,0xf8,0xe0,0x70,0x02,0xa1,0xb2, ++0xa2,0xaf,0xe4,0x33,0x90,0x91,0x1c,0xf0,0xc2,0xaf,0x90,0x91,0x07,0x74,0x01,0xf0, ++0x90,0x91,0x1c,0xe0,0x24,0xff,0x92,0xaf,0x71,0xe5,0x90,0x00,0x46,0xe0,0x44,0x01, ++0xfd,0x7f,0x46,0x71,0xee,0x90,0x90,0xed,0xe0,0x60,0x15,0x90,0x90,0xf9,0x12,0x43, ++0x09,0x90,0x80,0x96,0x12,0x25,0x08,0x7f,0x80,0x7e,0x08,0x12,0x2b,0x08,0x80,0x06, ++0x90,0x05,0x22,0x74,0x7f,0xf0,0x90,0x00,0x45,0xe0,0x54,0xef,0xfd,0x7f,0x45,0x71, ++0xee,0x90,0x05,0x87,0xe0,0x64,0x80,0xf0,0x90,0x91,0x03,0xe0,0x90,0x05,0x84,0xf0, ++0x90,0x91,0x04,0xe0,0x90,0x05,0x85,0xf0,0x90,0x91,0x05,0xe0,0x90,0x05,0x86,0xf0, ++0x90,0x91,0x06,0xe0,0x90,0x05,0x87,0xf0,0xa2,0xaf,0xe4,0x33,0x90,0x91,0x1c,0xf0, ++0xc2,0xaf,0x90,0x01,0x3c,0xe0,0x44,0x20,0xf0,0x7d,0x20,0xe4,0xff,0x12,0x31,0xb7, ++0x80,0x2b,0x90,0x90,0xf5,0xe0,0x70,0x2d,0x90,0x91,0x07,0x71,0xe4,0x90,0x00,0x46, ++0xe0,0x54,0xfe,0xfd,0x7f,0x46,0x71,0xee,0x90,0x05,0x22,0xe4,0xf0,0xa2,0xaf,0x33, ++0x90,0x91,0x1c,0xf0,0xc2,0xaf,0x7d,0x20,0xe4,0xff,0x12,0x31,0x49,0x90,0x91,0x1c, ++0xe0,0x24,0xff,0x92,0xaf,0x22,0x8b,0x0e,0x8a,0x0f,0x89,0x10,0x90,0x00,0x02,0x12, ++0x42,0x20,0x90,0x90,0xf6,0xf0,0xe0,0x30,0xe0,0x4b,0x90,0x90,0xed,0x74,0x01,0xf0, ++0x7f,0x80,0x7e,0x08,0x12,0x22,0x65,0x90,0x90,0xef,0x12,0x25,0x08,0xab,0x0e,0xaa, ++0x0f,0xa9,0x10,0x90,0x00,0x01,0x12,0x42,0x20,0xff,0xe4,0xfc,0xfd,0xfe,0x78,0x1a, ++0x12,0x24,0xf5,0xa8,0x04,0xa9,0x05,0xaa,0x06,0xab,0x07,0x90,0x90,0xef,0x12,0x43, ++0x09,0xec,0x54,0x03,0xfc,0x12,0x42,0xfc,0x90,0x90,0xf9,0x12,0x25,0x08,0x90,0x05, ++0x22,0xe4,0xf0,0x80,0x2d,0xe4,0x90,0x90,0xed,0xf0,0x7f,0x80,0x7e,0x08,0x12,0x22, ++0x65,0xec,0x54,0x03,0xfc,0xec,0x44,0xc0,0xfc,0x90,0x90,0xef,0x12,0x25,0x08,0x90, ++0x90,0xef,0x12,0x43,0x09,0x90,0x80,0x96,0x12,0x25,0x08,0x7f,0x80,0x7e,0x08,0x12, ++0x2b,0x08,0x90,0x90,0xf6,0xe0,0x30,0xe1,0x19,0x7d,0x0c,0x7f,0x47,0x71,0xee,0x90, ++0x00,0x48,0xe0,0x44,0x0c,0xfd,0x7f,0x48,0x71,0xee,0x90,0x00,0x46,0xe0,0x44,0x10, ++0x80,0x1c,0x90,0x00,0x47,0xe0,0x54,0xf3,0xfd,0x7f,0x47,0x71,0xee,0x90,0x00,0x48, ++0xe0,0x54,0xf3,0xfd,0x7f,0x48,0x71,0xee,0x90,0x00,0x46,0xe0,0x54,0xef,0xfd,0x7f, ++0x46,0x71,0xee,0xe4,0x90,0x90,0xf3,0xf0,0x22,0x90,0x01,0x3c,0x74,0xff,0xf0,0xa3, ++0xf0,0xa3,0xf0,0x90,0x01,0x34,0xf0,0xa3,0xf0,0xa3,0xf0,0xa3,0xf0,0xfd,0x7f,0x54, ++0x71,0xee,0x7d,0xff,0x7f,0x55,0x71,0xee,0x7d,0xff,0x7f,0x56,0x71,0xee,0x7d,0xff, ++0x7f,0x57,0x61,0xee,0x90,0x01,0x30,0xe4,0xf0,0xa3,0xf0,0xa3,0xf0,0xa3,0xf0,0x90, ++0x01,0x38,0xf0,0xa3,0xf0,0xa3,0xf0,0xa3,0xf0,0xfd,0x7f,0x50,0x71,0xee,0xe4,0xfd, ++0x7f,0x51,0x71,0xee,0xe4,0xfd,0x7f,0x52,0x71,0xee,0xe4,0xfd,0x7f,0x53,0x61,0xee, ++0xd3,0x10,0xaf,0x01,0xc3,0xc0,0xd0,0x90,0x91,0x22,0xed,0xf0,0x90,0x91,0x21,0xef, ++0xf0,0xd3,0x94,0x07,0x50,0x4e,0xa3,0xe0,0x70,0x1a,0x90,0x91,0x21,0xe0,0xff,0x74, ++0x01,0xa8,0x07,0x08,0x80,0x02,0xc3,0x33,0xd8,0xfc,0xf4,0xff,0x90,0x00,0x47,0xe0, ++0x5f,0xf0,0x80,0x17,0x90,0x91,0x21,0xe0,0xff,0x74,0x01,0xa8,0x07,0x08,0x80,0x02, ++0xc3,0x33,0xd8,0xfc,0xff,0x90,0x00,0x47,0xe0,0x4f,0xf0,0x51,0xe6,0x90,0x91,0x21, ++0xe0,0xff,0x74,0x01,0xa8,0x07,0x08,0x80,0x02,0xc3,0x33,0xd8,0xfc,0xf4,0xff,0x90, ++0x00,0x46,0x80,0x59,0x90,0x91,0x21,0xe0,0x24,0xf8,0xf0,0xa3,0xe0,0x70,0x1d,0x90, ++0x91,0x21,0xe0,0xff,0x74,0x01,0xa8,0x07,0x08,0x80,0x02,0xc3,0x33,0xd8,0xfc,0xc4, ++0x54,0xf0,0xf4,0xff,0x90,0x00,0x43,0xe0,0x5f,0xf0,0x80,0x1a,0x90,0x91,0x21,0xe0, ++0xff,0x74,0x01,0xa8,0x07,0x08,0x80,0x02,0xc3,0x33,0xd8,0xfc,0xc4,0x54,0xf0,0xff, ++0x90,0x00,0x43,0xe0,0x4f,0xf0,0x51,0xe6,0x90,0x91,0x21,0xe0,0xff,0x74,0x01,0xa8, ++0x07,0x08,0x80,0x02,0xc3,0x33,0xd8,0xfc,0xf4,0xff,0x90,0x00,0x43,0xe0,0x5f,0xf0, ++0x51,0xe6,0xd0,0xd0,0x92,0xaf,0x22,0x90,0x00,0x49,0xe0,0x90,0x91,0x9f,0xf0,0xe0, ++0x54,0x0f,0xf0,0x44,0xf0,0xfd,0x7f,0x49,0x71,0xee,0x90,0x91,0x9f,0xe0,0x44,0xb0, ++0xfd,0x7f,0x49,0x61,0xee,0x12,0x47,0xe6,0xbf,0x01,0x10,0x90,0x02,0x09,0xe0,0xff, ++0x7d,0x01,0x12,0x48,0x22,0x90,0x04,0x1f,0x74,0x20,0xf0,0x22,0x75,0x28,0x33,0xe4, ++0xf5,0x29,0x75,0x2a,0x07,0xf5,0x2b,0x90,0x01,0x30,0xe5,0x28,0xf0,0xa3,0xe5,0x29, ++0xf0,0xa3,0xe5,0x2a,0xf0,0xa3,0xe5,0x2b,0xf0,0x22,0xe4,0x90,0x91,0x0e,0xf0,0xa3, ++0xf0,0x75,0x8e,0x02,0xf1,0x25,0xd1,0xe8,0x90,0x91,0x4f,0xef,0xf0,0xf1,0x0b,0x90, ++0x91,0x51,0xef,0xf0,0xf1,0x60,0x90,0x91,0x3d,0xee,0xf0,0xa3,0xef,0xf0,0xe4,0xf5, ++0x57,0xf1,0x02,0x12,0x61,0xc4,0x12,0x2e,0x01,0x12,0x44,0xff,0x11,0x0c,0xf1,0x36, ++0xd1,0xfb,0xd1,0xd0,0x12,0x44,0xfe,0x31,0x13,0x12,0x44,0xf4,0x12,0x6e,0x09,0x90, ++0x91,0x10,0xe5,0xd9,0xf0,0x12,0x4e,0xb9,0xc2,0xaf,0x90,0x00,0x80,0xe0,0x44,0x40, ++0xf0,0x12,0x4a,0xe6,0x75,0xe8,0x03,0x43,0xa8,0x85,0xd2,0xaf,0x90,0x91,0x0e,0xe0, ++0x64,0x01,0xf0,0x24,0x2a,0x90,0x01,0xc4,0xf0,0x74,0x50,0xa3,0xf0,0xe5,0x57,0x30, ++0xe2,0x10,0x12,0x5f,0xf0,0xbf,0x01,0x0a,0xc2,0xaf,0x53,0x57,0xfb,0xd2,0xaf,0x12, ++0x71,0x97,0xe5,0x57,0x30,0xe4,0x0a,0xc2,0xaf,0x53,0x57,0xef,0xd2,0xaf,0x12,0x60, ++0x2d,0x90,0x90,0xf7,0xe0,0x70,0x03,0x12,0x70,0x74,0x11,0xe7,0x90,0x91,0x3f,0xe0, ++0x90,0x01,0xba,0xf0,0x80,0xb6,0xe4,0x90,0x91,0x55,0xf0,0x90,0x91,0x53,0xe0,0x54, ++0x7f,0xf0,0xa3,0x74,0x0a,0xf0,0x22,0x90,0x06,0x34,0xe0,0x60,0x25,0x14,0x70,0x1b, ++0x7b,0x01,0x7a,0x06,0x79,0x35,0x7f,0xf9,0x7e,0x01,0x12,0x67,0xe4,0xbf,0x01,0x09, ++0x90,0x06,0x35,0xe0,0x54,0x0f,0xf0,0x80,0x04,0x80,0x00,0xe1,0x17,0xe4,0x90,0x06, ++0x34,0xf0,0x22,0x90,0x91,0x56,0xe0,0x54,0xfe,0xf0,0xe0,0x54,0x7f,0xf0,0x90,0x01, ++0x17,0xe0,0xfe,0x90,0x01,0x16,0xe0,0x7c,0x00,0x24,0x00,0xff,0xec,0x3e,0x90,0x91, ++0x5c,0xf0,0xa3,0xef,0xf0,0x90,0x01,0x04,0xe0,0x54,0x0f,0x90,0x91,0x1c,0xf0,0xe0, ++0xff,0x74,0x40,0x7e,0x00,0xa8,0x07,0x08,0x80,0x05,0xc3,0x33,0xce,0x33,0xce,0xd8, ++0xf9,0x90,0x91,0x5b,0xf0,0xee,0x90,0x91,0x5a,0xf0,0x90,0x91,0x5e,0xe0,0x54,0xfe, ++0xf0,0xe0,0x54,0xfd,0xf0,0xe0,0x54,0xfb,0xf0,0xe0,0x54,0xf7,0xf0,0xe0,0x54,0xef, ++0xf0,0xe0,0x54,0xdf,0xf0,0xe0,0x54,0xbf,0xf0,0xe0,0x54,0x7f,0xf0,0xe4,0xa3,0xf0, ++0xa3,0xf0,0xa3,0xe0,0x54,0xfe,0xf0,0xe0,0x54,0xfd,0xf0,0xe0,0x54,0xf7,0xf0,0x22, ++0xd3,0x10,0xaf,0x01,0xc3,0xc0,0xd0,0x12,0x24,0x62,0x54,0x01,0xff,0x90,0x91,0x56, ++0xe0,0x54,0xfe,0x4f,0xf0,0x90,0x00,0x01,0x12,0x42,0x20,0x90,0x91,0x57,0xf0,0x90, ++0x00,0x02,0x12,0x42,0x20,0x90,0x91,0x58,0xf0,0x90,0x91,0x56,0xe0,0x30,0xe0,0x1a, ++0x90,0x06,0x09,0xe0,0x54,0xfe,0xf0,0x90,0x02,0x86,0xe0,0x44,0x04,0xf0,0x43,0x57, ++0x04,0x7d,0x08,0xe4,0xff,0x12,0x31,0x9d,0x80,0x12,0x7d,0x08,0xe4,0xff,0x12,0x31, ++0x2c,0x90,0x02,0x86,0xe0,0x54,0xfb,0xf0,0x31,0xf1,0x31,0x13,0xd0,0xd0,0x92,0xaf, ++0x22,0x90,0x06,0x90,0xe4,0xf0,0x21,0x5a,0x90,0x91,0x19,0x12,0x43,0x41,0xef,0x12, ++0x43,0x4a,0x52,0x30,0x01,0x52,0x39,0x02,0x52,0x5b,0x03,0x52,0x64,0x09,0x52,0x6c, ++0x0c,0x52,0x75,0x0d,0x52,0x7d,0x0e,0x52,0x8e,0x1a,0x52,0x96,0x2c,0x52,0x41,0x2d, ++0x52,0x4a,0x2e,0x52,0x9e,0x30,0x52,0x53,0x3b,0x52,0x86,0x3c,0x00,0x00,0x52,0xa6, ++0x90,0x91,0x19,0x12,0x43,0x21,0x02,0x64,0x72,0x90,0x91,0x19,0x12,0x43,0x21,0xc1, ++0xf5,0x90,0x91,0x19,0x12,0x43,0x21,0x02,0x65,0x8d,0x90,0x91,0x19,0x12,0x43,0x21, ++0x02,0x65,0xd5,0x90,0x91,0x19,0x12,0x43,0x21,0xe1,0x4b,0x90,0x91,0x19,0x12,0x43, ++0x21,0x02,0x66,0x0e,0x90,0x91,0x19,0x12,0x43,0x21,0x80,0x42,0x90,0x91,0x19,0x12, ++0x43,0x21,0x02,0x4c,0xab,0x90,0x91,0x19,0x12,0x43,0x21,0xe1,0x98,0x90,0x91,0x19, ++0x12,0x43,0x21,0x02,0x4d,0xe6,0x90,0x91,0x19,0x12,0x43,0x21,0x21,0x90,0x90,0x91, ++0x19,0x12,0x43,0x21,0xa1,0x9b,0x90,0x91,0x19,0x12,0x43,0x21,0x81,0x7a,0x90,0x91, ++0x19,0x12,0x43,0x21,0xe1,0x78,0x90,0x01,0xc6,0xe0,0x44,0x01,0xf0,0x22,0xd3,0x10, ++0xaf,0x01,0xc3,0xc0,0xd0,0x90,0x91,0x1c,0x12,0x43,0x41,0x90,0x91,0x1c,0x12,0x43, ++0x21,0x90,0x00,0x01,0x12,0x42,0x97,0xfa,0xe5,0xf0,0x24,0x00,0xff,0xe4,0x3a,0xfe, ++0x90,0x91,0x1c,0x12,0x43,0x21,0x90,0x00,0x01,0xee,0x8f,0xf0,0x12,0x42,0xcf,0x12, ++0x24,0x62,0xff,0x60,0x2c,0xb5,0x72,0x16,0x90,0x91,0x1c,0x12,0x43,0x21,0x90,0x00, ++0x01,0x12,0x42,0x97,0x65,0x74,0x70,0x04,0xe5,0x73,0x65,0xf0,0x60,0x23,0x90,0x91, ++0x1c,0x12,0x43,0x21,0x90,0x00,0x01,0x12,0x42,0x97,0xff,0xae,0xf0,0x71,0x26,0x80, ++0x10,0x90,0x91,0x1c,0x12,0x43,0x21,0x12,0x24,0x62,0x65,0x72,0x60,0x03,0x12,0x44, ++0xe8,0xd0,0xd0,0x92,0xaf,0x22,0x90,0x91,0x1f,0xee,0xf0,0xa3,0xef,0xf0,0x75,0x72, ++0x01,0x8e,0x73,0xf5,0x74,0xe4,0xfd,0x7f,0x0b,0x12,0x4f,0x10,0xe4,0xfd,0x7f,0x02, ++0x12,0x4f,0x10,0x71,0x6a,0xe4,0xff,0x71,0xcc,0xe4,0xf5,0x76,0x90,0x01,0xc9,0xe5, ++0x76,0xf0,0x90,0x91,0x1f,0xe0,0xfc,0xa3,0xe0,0xfd,0xec,0xfb,0x8d,0x44,0xe4,0xf5, ++0x45,0x7d,0x01,0x7f,0x60,0x7e,0x01,0x02,0x30,0x62,0x7f,0x0b,0x71,0xd9,0xef,0x65, ++0x75,0x60,0x10,0xe5,0x75,0xb4,0x01,0x05,0xe4,0xf5,0x75,0x80,0x03,0x75,0x75,0x01, ++0x7f,0x01,0x22,0x7f,0x00,0x22,0xe5,0x72,0x64,0x01,0x70,0x3f,0x71,0x6a,0xbf,0x01, ++0x04,0x7f,0x01,0x71,0xcc,0x90,0x00,0x46,0xe0,0x44,0x04,0xfd,0x7f,0x46,0x12,0x4b, ++0xee,0x90,0x00,0x44,0xe0,0x54,0xfb,0xfd,0x7f,0x44,0x12,0x4b,0xee,0x90,0x00,0x46, ++0xe0,0x54,0xfb,0xfd,0x7f,0x46,0x12,0x4b,0xee,0x7f,0x02,0x71,0xd9,0x8f,0x76,0x90, ++0x01,0xc9,0xe5,0x76,0xf0,0xb4,0x01,0x03,0x12,0x4f,0xd7,0x22,0x90,0x01,0xca,0xe5, ++0x75,0xf0,0xef,0x60,0x03,0x12,0x4f,0xd7,0x22,0xd3,0x10,0xaf,0x01,0xc3,0xc0,0xd0, ++0x90,0x91,0xa0,0xef,0xf0,0xd3,0x94,0x07,0x50,0x47,0xe0,0xff,0x74,0x01,0xa8,0x07, ++0x08,0x80,0x02,0xc3,0x33,0xd8,0xfc,0xf4,0xff,0x90,0x00,0x46,0xe0,0x5f,0xf0,0x12, ++0x4a,0xe6,0x90,0x91,0xa0,0xe0,0xfd,0x74,0x01,0x7e,0x00,0xa8,0x05,0x08,0x80,0x05, ++0xc3,0x33,0xce,0x33,0xce,0xd8,0xf9,0xff,0x90,0x00,0x44,0xe0,0xfb,0xe4,0xfe,0xef, ++0x5b,0xa8,0x05,0x08,0x80,0x06,0xce,0xa2,0xe7,0x13,0xce,0x13,0xd8,0xf8,0xff,0x80, ++0x44,0x90,0x91,0xa0,0xe0,0x24,0xf8,0xf0,0xe0,0xff,0x74,0x01,0xa8,0x07,0x08,0x80, ++0x02,0xc3,0x33,0xd8,0xfc,0x12,0x4a,0xde,0x90,0x91,0xa0,0xe0,0xfd,0x74,0x01,0x7e, ++0x00,0xa8,0x05,0x08,0x80,0x05,0xc3,0x33,0xce,0x33,0xce,0xd8,0xf9,0xff,0x90,0x00, ++0x42,0xe0,0xfb,0xe4,0xfe,0xef,0x5b,0xa8,0x05,0x08,0x80,0x06,0xce,0xa2,0xe7,0x13, ++0xce,0x13,0xd8,0xf8,0xff,0xd0,0xd0,0x92,0xaf,0x22,0xd3,0x10,0xaf,0x01,0xc3,0xc0, ++0xd0,0xe4,0xf5,0x10,0x75,0x11,0x04,0xf5,0x12,0xf5,0x14,0xf5,0x15,0x90,0x02,0x09, ++0xe0,0xff,0x12,0x24,0x62,0xfe,0xef,0x2e,0xf5,0x13,0x30,0xe0,0x08,0x75,0x0e,0x00, ++0x75,0x0f,0x80,0x80,0x05,0xe4,0xf5,0x0e,0xf5,0x0f,0xe5,0x13,0xc3,0x13,0x90,0xfd, ++0x10,0xf0,0x74,0x20,0x25,0x10,0xf5,0x10,0xad,0x0f,0xe5,0x10,0x2d,0xff,0x24,0x01, ++0xf5,0x82,0xe4,0x34,0xfc,0xf5,0x83,0xe0,0x90,0x91,0x47,0xf0,0x74,0x02,0x2f,0xf5, ++0x82,0xe4,0x34,0xfc,0xf5,0x83,0xe0,0xfe,0xe5,0x10,0x2d,0x24,0x03,0xf5,0x82,0xe4, ++0x34,0xfc,0xf5,0x83,0xe0,0x24,0x00,0xff,0xe4,0x3e,0x90,0x91,0x48,0xf0,0xa3,0xef, ++0xf0,0x7f,0x04,0xe5,0x10,0x25,0x0f,0x2f,0x24,0x00,0xf5,0x82,0xe4,0x34,0xfc,0xf5, ++0x83,0xe0,0xfe,0x74,0x46,0x2f,0xf5,0x82,0xe4,0x34,0x91,0xf5,0x83,0xee,0xf0,0x0f, ++0xbf,0x08,0xe0,0x12,0x66,0x56,0xef,0x70,0x3f,0x90,0x01,0xc3,0xe0,0x60,0x25,0xc3, ++0xe5,0x15,0x94,0xe8,0xe5,0x14,0x94,0x03,0x40,0x09,0x90,0x01,0xc6,0xe0,0x44,0x10, ++0xf0,0x80,0x63,0x05,0x15,0xe5,0x15,0x70,0x02,0x05,0x14,0x7f,0x0a,0x7e,0x00,0x12, ++0x32,0x15,0x80,0xd5,0x90,0x01,0xc6,0xe0,0x90,0x01,0xc3,0x30,0xe2,0x05,0x74,0xfe, ++0xf0,0x80,0x43,0x74,0xff,0xf0,0x80,0x3e,0xe5,0x10,0xb4,0x78,0x23,0xe4,0xf5,0x10, ++0x05,0x13,0xe5,0x0f,0x64,0x80,0x45,0x0e,0x70,0x06,0xf5,0x0e,0xf5,0x0f,0x80,0x06, ++0x75,0x0e,0x00,0x75,0x0f,0x80,0xe5,0x13,0xc3,0x13,0x90,0xfd,0x10,0xf0,0x80,0x06, ++0x74,0x08,0x25,0x10,0xf5,0x10,0xe5,0x12,0x15,0x12,0x70,0x02,0x15,0x11,0xe5,0x12, ++0x45,0x11,0x60,0x02,0x81,0xb8,0xd0,0xd0,0x92,0xaf,0x22,0x90,0x91,0x1c,0x12,0x43, ++0x41,0x12,0x24,0x62,0xff,0x54,0x01,0xfe,0x90,0x91,0x5e,0xe0,0x54,0xfe,0x4e,0xf0, ++0xef,0x54,0x04,0xff,0xe0,0x54,0xfb,0x4f,0xf0,0x12,0x24,0x62,0xff,0x54,0x02,0xfe, ++0x90,0x91,0x5e,0xe0,0x54,0xfd,0x4e,0xf0,0xef,0x54,0x08,0xff,0xe0,0x54,0xf7,0x4f, ++0xf0,0x12,0x24,0x62,0xff,0x54,0x10,0xfe,0x90,0x91,0x5e,0xe0,0x54,0xef,0x4e,0xf0, ++0xef,0x54,0x20,0xff,0xe0,0x54,0xdf,0x4f,0xf0,0x12,0x24,0x62,0xff,0x54,0x40,0xfe, ++0x90,0x91,0x5e,0xe0,0x54,0xbf,0x4e,0xf0,0xef,0x54,0x80,0xff,0xe0,0x54,0x7f,0x4f, ++0xf0,0x90,0x00,0x02,0x12,0x42,0x20,0x90,0x91,0x60,0xf0,0x90,0x00,0x01,0x12,0x42, ++0x20,0x90,0x91,0x5f,0xf0,0x90,0x00,0x03,0x12,0x42,0x20,0xff,0x54,0x01,0xfe,0x90, ++0x91,0x61,0xe0,0x54,0xfe,0x4e,0xf0,0xef,0x54,0x02,0xff,0xe0,0x54,0xfd,0x4f,0xf0, ++0x90,0x00,0x03,0x12,0x42,0x20,0x54,0x04,0xff,0x90,0x91,0x61,0xe0,0x54,0xfb,0x4f, ++0xf0,0x90,0x91,0x5e,0xe0,0x54,0x01,0x90,0x01,0xb8,0xf0,0x90,0x91,0x5e,0xe0,0xff, ++0xc4,0x13,0x54,0x01,0x90,0x01,0xb9,0xf0,0x90,0x91,0x61,0xe0,0x54,0x01,0x90,0x01, ++0xba,0xf0,0xa3,0x74,0xff,0xf0,0x12,0x24,0x62,0x20,0xe0,0x02,0x21,0xf1,0xe4,0xfd, ++0x7f,0x81,0x12,0x4b,0xee,0x90,0x91,0x1c,0x12,0x43,0x21,0x12,0x24,0x62,0xff,0xc3, ++0x13,0x30,0xe0,0x07,0x90,0x06,0x90,0xe0,0x44,0x02,0xf0,0xef,0x13,0x13,0x54,0x3f, ++0x30,0xe0,0x07,0x90,0x06,0x90,0xe0,0x44,0x04,0xf0,0x12,0x24,0x62,0x13,0x13,0x13, ++0x54,0x1f,0x30,0xe0,0x07,0x90,0x06,0x90,0xe0,0x44,0x08,0xf0,0x90,0x91,0x61,0xe0, ++0x30,0xe0,0x1c,0x90,0x91,0x5e,0xe0,0xc4,0x13,0x54,0x07,0x30,0xe0,0x07,0xa3,0xe0, ++0xff,0xe4,0xfd,0x80,0x07,0x90,0x91,0x5f,0xe0,0xff,0x7d,0x01,0x12,0x4a,0xf6,0x22, ++0x75,0x30,0x1f,0x75,0x31,0x01,0xe4,0xf5,0x32,0x90,0x01,0x38,0xe5,0x30,0xf0,0xa3, ++0xe5,0x31,0xf0,0xa3,0xe5,0x32,0xf0,0x22,0x90,0x00,0x02,0xe0,0x54,0xe0,0x7f,0x01, ++0x60,0x02,0x7f,0x00,0x22,0x12,0x24,0x62,0xf5,0x6d,0x22,0x90,0x01,0x64,0x74,0xa0, ++0xf0,0x22,0x90,0x91,0x51,0xe0,0x90,0x90,0xe8,0xf0,0x22,0x90,0x00,0xf3,0xe0,0x7f, ++0x00,0x30,0xe3,0x02,0x7f,0x01,0x22,0x90,0x06,0x34,0x74,0xff,0xf0,0xe4,0xa3,0xf0, ++0xa3,0xf0,0xa3,0xf0,0x22,0xe4,0x90,0x91,0x4e,0xf0,0x90,0x00,0x80,0xe0,0x44,0x80, ++0xfd,0x7f,0x80,0x02,0x4b,0xee,0x90,0x00,0xf3,0xe0,0x30,0xe2,0x0d,0x90,0x05,0x41, ++0x74,0x10,0xf0,0x90,0x05,0x5a,0xf0,0xa3,0xe4,0xf0,0x22,0x12,0x24,0x62,0x60,0x02, ++0x80,0x01,0xe4,0x90,0x91,0x31,0xf0,0x90,0x91,0x31,0xe0,0x90,0x01,0xe7,0xf0,0x22, ++0x90,0x91,0x51,0xe0,0xb4,0x01,0x0c,0x90,0x00,0xf2,0xe0,0x30,0xe7,0x05,0x7e,0xfd, ++0x7f,0x33,0x22,0x7e,0xfd,0x7f,0x2f,0x22,0x12,0x24,0x62,0xff,0x54,0x01,0xfe,0x90, ++0x91,0x53,0xe0,0x54,0xfe,0x4e,0xf0,0xef,0xc3,0x13,0x30,0xe0,0x0a,0x90,0x00,0x01, ++0x12,0x42,0x20,0x90,0x91,0x54,0xf0,0x22,0x90,0x00,0x02,0x12,0x42,0x20,0x90,0x90, ++0xf7,0xf0,0xe0,0x60,0x04,0xe0,0xf4,0x70,0x21,0xa2,0xaf,0xe4,0x33,0xf5,0x0e,0xc2, ++0xaf,0x90,0x00,0x47,0xe0,0x54,0xfb,0xfd,0x7f,0x47,0x12,0x4b,0xee,0x7d,0x40,0x7f, ++0x01,0x12,0x31,0x66,0xe5,0x0e,0x24,0xff,0x92,0xaf,0x22,0xc0,0xe0,0xc0,0xf0,0xc0, ++0x83,0xc0,0x82,0xc0,0xd0,0x75,0xd0,0x00,0xc0,0x00,0xc0,0x01,0xc0,0x02,0xc0,0x03, ++0xc0,0x04,0xc0,0x05,0xc0,0x06,0xc0,0x07,0x90,0x01,0xc4,0x74,0xcb,0xf0,0x74,0x57, ++0xa3,0xf0,0x90,0x01,0x34,0xe0,0x55,0x28,0xf5,0x2c,0x90,0x01,0x36,0xe0,0x55,0x2a, ++0xf5,0x2e,0xa3,0xe0,0x55,0x2b,0xf5,0x2f,0xe5,0x2c,0x30,0xe0,0x5a,0x90,0x01,0x34, ++0x74,0x01,0xf0,0x85,0xd9,0x54,0xe5,0x70,0x14,0x24,0xfd,0x50,0x02,0x80,0x48,0x90, ++0x91,0x3b,0xe0,0x60,0x3a,0x90,0x01,0x5b,0xe4,0xf0,0x90,0x01,0x3c,0x74,0x04,0xf0, ++0x51,0x30,0xef,0x64,0x01,0x70,0x30,0x90,0x91,0x66,0xf0,0x90,0x91,0x2d,0xe0,0x90, ++0x91,0x67,0xf0,0xe4,0xfb,0xfd,0x7f,0x58,0x7e,0x01,0x12,0x44,0x59,0x90,0x01,0x5b, ++0x74,0x05,0xf0,0x90,0x06,0x92,0x74,0x01,0xf0,0x90,0x91,0x37,0xf0,0x80,0x08,0x51, ++0x30,0xbf,0x01,0x03,0x12,0x44,0xc2,0xe5,0x2c,0x30,0xe1,0x20,0x90,0x01,0x34,0x74, ++0x02,0xf0,0x85,0xd1,0x58,0x85,0xd2,0x59,0x85,0xd3,0x5a,0x85,0xd4,0x5b,0x85,0xd5, ++0x5c,0x85,0xd6,0x5d,0x85,0xd7,0x5e,0x85,0xd9,0x5f,0x71,0x5c,0xe5,0x2c,0x30,0xe3, ++0x10,0x90,0x01,0x34,0x74,0x08,0xf0,0x90,0x91,0x56,0xe0,0x30,0xe0,0x03,0x43,0x57, ++0x04,0xe5,0x2c,0x30,0xe4,0x09,0x90,0x01,0x34,0x74,0x10,0xf0,0x43,0x57,0x10,0xe5, ++0x2c,0x30,0xe5,0x26,0x90,0x01,0xcf,0xe0,0x30,0xe5,0x1f,0xe0,0x54,0xdf,0xf0,0x90, ++0x01,0x34,0x74,0x20,0xf0,0x75,0xa8,0x00,0x75,0xe8,0x00,0x12,0x4e,0xe4,0x90,0x00, ++0x03,0xe0,0x54,0xfb,0xf0,0x12,0x4a,0xe6,0x80,0xfe,0xe5,0x2c,0x30,0xe6,0x06,0x90, ++0x01,0x34,0x74,0x40,0xf0,0xe5,0x2e,0x30,0xe0,0x13,0x90,0x91,0x50,0x74,0x01,0xf0, ++0x90,0x01,0x36,0xf0,0x91,0x23,0x51,0x87,0x90,0x91,0x50,0xe4,0xf0,0xe5,0x2e,0x30, ++0xe1,0x3c,0x90,0x01,0x36,0x74,0x02,0xf0,0x43,0x57,0x40,0x90,0x01,0x02,0xe0,0x54, ++0x03,0x64,0x01,0x70,0x29,0x90,0x01,0x37,0xe0,0x30,0xe0,0x0a,0x74,0x01,0xf0,0x90, ++0x91,0x40,0xe4,0xf0,0x80,0x18,0x90,0x91,0x40,0xe0,0x04,0xf0,0xe0,0xc3,0x94,0x0a, ++0x40,0x0c,0xe4,0xf0,0x90,0x04,0x19,0xe0,0x30,0xe0,0x03,0x12,0x4f,0xf5,0xe5,0x2e, ++0x30,0xe2,0x19,0x90,0x01,0x36,0x74,0x04,0xf0,0x90,0x91,0x3a,0xe4,0xf0,0x90,0x05, ++0x58,0x74,0x03,0xf0,0x51,0xd8,0x90,0x91,0x3f,0xe0,0x04,0xf0,0xe5,0x2e,0x30,0xe3, ++0x28,0x90,0x01,0x36,0x74,0x08,0xf0,0xe5,0x6d,0x64,0x01,0x70,0x1c,0xe5,0x70,0x60, ++0x18,0x90,0x01,0x57,0xe4,0xf0,0x90,0x01,0x3c,0x74,0x02,0xf0,0x90,0x91,0x66,0xe4, ++0x12,0x44,0x49,0x90,0x01,0x57,0x74,0x05,0xf0,0xe5,0x2e,0x30,0xe4,0x2b,0x90,0x01, ++0x36,0x74,0x10,0xf0,0xe5,0x6d,0xb4,0x01,0x20,0xe5,0x70,0x60,0x1c,0x90,0x01,0x57, ++0xe4,0xf0,0x90,0x01,0x3c,0x74,0x02,0xf0,0x90,0x91,0x3c,0xe4,0xf0,0x53,0x71,0xfd, ++0xe5,0x71,0x54,0x07,0x70,0x03,0x12,0x44,0xc2,0xe5,0x2e,0x30,0xe5,0x1f,0x90,0x01, ++0x36,0x74,0x20,0xf0,0xe5,0x6d,0xb4,0x01,0x14,0xe5,0x70,0x60,0x10,0x90,0x91,0x3b, ++0xe0,0x64,0x02,0x60,0x05,0x12,0x44,0xc8,0x80,0x03,0x12,0x44,0x77,0xe5,0x2e,0x30, ++0xe6,0x1b,0x90,0x01,0x36,0x74,0x40,0xf0,0xe5,0x6d,0xb4,0x01,0x10,0xe5,0x70,0x60, ++0x0c,0x53,0x71,0xfe,0xe5,0x71,0x54,0x07,0x70,0x03,0x12,0x44,0xc2,0xe5,0x2f,0x30, ++0xe1,0x08,0x90,0x01,0x37,0x74,0x02,0xf0,0x71,0x7e,0x74,0xcb,0x04,0x90,0x01,0xc4, ++0xf0,0x74,0x57,0xa3,0xf0,0xd0,0x07,0xd0,0x06,0xd0,0x05,0xd0,0x04,0xd0,0x03,0xd0, ++0x02,0xd0,0x01,0xd0,0x00,0xd0,0xd0,0xd0,0x82,0xd0,0x83,0xd0,0xf0,0xd0,0xe0,0x32, ++0x90,0x04,0x1b,0xe0,0x54,0x7f,0x64,0x7f,0x7f,0x01,0x60,0x02,0x7f,0x00,0x22,0x51, ++0x30,0xef,0x64,0x01,0x60,0x08,0x90,0x01,0xb9,0x74,0x01,0xf0,0x80,0x30,0x90,0x91, ++0x37,0xe0,0x60,0x08,0x90,0x01,0xb9,0x74,0x02,0xf0,0x80,0x22,0x90,0x91,0x36,0xe0, ++0x60,0x08,0x90,0x01,0xb9,0x74,0x04,0xf0,0x80,0x14,0xe5,0x6f,0x54,0x0f,0xd3,0x94, ++0x04,0x40,0x08,0x90,0x01,0xb9,0x74,0x08,0xf0,0x80,0x03,0x7f,0x01,0x22,0x90,0x01, ++0xb8,0x74,0x08,0xf0,0x7f,0x00,0x22,0x90,0x91,0x53,0xe0,0x30,0xe0,0x49,0xe5,0x6d, ++0x64,0x01,0x70,0x43,0x90,0x91,0x52,0xe0,0x04,0xf0,0xe5,0x70,0x64,0x03,0x60,0x05, ++0xe5,0x70,0xb4,0x06,0x0d,0x90,0x91,0x52,0xe0,0xff,0x74,0x01,0xd3,0x9f,0x50,0x14, ++0x80,0x07,0x90,0x91,0x52,0xe0,0xb4,0x0a,0x0b,0x90,0x91,0x55,0xe0,0x04,0xf0,0xe4, ++0x90,0x91,0x52,0xf0,0x90,0x91,0x55,0xe0,0xff,0x90,0x91,0x54,0xe0,0xb5,0x07,0x07, ++0x71,0x4e,0xe4,0x90,0x91,0x55,0xf0,0x22,0xe5,0x6d,0x64,0x01,0x70,0x63,0xe5,0x70, ++0x60,0x5f,0xe5,0x70,0x64,0x02,0x60,0x06,0xe5,0x70,0x64,0x05,0x70,0x27,0x90,0x06, ++0xab,0xe0,0x90,0x91,0x27,0xf0,0x90,0x06,0xaa,0xe0,0x90,0x91,0x39,0xf0,0x90,0x91, ++0x27,0xe0,0x70,0x07,0x90,0x91,0x39,0xe0,0xff,0x80,0x05,0x90,0x91,0x27,0xe0,0xff, ++0x90,0x91,0x27,0xef,0xf0,0x90,0x91,0x29,0xe0,0x60,0x03,0xe0,0x14,0xf0,0xe4,0x90, ++0x91,0x28,0xf0,0x90,0x01,0x57,0xf0,0x90,0x01,0x3c,0x74,0x02,0xf0,0x53,0x71,0xfd, ++0x53,0x71,0xef,0xe5,0x70,0x14,0x24,0xfd,0x50,0x02,0x80,0x03,0x12,0x45,0xc7,0x71, ++0x42,0x22,0xd3,0x10,0xaf,0x01,0xc3,0xc0,0xd0,0xd0,0xd0,0x92,0xaf,0x22,0xe5,0x6e, ++0x30,0xe3,0x04,0xe4,0xff,0x80,0x02,0x7f,0x01,0x02,0x47,0xc9,0x90,0x91,0x08,0xe0, ++0x54,0xf0,0x44,0x03,0xf0,0x54,0x0f,0x44,0x80,0xf0,0x7b,0x00,0x7a,0x00,0x79,0x58, ++0x90,0x91,0x71,0x12,0x43,0x41,0x0b,0x7a,0x91,0x79,0x08,0x02,0x46,0xb7,0x90,0x91, ++0x80,0x12,0x25,0x14,0x00,0x00,0x00,0x00,0xe5,0x70,0x14,0x24,0xfd,0x50,0x02,0x80, ++0x21,0x90,0x91,0x3b,0xe0,0x60,0x06,0x7d,0x01,0x7f,0x0c,0x80,0x0d,0xe5,0x6e,0x54, ++0x0f,0xc3,0x94,0x04,0x50,0x07,0x7d,0x01,0x7f,0x04,0x12,0x47,0x27,0xe4,0xff,0x12, ++0x48,0xb3,0x22,0x51,0x30,0xef,0x64,0x01,0x60,0x08,0x90,0x01,0xb9,0x74,0x01,0xf0, ++0x80,0x58,0xe5,0x71,0x54,0x03,0x60,0x08,0x90,0x01,0xb9,0x74,0x02,0xf0,0x80,0x4a, ++0xe5,0x6f,0x54,0x0f,0xd3,0x94,0x02,0x40,0x08,0x90,0x01,0xb9,0x74,0x04,0xf0,0x80, ++0x39,0xe5,0x71,0x30,0xe2,0x08,0x90,0x01,0xb9,0x74,0x08,0xf0,0x80,0x2c,0xe5,0x71, ++0x30,0xe4,0x08,0x90,0x01,0xb9,0x74,0x10,0xf0,0x80,0x1f,0x90,0x91,0x29,0xe0,0x60, ++0x08,0x90,0x01,0xb9,0x74,0x20,0xf0,0x80,0x11,0x90,0x91,0x31,0xe0,0x60,0x08,0x90, ++0x01,0xb9,0x74,0x80,0xf0,0x80,0x03,0x7f,0x01,0x22,0x90,0x01,0xb8,0x74,0x04,0xf0, ++0x7f,0x00,0x22,0xe4,0xfb,0x90,0x91,0x78,0x12,0x25,0x14,0x00,0x00,0x00,0x00,0xe5, ++0x70,0x70,0x02,0x81,0xb5,0xe5,0x6d,0x64,0x01,0x70,0x7a,0xe5,0x70,0x14,0x60,0x2b, ++0x24,0xfd,0x60,0x27,0x24,0x02,0x24,0xfb,0x50,0x02,0x80,0x21,0x90,0x91,0x27,0xe0, ++0x14,0xf0,0xe0,0x60,0x04,0xa3,0xe0,0x60,0x14,0x90,0x91,0x27,0xe0,0x70,0x08,0x90, ++0x91,0x39,0xe0,0x90,0x91,0x27,0xf0,0x7b,0x01,0x80,0x02,0x7b,0x01,0xeb,0x60,0x45, ++0x43,0x71,0x10,0xe4,0x90,0x91,0x66,0xf0,0x90,0x91,0x3a,0xe0,0x75,0xf0,0x05,0xa4, ++0xff,0x90,0x91,0x34,0xe0,0x2f,0x12,0x44,0x4e,0x90,0x01,0x57,0x74,0x05,0xf0,0xe5, ++0x6e,0x54,0x0f,0xc3,0x94,0x04,0x50,0x07,0x7d,0x01,0x7f,0x04,0x12,0x47,0x27,0x90, ++0x91,0x2e,0xe0,0x60,0x10,0x90,0x91,0x2c,0xe0,0x90,0x07,0x78,0x60,0x04,0x74,0x0d, ++0xf0,0x22,0x74,0x09,0xf0,0x22,0xc0,0xe0,0xc0,0xf0,0xc0,0x83,0xc0,0x82,0xc0,0xd0, ++0x75,0xd0,0x00,0xc0,0x00,0xc0,0x01,0xc0,0x02,0xc0,0x03,0xc0,0x04,0xc0,0x05,0xc0, ++0x06,0xc0,0x07,0x90,0x01,0xc4,0x74,0xb6,0xf0,0x74,0x5c,0xa3,0xf0,0x53,0x91,0xef, ++0x90,0x00,0x51,0xe0,0xff,0x90,0x00,0x55,0xe0,0x5f,0xf5,0x3d,0x90,0x00,0x52,0xe0, ++0xff,0x90,0x00,0x56,0xe0,0x5f,0xf5,0x3e,0xe5,0x3d,0x30,0xe4,0x06,0x90,0x00,0x55, ++0x74,0x10,0xf0,0xe5,0x3d,0x30,0xe5,0x06,0x90,0x00,0x55,0x74,0x20,0xf0,0xe5,0x3d, ++0x30,0xe6,0x1b,0x90,0x00,0x55,0x74,0x40,0xf0,0x90,0x90,0xf6,0xe0,0x54,0x03,0xff, ++0xbf,0x03,0x0b,0x90,0x90,0xf3,0xe0,0x60,0x05,0x7f,0x01,0x12,0x4c,0x03,0xe5,0x3d, ++0x30,0xe7,0x15,0x90,0x00,0x55,0x74,0x80,0xf0,0x90,0x90,0xf6,0xe0,0x54,0x03,0xff, ++0xbf,0x03,0x05,0x7f,0x02,0x12,0x4c,0x03,0xe5,0x3e,0x30,0xe0,0x06,0x90,0x00,0x56, ++0x74,0x01,0xf0,0xe5,0x3e,0x30,0xe1,0x06,0x90,0x00,0x56,0x74,0x02,0xf0,0xe5,0x3e, ++0x30,0xe2,0x06,0x90,0x00,0x56,0x74,0x04,0xf0,0xe5,0x3e,0x30,0xe3,0x06,0x90,0x00, ++0x56,0x74,0x08,0xf0,0x90,0x01,0xc4,0x74,0xb6,0xf0,0x74,0x5c,0xa3,0xf0,0xd0,0x07, ++0xd0,0x06,0xd0,0x05,0xd0,0x04,0xd0,0x03,0xd0,0x02,0xd0,0x01,0xd0,0x00,0xd0,0xd0, ++0xd0,0x82,0xd0,0x83,0xd0,0xf0,0xd0,0xe0,0x32,0xc0,0xe0,0xc0,0xf0,0xc0,0x83,0xc0, ++0x82,0xc0,0xd0,0x75,0xd0,0x00,0xc0,0x00,0xc0,0x01,0xc0,0x02,0xc0,0x03,0xc0,0x04, ++0xc0,0x05,0xc0,0x06,0xc0,0x07,0x75,0x0d,0x00,0x90,0x01,0xc4,0x74,0x99,0xf0,0x74, ++0x5d,0xa3,0xf0,0x53,0x91,0xdf,0x90,0x01,0x3c,0xe0,0x55,0x30,0xf5,0x34,0xa3,0xe0, ++0x55,0x31,0xf5,0x35,0xa3,0xe0,0x55,0x32,0xf5,0x36,0xa3,0xe0,0x55,0x33,0xf5,0x37, ++0xe5,0x34,0x30,0xe0,0x06,0x90,0x01,0x3c,0x74,0x01,0xf0,0xe5,0x34,0x30,0xe1,0x08, ++0x90,0x01,0x3c,0x74,0x02,0xf0,0xf1,0x57,0xe5,0x34,0x30,0xe2,0x3a,0x90,0x01,0x3c, ++0x74,0x04,0xf0,0x90,0x06,0x92,0xe0,0x30,0xe0,0x25,0x90,0x91,0x66,0xe4,0xf0,0x90, ++0x91,0x2d,0xe0,0x90,0x91,0x67,0xf0,0xe4,0xfb,0xfd,0x7f,0x58,0x7e,0x01,0x12,0x44, ++0x59,0x90,0x01,0x5b,0x74,0x05,0xf0,0x90,0x06,0x92,0x74,0x01,0xf0,0x80,0x08,0x90, ++0x91,0x37,0xe4,0xf0,0x12,0x44,0xc2,0xe5,0x34,0x30,0xe3,0x3a,0x90,0x01,0x3c,0x74, ++0x08,0xf0,0x90,0x06,0x92,0xe0,0x30,0xe1,0x25,0x90,0x91,0x66,0xe4,0xf0,0x90,0x91, ++0x2d,0xe0,0x90,0x91,0x67,0xf0,0xe4,0xfb,0xfd,0x7f,0x5c,0x7e,0x01,0x12,0x44,0x59, ++0x90,0x01,0x5f,0x74,0x05,0xf0,0x90,0x06,0x92,0x74,0x02,0xf0,0x80,0x08,0x90,0x91, ++0x36,0xe4,0xf0,0x12,0x44,0xc2,0xe5,0x34,0x30,0xe4,0x09,0x90,0x01,0x3c,0x74,0x10, ++0xf0,0x12,0x53,0x86,0xe5,0x34,0x30,0xe5,0x09,0x90,0x01,0x3c,0x74,0x20,0xf0,0x12, ++0x6e,0xb9,0xe5,0x35,0x30,0xe0,0x5a,0x90,0x01,0x3d,0x74,0x01,0xf0,0x90,0x01,0x2f, ++0xe0,0x44,0x7f,0xf0,0x90,0x00,0x83,0xe0,0x54,0x0f,0xf5,0x0d,0xb4,0x01,0x02,0x80, ++0x1c,0xe5,0x0d,0xb4,0x02,0x05,0x90,0x00,0x83,0x80,0x12,0xe5,0x0d,0xb4,0x04,0x05, ++0x90,0x00,0x83,0x80,0x08,0xe5,0x0d,0xb4,0x0c,0x08,0x90,0x00,0x83,0xe0,0xf5,0x6f, ++0x80,0x06,0x90,0x01,0xbe,0xe0,0x04,0xf0,0x90,0x01,0xbb,0xe5,0x6f,0xf0,0xe5,0x6f, ++0x30,0xe0,0x03,0xa3,0x80,0x03,0x90,0x01,0xbd,0xe0,0x04,0xf0,0xf1,0x38,0x12,0x44, ++0xc2,0xe5,0x35,0x30,0xe2,0x06,0x90,0x01,0x3d,0x74,0x04,0xf0,0xe5,0x36,0x30,0xe0, ++0x06,0x90,0x01,0x3e,0x74,0x01,0xf0,0xe5,0x36,0x30,0xe1,0x06,0x90,0x01,0x3e,0x74, ++0x02,0xf0,0x74,0x99,0x04,0x90,0x01,0xc4,0xf0,0x74,0x5d,0xa3,0xf0,0xd0,0x07,0xd0, ++0x06,0xd0,0x05,0xd0,0x04,0xd0,0x03,0xd0,0x02,0xd0,0x01,0xd0,0x00,0xd0,0xd0,0xd0, ++0x82,0xd0,0x83,0xd0,0xf0,0xd0,0xe0,0x32,0xe5,0x6f,0x30,0xe6,0x19,0xe5,0x6f,0x54, ++0x0f,0xff,0x90,0x91,0x24,0xe0,0xfe,0x4f,0x90,0x01,0x2f,0xf0,0xee,0x64,0x80,0x90, ++0x91,0x24,0xf0,0x53,0x6f,0xbf,0x22,0xe4,0x90,0x91,0x0d,0xf0,0xe5,0x70,0x70,0x02, ++0xe1,0xe1,0x90,0x91,0x3c,0xe0,0x60,0x0d,0xe4,0xf0,0x53,0x71,0xfd,0xe5,0x71,0x54, ++0x07,0x70,0x6e,0x80,0x69,0x90,0x91,0x28,0xe0,0x04,0xf0,0x53,0x71,0xef,0x90,0x91, ++0x3a,0xe0,0x04,0xf0,0x90,0x91,0x0d,0xe0,0xf9,0xff,0x7e,0x00,0x24,0x01,0xfd,0xee, ++0x33,0xfc,0x90,0x91,0x3a,0xe0,0xb5,0x05,0x06,0xe4,0xb5,0x04,0x02,0x80,0x12,0xef, ++0x24,0x02,0xff,0xe4,0x3e,0xfe,0x90,0x91,0x3a,0xe0,0xb5,0x07,0x0a,0xe4,0xb5,0x06, ++0x06,0x90,0x05,0x58,0xe0,0x04,0xf0,0xe9,0xff,0x90,0x91,0x2f,0xe0,0x2f,0xff,0xe4, ++0x33,0xfe,0x90,0x91,0x28,0xe0,0xd3,0x9f,0xee,0x64,0x80,0xf8,0x74,0x80,0x98,0x40, ++0x0d,0xe5,0x6d,0xb4,0x01,0x0b,0xa3,0xe0,0x70,0x07,0xe0,0x04,0xf0,0x22,0x12,0x44, ++0xc2,0x22,0x8f,0x20,0x8c,0x21,0x8d,0x22,0x22,0x8f,0x23,0x8c,0x24,0x8d,0x25,0x22, ++0xe4,0x90,0x91,0x11,0xf0,0xa3,0xf0,0x90,0x02,0x86,0xe0,0x20,0xe1,0x2c,0xc3,0x90, ++0x91,0x12,0xe0,0x94,0x20,0x90,0x91,0x11,0xe0,0x94,0x03,0x40,0x0a,0x90,0x01,0xc6, ++0xe0,0x44,0x20,0xf0,0x7f,0x00,0x22,0x90,0x91,0x11,0xe4,0x75,0xf0,0x01,0x12,0x42, ++0x81,0x7f,0x01,0x7e,0x00,0x12,0x32,0x15,0x80,0xcd,0x7f,0x01,0x22,0x90,0x01,0xcc, ++0xe0,0x54,0x0f,0x90,0x91,0x11,0xf0,0x90,0x91,0x11,0xe0,0xfd,0x70,0x02,0x21,0x6f, ++0x90,0x91,0x9c,0xe0,0xff,0x74,0x01,0x7e,0x00,0xa8,0x07,0x08,0x80,0x05,0xc3,0x33, ++0xce,0x33,0xce,0xd8,0xf9,0xff,0xef,0x5d,0x70,0x02,0x21,0x68,0x90,0x91,0x9c,0xe0, ++0x75,0xf0,0x04,0x90,0x01,0xd0,0x12,0x43,0x15,0xe0,0x90,0x91,0x12,0xf0,0x75,0x63, ++0x01,0x75,0x64,0x91,0x75,0x65,0x12,0x75,0x66,0x01,0x7b,0x01,0x7a,0x91,0x79,0x13, ++0x12,0x46,0x6d,0x90,0x91,0x13,0xe0,0xff,0xc4,0x13,0x13,0x13,0x54,0x01,0x90,0x91, ++0x9c,0x30,0xe0,0x59,0xe0,0x75,0xf0,0x02,0x90,0x00,0x88,0x12,0x43,0x15,0xe0,0x90, ++0x91,0x14,0xf0,0x90,0x91,0x9c,0xe0,0x75,0xf0,0x02,0x90,0x00,0x89,0x12,0x43,0x15, ++0xe0,0x90,0x91,0x15,0xf0,0x90,0x91,0x9c,0xe0,0x75,0xf0,0x04,0x90,0x01,0xd1,0x12, ++0x43,0x15,0xe0,0x90,0x91,0x16,0xf0,0x90,0x91,0x9c,0xe0,0x75,0xf0,0x04,0x90,0x01, ++0xd2,0x12,0x43,0x15,0xe0,0x90,0x91,0x17,0xf0,0x90,0x91,0x9c,0xe0,0x75,0xf0,0x04, ++0x90,0x01,0xd3,0x12,0x43,0x15,0xe0,0x90,0x91,0x18,0xf0,0x80,0x33,0xe0,0x75,0xf0, ++0x04,0x90,0x01,0xd1,0x12,0x43,0x15,0xe0,0x90,0x91,0x14,0xf0,0x90,0x91,0x9c,0xe0, ++0x75,0xf0,0x04,0x90,0x01,0xd2,0x12,0x43,0x15,0xe0,0x90,0x91,0x15,0xf0,0x90,0x91, ++0x9c,0xe0,0x75,0xf0,0x04,0x90,0x01,0xd3,0x12,0x43,0x15,0xe0,0x90,0x91,0x16,0xf0, ++0xef,0x54,0x7f,0xff,0x7b,0x01,0x7a,0x91,0x79,0x14,0x12,0x51,0xf8,0x90,0x91,0x11, ++0xe0,0xff,0x90,0x91,0x9c,0xe0,0xfe,0x74,0x01,0xa8,0x06,0x08,0x80,0x02,0xc3,0x33, ++0xd8,0xfc,0xf4,0x5f,0x90,0x91,0x11,0xf0,0x90,0x91,0x9c,0xe0,0xff,0x74,0x01,0xa8, ++0x07,0x08,0x80,0x02,0xc3,0x33,0xd8,0xfc,0x90,0x01,0xcc,0xf0,0x90,0x91,0x9c,0xe0, ++0x04,0xf0,0xe0,0x54,0x03,0xf0,0x01,0x37,0x90,0x01,0xc6,0xe0,0x44,0x02,0xf0,0x22, ++0xad,0x07,0x74,0x11,0x2d,0xf5,0x82,0xe4,0x34,0xfc,0xf5,0x83,0xe0,0x44,0x01,0xf0, ++0x90,0x04,0x80,0xe0,0x54,0x0f,0xfc,0x74,0x14,0x2d,0xf5,0x82,0xe4,0x34,0xfc,0xf5, ++0x83,0xe0,0x54,0xc0,0x4c,0xfd,0x74,0x14,0x2f,0xf5,0x82,0xe4,0x34,0xfc,0xf5,0x83, ++0xed,0xf0,0x22,0xef,0x60,0x0f,0x74,0x21,0x2d,0xf5,0x82,0xe4,0x34,0xfc,0xf5,0x83, ++0xe0,0x44,0x10,0xf0,0x22,0x74,0x21,0x2d,0xf5,0x82,0xe4,0x34,0xfc,0xf5,0x83,0xe0, ++0x54,0xef,0xf0,0x22,0xe4,0xf5,0x6d,0xf5,0x71,0xf5,0x70,0x75,0x6f,0x0c,0x75,0x6e, ++0x0c,0x90,0x91,0x3b,0xf0,0x90,0x91,0x37,0xf0,0x90,0x91,0x36,0xf0,0x90,0x91,0x39, ++0x04,0xf0,0x90,0x91,0x27,0xf0,0xe4,0x90,0x91,0x3c,0xf0,0x90,0x91,0x29,0xf0,0x90, ++0x91,0x34,0x74,0x07,0xf0,0xe4,0x90,0x91,0x28,0xf0,0x90,0x91,0x32,0xf0,0xa3,0x74, ++0x03,0xf0,0x90,0x91,0x2f,0x74,0x0a,0xf0,0xa3,0x74,0x05,0xf0,0x90,0x91,0x2d,0x74, ++0x14,0xf0,0x90,0x91,0x35,0x74,0x05,0xf0,0xe4,0x90,0x91,0x2b,0xf0,0x90,0x91,0x25, ++0xf0,0x90,0x91,0x50,0xf0,0x90,0x91,0x31,0xf0,0x90,0x91,0x3a,0xf0,0x90,0x91,0x26, ++0xf0,0x90,0x91,0x38,0xf0,0x90,0x91,0x2e,0xf0,0x90,0x91,0x2c,0xf0,0x22,0xe4,0x90, ++0x91,0x3c,0xf0,0x90,0x91,0x28,0xf0,0xf5,0x71,0x22,0x90,0x06,0x04,0xe0,0x54,0xbf, ++0xf0,0xef,0x60,0x0a,0xe5,0x6d,0xb4,0x01,0x05,0xe4,0xff,0x12,0x47,0xc9,0x53,0x6e, ++0xf0,0x43,0x6e,0x0c,0x22,0x90,0x91,0x9d,0xef,0xf0,0x51,0x7e,0x90,0x91,0x9d,0xe0, ++0x60,0x05,0x90,0x05,0x22,0xe4,0xf0,0x53,0x6e,0xf0,0x43,0x6e,0x04,0x22,0x90,0x00, ++0x11,0xe0,0x44,0x09,0xf0,0x12,0x4a,0xe6,0x90,0x90,0xd8,0x12,0x43,0x09,0x90,0x80, ++0x96,0x12,0x25,0x08,0x7f,0x78,0x7e,0x08,0x12,0x2b,0x08,0x90,0x90,0xdc,0x12,0x43, ++0x09,0x90,0x80,0x96,0x12,0x25,0x08,0x7f,0x04,0x7e,0x0c,0x12,0x2b,0x08,0x90,0x90, ++0xe0,0x12,0x43,0x09,0x90,0x80,0x96,0x12,0x25,0x08,0x7f,0x00,0x7e,0x08,0x12,0x2b, ++0x08,0x90,0x90,0xe4,0x12,0x43,0x09,0x90,0x80,0x96,0x12,0x25,0x08,0x7f,0x70,0x7e, ++0x0e,0x12,0x2b,0x08,0x90,0x80,0x68,0x12,0x25,0x14,0x00,0x03,0x2d,0x95,0xe4,0xfd, ++0xff,0x12,0x30,0x2c,0x90,0x91,0x51,0xe0,0xb4,0x01,0x11,0x90,0x80,0x68,0x12,0x25, ++0x14,0x00,0x03,0x2d,0x95,0xe4,0xfd,0x7f,0x01,0x12,0x30,0x2c,0x22,0x8f,0x77,0xe4, ++0x90,0x91,0x96,0xf0,0xa3,0xf0,0x90,0x01,0x09,0xe0,0x7f,0x00,0x30,0xe7,0x02,0x7f, ++0x01,0xef,0x65,0x77,0x60,0x3e,0xc3,0x90,0x91,0x97,0xe0,0x94,0x88,0x90,0x91,0x96, ++0xe0,0x94,0x13,0x40,0x08,0x90,0x01,0xc6,0xe0,0x44,0x80,0xf0,0x22,0x90,0x91,0x96, ++0xe4,0x75,0xf0,0x01,0x12,0x42,0x81,0x7f,0x14,0x7e,0x00,0x12,0x32,0x15,0xd3,0x90, ++0x91,0x97,0xe0,0x94,0x32,0x90,0x91,0x96,0xe0,0x94,0x00,0x40,0xb9,0x90,0x01,0xc7, ++0xe0,0x30,0xe0,0xb2,0x22,0x22,0x53,0x6e,0xf0,0x43,0x6e,0x01,0x71,0x55,0x71,0x67, ++0x53,0x6e,0xf0,0x43,0x6e,0x02,0x22,0x22,0x8f,0x78,0x12,0x47,0xe6,0xef,0x64,0x01, ++0x70,0x2e,0x90,0x91,0x44,0x12,0x48,0x1e,0xe5,0x78,0x60,0x10,0x74,0x21,0x2f,0xf5, ++0x82,0xe4,0x34,0xfc,0xf5,0x83,0xe0,0x44,0x10,0xf0,0x80,0x0e,0x74,0x21,0x2f,0xf5, ++0x82,0xe4,0x34,0xfc,0xf5,0x83,0xe0,0x54,0xef,0xf0,0x90,0x04,0x1f,0x74,0x20,0xf0, ++0x22,0xe4,0xfb,0x90,0x91,0x7c,0x12,0x25,0x14,0x00,0x00,0x00,0x00,0xe5,0x70,0x60, ++0x5f,0xe5,0x6d,0x64,0x01,0x70,0x59,0x0b,0x90,0x91,0x27,0xf0,0x04,0x60,0x51,0x43, ++0x71,0x10,0xe4,0x90,0x91,0x66,0xf0,0x90,0x91,0x3a,0xe0,0x75,0xf0,0x05,0xa4,0xff, ++0x90,0x91,0x34,0xe0,0x2f,0x90,0x91,0x67,0xf0,0xe4,0x1b,0x12,0x44,0x54,0x90,0x01, ++0x57,0x74,0x05,0xf0,0xe5,0x6e,0x54,0x0f,0xc3,0x94,0x04,0x50,0x07,0x7d,0x01,0x7f, ++0x04,0x12,0x47,0x27,0x90,0x91,0x2e,0xe0,0x60,0x11,0x90,0x91,0x2c,0xe0,0x90,0x07, ++0x78,0x60,0x05,0x74,0x0d,0xf0,0x80,0x03,0x74,0x09,0xf0,0x90,0x05,0x22,0xe4,0xf0, ++0x22,0x90,0x91,0x32,0xe0,0xa3,0xe0,0x90,0x05,0x58,0xf0,0x22,0xd3,0x10,0xaf,0x01, ++0xc3,0xc0,0xd0,0x90,0x91,0x84,0xee,0xf0,0xa3,0xef,0xf0,0xe4,0xa3,0xf0,0xa3,0xf0, ++0x90,0x91,0x84,0xe0,0xfe,0xa3,0xe0,0xf5,0x82,0x8e,0x83,0xe0,0x60,0x2d,0xc3,0x90, ++0x91,0x87,0xe0,0x94,0xe8,0x90,0x91,0x86,0xe0,0x94,0x03,0x40,0x0b,0x90,0x01,0xc6, ++0xe0,0x44,0x10,0xf0,0x7f,0x00,0x80,0x15,0x90,0x91,0x86,0xe4,0x75,0xf0,0x01,0x12, ++0x42,0x81,0x7f,0x0a,0x7e,0x00,0x12,0x32,0x15,0x80,0xc5,0x7f,0x01,0xd0,0xd0,0x92, ++0xaf,0x22,0xd3,0x10,0xaf,0x01,0xc3,0xc0,0xd0,0x90,0x91,0x1c,0x12,0x43,0x41,0x90, ++0x91,0x1f,0x12,0x25,0x14,0x00,0x00,0x00,0x00,0x90,0x91,0x1c,0x12,0x43,0x21,0x90, ++0x00,0x01,0x12,0x42,0x20,0x90,0x91,0x3b,0xf0,0x90,0x00,0x03,0x12,0x42,0x20,0x90, ++0x91,0x25,0xf0,0x90,0x00,0x04,0x12,0x42,0x20,0xff,0x54,0x01,0x90,0x91,0x26,0xf0, ++0xef,0xc3,0x13,0x54,0x01,0x90,0x91,0x2e,0xf0,0x90,0x00,0x04,0x12,0x42,0x20,0xff, ++0x13,0x13,0x54,0x01,0x90,0x91,0x2c,0xf0,0x90,0x91,0x2e,0xe0,0x90,0x91,0x1f,0x70, ++0x26,0x12,0x25,0x14,0x00,0x00,0x02,0x10,0x90,0x91,0x1f,0x12,0x43,0x09,0x90,0x80, ++0x96,0x12,0x25,0x08,0x7f,0x60,0x7e,0x08,0x12,0x2b,0x08,0x90,0x91,0x1f,0x12,0x25, ++0x14,0x00,0x00,0x03,0x10,0x80,0x24,0x12,0x25,0x14,0x00,0x00,0x01,0x10,0x90,0x91, ++0x1f,0x12,0x43,0x09,0x90,0x80,0x96,0x12,0x25,0x08,0x7f,0x60,0x7e,0x08,0x12,0x2b, ++0x08,0x90,0x91,0x1f,0x12,0x25,0x14,0x00,0x00,0x03,0x00,0x90,0x91,0x1f,0x12,0x43, ++0x09,0x90,0x80,0x96,0x12,0x25,0x08,0x7f,0x70,0x7e,0x08,0x12,0x2b,0x08,0x90,0x91, ++0x26,0xe0,0x70,0x3d,0x90,0x91,0x38,0x74,0x01,0xf0,0x7f,0x00,0x7e,0x08,0x12,0x22, ++0x65,0x90,0x91,0x1f,0x12,0x25,0x08,0x90,0x91,0x1f,0x12,0x43,0x09,0xec,0x44,0x02, ++0xfc,0x90,0x91,0x1f,0x12,0x25,0x08,0x90,0x91,0x1f,0x12,0x43,0x09,0x90,0x80,0x96, ++0x12,0x25,0x08,0x7f,0x00,0x7e,0x08,0x12,0x2b,0x08,0x90,0x02,0x86,0xe0,0x54,0xfb, ++0xf0,0x90,0x91,0x1c,0x12,0x43,0x21,0x12,0x49,0x7f,0x90,0x01,0xe5,0xe5,0x70,0xf0, ++0x90,0x91,0x3b,0xe0,0x90,0x01,0xe6,0xf0,0xd0,0xd0,0x92,0xaf,0x22,0x90,0x00,0x02, ++0x12,0x42,0x20,0xff,0x30,0xe0,0x25,0x12,0x24,0x62,0x90,0x91,0x2f,0xf0,0x90,0x00, ++0x01,0x12,0x42,0x20,0x90,0x91,0x30,0xf0,0xef,0xc3,0x13,0x54,0x7f,0x90,0x91,0x2d, ++0xf0,0x90,0x00,0x03,0x12,0x42,0x20,0x90,0x91,0x35,0xf0,0x22,0x90,0x91,0x2f,0x74, ++0x0a,0xf0,0x90,0x91,0x30,0x74,0x05,0xf0,0x90,0x91,0x2d,0x74,0x14,0xf0,0x90,0x91, ++0x35,0x74,0x05,0xf0,0x22,0x12,0x24,0x62,0x30,0xe0,0x19,0xc3,0x13,0x54,0x7f,0x90, ++0x91,0x34,0xf0,0x90,0x00,0x01,0x12,0x42,0x20,0xff,0x90,0x91,0x32,0xe4,0xf0,0xa3, ++0xef,0xf0,0x80,0x0f,0x90,0x91,0x34,0x74,0x07,0xf0,0x90,0x91,0x32,0xe4,0xf0,0xa3, ++0x74,0x03,0xf0,0x90,0x91,0x32,0xe0,0xa3,0xe0,0x90,0x05,0x58,0xf0,0x22,0x90,0x02, ++0x09,0xe0,0xfd,0x12,0x24,0x62,0xfe,0xaf,0x05,0xed,0x2e,0x90,0x91,0x41,0xf0,0x90, ++0x00,0x01,0x12,0x42,0x20,0xff,0xed,0x2f,0x90,0x91,0x42,0xf0,0x90,0x00,0x02,0x12, ++0x42,0x20,0xff,0xed,0x2f,0x90,0x91,0x43,0xf0,0x90,0x00,0x03,0x12,0x42,0x20,0xff, ++0xed,0x2f,0x90,0x91,0x44,0xf0,0x90,0x00,0x04,0x12,0x42,0x20,0xff,0xae,0x05,0xed, ++0x2f,0x90,0x91,0x45,0xf0,0x22,0xd3,0x10,0xaf,0x01,0xc3,0xc0,0xd0,0x90,0x91,0x47, ++0xe0,0x90,0x91,0x1d,0xf0,0x90,0x91,0x48,0xe0,0xf5,0x19,0xa3,0xe0,0xf5,0x1a,0xe4, ++0xf5,0x16,0x74,0x4a,0x25,0x16,0xf5,0x82,0xe4,0x34,0x91,0xf5,0x83,0xe0,0xff,0x74, ++0x1b,0x25,0x16,0xf8,0xa6,0x07,0x05,0x16,0xe5,0x16,0xb4,0x04,0xe5,0x90,0x91,0x1d, ++0xe0,0x12,0x43,0x4a,0x66,0xb3,0x00,0x67,0xdc,0x01,0x66,0xba,0x02,0x66,0xba,0x03, ++0x66,0xba,0x04,0x67,0xdc,0x05,0x67,0xac,0x80,0x67,0xc2,0x81,0x67,0xdc,0x82,0x00, ++0x00,0x67,0xd8,0xaf,0x1e,0x12,0x73,0xea,0xe1,0xdc,0x90,0x91,0x1d,0xe0,0xff,0xb4, ++0x02,0x08,0x90,0x91,0x1c,0x74,0x01,0xf0,0x80,0x0f,0xef,0x90,0x91,0x1c,0xb4,0x03, ++0x05,0x74,0x02,0xf0,0x80,0x03,0x74,0x04,0xf0,0xc3,0xe5,0x19,0x94,0x08,0x50,0x49, ++0xe4,0xf5,0x16,0x90,0x91,0x1c,0xe0,0xff,0xe5,0x16,0xc3,0x9f,0x40,0x02,0xe1,0xdc, ++0xc3,0xe5,0x19,0x94,0x01,0x50,0x14,0xe5,0x16,0x25,0x1a,0xff,0xc3,0x74,0x03,0x95, ++0x16,0x24,0x1b,0xf8,0xe6,0xfd,0x12,0x4b,0xee,0x80,0x1a,0xc3,0x74,0x03,0x95,0x16, ++0x24,0x1b,0xf8,0xe6,0xff,0xe5,0x16,0x7c,0x00,0x25,0x1a,0xfd,0xec,0x35,0x19,0x8d, ++0x82,0xf5,0x83,0xef,0xf0,0x05,0x16,0x80,0xba,0xc3,0xe5,0x19,0x94,0x10,0x40,0x02, ++0xe1,0xdc,0x90,0x91,0x1d,0xe0,0x64,0x04,0x60,0x02,0xe1,0xdc,0xaf,0x1c,0xfc,0xfd, ++0xfe,0x78,0x10,0x12,0x24,0xf5,0xc0,0x04,0xc0,0x05,0xc0,0x06,0xc0,0x07,0xaf,0x1b, ++0xe4,0xfc,0xfd,0xfe,0x78,0x18,0x12,0x24,0xf5,0xd0,0x03,0xd0,0x02,0xd0,0x01,0xd0, ++0x00,0x12,0x42,0xfc,0xc0,0x04,0xc0,0x05,0xc0,0x06,0xc0,0x07,0xaf,0x1d,0xe4,0xfc, ++0xfd,0xfe,0x78,0x08,0x12,0x24,0xf5,0xd0,0x03,0xd0,0x02,0xd0,0x01,0xd0,0x00,0x12, ++0x42,0xfc,0xa8,0x04,0xa9,0x05,0xaa,0x06,0xab,0x07,0xaf,0x1e,0xe4,0xfc,0xfd,0xfe, ++0x12,0x42,0xfc,0xa3,0x12,0x25,0x08,0x90,0x91,0x1e,0x12,0x43,0x09,0x90,0x80,0x96, ++0x12,0x25,0x08,0xaf,0x1a,0xae,0x19,0x12,0x2b,0x08,0x80,0x30,0xe5,0x1d,0x7f,0x00, ++0xfe,0xef,0x25,0x1e,0xf5,0x18,0xe4,0x3e,0xf5,0x17,0xaf,0x18,0xfe,0x12,0x32,0x15, ++0x80,0x1a,0xe5,0x1d,0x7f,0x00,0xfe,0xef,0x25,0x1e,0xf5,0x18,0xe4,0x3e,0xf5,0x17, ++0xaf,0x18,0xfe,0x12,0x31,0x82,0x80,0x04,0x7f,0x00,0x80,0x02,0x7f,0x01,0xd0,0xd0, ++0x92,0xaf,0x22,0x22,0x8e,0x0e,0x8f,0x0f,0x8b,0x10,0x8a,0x11,0x89,0x12,0xe4,0x90, ++0x91,0x11,0xf0,0xef,0x90,0x00,0x31,0xf0,0x12,0x4a,0xe6,0xe5,0x0e,0x54,0x03,0xff, ++0x90,0x00,0x32,0xe0,0x54,0xfc,0x4f,0xf0,0x12,0x4a,0xe6,0x90,0x00,0x33,0xe0,0x54, ++0x7f,0xf0,0x12,0x4a,0xe6,0x90,0x00,0x33,0xe0,0x20,0xe7,0x0e,0x90,0x91,0x11,0xe0, ++0xc3,0x94,0x64,0x50,0x05,0xe0,0x04,0xf0,0x80,0xeb,0x90,0x91,0x11,0xe0,0xc3,0x94, ++0x64,0x50,0x10,0x90,0x00,0x30,0xe0,0xab,0x10,0xaa,0x11,0xa9,0x12,0x12,0x42,0x4d, ++0x7f,0x01,0x22,0x7f,0x00,0x22,0xe4,0x90,0x91,0x98,0xf0,0xa3,0xf0,0x90,0x05,0xf8, ++0xe0,0x70,0x0f,0xa3,0xe0,0x70,0x0b,0xa3,0xe0,0x70,0x07,0xa3,0xe0,0x70,0x03,0x7f, ++0x01,0x22,0xd3,0x90,0x91,0x99,0xe0,0x94,0xe8,0x90,0x91,0x98,0xe0,0x94,0x03,0x40, ++0x03,0x7f,0x00,0x22,0x7f,0x32,0x7e,0x00,0x12,0x32,0x15,0x90,0x91,0x98,0xe4,0x75, ++0xf0,0x01,0x12,0x42,0x81,0x80,0xc6,0xef,0x70,0x02,0x41,0x3d,0x90,0x90,0xe8,0xe0, ++0x60,0x02,0xc1,0x08,0x90,0x90,0xd4,0x12,0x43,0x09,0x90,0x80,0x96,0x12,0x25,0x08, ++0x7f,0x8c,0x7e,0x08,0x12,0x2b,0x08,0x90,0x90,0x80,0x12,0x43,0x09,0x90,0x80,0x96, ++0x12,0x25,0x08,0x7f,0x44,0x7e,0x08,0x12,0x2b,0x08,0x90,0x90,0x84,0x12,0x43,0x09, ++0x90,0x80,0x96,0x12,0x25,0x08,0x7f,0x5c,0x7e,0x08,0x12,0x2b,0x08,0x90,0x90,0x88, ++0x12,0x43,0x09,0x90,0x80,0x96,0x12,0x25,0x08,0x7f,0x6c,0x7e,0x0e,0x12,0x2b,0x08, ++0x90,0x90,0x8c,0x12,0x43,0x09,0x90,0x80,0x96,0x12,0x25,0x08,0x7f,0x70,0x7e,0x0e, ++0x12,0x2b,0x08,0x90,0x90,0x90,0x12,0x43,0x09,0x90,0x80,0x96,0x12,0x25,0x08,0x7f, ++0x74,0x7e,0x0e,0x12,0x2b,0x08,0x90,0x90,0x94,0x12,0x43,0x09,0x90,0x80,0x96,0x12, ++0x25,0x08,0x7f,0x78,0x7e,0x0e,0x12,0x2b,0x08,0x90,0x90,0x98,0x12,0x43,0x09,0x90, ++0x80,0x96,0x12,0x25,0x08,0x7f,0x7c,0x7e,0x0e,0x12,0x2b,0x08,0x90,0x90,0x9c,0x12, ++0x43,0x09,0x90,0x80,0x96,0x12,0x25,0x08,0x7f,0x80,0x7e,0x0e,0x12,0x2b,0x08,0x90, ++0x90,0xa0,0x12,0x43,0x09,0x90,0x80,0x96,0x12,0x25,0x08,0x7f,0x84,0x7e,0x0e,0x12, ++0x2b,0x08,0x90,0x90,0xa4,0x12,0x43,0x09,0x90,0x80,0x96,0x12,0x25,0x08,0x7f,0x88, ++0x7e,0x0e,0x12,0x2b,0x08,0x90,0x90,0xa8,0x12,0x43,0x09,0x90,0x80,0x96,0x12,0x25, ++0x08,0x7f,0x8c,0x7e,0x0e,0x12,0x2b,0x08,0x90,0x90,0xac,0x12,0x43,0x09,0x90,0x80, ++0x96,0x12,0x25,0x08,0x7f,0xd0,0x7e,0x0e,0x12,0x2b,0x08,0x90,0x90,0xb0,0x12,0x43, ++0x09,0x90,0x80,0x96,0x12,0x25,0x08,0x7f,0xd4,0x7e,0x0e,0x12,0x2b,0x08,0x90,0x90, ++0xb4,0x12,0x43,0x09,0x90,0x80,0x96,0x12,0x25,0x08,0x7f,0xd8,0x7e,0x0e,0x12,0x2b, ++0x08,0x90,0x90,0xb8,0x12,0x43,0x09,0x90,0x80,0x96,0x12,0x25,0x08,0x7f,0xdc,0x7e, ++0x0e,0x12,0x2b,0x08,0x90,0x90,0xbc,0x12,0x43,0x09,0x90,0x80,0x96,0x12,0x25,0x08, ++0x7f,0xe0,0x7e,0x0e,0x12,0x2b,0x08,0x90,0x90,0xc0,0x12,0x43,0x09,0x90,0x80,0x96, ++0x12,0x25,0x08,0x7f,0xec,0x7e,0x0e,0x12,0x2b,0x08,0x90,0x90,0xc4,0x12,0x43,0x09, ++0x90,0x80,0x96,0x12,0x25,0x08,0x7f,0x04,0x7e,0x0c,0x12,0x2b,0x08,0x90,0x90,0xc8, ++0x12,0x43,0x09,0x90,0x80,0x96,0x12,0x25,0x08,0x7f,0x04,0x7e,0x0d,0x12,0x2b,0x08, ++0x90,0x90,0xcc,0x12,0x43,0x09,0x90,0x80,0x96,0x12,0x25,0x08,0x7f,0x0c,0x7e,0x09, ++0x12,0x2b,0x08,0x90,0x90,0xd0,0x12,0x43,0x09,0x90,0x80,0x96,0x12,0x25,0x08,0x7f, ++0x04,0x7e,0x08,0x12,0x2b,0x08,0x90,0x90,0xe8,0x74,0x01,0xf0,0x22,0x90,0x90,0xe8, ++0xe0,0x64,0x01,0x60,0x02,0xc1,0x08,0x7f,0x8c,0x7e,0x08,0x12,0x22,0x65,0x90,0x90, ++0xd4,0x12,0x25,0x08,0x7f,0x44,0x7e,0x08,0x12,0x22,0x65,0x90,0x90,0x80,0x12,0x25, ++0x08,0x7f,0x5c,0x7e,0x08,0x12,0x22,0x65,0x90,0x90,0x84,0x12,0x25,0x08,0x7f,0x6c, ++0x7e,0x0e,0x12,0x22,0x65,0x90,0x90,0x88,0x12,0x25,0x08,0x7f,0x70,0x7e,0x0e,0x12, ++0x22,0x65,0x90,0x90,0x8c,0x12,0x25,0x08,0x7f,0x74,0x7e,0x0e,0x12,0x22,0x65,0x90, ++0x90,0x90,0x12,0x25,0x08,0x7f,0x78,0x7e,0x0e,0x12,0x22,0x65,0x90,0x90,0x94,0x12, ++0x25,0x08,0x7f,0x7c,0x7e,0x0e,0x12,0x22,0x65,0x90,0x90,0x98,0x12,0x25,0x08,0x7f, ++0x80,0x7e,0x0e,0x12,0x22,0x65,0x90,0x90,0x9c,0x12,0x25,0x08,0x7f,0x84,0x7e,0x0e, ++0x12,0x22,0x65,0x90,0x90,0xa0,0x12,0x25,0x08,0x7f,0x88,0x7e,0x0e,0x12,0x22,0x65, ++0x90,0x90,0xa4,0x12,0x25,0x08,0x7f,0x8c,0x7e,0x0e,0x12,0x22,0x65,0x90,0x90,0xa8, ++0x12,0x25,0x08,0x7f,0xd0,0x7e,0x0e,0x12,0x22,0x65,0x90,0x90,0xac,0x12,0x25,0x08, ++0x7f,0xd4,0x7e,0x0e,0x12,0x22,0x65,0x90,0x90,0xb0,0x12,0x25,0x08,0x7f,0xd8,0x7e, ++0x0e,0x12,0x22,0x65,0x90,0x90,0xb4,0x12,0x25,0x08,0x7f,0xdc,0x7e,0x0e,0x12,0x22, ++0x65,0x90,0x90,0xb8,0x12,0x25,0x08,0x7f,0xe0,0x7e,0x0e,0x12,0x22,0x65,0x90,0x90, ++0xbc,0x12,0x25,0x08,0x7f,0xec,0x7e,0x0e,0x12,0x22,0x65,0x90,0x90,0xc0,0x12,0x25, ++0x08,0x7f,0x04,0x7e,0x0c,0x12,0x22,0x65,0x90,0x90,0xc4,0x12,0x25,0x08,0x7f,0x04, ++0x7e,0x0d,0x12,0x22,0x65,0x90,0x90,0xc8,0x12,0x25,0x08,0x7f,0x0c,0x7e,0x09,0x12, ++0x22,0x65,0x90,0x90,0xcc,0x12,0x25,0x08,0x7f,0x04,0x7e,0x08,0x12,0x22,0x65,0x90, ++0x90,0xd0,0x12,0x25,0x08,0x7f,0x8c,0x7e,0x08,0x12,0x22,0x65,0x90,0x91,0x88,0x12, ++0x25,0x08,0x90,0x91,0x88,0x12,0x43,0x09,0xed,0x44,0xc0,0xfd,0xec,0x90,0x91,0x88, ++0x12,0x25,0x08,0x90,0x91,0x88,0x12,0x43,0x09,0x90,0x80,0x96,0x12,0x25,0x08,0x7f, ++0x8c,0x7e,0x08,0x12,0x2b,0x08,0x90,0x80,0x96,0x12,0x25,0x14,0x00,0x01,0x00,0x00, ++0x7f,0x44,0x7e,0x08,0x12,0x2b,0x08,0x90,0x80,0x96,0x12,0x25,0x14,0x00,0xdb,0x25, ++0xa4,0x7f,0x5c,0x7e,0x08,0x12,0x2b,0x08,0x90,0x80,0x96,0x12,0x25,0x14,0x20,0xdb, ++0x25,0xa4,0x7f,0x6c,0x7e,0x0e,0x12,0x2b,0x08,0x90,0x80,0x96,0x12,0x25,0x14,0x20, ++0xdb,0x25,0xa4,0x7f,0x70,0x7e,0x0e,0x12,0x2b,0x08,0x90,0x80,0x96,0x12,0x25,0x14, ++0x04,0x1b,0x25,0xa4,0x7f,0x74,0x7e,0x0e,0x12,0x2b,0x08,0x90,0x80,0x96,0x12,0x25, ++0x14,0x04,0x1b,0x25,0xa4,0x7f,0x78,0x7e,0x0e,0x12,0x2b,0x08,0x90,0x80,0x96,0x12, ++0x25,0x14,0x04,0x1b,0x25,0xa4,0x7f,0x7c,0x7e,0x0e,0x12,0x2b,0x08,0x90,0x80,0x96, ++0x12,0x25,0x14,0x04,0x1b,0x25,0xa4,0x7f,0x80,0x7e,0x0e,0x12,0x2b,0x08,0x90,0x80, ++0x96,0x12,0x25,0x14,0x63,0xdb,0x25,0xa4,0x7f,0x84,0x7e,0x0e,0x12,0x2b,0x08,0x90, ++0x80,0x96,0x12,0x25,0x14,0x04,0x1b,0x25,0xa4,0x7f,0x88,0x7e,0x0e,0x12,0x2b,0x08, ++0x90,0x80,0x96,0x12,0x25,0x14,0x20,0xdb,0x25,0xa4,0x7f,0x8c,0x7e,0x0e,0x12,0x2b, ++0x08,0x90,0x80,0x96,0x12,0x25,0x14,0x20,0xdb,0x25,0xa4,0x7f,0xd0,0x7e,0x0e,0x12, ++0x2b,0x08,0x90,0x80,0x96,0x12,0x25,0x14,0x20,0xdb,0x25,0xa4,0x7f,0xd4,0x7e,0x0e, ++0x12,0x2b,0x08,0x90,0x80,0x96,0x12,0x25,0x14,0x20,0xdb,0x25,0xa4,0x7f,0xd8,0x7e, ++0x0e,0x12,0x2b,0x08,0x90,0x80,0x96,0x12,0x25,0x14,0x00,0x1b,0x25,0xa4,0x7f,0xdc, ++0x7e,0x0e,0x12,0x2b,0x08,0x90,0x80,0x96,0x12,0x25,0x14,0x00,0x1b,0x25,0xa4,0x7f, ++0xe0,0x7e,0x0e,0x12,0x2b,0x08,0x90,0x80,0x96,0x12,0x25,0x14,0x24,0xdb,0x25,0xa4, ++0x7f,0xec,0x7e,0x0e,0x12,0x2b,0x08,0x7f,0x04,0x7e,0x0c,0x12,0x22,0x65,0x90,0x91, ++0x88,0x12,0x25,0x08,0x90,0x91,0x88,0x12,0x43,0x09,0xe4,0xff,0xec,0x90,0x91,0x88, ++0x12,0x25,0x08,0x90,0x91,0x88,0x12,0x43,0x09,0xef,0x44,0x11,0xff,0xec,0x90,0x91, ++0x88,0x12,0x25,0x08,0x90,0x91,0x88,0x12,0x43,0x09,0x90,0x80,0x96,0x12,0x25,0x08, ++0x7f,0x04,0x7e,0x0c,0x12,0x2b,0x08,0x7f,0x04,0x7e,0x0d,0x12,0x22,0x65,0x90,0x91, ++0x88,0x12,0x25,0x08,0x90,0x91,0x88,0x12,0x43,0x09,0xef,0x54,0xf0,0xff,0xec,0x90, ++0x91,0x88,0x12,0x25,0x08,0x90,0x91,0x88,0x12,0x43,0x09,0xef,0x44,0x01,0xff,0xec, ++0x90,0x91,0x88,0x12,0x25,0x08,0x90,0x91,0x88,0x12,0x43,0x09,0x90,0x80,0x96,0x12, ++0x25,0x08,0x7f,0x04,0x7e,0x0d,0x12,0x2b,0x08,0x7f,0x0c,0x7e,0x09,0x12,0x22,0x65, ++0x90,0x91,0x88,0x12,0x25,0x08,0x90,0x91,0x88,0x12,0x43,0x09,0xe4,0xff,0xec,0x90, ++0x91,0x88,0x12,0x25,0x08,0x90,0x91,0x88,0x12,0x43,0x09,0xef,0x44,0x11,0xff,0xec, ++0x90,0x91,0x88,0x12,0x25,0x08,0x90,0x91,0x88,0x12,0x43,0x09,0x90,0x80,0x96,0x12, ++0x25,0x08,0x7f,0x0c,0x7e,0x09,0x12,0x2b,0x08,0x7f,0x0c,0x7e,0x09,0x12,0x22,0x65, ++0x90,0x91,0x88,0x12,0x25,0x08,0x90,0x91,0x88,0x12,0x43,0x09,0xed,0x54,0x0f,0xfd, ++0xec,0x54,0xf0,0xfc,0x90,0x91,0x88,0x12,0x25,0x08,0x90,0x91,0x88,0x12,0x43,0x09, ++0xed,0x44,0x10,0xfd,0xec,0x44,0x01,0xfc,0x90,0x91,0x88,0x12,0x25,0x08,0x90,0x91, ++0x88,0x12,0x43,0x09,0x90,0x80,0x96,0x12,0x25,0x08,0x7f,0x0c,0x7e,0x09,0x12,0x2b, ++0x08,0x7f,0x04,0x7e,0x08,0x12,0x22,0x65,0x90,0x91,0x88,0x12,0x25,0x08,0x90,0x91, ++0x88,0x12,0x43,0x09,0xef,0x54,0xf0,0xff,0xec,0x90,0x91,0x88,0x12,0x25,0x08,0x90, ++0x91,0x88,0x12,0x43,0x09,0xef,0x44,0x01,0xff,0xec,0x90,0x91,0x88,0x12,0x25,0x08, ++0x90,0x91,0x88,0x12,0x43,0x09,0x90,0x80,0x96,0x12,0x25,0x08,0x7f,0x04,0x7e,0x08, ++0x12,0x2b,0x08,0xe4,0x90,0x90,0xe8,0xf0,0x22,0xe4,0xfd,0x7f,0x45,0x12,0x4b,0xee, ++0x90,0x04,0xfd,0xe4,0xf0,0xa3,0xf0,0x90,0x90,0xf7,0xf0,0x90,0x90,0xfd,0xf0,0x90, ++0x91,0x00,0xf0,0x90,0x90,0xfe,0xf0,0x90,0x91,0x01,0xf0,0x90,0x90,0xff,0xf0,0x90, ++0x91,0x02,0xf0,0x90,0x90,0xe9,0x04,0xf0,0xe4,0xa3,0xf0,0xa3,0xf0,0xa3,0xf0,0x90, ++0x90,0xee,0xf0,0x90,0x90,0xf3,0xf0,0x90,0x90,0xf5,0xf0,0x90,0x91,0x07,0xf0,0x90, ++0x90,0xf8,0xf0,0x90,0x90,0xf4,0xf0,0x90,0x90,0xed,0xf0,0x90,0x00,0x51,0xe0,0x44, ++0xc0,0xfd,0x7f,0x51,0x02,0x4b,0xee,0x90,0x05,0x60,0xe0,0x90,0x91,0x03,0xf0,0x90, ++0x05,0x61,0xe0,0x90,0x91,0x04,0xf0,0x90,0x05,0x62,0xe0,0x90,0x91,0x05,0xf0,0x90, ++0x05,0x63,0xe0,0x90,0x91,0x06,0xf0,0xc3,0x74,0xff,0x9f,0xfe,0x90,0x91,0x04,0xe0, ++0xd3,0x9e,0x40,0x1e,0xe0,0x2f,0xf0,0xa3,0xe0,0xb4,0xff,0x0f,0xe4,0xf0,0xa3,0xe0, ++0xb4,0xff,0x03,0xe4,0xf0,0x22,0x90,0x91,0x06,0x80,0x03,0x90,0x91,0x05,0xe0,0x04, ++0xf0,0x22,0x90,0x91,0x04,0xe0,0x2f,0xf0,0x22,0x90,0x90,0xf5,0xe0,0x64,0x01,0x60, ++0x02,0xe1,0x6e,0x90,0x00,0x46,0xe0,0x44,0x01,0xfd,0x7f,0x46,0x12,0x4b,0xee,0x90, ++0x91,0x07,0xe0,0x70,0x32,0x90,0x90,0xed,0xe0,0x60,0x15,0x90,0x90,0xf9,0x12,0x43, ++0x09,0x90,0x80,0x96,0x12,0x25,0x08,0x7f,0x80,0x7e,0x08,0x12,0x2b,0x08,0x80,0x06, ++0x90,0x05,0x22,0x74,0x7f,0xf0,0x90,0x90,0xf4,0xe0,0xff,0xd1,0x67,0x90,0x91,0x07, ++0x74,0x01,0x12,0x4b,0xe4,0x80,0x40,0x90,0x91,0x07,0xe0,0x64,0x01,0x70,0x38,0x90, ++0x90,0xf8,0xe0,0xff,0xd1,0x67,0xe4,0x90,0x91,0x07,0xf0,0x90,0x00,0x45,0xe0,0x44, ++0x01,0xfd,0x7f,0x45,0x12,0x4b,0xee,0x90,0x90,0xed,0xe0,0x60,0x15,0x90,0x90,0xef, ++0x12,0x43,0x09,0x90,0x80,0x96,0x12,0x25,0x08,0x7f,0x80,0x7e,0x08,0x12,0x2b,0x08, ++0x80,0x05,0x90,0x05,0x22,0xe4,0xf0,0x90,0x05,0x87,0xe0,0x64,0x80,0xf0,0x90,0x91, ++0x03,0xe0,0x90,0x05,0x84,0xf0,0x90,0x91,0x04,0xe0,0x90,0x05,0x85,0xf0,0x90,0x91, ++0x05,0xe0,0x90,0x05,0x86,0xf0,0x90,0x91,0x06,0xe0,0x90,0x05,0x87,0xf0,0x22,0x90, ++0x90,0xee,0xe0,0xc3,0x94,0x14,0x50,0x06,0xe0,0x04,0xf0,0x02,0x70,0x29,0x90,0x90, ++0xee,0xe0,0x64,0x14,0x60,0x03,0x02,0x70,0x29,0x90,0x90,0xfd,0xe0,0x70,0x25,0x90, ++0x91,0x00,0xe0,0x70,0x1f,0x90,0x90,0xfe,0xe0,0x70,0x19,0x90,0x91,0x01,0xe0,0x70, ++0x13,0x90,0x90,0xff,0xe0,0x70,0x0d,0x90,0x91,0x02,0xe0,0x70,0x07,0x90,0x04,0xfd, ++0xe0,0x54,0xfe,0xf0,0x90,0x90,0xfd,0xe0,0x90,0x04,0x44,0xf0,0x90,0x90,0xfe,0xe0, ++0x90,0x04,0x45,0xf0,0x90,0x90,0xff,0xe0,0x90,0x04,0x46,0xf0,0xa3,0xe4,0xf0,0x90, ++0x91,0x00,0xe0,0x90,0x04,0x48,0xf0,0x90,0x91,0x01,0xe0,0x90,0x04,0x49,0xf0,0x90, ++0x91,0x02,0xe0,0x90,0x04,0x4a,0xf0,0xa3,0xe4,0xf0,0x90,0x90,0xe9,0xe0,0x90,0x04, ++0x4c,0xf0,0x90,0x90,0xea,0xe0,0x90,0x04,0x4d,0xf0,0x90,0x90,0xeb,0xe0,0x90,0x04, ++0x4e,0xf0,0x90,0x90,0xec,0xe0,0x90,0x04,0x4f,0xf0,0xe4,0x90,0x90,0xee,0xf0,0x90, ++0x90,0xe9,0x04,0xf0,0xe4,0xa3,0xf0,0xa3,0xf0,0xa3,0xf0,0x90,0x90,0xfd,0xf0,0xa3, ++0xf0,0xa3,0xf0,0xa3,0xf0,0xa3,0xf0,0xa3,0xf0,0x90,0x05,0x60,0xe0,0x90,0x91,0x8c, ++0xf0,0x90,0x05,0x61,0xe0,0x90,0x91,0x8d,0xf0,0x90,0x05,0x62,0xe0,0x90,0x91,0x8e, ++0xf0,0x90,0x05,0x63,0xe0,0x90,0x91,0x8f,0xf0,0x90,0x91,0x06,0xe0,0xff,0x90,0x91, ++0x8f,0xe0,0xfe,0xd3,0x9f,0x50,0x0b,0x90,0x91,0x06,0xe0,0xc3,0x9e,0xd3,0x94,0x01, ++0x40,0x11,0x90,0x90,0xf4,0xe0,0xb4,0x01,0x02,0x80,0x03,0x90,0x90,0xf8,0xe0,0xff, ++0x12,0x6e,0x67,0x22,0x90,0x91,0x07,0xe0,0x64,0x01,0x60,0x08,0x90,0x90,0xf5,0xe0, ++0x60,0x02,0x21,0x4b,0x90,0x90,0xe9,0xe0,0xc3,0x94,0xff,0x50,0x05,0xe0,0x04,0xf0, ++0x80,0x3b,0x90,0x90,0xea,0xe0,0xc3,0x94,0xff,0x50,0x06,0xe0,0x04,0xf0,0xe4,0x80, ++0x28,0x90,0x90,0xeb,0xe0,0xc3,0x94,0xff,0x50,0x0a,0xe0,0x04,0xf0,0xe4,0x90,0x90, ++0xea,0xf0,0x80,0x15,0x90,0x90,0xec,0xe0,0xc3,0x94,0xff,0x50,0x10,0xe0,0x04,0xf0, ++0xe4,0x90,0x90,0xeb,0xf0,0x90,0x90,0xea,0xf0,0x90,0x90,0xe9,0xf0,0x90,0x00,0x44, ++0xe0,0x54,0x0c,0x60,0x76,0xe0,0x30,0xe2,0x32,0x90,0x90,0xfd,0xe0,0xc3,0x94,0xff, ++0x50,0x05,0xe0,0x04,0xf0,0x80,0x24,0x90,0x90,0xfe,0xe0,0xc3,0x94,0xff,0x50,0x06, ++0xe0,0x04,0xf0,0xe4,0x80,0x11,0x90,0x90,0xff,0xe0,0xc3,0x94,0xff,0x50,0x0c,0xe0, ++0x04,0xf0,0xe4,0x90,0x90,0xfe,0xf0,0x90,0x90,0xfd,0xf0,0x90,0x00,0x44,0xe0,0x30, ++0xe3,0x32,0x90,0x91,0x00,0xe0,0xc3,0x94,0xff,0x50,0x05,0xe0,0x04,0xf0,0x80,0x24, ++0x90,0x91,0x01,0xe0,0xc3,0x94,0xff,0x50,0x06,0xe0,0x04,0xf0,0xe4,0x80,0x11,0x90, ++0x91,0x02,0xe0,0xc3,0x94,0xff,0x50,0x0c,0xe0,0x04,0xf0,0xe4,0x90,0x91,0x01,0xf0, ++0x90,0x91,0x00,0xf0,0x90,0x04,0xfd,0xe0,0x44,0x01,0xf0,0x22,0x90,0x06,0x90,0xe0, ++0x44,0x01,0xf0,0x90,0x91,0x61,0xe0,0x30,0xe0,0x3c,0x90,0x91,0x5f,0xe0,0xff,0x90, ++0x91,0x5e,0xe0,0xfe,0xc4,0x13,0x54,0x01,0xfd,0x12,0x4a,0xf6,0x90,0x91,0x60,0xe0, ++0x75,0xf0,0x20,0xa4,0xff,0xae,0xf0,0x12,0x32,0x15,0x90,0x91,0x5e,0xe0,0xc4,0x13, ++0x54,0x07,0x30,0xe0,0x07,0xa3,0xe0,0xff,0xe4,0xfd,0x80,0x07,0x90,0x91,0x5f,0xe0, ++0xff,0x7d,0x01,0x12,0x4a,0xf6,0x22,0xd3,0x10,0xaf,0x01,0xc3,0xc0,0xd0,0xe4,0x90, ++0x91,0x19,0xf0,0xa3,0x74,0x08,0xf0,0xa3,0xf0,0xe4,0xa3,0xf0,0x90,0x01,0x1f,0xe0, ++0xfe,0x90,0x01,0x1e,0xe0,0x7c,0x00,0x24,0x00,0xff,0xec,0x3e,0x90,0x91,0x11,0xf0, ++0xa3,0xef,0xf0,0x90,0x02,0x87,0xe0,0x90,0x91,0x18,0xf0,0x90,0x91,0x56,0xe0,0x20, ++0xe0,0x02,0x61,0xc4,0xe4,0x90,0x91,0x17,0xf0,0x90,0x91,0x18,0xe0,0xff,0x90,0x91, ++0x17,0xe0,0xc3,0x9f,0x40,0x02,0x61,0xc4,0x90,0x91,0x11,0xe0,0xfc,0xa3,0xe0,0xfd, ++0xec,0xff,0x90,0xfd,0x11,0xf0,0x90,0x91,0x1c,0xef,0xf0,0x74,0x02,0x2d,0xf5,0x82, ++0xe4,0x34,0xfb,0xf5,0x83,0xe0,0x54,0x0f,0xfc,0x33,0x33,0x33,0x54,0xf8,0xff,0xed, ++0x24,0x18,0x2f,0x90,0x91,0x15,0xf0,0xe0,0x24,0x00,0xf5,0x82,0xe4,0x34,0xfb,0xf5, ++0x83,0xe0,0x54,0xfc,0x90,0x91,0x16,0xf0,0x74,0x01,0x2d,0xf5,0x82,0xe4,0x34,0xfb, ++0xf5,0x83,0xe0,0xfe,0x74,0x00,0x2d,0xf5,0x82,0xe4,0x34,0xfb,0xf5,0x83,0xe0,0x7a, ++0x00,0x24,0x00,0xff,0xea,0x3e,0x54,0x3f,0xab,0x07,0xfa,0x90,0x91,0x13,0xf0,0xa3, ++0xeb,0xf0,0xaf,0x04,0xef,0x75,0xf0,0x08,0xa4,0x24,0x18,0xff,0xe4,0x35,0xf0,0xfe, ++0xef,0x2b,0xfb,0xee,0x3a,0xfa,0x90,0x91,0x5a,0xe0,0xfe,0xa3,0xe0,0xff,0xad,0x03, ++0xac,0x02,0x12,0x45,0x09,0xaa,0x06,0xab,0x07,0x90,0x91,0x15,0xe0,0x24,0x00,0xf5, ++0x82,0xe4,0x34,0xfb,0xf5,0x83,0xe0,0x30,0xe7,0x08,0x90,0x91,0x19,0x74,0x02,0xf0, ++0x80,0x05,0xe4,0x90,0x91,0x19,0xf0,0xaf,0x03,0x90,0x91,0x11,0xea,0x8f,0xf0,0x12, ++0x42,0x81,0x90,0x91,0x5c,0xe0,0xfe,0xa3,0xe0,0xff,0x90,0x91,0x11,0xe0,0xfc,0xa3, ++0xe0,0xfd,0xd3,0x9f,0xec,0x9e,0x40,0x1b,0x90,0x91,0x5d,0xe0,0x24,0x01,0xff,0x90, ++0x91,0x5c,0xe0,0x34,0x00,0xfe,0xc3,0xed,0x9f,0xff,0xec,0x9e,0x90,0x91,0x11,0xf0, ++0xa3,0xef,0xf0,0x90,0x91,0x16,0xe0,0xff,0x24,0x40,0x60,0x04,0x24,0x20,0x70,0x27, ++0x90,0x91,0x5e,0xe0,0xfe,0xc4,0x13,0x13,0x13,0x54,0x01,0x20,0xe0,0x02,0x61,0x9c, ++0xef,0x90,0x00,0x81,0xb4,0xa0,0x05,0xe0,0x44,0x04,0x80,0x03,0xe0,0x44,0x08,0xfd, ++0x7f,0x81,0x12,0x4b,0xee,0x61,0x95,0x90,0x91,0x5e,0xe0,0xc4,0x13,0x13,0x54,0x03, ++0x20,0xe0,0x02,0x61,0x9c,0x90,0x91,0x15,0xe0,0xff,0x24,0x00,0xf5,0x82,0xe4,0x34, ++0xfb,0xf5,0x83,0xe0,0x54,0x0c,0x64,0x08,0x70,0x72,0x90,0x91,0x19,0xe0,0xfe,0xef, ++0x2e,0xff,0xa3,0xe0,0x2f,0xff,0x24,0x1e,0xf5,0x82,0xe4,0x34,0xfb,0xf5,0x83,0xe0, ++0x64,0x88,0x70,0x58,0x74,0x1f,0x2f,0xf5,0x82,0xe4,0x34,0xfb,0xf5,0x83,0xe0,0x64, ++0x8e,0x70,0x49,0x90,0x91,0x19,0xe0,0xff,0x90,0x91,0x15,0xe0,0x2f,0xff,0x90,0x91, ++0x1a,0xe0,0x2f,0xff,0xa3,0xe0,0x2f,0xff,0x24,0x19,0xf5,0x82,0xe4,0x34,0xfb,0xf5, ++0x83,0xe0,0x64,0x03,0x70,0x26,0x74,0x1e,0x2f,0xf5,0x82,0xe4,0x34,0xfb,0xf5,0x83, ++0xe0,0x90,0x00,0x81,0x30,0xe3,0x05,0xe0,0x44,0x01,0x80,0x03,0xe0,0x44,0x02,0xfd, ++0x7f,0x81,0x12,0x4b,0xee,0x90,0x91,0x56,0xe0,0x44,0x80,0xf0,0x90,0x91,0x56,0xe0, ++0xff,0xc4,0x13,0x13,0x13,0x54,0x01,0x30,0xe0,0x02,0x31,0x4c,0x71,0xc9,0xbf,0x01, ++0x13,0x90,0x91,0x11,0xe0,0xfe,0xa3,0xe0,0xff,0x12,0x44,0xb5,0x90,0x91,0x17,0xe0, ++0x04,0xf0,0x21,0xd9,0xd0,0xd0,0x92,0xaf,0x22,0x90,0x91,0x56,0xe0,0xc4,0x13,0x13, ++0x13,0x54,0x01,0x30,0xe0,0x11,0xe0,0x44,0x80,0xf0,0x90,0x91,0x5e,0xe0,0xc4,0x54, ++0x0f,0x20,0xe0,0x03,0x7f,0x00,0x22,0x7f,0x01,0x22,0x8f,0x1f,0xe4,0x90,0x91,0x22, ++0xf0,0xe5,0x1f,0x14,0xfe,0x90,0x91,0x22,0xe0,0xff,0xc3,0x9e,0x50,0x0e,0xef,0x04, ++0xfd,0x12,0x2d,0x4d,0x90,0x91,0x22,0xe0,0x04,0xf0,0x80,0xe5,0xe5,0x1f,0x14,0xff, ++0x7d,0xff,0x12,0x2d,0x4d,0x90,0x91,0x22,0xe5,0x1f,0xf0,0x90,0x91,0x22,0xe0,0xc3, ++0x94,0xff,0x50,0x0f,0xe0,0xff,0x04,0xfd,0x12,0x2d,0x4d,0x90,0x91,0x22,0xe0,0x04, ++0xf0,0x80,0xe8,0xad,0x1f,0x7f,0xff,0x02,0x2d,0x4d,0xc3,0xee,0x94,0x01,0x40,0x0a, ++0x0d,0xed,0x13,0x90,0xfd,0x10,0xf0,0xe4,0x2f,0xff,0x22,0xc3,0xee,0x94,0x01,0x40, ++0x1e,0x90,0xfd,0x11,0xe0,0xb5,0x05,0x14,0x90,0x01,0x17,0xe0,0xb5,0x05,0x07,0x90, ++0xfd,0x11,0xe4,0xf0,0x80,0x06,0xed,0x04,0x90,0xfd,0x11,0xf0,0xe4,0x2f,0xff,0x22, ++0x14,0x25,}; ++ ++ ++ ++u8 Rtl8192CUFwUMCBCutWWImgArray[UMCBCutWWImgArrayLength] = { ++0xc2,0x88,0x02,0x00,0x51,0x00,0x00,0x00,0x03,0x23,0x16,0x45,0x66,0x34,0x01,0x00, ++0x58,0x92,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x02,0x43,0x9d,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x02,0x4a,0x22,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x02,0x57,0xe1,0x00,0x00,0x00,0x00,0x00,0x02,0x58,0xc4,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, ++0xbb,0x01,0x0c,0xe5,0x82,0x29,0xf5,0x82,0xe5,0x83,0x3a,0xf5,0x83,0xe0,0x22,0x50, ++0x06,0xe9,0x25,0x82,0xf8,0xe6,0x22,0xbb,0xfe,0x06,0xe9,0x25,0x82,0xf8,0xe2,0x22, ++0xe5,0x82,0x29,0xf5,0x82,0xe5,0x83,0x3a,0xf5,0x83,0xe4,0x93,0x22,0xbb,0x01,0x06, ++0x89,0x82,0x8a,0x83,0xf0,0x22,0x50,0x02,0xf7,0x22,0xbb,0xfe,0x01,0xf3,0x22,0xf8, ++0xbb,0x01,0x0d,0xe5,0x82,0x29,0xf5,0x82,0xe5,0x83,0x3a,0xf5,0x83,0xe8,0xf0,0x22, ++0x50,0x06,0xe9,0x25,0x82,0xc8,0xf6,0x22,0xbb,0xfe,0x05,0xe9,0x25,0x82,0xc8,0xf2, ++0x22,0xc5,0xf0,0xf8,0xa3,0xe0,0x28,0xf0,0xc5,0xf0,0xf8,0xe5,0x82,0x15,0x82,0x70, ++0x02,0x15,0x83,0xe0,0x38,0xf0,0x22,0xbb,0x01,0x10,0xe5,0x82,0x29,0xf5,0x82,0xe5, ++0x83,0x3a,0xf5,0x83,0xe0,0xf5,0xf0,0xa3,0xe0,0x22,0x50,0x09,0xe9,0x25,0x82,0xf8, ++0x86,0xf0,0x08,0xe6,0x22,0xbb,0xfe,0x0a,0xe9,0x25,0x82,0xf8,0xe2,0xf5,0xf0,0x08, ++0xe2,0x22,0xe5,0x83,0x2a,0xf5,0x83,0xe9,0x93,0xf5,0xf0,0xa3,0xe9,0x93,0x22,0xf8, ++0xbb,0x01,0x11,0xe5,0x82,0x29,0xf5,0x82,0xe5,0x83,0x3a,0xf5,0x83,0xe8,0xf0,0xe5, ++0xf0,0xa3,0xf0,0x22,0x50,0x09,0xe9,0x25,0x82,0xc8,0xf6,0x08,0xa6,0xf0,0x22,0xbb, ++0xfe,0x09,0xe9,0x25,0x82,0xc8,0xf2,0xe5,0xf0,0x08,0xf2,0x22,0xef,0x4b,0xff,0xee, ++0x4a,0xfe,0xed,0x49,0xfd,0xec,0x48,0xfc,0x22,0xe0,0xfc,0xa3,0xe0,0xfd,0xa3,0xe0, ++0xfe,0xa3,0xe0,0xff,0x22,0xa4,0x25,0x82,0xf5,0x82,0xe5,0xf0,0x35,0x83,0xf5,0x83, ++0x22,0xe0,0xfb,0xa3,0xe0,0xfa,0xa3,0xe0,0xf9,0x22,0xf8,0xe0,0xfb,0xa3,0xa3,0xe0, ++0xf9,0x25,0xf0,0xf0,0xe5,0x82,0x15,0x82,0x70,0x02,0x15,0x83,0xe0,0xfa,0x38,0xf0, ++0x22,0xeb,0xf0,0xa3,0xea,0xf0,0xa3,0xe9,0xf0,0x22,0xd0,0x83,0xd0,0x82,0xf8,0xe4, ++0x93,0x70,0x12,0x74,0x01,0x93,0x70,0x0d,0xa3,0xa3,0x93,0xf8,0x74,0x01,0x93,0xf5, ++0x82,0x88,0x83,0xe4,0x73,0x74,0x02,0x93,0x68,0x60,0xef,0xa3,0xa3,0xa3,0x80,0xdf, ++0xd0,0x83,0xd0,0x82,0xf8,0xe4,0x93,0x70,0x12,0x74,0x01,0x93,0x70,0x0d,0xa3,0xa3, ++0x93,0xf8,0x74,0x01,0x93,0xf5,0x82,0x88,0x83,0xe4,0x73,0x74,0x02,0x93,0xb5,0xf0, ++0x06,0x74,0x03,0x93,0x68,0x60,0xe9,0xa3,0xa3,0xa3,0xa3,0x80,0xd8,0x02,0x43,0xdb, ++0x02,0x50,0x34,0xe4,0x93,0xa3,0xf8,0xe4,0x93,0xa3,0x40,0x03,0xf6,0x80,0x01,0xf2, ++0x08,0xdf,0xf4,0x80,0x29,0xe4,0x93,0xa3,0xf8,0x54,0x07,0x24,0x0c,0xc8,0xc3,0x33, ++0xc4,0x54,0x0f,0x44,0x20,0xc8,0x83,0x40,0x04,0xf4,0x56,0x80,0x01,0x46,0xf6,0xdf, ++0xe4,0x80,0x0b,0x01,0x02,0x04,0x08,0x10,0x20,0x40,0x80,0x90,0x44,0x20,0xe4,0x7e, ++0x01,0x93,0x60,0xbc,0xa3,0xff,0x54,0x3f,0x30,0xe5,0x09,0x54,0x1f,0xfe,0xe4,0x93, ++0xa3,0x60,0x01,0x0e,0xcf,0x54,0xc0,0x25,0xe0,0x60,0xa8,0x40,0xb8,0xe4,0x93,0xa3, ++0xfa,0xe4,0x93,0xa3,0xf8,0xe4,0x93,0xa3,0xc8,0xc5,0x82,0xc8,0xca,0xc5,0x83,0xca, ++0xf0,0xa3,0xc8,0xc5,0x82,0xc8,0xca,0xc5,0x83,0xca,0xdf,0xe9,0xde,0xe7,0x80,0xbe, ++0x41,0x91,0x40,0x00,0x41,0x91,0x9c,0x00,0x41,0x91,0x23,0x80,0x41,0x91,0x24,0x80, ++0x41,0x91,0x9e,0x00,0x41,0x91,0x52,0x00,0x41,0x91,0x93,0x00,0x41,0x91,0x91,0x00, ++0x41,0x91,0x90,0x00,0x41,0x91,0x92,0x00,0x00,0xf0,0x90,0x91,0x30,0xe0,0x90,0x91, ++0x67,0xf0,0xe4,0xfb,0xfd,0x7f,0x54,0x7e,0x01,0xd3,0x10,0xaf,0x01,0xc3,0xc0,0xd0, ++0x90,0x91,0x65,0xeb,0xf0,0xa3,0xe0,0xfb,0xa3,0xe0,0xf5,0x44,0xe4,0xf5,0x45,0x12, ++0x35,0xab,0xd0,0xd0,0x92,0xaf,0x22,0x90,0x01,0x5f,0xe4,0xf0,0x90,0x01,0x3c,0x74, ++0x08,0xf0,0xe4,0x90,0x91,0x66,0xf0,0x90,0x91,0x2d,0xe0,0x90,0x91,0x67,0xf0,0xe4, ++0xfb,0xfd,0x7f,0x5c,0x7e,0x01,0x91,0x59,0x90,0x01,0x5f,0x74,0x05,0xf0,0x90,0x06, ++0x92,0x74,0x02,0xf0,0x90,0x91,0x36,0x14,0xf0,0xe5,0x6e,0x54,0x0f,0xc3,0x94,0x0c, ++0x50,0x02,0xf1,0x23,0x22,0x90,0x02,0x84,0xef,0xf0,0xa3,0xee,0xf0,0xa3,0x74,0x05, ++0xf0,0x22,0x7d,0x01,0xaf,0x6f,0xe1,0x27,0xf1,0xe6,0xbf,0x01,0x10,0x90,0x91,0x42, ++0xe0,0xff,0xe4,0xfd,0x12,0x48,0x22,0x90,0x04,0x1f,0x74,0x20,0xf0,0x22,0x8f,0x82, ++0x8e,0x83,0xa3,0xa3,0xa3,0xe4,0xf0,0x22,0xe4,0xf5,0x72,0x7f,0x60,0x7e,0x01,0x80, ++0xed,0x7f,0x00,0x22,0x90,0x91,0x32,0xe0,0xa3,0xe0,0x90,0x05,0x58,0xf0,0x22,0x22, ++0x22,0x22,0x22,0x02,0x5e,0x55,0x02,0x5e,0x5c,0xef,0x8e,0xf0,0x71,0x70,0x45,0x26, ++0x00,0x40,0x45,0x4e,0x00,0x80,0x45,0x79,0x01,0x00,0x45,0x8d,0x02,0x00,0x45,0xa5, ++0x04,0x00,0x00,0x00,0x45,0xc2,0xed,0x54,0x3f,0x70,0x04,0xfe,0xff,0x80,0x04,0x7e, ++0x00,0x7f,0x40,0xef,0x2d,0xff,0xee,0x3c,0xfe,0xef,0x78,0x06,0xce,0xc3,0x13,0xce, ++0x13,0xd8,0xf9,0x78,0x06,0xc3,0x33,0xce,0x33,0xce,0xd8,0xf9,0x80,0x26,0xed,0x54, ++0x7f,0x70,0x04,0xfe,0xff,0x80,0x04,0x7e,0x00,0x7f,0x80,0xef,0x2d,0xff,0xee,0x3c, ++0xfe,0xef,0x78,0x07,0xce,0xc3,0x13,0xce,0x13,0xd8,0xf9,0x78,0x07,0xc3,0x33,0xce, ++0x33,0xce,0xd8,0xf9,0xfd,0xac,0x06,0x80,0x49,0xed,0x70,0x04,0xfe,0xff,0x80,0x04, ++0x7e,0x01,0x7f,0x00,0xef,0x2d,0xee,0x3c,0x7d,0x00,0xfc,0x80,0x35,0xec,0x54,0x01, ++0x4d,0x70,0x04,0xfe,0xff,0x80,0x04,0x7e,0x02,0x7f,0x00,0xef,0x2d,0xee,0x3c,0xc3, ++0x13,0x7d,0x00,0x80,0x1a,0xec,0x54,0x03,0x4d,0x70,0x04,0xfe,0xff,0x80,0x04,0x7e, ++0x04,0x7f,0x00,0xef,0x2d,0xee,0x3c,0x13,0x13,0x54,0x3f,0x7d,0x00,0x25,0xe0,0x25, ++0xe0,0xfc,0xae,0x04,0xaf,0x05,0x22,0x90,0x91,0x09,0x12,0x2a,0x8b,0x00,0x00,0x00, ++0x00,0x90,0x06,0xa9,0xe0,0x90,0x91,0x08,0xf0,0xe0,0x54,0xc0,0x70,0x0a,0x53,0x71, ++0xfe,0x53,0x71,0xfd,0x91,0xc2,0x80,0x47,0x90,0x91,0x26,0xe0,0x60,0x41,0x90,0x91, ++0x38,0xe0,0x70,0x3b,0x90,0x91,0x38,0x74,0x01,0xf0,0x7f,0x00,0x7e,0x08,0x12,0x27, ++0xde,0x90,0x91,0x09,0x12,0x2a,0x7f,0x90,0x91,0x09,0x71,0x09,0xec,0x44,0x02,0xfc, ++0x90,0x91,0x09,0x12,0x2a,0x7f,0x90,0x91,0x09,0x71,0x09,0x90,0x80,0x85,0x12,0x2a, ++0x7f,0x7f,0x00,0x7e,0x08,0x12,0x2f,0xd9,0x90,0x02,0x86,0xe0,0x54,0xfb,0xf0,0x90, ++0x91,0x08,0xe0,0x30,0xe6,0x13,0x43,0x71,0x01,0x90,0x91,0x3b,0xe0,0x64,0x02,0x60, ++0x04,0x91,0xc8,0x80,0x07,0x91,0x77,0x80,0x03,0x53,0x71,0xfe,0x90,0x91,0x08,0xe0, ++0x30,0xe7,0x16,0x43,0x71,0x02,0xe4,0x90,0x91,0x66,0x91,0x49,0x90,0x01,0x57,0x74, ++0x05,0xf0,0x90,0x91,0x3c,0x74,0x01,0xf0,0x22,0x53,0x71,0xfd,0x22,0xd3,0x10,0xaf, ++0x01,0xc3,0xc0,0xd0,0x8b,0x60,0x8a,0x61,0x89,0x62,0x90,0x91,0x68,0x71,0x41,0xab, ++0x63,0xaa,0x64,0xa9,0x65,0x90,0x91,0x6b,0x71,0x41,0xaf,0x66,0x15,0x66,0xef,0x60, ++0x1b,0x90,0x91,0x6b,0xe4,0x75,0xf0,0x01,0x71,0x2a,0x12,0x29,0xd9,0xff,0x90,0x91, ++0x68,0xe4,0x75,0xf0,0x01,0x71,0x2a,0xef,0x51,0x4d,0x80,0xde,0xab,0x60,0xaa,0x61, ++0xa9,0x62,0xd0,0xd0,0x92,0xaf,0x22,0xd3,0x10,0xaf,0x01,0xc3,0xc0,0xd0,0x90,0x91, ++0x6e,0x71,0x41,0x90,0x91,0x9e,0xe0,0xff,0x04,0xf0,0x90,0x00,0x01,0xef,0x51,0x5f, ++0x7f,0xaf,0x7e,0x01,0x12,0x64,0x88,0xef,0x60,0x44,0x90,0x91,0x6e,0x71,0x21,0x8b, ++0x63,0x8a,0x64,0x89,0x65,0x75,0x66,0x02,0x7b,0x01,0x7a,0x01,0x79,0xa0,0xd1,0x6d, ++0x90,0x91,0x71,0x71,0x21,0x8b,0x63,0x8a,0x64,0x89,0x65,0x90,0x91,0x6e,0x71,0x21, ++0x12,0x29,0xd9,0xff,0xc4,0x54,0x0f,0xf5,0x66,0x7b,0x01,0x7a,0x01,0x79,0xa2,0xd1, ++0x6d,0x90,0x01,0xaf,0x74,0xff,0xf0,0x90,0x01,0xcb,0xe0,0x64,0x80,0xf0,0xd0,0xd0, ++0x92,0xaf,0x22,0x7d,0x01,0x7f,0x0c,0x90,0x91,0x95,0xed,0xf0,0x90,0x91,0x94,0xef, ++0xf0,0x54,0x0f,0xff,0xe5,0x6e,0x54,0x0f,0x6f,0x60,0x76,0x90,0x91,0x94,0xe0,0x30, ++0xe2,0x30,0xe5,0x6e,0x20,0xe2,0x05,0x7f,0x01,0x12,0x61,0x86,0xe5,0x6e,0x30,0xe3, ++0x0f,0x90,0x91,0x94,0xe0,0x20,0xe3,0x08,0x12,0x60,0xb1,0xef,0x60,0x53,0x80,0x52, ++0xe5,0x6e,0x20,0xe3,0x4c,0x90,0x91,0x94,0xe0,0x30,0xe3,0x45,0xa3,0xe0,0xff,0x02, ++0x61,0x6b,0xe5,0x6e,0x54,0x0f,0xff,0xbf,0x0c,0x0f,0x90,0x91,0x94,0xe0,0x20,0xe3, ++0x08,0x12,0x60,0xb1,0xef,0x60,0x2a,0xf1,0xb2,0xe5,0x6e,0x54,0x0f,0xff,0xbf,0x04, ++0x10,0x90,0x91,0x94,0xe0,0x20,0xe2,0x09,0x12,0x60,0xfa,0xef,0x60,0x13,0x12,0x48, ++0xce,0xe5,0x6e,0x54,0x0f,0xff,0xbf,0x02,0x08,0x91,0xf1,0xef,0x60,0x03,0x12,0x62, ++0x6c,0x22,0x90,0x06,0x04,0xe0,0x44,0x40,0xf0,0xe5,0x6d,0xb4,0x01,0x04,0x7f,0x01, ++0xf1,0xc9,0x53,0x6e,0xf0,0x43,0x6e,0x04,0x22,0x8f,0x67,0xf1,0xe6,0xbf,0x01,0x15, ++0x90,0x91,0x43,0x12,0x48,0x1e,0xad,0x07,0xac,0x06,0xaf,0x67,0x12,0x60,0x16,0x90, ++0x04,0x1f,0x74,0x20,0xf0,0x22,0xd3,0x10,0xaf,0x01,0xc3,0xc0,0xd0,0x90,0x01,0xc4, ++0x74,0xe6,0xf0,0x74,0x47,0xa3,0xf0,0x90,0x04,0x1d,0xe0,0x60,0x1a,0x90,0x05,0x22, ++0xe0,0x54,0x90,0x60,0x07,0x90,0x01,0xc6,0xe0,0x44,0x40,0xf0,0x90,0x01,0xc7,0xe0, ++0x30,0xe1,0xe4,0x7f,0x00,0x80,0x02,0x7f,0x01,0xd0,0xd0,0x92,0xaf,0x22,0xe0,0xff, ++0x7d,0x01,0x90,0x91,0x74,0xef,0xf0,0xa3,0xed,0xf0,0xe4,0xa3,0xf0,0xa3,0xf0,0xe5, ++0x70,0x60,0x04,0xe4,0xff,0x11,0xb3,0x90,0x91,0x74,0xe0,0x30,0xe0,0x09,0x90,0x91, ++0x76,0xe4,0xf0,0xa3,0x74,0x80,0xf0,0x90,0x91,0x74,0xe0,0xff,0xc3,0x13,0x90,0xfd, ++0x10,0xf0,0x90,0x04,0x25,0xef,0xf0,0x90,0x91,0x75,0xe0,0x60,0x1f,0xa3,0xa3,0xe0, ++0xff,0x24,0x0f,0xf5,0x82,0xe4,0x34,0xfc,0xf5,0x83,0xe0,0x44,0x80,0xf0,0x74,0x10, ++0x2f,0xf5,0x82,0xe4,0x34,0xfc,0xf5,0x83,0xe0,0x44,0x80,0xf0,0x90,0x91,0x76,0xa3, ++0xe0,0xff,0xfd,0x24,0x08,0xf5,0x82,0xe4,0x34,0xfc,0xf5,0x83,0xe4,0xf0,0x74,0x09, ++0x2d,0xf5,0x82,0xe4,0x34,0xfc,0xf5,0x83,0xe0,0x54,0xf0,0xf0,0x74,0x21,0x2f,0xf5, ++0x82,0xe4,0x34,0xfc,0xf5,0x83,0xe0,0x54,0xf7,0xf0,0x90,0x91,0x76,0xe0,0xfe,0xa3, ++0xe0,0xff,0x22,0xef,0x60,0x0b,0x90,0x91,0x51,0xe0,0xb4,0x01,0x10,0xe4,0xff,0x80, ++0x09,0x90,0x91,0x51,0xe0,0xb4,0x01,0x05,0x7f,0x01,0x12,0x69,0x87,0x22,0x90,0x01, ++0x37,0x74,0x02,0xf0,0x90,0x05,0x22,0x74,0xff,0xf0,0x12,0x68,0x7c,0xef,0x70,0x06, ++0x90,0x01,0xc8,0x74,0xfd,0xf0,0x7d,0x02,0x7f,0x03,0x12,0x36,0xe6,0xe5,0x70,0x60, ++0x04,0x7f,0x01,0x11,0xb3,0x12,0x68,0xbd,0x53,0x6e,0xf0,0x43,0x6e,0x02,0x22,0xef, ++0x64,0x01,0x70,0x42,0x7d,0x78,0x7f,0x02,0x12,0x36,0x75,0x7d,0x02,0x7f,0x03,0x12, ++0x36,0x75,0x90,0x01,0x36,0x74,0x03,0xf0,0xfd,0x7f,0x02,0x12,0x36,0xe6,0x7d,0x10, ++0x7f,0x03,0x12,0x36,0x92,0x90,0x01,0x57,0xe4,0xf0,0x90,0x01,0x3c,0x74,0x02,0xf0, ++0x12,0x47,0x23,0xe4,0xff,0x11,0xb3,0x90,0x06,0x04,0xe0,0x54,0x7f,0xf0,0x90,0x06, ++0x0a,0xe0,0x54,0xf8,0xf0,0x22,0x90,0x01,0x36,0x74,0x7b,0xf0,0xa3,0x74,0x02,0xf0, ++0x7d,0x7b,0xff,0x12,0x36,0xe6,0x7d,0x02,0x7f,0x03,0x12,0x36,0xe6,0x7d,0x10,0x7f, ++0x03,0x12,0x36,0x92,0x90,0x06,0x04,0xe0,0x44,0x80,0xf0,0x90,0x06,0x0a,0xe0,0x44, ++0x07,0xf0,0x12,0x44,0xf4,0xe5,0x6d,0x20,0xe0,0x05,0xe4,0x90,0x91,0x29,0xf0,0x22, ++0x8b,0x0e,0x8a,0x0f,0x89,0x10,0xf1,0xf2,0xab,0x0e,0xaa,0x0f,0xa9,0x10,0x12,0x29, ++0xd9,0xf5,0x70,0x14,0x60,0x0e,0x14,0x60,0x1e,0x14,0x60,0x2f,0x24,0x03,0x70,0x40, ++0x7f,0x01,0x80,0x3a,0xab,0x0e,0xaa,0x0f,0xa9,0x10,0x90,0x00,0x02,0x12,0x42,0x20, ++0xfd,0xe4,0xff,0x31,0xe1,0x80,0x27,0xab,0x0e,0xaa,0x0f,0xa9,0x10,0x90,0x00,0x02, ++0x12,0x42,0x20,0xfd,0x7f,0x01,0x31,0xe1,0x1f,0x80,0x13,0xab,0x0e,0xaa,0x0f,0xa9, ++0x10,0x90,0x00,0x02,0x12,0x42,0x20,0xfd,0x7f,0x02,0x31,0xe1,0xe4,0xff,0x11,0xff, ++0x22,0xef,0x24,0xfe,0x60,0x0b,0x04,0x70,0x22,0x90,0x91,0x39,0x74,0x01,0xf0,0x80, ++0x16,0xed,0x70,0x0a,0x90,0x91,0x35,0xe0,0x90,0x91,0x39,0xf0,0x80,0x05,0x90,0x91, ++0x39,0xed,0xf0,0x90,0x91,0x39,0xe0,0x90,0x91,0x27,0xf0,0x22,0x12,0x47,0xe6,0xbf, ++0x01,0x0f,0x90,0x02,0x09,0xe0,0xff,0x7d,0x01,0x11,0x22,0x90,0x04,0x1f,0x74,0x20, ++0xf0,0x22,0xc0,0xe0,0xc0,0xf0,0xc0,0x83,0xc0,0x82,0xc0,0xd0,0x75,0xd0,0x00,0xc0, ++0x00,0xc0,0x01,0xc0,0x02,0xc0,0x03,0xc0,0x04,0xc0,0x05,0xc0,0x06,0xc0,0x07,0x90, ++0x01,0xc4,0x74,0x22,0xf0,0x74,0x4a,0xa3,0xf0,0x90,0x01,0x34,0xe0,0x55,0x28,0xf5, ++0x2c,0x90,0x01,0x36,0xe0,0x55,0x2a,0xf5,0x2e,0xa3,0xe0,0x55,0x2b,0xf5,0x2f,0xe5, ++0x2c,0x30,0xe0,0x5a,0x90,0x01,0x34,0x74,0x01,0xf0,0x85,0xd9,0x54,0xe5,0x70,0x14, ++0x24,0xfd,0x50,0x02,0x80,0x48,0x90,0x91,0x3b,0xe0,0x60,0x3a,0x90,0x01,0x5b,0xe4, ++0xf0,0x90,0x01,0x3c,0x74,0x04,0xf0,0x91,0x89,0xef,0x64,0x01,0x70,0x30,0x90,0x91, ++0x66,0xf0,0x90,0x91,0x2d,0xe0,0x90,0x91,0x67,0xf0,0xe4,0xfb,0xfd,0x7f,0x58,0x7e, ++0x01,0x12,0x44,0x59,0x90,0x01,0x5b,0x74,0x05,0xf0,0x90,0x06,0x92,0x74,0x01,0xf0, ++0x90,0x91,0x37,0xf0,0x80,0x08,0x91,0x89,0xbf,0x01,0x03,0x12,0x44,0xc2,0xe5,0x2c, ++0x30,0xe1,0x21,0x90,0x01,0x34,0x74,0x02,0xf0,0x85,0xd1,0x58,0x85,0xd2,0x59,0x85, ++0xd3,0x5a,0x85,0xd4,0x5b,0x85,0xd5,0x5c,0x85,0xd6,0x5d,0x85,0xd7,0x5e,0x85,0xd9, ++0x5f,0x12,0x64,0x66,0xe5,0x2c,0x30,0xe3,0x10,0x90,0x01,0x34,0x74,0x08,0xf0,0x90, ++0x91,0x56,0xe0,0x30,0xe0,0x03,0x43,0x57,0x04,0xe5,0x2c,0x30,0xe4,0x09,0x90,0x01, ++0x34,0x74,0x10,0xf0,0x43,0x57,0x10,0xe5,0x2c,0x30,0xe5,0x24,0x90,0x01,0xcf,0xe0, ++0x30,0xe5,0x1d,0xe0,0x54,0xdf,0xf0,0x90,0x01,0x34,0x74,0x20,0xf0,0x75,0xa8,0x00, ++0x75,0xe8,0x00,0xd1,0x65,0x90,0x00,0x03,0xe0,0x54,0xfb,0xf0,0x91,0xa0,0x80,0xfe, ++0xe5,0x2c,0x30,0xe6,0x06,0x90,0x01,0x34,0x74,0x40,0xf0,0xe5,0x2e,0x30,0xe0,0x15, ++0x90,0x91,0x50,0x74,0x01,0xf0,0x90,0x01,0x36,0xf0,0x12,0x63,0x2e,0x12,0x70,0xee, ++0x90,0x91,0x50,0xe4,0xf0,0xe5,0x2e,0x30,0xe1,0x3b,0x90,0x01,0x36,0x74,0x02,0xf0, ++0x43,0x57,0x40,0x90,0x01,0x02,0xe0,0x54,0x03,0x64,0x01,0x70,0x28,0x90,0x01,0x37, ++0xe0,0x30,0xe0,0x0a,0x74,0x01,0xf0,0x90,0x91,0x40,0xe4,0xf0,0x80,0x17,0x90,0x91, ++0x40,0xe0,0x04,0xf0,0xe0,0xc3,0x94,0x0a,0x40,0x0b,0xe4,0xf0,0x90,0x04,0x19,0xe0, ++0x30,0xe0,0x02,0x51,0x0c,0xe5,0x2e,0x30,0xe2,0x1a,0x90,0x01,0x36,0x74,0x04,0xf0, ++0x90,0x91,0x3a,0xe4,0xf0,0x90,0x05,0x58,0x74,0x03,0xf0,0x12,0x62,0xb8,0x90,0x91, ++0x3f,0xe0,0x04,0xf0,0xe5,0x2e,0x30,0xe3,0x28,0x90,0x01,0x36,0x74,0x08,0xf0,0xe5, ++0x6d,0x64,0x01,0x70,0x1c,0xe5,0x70,0x60,0x18,0x90,0x01,0x57,0xe4,0xf0,0x90,0x01, ++0x3c,0x74,0x02,0xf0,0x90,0x91,0x66,0xe4,0x12,0x44,0x49,0x90,0x01,0x57,0x74,0x05, ++0xf0,0xe5,0x2e,0x30,0xe4,0x2b,0x90,0x01,0x36,0x74,0x10,0xf0,0xe5,0x6d,0xb4,0x01, ++0x20,0xe5,0x70,0x60,0x1c,0x90,0x01,0x57,0xe4,0xf0,0x90,0x01,0x3c,0x74,0x02,0xf0, ++0x90,0x91,0x3c,0xe4,0xf0,0x53,0x71,0xfd,0xe5,0x71,0x54,0x07,0x70,0x03,0x12,0x44, ++0xc2,0xe5,0x2e,0x30,0xe5,0x1f,0x90,0x01,0x36,0x74,0x20,0xf0,0xe5,0x6d,0xb4,0x01, ++0x14,0xe5,0x70,0x60,0x10,0x90,0x91,0x3b,0xe0,0x64,0x02,0x60,0x05,0x12,0x44,0xc8, ++0x80,0x03,0x12,0x44,0x77,0xe5,0x2e,0x30,0xe6,0x1b,0x90,0x01,0x36,0x74,0x40,0xf0, ++0xe5,0x6d,0xb4,0x01,0x10,0xe5,0x70,0x60,0x0c,0x53,0x71,0xfe,0xe5,0x71,0x54,0x07, ++0x70,0x03,0x12,0x44,0xc2,0xe5,0x2f,0x30,0xe1,0x09,0x90,0x01,0x37,0x74,0x02,0xf0, ++0x12,0x64,0x31,0x74,0x22,0x04,0x90,0x01,0xc4,0xf0,0x74,0x4a,0xa3,0xf0,0xd0,0x07, ++0xd0,0x06,0xd0,0x05,0xd0,0x04,0xd0,0x03,0xd0,0x02,0xd0,0x01,0xd0,0x00,0xd0,0xd0, ++0xd0,0x82,0xd0,0x83,0xd0,0xf0,0xd0,0xe0,0x32,0x90,0x04,0x1b,0xe0,0x54,0x7f,0x64, ++0x7f,0x7f,0x01,0x60,0x02,0x7f,0x00,0x22,0xf4,0xff,0x90,0x00,0x43,0xe0,0x5f,0xf0, ++0xd3,0x10,0xaf,0x01,0xc3,0xc0,0xd0,0x7f,0x10,0xdf,0xfe,0xd0,0xd0,0x92,0xaf,0x22, ++0xd3,0x10,0xaf,0x01,0xc3,0xc0,0xd0,0x90,0x91,0x9b,0xed,0xf0,0x90,0x91,0x9a,0xef, ++0xf0,0xd3,0x94,0x07,0x50,0x63,0xe0,0xff,0x74,0x01,0xa8,0x07,0x08,0x80,0x02,0xc3, ++0x33,0xd8,0xfc,0xf4,0xff,0x90,0x00,0x47,0xe0,0x5f,0xf0,0x91,0xa0,0x90,0x91,0x9a, ++0xe0,0xff,0x74,0x01,0xa8,0x07,0x08,0x80,0x02,0xc3,0x33,0xd8,0xfc,0xff,0x90,0x00, ++0x46,0xe0,0x4f,0xf0,0x91,0xa0,0x90,0x91,0x9b,0xe0,0x60,0x16,0x90,0x91,0x9a,0xe0, ++0xff,0x74,0x01,0xa8,0x07,0x08,0x80,0x02,0xc3,0x33,0xd8,0xfc,0xff,0x90,0x00,0x45, ++0x80,0x66,0x90,0x91,0x9a,0xe0,0xff,0x74,0x01,0xa8,0x07,0x08,0x80,0x02,0xc3,0x33, ++0xd8,0xfc,0xf4,0xff,0x90,0x00,0x45,0x80,0x6b,0x90,0x91,0x9a,0xe0,0x24,0xf8,0xf0, ++0xe0,0xff,0x74,0x01,0xa8,0x07,0x08,0x80,0x02,0xc3,0x33,0xd8,0xfc,0xc4,0x54,0xf0, ++0x91,0x98,0x90,0x91,0x9a,0xe0,0xff,0x74,0x01,0xa8,0x07,0x08,0x80,0x02,0xc3,0x33, ++0xd8,0xfc,0xff,0x90,0x00,0x43,0xe0,0x4f,0xf0,0x91,0xa0,0x90,0x91,0x9b,0xe0,0x60, ++0x1b,0x90,0x91,0x9a,0xe0,0xff,0x74,0x01,0xa8,0x07,0x08,0x80,0x02,0xc3,0x33,0xd8, ++0xfc,0xc4,0x54,0xf0,0xff,0x90,0x00,0x42,0xe0,0x4f,0x80,0x1a,0x90,0x91,0x9a,0xe0, ++0xff,0x74,0x01,0xa8,0x07,0x08,0x80,0x02,0xc3,0x33,0xd8,0xfc,0xc4,0x54,0xf0,0xf4, ++0xff,0x90,0x00,0x42,0xe0,0x5f,0xf0,0x91,0xa0,0xd0,0xd0,0x92,0xaf,0x22,0xf0,0x90, ++0x00,0x45,0xe0,0x54,0xfe,0xfd,0x7f,0x45,0xd3,0x10,0xaf,0x01,0xc3,0xc0,0xd0,0x8f, ++0x82,0x75,0x83,0x00,0xed,0xf0,0x91,0xa0,0xd0,0xd0,0x92,0xaf,0x22,0xef,0x14,0x60, ++0x30,0x14,0x60,0x66,0x24,0x02,0x60,0x02,0xc1,0x64,0x90,0x90,0xf3,0x74,0x02,0xf0, ++0x90,0x00,0x48,0xe0,0x44,0x0c,0xfd,0x7f,0x48,0xb1,0xa8,0x90,0x00,0x47,0xe0,0x44, ++0x08,0xfd,0x7f,0x47,0xb1,0xa8,0x90,0x00,0x45,0xe0,0x44,0x10,0xfd,0x7f,0x45,0x80, ++0x71,0xe4,0x90,0x90,0xf3,0xf0,0x90,0x90,0xef,0x12,0x43,0x09,0x90,0x80,0x85,0x12, ++0x2a,0x7f,0x7f,0x80,0x7e,0x08,0x12,0x2f,0xd9,0x90,0x00,0x45,0xe0,0x44,0xef,0xfd, ++0x7f,0x45,0xb1,0xa8,0x90,0x00,0x45,0xe0,0x54,0xef,0xfd,0x7f,0x45,0xb1,0xa8,0x90, ++0x00,0x46,0xe0,0x44,0x10,0xfd,0x7f,0x46,0x80,0x38,0x90,0x90,0xf3,0x74,0x01,0xf0, ++0x90,0x90,0xf9,0x12,0x43,0x09,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0x80,0x7e,0x08, ++0x12,0x2f,0xd9,0x90,0x00,0x45,0xe0,0x44,0x20,0xfd,0x7f,0x45,0xb1,0xa8,0x90,0x00, ++0x45,0xe0,0x44,0x10,0xfd,0x7f,0x45,0xb1,0xa8,0x90,0x00,0x46,0xe0,0x44,0x10,0xfd, ++0x7f,0x46,0xb1,0xa8,0x22,0x90,0x01,0x30,0xe4,0xf0,0xa3,0xf0,0xa3,0xf0,0xa3,0xf0, ++0x90,0x01,0x38,0xf0,0xa3,0xf0,0xa3,0xf0,0xa3,0xf0,0xfd,0x7f,0x50,0xb1,0xa8,0xe4, ++0xfd,0x7f,0x51,0xb1,0xa8,0xe4,0xfd,0x7f,0x52,0xb1,0xa8,0xe4,0xfd,0x7f,0x53,0xa1, ++0xa8,0x8b,0x0e,0x8a,0x0f,0x89,0x10,0x90,0x00,0x02,0x12,0x42,0x20,0x90,0x90,0xf6, ++0xf0,0xe0,0x30,0xe0,0x4b,0x90,0x90,0xed,0x74,0x01,0xf0,0x7f,0x80,0x7e,0x08,0x12, ++0x27,0xde,0x90,0x90,0xef,0x12,0x2a,0x7f,0xab,0x0e,0xaa,0x0f,0xa9,0x10,0x90,0x00, ++0x01,0x12,0x42,0x20,0xff,0xe4,0xfc,0xfd,0xfe,0x78,0x1a,0x12,0x2a,0x6c,0xa8,0x04, ++0xa9,0x05,0xaa,0x06,0xab,0x07,0x90,0x90,0xef,0x12,0x43,0x09,0xec,0x54,0x03,0xfc, ++0x12,0x42,0xfc,0x90,0x90,0xf9,0x12,0x2a,0x7f,0x90,0x05,0x22,0xe4,0xf0,0x80,0x2d, ++0xe4,0x90,0x90,0xed,0xf0,0x7f,0x80,0x7e,0x08,0x12,0x27,0xde,0xec,0x54,0x03,0xfc, ++0xec,0x44,0xc0,0xfc,0x90,0x90,0xef,0x12,0x2a,0x7f,0x90,0x90,0xef,0x12,0x43,0x09, ++0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0x80,0x7e,0x08,0x12,0x2f,0xd9,0x90,0x90,0xf6, ++0xe0,0x30,0xe1,0x19,0x7d,0x0c,0x7f,0x47,0xb1,0xa8,0x90,0x00,0x48,0xe0,0x44,0x0c, ++0xfd,0x7f,0x48,0xb1,0xa8,0x90,0x00,0x46,0xe0,0x44,0x10,0x80,0x1c,0x90,0x00,0x47, ++0xe0,0x54,0xf3,0xfd,0x7f,0x47,0xb1,0xa8,0x90,0x00,0x48,0xe0,0x54,0xf3,0xfd,0x7f, ++0x48,0xb1,0xa8,0x90,0x00,0x46,0xe0,0x54,0xef,0xfd,0x7f,0x46,0xb1,0xa8,0xe4,0x90, ++0x90,0xf3,0xf0,0x22,0x90,0x01,0x3c,0x74,0xff,0xf0,0xa3,0xf0,0xa3,0xf0,0x90,0x01, ++0x34,0xf0,0xa3,0xf0,0xa3,0xf0,0xa3,0xf0,0xfd,0x7f,0x54,0xb1,0xa8,0x7d,0xff,0x7f, ++0x55,0xb1,0xa8,0x7d,0xff,0x7f,0x56,0xb1,0xa8,0x7d,0xff,0x7f,0x57,0xa1,0xa8,0xe5, ++0x72,0x64,0x01,0x70,0x3e,0x12,0x54,0x41,0xbf,0x01,0x05,0x7f,0x01,0x12,0x56,0xe7, ++0x90,0x00,0x46,0xe0,0x44,0x04,0xfd,0x7f,0x46,0xb1,0xa8,0x90,0x00,0x44,0xe0,0x54, ++0xfb,0xfd,0x7f,0x44,0xb1,0xa8,0x90,0x00,0x46,0xe0,0x54,0xfb,0xfd,0x7f,0x46,0xb1, ++0xa8,0x7f,0x02,0x12,0x6f,0x09,0x8f,0x76,0x90,0x01,0xc9,0xe5,0x76,0xf0,0xb4,0x01, ++0x02,0xf1,0xd4,0x22,0x90,0x00,0x49,0xe0,0x90,0x91,0x9f,0xf0,0xe0,0x54,0x0f,0xf0, ++0x44,0xf0,0xfd,0x7f,0x49,0xb1,0xa8,0x90,0x91,0x9f,0xe0,0x44,0xb0,0xfd,0x7f,0x49, ++0xa1,0xa8,0xe4,0x90,0x91,0x3c,0xf0,0x90,0x91,0x28,0xf0,0xf5,0x71,0x22,0x75,0x28, ++0x33,0xe4,0xf5,0x29,0x75,0x2a,0x07,0xf5,0x2b,0x90,0x01,0x30,0xe5,0x28,0xf0,0xa3, ++0xe5,0x29,0xf0,0xa3,0xe5,0x2a,0xf0,0xa3,0xe5,0x2b,0xf0,0x22,0x75,0x30,0x1f,0x75, ++0x31,0x01,0xe4,0xf5,0x32,0x90,0x01,0x38,0xe5,0x30,0xf0,0xa3,0xe5,0x31,0xf0,0xa3, ++0xe5,0x32,0xf0,0x22,0xe4,0x90,0x91,0x0e,0xf0,0xa3,0xf0,0x75,0x8e,0x02,0xf1,0x02, ++0xd1,0xb4,0x90,0x91,0x4f,0xef,0xf0,0xd1,0xdb,0x90,0x91,0x51,0xef,0xf0,0xf1,0x3d, ++0x90,0x91,0x3d,0xee,0xf0,0xa3,0xef,0xf0,0xe4,0xf5,0x57,0xd1,0xd2,0x12,0x60,0x37, ++0x12,0x32,0x3d,0xd1,0xc1,0x12,0x4f,0xfe,0xf1,0x13,0xd1,0xcb,0x11,0x1c,0x12,0x44, ++0xff,0x31,0x23,0x11,0xdf,0x12,0x6f,0xaa,0x90,0x91,0x10,0xe5,0xd9,0xf0,0x12,0x4f, ++0x64,0xc2,0xaf,0x90,0x00,0x80,0xe0,0x44,0x40,0xf0,0x12,0x4c,0xa0,0x75,0xe8,0x03, ++0x43,0xa8,0x85,0xd2,0xaf,0x90,0x91,0x0e,0xe0,0x64,0x01,0xf0,0x24,0x34,0x90,0x01, ++0xc4,0xf0,0x74,0x50,0xa3,0xf0,0xe5,0x57,0x30,0xe2,0x10,0x12,0x5e,0x63,0xbf,0x01, ++0x0a,0xc2,0xaf,0x53,0x57,0xfb,0xd2,0xaf,0x12,0x71,0x8a,0xe5,0x57,0x30,0xe4,0x0a, ++0xc2,0xaf,0x53,0x57,0xef,0xd2,0xaf,0x12,0x5e,0xa0,0x90,0x90,0xf7,0xe0,0x70,0x03, ++0x12,0x70,0x08,0x11,0xf7,0x90,0x91,0x3f,0xe0,0x90,0x01,0xba,0xf0,0x80,0xb6,0x90, ++0x91,0x53,0xe0,0x54,0xfe,0xf0,0xe4,0x90,0x91,0x55,0xf0,0x90,0x91,0x53,0xe0,0x54, ++0x7f,0xf0,0xa3,0x74,0x0a,0xf0,0x22,0x90,0x06,0x34,0xe0,0x60,0x25,0x14,0x70,0x1b, ++0x7b,0x01,0x7a,0x06,0x79,0x35,0x7f,0xf9,0x7e,0x01,0x12,0x68,0x1a,0xbf,0x01,0x09, ++0x90,0x06,0x35,0xe0,0x54,0x0f,0xf0,0x80,0x04,0x80,0x00,0xc1,0xf4,0xe4,0x90,0x06, ++0x34,0xf0,0x22,0x90,0x91,0x56,0xe0,0x54,0xfe,0xf0,0xe0,0x54,0x7f,0xf0,0x90,0x01, ++0x17,0xe0,0xfe,0x90,0x01,0x16,0xe0,0x7c,0x00,0x24,0x00,0xff,0xec,0x3e,0x90,0x91, ++0x5c,0xf0,0xa3,0xef,0xf0,0x90,0x01,0x04,0xe0,0x54,0x0f,0x90,0x91,0x1c,0xf0,0xe0, ++0xff,0x74,0x40,0x7e,0x00,0xa8,0x07,0x08,0x80,0x05,0xc3,0x33,0xce,0x33,0xce,0xd8, ++0xf9,0x90,0x91,0x5b,0xf0,0xee,0x90,0x91,0x5a,0xf0,0x90,0x91,0x5e,0xe0,0x54,0xfe, ++0xf0,0xe0,0x54,0xfd,0xf0,0xe0,0x54,0xfb,0xf0,0xe0,0x54,0xf7,0xf0,0xe0,0x54,0xef, ++0xf0,0xe0,0x54,0xdf,0xf0,0xe0,0x54,0xbf,0xf0,0xe0,0x54,0x7f,0xf0,0xe4,0xa3,0xf0, ++0xa3,0xf0,0xa3,0xe0,0x54,0xfe,0xf0,0xe0,0x54,0xfd,0xf0,0xe0,0x54,0xf7,0xf0,0x22, ++0xd3,0x10,0xaf,0x01,0xc3,0xc0,0xd0,0x12,0x29,0xd9,0x54,0x01,0xff,0x90,0x91,0x56, ++0xe0,0x54,0xfe,0x4f,0xf0,0x90,0x00,0x01,0x12,0x42,0x20,0x90,0x91,0x57,0xf0,0x90, ++0x00,0x02,0x12,0x42,0x20,0x90,0x91,0x58,0xf0,0x90,0x91,0x56,0xe0,0x30,0xe0,0x1a, ++0x90,0x06,0x09,0xe0,0x54,0xfe,0xf0,0x90,0x02,0x86,0xe0,0x44,0x04,0xf0,0x43,0x57, ++0x04,0x7d,0x08,0xe4,0xff,0x12,0x36,0xe6,0x80,0x12,0x7d,0x08,0xe4,0xff,0x12,0x36, ++0x75,0x90,0x02,0x86,0xe0,0x54,0xfb,0xf0,0x51,0x01,0x31,0x23,0xd0,0xd0,0x92,0xaf, ++0x22,0x90,0x06,0x90,0xe4,0xf0,0x21,0x6a,0x90,0x91,0x19,0x12,0x43,0x41,0xef,0x12, ++0x43,0x4a,0x52,0x40,0x01,0x52,0x49,0x02,0x52,0x6a,0x03,0x52,0x73,0x09,0x52,0x7b, ++0x0c,0x52,0x84,0x0d,0x52,0x8c,0x0e,0x52,0x9d,0x1a,0x52,0xa5,0x2c,0x52,0x51,0x2d, ++0x52,0x5a,0x2e,0x52,0xad,0x30,0x52,0x62,0x3b,0x52,0x95,0x3c,0x00,0x00,0x52,0xb5, ++0x90,0x91,0x19,0x12,0x43,0x21,0x02,0x64,0xde,0x90,0x91,0x19,0x12,0x43,0x21,0xc1, ++0xc5,0x90,0x91,0x19,0x12,0x43,0x21,0x02,0x65,0xf9,0x90,0x91,0x19,0x12,0x43,0x21, ++0xe1,0xa8,0x90,0x91,0x19,0x12,0x43,0x21,0xe1,0x28,0x90,0x91,0x19,0x12,0x43,0x21, ++0x02,0x66,0x41,0x90,0x91,0x19,0x12,0x43,0x21,0x80,0x42,0x90,0x91,0x19,0x12,0x43, ++0x21,0x02,0x5d,0x16,0x90,0x91,0x19,0x12,0x43,0x21,0xe1,0x75,0x90,0x91,0x19,0x12, ++0x43,0x21,0x02,0x4e,0x91,0x90,0x91,0x19,0x12,0x43,0x21,0x21,0xa0,0x90,0x91,0x19, ++0x12,0x43,0x21,0xa1,0x7f,0x90,0x91,0x19,0x12,0x43,0x21,0x81,0x5e,0x90,0x91,0x19, ++0x12,0x43,0x21,0xe1,0x55,0x90,0x01,0xc6,0xe0,0x44,0x01,0xf0,0x22,0xd3,0x10,0xaf, ++0x01,0xc3,0xc0,0xd0,0x90,0x91,0x1c,0x12,0x43,0x41,0x90,0x91,0x1c,0x12,0x43,0x21, ++0x90,0x00,0x01,0x12,0x42,0x97,0xfa,0xe5,0xf0,0x24,0x00,0xff,0xe4,0x3a,0xfe,0x90, ++0x91,0x1c,0x12,0x43,0x21,0x90,0x00,0x01,0xee,0x8f,0xf0,0x12,0x42,0xcf,0x12,0x29, ++0xd9,0xff,0x60,0x2c,0xb5,0x72,0x16,0x90,0x91,0x1c,0x12,0x43,0x21,0x90,0x00,0x01, ++0x12,0x42,0x97,0x65,0x74,0x70,0x04,0xe5,0x73,0x65,0xf0,0x60,0x23,0x90,0x91,0x1c, ++0x12,0x43,0x21,0x90,0x00,0x01,0x12,0x42,0x97,0xff,0xae,0xf0,0x71,0x35,0x80,0x10, ++0x90,0x91,0x1c,0x12,0x43,0x21,0x12,0x29,0xd9,0x65,0x72,0x60,0x03,0x12,0x44,0xe8, ++0xd0,0xd0,0x92,0xaf,0x22,0x90,0x91,0x1f,0xee,0xf0,0xa3,0xef,0xf0,0x75,0x72,0x01, ++0x8e,0x73,0xf5,0x74,0xe4,0xfd,0x7f,0x0b,0x71,0x77,0xe4,0xfd,0x7f,0x02,0x71,0x77, ++0x91,0x41,0xe4,0xff,0xd1,0xe7,0xe4,0xf5,0x76,0x90,0x01,0xc9,0xe5,0x76,0xf0,0x90, ++0x91,0x1f,0xe0,0xfc,0xa3,0xe0,0xfd,0xec,0xfb,0x8d,0x44,0xe4,0xf5,0x45,0x7d,0x01, ++0x7f,0x60,0x7e,0x01,0x02,0x35,0xab,0xd3,0x10,0xaf,0x01,0xc3,0xc0,0xd0,0x90,0x91, ++0x22,0xed,0xf0,0x90,0x91,0x21,0xef,0xf0,0xd3,0x94,0x07,0x50,0x4f,0xa3,0xe0,0x70, ++0x1a,0x90,0x91,0x21,0xe0,0xff,0x74,0x01,0xa8,0x07,0x08,0x80,0x02,0xc3,0x33,0xd8, ++0xfc,0xf4,0xff,0x90,0x00,0x47,0xe0,0x5f,0xf0,0x80,0x17,0x90,0x91,0x21,0xe0,0xff, ++0x74,0x01,0xa8,0x07,0x08,0x80,0x02,0xc3,0x33,0xd8,0xfc,0xff,0x90,0x00,0x47,0xe0, ++0x4f,0xf0,0x12,0x4c,0xa0,0x90,0x91,0x21,0xe0,0xff,0x74,0x01,0xa8,0x07,0x08,0x80, ++0x02,0xc3,0x33,0xd8,0xfc,0xf4,0xff,0x90,0x00,0x46,0x80,0x5a,0x90,0x91,0x21,0xe0, ++0x24,0xf8,0xf0,0xa3,0xe0,0x70,0x1d,0x90,0x91,0x21,0xe0,0xff,0x74,0x01,0xa8,0x07, ++0x08,0x80,0x02,0xc3,0x33,0xd8,0xfc,0xc4,0x54,0xf0,0xf4,0xff,0x90,0x00,0x43,0xe0, ++0x5f,0xf0,0x80,0x1a,0x90,0x91,0x21,0xe0,0xff,0x74,0x01,0xa8,0x07,0x08,0x80,0x02, ++0xc3,0x33,0xd8,0xfc,0xc4,0x54,0xf0,0xff,0x90,0x00,0x43,0xe0,0x4f,0xf0,0x12,0x4c, ++0xa0,0x90,0x91,0x21,0xe0,0xff,0x74,0x01,0xa8,0x07,0x08,0x80,0x02,0xc3,0x33,0xd8, ++0xfc,0xf4,0xff,0x90,0x00,0x43,0xe0,0x5f,0xf0,0x12,0x4c,0xa0,0xd0,0xd0,0x92,0xaf, ++0x22,0x7f,0x0b,0x12,0x6f,0x09,0xef,0x65,0x75,0x60,0x10,0xe5,0x75,0xb4,0x01,0x05, ++0xe4,0xf5,0x75,0x80,0x03,0x75,0x75,0x01,0x7f,0x01,0x22,0x7f,0x00,0x22,0xd3,0x10, ++0xaf,0x01,0xc3,0xc0,0xd0,0xe4,0xf5,0x10,0x75,0x11,0x04,0xf5,0x12,0xf5,0x14,0xf5, ++0x15,0x90,0x02,0x09,0xe0,0xff,0x12,0x29,0xd9,0xfe,0xef,0x2e,0xf5,0x13,0x30,0xe0, ++0x08,0x75,0x0e,0x00,0x75,0x0f,0x80,0x80,0x05,0xe4,0xf5,0x0e,0xf5,0x0f,0xe5,0x13, ++0xc3,0x13,0x90,0xfd,0x10,0xf0,0x74,0x20,0x25,0x10,0xf5,0x10,0xad,0x0f,0xe5,0x10, ++0x2d,0xff,0x24,0x01,0xf5,0x82,0xe4,0x34,0xfc,0xf5,0x83,0xe0,0x90,0x91,0x47,0xf0, ++0x74,0x02,0x2f,0xf5,0x82,0xe4,0x34,0xfc,0xf5,0x83,0xe0,0xfe,0xe5,0x10,0x2d,0x24, ++0x03,0xf5,0x82,0xe4,0x34,0xfc,0xf5,0x83,0xe0,0x24,0x00,0xff,0xe4,0x3e,0x90,0x91, ++0x48,0xf0,0xa3,0xef,0xf0,0x7f,0x04,0xe5,0x10,0x25,0x0f,0x2f,0x24,0x00,0xf5,0x82, ++0xe4,0x34,0xfc,0xf5,0x83,0xe0,0xfe,0x74,0x46,0x2f,0xf5,0x82,0xe4,0x34,0x91,0xf5, ++0x83,0xee,0xf0,0x0f,0xbf,0x08,0xe0,0x12,0x66,0x89,0xef,0x70,0x3f,0x90,0x01,0xc3, ++0xe0,0x60,0x25,0xc3,0xe5,0x15,0x94,0xe8,0xe5,0x14,0x94,0x03,0x40,0x09,0x90,0x01, ++0xc6,0xe0,0x44,0x10,0xf0,0x80,0x63,0x05,0x15,0xe5,0x15,0x70,0x02,0x05,0x14,0x7f, ++0x0a,0x7e,0x00,0x12,0x37,0x54,0x80,0xd5,0x90,0x01,0xc6,0xe0,0x90,0x01,0xc3,0x30, ++0xe2,0x05,0x74,0xfe,0xf0,0x80,0x43,0x74,0xff,0xf0,0x80,0x3e,0xe5,0x10,0xb4,0x78, ++0x23,0xe4,0xf5,0x10,0x05,0x13,0xe5,0x0f,0x64,0x80,0x45,0x0e,0x70,0x06,0xf5,0x0e, ++0xf5,0x0f,0x80,0x06,0x75,0x0e,0x00,0x75,0x0f,0x80,0xe5,0x13,0xc3,0x13,0x90,0xfd, ++0x10,0xf0,0x80,0x06,0x74,0x08,0x25,0x10,0xf5,0x10,0xe5,0x12,0x15,0x12,0x70,0x02, ++0x15,0x11,0xe5,0x12,0x45,0x11,0x60,0x02,0x81,0x9c,0xd0,0xd0,0x92,0xaf,0x22,0x90, ++0x91,0x1c,0x12,0x43,0x41,0x12,0x29,0xd9,0xff,0x54,0x01,0xfe,0x90,0x91,0x5e,0xe0, ++0x54,0xfe,0x4e,0xf0,0xef,0x54,0x04,0xff,0xe0,0x54,0xfb,0x4f,0xf0,0x12,0x29,0xd9, ++0xff,0x54,0x02,0xfe,0x90,0x91,0x5e,0xe0,0x54,0xfd,0x4e,0xf0,0xef,0x54,0x08,0xff, ++0xe0,0x54,0xf7,0x4f,0xf0,0x12,0x29,0xd9,0xff,0x54,0x10,0xfe,0x90,0x91,0x5e,0xe0, ++0x54,0xef,0x4e,0xf0,0xef,0x54,0x20,0xff,0xe0,0x54,0xdf,0x4f,0xf0,0x12,0x29,0xd9, ++0xff,0x54,0x40,0xfe,0x90,0x91,0x5e,0xe0,0x54,0xbf,0x4e,0xf0,0xef,0x54,0x80,0xff, ++0xe0,0x54,0x7f,0x4f,0xf0,0x90,0x00,0x02,0x12,0x42,0x20,0x90,0x91,0x60,0xf0,0x90, ++0x00,0x01,0x12,0x42,0x20,0x90,0x91,0x5f,0xf0,0x90,0x00,0x03,0x12,0x42,0x20,0xff, ++0x54,0x01,0xfe,0x90,0x91,0x61,0xe0,0x54,0xfe,0x4e,0xf0,0xef,0x54,0x02,0xff,0xe0, ++0x54,0xfd,0x4f,0xf0,0x90,0x00,0x03,0x12,0x42,0x20,0x54,0x04,0xff,0x90,0x91,0x61, ++0xe0,0x54,0xfb,0x4f,0xf0,0x90,0x91,0x5e,0xe0,0x54,0x01,0x90,0x01,0xb8,0xf0,0x90, ++0x91,0x5e,0xe0,0xff,0xc4,0x13,0x54,0x01,0x90,0x01,0xb9,0xf0,0x90,0x91,0x61,0xe0, ++0x54,0x01,0x90,0x01,0xba,0xf0,0xa3,0x74,0xff,0xf0,0x12,0x29,0xd9,0x20,0xe0,0x02, ++0x41,0x01,0xe4,0xfd,0x7f,0x81,0x12,0x4d,0xa8,0x90,0x91,0x1c,0x12,0x43,0x21,0x12, ++0x29,0xd9,0xff,0xc3,0x13,0x30,0xe0,0x07,0x90,0x06,0x90,0xe0,0x44,0x02,0xf0,0xef, ++0x13,0x13,0x54,0x3f,0x30,0xe0,0x07,0x90,0x06,0x90,0xe0,0x44,0x04,0xf0,0x12,0x29, ++0xd9,0x13,0x13,0x13,0x54,0x1f,0x30,0xe0,0x07,0x90,0x06,0x90,0xe0,0x44,0x08,0xf0, ++0x90,0x91,0x61,0xe0,0x30,0xe0,0x1c,0x90,0x91,0x5e,0xe0,0xc4,0x13,0x54,0x07,0x30, ++0xe0,0x07,0xa3,0xe0,0xff,0xe4,0xfd,0x80,0x07,0x90,0x91,0x5f,0xe0,0xff,0x7d,0x01, ++0x12,0x4c,0xb0,0x22,0x90,0x00,0x02,0xe0,0x54,0xe0,0x7f,0x01,0x60,0x02,0x7f,0x00, ++0x22,0xe4,0xf5,0x75,0x22,0x12,0x29,0xd9,0xf5,0x6d,0x22,0x90,0x01,0x64,0x74,0xa0, ++0xf0,0x22,0x90,0x91,0x51,0xe0,0x90,0x90,0xe8,0xf0,0x22,0x90,0x00,0xf3,0xe0,0x7f, ++0x00,0x30,0xe3,0x02,0x7f,0x01,0x22,0x90,0x01,0xca,0xe5,0x75,0xf0,0xef,0x60,0x03, ++0x12,0x4f,0xd4,0x22,0x90,0x06,0x34,0x74,0xff,0xf0,0xe4,0xa3,0xf0,0xa3,0xf0,0xa3, ++0xf0,0x22,0xe4,0x90,0x91,0x4e,0xf0,0x90,0x00,0x80,0xe0,0x44,0x80,0xfd,0x7f,0x80, ++0x02,0x4d,0xa8,0x90,0x00,0xf3,0xe0,0x30,0xe2,0x0d,0x90,0x05,0x41,0x74,0x10,0xf0, ++0x90,0x05,0x5a,0xf0,0xa3,0xe4,0xf0,0x22,0x12,0x29,0xd9,0x60,0x02,0x80,0x01,0xe4, ++0x90,0x91,0x31,0xf0,0x90,0x91,0x31,0xe0,0x90,0x01,0xe7,0xf0,0x22,0x90,0x91,0x51, ++0xe0,0xb4,0x01,0x0c,0x90,0x00,0xf2,0xe0,0x30,0xe7,0x05,0x7e,0xfd,0x7f,0x33,0x22, ++0x7e,0xfd,0x7f,0x2f,0x22,0x12,0x29,0xd9,0xff,0x54,0x01,0xfe,0x90,0x91,0x53,0xe0, ++0x54,0xfe,0x4e,0xf0,0xef,0xc3,0x13,0x30,0xe0,0x0a,0x90,0x00,0x01,0x12,0x42,0x20, ++0x90,0x91,0x54,0xf0,0x22,0x90,0x00,0x02,0x12,0x42,0x20,0x90,0x90,0xf7,0xf0,0xe0, ++0x60,0x04,0xe0,0xf4,0x70,0x21,0xa2,0xaf,0xe4,0x33,0xf5,0x0e,0xc2,0xaf,0x90,0x00, ++0x47,0xe0,0x54,0xfb,0xfd,0x7f,0x47,0x12,0x4d,0xa8,0x7d,0x40,0x7f,0x01,0x12,0x36, ++0xaf,0xe5,0x0e,0x24,0xff,0x92,0xaf,0x22,0x12,0x29,0xd9,0x30,0xe0,0x19,0xc3,0x13, ++0x54,0x7f,0x90,0x91,0x34,0xf0,0x90,0x00,0x01,0x12,0x42,0x20,0xff,0x90,0x91,0x32, ++0xe4,0xf0,0xa3,0xef,0xf0,0x80,0x0f,0x90,0x91,0x34,0x74,0x07,0xf0,0x90,0x91,0x32, ++0xe4,0xf0,0xa3,0x74,0x03,0xf0,0x90,0x91,0x32,0xe0,0xa3,0xe0,0x90,0x05,0x58,0xf0, ++0x22,0xc0,0xe0,0xc0,0xf0,0xc0,0x83,0xc0,0x82,0xc0,0xd0,0x75,0xd0,0x00,0xc0,0x00, ++0xc0,0x01,0xc0,0x02,0xc0,0x03,0xc0,0x04,0xc0,0x05,0xc0,0x06,0xc0,0x07,0x90,0x01, ++0xc4,0x74,0xe1,0xf0,0x74,0x57,0xa3,0xf0,0x53,0x91,0xef,0x90,0x00,0x51,0xe0,0xff, ++0x90,0x00,0x55,0xe0,0x5f,0xf5,0x3d,0x90,0x00,0x52,0xe0,0xff,0x90,0x00,0x56,0xe0, ++0x5f,0xf5,0x3e,0xe5,0x3d,0x30,0xe4,0x06,0x90,0x00,0x55,0x74,0x10,0xf0,0xe5,0x3d, ++0x30,0xe5,0x06,0x90,0x00,0x55,0x74,0x20,0xf0,0xe5,0x3d,0x30,0xe6,0x1b,0x90,0x00, ++0x55,0x74,0x40,0xf0,0x90,0x90,0xf6,0xe0,0x54,0x03,0xff,0xbf,0x03,0x0b,0x90,0x90, ++0xf3,0xe0,0x60,0x05,0x7f,0x01,0x12,0x4d,0xbd,0xe5,0x3d,0x30,0xe7,0x15,0x90,0x00, ++0x55,0x74,0x80,0xf0,0x90,0x90,0xf6,0xe0,0x54,0x03,0xff,0xbf,0x03,0x05,0x7f,0x02, ++0x12,0x4d,0xbd,0xe5,0x3e,0x30,0xe0,0x06,0x90,0x00,0x56,0x74,0x01,0xf0,0xe5,0x3e, ++0x30,0xe1,0x06,0x90,0x00,0x56,0x74,0x02,0xf0,0xe5,0x3e,0x30,0xe2,0x06,0x90,0x00, ++0x56,0x74,0x04,0xf0,0xe5,0x3e,0x30,0xe3,0x06,0x90,0x00,0x56,0x74,0x08,0xf0,0x90, ++0x01,0xc4,0x74,0xe1,0xf0,0x74,0x57,0xa3,0xf0,0xd0,0x07,0xd0,0x06,0xd0,0x05,0xd0, ++0x04,0xd0,0x03,0xd0,0x02,0xd0,0x01,0xd0,0x00,0xd0,0xd0,0xd0,0x82,0xd0,0x83,0xd0, ++0xf0,0xd0,0xe0,0x32,0xc0,0xe0,0xc0,0xf0,0xc0,0x83,0xc0,0x82,0xc0,0xd0,0x75,0xd0, ++0x00,0xc0,0x00,0xc0,0x01,0xc0,0x02,0xc0,0x03,0xc0,0x04,0xc0,0x05,0xc0,0x06,0xc0, ++0x07,0x75,0x0d,0x00,0x90,0x01,0xc4,0x74,0xc4,0xf0,0x74,0x58,0xa3,0xf0,0x53,0x91, ++0xdf,0x90,0x01,0x3c,0xe0,0x55,0x30,0xf5,0x34,0xa3,0xe0,0x55,0x31,0xf5,0x35,0xa3, ++0xe0,0x55,0x32,0xf5,0x36,0xa3,0xe0,0x55,0x33,0xf5,0x37,0xe5,0x34,0x30,0xe0,0x06, ++0x90,0x01,0x3c,0x74,0x01,0xf0,0xe5,0x34,0x30,0xe1,0x08,0x90,0x01,0x3c,0x74,0x02, ++0xf0,0x71,0x89,0xe5,0x34,0x30,0xe2,0x3a,0x90,0x01,0x3c,0x74,0x04,0xf0,0x90,0x06, ++0x92,0xe0,0x30,0xe0,0x25,0x90,0x91,0x66,0xe4,0xf0,0x90,0x91,0x2d,0xe0,0x90,0x91, ++0x67,0xf0,0xe4,0xfb,0xfd,0x7f,0x58,0x7e,0x01,0x12,0x44,0x59,0x90,0x01,0x5b,0x74, ++0x05,0xf0,0x90,0x06,0x92,0x74,0x01,0xf0,0x80,0x08,0x90,0x91,0x37,0xe4,0xf0,0x12, ++0x44,0xc2,0xe5,0x34,0x30,0xe3,0x3a,0x90,0x01,0x3c,0x74,0x08,0xf0,0x90,0x06,0x92, ++0xe0,0x30,0xe1,0x25,0x90,0x91,0x66,0xe4,0xf0,0x90,0x91,0x2d,0xe0,0x90,0x91,0x67, ++0xf0,0xe4,0xfb,0xfd,0x7f,0x5c,0x7e,0x01,0x12,0x44,0x59,0x90,0x01,0x5f,0x74,0x05, ++0xf0,0x90,0x06,0x92,0x74,0x02,0xf0,0x80,0x08,0x90,0x91,0x36,0xe4,0xf0,0x12,0x44, ++0xc2,0xe5,0x34,0x30,0xe4,0x09,0x90,0x01,0x3c,0x74,0x10,0xf0,0x12,0x4f,0x8f,0xe5, ++0x34,0x30,0xe5,0x08,0x90,0x01,0x3c,0x74,0x20,0xf0,0x51,0x62,0xe5,0x35,0x30,0xe0, ++0x5a,0x90,0x01,0x3d,0x74,0x01,0xf0,0x90,0x01,0x2f,0xe0,0x44,0x7f,0xf0,0x90,0x00, ++0x83,0xe0,0x54,0x0f,0xf5,0x0d,0xb4,0x01,0x02,0x80,0x1c,0xe5,0x0d,0xb4,0x02,0x05, ++0x90,0x00,0x83,0x80,0x12,0xe5,0x0d,0xb4,0x04,0x05,0x90,0x00,0x83,0x80,0x08,0xe5, ++0x0d,0xb4,0x0c,0x08,0x90,0x00,0x83,0xe0,0xf5,0x6f,0x80,0x06,0x90,0x01,0xbe,0xe0, ++0x04,0xf0,0x90,0x01,0xbb,0xe5,0x6f,0xf0,0xe5,0x6f,0x30,0xe0,0x03,0xa3,0x80,0x03, ++0x90,0x01,0xbd,0xe0,0x04,0xf0,0x71,0x6a,0x12,0x44,0xc2,0xe5,0x35,0x30,0xe2,0x06, ++0x90,0x01,0x3d,0x74,0x04,0xf0,0xe5,0x36,0x30,0xe0,0x06,0x90,0x01,0x3e,0x74,0x01, ++0xf0,0xe5,0x36,0x30,0xe1,0x06,0x90,0x01,0x3e,0x74,0x02,0xf0,0x74,0xc4,0x04,0x90, ++0x01,0xc4,0xf0,0x74,0x58,0xa3,0xf0,0xd0,0x07,0xd0,0x06,0xd0,0x05,0xd0,0x04,0xd0, ++0x03,0xd0,0x02,0xd0,0x01,0xd0,0x00,0xd0,0xd0,0xd0,0x82,0xd0,0x83,0xd0,0xf0,0xd0, ++0xe0,0x32,0x90,0x90,0xf5,0xe0,0x64,0x01,0x60,0x02,0x61,0x17,0x90,0x00,0x46,0xe0, ++0x44,0x01,0xfd,0x7f,0x46,0x12,0x4d,0xa8,0x90,0x91,0x07,0xe0,0x70,0x32,0x90,0x90, ++0xed,0xe0,0x60,0x15,0x90,0x90,0xf9,0x12,0x43,0x09,0x90,0x80,0x85,0x12,0x2a,0x7f, ++0x7f,0x80,0x7e,0x08,0x12,0x2f,0xd9,0x80,0x06,0x90,0x05,0x22,0x74,0x7f,0xf0,0x90, ++0x90,0xf4,0xe0,0xff,0x71,0x18,0x90,0x91,0x07,0x74,0x01,0x12,0x4d,0x9e,0x80,0x40, ++0x90,0x91,0x07,0xe0,0x64,0x01,0x70,0x38,0x90,0x90,0xf8,0xe0,0xff,0x71,0x18,0xe4, ++0x90,0x91,0x07,0xf0,0x90,0x00,0x45,0xe0,0x44,0x01,0xfd,0x7f,0x45,0x12,0x4d,0xa8, ++0x90,0x90,0xed,0xe0,0x60,0x15,0x90,0x90,0xef,0x12,0x43,0x09,0x90,0x80,0x85,0x12, ++0x2a,0x7f,0x7f,0x80,0x7e,0x08,0x12,0x2f,0xd9,0x80,0x05,0x90,0x05,0x22,0xe4,0xf0, ++0x90,0x05,0x87,0xe0,0x64,0x80,0xf0,0x90,0x91,0x03,0xe0,0x90,0x05,0x84,0xf0,0x90, ++0x91,0x04,0xe0,0x90,0x05,0x85,0xf0,0x90,0x91,0x05,0xe0,0x90,0x05,0x86,0xf0,0x90, ++0x91,0x06,0xe0,0x90,0x05,0x87,0xf0,0x22,0x90,0x05,0x60,0xe0,0x90,0x91,0x03,0xf0, ++0x90,0x05,0x61,0xe0,0x90,0x91,0x04,0xf0,0x90,0x05,0x62,0xe0,0x90,0x91,0x05,0xf0, ++0x90,0x05,0x63,0xe0,0x90,0x91,0x06,0xf0,0xc3,0x74,0xff,0x9f,0xfe,0x90,0x91,0x04, ++0xe0,0xd3,0x9e,0x40,0x1e,0xe0,0x2f,0xf0,0xa3,0xe0,0xb4,0xff,0x0f,0xe4,0xf0,0xa3, ++0xe0,0xb4,0xff,0x03,0xe4,0xf0,0x22,0x90,0x91,0x06,0x80,0x03,0x90,0x91,0x05,0xe0, ++0x04,0xf0,0x22,0x90,0x91,0x04,0xe0,0x2f,0xf0,0x22,0xe5,0x6f,0x30,0xe6,0x19,0xe5, ++0x6f,0x54,0x0f,0xff,0x90,0x91,0x24,0xe0,0xfe,0x4f,0x90,0x01,0x2f,0xf0,0xee,0x64, ++0x80,0x90,0x91,0x24,0xf0,0x53,0x6f,0xbf,0x22,0xe4,0x90,0x91,0x0d,0xf0,0xe5,0x70, ++0x70,0x02,0x81,0x13,0x90,0x91,0x3c,0xe0,0x60,0x0d,0xe4,0xf0,0x53,0x71,0xfd,0xe5, ++0x71,0x54,0x07,0x70,0x6e,0x80,0x69,0x90,0x91,0x28,0xe0,0x04,0xf0,0x53,0x71,0xef, ++0x90,0x91,0x3a,0xe0,0x04,0xf0,0x90,0x91,0x0d,0xe0,0xf9,0xff,0x7e,0x00,0x24,0x01, ++0xfd,0xee,0x33,0xfc,0x90,0x91,0x3a,0xe0,0xb5,0x05,0x06,0xe4,0xb5,0x04,0x02,0x80, ++0x12,0xef,0x24,0x02,0xff,0xe4,0x3e,0xfe,0x90,0x91,0x3a,0xe0,0xb5,0x07,0x0a,0xe4, ++0xb5,0x06,0x06,0x90,0x05,0x58,0xe0,0x04,0xf0,0xe9,0xff,0x90,0x91,0x2f,0xe0,0x2f, ++0xff,0xe4,0x33,0xfe,0x90,0x91,0x28,0xe0,0xd3,0x9f,0xee,0x64,0x80,0xf8,0x74,0x80, ++0x98,0x40,0x0d,0xe5,0x6d,0xb4,0x01,0x0b,0xa3,0xe0,0x70,0x07,0xe0,0x04,0xf0,0x22, ++0x12,0x44,0xc2,0x22,0x90,0x90,0xee,0xe0,0xc3,0x94,0x14,0x50,0x05,0xe0,0x04,0xf0, ++0x81,0xcc,0x90,0x90,0xee,0xe0,0x64,0x14,0x60,0x02,0x81,0xcc,0x90,0x90,0xfd,0xe0, ++0x70,0x25,0x90,0x91,0x00,0xe0,0x70,0x1f,0x90,0x90,0xfe,0xe0,0x70,0x19,0x90,0x91, ++0x01,0xe0,0x70,0x13,0x90,0x90,0xff,0xe0,0x70,0x0d,0x90,0x91,0x02,0xe0,0x70,0x07, ++0x90,0x04,0xfd,0xe0,0x54,0xfe,0xf0,0x90,0x90,0xfd,0xe0,0x90,0x04,0x44,0xf0,0x90, ++0x90,0xfe,0xe0,0x90,0x04,0x45,0xf0,0x90,0x90,0xff,0xe0,0x90,0x04,0x46,0xf0,0xa3, ++0xe4,0xf0,0x90,0x91,0x00,0xe0,0x90,0x04,0x48,0xf0,0x90,0x91,0x01,0xe0,0x90,0x04, ++0x49,0xf0,0x90,0x91,0x02,0xe0,0x90,0x04,0x4a,0xf0,0xa3,0xe4,0xf0,0x90,0x90,0xe9, ++0xe0,0x90,0x04,0x4c,0xf0,0x90,0x90,0xea,0xe0,0x90,0x04,0x4d,0xf0,0x90,0x90,0xeb, ++0xe0,0x90,0x04,0x4e,0xf0,0x90,0x90,0xec,0xe0,0x90,0x04,0x4f,0xf0,0xe4,0x90,0x90, ++0xee,0xf0,0x90,0x90,0xe9,0x04,0xf0,0xe4,0xa3,0xf0,0xa3,0xf0,0xa3,0xf0,0x90,0x90, ++0xfd,0xf0,0xa3,0xf0,0xa3,0xf0,0xa3,0xf0,0xa3,0xf0,0xa3,0xf0,0x90,0x05,0x60,0xe0, ++0x90,0x91,0x8c,0xf0,0x90,0x05,0x61,0xe0,0x90,0x91,0x8d,0xf0,0x90,0x05,0x62,0xe0, ++0x90,0x91,0x8e,0xf0,0x90,0x05,0x63,0xe0,0x90,0x91,0x8f,0xf0,0x90,0x91,0x06,0xe0, ++0xff,0x90,0x91,0x8f,0xe0,0xfe,0xd3,0x9f,0x50,0x0b,0x90,0x91,0x06,0xe0,0xc3,0x9e, ++0xd3,0x94,0x01,0x40,0x10,0x90,0x90,0xf4,0xe0,0xb4,0x01,0x02,0x80,0x03,0x90,0x90, ++0xf8,0xe0,0xff,0x71,0x18,0x22,0x90,0x00,0x02,0x12,0x42,0x20,0x90,0x90,0xf5,0xf0, ++0x90,0x00,0x01,0x12,0x42,0x20,0x25,0xe0,0x25,0xe0,0x90,0x90,0xf4,0xf0,0x12,0x29, ++0xd9,0x25,0xe0,0x25,0xe0,0x90,0x90,0xf8,0xf0,0x90,0x05,0x60,0xe0,0x90,0x91,0x03, ++0xf0,0x90,0x05,0x61,0xe0,0x90,0x91,0x04,0xf0,0x90,0x05,0x62,0xe0,0x90,0x91,0x05, ++0xf0,0x90,0x05,0x63,0xe0,0x90,0x91,0x06,0xf0,0xa2,0xaf,0xe4,0x33,0x90,0x91,0x1c, ++0xf0,0xc2,0xaf,0x90,0x90,0xf4,0xe0,0xff,0x71,0x18,0x90,0x91,0x1c,0xe0,0x24,0xff, ++0x92,0xaf,0x90,0x90,0xf5,0xe0,0x70,0x02,0xc1,0x1f,0x90,0x90,0xf4,0xe0,0x70,0x02, ++0xc1,0x1f,0x90,0x90,0xf8,0xe0,0x70,0x02,0xc1,0x1f,0xa2,0xaf,0xe4,0x33,0x90,0x91, ++0x1c,0xf0,0xc2,0xaf,0x90,0x91,0x07,0x74,0x01,0xf0,0x90,0x91,0x1c,0xe0,0x24,0xff, ++0x92,0xaf,0x12,0x4d,0x9f,0x90,0x00,0x46,0xe0,0x44,0x01,0xfd,0x7f,0x46,0x12,0x4d, ++0xa8,0x90,0x90,0xed,0xe0,0x60,0x15,0x90,0x90,0xf9,0x12,0x43,0x09,0x90,0x80,0x85, ++0x12,0x2a,0x7f,0x7f,0x80,0x7e,0x08,0x12,0x2f,0xd9,0x80,0x06,0x90,0x05,0x22,0x74, ++0x7f,0xf0,0x90,0x00,0x45,0xe0,0x54,0xef,0xfd,0x7f,0x45,0x12,0x4d,0xa8,0x90,0x05, ++0x87,0xe0,0x64,0x80,0xf0,0x90,0x91,0x03,0xe0,0x90,0x05,0x84,0xf0,0x90,0x91,0x04, ++0xe0,0x90,0x05,0x85,0xf0,0x90,0x91,0x05,0xe0,0x90,0x05,0x86,0xf0,0x90,0x91,0x06, ++0xe0,0x90,0x05,0x87,0xf0,0xa2,0xaf,0xe4,0x33,0x90,0x91,0x1c,0xf0,0xc2,0xaf,0x90, ++0x01,0x3c,0xe0,0x44,0x20,0xf0,0x7d,0x20,0xe4,0xff,0x12,0x37,0x00,0x80,0x2d,0x90, ++0x90,0xf5,0xe0,0x70,0x2f,0x90,0x91,0x07,0x12,0x4d,0x9e,0x90,0x00,0x46,0xe0,0x54, ++0xfe,0xfd,0x7f,0x46,0x12,0x4d,0xa8,0x90,0x05,0x22,0xe4,0xf0,0xa2,0xaf,0x33,0x90, ++0x91,0x1c,0xf0,0xc2,0xaf,0x7d,0x20,0xe4,0xff,0x12,0x36,0x92,0x90,0x91,0x1c,0xe0, ++0x24,0xff,0x92,0xaf,0x22,0x8f,0x20,0x8c,0x21,0x8d,0x22,0x22,0x8f,0x23,0x8c,0x24, ++0x8d,0x25,0x22,0xe4,0x90,0x91,0x11,0xf0,0xa3,0xf0,0x90,0x02,0x86,0xe0,0x20,0xe1, ++0x2c,0xc3,0x90,0x91,0x12,0xe0,0x94,0x20,0x90,0x91,0x11,0xe0,0x94,0x03,0x40,0x0a, ++0x90,0x01,0xc6,0xe0,0x44,0x20,0xf0,0x7f,0x00,0x22,0x90,0x91,0x11,0xe4,0x75,0xf0, ++0x01,0x12,0x42,0x81,0x7f,0x01,0x7e,0x00,0x12,0x37,0x54,0x80,0xcd,0x7f,0x01,0x22, ++0x90,0x01,0xcc,0xe0,0x54,0x0f,0x90,0x91,0x11,0xf0,0x90,0x91,0x11,0xe0,0xfd,0x70, ++0x02,0xe1,0xe2,0x90,0x91,0x9c,0xe0,0xff,0x74,0x01,0x7e,0x00,0xa8,0x07,0x08,0x80, ++0x05,0xc3,0x33,0xce,0x33,0xce,0xd8,0xf9,0xff,0xef,0x5d,0x70,0x02,0xe1,0xdb,0x90, ++0x91,0x9c,0xe0,0x75,0xf0,0x04,0x90,0x01,0xd0,0x12,0x43,0x15,0xe0,0x90,0x91,0x12, ++0xf0,0x75,0x63,0x01,0x75,0x64,0x91,0x75,0x65,0x12,0x75,0x66,0x01,0x7b,0x01,0x7a, ++0x91,0x79,0x13,0x12,0x46,0x6d,0x90,0x91,0x13,0xe0,0xff,0xc4,0x13,0x13,0x13,0x54, ++0x01,0x90,0x91,0x9c,0x30,0xe0,0x59,0xe0,0x75,0xf0,0x02,0x90,0x00,0x88,0x12,0x43, ++0x15,0xe0,0x90,0x91,0x14,0xf0,0x90,0x91,0x9c,0xe0,0x75,0xf0,0x02,0x90,0x00,0x89, ++0x12,0x43,0x15,0xe0,0x90,0x91,0x15,0xf0,0x90,0x91,0x9c,0xe0,0x75,0xf0,0x04,0x90, ++0x01,0xd1,0x12,0x43,0x15,0xe0,0x90,0x91,0x16,0xf0,0x90,0x91,0x9c,0xe0,0x75,0xf0, ++0x04,0x90,0x01,0xd2,0x12,0x43,0x15,0xe0,0x90,0x91,0x17,0xf0,0x90,0x91,0x9c,0xe0, ++0x75,0xf0,0x04,0x90,0x01,0xd3,0x12,0x43,0x15,0xe0,0x90,0x91,0x18,0xf0,0x80,0x33, ++0xe0,0x75,0xf0,0x04,0x90,0x01,0xd1,0x12,0x43,0x15,0xe0,0x90,0x91,0x14,0xf0,0x90, ++0x91,0x9c,0xe0,0x75,0xf0,0x04,0x90,0x01,0xd2,0x12,0x43,0x15,0xe0,0x90,0x91,0x15, ++0xf0,0x90,0x91,0x9c,0xe0,0x75,0xf0,0x04,0x90,0x01,0xd3,0x12,0x43,0x15,0xe0,0x90, ++0x91,0x16,0xf0,0xef,0x54,0x7f,0xff,0x7b,0x01,0x7a,0x91,0x79,0x14,0x12,0x52,0x08, ++0x90,0x91,0x11,0xe0,0xff,0x90,0x91,0x9c,0xe0,0xfe,0x74,0x01,0xa8,0x06,0x08,0x80, ++0x02,0xc3,0x33,0xd8,0xfc,0xf4,0x5f,0x90,0x91,0x11,0xf0,0x90,0x91,0x9c,0xe0,0xff, ++0x74,0x01,0xa8,0x07,0x08,0x80,0x02,0xc3,0x33,0xd8,0xfc,0x90,0x01,0xcc,0xf0,0x90, ++0x91,0x9c,0xe0,0x04,0xf0,0xe0,0x54,0x03,0xf0,0xc1,0xaa,0x90,0x01,0xc6,0xe0,0x44, ++0x02,0xf0,0x22,0xad,0x07,0x74,0x11,0x2d,0xf5,0x82,0xe4,0x34,0xfc,0xf5,0x83,0xe0, ++0x44,0x01,0xf0,0x90,0x04,0x80,0xe0,0x54,0x0f,0xfc,0x74,0x14,0x2d,0xf5,0x82,0xe4, ++0x34,0xfc,0xf5,0x83,0xe0,0x54,0xc0,0x4c,0xfd,0x74,0x14,0x2f,0xf5,0x82,0xe4,0x34, ++0xfc,0xf5,0x83,0xed,0xf0,0x22,0xef,0x60,0x0f,0x74,0x21,0x2d,0xf5,0x82,0xe4,0x34, ++0xfc,0xf5,0x83,0xe0,0x44,0x10,0xf0,0x22,0x74,0x21,0x2d,0xf5,0x82,0xe4,0x34,0xfc, ++0xf5,0x83,0xe0,0x54,0xef,0xf0,0x22,0xe4,0xf5,0x6d,0xf5,0x71,0xf5,0x70,0x75,0x6f, ++0x0c,0x75,0x6e,0x0c,0x90,0x91,0x3b,0xf0,0x90,0x91,0x37,0xf0,0x90,0x91,0x36,0xf0, ++0x90,0x91,0x39,0x04,0xf0,0x90,0x91,0x27,0xf0,0xe4,0x90,0x91,0x3c,0xf0,0x90,0x91, ++0x29,0xf0,0x90,0x91,0x34,0x74,0x07,0xf0,0xe4,0x90,0x91,0x28,0xf0,0x90,0x91,0x32, ++0xf0,0xa3,0x74,0x03,0xf0,0x90,0x91,0x2f,0x74,0x0a,0xf0,0xa3,0x74,0x05,0xf0,0x90, ++0x91,0x2d,0x74,0x14,0xf0,0x90,0x91,0x35,0x74,0x05,0xf0,0xe4,0x90,0x91,0x2b,0xf0, ++0x90,0x91,0x25,0xf0,0x90,0x91,0x50,0xf0,0x90,0x91,0x31,0xf0,0x90,0x91,0x3a,0xf0, ++0x90,0x91,0x26,0xf0,0x90,0x91,0x38,0xf0,0x90,0x91,0x2e,0xf0,0x90,0x91,0x2c,0xf0, ++0x22,0x12,0x4c,0x89,0xef,0x64,0x01,0x60,0x08,0x90,0x01,0xb9,0x74,0x01,0xf0,0x80, ++0x30,0x90,0x91,0x37,0xe0,0x60,0x08,0x90,0x01,0xb9,0x74,0x02,0xf0,0x80,0x22,0x90, ++0x91,0x36,0xe0,0x60,0x08,0x90,0x01,0xb9,0x74,0x04,0xf0,0x80,0x14,0xe5,0x6f,0x54, ++0x0f,0xd3,0x94,0x04,0x40,0x08,0x90,0x01,0xb9,0x74,0x08,0xf0,0x80,0x03,0x7f,0x01, ++0x22,0x90,0x01,0xb8,0x74,0x08,0xf0,0x7f,0x00,0x22,0x12,0x4c,0x89,0xef,0x64,0x01, ++0x60,0x08,0x90,0x01,0xb9,0x74,0x01,0xf0,0x80,0x58,0xe5,0x71,0x54,0x03,0x60,0x08, ++0x90,0x01,0xb9,0x74,0x02,0xf0,0x80,0x4a,0xe5,0x6f,0x54,0x0f,0xd3,0x94,0x02,0x40, ++0x08,0x90,0x01,0xb9,0x74,0x04,0xf0,0x80,0x39,0xe5,0x71,0x30,0xe2,0x08,0x90,0x01, ++0xb9,0x74,0x08,0xf0,0x80,0x2c,0xe5,0x71,0x30,0xe4,0x08,0x90,0x01,0xb9,0x74,0x10, ++0xf0,0x80,0x1f,0x90,0x91,0x29,0xe0,0x60,0x08,0x90,0x01,0xb9,0x74,0x20,0xf0,0x80, ++0x11,0x90,0x91,0x31,0xe0,0x60,0x08,0x90,0x01,0xb9,0x74,0x80,0xf0,0x80,0x03,0x7f, ++0x01,0x22,0x90,0x01,0xb8,0x74,0x04,0xf0,0x7f,0x00,0x22,0x90,0x06,0x04,0xe0,0x54, ++0xbf,0xf0,0xef,0x60,0x0a,0xe5,0x6d,0xb4,0x01,0x05,0xe4,0xff,0x12,0x47,0xc9,0x53, ++0x6e,0xf0,0x43,0x6e,0x0c,0x22,0x90,0x91,0x9d,0xef,0xf0,0x31,0x9f,0x90,0x91,0x9d, ++0xe0,0x60,0x05,0x90,0x05,0x22,0xe4,0xf0,0x53,0x6e,0xf0,0x43,0x6e,0x04,0x22,0x90, ++0x90,0xd8,0x12,0x43,0x09,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0x78,0x7e,0x08,0x12, ++0x2f,0xd9,0x90,0x90,0xdc,0x12,0x43,0x09,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0x04, ++0x7e,0x0c,0x12,0x2f,0xd9,0x90,0x90,0xe0,0x12,0x43,0x09,0x90,0x80,0x85,0x12,0x2a, ++0x7f,0x7f,0x00,0x7e,0x08,0x12,0x2f,0xd9,0x90,0x90,0xe4,0x12,0x43,0x09,0x90,0x80, ++0x85,0x12,0x2a,0x7f,0x7f,0x70,0x7e,0x0e,0x12,0x2f,0xd9,0x90,0x80,0x59,0x12,0x2a, ++0x8b,0x00,0x03,0x2d,0x95,0xe4,0xfd,0xff,0x12,0x34,0x81,0x90,0x91,0x51,0xe0,0xb4, ++0x01,0x11,0x90,0x80,0x59,0x12,0x2a,0x8b,0x00,0x03,0x2d,0x95,0xe4,0xfd,0x7f,0x01, ++0x12,0x34,0x81,0x22,0x8f,0x77,0xe4,0x90,0x91,0x96,0xf0,0xa3,0xf0,0x90,0x01,0x09, ++0xe0,0x7f,0x00,0x30,0xe7,0x02,0x7f,0x01,0xef,0x65,0x77,0x60,0x3e,0xc3,0x90,0x91, ++0x97,0xe0,0x94,0x88,0x90,0x91,0x96,0xe0,0x94,0x13,0x40,0x08,0x90,0x01,0xc6,0xe0, ++0x44,0x80,0xf0,0x22,0x90,0x91,0x96,0xe4,0x75,0xf0,0x01,0x12,0x42,0x81,0x7f,0x14, ++0x7e,0x00,0x12,0x37,0x54,0xd3,0x90,0x91,0x97,0xe0,0x94,0x32,0x90,0x91,0x96,0xe0, ++0x94,0x00,0x40,0xb9,0x90,0x01,0xc7,0xe0,0x30,0xe0,0xb2,0x22,0x53,0x6e,0xf0,0x43, ++0x6e,0x01,0x12,0x45,0x00,0x12,0x45,0x01,0x53,0x6e,0xf0,0x43,0x6e,0x02,0x22,0x8f, ++0x78,0x12,0x47,0xe6,0xef,0x64,0x01,0x70,0x2e,0x90,0x91,0x44,0x12,0x48,0x1e,0xe5, ++0x78,0x60,0x10,0x74,0x21,0x2f,0xf5,0x82,0xe4,0x34,0xfc,0xf5,0x83,0xe0,0x44,0x10, ++0xf0,0x80,0x0e,0x74,0x21,0x2f,0xf5,0x82,0xe4,0x34,0xfc,0xf5,0x83,0xe0,0x54,0xef, ++0xf0,0x90,0x04,0x1f,0x74,0x20,0xf0,0x22,0xe5,0x6d,0x64,0x01,0x70,0x63,0xe5,0x70, ++0x60,0x5f,0xe5,0x70,0x64,0x02,0x60,0x06,0xe5,0x70,0x64,0x05,0x70,0x27,0x90,0x06, ++0xab,0xe0,0x90,0x91,0x27,0xf0,0x90,0x06,0xaa,0xe0,0x90,0x91,0x39,0xf0,0x90,0x91, ++0x27,0xe0,0x70,0x07,0x90,0x91,0x39,0xe0,0xff,0x80,0x05,0x90,0x91,0x27,0xe0,0xff, ++0x90,0x91,0x27,0xef,0xf0,0x90,0x91,0x29,0xe0,0x60,0x03,0xe0,0x14,0xf0,0xe4,0x90, ++0x91,0x28,0xf0,0x90,0x01,0x57,0xf0,0x90,0x01,0x3c,0x74,0x02,0xf0,0x53,0x71,0xfd, ++0x53,0x71,0xef,0xe5,0x70,0x14,0x24,0xfd,0x50,0x02,0x80,0x03,0x12,0x45,0xc7,0x71, ++0x22,0x22,0xd3,0x10,0xaf,0x01,0xc3,0xc0,0xd0,0xd0,0xd0,0x92,0xaf,0x22,0xe4,0xfb, ++0x90,0x91,0x78,0x12,0x2a,0x8b,0x00,0x00,0x00,0x00,0xe5,0x70,0x70,0x02,0x61,0xc0, ++0xe5,0x6d,0x64,0x01,0x70,0x7a,0xe5,0x70,0x14,0x60,0x2b,0x24,0xfd,0x60,0x27,0x24, ++0x02,0x24,0xfb,0x50,0x02,0x80,0x21,0x90,0x91,0x27,0xe0,0x14,0xf0,0xe0,0x60,0x04, ++0xa3,0xe0,0x60,0x14,0x90,0x91,0x27,0xe0,0x70,0x08,0x90,0x91,0x39,0xe0,0x90,0x91, ++0x27,0xf0,0x7b,0x01,0x80,0x02,0x7b,0x01,0xeb,0x60,0x45,0x43,0x71,0x10,0xe4,0x90, ++0x91,0x66,0xf0,0x90,0x91,0x3a,0xe0,0x75,0xf0,0x05,0xa4,0xff,0x90,0x91,0x34,0xe0, ++0x2f,0x12,0x44,0x4e,0x90,0x01,0x57,0x74,0x05,0xf0,0xe5,0x6e,0x54,0x0f,0xc3,0x94, ++0x04,0x50,0x07,0x7d,0x01,0x7f,0x04,0x12,0x47,0x27,0x90,0x91,0x2e,0xe0,0x60,0x10, ++0x90,0x91,0x2c,0xe0,0x90,0x07,0x78,0x60,0x04,0x74,0x0d,0xf0,0x22,0x74,0x09,0xf0, ++0x22,0xe4,0xfb,0x90,0x91,0x7c,0x12,0x2a,0x8b,0x00,0x00,0x00,0x00,0xe5,0x70,0x60, ++0x5f,0xe5,0x6d,0x64,0x01,0x70,0x59,0x0b,0x90,0x91,0x27,0xf0,0x04,0x60,0x51,0x43, ++0x71,0x10,0xe4,0x90,0x91,0x66,0xf0,0x90,0x91,0x3a,0xe0,0x75,0xf0,0x05,0xa4,0xff, ++0x90,0x91,0x34,0xe0,0x2f,0x90,0x91,0x67,0xf0,0xe4,0x1b,0x12,0x44,0x54,0x90,0x01, ++0x57,0x74,0x05,0xf0,0xe5,0x6e,0x54,0x0f,0xc3,0x94,0x04,0x50,0x07,0x7d,0x01,0x7f, ++0x04,0x12,0x47,0x27,0x90,0x91,0x2e,0xe0,0x60,0x11,0x90,0x91,0x2c,0xe0,0x90,0x07, ++0x78,0x60,0x05,0x74,0x0d,0xf0,0x80,0x03,0x74,0x09,0xf0,0x90,0x05,0x22,0xe4,0xf0, ++0x22,0x90,0x91,0x80,0x12,0x2a,0x8b,0x00,0x00,0x00,0x00,0xe5,0x70,0x14,0x24,0xfd, ++0x50,0x02,0x80,0x21,0x90,0x91,0x3b,0xe0,0x60,0x06,0x7d,0x01,0x7f,0x0c,0x80,0x0d, ++0xe5,0x6e,0x54,0x0f,0xc3,0x94,0x04,0x50,0x07,0x7d,0x01,0x7f,0x04,0x12,0x47,0x27, ++0xe4,0xff,0x12,0x48,0xb3,0x22,0x90,0x91,0x08,0xe0,0x54,0xf0,0x44,0x03,0xf0,0x54, ++0x0f,0x44,0x80,0xf0,0x7b,0x00,0x7a,0x00,0x79,0x58,0x90,0x91,0x71,0x12,0x43,0x41, ++0x0b,0x7a,0x91,0x79,0x08,0x02,0x46,0xb7,0xd3,0x10,0xaf,0x01,0xc3,0xc0,0xd0,0x90, ++0x91,0x84,0xee,0xf0,0xa3,0xef,0xf0,0xe4,0xa3,0xf0,0xa3,0xf0,0x90,0x91,0x84,0xe0, ++0xfe,0xa3,0xe0,0xf5,0x82,0x8e,0x83,0xe0,0x60,0x2d,0xc3,0x90,0x91,0x87,0xe0,0x94, ++0xe8,0x90,0x91,0x86,0xe0,0x94,0x03,0x40,0x0b,0x90,0x01,0xc6,0xe0,0x44,0x10,0xf0, ++0x7f,0x00,0x80,0x15,0x90,0x91,0x86,0xe4,0x75,0xf0,0x01,0x12,0x42,0x81,0x7f,0x0a, ++0x7e,0x00,0x12,0x37,0x54,0x80,0xc5,0x7f,0x01,0xd0,0xd0,0x92,0xaf,0x22,0xd3,0x10, ++0xaf,0x01,0xc3,0xc0,0xd0,0x90,0x91,0x1c,0x12,0x43,0x41,0x90,0x91,0x1f,0x12,0x2a, ++0x8b,0x00,0x00,0x00,0x00,0x90,0x91,0x1c,0x12,0x43,0x21,0x90,0x00,0x01,0x12,0x42, ++0x20,0x90,0x91,0x3b,0xf0,0x90,0x00,0x03,0x12,0x42,0x20,0x90,0x91,0x25,0xf0,0x90, ++0x00,0x04,0x12,0x42,0x20,0xff,0x54,0x01,0x90,0x91,0x26,0xf0,0xef,0xc3,0x13,0x54, ++0x01,0x90,0x91,0x2e,0xf0,0x90,0x00,0x04,0x12,0x42,0x20,0xff,0x13,0x13,0x54,0x01, ++0x90,0x91,0x2c,0xf0,0x90,0x91,0x2e,0xe0,0x90,0x91,0x1f,0x70,0x26,0x12,0x2a,0x8b, ++0x00,0x00,0x02,0x10,0x90,0x91,0x1f,0x12,0x43,0x09,0x90,0x80,0x85,0x12,0x2a,0x7f, ++0x7f,0x60,0x7e,0x08,0x12,0x2f,0xd9,0x90,0x91,0x1f,0x12,0x2a,0x8b,0x00,0x00,0x03, ++0x10,0x80,0x24,0x12,0x2a,0x8b,0x00,0x00,0x01,0x10,0x90,0x91,0x1f,0x12,0x43,0x09, ++0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0x60,0x7e,0x08,0x12,0x2f,0xd9,0x90,0x91,0x1f, ++0x12,0x2a,0x8b,0x00,0x00,0x03,0x00,0x90,0x91,0x1f,0x12,0x43,0x09,0x90,0x80,0x85, ++0x12,0x2a,0x7f,0x7f,0x70,0x7e,0x08,0x12,0x2f,0xd9,0x90,0x91,0x26,0xe0,0x70,0x3d, ++0x90,0x91,0x38,0x74,0x01,0xf0,0x7f,0x00,0x7e,0x08,0x12,0x27,0xde,0x90,0x91,0x1f, ++0x12,0x2a,0x7f,0x90,0x91,0x1f,0x12,0x43,0x09,0xec,0x44,0x02,0xfc,0x90,0x91,0x1f, ++0x12,0x2a,0x7f,0x90,0x91,0x1f,0x12,0x43,0x09,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f, ++0x00,0x7e,0x08,0x12,0x2f,0xd9,0x90,0x02,0x86,0xe0,0x54,0xfb,0xf0,0x90,0x91,0x1c, ++0x12,0x43,0x21,0x12,0x49,0x80,0x90,0x01,0xe5,0xe5,0x70,0xf0,0x90,0x91,0x3b,0xe0, ++0x90,0x01,0xe6,0xf0,0xd0,0xd0,0x92,0xaf,0x22,0x90,0x00,0x02,0x12,0x42,0x20,0xff, ++0x30,0xe0,0x25,0x12,0x29,0xd9,0x90,0x91,0x2f,0xf0,0x90,0x00,0x01,0x12,0x42,0x20, ++0x90,0x91,0x30,0xf0,0xef,0xc3,0x13,0x54,0x7f,0x90,0x91,0x2d,0xf0,0x90,0x00,0x03, ++0x12,0x42,0x20,0x90,0x91,0x35,0xf0,0x22,0x90,0x91,0x2f,0x74,0x0a,0xf0,0x90,0x91, ++0x30,0x74,0x05,0xf0,0x90,0x91,0x2d,0x74,0x14,0xf0,0x90,0x91,0x35,0x74,0x05,0xf0, ++0x22,0x90,0x02,0x09,0xe0,0xfd,0x12,0x29,0xd9,0xfe,0xaf,0x05,0xed,0x2e,0x90,0x91, ++0x41,0xf0,0x90,0x00,0x01,0x12,0x42,0x20,0xff,0xed,0x2f,0x90,0x91,0x42,0xf0,0x90, ++0x00,0x02,0x12,0x42,0x20,0xff,0xed,0x2f,0x90,0x91,0x43,0xf0,0x90,0x00,0x03,0x12, ++0x42,0x20,0xff,0xed,0x2f,0x90,0x91,0x44,0xf0,0x90,0x00,0x04,0x12,0x42,0x20,0xff, ++0xae,0x05,0xed,0x2f,0x90,0x91,0x45,0xf0,0x22,0xd3,0x10,0xaf,0x01,0xc3,0xc0,0xd0, ++0x90,0x91,0x47,0xe0,0x90,0x91,0x1d,0xf0,0x90,0x91,0x48,0xe0,0xf5,0x19,0xa3,0xe0, ++0xf5,0x1a,0xe4,0xf5,0x16,0x74,0x4a,0x25,0x16,0xf5,0x82,0xe4,0x34,0x91,0xf5,0x83, ++0xe0,0xff,0x74,0x1b,0x25,0x16,0xf8,0xa6,0x07,0x05,0x16,0xe5,0x16,0xb4,0x04,0xe5, ++0x90,0x91,0x1d,0xe0,0x12,0x43,0x4a,0x66,0xe6,0x00,0x68,0x13,0x01,0x66,0xee,0x02, ++0x66,0xee,0x03,0x66,0xee,0x04,0x68,0x13,0x05,0x67,0xe3,0x80,0x67,0xf9,0x81,0x68, ++0x13,0x82,0x00,0x00,0x68,0x0f,0xaf,0x1e,0x12,0x73,0xdd,0x02,0x68,0x13,0x90,0x91, ++0x1d,0xe0,0xff,0xb4,0x02,0x08,0x90,0x91,0x1c,0x74,0x01,0xf0,0x80,0x0f,0xef,0x90, ++0x91,0x1c,0xb4,0x03,0x05,0x74,0x02,0xf0,0x80,0x03,0x74,0x04,0xf0,0xc3,0xe5,0x19, ++0x94,0x08,0x50,0x4a,0xe4,0xf5,0x16,0x90,0x91,0x1c,0xe0,0xff,0xe5,0x16,0xc3,0x9f, ++0x40,0x03,0x02,0x68,0x13,0xc3,0xe5,0x19,0x94,0x01,0x50,0x14,0xe5,0x16,0x25,0x1a, ++0xff,0xc3,0x74,0x03,0x95,0x16,0x24,0x1b,0xf8,0xe6,0xfd,0x12,0x4d,0xa8,0x80,0x1a, ++0xc3,0x74,0x03,0x95,0x16,0x24,0x1b,0xf8,0xe6,0xff,0xe5,0x16,0x7c,0x00,0x25,0x1a, ++0xfd,0xec,0x35,0x19,0x8d,0x82,0xf5,0x83,0xef,0xf0,0x05,0x16,0x80,0xb9,0xc3,0xe5, ++0x19,0x94,0x10,0x40,0x03,0x02,0x68,0x13,0x90,0x91,0x1d,0xe0,0x64,0x04,0x60,0x03, ++0x02,0x68,0x13,0xaf,0x1c,0xfc,0xfd,0xfe,0x78,0x10,0x12,0x2a,0x6c,0xc0,0x04,0xc0, ++0x05,0xc0,0x06,0xc0,0x07,0xaf,0x1b,0xe4,0xfc,0xfd,0xfe,0x78,0x18,0x12,0x2a,0x6c, ++0xd0,0x03,0xd0,0x02,0xd0,0x01,0xd0,0x00,0x12,0x42,0xfc,0xc0,0x04,0xc0,0x05,0xc0, ++0x06,0xc0,0x07,0xaf,0x1d,0xe4,0xfc,0xfd,0xfe,0x78,0x08,0x12,0x2a,0x6c,0xd0,0x03, ++0xd0,0x02,0xd0,0x01,0xd0,0x00,0x12,0x42,0xfc,0xa8,0x04,0xa9,0x05,0xaa,0x06,0xab, ++0x07,0xaf,0x1e,0xe4,0xfc,0xfd,0xfe,0x12,0x42,0xfc,0xa3,0x12,0x2a,0x7f,0x90,0x91, ++0x1e,0x12,0x43,0x09,0x90,0x80,0x85,0x12,0x2a,0x7f,0xaf,0x1a,0xae,0x19,0x12,0x2f, ++0xd9,0x80,0x30,0xe5,0x1d,0x7f,0x00,0xfe,0xef,0x25,0x1e,0xf5,0x18,0xe4,0x3e,0xf5, ++0x17,0xaf,0x18,0xfe,0x12,0x37,0x54,0x80,0x1a,0xe5,0x1d,0x7f,0x00,0xfe,0xef,0x25, ++0x1e,0xf5,0x18,0xe4,0x3e,0xf5,0x17,0xaf,0x18,0xfe,0x12,0x36,0xcb,0x80,0x04,0x7f, ++0x00,0x80,0x02,0x7f,0x01,0xd0,0xd0,0x92,0xaf,0x22,0x8e,0x0e,0x8f,0x0f,0x8b,0x10, ++0x8a,0x11,0x89,0x12,0xe4,0x90,0x91,0x11,0xf0,0xef,0x90,0x00,0x31,0xf0,0x12,0x4c, ++0xa0,0xe5,0x0e,0x54,0x03,0xff,0x90,0x00,0x32,0xe0,0x54,0xfc,0x4f,0xf0,0x12,0x4c, ++0xa0,0x90,0x00,0x33,0xe0,0x54,0x7f,0xf0,0x12,0x4c,0xa0,0x90,0x00,0x33,0xe0,0x20, ++0xe7,0x0e,0x90,0x91,0x11,0xe0,0xc3,0x94,0x64,0x50,0x05,0xe0,0x04,0xf0,0x80,0xeb, ++0x90,0x91,0x11,0xe0,0xc3,0x94,0x64,0x50,0x10,0x90,0x00,0x30,0xe0,0xab,0x10,0xaa, ++0x11,0xa9,0x12,0x12,0x42,0x4d,0x7f,0x01,0x22,0x7f,0x00,0x22,0xe4,0x90,0x91,0x98, ++0xf0,0xa3,0xf0,0x90,0x05,0xf8,0xe0,0x70,0x0f,0xa3,0xe0,0x70,0x0b,0xa3,0xe0,0x70, ++0x07,0xa3,0xe0,0x70,0x03,0x7f,0x01,0x22,0xd3,0x90,0x91,0x99,0xe0,0x94,0xe8,0x90, ++0x91,0x98,0xe0,0x94,0x03,0x40,0x03,0x7f,0x00,0x22,0x7f,0x32,0x7e,0x00,0x12,0x37, ++0x54,0x90,0x91,0x98,0xe4,0x75,0xf0,0x01,0x12,0x42,0x81,0x80,0xc6,0x7f,0x78,0x7e, ++0x08,0x12,0x27,0xde,0x90,0x90,0xd8,0x12,0x2a,0x7f,0x7f,0x04,0x7e,0x0c,0x12,0x27, ++0xde,0x90,0x90,0xdc,0x12,0x2a,0x7f,0x7f,0x00,0x7e,0x08,0x12,0x27,0xde,0x90,0x90, ++0xe0,0x12,0x2a,0x7f,0x90,0x91,0x51,0xe0,0x90,0x90,0xd8,0xb4,0x01,0x0d,0x12,0x43, ++0x09,0xef,0x54,0xc7,0xff,0xed,0x54,0xc7,0xfd,0x80,0x07,0x12,0x43,0x09,0xef,0x54, ++0xc7,0xff,0xec,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0x78,0x7e,0x08,0x12,0x2f,0xd9, ++0x90,0x90,0xdc,0x12,0x43,0x09,0xef,0x54,0x0f,0xff,0xec,0x90,0x80,0x85,0x12,0x2a, ++0x7f,0x7f,0x04,0x7e,0x0c,0x12,0x2f,0xd9,0x90,0x90,0xe0,0x12,0x43,0x09,0xef,0x44, ++0x02,0xff,0xec,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0x00,0x7e,0x08,0x12,0x2f,0xd9, ++0x7f,0x70,0x7e,0x0e,0x12,0x27,0xde,0x90,0x90,0xe4,0x12,0x2a,0x7f,0x90,0x80,0x85, ++0x12,0x2a,0x8b,0x00,0x1b,0x25,0xa0,0x7f,0x70,0x7e,0x0e,0x12,0x2f,0xd9,0x90,0x80, ++0x59,0x12,0x2a,0x8b,0x00,0x00,0x00,0x00,0xe4,0xfd,0xff,0x12,0x34,0x81,0x90,0x91, ++0x51,0xe0,0xb4,0x01,0x11,0x90,0x80,0x59,0x12,0x2a,0x8b,0x00,0x00,0x00,0x00,0xe4, ++0xfd,0x7f,0x01,0x12,0x34,0x81,0x22,0xef,0x70,0x02,0x61,0x3d,0x90,0x90,0xe8,0xe0, ++0x60,0x02,0xe1,0x08,0x90,0x90,0xd4,0x12,0x43,0x09,0x90,0x80,0x85,0x12,0x2a,0x7f, ++0x7f,0x8c,0x7e,0x08,0x12,0x2f,0xd9,0x90,0x90,0x80,0x12,0x43,0x09,0x90,0x80,0x85, ++0x12,0x2a,0x7f,0x7f,0x44,0x7e,0x08,0x12,0x2f,0xd9,0x90,0x90,0x84,0x12,0x43,0x09, ++0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0x5c,0x7e,0x08,0x12,0x2f,0xd9,0x90,0x90,0x88, ++0x12,0x43,0x09,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0x6c,0x7e,0x0e,0x12,0x2f,0xd9, ++0x90,0x90,0x8c,0x12,0x43,0x09,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0x70,0x7e,0x0e, ++0x12,0x2f,0xd9,0x90,0x90,0x90,0x12,0x43,0x09,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f, ++0x74,0x7e,0x0e,0x12,0x2f,0xd9,0x90,0x90,0x94,0x12,0x43,0x09,0x90,0x80,0x85,0x12, ++0x2a,0x7f,0x7f,0x78,0x7e,0x0e,0x12,0x2f,0xd9,0x90,0x90,0x98,0x12,0x43,0x09,0x90, ++0x80,0x85,0x12,0x2a,0x7f,0x7f,0x7c,0x7e,0x0e,0x12,0x2f,0xd9,0x90,0x90,0x9c,0x12, ++0x43,0x09,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0x80,0x7e,0x0e,0x12,0x2f,0xd9,0x90, ++0x90,0xa0,0x12,0x43,0x09,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0x84,0x7e,0x0e,0x12, ++0x2f,0xd9,0x90,0x90,0xa4,0x12,0x43,0x09,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0x88, ++0x7e,0x0e,0x12,0x2f,0xd9,0x90,0x90,0xa8,0x12,0x43,0x09,0x90,0x80,0x85,0x12,0x2a, ++0x7f,0x7f,0x8c,0x7e,0x0e,0x12,0x2f,0xd9,0x90,0x90,0xac,0x12,0x43,0x09,0x90,0x80, ++0x85,0x12,0x2a,0x7f,0x7f,0xd0,0x7e,0x0e,0x12,0x2f,0xd9,0x90,0x90,0xb0,0x12,0x43, ++0x09,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0xd4,0x7e,0x0e,0x12,0x2f,0xd9,0x90,0x90, ++0xb4,0x12,0x43,0x09,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0xd8,0x7e,0x0e,0x12,0x2f, ++0xd9,0x90,0x90,0xb8,0x12,0x43,0x09,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0xdc,0x7e, ++0x0e,0x12,0x2f,0xd9,0x90,0x90,0xbc,0x12,0x43,0x09,0x90,0x80,0x85,0x12,0x2a,0x7f, ++0x7f,0xe0,0x7e,0x0e,0x12,0x2f,0xd9,0x90,0x90,0xc0,0x12,0x43,0x09,0x90,0x80,0x85, ++0x12,0x2a,0x7f,0x7f,0xec,0x7e,0x0e,0x12,0x2f,0xd9,0x90,0x90,0xc4,0x12,0x43,0x09, ++0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0x04,0x7e,0x0c,0x12,0x2f,0xd9,0x90,0x90,0xc8, ++0x12,0x43,0x09,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0x04,0x7e,0x0d,0x12,0x2f,0xd9, ++0x90,0x90,0xcc,0x12,0x43,0x09,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0x0c,0x7e,0x09, ++0x12,0x2f,0xd9,0x90,0x90,0xd0,0x12,0x43,0x09,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f, ++0x04,0x7e,0x08,0x12,0x2f,0xd9,0x90,0x90,0xe8,0x74,0x01,0xf0,0x22,0x90,0x90,0xe8, ++0xe0,0x64,0x01,0x60,0x02,0xe1,0x08,0x7f,0x8c,0x7e,0x08,0x12,0x27,0xde,0x90,0x90, ++0xd4,0x12,0x2a,0x7f,0x7f,0x44,0x7e,0x08,0x12,0x27,0xde,0x90,0x90,0x80,0x12,0x2a, ++0x7f,0x7f,0x5c,0x7e,0x08,0x12,0x27,0xde,0x90,0x90,0x84,0x12,0x2a,0x7f,0x7f,0x6c, ++0x7e,0x0e,0x12,0x27,0xde,0x90,0x90,0x88,0x12,0x2a,0x7f,0x7f,0x70,0x7e,0x0e,0x12, ++0x27,0xde,0x90,0x90,0x8c,0x12,0x2a,0x7f,0x7f,0x74,0x7e,0x0e,0x12,0x27,0xde,0x90, ++0x90,0x90,0x12,0x2a,0x7f,0x7f,0x78,0x7e,0x0e,0x12,0x27,0xde,0x90,0x90,0x94,0x12, ++0x2a,0x7f,0x7f,0x7c,0x7e,0x0e,0x12,0x27,0xde,0x90,0x90,0x98,0x12,0x2a,0x7f,0x7f, ++0x80,0x7e,0x0e,0x12,0x27,0xde,0x90,0x90,0x9c,0x12,0x2a,0x7f,0x7f,0x84,0x7e,0x0e, ++0x12,0x27,0xde,0x90,0x90,0xa0,0x12,0x2a,0x7f,0x7f,0x88,0x7e,0x0e,0x12,0x27,0xde, ++0x90,0x90,0xa4,0x12,0x2a,0x7f,0x7f,0x8c,0x7e,0x0e,0x12,0x27,0xde,0x90,0x90,0xa8, ++0x12,0x2a,0x7f,0x7f,0xd0,0x7e,0x0e,0x12,0x27,0xde,0x90,0x90,0xac,0x12,0x2a,0x7f, ++0x7f,0xd4,0x7e,0x0e,0x12,0x27,0xde,0x90,0x90,0xb0,0x12,0x2a,0x7f,0x7f,0xd8,0x7e, ++0x0e,0x12,0x27,0xde,0x90,0x90,0xb4,0x12,0x2a,0x7f,0x7f,0xdc,0x7e,0x0e,0x12,0x27, ++0xde,0x90,0x90,0xb8,0x12,0x2a,0x7f,0x7f,0xe0,0x7e,0x0e,0x12,0x27,0xde,0x90,0x90, ++0xbc,0x12,0x2a,0x7f,0x7f,0xec,0x7e,0x0e,0x12,0x27,0xde,0x90,0x90,0xc0,0x12,0x2a, ++0x7f,0x7f,0x04,0x7e,0x0c,0x12,0x27,0xde,0x90,0x90,0xc4,0x12,0x2a,0x7f,0x7f,0x04, ++0x7e,0x0d,0x12,0x27,0xde,0x90,0x90,0xc8,0x12,0x2a,0x7f,0x7f,0x0c,0x7e,0x09,0x12, ++0x27,0xde,0x90,0x90,0xcc,0x12,0x2a,0x7f,0x7f,0x04,0x7e,0x08,0x12,0x27,0xde,0x90, ++0x90,0xd0,0x12,0x2a,0x7f,0x7f,0x8c,0x7e,0x08,0x12,0x27,0xde,0x90,0x91,0x88,0x12, ++0x2a,0x7f,0x90,0x91,0x88,0x12,0x43,0x09,0xed,0x44,0xc0,0xfd,0xec,0x90,0x91,0x88, ++0x12,0x2a,0x7f,0x90,0x91,0x88,0x12,0x43,0x09,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f, ++0x8c,0x7e,0x08,0x12,0x2f,0xd9,0x90,0x80,0x85,0x12,0x2a,0x8b,0x00,0x01,0x00,0x00, ++0x7f,0x44,0x7e,0x08,0x12,0x2f,0xd9,0x90,0x80,0x85,0x12,0x2a,0x8b,0x00,0xdb,0x25, ++0xa4,0x7f,0x5c,0x7e,0x08,0x12,0x2f,0xd9,0x90,0x80,0x85,0x12,0x2a,0x8b,0x20,0xdb, ++0x25,0xa4,0x7f,0x6c,0x7e,0x0e,0x12,0x2f,0xd9,0x90,0x80,0x85,0x12,0x2a,0x8b,0x20, ++0xdb,0x25,0xa4,0x7f,0x70,0x7e,0x0e,0x12,0x2f,0xd9,0x90,0x80,0x85,0x12,0x2a,0x8b, ++0x04,0x1b,0x25,0xa4,0x7f,0x74,0x7e,0x0e,0x12,0x2f,0xd9,0x90,0x80,0x85,0x12,0x2a, ++0x8b,0x04,0x1b,0x25,0xa4,0x7f,0x78,0x7e,0x0e,0x12,0x2f,0xd9,0x90,0x80,0x85,0x12, ++0x2a,0x8b,0x04,0x1b,0x25,0xa4,0x7f,0x7c,0x7e,0x0e,0x12,0x2f,0xd9,0x90,0x80,0x85, ++0x12,0x2a,0x8b,0x04,0x1b,0x25,0xa4,0x7f,0x80,0x7e,0x0e,0x12,0x2f,0xd9,0x90,0x80, ++0x85,0x12,0x2a,0x8b,0x63,0xdb,0x25,0xa4,0x7f,0x84,0x7e,0x0e,0x12,0x2f,0xd9,0x90, ++0x80,0x85,0x12,0x2a,0x8b,0x04,0x1b,0x25,0xa4,0x7f,0x88,0x7e,0x0e,0x12,0x2f,0xd9, ++0x90,0x80,0x85,0x12,0x2a,0x8b,0x20,0xdb,0x25,0xa4,0x7f,0x8c,0x7e,0x0e,0x12,0x2f, ++0xd9,0x90,0x80,0x85,0x12,0x2a,0x8b,0x20,0xdb,0x25,0xa4,0x7f,0xd0,0x7e,0x0e,0x12, ++0x2f,0xd9,0x90,0x80,0x85,0x12,0x2a,0x8b,0x20,0xdb,0x25,0xa4,0x7f,0xd4,0x7e,0x0e, ++0x12,0x2f,0xd9,0x90,0x80,0x85,0x12,0x2a,0x8b,0x20,0xdb,0x25,0xa4,0x7f,0xd8,0x7e, ++0x0e,0x12,0x2f,0xd9,0x90,0x80,0x85,0x12,0x2a,0x8b,0x00,0x1b,0x25,0xa4,0x7f,0xdc, ++0x7e,0x0e,0x12,0x2f,0xd9,0x90,0x80,0x85,0x12,0x2a,0x8b,0x00,0x1b,0x25,0xa4,0x7f, ++0xe0,0x7e,0x0e,0x12,0x2f,0xd9,0x90,0x80,0x85,0x12,0x2a,0x8b,0x24,0xdb,0x25,0xa4, ++0x7f,0xec,0x7e,0x0e,0x12,0x2f,0xd9,0x7f,0x04,0x7e,0x0c,0x12,0x27,0xde,0x90,0x91, ++0x88,0x12,0x2a,0x7f,0x90,0x91,0x88,0x12,0x43,0x09,0xe4,0xff,0xec,0x90,0x91,0x88, ++0x12,0x2a,0x7f,0x90,0x91,0x88,0x12,0x43,0x09,0xef,0x44,0x11,0xff,0xec,0x90,0x91, ++0x88,0x12,0x2a,0x7f,0x90,0x91,0x88,0x12,0x43,0x09,0x90,0x80,0x85,0x12,0x2a,0x7f, ++0x7f,0x04,0x7e,0x0c,0x12,0x2f,0xd9,0x7f,0x04,0x7e,0x0d,0x12,0x27,0xde,0x90,0x91, ++0x88,0x12,0x2a,0x7f,0x90,0x91,0x88,0x12,0x43,0x09,0xef,0x54,0xf0,0xff,0xec,0x90, ++0x91,0x88,0x12,0x2a,0x7f,0x90,0x91,0x88,0x12,0x43,0x09,0xef,0x44,0x01,0xff,0xec, ++0x90,0x91,0x88,0x12,0x2a,0x7f,0x90,0x91,0x88,0x12,0x43,0x09,0x90,0x80,0x85,0x12, ++0x2a,0x7f,0x7f,0x04,0x7e,0x0d,0x12,0x2f,0xd9,0x7f,0x0c,0x7e,0x09,0x12,0x27,0xde, ++0x90,0x91,0x88,0x12,0x2a,0x7f,0x90,0x91,0x88,0x12,0x43,0x09,0xe4,0xff,0xec,0x90, ++0x91,0x88,0x12,0x2a,0x7f,0x90,0x91,0x88,0x12,0x43,0x09,0xef,0x44,0x11,0xff,0xec, ++0x90,0x91,0x88,0x12,0x2a,0x7f,0x90,0x91,0x88,0x12,0x43,0x09,0x90,0x80,0x85,0x12, ++0x2a,0x7f,0x7f,0x0c,0x7e,0x09,0x12,0x2f,0xd9,0x7f,0x0c,0x7e,0x09,0x12,0x27,0xde, ++0x90,0x91,0x88,0x12,0x2a,0x7f,0x90,0x91,0x88,0x12,0x43,0x09,0xed,0x54,0x0f,0xfd, ++0xec,0x54,0xf0,0xfc,0x90,0x91,0x88,0x12,0x2a,0x7f,0x90,0x91,0x88,0x12,0x43,0x09, ++0xed,0x44,0x10,0xfd,0xec,0x44,0x01,0xfc,0x90,0x91,0x88,0x12,0x2a,0x7f,0x90,0x91, ++0x88,0x12,0x43,0x09,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0x0c,0x7e,0x09,0x12,0x2f, ++0xd9,0x7f,0x04,0x7e,0x08,0x12,0x27,0xde,0x90,0x91,0x88,0x12,0x2a,0x7f,0x90,0x91, ++0x88,0x12,0x43,0x09,0xef,0x54,0xf0,0xff,0xec,0x90,0x91,0x88,0x12,0x2a,0x7f,0x90, ++0x91,0x88,0x12,0x43,0x09,0xef,0x44,0x01,0xff,0xec,0x90,0x91,0x88,0x12,0x2a,0x7f, ++0x90,0x91,0x88,0x12,0x43,0x09,0x90,0x80,0x85,0x12,0x2a,0x7f,0x7f,0x04,0x7e,0x08, ++0x12,0x2f,0xd9,0xe4,0x90,0x90,0xe8,0xf0,0x22,0xd3,0x10,0xaf,0x01,0xc3,0xc0,0xd0, ++0x90,0x91,0xa0,0xef,0xf0,0xd3,0x94,0x07,0x50,0x47,0xe0,0xff,0x74,0x01,0xa8,0x07, ++0x08,0x80,0x02,0xc3,0x33,0xd8,0xfc,0xf4,0xff,0x90,0x00,0x46,0xe0,0x5f,0xf0,0x12, ++0x4c,0xa0,0x90,0x91,0xa0,0xe0,0xfd,0x74,0x01,0x7e,0x00,0xa8,0x05,0x08,0x80,0x05, ++0xc3,0x33,0xce,0x33,0xce,0xd8,0xf9,0xff,0x90,0x00,0x44,0xe0,0xfb,0xe4,0xfe,0xef, ++0x5b,0xa8,0x05,0x08,0x80,0x06,0xce,0xa2,0xe7,0x13,0xce,0x13,0xd8,0xf8,0xff,0x80, ++0x44,0x90,0x91,0xa0,0xe0,0x24,0xf8,0xf0,0xe0,0xff,0x74,0x01,0xa8,0x07,0x08,0x80, ++0x02,0xc3,0x33,0xd8,0xfc,0x12,0x4c,0x98,0x90,0x91,0xa0,0xe0,0xfd,0x74,0x01,0x7e, ++0x00,0xa8,0x05,0x08,0x80,0x05,0xc3,0x33,0xce,0x33,0xce,0xd8,0xf9,0xff,0x90,0x00, ++0x42,0xe0,0xfb,0xe4,0xfe,0xef,0x5b,0xa8,0x05,0x08,0x80,0x06,0xce,0xa2,0xe7,0x13, ++0xce,0x13,0xd8,0xf8,0xff,0xd0,0xd0,0x92,0xaf,0x22,0xe4,0xfd,0x7f,0x45,0x12,0x4d, ++0xa8,0x90,0x04,0xfd,0xe4,0xf0,0xa3,0xf0,0x90,0x90,0xf7,0xf0,0x90,0x90,0xfd,0xf0, ++0x90,0x91,0x00,0xf0,0x90,0x90,0xfe,0xf0,0x90,0x91,0x01,0xf0,0x90,0x90,0xff,0xf0, ++0x90,0x91,0x02,0xf0,0x90,0x90,0xe9,0x04,0xf0,0xe4,0xa3,0xf0,0xa3,0xf0,0xa3,0xf0, ++0x90,0x90,0xee,0xf0,0x90,0x90,0xf3,0xf0,0x90,0x90,0xf5,0xf0,0x90,0x91,0x07,0xf0, ++0x90,0x90,0xf8,0xf0,0x90,0x90,0xf4,0xf0,0x90,0x90,0xed,0xf0,0x90,0x00,0x51,0xe0, ++0x44,0xc0,0xfd,0x7f,0x51,0x02,0x4d,0xa8,0x90,0x91,0x07,0xe0,0x64,0x01,0x60,0x08, ++0x90,0x90,0xf5,0xe0,0x60,0x02,0x01,0xdf,0x90,0x90,0xe9,0xe0,0xc3,0x94,0xff,0x50, ++0x05,0xe0,0x04,0xf0,0x80,0x3b,0x90,0x90,0xea,0xe0,0xc3,0x94,0xff,0x50,0x06,0xe0, ++0x04,0xf0,0xe4,0x80,0x28,0x90,0x90,0xeb,0xe0,0xc3,0x94,0xff,0x50,0x0a,0xe0,0x04, ++0xf0,0xe4,0x90,0x90,0xea,0xf0,0x80,0x15,0x90,0x90,0xec,0xe0,0xc3,0x94,0xff,0x50, ++0x10,0xe0,0x04,0xf0,0xe4,0x90,0x90,0xeb,0xf0,0x90,0x90,0xea,0xf0,0x90,0x90,0xe9, ++0xf0,0x90,0x00,0x44,0xe0,0x54,0x0c,0x60,0x76,0xe0,0x30,0xe2,0x32,0x90,0x90,0xfd, ++0xe0,0xc3,0x94,0xff,0x50,0x05,0xe0,0x04,0xf0,0x80,0x24,0x90,0x90,0xfe,0xe0,0xc3, ++0x94,0xff,0x50,0x06,0xe0,0x04,0xf0,0xe4,0x80,0x11,0x90,0x90,0xff,0xe0,0xc3,0x94, ++0xff,0x50,0x0c,0xe0,0x04,0xf0,0xe4,0x90,0x90,0xfe,0xf0,0x90,0x90,0xfd,0xf0,0x90, ++0x00,0x44,0xe0,0x30,0xe3,0x32,0x90,0x91,0x00,0xe0,0xc3,0x94,0xff,0x50,0x05,0xe0, ++0x04,0xf0,0x80,0x24,0x90,0x91,0x01,0xe0,0xc3,0x94,0xff,0x50,0x06,0xe0,0x04,0xf0, ++0xe4,0x80,0x11,0x90,0x91,0x02,0xe0,0xc3,0x94,0xff,0x50,0x0c,0xe0,0x04,0xf0,0xe4, ++0x90,0x91,0x01,0xf0,0x90,0x91,0x00,0xf0,0x90,0x04,0xfd,0xe0,0x44,0x01,0xf0,0x22, ++0xe5,0x6e,0x30,0xe3,0x04,0xe4,0xff,0x80,0x02,0x7f,0x01,0x02,0x47,0xc9,0x90,0x91, ++0x53,0xe0,0x30,0xe0,0x49,0xe5,0x6d,0x64,0x01,0x70,0x43,0x90,0x91,0x52,0xe0,0x04, ++0xf0,0xe5,0x70,0x64,0x03,0x60,0x05,0xe5,0x70,0xb4,0x06,0x0d,0x90,0x91,0x52,0xe0, ++0xff,0x74,0x01,0xd3,0x9f,0x50,0x14,0x80,0x07,0x90,0x91,0x52,0xe0,0xb4,0x0a,0x0b, ++0x90,0x91,0x55,0xe0,0x04,0xf0,0xe4,0x90,0x91,0x52,0xf0,0x90,0x91,0x55,0xe0,0xff, ++0x90,0x91,0x54,0xe0,0xb5,0x07,0x07,0x11,0xe0,0xe4,0x90,0x91,0x55,0xf0,0x22,0x90, ++0x06,0x90,0xe0,0x44,0x01,0xf0,0x90,0x91,0x61,0xe0,0x30,0xe0,0x3c,0x90,0x91,0x5f, ++0xe0,0xff,0x90,0x91,0x5e,0xe0,0xfe,0xc4,0x13,0x54,0x01,0xfd,0x12,0x4c,0xb0,0x90, ++0x91,0x60,0xe0,0x75,0xf0,0x20,0xa4,0xff,0xae,0xf0,0x12,0x37,0x54,0x90,0x91,0x5e, ++0xe0,0xc4,0x13,0x54,0x07,0x30,0xe0,0x07,0xa3,0xe0,0xff,0xe4,0xfd,0x80,0x07,0x90, ++0x91,0x5f,0xe0,0xff,0x7d,0x01,0x12,0x4c,0xb0,0x22,0xd3,0x10,0xaf,0x01,0xc3,0xc0, ++0xd0,0xe4,0x90,0x91,0x19,0xf0,0xa3,0x74,0x08,0xf0,0xa3,0xf0,0xe4,0xa3,0xf0,0x90, ++0x01,0x1f,0xe0,0xfe,0x90,0x01,0x1e,0xe0,0x7c,0x00,0x24,0x00,0xff,0xec,0x3e,0x90, ++0x91,0x11,0xf0,0xa3,0xef,0xf0,0x90,0x02,0x87,0xe0,0x90,0x91,0x18,0xf0,0x90,0x91, ++0x56,0xe0,0x20,0xe0,0x02,0x61,0xb7,0xe4,0x90,0x91,0x17,0xf0,0x90,0x91,0x18,0xe0, ++0xff,0x90,0x91,0x17,0xe0,0xc3,0x9f,0x40,0x02,0x61,0xb7,0x90,0x91,0x11,0xe0,0xfc, ++0xa3,0xe0,0xfd,0xec,0xff,0x90,0xfd,0x11,0xf0,0x90,0x91,0x1c,0xef,0xf0,0x74,0x02, ++0x2d,0xf5,0x82,0xe4,0x34,0xfb,0xf5,0x83,0xe0,0x54,0x0f,0xfc,0x33,0x33,0x33,0x54, ++0xf8,0xff,0xed,0x24,0x18,0x2f,0x90,0x91,0x15,0xf0,0xe0,0x24,0x00,0xf5,0x82,0xe4, ++0x34,0xfb,0xf5,0x83,0xe0,0x54,0xfc,0x90,0x91,0x16,0xf0,0x74,0x01,0x2d,0xf5,0x82, ++0xe4,0x34,0xfb,0xf5,0x83,0xe0,0xfe,0x74,0x00,0x2d,0xf5,0x82,0xe4,0x34,0xfb,0xf5, ++0x83,0xe0,0x7a,0x00,0x24,0x00,0xff,0xea,0x3e,0x54,0x3f,0xab,0x07,0xfa,0x90,0x91, ++0x13,0xf0,0xa3,0xeb,0xf0,0xaf,0x04,0xef,0x75,0xf0,0x08,0xa4,0x24,0x18,0xff,0xe4, ++0x35,0xf0,0xfe,0xef,0x2b,0xfb,0xee,0x3a,0xfa,0x90,0x91,0x5a,0xe0,0xfe,0xa3,0xe0, ++0xff,0xad,0x03,0xac,0x02,0x12,0x45,0x09,0xaa,0x06,0xab,0x07,0x90,0x91,0x15,0xe0, ++0x24,0x00,0xf5,0x82,0xe4,0x34,0xfb,0xf5,0x83,0xe0,0x30,0xe7,0x08,0x90,0x91,0x19, ++0x74,0x02,0xf0,0x80,0x05,0xe4,0x90,0x91,0x19,0xf0,0xaf,0x03,0x90,0x91,0x11,0xea, ++0x8f,0xf0,0x12,0x42,0x81,0x90,0x91,0x5c,0xe0,0xfe,0xa3,0xe0,0xff,0x90,0x91,0x11, ++0xe0,0xfc,0xa3,0xe0,0xfd,0xd3,0x9f,0xec,0x9e,0x40,0x1b,0x90,0x91,0x5d,0xe0,0x24, ++0x01,0xff,0x90,0x91,0x5c,0xe0,0x34,0x00,0xfe,0xc3,0xed,0x9f,0xff,0xec,0x9e,0x90, ++0x91,0x11,0xf0,0xa3,0xef,0xf0,0x90,0x91,0x16,0xe0,0xff,0x24,0x40,0x60,0x04,0x24, ++0x20,0x70,0x27,0x90,0x91,0x5e,0xe0,0xfe,0xc4,0x13,0x13,0x13,0x54,0x01,0x20,0xe0, ++0x02,0x61,0x8f,0xef,0x90,0x00,0x81,0xb4,0xa0,0x05,0xe0,0x44,0x04,0x80,0x03,0xe0, ++0x44,0x08,0xfd,0x7f,0x81,0x12,0x4d,0xa8,0x61,0x88,0x90,0x91,0x5e,0xe0,0xc4,0x13, ++0x13,0x54,0x03,0x20,0xe0,0x02,0x61,0x8f,0x90,0x91,0x15,0xe0,0xff,0x24,0x00,0xf5, ++0x82,0xe4,0x34,0xfb,0xf5,0x83,0xe0,0x54,0x0c,0x64,0x08,0x70,0x72,0x90,0x91,0x19, ++0xe0,0xfe,0xef,0x2e,0xff,0xa3,0xe0,0x2f,0xff,0x24,0x1e,0xf5,0x82,0xe4,0x34,0xfb, ++0xf5,0x83,0xe0,0x64,0x88,0x70,0x58,0x74,0x1f,0x2f,0xf5,0x82,0xe4,0x34,0xfb,0xf5, ++0x83,0xe0,0x64,0x8e,0x70,0x49,0x90,0x91,0x19,0xe0,0xff,0x90,0x91,0x15,0xe0,0x2f, ++0xff,0x90,0x91,0x1a,0xe0,0x2f,0xff,0xa3,0xe0,0x2f,0xff,0x24,0x19,0xf5,0x82,0xe4, ++0x34,0xfb,0xf5,0x83,0xe0,0x64,0x03,0x70,0x26,0x74,0x1e,0x2f,0xf5,0x82,0xe4,0x34, ++0xfb,0xf5,0x83,0xe0,0x90,0x00,0x81,0x30,0xe3,0x05,0xe0,0x44,0x01,0x80,0x03,0xe0, ++0x44,0x02,0xfd,0x7f,0x81,0x12,0x4d,0xa8,0x90,0x91,0x56,0xe0,0x44,0x80,0xf0,0x90, ++0x91,0x56,0xe0,0xff,0xc4,0x13,0x13,0x13,0x54,0x01,0x30,0xe0,0x02,0x31,0x3f,0x71, ++0xbc,0xbf,0x01,0x13,0x90,0x91,0x11,0xe0,0xfe,0xa3,0xe0,0xff,0x12,0x44,0xb5,0x90, ++0x91,0x17,0xe0,0x04,0xf0,0x21,0xcc,0xd0,0xd0,0x92,0xaf,0x22,0x90,0x91,0x56,0xe0, ++0xc4,0x13,0x13,0x13,0x54,0x01,0x30,0xe0,0x11,0xe0,0x44,0x80,0xf0,0x90,0x91,0x5e, ++0xe0,0xc4,0x54,0x0f,0x20,0xe0,0x03,0x7f,0x00,0x22,0x7f,0x01,0x22,0x8f,0x1f,0xe4, ++0x90,0x91,0x22,0xf0,0xe5,0x1f,0x14,0xfe,0x90,0x91,0x22,0xe0,0xff,0xc3,0x9e,0x50, ++0x0e,0xef,0x04,0xfd,0x12,0x34,0xb7,0x90,0x91,0x22,0xe0,0x04,0xf0,0x80,0xe5,0xe5, ++0x1f,0x14,0xff,0x7d,0xff,0x12,0x34,0xb7,0x90,0x91,0x22,0xe5,0x1f,0xf0,0x90,0x91, ++0x22,0xe0,0xc3,0x94,0xff,0x50,0x0f,0xe0,0xff,0x04,0xfd,0x12,0x34,0xb7,0x90,0x91, ++0x22,0xe0,0x04,0xf0,0x80,0xe8,0xad,0x1f,0x7f,0xff,0x02,0x34,0xb7,0xc3,0xee,0x94, ++0x01,0x40,0x0a,0x0d,0xed,0x13,0x90,0xfd,0x10,0xf0,0xe4,0x2f,0xff,0x22,0xc3,0xee, ++0x94,0x01,0x40,0x1e,0x90,0xfd,0x11,0xe0,0xb5,0x05,0x14,0x90,0x01,0x17,0xe0,0xb5, ++0x05,0x07,0x90,0xfd,0x11,0xe4,0xf0,0x80,0x06,0xed,0x04,0x90,0xfd,0x11,0xf0,0xe4, ++0x2f,0xff,0x22,0x00,0x18,0x58,}; ++ ++ ++ ++ ++ ++ ++ +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/hal/rtl8192c/usb/rtl8192cu_led.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/hal/rtl8192c/usb/rtl8192cu_led.c 2013-07-26 19:36:06.000000000 +0000 +@@ -0,0 +1,2668 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ++******************************************************************************/ ++ ++#include "drv_types.h" ++#include "rtl8192c_hal.h" ++ ++//================================================================================ ++// Constant. ++//================================================================================ ++ ++// ++// Default LED behavior. ++// ++#define LED_BLINK_NORMAL_INTERVAL 100 ++#define LED_BLINK_SLOWLY_INTERVAL 200 ++#define LED_BLINK_LONG_INTERVAL 400 ++ ++#define LED_BLINK_NO_LINK_INTERVAL_ALPHA 1000 ++#define LED_BLINK_LINK_INTERVAL_ALPHA 500 //500 ++#define LED_BLINK_SCAN_INTERVAL_ALPHA 180 //150 ++#define LED_BLINK_FASTER_INTERVAL_ALPHA 50 ++#define LED_BLINK_WPS_SUCESS_INTERVAL_ALPHA 5000 ++ ++//================================================================================ ++// LED object. ++//================================================================================ ++ ++ ++//================================================================================ ++// Prototype of protected function. ++//================================================================================ ++ ++ ++static void ++BlinkTimerCallback( ++ unsigned long data ++ ); ++ ++static void ++BlinkWorkItemCallback( ++ struct work_struct *work ++ ); ++ ++// ++// Description: ++// Reset blinking status of LED_871x object. ++// ++static void ++ResetLedStatus(PLED_871x pLed) { ++ pLed->CurrLedState = LED_OFF; // Current LED state. ++ pLed->bLedOn = _FALSE; // true if LED is ON, false if LED is OFF. ++ ++ pLed->bLedBlinkInProgress = _FALSE; // true if it is blinking, false o.w.. ++ pLed->bLedNoLinkBlinkInProgress = _FALSE; ++ pLed->bLedLinkBlinkInProgress = _FALSE; ++ pLed->bLedStartToLinkBlinkInProgress = _FALSE; ++ pLed->bLedScanBlinkInProgress = _FALSE; ++ pLed->bLedWPSBlinkInProgress = _FALSE; ++ pLed->BlinkTimes = 0; // Number of times to toggle led state for blinking. ++ pLed->BlinkingLedState = LED_UNKNOWN; // Next state for blinking, either LED_ON or LED_OFF are. ++} ++ ++//================================================================================ ++// LED_819xUsb routines. ++//================================================================================ ++ ++// ++// Description: ++// Initialize an LED_871x object. ++// ++static void ++InitLed871x( ++ _adapter *padapter, ++ PLED_871x pLed, ++ LED_PIN_871x LedPin ++ ) ++{ ++ pLed->padapter = padapter; ++ pLed->LedPin = LedPin; ++ ++ ResetLedStatus(pLed); ++ ++ _init_timer(&(pLed->BlinkTimer), padapter->pnetdev, BlinkTimerCallback, pLed); ++ _init_workitem(&(pLed->BlinkWorkItem), BlinkWorkItemCallback, pLed); ++} ++ ++ ++// ++// Description: ++// DeInitialize an LED_871x object. ++// ++static void ++DeInitLed871x( ++ PLED_871x pLed ++ ) ++{ ++ _cancel_timer_ex(&(pLed->BlinkTimer)); ++ ResetLedStatus(pLed); ++} ++ ++// ++// Description: ++// Turn on LED according to LedPin specified. ++// ++static void ++SwLedOn( ++ _adapter *padapter, ++ PLED_871x pLed ++) ++{ ++ u8 LedCfg; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); ++ ++ if( (padapter->bSurpriseRemoved == _TRUE) || ( padapter->bDriverStopped == _TRUE)) ++ { ++ return; ++ } ++ ++ if( (BOARD_MINICARD == pHalData->BoardType )|| ++ (BOARD_USB_SOLO == pHalData->BoardType)|| ++ (BOARD_USB_COMBO == pHalData->BoardType)) ++ { ++ LedCfg = rtw_read8(padapter, REG_LEDCFG2); ++ switch(pLed->LedPin) ++ { ++ case LED_PIN_GPIO0: ++ break; ++ ++ case LED_PIN_LED0: ++ rtw_write8(padapter, REG_LEDCFG2, (LedCfg&0xf0)|BIT5|BIT6); // SW control led0 on. ++ break; ++ ++ case LED_PIN_LED1: ++ rtw_write8(padapter, REG_LEDCFG2, (LedCfg&0x0f)|BIT5); // SW control led1 on. ++ break; ++ ++ default: ++ break; ++ ++ } ++ } ++ else ++ { ++ switch(pLed->LedPin) ++ { ++ case LED_PIN_GPIO0: ++ break; ++ ++ case LED_PIN_LED0: ++#ifdef CONFIG_SW_ANTENNA_DIVERSITY ++ if(pHalData->AntDivCfg) ++ { ++ LedCfg = rtw_read8(padapter, REG_LEDCFG2); ++ rtw_write8(padapter, REG_LEDCFG2, (LedCfg&0xe0)|BIT7|BIT6|BIT5); // SW control led0 on. ++ //RT_TRACE(COMP_LED, DBG_LOUD, ("SwLedOn LED0 0x%x\n", PlatformEFIORead4Byte(Adapter, REG_LEDCFG2))); ++ } ++ else ++#endif ++ { ++ LedCfg = rtw_read8(padapter, REG_LEDCFG0); ++ rtw_write8(padapter,REG_LEDCFG0, LedCfg&0x70); // SW control led0 on. ++ //RT_TRACE(COMP_LED, DBG_LOUD, ("SwLedOn LED0 0x%lx\n", PlatformEFIORead4Byte(Adapter, REG_LEDCFG0))); ++ } ++ break; ++ ++ case LED_PIN_LED1: ++ LedCfg = rtw_read8(padapter,(REG_LEDCFG1)); ++ rtw_write8(padapter,(REG_LEDCFG1), LedCfg&0x70); // SW control led1 on. ++ //RT_TRACE(COMP_LED, DBG_LOUD, ("SwLedOn LED1 0x%lx\n", PlatformEFIORead4Byte(Adapter, REG_LEDCFG0))); ++ ++ break; ++ ++ default: ++ break; ++ } ++ } ++ pLed->bLedOn = _TRUE; ++ ++} ++ ++ ++// ++// Description: ++// Turn off LED according to LedPin specified. ++// ++static void ++SwLedOff( ++ _adapter *padapter, ++ PLED_871x pLed ++) ++{ ++ u8 LedCfg; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); ++ ++ if((padapter->bSurpriseRemoved == _TRUE) || ( padapter->bDriverStopped == _TRUE)) ++ { ++ goto exit; ++ } ++ ++ if( (BOARD_MINICARD == pHalData->BoardType )|| ++ (BOARD_USB_SOLO == pHalData->BoardType)|| ++ (BOARD_USB_COMBO == pHalData->BoardType)) ++ { ++ LedCfg = rtw_read8(padapter, REG_LEDCFG2);//0x4E ++ ++ switch(pLed->LedPin) ++ { ++ ++ case LED_PIN_GPIO0: ++ break; ++ ++ case LED_PIN_LED0: ++ if(BOARD_USB_COMBO == pHalData->BoardType) ++ { ++ LedCfg &= 0x90; // Set to software control. ++ rtw_write8(padapter, REG_LEDCFG2, (LedCfg|BIT3)); ++ LedCfg = rtw_read8(padapter, REG_MAC_PINMUX_CFG); ++ LedCfg &= 0xFE; ++ rtw_write8(padapter, REG_MAC_PINMUX_CFG, LedCfg); ++ } ++ else ++ { ++ LedCfg &= 0xf0; // Set to software control. ++ if(pHalData->bLedOpenDrain == _TRUE) // Open-drain arrangement for controlling the LED ++ rtw_write8(padapter, REG_LEDCFG2, (LedCfg|BIT1|BIT5|BIT6)); ++ else ++ rtw_write8(padapter, REG_LEDCFG2, (LedCfg|BIT3|BIT5|BIT6)); ++ } ++ break; ++ ++ case LED_PIN_LED1: ++ LedCfg &= 0x0f; // Set to software control. ++ rtw_write8(padapter, REG_LEDCFG2, (LedCfg|BIT3)); ++ break; ++ ++ default: ++ break; ++ } ++ } ++ else ++ { ++ switch(pLed->LedPin) ++ { ++ case LED_PIN_GPIO0: ++ break; ++ ++ case LED_PIN_LED0: ++#ifdef CONFIG_SW_ANTENNA_DIVERSITY ++ if(pHalData->AntDivCfg) ++ { ++ LedCfg = rtw_read8(padapter, REG_LEDCFG2); ++ LedCfg &= 0xe0; // Set to software control. ++ rtw_write8(padapter, REG_LEDCFG2, (LedCfg|BIT3|BIT7|BIT6|BIT5)); ++ //RT_TRACE(COMP_LED, DBG_LOUD, ("SwLedOff LED0 0x%x\n", PlatformEFIORead4Byte(Adapter, REG_LEDCFG2))); ++ } ++ else ++#endif ++ { ++ LedCfg = rtw_read8(padapter, REG_LEDCFG0); ++ LedCfg &= 0x70; // Set to software control. ++ rtw_write8(padapter, REG_LEDCFG0, (LedCfg|BIT3)); ++ //RT_TRACE(COMP_LED, DBG_LOUD, ("SwLedOff LED0 0x%lx\n", PlatformEFIORead4Byte(Adapter, REG_LEDCFG0))); ++ } ++ break; ++ ++ case LED_PIN_LED1: ++ LedCfg = rtw_read8(padapter, (REG_LEDCFG1)); ++ LedCfg &= 0x70; // Set to software control. ++ rtw_write8(padapter, (REG_LEDCFG1), (LedCfg|BIT3)); ++ //RT_TRACE(COMP_LED, DBG_LOUD, ("SwLedOff LED1 0x%lx\n", PlatformEFIORead4Byte(Adapter, REG_LEDCFG0))); ++ break; ++ ++ default: ++ break; ++ } ++ } ++ ++exit: ++ pLed->bLedOn = _FALSE; ++ ++} ++ ++//================================================================================ ++// Interface to manipulate LED objects. ++//================================================================================ ++ ++ ++// ++// Description: ++// Implementation of LED blinking behavior. ++// It toggle off LED and schedule corresponding timer if necessary. ++// ++static void ++SwLedBlink( ++ PLED_871x pLed ++ ) ++{ ++ _adapter *padapter = pLed->padapter; ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ u8 bStopBlinking = _FALSE; ++ ++ // Change LED according to BlinkingLedState specified. ++ if( pLed->BlinkingLedState == LED_ON ) ++ { ++ SwLedOn(padapter, pLed); ++ RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("Blinktimes (%d): turn on\n", pLed->BlinkTimes)); ++ } ++ else ++ { ++ SwLedOff(padapter, pLed); ++ RT_TRACE(_module_rtl8712_led_c_,_drv_info_,( "Blinktimes (%d): turn off\n", pLed->BlinkTimes)); ++ } ++ ++ // Determine if we shall change LED state again. ++ pLed->BlinkTimes--; ++ switch(pLed->CurrLedState) ++ { ++ ++ case LED_BLINK_NORMAL: ++ if(pLed->BlinkTimes == 0) ++ { ++ bStopBlinking = _TRUE; ++ } ++ break; ++ ++ case LED_BLINK_StartToBlink: ++ if( check_fwstate(pmlmepriv, _FW_LINKED) && check_fwstate(pmlmepriv, WIFI_STATION_STATE) ) ++ { ++ bStopBlinking = _TRUE; ++ } ++ if( check_fwstate(pmlmepriv, _FW_LINKED) && ++ (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) || check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE)) ) ++ { ++ bStopBlinking = _TRUE; ++ } ++ else if(pLed->BlinkTimes == 0) ++ { ++ bStopBlinking = _TRUE; ++ } ++ break; ++ ++ case LED_BLINK_WPS: ++ if( pLed->BlinkTimes == 0 ) ++ { ++ bStopBlinking = _TRUE; ++ } ++ break; ++ ++ ++ default: ++ bStopBlinking = _TRUE; ++ break; ++ ++ } ++ ++ if(bStopBlinking) ++ { ++ //if( padapter->pwrctrlpriv.cpwm >= PS_STATE_S2) ++ if(0) ++ { ++ SwLedOff(padapter, pLed); ++ } ++ else if( (check_fwstate(pmlmepriv, _FW_LINKED)== _TRUE) && (pLed->bLedOn == _FALSE)) ++ { ++ SwLedOn(padapter, pLed); ++ } ++ else if( (check_fwstate(pmlmepriv, _FW_LINKED)== _TRUE) && pLed->bLedOn == _TRUE) ++ { ++ SwLedOff(padapter, pLed); ++ } ++ ++ pLed->BlinkTimes = 0; ++ pLed->bLedBlinkInProgress = _FALSE; ++ } ++ else ++ { ++ // Assign LED state to toggle. ++ if( pLed->BlinkingLedState == LED_ON ) ++ pLed->BlinkingLedState = LED_OFF; ++ else ++ pLed->BlinkingLedState = LED_ON; ++ ++ // Schedule a timer to toggle LED state. ++ switch( pLed->CurrLedState ) ++ { ++ case LED_BLINK_NORMAL: ++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_NORMAL_INTERVAL); ++ break; ++ ++ case LED_BLINK_SLOWLY: ++ case LED_BLINK_StartToBlink: ++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_SLOWLY_INTERVAL); ++ break; ++ ++ case LED_BLINK_WPS: ++ { ++ if( pLed->BlinkingLedState == LED_ON ) ++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_LONG_INTERVAL); ++ else ++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_LONG_INTERVAL); ++ } ++ break; ++ ++ default: ++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_SLOWLY_INTERVAL); ++ break; ++ } ++ } ++} ++ ++ ++static void ++SwLedBlink1( ++ PLED_871x pLed ++ ) ++{ ++ _adapter *padapter = pLed->padapter; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); ++ struct led_priv *ledpriv = &(padapter->ledpriv); ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ PLED_871x pLed1 = &(ledpriv->SwLed1); ++ u8 bStopBlinking = _FALSE; ++ ++ if(pHalData->EEPROMCustomerID == RT_CID_819x_CAMEO) ++ pLed = &(ledpriv->SwLed1); ++ ++ // Change LED according to BlinkingLedState specified. ++ if( pLed->BlinkingLedState == LED_ON ) ++ { ++ SwLedOn(padapter, pLed); ++ RT_TRACE(_module_rtl8712_led_c_,_drv_info_,( "Blinktimes (%d): turn on\n", pLed->BlinkTimes)); ++ } ++ else ++ { ++ SwLedOff(padapter, pLed); ++ RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("Blinktimes (%d): turn off\n", pLed->BlinkTimes)); ++ } ++ ++ ++ if(pHalData->EEPROMCustomerID == RT_CID_DEFAULT) ++ { ++ if(check_fwstate(pmlmepriv, _FW_LINKED)== _TRUE) ++ { ++ if(!pLed1->bSWLedCtrl) ++ { ++ SwLedOn(padapter, pLed1); ++ pLed1->bSWLedCtrl = _TRUE; ++ } ++ else if(!pLed1->bLedOn) ++ SwLedOn(padapter, pLed1); ++ RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("Blinktimes (): turn on pLed1\n")); ++ } ++ else ++ { ++ if(!pLed1->bSWLedCtrl) ++ { ++ SwLedOff(padapter, pLed1); ++ pLed1->bSWLedCtrl = _TRUE; ++ } ++ else if(pLed1->bLedOn) ++ SwLedOff(padapter, pLed1); ++ RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("Blinktimes (): turn off pLed1\n")); ++ } ++ } ++ ++ ++ if( padapter->pwrctrlpriv.rf_pwrstate != rf_on ) ++ { ++ SwLedOff(padapter, pLed); ++ ResetLedStatus(pLed); ++ return; ++ } ++ ++ ++ switch(pLed->CurrLedState) ++ { ++ case LED_BLINK_SLOWLY: ++ if( pLed->bLedOn ) ++ pLed->BlinkingLedState = LED_OFF; ++ else ++ pLed->BlinkingLedState = LED_ON; ++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_NO_LINK_INTERVAL_ALPHA); ++ break; ++ ++ case LED_BLINK_NORMAL: ++ if( pLed->bLedOn ) ++ pLed->BlinkingLedState = LED_OFF; ++ else ++ pLed->BlinkingLedState = LED_ON; ++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_LINK_INTERVAL_ALPHA); ++ break; ++ ++ case LED_SCAN_BLINK: ++ pLed->BlinkTimes--; ++ if( pLed->BlinkTimes == 0 ) ++ { ++ bStopBlinking = _TRUE; ++ } ++ ++ if(bStopBlinking) ++ { ++ if(check_fwstate(pmlmepriv, _FW_LINKED)== _TRUE) ++ { ++ pLed->bLedLinkBlinkInProgress = _TRUE; ++ pLed->CurrLedState = LED_BLINK_NORMAL; ++ if( pLed->bLedOn ) ++ pLed->BlinkingLedState = LED_OFF; ++ else ++ pLed->BlinkingLedState = LED_ON; ++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_LINK_INTERVAL_ALPHA); ++ RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("CurrLedState %d\n", pLed->CurrLedState)); ++ ++ } ++ else if(check_fwstate(pmlmepriv, _FW_LINKED)== _FALSE) ++ { ++ pLed->bLedNoLinkBlinkInProgress = _TRUE; ++ pLed->CurrLedState = LED_BLINK_SLOWLY; ++ if( pLed->bLedOn ) ++ pLed->BlinkingLedState = LED_OFF; ++ else ++ pLed->BlinkingLedState = LED_ON; ++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_NO_LINK_INTERVAL_ALPHA); ++ RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("CurrLedState %d\n", pLed->CurrLedState)); ++ } ++ pLed->bLedScanBlinkInProgress = _FALSE; ++ } ++ else ++ { ++ if( pLed->bLedOn ) ++ pLed->BlinkingLedState = LED_OFF; ++ else ++ pLed->BlinkingLedState = LED_ON; ++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_SCAN_INTERVAL_ALPHA); ++ } ++ break; ++ ++ case LED_TXRX_BLINK: ++ pLed->BlinkTimes--; ++ if( pLed->BlinkTimes == 0 ) ++ { ++ bStopBlinking = _TRUE; ++ } ++ if(bStopBlinking) ++ { ++ if(check_fwstate(pmlmepriv, _FW_LINKED)== _TRUE) ++ { ++ pLed->bLedLinkBlinkInProgress = _TRUE; ++ pLed->CurrLedState = LED_BLINK_NORMAL; ++ if( pLed->bLedOn ) ++ pLed->BlinkingLedState = LED_OFF; ++ else ++ pLed->BlinkingLedState = LED_ON; ++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_LINK_INTERVAL_ALPHA); ++ RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("CurrLedState %d\n", pLed->CurrLedState)); ++ } ++ else if(check_fwstate(pmlmepriv, _FW_LINKED)== _FALSE) ++ { ++ pLed->bLedNoLinkBlinkInProgress = _TRUE; ++ pLed->CurrLedState = LED_BLINK_SLOWLY; ++ if( pLed->bLedOn ) ++ pLed->BlinkingLedState = LED_OFF; ++ else ++ pLed->BlinkingLedState = LED_ON; ++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_NO_LINK_INTERVAL_ALPHA); ++ RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("CurrLedState %d\n", pLed->CurrLedState)); ++ } ++ pLed->BlinkTimes = 0; ++ pLed->bLedBlinkInProgress = _FALSE; ++ } ++ else ++ { ++ if( pLed->bLedOn ) ++ pLed->BlinkingLedState = LED_OFF; ++ else ++ pLed->BlinkingLedState = LED_ON; ++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_FASTER_INTERVAL_ALPHA); ++ } ++ break; ++ ++ case LED_BLINK_WPS: ++ if( pLed->bLedOn ) ++ pLed->BlinkingLedState = LED_OFF; ++ else ++ pLed->BlinkingLedState = LED_ON; ++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_SCAN_INTERVAL_ALPHA); ++ break; ++ ++ case LED_BLINK_WPS_STOP: //WPS success ++ if(pLed->BlinkingLedState == LED_ON) ++ bStopBlinking = _FALSE; ++ else ++ bStopBlinking = _TRUE; ++ ++ if(bStopBlinking) ++ { ++ pLed->bLedLinkBlinkInProgress = _TRUE; ++ pLed->CurrLedState = LED_BLINK_NORMAL; ++ if( pLed->bLedOn ) ++ pLed->BlinkingLedState = LED_OFF; ++ else ++ pLed->BlinkingLedState = LED_ON; ++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_LINK_INTERVAL_ALPHA); ++ RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("CurrLedState %d\n", pLed->CurrLedState)); ++ ++ pLed->bLedWPSBlinkInProgress = _FALSE; ++ } ++ else ++ { ++ pLed->BlinkingLedState = LED_OFF; ++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_WPS_SUCESS_INTERVAL_ALPHA); ++ } ++ break; ++ ++ default: ++ break; ++ } ++ ++} ++ ++static void ++SwLedBlink2( ++ PLED_871x pLed ++ ) ++{ ++ _adapter *padapter = pLed->padapter; ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ u8 bStopBlinking = _FALSE; ++ ++ // Change LED according to BlinkingLedState specified. ++ if( pLed->BlinkingLedState == LED_ON) ++ { ++ SwLedOn(padapter, pLed); ++ RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("Blinktimes (%d): turn on\n", pLed->BlinkTimes)); ++ } ++ else ++ { ++ SwLedOff(padapter, pLed); ++ RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("Blinktimes (%d): turn off\n", pLed->BlinkTimes)); ++ } ++ ++ switch(pLed->CurrLedState) ++ { ++ case LED_SCAN_BLINK: ++ pLed->BlinkTimes--; ++ if( pLed->BlinkTimes == 0 ) ++ { ++ bStopBlinking = _TRUE; ++ } ++ ++ if(bStopBlinking) ++ { ++ if( padapter->pwrctrlpriv.rf_pwrstate != rf_on ) ++ { ++ SwLedOff(padapter, pLed); ++ } ++ else if(check_fwstate(pmlmepriv, _FW_LINKED)== _TRUE) ++ { ++ pLed->CurrLedState = LED_ON; ++ pLed->BlinkingLedState = LED_ON; ++ SwLedOn(padapter, pLed); ++ RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("stop scan blink CurrLedState %d\n", pLed->CurrLedState)); ++ ++ } ++ else if(check_fwstate(pmlmepriv, _FW_LINKED)== _FALSE) ++ { ++ pLed->CurrLedState = LED_OFF; ++ pLed->BlinkingLedState = LED_OFF; ++ SwLedOff(padapter, pLed); ++ RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("stop scan blink CurrLedState %d\n", pLed->CurrLedState)); ++ } ++ pLed->bLedScanBlinkInProgress = _FALSE; ++ } ++ else ++ { ++ if( padapter->pwrctrlpriv.rf_pwrstate != rf_on ) ++ { ++ SwLedOff(padapter, pLed); ++ } ++ else ++ { ++ if( pLed->bLedOn ) ++ pLed->BlinkingLedState = LED_OFF; ++ else ++ pLed->BlinkingLedState = LED_ON; ++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_SCAN_INTERVAL_ALPHA); ++ } ++ } ++ break; ++ ++ case LED_TXRX_BLINK: ++ pLed->BlinkTimes--; ++ if( pLed->BlinkTimes == 0 ) ++ { ++ bStopBlinking = _TRUE; ++ } ++ if(bStopBlinking) ++ { ++ if( padapter->pwrctrlpriv.rf_pwrstate != rf_on ) ++ { ++ SwLedOff(padapter, pLed); ++ } ++ else if(check_fwstate(pmlmepriv, _FW_LINKED)== _TRUE) ++ { ++ pLed->CurrLedState = LED_ON; ++ pLed->BlinkingLedState = LED_ON; ++ SwLedOn(padapter, pLed); ++ RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("stop CurrLedState %d\n", pLed->CurrLedState)); ++ ++ } ++ else if(check_fwstate(pmlmepriv, _FW_LINKED)== _FALSE) ++ { ++ pLed->CurrLedState = LED_OFF; ++ pLed->BlinkingLedState = LED_OFF; ++ SwLedOff(padapter, pLed); ++ RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("stop CurrLedState %d\n", pLed->CurrLedState)); ++ } ++ pLed->bLedBlinkInProgress = _FALSE; ++ } ++ else ++ { ++ if( padapter->pwrctrlpriv.rf_pwrstate != rf_on ) ++ { ++ SwLedOff(padapter, pLed); ++ } ++ else ++ { ++ if( pLed->bLedOn ) ++ pLed->BlinkingLedState = LED_OFF; ++ else ++ pLed->BlinkingLedState = LED_ON; ++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_FASTER_INTERVAL_ALPHA); ++ } ++ } ++ break; ++ ++ default: ++ break; ++ } ++ ++} ++ ++static void ++SwLedBlink3( ++ PLED_871x pLed ++ ) ++{ ++ _adapter *padapter = pLed->padapter; ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ u8 bStopBlinking = _FALSE; ++ ++ // Change LED according to BlinkingLedState specified. ++ if( pLed->BlinkingLedState == LED_ON ) ++ { ++ SwLedOn(padapter, pLed); ++ RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("Blinktimes (%d): turn on\n", pLed->BlinkTimes)); ++ } ++ else ++ { ++ if(pLed->CurrLedState != LED_BLINK_WPS_STOP) ++ SwLedOff(padapter, pLed); ++ RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("Blinktimes (%d): turn off\n", pLed->BlinkTimes)); ++ } ++ ++ switch(pLed->CurrLedState) ++ { ++ case LED_SCAN_BLINK: ++ pLed->BlinkTimes--; ++ if( pLed->BlinkTimes == 0 ) ++ { ++ bStopBlinking = _TRUE; ++ } ++ ++ if(bStopBlinking) ++ { ++ if( padapter->pwrctrlpriv.rf_pwrstate != rf_on ) ++ { ++ SwLedOff(padapter, pLed); ++ } ++ else if(check_fwstate(pmlmepriv, _FW_LINKED)== _TRUE) ++ { ++ pLed->CurrLedState = LED_ON; ++ pLed->BlinkingLedState = LED_ON; ++ if( !pLed->bLedOn ) ++ SwLedOn(padapter, pLed); ++ ++ RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("CurrLedState %d\n", pLed->CurrLedState)); ++ } ++ else if(check_fwstate(pmlmepriv, _FW_LINKED)== _FALSE) ++ { ++ pLed->CurrLedState = LED_OFF; ++ pLed->BlinkingLedState = LED_OFF; ++ if( pLed->bLedOn ) ++ SwLedOff(padapter, pLed); ++ ++ RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("CurrLedState %d\n", pLed->CurrLedState)); ++ } ++ pLed->bLedScanBlinkInProgress = _FALSE; ++ } ++ else ++ { ++ if( padapter->pwrctrlpriv.rf_pwrstate != rf_on ) ++ { ++ SwLedOff(padapter, pLed); ++ } ++ else ++ { ++ if( pLed->bLedOn ) ++ pLed->BlinkingLedState = LED_OFF; ++ else ++ pLed->BlinkingLedState = LED_ON; ++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_SCAN_INTERVAL_ALPHA); ++ } ++ } ++ break; ++ ++ case LED_TXRX_BLINK: ++ pLed->BlinkTimes--; ++ if( pLed->BlinkTimes == 0 ) ++ { ++ bStopBlinking = _TRUE; ++ } ++ if(bStopBlinking) ++ { ++ if( padapter->pwrctrlpriv.rf_pwrstate != rf_on ) ++ { ++ SwLedOff(padapter, pLed); ++ } ++ else if(check_fwstate(pmlmepriv, _FW_LINKED)== _TRUE) ++ { ++ pLed->CurrLedState = LED_ON; ++ pLed->BlinkingLedState = LED_ON; ++ ++ if( !pLed->bLedOn ) ++ SwLedOn(padapter, pLed); ++ ++ RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("CurrLedState %d\n", pLed->CurrLedState)); ++ } ++ else if(check_fwstate(pmlmepriv, _FW_LINKED)== _FALSE) ++ { ++ pLed->CurrLedState = LED_OFF; ++ pLed->BlinkingLedState = LED_OFF; ++ ++ if( pLed->bLedOn ) ++ SwLedOff(padapter, pLed); ++ ++ ++ RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("CurrLedState %d\n", pLed->CurrLedState)); ++ } ++ pLed->bLedBlinkInProgress = _FALSE; ++ } ++ else ++ { ++ if( padapter->pwrctrlpriv.rf_pwrstate != rf_on ) ++ { ++ SwLedOff(padapter, pLed); ++ } ++ else ++ { ++ if( pLed->bLedOn ) ++ pLed->BlinkingLedState = LED_OFF; ++ else ++ pLed->BlinkingLedState = LED_ON; ++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_FASTER_INTERVAL_ALPHA); ++ } ++ } ++ break; ++ ++ case LED_BLINK_WPS: ++ if( pLed->bLedOn ) ++ pLed->BlinkingLedState = LED_OFF; ++ else ++ pLed->BlinkingLedState = LED_ON; ++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_SCAN_INTERVAL_ALPHA); ++ break; ++ ++ case LED_BLINK_WPS_STOP: //WPS success ++ if(pLed->BlinkingLedState == LED_ON) ++ { ++ pLed->BlinkingLedState = LED_OFF; ++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_WPS_SUCESS_INTERVAL_ALPHA); ++ bStopBlinking = _FALSE; ++ } ++ else ++ { ++ bStopBlinking = _TRUE; ++ } ++ ++ if(bStopBlinking) ++ { ++ if( padapter->pwrctrlpriv.rf_pwrstate != rf_on ) ++ { ++ SwLedOff(padapter, pLed); ++ } ++ else ++ { ++ pLed->CurrLedState = LED_ON; ++ pLed->BlinkingLedState = LED_ON; ++ SwLedOn(padapter, pLed); ++ RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("CurrLedState %d\n", pLed->CurrLedState)); ++ } ++ pLed->bLedWPSBlinkInProgress = _FALSE; ++ } ++ break; ++ ++ ++ default: ++ break; ++ } ++ ++} ++ ++ ++static void ++SwLedBlink4( ++ PLED_871x pLed ++ ) ++{ ++ _adapter *padapter = pLed->padapter; ++ struct led_priv *ledpriv = &(padapter->ledpriv); ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ PLED_871x pLed1 = &(ledpriv->SwLed1); ++ u8 bStopBlinking = _FALSE; ++ ++ // Change LED according to BlinkingLedState specified. ++ if( pLed->BlinkingLedState == LED_ON ) ++ { ++ SwLedOn(padapter, pLed); ++ RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("Blinktimes (%d): turn on\n", pLed->BlinkTimes)); ++ } ++ else ++ { ++ SwLedOff(padapter, pLed); ++ RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("Blinktimes (%d): turn off\n", pLed->BlinkTimes)); ++ } ++ ++ if(!pLed1->bLedWPSBlinkInProgress && pLed1->BlinkingLedState == LED_UNKNOWN) ++ { ++ pLed1->BlinkingLedState = LED_OFF; ++ pLed1->CurrLedState = LED_OFF; ++ SwLedOff(padapter, pLed1); ++ } ++ ++ switch(pLed->CurrLedState) ++ { ++ case LED_BLINK_SLOWLY: ++ if( pLed->bLedOn ) ++ pLed->BlinkingLedState = LED_OFF; ++ else ++ pLed->BlinkingLedState = LED_ON; ++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_NO_LINK_INTERVAL_ALPHA); ++ break; ++ ++ case LED_BLINK_StartToBlink: ++ if( pLed->bLedOn ) ++ { ++ pLed->BlinkingLedState = LED_OFF; ++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_SLOWLY_INTERVAL); ++ } ++ else ++ { ++ pLed->BlinkingLedState = LED_ON; ++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_NORMAL_INTERVAL); ++ } ++ break; ++ ++ case LED_SCAN_BLINK: ++ pLed->BlinkTimes--; ++ if( pLed->BlinkTimes == 0 ) ++ { ++ bStopBlinking = _FALSE; ++ } ++ ++ if(bStopBlinking) ++ { ++ if( padapter->pwrctrlpriv.rf_pwrstate != rf_on && padapter->pwrctrlpriv.rfoff_reason > RF_CHANGE_BY_PS) ++ { ++ SwLedOff(padapter, pLed); ++ } ++ else ++ { ++ pLed->bLedNoLinkBlinkInProgress = _FALSE; ++ pLed->CurrLedState = LED_BLINK_SLOWLY; ++ if( pLed->bLedOn ) ++ pLed->BlinkingLedState = LED_OFF; ++ else ++ pLed->BlinkingLedState = LED_ON; ++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_NO_LINK_INTERVAL_ALPHA); ++ } ++ pLed->bLedScanBlinkInProgress = _FALSE; ++ } ++ else ++ { ++ if( padapter->pwrctrlpriv.rf_pwrstate != rf_on && padapter->pwrctrlpriv.rfoff_reason > RF_CHANGE_BY_PS) ++ { ++ SwLedOff(padapter, pLed); ++ } ++ else ++ { ++ if( pLed->bLedOn ) ++ pLed->BlinkingLedState = LED_OFF; ++ else ++ pLed->BlinkingLedState = LED_ON; ++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_SCAN_INTERVAL_ALPHA); ++ } ++ } ++ break; ++ ++ case LED_TXRX_BLINK: ++ pLed->BlinkTimes--; ++ if( pLed->BlinkTimes == 0 ) ++ { ++ bStopBlinking = _TRUE; ++ } ++ if(bStopBlinking) ++ { ++ if( padapter->pwrctrlpriv.rf_pwrstate != rf_on && padapter->pwrctrlpriv.rfoff_reason > RF_CHANGE_BY_PS) ++ { ++ SwLedOff(padapter, pLed); ++ } ++ else ++ { ++ pLed->bLedNoLinkBlinkInProgress = _TRUE; ++ pLed->CurrLedState = LED_BLINK_SLOWLY; ++ if( pLed->bLedOn ) ++ pLed->BlinkingLedState = LED_OFF; ++ else ++ pLed->BlinkingLedState = LED_ON; ++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_NO_LINK_INTERVAL_ALPHA); ++ } ++ pLed->bLedBlinkInProgress = _FALSE; ++ } ++ else ++ { ++ if( padapter->pwrctrlpriv.rf_pwrstate != rf_on && padapter->pwrctrlpriv.rfoff_reason > RF_CHANGE_BY_PS) ++ { ++ SwLedOff(padapter, pLed); ++ } ++ else ++ { ++ if( pLed->bLedOn ) ++ pLed->BlinkingLedState = LED_OFF; ++ else ++ pLed->BlinkingLedState = LED_ON; ++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_FASTER_INTERVAL_ALPHA); ++ } ++ } ++ break; ++ ++ case LED_BLINK_WPS: ++ if( pLed->bLedOn ) ++ { ++ pLed->BlinkingLedState = LED_OFF; ++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_SLOWLY_INTERVAL); ++ } ++ else ++ { ++ pLed->BlinkingLedState = LED_ON; ++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_NORMAL_INTERVAL); ++ } ++ break; ++ ++ case LED_BLINK_WPS_STOP: //WPS authentication fail ++ if( pLed->bLedOn ) ++ pLed->BlinkingLedState = LED_OFF; ++ else ++ pLed->BlinkingLedState = LED_ON; ++ ++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_NORMAL_INTERVAL); ++ break; ++ ++ case LED_BLINK_WPS_STOP_OVERLAP: //WPS session overlap ++ pLed->BlinkTimes--; ++ if(pLed->BlinkTimes == 0) ++ { ++ if(pLed->bLedOn) ++ { ++ pLed->BlinkTimes = 1; ++ } ++ else ++ { ++ bStopBlinking = _TRUE; ++ } ++ } ++ ++ if(bStopBlinking) ++ { ++ pLed->BlinkTimes = 10; ++ pLed->BlinkingLedState = LED_ON; ++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_LINK_INTERVAL_ALPHA); ++ } ++ else ++ { ++ if( pLed->bLedOn ) ++ pLed->BlinkingLedState = LED_OFF; ++ else ++ pLed->BlinkingLedState = LED_ON; ++ ++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_NORMAL_INTERVAL); ++ } ++ break; ++ ++ ++ default: ++ break; ++ } ++ ++ RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("SwLedBlink4 CurrLedState %d\n", pLed->CurrLedState)); ++ ++ ++} ++ ++static void ++SwLedBlink5( ++ PLED_871x pLed ++ ) ++{ ++ _adapter *padapter = pLed->padapter; ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ u8 bStopBlinking = _FALSE; ++ ++ // Change LED according to BlinkingLedState specified. ++ if( pLed->BlinkingLedState == LED_ON ) ++ { ++ SwLedOn(padapter, pLed); ++ RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("Blinktimes (%d): turn on\n", pLed->BlinkTimes)); ++ } ++ else ++ { ++ SwLedOff(padapter, pLed); ++ RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("Blinktimes (%d): turn off\n", pLed->BlinkTimes)); ++ } ++ ++ switch(pLed->CurrLedState) ++ { ++ case LED_SCAN_BLINK: ++ pLed->BlinkTimes--; ++ if( pLed->BlinkTimes == 0 ) ++ { ++ bStopBlinking = _TRUE; ++ } ++ ++ if(bStopBlinking) ++ { ++ if( padapter->pwrctrlpriv.rf_pwrstate != rf_on && padapter->pwrctrlpriv.rfoff_reason > RF_CHANGE_BY_PS) ++ { ++ pLed->CurrLedState = LED_OFF; ++ pLed->BlinkingLedState = LED_OFF; ++ if(pLed->bLedOn) ++ SwLedOff(padapter, pLed); ++ } ++ else ++ { pLed->CurrLedState = LED_ON; ++ pLed->BlinkingLedState = LED_ON; ++ if(!pLed->bLedOn) ++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_FASTER_INTERVAL_ALPHA); ++ } ++ ++ pLed->bLedScanBlinkInProgress = _FALSE; ++ } ++ else ++ { ++ if( padapter->pwrctrlpriv.rf_pwrstate != rf_on && padapter->pwrctrlpriv.rfoff_reason > RF_CHANGE_BY_PS) ++ { ++ SwLedOff(padapter, pLed); ++ } ++ else ++ { ++ if( pLed->bLedOn ) ++ pLed->BlinkingLedState = LED_OFF; ++ else ++ pLed->BlinkingLedState = LED_ON; ++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_SCAN_INTERVAL_ALPHA); ++ } ++ } ++ break; ++ ++ ++ case LED_TXRX_BLINK: ++ pLed->BlinkTimes--; ++ if( pLed->BlinkTimes == 0 ) ++ { ++ bStopBlinking = _TRUE; ++ } ++ ++ if(bStopBlinking) ++ { ++ if( padapter->pwrctrlpriv.rf_pwrstate != rf_on && padapter->pwrctrlpriv.rfoff_reason > RF_CHANGE_BY_PS) ++ { ++ pLed->CurrLedState = LED_OFF; ++ pLed->BlinkingLedState = LED_OFF; ++ if(pLed->bLedOn) ++ SwLedOff(padapter, pLed); ++ } ++ else ++ { ++ pLed->CurrLedState = LED_ON; ++ pLed->BlinkingLedState = LED_ON; ++ if(!pLed->bLedOn) ++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_FASTER_INTERVAL_ALPHA); ++ } ++ ++ pLed->bLedBlinkInProgress = _FALSE; ++ } ++ else ++ { ++ if( padapter->pwrctrlpriv.rf_pwrstate != rf_on && padapter->pwrctrlpriv.rfoff_reason > RF_CHANGE_BY_PS) ++ { ++ SwLedOff(padapter, pLed); ++ } ++ else ++ { ++ if( pLed->bLedOn ) ++ pLed->BlinkingLedState = LED_OFF; ++ else ++ pLed->BlinkingLedState = LED_ON; ++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_FASTER_INTERVAL_ALPHA); ++ } ++ } ++ break; ++ ++ default: ++ break; ++ } ++ ++ RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("SwLedBlink5 CurrLedState %d\n", pLed->CurrLedState)); ++ ++ ++} ++ ++static void ++SwLedBlink6( ++ PLED_871x pLed ++ ) ++{ ++ _adapter *padapter = pLed->padapter; ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ u8 bStopBlinking = _FALSE; ++ ++ // Change LED according to BlinkingLedState specified. ++ if( pLed->BlinkingLedState == LED_ON ) ++ { ++ SwLedOn(padapter, pLed); ++ RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("Blinktimes (%d): turn on\n", pLed->BlinkTimes)); ++ } ++ else ++ { ++ SwLedOff(padapter, pLed); ++ RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("Blinktimes (%d): turn off\n", pLed->BlinkTimes)); ++ } ++ ++ RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("<==== blink6\n")); ++} ++ ++ ++// ++// Description: ++// Callback function of LED BlinkTimer, ++// it just schedules to corresponding BlinkWorkItem. ++// ++static void ++BlinkTimerCallback( ++ unsigned long data ++ ) ++{ ++ PLED_871x pLed = (PLED_871x)data; ++ _adapter *padapter = pLed->padapter; ++ ++ //DBG_871X("%s\n", __FUNCTION__); ++ ++ if( (padapter->bSurpriseRemoved == _TRUE) || ( padapter->bDriverStopped == _TRUE)) ++ { ++ //DBG_871X("%s bSurpriseRemoved:%d, bDriverStopped:%d\n", __FUNCTION__, padapter->bSurpriseRemoved, padapter->bDriverStopped); ++ return; ++ } ++ ++#ifdef CONFIG_LED_HANDLED_BY_CMD_THREAD ++ rtw_led_blink_cmd(padapter, pLed); ++#else ++ _set_workitem(&(pLed->BlinkWorkItem)); ++#endif ++} ++ ++// ++// Description: ++// Handler function of LED Blinking. ++// We dispatch acture LED blink action according to LedStrategy. ++// ++void BlinkHandler(PLED_871x pLed) ++{ ++ struct led_priv *ledpriv = &(pLed->padapter->ledpriv); ++ _adapter *padapter = pLed->padapter; ++ ++ //DBG_871X("%s (%s:%d)\n",__FUNCTION__, current->comm, current->pid); ++ ++ if( (padapter->bSurpriseRemoved == _TRUE) || ( padapter->bDriverStopped == _TRUE)) ++ { ++ //DBG_871X("%s bSurpriseRemoved:%d, bDriverStopped:%d\n", __FUNCTION__, padapter->bSurpriseRemoved, padapter->bDriverStopped); ++ return; ++ } ++ ++ switch(ledpriv->LedStrategy) ++ { ++ case SW_LED_MODE0: ++ SwLedBlink(pLed); ++ break; ++ ++ case SW_LED_MODE1: ++ SwLedBlink1(pLed); ++ break; ++ ++ case SW_LED_MODE2: ++ SwLedBlink2(pLed); ++ break; ++ ++ case SW_LED_MODE3: ++ SwLedBlink3(pLed); ++ break; ++ ++ case SW_LED_MODE4: ++ SwLedBlink4(pLed); ++ break; ++ ++ case SW_LED_MODE5: ++ SwLedBlink5(pLed); ++ break; ++ ++ case SW_LED_MODE6: ++ SwLedBlink6(pLed); ++ break; ++ ++ default: ++ //RT_TRACE(COMP_LED, DBG_LOUD, ("BlinkWorkItemCallback 0x%x \n", pHalData->LedStrategy)); ++ //SwLedBlink(pLed); ++ break; ++ } ++} ++ ++// ++// Description: ++// Callback function of LED BlinkWorkItem. ++// We dispatch acture LED blink action according to LedStrategy. ++// ++static void BlinkWorkItemCallback(struct work_struct *work) ++{ ++ PLED_871x pLed = container_of(work, LED_871x, BlinkWorkItem); ++ BlinkHandler(pLed); ++} ++ ++ ++ ++//================================================================================ ++// Default LED behavior. ++//================================================================================ ++ ++// ++// Description: ++// Implement each led action for SW_LED_MODE0. ++// This is default strategy. ++// ++static void ++SwLedControlMode0( ++ _adapter *padapter, ++ LED_CTL_MODE LedAction ++) ++{ ++ struct led_priv *ledpriv = &(padapter->ledpriv); ++ PLED_871x pLed = &(ledpriv->SwLed1); ++ ++ // Decide led state ++ switch(LedAction) ++ { ++ case LED_CTL_TX: ++ case LED_CTL_RX: ++ if( pLed->bLedBlinkInProgress == _FALSE ) ++ { ++ pLed->bLedBlinkInProgress = _TRUE; ++ ++ pLed->CurrLedState = LED_BLINK_NORMAL; ++ pLed->BlinkTimes = 2; ++ ++ if( pLed->bLedOn ) ++ pLed->BlinkingLedState = LED_OFF; ++ else ++ pLed->BlinkingLedState = LED_ON; ++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_NORMAL_INTERVAL); ++ } ++ break; ++ ++ case LED_CTL_START_TO_LINK: ++ if( pLed->bLedBlinkInProgress == _FALSE ) ++ { ++ pLed->bLedBlinkInProgress = _TRUE; ++ ++ pLed->CurrLedState = LED_BLINK_StartToBlink; ++ pLed->BlinkTimes = 24; ++ ++ if( pLed->bLedOn ) ++ pLed->BlinkingLedState = LED_OFF; ++ else ++ pLed->BlinkingLedState = LED_ON; ++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_SLOWLY_INTERVAL); ++ } ++ else ++ { ++ pLed->CurrLedState = LED_BLINK_StartToBlink; ++ } ++ break; ++ ++ case LED_CTL_LINK: ++ pLed->CurrLedState = LED_ON; ++ if( pLed->bLedBlinkInProgress == _FALSE ) ++ { ++ SwLedOn(padapter, pLed); ++ } ++ break; ++ ++ case LED_CTL_NO_LINK: ++ pLed->CurrLedState = LED_OFF; ++ if( pLed->bLedBlinkInProgress == _FALSE ) ++ { ++ SwLedOff(padapter, pLed); ++ } ++ break; ++ ++ case LED_CTL_POWER_OFF: ++ pLed->CurrLedState = LED_OFF; ++ if(pLed->bLedBlinkInProgress) ++ { ++ _cancel_timer_ex(&(pLed->BlinkTimer)); ++ pLed->bLedBlinkInProgress = _FALSE; ++ } ++ SwLedOff(padapter, pLed); ++ break; ++ ++ case LED_CTL_START_WPS: ++ if( pLed->bLedBlinkInProgress == _FALSE || pLed->CurrLedState == LED_ON) ++ { ++ pLed->bLedBlinkInProgress = _TRUE; ++ ++ pLed->CurrLedState = LED_BLINK_WPS; ++ pLed->BlinkTimes = 20; ++ ++ if( pLed->bLedOn ) ++ { ++ pLed->BlinkingLedState = LED_OFF; ++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_LONG_INTERVAL); ++ } ++ else ++ { ++ pLed->BlinkingLedState = LED_ON; ++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_LONG_INTERVAL); ++ } ++ } ++ break; ++ ++ case LED_CTL_STOP_WPS: ++ if(pLed->bLedBlinkInProgress) ++ { ++ pLed->CurrLedState = LED_OFF; ++ _cancel_timer_ex(&(pLed->BlinkTimer)); ++ pLed->bLedBlinkInProgress = _FALSE; ++ } ++ break; ++ ++ ++ default: ++ break; ++ } ++ ++ RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("Led %d\n", pLed->CurrLedState)); ++ ++} ++ ++ //ALPHA, added by chiyoko, 20090106 ++static void ++SwLedControlMode1( ++ _adapter *padapter, ++ LED_CTL_MODE LedAction ++) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); ++ struct led_priv *ledpriv = &(padapter->ledpriv); ++ PLED_871x pLed = &(ledpriv->SwLed0); ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ ++ if(pHalData->EEPROMCustomerID == RT_CID_819x_CAMEO) ++ pLed = &(ledpriv->SwLed1); ++ ++ switch(LedAction) ++ { ++ case LED_CTL_POWER_ON: ++ case LED_CTL_START_TO_LINK: ++ case LED_CTL_NO_LINK: ++ if( pLed->bLedNoLinkBlinkInProgress == _FALSE ) ++ { ++ if(pLed->CurrLedState == LED_SCAN_BLINK || IS_LED_WPS_BLINKING(pLed)) ++ { ++ return; ++ } ++ if( pLed->bLedLinkBlinkInProgress == _TRUE ) ++ { ++ _cancel_timer_ex(&(pLed->BlinkTimer)); ++ pLed->bLedLinkBlinkInProgress = _FALSE; ++ } ++ if(pLed->bLedBlinkInProgress ==_TRUE) ++ { ++ _cancel_timer_ex(&(pLed->BlinkTimer)); ++ pLed->bLedBlinkInProgress = _FALSE; ++ } ++ ++ pLed->bLedNoLinkBlinkInProgress = _TRUE; ++ pLed->CurrLedState = LED_BLINK_SLOWLY; ++ if( pLed->bLedOn ) ++ pLed->BlinkingLedState = LED_OFF; ++ else ++ pLed->BlinkingLedState = LED_ON; ++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_NO_LINK_INTERVAL_ALPHA); ++ } ++ break; ++ ++ case LED_CTL_LINK: ++ if( pLed->bLedLinkBlinkInProgress == _FALSE ) ++ { ++ if(pLed->CurrLedState == LED_SCAN_BLINK || IS_LED_WPS_BLINKING(pLed)) ++ { ++ return; ++ } ++ if(pLed->bLedNoLinkBlinkInProgress == _TRUE) ++ { ++ _cancel_timer_ex(&(pLed->BlinkTimer)); ++ pLed->bLedNoLinkBlinkInProgress = _FALSE; ++ } ++ if(pLed->bLedBlinkInProgress ==_TRUE) ++ { ++ _cancel_timer_ex(&(pLed->BlinkTimer)); ++ pLed->bLedBlinkInProgress = _FALSE; ++ } ++ pLed->bLedLinkBlinkInProgress = _TRUE; ++ pLed->CurrLedState = LED_BLINK_NORMAL; ++ if( pLed->bLedOn ) ++ pLed->BlinkingLedState = LED_OFF; ++ else ++ pLed->BlinkingLedState = LED_ON; ++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_LINK_INTERVAL_ALPHA); ++ } ++ break; ++ ++ case LED_CTL_SITE_SURVEY: ++ if((pmlmepriv->LinkDetectInfo.bBusyTraffic) && (check_fwstate(pmlmepriv, _FW_LINKED)== _TRUE)) ++ ; ++ else if(pLed->bLedScanBlinkInProgress ==_FALSE) ++ { ++ if(IS_LED_WPS_BLINKING(pLed)) ++ return; ++ ++ if(pLed->bLedNoLinkBlinkInProgress == _TRUE) ++ { ++ _cancel_timer_ex(&(pLed->BlinkTimer)); ++ pLed->bLedNoLinkBlinkInProgress = _FALSE; ++ } ++ if( pLed->bLedLinkBlinkInProgress == _TRUE ) ++ { ++ _cancel_timer_ex(&(pLed->BlinkTimer)); ++ pLed->bLedLinkBlinkInProgress = _FALSE; ++ } ++ if(pLed->bLedBlinkInProgress ==_TRUE) ++ { ++ _cancel_timer_ex(&(pLed->BlinkTimer)); ++ pLed->bLedBlinkInProgress = _FALSE; ++ } ++ pLed->bLedScanBlinkInProgress = _TRUE; ++ pLed->CurrLedState = LED_SCAN_BLINK; ++ pLed->BlinkTimes = 24; ++ if( pLed->bLedOn ) ++ pLed->BlinkingLedState = LED_OFF; ++ else ++ pLed->BlinkingLedState = LED_ON; ++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_SCAN_INTERVAL_ALPHA); ++ } ++ break; ++ ++ case LED_CTL_TX: ++ case LED_CTL_RX: ++ if(pLed->bLedBlinkInProgress ==_FALSE) ++ { ++ if(pLed->CurrLedState == LED_SCAN_BLINK || IS_LED_WPS_BLINKING(pLed)) ++ { ++ return; ++ } ++ if(pLed->bLedNoLinkBlinkInProgress == _TRUE) ++ { ++ _cancel_timer_ex(&(pLed->BlinkTimer)); ++ pLed->bLedNoLinkBlinkInProgress = _FALSE; ++ } ++ if( pLed->bLedLinkBlinkInProgress == _TRUE ) ++ { ++ _cancel_timer_ex(&(pLed->BlinkTimer)); ++ pLed->bLedLinkBlinkInProgress = _FALSE; ++ } ++ pLed->bLedBlinkInProgress = _TRUE; ++ pLed->CurrLedState = LED_TXRX_BLINK; ++ pLed->BlinkTimes = 2; ++ if( pLed->bLedOn ) ++ pLed->BlinkingLedState = LED_OFF; ++ else ++ pLed->BlinkingLedState = LED_ON; ++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_FASTER_INTERVAL_ALPHA); ++ } ++ break; ++ ++ case LED_CTL_START_WPS: //wait until xinpin finish ++ case LED_CTL_START_WPS_BOTTON: ++ if(pLed->bLedWPSBlinkInProgress ==_FALSE) ++ { ++ if(pLed->bLedNoLinkBlinkInProgress == _TRUE) ++ { ++ _cancel_timer_ex(&(pLed->BlinkTimer)); ++ pLed->bLedNoLinkBlinkInProgress = _FALSE; ++ } ++ if( pLed->bLedLinkBlinkInProgress == _TRUE ) ++ { ++ _cancel_timer_ex(&(pLed->BlinkTimer)); ++ pLed->bLedLinkBlinkInProgress = _FALSE; ++ } ++ if(pLed->bLedBlinkInProgress ==_TRUE) ++ { ++ _cancel_timer_ex(&(pLed->BlinkTimer)); ++ pLed->bLedBlinkInProgress = _FALSE; ++ } ++ if(pLed->bLedScanBlinkInProgress ==_TRUE) ++ { ++ _cancel_timer_ex(&(pLed->BlinkTimer)); ++ pLed->bLedScanBlinkInProgress = _FALSE; ++ } ++ pLed->bLedWPSBlinkInProgress = _TRUE; ++ pLed->CurrLedState = LED_BLINK_WPS; ++ if( pLed->bLedOn ) ++ pLed->BlinkingLedState = LED_OFF; ++ else ++ pLed->BlinkingLedState = LED_ON; ++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_SCAN_INTERVAL_ALPHA); ++ } ++ break; ++ ++ ++ case LED_CTL_STOP_WPS: ++ if(pLed->bLedNoLinkBlinkInProgress == _TRUE) ++ { ++ _cancel_timer_ex(&(pLed->BlinkTimer)); ++ pLed->bLedNoLinkBlinkInProgress = _FALSE; ++ } ++ if( pLed->bLedLinkBlinkInProgress == _TRUE ) ++ { ++ _cancel_timer_ex(&(pLed->BlinkTimer)); ++ pLed->bLedLinkBlinkInProgress = _FALSE; ++ } ++ if(pLed->bLedBlinkInProgress ==_TRUE) ++ { ++ _cancel_timer_ex(&(pLed->BlinkTimer)); ++ pLed->bLedBlinkInProgress = _FALSE; ++ } ++ if(pLed->bLedScanBlinkInProgress ==_TRUE) ++ { ++ _cancel_timer_ex(&(pLed->BlinkTimer)); ++ pLed->bLedScanBlinkInProgress = _FALSE; ++ } ++ if(pLed->bLedWPSBlinkInProgress) ++ { ++ _cancel_timer_ex(&(pLed->BlinkTimer)); ++ } ++ else ++ { ++ pLed->bLedWPSBlinkInProgress = _TRUE; ++ } ++ ++ pLed->CurrLedState = LED_BLINK_WPS_STOP; ++ if(pLed->bLedOn) ++ { ++ pLed->BlinkingLedState = LED_OFF; ++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_WPS_SUCESS_INTERVAL_ALPHA); ++ } ++ else ++ { ++ pLed->BlinkingLedState = LED_ON; ++ _set_timer(&(pLed->BlinkTimer), 0); ++ } ++ break; ++ ++ case LED_CTL_STOP_WPS_FAIL: ++ if(pLed->bLedWPSBlinkInProgress) ++ { ++ _cancel_timer_ex(&(pLed->BlinkTimer)); ++ pLed->bLedWPSBlinkInProgress = _FALSE; ++ } ++ ++ pLed->bLedNoLinkBlinkInProgress = _TRUE; ++ pLed->CurrLedState = LED_BLINK_SLOWLY; ++ if( pLed->bLedOn ) ++ pLed->BlinkingLedState = LED_OFF; ++ else ++ pLed->BlinkingLedState = LED_ON; ++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_NO_LINK_INTERVAL_ALPHA); ++ break; ++ ++ case LED_CTL_POWER_OFF: ++ pLed->CurrLedState = LED_OFF; ++ pLed->BlinkingLedState = LED_OFF; ++ if( pLed->bLedNoLinkBlinkInProgress) ++ { ++ _cancel_timer_ex(&(pLed->BlinkTimer)); ++ pLed->bLedNoLinkBlinkInProgress = _FALSE; ++ } ++ if( pLed->bLedLinkBlinkInProgress) ++ { ++ _cancel_timer_ex(&(pLed->BlinkTimer)); ++ pLed->bLedLinkBlinkInProgress = _FALSE; ++ } ++ if( pLed->bLedBlinkInProgress) ++ { ++ _cancel_timer_ex(&(pLed->BlinkTimer)); ++ pLed->bLedBlinkInProgress = _FALSE; ++ } ++ if( pLed->bLedWPSBlinkInProgress ) ++ { ++ _cancel_timer_ex(&(pLed->BlinkTimer)); ++ pLed->bLedWPSBlinkInProgress = _FALSE; ++ } ++ if( pLed->bLedScanBlinkInProgress) ++ { ++ _cancel_timer_ex(&(pLed->BlinkTimer)); ++ pLed->bLedScanBlinkInProgress = _FALSE; ++ } ++ ++ SwLedOff(padapter, pLed); ++ break; ++ ++ default: ++ break; ++ ++ } ++ ++ RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("Led %d\n", pLed->CurrLedState)); ++} ++ ++ //Arcadyan/Sitecom , added by chiyoko, 20090216 ++static void ++SwLedControlMode2( ++ _adapter *padapter, ++ LED_CTL_MODE LedAction ++) ++{ ++ struct led_priv *ledpriv = &(padapter->ledpriv); ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ PLED_871x pLed = &(ledpriv->SwLed0); ++ ++ switch(LedAction) ++ { ++ case LED_CTL_SITE_SURVEY: ++ if(pmlmepriv->LinkDetectInfo.bBusyTraffic) ++ ; ++ else if(pLed->bLedScanBlinkInProgress ==_FALSE) ++ { ++ if(IS_LED_WPS_BLINKING(pLed)) ++ return; ++ ++ if(pLed->bLedBlinkInProgress ==_TRUE) ++ { ++ _cancel_timer_ex(&(pLed->BlinkTimer)); ++ pLed->bLedBlinkInProgress = _FALSE; ++ } ++ pLed->bLedScanBlinkInProgress = _TRUE; ++ pLed->CurrLedState = LED_SCAN_BLINK; ++ pLed->BlinkTimes = 24; ++ if( pLed->bLedOn ) ++ pLed->BlinkingLedState = LED_OFF; ++ else ++ pLed->BlinkingLedState = LED_ON; ++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_SCAN_INTERVAL_ALPHA); ++ } ++ break; ++ ++ case LED_CTL_TX: ++ case LED_CTL_RX: ++ if((pLed->bLedBlinkInProgress ==_FALSE) && (check_fwstate(pmlmepriv, _FW_LINKED)== _TRUE)) ++ { ++ if(pLed->CurrLedState == LED_SCAN_BLINK || IS_LED_WPS_BLINKING(pLed)) ++ { ++ return; ++ } ++ ++ pLed->bLedBlinkInProgress = _TRUE; ++ pLed->CurrLedState = LED_TXRX_BLINK; ++ pLed->BlinkTimes = 2; ++ if( pLed->bLedOn ) ++ pLed->BlinkingLedState = LED_OFF; ++ else ++ pLed->BlinkingLedState = LED_ON; ++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_FASTER_INTERVAL_ALPHA); ++ } ++ break; ++ ++ case LED_CTL_LINK: ++ pLed->CurrLedState = LED_ON; ++ pLed->BlinkingLedState = LED_ON; ++ if( pLed->bLedBlinkInProgress) ++ { ++ _cancel_timer_ex(&(pLed->BlinkTimer)); ++ pLed->bLedBlinkInProgress = _FALSE; ++ } ++ if( pLed->bLedScanBlinkInProgress) ++ { ++ _cancel_timer_ex(&(pLed->BlinkTimer)); ++ pLed->bLedScanBlinkInProgress = _FALSE; ++ } ++ ++ _set_timer(&(pLed->BlinkTimer), 0); ++ break; ++ ++ case LED_CTL_START_WPS: //wait until xinpin finish ++ case LED_CTL_START_WPS_BOTTON: ++ if(pLed->bLedWPSBlinkInProgress ==_FALSE) ++ { ++ if(pLed->bLedBlinkInProgress ==_TRUE) ++ { ++ _cancel_timer_ex(&(pLed->BlinkTimer)); ++ pLed->bLedBlinkInProgress = _FALSE; ++ } ++ if(pLed->bLedScanBlinkInProgress ==_TRUE) ++ { ++ _cancel_timer_ex(&(pLed->BlinkTimer)); ++ pLed->bLedScanBlinkInProgress = _FALSE; ++ } ++ pLed->bLedWPSBlinkInProgress = _TRUE; ++ pLed->CurrLedState = LED_ON; ++ pLed->BlinkingLedState = LED_ON; ++ _set_timer(&(pLed->BlinkTimer), 0); ++ } ++ break; ++ ++ case LED_CTL_STOP_WPS: ++ pLed->bLedWPSBlinkInProgress = _FALSE; ++ if(padapter->pwrctrlpriv.rf_pwrstate != rf_on) ++ { ++ SwLedOff(padapter, pLed); ++ } ++ else ++ { ++ pLed->CurrLedState = LED_ON; ++ pLed->BlinkingLedState = LED_ON; ++ _set_timer(&(pLed->BlinkTimer), 0); ++ RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("CurrLedState %d\n", pLed->CurrLedState)); ++ } ++ break; ++ ++ case LED_CTL_STOP_WPS_FAIL: ++ pLed->bLedWPSBlinkInProgress = _FALSE; ++ if(padapter->pwrctrlpriv.rf_pwrstate != rf_on) ++ { ++ SwLedOff(padapter, pLed); ++ } ++ else ++ { ++ pLed->CurrLedState = LED_OFF; ++ pLed->BlinkingLedState = LED_OFF; ++ _set_timer(&(pLed->BlinkTimer), 0); ++ RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("CurrLedState %d\n", pLed->CurrLedState)); ++ } ++ break; ++ ++ case LED_CTL_START_TO_LINK: ++ case LED_CTL_NO_LINK: ++ if(!IS_LED_BLINKING(pLed)) ++ { ++ pLed->CurrLedState = LED_OFF; ++ pLed->BlinkingLedState = LED_OFF; ++ _set_timer(&(pLed->BlinkTimer), 0); ++ } ++ break; ++ ++ case LED_CTL_POWER_OFF: ++ pLed->CurrLedState = LED_OFF; ++ pLed->BlinkingLedState = LED_OFF; ++ if( pLed->bLedBlinkInProgress) ++ { ++ _cancel_timer_ex(&(pLed->BlinkTimer)); ++ pLed->bLedBlinkInProgress = _FALSE; ++ } ++ if( pLed->bLedScanBlinkInProgress) ++ { ++ _cancel_timer_ex(&(pLed->BlinkTimer)); ++ pLed->bLedScanBlinkInProgress = _FALSE; ++ } ++ if( pLed->bLedWPSBlinkInProgress ) ++ { ++ _cancel_timer_ex(&(pLed->BlinkTimer)); ++ pLed->bLedWPSBlinkInProgress = _FALSE; ++ } ++ ++ _set_timer(&(pLed->BlinkTimer), 0); ++ break; ++ ++ default: ++ break; ++ ++ } ++ ++ RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("CurrLedState %d\n", pLed->CurrLedState)); ++} ++ ++ //COREGA, added by chiyoko, 20090316 ++ static void ++ SwLedControlMode3( ++ _adapter *padapter, ++ LED_CTL_MODE LedAction ++) ++{ ++ struct led_priv *ledpriv = &(padapter->ledpriv); ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ PLED_871x pLed = &(ledpriv->SwLed0); ++ ++ switch(LedAction) ++ { ++ case LED_CTL_SITE_SURVEY: ++ if(pmlmepriv->LinkDetectInfo.bBusyTraffic) ++ ; ++ else if(pLed->bLedScanBlinkInProgress ==_FALSE) ++ { ++ if(IS_LED_WPS_BLINKING(pLed)) ++ return; ++ ++ if(pLed->bLedBlinkInProgress ==_TRUE) ++ { ++ _cancel_timer_ex(&(pLed->BlinkTimer)); ++ pLed->bLedBlinkInProgress = _FALSE; ++ } ++ pLed->bLedScanBlinkInProgress = _TRUE; ++ pLed->CurrLedState = LED_SCAN_BLINK; ++ pLed->BlinkTimes = 24; ++ if( pLed->bLedOn ) ++ pLed->BlinkingLedState = LED_OFF; ++ else ++ pLed->BlinkingLedState = LED_ON; ++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_SCAN_INTERVAL_ALPHA); ++ } ++ break; ++ ++ case LED_CTL_TX: ++ case LED_CTL_RX: ++ if((pLed->bLedBlinkInProgress ==_FALSE) && (check_fwstate(pmlmepriv, _FW_LINKED)== _TRUE)) ++ { ++ if(pLed->CurrLedState == LED_SCAN_BLINK || IS_LED_WPS_BLINKING(pLed)) ++ { ++ return; ++ } ++ ++ pLed->bLedBlinkInProgress = _TRUE; ++ pLed->CurrLedState = LED_TXRX_BLINK; ++ pLed->BlinkTimes = 2; ++ if( pLed->bLedOn ) ++ pLed->BlinkingLedState = LED_OFF; ++ else ++ pLed->BlinkingLedState = LED_ON; ++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_FASTER_INTERVAL_ALPHA); ++ } ++ break; ++ ++ case LED_CTL_LINK: ++ if(IS_LED_WPS_BLINKING(pLed)) ++ return; ++ ++ pLed->CurrLedState = LED_ON; ++ pLed->BlinkingLedState = LED_ON; ++ if( pLed->bLedBlinkInProgress) ++ { ++ _cancel_timer_ex(&(pLed->BlinkTimer)); ++ pLed->bLedBlinkInProgress = _FALSE; ++ } ++ if( pLed->bLedScanBlinkInProgress) ++ { ++ _cancel_timer_ex(&(pLed->BlinkTimer)); ++ pLed->bLedScanBlinkInProgress = _FALSE; ++ } ++ ++ _set_timer(&(pLed->BlinkTimer), 0); ++ break; ++ ++ case LED_CTL_START_WPS: //wait until xinpin finish ++ case LED_CTL_START_WPS_BOTTON: ++ if(pLed->bLedWPSBlinkInProgress ==_FALSE) ++ { ++ if(pLed->bLedBlinkInProgress ==_TRUE) ++ { ++ _cancel_timer_ex(&(pLed->BlinkTimer)); ++ pLed->bLedBlinkInProgress = _FALSE; ++ } ++ if(pLed->bLedScanBlinkInProgress ==_TRUE) ++ { ++ _cancel_timer_ex(&(pLed->BlinkTimer)); ++ pLed->bLedScanBlinkInProgress = _FALSE; ++ } ++ pLed->bLedWPSBlinkInProgress = _TRUE; ++ pLed->CurrLedState = LED_BLINK_WPS; ++ if( pLed->bLedOn ) ++ pLed->BlinkingLedState = LED_OFF; ++ else ++ pLed->BlinkingLedState = LED_ON; ++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_SCAN_INTERVAL_ALPHA); ++ } ++ break; ++ ++ case LED_CTL_STOP_WPS: ++ if(pLed->bLedWPSBlinkInProgress) ++ { ++ _cancel_timer_ex(&(pLed->BlinkTimer)); ++ pLed->bLedWPSBlinkInProgress = _FALSE; ++ } ++ else ++ { ++ pLed->bLedWPSBlinkInProgress = _TRUE; ++ } ++ ++ pLed->CurrLedState = LED_BLINK_WPS_STOP; ++ if(pLed->bLedOn) ++ { ++ pLed->BlinkingLedState = LED_OFF; ++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_WPS_SUCESS_INTERVAL_ALPHA); ++ } ++ else ++ { ++ pLed->BlinkingLedState = LED_ON; ++ _set_timer(&(pLed->BlinkTimer), 0); ++ } ++ ++ break; ++ ++ case LED_CTL_STOP_WPS_FAIL: ++ if(pLed->bLedWPSBlinkInProgress) ++ { ++ _cancel_timer_ex(&(pLed->BlinkTimer)); ++ pLed->bLedWPSBlinkInProgress = _FALSE; ++ } ++ ++ pLed->CurrLedState = LED_OFF; ++ pLed->BlinkingLedState = LED_OFF; ++ _set_timer(&(pLed->BlinkTimer), 0); ++ break; ++ ++ case LED_CTL_START_TO_LINK: ++ case LED_CTL_NO_LINK: ++ if(!IS_LED_BLINKING(pLed)) ++ { ++ pLed->CurrLedState = LED_OFF; ++ pLed->BlinkingLedState = LED_OFF; ++ _set_timer(&(pLed->BlinkTimer), 0); ++ } ++ break; ++ ++ case LED_CTL_POWER_OFF: ++ pLed->CurrLedState = LED_OFF; ++ pLed->BlinkingLedState = LED_OFF; ++ if( pLed->bLedBlinkInProgress) ++ { ++ _cancel_timer_ex(&(pLed->BlinkTimer)); ++ pLed->bLedBlinkInProgress = _FALSE; ++ } ++ if( pLed->bLedScanBlinkInProgress) ++ { ++ _cancel_timer_ex(&(pLed->BlinkTimer)); ++ pLed->bLedScanBlinkInProgress = _FALSE; ++ } ++ if( pLed->bLedWPSBlinkInProgress ) ++ { ++ _cancel_timer_ex(&(pLed->BlinkTimer)); ++ pLed->bLedWPSBlinkInProgress = _FALSE; ++ } ++ ++ _set_timer(&(pLed->BlinkTimer), 0); ++ break; ++ ++ default: ++ break; ++ ++ } ++ ++ RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("CurrLedState %d\n", pLed->CurrLedState)); ++} ++ ++ ++ //Edimax-Belkin, added by chiyoko, 20090413 ++static void ++SwLedControlMode4( ++ _adapter *padapter, ++ LED_CTL_MODE LedAction ++) ++{ ++ struct led_priv *ledpriv = &(padapter->ledpriv); ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ PLED_871x pLed = &(ledpriv->SwLed0); ++ PLED_871x pLed1 = &(ledpriv->SwLed1); ++ ++ switch(LedAction) ++ { ++ case LED_CTL_START_TO_LINK: ++ if(pLed1->bLedWPSBlinkInProgress) ++ { ++ pLed1->bLedWPSBlinkInProgress = _FALSE; ++ _cancel_timer_ex(&(pLed1->BlinkTimer)); ++ ++ pLed1->BlinkingLedState = LED_OFF; ++ pLed1->CurrLedState = LED_OFF; ++ ++ if(pLed1->bLedOn) ++ _set_timer(&(pLed->BlinkTimer), 0); ++ } ++ ++ if( pLed->bLedStartToLinkBlinkInProgress == _FALSE ) ++ { ++ if(pLed->CurrLedState == LED_SCAN_BLINK || IS_LED_WPS_BLINKING(pLed)) ++ { ++ return; ++ } ++ if(pLed->bLedBlinkInProgress ==_TRUE) ++ { ++ _cancel_timer_ex(&(pLed->BlinkTimer)); ++ pLed->bLedBlinkInProgress = _FALSE; ++ } ++ if(pLed->bLedNoLinkBlinkInProgress ==_TRUE) ++ { ++ _cancel_timer_ex(&(pLed->BlinkTimer)); ++ pLed->bLedNoLinkBlinkInProgress = _FALSE; ++ } ++ ++ pLed->bLedStartToLinkBlinkInProgress = _TRUE; ++ pLed->CurrLedState = LED_BLINK_StartToBlink; ++ if( pLed->bLedOn ) ++ { ++ pLed->BlinkingLedState = LED_OFF; ++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_SLOWLY_INTERVAL); ++ } ++ else ++ { ++ pLed->BlinkingLedState = LED_ON; ++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_NORMAL_INTERVAL); ++ } ++ } ++ break; ++ ++ case LED_CTL_LINK: ++ case LED_CTL_NO_LINK: ++ //LED1 settings ++ if(LedAction == LED_CTL_LINK) ++ { ++ if(pLed1->bLedWPSBlinkInProgress) ++ { ++ pLed1->bLedWPSBlinkInProgress = _FALSE; ++ _cancel_timer_ex(&(pLed1->BlinkTimer)); ++ ++ pLed1->BlinkingLedState = LED_OFF; ++ pLed1->CurrLedState = LED_OFF; ++ ++ if(pLed1->bLedOn) ++ _set_timer(&(pLed->BlinkTimer), 0); ++ } ++ } ++ ++ if( pLed->bLedNoLinkBlinkInProgress == _FALSE ) ++ { ++ if(pLed->CurrLedState == LED_SCAN_BLINK || IS_LED_WPS_BLINKING(pLed)) ++ { ++ return; ++ } ++ if(pLed->bLedBlinkInProgress ==_TRUE) ++ { ++ _cancel_timer_ex(&(pLed->BlinkTimer)); ++ pLed->bLedBlinkInProgress = _FALSE; ++ } ++ ++ pLed->bLedNoLinkBlinkInProgress = _TRUE; ++ pLed->CurrLedState = LED_BLINK_SLOWLY; ++ if( pLed->bLedOn ) ++ pLed->BlinkingLedState = LED_OFF; ++ else ++ pLed->BlinkingLedState = LED_ON; ++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_NO_LINK_INTERVAL_ALPHA); ++ } ++ break; ++ ++ case LED_CTL_SITE_SURVEY: ++ if((pmlmepriv->LinkDetectInfo.bBusyTraffic) && (check_fwstate(pmlmepriv, _FW_LINKED)== _TRUE)) ++ ; ++ else if(pLed->bLedScanBlinkInProgress ==_FALSE) ++ { ++ if(IS_LED_WPS_BLINKING(pLed)) ++ return; ++ ++ if(pLed->bLedNoLinkBlinkInProgress == _TRUE) ++ { ++ _cancel_timer_ex(&(pLed->BlinkTimer)); ++ pLed->bLedNoLinkBlinkInProgress = _FALSE; ++ } ++ if(pLed->bLedBlinkInProgress ==_TRUE) ++ { ++ _cancel_timer_ex(&(pLed->BlinkTimer)); ++ pLed->bLedBlinkInProgress = _FALSE; ++ } ++ pLed->bLedScanBlinkInProgress = _TRUE; ++ pLed->CurrLedState = LED_SCAN_BLINK; ++ pLed->BlinkTimes = 24; ++ if( pLed->bLedOn ) ++ pLed->BlinkingLedState = LED_OFF; ++ else ++ pLed->BlinkingLedState = LED_ON; ++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_SCAN_INTERVAL_ALPHA); ++ } ++ break; ++ ++ case LED_CTL_TX: ++ case LED_CTL_RX: ++ if(pLed->bLedBlinkInProgress ==_FALSE) ++ { ++ if(pLed->CurrLedState == LED_SCAN_BLINK || IS_LED_WPS_BLINKING(pLed)) ++ { ++ return; ++ } ++ if(pLed->bLedNoLinkBlinkInProgress == _TRUE) ++ { ++ _cancel_timer_ex(&(pLed->BlinkTimer)); ++ pLed->bLedNoLinkBlinkInProgress = _FALSE; ++ } ++ pLed->bLedBlinkInProgress = _TRUE; ++ pLed->CurrLedState = LED_TXRX_BLINK; ++ pLed->BlinkTimes = 2; ++ if( pLed->bLedOn ) ++ pLed->BlinkingLedState = LED_OFF; ++ else ++ pLed->BlinkingLedState = LED_ON; ++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_FASTER_INTERVAL_ALPHA); ++ } ++ break; ++ ++ case LED_CTL_START_WPS: //wait until xinpin finish ++ case LED_CTL_START_WPS_BOTTON: ++ if(pLed1->bLedWPSBlinkInProgress) ++ { ++ pLed1->bLedWPSBlinkInProgress = _FALSE; ++ _cancel_timer_ex(&(pLed1->BlinkTimer)); ++ ++ pLed1->BlinkingLedState = LED_OFF; ++ pLed1->CurrLedState = LED_OFF; ++ ++ if(pLed1->bLedOn) ++ _set_timer(&(pLed->BlinkTimer), 0); ++ } ++ ++ if(pLed->bLedWPSBlinkInProgress ==_FALSE) ++ { ++ if(pLed->bLedNoLinkBlinkInProgress == _TRUE) ++ { ++ _cancel_timer_ex(&(pLed->BlinkTimer)); ++ pLed->bLedNoLinkBlinkInProgress = _FALSE; ++ } ++ if(pLed->bLedBlinkInProgress ==_TRUE) ++ { ++ _cancel_timer_ex(&(pLed->BlinkTimer)); ++ pLed->bLedBlinkInProgress = _FALSE; ++ } ++ if(pLed->bLedScanBlinkInProgress ==_TRUE) ++ { ++ _cancel_timer_ex(&(pLed->BlinkTimer)); ++ pLed->bLedScanBlinkInProgress = _FALSE; ++ } ++ pLed->bLedWPSBlinkInProgress = _TRUE; ++ pLed->CurrLedState = LED_BLINK_WPS; ++ if( pLed->bLedOn ) ++ { ++ pLed->BlinkingLedState = LED_OFF; ++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_SLOWLY_INTERVAL); ++ } ++ else ++ { ++ pLed->BlinkingLedState = LED_ON; ++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_NORMAL_INTERVAL); ++ } ++ } ++ break; ++ ++ case LED_CTL_STOP_WPS: //WPS connect success ++ if(pLed->bLedWPSBlinkInProgress) ++ { ++ _cancel_timer_ex(&(pLed->BlinkTimer)); ++ pLed->bLedWPSBlinkInProgress = _FALSE; ++ } ++ ++ pLed->bLedNoLinkBlinkInProgress = _TRUE; ++ pLed->CurrLedState = LED_BLINK_SLOWLY; ++ if( pLed->bLedOn ) ++ pLed->BlinkingLedState = LED_OFF; ++ else ++ pLed->BlinkingLedState = LED_ON; ++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_NO_LINK_INTERVAL_ALPHA); ++ ++ break; ++ ++ case LED_CTL_STOP_WPS_FAIL: //WPS authentication fail ++ if(pLed->bLedWPSBlinkInProgress) ++ { ++ _cancel_timer_ex(&(pLed->BlinkTimer)); ++ pLed->bLedWPSBlinkInProgress = _FALSE; ++ } ++ ++ pLed->bLedNoLinkBlinkInProgress = _TRUE; ++ pLed->CurrLedState = LED_BLINK_SLOWLY; ++ if( pLed->bLedOn ) ++ pLed->BlinkingLedState = LED_OFF; ++ else ++ pLed->BlinkingLedState = LED_ON; ++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_NO_LINK_INTERVAL_ALPHA); ++ ++ //LED1 settings ++ if(pLed1->bLedWPSBlinkInProgress) ++ _cancel_timer_ex(&(pLed1->BlinkTimer)); ++ else ++ pLed1->bLedWPSBlinkInProgress = _TRUE; ++ ++ pLed1->CurrLedState = LED_BLINK_WPS_STOP; ++ if( pLed1->bLedOn ) ++ pLed1->BlinkingLedState = LED_OFF; ++ else ++ pLed1->BlinkingLedState = LED_ON; ++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_NORMAL_INTERVAL); ++ ++ break; ++ ++ case LED_CTL_STOP_WPS_FAIL_OVERLAP: //WPS session overlap ++ if(pLed->bLedWPSBlinkInProgress) ++ { ++ _cancel_timer_ex(&(pLed->BlinkTimer)); ++ pLed->bLedWPSBlinkInProgress = _FALSE; ++ } ++ ++ pLed->bLedNoLinkBlinkInProgress = _TRUE; ++ pLed->CurrLedState = LED_BLINK_SLOWLY; ++ if( pLed->bLedOn ) ++ pLed->BlinkingLedState = LED_OFF; ++ else ++ pLed->BlinkingLedState = LED_ON; ++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_NO_LINK_INTERVAL_ALPHA); ++ ++ //LED1 settings ++ if(pLed1->bLedWPSBlinkInProgress) ++ _cancel_timer_ex(&(pLed1->BlinkTimer)); ++ else ++ pLed1->bLedWPSBlinkInProgress = _TRUE; ++ ++ pLed1->CurrLedState = LED_BLINK_WPS_STOP_OVERLAP; ++ pLed1->BlinkTimes = 10; ++ if( pLed1->bLedOn ) ++ pLed1->BlinkingLedState = LED_OFF; ++ else ++ pLed1->BlinkingLedState = LED_ON; ++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_NORMAL_INTERVAL); ++ ++ break; ++ ++ case LED_CTL_POWER_OFF: ++ pLed->CurrLedState = LED_OFF; ++ pLed->BlinkingLedState = LED_OFF; ++ ++ if( pLed->bLedNoLinkBlinkInProgress) ++ { ++ _cancel_timer_ex(&(pLed->BlinkTimer)); ++ pLed->bLedNoLinkBlinkInProgress = _FALSE; ++ } ++ if( pLed->bLedLinkBlinkInProgress) ++ { ++ _cancel_timer_ex(&(pLed->BlinkTimer)); ++ pLed->bLedLinkBlinkInProgress = _FALSE; ++ } ++ if( pLed->bLedBlinkInProgress) ++ { ++ _cancel_timer_ex(&(pLed->BlinkTimer)); ++ pLed->bLedBlinkInProgress = _FALSE; ++ } ++ if( pLed->bLedWPSBlinkInProgress ) ++ { ++ _cancel_timer_ex(&(pLed->BlinkTimer)); ++ pLed->bLedWPSBlinkInProgress = _FALSE; ++ } ++ if( pLed->bLedScanBlinkInProgress) ++ { ++ _cancel_timer_ex(&(pLed->BlinkTimer)); ++ pLed->bLedScanBlinkInProgress = _FALSE; ++ } ++ if( pLed->bLedStartToLinkBlinkInProgress) ++ { ++ _cancel_timer_ex(&(pLed->BlinkTimer)); ++ pLed->bLedStartToLinkBlinkInProgress = _FALSE; ++ } ++ ++ if( pLed1->bLedWPSBlinkInProgress ) ++ { ++ _cancel_timer_ex(&(pLed1->BlinkTimer)); ++ pLed1->bLedWPSBlinkInProgress = _FALSE; ++ } ++ ++ pLed1->BlinkingLedState = LED_UNKNOWN; ++ SwLedOff(padapter, pLed); ++ SwLedOff(padapter, pLed1); ++ break; ++ ++ default: ++ break; ++ ++ } ++ ++ RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("Led %d\n", pLed->CurrLedState)); ++} ++ ++ ++ ++ //Sercomm-Belkin, added by chiyoko, 20090415 ++static void ++SwLedControlMode5( ++ _adapter *padapter, ++ LED_CTL_MODE LedAction ++) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); ++ struct led_priv *ledpriv = &(padapter->ledpriv); ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ PLED_871x pLed = &(ledpriv->SwLed0); ++ ++ if(pHalData->EEPROMCustomerID == RT_CID_819x_CAMEO) ++ pLed = &(ledpriv->SwLed1); ++ ++ switch(LedAction) ++ { ++ case LED_CTL_POWER_ON: ++ case LED_CTL_NO_LINK: ++ case LED_CTL_LINK: //solid blue ++ pLed->CurrLedState = LED_ON; ++ pLed->BlinkingLedState = LED_ON; ++ ++ _set_timer(&(pLed->BlinkTimer), 0); ++ break; ++ ++ case LED_CTL_SITE_SURVEY: ++ if((pmlmepriv->LinkDetectInfo.bBusyTraffic) && (check_fwstate(pmlmepriv, _FW_LINKED)== _TRUE)) ++ ; ++ else if(pLed->bLedScanBlinkInProgress ==_FALSE) ++ { ++ if(pLed->bLedBlinkInProgress ==_TRUE) ++ { ++ _cancel_timer_ex(&(pLed->BlinkTimer)); ++ pLed->bLedBlinkInProgress = _FALSE; ++ } ++ pLed->bLedScanBlinkInProgress = _TRUE; ++ pLed->CurrLedState = LED_SCAN_BLINK; ++ pLed->BlinkTimes = 24; ++ if( pLed->bLedOn ) ++ pLed->BlinkingLedState = LED_OFF; ++ else ++ pLed->BlinkingLedState = LED_ON; ++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_SCAN_INTERVAL_ALPHA); ++ } ++ break; ++ ++ case LED_CTL_TX: ++ case LED_CTL_RX: ++ if(pLed->bLedBlinkInProgress ==_FALSE) ++ { ++ if(pLed->CurrLedState == LED_SCAN_BLINK) ++ { ++ return; ++ } ++ pLed->bLedBlinkInProgress = _TRUE; ++ pLed->CurrLedState = LED_TXRX_BLINK; ++ pLed->BlinkTimes = 2; ++ if( pLed->bLedOn ) ++ pLed->BlinkingLedState = LED_OFF; ++ else ++ pLed->BlinkingLedState = LED_ON; ++ _set_timer(&(pLed->BlinkTimer), LED_BLINK_FASTER_INTERVAL_ALPHA); ++ } ++ break; ++ ++ case LED_CTL_POWER_OFF: ++ pLed->CurrLedState = LED_OFF; ++ pLed->BlinkingLedState = LED_OFF; ++ ++ if( pLed->bLedBlinkInProgress) ++ { ++ _cancel_timer_ex(&(pLed->BlinkTimer)); ++ pLed->bLedBlinkInProgress = _FALSE; ++ } ++ ++ SwLedOff(padapter, pLed); ++ break; ++ ++ default: ++ break; ++ ++ } ++ ++ RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("Led %d\n", pLed->CurrLedState)); ++} ++ ++ //WNC-Corega, added by chiyoko, 20090902 ++static void ++SwLedControlMode6( ++ _adapter *padapter, ++ LED_CTL_MODE LedAction ++) ++{ ++ struct led_priv *ledpriv = &(padapter->ledpriv); ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ PLED_871x pLed0 = &(ledpriv->SwLed0); ++ ++ switch(LedAction) ++ { ++ case LED_CTL_POWER_ON: ++ case LED_CTL_LINK: ++ case LED_CTL_NO_LINK: ++ _cancel_timer_ex(&(pLed0->BlinkTimer)); ++ pLed0->CurrLedState = LED_ON; ++ pLed0->BlinkingLedState = LED_ON; ++ _set_timer(&(pLed0->BlinkTimer), 0); ++ break; ++ ++ case LED_CTL_POWER_OFF: ++ SwLedOff(padapter, pLed0); ++ break; ++ ++ default: ++ break; ++ } ++ ++ RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("ledcontrol 6 Led %d\n", pLed->CurrLedState)); ++} ++ ++ ++// ++// Description: ++// Dispatch LED action according to pHalData->LedStrategy. ++// ++static void ++LedControl871x( ++ _adapter *padapter, ++ LED_CTL_MODE LedAction ++ ) ++{ ++ struct led_priv *ledpriv = &(padapter->ledpriv); ++ ++ if( (padapter->bSurpriseRemoved == _TRUE) || ( padapter->bDriverStopped == _TRUE) ++ ||(padapter->hw_init_completed == _FALSE) ) ++ { ++ return; ++ } ++ ++ ++ if( ledpriv->bRegUseLed == _FALSE) ++ return; ++ ++ //if (!priv->up) ++ // return; ++ ++ //if(priv->bInHctTest) ++ // return; ++ ++ if( (padapter->pwrctrlpriv.rf_pwrstate != rf_on && ++ padapter->pwrctrlpriv.rfoff_reason > RF_CHANGE_BY_PS) && ++ (LedAction == LED_CTL_TX || LedAction == LED_CTL_RX || ++ LedAction == LED_CTL_SITE_SURVEY || ++ LedAction == LED_CTL_LINK || ++ LedAction == LED_CTL_NO_LINK || ++ LedAction == LED_CTL_POWER_ON) ) ++ { ++ return; ++ } ++ ++ switch(ledpriv->LedStrategy) ++ { ++ case SW_LED_MODE0: ++ //SwLedControlMode0(padapter, LedAction); ++ break; ++ ++ case SW_LED_MODE1: ++ SwLedControlMode1(padapter, LedAction); ++ break; ++ case SW_LED_MODE2: ++ SwLedControlMode2(padapter, LedAction); ++ break; ++ ++ case SW_LED_MODE3: ++ SwLedControlMode3(padapter, LedAction); ++ break; ++ ++ case SW_LED_MODE4: ++ SwLedControlMode4(padapter, LedAction); ++ break; ++ ++ case SW_LED_MODE5: ++ SwLedControlMode5(padapter, LedAction); ++ break; ++ ++ case SW_LED_MODE6: ++ SwLedControlMode6(padapter, LedAction); ++ break; ++ ++ default: ++ break; ++ } ++ ++ RT_TRACE(_module_rtl8712_led_c_,_drv_info_,("LedStrategy:%d, LedAction %d\n", ledpriv->LedStrategy,LedAction)); ++} ++ ++// ++// Description: ++// Initialize all LED_871x objects. ++// ++void ++rtl8192cu_InitSwLeds( ++ _adapter *padapter ++ ) ++{ ++ struct led_priv *pledpriv = &(padapter->ledpriv); ++ ++ pledpriv->LedControlHandler = LedControl871x; ++ ++ InitLed871x(padapter, &(pledpriv->SwLed0), LED_PIN_LED0); ++ ++ InitLed871x(padapter,&(pledpriv->SwLed1), LED_PIN_LED1); ++} ++ ++ ++// ++// Description: ++// DeInitialize all LED_819xUsb objects. ++// ++void ++rtl8192cu_DeInitSwLeds( ++ _adapter *padapter ++ ) ++{ ++ struct led_priv *ledpriv = &(padapter->ledpriv); ++ ++ DeInitLed871x( &(ledpriv->SwLed0) ); ++ DeInitLed871x( &(ledpriv->SwLed1) ); ++} ++ +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/hal/rtl8192c/usb/rtl8192cu_recv.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/hal/rtl8192c/usb/rtl8192cu_recv.c 2013-07-26 19:36:06.000000000 +0000 +@@ -0,0 +1,380 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ++******************************************************************************/ ++#define _RTL8192CU_RECV_C_ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#if defined (PLATFORM_LINUX) && defined (PLATFORM_WINDOWS) ++ ++#error "Shall be Linux or Windows, but not both!\n" ++ ++#endif ++ ++#include ++#include ++ ++#include ++ ++ ++void rtl8192cu_init_recvbuf(_adapter *padapter, struct recv_buf *precvbuf) ++{ ++ ++ precvbuf->transfer_len = 0; ++ ++ precvbuf->len = 0; ++ ++ precvbuf->ref_cnt = 0; ++ ++ if(precvbuf->pbuf) ++ { ++ precvbuf->pdata = precvbuf->phead = precvbuf->ptail = precvbuf->pbuf; ++ precvbuf->pend = precvbuf->pdata + MAX_RECVBUF_SZ; ++ } ++ ++} ++ ++int rtl8192cu_init_recv_priv(_adapter *padapter) ++{ ++ struct recv_priv *precvpriv = &padapter->recvpriv; ++ int i, res = _SUCCESS; ++ struct recv_buf *precvbuf; ++ ++#ifdef CONFIG_RECV_THREAD_MODE ++ _rtw_init_sema(&precvpriv->recv_sema, 0);//will be removed ++ _rtw_init_sema(&precvpriv->terminate_recvthread_sema, 0);//will be removed ++#endif ++ ++#ifdef PLATFORM_LINUX ++ tasklet_init(&precvpriv->recv_tasklet, ++ (void(*)(unsigned long))rtl8192cu_recv_tasklet, ++ (unsigned long)padapter); ++#endif ++ ++#ifdef CONFIG_USB_INTERRUPT_IN_PIPE ++#ifdef PLATFORM_LINUX ++ precvpriv->int_in_urb = usb_alloc_urb(0, GFP_KERNEL); ++ if(precvpriv->int_in_urb == NULL){ ++ DBG_8192C("alloc_urb for interrupt in endpoint fail !!!!\n"); ++ } ++#endif ++ precvpriv->int_in_buf = rtw_zmalloc(sizeof(INTERRUPT_MSG_FORMAT_EX)); ++ if(precvpriv->int_in_buf == NULL){ ++ DBG_8192C("alloc_mem for interrupt in endpoint fail !!!!\n"); ++ } ++#endif ++ ++ //init recv_buf ++ _rtw_init_queue(&precvpriv->free_recv_buf_queue); ++ ++#ifdef CONFIG_USE_USB_BUFFER_ALLOC_RX ++ _rtw_init_queue(&precvpriv->recv_buf_pending_queue); ++#endif // CONFIG_USE_USB_BUFFER_ALLOC_RX ++ ++ precvpriv->pallocated_recv_buf = rtw_zmalloc(NR_RECVBUFF *sizeof(struct recv_buf) + 4); ++ if(precvpriv->pallocated_recv_buf==NULL){ ++ res= _FAIL; ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("alloc recv_buf fail!\n")); ++ goto exit; ++ } ++ _rtw_memset(precvpriv->pallocated_recv_buf, 0, NR_RECVBUFF *sizeof(struct recv_buf) + 4); ++ ++ precvpriv->precv_buf = (u8 *)N_BYTE_ALIGMENT((SIZE_PTR)(precvpriv->pallocated_recv_buf), 4); ++ //precvpriv->precv_buf = precvpriv->pallocated_recv_buf + 4 - ++ // ((uint) (precvpriv->pallocated_recv_buf) &(4-1)); ++ ++ ++ precvbuf = (struct recv_buf*)precvpriv->precv_buf; ++ ++ for(i=0; i < NR_RECVBUFF ; i++) ++ { ++ _rtw_init_listhead(&precvbuf->list); ++ ++ _rtw_spinlock_init(&precvbuf->recvbuf_lock); ++ ++ precvbuf->alloc_sz = MAX_RECVBUF_SZ; ++ ++ res = rtw_os_recvbuf_resource_alloc(padapter, precvbuf); ++ if(res==_FAIL) ++ break; ++ ++ precvbuf->ref_cnt = 0; ++ precvbuf->adapter =padapter; ++ ++ ++ //rtw_list_insert_tail(&precvbuf->list, &(precvpriv->free_recv_buf_queue.queue)); ++ ++ precvbuf++; ++ ++ } ++ ++ precvpriv->free_recv_buf_queue_cnt = NR_RECVBUFF; ++ ++#ifdef PLATFORM_LINUX ++ ++ skb_queue_head_init(&precvpriv->rx_skb_queue); ++ ++#ifdef CONFIG_PREALLOC_RECV_SKB ++ { ++ int i; ++ SIZE_PTR tmpaddr=0; ++ SIZE_PTR alignment=0; ++ struct sk_buff *pskb=NULL; ++ ++ skb_queue_head_init(&precvpriv->free_recv_skb_queue); ++ ++ for(i=0; ipnetdev, MAX_RECVBUF_SZ + RECVBUFF_ALIGN_SZ); ++ #endif ++ ++ if(pskb) ++ { ++ pskb->dev = padapter->pnetdev; ++ ++ tmpaddr = (SIZE_PTR)pskb->data; ++ alignment = tmpaddr & (RECVBUFF_ALIGN_SZ-1); ++ skb_reserve(pskb, (RECVBUFF_ALIGN_SZ - alignment)); ++ ++ skb_queue_tail(&precvpriv->free_recv_skb_queue, pskb); ++ } ++ ++ pskb=NULL; ++ ++ } ++ } ++#endif ++ ++#endif ++ ++exit: ++ ++ return res; ++ ++} ++ ++void rtl8192cu_free_recv_priv (_adapter *padapter) ++{ ++ int i; ++ struct recv_buf *precvbuf; ++ struct recv_priv *precvpriv = &padapter->recvpriv; ++ ++ precvbuf = (struct recv_buf *)precvpriv->precv_buf; ++ ++ for(i=0; i < NR_RECVBUFF ; i++) ++ { ++ rtw_os_recvbuf_resource_free(padapter, precvbuf); ++ precvbuf++; ++ } ++ ++ if(precvpriv->pallocated_recv_buf) ++ rtw_mfree(precvpriv->pallocated_recv_buf, NR_RECVBUFF *sizeof(struct recv_buf) + 4); ++ ++#ifdef CONFIG_USB_INTERRUPT_IN_PIPE ++#ifdef PLATFORM_LINUX ++ if(precvpriv->int_in_urb) ++ { ++ usb_free_urb(precvpriv->int_in_urb); ++ } ++#endif ++ if(precvpriv->int_in_buf) ++ rtw_mfree(precvpriv->int_in_buf, sizeof(INTERRUPT_MSG_FORMAT_EX)); ++#endif ++ ++#ifdef PLATFORM_LINUX ++ ++ if (skb_queue_len(&precvpriv->rx_skb_queue)) { ++ DBG_8192C(KERN_WARNING "rx_skb_queue not empty\n"); ++ } ++ ++ skb_queue_purge(&precvpriv->rx_skb_queue); ++ ++#ifdef CONFIG_PREALLOC_RECV_SKB ++ ++ if (skb_queue_len(&precvpriv->free_recv_skb_queue)) { ++ DBG_8192C(KERN_WARNING "free_recv_skb_queue not empty, %d\n", skb_queue_len(&precvpriv->free_recv_skb_queue)); ++ } ++ ++ skb_queue_purge(&precvpriv->free_recv_skb_queue); ++ ++#endif ++ ++#endif ++ ++} ++ ++void rtl8192cu_update_recvframe_attrib_from_recvstat(union recv_frame *precvframe, struct recv_stat *prxstat) ++{ ++ u8 physt, qos, shift, icverr, htc, crcerr; ++ u16 drvinfo_sz=0; ++ struct phy_stat *pphy_info; ++ struct rx_pkt_attrib *pattrib = &precvframe->u.hdr.attrib; ++ _adapter *padapter = precvframe->u.hdr.adapter; ++ u8 bPacketMatchBSSID =_FALSE; ++ u8 bPacketToSelf = _FALSE; ++ u8 bPacketBeacon = _FALSE; ++ ++ ++ //Offset 0 ++ drvinfo_sz = (le32_to_cpu(prxstat->rxdw0)&0x000f0000)>>16; ++ drvinfo_sz = drvinfo_sz<<3; ++ ++ pattrib->bdecrypted = ((le32_to_cpu(prxstat->rxdw0) & BIT(27)) >> 27)? 0:1; ++ ++ physt = ((le32_to_cpu(prxstat->rxdw0) & BIT(26)) >> 26)? 1:0; ++ ++ shift = (le32_to_cpu(prxstat->rxdw0)&0x03000000)>>24; ++ ++ qos = ((le32_to_cpu(prxstat->rxdw0) & BIT(23)) >> 23)? 1:0; ++ ++ icverr = ((le32_to_cpu(prxstat->rxdw0) & BIT(15)) >> 15)? 1:0; ++ ++ pattrib->crc_err = crcerr = ((le32_to_cpu(prxstat->rxdw0) & BIT(14)) >> 14 )? 1:0; ++ ++ ++ //Offset 4 ++ ++ //Offset 8 ++ ++ //Offset 12 ++#ifdef CONFIG_TCP_CSUM_OFFLOAD_RX ++ if ( le32_to_cpu(prxstat->rxdw3) & BIT(13)) { ++ pattrib->tcpchk_valid = 1; // valid ++ if ( le32_to_cpu(prxstat->rxdw3) & BIT(11) ) { ++ pattrib->tcp_chkrpt = 1; // correct ++ //DBG_8192C("tcp csum ok\n"); ++ } else ++ pattrib->tcp_chkrpt = 0; // incorrect ++ ++ if ( le32_to_cpu(prxstat->rxdw3) & BIT(12) ) ++ pattrib->ip_chkrpt = 1; // correct ++ else ++ pattrib->ip_chkrpt = 0; // incorrect ++ ++ } else { ++ pattrib->tcpchk_valid = 0; // invalid ++ } ++ ++#endif ++ ++ pattrib->mcs_rate=(u8)((le32_to_cpu(prxstat->rxdw3))&0x3f); ++ pattrib->rxht=(u8)((le32_to_cpu(prxstat->rxdw3) >>6)&0x1); ++ ++ htc = (u8)((le32_to_cpu(prxstat->rxdw3) >>10)&0x1); ++ ++ //Offset 16 ++ //Offset 20 ++ ++ ++#if 0 //dump rxdesc for debug ++ DBG_8192C("drvinfo_sz=%d\n", drvinfo_sz); ++ DBG_8192C("physt=%d\n", physt); ++ DBG_8192C("shift=%d\n", shift); ++ DBG_8192C("qos=%d\n", qos); ++ DBG_8192C("icverr=%d\n", icverr); ++ DBG_8192C("htc=%d\n", htc); ++ DBG_8192C("bdecrypted=%d\n", pattrib->bdecrypted); ++ DBG_8192C("mcs_rate=%d\n", pattrib->mcs_rate); ++ DBG_8192C("rxht=%d\n", pattrib->rxht); ++#endif ++ ++ //phy_info ++ if(drvinfo_sz && physt) ++ { ++ bPacketMatchBSSID = ((!IsFrameTypeCtrl(precvframe->u.hdr.rx_data)) && !icverr && !crcerr && ++ _rtw_memcmp(get_hdr_bssid(precvframe->u.hdr.rx_data), get_bssid(&padapter->mlmepriv), ETH_ALEN)); ++ ++ bPacketToSelf = bPacketMatchBSSID && (_rtw_memcmp(get_da(precvframe->u.hdr.rx_data), myid(&padapter->eeprompriv), ETH_ALEN)); ++ ++ bPacketBeacon = (GetFrameSubType(precvframe->u.hdr.rx_data) == WIFI_BEACON); ++ ++ ++ pphy_info = (struct phy_stat *)(prxstat+1); ++ ++ //DBG_8192C("pphy_info, of0=0x%08x\n", *pphy_info); ++ //DBG_8192C("pphy_info, of1=0x%08x\n", *(pphy_info+1)); ++ //DBG_8192C("pphy_info, of2=0x%08x\n", *(pphy_info+2)); ++ //DBG_8192C("pphy_info, of3=0x%08x\n", *(pphy_info+3)); ++ //DBG_8192C("pphy_info, of4=0x%08x\n", *(pphy_info+4)); ++ //DBG_8192C("pphy_info, of5=0x%08x\n", *(pphy_info+5)); ++ //DBG_8192C("pphy_info, of6=0x%08x\n", *(pphy_info+6)); ++ //DBG_8192C("pphy_info, of7=0x%08x\n", *(pphy_info+7)); ++ ++ rtl8192c_query_rx_phy_status(precvframe, pphy_info); ++ ++ precvframe->u.hdr.psta = NULL; ++ if(bPacketMatchBSSID && check_fwstate(&padapter->mlmepriv, WIFI_AP_STATE) == _TRUE) ++ { ++ u8 *sa; ++ struct sta_info *psta=NULL; ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ ++ sa = get_sa(precvframe->u.hdr.rx_data); ++ ++ psta = rtw_get_stainfo(pstapriv, sa); ++ if(psta) ++ { ++ precvframe->u.hdr.psta = psta; ++ rtl8192c_process_phy_info(padapter, precvframe); ++ } ++ } ++ else if( bPacketToSelf || (bPacketBeacon && bPacketMatchBSSID) ) ++ { ++ if(check_fwstate(&padapter->mlmepriv, WIFI_ADHOC_STATE|WIFI_ADHOC_MASTER_STATE) == _TRUE) ++ { ++ u8 *sa; ++ struct sta_info *psta=NULL; ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ ++ sa = get_sa(precvframe->u.hdr.rx_data); ++ ++ psta = rtw_get_stainfo(pstapriv, sa); ++ if(psta) ++ { ++ precvframe->u.hdr.psta = psta; ++ } ++ } ++ ++ rtl8192c_process_phy_info(padapter, precvframe); ++ } ++ ++#if 0 //dump phy_status for debug ++ ++ DBG_8192C("signal_qual=%d\n", pattrib->signal_qual); ++ DBG_8192C("signal_strength=%d\n", pattrib->signal_strength); ++#endif ++ ++ } ++ ++ ++} ++ +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/hal/rtl8192c/usb/rtl8192cu_xmit.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/hal/rtl8192c/usb/rtl8192cu_xmit.c 2013-07-26 19:36:06.000000000 +0000 +@@ -0,0 +1,1322 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ++******************************************************************************/ ++#define _RTL8192C_XMIT_C_ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#if defined (PLATFORM_LINUX) && defined (PLATFORM_WINDOWS) ++#error "Shall be Linux or Windows, but not both!\n" ++#endif ++ ++ ++s32 rtl8192cu_init_xmit_priv(_adapter *padapter) ++{ ++ struct xmit_priv *pxmitpriv = &padapter->xmitpriv; ++ ++#ifdef PLATFORM_LINUX ++ tasklet_init(&pxmitpriv->xmit_tasklet, ++ (void(*)(unsigned long))rtl8192cu_xmit_tasklet, ++ (unsigned long)padapter); ++#endif ++ return _SUCCESS; ++} ++ ++void rtl8192cu_free_xmit_priv(_adapter *padapter) ++{ ++} ++ ++u32 rtw_get_ff_hwaddr(struct xmit_frame *pxmitframe) ++{ ++ u32 addr; ++ struct pkt_attrib *pattrib = &pxmitframe->attrib; ++ ++ switch(pattrib->qsel) ++ { ++ case 0: ++ case 3: ++ addr = BE_QUEUE_INX; ++ break; ++ case 1: ++ case 2: ++ addr = BK_QUEUE_INX; ++ break; ++ case 4: ++ case 5: ++ addr = VI_QUEUE_INX; ++ break; ++ case 6: ++ case 7: ++ addr = VO_QUEUE_INX; ++ break; ++ case 0x10: ++ addr = BCN_QUEUE_INX; ++ break; ++ case 0x11://BC/MC in PS (HIQ) ++ addr = HIGH_QUEUE_INX; ++ break; ++ case 0x12: ++ addr = MGT_QUEUE_INX; ++ break; ++ default: ++ addr = BE_QUEUE_INX; ++ break; ++ ++ } ++ ++ return addr; ++ ++} ++ ++int urb_zero_packet_chk(_adapter *padapter, int sz) ++{ ++ int blnSetTxDescOffset; ++ struct dvobj_priv *pdvobj = (struct dvobj_priv*)&padapter->dvobjpriv; ++ ++ if ( pdvobj->ishighspeed ) ++ { ++ if ( ( (sz + TXDESC_SIZE) % 512 ) == 0 ) { ++ blnSetTxDescOffset = 1; ++ } else { ++ blnSetTxDescOffset = 0; ++ } ++ } ++ else ++ { ++ if ( ( (sz + TXDESC_SIZE) % 64 ) == 0 ) { ++ blnSetTxDescOffset = 1; ++ } else { ++ blnSetTxDescOffset = 0; ++ } ++ } ++ ++ return blnSetTxDescOffset; ++ ++} ++ ++void rtl8192cu_cal_txdesc_chksum(struct tx_desc *ptxdesc) ++{ ++ u16 *usPtr = (u16*)ptxdesc; ++ u32 count = 16; // (32 bytes / 2 bytes per XOR) => 16 times ++ u32 index; ++ u16 checksum = 0; ++ ++ //Clear first ++ ptxdesc->txdw7 &= cpu_to_le32(0xffff0000); ++ ++ for(index = 0 ; index < count ; index++){ ++ checksum = checksum ^ le16_to_cpu(*(usPtr + index)); ++ } ++ ++ ptxdesc->txdw7 |= cpu_to_le32(0x0000ffff&checksum); ++ ++} ++ ++void fill_txdesc_sectype(struct pkt_attrib *pattrib, struct tx_desc *ptxdesc) ++{ ++ if ((pattrib->encrypt > 0) && !pattrib->bswenc) ++ { ++ switch (pattrib->encrypt) ++ { ++ //SEC_TYPE ++ case _WEP40_: ++ case _WEP104_: ++ ptxdesc->txdw1 |= cpu_to_le32((0x01<<22)&0x00c00000); ++ break; ++ case _TKIP_: ++ case _TKIP_WTMIC_: ++ //ptxdesc->txdw1 |= cpu_to_le32((0x02<<22)&0x00c00000); ++ ptxdesc->txdw1 |= cpu_to_le32((0x01<<22)&0x00c00000); ++ break; ++ case _AES_: ++ ptxdesc->txdw1 |= cpu_to_le32((0x03<<22)&0x00c00000); ++ break; ++ case _NO_PRIVACY_: ++ default: ++ break; ++ ++ } ++ ++ } ++ ++} ++ ++void fill_txdesc_vcs(struct pkt_attrib *pattrib, u32 *pdw) ++{ ++ //DBG_8192C("cvs_mode=%d\n", pattrib->vcs_mode); ++ ++ switch(pattrib->vcs_mode) ++ { ++ case RTS_CTS: ++ *pdw |= cpu_to_le32(BIT(12)); ++ break; ++ case CTS_TO_SELF: ++ *pdw |= cpu_to_le32(BIT(11)); ++ break; ++ case NONE_VCS: ++ default: ++ break; ++ } ++ ++ if(pattrib->vcs_mode) ++ { ++ *pdw |= cpu_to_le32(BIT(13));//ENABLE HW RTS ++ } ++ ++} ++ ++void fill_txdesc_phy(struct pkt_attrib *pattrib, u32 *pdw) ++{ ++ //DBG_8192C("bwmode=%d, ch_off=%d\n", pattrib->bwmode, pattrib->ch_offset); ++ ++ if(pattrib->ht_en) ++ { ++ *pdw |= (pattrib->bwmode&HT_CHANNEL_WIDTH_40)? cpu_to_le32(BIT(25)):0; ++ ++ if(pattrib->ch_offset == HAL_PRIME_CHNL_OFFSET_LOWER) ++ *pdw |= cpu_to_le32((0x01<<20)&0x003f0000); ++ else if(pattrib->ch_offset == HAL_PRIME_CHNL_OFFSET_UPPER) ++ *pdw |= cpu_to_le32((0x02<<20)&0x003f0000); ++ else if(pattrib->ch_offset == HAL_PRIME_CHNL_OFFSET_DONT_CARE) ++ *pdw |= 0; ++ else ++ *pdw |= cpu_to_le32((0x03<<20)&0x003f0000); ++ } ++} ++ ++#ifdef CONFIG_USB_TX_AGGREGATION ++static void _update_txdesc(struct xmit_frame *pxmitframe, u8 *pmem, int sz) ++{ ++ uint qsel; ++ _adapter *padapter = pxmitframe->padapter; ++ struct ht_priv *phtpriv = &padapter->mlmepriv.htpriv; ++ struct mlme_ext_info *pmlmeinfo = &padapter->mlmeextpriv.mlmext_info; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); ++ struct dm_priv *pdmpriv = &pHalData->dmpriv; ++ struct pkt_attrib *pattrib = &pxmitframe->attrib; ++ sint bmcst = IS_MCAST(pattrib->ra); ++ struct tx_desc *ptxdesc = (struct tx_desc*)pmem; ++ ++ ++ _rtw_memset(ptxdesc, 0, sizeof(struct tx_desc)); ++ ++ //4 offset 0 ++ ptxdesc->txdw0 |= cpu_to_le32(sz & 0x0000ffff); ++ ptxdesc->txdw0 |= cpu_to_le32(OWN | FSG | LSG); ++ ptxdesc->txdw0 |= cpu_to_le32(((TXDESC_SIZE + OFFSET_SZ) << OFFSET_SHT) & 0x00ff0000);//32 bytes for TX Desc ++ ++ if (bmcst) ptxdesc->txdw0 |= cpu_to_le32(BIT(24)); ++ ++ RT_TRACE(_module_rtl871x_xmit_c_, _drv_info_, ++ ("update_txdesc: offset0=0x%08x\n", ptxdesc->txdw0)); ++ ++ //4 offset 4 ++ // pkt_offset, unit:8 bytes padding ++ if (pxmitframe->pkt_offset > 0) ++ ptxdesc->txdw1 |= cpu_to_le32((pxmitframe->pkt_offset << 26) & 0x7c000000); ++ ++#ifdef CONFIG_USB_TX_AGGREGATION ++ if (pxmitframe->agg_num > 1) ++ ptxdesc->txdw5 |= cpu_to_le32((pxmitframe->agg_num << 24) & 0xff000000); ++#endif ++ ++ if (pxmitframe->frame_tag == DATA_FRAMETAG) ++ { ++ //4 offset 4 ++ ptxdesc->txdw1 |= cpu_to_le32(pattrib->mac_id&0x1f); ++ ++ qsel = (uint)(pattrib->qsel & 0x0000001f); ++ ptxdesc->txdw1 |= cpu_to_le32((qsel << QSEL_SHT) & 0x00001f00); ++ ++ ptxdesc->txdw1 |= cpu_to_le32((pattrib->raid << 16) & 0x000f0000); ++ ++ fill_txdesc_sectype(pattrib, ptxdesc); ++ ++ if(pattrib->ampdu_en==_TRUE) ++ ptxdesc->txdw1 |= cpu_to_le32(BIT(5));//AGG EN ++ else ++ ptxdesc->txdw1 |= cpu_to_le32(BIT(6));//AGG BK ++ ++ ++ //4 offset 8 ++ ++ ++ //4 offset 12 ++ ptxdesc->txdw3 |= cpu_to_le32((pattrib->seqnum << 16) & 0xffff0000); ++ ++ ++ //4 offset 16 , offset 20 ++ if (pattrib->qos_en) ++ ptxdesc->txdw4 |= cpu_to_le32(BIT(6));//QoS ++ ++ if ((pattrib->ether_type != 0x888e) && ++ (pattrib->ether_type != 0x0806) && ++ (pattrib->dhcp_pkt != 1)) ++ { ++ //Non EAP & ARP & DHCP type data packet ++ ++ fill_txdesc_vcs(pattrib, &ptxdesc->txdw4); ++ fill_txdesc_phy(pattrib, &ptxdesc->txdw4); ++ ++ ptxdesc->txdw4 |= cpu_to_le32(0x00000008);//RTS Rate=24M ++ ptxdesc->txdw5 |= cpu_to_le32(0x0001ff00); ++ //ptxdesc->txdw5 |= cpu_to_le32(0x0000000b);//DataRate - 54M ++ ++ #ifdef SUPPORT_64_STA ++ if(pattrib->mac_id>FW_CTRL_MACID ){ ++ ptxdesc->txdw5 |= cpu_to_le32(pattrib->psta->init_rate); ++ ptxdesc->txdw4 |=cpu_to_le32(0x00000100); //USE RATE ++ ptxdesc->txdw3 |=cpu_to_le32(BIT(28)); //PKT_ID ++ //printk("%s pattrib->mac_id=%d ptxdesc->txdw3=0x%x,ptxdesc->txdw4=0x%x,ptxdesc->txdw5=0x%x\n",__FUNCTION__,pattrib->mac_id,ptxdesc->txdw3,ptxdesc->txdw4,ptxdesc->txdw5); ++ } ++ else //use REG_INIDATA_RATE_SEL value ++ ptxdesc->txdw5 |= cpu_to_le32(pdmpriv->INIDATA_RATE[pattrib->mac_id]); ++ if(pattrib->mac_id==1){ ++ //bcmc sta ++ ptxdesc->txdw5 |= cpu_to_le32(padapter->registrypriv.bcmc_rate); ++ ptxdesc->txdw4 |=cpu_to_le32(0x00000100); //USE RATE ++ } ++ #else //SUPPORT_64_STA ++ ++ //use REG_INIDATA_RATE_SEL value ++ ptxdesc->txdw5 |= cpu_to_le32(pdmpriv->INIDATA_RATE[pattrib->mac_id]); ++ #endif //SUPPORT_64_STA ++ ++ if (0)//for driver dbg ++ { ++ ptxdesc->txdw4 |= cpu_to_le32(BIT(8));//driver uses rate ++ ++ if (pattrib->ht_en) ++ ptxdesc->txdw5 |= cpu_to_le32(BIT(6));//SGI ++ ++ ptxdesc->txdw5 |= cpu_to_le32(0x00000013);//init rate - mcs7 ++ } ++ } ++ else ++ { ++ // EAP data packet and ARP packet. ++ // Use the 1M data rate to send the EAP/ARP packet. ++ // This will maybe make the handshake smooth. ++ ++ ptxdesc->txdw1 |= cpu_to_le32(BIT(6));//AGG BK ++ ptxdesc->txdw4 |= cpu_to_le32(BIT(8));//driver uses rate ++ } ++ ++ ++ //4 offset 24 ++#ifdef CONFIG_TCP_CSUM_OFFLOAD_TX ++ if (pattrib->hw_tcp_csum == 1) { ++ // ptxdesc->txdw6 = 0; // clear TCP_CHECKSUM and IP_CHECKSUM. It's zero already!! ++ u8 ip_hdr_offset = 32 + pattrib->hdrlen + pattrib->iv_len + 8; ++ ptxdesc->txdw7 = (1 << 31) | (ip_hdr_offset << 16); ++ DBG_8192C("ptxdesc->txdw7 = %08x\n", ptxdesc->txdw7); ++ } ++#endif ++ } ++ else if(pxmitframe->frame_tag == MGNT_FRAMETAG) ++ { ++ //DBG_8192C("pxmitframe->frame_tag == MGNT_FRAMETAG\n"); ++ ++ //4 offset 4 ++ ptxdesc->txdw1 |= cpu_to_le32(pattrib->mac_id&0x1f); ++ ++ qsel = (uint)(pattrib->qsel&0x0000001f); ++ ptxdesc->txdw1 |= cpu_to_le32((qsel << QSEL_SHT) & 0x00001f00); ++ ++ ptxdesc->txdw1 |= cpu_to_le32((pattrib->raid<< 16) & 0x000f0000); ++ ++ //fill_txdesc_sectype(pattrib, ptxdesc); ++ ++ ++ //4 offset 8 ++ ++ ++ //4 offset 12 ++ ptxdesc->txdw3 |= cpu_to_le32((pattrib->seqnum<<16)&0xffff0000); ++ ++ ++ //4 offset 16 ++ ptxdesc->txdw4 |= cpu_to_le32(BIT(8));//driver uses rate ++ ++ ++ //4 offset 20 ++ } ++ else if(pxmitframe->frame_tag == TXAGG_FRAMETAG) ++ { ++ DBG_8192C("pxmitframe->frame_tag == TXAGG_FRAMETAG\n"); ++ } ++ else ++ { ++ DBG_8192C("pxmitframe->frame_tag = %d\n", pxmitframe->frame_tag); ++ ++ //4 offset 4 ++ ptxdesc->txdw1 |= cpu_to_le32((4)&0x1f);//CAM_ID(MAC_ID) ++ ++ ptxdesc->txdw1 |= cpu_to_le32((6<< 16) & 0x000f0000);//raid ++ ++ ++ //4 offset 8 ++ ++ ++ //4 offset 12 ++ ptxdesc->txdw3 |= cpu_to_le32((pattrib->seqnum << 16) & 0xffff0000); ++ ++ ++ //4 offset 16 ++ ptxdesc->txdw4 |= cpu_to_le32(BIT(8));//driver uses rate ++ ++ ++ //4 offset 20 ++ } ++ ++ // 2009.11.05. tynli_test. Suggested by SD4 Filen for FW LPS. ++ // (1) The sequence number of each non-Qos frame / broadcast / multicast / ++ // mgnt frame should be controled by Hw because Fw will also send null data ++ // which we cannot control when Fw LPS enable. ++ // --> default enable non-Qos data sequense number. 2010.06.23. by tynli. ++ // (2) Enable HW SEQ control for beacon packet, because we use Hw beacon. ++ // (3) Use HW Qos SEQ to control the seq num of Ext port non-Qos packets. ++ // 2010.06.23. Added by tynli. ++ if(!pattrib->qos_en) ++ { ++ ptxdesc->txdw4 |= cpu_to_le32(BIT(7)); // Hw set sequence number ++ ptxdesc->txdw3 |= cpu_to_le32((8 <<28)); //set bit3 to 1. Suugested by TimChen. 2009.12.29. ++ } ++ ++ rtl8192cu_cal_txdesc_chksum(ptxdesc); ++} ++#endif ++ ++static s32 update_txdesc(struct xmit_frame *pxmitframe, u8 *pmem, s32 sz) ++{ ++ int pull=0; ++ uint qsel; ++ _adapter *padapter = pxmitframe->padapter; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct pkt_attrib *pattrib = &pxmitframe->attrib; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); ++ struct dm_priv *pdmpriv = &pHalData->dmpriv; ++ struct tx_desc *ptxdesc = (struct tx_desc *)pmem; ++ struct ht_priv *phtpriv = &pmlmepriv->htpriv; ++ struct mlme_ext_info *pmlmeinfo = &padapter->mlmeextpriv.mlmext_info; ++ sint bmcst = IS_MCAST(pattrib->ra); ++#ifdef CONFIG_P2P ++ struct wifidirect_info* pwdinfo = &padapter->wdinfo; ++#endif //CONFIG_P2P ++ ++#ifndef CONFIG_USE_USB_BUFFER_ALLOC_TX ++ if(urb_zero_packet_chk(padapter, sz)==0) ++ { ++ ptxdesc = (struct tx_desc *)(pmem+PACKET_OFFSET_SZ); ++ pull = 1; ++ } ++#endif // CONFIG_USE_USB_BUFFER_ALLOC_TX ++ ++ _rtw_memset(ptxdesc, 0, sizeof(struct tx_desc)); ++ ++ if((pxmitframe->frame_tag&0x0f) == DATA_FRAMETAG) ++ { ++ //DBG_8192C("pxmitframe->frame_tag == DATA_FRAMETAG\n"); ++ ++ //offset 4 ++ ptxdesc->txdw1 |= cpu_to_le32(pattrib->mac_id&0x1f); ++ ++ qsel = (uint)(pattrib->qsel & 0x0000001f); ++ ptxdesc->txdw1 |= cpu_to_le32((qsel << QSEL_SHT) & 0x00001f00); ++ ++ ptxdesc->txdw1 |= cpu_to_le32((pattrib->raid<< 16) & 0x000f0000); ++ ++ fill_txdesc_sectype(pattrib, ptxdesc); ++ ++ ++ if(pattrib->ampdu_en==_TRUE) ++ ptxdesc->txdw1 |= cpu_to_le32(BIT(5));//AGG EN ++ else ++ ptxdesc->txdw1 |= cpu_to_le32(BIT(6));//AGG BK ++ ++ //offset 8 ++ ++ ++ //offset 12 ++ ptxdesc->txdw3 |= cpu_to_le32((pattrib->seqnum<<16)&0xffff0000); ++ ++ ++ //offset 16 , offset 20 ++ if (pattrib->qos_en) ++ ptxdesc->txdw4 |= cpu_to_le32(BIT(6));//QoS ++ ++ if ((pattrib->ether_type != 0x888e) && (pattrib->ether_type != 0x0806) && (pattrib->dhcp_pkt != 1)) ++ { ++ //Non EAP & ARP & DHCP type data packet ++ ++ fill_txdesc_vcs(pattrib, &ptxdesc->txdw4); ++ fill_txdesc_phy(pattrib, &ptxdesc->txdw4); ++ ++ ptxdesc->txdw4 |= cpu_to_le32(0x00000008);//RTS Rate=24M ++ ptxdesc->txdw5 |= cpu_to_le32(0x0001ff00);// ++ //ptxdesc->txdw5 |= cpu_to_le32(0x0000000b);//DataRate - 54M ++ ++ ++ #ifdef SUPPORT_64_STA ++ if(pattrib->mac_id>=FW_CTRL_MACID ){ ++ ptxdesc->txdw5 |= cpu_to_le32(pattrib->psta->init_rate); ++ ptxdesc->txdw4 |=cpu_to_le32(0x00000100); //USE RATE ++ ptxdesc->txdw3 |=cpu_to_le32(BIT(28)); //PKT_ID ++ //printk("%s pattrib->mac_id=%d\n",__FUNCTION__,pattrib->mac_id); ++ //printk("%s pattrib->mac_id=%d ptxdesc->txdw1=0x%x,ptxdesc->txdw3=0x%x,\nptxdesc->txdw4=0x%x,ptxdesc->txdw5=0x%x\n",__FUNCTION__,pattrib->mac_id,ptxdesc->txdw1,ptxdesc->txdw3,ptxdesc->txdw4,ptxdesc->txdw5); ++ } ++ else //use REG_INIDATA_RATE_SEL value ++ ptxdesc->txdw5 |= cpu_to_le32(pdmpriv->INIDATA_RATE[pattrib->mac_id]); ++ if(pattrib->mac_id==1){ ++ //bcmc sta ++ ptxdesc->txdw5 |= cpu_to_le32(padapter->registrypriv.bcmc_rate); ++ ptxdesc->txdw4 |=cpu_to_le32(0x00000100); //USE RATE ++ } ++ #else //SUPPORT_64_STA ++ //use REG_INIDATA_RATE_SEL value ++ ptxdesc->txdw5 |= cpu_to_le32(pdmpriv->INIDATA_RATE[pattrib->mac_id]); ++ #endif //SUPPORT_64_STA ++ if(0)//for driver dbg ++ { ++ ptxdesc->txdw4 |= cpu_to_le32(BIT(8));//driver uses rate ++ ++ if(pattrib->ht_en) ++ ptxdesc->txdw5 |= cpu_to_le32(BIT(6));//SGI ++ ++ ptxdesc->txdw5 |= cpu_to_le32(0x00000013);//init rate - mcs7 ++ } ++ ++ } ++ else ++ { ++ // EAP data packet and ARP packet. ++ // Use the 1M data rate to send the EAP/ARP packet. ++ // This will maybe make the handshake smooth. ++ ++ ptxdesc->txdw1 |= cpu_to_le32(BIT(6));//AGG BK ++ ++ ptxdesc->txdw4 |= cpu_to_le32(BIT(8));//driver uses rate ++ ++#ifdef CONFIG_P2P ++ // Added by Albert 2011/03/22 ++ // In the P2P mode, the driver should not support the b mode. ++ // So, the Tx packet shouldn't use the CCK rate ++ if(!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) ++ { ++ ptxdesc->txdw5 |= cpu_to_le32( 0x04 ); // Use the 6M data rate. ++ } ++#endif //CONFIG_P2P ++ ++ } ++ ++ //offset 24 ++ ++#ifdef CONFIG_TCP_CSUM_OFFLOAD_TX ++ if ( pattrib->hw_tcp_csum == 1 ) { ++ // ptxdesc->txdw6 = 0; // clear TCP_CHECKSUM and IP_CHECKSUM. It's zero already!! ++ u8 ip_hdr_offset = 32 + pattrib->hdrlen + pattrib->iv_len + 8; ++ ptxdesc->txdw7 = (1 << 31) | (ip_hdr_offset << 16); ++ DBG_8192C("ptxdesc->txdw7 = %08x\n", ptxdesc->txdw7); ++ } ++#endif ++ } ++ else if((pxmitframe->frame_tag&0x0f)== MGNT_FRAMETAG) ++ { ++ //DBG_8192C("pxmitframe->frame_tag == MGNT_FRAMETAG\n"); ++ ++ //offset 4 ++ ptxdesc->txdw1 |= cpu_to_le32(pattrib->mac_id&0x1f); ++ ++ qsel = (uint)(pattrib->qsel&0x0000001f); ++ ptxdesc->txdw1 |= cpu_to_le32((qsel<txdw1 |= cpu_to_le32((pattrib->raid<< 16) & 0x000f0000); ++ ++ //fill_txdesc_sectype(pattrib, ptxdesc); ++ ++ //offset 8 ++ ++ //offset 12 ++ ptxdesc->txdw3 |= cpu_to_le32((pattrib->seqnum<<16)&0xffff0000); ++ ++ //offset 16 ++ ptxdesc->txdw4 |= cpu_to_le32(BIT(8));//driver uses rate ++ ++ //offset 20 ++ ptxdesc->txdw5 |= cpu_to_le32(BIT(17));//retry limit enable ++ if(pattrib->retry_ctrl == _TRUE) ++ ptxdesc->txdw5 |= cpu_to_le32(0x00180000);//retry limit = 6 ++ else ++ ptxdesc->txdw5 |= cpu_to_le32(0x00300000);//retry limit = 12 ++ ++#ifdef CONFIG_P2P ++ // Added by Albert 2011/03/17 ++ // In the P2P mode, the driver should not support the b mode. ++ // So, the Tx packet shouldn't use the CCK rate ++ if(!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) ++ { ++ ptxdesc->txdw5 |= cpu_to_le32( 0x04 ); // Use the 6M data rate. ++ } ++#endif //CONFIG_P2P ++ ++#ifdef CONFIG_INTEL_PROXIM ++ if((padapter->proximity.proxim_on==_TRUE)&&(pattrib->intel_proxim==_TRUE)){ ++ printk("\n %s pattrib->rate=%d\n",__FUNCTION__,pattrib->rate); ++ ptxdesc->txdw5 |= cpu_to_le32( pattrib->rate); ++ } ++#endif ++ } ++ else if((pxmitframe->frame_tag&0x0f) == TXAGG_FRAMETAG) ++ { ++ DBG_8192C("pxmitframe->frame_tag == TXAGG_FRAMETAG\n"); ++ } ++#ifdef CONFIG_MP_INCLUDED ++ else if((pxmitframe->frame_tag&0x0f) == MP_FRAMETAG) ++ { ++ fill_txdesc_for_mp(padapter, ptxdesc); ++ } ++#endif ++ else ++ { ++ DBG_8192C("pxmitframe->frame_tag = %d\n", pxmitframe->frame_tag); ++ ++ //offset 4 ++ ptxdesc->txdw1 |= cpu_to_le32((4)&0x1f);//CAM_ID(MAC_ID) ++ ++ ptxdesc->txdw1 |= cpu_to_le32((6<< 16) & 0x000f0000);//raid ++ ++ //offset 8 ++ ++ //offset 12 ++ ptxdesc->txdw3 |= cpu_to_le32((pattrib->seqnum<<16)&0xffff0000); ++ ++ //offset 16 ++ ptxdesc->txdw4 |= cpu_to_le32(BIT(8));//driver uses rate ++ ++ //offset 20 ++ } ++ ++ // 2009.11.05. tynli_test. Suggested by SD4 Filen for FW LPS. ++ // (1) The sequence number of each non-Qos frame / broadcast / multicast / ++ // mgnt frame should be controled by Hw because Fw will also send null data ++ // which we cannot control when Fw LPS enable. ++ // --> default enable non-Qos data sequense number. 2010.06.23. by tynli. ++ // (2) Enable HW SEQ control for beacon packet, because we use Hw beacon. ++ // (3) Use HW Qos SEQ to control the seq num of Ext port non-Qos packets. ++ // 2010.06.23. Added by tynli. ++ if(!pattrib->qos_en) ++ { ++ ptxdesc->txdw4 |= cpu_to_le32(BIT(7)); // Hw set sequence number ++ ptxdesc->txdw3 |= cpu_to_le32((8 <<28)); //set bit3 to 1. Suugested by TimChen. 2009.12.29. ++ } ++ ++ //offset 0 ++ ptxdesc->txdw0 |= cpu_to_le32(sz&0x0000ffff); ++ ptxdesc->txdw0 |= cpu_to_le32(OWN | FSG | LSG); ++ ptxdesc->txdw0 |= cpu_to_le32(((TXDESC_SIZE+OFFSET_SZ)<txdw0 |= cpu_to_le32(BIT(24)); ++ } ++ ++ RT_TRACE(_module_rtl871x_xmit_c_,_drv_info_,("offset0-txdesc=0x%x\n", ptxdesc->txdw0)); ++ ++ //offset 4 ++ if(!pull) ptxdesc->txdw1 |= cpu_to_le32((0x01<<26)&0xff000000);//pkt_offset, unit:8 bytes padding ++ ++ rtl8192cu_cal_txdesc_chksum(ptxdesc); ++ ++ return pull; ++ ++} ++ ++static void _rtw_dump_xframe(_adapter *padapter, struct xmit_frame *pxmitframe, u8 sync) ++{ ++ int t, sz, w_sz, pull=0; ++ u8 *mem_addr; ++ u32 ff_hwaddr; ++ struct xmit_buf *pxmitbuf = pxmitframe->pxmitbuf; ++ struct pkt_attrib *pattrib = &pxmitframe->attrib; ++ struct xmit_priv *pxmitpriv = &padapter->xmitpriv; ++ struct security_priv *psecuritypriv = &padapter->securitypriv; ++ ++ if ((pxmitframe->frame_tag == DATA_FRAMETAG) && ++ (pxmitframe->attrib.ether_type != 0x0806) && ++ (pxmitframe->attrib.ether_type != 0x888e) && ++ (pxmitframe->attrib.dhcp_pkt != 1)) ++ { ++ rtw_issue_addbareq_cmd(padapter, pxmitframe); ++ } ++ ++ mem_addr = pxmitframe->buf_addr; ++ ++ RT_TRACE(_module_rtl871x_xmit_c_,_drv_info_,("rtw_dump_xframe()\n")); ++ ++ for (t = 0; t < pattrib->nr_frags; t++) ++ { ++ if (t != (pattrib->nr_frags - 1)) ++ { ++ RT_TRACE(_module_rtl871x_xmit_c_,_drv_err_,("pattrib->nr_frags=%d\n", pattrib->nr_frags)); ++ ++ sz = pxmitpriv->frag_len; ++ sz = sz - 4 - (psecuritypriv->sw_encrypt ? 0 : pattrib->icv_len); ++ } ++ else //no frag ++ { ++ sz = pattrib->last_txcmdsz; ++ } ++ ++ pull = update_txdesc(pxmitframe, mem_addr, sz); ++ ++ if(pull) ++ { ++ mem_addr += PACKET_OFFSET_SZ; //pull txdesc head ++ ++ //pxmitbuf ->pbuf = mem_addr; ++ pxmitframe->buf_addr = mem_addr; ++ ++ w_sz = sz + TXDESC_SIZE; ++ } ++ else ++ { ++ w_sz = sz + TXDESC_SIZE + PACKET_OFFSET_SZ; ++ } ++ ++ ff_hwaddr = rtw_get_ff_hwaddr(pxmitframe); ++ ++ if(sync == _TRUE) ++ rtw_write_port_sync(padapter, ff_hwaddr, w_sz, (unsigned char*)pxmitbuf); ++ else ++ rtw_write_port(padapter, ff_hwaddr, w_sz, (unsigned char*)pxmitbuf); ++ ++ rtw_count_tx_stats(padapter, pxmitframe, sz); ++ ++ ++ RT_TRACE(_module_rtl871x_xmit_c_,_drv_info_,("rtw_write_port, w_sz=%d\n", w_sz)); ++ //DBG_8192C("rtw_write_port, w_sz=%d, sz=%d, txdesc_sz=%d, tid=%d\n", w_sz, sz, w_sz-sz, pattrib->priority); ++ ++ mem_addr += w_sz; ++ ++ mem_addr = (u8 *)RND4(((SIZE_PTR)(mem_addr))); ++ ++ } ++ ++ rtw_free_xmitframe_ex(pxmitpriv, pxmitframe); ++ ++} ++ ++inline void rtw_dump_xframe(_adapter *padapter, struct xmit_frame *pxmitframe) ++{ ++ _rtw_dump_xframe(padapter, pxmitframe, _FALSE); ++} ++ ++inline void rtw_dump_xframe_sync(_adapter *padapter, struct xmit_frame *pxmitframe) ++{ ++ _rtw_dump_xframe(padapter, pxmitframe, _TRUE); ++} ++ ++#ifdef CONFIG_USB_TX_AGGREGATION ++static u32 xmitframe_need_length(struct xmit_frame *pxmitframe) ++{ ++ struct pkt_attrib *pattrib = &pxmitframe->attrib; ++ ++ u32 len = 0; ++ ++ // no consider fragement ++ len = pattrib->hdrlen + pattrib->iv_len + ++ SNAP_SIZE + sizeof(u16) + ++ pattrib->pktlen + ++ ((pattrib->bswenc) ? pattrib->icv_len : 0); ++ ++ if(pattrib->encrypt ==_TKIP_) ++ len += 8; ++ ++ return len; ++} ++ ++#define IDEA_CONDITION 1 // check all packets before enqueue ++s32 rtl8192cu_xmitframe_complete(_adapter *padapter, struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); ++ struct xmit_frame *pxmitframe = NULL; ++ struct xmit_frame *pfirstframe = NULL; ++ ++ // aggregate variable ++// struct hw_xmit *phwxmit; ++ struct sta_info *psta = NULL; ++ struct tx_servq *ptxservq = NULL; ++ ++ _irqL irqL; ++ _list *xmitframe_plist = NULL, *xmitframe_phead = NULL; ++ ++ u32 pbuf; // next pkt address ++ u32 pbuf_tail; // last pkt tail ++ u32 len; // packet length, except TXDESC_SIZE and PKT_OFFSET ++ ++ u32 bulkSize = pHalData->UsbBulkOutSize; ++ u8 descCount; ++ u32 bulkPtr; ++ ++ // dump frame variable ++ u32 ff_hwaddr; ++ ++#ifndef IDEA_CONDITION ++ int res = _SUCCESS; ++#endif ++ ++ RT_TRACE(_module_rtl8192c_xmit_c_, _drv_info_, ("+xmitframe_complete\n")); ++ ++ ++ // check xmitbuffer is ok ++ if (pxmitbuf == NULL) { ++ pxmitbuf = rtw_alloc_xmitbuf(pxmitpriv); ++ if (pxmitbuf == NULL) return _FALSE; ++ } ++ ++ ++ //3 1. pick up first frame ++ do { ++ rtw_free_xmitframe_ex(pxmitpriv, pxmitframe); ++ ++ pxmitframe = rtw_dequeue_xframe(pxmitpriv, pxmitpriv->hwxmits, pxmitpriv->hwxmit_entry); ++ if (pxmitframe == NULL) { ++ // no more xmit frame, release xmit buffer ++ rtw_free_xmitbuf(pxmitpriv, pxmitbuf); ++ return _FALSE; ++ } ++ ++ ++#ifndef IDEA_CONDITION ++ if (pxmitframe->frame_tag != DATA_FRAMETAG) { ++ RT_TRACE(_module_rtl8192c_xmit_c_, _drv_err_, ++ ("xmitframe_complete: frame tag(%d) is not DATA_FRAMETAG(%d)!\n", ++ pxmitframe->frame_tag, DATA_FRAMETAG)); ++// rtw_free_xmitframe_ex(pxmitpriv, pxmitframe); ++ continue; ++ } ++ ++ // TID 0~15 ++ if ((pxmitframe->attrib.priority < 0) || ++ (pxmitframe->attrib.priority > 15)) { ++ RT_TRACE(_module_rtl8192c_xmit_c_, _drv_err_, ++ ("xmitframe_complete: TID(%d) should be 0~15!\n", ++ pxmitframe->attrib.priority)); ++// rtw_free_xmitframe_ex(pxmitpriv, pxmitframe); ++ continue; ++ } ++#endif ++ ++ pxmitframe->pxmitbuf = pxmitbuf; ++ pxmitframe->buf_addr = pxmitbuf->pbuf; ++ pxmitbuf->priv_data = pxmitframe; ++ ++ //pxmitframe->agg_num = 1; // alloc xmitframe should assign to 1. ++ pxmitframe->pkt_offset = 1; // first frame of aggregation, reserve offset ++ ++#ifdef IDEA_CONDITION ++ rtw_xmitframe_coalesce(padapter, pxmitframe->pkt, pxmitframe); ++#else ++ res = rtw_xmitframe_coalesce(padapter, pxmitframe->pkt, pxmitframe); ++ if (res == _FALSE) { ++// rtw_free_xmitframe_ex(pxmitpriv, pxmitframe); ++ continue; ++ } ++#endif ++ ++ // always return ndis_packet after rtw_xmitframe_coalesce ++ rtw_os_xmit_complete(padapter, pxmitframe); ++ ++ break; ++ } while (1); ++ ++ //3 2. aggregate same priority and same DA(AP or STA) frames ++ pfirstframe = pxmitframe; ++ len = xmitframe_need_length(pfirstframe) + TXDESC_OFFSET; ++ pbuf_tail = len; ++ pbuf = _RND8(pbuf_tail); ++ ++ // check pkt amount in one bluk ++ descCount = 0; ++ bulkPtr = bulkSize; ++ if (pbuf < bulkPtr) ++ descCount++; ++ else { ++ descCount = 0; ++ bulkPtr = ((pbuf / bulkSize) + 1) * bulkSize; // round to next bulkSize ++ } ++ ++ // dequeue same priority packet from station tx queue ++ psta = pfirstframe->attrib.psta; ++ switch (pfirstframe->attrib.priority) { ++ case 1: ++ case 2: ++ ptxservq = &(psta->sta_xmitpriv.bk_q); ++// phwxmit = pxmitpriv->hwxmits + 3; ++ break; ++ ++ case 4: ++ case 5: ++ ptxservq = &(psta->sta_xmitpriv.vi_q); ++// phwxmit = pxmitpriv->hwxmits + 1; ++ break; ++ ++ case 6: ++ case 7: ++ ptxservq = &(psta->sta_xmitpriv.vo_q); ++// phwxmit = pxmitpriv->hwxmits; ++ break; ++ ++ case 0: ++ case 3: ++ default: ++ ptxservq = &(psta->sta_xmitpriv.be_q); ++// phwxmit = pxmitpriv->hwxmits + 2; ++ break; ++ } ++ ++ _enter_critical_bh(&pxmitpriv->lock, &irqL); ++ ++ xmitframe_phead = get_list_head(&ptxservq->sta_pending); ++ xmitframe_plist = get_next(xmitframe_phead); ++ while (rtw_end_of_queue_search(xmitframe_phead, xmitframe_plist) == _FALSE) ++ { ++ pxmitframe = LIST_CONTAINOR(xmitframe_plist, struct xmit_frame, list); ++ xmitframe_plist = get_next(xmitframe_plist); ++ ++ len = xmitframe_need_length(pxmitframe) + TXDESC_SIZE; // no offset ++ if (pbuf + len > MAX_XMITBUF_SZ) break; ++ ++ rtw_list_delete(&pxmitframe->list); ++ ptxservq->qcnt--; ++ ++#ifndef IDEA_CONDITION ++ // suppose only data frames would be in queue ++ if (pxmitframe->frame_tag != DATA_FRAMETAG) { ++ RT_TRACE(_module_rtl8192c_xmit_c_, _drv_err_, ++ ("xmitframe_complete: frame tag(%d) is not DATA_FRAMETAG(%d)!\n", ++ pxmitframe->frame_tag, DATA_FRAMETAG)); ++ rtw_free_xmitframe_ex(pxmitpriv, pxmitframe); ++ continue; ++ } ++ ++ // TID 0~15 ++ if ((pxmitframe->attrib.priority < 0) || ++ (pxmitframe->attrib.priority > 15)) { ++ RT_TRACE(_module_rtl8192c_xmit_c_, _drv_err_, ++ ("xmitframe_complete: TID(%d) should be 0~15!\n", ++ pxmitframe->attrib.priority)); ++ rtw_free_xmitframe_ex(pxmitpriv, pxmitframe); ++ continue; ++ } ++#endif ++ ++// pxmitframe->pxmitbuf = pxmitbuf; ++ pxmitframe->buf_addr = pxmitbuf->pbuf + pbuf; ++ ++ pxmitframe->agg_num = 0; // not first frame of aggregation ++ pxmitframe->pkt_offset = 0; // not first frame of aggregation, no need to reserve offset ++ ++#ifdef IDEA_CONDITION ++ rtw_xmitframe_coalesce(padapter, pxmitframe->pkt, pxmitframe); ++#else ++ res = rtw_xmitframe_coalesce(padapter, pxmitframe->pkt, pxmitframe); ++ if (res == _FALSE) { ++ rtw_free_xmitframe_ex(pxmitpriv, pxmitframe); ++ continue; ++ } ++#endif ++ ++ // always return ndis_packet after rtw_xmitframe_coalesce ++ rtw_os_xmit_complete(padapter, pxmitframe); ++ ++ // (len - TXDESC_SIZE) == pxmitframe->attrib.last_txcmdsz ++ _update_txdesc(pxmitframe, pxmitframe->buf_addr, pxmitframe->attrib.last_txcmdsz); ++ ++ // don't need xmitframe any more ++ rtw_free_xmitframe_ex(pxmitpriv, pxmitframe); ++ ++ // handle pointer and stop condition ++ pbuf_tail = pbuf + len; ++ pbuf = _RND8(pbuf_tail); ++ ++ pfirstframe->agg_num++; ++ if (MAX_TX_AGG_PACKET_NUMBER == pfirstframe->agg_num) ++ break; ++ ++ if (pbuf < bulkPtr) { ++ descCount++; ++ if (descCount == pHalData->UsbTxAggDescNum) ++ break; ++ } else { ++ descCount = 0; ++ bulkPtr = ((pbuf / bulkSize) + 1) * bulkSize; ++ } ++ } ++ if (_rtw_queue_empty(&ptxservq->sta_pending) == _TRUE) ++ rtw_list_delete(&ptxservq->tx_pending); ++ ++ _exit_critical_bh(&pxmitpriv->lock, &irqL); ++ ++ if ((pfirstframe->attrib.ether_type != 0x0806) && ++ (pfirstframe->attrib.ether_type != 0x888e) && ++ (pfirstframe->attrib.dhcp_pkt != 1)) ++ { ++ rtw_issue_addbareq_cmd(padapter, pfirstframe); ++ } ++ ++#ifndef CONFIG_USE_USB_BUFFER_ALLOC_TX ++ //3 3. update first frame txdesc ++ if ((pbuf_tail % bulkSize) == 0) { ++ // remove pkt_offset ++ pbuf_tail -= PACKET_OFFSET_SZ; ++ pfirstframe->buf_addr += PACKET_OFFSET_SZ; ++ pfirstframe->pkt_offset = 0; ++ } ++#endif // CONFIG_USE_USB_BUFFER_ALLOC_TX ++ _update_txdesc(pfirstframe, pfirstframe->buf_addr, pfirstframe->attrib.last_txcmdsz); ++ ++ //3 4. write xmit buffer to USB FIFO ++ ff_hwaddr = rtw_get_ff_hwaddr(pfirstframe); ++ ++ // xmit address == ((xmit_frame*)pxmitbuf->priv_data)->buf_addr ++ rtw_write_port(padapter, ff_hwaddr, pbuf_tail, (u8*)pxmitbuf); ++ ++ ++ //3 5. update statisitc ++ pbuf_tail -= (pfirstframe->agg_num * TXDESC_SIZE); ++ if (pfirstframe->pkt_offset == 1) pbuf_tail -= PACKET_OFFSET_SZ; ++ ++ rtw_count_tx_stats(padapter, pfirstframe, pbuf_tail); ++ ++ rtw_free_xmitframe_ex(pxmitpriv, pfirstframe); ++ ++ return _TRUE; ++} ++ ++#else ++ ++s32 rtl8192cu_xmitframe_complete(_adapter *padapter, struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf) ++{ ++ ++ struct hw_xmit *phwxmits; ++ sint hwentry; ++ struct xmit_frame *pxmitframe=NULL; ++ int res=_SUCCESS, xcnt = 0; ++ ++ phwxmits = pxmitpriv->hwxmits; ++ hwentry = pxmitpriv->hwxmit_entry; ++ ++ RT_TRACE(_module_rtl871x_xmit_c_,_drv_info_,("xmitframe_complete()\n")); ++ ++ if(pxmitbuf==NULL) ++ { ++ pxmitbuf = rtw_alloc_xmitbuf(pxmitpriv); ++ if(!pxmitbuf) ++ { ++ return _FALSE; ++ } ++ } ++ ++ ++ do ++ { ++ pxmitframe = rtw_dequeue_xframe(pxmitpriv, phwxmits, hwentry); ++ ++ if(pxmitframe) ++ { ++ pxmitframe->pxmitbuf = pxmitbuf; ++ ++ pxmitframe->buf_addr = pxmitbuf->pbuf; ++ ++ pxmitbuf->priv_data = pxmitframe; ++ ++ if((pxmitframe->frame_tag&0x0f) == DATA_FRAMETAG) ++ { ++ if(pxmitframe->attrib.priority<=15)//TID0~15 ++ { ++ res = rtw_xmitframe_coalesce(padapter, pxmitframe->pkt, pxmitframe); ++ } ++ ++ rtw_os_xmit_complete(padapter, pxmitframe);//always return ndis_packet after rtw_xmitframe_coalesce ++ } ++ ++ ++ RT_TRACE(_module_rtl871x_xmit_c_,_drv_info_,("xmitframe_complete(): rtw_dump_xframe\n")); ++ ++ ++ if(res == _SUCCESS) ++ { ++ rtw_dump_xframe(padapter, pxmitframe); ++ } ++ else ++ { ++ rtw_free_xmitbuf(pxmitpriv, pxmitbuf); ++ rtw_free_xmitframe_ex(pxmitpriv, pxmitframe); ++ } ++ ++ xcnt++; ++ ++ } ++ else ++ { ++ rtw_free_xmitbuf(pxmitpriv, pxmitbuf); ++ return _FALSE; ++ } ++ ++ break; ++ ++ }while(0/*xcnt < (NR_XMITFRAME >> 3)*/); ++ ++ return _TRUE; ++ ++} ++#endif ++ ++ ++ ++static s32 xmitframe_direct(_adapter *padapter, struct xmit_frame *pxmitframe) ++{ ++ s32 res = _SUCCESS; ++ ++ ++ res = rtw_xmitframe_coalesce(padapter, pxmitframe->pkt, pxmitframe); ++ if (res == _SUCCESS) { ++ rtw_dump_xframe(padapter, pxmitframe); ++ } ++ ++ return res; ++} ++ ++/* ++ * Return ++ * _TRUE dump packet directly ++ * _FALSE enqueue packet ++ */ ++static s32 pre_xmitframe(_adapter *padapter, struct xmit_frame *pxmitframe) ++{ ++ _irqL irqL; ++ s32 res; ++ struct xmit_buf *pxmitbuf = NULL; ++ struct xmit_priv *pxmitpriv = &padapter->xmitpriv; ++ struct pkt_attrib *pattrib = &pxmitframe->attrib; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ ++ _enter_critical_bh(&pxmitpriv->lock, &irqL); ++ ++ if (rtw_txframes_sta_ac_pending(padapter, pattrib) > 0) ++ goto enqueue; ++ ++ if (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY) == _TRUE) ++ goto enqueue; ++ ++ ++ pxmitbuf = rtw_alloc_xmitbuf(pxmitpriv); ++ if (pxmitbuf == NULL) ++ goto enqueue; ++ ++ _exit_critical_bh(&pxmitpriv->lock, &irqL); ++ ++ pxmitframe->pxmitbuf = pxmitbuf; ++ pxmitframe->buf_addr = pxmitbuf->pbuf; ++ pxmitbuf->priv_data = pxmitframe; ++ ++ if (xmitframe_direct(padapter, pxmitframe) != _SUCCESS) { ++ rtw_free_xmitbuf(pxmitpriv, pxmitbuf); ++ rtw_free_xmitframe_ex(pxmitpriv, pxmitframe); ++ } ++ ++ return _TRUE; ++ ++enqueue: ++ res = rtw_xmitframe_enqueue(padapter, pxmitframe); ++ _exit_critical_bh(&pxmitpriv->lock, &irqL); ++ ++ if (res != _SUCCESS) { ++ RT_TRACE(_module_xmit_osdep_c_, _drv_err_, ("pre_xmitframe: enqueue xmitframe fail\n")); ++ rtw_free_xmitframe_ex(pxmitpriv, pxmitframe); ++ ++ // Trick, make the statistics correct ++ pxmitpriv->tx_pkts--; ++ pxmitpriv->tx_drop++; ++ return _TRUE; ++ } ++ ++ return _FALSE; ++} ++ ++void rtl8192cu_mgnt_xmit(_adapter *padapter, struct xmit_frame *pmgntframe) ++{ ++ rtw_dump_xframe(padapter, pmgntframe); ++} ++ ++/* ++ * Return ++ * _TRUE dump packet directly ok ++ * _FALSE temporary can't transmit packets to hardware ++ */ ++s32 rtl8192cu_hal_xmit(_adapter *padapter, struct xmit_frame *pxmitframe) ++{ ++ return pre_xmitframe(padapter, pxmitframe); ++} ++ ++#ifdef CONFIG_HOSTAPD_MLME ++ ++static void rtl8192cu_hostap_mgnt_xmit_cb(struct urb *urb) ++{ ++#ifdef PLATFORM_LINUX ++ struct sk_buff *skb = (struct sk_buff *)urb->context; ++ ++ //DBG_8192C("%s\n", __FUNCTION__); ++ ++ dev_kfree_skb_any(skb); ++#endif ++} ++ ++s32 rtl8192cu_hostap_mgnt_xmit_entry(_adapter *padapter, _pkt *pkt) ++{ ++#ifdef PLATFORM_LINUX ++ u16 fc; ++ int rc, len, pipe; ++ unsigned int bmcst, tid, qsel; ++ struct sk_buff *skb, *pxmit_skb; ++ struct urb *urb; ++ unsigned char *pxmitbuf; ++ struct tx_desc *ptxdesc; ++ struct rtw_ieee80211_hdr *tx_hdr; ++ struct hostapd_priv *phostapdpriv = padapter->phostapdpriv; ++ struct net_device *pnetdev = padapter->pnetdev; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); ++ struct dvobj_priv *pdvobj = &padapter->dvobjpriv; ++ ++ ++ //DBG_8192C("%s\n", __FUNCTION__); ++ ++ skb = pkt; ++ ++ len = skb->len; ++ tx_hdr = (struct rtw_ieee80211_hdr *)(skb->data); ++ fc = le16_to_cpu(tx_hdr->frame_ctl); ++ bmcst = IS_MCAST(tx_hdr->addr1); ++ ++ if ((fc & RTW_IEEE80211_FCTL_FTYPE) != RTW_IEEE80211_FTYPE_MGMT) ++ goto _exit; ++ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18)) // http://www.mail-archive.com/netdev@vger.kernel.org/msg17214.html ++ pxmit_skb = dev_alloc_skb(len + TXDESC_SIZE); ++#else ++ pxmit_skb = netdev_alloc_skb(pnetdev, len + TXDESC_SIZE); ++#endif ++ ++ if(!pxmit_skb) ++ goto _exit; ++ ++ pxmitbuf = pxmit_skb->data; ++ ++ urb = usb_alloc_urb(0, GFP_ATOMIC); ++ if (!urb) { ++ goto _exit; ++ } ++ ++ // ----- fill tx desc ----- ++ ptxdesc = (struct tx_desc *)pxmitbuf; ++ _rtw_memset(ptxdesc, 0, sizeof(*ptxdesc)); ++ ++ //offset 0 ++ ptxdesc->txdw0 |= cpu_to_le32(len&0x0000ffff); ++ ptxdesc->txdw0 |= cpu_to_le32(((TXDESC_SIZE+OFFSET_SZ)<txdw0 |= cpu_to_le32(OWN | FSG | LSG); ++ ++ if(bmcst) ++ { ++ ptxdesc->txdw0 |= cpu_to_le32(BIT(24)); ++ } ++ ++ //offset 4 ++ ptxdesc->txdw1 |= cpu_to_le32(0x00);//MAC_ID ++ ++ ptxdesc->txdw1 |= cpu_to_le32((0x12<txdw1 |= cpu_to_le32((0x06<< 16) & 0x000f0000);//b mode ++ ++ //offset 8 ++ ++ //offset 12 ++ ptxdesc->txdw3 |= cpu_to_le32((le16_to_cpu(tx_hdr->seq_ctl)<<16)&0xffff0000); ++ ++ //offset 16 ++ ptxdesc->txdw4 |= cpu_to_le32(BIT(8));//driver uses rate ++ ++ //offset 20 ++ ++ ++ //HW append seq ++ ptxdesc->txdw4 |= cpu_to_le32(BIT(7)); // Hw set sequence number ++ ptxdesc->txdw3 |= cpu_to_le32((8 <<28)); //set bit3 to 1. Suugested by TimChen. 2009.12.29. ++ ++ ++ rtl8192cu_cal_txdesc_chksum(ptxdesc); ++ // ----- end of fill tx desc ----- ++ ++ // ++ skb_put(pxmit_skb, len + TXDESC_SIZE); ++ pxmitbuf = pxmitbuf + TXDESC_SIZE; ++ _rtw_memcpy(pxmitbuf, skb->data, len); ++ ++ //DBG_8192C("mgnt_xmit, len=%x\n", pxmit_skb->len); ++ ++ ++ // ----- prepare urb for submit ----- ++ ++ //translate DMA FIFO addr to pipehandle ++ //pipe = ffaddr2pipehdl(pdvobj, MGT_QUEUE_INX); ++ pipe = usb_sndbulkpipe(pdvobj->pusbdev, pHalData->Queue2EPNum[(u8)MGT_QUEUE_INX]&0x0f); ++ ++ usb_fill_bulk_urb(urb, pdvobj->pusbdev, pipe, ++ pxmit_skb->data, pxmit_skb->len, rtl8192cu_hostap_mgnt_xmit_cb, pxmit_skb); ++ ++ urb->transfer_flags |= URB_ZERO_PACKET; ++ usb_anchor_urb(urb, &phostapdpriv->anchored); ++ rc = usb_submit_urb(urb, GFP_ATOMIC); ++ if (rc < 0) { ++ usb_unanchor_urb(urb); ++ kfree_skb(skb); ++ } ++ usb_free_urb(urb); ++ ++ ++_exit: ++ ++ dev_kfree_skb_any(skb); ++ ++#endif ++ ++ return 0; ++ ++} ++#endif ++ +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/hal/rtl8192c/usb/usb_halinit.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/hal/rtl8192c/usb/usb_halinit.c 2013-07-26 19:36:06.000000000 +0000 +@@ -0,0 +1,6036 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++******************************************************************************/ ++#define _HCI_HAL_INIT_C_ ++ ++#include ++#include ++#include ++#include ++ ++#include ++#include ++ ++#ifdef DBG_CONFIG_ERROR_DETECT ++#include "rtl8192c_sreset.h" ++#endif ++ ++#ifdef CONFIG_IOL ++#include ++#endif ++ ++#if defined (PLATFORM_LINUX) && defined (PLATFORM_WINDOWS) ++ ++#error "Shall be Linux or Windows, but not both!\n" ++ ++#endif ++ ++#ifndef CONFIG_USB_HCI ++ ++#error "CONFIG_USB_HCI shall be on!\n" ++ ++#endif ++ ++#include ++#include ++#include ++ ++#if DISABLE_BB_RF ++ #define HAL_MAC_ENABLE 0 ++ #define HAL_BB_ENABLE 0 ++ #define HAL_RF_ENABLE 0 ++#else ++ #define HAL_MAC_ENABLE 1 ++ #define HAL_BB_ENABLE 1 ++ #define HAL_RF_ENABLE 1 ++#endif ++ ++//endpoint number 1,2,3,4,5 ++// bult in : 1 ++// bult out: 2 (High) ++// bult out: 3 (Normal) for 3 out_ep, (Low) for 2 out_ep ++// interrupt in: 4 ++// bult out: 5 (Low) for 3 out_ep ++ ++ ++static VOID ++_OneOutEpMapping( ++ IN HAL_DATA_TYPE *pHalData ++ ) ++{ ++ //only endpoint number 0x02 ++ ++ pHalData->Queue2EPNum[0] = pHalData->RtBulkOutPipe[0];//VO ++ pHalData->Queue2EPNum[1] = pHalData->RtBulkOutPipe[0];//VI ++ pHalData->Queue2EPNum[2] = pHalData->RtBulkOutPipe[0];//BE ++ pHalData->Queue2EPNum[3] = pHalData->RtBulkOutPipe[0];//BK ++ ++ pHalData->Queue2EPNum[4] = pHalData->RtBulkOutPipe[0];//BCN ++ pHalData->Queue2EPNum[5] = pHalData->RtBulkOutPipe[0];//MGT ++ pHalData->Queue2EPNum[6] = pHalData->RtBulkOutPipe[0];//HIGH ++ pHalData->Queue2EPNum[7] = pHalData->RtBulkOutPipe[0];//TXCMD ++} ++ ++ ++static VOID ++_TwoOutEpMapping( ++ IN BOOLEAN IsTestChip, ++ IN HAL_DATA_TYPE *pHalData, ++ IN BOOLEAN bWIFICfg ++ ) ++{ ++ ++/* ++#define VO_QUEUE_INX 0 ++#define VI_QUEUE_INX 1 ++#define BE_QUEUE_INX 2 ++#define BK_QUEUE_INX 3 ++#define BCN_QUEUE_INX 4 ++#define MGT_QUEUE_INX 5 ++#define HIGH_QUEUE_INX 6 ++#define TXCMD_QUEUE_INX 7 ++*/ ++ ++ if(IsTestChip && bWIFICfg){ // test chip && wmm ++ ++ ++ // BK, BE, VI, VO, BCN, CMD,MGT,HIGH,HCCA ++ //{ 1, 0, 1, 0, 0, 0, 0, 0, 0 }; ++ //0:H(end_number=0x02), 1:L (end_number=0x03) ++ ++ pHalData->Queue2EPNum[0] = pHalData->RtBulkOutPipe[0];//VO ++ pHalData->Queue2EPNum[1] = pHalData->RtBulkOutPipe[1];//VI ++ pHalData->Queue2EPNum[2] = pHalData->RtBulkOutPipe[0];//BE ++ pHalData->Queue2EPNum[3] = pHalData->RtBulkOutPipe[1];//BK ++ ++ pHalData->Queue2EPNum[4] = pHalData->RtBulkOutPipe[0];//BCN ++ pHalData->Queue2EPNum[5] = pHalData->RtBulkOutPipe[0];//MGT ++ pHalData->Queue2EPNum[6] = pHalData->RtBulkOutPipe[0];//HIGH ++ pHalData->Queue2EPNum[7] = pHalData->RtBulkOutPipe[0];//TXCMD ++ } ++ else if(!IsTestChip && bWIFICfg){ // Normal chip && wmm ++ ++ // BK, BE, VI, VO, BCN, CMD,MGT,HIGH,HCCA ++ //{ 0, 1, 0, 1, 0, 0, 0, 0, 0 }; ++ //0:H(end_number=0x02), 1:L (end_number=0x03) ++ ++ pHalData->Queue2EPNum[0] = pHalData->RtBulkOutPipe[1];//VO ++ pHalData->Queue2EPNum[1] = pHalData->RtBulkOutPipe[0];//VI ++ pHalData->Queue2EPNum[2] = pHalData->RtBulkOutPipe[1];//BE ++ pHalData->Queue2EPNum[3] = pHalData->RtBulkOutPipe[0];//BK ++ ++ pHalData->Queue2EPNum[4] = pHalData->RtBulkOutPipe[0];//BCN ++ pHalData->Queue2EPNum[5] = pHalData->RtBulkOutPipe[0];//MGT ++ pHalData->Queue2EPNum[6] = pHalData->RtBulkOutPipe[0];//HIGH ++ pHalData->Queue2EPNum[7] = pHalData->RtBulkOutPipe[0];//TXCMD ++ } ++ else{//typical setting ++ ++ //BK, BE, VI, VO, BCN, CMD,MGT,HIGH,HCCA ++ //{ 1, 1, 0, 0, 0, 0, 0, 0, 0 }; ++ //0:H(end_number=0x02), 1:L (end_number=0x03) ++ ++ pHalData->Queue2EPNum[0] = pHalData->RtBulkOutPipe[0];//VO ++ pHalData->Queue2EPNum[1] = pHalData->RtBulkOutPipe[0];//VI ++ pHalData->Queue2EPNum[2] = pHalData->RtBulkOutPipe[1];//BE ++ pHalData->Queue2EPNum[3] = pHalData->RtBulkOutPipe[1];//BK ++ ++ pHalData->Queue2EPNum[4] = pHalData->RtBulkOutPipe[0];//BCN ++ pHalData->Queue2EPNum[5] = pHalData->RtBulkOutPipe[0];//MGT ++ pHalData->Queue2EPNum[6] = pHalData->RtBulkOutPipe[0];//HIGH ++ pHalData->Queue2EPNum[7] = pHalData->RtBulkOutPipe[0];//TXCMD ++ } ++ ++} ++ ++ ++static VOID _ThreeOutEpMapping( ++ IN HAL_DATA_TYPE *pHalData, ++ IN BOOLEAN bWIFICfg ++ ) ++{ ++ if(bWIFICfg){//for WMM ++ ++ // BK, BE, VI, VO, BCN, CMD,MGT,HIGH,HCCA ++ //{ 1, 2, 1, 0, 0, 0, 0, 0, 0 }; ++ //0:H(end_number=0x02), 1:N(end_number=0x03), 2:L (end_number=0x05) ++ ++ pHalData->Queue2EPNum[0] = pHalData->RtBulkOutPipe[0];//VO ++ pHalData->Queue2EPNum[1] = pHalData->RtBulkOutPipe[1];//VI ++ pHalData->Queue2EPNum[2] = pHalData->RtBulkOutPipe[2];//BE ++ pHalData->Queue2EPNum[3] = pHalData->RtBulkOutPipe[1];//BK ++ ++ pHalData->Queue2EPNum[4] = pHalData->RtBulkOutPipe[0];//BCN ++ pHalData->Queue2EPNum[5] = pHalData->RtBulkOutPipe[0];//MGT ++ pHalData->Queue2EPNum[6] = pHalData->RtBulkOutPipe[0];//HIGH ++ pHalData->Queue2EPNum[7] = pHalData->RtBulkOutPipe[0];//TXCMD ++ } ++ else{//typical setting ++ ++ // BK, BE, VI, VO, BCN, CMD,MGT,HIGH,HCCA ++ //{ 2, 2, 1, 0, 0, 0, 0, 0, 0 }; ++ //0:H(end_number=0x02), 1:N(end_number=0x03), 2:L (end_number=0x05) ++ pHalData->Queue2EPNum[0] = pHalData->RtBulkOutPipe[0];//VO ++ pHalData->Queue2EPNum[1] = pHalData->RtBulkOutPipe[1];//VI ++ pHalData->Queue2EPNum[2] = pHalData->RtBulkOutPipe[2];//BE ++ pHalData->Queue2EPNum[3] = pHalData->RtBulkOutPipe[2];//BK ++ ++ pHalData->Queue2EPNum[4] = pHalData->RtBulkOutPipe[0];//BCN ++ pHalData->Queue2EPNum[5] = pHalData->RtBulkOutPipe[0];//MGT ++ pHalData->Queue2EPNum[6] = pHalData->RtBulkOutPipe[0];//HIGH ++ pHalData->Queue2EPNum[7] = pHalData->RtBulkOutPipe[0];//TXCMD ++ } ++ ++} ++ ++static BOOLEAN ++_MappingOutEP( ++ IN PADAPTER pAdapter, ++ IN u8 NumOutPipe, ++ IN BOOLEAN IsTestChip ++ ) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); ++ struct registry_priv *pregistrypriv = &pAdapter->registrypriv; ++ ++ BOOLEAN bWIFICfg = (pregistrypriv->wifi_spec) ?_TRUE:_FALSE; ++ ++ BOOLEAN result = _TRUE; ++ ++ switch(NumOutPipe) ++ { ++ case 2: ++ _TwoOutEpMapping(IsTestChip, pHalData, bWIFICfg); ++ break; ++ case 3: ++ // Test chip doesn't support three out EPs. ++ if(IsTestChip){ ++ return _FALSE; ++ } ++ _ThreeOutEpMapping(pHalData, bWIFICfg); ++ break; ++ case 1: ++ _OneOutEpMapping(pHalData); ++ break; ++ default: ++ result = _FALSE; ++ break; ++ } ++ ++ return result; ++ ++} ++ ++static VOID ++_ConfigTestChipOutEP( ++ IN PADAPTER pAdapter, ++ IN u8 NumOutPipe ++ ) ++{ ++ u8 value8,txqsele; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); ++ ++ pHalData->OutEpQueueSel = 0; ++ pHalData->OutEpNumber = 0; ++ ++ value8 = rtw_read8(pAdapter, REG_TEST_SIE_OPTIONAL); ++ value8 = (value8 & USB_TEST_EP_MASK) >> USB_TEST_EP_SHIFT; ++ ++ switch(value8) ++ { ++ case 0: // 2 bulk OUT, 1 bulk IN ++ case 3: ++ pHalData->OutEpQueueSel = TX_SELE_HQ | TX_SELE_LQ; ++ pHalData->OutEpNumber = 2; ++ //RT_TRACE(COMP_INIT, DBG_LOUD, ("EP Config: 2 bulk OUT, 1 bulk IN\n")); ++ break; ++ case 1: // 1 bulk IN/OUT => map all endpoint to Low queue ++ case 2: // 1 bulk IN, 1 bulk OUT => map all endpoint to High queue ++ txqsele = rtw_read8(pAdapter, REG_TEST_USB_TXQS); ++ if(txqsele & 0x0F){//map all endpoint to High queue ++ pHalData->OutEpQueueSel = TX_SELE_HQ; ++ } ++ else if(txqsele&0xF0){//map all endpoint to Low queue ++ pHalData->OutEpQueueSel = TX_SELE_LQ; ++ } ++ pHalData->OutEpNumber = 1; ++ //RT_TRACE(COMP_INIT, DBG_LOUD, ("%s\n", ((1 == value8) ? "1 bulk IN/OUT" : "1 bulk IN, 1 bulk OUT"))); ++ break; ++ default: ++ break; ++ } ++ ++ // TODO: Error recovery for this case ++ //RT_ASSERT((NumOutPipe == pHalData->OutEpNumber), ("Out EP number isn't match! %d(Descriptor) != %d (SIE reg)\n", (u4Byte)NumOutPipe, (u4Byte)pHalData->OutEpNumber)); ++ ++} ++ ++ ++ ++static VOID ++_ConfigNormalChipOutEP( ++ IN PADAPTER pAdapter, ++ IN u8 NumOutPipe ++ ) ++{ ++ u8 value8; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); ++ ++ pHalData->OutEpQueueSel = 0; ++ pHalData->OutEpNumber = 0; ++ ++ // Normal and High queue ++ value8 = rtw_read8(pAdapter, (REG_NORMAL_SIE_EP + 1)); ++ ++ if(value8 & USB_NORMAL_SIE_EP_MASK){ ++ pHalData->OutEpQueueSel |= TX_SELE_HQ; ++ pHalData->OutEpNumber++; ++ } ++ ++ if((value8 >> USB_NORMAL_SIE_EP_SHIFT) & USB_NORMAL_SIE_EP_MASK){ ++ pHalData->OutEpQueueSel |= TX_SELE_NQ; ++ pHalData->OutEpNumber++; ++ } ++ ++ // Low queue ++ value8 = rtw_read8(pAdapter, (REG_NORMAL_SIE_EP + 2)); ++ if(value8 & USB_NORMAL_SIE_EP_MASK){ ++ pHalData->OutEpQueueSel |= TX_SELE_LQ; ++ pHalData->OutEpNumber++; ++ } ++ ++ // TODO: Error recovery for this case ++ //RT_ASSERT((NumOutPipe == pHalData->OutEpNumber), ("Out EP number isn't match! %d(Descriptor) != %d (SIE reg)\n", (u4Byte)NumOutPipe, (u4Byte)pHalData->OutEpNumber)); ++ ++} ++ ++static BOOLEAN HalUsbSetQueuePipeMapping8192CUsb( ++ IN PADAPTER pAdapter, ++ IN u8 NumInPipe, ++ IN u8 NumOutPipe ++ ) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); ++ BOOLEAN result = _FALSE; ++ BOOLEAN isNormalChip; ++ ++ //may be update UPHY Parameter == georgia ++ ++ ++ // ReadAdapterInfo8192C also call _ReadChipVersion too. ++ // Since we need dynamic config EP mapping, so we call this function to get chip version. ++ // We can remove _ReadChipVersion from ReadAdapterInfo8192C later. ++ //pHalData->VersionID = rtl8192c_ReadChipVersion(pAdapter); ++ ++ isNormalChip = IS_NORMAL_CHIP(pHalData->VersionID); ++ ++ if(isNormalChip){ ++ _ConfigNormalChipOutEP(pAdapter, NumOutPipe); ++ } ++ else{ ++ _ConfigTestChipOutEP(pAdapter, NumOutPipe); ++ } ++ ++ // Normal chip with one IN and one OUT doesn't have interrupt IN EP. ++ if(isNormalChip && (1 == pHalData->OutEpNumber)){ ++ if(1 != NumInPipe){ ++ return result; ++ } ++ } ++ ++ // All config other than above support one Bulk IN and one Interrupt IN. ++ //if(2 != NumInPipe){ ++ // return result; ++ //} ++ ++ result = _MappingOutEP(pAdapter, NumOutPipe, !isNormalChip); ++ ++ return result; ++ ++} ++ ++void rtl8192cu_interface_configure(_adapter *padapter) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); ++ struct dvobj_priv *pdvobjpriv = &padapter->dvobjpriv; ++ ++ if (pdvobjpriv->ishighspeed == _TRUE) ++ { ++ pHalData->UsbBulkOutSize = USB_HIGH_SPEED_BULK_SIZE;//512 bytes ++ } ++ else ++ { ++ pHalData->UsbBulkOutSize = USB_FULL_SPEED_BULK_SIZE;//64 bytes ++ } ++ ++ pHalData->interfaceIndex = pdvobjpriv->InterfaceNumber; ++ pHalData->RtBulkInPipe = pdvobjpriv->ep_num[0]; ++ pHalData->RtBulkOutPipe[0] = pdvobjpriv->ep_num[1]; ++ pHalData->RtBulkOutPipe[1] = pdvobjpriv->ep_num[2]; ++ pHalData->RtIntInPipe = pdvobjpriv->ep_num[3]; ++ pHalData->RtBulkOutPipe[2] = pdvobjpriv->ep_num[4]; ++ ++#ifdef CONFIG_USB_TX_AGGREGATION ++ pHalData->UsbTxAggMode = 1; ++ pHalData->UsbTxAggDescNum = 0x6; // only 4 bits ++#endif ++ ++#ifdef CONFIG_USB_RX_AGGREGATION ++ pHalData->UsbRxAggMode = USB_RX_AGG_DMA;// USB_RX_AGG_DMA; ++ pHalData->UsbRxAggBlockCount = 8; //unit : 512b ++ pHalData->UsbRxAggBlockTimeout = 0x6; ++ pHalData->UsbRxAggPageCount = 48; //uint :128 b //0x0A; // 10 = MAX_RX_DMA_BUFFER_SIZE/2/pHalData->UsbBulkOutSize ++ pHalData->UsbRxAggPageTimeout = 0x4; //6, absolute time = 34ms/(2^6) ++#endif ++ ++ HalUsbSetQueuePipeMapping8192CUsb(padapter, ++ pdvobjpriv->RtNumInPipes, pdvobjpriv->RtNumOutPipes); ++ ++} ++ ++static u8 _InitPowerOn(_adapter *padapter) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); ++ u8 ret = _SUCCESS; ++ u16 value16=0; ++ u8 value8 = 0; ++ u32 value32 = 0; ++ ++ // polling autoload done. ++ u32 pollingCount = 0; ++ ++ do ++ { ++ if(rtw_read8(padapter, REG_APS_FSMCO) & PFM_ALDN){ ++ //RT_TRACE(COMP_INIT,DBG_LOUD,("Autoload Done!\n")); ++ break; ++ } ++ ++ if(pollingCount++ > POLLING_READY_TIMEOUT_COUNT){ ++ //RT_TRACE(COMP_INIT,DBG_SERIOUS,("Failed to polling REG_APS_FSMCO[PFM_ALDN] done!\n")); ++ return _FAIL; ++ } ++ ++ }while(_TRUE); ++ ++ ++// For hardware power on sequence. ++ ++ //0. RSV_CTRL 0x1C[7:0] = 0x00 // unlock ISO/CLK/Power control register ++ rtw_write8(padapter, REG_RSV_CTRL, 0x0); ++ // Power on when re-enter from IPS/Radio off/card disable ++ rtw_write8(padapter, REG_SPS0_CTRL, 0x2b);//enable SPS into PWM mode ++/* ++ value16 = PlatformIORead2Byte(Adapter, REG_AFE_XTAL_CTRL);//enable AFE clock ++ value16 &= (~XTAL_GATE_AFE); ++ PlatformIOWrite2Byte(Adapter,REG_AFE_XTAL_CTRL, value16 ); ++*/ ++ ++ rtw_udelay_os(100);//PlatformSleepUs(150);//this is not necessary when initially power on ++ ++ value8 = rtw_read8(padapter, REG_LDOV12D_CTRL); ++ if(0== (value8 & LDV12_EN) ){ ++ value8 |= LDV12_EN; ++ rtw_write8(padapter, REG_LDOV12D_CTRL, value8); ++ //RT_TRACE(COMP_INIT, DBG_LOUD, (" power-on :REG_LDOV12D_CTRL Reg0x21:0x%02x.\n",value8)); ++ rtw_udelay_os(100);//PlatformSleepUs(100);//this is not necessary when initially power on ++ value8 = rtw_read8(padapter, REG_SYS_ISO_CTRL); ++ value8 &= ~ISO_MD2PP; ++ rtw_write8(padapter, REG_SYS_ISO_CTRL, value8); ++ } ++ ++ // auto enable WLAN ++ pollingCount = 0; ++ value16 = rtw_read16(padapter, REG_APS_FSMCO); ++ value16 |= APFM_ONMAC; ++ rtw_write16(padapter, REG_APS_FSMCO, value16); ++ ++ do ++ { ++ if(0 == (rtw_read16(padapter, REG_APS_FSMCO) & APFM_ONMAC)){ ++ //RT_TRACE(COMP_INIT,DBG_LOUD,("MAC auto ON okay!\n")); ++ break; ++ } ++ ++ if(pollingCount++ > POLLING_READY_TIMEOUT_COUNT){ ++ //RT_TRACE(COMP_INIT,DBG_SERIOUS,("Failed to polling REG_APS_FSMCO[APFM_ONMAC] done!\n")); ++ return _FAIL; ++ } ++ ++ }while(_TRUE); ++ ++ //Enable Radio ,GPIO ,and LED function ++ rtw_write16(padapter,REG_APS_FSMCO,0x0812); ++ ++#ifdef CONFIG_AUTOSUSPEND ++ //for usb Combo card ,BT ++ if((BOARD_USB_COMBO == pHalData->BoardType)&&(padapter->registrypriv.usbss_enable)) ++ { ++ value32 = rtw_read32(padapter, REG_APS_FSMCO); ++ value32 |= (SOP_ABG|SOP_AMB|XOP_BTCK); ++ rtw_write32(padapter, REG_APS_FSMCO, value32); ++ } ++#endif ++ ++ // release RF digital isolation ++ value16 = rtw_read16(padapter, REG_SYS_ISO_CTRL); ++ value16 &= ~ISO_DIOR; ++ rtw_write16(padapter, REG_SYS_ISO_CTRL, value16); ++ ++ // Enable MAC DMA/WMAC/SCHEDULE/SEC block ++ value16 = rtw_read16(padapter, REG_CR); ++ value16 |= (HCI_TXDMA_EN | HCI_RXDMA_EN | TXDMA_EN | RXDMA_EN ++ | PROTOCOL_EN | SCHEDULE_EN | MACTXEN | MACRXEN | ENSEC); ++ rtw_write16(padapter, REG_CR, value16); ++ ++ //tynli_test for suspend mode. ++ { ++ rtw_write8(padapter, 0xfe10, 0x19); ++ } ++ ++ // 2010/11/22 MH For slim combo debug mode check. ++ if (pHalData->BoardType == BOARD_USB_COMBO) ++ { ++ if (pHalData->SlimComboDbg == _TRUE) ++ { ++ DBG_8192C("SlimComboDbg == TRUE\n"); ++ ++ // 1. SIC?Test Mode ¤¤, Debug Ports ·|¦Û°Ê Enable, ©Ò¥H Driver ¤W¨Ó«á, ++ // ­nÃö±¼½Ð³]©w 0x 00[7] -> "1", ±N¥¦ Disable. effect if not: power consumption increase ++ rtw_write8(padapter, REG_SYS_ISO_CTRL, rtw_read8(padapter, REG_SYS_ISO_CTRL)|BIT7); ++ ++ // 2. SIC?Test Mode ¤¤, GPIO-8?·| report Power State ©Ò¥H Driver ¤W¨Ó«á, ½Ð³]©w? 0x04[6] -> "1" ±N¥¦ Disable ++ // effect if not: GPIO-8 could not be GPIO or LED function ++ rtw_write8(padapter, REG_APS_FSMCO, rtw_read8(padapter, REG_APS_FSMCO)|BIT6); ++ ++ // 3. SIC Test Mode ¤¤, EESK, EECS ·| report?Host Clock status, ©Ò¥H Driver ¤W¨Ó«á, ½Ð³]©w? 0x40[4] -> "1" ±N¥¦¤Á¦¨ EEPROM ¨Ï¥Î Pin (autoload still from Efuse) ++ // effect if not:power consumption increase ++ value8 = rtw_read8(padapter, REG_GPIO_MUXCFG)|BIT4 ; ++ #ifdef CONFIG_BT_COEXIST ++ // 2011/01/26 MH UMB-B cut bug. We need to support the modification. ++ if (IS_81xxC_VENDOR_UMC_B_CUT(pHalData->VersionID) && ++ pHalData->bt_coexist.BT_Coexist) ++ { ++ value8 |= (BIT5); ++ } ++ #endif ++ rtw_write8(padapter, REG_GPIO_MUXCFG,value8 ); ++ ++ ++ // 4. SIC Test Mode ¤¤,?SIC Debug ports ·|¦Û°Ê Enable , ©Ò¥H Driver ¤W¨Ó«á°¨¤W, ½Ð³]©w? 0x40[15:11] -> ¡§0x00¡¨, ±N¥¦Disable ++ // 4.1Two Steps setting for safety: 0x40[15,13,12, 11] -> "0", then ?0x40[14] -> "0" ++ // effect if not: Host could not transfer packets, and GPIO-3,2 will occupied by SIC then Co-exist could not work. ++ rtw_write16(padapter, REG_GPIO_MUXCFG, (rtw_read16(padapter, REG_GPIO_MUXCFG)&0x07FF)|BIT14); ++ rtw_write16(padapter, REG_GPIO_MUXCFG, rtw_read16(padapter, REG_GPIO_MUXCFG)&0x07FF); ++ } ++ } ++ ++ ++ // 2011/02/18 To Fix RU LNA power leakage problem. We need to execute below below in ++ // Adapter init and halt sequence. Accordingto EEchou's opinion, we can enable the ability for all ++ // IC. According to Johnny's opinion, only RU will meet the condition. ++ if (IS_HARDWARE_TYPE_8192C(padapter) && (pHalData->BoardType == BOARD_USB_High_PA)) ++ rtw_write32(padapter, rFPGA0_XCD_RFParameter, rtw_read32(padapter, rFPGA0_XCD_RFParameter)&(~BIT1)); ++ return ret; ++ ++} ++ ++ ++static void _dbg_dump_macreg(_adapter *padapter) ++{ ++ u32 offset = 0; ++ u32 val32 = 0; ++ u32 index =0 ; ++ for(index=0;index<64;index++) ++ { ++ offset = index*4; ++ val32 = rtw_read32(padapter,offset); ++ DBG_8192C("offset : 0x%02x ,val:0x%08x\n",offset,val32); ++ } ++} ++ ++ ++static void _InitPABias(_adapter *padapter) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); ++ u8 pa_setting; ++ BOOLEAN isNormal = IS_NORMAL_CHIP(pHalData->VersionID); ++ BOOLEAN is92C = IS_92C_SERIAL(pHalData->VersionID); ++ ++ //FIXED PA current issue ++ //efuse_one_byte_read(padapter, 0x1FA, &pa_setting); ++ pa_setting = EFUSE_Read1Byte(padapter, 0x1FA); ++ ++ //RT_TRACE(COMP_INIT, DBG_LOUD, ("_InitPABias 0x1FA 0x%x \n",pa_setting)); ++ ++ if(!(pa_setting & BIT0)) ++ { ++ PHY_SetRFReg(padapter, RF90_PATH_A, 0x15, 0x0FFFFF, 0x0F406); ++ PHY_SetRFReg(padapter, RF90_PATH_A, 0x15, 0x0FFFFF, 0x4F406); ++ PHY_SetRFReg(padapter, RF90_PATH_A, 0x15, 0x0FFFFF, 0x8F406); ++ PHY_SetRFReg(padapter, RF90_PATH_A, 0x15, 0x0FFFFF, 0xCF406); ++ //RT_TRACE(COMP_INIT, DBG_LOUD, ("PA BIAS path A\n")); ++ } ++ ++ if(!(pa_setting & BIT1) && isNormal && is92C) ++ { ++ PHY_SetRFReg(padapter,RF90_PATH_B, 0x15, 0x0FFFFF, 0x0F406); ++ PHY_SetRFReg(padapter,RF90_PATH_B, 0x15, 0x0FFFFF, 0x4F406); ++ PHY_SetRFReg(padapter,RF90_PATH_B, 0x15, 0x0FFFFF, 0x8F406); ++ PHY_SetRFReg(padapter,RF90_PATH_B, 0x15, 0x0FFFFF, 0xCF406); ++ //RT_TRACE(COMP_INIT, DBG_LOUD, ("PA BIAS path B\n")); ++ } ++ ++ if(!(pa_setting & BIT4)) ++ { ++ pa_setting = rtw_read8(padapter, 0x16); ++ pa_setting &= 0x0F; ++ rtw_write8(padapter, 0x16, pa_setting | 0x90); ++ } ++} ++#ifdef CONFIG_BT_COEXIST ++static void _InitBTCoexist(_adapter *padapter) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); ++ struct btcoexist_priv *pbtpriv = &(pHalData->bt_coexist); ++ u8 u1Tmp; ++ ++ if(pbtpriv->BT_Coexist && pbtpriv->BT_CoexistType == BT_CSR_BC4) ++ { ++ ++#if MP_DRIVER != 1 ++ if(pbtpriv->BT_Ant_isolation) ++ { ++ rtw_write8( padapter,REG_GPIO_MUXCFG, 0xa0); ++ DBG_8192C("BT write 0x%x = 0x%x\n", REG_GPIO_MUXCFG, 0xa0); ++ } ++#endif ++ ++ u1Tmp = rtw_read8(padapter, 0x4fd) & BIT0; ++ u1Tmp = u1Tmp | ++ ((pbtpriv->BT_Ant_isolation==1)?0:BIT1) | ++ ((pbtpriv->BT_Service==BT_SCO)?0:BIT2); ++ rtw_write8( padapter, 0x4fd, u1Tmp); ++ DBG_8192C("BT write 0x%x = 0x%x for non-isolation\n", 0x4fd, u1Tmp); ++ ++ ++ rtw_write32(padapter, REG_BT_COEX_TABLE+4, 0xaaaa9aaa); ++ DBG_8192C("BT write 0x%x = 0x%x\n", REG_BT_COEX_TABLE+4, 0xaaaa9aaa); ++ ++ rtw_write32(padapter, REG_BT_COEX_TABLE+8, 0xffbd0040); ++ DBG_8192C("BT write 0x%x = 0x%x\n", REG_BT_COEX_TABLE+8, 0xffbd0040); ++ ++ rtw_write32(padapter, REG_BT_COEX_TABLE+0xc, 0x40000010); ++ DBG_8192C("BT write 0x%x = 0x%x\n", REG_BT_COEX_TABLE+0xc, 0x40000010); ++ ++ //Config to 1T1R ++ u1Tmp = rtw_read8(padapter,rOFDM0_TRxPathEnable); ++ u1Tmp &= ~(BIT1); ++ rtw_write8( padapter, rOFDM0_TRxPathEnable, u1Tmp); ++ DBG_8192C("BT write 0xC04 = 0x%x\n", u1Tmp); ++ ++ u1Tmp = rtw_read8(padapter, rOFDM1_TRxPathEnable); ++ u1Tmp &= ~(BIT1); ++ rtw_write8( padapter, rOFDM1_TRxPathEnable, u1Tmp); ++ DBG_8192C("BT write 0xD04 = 0x%x\n", u1Tmp); ++ ++ } ++} ++#endif ++ ++//------------------------------------------------------------------------- ++// ++// LLT R/W/Init function ++// ++//------------------------------------------------------------------------- ++static u8 _LLTWrite( ++ IN PADAPTER Adapter, ++ IN u32 address, ++ IN u32 data ++ ) ++{ ++ u8 status = _SUCCESS; ++ int count = 0; ++ u32 value = _LLT_INIT_ADDR(address) | _LLT_INIT_DATA(data) | _LLT_OP(_LLT_WRITE_ACCESS); ++ ++ rtw_write32(Adapter, REG_LLT_INIT, value); ++ ++ //polling ++ do{ ++ ++ value = rtw_read32(Adapter, REG_LLT_INIT); ++ if(_LLT_NO_ACTIVE == _LLT_OP_VALUE(value)){ ++ break; ++ } ++ ++ if(count > POLLING_LLT_THRESHOLD){ ++ //RT_TRACE(COMP_INIT,DBG_SERIOUS,("Failed to polling write LLT done at address %d!\n", address)); ++ status = _FAIL; ++ break; ++ } ++ }while(count++); ++ ++ return status; ++ ++} ++ ++ ++static u8 _LLTRead( ++ IN PADAPTER Adapter, ++ IN u32 address ++ ) ++{ ++ int count = 0; ++ u32 value = _LLT_INIT_ADDR(address) | _LLT_OP(_LLT_READ_ACCESS); ++ ++ rtw_write32(Adapter, REG_LLT_INIT, value); ++ ++ //polling and get value ++ do{ ++ ++ value = rtw_read32(Adapter, REG_LLT_INIT); ++ if(_LLT_NO_ACTIVE == _LLT_OP_VALUE(value)){ ++ return (u8)value; ++ } ++ ++ if(count > POLLING_LLT_THRESHOLD){ ++ //RT_TRACE(COMP_INIT,DBG_SERIOUS,("Failed to polling read LLT done at address %d!\n", address)); ++ break; ++ } ++ }while(count++); ++ ++ return 0xFF; ++ ++} ++ ++ ++static u8 InitLLTTable( ++ IN PADAPTER Adapter, ++ IN u32 boundary ++ ) ++{ ++ u8 status = _SUCCESS; ++ u32 i; ++ ++#ifdef CONFIG_IOL_LLT ++ if(rtw_IOL_applied(Adapter)) ++ { ++ struct xmit_frame *xmit_frame; ++ if((xmit_frame=rtw_IOL_accquire_xmit_frame(Adapter)) == NULL) ++ return _FAIL; ++ ++ rtw_IOL_append_LLT_cmd(xmit_frame, boundary); ++ status = rtw_IOL_exec_cmds_sync(Adapter, xmit_frame, 1000); ++ } ++ else ++#endif ++ { ++ for(i = 0 ; i < (boundary - 1) ; i++){ ++ status = _LLTWrite(Adapter, i , i + 1); ++ if(_SUCCESS != status){ ++ return status; ++ } ++ } ++ ++ // end of list ++ status = _LLTWrite(Adapter, (boundary - 1), 0xFF); ++ if(_SUCCESS != status){ ++ return status; ++ } ++ ++ // Make the other pages as ring buffer ++ // This ring buffer is used as beacon buffer if we config this MAC as two MAC transfer. ++ // Otherwise used as local loopback buffer. ++ for(i = boundary ; i < LAST_ENTRY_OF_TX_PKT_BUFFER ; i++){ ++ status = _LLTWrite(Adapter, i, (i + 1)); ++ if(_SUCCESS != status){ ++ return status; ++ } ++ } ++ ++ // Let last entry point to the start entry of ring buffer ++ status = _LLTWrite(Adapter, LAST_ENTRY_OF_TX_PKT_BUFFER, boundary); ++ if(_SUCCESS != status){ ++ return status; ++ } ++ } ++ ++ return status; ++ ++} ++ ++ ++//--------------------------------------------------------------- ++// ++// MAC init functions ++// ++//--------------------------------------------------------------- ++static VOID ++_SetMacID( ++ IN PADAPTER Adapter, u8* MacID ++ ) ++{ ++ u32 i; ++ for(i=0 ; i< MAC_ADDR_LEN ; i++){ ++ rtw_write32(Adapter, REG_MACID+i, MacID[i]); ++ } ++} ++ ++static VOID ++_SetBSSID( ++ IN PADAPTER Adapter, u8* BSSID ++ ) ++{ ++ u32 i; ++ for(i=0 ; i< MAC_ADDR_LEN ; i++){ ++ rtw_write32(Adapter, REG_BSSID+i, BSSID[i]); ++ } ++} ++ ++ ++// Shall USB interface init this? ++static VOID ++_InitInterrupt( ++ IN PADAPTER Adapter ++ ) ++{ ++ u32 value32; ++ ++ // HISR - turn all on ++ value32 = 0xFFFFFFFF; ++ rtw_write32(Adapter, REG_HISR, value32); ++ ++ // HIMR - turn all on ++ rtw_write32(Adapter, REG_HIMR, value32); ++} ++ ++ ++static VOID ++_InitQueueReservedPage( ++ IN PADAPTER Adapter ++ ) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ struct registry_priv *pregistrypriv = &Adapter->registrypriv; ++ BOOLEAN isNormalChip = IS_NORMAL_CHIP(pHalData->VersionID); ++ ++ u32 outEPNum = (u32)pHalData->OutEpNumber; ++ u32 numHQ = 0; ++ u32 numLQ = 0; ++ u32 numNQ = 0; ++ u32 numPubQ; ++ u32 value32; ++ u8 value8; ++ BOOLEAN bWiFiConfig = pregistrypriv->wifi_spec; ++ //u32 txQPageNum, txQPageUnit,txQRemainPage; ++ ++#if 0 ++ if(!pregistrypriv->wifi_spec){ ++ numPubQ = (isNormalChip) ? NORMAL_PAGE_NUM_PUBQ : TEST_PAGE_NUM_PUBQ; ++ //RT_ASSERT((numPubQ < TX_TOTAL_PAGE_NUMBER), ("Public queue page number is great than total tx page number.\n")); ++ txQPageNum = TX_TOTAL_PAGE_NUMBER - numPubQ; ++ ++ //RT_ASSERT((0 == txQPageNum%txQPageNum), ("Total tx page number is not dividable!\n")); ++ ++ txQPageUnit = txQPageNum/outEPNum; ++ txQRemainPage = txQPageNum % outEPNum; ++ ++ if(pHalData->OutEpQueueSel & TX_SELE_HQ){ ++ numHQ = txQPageUnit; ++ } ++ if(pHalData->OutEpQueueSel & TX_SELE_LQ){ ++ numLQ = txQPageUnit; ++ } ++ // HIGH priority queue always present in the configuration of 2 or 3 out-ep ++ // so ,remainder pages have assigned to High queue ++ if((outEPNum>1) && (txQRemainPage)){ ++ numHQ += txQRemainPage; ++ } ++ ++ // NOTE: This step shall be proceed before writting REG_RQPN. ++ if(isNormalChip){ ++ if(pHalData->OutEpQueueSel & TX_SELE_NQ){ ++ numNQ = txQPageUnit; ++ } ++ value8 = (u8)_NPQ(numNQ); ++ rtw_write8(Adapter, REG_RQPN_NPQ, value8); ++ } ++ //RT_ASSERT(((numHQ + numLQ + numNQ + numPubQ) < TX_PAGE_BOUNDARY), ("Total tx page number is greater than tx boundary!\n")); ++ } ++ else ++#endif ++ { //for WMM ++ //RT_ASSERT((outEPNum>=2), ("for WMM ,number of out-ep must more than or equal to 2!\n")); ++ ++ numPubQ = (isNormalChip) ? ((bWiFiConfig)?WMM_NORMAL_PAGE_NUM_PUBQ:NORMAL_PAGE_NUM_PUBQ) ++ :WMM_TEST_PAGE_NUM_PUBQ; ++ ++ if(pHalData->OutEpQueueSel & TX_SELE_HQ){ ++ numHQ = (isNormalChip)?((bWiFiConfig)?WMM_NORMAL_PAGE_NUM_HPQ:NORMAL_PAGE_NUM_HPQ) ++ :WMM_TEST_PAGE_NUM_HPQ; ++ } ++ ++ if(pHalData->OutEpQueueSel & TX_SELE_LQ){ ++ numLQ = (isNormalChip)?((bWiFiConfig)?WMM_NORMAL_PAGE_NUM_LPQ:NORMAL_PAGE_NUM_LPQ) ++ :WMM_TEST_PAGE_NUM_LPQ; ++ } ++ // NOTE: This step shall be proceed before writting REG_RQPN. ++ if(isNormalChip){ ++ if(pHalData->OutEpQueueSel & TX_SELE_NQ){ ++ numNQ = (bWiFiConfig)?WMM_NORMAL_PAGE_NUM_NPQ:NORMAL_PAGE_NUM_NPQ; ++ } ++ value8 = (u8)_NPQ(numNQ); ++ rtw_write8(Adapter, REG_RQPN_NPQ, value8); ++ } ++ } ++ ++ // TX DMA ++ value32 = _HPQ(numHQ) | _LPQ(numLQ) | _PUBQ(numPubQ) | LD_RQPN; ++ rtw_write32(Adapter, REG_RQPN, value32); ++} ++ ++static void _InitID(IN PADAPTER Adapter) ++{ ++ int i; ++ EEPROM_EFUSE_PRIV *pEEPROM = GET_EEPROM_EFUSE_PRIV(Adapter); ++ ++ for(i=0; i<6; i++) ++ { ++ rtw_write8(Adapter, (REG_MACID+i), pEEPROM->mac_addr[i]); ++ } ++ ++/* ++ NicIFSetMacAddress(Adapter, Adapter->PermanentAddress); ++ //Ziv test ++#if 1 ++ { ++ u1Byte sMacAddr[6] = {0}; ++ u4Byte i; ++ ++ for(i = 0 ; i < MAC_ADDR_LEN ; i++){ ++ sMacAddr[i] = PlatformIORead1Byte(Adapter, (REG_MACID + i)); ++ } ++ RT_PRINT_ADDR(COMP_INIT|COMP_EFUSE, DBG_LOUD, "Read back MAC Addr: ", sMacAddr); ++ } ++#endif ++ ++#if 0 ++ u4Byte nMAR = 0xFFFFFFFF; ++ u8 m_MacID[] = {0x01, 0x02, 0x03, 0x04, 0x05, 0x06}; ++ u8 m_BSSID[] = {0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f}; ++ int i; ++ ++ _SetMacID(Adapter, Adapter->PermanentAddress); ++ _SetBSSID(Adapter, m_BSSID); ++ ++ //set MAR ++ PlatformIOWrite4Byte(Adapter, REG_MAR, nMAR); ++ PlatformIOWrite4Byte(Adapter, REG_MAR+4, nMAR); ++#endif ++*/ ++} ++ ++ ++static VOID ++_InitTxBufferBoundary( ++ IN PADAPTER Adapter ++ ) ++{ ++ struct registry_priv *pregistrypriv = &Adapter->registrypriv; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ ++ u8 txpktbuf_bndy; ++ ++ if(!pregistrypriv->wifi_spec){ ++ txpktbuf_bndy = TX_PAGE_BOUNDARY; ++ } ++ else{//for WMM ++ txpktbuf_bndy = ( IS_NORMAL_CHIP( pHalData->VersionID))?WMM_NORMAL_TX_PAGE_BOUNDARY ++ :WMM_TEST_TX_PAGE_BOUNDARY; ++ } ++ ++ rtw_write8(Adapter, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy); ++ rtw_write8(Adapter, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy); ++ rtw_write8(Adapter, REG_TXPKTBUF_WMAC_LBK_BF_HD, txpktbuf_bndy); ++ rtw_write8(Adapter, REG_TRXFF_BNDY, txpktbuf_bndy); ++#if 1 ++ rtw_write8(Adapter, REG_TDECTRL+1, txpktbuf_bndy); ++#else ++ txdmactrl = PlatformIORead2Byte(Adapter, REG_TDECTRL); ++ txdmactrl &= ~BCN_HEAD_MASK; ++ txdmactrl |= BCN_HEAD(txpktbuf_bndy); ++ PlatformIOWrite2Byte(Adapter, REG_TDECTRL, txdmactrl); ++#endif ++} ++ ++static VOID ++_InitPageBoundary( ++ IN PADAPTER Adapter ++ ) ++{ ++ // RX Page Boundary ++ //srand(static_cast(time(NULL)) ); ++ u16 rxff_bndy = 0x27FF;//(rand() % 1) ? 0x27FF : 0x23FF; ++ ++ rtw_write16(Adapter, (REG_TRXFF_BNDY + 2), rxff_bndy); ++ ++ // TODO: ?? shall we set tx boundary? ++} ++ ++ ++static VOID ++_InitNormalChipRegPriority( ++ IN PADAPTER Adapter, ++ IN u16 beQ, ++ IN u16 bkQ, ++ IN u16 viQ, ++ IN u16 voQ, ++ IN u16 mgtQ, ++ IN u16 hiQ ++ ) ++{ ++ u16 value16 = (rtw_read16(Adapter, REG_TRXDMA_CTRL) & 0x7); ++ ++ value16 |= _TXDMA_BEQ_MAP(beQ) | _TXDMA_BKQ_MAP(bkQ) | ++ _TXDMA_VIQ_MAP(viQ) | _TXDMA_VOQ_MAP(voQ) | ++ _TXDMA_MGQ_MAP(mgtQ)| _TXDMA_HIQ_MAP(hiQ); ++ ++ rtw_write16(Adapter, REG_TRXDMA_CTRL, value16); ++} ++ ++static VOID ++_InitNormalChipOneOutEpPriority( ++ IN PADAPTER Adapter ++ ) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ ++ u16 value = 0; ++ switch(pHalData->OutEpQueueSel) ++ { ++ case TX_SELE_HQ: ++ value = QUEUE_HIGH; ++ break; ++ case TX_SELE_LQ: ++ value = QUEUE_LOW; ++ break; ++ case TX_SELE_NQ: ++ value = QUEUE_NORMAL; ++ break; ++ default: ++ //RT_ASSERT(FALSE,("Shall not reach here!\n")); ++ break; ++ } ++ ++ _InitNormalChipRegPriority(Adapter, ++ value, ++ value, ++ value, ++ value, ++ value, ++ value ++ ); ++ ++} ++ ++static VOID ++_InitNormalChipTwoOutEpPriority( ++ IN PADAPTER Adapter ++ ) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ struct registry_priv *pregistrypriv = &Adapter->registrypriv; ++ u16 beQ,bkQ,viQ,voQ,mgtQ,hiQ; ++ ++ ++ u16 valueHi = 0; ++ u16 valueLow = 0; ++ ++ switch(pHalData->OutEpQueueSel) ++ { ++ case (TX_SELE_HQ | TX_SELE_LQ): ++ valueHi = QUEUE_HIGH; ++ valueLow = QUEUE_LOW; ++ break; ++ case (TX_SELE_NQ | TX_SELE_LQ): ++ valueHi = QUEUE_NORMAL; ++ valueLow = QUEUE_LOW; ++ break; ++ case (TX_SELE_HQ | TX_SELE_NQ): ++ valueHi = QUEUE_HIGH; ++ valueLow = QUEUE_NORMAL; ++ break; ++ default: ++ //RT_ASSERT(FALSE,("Shall not reach here!\n")); ++ break; ++ } ++ ++ if(!pregistrypriv->wifi_spec ){ ++ beQ = valueLow; ++ bkQ = valueLow; ++ viQ = valueHi; ++ voQ = valueHi; ++ mgtQ = valueHi; ++ hiQ = valueHi; ++ } ++ else{//for WMM ,CONFIG_OUT_EP_WIFI_MODE ++ beQ = valueLow; ++ bkQ = valueHi; ++ viQ = valueHi; ++ voQ = valueLow; ++ mgtQ = valueHi; ++ hiQ = valueHi; ++ } ++ ++ _InitNormalChipRegPriority(Adapter,beQ,bkQ,viQ,voQ,mgtQ,hiQ); ++ ++} ++ ++static VOID ++_InitNormalChipThreeOutEpPriority( ++ IN PADAPTER Adapter ++ ) ++{ ++ struct registry_priv *pregistrypriv = &Adapter->registrypriv; ++ u16 beQ,bkQ,viQ,voQ,mgtQ,hiQ; ++ ++ if(!pregistrypriv->wifi_spec ){// typical setting ++ beQ = QUEUE_LOW; ++ bkQ = QUEUE_LOW; ++ viQ = QUEUE_NORMAL; ++ voQ = QUEUE_HIGH; ++ mgtQ = QUEUE_HIGH; ++ hiQ = QUEUE_HIGH; ++ } ++ else{// for WMM ++ beQ = QUEUE_LOW; ++ bkQ = QUEUE_NORMAL; ++ viQ = QUEUE_NORMAL; ++ voQ = QUEUE_HIGH; ++ mgtQ = QUEUE_HIGH; ++ hiQ = QUEUE_HIGH; ++ } ++ _InitNormalChipRegPriority(Adapter,beQ,bkQ,viQ,voQ,mgtQ,hiQ); ++} ++ ++static VOID ++_InitNormalChipQueuePriority( ++ IN PADAPTER Adapter ++ ) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ ++ switch(pHalData->OutEpNumber) ++ { ++ case 1: ++ _InitNormalChipOneOutEpPriority(Adapter); ++ break; ++ case 2: ++ _InitNormalChipTwoOutEpPriority(Adapter); ++ break; ++ case 3: ++ _InitNormalChipThreeOutEpPriority(Adapter); ++ break; ++ default: ++ //RT_ASSERT(FALSE,("Shall not reach here!\n")); ++ break; ++ } ++ ++ ++} ++ ++static VOID ++_InitTestChipQueuePriority( ++ IN PADAPTER Adapter ++ ) ++{ ++ u8 hq_sele ; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ struct registry_priv *pregistrypriv = &Adapter->registrypriv; ++ ++ switch(pHalData->OutEpNumber) ++ { ++ case 2: // (TX_SELE_HQ|TX_SELE_LQ) ++ if(!pregistrypriv->wifi_spec)//typical setting ++ hq_sele = HQSEL_VOQ | HQSEL_VIQ | HQSEL_MGTQ | HQSEL_HIQ ; ++ else //for WMM ++ hq_sele = HQSEL_VOQ | HQSEL_BEQ | HQSEL_MGTQ | HQSEL_HIQ ; ++ break; ++ case 1: ++ if(TX_SELE_LQ == pHalData->OutEpQueueSel ){//map all endpoint to Low queue ++ hq_sele = 0; ++ } ++ else if(TX_SELE_HQ == pHalData->OutEpQueueSel){//map all endpoint to High queue ++ hq_sele = HQSEL_VOQ | HQSEL_VIQ | HQSEL_BEQ | HQSEL_BKQ | HQSEL_MGTQ | HQSEL_HIQ ; ++ } ++ break; ++ default: ++ //RT_ASSERT(FALSE,("Shall not reach here!\n")); ++ break; ++ } ++ rtw_write8(Adapter, (REG_TRXDMA_CTRL+1), hq_sele); ++} ++ ++ ++static VOID ++_InitQueuePriority( ++ IN PADAPTER Adapter ++ ) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ ++ if(IS_NORMAL_CHIP( pHalData->VersionID)){ ++ _InitNormalChipQueuePriority(Adapter); ++ } ++ else{ ++ _InitTestChipQueuePriority(Adapter); ++ } ++} ++ ++static VOID ++_InitHardwareDropIncorrectBulkOut( ++ IN PADAPTER Adapter ++ ) ++{ ++ u32 value32 = rtw_read32(Adapter, REG_TXDMA_OFFSET_CHK); ++ value32 |= DROP_DATA_EN; ++ rtw_write32(Adapter, REG_TXDMA_OFFSET_CHK, value32); ++} ++ ++static VOID ++_InitNetworkType( ++ IN PADAPTER Adapter ++ ) ++{ ++ u32 value32; ++ ++ value32 = rtw_read32(Adapter, REG_CR); ++ ++ // TODO: use the other function to set network type ++#if RTL8191C_FPGA_NETWORKTYPE_ADHOC ++ value32 = (value32 & ~MASK_NETTYPE) | _NETTYPE(NT_LINK_AD_HOC); ++#else ++ value32 = (value32 & ~MASK_NETTYPE) | _NETTYPE(NT_LINK_AP); ++#endif ++ rtw_write32(Adapter, REG_CR, value32); ++// RASSERT(pIoBase->rtw_read8(REG_CR + 2) == 0x2); ++} ++ ++static VOID ++_InitTransferPageSize( ++ IN PADAPTER Adapter ++ ) ++{ ++ // Tx page size is always 128. ++ ++ u8 value8; ++ value8 = _PSRX(PBP_128) | _PSTX(PBP_128); ++ rtw_write8(Adapter, REG_PBP, value8); ++} ++ ++static VOID ++_InitDriverInfoSize( ++ IN PADAPTER Adapter, ++ IN u8 drvInfoSize ++ ) ++{ ++ rtw_write8(Adapter,REG_RX_DRVINFO_SZ, drvInfoSize); ++} ++ ++static VOID ++_InitWMACSetting( ++ IN PADAPTER Adapter ++ ) ++{ ++ //u4Byte value32; ++ //u16 value16; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ ++ //pHalData->ReceiveConfig = AAP | APM | AM | AB | APP_ICV | ADF | AMF | APP_FCS | HTC_LOC_CTRL | APP_MIC | APP_PHYSTS; ++ pHalData->ReceiveConfig = RCR_AAP | RCR_APM | RCR_AM | RCR_AB |RCR_CBSSID_DATA| RCR_CBSSID_BCN| RCR_APP_ICV | RCR_AMF | RCR_HTC_LOC_CTRL | RCR_APP_MIC | RCR_APP_PHYSTS; ++#if (0 == RTL8192C_RX_PACKET_NO_INCLUDE_CRC) ++ pHalData->ReceiveConfig |= ACRC32; ++#endif ++ ++ // some REG_RCR will be modified later by phy_ConfigMACWithHeaderFile() ++ rtw_write32(Adapter, REG_RCR, pHalData->ReceiveConfig); ++ ++ // Accept all multicast address ++ rtw_write32(Adapter, REG_MAR, 0xFFFFFFFF); ++ rtw_write32(Adapter, REG_MAR + 4, 0xFFFFFFFF); ++ ++ ++ // Accept all data frames ++ //value16 = 0xFFFF; ++ //rtw_write16(Adapter, REG_RXFLTMAP2, value16); ++ ++ // 2010.09.08 hpfan ++ // Since ADF is removed from RCR, ps-poll will not be indicate to driver, ++ // RxFilterMap should mask ps-poll to gurantee AP mode can rx ps-poll. ++ //value16 = 0x400; ++ //rtw_write16(Adapter, REG_RXFLTMAP1, value16); ++ ++ // Accept all management frames ++ //value16 = 0xFFFF; ++ //rtw_write16(Adapter, REG_RXFLTMAP0, value16); ++ ++ //enable RX_SHIFT bits ++ //rtw_write8(Adapter, REG_TRXDMA_CTRL, rtw_read8(Adapter, REG_TRXDMA_CTRL)|BIT(1)); ++ ++} ++ ++static VOID ++_InitAdaptiveCtrl( ++ IN PADAPTER Adapter ++ ) ++{ ++ u16 value16; ++ u32 value32; ++ ++ // Response Rate Set ++ value32 = rtw_read32(Adapter, REG_RRSR); ++ value32 &= ~RATE_BITMAP_ALL; ++ value32 |= RATE_RRSR_CCK_ONLY_1M; ++ rtw_write32(Adapter, REG_RRSR, value32); ++ ++ // CF-END Threshold ++ //m_spIoBase->rtw_write8(REG_CFEND_TH, 0x1); ++ ++ // SIFS (used in NAV) ++ value16 = _SPEC_SIFS_CCK(0x10) | _SPEC_SIFS_OFDM(0x10); ++ rtw_write16(Adapter, REG_SPEC_SIFS, value16); ++ ++ // Retry Limit ++ value16 = _LRL(0x30) | _SRL(0x30); ++ rtw_write16(Adapter, REG_RL, value16); ++ ++} ++ ++static VOID ++_InitRateFallback( ++ IN PADAPTER Adapter ++ ) ++{ ++ // Set Data Auto Rate Fallback Retry Count register. ++ rtw_write32(Adapter, REG_DARFRC, 0x00000000); ++ rtw_write32(Adapter, REG_DARFRC+4, 0x10080404); ++ rtw_write32(Adapter, REG_RARFRC, 0x04030201); ++ rtw_write32(Adapter, REG_RARFRC+4, 0x08070605); ++ ++} ++ ++ ++static VOID ++_InitEDCA( ++ IN PADAPTER Adapter ++ ) ++{ ++ // Set Spec SIFS (used in NAV) ++ rtw_write16(Adapter,REG_SPEC_SIFS, 0x100a); ++ rtw_write16(Adapter,REG_MAC_SPEC_SIFS, 0x100a); ++ ++ // Set SIFS for CCK ++ rtw_write16(Adapter,REG_SIFS_CTX, 0x100a); ++ ++ // Set SIFS for OFDM ++ rtw_write16(Adapter,REG_SIFS_TRX, 0x100a); ++ ++ // TXOP ++ rtw_write32(Adapter, REG_EDCA_BE_PARAM, 0x005EA42B); ++ rtw_write32(Adapter, REG_EDCA_BK_PARAM, 0x0000A44F); ++ rtw_write32(Adapter, REG_EDCA_VI_PARAM, 0x005EA324); ++ rtw_write32(Adapter, REG_EDCA_VO_PARAM, 0x002FA226); ++} ++ ++ ++static VOID ++_InitBeaconMaxError( ++ IN PADAPTER Adapter, ++ IN BOOLEAN InfraMode ++ ) ++{ ++#ifdef RTL8192CU_ADHOC_WORKAROUND_SETTING ++ rtw_write8(Adapter, REG_BCN_MAX_ERR, 0xFF); ++#else ++ //rtw_write8(Adapter, REG_BCN_MAX_ERR, (InfraMode ? 0xFF : 0x10)); ++#endif ++} ++ ++ ++#ifdef CONFIG_LED ++static void _InitHWLed(PADAPTER Adapter) ++{ ++ struct led_priv *pledpriv = &(Adapter->ledpriv); ++ ++ if( pledpriv->LedStrategy != HW_LED) ++ return; ++ ++// HW led control ++// to do .... ++//must consider cases of antenna diversity/ commbo card/solo card/mini card ++ ++} ++#endif //CONFIG_LED ++ ++static VOID ++_InitRDGSetting( ++ IN PADAPTER Adapter ++ ) ++{ ++ rtw_write8(Adapter,REG_RD_CTRL,0xFF); ++ rtw_write16(Adapter, REG_RD_NAV_NXT, 0x200); ++ rtw_write8(Adapter,REG_RD_RESP_PKT_TH,0x05); ++} ++ ++static VOID ++_InitRxSetting( ++ IN PADAPTER Adapter ++ ) ++{ ++ rtw_write32(Adapter, REG_MACID, 0x87654321); ++ rtw_write32(Adapter, 0x0700, 0x87654321); ++} ++ ++static VOID ++_InitRetryFunction( ++ IN PADAPTER Adapter ++ ) ++{ ++ u8 value8; ++ ++ value8 = rtw_read8(Adapter, REG_FWHW_TXQ_CTRL); ++ value8 |= EN_AMPDU_RTY_NEW; ++ rtw_write8(Adapter, REG_FWHW_TXQ_CTRL, value8); ++ ++ // Set ACK timeout ++ rtw_write8(Adapter, REG_ACKTO, 0x40); ++} ++ ++/*----------------------------------------------------------------------------- ++ * Function: usb_AggSettingTxUpdate() ++ * ++ * Overview: Seperate TX/RX parameters update independent for TP detection and ++ * dynamic TX/RX aggreagtion parameters update. ++ * ++ * Input: PADAPTER ++ * ++ * Output/Return: NONE ++ * ++ * Revised History: ++ * When Who Remark ++ * 12/10/2010 MHC Seperate to smaller function. ++ * ++ *---------------------------------------------------------------------------*/ ++static VOID ++usb_AggSettingTxUpdate( ++ IN PADAPTER Adapter ++ ) ++{ ++#ifdef CONFIG_USB_TX_AGGREGATION ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ //PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo); ++ u32 value32; ++ ++ if(Adapter->registrypriv.wifi_spec) ++ pHalData->UsbTxAggMode = _FALSE; ++ ++ if(pHalData->UsbTxAggMode){ ++ value32 = rtw_read32(Adapter, REG_TDECTRL); ++ value32 = value32 & ~(BLK_DESC_NUM_MASK << BLK_DESC_NUM_SHIFT); ++ value32 |= ((pHalData->UsbTxAggDescNum & BLK_DESC_NUM_MASK) << BLK_DESC_NUM_SHIFT); ++ ++ rtw_write32(Adapter, REG_TDECTRL, value32); ++ } ++ ++#endif ++} // usb_AggSettingTxUpdate ++ ++ ++/*----------------------------------------------------------------------------- ++ * Function: usb_AggSettingRxUpdate() ++ * ++ * Overview: Seperate TX/RX parameters update independent for TP detection and ++ * dynamic TX/RX aggreagtion parameters update. ++ * ++ * Input: PADAPTER ++ * ++ * Output/Return: NONE ++ * ++ * Revised History: ++ * When Who Remark ++ * 12/10/2010 MHC Seperate to smaller function. ++ * ++ *---------------------------------------------------------------------------*/ ++static VOID ++usb_AggSettingRxUpdate( ++ IN PADAPTER Adapter ++ ) ++{ ++#ifdef CONFIG_USB_RX_AGGREGATION ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ //PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo); ++ u8 valueDMA; ++ u8 valueUSB; ++ ++ valueDMA = rtw_read8(Adapter, REG_TRXDMA_CTRL); ++ valueUSB = rtw_read8(Adapter, REG_USB_SPECIAL_OPTION); ++ ++ switch(pHalData->UsbRxAggMode) ++ { ++ case USB_RX_AGG_DMA: ++ valueDMA |= RXDMA_AGG_EN; ++ valueUSB &= ~USB_AGG_EN; ++ break; ++ case USB_RX_AGG_USB: ++ valueDMA &= ~RXDMA_AGG_EN; ++ valueUSB |= USB_AGG_EN; ++ break; ++ case USB_RX_AGG_MIX: ++ valueDMA |= RXDMA_AGG_EN; ++ valueUSB |= USB_AGG_EN; ++ break; ++ case USB_RX_AGG_DISABLE: ++ default: ++ valueDMA &= ~RXDMA_AGG_EN; ++ valueUSB &= ~USB_AGG_EN; ++ break; ++ } ++ ++ rtw_write8(Adapter, REG_TRXDMA_CTRL, valueDMA); ++ rtw_write8(Adapter, REG_USB_SPECIAL_OPTION, valueUSB); ++ ++ switch(pHalData->UsbRxAggMode) ++ { ++ case USB_RX_AGG_DMA: ++ rtw_write8(Adapter, REG_RXDMA_AGG_PG_TH, pHalData->UsbRxAggPageCount); ++ rtw_write8(Adapter, REG_USB_DMA_AGG_TO, pHalData->UsbRxAggPageTimeout); ++ break; ++ case USB_RX_AGG_USB: ++ rtw_write8(Adapter, REG_USB_AGG_TH, pHalData->UsbRxAggBlockCount); ++ rtw_write8(Adapter, REG_USB_AGG_TO, pHalData->UsbRxAggBlockTimeout); ++ break; ++ case USB_RX_AGG_MIX: ++ rtw_write8(Adapter, REG_RXDMA_AGG_PG_TH, pHalData->UsbRxAggPageCount); ++ rtw_write8(Adapter, REG_USB_DMA_AGG_TO, pHalData->UsbRxAggPageTimeout); ++ rtw_write8(Adapter, REG_USB_AGG_TH, pHalData->UsbRxAggBlockCount); ++ rtw_write8(Adapter, REG_USB_AGG_TO, pHalData->UsbRxAggBlockTimeout); ++ break; ++ case USB_RX_AGG_DISABLE: ++ default: ++ // TODO: ++ break; ++ } ++ ++ switch(PBP_128) ++ { ++ case PBP_128: ++ pHalData->HwRxPageSize = 128; ++ break; ++ case PBP_64: ++ pHalData->HwRxPageSize = 64; ++ break; ++ case PBP_256: ++ pHalData->HwRxPageSize = 256; ++ break; ++ case PBP_512: ++ pHalData->HwRxPageSize = 512; ++ break; ++ case PBP_1024: ++ pHalData->HwRxPageSize = 1024; ++ break; ++ default: ++ //RT_ASSERT(FALSE, ("RX_PAGE_SIZE_REG_VALUE definition is incorrect!\n")); ++ break; ++ } ++#endif ++} // usb_AggSettingRxUpdate ++ ++static VOID ++InitUsbAggregationSetting( ++ IN PADAPTER Adapter ++ ) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ ++ // Tx aggregation setting ++ usb_AggSettingTxUpdate(Adapter); ++ ++ // Rx aggregation setting ++ usb_AggSettingRxUpdate(Adapter); ++ ++ // 201/12/10 MH Add for USB agg mode dynamic switch. ++ pHalData->UsbRxHighSpeedMode = _FALSE; ++} ++ ++/*----------------------------------------------------------------------------- ++ * Function: USB_AggModeSwitch() ++ * ++ * Overview: When RX traffic is more than 40M, we need to adjust some parameters to increase ++ * RX speed by increasing batch indication size. This will decrease TCP ACK speed, we ++ * need to monitor the influence of FTP/network share. ++ * For TX mode, we are still ubder investigation. ++ * ++ * Input: PADAPTER ++ * ++ * Output: NONE ++ * ++ * Return: NONE ++ * ++ * Revised History: ++ * When Who Remark ++ * 12/10/2010 MHC Create Version 0. ++ * ++ *---------------------------------------------------------------------------*/ ++VOID ++USB_AggModeSwitch( ++ IN PADAPTER Adapter ++ ) ++{ ++#if 0 ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ struct mlme_priv *pmlmepriv = &(Adapter->mlmepriv); ++ ++ //pHalData->UsbRxHighSpeedMode = FALSE; ++ // How to measure the RX speed? We assume that when traffic is more than ++ if (pMgntInfo->bRegAggDMEnable == _FALSE) ++ { ++ return; // Inf not support. ++ } ++ ++ ++ if (pmlmepriv->LinkDetectInfo.bHigherBusyTraffic == _TRUE && ++ pHalData->UsbRxHighSpeedMode == _FALSE) ++ { ++ pHalData->UsbRxHighSpeedMode = _TRUE; ++ DBG_8192C("UsbAggModeSwitchCheck to HIGH\n"); ++ } ++ else if (pmlmepriv->LinkDetectInfo.bHigherBusyTraffic == _FALSE && ++ pHalData->UsbRxHighSpeedMode == _TRUE) ++ { ++ pHalData->UsbRxHighSpeedMode = _FALSE; ++ DBG_8192C("UsbAggModeSwitchCheck to LOW\n"); ++ } ++ else ++ { ++ return; ++ } ++ ++ // 2010/12/10 MH Add for USB Aggregation judgement we need to ++ //if( pMgntInfo->LinkDetectInfo.NumRxOkInPeriod > 4000 || ++ // pMgntInfo->LinkDetectInfo.NumTxOkInPeriod > 4000 ) ++ ++#ifdef CONFIG_USB_TX_AGGREGATION ++ //usb_AggSettingTxUpdate(Adapter); ++#endif ++ ++#ifdef CONFIG_USB_RX_AGGREGATION ++ if (pHalData->UsbRxHighSpeedMode == _TRUE) ++ { ++ // 2010/12/10 MH The parameter is tested by SD1 engineer and SD3 channel emulator. ++ // USB mode ++ pHalData->UsbRxAggBlockCount = 40; ++ pHalData->UsbRxAggBlockTimeout = 5; ++ // Mix mode ++ pHalData->UsbRxAggPageCount = 72; ++ pHalData->UsbRxAggPageTimeout = 6; ++ } ++ else ++ { ++ // USB mode ++ pHalData->UsbRxAggBlockCount = pMgntInfo->RegUsbRxAggBlockCount; ++ pHalData->UsbRxAggBlockTimeout = pMgntInfo->RegUsbRxAggBlockTimeout; ++ // Mix mode ++ pHalData->UsbRxAggPageCount = pMgntInfo->RegUsbRxAggPageCount; ++ pHalData->UsbRxAggPageTimeout = pMgntInfo->RegUsbRxAggPageTimeout; ++ } ++#endif ++#endif ++} // USB_AggModeSwitch ++ ++static VOID ++_InitOperationMode( ++ IN PADAPTER Adapter ++ ) ++{ ++#if 0//gtest ++ PHAL_DATA_8192CUSB pHalData = GetHalData8192CUsb(Adapter); ++ u1Byte regBwOpMode = 0; ++ u4Byte regRATR = 0, regRRSR = 0; ++ ++ ++ //1 This part need to modified according to the rate set we filtered!! ++ // ++ // Set RRSR, RATR, and REG_BWOPMODE registers ++ // ++ switch(Adapter->RegWirelessMode) ++ { ++ case WIRELESS_MODE_B: ++ regBwOpMode = BW_OPMODE_20MHZ; ++ regRATR = RATE_ALL_CCK; ++ regRRSR = RATE_ALL_CCK; ++ break; ++ case WIRELESS_MODE_A: ++ ASSERT(FALSE); ++#if 0 ++ regBwOpMode = BW_OPMODE_5G |BW_OPMODE_20MHZ; ++ regRATR = RATE_ALL_OFDM_AG; ++ regRRSR = RATE_ALL_OFDM_AG; ++#endif ++ break; ++ case WIRELESS_MODE_G: ++ regBwOpMode = BW_OPMODE_20MHZ; ++ regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG; ++ regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG; ++ break; ++ case WIRELESS_MODE_AUTO: ++ if (Adapter->bInHctTest) ++ { ++ regBwOpMode = BW_OPMODE_20MHZ; ++ regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG; ++ regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG; ++ } ++ else ++ { ++ regBwOpMode = BW_OPMODE_20MHZ; ++ regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG | RATE_ALL_OFDM_1SS | RATE_ALL_OFDM_2SS; ++ regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG; ++ } ++ break; ++ case WIRELESS_MODE_N_24G: ++ // It support CCK rate by default. ++ // CCK rate will be filtered out only when associated AP does not support it. ++ regBwOpMode = BW_OPMODE_20MHZ; ++ regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG | RATE_ALL_OFDM_1SS | RATE_ALL_OFDM_2SS; ++ regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG; ++ break; ++ case WIRELESS_MODE_N_5G: ++ ASSERT(FALSE); ++#if 0 ++ regBwOpMode = BW_OPMODE_5G; ++ regRATR = RATE_ALL_OFDM_AG | RATE_ALL_OFDM_1SS | RATE_ALL_OFDM_2SS; ++ regRRSR = RATE_ALL_OFDM_AG; ++#endif ++ break; ++ } ++ ++ // Ziv ???????? ++ //PlatformEFIOWrite4Byte(Adapter, REG_INIRTS_RATE_SEL, regRRSR); ++ PlatformEFIOWrite1Byte(Adapter, REG_BWOPMODE, regBwOpMode); ++ ++ // For Min Spacing configuration. ++ switch(pHalData->RF_Type) ++ { ++ case RF_1T2R: ++ case RF_1T1R: ++ RT_TRACE(COMP_INIT, DBG_LOUD, ("Initializeadapter: RF_Type%s\n", (pHalData->RF_Type==RF_1T1R? "(1T1R)":"(1T2R)"))); ++ Adapter->MgntInfo.MinSpaceCfg = (MAX_MSS_DENSITY_1T<<3); ++ break; ++ case RF_2T2R: ++ case RF_2T2R_GREEN: ++ RT_TRACE(COMP_INIT, DBG_LOUD, ("Initializeadapter:RF_Type(2T2R)\n")); ++ Adapter->MgntInfo.MinSpaceCfg = (MAX_MSS_DENSITY_2T<<3); ++ break; ++ } ++ ++ PlatformEFIOWrite1Byte(Adapter, REG_AMPDU_MIN_SPACE, Adapter->MgntInfo.MinSpaceCfg); ++#endif ++} ++ ++ ++ static VOID ++_InitBeaconParameters( ++ IN PADAPTER Adapter ++ ) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ ++ rtw_write16(Adapter, REG_BCN_CTRL, 0x1010); ++ ++ // TODO: Remove these magic number ++ rtw_write16(Adapter, REG_TBTT_PROHIBIT,0x6404);// ms ++ rtw_write8(Adapter, REG_DRVERLYINT, DRIVER_EARLY_INT_TIME);// 5ms ++ rtw_write8(Adapter, REG_BCNDMATIM, BCN_DMA_ATIME_INT_TIME); // 2ms ++ ++ // Suggested by designer timchen. Change beacon AIFS to the largest number ++ // beacause test chip does not contension before sending beacon. by tynli. 2009.11.03 ++ if(IS_NORMAL_CHIP( pHalData->VersionID)){ ++ rtw_write16(Adapter, REG_BCNTCFG, 0x660F); ++ } ++ else{ ++ rtw_write16(Adapter, REG_BCNTCFG, 0x66FF); ++ } ++ ++} ++ ++static VOID ++_InitRFType( ++ IN PADAPTER Adapter ++ ) ++{ ++ struct registry_priv *pregpriv = &Adapter->registrypriv; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ BOOLEAN is92CU = IS_92C_SERIAL(pHalData->VersionID); ++ ++#if DISABLE_BB_RF ++ pHalData->rf_chip = RF_PSEUDO_11N; ++ return; ++#endif ++ ++ pHalData->rf_chip = RF_6052; ++ ++ if(_FALSE == is92CU){ ++ pHalData->rf_type = RF_1T1R; ++ DBG_8192C("Set RF Chip ID to RF_6052 and RF type to 1T1R.\n"); ++ return; ++ } ++ ++ // TODO: Consider that EEPROM set 92CU to 1T1R later. ++ // Force to overwrite setting according to chip version. Ignore EEPROM setting. ++ //pHalData->RF_Type = is92CU ? RF_2T2R : RF_1T1R; ++ MSG_8192C("Set RF Chip ID to RF_6052 and RF type to %d.\n", pHalData->rf_type); ++ ++} ++ ++static VOID _InitAdhocWorkaroundParams(IN PADAPTER Adapter) ++{ ++#if RTL8192CU_ADHOC_WORKAROUND_SETTING ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ pHalData->RegBcnCtrlVal = rtw_read8(Adapter, REG_BCN_CTRL); ++ pHalData->RegTxPause = rtw_read8(Adapter, REG_TXPAUSE); ++ pHalData->RegFwHwTxQCtrl = rtw_read8(Adapter, REG_FWHW_TXQ_CTRL+2); ++ pHalData->RegReg542 = rtw_read8(Adapter, REG_TBTT_PROHIBIT+2); ++#endif ++} ++ ++static VOID ++_BeaconFunctionEnable( ++ IN PADAPTER Adapter, ++ IN BOOLEAN Enable, ++ IN BOOLEAN Linked ++ ) ++{ ++#if 0 ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ u8 value8 = 0; ++ ++ //value8 = Enable ? (EN_BCN_FUNCTION | EN_TXBCN_RPT) : EN_BCN_FUNCTION; ++ ++ if(_FALSE == Linked){ ++ if(IS_NORMAL_CHIP( pHalData->VersionID)){ ++ value8 |= DIS_TSF_UDT0_NORMAL_CHIP; ++ } ++ else{ ++ value8 |= DIS_TSF_UDT0_TEST_CHIP; ++ } ++ } ++ ++ rtw_write8(Adapter, REG_BCN_CTRL, value8); ++#else ++ rtw_write8(Adapter, REG_BCN_CTRL, (BIT4 | BIT3 | BIT1)); ++ //SetBcnCtrlReg(Adapter, (BIT4 | BIT3 | BIT1), 0x00); ++ //RT_TRACE(COMP_BEACON, DBG_LOUD, ("_BeaconFunctionEnable 0x550 0x%x\n", PlatformEFIORead1Byte(Adapter, 0x550))); ++ ++ rtw_write8(Adapter, REG_RD_CTRL+1, 0x6F); ++#endif ++} ++ ++ ++// Set CCK and OFDM Block "ON" ++static VOID _BBTurnOnBlock( ++ IN PADAPTER Adapter ++ ) ++{ ++#if (DISABLE_BB_RF) ++ return; ++#endif ++ ++ PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bCCKEn, 0x1); ++ PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bOFDMEn, 0x1); ++} ++ ++static VOID _RfPowerSave( ++ IN PADAPTER Adapter ++ ) ++{ ++#if 0 ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo); ++ u1Byte eRFPath; ++ ++#if (DISABLE_BB_RF) ++ return; ++#endif ++ ++ if(pMgntInfo->RegRfOff == TRUE){ // User disable RF via registry. ++ RT_TRACE((COMP_INIT|COMP_RF), DBG_LOUD, ("InitializeAdapter8192CUsb(): Turn off RF for RegRfOff.\n")); ++ MgntActSet_RF_State(Adapter, eRfOff, RF_CHANGE_BY_SW); ++ // Those action will be discard in MgntActSet_RF_State because off the same state ++ for(eRFPath = 0; eRFPath NumTotalRFPath; eRFPath++) ++ PHY_SetRFReg(Adapter, (RF90_RADIO_PATH_E)eRFPath, 0x4, 0xC00, 0x0); ++ } ++ else if(pMgntInfo->RfOffReason > RF_CHANGE_BY_PS){ // H/W or S/W RF OFF before sleep. ++ RT_TRACE((COMP_INIT|COMP_RF), DBG_LOUD, ("InitializeAdapter8192CUsb(): Turn off RF for RfOffReason(%ld).\n", pMgntInfo->RfOffReason)); ++ MgntActSet_RF_State(Adapter, eRfOff, pMgntInfo->RfOffReason); ++ } ++ else{ ++ pHalData->eRFPowerState = eRfOn; ++ pMgntInfo->RfOffReason = 0; ++ if(Adapter->bInSetPower || Adapter->bResetInProgress) ++ PlatformUsbEnableInPipes(Adapter); ++ RT_TRACE((COMP_INIT|COMP_RF), DBG_LOUD, ("InitializeAdapter8192CUsb(): RF is on.\n")); ++ } ++#endif ++} ++ ++enum { ++ Antenna_Lfet = 1, ++ Antenna_Right = 2, ++}; ++ ++static VOID ++_InitAntenna_Selection(IN PADAPTER Adapter) ++{ ++ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ ++ if(pHalData->AntDivCfg==0) ++ return; ++ DBG_8192C("==> %s ....\n",__FUNCTION__); ++ ++ if((RF_1T1R == pHalData->rf_type)) ++ { ++ rtw_write32(Adapter, REG_LEDCFG0, rtw_read32(Adapter, REG_LEDCFG0)|BIT23); ++ PHY_SetBBReg(Adapter, rFPGA0_XAB_RFParameter, BIT13, 0x01); ++ ++ if(PHY_QueryBBReg(Adapter, rFPGA0_XA_RFInterfaceOE, 0x300) == Antenna_A) ++ pHalData->CurAntenna = Antenna_A; ++ else ++ pHalData->CurAntenna = Antenna_B; ++ DBG_8192C("%s,Cur_ant:(%x)%s\n",__FUNCTION__,pHalData->CurAntenna,(pHalData->CurAntenna == Antenna_A)?"Antenna_A":"Antenna_B"); ++ ++} ++ ++ ++} ++// ++// 2010/08/09 MH Add for power down check. ++// ++static BOOLEAN ++HalDetectPwrDownMode( ++ IN PADAPTER Adapter ++ ) ++{ ++ u8 tmpvalue; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ struct pwrctrl_priv *pwrctrlpriv = &Adapter->pwrctrlpriv; ++ ++ EFUSE_ShadowRead(Adapter, 1, EEPROM_RF_OPT3, (u32 *)&tmpvalue); ++ ++ // 2010/08/25 MH INF priority > PDN Efuse value. ++ if(tmpvalue & BIT4 && pwrctrlpriv->reg_pdnmode) ++ { ++ pHalData->pwrdown = _TRUE; ++ } ++ else ++ { ++ pHalData->pwrdown = _FALSE; ++ } ++ ++ DBG_8192C("HalDetectPwrDownMode(): PDN=%d\n", pHalData->pwrdown); ++ return pHalData->pwrdown; ++ ++} // HalDetectPwrDownMode ++ ++ ++// ++// 2010/08/26 MH Add for selective suspend mode check. ++// If Efuse 0x0e bit1 is not enabled, we can not support selective suspend for Minicard and ++// slim card. ++// ++static VOID ++HalDetectSelectiveSuspendMode( ++ IN PADAPTER Adapter ++ ) ++{ ++ u8 tmpvalue; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ struct dvobj_priv *pdvobjpriv = &Adapter->dvobjpriv; ++ ++ // If support HW radio detect, we need to enable WOL ability, otherwise, we ++ // can not use FW to notify host the power state switch. ++ ++ EFUSE_ShadowRead(Adapter, 1, EEPROM_USB_OPTIONAL1, (u32 *)&tmpvalue); ++ ++ DBG_8192C("HalDetectSelectiveSuspendMode(): SS "); ++ if(tmpvalue & BIT1) ++ { ++ DBG_8192C("Enable\n"); ++ } ++ else ++ { ++ DBG_8192C("Disable\n"); ++ pdvobjpriv->RegUsbSS = _FALSE; ++ } ++ ++ // 2010/09/01 MH According to Dongle Selective Suspend INF. We can switch SS mode. ++ if (pdvobjpriv->RegUsbSS && !SUPPORT_HW_RADIO_DETECT(pHalData)) ++ { ++ //PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo); ++ ++ //if (!pMgntInfo->bRegDongleSS) ++ //{ ++ // RT_TRACE(COMP_INIT, DBG_LOUD, ("Dongle disable SS\n")); ++ pdvobjpriv->RegUsbSS = _FALSE; ++ //} ++ } ++} // HalDetectSelectiveSuspendMode ++/*----------------------------------------------------------------------------- ++ * Function: HwSuspendModeEnable92Cu() ++ * ++ * Overview: HW suspend mode switch. ++ * ++ * Input: NONE ++ * ++ * Output: NONE ++ * ++ * Return: NONE ++ * ++ * Revised History: ++ * When Who Remark ++ * 08/23/2010 MHC HW suspend mode switch test.. ++ *---------------------------------------------------------------------------*/ ++static VOID ++HwSuspendModeEnable92Cu( ++ IN PADAPTER pAdapter, ++ IN u8 Type ++ ) ++{ ++ //PRT_USB_DEVICE pDevice = GET_RT_USB_DEVICE(pAdapter); ++ u16 reg = rtw_read16(pAdapter, REG_GPIO_MUXCFG); ++ ++ //if (!pDevice->RegUsbSS) ++ { ++ return; ++ } ++ ++ // ++ // 2010/08/23 MH According to Alfred's suggestion, we need to to prevent HW ++ // to enter suspend mode automatically. Otherwise, it will shut down major power ++ // domain and 8051 will stop. When we try to enter selective suspend mode, we ++ // need to prevent HW to enter D2 mode aumotmatically. Another way, Host will ++ // issue a S10 signal to power domain. Then it will cleat SIC setting(from Yngli). ++ // We need to enable HW suspend mode when enter S3/S4 or disable. We need ++ // to disable HW suspend mode for IPS/radio_off. ++ // ++ //RT_TRACE(COMP_RF, DBG_LOUD, ("HwSuspendModeEnable92Cu = %d\n", Type)); ++ if (Type == _FALSE) ++ { ++ reg |= BIT14; ++ //RT_TRACE(COMP_RF, DBG_LOUD, ("REG_GPIO_MUXCFG = %x\n", reg)); ++ rtw_write16(pAdapter, REG_GPIO_MUXCFG, reg); ++ reg |= BIT12; ++ //RT_TRACE(COMP_RF, DBG_LOUD, ("REG_GPIO_MUXCFG = %x\n", reg)); ++ rtw_write16(pAdapter, REG_GPIO_MUXCFG, reg); ++ } ++ else ++ { ++ reg &= (~BIT12); ++ rtw_write16(pAdapter, REG_GPIO_MUXCFG, reg); ++ reg &= (~BIT14); ++ rtw_write16(pAdapter, REG_GPIO_MUXCFG, reg); ++ } ++ ++} // HwSuspendModeEnable92Cu ++rt_rf_power_state RfOnOffDetect(IN PADAPTER pAdapter ) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); ++ u8 val8; ++ rt_rf_power_state rfpowerstate = rf_off; ++ ++ if(pAdapter->pwrctrlpriv.bHWPowerdown) ++ { ++ val8 = rtw_read8(pAdapter, REG_HSISR); ++ DBG_8192C("pwrdown, 0x5c(BIT7)=%02x\n", val8); ++ rfpowerstate = (val8 & BIT7) ? rf_off: rf_on; ++ } ++ else // rf on/off ++ { ++ rtw_write8( pAdapter, REG_MAC_PINMUX_CFG,rtw_read8(pAdapter, REG_MAC_PINMUX_CFG)&~(BIT3)); ++ val8 = rtw_read8(pAdapter, REG_GPIO_IO_SEL); ++ DBG_8192C("GPIO_IN=%02x\n", val8); ++ rfpowerstate = (val8 & BIT3) ? rf_on : rf_off; ++ } ++ return rfpowerstate; ++} // HalDetectPwrDownMode ++ ++void _ps_open_RF(_adapter *padapter); ++ ++ ++u32 rtl8192cu_hal_init(PADAPTER Adapter) ++{ ++ u8 val8 = 0; ++ u32 boundary, status = _SUCCESS; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ struct pwrctrl_priv *pwrctrlpriv = &Adapter->pwrctrlpriv; ++ struct registry_priv *pregistrypriv = &Adapter->registrypriv; ++ u8 isNormal = IS_NORMAL_CHIP(pHalData->VersionID); ++ u8 is92C = IS_92C_SERIAL(pHalData->VersionID); ++ rt_rf_power_state eRfPowerStateToSet; ++#ifdef CONFIG_BT_COEXIST ++ struct btcoexist_priv *pbtpriv = &(pHalData->bt_coexist); ++#endif ++ ++ u32 init_start_time = rtw_get_current_time(); ++ ++ ++#ifdef DBG_HAL_INIT_PROFILING ++ ++ enum HAL_INIT_STAGES { ++ HAL_INIT_STAGES_BEGIN = 0, ++ HAL_INIT_STAGES_INIT_PW_ON, ++ HAL_INIT_STAGES_MISC01, ++ HAL_INIT_STAGES_DOWNLOAD_FW, ++ HAL_INIT_STAGES_INIT_LLTT, ++ HAL_INIT_STAGES_MAC, ++ HAL_INIT_STAGES_MISC02, ++ HAL_INIT_STAGES_BB, ++ HAL_INIT_STAGES_RF, ++ HAL_INIT_STAGES_TURN_ON_BLOCK, ++ HAL_INIT_STAGES_INIT_SECURITY, ++ HAL_INIT_STAGES_MISC11, ++ //HAL_INIT_STAGES_RF_PS, ++ HAL_INIT_STAGES_IQK, ++ HAL_INIT_STAGES_PW_TRACK, ++ HAL_INIT_STAGES_LCK, ++ HAL_INIT_STAGES_MISC21, ++ HAL_INIT_STAGES_INIT_PABIAS, ++ HAL_INIT_STAGES_BT_COEXIST, ++ //HAL_INIT_STAGES_ANTENNA_SEL, ++ HAL_INIT_STAGES_INIT_HAL_DM, ++ HAL_INIT_STAGES_MISC31, ++ HAL_INIT_STAGES_END, ++ HAL_INIT_STAGES_NUM ++ }; ++ ++ char * hal_init_stages_str[] = { ++ "HAL_INIT_STAGES_BEGIN", ++ "HAL_INIT_STAGES_INIT_PW_ON", ++ "HAL_INIT_STAGES_MISC01", ++ "HAL_INIT_STAGES_DOWNLOAD_FW", ++ "HAL_INIT_STAGES_INIT_LLTT", ++ "HAL_INIT_STAGES_MAC", ++ "HAL_INIT_STAGES_MISC02", ++ "HAL_INIT_STAGES_BB", ++ "HAL_INIT_STAGES_RF", ++ "HAL_INIT_STAGES_TURN_ON_BLOCK", ++ "HAL_INIT_STAGES_INIT_SECURITY", ++ "HAL_INIT_STAGES_MISC11", ++ //"HAL_INIT_STAGES_RF_PS", ++ "HAL_INIT_STAGES_IQK", ++ "HAL_INIT_STAGES_PW_TRACK", ++ "HAL_INIT_STAGES_LCK", ++ "HAL_INIT_STAGES_MISC21", ++ "HAL_INIT_STAGES_INIT_PABIAS", ++ "HAL_INIT_STAGES_BT_COEXIST", ++ //"HAL_INIT_STAGES_ANTENNA_SEL", ++ "HAL_INIT_STAGES_INIT_HAL_DM", ++ "HAL_INIT_STAGES_MISC31", ++ "HAL_INIT_STAGES_END", ++ }; ++ ++ int hal_init_profiling_i; ++ u32 hal_init_stages_timestamp[HAL_INIT_STAGES_NUM]; //used to record the time of each stage's starting point ++ ++ for(hal_init_profiling_i=0;hal_init_profiling_ipwrctrlpriv.bkeepfwalive) ++ { ++ _ps_open_RF(Adapter); ++ ++ if(pHalData->bIQKInitialized ){ ++ rtl8192c_PHY_IQCalibrate(Adapter,_TRUE); ++ } ++ else{ ++ rtl8192c_PHY_IQCalibrate(Adapter,_FALSE); ++ pHalData->bIQKInitialized = _TRUE; ++ } ++ rtl8192c_dm_CheckTXPowerTracking(Adapter); ++ rtl8192c_PHY_LCCalibrate(Adapter); ++ ++ goto exit; ++ } ++ ++HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_PW_ON); ++ status = _InitPowerOn(Adapter); ++ if(status == _FAIL){ ++ RT_TRACE(_module_hci_hal_init_c_, _drv_err_, ("Failed to init power on!\n")); ++ goto exit; ++ } ++ ++ ++HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MISC01); ++ _InitQueueReservedPage(Adapter); ++ _InitTxBufferBoundary(Adapter); ++ _InitQueuePriority(Adapter); ++ _InitPageBoundary(Adapter); ++ _InitTransferPageSize(Adapter); ++ ++ ++#if ENABLE_USB_DROP_INCORRECT_OUT ++ _InitHardwareDropIncorrectBulkOut(Adapter); ++#endif ++ ++ if(pHalData->bRDGEnable){ ++ _InitRDGSetting(Adapter); ++ } ++ ++HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_DOWNLOAD_FW); ++#if (1 == MP_DRIVER) ++ _InitRxSetting(Adapter); ++ // Don't Download Firmware ++ Adapter->bFWReady = _FALSE; ++#elif RTL8192CU_FW_DOWNLOAD_ENABLE ++ status = FirmwareDownload92C(Adapter,_FALSE); ++ if(status != _SUCCESS) ++ { ++ Adapter->bFWReady = _FALSE; ++ pHalData->fw_ractrl = _FALSE; ++ DBG_8192C("fw download fail!\n"); ++ goto exit; ++ } ++ else ++ { ++ Adapter->bFWReady = _TRUE; ++ pHalData->fw_ractrl = _TRUE; ++ DBG_8192C("fw download ok!\n"); ++ } ++#endif ++ ++ InitializeFirmwareVars92C(Adapter); ++ ++ if(pwrctrlpriv->reg_rfoff == _TRUE){ ++ pwrctrlpriv->rf_pwrstate = rf_off; ++ } ++ ++ // 2010/08/09 MH We need to check if we need to turnon or off RF after detecting ++ // HW GPIO pin. Before PHY_RFConfig8192C. ++ //HalDetectPwrDownMode(Adapter); ++ // 2010/08/26 MH If Efuse does not support sective suspend then disable the function. ++ //HalDetectSelectiveSuspendMode(Adapter); ++ ++ ++ // Set RF type for BB/RF configuration ++ _InitRFType(Adapter);//->_ReadRFType() ++ ++ // Save target channel ++ // Current Channel will be updated again later. ++ pHalData->CurrentChannel = 6;//default set to 6 ++ ++HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_LLTT); ++ if(!pregistrypriv->wifi_spec){ ++ boundary = TX_PAGE_BOUNDARY; ++ } ++ else{// for WMM ++ boundary = (IS_NORMAL_CHIP(pHalData->VersionID)) ?WMM_NORMAL_TX_PAGE_BOUNDARY ++ :WMM_TEST_TX_PAGE_BOUNDARY; ++ } ++ status = InitLLTTable(Adapter, boundary); ++ if(status == _FAIL){ ++ RT_TRACE(_module_hci_hal_init_c_, _drv_err_, ("Failed to init LLT table\n")); ++ goto exit; ++ } ++ ++HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MAC); ++#if (HAL_MAC_ENABLE == 1) ++ status = PHY_MACConfig8192C(Adapter); ++ if(status == _FAIL) ++ { ++ goto exit; ++ } ++#endif ++ ++HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MISC02); ++ // Get Rx PHY status in order to report RSSI and others. ++ _InitDriverInfoSize(Adapter, DRVINFO_SZ); ++ ++ _InitInterrupt(Adapter); ++ _InitID(Adapter);//set mac_address ++ _InitNetworkType(Adapter);//set msr ++ _InitWMACSetting(Adapter); ++ _InitAdaptiveCtrl(Adapter); ++ _InitEDCA(Adapter); ++ _InitRateFallback(Adapter); ++ _InitRetryFunction(Adapter); ++ InitUsbAggregationSetting(Adapter); ++ _InitOperationMode(Adapter);//todo ++ _InitBeaconParameters(Adapter); ++ _InitBeaconMaxError(Adapter, _TRUE); ++ ++#if defined(CONFIG_CONCURRENT_MODE) || defined(CONFIG_TX_MCAST2UNI) ++ ++#ifdef CONFIG_CHECK_AC_LIFETIME ++ // Enable lifetime check for the four ACs ++ rtw_write8(Adapter, REG_LIFETIME_EN, 0x0F); ++#endif // CONFIG_CHECK_AC_LIFETIME ++ ++#ifdef CONFIG_TX_MCAST2UNI ++ rtw_write16(Adapter, REG_PKT_VO_VI_LIFE_TIME, 0x0400); // unit: 256us. 256ms ++ rtw_write16(Adapter, REG_PKT_BE_BK_LIFE_TIME, 0x0400); // unit: 256us. 256ms ++#else // CONFIG_TX_MCAST2UNI ++ rtw_write16(Adapter, REG_PKT_VO_VI_LIFE_TIME, 0x3000); // unit: 256us. 3s ++ rtw_write16(Adapter, REG_PKT_BE_BK_LIFE_TIME, 0x3000); // unit: 256us. 3s ++#endif // CONFIG_TX_MCAST2UNI ++#endif // CONFIG_CONCURRENT_MODE || CONFIG_TX_MCAST2UNI ++ ++ ++#ifdef CONFIG_LED ++ _InitHWLed(Adapter); ++#endif //CONFIG_LED ++ ++ // ++ //d. Initialize BB related configurations. ++ // ++ ++HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_BB); ++#if (HAL_BB_ENABLE == 1) ++ status = PHY_BBConfig8192C(Adapter); ++ if(status == _FAIL) ++ { ++ goto exit; ++ } ++#endif ++ ++ // 92CU use 3-wire to r/w RF ++ //pHalData->Rf_Mode = RF_OP_By_SW_3wire; ++ ++HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_RF); ++#if (HAL_RF_ENABLE == 1) ++ status = PHY_RFConfig8192C(Adapter); ++ if(status == _FAIL) ++ { ++ goto exit; ++ } ++ ++ if(IS_VENDOR_UMC_A_CUT(pHalData->VersionID) && !IS_92C_SERIAL(pHalData->VersionID)) ++ { ++ PHY_SetRFReg(Adapter, RF90_PATH_A, RF_RX_G1, bMaskDWord, 0x30255); ++ PHY_SetRFReg(Adapter, RF90_PATH_A, RF_RX_G2, bMaskDWord, 0x50a00); ++ } ++#endif ++ ++ // ++ // Joseph Note: Keep RfRegChnlVal for later use. ++ // ++ pHalData->RfRegChnlVal[0] = PHY_QueryRFReg(Adapter, (RF90_RADIO_PATH_E)0, RF_CHNLBW, bRFRegOffsetMask); ++ pHalData->RfRegChnlVal[1] = PHY_QueryRFReg(Adapter, (RF90_RADIO_PATH_E)1, RF_CHNLBW, bRFRegOffsetMask); ++ ++HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_TURN_ON_BLOCK); ++ _BBTurnOnBlock(Adapter); ++ //NicIFSetMacAddress(padapter, padapter->PermanentAddress); ++ ++HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_SECURITY); ++ invalidate_cam_all(Adapter); ++ ++HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MISC11); ++ // 2010/12/17 MH We need to set TX power according to EFUSE content at first. ++ PHY_SetTxPowerLevel8192C(Adapter, pHalData->CurrentChannel); ++ ++// Move by Neo for USB SS to below setp ++//_RfPowerSave(Adapter); ++ ++ if (!IS_92C_SERIAL( pHalData->VersionID) && (pHalData->AntDivCfg!=0)) ++ { //for 88CU ,1T1R ++ _InitAntenna_Selection(Adapter); ++ } ++ ++ ++ // ++ // Disable BAR, suggested by Scott ++ // 2010.04.09 add by hpfan ++ // ++ rtw_write32(Adapter, REG_BAR_MODE_CTRL, 0x0201ffff); ++ ++ // HW SEQ CTRL ++ //set 0x0 to 0xFF by tynli. Default enable HW SEQ NUM. ++ rtw_write8(Adapter,REG_HWSEQ_CTRL, 0xFF); ++ ++ if(pregistrypriv->wifi_spec) ++ rtw_write16(Adapter,REG_FAST_EDCA_CTRL ,0); ++ ++ //Nav limit , suggest by scott ++ rtw_write8(Adapter, 0x652, 0x0); ++ ++#if (MP_DRIVER == 1) ++ Adapter->mppriv.channel = pHalData->CurrentChannel; ++ MPT_InitializeAdapter(Adapter, Adapter->mppriv.channel); ++#else ++ // ++ // 2010/08/11 MH Merge from 8192SE for Minicard init. We need to confirm current radio status ++ // and then decide to enable RF or not.!!!??? For Selective suspend mode. We may not ++ // call init_adapter. May cause some problem?? ++ // ++ // Fix the bug that Hw/Sw radio off before S3/S4, the RF off action will not be executed ++ // in MgntActSet_RF_State() after wake up, because the value of pHalData->eRFPowerState ++ // is the same as eRfOff, we should change it to eRfOn after we config RF parameters. ++ // Added by tynli. 2010.03.30. ++ pwrctrlpriv->rf_pwrstate = rf_on; ++ ++#if 0 //to do ++ RT_CLEAR_PS_LEVEL(pwrctrlpriv, RT_RF_OFF_LEVL_HALT_NIC); ++#if 1 //Todo ++ // 20100326 Joseph: Copy from GPIOChangeRFWorkItemCallBack() function to check HW radio on/off. ++ // 20100329 Joseph: Revise and integrate the HW/SW radio off code in initialization. ++ ++ eRfPowerStateToSet = (rt_rf_power_state) RfOnOffDetect(Adapter); ++ pwrctrlpriv->rfoff_reason |= eRfPowerStateToSet==rf_on ? RF_CHANGE_BY_INIT : RF_CHANGE_BY_HW; ++ pwrctrlpriv->rfoff_reason |= (pwrctrlpriv->reg_rfoff) ? RF_CHANGE_BY_SW : 0; ++ ++ if(pwrctrlpriv->rfoff_reason&RF_CHANGE_BY_HW) ++ pwrctrlpriv->b_hw_radio_off = _TRUE; ++ ++ DBG_8192C("eRfPowerStateToSet=%d\n", eRfPowerStateToSet); ++ ++ if(pwrctrlpriv->reg_rfoff == _TRUE) ++ { // User disable RF via registry. ++ DBG_8192C("InitializeAdapter8192CU(): Turn off RF for RegRfOff.\n"); ++ //MgntActSet_RF_State(Adapter, rf_off, RF_CHANGE_BY_SW, _TRUE); ++ ++ // Those action will be discard in MgntActSet_RF_State because off the same state ++ //for(eRFPath = 0; eRFPath NumTotalRFPath; eRFPath++) ++ //PHY_SetRFReg(Adapter, (RF90_RADIO_PATH_E)eRFPath, 0x4, 0xC00, 0x0); ++ } ++ else if(pwrctrlpriv->rfoff_reason > RF_CHANGE_BY_PS) ++ { // H/W or S/W RF OFF before sleep. ++ DBG_8192C(" Turn off RF for RfOffReason(%x) ----------\n", pwrctrlpriv->rfoff_reason); ++ //pwrctrlpriv->rfoff_reason = RF_CHANGE_BY_INIT; ++ pwrctrlpriv->rf_pwrstate = rf_on; ++ //MgntActSet_RF_State(Adapter, rf_off, pwrctrlpriv->rfoff_reason, _TRUE); ++ } ++ else ++ { ++ // Perform GPIO polling to find out current RF state. added by Roger, 2010.04.09. ++ if(pHalData->BoardType == BOARD_MINICARD /*&& (Adapter->MgntInfo.PowerSaveControl.bGpioRfSw)*/) ++ { ++ DBG_8192C("InitializeAdapter8192CU(): RF=%d \n", eRfPowerStateToSet); ++ if (eRfPowerStateToSet == rf_off) ++ { ++ //MgntActSet_RF_State(Adapter, rf_off, RF_CHANGE_BY_HW, _TRUE); ++ pwrctrlpriv->b_hw_radio_off = _TRUE; ++ } ++ else ++ { ++ pwrctrlpriv->rf_pwrstate = rf_off; ++ pwrctrlpriv->rfoff_reason = RF_CHANGE_BY_INIT; ++ pwrctrlpriv->b_hw_radio_off = _FALSE; ++ //MgntActSet_RF_State(Adapter, rf_on, pwrctrlpriv->rfoff_reason, _TRUE); ++ } ++ } ++ else ++ { ++ pwrctrlpriv->rf_pwrstate = rf_off; ++ pwrctrlpriv->rfoff_reason = RF_CHANGE_BY_INIT; ++ //MgntActSet_RF_State(Adapter, rf_on, pwrctrlpriv->rfoff_reason, _TRUE); ++ } ++ ++ pwrctrlpriv->rfoff_reason = 0; ++ pwrctrlpriv->b_hw_radio_off = _FALSE; ++ pwrctrlpriv->rf_pwrstate = rf_on; ++ rtw_led_control(Adapter, LED_CTL_POWER_ON); ++ ++ } ++ ++ // 2010/-8/09 MH For power down module, we need to enable register block contrl reg at 0x1c. ++ // Then enable power down control bit of register 0x04 BIT4 and BIT15 as 1. ++ if(pHalData->pwrdown && eRfPowerStateToSet == rf_off) ++ { ++ // Enable register area 0x0-0xc. ++ rtw_write8(Adapter, REG_RSV_CTRL, 0x0); ++ ++ // ++ // We should configure HW PDn source for WiFi ONLY, and then ++ // our HW will be set in power-down mode if PDn source from all functions are configured. ++ // 2010.10.06. ++ // ++ //if(IS_HARDWARE_TYPE_8723U(Adapter)) ++ //{ ++ // u1bTmp = rtw_read8(Adapter, REG_MULTI_FUNC_CTRL); ++ // rtw_write8(Adapter, REG_MULTI_FUNC_CTRL, (u1bTmp|WL_HWPDN_EN)); ++ //} ++ //else ++ //{ ++ rtw_write16(Adapter, REG_APS_FSMCO, 0x8812); ++ //} ++ } ++ //DrvIFIndicateCurrentPhyStatus(Adapter); // 2010/08/17 MH Disable to prevent BSOD. ++#endif ++#endif ++ ++HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_IQK); ++ // 2010/08/26 MH Merge from 8192CE. ++ if(pwrctrlpriv->rf_pwrstate == rf_on) ++ { ++ if(pHalData->bIQKInitialized ){ ++ rtl8192c_PHY_IQCalibrate(Adapter,_TRUE); ++ } ++ else ++ { ++ rtl8192c_PHY_IQCalibrate(Adapter,_FALSE); ++ pHalData->bIQKInitialized = _TRUE; ++ } ++ ++HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_PW_TRACK); ++ rtl8192c_dm_CheckTXPowerTracking(Adapter); ++ ++HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_LCK); ++ rtl8192c_PHY_LCCalibrate(Adapter); ++ } ++#endif /* #if (MP_DRIVER == 1) */ ++ ++ ++HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MISC21); ++#if RTL8192CU_ADHOC_WORKAROUND_SETTING ++ _InitAdhocWorkaroundParams(Adapter); ++#endif ++ ++ ++#ifdef USB_INTERFERENCE_ISSUE ++ //fixed USB interface interference issue ++ rtw_write8(Adapter, 0xfe40, 0xe0); ++ rtw_write8(Adapter, 0xfe41, 0x8d); ++ rtw_write8(Adapter, 0xfe42, 0x80); ++ rtw_write32(Adapter,0x20c,0xfd0320); ++#if 1 ++ //2011/01/07 ,suggest by Johnny,for solved the problem that too many protocol error on USB bus ++ if(!IS_VENDOR_UMC_A_CUT(pHalData->VersionID) )//&& !IS_92C_SERIAL(pHalData->VersionID))// TSMC , 8188 ++ { ++ // 0xE6=0x94 ++ rtw_write8(Adapter, 0xFE40, 0xE6); ++ rtw_write8(Adapter, 0xFE41, 0x94); ++ rtw_write8(Adapter, 0xFE42, 0x80); ++ ++ // 0xE0=0x19 ++ rtw_write8(Adapter, 0xFE40, 0xE0); ++ rtw_write8(Adapter, 0xFE41, 0x19); ++ rtw_write8(Adapter, 0xFE42, 0x80); ++ ++ // 0xE5=0x91 ++ rtw_write8(Adapter, 0xFE40, 0xE5); ++ rtw_write8(Adapter, 0xFE41, 0x91); ++ rtw_write8(Adapter, 0xFE42, 0x80); ++ ++ // 0xE2=0x81 ++ rtw_write8(Adapter, 0xFE40, 0xE2); ++ rtw_write8(Adapter, 0xFE41, 0x81); ++ rtw_write8(Adapter, 0xFE42, 0x80); ++ ++ } ++ ++#endif ++#endif //USB_INTERFERENCE_ISSUE ++ ++HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_PABIAS); ++ _InitPABias(Adapter); ++ ++HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_BT_COEXIST); ++#ifdef CONFIG_BT_COEXIST ++ _InitBTCoexist(Adapter); ++#endif ++ ++HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_INIT_HAL_DM); ++ rtl8192c_InitHalDm(Adapter); ++ ++ // 2010/08/23 MH According to Alfred's suggestion, we need to to prevent HW enter ++ // suspend mode automatically. ++ //HwSuspendModeEnable92Cu(Adapter, _FALSE); ++ ++HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_MISC31); ++ rtw_write8(Adapter, 0x15, 0xe9);//suggest by Johnny for lower temperature ++ //_dbg_dump_macreg(padapter); ++ ++ //misc ++ { ++ int i; ++ u8 mac_addr[6]; ++ for(i=0; i<6; i++) ++ { ++ mac_addr[i] = rtw_read8(Adapter, REG_MACID+i); ++ } ++ ++ DBG_8192C("MAC Address from REG_MACID = "MAC_FMT"\n", MAC_ARG(mac_addr)); ++ } ++ ++exit: ++HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_END); ++ ++ DBG_871X("%s in %dms\n", __FUNCTION__, rtw_get_passing_time_ms(init_start_time)); ++ ++ #ifdef DBG_HAL_INIT_PROFILING ++ hal_init_stages_timestamp[HAL_INIT_STAGES_END]=rtw_get_current_time(); ++ ++ for(hal_init_profiling_i=0;hal_init_profiling_irf_type == RF_2T2R) ++ PHY_SetBBReg(Adapter, rFPGA0_XAB_RFParameter, 0x380038, 1); ++ else ++ PHY_SetBBReg(Adapter, rFPGA0_XAB_RFParameter, 0x38, 1); ++ PHY_SetBBReg(Adapter, rOFDM0_TRxPathEnable, 0xf0, 1); ++ PHY_SetBBReg(Adapter, rFPGA0_RFMOD, BIT1, 0); ++ ++ //AFE ++ //DbgPrint("0x0e70 = %x\n", Adapter->PS_BBRegBackup[PSBBREG_AFE0]); ++ //PHY_SetBBReg(Adapter, 0x0e70, bMaskDWord ,Adapter->PS_BBRegBackup[PSBBREG_AFE0] ); ++ //PHY_SetBBReg(Adapter, 0x0e70, bMaskDWord ,0x631B25A0 ); ++ if (pHalData->rf_type == RF_2T2R) ++ PHY_SetBBReg(Adapter, rRx_Wait_CCA, bMaskDWord ,0x63DB25A0 ); ++ else if (pHalData->rf_type == RF_1T1R) ++ PHY_SetBBReg(Adapter, rRx_Wait_CCA, bMaskDWord ,0x631B25A0 ); ++ ++ // 4. issue 3-wire command that RF set to Rx idle mode. This is used to re-write the RX idle mode. ++ // We can only prvide a usual value instead and then HW will modify the value by itself. ++ PHY_SetRFReg(Adapter,RF90_PATH_A, 0, bRFRegOffsetMask,0x32D95); ++ if (pHalData->rf_type == RF_2T2R) ++ { ++ PHY_SetRFReg(Adapter,RF90_PATH_B, 0, bRFRegOffsetMask,0x32D95); ++ } ++ } ++ else // Level 2 or others. ++ { ++ //h. AFE_PLL_CTRL 0x28[7:0] = 0x80 //disable AFE PLL ++ PlatformEFIOWrite1Byte(Adapter, REG_AFE_PLL_CTRL, 0x81); ++ ++ // i. AFE_XTAL_CTRL 0x24[15:0] = 0x880F //gated AFE DIG_CLOCK ++ PlatformEFIOWrite2Byte(Adapter, REG_AFE_XTAL_CTRL, 0x800F); ++ delay_ms(1); ++ ++ // 1. Enable MAC Clock. Can not be enabled now. ++ //WriteXBYTE(REG_SYS_CLKR+1, ReadXBYTE(REG_SYS_CLKR+1) | BIT(3)); ++ ++ // 2. Force PWM, Enable SPS18_LDO_Marco_Block ++ PlatformEFIOWrite1Byte(Adapter, REG_SPS0_CTRL, ++ PlatformEFIORead1Byte(Adapter, REG_SPS0_CTRL) | (BIT0|BIT3)); ++ ++ // 3. restore BB, AFE control register. ++ //RF ++ if (pHalData->rf_type == RF_2T2R) ++ PHY_SetBBReg(Adapter, rFPGA0_XAB_RFParameter, 0x380038, 1); ++ else ++ PHY_SetBBReg(Adapter, rFPGA0_XAB_RFParameter, 0x38, 1); ++ PHY_SetBBReg(Adapter, rOFDM0_TRxPathEnable, 0xf0, 1); ++ PHY_SetBBReg(Adapter, rFPGA0_RFMOD, BIT1, 0); ++ ++ //AFE ++ if (pHalData->rf_type == RF_2T2R) ++ PHY_SetBBReg(Adapter, rRx_Wait_CCA, bMaskDWord ,0x63DB25A0 ); ++ else if (pHalData->rf_type == RF_1T1R) ++ PHY_SetBBReg(Adapter, rRx_Wait_CCA, bMaskDWord ,0x631B25A0 ); ++ ++ // 4. issue 3-wire command that RF set to Rx idle mode. This is used to re-write the RX idle mode. ++ // We can only prvide a usual value instead and then HW will modify the value by itself. ++ PHY_SetRFReg(Adapter,RF90_PATH_A, 0, bRFRegOffsetMask,0x32D95); ++ if (pHalData->rf_type == RF_2T2R) ++ { ++ PHY_SetRFReg(Adapter,RF90_PATH_B, 0, bRFRegOffsetMask,0x32D95); ++ } ++ ++ // 5. gated MAC Clock ++ //WriteXBYTE(REG_SYS_CLKR+1, ReadXBYTE(REG_SYS_CLKR+1) & ~(BIT(3))); ++ //PlatformEFIOWrite1Byte(Adapter, REG_SYS_CLKR+1, PlatformEFIORead1Byte(Adapter, REG_SYS_CLKR+1)|(BIT3)); ++ ++ { ++ //u1Byte eRFPath = RF90_PATH_A,value8 = 0, retry = 0; ++ u1Byte bytetmp; ++ //PHY_SetRFReg(Adapter, (RF90_RADIO_PATH_E)eRFPath, 0x0, bMaskByte0, 0x0); ++ // 2010/08/12 MH Add for B path under SS test. ++ //if (pHalData->RF_Type == RF_2T2R) ++ //PHY_SetRFReg(Adapter, RF90_PATH_B, 0x0, bMaskByte0, 0x0); ++ ++ bytetmp = PlatformEFIORead1Byte(Adapter, REG_APSD_CTRL); ++ PlatformEFIOWrite1Byte(Adapter, REG_APSD_CTRL, bytetmp & ~BIT6); ++ ++ delay_ms(10); ++ ++ // Set BB reset at first ++ PlatformEFIOWrite1Byte(Adapter, REG_SYS_FUNC_EN, 0x17 );//0x16 ++ ++ // Enable TX ++ PlatformEFIOWrite1Byte(Adapter, REG_TXPAUSE, 0x0); ++ } ++ //Adapter->HalFunc.InitializeAdapterHandler(Adapter, Adapter->MgntInfo.dot11CurrentChannelNumber); ++ //CardSelectiveSuspendLeave(Adapter); ++ } ++ ++ break; ++ ++ case rf_sleep: ++ case rf_off: ++ value8 = PlatformEFIORead1Byte(Adapter, REG_SPS0_CTRL) ; ++ if (IS_81xxC_VENDOR_UMC_B_CUT(pHalData->VersionID)) ++ value8 &= ~(BIT0); ++ else ++ value8 &= ~(BIT0|BIT3); ++ if (bRegSSPwrLvl == 1) ++ { ++ RT_TRACE(COMP_POWER, DBG_LOUD, ("SS LVL1\n")); ++ // Disable RF and BB only for SelectSuspend. ++ ++ // 1. Set BB/RF to shutdown. ++ // (1) Reg878[5:3]= 0 // RF rx_code for preamble power saving ++ // (2)Reg878[21:19]= 0 //Turn off RF-B ++ // (3) RegC04[7:4]= 0 // turn off all paths for packet detection ++ // (4) Reg800[1] = 1 // enable preamble power saving ++ Adapter->pwrctrlpriv.PS_BBRegBackup[PSBBREG_RF0] = PHY_QueryBBReg(Adapter, rFPGA0_XAB_RFParameter, bMaskDWord); ++ Adapter->pwrctrlpriv.PS_BBRegBackup[PSBBREG_RF1] = PHY_QueryBBReg(Adapter, rOFDM0_TRxPathEnable, bMaskDWord); ++ Adapter->pwrctrlpriv.PS_BBRegBackup[PSBBREG_RF2] = PHY_QueryBBReg(Adapter, rFPGA0_RFMOD, bMaskDWord); ++ if (pHalData->rf_type == RF_2T2R) ++ { ++ PHY_SetBBReg(Adapter, rFPGA0_XAB_RFParameter, 0x380038, 0); ++ } ++ else if (pHalData->rf_type == RF_1T1R) ++ { ++ PHY_SetBBReg(Adapter, rFPGA0_XAB_RFParameter, 0x38, 0); ++ } ++ PHY_SetBBReg(Adapter, rOFDM0_TRxPathEnable, 0xf0, 0); ++ PHY_SetBBReg(Adapter, rFPGA0_RFMOD, BIT1,1); ++ ++ // 2 .AFE control register to power down. bit[30:22] ++ Adapter->pwrctrlpriv.PS_BBRegBackup[PSBBREG_AFE0] = PHY_QueryBBReg(Adapter, rRx_Wait_CCA, bMaskDWord); ++ if (pHalData->rf_type == RF_2T2R) ++ PHY_SetBBReg(Adapter, rRx_Wait_CCA, bMaskDWord ,0x00DB25A0); ++ else if (pHalData->rf_type == RF_1T1R) ++ PHY_SetBBReg(Adapter, rRx_Wait_CCA, bMaskDWord ,0x001B25A0); ++ ++ // 3. issue 3-wire command that RF set to power down. ++ PHY_SetRFReg(Adapter,RF90_PATH_A, 0, bRFRegOffsetMask,0); ++ if (pHalData->rf_type == RF_2T2R) ++ { ++ PHY_SetRFReg(Adapter,RF90_PATH_B, 0, bRFRegOffsetMask,0); ++ } ++ ++ // 4. Force PFM , disable SPS18_LDO_Marco_Block ++ PlatformEFIOWrite1Byte(Adapter, REG_SPS0_CTRL, value8); ++ ++ // 5. gated MAC Clock ++ //WriteXBYTE(REG_SYS_CLKR+1, ReadXBYTE(REG_SYS_CLKR+1) & ~(BIT(3))); ++ } ++ else // Level 2 or others. ++ { ++ RT_TRACE(COMP_POWER, DBG_LOUD, ("SS LVL2\n")); ++ { ++ u1Byte eRFPath = RF90_PATH_A,value8 = 0; ++ PlatformEFIOWrite1Byte(Adapter, REG_TXPAUSE, 0xFF); ++ PHY_SetRFReg(Adapter, (RF90_RADIO_PATH_E)eRFPath, 0x0, bMaskByte0, 0x0); ++ // 2010/08/12 MH Add for B path under SS test. ++ //if (pHalData->RF_Type == RF_2T2R) ++ //PHY_SetRFReg(Adapter, RF90_PATH_B, 0x0, bMaskByte0, 0x0); ++ ++ value8 |= APSDOFF; ++ PlatformEFIOWrite1Byte(Adapter, REG_APSD_CTRL, value8);//0x40 ++ ++ // After switch APSD, we need to delay for stability ++ delay_ms(10); ++ ++ // Set BB reset at first ++ value8 = 0 ; ++ value8 |=( FEN_USBD | FEN_USBA | FEN_BB_GLB_RSTn); ++ PlatformEFIOWrite1Byte(Adapter, REG_SYS_FUNC_EN,value8 );//0x16 ++ } ++ ++ // Disable RF and BB only for SelectSuspend. ++ ++ // 1. Set BB/RF to shutdown. ++ // (1) Reg878[5:3]= 0 // RF rx_code for preamble power saving ++ // (2)Reg878[21:19]= 0 //Turn off RF-B ++ // (3) RegC04[7:4]= 0 // turn off all paths for packet detection ++ // (4) Reg800[1] = 1 // enable preamble power saving ++ Adapter->pwrctrlpriv.PS_BBRegBackup[PSBBREG_RF0] = PHY_QueryBBReg(Adapter, rFPGA0_XAB_RFParameter, bMaskDWord); ++ Adapter->pwrctrlpriv.PS_BBRegBackup[PSBBREG_RF1] = PHY_QueryBBReg(Adapter, rOFDM0_TRxPathEnable, bMaskDWord); ++ Adapter->pwrctrlpriv.PS_BBRegBackup[PSBBREG_RF2] = PHY_QueryBBReg(Adapter, rFPGA0_RFMOD, bMaskDWord); ++ if (pHalData->rf_type == RF_2T2R) ++ { ++ PHY_SetBBReg(Adapter, rFPGA0_XAB_RFParameter, 0x380038, 0); ++ } ++ else if (pHalData->rf_type == RF_1T1R) ++ { ++ PHY_SetBBReg(Adapter, rFPGA0_XAB_RFParameter, 0x38, 0); ++ } ++ PHY_SetBBReg(Adapter, rOFDM0_TRxPathEnable, 0xf0, 0); ++ PHY_SetBBReg(Adapter, rFPGA0_RFMOD, BIT1,1); ++ ++ // 2 .AFE control register to power down. bit[30:22] ++ Adapter->pwrctrlpriv.PS_BBRegBackup[PSBBREG_AFE0] = PHY_QueryBBReg(Adapter, rRx_Wait_CCA, bMaskDWord); ++ if (pHalData->rf_type == RF_2T2R) ++ PHY_SetBBReg(Adapter, rRx_Wait_CCA, bMaskDWord ,0x00DB25A0); ++ else if (pHalData->rf_type == RF_1T1R) ++ PHY_SetBBReg(Adapter, rRx_Wait_CCA, bMaskDWord ,0x001B25A0); ++ ++ // 3. issue 3-wire command that RF set to power down. ++ PHY_SetRFReg(Adapter,RF90_PATH_A, 0, bRFRegOffsetMask,0); ++ if (pHalData->rf_type == RF_2T2R) ++ { ++ PHY_SetRFReg(Adapter,RF90_PATH_B, 0, bRFRegOffsetMask,0); ++ } ++ ++ // 4. Force PFM , disable SPS18_LDO_Marco_Block ++ PlatformEFIOWrite1Byte(Adapter, REG_SPS0_CTRL, value8); ++ ++ // 2010/10/13 MH/Isaachsu exchange sequence. ++ //h. AFE_PLL_CTRL 0x28[7:0] = 0x80 //disable AFE PLL ++ PlatformEFIOWrite1Byte(Adapter, REG_AFE_PLL_CTRL, 0x80); ++ delay_ms(1); ++ ++ // i. AFE_XTAL_CTRL 0x24[15:0] = 0x880F //gated AFE DIG_CLOCK ++ PlatformEFIOWrite2Byte(Adapter, REG_AFE_XTAL_CTRL, 0xA80F); ++ ++ // 5. gated MAC Clock ++ //WriteXBYTE(REG_SYS_CLKR+1, ReadXBYTE(REG_SYS_CLKR+1) & ~(BIT(3))); ++ //PlatformEFIOWrite1Byte(Adapter, REG_SYS_CLKR+1, PlatformEFIORead1Byte(Adapter, REG_SYS_CLKR+1)& ~(BIT3)) ++ ++ //CardSelectiveSuspendEnter(Adapter); ++ } ++ ++ break; ++ ++ default: ++ break; ++ } ++ ++} // phy_PowerSwitch92CU ++ ++void _ps_open_RF(_adapter *padapter) { ++ //here call with bRegSSPwrLvl 1, bRegSSPwrLvl 2 needs to be verified ++ phy_SsPwrSwitch92CU(padapter, rf_on, 1); ++} ++ ++void _ps_close_RF(_adapter *padapter){ ++ //here call with bRegSSPwrLvl 1, bRegSSPwrLvl 2 needs to be verified ++ phy_SsPwrSwitch92CU(padapter, rf_off, 1); ++} ++#endif //SYNC_SD7_20110802_phy_SsPwrSwitch92CU ++ ++ ++ ++static VOID ++_DisableGPIO( ++ IN PADAPTER Adapter ++ ) ++{ ++/*************************************** ++j. GPIO_PIN_CTRL 0x44[31:0]=0x000 // ++k. Value = GPIO_PIN_CTRL[7:0] ++l. GPIO_PIN_CTRL 0x44[31:0] = 0x00FF0000 | (value <<8); //write external PIN level ++m. GPIO_MUXCFG 0x42 [15:0] = 0x0780 ++n. LEDCFG 0x4C[15:0] = 0x8080 ++***************************************/ ++ u8 value8; ++ u16 value16; ++ u32 value32; ++ ++ //1. Disable GPIO[7:0] ++ rtw_write16(Adapter, REG_GPIO_PIN_CTRL+2, 0x0000); ++ value32 = rtw_read32(Adapter, REG_GPIO_PIN_CTRL) & 0xFFFF00FF; ++ value8 = (u8) (value32&0x000000FF); ++ value32 |= ((value8<<8) | 0x00FF0000); ++ rtw_write32(Adapter, REG_GPIO_PIN_CTRL, value32); ++ ++ //2. Disable GPIO[10:8] ++ rtw_write8(Adapter, REG_GPIO_MUXCFG+3, 0x00); ++ value16 = rtw_read16(Adapter, REG_GPIO_MUXCFG+2) & 0xFF0F; ++ value8 = (u8) (value16&0x000F); ++ value16 |= ((value8<<4) | 0x0780); ++ rtw_write16(Adapter, REG_GPIO_MUXCFG+2, value16); ++ ++ //3. Disable LED0 & 1 ++ rtw_write16(Adapter, REG_LEDCFG0, 0x8080); ++ ++ //RT_TRACE(COMP_INIT, DBG_LOUD, ("======> Disable GPIO and LED.\n")); ++ ++} //end of _DisableGPIO() ++ ++static VOID ++_ResetFWDownloadRegister( ++ IN PADAPTER Adapter ++ ) ++{ ++ u8 value8; ++ ++ value8 = rtw_read8(Adapter, REG_MCUFWDL); ++ value8 &= ~(MCUFWDL_EN | MCUFWDL_RDY); ++ rtw_write8(Adapter, REG_MCUFWDL, value8); ++ //RT_TRACE(COMP_INIT, DBG_LOUD, ("Reset FW download register.\n")); ++} ++ ++ ++static int ++_DisableRF_AFE( ++ IN PADAPTER Adapter ++ ) ++{ ++ int rtStatus = _SUCCESS; ++ u32 pollingCount = 0; ++ u8 value8; ++ ++ //disable RF/ AFE AD/DA ++ value8 = APSDOFF; ++ rtw_write8(Adapter, REG_APSD_CTRL, value8); ++ ++ ++#if (RTL8192CU_ASIC_VERIFICATION) ++ ++ do ++ { ++ if(rtw_read8(Adapter, REG_APSD_CTRL) & APSDOFF_STATUS){ ++ //RT_TRACE(COMP_INIT, DBG_LOUD, ("Disable RF, AFE, AD, DA Done!\n")); ++ break; ++ } ++ ++ if(pollingCount++ > POLLING_READY_TIMEOUT_COUNT){ ++ //RT_TRACE(COMP_INIT, DBG_SERIOUS, ("Failed to polling APSDOFF_STATUS done!\n")); ++ return _FAIL; ++ } ++ ++ }while(_TRUE); ++ ++#endif ++ ++ //RT_TRACE(COMP_INIT, DBG_LOUD, ("Disable RF, AFE,AD, DA.\n")); ++ return rtStatus; ++ ++} ++ ++static VOID ++_ResetBB( ++ IN PADAPTER Adapter ++ ) ++{ ++ u16 value16; ++ ++ //reset BB ++ value16 = rtw_read16(Adapter, REG_SYS_FUNC_EN); ++ value16 &= ~(FEN_BBRSTB | FEN_BB_GLB_RSTn); ++ rtw_write16(Adapter, REG_SYS_FUNC_EN, value16); ++ //RT_TRACE(COMP_INIT, DBG_LOUD, ("Reset BB.\n")); ++} ++ ++static VOID ++_ResetMCU( ++ IN PADAPTER Adapter ++ ) ++{ ++ u16 value16; ++ ++ // reset MCU ++ value16 = rtw_read16(Adapter, REG_SYS_FUNC_EN); ++ value16 &= ~FEN_CPUEN; ++ rtw_write16(Adapter, REG_SYS_FUNC_EN, value16); ++ //RT_TRACE(COMP_INIT, DBG_LOUD, ("Reset MCU.\n")); ++} ++ ++static VOID ++_DisableMAC_AFE_PLL( ++ IN PADAPTER Adapter ++ ) ++{ ++ u32 value32; ++ ++ //disable MAC/ AFE PLL ++ value32 = rtw_read32(Adapter, REG_APS_FSMCO); ++ value32 |= APDM_MAC; ++ rtw_write32(Adapter, REG_APS_FSMCO, value32); ++ ++ value32 |= APFM_OFF; ++ rtw_write32(Adapter, REG_APS_FSMCO, value32); ++ //RT_TRACE(COMP_INIT, DBG_LOUD, ("Disable MAC, AFE PLL.\n")); ++} ++ ++static VOID ++_AutoPowerDownToHostOff( ++ IN PADAPTER Adapter ++ ) ++{ ++ u32 value32; ++ rtw_write8(Adapter, REG_SPS0_CTRL, 0x22); ++ ++ value32 = rtw_read32(Adapter, REG_APS_FSMCO); ++ ++ value32 |= APDM_HOST;//card disable ++ rtw_write32(Adapter, REG_APS_FSMCO, value32); ++ //RT_TRACE(COMP_INIT, DBG_LOUD, ("Auto Power Down to Host-off state.\n")); ++ ++ // set USB suspend ++ value32 = rtw_read32(Adapter, REG_APS_FSMCO); ++ value32 &= ~AFSM_PCIE; ++ rtw_write32(Adapter, REG_APS_FSMCO, value32); ++ ++} ++ ++static VOID ++_SetUsbSuspend( ++ IN PADAPTER Adapter ++ ) ++{ ++ u32 value32; ++ ++ value32 = rtw_read32(Adapter, REG_APS_FSMCO); ++ ++ // set USB suspend ++ value32 |= AFSM_HSUS; ++ rtw_write32(Adapter, REG_APS_FSMCO, value32); ++ ++ //RT_ASSERT(0 == (rtw_read32(Adapter, REG_APS_FSMCO) & BIT(12)),("")); ++ //RT_TRACE(COMP_INIT, DBG_LOUD, ("Set USB suspend.\n")); ++ ++} ++ ++static VOID ++_DisableRFAFEAndResetBB( ++ IN PADAPTER Adapter ++ ) ++{ ++/************************************** ++a. TXPAUSE 0x522[7:0] = 0xFF //Pause MAC TX queue ++b. RF path 0 offset 0x00 = 0x00 // disable RF ++c. APSD_CTRL 0x600[7:0] = 0x40 ++d. SYS_FUNC_EN 0x02[7:0] = 0x16 //reset BB state machine ++e. SYS_FUNC_EN 0x02[7:0] = 0x14 //reset BB state machine ++***************************************/ ++ u8 eRFPath = 0,value8 = 0; ++ rtw_write8(Adapter, REG_TXPAUSE, 0xFF); ++ PHY_SetRFReg(Adapter, (RF90_RADIO_PATH_E)eRFPath, 0x0, bMaskByte0, 0x0); ++ ++ value8 |= APSDOFF; ++ rtw_write8(Adapter, REG_APSD_CTRL, value8);//0x40 ++ ++ value8 = 0 ; ++ value8 |=( FEN_USBD | FEN_USBA | FEN_BB_GLB_RSTn); ++ rtw_write8(Adapter, REG_SYS_FUNC_EN,value8 );//0x16 ++ ++ value8 &=( ~FEN_BB_GLB_RSTn ); ++ rtw_write8(Adapter, REG_SYS_FUNC_EN, value8); //0x14 ++ ++ //RT_TRACE(COMP_INIT, DBG_LOUD, ("======> RF off and reset BB.\n")); ++} ++ ++static VOID ++_ResetDigitalProcedure1( ++ IN PADAPTER Adapter, ++ IN BOOLEAN bWithoutHWSM ++ ) ++{ ++ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ ++ if(pHalData->FirmwareVersion <= 0x20){ ++ #if 0 ++ /***************************** ++ f. SYS_FUNC_EN 0x03[7:0]=0x54 // reset MAC register, DCORE ++ g. MCUFWDL 0x80[7:0]=0 // reset MCU ready status ++ ******************************/ ++ u4Byte value32 = 0; ++ PlatformIOWrite1Byte(Adapter, REG_SYS_FUNC_EN+1, 0x54); ++ PlatformIOWrite1Byte(Adapter, REG_MCUFWDL, 0); ++ #else ++ /***************************** ++ f. MCUFWDL 0x80[7:0]=0 // reset MCU ready status ++ g. SYS_FUNC_EN 0x02[10]= 0 // reset MCU register, (8051 reset) ++ h. SYS_FUNC_EN 0x02[15-12]= 5 // reset MAC register, DCORE ++ i. SYS_FUNC_EN 0x02[10]= 1 // enable MCU register, (8051 enable) ++ ******************************/ ++ u16 valu16 = 0; ++ rtw_write8(Adapter, REG_MCUFWDL, 0); ++ ++ valu16 = rtw_read16(Adapter, REG_SYS_FUNC_EN); ++ rtw_write16(Adapter, REG_SYS_FUNC_EN, (valu16 & (~FEN_CPUEN)));//reset MCU ,8051 ++ ++ valu16 = rtw_read16(Adapter, REG_SYS_FUNC_EN)&0x0FFF; ++ rtw_write16(Adapter, REG_SYS_FUNC_EN, (valu16 |(FEN_HWPDN|FEN_ELDR)));//reset MAC ++ ++ #ifdef DBG_SHOW_MCUFWDL_BEFORE_51_ENABLE ++ { ++ u8 val; ++ if( (val=rtw_read8(Adapter, REG_MCUFWDL))) ++ DBG_871X("DBG_SHOW_MCUFWDL_BEFORE_51_ENABLE %s:%d REG_MCUFWDL:0x%02x\n", __FUNCTION__, __LINE__, val); ++ } ++ #endif ++ ++ ++ valu16 = rtw_read16(Adapter, REG_SYS_FUNC_EN); ++ rtw_write16(Adapter, REG_SYS_FUNC_EN, (valu16 | FEN_CPUEN));//enable MCU ,8051 ++ ++ ++ #endif ++ } ++ else{ ++ u8 retry_cnts = 0; ++ ++ if(rtw_read8(Adapter, REG_MCUFWDL) & BIT1) ++ { //IF fw in RAM code, do reset ++ ++ rtw_write8(Adapter, REG_MCUFWDL, 0); ++ if(Adapter->bFWReady){ ++ // 2010/08/25 MH Accordign to RD alfred's suggestion, we need to disable other ++ // HRCV INT to influence 8051 reset. ++ rtw_write8(Adapter, REG_FWIMR, 0x20); ++ ++ rtw_write8(Adapter, REG_HMETFR+3, 0x20);//8051 reset by self ++ ++ while( (retry_cnts++ <100) && (FEN_CPUEN &rtw_read16(Adapter, REG_SYS_FUNC_EN))) ++ { ++ rtw_udelay_os(50);//PlatformStallExecution(50);//us ++ } ++ ++ if(retry_cnts >= 100){ ++ DBG_8192C("%s #####=> 8051 reset failed!.........................\n", __FUNCTION__); ++ // if 8051 reset fail we trigger GPIO 0 for LA ++ //PlatformEFIOWrite4Byte( Adapter, ++ // REG_GPIO_PIN_CTRL, ++ // 0x00010100); ++ // 2010/08/31 MH According to Filen's info, if 8051 reset fail, reset MAC directly. ++ rtw_write8(Adapter, REG_SYS_FUNC_EN+1, 0x50); //Reset MAC and Enable 8051 ++ rtw_mdelay_os(10); ++ } ++ else { ++ //DBG_871X("%s =====> 8051 reset success (%d) .\n", __FUNCTION__, retry_cnts); ++ } ++ } ++ else { ++ DBG_871X("%s =====> 8051 in RAM but !Adapter->bFWReady\n", __FUNCTION__); ++ } ++ } ++ else{ ++ //DBG_871X("%s =====> 8051 in ROM.\n", __FUNCTION__); ++ } ++ ++ #ifdef DBG_SHOW_MCUFWDL_BEFORE_51_ENABLE ++ { ++ u8 val; ++ if( (val=rtw_read8(Adapter, REG_MCUFWDL))) ++ DBG_871X("DBG_SHOW_MCUFWDL_BEFORE_51_ENABLE %s:%d REG_MCUFWDL:0x%02x\n", __FUNCTION__, __LINE__, val); ++ } ++ #endif ++ ++ rtw_write8(Adapter, REG_SYS_FUNC_EN+1, 0x54); //Reset MAC and Enable 8051 ++ } ++ ++ // Clear rpwm value for initial toggle bit trigger. ++ rtw_write8(Adapter, REG_USB_HRPWM, 0x00); ++ ++ if(bWithoutHWSM){ ++ /***************************** ++ Without HW auto state machine ++ g. SYS_CLKR 0x08[15:0] = 0x30A3 //disable MAC clock ++ h. AFE_PLL_CTRL 0x28[7:0] = 0x80 //disable AFE PLL ++ i. AFE_XTAL_CTRL 0x24[15:0] = 0x880F //gated AFE DIG_CLOCK ++ j. SYS_ISO_CTRL 0x00[7:0] = 0xF9 // isolated digital to PON ++ ******************************/ ++ //rtw_write16(Adapter, REG_SYS_CLKR, 0x30A3); ++ rtw_write16(Adapter, REG_SYS_CLKR, 0x70A3);//modify to 0x70A3 by Scott. ++ rtw_write8(Adapter, REG_AFE_PLL_CTRL, 0x80); ++ rtw_write16(Adapter, REG_AFE_XTAL_CTRL, 0x880F); ++ rtw_write8(Adapter, REG_SYS_ISO_CTRL, 0xF9); ++ } ++ else ++ { ++ // Disable all RF/BB power ++ rtw_write8(Adapter, REG_RF_CTRL, 0x00); ++ } ++ //RT_TRACE(COMP_INIT, DBG_LOUD, ("======> Reset Digital.\n")); ++ ++} ++ ++static VOID ++_ResetDigitalProcedure2( ++ IN PADAPTER Adapter ++) ++{ ++/***************************** ++k. SYS_FUNC_EN 0x03[7:0] = 0x44 // disable ELDR runction ++l. SYS_CLKR 0x08[15:0] = 0x3083 // disable ELDR clock ++m. SYS_ISO_CTRL 0x01[7:0] = 0x83 // isolated ELDR to PON ++******************************/ ++ //rtw_write8(Adapter, REG_SYS_FUNC_EN+1, 0x44);//marked by Scott. ++ //rtw_write16(Adapter, REG_SYS_CLKR, 0x3083); ++ //rtw_write8(Adapter, REG_SYS_ISO_CTRL+1, 0x83); ++ ++ rtw_write16(Adapter, REG_SYS_CLKR, 0x70a3); //modify to 0x70a3 by Scott. ++ rtw_write8(Adapter, REG_SYS_ISO_CTRL+1, 0x82); //modify to 0x82 by Scott. ++} ++ ++static VOID ++_DisableAnalog( ++ IN PADAPTER Adapter, ++ IN BOOLEAN bWithoutHWSM ++ ) ++{ ++ u16 value16 = 0; ++ u8 value8=0; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ ++ if(bWithoutHWSM){ ++ /***************************** ++ n. LDOA15_CTRL 0x20[7:0] = 0x04 // disable A15 power ++ o. LDOV12D_CTRL 0x21[7:0] = 0x54 // disable digital core power ++ r. When driver call disable, the ASIC will turn off remaining clock automatically ++ ******************************/ ++ ++ rtw_write8(Adapter, REG_LDOA15_CTRL, 0x04); ++ //PlatformIOWrite1Byte(Adapter, REG_LDOV12D_CTRL, 0x54); ++ ++ value8 = rtw_read8(Adapter, REG_LDOV12D_CTRL); ++ value8 &= (~LDV12_EN); ++ rtw_write8(Adapter, REG_LDOV12D_CTRL, value8); ++ //RT_TRACE(COMP_INIT, DBG_LOUD, (" REG_LDOV12D_CTRL Reg0x21:0x%02x.\n",value8)); ++ } ++ ++/***************************** ++h. SPS0_CTRL 0x11[7:0] = 0x23 //enter PFM mode ++i. APS_FSMCO 0x04[15:0] = 0x4802 // set USB suspend ++******************************/ ++ ++ ++ value8 = 0x23; ++ if (IS_81xxC_VENDOR_UMC_B_CUT(pHalData->VersionID)) ++ value8 |= BIT3; ++ ++ rtw_write8(Adapter, REG_SPS0_CTRL, value8); ++ ++ ++ if(bWithoutHWSM) ++ { ++ //value16 |= (APDM_HOST | /*AFSM_HSUS |*/PFM_ALDN); ++ // 2010/08/31 According to Filen description, we need to use HW to shut down 8051 automatically. ++ // Becasue suspend operatione need the asistance of 8051 to wait for 3ms. ++ value16 |= (APDM_HOST | AFSM_HSUS |PFM_ALDN); ++ } ++ else ++ { ++ value16 |= (APDM_HOST | AFSM_HSUS |PFM_ALDN); ++ } ++ ++ rtw_write16(Adapter, REG_APS_FSMCO,value16 );//0x4802 ++ ++ rtw_write8(Adapter, REG_RSV_CTRL, 0x0e); ++ ++ #if 0 ++ //tynli_test for suspend mode. ++ if(!bWithoutHWSM){ ++ rtw_write8(Adapter, 0xfe10, 0x19); ++ } ++#endif ++ ++ //RT_TRACE(COMP_INIT, DBG_LOUD, ("======> Disable Analog Reg0x04:0x%04x.\n",value16)); ++} ++ ++static int ++CardDisableHWSM( // HW Auto state machine ++ IN PADAPTER Adapter, ++ IN BOOLEAN resetMCU ++ ) ++{ ++ int rtStatus = _SUCCESS; ++ if(Adapter->bSurpriseRemoved){ ++ return rtStatus; ++ } ++#if 1 ++ //==== RF Off Sequence ==== ++ _DisableRFAFEAndResetBB(Adapter); ++ ++ // ==== Reset digital sequence ====== ++ _ResetDigitalProcedure1(Adapter, _FALSE); ++ ++ // ==== Pull GPIO PIN to balance level and LED control ====== ++ _DisableGPIO(Adapter); ++ ++ // ==== Disable analog sequence === ++ _DisableAnalog(Adapter, _FALSE); ++ ++ RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("======> Card disable finished.\n")); ++#else ++ _DisableGPIO(Adapter); ++ ++ //reset FW download register ++ _ResetFWDownloadRegister(Adapter); ++ ++ ++ //disable RF/ AFE AD/DA ++ rtStatus = _DisableRF_AFE(Adapter); ++ if(RT_STATUS_SUCCESS != rtStatus){ ++ RT_TRACE(COMP_INIT, DBG_SERIOUS, ("_DisableRF_AFE failed!\n")); ++ goto Exit; ++ } ++ _ResetBB(Adapter); ++ ++ if(resetMCU){ ++ _ResetMCU(Adapter); ++ } ++ ++ _AutoPowerDownToHostOff(Adapter); ++ //_DisableMAC_AFE_PLL(Adapter); ++ ++ _SetUsbSuspend(Adapter); ++Exit: ++#endif ++ return rtStatus; ++ ++} ++ ++static int ++CardDisableWithoutHWSM( // without HW Auto state machine ++ IN PADAPTER Adapter ++ ) ++{ ++ int rtStatus = _SUCCESS; ++ ++ if(Adapter->bSurpriseRemoved){ ++ return rtStatus; ++ } ++ //RT_TRACE(COMP_INIT, DBG_LOUD, ("======> Card Disable Without HWSM .\n")); ++ //==== RF Off Sequence ==== ++ _DisableRFAFEAndResetBB(Adapter); ++ ++ // ==== Reset digital sequence ====== ++ _ResetDigitalProcedure1(Adapter, _TRUE); ++ ++ // ==== Pull GPIO PIN to balance level and LED control ====== ++ _DisableGPIO(Adapter); ++ ++ // ==== Reset digital sequence ====== ++ _ResetDigitalProcedure2(Adapter); ++ ++ // ==== Disable analog sequence === ++ _DisableAnalog(Adapter, _TRUE); ++ //RT_TRACE(COMP_INIT, DBG_LOUD, ("<====== Card Disable Without HWSM .\n")); ++ return rtStatus; ++} ++ ++static void rtl8192cu_hw_power_down(_adapter *padapter) ++{ ++ // 2010/-8/09 MH For power down module, we need to enable register block contrl reg at 0x1c. ++ // Then enable power down control bit of register 0x04 BIT4 and BIT15 as 1. ++ ++ // Enable register area 0x0-0xc. ++ rtw_write8(padapter,REG_RSV_CTRL, 0x0); ++ rtw_write16(padapter, REG_APS_FSMCO, 0x8812); ++} ++ ++u32 rtl8192cu_hal_deinit(PADAPTER Adapter) ++ { ++ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ DBG_8192C("==> %s \n",__FUNCTION__); ++ // 2011/02/18 To Fix RU LNA power leakage problem. We need to execute below below in ++ // Adapter init and halt sequence. Accordingto EEchou's opinion, we can enable the ability for all ++ // IC. Accord to johnny's opinion, only RU need the support. ++ if (IS_HARDWARE_TYPE_8192C(Adapter) && (pHalData->BoardType == BOARD_USB_High_PA)) ++ rtw_write32(Adapter, rFPGA0_XCD_RFParameter, rtw_read32(Adapter, rFPGA0_XCD_RFParameter)|BIT1); ++ ++ #ifdef SUPPORT_HW_RFOFF_DETECTED ++ DBG_8192C("bkeepfwalive(%x)\n",Adapter->pwrctrlpriv.bkeepfwalive); ++ if(Adapter->pwrctrlpriv.bkeepfwalive) ++ { ++ _ps_close_RF(Adapter); ++ if((Adapter->pwrctrlpriv.bHWPwrPindetect) && (Adapter->pwrctrlpriv.bHWPowerdown)) ++ rtl8192cu_hw_power_down(Adapter); ++ } ++ else ++#endif ++ { ++ if( Adapter->bCardDisableWOHSM == _FALSE) ++ { ++ DBG_8192C("card disble HWSM...........\n"); ++ CardDisableHWSM(Adapter, _FALSE); ++ } ++ else ++ { ++ DBG_8192C("card disble without HWSM...........\n"); ++ CardDisableWithoutHWSM(Adapter); // without HW Auto state machine ++ ++ if((Adapter->pwrctrlpriv.bHWPwrPindetect ) && (Adapter->pwrctrlpriv.bHWPowerdown)) ++ rtl8192cu_hw_power_down(Adapter); ++ } ++ } ++ ++ return _SUCCESS; ++ } ++ ++ ++unsigned int rtl8192cu_inirp_init(PADAPTER Adapter) ++{ ++ u8 i; ++ struct recv_buf *precvbuf; ++ uint status; ++ struct dvobj_priv *pdev=&Adapter->dvobjpriv; ++ struct intf_hdl * pintfhdl=&Adapter->iopriv.intf; ++ struct recv_priv *precvpriv = &(Adapter->recvpriv); ++ u32 (*_read_port)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem); ++#ifdef CONFIG_USB_INTERRUPT_IN_PIPE ++ u32 (*_read_interrupt)(struct intf_hdl *pintfhdl, u32 addr); ++#endif ++ ++_func_enter_; ++ ++ _read_port = pintfhdl->io_ops._read_port; ++ ++ status = _SUCCESS; ++ ++ RT_TRACE(_module_hci_hal_init_c_,_drv_info_,("===> usb_inirp_init \n")); ++ ++ precvpriv->ff_hwaddr = RECV_BULK_IN_ADDR; ++ ++ //issue Rx irp to receive data ++ precvbuf = (struct recv_buf *)precvpriv->precv_buf; ++ for(i=0; iff_hwaddr, 0, (unsigned char *)precvbuf) == _FALSE ) ++ { ++ RT_TRACE(_module_hci_hal_init_c_,_drv_err_,("usb_rx_init: usb_read_port error \n")); ++ status = _FAIL; ++ goto exit; ++ } ++ ++ precvbuf++; ++ precvpriv->free_recv_buf_queue_cnt--; ++ } ++ ++#ifdef CONFIG_USB_INTERRUPT_IN_PIPE ++ _read_interrupt = pintfhdl->io_ops._read_interrupt; ++ if(_read_interrupt(pintfhdl, RECV_INT_IN_ADDR) == _FALSE ) ++ { ++ RT_TRACE(_module_hci_hal_init_c_,_drv_err_,("usb_rx_init: usb_read_interrupt error \n")); ++ status = _FAIL; ++ } ++#endif ++ ++exit: ++ ++ RT_TRACE(_module_hci_hal_init_c_,_drv_info_,("<=== usb_inirp_init \n")); ++ ++_func_exit_; ++ ++ return status; ++ ++} ++ ++unsigned int rtl8192cu_inirp_deinit(PADAPTER Adapter) ++{ ++ RT_TRACE(_module_hci_hal_init_c_,_drv_info_,("\n ===> usb_rx_deinit \n")); ++ ++ rtw_read_port_cancel(Adapter); ++ ++ RT_TRACE(_module_hci_hal_init_c_,_drv_info_,("\n <=== usb_rx_deinit \n")); ++ ++ return _SUCCESS; ++} ++ ++//------------------------------------------------------------------------- ++// ++// Channel Plan ++// ++//------------------------------------------------------------------------- ++ ++static VOID ++ReadChannelPlan( ++ IN PADAPTER Adapter, ++ IN u8* PROMContent, ++ IN BOOLEAN AutoLoadFail ++ ) ++{ ++ ++#define EEPROM_TEST_CHANNEL_PLAN (0x7D) ++#define EEPROM_NORMAL_CHANNEL_PLAN (0x75) ++ ++ struct mlme_priv *pmlmepriv = &(Adapter->mlmepriv); ++ struct registry_priv *pregistrypriv = &Adapter->registrypriv; ++ u8 channelPlan; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ ++ if(AutoLoadFail){ ++ channelPlan = CHPL_FCC; ++ } ++ else{ ++ if(IS_NORMAL_CHIP(pHalData->VersionID)) ++ channelPlan = PROMContent[EEPROM_NORMAL_CHANNEL_PLAN]; ++ else ++ channelPlan = PROMContent[EEPROM_TEST_CHANNEL_PLAN]; ++ } ++ ++ if((pregistrypriv->channel_plan>= RT_CHANNEL_DOMAIN_MAX) || (channelPlan & EEPROM_CHANNEL_PLAN_BY_HW_MASK)) ++ { ++ pmlmepriv->ChannelPlan = _HalMapChannelPlan8192C(Adapter, (channelPlan & (~(EEPROM_CHANNEL_PLAN_BY_HW_MASK)))); ++ //pMgntInfo->bChnlPlanFromHW = (channelPlan & EEPROM_CHANNEL_PLAN_BY_HW_MASK) ? _TRUE : _FALSE; // User cannot change channel plan. ++ } ++ else ++ { ++ pmlmepriv->ChannelPlan = (RT_CHANNEL_DOMAIN)pregistrypriv->channel_plan; ++ } ++ ++#if 0 //todo: ++ switch(pMgntInfo->ChannelPlan) ++ { ++ case RT_CHANNEL_DOMAIN_GLOBAL_DOAMIN: ++ { ++ PRT_DOT11D_INFO pDot11dInfo = GET_DOT11D_INFO(pMgntInfo); ++ ++ pDot11dInfo->bEnabled = _TRUE; ++ } ++ //RT_TRACE(COMP_INIT, DBG_LOUD, ("Enable dot11d when RT_CHANNEL_DOMAIN_GLOBAL_DOAMIN!\n")); ++ break; ++ } ++#endif ++ ++ //RT_TRACE(COMP_INIT, DBG_LOUD, ("RegChannelPlan(%d) EEPROMChannelPlan(%ld)", pMgntInfo->RegChannelPlan, (u4Byte)channelPlan)); ++ //RT_TRACE(COMP_INIT, DBG_LOUD, ("ChannelPlan = %d\n" , pMgntInfo->ChannelPlan)); ++ ++ MSG_8192C("RT_ChannelPlan: 0x%02x\n", pmlmepriv->ChannelPlan); ++ ++} ++ ++ ++//------------------------------------------------------------------------- ++// ++// EEPROM Power index mapping ++// ++//------------------------------------------------------------------------- ++ ++ static VOID ++_ReadPowerValueFromPROM( ++ IN PTxPowerInfo pwrInfo, ++ IN u8* PROMContent, ++ IN BOOLEAN AutoLoadFail ++ ) ++{ ++ u32 rfPath, eeAddr, group; ++ ++ _rtw_memset(pwrInfo, 0, sizeof(TxPowerInfo)); ++ ++ if(AutoLoadFail){ ++ for(group = 0 ; group < CHANNEL_GROUP_MAX ; group++){ ++ for(rfPath = 0 ; rfPath < RF90_PATH_MAX ; rfPath++){ ++ pwrInfo->CCKIndex[rfPath][group] = EEPROM_Default_TxPowerLevel; ++ pwrInfo->HT40_1SIndex[rfPath][group] = EEPROM_Default_TxPowerLevel; ++ pwrInfo->HT40_2SIndexDiff[rfPath][group]= EEPROM_Default_HT40_2SDiff; ++ pwrInfo->HT20IndexDiff[rfPath][group] = EEPROM_Default_HT20_Diff; ++ pwrInfo->OFDMIndexDiff[rfPath][group] = EEPROM_Default_LegacyHTTxPowerDiff; ++ pwrInfo->HT40MaxOffset[rfPath][group] = EEPROM_Default_HT40_PwrMaxOffset; ++ pwrInfo->HT20MaxOffset[rfPath][group] = EEPROM_Default_HT20_PwrMaxOffset; ++ } ++ } ++ ++ pwrInfo->TSSI_A = EEPROM_Default_TSSI; ++ pwrInfo->TSSI_B = EEPROM_Default_TSSI; ++ ++ return; ++ } ++ ++ for(rfPath = 0 ; rfPath < RF90_PATH_MAX ; rfPath++){ ++ for(group = 0 ; group < CHANNEL_GROUP_MAX ; group++){ ++ eeAddr = EEPROM_CCK_TX_PWR_INX + (rfPath * 3) + group; ++ pwrInfo->CCKIndex[rfPath][group] = PROMContent[eeAddr]; ++ ++ eeAddr = EEPROM_HT40_1S_TX_PWR_INX + (rfPath * 3) + group; ++ pwrInfo->HT40_1SIndex[rfPath][group] = PROMContent[eeAddr]; ++ } ++ } ++ ++ for(group = 0 ; group < CHANNEL_GROUP_MAX ; group++){ ++ for(rfPath = 0 ; rfPath < RF90_PATH_MAX ; rfPath++){ ++ pwrInfo->HT40_2SIndexDiff[rfPath][group] = ++ (PROMContent[EEPROM_HT40_2S_TX_PWR_INX_DIFF + group] >> (rfPath * 4)) & 0xF; ++ ++#if 1 ++ pwrInfo->HT20IndexDiff[rfPath][group] = ++ (PROMContent[EEPROM_HT20_TX_PWR_INX_DIFF + group] >> (rfPath * 4)) & 0xF; ++ if(pwrInfo->HT20IndexDiff[rfPath][group] & BIT3) //4bit sign number to 8 bit sign number ++ pwrInfo->HT20IndexDiff[rfPath][group] |= 0xF0; ++#else ++ pwrInfo->HT20IndexDiff[rfPath][group] = ++ (PROMContent[EEPROM_HT20_TX_PWR_INX_DIFF + group] >> (rfPath * 4)) & 0xF; ++#endif ++ ++ pwrInfo->OFDMIndexDiff[rfPath][group] = ++ (PROMContent[EEPROM_OFDM_TX_PWR_INX_DIFF+ group] >> (rfPath * 4)) & 0xF; ++ ++ pwrInfo->HT40MaxOffset[rfPath][group] = ++ (PROMContent[EEPROM_HT40_MAX_PWR_OFFSET+ group] >> (rfPath * 4)) & 0xF; ++ ++ pwrInfo->HT20MaxOffset[rfPath][group] = ++ (PROMContent[EEPROM_HT20_MAX_PWR_OFFSET+ group] >> (rfPath * 4)) & 0xF; ++ } ++ } ++ ++ pwrInfo->TSSI_A = PROMContent[EEPROM_TSSI_A]; ++ pwrInfo->TSSI_B = PROMContent[EEPROM_TSSI_B]; ++ ++} ++ ++ ++static u32 ++_GetChannelGroup( ++ IN u32 channel ++ ) ++{ ++ //RT_ASSERT((channel < 14), ("Channel %d no is supported!\n")); ++ ++ if(channel < 3){ // Channel 1~3 ++ return 0; ++ } ++ else if(channel < 9){ // Channel 4~9 ++ return 1; ++ } ++ ++ return 2; // Channel 10~14 ++} ++ ++ ++static VOID ++ReadTxPowerInfo( ++ IN PADAPTER Adapter, ++ IN u8* PROMContent, ++ IN BOOLEAN AutoLoadFail ++ ) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ TxPowerInfo pwrInfo; ++ u32 rfPath, ch, group; ++ u8 pwr, diff; ++ ++ _ReadPowerValueFromPROM(&pwrInfo, PROMContent, AutoLoadFail); ++ ++ if(!AutoLoadFail) ++ pHalData->bTXPowerDataReadFromEEPORM = _TRUE; ++ ++ for(rfPath = 0 ; rfPath < RF90_PATH_MAX ; rfPath++){ ++ for(ch = 0 ; ch < CHANNEL_MAX_NUMBER ; ch++){ ++ group = _GetChannelGroup(ch); ++ ++ pHalData->TxPwrLevelCck[rfPath][ch] = pwrInfo.CCKIndex[rfPath][group]; ++ pHalData->TxPwrLevelHT40_1S[rfPath][ch] = pwrInfo.HT40_1SIndex[rfPath][group]; ++ ++ pHalData->TxPwrHt20Diff[rfPath][ch] = pwrInfo.HT20IndexDiff[rfPath][group]; ++ pHalData->TxPwrLegacyHtDiff[rfPath][ch] = pwrInfo.OFDMIndexDiff[rfPath][group]; ++ pHalData->PwrGroupHT20[rfPath][ch] = pwrInfo.HT20MaxOffset[rfPath][group]; ++ pHalData->PwrGroupHT40[rfPath][ch] = pwrInfo.HT40MaxOffset[rfPath][group]; ++ ++ pwr = pwrInfo.HT40_1SIndex[rfPath][group]; ++ diff = pwrInfo.HT40_2SIndexDiff[rfPath][group]; ++ ++ pHalData->TxPwrLevelHT40_2S[rfPath][ch] = (pwr > diff) ? (pwr - diff) : 0; ++ } ++ } ++ ++#if DBG ++ ++ for(rfPath = 0 ; rfPath < RF90_PATH_MAX ; rfPath++){ ++ for(ch = 0 ; ch < CHANNEL_MAX_NUMBER ; ch++){ ++ RTPRINT(FINIT, INIT_TxPower, ++ ("RF(%d)-Ch(%d) [CCK / HT40_1S / HT40_2S] = [0x%x / 0x%x / 0x%x]\n", ++ rfPath, ch, pHalData->TxPwrLevelCck[rfPath][ch], ++ pHalData->TxPwrLevelHT40_1S[rfPath][ch], ++ pHalData->TxPwrLevelHT40_2S[rfPath][ch])); ++ ++ } ++ } ++ ++ for(ch = 0 ; ch < CHANNEL_MAX_NUMBER ; ch++){ ++ RTPRINT(FINIT, INIT_TxPower, ("RF-A Ht20 to HT40 Diff[%d] = 0x%x\n", ch, pHalData->TxPwrHt20Diff[RF90_PATH_A][ch])); ++ } ++ ++ for(ch = 0 ; ch < CHANNEL_MAX_NUMBER ; ch++){ ++ RTPRINT(FINIT, INIT_TxPower, ("RF-A Legacy to Ht40 Diff[%d] = 0x%x\n", ch, pHalData->TxPwrLegacyHtDiff[RF90_PATH_A][ch])); ++ } ++ ++ for(ch = 0 ; ch < CHANNEL_MAX_NUMBER ; ch++){ ++ RTPRINT(FINIT, INIT_TxPower, ("RF-B Ht20 to HT40 Diff[%d] = 0x%x\n", ch, pHalData->TxPwrHt20Diff[RF90_PATH_B][ch])); ++ } ++ ++ for(ch = 0 ; ch < CHANNEL_MAX_NUMBER ; ch++){ ++ RTPRINT(FINIT, INIT_TxPower, ("RF-B Legacy to HT40 Diff[%d] = 0x%x\n", ch, pHalData->TxPwrLegacyHtDiff[RF90_PATH_B][ch])); ++ } ++ ++#endif ++ // 2010/10/19 MH Add Regulator recognize for CU. ++ if(!AutoLoadFail) ++ { ++ pHalData->EEPROMRegulatory = (PROMContent[RF_OPTION1]&0x7); //bit0~2 ++ } ++ else ++ { ++ pHalData->EEPROMRegulatory = 0; ++ } ++ DBG_8192C("EEPROMRegulatory = 0x%x\n", pHalData->EEPROMRegulatory); ++ ++} ++ ++ ++//------------------------------------------------------------------- ++// ++// EEPROM/EFUSE Content Parsing ++// ++//------------------------------------------------------------------- ++static void ++_ReadIDs( ++ IN PADAPTER Adapter, ++ IN u8* PROMContent, ++ IN BOOLEAN AutoloadFail ++ ) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ ++ if(_FALSE == AutoloadFail){ ++ // VID, PID ++ pHalData->EEPROMVID = le16_to_cpu( *(u16 *)&PROMContent[EEPROM_VID]); ++ pHalData->EEPROMPID = le16_to_cpu( *(u16 *)&PROMContent[EEPROM_PID]); ++ ++ // Customer ID, 0x00 and 0xff are reserved for Realtek. ++ pHalData->EEPROMCustomerID = *(u8 *)&PROMContent[EEPROM_CUSTOMER_ID]; ++ pHalData->EEPROMSubCustomerID = *(u8 *)&PROMContent[EEPROM_SUBCUSTOMER_ID]; ++ ++ } ++ else{ ++ pHalData->EEPROMVID = EEPROM_Default_VID; ++ pHalData->EEPROMPID = EEPROM_Default_PID; ++ ++ // Customer ID, 0x00 and 0xff are reserved for Realtek. ++ pHalData->EEPROMCustomerID = EEPROM_Default_CustomerID; ++ pHalData->EEPROMSubCustomerID = EEPROM_Default_SubCustomerID; ++ ++ } ++ ++ // For customized behavior. ++ if((pHalData->EEPROMVID == 0x103C) && (pHalData->EEPROMVID == 0x1629))// HP Lite-On for RTL8188CUS Slim Combo. ++ pHalData->CustomerID = RT_CID_819x_HP; ++ ++ // Decide CustomerID according to VID/DID or EEPROM ++ switch(pHalData->EEPROMCustomerID) ++ { ++ case EEPROM_CID_DEFAULT: ++ if((pHalData->EEPROMVID == 0x2001) && (pHalData->EEPROMPID == 0x3308)) ++ pHalData->CustomerID = RT_CID_DLINK; ++ else if((pHalData->EEPROMVID == 0x2001) && (pHalData->EEPROMPID == 0x3309)) ++ pHalData->CustomerID = RT_CID_DLINK; ++ else if((pHalData->EEPROMVID == 0x2001) && (pHalData->EEPROMPID == 0x330a)) ++ pHalData->CustomerID = RT_CID_DLINK; ++ break; ++ case EEPROM_CID_WHQL: ++/* ++ Adapter->bInHctTest = TRUE; ++ ++ pMgntInfo->bSupportTurboMode = FALSE; ++ pMgntInfo->bAutoTurboBy8186 = FALSE; ++ ++ pMgntInfo->PowerSaveControl.bInactivePs = FALSE; ++ pMgntInfo->PowerSaveControl.bIPSModeBackup = FALSE; ++ pMgntInfo->PowerSaveControl.bLeisurePs = FALSE; ++ ++ pMgntInfo->keepAliveLevel = 0; ++ ++ Adapter->bUnloadDriverwhenS3S4 = FALSE; ++*/ ++ break; ++ default: ++ pHalData->CustomerID = RT_CID_DEFAULT; ++ break; ++ ++ } ++ ++ MSG_8192C("EEPROMVID = 0x%04x\n", pHalData->EEPROMVID); ++ MSG_8192C("EEPROMPID = 0x%04x\n", pHalData->EEPROMPID); ++ MSG_8192C("EEPROMCustomerID : 0x%02x\n", pHalData->EEPROMCustomerID); ++ MSG_8192C("EEPROMSubCustomerID: 0x%02x\n", pHalData->EEPROMSubCustomerID); ++ ++ MSG_8192C("RT_CustomerID: 0x%02x\n", pHalData->CustomerID); ++ ++} ++ ++ ++static VOID ++_ReadMACAddress( ++ IN PADAPTER Adapter, ++ IN u8* PROMContent, ++ IN BOOLEAN AutoloadFail ++ ) ++{ ++ EEPROM_EFUSE_PRIV *pEEPROM = GET_EEPROM_EFUSE_PRIV(Adapter); ++ ++ if(_FALSE == AutoloadFail){ ++ //Read Permanent MAC address and set value to hardware ++ _rtw_memcpy(pEEPROM->mac_addr, &PROMContent[EEPROM_MAC_ADDR], ETH_ALEN); ++ } ++ else{ ++ //Random assigh MAC address ++ u8 sMacAddr[MAC_ADDR_LEN] = {0x00, 0xE0, 0x4C, 0x81, 0x92, 0x00}; ++ //sMacAddr[5] = (u8)GetRandomNumber(1, 254); ++ _rtw_memcpy(pEEPROM->mac_addr, sMacAddr, ETH_ALEN); ++ } ++ DBG_8192C("%s MAC Address from EFUSE = "MAC_FMT"\n",__FUNCTION__, MAC_ARG(pEEPROM->mac_addr)); ++ //NicIFSetMacAddress(Adapter, Adapter->PermanentAddress); ++ //RT_PRINT_ADDR(COMP_INIT|COMP_EFUSE, DBG_LOUD, "MAC Addr: %s", Adapter->PermanentAddress); ++ ++} ++ ++static VOID ++_ReadBoardType( ++ IN PADAPTER Adapter, ++ IN u8* PROMContent, ++ IN BOOLEAN AutoloadFail ++ ) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ BOOLEAN isNormal = IS_NORMAL_CHIP(pHalData->VersionID); ++ u32 value32; ++ u8 boardType = BOARD_USB_DONGLE; ++#if 0 ++ if(isNormal) ++ { ++ value32 = rtw_read32(Adapter, REG_HPON_FSM); ++ ++ DBG_8192C("first value 0x%x BoardType after 0x%x \n", CHIP_BONDING_IDENTIFIER(value32), pHalData->BoardType); ++ ++ if(!IS_92C_SERIAL(pHalData->VersionID)) ++ { ++ if(CHIP_BONDING_IDENTIFIER(value32) == CHIP_BONDING_88C_USB_MCARD) ++ { ++ pHalData->BoardType = BOARD_MINICARD; ++ DBG_8192C("value 0x%x BoardType after 0x%x \n", CHIP_BONDING_IDENTIFIER(value32), pHalData->BoardType); ++ } ++ else if(CHIP_BONDING_IDENTIFIER(value32) == CHIP_BONDING_88C_USB_HP) ++ { ++ pHalData->BoardType = BOARD_USB_High_PA; ++ DBG_8192C("value 0x%x BoardType after 0x%x \n", CHIP_BONDING_IDENTIFIER(value32), pHalData->BoardType); ++ } ++ } ++ } ++#endif ++ ++ if(AutoloadFail){ ++ if(IS_8723_SERIES(pHalData->VersionID)) ++ pHalData->rf_type = RF_1T1R; ++ else ++ pHalData->rf_type = RF_2T2R; ++ ++ pHalData->BluetoothCoexist = _FALSE; ++ pHalData->BoardType = boardType; ++ return; ++ } ++ ++ if(isNormal) ++ { ++ boardType = PROMContent[EEPROM_NORMAL_BoardType]; ++ boardType &= BOARD_TYPE_NORMAL_MASK;//bit[7:5] ++ boardType >>= 5; ++ } ++ else ++ { ++ boardType = PROMContent[EEPROM_RF_OPT4]; ++ boardType &= BOARD_TYPE_TEST_MASK; ++ } ++ ++ pHalData->BoardType = boardType; ++ MSG_8192C("_ReadBoardType(%x)\n",pHalData->BoardType); ++ ++ if (boardType == BOARD_USB_High_PA) ++ pHalData->ExternalPA = 1; ++} ++ ++ ++static VOID ++_ReadLEDSetting( ++ IN PADAPTER Adapter, ++ IN u8* PROMContent, ++ IN BOOLEAN AutoloadFail ++ ) ++{ ++ struct led_priv *pledpriv = &(Adapter->ledpriv); ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++#ifdef CONFIG_SW_LED ++ pledpriv->bRegUseLed = _TRUE; ++ ++ // ++ // Led mode ++ // ++ switch(pHalData->CustomerID) ++ { ++ case RT_CID_DEFAULT: ++ pledpriv->LedStrategy = SW_LED_MODE1; ++ pledpriv->bRegUseLed = _TRUE; ++ break; ++ ++ case RT_CID_819x_HP: ++ pledpriv->LedStrategy = SW_LED_MODE6; ++ break; ++ ++ default: ++ pledpriv->LedStrategy = SW_LED_MODE1; ++ break; ++ } ++ ++ if( BOARD_MINICARD == pHalData->BoardType ) ++ { ++ pledpriv->LedStrategy = SW_LED_MODE6; ++ } ++ pHalData->bLedOpenDrain = _TRUE;// Support Open-drain arrangement for controlling the LED. Added by Roger, 2009.10.16. ++#else // HW LED ++ pledpriv->LedStrategy = HW_LED; ++#endif //CONFIG_SW_LED ++} ++ ++static VOID ++_ReadThermalMeter( ++ IN PADAPTER Adapter, ++ IN u8* PROMContent, ++ IN BOOLEAN AutoloadFail ++ ) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ struct dm_priv *pdmpriv = &pHalData->dmpriv; ++ u8 tempval; ++ ++ // ++ // ThermalMeter from EEPROM ++ // ++ if(!AutoloadFail) ++ tempval = PROMContent[EEPROM_THERMAL_METER]; ++ else ++ tempval = EEPROM_Default_ThermalMeter; ++ ++ pHalData->EEPROMThermalMeter = (tempval&0x1f); //[4:0] ++ ++ if(pHalData->EEPROMThermalMeter == 0x1f || AutoloadFail) ++ pdmpriv->bAPKThermalMeterIgnore = _TRUE; ++ ++#if 0 ++ if(pHalData->EEPROMThermalMeter < 0x06 || pHalData->EEPROMThermalMeter > 0x1c) ++ pHalData->EEPROMThermalMeter = 0x12; ++#endif ++ ++ pdmpriv->ThermalMeter[0] = pHalData->EEPROMThermalMeter; ++ ++ //RTPRINT(FINIT, INIT_TxPower, ("ThermalMeter = 0x%x\n", pHalData->EEPROMThermalMeter)); ++ ++} ++ ++static VOID ++_ReadRFSetting( ++ IN PADAPTER Adapter, ++ IN u8* PROMContent, ++ IN BOOLEAN AutoloadFail ++ ) ++{ ++} ++ ++static void ++_ReadPROMVersion( ++ IN PADAPTER Adapter, ++ IN u8* PROMContent, ++ IN BOOLEAN AutoloadFail ++ ) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ ++ if(AutoloadFail){ ++ pHalData->EEPROMVersion = EEPROM_Default_Version; ++ } ++ else{ ++ pHalData->EEPROMVersion = *(u8 *)&PROMContent[EEPROM_VERSION]; ++ } ++} ++ ++static VOID ++readAntennaDiversity( ++ IN PADAPTER pAdapter, ++ IN u8 *hwinfo, ++ IN BOOLEAN AutoLoadFail ++ ) ++{ ++ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); ++ struct registry_priv *registry_par = &pAdapter->registrypriv; ++ ++ if(!AutoLoadFail) ++ { ++ // Antenna Diversity setting. ++ if(registry_par->antdiv_cfg == 2) // 2: From Efuse ++ pHalData->AntDivCfg = (hwinfo[EEPROM_RF_OPT1]&0x18)>>3; ++ else ++ pHalData->AntDivCfg = registry_par->antdiv_cfg ; // 0:OFF , 1:ON, ++ ++ DBG_8192C("### AntDivCfg(%x)\n",pHalData->AntDivCfg); ++ ++ //if(pHalData->EEPROMBluetoothCoexist!=0 && pHalData->EEPROMBluetoothAntNum==Ant_x1) ++ // pHalData->AntDivCfg = 0; ++ } ++ else ++ { ++ pHalData->AntDivCfg = 0; ++ } ++ ++} ++ ++static VOID ++hal_InitPGData( ++ IN PADAPTER pAdapter, ++ IN OUT u8 *PROMContent ++ ) ++{ ++ EEPROM_EFUSE_PRIV *pEEPROM = GET_EEPROM_EFUSE_PRIV(pAdapter); ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter); ++ u32 i; ++ u16 value16; ++ ++ if(_FALSE == pEEPROM->bautoload_fail_flag) ++ { // autoload OK. ++ if (_TRUE == pEEPROM->EepromOrEfuse) ++ { ++ // Read all Content from EEPROM or EFUSE. ++ for(i = 0; i < HWSET_MAX_SIZE; i += 2) ++ { ++ //value16 = EF2Byte(ReadEEprom(pAdapter, (u2Byte) (i>>1))); ++ //*((u16 *)(&PROMContent[i])) = value16; ++ } ++ } ++ else ++ { ++ // Read EFUSE real map to shadow. ++ EFUSE_ShadowMapUpdate(pAdapter, EFUSE_WIFI, _FALSE); ++ _rtw_memcpy((void*)PROMContent, (void*)pEEPROM->efuse_eeprom_data, HWSET_MAX_SIZE); ++ } ++ } ++ else ++ {//autoload fail ++ //RT_TRACE(COMP_INIT, DBG_LOUD, ("AutoLoad Fail reported from CR9346!!\n")); ++ pEEPROM->bautoload_fail_flag = _TRUE; ++ //update to default value 0xFF ++ if (_FALSE == pEEPROM->EepromOrEfuse) ++ EFUSE_ShadowMapUpdate(pAdapter, EFUSE_WIFI, _FALSE); ++ } ++} ++// Read HW power down mode selection ++static void _ReadPSSetting(IN PADAPTER Adapter,IN u8*PROMContent,IN u8 AutoloadFail) ++{ ++ if(AutoloadFail){ ++ Adapter->pwrctrlpriv.bHWPowerdown = _FALSE; ++ Adapter->pwrctrlpriv.bSupportRemoteWakeup = _FALSE; ++ } ++ else { ++ //if(SUPPORT_HW_RADIO_DETECT(Adapter)) ++ Adapter->pwrctrlpriv.bHWPwrPindetect = Adapter->registrypriv.hwpwrp_detect; ++ //else ++ //Adapter->pwrctrlpriv.bHWPwrPindetect = _FALSE;//dongle not support new ++ ++ ++ //hw power down mode selection , 0:rf-off / 1:power down ++ ++ if(Adapter->registrypriv.hwpdn_mode==2) ++ Adapter->pwrctrlpriv.bHWPowerdown = (PROMContent[EEPROM_RF_OPT3] & BIT4); ++ else ++ Adapter->pwrctrlpriv.bHWPowerdown = Adapter->registrypriv.hwpdn_mode; ++#ifdef CONFIG_WOWLAN ++ // decide hw if support remote wakeup function ++ // if hw supported, 8051 (SIE) will generate WeakUP signal( D+/D- toggle) when autoresume ++ Adapter->pwrctrlpriv.bSupportRemoteWakeup = (PROMContent[EEPROM_TEST_USB_OPT] & BIT1)?_TRUE :_FALSE; ++#endif //CONFIG_WOWLAN ++ ++ //if(SUPPORT_HW_RADIO_DETECT(Adapter)) ++ //Adapter->registrypriv.usbss_enable = Adapter->pwrctrlpriv.bSupportRemoteWakeup ; ++ ++ DBG_8192C("%s...bHWPwrPindetect(%x)-bHWPowerdown(%x) ,bSupportRemoteWakeup(%x)\n",__FUNCTION__, ++ Adapter->pwrctrlpriv.bHWPwrPindetect,Adapter->pwrctrlpriv.bHWPowerdown ,Adapter->pwrctrlpriv.bSupportRemoteWakeup); ++ ++ DBG_8192C("### PS params=> power_mgnt(%x),usbss_enable(%x) ###\n",Adapter->registrypriv.power_mgnt,Adapter->registrypriv.usbss_enable); ++ ++ } ++ ++} ++ ++static VOID ++readAdapterInfo_8192CU( ++ IN PADAPTER Adapter ++ ) ++{ ++ EEPROM_EFUSE_PRIV *pEEPROM = GET_EEPROM_EFUSE_PRIV(Adapter); ++ PHAL_DATA_TYPE pHalData = GET_HAL_DATA(Adapter); ++ u8 PROMContent[HWSET_MAX_SIZE]={0}; ++ ++ hal_InitPGData(Adapter, PROMContent); ++ rtl8192c_EfuseParseIDCode(Adapter, PROMContent); ++ ++ _ReadPROMVersion(Adapter, PROMContent, pEEPROM->bautoload_fail_flag); ++ _ReadIDs(Adapter, PROMContent, pEEPROM->bautoload_fail_flag); ++ _ReadMACAddress(Adapter, PROMContent, pEEPROM->bautoload_fail_flag); ++ ReadTxPowerInfo(Adapter, PROMContent, pEEPROM->bautoload_fail_flag); ++ _ReadBoardType(Adapter, PROMContent, pEEPROM->bautoload_fail_flag); ++ ++#ifdef CONFIG_BT_COEXIST ++ // ++ // Read Bluetooth co-exist and initialize ++ // ++ rtl8192c_ReadBluetoothCoexistInfo(Adapter, PROMContent, pEEPROM->bautoload_fail_flag); ++#endif ++ ++ ReadChannelPlan(Adapter, PROMContent, pEEPROM->bautoload_fail_flag); ++ _ReadThermalMeter(Adapter, PROMContent, pEEPROM->bautoload_fail_flag); ++ _ReadLEDSetting(Adapter, PROMContent, pEEPROM->bautoload_fail_flag); ++ _ReadRFSetting(Adapter, PROMContent, pEEPROM->bautoload_fail_flag); ++ _ReadPSSetting(Adapter, PROMContent, pEEPROM->bautoload_fail_flag); ++ readAntennaDiversity(Adapter, PROMContent, pEEPROM->bautoload_fail_flag); ++ ++ //hal_CustomizedBehavior_8723U(Adapter); ++ ++ Adapter->bDongle = (PROMContent[EEPROM_EASY_REPLACEMENT] == 1)? 0: 1; ++ DBG_8192C("%s(): REPLACEMENT = %x\n",__FUNCTION__,Adapter->bDongle); ++#ifdef CONFIG_INTEL_PROXIM ++ /* for intel proximity */ ++ if (pHalData->rf_type== RF_1T1R) { ++ Adapter->proximity.proxim_support = _TRUE; ++ } else if (pHalData->rf_type== RF_2T2R) { ++ if ((pHalData->EEPROMPID == 0x8186) && ++ (pHalData->EEPROMVID== 0x0bda)) ++ Adapter->proximity.proxim_support = _TRUE; ++ } else { ++ Adapter->proximity.proxim_support = _FALSE; ++ } ++#endif //CONFIG_INTEL_PROXIM ++} ++ ++static void _ReadPROMContent( ++ IN PADAPTER Adapter ++ ) ++{ ++ EEPROM_EFUSE_PRIV *pEEPROM = GET_EEPROM_EFUSE_PRIV(Adapter); ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ u8 PROMContent[HWSET_MAX_SIZE]={0}; ++ u8 eeValue; ++ u32 i; ++ u16 value16; ++ ++ eeValue = rtw_read8(Adapter, REG_9346CR); ++ // To check system boot selection. ++ pEEPROM->EepromOrEfuse = (eeValue & BOOT_FROM_EEPROM) ? _TRUE : _FALSE; ++ pEEPROM->bautoload_fail_flag = (eeValue & EEPROM_EN) ? _FALSE : _TRUE; ++ ++ ++ DBG_8192C("Boot from %s, Autoload %s !\n", (pEEPROM->EepromOrEfuse ? "EEPROM" : "EFUSE"), ++ (pEEPROM->bautoload_fail_flag ? "Fail" : "OK") ); ++ ++ //pHalData->EEType = IS_BOOT_FROM_EEPROM(Adapter) ? EEPROM_93C46 : EEPROM_BOOT_EFUSE; ++ ++ //if(IS_HARDWARE_TYPE_8723(Adapter)) ++ // readAdapterInfo_8723U(Adapter); ++ //else ++ readAdapterInfo_8192CU(Adapter); ++} ++ ++ ++static VOID ++_InitOtherVariable( ++ IN PADAPTER Adapter ++ ) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ ++ ++ //if(Adapter->bInHctTest){ ++ // pMgntInfo->PowerSaveControl.bInactivePs = FALSE; ++ // pMgntInfo->PowerSaveControl.bIPSModeBackup = FALSE; ++ // pMgntInfo->PowerSaveControl.bLeisurePs = FALSE; ++ // pMgntInfo->keepAliveLevel = 0; ++ //} ++ ++ // 2009/06/10 MH For 92S 1*1=1R/ 1*2&2*2 use 2R. We default set 1*1 use radio A ++ // So if you want to use radio B. Please modify RF path enable bit for correct signal ++ // strength calculate. ++ if (pHalData->rf_type == RF_1T1R){ ++ pHalData->bRFPathRxEnable[0] = _TRUE; ++ } ++ else{ ++ pHalData->bRFPathRxEnable[0] = pHalData->bRFPathRxEnable[1] = _TRUE; ++ } ++ ++} ++ ++static VOID ++_ReadRFType( ++ IN PADAPTER Adapter ++ ) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ ++#if DISABLE_BB_RF ++ pHalData->rf_chip = RF_PSEUDO_11N; ++#else ++ pHalData->rf_chip = RF_6052; ++#endif ++} ++ ++void _ReadSilmComboMode(PADAPTER Adapter) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ ++ pHalData->SlimComboDbg = _FALSE; // Default is not debug mode. ++ ++ // 2010/11/22 MH We need to enter debug mode for TSMA and UMC A cut ++ if ((Adapter->chip_type == RTL8188C_8192C) && ++ (pHalData->BoardType == BOARD_USB_COMBO)) ++ { ++ switch (pHalData->VersionID) ++ { ++ case VERSION_NORMAL_TSMC_CHIP_88C: ++ case VERSION_NORMAL_TSMC_CHIP_92C: ++ case VERSION_NORMAL_TSMC_CHIP_92C_1T2R: ++ case VERSION_NORMAL_UMC_CHIP_88C_A_CUT: ++ case VERSION_NORMAL_UMC_CHIP_92C_A_CUT: ++ case VERSION_NORMAL_UMC_CHIP_92C_1T2R_A_CUT: ++ if ((rtw_read8(Adapter, REG_SYS_CFG+3) &0xF0) == 0x20) ++ pHalData->SlimComboDbg = _TRUE; ++ ++ break; ++ ++ case VERSION_NORMAL_UMC_CHIP_88C_B_CUT: ++ case VERSION_NORMAL_UMC_CHIP_92C_B_CUT: ++ case VERSION_NORMAL_UMC_CHIP_92C_1T2R_B_CUT: ++ // 2011/02/15 MH UNC-B cut ECO fail, we need to support slim combo debug mode. ++ if ((rtw_read8(Adapter, REG_SYS_CFG+3) &0xF0) == 0x20) ++ pHalData->SlimComboDbg = _TRUE; ++ break; ++ ++ default: ++ break; ++ } ++ ++ } ++ ++} ++static int _ReadAdapterInfo8192CU(PADAPTER Adapter) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ u32 start=rtw_get_current_time(); ++ ++ MSG_8192C("====> ReadAdapterInfo8192C\n"); ++ ++ //Efuse_InitSomeVar(Adapter); ++ ++ //if(IS_HARDWARE_TYPE_8723(Adapter)) ++ // _EfuseCellSel(Adapter); ++ ++ _ReadRFType(Adapter);//rf_chip -> _InitRFType() ++ _ReadPROMContent(Adapter); ++ ++ // 2010/10/25 MH THe function must be called after borad_type & IC-Version recognize. ++ _ReadSilmComboMode(Adapter); ++ ++ _InitOtherVariable(Adapter); ++ ++ //MSG_8192C("%s()(done), rf_chip=0x%x, rf_type=0x%x\n", __FUNCTION__, pHalData->rf_chip, pHalData->rf_type); ++ ++ MSG_8192C("<==== ReadAdapterInfo8192C in %d ms\n", rtw_get_passing_time_ms(start)); ++ ++ return _SUCCESS; ++} ++ ++ ++static void ReadAdapterInfo8192CU(PADAPTER Adapter) ++{ ++ // Read EEPROM size before call any EEPROM function ++ //Adapter->EepromAddressSize=Adapter->HalFunc.GetEEPROMSizeHandler(Adapter); ++ Adapter->EepromAddressSize = GetEEPROMSize8192C(Adapter); ++ ++ _ReadAdapterInfo8192CU(Adapter); ++} ++ ++ ++#define GPIO_DEBUG_PORT_NUM 0 ++static void rtl8192cu_trigger_gpio_0(_adapter *padapter) ++{ ++ ++ u32 gpioctrl; ++ DBG_8192C("==> trigger_gpio_0...\n"); ++ rtw_write16_async(padapter,REG_GPIO_PIN_CTRL,0); ++ rtw_write8_async(padapter,REG_GPIO_PIN_CTRL+2,0xFF); ++ gpioctrl = (BIT(GPIO_DEBUG_PORT_NUM)<<24 )|(BIT(GPIO_DEBUG_PORT_NUM)<<16); ++ rtw_write32_async(padapter,REG_GPIO_PIN_CTRL,gpioctrl); ++ gpioctrl |= (BIT(GPIO_DEBUG_PORT_NUM)<<8); ++ rtw_write32_async(padapter,REG_GPIO_PIN_CTRL,gpioctrl); ++ DBG_8192C("<=== trigger_gpio_0...\n"); ++ ++} ++ ++static void ResumeTxBeacon(_adapter *padapter) ++{ ++ HAL_DATA_TYPE* pHalData = GET_HAL_DATA(padapter); ++ ++ // 2010.03.01. Marked by tynli. No need to call workitem beacause we record the value ++ // which should be read from register to a global variable. ++ ++ if(IS_NORMAL_CHIP(pHalData->VersionID)) ++ { ++ rtw_write8(padapter, REG_FWHW_TXQ_CTRL+2, (pHalData->RegFwHwTxQCtrl) | BIT6); ++ pHalData->RegFwHwTxQCtrl |= BIT6; ++ rtw_write8(padapter, REG_TBTT_PROHIBIT+1, 0xff); ++ pHalData->RegReg542 |= BIT0; ++ rtw_write8(padapter, REG_TBTT_PROHIBIT+2, pHalData->RegReg542); ++ } ++ else ++ { ++ pHalData->RegTxPause = rtw_read8(padapter, REG_TXPAUSE); ++ rtw_write8(padapter, REG_TXPAUSE, pHalData->RegTxPause & (~BIT6)); ++ } ++ ++} ++ ++static void StopTxBeacon(_adapter *padapter) ++{ ++ HAL_DATA_TYPE* pHalData = GET_HAL_DATA(padapter); ++ ++ // 2010.03.01. Marked by tynli. No need to call workitem beacause we record the value ++ // which should be read from register to a global variable. ++ ++ if(IS_NORMAL_CHIP(pHalData->VersionID)) ++ { ++ rtw_write8(padapter, REG_FWHW_TXQ_CTRL+2, (pHalData->RegFwHwTxQCtrl) & (~BIT6)); ++ pHalData->RegFwHwTxQCtrl &= (~BIT6); ++ rtw_write8(padapter, REG_TBTT_PROHIBIT+1, 0x64); ++ pHalData->RegReg542 &= ~(BIT0); ++ rtw_write8(padapter, REG_TBTT_PROHIBIT+2, pHalData->RegReg542); ++ } ++ else ++ { ++ pHalData->RegTxPause = rtw_read8(padapter, REG_TXPAUSE); ++ rtw_write8(padapter, REG_TXPAUSE, pHalData->RegTxPause | BIT6); ++ } ++ ++ //todo: CheckFwRsvdPageContent(Adapter); // 2010.06.23. Added by tynli. ++ ++} ++ ++u16 CRC16(u8 data,u16 CRC) ++{ ++ unsigned char shift_in,CRC_BIT15,DataBit,CRC_BIT11,CRC_BIT4 ; ++ int index; ++ unsigned short CRC_Result; ++ ++ for(index=0;index<8;index++) ++ { ++ CRC_BIT15=((CRC&BIT15) ? 1:0); ++ DataBit =(data&(BIT0<pwrctrlpriv; ++ int res=0,crc_idx; ++ u32 content=0,cmd=0; ++ u32 *pdata; ++ u8 config,crc,mc,bc,uc,idx,pattern_len,packet[200],packet_len,valid; ++ u16 crc_val=0,i; ++ ++ config=pbuf[0]; ++ bc=config & BIT(3)?1:0; ++ mc=config & BIT(4)?1:0; ++ uc=config & BIT(5)?1:0; ++ idx=config & 0x7; ++ crc=config & BIT(6)?1:0; ++ valid=config & BIT(7)?1:0; ++ pattern_len=pbuf[1]; ++ packet_len=pattern_len*8; ++ pdata=(u32 *)pbuf; ++ ++ // Write to the Wakeup CAM ++ //offset 0 ++ if(pattern_len>=4){ ++ content=pdata[1]; ++ } ++ else{ ++ content=0; ++ } ++ DBG_8192C("\nrtw_wowlan_set_pattern offset[0] content 0x%x [cpu_to_le32 0x%x]\n", content,__cpu_to_le32(content)); ++ //rtw_write32(padapter, REG_WKFMCAM_RWD, __cpu_to_le32(content)); ++ pwrpriv->wowlan_pattern_context[idx][0]= __cpu_to_le32(content); ++ //cmd=BIT(31)|BIT(16)|(idx+0); ++ //rtw_write32(padapter, REG_WKFMCAM_CMD, cmd); ++ //offset 4 ++ if(pattern_len>=8){ ++ content=pdata[2]; ++ } ++ else{ ++ content=0; ++ } ++ DBG_8192C("rtw_wowlan_set_pattern offset[4] content 0x%x [cpu_to_le32 0x%x]\n", content,__cpu_to_le32(content)); ++ //rtw_write32(padapter, REG_WKFMCAM_RWD, __cpu_to_le32(content)); ++ pwrpriv->wowlan_pattern_context[idx][1]= __cpu_to_le32(content); ++ ++ //cmd=BIT(31)|BIT(16)|(idx+1); ++ //rtw_write32(padapter, REG_WKFMCAM_CMD, cmd); ++ //offset 8 ++ if(pattern_len>=12){ ++ content=pdata[3]; ++ } ++ else{ ++ content=0; ++ } ++ DBG_8192C("rtw_wowlan_set_pattern offset[8] content 0x%x [cpu_to_le32 0x%x]\n", content,__cpu_to_le32(content)); ++ //rtw_write32(padapter, REG_WKFMCAM_RWD, __cpu_to_le32(content)); ++ pwrpriv->wowlan_pattern_context[idx][2]= __cpu_to_le32(content); ++ //cmd=BIT(31)|BIT(16)|(idx+2); ++ //rtw_write32(padapter, REG_WKFMCAM_CMD, cmd); ++ //offset 12 ++ if(pattern_len>=16){ ++ content=pdata[4]; ++ } ++ else{ ++ content=0; ++ } ++ DBG_8192C("rtw_wowlan_set_pattern offset[12] content 0x%x [cpu_to_le32 0x%x]\n", content,__cpu_to_le32(content)); ++ //rtw_write32(padapter, REG_WKFMCAM_RWD, __cpu_to_le32(content)); ++ pwrpriv->wowlan_pattern_context[idx][3]= __cpu_to_le32(content); ++ //cmd=BIT(31)|BIT(16)|(idx+3); ++ //rtw_write32(padapter, REG_WKFMCAM_CMD, cmd); ++ ++ if(crc){ ++ // Have the CRC value ++ crc_val=*(u16 *)(&pbuf[2]); ++ DBG_8192C("rtw_wowlan_set_pattern crc_val 0x%x \n", crc_val); ++ crc_val=__cpu_to_le16(crc_val); ++ DBG_8192C("rtw_wowlan_set_pattern crc_val after 0x%x \n", crc_val); ++ } ++ else{ ++ DBG_8192C("+rtw_wowlan_set_pattern crc=0[%x] Should calculate the CRC\n", crc); ++ // calculate the CRC the write to the Wakeup CAM ++ crc_idx=0; ++ for(i=0;iwowlan_pattern_context[idx][4]= content; ++ //cmd=BIT(31)|BIT(16)|(idx+4); ++ //rtw_write32(padapter, REG_WKFMCAM_CMD, cmd); ++ pwrpriv->wowlan_pattern_idx|=BIT(idx); ++ ++_rtw_wowlan_set_pattern_exit: ++ return res; ++} ++ ++ ++ ++void rtw_wowlan_reload_pattern(_adapter *padapter){ ++ struct pwrctrl_priv *pwrpriv=&padapter->pwrctrlpriv; ++ u32 content=0,cmd=0; ++ u8 idx; ++ ++ for (idx=0;idx<8;idx ++){ ++ if(pwrpriv->wowlan_pattern_idx & BIT(idx)){ ++ //offset 0 ++ rtw_write32(padapter, REG_WKFMCAM_RWD, pwrpriv->wowlan_pattern_context[idx][0]); ++ cmd=BIT(31)|BIT(16)|(idx+0); ++ rtw_write32(padapter, REG_WKFMCAM_CMD, cmd); ++ ++ //offset 4 ++ rtw_write32(padapter, REG_WKFMCAM_RWD, pwrpriv->wowlan_pattern_context[idx][1]); ++ cmd=BIT(31)|BIT(16)|(idx+1); ++ rtw_write32(padapter, REG_WKFMCAM_CMD, cmd); ++ ++ //offset 8 ++ rtw_write32(padapter, REG_WKFMCAM_RWD, pwrpriv->wowlan_pattern_context[idx][2]); ++ cmd=BIT(31)|BIT(16)|(idx+2); ++ rtw_write32(padapter, REG_WKFMCAM_CMD, cmd); ++ ++ //offset 12 ++ rtw_write32(padapter, REG_WKFMCAM_RWD, pwrpriv->wowlan_pattern_context[idx][3]); ++ cmd=BIT(31)|BIT(16)|(idx+3); ++ rtw_write32(padapter, REG_WKFMCAM_CMD, cmd); ++ ++ //offset 16 ++ rtw_write32(padapter, REG_WKFMCAM_RWD, pwrpriv->wowlan_pattern_context[idx][4]); ++ cmd=BIT(31)|BIT(16)|(idx+4); ++ rtw_write32(padapter, REG_WKFMCAM_CMD, cmd); ++ ++ } ++ printk("print WOWCAM idx =%d\n",idx); ++ cmd=BIT(31)|(idx+0); ++ rtw_write32(padapter, REG_WKFMCAM_CMD, cmd); ++ printk("print WOWCAM offset[0] =%x\n",rtw_read32(padapter, REG_WKFMCAM_RWD)); ++ cmd=BIT(31)|(idx+1); ++ rtw_write32(padapter, REG_WKFMCAM_CMD, cmd); ++ printk("print WOWCAM offset[1] =%x\n",rtw_read32(padapter, REG_WKFMCAM_RWD)); ++ cmd=BIT(31)|(idx+2); ++ rtw_write32(padapter, REG_WKFMCAM_CMD, cmd); ++ printk("print WOWCAM offset[2] =%x\n",rtw_read32(padapter, REG_WKFMCAM_RWD)); ++ cmd=BIT(31)|(idx+3); ++ rtw_write32(padapter, REG_WKFMCAM_CMD, cmd); ++ printk("print WOWCAM offset[3] =%x\n",rtw_read32(padapter, REG_WKFMCAM_RWD)); ++ cmd=BIT(31)|(idx+4); ++ rtw_write32(padapter, REG_WKFMCAM_CMD, cmd); ++ printk("print WOWCAM offset[4] =%x\n",rtw_read32(padapter, REG_WKFMCAM_RWD)); ++ ++ ++ } ++} ++#endif //CONFIG_WOWLAN ++ ++void SetHwReg8192CU(PADAPTER Adapter, u8 variable, u8* val) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ struct dm_priv *pdmpriv = &pHalData->dmpriv; ++ ++_func_enter_; ++ ++ switch(variable) ++ { ++ case HW_VAR_MEDIA_STATUS: ++ { ++ u8 val8; ++ ++ val8 = rtw_read8(Adapter, MSR)&0x0c; ++ val8 |= *((u8 *)val); ++ rtw_write8(Adapter, MSR, val8); ++ } ++ break; ++ case HW_VAR_MEDIA_STATUS1: ++ { ++ u8 val8; ++ ++ val8 = rtw_read8(Adapter, MSR)&0x03; ++ val8 |= *((u8 *)val) <<2; ++ rtw_write8(Adapter, MSR, val8); ++ } ++ break; ++ case HW_VAR_SET_OPMODE: ++ { ++ u8 val8; ++ u8 mode = *((u8 *)val); ++ ++ if((mode == _HW_STATE_STATION_) || (mode == _HW_STATE_NOLINK_)) ++ { ++ StopTxBeacon(Adapter); ++ rtw_write8(Adapter,REG_BCN_CTRL, 0x18); ++ } ++ else if((mode == _HW_STATE_ADHOC_) /*|| (mode == _HW_STATE_AP_)*/) ++ { ++ ResumeTxBeacon(Adapter); ++ rtw_write8(Adapter,REG_BCN_CTRL, 0x1a); ++ } ++ else if(mode == _HW_STATE_AP_) ++ { ++ ResumeTxBeacon(Adapter); ++ ++ rtw_write8(Adapter, REG_BCN_CTRL, 0x12); ++ ++ ++ //Set RCR ++ //rtw_write32(padapter, REG_RCR, 0x70002a8e);//CBSSID_DATA must set to 0 ++ rtw_write32(Adapter, REG_RCR, 0x7000228e);//CBSSID_DATA must set to 0 ++ //enable to rx data frame ++ rtw_write16(Adapter, REG_RXFLTMAP2, 0xFFFF); ++ //enable to rx ps-poll ++ rtw_write16(Adapter, REG_RXFLTMAP1, 0x0400); ++ ++ //Beacon Control related register for first time ++ rtw_write8(Adapter, REG_BCNDMATIM, 0x02); // 2ms ++ rtw_write8(Adapter, REG_DRVERLYINT, 0x05);// 5ms ++ //rtw_write8(Adapter, REG_BCN_MAX_ERR, 0xFF); ++ rtw_write8(Adapter, REG_ATIMWND, 0x0a); // 10ms ++ rtw_write16(Adapter, REG_BCNTCFG, 0x00); ++ rtw_write16(Adapter, REG_TBTT_PROHIBIT, 0x6404); ++ ++ //reset TSF ++ rtw_write8(Adapter, REG_DUAL_TSF_RST, BIT(0)); ++ ++ //enable TSF Function for if1 ++ rtw_write8(Adapter, REG_BCN_CTRL, (EN_BCN_FUNCTION | EN_TXBCN_RPT)); ++ ++ //enable update TSF for if1 ++ if(IS_NORMAL_CHIP(pHalData->VersionID)) ++ { ++ rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)&(~BIT(4))); ++ } ++ else ++ { ++ rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)&(~(BIT(4)|BIT(5)))); ++ } ++ ++ } ++ ++ val8 = rtw_read8(Adapter, MSR)&0x0c; ++ val8 |= mode; ++ rtw_write8(Adapter, MSR, val8); ++ } ++ break; ++ case HW_VAR_BSSID: ++ { ++ u8 idx = 0; ++ for(idx = 0 ; idx < 6; idx++) ++ { ++ rtw_write8(Adapter, (REG_BSSID+idx), val[idx]); ++ } ++ } ++ break; ++ case HW_VAR_BASIC_RATE: ++ { ++ u16 BrateCfg = 0; ++ u8 RateIndex = 0; ++ ++ // 2007.01.16, by Emily ++ // Select RRSR (in Legacy-OFDM and CCK) ++ // For 8190, we select only 24M, 12M, 6M, 11M, 5.5M, 2M, and 1M from the Basic rate. ++ // We do not use other rates. ++ rtl8192c_HalSetBrateCfg( Adapter, val, &BrateCfg ); ++ ++ //2011.03.30 add by Luke Lee ++ //CCK 2M ACK should be disabled for some BCM and Atheros AP IOT ++ //because CCK 2M has poor TXEVM ++ //CCK 5.5M & 11M ACK should be enabled for better performance ++ ++ pHalData->BasicRateSet = BrateCfg = (BrateCfg |0xd) & 0x15d; ++ ++ BrateCfg |= 0x01; // default enable 1M ACK rate ++ ++ DBG_8192C("HW_VAR_BASIC_RATE: BrateCfg(%#x)\n", BrateCfg); ++ ++ // Set RRSR rate table. ++ rtw_write8(Adapter, REG_RRSR, BrateCfg&0xff); ++ rtw_write8(Adapter, REG_RRSR+1, (BrateCfg>>8)&0xff); ++ ++ // Set RTS initial rate ++ while(BrateCfg > 0x1) ++ { ++ BrateCfg = (BrateCfg>> 1); ++ RateIndex++; ++ } ++ // Ziv - Check ++ rtw_write8(Adapter, REG_INIRTS_RATE_SEL, RateIndex); ++ } ++ break; ++ case HW_VAR_TXPAUSE: ++ rtw_write8(Adapter, REG_TXPAUSE, *((u8 *)val)); ++ break; ++ case HW_VAR_BCN_FUNC: ++ if(*((u8 *)val)) ++ { ++ rtw_write8(Adapter, REG_BCN_CTRL, (EN_BCN_FUNCTION | EN_TXBCN_RPT)); ++ } ++ else ++ { ++ rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)&(~(EN_BCN_FUNCTION | EN_TXBCN_RPT))); ++ } ++ break; ++ case HW_VAR_CORRECT_TSF: ++ { ++ u64 tsf; ++ struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ ++ //tsf = pmlmeext->TSFValue - ((u32)pmlmeext->TSFValue % (pmlmeinfo->bcn_interval*1024)) -1024; //us ++ tsf = pmlmeext->TSFValue - rtw_modular64(pmlmeext->TSFValue, (pmlmeinfo->bcn_interval*1024)) -1024; //us ++ ++ if(((pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE) || ((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE)) ++ { ++ //pHalData->RegTxPause |= STOP_BCNQ;BIT(6) ++ //rtw_write8(Adapter, REG_TXPAUSE, (rtw_read8(Adapter, REG_TXPAUSE)|BIT(6))); ++ StopTxBeacon(Adapter); ++ } ++ ++ //disable related TSF function ++ rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)&(~BIT(3))); ++ ++ rtw_write32(Adapter, REG_TSFTR, tsf); ++ rtw_write32(Adapter, REG_TSFTR+4, tsf>>32); ++ ++ //enable related TSF function ++ rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)|BIT(3)); ++ ++ ++ if(((pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE) || ((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE)) ++ { ++ //pHalData->RegTxPause &= (~STOP_BCNQ); ++ //rtw_write8(Adapter, REG_TXPAUSE, (rtw_read8(Adapter, REG_TXPAUSE)&(~BIT(6)))); ++ ResumeTxBeacon(Adapter); ++ } ++ } ++ break; ++ case HW_VAR_CHECK_BSSID: ++ if(*((u8 *)val)) ++ { ++ if(IS_NORMAL_CHIP(pHalData->VersionID)) ++ { ++ rtw_write32(Adapter, REG_RCR, rtw_read32(Adapter, REG_RCR)|RCR_CBSSID_DATA|RCR_CBSSID_BCN); ++ } ++ else ++ { ++ rtw_write32(Adapter, REG_RCR, rtw_read32(Adapter, REG_RCR)|RCR_CBSSID_DATA); ++ } ++ } ++ else ++ { ++ u32 val32; ++ ++ val32 = rtw_read32(Adapter, REG_RCR); ++ ++ if(IS_NORMAL_CHIP(pHalData->VersionID)) ++ { ++ val32 &= ~(RCR_CBSSID_DATA | RCR_CBSSID_BCN); ++ } ++ else ++ { ++ val32 &= 0xfffff7bf; ++ } ++ ++ rtw_write32(Adapter, REG_RCR, val32); ++ } ++ break; ++ case HW_VAR_MLME_DISCONNECT: ++ { ++ //Set RCR to not to receive data frame when NO LINK state ++ //rtw_write32(Adapter, REG_RCR, rtw_read32(padapter, REG_RCR) & ~RCR_ADF); ++ //reject all data frames ++ rtw_write16(Adapter, REG_RXFLTMAP2,0x00); ++ ++ //reset TSF ++ rtw_write8(Adapter, REG_DUAL_TSF_RST, (BIT(0)|BIT(1))); ++ ++ //disable update TSF ++ if(IS_NORMAL_CHIP(pHalData->VersionID)) ++ { ++ rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)|BIT(4)); ++ } ++ else ++ { ++ rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)|BIT(4)|BIT(5)); ++ } ++ } ++ break; ++ case HW_VAR_MLME_SITESURVEY: ++ if(*((u8 *)val))//under sitesurvey ++ { ++ if(IS_NORMAL_CHIP(pHalData->VersionID)) ++ { ++ //config RCR to receive different BSSID & not to receive data frame ++ //pHalData->ReceiveConfig &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN)); ++ u32 v = rtw_read32(Adapter, REG_RCR); ++ v &= ~(RCR_CBSSID_DATA | RCR_CBSSID_BCN );//| RCR_ADF ++ rtw_write32(Adapter, REG_RCR, v); ++ //reject all data frame ++ rtw_write16(Adapter, REG_RXFLTMAP2,0x00); ++ ++ //disable update TSF ++ rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)|BIT(4)); ++ } ++ else ++ { ++ //config RCR to receive different BSSID & not to receive data frame ++ rtw_write32(Adapter, REG_RCR, rtw_read32(Adapter, REG_RCR) & 0xfffff7bf); ++ ++ ++ //disable update TSF ++ rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)|BIT(4)|BIT(5)); ++ } ++ } ++ else//sitesurvey done ++ { ++ struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ ++ if ((is_client_associated_to_ap(Adapter) == _TRUE) || ++ ((pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE) ) ++ { ++ //enable to rx data frame ++ //rtw_write32(Adapter, REG_RCR, rtw_read32(padapter, REG_RCR)|RCR_ADF); ++ rtw_write16(Adapter, REG_RXFLTMAP2,0xFFFF); ++ ++ //enable update TSF ++ if(IS_NORMAL_CHIP(pHalData->VersionID)) ++ { ++ rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)&(~BIT(4))); ++ } ++ else ++ { ++ rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)&(~(BIT(4)|BIT(5)))); ++ } ++ } ++ else if((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE) ++ { ++ rtw_write32(Adapter, REG_RCR, rtw_read32(Adapter, REG_RCR)|RCR_ADF); ++ ++ //enable update TSF ++ if(IS_NORMAL_CHIP(pHalData->VersionID)) ++ rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)&(~BIT(4))); ++ else ++ rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)&(~(BIT(4)|BIT(5)))); ++ } ++ ++ ++ if(IS_NORMAL_CHIP(pHalData->VersionID)) ++ { ++ if((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE) ++ rtw_write32(Adapter, REG_RCR, rtw_read32(Adapter, REG_RCR)|RCR_CBSSID_BCN); ++ else ++ rtw_write32(Adapter, REG_RCR, rtw_read32(Adapter, REG_RCR)|RCR_CBSSID_DATA|RCR_CBSSID_BCN); ++ } ++ else ++ { ++ rtw_write32(Adapter, REG_RCR, rtw_read32(Adapter, REG_RCR)|RCR_CBSSID_DATA); ++ } ++ } ++ break; ++ case HW_VAR_MLME_JOIN: ++ { ++ u8 RetryLimit = 0x30; ++ u8 type = *((u8 *)val); ++ struct mlme_priv *pmlmepriv = &Adapter->mlmepriv; ++ ++ if(type == 0) // prepare to join ++ { ++ //enable to rx data frame.Accept all data frame ++ //rtw_write32(padapter, REG_RCR, rtw_read32(padapter, REG_RCR)|RCR_ADF); ++ rtw_write16(Adapter, REG_RXFLTMAP2,0xFFFF); ++ ++ if(IS_NORMAL_CHIP(pHalData->VersionID)) ++ { ++ rtw_write32(Adapter, REG_RCR, rtw_read32(Adapter, REG_RCR)|RCR_CBSSID_DATA|RCR_CBSSID_BCN); ++ } ++ else ++ { ++ rtw_write32(Adapter, REG_RCR, rtw_read32(Adapter, REG_RCR)|RCR_CBSSID_DATA); ++ } ++ ++ if(check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE) ++ { ++ RetryLimit = (pHalData->CustomerID == RT_CID_CCX) ? 7 : 48; ++ } ++ else // Ad-hoc Mode ++ { ++ RetryLimit = 0x7; ++ } ++ } ++ else if(type == 1) //joinbss_event call back when join res < 0 ++ { ++ //if(IS_NORMAL_CHIP(pHalData->VersionID)) ++ //{ ++ //config RCR to receive different BSSID & not to receive data frame during linking ++ // u32 v = rtw_read32(Adapter, REG_RCR); ++ // v &= ~(RCR_CBSSID_DATA | RCR_CBSSID_BCN );//| RCR_ADF ++ // rtw_write32(Adapter, REG_RCR, v); ++ //} ++ //else ++ //{ ++ //config RCR to receive different BSSID & not to receive data frame during linking ++ // rtw_write32(Adapter, REG_RCR, rtw_read32(Adapter, REG_RCR) & 0xfffff7bf); ++ //} ++ ++ rtw_write16(Adapter, REG_RXFLTMAP2,0x00); ++ } ++ else if(type == 2) //sta add event call back ++ { ++ if(IS_NORMAL_CHIP(pHalData->VersionID)) ++ { ++ //enable update TSF ++ rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)&(~BIT(4))); ++ } ++ else ++ { ++ //enable update TSF ++ rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)&(~(BIT(4)|BIT(5)))); ++ } ++ ++ if(check_fwstate(pmlmepriv, WIFI_ADHOC_STATE|WIFI_ADHOC_MASTER_STATE)) ++ { ++ //fixed beacon issue for 8191su........... ++ rtw_write8(Adapter,0x542 ,0x02); ++ RetryLimit = 0x7; ++ } ++ } ++ ++ rtw_write16(Adapter, REG_RL, RetryLimit << RETRY_LIMIT_SHORT_SHIFT | RetryLimit << RETRY_LIMIT_LONG_SHIFT); ++ } ++ break; ++ case HW_VAR_BEACON_INTERVAL: ++ rtw_write16(Adapter, REG_BCN_INTERVAL, *((u16 *)val)); ++ break; ++ case HW_VAR_SLOT_TIME: ++ { ++ u8 u1bAIFS, aSifsTime; ++ struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ ++ rtw_write8(Adapter, REG_SLOT, val[0]); ++ ++ if(pmlmeinfo->WMM_enable == 0) ++ { ++ if( pmlmeext->cur_wireless_mode == WIRELESS_11B) ++ aSifsTime = 10; ++ else ++ aSifsTime = 16; ++ ++ u1bAIFS = aSifsTime + (2 * pmlmeinfo->slotTime); ++ ++ // Temporary removed, 2008.06.20. ++ rtw_write8(Adapter, REG_EDCA_VO_PARAM, u1bAIFS); ++ rtw_write8(Adapter, REG_EDCA_VI_PARAM, u1bAIFS); ++ rtw_write8(Adapter, REG_EDCA_BE_PARAM, u1bAIFS); ++ rtw_write8(Adapter, REG_EDCA_BK_PARAM, u1bAIFS); ++ } ++ } ++ break; ++ case HW_VAR_SIFS: ++ { ++ // SIFS for OFDM Data ACK ++ rtw_write8(Adapter, REG_SIFS_CTX+1, val[0]); ++ // SIFS for OFDM consecutive tx like CTS data! ++ rtw_write8(Adapter, REG_SIFS_TRX+1, val[1]); ++ ++ rtw_write8(Adapter,REG_SPEC_SIFS+1, val[0]); ++ rtw_write8(Adapter,REG_MAC_SPEC_SIFS+1, val[0]); ++ ++ // 20100719 Joseph: Revise SIFS setting due to Hardware register definition change. ++ rtw_write8(Adapter, REG_R2T_SIFS+1, val[0]); ++ rtw_write8(Adapter, REG_T2T_SIFS+1, val[0]); ++ } ++ break; ++ case HW_VAR_ACK_PREAMBLE: ++ { ++ u8 regTmp; ++ u8 bShortPreamble = *( (PBOOLEAN)val ); ++ // Joseph marked out for Netgear 3500 TKIP channel 7 issue.(Temporarily) ++ //regTmp = (pHalData->nCur40MhzPrimeSC)<<5; ++ regTmp = 0; ++ if(bShortPreamble) ++ regTmp |= 0x80; ++ ++ rtw_write8(Adapter, REG_RRSR+2, regTmp); ++ } ++ break; ++ case HW_VAR_SEC_CFG: ++ rtw_write8(Adapter, REG_SECCFG, *((u8 *)val)); ++ break; ++ case HW_VAR_DM_FLAG: ++ pdmpriv->DMFlag = *((u8 *)val); ++ break; ++ case HW_VAR_DM_FUNC_OP: ++ if(val[0]) ++ {// save dm flag ++ pdmpriv->DMFlag_tmp = pdmpriv->DMFlag; ++ } ++ else ++ {// restore dm flag ++ pdmpriv->DMFlag = pdmpriv->DMFlag_tmp; ++ } ++ break; ++ case HW_VAR_DM_FUNC_SET: ++ pdmpriv->DMFlag |= *((u8 *)val); ++ break; ++ case HW_VAR_DM_FUNC_CLR: ++ pdmpriv->DMFlag &= *((u8 *)val); ++ break; ++ case HW_VAR_CAM_EMPTY_ENTRY: ++ { ++ u8 ucIndex = *((u8 *)val); ++ u8 i; ++ u32 ulCommand=0; ++ u32 ulContent=0; ++ u32 ulEncAlgo=CAM_AES; ++ ++ for(i=0;iAcParam_BE = ((u32 *)(val))[0]; ++ rtw_write32(Adapter, REG_EDCA_BE_PARAM, ((u32 *)(val))[0]); ++ break; ++ case HW_VAR_AC_PARAM_BK: ++ rtw_write32(Adapter, REG_EDCA_BK_PARAM, ((u32 *)(val))[0]); ++ break; ++ case HW_VAR_ACM_CTRL: ++ { ++ u8 acm_ctrl = *((u8 *)val); ++ u8 AcmCtrl = rtw_read8( Adapter, REG_ACMHWCTRL); ++ ++ if(acm_ctrl > 1) ++ AcmCtrl = AcmCtrl | 0x1; ++ ++ if(acm_ctrl & BIT(3)) ++ AcmCtrl |= AcmHw_VoqEn; ++ else ++ AcmCtrl &= (~AcmHw_VoqEn); ++ ++ if(acm_ctrl & BIT(2)) ++ AcmCtrl |= AcmHw_ViqEn; ++ else ++ AcmCtrl &= (~AcmHw_ViqEn); ++ ++ if(acm_ctrl & BIT(1)) ++ AcmCtrl |= AcmHw_BeqEn; ++ else ++ AcmCtrl &= (~AcmHw_BeqEn); ++ ++ DBG_871X("[HW_VAR_ACM_CTRL] Write 0x%X\n", AcmCtrl ); ++ rtw_write8(Adapter, REG_ACMHWCTRL, AcmCtrl ); ++ } ++ break; ++ case HW_VAR_AMPDU_MIN_SPACE: ++ { ++ u8 MinSpacingToSet; ++ u8 SecMinSpace; ++ ++ MinSpacingToSet = *((u8 *)val); ++ if(MinSpacingToSet <= 7) ++ { ++ switch(Adapter->securitypriv.dot11PrivacyAlgrthm) ++ { ++ case _NO_PRIVACY_: ++ case _AES_: ++ SecMinSpace = 0; ++ break; ++ ++ case _WEP40_: ++ case _WEP104_: ++ case _TKIP_: ++ case _TKIP_WTMIC_: ++ SecMinSpace = 6; ++ break; ++ default: ++ SecMinSpace = 7; ++ break; ++ } ++ ++ if(MinSpacingToSet < SecMinSpace){ ++ MinSpacingToSet = SecMinSpace; ++ } ++ ++ //RT_TRACE(COMP_MLME, DBG_LOUD, ("Set HW_VAR_AMPDU_MIN_SPACE: %#x\n", Adapter->MgntInfo.MinSpaceCfg)); ++ rtw_write8(Adapter, REG_AMPDU_MIN_SPACE, (rtw_read8(Adapter, REG_AMPDU_MIN_SPACE) & 0xf8) | MinSpacingToSet); ++ } ++ } ++ break; ++ case HW_VAR_AMPDU_FACTOR: ++ { ++ u8 RegToSet_Normal[4]={0x41,0xa8,0x72, 0xb9}; ++ u8 RegToSet_BT[4]={0x31,0x74,0x42, 0x97}; ++ u8 FactorToSet; ++ u8 *pRegToSet; ++ u8 index = 0; ++ ++#ifdef CONFIG_BT_COEXIST ++ if( (pHalData->bt_coexist.BT_Coexist) && ++ (pHalData->bt_coexist.BT_CoexistType == BT_CSR_BC4) ) ++ pRegToSet = RegToSet_BT; // 0x97427431; ++ else ++#endif ++ pRegToSet = RegToSet_Normal; // 0xb972a841; ++ ++ FactorToSet = *((u8 *)val); ++ if(FactorToSet <= 3) ++ { ++ FactorToSet = (1<<(FactorToSet + 2)); ++ if(FactorToSet>0xf) ++ FactorToSet = 0xf; ++ ++ for(index=0; index<4; index++) ++ { ++ if((pRegToSet[index] & 0xf0) > (FactorToSet<<4)) ++ pRegToSet[index] = (pRegToSet[index] & 0x0f) | (FactorToSet<<4); ++ ++ if((pRegToSet[index] & 0x0f) > FactorToSet) ++ pRegToSet[index] = (pRegToSet[index] & 0xf0) | (FactorToSet); ++ ++ rtw_write8(Adapter, (REG_AGGLEN_LMT+index), pRegToSet[index]); ++ } ++ ++ //RT_TRACE(COMP_MLME, DBG_LOUD, ("Set HW_VAR_AMPDU_FACTOR: %#x\n", FactorToSet)); ++ } ++ } ++ break; ++ case HW_VAR_RXDMA_AGG_PG_TH: ++ #ifdef CONFIG_USB_RX_AGGREGATION ++ { ++ u8 threshold = *((u8 *)val); ++ if( threshold == 0) ++ { ++ ++ threshold = pHalData->UsbRxAggPageCount; ++ } ++ rtw_write8(Adapter, REG_RXDMA_AGG_PG_TH, threshold); ++ } ++ #endif ++ break; ++ case HW_VAR_SET_RPWM: ++ rtw_write8(Adapter, REG_USB_HRPWM, *((u8 *)val)); ++ break; ++ case HW_VAR_H2C_FW_PWRMODE: ++ { ++ u8 psmode = (*(u8 *)val); ++ ++ // Forece leave RF low power mode for 1T1R to prevent conficting setting in Fw power ++ // saving sequence. 2010.06.07. Added by tynli. Suggested by SD3 yschang. ++ if( (psmode != PS_MODE_ACTIVE) && (!IS_92C_SERIAL(pHalData->VersionID))) ++ { ++ rtl8192c_dm_RF_Saving(Adapter, _TRUE); ++ } ++ rtl8192c_set_FwPwrMode_cmd(Adapter, psmode); ++ } ++ break; ++ case HW_VAR_H2C_FW_JOINBSSRPT: ++ { ++ u8 mstatus = (*(u8 *)val); ++ rtl8192c_set_FwJoinBssReport_cmd(Adapter, mstatus); ++ } ++ break; ++#ifdef CONFIG_P2P ++ case HW_VAR_H2C_FW_P2P_PS_OFFLOAD: ++ { ++ u8 p2p_ps_state = (*(u8 *)val); ++ rtl8192c_set_p2p_ps_offload_cmd(Adapter, p2p_ps_state); ++ } ++ break; ++#endif //CONFIG_P2P ++#ifdef CONFIG_TDLS ++ case HW_VAR_TDLS_WRCR: ++ rtw_write32(Adapter, REG_RCR, rtw_read32(Adapter, REG_RCR)&(~ BIT(6) )); ++ break; ++ case HW_VAR_TDLS_INIT_CH_SEN: ++ { ++ rtw_write32(Adapter, REG_RCR, rtw_read32(Adapter, REG_RCR)&(~ BIT(6) )&(~ BIT(7) )); ++ rtw_write16(Adapter, REG_RXFLTMAP2,0xffff); ++ ++ //disable update TSF ++ rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)|BIT(4)); ++ } ++ break; ++ case HW_VAR_TDLS_DONE_CH_SEN: ++ { ++ //enable update TSF ++ rtw_write8(Adapter, REG_BCN_CTRL, rtw_read8(Adapter, REG_BCN_CTRL)&(~ BIT(4))); ++ rtw_write32(Adapter, REG_RCR, rtw_read32(Adapter, REG_RCR)|(BIT(7) )); ++ } ++ break; ++ case HW_VAR_TDLS_RS_RCR: ++ rtw_write32(Adapter, REG_RCR, rtw_read32(Adapter, REG_RCR)|(BIT(6))); ++ break; ++#endif //CONFIG_TDLS ++ case HW_VAR_INITIAL_GAIN: ++ { ++ DIG_T *pDigTable = &pdmpriv->DM_DigTable; ++ u32 rx_gain = ((u32 *)(val))[0]; ++ ++ if(rx_gain == 0xff){//restore rx gain ++ pDigTable->CurIGValue = pDigTable->BackupIGValue; ++ rtw_write8(Adapter,rOFDM0_XAAGCCore1, pDigTable->CurIGValue); ++ rtw_write8(Adapter,rOFDM0_XBAGCCore1, pDigTable->CurIGValue); ++ } ++ else{ ++ pDigTable->BackupIGValue = pDigTable->CurIGValue; ++ PHY_SetBBReg(Adapter, rOFDM0_XAAGCCore1, 0x7f,rx_gain ); ++ PHY_SetBBReg(Adapter, rOFDM0_XBAGCCore1, 0x7f,rx_gain); ++ pDigTable->CurIGValue = rx_gain; ++ } ++ } ++ break; ++ case HW_VAR_TRIGGER_GPIO_0: ++ rtl8192cu_trigger_gpio_0(Adapter); ++ break; ++#ifdef CONFIG_BT_COEXIST ++ case HW_VAR_BT_SET_COEXIST: ++ { ++ u8 bStart = (*(u8 *)val); ++ rtl8192c_set_dm_bt_coexist(Adapter, bStart); ++ } ++ break; ++ case HW_VAR_BT_ISSUE_DELBA: ++ { ++ u8 dir = (*(u8 *)val); ++ rtl8192c_issue_delete_ba(Adapter, dir); ++ } ++ break; ++#endif ++#ifdef CONFIG_SW_ANTENNA_DIVERSITY ++ ++ case HW_VAR_ANTENNA_DIVERSITY_LINK: ++ SwAntDivRestAfterLink8192C(Adapter); ++ break; ++ case HW_VAR_ANTENNA_DIVERSITY_SELECT: ++ { ++ u8 Optimum_antenna = (*(u8 *)val); ++ //switch antenna to Optimum_antenna ++ // DBG_8192C("==> HW_VAR_ANTENNA_DIVERSITY_SELECT , Ant_(%s)\n",(Optimum_antenna==2)?"A":"B"); ++ if(pHalData->CurAntenna != Optimum_antenna) ++ { ++ PHY_SetBBReg(Adapter, rFPGA0_XA_RFInterfaceOE, 0x300, Optimum_antenna); ++ pHalData->CurAntenna = Optimum_antenna ; ++ //DBG_8192C("==> HW_VAR_ANTENNA_DIVERSITY_SELECT , Ant_(%s)\n",(Optimum_antenna==2)?"A":"B"); ++ } ++ } ++ break; ++#endif ++ case HW_VAR_EFUSE_BYTES: // To set EFUE total used bytes, added by Roger, 2008.12.22. ++ pHalData->EfuseUsedBytes = *((u16 *)val); ++ break; ++ case HW_VAR_FIFO_CLEARN_UP: ++ { ++ #define RW_RELEASE_EN BIT18 ++ #define RXDMA_IDLE BIT17 ++ ++ struct pwrctrl_priv *pwrpriv = &Adapter->pwrctrlpriv; ++ u8 trycnt = 100; ++ ++ //pause tx ++ rtw_write8(Adapter,REG_TXPAUSE,0xff); ++ ++ //keep sn ++ Adapter->xmitpriv.nqos_ssn = rtw_read16(Adapter,REG_NQOS_SEQ); ++ ++ if(pwrpriv->bkeepfwalive != _TRUE) ++ { ++ //RX DMA stop ++ rtw_write32(Adapter,REG_RXPKT_NUM,(rtw_read32(Adapter,REG_RXPKT_NUM)|RW_RELEASE_EN)); ++ do{ ++ if(!(rtw_read32(Adapter,REG_RXPKT_NUM)&RXDMA_IDLE)) ++ break; ++ }while(trycnt--); ++ if(trycnt ==0) ++ DBG_8192C("Stop RX DMA failed...... \n"); ++ ++ //RQPN Load 0 ++ rtw_write16(Adapter,REG_RQPN_NPQ,0x0); ++ rtw_write32(Adapter,REG_RQPN,0x80000000); ++ rtw_mdelay_os(10); ++ } ++ } ++ break; ++ case HW_VAR_WOWLAN: ++#ifdef CONFIG_WOWLAN ++ { ++ struct wowlan_ioctl_param *poidparam; ++ ++ int res; ++ ++ poidparam = (struct wowlan_ioctl_param *)val; ++ switch (poidparam->subcode){ ++ case WOWLAN_PATTERN_MATCH: ++ //Turn on the Pattern Match feature ++ DBG_8192C("\n PATTERN_MATCH poidparam->subcode_value=%d\n",poidparam->subcode_value); ++ if(poidparam->subcode_value==1){ ++ //rtw_write8(Adapter, REG_WOW_CTRL, (rtw_read8(Adapter, REG_WOW_CTRL)|BIT(1))); ++ Adapter->pwrctrlpriv.wowlan_pattern=_TRUE; ++ DBG_8192C("%s Adapter->pwrctrlpriv.wowlan_pattern=%x\n",__FUNCTION__,Adapter->pwrctrlpriv.wowlan_pattern); ++ } ++ else{ ++ //rtw_write8(Adapter, REG_WOW_CTRL, (rtw_read8(Adapter, REG_WOW_CTRL)&~BIT(1))); ++ Adapter->pwrctrlpriv.wowlan_pattern=_FALSE; ++ } ++ break; ++ case WOWLAN_MAGIC_PACKET: ++ //Turn on the Magic Packet feature ++ DBG_8192C("\n MAGIC_PACKET poidparam->subcode_value=%d\n",poidparam->subcode_value); ++ if(poidparam->subcode_value==1){ ++ //rtw_write8(Adapter, REG_WOW_CTRL, (rtw_read8(Adapter, REG_WOW_CTRL)|BIT(2))); ++ Adapter->pwrctrlpriv.wowlan_magic=_TRUE; ++ DBG_8192C("%s Adapter->pwrctrlpriv.wowlan_magic=%x\n",__FUNCTION__,Adapter->pwrctrlpriv.wowlan_magic); ++ } ++ else{ ++ //rtw_write8(Adapter, REG_WOW_CTRL, (rtw_read8(Adapter, REG_WOW_CTRL)&~BIT(2))); ++ Adapter->pwrctrlpriv.wowlan_magic=_FALSE; ++ } ++ break; ++ case WOWLAN_UNICAST: ++ //Turn on the Unicast wakeup feature ++ if(poidparam->subcode_value==1){ ++ //rtw_write8(Adapter, REG_WOW_CTRL, (rtw_read8(Adapter, REG_WOW_CTRL)|BIT(3))); ++ Adapter->pwrctrlpriv.wowlan_unicast=_TRUE; ++ } ++ else{ ++ //rtw_write8(Adapter, REG_WOW_CTRL, (rtw_read8(Adapter, REG_WOW_CTRL)&~BIT(3))); ++ Adapter->pwrctrlpriv.wowlan_unicast=_FALSE; ++ DBG_8192C("%s Adapter->pwrctrlpriv.wowlan_unicast=%x\n",__FUNCTION__,Adapter->pwrctrlpriv.wowlan_unicast); ++ } ++ break; ++ case WOWLAN_SET_PATTERN: ++ //Setting the Pattern for wowlan ++ res=rtw_wowlan_set_pattern(Adapter,poidparam->pattern); ++ if(res) ++ DBG_8192C("rtw_wowlan_set_pattern retern value=0x%x",res); ++ break; ++ case WOWLAN_DUMP_REG: ++ //dump the WKFMCAM and WOW_CTRL register ++ /*DBG_8192C("\n\n\n\n rtw_wowlan_ctrl: WOW_CTRL=0x%x \n",rtw_read8(Adapter, REG_WOW_CTRL)); ++ DBG_8192C("print WKFMCAM index =%d ",poidparam->data[0]); ++ { int cmd=0,offset=0; ++ for(offset=0;offset<5;offset++){ ++ cmd=BIT(31)|(poidparam->data[0]+offset); ++ rtw_write32(Adapter, REG_WKFMCAM_CMD, cmd); ++ DBG_8192C("offset[%d]=0x%.8x ",offset,rtw_read32(Adapter, REG_WKFMCAM_RWD)); ++ DBG_8192C("offset[%d]=MSB 0x%x:0x%x:0x%x:0x%x ",offset,rtw_read8(Adapter, REG_WKFMCAM_RWD+3),rtw_read8(Adapter, REG_WKFMCAM_RWD+2),rtw_read8(Adapter, REG_WKFMCAM_RWD+1),rtw_read8(Adapter, REG_WKFMCAM_RWD)); ++ } ++ }*/ ++ ++ break; ++ case WOWLAN_ENABLE: ++ SetFwRelatedForWoWLAN8192CU(Adapter, _TRUE); ++ //Set Pattern ++ if(Adapter->pwrctrlpriv.wowlan_pattern==_TRUE) ++ rtw_wowlan_reload_pattern(Adapter); ++ rtl8192c_set_wowlan_cmd(Adapter); ++ rtw_write8(Adapter, 0x6, rtw_read8(Adapter, 0x6)|BIT(3)); ++ rtw_msleep_os(10); ++ //DBG_8192C(" \n REG_WOW_CTRL=0x%x \n",rtw_read8(Adapter, REG_WOW_CTRL)); ++// if(rtw_read8(Adapter, REG_WOW_CTRL)==0) ++// rtw_write8(Adapter, REG_WOW_CTRL, (rtw_read8(Adapter, REG_WOW_CTRL)|BIT(1)|BIT(2)|BIT(3))); ++ //DBG_8192C(" \n REG_WOW_CTRL=0x%x \n",rtw_read8(Adapter, REG_WOW_CTRL)); ++ break; ++ ++ case WOWLAN_DISABLE: ++ Adapter->pwrctrlpriv.wowlan_mode=_FALSE; ++ rtl8192c_set_wowlan_cmd(Adapter); ++ rtw_msleep_os(10); ++ break; ++ ++ case WOWLAN_STATUS: ++ poidparam->wakeup_reason = rtw_read8(Adapter, REG_WOWLAN_REASON); ++ DBG_8192C("wake on wlan reason 0x%02x\n", poidparam->wakeup_reason); ++ break; ++ ++ default: ++ break; ++ } ++ if (Adapter->pwrctrlpriv.wowlan_unicast||Adapter->pwrctrlpriv.wowlan_magic || Adapter->pwrctrlpriv.wowlan_pattern) ++ Adapter->pwrctrlpriv.wowlan_mode =_TRUE; ++ else ++ Adapter->pwrctrlpriv.wowlan_mode =_FALSE; ++ } ++ ++ break; ++#endif //CONFIG_WOWLAN ++ default: ++ break; ++ } ++ ++_func_exit_; ++} ++ ++void GetHwReg8192CU(PADAPTER Adapter, u8 variable, u8* val) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ ++_func_enter_; ++ ++ switch(variable) ++ { ++ case HW_VAR_BASIC_RATE: ++ *((u16 *)(val)) = pHalData->BasicRateSet; ++ case HW_VAR_TXPAUSE: ++ val[0] = rtw_read8(Adapter, REG_TXPAUSE); ++ break; ++ case HW_VAR_TX_BCN_DONE: ++ { ++ u32 xmitbcnDown; ++ xmitbcnDown= rtw_read32(Adapter, REG_TDECTRL); ++ if(xmitbcnDown & BCN_VALID ){ ++ rtw_write32(Adapter,REG_TDECTRL, xmitbcnDown | BCN_VALID ); // write 1 to clear, Clear by sw ++ val[0] = _TRUE; ++ } ++ } ++ break; ++ case HW_VAR_DM_FLAG: ++ val[0] = pHalData->dmpriv.DMFlag; ++ break; ++ case HW_VAR_RF_TYPE: ++ val[0] = pHalData->rf_type; ++ break; ++ case HW_VAR_FWLPS_RF_ON: ++ { ++ //When we halt NIC, we should check if FW LPS is leave. ++ u32 valRCR; ++ ++ if(Adapter->pwrctrlpriv.rf_pwrstate == rf_off) ++ { ++ // If it is in HW/SW Radio OFF or IPS state, we do not check Fw LPS Leave, ++ // because Fw is unload. ++ val[0] = _TRUE; ++ } ++ else ++ { ++ valRCR = rtw_read32(Adapter, REG_RCR); ++ valRCR &= 0x00070000; ++ if(valRCR) ++ val[0] = _FALSE; ++ else ++ val[0] = _TRUE; ++ } ++ } ++ break; ++#ifdef CONFIG_ANTENNA_DIVERSITY ++ case HW_VAR_CURRENT_ANTENNA: ++ val[0] = pHalData->CurAntenna; ++ break; ++#endif ++ case HW_VAR_EFUSE_BYTES: // To get EFUE total used bytes, added by Roger, 2008.12.22. ++ *((u16 *)(val)) = pHalData->EfuseUsedBytes; ++ break; ++ default: ++ break; ++ } ++ ++_func_exit_; ++} ++ ++// ++// Description: ++// Query setting of specified variable. ++// ++u8 ++GetHalDefVar8192CUsb( ++ IN PADAPTER Adapter, ++ IN HAL_DEF_VARIABLE eVariable, ++ IN PVOID pValue ++ ) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ u8 bResult = _TRUE; ++ ++ switch(eVariable) ++ { ++ case HAL_DEF_UNDERCORATEDSMOOTHEDPWDB: ++ *((int *)pValue) = pHalData->dmpriv.UndecoratedSmoothedPWDB; ++ break; ++ case HAL_DEF_IS_SUPPORT_ANT_DIV: ++ #ifdef CONFIG_ANTENNA_DIVERSITY ++ *((u8 *)pValue) = (IS_92C_SERIAL(pHalData->VersionID) ||(pHalData->AntDivCfg==0))?_FALSE:_TRUE; ++ #endif ++ break; ++ case HAL_DEF_CURRENT_ANTENNA: ++ #ifdef CONFIG_ANTENNA_DIVERSITY ++ *(( u8*)pValue) = pHalData->CurAntenna; ++ #endif ++ break; ++ case HAL_DEF_DRVINFO_SZ: ++ *(( u32*)pValue) = DRVINFO_SZ; ++ break; ++ case HAL_DEF_MAX_RECVBUF_SZ: ++ *(( u32*)pValue) = MAX_RECVBUF_SZ; ++ break; ++ case HAL_DEF_RX_PACKET_OFFSET: ++ *(( u32*)pValue) = RXDESC_SIZE + DRVINFO_SZ; ++ break; ++ case HAL_DEF_DBG_DUMP_RXPKT: ++ *(( u8*)pValue) = pHalData->bDumpRxPkt; ++ break; ++ case HAL_DEF_DBG_DM_FUNC: ++ *(( u8*)pValue) = pHalData->dmpriv.DMFlag; ++ break; ++ default: ++ //RT_TRACE(COMP_INIT, DBG_WARNING, ("GetHalDefVar8192CUsb(): Unkown variable: %d!\n", eVariable)); ++ bResult = _FALSE; ++ break; ++ } ++ ++ return bResult; ++} ++ ++ ++ ++ ++// ++// Description: ++// Change default setting of specified variable. ++// ++u8 ++SetHalDefVar8192CUsb( ++ IN PADAPTER Adapter, ++ IN HAL_DEF_VARIABLE eVariable, ++ IN PVOID pValue ++ ) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter); ++ u8 bResult = _TRUE; ++ ++ switch(eVariable) ++ { ++ case HAL_DEF_DBG_DUMP_RXPKT: ++ pHalData->bDumpRxPkt = *(( u8*)pValue); ++ break; ++ case HAL_DEF_DBG_DM_FUNC: ++ { ++ u8 dm_func = *(( u8*)pValue); ++ struct dm_priv *pdmpriv = &pHalData->dmpriv; ++ ++ if(dm_func == 0){ //disable all dynamic func ++ pdmpriv->DMFlag = DYNAMIC_FUNC_DISABLE; ++ DBG_8192C("==> Disable all dynamic function...\n"); ++ } ++ else if(dm_func == 1){//disable DIG ++ pdmpriv->DMFlag &= (~DYNAMIC_FUNC_DIG); ++ DBG_8192C("==> Disable DIG...\n"); ++ } ++ else if(dm_func == 2){//disable High power ++ pdmpriv->DMFlag &= (~DYNAMIC_FUNC_HP); ++ } ++ else if(dm_func == 3){//disable tx power tracking ++ pdmpriv->DMFlag &= (~DYNAMIC_FUNC_SS); ++ DBG_8192C("==> Disable tx power tracking...\n"); ++ } ++ else if(dm_func == 4){//disable BT coexistence ++ pdmpriv->DMFlag &= (~DYNAMIC_FUNC_BT); ++ } ++ else if(dm_func == 5){//disable antenna diversity ++ pdmpriv->DMFlag &= (~DYNAMIC_FUNC_ANT_DIV); ++ } ++ else if(dm_func == 6){//turn on all dynamic func ++ if(!(pdmpriv->DMFlag & DYNAMIC_FUNC_DIG)) ++ { ++ struct dm_priv *pdmpriv = &pHalData->dmpriv; ++ DIG_T *pDigTable = &pdmpriv->DM_DigTable; ++ pDigTable->PreIGValue = rtw_read8(Adapter,0xc50); ++ } ++ ++ pdmpriv->DMFlag |= (DYNAMIC_FUNC_DIG|DYNAMIC_FUNC_HP|DYNAMIC_FUNC_SS| ++ DYNAMIC_FUNC_BT|DYNAMIC_FUNC_ANT_DIV) ; ++ DBG_8192C("==> Turn on all dynamic function...\n"); ++ } ++ } ++ break; ++ default: ++ //RT_TRACE(COMP_INIT, DBG_TRACE, ("SetHalDefVar819xUsb(): Unkown variable: %d!\n", eVariable)); ++ bResult = _FALSE; ++ break; ++ } ++ ++ return bResult; ++} ++ ++u32 _update_92cu_basic_rate(_adapter *padapter, unsigned int mask) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); ++#ifdef CONFIG_BT_COEXIST ++ struct btcoexist_priv *pbtpriv = &(pHalData->bt_coexist); ++#endif ++ unsigned int BrateCfg = 0; ++ ++#ifdef CONFIG_BT_COEXIST ++ if( (pbtpriv->BT_Coexist) && (pbtpriv->BT_CoexistType == BT_CSR_BC4) ) ++ { ++ BrateCfg = mask & 0x151; ++ //DBG_8192C("BT temp disable cck 2/5.5/11M, (0x%x = 0x%x)\n", REG_RRSR, BrateCfg & 0x151); ++ } ++ else ++#endif ++ { ++ if(pHalData->VersionID != VERSION_TEST_CHIP_88C) ++ BrateCfg = mask & 0x15F; ++ else //for 88CU 46PING setting, Disable CCK 2M, 5.5M, Others must tuning ++ BrateCfg = mask & 0x159; ++ } ++ ++ BrateCfg |= 0x01; // default enable 1M ACK rate ++ ++ return BrateCfg; ++} ++ ++void _update_response_rate(_adapter *padapter,unsigned int mask) ++{ ++ u8 RateIndex = 0; ++ // Set RRSR rate table. ++ rtw_write8(padapter, REG_RRSR, mask&0xff); ++ rtw_write8(padapter,REG_RRSR+1, (mask>>8)&0xff); ++ ++ // Set RTS initial rate ++ while(mask > 0x1) ++ { ++ mask = (mask>> 1); ++ RateIndex++; ++ } ++ rtw_write8(padapter, REG_INIRTS_RATE_SEL, RateIndex); ++} ++ ++void UpdateHalRAMask8192CUsb(PADAPTER padapter, u32 mac_id) ++{ ++ //volatile unsigned int result; ++ u8 init_rate=0; ++ u8 networkType, raid; ++ u32 mask; ++ u8 shortGIrate = _FALSE; ++ int supportRateNum = 0; ++ struct sta_info *psta; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); ++ struct dm_priv *pdmpriv = &pHalData->dmpriv; ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ WLAN_BSSID_EX *cur_network = &(pmlmeinfo->network); ++#ifdef CONFIG_BT_COEXIST ++ struct btcoexist_priv *pbtpriv = &(pHalData->bt_coexist); ++#endif ++ ++ if (mac_id >= NUM_STA) //CAM_SIZE ++ { ++ return; ++ } ++ ++ psta = pmlmeinfo->FW_sta_info[mac_id].psta; ++ if(psta == NULL) ++ { ++ return; ++ } ++ ++ switch (mac_id) ++ { ++ case 0:// for infra mode ++ supportRateNum = rtw_get_rateset_len(cur_network->SupportedRates); ++ networkType = judge_network_type(padapter, cur_network->SupportedRates, supportRateNum) & 0xf; ++ //pmlmeext->cur_wireless_mode = networkType; ++ raid = networktype_to_raid(networkType); ++ ++ mask = update_supported_rate(cur_network->SupportedRates, supportRateNum); ++ mask |= (pmlmeinfo->HT_enable)? update_MSC_rate(&(pmlmeinfo->HT_caps)): 0; ++ mask |= ((raid<<28)&0xf0000000); ++ ++ if (support_short_GI(padapter, &(pmlmeinfo->HT_caps))) ++ { ++ shortGIrate = _TRUE; ++ } ++ ++ break; ++ ++ case 1://for broadcast/multicast ++ supportRateNum = rtw_get_rateset_len(pmlmeinfo->FW_sta_info[mac_id].SupportedRates); ++ if(pmlmeext->cur_wireless_mode & WIRELESS_11B) ++ networkType = WIRELESS_11B; ++ else ++ networkType = WIRELESS_11G; ++ raid = networktype_to_raid(networkType); ++ ++ mask = update_basic_rate(cur_network->SupportedRates, supportRateNum); ++ mask |= ((raid<<28)&0xf0000000); ++ ++ break; ++ ++ default: //for each sta in IBSS ++ supportRateNum = rtw_get_rateset_len(pmlmeinfo->FW_sta_info[mac_id].SupportedRates); ++ networkType = judge_network_type(padapter, pmlmeinfo->FW_sta_info[mac_id].SupportedRates, supportRateNum) & 0xf; ++ //pmlmeext->cur_wireless_mode = networkType; ++ raid = networktype_to_raid(networkType); ++ ++ mask = update_supported_rate(cur_network->SupportedRates, supportRateNum); ++ mask |= ((raid<<28)&0xf0000000); ++ ++ //todo: support HT in IBSS ++ ++ break; ++ } ++ ++#ifdef CONFIG_BT_COEXIST ++ if( (pbtpriv->BT_Coexist) && ++ (pbtpriv->BT_CoexistType == BT_CSR_BC4) && ++ (pbtpriv->BT_CUR_State) && ++ (pbtpriv->BT_Ant_isolation) && ++ ((pbtpriv->BT_Service==BT_SCO)|| ++ (pbtpriv->BT_Service==BT_Busy)) ) ++ mask &= 0xffffcfc0; ++ else ++#endif ++ mask &=0xffffffff; ++ ++ ++ init_rate = get_highest_rate_idx(mask)&0x3f; ++ ++ if(pHalData->fw_ractrl == _TRUE) ++ { ++ u8 arg = 0; ++ ++ //arg = (cam_idx-4)&0x1f;//MACID ++ arg = mac_id&0x1f;//MACID ++ ++ arg |= BIT(7); ++ ++ if (shortGIrate==_TRUE) ++ arg |= BIT(5); ++ ++ DBG_871X("update raid entry, mask=0x%x, arg=0x%x\n", mask, arg); ++ psta->ra_mask=mask; ++#ifdef CONFIG_INTEL_PROXIM ++ if(padapter->proximity.proxim_on ==_TRUE){ ++ arg &= ~BIT(6); ++ } ++ else { ++ arg |= BIT(6); ++ } ++#endif //CONFIG_INTEL_PROXIM ++ rtl8192c_set_raid_cmd(padapter, mask, arg); ++ ++ } ++ else ++ { ++ if (shortGIrate==_TRUE) ++ init_rate |= BIT(6); ++ ++ rtw_write8(padapter, (REG_INIDATA_RATE_SEL+mac_id), init_rate); ++ } ++ ++ ++ //set ra_id ++ psta->raid = raid; ++ psta->init_rate = init_rate; ++ ++ //set correct initial date rate for each mac_id ++ pdmpriv->INIDATA_RATE[mac_id] = init_rate; ++} ++ ++void SetBeaconRelatedRegisters8192CUsb(PADAPTER padapter) ++{ ++ u32 value32; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); ++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ ++ //reset TSF, enable update TSF, correcting TSF On Beacon ++ ++ //REG_BCN_INTERVAL ++ //REG_BCNDMATIM ++ //REG_ATIMWND ++ //REG_TBTT_PROHIBIT ++ //REG_DRVERLYINT ++ //REG_BCN_MAX_ERR ++ //REG_BCNTCFG //(0x510) ++ //REG_DUAL_TSF_RST ++ //REG_BCN_CTRL //(0x550) ++ ++ //BCN interval ++ rtw_write16(padapter, REG_BCN_INTERVAL, pmlmeinfo->bcn_interval); ++ rtw_write8(padapter, REG_ATIMWND, 0x02);// 2ms ++ ++ _InitBeaconParameters(padapter); ++ ++ rtw_write8(padapter, REG_SLOT, 0x09); ++ ++ value32 =rtw_read32(padapter, REG_TCR); ++ value32 &= ~TSFRST; ++ rtw_write32(padapter, REG_TCR, value32); ++ ++ value32 |= TSFRST; ++ rtw_write32(padapter, REG_TCR, value32); ++ ++ // NOTE: Fix test chip's bug (about contention windows's randomness) ++ rtw_write8(padapter, REG_RXTSF_OFFSET_CCK, 0x50); ++ rtw_write8(padapter, REG_RXTSF_OFFSET_OFDM, 0x50); ++ ++ _BeaconFunctionEnable(padapter, _TRUE, _TRUE); ++ ++ ResumeTxBeacon(padapter); ++ ++ //rtw_write8(padapter, 0x422, rtw_read8(padapter, 0x422)|BIT(6)); ++ ++ //rtw_write8(padapter, 0x541, 0xff); ++ ++ //rtw_write8(padapter, 0x542, rtw_read8(padapter, 0x541)|BIT(0)); ++ ++ rtw_write8(padapter, REG_BCN_CTRL, rtw_read8(padapter, REG_BCN_CTRL)|BIT(1)); ++ ++} ++ ++static void rtl8192cu_init_default_value(_adapter * padapter) ++{ ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); ++ struct pwrctrl_priv *pwrctrlpriv = &padapter->pwrctrlpriv; ++ struct dm_priv *pdmpriv = &pHalData->dmpriv; ++ u8 i; ++ ++ //init default value ++ pHalData->fw_ractrl = _FALSE; ++ pHalData->bIQKInitialized = _FALSE; ++ if(!pwrctrlpriv->bkeepfwalive) ++ pHalData->LastHMEBoxNum = 0; ++ ++ pHalData->bIQKInitialized = _FALSE; ++ //init dm default value ++ pdmpriv->TM_Trigger = 0; ++ pdmpriv->binitialized = _FALSE; ++ pdmpriv->prv_traffic_idx = 3; ++ pdmpriv->initialize = 0; ++ ++ pdmpriv->ThermalValue_HP_index = 0; ++ for(i = 0; i < HP_THERMAL_NUM; i++) ++ pdmpriv->ThermalValue_HP[i] = 0; ++} ++static u8 rtl8192cu_ps_func(PADAPTER Adapter,HAL_INTF_PS_FUNC efunc_id, u8 *val) ++{ ++ u8 bResult = _TRUE; ++ switch(efunc_id){ ++ ++ #if defined(CONFIG_AUTOSUSPEND) && defined(SUPPORT_HW_RFOFF_DETECTED) ++ case HAL_USB_SELECT_SUSPEND: ++ { ++ u8 bfwpoll = *(( u8*)val); ++ rtl8192c_set_FwSelectSuspend_cmd(Adapter,bfwpoll ,500);//note fw to support hw power down ping detect ++ } ++ break; ++ #endif //CONFIG_AUTOSUSPEND && SUPPORT_HW_RFOFF_DETECTED ++ ++ default: ++ break; ++ } ++ return bResult; ++} ++void rtl8192cu_set_hal_ops(_adapter * padapter) ++{ ++ struct hal_ops *pHalFunc = &padapter->HalFunc; ++ ++_func_enter_; ++ ++ padapter->HalData = rtw_zmalloc(sizeof(HAL_DATA_TYPE)); ++ if(padapter->HalData == NULL){ ++ DBG_8192C("cant not alloc memory for HAL DATA \n"); ++ } ++ //_rtw_memset(padapter->HalData, 0, sizeof(HAL_DATA_TYPE)); ++ ++ pHalFunc->hal_init = &rtl8192cu_hal_init; ++ pHalFunc->hal_deinit = &rtl8192cu_hal_deinit; ++ ++ //pHalFunc->free_hal_data = &rtl8192c_free_hal_data; ++ ++ pHalFunc->inirp_init = &rtl8192cu_inirp_init; ++ pHalFunc->inirp_deinit = &rtl8192cu_inirp_deinit; ++ ++ pHalFunc->init_xmit_priv = &rtl8192cu_init_xmit_priv; ++ pHalFunc->free_xmit_priv = &rtl8192cu_free_xmit_priv; ++ ++ pHalFunc->init_recv_priv = &rtl8192cu_init_recv_priv; ++ pHalFunc->free_recv_priv = &rtl8192cu_free_recv_priv; ++#ifdef CONFIG_SW_LED ++ pHalFunc->InitSwLeds = &rtl8192cu_InitSwLeds; ++ pHalFunc->DeInitSwLeds = &rtl8192cu_DeInitSwLeds; ++#else //case of hw led or no led ++ pHalFunc->InitSwLeds = NULL; ++ pHalFunc->DeInitSwLeds = NULL; ++#endif//CONFIG_SW_LED ++ ++ //pHalFunc->dm_init = &rtl8192c_init_dm_priv; ++ //pHalFunc->dm_deinit = &rtl8192c_deinit_dm_priv; ++ ++ pHalFunc->init_default_value = &rtl8192cu_init_default_value; ++ pHalFunc->intf_chip_configure = &rtl8192cu_interface_configure; ++ pHalFunc->read_adapter_info = &ReadAdapterInfo8192CU; ++ ++ //pHalFunc->set_bwmode_handler = &PHY_SetBWMode8192C; ++ //pHalFunc->set_channel_handler = &PHY_SwChnl8192C; ++ ++ //pHalFunc->hal_dm_watchdog = &rtl8192c_HalDmWatchDog; ++ ++ pHalFunc->SetHwRegHandler = &SetHwReg8192CU; ++ pHalFunc->GetHwRegHandler = &GetHwReg8192CU; ++ pHalFunc->GetHalDefVarHandler = &GetHalDefVar8192CUsb; ++ pHalFunc->SetHalDefVarHandler = &SetHalDefVar8192CUsb; ++ ++ pHalFunc->UpdateRAMaskHandler = &UpdateHalRAMask8192CUsb; ++ pHalFunc->SetBeaconRelatedRegistersHandler = &SetBeaconRelatedRegisters8192CUsb; ++ ++ //pHalFunc->Add_RateATid = &rtl8192c_Add_RateATid; ++ ++//#ifdef CONFIG_SW_ANTENNA_DIVERSITY ++ //pHalFunc->SwAntDivBeforeLinkHandler = &SwAntDivBeforeLink8192C; ++ //pHalFunc->SwAntDivCompareHandler = &SwAntDivCompare8192C; ++//#endif ++ ++ pHalFunc->hal_xmit = &rtl8192cu_hal_xmit; ++ pHalFunc->mgnt_xmit = &rtl8192cu_mgnt_xmit; ++ ++ //pHalFunc->read_bbreg = &rtl8192c_PHY_QueryBBReg; ++ //pHalFunc->write_bbreg = &rtl8192c_PHY_SetBBReg; ++ //pHalFunc->read_rfreg = &rtl8192c_PHY_QueryRFReg; ++ //pHalFunc->write_rfreg = &rtl8192c_PHY_SetRFReg; ++ ++#ifdef CONFIG_HOSTAPD_MLME ++ pHalFunc->hostap_mgnt_xmit_entry = &rtl8192cu_hostap_mgnt_xmit_entry; ++#endif ++ pHalFunc->interface_ps_func = &rtl8192cu_ps_func; ++ ++ rtl8192c_set_hal_ops(pHalFunc); ++_func_exit_; ++ ++} ++ +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/hal/rtl8192c/usb/usb_ops_ce.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/hal/rtl8192c/usb/usb_ops_ce.c 2013-07-26 19:36:06.000000000 +0000 +@@ -0,0 +1,1208 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ++******************************************************************************/ ++#define _HCI_OPS_OS_C_ ++ ++#include ++#include ++#include ++#include ++ ++#ifndef PLATFORM_OS_CE ++ #error "PLATFORM_OS_CE shall be set \n" ++#endif ++ ++#ifndef CONFIG_USB_HCI ++ #error "CONFIG_USB_HCI shall be on!\n" ++#endif ++ ++#include ++#include ++ ++#include ++ ++ ++struct zero_bulkout_context ++{ ++ void *pbuf; ++ void *purb; ++ void *pirp; ++ void *padapter; ++}; ++ ++ ++ ++#define PUSB_ERROR LPDWORD ++#define USBD_HALTED(Status) ((ULONG)(Status) >> 30 == 3) ++ ++ ++USB_PIPE ffaddr2pipehdl(struct dvobj_priv *pNdisCEDvice, u32 addr); ++ ++ ++static NTSTATUS usb_async_interrupt_in_complete( LPVOID Context ); ++static NTSTATUS usb_async_interrupt_out_complete( LPVOID Context ); ++ ++DWORD usb_write_port_complete( LPVOID Context ); ++DWORD usb_read_port_complete( LPVOID Context ); ++ ++void usb_read_mem(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *rmem) ++{ ++_func_enter_; ++ RT_TRACE( _module_hci_ops_os_c_, _drv_info_, ("%s(%u)\n",__FUNCTION__, __LINE__)); ++_func_exit_; ++} ++ ++ ++ ++BOOL ++CloseTransferHandle( ++ LPCUSB_FUNCS pUsbFuncs, ++ USB_TRANSFER hTransfer ++ ) ++{ ++ BOOL bRc = TRUE; ++ ++ // This assert may fail on suprise remove, ++ // but should pass during normal I/O. ++ // ASSERT( pUsbFuncs->lpIsTransferComplete(hTransfer) ); ++ ++ // CloseTransfer aborts any pending transfers ++ if ( !pUsbFuncs->lpCloseTransfer(hTransfer) ) { ++ ++ RT_TRACE( _module_hci_ops_os_c_, _drv_err_, ("*** CloseTransfer ERROR:%d ***\n", GetLastError())); ++ bRc = FALSE; ++ } ++ ++ return bRc; ++} ++ ++ ++BOOL ++GetTransferStatus( ++ LPCUSB_FUNCS pUsbFuncs, ++ USB_TRANSFER hTransfer, ++ LPDWORD pBytesTransferred , // OPTIONAL returns number of bytes transferred ++ PUSB_ERROR pUsbError // returns USB error code ++ ) ++{ ++ ++ BOOL bRc = TRUE; ++ ++ if ( pUsbFuncs->lpGetTransferStatus(hTransfer, pBytesTransferred, pUsbError) ) { ++ if ( USB_NO_ERROR != *pUsbError ) { ++ RT_TRACE( _module_hci_ops_os_c_, _drv_err_, ("*** CloseTransfer ERROR:%d ***\n", GetLastError())); ++ RT_TRACE( _module_hci_ops_os_c_, _drv_err_, ("GetTransferStatus (BytesTransferred:%d, UsbError:0x%x)\n", pBytesTransferred?*pBytesTransferred:-1, pUsbError?*pUsbError:-1 )); ++ } ++ } else { ++ RT_TRACE( _module_hci_ops_os_c_, _drv_err_,("*** GetTransferStatus ERROR:%d ***\n", GetLastError())); ++ *pUsbError = USB_CANCELED_ERROR; ++ bRc = FALSE; ++ } ++ ++ return bRc; ++} ++ ++ ++// The driver should never read RxCmd register. We have to set ++// RCR CMDHAT0 (bit6) to append Rx status before the Rx frame. ++// ++// |<-------- pBulkUrb->TransferBufferLength ------------>| ++// +------------------+-------------------+------------+ ++// | Rx status (16 bytes) | Rx frame ..... | CRC(4 bytes) | ++// +------------------+-------------------+------------+ ++// ^ ++// ^pRfd->Buffer.VirtualAddress ++// ++/*! \brief USB RX IRP Complete Routine. ++ @param Context pointer of RT_RFD ++*/ ++u32 usb_read_port(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *rmem) ++{ ++ struct intf_priv *pintfpriv = pintfhdl->pintfpriv; ++ struct dvobj_priv *pdvobj_priv = (struct dvobj_priv*)pintfpriv->intf_dev; ++ _adapter *adapter = (_adapter *)pdvobj_priv->padapter; ++ ++ struct recv_priv *precvpriv = &adapter->recvpriv; ++ ++ struct recv_buf *precvbuf = (struct recv_buf *)rmem; ++ DWORD dwErr = ERROR_SUCCESS ; ++ DWORD dwBytesTransferred = 0 ; ++ USB_TRANSFER hTransfer = NULL; ++ USB_PIPE hPipe; ++ LPCUSB_FUNCS usb_funcs_vp = pdvobj_priv->usb_extension._lpUsbFuncs; ++ ++_func_enter_; ++ RT_TRACE( _module_hci_ops_os_c_, _drv_info_, ("usb_read_port(%u)\n", __LINE__)); ++ ++#if (CONFIG_PWRCTRL == 1) ++ if (adapter->pwrctrlpriv.pnp_bstop_trx) ++ { ++ return _FALSE; ++ } ++#endif ++ ++ if(adapter->bDriverStopped || adapter->bSurpriseRemoved) ++ { ++ RT_TRACE(_module_hci_ops_os_c_, _drv_info_,("usb_read_port:( padapter->bDriverStopped ||padapter->bSurpriseRemoved)!!!\n")); ++ return _FALSE; ++ } ++ ++ if(precvbuf !=NULL) ++ { ++ ++ // get a recv buffer ++ rtl8192cu_init_recvbuf(adapter, precvbuf); ++ ++ ++ ++ _rtw_spinlock(&precvpriv->lock); ++ precvpriv->rx_pending_cnt++; ++ precvbuf->irp_pending = _TRUE; ++ _rtw_spinunlock(&precvpriv->lock); ++ ++ ++ //translate DMA FIFO addr to pipehandle ++ hPipe = ffaddr2pipehdl(pdvobj_priv, addr); ++ ++ ++ RT_TRACE( _module_hci_ops_os_c_, _drv_info_, ("usb_read_port(%u)\n", __LINE__)); ++ ++ precvbuf->usb_transfer_read_port = (*usb_funcs_vp->lpIssueBulkTransfer)( ++ hPipe, ++ usb_read_port_complete, ++ precvbuf, ++ USB_IN_TRANSFER|USB_SHORT_TRANSFER_OK, ++ MAX_RECVBUF_SZ, ++ precvbuf->pbuf, ++ 0); ++ ++ ++ if(precvbuf->usb_transfer_read_port) ++ { ++ ++ // GetTransferStatus(usb_funcs_vp, hTransfer, &dwBytesTransferred,&UsbRc); ++ ++ // CloseTransferHandle(usb_funcs_vp, hTransfer); ++ ++ } ++ else ++ { ++ ++ dwErr = GetLastError(); ++ //RT_TRACE( _module_hci_ops_os_c_, _drv_err_, ("usb_read_port ERROR : %d\n", dwErr)); ++ ++ } ++ ++// if ( USB_NO_ERROR != UsbRc && ERROR_SUCCESS == dwErr) { ++// dwErr = ERROR_GEN_FAILURE; ++// } ++ ++ ++ if ( ERROR_SUCCESS != dwErr ) { ++ ++ SetLastError(dwErr); ++ RT_TRACE( _module_hci_ops_os_c_, _drv_err_, ("usb_read_port ERROR : %d\n", dwErr)); ++ } ++ ++ RT_TRACE( _module_hci_ops_os_c_, _drv_info_, ("-usb_read_port(%u)\n", __LINE__)); ++ ++ } ++ else // if(precvbuf !=NULL) ++ { ++ ++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port:precv_frame ==NULL\n")); ++ } ++ ++ return _TRUE; ++ ++} ++ ++DWORD usb_read_port_complete( PVOID context ) ++{ ++ struct recv_buf *precvbuf = (struct recv_buf *)context; ++ _adapter *adapter = (_adapter *)precvbuf->adapter; ++ struct recv_priv *precvpriv = &adapter->recvpriv; ++ ++ ++ struct intf_hdl *pintfhdl = &adapter->pio_queue->intf; ++ struct intf_priv *pintfpriv = pintfhdl->pintfpriv; ++ struct dvobj_priv *pdvobj_priv = (struct dvobj_priv*)pintfpriv->intf_dev; ++ ++ ++ LPCUSB_FUNCS usb_funcs_vp = pdvobj_priv->usb_extension._lpUsbFuncs; ++ ++ DWORD dwBytesTransferred = 0; ++ DWORD dwErr = USB_CANCELED_ERROR; ++ ++ uint isevt, *pbuf; ++ int fComplete =_FALSE; ++ ++ ++ RT_TRACE( _module_hci_ops_os_c_, _drv_info_, ("usb_read_port_complete(%u)\n", __LINE__)); ++ ++_func_enter_; ++ ++ ++ _rtw_spinlock_ex(&precvpriv->lock); ++ precvbuf->irp_pending=_FALSE; ++ precvpriv->rx_pending_cnt --; ++ _rtw_spinunlock_ex(&precvpriv->lock); ++ ++ ++#if 1 ++ ++ (*usb_funcs_vp->lpGetTransferStatus)(precvbuf->usb_transfer_read_port, &dwBytesTransferred, &dwErr); ++ fComplete = (*usb_funcs_vp->lpIsTransferComplete)(precvbuf->usb_transfer_read_port); ++ if(fComplete!=_TRUE) ++ { ++ RT_TRACE( _module_hci_ops_os_c_, _drv_err_, ("usb_read_port_complete CloseTransfer before complete\n")); ++ } ++ (*usb_funcs_vp->lpCloseTransfer)(precvbuf->usb_transfer_read_port); ++ ++ ++#endif ++ ++ ++ if(USB_NO_ERROR != dwErr) ++ RT_TRACE( _module_hci_ops_os_c_, _drv_err_, ("usb_read_port_complete Fail :%d\n",dwErr)); ++ ++ { ++ ++ if ( dwBytesTransferred > MAX_RECVBUF_SZ || dwBytesTransferred < RXDESC_SIZE ) ++ { ++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_, ++ ("\n usb_read_port_complete: (pbulkurb->TransferBufferLength > MAX_RECVBUF_SZ) || (pbulkurb->TransferBufferLength < RXDESC_SIZE): %d\n",dwBytesTransferred)); ++ rtw_read_port(adapter, precvpriv->ff_hwaddr, 0, (unsigned char *)precvbuf); ++ ++ //usb_read_port(pintfhdl, 0, 0, (unsigned char *)precvframe); ++ } ++ else ++ { ++ precvbuf->transfer_len = dwBytesTransferred; ++ ++ pbuf = (uint*)precvbuf->pbuf; ++ ++ if((isevt = *(pbuf+1)&0x1ff) == 0x1ff) ++ { ++ RT_TRACE(_module_hci_ops_os_c_,_drv_info_, ++ ("\n usb_read_port_complete: get a event\n")); ++ rxcmd_event_hdl(adapter, pbuf);//rx c2h events ++ ++ rtw_read_port(adapter, precvpriv->ff_hwaddr, 0, (unsigned char *)precvbuf); ++ } ++ else ++ { ++ if(recvbuf2recvframe(adapter, precvbuf)==_FAIL)//rx packets ++ { ++ //precvbuf->reuse = _TRUE; ++ rtw_read_port(adapter, precvpriv->ff_hwaddr, 0, (unsigned char *)precvbuf); ++ } ++ } ++ } ++ } ++ ++ RT_TRACE( _module_hci_ops_os_c_, _drv_info_, ("-usb_read_port_complete(%u)\n", __LINE__)); ++ ++_func_exit_; ++ return ERROR_SUCCESS; ++// return STATUS_MORE_PROCESSING_REQUIRED; ++} ++ ++void usb_read_port_cancel(_adapter *padapter){ ++ RT_TRACE( _module_hci_ops_os_c_, _drv_info_, ("usb_read_port_cancel(%u)\n",__FUNCTION__, __LINE__)); ++} ++ ++DWORD usb_write_mem_complete( LPVOID Context ) ++{ ++ int fComplete =_FALSE; ++ DWORD dwBytes = 0; ++ DWORD dwErr = USB_CANCELED_ERROR; ++ ++ _irqL irqL; ++ _list *head; ++ _list *plist; ++ struct io_req *pio_req; ++ struct io_queue *pio_q = (struct io_queue *) Context; ++ struct intf_hdl *pintf = &(pio_q->intf); ++ struct intf_priv *pintfpriv = pintf->pintfpriv; ++ _adapter *padapter = (_adapter *)pintf->adapter; ++ NTSTATUS status = STATUS_SUCCESS; ++ struct xmit_priv * pxmitpriv = &padapter->xmitpriv; ++ ++ struct dvobj_priv * pdvobj_priv = (struct dvobj_priv*)pintfpriv->intf_dev; ++ ++ USB_HANDLE usbHandle = pdvobj_priv->usb_extension._hDevice; ++ LPCUSB_FUNCS usb_funcs_vp = pdvobj_priv->usb_extension._lpUsbFuncs; ++ ++ // get the head from the processing io_queue ++ head = &(pio_q->processing); ++ ++_func_enter_; ++ RT_TRACE( _module_hci_ops_os_c_, _drv_info_, ("+usb_write_mem_complete %p\n", Context)); ++ ++#if 1 ++ _enter_critical_bh(&(pio_q->lock), &irqL); ++ ++ ++ //free irp in processing list... ++ while(rtw_is_list_empty(head) != _TRUE) ++ { ++ plist = get_next(head); ++ rtw_list_delete(plist); ++ pio_req = LIST_CONTAINOR(plist, struct io_req, list); ++ _rtw_up_sema(&pio_req->sema); ++ } ++ ++ _exit_critical_bh(&(pio_q->lock), &irqL); ++#endif ++ ++ ++#if 1 ++ ++ (*usb_funcs_vp->lpGetTransferStatus)(pio_req->usb_transfer_write_mem , &dwBytes, &dwErr); ++ fComplete = (*usb_funcs_vp->lpIsTransferComplete)(pio_req->usb_transfer_write_mem); ++ if(fComplete!=_TRUE) ++ { ++ RT_TRACE( _module_hci_ops_os_c_, _drv_err_, ("usb_write_mem_complete CloseTransfer before complete\n")); ++ } ++ (*usb_funcs_vp->lpCloseTransfer)(pio_req->usb_transfer_write_mem ); ++ ++#endif ++ ++ RT_TRACE( _module_hci_ops_os_c_, _drv_info_, ("-usb_write_mem_complete\n")); ++ ++_func_exit_; ++ ++ ++ return STATUS_MORE_PROCESSING_REQUIRED; ++ ++} ++ ++ ++void usb_write_mem(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *wmem) ++{ ++ ++ NTSTATUS NtStatus = STATUS_SUCCESS; ++ USB_PIPE hPipe; ++ _irqL irqL; ++ ++ int fComplete = _FALSE; ++ DWORD dwBytes = 0; ++ DWORD dwErr = USB_CANCELED_ERROR; ++ ++ ++ struct io_req *pio_req; ++ ++ _adapter *adapter = (_adapter *)pintfhdl->adapter; ++ struct intf_priv *pintfpriv = pintfhdl->pintfpriv; ++ struct dvobj_priv * pdvobj_priv = (struct dvobj_priv*)pintfpriv->intf_dev; ++ ++ ++ struct xmit_priv *pxmitpriv = &adapter->xmitpriv; ++ struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue; ++ ++ LPCUSB_FUNCS usb_funcs_vp = pdvobj_priv->usb_extension._lpUsbFuncs; ++ ++ ++_func_enter_; ++ RT_TRACE( _module_hci_ops_os_c_, _drv_info_, ("usb_write_mem(%u) pintfhdl %p wmem %p\n", __LINE__, pintfhdl, wmem)); ++ ++ // fetch a io_request from the io_queue ++ pio_req = alloc_ioreq(pio_queue); ++ ++ if ((pio_req == NULL)||(adapter->bSurpriseRemoved)) ++ { ++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("async_irp_write32 : pio_req =0x%x adapter->bSurpriseRemoved=0x%x",pio_req,adapter->bSurpriseRemoved )); ++ goto exit; ++ } ++ ++ _enter_critical_bh(&(pio_queue->lock), &irqL); ++ ++ ++ // insert the io_request into processing io_queue ++ rtw_list_insert_tail(&(pio_req->list),&(pio_queue->processing)); ++ ++ ++ if((adapter->bDriverStopped) || (adapter->bSurpriseRemoved) ||(adapter->pwrctrlpriv.pnp_bstop_trx)) ++ { ++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("\npadapter->pwrctrlpriv.pnp_bstop_trx==_TRUE\n")); ++ goto exit; ++ } ++ ++ //translate DMA FIFO addr to pipehandle ++ hPipe = ffaddr2pipehdl(pdvobj_priv, addr); ++ ++ RT_TRACE( _module_hci_ops_os_c_, _drv_info_,("usb_write_mem(%u)\n",__LINE__)); ++ ++ pio_req->usb_transfer_write_mem = (*usb_funcs_vp->lpIssueBulkTransfer)( ++ hPipe, ++ usb_write_mem_complete, ++ pio_queue, ++ USB_OUT_TRANSFER, ++ cnt, ++ wmem, ++ 0); ++ ++#if 0 ++ ++ (*usb_funcs_vp->lpGetTransferStatus)(pio_req->usb_transfer_write_mem , &dwBytes, &dwErr); ++ ++ while( fComplete != _TRUE) ++ { ++ fComplete = (*usb_funcs_vp->lpIsTransferComplete)(pio_req->usb_transfer_write_mem); ++ if(fComplete==_TRUE) ++ { ++ (*usb_funcs_vp->lpCloseTransfer)(pio_req->usb_transfer_write_mem ); ++ RT_TRACE( _module_hci_ops_os_c_, _drv_err_, ("usb_write_mem finished\n")); ++ break; ++ } ++ else ++ { ++ RT_TRACE( _module_hci_ops_os_c_, _drv_err_, ++ ("usb_write_mem not yet finished %X\n", ++ pio_req->usb_transfer_write_mem)); ++ rtw_msleep_os(10); ++ } ++ ++ } ++ ++#endif ++ ++ ++// _rtw_down_sema(&pio_req->sema); ++ ++ RT_TRACE( _module_hci_ops_os_c_, _drv_info_, ("-usb_write_mem(%X)\n",pio_req->usb_transfer_write_mem)); ++ ++ _exit_critical_bh(&(pio_queue->lock), &irqL); ++ ++ _rtw_down_sema(&pio_req->sema); ++ free_ioreq(pio_req, pio_queue); ++ ++exit: ++_func_exit_; ++ return; ++} ++ ++u32 usb_write_cnt=0; ++u32 usb_complete_cnt=0; ++ ++USB_PIPE ffaddr2pipehdl(struct dvobj_priv *pNdisCEDvice, u32 addr) ++{ ++ USB_PIPE PipeHandle = NULL; ++ _adapter *padapter = pNdisCEDvice->padapter; ++ ++ ++ if(pNdisCEDvice->nr_endpoint == 11) ++ { ++ switch(addr) ++ { ++ case RTL8712_DMA_BEQ: ++ PipeHandle= padapter->halpriv.pipehdls_r8712[3] ; ++ break; ++ case RTL8712_DMA_BKQ: ++ PipeHandle= padapter->halpriv.pipehdls_r8712[4]; ++ break; ++ case RTL8712_DMA_VIQ: ++ PipeHandle= padapter->halpriv.pipehdls_r8712[2]; ++ break; ++ case RTL8712_DMA_VOQ: ++ PipeHandle= padapter->halpriv.pipehdls_r8712[1]; ++ break; ++ case RTL8712_DMA_BCNQ: ++ PipeHandle= padapter->halpriv.pipehdls_r8712[6]; ++ break; ++ case RTL8712_DMA_BMCQ: //HI Queue ++ PipeHandle= padapter->halpriv.pipehdls_r8712[7]; ++ break; ++ case RTL8712_DMA_MGTQ: ++ PipeHandle= padapter->halpriv.pipehdls_r8712[8]; ++ break; ++ case RTL8712_DMA_RX0FF: ++ PipeHandle= padapter->halpriv.pipehdls_r8712[0]; ++ break; ++ case RTL8712_DMA_C2HCMD: ++ PipeHandle= padapter->halpriv.pipehdls_r8712[5]; ++ break; ++ case RTL8712_DMA_H2CCMD: ++ PipeHandle= padapter->halpriv.pipehdls_r8712[9]; ++ break; ++ ++ } ++ ++ } ++ else if(pNdisCEDvice->nr_endpoint == 6) ++ { ++ switch(addr) ++ { ++ case RTL8712_DMA_BEQ: ++ PipeHandle= padapter->halpriv.pipehdls_r8712[3]; ++ break; ++ case RTL8712_DMA_BKQ: ++ PipeHandle= padapter->halpriv.pipehdls_r8712[4]; ++ break; ++ case RTL8712_DMA_VIQ: ++ PipeHandle= padapter->halpriv.pipehdls_r8712[2]; ++ break; ++ case RTL8712_DMA_VOQ: ++ PipeHandle= padapter->halpriv.pipehdls_r8712[1]; ++ break; ++ case RTL8712_DMA_RX0FF: ++ case RTL8712_DMA_C2HCMD: ++ PipeHandle= padapter->halpriv.pipehdls_r8712[0]; ++ break; ++ case RTL8712_DMA_H2CCMD: ++ case RTL8712_DMA_BCNQ: ++ case RTL8712_DMA_BMCQ: ++ case RTL8712_DMA_MGTQ: ++ PipeHandle= padapter->halpriv.pipehdls_r8712[5]; ++ break; ++ ++ } ++ ++ } ++ else if(pNdisCEDvice->nr_endpoint == 4) ++ { ++ switch(addr) ++ { ++ case RTL8712_DMA_BEQ: ++ case RTL8712_DMA_BKQ: ++ PipeHandle= padapter->halpriv.pipehdls_r8712[2]; ++ break; ++ case RTL8712_DMA_VIQ: ++ case RTL8712_DMA_VOQ: ++ PipeHandle= padapter->halpriv.pipehdls_r8712[1]; ++ break; ++ case RTL8712_DMA_RX0FF: ++ case RTL8712_DMA_C2HCMD: ++ PipeHandle= padapter->halpriv.pipehdls_r8712[0]; ++ break; ++ case RTL8712_DMA_H2CCMD: ++ case RTL8712_DMA_BCNQ: ++ case RTL8712_DMA_BMCQ: ++ case RTL8712_DMA_MGTQ: ++ PipeHandle= padapter->halpriv.pipehdls_r8712[3]; ++ break; ++ } ++ ++ } ++ else ++ { ++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("ffaddr2pipehdl():nr_endpoint=%d error!\n", pNdisCEDvice->nr_endpoint)); ++ } ++ ++ return PipeHandle; ++ ++} ++ ++DWORD usb_bulkout_zero_complete( LPVOID pZeroContext ) ++{ ++ struct zero_bulkout_context *pcontext = (struct zero_bulkout_context *)pZeroContext; ++ _adapter * padapter = pcontext->padapter; ++ struct dvobj_priv * pdvobj_priv = (struct dvobj_priv *)&padapter->dvobjpriv; ++ LPCUSB_FUNCS usb_funcs_vp = pdvobj_priv->usb_extension._lpUsbFuncs; ++ struct xmit_priv * pxmitpriv = &padapter->xmitpriv; ++ ++ int fComplete =_FALSE; ++ DWORD dwBytesTransferred = 0; ++ DWORD dwErr = USB_CANCELED_ERROR; ++ ++_func_enter_; ++ ++#if 1 ++ ++ (*usb_funcs_vp->lpGetTransferStatus)(pxmitpriv->usb_transfer_write_port, &dwBytesTransferred, &dwErr); ++ fComplete = (*usb_funcs_vp->lpIsTransferComplete)(pxmitpriv->usb_transfer_write_port); ++ if(fComplete!=_TRUE) ++ { ++ RT_TRACE( _module_hci_ops_os_c_, _drv_err_, ("usb_bulkout_zero_complete CloseTransfer before complete\n")); ++ } ++ (*usb_funcs_vp->lpCloseTransfer)(pxmitpriv->usb_transfer_write_port); ++ ++#endif ++ ++ if(pcontext) ++ { ++ if(pcontext->pbuf) ++ { ++ rtw_mfree(pcontext->pbuf, sizeof(int)); ++ } ++ ++ rtw_mfree((u8*)pcontext, sizeof(struct zero_bulkout_context)); ++ } ++ ++_func_exit_; ++ ++ return ERROR_SUCCESS; ++ ++ ++} ++ ++u32 usb_bulkout_zero(struct intf_hdl *pintfhdl, u32 addr) ++{ ++ struct zero_bulkout_context *pcontext; ++ unsigned char *pbuf; ++ u8 len = 0 ; ++ _adapter *padapter = (_adapter *)pintfhdl->adapter; ++ struct dvobj_priv *pdvobj = (struct dvobj_priv *)&padapter->dvobjpriv; ++ struct xmit_priv * pxmitpriv = &padapter->xmitpriv; ++ ++ ++ LPCUSB_FUNCS usb_funcs_vp = pdvobj->usb_extension._lpUsbFuncs; ++ ++ USB_PIPE hPipe; ++ ++_func_enter_; ++ ++ if((padapter->bDriverStopped) || (padapter->bSurpriseRemoved) ||(padapter->pwrctrlpriv.pnp_bstop_trx)) ++ { ++ return _FAIL; ++ } ++ ++ ++ pcontext = (struct zero_bulkout_context *)rtw_zmalloc(sizeof(struct zero_bulkout_context)); ++ ++ pbuf = (unsigned char *)rtw_zmalloc(sizeof(int)); ++ ++ len = 0; ++ ++ pcontext->pbuf = pbuf; ++ pcontext->purb = NULL; ++ pcontext->pirp = NULL; ++ pcontext->padapter = padapter; ++ ++ ++//translate DMA FIFO addr to pipehandle ++ hPipe = ffaddr2pipehdl(pdvobj, addr); ++ ++ ++ ++ ++ pxmitpriv->usb_transfer_write_port = (*usb_funcs_vp->lpIssueBulkTransfer)( ++ hPipe, usb_bulkout_zero_complete, ++ pcontext, USB_OUT_TRANSFER, ++ len, pbuf, 0); ++ ++ ++_func_exit_; ++ ++ return _SUCCESS; ++ ++} ++ ++u32 usb_write_port(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *wmem) ++{ ++ ++ u32 i, bwritezero = _FALSE; ++ u32 ac_tag = addr; ++ ++ u8* ptr; ++ ++ struct intf_priv * pintfpriv = pintfhdl->pintfpriv; ++ struct dvobj_priv * pdvobj_priv = (struct dvobj_priv*)pintfpriv->intf_dev; ++ _adapter * padapter = pdvobj_priv->padapter; ++ ++ struct xmit_priv * pxmitpriv = &padapter->xmitpriv; ++ struct xmit_frame * pxmitframe = (struct xmit_frame *)wmem; ++ ++ LPCUSB_FUNCS usb_funcs_vp = pdvobj_priv->usb_extension._lpUsbFuncs; ++ ++ USB_PIPE hPipe; ++ ++ u32 bResult = _FALSE; ++ ++_func_enter_; ++ RT_TRACE( _module_hci_ops_os_c_, _drv_info_, ("+usb_write_port\n")); ++ ++#if (CONFIG_PWRCTRL == 1) ++ if(padapter->pwrctrlpriv.pnp_bstop_trx==_TRUE){ ++ RT_TRACE( _module_hci_ops_os_c_, _drv_err_, ("\npadapter->pwrctrlpriv.pnp_bstop_trx==_TRUE\n")); ++ ++ } ++#endif ++ ++ if((padapter->bDriverStopped) || (padapter->bSurpriseRemoved) ||(padapter->pwrctrlpriv.pnp_bstop_trx)) ++ { ++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_write_port:( padapter->bDriverStopped ||padapter->bSurpriseRemoved ||adapter->pwrctrlpriv.pnp_bstop_trx)!!!\n")); ++ bResult = _FALSE; ++ goto exit; ++ } ++ ++ RT_TRACE( _module_hci_ops_os_c_, _drv_info_, ("usb_write_port(%u)\n", __LINE__)); ++ ++ for(i=0; i<8; i++) ++ { ++ if(pxmitframe->bpending[i] == _FALSE) ++ { ++ _rtw_spinlock(&pxmitpriv->lock); ++ pxmitpriv->txirp_cnt++; ++ pxmitframe->bpending[i] = _TRUE; ++ _rtw_spinunlock(&pxmitpriv->lock); ++ ++ pxmitframe->sz[i] = cnt; ++ pxmitframe->ac_tag[i] = ac_tag; ++ ++ break; ++ } ++ } ++ ++ ++ //TODO: ++ if (pdvobj_priv->ishighspeed) ++ { ++ if(cnt> 0 && cnt%512 == 0) ++ { ++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("ishighspeed, cnt=%d\n", cnt)); ++ // cnt=cnt+1; ++ bwritezero = _TRUE; ++ ++ } ++ } ++ else ++ { ++ if(cnt > 0 && cnt%64 == 0) ++ { ++ RT_TRACE(_module_hci_ops_os_c_,_drv_info_,("cnt=%d\n", cnt)); ++ // cnt=cnt+1; ++ bwritezero = _TRUE; ++ ++ } ++ } ++ ++ RT_TRACE( _module_hci_ops_os_c_, _drv_info_, ("usb_write_port: pipe handle convert\n")); ++ ++ //translate DMA FIFO addr to pipehandle ++ hPipe = ffaddr2pipehdl(pdvobj_priv, addr); ++ ++ ++#if 0 ++ // for tx fifo, the maximum payload number is 8, ++ // we workaround this issue here by separate whole fifo into 8 segments. ++ if (cnt <= 500) ++ cnt = 500; ++#endif ++ ++ RT_TRACE( _module_hci_ops_os_c_, _drv_info_, ++ ("usb_write_port(%u): pxmitframe %X pxmitframe->padapter %X\n",__LINE__, pxmitframe, pxmitframe->padapter)); ++ ++ pxmitpriv->usb_transfer_write_port = (*usb_funcs_vp->lpIssueBulkTransfer)( ++ hPipe, usb_write_port_complete, ++ pxmitframe, USB_OUT_TRANSFER, ++ cnt, pxmitframe->mem_addr, 0); ++ ++ RT_TRACE( _module_hci_ops_os_c_, _drv_info_, ("%s(%u)\n",__FUNCTION__, __LINE__)); ++ ++ ptr=(u8 *)&pxmitframe->mem; ++ ++#if 0 ++ if (pdvobj_priv->ishighspeed) ++ { ++ ptr=ptr+512; ++ } ++ else ++ { ++ ptr=ptr+64; ++ ++ } ++#endif ++ if(bwritezero == _TRUE) ++ { ++ usb_bulkout_zero(pintfhdl, addr); ++ } ++ ++// if (!pxmitframe->usb_transfer_xmit) ++// padapter->bSurpriseRemoved=_TRUE; ++ ++ RT_TRACE( _module_hci_ops_os_c_, _drv_info_, ("%s(%u)\n",__FUNCTION__, __LINE__)); ++ bResult = _SUCCESS; ++ ++exit: ++_func_exit_; ++ return bResult; ++} ++ ++DWORD usb_write_port_complete( LPVOID Context ) ++{ ++ ++// u8 *ptr; ++ ++ struct xmit_frame * pxmitframe = (struct xmit_frame *) Context; ++ _adapter * padapter = pxmitframe->padapter; ++ struct dvobj_priv * pdvobj_priv = (struct dvobj_priv *)&padapter->dvobjpriv; ++ struct xmit_priv * pxmitpriv = &padapter->xmitpriv; ++ struct xmit_buf *pxmitbuf = pxmitframe->pxmitbuf; ++ LPCUSB_FUNCS usb_funcs_vp = pdvobj_priv->usb_extension._lpUsbFuncs; ++ ++ int fComplete =_FALSE; ++ DWORD dwBytesTransferred = 0; ++ DWORD dwErr = USB_CANCELED_ERROR; ++ ++ RT_TRACE( _module_hci_ops_os_c_, _drv_info_, ("%s(%u), pxmitframe %X\n",__FUNCTION__, __LINE__, Context)); ++ ++_func_enter_; ++ ++ RT_TRACE(_module_hci_ops_os_c_,_drv_info_,("+usb_write_port_complete\n")); ++ ++ _rtw_spinlock_ex(&pxmitpriv->lock); ++ pxmitpriv->txirp_cnt--; ++ _rtw_spinunlock_ex(&pxmitpriv->lock); ++ ++ if(pxmitpriv->txirp_cnt==0){ ++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_write_port_complete: txirp_cnt== 0, set allrxreturnevt!\n")); ++ _rtw_up_sema(&(pxmitpriv->tx_retevt)); ++ } ++ ++ ++ //not to consider tx fragment ++ rtw_free_xmitframe_ex(pxmitpriv, pxmitframe); ++ ++ ++#if 1 ++ ++ (*usb_funcs_vp->lpGetTransferStatus)(pxmitpriv->usb_transfer_write_port, &dwBytesTransferred, &dwErr); ++ fComplete = (*usb_funcs_vp->lpIsTransferComplete)(pxmitpriv->usb_transfer_write_port); ++ if(fComplete!=_TRUE) ++ { ++ RT_TRACE( _module_hci_ops_os_c_, _drv_err_, ("usb_write_port_complete CloseTransfer before complete\n")); ++ } ++ (*usb_funcs_vp->lpCloseTransfer)(pxmitpriv->usb_transfer_write_port); ++ ++#else ++ ++ if((*usb_funcs_vp->lpIsTransferComplete)(pxmitpriv->usb_transfer_write_port)) ++ { ++ (*usb_funcs_vp->lpCloseTransfer)(pxmitpriv->usb_transfer_write_port); ++ } ++ ++#endif ++ ++ RT_TRACE( _module_hci_ops_os_c_, _drv_info_, ++ ("%s(%u): pxmitpriv %X pxmitpriv->free_xmitframe_cnt %X pxmitframe->padapter %X pxmitframe->padapter %X\n", ++ __LINE__, pxmitpriv, pxmitpriv->free_xmitframe_cnt, pxmitframe->padapter)); ++ ++ rtl8192cu_xmitframe_complete(padapter, pxmitpriv, pxmitbuf); ++ ++_func_exit_; ++ ++ return STATUS_SUCCESS; ++} ++ ++DWORD usb_write_scsi_complete(LPVOID pTxContext) ++{ ++#ifndef PLATFORM_OS_CE ++ struct SCSI_BUFFER_ENTRY *psb_entry = (struct SCSI_BUFFER_ENTRY *)pTxContext; ++ _adapter *padapter = psb_entry->padapter; ++ struct SCSI_BUFFER *psb = padapter->pscsi_buf; ++ struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); ++ struct dvobj_priv *pdvobj_priv = (struct dvobj_priv *)&padapter->dvobjpriv; ++ LPCUSB_FUNCS lpUsbFuncs = pdvobj_priv->pUsbExtension->_lpUsbFuncs; ++ ++ int fComplete =_FALSE; ++ DWORD dwBytesTransferred = 0; ++ DWORD dwErr = USB_CANCELED_ERROR; ++ ++_func_enter_; ++ RT_TRACE( _module_hci_ops_os_c_, _drv_info_, ("%s(%u): circ_space = %d\n",__FUNCTION__, __LINE__, CIRC_SPACE( psb->head,psb->tail, SCSI_BUFFER_NUMBER))); ++ ++#if 1 ++ ++ (*lpUsbFuncs->lpGetTransferStatus)(psb_entry->usb_transfer_scsi_txcmd, &dwBytesTransferred, &dwErr); ++ fComplete = (*lpUsbFuncs->lpIsTransferComplete)(psb_entry->usb_transfer_scsi_txcmd); ++ if(fComplete!=_TRUE) ++ { ++ RT_TRACE( _module_hci_ops_os_c_, _drv_err_, ("usb_write_scsi_complete CloseTransfer before complete\n")); ++ } ++ (*lpUsbFuncs->lpCloseTransfer)(psb_entry->usb_transfer_scsi_txcmd); ++ ++#else ++ ++ if((*lpUsbFuncs->lpIsTransferComplete)(psb_entry->usb_transfer_scsi_txcmd)) ++ (*lpUsbFuncs->lpCloseTransfer)(psb_entry->usb_transfer_scsi_txcmd); ++#endif ++ ++ memset(psb_entry->entry_memory, 0, 8); ++ ++ RT_TRACE( _module_hci_ops_os_c_, _drv_info_, ("%s(%u)\n",__FUNCTION__, __LINE__)); ++ if((psb->tail+1)==SCSI_BUFFER_NUMBER) ++ psb->tail=0; ++ else ++ psb->tail++; ++ ++ RT_TRACE( _module_hci_ops_os_c_, _drv_info_, ("%s(%u)\n",__FUNCTION__, __LINE__)); ++ if(CIRC_CNT(psb->head,psb->tail,SCSI_BUFFER_NUMBER)==0){ ++ RT_TRACE( _module_hci_ops_os_c_, _drv_info_, ("write_txcmd_scsififo_callback: up_sema\n")); ++ _rtw_up_sema(&pxmitpriv->xmit_sema); ++ } ++ ++ RT_TRACE( _module_hci_ops_os_c_, _drv_info_, ("%s(%u)\n",__FUNCTION__, __LINE__)); ++ if(padapter->bSurpriseRemoved) { ++ return STATUS_MORE_PROCESSING_REQUIRED; ++ } ++ ++_func_exit_; ++#endif ++ RT_TRACE( _module_hci_ops_os_c_, _drv_info_, ("%s(%u)\n",__FUNCTION__, __LINE__)); ++ return STATUS_MORE_PROCESSING_REQUIRED; ++} ++ ++uint usb_write_scsi(struct intf_hdl *pintfhdl, u32 cnt, u8 *wmem) ++{ ++ ++#ifndef PLATFORM_OS_CE ++ ++ _adapter *padapter = (_adapter *)pintfhdl->adapter; ++ struct dvobj_priv *pdev = (struct dvobj_priv*)&padapter->dvobjpriv; ++ ++ struct SCSI_BUFFER *psb =padapter->pscsi_buf; ++ struct SCSI_BUFFER_ENTRY *psb_entry=LIST_CONTAINOR(wmem,struct SCSI_BUFFER_ENTRY,entry_memory); ++ ++_func_enter_; ++ if(padapter->bSurpriseRemoved||padapter->bDriverStopped) ++ return 0; ++ ++ RT_TRACE( _module_hci_ops_os_c_, _drv_info_, ("%s(%u)\n",__FUNCTION__, __LINE__)); ++ psb_entry->usb_transfer_scsi_txcmd=pdev->pUsbExtension->_lpUsbFuncs->lpIssueBulkTransfer( ++ pdev->scsi_out_pipehandle, ++ usb_write_scsi_complete, ++ psb_entry, ++ USB_OUT_TRANSFER, ++ cnt, ++ wmem, ++ 0); ++ ++_func_exit_; ++#endif ++ ++ return _SUCCESS; ++} ++ ++ ++/* ++ */ ++uint usb_init_intf_priv(struct intf_priv *pintfpriv) ++{ ++ // get the dvobj_priv object ++ struct dvobj_priv * pNdisCEDvice = (struct dvobj_priv *) pintfpriv->intf_dev; ++ ++ RT_TRACE( _module_hci_ops_os_c_, _drv_info_, ("%s(%u)\n",__FUNCTION__, __LINE__)); ++ // set init intf_priv init status as _IOREADY ++ pintfpriv->intf_status = _IOREADY; ++ ++ // determine the max io size by dvobj_priv.ishighspeed ++ if(pNdisCEDvice->ishighspeed) ++ pintfpriv->max_iosz = 128; ++ else ++ pintfpriv->max_iosz = 64; ++ ++ // read/write size set as 0 ++ pintfpriv->io_wsz = 0; ++ pintfpriv->io_rsz = 0; ++ ++ // init io_rwmem buffer ++ pintfpriv->allocated_io_rwmem = rtw_zmalloc(pintfpriv->max_iosz +4); ++ if (pintfpriv->allocated_io_rwmem == NULL) ++ { ++ rtw_mfree((u8 *)(pintfpriv->allocated_io_rwmem), pintfpriv->max_iosz +4); ++ return _FAIL; ++ } ++ else ++ { ++ // word align the io_rwmem ++ pintfpriv->io_rwmem = pintfpriv->allocated_io_rwmem + 4 - ( (u32)(pintfpriv->allocated_io_rwmem) & 3); ++ } ++ ++#ifndef PLATFORM_OS_CE ++ ++ // init io_r_mem buffer ++ pintfpriv->allocated_io_r_mem = rtw_zmalloc(pintfpriv->max_iosz +4); ++ if (pintfpriv->allocated_io_r_mem == NULL) ++ { ++ rtw_mfree((u8 *)(pintfpriv->allocated_io_r_mem), pintfpriv->max_iosz +4); ++ return _FAIL; ++ } ++ else ++ { ++ // word align the io_rwmem ++ pintfpriv->io_r_mem = pintfpriv->allocated_io_r_mem + 4 - ( (u32)(pintfpriv->allocated_io_r_mem) & 3); ++ } ++#endif ++ ++ return _SUCCESS; ++} ++ ++void usb_unload_intf_priv(struct intf_priv *pintfpriv) ++{ ++#ifndef PLATFORM_OS_CE ++ ++ rtw_mfree((u8 *)(pintfpriv->allocated_io_rwmem), pintfpriv->max_iosz+4); ++ rtw_mfree((u8 *)(pintfpriv->allocated_io_r_mem), pintfpriv->max_iosz+4); ++#endif ++ ++ RT_TRACE( _module_hci_ops_os_c_, _drv_info_, ("%s(%u)\n",__FUNCTION__, __LINE__)); ++} ++ ++ ++ ++void usb_write_port_cancel(_adapter *padapter) ++{ ++ ++ sint i,j; ++ struct dvobj_priv *pdev = &padapter->dvobjpriv; ++ struct xmit_priv *pxmitpriv=&padapter->xmitpriv; ++ struct xmit_frame *pxmitframe; ++ ++ _rtw_spinlock(&pxmitpriv->lock); ++ pxmitpriv->txirp_cnt--; //decrease 1 for Initialize ++ ++ _rtw_spinunlock(&pxmitpriv->lock); ++ ++ if (pxmitpriv->txirp_cnt) ++ { ++ // Canceling Pending Recv Irp ++ pxmitframe= (struct xmit_frame *)pxmitpriv->pxmit_frame_buf; ++ ++ for( i = 0; i < NR_XMITFRAME; i++ ) ++ { ++ for(j=0;j<8;j++) ++ { ++ if (pxmitframe->bpending[j]==_TRUE) ++ { ++ ++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,(" usb_write_port_cancel() :IoCancelIrp\n")); ++ ++ } ++ } ++ ++ pxmitframe++; ++ } ++ ++ _rtw_down_sema(&(pxmitpriv->tx_retevt)); ++ ++ } ++ ++} ++ ++DWORD usbctrl_vendorreq_complete(LPVOID lpvNotifyParameter) ++{ ++ struct dvobj_priv *pdvobjpriv = (struct dvobj_priv*)lpvNotifyParameter; ++ ++ RT_TRACE(_module_hci_ops_os_c_,_drv_debug_,("+usbctrl_vendorreq_complete\n")); ++ ++ return STATUS_SUCCESS; ++} ++ ++ ++int usbctrl_vendorreq(struct intf_priv *pintfpriv, u8 request, u16 value, u16 index, void *pdata, u16 len, u8 requesttype) ++{ ++ u8 ret=_TRUE; ++// NTSTATUS ntstatus; ++// int fComplete; ++// LPCUSB_DEVICE lpDeviceInfo; ++ ++ struct dvobj_priv *pdvobjpriv = (struct dvobj_priv *)pintfpriv->intf_dev; ++ ++ USB_TRANSFER usbTrans; ++ USB_DEVICE_REQUEST usb_device_req; ++ USB_HANDLE usbHandle = pdvobjpriv->usb_extension._hDevice; ++ LPCUSB_FUNCS usbFuncs = pdvobjpriv->usb_extension._lpUsbFuncs; ++ ++ u32 transfer_flags = 0; ++ ++ _func_enter_; ++ ++ memset( &usb_device_req, 0, sizeof( USB_DEVICE_REQUEST ) ); ++ ++ if( 0x01 == requesttype ) ++ { ++ usb_device_req.bmRequestType = USB_REQUEST_DEVICE_TO_HOST | USB_REQUEST_VENDOR | USB_REQUEST_FOR_DEVICE; ++ } ++ else ++ { ++ usb_device_req.bmRequestType = USB_REQUEST_HOST_TO_DEVICE | USB_REQUEST_VENDOR | USB_REQUEST_FOR_DEVICE; ++ } ++ ++ usb_device_req.bRequest = request; ++ usb_device_req.wValue = value; ++ usb_device_req.wIndex = index; ++ usb_device_req.wLength = len; ++ ++ if (requesttype == 0x01) ++ { ++ transfer_flags = USB_IN_TRANSFER;//read_in ++ } ++ else ++ { ++ transfer_flags= USB_OUT_TRANSFER;//write_out ++ } ++ ++ RT_TRACE(_module_hci_ops_os_c_,_drv_debug_,("+usbctrl_vendorreq\n",__FUNCTION__,__LINE__)); ++ ++#if 0 ++ // Remember to add callback for sync ++ usbTrans = (*usbFuncs->lpIssueVendorTransfer)(usbHandle, ++ usbctrl_vendorreq_complete, pdvobjpriv, ++ transfer_flags, &usb_device_req, pdata, 0); ++#else ++ // Remember to add callback for sync ++ usbTrans = (*usbFuncs->lpIssueVendorTransfer)(usbHandle, ++ NULL, 0, ++ transfer_flags, &usb_device_req, pdata, 0); ++#endif ++ ++// rtw_usleep_os(10); ++ ++ if ( usbTrans ) ++ { ++ DWORD dwBytes = 0; ++ DWORD dwErr = USB_CANCELED_ERROR; ++ int fComplete; ++ ++ (*usbFuncs->lpGetTransferStatus)(usbTrans, &dwBytes, &dwErr); ++ ++ fComplete = (*usbFuncs->lpIsTransferComplete)(usbTrans); ++ ++ if (fComplete== _TRUE) ++ { ++ (*usbFuncs->lpCloseTransfer)(usbTrans); ++ RT_TRACE(_module_hci_ops_os_c_,_drv_debug_,("usbctrl_vendorreq lpCloseTransfer\n")); ++ } ++ ++ if ( dwErr != USB_NO_ERROR || fComplete != _TRUE) ++ { ++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usbctrl_vendorreq lpCloseTransfer without complete\n")); ++ ret = _FALSE; ++ goto exit; ++ } ++ } ++ else ++ { ++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usbctrl_vendorreq without usbTrans\n")); ++ ret = _FALSE; ++ goto exit; ++ ++ } ++ ++exit: ++ RT_TRACE(_module_hci_ops_os_c_,_drv_debug_,("-usbctrl_vendorreq\n")); ++_func_exit_; ++ ++ return ret; ++ ++} ++ ++ +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/hal/rtl8192c/usb/usb_ops_linux.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/hal/rtl8192c/usb/usb_ops_linux.c 2013-07-26 19:36:06.000000000 +0000 +@@ -0,0 +1,2045 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ++******************************************************************************/ ++#define _HCI_OPS_OS_C_ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#if defined (PLATFORM_LINUX) && defined (PLATFORM_WINDOWS) ++ ++#error "Shall be Linux or Windows, but not both!\n" ++ ++#endif ++ ++struct zero_bulkout_context{ ++ void *pbuf; ++ void *purb; ++ void *pirp; ++ void *padapter; ++}; ++ ++#define REALTEK_USB_VENQT_MAX_BUF_SIZE 254 ++ ++#define RTW_USB_CONTROL_MSG_TIMEOUT_TEST 10 //ms ++#define RTW_USB_CONTROL_MSG_TIMEOUT 500 //ms ++//#define RTW_USB_CONTROL_MSG_TIMEOUT 5000 //ms ++ ++#if defined(CONFIG_VENDOR_REQ_RETRY) && defined(CONFIG_USB_VENDOR_REQ_MUTEX) ++//vendor req retry should be in the situation when each vendor req is atomically submitted from others ++#define MAX_USBCTRL_VENDORREQ_TIMES 10 ++#else ++#define MAX_USBCTRL_VENDORREQ_TIMES 1 ++#endif ++ ++#define RTW_USB_BULKOUT_TIMEOUT 5000 //ms ++ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)) || (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,18)) ++#define _usbctrl_vendorreq_async_callback(urb, regs) _usbctrl_vendorreq_async_callback(urb) ++#define usb_bulkout_zero_complete(purb, regs) usb_bulkout_zero_complete(purb) ++#define usb_write_mem_complete(purb, regs) usb_write_mem_complete(purb) ++#define usb_write_port_complete(purb, regs) usb_write_port_complete(purb) ++#define usb_read_port_complete(purb, regs) usb_read_port_complete(purb) ++#define usb_read_interrupt_complete(purb, regs) usb_read_interrupt_complete(purb) ++#endif ++ ++static int usbctrl_vendorreq(struct dvobj_priv *pdvobjpriv, u8 request, u16 value, u16 index, void *pdata, u16 len, u8 requesttype) ++{ ++ _adapter *padapter = pdvobjpriv->padapter ; ++ struct usb_device *udev=pdvobjpriv->pusbdev; ++ ++ unsigned int pipe; ++ int status = 0; ++ u32 tmp_buflen=0; ++ u8 reqtype; ++ u8 *pIo_buf; ++ int vendorreq_times = 0; ++ ++ #ifdef CONFIG_USB_VENDOR_REQ_BUFFER_DYNAMIC_ALLOCATE ++ u8 *tmp_buf; ++ #else // use stack memory ++ u8 tmp_buf[MAX_USB_IO_CTL_SIZE]; ++ #endif ++ ++ //DBG_871X("%s %s:%d\n",__FUNCTION__, current->comm, current->pid); ++ ++ if((padapter->bSurpriseRemoved) ||(padapter->pwrctrlpriv.pnp_bstop_trx)){ ++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usbctrl_vendorreq:(padapter->bSurpriseRemoved ||adapter->pwrctrlpriv.pnp_bstop_trx)!!!\n")); ++ status = -EPERM; ++ goto exit; ++ } ++ ++ if(len>MAX_VENDOR_REQ_CMD_SIZE){ ++ DBG_8192C( "[%s] Buffer len error ,vendor request failed\n", __FUNCTION__ ); ++ status = -EINVAL; ++ goto exit; ++ } ++ ++ #ifdef CONFIG_USB_VENDOR_REQ_MUTEX ++ _enter_critical_mutex(&pdvobjpriv->usb_vendor_req_mutex, NULL); ++ #endif ++ ++ ++ // Acquire IO memory for vendorreq ++#ifdef CONFIG_USB_VENDOR_REQ_BUFFER_PREALLOC ++ pIo_buf = pdvobjpriv->usb_vendor_req_buf; ++#else ++ #ifdef CONFIG_USB_VENDOR_REQ_BUFFER_DYNAMIC_ALLOCATE ++ tmp_buf = rtw_malloc( (u32) len + ALIGNMENT_UNIT); ++ tmp_buflen = (u32)len + ALIGNMENT_UNIT; ++ #else // use stack memory ++ tmp_buflen = MAX_USB_IO_CTL_SIZE; ++ #endif ++ ++ // Added by Albert 2010/02/09 ++ // For mstar platform, mstar suggests the address for USB IO should be 16 bytes alignment. ++ // Trying to fix it here. ++ pIo_buf = (tmp_buf==NULL)?NULL:tmp_buf + ALIGNMENT_UNIT -((SIZE_PTR)(tmp_buf) & 0x0f ); ++#endif ++ ++ if ( pIo_buf== NULL) { ++ DBG_8192C( "[%s] pIo_buf == NULL \n", __FUNCTION__ ); ++ status = -ENOMEM; ++ goto release_mutex; ++ } ++ ++ while(++vendorreq_times<= MAX_USBCTRL_VENDORREQ_TIMES) ++ { ++ _rtw_memset(pIo_buf, 0, len); ++ ++ if (requesttype == 0x01) ++ { ++ pipe = usb_rcvctrlpipe(udev, 0);//read_in ++ reqtype = REALTEK_USB_VENQT_READ; ++ } ++ else ++ { ++ pipe = usb_sndctrlpipe(udev, 0);//write_out ++ reqtype = REALTEK_USB_VENQT_WRITE; ++ _rtw_memcpy( pIo_buf, pdata, len); ++ } ++ ++ #if 0 ++ //timeout test for firmware downloading ++ status = rtw_usb_control_msg(udev, pipe, request, reqtype, value, index, pIo_buf, len ++ , ((value >= FW_8192C_START_ADDRESS && value <= FW_8192C_END_ADDRESS) ||value!=0x1000) ?RTW_USB_CONTROL_MSG_TIMEOUT : RTW_USB_CONTROL_MSG_TIMEOUT_TEST ++ ); ++ #else ++ status = rtw_usb_control_msg(udev, pipe, request, reqtype, value, index, pIo_buf, len, RTW_USB_CONTROL_MSG_TIMEOUT); ++ #endif ++ ++ if ( status == len) // Success this control transfer. ++ { ++ rtw_reset_continual_urb_error(&padapter->dvobjpriv); ++ if ( requesttype == 0x01 ) ++ { // For Control read transfer, we have to copy the read data from pIo_buf to pdata. ++ _rtw_memcpy( pdata, pIo_buf, len ); ++ } ++ } ++ else { // error cases ++ DBG_8192C("reg 0x%x, usb %s %u fail, status:%d value=0x%x, vendorreq_times:%d\n" ++ , value,(requesttype == 0x01)?"read":"write" , len, status, *(u32*)pdata, vendorreq_times); ++ ++ if (status < 0) { ++ if(status == (-ESHUTDOWN) || status == -ENODEV ) ++ { ++ padapter->bSurpriseRemoved = _TRUE; ++ } else { ++ #ifdef DBG_CONFIG_ERROR_DETECT ++ { ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); ++ pHalData->srestpriv.Wifi_Error_Status = USB_VEN_REQ_CMD_FAIL; ++ } ++ #endif ++ } ++ } ++ else // status != len && status >= 0 ++ { ++ if(status > 0) { ++ if ( requesttype == 0x01 ) ++ { // For Control read transfer, we have to copy the read data from pIo_buf to pdata. ++ _rtw_memcpy( pdata, pIo_buf, len ); ++ } ++ } ++ } ++ ++ if(rtw_inc_and_chk_continual_urb_error(&padapter->dvobjpriv) == _TRUE ){ ++ padapter->bSurpriseRemoved = _TRUE; ++ break; ++ } ++ ++ } ++ ++ // firmware download is checksumed, don't retry ++ if( (value >= FW_8192C_START_ADDRESS && value <= FW_8192C_END_ADDRESS) || status == len ) ++ break; ++ ++ } ++ ++ // release IO memory used by vendorreq ++ #ifdef CONFIG_USB_VENDOR_REQ_BUFFER_DYNAMIC_ALLOCATE ++ rtw_mfree(tmp_buf, tmp_buflen); ++ #endif ++ ++release_mutex: ++ #ifdef CONFIG_USB_VENDOR_REQ_MUTEX ++ _exit_critical_mutex(&pdvobjpriv->usb_vendor_req_mutex, NULL); ++ #endif ++exit: ++ return status; ++ ++} ++ ++static u8 usb_read8(struct intf_hdl *pintfhdl, u32 addr) ++{ ++ u8 request; ++ u8 requesttype; ++ u16 wvalue; ++ u16 index; ++ u16 len; ++ u32 data=0; ++ struct dvobj_priv *pdvobjpriv = (struct dvobj_priv *)pintfhdl->pintf_dev; ++ ++ _func_enter_; ++ ++ request = 0x05; ++ requesttype = 0x01;//read_in ++ index = 0;//n/a ++ ++ wvalue = (u16)(addr&0x0000ffff); ++ len = 1; ++ ++ usbctrl_vendorreq(pdvobjpriv, request, wvalue, index, &data, len, requesttype); ++ ++ _func_exit_; ++ ++ return (u8)(le32_to_cpu(data)&0x0ff); ++ ++} ++ ++static u16 usb_read16(struct intf_hdl *pintfhdl, u32 addr) ++{ ++ u8 request; ++ u8 requesttype; ++ u16 wvalue; ++ u16 index; ++ u16 len; ++ u32 data=0; ++ struct dvobj_priv *pdvobjpriv = (struct dvobj_priv *)pintfhdl->pintf_dev; ++ ++ _func_enter_; ++ ++ request = 0x05; ++ requesttype = 0x01;//read_in ++ index = 0;//n/a ++ ++ wvalue = (u16)(addr&0x0000ffff); ++ len = 2; ++ ++ usbctrl_vendorreq(pdvobjpriv, request, wvalue, index, &data, len, requesttype); ++ ++ _func_exit_; ++ ++ return (u16)(le32_to_cpu(data)&0xffff); ++ ++} ++ ++static u32 usb_read32(struct intf_hdl *pintfhdl, u32 addr) ++{ ++ u8 request; ++ u8 requesttype; ++ u16 wvalue; ++ u16 index; ++ u16 len; ++ u32 data=0; ++ struct dvobj_priv *pdvobjpriv = (struct dvobj_priv *)pintfhdl->pintf_dev; ++ ++ _func_enter_; ++ ++ request = 0x05; ++ requesttype = 0x01;//read_in ++ index = 0;//n/a ++ ++ wvalue = (u16)(addr&0x0000ffff); ++ len = 4; ++ ++ usbctrl_vendorreq(pdvobjpriv, request, wvalue, index, &data, len, requesttype); ++ ++ _func_exit_; ++ ++ return le32_to_cpu(data); ++ ++} ++ ++static int usb_write8(struct intf_hdl *pintfhdl, u32 addr, u8 val) ++{ ++ u8 request; ++ u8 requesttype; ++ u16 wvalue; ++ u16 index; ++ u16 len; ++ u32 data; ++ int ret; ++ struct dvobj_priv *pdvobjpriv = (struct dvobj_priv *)pintfhdl->pintf_dev; ++ ++ _func_enter_; ++ ++ request = 0x05; ++ requesttype = 0x00;//write_out ++ index = 0;//n/a ++ ++ wvalue = (u16)(addr&0x0000ffff); ++ len = 1; ++ ++ data = val; ++ data = cpu_to_le32(data&0x000000ff); ++ ++ ret = usbctrl_vendorreq(pdvobjpriv, request, wvalue, index, &data, len, requesttype); ++ ++ _func_exit_; ++ ++ return ret; ++ ++} ++ ++static int usb_write16(struct intf_hdl *pintfhdl, u32 addr, u16 val) ++{ ++ u8 request; ++ u8 requesttype; ++ u16 wvalue; ++ u16 index; ++ u16 len; ++ u32 data; ++ int ret; ++ struct dvobj_priv *pdvobjpriv = (struct dvobj_priv *)pintfhdl->pintf_dev; ++ ++ _func_enter_; ++ ++ request = 0x05; ++ requesttype = 0x00;//write_out ++ index = 0;//n/a ++ ++ wvalue = (u16)(addr&0x0000ffff); ++ len = 2; ++ ++ data = val; ++ data = cpu_to_le32(data&0x0000ffff); ++ ++ ret = usbctrl_vendorreq(pdvobjpriv, request, wvalue, index, &data, len, requesttype); ++ ++ _func_exit_; ++ ++ return ret; ++ ++} ++ ++static int usb_write32(struct intf_hdl *pintfhdl, u32 addr, u32 val) ++{ ++ u8 request; ++ u8 requesttype; ++ u16 wvalue; ++ u16 index; ++ u16 len; ++ u32 data; ++ int ret; ++ struct dvobj_priv *pdvobjpriv = (struct dvobj_priv *)pintfhdl->pintf_dev; ++ ++ _func_enter_; ++ ++ request = 0x05; ++ requesttype = 0x00;//write_out ++ index = 0;//n/a ++ ++ wvalue = (u16)(addr&0x0000ffff); ++ len = 4; ++ data = cpu_to_le32(val); ++ ++ ++ ret =usbctrl_vendorreq(pdvobjpriv, request, wvalue, index, &data, len, requesttype); ++ ++ _func_exit_; ++ ++ return ret; ++ ++} ++#define VENDOR_CMD_MAX_DATA_LEN 254 ++static int usb_writeN(struct intf_hdl *pintfhdl, u32 addr, u32 length, u8 *pdata) ++{ ++ u8 request; ++ u8 requesttype; ++ u16 wvalue; ++ u16 index; ++ u16 len; ++ u8 buf[VENDOR_CMD_MAX_DATA_LEN]={0}; ++ int ret; ++ struct dvobj_priv *pdvobjpriv = (struct dvobj_priv *)pintfhdl->pintf_dev; ++ ++ _func_enter_; ++ ++ request = 0x05; ++ requesttype = 0x00;//write_out ++ index = 0;//n/a ++ ++ wvalue = (u16)(addr&0x0000ffff); ++ len = length; ++ _rtw_memcpy(buf, pdata, len ); ++ ++ ret = usbctrl_vendorreq(pdvobjpriv, request, wvalue, index, buf, len, requesttype); ++ ++ _func_exit_; ++ ++ return ret; ++ ++} ++ ++#ifdef CONFIG_USB_SUPPORT_ASYNC_VDN_REQ ++static void _usbctrl_vendorreq_async_callback(struct urb *urb, struct pt_regs *regs) ++{ ++ if(urb){ ++ if(urb->context){ ++ kfree(urb->context); ++ } ++ usb_free_urb(urb); ++ } ++} ++ ++static int _usbctrl_vendorreq_async_write(struct usb_device *udev, u8 request, u16 value, u16 index, void *pdata, u16 len, u8 requesttype) ++{ ++ ++ int rc; ++ unsigned int pipe; ++ u8 reqtype; ++ struct usb_ctrlrequest *dr; ++ struct urb *urb; ++ struct rtl819x_async_write_data { ++ u8 data[REALTEK_USB_VENQT_MAX_BUF_SIZE]; ++ struct usb_ctrlrequest dr; ++ } *buf; ++ ++ if (requesttype == VENDOR_READ){ ++ pipe = usb_rcvctrlpipe(udev, 0);//read_in ++ reqtype = REALTEK_USB_VENQT_READ; ++ } ++ else { ++ pipe = usb_sndctrlpipe(udev, 0);//write_out ++ reqtype = REALTEK_USB_VENQT_WRITE; ++ } ++ ++ //buf = kmalloc(sizeof(*buf), GFP_ATOMIC); ++ buf = (struct rtl819x_async_write_data *)rtw_zmalloc(sizeof(*buf)); ++ if (!buf) { ++ rc = -ENOMEM; ++ goto exit; ++ } ++ ++ urb = usb_alloc_urb(0, GFP_ATOMIC); ++ if (!urb) { ++ rtw_mfree((u8*)buf,sizeof(*buf)); ++ rc = -ENOMEM; ++ goto exit; ++ } ++ ++ dr = &buf->dr; ++ ++ dr->bRequestType = reqtype; ++ dr->bRequest = request; ++ dr->wValue = cpu_to_le16(value); ++ dr->wIndex = cpu_to_le16(index); ++ dr->wLength = cpu_to_le16(len); ++ ++ _rtw_memcpy(buf, pdata, len); ++ ++ usb_fill_control_urb(urb, udev, pipe, ++ (unsigned char *)dr, buf, len, ++ _usbctrl_vendorreq_async_callback, buf); ++ ++ rc = usb_submit_urb(urb, GFP_ATOMIC); ++ if (rc < 0) { ++ rtw_mfree((u8*)buf,sizeof(*buf)); ++ usb_free_urb(urb); ++ } ++ ++exit: ++ return rc; ++ ++} ++ ++static int usb_write_async(struct usb_device *udev, u32 addr, u32 val, u16 len) ++{ ++ u8 request; ++ u8 requesttype; ++ u16 wvalue; ++ u16 index; ++ u32 data; ++ int ret; ++ ++ requesttype = VENDOR_WRITE;//write_out ++ request = REALTEK_USB_VENQT_CMD_REQ; ++ index = REALTEK_USB_VENQT_CMD_IDX;//n/a ++ ++ wvalue = (u16)(addr&0x0000ffff); ++ data = val & (0xffffffff >> ((4 - len) * 8)); ++ data = cpu_to_le32(data); ++ ++ ret = _usbctrl_vendorreq_async_write(udev, request, wvalue, index, &data, len, requesttype); ++ ++ return ret; ++} ++static int usb_async_write8(struct intf_hdl *pintfhdl, u32 addr, u8 val) ++{ ++ u32 data; ++ int ret; ++ struct dvobj_priv *pdvobjpriv = (struct dvobj_priv *)pintfhdl->pintf_dev; ++ struct usb_device *udev=pdvobjpriv->pusbdev; ++ ++ _func_enter_; ++ data = cpu_to_le32(val & 0xFF); ++ ret = usb_write_async(udev, addr, val, 1); ++ _func_exit_; ++ ++ return ret; ++} ++ ++static int usb_async_write16(struct intf_hdl *pintfhdl, u32 addr, u16 val) ++{ ++ u32 data; ++ int ret; ++ struct dvobj_priv *pdvobjpriv = (struct dvobj_priv *)pintfhdl->pintf_dev; ++ struct usb_device *udev=pdvobjpriv->pusbdev; ++ ++ _func_enter_; ++ data = cpu_to_le32(val & 0xFFFF); ++ ret = usb_write_async(udev, addr, val, 2); ++ _func_exit_; ++ ++ return ret; ++} ++static int usb_async_write32(struct intf_hdl *pintfhdl, u32 addr, u32 val) ++{ ++ u32 data; ++ int ret; ++ struct dvobj_priv *pdvobjpriv = (struct dvobj_priv *)pintfhdl->pintf_dev; ++ struct usb_device *udev=pdvobjpriv->pusbdev; ++ ++ _func_enter_; ++ data = cpu_to_le32(val); ++ ret = usb_write_async(udev, addr, val, 4); ++ _func_exit_; ++ ++ return ret; ++} ++#endif ++ ++static unsigned int ffaddr2pipehdl(struct dvobj_priv *pdvobj, u32 addr) ++{ ++ unsigned int pipe=0; ++ int ep_num=0; ++ _adapter *padapter = pdvobj->padapter; ++ struct usb_device *pusbd = pdvobj->pusbdev; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); ++ ++ if(addr == RECV_BULK_IN_ADDR) ++ { ++ pipe=usb_rcvbulkpipe(pusbd, 0x01); ++ ++ return pipe; ++ } ++ ++ if(addr == RECV_INT_IN_ADDR) ++ { ++ pipe=usb_rcvbulkpipe(pusbd, 0x04); ++ ++ return pipe; ++ } ++ ++ if(addr < HW_QUEUE_ENTRY) ++ { ++ ep_num = (pHalData->Queue2EPNum[(u8)addr] & 0x0f); ++ ++ pipe = usb_sndbulkpipe(pusbd, ep_num); ++ ++ return pipe; ++ } ++ ++ return pipe; ++ ++} ++ ++static void usb_bulkout_zero_complete(struct urb *purb, struct pt_regs *regs) ++{ ++ struct zero_bulkout_context *pcontext = (struct zero_bulkout_context *)purb->context; ++ ++ //DBG_8192C("+usb_bulkout_zero_complete\n"); ++ ++ if(pcontext) ++ { ++ if(pcontext->pbuf) ++ { ++ rtw_mfree(pcontext->pbuf, sizeof(int)); ++ } ++ ++ if(pcontext->purb && (pcontext->purb==purb)) ++ { ++ usb_free_urb(pcontext->purb); ++ } ++ ++ ++ rtw_mfree((u8*)pcontext, sizeof(struct zero_bulkout_context)); ++ } ++ ++ ++} ++ ++static u32 usb_bulkout_zero(struct intf_hdl *pintfhdl, u32 addr) ++{ ++ int pipe, status, len; ++ u32 ret; ++ unsigned char *pbuf; ++ struct zero_bulkout_context *pcontext; ++ PURB purb = NULL; ++ _adapter *padapter = (_adapter *)pintfhdl->padapter; ++ struct dvobj_priv *pdvobj = (struct dvobj_priv *)&padapter->dvobjpriv; ++ struct usb_device *pusbd = pdvobj->pusbdev; ++ ++ //DBG_8192C("+usb_bulkout_zero\n"); ++ ++ ++ if((padapter->bDriverStopped) || (padapter->bSurpriseRemoved) ||(padapter->pwrctrlpriv.pnp_bstop_trx)) ++ { ++ return _FAIL; ++ } ++ ++ ++ pcontext = (struct zero_bulkout_context *)rtw_zmalloc(sizeof(struct zero_bulkout_context)); ++ ++ pbuf = (unsigned char *)rtw_zmalloc(sizeof(int)); ++ purb = usb_alloc_urb(0, GFP_ATOMIC); ++ ++ len = 0; ++ pcontext->pbuf = pbuf; ++ pcontext->purb = purb; ++ pcontext->pirp = NULL; ++ pcontext->padapter = padapter; ++ ++ ++ //translate DMA FIFO addr to pipehandle ++ //pipe = ffaddr2pipehdl(pdvobj, addr); ++ ++ usb_fill_bulk_urb(purb, pusbd, pipe, ++ pbuf, ++ len, ++ usb_bulkout_zero_complete, ++ pcontext);//context is pcontext ++ ++ status = usb_submit_urb(purb, GFP_ATOMIC); ++ ++ if (!status) ++ { ++ ret= _SUCCESS; ++ } ++ else ++ { ++ ret= _FAIL; ++ } ++ ++ ++ return _SUCCESS; ++ ++} ++ ++static void usb_read_mem(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *rmem) ++{ ++ ++} ++ ++static void usb_write_mem(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *wmem) ++{ ++ ++} ++ ++#ifdef CONFIG_USB_INTERRUPT_IN_PIPE ++static void usb_read_interrupt_complete(struct urb *purb, struct pt_regs *regs) ++{ ++ int err; ++ _adapter *padapter = (_adapter *)purb->context; ++ ++ if(purb->status==0)//SUCCESS ++ { ++ if (purb->actual_length > sizeof(INTERRUPT_MSG_FORMAT_EX)) ++ { ++ DBG_8192C("usb_read_interrupt_complete: purb->actual_length > sizeof(INTERRUPT_MSG_FORMAT_EX) \n"); ++ } ++ ++ err = usb_submit_urb(purb, GFP_ATOMIC); ++ if((err) && (err != (-EPERM))) ++ { ++ DBG_8192C("cannot submit interrupt in-token(err = 0x%08x),urb_status = %d\n",err, purb->status); ++ } ++ } ++ else ++ { ++ DBG_8192C("###=> usb_read_interrupt_complete => urb status(%d)\n", purb->status); ++ ++ switch(purb->status) { ++ case -EINVAL: ++ case -EPIPE: ++ case -ENODEV: ++ case -ESHUTDOWN: ++ //padapter->bSurpriseRemoved=_TRUE; ++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port_complete:bSurpriseRemoved=TRUE\n")); ++ case -ENOENT: ++ padapter->bDriverStopped=_TRUE; ++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port_complete:bDriverStopped=TRUE\n")); ++ break; ++ case -EPROTO: ++ break; ++ case -EINPROGRESS: ++ DBG_8192C("ERROR: URB IS IN PROGRESS!/n"); ++ break; ++ default: ++ break; ++ } ++ } ++ ++} ++ ++static u32 usb_read_interrupt(struct intf_hdl *pintfhdl, u32 addr) ++{ ++ int err; ++ unsigned int pipe; ++ u32 ret = _SUCCESS; ++ struct dvobj_priv *pdvobj = (struct dvobj_priv *)pintfhdl->pintf_dev; ++ _adapter *adapter = (_adapter *)pdvobj->padapter; ++ struct recv_priv *precvpriv = &adapter->recvpriv; ++ struct usb_device *pusbd = pdvobj->pusbdev; ++ ++_func_enter_; ++ ++ //translate DMA FIFO addr to pipehandle ++ pipe = ffaddr2pipehdl(pdvobj, addr); ++ ++ usb_fill_int_urb(precvpriv->int_in_urb, pusbd, pipe, ++ precvpriv->int_in_buf, ++ sizeof(INTERRUPT_MSG_FORMAT_EX), ++ usb_read_interrupt_complete, ++ adapter, ++ 1); ++ ++ err = usb_submit_urb(precvpriv->int_in_urb, GFP_ATOMIC); ++ if((err) && (err != (-EPERM))) ++ { ++ DBG_8192C("cannot submit interrupt in-token(err = 0x%08x),urb_status = %d\n",err, precvpriv->int_in_urb->status); ++ ret = _FAIL; ++ } ++ ++_func_exit_; ++ ++ return ret; ++} ++#endif ++ ++#ifdef CONFIG_USE_USB_BUFFER_ALLOC_RX ++static int recvbuf2recvframe(_adapter *padapter, struct recv_buf *precvbuf) ++{ ++ u8 *pbuf; ++ u8 frag, mf, shift_sz = 0; ++ u16 pkt_cnt, drvinfo_sz; ++ u32 pkt_len, pkt_offset, skb_len, alloc_sz; ++ s32 transfer_len; ++ struct recv_stat *prxstat; ++ _pkt *pkt_copy = NULL; ++ union recv_frame *precvframe = NULL; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); ++ struct recv_priv *precvpriv = &padapter->recvpriv; ++ _queue *pfree_recv_queue = &precvpriv->free_recv_queue; ++ ++ ++ transfer_len = (s32)precvbuf->transfer_len; ++ pbuf = precvbuf->pbuf; ++ ++ prxstat = (struct recv_stat *)pbuf; ++ pkt_cnt = (le32_to_cpu(prxstat->rxdw2)>>16) & 0xff; ++ ++#if 0 //temp remove when disable usb rx aggregation ++ if((pkt_cnt > 10) || (pkt_cnt < 1) || (transfer_lenrxdw0, prxstat->rxdw1, prxstat->rxdw2, prxstat->rxdw4)); ++ ++ prxstat = (struct recv_stat *)pbuf; ++ pkt_len = le32_to_cpu(prxstat->rxdw0)&0x00003fff; ++ ++ ++ mf = (le32_to_cpu(prxstat->rxdw1) >> 27) & 0x1;//more fragment bit ++ frag = (le32_to_cpu(prxstat->rxdw2) >> 12) & 0xf;//fragmentation number ++ ++ drvinfo_sz = (le32_to_cpu(prxstat->rxdw0) & 0x000f0000) >> 16; ++ drvinfo_sz = drvinfo_sz << 3;//uint (2^3) = 8 bytes; REG_RX_DRVINFO_SZ ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("recvbuf2recvframe: DRV_INFO_SIZE=%d\n", drvinfo_sz)); ++ ++ pkt_offset = pkt_len + drvinfo_sz + RXDESC_SIZE; ++ ++ if((pkt_len<=0) || (pkt_offset>transfer_len)) ++ { ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("recvbuf2recvframe: pkt_len<=0\n")); ++ goto _exit_recvbuf2recvframe; ++ } ++ ++ // Modified by Albert 20101213 ++ // For 8 bytes IP header alignment. ++ if ( ( le32_to_cpu( prxstat->rxdw0 ) >> 23 ) & 0x01 ) // Qos data, wireless lan header length is 26 ++ { ++ shift_sz = 6; ++ } ++ else ++ { ++ shift_sz = 0; ++ } ++ ++ precvframe = rtw_alloc_recvframe(pfree_recv_queue); ++ if(precvframe==NULL) ++ { ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("recvbuf2recvframe: precvframe==NULL\n")); ++ goto _exit_recvbuf2recvframe; ++ } ++ ++ _rtw_init_listhead(&precvframe->u.hdr.list); ++ precvframe->u.hdr.precvbuf = NULL; //can't access the precvbuf for new arch. ++ precvframe->u.hdr.len=0; ++ ++ //skb_len = pkt_offset; ++ skb_len = pkt_len; ++ ++ // for first fragment packet, driver need allocate 1536+drvinfo_sz+RXDESC_SIZE to defrag packet. ++ // modify alloc_sz for recvive crc error packet by thomas 2011-06-02 ++ if((mf ==1)&&(frag == 0)){ ++ //alloc_sz = 1664; //1664 is 128 alignment. ++ if(skb_len <= 1650) ++ alloc_sz = 1664; ++ else ++ alloc_sz = skb_len + 14; ++ } ++ else { ++ alloc_sz = skb_len; ++ // 6 is for IP header 8 bytes alignment in QoS packet case. ++ // 8 is for skb->data 4 bytes alignment. ++ alloc_sz += 14; ++ } ++ ++ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18)) // http://www.mail-archive.com/netdev@vger.kernel.org/msg17214.html ++ pkt_copy = dev_alloc_skb(alloc_sz); ++#else ++ pkt_copy = netdev_alloc_skb(padapter->pnetdev, alloc_sz); ++#endif ++ if(pkt_copy) ++ { ++ pkt_copy->dev = padapter->pnetdev; ++ precvframe->u.hdr.pkt = pkt_copy; ++ skb_reserve( pkt_copy, 8 - ((SIZE_PTR)( pkt_copy->data ) & 7 ));//force pkt_copy->data at 8-byte alignment address ++ skb_reserve( pkt_copy, shift_sz );//force ip_hdr at 8-byte alignment address according to shift_sz. ++ _rtw_memcpy(pkt_copy->data, (pbuf + drvinfo_sz + RXDESC_SIZE), skb_len); ++ precvframe->u.hdr.rx_head = precvframe->u.hdr.rx_data = precvframe->u.hdr.rx_tail = pkt_copy->data; ++ precvframe->u.hdr.rx_end = pkt_copy->data + alloc_sz; ++ } ++ else ++ { ++ DBG_8192C("recvbuf2recvframe:can not allocate memory for skb copy\n"); ++ //precvframe->u.hdr.pkt = skb_clone(pskb, GFP_ATOMIC); ++ //precvframe->u.hdr.rx_head = precvframe->u.hdr.rx_data = precvframe->u.hdr.rx_tail = pbuf; ++ //precvframe->u.hdr.rx_end = pbuf + (pkt_offset>1612?pkt_offset:1612); ++ ++ precvframe->u.hdr.pkt = NULL; ++ rtw_free_recvframe(precvframe, pfree_recv_queue); ++ ++ goto _exit_recvbuf2recvframe; ++ } ++ ++ recvframe_put(precvframe, skb_len); ++ //recvframe_pull(precvframe, drvinfo_sz + RXDESC_SIZE); ++ ++#ifdef CONFIG_USB_RX_AGGREGATION ++ switch(pHalData->UsbRxAggMode) ++ { ++ case USB_RX_AGG_DMA: ++ case USB_RX_AGG_MIX: ++ pkt_offset = (u16)_RND128(pkt_offset); ++ break; ++ case USB_RX_AGG_USB: ++ pkt_offset = (u16)_RND4(pkt_offset); ++ break; ++ case USB_RX_AGG_DISABLE: ++ default: ++ break; ++ } ++#endif ++ ++ //because the endian issue, driver avoid reference to the rxstat after calling update_recvframe_attrib_from_recvstat(); ++ rtl8192cu_update_recvframe_attrib_from_recvstat(precvframe, prxstat); ++ ++ if(rtw_recv_entry(precvframe) != _SUCCESS) ++ { ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("recvbuf2recvframe: rtw_recv_entry(precvframe) != _SUCCESS\n")); ++ } ++ ++ pkt_cnt--; ++ transfer_len -= pkt_offset; ++ pbuf += pkt_offset; ++ precvframe = NULL; ++ pkt_copy = NULL; ++ ++ if(transfer_len>0 && pkt_cnt==0) ++ pkt_cnt = (le32_to_cpu(prxstat->rxdw2)>>16) & 0xff; ++ ++ }while((transfer_len>0) && (pkt_cnt>0)); ++ ++_exit_recvbuf2recvframe: ++ ++ return _SUCCESS; ++} ++ ++void rtl8192cu_recv_tasklet(void *priv) ++{ ++ struct recv_buf *precvbuf = NULL; ++ _adapter *padapter = (_adapter*)priv; ++ struct recv_priv *precvpriv = &padapter->recvpriv; ++ ++ while (NULL != (precvbuf = rtw_dequeue_recvbuf(&precvpriv->recv_buf_pending_queue))) ++ { ++ if ((padapter->bDriverStopped == _TRUE)||(padapter->bSurpriseRemoved== _TRUE)) ++ { ++ DBG_8192C("recv_tasklet => bDriverStopped or bSurpriseRemoved \n"); ++ ++ break; ++ } ++ ++ ++ recvbuf2recvframe(padapter, precvbuf); ++ ++ rtw_read_port(padapter, precvpriv->ff_hwaddr, 0, (unsigned char *)precvbuf); ++ } ++ ++} ++ ++static void usb_read_port_complete(struct urb *purb, struct pt_regs *regs) ++{ ++ struct recv_buf *precvbuf = (struct recv_buf *)purb->context; ++ _adapter *padapter =(_adapter *)precvbuf->adapter; ++ struct recv_priv *precvpriv = &padapter->recvpriv; ++ ++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port_complete!!!\n")); ++ ++ precvpriv->rx_pending_cnt --; ++ ++ if(padapter->bSurpriseRemoved || padapter->bDriverStopped||padapter->bReadPortCancel) ++ { ++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port_complete:bDriverStopped(%d) OR bSurpriseRemoved(%d)\n", padapter->bDriverStopped, padapter->bSurpriseRemoved)); ++ ++ goto exit; ++ } ++ ++ if(purb->status==0)//SUCCESS ++ { ++ if ((purb->actual_length > MAX_RECVBUF_SZ) || (purb->actual_length < RXDESC_SIZE)) ++ { ++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port_complete: (purb->actual_length > MAX_RECVBUF_SZ) || (purb->actual_length < RXDESC_SIZE)\n")); ++ ++ rtw_read_port(padapter, precvpriv->ff_hwaddr, 0, (unsigned char *)precvbuf); ++ } ++ else ++ { ++ rtw_reset_continual_urb_error(&padapter->dvobjpriv); ++ ++ precvbuf->transfer_len = purb->actual_length; ++ ++ //rtw_enqueue_rx_transfer_buffer(precvpriv, rx_transfer_buf); ++ rtw_enqueue_recvbuf(precvbuf, &precvpriv->recv_buf_pending_queue); ++ ++ tasklet_schedule(&precvpriv->recv_tasklet); ++ } ++ } ++ else ++ { ++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port_complete : purb->status(%d) != 0 \n", purb->status)); ++ ++ DBG_8192C("###=> usb_read_port_complete => urb status(%d)\n", purb->status); ++ ++ if(rtw_inc_and_chk_continual_urb_error(&padapter->dvobjpriv) == _TRUE ){ ++ padapter->bSurpriseRemoved = _TRUE; ++ } ++ ++ switch(purb->status) { ++ case -EINVAL: ++ case -EPIPE: ++ case -ENODEV: ++ case -ESHUTDOWN: ++ //padapter->bSurpriseRemoved=_TRUE; ++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port_complete:bSurpriseRemoved=TRUE\n")); ++ case -ENOENT: ++ padapter->bDriverStopped=_TRUE; ++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port_complete:bDriverStopped=TRUE\n")); ++ break; ++ case -EPROTO: ++ #ifdef DBG_CONFIG_ERROR_DETECT ++ { ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); ++ pHalData->srestpriv.Wifi_Error_Status = USB_READ_PORT_FAIL; ++ } ++ #endif ++ rtw_read_port(padapter, precvpriv->ff_hwaddr, 0, (unsigned char *)precvbuf); ++ break; ++ case -EINPROGRESS: ++ DBG_8192C("ERROR: URB IS IN PROGRESS!/n"); ++ break; ++ default: ++ break; ++ } ++ ++ } ++ ++exit: ++ ++_func_exit_; ++ ++} ++ ++static u32 usb_read_port(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *rmem) ++{ ++ int err; ++ unsigned int pipe; ++ u32 ret = _SUCCESS; ++ PURB purb = NULL; ++ struct recv_buf *precvbuf = (struct recv_buf *)rmem; ++ struct dvobj_priv *pdvobj = (struct dvobj_priv *)pintfhdl->pintf_dev; ++ _adapter *adapter = (_adapter *)pdvobj->padapter; ++ struct recv_priv *precvpriv = &adapter->recvpriv; ++ struct usb_device *pusbd = pdvobj->pusbdev; ++ ++_func_enter_; ++ ++ if(adapter->bDriverStopped || adapter->bSurpriseRemoved ||adapter->pwrctrlpriv.pnp_bstop_trx) ++ { ++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port:( padapter->bDriverStopped ||padapter->bSurpriseRemoved ||adapter->pwrctrlpriv.pnp_bstop_trx)!!!\n")); ++ return _FAIL; ++ } ++ ++ if(precvbuf !=NULL) ++ { ++ rtl8192cu_init_recvbuf(adapter, precvbuf); ++ ++ if(precvbuf->pbuf) ++ { ++ precvpriv->rx_pending_cnt++; ++ ++ purb = precvbuf->purb; ++ ++ //translate DMA FIFO addr to pipehandle ++ pipe = ffaddr2pipehdl(pdvobj, addr); ++ ++ usb_fill_bulk_urb(purb, pusbd, pipe, ++ precvbuf->pbuf, ++ MAX_RECVBUF_SZ, ++ usb_read_port_complete, ++ precvbuf);//context is precvbuf ++ ++ purb->transfer_dma = precvbuf->dma_transfer_addr; ++ purb->transfer_flags |= URB_NO_TRANSFER_DMA_MAP; ++ ++ err = usb_submit_urb(purb, GFP_ATOMIC); ++ if((err) && (err != (-EPERM))) ++ { ++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("cannot submit rx in-token(err=0x%.8x), URB_STATUS =0x%.8x", err, purb->status)); ++ DBG_8192C("cannot submit rx in-token(err = 0x%08x),urb_status = %d\n",err,purb->status); ++ ret = _FAIL; ++ } ++ ++ } ++ ++ } ++ else ++ { ++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port:precvbuf ==NULL\n")); ++ ret = _FAIL; ++ } ++ ++_func_exit_; ++ ++ return ret; ++} ++#else // CONFIG_USE_USB_BUFFER_ALLOC_RX ++static int recvbuf2recvframe(_adapter *padapter, _pkt *pskb) ++{ ++ u8 *pbuf; ++ u8 frag, mf, shift_sz = 0; ++ u16 pkt_cnt, drvinfo_sz; ++ u32 pkt_len, pkt_offset, skb_len, alloc_sz; ++ s32 transfer_len; ++ struct recv_stat *prxstat; ++ _pkt *pkt_copy = NULL; ++ union recv_frame *precvframe = NULL; ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); ++ struct recv_priv *precvpriv = &padapter->recvpriv; ++ _queue *pfree_recv_queue = &precvpriv->free_recv_queue; ++ ++ ++ transfer_len = (s32)pskb->len; ++ pbuf = pskb->data; ++ ++ prxstat = (struct recv_stat *)pbuf; ++ pkt_cnt = (le32_to_cpu(prxstat->rxdw2)>>16) & 0xff; ++ ++#if 0 //temp remove when disable usb rx aggregation ++ if((pkt_cnt > 10) || (pkt_cnt < 1) || (transfer_lenrxdw0, prxstat->rxdw1, prxstat->rxdw2, prxstat->rxdw4)); ++ ++ prxstat = (struct recv_stat *)pbuf; ++ pkt_len = le32_to_cpu(prxstat->rxdw0)&0x00003fff; ++ ++ mf = (le32_to_cpu(prxstat->rxdw1) >> 27) & 0x1;//more fragment bit ++ frag = (le32_to_cpu(prxstat->rxdw2) >> 12) & 0xf;//fragmentation number ++ ++ drvinfo_sz = (le32_to_cpu(prxstat->rxdw0) & 0x000f0000) >> 16; ++ drvinfo_sz = drvinfo_sz << 3;//uint (2^3) = 8 bytes; REG_RX_DRVINFO_SZ ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("recvbuf2recvframe: DRV_INFO_SIZE=%d\n", drvinfo_sz)); ++ ++ pkt_offset = pkt_len + drvinfo_sz + RXDESC_SIZE; ++ ++ if((pkt_len<=0) || (pkt_offset>transfer_len)) ++ { ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("recvbuf2recvframe: pkt_len<=0\n")); ++ goto _exit_recvbuf2recvframe; ++ } ++ ++ // Modified by Albert 20101213 ++ // For 8 bytes IP header alignment. ++ if ( ( le32_to_cpu( prxstat->rxdw0 ) >> 23 ) & 0x01 ) // Qos data, wireless lan header length is 26 ++ { ++ shift_sz = 6; ++ } ++ else ++ { ++ shift_sz = 0; ++ } ++ ++ precvframe = rtw_alloc_recvframe(pfree_recv_queue); ++ if(precvframe==NULL) ++ { ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("recvbuf2recvframe: precvframe==NULL\n")); ++ goto _exit_recvbuf2recvframe; ++ } ++ ++ _rtw_init_listhead(&precvframe->u.hdr.list); ++ precvframe->u.hdr.precvbuf = NULL; //can't access the precvbuf for new arch. ++ precvframe->u.hdr.len=0; ++ ++ //skb_len = pkt_offset; ++ skb_len = pkt_len; ++ ++ // for first fragment packet, driver need allocate 1536+drvinfo_sz+RXDESC_SIZE to defrag packet. ++ // modify alloc_sz for recvive crc error packet by thomas 2011-06-02 ++ if((mf ==1)&&(frag == 0)){ ++ //alloc_sz = 1664; //1664 is 128 alignment. ++ if(skb_len <= 1650) ++ alloc_sz = 1664; ++ else ++ alloc_sz = skb_len + 14; ++ } ++ else { ++ alloc_sz = skb_len; ++ // 6 is for IP header 8 bytes alignment in QoS packet case. ++ // 8 is for skb->data 4 bytes alignment. ++ alloc_sz += 14; ++ } ++ ++ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18)) // http://www.mail-archive.com/netdev@vger.kernel.org/msg17214.html ++ pkt_copy = dev_alloc_skb(alloc_sz); ++#else ++ pkt_copy = netdev_alloc_skb(padapter->pnetdev, alloc_sz); ++#endif ++ if(pkt_copy) ++ { ++ pkt_copy->dev = padapter->pnetdev; ++ precvframe->u.hdr.pkt = pkt_copy; ++ skb_reserve( pkt_copy, 8 - ((SIZE_PTR)( pkt_copy->data ) & 7 ));//force pkt_copy->data at 8-byte alignment address ++ skb_reserve( pkt_copy, shift_sz );//force ip_hdr at 8-byte alignment address according to shift_sz. ++ _rtw_memcpy(pkt_copy->data, (pbuf + drvinfo_sz + RXDESC_SIZE), skb_len); ++ precvframe->u.hdr.rx_head = precvframe->u.hdr.rx_data = precvframe->u.hdr.rx_tail = pkt_copy->data; ++ precvframe->u.hdr.rx_end = pkt_copy->data + alloc_sz; ++ } ++ else ++ { ++ precvframe->u.hdr.pkt = skb_clone(pskb, GFP_ATOMIC); ++ if(pkt_copy) ++ { ++ precvframe->u.hdr.rx_head = precvframe->u.hdr.rx_data = precvframe->u.hdr.rx_tail = pbuf; ++ precvframe->u.hdr.rx_end = pbuf + alloc_sz; ++ } ++ else ++ { ++ DBG_8192C("recvbuf2recvframe: skb_clone fail\n"); ++ goto _exit_recvbuf2recvframe; ++ } ++ } ++ ++ recvframe_put(precvframe, skb_len); ++ //recvframe_pull(precvframe, drvinfo_sz + RXDESC_SIZE); ++ ++#ifdef CONFIG_USB_RX_AGGREGATION ++ switch(pHalData->UsbRxAggMode) ++ { ++ case USB_RX_AGG_DMA: ++ case USB_RX_AGG_MIX: ++ pkt_offset = (u16)_RND128(pkt_offset); ++ break; ++ case USB_RX_AGG_USB: ++ pkt_offset = (u16)_RND4(pkt_offset); ++ break; ++ case USB_RX_AGG_DISABLE: ++ default: ++ break; ++ } ++#endif ++ ++ //because the endian issue, driver avoid reference to the rxstat after calling update_recvframe_attrib_from_recvstat(); ++ rtl8192cu_update_recvframe_attrib_from_recvstat(precvframe, prxstat); ++ ++ if(rtw_recv_entry(precvframe) != _SUCCESS) ++ { ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("recvbuf2recvframe: rtw_recv_entry(precvframe) != _SUCCESS\n")); ++ } ++ ++ pkt_cnt--; ++ transfer_len -= pkt_offset; ++ pbuf += pkt_offset; ++ precvframe = NULL; ++ pkt_copy = NULL; ++ ++ if(transfer_len>0 && pkt_cnt==0) ++ pkt_cnt = (le32_to_cpu(prxstat->rxdw2)>>16) & 0xff; ++ ++ }while((transfer_len>0) && (pkt_cnt>0)); ++ ++_exit_recvbuf2recvframe: ++ ++ return _SUCCESS; ++} ++ ++void rtl8192cu_recv_tasklet(void *priv) ++{ ++ _pkt *pskb; ++ _adapter *padapter = (_adapter*)priv; ++ struct recv_priv *precvpriv = &padapter->recvpriv; ++ ++ while (NULL != (pskb = skb_dequeue(&precvpriv->rx_skb_queue))) ++ { ++ if ((padapter->bDriverStopped == _TRUE)||(padapter->bSurpriseRemoved== _TRUE)) ++ { ++ DBG_8192C("recv_tasklet => bDriverStopped or bSurpriseRemoved \n"); ++ dev_kfree_skb_any(pskb); ++ break; ++ } ++ ++ recvbuf2recvframe(padapter, pskb); ++ ++#ifdef CONFIG_PREALLOC_RECV_SKB ++ ++#ifdef NET_SKBUFF_DATA_USES_OFFSET ++ skb_reset_tail_pointer(pskb); ++#else ++ pskb->tail = pskb->data; ++#endif ++ pskb->len = 0; ++ ++ skb_queue_tail(&precvpriv->free_recv_skb_queue, pskb); ++ ++#else ++ dev_kfree_skb_any(pskb); ++#endif ++ ++ } ++ ++} ++ ++ ++static void usb_read_port_complete(struct urb *purb, struct pt_regs *regs) ++{ ++ _irqL irqL; ++ uint isevt, *pbuf; ++ struct recv_buf *precvbuf = (struct recv_buf *)purb->context; ++ _adapter *padapter =(_adapter *)precvbuf->adapter; ++ struct recv_priv *precvpriv = &padapter->recvpriv; ++ ++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port_complete!!!\n")); ++ ++ //_enter_critical(&precvpriv->lock, &irqL); ++ //precvbuf->irp_pending=_FALSE; ++ //precvpriv->rx_pending_cnt --; ++ //_exit_critical(&precvpriv->lock, &irqL); ++ ++ precvpriv->rx_pending_cnt --; ++ ++ //if(precvpriv->rx_pending_cnt== 0) ++ //{ ++ // RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port_complete: rx_pending_cnt== 0, set allrxreturnevt!\n")); ++ // _rtw_up_sema(&precvpriv->allrxreturnevt); ++ //} ++ ++ if(padapter->bSurpriseRemoved || padapter->bDriverStopped||padapter->bReadPortCancel) ++ { ++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port_complete:bDriverStopped(%d) OR bSurpriseRemoved(%d)\n", padapter->bDriverStopped, padapter->bSurpriseRemoved)); ++ ++ #ifdef CONFIG_PREALLOC_RECV_SKB ++ precvbuf->reuse = _TRUE; ++ #else ++ if(precvbuf->pskb){ ++ DBG_8192C("==> free skb(%p)\n",precvbuf->pskb); ++ dev_kfree_skb_any(precvbuf->pskb); ++ } ++ #endif ++ ++ goto exit; ++ } ++ ++ if(purb->status==0)//SUCCESS ++ { ++ if ((purb->actual_length > MAX_RECVBUF_SZ) || (purb->actual_length < RXDESC_SIZE)) ++ { ++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port_complete: (purb->actual_length > MAX_RECVBUF_SZ) || (purb->actual_length < RXDESC_SIZE)\n")); ++ precvbuf->reuse = _TRUE; ++ rtw_read_port(padapter, precvpriv->ff_hwaddr, 0, (unsigned char *)precvbuf); ++ } ++ else ++ { ++ rtw_reset_continual_urb_error(&padapter->dvobjpriv); ++ ++ precvbuf->transfer_len = purb->actual_length; ++ skb_put(precvbuf->pskb, purb->actual_length); ++ skb_queue_tail(&precvpriv->rx_skb_queue, precvbuf->pskb); ++ ++ if (skb_queue_len(&precvpriv->rx_skb_queue)<=1) ++ tasklet_schedule(&precvpriv->recv_tasklet); ++ ++ precvbuf->pskb = NULL; ++ precvbuf->reuse = _FALSE; ++ rtw_read_port(padapter, precvpriv->ff_hwaddr, 0, (unsigned char *)precvbuf); ++ } ++ } ++ else ++ { ++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port_complete : purb->status(%d) != 0 \n", purb->status)); ++ ++ DBG_8192C("###=> usb_read_port_complete => urb status(%d)\n", purb->status); ++ ++ if(rtw_inc_and_chk_continual_urb_error(&padapter->dvobjpriv) == _TRUE ){ ++ padapter->bSurpriseRemoved = _TRUE; ++ } ++ ++ switch(purb->status) { ++ case -EINVAL: ++ case -EPIPE: ++ case -ENODEV: ++ case -ESHUTDOWN: ++ //padapter->bSurpriseRemoved=_TRUE; ++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port_complete:bSurpriseRemoved=TRUE\n")); ++ case -ENOENT: ++ padapter->bDriverStopped=_TRUE; ++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port_complete:bDriverStopped=TRUE\n")); ++ break; ++ case -EPROTO: ++ #ifdef DBG_CONFIG_ERROR_DETECT ++ { ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); ++ pHalData->srestpriv.Wifi_Error_Status = USB_READ_PORT_FAIL; ++ } ++ #endif ++ precvbuf->reuse = _TRUE; ++ rtw_read_port(padapter, precvpriv->ff_hwaddr, 0, (unsigned char *)precvbuf); ++ break; ++ case -EINPROGRESS: ++ DBG_8192C("ERROR: URB IS IN PROGRESS!/n"); ++ break; ++ default: ++ break; ++ } ++ ++ } ++ ++exit: ++ ++_func_exit_; ++ ++} ++ ++static u32 usb_read_port(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *rmem) ++{ ++ _irqL irqL; ++ int err; ++ unsigned int pipe; ++ SIZE_PTR tmpaddr=0; ++ SIZE_PTR alignment=0; ++ u32 ret = _SUCCESS; ++ PURB purb = NULL; ++ struct recv_buf *precvbuf = (struct recv_buf *)rmem; ++ struct dvobj_priv *pdvobj = (struct dvobj_priv *)pintfhdl->pintf_dev; ++ _adapter *adapter = (_adapter *)pdvobj->padapter; ++ struct recv_priv *precvpriv = &adapter->recvpriv; ++ struct usb_device *pusbd = pdvobj->pusbdev; ++ ++ ++_func_enter_; ++ ++ if(adapter->bDriverStopped || adapter->bSurpriseRemoved ||adapter->pwrctrlpriv.pnp_bstop_trx) ++ { ++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port:( padapter->bDriverStopped ||padapter->bSurpriseRemoved ||adapter->pwrctrlpriv.pnp_bstop_trx)!!!\n")); ++ return _FAIL; ++ } ++ ++#ifdef CONFIG_PREALLOC_RECV_SKB ++ if((precvbuf->reuse == _FALSE) || (precvbuf->pskb == NULL)) ++ { ++ if (NULL != (precvbuf->pskb = skb_dequeue(&precvpriv->free_recv_skb_queue))) ++ { ++ precvbuf->reuse = _TRUE; ++ } ++ } ++#endif ++ ++ ++ if(precvbuf !=NULL) ++ { ++ rtl8192cu_init_recvbuf(adapter, precvbuf); ++ ++ //re-assign for linux based on skb ++ if((precvbuf->reuse == _FALSE) || (precvbuf->pskb == NULL)) ++ { ++ //precvbuf->pskb = alloc_skb(MAX_RECVBUF_SZ, GFP_ATOMIC);//don't use this after v2.6.25 ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18)) // http://www.mail-archive.com/netdev@vger.kernel.org/msg17214.html ++ precvbuf->pskb = dev_alloc_skb(MAX_RECVBUF_SZ + RECVBUFF_ALIGN_SZ); ++#else ++ precvbuf->pskb = netdev_alloc_skb(adapter->pnetdev, MAX_RECVBUF_SZ + RECVBUFF_ALIGN_SZ); ++#endif ++ if(precvbuf->pskb == NULL) ++ { ++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("init_recvbuf(): alloc_skb fail!\n")); ++ return _FAIL; ++ } ++ ++ tmpaddr = (SIZE_PTR)precvbuf->pskb->data; ++ alignment = tmpaddr & (RECVBUFF_ALIGN_SZ-1); ++ skb_reserve(precvbuf->pskb, (RECVBUFF_ALIGN_SZ - alignment)); ++ ++ precvbuf->phead = precvbuf->pskb->head; ++ precvbuf->pdata = precvbuf->pskb->data; ++ ++#ifdef NET_SKBUFF_DATA_USES_OFFSET ++ precvbuf->ptail = precvbuf->pskb->head + precvbuf->pskb->tail; ++ precvbuf->pend = precvbuf->ptail + (MAX_RECVBUF_SZ + RECVBUFF_ALIGN_SZ); ++#else ++ precvbuf->ptail = precvbuf->pskb->tail; ++ precvbuf->pend = precvbuf->pskb->end; ++#endif ++ precvbuf->pbuf = precvbuf->pskb->data; ++ } ++ else//reuse skb ++ { ++ precvbuf->phead = precvbuf->pskb->head; ++ precvbuf->pdata = precvbuf->pskb->data; ++ ++#ifdef NET_SKBUFF_DATA_USES_OFFSET ++ precvbuf->ptail = precvbuf->pskb->head + precvbuf->pskb->tail; ++ precvbuf->pend = precvbuf->ptail + (MAX_RECVBUF_SZ + RECVBUFF_ALIGN_SZ); ++#else ++ precvbuf->ptail = precvbuf->pskb->tail; ++ precvbuf->pend = precvbuf->pskb->end; ++#endif ++ precvbuf->pbuf = precvbuf->pskb->data; ++ ++ precvbuf->reuse = _FALSE; ++ } ++ ++ //_enter_critical(&precvpriv->lock, &irqL); ++ //precvpriv->rx_pending_cnt++; ++ //precvbuf->irp_pending = _TRUE; ++ //_exit_critical(&precvpriv->lock, &irqL); ++ ++ precvpriv->rx_pending_cnt++; ++ ++ purb = precvbuf->purb; ++ ++ //translate DMA FIFO addr to pipehandle ++ pipe = ffaddr2pipehdl(pdvobj, addr); ++ ++ usb_fill_bulk_urb(purb, pusbd, pipe, ++ precvbuf->pbuf, ++ MAX_RECVBUF_SZ, ++ usb_read_port_complete, ++ precvbuf);//context is precvbuf ++ ++ err = usb_submit_urb(purb, GFP_ATOMIC); ++ if((err) && (err != (-EPERM))) ++ { ++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("cannot submit rx in-token(err=0x%.8x), URB_STATUS =0x%.8x", err, purb->status)); ++ DBG_8192C("cannot submit rx in-token(err = 0x%08x),urb_status = %d\n",err,purb->status); ++ ret = _FAIL; ++ } ++ } ++ else ++ { ++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port:precvbuf ==NULL\n")); ++ ret = _FAIL; ++ } ++ ++_func_exit_; ++ ++ return ret; ++} ++#endif // CONFIG_USE_USB_BUFFER_ALLOC_RX ++ ++static void usb_read_port_cancel(struct intf_hdl *pintfhdl) ++{ ++ int i; ++ struct recv_buf *precvbuf; ++ _adapter *padapter = pintfhdl->padapter; ++ precvbuf = (struct recv_buf *)padapter->recvpriv.precv_buf; ++ ++ DBG_8192C("usb_read_port_cancel \n"); ++ ++ padapter->bReadPortCancel = _TRUE; ++ ++ for(i=0; i < NR_RECVBUFF ; i++) ++ { ++ precvbuf->reuse = _TRUE; ++ if(precvbuf->purb) ++ { ++ //DBG_8192C("usb_read_port_cancel : usb_kill_urb \n"); ++ usb_kill_urb(precvbuf->purb); ++ } ++ ++ precvbuf++; ++ } ++ ++#ifdef CONFIG_USB_INTERRUPT_IN_PIPE ++ usb_kill_urb(padapter->recvpriv.int_in_urb); ++#endif ++} ++ ++void rtl8192cu_xmit_tasklet(void *priv) ++{ ++ int ret = _FALSE; ++ _adapter *padapter = (_adapter*)priv; ++ struct xmit_priv *pxmitpriv = &padapter->xmitpriv; ++ ++ if(check_fwstate(&padapter->mlmepriv, _FW_UNDER_SURVEY) == _TRUE) ++ return; ++ ++ while(1) ++ { ++ if ((padapter->bDriverStopped == _TRUE)||(padapter->bSurpriseRemoved== _TRUE) || (padapter->bWritePortCancel == _TRUE)) ++ { ++ DBG_8192C("xmit_tasklet => bDriverStopped or bSurpriseRemoved or bWritePortCancel\n"); ++ break; ++ } ++ ++ ret = rtl8192cu_xmitframe_complete(padapter, pxmitpriv, NULL); ++ ++ if(ret==_FALSE) ++ break; ++ ++ } ++ ++} ++ ++static void usb_write_port_complete(struct urb *purb, struct pt_regs *regs) ++{ ++ _irqL irqL; ++ int i; ++ struct xmit_buf *pxmitbuf = (struct xmit_buf *)purb->context; ++ //struct xmit_frame *pxmitframe = (struct xmit_frame *)pxmitbuf->priv_data; ++ //_adapter *padapter = pxmitframe->padapter; ++ _adapter *padapter = pxmitbuf->padapter; ++ struct xmit_priv *pxmitpriv = &padapter->xmitpriv; ++ //struct pkt_attrib *pattrib = &pxmitframe->attrib; ++ ++_func_enter_; ++ ++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("+usb_write_port_complete\n")); ++ ++ ++ switch(pxmitbuf->flags) ++ { ++ case XMIT_VO_QUEUE: ++ pxmitpriv->voq_cnt--; ++ break; ++ case XMIT_VI_QUEUE: ++ pxmitpriv->viq_cnt--; ++ break; ++ case XMIT_BE_QUEUE: ++ pxmitpriv->beq_cnt--; ++ break; ++ case XMIT_BK_QUEUE: ++ pxmitpriv->bkq_cnt--; ++ break; ++ case HIGH_QUEUE_INX: ++#ifdef CONFIG_AP_MODE ++ rtw_chk_hi_queue_cmd(padapter); ++#endif ++ break; ++ default: ++ break; ++ } ++ ++ ++/* ++ _enter_critical(&pxmitpriv->lock, &irqL); ++ ++ pxmitpriv->txirp_cnt--; ++ ++ switch(pattrib->priority) ++ { ++ case 1: ++ case 2: ++ pxmitpriv->bkq_cnt--; ++ //DBG_8192C("pxmitpriv->bkq_cnt=%d\n", pxmitpriv->bkq_cnt); ++ break; ++ case 4: ++ case 5: ++ pxmitpriv->viq_cnt--; ++ //DBG_8192C("pxmitpriv->viq_cnt=%d\n", pxmitpriv->viq_cnt); ++ break; ++ case 6: ++ case 7: ++ pxmitpriv->voq_cnt--; ++ //DBG_8192C("pxmitpriv->voq_cnt=%d\n", pxmitpriv->voq_cnt); ++ break; ++ case 0: ++ case 3: ++ default: ++ pxmitpriv->beq_cnt--; ++ //DBG_8192C("pxmitpriv->beq_cnt=%d\n", pxmitpriv->beq_cnt); ++ break; ++ ++ } ++ ++ _exit_critical(&pxmitpriv->lock, &irqL); ++ ++ ++ if(pxmitpriv->txirp_cnt==0) ++ { ++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_write_port_complete: txirp_cnt== 0, set allrxreturnevt!\n")); ++ _rtw_up_sema(&(pxmitpriv->tx_retevt)); ++ } ++*/ ++ //rtw_free_xmitframe_ex(pxmitpriv, pxmitframe); ++ ++ if(padapter->bSurpriseRemoved || padapter->bDriverStopped ||padapter->bWritePortCancel) ++ { ++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_write_port_complete:bDriverStopped(%d) OR bSurpriseRemoved(%d)", padapter->bDriverStopped, padapter->bSurpriseRemoved)); ++ goto check_completion; ++ } ++ ++ ++ if(purb->status==0) ++ { ++ ++ } ++ else ++ { ++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_write_port_complete : purb->status(%d) != 0 \n", purb->status)); ++ DBG_8192C("###=> urb_write_port_complete status(%d)\n",purb->status); ++ if((purb->status==-EPIPE)||(purb->status==-EPROTO)) ++ { ++ //usb_clear_halt(pusbdev, purb->pipe); ++ //msleep(10); ++ #ifdef DBG_CONFIG_ERROR_DETECT ++ { ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); ++ pHalData->srestpriv.Wifi_Error_Status = USB_WRITE_PORT_FAIL; ++ } ++ #endif ++ } ++ else if(purb->status == -EINPROGRESS) ++ { ++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_write_port_complete: EINPROGESS\n")); ++ } ++ else if(purb->status == (-ESHUTDOWN)) ++ { ++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_write_port_complete: ESHUTDOWN\n")); ++ ++ padapter->bDriverStopped=_TRUE; ++ ++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_write_port_complete:bDriverStopped=TRUE\n")); ++ ++ goto check_completion; ++ } ++ else ++ { ++ padapter->bSurpriseRemoved=_TRUE; ++ DBG_8192C("bSurpriseRemoved=TRUE\n"); ++ //rtl8192cu_trigger_gpio_0(padapter); ++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_write_port_complete:bSurpriseRemoved=TRUE\n")); ++ ++ goto check_completion; ++ } ++ ++ ++ ++ } ++ ++ #ifdef DBG_CONFIG_ERROR_DETECT ++ { ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); ++ pHalData->srestpriv.last_tx_complete_time = rtw_get_current_time(); ++ } ++ #endif ++ ++check_completion: ++ if(pxmitbuf->isSync) { ++ pxmitbuf->status = purb->status; ++ complete(&pxmitbuf->done); ++ } ++ ++ rtw_free_xmitbuf(pxmitpriv, pxmitbuf); ++ ++ //if(rtw_txframes_pending(padapter)) ++ { ++ tasklet_hi_schedule(&pxmitpriv->xmit_tasklet); ++ } ++ ++ ++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("-usb_write_port_complete\n")); ++_func_exit_; ++ ++} ++ ++static u32 usb_write_port(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *wmem, int timeout_ms) ++{ ++ _irqL irqL; ++ unsigned int pipe; ++ int status; ++ u32 ret, bwritezero = _FALSE; ++ PURB purb = NULL; ++ _adapter *padapter = (_adapter *)pintfhdl->padapter; ++ struct dvobj_priv *pdvobj = (struct dvobj_priv *)&padapter->dvobjpriv; ++ struct xmit_priv *pxmitpriv = &padapter->xmitpriv; ++ struct xmit_buf *pxmitbuf = (struct xmit_buf *)wmem; ++ struct xmit_frame *pxmitframe = (struct xmit_frame *)pxmitbuf->priv_data; ++ struct usb_device *pusbd = pdvobj->pusbdev; ++ struct pkt_attrib *pattrib = &pxmitframe->attrib; ++ ++_func_enter_; ++ ++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("+usb_write_port\n")); ++ ++ if((padapter->bDriverStopped) || (padapter->bSurpriseRemoved) ||(padapter->pwrctrlpriv.pnp_bstop_trx)) ++ { ++ #ifdef DBG_TX ++ DBG_871X(" DBG_TX %s:%d bDriverStopped%d, bSurpriseRemoved:%d, pnp_bstop_trx:%d\n",__FUNCTION__, __LINE__ ++ ,padapter->bDriverStopped, padapter->bSurpriseRemoved, padapter->pwrctrlpriv.pnp_bstop_trx ); ++ #endif ++ ++ rtw_free_xmitbuf(pxmitpriv, pxmitbuf); ++ ++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_write_port:( padapter->bDriverStopped ||padapter->bSurpriseRemoved ||adapter->pwrctrlpriv.pnp_bstop_trx)!!!\n")); ++ return _FAIL; ++ } ++ ++ _enter_critical(&pxmitpriv->lock, &irqL); ++ ++ switch(addr) ++ { ++ case VO_QUEUE_INX: ++ pxmitpriv->voq_cnt++; ++ pxmitbuf->flags = XMIT_VO_QUEUE; ++ break; ++ case VI_QUEUE_INX: ++ pxmitpriv->viq_cnt++; ++ pxmitbuf->flags = XMIT_VI_QUEUE; ++ break; ++ case BE_QUEUE_INX: ++ pxmitpriv->beq_cnt++; ++ pxmitbuf->flags = XMIT_BE_QUEUE; ++ break; ++ case BK_QUEUE_INX: ++ pxmitpriv->bkq_cnt++; ++ pxmitbuf->flags = XMIT_BK_QUEUE; ++ break; ++ case HIGH_QUEUE_INX: ++ pxmitbuf->flags = HIGH_QUEUE_INX; ++ break; ++ default: ++ pxmitbuf->flags = XMIT_VO_QUEUE; ++ break; ++ } ++ ++ _exit_critical(&pxmitpriv->lock, &irqL); ++ ++/* ++ _enter_critical(&pxmitpriv->lock, &irqL); ++ ++ //total irp ++ pxmitpriv->txirp_cnt++; ++ ++ //per ac irp ++ switch(pattrib->priority) ++ { ++ case 1: ++ case 2: ++ pxmitpriv->bkq_cnt++; ++ break; ++ case 4: ++ case 5: ++ pxmitpriv->viq_cnt++; ++ break; ++ case 6: ++ case 7: ++ pxmitpriv->voq_cnt++; ++ break; ++ case 0: ++ case 3: ++ default: ++ pxmitpriv->beq_cnt++; ++ break; ++ } ++ ++ ++ _exit_critical(&pxmitpriv->lock, &irqL); ++*/ ++ ++ purb = pxmitbuf->pxmit_urb[0]; ++ ++#if 0 ++ if(pdvobj->ishighspeed) ++ { ++ if(cnt> 0 && cnt%512 == 0) ++ { ++ //DBG_8192C("ishighspeed, cnt=%d\n", cnt); ++ bwritezero = _TRUE; ++ } ++ } ++ else ++ { ++ if(cnt > 0 && cnt%64 == 0) ++ { ++ //DBG_8192C("cnt=%d\n", cnt); ++ bwritezero = _TRUE; ++ } ++ } ++#endif ++ ++ //translate DMA FIFO addr to pipehandle ++ pipe = ffaddr2pipehdl(pdvobj, addr); ++ ++#ifdef CONFIG_REDUCE_USB_TX_INT ++ if ( pxmitpriv->free_xmitbuf_cnt%NR_XMITBUFF == 0 ++ || pxmitbuf->ext_tag ) ++ { ++ purb->transfer_flags &= (~URB_NO_INTERRUPT); ++ } else { ++ purb->transfer_flags |= URB_NO_INTERRUPT; ++ //DBG_8192C("URB_NO_INTERRUPT "); ++ } ++#endif ++ ++ ++ usb_fill_bulk_urb(purb, pusbd, pipe, ++ pxmitframe->buf_addr, //= pxmitbuf->pbuf ++ cnt, ++ usb_write_port_complete, ++ pxmitbuf);//context is pxmitbuf ++ ++#ifdef CONFIG_USE_USB_BUFFER_ALLOC_TX ++ purb->transfer_dma = pxmitbuf->dma_transfer_addr; ++ purb->transfer_flags |= URB_NO_TRANSFER_DMA_MAP; ++ purb->transfer_flags |= URB_ZERO_PACKET; ++#endif // CONFIG_USE_USB_BUFFER_ALLOC_TX ++ ++#if 0 ++ if (bwritezero) ++ { ++ purb->transfer_flags |= URB_ZERO_PACKET; ++ } ++#endif ++ ++ status = usb_submit_urb(purb, GFP_ATOMIC); ++ ++ if (!status) ++ { ++ ret= _SUCCESS; ++ #ifdef DBG_CONFIG_ERROR_DETECT ++ { ++ HAL_DATA_TYPE *pHalData = GET_HAL_DATA(padapter); ++ pHalData->srestpriv.last_tx_time = rtw_get_current_time(); ++ } ++ #endif ++ } ++ else ++ { ++ DBG_8192C("usb_write_port, status=%d\n", status); ++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_write_port(): usb_submit_urb, status=%x\n", status)); ++ ret= _FAIL; ++ } ++ ++// Commented by Albert 2009/10/13 ++// We add the URB_ZERO_PACKET flag to urb so that the host will send the zero packet automatically. ++/* ++ if(bwritezero == _TRUE) ++ { ++ usb_bulkout_zero(pintfhdl, addr); ++ } ++*/ ++ ++ // synchronous write handling ++ if(timeout_ms >= 0) { ++ unsigned long expire = timeout_ms ? msecs_to_jiffies(timeout_ms) : MAX_SCHEDULE_TIMEOUT; ++ int status; ++ init_completion(&pxmitbuf->done); ++ pxmitbuf->isSync = _TRUE; ++ pxmitbuf->status = 0; ++ ++ if (!wait_for_completion_timeout(&pxmitbuf->done, expire)) { ++ usb_kill_urb(purb); ++ status = (pxmitbuf->status == -ENOENT ? -ETIMEDOUT : pxmitbuf->status); ++ } else ++ status = pxmitbuf->status; ++ ++ if (!status) { ++ ret= _SUCCESS; ++ } else { ++ DBG_8192C("usb_write_port sync, status=%d\n", status); ++ ret = _FAIL; ++ } ++ } ++ ++ ++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("-usb_write_port\n")); ++ ++_func_exit_; ++ ++ return ret; ++ ++} ++ ++static inline u32 usb_write_port_async(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *wmem) ++{ ++ return usb_write_port(pintfhdl, addr, cnt, wmem, -1); ++} ++ ++static inline int usb_write_port_sync(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *wmem) ++{ ++ return usb_write_port(pintfhdl, addr, cnt, wmem, RTW_USB_BULKOUT_TIMEOUT); ++} ++ ++static void usb_write_port_cancel(struct intf_hdl *pintfhdl) ++{ ++ int i, j; ++ _adapter *padapter = pintfhdl->padapter; ++ struct xmit_buf *pxmitbuf = (struct xmit_buf *)padapter->xmitpriv.pxmitbuf; ++ ++ DBG_8192C("usb_write_port_cancel \n"); ++ ++ padapter->bWritePortCancel = _TRUE; ++ ++ for(i=0; ipxmit_urb[j]) ++ { ++ usb_kill_urb(pxmitbuf->pxmit_urb[j]); ++ } ++ } ++ ++ pxmitbuf++; ++ } ++ pxmitbuf = (struct xmit_buf*)padapter->xmitpriv.pxmit_extbuf; ++ ++ for (i = 0; i < NR_XMIT_EXTBUFF; i++) ++ { ++ for(j=0; j<8; j++) ++ { ++ if(pxmitbuf->pxmit_urb[j]) ++ { ++ usb_kill_urb(pxmitbuf->pxmit_urb[j]); ++ } ++ } ++ ++ pxmitbuf++; ++ } ++ ++} ++ ++void rtl8192cu_set_intf_ops(struct _io_ops *pops) ++{ ++ _func_enter_; ++ ++ _rtw_memset((u8 *)pops, 0, sizeof(struct _io_ops)); ++ ++ pops->_read8 = &usb_read8; ++ pops->_read16 = &usb_read16; ++ pops->_read32 = &usb_read32; ++ pops->_read_mem = &usb_read_mem; ++ pops->_read_port = &usb_read_port; ++ ++ pops->_write8 = &usb_write8; ++ pops->_write16 = &usb_write16; ++ pops->_write32 = &usb_write32; ++ pops->_writeN = &usb_writeN; ++ ++#ifdef CONFIG_USB_SUPPORT_ASYNC_VDN_REQ ++ pops->_write8_async= &usb_async_write8; ++ pops->_write16_async = &usb_async_write16; ++ pops->_write32_async = &usb_async_write32; ++#endif ++ pops->_write_mem = &usb_write_mem; ++ pops->_write_port = &usb_write_port_async; ++ pops->_write_port_sync = &usb_write_port_sync; ++ ++ pops->_read_port_cancel = &usb_read_port_cancel; ++ pops->_write_port_cancel = &usb_write_port_cancel; ++ ++#ifdef CONFIG_USB_INTERRUPT_IN_PIPE ++ pops->_read_interrupt = &usb_read_interrupt; ++#endif ++ ++ _func_exit_; ++ ++} ++ +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/hal/rtl8192c/usb/usb_ops_xp.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/hal/rtl8192c/usb/usb_ops_xp.c 2013-07-26 19:36:06.000000000 +0000 +@@ -0,0 +1,1266 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ++******************************************************************************/ ++#define _HCI_OPS_OS_C_ ++ ++#include ++#include ++#include ++#include ++#include ++ ++#if defined (PLATFORM_LINUX) && defined (PLATFORM_WINDOWS) ++ #error "Shall be Linux or Windows, but not both!\n" ++#endif ++ ++#ifndef CONFIG_USB_HCI ++ #error "CONFIG_USB_HCI shall be on!\n" ++#endif ++ ++ ++#include ++#include ++#include ++ ++#include ++#include ++ ++#include ++ ++ ++struct zero_bulkout_context ++{ ++ void *pbuf; ++ void *purb; ++ void *pirp; ++ void *padapter; ++}; ++ ++#define usb_write_cmd usb_write_mem ++#define usb_read_cmd usb_read_mem ++#define usb_write_cmd_complete usb_write_mem_complete ++//#define usb_read_cmd_complete usb_read_mem_complete ++ ++ ++ ++uint usb_init_intf_priv(struct intf_priv *pintfpriv) ++{ ++ ++ PURB piorw_urb; ++ u8 NextDeviceStackSize; ++ struct dvobj_priv *pdev = (struct dvobj_priv *)pintfpriv->intf_dev; ++ _adapter * padapter=pdev->padapter; ++ ++_func_enter_; ++ ++ RT_TRACE(_module_hci_ops_os_c_,_drv_info_,("\n +usb_init_intf_priv\n")); ++ ++ pintfpriv->intf_status = _IOREADY; ++ ++ if(pdev->ishighspeed) pintfpriv->max_iosz = 128; ++ else pintfpriv->max_iosz = 64; ++ ++ ++ _init_timer(&pintfpriv->io_timer, padapter->hndis_adapter, io_irp_timeout_handler, pintfpriv); ++ ++ ++ RT_TRACE(_module_hci_ops_os_c_,_drv_info_,("usb_init_intf_priv:pintfpriv->max_iosz:%d\n",pintfpriv->max_iosz)); ++ ++ pintfpriv->io_wsz = 0; ++ pintfpriv->io_rsz = 0; ++ ++ pintfpriv->allocated_io_rwmem = rtw_zmalloc(pintfpriv->max_iosz +4); ++ ++ if (pintfpriv->allocated_io_rwmem == NULL){ ++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("\n usb_init_intf_priv:pintfpriv->allocated_io_rwmem == NULL\n")); ++ goto usb_init_intf_priv_fail; ++ } ++ ++ pintfpriv->io_rwmem = pintfpriv->allocated_io_rwmem + 4 \ ++ -( (u32)(pintfpriv->allocated_io_rwmem) & 3); ++ ++ ++ ++ NextDeviceStackSize = (u8)pdev->nextdevstacksz;//pintfpriv->pUsbDevObj->StackSize + 1; ++ ++ piorw_urb = (PURB)ExAllocatePool(NonPagedPool, sizeof(URB) ); ++ if(piorw_urb == NULL) ++ goto usb_init_intf_priv_fail; ++ ++ pintfpriv->piorw_urb = piorw_urb; ++ ++ pintfpriv->piorw_irp = IoAllocateIrp(NextDeviceStackSize , FALSE); ++ ++ ++ pintfpriv->io_irp_cnt=1; ++ pintfpriv->bio_irp_pending=_FALSE; ++ ++ _rtw_init_sema(&(pintfpriv->io_retevt), 0);//NdisInitializeEvent(&pintfpriv->io_irp_return_evt); ++ ++_func_exit_; ++ return _SUCCESS; ++ ++usb_init_intf_priv_fail: ++ ++ if (pintfpriv->allocated_io_rwmem) ++ rtw_mfree((u8 *)(pintfpriv->allocated_io_rwmem), pintfpriv->max_iosz +4); ++ ++ if(piorw_urb) ++ ExFreePool(piorw_urb); ++ ++ RT_TRACE(_module_hci_ops_os_c_,_drv_info_,("\n -usb_init_intf_priv(usb_init_intf_priv_fail)\n")); ++ ++_func_exit_; ++ return _FAIL; ++ ++} ++ ++void usb_unload_intf_priv(struct intf_priv *pintfpriv) ++{ ++ ++_func_enter_; ++ ++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("\n+usb_unload_intf_priv\n")); ++ ++ rtw_mfree((u8 *)(pintfpriv->allocated_io_rwmem), pintfpriv->max_iosz+4); ++ ++#ifdef PLATFORM_WINDOWS ++ if(pintfpriv->piorw_urb) ++ ExFreePool(pintfpriv->piorw_urb); ++ ++ if(pintfpriv->piorw_irp) ++ IoFreeIrp(pintfpriv->piorw_irp); ++#endif ++ ++ ++#ifdef PLATFORM_LINUX ++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("\npintfpriv->io_irp_cnt=%d\n",pintfpriv->io_irp_cnt)); ++ pintfpriv->io_irp_cnt--; ++ if(pintfpriv->io_irp_cnt){ ++ if(pintfpriv->bio_irp_pending==_TRUE){ ++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("\nkill iorw_urb\n")); ++ usb_kill_urb(pintfpriv->piorw_urb); ++ } ++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("\n wait io_retevt\n")); ++ _rtw_down_sema(&(pintfpriv->io_retevt)); ++ } ++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("\n cancel io_urb ok\n")); ++#endif ++ ++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("\n-usb_unload_intf_priv\n")); ++ ++_func_exit_; ++ ++} ++ ++void *ffaddr2pipehdl(struct dvobj_priv *pNdisCEDvice, u32 addr) ++{ ++ HANDLE PipeHandle = NULL; ++ _adapter *padapter = pNdisCEDvice->padapter; ++ ++ ++ if(pNdisCEDvice->nr_endpoint == 11) ++ { ++ switch(addr) ++ { ++ case RTL8712_DMA_BEQ: ++ PipeHandle= padapter->halpriv.pipehdls_r8712[3] ; ++ break; ++ case RTL8712_DMA_BKQ: ++ PipeHandle= padapter->halpriv.pipehdls_r8712[4]; ++ break; ++ case RTL8712_DMA_VIQ: ++ PipeHandle= padapter->halpriv.pipehdls_r8712[2]; ++ break; ++ case RTL8712_DMA_VOQ: ++ PipeHandle= padapter->halpriv.pipehdls_r8712[1]; ++ break; ++ case RTL8712_DMA_BCNQ: ++ PipeHandle= padapter->halpriv.pipehdls_r8712[6]; ++ break; ++ case RTL8712_DMA_BMCQ: //HI Queue ++ PipeHandle= padapter->halpriv.pipehdls_r8712[7]; ++ break; ++ case RTL8712_DMA_MGTQ: ++ PipeHandle= padapter->halpriv.pipehdls_r8712[8]; ++ break; ++ case RTL8712_DMA_RX0FF: ++ PipeHandle= padapter->halpriv.pipehdls_r8712[0]; ++ break; ++ case RTL8712_DMA_C2HCMD: ++ PipeHandle= padapter->halpriv.pipehdls_r8712[5]; ++ break; ++ case RTL8712_DMA_H2CCMD: ++ PipeHandle= padapter->halpriv.pipehdls_r8712[9]; ++ break; ++ ++ } ++ ++ } ++ else if(pNdisCEDvice->nr_endpoint == 6) ++ { ++ switch(addr) ++ { ++ case RTL8712_DMA_BEQ: ++ PipeHandle= padapter->halpriv.pipehdls_r8712[3]; ++ break; ++ case RTL8712_DMA_BKQ: ++ PipeHandle= padapter->halpriv.pipehdls_r8712[4]; ++ break; ++ case RTL8712_DMA_VIQ: ++ PipeHandle= padapter->halpriv.pipehdls_r8712[2]; ++ break; ++ case RTL8712_DMA_VOQ: ++ PipeHandle= padapter->halpriv.pipehdls_r8712[1]; ++ break; ++ case RTL8712_DMA_RX0FF: ++ case RTL8712_DMA_C2HCMD: ++ PipeHandle= padapter->halpriv.pipehdls_r8712[0]; ++ break; ++ case RTL8712_DMA_H2CCMD: ++ case RTL8712_DMA_BCNQ: ++ case RTL8712_DMA_BMCQ: ++ case RTL8712_DMA_MGTQ: ++ PipeHandle= padapter->halpriv.pipehdls_r8712[5]; ++ break; ++ ++ } ++ ++ } ++ else if(pNdisCEDvice->nr_endpoint == 4) ++ { ++ switch(addr) ++ { ++ case RTL8712_DMA_BEQ: ++ //case RTL8712_DMA_BKQ: ++ PipeHandle= padapter->halpriv.pipehdls_r8712[2]; ++ break; ++ //case RTL8712_DMA_VIQ: ++ case RTL8712_DMA_VOQ: ++ PipeHandle= padapter->halpriv.pipehdls_r8712[1]; ++ break; ++ case RTL8712_DMA_RX0FF: ++ case RTL8712_DMA_C2HCMD: ++ PipeHandle= padapter->halpriv.pipehdls_r8712[0]; ++ break; ++ case RTL8712_DMA_H2CCMD: ++ case RTL8712_DMA_BCNQ: ++ case RTL8712_DMA_BMCQ: ++ case RTL8712_DMA_MGTQ: ++ PipeHandle= padapter->halpriv.pipehdls_r8712[3]; ++ break; ++ } ++ ++ } ++ else ++ { ++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("ffaddr2pipehdl():nr_endpoint=%d error!\n", pNdisCEDvice->nr_endpoint)); ++ } ++ ++ return PipeHandle; ++ ++} ++ ++ ++NTSTATUS usb_bulkout_zero_complete( ++ PDEVICE_OBJECT pUsbDevObj, ++ PIRP pIrp, void* pZeroContext) ++{ ++ struct zero_bulkout_context *pcontext = (struct zero_bulkout_context *)pZeroContext; ++ ++_func_enter_; ++ ++ if(pcontext) ++ { ++ if(pcontext->pbuf) ++ { ++ ExFreePool(pcontext->pbuf); ++ } ++ ++ if(pcontext->purb) ++ { ++ ExFreePool(pcontext->purb); ++ } ++ ++ if(pcontext->pirp && (pIrp ==pcontext->pirp)) ++ { ++ IoFreeIrp(pIrp); ++ } ++ ++ ExFreePool(pcontext); ++ } ++ ++_func_exit_; ++ ++ return STATUS_MORE_PROCESSING_REQUIRED; ++ ++ ++} ++ ++u32 usb_bulkout_zero(struct intf_hdl *pintfhdl, u32 addr) ++{ ++ struct zero_bulkout_context *pcontext; ++ unsigned char *pbuf; ++ char NextDeviceStackSize, len; ++ PIO_STACK_LOCATION nextStack; ++ USBD_STATUS usbdstatus; ++ HANDLE PipeHandle; ++ PIRP pirp = NULL; ++ PURB purb = NULL; ++ NDIS_STATUS ndisStatus = NDIS_STATUS_SUCCESS; ++ _adapter *padapter = (_adapter *)pintfhdl->adapter; ++ struct dvobj_priv *pdvobj = (struct dvobj_priv *)&padapter->dvobjpriv; ++ ++ ++_func_enter_; ++ ++ if((padapter->bDriverStopped) || (padapter->bSurpriseRemoved) ||(padapter->pwrctrlpriv.pnp_bstop_trx)) ++ { ++ return _FAIL; ++ } ++ ++ len = 0; ++ NextDeviceStackSize = (char)pdvobj->nextdevstacksz; ++ ++ pcontext = (struct zero_bulkout_context *)ExAllocatePool(NonPagedPool, sizeof(struct zero_bulkout_context)); ++ pbuf = (unsigned char *)ExAllocatePool(NonPagedPool, sizeof(int)); ++ purb = (PURB)ExAllocatePool(NonPagedPool, sizeof(URB)); ++ pirp = IoAllocateIrp(NextDeviceStackSize, FALSE); ++ ++ pcontext->pbuf = pbuf; ++ pcontext->purb = purb; ++ pcontext->pirp = pirp; ++ pcontext->padapter = padapter; ++ ++ //translate DMA FIFO addr to pipehandle ++ PipeHandle = ffaddr2pipehdl(pdvobj, addr); ++ ++ ++ // Build our URB for USBD ++ UsbBuildInterruptOrBulkTransferRequest( ++ purb, ++ sizeof(struct _URB_BULK_OR_INTERRUPT_TRANSFER), ++ PipeHandle, ++ pbuf, ++ NULL, ++ len, ++ 0, ++ NULL); ++ ++ // ++ // call the calss driver to perform the operation ++ // pass the URB to the USB driver stack ++ // ++ nextStack = IoGetNextIrpStackLocation(pirp); ++ nextStack->MajorFunction = IRP_MJ_INTERNAL_DEVICE_CONTROL; ++ nextStack->Parameters.Others.Argument1 = purb; ++ nextStack->Parameters.DeviceIoControl.IoControlCode = IOCTL_INTERNAL_USB_SUBMIT_URB; ++ ++ //Set Completion Routine ++ IoSetCompletionRoutine(pirp, // irp to use ++ usb_bulkout_zero_complete, // callback routine ++ pcontext, // context ++ TRUE, // call on success ++ TRUE, // call on error ++ TRUE); // call on cancel ++ ++ ++ // Call IoCallDriver to send the irp to the usb bus driver ++ // ++ ndisStatus = IoCallDriver(pdvobj->pnextdevobj, pirp); ++ usbdstatus = URB_STATUS(purb); ++ ++ if( USBD_HALTED(usbdstatus) ) ++ { ++ padapter->bDriverStopped=_TRUE; ++ padapter->bSurpriseRemoved=_TRUE; ++ } ++ ++ // ++ // The usb bus driver should always return STATUS_PENDING when bulk out irp async ++ // ++ if ( ndisStatus != STATUS_PENDING ) ++ { ++ return _FAIL; ++ } ++ ++_func_exit_; ++ ++ return _SUCCESS; ++ ++} ++ ++void usb_read_mem(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *rmem) ++{ ++ _func_enter_; ++ ++ ++ ++ _func_exit_; ++} ++ ++NTSTATUS usb_write_mem_complete(PDEVICE_OBJECT pUsbDevObj, PIRP piowrite_irp, PVOID pusb_cnxt) ++{ ++ ++ _irqL irqL; ++ _list *head, *plist; ++ struct io_req *pio_req; ++ struct io_queue *pio_q = (struct io_queue *) pusb_cnxt; ++ struct intf_hdl *pintf = &(pio_q->intf); ++ struct intf_priv *pintfpriv = pintf->pintfpriv; ++ _adapter *padapter = (_adapter *)pintf->adapter; ++ NTSTATUS status = STATUS_SUCCESS; ++ ++ head = &(pio_q->processing); ++ ++ _func_enter_; ++ ++ _enter_critical_bh(&(pio_q->lock), &irqL); ++ ++ pintfpriv->io_irp_cnt--; ++ if(pintfpriv->io_irp_cnt ==0){ ++ _rtw_up_sema(&(pintfpriv->io_retevt)); ++ } ++ ++ pintfpriv->bio_irp_pending=_FALSE; ++ ++ switch(piowrite_irp->IoStatus.Status) ++ { ++ case STATUS_SUCCESS: ++ break; ++ ++ default: ++ padapter->bSurpriseRemoved=_TRUE; ++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("\n usbAsynIntOutComplete:pioread_irp->IoStatus.Status !=STATUS_SUCCESS\n")); ++ break; ++ } ++ ++ //free irp in processing list... ++ while(rtw_is_list_empty(head) != _TRUE) ++ { ++ plist = get_next(head); ++ rtw_list_delete(plist); ++ pio_req = LIST_CONTAINOR(plist, struct io_req, list); ++ _rtw_up_sema(&pio_req->sema); ++ } ++ ++ _exit_critical_bh(&(pio_q->lock), &irqL); ++ ++ _func_exit_; ++ ++ return STATUS_MORE_PROCESSING_REQUIRED; ++ ++} ++ ++void usb_write_mem(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *wmem) ++{ ++ u32 bwritezero; ++ _irqL irqL; ++ USBD_STATUS usbdstatus; ++ PIO_STACK_LOCATION nextStack; ++ HANDLE PipeHandle; ++ struct io_req *pio_req; ++ ++ _adapter *adapter = (_adapter *)pintfhdl->adapter; ++ struct intf_priv *pintfpriv = pintfhdl->pintfpriv; ++ struct dvobj_priv *pdev = (struct dvobj_priv *)pintfpriv->intf_dev; ++ PURB piorw_urb = pintfpriv->piorw_urb; ++ PIRP piorw_irp = pintfpriv->piorw_irp; ++ struct io_queue *pio_queue = (struct io_queue *)adapter->pio_queue; ++ NTSTATUS NtStatus = STATUS_SUCCESS; ++ ++ _func_enter_; ++ ++ pio_req = alloc_ioreq(pio_queue); ++ ++ if ((pio_req == NULL)||(adapter->bSurpriseRemoved)){ ++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("async_irp_write32 : pio_req =0x%x adapter->bSurpriseRemoved=0x%x",pio_req,adapter->bSurpriseRemoved )); ++ goto exit; ++ } ++ ++ _enter_critical_bh(&(pio_queue->lock), &irqL); ++ ++ rtw_list_insert_tail(&(pio_req->list),&(pio_queue->processing)); ++ ++ ++#ifdef NDIS51_MINIPORT ++ IoReuseIrp(piorw_irp, STATUS_SUCCESS); ++#else ++ piorw_irp->Cancel = _FALSE; ++#endif ++ ++ if((adapter->bDriverStopped) || (adapter->bSurpriseRemoved) ||(adapter->pwrctrlpriv.pnp_bstop_trx)) ++ { ++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("\npadapter->pwrctrlpriv.pnp_bstop_trx==_TRUE\n")); ++ _func_exit_; ++ return; ++ } ++ ++ //translate DMA FIFO addr to pipehandle ++ PipeHandle = ffaddr2pipehdl(pdev, addr); ++ ++ ++ pintfpriv->io_irp_cnt++; ++ pintfpriv->bio_irp_pending=_TRUE; ++ // Build our URB for USBD ++ UsbBuildInterruptOrBulkTransferRequest( ++ piorw_urb, ++ sizeof(struct _URB_BULK_OR_INTERRUPT_TRANSFER), ++ PipeHandle, ++ (PVOID)wmem, ++ NULL, ++ cnt, ++ 0, ++ NULL); ++ ++ // ++ // call the calss driver to perform the operation ++ // pass the URB to the USB driver stack ++ // ++ nextStack = IoGetNextIrpStackLocation(piorw_irp); ++ nextStack->MajorFunction = IRP_MJ_INTERNAL_DEVICE_CONTROL; ++ nextStack->Parameters.Others.Argument1 = (PURB)piorw_urb; ++ nextStack->Parameters.DeviceIoControl.IoControlCode = IOCTL_INTERNAL_USB_SUBMIT_URB; ++ ++ IoSetCompletionRoutine( ++ piorw_irp, // irp to use ++ usb_write_mem_complete, // routine to call when irp is done ++ pio_queue, // context to pass routine ++ TRUE, // call on success ++ TRUE, // call on error ++ TRUE); // call on cancel ++ ++ // ++ // Call IoCallDriver to send the irp to the usb port ++ // ++ NtStatus = IoCallDriver(pdev->pnextdevobj, piorw_irp); ++ usbdstatus = URB_STATUS(piorw_urb); ++ ++ // ++ // The USB driver should always return STATUS_PENDING when ++ // it receives a write irp ++ // ++ if ((NtStatus != STATUS_PENDING) || USBD_HALTED(usbdstatus) ) { ++ ++ if( USBD_HALTED(usbdstatus) ) { ++ ++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_write_mem():USBD_HALTED(usbdstatus)=%X!\n",USBD_HALTED(usbdstatus)) ); ++ } ++ _func_exit_; ++ return;//STATUS_UNSUCCESSFUL; ++ } ++ ++ _exit_critical_bh(&(pio_queue->lock), &irqL); ++ ++ _rtw_down_sema(&pio_req->sema); ++ free_ioreq(pio_req, pio_queue); ++ ++ ++ bwritezero = _FALSE; ++ if (pdev->ishighspeed) ++ { ++ if(cnt> 0 && cnt%512 == 0) ++ bwritezero = _TRUE; ++ ++ } ++ else ++ { ++ if(cnt > 0 && cnt%64 == 0) ++ bwritezero = _TRUE; ++ } ++ ++ ++ if(bwritezero == _TRUE) ++ { ++ usb_bulkout_zero(pintfhdl, addr); ++ } ++ ++exit: ++ ++ _func_exit_; ++ ++} ++ ++NTSTATUS usb_read_port_complete(PDEVICE_OBJECT pUsbDevObj, PIRP pIrp, PVOID context) ++{ ++ uint isevt, *pbuf; ++ struct _URB_BULK_OR_INTERRUPT_TRANSFER *pbulkurb; ++ USBD_STATUS usbdstatus; ++ struct recv_buf *precvbuf = (struct recv_buf *)context; ++ _adapter *adapter =(_adapter *)precvbuf->adapter; ++ struct recv_priv *precvpriv = &adapter->recvpriv; ++ struct dvobj_priv *dev = (struct dvobj_priv *)&adapter->dvobjpriv; ++ PURB purb = precvbuf->purb; ++ struct intf_hdl *pintfhdl = &adapter->pio_queue->intf; ++ ++ //RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port_complete!!!\n")); ++ ++ usbdstatus = URB_STATUS(purb); ++ ++ _rtw_spinlock_ex(&precvpriv->lock); ++ precvbuf->irp_pending=_FALSE; ++ precvpriv->rx_pending_cnt --; ++ _rtw_spinunlock_ex(&precvpriv->lock); ++ ++ if(precvpriv->rx_pending_cnt== 0) { ++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port_complete: rx_pending_cnt== 0, set allrxreturnevt!\n")); ++ _rtw_up_sema(&precvpriv->allrxreturnevt); ++ } ++ ++ ++ if( pIrp->Cancel == _TRUE ) { ++ ++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port_complete: One IRP has been cancelled succesfully\n")); ++ return STATUS_MORE_PROCESSING_REQUIRED; ++ } ++ if(adapter->bSurpriseRemoved) { ++ ++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port_complete:bDriverStopped(%d) OR bSurpriseRemoved(%d)", adapter->bDriverStopped, adapter->bSurpriseRemoved)); ++ return STATUS_MORE_PROCESSING_REQUIRED; ++ } ++ ++ switch(pIrp->IoStatus.Status) ++ { ++ case STATUS_SUCCESS: ++ ++ pbulkurb = &(precvbuf->purb)->UrbBulkOrInterruptTransfer; ++ if((pbulkurb->TransferBufferLength >(MAX_RECVBUF_SZ)) || (pbulkurb->TransferBufferLength < RXDESC_SIZE) ) ++ { ++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("\n usb_read_port_complete: (pbulkurb->TransferBufferLength > MAX_RECVBUF_SZ) || (pbulkurb->TransferBufferLength < RXDESC_SIZE)\n")); ++ rtw_read_port(adapter, precvpriv->ff_hwaddr, 0, (unsigned char *)precvbuf); ++ } ++ else ++ { ++ precvbuf->transfer_len = pbulkurb->TransferBufferLength; ++ ++ pbuf = (uint*)precvbuf->pbuf; ++ ++ if((isevt = *(pbuf+1)&0x1ff) == 0x1ff) ++ { ++ rxcmd_event_hdl(adapter, pbuf);//rx c2h events ++ ++ rtw_read_port(adapter, precvpriv->ff_hwaddr, 0, (unsigned char *)precvbuf); ++ } ++ else ++ { ++ if(recvbuf2recvframe(adapter, precvbuf)==_FAIL)//rx packets ++ { ++ //precvbuf->reuse = _TRUE; ++ rtw_read_port(adapter, precvpriv->ff_hwaddr, 0, (unsigned char *)precvbuf); ++ } ++ } ++ ++ } ++ ++ break; ++ ++ default: ++ ++ if( !USBD_HALTED(usbdstatus) ) ++ { ++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("\n usb_read_port_complete():USBD_HALTED(usbdstatus)=%x (need to handle ) \n",USBD_HALTED(usbdstatus))); ++ ++ } ++ else ++ { ++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("\n usb_read_port_complete(): USBD_HALTED(usbdstatus)=%x \n\n", USBD_HALTED(usbdstatus)) ); ++ adapter->bDriverStopped = _TRUE; ++ adapter->bSurpriseRemoved = _TRUE; ++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port_complete(): USBD_HALTED(usbdstatus)=%x \n\n", USBD_HALTED(usbdstatus))) ; ++ } ++ ++ break; ++ ++ } ++ ++ return STATUS_MORE_PROCESSING_REQUIRED; ++ ++} ++ ++u32 usb_read_port(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *rmem) ++{ ++ u8 *pdata; ++ u16 size; ++ PURB purb; ++ PIRP pirp; ++ PIO_STACK_LOCATION nextStack; ++ NTSTATUS ntstatus; ++ USBD_STATUS usbdstatus; ++ HANDLE PipeHandle; ++ struct recv_buf *precvbuf = (struct recv_buf *)rmem; ++ struct intf_priv *pintfpriv = pintfhdl->pintfpriv; ++ struct dvobj_priv *pdev = (struct dvobj_priv *)pintfpriv->intf_dev; ++ _adapter *adapter = (_adapter *)pdev->padapter; ++ struct recv_priv *precvpriv = &adapter->recvpriv; ++ u32 bResult = _FALSE; ++ ++_func_enter_; ++ ++ if(adapter->bDriverStopped || adapter->bSurpriseRemoved ||adapter->pwrctrlpriv.pnp_bstop_trx) { ++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port:( padapter->bDriverStopped ||padapter->bSurpriseRemoved ||adapter->pwrctrlpriv.pnp_bstop_trx)!!!\n")); ++ return bResult; ++ } ++ ++ if(precvbuf !=NULL) ++ { ++ ++ rtl8192cu_init_recvbuf(adapter, precvbuf); ++ ++ _rtw_spinlock(&precvpriv->lock); ++ precvpriv->rx_pending_cnt++; ++ precvbuf->irp_pending = _TRUE; ++ _rtw_spinunlock(&precvpriv->lock); ++ ++ pdata = (u8*)precvbuf->pbuf; ++ ++ size = sizeof( struct _URB_BULK_OR_INTERRUPT_TRANSFER ); ++ purb = precvbuf->purb; ++ ++ //translate DMA FIFO addr to pipehandle ++ PipeHandle = ffaddr2pipehdl(pdev, addr); ++ ++ UsbBuildInterruptOrBulkTransferRequest( ++ purb, ++ (USHORT)size, ++ PipeHandle, ++ pdata, ++ NULL, ++ MAX_RECVBUF_SZ, ++ USBD_TRANSFER_DIRECTION_IN | USBD_SHORT_TRANSFER_OK, ++ NULL ++ ); ++ ++ pirp = precvbuf->pirp; ++ ++#if NDIS51_MINIPORT ++ IoReuseIrp(pirp, STATUS_SUCCESS); ++#else ++ pirp->Cancel = _FALSE; ++#endif ++ ++ // call the class driver to perform the operation ++ // and pass the URB to the USB driver stack ++ nextStack = IoGetNextIrpStackLocation(pirp); ++ nextStack->Parameters.Others.Argument1 = purb; ++ nextStack->Parameters.DeviceIoControl.IoControlCode = IOCTL_INTERNAL_USB_SUBMIT_URB; ++ nextStack->MajorFunction = IRP_MJ_INTERNAL_DEVICE_CONTROL; ++ ++ IoSetCompletionRoutine( ++ pirp, // irp to use ++ usb_read_port_complete, // routine to call when irp is done ++ precvbuf, // context to pass routine ++ TRUE, // call on success ++ TRUE, // call on error ++ TRUE); // call on cancel ++ ++ // ++ // The IoCallDriver routine ++ // sends an IRP to the driver associated with a specified device object. ++ // ++ ntstatus = IoCallDriver(pdev->pnextdevobj, pirp); ++ usbdstatus = URB_STATUS(purb); ++ ++ if( USBD_HALTED(usbdstatus) ) { ++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("\n usb_read_port(): USBD_HALTED(usbdstatus=0x%.8x)=%.8x \n\n", usbdstatus, USBD_HALTED(usbdstatus))); ++ pdev->padapter->bDriverStopped=_TRUE; ++ pdev->padapter->bSurpriseRemoved=_TRUE; ++ } ++ ++ if( ntstatus == STATUS_PENDING ) ++ { ++ bResult = _TRUE;// The IRP is pended in USBD as we expected. ++ } ++ else { ++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port(): IoCallDriver failed!!! IRP STATUS: %X\n", ntstatus)); ++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port(): IoCallDriver failed!!! USB STATUS: %X\n", usbdstatus)); ++ } ++ ++ } ++ else{ ++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port:precv_frame ==NULL\n")); ++ } ++ ++_func_exit_; ++ ++ return bResult; ++ ++} ++ ++void usb_read_port_cancel(_adapter *padapter) ++{ ++ struct recv_buf *precvbuf; ++ sint i; ++ struct dvobj_priv *pdev = &padapter->dvobjpriv; ++ struct recv_priv *precvpriv=&padapter->recvpriv; ++ ++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("\n ==>usb_read_port_cancel\n")); ++ ++ _rtw_spinlock(&precvpriv->lock); ++ precvpriv->rx_pending_cnt--; //decrease 1 for Initialize ++ ++ _rtw_spinunlock(&precvpriv->lock); ++ ++ if (precvpriv->rx_pending_cnt) ++ { ++ // Canceling Pending Recv Irp ++ precvbuf = (struct recv_buf *)precvpriv->precv_buf; ++ ++ for( i = 0; i < NR_RECVBUFF; i++ ) ++ { ++ if (precvbuf->irp_pending == _TRUE) ++ { ++ IoCancelIrp(precvbuf->pirp); ++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port_cancel() :IoCancelIrp\n")); ++ } ++ ++ precvbuf++; ++ } ++ ++ _rtw_down_sema(&precvpriv->allrxreturnevt); ++ ++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_read_port_cancel:down sema\n")); ++ ++ } ++ ++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("<==usb_read_port_cancel\n")); ++ ++} ++ ++NTSTATUS usb_write_port_complete( ++ PDEVICE_OBJECT pUsbDevObj, ++ PIRP pIrp, ++ PVOID pTxContext ++) ++{ ++ u32 i, bIrpSuccess, sz; ++ NTSTATUS status = STATUS_SUCCESS; ++ u8 *ptr; ++ struct xmit_frame *pxmitframe = (struct xmit_frame *) pTxContext; ++ struct xmit_buf *pxmitbuf = pxmitframe->pxmitbuf; ++ _adapter *padapter = pxmitframe->padapter; ++ struct dvobj_priv *pdev = (struct dvobj_priv *)&padapter->dvobjpriv; ++ struct io_queue *pio_queue = (struct io_queue *)padapter->pio_queue; ++ struct intf_hdl *pintfhdl = &(pio_queue->intf); ++ struct xmit_priv *pxmitpriv = &padapter->xmitpriv; ++ ++_func_enter_; ++ ++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("+usb_write_port_complete\n")); ++ ++ _rtw_spinlock_ex(&pxmitpriv->lock); ++ pxmitpriv->txirp_cnt--; ++ _rtw_spinunlock_ex(&pxmitpriv->lock); ++ ++ if(pxmitpriv->txirp_cnt==0){ ++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_write_port_complete: txirp_cnt== 0, set allrxreturnevt!\n")); ++ _rtw_up_sema(&(pxmitpriv->tx_retevt)); ++ } ++ ++ status = pIrp->IoStatus.Status; ++ ++ if( status == STATUS_SUCCESS ) ++ bIrpSuccess = _TRUE; ++ else ++ bIrpSuccess = _FALSE; ++ ++ if( pIrp->Cancel == _TRUE ) ++ { ++ if(pxmitframe !=NULL) ++ { ++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("\n usb_write_port_complete:pIrp->Cancel == _TRUE,(pxmitframe !=NULL\n")); ++ rtw_free_xmitframe_ex(pxmitpriv, pxmitframe); ++ } ++ ++ return STATUS_MORE_PROCESSING_REQUIRED; ++ } ++ ++ if(padapter->bSurpriseRemoved) ++ { ++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_write_port_complete:bDriverStopped(%d) OR bSurpriseRemoved(%d)", padapter->bDriverStopped, padapter->bSurpriseRemoved)); ++ return STATUS_MORE_PROCESSING_REQUIRED; ++ } ++ ++ ++ // ++ // Send 0-byte here if necessary. ++ // ++ // ++ // 1. We MUST keep at most one IRP pending in each endpoint, otherwise USB host controler driver will hang. ++ // Besides, even 0-byte IRP shall be count into #IRP sent down, so, we send 0-byte here instead of TxFillDescriptor8187(). ++ // 2. If we don't count 0-byte IRP into an #IRP sent down, Tx will stuck when we download files via BT and ++ // play online video on XP SP1 EHCU. ++ // 2005.12.26, by rcnjko. ++ // ++ ++ ++ for(i=0; i< 8; i++) ++ { ++ if(pIrp == pxmitframe->pxmit_irp[i]) ++ { ++ pxmitframe->bpending[i] = _FALSE;// ++ //ac_tag = pxmitframe->ac_tag[i]; ++ sz = pxmitframe->sz[i]; ++ break; ++ } ++ } ++ ++#if 0 ++ pxmitframe->fragcnt--; ++ if(pxmitframe->fragcnt == 0)// if((pxmitframe->fragcnt == 0) && (pxmitframe->irpcnt == 8)){ ++ { ++ //RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("\n usb_write_port_complete:pxmitframe->fragcnt == 0\n")); ++ rtw_free_xmitframe(pxmitpriv,pxmitframe); ++ } ++#else ++ ++ //not to consider tx fragment ++ rtw_free_xmitframe_ex(pxmitpriv, pxmitframe); ++ ++#endif ++ ++ rtl8192cu_xmitframe_complete(padapter, pxmitpriv, pxmitbuf); ++ ++_func_exit_; ++ ++ return STATUS_MORE_PROCESSING_REQUIRED; ++ ++} ++ ++u32 usb_write_port(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *wmem) ++{ ++ u32 i, bwritezero; ++ u8 *ptr; ++ PIO_STACK_LOCATION nextStack; ++ USBD_STATUS usbdstatus; ++ HANDLE PipeHandle; ++ PIRP pirp = NULL; ++ PURB purb = NULL; ++ NDIS_STATUS ndisStatus = NDIS_STATUS_SUCCESS; ++ _adapter *padapter = (_adapter *)pintfhdl->adapter; ++ struct dvobj_priv *pNdisCEDvice = (struct dvobj_priv *)&padapter->dvobjpriv; ++ struct xmit_priv *pxmitpriv = &padapter->xmitpriv; ++ struct xmit_frame *pxmitframe = (struct xmit_frame *)wmem; ++ ++_func_enter_; ++ ++ if((padapter->bDriverStopped) || (padapter->bSurpriseRemoved) ||(padapter->pwrctrlpriv.pnp_bstop_trx)) ++ { ++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usb_write_port:( padapter->bDriverStopped ||padapter->bSurpriseRemoved ||adapter->pwrctrlpriv.pnp_bstop_trx)!!!\n")); ++ return _FAIL; ++ } ++ ++ ++ for(i=0; i<8; i++) ++ { ++ if(pxmitframe->bpending[i] == _FALSE) ++ { ++ _rtw_spinlock(&pxmitpriv->lock); ++ pxmitpriv->txirp_cnt++; ++ pxmitframe->bpending[i] = _TRUE; ++ _rtw_spinunlock(&pxmitpriv->lock); ++ ++ pxmitframe->sz[i] = cnt; ++ purb = pxmitframe->pxmit_urb[i]; ++ pirp = pxmitframe->pxmit_irp[i]; ++ ++ //pxmitframe->ac_tag[i] = ac_tag; ++ ++ break; ++ } ++ } ++ ++ bwritezero = _FALSE; ++ if (pNdisCEDvice->ishighspeed) ++ { ++ if(cnt> 0 && cnt%512 == 0) ++ { ++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("ishighspeed, cnt=%d\n", cnt)); ++ //cnt=cnt+1; ++ bwritezero = _TRUE; ++ } ++ } ++ else ++ { ++ if(cnt > 0 && cnt%64 == 0) ++ { ++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("cnt=%d\n", cnt)); ++ //cnt=cnt+1; ++ bwritezero = _TRUE; ++ } ++ } ++ ++ ++#ifdef NDIS51_MINIPORT ++ IoReuseIrp(pirp, STATUS_SUCCESS); ++#else ++ pirp->Cancel = _FALSE; ++#endif ++ ++ ++ //translate DMA FIFO addr to pipehandle ++ PipeHandle = ffaddr2pipehdl(pNdisCEDvice, addr); ++ ++ ++ // Build our URB for USBD ++ UsbBuildInterruptOrBulkTransferRequest( ++ purb, ++ sizeof(struct _URB_BULK_OR_INTERRUPT_TRANSFER), ++ PipeHandle, ++ pxmitframe->mem_addr, ++ NULL, ++ cnt, ++ 0, ++ NULL); ++ ++ // ++ // call the calss driver to perform the operation ++ // pass the URB to the USB driver stack ++ // ++ nextStack = IoGetNextIrpStackLocation(pirp); ++ nextStack->MajorFunction = IRP_MJ_INTERNAL_DEVICE_CONTROL; ++ nextStack->Parameters.Others.Argument1 = purb; ++ nextStack->Parameters.DeviceIoControl.IoControlCode = IOCTL_INTERNAL_USB_SUBMIT_URB; ++ ++ //Set Completion Routine ++ IoSetCompletionRoutine(pirp, // irp to use ++ usb_write_port_complete, // callback routine ++ pxmitframe, // context ++ TRUE, // call on success ++ TRUE, // call on error ++ TRUE); // call on cancel ++ ++ ++ // Call IoCallDriver to send the irp to the usb bus driver ++ // ++ ndisStatus = IoCallDriver(pNdisCEDvice->pnextdevobj, pirp); ++ usbdstatus = URB_STATUS(purb); ++ ++ if( USBD_HALTED(usbdstatus) ) ++ { ++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("\n usb_write_port(): USBD_HALTED(usbdstatus)=%x set bDriverStopped TRUE!\n\n",USBD_HALTED(usbdstatus)) ); ++ padapter->bDriverStopped=_TRUE; ++ padapter->bSurpriseRemoved=_TRUE; ++ } ++ ++ // ++ // The usb bus driver should always return STATUS_PENDING when bulk out irp async ++ // ++ if ( ndisStatus != STATUS_PENDING ) ++ { ++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("\n usb_write_port(): ndisStatus(%x) != STATUS_PENDING!\n\n", ndisStatus)); ++ ++ _func_exit_; ++ ++ return _FAIL; ++ } ++ ++ if(bwritezero == _TRUE) ++ { ++ usb_bulkout_zero(pintfhdl, addr); ++ } ++ ++ ++_func_exit_; ++ ++ return _SUCCESS; ++ ++} ++ ++ ++void usb_write_port_cancel(_adapter *padapter) ++{ ++ ++ sint i,j; ++ struct dvobj_priv *pdev = &padapter->dvobjpriv; ++ struct xmit_priv *pxmitpriv=&padapter->xmitpriv; ++ struct xmit_frame *pxmitframe; ++ ++ _rtw_spinlock(&pxmitpriv->lock); ++ pxmitpriv->txirp_cnt--; //decrease 1 for Initialize ++ ++ _rtw_spinunlock(&pxmitpriv->lock); ++ ++ if (pxmitpriv->txirp_cnt) ++ { ++ // Canceling Pending Recv Irp ++ pxmitframe= (struct xmit_frame *)pxmitpriv->pxmit_frame_buf; ++ ++ for( i = 0; i < NR_XMITFRAME; i++ ) ++ { ++ for(j=0;j<8;j++) ++ { ++ if (pxmitframe->bpending[j]==_TRUE) ++ { ++ IoCancelIrp(pxmitframe->pxmit_irp[j]); ++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,(" usb_write_port_cancel() :IoCancelIrp\n")); ++ ++ } ++ } ++ ++ pxmitframe++; ++ } ++ ++ _rtw_down_sema(&(pxmitpriv->tx_retevt)); ++ ++ } ++ ++} ++ ++ ++/*! \brief Wrap the pUrb to an IRP and send this IRP to Bus Driver. Then wait for this IRP completion. ++ The Caller shall be at Passive Level. ++*/ ++NTSTATUS sync_callusbd(struct dvobj_priv *pdvobjpriv, PURB purb) ++{ ++ ++ KEVENT kevent; ++ PIRP irp; ++ IO_STATUS_BLOCK iostatusblock; ++ PIO_STACK_LOCATION nextstack; ++ USBD_STATUS usbdstatus; ++ LARGE_INTEGER waittime; ++ NTSTATUS ntstatus = STATUS_SUCCESS; ++ _adapter *padapter = pdvobjpriv->padapter; ++ ++ ++ _func_enter_; ++ ++// if(padapter->bDriverStopped) { ++// goto exit; ++// } ++ ++ KeInitializeEvent(&kevent, NotificationEvent, _FALSE); ++ irp = IoBuildDeviceIoControlRequest( ++ IOCTL_INTERNAL_USB_SUBMIT_URB, ++ pdvobjpriv->pphysdevobj,//CEdevice->pUsbDevObj, ++ NULL, ++ 0, ++ NULL, ++ 0, ++ _TRUE, ++ &kevent, ++ &iostatusblock); ++ ++ if(irp == NULL) { ++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("SyncCallUSBD: memory alloc for irp failed\n")); ++ ntstatus=STATUS_INSUFFICIENT_RESOURCES; ++ goto exit; ++ } ++ ++ nextstack = IoGetNextIrpStackLocation(irp); ++ if(nextstack == NULL) ++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("IoGetNextIrpStackLocation fail\n")); ++ ++ nextstack->Parameters.Others.Argument1 = purb; ++ ++ // Issue an IRP for Sync IO. ++ ntstatus = IoCallDriver(pdvobjpriv->pphysdevobj, irp); ++ usbdstatus = URB_STATUS(purb); ++ ++ if(ntstatus == STATUS_PENDING) ++ { ++ // Method 1 ++ waittime.QuadPart = -10000 * 50000; ++ ntstatus = KeWaitForSingleObject(&kevent, Executive, KernelMode, _FALSE, &waittime); //8150 code ++ ++ // Method 2 ++ //ntStatus = KeWaitForSingleObject(&Kevent, Executive, KernelMode, FALSE, NULL); //DDK sample ++ ++ usbdstatus = URB_STATUS(purb); ++ ++ if(ntstatus == STATUS_TIMEOUT) ++ { ++ //usbdevice->nIoStuckCnt++; ++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("SyncCallUSBD: TIMEOUT....5000ms\n")); ++ ++ // Method 2 ++ IoCancelIrp(irp); ++ ntstatus = KeWaitForSingleObject(&kevent, Executive, KernelMode, _FALSE, NULL); //DDK sample ++ usbdstatus = URB_STATUS(purb); ++ ++ usbdstatus = USBD_STATUS_SUCCESS; ++ } ++ ++ } ++ ++exit: ++ ++ _func_exit_; ++ ++ return ntstatus; ++ ++} ++int usbctrl_vendorreq(struct intf_priv *pintfpriv, u8 request, u16 value, u16 index, void *pdata, u16 len, u8 requesttype) ++{ ++ PURB purb; ++ u8 ret; ++ unsigned long transferflags; ++ NTSTATUS ntstatus; ++ ++ struct dvobj_priv *pdvobjpriv = (struct dvobj_priv *)pintfpriv->intf_dev; ++ ++ _func_enter_; ++ ++ ret=_TRUE; ++ purb = (PURB)ExAllocatePool(NonPagedPool, sizeof(struct _URB_CONTROL_VENDOR_OR_CLASS_REQUEST) ); ++ if(purb == NULL) { ++ ++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("usbctrl_vendorreq(): Failed to allocate urb !!!\n")); ++ ret =_FALSE; ++ goto exit; ++ } ++ ++ if (requesttype == 0x01) { ++ transferflags = USBD_TRANSFER_DIRECTION_IN;//read_in ++ } else { ++ transferflags= 0;//write_out ++ } ++ ++ UsbBuildVendorRequest( ++ purb, //Pointer to an URB that is to be formatted as a vendor or class request. ++ URB_FUNCTION_VENDOR_DEVICE, //Indicates the URB is a vendor-defined request for a USB device. ++ sizeof(struct _URB_CONTROL_VENDOR_OR_CLASS_REQUEST), //Specifies the length, in bytes, of the URB. ++ transferflags, //TransferFlags ++ 0, //ReservedBits ++ request, //Request ++ value, //Value ++ index, //Index ++ pdata, //TransferBuffer ++ NULL, //TransferBufferMDL ++ len, //TransferBufferLength ++ NULL //Link ++ ); ++ ++ ntstatus = sync_callusbd(pdvobjpriv, purb); ++ if(!NT_SUCCESS(ntstatus)) ++ { ++ ExFreePool(purb); ++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,(" usbctrl_vendorreq() : SOMETHING WRONG\n") ); ++ ret = _FALSE; ++ goto exit; ++ } ++ ++ ExFreePool(purb); ++ ++exit: ++ _func_exit_; ++ ++ return ret; ++ ++} ++ +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/ifcfg-wlan0 +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/ifcfg-wlan0 2013-07-26 19:36:06.000000000 +0000 +@@ -0,0 +1,4 @@ ++#DHCP client ++DEVICE=wlan0 ++BOOTPROTO=dhcp ++ONBOOT=yes +\ No newline at end of file +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/include/Hal8192CEHWImg.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/include/Hal8192CEHWImg.h 2013-07-26 19:36:06.000000000 +0000 +@@ -0,0 +1,81 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef __INC_HAL8192CE_FW_IMG_H ++#define __INC_HAL8192CE_FW_IMG_H ++ ++#include ++ ++/*Created on 2011/ 6/15, 5:45*/ ++ ++#ifdef CONFIG_BT_COEXISTENCE ++#define TSMCImgArrayLength 16248 //v79 TSMC COMMON 2011-10-06 ++#else //#ifdef CONFIG_P2P ++#define TSMCImgArrayLength 16404 //v79 TSMC P2PPS 2011-10-06 ++#endif ++extern u8 Rtl8192CEFwTSMCImgArray[TSMCImgArrayLength]; ++ ++#ifdef CONFIG_BT_COEXISTENCE ++#define UMCACutImgArrayLength 16248 //v79 UMC A Cut COMMON 2011-10-06 ++#else //#ifdef CONFIG_P2P ++#define UMCACutImgArrayLength 16404 //v79 UMC A Cut P2PPS 2011-10-06 ++#endif ++extern u8 Rtl8192CEFwUMCACutImgArray[UMCACutImgArrayLength]; ++ ++#ifdef CONFIG_BT_COEXISTENCE ++#define UMCBCutImgArrayLength 16254 //v79 UMC B Cut COMMON 2011-10-06 ++#else //#ifdef CONFIG_P2P ++#define UMCBCutImgArrayLength 16386 //v79 UMC B Cut P2PPS 2011-10-06 ++#endif ++extern u8 Rtl8192CEFwUMCBCutImgArray[UMCBCutImgArrayLength]; ++ ++#define PHY_REG_2TArrayLength 374 ++extern u32 Rtl8192CEPHY_REG_2TArray[PHY_REG_2TArrayLength]; ++#define PHY_REG_1TArrayLength 374 ++extern u32 Rtl8192CEPHY_REG_1TArray[PHY_REG_1TArrayLength]; ++#define PHY_ChangeTo_1T1RArrayLength 1 ++extern u32 Rtl8192CEPHY_ChangeTo_1T1RArray[PHY_ChangeTo_1T1RArrayLength]; ++#define PHY_ChangeTo_1T2RArrayLength 1 ++extern u32 Rtl8192CEPHY_ChangeTo_1T2RArray[PHY_ChangeTo_1T2RArrayLength]; ++#define PHY_ChangeTo_2T2RArrayLength 1 ++extern u32 Rtl8192CEPHY_ChangeTo_2T2RArray[PHY_ChangeTo_2T2RArrayLength]; ++#define PHY_REG_Array_PGLength 336 ++extern u32 Rtl8192CEPHY_REG_Array_PG[PHY_REG_Array_PGLength]; ++#define PHY_REG_Array_MPLength 4 ++extern u32 Rtl8192CEPHY_REG_Array_MP[PHY_REG_Array_MPLength]; ++#define RadioA_2TArrayLength 282 ++extern u32 Rtl8192CERadioA_2TArray[RadioA_2TArrayLength]; ++#define RadioB_2TArrayLength 78 ++extern u32 Rtl8192CERadioB_2TArray[RadioB_2TArrayLength]; ++#define RadioA_1TArrayLength 282 ++extern u32 Rtl8192CERadioA_1TArray[RadioA_1TArrayLength]; ++#define RadioB_1TArrayLength 1 ++extern u32 Rtl8192CERadioB_1TArray[RadioB_1TArrayLength]; ++#define RadioB_GM_ArrayLength 1 ++extern u32 Rtl8192CERadioB_GM_Array[RadioB_GM_ArrayLength]; ++#define MAC_2T_ArrayLength 172 ++extern u32 Rtl8192CEMAC_2T_Array[MAC_2T_ArrayLength]; ++#define MACPHY_Array_PGLength 1 ++extern u32 Rtl8192CEMACPHY_Array_PG[MACPHY_Array_PGLength]; ++#define AGCTAB_2TArrayLength 320 ++extern u32 Rtl8192CEAGCTAB_2TArray[AGCTAB_2TArrayLength]; ++#define AGCTAB_1TArrayLength 320 ++extern u32 Rtl8192CEAGCTAB_1TArray[AGCTAB_1TArrayLength]; ++ ++#endif //__INC_HAL8192CE_FW_IMG_H +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/include/Hal8192CPhyCfg.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/include/Hal8192CPhyCfg.h 2013-07-26 19:36:06.000000000 +0000 +@@ -0,0 +1,451 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++/***************************************************************************** ++ * Module: __INC_HAL8192CPHYCFG_H ++ * ++ * ++ * Note: ++ * ++ * ++ * Export: Constants, macro, functions(API), global variables(None). ++ * ++ * Abbrev: ++ * ++ * History: ++ * Data Who Remark ++ * 08/07/2007 MHC 1. Porting from 9x series PHYCFG.h. ++ * 2. Reorganize code architecture. ++ * ++ *****************************************************************************/ ++ /* Check to see if the file has been included already. */ ++#ifndef __INC_HAL8192CPHYCFG_H ++#define __INC_HAL8192CPHYCFG_H ++ ++ ++/*--------------------------Define Parameters-------------------------------*/ ++#define LOOP_LIMIT 5 ++#define MAX_STALL_TIME 50 //us ++#define AntennaDiversityValue 0x80 //(Adapter->bSoftwareAntennaDiversity ? 0x00:0x80) ++#define MAX_TXPWR_IDX_NMODE_92S 63 ++#define Reset_Cnt_Limit 3 ++ ++#define IQK_MAC_REG_NUM 4 ++#define IQK_ADDA_REG_NUM 16 ++#define IQK_BB_REG_NUM 9 ++#define HP_THERMAL_NUM 8 ++ ++#ifdef CONFIG_PCI_HCI ++#define MAX_AGGR_NUM 0x0A0A ++#else ++#define MAX_AGGR_NUM 0x0909 ++#endif ++ ++#ifdef CONFIG_PCI_HCI ++#define SET_RTL8192SE_RF_SLEEP(_pAdapter) \ ++{ \ ++ u1Byte u1bTmp; \ ++ u1bTmp = PlatformEFIORead1Byte(_pAdapter, REG_LDOV12D_CTRL); \ ++ u1bTmp |= BIT0; \ ++ PlatformEFIOWrite1Byte(_pAdapter, REG_LDOV12D_CTRL, u1bTmp); \ ++ PlatformEFIOWrite1Byte(_pAdapter, REG_SPS_OCP_CFG, 0x0); \ ++ PlatformEFIOWrite1Byte(_pAdapter, TXPAUSE, 0xFF); \ ++ PlatformEFIOWrite2Byte(_pAdapter, CMDR, 0x57FC); \ ++ delay_us(100); \ ++ PlatformEFIOWrite2Byte(_pAdapter, CMDR, 0x77FC); \ ++ PlatformEFIOWrite1Byte(_pAdapter, PHY_CCA, 0x0); \ ++ delay_us(10); \ ++ PlatformEFIOWrite2Byte(_pAdapter, CMDR, 0x37FC); \ ++ delay_us(10); \ ++ PlatformEFIOWrite2Byte(_pAdapter, CMDR, 0x77FC); \ ++ delay_us(10); \ ++ PlatformEFIOWrite2Byte(_pAdapter, CMDR, 0x57FC); \ ++} ++#endif ++ ++ ++/*--------------------------Define Parameters-------------------------------*/ ++ ++ ++/*------------------------------Define structure----------------------------*/ ++typedef enum _SwChnlCmdID{ ++ CmdID_End, ++ CmdID_SetTxPowerLevel, ++ CmdID_BBRegWrite10, ++ CmdID_WritePortUlong, ++ CmdID_WritePortUshort, ++ CmdID_WritePortUchar, ++ CmdID_RF_WriteReg, ++}SwChnlCmdID; ++ ++ ++/* 1. Switch channel related */ ++typedef struct _SwChnlCmd{ ++ SwChnlCmdID CmdID; ++ u32 Para1; ++ u32 Para2; ++ u32 msDelay; ++}SwChnlCmd; ++ ++typedef enum _HW90_BLOCK{ ++ HW90_BLOCK_MAC = 0, ++ HW90_BLOCK_PHY0 = 1, ++ HW90_BLOCK_PHY1 = 2, ++ HW90_BLOCK_RF = 3, ++ HW90_BLOCK_MAXIMUM = 4, // Never use this ++}HW90_BLOCK_E, *PHW90_BLOCK_E; ++ ++typedef enum _RF90_RADIO_PATH{ ++ RF90_PATH_A = 0, //Radio Path A ++ RF90_PATH_B = 1, //Radio Path B ++ RF90_PATH_C = 2, //Radio Path C ++ RF90_PATH_D = 3, //Radio Path D ++ //RF90_PATH_MAX //Max RF number 90 support ++}RF90_RADIO_PATH_E, *PRF90_RADIO_PATH_E; ++ ++#define RF90_PATH_MAX 2 ++ ++#define CHANNEL_MAX_NUMBER 14 // 14 is the max channel number ++#define CHANNEL_GROUP_MAX 3 // ch1~3, ch4~9, ch10~14 total three groups ++ ++typedef enum _WIRELESS_MODE { ++ WIRELESS_MODE_UNKNOWN = 0x00, ++ WIRELESS_MODE_A = 0x01, ++ WIRELESS_MODE_B = 0x02, ++ WIRELESS_MODE_G = 0x04, ++ WIRELESS_MODE_AUTO = 0x08, ++ WIRELESS_MODE_N_24G = 0x10, ++ WIRELESS_MODE_N_5G = 0x20 ++} WIRELESS_MODE; ++ ++typedef enum _BaseBand_Config_Type{ ++ BaseBand_Config_PHY_REG = 0, //Radio Path A ++ BaseBand_Config_AGC_TAB = 1, //Radio Path B ++}BaseBand_Config_Type, *PBaseBand_Config_Type; ++ ++ ++typedef enum _PHY_Rate_Tx_Power_Offset_Area{ ++ RA_OFFSET_LEGACY_OFDM1, ++ RA_OFFSET_LEGACY_OFDM2, ++ RA_OFFSET_HT_OFDM1, ++ RA_OFFSET_HT_OFDM2, ++ RA_OFFSET_HT_OFDM3, ++ RA_OFFSET_HT_OFDM4, ++ RA_OFFSET_HT_CCK, ++}RA_OFFSET_AREA,*PRA_OFFSET_AREA; ++ ++ ++/* BB/RF related */ ++typedef enum _RF_TYPE_8190P{ ++ RF_TYPE_MIN, // 0 ++ RF_8225=1, // 1 11b/g RF for verification only ++ RF_8256=2, // 2 11b/g/n ++ RF_8258=3, // 3 11a/b/g/n RF ++ RF_6052=4, // 4 11b/g/n RF ++ //RF_6052=5, // 4 11b/g/n RF ++ // TODO: We sholud remove this psudo PHY RF after we get new RF. ++ RF_PSEUDO_11N=5, // 5, It is a temporality RF. ++}RF_TYPE_8190P_E,*PRF_TYPE_8190P_E; ++ ++ ++typedef enum _RATR_TABLE_MODE_8192C{ ++ RATR_INX_WIRELESS_NGB = 0, ++ RATR_INX_WIRELESS_NG = 1, ++ RATR_INX_WIRELESS_NB = 2, ++ RATR_INX_WIRELESS_N = 3, ++ RATR_INX_WIRELESS_GB = 4, ++ RATR_INX_WIRELESS_G = 5, ++ RATR_INX_WIRELESS_B = 6, ++ RATR_INX_WIRELESS_MC = 7, ++ RATR_INX_WIRELESS_A = 8, ++}RATR_TABLE_MODE_8192C, *PRATR_TABLE_MODE_8192C; ++ ++typedef struct _BB_REGISTER_DEFINITION{ ++ u32 rfintfs; // set software control: ++ // 0x870~0x877[8 bytes] ++ ++ u32 rfintfi; // readback data: ++ // 0x8e0~0x8e7[8 bytes] ++ ++ u32 rfintfo; // output data: ++ // 0x860~0x86f [16 bytes] ++ ++ u32 rfintfe; // output enable: ++ // 0x860~0x86f [16 bytes] ++ ++ u32 rf3wireOffset; // LSSI data: ++ // 0x840~0x84f [16 bytes] ++ ++ u32 rfLSSI_Select; // BB Band Select: ++ // 0x878~0x87f [8 bytes] ++ ++ u32 rfTxGainStage; // Tx gain stage: ++ // 0x80c~0x80f [4 bytes] ++ ++ u32 rfHSSIPara1; // wire parameter control1 : ++ // 0x820~0x823,0x828~0x82b, 0x830~0x833, 0x838~0x83b [16 bytes] ++ ++ u32 rfHSSIPara2; // wire parameter control2 : ++ // 0x824~0x827,0x82c~0x82f, 0x834~0x837, 0x83c~0x83f [16 bytes] ++ ++ u32 rfSwitchControl; //Tx Rx antenna control : ++ // 0x858~0x85f [16 bytes] ++ ++ u32 rfAGCControl1; //AGC parameter control1 : ++ // 0xc50~0xc53,0xc58~0xc5b, 0xc60~0xc63, 0xc68~0xc6b [16 bytes] ++ ++ u32 rfAGCControl2; //AGC parameter control2 : ++ // 0xc54~0xc57,0xc5c~0xc5f, 0xc64~0xc67, 0xc6c~0xc6f [16 bytes] ++ ++ u32 rfRxIQImbalance; //OFDM Rx IQ imbalance matrix : ++ // 0xc14~0xc17,0xc1c~0xc1f, 0xc24~0xc27, 0xc2c~0xc2f [16 bytes] ++ ++ u32 rfRxAFE; //Rx IQ DC ofset and Rx digital filter, Rx DC notch filter : ++ // 0xc10~0xc13,0xc18~0xc1b, 0xc20~0xc23, 0xc28~0xc2b [16 bytes] ++ ++ u32 rfTxIQImbalance; //OFDM Tx IQ imbalance matrix ++ // 0xc80~0xc83,0xc88~0xc8b, 0xc90~0xc93, 0xc98~0xc9b [16 bytes] ++ ++ u32 rfTxAFE; //Tx IQ DC Offset and Tx DFIR type ++ // 0xc84~0xc87,0xc8c~0xc8f, 0xc94~0xc97, 0xc9c~0xc9f [16 bytes] ++ ++ u32 rfLSSIReadBack; //LSSI RF readback data SI mode ++ // 0x8a0~0x8af [16 bytes] ++ ++ u32 rfLSSIReadBackPi; //LSSI RF readback data PI mode 0x8b8-8bc for Path A and B ++ ++}BB_REGISTER_DEFINITION_T, *PBB_REGISTER_DEFINITION_T; ++ ++#ifdef CONFIG_MP_INCLUDED ++typedef enum _ANTENNA_PATH{ ++ ANTENNA_NONE = 0x00, ++ ANTENNA_D , ++ ANTENNA_C , ++ ANTENNA_CD , ++ ANTENNA_B , ++ ANTENNA_BD , ++ ANTENNA_BC , ++ ANTENNA_BCD , ++ ANTENNA_A , ++ ANTENNA_AD , ++ ANTENNA_AC , ++ ANTENNA_ACD , ++ ANTENNA_AB , ++ ANTENNA_ABD , ++ ANTENNA_ABC , ++ ANTENNA_ABCD ++} ANTENNA_PATH; ++#endif ++ ++typedef struct _R_ANTENNA_SELECT_OFDM{ ++ u32 r_tx_antenna:4; ++ u32 r_ant_l:4; ++ u32 r_ant_non_ht:4; ++ u32 r_ant_ht1:4; ++ u32 r_ant_ht2:4; ++ u32 r_ant_ht_s1:4; ++ u32 r_ant_non_ht_s1:4; ++ u32 OFDM_TXSC:2; ++ u32 Reserved:2; ++}R_ANTENNA_SELECT_OFDM; ++ ++typedef struct _R_ANTENNA_SELECT_CCK{ ++ u8 r_cckrx_enable_2:2; ++ u8 r_cckrx_enable:2; ++ u8 r_ccktx_enable:4; ++}R_ANTENNA_SELECT_CCK; ++ ++/*------------------------------Define structure----------------------------*/ ++ ++ ++/*------------------------Export global variable----------------------------*/ ++/*------------------------Export global variable----------------------------*/ ++ ++ ++/*------------------------Export Marco Definition---------------------------*/ ++/*------------------------Export Marco Definition---------------------------*/ ++ ++ ++/*--------------------------Exported Function prototype---------------------*/ ++// ++// BB and RF register read/write ++// ++u32 rtl8192c_PHY_QueryBBReg( IN PADAPTER Adapter, ++ IN u32 RegAddr, ++ IN u32 BitMask ); ++void rtl8192c_PHY_SetBBReg( IN PADAPTER Adapter, ++ IN u32 RegAddr, ++ IN u32 BitMask, ++ IN u32 Data ); ++u32 rtl8192c_PHY_QueryRFReg( IN PADAPTER Adapter, ++ IN RF90_RADIO_PATH_E eRFPath, ++ IN u32 RegAddr, ++ IN u32 BitMask ); ++void rtl8192c_PHY_SetRFReg( IN PADAPTER Adapter, ++ IN RF90_RADIO_PATH_E eRFPath, ++ IN u32 RegAddr, ++ IN u32 BitMask, ++ IN u32 Data ); ++ ++// ++// Initialization related function ++// ++/* MAC/BB/RF HAL config */ ++int PHY_MACConfig8192C( IN PADAPTER Adapter ); ++int PHY_BBConfig8192C( IN PADAPTER Adapter ); ++int PHY_RFConfig8192C( IN PADAPTER Adapter ); ++/* RF config */ ++int rtl8192c_PHY_ConfigRFWithParaFile( IN PADAPTER Adapter, ++ IN u8* pFileName, ++ IN RF90_RADIO_PATH_E eRFPath); ++int rtl8192c_PHY_ConfigRFWithHeaderFile( IN PADAPTER Adapter, ++ IN RF90_RADIO_PATH_E eRFPath); ++ ++/* BB/RF readback check for making sure init OK */ ++int rtl8192c_PHY_CheckBBAndRFOK( IN PADAPTER Adapter, ++ IN HW90_BLOCK_E CheckBlock, ++ IN RF90_RADIO_PATH_E eRFPath ); ++/* Read initi reg value for tx power setting. */ ++void rtl8192c_PHY_GetHWRegOriginalValue( IN PADAPTER Adapter ); ++ ++// ++// RF Power setting ++// ++//extern BOOLEAN PHY_SetRFPowerState(IN PADAPTER Adapter, ++// IN RT_RF_POWER_STATE eRFPowerState); ++ ++// ++// BB TX Power R/W ++// ++void PHY_GetTxPowerLevel8192C( IN PADAPTER Adapter, ++ OUT u32* powerlevel ); ++void PHY_SetTxPowerLevel8192C( IN PADAPTER Adapter, ++ IN u8 channel ); ++BOOLEAN PHY_UpdateTxPowerDbm8192C( IN PADAPTER Adapter, ++ IN int powerInDbm ); ++ ++// ++VOID ++PHY_ScanOperationBackup8192C(IN PADAPTER Adapter, ++ IN u8 Operation ); ++ ++// ++// Switch bandwidth for 8192S ++// ++//extern void PHY_SetBWModeCallback8192C( IN PRT_TIMER pTimer ); ++void PHY_SetBWMode8192C( IN PADAPTER pAdapter, ++ IN HT_CHANNEL_WIDTH ChnlWidth, ++ IN unsigned char Offset ); ++ ++// ++// Set FW CMD IO for 8192S. ++// ++//extern BOOLEAN HalSetIO8192C( IN PADAPTER Adapter, ++// IN IO_TYPE IOType); ++ ++// ++// Set A2 entry to fw for 8192S ++// ++extern void FillA2Entry8192C( IN PADAPTER Adapter, ++ IN u8 index, ++ IN u8* val); ++ ++ ++// ++// channel switch related funciton ++// ++//extern void PHY_SwChnlCallback8192C( IN PRT_TIMER pTimer ); ++void PHY_SwChnl8192C( IN PADAPTER pAdapter, ++ IN u8 channel ); ++ // Call after initialization ++void PHY_SwChnlPhy8192C( IN PADAPTER pAdapter, ++ IN u8 channel ); ++ ++void ChkFwCmdIoDone( IN PADAPTER Adapter); ++ ++#ifdef USE_WORKITEM ++//extern void SetIOWorkItemCallback( IN PVOID pContext ); ++#else ++//extern void SetIOTimerCallback( IN PRT_TIMER pTimer); ++#endif ++ ++// ++// BB/MAC/RF other monitor API ++// ++void PHY_SetMonitorMode8192C(IN PADAPTER pAdapter, ++ IN BOOLEAN bEnableMonitorMode ); ++ ++BOOLEAN PHY_CheckIsLegalRfPath8192C(IN PADAPTER pAdapter, ++ IN u32 eRFPath ); ++ ++// ++// IQ calibrate ++// ++VOID rtl8192c_PHY_IQCalibrate( IN PADAPTER pAdapter , IN BOOLEAN bReCovery); ++ ++// ++// LC calibrate ++// ++VOID rtl8192c_PHY_LCCalibrate(IN PADAPTER pAdapter); ++ ++// ++// AP calibrate ++// ++VOID rtl8192c_PHY_APCalibrate(IN PADAPTER pAdapter, IN char delta); ++ ++VOID rtl8192c_PHY_DigitalPredistortion(IN PADAPTER pAdapter); ++ ++VOID rtl8192c_PHY_SetRFPathSwitch(IN PADAPTER pAdapter, IN BOOLEAN bMain); ++ ++// ++// Modify the value of the hw register when beacon interval be changed. ++// ++void ++rtl8192c_PHY_SetBeaconHwReg( IN PADAPTER Adapter, ++ IN u16 BeaconInterval ); ++ ++ ++extern VOID ++PHY_SwitchEphyParameter( ++ IN PADAPTER Adapter ++ ); ++ ++extern VOID ++PHY_EnableHostClkReq( ++ IN PADAPTER Adapter ++ ); ++ ++BOOLEAN ++SetAntennaConfig92C( ++ IN PADAPTER Adapter, ++ IN u8 DefaultAnt ++ ); ++ ++ ++/*--------------------------Exported Function prototype---------------------*/ ++ ++#define PHY_QueryBBReg(Adapter, RegAddr, BitMask) rtl8192c_PHY_QueryBBReg((Adapter), (RegAddr), (BitMask)) ++#define PHY_SetBBReg(Adapter, RegAddr, BitMask, Data) rtl8192c_PHY_SetBBReg((Adapter), (RegAddr), (BitMask), (Data)) ++#define PHY_QueryRFReg(Adapter, eRFPath, RegAddr, BitMask) rtl8192c_PHY_QueryRFReg((Adapter), (eRFPath), (RegAddr), (BitMask)) ++#define PHY_SetRFReg(Adapter, eRFPath, RegAddr, BitMask, Data) rtl8192c_PHY_SetRFReg((Adapter), (eRFPath), (RegAddr), (BitMask), (Data)) ++ ++#define PHY_SetMacReg PHY_SetBBReg ++ ++#endif // __INC_HAL8192CPHYCFG_H ++ +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/include/Hal8192CPhyReg.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/include/Hal8192CPhyReg.h 2013-07-26 19:36:06.000000000 +0000 +@@ -0,0 +1,1102 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++/***************************************************************************** ++ * ++ * Module: __INC_HAL8192CPHYREG_H ++ * ++ * ++ * Note: 1. Define PMAC/BB register map ++ * 2. Define RF register map ++ * 3. PMAC/BB register bit mask. ++ * 4. RF reg bit mask. ++ * 5. Other BB/RF relative definition. ++ * ++ * ++ * Export: Constants, macro, functions(API), global variables(None). ++ * ++ * Abbrev: ++ * ++ * History: ++ * Data Who Remark ++ * 08/07/2007 MHC 1. Porting from 9x series PHYCFG.h. ++ * 2. Reorganize code architecture. ++ * 09/25/2008 MH 1. Add RL6052 register definition ++ * ++ *****************************************************************************/ ++#ifndef __INC_HAL8192CPHYREG_H ++#define __INC_HAL8192CPHYREG_H ++ ++ ++/*--------------------------Define Parameters-------------------------------*/ ++ ++//============================================================ ++// 8192S Regsiter offset definition ++//============================================================ ++ ++// ++// BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF ++// 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF ++// 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00 ++// 3. RF register 0x00-2E ++// 4. Bit Mask for BB/RF register ++// 5. Other defintion for BB/RF R/W ++// ++ ++ ++// ++// 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF ++// 1. Page1(0x100) ++// ++#define rPMAC_Reset 0x100 ++#define rPMAC_TxStart 0x104 ++#define rPMAC_TxLegacySIG 0x108 ++#define rPMAC_TxHTSIG1 0x10c ++#define rPMAC_TxHTSIG2 0x110 ++#define rPMAC_PHYDebug 0x114 ++#define rPMAC_TxPacketNum 0x118 ++#define rPMAC_TxIdle 0x11c ++#define rPMAC_TxMACHeader0 0x120 ++#define rPMAC_TxMACHeader1 0x124 ++#define rPMAC_TxMACHeader2 0x128 ++#define rPMAC_TxMACHeader3 0x12c ++#define rPMAC_TxMACHeader4 0x130 ++#define rPMAC_TxMACHeader5 0x134 ++#define rPMAC_TxDataType 0x138 ++#define rPMAC_TxRandomSeed 0x13c ++#define rPMAC_CCKPLCPPreamble 0x140 ++#define rPMAC_CCKPLCPHeader 0x144 ++#define rPMAC_CCKCRC16 0x148 ++#define rPMAC_OFDMRxCRC32OK 0x170 ++#define rPMAC_OFDMRxCRC32Er 0x174 ++#define rPMAC_OFDMRxParityEr 0x178 ++#define rPMAC_OFDMRxCRC8Er 0x17c ++#define rPMAC_CCKCRxRC16Er 0x180 ++#define rPMAC_CCKCRxRC32Er 0x184 ++#define rPMAC_CCKCRxRC32OK 0x188 ++#define rPMAC_TxStatus 0x18c ++ ++// ++// 2. Page2(0x200) ++// ++// The following two definition are only used for USB interface. ++#define RF_BB_CMD_ADDR 0x02c0 // RF/BB read/write command address. ++#define RF_BB_CMD_DATA 0x02c4 // RF/BB read/write command data. ++ ++// ++// 3. Page8(0x800) ++// ++#define rFPGA0_RFMOD 0x800 //RF mode & CCK TxSC // RF BW Setting?? ++ ++#define rFPGA0_TxInfo 0x804 // Status report?? ++#define rFPGA0_PSDFunction 0x808 ++ ++#define rFPGA0_TxGainStage 0x80c // Set TX PWR init gain? ++ ++#define rFPGA0_RFTiming1 0x810 // Useless now ++#define rFPGA0_RFTiming2 0x814 ++ ++#define rFPGA0_XA_HSSIParameter1 0x820 // RF 3 wire register ++#define rFPGA0_XA_HSSIParameter2 0x824 ++#define rFPGA0_XB_HSSIParameter1 0x828 ++#define rFPGA0_XB_HSSIParameter2 0x82c ++#define rTxAGC_B_Rate18_06 0x830 ++#define rTxAGC_B_Rate54_24 0x834 ++#define rTxAGC_B_CCK1_55_Mcs32 0x838 ++#define rTxAGC_B_Mcs03_Mcs00 0x83c ++ ++#define rTxAGC_B_Mcs07_Mcs04 0x848 ++#define rTxAGC_B_Mcs11_Mcs08 0x84c ++ ++#define rFPGA0_XA_LSSIParameter 0x840 ++#define rFPGA0_XB_LSSIParameter 0x844 ++ ++#define rFPGA0_RFWakeUpParameter 0x850 // Useless now ++#define rFPGA0_RFSleepUpParameter 0x854 ++ ++#define rFPGA0_XAB_SwitchControl 0x858 // RF Channel switch ++#define rFPGA0_XCD_SwitchControl 0x85c ++ ++#define rFPGA0_XA_RFInterfaceOE 0x860 // RF Channel switch ++#define rFPGA0_XB_RFInterfaceOE 0x864 ++ ++#define rTxAGC_B_Mcs15_Mcs12 0x868 ++#define rTxAGC_B_CCK11_A_CCK2_11 0x86c ++ ++#define rFPGA0_XAB_RFInterfaceSW 0x870 // RF Interface Software Control ++#define rFPGA0_XCD_RFInterfaceSW 0x874 ++ ++#define rFPGA0_XAB_RFParameter 0x878 // RF Parameter ++#define rFPGA0_XCD_RFParameter 0x87c ++ ++#define rFPGA0_AnalogParameter1 0x880 // Crystal cap setting RF-R/W protection for parameter4?? ++#define rFPGA0_AnalogParameter2 0x884 ++#define rFPGA0_AnalogParameter3 0x888 // Useless now ++#define rFPGA0_AnalogParameter4 0x88c ++ ++#define rFPGA0_XA_LSSIReadBack 0x8a0 // Tranceiver LSSI Readback ++#define rFPGA0_XB_LSSIReadBack 0x8a4 ++#define rFPGA0_XC_LSSIReadBack 0x8a8 ++#define rFPGA0_XD_LSSIReadBack 0x8ac ++ ++#define rFPGA0_PSDReport 0x8b4 // Useless now ++#define TransceiverA_HSPI_Readback 0x8b8 // Transceiver A HSPI Readback ++#define TransceiverB_HSPI_Readback 0x8bc // Transceiver B HSPI Readback ++#define rFPGA0_XAB_RFInterfaceRB 0x8e0 // Useless now // RF Interface Readback Value ++#define rFPGA0_XCD_RFInterfaceRB 0x8e4 // Useless now ++ ++// ++// 4. Page9(0x900) ++// ++#define rFPGA1_RFMOD 0x900 //RF mode & OFDM TxSC // RF BW Setting?? ++ ++#define rFPGA1_TxBlock 0x904 // Useless now ++#define rFPGA1_DebugSelect 0x908 // Useless now ++#define rFPGA1_TxInfo 0x90c // Useless now // Status report?? ++ ++// ++// 5. PageA(0xA00) ++// ++// Set Control channel to upper or lower. These settings are required only for 40MHz ++#define rCCK0_System 0xa00 ++ ++#define rCCK0_AFESetting 0xa04 // Disable init gain now // Select RX path by RSSI ++#define rCCK0_CCA 0xa08 // Disable init gain now // Init gain ++ ++#define rCCK0_RxAGC1 0xa0c //AGC default value, saturation level // Antenna Diversity, RX AGC, LNA Threshold, RX LNA Threshold useless now. Not the same as 90 series ++#define rCCK0_RxAGC2 0xa10 //AGC & DAGC ++ ++#define rCCK0_RxHP 0xa14 ++ ++#define rCCK0_DSPParameter1 0xa18 //Timing recovery & Channel estimation threshold ++#define rCCK0_DSPParameter2 0xa1c //SQ threshold ++ ++#define rCCK0_TxFilter1 0xa20 ++#define rCCK0_TxFilter2 0xa24 ++#define rCCK0_DebugPort 0xa28 //debug port and Tx filter3 ++#define rCCK0_FalseAlarmReport 0xa2c //0xa2d useless now 0xa30-a4f channel report ++#define rCCK0_TRSSIReport 0xa50 ++#define rCCK0_RxReport 0xa54 //0xa57 ++#define rCCK0_FACounterLower 0xa5c //0xa5b ++#define rCCK0_FACounterUpper 0xa58 //0xa5c ++ ++// ++// 6. PageC(0xC00) ++// ++#define rOFDM0_LSTF 0xc00 ++ ++#define rOFDM0_TRxPathEnable 0xc04 ++#define rOFDM0_TRMuxPar 0xc08 ++#define rOFDM0_TRSWIsolation 0xc0c ++ ++#define rOFDM0_XARxAFE 0xc10 //RxIQ DC offset, Rx digital filter, DC notch filter ++#define rOFDM0_XARxIQImbalance 0xc14 //RxIQ imblance matrix ++#define rOFDM0_XBRxAFE 0xc18 ++#define rOFDM0_XBRxIQImbalance 0xc1c ++#define rOFDM0_XCRxAFE 0xc20 ++#define rOFDM0_XCRxIQImbalance 0xc24 ++#define rOFDM0_XDRxAFE 0xc28 ++#define rOFDM0_XDRxIQImbalance 0xc2c ++ ++#define rOFDM0_RxDetector1 0xc30 //PD,BW & SBD // DM tune init gain ++#define rOFDM0_RxDetector2 0xc34 //SBD & Fame Sync. ++#define rOFDM0_RxDetector3 0xc38 //Frame Sync. ++#define rOFDM0_RxDetector4 0xc3c //PD, SBD, Frame Sync & Short-GI ++ ++#define rOFDM0_RxDSP 0xc40 //Rx Sync Path ++#define rOFDM0_CFOandDAGC 0xc44 //CFO & DAGC ++#define rOFDM0_CCADropThreshold 0xc48 //CCA Drop threshold ++#define rOFDM0_ECCAThreshold 0xc4c // energy CCA ++ ++#define rOFDM0_XAAGCCore1 0xc50 // DIG ++#define rOFDM0_XAAGCCore2 0xc54 ++#define rOFDM0_XBAGCCore1 0xc58 ++#define rOFDM0_XBAGCCore2 0xc5c ++#define rOFDM0_XCAGCCore1 0xc60 ++#define rOFDM0_XCAGCCore2 0xc64 ++#define rOFDM0_XDAGCCore1 0xc68 ++#define rOFDM0_XDAGCCore2 0xc6c ++ ++#define rOFDM0_AGCParameter1 0xc70 ++#define rOFDM0_AGCParameter2 0xc74 ++#define rOFDM0_AGCRSSITable 0xc78 ++#define rOFDM0_HTSTFAGC 0xc7c ++ ++#define rOFDM0_XATxIQImbalance 0xc80 // TX PWR TRACK and DIG ++#define rOFDM0_XATxAFE 0xc84 ++#define rOFDM0_XBTxIQImbalance 0xc88 ++#define rOFDM0_XBTxAFE 0xc8c ++#define rOFDM0_XCTxIQImbalance 0xc90 ++#define rOFDM0_XCTxAFE 0xc94 ++#define rOFDM0_XDTxIQImbalance 0xc98 ++#define rOFDM0_XDTxAFE 0xc9c ++ ++#define rOFDM0_RxIQExtAnta 0xca0 ++#define rOFDM0_TxCoeff1 0xca4 ++#define rOFDM0_TxCoeff2 0xca8 ++#define rOFDM0_TxCoeff3 0xcac ++#define rOFDM0_TxCoeff4 0xcb0 ++#define rOFDM0_TxCoeff5 0xcb4 ++#define rOFDM0_TxCoeff6 0xcb8 ++#define rOFDM0_RxHPParameter 0xce0 ++#define rOFDM0_TxPseudoNoiseWgt 0xce4 ++#define rOFDM0_FrameSync 0xcf0 ++#define rOFDM0_DFSReport 0xcf4 ++ ++// ++// 7. PageD(0xD00) ++// ++#define rOFDM1_LSTF 0xd00 ++#define rOFDM1_TRxPathEnable 0xd04 ++ ++#define rOFDM1_CFO 0xd08 // No setting now ++#define rOFDM1_CSI1 0xd10 ++#define rOFDM1_SBD 0xd14 ++#define rOFDM1_CSI2 0xd18 ++#define rOFDM1_CFOTracking 0xd2c ++#define rOFDM1_TRxMesaure1 0xd34 ++#define rOFDM1_IntfDet 0xd3c ++#define rOFDM1_PseudoNoiseStateAB 0xd50 ++#define rOFDM1_PseudoNoiseStateCD 0xd54 ++#define rOFDM1_RxPseudoNoiseWgt 0xd58 ++ ++#define rOFDM_PHYCounter1 0xda0 //cca, parity fail ++#define rOFDM_PHYCounter2 0xda4 //rate illegal, crc8 fail ++#define rOFDM_PHYCounter3 0xda8 //MCS not support ++ ++#define rOFDM_ShortCFOAB 0xdac // No setting now ++#define rOFDM_ShortCFOCD 0xdb0 ++#define rOFDM_LongCFOAB 0xdb4 ++#define rOFDM_LongCFOCD 0xdb8 ++#define rOFDM_TailCFOAB 0xdbc ++#define rOFDM_TailCFOCD 0xdc0 ++#define rOFDM_PWMeasure1 0xdc4 ++#define rOFDM_PWMeasure2 0xdc8 ++#define rOFDM_BWReport 0xdcc ++#define rOFDM_AGCReport 0xdd0 ++#define rOFDM_RxSNR 0xdd4 ++#define rOFDM_RxEVMCSI 0xdd8 ++#define rOFDM_SIGReport 0xddc ++ ++ ++// ++// 8. PageE(0xE00) ++// ++#define rTxAGC_A_Rate18_06 0xe00 ++#define rTxAGC_A_Rate54_24 0xe04 ++#define rTxAGC_A_CCK1_Mcs32 0xe08 ++#define rTxAGC_A_Mcs03_Mcs00 0xe10 ++#define rTxAGC_A_Mcs07_Mcs04 0xe14 ++#define rTxAGC_A_Mcs11_Mcs08 0xe18 ++#define rTxAGC_A_Mcs15_Mcs12 0xe1c ++ ++#define rFPGA0_IQK 0xe28 ++#define rTx_IQK_Tone_A 0xe30 ++#define rRx_IQK_Tone_A 0xe34 ++#define rTx_IQK_PI_A 0xe38 ++#define rRx_IQK_PI_A 0xe3c ++ ++#define rTx_IQK 0xe40 ++#define rRx_IQK 0xe44 ++#define rIQK_AGC_Pts 0xe48 ++#define rIQK_AGC_Rsp 0xe4c ++#define rTx_IQK_Tone_B 0xe50 ++#define rRx_IQK_Tone_B 0xe54 ++#define rTx_IQK_PI_B 0xe58 ++#define rRx_IQK_PI_B 0xe5c ++#define rIQK_AGC_Cont 0xe60 ++ ++#define rBlue_Tooth 0xe6c ++#define rRx_Wait_CCA 0xe70 ++#define rTx_CCK_RFON 0xe74 ++#define rTx_CCK_BBON 0xe78 ++#define rTx_OFDM_RFON 0xe7c ++#define rTx_OFDM_BBON 0xe80 ++#define rTx_To_Rx 0xe84 ++#define rTx_To_Tx 0xe88 ++#define rRx_CCK 0xe8c ++ ++#define rTx_Power_Before_IQK_A 0xe94 ++#define rTx_Power_After_IQK_A 0xe9c ++ ++#define rRx_Power_Before_IQK_A 0xea0 ++#define rRx_Power_Before_IQK_A_2 0xea4 ++#define rRx_Power_After_IQK_A 0xea8 ++#define rRx_Power_After_IQK_A_2 0xeac ++ ++#define rTx_Power_Before_IQK_B 0xeb4 ++#define rTx_Power_After_IQK_B 0xebc ++ ++#define rRx_Power_Before_IQK_B 0xec0 ++#define rRx_Power_Before_IQK_B_2 0xec4 ++#define rRx_Power_After_IQK_B 0xec8 ++#define rRx_Power_After_IQK_B_2 0xecc ++ ++#define rRx_OFDM 0xed0 ++#define rRx_Wait_RIFS 0xed4 ++#define rRx_TO_Rx 0xed8 ++#define rStandby 0xedc ++#define rSleep 0xee0 ++#define rPMPD_ANAEN 0xeec ++ ++// ++// 7. RF Register 0x00-0x2E (RF 8256) ++// RF-0222D 0x00-3F ++// ++//Zebra1 ++#define rZebra1_HSSIEnable 0x0 // Useless now ++#define rZebra1_TRxEnable1 0x1 ++#define rZebra1_TRxEnable2 0x2 ++#define rZebra1_AGC 0x4 ++#define rZebra1_ChargePump 0x5 ++#define rZebra1_Channel 0x7 // RF channel switch ++ ++//#endif ++#define rZebra1_TxGain 0x8 // Useless now ++#define rZebra1_TxLPF 0x9 ++#define rZebra1_RxLPF 0xb ++#define rZebra1_RxHPFCorner 0xc ++ ++//Zebra4 ++#define rGlobalCtrl 0 // Useless now ++#define rRTL8256_TxLPF 19 ++#define rRTL8256_RxLPF 11 ++ ++//RTL8258 ++#define rRTL8258_TxLPF 0x11 // Useless now ++#define rRTL8258_RxLPF 0x13 ++#define rRTL8258_RSSILPF 0xa ++ ++// ++// RL6052 Register definition ++// ++#define RF_AC 0x00 // ++ ++#define RF_IQADJ_G1 0x01 // ++#define RF_IQADJ_G2 0x02 // ++#define RF_POW_TRSW 0x05 // ++ ++#define RF_GAIN_RX 0x06 // ++#define RF_GAIN_TX 0x07 // ++ ++#define RF_TXM_IDAC 0x08 // ++#define RF_BS_IQGEN 0x0F // ++ ++#define RF_MODE1 0x10 // ++#define RF_MODE2 0x11 // ++ ++#define RF_RX_AGC_HP 0x12 // ++#define RF_TX_AGC 0x13 // ++#define RF_BIAS 0x14 // ++#define RF_IPA 0x15 // ++#define RF_POW_ABILITY 0x17 // ++#define RF_MODE_AG 0x18 // ++#define rRfChannel 0x18 // RF channel and BW switch ++#define RF_CHNLBW 0x18 // RF channel and BW switch ++#define RF_TOP 0x19 // ++ ++#define RF_RX_G1 0x1A // ++#define RF_RX_G2 0x1B // ++ ++#define RF_RX_BB2 0x1C // ++#define RF_RX_BB1 0x1D // ++ ++#define RF_RCK1 0x1E // ++#define RF_RCK2 0x1F // ++ ++#define RF_TX_G1 0x20 // ++#define RF_TX_G2 0x21 // ++#define RF_TX_G3 0x22 // ++ ++#define RF_TX_BB1 0x23 // ++ ++#define RF_T_METER 0x24 // ++ ++#define RF_SYN_G1 0x25 // RF TX Power control ++#define RF_SYN_G2 0x26 // RF TX Power control ++#define RF_SYN_G3 0x27 // RF TX Power control ++#define RF_SYN_G4 0x28 // RF TX Power control ++#define RF_SYN_G5 0x29 // RF TX Power control ++#define RF_SYN_G6 0x2A // RF TX Power control ++#define RF_SYN_G7 0x2B // RF TX Power control ++#define RF_SYN_G8 0x2C // RF TX Power control ++ ++#define RF_RCK_OS 0x30 // RF TX PA control ++ ++#define RF_TXPA_G1 0x31 // RF TX PA control ++#define RF_TXPA_G2 0x32 // RF TX PA control ++#define RF_TXPA_G3 0x33 // RF TX PA control ++ ++// ++//Bit Mask ++// ++// 1. Page1(0x100) ++#define bBBResetB 0x100 // Useless now? ++#define bGlobalResetB 0x200 ++#define bOFDMTxStart 0x4 ++#define bCCKTxStart 0x8 ++#define bCRC32Debug 0x100 ++#define bPMACLoopback 0x10 ++#define bTxLSIG 0xffffff ++#define bOFDMTxRate 0xf ++#define bOFDMTxReserved 0x10 ++#define bOFDMTxLength 0x1ffe0 ++#define bOFDMTxParity 0x20000 ++#define bTxHTSIG1 0xffffff ++#define bTxHTMCSRate 0x7f ++#define bTxHTBW 0x80 ++#define bTxHTLength 0xffff00 ++#define bTxHTSIG2 0xffffff ++#define bTxHTSmoothing 0x1 ++#define bTxHTSounding 0x2 ++#define bTxHTReserved 0x4 ++#define bTxHTAggreation 0x8 ++#define bTxHTSTBC 0x30 ++#define bTxHTAdvanceCoding 0x40 ++#define bTxHTShortGI 0x80 ++#define bTxHTNumberHT_LTF 0x300 ++#define bTxHTCRC8 0x3fc00 ++#define bCounterReset 0x10000 ++#define bNumOfOFDMTx 0xffff ++#define bNumOfCCKTx 0xffff0000 ++#define bTxIdleInterval 0xffff ++#define bOFDMService 0xffff0000 ++#define bTxMACHeader 0xffffffff ++#define bTxDataInit 0xff ++#define bTxHTMode 0x100 ++#define bTxDataType 0x30000 ++#define bTxRandomSeed 0xffffffff ++#define bCCKTxPreamble 0x1 ++#define bCCKTxSFD 0xffff0000 ++#define bCCKTxSIG 0xff ++#define bCCKTxService 0xff00 ++#define bCCKLengthExt 0x8000 ++#define bCCKTxLength 0xffff0000 ++#define bCCKTxCRC16 0xffff ++#define bCCKTxStatus 0x1 ++#define bOFDMTxStatus 0x2 ++ ++#define IS_BB_REG_OFFSET_92S(_Offset) ((_Offset >= 0x800) && (_Offset <= 0xfff)) ++ ++// 2. Page8(0x800) ++#define bRFMOD 0x1 // Reg 0x800 rFPGA0_RFMOD ++#define bJapanMode 0x2 ++#define bCCKTxSC 0x30 ++#define bCCKEn 0x1000000 ++#define bOFDMEn 0x2000000 ++ ++#define bOFDMRxADCPhase 0x10000 // Useless now ++#define bOFDMTxDACPhase 0x40000 ++#define bXATxAGC 0x3f ++ ++#define bAntennaSelect 0x0300 ++ ++#define bXBTxAGC 0xf00 // Reg 80c rFPGA0_TxGainStage ++#define bXCTxAGC 0xf000 ++#define bXDTxAGC 0xf0000 ++ ++#define bPAStart 0xf0000000 // Useless now ++#define bTRStart 0x00f00000 ++#define bRFStart 0x0000f000 ++#define bBBStart 0x000000f0 ++#define bBBCCKStart 0x0000000f ++#define bPAEnd 0xf //Reg0x814 ++#define bTREnd 0x0f000000 ++#define bRFEnd 0x000f0000 ++#define bCCAMask 0x000000f0 //T2R ++#define bR2RCCAMask 0x00000f00 ++#define bHSSI_R2TDelay 0xf8000000 ++#define bHSSI_T2RDelay 0xf80000 ++#define bContTxHSSI 0x400 //chane gain at continue Tx ++#define bIGFromCCK 0x200 ++#define bAGCAddress 0x3f ++#define bRxHPTx 0x7000 ++#define bRxHPT2R 0x38000 ++#define bRxHPCCKIni 0xc0000 ++#define bAGCTxCode 0xc00000 ++#define bAGCRxCode 0x300000 ++ ++#define b3WireDataLength 0x800 // Reg 0x820~84f rFPGA0_XA_HSSIParameter1 ++#define b3WireAddressLength 0x400 ++ ++#define b3WireRFPowerDown 0x1 // Useless now ++//#define bHWSISelect 0x8 ++#define b5GPAPEPolarity 0x40000000 ++#define b2GPAPEPolarity 0x80000000 ++#define bRFSW_TxDefaultAnt 0x3 ++#define bRFSW_TxOptionAnt 0x30 ++#define bRFSW_RxDefaultAnt 0x300 ++#define bRFSW_RxOptionAnt 0x3000 ++#define bRFSI_3WireData 0x1 ++#define bRFSI_3WireClock 0x2 ++#define bRFSI_3WireLoad 0x4 ++#define bRFSI_3WireRW 0x8 ++#define bRFSI_3Wire 0xf ++ ++#define bRFSI_RFENV 0x10 // Reg 0x870 rFPGA0_XAB_RFInterfaceSW ++ ++#define bRFSI_TRSW 0x20 // Useless now ++#define bRFSI_TRSWB 0x40 ++#define bRFSI_ANTSW 0x100 ++#define bRFSI_ANTSWB 0x200 ++#define bRFSI_PAPE 0x400 ++#define bRFSI_PAPE5G 0x800 ++#define bBandSelect 0x1 ++#define bHTSIG2_GI 0x80 ++#define bHTSIG2_Smoothing 0x01 ++#define bHTSIG2_Sounding 0x02 ++#define bHTSIG2_Aggreaton 0x08 ++#define bHTSIG2_STBC 0x30 ++#define bHTSIG2_AdvCoding 0x40 ++#define bHTSIG2_NumOfHTLTF 0x300 ++#define bHTSIG2_CRC8 0x3fc ++#define bHTSIG1_MCS 0x7f ++#define bHTSIG1_BandWidth 0x80 ++#define bHTSIG1_HTLength 0xffff ++#define bLSIG_Rate 0xf ++#define bLSIG_Reserved 0x10 ++#define bLSIG_Length 0x1fffe ++#define bLSIG_Parity 0x20 ++#define bCCKRxPhase 0x4 ++ ++#define bLSSIReadAddress 0x7f800000 // T65 RF ++ ++#define bLSSIReadEdge 0x80000000 //LSSI "Read" edge signal ++ ++#define bLSSIReadBackData 0xfffff // T65 RF ++ ++#define bLSSIReadOKFlag 0x1000 // Useless now ++#define bCCKSampleRate 0x8 //0: 44MHz, 1:88MHz ++#define bRegulator0Standby 0x1 ++#define bRegulatorPLLStandby 0x2 ++#define bRegulator1Standby 0x4 ++#define bPLLPowerUp 0x8 ++#define bDPLLPowerUp 0x10 ++#define bDA10PowerUp 0x20 ++#define bAD7PowerUp 0x200 ++#define bDA6PowerUp 0x2000 ++#define bXtalPowerUp 0x4000 ++#define b40MDClkPowerUP 0x8000 ++#define bDA6DebugMode 0x20000 ++#define bDA6Swing 0x380000 ++ ++#define bADClkPhase 0x4000000 // Reg 0x880 rFPGA0_AnalogParameter1 20/40 CCK support switch 40/80 BB MHZ ++ ++#define b80MClkDelay 0x18000000 // Useless ++#define bAFEWatchDogEnable 0x20000000 ++ ++#define bXtalCap01 0xc0000000 // Reg 0x884 rFPGA0_AnalogParameter2 Crystal cap ++#define bXtalCap23 0x3 ++#define bXtalCap92x 0x0f000000 ++#define bXtalCap 0x0f000000 ++ ++#define bIntDifClkEnable 0x400 // Useless ++#define bExtSigClkEnable 0x800 ++#define bBandgapMbiasPowerUp 0x10000 ++#define bAD11SHGain 0xc0000 ++#define bAD11InputRange 0x700000 ++#define bAD11OPCurrent 0x3800000 ++#define bIPathLoopback 0x4000000 ++#define bQPathLoopback 0x8000000 ++#define bAFELoopback 0x10000000 ++#define bDA10Swing 0x7e0 ++#define bDA10Reverse 0x800 ++#define bDAClkSource 0x1000 ++#define bAD7InputRange 0x6000 ++#define bAD7Gain 0x38000 ++#define bAD7OutputCMMode 0x40000 ++#define bAD7InputCMMode 0x380000 ++#define bAD7Current 0xc00000 ++#define bRegulatorAdjust 0x7000000 ++#define bAD11PowerUpAtTx 0x1 ++#define bDA10PSAtTx 0x10 ++#define bAD11PowerUpAtRx 0x100 ++#define bDA10PSAtRx 0x1000 ++#define bCCKRxAGCFormat 0x200 ++#define bPSDFFTSamplepPoint 0xc000 ++#define bPSDAverageNum 0x3000 ++#define bIQPathControl 0xc00 ++#define bPSDFreq 0x3ff ++#define bPSDAntennaPath 0x30 ++#define bPSDIQSwitch 0x40 ++#define bPSDRxTrigger 0x400000 ++#define bPSDTxTrigger 0x80000000 ++#define bPSDSineToneScale 0x7f000000 ++#define bPSDReport 0xffff ++ ++// 3. Page9(0x900) ++#define bOFDMTxSC 0x30000000 // Useless ++#define bCCKTxOn 0x1 ++#define bOFDMTxOn 0x2 ++#define bDebugPage 0xfff //reset debug page and also HWord, LWord ++#define bDebugItem 0xff //reset debug page and LWord ++#define bAntL 0x10 ++#define bAntNonHT 0x100 ++#define bAntHT1 0x1000 ++#define bAntHT2 0x10000 ++#define bAntHT1S1 0x100000 ++#define bAntNonHTS1 0x1000000 ++ ++// 4. PageA(0xA00) ++#define bCCKBBMode 0x3 // Useless ++#define bCCKTxPowerSaving 0x80 ++#define bCCKRxPowerSaving 0x40 ++ ++#define bCCKSideBand 0x10 // Reg 0xa00 rCCK0_System 20/40 switch ++ ++#define bCCKScramble 0x8 // Useless ++#define bCCKAntDiversity 0x8000 ++#define bCCKCarrierRecovery 0x4000 ++#define bCCKTxRate 0x3000 ++#define bCCKDCCancel 0x0800 ++#define bCCKISICancel 0x0400 ++#define bCCKMatchFilter 0x0200 ++#define bCCKEqualizer 0x0100 ++#define bCCKPreambleDetect 0x800000 ++#define bCCKFastFalseCCA 0x400000 ++#define bCCKChEstStart 0x300000 ++#define bCCKCCACount 0x080000 ++#define bCCKcs_lim 0x070000 ++#define bCCKBistMode 0x80000000 ++#define bCCKCCAMask 0x40000000 ++#define bCCKTxDACPhase 0x4 ++#define bCCKRxADCPhase 0x20000000 //r_rx_clk ++#define bCCKr_cp_mode0 0x0100 ++#define bCCKTxDCOffset 0xf0 ++#define bCCKRxDCOffset 0xf ++#define bCCKCCAMode 0xc000 ++#define bCCKFalseCS_lim 0x3f00 ++#define bCCKCS_ratio 0xc00000 ++#define bCCKCorgBit_sel 0x300000 ++#define bCCKPD_lim 0x0f0000 ++#define bCCKNewCCA 0x80000000 ++#define bCCKRxHPofIG 0x8000 ++#define bCCKRxIG 0x7f00 ++#define bCCKLNAPolarity 0x800000 ++#define bCCKRx1stGain 0x7f0000 ++#define bCCKRFExtend 0x20000000 //CCK Rx Iinital gain polarity ++#define bCCKRxAGCSatLevel 0x1f000000 ++#define bCCKRxAGCSatCount 0xe0 ++#define bCCKRxRFSettle 0x1f //AGCsamp_dly ++#define bCCKFixedRxAGC 0x8000 ++//#define bCCKRxAGCFormat 0x4000 //remove to HSSI register 0x824 ++#define bCCKAntennaPolarity 0x2000 ++#define bCCKTxFilterType 0x0c00 ++#define bCCKRxAGCReportType 0x0300 ++#define bCCKRxDAGCEn 0x80000000 ++#define bCCKRxDAGCPeriod 0x20000000 ++#define bCCKRxDAGCSatLevel 0x1f000000 ++#define bCCKTimingRecovery 0x800000 ++#define bCCKTxC0 0x3f0000 ++#define bCCKTxC1 0x3f000000 ++#define bCCKTxC2 0x3f ++#define bCCKTxC3 0x3f00 ++#define bCCKTxC4 0x3f0000 ++#define bCCKTxC5 0x3f000000 ++#define bCCKTxC6 0x3f ++#define bCCKTxC7 0x3f00 ++#define bCCKDebugPort 0xff0000 ++#define bCCKDACDebug 0x0f000000 ++#define bCCKFalseAlarmEnable 0x8000 ++#define bCCKFalseAlarmRead 0x4000 ++#define bCCKTRSSI 0x7f ++#define bCCKRxAGCReport 0xfe ++#define bCCKRxReport_AntSel 0x80000000 ++#define bCCKRxReport_MFOff 0x40000000 ++#define bCCKRxRxReport_SQLoss 0x20000000 ++#define bCCKRxReport_Pktloss 0x10000000 ++#define bCCKRxReport_Lockedbit 0x08000000 ++#define bCCKRxReport_RateError 0x04000000 ++#define bCCKRxReport_RxRate 0x03000000 ++#define bCCKRxFACounterLower 0xff ++#define bCCKRxFACounterUpper 0xff000000 ++#define bCCKRxHPAGCStart 0xe000 ++#define bCCKRxHPAGCFinal 0x1c00 ++#define bCCKRxFalseAlarmEnable 0x8000 ++#define bCCKFACounterFreeze 0x4000 ++#define bCCKTxPathSel 0x10000000 ++#define bCCKDefaultRxPath 0xc000000 ++#define bCCKOptionRxPath 0x3000000 ++ ++// 5. PageC(0xC00) ++#define bNumOfSTF 0x3 // Useless ++#define bShift_L 0xc0 ++#define bGI_TH 0xc ++#define bRxPathA 0x1 ++#define bRxPathB 0x2 ++#define bRxPathC 0x4 ++#define bRxPathD 0x8 ++#define bTxPathA 0x1 ++#define bTxPathB 0x2 ++#define bTxPathC 0x4 ++#define bTxPathD 0x8 ++#define bTRSSIFreq 0x200 ++#define bADCBackoff 0x3000 ++#define bDFIRBackoff 0xc000 ++#define bTRSSILatchPhase 0x10000 ++#define bRxIDCOffset 0xff ++#define bRxQDCOffset 0xff00 ++#define bRxDFIRMode 0x1800000 ++#define bRxDCNFType 0xe000000 ++#define bRXIQImb_A 0x3ff ++#define bRXIQImb_B 0xfc00 ++#define bRXIQImb_C 0x3f0000 ++#define bRXIQImb_D 0xffc00000 ++#define bDC_dc_Notch 0x60000 ++#define bRxNBINotch 0x1f000000 ++#define bPD_TH 0xf ++#define bPD_TH_Opt2 0xc000 ++#define bPWED_TH 0x700 ++#define bIfMF_Win_L 0x800 ++#define bPD_Option 0x1000 ++#define bMF_Win_L 0xe000 ++#define bBW_Search_L 0x30000 ++#define bwin_enh_L 0xc0000 ++#define bBW_TH 0x700000 ++#define bED_TH2 0x3800000 ++#define bBW_option 0x4000000 ++#define bRatio_TH 0x18000000 ++#define bWindow_L 0xe0000000 ++#define bSBD_Option 0x1 ++#define bFrame_TH 0x1c ++#define bFS_Option 0x60 ++#define bDC_Slope_check 0x80 ++#define bFGuard_Counter_DC_L 0xe00 ++#define bFrame_Weight_Short 0x7000 ++#define bSub_Tune 0xe00000 ++#define bFrame_DC_Length 0xe000000 ++#define bSBD_start_offset 0x30000000 ++#define bFrame_TH_2 0x7 ++#define bFrame_GI2_TH 0x38 ++#define bGI2_Sync_en 0x40 ++#define bSarch_Short_Early 0x300 ++#define bSarch_Short_Late 0xc00 ++#define bSarch_GI2_Late 0x70000 ++#define bCFOAntSum 0x1 ++#define bCFOAcc 0x2 ++#define bCFOStartOffset 0xc ++#define bCFOLookBack 0x70 ++#define bCFOSumWeight 0x80 ++#define bDAGCEnable 0x10000 ++#define bTXIQImb_A 0x3ff ++#define bTXIQImb_B 0xfc00 ++#define bTXIQImb_C 0x3f0000 ++#define bTXIQImb_D 0xffc00000 ++#define bTxIDCOffset 0xff ++#define bTxQDCOffset 0xff00 ++#define bTxDFIRMode 0x10000 ++#define bTxPesudoNoiseOn 0x4000000 ++#define bTxPesudoNoise_A 0xff ++#define bTxPesudoNoise_B 0xff00 ++#define bTxPesudoNoise_C 0xff0000 ++#define bTxPesudoNoise_D 0xff000000 ++#define bCCADropOption 0x20000 ++#define bCCADropThres 0xfff00000 ++#define bEDCCA_H 0xf ++#define bEDCCA_L 0xf0 ++#define bLambda_ED 0x300 ++#define bRxInitialGain 0x7f ++#define bRxAntDivEn 0x80 ++#define bRxAGCAddressForLNA 0x7f00 ++#define bRxHighPowerFlow 0x8000 ++#define bRxAGCFreezeThres 0xc0000 ++#define bRxFreezeStep_AGC1 0x300000 ++#define bRxFreezeStep_AGC2 0xc00000 ++#define bRxFreezeStep_AGC3 0x3000000 ++#define bRxFreezeStep_AGC0 0xc000000 ++#define bRxRssi_Cmp_En 0x10000000 ++#define bRxQuickAGCEn 0x20000000 ++#define bRxAGCFreezeThresMode 0x40000000 ++#define bRxOverFlowCheckType 0x80000000 ++#define bRxAGCShift 0x7f ++#define bTRSW_Tri_Only 0x80 ++#define bPowerThres 0x300 ++#define bRxAGCEn 0x1 ++#define bRxAGCTogetherEn 0x2 ++#define bRxAGCMin 0x4 ++#define bRxHP_Ini 0x7 ++#define bRxHP_TRLNA 0x70 ++#define bRxHP_RSSI 0x700 ++#define bRxHP_BBP1 0x7000 ++#define bRxHP_BBP2 0x70000 ++#define bRxHP_BBP3 0x700000 ++#define bRSSI_H 0x7f0000 //the threshold for high power ++#define bRSSI_Gen 0x7f000000 //the threshold for ant diversity ++#define bRxSettle_TRSW 0x7 ++#define bRxSettle_LNA 0x38 ++#define bRxSettle_RSSI 0x1c0 ++#define bRxSettle_BBP 0xe00 ++#define bRxSettle_RxHP 0x7000 ++#define bRxSettle_AntSW_RSSI 0x38000 ++#define bRxSettle_AntSW 0xc0000 ++#define bRxProcessTime_DAGC 0x300000 ++#define bRxSettle_HSSI 0x400000 ++#define bRxProcessTime_BBPPW 0x800000 ++#define bRxAntennaPowerShift 0x3000000 ++#define bRSSITableSelect 0xc000000 ++#define bRxHP_Final 0x7000000 ++#define bRxHTSettle_BBP 0x7 ++#define bRxHTSettle_HSSI 0x8 ++#define bRxHTSettle_RxHP 0x70 ++#define bRxHTSettle_BBPPW 0x80 ++#define bRxHTSettle_Idle 0x300 ++#define bRxHTSettle_Reserved 0x1c00 ++#define bRxHTRxHPEn 0x8000 ++#define bRxHTAGCFreezeThres 0x30000 ++#define bRxHTAGCTogetherEn 0x40000 ++#define bRxHTAGCMin 0x80000 ++#define bRxHTAGCEn 0x100000 ++#define bRxHTDAGCEn 0x200000 ++#define bRxHTRxHP_BBP 0x1c00000 ++#define bRxHTRxHP_Final 0xe0000000 ++#define bRxPWRatioTH 0x3 ++#define bRxPWRatioEn 0x4 ++#define bRxMFHold 0x3800 ++#define bRxPD_Delay_TH1 0x38 ++#define bRxPD_Delay_TH2 0x1c0 ++#define bRxPD_DC_COUNT_MAX 0x600 ++//#define bRxMF_Hold 0x3800 ++#define bRxPD_Delay_TH 0x8000 ++#define bRxProcess_Delay 0xf0000 ++#define bRxSearchrange_GI2_Early 0x700000 ++#define bRxFrame_Guard_Counter_L 0x3800000 ++#define bRxSGI_Guard_L 0xc000000 ++#define bRxSGI_Search_L 0x30000000 ++#define bRxSGI_TH 0xc0000000 ++#define bDFSCnt0 0xff ++#define bDFSCnt1 0xff00 ++#define bDFSFlag 0xf0000 ++#define bMFWeightSum 0x300000 ++#define bMinIdxTH 0x7f000000 ++#define bDAFormat 0x40000 ++#define bTxChEmuEnable 0x01000000 ++#define bTRSWIsolation_A 0x7f ++#define bTRSWIsolation_B 0x7f00 ++#define bTRSWIsolation_C 0x7f0000 ++#define bTRSWIsolation_D 0x7f000000 ++#define bExtLNAGain 0x7c00 ++ ++// 6. PageE(0xE00) ++#define bSTBCEn 0x4 // Useless ++#define bAntennaMapping 0x10 ++#define bNss 0x20 ++#define bCFOAntSumD 0x200 ++#define bPHYCounterReset 0x8000000 ++#define bCFOReportGet 0x4000000 ++#define bOFDMContinueTx 0x10000000 ++#define bOFDMSingleCarrier 0x20000000 ++#define bOFDMSingleTone 0x40000000 ++//#define bRxPath1 0x01 ++//#define bRxPath2 0x02 ++//#define bRxPath3 0x04 ++//#define bRxPath4 0x08 ++//#define bTxPath1 0x10 ++//#define bTxPath2 0x20 ++#define bHTDetect 0x100 ++#define bCFOEn 0x10000 ++#define bCFOValue 0xfff00000 ++#define bSigTone_Re 0x3f ++#define bSigTone_Im 0x7f00 ++#define bCounter_CCA 0xffff ++#define bCounter_ParityFail 0xffff0000 ++#define bCounter_RateIllegal 0xffff ++#define bCounter_CRC8Fail 0xffff0000 ++#define bCounter_MCSNoSupport 0xffff ++#define bCounter_FastSync 0xffff ++#define bShortCFO 0xfff ++#define bShortCFOTLength 12 //total ++#define bShortCFOFLength 11 //fraction ++#define bLongCFO 0x7ff ++#define bLongCFOTLength 11 ++#define bLongCFOFLength 11 ++#define bTailCFO 0x1fff ++#define bTailCFOTLength 13 ++#define bTailCFOFLength 12 ++#define bmax_en_pwdB 0xffff ++#define bCC_power_dB 0xffff0000 ++#define bnoise_pwdB 0xffff ++#define bPowerMeasTLength 10 ++#define bPowerMeasFLength 3 ++#define bRx_HT_BW 0x1 ++#define bRxSC 0x6 ++#define bRx_HT 0x8 ++#define bNB_intf_det_on 0x1 ++#define bIntf_win_len_cfg 0x30 ++#define bNB_Intf_TH_cfg 0x1c0 ++#define bRFGain 0x3f ++#define bTableSel 0x40 ++#define bTRSW 0x80 ++#define bRxSNR_A 0xff ++#define bRxSNR_B 0xff00 ++#define bRxSNR_C 0xff0000 ++#define bRxSNR_D 0xff000000 ++#define bSNREVMTLength 8 ++#define bSNREVMFLength 1 ++#define bCSI1st 0xff ++#define bCSI2nd 0xff00 ++#define bRxEVM1st 0xff0000 ++#define bRxEVM2nd 0xff000000 ++#define bSIGEVM 0xff ++#define bPWDB 0xff00 ++#define bSGIEN 0x10000 ++ ++#define bSFactorQAM1 0xf // Useless ++#define bSFactorQAM2 0xf0 ++#define bSFactorQAM3 0xf00 ++#define bSFactorQAM4 0xf000 ++#define bSFactorQAM5 0xf0000 ++#define bSFactorQAM6 0xf0000 ++#define bSFactorQAM7 0xf00000 ++#define bSFactorQAM8 0xf000000 ++#define bSFactorQAM9 0xf0000000 ++#define bCSIScheme 0x100000 ++ ++#define bNoiseLvlTopSet 0x3 // Useless ++#define bChSmooth 0x4 ++#define bChSmoothCfg1 0x38 ++#define bChSmoothCfg2 0x1c0 ++#define bChSmoothCfg3 0xe00 ++#define bChSmoothCfg4 0x7000 ++#define bMRCMode 0x800000 ++#define bTHEVMCfg 0x7000000 ++ ++#define bLoopFitType 0x1 // Useless ++#define bUpdCFO 0x40 ++#define bUpdCFOOffData 0x80 ++#define bAdvUpdCFO 0x100 ++#define bAdvTimeCtrl 0x800 ++#define bUpdClko 0x1000 ++#define bFC 0x6000 ++#define bTrackingMode 0x8000 ++#define bPhCmpEnable 0x10000 ++#define bUpdClkoLTF 0x20000 ++#define bComChCFO 0x40000 ++#define bCSIEstiMode 0x80000 ++#define bAdvUpdEqz 0x100000 ++#define bUChCfg 0x7000000 ++#define bUpdEqz 0x8000000 ++ ++//Rx Pseduo noise ++#define bRxPesudoNoiseOn 0x20000000 // Useless ++#define bRxPesudoNoise_A 0xff ++#define bRxPesudoNoise_B 0xff00 ++#define bRxPesudoNoise_C 0xff0000 ++#define bRxPesudoNoise_D 0xff000000 ++#define bPesudoNoiseState_A 0xffff ++#define bPesudoNoiseState_B 0xffff0000 ++#define bPesudoNoiseState_C 0xffff ++#define bPesudoNoiseState_D 0xffff0000 ++ ++//7. RF Register ++//Zebra1 ++#define bZebra1_HSSIEnable 0x8 // Useless ++#define bZebra1_TRxControl 0xc00 ++#define bZebra1_TRxGainSetting 0x07f ++#define bZebra1_RxCorner 0xc00 ++#define bZebra1_TxChargePump 0x38 ++#define bZebra1_RxChargePump 0x7 ++#define bZebra1_ChannelNum 0xf80 ++#define bZebra1_TxLPFBW 0x400 ++#define bZebra1_RxLPFBW 0x600 ++ ++//Zebra4 ++#define bRTL8256RegModeCtrl1 0x100 // Useless ++#define bRTL8256RegModeCtrl0 0x40 ++#define bRTL8256_TxLPFBW 0x18 ++#define bRTL8256_RxLPFBW 0x600 ++ ++//RTL8258 ++#define bRTL8258_TxLPFBW 0xc // Useless ++#define bRTL8258_RxLPFBW 0xc00 ++#define bRTL8258_RSSILPFBW 0xc0 ++ ++ ++// ++// Other Definition ++// ++ ++//byte endable for sb_write ++#define bByte0 0x1 // Useless ++#define bByte1 0x2 ++#define bByte2 0x4 ++#define bByte3 0x8 ++#define bWord0 0x3 ++#define bWord1 0xc ++#define bDWord 0xf ++ ++//for PutRegsetting & GetRegSetting BitMask ++#define bMaskByte0 0xff // Reg 0xc50 rOFDM0_XAAGCCore~0xC6f ++#define bMaskByte1 0xff00 ++#define bMaskByte2 0xff0000 ++#define bMaskByte3 0xff000000 ++#define bMaskHWord 0xffff0000 ++#define bMaskLWord 0x0000ffff ++#define bMaskDWord 0xffffffff ++#define bMask12Bits 0xfff ++#define bMaskH4Bits 0xf0000000 ++#define bMaskOFDM_D 0xffc00000 ++#define bMaskCCK 0x3f3f3f3f ++ ++//for PutRFRegsetting & GetRFRegSetting BitMask ++//#define bMask12Bits 0xfffff // RF Reg mask bits ++//#define bMask20Bits 0xfffff // RF Reg mask bits T65 RF ++#define bRFRegOffsetMask 0xfffff ++ ++#define bEnable 0x1 // Useless ++#define bDisable 0x0 ++ ++#define LeftAntenna 0x0 // Useless ++#define RightAntenna 0x1 ++ ++#define tCheckTxStatus 500 //500ms // Useless ++#define tUpdateRxCounter 100 //100ms ++ ++#define rateCCK 0 // Useless ++#define rateOFDM 1 ++#define rateHT 2 ++ ++//define Register-End ++#define bPMAC_End 0x1ff // Useless ++#define bFPGAPHY0_End 0x8ff ++#define bFPGAPHY1_End 0x9ff ++#define bCCKPHY0_End 0xaff ++#define bOFDMPHY0_End 0xcff ++#define bOFDMPHY1_End 0xdff ++ ++//define max debug item in each debug page ++//#define bMaxItem_FPGA_PHY0 0x9 ++//#define bMaxItem_FPGA_PHY1 0x3 ++//#define bMaxItem_PHY_11B 0x16 ++//#define bMaxItem_OFDM_PHY0 0x29 ++//#define bMaxItem_OFDM_PHY1 0x0 ++ ++#define bPMACControl 0x0 // Useless ++#define bWMACControl 0x1 ++#define bWNICControl 0x2 ++ ++#define PathA 0x0 // Useless ++#define PathB 0x1 ++#define PathC 0x2 ++#define PathD 0x3 ++ ++/*--------------------------Define Parameters-------------------------------*/ ++ ++ ++#endif //__INC_HAL8192SPHYREG_H ++ +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/include/Hal8192CUHWImg.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/include/Hal8192CUHWImg.h 2013-07-26 19:36:06.000000000 +0000 +@@ -0,0 +1,99 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef __INC_HAL8192CU_FW_IMG_H ++#define __INC_HAL8192CU_FW_IMG_H ++ ++/*Created on 2011/12/14, 8:38*/ ++ ++#ifdef CONFIG_BT_COEXISTENCE ++#define TSMCImgArrayLength 16248 //v79 TSMC COMMON 2011-10-06 ++#else ++#define TSMCImgArrayLength 16116 //v80 TSMC P2PPS 2011-12-14 ++#endif ++extern u8 Rtl8192CUFwTSMCImgArray[TSMCImgArrayLength]; ++ ++#ifdef CONFIG_BT_COEXISTENCE ++#define UMCACutImgArrayLength 16248 //v79 UMC A Cut COMMON 2011-10-06 ++#else //#ifdef CONFIG_P2P ++#define UMCACutImgArrayLength 16116 //v80 UMC A Cut P2PPS 2011-12-14 ++#endif ++extern u8 Rtl8192CUFwUMCACutImgArray[UMCACutImgArrayLength]; ++ ++#ifdef CONFIG_BT_COEXISTENCE ++#define UMCBCutImgArrayLength 16254 //v79 UMC B Cut COMMON 2011-10-06 ++#else //#ifdef CONFIG_P2P ++#define UMCBCutImgArrayLength 16096 //v80 UMC B Cut P2PPS 2011-12-14 ++#endif ++extern u8 Rtl8192CUFwUMCBCutImgArray[UMCBCutImgArrayLength]; ++ ++#define UMC8723ImgArrayLength 16288 ++extern u8 Rtl8192CUFwUMC8723ImgArray[UMC8723ImgArrayLength]; ++#define PHY_REG_2TArrayLength 374 ++extern u32 Rtl8192CUPHY_REG_2TArray[PHY_REG_2TArrayLength]; ++#define PHY_REG_1TArrayLength 374 ++extern u32 Rtl8192CUPHY_REG_1TArray[PHY_REG_1TArrayLength]; ++#define PHY_ChangeTo_1T1RArrayLength 1 ++extern u32 Rtl8192CUPHY_ChangeTo_1T1RArray[PHY_ChangeTo_1T1RArrayLength]; ++#define PHY_ChangeTo_1T2RArrayLength 1 ++extern u32 Rtl8192CUPHY_ChangeTo_1T2RArray[PHY_ChangeTo_1T2RArrayLength]; ++#define PHY_ChangeTo_2T2RArrayLength 1 ++extern u32 Rtl8192CUPHY_ChangeTo_2T2RArray[PHY_ChangeTo_2T2RArrayLength]; ++#define PHY_REG_Array_PGLength 336 ++extern u32 Rtl8192CUPHY_REG_Array_PG[PHY_REG_Array_PGLength]; ++#define PHY_REG_Array_PG_mCardLength 336 ++extern u32 Rtl8192CUPHY_REG_Array_PG_mCard[PHY_REG_Array_PG_mCardLength]; ++#define PHY_REG_Array_MPLength 4 ++extern u32 Rtl8192CUPHY_REG_Array_MP[PHY_REG_Array_MPLength]; ++#define PHY_REG_1T_HPArrayLength 378 ++extern u32 Rtl8192CUPHY_REG_1T_HPArray[PHY_REG_1T_HPArrayLength]; ++#define PHY_REG_1T_mCardArrayLength 374 ++extern u32 Rtl8192CUPHY_REG_1T_mCardArray[PHY_REG_1T_mCardArrayLength]; ++#define PHY_REG_2T_mCardArrayLength 374 ++extern u32 Rtl8192CUPHY_REG_2T_mCardArray[PHY_REG_2T_mCardArrayLength]; ++#define PHY_REG_Array_PG_HPLength 336 ++extern u32 Rtl8192CUPHY_REG_Array_PG_HP[PHY_REG_Array_PG_HPLength]; ++#define RadioA_2TArrayLength 282 ++extern u32 Rtl8192CURadioA_2TArray[RadioA_2TArrayLength]; ++#define RadioB_2TArrayLength 78 ++extern u32 Rtl8192CURadioB_2TArray[RadioB_2TArrayLength]; ++#define RadioA_1TArrayLength 282 ++extern u32 Rtl8192CURadioA_1TArray[RadioA_1TArrayLength]; ++#define RadioB_1TArrayLength 1 ++extern u32 Rtl8192CURadioB_1TArray[RadioB_1TArrayLength]; ++#define RadioA_1T_mCardArrayLength 282 ++extern u32 Rtl8192CURadioA_1T_mCardArray[RadioA_1T_mCardArrayLength]; ++#define RadioB_1T_mCardArrayLength 1 ++extern u32 Rtl8192CURadioB_1T_mCardArray[RadioB_1T_mCardArrayLength]; ++#define RadioA_1T_HPArrayLength 282 ++extern u32 Rtl8192CURadioA_1T_HPArray[RadioA_1T_HPArrayLength]; ++#define RadioB_GM_ArrayLength 1 ++extern u32 Rtl8192CURadioB_GM_Array[RadioB_GM_ArrayLength]; ++#define MAC_2T_ArrayLength 172 ++extern u32 Rtl8192CUMAC_2T_Array[MAC_2T_ArrayLength]; ++#define MACPHY_Array_PGLength 1 ++extern u32 Rtl8192CUMACPHY_Array_PG[MACPHY_Array_PGLength]; ++#define AGCTAB_2TArrayLength 320 ++extern u32 Rtl8192CUAGCTAB_2TArray[AGCTAB_2TArrayLength]; ++#define AGCTAB_1TArrayLength 320 ++extern u32 Rtl8192CUAGCTAB_1TArray[AGCTAB_1TArrayLength]; ++#define AGCTAB_1T_HPArrayLength 320 ++extern u32 Rtl8192CUAGCTAB_1T_HPArray[AGCTAB_1T_HPArrayLength]; ++ ++#endif //__INC_HAL8192CU_FW_IMG_H +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/include/Hal8192CUHWImg_wowlan.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/include/Hal8192CUHWImg_wowlan.h 2013-07-26 19:36:06.000000000 +0000 +@@ -0,0 +1,34 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef __INC_HAL8192CU_FW_IMG_WOWLAN_H ++#define __INC_HAL8192CU_FW_IMG_WOWLAN_H ++ ++/*Created on 2011/11/ 8, 14:15*/ ++ ++ ++#define TSMCWWImgArrayLength 13458 ++extern u8 Rtl8192CUFwTSMCWWImgArray[TSMCWWImgArrayLength]; ++#define UMCACutWWImgArrayLength 13458 ++extern u8 Rtl8192CUFwUMCACutWWImgArray[UMCACutWWImgArrayLength]; ++#define UMCBCutWWImgArrayLength 13446 ++extern u8 Rtl8192CUFwUMCBCutWWImgArray[UMCBCutWWImgArrayLength]; ++ ++#endif //__INC_HAL8192CU_FW_IMG_WOWLAN_H ++ +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/include/Hal8192DEHWImg.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/include/Hal8192DEHWImg.h 2013-07-26 19:36:06.000000000 +0000 +@@ -0,0 +1,66 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef __INC_HAL8192DU_FW_IMG_H ++#define __INC_HAL8192DU_FW_IMG_H ++ ++#include ++ ++/*Created on 2011/ 8/ 8, 1:41*/ ++ ++#define ImgArrayLength 29642 ++extern u8 Rtl8192DEFwImgArray[ImgArrayLength]; ++#define MainArrayLength 1 ++extern u8 Rtl8192DEFwMainArray[MainArrayLength]; ++#define DataArrayLength 1 ++extern u8 Rtl8192DEFwDataArray[DataArrayLength]; ++#define PHY_REG_2TArrayLength 380 ++extern u32 Rtl8192DEPHY_REG_2TArray[PHY_REG_2TArrayLength]; ++#define PHY_REG_1TArrayLength 1 ++extern u32 Rtl8192DEPHY_REG_1TArray[PHY_REG_1TArrayLength]; ++#define PHY_REG_Array_PGLength 624 ++extern u32 Rtl8192DEPHY_REG_Array_PG[PHY_REG_Array_PGLength]; ++#define PHY_REG_Array_MPLength 10 ++extern u32 Rtl8192DEPHY_REG_Array_MP[PHY_REG_Array_MPLength]; ++#define RadioA_2TArrayLength 378 ++extern u32 Rtl8192DERadioA_2TArray[RadioA_2TArrayLength]; ++#define RadioB_2TArrayLength 384 ++extern u32 Rtl8192DERadioB_2TArray[RadioB_2TArrayLength]; ++#define RadioA_1TArrayLength 1 ++extern u32 Rtl8192DERadioA_1TArray[RadioA_1TArrayLength]; ++#define RadioB_1TArrayLength 1 ++extern u32 Rtl8192DERadioB_1TArray[RadioB_1TArrayLength]; ++#define RadioA_2T_intPAArrayLength 378 ++extern u32 Rtl8192DERadioA_2T_intPAArray[RadioA_2T_intPAArrayLength]; ++#define RadioB_2T_intPAArrayLength 384 ++extern u32 Rtl8192DERadioB_2T_intPAArray[RadioB_2T_intPAArrayLength]; ++#define MAC_2TArrayLength 160 ++extern u32 Rtl8192DEMAC_2TArray[MAC_2TArrayLength]; ++#define AGCTAB_ArrayLength 386 ++extern u32 Rtl8192DEAGCTAB_Array[AGCTAB_ArrayLength]; ++#define AGCTAB_5GArrayLength 194 ++extern u32 Rtl8192DEAGCTAB_5GArray[AGCTAB_5GArrayLength]; ++#define AGCTAB_2GArrayLength 194 ++extern u32 Rtl8192DEAGCTAB_2GArray[AGCTAB_2GArrayLength]; ++#define AGCTAB_2TArrayLength 1 ++extern u32 Rtl8192DEAGCTAB_2TArray[AGCTAB_2TArrayLength]; ++#define AGCTAB_1TArrayLength 1 ++extern u32 Rtl8192DEAGCTAB_1TArray[AGCTAB_1TArrayLength]; ++ ++#endif //__INC_HAL8192CU_FW_IMG_H +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/include/Hal8192DETestHWImg.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/include/Hal8192DETestHWImg.h 2013-07-26 19:36:06.000000000 +0000 +@@ -0,0 +1,54 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef __INC_HAL8192DETEST_FW_IMG_H ++#define __INC_HAL8192DETEST_FW_IMG_H ++ ++#include ++ ++/*Created on 2010/ 5/27, 8: 6*/ ++ ++#define Rtl8192DTestImgArrayLength 15054 ++extern u8 Rtl8192DTestFwImgArray[Rtl8192DTestImgArrayLength]; ++#define Rtl8192DTestMainArrayLength 1 ++extern u8 Rtl8192DTestFwMainArray[Rtl8192DTestMainArrayLength]; ++#define Rtl8192DTestDataArrayLength 1 ++extern u8 Rtl8192DTestFwDataArray[Rtl8192DTestDataArrayLength]; ++#define Rtl8192DTestPHY_REG_2TArrayLength 376 ++extern u32 Rtl8192DTestPHY_REG_2TArray[Rtl8192DTestPHY_REG_2TArrayLength]; ++#define Rtl8192DTestPHY_REG_1TArrayLength 1 ++extern u32 Rtl8192DTestPHY_REG_1TArray[Rtl8192DTestPHY_REG_1TArrayLength]; ++#define Rtl8192DTestPHY_REG_Array_PGLength 1 ++extern u32 Rtl8192DTestPHY_REG_Array_PG[Rtl8192DTestPHY_REG_Array_PGLength]; ++#define Rtl8192DTestRadioA_2TArrayLength 340 ++extern u32 Rtl8192DTestRadioA_2TArray[Rtl8192DTestRadioA_2TArrayLength]; ++#define Rtl8192DTestRadioB_2TArrayLength 340 ++extern u32 Rtl8192DTestRadioB_2TArray[Rtl8192DTestRadioB_2TArrayLength]; ++#define Rtl8192DTestRadioA_1TArrayLength 1 ++extern u32 Rtl8192DTestRadioA_1TArray[Rtl8192DTestRadioA_1TArrayLength]; ++#define Rtl8192DTestRadioB_1TArrayLength 1 ++extern u32 Rtl8192DTestRadioB_1TArray[Rtl8192DTestRadioB_1TArrayLength]; ++#define Rtl8192DTestMAC_2TArrayLength 174 ++extern u32 Rtl8192DTestMAC_2TArray[Rtl8192DTestMAC_2TArrayLength]; ++#define Rtl8192DTestAGCTAB_5GArrayLength 514 ++extern u32 Rtl8192DTestAGCTAB_5GArray[Rtl8192DTestAGCTAB_5GArrayLength]; ++#define Rtl8192DTestAGCTAB_2GArrayLength 514 ++extern u32 Rtl8192DTestAGCTAB_2GArray[Rtl8192DTestAGCTAB_2GArrayLength]; ++ ++#endif //__INC_HAL8192CU_FW_IMG_H +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/include/Hal8192DPhyCfg.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/include/Hal8192DPhyCfg.h 2013-07-26 19:36:06.000000000 +0000 +@@ -0,0 +1,528 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++/***************************************************************************** ++ * ++ * Module: __INC_HAL8192DPHYCFG_H ++ * ++ * ++ * Note: ++ * ++ * ++ * Export: Constants, macro, functions(API), global variables(None). ++ * ++ * Abbrev: ++ * ++ * History: ++ * Data Who Remark ++ * 08/07/2007 MHC 1. Porting from 9x series PHYCFG.h. ++ * 2. Reorganize code architecture. ++ * ++ *****************************************************************************/ ++ /* Check to see if the file has been included already. */ ++#ifndef __INC_HAL8192DPHYCFG_H ++#define __INC_HAL8192DPHYCFG_H ++ ++ ++/*--------------------------Define Parameters-------------------------------*/ ++#define LOOP_LIMIT 5 ++#define MAX_STALL_TIME 50 //us ++#define AntennaDiversityValue 0x80 //(Adapter->bSoftwareAntennaDiversity ? 0x00:0x80) ++#define MAX_TXPWR_IDX_NMODE_92S 63 ++#define Reset_Cnt_Limit 3 ++ ++ ++#define IQK_MAC_REG_NUM 4 ++#define IQK_ADDA_REG_NUM 16 ++#define IQK_BB_REG_NUM 10 ++#define IQK_BB_REG_NUM_92C 9 ++#define IQK_BB_REG_NUM_92D 10 ++#define IQK_BB_REG_NUM_test 6 ++#define index_mapping_NUM 13 ++#define Rx_index_mapping_NUM 15 ++#define AVG_THERMAL_NUM 8 ++#define IQK_Matrix_REG_NUM 8 ++#define IQK_Matrix_Settings_NUM 1+24+21 ++ ++#ifdef CONFIG_PCI_HCI ++#define SET_RTL8192SE_RF_SLEEP(_pAdapter) \ ++{ \ ++ u1Byte u1bTmp; \ ++ u1bTmp = PlatformEFIORead1Byte(_pAdapter, REG_LDOV12D_CTRL); \ ++ u1bTmp |= BIT0; \ ++ PlatformEFIOWrite1Byte(_pAdapter, REG_LDOV12D_CTRL, u1bTmp); \ ++ PlatformEFIOWrite1Byte(_pAdapter, REG_SPS_OCP_CFG, 0x0); \ ++ PlatformEFIOWrite1Byte(_pAdapter, TXPAUSE, 0xFF); \ ++ PlatformEFIOWrite2Byte(_pAdapter, CMDR, 0x57FC); \ ++ delay_us(100); \ ++ PlatformEFIOWrite2Byte(_pAdapter, CMDR, 0x77FC); \ ++ PlatformEFIOWrite1Byte(_pAdapter, PHY_CCA, 0x0); \ ++ delay_us(10); \ ++ PlatformEFIOWrite2Byte(_pAdapter, CMDR, 0x37FC); \ ++ delay_us(10); \ ++ PlatformEFIOWrite2Byte(_pAdapter, CMDR, 0x77FC); \ ++ delay_us(10); \ ++ PlatformEFIOWrite2Byte(_pAdapter, CMDR, 0x57FC); \ ++} ++#endif ++ ++ ++/*--------------------------Define Parameters-------------------------------*/ ++ ++ ++/*------------------------------Define structure----------------------------*/ ++typedef enum _SwChnlCmdID{ ++ CmdID_End, ++ CmdID_SetTxPowerLevel, ++ CmdID_BBRegWrite10, ++ CmdID_WritePortUlong, ++ CmdID_WritePortUshort, ++ CmdID_WritePortUchar, ++ CmdID_RF_WriteReg, ++}SwChnlCmdID; ++ ++ ++/* 1. Switch channel related */ ++typedef struct _SwChnlCmd{ ++ SwChnlCmdID CmdID; ++ u32 Para1; ++ u32 Para2; ++ u32 msDelay; ++}SwChnlCmd; ++ ++typedef enum _HW90_BLOCK{ ++ HW90_BLOCK_MAC = 0, ++ HW90_BLOCK_PHY0 = 1, ++ HW90_BLOCK_PHY1 = 2, ++ HW90_BLOCK_RF = 3, ++ HW90_BLOCK_MAXIMUM = 4, // Never use this ++}HW90_BLOCK_E, *PHW90_BLOCK_E; ++ ++//vivi added this for read parameter from header, 20100908 ++typedef enum _RF_CONTENT{ ++ radioa_txt = 0x1000, ++ radiob_txt = 0x1001, ++ radioc_txt = 0x1002, ++ radiod_txt = 0x1003 ++} RF_CONTENT; ++ ++#define RF_PATH_MAX 2 ++ ++typedef enum _WIRELESS_MODE { ++ WIRELESS_MODE_UNKNOWN = 0x00, ++ WIRELESS_MODE_A = 0x01, ++ WIRELESS_MODE_B = 0x02, ++ WIRELESS_MODE_G = 0x04, ++ WIRELESS_MODE_AUTO = 0x08, ++ WIRELESS_MODE_N_24G = 0x10, ++ WIRELESS_MODE_N_5G = 0x20 ++} WIRELESS_MODE; ++ ++ ++#define CHANNEL_MAX_NUMBER 14+24+21 // 14 is the max channel number ++#define CHANNEL_GROUP_MAX 3+9 // ch1~3, ch4~9, ch10~14 total three groups ++#define MAX_PG_GROUP 13 ++ ++#define CHANNEL_GROUP_MAX_2G 3 ++#define CHANNEL_GROUP_IDX_5GL 3 ++#define CHANNEL_GROUP_IDX_5GM 6 ++#define CHANNEL_GROUP_IDX_5GH 9 ++#define CHANNEL_GROUP_MAX_5G 9 ++#define CHANNEL_MAX_NUMBER_2G 14 ++ ++typedef enum _BaseBand_Config_Type{ ++ BaseBand_Config_PHY_REG = 0, //Radio Path A ++ BaseBand_Config_AGC_TAB = 1, //Radio Path B ++}BaseBand_Config_Type, *PBaseBand_Config_Type; ++ ++typedef enum _MACPHY_MODE_8192D{ ++ SINGLEMAC_SINGLEPHY, ++ DUALMAC_DUALPHY, ++ DUALMAC_SINGLEPHY, ++}MACPHY_MODE_8192D,*PMACPHY_MODE_8192D; ++ ++typedef enum _BAND_TYPE{ ++ BAND_ON_2_4G = 0, ++ BAND_ON_5G, ++ BAND_ON_BOTH, ++ BANDMAX ++}BAND_TYPE,*PBAND_TYPE; ++ ++typedef enum _PHY_Rate_Tx_Power_Offset_Area{ ++ RA_OFFSET_LEGACY_OFDM1, ++ RA_OFFSET_LEGACY_OFDM2, ++ RA_OFFSET_HT_OFDM1, ++ RA_OFFSET_HT_OFDM2, ++ RA_OFFSET_HT_OFDM3, ++ RA_OFFSET_HT_OFDM4, ++ RA_OFFSET_HT_CCK, ++}RA_OFFSET_AREA,*PRA_OFFSET_AREA; ++ ++ ++/* BB/RF related */ ++typedef enum _RF_TYPE_8190P{ ++ RF_TYPE_MIN, // 0 ++ RF_8225=1, // 1 11b/g RF for verification only ++ RF_8256=2, // 2 11b/g/n ++ RF_8258=3, // 3 11a/b/g/n RF ++ RF_6052=4, // 4 11b/g/n RF ++ //RF_6052=5, // 4 11b/g/n RF ++ // TODO: We sholud remove this psudo PHY RF after we get new RF. ++ RF_PSEUDO_11N=5, // 5, It is a temporality RF. ++}RF_TYPE_8190P_E,*PRF_TYPE_8190P_E; ++ ++ ++typedef enum _RATR_TABLE_MODE_8192C{ ++ RATR_INX_WIRELESS_NGB = 0, ++ RATR_INX_WIRELESS_NG = 1, ++ RATR_INX_WIRELESS_NB = 2, ++ RATR_INX_WIRELESS_N = 3, ++ RATR_INX_WIRELESS_GB = 4, ++ RATR_INX_WIRELESS_G = 5, ++ RATR_INX_WIRELESS_B = 6, ++ RATR_INX_WIRELESS_MC = 7, ++ RATR_INX_WIRELESS_A = 8, ++}RATR_TABLE_MODE_8192C, *PRATR_TABLE_MODE_8192C; ++ ++typedef struct _BB_REGISTER_DEFINITION{ ++ u32 rfintfs; // set software control: ++ // 0x870~0x877[8 bytes] ++ ++ u32 rfintfi; // readback data: ++ // 0x8e0~0x8e7[8 bytes] ++ ++ u32 rfintfo; // output data: ++ // 0x860~0x86f [16 bytes] ++ ++ u32 rfintfe; // output enable: ++ // 0x860~0x86f [16 bytes] ++ ++ u32 rf3wireOffset; // LSSI data: ++ // 0x840~0x84f [16 bytes] ++ ++ u32 rfLSSI_Select; // BB Band Select: ++ // 0x878~0x87f [8 bytes] ++ ++ u32 rfTxGainStage; // Tx gain stage: ++ // 0x80c~0x80f [4 bytes] ++ ++ u32 rfHSSIPara1; // wire parameter control1 : ++ // 0x820~0x823,0x828~0x82b, 0x830~0x833, 0x838~0x83b [16 bytes] ++ ++ u32 rfHSSIPara2; // wire parameter control2 : ++ // 0x824~0x827,0x82c~0x82f, 0x834~0x837, 0x83c~0x83f [16 bytes] ++ ++ u32 rfSwitchControl; //Tx Rx antenna control : ++ // 0x858~0x85f [16 bytes] ++ ++ u32 rfAGCControl1; //AGC parameter control1 : ++ // 0xc50~0xc53,0xc58~0xc5b, 0xc60~0xc63, 0xc68~0xc6b [16 bytes] ++ ++ u32 rfAGCControl2; //AGC parameter control2 : ++ // 0xc54~0xc57,0xc5c~0xc5f, 0xc64~0xc67, 0xc6c~0xc6f [16 bytes] ++ ++ u32 rfRxIQImbalance; //OFDM Rx IQ imbalance matrix : ++ // 0xc14~0xc17,0xc1c~0xc1f, 0xc24~0xc27, 0xc2c~0xc2f [16 bytes] ++ ++ u32 rfRxAFE; //Rx IQ DC ofset and Rx digital filter, Rx DC notch filter : ++ // 0xc10~0xc13,0xc18~0xc1b, 0xc20~0xc23, 0xc28~0xc2b [16 bytes] ++ ++ u32 rfTxIQImbalance; //OFDM Tx IQ imbalance matrix ++ // 0xc80~0xc83,0xc88~0xc8b, 0xc90~0xc93, 0xc98~0xc9b [16 bytes] ++ ++ u32 rfTxAFE; //Tx IQ DC Offset and Tx DFIR type ++ // 0xc84~0xc87,0xc8c~0xc8f, 0xc94~0xc97, 0xc9c~0xc9f [16 bytes] ++ ++ u32 rfLSSIReadBack; //LSSI RF readback data SI mode ++ // 0x8a0~0x8af [16 bytes] ++ ++ u32 rfLSSIReadBackPi; //LSSI RF readback data PI mode 0x8b8-8bc for Path A and B ++ ++}BB_REGISTER_DEFINITION_T, *PBB_REGISTER_DEFINITION_T; ++ ++#ifdef CONFIG_MP_INCLUDED ++typedef enum _ANTENNA_PATH{ ++ ANTENNA_NONE = 0x00, ++ ANTENNA_D , ++ ANTENNA_C , ++ ANTENNA_CD , ++ ANTENNA_B , ++ ANTENNA_BD , ++ ANTENNA_BC , ++ ANTENNA_BCD , ++ ANTENNA_A , ++ ANTENNA_AD , ++ ANTENNA_AC , ++ ANTENNA_ACD , ++ ANTENNA_AB , ++ ANTENNA_ABD , ++ ANTENNA_ABC , ++ ANTENNA_ABCD ++} ANTENNA_PATH; ++#endif ++ ++typedef struct _R_ANTENNA_SELECT_OFDM{ ++ u32 r_tx_antenna:4; ++ u32 r_ant_l:4; ++ u32 r_ant_non_ht:4; ++ u32 r_ant_ht1:4; ++ u32 r_ant_ht2:4; ++ u32 r_ant_ht_s1:4; ++ u32 r_ant_non_ht_s1:4; ++ u32 OFDM_TXSC:2; ++ u32 Reserved:2; ++}R_ANTENNA_SELECT_OFDM; ++ ++typedef struct _R_ANTENNA_SELECT_CCK{ ++ u8 r_cckrx_enable_2:2; ++ u8 r_cckrx_enable:2; ++ u8 r_ccktx_enable:4; ++}R_ANTENNA_SELECT_CCK; ++ ++/*------------------------------Define structure----------------------------*/ ++ ++ ++/*------------------------Export global variable----------------------------*/ ++/*------------------------Export global variable----------------------------*/ ++ ++ ++/*------------------------Export Marco Definition---------------------------*/ ++/*------------------------Export Marco Definition---------------------------*/ ++ ++//Added for TX Power ++//u8 GetRightChnlPlace(u8 chnl); ++u8 rtl8192d_GetRightChnlPlaceforIQK(u8 chnl); ++u8 rtl8192d_getChnlGroupfromArray(u8 chnl); ++/*--------------------------Exported Function prototype---------------------*/ ++// ++// BB and RF register read/write ++// ++void rtl8192d_PHY_SetBBReg1Byte( IN PADAPTER Adapter, ++ IN u32 RegAddr, ++ IN u32 BitMask, ++ IN u32 Data ); ++u32 rtl8192d_PHY_QueryBBReg( IN PADAPTER Adapter, ++ IN u32 RegAddr, ++ IN u32 BitMask ); ++void rtl8192d_PHY_SetBBReg( IN PADAPTER Adapter, ++ IN u32 RegAddr, ++ IN u32 BitMask, ++ IN u32 Data ); ++u32 rtl8192d_PHY_QueryRFReg( IN PADAPTER Adapter, ++ IN RF_RADIO_PATH_E eRFPath, ++ IN u32 RegAddr, ++ IN u32 BitMask ); ++void rtl8192d_PHY_SetRFReg( IN PADAPTER Adapter, ++ IN RF_RADIO_PATH_E eRFPath, ++ IN u32 RegAddr, ++ IN u32 BitMask, ++ IN u32 Data ); ++ ++// ++// Initialization related function ++// ++/* MAC/BB/RF HAL config */ ++extern int PHY_MACConfig8192D( IN PADAPTER Adapter ); ++extern int PHY_BBConfig8192D( IN PADAPTER Adapter ); ++extern int PHY_RFConfig8192D( IN PADAPTER Adapter ); ++/* RF config */ ++int rtl8192d_PHY_ConfigRFWithParaFile( IN PADAPTER Adapter, ++ IN u8* pFileName, ++ IN RF_RADIO_PATH_E eRFPath); ++int rtl8192d_PHY_ConfigRFWithHeaderFile( IN PADAPTER Adapter, ++ IN RF_CONTENT Content, ++ IN RF_RADIO_PATH_E eRFPath); ++/* BB/RF readback check for making sure init OK */ ++int rtl8192d_PHY_CheckBBAndRFOK( IN PADAPTER Adapter, ++ IN HW90_BLOCK_E CheckBlock, ++ IN RF_RADIO_PATH_E eRFPath ); ++/* Read initi reg value for tx power setting. */ ++void rtl8192d_PHY_GetHWRegOriginalValue( IN PADAPTER Adapter ); ++ ++// ++// RF Power setting ++// ++//extern BOOLEAN PHY_SetRFPowerState(IN PADAPTER Adapter, ++// IN RT_RF_POWER_STATE eRFPowerState); ++ ++// ++// BB TX Power R/W ++// ++void PHY_GetTxPowerLevel8192D( IN PADAPTER Adapter, ++ OUT u32* powerlevel ); ++void PHY_SetTxPowerLevel8192D( IN PADAPTER Adapter, ++ IN u8 channel ); ++BOOLEAN PHY_UpdateTxPowerDbm8192D( IN PADAPTER Adapter, ++ IN int powerInDbm ); ++ ++// ++VOID ++PHY_ScanOperationBackup8192D(IN PADAPTER Adapter, ++ IN u8 Operation ); ++ ++// ++// Switch bandwidth for 8192S ++// ++//void PHY_SetBWModeCallback8192C( IN PRT_TIMER pTimer ); ++void PHY_SetBWMode8192D( IN PADAPTER pAdapter, ++ IN HT_CHANNEL_WIDTH ChnlWidth, ++ IN unsigned char Offset ); ++ ++// ++// Set FW CMD IO for 8192S. ++// ++//extern BOOLEAN HalSetIO8192C( IN PADAPTER Adapter, ++// IN IO_TYPE IOType); ++ ++// ++// Set A2 entry to fw for 8192S ++// ++extern void FillA2Entry8192C( IN PADAPTER Adapter, ++ IN u8 index, ++ IN u8* val); ++ ++ ++// ++// channel switch related funciton ++// ++//extern void PHY_SwChnlCallback8192C( IN PRT_TIMER pTimer ); ++void PHY_SwChnl8192D( IN PADAPTER pAdapter, ++ IN u8 channel ); ++ // Call after initialization ++void PHY_SwChnlPhy8192D( IN PADAPTER pAdapter, ++ IN u8 channel ); ++ ++extern void ChkFwCmdIoDone( IN PADAPTER Adapter); ++ ++#ifdef USE_WORKITEM ++//extern void SetIOWorkItemCallback( IN PVOID pContext ); ++#else ++//extern void SetIOTimerCallback( IN PRT_TIMER pTimer); ++#endif ++ ++// ++// BB/MAC/RF other monitor API ++// ++void PHY_SetMonitorMode8192D(IN PADAPTER pAdapter, ++ IN BOOLEAN bEnableMonitorMode ); ++ ++BOOLEAN PHY_CheckIsLegalRfPath8192D(IN PADAPTER pAdapter, ++ IN u32 eRFPath ); ++ ++// ++// IQ calibrate ++// ++void rtl8192d_PHY_IQCalibrate( IN PADAPTER pAdapter); ++ ++ ++// ++// LC calibrate ++// ++void rtl8192d_PHY_LCCalibrate(IN PADAPTER pAdapter); ++ ++// ++// AP calibrate ++// ++void rtl8192d_PHY_APCalibrate(IN PADAPTER pAdapter, IN char delta); ++ ++ ++// ++// Modify the value of the hw register when beacon interval be changed. ++// ++void ++rtl8192d_PHY_SetBeaconHwReg( IN PADAPTER Adapter, ++ IN u16 BeaconInterval ); ++ ++ ++extern VOID ++PHY_SwitchEphyParameter( ++ IN PADAPTER Adapter ++ ); ++ ++extern VOID ++PHY_EnableHostClkReq( ++ IN PADAPTER Adapter ++ ); ++ ++BOOLEAN ++SetAntennaConfig92C( ++ IN PADAPTER Adapter, ++ IN u8 DefaultAnt ++ ); ++ ++VOID ++PHY_StopTRXBeforeChangeBand8192D( ++ PADAPTER Adapter ++); ++ ++VOID ++PHY_UpdateBBRFConfiguration8192D( ++ IN PADAPTER Adapter, ++ IN BOOLEAN bisBandSwitch ++); ++ ++VOID PHY_ReadMacPhyMode92D( ++ IN PADAPTER Adapter, ++ IN BOOLEAN AutoloadFail ++); ++ ++VOID PHY_ConfigMacPhyMode92D( ++ IN PADAPTER Adapter ++); ++ ++VOID PHY_ConfigMacPhyModeInfo92D( ++ IN PADAPTER Adapter ++); ++ ++VOID PHY_ConfigMacCoexist_RFPage92D( ++ IN PADAPTER Adapter ++); ++ ++VOID ++rtl8192d_PHY_InitRxSetting( ++ IN PADAPTER Adapter ++); ++ ++VOID ++rtl8192d_PHY_ResetIQKResult( ++ IN PADAPTER Adapter ++); ++ ++ ++VOID ++rtl8192d_PHY_SetRFPathSwitch(IN PADAPTER pAdapter, IN BOOLEAN bMain); ++ ++VOID ++HalChangeCCKStatus8192D( ++ IN PADAPTER Adapter, ++ IN BOOLEAN bCCKDisable ++); ++ ++/*--------------------------Exported Function prototype---------------------*/ ++ ++#define PHY_SetBBReg1Byte(Adapter, RegAddr, BitMask, Data) rtl8192d_PHY_SetBBReg1Byte((Adapter), (RegAddr), (BitMask), (Data)) ++#define PHY_QueryBBReg(Adapter, RegAddr, BitMask) rtl8192d_PHY_QueryBBReg((Adapter), (RegAddr), (BitMask)) ++#define PHY_SetBBReg(Adapter, RegAddr, BitMask, Data) rtl8192d_PHY_SetBBReg((Adapter), (RegAddr), (BitMask), (Data)) ++#define PHY_QueryRFReg(Adapter, eRFPath, RegAddr, BitMask) rtl8192d_PHY_QueryRFReg((Adapter), (eRFPath), (RegAddr), (BitMask)) ++#define PHY_SetRFReg(Adapter, eRFPath, RegAddr, BitMask, Data) rtl8192d_PHY_SetRFReg((Adapter), (eRFPath), (RegAddr), (BitMask), (Data)) ++ ++#define PHY_SetMacReg PHY_SetBBReg ++ ++#endif // __INC_HAL8192SPHYCFG_H ++ +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/include/Hal8192DPhyReg.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/include/Hal8192DPhyReg.h 2013-07-26 19:36:06.000000000 +0000 +@@ -0,0 +1,1171 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++/***************************************************************************** ++ * ++ * Module: __INC_HAL8192DPHYREG_H ++ * ++ * ++ * Note: 1. Define PMAC/BB register map ++ * 2. Define RF register map ++ * 3. PMAC/BB register bit mask. ++ * 4. RF reg bit mask. ++ * 5. Other BB/RF relative definition. ++ * ++ * ++ * Export: Constants, macro, functions(API), global variables(None). ++ * ++ * Abbrev: ++ * ++ * History: ++ * Data Who Remark ++ * 08/07/2007 MHC 1. Porting from 9x series PHYCFG.h. ++ * 2. Reorganize code architecture. ++ * 09/25/2008 MH 1. Add RL6052 register definition ++ * ++ *****************************************************************************/ ++#ifndef __INC_HAL8192DPHYREG_H ++#define __INC_HAL8192DPHYREG_H ++ ++ ++/*--------------------------Define Parameters-------------------------------*/ ++ ++//============================================================ ++// 8192S Regsiter offset definition ++//============================================================ ++ ++// ++// BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF ++// 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF ++// 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00 ++// 3. RF register 0x00-2E ++// 4. Bit Mask for BB/RF register ++// 5. Other defintion for BB/RF R/W ++// ++ ++ ++// ++// 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF ++// 1. Page1(0x100) ++// ++#define rPMAC_Reset 0x100 ++#define rPMAC_TxStart 0x104 ++#define rPMAC_TxLegacySIG 0x108 ++#define rPMAC_TxHTSIG1 0x10c ++#define rPMAC_TxHTSIG2 0x110 ++#define rPMAC_PHYDebug 0x114 ++#define rPMAC_TxPacketNum 0x118 ++#define rPMAC_TxIdle 0x11c ++#define rPMAC_TxMACHeader0 0x120 ++#define rPMAC_TxMACHeader1 0x124 ++#define rPMAC_TxMACHeader2 0x128 ++#define rPMAC_TxMACHeader3 0x12c ++#define rPMAC_TxMACHeader4 0x130 ++#define rPMAC_TxMACHeader5 0x134 ++#define rPMAC_TxDataType 0x138 ++#define rPMAC_TxRandomSeed 0x13c ++#define rPMAC_CCKPLCPPreamble 0x140 ++#define rPMAC_CCKPLCPHeader 0x144 ++#define rPMAC_CCKCRC16 0x148 ++#define rPMAC_OFDMRxCRC32OK 0x170 ++#define rPMAC_OFDMRxCRC32Er 0x174 ++#define rPMAC_OFDMRxParityEr 0x178 ++#define rPMAC_OFDMRxCRC8Er 0x17c ++#define rPMAC_CCKCRxRC16Er 0x180 ++#define rPMAC_CCKCRxRC32Er 0x184 ++#define rPMAC_CCKCRxRC32OK 0x188 ++#define rPMAC_TxStatus 0x18c ++ ++// ++// 2. Page2(0x200) ++// ++// The following two definition are only used for USB interface. ++#define RF_BB_CMD_ADDR 0x02c0 // RF/BB read/write command address. ++#define RF_BB_CMD_DATA 0x02c4 // RF/BB read/write command data. ++ ++// ++// 3. Page8(0x800) ++// ++#define rFPGA0_RFMOD 0x800 //RF mode & CCK TxSC // RF BW Setting?? ++ ++#define rFPGA0_TxInfo 0x804 // Status report?? ++#define rFPGA0_PSDFunction 0x808 ++ ++#define rFPGA0_TxGainStage 0x80c // Set TX PWR init gain? ++ ++#define rFPGA0_RFTiming1 0x810 // Useless now ++#define rFPGA0_RFTiming2 0x814 ++ ++#define rFPGA0_XA_HSSIParameter1 0x820 // RF 3 wire register ++#define rFPGA0_XA_HSSIParameter2 0x824 ++#define rFPGA0_XB_HSSIParameter1 0x828 ++#define rFPGA0_XB_HSSIParameter2 0x82c ++ ++#define rFPGA0_XA_LSSIParameter 0x840 ++#define rFPGA0_XB_LSSIParameter 0x844 ++ ++#define rFPGA0_RFWakeUpParameter 0x850 // Useless now ++#define rFPGA0_RFSleepUpParameter 0x854 ++ ++#define rFPGA0_XAB_SwitchControl 0x858 // RF Channel switch ++#define rFPGA0_XCD_SwitchControl 0x85c ++ ++#define rFPGA0_XA_RFInterfaceOE 0x860 // RF Channel switch ++#define rFPGA0_XB_RFInterfaceOE 0x864 ++ ++#define rFPGA0_XAB_RFInterfaceSW 0x870 // RF Interface Software Control ++#define rFPGA0_XCD_RFInterfaceSW 0x874 ++ ++#define rFPGA0_XAB_RFParameter 0x878 // RF Parameter ++#define rFPGA0_XCD_RFParameter 0x87c ++ ++#define rFPGA0_AnalogParameter1 0x880 // Crystal cap setting RF-R/W protection for parameter4?? ++#define rFPGA0_AnalogParameter2 0x884 ++#define rFPGA0_AnalogParameter3 0x888 ++#define rFPGA0_AdDaClockEn 0x888 // enable ad/da clock1 for dual-phy ++#define rFPGA0_AnalogParameter4 0x88c ++ ++#define rFPGA0_XA_LSSIReadBack 0x8a0 // Tranceiver LSSI Readback ++#define rFPGA0_XB_LSSIReadBack 0x8a4 ++#define rFPGA0_XC_LSSIReadBack 0x8a8 ++#define rFPGA0_XD_LSSIReadBack 0x8ac ++ ++#define rFPGA0_PSDReport 0x8b4 // Useless now ++#define TransceiverA_HSPI_Readback 0x8b8 // Transceiver A HSPI Readback ++#define TransceiverB_HSPI_Readback 0x8bc // Transceiver B HSPI Readback ++#define rFPGA0_XAB_RFInterfaceRB 0x8e0 // Useless now // RF Interface Readback Value ++#define rFPGA0_XCD_RFInterfaceRB 0x8e4 // Useless now ++ ++// ++// 4. Page9(0x900) ++// ++#define rFPGA1_RFMOD 0x900 //RF mode & OFDM TxSC // RF BW Setting?? ++ ++#define rFPGA1_TxBlock 0x904 // Useless now ++#define rFPGA1_DebugSelect 0x908 // Useless now ++#define rFPGA1_TxInfo 0x90c // Useless now // Status report?? ++ ++// ++// 5. PageA(0xA00) ++// ++// Set Control channel to upper or lower. These settings are required only for 40MHz ++#define rCCK0_System 0xa00 ++ ++#define rCCK0_AFESetting 0xa04 // Disable init gain now // Select RX path by RSSI ++#define rCCK0_CCA 0xa08 // Disable init gain now // Init gain ++ ++#define rCCK0_RxAGC1 0xa0c //AGC default value, saturation level // Antenna Diversity, RX AGC, LNA Threshold, RX LNA Threshold useless now. Not the same as 90 series ++#define rCCK0_RxAGC2 0xa10 //AGC & DAGC ++ ++#define rCCK0_RxHP 0xa14 ++ ++#define rCCK0_DSPParameter1 0xa18 //Timing recovery & Channel estimation threshold ++#define rCCK0_DSPParameter2 0xa1c //SQ threshold ++ ++#define rCCK0_TxFilter1 0xa20 ++#define rCCK0_TxFilter2 0xa24 ++#define rCCK0_DebugPort 0xa28 //debug port and Tx filter3 ++#define rCCK0_FalseAlarmReport 0xa2c //0xa2d useless now 0xa30-a4f channel report ++#define rCCK0_TRSSIReport 0xa50 ++#define rCCK0_RxReport 0xa54 //0xa57 ++#define rCCK0_FACounterLower 0xa5c //0xa5b ++#define rCCK0_FACounterUpper 0xa58 //0xa5c ++ ++// ++// PageB(0xB00) ++// ++#define rPdp_AntA 0xb00 ++#define rPdp_AntA_4 0xb04 ++#define rPdp_AntA_8 0xb08 ++#define rPdp_AntA_C 0xb0c ++#define rPdp_AntA_10 0xb10 ++#define rPdp_AntA_14 0xb14 ++#define rPdp_AntA_18 0xb18 ++#define rPdp_AntA_1C 0xb1c ++#define rPdp_AntA_20 0xb20 ++#define rPdp_AntA_24 0xb24 ++ ++#define rConfig_Pmpd_AntA 0xb28 ++#define rConfig_ram64x16 0xb2c ++ ++#define rBndA 0xb30 ++#define rHssiPar 0xb34 ++ ++#define rConfig_AntA 0xb68 ++#define rConfig_AntB 0xb6c ++ ++#define rPdp_AntB 0xb70 ++#define rPdp_AntB_4 0xb74 ++#define rPdp_AntB_8 0xb78 ++#define rPdp_AntB_C 0xb7c ++#define rPdp_AntB_10 0xb80 ++#define rPdp_AntB_14 0xb84 ++#define rPdp_AntB_18 0xb88 ++#define rPdp_AntB_1C 0xb8c ++#define rPdp_AntB_20 0xb90 ++#define rPdp_AntB_24 0xb94 ++ ++#define rConfig_Pmpd_AntB 0xb98 ++ ++#define rBndB 0xba0 ++ ++#define rAPK 0xbd8 ++#define rPm_Rx0_AntA 0xbdc ++#define rPm_Rx1_AntA 0xbe0 ++#define rPm_Rx2_AntA 0xbe4 ++#define rPm_Rx3_AntA 0xbe8 ++#define rPm_Rx0_AntB 0xbec ++#define rPm_Rx1_AntB 0xbf0 ++#define rPm_Rx2_AntB 0xbf4 ++#define rPm_Rx3_AntB 0xbf8 ++ ++// ++// 6. PageC(0xC00) ++// ++#define rOFDM0_LSTF 0xc00 ++ ++#define rOFDM0_TRxPathEnable 0xc04 ++#define rOFDM0_TRMuxPar 0xc08 ++#define rOFDM0_TRSWIsolation 0xc0c ++ ++#define rOFDM0_XARxAFE 0xc10 //RxIQ DC offset, Rx digital filter, DC notch filter ++#define rOFDM0_XARxIQImbalance 0xc14 //RxIQ imblance matrix ++#define rOFDM0_XBRxAFE 0xc18 ++#define rOFDM0_XBRxIQImbalance 0xc1c ++#define rOFDM0_XCRxAFE 0xc20 ++#define rOFDM0_XCRxIQImbalance 0xc24 ++#define rOFDM0_XDRxAFE 0xc28 ++#define rOFDM0_XDRxIQImbalance 0xc2c ++ ++#define rOFDM0_RxDetector1 0xc30 //PD,BW & SBD // DM tune init gain ++#define rOFDM0_RxDetector2 0xc34 //SBD & Fame Sync. ++#define rOFDM0_RxDetector3 0xc38 //Frame Sync. ++#define rOFDM0_RxDetector4 0xc3c //PD, SBD, Frame Sync & Short-GI ++ ++#define rOFDM0_RxDSP 0xc40 //Rx Sync Path ++#define rOFDM0_CFOandDAGC 0xc44 //CFO & DAGC ++#define rOFDM0_CCADropThreshold 0xc48 //CCA Drop threshold ++#define rOFDM0_ECCAThreshold 0xc4c // energy CCA ++ ++#define rOFDM0_XAAGCCore1 0xc50 // DIG ++#define rOFDM0_XAAGCCore2 0xc54 ++#define rOFDM0_XBAGCCore1 0xc58 ++#define rOFDM0_XBAGCCore2 0xc5c ++#define rOFDM0_XCAGCCore1 0xc60 ++#define rOFDM0_XCAGCCore2 0xc64 ++#define rOFDM0_XDAGCCore1 0xc68 ++#define rOFDM0_XDAGCCore2 0xc6c ++ ++#define rOFDM0_AGCParameter1 0xc70 ++#define rOFDM0_AGCParameter2 0xc74 ++#define rOFDM0_AGCRSSITable 0xc78 ++#define rOFDM0_HTSTFAGC 0xc7c ++ ++#define rOFDM0_XATxIQImbalance 0xc80 // TX PWR TRACK and DIG ++#define rOFDM0_XATxAFE 0xc84 ++#define rOFDM0_XBTxIQImbalance 0xc88 ++#define rOFDM0_XBTxAFE 0xc8c ++#define rOFDM0_XCTxIQImbalance 0xc90 ++#define rOFDM0_XCTxAFE 0xc94 ++#define rOFDM0_XDTxIQImbalance 0xc98 ++#define rOFDM0_XDTxAFE 0xc9c ++ ++#define rOFDM0_RxIQExtAnta 0xca0 ++#define rOFDM0_TxCoeff1 0xca4 ++#define rOFDM0_TxCoeff2 0xca8 ++#define rOFDM0_TxCoeff3 0xcac ++#define rOFDM0_TxCoeff4 0xcb0 ++#define rOFDM0_TxCoeff5 0xcb4 ++#define rOFDM0_TxCoeff6 0xcb8 ++#define rOFDM0_RxHPParameter 0xce0 ++#define rOFDM0_TxPseudoNoiseWgt 0xce4 ++#define rOFDM0_FrameSync 0xcf0 ++#define rOFDM0_DFSReport 0xcf4 ++ ++// ++// 7. PageD(0xD00) ++// ++#define rOFDM1_LSTF 0xd00 ++#define rOFDM1_TRxPathEnable 0xd04 ++ ++#define rOFDM1_CFO 0xd08 // No setting now ++#define rOFDM1_CSI1 0xd10 ++#define rOFDM1_SBD 0xd14 ++#define rOFDM1_CSI2 0xd18 ++#define rOFDM1_CFOTracking 0xd2c ++#define rOFDM1_TRxMesaure1 0xd34 ++#define rOFDM1_IntfDet 0xd3c ++#define rOFDM1_PseudoNoiseStateAB 0xd50 ++#define rOFDM1_PseudoNoiseStateCD 0xd54 ++#define rOFDM1_RxPseudoNoiseWgt 0xd58 ++ ++#define rOFDM_PHYCounter1 0xda0 //cca, parity fail ++#define rOFDM_PHYCounter2 0xda4 //rate illegal, crc8 fail ++#define rOFDM_PHYCounter3 0xda8 //MCS not support ++ ++#define rOFDM_ShortCFOAB 0xdac // No setting now ++#define rOFDM_ShortCFOCD 0xdb0 ++#define rOFDM_LongCFOAB 0xdb4 ++#define rOFDM_LongCFOCD 0xdb8 ++#define rOFDM_TailCFOAB 0xdbc ++#define rOFDM_TailCFOCD 0xdc0 ++#define rOFDM_PWMeasure1 0xdc4 ++#define rOFDM_PWMeasure2 0xdc8 ++#define rOFDM_BWReport 0xdcc ++#define rOFDM_AGCReport 0xdd0 ++#define rOFDM_RxSNR 0xdd4 ++#define rOFDM_RxEVMCSI 0xdd8 ++#define rOFDM_SIGReport 0xddc ++ ++ ++// ++// 8. PageE(0xE00) ++// ++#define rTxAGC_A_Rate18_06 0xe00 ++#define rTxAGC_A_Rate54_24 0xe04 ++#define rTxAGC_A_CCK1_Mcs32 0xe08 ++#define rTxAGC_A_Mcs03_Mcs00 0xe10 ++#define rTxAGC_A_Mcs07_Mcs04 0xe14 ++#define rTxAGC_A_Mcs11_Mcs08 0xe18 ++#define rTxAGC_A_Mcs15_Mcs12 0xe1c ++ ++#define rTxAGC_B_Rate18_06 0x830 ++#define rTxAGC_B_Rate54_24 0x834 ++#define rTxAGC_B_CCK1_55_Mcs32 0x838 ++#define rTxAGC_B_Mcs03_Mcs00 0x83c ++#define rTxAGC_B_Mcs07_Mcs04 0x848 ++#define rTxAGC_B_Mcs11_Mcs08 0x84c ++#define rTxAGC_B_Mcs15_Mcs12 0x868 ++#define rTxAGC_B_CCK11_A_CCK2_11 0x86c ++ ++#define rFPGA0_IQK 0xe28 ++#define rTx_IQK_Tone_A 0xe30 ++#define rRx_IQK_Tone_A 0xe34 ++#define rTx_IQK_PI_A 0xe38 ++#define rRx_IQK_PI_A 0xe3c ++ ++#define rTx_IQK 0xe40 ++#define rRx_IQK 0xe44 ++#define rIQK_AGC_Pts 0xe48 ++#define rIQK_AGC_Rsp 0xe4c ++#define rTx_IQK_Tone_B 0xe50 ++#define rRx_IQK_Tone_B 0xe54 ++#define rTx_IQK_PI_B 0xe58 ++#define rRx_IQK_PI_B 0xe5c ++#define rIQK_AGC_Cont 0xe60 ++ ++#define rBlue_Tooth 0xe6c ++#define rRx_Wait_CCA 0xe70 ++#define rTx_CCK_RFON 0xe74 ++#define rTx_CCK_BBON 0xe78 ++#define rTx_OFDM_RFON 0xe7c ++#define rTx_OFDM_BBON 0xe80 ++#define rTx_To_Rx 0xe84 ++#define rTx_To_Tx 0xe88 ++#define rRx_CCK 0xe8c ++ ++#define rTx_Power_Before_IQK_A 0xe94 ++#define rTx_Power_After_IQK_A 0xe9c ++ ++#define rRx_Power_Before_IQK_A 0xea0 ++#define rRx_Power_Before_IQK_A_2 0xea4 ++#define rRx_Power_After_IQK_A 0xea8 ++#define rRx_Power_After_IQK_A_2 0xeac ++ ++#define rTx_Power_Before_IQK_B 0xeb4 ++#define rTx_Power_After_IQK_B 0xebc ++ ++#define rRx_Power_Before_IQK_B 0xec0 ++#define rRx_Power_Before_IQK_B_2 0xec4 ++#define rRx_Power_After_IQK_B 0xec8 ++#define rRx_Power_After_IQK_B_2 0xecc ++ ++#define rRx_OFDM 0xed0 ++#define rRx_Wait_RIFS 0xed4 ++#define rRx_TO_Rx 0xed8 ++#define rStandby 0xedc ++#define rSleep 0xee0 ++#define rPMPD_ANAEN 0xeec ++ ++// ++// 7. RF Register 0x00-0x2E (RF 8256) ++// RF-0222D 0x00-3F ++// ++//Zebra1 ++#define rZebra1_HSSIEnable 0x0 // Useless now ++#define rZebra1_TRxEnable1 0x1 ++#define rZebra1_TRxEnable2 0x2 ++#define rZebra1_AGC 0x4 ++#define rZebra1_ChargePump 0x5 ++#define rZebra1_Channel 0x7 // RF channel switch ++ ++//#endif ++#define rZebra1_TxGain 0x8 // Useless now ++#define rZebra1_TxLPF 0x9 ++#define rZebra1_RxLPF 0xb ++#define rZebra1_RxHPFCorner 0xc ++ ++//Zebra4 ++#define rGlobalCtrl 0 // Useless now ++#define rRTL8256_TxLPF 19 ++#define rRTL8256_RxLPF 11 ++ ++//RTL8258 ++#define rRTL8258_TxLPF 0x11 // Useless now ++#define rRTL8258_RxLPF 0x13 ++#define rRTL8258_RSSILPF 0xa ++ ++// ++// RL6052 Register definition ++// ++#define RF_AC 0x00 // ++ ++#define RF_IQADJ_G1 0x01 // ++#define RF_IQADJ_G2 0x02 // ++#define RF_BS_PA_APSET_G1_G4 0x03 ++#define RF_BS_PA_APSET_G5_G8 0x04 ++#define RF_POW_TRSW 0x05 // ++ ++#define RF_GAIN_RX 0x06 // ++#define RF_GAIN_TX 0x07 // ++ ++#define RF_TXM_IDAC 0x08 // ++#define RF_IPA_G 0x09 // ++#define RF_TXBIAS_G 0x0A ++#define RF_TXPA_AG 0x0B ++#define RF_IPA_A 0x0C // ++#define RF_TXBIAS_A 0x0D ++#define RF_BS_PA_APSET_G9_G11 0x0E ++#define RF_BS_IQGEN 0x0F // ++ ++#define RF_MODE1 0x10 // ++#define RF_MODE2 0x11 // ++ ++#define RF_RX_AGC_HP 0x12 // ++#define RF_TX_AGC 0x13 // ++#define RF_BIAS 0x14 // ++#define RF_IPA 0x15 // ++#define RF_POW_ABILITY 0x17 // ++#define RF_MODE_AG 0x18 // ++#define rRfChannel 0x18 // RF channel and BW switch ++#define RF_CHNLBW 0x18 // RF channel and BW switch ++#define RF_TOP 0x19 // ++ ++#define RF_RX_G1 0x1A // ++#define RF_RX_G2 0x1B // ++ ++#define RF_RX_BB2 0x1C // ++#define RF_RX_BB1 0x1D // ++ ++#define RF_RCK1 0x1E // ++#define RF_RCK2 0x1F // ++ ++#define RF_TX_G1 0x20 // ++#define RF_TX_G2 0x21 // ++#define RF_TX_G3 0x22 // ++ ++#define RF_TX_BB1 0x23 // ++ ++#define RF_T_METER 0x42 // ++ ++#define RF_SYN_G1 0x25 // RF TX Power control ++#define RF_SYN_G2 0x26 // RF TX Power control ++#define RF_SYN_G3 0x27 // RF TX Power control ++#define RF_SYN_G4 0x28 // RF TX Power control ++#define RF_SYN_G5 0x29 // RF TX Power control ++#define RF_SYN_G6 0x2A // RF TX Power control ++#define RF_SYN_G7 0x2B // RF TX Power control ++#define RF_SYN_G8 0x2C // RF TX Power control ++ ++#define RF_RCK_OS 0x30 // RF TX PA control ++ ++#define RF_TXPA_G1 0x31 // RF TX PA control ++#define RF_TXPA_G2 0x32 // RF TX PA control ++#define RF_TXPA_G3 0x33 // RF TX PA control ++#define RF_LOBF_9 0x38 ++#define RF_RXRF_A3 0x3C // ++#define RF_TRSW 0x3F ++ ++#define RF_TXRF_A2 0x41 ++#define RF_TXPA_G4 0x46 ++#define RF_TXPA_A4 0x4B ++ ++// ++//Bit Mask ++// ++// 1. Page1(0x100) ++#define bBBResetB 0x100 // Useless now? ++#define bGlobalResetB 0x200 ++#define bOFDMTxStart 0x4 ++#define bCCKTxStart 0x8 ++#define bCRC32Debug 0x100 ++#define bPMACLoopback 0x10 ++#define bTxLSIG 0xffffff ++#define bOFDMTxRate 0xf ++#define bOFDMTxReserved 0x10 ++#define bOFDMTxLength 0x1ffe0 ++#define bOFDMTxParity 0x20000 ++#define bTxHTSIG1 0xffffff ++#define bTxHTMCSRate 0x7f ++#define bTxHTBW 0x80 ++#define bTxHTLength 0xffff00 ++#define bTxHTSIG2 0xffffff ++#define bTxHTSmoothing 0x1 ++#define bTxHTSounding 0x2 ++#define bTxHTReserved 0x4 ++#define bTxHTAggreation 0x8 ++#define bTxHTSTBC 0x30 ++#define bTxHTAdvanceCoding 0x40 ++#define bTxHTShortGI 0x80 ++#define bTxHTNumberHT_LTF 0x300 ++#define bTxHTCRC8 0x3fc00 ++#define bCounterReset 0x10000 ++#define bNumOfOFDMTx 0xffff ++#define bNumOfCCKTx 0xffff0000 ++#define bTxIdleInterval 0xffff ++#define bOFDMService 0xffff0000 ++#define bTxMACHeader 0xffffffff ++#define bTxDataInit 0xff ++#define bTxHTMode 0x100 ++#define bTxDataType 0x30000 ++#define bTxRandomSeed 0xffffffff ++#define bCCKTxPreamble 0x1 ++#define bCCKTxSFD 0xffff0000 ++#define bCCKTxSIG 0xff ++#define bCCKTxService 0xff00 ++#define bCCKLengthExt 0x8000 ++#define bCCKTxLength 0xffff0000 ++#define bCCKTxCRC16 0xffff ++#define bCCKTxStatus 0x1 ++#define bOFDMTxStatus 0x2 ++ ++#define IS_BB_REG_OFFSET_92S(_Offset) ((_Offset >= 0x800) && (_Offset <= 0xfff)) ++ ++// 2. Page8(0x800) ++#define bRFMOD 0x1 // Reg 0x800 rFPGA0_RFMOD ++#define bJapanMode 0x2 ++#define bCCKTxSC 0x30 ++#define bCCKEn 0x1000000 ++#define bOFDMEn 0x2000000 ++ ++#define bOFDMRxADCPhase 0x10000 // Useless now ++#define bOFDMTxDACPhase 0x40000 ++#define bXATxAGC 0x3f ++ ++#define bAntennaSelect 0x0300 ++ ++#define bXBTxAGC 0xf00 // Reg 80c rFPGA0_TxGainStage ++#define bXCTxAGC 0xf000 ++#define bXDTxAGC 0xf0000 ++ ++#define bPAStart 0xf0000000 // Useless now ++#define bTRStart 0x00f00000 ++#define bRFStart 0x0000f000 ++#define bBBStart 0x000000f0 ++#define bBBCCKStart 0x0000000f ++#define bPAEnd 0xf //Reg0x814 ++#define bTREnd 0x0f000000 ++#define bRFEnd 0x000f0000 ++#define bCCAMask 0x000000f0 //T2R ++#define bR2RCCAMask 0x00000f00 ++#define bHSSI_R2TDelay 0xf8000000 ++#define bHSSI_T2RDelay 0xf80000 ++#define bContTxHSSI 0x400 //chane gain at continue Tx ++#define bIGFromCCK 0x200 ++#define bAGCAddress 0x3f ++#define bRxHPTx 0x7000 ++#define bRxHPT2R 0x38000 ++#define bRxHPCCKIni 0xc0000 ++#define bAGCTxCode 0xc00000 ++#define bAGCRxCode 0x300000 ++ ++#define b3WireDataLength 0x800 // Reg 0x820~84f rFPGA0_XA_HSSIParameter1 ++#define b3WireAddressLength 0x400 ++ ++#define b3WireRFPowerDown 0x1 // Useless now ++//#define bHWSISelect 0x8 ++#define b5GPAPEPolarity 0x40000000 ++#define b2GPAPEPolarity 0x80000000 ++#define bRFSW_TxDefaultAnt 0x3 ++#define bRFSW_TxOptionAnt 0x30 ++#define bRFSW_RxDefaultAnt 0x300 ++#define bRFSW_RxOptionAnt 0x3000 ++#define bRFSI_3WireData 0x1 ++#define bRFSI_3WireClock 0x2 ++#define bRFSI_3WireLoad 0x4 ++#define bRFSI_3WireRW 0x8 ++#define bRFSI_3Wire 0xf ++ ++#define bRFSI_RFENV 0x10 // Reg 0x870 rFPGA0_XAB_RFInterfaceSW ++ ++#define bRFSI_TRSW 0x20 // Useless now ++#define bRFSI_TRSWB 0x40 ++#define bRFSI_ANTSW 0x100 ++#define bRFSI_ANTSWB 0x200 ++#define bRFSI_PAPE 0x400 ++#define bRFSI_PAPE5G 0x800 ++#define bBandSelect 0x1 ++#define bHTSIG2_GI 0x80 ++#define bHTSIG2_Smoothing 0x01 ++#define bHTSIG2_Sounding 0x02 ++#define bHTSIG2_Aggreaton 0x08 ++#define bHTSIG2_STBC 0x30 ++#define bHTSIG2_AdvCoding 0x40 ++#define bHTSIG2_NumOfHTLTF 0x300 ++#define bHTSIG2_CRC8 0x3fc ++#define bHTSIG1_MCS 0x7f ++#define bHTSIG1_BandWidth 0x80 ++#define bHTSIG1_HTLength 0xffff ++#define bLSIG_Rate 0xf ++#define bLSIG_Reserved 0x10 ++#define bLSIG_Length 0x1fffe ++#define bLSIG_Parity 0x20 ++#define bCCKRxPhase 0x4 ++ ++#define bLSSIReadAddress 0x7f800000 // T65 RF ++ ++#define bLSSIReadEdge 0x80000000 //LSSI "Read" edge signal ++ ++#define bLSSIReadBackData 0xfffff // T65 RF ++ ++#define bLSSIReadOKFlag 0x1000 // Useless now ++#define bCCKSampleRate 0x8 //0: 44MHz, 1:88MHz ++#define bRegulator0Standby 0x1 ++#define bRegulatorPLLStandby 0x2 ++#define bRegulator1Standby 0x4 ++#define bPLLPowerUp 0x8 ++#define bDPLLPowerUp 0x10 ++#define bDA10PowerUp 0x20 ++#define bAD7PowerUp 0x200 ++#define bDA6PowerUp 0x2000 ++#define bXtalPowerUp 0x4000 ++#define b40MDClkPowerUP 0x8000 ++#define bDA6DebugMode 0x20000 ++#define bDA6Swing 0x380000 ++ ++#define bADClkPhase 0x4000000 // Reg 0x880 rFPGA0_AnalogParameter1 20/40 CCK support switch 40/80 BB MHZ ++ ++#define b80MClkDelay 0x18000000 // Useless ++#define bAFEWatchDogEnable 0x20000000 ++ ++#define bXtalCap01 0xc0000000 // Reg 0x884 rFPGA0_AnalogParameter2 Crystal cap ++#define bXtalCap23 0x3 ++#define bXtalCap92x 0x0f000000 ++#define bXtalCap 0x0f000000 ++ ++#define bIntDifClkEnable 0x400 // Useless ++#define bExtSigClkEnable 0x800 ++#define bBandgapMbiasPowerUp 0x10000 ++#define bAD11SHGain 0xc0000 ++#define bAD11InputRange 0x700000 ++#define bAD11OPCurrent 0x3800000 ++#define bIPathLoopback 0x4000000 ++#define bQPathLoopback 0x8000000 ++#define bAFELoopback 0x10000000 ++#define bDA10Swing 0x7e0 ++#define bDA10Reverse 0x800 ++#define bDAClkSource 0x1000 ++#define bAD7InputRange 0x6000 ++#define bAD7Gain 0x38000 ++#define bAD7OutputCMMode 0x40000 ++#define bAD7InputCMMode 0x380000 ++#define bAD7Current 0xc00000 ++#define bRegulatorAdjust 0x7000000 ++#define bAD11PowerUpAtTx 0x1 ++#define bDA10PSAtTx 0x10 ++#define bAD11PowerUpAtRx 0x100 ++#define bDA10PSAtRx 0x1000 ++#define bCCKRxAGCFormat 0x200 ++#define bPSDFFTSamplepPoint 0xc000 ++#define bPSDAverageNum 0x3000 ++#define bIQPathControl 0xc00 ++#define bPSDFreq 0x3ff ++#define bPSDAntennaPath 0x30 ++#define bPSDIQSwitch 0x40 ++#define bPSDRxTrigger 0x400000 ++#define bPSDTxTrigger 0x80000000 ++#define bPSDSineToneScale 0x7f000000 ++#define bPSDReport 0xffff ++ ++// 3. Page9(0x900) ++#define bOFDMTxSC 0x30000000 // Useless ++#define bCCKTxOn 0x1 ++#define bOFDMTxOn 0x2 ++#define bDebugPage 0xfff //reset debug page and also HWord, LWord ++#define bDebugItem 0xff //reset debug page and LWord ++#define bAntL 0x10 ++#define bAntNonHT 0x100 ++#define bAntHT1 0x1000 ++#define bAntHT2 0x10000 ++#define bAntHT1S1 0x100000 ++#define bAntNonHTS1 0x1000000 ++ ++// 4. PageA(0xA00) ++#define bCCKBBMode 0x3 // Useless ++#define bCCKTxPowerSaving 0x80 ++#define bCCKRxPowerSaving 0x40 ++ ++#define bCCKSideBand 0x10 // Reg 0xa00 rCCK0_System 20/40 switch ++ ++#define bCCKScramble 0x8 // Useless ++#define bCCKAntDiversity 0x8000 ++#define bCCKCarrierRecovery 0x4000 ++#define bCCKTxRate 0x3000 ++#define bCCKDCCancel 0x0800 ++#define bCCKISICancel 0x0400 ++#define bCCKMatchFilter 0x0200 ++#define bCCKEqualizer 0x0100 ++#define bCCKPreambleDetect 0x800000 ++#define bCCKFastFalseCCA 0x400000 ++#define bCCKChEstStart 0x300000 ++#define bCCKCCACount 0x080000 ++#define bCCKcs_lim 0x070000 ++#define bCCKBistMode 0x80000000 ++#define bCCKCCAMask 0x40000000 ++#define bCCKTxDACPhase 0x4 ++#define bCCKRxADCPhase 0x20000000 //r_rx_clk ++#define bCCKr_cp_mode0 0x0100 ++#define bCCKTxDCOffset 0xf0 ++#define bCCKRxDCOffset 0xf ++#define bCCKCCAMode 0xc000 ++#define bCCKFalseCS_lim 0x3f00 ++#define bCCKCS_ratio 0xc00000 ++#define bCCKCorgBit_sel 0x300000 ++#define bCCKPD_lim 0x0f0000 ++#define bCCKNewCCA 0x80000000 ++#define bCCKRxHPofIG 0x8000 ++#define bCCKRxIG 0x7f00 ++#define bCCKLNAPolarity 0x800000 ++#define bCCKRx1stGain 0x7f0000 ++#define bCCKRFExtend 0x20000000 //CCK Rx Iinital gain polarity ++#define bCCKRxAGCSatLevel 0x1f000000 ++#define bCCKRxAGCSatCount 0xe0 ++#define bCCKRxRFSettle 0x1f //AGCsamp_dly ++#define bCCKFixedRxAGC 0x8000 ++//#define bCCKRxAGCFormat 0x4000 //remove to HSSI register 0x824 ++#define bCCKAntennaPolarity 0x2000 ++#define bCCKTxFilterType 0x0c00 ++#define bCCKRxAGCReportType 0x0300 ++#define bCCKRxDAGCEn 0x80000000 ++#define bCCKRxDAGCPeriod 0x20000000 ++#define bCCKRxDAGCSatLevel 0x1f000000 ++#define bCCKTimingRecovery 0x800000 ++#define bCCKTxC0 0x3f0000 ++#define bCCKTxC1 0x3f000000 ++#define bCCKTxC2 0x3f ++#define bCCKTxC3 0x3f00 ++#define bCCKTxC4 0x3f0000 ++#define bCCKTxC5 0x3f000000 ++#define bCCKTxC6 0x3f ++#define bCCKTxC7 0x3f00 ++#define bCCKDebugPort 0xff0000 ++#define bCCKDACDebug 0x0f000000 ++#define bCCKFalseAlarmEnable 0x8000 ++#define bCCKFalseAlarmRead 0x4000 ++#define bCCKTRSSI 0x7f ++#define bCCKRxAGCReport 0xfe ++#define bCCKRxReport_AntSel 0x80000000 ++#define bCCKRxReport_MFOff 0x40000000 ++#define bCCKRxRxReport_SQLoss 0x20000000 ++#define bCCKRxReport_Pktloss 0x10000000 ++#define bCCKRxReport_Lockedbit 0x08000000 ++#define bCCKRxReport_RateError 0x04000000 ++#define bCCKRxReport_RxRate 0x03000000 ++#define bCCKRxFACounterLower 0xff ++#define bCCKRxFACounterUpper 0xff000000 ++#define bCCKRxHPAGCStart 0xe000 ++#define bCCKRxHPAGCFinal 0x1c00 ++#define bCCKRxFalseAlarmEnable 0x8000 ++#define bCCKFACounterFreeze 0x4000 ++#define bCCKTxPathSel 0x10000000 ++#define bCCKDefaultRxPath 0xc000000 ++#define bCCKOptionRxPath 0x3000000 ++ ++// 5. PageC(0xC00) ++#define bNumOfSTF 0x3 // Useless ++#define bShift_L 0xc0 ++#define bGI_TH 0xc ++#define bRxPathA 0x1 ++#define bRxPathB 0x2 ++#define bRxPathC 0x4 ++#define bRxPathD 0x8 ++#define bTxPathA 0x1 ++#define bTxPathB 0x2 ++#define bTxPathC 0x4 ++#define bTxPathD 0x8 ++#define bTRSSIFreq 0x200 ++#define bADCBackoff 0x3000 ++#define bDFIRBackoff 0xc000 ++#define bTRSSILatchPhase 0x10000 ++#define bRxIDCOffset 0xff ++#define bRxQDCOffset 0xff00 ++#define bRxDFIRMode 0x1800000 ++#define bRxDCNFType 0xe000000 ++#define bRXIQImb_A 0x3ff ++#define bRXIQImb_B 0xfc00 ++#define bRXIQImb_C 0x3f0000 ++#define bRXIQImb_D 0xffc00000 ++#define bDC_dc_Notch 0x60000 ++#define bRxNBINotch 0x1f000000 ++#define bPD_TH 0xf ++#define bPD_TH_Opt2 0xc000 ++#define bPWED_TH 0x700 ++#define bIfMF_Win_L 0x800 ++#define bPD_Option 0x1000 ++#define bMF_Win_L 0xe000 ++#define bBW_Search_L 0x30000 ++#define bwin_enh_L 0xc0000 ++#define bBW_TH 0x700000 ++#define bED_TH2 0x3800000 ++#define bBW_option 0x4000000 ++#define bRatio_TH 0x18000000 ++#define bWindow_L 0xe0000000 ++#define bSBD_Option 0x1 ++#define bFrame_TH 0x1c ++#define bFS_Option 0x60 ++#define bDC_Slope_check 0x80 ++#define bFGuard_Counter_DC_L 0xe00 ++#define bFrame_Weight_Short 0x7000 ++#define bSub_Tune 0xe00000 ++#define bFrame_DC_Length 0xe000000 ++#define bSBD_start_offset 0x30000000 ++#define bFrame_TH_2 0x7 ++#define bFrame_GI2_TH 0x38 ++#define bGI2_Sync_en 0x40 ++#define bSarch_Short_Early 0x300 ++#define bSarch_Short_Late 0xc00 ++#define bSarch_GI2_Late 0x70000 ++#define bCFOAntSum 0x1 ++#define bCFOAcc 0x2 ++#define bCFOStartOffset 0xc ++#define bCFOLookBack 0x70 ++#define bCFOSumWeight 0x80 ++#define bDAGCEnable 0x10000 ++#define bTXIQImb_A 0x3ff ++#define bTXIQImb_B 0xfc00 ++#define bTXIQImb_C 0x3f0000 ++#define bTXIQImb_D 0xffc00000 ++#define bTxIDCOffset 0xff ++#define bTxQDCOffset 0xff00 ++#define bTxDFIRMode 0x10000 ++#define bTxPesudoNoiseOn 0x4000000 ++#define bTxPesudoNoise_A 0xff ++#define bTxPesudoNoise_B 0xff00 ++#define bTxPesudoNoise_C 0xff0000 ++#define bTxPesudoNoise_D 0xff000000 ++#define bCCADropOption 0x20000 ++#define bCCADropThres 0xfff00000 ++#define bEDCCA_H 0xf ++#define bEDCCA_L 0xf0 ++#define bLambda_ED 0x300 ++#define bRxInitialGain 0x7f ++#define bRxAntDivEn 0x80 ++#define bRxAGCAddressForLNA 0x7f00 ++#define bRxHighPowerFlow 0x8000 ++#define bRxAGCFreezeThres 0xc0000 ++#define bRxFreezeStep_AGC1 0x300000 ++#define bRxFreezeStep_AGC2 0xc00000 ++#define bRxFreezeStep_AGC3 0x3000000 ++#define bRxFreezeStep_AGC0 0xc000000 ++#define bRxRssi_Cmp_En 0x10000000 ++#define bRxQuickAGCEn 0x20000000 ++#define bRxAGCFreezeThresMode 0x40000000 ++#define bRxOverFlowCheckType 0x80000000 ++#define bRxAGCShift 0x7f ++#define bTRSW_Tri_Only 0x80 ++#define bPowerThres 0x300 ++#define bRxAGCEn 0x1 ++#define bRxAGCTogetherEn 0x2 ++#define bRxAGCMin 0x4 ++#define bRxHP_Ini 0x7 ++#define bRxHP_TRLNA 0x70 ++#define bRxHP_RSSI 0x700 ++#define bRxHP_BBP1 0x7000 ++#define bRxHP_BBP2 0x70000 ++#define bRxHP_BBP3 0x700000 ++#define bRSSI_H 0x7f0000 //the threshold for high power ++#define bRSSI_Gen 0x7f000000 //the threshold for ant diversity ++#define bRxSettle_TRSW 0x7 ++#define bRxSettle_LNA 0x38 ++#define bRxSettle_RSSI 0x1c0 ++#define bRxSettle_BBP 0xe00 ++#define bRxSettle_RxHP 0x7000 ++#define bRxSettle_AntSW_RSSI 0x38000 ++#define bRxSettle_AntSW 0xc0000 ++#define bRxProcessTime_DAGC 0x300000 ++#define bRxSettle_HSSI 0x400000 ++#define bRxProcessTime_BBPPW 0x800000 ++#define bRxAntennaPowerShift 0x3000000 ++#define bRSSITableSelect 0xc000000 ++#define bRxHP_Final 0x7000000 ++#define bRxHTSettle_BBP 0x7 ++#define bRxHTSettle_HSSI 0x8 ++#define bRxHTSettle_RxHP 0x70 ++#define bRxHTSettle_BBPPW 0x80 ++#define bRxHTSettle_Idle 0x300 ++#define bRxHTSettle_Reserved 0x1c00 ++#define bRxHTRxHPEn 0x8000 ++#define bRxHTAGCFreezeThres 0x30000 ++#define bRxHTAGCTogetherEn 0x40000 ++#define bRxHTAGCMin 0x80000 ++#define bRxHTAGCEn 0x100000 ++#define bRxHTDAGCEn 0x200000 ++#define bRxHTRxHP_BBP 0x1c00000 ++#define bRxHTRxHP_Final 0xe0000000 ++#define bRxPWRatioTH 0x3 ++#define bRxPWRatioEn 0x4 ++#define bRxMFHold 0x3800 ++#define bRxPD_Delay_TH1 0x38 ++#define bRxPD_Delay_TH2 0x1c0 ++#define bRxPD_DC_COUNT_MAX 0x600 ++//#define bRxMF_Hold 0x3800 ++#define bRxPD_Delay_TH 0x8000 ++#define bRxProcess_Delay 0xf0000 ++#define bRxSearchrange_GI2_Early 0x700000 ++#define bRxFrame_Guard_Counter_L 0x3800000 ++#define bRxSGI_Guard_L 0xc000000 ++#define bRxSGI_Search_L 0x30000000 ++#define bRxSGI_TH 0xc0000000 ++#define bDFSCnt0 0xff ++#define bDFSCnt1 0xff00 ++#define bDFSFlag 0xf0000 ++#define bMFWeightSum 0x300000 ++#define bMinIdxTH 0x7f000000 ++#define bDAFormat 0x40000 ++#define bTxChEmuEnable 0x01000000 ++#define bTRSWIsolation_A 0x7f ++#define bTRSWIsolation_B 0x7f00 ++#define bTRSWIsolation_C 0x7f0000 ++#define bTRSWIsolation_D 0x7f000000 ++#define bExtLNAGain 0x7c00 ++ ++// 6. PageE(0xE00) ++#define bSTBCEn 0x4 // Useless ++#define bAntennaMapping 0x10 ++#define bNss 0x20 ++#define bCFOAntSumD 0x200 ++#define bPHYCounterReset 0x8000000 ++#define bCFOReportGet 0x4000000 ++#define bOFDMContinueTx 0x10000000 ++#define bOFDMSingleCarrier 0x20000000 ++#define bOFDMSingleTone 0x40000000 ++//#define bRxPath1 0x01 ++//#define bRxPath2 0x02 ++//#define bRxPath3 0x04 ++//#define bRxPath4 0x08 ++//#define bTxPath1 0x10 ++//#define bTxPath2 0x20 ++#define bHTDetect 0x100 ++#define bCFOEn 0x10000 ++#define bCFOValue 0xfff00000 ++#define bSigTone_Re 0x3f ++#define bSigTone_Im 0x7f00 ++#define bCounter_CCA 0xffff ++#define bCounter_ParityFail 0xffff0000 ++#define bCounter_RateIllegal 0xffff ++#define bCounter_CRC8Fail 0xffff0000 ++#define bCounter_MCSNoSupport 0xffff ++#define bCounter_FastSync 0xffff ++#define bShortCFO 0xfff ++#define bShortCFOTLength 12 //total ++#define bShortCFOFLength 11 //fraction ++#define bLongCFO 0x7ff ++#define bLongCFOTLength 11 ++#define bLongCFOFLength 11 ++#define bTailCFO 0x1fff ++#define bTailCFOTLength 13 ++#define bTailCFOFLength 12 ++#define bmax_en_pwdB 0xffff ++#define bCC_power_dB 0xffff0000 ++#define bnoise_pwdB 0xffff ++#define bPowerMeasTLength 10 ++#define bPowerMeasFLength 3 ++#define bRx_HT_BW 0x1 ++#define bRxSC 0x6 ++#define bRx_HT 0x8 ++#define bNB_intf_det_on 0x1 ++#define bIntf_win_len_cfg 0x30 ++#define bNB_Intf_TH_cfg 0x1c0 ++#define bRFGain 0x3f ++#define bTableSel 0x40 ++#define bTRSW 0x80 ++#define bRxSNR_A 0xff ++#define bRxSNR_B 0xff00 ++#define bRxSNR_C 0xff0000 ++#define bRxSNR_D 0xff000000 ++#define bSNREVMTLength 8 ++#define bSNREVMFLength 1 ++#define bCSI1st 0xff ++#define bCSI2nd 0xff00 ++#define bRxEVM1st 0xff0000 ++#define bRxEVM2nd 0xff000000 ++#define bSIGEVM 0xff ++#define bPWDB 0xff00 ++#define bSGIEN 0x10000 ++ ++#define bSFactorQAM1 0xf // Useless ++#define bSFactorQAM2 0xf0 ++#define bSFactorQAM3 0xf00 ++#define bSFactorQAM4 0xf000 ++#define bSFactorQAM5 0xf0000 ++#define bSFactorQAM6 0xf0000 ++#define bSFactorQAM7 0xf00000 ++#define bSFactorQAM8 0xf000000 ++#define bSFactorQAM9 0xf0000000 ++#define bCSIScheme 0x100000 ++ ++#define bNoiseLvlTopSet 0x3 // Useless ++#define bChSmooth 0x4 ++#define bChSmoothCfg1 0x38 ++#define bChSmoothCfg2 0x1c0 ++#define bChSmoothCfg3 0xe00 ++#define bChSmoothCfg4 0x7000 ++#define bMRCMode 0x800000 ++#define bTHEVMCfg 0x7000000 ++ ++#define bLoopFitType 0x1 // Useless ++#define bUpdCFO 0x40 ++#define bUpdCFOOffData 0x80 ++#define bAdvUpdCFO 0x100 ++#define bAdvTimeCtrl 0x800 ++#define bUpdClko 0x1000 ++#define bFC 0x6000 ++#define bTrackingMode 0x8000 ++#define bPhCmpEnable 0x10000 ++#define bUpdClkoLTF 0x20000 ++#define bComChCFO 0x40000 ++#define bCSIEstiMode 0x80000 ++#define bAdvUpdEqz 0x100000 ++#define bUChCfg 0x7000000 ++#define bUpdEqz 0x8000000 ++ ++//Rx Pseduo noise ++#define bRxPesudoNoiseOn 0x20000000 // Useless ++#define bRxPesudoNoise_A 0xff ++#define bRxPesudoNoise_B 0xff00 ++#define bRxPesudoNoise_C 0xff0000 ++#define bRxPesudoNoise_D 0xff000000 ++#define bPesudoNoiseState_A 0xffff ++#define bPesudoNoiseState_B 0xffff0000 ++#define bPesudoNoiseState_C 0xffff ++#define bPesudoNoiseState_D 0xffff0000 ++ ++//7. RF Register ++//Zebra1 ++#define bZebra1_HSSIEnable 0x8 // Useless ++#define bZebra1_TRxControl 0xc00 ++#define bZebra1_TRxGainSetting 0x07f ++#define bZebra1_RxCorner 0xc00 ++#define bZebra1_TxChargePump 0x38 ++#define bZebra1_RxChargePump 0x7 ++#define bZebra1_ChannelNum 0xf80 ++#define bZebra1_TxLPFBW 0x400 ++#define bZebra1_RxLPFBW 0x600 ++ ++//Zebra4 ++#define bRTL8256RegModeCtrl1 0x100 // Useless ++#define bRTL8256RegModeCtrl0 0x40 ++#define bRTL8256_TxLPFBW 0x18 ++#define bRTL8256_RxLPFBW 0x600 ++ ++//RTL8258 ++#define bRTL8258_TxLPFBW 0xc // Useless ++#define bRTL8258_RxLPFBW 0xc00 ++#define bRTL8258_RSSILPFBW 0xc0 ++ ++ ++// ++// Other Definition ++// ++ ++//byte endable for sb_write ++#define bByte0 0x1 // Useless ++#define bByte1 0x2 ++#define bByte2 0x4 ++#define bByte3 0x8 ++#define bWord0 0x3 ++#define bWord1 0xc ++#define bDWord 0xf ++ ++//for PutRegsetting & GetRegSetting BitMask ++#define bMaskByte0 0xff // Reg 0xc50 rOFDM0_XAAGCCore~0xC6f ++#define bMaskByte1 0xff00 ++#define bMaskByte2 0xff0000 ++#define bMaskByte3 0xff000000 ++#define bMaskHWord 0xffff0000 ++#define bMaskLWord 0x0000ffff ++#define bMaskDWord 0xffffffff ++#define bMask12Bits 0xfff ++#define bMaskH4Bits 0xf0000000 ++#define bMaskOFDM_D 0xffc00000 ++#define bMaskCCK 0x3f3f3f3f ++ ++//for PutRFRegsetting & GetRFRegSetting BitMask ++//#define bMask12Bits 0xfffff // RF Reg mask bits ++//#define bMask20Bits 0xfffff // RF Reg mask bits T65 RF ++#define bRFRegOffsetMask 0xfffff ++//#define bRFRegOffsetMask 0xfff ++ ++//MAC0 will wirte PHY1 ++#define MAC0_ACCESS_PHY1 0x4000 ++//MAC1 will wirte PHY0 ++#define MAC1_ACCESS_PHY0 0x2000 ++ ++#define bEnable 0x1 // Useless ++#define bDisable 0x0 ++ ++#define LeftAntenna 0x0 // Useless ++#define RightAntenna 0x1 ++ ++#define tCheckTxStatus 500 //500ms // Useless ++#define tUpdateRxCounter 100 //100ms ++ ++#define rateCCK 0 // Useless ++#define rateOFDM 1 ++#define rateHT 2 ++ ++//define Register-End ++#define bPMAC_End 0x1ff // Useless ++#define bFPGAPHY0_End 0x8ff ++#define bFPGAPHY1_End 0x9ff ++#define bCCKPHY0_End 0xaff ++#define bOFDMPHY0_End 0xcff ++#define bOFDMPHY1_End 0xdff ++ ++//define max debug item in each debug page ++//#define bMaxItem_FPGA_PHY0 0x9 ++//#define bMaxItem_FPGA_PHY1 0x3 ++//#define bMaxItem_PHY_11B 0x16 ++//#define bMaxItem_OFDM_PHY0 0x29 ++//#define bMaxItem_OFDM_PHY1 0x0 ++ ++#define bPMACControl 0x0 // Useless ++#define bWMACControl 0x1 ++#define bWNICControl 0x2 ++ ++#define PathA 0x0 // Useless ++#define PathB 0x1 ++#define PathC 0x2 ++#define PathD 0x3 ++ ++/*--------------------------Define Parameters-------------------------------*/ ++ ++ ++#endif //__INC_HAL8192SPHYREG_H ++ +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/include/Hal8192DUHWImg.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/include/Hal8192DUHWImg.h 2013-07-26 19:36:06.000000000 +0000 +@@ -0,0 +1,66 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef __INC_HAL8192DU_FW_IMG_H ++#define __INC_HAL8192DU_FW_IMG_H ++ ++#include ++ ++/*Created on 2011/11/11, 8: 8*/ ++ ++#define Rtl8192DUImgArrayLength 32142 ++extern const u8 Rtl8192DUFwImgArray[Rtl8192DUImgArrayLength]; ++#define Rtl8192DUMainArrayLength 1 ++extern const u8 Rtl8192DUFwMainArray[Rtl8192DUMainArrayLength]; ++#define Rtl8192DUDataArrayLength 1 ++extern const u8 Rtl8192DUFwDataArray[Rtl8192DUDataArrayLength]; ++#define Rtl8192DUPHY_REG_2TArrayLength 372 ++extern const u32 Rtl8192DUPHY_REG_2TArray[Rtl8192DUPHY_REG_2TArrayLength]; ++#define Rtl8192DUPHY_REG_1TArrayLength 1 ++extern const u32 Rtl8192DUPHY_REG_1TArray[Rtl8192DUPHY_REG_1TArrayLength]; ++#define Rtl8192DUPHY_REG_Array_PGLength 624 ++extern const u32 Rtl8192DUPHY_REG_Array_PG[Rtl8192DUPHY_REG_Array_PGLength]; ++#define Rtl8192DUPHY_REG_Array_MPLength 12 ++extern const u32 Rtl8192DUPHY_REG_Array_MP[Rtl8192DUPHY_REG_Array_MPLength]; ++#define Rtl8192DURadioA_2TArrayLength 378 ++extern const u32 Rtl8192DURadioA_2TArray[Rtl8192DURadioA_2TArrayLength]; ++#define Rtl8192DURadioB_2TArrayLength 384 ++extern const u32 Rtl8192DURadioB_2TArray[Rtl8192DURadioB_2TArrayLength]; ++#define Rtl8192DURadioA_1TArrayLength 1 ++extern const u32 Rtl8192DURadioA_1TArray[Rtl8192DURadioA_1TArrayLength]; ++#define Rtl8192DURadioB_1TArrayLength 1 ++extern const u32 Rtl8192DURadioB_1TArray[Rtl8192DURadioB_1TArrayLength]; ++#define Rtl8192DURadioA_2T_intPAArrayLength 378 ++extern const u32 Rtl8192DURadioA_2T_intPAArray[Rtl8192DURadioA_2T_intPAArrayLength]; ++#define Rtl8192DURadioB_2T_intPAArrayLength 384 ++extern const u32 Rtl8192DURadioB_2T_intPAArray[Rtl8192DURadioB_2T_intPAArrayLength]; ++#define Rtl8192DUMAC_2T_ArrayLength 192 ++extern const u32 Rtl8192DUMAC_2T_Array[Rtl8192DUMAC_2T_ArrayLength]; ++#define Rtl8192DUAGCTAB_ArrayLength 386 ++extern const u32 Rtl8192DUAGCTAB_Array[Rtl8192DUAGCTAB_ArrayLength]; ++#define Rtl8192DUAGCTAB_5GArrayLength 194 ++extern const u32 Rtl8192DUAGCTAB_5GArray[Rtl8192DUAGCTAB_5GArrayLength]; ++#define Rtl8192DUAGCTAB_2GArrayLength 194 ++extern const u32 Rtl8192DUAGCTAB_2GArray[Rtl8192DUAGCTAB_2GArrayLength]; ++#define Rtl8192DUAGCTAB_2TArrayLength 1 ++extern const u32 Rtl8192DUAGCTAB_2TArray[Rtl8192DUAGCTAB_2TArrayLength]; ++#define Rtl8192DUAGCTAB_1TArrayLength 1 ++extern const u32 Rtl8192DUAGCTAB_1TArray[Rtl8192DUAGCTAB_1TArrayLength]; ++ ++#endif //__INC_HAL8192CU_FW_IMG_H +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/include/Hal8192DUHWImg_wowlan.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/include/Hal8192DUHWImg_wowlan.h 2013-07-26 19:36:06.000000000 +0000 +@@ -0,0 +1,30 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef __INC_HAL8192DU_FW_IMG_WOWLAN_H ++#define __INC_HAL8192DU_FW_IMG_WOWLAN_H ++ ++/*Created on 2011/11/ 8, 14:15*/ ++ ++ ++#define DUWWImgArrayLength 16656 ++extern u8 Rtl8192DUFwWWImgArray[DUWWImgArrayLength]; ++ ++#endif //__INC_HAL8192DU_FW_IMG_WOWLAN_H ++ +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/include/Hal8192DUTestHWImg.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/include/Hal8192DUTestHWImg.h 2013-07-26 19:36:06.000000000 +0000 +@@ -0,0 +1,54 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef __INC_HAL8192DUTEST_FW_IMG_H ++#define __INC_HAL8192DUTEST_FW_IMG_H ++ ++#include ++ ++/*Created on 2010/ 5/27, 9:49*/ ++ ++#define Rtl8192DTestImgArrayLength 15054 ++extern u8 Rtl8192DTestFwImgArray[Rtl8192DTestImgArrayLength]; ++#define Rtl8192DTestMainArrayLength 1 ++extern u8 Rtl8192DTestFwMainArray[Rtl8192DTestMainArrayLength]; ++#define Rtl8192DTestDataArrayLength 1 ++extern u8 Rtl8192DTestFwDataArray[Rtl8192DTestDataArrayLength]; ++#define Rtl8192DTestPHY_REG_2TArrayLength 376 ++extern u32 Rtl8192DTestPHY_REG_2TArray[Rtl8192DTestPHY_REG_2TArrayLength]; ++#define Rtl8192DTestPHY_REG_1TArrayLength 1 ++extern u32 Rtl8192DTestPHY_REG_1TArray[Rtl8192DTestPHY_REG_1TArrayLength]; ++#define Rtl8192DTestPHY_REG_Array_PGLength 1 ++extern u32 Rtl8192DTestPHY_REG_Array_PG[Rtl8192DTestPHY_REG_Array_PGLength]; ++#define Rtl8192DTestRadioA_2TArrayLength 340 ++extern u32 Rtl8192DTestRadioA_2TArray[Rtl8192DTestRadioA_2TArrayLength]; ++#define Rtl8192DTestRadioB_2TArrayLength 340 ++extern u32 Rtl8192DTestRadioB_2TArray[Rtl8192DTestRadioB_2TArrayLength]; ++#define Rtl8192DTestRadioA_1TArrayLength 1 ++extern u32 Rtl8192DTestRadioA_1TArray[Rtl8192DTestRadioA_1TArrayLength]; ++#define Rtl8192DTestRadioB_1TArrayLength 1 ++extern u32 Rtl8192DTestRadioB_1TArray[Rtl8192DTestRadioB_1TArrayLength]; ++#define Rtl8192DTestMAC_2TArrayLength 174 ++extern u32 Rtl8192DTestMAC_2TArray[Rtl8192DTestMAC_2TArrayLength]; ++#define Rtl8192DTestAGCTAB_5GArrayLength 514 ++extern u32 Rtl8192DTestAGCTAB_5GArray[Rtl8192DTestAGCTAB_5GArrayLength]; ++#define Rtl8192DTestAGCTAB_2GArrayLength 514 ++extern u32 Rtl8192DTestAGCTAB_2GArray[Rtl8192DTestAGCTAB_2GArrayLength]; ++ ++#endif //__INC_HAL8192CU_FW_IMG_H +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/include/autoconf.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/include/autoconf.h 2013-07-26 19:36:06.000000000 +0000 +@@ -0,0 +1,285 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++ ++/* ++ * Public General Config ++ */ ++#define AUTOCONF_INCLUDED ++#define RTL871X_MODULE_NAME "92CU" ++#define DRV_NAME "rtl8192cu" ++ ++#define CONFIG_USB_HCI 1 ++ ++#define CONFIG_RTL8192C 1 ++ ++#define PLATFORM_LINUX 1 ++ ++ ++//#define CONFIG_IOCTL_CFG80211 1 ++#ifdef CONFIG_IOCTL_CFG80211 ++ #define CONFIG_CFG80211_FORCE_COMPATIBLE_2_6_37_UNDER ++ //#define CONFIG_DEBUG_CFG80211 1 ++#endif ++ ++/* ++ * Internal General Config ++ */ ++//#define CONFIG_PWRCTRL ++//#define CONFIG_H2CLBK ++ ++#define CONFIG_EMBEDDED_FWIMG 1 ++//#define CONFIG_FILE_FWIMG ++ ++#ifdef CONFIG_WAKE_ON_WLAN ++#define CONFIG_WOWLAN 1 ++#endif //CONFIG_WAKE_ON_WLAN ++ ++#define CONFIG_R871X_TEST 1 ++ ++#define CONFIG_80211N_HT 1 ++ ++#define CONFIG_RECV_REORDERING_CTRL 1 ++ ++//#define CONFIG_TCP_CSUM_OFFLOAD_RX 1 ++ ++//#define CONFIG_DRVEXT_MODULE 1 ++ ++#ifndef CONFIG_MP_INCLUDED ++ #define CONFIG_IPS 1 ++ #ifdef CONFIG_IPS ++ //#define CONFIG_IPS_LEVEL_2 1 //enable this to set default IPS mode to IPS_LEVEL_2 ++ #endif ++ #define SUPPORT_HW_RFOFF_DETECTED 1 ++ ++ #define CONFIG_LPS 1 ++ #define CONFIG_BT_COEXIST 1 ++ //befor link ++ #define CONFIG_ANTENNA_DIVERSITY ++ //after link ++ #ifdef CONFIG_ANTENNA_DIVERSITY ++ #define CONFIG_SW_ANTENNA_DIVERSITY ++ //#define CONFIG_HW_ANTENNA_DIVERSITY ++ #endif ++ ++ #define CONFIG_IOL ++#else //#ifndef CONFIG_MP_INCLUDED ++ #define CONFIG_MP_IWPRIV_SUPPORT 1 ++#endif //#ifndef CONFIG_MP_INCLUDED ++ ++#define CONFIG_AP_MODE 1 ++#define CONFIG_NATIVEAP_MLME 1 ++ ++// Added by Albert 20110314 ++#define CONFIG_P2P 1 ++ ++ ++#ifdef CONFIG_P2P ++// Added by Albert 20110812 ++// The CONFIG_WFD is for supporting the Wi-Fi display ++//#define CONFIG_WFD 1 ++ ++// Unmarked if there is low p2p scanned ratio; Kurt ++//#define CONFIG_P2P_AGAINST_NOISE 1 ++#define CONFIG_P2P_REMOVE_GROUP_INFO ++//#define CONFIG_DBG_P2P ++#endif ++ ++// Added by Kurt 20110511 ++//#define CONFIG_TDLS 1 ++#ifdef CONFIG_TDLS ++ #define CONFIG_TDLS_AUTOSETUP 1 ++ #define CONFIG_TDLS_AUTOCHECKALIVE 1 ++#endif ++ ++#ifdef CONFIG_AP_MODE ++ #ifndef CONFIG_NATIVEAP_MLME ++ #define CONFIG_HOSTAPD_MLME 1 ++ #endif ++ #define CONFIG_FIND_BEST_CHANNEL 1 ++#endif ++ ++#define CONFIG_SKB_COPY 1//for amsdu ++ ++#define CONFIG_LED ++#ifdef CONFIG_LED ++ #define CONFIG_SW_LED ++ #ifdef CONFIG_SW_LED ++ //#define CONFIG_LED_HANDLED_BY_CMD_THREAD ++ #endif ++#endif // CONFIG_LED ++ ++ ++ ++#define USB_INTERFERENCE_ISSUE // this should be checked in all usb interface ++#define CONFIG_GLOBAL_UI_PID ++ ++#define CONFIG_LAYER2_ROAMING ++#define CONFIG_LAYER2_ROAMING_RESUME ++//#define CONFIG_ADAPTOR_INFO_CACHING_FILE // now just applied on 8192cu only, should make it general... ++//#define CONFIG_RESUME_IN_WORKQUEUE ++//#define CONFIG_SET_SCAN_DENY_TIMER ++#define CONFIG_LONG_DELAY_ISSUE ++#define CONFIG_NEW_SIGNAL_STAT_PROCESS ++//#define CONFIG_SIGNAL_DISPLAY_DBM //display RX signal with dbm ++ ++#ifdef CONFIG_IOL ++ #define CONFIG_IOL_LLT ++ #define CONFIG_IOL_MAC ++ #define CONFIG_IOL_BB_PHY_REG ++ #define CONFIG_IOL_BB_AGC_TAB ++ #define CONFIG_IOL_RF_RF90_PATH_A ++ #define CONFIG_IOL_RF_RF90_PATH_B ++#endif ++ ++#define CONFIG_BR_EXT 1 // Enable NAT2.5 support for STA mode interface with a L2 Bridge ++#ifdef CONFIG_BR_EXT ++#define CONFIG_BR_EXT_BRNAME "br0" ++#endif // CONFIG_BR_EXT ++ ++#define CONFIG_TX_MCAST2UNI 1 // Support IP multicast->unicast ++//#define CONFIG_CHECK_AC_LIFETIME 1 // Check packet lifetime of 4 ACs. ++ ++ ++/* ++ * Interface Related Config ++ */ ++//#define CONFIG_USB_INTERRUPT_IN_PIPE 1 ++ ++#ifndef CONFIG_MINIMAL_MEMORY_USAGE ++ #define CONFIG_USB_TX_AGGREGATION 1 ++ #define CONFIG_USB_RX_AGGREGATION 1 ++#endif ++ ++#define CONFIG_PREALLOC_RECV_SKB 1 ++//#define CONFIG_REDUCE_USB_TX_INT 1 // Trade-off: Improve performance, but may cause TX URBs blocked by USB Host/Bus driver on few platforms. ++//#define CONFIG_EASY_REPLACEMENT 1 ++ ++/* ++ * CONFIG_USE_USB_BUFFER_ALLOC_XX uses Linux USB Buffer alloc API and is for Linux platform only now! ++ */ ++#define CONFIG_USE_USB_BUFFER_ALLOC_TX 1 // Trade-off: For TX path, improve stability on some platforms, but may cause performance degrade on other platforms. ++//#define CONFIG_USE_USB_BUFFER_ALLOC_RX 1 // For RX path ++ ++/* ++ * USB VENDOR REQ BUFFER ALLOCATION METHOD ++ * if not set we'll use function local variable (stack memory) ++ */ ++//#define CONFIG_USB_VENDOR_REQ_BUFFER_DYNAMIC_ALLOCATE ++#define CONFIG_USB_VENDOR_REQ_BUFFER_PREALLOC ++ ++#define CONFIG_USB_VENDOR_REQ_MUTEX ++#define CONFIG_VENDOR_REQ_RETRY ++ ++//#define CONFIG_USB_SUPPORT_ASYNC_VDN_REQ 1 ++ ++ ++/* ++ * HAL Related Config ++ */ ++ ++#define RTL8192C_RX_PACKET_NO_INCLUDE_CRC 1 ++ ++#define SUPPORTED_BLOCK_IO ++ ++ ++ ++#define RTL8192CU_FW_DOWNLOAD_ENABLE 1 ++ ++#define CONFIG_ONLY_ONE_OUT_EP_TO_LOW 0 ++ ++#define CONFIG_OUT_EP_WIFI_MODE 0 ++ ++#define ENABLE_USB_DROP_INCORRECT_OUT 0 ++ ++#define RTL8192CU_ASIC_VERIFICATION 0 // For ASIC verification. ++ ++#define RTL8192CU_ADHOC_WORKAROUND_SETTING 1 ++ ++#define DISABLE_BB_RF 0 ++ ++#define RTL8191C_FPGA_NETWORKTYPE_ADHOC 0 ++ ++#ifdef CONFIG_MP_INCLUDED ++ #define MP_DRIVER 1 ++ #undef CONFIG_USB_TX_AGGREGATION ++ #undef CONFIG_USB_RX_AGGREGATION ++#else ++ #define MP_DRIVER 0 ++#endif ++ ++ ++/* ++ * Platform Related Config ++ */ ++#ifdef CONFIG_PLATFORM_MN10300 ++#define CONFIG_SPECIAL_SETTING_FOR_FUNAI_TV ++ ++#if defined (CONFIG_SW_ANTENNA_DIVERSITY) ++ #undef CONFIG_SW_ANTENNA_DIVERSITY ++ #define CONFIG_HW_ANTENNA_DIVERSITY ++#endif ++ ++#endif ++ ++#ifdef CONFIG_WISTRON_PLATFORM ++ ++#endif ++ ++#ifdef CONFIG_PLATFORM_TI_DM365 ++#define CONFIG_USE_USB_BUFFER_ALLOC_RX 1 ++#endif ++ ++ ++/* ++ * Debug Related Config ++ */ ++//#define CONFIG_DEBUG_RTL871X ++ ++#define DBG 0 ++//#define CONFIG_DEBUG_RTL819X ++ ++#define CONFIG_PROC_DEBUG 1 ++ ++//#define DBG_IO ++//#define DBG_DELAY_OS ++//#define DBG_MEM_ALLOC ++//#define DBG_IOCTL ++ ++//#define DBG_TX ++//#define DBG_XMIT_BUF ++//#define DBG_TX_DROP_FRAME ++ ++//#define DBG_RX_DROP_FRAME ++//#define DBG_RX_SEQ ++//#define DBG_RX_SIGNAL_DISPLAY_PROCESSING ++//#define DBG_RX_SIGNAL_DISPLAY_SSID_MONITORED "jeff-ap" ++ ++//#define DBG_EXPIRATION_CHK ++ ++ ++//#define DBG_SHOW_MCUFWDL_BEFORE_51_ENABLE ++//#define DBG_ROAMING_TEST ++ ++//#define DBG_HAL_INIT_PROFILING ++#define DBG_MEMORY_LEAK 1 ++ ++#define DBG_CONFIG_ERROR_DETECT ++//#define DBG_CONFIG_ERROR_RESET ++ +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/include/basic_types.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/include/basic_types.h 2013-07-26 19:36:06.000000000 +0000 +@@ -0,0 +1,276 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef __BASIC_TYPES_H__ ++#define __BASIC_TYPES_H__ ++ ++#include ++ ++ ++#define SUCCESS 0 ++#define FAIL (-1) ++ ++#ifndef TRUE ++ #define _TRUE 1 ++#else ++ #define _TRUE TRUE ++#endif ++ ++#ifndef FALSE ++ #define _FALSE 0 ++#else ++ #define _FALSE FALSE ++#endif ++ ++#ifdef PLATFORM_WINDOWS ++ ++ typedef signed char s8; ++ typedef unsigned char u8; ++ ++ typedef signed short s16; ++ typedef unsigned short u16; ++ ++ typedef signed long s32; ++ typedef unsigned long u32; ++ ++ typedef unsigned int uint; ++ typedef signed int sint; ++ ++ ++ typedef signed long long s64; ++ typedef unsigned long long u64; ++ ++ #ifdef NDIS50_MINIPORT ++ ++ #define NDIS_MAJOR_VERSION 5 ++ #define NDIS_MINOR_VERSION 0 ++ ++ #endif ++ ++ #ifdef NDIS51_MINIPORT ++ ++ #define NDIS_MAJOR_VERSION 5 ++ #define NDIS_MINOR_VERSION 1 ++ ++ #endif ++ ++ typedef NDIS_PROC proc_t; ++ ++ typedef LONG atomic_t; ++ ++#endif ++ ++ ++#ifdef PLATFORM_LINUX ++ ++ #include ++ #define IN ++ #define OUT ++ #define VOID void ++ #define NDIS_OID uint ++ #define NDIS_STATUS uint ++ ++ typedef signed int sint; ++ ++ #ifndef PVOID ++ typedef void * PVOID; ++ //#define PVOID (void *) ++ #endif ++ ++ #define UCHAR u8 ++ #define USHORT u16 ++ #define UINT u32 ++ #define ULONG u32 ++ ++ typedef void (*proc_t)(void*); ++ ++ typedef __kernel_size_t SIZE_T; ++ typedef __kernel_ssize_t SSIZE_T; ++ #define FIELD_OFFSET(s,field) ((SSIZE_T)&((s*)(0))->field) ++ ++#endif ++ ++#define MEM_ALIGNMENT_OFFSET (sizeof (SIZE_T)) ++#define MEM_ALIGNMENT_PADDING (sizeof(SIZE_T) - 1) ++ ++#define SIZE_PTR SIZE_T ++#define SSIZE_PTR SSIZE_T ++ ++//port from fw by thomas ++// TODO: Belows are Sync from SD7-Driver. It is necessary to check correctness ++ ++/* ++ * Call endian free function when ++ * 1. Read/write packet content. ++ * 2. Before write integer to IO. ++ * 3. After read integer from IO. ++*/ ++ ++// ++// Byte Swapping routine. ++// ++#define EF1Byte ++#define EF2Byte le16_to_cpu ++#define EF4Byte le32_to_cpu ++ ++// ++// Read LE format data from memory ++// ++#define ReadEF1Byte(_ptr) EF1Byte(*((u8 *)(_ptr))) ++#define ReadEF2Byte(_ptr) EF2Byte(*((u16 *)(_ptr))) ++#define ReadEF4Byte(_ptr) EF4Byte(*((u32 *)(_ptr))) ++ ++// ++// Write LE data to memory ++// ++#define WriteEF1Byte(_ptr, _val) (*((u8 *)(_ptr)))=EF1Byte(_val) ++#define WriteEF2Byte(_ptr, _val) (*((u16 *)(_ptr)))=EF2Byte(_val) ++#define WriteEF4Byte(_ptr, _val) (*((u32 *)(_ptr)))=EF4Byte(_val) ++ ++// ++// Example: ++// BIT_LEN_MASK_32(0) => 0x00000000 ++// BIT_LEN_MASK_32(1) => 0x00000001 ++// BIT_LEN_MASK_32(2) => 0x00000003 ++// BIT_LEN_MASK_32(32) => 0xFFFFFFFF ++// ++#define BIT_LEN_MASK_32(__BitLen) \ ++ (0xFFFFFFFF >> (32 - (__BitLen))) ++// ++// Example: ++// BIT_OFFSET_LEN_MASK_32(0, 2) => 0x00000003 ++// BIT_OFFSET_LEN_MASK_32(16, 2) => 0x00030000 ++// ++#define BIT_OFFSET_LEN_MASK_32(__BitOffset, __BitLen) \ ++ (BIT_LEN_MASK_32(__BitLen) << (__BitOffset)) ++ ++// ++// Description: ++// Return 4-byte value in host byte ordering from ++// 4-byte pointer in litten-endian system. ++// ++#define LE_P4BYTE_TO_HOST_4BYTE(__pStart) \ ++ (EF4Byte(*((u32 *)(__pStart)))) ++ ++// ++// Description: ++// Translate subfield (continuous bits in little-endian) of 4-byte value in litten byte to ++// 4-byte value in host byte ordering. ++// ++#define LE_BITS_TO_4BYTE(__pStart, __BitOffset, __BitLen) \ ++ ( \ ++ ( LE_P4BYTE_TO_HOST_4BYTE(__pStart) >> (__BitOffset) ) \ ++ & \ ++ BIT_LEN_MASK_32(__BitLen) \ ++ ) ++ ++// ++// Description: ++// Mask subfield (continuous bits in little-endian) of 4-byte value in litten byte oredering ++// and return the result in 4-byte value in host byte ordering. ++// ++#define LE_BITS_CLEARED_TO_4BYTE(__pStart, __BitOffset, __BitLen) \ ++ ( \ ++ LE_P4BYTE_TO_HOST_4BYTE(__pStart) \ ++ & \ ++ ( ~BIT_OFFSET_LEN_MASK_32(__BitOffset, __BitLen) ) \ ++ ) ++ ++// ++// Description: ++// Set subfield of little-endian 4-byte value to specified value. ++// ++#define SET_BITS_TO_LE_4BYTE(__pStart, __BitOffset, __BitLen, __Value) \ ++ *((u32 *)(__pStart)) = \ ++ EF4Byte( \ ++ LE_BITS_CLEARED_TO_4BYTE(__pStart, __BitOffset, __BitLen) \ ++ | \ ++ ( (((u32)__Value) & BIT_LEN_MASK_32(__BitLen)) << (__BitOffset) ) \ ++ ); ++ ++ ++#define BIT_LEN_MASK_16(__BitLen) \ ++ (0xFFFF >> (16 - (__BitLen))) ++ ++#define BIT_OFFSET_LEN_MASK_16(__BitOffset, __BitLen) \ ++ (BIT_LEN_MASK_16(__BitLen) << (__BitOffset)) ++ ++#define LE_P2BYTE_TO_HOST_2BYTE(__pStart) \ ++ (EF2Byte(*((u16 *)(__pStart)))) ++ ++#define LE_BITS_TO_2BYTE(__pStart, __BitOffset, __BitLen) \ ++ ( \ ++ ( LE_P2BYTE_TO_HOST_2BYTE(__pStart) >> (__BitOffset) ) \ ++ & \ ++ BIT_LEN_MASK_16(__BitLen) \ ++ ) ++ ++#define LE_BITS_CLEARED_TO_2BYTE(__pStart, __BitOffset, __BitLen) \ ++ ( \ ++ LE_P2BYTE_TO_HOST_2BYTE(__pStart) \ ++ & \ ++ ( ~BIT_OFFSET_LEN_MASK_16(__BitOffset, __BitLen) ) \ ++ ) ++ ++#define SET_BITS_TO_LE_2BYTE(__pStart, __BitOffset, __BitLen, __Value) \ ++ *((u16 *)(__pStart)) = \ ++ EF2Byte( \ ++ LE_BITS_CLEARED_TO_2BYTE(__pStart, __BitOffset, __BitLen) \ ++ | \ ++ ( (((u16)__Value) & BIT_LEN_MASK_16(__BitLen)) << (__BitOffset) ) \ ++ ); ++ ++#define BIT_LEN_MASK_8(__BitLen) \ ++ (0xFF >> (8 - (__BitLen))) ++ ++#define BIT_OFFSET_LEN_MASK_8(__BitOffset, __BitLen) \ ++ (BIT_LEN_MASK_8(__BitLen) << (__BitOffset)) ++ ++#define LE_P1BYTE_TO_HOST_1BYTE(__pStart) \ ++ (EF1Byte(*((u8 *)(__pStart)))) ++ ++#define LE_BITS_TO_1BYTE(__pStart, __BitOffset, __BitLen) \ ++ ( \ ++ ( LE_P1BYTE_TO_HOST_1BYTE(__pStart) >> (__BitOffset) ) \ ++ & \ ++ BIT_LEN_MASK_8(__BitLen) \ ++ ) ++ ++#define LE_BITS_CLEARED_TO_1BYTE(__pStart, __BitOffset, __BitLen) \ ++ ( \ ++ LE_P1BYTE_TO_HOST_1BYTE(__pStart) \ ++ & \ ++ ( ~BIT_OFFSET_LEN_MASK_8(__BitOffset, __BitLen) ) \ ++ ) ++ ++#define SET_BITS_TO_LE_1BYTE(__pStart, __BitOffset, __BitLen, __Value) \ ++ *((u8 *)(__pStart)) = \ ++ EF1Byte( \ ++ LE_BITS_CLEARED_TO_1BYTE(__pStart, __BitOffset, __BitLen) \ ++ | \ ++ ( (((u8)__Value) & BIT_LEN_MASK_8(__BitLen)) << (__BitOffset) ) \ ++ ); ++ ++// Get the N-bytes aligment offset from the current length ++#define N_BYTE_ALIGMENT(__Value, __Aligment) ((__Aligment == 1) ? (__Value) : (((__Value + __Aligment - 1) / __Aligment) * __Aligment)) ++ ++typedef unsigned char BOOLEAN,*PBOOLEAN; ++ ++#endif //__BASIC_TYPES_H__ ++ +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/include/byteorder/big_endian.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/include/byteorder/big_endian.h 2013-07-26 19:36:06.000000000 +0000 +@@ -0,0 +1,87 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef _LINUX_BYTEORDER_BIG_ENDIAN_H ++#define _LINUX_BYTEORDER_BIG_ENDIAN_H ++ ++#ifndef __BIG_ENDIAN ++#define __BIG_ENDIAN 4321 ++#endif ++#ifndef __BIG_ENDIAN_BITFIELD ++#define __BIG_ENDIAN_BITFIELD ++#endif ++ ++#include ++ ++#define __constant_htonl(x) ((__u32)(x)) ++#define __constant_ntohl(x) ((__u32)(x)) ++#define __constant_htons(x) ((__u16)(x)) ++#define __constant_ntohs(x) ((__u16)(x)) ++#define __constant_cpu_to_le64(x) ___constant_swab64((x)) ++#define __constant_le64_to_cpu(x) ___constant_swab64((x)) ++#define __constant_cpu_to_le32(x) ___constant_swab32((x)) ++#define __constant_le32_to_cpu(x) ___constant_swab32((x)) ++#define __constant_cpu_to_le16(x) ___constant_swab16((x)) ++#define __constant_le16_to_cpu(x) ___constant_swab16((x)) ++#define __constant_cpu_to_be64(x) ((__u64)(x)) ++#define __constant_be64_to_cpu(x) ((__u64)(x)) ++#define __constant_cpu_to_be32(x) ((__u32)(x)) ++#define __constant_be32_to_cpu(x) ((__u32)(x)) ++#define __constant_cpu_to_be16(x) ((__u16)(x)) ++#define __constant_be16_to_cpu(x) ((__u16)(x)) ++#define __cpu_to_le64(x) __swab64((x)) ++#define __le64_to_cpu(x) __swab64((x)) ++#define __cpu_to_le32(x) __swab32((x)) ++#define __le32_to_cpu(x) __swab32((x)) ++#define __cpu_to_le16(x) __swab16((x)) ++#define __le16_to_cpu(x) __swab16((x)) ++#define __cpu_to_be64(x) ((__u64)(x)) ++#define __be64_to_cpu(x) ((__u64)(x)) ++#define __cpu_to_be32(x) ((__u32)(x)) ++#define __be32_to_cpu(x) ((__u32)(x)) ++#define __cpu_to_be16(x) ((__u16)(x)) ++#define __be16_to_cpu(x) ((__u16)(x)) ++#define __cpu_to_le64p(x) __swab64p((x)) ++#define __le64_to_cpup(x) __swab64p((x)) ++#define __cpu_to_le32p(x) __swab32p((x)) ++#define __le32_to_cpup(x) __swab32p((x)) ++#define __cpu_to_le16p(x) __swab16p((x)) ++#define __le16_to_cpup(x) __swab16p((x)) ++#define __cpu_to_be64p(x) (*(__u64*)(x)) ++#define __be64_to_cpup(x) (*(__u64*)(x)) ++#define __cpu_to_be32p(x) (*(__u32*)(x)) ++#define __be32_to_cpup(x) (*(__u32*)(x)) ++#define __cpu_to_be16p(x) (*(__u16*)(x)) ++#define __be16_to_cpup(x) (*(__u16*)(x)) ++#define __cpu_to_le64s(x) __swab64s((x)) ++#define __le64_to_cpus(x) __swab64s((x)) ++#define __cpu_to_le32s(x) __swab32s((x)) ++#define __le32_to_cpus(x) __swab32s((x)) ++#define __cpu_to_le16s(x) __swab16s((x)) ++#define __le16_to_cpus(x) __swab16s((x)) ++#define __cpu_to_be64s(x) do {} while (0) ++#define __be64_to_cpus(x) do {} while (0) ++#define __cpu_to_be32s(x) do {} while (0) ++#define __be32_to_cpus(x) do {} while (0) ++#define __cpu_to_be16s(x) do {} while (0) ++#define __be16_to_cpus(x) do {} while (0) ++ ++#include ++ ++#endif /* _LINUX_BYTEORDER_BIG_ENDIAN_H */ +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/include/byteorder/generic.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/include/byteorder/generic.h 2013-07-26 19:36:06.000000000 +0000 +@@ -0,0 +1,209 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef _LINUX_BYTEORDER_GENERIC_H ++#define _LINUX_BYTEORDER_GENERIC_H ++ ++/* ++ * linux/byteorder_generic.h ++ * Generic Byte-reordering support ++ * ++ * Francois-Rene Rideau 19970707 ++ * gathered all the good ideas from all asm-foo/byteorder.h into one file, ++ * cleaned them up. ++ * I hope it is compliant with non-GCC compilers. ++ * I decided to put __BYTEORDER_HAS_U64__ in byteorder.h, ++ * because I wasn't sure it would be ok to put it in types.h ++ * Upgraded it to 2.1.43 ++ * Francois-Rene Rideau 19971012 ++ * Upgraded it to 2.1.57 ++ * to please Linus T., replaced huge #ifdef's between little/big endian ++ * by nestedly #include'd files. ++ * Francois-Rene Rideau 19971205 ++ * Made it to 2.1.71; now a facelift: ++ * Put files under include/linux/byteorder/ ++ * Split swab from generic support. ++ * ++ * TODO: ++ * = Regular kernel maintainers could also replace all these manual ++ * byteswap macros that remain, disseminated among drivers, ++ * after some grep or the sources... ++ * = Linus might want to rename all these macros and files to fit his taste, ++ * to fit his personal naming scheme. ++ * = it seems that a few drivers would also appreciate ++ * nybble swapping support... ++ * = every architecture could add their byteswap macro in asm/byteorder.h ++ * see how some architectures already do (i386, alpha, ppc, etc) ++ * = cpu_to_beXX and beXX_to_cpu might some day need to be well ++ * distinguished throughout the kernel. This is not the case currently, ++ * since little endian, big endian, and pdp endian machines needn't it. ++ * But this might be the case for, say, a port of Linux to 20/21 bit ++ * architectures (and F21 Linux addict around?). ++ */ ++ ++/* ++ * The following macros are to be defined by : ++ * ++ * Conversion of long and short int between network and host format ++ * ntohl(__u32 x) ++ * ntohs(__u16 x) ++ * htonl(__u32 x) ++ * htons(__u16 x) ++ * It seems that some programs (which? where? or perhaps a standard? POSIX?) ++ * might like the above to be functions, not macros (why?). ++ * if that's true, then detect them, and take measures. ++ * Anyway, the measure is: define only ___ntohl as a macro instead, ++ * and in a separate file, have ++ * unsigned long inline ntohl(x){return ___ntohl(x);} ++ * ++ * The same for constant arguments ++ * __constant_ntohl(__u32 x) ++ * __constant_ntohs(__u16 x) ++ * __constant_htonl(__u32 x) ++ * __constant_htons(__u16 x) ++ * ++ * Conversion of XX-bit integers (16- 32- or 64-) ++ * between native CPU format and little/big endian format ++ * 64-bit stuff only defined for proper architectures ++ * cpu_to_[bl]eXX(__uXX x) ++ * [bl]eXX_to_cpu(__uXX x) ++ * ++ * The same, but takes a pointer to the value to convert ++ * cpu_to_[bl]eXXp(__uXX x) ++ * [bl]eXX_to_cpup(__uXX x) ++ * ++ * The same, but change in situ ++ * cpu_to_[bl]eXXs(__uXX x) ++ * [bl]eXX_to_cpus(__uXX x) ++ * ++ * See asm-foo/byteorder.h for examples of how to provide ++ * architecture-optimized versions ++ * ++ */ ++ ++ ++#if defined(PLATFORM_LINUX) || defined(PLATFORM_WINDOWS) || defined(PLATFORM_MPIXEL) ++/* ++ * inside the kernel, we can use nicknames; ++ * outside of it, we must avoid POSIX namespace pollution... ++ */ ++#define cpu_to_le64 __cpu_to_le64 ++#define le64_to_cpu __le64_to_cpu ++#define cpu_to_le32 __cpu_to_le32 ++#define le32_to_cpu __le32_to_cpu ++#define cpu_to_le16 __cpu_to_le16 ++#define le16_to_cpu __le16_to_cpu ++#define cpu_to_be64 __cpu_to_be64 ++#define be64_to_cpu __be64_to_cpu ++#define cpu_to_be32 __cpu_to_be32 ++#define be32_to_cpu __be32_to_cpu ++#define cpu_to_be16 __cpu_to_be16 ++#define be16_to_cpu __be16_to_cpu ++#define cpu_to_le64p __cpu_to_le64p ++#define le64_to_cpup __le64_to_cpup ++#define cpu_to_le32p __cpu_to_le32p ++#define le32_to_cpup __le32_to_cpup ++#define cpu_to_le16p __cpu_to_le16p ++#define le16_to_cpup __le16_to_cpup ++#define cpu_to_be64p __cpu_to_be64p ++#define be64_to_cpup __be64_to_cpup ++#define cpu_to_be32p __cpu_to_be32p ++#define be32_to_cpup __be32_to_cpup ++#define cpu_to_be16p __cpu_to_be16p ++#define be16_to_cpup __be16_to_cpup ++#define cpu_to_le64s __cpu_to_le64s ++#define le64_to_cpus __le64_to_cpus ++#define cpu_to_le32s __cpu_to_le32s ++#define le32_to_cpus __le32_to_cpus ++#define cpu_to_le16s __cpu_to_le16s ++#define le16_to_cpus __le16_to_cpus ++#define cpu_to_be64s __cpu_to_be64s ++#define be64_to_cpus __be64_to_cpus ++#define cpu_to_be32s __cpu_to_be32s ++#define be32_to_cpus __be32_to_cpus ++#define cpu_to_be16s __cpu_to_be16s ++#define be16_to_cpus __be16_to_cpus ++#endif ++ ++ ++/* ++ * Handle ntohl and suches. These have various compatibility ++ * issues - like we want to give the prototype even though we ++ * also have a macro for them in case some strange program ++ * wants to take the address of the thing or something.. ++ * ++ * Note that these used to return a "long" in libc5, even though ++ * long is often 64-bit these days.. Thus the casts. ++ * ++ * They have to be macros in order to do the constant folding ++ * correctly - if the argument passed into a inline function ++ * it is no longer constant according to gcc.. ++ */ ++ ++#undef ntohl ++#undef ntohs ++#undef htonl ++#undef htons ++ ++/* ++ * Do the prototypes. Somebody might want to take the ++ * address or some such sick thing.. ++ */ ++#if defined(PLATFORM_LINUX) || (defined (__GLIBC__) && __GLIBC__ >= 2) ++extern __u32 ntohl(__u32); ++extern __u32 htonl(__u32); ++#else ++extern unsigned long int ntohl(unsigned long int); ++extern unsigned long int htonl(unsigned long int); ++#endif ++extern unsigned short int ntohs(unsigned short int); ++extern unsigned short int htons(unsigned short int); ++ ++ ++#if defined(__GNUC__) && (__GNUC__ >= 2) && defined(__OPTIMIZE__) || defined(PLATFORM_MPIXEL) ++ ++#define ___htonl(x) __cpu_to_be32(x) ++#define ___htons(x) __cpu_to_be16(x) ++#define ___ntohl(x) __be32_to_cpu(x) ++#define ___ntohs(x) __be16_to_cpu(x) ++ ++#if defined(PLATFORM_LINUX) || (defined (__GLIBC__) && __GLIBC__ >= 2) ++#define htonl(x) ___htonl(x) ++#define ntohl(x) ___ntohl(x) ++#else ++#define htonl(x) ((unsigned long)___htonl(x)) ++#define ntohl(x) ((unsigned long)___ntohl(x)) ++#endif ++#define htons(x) ___htons(x) ++#define ntohs(x) ___ntohs(x) ++ ++#endif /* OPTIMIZE */ ++ ++ ++#if defined (PLATFORM_WINDOWS) ++ ++#define htonl(x) __cpu_to_be32(x) ++#define ntohl(x) __be32_to_cpu(x) ++#define htons(x) __cpu_to_be16(x) ++#define ntohs(x) __be16_to_cpu(x) ++ ++ ++#endif ++ ++#endif /* _LINUX_BYTEORDER_GENERIC_H */ +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/include/byteorder/little_endian.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/include/byteorder/little_endian.h 2013-07-26 19:36:06.000000000 +0000 +@@ -0,0 +1,89 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef _LINUX_BYTEORDER_LITTLE_ENDIAN_H ++#define _LINUX_BYTEORDER_LITTLE_ENDIAN_H ++ ++#ifndef __LITTLE_ENDIAN ++#define __LITTLE_ENDIAN 1234 ++#endif ++#ifndef __LITTLE_ENDIAN_BITFIELD ++#define __LITTLE_ENDIAN_BITFIELD ++#endif ++ ++#include ++ ++#ifndef __constant_htonl ++#define __constant_htonl(x) ___constant_swab32((x)) ++#define __constant_ntohl(x) ___constant_swab32((x)) ++#define __constant_htons(x) ___constant_swab16((x)) ++#define __constant_ntohs(x) ___constant_swab16((x)) ++#define __constant_cpu_to_le64(x) ((__u64)(x)) ++#define __constant_le64_to_cpu(x) ((__u64)(x)) ++#define __constant_cpu_to_le32(x) ((__u32)(x)) ++#define __constant_le32_to_cpu(x) ((__u32)(x)) ++#define __constant_cpu_to_le16(x) ((__u16)(x)) ++#define __constant_le16_to_cpu(x) ((__u16)(x)) ++#define __constant_cpu_to_be64(x) ___constant_swab64((x)) ++#define __constant_be64_to_cpu(x) ___constant_swab64((x)) ++#define __constant_cpu_to_be32(x) ___constant_swab32((x)) ++#define __constant_be32_to_cpu(x) ___constant_swab32((x)) ++#define __constant_cpu_to_be16(x) ___constant_swab16((x)) ++#define __constant_be16_to_cpu(x) ___constant_swab16((x)) ++#define __cpu_to_le64(x) ((__u64)(x)) ++#define __le64_to_cpu(x) ((__u64)(x)) ++#define __cpu_to_le32(x) ((__u32)(x)) ++#define __le32_to_cpu(x) ((__u32)(x)) ++#define __cpu_to_le16(x) ((__u16)(x)) ++#define __le16_to_cpu(x) ((__u16)(x)) ++#define __cpu_to_be64(x) __swab64((x)) ++#define __be64_to_cpu(x) __swab64((x)) ++#define __cpu_to_be32(x) __swab32((x)) ++#define __be32_to_cpu(x) __swab32((x)) ++#define __cpu_to_be16(x) __swab16((x)) ++#define __be16_to_cpu(x) __swab16((x)) ++#define __cpu_to_le64p(x) (*(__u64*)(x)) ++#define __le64_to_cpup(x) (*(__u64*)(x)) ++#define __cpu_to_le32p(x) (*(__u32*)(x)) ++#define __le32_to_cpup(x) (*(__u32*)(x)) ++#define __cpu_to_le16p(x) (*(__u16*)(x)) ++#define __le16_to_cpup(x) (*(__u16*)(x)) ++#define __cpu_to_be64p(x) __swab64p((x)) ++#define __be64_to_cpup(x) __swab64p((x)) ++#define __cpu_to_be32p(x) __swab32p((x)) ++#define __be32_to_cpup(x) __swab32p((x)) ++#define __cpu_to_be16p(x) __swab16p((x)) ++#define __be16_to_cpup(x) __swab16p((x)) ++#define __cpu_to_le64s(x) do {} while (0) ++#define __le64_to_cpus(x) do {} while (0) ++#define __cpu_to_le32s(x) do {} while (0) ++#define __le32_to_cpus(x) do {} while (0) ++#define __cpu_to_le16s(x) do {} while (0) ++#define __le16_to_cpus(x) do {} while (0) ++#define __cpu_to_be64s(x) __swab64s((x)) ++#define __be64_to_cpus(x) __swab64s((x)) ++#define __cpu_to_be32s(x) __swab32s((x)) ++#define __be32_to_cpus(x) __swab32s((x)) ++#define __cpu_to_be16s(x) __swab16s((x)) ++#define __be16_to_cpus(x) __swab16s((x)) ++#endif // __constant_htonl ++ ++#include ++ ++#endif /* _LINUX_BYTEORDER_LITTLE_ENDIAN_H */ +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/include/byteorder/swab.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/include/byteorder/swab.h 2013-07-26 19:36:06.000000000 +0000 +@@ -0,0 +1,133 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ++******************************************************************************/ ++#ifndef _LINUX_BYTEORDER_SWAB_H ++#define _LINUX_BYTEORDER_SWAB_H ++ ++#if !defined(CONFIG_PLATFORM_MSTAR_TITANIA12) ++#ifndef __u16 ++typedef unsigned short __u16; ++#endif ++ ++#ifndef __u32 ++typedef unsigned int __u32; ++#endif ++ ++#ifndef __u8 ++typedef unsigned char __u8; ++#endif ++ ++#ifndef __u64 ++typedef unsigned long long __u64; ++#endif ++ ++ ++__inline static __u16 ___swab16(__u16 x) ++{ ++ __u16 __x = x; ++ return ++ ((__u16)( ++ (((__u16)(__x) & (__u16)0x00ffU) << 8) | ++ (((__u16)(__x) & (__u16)0xff00U) >> 8) )); ++ ++} ++ ++__inline static __u32 ___swab32(__u32 x) ++{ ++ __u32 __x = (x); ++ return ((__u32)( ++ (((__u32)(__x) & (__u32)0x000000ffUL) << 24) | ++ (((__u32)(__x) & (__u32)0x0000ff00UL) << 8) | ++ (((__u32)(__x) & (__u32)0x00ff0000UL) >> 8) | ++ (((__u32)(__x) & (__u32)0xff000000UL) >> 24) )); ++} ++ ++__inline static __u64 ___swab64(__u64 x) ++{ ++ __u64 __x = (x); ++ ++ return ++ ((__u64)( \ ++ (__u64)(((__u64)(__x) & (__u64)0x00000000000000ffULL) << 56) | \ ++ (__u64)(((__u64)(__x) & (__u64)0x000000000000ff00ULL) << 40) | \ ++ (__u64)(((__u64)(__x) & (__u64)0x0000000000ff0000ULL) << 24) | \ ++ (__u64)(((__u64)(__x) & (__u64)0x00000000ff000000ULL) << 8) | \ ++ (__u64)(((__u64)(__x) & (__u64)0x000000ff00000000ULL) >> 8) | \ ++ (__u64)(((__u64)(__x) & (__u64)0x0000ff0000000000ULL) >> 24) | \ ++ (__u64)(((__u64)(__x) & (__u64)0x00ff000000000000ULL) >> 40) | \ ++ (__u64)(((__u64)(__x) & (__u64)0xff00000000000000ULL) >> 56) )); \ ++} ++#endif // CONFIG_PLATFORM_MSTAR_TITANIA12 ++ ++#ifndef __arch__swab16 ++__inline static __u16 __arch__swab16(__u16 x) ++{ ++ return ___swab16(x); ++} ++ ++#endif ++ ++#ifndef __arch__swab32 ++__inline static __u32 __arch__swab32(__u32 x) ++{ ++ __u32 __tmp = (x) ; ++ return ___swab32(__tmp); ++} ++#endif ++ ++#ifndef __arch__swab64 ++ ++__inline static __u64 __arch__swab64(__u64 x) ++{ ++ __u64 __tmp = (x) ; ++ return ___swab64(__tmp); ++} ++ ++ ++#endif ++ ++#ifndef __swab16 ++#define __swab16(x) __fswab16(x) ++#define __swab32(x) __fswab32(x) ++#define __swab64(x) __fswab64(x) ++#endif // __swab16 ++ ++__inline static const __u16 __fswab16(__u16 x) ++{ ++ return __arch__swab16(x); ++} ++__inline static const __u32 __fswab32(__u32 x) ++{ ++ return __arch__swab32(x); ++} ++ ++#if defined(PLATFORM_LINUX) || defined(PLATFORM_WINDOWS) ++#define swab16 __swab16 ++#define swab32 __swab32 ++#define swab64 __swab64 ++#define swab16p __swab16p ++#define swab32p __swab32p ++#define swab64p __swab64p ++#define swab16s __swab16s ++#define swab32s __swab32s ++#define swab64s __swab64s ++#endif ++ ++#endif /* _LINUX_BYTEORDER_SWAB_H */ +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/include/byteorder/swabb.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/include/byteorder/swabb.h 2013-07-26 19:36:06.000000000 +0000 +@@ -0,0 +1,157 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ++******************************************************************************/ ++#ifndef _LINUX_BYTEORDER_SWABB_H ++#define _LINUX_BYTEORDER_SWABB_H ++ ++/* ++ * linux/byteorder/swabb.h ++ * SWAp Bytes Bizarrely ++ * swaHHXX[ps]?(foo) ++ * ++ * Support for obNUXIous pdp-endian and other bizarre architectures. ++ * Will Linux ever run on such ancient beasts? if not, this file ++ * will be but a programming pearl. Still, it's a reminder that we ++ * shouldn't be making too many assumptions when trying to be portable. ++ * ++ */ ++ ++/* ++ * Meaning of the names I chose (vaxlinux people feel free to correct them): ++ * swahw32 swap 16-bit half-words in a 32-bit word ++ * swahb32 swap 8-bit halves of each 16-bit half-word in a 32-bit word ++ * ++ * No 64-bit support yet. I don't know NUXI conventions for long longs. ++ * I guarantee it will be a mess when it's there, though :-> ++ * It will be even worse if there are conflicting 64-bit conventions. ++ * Hopefully, no one ever used 64-bit objects on NUXI machines. ++ * ++ */ ++ ++#define ___swahw32(x) \ ++({ \ ++ __u32 __x = (x); \ ++ ((__u32)( \ ++ (((__u32)(__x) & (__u32)0x0000ffffUL) << 16) | \ ++ (((__u32)(__x) & (__u32)0xffff0000UL) >> 16) )); \ ++}) ++#define ___swahb32(x) \ ++({ \ ++ __u32 __x = (x); \ ++ ((__u32)( \ ++ (((__u32)(__x) & (__u32)0x00ff00ffUL) << 8) | \ ++ (((__u32)(__x) & (__u32)0xff00ff00UL) >> 8) )); \ ++}) ++ ++#define ___constant_swahw32(x) \ ++ ((__u32)( \ ++ (((__u32)(x) & (__u32)0x0000ffffUL) << 16) | \ ++ (((__u32)(x) & (__u32)0xffff0000UL) >> 16) )) ++#define ___constant_swahb32(x) \ ++ ((__u32)( \ ++ (((__u32)(x) & (__u32)0x00ff00ffUL) << 8) | \ ++ (((__u32)(x) & (__u32)0xff00ff00UL) >> 8) )) ++ ++/* ++ * provide defaults when no architecture-specific optimization is detected ++ */ ++#ifndef __arch__swahw32 ++# define __arch__swahw32(x) ___swahw32(x) ++#endif ++#ifndef __arch__swahb32 ++# define __arch__swahb32(x) ___swahb32(x) ++#endif ++ ++#ifndef __arch__swahw32p ++# define __arch__swahw32p(x) __swahw32(*(x)) ++#endif ++#ifndef __arch__swahb32p ++# define __arch__swahb32p(x) __swahb32(*(x)) ++#endif ++ ++#ifndef __arch__swahw32s ++# define __arch__swahw32s(x) do { *(x) = __swahw32p((x)); } while (0) ++#endif ++#ifndef __arch__swahb32s ++# define __arch__swahb32s(x) do { *(x) = __swahb32p((x)); } while (0) ++#endif ++ ++ ++/* ++ * Allow constant folding ++ */ ++#if defined(__GNUC__) && (__GNUC__ >= 2) && defined(__OPTIMIZE__) ++# define __swahw32(x) \ ++(__builtin_constant_p((__u32)(x)) ? \ ++ ___swahw32((x)) : \ ++ __fswahw32((x))) ++# define __swahb32(x) \ ++(__builtin_constant_p((__u32)(x)) ? \ ++ ___swahb32((x)) : \ ++ __fswahb32((x))) ++#else ++# define __swahw32(x) __fswahw32(x) ++# define __swahb32(x) __fswahb32(x) ++#endif /* OPTIMIZE */ ++ ++ ++__inline static__ __const__ __u32 __fswahw32(__u32 x) ++{ ++ return __arch__swahw32(x); ++} ++__inline static__ __u32 __swahw32p(__u32 *x) ++{ ++ return __arch__swahw32p(x); ++} ++__inline static__ void __swahw32s(__u32 *addr) ++{ ++ __arch__swahw32s(addr); ++} ++ ++ ++__inline static__ __const__ __u32 __fswahb32(__u32 x) ++{ ++ return __arch__swahb32(x); ++} ++__inline static__ __u32 __swahb32p(__u32 *x) ++{ ++ return __arch__swahb32p(x); ++} ++__inline static__ void __swahb32s(__u32 *addr) ++{ ++ __arch__swahb32s(addr); ++} ++ ++#ifdef __BYTEORDER_HAS_U64__ ++/* ++ * Not supported yet ++ */ ++#endif /* __BYTEORDER_HAS_U64__ */ ++ ++#if defined(PLATFORM_LINUX) ++#define swahw32 __swahw32 ++#define swahb32 __swahb32 ++#define swahw32p __swahw32p ++#define swahb32p __swahb32p ++#define swahw32s __swahw32s ++#define swahb32s __swahb32s ++#endif ++ ++#endif /* _LINUX_BYTEORDER_SWABB_H */ +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/include/circ_buf.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/include/circ_buf.h 2013-07-26 19:36:06.000000000 +0000 +@@ -0,0 +1,27 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef __CIRC_BUF_H_ ++#define __CIRC_BUF_H_ 1 ++ ++#define CIRC_CNT(head,tail,size) (((head) - (tail)) & ((size)-1)) ++ ++#define CIRC_SPACE(head,tail,size) CIRC_CNT((tail),((head)+1),(size)) ++ ++#endif //_CIRC_BUF_H_ +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/include/cmd_osdep.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/include/cmd_osdep.h 2013-07-26 19:36:06.000000000 +0000 +@@ -0,0 +1,36 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef __CMD_OSDEP_H_ ++#define __CMD_OSDEP_H_ ++ ++ ++#include ++#include ++#include ++ ++extern sint _rtw_init_cmd_priv (struct cmd_priv *pcmdpriv); ++extern sint _rtw_init_evt_priv(struct evt_priv *pevtpriv); ++extern void _rtw_free_evt_priv (struct evt_priv *pevtpriv); ++extern void _rtw_free_cmd_priv (struct cmd_priv *pcmdpriv); ++extern sint _rtw_enqueue_cmd(_queue *queue, struct cmd_obj *obj); ++extern struct cmd_obj *_rtw_dequeue_cmd(_queue *queue); ++ ++#endif ++ +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/include/drv_conf.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/include/drv_conf.h 2013-07-26 19:36:06.000000000 +0000 +@@ -0,0 +1,78 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef __DRV_CONF_H__ ++#define __DRV_CONF_H__ ++#include "autoconf.h" ++ ++#if defined (PLATFORM_LINUX) && defined (PLATFORM_WINDOWS) ++ ++#error "Shall be Linux or Windows, but not both!\n" ++ ++#endif ++ ++//Older Android kernel doesn't has CONFIG_ANDROID defined, ++//add this to force CONFIG_ANDROID defined ++#ifdef CONFIG_PLATFORM_ANDROID ++#define CONFIG_ANDROID ++#endif ++ ++#ifdef CONFIG_ANDROID ++//Some Android build will restart the UI while non-printable ascii is passed ++//between java and c/c++ layer (JNI). We force CONFIG_VALIDATE_SSID ++//for Android here. If you are sure there is no risk on your system about this, ++//mask this macro define to support non-printable ascii ssid. ++#define CONFIG_VALIDATE_SSID ++ ++//Android expect dbm as the rx signal strength unit ++#define CONFIG_SIGNAL_DISPLAY_DBM ++#endif ++ ++#if defined(CONFIG_HAS_EARLYSUSPEND) && defined (CONFIG_RESUME_IN_WORKQUEUE) ++ #warning "You have CONFIG_HAS_EARLYSUSPEND enabled in your system, we disable CONFIG_RESUME_IN_WORKQUEUE automatically" ++ #undef CONFIG_RESUME_IN_WORKQUEUE ++#endif ++ ++#if defined(CONFIG_ANDROID_POWER) && defined (CONFIG_RESUME_IN_WORKQUEUE) ++ #warning "You have CONFIG_ANDROID_POWER enabled in your system, we disable CONFIG_RESUME_IN_WORKQUEUE automatically" ++ #undef CONFIG_RESUME_IN_WORKQUEUE ++#endif ++ ++#ifdef CONFIG_RESUME_IN_WORKQUEUE //this can be removed, because there is no case for this... ++ #if !defined( CONFIG_WAKELOCK) && !defined(CONFIG_ANDROID_POWER) ++ #error "enable CONFIG_RESUME_IN_WORKQUEUE without CONFIG_WAKELOCK or CONFIG_ANDROID_POWER will suffer from the danger of wifi's unfunctionality..." ++ #error "If you still want to enable CONFIG_RESUME_IN_WORKQUEUE in this case, mask this preprossor checking and GOOD LUCK..." ++ #endif ++#endif ++ ++//About USB VENDOR REQ ++#if defined(CONFIG_USB_VENDOR_REQ_BUFFER_PREALLOC) && !defined(CONFIG_USB_VENDOR_REQ_MUTEX) ++ #warning "define CONFIG_USB_VENDOR_REQ_MUTEX for CONFIG_USB_VENDOR_REQ_BUFFER_PREALLOC automatically" ++ #define CONFIG_USB_VENDOR_REQ_MUTEX ++#endif ++#if defined(CONFIG_VENDOR_REQ_RETRY) && !defined(CONFIG_USB_VENDOR_REQ_MUTEX) ++ #warning "define CONFIG_USB_VENDOR_REQ_MUTEX for CONFIG_VENDOR_REQ_RETRY automatically" ++ #define CONFIG_USB_VENDOR_REQ_MUTEX ++#endif ++ ++ ++//#include ++ ++#endif // __DRV_CONF_H__ ++ +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/include/drv_types.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/include/drv_types.h 2013-07-26 19:36:06.000000000 +0000 +@@ -0,0 +1,555 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++/*------------------------------------------------------------------------------- ++ ++ For type defines and data structure defines ++ ++--------------------------------------------------------------------------------*/ ++ ++ ++#ifndef __DRV_TYPES_H__ ++#define __DRV_TYPES_H__ ++ ++#include ++#include ++#include ++ ++ ++#ifdef PLATFORM_OS_XP ++#include ++#endif ++ ++#ifdef PLATFORM_OS_CE ++#include ++#endif ++ ++#ifdef PLATFORM_LINUX ++#include ++#endif ++ ++enum _NIC_VERSION { ++ ++ RTL8711_NIC, ++ RTL8712_NIC, ++ RTL8713_NIC, ++ RTL8716_NIC ++ ++}; ++ ++enum{ ++ UP_LINK, ++ DOWN_LINK, ++}; ++typedef struct _ADAPTER _adapter, ADAPTER,*PADAPTER; ++ ++#ifdef CONFIG_80211N_HT ++#include ++#endif ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#ifdef CONFIG_DRVEXT_MODULE ++#include ++#endif ++ ++#ifdef CONFIG_MP_INCLUDED ++#include ++#endif ++ ++#ifdef CONFIG_BR_EXT ++#include ++#endif // CONFIG_BR_EXT ++ ++#ifdef CONFIG_IOCTL_CFG80211 ++ #include "ioctl_cfg80211.h" ++#endif //CONFIG_IOCTL_CFG80211 ++ ++#define SPEC_DEV_ID_NONE BIT(0) ++#define SPEC_DEV_ID_DISABLE_HT BIT(1) ++#define SPEC_DEV_ID_ENABLE_PS BIT(2) ++#define SPEC_DEV_ID_RF_CONFIG_1T1R BIT(3) ++#define SPEC_DEV_ID_RF_CONFIG_2T2R BIT(4) ++#define SPEC_DEV_ID_ASSIGN_IFNAME BIT(5) ++ ++struct specific_device_id{ ++ ++ u32 flags; ++ ++ u16 idVendor; ++ u16 idProduct; ++ ++}; ++ ++struct registry_priv ++{ ++ u8 chip_version; ++ u8 rfintfs; ++ u8 lbkmode; ++ u8 hci; ++ NDIS_802_11_SSID ssid; ++ u8 network_mode; //infra, ad-hoc, auto ++ u8 channel;//ad-hoc support requirement ++ u8 wireless_mode;//A, B, G, auto ++ u8 scan_mode;//active, passive ++ u8 radio_enable; ++ u8 preamble;//long, short, auto ++ u8 vrtl_carrier_sense;//Enable, Disable, Auto ++ u8 vcs_type;//RTS/CTS, CTS-to-self ++ u16 rts_thresh; ++ u16 frag_thresh; ++ u8 adhoc_tx_pwr; ++ u8 soft_ap; ++ u8 power_mgnt; ++ u8 ips_mode; ++ u8 smart_ps; ++ u8 long_retry_lmt; ++ u8 short_retry_lmt; ++ u16 busy_thresh; ++ u8 ack_policy; ++ u8 mp_mode; ++ u8 software_encrypt; ++ u8 software_decrypt; ++ ++ u8 acm_method; ++ //UAPSD ++ u8 wmm_enable; ++ u8 uapsd_enable; ++ u8 uapsd_max_sp; ++ u8 uapsd_acbk_en; ++ u8 uapsd_acbe_en; ++ u8 uapsd_acvi_en; ++ u8 uapsd_acvo_en; ++ ++ WLAN_BSSID_EX dev_network; ++ ++#ifdef CONFIG_80211N_HT ++ u8 ht_enable; ++ u8 cbw40_enable; ++ u8 ampdu_enable;//for tx ++ u8 rx_stbc; ++ u8 ampdu_amsdu;//A-MPDU Supports A-MSDU is permitted ++#endif ++ u8 lowrate_two_xmit; ++ ++ u8 rf_config ; ++ u8 low_power ; ++ ++ u8 wifi_spec;// !turbo_mode ++ ++ u8 channel_plan; ++#ifdef CONFIG_BT_COEXIST ++ u8 bt_iso; ++ u8 bt_sco; ++ u8 bt_ampdu; ++#endif ++ BOOLEAN bAcceptAddbaReq; ++ ++ u8 antdiv_cfg; ++ ++ u8 usbss_enable;//0:disable,1:enable ++ u8 hwpdn_mode;//0:disable,1:enable,2:decide by EFUSE config ++ u8 hwpwrp_detect;//0:disable,1:enable ++ ++ u8 hw_wps_pbc;//0:disable,1:enable ++ ++#ifdef CONFIG_ADAPTOR_INFO_CACHING_FILE ++ char adaptor_info_caching_file_path[PATH_LENGTH_MAX]; ++#endif ++ ++#ifdef CONFIG_LAYER2_ROAMING ++ u8 max_roaming_times; // the max number driver will try to roaming ++#endif ++ ++#ifdef CONFIG_IOL ++ bool force_iol; //enable iol without other concern ++#endif ++ ++#ifdef SUPPORT_64_STA ++ u8 bcmc_rate; ++#endif ++ u8 intel_class_mode; ++}; ++ ++ ++//For registry parameters ++#define RGTRY_OFT(field) ((ULONG)FIELD_OFFSET(struct registry_priv,field)) ++#define RGTRY_SZ(field) sizeof(((struct registry_priv*) 0)->field) ++#define BSSID_OFT(field) ((ULONG)FIELD_OFFSET(WLAN_BSSID_EX,field)) ++#define BSSID_SZ(field) sizeof(((PWLAN_BSSID_EX) 0)->field) ++ ++#define MAX_CONTINUAL_URB_ERR 4 ++ ++struct dvobj_priv { ++ ++ _adapter * padapter; ++ ++ //For 92D, DMDP have 2 interface. ++ u8 InterfaceNumber; ++ u8 NumInterfaces; ++ ++/*-------- below is for SDIO INTERFACE --------*/ ++ ++#ifdef CONFIG_SDIO_HCI ++ ++#ifdef PLATFORM_OS_XP ++ PDEVICE_OBJECT pphysdevobj;//pPhysDevObj; ++ PDEVICE_OBJECT pfuncdevobj;//pFuncDevObj; ++ PDEVICE_OBJECT pnextdevobj;//pNextDevObj; ++ SDBUS_INTERFACE_STANDARD sdbusinft;//SdBusInterface; ++ u8 nextdevstacksz;//unsigned char NextDeviceStackSize; ++#endif//PLATFORM_OS_XP ++ ++#ifdef PLATFORM_OS_CE ++ SD_DEVICE_HANDLE hDevice; ++ SD_CARD_RCA sd_rca; ++ SD_CARD_INTERFACE card_intf; ++ BOOLEAN enableIsarWithStatus; ++ WCHAR active_path[MAX_ACTIVE_REG_PATH]; ++ SD_HOST_BLOCK_CAPABILITY sd_host_blk_cap; ++#endif//PLATFORM_OS_CE ++ ++#ifdef PLATFORM_LINUX ++ struct sdio_func *func; ++#endif//PLATFORM_LINUX ++ ++ u8 func_number;//unsigned char FunctionNumber; ++ u32 block_transfer_len;//unsigned long BLOCK_TRANSFER_LEN; ++ u32 blk_shiftbits; ++ u16 driver_version; ++ u16 rxblknum; ++ u16 rxblknum_rd; ++ u16 c2hblknum; ++ u8 tx_block_mode; ++ u8 rx_block_mode; ++ u8 cmdfifo_cnt; ++ u8 rxfifo_cnt; ++ u16 sdio_hisr; ++ u16 sdio_himr; ++#endif// CONFIG_SDIO_HCI ++ ++/*-------- below is for USB INTERFACE --------*/ ++ ++#ifdef CONFIG_USB_HCI ++ ++ u8 nr_endpoint; ++ u8 ishighspeed; ++ u8 RtNumInPipes; ++ u8 RtNumOutPipes; ++ int ep_num[5]; //endpoint number ++ ++ int RegUsbSS; ++ ++ _sema usb_suspend_sema; ++ ++#ifdef CONFIG_USB_VENDOR_REQ_MUTEX ++ _mutex usb_vendor_req_mutex; ++#endif ++ ++#ifdef CONFIG_USB_VENDOR_REQ_BUFFER_PREALLOC ++ u8 * usb_alloc_vendor_req_buf; ++ u8 * usb_vendor_req_buf; ++#endif ++ ++#ifdef PLATFORM_WINDOWS ++ //related device objects ++ PDEVICE_OBJECT pphysdevobj;//pPhysDevObj; ++ PDEVICE_OBJECT pfuncdevobj;//pFuncDevObj; ++ PDEVICE_OBJECT pnextdevobj;//pNextDevObj; ++ ++ u8 nextdevstacksz;//unsigned char NextDeviceStackSize; //= (CHAR)CEdevice->pUsbDevObj->StackSize + 1; ++ ++ //urb for control diescriptor request ++ ++#ifdef PLATFORM_OS_XP ++ struct _URB_CONTROL_DESCRIPTOR_REQUEST descriptor_urb; ++ PUSB_CONFIGURATION_DESCRIPTOR pconfig_descriptor;//UsbConfigurationDescriptor; ++#endif ++ ++#ifdef PLATFORM_OS_CE ++ WCHAR active_path[MAX_ACTIVE_REG_PATH]; // adapter regpath ++ USB_EXTENSION usb_extension; ++ ++ _nic_hdl pipehdls_r8192c[0x10]; ++#endif ++ ++ u32 config_descriptor_len;//ULONG UsbConfigurationDescriptorLength; ++#endif//PLATFORM_WINDOWS ++ ++#ifdef PLATFORM_LINUX ++ struct usb_interface *pusbintf; ++ struct usb_device *pusbdev; ++#endif//PLATFORM_LINUX ++ ++ ATOMIC_T continual_urb_error; ++#endif//CONFIG_USB_HCI ++ ++/*-------- below is for PCIE INTERFACE --------*/ ++ ++#ifdef CONFIG_PCI_HCI ++ ++#ifdef PLATFORM_LINUX ++ struct pci_dev *ppcidev; ++ ++ //PCI MEM map ++ unsigned long pci_mem_end; /* shared mem end */ ++ unsigned long pci_mem_start; /* shared mem start */ ++ ++ //PCI IO map ++ unsigned long pci_base_addr; /* device I/O address */ ++ ++ //PciBridge ++ struct pci_priv pcipriv; ++ ++ u16 irqline; ++ u8 irq_enabled; ++ u8 irq_alloc; ++ RT_ISR_CONTENT isr_content; ++ _lock irq_th_lock; ++ ++ //ASPM ++ u8 const_pci_aspm; ++ u8 const_amdpci_aspm; ++ u8 const_hwsw_rfoff_d3; ++ u8 const_support_pciaspm; ++ // pci-e bridge */ ++ u8 const_hostpci_aspm_setting; ++ // pci-e device */ ++ u8 const_devicepci_aspm_setting; ++ u8 b_support_aspm; // If it supports ASPM, Offset[560h] = 0x40, otherwise Offset[560h] = 0x00. ++ u8 b_support_backdoor; ++#endif//PLATFORM_LINUX ++ ++#endif//CONFIG_PCI_HCI ++}; ++ ++typedef enum _DRIVER_STATE{ ++ DRIVER_NORMAL = 0, ++ DRIVER_DISAPPEAR = 1, ++ DRIVER_REPLACE_DONGLE = 2, ++}DRIVER_STATE; ++ ++#ifdef CONFIG_INTEL_PROXIM ++struct proxim { ++ bool proxim_support; ++ bool proxim_on; ++ ++ void *proximity_priv; ++ int (*proxim_rx)(_adapter *padapter, ++ union recv_frame *precv_frame); ++ u8 (*proxim_get_var)(_adapter* padapter, u8 type); ++}; ++#endif //CONFIG_INTEL_PROXIM ++ ++#ifdef RTL8723A_SDIO_LOOPBACK ++typedef struct loopbackdata ++{ ++ _sema sema; ++ _thread_hdl_ lbkthread; ++ u8 bstop; ++ u32 cnt; ++ u16 size; ++ u16 txsize; ++ u8 txbuf[0x8000]; ++ u16 rxsize; ++ u8 rxbuf[0x8000]; ++ u8 msg[100]; ++ ++}LOOPBACKDATA, *PLOOPBACKDATA; ++#endif ++ ++struct _ADAPTER{ ++ int DriverState;// for disable driver using module, use dongle to replace module. ++ int pid[3];//process id from UI, 0:wps, 1:hostapd, 2:dhcpcd ++ int bDongle;//build-in module or external dongle ++ u16 chip_type; ++ u16 HardwareType; ++ u16 interface_type;//USB,SDIO,PCI ++ ++ struct dvobj_priv dvobjpriv; ++ struct mlme_priv mlmepriv; ++ struct mlme_ext_priv mlmeextpriv; ++ struct cmd_priv cmdpriv; ++ struct evt_priv evtpriv; ++ //struct io_queue *pio_queue; ++ struct io_priv iopriv; ++ struct xmit_priv xmitpriv; ++ struct recv_priv recvpriv; ++ struct sta_priv stapriv; ++ struct security_priv securitypriv; ++ struct registry_priv registrypriv; ++ struct wlan_acl_pool acl_list; ++ struct pwrctrl_priv pwrctrlpriv; ++ struct eeprom_priv eeprompriv; ++ struct led_priv ledpriv; ++ ++#ifdef CONFIG_MP_INCLUDED ++ struct mp_priv mppriv; ++#endif ++ ++#ifdef CONFIG_DRVEXT_MODULE ++ struct drvext_priv drvextpriv; ++#endif ++ ++#ifdef CONFIG_AP_MODE ++ struct hostapd_priv *phostapdpriv; ++#endif ++ ++#ifdef CONFIG_IOCTL_CFG80211 ++#ifdef CONFIG_P2P ++ struct cfg80211_wifidirect_info cfg80211_wdinfo; ++#endif //CONFIG_IOCTL_CFG80211 ++#endif //CONFIG_P2P ++ ++#ifdef CONFIG_P2P ++ struct wifidirect_info wdinfo; ++#endif //CONFIG_P2P ++ ++#ifdef CONFIG_TDLS ++ struct tdls_info tdlsinfo; ++#endif //CONFIG_TDLS ++ ++ PVOID HalData; ++ u32 hal_data_sz; ++ struct hal_ops HalFunc; ++ ++#ifdef CONFIG_BT_COEXIST ++ //struct btcoexist_priv bt_coexist; ++#endif ++ s32 bDriverStopped; ++ s32 bSurpriseRemoved; ++ s32 bCardDisableWOHSM; ++ ++ u32 IsrContent; ++ u32 ImrContent; ++ ++ u8 EepromAddressSize; ++ u8 hw_init_completed; ++ u8 init_adpt_in_progress; ++ u8 bfirst_init; ++ u8 bHaltInProgress; ++ ++ _thread_hdl_ cmdThread; ++ _thread_hdl_ evtThread; ++ _thread_hdl_ xmitThread; ++ _thread_hdl_ recvThread; ++ ++ ++ NDIS_STATUS (*dvobj_init)(_adapter * adapter); ++ void (*dvobj_deinit)(_adapter * adapter); ++ ++ void (*intf_start)(_adapter * adapter); ++ void (*intf_stop)(_adapter * adapter); ++ ++#ifdef PLATFORM_WINDOWS ++ _nic_hdl hndis_adapter;//hNdisAdapter(NDISMiniportAdapterHandle); ++ _nic_hdl hndis_config;//hNdisConfiguration; ++ NDIS_STRING fw_img; ++ ++ u32 NdisPacketFilter; ++ u8 MCList[MAX_MCAST_LIST_NUM][6]; ++ u32 MCAddrCount; ++#endif //end of PLATFORM_WINDOWS ++ ++ ++#ifdef PLATFORM_LINUX ++ _nic_hdl pnetdev; ++ ++ // used by rtw_rereg_nd_name related function ++ struct rereg_nd_name_data { ++ _nic_hdl old_pnetdev; ++ char old_ifname[IFNAMSIZ]; ++ u8 old_ips_mode; ++ u8 old_bRegUseLed; ++ } rereg_nd_name_priv; ++ ++ int bup; ++ struct net_device_stats stats; ++ struct iw_statistics iwstats; ++ struct proc_dir_entry *dir_dev;// for proc directory ++ ++ ++#ifdef CONFIG_IOCTL_CFG80211 ++ struct wireless_dev *rtw_wdev; ++#endif //CONFIG_IOCTL_CFG80211 ++ ++#endif //end of PLATFORM_LINUX ++ ++ int net_closed; ++ ++ u8 bFWReady; ++ u8 bReadPortCancel; ++ u8 bWritePortCancel; ++ u8 bRxRSSIDisplay; ++#ifdef CONFIG_AUTOSUSPEND ++ u8 bDisableAutosuspend; ++#endif ++#ifdef CONFIG_BR_EXT ++ _lock br_ext_lock; ++ //unsigned int macclone_completed; ++ struct nat25_network_db_entry *nethash[NAT25_HASH_SIZE]; ++ int pppoe_connection_in_progress; ++ unsigned char pppoe_addr[MACADDRLEN]; ++ unsigned char scdb_mac[MACADDRLEN]; ++ unsigned char scdb_ip[4]; ++ struct nat25_network_db_entry *scdb_entry; ++ unsigned char br_mac[MACADDRLEN]; ++ unsigned char br_ip[4]; ++ ++ struct br_ext_info ethBrExtInfo; ++#endif // CONFIG_BR_EXT ++ ++#ifdef CONFIG_INTEL_PROXIM ++ /* intel Proximity, should be alloc mem ++ * in intel Proximity module and can only ++ * be used in intel Proximity mode */ ++ struct proxim proximity; ++#endif //CONFIG_INTEL_PROXIM ++ ++#ifdef RTL8723A_SDIO_LOOPBACK ++ PLOOPBACKDATA ploopback; ++#endif ++ ++}; ++ ++__inline static u8 *myid(struct eeprom_priv *peepriv) ++{ ++ return (peepriv->mac_addr); ++} ++ ++ ++#endif //__DRV_TYPES_H__ ++ +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/include/drv_types_ce.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/include/drv_types_ce.h 2013-07-26 19:36:06.000000000 +0000 +@@ -0,0 +1,92 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef __DRV_TYPES_CE_H__ ++#define __DRV_TYPES_CE_H__ ++ ++#include ++#include ++ ++#include ++ ++#define MAX_ACTIVE_REG_PATH 256 ++ ++#define MAX_MCAST_LIST_NUM 32 ++ ++ ++ ++//for ioctl ++#define MAKE_DRIVER_VERSION(_MainVer,_MinorVer) ((((u32)(_MainVer))<<16)+_MinorVer) ++ ++#define NIC_HEADER_SIZE 14 //!< can be moved to typedef.h ++#define NIC_MAX_PACKET_SIZE 1514 //!< can be moved to typedef.h ++#define NIC_MAX_SEND_PACKETS 10 // max number of send packets the MiniportSendPackets function can accept, can be moved to typedef.h ++#define NIC_VENDOR_DRIVER_VERSION MAKE_DRIVER_VERSION(0,001) //!< can be moved to typedef.h ++#define NIC_MAX_PACKET_SIZE 1514 //!< can be moved to typedef.h ++ ++typedef struct _MP_REG_ENTRY ++{ ++ ++ NDIS_STRING RegName; // variable name text ++ BOOLEAN bRequired; // 1 -> required, 0 -> optional ++ ++ u8 Type; // NdisParameterInteger/NdisParameterHexInteger/NdisParameterStringle/NdisParameterMultiString ++ uint FieldOffset; // offset to MP_ADAPTER field ++ uint FieldSize; // size (in bytes) of the field ++ ++#ifdef UNDER_AMD64 ++ u64 Default; ++#else ++ u32 Default; // default value to use ++#endif ++ ++ u32 Min; // minimum value allowed ++ u32 Max; // maximum value allowed ++} MP_REG_ENTRY, *PMP_REG_ENTRY; ++ ++#ifdef CONFIG_USB_HCI ++typedef struct _USB_EXTENSION { ++ LPCUSB_FUNCS _lpUsbFuncs; ++ USB_HANDLE _hDevice; ++ PVOID pAdapter; ++ ++#if 0 ++ USB_ENDPOINT_DESCRIPTOR _endpACLIn; ++ USB_ENDPOINT_DESCRIPTOR _endpACLOutHigh; ++ USB_ENDPOINT_DESCRIPTOR _endpACLOutNormal; ++ ++ USB_PIPE pPipeIn; ++ USB_PIPE pPipeOutNormal; ++ USB_PIPE pPipeOutHigh; ++#endif ++ ++} USB_EXTENSION, *PUSB_EXTENSION; ++#endif ++ ++ ++typedef struct _OCTET_STRING{ ++ u8 *Octet; ++ u16 Length; ++} OCTET_STRING, *POCTET_STRING; ++ ++ ++ ++ ++ ++#endif +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/include/drv_types_linux.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/include/drv_types_linux.h 2013-07-26 19:36:06.000000000 +0000 +@@ -0,0 +1,25 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef __DRV_TYPES_LINUX_H__ ++#define __DRV_TYPES_LINUX_H__ ++ ++ ++#endif ++ +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/include/drv_types_xp.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/include/drv_types_xp.h 2013-07-26 19:36:06.000000000 +0000 +@@ -0,0 +1,95 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef __DRV_TYPES_XP_H__ ++#define __DRV_TYPES_XP_H__ ++ ++#include ++#include ++ ++ ++ ++#define MAX_MCAST_LIST_NUM 32 ++ ++ ++ ++//for ioctl ++#define MAKE_DRIVER_VERSION(_MainVer,_MinorVer) ((((u32)(_MainVer))<<16)+_MinorVer) ++ ++#define NIC_HEADER_SIZE 14 //!< can be moved to typedef.h ++#define NIC_MAX_PACKET_SIZE 1514 //!< can be moved to typedef.h ++#define NIC_MAX_SEND_PACKETS 10 // max number of send packets the MiniportSendPackets function can accept, can be moved to typedef.h ++#define NIC_VENDOR_DRIVER_VERSION MAKE_DRIVER_VERSION(0,001) //!< can be moved to typedef.h ++#define NIC_MAX_PACKET_SIZE 1514 //!< can be moved to typedef.h ++ ++ ++#undef ON_VISTA ++//added by Jackson ++#ifndef ON_VISTA ++// ++// Bus driver versions ++// ++ ++#define SDBUS_DRIVER_VERSION_1 0x100 ++#define SDBUS_DRIVER_VERSION_2 0x200 ++ ++#define SDP_FUNCTION_TYPE 4 ++#define SDP_BUS_DRIVER_VERSION 5 ++#define SDP_BUS_WIDTH 6 ++#define SDP_BUS_CLOCK 7 ++#define SDP_BUS_INTERFACE_CONTROL 8 ++#define SDP_HOST_BLOCK_LENGTH 9 ++#define SDP_FUNCTION_BLOCK_LENGTH 10 ++#define SDP_FN0_BLOCK_LENGTH 11 ++#define SDP_FUNCTION_INT_ENABLE 12 ++#endif ++ ++ ++typedef struct _MP_REG_ENTRY ++{ ++ ++ NDIS_STRING RegName; // variable name text ++ BOOLEAN bRequired; // 1 -> required, 0 -> optional ++ ++ u8 Type; // NdisParameterInteger/NdisParameterHexInteger/NdisParameterStringle/NdisParameterMultiString ++ uint FieldOffset; // offset to MP_ADAPTER field ++ uint FieldSize; // size (in bytes) of the field ++ ++#ifdef UNDER_AMD64 ++ u64 Default; ++#else ++ u32 Default; // default value to use ++#endif ++ ++ u32 Min; // minimum value allowed ++ u32 Max; // maximum value allowed ++} MP_REG_ENTRY, *PMP_REG_ENTRY; ++ ++ ++typedef struct _OCTET_STRING{ ++ u8 *Octet; ++ u16 Length; ++} OCTET_STRING, *POCTET_STRING; ++ ++ ++ ++ ++ ++#endif ++ +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/include/ethernet.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/include/ethernet.h 2013-07-26 19:36:06.000000000 +0000 +@@ -0,0 +1,41 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++/*! \file */ ++#ifndef __INC_ETHERNET_H ++#define __INC_ETHERNET_H ++ ++#define ETHERNET_ADDRESS_LENGTH 6 //!< Ethernet Address Length ++#define ETHERNET_HEADER_SIZE 14 //!< Ethernet Header Length ++#define LLC_HEADER_SIZE 6 //!< LLC Header Length ++#define TYPE_LENGTH_FIELD_SIZE 2 //!< Type/Length Size ++#define MINIMUM_ETHERNET_PACKET_SIZE 60 //!< Minimum Ethernet Packet Size ++#define MAXIMUM_ETHERNET_PACKET_SIZE 1514 //!< Maximum Ethernet Packet Size ++ ++#define RT_ETH_IS_MULTICAST(_pAddr) ((((UCHAR *)(_pAddr))[0]&0x01)!=0) //!< Is Multicast Address? ++#define RT_ETH_IS_BROADCAST(_pAddr) ( \ ++ ((UCHAR *)(_pAddr))[0]==0xff && \ ++ ((UCHAR *)(_pAddr))[1]==0xff && \ ++ ((UCHAR *)(_pAddr))[2]==0xff && \ ++ ((UCHAR *)(_pAddr))[3]==0xff && \ ++ ((UCHAR *)(_pAddr))[4]==0xff && \ ++ ((UCHAR *)(_pAddr))[5]==0xff ) //!< Is Broadcast Address? ++ ++ ++#endif // #ifndef __INC_ETHERNET_H +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/include/farray.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/include/farray.h 2013-07-26 19:36:06.000000000 +0000 +@@ -0,0 +1,31480 @@ ++unsigned char f_array[125912] = { ++0x12,0x87,0x09,0x10, ++0x30,0x00,0x00,0x00, ++0x08,0xF8,0x00,0x00, ++0x50,0xF3,0x00,0x00, ++0x30,0x00,0x00,0x00, ++0xB8,0xF1,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x10,0x27,0x17,0x41, ++0x87,0x12,0x12,0x01, ++0x00,0x00,0x12,0x06, ++0x00,0x00,0x00,0x00, ++0x00,0x07,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x01,0x01,0x00,0x01, ++0x01,0x01,0x00,0x00, ++0x01,0x00,0x01,0x00, ++0x00,0x00,0x01,0x01, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x7F,0x00,0x00,0x10, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x1F,0x00,0x00,0x10, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x25,0xB0,0x1A,0x3C, ++0x80,0x03,0x5A,0x37, ++0x00,0x80,0x1B,0x3C, ++0x80,0x00,0x7B,0x37, ++0x00,0x00,0x5B,0xAF, ++0x25,0xB0,0x1A,0x3C, ++0x18,0x03,0x5A,0x37, ++0x00,0x80,0x1B,0x3C, ++0x80,0x00,0x7B,0x37, ++0x00,0x00,0x5B,0xAF, ++0x01,0x80,0x1A,0x3C, ++0x90,0xEE,0x5A,0x27, ++0x08,0x00,0x40,0x03, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x04,0x00,0xA1,0xAF, ++0x08,0x00,0xA2,0xAF, ++0x0C,0x00,0xA3,0xAF, ++0x10,0x00,0xA4,0xAF, ++0x14,0x00,0xA5,0xAF, ++0x18,0x00,0xA6,0xAF, ++0x1C,0x00,0xA7,0xAF, ++0x20,0x00,0xA8,0xAF, ++0x24,0x00,0xA9,0xAF, ++0x28,0x00,0xAA,0xAF, ++0x2C,0x00,0xAB,0xAF, ++0x30,0x00,0xAC,0xAF, ++0x34,0x00,0xAD,0xAF, ++0x38,0x00,0xAE,0xAF, ++0x3C,0x00,0xAF,0xAF, ++0x12,0x40,0x00,0x00, ++0x10,0x48,0x00,0x00, ++0x00,0x70,0x0A,0x40, ++0x40,0x00,0xB0,0xAF, ++0x44,0x00,0xB1,0xAF, ++0x48,0x00,0xB2,0xAF, ++0x4C,0x00,0xB3,0xAF, ++0x50,0x00,0xB4,0xAF, ++0x54,0x00,0xB5,0xAF, ++0x58,0x00,0xB6,0xAF, ++0x5C,0x00,0xB7,0xAF, ++0x60,0x00,0xB8,0xAF, ++0x64,0x00,0xB9,0xAF, ++0x68,0x00,0xBC,0xAF, ++0x6C,0x00,0xBD,0xAF, ++0x70,0x00,0xBE,0xAF, ++0x74,0x00,0xBF,0xAF, ++0x78,0x00,0xA8,0xAF, ++0x7C,0x00,0xA9,0xAF, ++0x80,0x00,0xAA,0xAF, ++0x32,0x3B,0x00,0x08, ++0x21,0x20,0xA0,0x03, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x25,0xB0,0x05,0x3C, ++0x00,0x80,0x02,0x3C, ++0xE0,0xFF,0xBD,0x27, ++0x18,0x03,0xA3,0x34, ++0x00,0x03,0x42,0x24, ++0x18,0x00,0xBF,0xAF, ++0x14,0x00,0xB1,0xAF, ++0x10,0x00,0xB0,0xAF, ++0x00,0x00,0x62,0xAC, ++0x00,0x60,0x01,0x40, ++0x01,0x00,0x21,0x34, ++0x00,0x60,0x81,0x40, ++0x42,0xB0,0x02,0x3C, ++0x03,0x00,0x46,0x34, ++0x00,0x00,0xC3,0x90, ++0x00,0x00,0x00,0x00, ++0xFF,0x00,0x70,0x30, ++0x10,0x00,0x02,0x32, ++0x18,0x00,0x40,0x10, ++0x02,0x80,0x11,0x3C, ++0x30,0x1F,0x27,0x26, ++0x78,0x36,0xE4,0x94, ++0x10,0x00,0x02,0x24, ++0x00,0x00,0xC2,0xA0, ++0x08,0x00,0x80,0x10, ++0x1C,0x03,0xA3,0x34, ++0x7C,0x36,0xE2,0x94, ++0xB0,0x03,0xA4,0x34, ++0x00,0x00,0x62,0xAC, ++0x00,0x00,0x80,0xAC, ++0x78,0x36,0xE0,0xA4, ++0x7C,0x36,0xE0,0xA4, ++0x00,0x00,0x04,0x24, ++0x02,0x80,0x05,0x3C, ++0x02,0x80,0x06,0x3C, ++0x14,0x5E,0xA2,0x8C, ++0x18,0x5F,0xC3,0x8C, ++0x01,0x00,0x84,0x24, ++0x01,0x00,0x42,0x24, ++0x01,0x00,0x63,0x24, ++0x78,0x36,0xE4,0xA4, ++0x14,0x5E,0xA2,0xAC, ++0x18,0x5F,0xC3,0xAC, ++0x00,0x16,0x10,0x00, ++0x03,0x16,0x02,0x00, ++0x7B,0x00,0x40,0x04, ++0x42,0xB0,0x02,0x3C, ++0x00,0x60,0x01,0x40, ++0x01,0x00,0x21,0x34, ++0x01,0x00,0x21,0x38, ++0x00,0x60,0x81,0x40, ++0x40,0x00,0x02,0x32, ++0x16,0x00,0x40,0x10, ++0x30,0x1F,0x24,0x26, ++0x42,0xB0,0x0B,0x3C, ++0x03,0x00,0x62,0x35, ++0x40,0x00,0x03,0x24, ++0x00,0x00,0x43,0xA0, ++0x02,0x80,0x03,0x3C, ++0x12,0x5F,0x62,0x90, ++0x00,0x00,0x00,0x00, ++0x1A,0x00,0x40,0x10, ++0x02,0x80,0x04,0x3C, ++0x12,0x5F,0x60,0xA0, ++0x02,0x80,0x04,0x3C, ++0x0E,0x5F,0x83,0x90, ++0xFD,0xFF,0x02,0x24, ++0x24,0x18,0x62,0x00, ++0x0E,0x5F,0x83,0xA0, ++0x0E,0x5F,0x82,0x90, ++0x00,0x00,0x00,0x00, ++0x07,0x00,0x42,0x30, ++0x5D,0x00,0x40,0x10, ++0x02,0x80,0x02,0x3C, ++0x30,0x1F,0x24,0x26, ++0xE0,0x1B,0x83,0x94, ++0xDC,0x1B,0x85,0x94, ++0x18,0x00,0xBF,0x8F, ++0x14,0x00,0xB1,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x80,0x00,0x63,0x30, ++0x41,0xB0,0x02,0x3C, ++0x25,0x18,0x65,0x00, ++0x08,0x00,0x42,0x34, ++0x20,0x00,0xBD,0x27, ++0x00,0x00,0x43,0xA4, ++0x08,0x00,0xE0,0x03, ++0xDC,0x1B,0x83,0xA4, ++0xFA,0x5E,0x82,0x90, ++0x02,0x80,0x05,0x3C, ++0x01,0x00,0x42,0x24, ++0xFA,0x5E,0x82,0xA0, ++0x0E,0x5F,0xA3,0x90, ++0xEF,0xFF,0x02,0x24, ++0x24,0x18,0x62,0x00, ++0x0E,0x5F,0xA3,0xA0, ++0xFA,0x5E,0x82,0x90, ++0x00,0x00,0x00,0x00, ++0x02,0x00,0x42,0x2C, ++0x32,0x00,0x40,0x10, ++0x30,0x1F,0x23,0x26, ++0x25,0xB0,0x06,0x3C, ++0x84,0x00,0xC4,0x34, ++0x80,0x00,0xC6,0x34, ++0x00,0x00,0x82,0x8C, ++0x00,0x00,0xC4,0x8C, ++0x02,0x80,0x08,0x3C, ++0x21,0x10,0x00,0x00, ++0x1C,0x5F,0x06,0x8D, ++0x25,0x10,0x44,0x00, ++0x02,0x80,0x04,0x3C, ++0x20,0x5F,0x88,0x8C, ++0x24,0x5F,0x89,0x8C, ++0x00,0x00,0x65,0x91, ++0x21,0x10,0x46,0x00, ++0xFB,0xFF,0x04,0x24, ++0x24,0x28,0xA4,0x00, ++0x23,0x40,0x02,0x01, ++0x00,0x00,0x65,0xA1, ++0x04,0x00,0x00,0x11, ++0x01,0x00,0x06,0x24, ++0x80,0x10,0x08,0x00, ++0x21,0x10,0x48,0x00, ++0x80,0x30,0x02,0x00, ++0x01,0x00,0x04,0x24, ++0x8C,0x23,0x00,0x0C, ++0x21,0x28,0x00,0x00, ++0x42,0xB0,0x02,0x3C, ++0x22,0x00,0x04,0x24, ++0x03,0x00,0x42,0x34, ++0x00,0x00,0x44,0xA0, ++0x02,0x80,0x03,0x3C, ++0xF5,0x5E,0x64,0x90, ++0x01,0x00,0x05,0x24, ++0x64,0x31,0x00,0x0C, ++0xFF,0x00,0x84,0x30, ++0x30,0x1F,0x24,0x26, ++0xE0,0x1B,0x83,0x94, ++0xDC,0x1B,0x85,0x94, ++0x18,0x00,0xBF,0x8F, ++0x14,0x00,0xB1,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x80,0x00,0x63,0x30, ++0x41,0xB0,0x02,0x3C, ++0x25,0x18,0x65,0x00, ++0x08,0x00,0x42,0x34, ++0x20,0x00,0xBD,0x27, ++0x00,0x00,0x43,0xA4, ++0x08,0x00,0xE0,0x03, ++0xDC,0x1B,0x83,0xA4, ++0xB0,0x1B,0x62,0x94, ++0x00,0x00,0x00,0x00, ++0x00,0x01,0x42,0x30, ++0x16,0x00,0x40,0x10, ++0x02,0x80,0x02,0x3C, ++0x02,0x80,0x03,0x3C, ++0x15,0x5F,0x62,0x90, ++0x00,0x00,0x00,0x00, ++0xAB,0xFF,0x40,0x14, ++0x00,0x00,0x00,0x00, ++0x15,0x5F,0x62,0x90, ++0x00,0x00,0x00,0x00, ++0x01,0x00,0x42,0x24, ++0x15,0x5F,0x62,0xA0, ++0x0B,0x01,0x00,0x08, ++0x30,0x1F,0x24,0x26, ++0x0C,0x5F,0x40,0xA0, ++0x44,0x01,0x00,0x08, ++0x02,0x80,0x03,0x3C, ++0x80,0xFF,0x03,0x24, ++0x03,0x00,0x42,0x34, ++0x00,0x00,0x43,0xA0, ++0x9E,0x25,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0xEF,0x00,0x00,0x08, ++0x00,0x00,0x00,0x00, ++0x15,0x5F,0x40,0xA0, ++0x0B,0x01,0x00,0x08, ++0x30,0x1F,0x24,0x26, ++0xFF,0x00,0x84,0x30, ++0x0B,0x00,0x82,0x2C, ++0xFF,0xFF,0xE7,0x30, ++0x10,0x00,0xA8,0x93, ++0x19,0x00,0x40,0x10, ++0x21,0x18,0x00,0x00, ++0x02,0x80,0x03,0x3C, ++0x80,0x10,0x04,0x00, ++0xD8,0xE9,0x63,0x24, ++0x21,0x10,0x43,0x00, ++0x00,0x00,0x44,0x8C, ++0x00,0x00,0x00,0x00, ++0x08,0x00,0x80,0x00, ++0x00,0x00,0x00,0x00, ++0x43,0xB0,0x02,0x3C, ++0x78,0x00,0x44,0x34, ++0x07,0x00,0xE2,0x30, ++0x00,0x00,0x85,0xAC, ++0x04,0x00,0x86,0xAC, ++0x04,0x00,0x40,0x18, ++0x00,0x00,0x00,0x00, ++0xF8,0xFF,0xE2,0x30, ++0x08,0x00,0x42,0x24, ++0xFF,0xFF,0x47,0x30, ++0x21,0x10,0xE8,0x00, ++0x00,0x80,0x03,0x3C, ++0x08,0x00,0x82,0xAC, ++0x25,0x10,0x43,0x00, ++0x08,0x00,0x82,0xAC, ++0x01,0x00,0x03,0x24, ++0x08,0x00,0xE0,0x03, ++0x21,0x10,0x60,0x00, ++0x43,0xB0,0x02,0x3C, ++0x83,0x01,0x00,0x08, ++0x6C,0x00,0x44,0x34, ++0x43,0xB0,0x02,0x3C, ++0x83,0x01,0x00,0x08, ++0x60,0x00,0x44,0x34, ++0x43,0xB0,0x02,0x3C, ++0x83,0x01,0x00,0x08, ++0x54,0x00,0x44,0x34, ++0x43,0xB0,0x02,0x3C, ++0x83,0x01,0x00,0x08, ++0x48,0x00,0x44,0x34, ++0x43,0xB0,0x02,0x3C, ++0x83,0x01,0x00,0x08, ++0x3C,0x00,0x44,0x34, ++0x43,0xB0,0x02,0x3C, ++0x83,0x01,0x00,0x08, ++0x30,0x00,0x44,0x34, ++0x43,0xB0,0x02,0x3C, ++0x83,0x01,0x00,0x08, ++0x24,0x00,0x44,0x34, ++0x43,0xB0,0x02,0x3C, ++0x83,0x01,0x00,0x08, ++0x18,0x00,0x44,0x34, ++0x43,0xB0,0x02,0x3C, ++0x83,0x01,0x00,0x08, ++0x0C,0x00,0x44,0x34, ++0x83,0x01,0x00,0x08, ++0x43,0xB0,0x04,0x3C, ++0x00,0x80,0x03,0x3C, ++0x25,0xB0,0x02,0x3C, ++0x18,0x03,0x42,0x34, ++0xC0,0x06,0x63,0x24, ++0x00,0x00,0x43,0xAC, ++0x01,0x00,0x05,0x24, ++0x43,0xB0,0x02,0x3C, ++0x04,0x28,0x85,0x00, ++0x88,0x00,0x44,0x34, ++0x21,0x10,0x00,0x00, ++0x01,0x00,0x42,0x24, ++0xFF,0xFF,0x42,0x30, ++0x05,0x00,0x43,0x2C, ++0xFD,0xFF,0x60,0x14, ++0x01,0x00,0x42,0x24, ++0x00,0x00,0x82,0x94, ++0x00,0x00,0x00,0x00, ++0xFF,0xFF,0x42,0x30, ++0x24,0x10,0x45,0x00, ++0xF5,0xFF,0x40,0x1C, ++0x00,0x00,0x00,0x00, ++0x08,0x00,0xE0,0x03, ++0x00,0x00,0x00,0x00, ++0x25,0xB0,0x08,0x3C, ++0x00,0x80,0x02,0x3C, ++0xC8,0xFF,0xBD,0x27, ++0x18,0x03,0x03,0x35, ++0x1C,0x07,0x42,0x24, ++0x00,0x00,0x62,0xAC, ++0x30,0x00,0xB6,0xAF, ++0x28,0x00,0xB4,0xAF, ++0x24,0x00,0xB3,0xAF, ++0x1C,0x00,0xB1,0xAF, ++0x34,0x00,0xBF,0xAF, ++0x2C,0x00,0xB5,0xAF, ++0x20,0x00,0xB2,0xAF, ++0x18,0x00,0xB0,0xAF, ++0x0C,0x00,0xF2,0x84, ++0x08,0x00,0xF5,0x8C, ++0xFF,0x00,0xC6,0x30, ++0x00,0x01,0x02,0x24, ++0x23,0x10,0x46,0x00, ++0xFF,0xFF,0x51,0x30, ++0xD0,0x03,0x08,0x35, ++0xFF,0x00,0x96,0x30, ++0x00,0x00,0x12,0xAD, ++0x21,0xA0,0xA0,0x00, ++0x21,0x30,0xC5,0x00, ++0x00,0x00,0x15,0xAD, ++0x21,0x20,0xC0,0x02, ++0x21,0x28,0xA0,0x02, ++0x21,0x38,0x20,0x02, ++0x73,0x01,0x00,0x0C, ++0x10,0x00,0xA0,0xAF, ++0x23,0x18,0x51,0x02, ++0xFF,0xFF,0x82,0x32, ++0x00,0x94,0x03,0x00, ++0x03,0x94,0x12,0x00, ++0x09,0x02,0x00,0x08, ++0x02,0x9A,0x02,0x00, ++0x28,0xB0,0x03,0x3C, ++0xC0,0x10,0x13,0x00, ++0x21,0x10,0x43,0x00, ++0x00,0x00,0x44,0x90, ++0x25,0xB0,0x10,0x3C, ++0x20,0x10,0x02,0x3C, ++0xFF,0x00,0x93,0x30, ++0x00,0x22,0x13,0x00, ++0xFF,0xFF,0x43,0x32, ++0x01,0x01,0x45,0x2A, ++0x21,0xA0,0x82,0x00, ++0x21,0xA8,0xB1,0x02, ++0xD0,0x03,0x02,0x36, ++0x00,0x01,0x11,0x24, ++0x0B,0x88,0x65,0x00, ++0x21,0x20,0xC0,0x02, ++0x00,0x00,0x53,0xAC, ++0xB0,0x01,0x00,0x0C, ++0xB0,0x03,0x10,0x36, ++0x21,0x30,0x80,0x02, ++0x21,0x20,0xC0,0x02, ++0x21,0x28,0xA0,0x02, ++0x21,0x38,0x20,0x02, ++0x73,0x01,0x00,0x0C, ++0x10,0x00,0xA0,0xAF, ++0x23,0x18,0x51,0x02, ++0x00,0x94,0x03,0x00, ++0x03,0x94,0x12,0x00, ++0x00,0x00,0x12,0xAE, ++0xE2,0xFF,0x40,0x1E, ++0x00,0x00,0x00,0x00, ++0x34,0x00,0xBF,0x8F, ++0x30,0x00,0xB6,0x8F, ++0x2C,0x00,0xB5,0x8F, ++0x28,0x00,0xB4,0x8F, ++0x24,0x00,0xB3,0x8F, ++0x20,0x00,0xB2,0x8F, ++0x1C,0x00,0xB1,0x8F, ++0x18,0x00,0xB0,0x8F, ++0x08,0x00,0xE0,0x03, ++0x38,0x00,0xBD,0x27, ++0xD8,0xFF,0xBD,0x27, ++0x20,0x00,0xB2,0xAF, ++0x18,0x00,0xB0,0xAF, ++0x24,0x00,0xBF,0xAF, ++0x1C,0x00,0xB1,0xAF, ++0x04,0x00,0x8B,0x8C, ++0x21,0x80,0x80,0x00, ++0x08,0x00,0x84,0x8C, ++0x0E,0x00,0x07,0x96, ++0xFF,0xE0,0x02,0x3C, ++0x10,0x00,0x08,0x8E, ++0x1F,0x00,0x6A,0x31, ++0xFF,0xFF,0x42,0x34, ++0x24,0x20,0x82,0x00, ++0x00,0x1E,0x0A,0x00, ++0x25,0x48,0x83,0x00, ++0x21,0x90,0xA0,0x00, ++0x21,0x60,0xC0,0x00, ++0x10,0x01,0x00,0x05, ++0x07,0x00,0xE7,0x30, ++0x00,0x00,0x02,0x96, ++0x00,0x00,0x00,0x00, ++0xFD,0x0F,0x42,0x28, ++0xC0,0x00,0x40,0x14, ++0x02,0x80,0x11,0x3C, ++0xFF,0xDF,0x02,0x3C, ++0xFF,0xFF,0x42,0x34, ++0x24,0x48,0x22,0x01, ++0x1C,0x00,0x02,0x8E, ++0x00,0x40,0x03,0x3C, ++0x25,0x48,0x23,0x01, ++0x02,0x80,0x11,0x3C, ++0xC5,0x00,0x40,0x04, ++0x08,0x00,0x09,0xAE, ++0xC0,0x30,0x0A,0x00, ++0x21,0x10,0xCA,0x00, ++0x80,0x10,0x02,0x00, ++0x21,0x10,0x4A,0x00, ++0x80,0x10,0x02,0x00, ++0x30,0x1F,0x27,0x26, ++0x21,0x28,0x47,0x00, ++0x1C,0x24,0xA3,0x8C, ++0x01,0x00,0x0A,0x24, ++0x02,0x13,0x03,0x00, ++0x01,0x00,0x42,0x30, ++0xDB,0x00,0x4A,0x10, ++0x42,0x18,0x03,0x00, ++0x82,0x11,0x09,0x00, ++0x01,0x00,0x42,0x30, ++0x06,0x00,0x40,0x14, ++0x02,0x80,0x02,0x3C, ++0xC0,0xFF,0x02,0x24, ++0x24,0x10,0x22,0x01, ++0x04,0x00,0x49,0x34, ++0x08,0x00,0x09,0xAE, ++0x02,0x80,0x02,0x3C, ++0xE9,0x5D,0x43,0x90, ++0x00,0x00,0x00,0x00, ++0x6C,0x00,0x60,0x14, ++0x21,0x28,0xC7,0x00, ++0xE8,0x22,0xA4,0x8C, ++0x10,0x00,0x02,0x8E, ++0xBF,0xFF,0x03,0x24, ++0x40,0x00,0x84,0x30, ++0x24,0x10,0x43,0x00, ++0x25,0x40,0x44,0x00, ++0x10,0x00,0x08,0xAE, ++0xE8,0x22,0xA3,0x8C, ++0x7F,0xF8,0x02,0x24, ++0x24,0x10,0x02,0x01, ++0x80,0x07,0x63,0x30, ++0x42,0x27,0x09,0x00, ++0x25,0x40,0x43,0x00, ++0x01,0x00,0x84,0x30, ++0xE1,0x00,0x8A,0x10, ++0x10,0x00,0x08,0xAE, ++0x30,0x1F,0x24,0x26, ++0x21,0x20,0xC4,0x00, ++0xE8,0x22,0x83,0x8C, ++0xFF,0xF7,0x02,0x24, ++0x24,0x10,0x02,0x01, ++0x00,0x08,0x63,0x30, ++0x25,0x40,0x43,0x00, ++0x10,0x00,0x08,0xAE, ++0xE8,0x22,0x83,0x8C, ++0xFF,0xEF,0x02,0x24, ++0x24,0x10,0x02,0x01, ++0x00,0x10,0x63,0x30, ++0x30,0x1F,0x25,0x26, ++0x25,0x40,0x43,0x00, ++0x10,0x00,0x08,0xAE, ++0x21,0x30,0xC5,0x00, ++0xE8,0x22,0xC4,0x8C, ++0xFD,0xFF,0x02,0x3C, ++0x02,0x00,0x03,0x3C, ++0xFF,0xFF,0x42,0x34, ++0x24,0x20,0x83,0x00, ++0x24,0x10,0x02,0x01, ++0x25,0x40,0x44,0x00, ++0x10,0x00,0x08,0xAE, ++0xB0,0x1B,0xA3,0x94, ++0xFB,0xFF,0x02,0x3C, ++0xFF,0xFF,0x42,0x34, ++0xC2,0x1B,0x03,0x00, ++0x24,0x10,0x02,0x01, ++0x80,0x1C,0x03,0x00, ++0x25,0x40,0x43,0x00, ++0x10,0x00,0x08,0xAE, ++0x8F,0x3E,0xA3,0x90, ++0xE7,0xFF,0x02,0x3C, ++0xFF,0xFF,0x42,0x34, ++0x03,0x00,0x63,0x30, ++0x24,0x10,0x02,0x01, ++0xC0,0x1C,0x03,0x00, ++0x25,0x40,0x43,0x00, ++0x10,0x00,0x08,0xAE, ++0xE8,0x22,0xC4,0x8C, ++0xFF,0xFD,0x02,0x3C, ++0x00,0x02,0x03,0x3C, ++0xFF,0xFF,0x42,0x34, ++0x24,0x20,0x83,0x00, ++0x24,0x10,0x02,0x01, ++0x25,0x40,0x44,0x00, ++0x10,0x00,0x08,0xAE, ++0xB0,0x1B,0xA3,0x94, ++0xFF,0xFB,0x02,0x3C, ++0xFF,0xFF,0x42,0x34, ++0xC2,0x1B,0x03,0x00, ++0x24,0x10,0x02,0x01, ++0x80,0x1E,0x03,0x00, ++0x25,0x40,0x43,0x00, ++0x10,0x00,0x08,0xAE, ++0x8F,0x3E,0xA3,0x90, ++0xFF,0xE7,0x02,0x3C, ++0xFF,0xFF,0x42,0x34, ++0x03,0x00,0x63,0x30, ++0x24,0x10,0x02,0x01, ++0xC0,0x1E,0x03,0x00, ++0x25,0x40,0x43,0x00, ++0x10,0x00,0x08,0xAE, ++0xE8,0x22,0xC3,0x8C, ++0xC0,0xFF,0x02,0x24, ++0x24,0x10,0x02,0x01, ++0x3F,0x00,0x63,0x30, ++0x25,0x10,0x43,0x00, ++0x10,0x00,0x02,0xAE, ++0xEC,0x22,0xC5,0x8C, ++0x14,0x00,0x03,0x8E, ++0xFF,0xFF,0x04,0x3C, ++0xFF,0x7F,0x84,0x34, ++0x24,0x18,0x64,0x00, ++0x00,0x80,0xA5,0x30, ++0x25,0x18,0x65,0x00, ++0x14,0x00,0x03,0xAE, ++0xEC,0x22,0xC2,0x8C, ++0x24,0x18,0x64,0x00, ++0x00,0x80,0x42,0x30, ++0x25,0x18,0x62,0x00, ++0x14,0x00,0x03,0xAE, ++0xEE,0x22,0xC4,0x94, ++0xE0,0xFF,0x02,0x3C, ++0xFF,0xFF,0x42,0x34, ++0x1F,0x00,0x84,0x30, ++0x24,0x18,0x62,0x00, ++0x00,0x24,0x04,0x00, ++0x25,0x18,0x64,0x00, ++0x14,0x00,0x03,0xAE, ++0x02,0x00,0x02,0x92, ++0x02,0x24,0x0B,0x00, ++0x02,0x80,0x03,0x3C, ++0x21,0x10,0x4C,0x00, ++0xFF,0xFF,0x42,0x30, ++0x01,0x00,0x84,0x30, ++0x6A,0x00,0x80,0x10, ++0x25,0x30,0x43,0x00, ++0x30,0x1F,0x23,0x26, ++0xF8,0x1D,0x62,0x94, ++0x00,0x00,0x00,0x00, ++0xFF,0x0F,0x45,0x30, ++0x01,0x00,0x42,0x24, ++0xF8,0x1D,0x62,0xA4, ++0x0C,0x00,0x03,0x8E, ++0x00,0xF0,0x02,0x3C, ++0xFF,0xFF,0x42,0x34, ++0x00,0x24,0x05,0x00, ++0x24,0x18,0x62,0x00, ++0x25,0x18,0x64,0x00, ++0x0C,0x00,0x03,0xAE, ++0x16,0x00,0xC2,0x94, ++0x00,0x19,0x05,0x00, ++0x02,0x00,0x04,0x24, ++0x0F,0x00,0x42,0x30, ++0x25,0x10,0x43,0x00, ++0x16,0x00,0xC2,0xA4, ++0x21,0x28,0x80,0x01, ++0x21,0x30,0x40,0x02, ++0x80,0x00,0x07,0x24, ++0x01,0x00,0x02,0x24, ++0x73,0x01,0x00,0x0C, ++0x10,0x00,0xA2,0xAF, ++0x25,0xB0,0x02,0x3C, ++0xB0,0x03,0x42,0x34, ++0x00,0x00,0x52,0xAC, ++0xB0,0x01,0x00,0x0C, ++0x02,0x00,0x04,0x24, ++0x30,0x1F,0x24,0x26, ++0x00,0x00,0x03,0x96, ++0x94,0x3E,0x82,0x8C, ++0x24,0x00,0xBF,0x8F, ++0x20,0x00,0xB2,0x8F, ++0x1C,0x00,0xB1,0x8F, ++0x18,0x00,0xB0,0x8F, ++0x21,0x10,0x43,0x00, ++0x28,0x00,0xBD,0x27, ++0x08,0x00,0xE0,0x03, ++0x94,0x3E,0x82,0xAC, ++0x08,0x00,0x09,0xAE, ++0x30,0x1F,0x22,0x26, ++0x1A,0x3E,0x43,0x90, ++0xFF,0xDF,0x02,0x3C, ++0xFF,0xFF,0x42,0x34, ++0x07,0x18,0xE3,0x00, ++0x01,0x00,0x63,0x30, ++0x24,0x10,0x22,0x01, ++0x40,0x1F,0x03,0x00, ++0x25,0x48,0x43,0x00, ++0x1C,0x00,0x02,0x8E, ++0x00,0x00,0x00,0x00, ++0x3D,0xFF,0x41,0x04, ++0x08,0x00,0x09,0xAE, ++0x1E,0x00,0x02,0x92, ++0x04,0x00,0x03,0x24, ++0x21,0x30,0x50,0x00, ++0x00,0x00,0xC4,0x90, ++0x00,0x00,0x00,0x00, ++0xFF,0x00,0x82,0x30, ++0x02,0x29,0x02,0x00, ++0x50,0x00,0xA3,0x10, ++0x06,0x00,0x02,0x24, ++0x32,0xFF,0xA2,0x14, ++0x00,0x00,0x00,0x00, ++0x1A,0x00,0x02,0x96, ++0x00,0x00,0x00,0x00, ++0x39,0x00,0xC2,0xA0, ++0x1E,0x00,0x03,0x92, ++0x1A,0x00,0x02,0x96, ++0x21,0x18,0x70,0x00, ++0x03,0x12,0x02,0x00, ++0x38,0x00,0x62,0xA0, ++0x04,0x00,0x0B,0x8E, ++0x08,0x00,0x09,0x8E, ++0xC0,0x30,0x0A,0x00, ++0x21,0x10,0xCA,0x00, ++0x80,0x10,0x02,0x00, ++0x21,0x10,0x4A,0x00, ++0x80,0x10,0x02,0x00, ++0x30,0x1F,0x27,0x26, ++0x21,0x28,0x47,0x00, ++0x1C,0x24,0xA3,0x8C, ++0x01,0x00,0x0A,0x24, ++0x02,0x13,0x03,0x00, ++0x01,0x00,0x42,0x30, ++0x29,0xFF,0x4A,0x14, ++0x82,0x11,0x09,0x00, ++0x42,0x18,0x03,0x00, ++0x7F,0xFF,0x02,0x24, ++0x24,0x10,0x22,0x01, ++0x80,0x00,0x63,0x30, ++0x25,0x48,0x43,0x00, ++0x08,0x00,0x09,0xAE, ++0x1C,0x24,0xA3,0x8C, ++0x10,0x00,0x04,0x8E, ++0xFF,0xFF,0x02,0x3C, ++0x07,0x00,0x63,0x30, ++0xFF,0x1F,0x42,0x34, ++0x24,0x20,0x82,0x00, ++0x40,0x1B,0x03,0x00, ++0x25,0x40,0x83,0x00, ++0x44,0x02,0x00,0x08, ++0x10,0x00,0x08,0xAE, ++0x0E,0x00,0x02,0x96, ++0x30,0x1F,0x23,0x26, ++0x07,0x00,0x42,0x30, ++0x40,0x10,0x02,0x00, ++0x21,0x10,0x43,0x00, ++0xE8,0x1D,0x44,0x94, ++0x00,0x00,0x00,0x00, ++0x01,0x00,0x83,0x24, ++0xFF,0x0F,0x85,0x30, ++0xCA,0x02,0x00,0x08, ++0xE8,0x1D,0x43,0xA4, ++0x14,0x00,0x02,0x8E, ++0x00,0x00,0x00,0x00, ++0x42,0x12,0x02,0x00, ++0x3F,0x00,0x42,0x30, ++0x0C,0x00,0x42,0x28, ++0xF1,0xFE,0x40,0x14, ++0xFF,0xDF,0x02,0x3C, ++0x29,0x02,0x00,0x08, ++0x00,0x00,0x00,0x00, ++0x02,0x80,0x02,0x3C, ++0xE6,0x5D,0x43,0x90, ++0x00,0x00,0x00,0x00, ++0x1D,0xFF,0x64,0x14, ++0x30,0x1F,0x24,0x26, ++0x90,0x3E,0xE2,0x90, ++0xFF,0xF7,0x03,0x24, ++0x24,0x18,0x03,0x01, ++0x01,0x00,0x42,0x30, ++0xC0,0x12,0x02,0x00, ++0x25,0x40,0x62,0x00, ++0x10,0x00,0x08,0xAE, ++0x91,0x3E,0xE2,0x90, ++0xFF,0xEF,0x03,0x24, ++0x24,0x18,0x03,0x01, ++0x01,0x00,0x42,0x30, ++0x6D,0x02,0x00,0x08, ++0x00,0x13,0x02,0x00, ++0x1A,0x00,0x05,0x96, ++0x0F,0x00,0x84,0x30, ++0x80,0x20,0x04,0x00, ++0x21,0x18,0xC4,0x00, ++0x11,0x00,0x65,0xA0, ++0x1E,0x00,0x02,0x92, ++0x1A,0x00,0x03,0x96, ++0x21,0x10,0x50,0x00, ++0x21,0x10,0x44,0x00, ++0x03,0x1A,0x03,0x00, ++0x10,0x00,0x43,0xA0, ++0x04,0x00,0x0B,0x8E, ++0x08,0x00,0x09,0x8E, ++0x11,0x03,0x00,0x08, ++0xC0,0x30,0x0A,0x00, ++0x00,0x80,0x03,0x3C, ++0x25,0xB0,0x02,0x3C, ++0x88,0x0D,0x63,0x24, ++0x18,0x03,0x42,0x34, ++0x00,0x00,0x43,0xAC, ++0x08,0x00,0xE0,0x03, ++0x00,0x00,0x00,0x00, ++0x25,0xB0,0x04,0x3C, ++0x00,0x80,0x02,0x3C, ++0xC0,0xFF,0xBD,0x27, ++0x18,0x03,0x83,0x34, ++0xA4,0x0D,0x42,0x24, ++0x3C,0x00,0xBF,0xAF, ++0x38,0x00,0xBE,0xAF, ++0x34,0x00,0xB7,0xAF, ++0x30,0x00,0xB6,0xAF, ++0x2C,0x00,0xB5,0xAF, ++0x28,0x00,0xB4,0xAF, ++0x24,0x00,0xB3,0xAF, ++0x20,0x00,0xB2,0xAF, ++0x1C,0x00,0xB1,0xAF, ++0x18,0x00,0xB0,0xAF, ++0x00,0x00,0x62,0xAC, ++0x00,0x60,0x01,0x40, ++0x01,0x00,0x21,0x34, ++0x00,0x60,0x81,0x40, ++0x02,0x80,0x02,0x3C, ++0xB0,0x03,0x9E,0x34, ++0x98,0x03,0x00,0x08, ++0x30,0x1F,0x55,0x24, ++0x08,0x00,0x04,0xAE, ++0x14,0x37,0x46,0x8E, ++0x21,0x28,0x60,0x02, ++0x80,0x00,0x07,0x24, ++0x01,0x00,0x04,0x24, ++0x01,0x00,0x14,0x24, ++0x73,0x01,0x00,0x0C, ++0x10,0x00,0xB4,0xAF, ++0x14,0x37,0x43,0x8E, ++0x01,0x00,0x04,0x24, ++0x00,0x00,0xC3,0xAE, ++0xB0,0x01,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x2A,0x1C,0x42,0x92, ++0x00,0x00,0x00,0x00, ++0x5F,0x00,0x40,0x10, ++0x2A,0xB0,0x02,0x3C, ++0x09,0x00,0x42,0x34, ++0x02,0x00,0x03,0x24, ++0x00,0x00,0x54,0xA0, ++0x00,0x00,0x43,0xA0, ++0xFF,0x00,0x03,0x24, ++0x74,0x00,0x23,0x12, ++0x00,0x00,0x00,0x00, ++0x10,0x37,0xA2,0x8E, ++0x7C,0x37,0xB3,0x8E, ++0x01,0x00,0x04,0x24, ++0x00,0x00,0xC2,0xAF, ++0x14,0x37,0xA2,0xAE, ++0x00,0x00,0xD3,0xAF, ++0xB0,0x01,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x7C,0x37,0xA4,0x8E, ++0x80,0x37,0xA3,0x8E, ++0x02,0x80,0x02,0x3C, ++0x04,0xEA,0x42,0x24, ++0x00,0x00,0x52,0x8C, ++0x80,0x00,0x84,0x24, ++0xFF,0x00,0x62,0x24, ++0x2B,0x10,0x44,0x00, ++0x0A,0x18,0x82,0x00, ++0x7C,0x37,0xA3,0xAE, ++0x02,0x80,0x03,0x3C, ++0x08,0xEA,0x63,0x24, ++0x7C,0x37,0x42,0x8E, ++0x00,0x00,0x76,0x8C, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0xC2,0xAE, ++0x02,0x80,0x17,0x3C, ++0xFF,0xFF,0x62,0x32, ++0x25,0x80,0x57,0x00, ++0x00,0x00,0xD0,0xAE, ++0x0C,0x00,0x02,0x92, ++0x21,0x28,0x00,0x00, ++0x00,0x00,0xC2,0xAE, ++0x02,0x00,0x04,0x92, ++0x00,0x00,0x00,0x00, ++0x21,0x20,0x93,0x00, ++0xFF,0xFF,0x84,0x30, ++0xFB,0x60,0x00,0x0C, ++0x25,0x20,0x97,0x00, ++0x0C,0x00,0x11,0x92, ++0x20,0x10,0x02,0x3C, ++0x01,0x00,0x04,0x24, ++0x00,0x1A,0x11,0x00, ++0x21,0x18,0x62,0x00, ++0xFF,0x00,0x02,0x24, ++0x21,0x30,0x60,0x00, ++0x06,0x00,0x22,0x12, ++0x80,0x00,0x07,0x24, ++0x7C,0x37,0x45,0x8E, ++0x10,0x37,0x43,0xAE, ++0xB4,0x36,0x51,0xA2, ++0x73,0x01,0x00,0x0C, ++0x10,0x00,0xA0,0xAF, ++0x04,0x00,0x04,0x8E, ++0x08,0x00,0x03,0x8E, ++0xFF,0xE0,0x02,0x3C, ++0xFF,0xFF,0x42,0x34, ++0x1F,0x00,0x84,0x30, ++0x24,0x18,0x62,0x00, ++0x00,0x26,0x04,0x00, ++0xFF,0xDF,0x02,0x3C, ++0x25,0x18,0x64,0x00, ++0xFF,0xFF,0x42,0x34, ++0x24,0x18,0x62,0x00, ++0x00,0x40,0x04,0x3C, ++0x25,0x18,0x64,0x00, ++0xC0,0xFF,0x05,0x24, ++0x82,0x11,0x03,0x00, ++0x24,0x20,0x65,0x00, ++0x01,0x00,0x42,0x30, ++0xA3,0xFF,0x40,0x10, ++0x04,0x00,0x84,0x34, ++0x08,0x00,0x03,0xAE, ++0x14,0x37,0x46,0x8E, ++0x21,0x28,0x60,0x02, ++0x80,0x00,0x07,0x24, ++0x01,0x00,0x04,0x24, ++0x01,0x00,0x14,0x24, ++0x73,0x01,0x00,0x0C, ++0x10,0x00,0xB4,0xAF, ++0x14,0x37,0x43,0x8E, ++0x01,0x00,0x04,0x24, ++0x00,0x00,0xC3,0xAE, ++0xB0,0x01,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x2A,0x1C,0x42,0x92, ++0x00,0x00,0x00,0x00, ++0xA3,0xFF,0x40,0x14, ++0x2A,0xB0,0x02,0x3C, ++0x00,0x60,0x01,0x40, ++0x01,0x00,0x21,0x34, ++0x01,0x00,0x21,0x38, ++0x00,0x60,0x81,0x40, ++0x2A,0x1C,0x54,0xA2, ++0x02,0x00,0x02,0x92, ++0x00,0x00,0x00,0x00, ++0x21,0x10,0x53,0x00, ++0xFF,0xFF,0x42,0x30, ++0x25,0x10,0x57,0x00, ++0x02,0x00,0x43,0x94, ++0x00,0x00,0x00,0x00, ++0xFF,0x00,0x64,0x30, ++0x00,0xC0,0x84,0x24, ++0xFF,0xFF,0x84,0x30, ++0xC2,0x34,0x00,0x0C, ++0x2B,0x1C,0x43,0xA2, ++0x00,0x60,0x01,0x40, ++0x01,0x00,0x21,0x34, ++0x00,0x60,0x81,0x40, ++0x2A,0xB0,0x02,0x3C, ++0x09,0x00,0x42,0x34, ++0x02,0x00,0x03,0x24, ++0x00,0x00,0x54,0xA0, ++0x00,0x00,0x43,0xA0, ++0xFF,0x00,0x03,0x24, ++0x8E,0xFF,0x23,0x16, ++0x00,0x00,0x00,0x00, ++0x00,0x60,0x01,0x40, ++0x01,0x00,0x21,0x34, ++0x01,0x00,0x21,0x38, ++0x00,0x60,0x81,0x40, ++0x02,0x80,0x03,0x3C, ++0x30,0x1F,0x62,0x24, ++0xD0,0x1B,0x43,0x8C, ++0x3C,0x00,0xBF,0x8F, ++0x38,0x00,0xBE,0x8F, ++0x34,0x00,0xB7,0x8F, ++0x30,0x00,0xB6,0x8F, ++0x2C,0x00,0xB5,0x8F, ++0x28,0x00,0xB4,0x8F, ++0x24,0x00,0xB3,0x8F, ++0x20,0x00,0xB2,0x8F, ++0x1C,0x00,0xB1,0x8F, ++0x18,0x00,0xB0,0x8F, ++0x00,0x38,0x63,0x34, ++0x41,0xB0,0x04,0x3C, ++0x40,0x00,0xBD,0x27, ++0x00,0x00,0x83,0xAC, ++0x08,0x00,0xE0,0x03, ++0xD0,0x1B,0x43,0xAC, ++0x00,0x80,0x03,0x3C, ++0x25,0xB0,0x02,0x3C, ++0x88,0x10,0x63,0x24, ++0x18,0x03,0x42,0x34, ++0x00,0x00,0x43,0xAC, ++0x08,0x00,0xE0,0x03, ++0x00,0x00,0x00,0x00, ++0xC0,0xFF,0xBD,0x27, ++0x34,0x00,0xB7,0xAF, ++0x3C,0x00,0xBF,0xAF, ++0x38,0x00,0xBE,0xAF, ++0x30,0x00,0xB6,0xAF, ++0x2C,0x00,0xB5,0xAF, ++0x28,0x00,0xB4,0xAF, ++0x24,0x00,0xB3,0xAF, ++0x20,0x00,0xB2,0xAF, ++0x1C,0x00,0xB1,0xAF, ++0x18,0x00,0xB0,0xAF, ++0x02,0x80,0x06,0x3C, ++0xCC,0x5E,0xC5,0x90, ++0x00,0x80,0x03,0x3C, ++0x25,0xB0,0x02,0x3C, ++0x18,0x03,0x42,0x34, ++0xA4,0x10,0x63,0x24, ++0x40,0x00,0xA4,0x30, ++0x00,0x00,0x43,0xAC, ++0x21,0xB8,0x00,0x00, ++0x03,0x00,0x80,0x10, ++0x7F,0x00,0xA2,0x30, ++0xBF,0x00,0xA2,0x30, ++0x01,0x00,0x17,0x24, ++0xCC,0x5E,0xC2,0xA0, ++0x00,0x60,0x01,0x40, ++0x01,0x00,0x21,0x34, ++0x00,0x60,0x81,0x40, ++0x02,0x80,0x1E,0x3C, ++0x25,0xB0,0x02,0x3C, ++0x30,0x1F,0xD3,0x27, ++0xB0,0x03,0x55,0x34, ++0x6A,0x04,0x00,0x08, ++0x02,0x80,0x16,0x3C, ++0x90,0x36,0x91,0xA2, ++0x30,0x1F,0xC2,0x27, ++0xC8,0x36,0x46,0x8C, ++0x34,0x37,0x45,0x8C, ++0x03,0x00,0x04,0x24, ++0x80,0x00,0x07,0x24, ++0x73,0x01,0x00,0x0C, ++0x10,0x00,0xA0,0xAF, ++0x30,0x1F,0xD4,0x27, ++0xCC,0x36,0x85,0x8E, ++0x21,0x20,0x00,0x02, ++0x15,0x02,0x00,0x0C, ++0x21,0x30,0x40,0x02, ++0x2A,0xB0,0x07,0x3C, ++0x0D,0x00,0xE2,0x34, ++0x04,0x00,0x43,0x24, ++0x0B,0x10,0x77,0x00, ++0x01,0x00,0x04,0x24, ++0x02,0x00,0x03,0x24, ++0x00,0x00,0x44,0xA0, ++0x00,0x00,0x43,0xA0, ++0x1A,0x5E,0xC4,0x96, ++0x25,0xB0,0x06,0x3C, ++0x66,0x03,0xC5,0x34, ++0x01,0x00,0x84,0x24, ++0x1A,0x5E,0xC4,0xA6, ++0x1A,0x5E,0xC2,0x96, ++0xFF,0x00,0x03,0x24, ++0x00,0x00,0xA2,0xA4, ++0x2F,0x00,0x23,0x12, ++0x00,0x00,0x00,0x00, ++0xC8,0x36,0x62,0x8E, ++0x34,0x37,0x72,0x8E, ++0x03,0x00,0x04,0x24, ++0x00,0x00,0xA2,0xAE, ++0xCC,0x36,0x62,0xAE, ++0x00,0x00,0xB2,0xAE, ++0xB0,0x01,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x34,0x37,0x64,0x8E, ++0x38,0x37,0x63,0x8E, ++0x02,0x80,0x02,0x3C, ++0x0C,0xEA,0x42,0x24, ++0x00,0x00,0x54,0x8C, ++0x80,0x00,0x84,0x24, ++0xFF,0x00,0x62,0x24, ++0x2B,0x10,0x44,0x00, ++0x0A,0x18,0x82,0x00, ++0x34,0x37,0x63,0xAE, ++0x34,0x37,0x82,0x8E, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0xA2,0xAE, ++0x02,0x80,0x03,0x3C, ++0xFF,0xFF,0x42,0x32, ++0x25,0x80,0x43,0x00, ++0x00,0x00,0xB0,0xAE, ++0x0C,0x00,0x02,0x92, ++0x01,0x00,0x05,0x24, ++0x00,0x00,0xA2,0xAE, ++0x02,0x00,0x04,0x92, ++0x00,0x00,0x00,0x00, ++0x21,0x20,0x92,0x00, ++0xFF,0xFF,0x84,0x30, ++0xFB,0x60,0x00,0x0C, ++0x25,0x20,0x83,0x00, ++0x0C,0x00,0x11,0x92, ++0x20,0x10,0x02,0x3C, ++0xFF,0x00,0x03,0x24, ++0x00,0x22,0x11,0x00, ++0xC2,0xFF,0x23,0x12, ++0x21,0x20,0x82,0x00, ++0xB8,0xFF,0xE0,0x16, ++0xC8,0x36,0x84,0xAE, ++0x02,0x80,0x02,0x3C, ++0x30,0x1F,0x42,0x24, ++0x4C,0x04,0x00,0x08, ++0x8C,0x36,0x51,0xA0, ++0x21,0x00,0xE0,0x12, ++0x40,0x00,0xE4,0x34, ++0x90,0x36,0x83,0x92, ++0x41,0x00,0xE4,0x34, ++0xB0,0x03,0xC5,0x34, ++0x00,0x00,0x83,0xA0, ++0x00,0x00,0xA3,0xAC, ++0x00,0x60,0x01,0x40, ++0x01,0x00,0x21,0x34, ++0x00,0x60,0x81,0x40, ++0x00,0x60,0x01,0x40, ++0x01,0x00,0x21,0x34, ++0x01,0x00,0x21,0x38, ++0x00,0x60,0x81,0x40, ++0x30,0x1F,0xC5,0x27, ++0xD0,0x1B,0xA4,0x8C, ++0x01,0x00,0x02,0x3C, ++0x3C,0x00,0xBF,0x8F, ++0x38,0x00,0xBE,0x8F, ++0x34,0x00,0xB7,0x8F, ++0x30,0x00,0xB6,0x8F, ++0x2C,0x00,0xB5,0x8F, ++0x28,0x00,0xB4,0x8F, ++0x24,0x00,0xB3,0x8F, ++0x20,0x00,0xB2,0x8F, ++0x1C,0x00,0xB1,0x8F, ++0x18,0x00,0xB0,0x8F, ++0x00,0x80,0x42,0x34, ++0x25,0x20,0x82,0x00, ++0x41,0xB0,0x03,0x3C, ++0x40,0x00,0xBD,0x27, ++0x00,0x00,0x64,0xAC, ++0x08,0x00,0xE0,0x03, ++0xD0,0x1B,0xA4,0xAC, ++0x8C,0x36,0x83,0x92, ++0xB0,0x03,0xC5,0x34, ++0x00,0x00,0x83,0xA0, ++0x00,0x00,0xA3,0xAC, ++0x00,0x60,0x01,0x40, ++0x01,0x00,0x21,0x34, ++0x00,0x60,0x81,0x40, ++0x00,0x60,0x01,0x40, ++0x01,0x00,0x21,0x34, ++0x01,0x00,0x21,0x38, ++0x00,0x60,0x81,0x40, ++0x30,0x1F,0xC5,0x27, ++0xD0,0x1B,0xA4,0x8C, ++0x01,0x00,0x02,0x3C, ++0x3C,0x00,0xBF,0x8F, ++0x38,0x00,0xBE,0x8F, ++0x34,0x00,0xB7,0x8F, ++0x30,0x00,0xB6,0x8F, ++0x2C,0x00,0xB5,0x8F, ++0x28,0x00,0xB4,0x8F, ++0x24,0x00,0xB3,0x8F, ++0x20,0x00,0xB2,0x8F, ++0x1C,0x00,0xB1,0x8F, ++0x18,0x00,0xB0,0x8F, ++0x00,0x80,0x42,0x34, ++0x25,0x20,0x82,0x00, ++0x41,0xB0,0x03,0x3C, ++0x40,0x00,0xBD,0x27, ++0x00,0x00,0x64,0xAC, ++0x08,0x00,0xE0,0x03, ++0xD0,0x1B,0xA4,0xAC, ++0xC0,0xFF,0xBD,0x27, ++0x34,0x00,0xB7,0xAF, ++0x3C,0x00,0xBF,0xAF, ++0x38,0x00,0xBE,0xAF, ++0x30,0x00,0xB6,0xAF, ++0x2C,0x00,0xB5,0xAF, ++0x28,0x00,0xB4,0xAF, ++0x24,0x00,0xB3,0xAF, ++0x20,0x00,0xB2,0xAF, ++0x1C,0x00,0xB1,0xAF, ++0x18,0x00,0xB0,0xAF, ++0x02,0x80,0x06,0x3C, ++0xCC,0x5E,0xC5,0x90, ++0x00,0x80,0x03,0x3C, ++0x25,0xB0,0x02,0x3C, ++0x18,0x03,0x42,0x34, ++0x64,0x13,0x63,0x24, ++0x10,0x00,0xA4,0x30, ++0x00,0x00,0x43,0xAC, ++0x21,0xB8,0x00,0x00, ++0x03,0x00,0x80,0x10, ++0xDF,0x00,0xA2,0x30, ++0xEF,0x00,0xA2,0x30, ++0x01,0x00,0x17,0x24, ++0xCC,0x5E,0xC2,0xA0, ++0xCC,0x5E,0xC3,0x90, ++0x25,0xB0,0x02,0x3C, ++0xB0,0x03,0x42,0x34, ++0x00,0x00,0x43,0xAC, ++0x00,0x00,0x43,0xAC, ++0x00,0x60,0x01,0x40, ++0x01,0x00,0x21,0x34, ++0x00,0x60,0x81,0x40, ++0x02,0x80,0x1E,0x3C, ++0x30,0x1F,0xD3,0x27, ++0x21,0xA8,0x40,0x00, ++0x1E,0x05,0x00,0x08, ++0x02,0x80,0x16,0x3C, ++0x98,0x36,0x91,0xA2, ++0x30,0x1F,0xC2,0x27, ++0xD4,0x36,0x46,0x8C, ++0x40,0x37,0x45,0x8C, ++0x04,0x00,0x04,0x24, ++0x80,0x00,0x07,0x24, ++0x73,0x01,0x00,0x0C, ++0x10,0x00,0xA0,0xAF, ++0x30,0x1F,0xD4,0x27, ++0xD8,0x36,0x85,0x8E, ++0x21,0x20,0x00,0x02, ++0x15,0x02,0x00,0x0C, ++0x21,0x30,0x40,0x02, ++0x2A,0xB0,0x07,0x3C, ++0x15,0x00,0xE2,0x34, ++0x04,0x00,0x43,0x24, ++0x0B,0x10,0x77,0x00, ++0x01,0x00,0x04,0x24, ++0x02,0x00,0x03,0x24, ++0x00,0x00,0x44,0xA0, ++0x00,0x00,0x43,0xA0, ++0x1A,0x5E,0xC4,0x96, ++0x25,0xB0,0x06,0x3C, ++0x66,0x03,0xC5,0x34, ++0x01,0x00,0x84,0x24, ++0x1A,0x5E,0xC4,0xA6, ++0x1A,0x5E,0xC2,0x96, ++0xFF,0x00,0x03,0x24, ++0x00,0x00,0xA2,0xA4, ++0x2F,0x00,0x23,0x12, ++0x00,0x00,0x00,0x00, ++0xD4,0x36,0x62,0x8E, ++0x40,0x37,0x72,0x8E, ++0x04,0x00,0x04,0x24, ++0x00,0x00,0xA2,0xAE, ++0xD8,0x36,0x62,0xAE, ++0x00,0x00,0xB2,0xAE, ++0xB0,0x01,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x40,0x37,0x64,0x8E, ++0x44,0x37,0x63,0x8E, ++0x02,0x80,0x02,0x3C, ++0x10,0xEA,0x42,0x24, ++0x00,0x00,0x54,0x8C, ++0x80,0x00,0x84,0x24, ++0xFF,0x00,0x62,0x24, ++0x2B,0x10,0x44,0x00, ++0x0A,0x18,0x82,0x00, ++0x40,0x37,0x63,0xAE, ++0x40,0x37,0x82,0x8E, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0xA2,0xAE, ++0x02,0x80,0x03,0x3C, ++0xFF,0xFF,0x42,0x32, ++0x25,0x80,0x43,0x00, ++0x00,0x00,0xB0,0xAE, ++0x0C,0x00,0x02,0x92, ++0x02,0x00,0x05,0x24, ++0x00,0x00,0xA2,0xAE, ++0x02,0x00,0x04,0x92, ++0x00,0x00,0x00,0x00, ++0x21,0x20,0x92,0x00, ++0xFF,0xFF,0x84,0x30, ++0xFB,0x60,0x00,0x0C, ++0x25,0x20,0x83,0x00, ++0x0C,0x00,0x11,0x92, ++0x20,0x10,0x02,0x3C, ++0xFF,0x00,0x03,0x24, ++0x00,0x22,0x11,0x00, ++0xC2,0xFF,0x23,0x12, ++0x21,0x20,0x82,0x00, ++0xB8,0xFF,0xE0,0x16, ++0xD4,0x36,0x84,0xAE, ++0x02,0x80,0x02,0x3C, ++0x30,0x1F,0x42,0x24, ++0x00,0x05,0x00,0x08, ++0x94,0x36,0x51,0xA0, ++0x20,0x00,0xE0,0x12, ++0x42,0x00,0xE4,0x34, ++0x98,0x36,0x83,0x92, ++0x43,0x00,0xE4,0x34, ++0xB0,0x03,0xC5,0x34, ++0x00,0x00,0x83,0xA0, ++0x00,0x00,0xA3,0xAC, ++0x00,0x60,0x01,0x40, ++0x01,0x00,0x21,0x34, ++0x00,0x60,0x81,0x40, ++0x00,0x60,0x01,0x40, ++0x01,0x00,0x21,0x34, ++0x01,0x00,0x21,0x38, ++0x00,0x60,0x81,0x40, ++0x30,0x1F,0xC5,0x27, ++0xD0,0x1B,0xA2,0x8C, ++0x3C,0x00,0xBF,0x8F, ++0x38,0x00,0xBE,0x8F, ++0x34,0x00,0xB7,0x8F, ++0x30,0x00,0xB6,0x8F, ++0x2C,0x00,0xB5,0x8F, ++0x28,0x00,0xB4,0x8F, ++0x24,0x00,0xB3,0x8F, ++0x20,0x00,0xB2,0x8F, ++0x1C,0x00,0xB1,0x8F, ++0x18,0x00,0xB0,0x8F, ++0x06,0x00,0x03,0x3C, ++0x25,0x10,0x43,0x00, ++0x41,0xB0,0x04,0x3C, ++0x40,0x00,0xBD,0x27, ++0x00,0x00,0x82,0xAC, ++0x08,0x00,0xE0,0x03, ++0xD0,0x1B,0xA2,0xAC, ++0x94,0x36,0x83,0x92, ++0xB0,0x03,0xC5,0x34, ++0x00,0x00,0x83,0xA0, ++0x00,0x00,0xA3,0xAC, ++0x00,0x60,0x01,0x40, ++0x01,0x00,0x21,0x34, ++0x00,0x60,0x81,0x40, ++0x00,0x60,0x01,0x40, ++0x01,0x00,0x21,0x34, ++0x01,0x00,0x21,0x38, ++0x00,0x60,0x81,0x40, ++0x30,0x1F,0xC5,0x27, ++0xD0,0x1B,0xA2,0x8C, ++0x3C,0x00,0xBF,0x8F, ++0x38,0x00,0xBE,0x8F, ++0x34,0x00,0xB7,0x8F, ++0x30,0x00,0xB6,0x8F, ++0x2C,0x00,0xB5,0x8F, ++0x28,0x00,0xB4,0x8F, ++0x24,0x00,0xB3,0x8F, ++0x20,0x00,0xB2,0x8F, ++0x1C,0x00,0xB1,0x8F, ++0x18,0x00,0xB0,0x8F, ++0x06,0x00,0x03,0x3C, ++0x25,0x10,0x43,0x00, ++0x41,0xB0,0x04,0x3C, ++0x40,0x00,0xBD,0x27, ++0x00,0x00,0x82,0xAC, ++0x08,0x00,0xE0,0x03, ++0xD0,0x1B,0xA2,0xAC, ++0xC0,0xFF,0xBD,0x27, ++0x34,0x00,0xB7,0xAF, ++0x3C,0x00,0xBF,0xAF, ++0x38,0x00,0xBE,0xAF, ++0x30,0x00,0xB6,0xAF, ++0x2C,0x00,0xB5,0xAF, ++0x28,0x00,0xB4,0xAF, ++0x24,0x00,0xB3,0xAF, ++0x20,0x00,0xB2,0xAF, ++0x1C,0x00,0xB1,0xAF, ++0x18,0x00,0xB0,0xAF, ++0x02,0x80,0x06,0x3C, ++0xCC,0x5E,0xC5,0x90, ++0x00,0x80,0x03,0x3C, ++0x25,0xB0,0x02,0x3C, ++0x18,0x03,0x42,0x34, ++0x2C,0x16,0x63,0x24, ++0x01,0x00,0xA4,0x30, ++0x00,0x00,0x43,0xAC, ++0x21,0xB8,0x00,0x00, ++0x03,0x00,0x80,0x10, ++0xF7,0x00,0xA2,0x30, ++0xFE,0x00,0xA2,0x30, ++0x01,0x00,0x17,0x24, ++0xCC,0x5E,0xC2,0xA0, ++0xCC,0x5E,0xC3,0x90, ++0x25,0xB0,0x02,0x3C, ++0xB0,0x03,0x42,0x34, ++0x00,0x00,0x43,0xAC, ++0x00,0x60,0x01,0x40, ++0x01,0x00,0x21,0x34, ++0x00,0x60,0x81,0x40, ++0x02,0x80,0x1E,0x3C, ++0x30,0x1F,0xD3,0x27, ++0x21,0xA8,0x40,0x00, ++0xCF,0x05,0x00,0x08, ++0x02,0x80,0x16,0x3C, ++0xA8,0x36,0x91,0xA2, ++0x30,0x1F,0xC2,0x27, ++0xE0,0x36,0x46,0x8C, ++0x4C,0x37,0x45,0x8C, ++0x05,0x00,0x04,0x24, ++0x80,0x00,0x07,0x24, ++0x73,0x01,0x00,0x0C, ++0x10,0x00,0xA0,0xAF, ++0x30,0x1F,0xD4,0x27, ++0xE4,0x36,0x85,0x8E, ++0x21,0x20,0x00,0x02, ++0x15,0x02,0x00,0x0C, ++0x21,0x30,0x40,0x02, ++0x2A,0xB0,0x07,0x3C, ++0x1D,0x00,0xE2,0x34, ++0x04,0x00,0x43,0x24, ++0x0B,0x10,0x77,0x00, ++0x01,0x00,0x04,0x24, ++0x02,0x00,0x03,0x24, ++0x00,0x00,0x44,0xA0, ++0x00,0x00,0x43,0xA0, ++0x1A,0x5E,0xC4,0x96, ++0x25,0xB0,0x06,0x3C, ++0x66,0x03,0xC5,0x34, ++0x01,0x00,0x84,0x24, ++0x1A,0x5E,0xC4,0xA6, ++0x1A,0x5E,0xC2,0x96, ++0xFF,0x00,0x03,0x24, ++0x00,0x00,0xA2,0xA4, ++0x2F,0x00,0x23,0x12, ++0x00,0x00,0x00,0x00, ++0xE0,0x36,0x62,0x8E, ++0x4C,0x37,0x72,0x8E, ++0x05,0x00,0x04,0x24, ++0x00,0x00,0xA2,0xAE, ++0xE4,0x36,0x62,0xAE, ++0x00,0x00,0xB2,0xAE, ++0xB0,0x01,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x4C,0x37,0x64,0x8E, ++0x50,0x37,0x63,0x8E, ++0x02,0x80,0x02,0x3C, ++0x14,0xEA,0x42,0x24, ++0x00,0x00,0x54,0x8C, ++0x80,0x00,0x84,0x24, ++0xFF,0x00,0x62,0x24, ++0x2B,0x10,0x44,0x00, ++0x0A,0x18,0x82,0x00, ++0x4C,0x37,0x63,0xAE, ++0x4C,0x37,0x82,0x8E, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0xA2,0xAE, ++0x02,0x80,0x03,0x3C, ++0xFF,0xFF,0x42,0x32, ++0x25,0x80,0x43,0x00, ++0x00,0x00,0xB0,0xAE, ++0x0C,0x00,0x02,0x92, ++0x08,0x00,0x05,0x24, ++0x00,0x00,0xA2,0xAE, ++0x02,0x00,0x04,0x92, ++0x00,0x00,0x00,0x00, ++0x21,0x20,0x92,0x00, ++0xFF,0xFF,0x84,0x30, ++0xFB,0x60,0x00,0x0C, ++0x25,0x20,0x83,0x00, ++0x0C,0x00,0x11,0x92, ++0x20,0x10,0x02,0x3C, ++0xFF,0x00,0x03,0x24, ++0x00,0x22,0x11,0x00, ++0xC2,0xFF,0x23,0x12, ++0x21,0x20,0x82,0x00, ++0xB8,0xFF,0xE0,0x16, ++0xE0,0x36,0x84,0xAE, ++0x02,0x80,0x02,0x3C, ++0x30,0x1F,0x42,0x24, ++0xB1,0x05,0x00,0x08, ++0x9C,0x36,0x51,0xA0, ++0x20,0x00,0xE0,0x12, ++0x44,0x00,0xE4,0x34, ++0xA8,0x36,0x83,0x92, ++0x45,0x00,0xE4,0x34, ++0xB0,0x03,0xC5,0x34, ++0x00,0x00,0x83,0xA0, ++0x00,0x00,0xA3,0xAC, ++0x00,0x60,0x01,0x40, ++0x01,0x00,0x21,0x34, ++0x00,0x60,0x81,0x40, ++0x00,0x60,0x01,0x40, ++0x01,0x00,0x21,0x34, ++0x01,0x00,0x21,0x38, ++0x00,0x60,0x81,0x40, ++0x30,0x1F,0xC5,0x27, ++0xD0,0x1B,0xA2,0x8C, ++0x3C,0x00,0xBF,0x8F, ++0x38,0x00,0xBE,0x8F, ++0x34,0x00,0xB7,0x8F, ++0x30,0x00,0xB6,0x8F, ++0x2C,0x00,0xB5,0x8F, ++0x28,0x00,0xB4,0x8F, ++0x24,0x00,0xB3,0x8F, ++0x20,0x00,0xB2,0x8F, ++0x1C,0x00,0xB1,0x8F, ++0x18,0x00,0xB0,0x8F, ++0x18,0x00,0x03,0x3C, ++0x25,0x10,0x43,0x00, ++0x41,0xB0,0x04,0x3C, ++0x40,0x00,0xBD,0x27, ++0x00,0x00,0x82,0xAC, ++0x08,0x00,0xE0,0x03, ++0xD0,0x1B,0xA2,0xAC, ++0x9C,0x36,0x83,0x92, ++0xB0,0x03,0xC5,0x34, ++0x00,0x00,0x83,0xA0, ++0x00,0x00,0xA3,0xAC, ++0x00,0x60,0x01,0x40, ++0x01,0x00,0x21,0x34, ++0x00,0x60,0x81,0x40, ++0x00,0x60,0x01,0x40, ++0x01,0x00,0x21,0x34, ++0x01,0x00,0x21,0x38, ++0x00,0x60,0x81,0x40, ++0x30,0x1F,0xC5,0x27, ++0xD0,0x1B,0xA2,0x8C, ++0x3C,0x00,0xBF,0x8F, ++0x38,0x00,0xBE,0x8F, ++0x34,0x00,0xB7,0x8F, ++0x30,0x00,0xB6,0x8F, ++0x2C,0x00,0xB5,0x8F, ++0x28,0x00,0xB4,0x8F, ++0x24,0x00,0xB3,0x8F, ++0x20,0x00,0xB2,0x8F, ++0x1C,0x00,0xB1,0x8F, ++0x18,0x00,0xB0,0x8F, ++0x18,0x00,0x03,0x3C, ++0x25,0x10,0x43,0x00, ++0x41,0xB0,0x04,0x3C, ++0x40,0x00,0xBD,0x27, ++0x00,0x00,0x82,0xAC, ++0x08,0x00,0xE0,0x03, ++0xD0,0x1B,0xA2,0xAC, ++0xC0,0xFF,0xBD,0x27, ++0x34,0x00,0xB7,0xAF, ++0x3C,0x00,0xBF,0xAF, ++0x38,0x00,0xBE,0xAF, ++0x30,0x00,0xB6,0xAF, ++0x2C,0x00,0xB5,0xAF, ++0x28,0x00,0xB4,0xAF, ++0x24,0x00,0xB3,0xAF, ++0x20,0x00,0xB2,0xAF, ++0x1C,0x00,0xB1,0xAF, ++0x18,0x00,0xB0,0xAF, ++0x02,0x80,0x06,0x3C, ++0xCC,0x5E,0xC5,0x90, ++0x00,0x80,0x03,0x3C, ++0x25,0xB0,0x02,0x3C, ++0x18,0x03,0x42,0x34, ++0xF0,0x18,0x63,0x24, ++0x02,0x00,0xA4,0x30, ++0x00,0x00,0x43,0xAC, ++0x21,0xB8,0x00,0x00, ++0x03,0x00,0x80,0x10, ++0xFB,0x00,0xA2,0x30, ++0xFD,0x00,0xA2,0x30, ++0x01,0x00,0x17,0x24, ++0xCC,0x5E,0xC2,0xA0, ++0xCC,0x5E,0xC3,0x90, ++0x25,0xB0,0x02,0x3C, ++0xB0,0x03,0x42,0x34, ++0x00,0x00,0x43,0xAC, ++0x00,0x60,0x01,0x40, ++0x01,0x00,0x21,0x34, ++0x00,0x60,0x81,0x40, ++0x02,0x80,0x1E,0x3C, ++0x30,0x1F,0xD3,0x27, ++0x21,0xA8,0x40,0x00, ++0x80,0x06,0x00,0x08, ++0x02,0x80,0x16,0x3C, ++0xA4,0x36,0x91,0xA2, ++0x30,0x1F,0xC2,0x27, ++0xEC,0x36,0x46,0x8C, ++0x58,0x37,0x45,0x8C, ++0x06,0x00,0x04,0x24, ++0x80,0x00,0x07,0x24, ++0x73,0x01,0x00,0x0C, ++0x10,0x00,0xA0,0xAF, ++0x30,0x1F,0xD4,0x27, ++0xF0,0x36,0x85,0x8E, ++0x21,0x20,0x00,0x02, ++0x15,0x02,0x00,0x0C, ++0x21,0x30,0x40,0x02, ++0x2A,0xB0,0x07,0x3C, ++0x25,0x00,0xE2,0x34, ++0x04,0x00,0x43,0x24, ++0x0B,0x10,0x77,0x00, ++0x01,0x00,0x04,0x24, ++0x02,0x00,0x03,0x24, ++0x00,0x00,0x44,0xA0, ++0x00,0x00,0x43,0xA0, ++0x1A,0x5E,0xC4,0x96, ++0x25,0xB0,0x06,0x3C, ++0x66,0x03,0xC5,0x34, ++0x01,0x00,0x84,0x24, ++0x1A,0x5E,0xC4,0xA6, ++0x1A,0x5E,0xC2,0x96, ++0xFF,0x00,0x03,0x24, ++0x00,0x00,0xA2,0xA4, ++0x2F,0x00,0x23,0x12, ++0x00,0x00,0x00,0x00, ++0xEC,0x36,0x62,0x8E, ++0x58,0x37,0x72,0x8E, ++0x06,0x00,0x04,0x24, ++0x00,0x00,0xA2,0xAE, ++0xF0,0x36,0x62,0xAE, ++0x00,0x00,0xB2,0xAE, ++0xB0,0x01,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x58,0x37,0x64,0x8E, ++0x5C,0x37,0x63,0x8E, ++0x02,0x80,0x02,0x3C, ++0x18,0xEA,0x42,0x24, ++0x00,0x00,0x54,0x8C, ++0x80,0x00,0x84,0x24, ++0xFF,0x00,0x62,0x24, ++0x2B,0x10,0x44,0x00, ++0x0A,0x18,0x82,0x00, ++0x58,0x37,0x63,0xAE, ++0x58,0x37,0x82,0x8E, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0xA2,0xAE, ++0x02,0x80,0x03,0x3C, ++0xFF,0xFF,0x42,0x32, ++0x25,0x80,0x43,0x00, ++0x00,0x00,0xB0,0xAE, ++0x0C,0x00,0x02,0x92, ++0x04,0x00,0x05,0x24, ++0x00,0x00,0xA2,0xAE, ++0x02,0x00,0x04,0x92, ++0x00,0x00,0x00,0x00, ++0x21,0x20,0x92,0x00, ++0xFF,0xFF,0x84,0x30, ++0xFB,0x60,0x00,0x0C, ++0x25,0x20,0x83,0x00, ++0x0C,0x00,0x11,0x92, ++0x20,0x10,0x02,0x3C, ++0xFF,0x00,0x03,0x24, ++0x00,0x22,0x11,0x00, ++0xC2,0xFF,0x23,0x12, ++0x21,0x20,0x82,0x00, ++0xB8,0xFF,0xE0,0x16, ++0xEC,0x36,0x84,0xAE, ++0x02,0x80,0x02,0x3C, ++0x30,0x1F,0x42,0x24, ++0x62,0x06,0x00,0x08, ++0xA0,0x36,0x51,0xA0, ++0x20,0x00,0xE0,0x12, ++0x46,0x00,0xE4,0x34, ++0xA4,0x36,0x83,0x92, ++0x47,0x00,0xE4,0x34, ++0xB0,0x03,0xC5,0x34, ++0x00,0x00,0x83,0xA0, ++0x00,0x00,0xA3,0xAC, ++0x00,0x60,0x01,0x40, ++0x01,0x00,0x21,0x34, ++0x00,0x60,0x81,0x40, ++0x00,0x60,0x01,0x40, ++0x01,0x00,0x21,0x34, ++0x01,0x00,0x21,0x38, ++0x00,0x60,0x81,0x40, ++0x30,0x1F,0xC5,0x27, ++0xD0,0x1B,0xA2,0x8C, ++0x3C,0x00,0xBF,0x8F, ++0x38,0x00,0xBE,0x8F, ++0x34,0x00,0xB7,0x8F, ++0x30,0x00,0xB6,0x8F, ++0x2C,0x00,0xB5,0x8F, ++0x28,0x00,0xB4,0x8F, ++0x24,0x00,0xB3,0x8F, ++0x20,0x00,0xB2,0x8F, ++0x1C,0x00,0xB1,0x8F, ++0x18,0x00,0xB0,0x8F, ++0x60,0x00,0x03,0x3C, ++0x25,0x10,0x43,0x00, ++0x41,0xB0,0x04,0x3C, ++0x40,0x00,0xBD,0x27, ++0x00,0x00,0x82,0xAC, ++0x08,0x00,0xE0,0x03, ++0xD0,0x1B,0xA2,0xAC, ++0xA0,0x36,0x83,0x92, ++0xB0,0x03,0xC5,0x34, ++0x00,0x00,0x83,0xA0, ++0x00,0x00,0xA3,0xAC, ++0x00,0x60,0x01,0x40, ++0x01,0x00,0x21,0x34, ++0x00,0x60,0x81,0x40, ++0x00,0x60,0x01,0x40, ++0x01,0x00,0x21,0x34, ++0x01,0x00,0x21,0x38, ++0x00,0x60,0x81,0x40, ++0x30,0x1F,0xC5,0x27, ++0xD0,0x1B,0xA2,0x8C, ++0x3C,0x00,0xBF,0x8F, ++0x38,0x00,0xBE,0x8F, ++0x34,0x00,0xB7,0x8F, ++0x30,0x00,0xB6,0x8F, ++0x2C,0x00,0xB5,0x8F, ++0x28,0x00,0xB4,0x8F, ++0x24,0x00,0xB3,0x8F, ++0x20,0x00,0xB2,0x8F, ++0x1C,0x00,0xB1,0x8F, ++0x18,0x00,0xB0,0x8F, ++0x60,0x00,0x03,0x3C, ++0x25,0x10,0x43,0x00, ++0x41,0xB0,0x04,0x3C, ++0x40,0x00,0xBD,0x27, ++0x00,0x00,0x82,0xAC, ++0x08,0x00,0xE0,0x03, ++0xD0,0x1B,0xA2,0xAC, ++0x00,0x80,0x03,0x3C, ++0x25,0xB0,0x02,0x3C, ++0xB4,0x1B,0x63,0x24, ++0x18,0x03,0x42,0x34, ++0x00,0x00,0x43,0xAC, ++0x00,0x60,0x01,0x40, ++0x01,0x00,0x21,0x34, ++0x00,0x60,0x81,0x40, ++0x00,0x60,0x01,0x40, ++0x01,0x00,0x21,0x34, ++0x01,0x00,0x21,0x38, ++0x00,0x60,0x81,0x40, ++0x02,0x80,0x05,0x3C, ++0x30,0x1F,0xA5,0x24, ++0xD8,0x1B,0xA2,0x8C, ++0xD0,0x1B,0xA4,0x8C, ++0x00,0x08,0x03,0x3C, ++0x24,0x10,0x43,0x00, ++0x25,0x20,0x82,0x00, ++0x41,0xB0,0x03,0x3C, ++0x00,0x00,0x64,0xAC, ++0x08,0x00,0xE0,0x03, ++0xD0,0x1B,0xA4,0xAC, ++0x25,0xB0,0x04,0x3C, ++0x00,0x80,0x02,0x3C, ++0xC8,0xFF,0xBD,0x27, ++0x18,0x03,0x83,0x34, ++0x10,0x1C,0x42,0x24, ++0x30,0x00,0xBF,0xAF, ++0x2C,0x00,0xB5,0xAF, ++0x28,0x00,0xB4,0xAF, ++0x24,0x00,0xB3,0xAF, ++0x20,0x00,0xB2,0xAF, ++0x1C,0x00,0xB1,0xAF, ++0x18,0x00,0xB0,0xAF, ++0x00,0x00,0x62,0xAC, ++0x00,0x60,0x01,0x40, ++0x01,0x00,0x21,0x34, ++0x00,0x60,0x81,0x40, ++0x02,0x80,0x14,0x3C, ++0x30,0x1F,0x93,0x26, ++0xFC,0x00,0x82,0x34, ++0x00,0x00,0x45,0x8C, ++0xAC,0x1B,0x66,0x96, ++0xD8,0x37,0x63,0x96, ++0xD0,0x37,0x67,0x8E, ++0x23,0x28,0xA6,0x00, ++0x21,0x10,0xA3,0x00, ++0x23,0x88,0x47,0x00, ++0xB0,0x03,0x84,0x34, ++0x23,0x30,0x23,0x02, ++0x2B,0x10,0x71,0x00, ++0x00,0x00,0x83,0xAC, ++0x00,0x00,0x91,0xAC, ++0x0B,0x88,0xC2,0x00, ++0x21,0x20,0x20,0x02, ++0x25,0x24,0x00,0x0C, ++0xD4,0x37,0x65,0xAE, ++0x4B,0x00,0x40,0x10, ++0x21,0x90,0x40,0x00, ++0x0C,0x00,0x51,0xAC, ++0xD0,0x37,0x68,0x8E, ++0xD4,0x37,0x62,0x8E, ++0x08,0x00,0x45,0x8E, ++0x20,0xBD,0x03,0x3C, ++0x88,0x03,0x63,0x34, ++0x2B,0x10,0x48,0x00, ++0x40,0x10,0x15,0x3C, ++0x21,0x20,0x00,0x00, ++0xFF,0xFF,0x27,0x32, ++0x00,0x00,0x65,0xAC, ++0x28,0x00,0x40,0x14, ++0x00,0x00,0x00,0x00, ++0xAC,0x1B,0x66,0x96, ++0x08,0x00,0x42,0x96, ++0x40,0x10,0x05,0x3C, ++0x21,0x20,0x00,0x00, ++0x21,0x30,0x06,0x01, ++0x25,0x28,0x45,0x00, ++0x73,0x01,0x00,0x0C, ++0x10,0x00,0xA0,0xAF, ++0x02,0x80,0x02,0x3C, ++0x64,0x57,0x42,0x24, ++0x30,0x1F,0x84,0x26, ++0xD4,0x37,0x83,0x8C, ++0x04,0x00,0x45,0x8C, ++0xD0,0x37,0x83,0xAC, ++0x00,0x00,0x42,0xAE, ++0x04,0x00,0x52,0xAC, ++0x00,0x00,0xB2,0xAC, ++0x04,0x00,0x45,0xAE, ++0x00,0x60,0x01,0x40, ++0x01,0x00,0x21,0x34, ++0x01,0x00,0x21,0x38, ++0x00,0x60,0x81,0x40, ++0x30,0x1F,0x85,0x26, ++0xD8,0x1B,0xA2,0x8C, ++0xD0,0x1B,0xA3,0x8C, ++0x30,0x00,0xBF,0x8F, ++0x2C,0x00,0xB5,0x8F, ++0x28,0x00,0xB4,0x8F, ++0x24,0x00,0xB3,0x8F, ++0x20,0x00,0xB2,0x8F, ++0x1C,0x00,0xB1,0x8F, ++0x18,0x00,0xB0,0x8F, ++0x04,0x00,0x42,0x30, ++0x25,0x18,0x62,0x00, ++0x41,0xB0,0x04,0x3C, ++0x38,0x00,0xBD,0x27, ++0x00,0x00,0x83,0xAC, ++0x08,0x00,0xE0,0x03, ++0xD0,0x1B,0xA3,0xAC, ++0xD8,0x37,0x70,0x8E, ++0x08,0x00,0x45,0x96, ++0xAC,0x1B,0x66,0x96, ++0x23,0x80,0x08,0x02, ++0xFF,0xFF,0x10,0x32, ++0x21,0x30,0x06,0x01, ++0x25,0x28,0xB5,0x00, ++0x21,0x38,0x00,0x02, ++0x73,0x01,0x00,0x0C, ++0x10,0x00,0xA0,0xAF, ++0xB0,0x01,0x00,0x0C, ++0x21,0x20,0x00,0x00, ++0x08,0x00,0x45,0x96, ++0xAC,0x1B,0x62,0x96, ++0x23,0x38,0x30,0x02, ++0x25,0x28,0xB5,0x00, ++0x21,0x10,0x06,0x3C, ++0x21,0x28,0xB0,0x00, ++0x21,0x30,0x46,0x00, ++0xFF,0xFF,0xE7,0x30, ++0x3C,0x07,0x00,0x08, ++0x21,0x20,0x00,0x00, ++0x00,0x60,0x02,0x40, ++0x01,0x00,0x41,0x34, ++0x01,0x00,0x21,0x38, ++0x00,0x60,0x81,0x40, ++0x02,0x80,0x04,0x3C, ++0xD0,0x5E,0x83,0x8C, ++0x00,0x00,0x00,0x00, ++0x00,0x10,0x63,0x34, ++0xD0,0x5E,0x83,0xAC, ++0x00,0x60,0x82,0x40, ++0x48,0x07,0x00,0x08, ++0x00,0x00,0x00,0x00, ++0x25,0xB0,0x04,0x3C, ++0x00,0x80,0x02,0x3C, ++0xC0,0xFF,0xBD,0x27, ++0x18,0x03,0x83,0x34, ++0xFC,0x1D,0x42,0x24, ++0x3C,0x00,0xBF,0xAF, ++0x38,0x00,0xBE,0xAF, ++0x34,0x00,0xB7,0xAF, ++0x30,0x00,0xB6,0xAF, ++0x2C,0x00,0xB5,0xAF, ++0x28,0x00,0xB4,0xAF, ++0x24,0x00,0xB3,0xAF, ++0x20,0x00,0xB2,0xAF, ++0x1C,0x00,0xB1,0xAF, ++0x18,0x00,0xB0,0xAF, ++0x00,0x00,0x62,0xAC, ++0x00,0x60,0x01,0x40, ++0x01,0x00,0x21,0x34, ++0x00,0x60,0x81,0x40, ++0x02,0x80,0x1E,0x3C, ++0x02,0x80,0x02,0x3C, ++0x2A,0xB0,0x03,0x3C, ++0xB0,0x03,0x96,0x34, ++0x80,0xD5,0x57,0x24, ++0x2C,0x00,0x73,0x34, ++0x30,0x1F,0xD1,0x27, ++0x02,0x80,0x15,0x3C, ++0xD1,0x07,0x00,0x08, ++0x02,0x80,0x14,0x3C, ++0x54,0xF3,0x90,0xAE, ++0x02,0x80,0x04,0x3C, ++0x03,0x00,0xC3,0x90, ++0x7C,0xD5,0x82,0x90, ++0x7F,0x00,0x63,0x30, ++0xFF,0x00,0x42,0x30, ++0x6B,0x00,0x62,0x10, ++0x08,0x00,0x10,0x26, ++0x02,0x00,0xC2,0x90, ++0x00,0x00,0x00,0x00, ++0xFF,0x00,0x42,0x30, ++0x37,0x00,0x42,0x28, ++0x5E,0x00,0x40,0x10, ++0x00,0x00,0x00,0x00, ++0x02,0x00,0xC5,0x90, ++0x03,0x00,0xC3,0x90, ++0xFF,0x00,0xA5,0x30, ++0x7F,0x00,0x63,0x30, ++0x7C,0xD5,0x83,0xA0, ++0x02,0x00,0xC2,0x90, ++0x0E,0x00,0xA5,0x38, ++0x0A,0x80,0xE5,0x00, ++0xFF,0x00,0x42,0x30, ++0xC0,0x10,0x02,0x00, ++0x21,0x10,0x57,0x00, ++0x04,0x00,0x43,0x8C, ++0x02,0x80,0x04,0x3C, ++0x8C,0xD7,0x84,0x24, ++0x4C,0xF3,0xA3,0xAE, ++0x02,0x00,0xC5,0x90, ++0x2F,0x55,0x00,0x0C, ++0xFF,0x00,0xA5,0x30, ++0x4C,0xF3,0xA2,0x8E, ++0x00,0x00,0x00,0x00, ++0x09,0xF8,0x40,0x00, ++0x21,0x20,0x00,0x02, ++0x01,0x00,0x02,0x24, ++0x02,0x00,0x03,0x24, ++0x01,0x00,0x62,0xA2, ++0x01,0x00,0x63,0xA2, ++0x2B,0x00,0x40,0x12, ++0x00,0x00,0x00,0x00, ++0xB8,0x36,0x22,0x92, ++0x20,0x10,0x03,0x3C, ++0x88,0x37,0x25,0x8E, ++0x00,0x12,0x02,0x00, ++0x21,0x10,0x43,0x00, ++0x21,0x30,0x40,0x00, ++0x0A,0x00,0x04,0x24, ++0x00,0x01,0x07,0x24, ++0x1C,0x37,0x22,0xAE, ++0x73,0x01,0x00,0x0C, ++0x10,0x00,0xA0,0xAF, ++0x88,0x37,0x30,0x8E, ++0xB0,0x01,0x00,0x0C, ++0x0A,0x00,0x04,0x24, ++0xFF,0xFF,0x10,0x32, ++0x02,0x80,0x02,0x3C, ++0x25,0x80,0x02,0x02, ++0x0C,0x00,0x04,0x92, ++0xFF,0x00,0x02,0x24, ++0x21,0x38,0x00,0x02, ++0xFF,0x00,0x83,0x30, ++0x20,0x00,0x10,0x26, ++0x04,0x00,0x62,0x10, ++0x21,0x90,0x00,0x00, ++0xB8,0x36,0x24,0xA2, ++0x01,0x00,0x12,0x24, ++0x00,0x00,0xC3,0xAE, ++0x04,0x00,0xE2,0x8C, ++0x13,0x00,0x03,0x24, ++0x02,0x12,0x02,0x00, ++0x1F,0x00,0x45,0x30, ++0xB6,0xFF,0xA3,0x10, ++0x21,0x30,0x00,0x02, ++0x02,0x80,0x04,0x3C, ++0x2F,0x55,0x00,0x0C, ++0x38,0xD7,0x84,0x24, ++0x01,0x00,0x02,0x24, ++0x02,0x00,0x03,0x24, ++0x01,0x00,0x62,0xA2, ++0x01,0x00,0x63,0xA2, ++0xD7,0xFF,0x40,0x16, ++0x00,0x00,0x00,0x00, ++0x00,0x60,0x01,0x40, ++0x01,0x00,0x21,0x34, ++0x01,0x00,0x21,0x38, ++0x00,0x60,0x81,0x40, ++0x30,0x1F,0xC5,0x27, ++0xD0,0x1B,0xA2,0x8C, ++0x3C,0x00,0xBF,0x8F, ++0x38,0x00,0xBE,0x8F, ++0x34,0x00,0xB7,0x8F, ++0x30,0x00,0xB6,0x8F, ++0x2C,0x00,0xB5,0x8F, ++0x28,0x00,0xB4,0x8F, ++0x24,0x00,0xB3,0x8F, ++0x20,0x00,0xB2,0x8F, ++0x1C,0x00,0xB1,0x8F, ++0x18,0x00,0xB0,0x8F, ++0x00,0x04,0x03,0x3C, ++0x25,0x10,0x43,0x00, ++0x41,0xB0,0x04,0x3C, ++0x40,0x00,0xBD,0x27, ++0x00,0x00,0x82,0xAC, ++0x08,0x00,0xE0,0x03, ++0xD0,0x1B,0xA2,0xAC, ++0x02,0x00,0xC5,0x90, ++0x02,0x80,0x04,0x3C, ++0x78,0xD7,0x84,0x24, ++0x2F,0x55,0x00,0x0C, ++0xFF,0x00,0xA5,0x30, ++0xEB,0x07,0x00,0x08, ++0x01,0x00,0x02,0x24, ++0x02,0x00,0xC5,0x90, ++0x02,0x00,0xC6,0x90, ++0x7C,0xD5,0x87,0x90, ++0x02,0x80,0x04,0x3C, ++0x48,0xD7,0x84,0x24, ++0xFF,0x00,0xA5,0x30, ++0xFF,0x00,0xC6,0x30, ++0x2F,0x55,0x00,0x0C, ++0xFF,0x00,0xE7,0x30, ++0xC1,0x07,0x00,0x08, ++0x01,0x00,0x02,0x24, ++0xC8,0xFF,0xBD,0x27, ++0xFF,0xFF,0xA8,0x30, ++0x02,0x80,0x02,0x3C, ++0x25,0x40,0x02,0x01, ++0x30,0x00,0xB6,0xAF, ++0x20,0x00,0xB2,0xAF, ++0x34,0x00,0xBF,0xAF, ++0x2C,0x00,0xB5,0xAF, ++0x28,0x00,0xB4,0xAF, ++0x24,0x00,0xB3,0xAF, ++0x1C,0x00,0xB1,0xAF, ++0x18,0x00,0xB0,0xAF, ++0x00,0x00,0x03,0x8D, ++0xFF,0xFF,0xD2,0x30, ++0x21,0xB0,0xA0,0x00, ++0x00,0xC0,0x02,0x24, ++0x08,0x00,0x45,0x26, ++0x04,0x00,0x06,0x8D, ++0x24,0x18,0x62,0x00, ++0xFF,0x3F,0xA5,0x30, ++0xF0,0xFF,0x02,0x3C, ++0x25,0x18,0x65,0x00, ++0xFF,0xFF,0x42,0x34, ++0x24,0x18,0x62,0x00, ++0x00,0x80,0x05,0x3C, ++0x25,0x18,0x65,0x00, ++0xFF,0x01,0xC6,0x34, ++0x00,0x00,0x03,0xAD, ++0x04,0x00,0x06,0xAD, ++0x21,0x48,0x80,0x00, ++0xFF,0xFF,0xE7,0x30, ++0x18,0x00,0x12,0xA5, ++0x1A,0x00,0x07,0xA1, ++0x18,0x00,0x03,0x8D, ++0xFF,0x7F,0x02,0x3C, ++0xFF,0xFF,0x42,0x34, ++0x24,0x18,0x62,0x00, ++0x02,0x80,0x15,0x3C, ++0x18,0x00,0x03,0xAD, ++0x30,0x1F,0xA5,0x26, ++0x7A,0x36,0xA3,0x90, ++0x00,0x00,0x00,0x00, ++0x01,0x00,0x62,0x24, ++0x7A,0x36,0xA2,0xA0, ++0x18,0x00,0x04,0x8D, ++0xFF,0x80,0x02,0x3C, ++0x20,0x00,0x45,0x26, ++0xFF,0xFF,0x42,0x34, ++0x7F,0x00,0x63,0x30, ++0xFF,0xFF,0xB2,0x30, ++0x24,0x20,0x82,0x00, ++0x00,0x1E,0x03,0x00, ++0x25,0xB0,0x02,0x3C, ++0xC0,0x00,0x42,0x34, ++0x25,0x20,0x83,0x00, ++0x07,0x00,0x45,0x32, ++0x18,0x00,0x04,0xAD, ++0x00,0x00,0x52,0xA4, ++0x03,0x00,0xA0,0x10, ++0xFF,0xFF,0x42,0x32, ++0x08,0x00,0x42,0x26, ++0xFF,0xFF,0x42,0x30, ++0x30,0x1F,0xB4,0x26, ++0xF8,0x37,0x86,0x8E, ++0xFC,0x37,0x90,0x8E, ++0xF8,0xFF,0x52,0x30, ++0x21,0x10,0xD2,0x00, ++0x2B,0x10,0x02,0x02, ++0x31,0x00,0x40,0x10, ++0xFF,0x00,0x33,0x31, ++0x23,0x80,0x06,0x02, ++0x21,0x28,0xC0,0x02, ++0xFF,0xFF,0x07,0x32, ++0x01,0x00,0x11,0x24, ++0x21,0x20,0x60,0x02, ++0x73,0x01,0x00,0x0C, ++0x10,0x00,0xB1,0xAF, ++0x23,0x18,0x50,0x02, ++0xFF,0xFF,0x72,0x30, ++0x22,0x10,0x02,0x3C, ++0x21,0x10,0x42,0x02, ++0x21,0x20,0x60,0x02, ++0xB0,0x01,0x00,0x0C, ++0xF8,0x37,0x82,0xAE, ++0x21,0x28,0xD0,0x02, ++0x21,0x38,0x40,0x02, ++0x21,0x20,0x60,0x02, ++0x10,0x00,0xB1,0xAF, ++0x22,0x10,0x06,0x3C, ++0x73,0x01,0x00,0x0C, ++0x30,0x1F,0xB1,0x26, ++0xF8,0x37,0x23,0x8E, ++0x25,0xB0,0x10,0x3C, ++0xB0,0x03,0x02,0x36, ++0x21,0x20,0x60,0x02, ++0x00,0x00,0x43,0xAC, ++0xB0,0x01,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0xF8,0x37,0x25,0x8E, ++0xEC,0x00,0x02,0x36, ++0xBD,0x00,0x04,0x36, ++0x00,0x00,0x45,0xAC, ++0x00,0x00,0x83,0x90, ++0xC2,0x00,0x10,0x36, ++0x34,0x00,0xBF,0x8F, ++0x10,0x00,0x63,0x34, ++0x00,0x00,0x83,0xA0, ++0x30,0x00,0xB6,0x8F, ++0x00,0x00,0x05,0xA6, ++0x2C,0x00,0xB5,0x8F, ++0x28,0x00,0xB4,0x8F, ++0x24,0x00,0xB3,0x8F, ++0x20,0x00,0xB2,0x8F, ++0x1C,0x00,0xB1,0x8F, ++0x18,0x00,0xB0,0x8F, ++0x01,0x00,0x02,0x24, ++0x08,0x00,0xE0,0x03, ++0x38,0x00,0xBD,0x27, ++0x21,0x28,0xC0,0x02, ++0x21,0x20,0x60,0x02, ++0x21,0x38,0x40,0x02, ++0x01,0x00,0x02,0x24, ++0x73,0x01,0x00,0x0C, ++0x10,0x00,0xA2,0xAF, ++0xF8,0x37,0x83,0x8E, ++0x30,0x1F,0xB1,0x26, ++0x25,0xB0,0x10,0x3C, ++0x21,0x18,0x72,0x00, ++0xF8,0x37,0x83,0xAE, ++0xF8,0x37,0x23,0x8E, ++0xB0,0x03,0x02,0x36, ++0x21,0x20,0x60,0x02, ++0x00,0x00,0x43,0xAC, ++0xB0,0x01,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0xF8,0x37,0x25,0x8E, ++0xEC,0x00,0x02,0x36, ++0xBD,0x00,0x04,0x36, ++0x00,0x00,0x45,0xAC, ++0x00,0x00,0x83,0x90, ++0xC2,0x00,0x10,0x36, ++0x34,0x00,0xBF,0x8F, ++0x10,0x00,0x63,0x34, ++0x00,0x00,0x83,0xA0, ++0x30,0x00,0xB6,0x8F, ++0x00,0x00,0x05,0xA6, ++0x2C,0x00,0xB5,0x8F, ++0x28,0x00,0xB4,0x8F, ++0x24,0x00,0xB3,0x8F, ++0x20,0x00,0xB2,0x8F, ++0x1C,0x00,0xB1,0x8F, ++0x18,0x00,0xB0,0x8F, ++0x01,0x00,0x02,0x24, ++0x08,0x00,0xE0,0x03, ++0x38,0x00,0xBD,0x27, ++0xC8,0xFF,0xBD,0x27, ++0x18,0x00,0xB0,0xAF, ++0x34,0x00,0xBF,0xAF, ++0x30,0x00,0xB6,0xAF, ++0x2C,0x00,0xB5,0xAF, ++0x28,0x00,0xB4,0xAF, ++0x24,0x00,0xB3,0xAF, ++0x20,0x00,0xB2,0xAF, ++0x1C,0x00,0xB1,0xAF, ++0x21,0x80,0x80,0x00, ++0x00,0x60,0x14,0x40, ++0x01,0x00,0x81,0x36, ++0x01,0x00,0x21,0x38, ++0x00,0x60,0x81,0x40, ++0x14,0x00,0x83,0x8C, ++0x02,0x80,0x15,0x3C, ++0x16,0x00,0x02,0x24, ++0x30,0x1F,0xB3,0x26, ++0x21,0x28,0x00,0x00, ++0x1D,0x00,0x62,0x10, ++0x08,0x00,0x06,0x24, ++0x08,0x00,0x82,0x94, ++0x02,0x80,0x04,0x3C, ++0x08,0x52,0x00,0x0C, ++0x25,0x20,0x44,0x00, ++0x08,0x00,0x05,0x8E, ++0x0C,0x00,0x06,0x96, ++0x14,0x00,0x07,0x96, ++0x19,0x08,0x00,0x0C, ++0x09,0x00,0x04,0x24, ++0x04,0x00,0x02,0x8E, ++0x00,0x00,0x03,0x8E, ++0x21,0x20,0x00,0x02, ++0x00,0x00,0x43,0xAC, ++0x04,0x00,0x62,0xAC, ++0x00,0x00,0x10,0xAE, ++0x3D,0x24,0x00,0x0C, ++0x04,0x00,0x10,0xAE, ++0x00,0x60,0x94,0x40, ++0x34,0x00,0xBF,0x8F, ++0x30,0x00,0xB6,0x8F, ++0x2C,0x00,0xB5,0x8F, ++0x28,0x00,0xB4,0x8F, ++0x24,0x00,0xB3,0x8F, ++0x20,0x00,0xB2,0x8F, ++0x1C,0x00,0xB1,0x8F, ++0x18,0x00,0xB0,0x8F, ++0x08,0x00,0xE0,0x03, ++0x38,0x00,0xBD,0x27, ++0xF8,0x37,0x68,0x8E, ++0x0C,0x00,0x11,0x8E, ++0xFC,0x37,0x62,0x8E, ++0x25,0xB0,0x03,0x3C, ++0x21,0x28,0x11,0x01, ++0xC0,0x00,0x63,0x34, ++0x23,0x90,0x48,0x00, ++0x2B,0x10,0x45,0x00, ++0x01,0x00,0x16,0x24, ++0x09,0x00,0x04,0x24, ++0xFF,0xFF,0x27,0x32, ++0x21,0x30,0x00,0x01, ++0x00,0x00,0x71,0xA4, ++0x33,0x00,0x40,0x10, ++0x01,0x00,0x02,0x24, ++0x08,0x00,0x05,0x8E, ++0xFF,0xFF,0x47,0x32, ++0x23,0x88,0x32,0x02, ++0x73,0x01,0x00,0x0C, ++0x10,0x00,0xB6,0xAF, ++0x22,0x10,0x03,0x3C, ++0x21,0x18,0x23,0x02, ++0x09,0x00,0x04,0x24, ++0xB0,0x01,0x00,0x0C, ++0xF8,0x37,0x63,0xAE, ++0x08,0x00,0x05,0x8E, ++0xFF,0xFF,0x27,0x32, ++0x09,0x00,0x04,0x24, ++0x21,0x28,0xB2,0x00, ++0x22,0x10,0x06,0x3C, ++0x73,0x01,0x00,0x0C, ++0x10,0x00,0xB6,0xAF, ++0xB0,0x01,0x00,0x0C, ++0x09,0x00,0x04,0x24, ++0x30,0x1F,0xA2,0x26, ++0xF8,0x37,0x46,0x8C, ++0x25,0xB0,0x03,0x3C, ++0xEC,0x00,0x64,0x34, ++0x00,0x00,0x86,0xAC, ++0xBD,0x00,0x65,0x34, ++0x00,0x00,0xA2,0x90, ++0xC2,0x00,0x63,0x34, ++0x21,0x20,0x00,0x02, ++0x10,0x00,0x42,0x34, ++0x00,0x00,0xA2,0xA0, ++0x00,0x00,0x66,0xA4, ++0x04,0x00,0x02,0x8E, ++0x00,0x00,0x03,0x8E, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x43,0xAC, ++0x04,0x00,0x62,0xAC, ++0x00,0x00,0x10,0xAE, ++0x3D,0x24,0x00,0x0C, ++0x04,0x00,0x10,0xAE, ++0x00,0x60,0x94,0x40, ++0x34,0x00,0xBF,0x8F, ++0x30,0x00,0xB6,0x8F, ++0x2C,0x00,0xB5,0x8F, ++0x28,0x00,0xB4,0x8F, ++0x24,0x00,0xB3,0x8F, ++0x20,0x00,0xB2,0x8F, ++0x1C,0x00,0xB1,0x8F, ++0x18,0x00,0xB0,0x8F, ++0x08,0x00,0xE0,0x03, ++0x38,0x00,0xBD,0x27, ++0x08,0x00,0x05,0x8E, ++0x21,0x30,0x00,0x01, ++0x09,0x00,0x04,0x24, ++0x73,0x01,0x00,0x0C, ++0x10,0x00,0xA2,0xAF, ++0xF8,0x37,0x63,0x8E, ++0x00,0x00,0x00,0x00, ++0x21,0x18,0x71,0x00, ++0x05,0x09,0x00,0x08, ++0xF8,0x37,0x63,0xAE, ++0xE8,0xFF,0xBD,0x27, ++0x14,0x00,0xBF,0xAF, ++0x10,0x00,0xB0,0xAF, ++0x21,0x28,0x80,0x00, ++0x00,0x60,0x10,0x40, ++0x01,0x00,0x01,0x36, ++0x01,0x00,0x21,0x38, ++0x00,0x60,0x81,0x40, ++0x25,0xB0,0x02,0x3C, ++0xBF,0x00,0x42,0x34, ++0x00,0x00,0x43,0x90, ++0x00,0x00,0x00,0x00, ++0x04,0x00,0x63,0x2C, ++0x05,0x00,0x60,0x10, ++0x02,0x80,0x06,0x3C, ++0x6C,0x57,0xC3,0x8C, ++0x6C,0x57,0xC2,0x24, ++0x0C,0x00,0x62,0x10, ++0x00,0x00,0x00,0x00, ++0x6C,0x57,0xC2,0x24, ++0x04,0x00,0x43,0x8C, ++0x00,0x00,0xA2,0xAC, ++0x04,0x00,0x45,0xAC, ++0x00,0x00,0x65,0xAC, ++0x04,0x00,0xA3,0xAC, ++0x00,0x60,0x90,0x40, ++0x14,0x00,0xBF,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x08,0x00,0xE0,0x03, ++0x18,0x00,0xBD,0x27, ++0xB4,0x08,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x00,0x60,0x90,0x40, ++0x14,0x00,0xBF,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x08,0x00,0xE0,0x03, ++0x18,0x00,0xBD,0x27, ++0xE0,0xFF,0xBD,0x27, ++0x10,0x00,0xB0,0xAF, ++0x21,0x80,0x80,0x00, ++0x02,0x80,0x04,0x3C, ++0x98,0xD7,0x84,0x24, ++0x1C,0x00,0xBF,0xAF, ++0x18,0x00,0xB2,0xAF, ++0x2F,0x55,0x00,0x0C, ++0x14,0x00,0xB1,0xAF, ++0x00,0x00,0x04,0x96, ++0x00,0x00,0x00,0x00, ++0x20,0x00,0x83,0x24, ++0x07,0x00,0x62,0x30, ++0x49,0x00,0x40,0x10, ++0xC2,0x10,0x03,0x00, ++0x28,0x00,0x82,0x24, ++0xC2,0x10,0x02,0x00, ++0x25,0x24,0x00,0x0C, ++0xC0,0x20,0x02,0x00, ++0x47,0x00,0x40,0x10, ++0x21,0x88,0x40,0x00, ++0x02,0x80,0x12,0x3C, ++0x30,0x1F,0x50,0x26, ++0x1C,0x37,0x05,0x8E, ++0x0A,0x00,0x04,0x24, ++0x28,0x00,0x06,0x24, ++0xC7,0x01,0x00,0x0C, ++0x21,0x38,0x40,0x00, ++0xB0,0x1B,0x03,0x96, ++0x00,0x00,0x00,0x00, ++0x00,0x01,0x62,0x30, ++0x47,0x00,0x40,0x14, ++0x01,0x00,0x62,0x30, ++0x02,0x80,0x02,0x3C, ++0xEA,0x5D,0x48,0x90, ++0x25,0xB0,0x04,0x3C, ++0x2F,0x00,0x02,0x3C, ++0xD0,0x01,0x85,0x34, ++0x17,0x32,0x42,0x34, ++0x00,0x00,0xA2,0xAC, ++0x5E,0x00,0x03,0x3C, ++0x10,0x00,0x02,0x3C, ++0xDC,0x01,0x87,0x34, ++0xD4,0x01,0x86,0x34, ++0x17,0x43,0x63,0x34, ++0x20,0x53,0x42,0x34, ++0xD8,0x01,0x84,0x34, ++0x00,0x00,0xC3,0xAC, ++0x30,0x1F,0x49,0x26, ++0x00,0x00,0x82,0xAC, ++0x44,0xA4,0x03,0x34, ++0x01,0x00,0x02,0x24, ++0x00,0x00,0xE3,0xAC, ++0xEC,0x38,0x20,0xAD, ++0x08,0x39,0x20,0xAD, ++0x50,0x3E,0x20,0xAD, ++0x10,0x3E,0x20,0xAD, ++0x51,0x00,0x02,0x11, ++0x1A,0x3E,0x20,0xA1, ++0x10,0x23,0x22,0x8D, ++0xFF,0xF7,0x03,0x24, ++0xFF,0xEF,0x04,0x24, ++0x24,0x10,0x43,0x00, ++0x24,0x10,0x44,0x00, ++0x10,0x23,0x22,0xAD, ++0xB0,0x01,0x00,0x0C, ++0x0A,0x00,0x04,0x24, ++0x08,0x00,0x22,0x96, ++0x02,0x80,0x05,0x3C, ++0x02,0x80,0x04,0x3C, ++0x25,0x28,0x45,0x00, ++0xDC,0x01,0x06,0x24, ++0x10,0x52,0x00,0x0C, ++0x84,0x58,0x84,0x24, ++0x3D,0x24,0x00,0x0C, ++0x21,0x20,0x20,0x02, ++0x30,0x1F,0x43,0x26, ++0x9C,0x39,0x62,0x8C, ++0xD1,0x11,0x00,0x0C, ++0x30,0x3B,0x62,0xA0, ++0x1C,0x00,0xBF,0x8F, ++0x18,0x00,0xB2,0x8F, ++0x14,0x00,0xB1,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x21,0x10,0x00,0x00, ++0x08,0x00,0xE0,0x03, ++0x20,0x00,0xBD,0x27, ++0x25,0x24,0x00,0x0C, ++0xC0,0x20,0x02,0x00, ++0xBB,0xFF,0x40,0x14, ++0x21,0x88,0x40,0x00, ++0x02,0x80,0x04,0x3C, ++0x02,0x80,0x05,0x3C, ++0xA8,0xD7,0x84,0x24, ++0x2F,0x55,0x00,0x0C, ++0x1C,0xEA,0xA5,0x24, ++0x1C,0x00,0xBF,0x8F, ++0x18,0x00,0xB2,0x8F, ++0x14,0x00,0xB1,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x21,0x10,0x00,0x00, ++0x08,0x00,0xE0,0x03, ++0x20,0x00,0xBD,0x27, ++0x32,0x00,0x40,0x14, ++0x02,0x80,0x04,0x3C, ++0xA3,0x51,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0xB0,0x1B,0x02,0x96, ++0x25,0xB0,0x03,0x3C, ++0x4C,0x00,0x63,0x34, ++0xFF,0xFE,0x42,0x30, ++0xB0,0x1B,0x02,0xA6, ++0x00,0x00,0x60,0xA0, ++0x02,0x80,0x02,0x3C, ++0xEA,0x5D,0x48,0x90, ++0x25,0xB0,0x04,0x3C, ++0x2F,0x00,0x02,0x3C, ++0xD0,0x01,0x85,0x34, ++0x17,0x32,0x42,0x34, ++0x00,0x00,0xA2,0xAC, ++0x5E,0x00,0x03,0x3C, ++0x10,0x00,0x02,0x3C, ++0xDC,0x01,0x87,0x34, ++0xD4,0x01,0x86,0x34, ++0x17,0x43,0x63,0x34, ++0x20,0x53,0x42,0x34, ++0xD8,0x01,0x84,0x34, ++0x00,0x00,0xC3,0xAC, ++0x30,0x1F,0x49,0x26, ++0x00,0x00,0x82,0xAC, ++0x44,0xA4,0x03,0x34, ++0x01,0x00,0x02,0x24, ++0x00,0x00,0xE3,0xAC, ++0xEC,0x38,0x20,0xAD, ++0x08,0x39,0x20,0xAD, ++0x50,0x3E,0x20,0xAD, ++0x10,0x3E,0x20,0xAD, ++0xB1,0xFF,0x02,0x15, ++0x1A,0x3E,0x20,0xA1, ++0x02,0x80,0x02,0x3C, ++0xEB,0x5D,0x44,0x90, ++0x02,0x00,0x03,0x24, ++0x06,0x00,0x83,0x10, ++0xFF,0xF7,0x03,0x24, ++0x10,0x23,0x22,0x8D, ++0x00,0x00,0x00,0x00, ++0x24,0x10,0x43,0x00, ++0x95,0x09,0x00,0x08, ++0x00,0x10,0x42,0x34, ++0x10,0x23,0x22,0x8D, ++0xFF,0xEF,0x03,0x24, ++0x00,0x08,0x42,0x34, ++0x95,0x09,0x00,0x08, ++0x24,0x10,0x43,0x00, ++0x88,0x58,0x84,0x24, ++0x6C,0x4C,0x00,0x0C, ++0x03,0x00,0x05,0x24, ++0xBE,0x09,0x00,0x08, ++0x00,0x00,0x00,0x00, ++0x08,0x00,0xE0,0x03, ++0x21,0x10,0x00,0x00, ++0xD8,0xFF,0xBD,0x27, ++0x18,0x00,0xB2,0xAF, ++0x02,0x80,0x12,0x3C, ++0x1C,0x00,0xB3,0xAF, ++0x24,0x00,0xBF,0xAF, ++0x20,0x00,0xB4,0xAF, ++0x14,0x00,0xB1,0xAF, ++0x10,0x00,0xB0,0xAF, ++0x30,0x1F,0x43,0x26, ++0xB0,0x1B,0x62,0x94, ++0x00,0x00,0x00,0x00, ++0x00,0x10,0x42,0x30, ++0x76,0x00,0x40,0x14, ++0x21,0x98,0x80,0x00, ++0x00,0x60,0x10,0x40, ++0x01,0x00,0x01,0x36, ++0x01,0x00,0x21,0x38, ++0x00,0x60,0x81,0x40, ++0x02,0x80,0x14,0x3C, ++0xF6,0x5E,0x82,0x92, ++0x00,0x00,0x00,0x00, ++0x0F,0x00,0x42,0x30, ++0x04,0x00,0x42,0x28, ++0x74,0x00,0x40,0x14, ++0x04,0x00,0x04,0x24, ++0x00,0x60,0x90,0x40, ++0x30,0x1F,0x42,0x8E, ++0xFF,0xF0,0x03,0x24, ++0x0F,0xFF,0x04,0x24, ++0x24,0x10,0x43,0x00, ++0x24,0x10,0x44,0x00, ++0x25,0xB0,0x05,0x3C, ++0xF0,0xFF,0x03,0x24, ++0x24,0x10,0x43,0x00, ++0x64,0x03,0xA4,0x34, ++0x17,0x00,0x03,0x24, ++0x00,0x00,0x80,0xA0, ++0x50,0x0C,0xA3,0xA0, ++0x30,0x1F,0x42,0xAE, ++0x21,0x10,0x00,0x00, ++0x01,0x00,0x42,0x24, ++0xFF,0x00,0x42,0x30, ++0x06,0x00,0x43,0x2C, ++0xFD,0xFF,0x60,0x14, ++0x01,0x00,0x42,0x24, ++0x25,0xB0,0x02,0x3C, ++0x17,0x00,0x03,0x24, ++0x58,0x0C,0x43,0xA0, ++0x21,0x10,0x00,0x00, ++0x01,0x00,0x42,0x24, ++0xFF,0x00,0x42,0x30, ++0x06,0x00,0x43,0x2C, ++0xFD,0xFF,0x60,0x14, ++0x01,0x00,0x42,0x24, ++0x30,0x1F,0x51,0x26, ++0xB0,0x1B,0x22,0x96, ++0x02,0x80,0x04,0x3C, ++0xB4,0xD7,0x84,0x24, ++0x00,0x10,0x42,0x34, ++0x2F,0x55,0x00,0x0C, ++0xB0,0x1B,0x22,0xA6, ++0x01,0x00,0x02,0x24, ++0x25,0xB0,0x03,0x3C, ++0x6C,0x3B,0x22,0xAE, ++0x4C,0x00,0x63,0x34, ++0x08,0x00,0x66,0x8E, ++0x00,0x00,0x67,0x90, ++0xB0,0x1B,0x22,0x96, ++0x30,0x3B,0x28,0x92, ++0x31,0x3B,0x29,0x92, ++0x8F,0x3E,0x2A,0x92, ++0x38,0x3B,0x2B,0x92, ++0x67,0x3B,0x2C,0x92, ++0x74,0x3B,0x26,0xAE, ++0x00,0x80,0x42,0x30, ++0xA1,0x3B,0x27,0xA2, ++0x21,0x20,0x00,0x00, ++0x00,0x00,0x60,0xA0, ++0x21,0x28,0x00,0x00, ++0x99,0x3B,0x28,0xA2, ++0x9A,0x3B,0x29,0xA2, ++0x9E,0x3B,0x22,0xA6, ++0xA0,0x3B,0x2A,0xA2, ++0x30,0x3B,0x2B,0xA2, ++0x31,0x3B,0x2C,0xA2, ++0xA4,0x3B,0x20,0xAE, ++0xA8,0x3B,0x20,0xAE, ++0x9C,0x3B,0x20,0xA2, ++0x12,0x0D,0x00,0x0C, ++0x9B,0x3B,0x20,0xA2, ++0x08,0x00,0x66,0x8E, ++0x00,0x00,0x00,0x00, ++0x33,0x00,0xC0,0x14, ++0x0C,0x00,0x70,0x26, ++0x00,0x00,0x62,0x8E, ++0x21,0x20,0x20,0x02, ++0xAC,0x3B,0x23,0x26, ++0x70,0x3B,0x22,0xAE, ++0x3F,0x00,0x02,0x24, ++0xFF,0xFF,0x42,0x24, ++0x00,0x00,0x60,0xA0, ++0xFD,0xFF,0x41,0x04, ++0x07,0x00,0x63,0x24, ++0xB0,0x1B,0x83,0x94, ++0x00,0x00,0x00,0x00, ++0x00,0x01,0x62,0x30, ++0x09,0x00,0x40,0x10, ++0x30,0x1F,0x50,0x26, ++0x01,0x00,0x62,0x30, ++0x06,0x00,0x40,0x10, ++0x00,0x00,0x00,0x00, ++0xF6,0x5E,0x82,0x92, ++0x0C,0x00,0x03,0x24, ++0x0F,0x00,0x42,0x30, ++0x2C,0x00,0x43,0x10, ++0x00,0x00,0x00,0x00, ++0x30,0x3B,0x04,0x92, ++0x4F,0x0C,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x25,0xB0,0x04,0x3C, ++0x48,0x00,0x84,0x34, ++0x00,0x00,0x83,0x8C, ++0x70,0x3B,0x05,0x8E, ++0x7B,0xFF,0x02,0x3C, ++0xFF,0xFF,0x42,0x34, ++0x24,0x18,0x62,0x00, ++0x01,0x00,0x02,0x24, ++0x00,0x00,0x83,0xAC, ++0x19,0x00,0xA2,0x10, ++0x3C,0x00,0x02,0x24, ++0x98,0x38,0x02,0xAE, ++0x24,0x00,0xBF,0x8F, ++0x20,0x00,0xB4,0x8F, ++0x1C,0x00,0xB3,0x8F, ++0x18,0x00,0xB2,0x8F, ++0x14,0x00,0xB1,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x21,0x10,0x00,0x00, ++0x08,0x00,0xE0,0x03, ++0x28,0x00,0xBD,0x27, ++0x64,0x31,0x00,0x0C, ++0x01,0x00,0x05,0x24, ++0x0F,0x0A,0x00,0x08, ++0x00,0x00,0x00,0x00, ++0x02,0x80,0x04,0x3C, ++0x21,0x28,0x00,0x02, ++0x10,0x52,0x00,0x0C, ++0xA8,0x5A,0x84,0x24, ++0x02,0x80,0x04,0x3C, ++0xC4,0xD7,0x84,0x24, ++0x2F,0x55,0x00,0x0C, ++0x21,0x28,0x00,0x02, ++0x54,0x0A,0x00,0x08, ++0x00,0x00,0x00,0x00, ++0x13,0x0F,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x3C,0x00,0x02,0x24, ++0x79,0x0A,0x00,0x08, ++0x98,0x38,0x02,0xAE, ++0xCD,0x4E,0x00,0x0C, ++0x01,0x00,0x04,0x24, ++0x6A,0x0A,0x00,0x08, ++0x30,0x1F,0x50,0x26, ++0xE8,0xFF,0xBD,0x27, ++0x10,0x00,0xB0,0xAF, ++0x14,0x00,0xBF,0xAF, ++0x21,0x80,0x80,0x00, ++0x00,0x00,0x02,0x92, ++0x02,0x80,0x04,0x3C, ++0x21,0x28,0x40,0x00, ++0x03,0x00,0x42,0x2C, ++0x06,0x00,0x40,0x14, ++0xD0,0xD7,0x84,0x24, ++0x14,0x00,0xBF,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x21,0x10,0x00,0x00, ++0x08,0x00,0xE0,0x03, ++0x18,0x00,0xBD,0x27, ++0x2F,0x55,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x03,0x92, ++0x14,0x00,0xBF,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x02,0x80,0x02,0x3C, ++0xA8,0x5C,0x43,0xAC, ++0x18,0x00,0xBD,0x27, ++0x08,0x00,0xE0,0x03, ++0x21,0x10,0x00,0x00, ++0x00,0x80,0x03,0x3C, ++0x25,0xB0,0x02,0x3C, ++0xD0,0xFF,0xBD,0x27, ++0x18,0x03,0x42,0x34, ++0xC8,0x2A,0x63,0x24, ++0x24,0x00,0xB3,0xAF, ++0x28,0x00,0xBF,0xAF, ++0x20,0x00,0xB2,0xAF, ++0x1C,0x00,0xB1,0xAF, ++0x18,0x00,0xB0,0xAF, ++0x00,0x00,0x43,0xAC, ++0x02,0x80,0x04,0x3C, ++0xF4,0x5E,0x82,0x90, ++0x00,0x00,0x00,0x00, ++0x12,0x00,0x40,0x10, ++0x02,0x80,0x13,0x3C, ++0x02,0x80,0x02,0x3C, ++0x0D,0x5F,0x43,0x90, ++0x00,0x00,0x00,0x00, ++0x66,0x00,0x60,0x14, ++0x01,0x00,0x04,0x24, ++0x02,0x80,0x02,0x3C, ++0x16,0x5F,0x44,0xA0, ++0x02,0x80,0x03,0x3C, ++0xF5,0x5E,0x64,0x90, ++0x01,0x00,0x05,0x24, ++0x64,0x31,0x00,0x0C, ++0xFF,0x00,0x84,0x30, ++0x02,0x80,0x02,0x3C, ++0x74,0x57,0x43,0x8C, ++0x74,0x57,0x42,0x24, ++0xA7,0x00,0x62,0x10, ++0x02,0x80,0x13,0x3C, ++0x00,0x60,0x01,0x40, ++0x01,0x00,0x21,0x34, ++0x00,0x60,0x81,0x40, ++0x2A,0xB0,0x02,0x3C, ++0x36,0x00,0x42,0x34, ++0x00,0x00,0x43,0x90, ++0x30,0x1F,0x66,0x26, ++0x00,0x38,0xC5,0x8C, ++0xC0,0x18,0x03,0x00, ++0x23,0xB0,0x04,0x3C, ++0xF0,0x07,0x63,0x30, ++0xFF,0x1F,0x02,0x3C, ++0x21,0x18,0x64,0x00, ++0xFF,0xFF,0x42,0x34, ++0x24,0x20,0x62,0x00, ++0x23,0x88,0x85,0x00, ++0x00,0x04,0x22,0x26, ++0x2B,0x28,0x85,0x00, ++0xA4,0x37,0xC3,0x8C, ++0x0B,0x88,0x45,0x00, ++0xE1,0x01,0x22,0x2E, ++0xA0,0x37,0xC3,0xAC, ++0x04,0x38,0xC4,0xAC, ++0xAA,0x37,0xC0,0xA4, ++0x14,0x00,0x40,0x14, ++0xA9,0x37,0xC0,0xA0, ++0x20,0xFE,0x82,0x24, ++0x20,0x02,0x83,0x24, ++0x0A,0x18,0x45,0x00, ++0x23,0x10,0x02,0x3C, ++0xFF,0x03,0x42,0x34, ++0x2B,0x10,0x43,0x00, ++0x21,0x28,0x60,0x00, ++0x34,0x00,0x40,0x14, ++0x00,0x38,0xC3,0xAC, ++0x04,0x38,0xC2,0x8C, ++0x00,0x00,0x00,0x00, ++0x2B,0x18,0x45,0x00, ++0x23,0x88,0x45,0x00, ++0x03,0x00,0x60,0x10, ++0xE1,0x01,0x22,0x2E, ++0x00,0x04,0x31,0x26, ++0xE1,0x01,0x22,0x2E, ++0x0E,0x00,0x40,0x10, ++0x30,0x1F,0x70,0x26, ++0x30,0x1F,0x70,0x26, ++0x04,0x38,0x03,0x8E, ++0x00,0x38,0x04,0x8E, ++0x00,0x00,0x00,0x00, ++0x2B,0x10,0x83,0x00, ++0x2E,0x00,0x40,0x14, ++0x2B,0x10,0x64,0x00, ++0x5A,0x00,0x40,0x14, ++0x25,0xB0,0x02,0x3C, ++0x80,0x00,0x03,0x24, ++0xD0,0x03,0x42,0x34, ++0x00,0x00,0x43,0xAC, ++0x30,0x1F,0x70,0x26, ++0x00,0x38,0x03,0x96, ++0x2A,0xB0,0x02,0x3C, ++0x35,0x00,0x42,0x34, ++0xC2,0x88,0x03,0x00, ++0x00,0x00,0x51,0xA0, ++0x5D,0x27,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0xAA,0x37,0x03,0x96, ++0x25,0xB0,0x02,0x3C, ++0xB0,0x03,0x42,0x34, ++0x00,0x00,0x43,0xAC, ++0x00,0x60,0x01,0x40, ++0x01,0x00,0x21,0x34, ++0x01,0x00,0x21,0x38, ++0x00,0x60,0x81,0x40, ++0xD0,0x1B,0x02,0x8E, ++0x80,0x00,0x03,0x3C, ++0x41,0xB0,0x04,0x3C, ++0x25,0x10,0x43,0x00, ++0x00,0x00,0x82,0xAC, ++0x28,0x00,0xBF,0x8F, ++0xD0,0x1B,0x02,0xAE, ++0x24,0x00,0xB3,0x8F, ++0x20,0x00,0xB2,0x8F, ++0x1C,0x00,0xB1,0x8F, ++0x18,0x00,0xB0,0x8F, ++0x08,0x00,0xE0,0x03, ++0x30,0x00,0xBD,0x27, ++0x00,0xFC,0xA5,0x24, ++0xF6,0x0A,0x00,0x08, ++0x00,0x38,0xC5,0xAC, ++0x17,0x30,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x9F,0xFF,0x40,0x10, ++0x00,0x00,0x00,0x00, ++0x0D,0x30,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0xCF,0x0A,0x00,0x08, ++0x02,0x80,0x02,0x3C, ++0xA0,0x37,0x05,0x8E, ++0x21,0x30,0x80,0x00, ++0xFF,0xFF,0x27,0x32, ++0x09,0x00,0x04,0x24, ++0x73,0x01,0x00,0x0C, ++0x10,0x00,0xA0,0xAF, ++0xA0,0x37,0x03,0x8E, ++0xAA,0x37,0x05,0x96, ++0x00,0x38,0x02,0x8E, ++0x21,0x18,0x71,0x00, ++0x21,0x28,0x25,0x02, ++0x21,0x10,0x51,0x00, ++0x09,0x00,0x04,0x24, ++0x00,0x38,0x02,0xAE, ++0xA0,0x37,0x03,0xAE, ++0xB0,0x01,0x00,0x0C, ++0xAA,0x37,0x05,0xA6, ++0x30,0x1F,0x70,0x26, ++0x00,0x38,0x03,0x96, ++0x2A,0xB0,0x02,0x3C, ++0x35,0x00,0x42,0x34, ++0xC2,0x88,0x03,0x00, ++0x00,0x00,0x51,0xA0, ++0x5D,0x27,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0xAA,0x37,0x03,0x96, ++0x25,0xB0,0x02,0x3C, ++0xB0,0x03,0x42,0x34, ++0x00,0x00,0x43,0xAC, ++0x00,0x60,0x01,0x40, ++0x01,0x00,0x21,0x34, ++0x01,0x00,0x21,0x38, ++0x00,0x60,0x81,0x40, ++0xD0,0x1B,0x02,0x8E, ++0x80,0x00,0x03,0x3C, ++0x41,0xB0,0x04,0x3C, ++0x25,0x10,0x43,0x00, ++0x00,0x00,0x82,0xAC, ++0x28,0x00,0xBF,0x8F, ++0xD0,0x1B,0x02,0xAE, ++0x24,0x00,0xB3,0x8F, ++0x20,0x00,0xB2,0x8F, ++0x1C,0x00,0xB1,0x8F, ++0x18,0x00,0xB0,0x8F, ++0x08,0x00,0xE0,0x03, ++0x30,0x00,0xBD,0x27, ++0x08,0x38,0x02,0x8E, ++0xA0,0x37,0x05,0x8E, ++0x21,0x30,0x80,0x00, ++0x23,0x88,0x44,0x00, ++0xFF,0xFF,0x27,0x32, ++0x09,0x00,0x04,0x24, ++0x73,0x01,0x00,0x0C, ++0x10,0x00,0xA0,0xAF, ++0xA0,0x37,0x03,0x8E, ++0xAA,0x37,0x02,0x96, ++0x04,0x38,0x12,0x96, ++0x21,0x18,0x71,0x00, ++0x21,0x10,0x22,0x02, ++0x23,0x10,0x11,0x3C, ++0xA0,0x37,0x03,0xAE, ++0xAA,0x37,0x02,0xA6, ++0x15,0x00,0x40,0x16, ++0x00,0x38,0x11,0xAE, ++0x09,0x00,0x04,0x24, ++0xB0,0x01,0x00,0x0C, ++0x30,0x1F,0x70,0x26, ++0x46,0x0B,0x00,0x08, ++0x00,0x00,0x00,0x00, ++0x17,0x30,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x57,0xFF,0x40,0x10, ++0x30,0x1F,0x63,0x26, ++0x2A,0x1C,0x62,0x90, ++0x00,0x00,0x00,0x00, ++0x53,0xFF,0x40,0x10, ++0x00,0x00,0x00,0x00, ++0x50,0x39,0x64,0x94, ++0x2A,0x1C,0x60,0xA0, ++0x00,0xC0,0x84,0x24, ++0xC2,0x34,0x00,0x0C, ++0xFF,0xFF,0x84,0x30, ++0xD3,0x0A,0x00,0x08, ++0x00,0x00,0x00,0x00, ++0xB0,0x01,0x00,0x0C, ++0x09,0x00,0x04,0x24, ++0xA0,0x37,0x05,0x8E, ++0x09,0x00,0x04,0x24, ++0x23,0x10,0x06,0x3C, ++0x21,0x38,0x40,0x02, ++0x73,0x01,0x00,0x0C, ++0x10,0x00,0xA0,0xAF, ++0xA0,0x37,0x03,0x8E, ++0xAA,0x37,0x02,0x96, ++0x21,0x20,0x51,0x02, ++0x21,0x18,0x72,0x00, ++0x21,0x10,0x42,0x02, ++0x00,0x38,0x04,0xAE, ++0x09,0x00,0x04,0x24, ++0xA0,0x37,0x03,0xAE, ++0x75,0x0B,0x00,0x08, ++0xAA,0x37,0x02,0xA6, ++0xFF,0x00,0x86,0x30, ++0x02,0x80,0x02,0x3C, ++0x40,0x00,0xC3,0x2C, ++0x4A,0xF3,0x47,0x90, ++0x00,0x00,0x63,0x38, ++0x3F,0x00,0x02,0x24, ++0x0A,0x30,0x43,0x00, ++0x01,0x00,0x02,0x24, ++0x08,0x0E,0x04,0x24, ++0x00,0x7F,0x05,0x24, ++0x03,0x00,0xE2,0x10, ++0x31,0x00,0xC3,0x2C, ++0xA9,0x45,0x00,0x08, ++0x00,0x00,0x00,0x00, ++0x30,0x00,0x02,0x24, ++0xA9,0x45,0x00,0x08, ++0x0A,0x30,0x43,0x00, ++0xC0,0xFF,0xBD,0x27, ++0x02,0x80,0x03,0x3C, ++0x38,0x00,0xB4,0xAF, ++0x34,0x00,0xB3,0xAF, ++0x30,0x00,0xB2,0xAF, ++0x2C,0x00,0xB1,0xAF, ++0x28,0x00,0xB0,0xAF, ++0x28,0xEA,0x62,0x24, ++0x3C,0x00,0xBF,0xAF, ++0x0A,0x00,0x4A,0x94, ++0x02,0x00,0x48,0x94, ++0x06,0x00,0x49,0x94, ++0xFF,0x00,0x84,0x30, ++0xFF,0x00,0xA5,0x30, ++0x28,0xEA,0x6B,0x94, ++0x04,0x00,0x4C,0x94, ++0x08,0x00,0x4D,0x94, ++0x00,0x1C,0x05,0x00, ++0x00,0x14,0x04,0x00, ++0x00,0x3E,0x05,0x00, ++0x00,0x36,0x04,0x00, ++0x25,0x38,0xE3,0x00, ++0x25,0x30,0xC2,0x00, ++0x00,0x44,0x08,0x00, ++0x00,0x12,0x05,0x00, ++0x00,0x4C,0x09,0x00, ++0x00,0x54,0x0A,0x00, ++0x00,0x1A,0x04,0x00, ++0x25,0x38,0xE2,0x00, ++0x25,0x40,0x0B,0x01, ++0x25,0x48,0x2C,0x01, ++0x25,0x50,0x4D,0x01, ++0x25,0x30,0xC3,0x00, ++0x02,0x80,0x02,0x3C, ++0x10,0x00,0xA8,0xAF, ++0x14,0x00,0xA9,0xAF, ++0x18,0x00,0xAA,0xAF, ++0x25,0x98,0xE5,0x00, ++0x25,0x90,0xC4,0x00, ++0x30,0x1F,0x54,0x24, ++0x21,0x80,0x00,0x00, ++0x10,0x00,0xB1,0x27, ++0x02,0x00,0x02,0x2E, ++0x32,0x00,0x40,0x10, ++0x80,0x10,0x10,0x00, ++0x21,0x10,0x54,0x00, ++0xF0,0x1C,0x43,0x8C, ++0x00,0x00,0x00,0x00, ++0x21,0x40,0x73,0x00, ++0x21,0x38,0x00,0x00, ++0x7F,0x00,0x09,0x24, ++0xC0,0x20,0x07,0x00, ++0x04,0x10,0x89,0x00, ++0x24,0x10,0x48,0x00, ++0x06,0x10,0x82,0x00, ++0x01,0x00,0xE5,0x24, ++0xFF,0x00,0x43,0x30, ++0x21,0x30,0x27,0x02, ++0x40,0x00,0x63,0x2C, ++0xFF,0x00,0xA7,0x30, ++0x02,0x00,0x60,0x14, ++0x04,0x00,0xE4,0x2C, ++0x3F,0x00,0x02,0x24, ++0xF3,0xFF,0x80,0x14, ++0x10,0x00,0xC2,0xA0, ++0x23,0x00,0xA6,0x93, ++0x22,0x00,0xA2,0x93, ++0x21,0x00,0xA5,0x93, ++0x40,0x18,0x10,0x00, ++0x00,0x14,0x02,0x00, ++0x21,0x18,0x71,0x00, ++0x20,0x00,0xA7,0x93, ++0x00,0x36,0x06,0x00, ++0x25,0x30,0xC2,0x00, ++0x00,0x2A,0x05,0x00, ++0x00,0x00,0x64,0x94, ++0x25,0x30,0xC5,0x00, ++0x7F,0x7F,0x05,0x3C, ++0x25,0x30,0xC7,0x00, ++0xA9,0x45,0x00,0x0C, ++0x7F,0x7F,0xA5,0x34, ++0x01,0x00,0x02,0x26, ++0xFF,0x00,0x50,0x30, ++0x06,0x00,0x03,0x2E, ++0xD5,0xFF,0x60,0x14, ++0x00,0x00,0x00,0x00, ++0x3C,0x00,0xBF,0x8F, ++0x38,0x00,0xB4,0x8F, ++0x34,0x00,0xB3,0x8F, ++0x30,0x00,0xB2,0x8F, ++0x2C,0x00,0xB1,0x8F, ++0x28,0x00,0xB0,0x8F, ++0x08,0x00,0xE0,0x03, ++0x40,0x00,0xBD,0x27, ++0x21,0x10,0x54,0x00, ++0xF0,0x1C,0x43,0x8C, ++0xDC,0x0B,0x00,0x08, ++0x21,0x40,0x72,0x00, ++0xD8,0xFF,0xBD,0x27, ++0x02,0x80,0x09,0x3C, ++0x1C,0x00,0xB3,0xAF, ++0x10,0x00,0xB0,0xAF, ++0x20,0x00,0xBF,0xAF, ++0x18,0x00,0xB2,0xAF, ++0x14,0x00,0xB1,0xAF, ++0x30,0x1F,0x27,0x25, ++0x02,0x80,0x02,0x3C, ++0xB0,0x1B,0xE3,0x94, ++0xDE,0x5D,0x46,0x90, ++0xFF,0x00,0x90,0x30, ++0x00,0x10,0x63,0x30, ++0x20,0x00,0xC5,0x30, ++0x21,0x20,0x07,0x02, ++0x10,0x00,0xC6,0x30, ++0x02,0x00,0x60,0x14, ++0x3F,0x00,0x13,0x24, ++0x63,0x1D,0x93,0x90, ++0x28,0x00,0xC0,0x10, ++0x30,0x1F,0x22,0x25, ++0x8D,0x1D,0x82,0x90, ++0x7F,0x1D,0x83,0x90, ++0x00,0x00,0x00,0x00, ++0x23,0x10,0x43,0x00, ++0x00,0x46,0x02,0x00, ++0x03,0x46,0x08,0x00, ++0xFF,0x00,0x71,0x30, ++0x30,0x1F,0x27,0x25, ++0x0F,0x00,0x08,0x31, ++0x21,0x30,0x00,0x01, ++0x21,0x40,0x07,0x02, ++0xB7,0x1D,0x02,0x91, ++0xB0,0x1B,0xE3,0x84, ++0x0F,0x00,0x05,0x3C, ++0x0F,0x00,0x42,0x30, ++0x21,0x10,0x51,0x00, ++0x0C,0x08,0x04,0x24, ++0x00,0xFF,0xA5,0x34, ++0x06,0x00,0x60,0x04, ++0xFF,0x00,0x52,0x30, ++0xC5,0x1D,0x02,0x91, ++0x00,0x00,0x00,0x00, ++0x0F,0x00,0x42,0x30, ++0x21,0x10,0x51,0x00, ++0xFF,0x00,0x51,0x30, ++0xA9,0x45,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x9A,0x0B,0x00,0x0C, ++0x21,0x20,0x60,0x02, ++0x21,0x20,0x20,0x02, ++0x21,0x28,0x40,0x02, ++0x21,0x30,0x00,0x02, ++0x20,0x00,0xBF,0x8F, ++0x1C,0x00,0xB3,0x8F, ++0x18,0x00,0xB2,0x8F, ++0x14,0x00,0xB1,0x8F, ++0x10,0x00,0xB0,0x8F, ++0xAB,0x0B,0x00,0x08, ++0x28,0x00,0xBD,0x27, ++0xDF,0xFF,0xA0,0x10, ++0x21,0x18,0x02,0x02, ++0xA9,0x1D,0x62,0x90, ++0x9B,0x1D,0x63,0x90, ++0x26,0x0C,0x00,0x08, ++0x23,0x10,0x43,0x00, ++0xE0,0xFF,0xBD,0x27, ++0x14,0x00,0xB1,0xAF, ++0x02,0x80,0x02,0x3C, ++0x18,0x00,0xBF,0xAF, ++0x10,0x00,0xB0,0xAF, ++0xE9,0x5D,0x43,0x90, ++0x01,0x00,0x02,0x24, ++0x0D,0x00,0x62,0x10, ++0xFF,0x00,0x91,0x30, ++0x0D,0x0C,0x00,0x0C, ++0x21,0x20,0x20,0x02, ++0x21,0x30,0x20,0x02, ++0x18,0x00,0x04,0x24, ++0x5F,0x47,0x00,0x0C, ++0xFF,0x03,0x05,0x24, ++0x18,0x00,0xBF,0x8F, ++0x14,0x00,0xB1,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x0A,0x00,0x04,0x24, ++0x25,0x22,0x00,0x08, ++0x20,0x00,0xBD,0x27, ++0x1A,0x00,0x23,0x12, ++0x0B,0x00,0x02,0x24, ++0x1D,0x00,0x22,0x12, ++0x0F,0x00,0x05,0x3C, ++0xFF,0xFF,0xA5,0x34, ++0x15,0x00,0x04,0x24, ++0xF4,0xF8,0x06,0x34, ++0x5F,0x47,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x02,0x80,0x02,0x3C, ++0x48,0xF3,0x44,0x90, ++0xFE,0x00,0x03,0x24, ++0xE9,0xFF,0x83,0x14, ++0x0F,0x00,0x10,0x3C, ++0xFF,0xFF,0x05,0x36, ++0x8A,0x47,0x00,0x0C, ++0x15,0x00,0x04,0x24, ++0xFF,0x00,0x46,0x30, ++0x00,0xFF,0x03,0x36, ++0x24,0x10,0x43,0x00, ++0x01,0x00,0xC6,0x24, ++0x25,0x30,0x46,0x00, ++0xFF,0xFF,0x05,0x36, ++0x5F,0x47,0x00,0x0C, ++0x15,0x00,0x04,0x24, ++0x5B,0x0C,0x00,0x08, ++0x21,0x30,0x20,0x02, ++0x0F,0x00,0x05,0x3C, ++0xFF,0xFF,0xA5,0x34, ++0x15,0x00,0x04,0x24, ++0x6B,0x0C,0x00,0x08, ++0xF4,0xA8,0x06,0x34, ++0xFF,0xFF,0xA5,0x34, ++0x15,0x00,0x04,0x24, ++0x6B,0x0C,0x00,0x08, ++0xF5,0xF8,0x06,0x34, ++0xFC,0x00,0x84,0x30, ++0x50,0x00,0x02,0x24, ++0x11,0x00,0x82,0x10, ++0x05,0x00,0x03,0x24, ++0x51,0x00,0x82,0x28, ++0x10,0x00,0x40,0x10, ++0xA0,0x00,0x02,0x24, ++0x20,0x00,0x02,0x24, ++0x0B,0x00,0x82,0x10, ++0x02,0x00,0x03,0x24, ++0x21,0x00,0x82,0x28, ++0x15,0x00,0x40,0x14, ++0x30,0x00,0x02,0x24, ++0x06,0x00,0x82,0x10, ++0x03,0x00,0x03,0x24, ++0x04,0x00,0x03,0x24, ++0x40,0x00,0x02,0x24, ++0x02,0x00,0x82,0x10, ++0x00,0x00,0x00,0x00, ++0x0C,0x00,0x03,0x24, ++0x08,0x00,0xE0,0x03, ++0x21,0x10,0x60,0x00, ++0xFD,0xFF,0x82,0x10, ++0x08,0x00,0x03,0x24, ++0xA1,0x00,0x82,0x28, ++0x0C,0x00,0x40,0x10, ++0xC0,0x00,0x02,0x24, ++0x80,0x00,0x02,0x24, ++0xF7,0xFF,0x82,0x10, ++0x06,0x00,0x03,0x24, ++0x07,0x00,0x03,0x24, ++0x99,0x0C,0x00,0x08, ++0x90,0x00,0x02,0x24, ++0xF2,0xFF,0x80,0x10, ++0x21,0x18,0x00,0x00, ++0x01,0x00,0x03,0x24, ++0x99,0x0C,0x00,0x08, ++0x10,0x00,0x02,0x24, ++0xED,0xFF,0x82,0x10, ++0x0A,0x00,0x03,0x24, ++0xC1,0x00,0x82,0x28, ++0x04,0x00,0x40,0x10, ++0x00,0x00,0x00,0x00, ++0x09,0x00,0x03,0x24, ++0x99,0x0C,0x00,0x08, ++0xB0,0x00,0x02,0x24, ++0x0B,0x00,0x03,0x24, ++0x99,0x0C,0x00,0x08, ++0xD0,0x00,0x02,0x24, ++0xD8,0xFF,0xBD,0x27, ++0x1C,0x00,0xB3,0xAF, ++0x18,0x00,0xB2,0xAF, ++0x14,0x00,0xB1,0xAF, ++0x20,0x00,0xBF,0xAF, ++0x10,0x00,0xB0,0xAF, ++0x08,0x00,0x83,0x8C, ++0x25,0xB0,0x02,0x3C, ++0xB0,0x03,0x42,0x34, ++0x00,0x00,0x43,0xAC, ++0x08,0x00,0x90,0x94, ++0x02,0x80,0x02,0x3C, ++0x21,0x98,0x80,0x00, ++0x25,0x80,0x02,0x02, ++0x21,0x20,0x00,0x02, ++0xFF,0x00,0xB2,0x30, ++0xFF,0x00,0xD1,0x30, ++0x21,0x28,0x00,0x00, ++0x08,0x52,0x00,0x0C, ++0x08,0x00,0x06,0x24, ++0x08,0x00,0x04,0x8E, ++0x04,0x00,0x05,0x8E, ++0xFF,0xDF,0x02,0x3C, ++0xFF,0xFF,0x42,0x34, ++0xFF,0xE0,0x03,0x24, ++0x24,0x20,0x82,0x00, ++0x00,0x40,0x02,0x3C, ++0x10,0x00,0x06,0x8E, ++0x24,0x28,0xA3,0x00, ++0x25,0x20,0x82,0x00, ++0x3F,0xFF,0x02,0x3C, ++0x0C,0x00,0x67,0x8E, ++0x7F,0xFF,0x03,0x24, ++0xFF,0xFF,0x42,0x34, ++0x00,0x12,0xA5,0x34, ++0x01,0x00,0x52,0x32, ++0x03,0x00,0x31,0x32, ++0x24,0x20,0x83,0x00, ++0x24,0x28,0xA2,0x00, ++0xC0,0x91,0x12,0x00, ++0x80,0x8D,0x11,0x00, ++0x00,0x80,0x02,0x3C, ++0x25,0x30,0xC2,0x00, ++0x25,0x20,0x92,0x00, ++0x25,0x28,0xB1,0x00, ++0x20,0x00,0x02,0x24, ++0x10,0x00,0x06,0xAE, ++0x02,0x00,0x02,0xA2, ++0x08,0x00,0x04,0xAE, ++0x04,0x00,0x05,0xAE, ++0x00,0x00,0x07,0xA6, ++0x02,0x80,0x02,0x3C, ++0xE0,0x3A,0x43,0x94, ++0xFB,0xFF,0x02,0x3C, ++0xFF,0xFF,0x42,0x34, ++0xC2,0x1B,0x03,0x00, ++0x24,0x30,0xC2,0x00, ++0x80,0x1C,0x03,0x00, ++0x25,0x30,0xC3,0x00, ++0x14,0x00,0x05,0x8E, ++0x82,0x24,0x06,0x00, ++0x01,0x00,0x84,0x30, ++0x0C,0x00,0x02,0x24, ++0x0A,0x10,0x04,0x00, ++0xFF,0x81,0x03,0x24, ++0x24,0x28,0xA3,0x00, ++0x40,0x12,0x02,0x00, ++0x25,0x28,0xA2,0x00, ++0x14,0x00,0x05,0xAE, ++0x10,0x00,0x06,0xAE, ++0x00,0x60,0x03,0x40, ++0x01,0x00,0x61,0x34, ++0x01,0x00,0x21,0x38, ++0x00,0x60,0x81,0x40, ++0x02,0x80,0x02,0x3C, ++0x74,0x57,0x42,0x24, ++0x04,0x00,0x44,0x8C, ++0x00,0x00,0x62,0xAE, ++0x04,0x00,0x53,0xAC, ++0x00,0x00,0x93,0xAC, ++0x04,0x00,0x64,0xAE, ++0x00,0x60,0x83,0x40, ++0x20,0x00,0xBF,0x8F, ++0x1C,0x00,0xB3,0x8F, ++0x18,0x00,0xB2,0x8F, ++0x14,0x00,0xB1,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x08,0x00,0xE0,0x03, ++0x28,0x00,0xBD,0x27, ++0xD8,0xFF,0xBD,0x27, ++0x14,0x00,0xB1,0xAF, ++0x20,0x00,0xBF,0xAF, ++0x1C,0x00,0xB3,0xAF, ++0x18,0x00,0xB2,0xAF, ++0x10,0x00,0xB0,0xAF, ++0xFF,0xFF,0x83,0x30, ++0xFF,0x00,0xB1,0x30, ++0x00,0x60,0x12,0x40, ++0x01,0x00,0x41,0x36, ++0x01,0x00,0x21,0x38, ++0x00,0x60,0x81,0x40, ++0x02,0x80,0x13,0x3C, ++0x30,0x1F,0x70,0x26, ++0xB0,0x1B,0x02,0x96, ++0x00,0x00,0x00,0x00, ++0x00,0x80,0x42,0x30, ++0x2F,0x00,0x43,0x10, ++0x02,0x80,0x04,0x3C, ++0x00,0x80,0x02,0x34, ++0x50,0xDF,0x84,0x24, ++0x33,0x00,0x62,0x10, ++0x21,0x30,0x20,0x02, ++0x2F,0x55,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x30,0x3B,0x04,0x92, ++0x4F,0x0C,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x25,0xB0,0x03,0x3C, ++0x03,0x02,0x63,0x34, ++0x00,0x00,0x62,0x90, ++0x00,0x08,0x04,0x24, ++0x01,0x00,0x05,0x24, ++0x04,0x00,0x42,0x30, ++0x00,0x00,0x62,0xA0, ++0x1B,0x47,0x00,0x0C, ++0x21,0x30,0x00,0x00, ++0x00,0x09,0x04,0x24, ++0x01,0x00,0x05,0x24, ++0x1B,0x47,0x00,0x0C, ++0x21,0x30,0x00,0x00, ++0x84,0x08,0x04,0x24, ++0xFF,0xFF,0x05,0x24, ++0x1B,0x47,0x00,0x0C, ++0x58,0x00,0x06,0x24, ++0x00,0x0C,0x05,0x24, ++0x01,0x00,0x06,0x24, ++0x5F,0x47,0x00,0x0C, ++0x18,0x00,0x04,0x24, ++0xB0,0x1B,0x02,0x96, ++0x8F,0x3E,0x11,0xA2, ++0xFF,0x7F,0x42,0x30, ++0xB0,0x1B,0x02,0xA6, ++0x30,0x1F,0x62,0x26, ++0x30,0x3B,0x44,0x90, ++0x0D,0x0C,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x00,0x60,0x92,0x40, ++0x20,0x00,0xBF,0x8F, ++0x1C,0x00,0xB3,0x8F, ++0x18,0x00,0xB2,0x8F, ++0x14,0x00,0xB1,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x08,0x00,0xE0,0x03, ++0x28,0x00,0xBD,0x27, ++0x00,0x60,0x92,0x40, ++0x20,0x00,0xBF,0x8F, ++0x1C,0x00,0xB3,0x8F, ++0x18,0x00,0xB2,0x8F, ++0x14,0x00,0xB1,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x08,0x00,0xE0,0x03, ++0x28,0x00,0xBD,0x27, ++0x30,0x3B,0x05,0x92, ++0x02,0x80,0x04,0x3C, ++0x2F,0x55,0x00,0x0C, ++0x30,0xDF,0x84,0x24, ++0x01,0x00,0x02,0x24, ++0x2C,0x00,0x22,0x12, ++0x00,0x00,0x00,0x00, ++0x30,0x3B,0x04,0x92, ++0x00,0x00,0x00,0x00, ++0xFE,0xFF,0x84,0x24, ++0x4F,0x0C,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x25,0xB0,0x07,0x3C, ++0x03,0x02,0xE7,0x34, ++0x00,0x00,0xE2,0x90, ++0xFB,0xFF,0x03,0x24, ++0x00,0x08,0x04,0x24, ++0x24,0x10,0x43,0x00, ++0x00,0x00,0xE2,0xA0, ++0x01,0x00,0x05,0x24, ++0x1B,0x47,0x00,0x0C, ++0x01,0x00,0x06,0x24, ++0x03,0x00,0x30,0x32, ++0x00,0x09,0x04,0x24, ++0x01,0x00,0x05,0x24, ++0x1B,0x47,0x00,0x0C, ++0x01,0x00,0x06,0x24, ++0x00,0x0A,0x04,0x24, ++0x10,0x00,0x05,0x24, ++0x1B,0x47,0x00,0x0C, ++0x42,0x30,0x10,0x00, ++0x21,0x30,0x00,0x02, ++0x00,0x0D,0x04,0x24, ++0x1B,0x47,0x00,0x0C, ++0x00,0x0C,0x05,0x24, ++0x84,0x08,0x04,0x24, ++0xFF,0xFF,0x05,0x24, ++0x1B,0x47,0x00,0x0C, ++0x18,0x00,0x06,0x24, ++0x18,0x00,0x04,0x24, ++0x00,0x0C,0x05,0x24, ++0x5F,0x47,0x00,0x0C, ++0x21,0x30,0x00,0x00, ++0x30,0x1F,0x64,0x26, ++0xB0,0x1B,0x82,0x94, ++0x00,0x80,0x03,0x24, ++0x8F,0x3E,0x91,0xA0, ++0x25,0x10,0x43,0x00, ++0x47,0x0D,0x00,0x08, ++0xB0,0x1B,0x82,0xA4, ++0x30,0x3B,0x04,0x92, ++0x65,0x0D,0x00,0x08, ++0x02,0x00,0x84,0x24, ++0xC8,0xFF,0xBD,0x27, ++0x02,0x80,0x03,0x3C, ++0x34,0x00,0xBF,0xAF, ++0x30,0x00,0xB2,0xAF, ++0x2C,0x00,0xB1,0xAF, ++0x28,0x00,0xB0,0xAF, ++0x34,0xEA,0x62,0x24, ++0x01,0x00,0x44,0x90, ++0x05,0x00,0x45,0x90, ++0x09,0x00,0x46,0x90, ++0x0D,0x00,0x47,0x90, ++0x04,0x00,0x51,0x90, ++0x08,0x00,0x50,0x90, ++0x34,0xEA,0x72,0x90, ++0x02,0x00,0x4F,0x90, ++0x0C,0x00,0x43,0x90, ++0x06,0x00,0x4E,0x90, ++0x0A,0x00,0x4D,0x90, ++0x0E,0x00,0x48,0x90, ++0x03,0x00,0x49,0x90, ++0x07,0x00,0x4A,0x90, ++0x0B,0x00,0x4B,0x90, ++0x0F,0x00,0x4C,0x90, ++0x00,0x22,0x04,0x00, ++0x00,0x2A,0x05,0x00, ++0x00,0x32,0x06,0x00, ++0x00,0x3A,0x07,0x00, ++0x02,0x80,0x18,0x3C, ++0x25,0x28,0xB1,0x00, ++0x25,0x30,0xD0,0x00, ++0x25,0x38,0xE3,0x00, ++0x25,0x20,0x92,0x00, ++0x11,0x00,0x51,0x90, ++0x10,0x00,0x50,0x90, ++0x30,0x1F,0x03,0x27, ++0x00,0x7C,0x0F,0x00, ++0x00,0x74,0x0E,0x00, ++0x00,0x6C,0x0D,0x00, ++0x00,0x44,0x08,0x00, ++0x25,0x78,0xE4,0x01, ++0x25,0x70,0xC5,0x01, ++0x25,0x68,0xA6,0x01, ++0x25,0x40,0x07,0x01, ++0x5A,0x3E,0x66,0x90, ++0x00,0x4E,0x09,0x00, ++0x00,0x56,0x0A,0x00, ++0x00,0x5E,0x0B,0x00, ++0x00,0x66,0x0C,0x00, ++0x25,0x48,0x2F,0x01, ++0x25,0x50,0x4E,0x01, ++0x25,0x58,0x6D,0x01, ++0x25,0x60,0x88,0x01, ++0x25,0xB0,0x05,0x3C, ++0x37,0x02,0xA5,0x34, ++0x10,0x00,0xA9,0xAF, ++0x14,0x00,0xAA,0xAF, ++0x18,0x00,0xAB,0xAF, ++0x1C,0x00,0xAC,0xAF, ++0x20,0x00,0xB0,0xA3, ++0x21,0x00,0xB1,0xA3, ++0x03,0x00,0xC7,0x30, ++0x00,0x00,0xA4,0x90, ++0x02,0x00,0xE2,0x24, ++0x01,0x00,0x03,0x24, ++0x04,0x18,0x43,0x00, ++0x1C,0x00,0xC6,0x30, ++0xF8,0xFF,0x02,0x24, ++0x24,0x20,0x82,0x00, ++0xFF,0x00,0x67,0x30, ++0x82,0x30,0x06,0x00, ++0x10,0x00,0xE3,0x2C, ++0x25,0x20,0x86,0x00, ++0x0F,0x00,0x02,0x24, ++0x00,0x00,0xA4,0xA0, ++0x0A,0x38,0x43,0x00, ++0x21,0x28,0x00,0x00, ++0x10,0x00,0xA3,0x27, ++0x21,0x30,0x65,0x00, ++0x00,0x00,0xC2,0x90, ++0x01,0x00,0xA5,0x24, ++0x2B,0x10,0xE2,0x00, ++0x02,0x00,0x40,0x10, ++0x11,0x00,0xA4,0x2C, ++0x00,0x00,0xC7,0xA0, ++0xF8,0xFF,0x80,0x14, ++0x21,0x30,0x60,0x00, ++0x21,0x28,0x00,0x00, ++0x25,0xB0,0x07,0x3C, ++0x01,0x00,0xC2,0x90, ++0x00,0x00,0xC3,0x90, ++0x21,0x20,0xA7,0x00, ++0x00,0x11,0x02,0x00, ++0x25,0x10,0x43,0x00, ++0x01,0x00,0xA5,0x24, ++0xFF,0x00,0x42,0x30, ++0x08,0x00,0xA3,0x2C, ++0xA8,0x01,0x82,0xA0, ++0xF6,0xFF,0x60,0x14, ++0x02,0x00,0xC6,0x24, ++0x21,0x00,0xA2,0x93, ++0x20,0x00,0xA4,0x93, ++0x02,0x80,0x03,0x3C, ++0x00,0x11,0x02,0x00, ++0xF1,0x5D,0x65,0x90, ++0x25,0x10,0x44,0x00, ++0xFF,0x00,0x42,0x30, ++0xA7,0x01,0xE3,0x34, ++0x00,0x00,0x62,0xA0, ++0x01,0x00,0x02,0x24, ++0x07,0x00,0xA2,0x10, ++0x30,0x1F,0x03,0x27, ++0x34,0x00,0xBF,0x8F, ++0x30,0x00,0xB2,0x8F, ++0x2C,0x00,0xB1,0x8F, ++0x28,0x00,0xB0,0x8F, ++0x08,0x00,0xE0,0x03, ++0x38,0x00,0xBD,0x27, ++0x58,0x3E,0x62,0x94, ++0x00,0x00,0x00,0x00, ++0x02,0x00,0x42,0x30, ++0xF6,0xFF,0x40,0x10, ++0x00,0x00,0x00,0x00, ++0x79,0x3E,0x63,0x90, ++0x00,0x00,0x00,0x00, ++0x04,0x00,0x62,0x30, ++0xF1,0xFF,0x40,0x10, ++0x03,0x00,0x63,0x30, ++0x0C,0x00,0x65,0x10, ++0x03,0x00,0x02,0x24, ++0x05,0x00,0x62,0x10, ++0x21,0x20,0x00,0x00, ++0x12,0x0D,0x00,0x0C, ++0x21,0x28,0x00,0x00, ++0xFF,0x0D,0x00,0x08, ++0x00,0x00,0x00,0x00, ++0x00,0x80,0x04,0x34, ++0x12,0x0D,0x00,0x0C, ++0x02,0x00,0x05,0x24, ++0xFF,0x0D,0x00,0x08, ++0x00,0x00,0x00,0x00, ++0x00,0x80,0x04,0x34, ++0x12,0x0D,0x00,0x0C, ++0x01,0x00,0x05,0x24, ++0xFF,0x0D,0x00,0x08, ++0x00,0x00,0x00,0x00, ++0xE8,0xFF,0xBD,0x27, ++0x02,0x80,0x06,0x3C, ++0x14,0x00,0xBF,0xAF, ++0x10,0x00,0xB0,0xAF, ++0x88,0x58,0xC2,0x24, ++0x01,0x00,0x44,0x90, ++0x88,0x58,0xC3,0x90, ++0x02,0x00,0x45,0x90, ++0x03,0x00,0x46,0x90, ++0x05,0x00,0x47,0x90, ++0x04,0x00,0x48,0x90, ++0x00,0x22,0x04,0x00, ++0x25,0x18,0x64,0x00, ++0x00,0x2C,0x05,0x00, ++0x25,0xB0,0x10,0x3C, ++0x25,0x18,0x65,0x00, ++0x00,0x36,0x06,0x00, ++0x00,0x3A,0x07,0x00, ++0x25,0x18,0x66,0x00, ++0x58,0x00,0x02,0x36, ++0x5C,0x00,0x05,0x36, ++0x25,0x40,0x07,0x01, ++0x02,0x80,0x04,0x3C, ++0x00,0x00,0x43,0xAC, ++0x84,0x58,0x84,0x24, ++0x00,0x00,0xA8,0xAC, ++0x19,0x4F,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x94,0x00,0x03,0x36, ++0x00,0x00,0x62,0xA4, ++0x48,0x00,0x10,0x36, ++0x00,0x00,0x02,0x8E, ++0x04,0x00,0x03,0x3C, ++0x14,0x00,0xBF,0x8F, ++0x25,0x10,0x43,0x00, ++0x00,0x00,0x02,0xAE, ++0x10,0x00,0xB0,0x8F, ++0x08,0x00,0xE0,0x03, ++0x18,0x00,0xBD,0x27, ++0xE0,0xFF,0xBD,0x27, ++0x18,0x00,0xB2,0xAF, ++0x21,0x90,0x80,0x00, ++0x18,0x02,0x04,0x24, ++0x14,0x00,0xB1,0xAF, ++0x1C,0x00,0xBF,0xAF, ++0x25,0x24,0x00,0x0C, ++0x10,0x00,0xB0,0xAF, ++0x02,0x80,0x05,0x3C, ++0x02,0x80,0x04,0x3C, ++0x21,0x88,0x40,0x00, ++0x84,0x58,0xA5,0x24, ++0xDC,0x01,0x06,0x24, ++0x18,0x00,0x40,0x10, ++0x98,0xDF,0x84,0x24, ++0x08,0x00,0x50,0x94, ++0xF8,0x01,0x02,0x24, ++0x0C,0x00,0x22,0xAE, ++0x02,0x80,0x02,0x3C, ++0x0A,0x00,0x03,0x24, ++0x25,0x80,0x02,0x02, ++0x14,0x00,0x23,0xAE, ++0x3C,0x00,0x04,0x26, ++0x10,0x52,0x00,0x0C, ++0x20,0x00,0x10,0x26, ++0x18,0x00,0x12,0xAE, ++0x21,0x20,0x20,0x02, ++0x30,0x09,0x00,0x0C, ++0x14,0x00,0x12,0xAE, ++0x02,0x80,0x04,0x3C, ++0x21,0x28,0x40,0x02, ++0x1C,0x00,0xBF,0x8F, ++0x18,0x00,0xB2,0x8F, ++0x14,0x00,0xB1,0x8F, ++0x10,0x00,0xB0,0x8F, ++0xA4,0xDF,0x84,0x24, ++0x2F,0x55,0x00,0x08, ++0x20,0x00,0xBD,0x27, ++0x02,0x80,0x05,0x3C, ++0x1C,0x00,0xBF,0x8F, ++0x18,0x00,0xB2,0x8F, ++0x14,0x00,0xB1,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x5C,0xEA,0xA5,0x24, ++0x2F,0x55,0x00,0x08, ++0x20,0x00,0xBD,0x27, ++0xE0,0xFF,0xBD,0x27, ++0x10,0x00,0xB0,0xAF, ++0x21,0x80,0x80,0x00, ++0x14,0x00,0xB1,0xAF, ++0x18,0x00,0xBF,0xAF, ++0x25,0x24,0x00,0x0C, ++0x28,0x00,0x04,0x24, ++0x02,0x80,0x04,0x3C, ++0x21,0x88,0x40,0x00, ++0x21,0x28,0x00,0x02, ++0x06,0x00,0x06,0x24, ++0x15,0x00,0x40,0x10, ++0xB4,0xDF,0x84,0x24, ++0x08,0x00,0x44,0x94, ++0x08,0x00,0x02,0x24, ++0x0C,0x00,0x22,0xAE, ++0x02,0x80,0x02,0x3C, ++0x0C,0x00,0x03,0x24, ++0x25,0x20,0x82,0x00, ++0x14,0x00,0x23,0xAE, ++0x10,0x52,0x00,0x0C, ++0x20,0x00,0x84,0x24, ++0x30,0x09,0x00,0x0C, ++0x21,0x20,0x20,0x02, ++0x02,0x80,0x04,0x3C, ++0x2F,0x55,0x00,0x0C, ++0xC0,0xDF,0x84,0x24, ++0x21,0x10,0x00,0x00, ++0x18,0x00,0xBF,0x8F, ++0x14,0x00,0xB1,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x08,0x00,0xE0,0x03, ++0x20,0x00,0xBD,0x27, ++0x02,0x80,0x05,0x3C, ++0x2F,0x55,0x00,0x0C, ++0x6C,0xEA,0xA5,0x24, ++0x92,0x0E,0x00,0x08, ++0xFF,0xFF,0x02,0x24, ++0xD8,0xFF,0xBD,0x27, ++0x1C,0x00,0xB3,0xAF, ++0x21,0x98,0x80,0x00, ++0x2C,0x00,0x04,0x24, ++0x18,0x00,0xB2,0xAF, ++0x14,0x00,0xB1,0xAF, ++0x21,0x90,0xA0,0x00, ++0x20,0x00,0xBF,0xAF, ++0x25,0x24,0x00,0x0C, ++0x10,0x00,0xB0,0xAF, ++0x02,0x80,0x04,0x3C, ++0x02,0x80,0x05,0x3C, ++0x21,0x88,0x40,0x00, ++0xD8,0xDF,0x84,0x24, ++0x21,0x30,0x40,0x02, ++0x19,0x00,0x40,0x10, ++0x84,0xEA,0xA5,0x24, ++0x05,0x00,0x65,0x92, ++0x2F,0x55,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x08,0x00,0x30,0x96, ++0x02,0x80,0x02,0x3C, ++0x0B,0x00,0x03,0x24, ++0x25,0x80,0x02,0x02, ++0x20,0x00,0x10,0x26, ++0x0C,0x00,0x02,0x24, ++0x21,0x20,0x00,0x02, ++0x0C,0x00,0x22,0xAE, ++0x14,0x00,0x23,0xAE, ++0x21,0x28,0x60,0x02, ++0x10,0x52,0x00,0x0C, ++0x06,0x00,0x06,0x24, ++0x08,0x00,0x12,0xAE, ++0x21,0x20,0x20,0x02, ++0x20,0x00,0xBF,0x8F, ++0x1C,0x00,0xB3,0x8F, ++0x18,0x00,0xB2,0x8F, ++0x14,0x00,0xB1,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x30,0x09,0x00,0x08, ++0x28,0x00,0xBD,0x27, ++0x02,0x80,0x04,0x3C, ++0x20,0x00,0xBF,0x8F, ++0x1C,0x00,0xB3,0x8F, ++0x18,0x00,0xB2,0x8F, ++0x14,0x00,0xB1,0x8F, ++0x10,0x00,0xB0,0x8F, ++0xCC,0xDF,0x84,0x24, ++0x2F,0x55,0x00,0x08, ++0x28,0x00,0xBD,0x27, ++0xE0,0xFF,0xBD,0x27, ++0x14,0x00,0xB1,0xAF, ++0x18,0x00,0xBF,0xAF, ++0x10,0x00,0xB0,0xAF, ++0x02,0x80,0x02,0x3C, ++0xF6,0x5E,0x43,0x90, ++0x02,0x80,0x11,0x3C, ++0x04,0x00,0x04,0x24, ++0x0F,0x00,0x63,0x30, ++0x04,0x00,0x63,0x28, ++0x36,0x00,0x60,0x14, ++0x01,0x00,0x05,0x24, ++0x02,0x80,0x02,0x3C, ++0x30,0x1F,0x50,0x24, ++0x2C,0xE0,0x22,0x8E, ++0x0F,0x00,0x05,0x3C, ++0xFF,0xFF,0xA5,0x34, ++0x24,0x00,0x04,0x24, ++0x12,0x00,0x40,0x14, ++0x60,0x00,0x06,0x24, ++0x0F,0x00,0x05,0x3C, ++0x5F,0x47,0x00,0x0C, ++0xFF,0xFF,0xA5,0x34, ++0x01,0x00,0x02,0x24, ++0x2C,0xE0,0x22,0xAE, ++0xD0,0x07,0x03,0x24, ++0x02,0x80,0x02,0x3C, ++0x70,0x58,0x43,0xAC, ++0x02,0x80,0x02,0x3C, ++0xF5,0x5E,0x44,0x90, ++0x18,0x00,0xBF,0x8F, ++0x14,0x00,0xB1,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x01,0x00,0x05,0x24, ++0xFF,0x00,0x84,0x30, ++0x64,0x31,0x00,0x08, ++0x20,0x00,0xBD,0x27, ++0x8A,0x47,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x9C,0x3E,0x04,0x92, ++0xFF,0x00,0x43,0x30, ++0x00,0x2C,0x03,0x00, ++0x0A,0x00,0x64,0x10, ++0x9D,0x3E,0x02,0xA2, ++0x02,0x80,0x02,0x3C, ++0x49,0xF3,0x44,0x90, ++0x00,0x00,0x00,0x00, ++0x00,0x22,0x04,0x00, ++0x6B,0x1E,0x00,0x0C, ++0x25,0x20,0xA4,0x00, ++0x9D,0x3E,0x03,0x92, ++0x00,0x00,0x00,0x00, ++0x9C,0x3E,0x03,0xA2, ++0x10,0x27,0x02,0x24, ++0x40,0x39,0x02,0xAE, ++0x02,0x80,0x02,0x3C, ++0xF5,0x5E,0x44,0x90, ++0x2C,0xE0,0x20,0xAE, ++0x18,0x00,0xBF,0x8F, ++0x14,0x00,0xB1,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x01,0x00,0x05,0x24, ++0xFF,0x00,0x84,0x30, ++0x64,0x31,0x00,0x08, ++0x20,0x00,0xBD,0x27, ++0x64,0x31,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0xDB,0x0E,0x00,0x08, ++0x02,0x80,0x02,0x3C, ++0xB8,0xFF,0xBD,0x27, ++0x00,0x01,0x04,0x24, ++0x3C,0x00,0xB3,0xAF, ++0x38,0x00,0xB2,0xAF, ++0x34,0x00,0xB1,0xAF, ++0x40,0x00,0xBF,0xAF, ++0x30,0x00,0xB0,0xAF, ++0x25,0x24,0x00,0x0C, ++0x02,0x80,0x13,0x3C, ++0x02,0x80,0x04,0x3C, ++0x21,0x88,0x40,0x00, ++0xF0,0xDD,0x65,0x26, ++0x06,0x00,0x06,0x24, ++0x0C,0x00,0x52,0x24, ++0x4C,0x00,0x40,0x10, ++0x30,0xE0,0x84,0x24, ++0x08,0x00,0x50,0x94, ++0x02,0x80,0x02,0x3C, ++0x25,0x80,0x02,0x02, ++0x24,0x00,0x04,0x26, ++0x10,0x52,0x00,0x0C, ++0x20,0x00,0x00,0xA6, ++0x02,0x80,0x05,0x3C, ++0x2A,0x00,0x04,0x26, ++0x18,0x3B,0xA5,0x24, ++0x10,0x52,0x00,0x0C, ++0x06,0x00,0x06,0x24, ++0x30,0x00,0x04,0x26, ++0xF0,0xDD,0x65,0x26, ++0x10,0x52,0x00,0x0C, ++0x06,0x00,0x06,0x24, ++0x20,0x00,0x03,0x96, ++0x18,0x00,0x02,0x24, ++0x02,0x80,0x04,0x3C, ++0x03,0xFF,0x63,0x30, ++0x40,0x00,0x63,0x34, ++0x20,0x00,0x03,0xA6, ++0x30,0x1F,0x84,0x24, ++0x0C,0x00,0x22,0xAE, ++0xF8,0x1D,0x82,0x94, ++0x20,0x00,0x06,0x26, ++0x02,0x80,0x07,0x3C, ++0xFF,0x0F,0x43,0x30, ++0x00,0x19,0x03,0x00, ++0x02,0x2A,0x03,0x00, ++0x01,0x00,0x42,0x24, ++0xF8,0x1D,0x82,0xA4, ++0x16,0x00,0xC3,0xA0, ++0x17,0x00,0xC5,0xA0, ++0x74,0x3B,0x86,0x8C, ++0xA8,0x5A,0xE7,0x24, ++0x38,0x00,0x04,0x26, ++0x21,0x28,0x00,0x00, ++0x41,0x4F,0x00,0x0C, ++0x10,0x00,0xB2,0xAF, ++0x18,0x00,0xA4,0x27, ++0x28,0x00,0xA5,0x27, ++0x21,0x50,0x00,0x0C, ++0x21,0x80,0x40,0x00, ++0x28,0x00,0xA3,0x8F, ++0x21,0x20,0x00,0x02, ++0x18,0x00,0xA7,0x27, ++0x09,0x00,0x62,0x28, ++0x01,0x00,0x05,0x24, ++0x12,0x00,0x40,0x10, ++0x08,0x00,0x06,0x24, ++0x21,0x20,0x00,0x02, ++0x21,0x30,0x60,0x00, ++0x01,0x00,0x05,0x24, ++0x18,0x00,0xA7,0x27, ++0x41,0x4F,0x00,0x0C, ++0x10,0x00,0xB2,0xAF, ++0x21,0x20,0x20,0x02, ++0x01,0x00,0x05,0x24, ++0xB9,0x0C,0x00,0x0C, ++0x21,0x30,0x00,0x00, ++0x40,0x00,0xBF,0x8F, ++0x3C,0x00,0xB3,0x8F, ++0x38,0x00,0xB2,0x8F, ++0x34,0x00,0xB1,0x8F, ++0x30,0x00,0xB0,0x8F, ++0x08,0x00,0xE0,0x03, ++0x48,0x00,0xBD,0x27, ++0x41,0x4F,0x00,0x0C, ++0x10,0x00,0xB2,0xAF, ++0x28,0x00,0xA6,0x8F, ++0x21,0x20,0x40,0x00, ++0x32,0x00,0x05,0x24, ++0xF8,0xFF,0xC6,0x24, ++0x59,0x0F,0x00,0x08, ++0x20,0x00,0xA7,0x27, ++0x02,0x80,0x05,0x3C, ++0x2F,0x55,0x00,0x0C, ++0x9C,0xEA,0xA5,0x24, ++0x40,0x00,0xBF,0x8F, ++0x3C,0x00,0xB3,0x8F, ++0x38,0x00,0xB2,0x8F, ++0x34,0x00,0xB1,0x8F, ++0x30,0x00,0xB0,0x8F, ++0x08,0x00,0xE0,0x03, ++0x48,0x00,0xBD,0x27, ++0xC8,0xFF,0xBD,0x27, ++0x18,0x00,0xB2,0xAF, ++0x10,0x00,0xB0,0xAF, ++0x34,0x00,0xBF,0xAF, ++0x30,0x00,0xBE,0xAF, ++0x2C,0x00,0xB7,0xAF, ++0x28,0x00,0xB6,0xAF, ++0x24,0x00,0xB5,0xAF, ++0x20,0x00,0xB4,0xAF, ++0x1C,0x00,0xB3,0xAF, ++0x14,0x00,0xB1,0xAF, ++0x21,0x80,0x80,0x00, ++0x45,0x00,0xA0,0x14, ++0x21,0x90,0x00,0x00, ++0x08,0x00,0x82,0x90, ++0x02,0x80,0x13,0x3C, ++0x30,0x1F,0x63,0x26, ++0x0F,0x00,0x42,0x30, ++0x14,0x3E,0x62,0xAC, ++0x25,0xB0,0x02,0x3C, ++0x0A,0x00,0x10,0x26, ++0xD0,0x01,0x57,0x34, ++0x02,0x80,0x14,0x3C, ++0xD8,0x01,0x5E,0x34, ++0xDC,0x01,0x55,0x34, ++0xD4,0x01,0x56,0x34, ++0x03,0x00,0x11,0x24, ++0x00,0x00,0x06,0x92, ++0x30,0x1F,0x62,0x26, ++0x0C,0x3E,0x47,0x90, ++0x0F,0x00,0xC3,0x30, ++0x01,0x00,0x05,0x92, ++0x18,0x00,0x67,0x00, ++0x03,0x00,0x04,0x92, ++0x02,0x00,0x02,0x92, ++0x0F,0x00,0xA7,0x30, ++0x00,0x3A,0x07,0x00, ++0x02,0x29,0x05,0x00, ++0x00,0x22,0x04,0x00, ++0x25,0x20,0x82,0x00, ++0x00,0x2B,0x05,0x00, ++0x42,0x11,0x06,0x00, ++0x00,0x24,0x04,0x00, ++0x03,0x00,0x49,0x30, ++0x02,0x31,0x06,0x00, ++0x01,0x00,0x02,0x24, ++0x01,0x00,0xC6,0x30, ++0x12,0x18,0x00,0x00, ++0x0A,0x00,0x63,0x24, ++0xFF,0x00,0x63,0x30, ++0x25,0x18,0x67,0x00, ++0x25,0x18,0x65,0x00, ++0x30,0x00,0x22,0x11, ++0x25,0x38,0x64,0x00, ++0x02,0x00,0x22,0x29, ++0x3E,0x00,0x40,0x14, ++0x02,0x00,0x02,0x24, ++0x38,0x00,0x22,0x11, ++0x03,0x00,0x02,0x24, ++0x40,0x00,0x22,0x11, ++0x00,0x00,0x00,0x00, ++0x21,0x28,0x20,0x01, ++0x3C,0xE0,0x84,0x26, ++0x2F,0x55,0x00,0x0C, ++0xFF,0xFF,0x31,0x26, ++0xD9,0xFF,0x21,0x06, ++0x04,0x00,0x10,0x26, ++0x25,0xB0,0x02,0x3C, ++0xE7,0x01,0x42,0x34, ++0x00,0x00,0x52,0xA0, ++0x34,0x00,0xBF,0x8F, ++0x30,0x00,0xBE,0x8F, ++0x2C,0x00,0xB7,0x8F, ++0x28,0x00,0xB6,0x8F, ++0x24,0x00,0xB5,0x8F, ++0x20,0x00,0xB4,0x8F, ++0x1C,0x00,0xB3,0x8F, ++0x18,0x00,0xB2,0x8F, ++0x14,0x00,0xB1,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x08,0x00,0xE0,0x03, ++0x38,0x00,0xBD,0x27, ++0x02,0x80,0x13,0x3C, ++0x08,0x00,0x83,0x90, ++0x30,0x1F,0x62,0x26, ++0x14,0x3E,0x44,0x8C, ++0x0F,0x00,0x63,0x30, ++0xBB,0xFF,0x83,0x14, ++0x00,0x00,0x00,0x00, ++0x34,0x00,0xBF,0x8F, ++0x30,0x00,0xBE,0x8F, ++0x2C,0x00,0xB7,0x8F, ++0x28,0x00,0xB6,0x8F, ++0x24,0x00,0xB5,0x8F, ++0x20,0x00,0xB4,0x8F, ++0x1C,0x00,0xB3,0x8F, ++0x18,0x00,0xB2,0x8F, ++0x14,0x00,0xB1,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x08,0x00,0xE0,0x03, ++0x38,0x00,0xBD,0x27, ++0x00,0x00,0xA7,0xAE, ++0x21,0x20,0x00,0x00, ++0x25,0xB0,0x08,0x3C, ++0x07,0x10,0x92,0x00, ++0x01,0x00,0x42,0x30, ++0x01,0x00,0x84,0x24, ++0x02,0x00,0x40,0x10, ++0x03,0x00,0x85,0x2C, ++0xD0,0x01,0x07,0xAD, ++0xF9,0xFF,0xA0,0x14, ++0x04,0x00,0x08,0x25, ++0xB6,0x0F,0x00,0x08, ++0x21,0x28,0x20,0x01, ++0x0D,0x00,0xC0,0x10, ++0x00,0x00,0x00,0x00, ++0xB5,0x0F,0x00,0x08, ++0x02,0x00,0x52,0x36, ++0xC7,0xFF,0x20,0x15, ++0x21,0x28,0x20,0x01, ++0x0D,0x00,0xC0,0x10, ++0x00,0x00,0x00,0x00, ++0xB6,0x0F,0x00,0x08, ++0x04,0x00,0x52,0x36, ++0x06,0x00,0xC0,0x10, ++0x00,0x00,0x00,0x00, ++0xB5,0x0F,0x00,0x08, ++0x01,0x00,0x52,0x36, ++0x00,0x00,0xC7,0xAE, ++0xB6,0x0F,0x00,0x08, ++0x21,0x28,0x20,0x01, ++0x00,0x00,0xE7,0xAE, ++0xB6,0x0F,0x00,0x08, ++0x21,0x28,0x20,0x01, ++0x00,0x00,0xC7,0xAF, ++0xB6,0x0F,0x00,0x08, ++0x21,0x28,0x20,0x01, ++0xC8,0xFF,0xBD,0x27, ++0x1C,0x00,0xB1,0xAF, ++0x02,0x80,0x02,0x3C, ++0x21,0x88,0x80,0x00, ++0x00,0x01,0x04,0x24, ++0x30,0x00,0xB6,0xAF, ++0x24,0x00,0xB3,0xAF, ++0x34,0x00,0xBF,0xAF, ++0x2C,0x00,0xB5,0xAF, ++0x28,0x00,0xB4,0xAF, ++0x20,0x00,0xB2,0xAF, ++0x18,0x00,0xB0,0xAF, ++0x25,0x24,0x00,0x0C, ++0x84,0x58,0x56,0x24, ++0x74,0x00,0x40,0x10, ++0x21,0x98,0x40,0x00, ++0x08,0x00,0x50,0x94, ++0x02,0x80,0x02,0x3C, ++0x21,0x28,0x20,0x02, ++0x25,0x80,0x02,0x02, ++0x24,0x00,0x04,0x26, ++0x20,0x00,0x00,0xA6, ++0x10,0x52,0x00,0x0C, ++0x06,0x00,0x06,0x24, ++0x02,0x80,0x05,0x3C, ++0x2A,0x00,0x04,0x26, ++0x18,0x3B,0xA5,0x24, ++0x10,0x52,0x00,0x0C, ++0x06,0x00,0x06,0x24, ++0x02,0x80,0x05,0x3C, ++0x06,0x00,0x06,0x24, ++0x30,0x00,0x04,0x26, ++0x10,0x52,0x00,0x0C, ++0x88,0x58,0xA5,0x24, ++0x20,0x00,0x03,0x96, ++0x02,0x80,0x04,0x3C, ++0x30,0x1F,0x84,0x24, ++0x03,0xFF,0x63,0x30, ++0x50,0x00,0x63,0x34, ++0x20,0x00,0x03,0xA6, ++0xF8,0x1D,0x82,0x94, ++0x20,0x00,0x12,0x26, ++0x74,0x00,0xD1,0x26, ++0xFF,0x0F,0x43,0x30, ++0x00,0x19,0x03,0x00, ++0x01,0x00,0x42,0x24, ++0xF8,0x1D,0x82,0xA4, ++0x02,0x2A,0x03,0x00, ++0x20,0x00,0x02,0x24, ++0x16,0x00,0x43,0xA2, ++0x17,0x00,0x45,0xA2, ++0x21,0x20,0x20,0x02, ++0x17,0x4F,0x00,0x0C, ++0x0C,0x00,0x62,0xAE, ++0x40,0x00,0x12,0x26, ++0x21,0x20,0x40,0x02, ++0x21,0x28,0x40,0x00, ++0x10,0x52,0x00,0x0C, ++0x02,0x00,0x06,0x24, ++0x0C,0x00,0x63,0x8E, ++0x21,0x20,0x20,0x02, ++0x42,0x00,0x12,0x26, ++0x02,0x00,0x63,0x24, ++0x32,0x4F,0x00,0x0C, ++0x0C,0x00,0x63,0xAE, ++0x21,0x28,0x40,0x00, ++0x21,0x20,0x40,0x02, ++0x10,0x52,0x00,0x0C, ++0x02,0x00,0x06,0x24, ++0x0C,0x00,0x63,0x8E, ++0x44,0x00,0x04,0x26, ++0x0C,0x00,0x75,0x26, ++0x02,0x00,0x63,0x24, ++0x0C,0x00,0x63,0xAE, ++0x0C,0x00,0xC6,0x8E, ++0x21,0x28,0x00,0x00, ++0x10,0x00,0xC7,0x26, ++0x60,0x00,0xD0,0x26, ++0x41,0x4F,0x00,0x0C, ++0x10,0x00,0xB5,0xAF, ++0x21,0x20,0x00,0x02, ++0x37,0x50,0x00,0x0C, ++0x21,0x90,0x40,0x00, ++0x09,0x00,0x51,0x2C, ++0x08,0x00,0x06,0x24, ++0x21,0x20,0x40,0x02, ++0x0B,0x30,0x51,0x00, ++0x21,0x38,0x00,0x02, ++0x01,0x00,0x05,0x24, ++0x21,0xA0,0x40,0x00, ++0x41,0x4F,0x00,0x0C, ++0x10,0x00,0xB5,0xAF, ++0x21,0x20,0x40,0x00, ++0x03,0x00,0x05,0x24, ++0x01,0x00,0x06,0x24, ++0x48,0x00,0xC7,0x26, ++0x41,0x4F,0x00,0x0C, ++0x10,0x00,0xB5,0xAF, ++0x0D,0x00,0x20,0x12, ++0x21,0x20,0x60,0x02, ++0x34,0x00,0xBF,0x8F, ++0x30,0x00,0xB6,0x8F, ++0x2C,0x00,0xB5,0x8F, ++0x28,0x00,0xB4,0x8F, ++0x24,0x00,0xB3,0x8F, ++0x20,0x00,0xB2,0x8F, ++0x1C,0x00,0xB1,0x8F, ++0x18,0x00,0xB0,0x8F, ++0x01,0x00,0x05,0x24, ++0x21,0x30,0x00,0x00, ++0xB9,0x0C,0x00,0x08, ++0x38,0x00,0xBD,0x27, ++0xF8,0xFF,0x86,0x26, ++0x21,0x20,0x40,0x00, ++0x68,0x00,0xC7,0x26, ++0x32,0x00,0x05,0x24, ++0x41,0x4F,0x00,0x0C, ++0x10,0x00,0xB5,0xAF, ++0x21,0x20,0x60,0x02, ++0x34,0x00,0xBF,0x8F, ++0x30,0x00,0xB6,0x8F, ++0x2C,0x00,0xB5,0x8F, ++0x28,0x00,0xB4,0x8F, ++0x24,0x00,0xB3,0x8F, ++0x20,0x00,0xB2,0x8F, ++0x1C,0x00,0xB1,0x8F, ++0x18,0x00,0xB0,0x8F, ++0x01,0x00,0x05,0x24, ++0x21,0x30,0x00,0x00, ++0xB9,0x0C,0x00,0x08, ++0x38,0x00,0xBD,0x27, ++0x02,0x80,0x04,0x3C, ++0x02,0x80,0x05,0x3C, ++0x34,0x00,0xBF,0x8F, ++0x30,0x00,0xB6,0x8F, ++0x2C,0x00,0xB5,0x8F, ++0x28,0x00,0xB4,0x8F, ++0x24,0x00,0xB3,0x8F, ++0x20,0x00,0xB2,0x8F, ++0x1C,0x00,0xB1,0x8F, ++0x18,0x00,0xB0,0x8F, ++0x98,0xE0,0x84,0x24, ++0xAC,0xEA,0xA5,0x24, ++0x2F,0x55,0x00,0x08, ++0x38,0x00,0xBD,0x27, ++0xB0,0xFF,0xBD,0x27, ++0x50,0x00,0xA4,0xAF, ++0xFC,0x01,0x04,0x24, ++0x4C,0x00,0xBF,0xAF, ++0x48,0x00,0xBE,0xAF, ++0x44,0x00,0xB7,0xAF, ++0x40,0x00,0xB6,0xAF, ++0x3C,0x00,0xB5,0xAF, ++0x38,0x00,0xB4,0xAF, ++0x34,0x00,0xB3,0xAF, ++0x30,0x00,0xB2,0xAF, ++0x2C,0x00,0xB1,0xAF, ++0x25,0x24,0x00,0x0C, ++0x28,0x00,0xB0,0xAF, ++0xE3,0x00,0x40,0x10, ++0x1C,0x00,0xA2,0xAF, ++0x50,0x00,0xA6,0x8F, ++0x02,0x80,0x03,0x3C, ++0xD0,0xEA,0x62,0x24, ++0xD0,0xEA,0x68,0x90, ++0x01,0x00,0x44,0x90, ++0x02,0x00,0xC3,0x90, ++0x02,0x00,0x45,0x90, ++0x03,0x00,0x46,0x90, ++0x1C,0x00,0xA2,0x8F, ++0x00,0x22,0x04,0x00, ++0x25,0x20,0x88,0x00, ++0x08,0x00,0x47,0x94, ++0x50,0x00,0xA2,0x8F, ++0x00,0x2C,0x05,0x00, ++0x0F,0x00,0x63,0x30, ++0x00,0x00,0x48,0x8C, ++0x02,0x80,0x02,0x3C, ++0x25,0x38,0xE2,0x00, ++0x50,0x00,0xA2,0x8F, ++0x25,0x28,0xA4,0x00, ++0x00,0x36,0x06,0x00, ++0xC0,0x18,0x03,0x00, ++0x21,0x18,0x62,0x00, ++0x25,0x30,0xC5,0x00, ++0x02,0x80,0x02,0x3C, ++0x10,0x00,0xA6,0xAF, ++0xDD,0x5A,0x55,0x24, ++0x22,0x00,0x66,0x24, ++0x18,0x00,0x62,0x24, ++0x28,0x00,0x76,0x24, ++0x02,0x80,0x03,0x3C, ++0x20,0x00,0xF7,0x24, ++0xFF,0x3F,0x1E,0x31, ++0x21,0x90,0x00,0x00, ++0x30,0x1F,0x73,0x24, ++0x01,0x00,0x14,0x24, ++0x21,0x80,0x00,0x00, ++0x24,0x00,0xA6,0xAF, ++0xD0,0x10,0x00,0x08, ++0x20,0x00,0xA2,0xAF, ++0x39,0x52,0x00,0x0C, ++0x07,0x00,0x10,0x26, ++0x19,0x00,0x40,0x10, ++0x40,0x00,0x43,0x2A, ++0x0E,0x00,0x60,0x10, ++0xE8,0xFF,0xC2,0x27, ++0x21,0x88,0x13,0x02, ++0xAC,0x3B,0x22,0x92, ++0x01,0x00,0x52,0x26, ++0x21,0x20,0x15,0x02, ++0x21,0x28,0xC0,0x02, ++0xF4,0xFF,0x54,0x10, ++0x06,0x00,0x06,0x24, ++0x21,0x20,0x15,0x02, ++0x21,0x28,0xC0,0x02, ++0x10,0x52,0x00,0x0C, ++0x06,0x00,0x06,0x24, ++0xAC,0x3B,0x34,0xA2, ++0xE8,0xFF,0xC2,0x27, ++0x69,0x01,0x43,0x28, ++0x16,0x00,0x60,0x14, ++0x18,0x00,0xA2,0xAF, ++0x02,0x80,0x06,0x3C, ++0x30,0x1F,0xC3,0x24, ++0xA8,0x3B,0x62,0x8C, ++0x00,0x00,0x00,0x00, ++0x01,0x00,0x42,0x24, ++0xA8,0x3B,0x62,0xAC, ++0x1C,0x00,0xA4,0x8F, ++0x3D,0x24,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x4C,0x00,0xBF,0x8F, ++0x48,0x00,0xBE,0x8F, ++0x44,0x00,0xB7,0x8F, ++0x40,0x00,0xB6,0x8F, ++0x3C,0x00,0xB5,0x8F, ++0x38,0x00,0xB4,0x8F, ++0x34,0x00,0xB3,0x8F, ++0x30,0x00,0xB2,0x8F, ++0x2C,0x00,0xB1,0x8F, ++0x28,0x00,0xB0,0x8F, ++0x08,0x00,0xE0,0x03, ++0x50,0x00,0xBD,0x27, ++0x21,0x20,0xE0,0x02, ++0x21,0x28,0x00,0x00, ++0xFF,0x51,0x00,0x0C, ++0xDC,0x01,0x06,0x24, ++0x20,0x00,0xA2,0x8F, ++0x74,0x00,0xF4,0x26, ++0x21,0x20,0x80,0x02, ++0x18,0x00,0x45,0x24, ++0x18,0x00,0xA2,0x8F, ++0x80,0x00,0xF1,0x26, ++0x74,0x00,0x42,0x24, ++0x00,0x00,0xE2,0xAE, ++0x18,0x00,0xA3,0x8F, ++0x00,0x00,0x00,0x00, ++0x21,0x30,0x60,0x00, ++0x10,0x52,0x00,0x0C, ++0x70,0x00,0xE3,0xAE, ++0x70,0x00,0xE7,0x8E, ++0x21,0x20,0x20,0x02, ++0x21,0x28,0x00,0x00, ++0xF4,0xFF,0xE7,0x24, ++0x55,0x1D,0x00,0x0C, ++0x18,0x00,0xA6,0x27, ++0xD9,0xFF,0x40,0x10, ++0x21,0x80,0x40,0x00, ++0x02,0x80,0x03,0x3C, ++0x30,0x1F,0x62,0x24, ++0x74,0x3B,0x46,0x8C, ++0x00,0x00,0x00,0x00, ++0x0A,0x00,0xC0,0x18, ++0x00,0x00,0x00,0x00, ++0x18,0x00,0xA2,0x8F, ++0x00,0x00,0x00,0x00, ++0xCF,0xFF,0xC2,0x14, ++0x02,0x80,0x04,0x3C, ++0xA8,0x5A,0x84,0x24, ++0x39,0x52,0x00,0x0C, ++0x02,0x00,0x05,0x26, ++0xCA,0xFF,0x40,0x14, ++0x00,0x00,0x00,0x00, ++0x01,0x00,0x06,0x92, ++0x00,0x00,0x00,0x00, ++0x77,0x00,0xC0,0x14, ++0x10,0x00,0xE4,0x26, ++0x0C,0x00,0xE0,0xAE, ++0x50,0x00,0xA6,0x8F, ++0x00,0x00,0x00,0x00, ++0x02,0x00,0xC2,0x94, ++0x00,0x00,0x00,0x00, ++0x0F,0x00,0x42,0x30, ++0x04,0x00,0x42,0x28, ++0x68,0x00,0x40,0x10, ++0x21,0x20,0xC0,0x00, ++0x34,0x00,0xE0,0xAE, ++0x60,0x00,0xF3,0x26, ++0x21,0x20,0x60,0x02, ++0x21,0x28,0x00,0x00, ++0xFF,0x51,0x00,0x0C, ++0x10,0x00,0x06,0x24, ++0x70,0x00,0xE7,0x8E, ++0x21,0x20,0x20,0x02, ++0x01,0x00,0x05,0x24, ++0xF4,0xFF,0xE7,0x24, ++0x55,0x1D,0x00,0x0C, ++0x18,0x00,0xA6,0x27, ++0x06,0x00,0x40,0x10, ++0x21,0x90,0x00,0x00, ++0x18,0x00,0xA6,0x8F, ++0x02,0x00,0x45,0x24, ++0x10,0x52,0x00,0x0C, ++0x21,0x20,0x60,0x02, ++0x18,0x00,0xB2,0x8F, ++0x70,0x00,0xE7,0x8E, ++0x21,0x20,0x20,0x02, ++0x32,0x00,0x05,0x24, ++0xF4,0xFF,0xE7,0x24, ++0x55,0x1D,0x00,0x0C, ++0x18,0x00,0xA6,0x27, ++0x05,0x00,0x40,0x10, ++0x21,0x20,0xF2,0x02, ++0x18,0x00,0xA6,0x8F, ++0x60,0x00,0x84,0x24, ++0x10,0x52,0x00,0x0C, ++0x02,0x00,0x45,0x24, ++0x18,0x00,0xA5,0x8F, ++0x21,0x20,0x60,0x02, ++0x7D,0x50,0x00,0x0C, ++0x21,0x28,0xB2,0x00, ++0x21,0x18,0x40,0x00, ++0x01,0x00,0x02,0x24, ++0x3F,0x00,0x62,0x10, ++0x03,0x00,0x02,0x24, ++0x38,0x00,0xE2,0xAE, ++0x70,0x00,0xE7,0x8E, ++0x21,0x20,0x20,0x02, ++0x03,0x00,0x05,0x24, ++0xF4,0xFF,0xE7,0x24, ++0x55,0x1D,0x00,0x0C, ++0x18,0x00,0xA6,0x27, ++0x48,0x00,0xE0,0xAE, ++0x04,0x00,0x40,0x10, ++0x3C,0x00,0xE0,0xAE, ++0x02,0x00,0x42,0x90, ++0x00,0x00,0x00,0x00, ++0x48,0x00,0xE2,0xAE, ++0x17,0x4F,0x00,0x0C, ++0x21,0x20,0x80,0x02, ++0x21,0x28,0x40,0x00, ++0x40,0x00,0xE4,0x26, ++0x10,0x52,0x00,0x0C, ++0x02,0x00,0x06,0x24, ++0x34,0x4F,0x00,0x0C, ++0x21,0x20,0xE0,0x02, ++0xFF,0xFF,0x50,0x30, ++0x01,0x00,0x02,0x32, ++0x22,0x00,0x40,0x10, ++0x21,0x28,0xC0,0x02, ++0x01,0x00,0x02,0x24, ++0x5C,0x00,0xE2,0xAE, ++0x24,0x00,0xA5,0x8F, ++0x04,0x00,0xE4,0x26, ++0x10,0x52,0x00,0x0C, ++0x06,0x00,0x06,0x24, ++0x10,0x00,0x02,0x32, ++0x1B,0x00,0x40,0x10, ++0x01,0x00,0x02,0x24, ++0x30,0x00,0xE2,0xAE, ++0x02,0x80,0x02,0x3C, ++0x44,0x00,0xE0,0xAE, ++0x30,0x1F,0x44,0x24, ++0xA4,0x3B,0x82,0x8C, ++0x1C,0x00,0xA6,0x8F, ++0xDC,0x01,0x03,0x24, ++0x01,0x00,0x42,0x24, ++0xA4,0x3B,0x82,0xAC, ++0x08,0x00,0x02,0x24, ++0x0C,0x00,0xC3,0xAC, ++0x14,0x00,0xC2,0xAC, ++0x1C,0x00,0xA4,0x8F, ++0x30,0x09,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0xE9,0x10,0x00,0x08, ++0x00,0x00,0x00,0x00, ++0x02,0x80,0x04,0x3C, ++0x02,0x80,0x05,0x3C, ++0xA4,0xE0,0x84,0x24, ++0x2F,0x55,0x00,0x0C, ++0xBC,0xEA,0xA5,0x24, ++0xE9,0x10,0x00,0x08, ++0x00,0x00,0x00,0x00, ++0x6D,0x11,0x00,0x08, ++0x5C,0x00,0xE0,0xAE, ++0x74,0x11,0x00,0x08, ++0x30,0x00,0xE0,0xAE, ++0x52,0x11,0x00,0x08, ++0x38,0x00,0xE3,0xAE, ++0xF7,0x19,0x00,0x0C, ++0x18,0x00,0xC5,0x24, ++0x4C,0x1A,0x00,0x0C, ++0x21,0x20,0x40,0x00, ++0x2B,0x11,0x00,0x08, ++0x34,0x00,0xE2,0xAE, ++0x10,0x52,0x00,0x0C, ++0x02,0x00,0x05,0x26, ++0x01,0x00,0x03,0x92, ++0x22,0x11,0x00,0x08, ++0x0C,0x00,0xE3,0xAE, ++0x02,0x80,0x04,0x3C, ++0x84,0x58,0x84,0x24, ++0xE0,0xFF,0xBD,0x27, ++0x18,0x00,0xBF,0xAF, ++0x17,0x4F,0x00,0x0C, ++0x74,0x00,0x84,0x24, ++0x21,0x28,0x40,0x00, ++0x10,0x00,0xA4,0x27, ++0x10,0x52,0x00,0x0C, ++0x02,0x00,0x06,0x24, ++0x10,0x00,0xA2,0x97, ++0x25,0xB0,0x04,0x3C, ++0x94,0x00,0x85,0x34, ++0x9A,0x00,0x87,0x34, ++0x26,0xB0,0x06,0x3C, ++0x00,0x08,0x03,0x24, ++0x00,0x00,0xA2,0xA4, ++0x0A,0x00,0x0B,0x24, ++0x00,0x00,0xE3,0xA4, ++0x98,0x00,0x88,0x34, ++0x96,0x00,0x89,0x34, ++0x7A,0x00,0xCA,0x34, ++0x50,0x00,0x02,0x24, ++0x04,0x00,0x03,0x24, ++0x00,0x00,0x02,0xA5, ++0x00,0x00,0x2B,0xA5, ++0x00,0x00,0x43,0xA1, ++0x10,0x00,0xA2,0x97, ++0x89,0x00,0x83,0x34, ++0x14,0x00,0x07,0x24, ++0x40,0x11,0x02,0x00, ++0xA0,0xFF,0x42,0x24, ++0xFF,0xFF,0x42,0x30, ++0x9C,0x00,0x85,0x34, ++0x7C,0x00,0xC6,0x34, ++0x00,0x00,0xC2,0xA4, ++0x44,0x00,0x84,0x34, ++0x00,0x00,0x67,0xA0, ++0x00,0x00,0xAB,0xA0, ++0x00,0x00,0x82,0x94, ++0xFF,0xFD,0x03,0x24, ++0x18,0x00,0xBF,0x8F, ++0x24,0x10,0x43,0x00, ++0x00,0x00,0x82,0xA4, ++0x00,0x00,0x83,0x94, ++0x02,0x80,0x02,0x3C, ++0x30,0x1F,0x42,0x24, ++0x00,0x02,0x63,0x34, ++0x20,0x00,0xBD,0x27, ++0x8E,0x3E,0x40,0xA0, ++0x00,0x00,0x83,0xA4, ++0x08,0x00,0xE0,0x03, ++0x0C,0x3E,0x47,0xA0, ++0xD8,0xFF,0xBD,0x27, ++0x10,0x00,0xB0,0xAF, ++0x02,0x80,0x10,0x3C, ++0x84,0x58,0x04,0x26, ++0x24,0x00,0xBF,0xAF, ++0x14,0x00,0xB1,0xAF, ++0x20,0x00,0xB4,0xAF, ++0x1C,0x00,0xB3,0xAF, ++0x34,0x4F,0x00,0x0C, ++0x18,0x00,0xB2,0xAF, ++0xFF,0xFF,0x51,0x30, ++0x84,0x58,0x04,0x26, ++0x19,0x4F,0x00,0x0C, ++0x02,0x80,0x10,0x3C, ++0x30,0x1F,0x03,0x26, ++0x01,0x00,0x24,0x32, ++0x08,0x3E,0x62,0xA4, ++0x03,0x00,0x80,0x14, ++0x02,0x00,0x05,0x24, ++0x40,0x10,0x11,0x00, ++0x04,0x00,0x45,0x30, ++0x02,0x00,0x02,0x24, ++0x59,0x00,0xA2,0x10, ++0x30,0x1F,0x02,0x26, ++0x0F,0x00,0x80,0x10, ++0x02,0x00,0x03,0x24, ++0x04,0x00,0x02,0x24, ++0x11,0x00,0x62,0x10, ++0x30,0x1F,0x13,0x26, ++0x02,0x80,0x04,0x3C, ++0x21,0x28,0x20,0x02, ++0x24,0x00,0xBF,0x8F, ++0x20,0x00,0xB4,0x8F, ++0x1C,0x00,0xB3,0x8F, ++0x18,0x00,0xB2,0x8F, ++0x14,0x00,0xB1,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x18,0xE1,0x84,0x24, ++0x2F,0x55,0x00,0x08, ++0x28,0x00,0xBD,0x27, ++0x40,0x10,0x11,0x00, ++0x04,0x00,0x43,0x30, ++0x04,0x00,0x02,0x24, ++0xF1,0xFF,0x62,0x14, ++0x30,0x1F,0x13,0x26, ++0x08,0x3E,0x66,0x96, ++0x30,0x3B,0x65,0x92, ++0x02,0x80,0x04,0x3C, ++0xB0,0x1B,0x63,0xA6, ++0xD4,0xE0,0x84,0x24, ++0x2F,0x55,0x00,0x0C, ++0x25,0xB0,0x10,0x3C, ++0x50,0x02,0x03,0x36, ++0x0F,0x00,0x02,0x24, ++0x00,0x00,0x62,0xA0, ++0x21,0x28,0x00,0x00, ++0x12,0x0D,0x00,0x0C, ++0x21,0x20,0x00,0x00, ++0x30,0x3B,0x64,0x92, ++0x01,0x00,0x14,0x24, ++0x4F,0x0C,0x00,0x0C, ++0x4C,0x00,0x10,0x36, ++0x02,0x80,0x11,0x3C, ++0x00,0x00,0x14,0xA2, ++0x21,0x0E,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x37,0x50,0x00,0x0C, ++0xE4,0x58,0x24,0x26, ++0x21,0x28,0x40,0x00, ++0xE4,0x58,0x24,0x26, ++0x7D,0x50,0x00,0x0C, ++0x21,0x90,0x40,0x00, ++0x0F,0x00,0x50,0x30, ++0xE4,0x58,0x24,0x26, ++0x96,0x50,0x00,0x0C, ++0x21,0x28,0x40,0x02, ++0x40,0x02,0x10,0x36, ++0x02,0x80,0x04,0x3C, ++0x21,0x88,0x40,0x00, ++0x21,0x30,0x40,0x00, ++0x21,0x28,0x00,0x02, ++0x2F,0x55,0x00,0x0C, ++0x04,0xE1,0x84,0x24, ++0x21,0x20,0x00,0x02, ++0xC1,0x5B,0x00,0x0C, ++0x21,0x28,0x20,0x02, ++0x02,0x80,0x04,0x3C, ++0x02,0x80,0x05,0x3C, ++0xF3,0x3D,0x84,0x24, ++0x88,0x58,0xA5,0x24, ++0x06,0x00,0x06,0x24, ++0x10,0x52,0x00,0x0C, ++0xC2,0x1E,0x74,0xA2, ++0x0F,0x48,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x9C,0x11,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0xB0,0x1B,0x62,0x96, ++0x00,0x00,0x00,0x00, ++0x00,0x01,0x42,0x34, ++0x53,0x1E,0x00,0x0C, ++0xB0,0x1B,0x62,0xA6, ++0xEC,0x38,0x62,0xAE, ++0x24,0x00,0xBF,0x8F, ++0x20,0x00,0xB4,0x8F, ++0x1C,0x00,0xB3,0x8F, ++0x18,0x00,0xB2,0x8F, ++0x14,0x00,0xB1,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x01,0x00,0x04,0x24, ++0x48,0x0E,0x00,0x08, ++0x28,0x00,0xBD,0x27, ++0x78,0x3D,0x44,0x8C, ++0x01,0x20,0x03,0x24, ++0xB0,0x1B,0x43,0xA4, ++0x02,0x00,0x85,0x10, ++0x0C,0x00,0x03,0x24, ++0x0F,0x00,0x03,0x24, ++0x25,0xB0,0x02,0x3C, ++0x50,0x02,0x42,0x34, ++0x00,0x00,0x43,0xA0, ++0x30,0x1F,0x10,0x26, ++0xB0,0x1B,0x02,0x96, ++0x08,0x3E,0x06,0x96, ++0x30,0x3B,0x05,0x92, ++0x10,0x00,0x42,0x34, ++0x02,0x80,0x04,0x3C, ++0xB0,0x1B,0x02,0xA6, ++0x2F,0x55,0x00,0x0C, ++0xB0,0xE0,0x84,0x24, ++0x21,0x28,0x00,0x00, ++0x12,0x0D,0x00,0x0C, ++0x21,0x20,0x00,0x00, ++0x30,0x3B,0x04,0x92, ++0x4F,0x0C,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x53,0x1E,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0xEC,0x38,0x02,0xAE, ++0x24,0x00,0xBF,0x8F, ++0x20,0x00,0xB4,0x8F, ++0x1C,0x00,0xB3,0x8F, ++0x18,0x00,0xB2,0x8F, ++0x14,0x00,0xB1,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x08,0x00,0xE0,0x03, ++0x28,0x00,0xBD,0x27, ++0x02,0x80,0x03,0x3C, ++0x30,0x1F,0x65,0x24, ++0x50,0x3E,0xA2,0x8C, ++0x00,0x00,0x00,0x00, ++0x1F,0x00,0x40,0x10, ++0x00,0x00,0x00,0x00, ++0x0A,0x3E,0xA2,0x90, ++0x00,0x00,0x00,0x00, ++0x07,0x00,0x42,0x2C, ++0x1A,0x00,0x40,0x10, ++0x21,0x38,0xA0,0x00, ++0x98,0x3E,0xA4,0x8C, ++0x94,0x3E,0xA5,0x8C, ++0x21,0x30,0x00,0x00, ++0x80,0x10,0x04,0x00, ++0x80,0x18,0x05,0x00, ++0x2B,0x10,0x45,0x00, ++0x04,0x00,0x40,0x14, ++0x2B,0x18,0x64,0x00, ++0x01,0x00,0x06,0x24, ++0x02,0x00,0x02,0x24, ++0x0A,0x30,0x43,0x00, ++0x0A,0x3E,0xE2,0x90, ++0x94,0x3E,0xE0,0xAC, ++0x98,0x3E,0xE0,0xAC, ++0x40,0x18,0x02,0x00, ++0x21,0x18,0x62,0x00, ++0x21,0x18,0x66,0x00, ++0x02,0x80,0x02,0x3C, ++0x48,0xDD,0x42,0x24, ++0x80,0x18,0x03,0x00, ++0x21,0x18,0x62,0x00, ++0x00,0x00,0x64,0x8C, ++0x25,0xB0,0x02,0x3C, ++0xD8,0x01,0x42,0x34, ++0x00,0x00,0x44,0xAC, ++0x08,0x00,0xE0,0x03, ++0x00,0x00,0x00,0x00, ++0xE8,0xFF,0xBD,0x27, ++0x10,0x00,0xB0,0xAF, ++0x14,0x00,0xBF,0xAF, ++0x21,0x80,0x80,0x00, ++0x02,0x00,0x84,0x90, ++0x02,0x80,0x05,0x3C, ++0x18,0x3B,0xA5,0x24, ++0x0F,0x00,0x84,0x30, ++0xC0,0x20,0x04,0x00, ++0x21,0x20,0x90,0x00, ++0x1C,0x00,0x84,0x24, ++0x39,0x52,0x00,0x0C, ++0x06,0x00,0x06,0x24, ++0x06,0x00,0x40,0x10, ++0x21,0x20,0x00,0x02, ++0x14,0x00,0xBF,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x21,0x10,0x00,0x00, ++0x08,0x00,0xE0,0x03, ++0x18,0x00,0xBD,0x27, ++0x92,0x10,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x14,0x00,0xBF,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x21,0x10,0x00,0x00, ++0x08,0x00,0xE0,0x03, ++0x18,0x00,0xBD,0x27, ++0x80,0xFF,0xBD,0x27, ++0x02,0x80,0x06,0x3C, ++0x02,0x80,0x08,0x3C, ++0x78,0x00,0xBE,0xAF, ++0x7C,0x00,0xBF,0xAF, ++0x74,0x00,0xB7,0xAF, ++0x70,0x00,0xB6,0xAF, ++0x6C,0x00,0xB5,0xAF, ++0x68,0x00,0xB4,0xAF, ++0x64,0x00,0xB3,0xAF, ++0x60,0x00,0xB2,0xAF, ++0x5C,0x00,0xB1,0xAF, ++0x58,0x00,0xB0,0xAF, ++0xD0,0xEA,0xC2,0x24, ++0xE4,0xEA,0x03,0x25, ++0x01,0x00,0x44,0x90, ++0x01,0x00,0x65,0x90, ++0xD0,0xEA,0xCB,0x90, ++0xE4,0xEA,0x0A,0x91, ++0x02,0x00,0x47,0x90, ++0x02,0x00,0x66,0x90, ++0x03,0x00,0x48,0x90, ++0x03,0x00,0x69,0x90, ++0x00,0x22,0x04,0x00, ++0x00,0x2A,0x05,0x00, ++0x25,0x20,0x8B,0x00, ++0x25,0x28,0xAA,0x00, ++0x00,0x3C,0x07,0x00, ++0x00,0x34,0x06,0x00, ++0x25,0x38,0xE4,0x00, ++0x25,0x30,0xC5,0x00, ++0x00,0x46,0x08,0x00, ++0x00,0x4E,0x09,0x00, ++0x25,0x40,0x07,0x01, ++0x25,0x48,0x26,0x01, ++0x00,0x02,0x04,0x24, ++0x40,0x00,0xA8,0xAF, ++0x25,0x24,0x00,0x0C, ++0x48,0x00,0xA9,0xAF, ++0xB0,0x01,0x40,0x10, ++0x21,0xF0,0x40,0x00, ++0x02,0x80,0x02,0x3C, ++0x30,0x1F,0x52,0x24, ++0xC4,0x39,0x45,0x8E, ++0x02,0x80,0x04,0x3C, ++0x2F,0x55,0x00,0x0C, ++0x34,0xE1,0x84,0x24, ++0x08,0x00,0xD1,0x97, ++0x02,0x80,0x02,0x3C, ++0x02,0x80,0x10,0x3C, ++0x25,0x88,0x22,0x02, ++0x88,0x58,0x10,0x26, ++0x24,0x00,0x24,0x26, ++0x21,0x28,0x00,0x02, ++0x20,0x00,0x20,0xA6, ++0x10,0x52,0x00,0x0C, ++0x06,0x00,0x06,0x24, ++0x02,0x80,0x05,0x3C, ++0x2A,0x00,0x24,0x26, ++0x18,0x3B,0xA5,0x24, ++0x10,0x52,0x00,0x0C, ++0x06,0x00,0x06,0x24, ++0x21,0x28,0x00,0x02, ++0x06,0x00,0x06,0x24, ++0x10,0x52,0x00,0x0C, ++0x30,0x00,0x24,0x26, ++0x18,0x00,0x03,0x24, ++0x0C,0x00,0xC3,0xAF, ++0xF8,0x1D,0x42,0x96, ++0x20,0x00,0x25,0x26, ++0x38,0x00,0x37,0x26, ++0xFF,0x0F,0x43,0x30, ++0x00,0x19,0x03,0x00, ++0x02,0x22,0x03,0x00, ++0x01,0x00,0x42,0x24, ++0xF8,0x1D,0x42,0xA6, ++0x17,0x00,0xA4,0xA0, ++0x02,0x80,0x04,0x3C, ++0x16,0x00,0xA3,0xA0, ++0x32,0x4F,0x00,0x0C, ++0xF8,0x58,0x84,0x24, ++0x21,0x28,0x40,0x00, ++0x21,0x20,0xE0,0x02, ++0x10,0x52,0x00,0x0C, ++0x02,0x00,0x06,0x24, ++0x3A,0x00,0x24,0x26, ++0x18,0x00,0xA5,0x27, ++0x02,0x00,0x06,0x24, ++0x03,0x00,0x02,0x24, ++0x10,0x52,0x00,0x0C, ++0x18,0x00,0xA2,0xA7, ++0x0C,0x00,0xC3,0x8F, ++0x02,0x80,0x07,0x3C, ++0x3C,0x00,0x24,0x26, ++0x04,0x00,0x63,0x24, ++0x0C,0x00,0xC3,0xAF, ++0x60,0x39,0x46,0x8E, ++0x0C,0x00,0xC2,0x27, ++0x94,0x58,0xE7,0x24, ++0x21,0x28,0x00,0x00, ++0x54,0x00,0xA2,0xAF, ++0x41,0x4F,0x00,0x0C, ++0x10,0x00,0xA2,0xAF, ++0x20,0x00,0xA4,0x27, ++0x50,0x00,0xA5,0x27, ++0x21,0x50,0x00,0x0C, ++0x21,0xB8,0x40,0x00, ++0x50,0x00,0xA8,0x8F, ++0x21,0x88,0x00,0x00, ++0x52,0x00,0x00,0x11, ++0x21,0x80,0x00,0x00, ++0x21,0x38,0x40,0x02, ++0x18,0x00,0xA9,0x27, ++0x21,0x10,0x31,0x01, ++0x08,0x00,0x46,0x90, ++0x21,0x20,0x00,0x00, ++0x7F,0x00,0xC5,0x30, ++0x21,0x10,0x87,0x00, ++0xB4,0x39,0x43,0x90, ++0x01,0x00,0x84,0x24, ++0x7F,0x00,0x63,0x30, ++0x3D,0x00,0xA3,0x10, ++0x0D,0x00,0x82,0x2C, ++0xFA,0xFF,0x40,0x14, ++0x21,0x10,0x87,0x00, ++0x01,0x00,0x31,0x26, ++0x2B,0x10,0x28,0x02, ++0xF2,0xFF,0x40,0x14, ++0x21,0x10,0x31,0x01, ++0x09,0x00,0x02,0x2E, ++0x3D,0x00,0x40,0x14, ++0x21,0x20,0xE0,0x02, ++0x54,0x00,0xA2,0x8F, ++0x01,0x00,0x05,0x24, ++0x08,0x00,0x06,0x24, ++0x30,0x00,0xA7,0x27, ++0x41,0x4F,0x00,0x0C, ++0x10,0x00,0xA2,0xAF, ++0x21,0x20,0x40,0x00, ++0x54,0x00,0xA2,0x8F, ++0xF8,0xFF,0x06,0x26, ++0x32,0x00,0x05,0x24, ++0x38,0x00,0xA7,0x27, ++0x41,0x4F,0x00,0x0C, ++0x10,0x00,0xA2,0xAF, ++0x21,0xB8,0x40,0x00, ++0x02,0x80,0x02,0x3C, ++0x30,0x1F,0x44,0x24, ++0x78,0x3D,0x83,0x8C, ++0x02,0x00,0x02,0x24, ++0x37,0x00,0x62,0x14, ++0x00,0x00,0x00,0x00, ++0xC4,0x39,0x83,0x8C, ++0x0C,0x00,0x11,0x24, ++0x2B,0x10,0x23,0x02, ++0x32,0x00,0x40,0x10, ++0x02,0x80,0x02,0x3C, ++0xF8,0x58,0x46,0x24, ++0x21,0x20,0x60,0x00, ++0x4D,0x13,0x00,0x08, ++0x30,0x00,0x05,0x24, ++0x01,0x00,0x62,0x90, ++0x00,0x00,0x00,0x00, ++0x21,0x10,0x51,0x00, ++0x02,0x00,0x51,0x24, ++0x2B,0x18,0x24,0x02, ++0x27,0x00,0x60,0x10, ++0x00,0x00,0x00,0x00, ++0x21,0x18,0x26,0x02, ++0x00,0x00,0x62,0x90, ++0x00,0x00,0x00,0x00, ++0xF5,0xFF,0x45,0x14, ++0x02,0x80,0x07,0x3C, ++0x01,0x00,0x66,0x90, ++0x54,0x00,0xA2,0x8F, ++0xFA,0x58,0xE7,0x24, ++0x21,0x20,0xE0,0x02, ++0x21,0x38,0x27,0x02, ++0x30,0x00,0x05,0x24, ++0x41,0x4F,0x00,0x0C, ++0x10,0x00,0xA2,0xAF, ++0x73,0x13,0x00,0x08, ++0x21,0xB8,0x40,0x00, ++0x21,0x10,0x30,0x01, ++0x18,0x00,0x46,0xA0, ++0x50,0x00,0xA8,0x8F, ++0x01,0x00,0x31,0x26, ++0x2B,0x10,0x28,0x02, ++0xB4,0xFF,0x40,0x14, ++0x01,0x00,0x10,0x26, ++0x27,0x13,0x00,0x08, ++0x09,0x00,0x02,0x2E, ++0x54,0x00,0xA2,0x8F, ++0x21,0x20,0xE0,0x02, ++0x21,0x30,0x00,0x02, ++0x01,0x00,0x05,0x24, ++0x30,0x00,0xA7,0x27, ++0x41,0x4F,0x00,0x0C, ++0x10,0x00,0xA2,0xAF, ++0x21,0xB8,0x40,0x00, ++0x02,0x80,0x02,0x3C, ++0x30,0x1F,0x44,0x24, ++0x78,0x3D,0x83,0x8C, ++0x02,0x00,0x02,0x24, ++0xCB,0xFF,0x62,0x10, ++0x00,0x00,0x00,0x00, ++0xD5,0x1D,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x16,0x00,0x40,0x14, ++0x02,0x80,0x02,0x3C, ++0x30,0x1F,0x43,0x24, ++0xC4,0x39,0x62,0x8C, ++0x0C,0x00,0x11,0x24, ++0x2B,0x10,0x22,0x02, ++0x10,0x00,0x40,0x10, ++0x02,0x80,0x02,0x3C, ++0xF8,0x58,0x52,0x24, ++0x21,0x80,0x60,0x00, ++0x02,0x80,0x13,0x3C, ++0x21,0x20,0x32,0x02, ++0x00,0x00,0x83,0x90, ++0x2D,0x00,0x02,0x24, ++0xCB,0x00,0x62,0x10, ++0x02,0x80,0x05,0x3C, ++0x01,0x00,0x82,0x90, ++0xC4,0x39,0x03,0x8E, ++0x21,0x10,0x51,0x00, ++0x02,0x00,0x51,0x24, ++0x2B,0x18,0x23,0x02, ++0xF6,0xFF,0x60,0x14, ++0x21,0x20,0x32,0x02, ++0x02,0x80,0x02,0x3C, ++0x30,0x1F,0x44,0x24, ++0x78,0x3D,0x83,0x8C, ++0x02,0x00,0x02,0x24, ++0x82,0x00,0x62,0x10, ++0x0C,0x00,0x11,0x24, ++0x02,0x80,0x02,0x3C, ++0x30,0x1F,0x43,0x24, ++0xC4,0x39,0x62,0x8C, ++0x0C,0x00,0x11,0x24, ++0x2B,0x10,0x22,0x02, ++0x26,0x00,0x40,0x10, ++0x02,0x80,0x02,0x3C, ++0xF8,0x58,0x56,0x24, ++0x21,0xA8,0x60,0x00, ++0xDD,0x00,0x14,0x24, ++0xA5,0x13,0x00,0x08, ++0x02,0x80,0x13,0x3C, ++0x01,0x00,0x02,0x92, ++0xC4,0x39,0xA3,0x8E, ++0x21,0x10,0x51,0x00, ++0x02,0x00,0x51,0x24, ++0x2B,0x18,0x23,0x02, ++0x1B,0x00,0x60,0x10, ++0x02,0x80,0x02,0x3C, ++0x21,0x80,0x36,0x02, ++0x00,0x00,0x02,0x92, ++0x02,0x00,0x12,0x26, ++0x21,0x20,0x40,0x02, ++0xD0,0xDD,0x65,0x26, ++0xF3,0xFF,0x54,0x14, ++0x06,0x00,0x06,0x24, ++0x39,0x52,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0xEF,0xFF,0x40,0x14, ++0x21,0x20,0xE0,0x02, ++0x54,0x00,0xA2,0x8F, ++0xDD,0x00,0x05,0x24, ++0x21,0x38,0x40,0x02, ++0x07,0x00,0x06,0x24, ++0x41,0x4F,0x00,0x0C, ++0x10,0x00,0xA2,0xAF, ++0x08,0x00,0x04,0x92, ++0x21,0xB8,0x40,0x00, ++0x02,0x80,0x02,0x3C, ++0x30,0x1F,0x45,0x24, ++0x01,0x00,0x03,0x24, ++0x02,0x80,0x02,0x3C, ++0x0F,0x5F,0x44,0xA0, ++0x10,0x3E,0xA3,0xAC, ++0x02,0x80,0x02,0x3C, ++0x30,0x1F,0x44,0x24, ++0xC4,0x39,0x82,0x8C, ++0x0C,0x00,0x11,0x24, ++0x2B,0x10,0x22,0x02, ++0x20,0x00,0x40,0x10, ++0x02,0x80,0x02,0x3C, ++0x02,0x80,0x03,0x3C, ++0xF8,0x58,0x56,0x24, ++0xFA,0x58,0x75,0x24, ++0x21,0xA0,0x80,0x00, ++0xD2,0x13,0x00,0x08, ++0xDD,0x00,0x13,0x24, ++0x01,0x00,0x02,0x92, ++0xC4,0x39,0x83,0x8E, ++0x21,0x10,0x51,0x00, ++0x02,0x00,0x51,0x24, ++0x2B,0x18,0x23,0x02, ++0x14,0x00,0x60,0x10, ++0x02,0x80,0x02,0x3C, ++0x21,0x80,0x36,0x02, ++0x00,0x00,0x02,0x92, ++0x21,0x90,0x35,0x02, ++0x21,0x20,0x40,0x02, ++0x48,0x00,0xA5,0x27, ++0xF3,0xFF,0x53,0x14, ++0x04,0x00,0x06,0x24, ++0x39,0x52,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0xEF,0xFF,0x40,0x14, ++0x21,0x20,0xE0,0x02, ++0x01,0x00,0x06,0x92, ++0x54,0x00,0xA2,0x8F, ++0x21,0x38,0x40,0x02, ++0xDD,0x00,0x05,0x24, ++0x41,0x4F,0x00,0x0C, ++0x10,0x00,0xA2,0xAF, ++0x21,0xB8,0x40,0x00, ++0x02,0x80,0x02,0x3C, ++0x30,0x1F,0x50,0x24, ++0x0A,0x3E,0x02,0x92, ++0x50,0x3E,0x03,0x8E, ++0x05,0x00,0x42,0x38, ++0x01,0x00,0x63,0x38, ++0x01,0x00,0x42,0x2C, ++0x01,0x00,0x63,0x2C, ++0x24,0x10,0x43,0x00, ++0x58,0x00,0x40,0x14, ++0x02,0x80,0x07,0x3C, ++0xC4,0x39,0x05,0x8E, ++0x0C,0x00,0x11,0x24, ++0x2B,0x10,0x25,0x02, ++0x0F,0x00,0x40,0x10, ++0x02,0x80,0x02,0x3C, ++0xF8,0x58,0x46,0x24, ++0x44,0x00,0x04,0x24, ++0x21,0x80,0x26,0x02, ++0x00,0x00,0x02,0x92, ++0x00,0x00,0x00,0x00, ++0x3E,0x00,0x44,0x10, ++0x00,0x00,0x00,0x00, ++0x01,0x00,0x02,0x92, ++0x00,0x00,0x00,0x00, ++0x21,0x10,0x51,0x00, ++0x02,0x00,0x51,0x24, ++0x2B,0x18,0x25,0x02, ++0xF6,0xFF,0x60,0x14, ++0x21,0x80,0x26,0x02, ++0x21,0x20,0xC0,0x03, ++0x21,0x28,0x00,0x00, ++0xB9,0x0C,0x00,0x0C, ++0x21,0x30,0x00,0x00, ++0x21,0x10,0x00,0x00, ++0x7C,0x00,0xBF,0x8F, ++0x78,0x00,0xBE,0x8F, ++0x74,0x00,0xB7,0x8F, ++0x70,0x00,0xB6,0x8F, ++0x6C,0x00,0xB5,0x8F, ++0x68,0x00,0xB4,0x8F, ++0x64,0x00,0xB3,0x8F, ++0x60,0x00,0xB2,0x8F, ++0x5C,0x00,0xB1,0x8F, ++0x58,0x00,0xB0,0x8F, ++0x08,0x00,0xE0,0x03, ++0x80,0x00,0xBD,0x27, ++0xC4,0x39,0x82,0x8C, ++0x00,0x00,0x00,0x00, ++0x2B,0x10,0x22,0x02, ++0x7B,0xFF,0x40,0x10, ++0x02,0x80,0x02,0x3C, ++0x02,0x80,0x03,0x3C, ++0xF8,0x58,0x56,0x24, ++0xFA,0x58,0x75,0x24, ++0x21,0xA0,0x80,0x00, ++0x25,0x14,0x00,0x08, ++0xDD,0x00,0x13,0x24, ++0x01,0x00,0x02,0x92, ++0xC4,0x39,0x83,0x8E, ++0x21,0x10,0x51,0x00, ++0x02,0x00,0x51,0x24, ++0x2B,0x18,0x23,0x02, ++0x6F,0xFF,0x60,0x10, ++0x02,0x80,0x02,0x3C, ++0x21,0x80,0x36,0x02, ++0x00,0x00,0x02,0x92, ++0x21,0x90,0x35,0x02, ++0x21,0x20,0x40,0x02, ++0x40,0x00,0xA5,0x27, ++0xF3,0xFF,0x53,0x14, ++0x04,0x00,0x06,0x24, ++0x39,0x52,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0xEF,0xFF,0x40,0x14, ++0x21,0x20,0xE0,0x02, ++0x01,0x00,0x06,0x92, ++0x54,0x00,0xA2,0x8F, ++0x21,0x38,0x40,0x02, ++0xDD,0x00,0x05,0x24, ++0x41,0x4F,0x00,0x0C, ++0x10,0x00,0xA2,0xAF, ++0x92,0x13,0x00,0x08, ++0x21,0xB8,0x40,0x00, ++0x02,0x80,0x04,0x3C, ++0x2F,0x55,0x00,0x0C, ++0x48,0xE1,0x84,0x24, ++0x01,0x00,0x06,0x92, ++0x54,0x00,0xA2,0x8F, ++0x02,0x80,0x07,0x3C, ++0xFA,0x58,0xE7,0x24, ++0x21,0x38,0x27,0x02, ++0x21,0x20,0xE0,0x02, ++0x44,0x00,0x05,0x24, ++0x41,0x4F,0x00,0x0C, ++0x10,0x00,0xA2,0xAF, ++0x03,0x14,0x00,0x08, ++0x21,0x20,0xC0,0x03, ++0x54,0x00,0xA2,0x8F, ++0x21,0x20,0xE0,0x02, ++0x9C,0xDD,0xE7,0x24, ++0xDD,0x00,0x05,0x24, ++0x06,0x00,0x06,0x24, ++0x41,0x4F,0x00,0x0C, ++0x10,0x00,0xA2,0xAF, ++0xEF,0x13,0x00,0x08, ++0x21,0xB8,0x40,0x00, ++0x02,0x80,0x14,0x3C, ++0xFA,0x58,0xA5,0x24, ++0x21,0x28,0x25,0x02, ++0x88,0x5D,0x84,0x26, ++0x10,0x52,0x00,0x0C, ++0x20,0x00,0x06,0x24, ++0x02,0x80,0x03,0x3C, ++0xF1,0x5D,0x62,0x90, ++0x00,0x00,0x00,0x00, ++0x1D,0x00,0x40,0x14, ++0x00,0x00,0x00,0x00, ++0x58,0x3E,0x02,0x96, ++0x00,0x00,0x00,0x00, ++0xBD,0xFF,0x42,0x30, ++0x58,0x3E,0x02,0xA6, ++0x02,0x80,0x02,0x3C, ++0x58,0x3E,0x03,0x96, ++0xDE,0x5D,0x44,0x90, ++0x0C,0x00,0x63,0x34, ++0x01,0x00,0x84,0x30, ++0x15,0x00,0x80,0x10, ++0x58,0x3E,0x03,0xA6, ++0x02,0x80,0x05,0x3C, ++0x8B,0x5D,0x64,0x26, ++0x3C,0xE3,0xA5,0x24, ++0x10,0x52,0x00,0x0C, ++0x10,0x00,0x06,0x24, ++0x21,0x10,0x32,0x02, ++0x01,0x00,0x46,0x90, ++0x54,0x00,0xA2,0x8F, ++0x21,0x20,0xE0,0x02, ++0x88,0x5D,0x87,0x26, ++0x2D,0x00,0x05,0x24, ++0x41,0x4F,0x00,0x0C, ++0x10,0x00,0xA2,0xAF, ++0x21,0xB8,0x40,0x00, ++0x01,0x00,0x02,0x24, ++0x8C,0x13,0x00,0x08, ++0x50,0x3E,0x02,0xAE, ++0x58,0x3E,0x02,0x96, ++0x5D,0x14,0x00,0x08, ++0x02,0x00,0x42,0x34, ++0x02,0x80,0x05,0x3C, ++0x8B,0x5D,0x64,0x26, ++0x68,0x14,0x00,0x08, ++0x4C,0xE3,0xA5,0x24, ++0x02,0x80,0x04,0x3C, ++0x02,0x80,0x05,0x3C, ++0x28,0xE1,0x84,0x24, ++0x2F,0x55,0x00,0x0C, ++0xD4,0xEA,0xA5,0x24, ++0x07,0x14,0x00,0x08, ++0xFF,0xFF,0x02,0x24, ++0x02,0x80,0x02,0x3C, ++0x30,0x1F,0x42,0x24, ++0xB0,0x1B,0x43,0x94, ++0xC8,0x00,0x04,0x24, ++0xD0,0x38,0x44,0xAC, ++0x9F,0xFE,0x63,0x30, ++0x80,0x00,0x63,0x34, ++0xB0,0x1B,0x43,0xA4, ++0x6C,0x3D,0x40,0xAC, ++0x70,0x3D,0x40,0xAC, ++0xA5,0x12,0x00,0x08, ++0xB4,0x38,0x40,0xAC, ++0xD8,0xFF,0xBD,0x27, ++0x28,0x00,0xA4,0xA3, ++0x00,0x01,0x04,0x24, ++0x18,0x00,0xB2,0xAF, ++0x20,0x00,0xBF,0xAF, ++0x1C,0x00,0xB3,0xAF, ++0x14,0x00,0xB1,0xAF, ++0x10,0x00,0xB0,0xAF, ++0x2C,0x00,0xA5,0xA3, ++0x25,0x24,0x00,0x0C, ++0x30,0x00,0xA6,0xA7, ++0x94,0x00,0x40,0x10, ++0x21,0x90,0x40,0x00, ++0x30,0x00,0xA7,0x97, ++0x28,0x00,0xA5,0x93, ++0x2C,0x00,0xA6,0x93, ++0x02,0x80,0x04,0x3C, ++0x2F,0x55,0x00,0x0C, ++0x68,0xE1,0x84,0x24, ++0x08,0x00,0x50,0x96, ++0x02,0x80,0x02,0x3C, ++0x02,0x80,0x11,0x3C, ++0x25,0x80,0x02,0x02, ++0x88,0x58,0x31,0x26, ++0x21,0x28,0x20,0x02, ++0x24,0x00,0x04,0x26, ++0x06,0x00,0x06,0x24, ++0x10,0x52,0x00,0x0C, ++0x20,0x00,0x00,0xA6, ++0x02,0x80,0x05,0x3C, ++0x18,0x3B,0xA5,0x24, ++0x2A,0x00,0x04,0x26, ++0x10,0x52,0x00,0x0C, ++0x06,0x00,0x06,0x24, ++0x21,0x28,0x20,0x02, ++0x30,0x00,0x04,0x26, ++0x10,0x52,0x00,0x0C, ++0x06,0x00,0x06,0x24, ++0x20,0x00,0x03,0x96, ++0x18,0x00,0x02,0x24, ++0x20,0x00,0x05,0x26, ++0x03,0xFF,0x63,0x30, ++0xD0,0x00,0x63,0x34, ++0x20,0x00,0x03,0xA6, ++0x02,0x80,0x03,0x3C, ++0x0C,0x00,0x42,0xAE, ++0x30,0x1F,0x73,0x24, ++0xF8,0x1D,0x62,0x96, ++0x0C,0x00,0x51,0x26, ++0x28,0x00,0xA6,0x27, ++0xFF,0x0F,0x43,0x30, ++0x00,0x19,0x03,0x00, ++0x02,0x22,0x03,0x00, ++0x01,0x00,0x42,0x24, ++0xF8,0x1D,0x62,0xA6, ++0x21,0x38,0x20,0x02, ++0x16,0x00,0xA3,0xA0, ++0x17,0x00,0xA4,0xA0, ++0x38,0x00,0x04,0x26, ++0x68,0x4F,0x00,0x0C, ++0x01,0x00,0x05,0x24, ++0x21,0x20,0x40,0x00, ++0x01,0x00,0x05,0x24, ++0x2C,0x00,0xA6,0x27, ++0x68,0x4F,0x00,0x0C, ++0x21,0x38,0x20,0x02, ++0x28,0x00,0xA3,0x93, ++0x21,0x20,0x40,0x00, ++0x03,0x00,0x02,0x24, ++0x0C,0x00,0x62,0x10, ++0x00,0x00,0x00,0x00, ++0x21,0x20,0x40,0x02, ++0x21,0x28,0x00,0x00, ++0xB9,0x0C,0x00,0x0C, ++0x21,0x30,0x00,0x00, ++0x20,0x00,0xBF,0x8F, ++0x1C,0x00,0xB3,0x8F, ++0x18,0x00,0xB2,0x8F, ++0x14,0x00,0xB1,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x08,0x00,0xE0,0x03, ++0x28,0x00,0xBD,0x27, ++0x2C,0x00,0xA3,0x93, ++0x00,0x00,0x00,0x00, ++0x2E,0x00,0x60,0x14, ++0x01,0x00,0x02,0x24, ++0x19,0x3E,0x63,0x92, ++0x21,0x80,0x60,0x02, ++0x01,0x00,0x68,0x24, ++0xFF,0x00,0x02,0x31, ++0xFD,0xFF,0x40,0x10, ++0x21,0x18,0x00,0x01, ++0x02,0x80,0x06,0x3C, ++0x19,0x3E,0x08,0xA2, ++0x21,0x38,0x20,0x02, ++0x49,0x5D,0xC6,0x24, ++0x68,0x4F,0x00,0x0C, ++0x01,0x00,0x05,0x24, ++0x30,0x00,0xA3,0x97, ++0x02,0x80,0x06,0x3C, ++0x21,0x38,0x20,0x02, ++0x0F,0x00,0x63,0x30, ++0x80,0x18,0x03,0x00, ++0x02,0x08,0x63,0x34, ++0x1C,0x3E,0x03,0xA6, ++0x4C,0x5D,0xC6,0x24, ++0x21,0x20,0x40,0x00, ++0x68,0x4F,0x00,0x0C, ++0x02,0x00,0x05,0x24, ++0x02,0x80,0x06,0x3C, ++0x21,0x38,0x20,0x02, ++0x4E,0x5D,0xC6,0x24, ++0x21,0x20,0x40,0x00, ++0x02,0x00,0x05,0x24, ++0x68,0x4F,0x00,0x0C, ++0x1E,0x3E,0x00,0xA6, ++0x30,0x00,0xA3,0x97, ++0x21,0x20,0x40,0x00, ++0x02,0x80,0x06,0x3C, ++0x07,0x00,0x63,0x30, ++0x40,0x18,0x03,0x00, ++0x21,0x18,0x70,0x00, ++0xE8,0x1D,0x62,0x94, ++0x50,0x5D,0xC6,0x24, ++0x21,0x38,0x20,0x02, ++0x00,0x11,0x02,0x00, ++0x02,0x00,0x05,0x24, ++0x68,0x4F,0x00,0x0C, ++0x20,0x3E,0x02,0xA6, ++0xD8,0x14,0x00,0x08, ++0x21,0x20,0x40,0x02, ++0xC3,0xFF,0x62,0x14, ++0x02,0x80,0x06,0x3C, ++0x21,0x38,0x20,0x02, ++0x48,0x5D,0xC6,0x24, ++0x68,0x4F,0x00,0x0C, ++0x01,0x00,0x05,0x24, ++0x21,0x20,0x40,0x00, ++0x30,0x00,0xA6,0x27, ++0x21,0x38,0x20,0x02, ++0x68,0x4F,0x00,0x0C, ++0x02,0x00,0x05,0x24, ++0x1C,0x3E,0x63,0x96, ++0x02,0x80,0x06,0x3C, ++0x21,0x38,0x20,0x02, ++0x3F,0x00,0x63,0x30, ++0x00,0x08,0x63,0x34, ++0x21,0x20,0x40,0x00, ++0x4C,0x5D,0xC6,0x24, ++0x02,0x00,0x05,0x24, ++0x68,0x4F,0x00,0x0C, ++0x1C,0x3E,0x63,0xA6, ++0x02,0x80,0x06,0x3C, ++0x21,0x20,0x40,0x00, ++0x4E,0x5D,0xC6,0x24, ++0x21,0x38,0x20,0x02, ++0x68,0x4F,0x00,0x0C, ++0x02,0x00,0x05,0x24, ++0xD8,0x14,0x00,0x08, ++0x21,0x20,0x40,0x02, ++0x02,0x80,0x04,0x3C, ++0x02,0x80,0x05,0x3C, ++0x5C,0xE1,0x84,0x24, ++0x2F,0x55,0x00,0x0C, ++0xE8,0xEA,0xA5,0x24, ++0x20,0x00,0xBF,0x8F, ++0x1C,0x00,0xB3,0x8F, ++0x18,0x00,0xB2,0x8F, ++0x14,0x00,0xB1,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x08,0x00,0xE0,0x03, ++0x28,0x00,0xBD,0x27, ++0x00,0x80,0x03,0x3C, ++0x25,0xB0,0x02,0x3C, ++0xE0,0xFF,0xBD,0x27, ++0x18,0x03,0x42,0x34, ++0xF0,0x54,0x63,0x24, ++0x14,0x00,0xB1,0xAF, ++0x10,0x00,0xB0,0xAF, ++0x1C,0x00,0xBF,0xAF, ++0x18,0x00,0xB2,0xAF, ++0x00,0x00,0x43,0xAC, ++0x02,0x00,0x82,0x90, ++0x02,0x80,0x05,0x3C, ++0x88,0x58,0xA5,0x24, ++0x0F,0x00,0x42,0x30, ++0xC0,0x10,0x02,0x00, ++0x21,0x80,0x44,0x00, ++0x28,0x00,0x04,0x26, ++0x06,0x00,0x06,0x24, ++0x39,0x52,0x00,0x0C, ++0x18,0x00,0x11,0x26, ++0x08,0x00,0x40,0x10, ++0x00,0x00,0x00,0x00, ++0x1C,0x00,0xBF,0x8F, ++0x18,0x00,0xB2,0x8F, ++0x14,0x00,0xB1,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x21,0x10,0x00,0x00, ++0x08,0x00,0xE0,0x03, ++0x20,0x00,0xBD,0x27, ++0x55,0x50,0x00,0x0C, ++0x21,0x20,0x20,0x02, ++0x02,0x80,0x04,0x3C, ++0x18,0x3B,0x84,0x24, ++0x21,0x28,0x40,0x00, ++0x39,0x52,0x00,0x0C, ++0x06,0x00,0x06,0x24, ++0xF1,0xFF,0x40,0x14, ++0x03,0x00,0x02,0x24, ++0x30,0x00,0x03,0x92, ++0x00,0x00,0x00,0x00, ++0xED,0xFF,0x62,0x14, ++0x30,0x00,0x07,0x26, ++0x02,0x80,0x06,0x3C, ++0x30,0x1F,0xC8,0x24, ++0x50,0x3E,0x02,0x8D, ++0x00,0x00,0x00,0x00, ++0xE7,0xFF,0x40,0x10, ++0x01,0x00,0x05,0x24, ++0x01,0x00,0xE3,0x90, ++0x00,0x00,0x00,0x00, ++0x1A,0x00,0x65,0x10, ++0x02,0x00,0x62,0x28, ++0x2E,0x00,0x40,0x14, ++0x02,0x00,0x02,0x24, ++0xDF,0xFF,0x62,0x14, ++0x00,0x00,0x00,0x00, ++0x03,0x00,0xE3,0x90, ++0x00,0x00,0x00,0x00, ++0x08,0x00,0x62,0x30, ++0x0A,0x00,0x40,0x14, ++0x02,0x11,0x03,0x00, ++0x1A,0x3E,0x03,0x91, ++0x04,0x10,0x45,0x00, ++0x27,0x10,0x02,0x00, ++0x24,0x10,0x43,0x00, ++0x1A,0x3E,0x02,0xA1, ++0x05,0x00,0xE3,0x90, ++0x04,0x00,0xE2,0x90, ++0x00,0x1A,0x03,0x00, ++0x25,0x90,0x62,0x00, ++0x1A,0x3E,0x05,0x91, ++0x02,0x80,0x04,0x3C, ++0x94,0xE1,0x84,0x24, ++0x2F,0x55,0x00,0x0C, ++0x21,0x30,0x40,0x02, ++0x52,0x15,0x00,0x08, ++0x00,0x00,0x00,0x00, ++0x04,0x00,0xE2,0x90, ++0x03,0x00,0xE4,0x90, ++0x05,0x00,0xE3,0x90, ++0x00,0x12,0x02,0x00, ++0x25,0x10,0x44,0x00, ++0x82,0x18,0x03,0x00, ++0x27,0x00,0x40,0x14, ++0x07,0x00,0x64,0x30, ++0x1A,0x3E,0x03,0x91, ++0x04,0x10,0x85,0x00, ++0x25,0x10,0x43,0x00, ++0x1A,0x3E,0x02,0xA1, ++0x30,0x1F,0xC2,0x24, ++0x4C,0x3E,0x43,0x90, ++0x1A,0x3E,0x45,0x90, ++0x02,0x80,0x04,0x3C, ++0x21,0x18,0x62,0x00, ++0x84,0xE1,0x84,0x24, ++0x2F,0x55,0x00,0x0C, ++0x44,0x3E,0x60,0xA0, ++0x52,0x15,0x00,0x08, ++0x00,0x00,0x00,0x00, ++0xB2,0xFF,0x60,0x14, ++0x03,0x00,0x04,0x24, ++0x02,0x00,0xE2,0x90, ++0x01,0x00,0x05,0x24, ++0x18,0x3E,0x02,0xA1, ++0x04,0x00,0xE3,0x90, ++0x03,0x00,0xE2,0x90, ++0x21,0x30,0x00,0x00, ++0x00,0x1A,0x03,0x00, ++0x25,0x18,0x62,0x00, ++0x1C,0x3E,0x03,0xA5, ++0x06,0x00,0xE2,0x90, ++0x05,0x00,0xE3,0x90, ++0x00,0x12,0x02,0x00, ++0x25,0x10,0x43,0x00, ++0x1E,0x3E,0x02,0xA5, ++0x08,0x00,0xE3,0x90, ++0x07,0x00,0xE2,0x90, ++0x00,0x1A,0x03,0x00, ++0x25,0x18,0x62,0x00, ++0x90,0x14,0x00,0x0C, ++0x20,0x3E,0x03,0xA5, ++0x52,0x15,0x00,0x08, ++0x00,0x00,0x00,0x00, ++0x1A,0x3E,0x03,0x91, ++0x04,0x10,0x85,0x00, ++0x27,0x10,0x02,0x00, ++0x94,0x15,0x00,0x08, ++0x24,0x10,0x43,0x00, ++0xC0,0xFF,0xBD,0x27, ++0x34,0x00,0xB5,0xAF, ++0xFF,0xFF,0x95,0x30, ++0x00,0x01,0x04,0x24, ++0x38,0x00,0xB6,0xAF, ++0x28,0x00,0xB2,0xAF, ++0x3C,0x00,0xBF,0xAF, ++0x30,0x00,0xB4,0xAF, ++0x2C,0x00,0xB3,0xAF, ++0x24,0x00,0xB1,0xAF, ++0x25,0x24,0x00,0x0C, ++0x20,0x00,0xB0,0xAF, ++0x21,0x90,0x40,0x00, ++0x7A,0x00,0x40,0x10, ++0x21,0xB0,0x00,0x00, ++0x02,0x80,0x04,0x3C, ++0x2F,0x55,0x00,0x0C, ++0xB0,0xE1,0x84,0x24, ++0x08,0x00,0x50,0x96, ++0x02,0x80,0x02,0x3C, ++0x02,0x80,0x11,0x3C, ++0x25,0x80,0x02,0x02, ++0x88,0x58,0x31,0x26, ++0x24,0x00,0x04,0x26, ++0x21,0x28,0x20,0x02, ++0x20,0x00,0x00,0xA6, ++0x10,0x52,0x00,0x0C, ++0x06,0x00,0x06,0x24, ++0x02,0x80,0x05,0x3C, ++0x2A,0x00,0x04,0x26, ++0x18,0x3B,0xA5,0x24, ++0x10,0x52,0x00,0x0C, ++0x06,0x00,0x06,0x24, ++0x30,0x00,0x04,0x26, ++0x21,0x28,0x20,0x02, ++0x10,0x52,0x00,0x0C, ++0x06,0x00,0x06,0x24, ++0x20,0x00,0x03,0x96, ++0x18,0x00,0x02,0x24, ++0x02,0x80,0x13,0x3C, ++0x03,0xFF,0x63,0x30, ++0xB0,0x00,0x63,0x34, ++0x20,0x00,0x03,0xA6, ++0x30,0x1F,0x68,0x26, ++0x0C,0x00,0x42,0xAE, ++0xF8,0x1D,0x02,0x95, ++0x20,0x00,0x14,0x26, ++0x0C,0x00,0x51,0x26, ++0xFF,0x0F,0x43,0x30, ++0x00,0x19,0x03,0x00, ++0x02,0x22,0x03,0x00, ++0x01,0x00,0x42,0x24, ++0xF8,0x1D,0x02,0xA5, ++0x17,0x00,0x84,0xA2, ++0x16,0x00,0x83,0xA2, ++0x74,0x3D,0x04,0x8D, ++0x03,0x00,0x02,0x24, ++0x3C,0x00,0x82,0x10, ++0x38,0x00,0x10,0x26, ++0x30,0x1F,0x73,0x26, ++0x78,0x3D,0x62,0x8E, ++0x21,0x20,0x00,0x02, ++0x02,0x00,0x05,0x24, ++0x01,0x00,0x42,0x38, ++0x01,0x00,0x42,0x2C, ++0x18,0x00,0xA6,0x27, ++0x21,0x38,0x20,0x02, ++0x68,0x4F,0x00,0x0C, ++0x18,0x00,0xA2,0xA7, ++0x74,0x3D,0x63,0x8E, ++0x21,0x20,0x40,0x00, ++0x02,0x00,0x05,0x24, ++0x18,0x00,0xA6,0x27, ++0x21,0x38,0x20,0x02, ++0x68,0x4F,0x00,0x0C, ++0x18,0x00,0xA3,0xA7, ++0x21,0x20,0x40,0x00, ++0x02,0x00,0x05,0x24, ++0x18,0x00,0xA6,0x27, ++0x21,0x38,0x20,0x02, ++0x68,0x4F,0x00,0x0C, ++0x18,0x00,0xB5,0xA7, ++0x74,0x3D,0x63,0x8E, ++0x21,0x80,0x40,0x00, ++0x03,0x00,0x02,0x24, ++0x0F,0x00,0x62,0x10, ++0x00,0x00,0x00,0x00, ++0x21,0x20,0x40,0x02, ++0x21,0x30,0xC0,0x02, ++0xB9,0x0C,0x00,0x0C, ++0x21,0x28,0x00,0x00, ++0x3C,0x00,0xBF,0x8F, ++0x38,0x00,0xB6,0x8F, ++0x34,0x00,0xB5,0x8F, ++0x30,0x00,0xB4,0x8F, ++0x2C,0x00,0xB3,0x8F, ++0x28,0x00,0xB2,0x8F, ++0x24,0x00,0xB1,0x8F, ++0x20,0x00,0xB0,0x8F, ++0x08,0x00,0xE0,0x03, ++0x40,0x00,0xBD,0x27, ++0xB0,0x1B,0x62,0x96, ++0x00,0x00,0x00,0x00, ++0x40,0x00,0x42,0x30, ++0xEF,0xFF,0x40,0x10, ++0x21,0x20,0x40,0x02, ++0x02,0x80,0x07,0x3C, ++0x21,0x20,0x00,0x02, ++0xB8,0x5C,0xE7,0x24, ++0x10,0x00,0x05,0x24, ++0x80,0x00,0x06,0x24, ++0x41,0x4F,0x00,0x0C, ++0x10,0x00,0xB1,0xAF, ++0x00,0x00,0x83,0x96, ++0x01,0x00,0x16,0x24, ++0x00,0x40,0x63,0x34, ++0x13,0x16,0x00,0x08, ++0x00,0x00,0x83,0xA6, ++0xB0,0x1B,0x02,0x95, ++0x00,0x00,0x00,0x00, ++0x40,0x00,0x42,0x30, ++0xC1,0xFF,0x40,0x10, ++0x21,0x20,0x00,0x02, ++0x80,0x3D,0x03,0x8D, ++0x84,0x3D,0x02,0x8D, ++0x80,0x1F,0x03,0x00, ++0x25,0x18,0x43,0x00, ++0x04,0x00,0x05,0x24, ++0x01,0x00,0x42,0x24, ++0x1C,0x00,0xA6,0x27, ++0x21,0x38,0x20,0x02, ++0x84,0x3D,0x02,0xAD, ++0x68,0x4F,0x00,0x0C, ++0x1C,0x00,0xA3,0xAF, ++0xF7,0x15,0x00,0x08, ++0x21,0x80,0x40,0x00, ++0x02,0x80,0x04,0x3C, ++0x02,0x80,0x05,0x3C, ++0xA4,0xE1,0x84,0x24, ++0x2F,0x55,0x00,0x0C, ++0xF8,0xEA,0xA5,0x24, ++0x3C,0x00,0xBF,0x8F, ++0x38,0x00,0xB6,0x8F, ++0x34,0x00,0xB5,0x8F, ++0x30,0x00,0xB4,0x8F, ++0x2C,0x00,0xB3,0x8F, ++0x28,0x00,0xB2,0x8F, ++0x24,0x00,0xB1,0x8F, ++0x20,0x00,0xB0,0x8F, ++0x08,0x00,0xE0,0x03, ++0x40,0x00,0xBD,0x27, ++0x02,0x80,0x03,0x3C, ++0x30,0x1F,0x63,0x24, ++0xB0,0x1B,0x62,0x94, ++0x01,0x00,0x05,0x24, ++0x21,0x20,0x00,0x00, ++0xEF,0xFF,0x42,0x30, ++0x20,0x00,0x42,0x34, ++0xB0,0x1B,0x62,0xA4, ++0xC8,0x00,0x02,0x24, ++0x74,0x3D,0x65,0xAC, ++0xB4,0x38,0x62,0xAC, ++0xD0,0x38,0x60,0xAC, ++0x6C,0x3D,0x60,0xAC, ++0xBC,0x15,0x00,0x08, ++0x70,0x3D,0x60,0xAC, ++0x08,0x00,0xE0,0x03, ++0x00,0x00,0x00,0x00, ++0xA8,0xFF,0xBD,0x27, ++0x50,0x00,0xBE,0xAF, ++0x40,0x00,0xB4,0xAF, ++0x3C,0x00,0xB3,0xAF, ++0x54,0x00,0xBF,0xAF, ++0x4C,0x00,0xB7,0xAF, ++0x48,0x00,0xB6,0xAF, ++0x44,0x00,0xB5,0xAF, ++0x38,0x00,0xB2,0xAF, ++0x34,0x00,0xB1,0xAF, ++0x30,0x00,0xB0,0xAF, ++0x21,0xA0,0x80,0x00, ++0x02,0x00,0x84,0x90, ++0x21,0xF0,0x00,0x00, ++0x24,0x00,0xA0,0xAF, ++0x0F,0x00,0x84,0x30, ++0xC0,0x20,0x04,0x00, ++0x21,0x20,0x94,0x00, ++0x18,0x00,0x93,0x24, ++0x00,0x60,0x12,0x40, ++0x01,0x00,0x41,0x36, ++0x01,0x00,0x21,0x38, ++0x00,0x60,0x81,0x40, ++0x02,0x80,0x15,0x3C, ++0x28,0x00,0x84,0x24, ++0x88,0x58,0xA5,0x26, ++0x39,0x52,0x00,0x0C, ++0x06,0x00,0x06,0x24, ++0x0F,0x00,0x40,0x14, ++0x02,0x80,0x16,0x3C, ++0xF4,0x5E,0xC2,0x92, ++0x00,0x00,0x00,0x00, ++0x29,0x00,0x40,0x14, ++0x02,0x80,0x02,0x3C, ++0xF4,0x5E,0xC2,0x92, ++0x00,0x00,0x00,0x00, ++0x07,0x00,0x40,0x14, ++0x02,0x80,0x02,0x3C, ++0x30,0x1F,0x50,0x24, ++0xB0,0x1B,0x02,0x96, ++0x00,0x00,0x00,0x00, ++0x00,0x01,0x42,0x30, ++0x3C,0x01,0x40,0x14, ++0x05,0x00,0x05,0x24, ++0x00,0x60,0x92,0x40, ++0x02,0x80,0x03,0x3C, ++0x30,0x1F,0x70,0x24, ++0xB0,0x1B,0x03,0x96, ++0x00,0x00,0x00,0x00, ++0x00,0x10,0x62,0x30, ++0x24,0x01,0x40,0x14, ++0x10,0x00,0x62,0x30, ++0xCB,0x00,0x40,0x14, ++0x10,0x00,0x64,0x26, ++0x02,0x80,0x04,0x3C, ++0x30,0x1F,0x92,0x24, ++0xB0,0x1B,0x42,0x96, ++0x00,0x00,0x00,0x00, ++0x00,0x01,0x42,0x30, ++0x4E,0x01,0x40,0x14, ++0x21,0x18,0x00,0x00, ++0x54,0x00,0xBF,0x8F, ++0x50,0x00,0xBE,0x8F, ++0x4C,0x00,0xB7,0x8F, ++0x48,0x00,0xB6,0x8F, ++0x44,0x00,0xB5,0x8F, ++0x40,0x00,0xB4,0x8F, ++0x3C,0x00,0xB3,0x8F, ++0x38,0x00,0xB2,0x8F, ++0x34,0x00,0xB1,0x8F, ++0x30,0x00,0xB0,0x8F, ++0x21,0x10,0x60,0x00, ++0x08,0x00,0xE0,0x03, ++0x58,0x00,0xBD,0x27, ++0x30,0x1F,0x43,0x24, ++0xB0,0x1B,0x62,0x94, ++0x00,0x00,0x00,0x00, ++0x00,0x01,0x42,0x30, ++0xD3,0xFF,0x40,0x10, ++0x00,0x00,0x00,0x00, ++0x6C,0x3B,0x62,0x8C, ++0x00,0x00,0x00,0x00, ++0xCF,0xFF,0x40,0x14, ++0x02,0x80,0x0B,0x3C, ++0x15,0x5F,0x62,0x91, ++0x00,0x00,0x00,0x00, ++0x55,0x01,0x40,0x14, ++0x00,0x00,0x00,0x00, ++0x02,0x80,0x02,0x3C, ++0x02,0x80,0x03,0x3C, ++0xFA,0x5E,0x40,0xA0, ++0x1C,0x5F,0x60,0xAC, ++0x02,0x80,0x03,0x3C, ++0x0E,0x5F,0x62,0x90, ++0xFD,0xFF,0x03,0x24, ++0x02,0x80,0x04,0x3C, ++0x24,0x10,0x43,0x00, ++0x0E,0x5F,0x82,0xA0, ++0x42,0xB0,0x17,0x3C, ++0x00,0x00,0xE3,0x92, ++0xEF,0xFF,0x02,0x24, ++0x03,0x00,0xE4,0x36, ++0x24,0x18,0x62,0x00, ++0x40,0x00,0x02,0x24, ++0x00,0x00,0xE3,0xA2, ++0x00,0x00,0x82,0xA0, ++0x02,0x80,0x04,0x3C, ++0xFC,0x5E,0x82,0x94, ++0x20,0x00,0x63,0x96, ++0xFF,0xFF,0x42,0x30, ++0x0A,0x00,0x43,0x10, ++0x02,0x80,0x07,0x3C, ++0x25,0xB0,0x02,0x3C, ++0x94,0x00,0x42,0x34, ++0xFC,0x5E,0x83,0xA4, ++0x00,0x00,0x43,0xA4, ++0xFC,0x5E,0x83,0x94, ++0x00,0x00,0x00,0x00, ++0xFF,0xFF,0x63,0x30, ++0x80,0x1A,0x03,0x00, ++0x00,0x5F,0xE3,0xAC, ++0x25,0xB0,0x04,0x3C, ++0x84,0x00,0x82,0x34, ++0x00,0x00,0x50,0x8C, ++0x80,0x00,0x84,0x34, ++0x00,0x00,0x82,0x8C, ++0x21,0x18,0x00,0x00, ++0x00,0x5F,0xE6,0x8C, ++0x00,0x88,0x10,0x00, ++0x21,0x80,0x00,0x00, ++0x25,0x80,0x02,0x02, ++0x25,0x88,0x23,0x02, ++0x21,0x20,0x00,0x02, ++0x21,0x28,0x20,0x02, ++0x28,0x00,0xA7,0xAF, ++0xBA,0x34,0x00,0x0C, ++0x2C,0x00,0xAB,0xAF, ++0x28,0x00,0xA7,0x8F, ++0x02,0x80,0x0A,0x3C, ++0x21,0x28,0x00,0x00, ++0x00,0x5F,0xE8,0x8C, ++0x04,0x5F,0x43,0x95, ++0x21,0x28,0xB1,0x00, ++0x23,0x48,0x02,0x01, ++0x21,0x20,0x30,0x01, ++0x2B,0x10,0x90,0x00, ++0xFF,0xFF,0x63,0x30, ++0x80,0x1A,0x03,0x00, ++0x21,0x28,0xA2,0x00, ++0x21,0x38,0x00,0x00, ++0x2B,0x40,0x83,0x00, ++0x23,0x28,0xA7,0x00, ++0x23,0x20,0x83,0x00, ++0x23,0x28,0xA8,0x00, ++0x02,0x80,0x03,0x3C, ++0x20,0x5F,0x64,0xAC, ++0x24,0x5F,0x65,0xAC, ++0x04,0x5F,0x42,0x95, ++0x2C,0x00,0xAB,0x8F, ++0xFF,0xFF,0x42,0x30, ++0x80,0x12,0x02,0x00, ++0x2B,0x10,0x49,0x00, ++0x31,0x01,0x40,0x10, ++0x00,0x00,0x00,0x00, ++0x04,0x5F,0x42,0x95, ++0x00,0x00,0xE4,0x92, ++0xFB,0xFF,0x03,0x24, ++0xFF,0xFF,0x42,0x30, ++0x80,0x12,0x02,0x00, ++0x24,0x20,0x83,0x00, ++0x23,0x48,0x22,0x01, ++0x00,0x00,0xE4,0xA2, ++0x01,0x00,0x06,0x24, ++0x04,0x00,0x20,0x11, ++0x01,0x00,0x04,0x24, ++0x80,0x10,0x09,0x00, ++0x21,0x10,0x49,0x00, ++0x80,0x30,0x02,0x00, ++0x8C,0x23,0x00,0x0C, ++0x21,0x28,0x00,0x00, ++0x42,0xB0,0x02,0x3C, ++0x22,0x00,0x03,0x24, ++0x03,0x00,0x42,0x34, ++0x00,0x00,0x43,0xA0, ++0x00,0x00,0x87,0x8E, ++0x05,0x00,0x05,0x24, ++0x24,0x00,0x64,0x26, ++0xFF,0x3F,0xE7,0x30, ++0xDC,0xFF,0xE7,0x24, ++0x55,0x1D,0x00,0x0C, ++0x20,0x00,0xA6,0x27, ++0x2E,0x00,0x40,0x10, ++0x21,0x28,0x40,0x00, ++0xF4,0x5E,0xC2,0x92, ++0x02,0x00,0x03,0x24, ++0xFF,0x00,0x42,0x30, ++0x45,0x01,0x43,0x10, ++0x02,0x80,0x07,0x3C, ++0x02,0x00,0xA2,0x90, ++0x00,0x00,0x00,0x00, ++0x08,0x00,0x40,0x14, ++0x00,0x00,0x00,0x00, ++0x04,0x00,0xA3,0x90, ++0x00,0x00,0x00,0x00, ++0x01,0x00,0x62,0x30, ++0x04,0x00,0x40,0x10, ++0x02,0x80,0x02,0x3C, ++0x01,0x00,0x1E,0x24, ++0x12,0x5F,0x5E,0xA0, ++0x04,0x00,0xA3,0x90, ++0x20,0x00,0xA7,0x8F, ++0x00,0x00,0x00,0x00, ++0x04,0x00,0xE2,0x28, ++0x18,0x00,0x40,0x14, ++0xFE,0x00,0x66,0x30, ++0x02,0x80,0x02,0x3C, ++0x30,0x1F,0x43,0x24, ++0x50,0x39,0x64,0x94, ++0xC0,0x10,0x06,0x00, ++0x2A,0x10,0x82,0x00, ++0x12,0x00,0x40,0x14, ++0x02,0x80,0x03,0x3C, ++0x21,0x10,0xC7,0x00, ++0xFD,0xFF,0x42,0x24, ++0xC0,0x10,0x02,0x00, ++0x2A,0x10,0x44,0x00, ++0x0C,0x00,0x40,0x14, ++0xC2,0x10,0x04,0x00, ++0x23,0x30,0x46,0x00, ++0x21,0x18,0xA6,0x00, ++0x05,0x00,0x62,0x90, ++0x07,0x00,0x84,0x30, ++0x01,0x00,0x03,0x24, ++0x07,0x10,0x82,0x00, ++0x24,0x00,0xA4,0x8F, ++0x01,0x00,0x42,0x30, ++0x0B,0x20,0x62,0x00, ++0x24,0x00,0xA4,0xAF, ++0x02,0x80,0x03,0x3C, ++0x0E,0x5F,0x62,0x90, ++0xEF,0xFF,0x03,0x24, ++0x02,0x80,0x04,0x3C, ++0x24,0x10,0x43,0x00, ++0x0E,0x5F,0x82,0xA0, ++0xF4,0x5E,0xC3,0x92, ++0x02,0x80,0x02,0x3C, ++0x24,0xE9,0x42,0x24, ++0xFF,0x00,0x63,0x30, ++0x80,0x18,0x03,0x00, ++0x21,0x18,0x62,0x00, ++0x00,0x00,0x66,0x8C, ++0x24,0x00,0xA5,0x8F, ++0x09,0xF8,0xC0,0x00, ++0x21,0x20,0xC0,0x03, ++0x90,0x16,0x00,0x08, ++0x00,0x00,0x00,0x00, ++0x88,0x58,0xA5,0x26, ++0x39,0x52,0x00,0x0C, ++0x06,0x00,0x06,0x24, ++0x33,0xFF,0x40,0x14, ++0x02,0x80,0x04,0x3C, ++0x06,0x00,0x02,0x24, ++0x0A,0x3E,0x02,0xA2, ++0xEC,0x38,0x00,0xAE, ++0x00,0x00,0x84,0x8E, ++0x0C,0x00,0x12,0x24, ++0xFF,0x3F,0x82,0x30, ++0xE8,0xFF,0x42,0x24, ++0x2A,0x10,0x42,0x02, ++0xA4,0x00,0x40,0x10, ++0x21,0xA8,0x00,0x02, ++0x7D,0x17,0x00,0x08, ++0x21,0x80,0x72,0x02, ++0x19,0x00,0x03,0x92, ++0xFF,0x3F,0x82,0x30, ++0xE8,0xFF,0x42,0x24, ++0x21,0x18,0x72,0x00, ++0x02,0x00,0x72,0x24, ++0x2A,0x10,0x42,0x02, ++0x9A,0x00,0x40,0x10, ++0x21,0x80,0x72,0x02, ++0x18,0x00,0x03,0x92, ++0xDD,0x00,0x02,0x24, ++0xF5,0xFF,0x62,0x14, ++0x1A,0x00,0x11,0x26, ++0x02,0x80,0x05,0x3C, ++0xC4,0xDD,0xA5,0x24, ++0x21,0x20,0x20,0x02, ++0x39,0x52,0x00,0x0C, ++0x03,0x00,0x06,0x24, ++0x20,0x01,0x40,0x10, ++0x02,0x80,0x05,0x3C, ++0xC0,0xDD,0xA5,0x24, ++0x21,0x20,0x20,0x02, ++0x39,0x52,0x00,0x0C, ++0x03,0x00,0x06,0x24, ++0x1A,0x01,0x40,0x10, ++0x02,0x80,0x05,0x3C, ++0xBC,0xDD,0xA5,0x24, ++0x21,0x20,0x20,0x02, ++0x39,0x52,0x00,0x0C, ++0x03,0x00,0x06,0x24, ++0x0F,0x01,0x40,0x10, ++0x02,0x80,0x05,0x3C, ++0xB8,0xDD,0xA5,0x24, ++0x21,0x20,0x20,0x02, ++0x39,0x52,0x00,0x0C, ++0x03,0x00,0x06,0x24, ++0x09,0x01,0x40,0x10, ++0x02,0x80,0x05,0x3C, ++0xB4,0xDD,0xA5,0x24, ++0x21,0x20,0x20,0x02, ++0x39,0x52,0x00,0x0C, ++0x03,0x00,0x06,0x24, ++0x03,0x01,0x40,0x10, ++0x02,0x80,0x05,0x3C, ++0xAC,0xDD,0xA5,0x24, ++0x21,0x20,0x20,0x02, ++0x39,0x52,0x00,0x0C, ++0x03,0x00,0x06,0x24, ++0x64,0x01,0x40,0x10, ++0x02,0x80,0x05,0x3C, ++0xA8,0xDD,0xA5,0x24, ++0x21,0x20,0x20,0x02, ++0x39,0x52,0x00,0x0C, ++0x03,0x00,0x06,0x24, ++0x57,0x01,0x40,0x10, ++0x02,0x80,0x05,0x3C, ++0xB0,0xDD,0xA5,0x24, ++0x21,0x20,0x20,0x02, ++0x39,0x52,0x00,0x0C, ++0x03,0x00,0x06,0x24, ++0x4A,0x01,0x40,0x10, ++0x02,0x80,0x05,0x3C, ++0x21,0x20,0x20,0x02, ++0x9C,0xDD,0xA5,0x24, ++0x39,0x52,0x00,0x0C, ++0x06,0x00,0x06,0x24, ++0x3E,0x01,0x40,0x10, ++0x02,0x80,0x02,0x3C, ++0x00,0x00,0x84,0x8E, ++0x75,0x17,0x00,0x08, ++0x00,0x00,0x00,0x00, ++0x92,0x10,0x00,0x0C, ++0x21,0x20,0x80,0x02, ++0x21,0x18,0x00,0x00, ++0x54,0x00,0xBF,0x8F, ++0x50,0x00,0xBE,0x8F, ++0x4C,0x00,0xB7,0x8F, ++0x48,0x00,0xB6,0x8F, ++0x44,0x00,0xB5,0x8F, ++0x40,0x00,0xB4,0x8F, ++0x3C,0x00,0xB3,0x8F, ++0x38,0x00,0xB2,0x8F, ++0x34,0x00,0xB1,0x8F, ++0x30,0x00,0xB0,0x8F, ++0x21,0x10,0x60,0x00, ++0x08,0x00,0xE0,0x03, ++0x58,0x00,0xBD,0x27, ++0x00,0x00,0x87,0x8E, ++0x24,0x00,0x64,0x26, ++0xFF,0x3F,0xE7,0x30, ++0xDC,0xFF,0xE7,0x24, ++0x55,0x1D,0x00,0x0C, ++0x20,0x00,0xA6,0x27, ++0xBE,0xFE,0x40,0x10, ++0x21,0x28,0x40,0x00, ++0x20,0x00,0xA7,0x8F, ++0x04,0x00,0x42,0x90, ++0x04,0x00,0xE3,0x28, ++0xB9,0xFE,0x60,0x14, ++0xFE,0x00,0x46,0x30, ++0x50,0x39,0x04,0x96, ++0xC0,0x10,0x06,0x00, ++0x2A,0x10,0x82,0x00, ++0xB4,0xFE,0x40,0x14, ++0x21,0x10,0xC7,0x00, ++0xFD,0xFF,0x42,0x24, ++0xC0,0x10,0x02,0x00, ++0x2A,0x10,0x44,0x00, ++0xAF,0xFE,0x40,0x14, ++0xC2,0x10,0x04,0x00, ++0x23,0x30,0x46,0x00, ++0x21,0x18,0xA6,0x00, ++0x05,0x00,0x62,0x90, ++0x07,0x00,0x84,0x30, ++0x07,0x10,0x82,0x00, ++0x01,0x00,0x42,0x30, ++0xA7,0xFE,0x40,0x10, ++0x00,0x00,0x00,0x00, ++0xCD,0x4E,0x00,0x0C, ++0x21,0x20,0x00,0x00, ++0x90,0x16,0x00,0x08, ++0x00,0x00,0x00,0x00, ++0x88,0x58,0xA5,0x26, ++0x10,0x00,0x64,0x26, ++0x39,0x52,0x00,0x0C, ++0x06,0x00,0x06,0x24, ++0xCB,0xFF,0x40,0x14, ++0x21,0x18,0x00,0x00, ++0xB0,0x1B,0x43,0x96, ++0x00,0x00,0x00,0x00, ++0x01,0x00,0x62,0x30, ++0x0D,0x00,0x40,0x14, ++0x04,0x00,0x62,0x30, ++0x83,0x00,0x40,0x14, ++0x02,0x80,0x03,0x3C, ++0x30,0x1F,0x70,0x24, ++0x0B,0x3E,0x02,0x92, ++0x00,0x00,0x00,0x00, ++0x01,0x00,0x44,0x24, ++0xFF,0x00,0x83,0x30, ++0x0B,0x00,0x02,0x24, ++0x45,0x00,0x62,0x10, ++0x21,0x18,0x00,0x00, ++0xA1,0x16,0x00,0x08, ++0x0B,0x3E,0x04,0xA2, ++0x00,0x60,0x03,0x40, ++0x01,0x00,0x61,0x34, ++0x01,0x00,0x21,0x38, ++0x00,0x60,0x81,0x40, ++0xD4,0x1E,0x42,0x8E, ++0x00,0x00,0x00,0x00, ++0x01,0x00,0x42,0x24, ++0xD4,0x1E,0x42,0xAE, ++0x00,0x60,0x83,0x40, ++0xFB,0x17,0x00,0x08, ++0x02,0x80,0x03,0x3C, ++0x15,0x5F,0x62,0x91, ++0x00,0x00,0x00,0x00, ++0xFF,0xFF,0x42,0x24, ++0x15,0x5F,0x62,0xA1, ++0xBD,0x16,0x00,0x08, ++0x02,0x80,0x02,0x3C, ++0x02,0x80,0x04,0x3C, ++0xFC,0xE2,0x84,0x24, ++0x2F,0x55,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x02,0x80,0x02,0x3C, ++0xE6,0x5D,0x46,0x90, ++0x01,0x00,0x03,0x24, ++0x10,0x00,0xC3,0x10, ++0x02,0x80,0x03,0x3C, ++0x53,0x16,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x54,0x00,0xBF,0x8F, ++0x50,0x00,0xBE,0x8F, ++0x4C,0x00,0xB7,0x8F, ++0x48,0x00,0xB6,0x8F, ++0x44,0x00,0xB5,0x8F, ++0x40,0x00,0xB4,0x8F, ++0x3C,0x00,0xB3,0x8F, ++0x38,0x00,0xB2,0x8F, ++0x34,0x00,0xB1,0x8F, ++0x30,0x00,0xB0,0x8F, ++0x21,0x10,0x60,0x00, ++0x08,0x00,0xE0,0x03, ++0x58,0x00,0xBD,0x27, ++0x30,0x1F,0x64,0x24, ++0x0A,0x3E,0x83,0x90, ++0x03,0x00,0x02,0x24, ++0x62,0x00,0x62,0x10, ++0x00,0x00,0x00,0x00, ++0x91,0x3E,0x86,0xA0, ++0x53,0x16,0x00,0x0C, ++0x90,0x3E,0x80,0xA0, ++0x21,0x18,0x00,0x08, ++0x00,0x00,0x00,0x00, ++0x15,0x5F,0x62,0x91, ++0x00,0x00,0x00,0x00, ++0x05,0x00,0x40,0x14, ++0x00,0x00,0x00,0x00, ++0x15,0x5F,0x62,0x91, ++0x00,0x00,0x00,0x00, ++0x01,0x00,0x42,0x24, ++0x15,0x5F,0x62,0xA1, ++0x00,0x00,0xE2,0x92, ++0xFB,0xFF,0x03,0x24, ++0x01,0x00,0x06,0x24, ++0x24,0x10,0x43,0x00, ++0x00,0x00,0xE2,0xA2, ++0x11,0x17,0x00,0x08, ++0x00,0x00,0x00,0x00, ++0x02,0x80,0x02,0x3C, ++0xE6,0x5D,0x43,0x90, ++0x01,0x00,0x11,0x24, ++0x53,0x00,0x71,0x10, ++0x0B,0x3E,0x00,0xA2, ++0x02,0x80,0x02,0x3C, ++0xEA,0x5D,0x44,0x90, ++0x02,0x00,0x03,0x24, ++0x6E,0xFF,0x83,0x14, ++0x21,0x18,0x00,0x00, ++0x00,0x00,0x87,0x8E, ++0x24,0x00,0x64,0x26, ++0x2A,0x00,0x05,0x24, ++0xFF,0x3F,0xE7,0x30, ++0xDC,0xFF,0xE7,0x24, ++0x55,0x1D,0x00,0x0C, ++0x20,0x00,0xA6,0x27, ++0x65,0xFF,0x40,0x10, ++0x21,0x18,0x00,0x00, ++0x02,0x00,0x43,0x90, ++0x00,0x00,0x00,0x00, ++0x02,0x00,0x62,0x30, ++0x4D,0x00,0x40,0x10, ++0x02,0x80,0x04,0x3C, ++0x01,0x00,0x62,0x30, ++0x4B,0x00,0x40,0x14, ++0x30,0x1F,0x85,0x24, ++0x02,0x80,0x02,0x3C, ++0xEB,0x5D,0x43,0x90, ++0x00,0x00,0x00,0x00, ++0xAA,0x00,0x71,0x10, ++0x00,0x00,0x00,0x00, ++0x10,0x23,0x02,0x8E, ++0xFF,0xEF,0x03,0x24, ++0x00,0x08,0x42,0x34, ++0x24,0x10,0x43,0x00, ++0x10,0x23,0x02,0xAE, ++0xBE,0x17,0x00,0x08, ++0x21,0x18,0x00,0x00, ++0x03,0x00,0xA2,0x90, ++0x02,0x80,0x04,0x3C, ++0x10,0x5F,0xE2,0xA0, ++0x02,0x00,0xA3,0x90, ++0x21,0x30,0x80,0x00, ++0x11,0x5F,0x83,0xA0, ++0x11,0x5F,0x82,0x90, ++0x00,0x00,0x00,0x00, ++0x22,0x00,0x40,0x14, ++0x00,0x00,0x00,0x00, ++0x10,0x5F,0xE2,0x90, ++0x00,0x00,0x00,0x00, ++0x11,0x5F,0xC2,0xA0, ++0x2A,0x17,0x00,0x08, ++0x00,0x00,0x00,0x00, ++0x0A,0x00,0x76,0x26, ++0x3B,0x51,0x00,0x0C, ++0x21,0x20,0xC0,0x02, ++0x20,0x00,0x10,0x24, ++0x32,0x00,0x50,0x10, ++0x21,0xA8,0x40,0x00, ++0x00,0x60,0x05,0x40, ++0x01,0x00,0xA1,0x34, ++0x01,0x00,0x21,0x38, ++0x00,0x60,0x81,0x40, ++0x80,0x18,0x15,0x00, ++0x21,0x18,0x75,0x00, ++0x02,0x80,0x02,0x3C, ++0x30,0x1F,0x44,0x24, ++0xC0,0x18,0x03,0x00, ++0x21,0x18,0x64,0x00, ++0x0C,0x1E,0x62,0x8C, ++0x00,0x00,0x00,0x00, ++0x01,0x00,0x42,0x24, ++0x0C,0x1E,0x62,0xAC, ++0x00,0x60,0x85,0x40, ++0xBE,0x17,0x00,0x08, ++0x21,0x18,0x00,0x00, ++0x90,0x3E,0x86,0xA0, ++0x53,0x16,0x00,0x0C, ++0x91,0x3E,0x80,0xA0, ++0x21,0x18,0x00,0x08, ++0x00,0x00,0x00,0x00, ++0x11,0x5F,0x82,0x90, ++0x00,0x00,0x00,0x00, ++0x11,0x5F,0xC2,0xA0, ++0x2A,0x17,0x00,0x08, ++0x00,0x00,0x00,0x00, ++0x64,0x12,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x4D,0x18,0x00,0x08, ++0x02,0x80,0x02,0x3C, ++0x02,0x80,0x04,0x3C, ++0x01,0x00,0x02,0x24, ++0x90,0xE2,0x84,0x24, ++0x18,0x18,0x00,0x08, ++0x0A,0x3E,0xA2,0xA2, ++0x02,0x80,0x04,0x3C, ++0x78,0xE2,0x84,0x24, ++0x18,0x18,0x00,0x08, ++0x0A,0x3E,0xA0,0xA2, ++0x30,0x1F,0x85,0x24, ++0x10,0x23,0xA2,0x8C, ++0xFF,0xEF,0x03,0x24, ++0xFF,0xF7,0x04,0x24, ++0x24,0x10,0x43,0x00, ++0x24,0x10,0x44,0x00, ++0x21,0x18,0x00,0x00, ++0xBE,0x17,0x00,0x08, ++0x10,0x23,0xA2,0xAC, ++0xFF,0xFF,0x04,0x24, ++0xE3,0x50,0x00,0x0C, ++0x21,0x28,0xC0,0x02, ++0xCB,0xFF,0x50,0x10, ++0x21,0xA8,0x40,0x00, ++0x00,0x00,0x87,0x8E, ++0x24,0x00,0x70,0x26, ++0x21,0x20,0x00,0x02, ++0xFF,0x3F,0xE7,0x30, ++0xDC,0xFF,0xE7,0x24, ++0x01,0x00,0x05,0x24, ++0x55,0x1D,0x00,0x0C, ++0x20,0x00,0xA6,0x27, ++0xDF,0xFD,0x40,0x10, ++0x21,0x18,0x00,0x00, ++0x20,0x00,0xA6,0x8F, ++0x02,0x00,0x45,0x24, ++0x10,0x52,0x00,0x0C, ++0x10,0x00,0xA4,0x27, ++0x00,0x00,0x87,0x8E, ++0x21,0x20,0x00,0x02, ++0x32,0x00,0x05,0x24, ++0xFF,0x3F,0xE7,0x30, ++0xDC,0xFF,0xE7,0x24, ++0x20,0x00,0xB1,0x8F, ++0x55,0x1D,0x00,0x0C, ++0x20,0x00,0xA6,0x27, ++0x09,0x00,0x40,0x10, ++0x00,0x00,0x00,0x00, ++0x20,0x00,0xA6,0x8F, ++0x10,0x00,0xA4,0x27, ++0x21,0x20,0x91,0x00, ++0x10,0x52,0x00,0x0C, ++0x02,0x00,0x45,0x24, ++0x20,0x00,0xA3,0x8F, ++0x00,0x00,0x00,0x00, ++0x21,0x88,0x23,0x02, ++0x10,0x00,0xA4,0x27, ++0x7D,0x50,0x00,0x0C, ++0x21,0x28,0x20,0x02, ++0x0F,0x00,0x42,0x30, ++0x00,0x81,0x15,0x00, ++0x21,0x28,0x20,0x02, ++0x10,0x00,0xA4,0x27, ++0x25,0x80,0x02,0x02, ++0xC2,0x50,0x00,0x0C, ++0xFF,0xFF,0x10,0x32, ++0x02,0x80,0x04,0x3C, ++0x21,0x88,0x40,0x00, ++0x21,0x38,0x40,0x00, ++0x21,0x28,0xA0,0x02, ++0x21,0x30,0x00,0x02, ++0x2F,0x55,0x00,0x0C, ++0x10,0xE3,0x84,0x24, ++0x21,0x20,0x00,0x02, ++0xC1,0x5B,0x00,0x0C, ++0x21,0x28,0x20,0x02, ++0x8E,0x3E,0x42,0x92, ++0x21,0x20,0xC0,0x02, ++0x21,0x28,0xA0,0x02, ++0x01,0x00,0x42,0x24, ++0x9C,0x0E,0x00,0x0C, ++0x8E,0x3E,0x42,0xA2, ++0x83,0x18,0x00,0x08, ++0x00,0x00,0x00,0x00, ++0x02,0x80,0x04,0x3C, ++0x30,0x1F,0x43,0x24, ++0xE4,0xE2,0x84,0x24, ++0x05,0x00,0x02,0x24, ++0x18,0x18,0x00,0x08, ++0x0A,0x3E,0x62,0xA0, ++0x02,0x80,0x02,0x3C, ++0x02,0x80,0x04,0x3C, ++0x30,0x1F,0x43,0x24, ++0xD0,0xE2,0x84,0x24, ++0x02,0x00,0x02,0x24, ++0x18,0x18,0x00,0x08, ++0x0A,0x3E,0x62,0xA0, ++0x02,0x80,0x02,0x3C, ++0x02,0x80,0x04,0x3C, ++0x30,0x1F,0x43,0x24, ++0xBC,0xE2,0x84,0x24, ++0x04,0x00,0x02,0x24, ++0x18,0x18,0x00,0x08, ++0x0A,0x3E,0x62,0xA0, ++0x02,0x80,0x02,0x3C, ++0x02,0x80,0x04,0x3C, ++0x30,0x1F,0x43,0x24, ++0xA8,0xE2,0x84,0x24, ++0x03,0x00,0x02,0x24, ++0x18,0x18,0x00,0x08, ++0x0A,0x3E,0x62,0xA0, ++0x10,0x23,0x02,0x8E, ++0xFF,0xF7,0x03,0x24, ++0x24,0x10,0x43,0x00, ++0x00,0x10,0x42,0x34, ++0x6C,0x18,0x00,0x08, ++0x10,0x23,0x02,0xAE, ++0xE8,0xFF,0xBD,0x27, ++0x10,0x00,0xB0,0xAF, ++0x02,0x80,0x10,0x3C, ++0x30,0x1F,0x02,0x26, ++0x14,0x00,0xBF,0xAF, ++0xB0,0x1B,0x43,0x94, ++0x21,0x28,0x00,0x00, ++0x00,0x01,0x62,0x30, ++0x03,0x00,0x40,0x10, ++0x01,0x00,0x64,0x30, ++0x06,0x00,0x80,0x14, ++0x00,0x10,0x62,0x30, ++0x14,0x00,0xBF,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x21,0x10,0xA0,0x00, ++0x08,0x00,0xE0,0x03, ++0x18,0x00,0xBD,0x27, ++0x08,0x00,0x40,0x14, ++0x02,0x00,0x03,0x3C, ++0x02,0x80,0x02,0x3C, ++0xF6,0x5E,0x43,0x90, ++0x0C,0x00,0x02,0x24, ++0x0F,0x00,0x63,0x30, ++0x0A,0x00,0x62,0x10, ++0x21,0x20,0x00,0x00, ++0x02,0x00,0x03,0x3C, ++0x30,0x1F,0x04,0x26, ++0x20,0xBF,0x63,0x34, ++0x08,0x39,0x83,0xAC, ++0x14,0x00,0xBF,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x21,0x10,0xA0,0x00, ++0x08,0x00,0xE0,0x03, ++0x18,0x00,0xBD,0x27, ++0xCD,0x4E,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x02,0x00,0x03,0x3C, ++0x30,0x1F,0x04,0x26, ++0x20,0xBF,0x63,0x34, ++0x33,0x19,0x00,0x08, ++0x08,0x39,0x83,0xAC, ++0xE0,0xFF,0xBD,0x27, ++0x14,0x00,0xB1,0xAF, ++0x02,0x80,0x11,0x3C, ++0x1C,0x00,0xBF,0xAF, ++0x18,0x00,0xB2,0xAF, ++0x10,0x00,0xB0,0xAF, ++0x30,0x1F,0x25,0x26, ++0x6C,0x3B,0xA2,0x8C, ++0x00,0x10,0x03,0x3C, ++0x24,0x10,0x43,0x00, ++0x21,0x00,0x40,0x10, ++0x00,0x00,0x00,0x00, ++0x9B,0x3B,0xA6,0x90, ++0x9C,0x3B,0xA4,0x90, ++0xFF,0x00,0xC3,0x30, ++0x40,0x10,0x03,0x00, ++0x21,0x10,0x43,0x00, ++0x80,0x10,0x02,0x00, ++0x21,0x10,0x43,0x00, ++0x01,0x00,0x84,0x24, ++0x80,0x10,0x02,0x00, ++0xFF,0x00,0x83,0x30, ++0x21,0x10,0x45,0x00, ++0x21,0x10,0x43,0x00, ++0x9C,0x3B,0xA4,0xA0, ++0x38,0x3B,0x43,0x90, ++0x00,0x00,0x00,0x00, ++0x21,0x00,0x60,0x10, ++0x01,0x00,0xC2,0x24, ++0xFF,0x00,0xC2,0x30, ++0x22,0x00,0x40,0x14, ++0x30,0x1F,0x30,0x26, ++0x9C,0x3B,0xA2,0x90, ++0x00,0x00,0x00,0x00, ++0x21,0x10,0x45,0x00, ++0x38,0x3B,0x43,0x90, ++0x00,0x00,0x00,0x00, ++0xFF,0x00,0x64,0x30, ++0x1A,0x00,0x80,0x10, ++0x00,0x00,0x00,0x00, ++0x67,0x3B,0xA2,0x90, ++0x30,0x3B,0xA3,0xA0, ++0x4F,0x0C,0x00,0x0C, ++0x31,0x3B,0xA2,0xA0, ++0x30,0x1F,0x30,0x26, ++0x70,0x3B,0x03,0x8E, ++0x01,0x00,0x02,0x24, ++0x7C,0x00,0x62,0x10, ++0x00,0x00,0x00,0x00, ++0x6C,0x3B,0x03,0x8E, ++0x00,0x10,0x02,0x3C, ++0x3C,0x00,0x04,0x24, ++0x26,0x18,0x62,0x00, ++0x98,0x38,0x04,0xAE, ++0x6C,0x3B,0x03,0xAE, ++0x1C,0x00,0xBF,0x8F, ++0x18,0x00,0xB2,0x8F, ++0x14,0x00,0xB1,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x08,0x00,0xE0,0x03, ++0x20,0x00,0xBD,0x27, ++0x21,0x30,0x40,0x00, ++0x9B,0x3B,0xA2,0xA0, ++0x5C,0x19,0x00,0x08, ++0x9C,0x3B,0xA0,0xA0, ++0x99,0x3B,0x03,0x92, ++0x9A,0x3B,0x02,0x92, ++0xFF,0x00,0x64,0x30, ++0x30,0x3B,0x03,0xA2, ++0x4F,0x0C,0x00,0x0C, ++0x31,0x3B,0x02,0xA2, ++0xB0,0x1B,0x03,0x96, ++0x00,0x00,0x00,0x00, ++0x00,0x01,0x62,0x30, ++0x09,0x00,0x40,0x10, ++0x01,0x00,0x62,0x30, ++0x08,0x00,0x40,0x10, ++0x30,0x1F,0x30,0x26, ++0x02,0x80,0x02,0x3C, ++0xF6,0x5E,0x43,0x90, ++0x0C,0x00,0x02,0x24, ++0x0F,0x00,0x63,0x30, ++0x61,0x00,0x62,0x10, ++0x00,0x00,0x00,0x00, ++0x30,0x1F,0x30,0x26, ++0x9E,0x3B,0x04,0x96, ++0xA0,0x3B,0x05,0x92, ++0x12,0x0D,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0xC1,0x48,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x6C,0x3B,0x00,0xAE, ++0x00,0x60,0x12,0x40, ++0x01,0x00,0x41,0x36, ++0x01,0x00,0x21,0x38, ++0x00,0x60,0x81,0x40, ++0xB0,0x1B,0x02,0x96, ++0x00,0x00,0x00,0x00, ++0x00,0x01,0x42,0x30, ++0x3F,0x00,0x40,0x10, ++0x02,0x80,0x02,0x3C, ++0xF4,0x5E,0x43,0x90, ++0x00,0x00,0x00,0x00, ++0x3C,0x00,0x60,0x10, ++0x02,0x80,0x02,0x3C, ++0x02,0x80,0x03,0x3C, ++0xF6,0x5E,0x62,0x90, ++0x00,0x00,0x00,0x00, ++0x0F,0x00,0x42,0x30, ++0x04,0x00,0x42,0x28, ++0x41,0x00,0x40,0x14, ++0x04,0x00,0x04,0x24, ++0x02,0x80,0x03,0x3C, ++0x15,0x5F,0x62,0x90, ++0x00,0x00,0x00,0x00, ++0x05,0x00,0x40,0x14, ++0x00,0x00,0x00,0x00, ++0x15,0x5F,0x62,0x90, ++0x00,0x00,0x00,0x00, ++0x01,0x00,0x42,0x24, ++0x15,0x5F,0x62,0xA0, ++0x00,0x60,0x92,0x40, ++0x25,0xB0,0x07,0x3C, ++0x30,0x1F,0x30,0x26, ++0xB0,0x1B,0x04,0x96, ++0x48,0x00,0xE6,0x34, ++0x00,0x00,0xC3,0x8C, ++0xFF,0xEF,0x84,0x30, ++0x80,0x00,0x02,0x3C, ++0x25,0x18,0x62,0x00, ++0x00,0x01,0x85,0x30, ++0x00,0x00,0xC3,0xAC, ++0x02,0x80,0x08,0x3C, ++0x05,0x00,0xA0,0x10, ++0xB0,0x1B,0x04,0xA6, ++0x00,0x00,0xC2,0x8C, ++0x04,0x00,0x03,0x3C, ++0x25,0x10,0x43,0x00, ++0x00,0x00,0xC2,0xAC, ++0x30,0x1F,0x02,0x8D, ++0xFF,0xF0,0x03,0x24, ++0xA1,0x3B,0x05,0x92, ++0x24,0x10,0x43,0x00, ++0x00,0x01,0x42,0x34, ++0x0F,0xFF,0x03,0x24, ++0x24,0x10,0x43,0x00, ++0x10,0x00,0x42,0x34, ++0xF0,0xFF,0x03,0x24, ++0x1C,0x00,0xBF,0x8F, ++0x18,0x00,0xB2,0x8F, ++0x14,0x00,0xB1,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x24,0x10,0x43,0x00, ++0x4C,0x00,0xE3,0x34, ++0x01,0x00,0x42,0x34, ++0x00,0x00,0x65,0xA0, ++0x64,0x03,0xE4,0x34, ++0x07,0x00,0x03,0x24, ++0x20,0x00,0xBD,0x27, ++0x30,0x1F,0x02,0xAD, ++0x00,0x00,0x83,0xA0, ++0x08,0x00,0xE0,0x03, ++0x00,0x00,0x00,0x00, ++0x02,0x80,0x02,0x3C, ++0x15,0x5F,0x40,0xA0, ++0x02,0x80,0x03,0x3C, ++0xF5,0x5E,0x64,0x90, ++0x01,0x00,0x05,0x24, ++0x64,0x31,0x00,0x0C, ++0xFF,0x00,0x84,0x30, ++0xB8,0x19,0x00,0x08, ++0x00,0x00,0x00,0x00, ++0x13,0x0F,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x70,0x19,0x00,0x08, ++0x00,0x00,0x00,0x00, ++0x64,0x31,0x00,0x0C, ++0x01,0x00,0x05,0x24, ++0xB0,0x19,0x00,0x08, ++0x02,0x80,0x03,0x3C, ++0xCD,0x4E,0x00,0x0C, ++0x21,0x20,0x00,0x00, ++0x94,0x19,0x00,0x08, ++0x30,0x1F,0x30,0x26, ++0x0C,0x00,0x82,0x8C, ++0x00,0x00,0x00,0x00, ++0x3F,0x00,0x42,0x30, ++0x04,0x00,0x42,0x28, ++0x17,0x00,0x40,0x10, ++0x00,0x00,0x00,0x00, ++0x25,0xB0,0x02,0x3C, ++0x24,0x08,0x42,0x34, ++0x00,0x00,0x43,0x8C, ++0x00,0x00,0x00,0x00, ++0x00,0x02,0x63,0x30, ++0x15,0x00,0x60,0x14, ++0x01,0x00,0x02,0x24, ++0x05,0x00,0xA3,0x90, ++0x00,0x00,0x00,0x00, ++0x82,0x21,0x03,0x00, ++0x28,0x00,0x82,0x10, ++0xF5,0xFF,0x02,0x24, ++0x02,0x00,0x82,0x28, ++0x3B,0x00,0x40,0x14, ++0x02,0x00,0x02,0x24, ++0x2F,0x00,0x82,0x10, ++0xE9,0xFF,0x02,0x24, ++0x03,0x00,0x02,0x24, ++0x24,0x00,0x82,0x10, ++0x00,0x00,0x00,0x00, ++0x08,0x00,0xE0,0x03, ++0x05,0x00,0xC2,0x24, ++0x04,0x00,0xA2,0x90, ++0x00,0x00,0x00,0x00, ++0x42,0x10,0x02,0x00, ++0x08,0x00,0xE0,0x03, ++0x96,0xFF,0x42,0x24, ++0x05,0x00,0xA3,0x90, ++0x00,0x00,0x00,0x00, ++0x60,0x00,0x64,0x30, ++0x42,0x21,0x04,0x00, ++0x0F,0x00,0x82,0x10, ++0x1F,0x00,0x62,0x30, ++0x02,0x00,0x82,0x28, ++0x1F,0x00,0x40,0x14, ++0x02,0x00,0x02,0x24, ++0x16,0x00,0x82,0x10, ++0x1F,0x00,0x62,0x30, ++0x03,0x00,0x02,0x24, ++0xEC,0xFF,0x82,0x14, ++0x00,0x00,0x00,0x00, ++0x1F,0x00,0x62,0x30, ++0x40,0x10,0x02,0x00, ++0xDD,0xFF,0x03,0x24, ++0x23,0x30,0x62,0x00, ++0x08,0x00,0xE0,0x03, ++0x05,0x00,0xC2,0x24, ++0x40,0x10,0x02,0x00, ++0xF5,0xFF,0x03,0x24, ++0x2A,0x1A,0x00,0x08, ++0x23,0x30,0x62,0x00, ++0x3E,0x00,0x63,0x30, ++0x23,0x30,0x43,0x00, ++0x08,0x00,0xE0,0x03, ++0x05,0x00,0xC2,0x24, ++0x3E,0x00,0x63,0x30, ++0xDD,0xFF,0x02,0x24, ++0x32,0x1A,0x00,0x08, ++0x23,0x30,0x43,0x00, ++0x40,0x10,0x02,0x00, ++0xE9,0xFF,0x03,0x24, ++0x2A,0x1A,0x00,0x08, ++0x23,0x30,0x62,0x00, ++0x3E,0x00,0x63,0x30, ++0x32,0x1A,0x00,0x08, ++0x23,0x30,0x43,0x00, ++0xD1,0xFF,0x80,0x14, ++0x00,0x00,0x00,0x00, ++0x1F,0x00,0x62,0x30, ++0x40,0x10,0x02,0x00, ++0xF8,0xFF,0x03,0x24, ++0x2A,0x1A,0x00,0x08, ++0x23,0x30,0x62,0x00, ++0xCA,0xFF,0x80,0x14, ++0x00,0x00,0x00,0x00, ++0x3E,0x00,0x63,0x30, ++0xF8,0xFF,0x02,0x24, ++0x32,0x1A,0x00,0x08, ++0x23,0x30,0x43,0x00, ++0x63,0x00,0x82,0x24, ++0x77,0x00,0x42,0x2C, ++0x00,0x00,0x85,0x28, ++0x04,0x00,0x40,0x10, ++0x21,0x18,0x00,0x00, ++0x64,0x00,0x82,0x24, ++0x64,0x00,0x03,0x24, ++0x0B,0x18,0x45,0x00, ++0x08,0x00,0xE0,0x03, ++0x21,0x10,0x60,0x00, ++0x02,0x80,0x09,0x3C, ++0x30,0x1F,0x28,0x25, ++0x80,0x36,0x06,0x8D, ++0xFF,0xFF,0x02,0x34, ++0x3F,0x00,0xC2,0x10, ++0x21,0x38,0x80,0x00, ++0x2B,0x10,0xC7,0x00, ++0x30,0x00,0x40,0x10, ++0x02,0x19,0x06,0x00, ++0x21,0x10,0xC7,0x00, ++0x23,0x10,0x43,0x00, ++0x10,0x00,0x46,0x24, ++0x80,0x36,0x06,0xAD, ++0x30,0x1F,0x26,0x25, ++0x04,0x00,0xC4,0x8C, ++0x84,0x36,0x02,0xAD, ++0xFF,0xFF,0x02,0x34, ++0x2F,0x00,0x82,0x10, ++0x00,0x00,0x00,0x00, ++0x2B,0x10,0x87,0x00, ++0x1F,0x00,0x40,0x10, ++0x02,0x19,0x04,0x00, ++0x21,0x10,0x87,0x00, ++0x23,0x10,0x43,0x00, ++0x10,0x00,0x44,0x24, ++0x04,0x00,0xC4,0xAC, ++0x84,0x36,0xC2,0xAC, ++0xC0,0x10,0x05,0x00, ++0x21,0x10,0x45,0x00, ++0x80,0x10,0x02,0x00, ++0x21,0x10,0x45,0x00, ++0x30,0x1F,0x23,0x25, ++0x80,0x10,0x02,0x00, ++0x21,0x28,0x43,0x00, ++0x0C,0x24,0xA6,0x8C, ++0x00,0x21,0x07,0x00, ++0xFF,0xFF,0xC2,0x38, ++0x0A,0x30,0x82,0x00, ++0x2B,0x18,0xC7,0x00, ++0x07,0x00,0x60,0x10, ++0x21,0x10,0xC7,0x00, ++0x02,0x19,0x06,0x00, ++0x23,0x10,0x43,0x00, ++0x10,0x00,0x46,0x24, ++0x0C,0x24,0xA6,0xAC, ++0x08,0x00,0xE0,0x03, ++0x10,0x24,0xA2,0xAC, ++0x02,0x19,0x06,0x00, ++0x23,0x10,0x43,0x00, ++0x0C,0x24,0xA2,0xAC, ++0x08,0x00,0xE0,0x03, ++0x10,0x24,0xA2,0xAC, ++0x21,0x10,0x87,0x00, ++0x23,0x10,0x43,0x00, ++0x70,0x1A,0x00,0x08, ++0x04,0x00,0xC2,0xAC, ++0x21,0x10,0xC7,0x00, ++0x30,0x1F,0x26,0x25, ++0x04,0x00,0xC4,0x8C, ++0x23,0x10,0x43,0x00, ++0x80,0x36,0x02,0xAD, ++0x84,0x36,0x02,0xAD, ++0xFF,0xFF,0x02,0x34, ++0xD4,0xFF,0x82,0x14, ++0x2B,0x10,0x87,0x00, ++0x00,0x21,0x07,0x00, ++0x69,0x1A,0x00,0x08, ++0x04,0x00,0xC4,0xAC, ++0x00,0x31,0x04,0x00, ++0x5C,0x1A,0x00,0x08, ++0x80,0x36,0x06,0xAD, ++0xA0,0xFF,0xBD,0x27, ++0x54,0x00,0xB7,0xAF, ++0x5C,0x00,0xBF,0xAF, ++0x58,0x00,0xBE,0xAF, ++0x50,0x00,0xB6,0xAF, ++0x4C,0x00,0xB5,0xAF, ++0x48,0x00,0xB4,0xAF, ++0x44,0x00,0xB3,0xAF, ++0x40,0x00,0xB2,0xAF, ++0x3C,0x00,0xB1,0xAF, ++0x38,0x00,0xB0,0xAF, ++0x02,0x80,0x17,0x3C, ++0x02,0x80,0x02,0x3C, ++0x64,0x57,0x45,0x8C, ++0x00,0x80,0x04,0x3C, ++0x74,0x6A,0x83,0x24, ++0x64,0x57,0x44,0x24, ++0x25,0xB0,0x02,0x3C, ++0x18,0x03,0x42,0x34, ++0x00,0x00,0x43,0xAC, ++0x7F,0x00,0xA4,0x10, ++0x02,0x80,0x09,0x3C, ++0x02,0x80,0x02,0x3C, ++0x40,0xEB,0x29,0x25, ++0x44,0xEB,0x42,0x24, ++0x00,0x00,0x35,0x8D, ++0x00,0x00,0x53,0x8C, ++0x02,0x80,0x03,0x3C, ++0x48,0xEB,0x63,0x24, ++0x00,0x00,0x7E,0x8C, ++0x34,0x38,0xB4,0x8E, ++0x21,0x20,0x00,0x00, ++0x21,0xB0,0x00,0x00, ++0x08,0x00,0x82,0x8E, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x62,0xAE, ++0x08,0x00,0x83,0x96, ++0x02,0x80,0x02,0x3C, ++0xB0,0x01,0x00,0x0C, ++0x25,0x90,0x62,0x00, ++0x00,0x60,0x01,0x40, ++0x01,0x00,0x21,0x34, ++0x01,0x00,0x21,0x38, ++0x00,0x60,0x81,0x40, ++0xAC,0x1B,0xA3,0x96, ++0xD0,0x37,0xA2,0x8E, ++0x00,0x00,0x00,0x00, ++0x21,0x10,0x43,0x00, ++0x00,0x00,0xC2,0xAF, ++0x00,0x60,0x01,0x40, ++0x01,0x00,0x21,0x34, ++0x00,0x60,0x81,0x40, ++0xF4,0x1A,0x00,0x08, ++0x00,0x00,0x00,0x00, ++0x17,0x00,0xC7,0x90, ++0x16,0x00,0xC8,0x90, ++0x32,0x3B,0xA2,0x96, ++0xFF,0x00,0xE3,0x30, ++0x00,0x1A,0x03,0x00, ++0xFF,0x00,0x05,0x31, ++0x25,0x18,0x65,0x00, ++0xB7,0x00,0x43,0x10, ++0x24,0xE3,0x24,0x25, ++0xFF,0x00,0xE2,0x30, ++0xFF,0x00,0x03,0x31, ++0x00,0x12,0x02,0x00, ++0x25,0x10,0x43,0x00, ++0x32,0x3B,0xA2,0xA6, ++0x01,0x00,0xC4,0x90, ++0x00,0x00,0xC2,0x90, ++0x00,0x22,0x04,0x00, ++0x88,0x0C,0x00,0x0C, ++0x25,0x20,0x82,0x00, ++0x40,0x18,0x02,0x00, ++0x21,0x18,0x62,0x00, ++0x80,0x18,0x03,0x00, ++0x94,0xDE,0xE2,0x26, ++0x21,0x18,0x62,0x00, ++0x08,0x00,0x62,0x8C, ++0x00,0x00,0x00,0x00, ++0x09,0xF8,0x40,0x00, ++0x21,0x20,0x20,0x02, ++0x0C,0x00,0x82,0x8E, ++0x00,0x00,0x00,0x00, ++0x2B,0x10,0xC2,0x02, ++0x2C,0x00,0x40,0x10, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x42,0x8E, ++0x21,0x88,0x40,0x02, ++0x42,0x1B,0x02,0x00, ++0x78,0x00,0x63,0x30, ++0x02,0x26,0x02,0x00, ++0xFF,0x3F,0x42,0x30, ++0x21,0x10,0x43,0x00, ++0x03,0x00,0x84,0x30, ++0x21,0x10,0x44,0x00, ++0x18,0x00,0x42,0x24, ++0xFF,0xFF,0x50,0x30, ++0x7F,0x00,0x02,0x32, ++0x80,0x00,0x03,0x26, ++0x00,0x00,0x70,0xAE, ++0x02,0x00,0x40,0x10, ++0x80,0xFF,0x05,0x32, ++0x80,0xFF,0x65,0x30, ++0x00,0x00,0x65,0xAE, ++0x02,0x00,0x22,0x96, ++0x21,0x18,0xC5,0x02, ++0xFF,0xFF,0x76,0x30, ++0x0F,0x00,0x42,0x30, ++0x00,0x00,0x62,0xAE, ++0x00,0x00,0x23,0x8E, ++0x21,0x90,0x45,0x02, ++0x42,0x13,0x03,0x00, ++0x78,0x00,0x42,0x30, ++0x02,0x1E,0x03,0x00, ++0x21,0x10,0x51,0x00, ++0x03,0x00,0x63,0x30, ++0x21,0x10,0x43,0x00, ++0x18,0x00,0x46,0x24, ++0x00,0x00,0x66,0xAE, ++0x01,0x00,0xC2,0x90, ++0x00,0x00,0x00,0x00, ++0x00,0x12,0x02,0x00, ++0x00,0x08,0x42,0x30, ++0xB9,0xFF,0x40,0x14, ++0x02,0x80,0x09,0x3C, ++0x16,0x00,0xC8,0x90, ++0x17,0x00,0xC7,0x90, ++0xDD,0x1A,0x00,0x08, ++0xFF,0x00,0xE2,0x30, ++0x00,0x60,0x10,0x40, ++0x01,0x00,0x01,0x36, ++0x01,0x00,0x21,0x38, ++0x00,0x60,0x81,0x40, ++0x04,0x00,0x83,0x8E, ++0x00,0x00,0x82,0x8E, ++0x21,0x20,0x80,0x02, ++0x00,0x00,0x62,0xAC, ++0x04,0x00,0x43,0xAC, ++0x00,0x00,0x94,0xAE, ++0x3D,0x24,0x00,0x0C, ++0x04,0x00,0x94,0xAE, ++0x00,0x60,0x90,0x40, ++0x02,0x80,0x02,0x3C, ++0x64,0x57,0x43,0x8C, ++0x64,0x57,0x42,0x24, ++0x8B,0xFF,0x62,0x14, ++0x00,0x00,0x00,0x00, ++0x02,0x80,0x03,0x3C, ++0x40,0xEB,0x63,0x24, ++0x00,0x00,0x71,0x8C, ++0x25,0xB0,0x10,0x3C, ++0x04,0x01,0x02,0x36, ++0x00,0x00,0x43,0x8C, ++0xE8,0x37,0x27,0x8E, ++0x00,0x00,0x00,0x00, ++0xC8,0x00,0xE3,0x10, ++0xEC,0x37,0x23,0xAE, ++0x2B,0x10,0x67,0x00, ++0xD2,0x00,0x40,0x14, ++0x2B,0x10,0xE3,0x00, ++0x08,0x01,0x40,0x14, ++0x02,0x80,0x09,0x3C, ++0x30,0x1F,0x24,0x25, ++0xBC,0x37,0x83,0x94, ++0x02,0x80,0x02,0x3C, ++0x21,0x80,0x00,0x00, ++0x2F,0x00,0xC0,0x1A, ++0x25,0xA8,0x62,0x00, ++0x21,0x98,0x80,0x00, ++0x21,0x90,0x00,0x00, ++0x01,0x00,0x1E,0x24, ++0x21,0x88,0x55,0x02, ++0x00,0x00,0x22,0x8E, ++0x98,0x3E,0x63,0x8E, ++0xFF,0x3F,0x42,0x30, ++0x21,0x18,0x62,0x00, ++0x98,0x3E,0x63,0xAE, ++0x00,0x60,0x04,0x40, ++0x01,0x00,0x81,0x34, ++0x01,0x00,0x21,0x38, ++0x00,0x60,0x81,0x40, ++0xD4,0x1E,0x62,0x8E, ++0x00,0x00,0x00,0x00, ++0x01,0x00,0x42,0x24, ++0xD4,0x1E,0x62,0xAE, ++0x00,0x60,0x84,0x40, ++0x04,0x00,0x22,0x8E, ++0x02,0x00,0x03,0x24, ++0x02,0x17,0x02,0x00, ++0x03,0x00,0x42,0x30, ++0x39,0x00,0x43,0x10, ++0x02,0x80,0x03,0x3C, ++0x21,0x10,0x55,0x02, ++0x00,0x00,0x43,0x8C, ++0x00,0x00,0x00,0x00, ++0x08,0x00,0x60,0x10, ++0x01,0x00,0x02,0x26, ++0x04,0x00,0x22,0x8E, ++0x00,0xF0,0x03,0x3C, ++0x00,0x20,0x04,0x3C, ++0x24,0x10,0x43,0x00, ++0x10,0x00,0x44,0x10, ++0x02,0x80,0x09,0x3C, ++0x06,0x00,0x02,0x26, ++0x00,0x00,0x23,0x8E, ++0xFF,0xFF,0x50,0x30, ++0x82,0x16,0x03,0x00, ++0x01,0x00,0x42,0x30, ++0x52,0x00,0x5E,0x10, ++0x02,0x80,0x04,0x3C, ++0x80,0x90,0x10,0x00, ++0x2A,0x10,0x56,0x02, ++0xD7,0xFF,0x40,0x14, ++0x21,0x88,0x55,0x02, ++0x3D,0x24,0x00,0x0C, ++0x21,0x20,0x80,0x02, ++0x08,0x1C,0x00,0x08, ++0x02,0x80,0x02,0x3C, ++0x40,0xEB,0x29,0x25, ++0x00,0x00,0x25,0x8D, ++0x00,0x00,0x00,0x00, ++0xD4,0x1D,0xA2,0x8C, ++0x00,0x00,0x00,0x00, ++0x01,0x00,0x42,0x24, ++0xD4,0x1D,0xA2,0xAC, ++0x0C,0x00,0x24,0x8E, ++0x0C,0x00,0x02,0x24, ++0x3F,0x00,0x83,0x30, ++0xBD,0x00,0x62,0x10, ++0x00,0x00,0x00,0x00, ++0x0D,0x00,0x02,0x24, ++0xB3,0x00,0x62,0x10, ++0x00,0x00,0x00,0x00, ++0x3F,0x00,0x83,0x30, ++0x0E,0x00,0x02,0x24, ++0xE0,0xFF,0x62,0x14, ++0x06,0x00,0x02,0x26, ++0x02,0x80,0x03,0x3C, ++0x30,0x1F,0x63,0x24, ++0xE0,0x1D,0x62,0x8C, ++0x00,0x00,0x00,0x00, ++0x01,0x00,0x42,0x24, ++0x69,0x1B,0x00,0x08, ++0xE0,0x1D,0x62,0xAC, ++0x2F,0x55,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0xEF,0x1A,0x00,0x08, ++0x00,0x00,0x00,0x00, ++0xF4,0x5E,0x62,0x90, ++0x00,0x00,0x00,0x00, ++0xC6,0xFF,0x40,0x10, ++0x21,0x10,0x55,0x02, ++0x00,0x60,0x01,0x40, ++0x01,0x00,0x21,0x34, ++0x01,0x00,0x21,0x38, ++0x00,0x60,0x81,0x40, ++0xF4,0x5E,0x62,0x90, ++0x02,0x80,0x04,0x3C, ++0xF8,0xE8,0x85,0x24, ++0xFF,0x00,0x42,0x30, ++0x80,0x10,0x02,0x00, ++0x21,0x10,0x45,0x00, ++0x00,0x00,0x43,0x8C, ++0x00,0x00,0x24,0x8E, ++0x04,0x00,0x25,0x8E, ++0x09,0xF8,0x60,0x00, ++0x00,0x00,0x00,0x00, ++0x02,0x80,0x09,0x3C, ++0xF6,0x5E,0x22,0x91, ++0x0C,0x00,0x03,0x24, ++0xFF,0x00,0x42,0x30, ++0x06,0x00,0x43,0x10, ++0x02,0x80,0x03,0x3C, ++0x00,0x60,0x01,0x40, ++0x01,0x00,0x21,0x34, ++0x00,0x60,0x81,0x40, ++0x5F,0x1B,0x00,0x08, ++0x21,0x10,0x55,0x02, ++0x0D,0x5F,0x62,0x90, ++0x00,0x00,0x00,0x00, ++0xF8,0xFF,0x40,0x10, ++0x02,0x80,0x04,0x3C, ++0x13,0x5F,0x82,0x90, ++0x00,0x00,0x00,0x00, ++0x01,0x00,0x42,0x24, ++0x13,0x5F,0x82,0xA0, ++0x00,0x60,0x01,0x40, ++0x01,0x00,0x21,0x34, ++0x00,0x60,0x81,0x40, ++0x5F,0x1B,0x00,0x08, ++0x21,0x10,0x55,0x02, ++0x30,0x1F,0x82,0x8C, ++0x00,0x00,0x00,0x00, ++0x02,0x12,0x02,0x00, ++0x0F,0x00,0x42,0x30, ++0x05,0x00,0x5E,0x10, ++0xC2,0x13,0x03,0x00, ++0x1E,0x00,0x42,0x30, ++0x21,0x10,0x50,0x00, ++0x70,0x1B,0x00,0x08, ++0xFF,0xFF,0x50,0x30, ++0x02,0x00,0x62,0x92, ++0x00,0x00,0x00,0x00, ++0x1C,0x00,0x40,0x14, ++0x00,0x00,0x00,0x00, ++0x04,0x00,0x23,0x8E, ++0x00,0x00,0x00,0x00, ++0x02,0x14,0x03,0x00, ++0x0F,0x00,0x42,0x30, ++0x14,0x00,0x40,0x14, ++0x02,0x17,0x03,0x00, ++0x03,0x00,0x44,0x30, ++0x08,0x00,0x80,0x10, ++0x00,0xC0,0x02,0x3C, ++0x24,0x10,0x62,0x00, ++0x0E,0x00,0x40,0x14, ++0x03,0x00,0x02,0x24, ++0x0C,0x00,0x82,0x10, ++0x00,0x00,0x00,0x00, ++0x0A,0x00,0x80,0x10, ++0x00,0x00,0x00,0x00, ++0x80,0x28,0x10,0x00, ++0x21,0x28,0xB5,0x00, ++0xF7,0x19,0x00,0x0C, ++0x21,0x20,0x20,0x02, ++0x4C,0x1A,0x00,0x0C, ++0x21,0x20,0x40,0x00, ++0x21,0x20,0x40,0x00, ++0x56,0x1A,0x00,0x0C, ++0x21,0x28,0x00,0x00, ++0x02,0x00,0x62,0x92, ++0x00,0x00,0x00,0x00, ++0x8B,0x00,0x5E,0x10, ++0x00,0x00,0x00,0x00, ++0x02,0x00,0x63,0x92, ++0x02,0x00,0x02,0x24, ++0x71,0x00,0x62,0x10, ++0x00,0x00,0x00,0x00, ++0x25,0xB0,0x02,0x3C, ++0x4C,0x00,0x42,0x34, ++0x00,0x00,0x43,0x90, ++0x00,0x00,0x00,0x00, ++0x03,0x00,0x63,0x30, ++0x08,0x00,0x7E,0x10, ++0xD0,0x02,0x02,0x24, ++0x00,0x00,0x23,0x8E, ++0x00,0x00,0x00,0x00, ++0xC2,0x13,0x03,0x00, ++0x1E,0x00,0x42,0x30, ++0x21,0x10,0x50,0x00, ++0x70,0x1B,0x00,0x08, ++0xFF,0xFF,0x50,0x30, ++0x80,0x36,0x62,0xAE, ++0x00,0x00,0x23,0x8E, ++0xFA,0x1B,0x00,0x08, ++0xC2,0x13,0x03,0x00, ++0x02,0x80,0x09,0x3C, ++0x00,0x01,0x02,0x36, ++0x30,0x1F,0x29,0x25, ++0x00,0x00,0x47,0xAC, ++0xE8,0x37,0x27,0xAD, ++0x02,0x80,0x02,0x3C, ++0x08,0x04,0x44,0x24, ++0x21,0x28,0x00,0x00, ++0x21,0x30,0x00,0x00, ++0x91,0x3C,0x00,0x0C, ++0x21,0x38,0x00,0x00, ++0xAA,0x1A,0x00,0x08, ++0x02,0x80,0x02,0x3C, ++0xF0,0x37,0x22,0x8E, ++0xFF,0xFF,0x73,0x30, ++0x23,0x10,0x47,0x00, ++0xFF,0xFF,0x52,0x30, ++0x21,0x18,0x53,0x02, ++0xFF,0xFF,0x76,0x30, ++0x25,0x24,0x00,0x0C, ++0x21,0x20,0xC0,0x02, ++0xEF,0xFF,0x40,0x10, ++0x21,0xA0,0x40,0x00, ++0x08,0x00,0x42,0x8C, ++0xE8,0x37,0x26,0x8E, ++0x21,0x38,0x40,0x02, ++0x21,0x18,0x56,0x00, ++0xB8,0x37,0x23,0xAE, ++0x21,0x28,0x40,0x00, ++0x08,0x00,0x04,0x24, ++0xBC,0x37,0x22,0xAE, ++0x73,0x01,0x00,0x0C, ++0x10,0x00,0xA0,0xAF, ++0xB0,0x01,0x00,0x0C, ++0x08,0x00,0x04,0x24, ++0xBC,0x37,0x25,0x8E, ++0x24,0x10,0x02,0x3C, ++0x00,0x01,0x10,0x36, ++0x00,0x00,0x02,0xAE, ++0x21,0x38,0x60,0x02, ++0x21,0x28,0xB2,0x00, ++0x08,0x00,0x04,0x24, ++0x24,0x10,0x06,0x3C, ++0xE8,0x37,0x22,0xAE, ++0x73,0x01,0x00,0x0C, ++0x10,0x00,0xA0,0xAF, ++0xEC,0x37,0x23,0x8E, ++0x08,0x00,0x04,0x24, ++0xB0,0x01,0x00,0x0C, ++0xE8,0x37,0x23,0xAE, ++0xE8,0x37,0x22,0x8E, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x02,0xAE, ++0x40,0x1B,0x00,0x08, ++0x02,0x80,0x09,0x3C, ++0xDC,0x1D,0xA2,0x8C, ++0x00,0x00,0x00,0x00, ++0x01,0x00,0x42,0x24, ++0xDC,0x1D,0xA2,0xAC, ++0x0C,0x00,0x24,0x8E, ++0x88,0x1B,0x00,0x08, ++0x3F,0x00,0x83,0x30, ++0xD8,0x1D,0xA2,0x8C, ++0x00,0x00,0x00,0x00, ++0x01,0x00,0x42,0x24, ++0xD8,0x1D,0xA2,0xAC, ++0x0C,0x00,0x24,0x8E, ++0x84,0x1B,0x00,0x08, ++0x3F,0x00,0x83,0x30, ++0x23,0x10,0x67,0x00, ++0xFF,0xFF,0x56,0x30, ++0x25,0x24,0x00,0x0C, ++0x21,0x20,0xC0,0x02, ++0x4A,0x00,0x40,0x10, ++0x21,0xA0,0x40,0x00, ++0x08,0x00,0x42,0x8C, ++0xE8,0x37,0x26,0x8E, ++0x08,0x00,0x04,0x24, ++0x21,0x18,0x56,0x00, ++0xB8,0x37,0x23,0xAE, ++0x21,0x28,0x40,0x00, ++0x21,0x38,0xC0,0x02, ++0xBC,0x37,0x22,0xAE, ++0x73,0x01,0x00,0x0C, ++0x10,0x00,0xA0,0xAF, ++0xEC,0x37,0x23,0x8E, ++0x08,0x00,0x04,0x24, ++0xB0,0x01,0x00,0x0C, ++0xE8,0x37,0x23,0xAE, ++0xE8,0x37,0x23,0x8E, ++0x00,0x01,0x02,0x36, ++0x00,0x00,0x43,0xAC, ++0x40,0x1B,0x00,0x08, ++0x02,0x80,0x09,0x3C, ++0x04,0x00,0x23,0x8E, ++0x00,0x00,0x00,0x00, ++0x02,0x14,0x03,0x00, ++0x0F,0x00,0x42,0x30, ++0x08,0x00,0x42,0x28, ++0x8B,0xFF,0x40,0x10, ++0x25,0xB0,0x02,0x3C, ++0x02,0x17,0x03,0x00, ++0x03,0x00,0x42,0x30, ++0x86,0xFF,0x40,0x14, ++0x00,0x00,0x00,0x00, ++0x80,0x28,0x10,0x00, ++0x21,0x28,0xB5,0x00, ++0xF7,0x19,0x00,0x0C, ++0x21,0x20,0x20,0x02, ++0x4C,0x1A,0x00,0x0C, ++0x21,0x20,0x40,0x00, ++0x21,0x20,0x40,0x00, ++0x56,0x1A,0x00,0x0C, ++0x21,0x28,0x00,0x00, ++0xF1,0x1B,0x00,0x08, ++0x25,0xB0,0x02,0x3C, ++0x04,0x00,0x23,0x8E, ++0x00,0x00,0x00,0x00, ++0x02,0x14,0x03,0x00, ++0x0F,0x00,0x42,0x30, ++0x08,0x00,0x42,0x28, ++0x06,0x00,0x40,0x10, ++0x00,0xC0,0x02,0x3C, ++0x02,0x17,0x03,0x00, ++0x03,0x00,0x42,0x30, ++0x0C,0x00,0x40,0x10, ++0x80,0x28,0x10,0x00, ++0x00,0xC0,0x02,0x3C, ++0x24,0x10,0x62,0x00, ++0x68,0xFF,0x40,0x14, ++0x02,0x17,0x03,0x00, ++0x03,0x00,0x42,0x30, ++0x03,0x00,0x03,0x24, ++0x64,0xFF,0x43,0x10, ++0x00,0x00,0x00,0x00, ++0x62,0xFF,0x40,0x10, ++0x00,0x00,0x00,0x00, ++0x80,0x28,0x10,0x00, ++0x21,0x28,0xB5,0x00, ++0xF7,0x19,0x00,0x0C, ++0x21,0x20,0x20,0x02, ++0x4C,0x1A,0x00,0x0C, ++0x21,0x20,0x40,0x00, ++0x21,0x20,0x40,0x00, ++0x56,0x1A,0x00,0x0C, ++0x21,0x28,0x00,0x00, ++0xEC,0x1B,0x00,0x08, ++0x00,0x00,0x00,0x00, ++0xEC,0x37,0x23,0x8E, ++0x00,0x01,0x02,0x36, ++0x00,0x00,0x43,0xAC, ++0x07,0x1C,0x00,0x08, ++0xE8,0x37,0x23,0xAE, ++0xB8,0xFF,0xBD,0x27, ++0x25,0xB0,0x03,0x3C, ++0x44,0x00,0xBF,0xAF, ++0x40,0x00,0xBE,0xAF, ++0x3C,0x00,0xB7,0xAF, ++0x38,0x00,0xB6,0xAF, ++0x34,0x00,0xB5,0xAF, ++0x30,0x00,0xB4,0xAF, ++0x2C,0x00,0xB3,0xAF, ++0x28,0x00,0xB2,0xAF, ++0x24,0x00,0xB1,0xAF, ++0x20,0x00,0xB0,0xAF, ++0x44,0x00,0x63,0x34, ++0x00,0x00,0x62,0x90, ++0x00,0x00,0x00,0x00, ++0x00,0x16,0x02,0x00, ++0x03,0x16,0x02,0x00, ++0x0E,0x00,0x40,0x04, ++0x18,0x00,0xA0,0xAF, ++0x21,0x20,0x60,0x00, ++0x21,0x10,0x00,0x00, ++0x01,0x00,0x42,0x24, ++0xFF,0xFF,0x42,0x30, ++0x64,0x00,0x43,0x2C, ++0xFD,0xFF,0x60,0x14, ++0x01,0x00,0x42,0x24, ++0x00,0x00,0x82,0x90, ++0x00,0x00,0x00,0x00, ++0x00,0x16,0x02,0x00, ++0x03,0x16,0x02,0x00, ++0xF6,0xFF,0x41,0x04, ++0x21,0x10,0x00,0x00, ++0x02,0x80,0x02,0x3C, ++0x74,0x57,0x43,0x8C, ++0x00,0x80,0x06,0x3C, ++0x6C,0x72,0xC2,0x24, ++0x25,0xB0,0x05,0x3C, ++0x02,0x80,0x06,0x3C, ++0x18,0x03,0xA4,0x34, ++0x74,0x57,0xD2,0x24, ++0x00,0x00,0x82,0xAC, ++0x67,0x00,0x72,0x10, ++0x01,0x00,0x16,0x24, ++0x11,0x11,0x02,0x3C, ++0x2A,0xB0,0x03,0x3C, ++0x22,0x22,0x5E,0x34, ++0x02,0x80,0x02,0x3C, ++0x21,0xB8,0x80,0x00, ++0x05,0x00,0x74,0x34, ++0x30,0x1F,0x55,0x24, ++0x01,0x00,0x13,0x24, ++0x00,0x00,0xFE,0xAE, ++0x21,0x00,0xC0,0x12, ++0x2A,0xB0,0x03,0x3C, ++0x02,0x80,0x03,0x3C, ++0xF4,0x5E,0x62,0x90, ++0x00,0x00,0x00,0x00, ++0x1B,0x00,0x40,0x10, ++0x21,0xB0,0x00,0x00, ++0x01,0x00,0x06,0x24, ++0x18,0x00,0xA6,0xAF, ++0x00,0x60,0x01,0x40, ++0x01,0x00,0x21,0x34, ++0x01,0x00,0x21,0x38, ++0x00,0x60,0x81,0x40, ++0x02,0x80,0x03,0x3C, ++0xF6,0x5E,0x62,0x90, ++0x00,0x00,0x00,0x00, ++0x0F,0x00,0x42,0x30, ++0x04,0x00,0x42,0x28, ++0x5F,0x00,0x40,0x14, ++0x04,0x00,0x04,0x24, ++0x02,0x80,0x06,0x3C, ++0xDE,0x5D,0xC2,0x90, ++0x00,0x00,0x00,0x00, ++0x02,0x00,0x42,0x30, ++0x55,0x00,0x40,0x14, ++0x00,0x00,0x00,0x00, ++0x00,0x08,0x04,0x24, ++0x00,0x02,0x05,0x3C, ++0xA9,0x45,0x00,0x0C, ++0x01,0x00,0x06,0x24, ++0x00,0x60,0x01,0x40, ++0x01,0x00,0x21,0x34, ++0x00,0x60,0x81,0x40, ++0x2A,0xB0,0x03,0x3C, ++0x06,0x00,0x63,0x34, ++0x00,0x00,0x62,0x94, ++0x44,0x38,0xB1,0x8E, ++0x25,0xB0,0x06,0x3C, ++0xB0,0x03,0xC6,0x34, ++0x00,0xFF,0x42,0x30, ++0x00,0x00,0xD1,0xAC, ++0x0F,0x00,0x40,0x18, ++0x02,0x80,0x02,0x3C, ++0x02,0x80,0x03,0x3C, ++0x4C,0xEB,0x42,0x24, ++0x50,0xEB,0x63,0x24, ++0x00,0x00,0x45,0x8C, ++0x00,0x00,0x64,0x8C, ++0x02,0x80,0x06,0x3C, ++0x54,0xEB,0xC6,0x24, ++0x00,0x00,0xC3,0x8C, ++0x00,0x00,0xA4,0xAC, ++0x00,0x00,0x62,0x94, ++0x00,0x00,0x00,0x00, ++0x00,0xFF,0x42,0x30, ++0xFB,0xFF,0x40,0x1C, ++0x00,0x00,0x00,0x00, ++0x0C,0x00,0x23,0x8E, ++0x00,0x00,0x00,0x00, ++0x07,0x00,0x62,0x30, ++0x47,0x00,0x40,0x14, ++0x08,0x00,0x62,0x24, ++0xC2,0x10,0x03,0x00, ++0x08,0x00,0x25,0x8E, ++0x04,0x37,0xA6,0x8E, ++0xC0,0x10,0x02,0x00, ++0x20,0x00,0x42,0x24, ++0xFF,0xFF,0x47,0x30, ++0x01,0x00,0x04,0x24, ++0x73,0x01,0x00,0x0C, ++0x10,0x00,0xB3,0xAF, ++0xB0,0x01,0x00,0x0C, ++0x01,0x00,0x04,0x24, ++0x02,0x00,0x02,0x24, ++0x00,0x00,0x93,0xA2, ++0x00,0x00,0x82,0xA2, ++0x00,0x60,0x10,0x40, ++0x01,0x00,0x01,0x36, ++0x01,0x00,0x21,0x38, ++0x00,0x60,0x81,0x40, ++0x04,0x00,0x23,0x8E, ++0x00,0x00,0x22,0x8E, ++0x21,0x20,0x20,0x02, ++0x00,0x00,0x62,0xAC, ++0x04,0x00,0x43,0xAC, ++0x00,0x00,0x31,0xAE, ++0x3D,0x24,0x00,0x0C, ++0x04,0x00,0x31,0xAE, ++0x00,0x60,0x90,0x40, ++0x00,0x00,0x42,0x8E, ++0x00,0x00,0x00,0x00, ++0xA3,0xFF,0x52,0x14, ++0x00,0x00,0x00,0x00, ++0x18,0x00,0xA2,0x8F, ++0x00,0x00,0x00,0x00, ++0x07,0x00,0x40,0x10, ++0x02,0x80,0x02,0x3C, ++0x02,0x80,0x03,0x3C, ++0xF4,0x5E,0x62,0x90, ++0x00,0x00,0x00,0x00, ++0x11,0x00,0x40,0x14, ++0x18,0x00,0xA0,0xAF, ++0x02,0x80,0x02,0x3C, ++0x08,0x08,0x44,0x24, ++0x21,0x28,0x00,0x00, ++0x21,0x30,0x00,0x00, ++0x91,0x3C,0x00,0x0C, ++0x21,0x38,0x00,0x00, ++0xBC,0x1C,0x00,0x08, ++0x02,0x80,0x02,0x3C, ++0x9B,0x30,0x00,0x0C, ++0x01,0x00,0x04,0x24, ++0xEA,0x1C,0x00,0x08, ++0x00,0x08,0x04,0x24, ++0x64,0x31,0x00,0x0C, ++0x01,0x00,0x05,0x24, ++0xE4,0x1C,0x00,0x08, ++0x02,0x80,0x06,0x3C, ++0x00,0x60,0x01,0x40, ++0x01,0x00,0x21,0x34, ++0x01,0x00,0x21,0x38, ++0x00,0x60,0x81,0x40, ++0x02,0x80,0x06,0x3C, ++0xF5,0x5E,0xC4,0x90, ++0x01,0x00,0x05,0x24, ++0x64,0x31,0x00,0x0C, ++0xFF,0x00,0x84,0x30, ++0x00,0x60,0x01,0x40, ++0x01,0x00,0x21,0x34, ++0x00,0x60,0x81,0x40, ++0x36,0x1D,0x00,0x08, ++0x02,0x80,0x02,0x3C, ++0x0E,0x1D,0x00,0x08, ++0xC2,0x10,0x02,0x00, ++0x10,0x00,0xE0,0x18, ++0x21,0x18,0x00,0x00, ++0x00,0x00,0xC0,0xAC, ++0x21,0x40,0x00,0x00, ++0x00,0x00,0x82,0x90, ++0x00,0x00,0x00,0x00, ++0x0C,0x00,0x45,0x10, ++0x21,0x18,0x80,0x00, ++0x01,0x00,0x82,0x90, ++0x00,0x00,0x00,0x00, ++0x21,0x18,0x48,0x00, ++0x02,0x00,0x68,0x24, ++0x21,0x10,0x82,0x00, ++0x2B,0x18,0x07,0x01, ++0xF5,0xFF,0x60,0x14, ++0x02,0x00,0x44,0x24, ++0x21,0x18,0x00,0x00, ++0x08,0x00,0xE0,0x03, ++0x21,0x10,0x60,0x00, ++0x01,0x00,0x82,0x90, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0xC2,0xAC, ++0x08,0x00,0xE0,0x03, ++0x21,0x10,0x60,0x00, ++0x02,0x80,0x07,0x3C, ++0x30,0x1F,0xE5,0x24, ++0x22,0x3E,0xA3,0x90, ++0xFF,0x00,0x84,0x30, ++0x80,0x10,0x04,0x00, ++0x0C,0x00,0x60,0x14, ++0x21,0x30,0x45,0x00, ++0xC8,0x00,0x02,0x24, ++0x24,0x39,0xA2,0xAC, ++0x01,0x00,0x03,0x24, ++0x30,0x1F,0xE2,0x24, ++0x04,0x18,0x83,0x00, ++0x4C,0x3E,0xA4,0xA0, ++0x22,0x3E,0x44,0x90, ++0x00,0x00,0x00,0x00, ++0x25,0x18,0x64,0x00, ++0x08,0x00,0xE0,0x03, ++0x22,0x3E,0x43,0xA0, ++0x24,0x39,0xA3,0x8C, ++0xC8,0x00,0x02,0x24, ++0x23,0x10,0x43,0x00, ++0x24,0x3E,0xC2,0xAC, ++0x01,0x00,0x03,0x24, ++0x30,0x1F,0xE2,0x24, ++0x04,0x18,0x83,0x00, ++0x22,0x3E,0x44,0x90, ++0x00,0x00,0x00,0x00, ++0x25,0x18,0x64,0x00, ++0x08,0x00,0xE0,0x03, ++0x22,0x3E,0x43,0xA0, ++0xE0,0xFF,0xBD,0x27, ++0x14,0x00,0xB1,0xAF, ++0x02,0x80,0x11,0x3C, ++0x10,0x00,0xB0,0xAF, ++0x18,0x00,0xBF,0xAF, ++0x30,0x1F,0x25,0x26, ++0x4C,0x3E,0xA6,0x90, ++0x01,0x00,0x02,0x24, ++0x04,0x10,0xC2,0x00, ++0x06,0x00,0x40,0x14, ++0xC9,0x00,0x10,0x24, ++0x1A,0x3E,0xA2,0x90, ++0x00,0x00,0x00,0x00, ++0x01,0x00,0x42,0x30, ++0x23,0x00,0x40,0x14, ++0x21,0x20,0xC5,0x00, ++0x02,0x80,0x02,0x3C, ++0x30,0x1F,0x46,0x24, ++0x21,0x20,0x00,0x00, ++0x24,0x3E,0xC5,0x24, ++0x00,0x00,0xA2,0x8C, ++0x04,0x00,0xA5,0x24, ++0x05,0x00,0x40,0x10, ++0x2B,0x18,0x50,0x00, ++0x03,0x00,0x60,0x10, ++0x00,0x00,0x00,0x00, ++0x21,0x80,0x40,0x00, ++0x4C,0x3E,0xC4,0xA0, ++0x01,0x00,0x84,0x24, ++0x08,0x00,0x82,0x2C, ++0xF5,0xFF,0x40,0x14, ++0xC9,0x00,0x02,0x24, ++0x21,0x00,0x02,0x12, ++0x02,0x80,0x02,0x3C, ++0x30,0x1F,0x45,0x24, ++0x07,0x00,0x04,0x24, ++0x24,0x3E,0xA2,0x8C, ++0xFF,0xFF,0x84,0x24, ++0x02,0x00,0x40,0x10, ++0x23,0x18,0x50,0x00, ++0x24,0x3E,0xA3,0xAC, ++0xFA,0xFF,0x81,0x04, ++0x04,0x00,0xA5,0x24, ++0x30,0x1F,0x22,0x26, ++0x24,0x39,0x50,0xAC, ++0x18,0x00,0xBF,0x8F, ++0x14,0x00,0xB1,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x08,0x00,0xE0,0x03, ++0x20,0x00,0xBD,0x27, ++0x44,0x3E,0x83,0x90, ++0x00,0x00,0x00,0x00, ++0x01,0x00,0x63,0x24, ++0xFF,0x00,0x62,0x30, ++0x03,0x00,0x42,0x2C, ++0xD8,0xFF,0x40,0x10, ++0x44,0x3E,0x83,0xA0, ++0x80,0x18,0x06,0x00, ++0x21,0x18,0x65,0x00, ++0xC8,0x00,0x02,0x24, ++0x03,0x00,0x04,0x24, ++0x21,0x28,0x00,0x00, ++0x90,0x14,0x00,0x0C, ++0x24,0x3E,0x62,0xAC, ++0x9C,0x1D,0x00,0x08, ++0x02,0x80,0x02,0x3C, ++0x30,0x1F,0x22,0x26, ++0x18,0x00,0xBF,0x8F, ++0x14,0x00,0xB1,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x20,0x00,0xBD,0x27, ++0x22,0x3E,0x40,0xA0, ++0x08,0x00,0xE0,0x03, ++0x24,0x39,0x40,0xAC, ++0xB8,0xFF,0xBD,0x27, ++0x02,0x80,0x08,0x3C, ++0x02,0x80,0x0B,0x3C, ++0x02,0x80,0x0C,0x3C, ++0x40,0x00,0xBF,0xAF, ++0x3C,0x00,0xB5,0xAF, ++0x38,0x00,0xB4,0xAF, ++0x34,0x00,0xB3,0xAF, ++0x30,0x00,0xB2,0xAF, ++0x2C,0x00,0xB1,0xAF, ++0x28,0x00,0xB0,0xAF, ++0x40,0xED,0x63,0x25, ++0x3C,0xED,0x02,0x25, ++0x44,0xED,0x84,0x25, ++0x01,0x00,0x45,0x90, ++0x01,0x00,0x66,0x90, ++0x01,0x00,0x87,0x90, ++0x3C,0xED,0x0F,0x91, ++0x02,0x00,0x4A,0x90, ++0x40,0xED,0x6E,0x91, ++0x02,0x00,0x69,0x90, ++0x44,0xED,0x8D,0x91, ++0x02,0x00,0x88,0x90, ++0x03,0x00,0x4B,0x90, ++0x03,0x00,0x6C,0x90, ++0x03,0x00,0x82,0x90, ++0x00,0x2A,0x05,0x00, ++0x00,0x32,0x06,0x00, ++0x00,0x3A,0x07,0x00, ++0x25,0x28,0xAF,0x00, ++0x25,0x30,0xCE,0x00, ++0x25,0x38,0xED,0x00, ++0x00,0x54,0x0A,0x00, ++0x00,0x4C,0x09,0x00, ++0x00,0x44,0x08,0x00, ++0x25,0x50,0x45,0x01, ++0x25,0x48,0x26,0x01, ++0x25,0x40,0x07,0x01, ++0x00,0x5E,0x0B,0x00, ++0x00,0x66,0x0C,0x00, ++0x00,0x16,0x02,0x00, ++0x02,0x80,0x04,0x3C, ++0x25,0x58,0x6A,0x01, ++0x25,0x60,0x89,0x01, ++0x25,0x10,0x48,0x00, ++0x84,0x58,0x84,0x24, ++0x10,0x00,0xAB,0xAF, ++0x18,0x00,0xAC,0xAF, ++0x34,0x4F,0x00,0x0C, ++0x20,0x00,0xA2,0xAF, ++0x10,0x00,0x42,0x30, ++0x29,0x00,0x40,0x10, ++0x21,0x18,0x00,0x00, ++0x02,0x80,0x13,0x3C, ++0x30,0x1F,0x63,0x26, ++0xC4,0x39,0x62,0x8C, ++0x0C,0x00,0x10,0x24, ++0x2B,0x10,0x02,0x02, ++0x2C,0x00,0x40,0x10, ++0x02,0x80,0x02,0x3C, ++0x02,0x80,0x03,0x3C, ++0xF8,0x58,0x51,0x24, ++0x02,0x59,0x72,0x24, ++0x02,0x80,0x02,0x3C, ++0x02,0x80,0x03,0x3C, ++0xFA,0x58,0x54,0x24, ++0x26,0x1E,0x00,0x08, ++0x06,0x59,0x75,0x24, ++0xDD,0x00,0x02,0x24, ++0x21,0x20,0x14,0x02, ++0x2B,0x00,0x62,0x10, ++0x10,0x00,0xA5,0x27, ++0x21,0x10,0x11,0x02, ++0x01,0x00,0x43,0x90, ++0x30,0x1F,0x64,0x26, ++0xC4,0x39,0x82,0x8C, ++0x21,0x18,0x70,0x00, ++0x02,0x00,0x70,0x24, ++0x2B,0x10,0x02,0x02, ++0x17,0x00,0x40,0x10, ++0x00,0x00,0x00,0x00, ++0x21,0x10,0x11,0x02, ++0x00,0x00,0x43,0x90, ++0x30,0x00,0x02,0x24, ++0x21,0x20,0x12,0x02, ++0x20,0x00,0xA5,0x27, ++0xED,0xFF,0x62,0x14, ++0x04,0x00,0x06,0x24, ++0x39,0x52,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0xEE,0xFF,0x40,0x14, ++0x21,0x10,0x11,0x02, ++0x01,0x00,0x03,0x24, ++0x40,0x00,0xBF,0x8F, ++0x3C,0x00,0xB5,0x8F, ++0x38,0x00,0xB4,0x8F, ++0x34,0x00,0xB3,0x8F, ++0x30,0x00,0xB2,0x8F, ++0x2C,0x00,0xB1,0x8F, ++0x28,0x00,0xB0,0x8F, ++0x21,0x10,0x60,0x00, ++0x08,0x00,0xE0,0x03, ++0x48,0x00,0xBD,0x27, ++0x40,0x00,0xBF,0x8F, ++0x3C,0x00,0xB5,0x8F, ++0x38,0x00,0xB4,0x8F, ++0x34,0x00,0xB3,0x8F, ++0x30,0x00,0xB2,0x8F, ++0x2C,0x00,0xB1,0x8F, ++0x28,0x00,0xB0,0x8F, ++0x21,0x18,0x00,0x00, ++0x21,0x10,0x60,0x00, ++0x08,0x00,0xE0,0x03, ++0x48,0x00,0xBD,0x27, ++0x39,0x52,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x21,0x20,0x15,0x02, ++0x18,0x00,0xA5,0x27, ++0xD1,0xFF,0x40,0x14, ++0x04,0x00,0x06,0x24, ++0x39,0x52,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0xCE,0xFF,0x40,0x14, ++0x21,0x10,0x11,0x02, ++0x32,0x1E,0x00,0x08, ++0x01,0x00,0x03,0x24, ++0x02,0x80,0x02,0x3C, ++0x38,0x5D,0x43,0x94, ++0x00,0x00,0x00,0x00, ++0x80,0x18,0x03,0x00, ++0xB8,0x0B,0x62,0x28, ++0x04,0x00,0x40,0x14, ++0xB8,0x0B,0x04,0x24, ++0x21,0x4E,0x62,0x28, ++0x20,0x4E,0x04,0x24, ++0x0B,0x20,0x62,0x00, ++0x08,0x00,0xE0,0x03, ++0x21,0x10,0x80,0x00, ++0x21,0x38,0x80,0x00, ++0x08,0x00,0xC0,0x10, ++0xFF,0xFF,0xC3,0x24, ++0xFF,0xFF,0x06,0x24, ++0x00,0x00,0xA2,0x8C, ++0xFF,0xFF,0x63,0x24, ++0x04,0x00,0xA5,0x24, ++0x00,0x00,0xE2,0xAC, ++0xFB,0xFF,0x66,0x14, ++0x04,0x00,0xE7,0x24, ++0x08,0x00,0xE0,0x03, ++0x21,0x10,0x80,0x00, ++0x25,0xB0,0x03,0x3C, ++0xD8,0xFF,0xBD,0x27, ++0x20,0x00,0xBF,0xAF, ++0x1C,0x00,0xB1,0xAF, ++0x18,0x00,0xB0,0xAF, ++0x94,0x0E,0x65,0x34, ++0x9C,0x0E,0x66,0x34, ++0xA4,0x0E,0x67,0x34, ++0xAC,0x0E,0x68,0x34, ++0x02,0x80,0x02,0x3C, ++0x00,0x00,0xA9,0x8C, ++0x30,0x1F,0x58,0x24, ++0x00,0x00,0xCC,0x8C, ++0x00,0x00,0xF1,0x8C, ++0x00,0x00,0x05,0x8D, ++0x0C,0x00,0x07,0x8F, ++0x10,0x00,0x08,0x8F, ++0xFF,0x03,0x0A,0x3C, ++0xB4,0x0E,0x62,0x34, ++0x00,0x00,0x4B,0x8C, ++0x24,0x48,0x2A,0x01, ++0x00,0xFC,0x02,0x24, ++0x24,0x28,0xAA,0x00, ++0xBC,0x0E,0x66,0x34, ++0x24,0x40,0x02,0x01, ++0x02,0x4C,0x09,0x00, ++0x24,0x38,0xE2,0x00, ++0x02,0x2C,0x05,0x00, ++0xF0,0xFF,0x02,0x3C, ++0x00,0x00,0xD0,0x8C, ++0xFF,0x03,0x42,0x34, ++0xCC,0x0E,0x66,0x34, ++0x25,0x38,0xE9,0x00, ++0xC4,0x0E,0x63,0x34, ++0x25,0x40,0x05,0x01, ++0x08,0x00,0x0D,0x8F, ++0x00,0x00,0x6F,0x8C, ++0x24,0x40,0x02,0x01, ++0x00,0x00,0xCE,0x8C, ++0x24,0x38,0xE2,0x00, ++0x24,0x60,0x8A,0x01, ++0x24,0x58,0x6A,0x01, ++0xFF,0x9F,0x02,0x3C, ++0x82,0x61,0x0C,0x00, ++0x82,0x59,0x0B,0x00, ++0xFF,0xFF,0x42,0x34, ++0x0F,0xC0,0x05,0x3C, ++0xFF,0xFF,0xA5,0x34, ++0x25,0x38,0xEC,0x00, ++0x25,0x40,0x0B,0x01, ++0x24,0x68,0xA2,0x01, ++0xFF,0x00,0x0B,0x3C, ++0x00,0xFF,0x82,0x30, ++0x24,0x88,0x2A,0x02, ++0x24,0x80,0x0A,0x02, ++0x24,0x18,0x8B,0x00, ++0x24,0x40,0x05,0x01, ++0x21,0x48,0x80,0x00, ++0x02,0x62,0x02,0x00, ++0x24,0x38,0xE5,0x00, ++0x00,0x20,0x02,0x3C, ++0x24,0x70,0xCA,0x01, ++0x00,0x89,0x11,0x00, ++0x00,0x81,0x10,0x00, ++0x24,0x78,0xEA,0x01, ++0x00,0xFF,0x6B,0x35, ++0x25,0x68,0xA2,0x01, ++0x02,0x1C,0x03,0x00, ++0x02,0x80,0x04,0x3C, ++0x25,0x38,0xF1,0x00, ++0x25,0x40,0x10,0x01, ++0x02,0x7C,0x0F,0x00, ++0x02,0x74,0x0E,0x00, ++0x24,0x48,0x2B,0x01, ++0xDC,0xE3,0x84,0x24, ++0x21,0x28,0x80,0x01, ++0x21,0x30,0x60,0x00, ++0x12,0x00,0x02,0x24, ++0x08,0x00,0x0D,0xAF, ++0x0C,0x00,0x07,0xAF, ++0x10,0x00,0x08,0xAF, ++0x14,0x00,0x0F,0xA7, ++0x0A,0x00,0x20,0x15, ++0x16,0x00,0x0E,0xA7, ++0x10,0x00,0xA4,0x27, ++0xC7,0x02,0x02,0xA3, ++0xC8,0x5C,0x00,0x0C, ++0xC3,0x02,0x02,0xA3, ++0x20,0x00,0xBF,0x8F, ++0x1C,0x00,0xB1,0x8F, ++0x18,0x00,0xB0,0x8F, ++0x08,0x00,0xE0,0x03, ++0x28,0x00,0xBD,0x27, ++0xC7,0x02,0x03,0xA3, ++0x2F,0x55,0x00,0x0C, ++0xC3,0x02,0x0C,0xA3, ++0xC8,0x5C,0x00,0x0C, ++0x10,0x00,0xA4,0x27, ++0x20,0x00,0xBF,0x8F, ++0x1C,0x00,0xB1,0x8F, ++0x18,0x00,0xB0,0x8F, ++0x08,0x00,0xE0,0x03, ++0x28,0x00,0xBD,0x27, ++0xC8,0xFF,0xBD,0x27, ++0x28,0x00,0xB6,0xAF, ++0x25,0xB0,0x02,0x3C, ++0x00,0x80,0x16,0x3C, ++0x48,0x7B,0xC3,0x26, ++0x18,0x03,0x42,0x34, ++0x30,0x00,0xBE,0xAF, ++0x2C,0x00,0xB7,0xAF, ++0x24,0x00,0xB5,0xAF, ++0x20,0x00,0xB4,0xAF, ++0x1C,0x00,0xB3,0xAF, ++0x34,0x00,0xBF,0xAF, ++0x18,0x00,0xB2,0xAF, ++0x14,0x00,0xB1,0xAF, ++0x10,0x00,0xB0,0xAF, ++0x00,0x00,0x43,0xAC, ++0x21,0x98,0x00,0x00, ++0x02,0x80,0x15,0x3C, ++0x00,0x80,0x1E,0x3C, ++0x02,0x80,0x14,0x3C, ++0x02,0x80,0x17,0x3C, ++0x25,0xB0,0x10,0x3C, ++0x18,0x03,0x02,0x36, ++0x48,0x7B,0xC3,0x26, ++0x00,0x00,0x43,0xAC, ++0x30,0x1F,0xB1,0x26, ++0x7C,0x36,0x24,0x96, ++0x70,0x03,0x05,0x36, ++0x00,0x00,0xB2,0x8C, ++0x01,0x00,0x84,0x24, ++0x03,0x00,0x40,0x12, ++0x7C,0x36,0x24,0xA6, ++0x01,0x00,0x62,0x26, ++0xFF,0xFF,0x53,0x30, ++0xFF,0x00,0x04,0x3C, ++0xFF,0xFF,0x82,0x34, ++0x2B,0x10,0x52,0x00, ++0x47,0x00,0x40,0x10, ++0x00,0x50,0x62,0x2E, ++0x00,0xFF,0x06,0x3C, ++0xFF,0x00,0xC2,0x34, ++0x00,0xFD,0x05,0x3C, ++0x24,0x18,0x42,0x02, ++0x29,0x00,0xA2,0x34, ++0xA7,0x01,0x62,0x10, ++0x2B,0x10,0x43,0x00, ++0x46,0x00,0x40,0x14, ++0xAC,0x00,0xA2,0x34, ++0x00,0xF2,0x06,0x3C, ++0x01,0x00,0xC2,0x34, ++0xB8,0x01,0x62,0x10, ++0x2B,0x10,0x43,0x00, ++0x7D,0x00,0x40,0x14, ++0x07,0x00,0xA2,0x34, ++0x00,0xF0,0x05,0x3C, ++0x03,0x00,0xA2,0x34, ++0xD5,0x01,0x62,0x10, ++0x2B,0x10,0x43,0x00, ++0xC8,0x00,0x40,0x14, ++0x00,0xF1,0x07,0x3C, ++0x21,0x02,0x65,0x10, ++0x00,0xFF,0x82,0x34, ++0x2B,0x10,0xA3,0x00, ++0x48,0x01,0x40,0x14, ++0x01,0x00,0xA2,0x34, ++0x00,0xE0,0x02,0x3C, ++0x73,0x01,0x62,0x10, ++0x00,0xFF,0x48,0x32, ++0x25,0xB0,0x02,0x3C, ++0x70,0x03,0x42,0x34, ++0x21,0x98,0x00,0x00, ++0x00,0x00,0x40,0xAC, ++0x25,0xB0,0x04,0x3C, ++0x18,0x03,0x82,0x34, ++0x48,0x7C,0xC3,0x27, ++0x00,0x00,0x43,0xAC, ++0x00,0x60,0x01,0x40, ++0x01,0x00,0x21,0x34, ++0x01,0x00,0x21,0x38, ++0x00,0x60,0x81,0x40, ++0x6C,0x57,0x82,0x8E, ++0x6C,0x57,0x83,0x26, ++0x10,0x00,0x43,0x10, ++0x02,0x80,0x02,0x3C, ++0xBF,0x00,0x92,0x34, ++0x30,0x1F,0x51,0x24, ++0x21,0x80,0x60,0x00, ++0x00,0x00,0x42,0x92, ++0x00,0x00,0x00,0x00, ++0x04,0x00,0x42,0x2C, ++0x08,0x00,0x40,0x10, ++0x00,0x00,0x00,0x00, ++0x3C,0x38,0x24,0x8E, ++0xB4,0x08,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x6C,0x57,0x83,0x8E, ++0x00,0x00,0x00,0x00, ++0xF5,0xFF,0x70,0x14, ++0x00,0x00,0x00,0x00, ++0x00,0x60,0x01,0x40, ++0x01,0x00,0x21,0x34, ++0x00,0x60,0x81,0x40, ++0x21,0x28,0x00,0x00, ++0x08,0x10,0xE4,0x26, ++0x21,0x30,0x00,0x00, ++0x91,0x3C,0x00,0x0C, ++0x21,0x38,0x00,0x00, ++0xE8,0x1E,0x00,0x08, ++0x25,0xB0,0x10,0x3C, ++0xDA,0xFF,0x40,0x14, ++0x74,0x03,0x03,0x36, ++0xFF,0xFF,0x02,0x24, ++0x21,0x98,0x00,0x00, ++0x00,0x00,0xA0,0xAC, ++0x00,0x00,0x62,0xAC, ++0x1B,0x1F,0x00,0x08, ++0x25,0xB0,0x04,0x3C, ++0x84,0x01,0x62,0x10, ++0x00,0x00,0x00,0x00, ++0x2B,0x10,0x43,0x00, ++0x1E,0x00,0x40,0x14, ++0x00,0xFE,0x07,0x3C, ++0xA4,0x00,0xA2,0x34, ++0x8F,0x01,0x62,0x10, ++0x2B,0x10,0x43,0x00, ++0x47,0x00,0x40,0x14, ++0xA7,0x00,0xA2,0x34, ++0xA1,0x00,0xA2,0x34, ++0xEA,0x01,0x62,0x10, ++0x00,0x00,0x00,0x00, ++0x2B,0x10,0x43,0x00, ++0xAD,0x00,0x40,0x14, ++0xA2,0x00,0xA2,0x34, ++0xA0,0x00,0xA2,0x34, ++0xBE,0xFF,0x62,0x14, ++0x25,0xB0,0x02,0x3C, ++0x00,0x0F,0x42,0x32, ++0x02,0x22,0x02,0x00, ++0x01,0x00,0x03,0x24, ++0x96,0x02,0x83,0x10, ++0x00,0x00,0x00,0x00, ++0x02,0x00,0x02,0x24, ++0x8F,0x02,0x82,0x10, ++0x00,0x00,0x00,0x00, ++0x03,0x00,0x02,0x24, ++0x88,0x02,0x82,0x10, ++0x00,0x00,0x00,0x00, ++0xCD,0x5A,0x00,0x0C, ++0x21,0x20,0x00,0x00, ++0x17,0x1F,0x00,0x08, ++0x25,0xB0,0x02,0x3C, ++0x12,0x00,0xE2,0x34, ++0x65,0x01,0x62,0x10, ++0x00,0x00,0x00,0x00, ++0x2B,0x10,0x43,0x00, ++0x37,0x00,0x40,0x14, ++0x1A,0x00,0xE2,0x34, ++0xAF,0x00,0xA2,0x34, ++0xC8,0x01,0x62,0x10, ++0x00,0x00,0x00,0x00, ++0x2B,0x10,0x43,0x00, ++0x97,0x00,0x40,0x14, ++0x10,0x00,0xE2,0x34, ++0xAD,0x00,0xA2,0x34, ++0x44,0x02,0x62,0x10, ++0x00,0x00,0x00,0x00, ++0xAE,0x00,0xA2,0x34, ++0x9C,0xFF,0x62,0x14, ++0x02,0x24,0x12,0x00, ++0x00,0xFF,0x45,0x32, ++0xFF,0x00,0x84,0x30, ++0x58,0x5A,0x00,0x0C, ++0x02,0x2A,0x05,0x00, ++0x25,0xB0,0x03,0x3C, ++0x74,0x03,0x63,0x34, ++0x00,0x00,0x62,0xA0, ++0x17,0x1F,0x00,0x08, ++0x25,0xB0,0x02,0x3C, ++0x73,0x01,0x62,0x10, ++0x00,0x00,0x00,0x00, ++0x2B,0x10,0x43,0x00, ++0x35,0x00,0x40,0x14, ++0x18,0x00,0xA2,0x34, ++0x00,0xF8,0x04,0x3C, ++0x16,0x00,0x82,0x34, ++0xB6,0x01,0x62,0x10, ++0x00,0x00,0x00,0x00, ++0x2B,0x10,0x43,0x00, ++0x90,0x00,0x40,0x14, ++0x17,0x00,0x82,0x34, ++0x15,0x00,0x82,0x34, ++0x84,0xFF,0x62,0x14, ++0x00,0x00,0x00,0x00, ++0xA7,0x22,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x17,0x1F,0x00,0x08, ++0x25,0xB0,0x02,0x3C, ++0x6A,0x01,0x62,0x10, ++0x2B,0x10,0x43,0x00, ++0xB7,0x00,0x40,0x14, ++0xAA,0x00,0xA2,0x34, ++0xA5,0x00,0xA2,0x34, ++0x35,0x02,0x62,0x10, ++0x24,0x20,0x44,0x02, ++0xA6,0x00,0xA2,0x34, ++0x76,0xFF,0x62,0x14, ++0x00,0x00,0x00,0x00, ++0xF7,0x5B,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x17,0x1F,0x00,0x08, ++0x25,0xB0,0x02,0x3C, ++0x75,0x01,0x62,0x10, ++0x2B,0x10,0x43,0x00, ++0x80,0x00,0x40,0x14, ++0x0F,0x00,0xC2,0x34, ++0x18,0x00,0xE2,0x34, ++0xC1,0x01,0x62,0x10, ++0x00,0x00,0x00,0x00, ++0x19,0x00,0xE2,0x34, ++0x68,0xFF,0x62,0x14, ++0x00,0x00,0x00,0x00, ++0x00,0x60,0x01,0x40, ++0x01,0x00,0x21,0x34, ++0x01,0x00,0x21,0x38, ++0x00,0x60,0x81,0x40, ++0x30,0x1F,0xA2,0x26, ++0x2A,0x1C,0x44,0x90, ++0x25,0xB0,0x03,0x3C, ++0x74,0x03,0x63,0x34, ++0x00,0x00,0x64,0xAC, ++0x00,0x60,0x01,0x40, ++0x01,0x00,0x21,0x34, ++0x00,0x60,0x81,0x40, ++0x17,0x1F,0x00,0x08, ++0x25,0xB0,0x02,0x3C, ++0x3E,0x01,0x62,0x10, ++0x2B,0x10,0x43,0x00, ++0x74,0x00,0x40,0x14, ++0x19,0x00,0xA2,0x34, ++0x14,0x00,0xA2,0x34, ++0x96,0x01,0x62,0x10, ++0x17,0x00,0xA2,0x34, ++0x51,0xFF,0x62,0x14, ++0x25,0xB0,0x04,0x3C, ++0x68,0x03,0x85,0x34, ++0x00,0x00,0xA3,0x8C, ++0x00,0xFF,0x42,0x32, ++0x00,0x12,0x02,0x00, ++0xFF,0xFF,0x73,0x30, ++0x25,0x10,0x53,0x00, ++0x00,0x00,0xA2,0xAC, ++0x64,0x03,0x84,0x34, ++0x00,0x00,0x82,0x90, ++0x00,0x00,0x00,0x00, ++0xFF,0x00,0x53,0x30, ++0x40,0x00,0x63,0x36, ++0x00,0x00,0x83,0xA0, ++0x17,0x1F,0x00,0x08, ++0x25,0xB0,0x02,0x3C, ++0x02,0x00,0xE2,0x34, ++0x3F,0xFF,0x62,0x10, ++0x2B,0x10,0x43,0x00, ++0x9B,0x00,0x40,0x14, ++0x04,0x00,0xE2,0x34, ++0x08,0x00,0xA2,0x34, ++0xA3,0x01,0x62,0x10, ++0x00,0xFF,0x42,0x32, ++0x38,0xFF,0x67,0x14, ++0x25,0xB0,0x04,0x3C, ++0xFF,0x00,0x05,0x3C, ++0x00,0xFF,0xA5,0x34, ++0x24,0x28,0x45,0x02, ++0x02,0x2A,0x05,0x00, ++0x94,0x00,0x83,0x34, ++0x40,0x11,0x05,0x00, ++0x26,0xB0,0x06,0x3C, ++0x00,0x00,0x65,0xA4, ++0xC0,0xFF,0x53,0x24, ++0x7C,0x00,0xCC,0x34, ++0x04,0x00,0x07,0x24, ++0x9A,0x00,0x88,0x34, ++0x98,0x00,0x89,0x34, ++0x96,0x00,0x8A,0x34, ++0x7A,0x00,0xC6,0x34, ++0xB0,0x03,0x8B,0x34, ++0x00,0x04,0x02,0x24, ++0xA0,0x00,0x03,0x24, ++0x00,0x00,0x02,0xA5, ++0x44,0x00,0x84,0x34, ++0x00,0x00,0x23,0xA5, ++0x00,0x00,0x47,0xA5, ++0x00,0x00,0xC7,0xA0, ++0x00,0x00,0x73,0xAD, ++0x00,0x00,0x93,0xA5, ++0x00,0x00,0x83,0x94, ++0xFF,0xFD,0x02,0x24, ++0x30,0x1F,0xA6,0x26, ++0x24,0x18,0x62,0x00, ++0x00,0x00,0x83,0xA4, ++0x00,0x00,0x82,0x94, ++0xBA,0x1B,0xC5,0xA4, ++0x00,0x02,0x42,0x34, ++0x00,0x00,0x82,0xA4, ++0x17,0x1F,0x00,0x08, ++0x25,0xB0,0x02,0x3C, ++0xBF,0x01,0x62,0x10, ++0x25,0xB0,0x02,0x3C, ++0xA3,0x00,0xA2,0x34, ++0x10,0xFF,0x62,0x14, ++0x25,0xB0,0x02,0x3C, ++0x30,0x1F,0xA2,0x26, ++0x16,0x1F,0x00,0x08, ++0x30,0x38,0x40,0xAC, ++0x3A,0x01,0x62,0x10, ++0x11,0x00,0xE2,0x34, ++0x08,0xFF,0x62,0x14, ++0x00,0x00,0x00,0x00, ++0x00,0x60,0x01,0x40, ++0x01,0x00,0x21,0x34, ++0x01,0x00,0x21,0x38, ++0x00,0x60,0x81,0x40, ++0xFF,0x00,0x04,0x3C, ++0x00,0xFF,0x84,0x34, ++0x24,0x20,0x44,0x02, ++0x30,0x1F,0xA2,0x26, ++0x02,0x22,0x04,0x00, ++0xC2,0x34,0x00,0x0C, ++0x2A,0x1C,0x40,0xA0, ++0x00,0x60,0x01,0x40, ++0x01,0x00,0x21,0x34, ++0x00,0x60,0x81,0x40, ++0x17,0x1F,0x00,0x08, ++0x25,0xB0,0x02,0x3C, ++0x9F,0x01,0x62,0x10, ++0x00,0x00,0x00,0x00, ++0x18,0x00,0x82,0x34, ++0xF3,0xFE,0x62,0x14, ++0x00,0x00,0x00,0x00, ++0x0A,0x23,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x17,0x1F,0x00,0x08, ++0x25,0xB0,0x02,0x3C, ++0x4E,0x01,0x62,0x10, ++0x10,0x00,0xC2,0x34, ++0xEC,0xFE,0x62,0x14, ++0x25,0xB0,0x02,0x3C, ++0x00,0xFF,0x43,0x32, ++0x00,0xFF,0x02,0x34, ++0xDA,0xFF,0x62,0x14, ++0x30,0x1F,0xA2,0x26, ++0x30,0x1F,0xA3,0x26, ++0xFF,0xFF,0x02,0x34, ++0x16,0x1F,0x00,0x08, ++0x30,0x38,0x62,0xAC, ++0x96,0x01,0x62,0x10, ++0x25,0xB0,0x02,0x3C, ++0x28,0x00,0xA2,0x34, ++0xDE,0xFE,0x62,0x14, ++0x0F,0x00,0x10,0x3C, ++0xFF,0xFF,0x05,0x36, ++0x60,0x00,0x06,0x24, ++0x5F,0x47,0x00,0x0C, ++0x24,0x00,0x04,0x24, ++0x25,0x22,0x00,0x0C, ++0xE8,0x03,0x04,0x24, ++0x00,0x60,0x01,0x40, ++0x01,0x00,0x21,0x34, ++0x01,0x00,0x21,0x38, ++0x00,0x60,0x81,0x40, ++0x24,0x00,0x04,0x24, ++0x8A,0x47,0x00,0x0C, ++0xFF,0xFF,0x05,0x36, ++0x1F,0x00,0x53,0x30, ++0x00,0x60,0x01,0x40, ++0x01,0x00,0x21,0x34, ++0x00,0x60,0x81,0x40, ++0x54,0x22,0x00,0x0C, ++0x64,0x00,0x04,0x24, ++0x25,0xB0,0x02,0x3C, ++0x74,0x03,0x42,0x34, ++0x00,0x00,0x53,0xA0, ++0x17,0x1F,0x00,0x08, ++0x25,0xB0,0x02,0x3C, ++0x84,0x01,0x62,0x10, ++0x00,0x00,0x00,0x00, ++0xAB,0x00,0xA2,0x34, ++0xC1,0xFE,0x62,0x14, ++0x00,0x00,0x00,0x00, ++0xE6,0x5F,0x00,0x0C, ++0x21,0x20,0x40,0x02, ++0x17,0x1F,0x00,0x08, ++0x25,0xB0,0x02,0x3C, ++0x4C,0x01,0x62,0x10, ++0x25,0xB0,0x02,0x3C, ++0x02,0x00,0xA2,0x34, ++0xB9,0xFE,0x62,0x14, ++0x25,0xB0,0x02,0x3C, ++0x02,0x14,0x12,0x00, ++0x00,0xFF,0x43,0x32, ++0xFF,0x00,0x45,0x30, ++0x04,0x00,0xA0,0x10, ++0x02,0x92,0x03,0x00, ++0x01,0x00,0x02,0x24, ++0x02,0x00,0xA2,0x10, ++0x01,0x00,0x04,0x24, ++0x21,0x20,0x00,0x00, ++0xE6,0x44,0x00,0x0C, ++0x0F,0x00,0x10,0x3C, ++0xFF,0xFF,0x05,0x36, ++0x8A,0x47,0x00,0x0C, ++0x21,0x20,0x40,0x02, ++0xFF,0xFF,0x10,0x36, ++0x24,0x98,0x50,0x00, ++0x25,0xB0,0x02,0x3C, ++0x74,0x03,0x42,0x34, ++0x00,0x00,0x53,0xAC, ++0x17,0x1F,0x00,0x08, ++0x25,0xB0,0x02,0x3C, ++0x15,0x01,0x62,0x10, ++0x24,0x10,0x44,0x02, ++0xA0,0xFE,0x66,0x14, ++0x25,0xB0,0x02,0x3C, ++0x25,0xB0,0x05,0x3C, ++0x74,0x03,0xA3,0x34, ++0x00,0x00,0x64,0x8C, ++0xFF,0x0F,0x02,0x3C, ++0xFF,0xFF,0x42,0x34, ++0x24,0x90,0x82,0x00, ++0x01,0x00,0x03,0x3C, ++0x2B,0x18,0x72,0x00, ++0x95,0xFE,0x60,0x10, ++0x00,0xB0,0x02,0x3C, ++0x25,0x90,0x42,0x02, ++0x00,0x00,0x53,0x8E, ++0x78,0x03,0xA2,0x34, ++0x00,0x00,0x53,0xAC, ++0x17,0x1F,0x00,0x08, ++0x25,0xB0,0x02,0x3C, ++0x02,0x1A,0x08,0x00, ++0xFF,0x00,0x02,0x24, ++0x56,0x01,0x62,0x10, ++0x25,0xB0,0x05,0x3C, ++0x0E,0x00,0x60,0x14, ++0x00,0xCC,0x02,0x34, ++0x25,0xB0,0x04,0x3C, ++0x64,0x03,0x84,0x34, ++0x30,0x1F,0xA7,0x26, ++0x00,0x00,0x85,0x94, ++0xE4,0x02,0xE6,0x8C, ++0xFF,0xCF,0x02,0x3C, ++0xFF,0xFE,0x03,0x24, ++0xFF,0xFF,0x42,0x34, ++0x24,0x28,0xA3,0x00, ++0x24,0x30,0xC2,0x00, ++0x00,0x00,0x85,0xA4, ++0xE4,0x02,0xE6,0xAC, ++0x00,0xCC,0x02,0x34, ++0x7B,0xFE,0x02,0x15, ++0x25,0xB0,0x02,0x3C, ++0x30,0x1F,0xA5,0x26, ++0xE4,0x02,0xA3,0x8C, ++0xFF,0xCF,0x02,0x3C, ++0xFF,0xFF,0x42,0x34, ++0x24,0x18,0x62,0x00, ++0x00,0x10,0x04,0x3C, ++0x25,0x18,0x64,0x00, ++0x16,0x1F,0x00,0x08, ++0xE4,0x02,0xA3,0xAC, ++0x02,0x14,0x12,0x00, ++0x00,0x1F,0x43,0x32, ++0x02,0x9A,0x03,0x00, ++0x3F,0x00,0x42,0x30, ++0xC1,0x02,0x22,0xA2, ++0xBC,0x02,0x33,0xA2, ++0x00,0x60,0x01,0x40, ++0x01,0x00,0x21,0x34, ++0x01,0x00,0x21,0x38, ++0x00,0x60,0x81,0x40, ++0x76,0x2C,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x21,0x98,0x40,0x00, ++0x74,0x03,0x02,0x36, ++0x00,0x00,0x53,0xAC, ++0x00,0x60,0x01,0x40, ++0x01,0x00,0x21,0x34, ++0x00,0x60,0x81,0x40, ++0x03,0x00,0x22,0x92, ++0x00,0x00,0x00,0x00, ++0x01,0x00,0x42,0x24, ++0x16,0x1F,0x00,0x08, ++0x03,0x00,0x22,0xA2, ++0x74,0x03,0x03,0x36, ++0x00,0x00,0x64,0x8C, ++0xFF,0x0F,0x02,0x3C, ++0xFF,0xFF,0x42,0x34, ++0x24,0x90,0x82,0x00, ++0x01,0x00,0x03,0x3C, ++0x2B,0x18,0x72,0x00, ++0x51,0xFE,0x60,0x10, ++0x78,0x03,0x02,0x36, ++0x00,0x00,0x53,0x8C, ++0x00,0xB0,0x03,0x3C, ++0x25,0x90,0x43,0x02, ++0x00,0x00,0x53,0xAE, ++0x17,0x1F,0x00,0x08, ++0x25,0xB0,0x02,0x3C, ++0xBE,0x59,0x00,0x0C, ++0x21,0x20,0x40,0x02, ++0x17,0x1F,0x00,0x08, ++0x25,0xB0,0x02,0x3C, ++0x00,0x60,0x01,0x40, ++0x01,0x00,0x21,0x34, ++0x01,0x00,0x21,0x38, ++0x00,0x60,0x81,0x40, ++0x00,0xFF,0x82,0x34, ++0x24,0x10,0x42,0x02, ++0x02,0x2A,0x02,0x00, ++0x2B,0x1C,0x25,0xA2, ++0x00,0x60,0x01,0x40, ++0x01,0x00,0x21,0x34, ++0x00,0x60,0x81,0x40, ++0x17,0x1F,0x00,0x08, ++0x25,0xB0,0x02,0x3C, ++0xFF,0xFF,0x02,0x34, ++0x16,0x1F,0x00,0x08, ++0x30,0x38,0x22,0xAE, ++0x24,0x10,0x44,0x02, ++0x00,0xFF,0x43,0x32, ++0x02,0x2C,0x02,0x00, ++0x04,0x00,0xA0,0x10, ++0x02,0x92,0x03,0x00, ++0x01,0x00,0x02,0x24, ++0x02,0x00,0xA2,0x10, ++0x01,0x00,0x04,0x24, ++0x21,0x20,0x00,0x00, ++0x25,0xB0,0x10,0x3C, ++0xE6,0x44,0x00,0x0C, ++0x74,0x03,0x10,0x36, ++0x00,0x00,0x13,0x8E, ++0x0F,0x00,0x11,0x3C, ++0x21,0x20,0x40,0x02, ++0x21,0x30,0x60,0x02, ++0x5F,0x47,0x00,0x0C, ++0xFF,0xFF,0x25,0x36, ++0x21,0x20,0x40,0x02, ++0x8A,0x47,0x00,0x0C, ++0xFF,0xFF,0x25,0x36, ++0x00,0x00,0x02,0xAE, ++0x17,0x1F,0x00,0x08, ++0x25,0xB0,0x02,0x3C, ++0x85,0x5F,0x00,0x0C, ++0x21,0x20,0x40,0x02, ++0x17,0x1F,0x00,0x08, ++0x25,0xB0,0x02,0x3C, ++0x08,0x00,0x23,0x8E, ++0xFF,0x9F,0x02,0x3C, ++0xFF,0xFF,0x42,0x34, ++0x24,0x18,0x62,0x00, ++0x16,0x1F,0x00,0x08, ++0x08,0x00,0x23,0xAE, ++0x00,0xFF,0x42,0x32, ++0x24,0x18,0x44,0x02, ++0x02,0x9A,0x02,0x00, ++0x01,0x00,0x02,0x24, ++0x95,0x00,0x62,0x12, ++0x02,0x1C,0x03,0x00, ++0x02,0x00,0x02,0x24, ++0xA9,0x00,0x62,0x12, ++0xC0,0x10,0x03,0x00, ++0x03,0x00,0x02,0x24, ++0x09,0xFE,0x62,0x16, ++0xC0,0x10,0x03,0x00, ++0x21,0x10,0x43,0x00, ++0x80,0x10,0x02,0x00, ++0x21,0x10,0x43,0x00, ++0x02,0x80,0x04,0x3C, ++0x4C,0x43,0x83,0x24, ++0x80,0x10,0x02,0x00, ++0x21,0x10,0x43,0x00, ++0x00,0x00,0x44,0x8C, ++0x25,0xB0,0x03,0x3C, ++0x74,0x03,0x63,0x34, ++0x00,0x00,0x64,0xAC, ++0x17,0x1F,0x00,0x08, ++0x25,0xB0,0x02,0x3C, ++0x00,0xFF,0x82,0x34, ++0x24,0x10,0x42,0x02, ++0x02,0x2A,0x02,0x00, ++0x01,0x00,0x03,0x24, ++0x77,0x00,0xA3,0x10, ++0x74,0x03,0x02,0x36, ++0x02,0x00,0xA2,0x28, ++0xB7,0x00,0x40,0x14, ++0x03,0x00,0x02,0x24, ++0x06,0x00,0xA2,0x10, ++0x00,0x00,0x00,0x00, ++0x30,0x1F,0xA2,0x26, ++0x24,0x1C,0x44,0x94, ++0x25,0xB0,0x03,0x3C, ++0x18,0x21,0x00,0x08, ++0x74,0x03,0x63,0x34, ++0x30,0x1F,0xA2,0x26, ++0x26,0x1C,0x44,0x94, ++0x25,0xB0,0x03,0x3C, ++0x18,0x21,0x00,0x08, ++0x74,0x03,0x63,0x34, ++0x24,0x10,0x42,0x02, ++0x02,0x92,0x02,0x00, ++0x21,0x18,0x50,0x02, ++0x00,0x00,0x73,0x8C, ++0x74,0x03,0x02,0x36, ++0x00,0x00,0x53,0xAC, ++0x00,0x00,0x73,0x8C, ++0x17,0x1F,0x00,0x08, ++0x25,0xB0,0x02,0x3C, ++0xA6,0x5A,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x17,0x1F,0x00,0x08, ++0x25,0xB0,0x02,0x3C, ++0x24,0x20,0x44,0x02, ++0x56,0x25,0x00,0x0C, ++0x02,0x24,0x04,0x00, ++0x17,0x1F,0x00,0x08, ++0x25,0xB0,0x02,0x3C, ++0xD7,0x22,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x17,0x1F,0x00,0x08, ++0x25,0xB0,0x02,0x3C, ++0x00,0x60,0x01,0x40, ++0x01,0x00,0x21,0x34, ++0x01,0x00,0x21,0x38, ++0x00,0x60,0x81,0x40, ++0x30,0x1F,0xA3,0x26, ++0x2A,0x1C,0x62,0x90, ++0x00,0x00,0x00,0x00, ++0x6A,0xFE,0x40,0x14, ++0x00,0x00,0x00,0x00, ++0x00,0xFF,0x82,0x34, ++0x24,0x10,0x42,0x02, ++0x02,0x2A,0x02,0x00, ++0x01,0x00,0x02,0x24, ++0x21,0x20,0xA0,0x00, ++0x2A,0x1C,0x62,0xA0, ++0xC2,0x34,0x00,0x0C, ++0x2B,0x1C,0x65,0xA0, ++0x1A,0x20,0x00,0x08, ++0x00,0x00,0x00,0x00, ++0x00,0xFF,0x82,0x34, ++0x24,0x10,0x42,0x02, ++0xBB,0xFD,0x40,0x10, ++0x25,0xB0,0x02,0x3C, ++0x30,0x1F,0xA3,0x26, ++0x04,0x03,0x66,0x90, ++0x24,0x20,0x44,0x02, ++0x00,0xFF,0x45,0x32, ++0x02,0x24,0x04,0x00, ++0x02,0x2A,0x05,0x00, ++0x00,0x01,0xC6,0x34, ++0xFB,0xFF,0x87,0x24, ++0xFB,0xFF,0xA2,0x24, ++0x1F,0x03,0x62,0xA0, ++0x04,0x03,0x66,0xAC, ++0x1D,0x03,0x67,0xA0, ++0x1C,0x03,0x64,0xA0, ++0x16,0x1F,0x00,0x08, ++0x1E,0x03,0x65,0xA0, ++0x00,0x60,0x01,0x40, ++0x01,0x00,0x21,0x34, ++0x01,0x00,0x21,0x38, ++0x00,0x60,0x81,0x40, ++0x30,0x1F,0xA2,0x26, ++0x2B,0x1C,0x44,0x90, ++0x25,0xB0,0x03,0x3C, ++0x74,0x03,0x63,0x34, ++0x00,0x00,0x64,0xAC, ++0xB8,0x1F,0x00,0x08, ++0x00,0x00,0x00,0x00, ++0x25,0xB0,0x03,0x3C, ++0xFF,0x00,0x02,0x24, ++0x56,0x01,0x63,0x34, ++0x00,0x00,0x62,0xA4, ++0x01,0x00,0x04,0x24, ++0x02,0x80,0x02,0x3C, ++0x16,0x1F,0x00,0x08, ++0x08,0x5E,0x44,0xA0, ++0x02,0x92,0x02,0x00, ++0x05,0x00,0x40,0x12, ++0x21,0x20,0x00,0x00, ++0x01,0x00,0x02,0x24, ++0x02,0x00,0x42,0x12, ++0x01,0x00,0x04,0x24, ++0x21,0x20,0x00,0x00, ++0xE6,0x44,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x17,0x1F,0x00,0x08, ++0x25,0xB0,0x02,0x3C, ++0x02,0x9C,0x02,0x00, ++0x00,0xFF,0x43,0x32, ++0x07,0x00,0x62,0x2E, ++0x88,0xFD,0x40,0x10, ++0x02,0x2A,0x03,0x00, ++0x02,0x80,0x04,0x3C, ++0x50,0xED,0x83,0x24, ++0x80,0x10,0x13,0x00, ++0x21,0x10,0x43,0x00, ++0x00,0x00,0x44,0x8C, ++0x00,0x00,0x00,0x00, ++0x08,0x00,0x80,0x00, ++0x00,0x00,0x00,0x00, ++0x22,0x1C,0x23,0x96, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x43,0xAC, ++0x17,0x1F,0x00,0x08, ++0x25,0xB0,0x02,0x3C, ++0xC0,0x10,0x03,0x00, ++0x21,0x10,0x43,0x00, ++0x80,0x10,0x02,0x00, ++0x21,0x10,0x43,0x00, ++0x80,0x10,0x02,0x00, ++0x21,0x10,0x51,0x00, ++0x14,0x24,0x44,0x8C, ++0x74,0x03,0x03,0x36, ++0x00,0x00,0x64,0xAC, ++0x17,0x1F,0x00,0x08, ++0x25,0xB0,0x02,0x3C, ++0x00,0xFF,0x83,0x34, ++0x74,0x03,0x44,0x34, ++0x00,0x00,0x93,0x8C, ++0x24,0x18,0x43,0x02, ++0x02,0x92,0x03,0x00, ++0x21,0x10,0x42,0x02, ++0x00,0x00,0x53,0xAC, ++0x00,0x00,0x53,0x8C, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x93,0xAC, ++0x17,0x1F,0x00,0x08, ++0x25,0xB0,0x02,0x3C, ++0x21,0x10,0x43,0x00, ++0x80,0x10,0x02,0x00, ++0x21,0x10,0x43,0x00, ++0x80,0x10,0x02,0x00, ++0x21,0x10,0x51,0x00, ++0x18,0x24,0x44,0x8C, ++0xA4,0x21,0x00,0x08, ++0x74,0x03,0x03,0x36, ++0xCD,0x59,0x00,0x0C, ++0x21,0x20,0x40,0x02, ++0x17,0x1F,0x00,0x08, ++0x25,0xB0,0x02,0x3C, ++0x3D,0x23,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x17,0x1F,0x00,0x08, ++0x25,0xB0,0x02,0x3C, ++0x74,0x03,0x42,0x34, ++0x00,0x00,0x45,0x8C, ++0x00,0xFF,0x84,0x34, ++0x24,0x20,0x44,0x02, ++0xC1,0x5B,0x00,0x0C, ++0x02,0x22,0x04,0x00, ++0x17,0x1F,0x00,0x08, ++0x25,0xB0,0x02,0x3C, ++0x70,0x03,0x42,0x34, ++0x21,0x20,0x40,0x02, ++0x00,0x00,0x40,0xAC, ++0x6B,0x1E,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x17,0x1F,0x00,0x08, ++0x25,0xB0,0x02,0x3C, ++0xF5,0x5B,0x00,0x0C, ++0x02,0x24,0x04,0x00, ++0x17,0x1F,0x00,0x08, ++0x25,0xB0,0x02,0x3C, ++0x00,0x60,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x17,0x1F,0x00,0x08, ++0x25,0xB0,0x02,0x3C, ++0x4B,0xFF,0xA0,0x14, ++0x00,0x00,0x00,0x00, ++0x30,0x1F,0xA2,0x26, ++0x20,0x1C,0x44,0x94, ++0x25,0xB0,0x03,0x3C, ++0x18,0x21,0x00,0x08, ++0x74,0x03,0x63,0x34, ++0x64,0x03,0xA5,0x34, ++0x30,0x1F,0xA6,0x26, ++0x00,0x00,0xA3,0x94, ++0xE4,0x02,0xC4,0x8C, ++0xFF,0xCF,0x02,0x3C, ++0xFF,0xFF,0x42,0x34, ++0x24,0x20,0x82,0x00, ++0x00,0x01,0x63,0x34, ++0x00,0x00,0xA3,0xA4, ++0x9A,0x20,0x00,0x08, ++0xE4,0x02,0xC4,0xAC, ++0xCD,0x5A,0x00,0x0C, ++0x03,0x00,0x04,0x24, ++0x17,0x1F,0x00,0x08, ++0x25,0xB0,0x02,0x3C, ++0xCD,0x5A,0x00,0x0C, ++0x02,0x00,0x04,0x24, ++0x17,0x1F,0x00,0x08, ++0x25,0xB0,0x02,0x3C, ++0xCD,0x5A,0x00,0x0C, ++0x01,0x00,0x04,0x24, ++0x17,0x1F,0x00,0x08, ++0x25,0xB0,0x02,0x3C, ++0x00,0x19,0x05,0x00, ++0x30,0x1F,0xA2,0x26, ++0x21,0x18,0x62,0x00, ++0x36,0x03,0x64,0x94, ++0x25,0xB0,0x02,0x3C, ++0x74,0x03,0x42,0x34, ++0x00,0x00,0x44,0xAC, ++0x17,0x1F,0x00,0x08, ++0x25,0xB0,0x02,0x3C, ++0x00,0x19,0x05,0x00, ++0x30,0x1F,0xA2,0x26, ++0x21,0x18,0x62,0x00, ++0x35,0x03,0x64,0x90, ++0xFD,0x21,0x00,0x08, ++0x25,0xB0,0x02,0x3C, ++0x00,0x19,0x05,0x00, ++0x30,0x1F,0xA2,0x26, ++0x21,0x18,0x62,0x00, ++0x34,0x03,0x64,0x90, ++0xFD,0x21,0x00,0x08, ++0x25,0xB0,0x02,0x3C, ++0x00,0x19,0x05,0x00, ++0x30,0x1F,0xA2,0x26, ++0x21,0x18,0x62,0x00, ++0x32,0x03,0x64,0x94, ++0xFD,0x21,0x00,0x08, ++0x25,0xB0,0x02,0x3C, ++0x00,0x19,0x05,0x00, ++0x30,0x1F,0xA2,0x26, ++0x21,0x18,0x62,0x00, ++0x30,0x03,0x64,0x94, ++0xFD,0x21,0x00,0x08, ++0x25,0xB0,0x02,0x3C, ++0x00,0x11,0x05,0x00, ++0x30,0x1F,0xA3,0x26, ++0x21,0x10,0x43,0x00, ++0x2C,0x03,0x44,0x8C, ++0xFC,0x21,0x00,0x08, ++0x42,0x26,0x04,0x00, ++0x00,0x11,0x05,0x00, ++0x30,0x1F,0xA3,0x26, ++0x21,0x10,0x43,0x00, ++0x2F,0x03,0x44,0x90, ++0xFC,0x21,0x00,0x08, ++0x01,0x00,0x84,0x30, ++0x01,0x80,0x03,0x3C, ++0x25,0xB0,0x02,0x3C, ++0x18,0x03,0x42,0x34, ++0x94,0x88,0x63,0x24, ++0x00,0x00,0x43,0xAC, ++0x02,0x80,0x05,0x3C, ++0xD4,0x5E,0xA5,0x8C, ++0x04,0x00,0x02,0x24, ++0x1E,0x00,0xA2,0x10, ++0x05,0x00,0xA2,0x2C, ++0x10,0x00,0x40,0x10, ++0x05,0x00,0x02,0x24, ++0x03,0x00,0x02,0x24, ++0x08,0x00,0xA2,0x10, ++0x00,0x19,0x04,0x00, ++0x80,0x10,0x04,0x00, ++0x21,0x10,0x44,0x00, ++0xC0,0x10,0x02,0x00, ++0x23,0x10,0x44,0x00, ++0x00,0x11,0x02,0x00, ++0x21,0x10,0x44,0x00, ++0x40,0x19,0x02,0x00, ++0xFF,0xFF,0x63,0x24, ++0xFE,0xFF,0x60,0x14, ++0x00,0x00,0x00,0x00, ++0x08,0x00,0xE0,0x03, ++0x00,0x00,0x00,0x00, ++0xF3,0xFF,0xA2,0x10, ++0x06,0x00,0x02,0x24, ++0xF2,0xFF,0xA2,0x14, ++0x80,0x10,0x04,0x00, ++0x40,0x11,0x04,0x00, ++0x23,0x10,0x44,0x00, ++0x80,0x10,0x02,0x00, ++0x21,0x10,0x44,0x00, ++0x00,0x19,0x02,0x00, ++0x23,0x18,0x62,0x00, ++0x3B,0x22,0x00,0x08, ++0x00,0x19,0x03,0x00, ++0x80,0x10,0x04,0x00, ++0x21,0x10,0x44,0x00, ++0xC0,0x10,0x02,0x00, ++0x23,0x10,0x44,0x00, ++0x00,0x11,0x02,0x00, ++0x21,0x10,0x44,0x00, ++0x3B,0x22,0x00,0x08, ++0x00,0x19,0x02,0x00, ++0x01,0x80,0x03,0x3C, ++0x25,0xB0,0x02,0x3C, ++0x50,0x89,0x63,0x24, ++0x18,0x03,0x42,0x34, ++0x00,0x00,0x43,0xAC, ++0x02,0x80,0x05,0x3C, ++0xD4,0x5E,0xA3,0x8C, ++0x05,0x00,0x02,0x24, ++0x06,0x00,0x62,0x10, ++0x06,0x00,0x62,0x2C, ++0x0C,0x00,0x40,0x10, ++0x06,0x00,0x02,0x24, ++0x04,0x00,0x02,0x24, ++0x0E,0x00,0x62,0x10, ++0x80,0x10,0x04,0x00, ++0x80,0x10,0x04,0x00, ++0x21,0x10,0x44,0x00, ++0x80,0x10,0x02,0x00, ++0xFF,0xFF,0x42,0x24, ++0xFE,0xFF,0x40,0x14, ++0x00,0x00,0x00,0x00, ++0x08,0x00,0xE0,0x03, ++0x00,0x00,0x00,0x00, ++0xF7,0xFF,0x62,0x14, ++0x00,0x11,0x04,0x00, ++0x23,0x10,0x44,0x00, ++0x66,0x22,0x00,0x08, ++0x40,0x10,0x02,0x00, ++0x21,0x10,0x44,0x00, ++0x66,0x22,0x00,0x08, ++0x40,0x10,0x02,0x00, ++0xFF,0xFF,0x85,0x30, ++0x21,0x30,0x00,0x00, ++0x25,0xB0,0x03,0x3C, ++0x2A,0xB0,0x04,0x3C, ++0xB4,0x00,0x63,0x34, ++0x01,0x00,0xA2,0x24, ++0x31,0x00,0x84,0x34, ++0x00,0x00,0x65,0xA0, ++0x00,0x00,0x85,0xA0, ++0xFF,0xFF,0x45,0x30, ++0x12,0x00,0xA0,0x10, ++0x01,0x00,0x03,0x24, ++0x28,0xB0,0x07,0x3C, ++0x88,0x22,0x00,0x08, ++0xFF,0xFF,0x08,0x24, ++0x00,0x00,0x83,0xA0, ++0x01,0x00,0x63,0x24, ++0xFF,0xFF,0x63,0x30, ++0x2B,0x10,0xA3,0x00, ++0x09,0x00,0x40,0x14, ++0x08,0x00,0xC6,0x24, ++0xF9,0xFF,0x65,0x14, ++0x21,0x20,0xC7,0x00, ++0x01,0x00,0x63,0x24, ++0xFF,0xFF,0x63,0x30, ++0x2B,0x10,0xA3,0x00, ++0x00,0x00,0x88,0xA0, ++0xF9,0xFF,0x40,0x10, ++0x08,0x00,0xC6,0x24, ++0x00,0x01,0xA2,0x2C, ++0x13,0x00,0x40,0x10, ++0x21,0x18,0xA0,0x00, ++0xFF,0x00,0x08,0x24, ++0x28,0xB0,0x07,0x3C, ++0x9C,0x22,0x00,0x08, ++0xFF,0xFF,0x09,0x24, ++0xFF,0xFF,0x43,0x30, ++0x00,0x00,0xA2,0xA0, ++0x00,0x01,0x62,0x2C, ++0x0A,0x00,0x40,0x10, ++0x08,0x00,0xC6,0x24, ++0x01,0x00,0x62,0x24, ++0xF9,0xFF,0x68,0x14, ++0x21,0x28,0xC7,0x00, ++0x00,0x01,0x02,0x24, ++0xFF,0xFF,0x43,0x30, ++0x00,0x01,0x62,0x2C, ++0x00,0x00,0xA9,0xA0, ++0xF8,0xFF,0x40,0x14, ++0x08,0x00,0xC6,0x24, ++0x08,0x00,0xE0,0x03, ++0x00,0x00,0x00,0x00, ++0xD0,0xFF,0xBD,0x27, ++0x2C,0x00,0xBF,0xAF, ++0x28,0x00,0xB6,0xAF, ++0x24,0x00,0xB5,0xAF, ++0x20,0x00,0xB4,0xAF, ++0x1C,0x00,0xB3,0xAF, ++0x18,0x00,0xB2,0xAF, ++0x14,0x00,0xB1,0xAF, ++0x10,0x00,0xB0,0xAF, ++0x00,0x60,0x01,0x40, ++0x01,0x00,0x21,0x34, ++0x01,0x00,0x21,0x38, ++0x00,0x60,0x81,0x40, ++0x25,0xB0,0x10,0x3C, ++0x40,0x00,0x03,0x36, ++0x00,0x00,0x60,0xA4, ++0xA8,0x00,0x13,0x36, ++0xA0,0x00,0x12,0x36, ++0xA4,0x00,0x10,0x36, ++0x00,0x00,0x55,0x8E, ++0x00,0x00,0x16,0x8E, ++0x00,0x00,0x71,0x8E, ++0x00,0x80,0x14,0x3C, ++0xFC,0x37,0x02,0x24, ++0x00,0x00,0x40,0xAE, ++0xFD,0x00,0x04,0x24, ++0x00,0x00,0x00,0xAE, ++0x21,0x88,0x34,0x02, ++0x00,0x00,0x74,0xAE, ++0x00,0x00,0x62,0xA4, ++0x73,0x22,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x55,0xAE, ++0x00,0x00,0x16,0xAE, ++0x00,0x00,0x71,0xAE, ++0x00,0x60,0x01,0x40, ++0x01,0x00,0x21,0x34, ++0x00,0x60,0x81,0x40, ++0x2C,0x00,0xBF,0x8F, ++0x28,0x00,0xB6,0x8F, ++0x24,0x00,0xB5,0x8F, ++0x20,0x00,0xB4,0x8F, ++0x1C,0x00,0xB3,0x8F, ++0x18,0x00,0xB2,0x8F, ++0x14,0x00,0xB1,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x08,0x00,0xE0,0x03, ++0x30,0x00,0xBD,0x27, ++0xD0,0xFF,0xBD,0x27, ++0x2C,0x00,0xBF,0xAF, ++0x28,0x00,0xB6,0xAF, ++0x24,0x00,0xB5,0xAF, ++0x20,0x00,0xB4,0xAF, ++0x1C,0x00,0xB3,0xAF, ++0x18,0x00,0xB2,0xAF, ++0x14,0x00,0xB1,0xAF, ++0x10,0x00,0xB0,0xAF, ++0x00,0x60,0x01,0x40, ++0x01,0x00,0x21,0x34, ++0x01,0x00,0x21,0x38, ++0x00,0x60,0x81,0x40, ++0x25,0xB0,0x10,0x3C, ++0x40,0x00,0x05,0x36, ++0x00,0x00,0xA2,0x94, ++0x24,0xFA,0x03,0x24, ++0xA8,0x00,0x13,0x36, ++0x24,0x10,0x43,0x00, ++0x00,0x00,0xA2,0xA4, ++0xA0,0x00,0x12,0x36, ++0xA4,0x00,0x10,0x36, ++0x00,0x00,0x55,0x8E, ++0x00,0x00,0x16,0x8E, ++0x00,0x00,0x71,0x8E, ++0x00,0x80,0x14,0x3C, ++0xFC,0x37,0x02,0x24, ++0x00,0x00,0x40,0xAE, ++0xFD,0x00,0x04,0x24, ++0x00,0x00,0x00,0xAE, ++0x21,0x88,0x34,0x02, ++0x00,0x00,0x74,0xAE, ++0x00,0x00,0xA2,0xA4, ++0x73,0x22,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x55,0xAE, ++0x00,0x00,0x16,0xAE, ++0x00,0x00,0x71,0xAE, ++0x00,0x60,0x01,0x40, ++0x01,0x00,0x21,0x34, ++0x00,0x60,0x81,0x40, ++0x2C,0x00,0xBF,0x8F, ++0x28,0x00,0xB6,0x8F, ++0x24,0x00,0xB5,0x8F, ++0x20,0x00,0xB4,0x8F, ++0x1C,0x00,0xB3,0x8F, ++0x18,0x00,0xB2,0x8F, ++0x14,0x00,0xB1,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x08,0x00,0xE0,0x03, ++0x30,0x00,0xBD,0x27, ++0xD0,0xFF,0xBD,0x27, ++0x2C,0x00,0xBF,0xAF, ++0x28,0x00,0xB6,0xAF, ++0x24,0x00,0xB5,0xAF, ++0x20,0x00,0xB4,0xAF, ++0x1C,0x00,0xB3,0xAF, ++0x18,0x00,0xB2,0xAF, ++0x14,0x00,0xB1,0xAF, ++0x10,0x00,0xB0,0xAF, ++0x00,0x60,0x01,0x40, ++0x01,0x00,0x21,0x34, ++0x01,0x00,0x21,0x38, ++0x00,0x60,0x81,0x40, ++0x25,0xB0,0x10,0x3C, ++0x40,0x00,0x05,0x36, ++0x00,0x00,0xA2,0x94, ++0xAF,0xFF,0x03,0x24, ++0xA8,0x00,0x13,0x36, ++0x24,0x10,0x43,0x00, ++0x00,0x00,0xA2,0xA4, ++0xA0,0x00,0x12,0x36, ++0xA4,0x00,0x10,0x36, ++0x00,0x00,0x55,0x8E, ++0x00,0x00,0x16,0x8E, ++0x00,0x00,0x71,0x8E, ++0x00,0x80,0x14,0x3C, ++0xFC,0x37,0x02,0x24, ++0x00,0x00,0x40,0xAE, ++0xFD,0x00,0x04,0x24, ++0x00,0x00,0x00,0xAE, ++0x21,0x88,0x34,0x02, ++0x00,0x00,0x74,0xAE, ++0x00,0x00,0xA2,0xA4, ++0x73,0x22,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x55,0xAE, ++0x00,0x00,0x16,0xAE, ++0x00,0x00,0x71,0xAE, ++0x00,0x60,0x01,0x40, ++0x01,0x00,0x21,0x34, ++0x00,0x60,0x81,0x40, ++0x2C,0x00,0xBF,0x8F, ++0x28,0x00,0xB6,0x8F, ++0x24,0x00,0xB5,0x8F, ++0x20,0x00,0xB4,0x8F, ++0x1C,0x00,0xB3,0x8F, ++0x18,0x00,0xB2,0x8F, ++0x14,0x00,0xB1,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x08,0x00,0xE0,0x03, ++0x30,0x00,0xBD,0x27, ++0x00,0x60,0x01,0x40, ++0x01,0x00,0x21,0x34, ++0x01,0x00,0x21,0x38, ++0x00,0x60,0x81,0x40, ++0x25,0xB0,0x04,0x3C, ++0x40,0x00,0x84,0x34, ++0x00,0x00,0x82,0x94, ++0xD8,0xFD,0x03,0x24, ++0x24,0x10,0x43,0x00, ++0xFC,0x37,0x03,0x24, ++0x00,0x00,0x82,0xA4, ++0x00,0x00,0x83,0xA4, ++0x00,0x60,0x01,0x40, ++0x01,0x00,0x21,0x34, ++0x00,0x60,0x81,0x40, ++0x08,0x00,0xE0,0x03, ++0x00,0x00,0x00,0x00, ++0xFF,0x00,0x84,0x30, ++0xFF,0xFF,0xAC,0x30, ++0xC0,0x48,0x04,0x00, ++0x00,0x60,0x0E,0x40, ++0x01,0x00,0xC1,0x35, ++0x01,0x00,0x21,0x38, ++0x00,0x60,0x81,0x40, ++0x25,0xB0,0x02,0x3C, ++0x40,0x02,0x4D,0x34, ++0xF8,0xFF,0xE7,0x24, ++0x21,0x40,0x00,0x00, ++0x01,0x00,0x0F,0x24, ++0x44,0x02,0x4B,0x34, ++0x72,0x23,0x00,0x08, ++0x01,0x80,0x0A,0x3C, ++0x28,0x00,0x0F,0x11, ++0x00,0x00,0x00,0x00, ++0x01,0x00,0xE2,0x90, ++0x00,0x00,0xE4,0x90, ++0x02,0x00,0xE3,0x90, ++0x03,0x00,0xE5,0x90, ++0x00,0x12,0x02,0x00, ++0x25,0x20,0x82,0x00, ++0x00,0x1C,0x03,0x00, ++0x25,0x20,0x83,0x00, ++0x21,0x10,0x28,0x01, ++0x00,0x2E,0x05,0x00, ++0x01,0x00,0x08,0x25, ++0x25,0x20,0x85,0x00, ++0x25,0x10,0x4A,0x00, ++0x06,0x00,0x03,0x2D, ++0x00,0x00,0x64,0xAD, ++0x04,0x00,0xE7,0x24, ++0x00,0x00,0xA2,0xAD, ++0x12,0x00,0x60,0x10, ++0x00,0x00,0x00,0x00, ++0xEA,0xFF,0x00,0x15, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0xC2,0x90, ++0x01,0x00,0xC3,0x90, ++0x04,0x00,0xE7,0x24, ++0x00,0x14,0x02,0x00, ++0x25,0x10,0x82,0x01, ++0x00,0x1E,0x03,0x00, ++0x25,0x20,0x43,0x00, ++0x21,0x10,0x28,0x01, ++0x01,0x00,0x08,0x25, ++0x25,0x10,0x4A,0x00, ++0x06,0x00,0x03,0x2D, ++0x00,0x00,0x64,0xAD, ++0x00,0x00,0xA2,0xAD, ++0xF0,0xFF,0x60,0x14, ++0x00,0x00,0x00,0x00, ++0x00,0x60,0x8E,0x40, ++0x08,0x00,0xE0,0x03, ++0x00,0x00,0x00,0x00, ++0x03,0x00,0xC2,0x90, ++0x02,0x00,0xC4,0x90, ++0x04,0x00,0xC3,0x90, ++0x05,0x00,0xC5,0x90, ++0x64,0x23,0x00,0x08, ++0x00,0x12,0x02,0x00, ++0xFF,0xFF,0x84,0x30, ++0x42,0xB0,0x08,0x3C, ++0x80,0x10,0x04,0x00, ++0x21,0x10,0x48,0x00, ++0x04,0x00,0x46,0xAC, ++0x00,0x00,0x07,0x91, ++0x40,0x18,0x04,0x00, ++0x03,0x00,0x06,0x24, ++0xFF,0x00,0xE7,0x30, ++0x04,0x30,0x66,0x00, ++0x01,0x00,0x02,0x24, ++0x04,0x10,0x62,0x00, ++0x25,0x30,0xC7,0x00, ++0xFF,0xFF,0xA5,0x30, ++0x25,0x10,0x47,0x00, ++0x02,0x00,0xA0,0x14, ++0xFF,0x00,0xC7,0x30, ++0xFF,0x00,0x47,0x30, ++0x42,0xB0,0x02,0x3C, ++0x00,0x00,0x47,0xA0, ++0x08,0x00,0xE0,0x03, ++0x00,0x00,0x00,0x00, ++0x14,0x00,0x83,0x90, ++0x01,0x00,0x02,0x24, ++0x08,0x00,0x86,0xAC, ++0x18,0x00,0x85,0xAC, ++0x00,0x00,0x84,0xAC, ++0x03,0x00,0x62,0x10, ++0x04,0x00,0x84,0xAC, ++0x99,0x59,0x00,0x08, ++0x0C,0x00,0x80,0xAC, ++0x0C,0x00,0x82,0x8C, ++0x99,0x59,0x00,0x08, ++0x10,0x00,0x82,0xAC, ++0xC8,0xFF,0xBD,0x27, ++0x28,0x00,0xB6,0xAF, ++0x25,0xB0,0x02,0x3C, ++0x02,0x80,0x16,0x3C, ++0x2C,0x00,0xB7,0xAF, ++0x24,0x00,0xB5,0xAF, ++0x20,0x00,0xB4,0xAF, ++0x1C,0x00,0xB3,0xAF, ++0x18,0x00,0xB2,0xAF, ++0x30,0x00,0xBF,0xAF, ++0x14,0x00,0xB1,0xAF, ++0x10,0x00,0xB0,0xAF, ++0x18,0x03,0x55,0x34, ++0x01,0x80,0x17,0x3C, ++0x02,0x80,0x13,0x3C, ++0x02,0x80,0x14,0x3C, ++0x08,0xE4,0xD2,0x26, ++0xB8,0x8E,0xE2,0x26, ++0x00,0x00,0xA2,0xAE, ++0x08,0xE4,0xD0,0x8E, ++0x00,0x60,0x01,0x40, ++0x01,0x00,0x21,0x34, ++0x01,0x00,0x21,0x38, ++0x00,0x60,0x81,0x40, ++0x14,0x5E,0x71,0x8E, ++0x00,0x00,0x00,0x00, ++0x25,0x00,0x20,0x12, ++0x00,0x00,0x00,0x00, ++0x14,0x5E,0x60,0xAE, ++0x00,0x60,0x01,0x40, ++0x01,0x00,0x21,0x34, ++0x00,0x60,0x81,0x40, ++0x23,0x00,0x12,0x12, ++0x08,0x0C,0x84,0x26, ++0x14,0x00,0x03,0x92, ++0x01,0x00,0x02,0x24, ++0x2B,0x00,0x62,0x10, ++0x00,0x00,0x00,0x00, ++0x0A,0x00,0x60,0x14, ++0x02,0x00,0x02,0x24, ++0x0C,0x00,0x03,0x8E, ++0x00,0x00,0x00,0x00, ++0x2B,0x10,0x23,0x02, ++0x1E,0x00,0x40,0x10, ++0x23,0x10,0x71,0x00, ++0x0C,0x00,0x02,0xAE, ++0x00,0x00,0x10,0x8E, ++0xCE,0x23,0x00,0x08, ++0x00,0x00,0x00,0x00, ++0xFC,0xFF,0x62,0x14, ++0x00,0x00,0x00,0x00, ++0x0C,0x00,0x03,0x8E, ++0x00,0x00,0x00,0x00, ++0xF8,0xFF,0x60,0x10, ++0x2B,0x10,0x23,0x02, ++0xF5,0xFF,0x40,0x14, ++0x23,0x10,0x71,0x00, ++0x08,0x00,0x02,0x8E, ++0x18,0x00,0x04,0x8E, ++0x09,0xF8,0x40,0x00, ++0x0C,0x00,0x00,0xAE, ++0x00,0x00,0x10,0x8E, ++0xCE,0x23,0x00,0x08, ++0x00,0x00,0x00,0x00, ++0x00,0x60,0x01,0x40, ++0x01,0x00,0x21,0x34, ++0x00,0x60,0x81,0x40, ++0x08,0x0C,0x84,0x26, ++0x21,0x28,0x00,0x00, ++0x21,0x30,0x00,0x00, ++0x91,0x3C,0x00,0x0C, ++0x21,0x38,0x00,0x00, ++0xC0,0x23,0x00,0x08, ++0xB8,0x8E,0xE2,0x26, ++0x08,0x00,0x02,0x8E, ++0x18,0x00,0x04,0x8E, ++0x09,0xF8,0x40,0x00, ++0x00,0x00,0x00,0x00, ++0xDC,0x23,0x00,0x08, ++0x0C,0x00,0x02,0xAE, ++0x0C,0x00,0x03,0x8E, ++0x00,0x00,0x00,0x00, ++0x2B,0x10,0x23,0x02, ++0xD9,0xFF,0x40,0x14, ++0x23,0x10,0x71,0x00, ++0x08,0x00,0x02,0x8E, ++0x18,0x00,0x04,0x8E, ++0x09,0xF8,0x40,0x00, ++0x00,0x00,0x00,0x00, ++0x10,0x00,0x03,0x8E, ++0x00,0x00,0x00,0x00, ++0x0C,0x00,0x03,0xAE, ++0x00,0x00,0x10,0x8E, ++0xCE,0x23,0x00,0x08, ++0x00,0x00,0x00,0x00, ++0x02,0x80,0x02,0x3C, ++0x9C,0x57,0x42,0x24, ++0xC0,0x20,0x04,0x00, ++0x21,0x20,0x82,0x00, ++0x21,0x28,0x00,0x00, ++0x00,0x60,0x06,0x40, ++0x01,0x00,0xC1,0x34, ++0x01,0x00,0x21,0x38, ++0x00,0x60,0x81,0x40, ++0x00,0x00,0x82,0x8C, ++0x00,0x00,0x00,0x00, ++0x09,0x00,0x44,0x10, ++0x00,0x00,0x00,0x00, ++0x04,0x00,0x43,0x8C, ++0x21,0x28,0x40,0x00, ++0x00,0x00,0x42,0x8C, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x62,0xAC, ++0x04,0x00,0x43,0xAC, ++0x00,0x00,0xA5,0xAC, ++0x04,0x00,0xA5,0xAC, ++0x00,0x60,0x86,0x40, ++0x08,0x00,0xE0,0x03, ++0x21,0x10,0xA0,0x00, ++0x21,0x18,0x80,0x00, ++0xE8,0xFF,0xBD,0x27, ++0x01,0x01,0x62,0x2C, ++0x10,0x00,0xBF,0xAF, ++0x01,0x00,0x04,0x24, ++0x01,0x02,0x65,0x2C, ++0x0A,0x00,0x40,0x14, ++0x21,0x30,0x00,0x00, ++0x02,0x00,0x04,0x24, ++0x07,0x00,0xA0,0x14, ++0x01,0x08,0x62,0x2C, ++0x05,0x00,0x40,0x14, ++0x03,0x00,0x04,0x24, ++0x10,0x00,0xBF,0x8F, ++0x21,0x10,0xC0,0x00, ++0x08,0x00,0xE0,0x03, ++0x18,0x00,0xBD,0x27, ++0x0D,0x24,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x10,0x00,0xBF,0x8F, ++0x21,0x30,0x40,0x00, ++0x21,0x10,0xC0,0x00, ++0x08,0x00,0xE0,0x03, ++0x18,0x00,0xBD,0x27, ++0x00,0x60,0x06,0x40, ++0x01,0x00,0xC1,0x34, ++0x01,0x00,0x21,0x38, ++0x00,0x60,0x81,0x40, ++0x10,0x00,0x83,0x8C, ++0x02,0x80,0x02,0x3C, ++0x9C,0x57,0x42,0x24, ++0xC0,0x18,0x03,0x00, ++0x21,0x18,0x62,0x00, ++0x00,0x00,0x65,0x8C, ++0x02,0x80,0x07,0x3C, ++0x02,0x80,0x08,0x3C, ++0x00,0x00,0x85,0xAC, ++0x04,0x00,0xA4,0xAC, ++0x04,0x00,0x83,0xAC, ++0xD0,0x5E,0xE5,0x8C, ++0x00,0x00,0x00,0x00, ++0x05,0x00,0xA0,0x10, ++0x00,0x00,0x64,0xAC, ++0xBC,0x5E,0x02,0x8D, ++0xD0,0x5E,0xE0,0xAC, ++0x25,0x10,0x45,0x00, ++0xBC,0x5E,0x02,0xAD, ++0x00,0x60,0x86,0x40, ++0x08,0x00,0xE0,0x03, ++0x00,0x00,0x00,0x00, ++0xFF,0x00,0xA5,0x30, ++0x25,0xB0,0x02,0x3C, ++0x21,0x28,0xA2,0x00, ++0xFF,0x00,0x84,0x30, ++0x60,0x01,0xA4,0xA0, ++0x08,0x00,0xE0,0x03, ++0x00,0x00,0x00,0x00, ++0xFF,0x00,0x84,0x30, ++0x01,0x00,0x03,0x24, ++0x10,0x00,0x02,0x3C, ++0x04,0x18,0x83,0x00, ++0xF0,0x70,0x42,0x34, ++0x15,0x00,0x84,0x2C, ++0x06,0x00,0x80,0x10, ++0x24,0x28,0x62,0x00, ++0x0F,0x00,0x63,0x30, ++0x04,0x00,0xA0,0x14, ++0x01,0x00,0x02,0x24, ++0x02,0x00,0x60,0x14, ++0x02,0x00,0x02,0x24, ++0x21,0x10,0x00,0x00, ++0x08,0x00,0xE0,0x03, ++0x00,0x00,0x00,0x00, ++0xFF,0x00,0xA5,0x30, ++0x04,0x00,0xA2,0x2C, ++0x14,0x00,0x40,0x10, ++0xFF,0x00,0x84,0x30, ++0x02,0x80,0x03,0x3C, ++0xDE,0x5D,0x62,0x90, ++0x00,0x00,0x00,0x00, ++0xEF,0xFF,0x42,0x24, ++0xFF,0x00,0x42,0x30, ++0x02,0x00,0x42,0x2C, ++0x0E,0x00,0x40,0x10, ++0x02,0x00,0x03,0x24, ++0x24,0x00,0x83,0x10, ++0x0F,0x10,0x02,0x3C, ++0x03,0x00,0x82,0x28, ++0x14,0x00,0x40,0x10, ++0x03,0x00,0x02,0x24, ++0x01,0x00,0x02,0x24, ++0x2F,0x00,0x82,0x10, ++0x00,0x00,0x00,0x00, ++0xFF,0x1F,0x02,0x3C, ++0x08,0x00,0xE0,0x03, ++0xFF,0xFF,0x42,0x34, ++0x08,0x00,0xE0,0x03, ++0x00,0x00,0x00,0x00, ++0x35,0x00,0x83,0x10, ++0x0F,0x1F,0x02,0x3C, ++0x03,0x00,0x82,0x28, ++0x16,0x00,0x40,0x10, ++0x03,0x00,0x02,0x24, ++0x01,0x00,0x02,0x24, ++0xF4,0xFF,0x82,0x14, ++0x00,0x00,0x00,0x00, ++0x0F,0x1F,0x02,0x3C, ++0x08,0x00,0xE0,0x03, ++0x00,0x80,0x42,0x34, ++0xF0,0xFF,0x82,0x14, ++0xFF,0x1F,0x02,0x3C, ++0x01,0x00,0x02,0x24, ++0x29,0x00,0xA2,0x10, ++0x0F,0x10,0x02,0x3C, ++0x02,0x00,0xA2,0x28, ++0x1F,0x00,0x40,0x14, ++0x00,0x00,0x00,0x00, ++0x28,0x00,0xA3,0x10, ++0x00,0x00,0x00,0x00, ++0xE5,0xFF,0xA4,0x14, ++0x00,0x00,0x00,0x00, ++0x0F,0x10,0x02,0x3C, ++0x08,0x00,0xE0,0x03, ++0x00,0xF0,0x42,0x34, ++0xE1,0xFF,0x82,0x14, ++0xFF,0x1F,0x02,0x3C, ++0x01,0x00,0x02,0x24, ++0x1C,0x00,0xA2,0x10, ++0x0F,0x00,0x02,0x3C, ++0x02,0x00,0xA2,0x28, ++0x0B,0x00,0x40,0x14, ++0x00,0x00,0x00,0x00, ++0x1C,0x00,0xA3,0x10, ++0x00,0x00,0x00,0x00, ++0xD6,0xFF,0xA4,0x14, ++0x00,0x00,0x00,0x00, ++0x0F,0x00,0x02,0x3C, ++0x08,0x00,0xE0,0x03, ++0x00,0xF0,0x42,0x34, ++0x0F,0x10,0x02,0x3C, ++0x08,0x00,0xE0,0x03, ++0x00,0x80,0x42,0x34, ++0xCE,0xFF,0xA0,0x14, ++0x00,0x00,0x00,0x00, ++0x0F,0x00,0x02,0x3C, ++0x08,0x00,0xE0,0x03, ++0x15,0xF0,0x42,0x34, ++0xC9,0xFF,0xA0,0x14, ++0x00,0x00,0x00,0x00, ++0x0F,0x10,0x02,0x3C, ++0x08,0x00,0xE0,0x03, ++0x15,0xF0,0x42,0x34, ++0x08,0x00,0xE0,0x03, ++0x00,0xF0,0x42,0x34, ++0x08,0x00,0xE0,0x03, ++0x10,0xF0,0x42,0x34, ++0x08,0x00,0xE0,0x03, ++0x10,0xF0,0x42,0x34, ++0x0F,0x10,0x02,0x3C, ++0x08,0x00,0xE0,0x03, ++0x05,0xF0,0x42,0x34, ++0x0F,0x00,0x02,0x3C, ++0x08,0x00,0xE0,0x03, ++0x05,0xF0,0x42,0x34, ++0xC0,0x40,0x04,0x00, ++0x21,0x18,0x04,0x01, ++0x80,0x18,0x03,0x00, ++0x21,0x18,0x64,0x00, ++0x02,0x80,0x02,0x3C, ++0x80,0x18,0x03,0x00, ++0x30,0x1F,0x42,0x24, ++0x21,0x18,0x62,0x00, ++0x18,0x24,0x66,0x8C, ++0x21,0x38,0x60,0x00, ++0x1E,0x24,0x60,0xA0, ++0x1F,0x24,0x60,0xA0, ++0x1C,0x00,0x05,0x24, ++0xDA,0x24,0x00,0x08, ++0x01,0x00,0x03,0x24, ++0x08,0x00,0xA0,0x04, ++0x21,0x10,0x04,0x01, ++0x04,0x10,0xA3,0x00, ++0x24,0x10,0xC2,0x00, ++0xFB,0xFF,0x40,0x10, ++0xFF,0xFF,0xA5,0x24, ++0x01,0x00,0xA5,0x24, ++0x1E,0x24,0xE5,0xA0, ++0x21,0x10,0x04,0x01, ++0x80,0x10,0x02,0x00, ++0x21,0x10,0x44,0x00, ++0x02,0x80,0x03,0x3C, ++0x80,0x10,0x02,0x00, ++0x30,0x1F,0x63,0x24, ++0x21,0x18,0x43,0x00, ++0x18,0x24,0x66,0x8C, ++0x21,0x28,0x00,0x00, ++0xEE,0x24,0x00,0x08, ++0x01,0x00,0x07,0x24, ++0x1D,0x00,0xA2,0x28, ++0x08,0x00,0x40,0x10, ++0x00,0x00,0x00,0x00, ++0x04,0x10,0xA7,0x00, ++0x24,0x10,0xC2,0x00, ++0xFA,0xFF,0x40,0x10, ++0x01,0x00,0xA5,0x24, ++0xFF,0xFF,0xA5,0x24, ++0x08,0x00,0xE0,0x03, ++0x1F,0x24,0x65,0xA0, ++0x08,0x00,0xE0,0x03, ++0x00,0x00,0x00,0x00, ++0xD8,0xFF,0xBD,0x27, ++0x02,0x80,0x02,0x3C, ++0x20,0x00,0xB4,0xAF, ++0x1C,0x00,0xB3,0xAF, ++0x14,0x00,0xB1,0xAF, ++0x10,0x00,0xB0,0xAF, ++0x21,0x88,0x00,0x00, ++0x30,0x1F,0x50,0x24, ++0xFF,0xF1,0x14,0x24, ++0x25,0xB0,0x13,0x3C, ++0x24,0x00,0xBF,0xAF, ++0x08,0x25,0x00,0x08, ++0x18,0x00,0xB2,0xAF, ++0x01,0x00,0x31,0x26, ++0x20,0x00,0x22,0x2E, ++0x2A,0x00,0x40,0x10, ++0x94,0x00,0x10,0x26, ++0x1C,0x24,0x06,0x8E, ++0x01,0x00,0x03,0x24, ++0x02,0x13,0x06,0x00, ++0x01,0x00,0x45,0x30, ++0xF7,0xFF,0xA3,0x14, ++0x42,0x1A,0x06,0x00, ++0x0C,0x24,0x02,0x8E, ++0x07,0x00,0x64,0x30, ++0x02,0x11,0x02,0x00, ++0x7F,0x00,0x43,0x30, ++0x27,0x00,0x85,0x10, ++0x07,0x00,0xD2,0x30, ++0x02,0x00,0x82,0x28, ++0x31,0x00,0x40,0x14, ++0x02,0x00,0x02,0x24, ++0x28,0x00,0x82,0x10, ++0x03,0x00,0x02,0x24, ++0x31,0x00,0x82,0x10, ++0x1A,0x00,0x62,0x2C, ++0x1C,0x24,0x02,0x8E, ++0x04,0x00,0x43,0x2E, ++0x42,0x12,0x02,0x00, ++0x0A,0x00,0x60,0x10, ++0x07,0x00,0x44,0x30, ++0x6E,0x24,0x00,0x0C, ++0x21,0x28,0x40,0x02, ++0x80,0x18,0x12,0x00, ++0x21,0x18,0x73,0x00, ++0x14,0x24,0x04,0x8E, ++0x84,0x01,0x65,0x8C, ++0x24,0x20,0x82,0x00, ++0x24,0x28,0xA4,0x00, ++0x18,0x24,0x05,0xAE, ++0xC9,0x24,0x00,0x0C, ++0x21,0x20,0x20,0x02, ++0x21,0x10,0x33,0x02, ++0x01,0x00,0x31,0x26, ++0x60,0x01,0x43,0x90, ++0x20,0x00,0x22,0x2E, ++0xD8,0xFF,0x40,0x14, ++0x94,0x00,0x10,0x26, ++0x24,0x00,0xBF,0x8F, ++0x20,0x00,0xB4,0x8F, ++0x1C,0x00,0xB3,0x8F, ++0x18,0x00,0xB2,0x8F, ++0x14,0x00,0xB1,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x21,0x10,0x00,0x00, ++0x08,0x00,0xE0,0x03, ++0x28,0x00,0xBD,0x27, ++0x32,0x00,0x62,0x2C, ++0xDF,0xFF,0x40,0x10, ++0x24,0x10,0xD4,0x00, ++0x00,0x04,0x42,0x34, ++0x1B,0x25,0x00,0x08, ++0x1C,0x24,0x02,0xAE, ++0x38,0x00,0x62,0x2C, ++0x0D,0x00,0x40,0x14, ++0x14,0x00,0x62,0x2C, ++0x24,0x10,0xD4,0x00, ++0x00,0x02,0x42,0x34, ++0x1B,0x25,0x00,0x08, ++0x1C,0x24,0x02,0xAE, ++0xD3,0xFF,0x80,0x14, ++0x24,0x10,0xD4,0x00, ++0x1B,0x25,0x00,0x08, ++0x1C,0x24,0x02,0xAE, ++0xCF,0xFF,0x40,0x14, ++0x24,0x10,0xD4,0x00, ++0x3E,0x25,0x00,0x08, ++0x00,0x04,0x42,0x34, ++0xCB,0xFF,0x40,0x10, ++0x24,0x10,0xD4,0x00, ++0x00,0x06,0x42,0x34, ++0x1B,0x25,0x00,0x08, ++0x1C,0x24,0x02,0xAE, ++0x08,0x00,0xE0,0x03, ++0x00,0x00,0x00,0x00, ++0xE0,0xFF,0xBD,0x27, ++0x10,0x00,0xB0,0xAF, ++0xC0,0x80,0x04,0x00, ++0x21,0x80,0x04,0x02, ++0x80,0x80,0x10,0x00, ++0x21,0x80,0x04,0x02, ++0x02,0x80,0x02,0x3C, ++0x30,0x1F,0x42,0x24, ++0x80,0x80,0x10,0x00, ++0x18,0x00,0xBF,0xAF, ++0x14,0x00,0xB1,0xAF, ++0x21,0x80,0x02,0x02, ++0x1C,0x24,0x03,0x8E, ++0x25,0xB0,0x02,0x3C, ++0x80,0x01,0x45,0x34, ++0x07,0x00,0x63,0x30, ++0x80,0x18,0x03,0x00, ++0x21,0x18,0x62,0x00, ++0x00,0x00,0xA6,0x90, ++0x14,0x24,0x05,0x8E, ++0x84,0x01,0x62,0x8C, ++0x21,0x88,0x80,0x00, ++0x24,0x10,0x45,0x00, ++0xC9,0x24,0x00,0x0C, ++0x18,0x24,0x02,0xAE, ++0x1E,0x24,0x04,0x92, ++0xFF,0x00,0x25,0x32, ++0x18,0x00,0xBF,0x8F, ++0x14,0x00,0xB1,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x57,0x24,0x00,0x08, ++0x20,0x00,0xBD,0x27, ++0xFF,0xFF,0x84,0x30, ++0x00,0x02,0x82,0x30, ++0x07,0x00,0x03,0x24, ++0x0D,0x00,0x40,0x14, ++0x0B,0x00,0x84,0x30, ++0x0C,0x00,0x82,0x2C, ++0x0A,0x00,0x40,0x10, ++0x00,0x00,0x00,0x00, ++0x02,0x80,0x03,0x3C, ++0x80,0x10,0x04,0x00, ++0x74,0xED,0x63,0x24, ++0x21,0x10,0x43,0x00, ++0x00,0x00,0x44,0x8C, ++0x00,0x00,0x00,0x00, ++0x08,0x00,0x80,0x00, ++0x00,0x00,0x00,0x00, ++0x07,0x00,0x03,0x24, ++0x08,0x00,0xE0,0x03, ++0x21,0x10,0x60,0x00, ++0x06,0x00,0x03,0x24, ++0x08,0x00,0xE0,0x03, ++0x21,0x10,0x60,0x00, ++0x05,0x00,0x03,0x24, ++0x08,0x00,0xE0,0x03, ++0x21,0x10,0x60,0x00, ++0x04,0x00,0x03,0x24, ++0x08,0x00,0xE0,0x03, ++0x21,0x10,0x60,0x00, ++0x03,0x00,0x03,0x24, ++0x08,0x00,0xE0,0x03, ++0x21,0x10,0x60,0x00, ++0x02,0x00,0x03,0x24, ++0x08,0x00,0xE0,0x03, ++0x21,0x10,0x60,0x00, ++0x01,0x00,0x03,0x24, ++0x08,0x00,0xE0,0x03, ++0x21,0x10,0x60,0x00, ++0x21,0x18,0x00,0x00, ++0x08,0x00,0xE0,0x03, ++0x21,0x10,0x60,0x00, ++0xA8,0xFF,0xBD,0x27, ++0x02,0x80,0x02,0x3C, ++0x50,0x00,0xBE,0xAF, ++0x4C,0x00,0xB7,0xAF, ++0x48,0x00,0xB6,0xAF, ++0x44,0x00,0xB5,0xAF, ++0x3C,0x00,0xB3,0xAF, ++0x38,0x00,0xB2,0xAF, ++0x54,0x00,0xBF,0xAF, ++0x40,0x00,0xB4,0xAF, ++0x34,0x00,0xB1,0xAF, ++0x30,0x00,0xB0,0xAF, ++0xA4,0xED,0x42,0x24, ++0x00,0x00,0x54,0x8C, ++0x21,0x98,0x00,0x00, ++0x21,0xA8,0x00,0x00, ++0x21,0xB0,0x00,0x00, ++0x10,0x00,0xA0,0xAF, ++0x21,0xB8,0x00,0x00, ++0x14,0x00,0xA0,0xAF, ++0x21,0xF0,0x00,0x00, ++0x18,0x00,0xA0,0xAF, ++0x1C,0x00,0xA0,0xAF, ++0x20,0x00,0xA0,0xAF, ++0x24,0x00,0xA0,0xAF, ++0x28,0x00,0xA0,0xAF, ++0x2C,0x00,0xA0,0xAF, ++0x21,0x90,0x80,0x02, ++0x1C,0x24,0x42,0x8E, ++0x00,0x00,0x00,0x00, ++0x02,0x13,0x02,0x00, ++0x01,0x00,0x42,0x30, ++0x68,0x00,0x40,0x10, ++0x25,0xB0,0x02,0x3C, ++0x21,0x10,0x62,0x02, ++0x60,0x01,0x44,0x90, ++0x04,0x24,0x43,0x8E, ++0x00,0x24,0x46,0x8E, ++0xFF,0x00,0x8B,0x30, ++0x02,0x80,0x04,0x3C, ++0x30,0x1F,0x84,0x24, ++0x21,0x10,0x64,0x01, ++0xE7,0x04,0x44,0x90, ++0xCA,0x04,0x45,0x90, ++0xE8,0x23,0x47,0x8E, ++0x18,0x00,0x64,0x00, ++0x12,0x18,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x18,0x00,0xC5,0x00, ++0x12,0x30,0x00,0x00, ++0x21,0x30,0xC3,0x00, ++0x2B,0x10,0xE6,0x00, ++0x02,0x01,0x40,0x14, ++0x23,0x10,0xE6,0x00, ++0xE8,0x23,0x42,0xAE, ++0x04,0x24,0x44,0x8E, ++0x00,0x24,0x47,0x8E, ++0xEC,0x23,0x48,0x8E, ++0xF0,0x23,0x45,0x8E, ++0xF8,0x23,0x46,0x8E, ++0xFC,0x23,0x43,0x8E, ++0x21,0x38,0xE4,0x00, ++0x02,0x80,0x04,0x3C, ++0x30,0x1F,0x84,0x24, ++0x21,0x10,0x64,0x01, ++0x21,0x40,0x05,0x01, ++0x21,0x30,0xC3,0x00, ++0x3E,0x05,0x42,0x90, ++0xE8,0x23,0x4A,0x8E, ++0x0C,0x00,0xE0,0x10, ++0x21,0x48,0x00,0x00, ++0x2B,0x48,0x47,0x00, ++0x0B,0x00,0x20,0x15, ++0x02,0x80,0x02,0x3C, ++0x07,0x00,0x62,0x2D, ++0x4B,0x01,0x40,0x14, ++0xC0,0x10,0x07,0x00, ++0x0C,0x00,0x02,0x24, ++0x47,0x01,0x62,0x11, ++0x0D,0x00,0x02,0x24, ++0x46,0x01,0x62,0x11, ++0xC0,0x10,0x07,0x00, ++0x6C,0x00,0x20,0x11, ++0x02,0x80,0x02,0x3C, ++0x30,0x1F,0x42,0x24, ++0x80,0x18,0x0B,0x00, ++0x21,0x18,0x62,0x00, ++0x21,0x20,0x4B,0x02, ++0x5A,0x24,0x85,0x90, ++0x60,0x05,0x62,0x8C, ++0x00,0x00,0x00,0x00, ++0x04,0x10,0xA2,0x00, ++0x2B,0x10,0x4A,0x00, ++0x61,0x00,0x40,0x10, ++0x00,0x00,0x00,0x00, ++0x78,0x24,0x42,0x8E, ++0x01,0x00,0x07,0x24, ++0x04,0x18,0x67,0x01, ++0x24,0x10,0x43,0x00, ++0xE1,0x00,0x40,0x10, ++0x1C,0x00,0x62,0x2D, ++0x21,0x28,0x4B,0x02, ++0x20,0x24,0xA6,0x90, ++0x5A,0x24,0xA2,0x90, ++0x0A,0x00,0x04,0x24, ++0xFF,0x00,0xC3,0x30, ++0x04,0x20,0x44,0x00, ++0x2A,0x18,0x64,0x00, ++0xD8,0x00,0x60,0x10, ++0x1C,0x00,0x62,0x2D, ++0x01,0x00,0xC2,0x24, ++0xFF,0x00,0x43,0x30, ++0x37,0x01,0x64,0x10, ++0x20,0x24,0xA2,0xA0, ++0x02,0x80,0x04,0x3C, ++0x30,0x1F,0x85,0x24, ++0x80,0x10,0x0B,0x00, ++0x21,0x10,0x45,0x00, ++0xD4,0x05,0x44,0x8C, ++0x60,0x05,0x43,0x8C, ++0x18,0x00,0xA2,0x8F, ++0x00,0x00,0x00,0x00, ++0x21,0x30,0x45,0x00, ++0x40,0x10,0x04,0x00, ++0x21,0x10,0x44,0x00, ++0x21,0x18,0x62,0x00, ++0x82,0x50,0x03,0x00, ++0xE8,0x23,0xCA,0xAC, ++0x30,0x38,0xA3,0x8C, ++0xFF,0xFF,0x02,0x34, ++0x03,0x00,0x62,0x10, ++0x21,0x20,0x60,0x01, ++0x57,0x24,0x00,0x0C, ++0xFF,0x00,0x65,0x32, ++0x9E,0x00,0x60,0x12, ++0x02,0x80,0x03,0x3C, ++0x02,0x80,0x04,0x3C, ++0x30,0x1F,0x82,0x24, ++0x21,0x10,0xA2,0x02, ++0xFC,0x23,0x40,0xAC, ++0x00,0x24,0x40,0xAC, ++0x04,0x24,0x40,0xAC, ++0xEC,0x23,0x40,0xAC, ++0xF0,0x23,0x40,0xAC, ++0xF4,0x23,0x40,0xAC, ++0xF8,0x23,0x40,0xAC, ++0x2C,0x00,0xA2,0x8F, ++0x28,0x00,0xA4,0x8F, ++0x01,0x00,0x73,0x26, ++0x94,0x00,0x42,0x24, ++0x94,0x00,0x84,0x24, ++0x2C,0x00,0xA2,0xAF, ++0x28,0x00,0xA4,0xAF, ++0x24,0x00,0xA2,0x8F, ++0x20,0x00,0xA4,0x8F, ++0x20,0x00,0x63,0x2A, ++0x94,0x00,0x42,0x24, ++0x94,0x00,0x84,0x24, ++0x24,0x00,0xA2,0xAF, ++0x20,0x00,0xA4,0xAF, ++0x1C,0x00,0xA2,0x8F, ++0x18,0x00,0xA4,0x8F, ++0x94,0x00,0x52,0x26, ++0x94,0x00,0x42,0x24, ++0x94,0x00,0x84,0x24, ++0x1C,0x00,0xA2,0xAF, ++0x18,0x00,0xA4,0xAF, ++0x14,0x00,0xA2,0x8F, ++0x10,0x00,0xA4,0x8F, ++0x94,0x00,0xDE,0x27, ++0x94,0x00,0x42,0x24, ++0x94,0x00,0x84,0x24, ++0x14,0x00,0xA2,0xAF, ++0x94,0x00,0xF7,0x26, ++0x10,0x00,0xA4,0xAF, ++0x94,0x00,0x94,0x26, ++0x94,0x00,0xD6,0x26, ++0x69,0xFF,0x60,0x14, ++0x94,0x00,0xB5,0x26, ++0x54,0x00,0xBF,0x8F, ++0x50,0x00,0xBE,0x8F, ++0x4C,0x00,0xB7,0x8F, ++0x48,0x00,0xB6,0x8F, ++0x44,0x00,0xB5,0x8F, ++0x40,0x00,0xB4,0x8F, ++0x3C,0x00,0xB3,0x8F, ++0x38,0x00,0xB2,0x8F, ++0x34,0x00,0xB1,0x8F, ++0x30,0x00,0xB0,0x8F, ++0x08,0x00,0xE0,0x03, ++0x58,0x00,0xBD,0x27, ++0x79,0x00,0xE0,0x10, ++0x00,0x00,0x00,0x00, ++0x79,0x00,0x20,0x15, ++0x02,0x80,0x03,0x3C, ++0x40,0x10,0x07,0x00, ++0x21,0x10,0x47,0x00, ++0x82,0x10,0x02,0x00, ++0x2B,0x10,0x46,0x00, ++0xBE,0xFF,0x40,0x10, ++0x02,0x80,0x04,0x3C, ++0x30,0x1F,0x88,0x24, ++0x21,0x20,0xC8,0x03, ++0x21,0x30,0x8B,0x00, ++0x78,0x24,0x83,0x8C, ++0x01,0x00,0x05,0x24, ++0x04,0x10,0x65,0x01, ++0x3D,0x24,0xC7,0x90, ++0x27,0x10,0x02,0x00, ++0x24,0x18,0x62,0x00, ++0x78,0x24,0x83,0xAC, ++0x09,0x00,0xE5,0x10, ++0x20,0x24,0xC0,0xA0, ++0x14,0x00,0xA2,0x8F, ++0x21,0x38,0x00,0x00, ++0x21,0x20,0x48,0x00, ++0x21,0x18,0x87,0x00, ++0x01,0x00,0xE7,0x24, ++0x1D,0x00,0xE2,0x28, ++0xFC,0xFF,0x40,0x14, ++0x5A,0x24,0x60,0xA0, ++0x02,0x80,0x04,0x3C, ++0x30,0x1F,0x83,0x24, ++0x21,0x10,0xE3,0x02, ++0x21,0x10,0x4B,0x00, ++0x3D,0x24,0x40,0xA0, ++0x21,0x50,0x60,0x00, ++0x02,0x80,0x02,0x3C, ++0x02,0x80,0x03,0x3C, ++0x78,0xE8,0x49,0x24, ++0x04,0xE8,0x68,0x24, ++0x21,0x38,0x00,0x00, ++0x80,0x18,0x07,0x00, ++0x21,0x10,0x69,0x00, ++0x21,0x20,0x68,0x00, ++0x00,0x00,0x46,0x8C, ++0x00,0x00,0x85,0x8C, ++0x01,0x00,0xE7,0x24, ++0x21,0x18,0x6A,0x00, ++0x1D,0x00,0xE2,0x28, ++0x60,0x05,0x65,0xAC, ++0xF6,0xFF,0x40,0x14, ++0xD4,0x05,0x66,0xAC, ++0x15,0x00,0x60,0x11, ++0x02,0x80,0x04,0x3C, ++0x1F,0x24,0x82,0x92, ++0xFF,0xFF,0x67,0x25, ++0x2A,0x10,0xE2,0x00, ++0x10,0x00,0x40,0x14, ++0x02,0x80,0x03,0x3C, ++0x10,0x00,0xA4,0x8F, ++0x30,0x1F,0x62,0x24, ++0x21,0x10,0x82,0x00, ++0x1F,0x24,0x45,0x90, ++0x18,0x24,0x44,0x8C, ++0x01,0x00,0x06,0x24, ++0x04,0x18,0xE6,0x00, ++0x24,0x10,0x83,0x00, ++0xB9,0x00,0x43,0x10, ++0x00,0x00,0x00,0x00, ++0xFF,0xFF,0xE7,0x24, ++0x2A,0x10,0xE5,0x00, ++0xFA,0xFF,0x40,0x10, ++0x04,0x18,0xE6,0x00, ++0x02,0x80,0x04,0x3C, ++0x30,0x1F,0x83,0x24, ++0x80,0x10,0x0B,0x00, ++0x21,0x10,0x43,0x00, ++0xD4,0x05,0x45,0x8C, ++0x60,0x05,0x44,0x8C, ++0x02,0x80,0x03,0x3C, ++0x40,0x10,0x05,0x00, ++0xDE,0x5D,0x66,0x90, ++0x21,0x10,0x45,0x00, ++0x21,0x20,0x82,0x00, ++0x22,0x00,0x02,0x24, ++0x9D,0x00,0xC2,0x10, ++0x82,0x50,0x04,0x00, ++0x78,0x24,0x83,0x8E, ++0x01,0x00,0x02,0x24, ++0x04,0x10,0x62,0x01, ++0x25,0x18,0x62,0x00, ++0x78,0x24,0x83,0xAE, ++0x02,0x80,0x02,0x3C, ++0x30,0x1F,0x43,0x24, ++0x21,0x10,0xC3,0x02, ++0xE8,0x23,0x4A,0xAC, ++0x30,0x38,0x64,0x8C, ++0xFF,0xFF,0x02,0x34, ++0x62,0xFF,0x82,0x14, ++0x21,0x20,0x60,0x01, ++0x64,0xFF,0x60,0x16, ++0x02,0x80,0x03,0x3C, ++0x30,0x1F,0x70,0x24, ++0xF0,0x23,0x05,0x96, ++0xEC,0x23,0x02,0x96, ++0x25,0xB0,0x11,0x3C, ++0x00,0x2C,0x05,0x00, ++0x21,0x28,0x45,0x00, ++0xB5,0x59,0x00,0x0C, ++0x68,0x0C,0x24,0x36, ++0xFC,0x23,0x02,0x8E, ++0xF8,0x23,0x05,0x8E, ++0xF4,0x23,0x03,0x96, ++0x6C,0x0C,0x24,0x36, ++0x21,0x28,0xA2,0x00, ++0x00,0x2C,0x05,0x00, ++0xB5,0x59,0x00,0x0C, ++0x21,0x28,0x65,0x00, ++0x28,0x26,0x00,0x08, ++0x02,0x80,0x04,0x3C, ++0xD6,0x25,0x00,0x08, ++0xE8,0x23,0x40,0xAE, ++0x4C,0xFF,0x20,0x11, ++0x02,0x80,0x03,0x3C, ++0x30,0x1F,0x62,0x24, ++0x80,0x18,0x0B,0x00, ++0x21,0x18,0x62,0x00, ++0xD4,0x05,0x64,0x8C, ++0x00,0x00,0x00,0x00, ++0x2B,0x20,0x44,0x01, ++0x44,0xFF,0x80,0x10, ++0x02,0x80,0x04,0x3C, ++0x69,0x26,0x00,0x08, ++0x30,0x1F,0x88,0x24, ++0x2D,0xFF,0x40,0x10, ++0x02,0x80,0x04,0x3C, ++0x21,0x20,0x4B,0x02, ++0x3D,0x24,0x83,0x90, ++0x01,0x00,0x02,0x24, ++0x53,0x00,0x62,0x10, ++0x02,0x80,0x02,0x3C, ++0x2C,0x00,0xA3,0x8F, ++0x30,0x1F,0x42,0x24, ++0x21,0x38,0x00,0x00, ++0x21,0x20,0x62,0x00, ++0x21,0x18,0x87,0x00, ++0x01,0x00,0xE7,0x24, ++0x1D,0x00,0xE2,0x28, ++0xFC,0xFF,0x40,0x14, ++0x5A,0x24,0x60,0xA0, ++0x28,0x00,0xA4,0x8F, ++0x02,0x80,0x03,0x3C, ++0x30,0x1F,0x65,0x24, ++0x21,0x30,0x85,0x00, ++0x78,0x24,0xC2,0x8C, ++0x01,0x00,0x03,0x24, ++0x04,0x18,0x63,0x01, ++0x27,0x18,0x03,0x00, ++0x21,0x20,0xCB,0x00, ++0x24,0x10,0x43,0x00, ++0x3D,0x24,0x80,0xA0, ++0x78,0x24,0xC2,0xAC, ++0x12,0x00,0x60,0x15, ++0x20,0x24,0x80,0xA0, ++0x1E,0x24,0xC2,0x90, ++0x00,0x00,0x00,0x00, ++0x0E,0x00,0x40,0x10, ++0x01,0x00,0x07,0x24, ++0x24,0x00,0xA3,0x8F, ++0x01,0x00,0x06,0x24, ++0x21,0x10,0x65,0x00, ++0x1E,0x24,0x44,0x90, ++0x18,0x24,0x45,0x8C, ++0x04,0x18,0xE6,0x00, ++0x24,0x10,0xA3,0x00, ++0x4B,0x00,0x43,0x10, ++0x00,0x00,0x00,0x00, ++0x01,0x00,0xE7,0x24, ++0x2A,0x10,0x87,0x00, ++0xFA,0xFF,0x40,0x10, ++0x04,0x18,0xE6,0x00, ++0x02,0x80,0x02,0x3C, ++0x30,0x1F,0x44,0x24, ++0x20,0x00,0xA2,0x8F, ++0x01,0x00,0x67,0x25, ++0x21,0x18,0x44,0x00, ++0x1E,0x24,0x62,0x90, ++0x00,0x00,0x00,0x00, ++0x2A,0x10,0x47,0x00, ++0x0E,0x00,0x40,0x14, ++0x01,0x00,0x06,0x24, ++0x1C,0x00,0xA3,0x8F, ++0x00,0x00,0x00,0x00, ++0x21,0x10,0x64,0x00, ++0x1E,0x24,0x45,0x90, ++0x18,0x24,0x44,0x8C, ++0x04,0x18,0xE6,0x00, ++0x24,0x10,0x83,0x00, ++0x31,0x00,0x43,0x10, ++0x00,0x00,0x00,0x00, ++0x01,0x00,0xE7,0x24, ++0x2A,0x10,0xA7,0x00, ++0xFA,0xFF,0x40,0x10, ++0x04,0x18,0xE6,0x00, ++0x02,0x80,0x02,0x3C, ++0xDE,0x5D,0x44,0x90, ++0x22,0x00,0x03,0x24, ++0xE4,0xFE,0x83,0x14, ++0x02,0x80,0x04,0x3C, ++0xEE,0xFF,0x62,0x25, ++0xFF,0x00,0x42,0x30, ++0x02,0x00,0x42,0x2C, ++0x18,0x00,0x03,0x24, ++0x12,0x26,0x00,0x08, ++0x0B,0x58,0x62,0x00, ++0xC0,0x10,0x07,0x00, ++0x23,0x10,0x47,0x00, ++0xC2,0x10,0x02,0x00, ++0x2B,0x10,0x48,0x00, ++0xC4,0xFE,0x40,0x14, ++0x00,0x00,0x00,0x00, ++0xF1,0x25,0x00,0x08, ++0x00,0x00,0x00,0x00, ++0x18,0x00,0x62,0x2D, ++0x0A,0x00,0x40,0x14, ++0x05,0x00,0x62,0x2D, ++0x5A,0x24,0x83,0x90, ++0x00,0x00,0x00,0x00, ++0x05,0x00,0x62,0x2C, ++0xB0,0xFF,0x40,0x10, ++0x01,0x00,0x62,0x24, ++0xF4,0x26,0x00,0x08, ++0x5A,0x24,0x82,0xA0, ++0x11,0x26,0x00,0x08, ++0x3D,0x24,0xA7,0xA0, ++0x04,0x00,0x40,0x10, ++0x00,0x00,0x00,0x00, ++0x5A,0x24,0x83,0x90, ++0x43,0x27,0x00,0x08, ++0x03,0x00,0x62,0x2C, ++0x5A,0x24,0x83,0x90, ++0x43,0x27,0x00,0x08, ++0x04,0x00,0x62,0x2C, ++0x13,0x00,0x02,0x24, ++0x62,0xFF,0x62,0x15, ++0x02,0x80,0x02,0x3C, ++0xBC,0x26,0x00,0x08, ++0x30,0x1F,0x43,0x24, ++0xFF,0x00,0xEB,0x30, ++0x2B,0x27,0x00,0x08, ++0x02,0x80,0x02,0x3C, ++0x13,0x27,0x00,0x08, ++0xFF,0x00,0xEB,0x30, ++0xA7,0x26,0x00,0x08, ++0xFF,0x00,0xEB,0x30, ++0xD8,0xFF,0xBD,0x27, ++0x02,0x80,0x02,0x3C, ++0x14,0x00,0xB1,0xAF, ++0x24,0x00,0xBF,0xAF, ++0x20,0x00,0xB4,0xAF, ++0x1C,0x00,0xB3,0xAF, ++0x18,0x00,0xB2,0xAF, ++0x10,0x00,0xB0,0xAF, ++0x30,0x1F,0x45,0x24, ++0xA9,0x37,0xA4,0x90, ++0xA4,0x37,0xA3,0x8C, ++0xA0,0x37,0xA2,0x8C, ++0x21,0x88,0x64,0x00, ++0x2B,0x10,0x22,0x02, ++0x60,0x00,0x40,0x10, ++0x21,0x80,0xA0,0x00, ++0x02,0x80,0x14,0x3C, ++0x21,0x98,0xA0,0x00, ++0x76,0x27,0x00,0x08, ++0x21,0x90,0xA0,0x00, ++0xA0,0x37,0x42,0x8E, ++0x10,0x00,0x31,0x26, ++0x2B,0x10,0x22,0x02, ++0x57,0x00,0x40,0x10, ++0x21,0x80,0x40,0x02, ++0xA9,0x37,0x02,0x92, ++0xFF,0xFF,0x23,0x32, ++0x02,0x80,0x05,0x3C, ++0x10,0x00,0x42,0x24, ++0x25,0x28,0x65,0x00, ++0x98,0x55,0x84,0x26, ++0x10,0x00,0x06,0x24, ++0x10,0x52,0x00,0x0C, ++0xA9,0x37,0x02,0xA2, ++0x6C,0x36,0x06,0x8E, ++0x00,0x00,0x00,0x00, ++0x42,0x24,0x06,0x00, ++0x1F,0x00,0x84,0x30, ++0xC0,0x10,0x04,0x00, ++0x21,0x10,0x44,0x00, ++0x80,0x10,0x02,0x00, ++0x21,0x10,0x44,0x00, ++0x80,0x10,0x02,0x00, ++0x21,0x38,0x50,0x00, ++0x1C,0x24,0xE3,0x8C, ++0x00,0x00,0x00,0x00, ++0x02,0x1B,0x03,0x00, ++0x01,0x00,0x63,0x30, ++0xE3,0xFF,0x60,0x10, ++0x25,0xB0,0x02,0x3C, ++0x68,0x36,0x05,0x8E, ++0x21,0x10,0x82,0x00, ++0x60,0x01,0x44,0x90, ++0x82,0x1D,0x05,0x00, ++0x3F,0x00,0x63,0x30, ++0x04,0x00,0x0A,0x24, ++0x05,0x00,0x62,0x28, ++0x21,0x40,0x40,0x01, ++0x0B,0x40,0x62,0x00, ++0x07,0x00,0xA0,0x04, ++0xFF,0x00,0x89,0x30, ++0x08,0x24,0xE2,0x8C, ++0x04,0x00,0x08,0x24, ++0x01,0x00,0x42,0x24, ++0x08,0x24,0xE2,0xAC, ++0x6C,0x36,0x66,0x8E, ++0x00,0x00,0x00,0x00, ++0x02,0x13,0x06,0x00, ++0x1F,0x00,0x42,0x30, ++0x08,0x00,0x42,0x28, ++0xCD,0xFF,0x40,0x10, ++0x00,0x00,0x00,0x00, ++0x68,0x36,0x62,0x8E, ++0x00,0x00,0x00,0x00, ++0x3F,0x00,0x42,0x30, ++0xC8,0xFF,0x49,0x14, ++0x00,0x00,0x00,0x00, ++0x29,0x00,0x00,0x11, ++0x01,0x00,0x02,0x24, ++0x2E,0x00,0x02,0x11, ++0x02,0x00,0x02,0x24, ++0x33,0x00,0x02,0x11, ++0x03,0x00,0x02,0x24, ++0x38,0x00,0x02,0x11, ++0x00,0x00,0x00,0x00, ++0x3B,0x00,0x0A,0x11, ++0x00,0x00,0x00,0x00, ++0x0C,0x24,0xE2,0x8C, ++0x21,0x18,0x33,0x01, ++0x04,0x05,0x64,0x90, ++0x02,0x11,0x02,0x00, ++0x2B,0x10,0x44,0x00, ++0x3E,0x00,0x40,0x14, ++0x00,0x00,0x00,0x00, ++0x00,0x24,0xE3,0x8C, ++0x80,0x10,0x09,0x00, ++0x21,0x10,0x49,0x00, ++0x01,0x00,0x63,0x24, ++0x21,0x10,0x53,0x00, ++0x00,0x24,0xE3,0xAC, ++0x21,0x10,0x48,0x00, ++0xA8,0x03,0x44,0x90, ++0xE8,0x23,0xE3,0x8C, ++0x00,0x00,0x00,0x00, ++0x21,0x18,0x64,0x00, ++0xE8,0x23,0xE3,0xAC, ++0xA0,0x37,0x42,0x8E, ++0x10,0x00,0x31,0x26, ++0x2B,0x10,0x22,0x02, ++0xAB,0xFF,0x40,0x14, ++0x21,0x80,0x40,0x02, ++0x24,0x00,0xBF,0x8F, ++0x20,0x00,0xB4,0x8F, ++0x1C,0x00,0xB3,0x8F, ++0x18,0x00,0xB2,0x8F, ++0x14,0x00,0xB1,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x08,0x00,0xE0,0x03, ++0x28,0x00,0xBD,0x27, ++0xEC,0x23,0xE2,0x8C, ++0x00,0x00,0x00,0x00, ++0x01,0x00,0x42,0x24, ++0xEC,0x23,0xE2,0xAC, ++0x01,0x00,0x02,0x24, ++0xD4,0xFF,0x02,0x15, ++0x02,0x00,0x02,0x24, ++0xF0,0x23,0xE2,0x8C, ++0x00,0x00,0x00,0x00, ++0x01,0x00,0x42,0x24, ++0xF0,0x23,0xE2,0xAC, ++0x02,0x00,0x02,0x24, ++0xCF,0xFF,0x02,0x15, ++0x03,0x00,0x02,0x24, ++0xF4,0x23,0xE2,0x8C, ++0x00,0x00,0x00,0x00, ++0x01,0x00,0x42,0x24, ++0xF4,0x23,0xE2,0xAC, ++0x03,0x00,0x02,0x24, ++0xCA,0xFF,0x02,0x15, ++0x00,0x00,0x00,0x00, ++0xF8,0x23,0xE2,0x8C, ++0x00,0x00,0x00,0x00, ++0x01,0x00,0x42,0x24, ++0xC7,0xFF,0x0A,0x15, ++0xF8,0x23,0xE2,0xAC, ++0xFC,0x23,0xE2,0x8C, ++0x21,0x18,0x33,0x01, ++0x01,0x00,0x42,0x24, ++0xFC,0x23,0xE2,0xAC, ++0x0C,0x24,0xE2,0x8C, ++0x04,0x05,0x64,0x90, ++0x02,0x11,0x02,0x00, ++0x2B,0x10,0x44,0x00, ++0xC4,0xFF,0x40,0x10, ++0x00,0x00,0x00,0x00, ++0x04,0x24,0xE3,0x8C, ++0x80,0x10,0x09,0x00, ++0x21,0x10,0x49,0x00, ++0x01,0x00,0x63,0x24, ++0x21,0x10,0x53,0x00, ++0x04,0x24,0xE3,0xAC, ++0x21,0x10,0x48,0x00, ++0x39,0x04,0x44,0x90, ++0xE8,0x23,0xE3,0x8C, ++0x00,0x00,0x00,0x00, ++0x21,0x18,0x64,0x00, ++0xC7,0x27,0x00,0x08, ++0xE8,0x23,0xE3,0xAC, ++0x23,0x10,0xA4,0x00, ++0x2B,0x18,0xA4,0x00, ++0x23,0x20,0x85,0x00, ++0x08,0x00,0xE0,0x03, ++0x0B,0x10,0x83,0x00, ++0x20,0xFF,0xBD,0x27, ++0xCC,0x00,0xB5,0xAF, ++0xDC,0x00,0xBF,0xAF, ++0xD8,0x00,0xBE,0xAF, ++0xD4,0x00,0xB7,0xAF, ++0xD0,0x00,0xB6,0xAF, ++0xC8,0x00,0xB4,0xAF, ++0xC4,0x00,0xB3,0xAF, ++0xC0,0x00,0xB2,0xAF, ++0xBC,0x00,0xB1,0xAF, ++0xB8,0x00,0xB0,0xAF, ++0x21,0xA8,0x00,0x00, ++0x40,0x11,0x15,0x00, ++0x10,0x00,0xA3,0x27, ++0x21,0x10,0x43,0x00, ++0x07,0x00,0x16,0x24, ++0xFF,0xFF,0xD6,0x26, ++0x00,0x00,0x40,0xAC, ++0xFD,0xFF,0xC1,0x06, ++0x04,0x00,0x42,0x24, ++0x01,0x00,0xB5,0x26, ++0x03,0x00,0xA2,0x2E, ++0xF6,0xFF,0x40,0x14, ++0x40,0x11,0x15,0x00, ++0x25,0xB0,0x10,0x3C, ++0xC4,0x02,0x02,0x36, ++0x00,0x00,0x40,0xAC, ++0x04,0x00,0x03,0x36, ++0x00,0x00,0x62,0x8C, ++0x04,0x0C,0x03,0x36, ++0x00,0x00,0x63,0x8C, ++0x08,0x0C,0x04,0x36, ++0x0F,0x00,0x11,0x3C, ++0xAC,0x00,0xA3,0xAF, ++0x00,0x00,0x84,0x8C, ++0x24,0x10,0x51,0x00, ++0x02,0xF4,0x02,0x00, ++0xB0,0x00,0xA4,0xAF, ++0x00,0x60,0x12,0x40, ++0x01,0x00,0x41,0x36, ++0x01,0x00,0x21,0x38, ++0x00,0x60,0x81,0x40, ++0x21,0x20,0x00,0x00, ++0x8A,0x47,0x00,0x0C, ++0xFF,0xFF,0x25,0x36, ++0x70,0x00,0xA2,0xAF, ++0x00,0x60,0x92,0x40, ++0x54,0x22,0x00,0x0C, ++0x64,0x00,0x04,0x24, ++0xE6,0x44,0x00,0x0C, ++0x01,0x00,0x04,0x24, ++0x00,0x60,0x12,0x40, ++0x01,0x00,0x41,0x36, ++0x01,0x00,0x21,0x38, ++0x00,0x60,0x81,0x40, ++0x21,0x20,0x00,0x00, ++0x8A,0x47,0x00,0x0C, ++0xFF,0xFF,0x25,0x36, ++0x74,0x00,0xA2,0xAF, ++0x00,0x60,0x92,0x40, ++0x54,0x22,0x00,0x0C, ++0x64,0x00,0x04,0x24, ++0xE6,0x44,0x00,0x0C, ++0x21,0x20,0x00,0x00, ++0xE0,0x0E,0x02,0x36, ++0x21,0x20,0x40,0x00, ++0x00,0x00,0x42,0x8C, ++0xDC,0x0E,0x12,0x36, ++0x70,0x0E,0x13,0x36, ++0x78,0x00,0xA2,0xAF, ++0x00,0x00,0x42,0x8E, ++0x74,0x0E,0x14,0x36, ++0x78,0x0E,0x15,0x36, ++0x7C,0x00,0xA2,0xAF, ++0x00,0x00,0x63,0x8E, ++0x7C,0x0E,0x16,0x36, ++0x80,0x0E,0x17,0x36, ++0x80,0x00,0xA3,0xAF, ++0x00,0x00,0x82,0x8E, ++0xD4,0x0E,0x10,0x36, ++0xED,0x3F,0x11,0x3C, ++0x84,0x00,0xA2,0xAF, ++0x00,0x00,0xA3,0x8E, ++0xFB,0x92,0x25,0x36, ++0x88,0x00,0xA3,0xAF, ++0x00,0x00,0xC2,0x8E, ++0x00,0x00,0x00,0x00, ++0x8C,0x00,0xA2,0xAF, ++0x00,0x00,0xE3,0x8E, ++0x25,0xB0,0x02,0x3C, ++0x84,0x0E,0x42,0x34, ++0x90,0x00,0xA3,0xAF, ++0x00,0x00,0x42,0x8C, ++0x25,0xB0,0x03,0x3C, ++0x88,0x0E,0x63,0x34, ++0x94,0x00,0xA2,0xAF, ++0x00,0x00,0x63,0x8C, ++0x25,0xB0,0x02,0x3C, ++0x8C,0x0E,0x42,0x34, ++0x98,0x00,0xA3,0xAF, ++0x00,0x00,0x42,0x8C, ++0x25,0xB0,0x03,0x3C, ++0xD0,0x0E,0x63,0x34, ++0x9C,0x00,0xA2,0xAF, ++0x00,0x00,0x63,0x8C, ++0x00,0x00,0x00,0x00, ++0xA0,0x00,0xA3,0xAF, ++0x00,0x00,0x02,0x8E, ++0x25,0xB0,0x03,0x3C, ++0xD8,0x0E,0x63,0x34, ++0xA4,0x00,0xA2,0xAF, ++0x00,0x00,0x63,0x8C, ++0x02,0x5C,0x00,0x0C, ++0xA8,0x00,0xA3,0xAF, ++0x21,0x20,0x40,0x02, ++0x02,0x5C,0x00,0x0C, ++0xFB,0x92,0x25,0x36, ++0x21,0x20,0x60,0x02, ++0x02,0x5C,0x00,0x0C, ++0xFB,0x92,0x25,0x36, ++0x21,0x20,0x80,0x02, ++0x02,0x5C,0x00,0x0C, ++0xFB,0x92,0x25,0x36, ++0x21,0x20,0xA0,0x02, ++0x02,0x5C,0x00,0x0C, ++0xFB,0x92,0x25,0x36, ++0x21,0x20,0xC0,0x02, ++0x02,0x5C,0x00,0x0C, ++0xFB,0x92,0x25,0x36, ++0x21,0x20,0xE0,0x02, ++0x02,0x5C,0x00,0x0C, ++0xFB,0x92,0x25,0x36, ++0x02,0x80,0x02,0x3C, ++0xA8,0xED,0x42,0x24, ++0x00,0x00,0x44,0x8C, ++0xFB,0x92,0x25,0x36, ++0x02,0x5C,0x00,0x0C, ++0x25,0xB0,0x13,0x3C, ++0x02,0x80,0x03,0x3C, ++0xAC,0xED,0x63,0x24, ++0x00,0x00,0x64,0x8C, ++0xFB,0x92,0x25,0x36, ++0x02,0x5C,0x00,0x0C, ++0x21,0xB0,0x00,0x00, ++0x02,0x80,0x02,0x3C, ++0xB0,0xED,0x42,0x24, ++0x00,0x00,0x44,0x8C, ++0xFB,0x92,0x25,0x36, ++0x02,0x5C,0x00,0x0C, ++0xFF,0x03,0x14,0x3C, ++0x02,0x80,0x03,0x3C, ++0xB4,0xED,0x63,0x24, ++0x00,0x00,0x64,0x8C, ++0xFB,0x92,0x25,0x36, ++0x02,0x5C,0x00,0x0C, ++0x10,0x00,0xB7,0x27, ++0x21,0x20,0x00,0x02, ++0x02,0x5C,0x00,0x0C, ++0xFB,0x92,0x25,0x36, ++0x02,0x80,0x02,0x3C, ++0xB8,0xED,0x42,0x24, ++0x00,0x00,0x44,0x8C, ++0x02,0x5C,0x00,0x0C, ++0xFB,0x92,0x25,0x36, ++0xE4,0x28,0x00,0x08, ++0x21,0xA8,0x00,0x00, ++0x6E,0x00,0xC2,0x13, ++0x02,0x80,0x02,0x3C, ++0xAC,0x0E,0x62,0x36, ++0x94,0x0E,0x63,0x36, ++0x00,0x00,0x48,0x8C, ++0x00,0x00,0x64,0x8C, ++0xB4,0x0E,0x62,0x36, ++0x9C,0x0E,0x63,0x36, ++0x00,0x00,0x45,0x8C, ++0x00,0x00,0x66,0x8C, ++0x25,0xB0,0x03,0x3C, ++0xBC,0x0E,0x63,0x34, ++0x00,0x00,0x67,0x8C, ++0x24,0x20,0x94,0x00, ++0x00,0xD8,0x02,0x3C, ++0x24,0x10,0x02,0x01, ++0x24,0x28,0xB4,0x00, ++0x24,0x30,0xD4,0x00, ++0x24,0x38,0xF4,0x00, ++0x02,0x24,0x04,0x00, ++0x20,0x01,0x03,0x24, ++0x01,0x00,0x42,0x2C, ++0x02,0x2C,0x05,0x00, ++0x02,0x34,0x06,0x00, ++0xE8,0x00,0x83,0x10, ++0x02,0x3C,0x07,0x00, ++0xE6,0x00,0xA3,0x10, ++0x20,0x00,0x03,0x24, ++0xE4,0x00,0xC3,0x10, ++0x00,0x00,0x00,0x00, ++0xE2,0x00,0xE3,0x10, ++0x01,0x00,0x08,0x24, ++0x80,0x00,0x03,0x24, ++0x08,0x00,0x83,0x10, ++0x21,0x20,0x00,0x00, ++0x06,0x00,0xA3,0x10, ++0x21,0x20,0x00,0x00, ++0xE0,0x03,0x03,0x24, ++0x03,0x00,0xC3,0x10, ++0x00,0x00,0x00,0x00, ++0xDB,0x00,0xE3,0x10, ++0x01,0x00,0x04,0x24, ++0x05,0x00,0x40,0x10, ++0x00,0x00,0x00,0x00, ++0x03,0x00,0x00,0x11, ++0x00,0x00,0x00,0x00, ++0xD7,0x00,0x80,0x14, ++0x94,0x0E,0x63,0x36, ++0x01,0x00,0xB5,0x26, ++0x0A,0x00,0xA2,0x2E, ++0x01,0x01,0x40,0x10, ++0x00,0x00,0x00,0x00, ++0xCB,0xFF,0xC0,0x17, ++0x01,0x00,0x02,0x24, ++0xA0,0x00,0x03,0x3C, ++0x30,0x54,0x65,0x34, ++0x02,0x5C,0x00,0x0C, ++0x04,0x0C,0x64,0x36, ++0x08,0x00,0x05,0x3C, ++0xE4,0x00,0xA5,0x34, ++0x02,0x5C,0x00,0x0C, ++0x08,0x0C,0x64,0x36, ++0x28,0x0E,0x64,0x36, ++0x02,0x5C,0x00,0x0C, ++0x80,0x80,0x05,0x3C, ++0x14,0x02,0x02,0x3C, ++0x48,0x01,0x45,0x34, ++0x02,0x5C,0x00,0x0C, ++0x40,0x0E,0x64,0x36, ++0x16,0x68,0x05,0x3C, ++0xA2,0x04,0xA5,0x34, ++0x02,0x5C,0x00,0x0C, ++0x44,0x0E,0x64,0x36, ++0x4C,0x0E,0x64,0x36, ++0x02,0x5C,0x00,0x0C, ++0xD1,0x28,0x05,0x24, ++0x14,0x02,0x03,0x3C, ++0x4D,0x01,0x65,0x34, ++0x02,0x5C,0x00,0x0C, ++0x60,0x0E,0x64,0x36, ++0x16,0x28,0x05,0x3C, ++0xBA,0x08,0xA5,0x34, ++0x02,0x5C,0x00,0x0C, ++0x64,0x0E,0x64,0x36, ++0x6C,0x0E,0x64,0x36, ++0x02,0x5C,0x00,0x0C, ++0xD1,0x28,0x05,0x24, ++0x00,0xFB,0x05,0x3C, ++0x01,0x00,0xA5,0x34, ++0x02,0x5C,0x00,0x0C, ++0x48,0x0E,0x64,0x36, ++0x00,0xF8,0x05,0x3C, ++0x01,0x00,0xA5,0x34, ++0x02,0x5C,0x00,0x0C, ++0x48,0x0E,0x64,0x36, ++0x25,0x22,0x00,0x0C, ++0x03,0x00,0x04,0x24, ++0xA0,0x00,0x02,0x3C, ++0x33,0x54,0x45,0x34, ++0x02,0x5C,0x00,0x0C, ++0x04,0x0C,0x64,0x36, ++0x08,0x0C,0x64,0x36, ++0x02,0x5C,0x00,0x0C, ++0xE4,0x00,0x05,0x24, ++0x28,0x0E,0x64,0x36, ++0x02,0x5C,0x00,0x0C, ++0x21,0x28,0x00,0x00, ++0x01,0x00,0x02,0x24, ++0x96,0xFF,0xC2,0x17, ++0xAC,0x0E,0x62,0x36, ++0x02,0x80,0x02,0x3C, ++0xBC,0xED,0x42,0x24, ++0x25,0xB0,0x03,0x3C, ++0x00,0x00,0x44,0x8C, ++0x20,0x08,0x63,0x34, ++0x00,0x00,0x71,0x8C, ++0x00,0x01,0x03,0x3C, ++0x00,0x01,0x65,0x34, ++0x02,0x5C,0x00,0x0C, ++0x25,0xB0,0x12,0x3C, ++0x00,0x01,0x02,0x3C, ++0x00,0x01,0x45,0x34, ++0x02,0x5C,0x00,0x0C, ++0x28,0x08,0x44,0x36, ++0xA0,0x00,0x03,0x3C, ++0x30,0x54,0x65,0x34, ++0x02,0x5C,0x00,0x0C, ++0x04,0x0C,0x44,0x36, ++0x08,0x00,0x05,0x3C, ++0xE4,0x00,0xA5,0x34, ++0x02,0x5C,0x00,0x0C, ++0x08,0x0C,0x44,0x36, ++0x28,0x0E,0x44,0x36, ++0x02,0x5C,0x00,0x0C, ++0x80,0x80,0x05,0x3C, ++0x00,0x01,0x02,0x3C, ++0x00,0x7C,0x45,0x34, ++0x02,0x5C,0x00,0x0C, ++0x30,0x0E,0x44,0x36, ++0x00,0x01,0x03,0x3C, ++0x00,0x48,0x65,0x34, ++0x02,0x5C,0x00,0x0C, ++0x34,0x0E,0x44,0x36, ++0x00,0x10,0x02,0x3C, ++0x1F,0xDC,0x45,0x34, ++0x02,0x5C,0x00,0x0C, ++0x38,0x0E,0x44,0x36, ++0x00,0x10,0x03,0x3C, ++0x1F,0x8C,0x65,0x34, ++0x02,0x5C,0x00,0x0C, ++0x3C,0x0E,0x44,0x36, ++0x14,0x02,0x02,0x3C, ++0x02,0x01,0x45,0x34, ++0x02,0x5C,0x00,0x0C, ++0x40,0x0E,0x44,0x36, ++0x16,0x68,0x05,0x3C, ++0xC7,0x04,0xA5,0x34, ++0x02,0x5C,0x00,0x0C, ++0x44,0x0E,0x44,0x36, ++0x4C,0x0E,0x44,0x36, ++0x02,0x5C,0x00,0x0C, ++0xD1,0x28,0x05,0x24, ++0x6C,0x0E,0x44,0x36, ++0x02,0x5C,0x00,0x0C, ++0xD1,0x28,0x05,0x24, ++0x00,0x01,0x03,0x3C, ++0x00,0x7C,0x65,0x34, ++0x02,0x5C,0x00,0x0C, ++0x50,0x0E,0x44,0x36, ++0x00,0x01,0x02,0x3C, ++0x00,0x48,0x45,0x34, ++0x02,0x5C,0x00,0x0C, ++0x54,0x0E,0x44,0x36, ++0x00,0x10,0x03,0x3C, ++0x23,0xDC,0x65,0x34, ++0x02,0x5C,0x00,0x0C, ++0x58,0x0E,0x44,0x36, ++0x00,0x10,0x02,0x3C, ++0x23,0x8C,0x45,0x34, ++0x02,0x5C,0x00,0x0C, ++0x5C,0x0E,0x44,0x36, ++0x14,0x02,0x03,0x3C, ++0x02,0x01,0x65,0x34, ++0x02,0x5C,0x00,0x0C, ++0x60,0x0E,0x44,0x36, ++0x16,0x28,0x05,0x3C, ++0x07,0x0D,0xA5,0x34, ++0x02,0x5C,0x00,0x0C, ++0x64,0x0E,0x44,0x36, ++0x48,0x0E,0x44,0x36, ++0x02,0x5C,0x00,0x0C, ++0x00,0xFB,0x05,0x3C, ++0x00,0xF8,0x05,0x3C, ++0x02,0x5C,0x00,0x0C, ++0x48,0x0E,0x44,0x36, ++0x00,0x02,0x10,0x3C, ++0x25,0x22,0x00,0x0C, ++0x03,0x00,0x04,0x24, ++0x4C,0x0E,0x44,0x36, ++0x02,0x5C,0x00,0x0C, ++0xD1,0x28,0x05,0x36, ++0xD1,0x28,0x05,0x36, ++0x02,0x5C,0x00,0x0C, ++0x6C,0x0E,0x44,0x36, ++0x48,0x0E,0x44,0x36, ++0x02,0x5C,0x00,0x0C, ++0x00,0xFB,0x05,0x3C, ++0x00,0xF8,0x05,0x3C, ++0x02,0x5C,0x00,0x0C, ++0x48,0x0E,0x44,0x36, ++0x25,0x22,0x00,0x0C, ++0x03,0x00,0x04,0x24, ++0xAC,0x00,0xA5,0x8F, ++0x04,0x0C,0x44,0x36, ++0x02,0x5C,0x00,0x0C, ++0x00,0x01,0x31,0x32, ++0xB0,0x00,0xA5,0x8F, ++0x08,0x0C,0x44,0x36, ++0x02,0x5C,0x00,0x0C, ++0x2B,0x88,0x11,0x00, ++0x28,0x0E,0x44,0x36, ++0x02,0x5C,0x00,0x0C, ++0x21,0x28,0x00,0x00, ++0x23,0xFF,0x20,0x16, ++0xAC,0x0E,0x62,0x36, ++0x02,0x80,0x02,0x3C, ++0xBC,0xED,0x42,0x24, ++0x00,0x00,0x44,0x8C, ++0x02,0x5C,0x00,0x0C, ++0x00,0x01,0x05,0x3C, ++0x28,0x08,0x44,0x36, ++0x02,0x5C,0x00,0x0C, ++0x00,0x01,0x05,0x3C, ++0xAC,0x0E,0x62,0x36, ++0x94,0x0E,0x63,0x36, ++0x00,0x00,0x48,0x8C, ++0x00,0x00,0x64,0x8C, ++0xB4,0x0E,0x62,0x36, ++0x9C,0x0E,0x63,0x36, ++0x00,0x00,0x45,0x8C, ++0x00,0x00,0x66,0x8C, ++0x25,0xB0,0x03,0x3C, ++0xBC,0x0E,0x63,0x34, ++0x00,0x00,0x67,0x8C, ++0x24,0x20,0x94,0x00, ++0x00,0xD8,0x02,0x3C, ++0x24,0x10,0x02,0x01, ++0x24,0x28,0xB4,0x00, ++0x24,0x30,0xD4,0x00, ++0x24,0x38,0xF4,0x00, ++0x02,0x24,0x04,0x00, ++0x20,0x01,0x03,0x24, ++0x01,0x00,0x42,0x2C, ++0x02,0x2C,0x05,0x00, ++0x02,0x34,0x06,0x00, ++0x1A,0xFF,0x83,0x14, ++0x02,0x3C,0x07,0x00, ++0x80,0x00,0x03,0x24, ++0x20,0xFF,0x83,0x14, ++0x21,0x40,0x00,0x00, ++0xDA,0x28,0x00,0x08, ++0x21,0x20,0x00,0x00, ++0x00,0x00,0x62,0x8C, ++0x9C,0x0E,0x65,0x36, ++0xA4,0x0E,0x66,0x36, ++0x24,0x10,0x54,0x00, ++0x02,0x14,0x02,0x00, ++0x00,0x00,0xE2,0xAE, ++0x00,0x00,0xA4,0x8C, ++0xAC,0x0E,0x67,0x36, ++0xB4,0x0E,0x65,0x36, ++0x24,0x20,0x94,0x00, ++0x02,0x24,0x04,0x00, ++0x04,0x00,0xE4,0xAE, ++0x00,0x00,0xC3,0x8C, ++0xC4,0x0E,0x64,0x36, ++0x24,0x18,0x74,0x00, ++0x02,0x1C,0x03,0x00, ++0x08,0x00,0xE3,0xAE, ++0x00,0x00,0xE2,0x8C, ++0x00,0x00,0x00,0x00, ++0x24,0x10,0x54,0x00, ++0x02,0x14,0x02,0x00, ++0x0C,0x00,0xE2,0xAE, ++0x00,0x00,0xA3,0x8C, ++0x00,0x00,0x00,0x00, ++0x24,0x18,0x74,0x00, ++0x02,0x1C,0x03,0x00, ++0x10,0x00,0xE3,0xAE, ++0x25,0xB0,0x03,0x3C, ++0xBC,0x0E,0x63,0x34, ++0x00,0x00,0x62,0x8C, ++0x00,0x00,0x00,0x00, ++0x24,0x10,0x54,0x00, ++0x02,0x14,0x02,0x00, ++0x14,0x00,0xE2,0xAE, ++0x00,0x00,0x83,0x8C, ++0x00,0x00,0x00,0x00, ++0x24,0x18,0x74,0x00, ++0x02,0x1C,0x03,0x00, ++0x18,0x00,0xE3,0xAE, ++0x25,0xB0,0x03,0x3C, ++0xCC,0x0E,0x63,0x34, ++0x00,0x00,0x62,0x8C, ++0x00,0x00,0x00,0x00, ++0x24,0x10,0x54,0x00, ++0x02,0x14,0x02,0x00, ++0x1C,0x00,0xE2,0xAE, ++0x01,0x00,0xD6,0x26, ++0x03,0x00,0xC2,0x2E, ++0xC7,0xFE,0x40,0x14, ++0x20,0x00,0xF7,0x26, ++0x10,0x00,0xB0,0x8F, ++0x00,0x00,0x00,0x00, ++0x49,0x01,0x00,0x16, ++0x00,0x00,0x00,0x00, ++0x30,0x00,0xB1,0x8F, ++0x00,0x00,0x00,0x00, ++0x06,0x00,0x20,0x16, ++0x21,0x20,0x00,0x02, ++0x50,0x00,0xA2,0x8F, ++0x00,0x00,0x00,0x00, ++0x29,0x00,0x40,0x10, ++0xFF,0x00,0x05,0x24, ++0x21,0x20,0x00,0x02, ++0x05,0x28,0x00,0x0C, ++0x21,0x28,0x20,0x02, ++0x03,0x00,0x42,0x2C, ++0x08,0x00,0x40,0x10, ++0x00,0x00,0x00,0x00, ++0x34,0x00,0xA5,0x8F, ++0x14,0x00,0xA4,0x8F, ++0x05,0x28,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x03,0x00,0x42,0x2C, ++0x1C,0x00,0x40,0x14, ++0x21,0x28,0x00,0x00, ++0x50,0x00,0xB2,0x8F, ++0x21,0x20,0x00,0x02, ++0x05,0x28,0x00,0x0C, ++0x21,0x28,0x40,0x02, ++0x03,0x00,0x42,0x2C, ++0x09,0x00,0x40,0x10, ++0x21,0x20,0x20,0x02, ++0x54,0x00,0xA5,0x8F, ++0x14,0x00,0xA4,0x8F, ++0x05,0x28,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x03,0x00,0x42,0x2C, ++0x0E,0x00,0x40,0x14, ++0x21,0x28,0x00,0x00, ++0x21,0x20,0x20,0x02, ++0x05,0x28,0x00,0x0C, ++0x21,0x28,0x40,0x02, ++0x03,0x00,0x42,0x2C, ++0xE0,0x00,0x40,0x10, ++0x00,0x00,0x00,0x00, ++0x54,0x00,0xA5,0x8F, ++0x34,0x00,0xA4,0x8F, ++0x05,0x28,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x03,0x00,0x42,0x2C, ++0xD9,0x00,0x40,0x10, ++0x01,0x00,0x05,0x24, ++0xFF,0x00,0x02,0x24, ++0xDB,0x00,0xA2,0x10, ++0x25,0xB0,0x03,0x3C, ++0x10,0x00,0xA2,0x27, ++0x40,0x29,0x05,0x00, ++0x02,0x80,0x0F,0x3C, ++0x21,0x28,0xA2,0x00, ++0x30,0x1F,0xEC,0x25, ++0x00,0x00,0xA6,0x8C, ++0x0C,0x00,0xA7,0x8C, ++0x0C,0x00,0x83,0x8D, ++0x10,0x00,0x84,0x8D, ++0x04,0x00,0xA8,0x8C, ++0x10,0x00,0xA9,0x8C, ++0x00,0xFC,0x02,0x24, ++0x08,0x00,0xAA,0x8C, ++0x14,0x00,0xAB,0x8C, ++0x24,0x20,0x82,0x00, ++0xFF,0x03,0xC6,0x30, ++0x24,0x18,0x62,0x00, ++0xFF,0x03,0xE7,0x30, ++0xF0,0xFF,0x02,0x3C, ++0xFF,0x03,0x42,0x34, ++0x25,0x18,0x66,0x00, ++0x25,0x20,0x87,0x00, ++0xFF,0x03,0x08,0x31, ++0xFF,0x03,0x29,0x31, ++0x24,0x20,0x82,0x00, ++0x24,0x18,0x62,0x00, ++0x80,0x42,0x08,0x00, ++0x80,0x4A,0x09,0x00, ++0x0F,0xC0,0x02,0x3C, ++0x1C,0x00,0xA6,0x8C, ++0x18,0x00,0xA7,0x8C, ++0xFF,0xFF,0x42,0x34, ++0x25,0x18,0x68,0x00, ++0x25,0x20,0x89,0x00, ++0xFF,0x03,0x4A,0x31, ++0xFF,0x03,0x6B,0x31, ++0x24,0x20,0x82,0x00, ++0x00,0x55,0x0A,0x00, ++0x24,0x18,0x62,0x00, ++0x00,0x5D,0x0B,0x00, ++0x25,0x18,0x6A,0x00, ++0x25,0x20,0x8B,0x00, ++0x16,0x00,0x86,0xA5, ++0x0C,0x00,0x83,0xAD, ++0x10,0x00,0x84,0xAD, ++0x14,0x00,0x87,0xA5, ++0x30,0x1F,0xF1,0x25, ++0x10,0x00,0x22,0x8E, ++0x01,0x00,0x03,0x24, ++0x82,0x17,0x02,0x00, ++0x4D,0x00,0x43,0x10, ++0x25,0xB0,0x12,0x3C, ++0x0C,0x00,0x23,0x8E, ++0x80,0x0C,0x44,0x36, ++0x00,0x00,0x88,0x8C, ++0x00,0x02,0x62,0x30, ++0xC0,0xFF,0x13,0x3C, ++0x82,0x6D,0x08,0x00, ++0x03,0x00,0x40,0x10, ++0xFF,0x03,0x65,0x30, ++0x00,0xFC,0x02,0x24, ++0x25,0x28,0xA2,0x00, ++0x18,0x00,0xAD,0x00, ++0x82,0x62,0x03,0x00, ++0xFF,0x03,0x8C,0x31, ++0x00,0x02,0x83,0x31, ++0x12,0x10,0x00,0x00, ++0x02,0x12,0x02,0x00, ++0x03,0x00,0x60,0x10, ++0xFF,0x03,0x46,0x30, ++0x00,0xFC,0x02,0x24, ++0x25,0x60,0x82,0x01, ++0x18,0x00,0x8D,0x01, ++0x00,0xFC,0x74,0x36, ++0x24,0x28,0x14,0x01, ++0x12,0x80,0x00,0x00, ++0x02,0x82,0x10,0x00, ++0x3F,0x00,0x02,0x32, ++0x00,0x14,0x02,0x00, ++0x25,0x28,0xA2,0x00, ++0x02,0x5C,0x00,0x0C, ++0x25,0x28,0xA6,0x00, ++0x94,0x0C,0x44,0x36, ++0x00,0x00,0x85,0x8C, ++0xFF,0x0F,0x02,0x3C, ++0xFF,0xFF,0x55,0x34, ++0xC0,0x03,0x10,0x32, ++0x24,0x28,0xB5,0x00, ++0x80,0x85,0x10,0x00, ++0x02,0x5C,0x00,0x0C, ++0x25,0x28,0xB0,0x00, ++0x10,0x00,0x2C,0x8E, ++0x88,0x0C,0x44,0x36, ++0x00,0x00,0x88,0x8C, ++0x82,0x2A,0x0C,0x00, ++0xFF,0x03,0xA5,0x30, ++0x24,0x10,0x13,0x01, ++0x00,0x02,0xA3,0x30, ++0x03,0x00,0x60,0x10, ++0x82,0x6D,0x02,0x00, ++0x00,0xFC,0x02,0x24, ++0x25,0x28,0xA2,0x00, ++0x18,0x00,0xAD,0x00, ++0x02,0x65,0x0C,0x00, ++0xFF,0x03,0x8C,0x31, ++0x00,0x02,0x83,0x31, ++0x12,0x10,0x00,0x00, ++0x02,0x12,0x02,0x00, ++0x03,0x00,0x60,0x10, ++0xFF,0x03,0x46,0x30, ++0x00,0xFC,0x02,0x24, ++0x25,0x60,0x82,0x01, ++0x18,0x00,0x8D,0x01, ++0x24,0x28,0x14,0x01, ++0x12,0x80,0x00,0x00, ++0x02,0x82,0x10,0x00, ++0x3F,0x00,0x02,0x32, ++0x00,0x14,0x02,0x00, ++0x25,0x28,0xA2,0x00, ++0x02,0x5C,0x00,0x0C, ++0x25,0x28,0xA6,0x00, ++0x9C,0x0C,0x44,0x36, ++0x00,0x00,0x85,0x8C, ++0xC0,0x03,0x10,0x32, ++0x80,0x85,0x10,0x00, ++0x24,0x28,0xB5,0x00, ++0x02,0x5C,0x00,0x0C, ++0x25,0x28,0xB0,0x00, ++0x78,0x00,0xA5,0x8F, ++0x25,0xB0,0x10,0x3C, ++0x02,0x5C,0x00,0x0C, ++0xE0,0x0E,0x04,0x36, ++0x7C,0x00,0xA5,0x8F, ++0x02,0x5C,0x00,0x0C, ++0xDC,0x0E,0x04,0x36, ++0x80,0x00,0xA5,0x8F, ++0x02,0x5C,0x00,0x0C, ++0x70,0x0E,0x04,0x36, ++0x84,0x00,0xA5,0x8F, ++0x02,0x5C,0x00,0x0C, ++0x74,0x0E,0x04,0x36, ++0x88,0x00,0xA5,0x8F, ++0x02,0x5C,0x00,0x0C, ++0x78,0x0E,0x04,0x36, ++0x8C,0x00,0xA5,0x8F, ++0x02,0x5C,0x00,0x0C, ++0x7C,0x0E,0x04,0x36, ++0x90,0x00,0xA5,0x8F, ++0x02,0x5C,0x00,0x0C, ++0x80,0x0E,0x04,0x36, ++0x94,0x00,0xA5,0x8F, ++0x02,0x5C,0x00,0x0C, ++0x84,0x0E,0x04,0x36, ++0x98,0x00,0xA5,0x8F, ++0x02,0x5C,0x00,0x0C, ++0x88,0x0E,0x04,0x36, ++0x9C,0x00,0xA5,0x8F, ++0x02,0x5C,0x00,0x0C, ++0x8C,0x0E,0x04,0x36, ++0xA0,0x00,0xA5,0x8F, ++0x02,0x5C,0x00,0x0C, ++0xD0,0x0E,0x04,0x36, ++0xA4,0x00,0xA5,0x8F, ++0x02,0x5C,0x00,0x0C, ++0xD4,0x0E,0x04,0x36, ++0xA8,0x00,0xA5,0x8F, ++0x88,0x0E,0x04,0x36, ++0x02,0x5C,0x00,0x0C, ++0x0F,0x00,0x10,0x3C, ++0x70,0x00,0xA6,0x8F, ++0xFF,0xFF,0x05,0x36, ++0x5F,0x47,0x00,0x0C, ++0x21,0x20,0x00,0x00, ++0x54,0x22,0x00,0x0C, ++0x64,0x00,0x04,0x24, ++0xE6,0x44,0x00,0x0C, ++0x01,0x00,0x04,0x24, ++0x74,0x00,0xA6,0x8F, ++0xFF,0xFF,0x05,0x36, ++0x5F,0x47,0x00,0x0C, ++0x21,0x20,0x00,0x00, ++0x54,0x22,0x00,0x0C, ++0x64,0x00,0x04,0x24, ++0xE6,0x44,0x00,0x0C, ++0x21,0x20,0x00,0x00, ++0xFF,0xFF,0x05,0x36, ++0x8A,0x47,0x00,0x0C, ++0x1E,0x00,0x04,0x24, ++0x21,0x88,0x40,0x00, ++0xFD,0xFF,0x06,0x24, ++0x01,0x00,0x42,0x34, ++0x24,0x30,0x46,0x00, ++0xFF,0xFF,0x05,0x36, ++0x5F,0x47,0x00,0x0C, ++0x1E,0x00,0x04,0x24, ++0x25,0x22,0x00,0x0C, ++0x03,0x00,0x04,0x24, ++0xFF,0xFF,0x05,0x36, ++0x03,0x00,0x26,0x36, ++0x5F,0x47,0x00,0x0C, ++0x1E,0x00,0x04,0x24, ++0xDC,0x00,0xBF,0x8F, ++0xD8,0x00,0xBE,0x8F, ++0xD4,0x00,0xB7,0x8F, ++0xD0,0x00,0xB6,0x8F, ++0xCC,0x00,0xB5,0x8F, ++0xC8,0x00,0xB4,0x8F, ++0xC4,0x00,0xB3,0x8F, ++0xC0,0x00,0xB2,0x8F, ++0xBC,0x00,0xB1,0x8F, ++0xB8,0x00,0xB0,0x8F, ++0x08,0x00,0xE0,0x03, ++0xE0,0x00,0xBD,0x27, ++0xFF,0x00,0x05,0x24, ++0xFF,0x00,0x02,0x24, ++0x29,0xFF,0xA2,0x14, ++0x10,0x00,0xA2,0x27, ++0x25,0xB0,0x03,0x3C, ++0x94,0x0E,0x62,0x34, ++0x9C,0x0E,0x64,0x34, ++0xA4,0x0E,0x65,0x34, ++0xAC,0x0E,0x66,0x34, ++0x02,0x80,0x0F,0x3C, ++0x00,0x00,0x49,0x8C, ++0x30,0x1F,0xED,0x25, ++0x00,0x00,0x8C,0x8C, ++0x00,0x00,0xAE,0x8C, ++0x00,0x00,0xC7,0x8C, ++0xB4,0x0E,0x62,0x34, ++0x0C,0x00,0xA4,0x8D, ++0x10,0x00,0xA5,0x8D, ++0x00,0x00,0x4A,0x8C, ++0xFF,0x03,0x06,0x3C, ++0x00,0xFC,0x08,0x24, ++0xBC,0x0E,0x62,0x34, ++0x24,0x48,0x26,0x01, ++0x24,0x38,0xE6,0x00, ++0x00,0x00,0x4B,0x8C, ++0x24,0x28,0xA8,0x00, ++0x24,0x20,0x88,0x00, ++0x02,0x3C,0x07,0x00, ++0xCC,0x0E,0x68,0x34, ++0x02,0x4C,0x09,0x00, ++0xC4,0x0E,0x63,0x34, ++0xF0,0xFF,0x02,0x3C, ++0xFF,0x03,0x42,0x34, ++0x25,0x28,0xA7,0x00, ++0x25,0x20,0x89,0x00, ++0x00,0x00,0x67,0x8C, ++0x24,0x60,0x86,0x01, ++0x00,0x00,0x03,0x8D, ++0x24,0x50,0x46,0x01, ++0x24,0x28,0xA2,0x00, ++0x24,0x20,0x82,0x00, ++0x82,0x61,0x0C,0x00, ++0x82,0x51,0x0A,0x00, ++0x0F,0xC0,0x02,0x3C, ++0xFF,0xFF,0x42,0x34, ++0x25,0x20,0x8C,0x00, ++0x25,0x28,0xAA,0x00, ++0x24,0x70,0xC6,0x01, ++0x24,0x58,0x66,0x01, ++0x24,0x28,0xA2,0x00, ++0x24,0x18,0x66,0x00, ++0x00,0x71,0x0E,0x00, ++0x24,0x20,0x82,0x00, ++0x00,0x59,0x0B,0x00, ++0x24,0x38,0xE6,0x00, ++0x25,0x20,0x8E,0x00, ++0x25,0x28,0xAB,0x00, ++0x02,0x3C,0x07,0x00, ++0x02,0x1C,0x03,0x00, ++0x16,0x00,0xA3,0xA5, ++0x0C,0x00,0xA4,0xAD, ++0x10,0x00,0xA5,0xAD, ++0x4D,0x2A,0x00,0x08, ++0x14,0x00,0xA7,0xA5, ++0x30,0x00,0xB1,0x8F, ++0xF5,0x29,0x00,0x08, ++0x21,0x20,0x00,0x02, ++0x25,0xB0,0x05,0x3C, ++0x4C,0x00,0xA2,0x34, ++0x02,0x80,0x07,0x3C, ++0x00,0x00,0x43,0x90, ++0x30,0x1F,0xE4,0x24, ++0xC1,0x1B,0x82,0x90, ++0x03,0x00,0x66,0x30, ++0x24,0x00,0x46,0x10, ++0x00,0x00,0x00,0x00, ++0x18,0x00,0xC0,0x14, ++0x25,0xB0,0x03,0x3C, ++0xE6,0x02,0x82,0x90, ++0x00,0x00,0x00,0x00, ++0x15,0x00,0x40,0x14, ++0x58,0x00,0x62,0x34, ++0x1C,0x00,0x02,0x24, ++0x50,0x0C,0xA3,0x34, ++0x00,0x00,0x62,0xA0, ++0x21,0x10,0x00,0x00, ++0x01,0x00,0x42,0x24, ++0xFF,0x00,0x42,0x30, ++0x06,0x00,0x43,0x2C, ++0xFD,0xFF,0x60,0x14, ++0x01,0x00,0x42,0x24, ++0x25,0xB0,0x02,0x3C, ++0x58,0x0C,0x42,0x34, ++0x1C,0x00,0x03,0x24, ++0x00,0x00,0x43,0xA0, ++0x21,0x10,0x00,0x00, ++0x01,0x00,0x42,0x24, ++0xFF,0x00,0x42,0x30, ++0x06,0x00,0x43,0x2C, ++0xFC,0xFF,0x60,0x14, ++0x25,0xB0,0x03,0x3C, ++0x58,0x00,0x62,0x34, ++0x00,0x00,0x45,0x8C, ++0x29,0xB0,0x04,0x3C, ++0x5C,0x00,0x63,0x34, ++0x00,0x00,0x85,0xAC, ++0x00,0x00,0x65,0x8C, ++0x30,0x1F,0xE2,0x24, ++0x04,0x00,0x84,0x34, ++0xC1,0x1B,0x46,0xA0, ++0x00,0x00,0x85,0xAC, ++0x08,0x00,0xE0,0x03, ++0x21,0x10,0x00,0x00, ++0x25,0xB0,0x02,0x3C, ++0xE8,0xFF,0xBD,0x27, ++0x10,0x00,0xBF,0xAF, ++0x2D,0x0A,0x46,0x34, ++0xA2,0x0D,0x43,0x34, ++0xA4,0x0D,0x44,0x34, ++0xA6,0x0D,0x45,0x34, ++0xA8,0x0D,0x42,0x34, ++0x00,0x00,0x67,0x94, ++0x00,0x00,0x88,0x94, ++0x00,0x00,0xA9,0x94, ++0x00,0x00,0x44,0x94, ++0x00,0x00,0xC3,0x90, ++0x02,0x80,0x0A,0x3C, ++0x30,0x1F,0x42,0x25, ++0x40,0x00,0x63,0x34, ++0xFF,0x00,0x63,0x30, ++0xDE,0x02,0x44,0xA4, ++0x00,0x00,0xC3,0xA0, ++0xD8,0x02,0x47,0xA4, ++0xDA,0x02,0x48,0xA4, ++0xDC,0x02,0x49,0xA4, ++0x21,0x10,0x00,0x00, ++0x01,0x00,0x42,0x24, ++0xFF,0x00,0x42,0x30, ++0x06,0x00,0x43,0x2C, ++0xFD,0xFF,0x60,0x14, ++0x01,0x00,0x42,0x24, ++0x25,0xB0,0x07,0x3C, ++0x5B,0x0A,0xE2,0x34, ++0x00,0x00,0x44,0x90, ++0x30,0x1F,0x46,0x25, ++0x5C,0x0A,0xE2,0x34, ++0x00,0x00,0x45,0x90, ++0xD8,0x02,0xC3,0x94, ++0xDA,0x02,0xC2,0x94, ++0xDC,0x02,0xC9,0x94, ++0xDE,0x02,0xC8,0x94, ++0xFF,0x00,0x84,0x30, ++0x21,0x18,0x62,0x00, ++0x00,0x22,0x04,0x00, ++0xFF,0x00,0xA5,0x30, ++0x21,0x20,0x85,0x00, ++0x21,0x18,0x69,0x00, ++0xFF,0xFF,0x82,0x30, ++0x21,0x18,0x68,0x00, ++0x21,0x18,0x62,0x00, ++0x64,0x0C,0xE7,0x34, ++0xFF,0xFF,0x42,0x30, ++0xE0,0x02,0xC3,0xAC, ++0x00,0x00,0xE2,0xA4, ++0xE4,0x02,0xC4,0xA4, ++0x21,0x10,0x00,0x00, ++0x01,0x00,0x42,0x24, ++0xFF,0x00,0x42,0x30, ++0x06,0x00,0x43,0x2C, ++0xFD,0xFF,0x60,0x14, ++0x01,0x00,0x42,0x24, ++0x30,0x1F,0x42,0x8D, ++0x01,0x00,0x03,0x24, ++0x0F,0x00,0x44,0x30, ++0x07,0x00,0x83,0x10, ++0x30,0x1F,0x45,0x25, ++0xB6,0x5F,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x10,0x00,0xBF,0x8F, ++0x21,0x10,0x00,0x00, ++0x08,0x00,0xE0,0x03, ++0x18,0x00,0xBD,0x27, ++0xE4,0x02,0xA2,0x8C, ++0x00,0x00,0x00,0x00, ++0x02,0x17,0x02,0x00, ++0x03,0x00,0x42,0x30, ++0xF5,0xFF,0x40,0x14, ++0x25,0xB0,0x02,0x3C, ++0x4C,0x00,0x42,0x34, ++0x00,0x00,0x43,0x90, ++0x00,0x00,0x00,0x00, ++0x03,0x00,0x63,0x30, ++0x3F,0x00,0x64,0x10, ++0x30,0x1F,0x44,0x25, ++0xE6,0x02,0x82,0x90, ++0x00,0x00,0x00,0x00, ++0x07,0x00,0x40,0x14, ++0x01,0x00,0x03,0x24, ++0x30,0x1F,0x42,0x8D, ++0x00,0x00,0x00,0x00, ++0x02,0x12,0x02,0x00, ++0x0F,0x00,0x42,0x30, ++0x3C,0x00,0x43,0x10, ++0x25,0xB0,0x02,0x3C, ++0x30,0x1F,0x45,0x25, ++0xE6,0x02,0xA3,0x90, ++0xFF,0x00,0x02,0x24, ++0xE0,0xFF,0x62,0x14, ++0x25,0xB0,0x03,0x3C, ++0xC8,0x02,0xA2,0x94, ++0xE0,0x02,0xA6,0x8C, ++0x50,0x0C,0x63,0x34, ++0x00,0x00,0x64,0x90, ++0x2B,0x10,0xC2,0x00, ++0x85,0x00,0x40,0x10, ++0x7F,0x00,0x84,0x30, ++0xFF,0xFF,0x82,0x24, ++0xFF,0x00,0x44,0x30, ++0x30,0x1F,0x45,0x25, ++0xD0,0x02,0xA3,0x90, ++0x00,0x00,0x00,0x00, ++0x2B,0x10,0x64,0x00, ++0x78,0x00,0x40,0x10, ++0x00,0x00,0x00,0x00, ++0x21,0x20,0x60,0x00, ++0x30,0x1F,0x43,0x25, ++0xE0,0x02,0x62,0x8C, ++0x00,0x00,0x00,0x00, ++0x11,0x27,0x42,0x2C, ++0x6D,0x00,0x40,0x14, ++0x3A,0x00,0x82,0x2C, ++0x32,0x00,0x04,0x24, ++0x44,0x00,0x03,0x24, ++0x25,0xB0,0x02,0x3C, ++0x30,0x0C,0x42,0x34, ++0x00,0x00,0x43,0xA0, ++0x25,0xB0,0x02,0x3C, ++0x50,0x0C,0x42,0x34, ++0x00,0x00,0x44,0xA0, ++0x21,0x10,0x00,0x00, ++0x01,0x00,0x42,0x24, ++0xFF,0x00,0x42,0x30, ++0x06,0x00,0x43,0x2C, ++0xFD,0xFF,0x60,0x14, ++0x01,0x00,0x42,0x24, ++0x25,0xB0,0x02,0x3C, ++0x58,0x0C,0x42,0x34, ++0x00,0x00,0x44,0xA0, ++0x21,0x10,0x00,0x00, ++0x01,0x00,0x42,0x24, ++0xFF,0x00,0x42,0x30, ++0x06,0x00,0x43,0x2C, ++0xFD,0xFF,0x60,0x14, ++0x01,0x00,0x42,0x24, ++0xA4,0x2B,0x00,0x08, ++0x00,0x00,0x00,0x00, ++0xE6,0x02,0xA2,0x90, ++0x00,0x00,0x00,0x00, ++0xBF,0xFF,0x40,0x14, ++0x00,0x00,0x00,0x00, ++0xFF,0xFF,0x02,0x24, ++0xB6,0x2B,0x00,0x08, ++0xE6,0x02,0xA2,0xA0, ++0x4C,0x00,0x42,0x34, ++0x00,0x00,0x43,0x90, ++0x00,0x00,0x00,0x00, ++0x03,0x00,0x63,0x30, ++0xA4,0xFF,0x60,0x10, ++0xFF,0xFF,0x02,0x34, ++0x80,0x36,0x83,0x8C, ++0x00,0x00,0x00,0x00, ++0xA0,0xFF,0x62,0x10, ++0x00,0x00,0x00,0x00, ++0xE0,0x02,0x83,0x8C, ++0x00,0x00,0x00,0x00, ++0x65,0x00,0x62,0x2C, ++0x59,0x00,0x40,0x14, ++0x28,0x00,0x62,0x2C, ++0xD2,0x02,0x83,0x90, ++0x00,0x00,0x00,0x00, ++0x00,0x16,0x03,0x00, ++0x03,0x16,0x02,0x00, ++0xFE,0xFF,0x42,0x24, ++0xFC,0xFF,0x42,0x28, ++0x02,0x00,0x40,0x10, ++0xFE,0xFF,0x62,0x24, ++0xFC,0xFF,0x02,0x24, ++0xD2,0x02,0x82,0xA0, ++0x30,0x1F,0x45,0x25, ++0x80,0x36,0xA2,0x8C, ++0xD2,0x02,0xA3,0x90, ++0xCE,0x02,0xA6,0x90, ++0x02,0x11,0x02,0x00, ++0x7F,0x00,0x42,0x30, ++0x0A,0x00,0x44,0x24, ++0x23,0x18,0x83,0x00, ++0x00,0x26,0x03,0x00, ++0x03,0x26,0x04,0x00, ++0xFF,0x00,0xC2,0x30, ++0x2A,0x10,0x44,0x00, ++0x4D,0x00,0x40,0x10, ++0x00,0x00,0x00,0x00, ++0x00,0x26,0x06,0x00, ++0x03,0x26,0x04,0x00, ++0x30,0x1F,0x43,0x25, ++0xE0,0x02,0x62,0x8C, ++0x00,0x00,0x00,0x00, ++0x11,0x27,0x42,0x2C, ++0x33,0x00,0x40,0x14, ++0x3A,0x00,0x82,0x28, ++0x32,0x00,0x82,0x28, ++0x30,0x00,0x40,0x10, ++0x3A,0x00,0x82,0x28, ++0x32,0x00,0x04,0x24, ++0x44,0x00,0x03,0x24, ++0x25,0xB0,0x02,0x3C, ++0x30,0x0C,0x42,0x34, ++0x00,0x00,0x43,0xA0, ++0x25,0xB0,0x02,0x3C, ++0x50,0x0C,0x42,0x34, ++0xFF,0x00,0x84,0x30, ++0x00,0x00,0x44,0xA0, ++0x21,0x10,0x00,0x00, ++0x01,0x00,0x42,0x24, ++0xFF,0x00,0x42,0x30, ++0x06,0x00,0x43,0x2C, ++0xFD,0xFF,0x60,0x14, ++0x01,0x00,0x42,0x24, ++0x25,0xB0,0x02,0x3C, ++0x58,0x0C,0x42,0x34, ++0x00,0x00,0x44,0xA0, ++0x21,0x10,0x00,0x00, ++0x01,0x00,0x42,0x24, ++0xFF,0x00,0x42,0x30, ++0x06,0x00,0x43,0x2C, ++0xFD,0xFF,0x60,0x14, ++0x01,0x00,0x42,0x24, ++0xA4,0x2B,0x00,0x08, ++0x00,0x00,0x00,0x00, ++0x95,0xFF,0x40,0x10, ++0x48,0x00,0x03,0x24, ++0xDD,0x2B,0x00,0x08, ++0x44,0x00,0x03,0x24, ++0xD1,0x02,0xA3,0x90, ++0x00,0x00,0x00,0x00, ++0x2B,0x10,0x83,0x00, ++0xD5,0x2B,0x00,0x08, ++0x0B,0x20,0x62,0x00, ++0xCA,0x02,0xA2,0x94, ++0x00,0x00,0x00,0x00, ++0x2B,0x10,0xC2,0x00, ++0x7A,0xFF,0x40,0x14, ++0x00,0x00,0x00,0x00, ++0xCC,0x02,0xA2,0x94, ++0x00,0x00,0x00,0x00, ++0x2B,0x10,0xC2,0x00, ++0x07,0x00,0x40,0x10, ++0x00,0x00,0x00,0x00, ++0xCD,0x2B,0x00,0x08, ++0x01,0x00,0x82,0x24, ++0xD2,0xFF,0x40,0x10, ++0x48,0x00,0x03,0x24, ++0x2F,0x2C,0x00,0x08, ++0x44,0x00,0x03,0x24, ++0xCD,0x2B,0x00,0x08, ++0x02,0x00,0x82,0x24, ++0xB2,0xFF,0x40,0x10, ++0x30,0x1F,0x45,0x25, ++0xD2,0x02,0x83,0x90, ++0x00,0x00,0x00,0x00, ++0x00,0x16,0x03,0x00, ++0x03,0x16,0x02,0x00, ++0x02,0x00,0x42,0x24, ++0x0D,0x00,0x42,0x28, ++0x09,0x00,0x40,0x14, ++0x00,0x00,0x00,0x00, ++0x13,0x2C,0x00,0x08, ++0x0C,0x00,0x02,0x24, ++0xCF,0x02,0xA3,0x80, ++0x00,0x00,0x00,0x00, ++0xFF,0x00,0x62,0x30, ++0x2A,0x10,0x82,0x00, ++0x24,0x2C,0x00,0x08, ++0x0B,0x20,0x62,0x00, ++0x13,0x2C,0x00,0x08, ++0x02,0x00,0x62,0x24, ++0xC0,0xFF,0xBD,0x27, ++0x28,0x00,0xB4,0xAF, ++0x25,0xB0,0x14,0x3C, ++0x20,0x00,0xB2,0xAF, ++0x1C,0x00,0xB1,0xAF, ++0x18,0x00,0xB0,0xAF, ++0x3C,0x00,0xBF,0xAF, ++0x38,0x00,0xBE,0xAF, ++0x34,0x00,0xB7,0xAF, ++0x30,0x00,0xB6,0xAF, ++0x2C,0x00,0xB5,0xAF, ++0x24,0x00,0xB3,0xAF, ++0xD8,0x00,0x86,0x36, ++0x00,0x00,0xC3,0x90, ++0x02,0x80,0x02,0x3C, ++0x30,0x1F,0x51,0x24, ++0x2A,0xB0,0x10,0x3C, ++0xA0,0xFF,0x02,0x24, ++0x25,0x18,0x62,0x00, ++0x34,0x00,0x05,0x36, ++0xFE,0xFF,0x02,0x24, ++0xBC,0x02,0x33,0x92, ++0x40,0x00,0x04,0x24, ++0x00,0x00,0xC3,0xA0, ++0x00,0x00,0xA2,0xA0, ++0x25,0x24,0x00,0x0C, ++0x00,0x9E,0x13,0x00, ++0x21,0x90,0x40,0x00, ++0x8A,0x00,0x40,0x12, ++0x00,0x40,0x02,0x3C, ++0x08,0x00,0x43,0x8E, ++0xB0,0x03,0x82,0x36, ++0x25,0xB0,0x1E,0x3C, ++0x21,0x20,0x40,0x02, ++0x00,0x00,0x43,0xAC, ++0x0C,0x4D,0x00,0x0C, ++0x21,0xB8,0x20,0x02, ++0x42,0x00,0xD5,0x37, ++0x03,0x0C,0xD1,0x37, ++0x17,0x0E,0xD6,0x37, ++0x04,0x00,0x14,0x24, ++0x2A,0xB0,0x03,0x3C, ++0x06,0x00,0x63,0x34, ++0x00,0x00,0x62,0x94, ++0x00,0x00,0x00,0x00, ++0x00,0xFF,0x42,0x30, ++0x0A,0x00,0x40,0x18, ++0x00,0x00,0x00,0x00, ++0x02,0x80,0x04,0x3C, ++0x8C,0xF0,0x84,0x24, ++0x00,0x00,0x83,0x8C, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x62,0x94, ++0x00,0x00,0x00,0x00, ++0x00,0xFF,0x42,0x30, ++0xFC,0xFF,0x40,0x1C, ++0x00,0x00,0x00,0x00, ++0x08,0x00,0x45,0x8E, ++0x20,0x10,0x06,0x3C, ++0x01,0x00,0x04,0x24, ++0x00,0xFE,0xC6,0x34, ++0x40,0x00,0x07,0x24, ++0x73,0x01,0x00,0x0C, ++0x10,0x00,0xA4,0xAF, ++0xB0,0x01,0x00,0x0C, ++0x01,0x00,0x04,0x24, ++0x02,0x80,0x02,0x3C, ++0x90,0xF0,0x42,0x24, ++0x00,0x00,0x45,0x8C, ++0x01,0x00,0x03,0x24, ++0x21,0x20,0x00,0x00, ++0x00,0x00,0xA3,0xA0, ++0xFF,0xFF,0x03,0x24, ++0x00,0x00,0xA3,0xA2, ++0x00,0x00,0x22,0x92, ++0x00,0x00,0x00,0x00, ++0xFF,0x00,0x42,0x30, ++0x40,0x00,0x42,0x34, ++0x00,0x00,0x22,0xA2, ++0x01,0x00,0x82,0x24, ++0xFF,0x00,0x44,0x30, ++0x06,0x00,0x83,0x2C, ++0xFD,0xFF,0x60,0x14, ++0x01,0x00,0x82,0x24, ++0x02,0x00,0x02,0x24, ++0x02,0x80,0x04,0x3C, ++0x00,0x00,0xA2,0xA0, ++0x30,0x1F,0x83,0x24, ++0xC1,0x02,0x62,0x90, ++0x00,0x00,0xC4,0x92, ++0x21,0x28,0x00,0x00, ++0x00,0x00,0xC2,0xA2, ++0xFF,0x00,0x90,0x30, ++0x01,0x00,0xA2,0x24, ++0xFF,0x00,0x45,0x30, ++0x06,0x00,0xA3,0x2C, ++0xFD,0xFF,0x60,0x14, ++0x01,0x00,0xA2,0x24, ++0xEF,0xFF,0x02,0x24, ++0x64,0x00,0x04,0x24, ++0x00,0x00,0xA2,0xA2, ++0x54,0x22,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x22,0x92, ++0x21,0x20,0x00,0x00, ++0xBF,0x00,0x42,0x30, ++0x00,0x00,0x22,0xA2, ++0x01,0x00,0x82,0x24, ++0xFF,0x00,0x44,0x30, ++0x06,0x00,0x83,0x2C, ++0xFD,0xFF,0x60,0x14, ++0x01,0x00,0x82,0x24, ++0x54,0x22,0x00,0x0C, ++0x84,0x03,0x04,0x24, ++0xF4,0x08,0xC2,0x37, ++0x00,0x00,0x43,0x8C, ++0x00,0x80,0x04,0x3C, ++0xDF,0x07,0x84,0x34, ++0x00,0x00,0xD0,0xA2, ++0x21,0x10,0x00,0x00, ++0x24,0x28,0x64,0x00, ++0x01,0x00,0x42,0x24, ++0xFF,0x00,0x42,0x30, ++0x06,0x00,0x43,0x2C, ++0xFD,0xFF,0x60,0x14, ++0x01,0x00,0x42,0x24, ++0x00,0x00,0xA0,0xA2, ++0x00,0x00,0x22,0x92, ++0x21,0x20,0x00,0x00, ++0xFF,0x00,0x42,0x30, ++0x40,0x00,0x42,0x34, ++0x00,0x00,0x22,0xA2, ++0x01,0x00,0x82,0x24, ++0xFF,0x00,0x44,0x30, ++0x06,0x00,0x83,0x2C, ++0xFD,0xFF,0x60,0x14, ++0x01,0x00,0x82,0x24, ++0xBE,0x02,0xE2,0x92, ++0x1F,0x00,0xA3,0x30, ++0x2B,0x10,0x62,0x00, ++0x0A,0x00,0x40,0x10, ++0x02,0x80,0x02,0x3C, ++0xBF,0x02,0xE2,0x92, ++0x00,0x00,0x00,0x00, ++0x2B,0x10,0x43,0x00, ++0x05,0x00,0x40,0x10, ++0x02,0x80,0x02,0x3C, ++0x01,0x00,0x02,0x3C, ++0x25,0x10,0x62,0x00, ++0x21,0x98,0x62,0x02, ++0x02,0x80,0x02,0x3C, ++0xDE,0x5D,0x43,0x90, ++0x22,0x00,0x02,0x24, ++0x19,0x00,0x62,0x10, ++0x92,0x00,0x02,0x24, ++0x18,0x00,0x62,0x10, ++0x02,0x80,0x03,0x3C, ++0xFF,0xFF,0x94,0x26, ++0x54,0x22,0x00,0x0C, ++0xF4,0x01,0x04,0x24, ++0x89,0xFF,0x81,0x06, ++0x2A,0xB0,0x03,0x3C, ++0x04,0x00,0x40,0x12, ++0x21,0x10,0x60,0x02, ++0x3D,0x24,0x00,0x0C, ++0x21,0x20,0x40,0x02, ++0x21,0x10,0x60,0x02, ++0x3C,0x00,0xBF,0x8F, ++0x38,0x00,0xBE,0x8F, ++0x34,0x00,0xB7,0x8F, ++0x30,0x00,0xB6,0x8F, ++0x2C,0x00,0xB5,0x8F, ++0x28,0x00,0xB4,0x8F, ++0x24,0x00,0xB3,0x8F, ++0x20,0x00,0xB2,0x8F, ++0x1C,0x00,0xB1,0x8F, ++0x18,0x00,0xB0,0x8F, ++0x08,0x00,0xE0,0x03, ++0x40,0x00,0xBD,0x27, ++0x02,0x80,0x03,0x3C, ++0x30,0x1F,0x63,0x24, ++0xBE,0x02,0x62,0x90, ++0xC0,0x07,0xA3,0x30, ++0x82,0x19,0x03,0x00, ++0x2B,0x10,0x62,0x00, ++0xE3,0xFF,0x40,0x10, ++0x02,0x80,0x04,0x3C, ++0x30,0x1F,0x84,0x24, ++0xBF,0x02,0x82,0x90, ++0x00,0x00,0x00,0x00, ++0x2B,0x10,0x43,0x00, ++0xDD,0xFF,0x40,0x10, ++0x00,0x12,0x03,0x00, ++0x10,0x00,0x03,0x3C, ++0x25,0x10,0x43,0x00, ++0x13,0x2D,0x00,0x08, ++0x21,0x98,0x62,0x02, ++0xE0,0xFF,0xBD,0x27, ++0x10,0x00,0xB0,0xAF, ++0x0F,0x00,0x10,0x3C, ++0xFF,0xFF,0x05,0x36, ++0xF0,0xF8,0x06,0x34, ++0x15,0x00,0x04,0x24, ++0x1C,0x00,0xBF,0xAF, ++0x18,0x00,0xB2,0xAF, ++0x5F,0x47,0x00,0x0C, ++0x14,0x00,0xB1,0xAF, ++0x54,0x22,0x00,0x0C, ++0x64,0x00,0x04,0x24, ++0x02,0x80,0x12,0x3C, ++0xFF,0xFF,0x05,0x36, ++0x56,0x30,0x06,0x24, ++0x5F,0x47,0x00,0x0C, ++0x1A,0x00,0x04,0x24, ++0x30,0x1F,0x51,0x26, ++0x54,0x22,0x00,0x0C, ++0x64,0x00,0x04,0x24, ++0x04,0x03,0x23,0x92, ++0x04,0x00,0x02,0x24, ++0x20,0x00,0x62,0x10, ++0x25,0xB0,0x02,0x3C, ++0x14,0x03,0x25,0x8E, ++0x25,0xB0,0x10,0x3C, ++0x43,0x60,0x00,0x0C, ++0x00,0x0E,0x04,0x36, ++0x14,0x03,0x25,0x8E, ++0x43,0x60,0x00,0x0C, ++0x04,0x0E,0x04,0x36, ++0x18,0x03,0x25,0x8E, ++0x43,0x60,0x00,0x0C, ++0x08,0x0E,0x04,0x36, ++0x14,0x03,0x25,0x8E, ++0x43,0x60,0x00,0x0C, ++0x10,0x0E,0x04,0x36, ++0x14,0x03,0x25,0x8E, ++0x43,0x60,0x00,0x0C, ++0x14,0x0E,0x04,0x36, ++0x14,0x03,0x25,0x8E, ++0x43,0x60,0x00,0x0C, ++0x18,0x0E,0x04,0x36, ++0x14,0x03,0x25,0x8E, ++0x43,0x60,0x00,0x0C, ++0x1C,0x0E,0x04,0x36, ++0x30,0x1F,0x43,0x26, ++0x1C,0x00,0xBF,0x8F, ++0x18,0x00,0xB2,0x8F, ++0x14,0x00,0xB1,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x04,0x00,0x02,0x24, ++0x20,0x00,0xBD,0x27, ++0x08,0x00,0xE0,0x03, ++0x04,0x03,0x62,0xA0, ++0x00,0x0E,0x42,0x34, ++0x00,0x00,0x43,0x8C, ++0x14,0x03,0x25,0x8E, ++0x00,0x00,0x00,0x00, ++0xDE,0xFF,0x65,0x14, ++0x25,0xB0,0x10,0x3C, ++0x6A,0x2D,0x00,0x08, ++0x30,0x1F,0x43,0x26, ++0xE0,0xFF,0xBD,0x27, ++0x10,0x00,0xB0,0xAF, ++0x0F,0x00,0x10,0x3C, ++0xFF,0xFF,0x05,0x36, ++0xF0,0xF8,0x06,0x34, ++0x15,0x00,0x04,0x24, ++0x1C,0x00,0xBF,0xAF, ++0x18,0x00,0xB2,0xAF, ++0x5F,0x47,0x00,0x0C, ++0x14,0x00,0xB1,0xAF, ++0x54,0x22,0x00,0x0C, ++0x64,0x00,0x04,0x24, ++0xFF,0xFF,0x05,0x36, ++0x56,0x30,0x06,0x24, ++0x5F,0x47,0x00,0x0C, ++0x1A,0x00,0x04,0x24, ++0x02,0x80,0x10,0x3C, ++0x54,0x22,0x00,0x0C, ++0x64,0x00,0x04,0x24, ++0x30,0x1F,0x02,0x26, ++0x04,0x03,0x46,0x90, ++0x25,0xB0,0x11,0x3C, ++0x10,0x10,0x12,0x3C, ++0x01,0x00,0x03,0x24, ++0x00,0x0E,0x24,0x36, ++0x1E,0x00,0xC3,0x10, ++0x10,0x10,0x45,0x36, ++0x43,0x60,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x04,0x0E,0x24,0x36, ++0x43,0x60,0x00,0x0C, ++0x10,0x10,0x45,0x36, ++0x08,0x0E,0x24,0x36, ++0x43,0x60,0x00,0x0C, ++0x10,0x10,0x05,0x24, ++0x10,0x0E,0x24,0x36, ++0x43,0x60,0x00,0x0C, ++0x10,0x10,0x45,0x36, ++0x14,0x0E,0x24,0x36, ++0x43,0x60,0x00,0x0C, ++0x10,0x10,0x45,0x36, ++0x18,0x0E,0x24,0x36, ++0x43,0x60,0x00,0x0C, ++0x10,0x10,0x45,0x36, ++0x1C,0x0E,0x24,0x36, ++0x43,0x60,0x00,0x0C, ++0x10,0x10,0x45,0x36, ++0x30,0x1F,0x03,0x26, ++0x1C,0x00,0xBF,0x8F, ++0x18,0x00,0xB2,0x8F, ++0x14,0x00,0xB1,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x01,0x00,0x02,0x24, ++0x20,0x00,0xBD,0x27, ++0x08,0x00,0xE0,0x03, ++0x04,0x03,0x62,0xA0, ++0x00,0x00,0x86,0x8C, ++0x00,0x00,0x00,0x00, ++0xE0,0xFF,0xC5,0x14, ++0x30,0x1F,0x03,0x26, ++0x1C,0x00,0xBF,0x8F, ++0x18,0x00,0xB2,0x8F, ++0x14,0x00,0xB1,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x01,0x00,0x02,0x24, ++0x20,0x00,0xBD,0x27, ++0x08,0x00,0xE0,0x03, ++0x04,0x03,0x62,0xA0, ++0xD8,0xFF,0xBD,0x27, ++0x1C,0x00,0xB3,0xAF, ++0x02,0x80,0x13,0x3C, ++0x14,0x00,0xB1,0xAF, ++0x30,0x1F,0x71,0x26, ++0x0C,0x03,0x26,0x8E, ++0x10,0x00,0xB0,0xAF, ++0x0F,0x00,0x10,0x3C, ++0xFF,0xFF,0x05,0x36, ++0x15,0x00,0x04,0x24, ++0x20,0x00,0xBF,0xAF, ++0x5F,0x47,0x00,0x0C, ++0x18,0x00,0xB2,0xAF, ++0x54,0x22,0x00,0x0C, ++0x64,0x00,0x04,0x24, ++0x10,0x03,0x26,0x8E, ++0xFF,0xFF,0x05,0x36, ++0x5F,0x47,0x00,0x0C, ++0x1A,0x00,0x04,0x24, ++0x54,0x22,0x00,0x0C, ++0x64,0x00,0x04,0x24, ++0x04,0x03,0x22,0x92, ++0x25,0xB0,0x12,0x3C, ++0x08,0x00,0x40,0x14, ++0x08,0x0E,0x44,0x36, ++0x25,0xB0,0x02,0x3C, ++0x00,0x0E,0x42,0x34, ++0x00,0x00,0x45,0x8C, ++0xEC,0x02,0x23,0x8E, ++0x00,0x00,0x00,0x00, ++0x17,0x00,0xA3,0x10, ++0x30,0x1F,0x62,0x26, ++0xE8,0x02,0x25,0x8E, ++0x43,0x60,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0xEC,0x02,0x25,0x8E, ++0x43,0x60,0x00,0x0C, ++0x00,0x0E,0x44,0x36, ++0xF0,0x02,0x25,0x8E, ++0x43,0x60,0x00,0x0C, ++0x04,0x0E,0x44,0x36, ++0xF4,0x02,0x25,0x8E, ++0x43,0x60,0x00,0x0C, ++0x10,0x0E,0x44,0x36, ++0xF8,0x02,0x25,0x8E, ++0x43,0x60,0x00,0x0C, ++0x14,0x0E,0x44,0x36, ++0xFC,0x02,0x25,0x8E, ++0x43,0x60,0x00,0x0C, ++0x18,0x0E,0x44,0x36, ++0x00,0x03,0x25,0x8E, ++0x43,0x60,0x00,0x0C, ++0x1C,0x0E,0x44,0x36, ++0x30,0x1F,0x62,0x26, ++0x20,0x00,0xBF,0x8F, ++0x1C,0x00,0xB3,0x8F, ++0x18,0x00,0xB2,0x8F, ++0x14,0x00,0xB1,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x28,0x00,0xBD,0x27, ++0x08,0x00,0xE0,0x03, ++0x04,0x03,0x40,0xA0, ++0xE0,0xFF,0xBD,0x27, ++0x18,0x00,0xB2,0xAF, ++0x02,0x80,0x12,0x3C, ++0x14,0x00,0xB1,0xAF, ++0x30,0x1F,0x51,0x26, ++0x0C,0x03,0x26,0x8E, ++0x10,0x00,0xB0,0xAF, ++0x0F,0x00,0x10,0x3C, ++0xFF,0xFF,0x05,0x36, ++0x1C,0x00,0xBF,0xAF, ++0x5F,0x47,0x00,0x0C, ++0x15,0x00,0x04,0x24, ++0x54,0x22,0x00,0x0C, ++0x64,0x00,0x04,0x24, ++0x10,0x03,0x26,0x8E, ++0xFF,0xFF,0x05,0x36, ++0x5F,0x47,0x00,0x0C, ++0x1A,0x00,0x04,0x24, ++0x54,0x22,0x00,0x0C, ++0x64,0x00,0x04,0x24, ++0x04,0x03,0x23,0x92, ++0x03,0x00,0x02,0x24, ++0x2C,0x00,0x62,0x10, ++0x25,0xB0,0x02,0x3C, ++0xEC,0x02,0x25,0x8E, ++0x25,0xB0,0x10,0x3C, ++0x43,0x60,0x00,0x0C, ++0x00,0x0E,0x04,0x36, ++0xF0,0x02,0x25,0x8E, ++0x43,0x60,0x00,0x0C, ++0x04,0x0E,0x04,0x36, ++0xF4,0x02,0x25,0x8E, ++0x43,0x60,0x00,0x0C, ++0x10,0x0E,0x04,0x36, ++0xF8,0x02,0x25,0x8E, ++0x43,0x60,0x00,0x0C, ++0x14,0x0E,0x04,0x36, ++0xFC,0x02,0x25,0x8E, ++0x43,0x60,0x00,0x0C, ++0x18,0x0E,0x04,0x36, ++0x00,0x03,0x25,0x8E, ++0x43,0x60,0x00,0x0C, ++0x1C,0x0E,0x04,0x36, ++0x08,0x03,0x24,0x8E, ++0xE8,0x02,0x22,0x8E, ++0x00,0x00,0x00,0x00, ++0x21,0x28,0x44,0x00, ++0x00,0xFF,0xA3,0x30, ++0xFF,0xFF,0x02,0x3C, ++0xFF,0x00,0x42,0x34, ++0x01,0x3F,0x63,0x2C, ++0x24,0x10,0xA2,0x00, ++0x0C,0x00,0x60,0x10, ++0x08,0x0E,0x04,0x36, ++0x43,0x60,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x30,0x1F,0x43,0x26, ++0x1C,0x00,0xBF,0x8F, ++0x18,0x00,0xB2,0x8F, ++0x14,0x00,0xB1,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x03,0x00,0x02,0x24, ++0x20,0x00,0xBD,0x27, ++0x08,0x00,0xE0,0x03, ++0x04,0x03,0x62,0xA0, ++0x32,0x2E,0x00,0x08, ++0x00,0x3F,0x45,0x34, ++0x00,0x0E,0x42,0x34, ++0x00,0x00,0x43,0x8C, ++0xEC,0x02,0x25,0x8E, ++0x00,0x00,0x00,0x00, ++0xD2,0xFF,0x65,0x14, ++0x25,0xB0,0x10,0x3C, ++0x35,0x2E,0x00,0x08, ++0x30,0x1F,0x43,0x26, ++0xD8,0xFF,0xBD,0x27, ++0x18,0x00,0xB2,0xAF, ++0x02,0x80,0x12,0x3C, ++0x20,0x00,0xB4,0xAF, ++0x24,0x00,0xBF,0xAF, ++0x1C,0x00,0xB3,0xAF, ++0x14,0x00,0xB1,0xAF, ++0x10,0x00,0xB0,0xAF, ++0x30,0x1F,0x44,0x26, ++0x0C,0x24,0x82,0x8C, ++0x30,0x1F,0x43,0x8E, ++0x04,0x03,0x93,0x90, ++0x02,0x11,0x02,0x00, ++0x7F,0x00,0x54,0x30, ++0xF0,0xF0,0x63,0x30, ++0x00,0x10,0x02,0x24, ++0x6A,0x00,0x62,0x10, ++0x01,0x00,0x02,0x24, ++0x25,0xB0,0x08,0x3C, ++0x4C,0x00,0x03,0x35, ++0x00,0x00,0x62,0x90, ++0x00,0x00,0x00,0x00, ++0x03,0x00,0x42,0x30, ++0x08,0x00,0x40,0x10, ++0x30,0x1F,0x45,0x26, ++0x30,0x1F,0x42,0x8E, ++0x00,0x00,0x00,0x00, ++0x02,0x13,0x02,0x00, ++0x0F,0x00,0x42,0x30, ++0x2F,0x00,0x40,0x10, ++0x00,0x0E,0x05,0x35, ++0x30,0x1F,0x45,0x26, ++0x04,0x03,0xA2,0x8C, ++0x00,0x00,0x00,0x00, ++0x02,0x12,0x02,0x00, ++0x0F,0x00,0x40,0x14, ++0x30,0x1F,0x42,0x26, ++0x25,0xB0,0x02,0x3C, ++0x84,0x01,0x42,0x34, ++0x00,0x00,0x44,0x8C, ++0x0D,0x00,0x03,0x24, ++0x7C,0x00,0x83,0x10, ++0x3E,0x00,0x02,0x24, ++0x4A,0x00,0x03,0x24, ++0x1F,0x03,0xA2,0xA0, ++0x1C,0x03,0xA3,0xA0, ++0x45,0x00,0x02,0x24, ++0x43,0x00,0x03,0x24, ++0x1D,0x03,0xA2,0xA0, ++0x1E,0x03,0xA3,0xA0, ++0x30,0x1F,0x42,0x26, ++0x0C,0x24,0x43,0x8C, ++0x25,0xB0,0x02,0x3C, ++0x60,0x0C,0x42,0x34, ++0x02,0x19,0x03,0x00, ++0xFF,0x00,0x63,0x30, ++0x00,0x00,0x43,0xA0, ++0x21,0x10,0x00,0x00, ++0x01,0x00,0x42,0x24, ++0xFF,0x00,0x42,0x30, ++0x06,0x00,0x43,0x2C, ++0xFD,0xFF,0x60,0x14, ++0x01,0x00,0x42,0x24, ++0x30,0x1F,0x45,0x8E, ++0x10,0x10,0x02,0x24, ++0xF0,0xF0,0xA3,0x30, ++0x3F,0x00,0x62,0x10, ++0x30,0x1F,0x44,0x26, ++0x24,0x00,0xBF,0x8F, ++0x20,0x00,0xB4,0x8F, ++0x1C,0x00,0xB3,0x8F, ++0x18,0x00,0xB2,0x8F, ++0x14,0x00,0xB1,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x21,0x10,0x00,0x00, ++0x08,0x00,0xE0,0x03, ++0x28,0x00,0xBD,0x27, ++0x00,0x00,0xA2,0x8C, ++0x00,0x00,0x00,0x00, ++0x5F,0x00,0x40,0x10, ++0x10,0x0E,0x07,0x35, ++0x00,0x60,0x01,0x40, ++0x01,0x00,0x21,0x34, ++0x01,0x00,0x21,0x38, ++0x00,0x60,0x81,0x40, ++0x08,0x0E,0x02,0x35, ++0x04,0x0E,0x03,0x35, ++0x00,0x00,0x44,0x8C, ++0x00,0x00,0xA5,0x8C, ++0x00,0x00,0x66,0x8C, ++0x02,0x80,0x02,0x3C, ++0x30,0x1F,0x49,0x24, ++0xE8,0x02,0x24,0xAD, ++0xEC,0x02,0x25,0xAD, ++0xF0,0x02,0x26,0xAD, ++0x14,0x0E,0x04,0x35, ++0x02,0x80,0x02,0x3C, ++0x18,0x0E,0x05,0x35, ++0x00,0x00,0xE7,0x8C, ++0x1C,0x0E,0x06,0x35, ++0x00,0x00,0x83,0x8C, ++0xDE,0x5D,0x4A,0x90, ++0x00,0x00,0xA2,0x8C, ++0x00,0x00,0xC4,0x8C, ++0xF4,0x02,0x27,0xAD, ++0xFC,0x02,0x22,0xAD, ++0x22,0x00,0x02,0x24, ++0xF8,0x02,0x23,0xAD, ++0x5B,0x00,0x42,0x11, ++0x00,0x03,0x24,0xAD, ++0x92,0x00,0x02,0x24, ++0x59,0x00,0x42,0x11, ++0x0D,0x08,0x02,0x35, ++0x00,0x60,0x01,0x40, ++0x01,0x00,0x21,0x34, ++0x00,0x60,0x81,0x40, ++0x30,0x1F,0x43,0x8E, ++0xFF,0xFF,0x02,0x3C, ++0xFF,0x0F,0x42,0x34, ++0x24,0x18,0x62,0x00, ++0x00,0x10,0x63,0x34, ++0x66,0x2E,0x00,0x08, ++0x30,0x1F,0x43,0xAE, ++0x3A,0x00,0x62,0x12, ++0x04,0x00,0x02,0x24, ++0x38,0x00,0x62,0x12, ++0x30,0x1F,0x43,0x26, ++0xFF,0xFF,0x02,0x24, ++0x59,0x2E,0x00,0x08, ++0x04,0x03,0x62,0xA0, ++0x0C,0x24,0x83,0x8C, ++0xFF,0xFF,0x02,0x34, ++0xBF,0xFF,0x62,0x10, ++0x02,0x12,0x05,0x00, ++0x0F,0x00,0x45,0x30, ++0x01,0x00,0x03,0x24, ++0xBB,0xFF,0xA3,0x14, ++0x25,0xB0,0x02,0x3C, ++0x4C,0x00,0x42,0x34, ++0x00,0x00,0x43,0x90, ++0x00,0x00,0x00,0x00, ++0x03,0x00,0x63,0x30, ++0xB5,0xFF,0x60,0x10, ++0x03,0x00,0x02,0x24, ++0x65,0x00,0x62,0x12, ++0x04,0x00,0x62,0x2A, ++0x47,0x00,0x40,0x10, ++0x00,0x00,0x00,0x00, ++0x6A,0x00,0x60,0x12, ++0x00,0x00,0x00,0x00, ++0xAD,0xFF,0x65,0x16, ++0x00,0x00,0x00,0x00, ++0x1C,0x03,0x82,0x90, ++0x00,0x00,0x00,0x00, ++0x2B,0x10,0x82,0x02, ++0x56,0x00,0x40,0x10, ++0x00,0x00,0x00,0x00, ++0x1F,0x03,0x82,0x90, ++0x00,0x00,0x00,0x00, ++0x2B,0x10,0x54,0x00, ++0x48,0x00,0x40,0x14, ++0x00,0x00,0x00,0x00, ++0xBE,0x2D,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x8B,0x2E,0x00,0x08, ++0x00,0x00,0x00,0x00, ++0x3B,0x00,0x02,0x24, ++0x46,0x00,0x03,0x24, ++0x1F,0x03,0xA2,0xA0, ++0x1C,0x03,0xA3,0xA0, ++0x41,0x00,0x02,0x24, ++0x40,0x00,0x03,0x24, ++0x1D,0x03,0xA2,0xA0, ++0x79,0x2E,0x00,0x08, ++0x1E,0x03,0xA3,0xA0, ++0x00,0x00,0xE3,0x8C, ++0x3F,0x3F,0x02,0x3C, ++0x3F,0x3F,0x42,0x34, ++0x9E,0xFF,0x62,0x14, ++0x00,0x00,0x00,0x00, ++0x67,0x2E,0x00,0x08, ++0x30,0x1F,0x45,0x26, ++0x0F,0x00,0x10,0x3C, ++0x01,0x00,0x11,0x3C, ++0xFF,0xFF,0x05,0x36, ++0xF4,0x98,0x26,0x36, ++0x5F,0x47,0x00,0x0C, ++0x15,0x00,0x04,0x24, ++0x54,0x22,0x00,0x0C, ++0x64,0x00,0x04,0x24, ++0xFF,0xFF,0x05,0x36, ++0x56,0x30,0x26,0x36, ++0x5F,0x47,0x00,0x0C, ++0x1A,0x00,0x04,0x24, ++0x54,0x22,0x00,0x0C, ++0x64,0x00,0x04,0x24, ++0x30,0x1F,0x43,0x26, ++0xFF,0xFF,0x02,0x24, ++0x59,0x2E,0x00,0x08, ++0x04,0x03,0x62,0xA0, ++0x0D,0x08,0x02,0x35, ++0x00,0x00,0x43,0x90, ++0x00,0x00,0x00,0x00, ++0x0F,0x00,0x63,0x30, ++0x08,0x00,0x62,0x2C, ++0x0F,0x00,0x63,0x38, ++0xA2,0xFF,0x40,0x14, ++0x01,0x00,0x65,0x24, ++0x00,0x16,0x05,0x00, ++0x00,0x24,0x05,0x00, ++0x00,0x1A,0x05,0x00, ++0x25,0x10,0x44,0x00, ++0x25,0x10,0x43,0x00, ++0x25,0x10,0x45,0x00, ++0x25,0x18,0x65,0x00, ++0x18,0x03,0x23,0xAD, ++0xB8,0x2E,0x00,0x08, ++0x14,0x03,0x22,0xAD, ++0x04,0x00,0x02,0x24, ++0x11,0x00,0x62,0x12, ++0xFF,0x00,0x02,0x24, ++0x66,0xFF,0x62,0x16, ++0x00,0x00,0x00,0x00, ++0x1E,0x03,0x82,0x90, ++0x00,0x00,0x00,0x00, ++0x2B,0x10,0x82,0x02, ++0x21,0x00,0x40,0x14, ++0x00,0x00,0x00,0x00, ++0x1C,0x03,0x82,0x90, ++0x00,0x00,0x00,0x00, ++0x2B,0x10,0x82,0x02, ++0x0A,0x00,0x40,0x10, ++0x00,0x00,0x00,0x00, ++0x7A,0x2D,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x8B,0x2E,0x00,0x08, ++0x00,0x00,0x00,0x00, ++0x1D,0x03,0x82,0x90, ++0x00,0x00,0x00,0x00, ++0x2B,0x10,0x54,0x00, ++0xF8,0xFF,0x40,0x10, ++0x00,0x00,0x00,0x00, ++0x3B,0x2D,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x8B,0x2E,0x00,0x08, ++0x00,0x00,0x00,0x00, ++0x20,0x03,0x82,0x90, ++0x00,0x00,0x00,0x00, ++0x2B,0x10,0x82,0x02, ++0xA8,0xFF,0x40,0x10, ++0x00,0x00,0x00,0x00, ++0xFC,0x2D,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x8B,0x2E,0x00,0x08, ++0x00,0x00,0x00,0x00, ++0x1E,0x03,0x82,0x90, ++0x00,0x00,0x00,0x00, ++0x2B,0x10,0x82,0x02, ++0xE6,0xFF,0x40,0x10, ++0x00,0x00,0x00,0x00, ++0x21,0x03,0x82,0x90, ++0x00,0x00,0x00,0x00, ++0x2B,0x10,0x54,0x00, ++0x9A,0xFF,0x40,0x14, ++0x00,0x00,0x00,0x00, ++0xFC,0x2D,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x8B,0x2E,0x00,0x08, ++0x00,0x00,0x00,0x00, ++0x02,0x80,0x08,0x3C, ++0x30,0x1F,0x05,0x25, ++0x80,0x36,0xA4,0x8C, ++0xE6,0x02,0xA3,0x90, ++0x02,0x11,0x04,0x00, ++0x26,0x00,0x60,0x14, ++0x7F,0x00,0x46,0x30, ++0x25,0xB0,0x07,0x3C, ++0x4C,0x00,0xE2,0x34, ++0x00,0x00,0x43,0x90, ++0x00,0x00,0x00,0x00, ++0x20,0x00,0x60,0x10, ++0x00,0x00,0x00,0x00, ++0xFF,0xFF,0x02,0x34, ++0x1D,0x00,0x82,0x10, ++0x00,0x00,0x00,0x00, ++0x00,0x08,0xE3,0x34, ++0x00,0x00,0x62,0x90, ++0x00,0x00,0x00,0x00, ++0x01,0x00,0x42,0x30, ++0x19,0x00,0x40,0x10, ++0x4B,0x00,0xC2,0x2C, ++0x3E,0x00,0x40,0x10, ++0x01,0x00,0x04,0x24, ++0xD8,0xFF,0xC2,0x24, ++0x1E,0x00,0x42,0x2C, ++0x49,0x00,0x40,0x10, ++0x23,0x00,0xC2,0x2C, ++0x30,0x1F,0x04,0x25, ++0xD3,0x02,0x82,0x90, ++0x00,0x00,0x00,0x00, ++0x44,0x00,0x40,0x10, ++0x23,0x00,0xC2,0x2C, ++0x25,0xB0,0x02,0x3C, ++0x87,0x0C,0x42,0x34, ++0x20,0x00,0x03,0x24, ++0x00,0x00,0x43,0xA0, ++0xD3,0x02,0x80,0xA0, ++0x21,0x10,0x00,0x00, ++0x01,0x00,0x42,0x24, ++0xFF,0x00,0x42,0x30, ++0x06,0x00,0x43,0x2C, ++0xFC,0xFF,0x60,0x14, ++0x00,0x00,0x00,0x00, ++0x08,0x00,0xE0,0x03, ++0x21,0x10,0x00,0x00, ++0x17,0x00,0x40,0x10, ++0x01,0x00,0x04,0x24, ++0xD8,0xFF,0xC2,0x24, ++0x1E,0x00,0x42,0x2C, ++0x44,0x00,0x40,0x10, ++0x23,0x00,0xC2,0x2C, ++0x30,0x1F,0x04,0x25, ++0xD3,0x02,0x82,0x90, ++0x00,0x00,0x00,0x00, ++0x3F,0x00,0x40,0x10, ++0x23,0x00,0xC2,0x2C, ++0x25,0xB0,0x02,0x3C, ++0x30,0x0C,0x42,0x34, ++0x44,0x00,0x03,0x24, ++0x00,0x00,0x43,0xA0, ++0xD3,0x02,0x80,0xA0, ++0x21,0x10,0x00,0x00, ++0x01,0x00,0x42,0x24, ++0xFF,0x00,0x42,0x30, ++0x06,0x00,0x43,0x2C, ++0xFC,0xFF,0x60,0x14, ++0x00,0x00,0x00,0x00, ++0x08,0x00,0xE0,0x03, ++0x21,0x10,0x00,0x00, ++0xD3,0x02,0xA2,0x90, ++0x00,0x00,0x00,0x00, ++0xE7,0xFF,0x44,0x10, ++0x43,0x00,0x02,0x24, ++0x30,0x0C,0xE3,0x34, ++0xD3,0x02,0xA4,0xA0, ++0x00,0x00,0x62,0xA0, ++0x21,0x10,0x00,0x00, ++0x01,0x00,0x42,0x24, ++0xFF,0x00,0x42,0x30, ++0x06,0x00,0x43,0x2C, ++0xFC,0xFF,0x60,0x14, ++0x00,0x00,0x00,0x00, ++0x08,0x00,0xE0,0x03, ++0x21,0x10,0x00,0x00, ++0xD3,0x02,0xA2,0x90, ++0x00,0x00,0x00,0x00, ++0xC0,0xFF,0x44,0x10, ++0x10,0x00,0x02,0x24, ++0x87,0x0C,0xE3,0x34, ++0xD3,0x02,0xA4,0xA0, ++0x00,0x00,0x62,0xA0, ++0x21,0x10,0x00,0x00, ++0x01,0x00,0x42,0x24, ++0xFF,0x00,0x42,0x30, ++0x06,0x00,0x43,0x2C, ++0xFC,0xFF,0x60,0x14, ++0x00,0x00,0x00,0x00, ++0x08,0x00,0xE0,0x03, ++0x21,0x10,0x00,0x00, ++0xC7,0xFF,0x40,0x10, ++0x00,0x00,0x00,0x00, ++0x30,0x1F,0x04,0x25, ++0xD3,0x02,0x82,0x90, ++0x02,0x00,0x03,0x24, ++0xC2,0xFF,0x43,0x10, ++0x00,0x00,0x00,0x00, ++0x25,0xB0,0x02,0x3C, ++0x87,0x0C,0x42,0x34, ++0xD3,0x02,0x83,0xA0, ++0x00,0x00,0x40,0xA0, ++0x21,0x10,0x00,0x00, ++0x01,0x00,0x42,0x24, ++0xFF,0x00,0x42,0x30, ++0x06,0x00,0x43,0x2C, ++0xFC,0xFF,0x60,0x14, ++0x00,0x00,0x00,0x00, ++0x08,0x00,0xE0,0x03, ++0x21,0x10,0x00,0x00, ++0xB4,0xFF,0x40,0x10, ++0x00,0x00,0x00,0x00, ++0x30,0x1F,0x04,0x25, ++0xD3,0x02,0x82,0x90, ++0x02,0x00,0x03,0x24, ++0xAF,0xFF,0x43,0x10, ++0x00,0x00,0x00,0x00, ++0x25,0xB0,0x02,0x3C, ++0xD3,0x02,0x83,0xA0, ++0x30,0x0C,0x42,0x34, ++0x42,0x00,0x03,0x24, ++0x00,0x00,0x43,0xA0, ++0x21,0x10,0x00,0x00, ++0x01,0x00,0x42,0x24, ++0xFF,0x00,0x42,0x30, ++0x06,0x00,0x43,0x2C, ++0xFC,0xFF,0x60,0x14, ++0x00,0x00,0x00,0x00, ++0x08,0x00,0xE0,0x03, ++0x21,0x10,0x00,0x00, ++0x25,0xB0,0x03,0x3C, ++0x01,0x80,0x02,0x3C, ++0x18,0x03,0x64,0x34, ++0x7C,0xBF,0x42,0x24, ++0x00,0x00,0x82,0xAC, ++0x00,0x60,0x07,0x40, ++0x01,0x00,0xE1,0x34, ++0x01,0x00,0x21,0x38, ++0x00,0x60,0x81,0x40, ++0x20,0x80,0x02,0x3C, ++0x30,0x03,0x63,0x34, ++0x00,0x00,0x62,0xAC, ++0x25,0xB0,0x06,0x3C, ++0x01,0x80,0x02,0x3C, ++0x7D,0xBF,0x45,0x24, ++0x33,0x03,0xC3,0x34, ++0x00,0x00,0x85,0xAC, ++0x00,0x00,0x62,0x90, ++0x00,0x00,0x00,0x00, ++0x40,0x00,0x42,0x30, ++0xFB,0xFF,0x40,0x10, ++0x30,0x03,0xC2,0x34, ++0x00,0x00,0x45,0x8C, ++0x0F,0x00,0x03,0x3C, ++0xFF,0xFF,0x63,0x34, ++0x24,0x28,0xA3,0x00, ++0x40,0x11,0x05,0x00, ++0x23,0x10,0x45,0x00, ++0x80,0x10,0x02,0x00, ++0x21,0x10,0x45,0x00, ++0xAF,0x0F,0x04,0x3C, ++0xC0,0x10,0x02,0x00, ++0x00,0xA0,0x84,0x34, ++0x1B,0x00,0x82,0x00, ++0x02,0x00,0x40,0x14, ++0x00,0x00,0x00,0x00, ++0x0D,0x00,0x07,0x00, ++0x02,0x80,0x03,0x3C, ++0x30,0x1F,0x63,0x24, ++0xC2,0x28,0x05,0x00, ++0xA0,0x3E,0x65,0xAC, ++0x12,0x20,0x00,0x00, ++0xA4,0x3E,0x64,0xAC, ++0x00,0x60,0x87,0x40, ++0x08,0x00,0xE0,0x03, ++0x00,0x00,0x00,0x00, ++0x01,0x00,0x03,0x24, ++0x02,0x80,0x02,0x3C, ++0x14,0x5F,0x43,0xA0, ++0xD0,0x07,0x04,0x24, ++0x02,0x80,0x02,0x3C, ++0x02,0x80,0x03,0x3C, ++0xE4,0x5E,0x44,0xAC, ++0x13,0x5F,0x60,0xA0, ++0x08,0x00,0xE0,0x03, ++0x00,0x00,0x00,0x00, ++0x2A,0xB0,0x04,0x3C, ++0x28,0x00,0x85,0x34, ++0x02,0x00,0x82,0x94, ++0x04,0x00,0x84,0x24, ++0x05,0x00,0x40,0x14, ++0x2B,0x18,0xA4,0x00, ++0xFB,0xFF,0x60,0x10, ++0x01,0x00,0x02,0x24, ++0x08,0x00,0xE0,0x03, ++0x00,0x00,0x00,0x00, ++0x08,0x00,0xE0,0x03, ++0x21,0x10,0x00,0x00, ++0x25,0xB0,0x03,0x3C, ++0xBE,0x00,0x63,0x34, ++0x00,0x00,0x62,0x94, ++0x08,0x00,0xE0,0x03, ++0x01,0x00,0x42,0x2C, ++0xE8,0xFF,0xBD,0x27, ++0x10,0x00,0xBF,0xAF, ++0x17,0x30,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x02,0x80,0x03,0x3C, ++0x19,0x00,0x40,0x10, ++0x74,0x57,0x64,0x24, ++0x74,0x57,0x62,0x8C, ++0x00,0x00,0x00,0x00, ++0x15,0x00,0x44,0x14, ++0x02,0x80,0x02,0x3C, ++0x14,0x5F,0x43,0x90, ++0x01,0x00,0x02,0x24, ++0xFF,0x00,0x63,0x30, ++0x10,0x00,0x62,0x10, ++0x02,0x80,0x03,0x3C, ++0xF5,0x5E,0x62,0x90, ++0x00,0x00,0x00,0x00, ++0x0F,0x00,0x42,0x30, ++0x05,0x00,0x42,0x28, ++0x0A,0x00,0x40,0x10, ++0x01,0x00,0x04,0x24, ++0x02,0x80,0x02,0x3C, ++0x9C,0x5A,0x43,0x8C, ++0x00,0x00,0x00,0x00, ++0x05,0x00,0x60,0x14, ++0x21,0x10,0x80,0x00, ++0x10,0x00,0xBF,0x8F, ++0x00,0x00,0x00,0x00, ++0x08,0x00,0xE0,0x03, ++0x18,0x00,0xBD,0x27, ++0x10,0x00,0xBF,0x8F, ++0x21,0x20,0x00,0x00, ++0x21,0x10,0x80,0x00, ++0x08,0x00,0xE0,0x03, ++0x18,0x00,0xBD,0x27, ++0xE8,0xFF,0xBD,0x27, ++0x10,0x00,0xBF,0xAF, ++0x17,0x30,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x2C,0x00,0x40,0x10, ++0x02,0x80,0x02,0x3C, ++0x74,0x57,0x43,0x8C, ++0x74,0x57,0x42,0x24, ++0x28,0x00,0x62,0x14, ++0x02,0x80,0x03,0x3C, ++0x0C,0x5F,0x62,0x90, ++0x01,0x00,0x04,0x24, ++0xFF,0x00,0x42,0x30, ++0x23,0x00,0x44,0x10, ++0x02,0x80,0x03,0x3C, ++0xF5,0x5E,0x62,0x90, ++0x00,0x00,0x00,0x00, ++0x0F,0x00,0x42,0x30, ++0x03,0x00,0x42,0x28, ++0x1D,0x00,0x40,0x10, ++0x02,0x80,0x03,0x3C, ++0x0E,0x5F,0x62,0x90, ++0x00,0x00,0x00,0x00, ++0x04,0x00,0x42,0x30, ++0x18,0x00,0x40,0x14, ++0x00,0x00,0x00,0x00, ++0x0E,0x5F,0x62,0x90, ++0x00,0x00,0x00,0x00, ++0x10,0x00,0x42,0x30, ++0x13,0x00,0x40,0x14, ++0x02,0x80,0x03,0x3C, ++0x14,0x5F,0x62,0x90, ++0x00,0x00,0x00,0x00, ++0xFF,0x00,0x42,0x30, ++0x0E,0x00,0x44,0x10, ++0x02,0x80,0x02,0x3C, ++0x15,0x5F,0x43,0x90, ++0x00,0x00,0x00,0x00, ++0x0A,0x00,0x60,0x14, ++0x02,0x80,0x02,0x3C, ++0x30,0x1F,0x42,0x24, ++0x6C,0x3B,0x43,0x8C, ++0x00,0x00,0x00,0x00, ++0x06,0x00,0x60,0x14, ++0x21,0x18,0x00,0x00, ++0x40,0x39,0x42,0x8C, ++0x00,0x00,0x00,0x00, ++0x02,0x00,0x40,0x14, ++0x01,0x00,0x03,0x24, ++0x21,0x18,0x00,0x00, ++0x10,0x00,0xBF,0x8F, ++0x21,0x10,0x60,0x00, ++0x08,0x00,0xE0,0x03, ++0x18,0x00,0xBD,0x27, ++0xE8,0xFF,0xBD,0x27, ++0x10,0x00,0xBF,0xAF, ++0x23,0x30,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x02,0x80,0x03,0x3C, ++0x0E,0x00,0x40,0x10, ++0x6C,0x57,0x65,0x24, ++0x6C,0x57,0x62,0x8C, ++0x02,0x80,0x04,0x3C, ++0x64,0x57,0x86,0x24, ++0x09,0x00,0x45,0x14, ++0x01,0x00,0x03,0x24, ++0x64,0x57,0x82,0x8C, ++0x00,0x00,0x00,0x00, ++0x05,0x00,0x46,0x14, ++0x21,0x10,0x60,0x00, ++0x10,0x00,0xBF,0x8F, ++0x00,0x00,0x00,0x00, ++0x08,0x00,0xE0,0x03, ++0x18,0x00,0xBD,0x27, ++0x10,0x00,0xBF,0x8F, ++0x21,0x18,0x00,0x00, ++0x21,0x10,0x60,0x00, ++0x08,0x00,0xE0,0x03, ++0x18,0x00,0xBD,0x27, ++0xD8,0xFF,0xBD,0x27, ++0x20,0x00,0xBF,0xAF, ++0x1C,0x00,0xB3,0xAF, ++0x18,0x00,0xB2,0xAF, ++0x14,0x00,0xB1,0xAF, ++0x10,0x00,0xB0,0xAF, ++0xFF,0x00,0x84,0x30, ++0x00,0x60,0x12,0x40, ++0x01,0x00,0x41,0x36, ++0x01,0x00,0x21,0x38, ++0x00,0x60,0x81,0x40, ++0x0E,0x00,0x80,0x10, ++0x02,0x80,0x13,0x3C, ++0x44,0x5F,0x62,0x92, ++0x01,0x00,0x03,0x24, ++0xFF,0x00,0x42,0x30, ++0x39,0x00,0x43,0x10, ++0x25,0xB0,0x03,0x3C, ++0x00,0x60,0x92,0x40, ++0x20,0x00,0xBF,0x8F, ++0x1C,0x00,0xB3,0x8F, ++0x18,0x00,0xB2,0x8F, ++0x14,0x00,0xB1,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x08,0x00,0xE0,0x03, ++0x28,0x00,0xBD,0x27, ++0x44,0x5F,0x62,0x92, ++0x02,0x00,0x03,0x24, ++0xFF,0x00,0x42,0x30, ++0xF4,0xFF,0x43,0x14, ++0x44,0x08,0x04,0x24, ++0x94,0x60,0x00,0x0C, ++0x21,0x28,0x00,0x00, ++0x25,0xB0,0x03,0x3C, ++0x04,0x0C,0x62,0x90, ++0x21,0x20,0x00,0x00, ++0xFD,0x00,0x42,0x30, ++0x04,0x0C,0x62,0xA0, ++0x01,0x00,0x82,0x24, ++0xFF,0x00,0x44,0x30, ++0x06,0x00,0x83,0x2C, ++0xFD,0xFF,0x60,0x14, ++0x01,0x00,0x82,0x24, ++0x25,0xB0,0x03,0x3C, ++0x04,0x0D,0x62,0x90, ++0x21,0x20,0x00,0x00, ++0xFD,0x00,0x42,0x30, ++0x04,0x0D,0x62,0xA0, ++0x01,0x00,0x82,0x24, ++0xFF,0x00,0x44,0x30, ++0x06,0x00,0x83,0x2C, ++0xFD,0xFF,0x60,0x14, ++0x01,0x00,0x82,0x24, ++0x25,0xB0,0x11,0x3C, ++0x70,0x0E,0x25,0x8E, ++0x7F,0xFE,0x10,0x3C, ++0xFF,0xFF,0x10,0x36, ++0x24,0x28,0xB0,0x00, ++0x94,0x60,0x00,0x0C, ++0x70,0x0E,0x04,0x24, ++0x8C,0x0E,0x25,0x8E, ++0x8C,0x0E,0x04,0x24, ++0x94,0x60,0x00,0x0C, ++0x24,0x28,0xB0,0x00, ++0x01,0x00,0x02,0x24, ++0x44,0x5F,0x62,0xA2, ++0x00,0x60,0x92,0x40, ++0x20,0x00,0xBF,0x8F, ++0x1C,0x00,0xB3,0x8F, ++0x18,0x00,0xB2,0x8F, ++0x14,0x00,0xB1,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x08,0x00,0xE0,0x03, ++0x28,0x00,0xBD,0x27, ++0x04,0x0C,0x62,0x90, ++0x21,0x20,0x00,0x00, ++0xFF,0x00,0x42,0x30, ++0x02,0x00,0x42,0x34, ++0x04,0x0C,0x62,0xA0, ++0x01,0x00,0x82,0x24, ++0xFF,0x00,0x44,0x30, ++0x06,0x00,0x83,0x2C, ++0xFD,0xFF,0x60,0x14, ++0x01,0x00,0x82,0x24, ++0x25,0xB0,0x03,0x3C, ++0x04,0x0D,0x62,0x90, ++0x21,0x20,0x00,0x00, ++0xFF,0x00,0x42,0x30, ++0x02,0x00,0x42,0x34, ++0x04,0x0D,0x62,0xA0, ++0x01,0x00,0x82,0x24, ++0xFF,0x00,0x44,0x30, ++0x06,0x00,0x83,0x2C, ++0xFD,0xFF,0x60,0x14, ++0x01,0x00,0x82,0x24, ++0x25,0xB0,0x10,0x3C, ++0x70,0x0E,0x05,0x8E, ++0x80,0x01,0x11,0x3C, ++0x70,0x0E,0x04,0x24, ++0x94,0x60,0x00,0x0C, ++0x25,0x28,0xB1,0x00, ++0x8C,0x0E,0x05,0x8E, ++0x8C,0x0E,0x04,0x24, ++0x94,0x60,0x00,0x0C, ++0x25,0x28,0xB1,0x00, ++0x03,0x00,0x05,0x3C, ++0x59,0x01,0xA5,0x34, ++0x94,0x60,0x00,0x0C, ++0x44,0x08,0x04,0x24, ++0x02,0x00,0x02,0x24, ++0x44,0x5F,0x62,0xA2, ++0xDD,0x30,0x00,0x08, ++0x00,0x00,0x00,0x00, ++0x25,0xB0,0x03,0x3C, ++0xFC,0x37,0x02,0x24, ++0x40,0x00,0x64,0x34, ++0x00,0x00,0x82,0xA4, ++0x42,0x00,0x65,0x34, ++0x03,0x00,0x02,0x24, ++0x00,0x00,0xA0,0xA0, ++0x03,0x08,0x62,0xA0, ++0x21,0x10,0x00,0x00, ++0x01,0x00,0x42,0x24, ++0xFF,0x00,0x42,0x30, ++0x06,0x00,0x43,0x2C, ++0xFC,0xFF,0x60,0x14, ++0x00,0x00,0x00,0x00, ++0x08,0x00,0xE0,0x03, ++0x00,0x00,0x00,0x00, ++0xE0,0xFF,0xBD,0x27, ++0x18,0x00,0xBF,0xAF, ++0x14,0x00,0xB1,0xAF, ++0x10,0x00,0xB0,0xAF, ++0x02,0x80,0x02,0x3C, ++0xF4,0x5E,0x43,0x90, ++0x00,0x00,0x00,0x00, ++0x0B,0x00,0x60,0x10, ++0x25,0xB0,0x10,0x3C, ++0x02,0x80,0x03,0x3C, ++0xDE,0x5D,0x62,0x90, ++0x00,0x00,0x00,0x00, ++0x02,0x00,0x42,0x30, ++0x32,0x00,0x40,0x14, ++0x00,0x02,0x05,0x3C, ++0x00,0x08,0x04,0x24, ++0xA9,0x45,0x00,0x0C, ++0x21,0x30,0x00,0x00, ++0x25,0xB0,0x10,0x3C, ++0x21,0x00,0x06,0x36, ++0x00,0x00,0xC2,0x90, ++0x18,0x00,0x03,0x36, ++0x42,0x00,0x05,0x36, ++0x01,0x00,0x42,0x34, ++0x00,0x00,0xC2,0xA0, ++0x40,0x00,0x11,0x36, ++0x00,0x00,0x60,0xA0, ++0xFF,0xFF,0x02,0x24, ++0xFC,0x57,0x03,0x24, ++0x00,0x00,0xA2,0xA0, ++0x64,0x00,0x04,0x24, ++0x00,0x00,0x23,0xA6, ++0x54,0x22,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0xFC,0x77,0x02,0x24, ++0x00,0x00,0x22,0xA6, ++0x54,0x22,0x00,0x0C, ++0x0A,0x00,0x04,0x24, ++0x03,0x08,0x00,0xA2, ++0x21,0x10,0x00,0x00, ++0x01,0x00,0x42,0x24, ++0xFF,0x00,0x42,0x30, ++0x06,0x00,0x43,0x2C, ++0xFD,0xFF,0x60,0x14, ++0x01,0x00,0x42,0x24, ++0x0A,0x00,0x04,0x24, ++0x54,0x22,0x00,0x0C, ++0x25,0xB0,0x10,0x3C, ++0x40,0x00,0x10,0x36, ++0xFC,0x37,0x02,0x24, ++0x00,0x00,0x02,0xA6, ++0x54,0x22,0x00,0x0C, ++0x0A,0x00,0x04,0x24, ++0xFC,0x77,0x02,0x24, ++0x00,0x00,0x02,0xA6, ++0x54,0x22,0x00,0x0C, ++0x0A,0x00,0x04,0x24, ++0xFC,0x57,0x02,0x24, ++0x00,0x00,0x02,0xA6, ++0x18,0x00,0xBF,0x8F, ++0x14,0x00,0xB1,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x08,0x00,0xE0,0x03, ++0x20,0x00,0xBD,0x27, ++0x9B,0x30,0x00,0x0C, ++0x21,0x20,0x00,0x00, ++0x00,0x08,0x04,0x24, ++0x00,0x02,0x05,0x3C, ++0xA9,0x45,0x00,0x0C, ++0x21,0x30,0x00,0x00, ++0x2F,0x31,0x00,0x08, ++0x25,0xB0,0x10,0x3C, ++0xC0,0xFF,0xBD,0x27, ++0x28,0x00,0xB4,0xAF, ++0x20,0x00,0xB2,0xAF, ++0x18,0x00,0xB0,0xAF, ++0x3C,0x00,0xBF,0xAF, ++0x38,0x00,0xBE,0xAF, ++0x34,0x00,0xB7,0xAF, ++0x30,0x00,0xB6,0xAF, ++0x2C,0x00,0xB5,0xAF, ++0x24,0x00,0xB3,0xAF, ++0x1C,0x00,0xB1,0xAF, ++0xFF,0x00,0x90,0x30, ++0xFF,0x00,0xB2,0x30, ++0x21,0xA0,0x00,0x00, ++0x00,0x60,0x16,0x40, ++0x01,0x00,0xC1,0x36, ++0x01,0x00,0x21,0x38, ++0x00,0x60,0x81,0x40, ++0x02,0x80,0x13,0x3C, ++0xF6,0x5E,0x62,0x92, ++0x0F,0x00,0x11,0x32, ++0x0F,0x00,0x42,0x30, ++0x12,0x00,0x51,0x10, ++0x04,0x00,0x02,0x32, ++0x40,0x00,0x40,0x14, ++0x00,0x00,0x00,0x00, ++0xF6,0x5E,0x62,0x92, ++0x0C,0x00,0x03,0x24, ++0x0F,0x00,0x42,0x30, ++0x8F,0x00,0x43,0x10, ++0x08,0x00,0x02,0x32, ++0xF6,0x5E,0x62,0x92, ++0x04,0x00,0x03,0x24, ++0x0F,0x00,0x42,0x30, ++0xD2,0x01,0x43,0x10, ++0x00,0x00,0x00,0x00, ++0xF6,0x5E,0x62,0x92, ++0x02,0x00,0x03,0x24, ++0x0F,0x00,0x42,0x30, ++0x9B,0x00,0x43,0x10, ++0x06,0x00,0x02,0x32, ++0x02,0x80,0x10,0x3C, ++0xF5,0x5E,0x03,0x92, ++0xF6,0x5E,0x62,0x92, ++0x0F,0x00,0x63,0x30, ++0x0F,0x00,0x42,0x30, ++0x2A,0x10,0x43,0x00, ++0x1C,0x00,0x40,0x14, ++0x02,0x80,0x12,0x3C, ++0xF5,0x5E,0x02,0x92, ++0x00,0x00,0x00,0x00, ++0x40,0x00,0x42,0x30, ++0x17,0x00,0x40,0x10, ++0x02,0x80,0x02,0x3C, ++0xDA,0x5D,0x42,0x90, ++0x00,0x00,0x00,0x00, ++0x02,0x00,0x43,0x30, ++0x52,0x00,0x60,0x14, ++0x04,0x00,0x42,0x30, ++0x10,0x00,0x40,0x10, ++0x00,0x00,0x00,0x00, ++0xF6,0x5E,0x43,0x92, ++0x02,0x80,0x06,0x3C, ++0x5C,0xE9,0xC5,0x90, ++0x0F,0x00,0x63,0x30, ++0x25,0xB0,0x02,0x3C, ++0x25,0x18,0x65,0x00, ++0xDD,0x02,0x42,0x34, ++0x00,0x00,0x43,0xA0, ++0xF5,0x5E,0x04,0x92, ++0x80,0xFF,0x02,0x24, ++0xBF,0xFF,0x03,0x24, ++0x26,0x28,0xA2,0x00, ++0x24,0x20,0x83,0x00, ++0x5C,0xE9,0xC5,0xA0, ++0xF5,0x5E,0x04,0xA2, ++0x00,0x60,0x96,0x40, ++0x3C,0x00,0xBF,0x8F, ++0x38,0x00,0xBE,0x8F, ++0x34,0x00,0xB7,0x8F, ++0x30,0x00,0xB6,0x8F, ++0x2C,0x00,0xB5,0x8F, ++0x28,0x00,0xB4,0x8F, ++0x24,0x00,0xB3,0x8F, ++0x20,0x00,0xB2,0x8F, ++0x1C,0x00,0xB1,0x8F, ++0x18,0x00,0xB0,0x8F, ++0x08,0x00,0xE0,0x03, ++0x40,0x00,0xBD,0x27, ++0xF6,0x5E,0x62,0x92, ++0x00,0x00,0x00,0x00, ++0x04,0x00,0x42,0x30, ++0x4C,0x00,0x40,0x10, ++0x00,0x00,0x00,0x00, ++0xF6,0x5E,0x62,0x92, ++0x00,0x00,0x00,0x00, ++0x08,0x00,0x42,0x30, ++0x03,0x00,0x40,0x10, ++0x08,0x00,0x02,0x32, ++0x1B,0x00,0x40,0x10, ++0x02,0x80,0x03,0x3C, ++0xF6,0x5E,0x62,0x92, ++0x00,0x00,0x00,0x00, ++0x08,0x00,0x42,0x30, ++0x0C,0x00,0x40,0x14, ++0x08,0x00,0x02,0x32, ++0x0A,0x00,0x40,0x10, ++0x00,0x00,0x00,0x00, ++0x08,0x00,0x40,0x12, ++0x02,0x80,0x03,0x3C, ++0xE0,0x3A,0x62,0x94, ++0x00,0x00,0x00,0x00, ++0x00,0x01,0x42,0x30, ++0x03,0x00,0x40,0x10, ++0x00,0x00,0x00,0x00, ++0xCD,0x4E,0x00,0x0C, ++0x21,0x20,0x00,0x00, ++0xF6,0x5E,0x62,0x92, ++0xF0,0xFF,0x03,0x24, ++0x24,0x10,0x43,0x00, ++0xF6,0x5E,0x62,0xA2, ++0xF6,0x5E,0x63,0x92, ++0x00,0x00,0x00,0x00, ++0x25,0x18,0x23,0x02, ++0xF6,0x5E,0x63,0xA2, ++0x8E,0x31,0x00,0x08, ++0x02,0x80,0x10,0x3C, ++0xE0,0x3A,0x62,0x94, ++0x00,0x00,0x00,0x00, ++0x00,0x01,0x42,0x30, ++0xF2,0xFF,0x40,0x10, ++0x02,0x80,0x02,0x3C, ++0x14,0x5F,0x43,0x90, ++0x00,0x00,0x00,0x00, ++0xA2,0xFF,0x60,0x14, ++0x01,0x00,0x04,0x24, ++0xCD,0x4E,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0xD9,0x31,0x00,0x08, ++0x00,0x00,0x00,0x00, ++0x25,0x24,0x00,0x0C, ++0x24,0x00,0x04,0x24, ++0x76,0x01,0x40,0x10, ++0x21,0x88,0x40,0x00, ++0x02,0x80,0x02,0x3C, ++0xF4,0x5E,0x45,0x90, ++0xF6,0x5E,0x44,0x92, ++0xF5,0x5E,0x02,0x92, ++0xBF,0xFF,0x03,0x24, ++0x0F,0x00,0x84,0x30, ++0x24,0x10,0x43,0x00, ++0xF5,0x5E,0x02,0xA2, ++0x10,0x00,0xA5,0xA3, ++0x11,0x00,0xA4,0xA3, ++0x08,0x00,0x24,0x96, ++0x02,0x80,0x02,0x3C, ++0x10,0x00,0xA5,0x27, ++0x25,0x20,0x82,0x00, ++0x20,0x00,0x84,0x24, ++0x5F,0x1E,0x00,0x0C, ++0x01,0x00,0x06,0x24, ++0x04,0x00,0x03,0x24, ++0x17,0x00,0x02,0x24, ++0x0C,0x00,0x23,0xAE, ++0x14,0x00,0x22,0xAE, ++0x30,0x09,0x00,0x0C, ++0x21,0x20,0x20,0x02, ++0xB0,0x31,0x00,0x08, ++0x00,0x00,0x00,0x00, ++0x0C,0x31,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0xC2,0x31,0x00,0x08, ++0x00,0x00,0x00,0x00, ++0x71,0xFF,0x40,0x14, ++0x00,0x00,0x00,0x00, ++0x28,0x30,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x77,0xFF,0x40,0x10, ++0x00,0x00,0x00,0x00, ++0xF6,0x5E,0x62,0x92, ++0xF0,0xFF,0x03,0x24, ++0x24,0x10,0x43,0x00, ++0xF6,0x5E,0x62,0xA2, ++0x02,0x80,0x03,0x3C, ++0xF6,0x5E,0x62,0x92, ++0xE0,0x3A,0x64,0x94, ++0x04,0x00,0x42,0x34, ++0x00,0x01,0x84,0x30, ++0xF6,0x5E,0x62,0xA2, ++0x61,0xFF,0x80,0x10, ++0x00,0x00,0x00,0x00, ++0xCD,0x4E,0x00,0x0C, ++0x01,0x00,0x04,0x24, ++0x83,0x31,0x00,0x08, ++0x00,0x00,0x00,0x00, ++0x65,0xFF,0x40,0x14, ++0x00,0x00,0x00,0x00, ++0x82,0x30,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x61,0xFF,0x40,0x10, ++0x00,0x00,0x00,0x00, ++0xF6,0x5E,0x62,0x92, ++0xF0,0xFF,0x03,0x24, ++0x41,0xB0,0x04,0x3C, ++0x24,0x10,0x43,0x00, ++0xF6,0x5E,0x62,0xA2, ++0xF6,0x5E,0x63,0x92, ++0x08,0x00,0x85,0x34, ++0x82,0x00,0x02,0x24, ++0x01,0x00,0x63,0x34, ++0x02,0x80,0x1E,0x3C, ++0xF6,0x5E,0x63,0xA2, ++0x00,0x00,0x80,0xAC, ++0x00,0x00,0xA2,0xA4, ++0x42,0xB0,0x04,0x3C, ++0x30,0x1F,0xC2,0x27, ++0xB0,0x1B,0x45,0x94, ++0x00,0x00,0x83,0x90, ++0xBE,0xFF,0x02,0x24, ++0x03,0x00,0x86,0x34, ++0x24,0x18,0x62,0x00, ++0x00,0x01,0xA5,0x30, ++0x90,0xFF,0x02,0x24, ++0x00,0x00,0x83,0xA0, ++0x00,0x00,0xC2,0xA0, ++0x38,0x00,0xA0,0x10, ++0x25,0xB0,0x06,0x3C, ++0x25,0xB0,0x04,0x3C, ++0x84,0x00,0x82,0x34, ++0x00,0x00,0x46,0x8C, ++0x80,0x00,0x84,0x34, ++0x00,0x00,0x82,0x8C, ++0x02,0x80,0x0B,0x3C, ++0x1C,0x5F,0x64,0x8D, ++0x00,0x38,0x06,0x00, ++0x21,0x30,0x00,0x00, ++0x25,0xA0,0xC2,0x00, ++0x21,0x18,0x00,0x00, ++0x02,0x80,0x0A,0x3C, ++0x25,0xA8,0xE3,0x00, ++0x21,0x28,0x00,0x00, ++0x24,0x5F,0x42,0x8D, ++0x21,0x20,0x94,0x00, ++0x2B,0x18,0x94,0x00, ++0x21,0x28,0xB5,0x00, ++0x21,0x28,0xA3,0x00, ++0x2B,0x10,0xA2,0x00, ++0x24,0x01,0x40,0x14, ++0x00,0x00,0x00,0x00, ++0x24,0x5F,0x42,0x8D, ++0x00,0x00,0x00,0x00, ++0x10,0x01,0x45,0x10, ++0x01,0x00,0x05,0x24, ++0x30,0x1F,0xC2,0x27, ++0xA4,0x3E,0x43,0x8C, ++0x42,0xB0,0x07,0x3C, ++0x00,0x00,0xE6,0x90, ++0x18,0x00,0x65,0x00, ++0xFB,0xFF,0x02,0x24, ++0x24,0x30,0xC2,0x00, ++0x00,0x00,0xE6,0xA0, ++0x67,0x46,0x06,0x3C, ++0xCF,0xAC,0xC6,0x34, ++0x01,0x00,0x04,0x24, ++0x21,0x28,0x00,0x00, ++0x12,0x18,0x00,0x00, ++0x82,0x1A,0x03,0x00, ++0x40,0x10,0x03,0x00, ++0x21,0x10,0x43,0x00, ++0xC0,0x10,0x02,0x00, ++0x21,0x10,0x43,0x00, ++0x80,0x10,0x02,0x00, ++0x19,0x00,0x46,0x00, ++0x10,0x30,0x00,0x00, ++0x23,0x10,0x46,0x00, ++0x42,0x10,0x02,0x00, ++0x21,0x30,0xC2,0x00, ++0x02,0x33,0x06,0x00, ++0x01,0x00,0x02,0x24, ++0x8C,0x23,0x00,0x0C, ++0x0A,0x30,0x46,0x00, ++0x25,0xB0,0x06,0x3C, ++0xF2,0x02,0xC3,0x34, ++0x88,0xFF,0x02,0x24, ++0x00,0x00,0x62,0xA0, ++0x11,0x00,0xC7,0x34, ++0x00,0x00,0xE2,0x90, ++0x08,0x00,0xC5,0x34, ++0x30,0x1F,0xC4,0x27, ++0x01,0x00,0x42,0x34, ++0x00,0x00,0xE2,0xA0, ++0x00,0x00,0xA3,0x94, ++0xB0,0x1B,0x82,0x94, ++0xFF,0xFF,0x64,0x30, ++0x10,0x00,0x84,0x34, ++0x00,0x00,0xA4,0xA4, ++0xFB,0xFF,0x84,0x30, ++0x00,0x00,0xA4,0xA4, ++0x00,0x01,0x42,0x30, ++0x02,0x00,0x84,0x34, ++0x00,0x00,0xA4,0xA4, ++0x04,0x00,0x40,0x10, ++0x42,0xB0,0x02,0x3C, ++0x22,0x00,0x03,0x24, ++0x03,0x00,0x42,0x34, ++0x00,0x00,0x43,0xA0, ++0xFF,0xF7,0x84,0x30, ++0x00,0x00,0xA4,0xA4, ++0x28,0x00,0xC4,0x34, ++0x00,0x00,0x83,0x94, ++0xEF,0xFE,0x02,0x24, ++0xFE,0xFF,0x08,0x24, ++0x24,0x18,0x62,0x00, ++0x00,0x00,0x83,0xA4, ++0x00,0x00,0x82,0x94, ++0x26,0x00,0xC5,0x34, ++0x02,0x80,0x03,0x3C, ++0x24,0x10,0x48,0x00, ++0x00,0x00,0x82,0xA4, ++0xDA,0x5D,0x64,0x90, ++0x00,0x00,0xA2,0x94, ++0x04,0x00,0x84,0x30, ++0x00,0x24,0x42,0x34, ++0x00,0x00,0xA2,0xA4, ++0x09,0x00,0x80,0x10, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0xA2,0x94, ++0x00,0x00,0x00,0x00, ++0x24,0x10,0x48,0x00, ++0x00,0x00,0xA2,0xA4, ++0x00,0x00,0xE3,0x90, ++0xFD,0xFF,0x02,0x24, ++0x24,0x18,0x62,0x00, ++0x00,0x00,0xE3,0xA0, ++0x00,0x68,0x02,0x40, ++0x00,0x08,0x42,0x30, ++0xFD,0xFF,0x40,0x10, ++0x00,0x00,0x00,0x00, ++0x25,0xB0,0x12,0x3C, ++0x11,0x00,0x43,0x36, ++0x00,0x00,0x62,0x90, ++0x00,0x00,0x00,0x00, ++0x02,0x00,0x42,0x34, ++0x00,0x00,0x62,0xA0, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x26,0x00,0x44,0x36, ++0x00,0x00,0x82,0x94, ++0x00,0x00,0x00,0x00, ++0x01,0x00,0x42,0x34, ++0x00,0x00,0x82,0xA4, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x83,0x94, ++0xFF,0xDB,0x02,0x24, ++0x28,0x00,0x45,0x36, ++0x24,0x18,0x62,0x00, ++0x00,0x00,0x83,0xA4, ++0x00,0x00,0xA2,0x94, ++0x00,0x00,0x00,0x00, ++0x01,0x00,0x42,0x34, ++0x00,0x00,0xA2,0xA4, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0xA2,0x94, ++0x00,0x00,0x00,0x00, ++0x10,0x01,0x42,0x34, ++0x00,0x00,0xA2,0xA4, ++0x08,0x00,0x51,0x36, ++0x00,0x00,0x23,0x96, ++0x30,0x1F,0xD7,0x27, ++0xB0,0x1B,0xE2,0x96, ++0xFF,0xFF,0x70,0x30, ++0x00,0x18,0x10,0x36, ++0x00,0x00,0x30,0xA6, ++0x00,0x01,0x42,0x30, ++0xFD,0xFF,0x10,0x32, ++0x00,0x00,0x30,0xA6, ++0x05,0x00,0x40,0x10, ++0x42,0xB0,0x02,0x3C, ++0x00,0x00,0x43,0x90, ++0xFB,0xFF,0x04,0x24, ++0x24,0x18,0x64,0x00, ++0x00,0x00,0x43,0xA0, ++0x04,0x00,0x10,0x36, ++0x54,0x22,0x00,0x0C, ++0x32,0x00,0x04,0x24, ++0x00,0x00,0x30,0xA6, ++0x22,0x00,0x02,0x24, ++0xF2,0x02,0x43,0x36, ++0xEF,0xFF,0x10,0x32, ++0x00,0x00,0x30,0xA6, ++0xC8,0x00,0x04,0x24, ++0x00,0x00,0x62,0xA0, ++0x54,0x22,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0xB0,0x1B,0xE2,0x96, ++0x00,0x00,0x00,0x00, ++0x00,0x01,0x42,0x30, ++0x41,0x00,0x40,0x10, ++0x42,0xB0,0x06,0x3C, ++0x84,0x00,0x42,0x36, ++0x00,0x00,0x44,0x8C, ++0x80,0x00,0x46,0x36, ++0x00,0x00,0xC2,0x8C, ++0x00,0x28,0x04,0x00, ++0x21,0x18,0x00,0x00, ++0x21,0x20,0x00,0x00, ++0x25,0x30,0x82,0x00, ++0x25,0x38,0xA3,0x00, ++0xA4,0x3E,0xE3,0x8E, ++0x23,0x28,0xD4,0x00, ++0x80,0x12,0x05,0x00, ++0x1B,0x00,0x43,0x00, ++0x02,0x00,0x60,0x14, ++0x00,0x00,0x00,0x00, ++0x0D,0x00,0x07,0x00, ++0x02,0x80,0x0B,0x3C, ++0x1C,0x5F,0x63,0x8D, ++0x12,0x10,0x00,0x00, ++0x23,0x10,0x45,0x00, ++0x21,0x10,0x43,0x00, ++0x1C,0x5F,0x62,0xAD, ++0x1C,0x5F,0x63,0x8D, ++0x42,0xB0,0x02,0x3C, ++0x03,0x00,0x42,0x34, ++0xC4,0x09,0x63,0x24, ++0x1C,0x5F,0x63,0xAD, ++0x00,0x00,0x43,0x90, ++0x00,0x00,0x00,0x00, ++0x20,0x00,0x63,0x30, ++0x20,0x00,0x60,0x14, ++0x00,0x00,0x00,0x00, ++0x1C,0x5F,0x62,0x8D, ++0x02,0x80,0x0A,0x3C, ++0x24,0x5F,0x44,0x8D, ++0x21,0x40,0x46,0x00, ++0x2B,0x28,0x06,0x01, ++0x21,0x48,0x67,0x00, ++0x21,0x48,0x25,0x01, ++0x2B,0x20,0x24,0x01, ++0x59,0x00,0x80,0x14, ++0x00,0x00,0x00,0x00, ++0x24,0x5F,0x42,0x8D, ++0x00,0x00,0x00,0x00, ++0x47,0x00,0x49,0x10, ++0x01,0x00,0x05,0x24, ++0x42,0xB0,0x02,0x3C, ++0x00,0x00,0x43,0x90, ++0xFB,0xFF,0x04,0x24, ++0x01,0x00,0x06,0x24, ++0x24,0x18,0x64,0x00, ++0x00,0x00,0x43,0xA0, ++0x04,0x00,0xA0,0x10, ++0x01,0x00,0x04,0x24, ++0x80,0x10,0x05,0x00, ++0x21,0x10,0x45,0x00, ++0x80,0x30,0x02,0x00, ++0x8C,0x23,0x00,0x0C, ++0x21,0x28,0x00,0x00, ++0x42,0xB0,0x02,0x3C, ++0x22,0x00,0x03,0x24, ++0x03,0x00,0x42,0x34, ++0x00,0x00,0x43,0xA0, ++0x42,0xB0,0x06,0x3C, ++0x00,0x00,0xC2,0x90, ++0x30,0x1F,0xC5,0x27, ++0xD0,0x1B,0xA8,0x8C, ++0xDC,0x1B,0xA7,0x94, ++0x41,0xB0,0x03,0x3C, ++0x41,0x00,0x42,0x34, ++0x08,0x00,0x64,0x34, ++0x00,0x00,0xC2,0xA0, ++0x00,0x00,0x68,0xAC, ++0x00,0x00,0x87,0xA4, ++0xF6,0x5E,0x63,0x92, ++0xF0,0xFF,0x02,0x24, ++0xDC,0x1B,0xA7,0xA4, ++0x24,0x18,0x62,0x00, ++0xF6,0x5E,0x63,0xA2, ++0xF6,0x5E,0x62,0x92, ++0xD0,0x1B,0xA8,0xAC, ++0x02,0x00,0x42,0x34, ++0xF6,0x5E,0x62,0xA2, ++0x8E,0x31,0x00,0x08, ++0x02,0x80,0x10,0x3C, ++0x4C,0x30,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x31,0xFE,0x40,0x10, ++0x00,0x00,0x00,0x00, ++0x1C,0x31,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0xF6,0x5E,0x62,0x92, ++0xF0,0xFF,0x03,0x24, ++0x24,0x10,0x43,0x00, ++0xF6,0x5E,0x62,0xA2, ++0xF6,0x5E,0x63,0x92, ++0x00,0x00,0x00,0x00, ++0x02,0x00,0x63,0x34, ++0xF6,0x5E,0x63,0xA2, ++0x88,0x31,0x00,0x08, ++0x00,0x00,0x00,0x00, ++0x99,0x99,0x03,0x3C, ++0x25,0xB0,0x02,0x3C, ++0x97,0x99,0x63,0x34, ++0x18,0x03,0x42,0x34, ++0x00,0x00,0x43,0xAC, ++0xB0,0x31,0x00,0x08, ++0x00,0x00,0x00,0x00, ++0x20,0x5F,0x42,0x8D, ++0x00,0x00,0x00,0x00, ++0x2B,0x10,0x82,0x00, ++0x0C,0x00,0x40,0x14, ++0x00,0x00,0x00,0x00, ++0x20,0x5F,0x42,0x8D, ++0x61,0x32,0x00,0x08, ++0x01,0x00,0x05,0x24, ++0x20,0x5F,0x42,0x8D, ++0x00,0x00,0x00,0x00, ++0x2B,0x10,0x02,0x01, ++0x0A,0x00,0x40,0x14, ++0x00,0x00,0x00,0x00, ++0x20,0x5F,0x42,0x8D, ++0x32,0x33,0x00,0x08, ++0x01,0x00,0x05,0x24, ++0x20,0x5F,0x42,0x8D, ++0x24,0x5F,0x43,0x8D, ++0x1C,0x5F,0x64,0x8D, ++0x23,0x10,0x54,0x00, ++0x61,0x32,0x00,0x08, ++0x23,0x28,0x44,0x00, ++0x20,0x5F,0x42,0x8D, ++0x24,0x5F,0x43,0x8D, ++0x1C,0x5F,0x64,0x8D, ++0x23,0x10,0x46,0x00, ++0x32,0x33,0x00,0x08, ++0x23,0x28,0x44,0x00, ++0x02,0x80,0x02,0x3C, ++0xF4,0x5E,0x43,0x90, ++0x00,0x00,0x00,0x00, ++0x07,0x00,0x60,0x10, ++0x02,0x80,0x02,0x3C, ++0xF6,0x5E,0x43,0x90, ++0x04,0x00,0x04,0x24, ++0x0F,0x00,0x63,0x30, ++0x04,0x00,0x63,0x28, ++0x03,0x00,0x60,0x14, ++0x01,0x00,0x05,0x24, ++0x08,0x00,0xE0,0x03, ++0x00,0x00,0x00,0x00, ++0x64,0x31,0x00,0x08, ++0x00,0x00,0x00,0x00, ++0x01,0x80,0x02,0x3C, ++0x25,0xB0,0x03,0x3C, ++0xE8,0xFF,0xBD,0x27, ++0x6C,0xCE,0x42,0x24, ++0x18,0x03,0x63,0x34, ++0x14,0x00,0xBF,0xAF, ++0x10,0x00,0xB0,0xAF, ++0x00,0x00,0x62,0xAC, ++0x00,0x60,0x10,0x40, ++0x01,0x00,0x01,0x36, ++0x01,0x00,0x21,0x38, ++0x00,0x60,0x81,0x40, ++0x02,0x80,0x04,0x3C, ++0x13,0x5F,0x82,0x90, ++0x00,0x00,0x00,0x00, ++0x0B,0x00,0x40,0x10, ++0x01,0x00,0x05,0x24, ++0xD0,0x07,0x03,0x24, ++0x02,0x80,0x02,0x3C, ++0xE4,0x5E,0x43,0xAC, ++0x13,0x5F,0x80,0xA0, ++0x00,0x60,0x90,0x40, ++0x14,0x00,0xBF,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x21,0x10,0x00,0x00, ++0x08,0x00,0xE0,0x03, ++0x18,0x00,0xBD,0x27, ++0x02,0x80,0x03,0x3C, ++0x01,0x00,0x04,0x24, ++0x02,0x80,0x02,0x3C, ++0x16,0x5F,0x44,0xA0, ++0x14,0x5F,0x60,0xA0, ++0x02,0x80,0x02,0x3C, ++0xF5,0x5E,0x44,0x90, ++0x64,0x31,0x00,0x0C, ++0xFF,0x00,0x84,0x30, ++0x00,0x60,0x90,0x40, ++0x14,0x00,0xBF,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x21,0x10,0x00,0x00, ++0x08,0x00,0xE0,0x03, ++0x18,0x00,0xBD,0x27, ++0x42,0x11,0x05,0x00, ++0x0F,0x00,0x46,0x30, ++0xE8,0xFF,0xBD,0x27, ++0x09,0x00,0xC3,0x28, ++0x14,0x00,0xBF,0xAF, ++0x15,0x00,0x60,0x10, ++0x10,0x00,0xB0,0xAF, ++0x82,0x16,0x05,0x00, ++0x01,0x00,0x42,0x30, ++0x15,0x00,0x40,0x10, ++0x00,0xC0,0x02,0x3C, ++0x24,0x10,0xA2,0x00, ++0x48,0x00,0x40,0x14, ++0xC2,0x15,0x04,0x00, ++0x01,0x00,0x42,0x30, ++0x55,0x00,0x40,0x10, ++0x00,0x00,0x00,0x00, ++0x02,0x80,0x03,0x3C, ++0x50,0xE9,0x63,0x24, ++0x21,0x18,0xC3,0x00, ++0x02,0x80,0x04,0x3C, ++0x0F,0x5F,0x85,0x90, ++0x00,0x00,0x62,0x90, ++0x00,0x00,0x00,0x00, ++0x24,0x10,0x45,0x00, ++0x4B,0x00,0x40,0x10, ++0x00,0x00,0x00,0x00, ++0x14,0x00,0xBF,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x08,0x00,0xE0,0x03, ++0x18,0x00,0xBD,0x27, ++0x24,0x10,0xA2,0x00, ++0x20,0x00,0x40,0x14, ++0xC2,0x15,0x04,0x00, ++0x01,0x00,0x42,0x30, ++0x0B,0x00,0x40,0x10, ++0x02,0x80,0x04,0x3C, ++0x02,0x80,0x03,0x3C, ++0x50,0xE9,0x63,0x24, ++0x21,0x18,0xC3,0x00, ++0x02,0x80,0x04,0x3C, ++0x0F,0x5F,0x85,0x90, ++0x00,0x00,0x62,0x90, ++0x00,0x00,0x00,0x00, ++0x24,0x10,0x45,0x00, ++0x3C,0x00,0x40,0x14, ++0x02,0x80,0x04,0x3C, ++0x0E,0x5F,0x82,0x90, ++0xFE,0xFF,0x03,0x24, ++0x24,0x10,0x43,0x00, ++0x0E,0x5F,0x82,0xA0, ++0x0E,0x5F,0x82,0x90, ++0x00,0x00,0x00,0x00, ++0x07,0x00,0x42,0x30, ++0xE4,0xFF,0x40,0x14, ++0x02,0x80,0x02,0x3C, ++0x0C,0x5F,0x40,0xA0, ++0x02,0x80,0x03,0x3C, ++0xF5,0x5E,0x64,0x90, ++0x14,0x00,0xBF,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x01,0x00,0x05,0x24, ++0xFF,0x00,0x84,0x30, ++0x64,0x31,0x00,0x08, ++0x18,0x00,0xBD,0x27, ++0x02,0x80,0x04,0x3C, ++0x0E,0x5F,0x82,0x90, ++0xFD,0xFF,0x03,0x24, ++0x14,0x00,0xBF,0x8F, ++0x24,0x10,0x43,0x00, ++0x02,0x80,0x03,0x3C, ++0x0E,0x5F,0x82,0xA0, ++0x12,0x5F,0x60,0xA0, ++0x42,0xB0,0x04,0x3C, ++0x00,0x00,0x82,0x90, ++0x10,0x00,0xB0,0x8F, ++0xEF,0xFF,0x03,0x24, ++0x24,0x10,0x43,0x00, ++0x03,0x00,0x85,0x34, ++0x40,0x00,0x03,0x24, ++0x18,0x00,0xBD,0x27, ++0x00,0x00,0x82,0xA0, ++0x00,0x00,0xA3,0xA0, ++0x08,0x00,0xE0,0x03, ++0x00,0x00,0x00,0x00, ++0x42,0xB0,0x07,0x3C, ++0x00,0x00,0xE3,0x90, ++0xEF,0xFF,0x02,0x24, ++0x03,0x00,0xF0,0x34, ++0x24,0x18,0x62,0x00, ++0x40,0x00,0x02,0x24, ++0x00,0x00,0xE3,0xA0, ++0x02,0x00,0x04,0x24, ++0x00,0x00,0x02,0xA2, ++0x21,0x28,0x00,0x00, ++0x8C,0x23,0x00,0x0C, ++0x00,0xF0,0x06,0x34, ++0x44,0x00,0x02,0x24, ++0x00,0x00,0x02,0xA2, ++0xE0,0x33,0x00,0x08, ++0x00,0x00,0x00,0x00, ++0x14,0x00,0xBF,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x01,0x00,0x04,0x24, ++0xFE,0x4E,0x00,0x08, ++0x18,0x00,0xBD,0x27, ++0x0E,0x5F,0x82,0x90, ++0xF6,0x33,0x00,0x08, ++0xFB,0xFF,0x03,0x24, ++0x82,0x16,0x05,0x00, ++0xE8,0xFF,0xBD,0x27, ++0x01,0x00,0x42,0x30, ++0x14,0x00,0xBF,0xAF, ++0x0E,0x00,0x40,0x10, ++0x10,0x00,0xB0,0xAF, ++0x00,0xC0,0x02,0x3C, ++0x24,0x10,0xA2,0x00, ++0x37,0x00,0x40,0x14, ++0x02,0x80,0x02,0x3C, ++0x0D,0x5F,0x43,0x90, ++0x02,0x00,0x02,0x24, ++0xFF,0x00,0x63,0x30, ++0x44,0x00,0x62,0x10, ++0x01,0x00,0x04,0x24, ++0x14,0x00,0xBF,0x8F, ++0x10,0x00,0xB0,0x8F, ++0xFE,0x4E,0x00,0x08, ++0x18,0x00,0xBD,0x27, ++0x00,0xC0,0x02,0x3C, ++0x24,0x10,0xA2,0x00, ++0x0E,0x00,0x40,0x14, ++0x02,0x80,0x06,0x3C, ++0x0E,0x5F,0xC2,0x90, ++0xFE,0xFF,0x03,0x24, ++0x24,0x10,0x43,0x00, ++0x0E,0x5F,0xC2,0xA0, ++0x0E,0x5F,0xC2,0x90, ++0x00,0x00,0x00,0x00, ++0x07,0x00,0x42,0x30, ++0x18,0x00,0x40,0x10, ++0x02,0x80,0x02,0x3C, ++0x14,0x00,0xBF,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x08,0x00,0xE0,0x03, ++0x18,0x00,0xBD,0x27, ++0x0E,0x5F,0xC2,0x90, ++0xFD,0xFF,0x03,0x24, ++0x42,0xB0,0x04,0x3C, ++0x24,0x10,0x43,0x00, ++0x02,0x80,0x03,0x3C, ++0x0E,0x5F,0xC2,0xA0, ++0x12,0x5F,0x60,0xA0, ++0x00,0x00,0x82,0x90, ++0xEF,0xFF,0x03,0x24, ++0x03,0x00,0x85,0x34, ++0x24,0x10,0x43,0x00, ++0x40,0x00,0x03,0x24, ++0x00,0x00,0x82,0xA0, ++0x00,0x00,0xA3,0xA0, ++0x0E,0x5F,0xC2,0x90, ++0x00,0x00,0x00,0x00, ++0x07,0x00,0x42,0x30, ++0xEA,0xFF,0x40,0x14, ++0x02,0x80,0x02,0x3C, ++0x0C,0x5F,0x40,0xA0, ++0x02,0x80,0x03,0x3C, ++0xF5,0x5E,0x64,0x90, ++0x14,0x00,0xBF,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x01,0x00,0x05,0x24, ++0xFF,0x00,0x84,0x30, ++0x64,0x31,0x00,0x08, ++0x18,0x00,0xBD,0x27, ++0x42,0xB0,0x07,0x3C, ++0x00,0x00,0xE3,0x90, ++0xEF,0xFF,0x02,0x24, ++0x03,0x00,0xF0,0x34, ++0x24,0x18,0x62,0x00, ++0x40,0x00,0x02,0x24, ++0x00,0x00,0xE3,0xA0, ++0x02,0x00,0x04,0x24, ++0x00,0x00,0x02,0xA2, ++0x21,0x28,0x00,0x00, ++0x8C,0x23,0x00,0x0C, ++0x00,0xF0,0x06,0x34, ++0x44,0x00,0x02,0x24, ++0x00,0x00,0x02,0xA2, ++0x14,0x00,0xBF,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x08,0x00,0xE0,0x03, ++0x18,0x00,0xBD,0x27, ++0x0D,0x30,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x14,0x00,0xBF,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x0C,0x00,0x04,0x24, ++0x01,0x00,0x05,0x24, ++0x64,0x31,0x00,0x08, ++0x18,0x00,0xBD,0x27, ++0x01,0x80,0x02,0x3C, ++0x25,0xB0,0x03,0x3C, ++0xE8,0xFF,0xBD,0x27, ++0x30,0xD2,0x42,0x24, ++0x18,0x03,0x63,0x34, ++0x10,0x00,0xB0,0xAF, ++0x00,0x00,0x62,0xAC, ++0x02,0x80,0x10,0x3C, ++0xF5,0x5E,0x02,0x92, ++0x14,0x00,0xBF,0xAF, ++0x0F,0x00,0x42,0x30, ++0x03,0x00,0x42,0x28, ++0x05,0x00,0x40,0x10, ++0x01,0x00,0x05,0x24, ++0x4C,0x30,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x04,0x00,0x40,0x10, ++0x01,0x00,0x05,0x24, ++0xF5,0x5E,0x04,0x92, ++0x64,0x31,0x00,0x0C, ++0xFF,0x00,0x84,0x30, ++0x02,0x80,0x04,0x3C, ++0x30,0x1F,0x84,0x24, ++0xE0,0x1B,0x83,0x94, ++0xDC,0x1B,0x85,0x94, ++0x14,0x00,0xBF,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x02,0x00,0x63,0x30, ++0x41,0xB0,0x02,0x3C, ++0x25,0x18,0x65,0x00, ++0x08,0x00,0x42,0x34, ++0x18,0x00,0xBD,0x27, ++0x00,0x00,0x43,0xA4, ++0x08,0x00,0xE0,0x03, ++0xDC,0x1B,0x83,0xA4, ++0xE8,0xFF,0xBD,0x27, ++0x10,0x00,0xB0,0xAF, ++0x14,0x00,0xBF,0xAF, ++0x02,0x80,0x10,0x3C, ++0x08,0x14,0x04,0x26, ++0x21,0x28,0x00,0x00, ++0x21,0x30,0x00,0x00, ++0x91,0x3C,0x00,0x0C, ++0x21,0x38,0x00,0x00, ++0xB4,0x34,0x00,0x08, ++0x08,0x14,0x04,0x26, ++0xE8,0xFF,0xBD,0x27, ++0x10,0x00,0xBF,0xAF, ++0xCF,0x61,0x00,0x0C, ++0x21,0x38,0x00,0x00, ++0x10,0x00,0xBF,0x8F, ++0x00,0x00,0x00,0x00, ++0x08,0x00,0xE0,0x03, ++0x18,0x00,0xBD,0x27, ++0xFF,0xFF,0x8D,0x30, ++0x00,0x60,0x0F,0x40, ++0x01,0x00,0xE1,0x35, ++0x01,0x00,0x21,0x38, ++0x00,0x60,0x81,0x40, ++0x02,0x80,0x06,0x3C, ++0x30,0x1F,0xCE,0x24, ++0x2A,0x1C,0xC2,0x91, ++0x00,0x00,0x00,0x00, ++0x1D,0x00,0x40,0x10, ++0x25,0xB0,0x03,0x3C, ++0x38,0x02,0x64,0x34, ++0x80,0xFF,0x02,0x24, ++0x00,0x00,0x82,0xA0, ++0x34,0x02,0x6A,0x34, ++0xD2,0x01,0x65,0x34, ++0xD6,0x01,0x66,0x34, ++0xDA,0x01,0x67,0x34, ++0xDE,0x01,0x63,0x34, ++0x00,0x00,0xA8,0x94, ++0x00,0x00,0xC9,0x94, ++0x00,0x00,0xEB,0x94, ++0x00,0x00,0x6C,0x94, ++0x00,0x00,0x44,0x95, ++0xB0,0xFE,0xA2,0x25, ++0xFF,0xFF,0x4D,0x30, ++0x28,0x1C,0xC4,0xA5, ++0x00,0x00,0xA0,0xA4, ++0x20,0x1C,0xC8,0xA5, ++0x00,0x00,0xC0,0xA4, ++0x22,0x1C,0xC9,0xA5, ++0x00,0x00,0xE0,0xA4, ++0x24,0x1C,0xCB,0xA5, ++0x00,0x00,0x60,0xA4, ++0x00,0x00,0x4D,0xA5, ++0x26,0x1C,0xCC,0xA5, ++0x00,0x60,0x8F,0x40, ++0x08,0x00,0xE0,0x03, ++0x00,0x00,0x00,0x00, ++0x2A,0xB0,0x02,0x3C, ++0x0A,0x00,0x45,0x34, ++0x63,0x00,0x03,0x24, ++0xFF,0xFF,0x04,0x34, ++0x00,0x00,0xA2,0x90, ++0x00,0x00,0x00,0x00, ++0x0A,0x00,0x40,0x10, ++0x30,0x1F,0xC2,0x24, ++0x64,0x00,0x02,0x24, ++0xFF,0xFF,0x42,0x24, ++0xFF,0xFF,0x42,0x30, ++0xFE,0xFF,0x40,0x14, ++0xFF,0xFF,0x42,0x24, ++0xFF,0xFF,0x62,0x24, ++0xFF,0xFF,0x43,0x30, ++0xF4,0xFF,0x64,0x14, ++0x30,0x1F,0xC2,0x24, ++0x28,0x1C,0x48,0x94, ++0x26,0x1C,0x47,0x94, ++0x20,0x1C,0x49,0x94, ++0x22,0x1C,0x4A,0x94, ++0x24,0x1C,0x4B,0x94, ++0x25,0xB0,0x03,0x3C, ++0x38,0x02,0x6C,0x34, ++0x34,0x02,0x62,0x34, ++0xD2,0x01,0x64,0x34, ++0xD6,0x01,0x65,0x34, ++0xDA,0x01,0x66,0x34, ++0xDE,0x01,0x63,0x34, ++0x00,0x00,0x48,0xA4, ++0x00,0x00,0x89,0xA4, ++0x00,0x00,0xAA,0xA4, ++0x00,0x00,0xCB,0xA4, ++0x00,0x00,0x67,0xA4, ++0x00,0x00,0x80,0xA1, ++0x00,0x60,0x8F,0x40, ++0x08,0x00,0xE0,0x03, ++0x00,0x00,0x00,0x00, ++0xD0,0xFF,0xBD,0x27, ++0x28,0x00,0xB4,0xAF, ++0x2C,0x00,0xBF,0xAF, ++0x24,0x00,0xB3,0xAF, ++0x20,0x00,0xB2,0xAF, ++0x1C,0x00,0xB1,0xAF, ++0x18,0x00,0xB0,0xAF, ++0xFF,0xFF,0x14,0x24, ++0x02,0x80,0x13,0x3C, ++0x41,0xB0,0x02,0x3C, ++0x30,0x1F,0x63,0x26, ++0x04,0x00,0x42,0x34, ++0x00,0x00,0x45,0x8C, ++0xD4,0x1B,0x64,0x8C, ++0xD0,0x1B,0x66,0x8C, ++0x02,0x80,0x02,0x3C, ++0x08,0x5E,0x47,0x90, ++0x25,0xB0,0x08,0x3C, ++0xB0,0x03,0x02,0x35, ++0x25,0x90,0x85,0x00, ++0x00,0x00,0x52,0xAC, ++0x00,0x00,0x46,0xAC, ++0x01,0x00,0x02,0x24, ++0x8D,0x03,0xE2,0x10, ++0xD4,0x1B,0x72,0xAC, ++0x30,0x1F,0x64,0x26, ++0xD0,0x1B,0x82,0x8C, ++0x00,0x00,0x00,0x00, ++0x24,0x10,0x52,0x00, ++0x01,0x00,0x42,0x30, ++0x0E,0x00,0x40,0x10, ++0x30,0x1F,0x67,0x26, ++0x25,0xB0,0x10,0x3C, ++0xB0,0x03,0x02,0x36, ++0x01,0x00,0x05,0x24, ++0x00,0x00,0x45,0xAC, ++0x04,0x00,0x0B,0x36, ++0xD4,0x1B,0x83,0x8C, ++0x00,0x00,0x69,0x8D, ++0x40,0x00,0x02,0x3C, ++0x01,0x00,0x63,0x38, ++0x24,0x10,0x22,0x01, ++0x2A,0x01,0x40,0x10, ++0xD4,0x1B,0x83,0xAC, ++0x30,0x1F,0x67,0x26, ++0xD0,0x1B,0xE8,0x8C, ++0x00,0x00,0x00,0x00, ++0x24,0x10,0x12,0x01, ++0x04,0x00,0x42,0x30, ++0x18,0x00,0x40,0x10, ++0x30,0x1F,0x71,0x26, ++0x25,0xB0,0x03,0x3C, ++0xB0,0x03,0x64,0x34, ++0x04,0x00,0x02,0x24, ++0x00,0x00,0x82,0xAC, ++0xD4,0x1B,0xE2,0x8C, ++0xFC,0x00,0x63,0x34, ++0xAC,0x1B,0xE5,0x94, ++0xD0,0x37,0xE4,0x8C, ++0x00,0x00,0x66,0x8C, ++0x04,0x00,0x42,0x38, ++0x21,0x48,0x85,0x00, ++0x0A,0x00,0xC9,0x10, ++0xD4,0x1B,0xE2,0xAC, ++0x02,0x80,0x05,0x3C, ++0xBC,0x5E,0xA2,0x8C, ++0xFB,0xFF,0x04,0x24, ++0x24,0x20,0x04,0x01, ++0x00,0x10,0x42,0x34, ++0x41,0xB0,0x03,0x3C, ++0xBC,0x5E,0xA2,0xAC, ++0x00,0x00,0x64,0xAC, ++0xD0,0x1B,0xE4,0xAC, ++0x30,0x1F,0x71,0x26, ++0xD0,0x1B,0x22,0x8E, ++0x00,0x00,0x00,0x00, ++0x24,0x10,0x52,0x00, ++0x08,0x00,0x42,0x30, ++0x0A,0x00,0x40,0x10, ++0x00,0x00,0x00,0x00, ++0xB0,0x1B,0x22,0x96, ++0x00,0x00,0x00,0x00, ++0x04,0x00,0x42,0x30, ++0x5D,0x03,0x40,0x14, ++0x00,0x80,0x02,0x3C, ++0xD4,0x1B,0x22,0x8E, ++0x00,0x00,0x00,0x00, ++0x08,0x00,0x42,0x38, ++0xD4,0x1B,0x22,0xAE, ++0x30,0x1F,0x70,0x26, ++0xD0,0x1B,0x02,0x8E, ++0x00,0x00,0x00,0x00, ++0x24,0x20,0x52,0x00, ++0x00,0x08,0x83,0x30, ++0x06,0x00,0x60,0x10, ++0x00,0x10,0x82,0x30, ++0xD4,0x1B,0x02,0x8E, ++0x00,0x00,0x00,0x00, ++0x00,0x08,0x42,0x38, ++0xD4,0x1B,0x02,0xAE, ++0x00,0x10,0x82,0x30, ++0x05,0x03,0x40,0x14, ++0x00,0x00,0x00,0x00, ++0x30,0x1F,0x70,0x26, ++0xD0,0x1B,0x03,0x8E, ++0x00,0x00,0x00,0x00, ++0x24,0x10,0x72,0x00, ++0x00,0x20,0x42,0x30, ++0xF7,0x02,0x40,0x14, ++0x00,0x00,0x00,0x00, ++0x24,0x10,0x72,0x00, ++0x00,0x80,0x42,0x30, ++0xB9,0x01,0x40,0x14, ++0x01,0x00,0x03,0x3C, ++0x30,0x1F,0x70,0x26, ++0xD0,0x1B,0x02,0x8E, ++0x00,0x00,0x00,0x00, ++0x24,0x10,0x52,0x00, ++0x24,0x10,0x54,0x00, ++0x24,0x10,0x43,0x00, ++0xF1,0x01,0x40,0x14, ++0x00,0x00,0x00,0x00, ++0xD0,0x1B,0x02,0x8E, ++0x02,0x00,0x03,0x3C, ++0x24,0x10,0x52,0x00, ++0x24,0x10,0x43,0x00, ++0x28,0x02,0x40,0x14, ++0x00,0x00,0x00,0x00, ++0x30,0x1F,0x70,0x26, ++0xD0,0x1B,0x02,0x8E, ++0x04,0x00,0x03,0x3C, ++0x24,0x10,0x52,0x00, ++0x24,0x10,0x54,0x00, ++0x24,0x10,0x43,0x00, ++0x62,0x02,0x40,0x14, ++0x00,0x00,0x00,0x00, ++0x30,0x1F,0x70,0x26, ++0xD0,0x1B,0x02,0x8E, ++0x08,0x00,0x03,0x3C, ++0x24,0x10,0x52,0x00, ++0x24,0x10,0x43,0x00, ++0x9B,0x02,0x40,0x14, ++0x00,0x00,0x00,0x00, ++0x30,0x1F,0x70,0x26, ++0xD0,0x1B,0x02,0x8E, ++0x10,0x00,0x03,0x3C, ++0x24,0x10,0x52,0x00, ++0x24,0x10,0x54,0x00, ++0x24,0x10,0x43,0x00, ++0x5A,0x01,0x40,0x14, ++0x00,0x00,0x00,0x00, ++0x30,0x1F,0x70,0x26, ++0xD0,0x1B,0x02,0x8E, ++0x20,0x00,0x03,0x3C, ++0x24,0x10,0x52,0x00, ++0x24,0x10,0x43,0x00, ++0x18,0x01,0x40,0x14, ++0x00,0x00,0x00,0x00, ++0x30,0x1F,0x70,0x26, ++0xD0,0x1B,0x02,0x8E, ++0x40,0x00,0x03,0x3C, ++0x24,0x10,0x52,0x00, ++0x24,0x10,0x54,0x00, ++0x24,0x10,0x43,0x00, ++0xD6,0x00,0x40,0x14, ++0x00,0x00,0x00,0x00, ++0x30,0x1F,0x65,0x26, ++0xD0,0x1B,0xA2,0x8C, ++0x00,0x04,0x03,0x3C, ++0x24,0x10,0x52,0x00, ++0x24,0x10,0x43,0x00, ++0x3D,0x00,0x40,0x10, ++0x30,0x1F,0x66,0x26, ++0x2A,0xB0,0x02,0x3C, ++0x2C,0x00,0x43,0x34, ++0x00,0x00,0x69,0x8C, ++0xFF,0x00,0x02,0x24, ++0xFF,0x00,0x24,0x31, ++0x29,0x03,0x82,0x10, ++0x00,0x80,0x22,0x31, ++0xF9,0x02,0x40,0x14, ++0x00,0x80,0x02,0x3C, ++0x00,0xFF,0x02,0x3C, ++0x24,0x10,0x22,0x01, ++0x0B,0x00,0x40,0x10, ++0xFF,0x00,0x02,0x24, ++0xB8,0x36,0xA2,0x90, ++0x20,0xB0,0x03,0x3C, ++0x00,0x12,0x02,0x00, ++0x21,0x10,0x43,0x00, ++0x0C,0x00,0x49,0x8C, ++0x25,0xB0,0x03,0x3C, ++0xB0,0x03,0x63,0x34, ++0x00,0x00,0x69,0xAC, ++0xFF,0x00,0x24,0x31, ++0xFF,0x00,0x02,0x24, ++0x1B,0x00,0x82,0x10, ++0x30,0x1F,0x70,0x26, ++0xFF,0x00,0x23,0x31, ++0x88,0x37,0x05,0x8E, ++0x20,0x10,0x02,0x3C, ++0x00,0x1A,0x03,0x00, ++0x21,0x18,0x62,0x00, ++0x21,0x30,0x60,0x00, ++0x1C,0x37,0x03,0xAE, ++0x0A,0x00,0x04,0x24, ++0xB8,0x36,0x09,0xA2, ++0x00,0x01,0x07,0x24, ++0x73,0x01,0x00,0x0C, ++0x10,0x00,0xA0,0xAF, ++0xD0,0x1B,0x05,0x8E, ++0x02,0x80,0x06,0x3C, ++0xBC,0x5E,0xC4,0x8C, ++0x00,0x04,0x02,0x3C, ++0x27,0x10,0x02,0x00, ++0x24,0x28,0xA2,0x00, ++0x25,0xB0,0x02,0x3C, ++0x00,0x40,0x84,0x34, ++0xB0,0x03,0x42,0x34, ++0x41,0xB0,0x03,0x3C, ++0x00,0x00,0x44,0xAC, ++0x00,0x00,0x65,0xAC, ++0xBC,0x5E,0xC4,0xAC, ++0xD0,0x1B,0x05,0xAE, ++0x30,0x1F,0x65,0x26, ++0xD4,0x1B,0xA4,0x8C, ++0x00,0x04,0x03,0x3C, ++0x25,0xB0,0x02,0x3C, ++0x26,0x20,0x83,0x00, ++0xB0,0x03,0x42,0x34, ++0x00,0x00,0x44,0xAC, ++0xD4,0x1B,0xA4,0xAC, ++0x30,0x1F,0x66,0x26, ++0xD0,0x1B,0xC7,0x8C, ++0x00,0x08,0x04,0x3C, ++0x24,0x28,0xF2,0x00, ++0x24,0x10,0xA4,0x00, ++0x08,0x00,0x40,0x10, ++0x80,0x00,0x08,0x3C, ++0xD4,0x1B,0xC3,0x8C, ++0x25,0xB0,0x02,0x3C, ++0xB0,0x03,0x42,0x34, ++0x26,0x18,0x64,0x00, ++0x00,0x00,0x44,0xAC, ++0xD4,0x1B,0xC3,0xAC, ++0x80,0x00,0x08,0x3C, ++0x24,0x10,0xA8,0x00, ++0x21,0x00,0x40,0x10, ++0x00,0x00,0x00,0x00, ++0xD4,0x1B,0xC3,0x8C, ++0x25,0xB0,0x09,0x3C, ++0xB0,0x03,0x2A,0x35, ++0x2A,0xB0,0x02,0x3C, ++0x00,0x00,0x43,0xAD, ++0x36,0x00,0x42,0x34, ++0x00,0x00,0x43,0x90, ++0x23,0xB0,0x04,0x3C, ++0xFF,0x1F,0x02,0x3C, ++0xC0,0x18,0x03,0x00, ++0xF0,0x07,0x63,0x30, ++0x00,0x38,0xC5,0x8C, ++0x21,0x18,0x64,0x00, ++0xFF,0xFF,0x42,0x34, ++0x24,0x18,0x62,0x00, ++0xCE,0x02,0x65,0x10, ++0x04,0x38,0xC3,0xAC, ++0x02,0x80,0x05,0x3C, ++0xBC,0x5E,0xA3,0x8C, ++0x27,0x20,0x08,0x00, ++0x24,0x20,0xE4,0x00, ++0x00,0x08,0x63,0x34, ++0x41,0xB0,0x02,0x3C, ++0x00,0x00,0x43,0xAD, ++0x00,0x00,0x44,0xAC, ++0xBC,0x5E,0xA3,0xAC, ++0xD0,0x1B,0xC4,0xAC, ++0x30,0x1F,0x62,0x26, ++0xD4,0x1B,0x43,0x8C, ++0x80,0x00,0x04,0x3C, ++0x26,0x18,0x64,0x00, ++0xD4,0x1B,0x43,0xAC, ++0x30,0x1F,0x66,0x26, ++0xD0,0x1B,0xC3,0x8C, ++0x00,0x01,0x05,0x3C, ++0x24,0x20,0x72,0x00, ++0x24,0x10,0x85,0x00, ++0x06,0x00,0x40,0x10, ++0x25,0xB0,0x02,0x3C, ++0xD4,0x1B,0xC3,0x8C, ++0xB0,0x03,0x42,0x34, ++0x26,0x18,0x65,0x00, ++0x00,0x00,0x45,0xAC, ++0xD4,0x1B,0xC3,0xAC, ++0x00,0x02,0x05,0x3C, ++0x24,0x10,0x85,0x00, ++0x06,0x00,0x40,0x10, ++0x25,0xB0,0x02,0x3C, ++0xD4,0x1B,0xC3,0x8C, ++0xB0,0x03,0x42,0x34, ++0x26,0x18,0x65,0x00, ++0x00,0x00,0x45,0xAC, ++0xD4,0x1B,0xC3,0xAC, ++0x00,0x10,0x05,0x3C, ++0x24,0x10,0x85,0x00, ++0x0C,0x00,0x40,0x10, ++0x30,0x1F,0x63,0x26, ++0xB0,0x1B,0xC3,0x94, ++0x00,0x00,0x00,0x00, ++0x04,0x00,0x62,0x30, ++0x02,0x00,0x40,0x10, ++0x00,0x08,0x62,0x34, ++0xB0,0x1B,0xC2,0xA4, ++0xD4,0x1B,0xC2,0x8C, ++0x00,0x00,0x00,0x00, ++0x26,0x10,0x45,0x00, ++0xD4,0x1B,0xC2,0xAC, ++0x30,0x1F,0x63,0x26, ++0xD0,0x1B,0x62,0x8C, ++0x00,0x20,0x05,0x3C, ++0x24,0x10,0x52,0x00, ++0x24,0x10,0x45,0x00, ++0x0B,0x00,0x40,0x10, ++0x00,0x00,0x00,0x00, ++0xB0,0x1B,0x64,0x94, ++0x00,0x00,0x00,0x00, ++0x04,0x00,0x82,0x30, ++0x02,0x00,0x40,0x10, ++0xFF,0xF7,0x82,0x30, ++0xB0,0x1B,0x62,0xA4, ++0xD4,0x1B,0x62,0x8C, ++0x00,0x00,0x00,0x00, ++0x26,0x10,0x45,0x00, ++0xD4,0x1B,0x62,0xAC, ++0x2C,0x00,0xBF,0x8F, ++0x28,0x00,0xB4,0x8F, ++0x24,0x00,0xB3,0x8F, ++0x20,0x00,0xB2,0x8F, ++0x1C,0x00,0xB1,0x8F, ++0x18,0x00,0xB0,0x8F, ++0x08,0x00,0xE0,0x03, ++0x30,0x00,0xBD,0x27, ++0x20,0xBD,0x02,0x3C, ++0xEC,0x02,0x03,0x36, ++0x4D,0x00,0x07,0x36, ++0xF1,0x02,0x08,0x36, ++0x08,0x00,0x06,0x24, ++0x78,0x02,0x42,0x34, ++0x00,0x00,0x45,0xA4, ++0x00,0x00,0xE0,0xA0, ++0x00,0x00,0x06,0xA1, ++0x00,0x00,0x60,0xAC, ++0x00,0x00,0x62,0x8C, ++0xFF,0x00,0x04,0x3C, ++0x00,0x00,0xE0,0xA0, ++0xFF,0x00,0x49,0x30, ++0x25,0x48,0x24,0x01, ++0x00,0x00,0x06,0xA1, ++0xF2,0x02,0x05,0x36, ++0x00,0x00,0x64,0xAC, ++0x0A,0x00,0x0A,0x36, ++0x00,0x00,0x69,0xAC, ++0x80,0xFF,0x03,0x24, ++0x00,0x00,0xA0,0xA0, ++0x00,0x00,0x43,0xA1, ++0x00,0x00,0x62,0x8D, ++0x80,0x00,0x03,0x3C, ++0x24,0x10,0x43,0x00, ++0x02,0x00,0x40,0x10, ++0x84,0xFF,0x02,0x24, ++0x00,0x00,0x42,0xA1, ++0x25,0x22,0x00,0x0C, ++0x01,0x00,0x04,0x24, ++0x02,0x00,0x02,0x36, ++0x00,0x00,0x43,0x94, ++0xFF,0xBF,0x04,0x24, ++0x24,0x18,0x64,0x00, ++0x00,0x00,0x43,0xA4, ++0x3C,0x35,0x00,0x08, ++0x30,0x1F,0x67,0x26, ++0x8C,0x33,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x25,0xB0,0x02,0x3C, ++0x2A,0xB0,0x06,0x3C, ++0xB0,0x03,0x42,0x34, ++0x00,0x00,0x54,0xAC, ++0x28,0x00,0xC3,0x34, ++0x00,0x00,0x69,0x8C, ++0xFF,0x00,0x05,0x24, ++0xFF,0x00,0x24,0x31, ++0x6D,0x03,0x85,0x10, ++0x25,0xBD,0x02,0x3C, ++0x00,0x80,0x22,0x31, ++0x59,0x02,0x40,0x10, ++0x00,0xFF,0x02,0x3C, ++0x00,0x80,0x02,0x3C, ++0x00,0x00,0x62,0xAC, ++0xFF,0x00,0x02,0x24, ++0x21,0x00,0x82,0x10, ++0xFF,0x00,0x23,0x31, ++0x30,0x1F,0x70,0x26, ++0x58,0x37,0x05,0x8E, ++0x20,0x10,0x02,0x3C, ++0x00,0x1A,0x03,0x00, ++0x21,0x18,0x62,0x00, ++0x21,0x30,0x60,0x00, ++0xA4,0x36,0x09,0xA2, ++0xEC,0x36,0x03,0xAE, ++0x06,0x00,0x04,0x24, ++0x80,0x00,0x07,0x24, ++0x73,0x01,0x00,0x0C, ++0x10,0x00,0xA0,0xAF, ++0x02,0x80,0x09,0x3C, ++0xCC,0x5E,0x27,0x91, ++0x02,0x80,0x08,0x3C, ++0xBC,0x5E,0x05,0x8D, ++0xD0,0x1B,0x06,0x8E, ++0x60,0x00,0x02,0x3C, ++0x02,0x00,0xE7,0x34, ++0x27,0x10,0x02,0x00, ++0x24,0x30,0xC2,0x00, ++0x00,0x04,0xA5,0x34, ++0x00,0x26,0x07,0x00, ++0x25,0xB0,0x02,0x3C, ++0x25,0x20,0x85,0x00, ++0x80,0x03,0x42,0x34, ++0x41,0xB0,0x03,0x3C, ++0x00,0x00,0x44,0xAC, ++0x00,0x00,0x66,0xAC, ++0xBC,0x5E,0x05,0xAD, ++0xCC,0x5E,0x27,0xA1, ++0xD0,0x1B,0x06,0xAE, ++0x30,0x1F,0x62,0x26, ++0xD4,0x1B,0x43,0x8C, ++0x40,0x00,0x04,0x3C, ++0x26,0x18,0x64,0x00, ++0xB5,0x35,0x00,0x08, ++0xD4,0x1B,0x43,0xAC, ++0x8C,0x33,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x2A,0xB0,0x05,0x3C, ++0x24,0x00,0xA3,0x34, ++0x00,0x00,0x69,0x8C, ++0xFF,0x00,0x06,0x24, ++0xFF,0x00,0x24,0x31, ++0x48,0x03,0x86,0x10, ++0x25,0xB0,0x02,0x3C, ++0x00,0x80,0x22,0x31, ++0x64,0x02,0x40,0x10, ++0x00,0xFF,0x02,0x3C, ++0x00,0x80,0x02,0x3C, ++0x00,0x00,0x62,0xAC, ++0xFF,0x00,0x02,0x24, ++0x25,0x00,0x82,0x10, ++0x30,0x1F,0x70,0x26, ++0xFF,0x00,0x23,0x31, ++0x58,0x37,0x05,0x8E, ++0x20,0x10,0x02,0x3C, ++0x00,0x1A,0x03,0x00, ++0x21,0x18,0x62,0x00, ++0x21,0x30,0x60,0x00, ++0xA0,0x36,0x09,0xA2, ++0xEC,0x36,0x03,0xAE, ++0x06,0x00,0x04,0x24, ++0x80,0x00,0x07,0x24, ++0x73,0x01,0x00,0x0C, ++0x10,0x00,0xA0,0xAF, ++0x02,0x80,0x0A,0x3C, ++0xCC,0x5E,0x47,0x91, ++0x02,0x80,0x09,0x3C, ++0xBC,0x5E,0x25,0x8D, ++0xD0,0x1B,0x06,0x8E, ++0x60,0x00,0x02,0x3C, ++0x04,0x00,0xE7,0x34, ++0x27,0x10,0x02,0x00, ++0x24,0x30,0xC2,0x00, ++0x00,0x04,0xA5,0x34, ++0x25,0xB0,0x03,0x3C, ++0x40,0x00,0x02,0x3C, ++0x00,0x26,0x07,0x00, ++0x26,0xA0,0x82,0x02, ++0xB0,0x03,0x68,0x34, ++0x25,0x20,0x85,0x00, ++0x80,0x03,0x63,0x34, ++0x41,0xB0,0x02,0x3C, ++0x00,0x00,0x64,0xAC, ++0x00,0x00,0x46,0xAC, ++0xBC,0x5E,0x25,0xAD, ++0xCC,0x5E,0x47,0xA1, ++0xD0,0x1B,0x06,0xAE, ++0x00,0x00,0x14,0xAD, ++0x30,0x1F,0x62,0x26, ++0xD4,0x1B,0x43,0x8C, ++0x20,0x00,0x04,0x3C, ++0x26,0x18,0x64,0x00, ++0xAD,0x35,0x00,0x08, ++0xD4,0x1B,0x43,0xAC, ++0x8C,0x33,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x25,0xB0,0x05,0x3C, ++0xB0,0x03,0xA2,0x34, ++0x2A,0xB0,0x07,0x3C, ++0x00,0x00,0x54,0xAC, ++0x20,0x00,0xE3,0x34, ++0x00,0x00,0x69,0x8C, ++0xFF,0x00,0x06,0x24, ++0xFF,0x00,0x24,0x31, ++0x07,0x03,0x86,0x10, ++0x90,0x03,0xA2,0x34, ++0x00,0x80,0x22,0x31, ++0x05,0x02,0x40,0x10, ++0x00,0xFF,0x02,0x3C, ++0x00,0x80,0x02,0x3C, ++0x00,0x00,0x62,0xAC, ++0xFF,0x00,0x02,0x24, ++0x21,0x00,0x82,0x10, ++0x30,0x1F,0x70,0x26, ++0xFF,0x00,0x23,0x31, ++0x4C,0x37,0x05,0x8E, ++0x20,0x10,0x02,0x3C, ++0x00,0x1A,0x03,0x00, ++0x21,0x18,0x62,0x00, ++0x21,0x30,0x60,0x00, ++0xA8,0x36,0x09,0xA2, ++0xE0,0x36,0x03,0xAE, ++0x05,0x00,0x04,0x24, ++0x80,0x00,0x07,0x24, ++0x73,0x01,0x00,0x0C, ++0x10,0x00,0xA0,0xAF, ++0x02,0x80,0x09,0x3C, ++0xCC,0x5E,0x27,0x91, ++0x02,0x80,0x08,0x3C, ++0xBC,0x5E,0x05,0x8D, ++0xD0,0x1B,0x06,0x8E, ++0x18,0x00,0x02,0x3C, ++0x01,0x00,0xE7,0x34, ++0x27,0x10,0x02,0x00, ++0x24,0x30,0xC2,0x00, ++0x00,0x02,0xA5,0x34, ++0x00,0x26,0x07,0x00, ++0x25,0xB0,0x02,0x3C, ++0x25,0x20,0x85,0x00, ++0x80,0x03,0x42,0x34, ++0x41,0xB0,0x03,0x3C, ++0x00,0x00,0x44,0xAC, ++0x00,0x00,0x66,0xAC, ++0xBC,0x5E,0x05,0xAD, ++0xCC,0x5E,0x27,0xA1, ++0xD0,0x1B,0x06,0xAE, ++0x30,0x1F,0x62,0x26, ++0xD4,0x1B,0x43,0x8C, ++0x10,0x00,0x04,0x3C, ++0x26,0x18,0x64,0x00, ++0xA6,0x35,0x00,0x08, ++0xD4,0x1B,0x43,0xAC, ++0x8C,0x33,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x2A,0xB0,0x05,0x3C, ++0x0C,0x00,0xA3,0x34, ++0x00,0x00,0x69,0x8C, ++0xFF,0x00,0x06,0x24, ++0xFF,0x00,0x24,0x31, ++0xC6,0x02,0x86,0x10, ++0x00,0x80,0x22,0x31, ++0x54,0x02,0x40,0x10, ++0x00,0xFF,0x02,0x3C, ++0x00,0x80,0x02,0x3C, ++0x00,0x00,0x62,0xAC, ++0xFF,0x00,0x02,0x24, ++0x24,0x00,0x82,0x10, ++0x30,0x1F,0x70,0x26, ++0xFF,0x00,0x23,0x31, ++0x34,0x37,0x05,0x8E, ++0x20,0x10,0x02,0x3C, ++0x00,0x1A,0x03,0x00, ++0x21,0x18,0x62,0x00, ++0x21,0x30,0x60,0x00, ++0x8C,0x36,0x09,0xA2, ++0xC8,0x36,0x03,0xAE, ++0x03,0x00,0x04,0x24, ++0x80,0x00,0x07,0x24, ++0x73,0x01,0x00,0x0C, ++0x10,0x00,0xA0,0xAF, ++0x02,0x80,0x0A,0x3C, ++0xCC,0x5E,0x47,0x91, ++0x02,0x80,0x09,0x3C, ++0xBC,0x5E,0x25,0x8D, ++0xD0,0x1B,0x06,0x8E, ++0x01,0x00,0x08,0x3C, ++0x80,0xFF,0x02,0x24, ++0x25,0x38,0xE2,0x00, ++0x00,0x80,0x03,0x35, ++0x80,0x00,0xA5,0x34, ++0x27,0x18,0x03,0x00, ++0x00,0x26,0x07,0x00, ++0x25,0xB0,0x02,0x3C, ++0x24,0x30,0xC3,0x00, ++0x25,0x20,0x85,0x00, ++0x80,0x03,0x42,0x34, ++0x41,0xB0,0x03,0x3C, ++0x00,0x00,0x44,0xAC, ++0x27,0xA0,0x08,0x00, ++0x00,0x00,0x66,0xAC, ++0xBC,0x5E,0x25,0xAD, ++0xCC,0x5E,0x47,0xA1, ++0xD0,0x1B,0x06,0xAE, ++0x30,0x1F,0x63,0x26, ++0xD4,0x1B,0x62,0x8C, ++0x00,0x00,0x00,0x00, ++0x00,0x80,0x42,0x38, ++0xD4,0x1B,0x62,0xAC, ++0x30,0x1F,0x70,0x26, ++0xD0,0x1B,0x02,0x8E, ++0x01,0x00,0x03,0x3C, ++0x24,0x10,0x52,0x00, ++0x24,0x10,0x54,0x00, ++0x24,0x10,0x43,0x00, ++0x11,0xFE,0x40,0x10, ++0x00,0x00,0x00,0x00, ++0x8C,0x33,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x2A,0xB0,0x05,0x3C, ++0x10,0x00,0xA3,0x34, ++0x00,0x00,0x69,0x8C, ++0xFF,0x00,0x06,0x24, ++0xFF,0x00,0x24,0x31, ++0x7C,0x02,0x86,0x10, ++0x25,0xB0,0x02,0x3C, ++0x00,0x80,0x22,0x31, ++0xD0,0x01,0x40,0x10, ++0x00,0x80,0x02,0x3C, ++0x00,0x00,0x62,0xAC, ++0xFF,0x00,0x02,0x24, ++0x22,0x00,0x82,0x10, ++0x30,0x1F,0x70,0x26, ++0xFF,0x00,0x23,0x31, ++0x34,0x37,0x05,0x8E, ++0x20,0x10,0x02,0x3C, ++0x00,0x1A,0x03,0x00, ++0x21,0x18,0x62,0x00, ++0x21,0x30,0x60,0x00, ++0x90,0x36,0x09,0xA2, ++0xC8,0x36,0x03,0xAE, ++0x03,0x00,0x04,0x24, ++0x80,0x00,0x07,0x24, ++0x73,0x01,0x00,0x0C, ++0x10,0x00,0xA0,0xAF, ++0x02,0x80,0x09,0x3C, ++0xCC,0x5E,0x27,0x91, ++0x02,0x80,0x08,0x3C, ++0xBC,0x5E,0x05,0x8D, ++0xD0,0x1B,0x06,0x8E, ++0x01,0x00,0x02,0x3C, ++0x00,0x80,0x42,0x34, ++0x40,0x00,0xE7,0x34, ++0x27,0x10,0x02,0x00, ++0x24,0x30,0xC2,0x00, ++0x80,0x00,0xA5,0x34, ++0x00,0x26,0x07,0x00, ++0x25,0xB0,0x02,0x3C, ++0x25,0x20,0x85,0x00, ++0x80,0x03,0x42,0x34, ++0x41,0xB0,0x03,0x3C, ++0x00,0x00,0x44,0xAC, ++0x00,0x00,0x66,0xAC, ++0xBC,0x5E,0x05,0xAD, ++0xCC,0x5E,0x27,0xA1, ++0xD0,0x1B,0x06,0xAE, ++0x30,0x1F,0x62,0x26, ++0xD4,0x1B,0x43,0x8C, ++0x01,0x00,0x04,0x3C, ++0x30,0x1F,0x70,0x26, ++0x26,0x18,0x64,0x00, ++0xD4,0x1B,0x43,0xAC, ++0xD0,0x1B,0x02,0x8E, ++0x02,0x00,0x03,0x3C, ++0x24,0x10,0x52,0x00, ++0x24,0x10,0x43,0x00, ++0xDB,0xFD,0x40,0x10, ++0x00,0x00,0x00,0x00, ++0x8C,0x33,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x2A,0xB0,0x05,0x3C, ++0x14,0x00,0xA3,0x34, ++0x00,0x00,0x69,0x8C, ++0xFF,0x00,0x06,0x24, ++0xFF,0x00,0x24,0x31, ++0x64,0x02,0x86,0x10, ++0x25,0xB0,0x02,0x3C, ++0x00,0x80,0x22,0x31, ++0xFA,0x01,0x40,0x10, ++0x00,0xFF,0x02,0x3C, ++0x00,0x80,0x02,0x3C, ++0x00,0x00,0x62,0xAC, ++0xFF,0x00,0x02,0x24, ++0x25,0x00,0x82,0x10, ++0x30,0x1F,0x70,0x26, ++0xFF,0x00,0x23,0x31, ++0x40,0x37,0x05,0x8E, ++0x20,0x10,0x02,0x3C, ++0x00,0x1A,0x03,0x00, ++0x21,0x18,0x62,0x00, ++0x21,0x30,0x60,0x00, ++0x94,0x36,0x09,0xA2, ++0xD4,0x36,0x03,0xAE, ++0x04,0x00,0x04,0x24, ++0x80,0x00,0x07,0x24, ++0x73,0x01,0x00,0x0C, ++0x10,0x00,0xA0,0xAF, ++0x02,0x80,0x0A,0x3C, ++0xCC,0x5E,0x47,0x91, ++0x02,0x80,0x09,0x3C, ++0xBC,0x5E,0x25,0x8D, ++0xD0,0x1B,0x06,0x8E, ++0x06,0x00,0x02,0x3C, ++0x20,0x00,0xE7,0x34, ++0x27,0x10,0x02,0x00, ++0x24,0x30,0xC2,0x00, ++0x00,0x01,0xA5,0x34, ++0x25,0xB0,0x03,0x3C, ++0x04,0x00,0x02,0x3C, ++0x00,0x26,0x07,0x00, ++0x26,0xA0,0x82,0x02, ++0xB0,0x03,0x68,0x34, ++0x25,0x20,0x85,0x00, ++0x80,0x03,0x63,0x34, ++0x41,0xB0,0x02,0x3C, ++0x00,0x00,0x64,0xAC, ++0x00,0x00,0x46,0xAC, ++0xBC,0x5E,0x25,0xAD, ++0xCC,0x5E,0x47,0xA1, ++0xD0,0x1B,0x06,0xAE, ++0x00,0x00,0x14,0xAD, ++0x30,0x1F,0x62,0x26, ++0xD4,0x1B,0x43,0x8C, ++0x02,0x00,0x04,0x3C, ++0x30,0x1F,0x70,0x26, ++0x26,0x18,0x64,0x00, ++0xD4,0x1B,0x43,0xAC, ++0xD0,0x1B,0x02,0x8E, ++0x04,0x00,0x03,0x3C, ++0x24,0x10,0x52,0x00, ++0x24,0x10,0x54,0x00, ++0x24,0x10,0x43,0x00, ++0xA1,0xFD,0x40,0x10, ++0x00,0x00,0x00,0x00, ++0x8C,0x33,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x25,0xB0,0x03,0x3C, ++0xB0,0x03,0x62,0x34, ++0x2A,0xB0,0x07,0x3C, ++0x00,0x00,0x54,0xAC, ++0x18,0x00,0xE5,0x34, ++0x00,0x00,0xA9,0x8C, ++0xFF,0x00,0x06,0x24, ++0xFF,0x00,0x24,0x31, ++0x16,0x02,0x86,0x10, ++0x04,0x00,0x02,0x24, ++0x00,0x80,0x22,0x31, ++0xD6,0x01,0x40,0x10, ++0x00,0xFF,0x02,0x3C, ++0x00,0x80,0x02,0x3C, ++0x00,0x00,0xA2,0xAC, ++0xFF,0x00,0x02,0x24, ++0x21,0x00,0x82,0x10, ++0x30,0x1F,0x70,0x26, ++0xFF,0x00,0x23,0x31, ++0x40,0x37,0x05,0x8E, ++0x20,0x10,0x02,0x3C, ++0x00,0x1A,0x03,0x00, ++0x21,0x18,0x62,0x00, ++0x21,0x30,0x60,0x00, ++0x98,0x36,0x09,0xA2, ++0xD4,0x36,0x03,0xAE, ++0x04,0x00,0x04,0x24, ++0x80,0x00,0x07,0x24, ++0x73,0x01,0x00,0x0C, ++0x10,0x00,0xA0,0xAF, ++0x02,0x80,0x09,0x3C, ++0xCC,0x5E,0x27,0x91, ++0x02,0x80,0x08,0x3C, ++0xBC,0x5E,0x05,0x8D, ++0xD0,0x1B,0x06,0x8E, ++0x06,0x00,0x02,0x3C, ++0x10,0x00,0xE7,0x34, ++0x27,0x10,0x02,0x00, ++0x24,0x30,0xC2,0x00, ++0x00,0x01,0xA5,0x34, ++0x00,0x26,0x07,0x00, ++0x25,0xB0,0x02,0x3C, ++0x25,0x20,0x85,0x00, ++0x80,0x03,0x42,0x34, ++0x41,0xB0,0x03,0x3C, ++0x00,0x00,0x44,0xAC, ++0x00,0x00,0x66,0xAC, ++0xBC,0x5E,0x05,0xAD, ++0xCC,0x5E,0x27,0xA1, ++0xD0,0x1B,0x06,0xAE, ++0x30,0x1F,0x62,0x26, ++0xD4,0x1B,0x43,0x8C, ++0x04,0x00,0x04,0x3C, ++0x30,0x1F,0x70,0x26, ++0x26,0x18,0x64,0x00, ++0xD4,0x1B,0x43,0xAC, ++0xD0,0x1B,0x02,0x8E, ++0x08,0x00,0x03,0x3C, ++0x24,0x10,0x52,0x00, ++0x24,0x10,0x43,0x00, ++0x68,0xFD,0x40,0x10, ++0x00,0x00,0x00,0x00, ++0x8C,0x33,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x2A,0xB0,0x05,0x3C, ++0x1C,0x00,0xA3,0x34, ++0x00,0x00,0x69,0x8C, ++0xFF,0x00,0x06,0x24, ++0xFF,0x00,0x24,0x31, ++0xDD,0x01,0x86,0x10, ++0x25,0xB0,0x02,0x3C, ++0x00,0x80,0x22,0x31, ++0x33,0x01,0x40,0x10, ++0x00,0xFF,0x02,0x3C, ++0x00,0x80,0x02,0x3C, ++0x00,0x00,0x62,0xAC, ++0xFF,0x00,0x02,0x24, ++0x25,0x00,0x82,0x10, ++0x30,0x1F,0x70,0x26, ++0xFF,0x00,0x23,0x31, ++0x4C,0x37,0x05,0x8E, ++0x20,0x10,0x02,0x3C, ++0x00,0x1A,0x03,0x00, ++0x21,0x18,0x62,0x00, ++0x21,0x30,0x60,0x00, ++0x9C,0x36,0x09,0xA2, ++0xE0,0x36,0x03,0xAE, ++0x05,0x00,0x04,0x24, ++0x80,0x00,0x07,0x24, ++0x73,0x01,0x00,0x0C, ++0x10,0x00,0xA0,0xAF, ++0x02,0x80,0x0A,0x3C, ++0xCC,0x5E,0x47,0x91, ++0x02,0x80,0x09,0x3C, ++0xBC,0x5E,0x25,0x8D, ++0xD0,0x1B,0x06,0x8E, ++0x18,0x00,0x02,0x3C, ++0x08,0x00,0xE7,0x34, ++0x27,0x10,0x02,0x00, ++0x24,0x30,0xC2,0x00, ++0x00,0x02,0xA5,0x34, ++0x25,0xB0,0x03,0x3C, ++0x10,0x00,0x02,0x3C, ++0x00,0x26,0x07,0x00, ++0x26,0xA0,0x82,0x02, ++0xB0,0x03,0x68,0x34, ++0x25,0x20,0x85,0x00, ++0x80,0x03,0x63,0x34, ++0x41,0xB0,0x02,0x3C, ++0x00,0x00,0x64,0xAC, ++0x00,0x00,0x46,0xAC, ++0xBC,0x5E,0x25,0xAD, ++0xCC,0x5E,0x47,0xA1, ++0xD0,0x1B,0x06,0xAE, ++0x00,0x00,0x14,0xAD, ++0x30,0x1F,0x62,0x26, ++0xD4,0x1B,0x43,0x8C, ++0x08,0x00,0x04,0x3C, ++0x26,0x18,0x64,0x00, ++0x9E,0x35,0x00,0x08, ++0xD4,0x1B,0x43,0xAC, ++0x8C,0x33,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0xD4,0x1B,0x02,0x8E, ++0xD0,0x1B,0x03,0x8E, ++0x00,0x20,0x42,0x38, ++0x7D,0x35,0x00,0x08, ++0xD4,0x1B,0x02,0xAE, ++0x8C,0x33,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x2A,0xB0,0x02,0x3C, ++0x08,0x00,0x43,0x34, ++0x00,0x00,0x69,0x8C, ++0xFF,0x00,0x02,0x24, ++0xFF,0x00,0x24,0x31, ++0x2C,0x00,0x82,0x10, ++0x00,0x80,0x22,0x31, ++0x34,0x01,0x40,0x14, ++0x00,0x80,0x02,0x3C, ++0x00,0xFF,0x02,0x3C, ++0x24,0x10,0x22,0x01, ++0x0B,0x00,0x40,0x10, ++0xFF,0x00,0x02,0x24, ++0xB4,0x36,0x02,0x92, ++0x20,0xB0,0x03,0x3C, ++0x00,0x12,0x02,0x00, ++0x21,0x10,0x43,0x00, ++0x0C,0x00,0x49,0x8C, ++0x25,0xB0,0x03,0x3C, ++0xB0,0x03,0x63,0x34, ++0x00,0x00,0x69,0xAC, ++0xFF,0x00,0x24,0x31, ++0xFF,0x00,0x02,0x24, ++0x1A,0x00,0x82,0x10, ++0x30,0x1F,0x70,0x26, ++0xFF,0x00,0x23,0x31, ++0x7C,0x37,0x05,0x8E, ++0x20,0x10,0x02,0x3C, ++0x00,0x1A,0x03,0x00, ++0x21,0x18,0x62,0x00, ++0x21,0x30,0x60,0x00, ++0x10,0x37,0x03,0xAE, ++0x01,0x00,0x04,0x24, ++0xB4,0x36,0x09,0xA2, ++0x80,0x00,0x07,0x24, ++0x73,0x01,0x00,0x0C, ++0x10,0x00,0xA0,0xAF, ++0xD0,0x1B,0x05,0x8E, ++0x02,0x80,0x06,0x3C, ++0xBC,0x5E,0xC4,0x8C, ++0xFF,0xC7,0x02,0x24, ++0x24,0x28,0xA2,0x00, ++0x25,0xB0,0x02,0x3C, ++0x10,0x00,0x84,0x34, ++0x80,0x03,0x42,0x34, ++0x41,0xB0,0x03,0x3C, ++0x00,0x00,0x44,0xAC, ++0x00,0x00,0x65,0xAC, ++0xBC,0x5E,0xC4,0xAC, ++0xD0,0x1B,0x05,0xAE, ++0x30,0x1F,0x63,0x26, ++0xD4,0x1B,0x62,0x8C, ++0x00,0x00,0x00,0x00, ++0x00,0x10,0x42,0x38, ++0x76,0x35,0x00,0x08, ++0xD4,0x1B,0x62,0xAC, ++0x56,0x01,0x02,0x35, ++0x00,0x00,0x43,0x94, ++0x00,0x00,0x00,0x00, ++0x70,0xFC,0x60,0x10, ++0x00,0x00,0x00,0x00, ++0x93,0x55,0x00,0x0C, ++0x07,0x00,0x04,0x24, ++0x29,0x35,0x00,0x08, ++0x30,0x1F,0x64,0x26, ++0x00,0x00,0x62,0xAC, ++0xD3,0x35,0x00,0x08, ++0xFF,0x00,0x02,0x24, ++0xF8,0x1D,0x24,0x96, ++0x64,0x37,0x25,0x8E, ++0xFF,0x0F,0x83,0x30, ++0x25,0x28,0xA2,0x00, ++0x00,0x19,0x03,0x00, ++0x20,0x00,0xA6,0x24, ++0x02,0x12,0x03,0x00, ++0x01,0x00,0x84,0x24, ++0xF8,0x1D,0x24,0xA6, ++0x17,0x00,0xC2,0xA0, ++0x16,0x00,0xC3,0xA0, ++0x0C,0x00,0xA4,0x8C, ++0x00,0xF0,0x02,0x3C, ++0xFF,0xFF,0x42,0x34, ++0xFF,0x0F,0x63,0x30, ++0x00,0x1C,0x03,0x00, ++0x24,0x20,0x82,0x00, ++0x25,0x20,0x83,0x00, ++0x0C,0x00,0xA4,0xAC, ++0x64,0x37,0x25,0x8E, ++0x01,0x00,0x10,0x24, ++0x01,0x00,0x04,0x24, ++0x31,0x10,0x06,0x3C, ++0x00,0x01,0x07,0x24, ++0x73,0x01,0x00,0x0C, ++0x10,0x00,0xB0,0xAF, ++0xB0,0x01,0x00,0x0C, ++0x01,0x00,0x04,0x24, ++0x2A,0xB0,0x02,0x3C, ++0x01,0x00,0x42,0x34, ++0x02,0x00,0x03,0x24, ++0x00,0x00,0x50,0xA0, ++0x00,0x00,0x43,0xA0, ++0xD4,0x1B,0x22,0x8E, ++0x00,0x00,0x00,0x00, ++0x08,0x00,0x42,0x38, ++0x68,0x35,0x00,0x08, ++0xD4,0x1B,0x22,0xAE, ++0xD0,0x03,0x23,0x35, ++0x80,0x00,0x02,0x24, ++0x00,0x00,0x62,0xAC, ++0x24,0x36,0x00,0x08, ++0x30,0x1F,0x62,0x26, ++0x25,0xB0,0x02,0x3C, ++0x01,0x00,0x03,0x24, ++0x90,0x03,0x42,0x34, ++0x00,0x00,0x43,0xAC, ++0xF0,0x35,0x00,0x08, ++0x30,0x1F,0x65,0x26, ++0x24,0x10,0x22,0x01, ++0xA9,0xFD,0x40,0x10, ++0xFF,0x00,0x02,0x24, ++0x47,0x00,0xC6,0x34, ++0x00,0x00,0xC2,0x90, ++0x00,0x00,0x00,0x00, ++0xFF,0x00,0x44,0x30, ++0x0E,0x00,0x85,0x10, ++0x30,0x1F,0x62,0x26, ++0xA4,0x36,0x04,0xA2, ++0x00,0x00,0xC2,0x90, ++0xFF,0x00,0x83,0x30, ++0xFF,0x00,0x44,0x30, ++0x07,0x00,0x83,0x10, ++0x21,0x38,0x00,0x02, ++0x21,0x28,0xC0,0x00, ++0x00,0x00,0xA2,0x90, ++0x21,0x18,0x80,0x00, ++0xFD,0xFF,0x62,0x14, ++0xFF,0x00,0x44,0x30, ++0xA4,0x36,0xE3,0xA0, ++0x30,0x1F,0x62,0x26, ++0xA4,0x36,0x43,0x90, ++0x20,0xB0,0x02,0x3C, ++0x00,0x1A,0x03,0x00, ++0x21,0x18,0x62,0x00, ++0x0C,0x00,0x69,0x8C, ++0x25,0xB0,0x02,0x3C, ++0xB0,0x03,0x42,0x34, ++0xFF,0x00,0x24,0x31, ++0x00,0x00,0x49,0xAC, ++0x9C,0x36,0x00,0x08, ++0xFF,0x00,0x02,0x24, ++0x24,0x10,0x22,0x01, ++0xFD,0xFD,0x40,0x10, ++0xFF,0x00,0x02,0x24, ++0x45,0x00,0xE5,0x34, ++0x00,0x00,0xA2,0x90, ++0x00,0x00,0x00,0x00, ++0xFF,0x00,0x44,0x30, ++0x0E,0x00,0x86,0x10, ++0x30,0x1F,0x62,0x26, ++0xA8,0x36,0x04,0xA2, ++0x00,0x00,0xA2,0x90, ++0xFF,0x00,0x83,0x30, ++0xFF,0x00,0x44,0x30, ++0x08,0x00,0x83,0x10, ++0x30,0x1F,0x62,0x26, ++0x21,0x30,0x00,0x02, ++0x00,0x00,0xA2,0x90, ++0x21,0x18,0x80,0x00, ++0xFD,0xFF,0x62,0x14, ++0xFF,0x00,0x44,0x30, ++0xA8,0x36,0xC3,0xA0, ++0x30,0x1F,0x62,0x26, ++0xA8,0x36,0x43,0x90, ++0x20,0xB0,0x02,0x3C, ++0x00,0x1A,0x03,0x00, ++0x21,0x18,0x62,0x00, ++0x0C,0x00,0x69,0x8C, ++0x25,0xB0,0x02,0x3C, ++0xB0,0x03,0x42,0x34, ++0xFF,0x00,0x24,0x31, ++0x00,0x00,0x49,0xAC, ++0x11,0x37,0x00,0x08, ++0xFF,0x00,0x02,0x24, ++0x24,0x10,0x22,0x01, ++0x9E,0xFD,0x40,0x10, ++0xFF,0x00,0x02,0x24, ++0x46,0x00,0xA5,0x34, ++0x00,0x00,0xA2,0x90, ++0x00,0x00,0x00,0x00, ++0xFF,0x00,0x44,0x30, ++0x0E,0x00,0x86,0x10, ++0x30,0x1F,0x62,0x26, ++0xA0,0x36,0x04,0xA2, ++0x00,0x00,0xA2,0x90, ++0xFF,0x00,0x83,0x30, ++0xFF,0x00,0x44,0x30, ++0x08,0x00,0x83,0x10, ++0x30,0x1F,0x62,0x26, ++0x21,0x30,0x00,0x02, ++0x00,0x00,0xA2,0x90, ++0x21,0x18,0x80,0x00, ++0xFD,0xFF,0x62,0x14, ++0xFF,0x00,0x44,0x30, ++0xA0,0x36,0xC3,0xA0, ++0x30,0x1F,0x62,0x26, ++0xA0,0x36,0x43,0x90, ++0x20,0xB0,0x02,0x3C, ++0x00,0x1A,0x03,0x00, ++0x21,0x18,0x62,0x00, ++0x0C,0x00,0x69,0x8C, ++0x25,0xB0,0x02,0x3C, ++0xB0,0x03,0x42,0x34, ++0xFF,0x00,0x24,0x31, ++0x00,0x00,0x49,0xAC, ++0xD3,0x36,0x00,0x08, ++0xFF,0x00,0x02,0x24, ++0x00,0xFF,0x02,0x3C, ++0x24,0x10,0x22,0x01, ++0x30,0xFE,0x40,0x10, ++0xFF,0x00,0x02,0x24, ++0x41,0x00,0xA5,0x34, ++0x00,0x00,0xA2,0x90, ++0x00,0x00,0x00,0x00, ++0xFF,0x00,0x44,0x30, ++0x0E,0x00,0x86,0x10, ++0x30,0x1F,0x62,0x26, ++0x90,0x36,0x04,0xA2, ++0x00,0x00,0xA2,0x90, ++0xFF,0x00,0x83,0x30, ++0xFF,0x00,0x44,0x30, ++0x08,0x00,0x83,0x10, ++0x30,0x1F,0x62,0x26, ++0x21,0x30,0x00,0x02, ++0x00,0x00,0xA2,0x90, ++0x21,0x18,0x80,0x00, ++0xFD,0xFF,0x62,0x14, ++0xFF,0x00,0x44,0x30, ++0x90,0x36,0xC3,0xA0, ++0x30,0x1F,0x62,0x26, ++0x90,0x36,0x43,0x90, ++0x20,0xB0,0x02,0x3C, ++0x00,0x1A,0x03,0x00, ++0x21,0x18,0x62,0x00, ++0x0C,0x00,0x69,0x8C, ++0x25,0xB0,0x02,0x3C, ++0xB0,0x03,0x42,0x34, ++0xFF,0x00,0x24,0x31, ++0x00,0x00,0x49,0xAC, ++0x87,0x37,0x00,0x08, ++0xFF,0x00,0x02,0x24, ++0x24,0x10,0x22,0x01, ++0xCF,0xFE,0x40,0x10, ++0xFF,0x00,0x02,0x24, ++0x44,0x00,0xA5,0x34, ++0x00,0x00,0xA2,0x90, ++0x00,0x00,0x00,0x00, ++0xFF,0x00,0x44,0x30, ++0x0E,0x00,0x86,0x10, ++0x30,0x1F,0x62,0x26, ++0x9C,0x36,0x04,0xA2, ++0x00,0x00,0xA2,0x90, ++0xFF,0x00,0x83,0x30, ++0xFF,0x00,0x44,0x30, ++0x08,0x00,0x83,0x10, ++0x30,0x1F,0x62,0x26, ++0x21,0x30,0x00,0x02, ++0x00,0x00,0xA2,0x90, ++0x21,0x18,0x80,0x00, ++0xFD,0xFF,0x62,0x14, ++0xFF,0x00,0x44,0x30, ++0x9C,0x36,0xC3,0xA0, ++0x30,0x1F,0x62,0x26, ++0x9C,0x36,0x43,0x90, ++0x20,0xB0,0x02,0x3C, ++0x00,0x1A,0x03,0x00, ++0x21,0x18,0x62,0x00, ++0x0C,0x00,0x69,0x8C, ++0x25,0xB0,0x02,0x3C, ++0xB0,0x03,0x42,0x34, ++0xFF,0x00,0x24,0x31, ++0x00,0x00,0x49,0xAC, ++0x47,0x38,0x00,0x08, ++0xFF,0x00,0x02,0x24, ++0x24,0x10,0x22,0x01, ++0xAE,0xFD,0x40,0x10, ++0xFF,0x00,0x02,0x24, ++0x40,0x00,0xA5,0x34, ++0x00,0x00,0xA2,0x90, ++0x00,0x00,0x00,0x00, ++0xFF,0x00,0x44,0x30, ++0x0E,0x00,0x86,0x10, ++0x30,0x1F,0x62,0x26, ++0x8C,0x36,0x04,0xA2, ++0x00,0x00,0xA2,0x90, ++0xFF,0x00,0x83,0x30, ++0xFF,0x00,0x44,0x30, ++0x08,0x00,0x83,0x10, ++0x30,0x1F,0x62,0x26, ++0x21,0x30,0x00,0x02, ++0x00,0x00,0xA2,0x90, ++0x21,0x18,0x80,0x00, ++0xFD,0xFF,0x62,0x14, ++0xFF,0x00,0x44,0x30, ++0x8C,0x36,0xC3,0xA0, ++0x30,0x1F,0x62,0x26, ++0x8C,0x36,0x43,0x90, ++0x20,0xB0,0x02,0x3C, ++0x00,0x1A,0x03,0x00, ++0x21,0x18,0x62,0x00, ++0x0C,0x00,0x69,0x8C, ++0x25,0xB0,0x02,0x3C, ++0xB0,0x03,0x42,0x34, ++0xFF,0x00,0x24,0x31, ++0x00,0x00,0x49,0xAC, ++0x47,0x37,0x00,0x08, ++0xFF,0x00,0x02,0x24, ++0x00,0x00,0x62,0xAC, ++0x93,0x38,0x00,0x08, ++0xFF,0x00,0x02,0x24, ++0x24,0x10,0x22,0x01, ++0x08,0xFE,0x40,0x10, ++0xFF,0x00,0x02,0x24, ++0x42,0x00,0xA5,0x34, ++0x00,0x00,0xA2,0x90, ++0x00,0x00,0x00,0x00, ++0xFF,0x00,0x44,0x30, ++0x0E,0x00,0x86,0x10, ++0x30,0x1F,0x62,0x26, ++0x94,0x36,0x04,0xA2, ++0x00,0x00,0xA2,0x90, ++0xFF,0x00,0x83,0x30, ++0xFF,0x00,0x44,0x30, ++0x08,0x00,0x83,0x10, ++0x30,0x1F,0x62,0x26, ++0x21,0x30,0x00,0x02, ++0x00,0x00,0xA2,0x90, ++0x21,0x18,0x80,0x00, ++0xFD,0xFF,0x62,0x14, ++0xFF,0x00,0x44,0x30, ++0x94,0x36,0xC3,0xA0, ++0x30,0x1F,0x62,0x26, ++0x94,0x36,0x43,0x90, ++0x20,0xB0,0x02,0x3C, ++0x00,0x1A,0x03,0x00, ++0x21,0x18,0x62,0x00, ++0x0C,0x00,0x69,0x8C, ++0x25,0xB0,0x02,0x3C, ++0xB0,0x03,0x42,0x34, ++0xFF,0x00,0x24,0x31, ++0x00,0x00,0x49,0xAC, ++0xC5,0x37,0x00,0x08, ++0xFF,0x00,0x02,0x24, ++0x24,0x10,0x22,0x01, ++0x2C,0xFE,0x40,0x10, ++0xFF,0x00,0x02,0x24, ++0x43,0x00,0xE5,0x34, ++0x00,0x00,0xA2,0x90, ++0x00,0x00,0x00,0x00, ++0xFF,0x00,0x44,0x30, ++0x0E,0x00,0x86,0x10, ++0x30,0x1F,0x62,0x26, ++0x98,0x36,0x04,0xA2, ++0x00,0x00,0xA2,0x90, ++0xFF,0x00,0x83,0x30, ++0xFF,0x00,0x44,0x30, ++0x08,0x00,0x83,0x10, ++0x30,0x1F,0x62,0x26, ++0x21,0x30,0x00,0x02, ++0x00,0x00,0xA2,0x90, ++0x21,0x18,0x80,0x00, ++0xFD,0xFF,0x62,0x14, ++0xFF,0x00,0x44,0x30, ++0x98,0x36,0xC3,0xA0, ++0x30,0x1F,0x62,0x26, ++0x98,0x36,0x43,0x90, ++0x20,0xB0,0x02,0x3C, ++0x00,0x1A,0x03,0x00, ++0x21,0x18,0x62,0x00, ++0x0C,0x00,0x69,0x8C, ++0x25,0xB0,0x02,0x3C, ++0xB0,0x03,0x42,0x34, ++0xFF,0x00,0x24,0x31, ++0x00,0x00,0x49,0xAC, ++0x0A,0x38,0x00,0x08, ++0xFF,0x00,0x02,0x24, ++0x06,0x00,0x03,0x24, ++0x90,0x03,0x42,0x34, ++0x00,0x00,0x43,0xAC, ++0xAB,0x37,0x00,0x08, ++0x30,0x1F,0x62,0x26, ++0x01,0x00,0x03,0x24, ++0x90,0x03,0x42,0x34, ++0x00,0x00,0x43,0xAC, ++0xBF,0x36,0x00,0x08, ++0x30,0x1F,0x62,0x26, ++0x25,0xB0,0x02,0x3C, ++0x07,0x00,0x03,0x24, ++0x90,0x03,0x42,0x34, ++0x00,0x00,0x43,0xAC, ++0x30,0x1F,0x63,0x26, ++0xD4,0x1B,0x62,0x8C, ++0x00,0x00,0x00,0x00, ++0x00,0x80,0x42,0x38, ++0x71,0x37,0x00,0x08, ++0xD4,0x1B,0x62,0xAC, ++0x00,0x00,0x40,0xAC, ++0x34,0x37,0x00,0x08, ++0x30,0x1F,0x62,0x26, ++0x02,0x00,0x03,0x24, ++0x90,0x03,0x42,0x34, ++0x00,0x00,0x43,0xAC, ++0xFA,0x36,0x00,0x08, ++0x30,0x1F,0x62,0x26, ++0x90,0x03,0x63,0x34, ++0x00,0x00,0x62,0xAC, ++0x2D,0x38,0x00,0x08, ++0x30,0x1F,0x62,0x26, ++0x03,0x00,0x03,0x24, ++0x90,0x03,0x42,0x34, ++0x00,0x00,0x43,0xAC, ++0x6E,0x38,0x00,0x08, ++0x30,0x1F,0x62,0x26, ++0x05,0x00,0x03,0x24, ++0x90,0x03,0x42,0x34, ++0x00,0x00,0x43,0xAC, ++0xEC,0x37,0x00,0x08, ++0x30,0x1F,0x62,0x26, ++0xE0,0xFF,0xBD,0x27, ++0x1C,0x00,0xBF,0xAF, ++0x18,0x00,0xB2,0xAF, ++0x14,0x00,0xB1,0xAF, ++0x10,0x00,0xB0,0xAF, ++0x25,0xB0,0x0C,0x3C, ++0x01,0x80,0x02,0x3C, ++0x18,0x03,0x83,0x35, ++0x9C,0xE8,0x42,0x24, ++0x02,0x80,0x12,0x3C, ++0x41,0xB0,0x0B,0x3C, ++0x00,0x00,0x62,0xAC, ++0x30,0x1F,0x4A,0x26, ++0x0A,0x00,0x62,0x35, ++0x00,0x00,0x44,0x94, ++0xDE,0x1B,0x43,0x95, ++0xDC,0x1B,0x49,0x95, ++0x25,0x30,0x64,0x00, ++0xFF,0xFF,0xD0,0x30, ++0x24,0x10,0x09,0x02, ++0x02,0x00,0x42,0x30, ++0xC2,0x00,0x40,0x10, ++0xC0,0x03,0x83,0x35, ++0x02,0x00,0x02,0x24, ++0x00,0x00,0x62,0xAC, ++0x02,0x80,0x08,0x3C, ++0xBC,0x5E,0x04,0x8D, ++0xDC,0x02,0x82,0x35, ++0x00,0x00,0x47,0x90, ++0xFD,0xFF,0x03,0x24, ++0x00,0x80,0x02,0x3C, ++0x24,0x18,0x23,0x01, ++0x25,0x20,0x82,0x00, ++0x02,0x00,0xC6,0x38, ++0x08,0x00,0x65,0x35, ++0x02,0x80,0x02,0x3C, ++0xF5,0x5E,0x47,0xA0, ++0xBC,0x5E,0x04,0xAD, ++0xDE,0x1B,0x46,0xA5, ++0x21,0x48,0x60,0x00, ++0x00,0x00,0xA3,0xA4, ++0xDC,0x1B,0x43,0xA5, ++0x24,0x38,0x09,0x02, ++0x04,0x00,0xE2,0x30, ++0x0A,0x00,0x40,0x10, ++0x08,0x00,0xE2,0x30, ++0xDE,0x1B,0x43,0x95, ++0x0C,0x00,0x64,0x35, ++0xC0,0x03,0x85,0x35, ++0x04,0x00,0x63,0x38, ++0x04,0x00,0x02,0x24, ++0x00,0x00,0x86,0x8C, ++0x00,0x00,0xA2,0xAC, ++0xDE,0x1B,0x43,0xA5, ++0x08,0x00,0xE2,0x30, ++0x08,0x00,0x40,0x10, ++0x10,0x00,0xE2,0x30, ++0xDE,0x1B,0x42,0x95, ++0xC0,0x03,0x84,0x35, ++0x08,0x00,0x03,0x24, ++0x08,0x00,0x42,0x38, ++0x00,0x00,0x83,0xAC, ++0xDE,0x1B,0x42,0xA5, ++0x10,0x00,0xE2,0x30, ++0x08,0x00,0x40,0x10, ++0x20,0x00,0xE2,0x30, ++0xDE,0x1B,0x42,0x95, ++0xC0,0x03,0x84,0x35, ++0x10,0x00,0x03,0x24, ++0x10,0x00,0x42,0x38, ++0x00,0x00,0x83,0xAC, ++0xDE,0x1B,0x42,0xA5, ++0x20,0x00,0xE2,0x30, ++0x08,0x00,0x40,0x10, ++0x80,0x00,0xE2,0x30, ++0xDE,0x1B,0x42,0x95, ++0xC0,0x03,0x84,0x35, ++0x20,0x00,0x03,0x24, ++0x20,0x00,0x42,0x38, ++0x00,0x00,0x83,0xAC, ++0xDE,0x1B,0x42,0xA5, ++0x80,0x00,0xE2,0x30, ++0x74,0x00,0x40,0x10, ++0x30,0x1F,0x47,0x26, ++0xC0,0x03,0x83,0x35, ++0x80,0x00,0x02,0x24, ++0x42,0xB0,0x0B,0x3C, ++0x00,0x00,0x62,0xAC, ++0x03,0x00,0x71,0x35, ++0xDE,0x1B,0x42,0x95, ++0x00,0x00,0x23,0x92, ++0x80,0x00,0x42,0x38, ++0x20,0x00,0x63,0x30, ++0x59,0x00,0x60,0x10, ++0xDE,0x1B,0x42,0xA5, ++0x20,0x00,0x02,0x24, ++0x00,0x00,0x22,0xA2, ++0x02,0x80,0x03,0x3C, ++0x16,0x5F,0x62,0x90, ++0x00,0x00,0x00,0x00, ++0x75,0x00,0x40,0x14, ++0x21,0x40,0x00,0x00, ++0xB0,0x1B,0x42,0x95, ++0x00,0x00,0x00,0x00, ++0x00,0x01,0x42,0x30, ++0x4E,0x00,0x40,0x10, ++0x02,0x80,0x06,0x3C, ++0x02,0x80,0x07,0x3C, ++0xF4,0x5E,0xE2,0x90, ++0x00,0x00,0x00,0x00, ++0x49,0x00,0x40,0x10, ++0x02,0x80,0x09,0x3C, ++0x02,0x80,0x04,0x3C, ++0x00,0x5F,0x82,0x8C, ++0x20,0x5F,0x24,0x8D, ++0x24,0x5F,0x25,0x8D, ++0x21,0x18,0x00,0x00, ++0x21,0x10,0x44,0x00, ++0x2B,0x30,0x44,0x00, ++0x21,0x18,0x65,0x00, ++0x21,0x18,0x66,0x00, ++0x20,0x5F,0x22,0xAD, ++0x24,0x5F,0x23,0xAD, ++0xF4,0x5E,0xE4,0x90, ++0x02,0x00,0x02,0x24, ++0xFF,0x00,0x84,0x30, ++0x07,0x00,0x82,0x10, ++0x02,0x80,0x04,0x3C, ++0xF4,0x5E,0xE2,0x90, ++0x03,0x00,0x03,0x24, ++0xFF,0x00,0x42,0x30, ++0x5A,0x00,0x43,0x14, ++0x02,0x80,0x05,0x3C, ++0x02,0x80,0x04,0x3C, ++0x11,0x5F,0x82,0x90, ++0x00,0x00,0x00,0x00, ++0xFF,0xFF,0x42,0x24, ++0x11,0x5F,0x82,0xA0, ++0x11,0x5F,0x83,0x90, ++0x00,0x00,0x00,0x00, ++0x07,0x00,0x60,0x10, ++0x02,0x80,0x02,0x3C, ++0xFA,0x5E,0x43,0x90, ++0x00,0x00,0x00,0x00, ++0x03,0x00,0x60,0x14, ++0x00,0x00,0x00,0x00, ++0x5B,0x00,0x00,0x11, ++0x80,0x00,0x86,0x35, ++0x11,0x5F,0x82,0x90, ++0x00,0x00,0x00,0x00, ++0x06,0x00,0x40,0x14, ++0x02,0x80,0x05,0x3C, ++0x02,0x80,0x02,0x3C, ++0x10,0x5F,0x43,0x90, ++0x00,0x00,0x00,0x00, ++0x11,0x5F,0x83,0xA0, ++0x02,0x80,0x05,0x3C, ++0x0E,0x5F,0xA2,0x90, ++0x02,0x80,0x03,0x3C, ++0x02,0x00,0x04,0x24, ++0x10,0x00,0x42,0x34, ++0x0E,0x5F,0xA2,0xA0, ++0xF9,0x5E,0x62,0x90, ++0x21,0x28,0x00,0x00, ++0xFF,0x00,0x42,0x30, ++0x80,0x30,0x02,0x00, ++0x21,0x30,0xC2,0x00, ++0x8C,0x23,0x00,0x0C, ++0x00,0x33,0x06,0x00, ++0x42,0xB0,0x02,0x3C, ++0x44,0x00,0x04,0x24, ++0x03,0x00,0x42,0x34, ++0x00,0x00,0x44,0xA0, ++0x02,0x80,0x03,0x3C, ++0xF6,0x5E,0x62,0x90, ++0x00,0x00,0x00,0x00, ++0x0F,0x00,0x42,0x30, ++0x04,0x00,0x42,0x28, ++0x05,0x00,0x40,0x10, ++0x02,0x80,0x06,0x3C, ++0x04,0x00,0x04,0x24, ++0x64,0x31,0x00,0x0C, ++0x01,0x00,0x05,0x24, ++0x02,0x80,0x06,0x3C, ++0xBC,0x5E,0xC4,0x8C, ++0x30,0x1F,0x47,0x26, ++0xDC,0x1B,0xE5,0x94, ++0x08,0x00,0x02,0x3C, ++0x25,0x20,0x82,0x00, ++0x41,0xB0,0x03,0x3C, ++0x25,0xB0,0x02,0x3C, ++0x7F,0xFF,0xA5,0x30, ++0xB0,0x03,0x42,0x34, ++0x08,0x00,0x63,0x34, ++0x00,0x00,0x44,0xAC, ++0x00,0x00,0x65,0xA4, ++0xBC,0x5E,0xC4,0xAC, ++0xDC,0x1B,0xE5,0xA4, ++0x30,0x1F,0x47,0x26, ++0xDC,0x1B,0xE2,0x94, ++0x00,0x00,0x00,0x00, ++0x24,0x10,0x50,0x00, ++0x00,0x30,0x42,0x30, ++0x06,0x00,0x40,0x10, ++0x00,0x00,0x00,0x00, ++0xDE,0x1B,0xE2,0x94, ++0x00,0x00,0x00,0x00, ++0x00,0x10,0x42,0x38, ++0x00,0x20,0x42,0x34, ++0xDE,0x1B,0xE2,0xA4, ++0x1C,0x00,0xBF,0x8F, ++0x18,0x00,0xB2,0x8F, ++0x14,0x00,0xB1,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x08,0x00,0xE0,0x03, ++0x20,0x00,0xBD,0x27, ++0x51,0x3A,0x00,0x08, ++0xDE,0x1B,0x46,0xA5, ++0x01,0x00,0x08,0x24, ++0x16,0x5F,0x60,0xA0, ++0x8D,0x3A,0x00,0x08, ++0x00,0x00,0x00,0x00, ++0x0E,0x5F,0xA2,0x90, ++0x02,0x80,0x03,0x3C, ++0x02,0x00,0x04,0x24, ++0x10,0x00,0x42,0x34, ++0x0E,0x5F,0xA2,0xA0, ++0xF9,0x5E,0x62,0x90, ++0x21,0x28,0x00,0x00, ++0xFF,0x00,0x42,0x30, ++0x80,0x30,0x02,0x00, ++0x21,0x30,0xC2,0x00, ++0x8C,0x23,0x00,0x0C, ++0x00,0x33,0x06,0x00, ++0x44,0x00,0x02,0x24, ++0x00,0x00,0x22,0xA2, ++0xD5,0x3A,0x00,0x08, ++0x02,0x80,0x03,0x3C, ++0x84,0x00,0x84,0x35, ++0x00,0x00,0x82,0x8C, ++0x02,0x80,0x08,0x3C, ++0x00,0x00,0xC4,0x8C, ++0x1C,0x5F,0x06,0x8D, ++0x21,0x10,0x00,0x00, ++0x20,0x5F,0x28,0x8D, ++0x24,0x5F,0x29,0x8D, ++0x00,0x00,0x65,0x91, ++0x25,0x10,0x44,0x00, ++0x21,0x10,0x46,0x00, ++0xFB,0xFF,0x04,0x24, ++0x24,0x28,0xA4,0x00, ++0x23,0x40,0x02,0x01, ++0x00,0x00,0x65,0xA1, ++0x04,0x00,0x00,0x11, ++0x01,0x00,0x06,0x24, ++0x80,0x10,0x08,0x00, ++0x21,0x10,0x48,0x00, ++0x80,0x30,0x02,0x00, ++0x01,0x00,0x04,0x24, ++0x8C,0x23,0x00,0x0C, ++0x21,0x28,0x00,0x00, ++0x42,0xB0,0x02,0x3C, ++0x22,0x00,0x03,0x24, ++0x03,0x00,0x42,0x34, ++0x00,0x00,0x43,0xA0, ++0xDF,0x3A,0x00,0x08, ++0x02,0x80,0x06,0x3C, ++0xF0,0xFF,0xBD,0x27, ++0x08,0x00,0xB2,0xAF, ++0x04,0x00,0xB1,0xAF, ++0x00,0x00,0xB0,0xAF, ++0x00,0x40,0x09,0x40, ++0x00,0x68,0x0A,0x40, ++0x00,0x70,0x02,0x40, ++0x00,0x60,0x0B,0x40, ++0x25,0xB0,0x05,0x3C, ++0x18,0x03,0xA7,0x34, ++0x00,0x00,0xE6,0x8C, ++0x01,0x80,0x02,0x3C, ++0x1C,0x03,0xA3,0x34, ++0xC8,0xEC,0x42,0x24, ++0x00,0x00,0x66,0xAC, ++0x00,0x00,0xE2,0xAC, ++0x80,0x00,0x83,0x8C, ++0x7C,0x02,0xA2,0x34, ++0x80,0x02,0xA6,0x34, ++0x84,0x02,0xA7,0x34, ++0x88,0x02,0xA8,0x34, ++0x00,0x00,0x43,0xAC, ++0x00,0x00,0xC9,0xAC, ++0x00,0x00,0xEA,0xAC, ++0x00,0x00,0x0B,0xAD, ++0x74,0x00,0x83,0x8C, ++0x8C,0x02,0xA2,0x34, ++0x90,0x02,0xA7,0x34, ++0x00,0x00,0x43,0xAC, ++0x08,0x00,0x86,0x8C, ++0x94,0x02,0xA8,0x34, ++0x98,0x02,0xA9,0x34, ++0x00,0x00,0xE6,0xAC, ++0x0C,0x00,0x82,0x8C, ++0x9C,0x02,0xA6,0x34, ++0xA0,0x02,0xA7,0x34, ++0x00,0x00,0x02,0xAD, ++0x10,0x00,0x83,0x8C, ++0xA4,0x02,0xA8,0x34, ++0xA8,0x02,0xAA,0x34, ++0x00,0x00,0x23,0xAD, ++0x14,0x00,0x82,0x8C, ++0xAC,0x02,0xA9,0x34, ++0xB0,0x02,0xAB,0x34, ++0x00,0x00,0xC2,0xAC, ++0x18,0x00,0x83,0x8C, ++0xB4,0x02,0xAC,0x34, ++0xB8,0x02,0xAD,0x34, ++0x00,0x00,0xE3,0xAC, ++0x1C,0x00,0x82,0x8C, ++0xBC,0x02,0xA7,0x34, ++0xC0,0x02,0xAE,0x34, ++0x00,0x00,0x02,0xAD, ++0x20,0x00,0x83,0x8C, ++0xC4,0x02,0xA8,0x34, ++0xC8,0x02,0xAF,0x34, ++0x00,0x00,0x43,0xAD, ++0x24,0x00,0x82,0x8C, ++0xCC,0x02,0xAA,0x34, ++0xD0,0x02,0xB0,0x34, ++0x00,0x00,0x22,0xAD, ++0x28,0x00,0x83,0x8C, ++0xD4,0x02,0xA9,0x34, ++0xD8,0x02,0xB1,0x34, ++0x00,0x00,0x63,0xAD, ++0x2C,0x00,0x86,0x8C, ++0x70,0x02,0xAB,0x34, ++0x74,0x02,0xB2,0x34, ++0x00,0x00,0x86,0xAD, ++0x30,0x00,0x82,0x8C, ++0x78,0x02,0xA6,0x34, ++0x6C,0x03,0xAC,0x34, ++0x00,0x00,0xA2,0xAD, ++0x34,0x00,0x83,0x8C, ++0x02,0x80,0x02,0x3C, ++0x00,0x00,0xE3,0xAC, ++0x38,0x00,0x85,0x8C, ++0x28,0xC7,0x47,0x8C, ++0x00,0x00,0xC5,0xAD, ++0x3C,0x00,0x82,0x8C, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x02,0xAD, ++0x40,0x00,0x83,0x8C, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0xE3,0xAD, ++0x44,0x00,0x82,0x8C, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x42,0xAD, ++0x48,0x00,0x83,0x8C, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x03,0xAE, ++0x4C,0x00,0x82,0x8C, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x22,0xAD, ++0x50,0x00,0x83,0x8C, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x23,0xAE, ++0x54,0x00,0x82,0x8C, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x62,0xAD, ++0x58,0x00,0x83,0x8C, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x43,0xAE, ++0x5C,0x00,0x82,0x8C, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0xC2,0xAC, ++0x21,0x10,0xE0,0x00, ++0x00,0x00,0x82,0xAD, ++0x01,0x00,0xE7,0x24, ++0x21,0x10,0xE0,0x00, ++0x01,0x00,0xE7,0x24, ++0x00,0x00,0x82,0xAD, ++0x9D,0x3B,0x00,0x08, ++0x21,0x10,0xE0,0x00, ++0x01,0x80,0x1B,0x3C, ++0x90,0xEE,0x7B,0x27, ++0x25,0xB0,0x1A,0x3C, ++0x18,0x03,0x5A,0x27, ++0x00,0x00,0x5B,0xAF, ++0x21,0xD8,0xA0,0x03, ++0x82,0xDA,0x1B,0x00, ++0x80,0xDA,0x1B,0x00, ++0x08,0x00,0x7B,0x27, ++0x04,0x00,0x61,0xAF, ++0x08,0x00,0x62,0xAF, ++0x0C,0x00,0x63,0xAF, ++0x10,0x00,0x64,0xAF, ++0x14,0x00,0x65,0xAF, ++0x18,0x00,0x66,0xAF, ++0x1C,0x00,0x67,0xAF, ++0x20,0x00,0x68,0xAF, ++0x24,0x00,0x69,0xAF, ++0x28,0x00,0x6A,0xAF, ++0x2C,0x00,0x6B,0xAF, ++0x30,0x00,0x6C,0xAF, ++0x34,0x00,0x6D,0xAF, ++0x38,0x00,0x6E,0xAF, ++0x3C,0x00,0x6F,0xAF, ++0x12,0x40,0x00,0x00, ++0x10,0x48,0x00,0x00, ++0x00,0x70,0x0A,0x40, ++0x40,0x00,0x70,0xAF, ++0x44,0x00,0x71,0xAF, ++0x48,0x00,0x72,0xAF, ++0x4C,0x00,0x73,0xAF, ++0x50,0x00,0x74,0xAF, ++0x54,0x00,0x75,0xAF, ++0x58,0x00,0x76,0xAF, ++0x5C,0x00,0x77,0xAF, ++0x60,0x00,0x78,0xAF, ++0x64,0x00,0x79,0xAF, ++0x68,0x00,0x7C,0xAF, ++0x6C,0x00,0x7D,0xAF, ++0x70,0x00,0x7E,0xAF, ++0x74,0x00,0x7F,0xAF, ++0x78,0x00,0x68,0xAF, ++0x7C,0x00,0x69,0xAF, ++0x80,0x00,0x6A,0xAF, ++0x00,0x68,0x1A,0x40, ++0x25,0xB0,0x1B,0x3C, ++0x1C,0x03,0x7B,0x37, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x7A,0xAF, ++0x7F,0x00,0x5B,0x33, ++0x30,0x00,0x60,0x13, ++0x00,0x00,0x00,0x00, ++0x25,0xB0,0x1B,0x3C, ++0x30,0x03,0x7B,0x37, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x7A,0xAF, ++0x00,0x00,0x00,0x00, ++0x21,0xD8,0xA0,0x03, ++0x82,0xDA,0x1B,0x00, ++0x80,0xDA,0x1B,0x00, ++0x08,0x00,0x7B,0x27, ++0x04,0x00,0x61,0xAF, ++0x08,0x00,0x62,0xAF, ++0x0C,0x00,0x63,0xAF, ++0x10,0x00,0x64,0xAF, ++0x14,0x00,0x65,0xAF, ++0x18,0x00,0x66,0xAF, ++0x1C,0x00,0x67,0xAF, ++0x20,0x00,0x68,0xAF, ++0x24,0x00,0x69,0xAF, ++0x28,0x00,0x6A,0xAF, ++0x2C,0x00,0x6B,0xAF, ++0x30,0x00,0x6C,0xAF, ++0x34,0x00,0x6D,0xAF, ++0x38,0x00,0x6E,0xAF, ++0x3C,0x00,0x6F,0xAF, ++0x12,0x40,0x00,0x00, ++0x10,0x48,0x00,0x00, ++0x00,0x70,0x0A,0x40, ++0x40,0x00,0x70,0xAF, ++0x44,0x00,0x71,0xAF, ++0x48,0x00,0x72,0xAF, ++0x4C,0x00,0x73,0xAF, ++0x50,0x00,0x74,0xAF, ++0x54,0x00,0x75,0xAF, ++0x58,0x00,0x76,0xAF, ++0x5C,0x00,0x77,0xAF, ++0x60,0x00,0x78,0xAF, ++0x64,0x00,0x79,0xAF, ++0x68,0x00,0x7C,0xAF, ++0x6C,0x00,0x7D,0xAF, ++0x70,0x00,0x7E,0xAF, ++0x74,0x00,0x7F,0xAF, ++0x78,0x00,0x68,0xAF, ++0x7C,0x00,0x69,0xAF, ++0x80,0x00,0x6A,0xAF, ++0x32,0x3B,0x00,0x08, ++0x21,0x20,0x60,0x03, ++0x00,0x00,0x00,0x00, ++0x25,0xB0,0x08,0x3C, ++0x20,0x03,0x08,0x35, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x1A,0xAD, ++0x00,0x04,0x5B,0x33, ++0x0A,0x00,0x60,0x13, ++0x00,0x00,0x00,0x00, ++0x01,0x80,0x08,0x3C, ++0x3C,0xD4,0x08,0x25, ++0x00,0x00,0x00,0x00, ++0x25,0xB0,0x1B,0x3C, ++0x24,0x03,0x7B,0x37, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x68,0xAF, ++0x09,0xF8,0x00,0x01, ++0x00,0x00,0x00,0x00, ++0x00,0x08,0x5B,0x33, ++0x25,0xB0,0x08,0x3C, ++0x28,0x03,0x08,0x35, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x1B,0xAD, ++0x06,0x00,0x60,0x13, ++0x00,0x00,0x00,0x00, ++0x01,0x80,0x08,0x3C, ++0x9C,0xE8,0x08,0x25, ++0x00,0x00,0x00,0x00, ++0x09,0xF8,0x00,0x01, ++0x00,0x00,0x00,0x00, ++0x02,0x80,0x1A,0x3C, ++0xBC,0x5E,0x5A,0x27, ++0x04,0x00,0x5B,0x97, ++0x25,0xB0,0x08,0x3C, ++0x30,0x03,0x08,0x35, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x1B,0xAD, ++0x18,0x00,0x60,0x13, ++0x00,0x00,0x00,0x00, ++0x08,0xE4,0x9B,0x27, ++0x00,0x00,0x00,0x00, ++0x04,0x00,0x61,0x8F, ++0xFC,0x03,0x70,0x7B, ++0x7C,0x00,0x62,0x7B, ++0xBC,0x00,0x64,0x7B, ++0xFC,0x00,0x66,0x7B, ++0x3C,0x01,0x68,0x7B, ++0x13,0x00,0x00,0x02, ++0x11,0x00,0x20,0x02, ++0x7C,0x01,0x6A,0x7B, ++0xBC,0x01,0x6C,0x7B, ++0xFC,0x01,0x6E,0x7B, ++0x3C,0x02,0x70,0x7B, ++0x7C,0x02,0x72,0x7B, ++0xBC,0x02,0x74,0x7B, ++0xFC,0x02,0x76,0x7B, ++0x3C,0x03,0x78,0x7B, ++0x7C,0x03,0x7C,0x7B, ++0xBC,0x03,0x7E,0x7B, ++0x80,0x00,0x7B,0x8F, ++0x8F,0x3C,0x00,0x08, ++0x00,0x00,0x00,0x00, ++0x21,0xD8,0xA0,0x03, ++0x82,0xDA,0x1B,0x00, ++0x80,0xDA,0x1B,0x00, ++0x08,0x00,0x7B,0x27, ++0x08,0x00,0x5B,0xAF, ++0xFC,0xE7,0x9D,0x27, ++0x00,0x00,0x4A,0x8F, ++0x00,0x00,0x00,0x00, ++0x21,0x00,0x40,0x11, ++0x00,0x00,0x00,0x00, ++0x02,0x80,0x08,0x3C, ++0x1C,0x5E,0x08,0x25, ++0x21,0x48,0x00,0x00, ++0x21,0x58,0x00,0x00, ++0x01,0x00,0x6B,0x25, ++0x1A,0x00,0x40,0x11, ++0x24,0x70,0x4B,0x01, ++0x14,0x00,0xC0,0x11, ++0x01,0x00,0x04,0x24, ++0x00,0x00,0x00,0x00, ++0x04,0x00,0x44,0xA3, ++0x26,0x50,0x4B,0x01, ++0x00,0x00,0x4A,0xAF, ++0x80,0x80,0x09,0x00, ++0x21,0x80,0x08,0x02, ++0x00,0x00,0x10,0x8E, ++0x00,0x00,0x00,0x00, ++0x09,0xF8,0x00,0x02, ++0x00,0x00,0x00,0x00, ++0x01,0x80,0x1B,0x3C, ++0x68,0xF1,0x7B,0x27, ++0x25,0xB0,0x1A,0x3C, ++0x18,0x03,0x5A,0x27, ++0x00,0x00,0x5B,0xAF, ++0x02,0x80,0x1A,0x3C, ++0xBC,0x5E,0x5A,0x27, ++0xE1,0xFF,0x00,0x10, ++0x00,0x00,0x00,0x00, ++0x01,0x00,0x29,0x25, ++0x40,0x58,0x0B,0x00, ++0x52,0x3C,0x00,0x08, ++0x00,0x00,0x00,0x00, ++0x02,0x80,0x1B,0x3C, ++0xBC,0x5E,0x7B,0x27, ++0x21,0x60,0x00,0x00, ++0x04,0x00,0x6C,0xA7, ++0x08,0x00,0x7A,0x8F, ++0x00,0x00,0x00,0x00, ++0xF8,0xFF,0x5A,0x27, ++0x00,0x00,0x5A,0x8F, ++0x00,0x00,0x00,0x00, ++0x08,0x00,0x5A,0x27, ++0x84,0x00,0x44,0x8F, ++0x00,0x00,0x00,0x00, ++0xF9,0xFF,0x80,0x10, ++0x00,0x00,0x00,0x00, ++0x04,0x00,0x41,0x8F, ++0xFC,0x03,0x50,0x7B, ++0x7C,0x00,0x42,0x7B, ++0xBC,0x00,0x44,0x7B, ++0xFC,0x00,0x46,0x7B, ++0x3C,0x01,0x48,0x7B, ++0x13,0x00,0x00,0x02, ++0x11,0x00,0x20,0x02, ++0x7C,0x01,0x4A,0x7B, ++0xBC,0x01,0x4C,0x7B, ++0xFC,0x01,0x4E,0x7B, ++0x3C,0x02,0x50,0x7B, ++0x7C,0x02,0x52,0x7B, ++0xBC,0x02,0x54,0x7B, ++0xFC,0x02,0x56,0x7B, ++0x3C,0x03,0x58,0x7B, ++0x7C,0x03,0x5C,0x7B, ++0xBC,0x03,0x5E,0x7B, ++0x80,0x00,0x5B,0x8F, ++0x00,0x00,0x00,0x00, ++0x08,0x00,0x60,0x03, ++0x10,0x00,0x00,0x42, ++0x00,0x60,0x05,0x40, ++0x42,0x28,0x05,0x00, ++0x40,0x28,0x05,0x00, ++0x00,0x60,0x85,0x40, ++0x04,0x00,0x81,0xAC, ++0x08,0x00,0x82,0xAC, ++0x0C,0x00,0x83,0xAC, ++0x20,0x00,0x88,0xAC, ++0x24,0x00,0x89,0xAC, ++0x28,0x00,0x8A,0xAC, ++0x2C,0x00,0x8B,0xAC, ++0x30,0x00,0x8C,0xAC, ++0x34,0x00,0x8D,0xAC, ++0x38,0x00,0x8E,0xAC, ++0x3C,0x00,0x8F,0xAC, ++0x12,0x40,0x00,0x00, ++0x10,0x48,0x00,0x00, ++0x40,0x00,0x90,0xAC, ++0x44,0x00,0x91,0xAC, ++0x48,0x00,0x92,0xAC, ++0x4C,0x00,0x93,0xAC, ++0x50,0x00,0x94,0xAC, ++0x54,0x00,0x95,0xAC, ++0x58,0x00,0x96,0xAC, ++0x5C,0x00,0x97,0xAC, ++0x60,0x00,0x98,0xAC, ++0x64,0x00,0x99,0xAC, ++0x68,0x00,0x9C,0xAC, ++0x6C,0x00,0x9D,0xAC, ++0x70,0x00,0x9E,0xAC, ++0x74,0x00,0x9F,0xAC, ++0x78,0x00,0x88,0xAC, ++0x7C,0x00,0x89,0xAC, ++0x80,0x00,0x9F,0xAC, ++0xF8,0xFF,0x84,0x24, ++0x00,0x00,0x84,0x8C, ++0x00,0x00,0x00,0x00, ++0x08,0x00,0x84,0x24, ++0x84,0x00,0x86,0x8C, ++0x00,0x00,0x00,0x00, ++0xF9,0xFF,0xC0,0x10, ++0x00,0x00,0x00,0x00, ++0x21,0xD8,0x80,0x00, ++0x01,0x00,0xBA,0x34, ++0x04,0x00,0x61,0x8F, ++0xFC,0x03,0x70,0x7B, ++0x7C,0x00,0x62,0x7B, ++0xBC,0x00,0x64,0x7B, ++0xFC,0x00,0x66,0x7B, ++0x3C,0x01,0x68,0x7B, ++0x13,0x00,0x00,0x02, ++0x11,0x00,0x20,0x02, ++0x7C,0x01,0x6A,0x7B, ++0xBC,0x01,0x6C,0x7B, ++0xFC,0x01,0x6E,0x7B, ++0x3C,0x02,0x70,0x7B, ++0x7C,0x02,0x72,0x7B, ++0xBC,0x02,0x74,0x7B, ++0xFC,0x02,0x76,0x7B, ++0x3C,0x03,0x78,0x7B, ++0x7C,0x03,0x7C,0x7B, ++0xBC,0x03,0x7E,0x7B, ++0x80,0x00,0x7B,0x8F, ++0x00,0x00,0x00,0x00, ++0x08,0x00,0x60,0x03, ++0x00,0x60,0x9A,0x40, ++0x00,0x60,0x05,0x40, ++0x42,0x28,0x05,0x00, ++0x40,0x28,0x05,0x00, ++0x00,0x60,0x85,0x40, ++0x04,0x00,0x81,0xAC, ++0x08,0x00,0x82,0xAC, ++0x0C,0x00,0x83,0xAC, ++0x20,0x00,0x88,0xAC, ++0x24,0x00,0x89,0xAC, ++0x28,0x00,0x8A,0xAC, ++0x2C,0x00,0x8B,0xAC, ++0x30,0x00,0x8C,0xAC, ++0x34,0x00,0x8D,0xAC, ++0x38,0x00,0x8E,0xAC, ++0x3C,0x00,0x8F,0xAC, ++0x12,0x40,0x00,0x00, ++0x10,0x48,0x00,0x00, ++0x40,0x00,0x90,0xAC, ++0x44,0x00,0x91,0xAC, ++0x48,0x00,0x92,0xAC, ++0x4C,0x00,0x93,0xAC, ++0x50,0x00,0x94,0xAC, ++0x54,0x00,0x94,0xAC, ++0x58,0x00,0x96,0xAC, ++0x5C,0x00,0x96,0xAC, ++0x60,0x00,0x98,0xAC, ++0x64,0x00,0x99,0xAC, ++0x68,0x00,0x9C,0xAC, ++0x6C,0x00,0x9D,0xAC, ++0x70,0x00,0x9E,0xAC, ++0x78,0x00,0x88,0xAC, ++0x7C,0x00,0x89,0xAC, ++0x80,0x00,0x9F,0xAC, ++0x84,0x00,0x80,0xAC, ++0xF8,0xFF,0x84,0x24, ++0x00,0x00,0x84,0x8C, ++0x00,0x00,0x00,0x00, ++0x08,0x00,0x84,0x24, ++0x84,0x00,0x86,0x8C, ++0xFA,0xFF,0xC0,0x10, ++0x00,0x00,0x00,0x00, ++0x21,0xD8,0x80,0x00, ++0x01,0x00,0xBA,0x24, ++0x04,0x00,0x61,0x8F, ++0xFC,0x03,0x70,0x7B, ++0x7C,0x00,0x62,0x7B, ++0xBC,0x00,0x64,0x7B, ++0xFC,0x00,0x66,0x7B, ++0x3C,0x01,0x68,0x7B, ++0x13,0x00,0x00,0x02, ++0x11,0x00,0x20,0x02, ++0x7C,0x01,0x6A,0x7B, ++0xBC,0x01,0x6C,0x7B, ++0xFC,0x01,0x6E,0x7B, ++0x3C,0x02,0x70,0x7B, ++0x7C,0x02,0x72,0x7B, ++0xBC,0x02,0x74,0x7B, ++0xFC,0x02,0x76,0x7B, ++0x3C,0x03,0x78,0x7B, ++0x7C,0x03,0x7C,0x7B, ++0xBC,0x03,0x7E,0x7B, ++0x80,0x00,0x7B,0x8F, ++0x08,0x00,0x60,0x03, ++0x00,0x60,0x9A,0x40, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x83,0x4E,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x01,0x80,0x1B,0x3C, ++0x00,0x00,0x7B,0x27, ++0x25,0xB0,0x1A,0x3C, ++0x18,0x03,0x5A,0x27, ++0x00,0x00,0x5B,0xAF, ++0x00,0x00,0x05,0x24, ++0x03,0x00,0xA4,0x24, ++0x00,0xA0,0x80,0x40, ++0x00,0xA0,0x84,0x40, ++0x01,0x80,0x04,0x3C, ++0x40,0x00,0x84,0x24, ++0x08,0x00,0x80,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x01,0x80,0x1B,0x3C, ++0x40,0x00,0x7B,0x27, ++0x25,0xB0,0x1A,0x3C, ++0x18,0x03,0x5A,0x27, ++0x00,0x00,0x5B,0xAF, ++0x02,0x80,0x1A,0x3C, ++0x00,0x00,0x5A,0x27, ++0xFC,0x03,0x5D,0x27, ++0x02,0x80,0x1C,0x3C, ++0x00,0x1C,0x9C,0x27, ++0x00,0xF0,0x08,0x3C, ++0x00,0x0C,0x08,0x35, ++0x00,0x60,0x88,0x40, ++0x02,0x80,0x04,0x3C, ++0x00,0x00,0x84,0x24, ++0xFF,0x7F,0x05,0x3C, ++0xFF,0xFF,0xA5,0x34, ++0x24,0x20,0x85,0x00, ++0x00,0x20,0x84,0x4C, ++0xFF,0xFF,0x05,0x34, ++0x21,0x28,0xA4,0x00, ++0x00,0x28,0x85,0x4C, ++0x02,0x80,0x08,0x3C, ++0x00,0x00,0x08,0x25, ++0x00,0x00,0x00,0xAD, ++0x03,0x80,0x09,0x3C, ++0xFC,0xCC,0x29,0x25, ++0x04,0x00,0x08,0x25, ++0xFE,0xFF,0x09,0x15, ++0x00,0x00,0x00,0xAD, ++0x00,0x80,0x04,0x3C, ++0x00,0x00,0x84,0x24, ++0xFF,0x7F,0x05,0x3C, ++0xFF,0xFF,0xA5,0x34, ++0x24,0x20,0x85,0x00, ++0x00,0x00,0x84,0x4C, ++0xFF,0xFF,0x06,0x34, ++0x21,0x30,0xC4,0x00, ++0x24,0x30,0xC5,0x00, ++0x00,0x08,0x86,0x4C, ++0x00,0xA0,0x04,0x40, ++0x10,0x00,0x84,0x34, ++0x00,0xA0,0x84,0x40, ++0x01,0x80,0x1B,0x3C, ++0xEC,0x00,0x7B,0x27, ++0x25,0xB0,0x1A,0x3C, ++0x18,0x03,0x5A,0x27, ++0x00,0x00,0x5B,0xAF, ++0x00,0x00,0x00,0x00, ++0x25,0xB0,0x04,0x3C, ++0x44,0x00,0x84,0x34, ++0x00,0x00,0x85,0x84, ++0x20,0x00,0x06,0x24, ++0x25,0x28,0xA6,0x00, ++0x00,0x00,0x85,0xA4, ++0x01,0x80,0x1B,0x3C, ++0x1C,0x01,0x7B,0x27, ++0x25,0xB0,0x1A,0x3C, ++0x18,0x03,0x5A,0x27, ++0x00,0x00,0x5B,0xAF, ++0x25,0xB0,0x04,0x3C, ++0x44,0x00,0x84,0x34, ++0x00,0x00,0x85,0x8C, ++0x00,0x00,0x00,0x00, ++0x10,0x00,0xA5,0x30, ++0xFC,0xFF,0xA0,0x10, ++0x00,0x00,0x00,0x00, ++0xFF,0x1F,0x07,0x3C, ++0xFF,0xFF,0xE7,0x34, ++0x02,0x80,0x05,0x3C, ++0xD8,0x5D,0xA5,0x24, ++0xFF,0xFF,0xA5,0x30, ++0x40,0xB0,0x04,0x3C, ++0x25,0x28,0xA4,0x00, ++0x24,0x28,0xA7,0x00, ++0x21,0x30,0x00,0x00, ++0x43,0xB0,0x02,0x3C, ++0x00,0x80,0x04,0x3C, ++0x40,0x00,0x84,0x34, ++0x00,0x00,0x45,0xAC, ++0x04,0x00,0x46,0xAC, ++0x08,0x00,0x44,0xAC, ++0xEA,0x65,0x00,0x08, ++0x00,0x00,0x00,0x00, ++0x08,0x00,0xE0,0x03, ++0x00,0x00,0x00,0x00, ++0x09,0x00,0x02,0x24, ++0xFF,0xFF,0x42,0x24, ++0xFF,0xFF,0x41,0x04, ++0xFF,0xFF,0x42,0x24, ++0x08,0x00,0xE0,0x03, ++0x01,0x00,0x42,0x24, ++0x00,0x60,0x02,0x40, ++0x01,0x00,0x41,0x34, ++0x01,0x00,0x21,0x38, ++0x00,0x60,0x81,0x40, ++0x08,0x00,0xE0,0x03, ++0x00,0x00,0x82,0xAC, ++0x00,0x00,0x82,0x8C, ++0x00,0x00,0x00,0x00, ++0x21,0x18,0x40,0x00, ++0x00,0x60,0x83,0x40, ++0x08,0x00,0xE0,0x03, ++0x00,0x00,0x82,0xAC, ++0x00,0x60,0x01,0x40, ++0x01,0x00,0x21,0x34, ++0x00,0x60,0x81,0x40, ++0x08,0x00,0xE0,0x03, ++0x00,0x00,0x00,0x00, ++0x00,0x60,0x01,0x40, ++0x01,0x00,0x21,0x34, ++0x01,0x00,0x21,0x38, ++0x00,0x60,0x81,0x40, ++0x08,0x00,0xE0,0x03, ++0x00,0x00,0x00,0x00, ++0x01,0x80,0x03,0x3C, ++0x25,0xB0,0x02,0x3C, ++0x0C,0x02,0x63,0x24, ++0x18,0x03,0x42,0x34, ++0x00,0x00,0x43,0xAC, ++0x04,0x00,0x85,0x8C, ++0x00,0xA0,0x03,0x3C, ++0x01,0x00,0x02,0x24, ++0x25,0x28,0xA3,0x00, ++0x00,0x00,0xA4,0x8C, ++0x08,0x00,0xE0,0x03, ++0x00,0x00,0x00,0x00, ++0x01,0x80,0x03,0x3C, ++0x25,0xB0,0x02,0x3C, ++0x3C,0x02,0x63,0x24, ++0x18,0x03,0x42,0x34, ++0x00,0x00,0x43,0xAC, ++0x04,0x00,0x82,0x8C, ++0x02,0x00,0x83,0x94, ++0x00,0xA0,0x07,0x3C, ++0x25,0x28,0x47,0x00, ++0x00,0x00,0xA2,0x8C, ++0x10,0x00,0x02,0x24, ++0x13,0x00,0x62,0x10, ++0x11,0x00,0x66,0x28, ++0x06,0x00,0xC0,0x10, ++0x20,0x00,0x02,0x24, ++0x08,0x00,0x02,0x24, ++0x17,0x00,0x62,0x10, ++0x00,0x00,0x00,0x00, ++0x08,0x00,0xE0,0x03, ++0x01,0x00,0x02,0x24, ++0xFD,0xFF,0x62,0x14, ++0x00,0x00,0x00,0x00, ++0x08,0x00,0x83,0x8C, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0xA3,0xAC, ++0x04,0x00,0x82,0x8C, ++0x00,0x00,0x00,0x00, ++0x25,0x10,0x47,0x00, ++0x00,0x00,0x42,0x8C, ++0x08,0x00,0xE0,0x03, ++0x01,0x00,0x02,0x24, ++0x08,0x00,0x82,0x8C, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0xA2,0xA4, ++0x04,0x00,0x83,0x8C, ++0x00,0x00,0x00,0x00, ++0x25,0x18,0x67,0x00, ++0x00,0x00,0x62,0x94, ++0x08,0x00,0xE0,0x03, ++0x01,0x00,0x02,0x24, ++0x08,0x00,0x82,0x8C, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0xA2,0xA0, ++0x04,0x00,0x83,0x8C, ++0x00,0x00,0x00,0x00, ++0x25,0x18,0x67,0x00, ++0x00,0x00,0x62,0x90, ++0x08,0x00,0xE0,0x03, ++0x01,0x00,0x02,0x24, ++0x02,0x80,0x02,0x3C, ++0x30,0x1F,0x47,0x24, ++0x30,0x37,0xE3,0x90, ++0xFF,0xFF,0xA5,0x30, ++0x09,0x00,0xA3,0x10, ++0x21,0x20,0xC0,0x00, ++0xA0,0x37,0xE2,0x8C, ++0x00,0x00,0x00,0x00, ++0x08,0x00,0xC2,0xAC, ++0xAA,0x37,0xE3,0x94, ++0x0E,0x00,0x02,0x24, ++0x14,0x00,0xC2,0xAC, ++0x30,0x09,0x00,0x08, ++0x0C,0x00,0xC3,0xAC, ++0x08,0x00,0xE0,0x03, ++0x00,0x00,0x00,0x00, ++0xE0,0xFF,0xBD,0x27, ++0x14,0x00,0xB1,0xAF, ++0x02,0x80,0x11,0x3C, ++0x1C,0x00,0xBF,0xAF, ++0x18,0x00,0xB2,0xAF, ++0x10,0x00,0xB0,0xAF, ++0x30,0x1F,0x31,0x26, ++0x88,0x37,0x30,0x96, ++0x02,0x80,0x02,0x3C, ++0x01,0x80,0x03,0x3C, ++0x25,0x80,0x02,0x02, ++0x25,0xB0,0x02,0x3C, ++0x40,0x03,0x63,0x24, ++0x18,0x03,0x42,0x34, ++0x60,0x00,0x04,0x26, ++0x80,0x00,0x05,0x26, ++0x00,0x00,0x43,0xAC, ++0x5F,0x1E,0x00,0x0C, ++0x03,0x00,0x06,0x24, ++0x21,0x20,0x00,0x02, ++0x21,0x28,0x00,0x00, ++0x08,0x52,0x00,0x0C, ++0x08,0x00,0x06,0x24, ++0x88,0x37,0x22,0x8E, ++0x0C,0x00,0x03,0x24, ++0x0C,0x00,0x43,0xAE, ++0x08,0x00,0x42,0xAE, ++0x12,0x00,0x02,0x24, ++0x14,0x00,0x42,0xAE, ++0x21,0x20,0x40,0x02, ++0x1C,0x00,0xBF,0x8F, ++0x18,0x00,0xB2,0x8F, ++0x14,0x00,0xB1,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x30,0x09,0x00,0x08, ++0x20,0x00,0xBD,0x27, ++0x08,0x00,0xE0,0x03, ++0x00,0x00,0x00,0x00, ++0x08,0x00,0xE0,0x03, ++0x21,0x10,0x00,0x00, ++0x08,0x00,0xE0,0x03, ++0x21,0x10,0x00,0x00, ++0x08,0x00,0xE0,0x03, ++0x21,0x10,0x00,0x00, ++0xE0,0xFF,0xBD,0x27, ++0x18,0x00,0xB2,0xAF, ++0x1C,0x00,0xBF,0xAF, ++0x14,0x00,0xB1,0xAF, ++0x10,0x00,0xB0,0xAF, ++0x21,0x30,0x80,0x00, ++0x21,0x90,0x00,0x00, ++0x00,0x60,0x11,0x40, ++0x01,0x00,0x21,0x36, ++0x01,0x00,0x21,0x38, ++0x00,0x60,0x81,0x40, ++0x0D,0x00,0x83,0x90, ++0x00,0x00,0x00,0x00, ++0x02,0x00,0x60,0x14, ++0x02,0x80,0x02,0x3C, ++0x01,0x00,0x03,0x24, ++0xF8,0x5E,0x43,0xA0, ++0x0C,0x00,0xC2,0x90, ++0x02,0x80,0x05,0x3C, ++0x0D,0x5F,0xA2,0xA0, ++0x00,0x00,0xC4,0x90, ++0x05,0x00,0x02,0x24, ++0xFF,0x00,0x83,0x30, ++0x41,0x00,0x62,0x10, ++0x00,0x00,0x00,0x00, ++0x03,0x00,0x02,0x24, ++0x31,0x00,0x62,0x10, ++0xFF,0x00,0x84,0x30, ++0x09,0x00,0x82,0x2C, ++0x25,0x00,0x40,0x10, ++0x02,0x80,0x10,0x3C, ++0xF4,0x5E,0x02,0x92, ++0x00,0x00,0x00,0x00, ++0xFF,0x00,0x42,0x30, ++0x21,0x00,0x82,0x10, ++0x00,0x00,0x00,0x00, ++0xB6,0x60,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0xF4,0x5E,0x02,0x92, ++0x00,0x00,0x00,0x00, ++0x34,0x00,0x40,0x10, ++0x02,0x80,0x03,0x3C, ++0xE0,0x3A,0x62,0x94, ++0x00,0x00,0x00,0x00, ++0x00,0x01,0x42,0x30, ++0x51,0x00,0x40,0x10, ++0x02,0x80,0x02,0x3C, ++0x02,0x80,0x03,0x3C, ++0x15,0x5F,0x62,0x90, ++0x00,0x00,0x00,0x00, ++0x11,0x00,0x40,0x14, ++0x00,0x00,0x00,0x00, ++0x15,0x5F,0x62,0x90, ++0x00,0x00,0x00,0x00, ++0x01,0x00,0x42,0x24, ++0x15,0x5F,0x62,0xA0, ++0x02,0x80,0x03,0x3C, ++0xF6,0x5E,0x62,0x90, ++0x00,0x00,0x00,0x00, ++0x0F,0x00,0x42,0x30, ++0x04,0x00,0x42,0x28, ++0x06,0x00,0x40,0x10, ++0x04,0x00,0x04,0x24, ++0x64,0x31,0x00,0x0C, ++0x01,0x00,0x05,0x24, ++0x40,0x41,0x00,0x08, ++0x00,0x00,0x00,0x00, ++0x04,0x00,0x12,0x24, ++0x00,0x60,0x91,0x40, ++0x21,0x10,0x40,0x02, ++0x1C,0x00,0xBF,0x8F, ++0x18,0x00,0xB2,0x8F, ++0x14,0x00,0xB1,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x08,0x00,0xE0,0x03, ++0x20,0x00,0xBD,0x27, ++0x0B,0x00,0xC2,0x90, ++0x00,0x00,0x00,0x00, ++0x03,0x00,0x40,0x14, ++0x02,0x80,0x03,0x3C, ++0x02,0x80,0x03,0x3C, ++0x01,0x00,0x02,0x24, ++0x10,0x5F,0x62,0xA0, ++0x10,0x5F,0x63,0x90, ++0x02,0x80,0x02,0x3C, ++0x11,0x5F,0x43,0xA0, ++0x00,0x00,0xC4,0x90, ++0x18,0x41,0x00,0x08, ++0xFF,0x00,0x84,0x30, ++0x0D,0x5F,0xA0,0xA0, ++0x00,0x00,0xC4,0x90, ++0x15,0x41,0x00,0x08, ++0xFF,0x00,0x83,0x30, ++0x42,0xB0,0x06,0x3C, ++0x00,0x00,0xC3,0x90, ++0xEF,0xFF,0x02,0x24, ++0x03,0x00,0xC7,0x34, ++0x24,0x18,0x62,0x00, ++0x40,0x00,0x02,0x24, ++0x00,0x00,0xC3,0xA0, ++0x0C,0x00,0x04,0x24, ++0x00,0x00,0xE2,0xA0, ++0x64,0x31,0x00,0x0C, ++0x01,0x00,0x05,0x24, ++0x02,0x80,0x03,0x3C, ++0xDE,0x5D,0x62,0x90, ++0x00,0x00,0x00,0x00, ++0x02,0x00,0x42,0x30, ++0x15,0x00,0x40,0x14, ++0x00,0x00,0x00,0x00, ++0x00,0x08,0x04,0x24, ++0x00,0x02,0x05,0x3C, ++0xA9,0x45,0x00,0x0C, ++0x01,0x00,0x06,0x24, ++0x02,0x80,0x02,0x3C, ++0x30,0x1F,0x42,0x24, ++0x2A,0x1C,0x43,0x90, ++0x00,0x00,0x00,0x00, ++0xCD,0xFF,0x60,0x10, ++0x00,0x00,0x00,0x00, ++0x50,0x39,0x44,0x94, ++0x2A,0x1C,0x40,0xA0, ++0x00,0xC0,0x84,0x24, ++0xC2,0x34,0x00,0x0C, ++0xFF,0xFF,0x84,0x30, ++0x40,0x41,0x00,0x08, ++0x00,0x00,0x00,0x00, ++0x15,0x5F,0x40,0xA0, ++0x40,0x41,0x00,0x08, ++0x00,0x00,0x00,0x00, ++0x9B,0x30,0x00,0x0C, ++0x01,0x00,0x04,0x24, ++0x6B,0x41,0x00,0x08, ++0x00,0x08,0x04,0x24, ++0x08,0x00,0xE0,0x03, ++0x21,0x10,0x00,0x00, ++0xE0,0xFF,0xBD,0x27, ++0x14,0x00,0xB1,0xAF, ++0x02,0x80,0x11,0x3C, ++0x10,0x00,0xB0,0xAF, ++0x30,0x1F,0x30,0x26, ++0xB0,0x1B,0x07,0x96, ++0x18,0x00,0xBF,0xAF, ++0xFF,0xFF,0xE3,0x30, ++0x00,0x01,0x62,0x30, ++0x0E,0x00,0x40,0x10, ++0x01,0x00,0x66,0x30, ++0x02,0x80,0x04,0x3C, ++0x88,0x58,0x84,0x24, ++0x03,0x00,0x05,0x24, ++0x17,0x00,0xC0,0x14, ++0x04,0x00,0x62,0x30, ++0x02,0x00,0x40,0x10, ++0xFB,0xF6,0xE3,0x30, ++0xB0,0x1B,0x03,0xA6, ++0xA3,0x51,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x25,0xB0,0x02,0x3C, ++0x4C,0x00,0x42,0x34, ++0x00,0x00,0x40,0xA0, ++0x21,0x20,0x00,0x00, ++0x12,0x0D,0x00,0x0C, ++0x21,0x28,0x00,0x00, ++0x30,0x1F,0x23,0x26, ++0x18,0x00,0xBF,0x8F, ++0x14,0x00,0xB1,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x21,0x10,0x00,0x00, ++0x20,0x00,0xBD,0x27, ++0x10,0x3E,0x60,0xAC, ++0xEC,0x38,0x60,0xAC, ++0x08,0x39,0x60,0xAC, ++0x08,0x00,0xE0,0x03, ++0x50,0x3E,0x60,0xAC, ++0x6C,0x4C,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0xB0,0x1B,0x02,0x96, ++0x00,0x00,0x00,0x00, ++0xFE,0xFE,0x42,0x30, ++0xA3,0x51,0x00,0x0C, ++0xB0,0x1B,0x02,0xA6, ++0x25,0xB0,0x02,0x3C, ++0x4C,0x00,0x42,0x34, ++0x00,0x00,0x40,0xA0, ++0x9D,0x41,0x00,0x08, ++0x21,0x20,0x00,0x00, ++0x08,0x00,0xE0,0x03, ++0x21,0x10,0x00,0x00, ++0x08,0x00,0xE0,0x03, ++0x21,0x10,0x00,0x00, ++0xE8,0xFF,0xBD,0x27, ++0x10,0x00,0xBF,0xAF, ++0x01,0x00,0x83,0x90, ++0x02,0x80,0x02,0x3C, ++0x21,0x38,0x80,0x00, ++0xB0,0x5C,0x43,0xAC, ++0x01,0x00,0x84,0x90, ++0x00,0x00,0xE2,0x90, ++0x02,0x80,0x06,0x3C, ++0xFF,0x00,0x85,0x30, ++0x80,0x10,0x02,0x00, ++0x25,0x28,0xA2,0x00, ++0xE8,0xDD,0xC6,0x24, ++0xFF,0x00,0x84,0x30, ++0x00,0x80,0xA5,0x34, ++0x4E,0x23,0x00,0x0C, ++0x03,0x00,0xE7,0x24, ++0x10,0x00,0xBF,0x8F, ++0x21,0x10,0x00,0x00, ++0x08,0x00,0xE0,0x03, ++0x18,0x00,0xBD,0x27, ++0xE0,0xFF,0xBD,0x27, ++0x18,0x00,0xB0,0xAF, ++0x02,0x80,0x03,0x3C, ++0x1C,0x00,0xBF,0xAF, ++0xE0,0x3A,0x62,0x94, ++0x00,0x00,0x00,0x00, ++0x01,0x00,0x43,0x30, ++0x00,0x01,0x42,0x30, ++0x04,0x00,0x40,0x10, ++0x21,0x80,0x80,0x00, ++0x02,0x80,0x04,0x3C, ++0x06,0x00,0x60,0x14, ++0xE0,0xD7,0x84,0x24, ++0x1C,0x00,0xBF,0x8F, ++0x18,0x00,0xB0,0x8F, ++0x21,0x10,0x00,0x00, ++0x08,0x00,0xE0,0x03, ++0x20,0x00,0xBD,0x27, ++0x2F,0x55,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x06,0x00,0x07,0x92, ++0x07,0x00,0x02,0x26, ++0x21,0x20,0x00,0x02, ++0x80,0x38,0x07,0x00, ++0x00,0x80,0xE7,0x34, ++0x05,0x00,0x05,0x24, ++0x21,0x30,0x00,0x00, ++0x1E,0x51,0x00,0x0C, ++0x10,0x00,0xA2,0xAF, ++0x1C,0x00,0xBF,0x8F, ++0x18,0x00,0xB0,0x8F, ++0x21,0x10,0x00,0x00, ++0x08,0x00,0xE0,0x03, ++0x20,0x00,0xBD,0x27, ++0x08,0x00,0xE0,0x03, ++0x21,0x10,0x00,0x00, ++0x08,0x00,0xE0,0x03, ++0x21,0x10,0x00,0x00, ++0x08,0x00,0xE0,0x03, ++0x21,0x10,0x00,0x00, ++0x08,0x00,0xE0,0x03, ++0x21,0x10,0x00,0x00, ++0x08,0x00,0xE0,0x03, ++0x21,0x10,0x00,0x00, ++0x08,0x00,0xE0,0x03, ++0x21,0x10,0x00,0x00, ++0x08,0x00,0xE0,0x03, ++0x21,0x10,0x00,0x00, ++0x08,0x00,0xE0,0x03, ++0x21,0x10,0x00,0x00, ++0x08,0x00,0xE0,0x03, ++0x01,0x00,0x02,0x24, ++0x08,0x00,0xE0,0x03, ++0x21,0x10,0x00,0x00, ++0x08,0x00,0xE0,0x03, ++0x01,0x00,0x02,0x24, ++0x08,0x00,0xE0,0x03, ++0x21,0x10,0x00,0x00, ++0x08,0x00,0xE0,0x03, ++0x21,0x10,0x00,0x00, ++0x08,0x00,0xE0,0x03, ++0x01,0x00,0x02,0x24, ++0x08,0x00,0xE0,0x03, ++0x21,0x10,0x00,0x00, ++0x08,0x00,0xE0,0x03, ++0x01,0x00,0x02,0x24, ++0x08,0x00,0xE0,0x03, ++0x21,0x10,0x00,0x00, ++0x08,0x00,0xE0,0x03, ++0x00,0x00,0x00,0x00, ++0x08,0x00,0xE0,0x03, ++0x01,0x00,0x02,0x24, ++0x08,0x00,0xE0,0x03, ++0x01,0x00,0x02,0x24, ++0x08,0x00,0xE0,0x03, ++0x21,0x10,0x00,0x00, ++0x08,0x00,0xE0,0x03, ++0x01,0x00,0x02,0x24, ++0x08,0x00,0xE0,0x03, ++0x21,0x10,0x00,0x00, ++0x08,0x00,0xE0,0x03, ++0x21,0x10,0x00,0x00, ++0x08,0x00,0xE0,0x03, ++0x21,0x10,0x00,0x00, ++0x08,0x00,0xE0,0x03, ++0x21,0x10,0x00,0x00, ++0x08,0x00,0xE0,0x03, ++0x21,0x10,0x00,0x00, ++0x08,0x00,0xE0,0x03, ++0x21,0x10,0x00,0x00, ++0x08,0x00,0xE0,0x03, ++0x21,0x10,0x00,0x00, ++0x08,0x00,0xE0,0x03, ++0x21,0x10,0x00,0x00, ++0xE8,0xFF,0xBD,0x27, ++0x02,0x80,0x02,0x3C, ++0x10,0x00,0xB0,0xAF, ++0x14,0x00,0xBF,0xAF, ++0x30,0x1F,0x45,0x24, ++0x50,0x3E,0xA3,0x8C, ++0x00,0x00,0x00,0x00, ++0x06,0x00,0x60,0x14, ++0x21,0x80,0x80,0x00, ++0x14,0x00,0xBF,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x21,0x10,0x00,0x00, ++0x08,0x00,0xE0,0x03, ++0x18,0x00,0xBD,0x27, ++0x4C,0x3E,0xA2,0x90, ++0x00,0x00,0x00,0x00, ++0x21,0x10,0x45,0x00, ++0x44,0x3E,0x40,0xA0, ++0x00,0x00,0x84,0x8C, ++0x6D,0x1D,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x06,0x8E, ++0x03,0x00,0x04,0x24, ++0x90,0x14,0x00,0x0C, ++0x21,0x28,0x00,0x00, ++0x14,0x00,0xBF,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x21,0x10,0x00,0x00, ++0x08,0x00,0xE0,0x03, ++0x18,0x00,0xBD,0x27, ++0x00,0x00,0x84,0x90, ++0x4F,0x0C,0x00,0x08, ++0x00,0x00,0x00,0x00, ++0xE0,0xFF,0xBD,0x27, ++0x18,0x00,0xBF,0xAF, ++0x14,0x00,0xB1,0xAF, ++0x10,0x00,0xB0,0xAF, ++0x00,0x00,0x86,0x90, ++0x21,0x80,0x80,0x00, ++0x00,0x7F,0x05,0x24, ++0xA9,0x45,0x00,0x0C, ++0x08,0x0E,0x04,0x24, ++0x00,0x00,0x05,0x92, ++0x7F,0x7F,0x11,0x3C, ++0x00,0x0E,0x04,0x24, ++0x00,0x14,0x05,0x00, ++0x00,0x86,0x05,0x00, ++0x00,0x1A,0x05,0x00, ++0x25,0x80,0x02,0x02, ++0x25,0x80,0x03,0x02, ++0x25,0x80,0x05,0x02, ++0x21,0x30,0x00,0x02, ++0xA9,0x45,0x00,0x0C, ++0x7F,0x7F,0x25,0x36, ++0x7F,0x7F,0x25,0x36, ++0x21,0x30,0x00,0x02, ++0xA9,0x45,0x00,0x0C, ++0x04,0x0E,0x04,0x24, ++0x7F,0x7F,0x25,0x36, ++0x21,0x30,0x00,0x02, ++0xA9,0x45,0x00,0x0C, ++0x10,0x0E,0x04,0x24, ++0x7F,0x7F,0x25,0x36, ++0x21,0x30,0x00,0x02, ++0xA9,0x45,0x00,0x0C, ++0x14,0x0E,0x04,0x24, ++0x7F,0x7F,0x25,0x36, ++0x21,0x30,0x00,0x02, ++0xA9,0x45,0x00,0x0C, ++0x18,0x0E,0x04,0x24, ++0x7F,0x7F,0x25,0x36, ++0x21,0x30,0x00,0x02, ++0x18,0x00,0xBF,0x8F, ++0x14,0x00,0xB1,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x1C,0x0E,0x04,0x24, ++0xA9,0x45,0x00,0x08, ++0x20,0x00,0xBD,0x27, ++0xD0,0xFF,0xBD,0x27, ++0x24,0x00,0xB3,0xAF, ++0x20,0x00,0xB2,0xAF, ++0x1C,0x00,0xB1,0xAF, ++0x18,0x00,0xB0,0xAF, ++0x28,0x00,0xBF,0xAF, ++0x00,0x00,0x85,0x94, ++0x02,0x00,0x02,0x24, ++0x21,0x98,0x80,0x00, ++0x10,0x00,0xA0,0xA3, ++0x21,0x80,0x00,0x00, ++0x21,0x30,0x00,0x00, ++0x21,0x88,0x00,0x00, ++0x66,0x00,0xA2,0x10, ++0x10,0x00,0xB2,0x27, ++0x03,0x00,0xA2,0x28, ++0x26,0x00,0x40,0x14, ++0x01,0x00,0x02,0x24, ++0x03,0x00,0x02,0x24, ++0x75,0x00,0xA2,0x10, ++0x24,0x08,0x04,0x24, ++0x0C,0x09,0x04,0x24, ++0xA9,0x45,0x00,0x0C, ++0xFF,0xFF,0x05,0x24, ++0x04,0x08,0x04,0x24, ++0x21,0x30,0x00,0x02, ++0xA9,0x45,0x00,0x0C, ++0x0F,0x00,0x05,0x24, ++0x02,0x00,0x64,0x96, ++0x02,0x00,0x02,0x24, ++0x35,0x00,0x82,0x10, ++0x03,0x00,0x82,0x28, ++0x4B,0x00,0x40,0x10, ++0x03,0x00,0x02,0x24, ++0x01,0x00,0x02,0x24, ++0x60,0x00,0x82,0x10, ++0x21,0x30,0x20,0x02, ++0x04,0x0C,0x04,0x24, ++0xA9,0x45,0x00,0x0C, ++0x0F,0x00,0x05,0x24, ++0x21,0x30,0x20,0x02, ++0x04,0x0D,0x04,0x24, ++0xA9,0x45,0x00,0x0C, ++0x0F,0x00,0x05,0x24, ++0x10,0x00,0xA6,0x93, ++0x04,0x0A,0x04,0x24, ++0xA9,0x45,0x00,0x0C, ++0x00,0xFF,0x05,0x3C, ++0x28,0x00,0xBF,0x8F, ++0x24,0x00,0xB3,0x8F, ++0x20,0x00,0xB2,0x8F, ++0x1C,0x00,0xB1,0x8F, ++0x18,0x00,0xB0,0x8F, ++0x08,0x00,0xE0,0x03, ++0x30,0x00,0xBD,0x27, ++0xDE,0xFF,0xA2,0x14, ++0x0C,0x09,0x04,0x24, ++0x24,0x08,0x04,0x24, ++0x0E,0x00,0x05,0x24, ++0xA9,0x45,0x00,0x0C, ++0x02,0x00,0x06,0x24, ++0x2C,0x08,0x04,0x24, ++0x01,0x00,0x06,0x24, ++0xA9,0x45,0x00,0x0C, ++0x0E,0x00,0x05,0x24, ++0x10,0x00,0xA2,0x93, ++0x80,0xFF,0x03,0x24, ++0x11,0x11,0x04,0x3C, ++0x0F,0x00,0x42,0x30, ++0x25,0x10,0x43,0x00, ++0x11,0x11,0x86,0x34, ++0x03,0x00,0x10,0x24, ++0x10,0x00,0xA2,0xA3, ++0x0C,0x09,0x04,0x24, ++0xA9,0x45,0x00,0x0C, ++0xFF,0xFF,0x05,0x24, ++0x04,0x08,0x04,0x24, ++0x21,0x30,0x00,0x02, ++0xA9,0x45,0x00,0x0C, ++0x0F,0x00,0x05,0x24, ++0x02,0x00,0x64,0x96, ++0x02,0x00,0x02,0x24, ++0xCD,0xFF,0x82,0x14, ++0x03,0x00,0x82,0x28, ++0x00,0x00,0x42,0x92, ++0x02,0x00,0x11,0x24, ++0xF5,0x00,0x42,0x30, ++0x05,0x00,0x42,0x34, ++0x00,0x00,0x42,0xA2, ++0x21,0x30,0x20,0x02, ++0x04,0x0C,0x04,0x24, ++0xA9,0x45,0x00,0x0C, ++0x0F,0x00,0x05,0x24, ++0x21,0x30,0x20,0x02, ++0x04,0x0D,0x04,0x24, ++0xA9,0x45,0x00,0x0C, ++0x0F,0x00,0x05,0x24, ++0x10,0x00,0xA6,0x93, ++0x04,0x0A,0x04,0x24, ++0xA9,0x45,0x00,0x0C, ++0x00,0xFF,0x05,0x3C, ++0x28,0x00,0xBF,0x8F, ++0x24,0x00,0xB3,0x8F, ++0x20,0x00,0xB2,0x8F, ++0x1C,0x00,0xB1,0x8F, ++0x18,0x00,0xB0,0x8F, ++0x08,0x00,0xE0,0x03, ++0x30,0x00,0xBD,0x27, ++0xB8,0xFF,0x82,0x14, ++0x21,0x30,0x20,0x02, ++0x00,0x00,0x42,0x92, ++0x03,0x00,0x11,0x24, ++0xF0,0x00,0x42,0x30, ++0x01,0x00,0x42,0x34, ++0xD4,0x42,0x00,0x08, ++0x00,0x00,0x42,0xA2, ++0x24,0x08,0x04,0x24, ++0x0E,0x00,0x05,0x24, ++0xA9,0x45,0x00,0x0C, ++0x01,0x00,0x06,0x24, ++0x02,0x00,0x06,0x24, ++0x2C,0x08,0x04,0x24, ++0xA9,0x45,0x00,0x0C, ++0x0E,0x00,0x05,0x24, ++0x10,0x00,0xA2,0x93, ++0x22,0x22,0x03,0x3C, ++0x22,0x22,0x66,0x34, ++0x0F,0x00,0x42,0x30, ++0x40,0x00,0x42,0x34, ++0x03,0x00,0x10,0x24, ++0xC4,0x42,0x00,0x08, ++0x10,0x00,0xA2,0xA3, ++0x00,0x00,0x42,0x92, ++0x01,0x00,0x11,0x24, ++0xF0,0x00,0x42,0x30, ++0xD4,0x42,0x00,0x08, ++0x00,0x00,0x42,0xA2, ++0x0E,0x00,0x05,0x24, ++0xA9,0x45,0x00,0x0C, ++0x02,0x00,0x06,0x24, ++0x02,0x00,0x06,0x24, ++0x2C,0x08,0x04,0x24, ++0xA9,0x45,0x00,0x0C, ++0x0E,0x00,0x05,0x24, ++0x10,0x00,0xA2,0x93, ++0xC0,0xFF,0x03,0x24, ++0x03,0x00,0x10,0x24, ++0x0F,0x00,0x42,0x30, ++0x25,0x10,0x43,0x00, ++0x32,0x03,0x03,0x3C, ++0x33,0x13,0x66,0x34, ++0x90,0x42,0x00,0x08, ++0x10,0x00,0xA2,0xA3, ++0x00,0x00,0x86,0x8C, ++0x00,0x0F,0x05,0x3C, ++0xA9,0x45,0x00,0x08, ++0x80,0x08,0x04,0x24, ++0xE8,0xFF,0xBD,0x27, ++0x10,0x00,0xB0,0xAF, ++0x21,0x80,0x80,0x00, ++0x02,0x80,0x04,0x3C, ++0x14,0x00,0xBF,0xAF, ++0x2F,0x55,0x00,0x0C, ++0xF0,0xD7,0x84,0x24, ++0x00,0x00,0x02,0x92, ++0x00,0x0D,0x04,0x24, ++0x00,0x10,0x05,0x3C, ++0x21,0x00,0x40,0x10, ++0x21,0x30,0x00,0x00, ++0x00,0x08,0x04,0x24, ++0xCB,0x45,0x00,0x0C, ++0x00,0x02,0x05,0x3C, ++0x00,0x08,0x04,0x24, ++0x00,0x02,0x05,0x3C, ++0x32,0x00,0x40,0x10, ++0x01,0x00,0x06,0x24, ++0x00,0x0A,0x04,0x24, ++0x03,0x00,0x05,0x24, ++0xA9,0x45,0x00,0x0C, ++0x21,0x30,0x00,0x00, ++0x00,0x0A,0x04,0x24, ++0x08,0x00,0x05,0x24, ++0xA9,0x45,0x00,0x0C, ++0x01,0x00,0x06,0x24, ++0x00,0x0D,0x04,0x24, ++0x00,0x10,0x05,0x3C, ++0xA9,0x45,0x00,0x0C, ++0x21,0x30,0x00,0x00, ++0x00,0x0D,0x04,0x24, ++0x00,0x20,0x05,0x3C, ++0xA9,0x45,0x00,0x0C, ++0x01,0x00,0x06,0x24, ++0x00,0x0D,0x04,0x24, ++0x00,0x40,0x05,0x3C, ++0x21,0x30,0x00,0x00, ++0xA9,0x45,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x14,0x00,0xBF,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x08,0x00,0xE0,0x03, ++0x18,0x00,0xBD,0x27, ++0xA9,0x45,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x00,0x0D,0x04,0x24, ++0x00,0x20,0x05,0x3C, ++0xA9,0x45,0x00,0x0C, ++0x21,0x30,0x00,0x00, ++0x00,0x40,0x05,0x3C, ++0x21,0x30,0x00,0x00, ++0xA9,0x45,0x00,0x0C, ++0x00,0x0D,0x04,0x24, ++0x54,0x22,0x00,0x0C, ++0x10,0x27,0x04,0x24, ++0x00,0x0F,0x04,0x24, ++0x00,0x01,0x05,0x24, ++0xA9,0x45,0x00,0x0C, ++0x21,0x30,0x00,0x00, ++0x00,0x0F,0x04,0x24, ++0x00,0x01,0x05,0x24, ++0xA9,0x45,0x00,0x0C, ++0x01,0x00,0x06,0x24, ++0x14,0x00,0xBF,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x08,0x00,0xE0,0x03, ++0x18,0x00,0xBD,0x27, ++0xA9,0x45,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x00,0x0A,0x04,0x24, ++0x03,0x00,0x05,0x24, ++0xA9,0x45,0x00,0x0C, ++0x21,0x30,0x00,0x00, ++0x00,0x0A,0x04,0x24, ++0x08,0x00,0x05,0x24, ++0xA9,0x45,0x00,0x0C, ++0x01,0x00,0x06,0x24, ++0x00,0x0D,0x04,0x24, ++0x00,0x10,0x05,0x3C, ++0xA9,0x45,0x00,0x0C, ++0x21,0x30,0x00,0x00, ++0x00,0x0D,0x04,0x24, ++0x00,0x20,0x05,0x3C, ++0xA9,0x45,0x00,0x0C, ++0x01,0x00,0x06,0x24, ++0x00,0x0D,0x04,0x24, ++0x00,0x40,0x05,0x3C, ++0x3E,0x43,0x00,0x08, ++0x21,0x30,0x00,0x00, ++0xE0,0xFF,0xBD,0x27, ++0x10,0x00,0xB0,0xAF, ++0x21,0x80,0x80,0x00, ++0x02,0x80,0x04,0x3C, ++0x18,0x00,0xB2,0xAF, ++0x14,0x00,0xB1,0xAF, ++0x1C,0x00,0xBF,0xAF, ++0x2F,0x55,0x00,0x0C, ++0x08,0xD8,0x84,0x24, ++0x00,0x00,0x02,0x92, ++0x0F,0x00,0x12,0x3C, ++0x0F,0x00,0x11,0x3C, ++0x00,0x08,0x04,0x24, ++0x00,0x01,0x05,0x3C, ++0x20,0x00,0x40,0x10, ++0x21,0x30,0x00,0x00, ++0xA9,0x45,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x00,0x02,0x05,0x3C, ++0x21,0x30,0x00,0x00, ++0xA9,0x45,0x00,0x0C, ++0x00,0x08,0x04,0x24, ++0x01,0x00,0x04,0x92, ++0xE6,0x44,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x0D,0x00,0x06,0x3C, ++0xFF,0xFF,0x45,0x36, ++0x00,0x40,0xC6,0x34, ++0x5F,0x47,0x00,0x0C, ++0x21,0x00,0x04,0x24, ++0x54,0x22,0x00,0x0C, ++0x64,0x00,0x04,0x24, ++0xE6,0x44,0x00,0x0C, ++0x21,0x20,0x00,0x00, ++0x02,0x00,0x06,0x3C, ++0xFF,0xFF,0x45,0x36, ++0x1F,0x00,0xC6,0x34, ++0x5F,0x47,0x00,0x0C, ++0x21,0x20,0x00,0x00, ++0x54,0x22,0x00,0x0C, ++0x64,0x00,0x04,0x24, ++0x1C,0x00,0xBF,0x8F, ++0x18,0x00,0xB2,0x8F, ++0x14,0x00,0xB1,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x08,0x00,0xE0,0x03, ++0x20,0x00,0xBD,0x27, ++0xA9,0x45,0x00,0x0C, ++0x01,0x00,0x06,0x24, ++0x00,0x02,0x05,0x3C, ++0x01,0x00,0x06,0x24, ++0xA9,0x45,0x00,0x0C, ++0x00,0x08,0x04,0x24, ++0x01,0x00,0x04,0x92, ++0xE6,0x44,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x05,0x00,0x06,0x3C, ++0xFF,0xFF,0x25,0x36, ++0x00,0x40,0xC6,0x34, ++0x5F,0x47,0x00,0x0C, ++0x21,0x00,0x04,0x24, ++0x54,0x22,0x00,0x0C, ++0x64,0x00,0x04,0x24, ++0xFF,0xFF,0x25,0x36, ++0x21,0x20,0x00,0x00, ++0x5F,0x47,0x00,0x0C, ++0x03,0x00,0x06,0x3C, ++0x54,0x22,0x00,0x0C, ++0x64,0x00,0x04,0x24, ++0x1C,0x00,0xBF,0x8F, ++0x18,0x00,0xB2,0x8F, ++0x14,0x00,0xB1,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x08,0x00,0xE0,0x03, ++0x20,0x00,0xBD,0x27, ++0xE8,0xFF,0xBD,0x27, ++0x10,0x00,0xB0,0xAF, ++0x21,0x80,0x80,0x00, ++0x02,0x80,0x04,0x3C, ++0x14,0x00,0xBF,0xAF, ++0x2F,0x55,0x00,0x0C, ++0x20,0xD8,0x84,0x24, ++0x00,0x00,0x02,0x92, ++0x00,0x00,0x00,0x00, ++0x0A,0x00,0x40,0x10, ++0x00,0x0A,0x04,0x24, ++0x04,0x00,0x02,0x8E, ++0x00,0x08,0x04,0x24, ++0x04,0x00,0x42,0x2C, ++0x1C,0x00,0x40,0x14, ++0x00,0x01,0x05,0x3C, ++0x14,0x00,0xBF,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x08,0x00,0xE0,0x03, ++0x18,0x00,0xBD,0x27, ++0x04,0x00,0x02,0x8E, ++0x03,0x00,0x05,0x24, ++0x04,0x00,0x42,0x2C, ++0xF8,0xFF,0x40,0x10, ++0x21,0x30,0x00,0x00, ++0xA9,0x45,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x00,0x0A,0x04,0x24, ++0x08,0x00,0x05,0x24, ++0xA9,0x45,0x00,0x0C, ++0x01,0x00,0x06,0x24, ++0x00,0x0F,0x04,0x24, ++0x00,0x01,0x05,0x24, ++0xA9,0x45,0x00,0x0C, ++0x21,0x30,0x00,0x00, ++0x00,0x0F,0x04,0x24, ++0x00,0x01,0x05,0x24, ++0xA9,0x45,0x00,0x0C, ++0x01,0x00,0x06,0x24, ++0x14,0x00,0xBF,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x08,0x00,0xE0,0x03, ++0x18,0x00,0xBD,0x27, ++0xCB,0x45,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x00,0x08,0x04,0x24, ++0x00,0x01,0x05,0x3C, ++0x1B,0x00,0x40,0x10, ++0x01,0x00,0x06,0x24, ++0x00,0x0D,0x04,0x24, ++0x00,0x10,0x05,0x3C, ++0xA9,0x45,0x00,0x0C, ++0x21,0x30,0x00,0x00, ++0x00,0x0D,0x04,0x24, ++0x00,0x20,0x05,0x3C, ++0xA9,0x45,0x00,0x0C, ++0x21,0x30,0x00,0x00, ++0x00,0x0D,0x04,0x24, ++0x00,0x40,0x05,0x3C, ++0xA9,0x45,0x00,0x0C, ++0x21,0x30,0x00,0x00, ++0x00,0x0A,0x04,0x24, ++0x03,0x00,0x05,0x24, ++0xA9,0x45,0x00,0x0C, ++0x02,0x00,0x06,0x24, ++0x00,0x0A,0x04,0x24, ++0x08,0x00,0x05,0x24, ++0xA9,0x45,0x00,0x0C, ++0x21,0x30,0x00,0x00, ++0x00,0x0A,0x04,0x24, ++0x00,0x30,0x05,0x24, ++0xA9,0x45,0x00,0x0C, ++0x21,0x30,0x00,0x00, ++0xE4,0x43,0x00,0x08, ++0x00,0x00,0x00,0x00, ++0xA9,0x45,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0xEF,0x43,0x00,0x08, ++0x00,0x0D,0x04,0x24, ++0xE8,0xFF,0xBD,0x27, ++0x10,0x00,0xB0,0xAF, ++0x21,0x80,0x80,0x00, ++0x02,0x80,0x04,0x3C, ++0x14,0x00,0xBF,0xAF, ++0x2F,0x55,0x00,0x0C, ++0x40,0xD8,0x84,0x24, ++0x04,0x00,0x03,0x8E, ++0x00,0x00,0x00,0x00, ++0x04,0x00,0x62,0x2C, ++0x2C,0x00,0x40,0x14, ++0xFC,0xFF,0x62,0x24, ++0x18,0x00,0x42,0x2C, ++0x05,0x00,0x40,0x14, ++0x00,0x00,0x00,0x00, ++0x14,0x00,0xBF,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x08,0x00,0xE0,0x03, ++0x18,0x00,0xBD,0x27, ++0x02,0x80,0x04,0x3C, ++0x2F,0x55,0x00,0x0C, ++0x6C,0xD8,0x84,0x24, ++0x00,0x00,0x02,0x92, ++0x00,0x00,0x00,0x00, ++0x54,0x00,0x40,0x10, ++0x00,0x0D,0x04,0x24, ++0x00,0x08,0x04,0x24, ++0xCB,0x45,0x00,0x0C, ++0x00,0x02,0x05,0x3C, ++0x63,0x00,0x40,0x10, ++0x00,0x08,0x04,0x24, ++0x00,0x0A,0x04,0x24, ++0x03,0x00,0x05,0x24, ++0xA9,0x45,0x00,0x0C, ++0x21,0x30,0x00,0x00, ++0x00,0x0A,0x04,0x24, ++0x08,0x00,0x05,0x24, ++0xA9,0x45,0x00,0x0C, ++0x01,0x00,0x06,0x24, ++0x00,0x0D,0x04,0x24, ++0x00,0x10,0x05,0x3C, ++0xA9,0x45,0x00,0x0C, ++0x01,0x00,0x06,0x24, ++0x00,0x0D,0x04,0x24, ++0x00,0x20,0x05,0x3C, ++0xA9,0x45,0x00,0x0C, ++0x21,0x30,0x00,0x00, ++0x00,0x0D,0x04,0x24, ++0x00,0x40,0x05,0x3C, ++0xA9,0x45,0x00,0x0C, ++0x21,0x30,0x00,0x00, ++0x14,0x00,0xBF,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x08,0x00,0xE0,0x03, ++0x18,0x00,0xBD,0x27, ++0x02,0x80,0x04,0x3C, ++0x2F,0x55,0x00,0x0C, ++0x58,0xD8,0x84,0x24, ++0x00,0x00,0x02,0x92, ++0x00,0x00,0x00,0x00, ++0x21,0x00,0x40,0x10, ++0x00,0x0A,0x04,0x24, ++0x00,0x08,0x04,0x24, ++0xCB,0x45,0x00,0x0C, ++0x00,0x01,0x05,0x3C, ++0x3A,0x00,0x40,0x10, ++0x00,0x08,0x04,0x24, ++0x00,0x0D,0x04,0x24, ++0x00,0x10,0x05,0x3C, ++0xA9,0x45,0x00,0x0C, ++0x21,0x30,0x00,0x00, ++0x00,0x0D,0x04,0x24, ++0x00,0x20,0x05,0x3C, ++0xA9,0x45,0x00,0x0C, ++0x21,0x30,0x00,0x00, ++0x00,0x0D,0x04,0x24, ++0x00,0x40,0x05,0x3C, ++0xA9,0x45,0x00,0x0C, ++0x21,0x30,0x00,0x00, ++0x04,0x00,0x06,0x8E, ++0x00,0x0A,0x04,0x24, ++0xA9,0x45,0x00,0x0C, ++0x00,0x30,0x05,0x24, ++0x00,0x0A,0x04,0x24, ++0x03,0x00,0x05,0x24, ++0xA9,0x45,0x00,0x0C, ++0x02,0x00,0x06,0x24, ++0x00,0x0A,0x04,0x24, ++0x08,0x00,0x05,0x24, ++0x01,0x00,0x06,0x24, ++0xA9,0x45,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x3F,0x44,0x00,0x08, ++0x00,0x00,0x00,0x00, ++0x03,0x00,0x05,0x24, ++0xA9,0x45,0x00,0x0C, ++0x21,0x30,0x00,0x00, ++0x00,0x0A,0x04,0x24, ++0x08,0x00,0x05,0x24, ++0xA9,0x45,0x00,0x0C, ++0x01,0x00,0x06,0x24, ++0x00,0x0F,0x04,0x24, ++0x00,0x01,0x05,0x24, ++0xA9,0x45,0x00,0x0C, ++0x21,0x30,0x00,0x00, ++0x00,0x0F,0x04,0x24, ++0x00,0x01,0x05,0x24, ++0x66,0x44,0x00,0x08, ++0x01,0x00,0x06,0x24, ++0x00,0x10,0x05,0x3C, ++0xA9,0x45,0x00,0x0C, ++0x21,0x30,0x00,0x00, ++0x00,0x0D,0x04,0x24, ++0x00,0x20,0x05,0x3C, ++0xA9,0x45,0x00,0x0C, ++0x21,0x30,0x00,0x00, ++0x00,0x40,0x05,0x3C, ++0x21,0x30,0x00,0x00, ++0xA9,0x45,0x00,0x0C, ++0x00,0x0D,0x04,0x24, ++0x54,0x22,0x00,0x0C, ++0x10,0x27,0x04,0x24, ++0x72,0x44,0x00,0x08, ++0x00,0x0F,0x04,0x24, ++0x00,0x01,0x05,0x3C, ++0xA9,0x45,0x00,0x0C, ++0x01,0x00,0x06,0x24, ++0x50,0x44,0x00,0x08, ++0x00,0x0D,0x04,0x24, ++0x00,0x02,0x05,0x3C, ++0xA9,0x45,0x00,0x0C, ++0x01,0x00,0x06,0x24, ++0x2C,0x44,0x00,0x08, ++0x00,0x0A,0x04,0x24, ++0xE8,0xFF,0xBD,0x27, ++0x25,0xB0,0x02,0x3C, ++0x14,0x00,0xBF,0xAF, ++0x10,0x00,0xB0,0xAF, ++0x03,0x02,0x42,0x34, ++0x00,0x00,0x43,0x90, ++0x00,0x00,0x90,0x90, ++0x25,0xB0,0x02,0x3C, ++0xFF,0x00,0x63,0x30, ++0xFB,0x00,0x65,0x30, ++0x00,0x00,0x04,0x3A, ++0x04,0x00,0x63,0x34, ++0x0B,0x18,0xA4,0x00, ++0x03,0x02,0x42,0x34, ++0x00,0x00,0x43,0xA0, ++0x12,0x00,0x00,0x12, ++0x01,0x00,0x02,0x24, ++0x22,0x00,0x02,0x12, ++0x00,0x08,0x04,0x24, ++0x1A,0x00,0x00,0x12, ++0x01,0x00,0x02,0x24, ++0x08,0x00,0x02,0x16, ++0x00,0x00,0x00,0x00, ++0xE6,0x44,0x00,0x0C, ++0x21,0x20,0x00,0x00, ++0x18,0x00,0x04,0x24, ++0x00,0x0C,0x05,0x24, ++0x21,0x30,0x00,0x00, ++0x5F,0x47,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x14,0x00,0xBF,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x08,0x00,0xE0,0x03, ++0x18,0x00,0xBD,0x27, ++0x00,0x08,0x04,0x24, ++0x01,0x00,0x05,0x24, ++0xA9,0x45,0x00,0x0C, ++0x21,0x30,0x00,0x00, ++0x00,0x09,0x04,0x24, ++0x01,0x00,0x05,0x24, ++0xA9,0x45,0x00,0x0C, ++0x21,0x30,0x00,0x00, ++0x84,0x08,0x04,0x24, ++0xFF,0xFF,0x05,0x24, ++0xA9,0x45,0x00,0x0C, ++0x58,0x00,0x06,0x24, ++0xE6,0x44,0x00,0x0C, ++0x21,0x20,0x00,0x00, ++0x18,0x00,0x04,0x24, ++0x00,0x0C,0x05,0x24, ++0xAE,0x44,0x00,0x08, ++0x01,0x00,0x06,0x24, ++0x01,0x00,0x05,0x24, ++0xA9,0x45,0x00,0x0C, ++0x01,0x00,0x06,0x24, ++0x00,0x09,0x04,0x24, ++0x01,0x00,0x05,0x24, ++0xA9,0x45,0x00,0x0C, ++0x01,0x00,0x06,0x24, ++0x00,0x0A,0x04,0x24, ++0x10,0x00,0x05,0x24, ++0xA9,0x45,0x00,0x0C, ++0x21,0x30,0x00,0x00, ++0x00,0x0D,0x04,0x24, ++0x00,0x0C,0x05,0x24, ++0xA9,0x45,0x00,0x0C, ++0x21,0x30,0x00,0x00, ++0x84,0x08,0x04,0x24, ++0xFF,0xFF,0x05,0x24, ++0xA9,0x45,0x00,0x0C, ++0x18,0x00,0x06,0x24, ++0xA5,0x44,0x00,0x08, ++0x00,0x00,0x00,0x00, ++0x25,0xB0,0x02,0x3C, ++0x21,0x20,0x82,0x00, ++0x00,0x00,0x85,0xAC, ++0x21,0x10,0x00,0x00, ++0x01,0x00,0x42,0x24, ++0xFF,0x00,0x42,0x30, ++0x06,0x00,0x43,0x2C, ++0xFC,0xFF,0x60,0x14, ++0x00,0x00,0x00,0x00, ++0x08,0x00,0xE0,0x03, ++0x00,0x00,0x00,0x00, ++0x25,0xB0,0x05,0x3C, ++0x01,0x80,0x03,0x3C, ++0x21,0x38,0x80,0x00, ++0x18,0x03,0xA2,0x34, ++0x98,0x13,0x63,0x24, ++0x01,0x00,0x04,0x24, ++0x00,0x00,0x43,0xAC, ++0x35,0x00,0xE4,0x10, ++0x00,0x00,0x00,0x00, ++0x08,0x00,0xE0,0x10, ++0x20,0x08,0xA2,0x34, ++0x02,0x00,0x02,0x24, ++0x83,0x00,0xE2,0x10, ++0x03,0x00,0x02,0x24, ++0x5A,0x00,0xE2,0x10, ++0x00,0x00,0x00,0x00, ++0x08,0x00,0xE0,0x03, ++0x00,0x00,0x00,0x00, ++0x02,0x80,0x03,0x3C, ++0x00,0x00,0x44,0x8C, ++0x30,0x1F,0x66,0x24, ++0x70,0x08,0x02,0x24, ++0xE0,0x08,0x03,0x24, ++0x34,0x1C,0xC2,0xAC, ++0x40,0x08,0x02,0x24, ++0x38,0x1C,0xC3,0xAC, ++0x44,0x1C,0xC2,0xAC, ++0x78,0x08,0x03,0x24, ++0x0C,0x08,0x02,0x24, ++0x48,0x1C,0xC3,0xAC, ++0x4C,0x1C,0xC2,0xAC, ++0x10,0x08,0x03,0x24, ++0x20,0x08,0x02,0x24, ++0x50,0x1C,0xC3,0xAC, ++0x54,0x1C,0xC2,0xAC, ++0x24,0x08,0x03,0x24, ++0x58,0x08,0x02,0x24, ++0x58,0x1C,0xC3,0xAC, ++0x5C,0x1C,0xC2,0xAC, ++0x50,0x0C,0x03,0x24, ++0x54,0x0C,0x02,0x24, ++0x60,0x1C,0xC3,0xAC, ++0x64,0x1C,0xC2,0xAC, ++0x14,0x0C,0x03,0x24, ++0x10,0x0C,0x02,0x24, ++0x60,0x08,0x05,0x24, ++0x68,0x1C,0xC3,0xAC, ++0x6C,0x1C,0xC2,0xAC, ++0x80,0x0C,0x03,0x24, ++0x84,0x0C,0x02,0x24, ++0x00,0x01,0x84,0x30, ++0x74,0x1C,0xC2,0xAC, ++0x40,0x1C,0xC5,0xAC, ++0x70,0x1C,0xC3,0xAC, ++0x31,0x1C,0xC0,0xA0, ++0x3C,0x1C,0xC5,0xAC, ++0x02,0x00,0x80,0x10, ++0xA0,0x08,0x02,0x24, ++0xB8,0x08,0x02,0x24, ++0x08,0x00,0xE0,0x03, ++0x78,0x1C,0xC2,0xAC, ++0x28,0x08,0xA2,0x34, ++0x02,0x80,0x03,0x3C, ++0x00,0x00,0x44,0x8C, ++0x30,0x1F,0x66,0x24, ++0x70,0x08,0x02,0x24, ++0xE0,0x08,0x03,0x24, ++0x34,0x1C,0xC2,0xAC, ++0x44,0x08,0x02,0x24, ++0x38,0x1C,0xC3,0xAC, ++0x44,0x1C,0xC2,0xAC, ++0x78,0x08,0x03,0x24, ++0x0C,0x08,0x02,0x24, ++0x48,0x1C,0xC3,0xAC, ++0x4C,0x1C,0xC2,0xAC, ++0x14,0x08,0x03,0x24, ++0x28,0x08,0x02,0x24, ++0x50,0x1C,0xC3,0xAC, ++0x54,0x1C,0xC2,0xAC, ++0x2C,0x08,0x03,0x24, ++0x58,0x08,0x02,0x24, ++0x58,0x1C,0xC3,0xAC, ++0x5C,0x1C,0xC2,0xAC, ++0x58,0x0C,0x03,0x24, ++0x5C,0x0C,0x02,0x24, ++0x60,0x1C,0xC3,0xAC, ++0x64,0x1C,0xC2,0xAC, ++0x1C,0x0C,0x03,0x24, ++0x18,0x0C,0x02,0x24, ++0x64,0x08,0x05,0x24, ++0x68,0x1C,0xC3,0xAC, ++0x6C,0x1C,0xC2,0xAC, ++0x88,0x0C,0x03,0x24, ++0x8C,0x0C,0x02,0x24, ++0x00,0x01,0x84,0x30, ++0x74,0x1C,0xC2,0xAC, ++0x31,0x1C,0xC7,0xA0, ++0x40,0x1C,0xC5,0xAC, ++0x70,0x1C,0xC3,0xAC, ++0x3C,0x1C,0xC5,0xAC, ++0xD6,0xFF,0x80,0x10, ++0xA4,0x08,0x02,0x24, ++0xBC,0x08,0x02,0x24, ++0x08,0x00,0xE0,0x03, ++0x78,0x1C,0xC2,0xAC, ++0x02,0x80,0x02,0x3C, ++0x30,0x1F,0x42,0x24, ++0xAC,0x08,0x03,0x24, ++0x78,0x1C,0x43,0xAC, ++0x74,0x08,0x03,0x24, ++0xE4,0x08,0x04,0x24, ++0x34,0x1C,0x43,0xAC, ++0x4C,0x08,0x03,0x24, ++0x38,0x1C,0x44,0xAC, ++0x44,0x1C,0x43,0xAC, ++0x7C,0x08,0x04,0x24, ++0x0C,0x08,0x03,0x24, ++0x48,0x1C,0x44,0xAC, ++0x4C,0x1C,0x43,0xAC, ++0x1C,0x08,0x04,0x24, ++0x38,0x08,0x03,0x24, ++0x50,0x1C,0x44,0xAC, ++0x54,0x1C,0x43,0xAC, ++0x3C,0x08,0x04,0x24, ++0x5C,0x08,0x03,0x24, ++0x58,0x1C,0x44,0xAC, ++0x5C,0x1C,0x43,0xAC, ++0x68,0x0C,0x04,0x24, ++0x6C,0x0C,0x03,0x24, ++0x60,0x1C,0x44,0xAC, ++0x64,0x1C,0x43,0xAC, ++0x2C,0x0C,0x04,0x24, ++0x28,0x0C,0x03,0x24, ++0x6C,0x08,0x05,0x24, ++0x68,0x1C,0x44,0xAC, ++0x6C,0x1C,0x43,0xAC, ++0x98,0x0C,0x04,0x24, ++0x9C,0x0C,0x03,0x24, ++0x31,0x1C,0x47,0xA0, ++0x40,0x1C,0x45,0xAC, ++0x70,0x1C,0x44,0xAC, ++0x74,0x1C,0x43,0xAC, ++0x08,0x00,0xE0,0x03, ++0x3C,0x1C,0x45,0xAC, ++0x02,0x80,0x02,0x3C, ++0x30,0x1F,0x42,0x24, ++0xA8,0x08,0x03,0x24, ++0x78,0x1C,0x43,0xAC, ++0x74,0x08,0x03,0x24, ++0xE4,0x08,0x04,0x24, ++0x34,0x1C,0x43,0xAC, ++0x48,0x08,0x03,0x24, ++0x38,0x1C,0x44,0xAC, ++0x44,0x1C,0x43,0xAC, ++0x7C,0x08,0x04,0x24, ++0x0C,0x08,0x03,0x24, ++0x48,0x1C,0x44,0xAC, ++0x4C,0x1C,0x43,0xAC, ++0x18,0x08,0x04,0x24, ++0x30,0x08,0x03,0x24, ++0x50,0x1C,0x44,0xAC, ++0x54,0x1C,0x43,0xAC, ++0x34,0x08,0x04,0x24, ++0x5C,0x08,0x03,0x24, ++0x58,0x1C,0x44,0xAC, ++0x5C,0x1C,0x43,0xAC, ++0x60,0x0C,0x04,0x24, ++0x64,0x0C,0x03,0x24, ++0x60,0x1C,0x44,0xAC, ++0x64,0x1C,0x43,0xAC, ++0x24,0x0C,0x04,0x24, ++0x20,0x0C,0x03,0x24, ++0x68,0x08,0x05,0x24, ++0x68,0x1C,0x44,0xAC, ++0x6C,0x1C,0x43,0xAC, ++0x90,0x0C,0x04,0x24, ++0x94,0x0C,0x03,0x24, ++0x31,0x1C,0x47,0xA0, ++0x40,0x1C,0x45,0xAC, ++0x70,0x1C,0x44,0xAC, ++0x74,0x1C,0x43,0xAC, ++0x08,0x00,0xE0,0x03, ++0x3C,0x1C,0x45,0xAC, ++0xA2,0x45,0x00,0x08, ++0x21,0x18,0x00,0x00, ++0x20,0x00,0x62,0x2C, ++0x06,0x00,0x40,0x10, ++0x00,0x00,0x00,0x00, ++0x06,0x10,0x64,0x00, ++0x01,0x00,0x42,0x30, ++0xFA,0xFF,0x40,0x10, ++0x01,0x00,0x63,0x24, ++0xFF,0xFF,0x63,0x24, ++0x08,0x00,0xE0,0x03, ++0x21,0x10,0x60,0x00, ++0xD8,0xFF,0xBD,0x27, ++0x14,0x00,0xB1,0xAF, ++0x25,0xB0,0x02,0x3C, ++0x21,0x88,0xA0,0x00, ++0xFF,0xFF,0x03,0x24, ++0x1C,0x00,0xB3,0xAF, ++0x18,0x00,0xB2,0xAF, ++0x10,0x00,0xB0,0xAF, ++0x20,0x00,0xBF,0xAF, ++0x21,0x98,0xC0,0x00, ++0x21,0x28,0xC0,0x00, ++0x21,0x90,0x80,0x00, ++0x09,0x00,0x23,0x12, ++0x21,0x80,0x82,0x00, ++0x00,0x00,0x10,0x8E, ++0x9D,0x45,0x00,0x0C, ++0x21,0x20,0x20,0x02, ++0x27,0x28,0x11,0x00, ++0x24,0x28,0xB0,0x00, ++0x04,0x10,0x53,0x00, ++0x25,0x28,0xA2,0x00, ++0x21,0x20,0x40,0x02, ++0x20,0x00,0xBF,0x8F, ++0x1C,0x00,0xB3,0x8F, ++0x18,0x00,0xB2,0x8F, ++0x14,0x00,0xB1,0x8F, ++0x10,0x00,0xB0,0x8F, ++0xDB,0x44,0x00,0x08, ++0x28,0x00,0xBD,0x27, ++0x02,0x80,0x02,0x3C, ++0x21,0x30,0x80,0x00, ++0x74,0x3B,0x44,0x8C, ++0xA9,0x45,0x00,0x08, ++0xFF,0xFF,0x05,0x24, ++0xE0,0xFF,0xBD,0x27, ++0x25,0xB0,0x02,0x3C, ++0x18,0x00,0xBF,0xAF, ++0x14,0x00,0xB1,0xAF, ++0x10,0x00,0xB0,0xAF, ++0x21,0x20,0x82,0x00, ++0x00,0x00,0x90,0x8C, ++0x21,0x88,0xA0,0x00, ++0x9D,0x45,0x00,0x0C, ++0x21,0x20,0xA0,0x00, ++0x24,0x80,0x11,0x02, ++0x06,0x10,0x50,0x00, ++0x18,0x00,0xBF,0x8F, ++0x14,0x00,0xB1,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x08,0x00,0xE0,0x03, ++0x20,0x00,0xBD,0x27, ++0xD8,0xFF,0xBD,0x27, ++0x14,0x00,0xB1,0xAF, ++0x02,0x80,0x11,0x3C, ++0x20,0x00,0xBF,0xAF, ++0x18,0x00,0xB2,0xAF, ++0x1C,0x00,0xB3,0xAF, ++0x10,0x00,0xB0,0xAF, ++0x30,0x1F,0x31,0x26, ++0x58,0x1C,0x23,0x8E, ++0x25,0xB0,0x02,0x3C, ++0x24,0x08,0x53,0x8C, ++0x21,0x18,0x62,0x00, ++0x00,0x00,0x70,0x8C, ++0x7F,0x80,0x02,0x3C, ++0xFF,0xFF,0x42,0x34, ++0xFF,0x7F,0x05,0x3C, ++0x24,0x80,0x02,0x02, ++0xC0,0x25,0x04,0x00, ++0xFF,0xFF,0xA5,0x34, ++0x24,0x28,0x65,0x02, ++0x25,0x80,0x04,0x02, ++0xDB,0x44,0x00,0x0C, ++0x24,0x08,0x04,0x24, ++0x25,0x22,0x00,0x0C, ++0x01,0x00,0x04,0x24, ++0x00,0x80,0x12,0x3C, ++0x58,0x1C,0x24,0x8E, ++0x25,0x80,0x12,0x02, ++0xDB,0x44,0x00,0x0C, ++0x21,0x28,0x00,0x02, ++0x25,0x22,0x00,0x0C, ++0x01,0x00,0x04,0x24, ++0x25,0x28,0x72,0x02, ++0xDB,0x44,0x00,0x0C, ++0x24,0x08,0x04,0x24, ++0x25,0x22,0x00,0x0C, ++0x01,0x00,0x04,0x24, ++0x78,0x1C,0x24,0x8E, ++0x0F,0x00,0x05,0x3C, ++0x20,0x00,0xBF,0x8F, ++0x1C,0x00,0xB3,0x8F, ++0x18,0x00,0xB2,0x8F, ++0x14,0x00,0xB1,0x8F, ++0x10,0x00,0xB0,0x8F, ++0xFF,0xFF,0xA5,0x34, ++0xCB,0x45,0x00,0x08, ++0x28,0x00,0xBD,0x27, ++0xE0,0xFF,0xBD,0x27, ++0x14,0x00,0xB1,0xAF, ++0x02,0x80,0x11,0x3C, ++0x10,0x00,0xB0,0xAF, ++0x18,0x00,0xBF,0xAF, ++0x30,0x1F,0x27,0x26, ++0x33,0x1C,0xE5,0x90, ++0x01,0x80,0x03,0x3C, ++0x25,0xB0,0x02,0x3C, ++0x2C,0x18,0x63,0x24, ++0x18,0x03,0x42,0x34, ++0x02,0x00,0x06,0x24, ++0x00,0x00,0x43,0xAC, ++0x34,0x00,0xA6,0x10, ++0x21,0x80,0x80,0x00, ++0x03,0x00,0x03,0x24, ++0x3A,0x00,0xA3,0x10, ++0x2E,0x00,0x02,0x2E, ++0x10,0x00,0x02,0x2E, ++0x07,0x00,0x40,0x10, ++0x00,0x00,0x00,0x00, ++0xFF,0x00,0x04,0x32, ++0x18,0x00,0xBF,0x8F, ++0x14,0x00,0xB1,0x8F, ++0x10,0x00,0xB0,0x8F, ++0xDC,0x45,0x00,0x08, ++0x20,0x00,0xBD,0x27, ++0xFA,0xFF,0xA6,0x14, ++0xFF,0x00,0x04,0x32, ++0x31,0x1C,0xE4,0x90, ++0x01,0x00,0x02,0x24, ++0x33,0x00,0x82,0x10, ++0x02,0x00,0x82,0x28, ++0x38,0x00,0x40,0x14, ++0x00,0x00,0x00,0x00, ++0x38,0x00,0x85,0x10, ++0x30,0x1F,0x22,0x26, ++0x2E,0x00,0x83,0x10, ++0x00,0x00,0x00,0x00, ++0x00,0x08,0x04,0x24, ++0xCB,0x45,0x00,0x0C, ++0xFF,0xFF,0x05,0x24, ++0xFF,0xFC,0x06,0x3C, ++0xFF,0xFF,0xC6,0x34, ++0x24,0x30,0x46,0x00, ++0x00,0x08,0x04,0x24, ++0xA9,0x45,0x00,0x0C, ++0xFF,0xFF,0x05,0x24, ++0x30,0x1F,0x22,0x26, ++0x31,0x1C,0x44,0x90, ++0x01,0x00,0x03,0x24, ++0x07,0x00,0x83,0x10, ++0x02,0x00,0x82,0x28, ++0x2C,0x00,0x40,0x14, ++0x02,0x00,0x02,0x24, ++0x2C,0x00,0x82,0x10, ++0x03,0x00,0x02,0x24, ++0xDB,0xFF,0x82,0x14, ++0x00,0x00,0x00,0x00, ++0x30,0x1F,0x22,0x26, ++0x34,0x1C,0x44,0x8C, ++0x0F,0x00,0x05,0x3C, ++0xA9,0x45,0x00,0x0C, ++0x21,0x30,0x00,0x00, ++0x21,0x46,0x00,0x08, ++0xFF,0x00,0x04,0x32, ++0x25,0x00,0x82,0x2C, ++0xCC,0xFF,0x40,0x14, ++0x03,0x00,0x03,0x24, ++0x18,0x00,0xBF,0x8F, ++0x14,0x00,0xB1,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x21,0x10,0x00,0x00, ++0x08,0x00,0xE0,0x03, ++0x20,0x00,0xBD,0x27, ++0xC7,0xFF,0x40,0x14, ++0x10,0x00,0x02,0x2E, ++0x18,0x00,0xBF,0x8F, ++0x14,0x00,0xB1,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x21,0x10,0x00,0x00, ++0x08,0x00,0xE0,0x03, ++0x20,0x00,0xBD,0x27, ++0x30,0x1F,0x22,0x26, ++0x34,0x1C,0x44,0x8C, ++0x0F,0x00,0x05,0x3C, ++0xA9,0x45,0x00,0x0C, ++0x0F,0x00,0x06,0x24, ++0x33,0x46,0x00,0x08, ++0x00,0x08,0x04,0x24, ++0xCC,0xFF,0x80,0x14, ++0x30,0x1F,0x22,0x26, ++0x34,0x1C,0x44,0x8C, ++0x0F,0x00,0x05,0x24, ++0xA9,0x45,0x00,0x0C, ++0x0F,0x00,0x06,0x24, ++0x33,0x46,0x00,0x08, ++0x00,0x08,0x04,0x24, ++0xB2,0xFF,0x80,0x14, ++0x00,0x00,0x00,0x00, ++0x30,0x1F,0x22,0x26, ++0x34,0x1C,0x44,0x8C, ++0x0F,0x00,0x05,0x24, ++0xA9,0x45,0x00,0x0C, ++0x21,0x30,0x00,0x00, ++0x21,0x46,0x00,0x08, ++0xFF,0x00,0x04,0x32, ++0xE0,0xFF,0xBD,0x27, ++0x14,0x00,0xB1,0xAF, ++0x02,0x80,0x11,0x3C, ++0x30,0x1F,0x28,0x26, ++0x33,0x1C,0x06,0x91, ++0x01,0x80,0x03,0x3C, ++0x25,0xB0,0x02,0x3C, ++0xD8,0x19,0x63,0x24, ++0x18,0x03,0x42,0x34, ++0x02,0x00,0x07,0x24, ++0x18,0x00,0xB2,0xAF, ++0x10,0x00,0xB0,0xAF, ++0x1C,0x00,0xBF,0xAF, ++0x00,0x00,0x43,0xAC, ++0x21,0x90,0xA0,0x00, ++0x39,0x00,0xC7,0x10, ++0xFF,0x00,0x90,0x30, ++0x03,0x00,0x03,0x24, ++0x3F,0x00,0xC3,0x10, ++0x2E,0x00,0x02,0x2E, ++0x10,0x00,0x02,0x2E, ++0x0C,0x00,0x40,0x10, ++0x00,0x00,0x00,0x00, ++0x0F,0x00,0x04,0x3C, ++0xFF,0xFF,0x84,0x34, ++0x24,0x20,0x44,0x02, ++0x00,0x15,0x10,0x00, ++0x1C,0x00,0xBF,0x8F, ++0x18,0x00,0xB2,0x8F, ++0x14,0x00,0xB1,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x25,0x20,0x44,0x00, ++0xC6,0x45,0x00,0x08, ++0x20,0x00,0xBD,0x27, ++0xF5,0xFF,0xC7,0x14, ++0x0F,0x00,0x04,0x3C, ++0x31,0x1C,0x04,0x91, ++0x01,0x00,0x02,0x24, ++0x33,0x00,0x82,0x10, ++0x02,0x00,0x82,0x28, ++0x38,0x00,0x40,0x14, ++0x00,0x00,0x00,0x00, ++0x38,0x00,0x86,0x10, ++0x30,0x1F,0x22,0x26, ++0x2E,0x00,0x83,0x10, ++0x00,0x00,0x00,0x00, ++0x00,0x08,0x04,0x24, ++0xCB,0x45,0x00,0x0C, ++0xFF,0xFF,0x05,0x24, ++0xFF,0xFC,0x06,0x3C, ++0xFF,0xFF,0xC6,0x34, ++0x24,0x30,0x46,0x00, ++0x00,0x08,0x04,0x24, ++0xA9,0x45,0x00,0x0C, ++0xFF,0xFF,0x05,0x24, ++0x30,0x1F,0x22,0x26, ++0x31,0x1C,0x44,0x90, ++0x01,0x00,0x03,0x24, ++0x07,0x00,0x83,0x10, ++0x02,0x00,0x82,0x28, ++0x2C,0x00,0x40,0x14, ++0x02,0x00,0x02,0x24, ++0x2C,0x00,0x82,0x10, ++0x03,0x00,0x02,0x24, ++0xD6,0xFF,0x82,0x14, ++0x00,0x00,0x00,0x00, ++0x30,0x1F,0x22,0x26, ++0x34,0x1C,0x44,0x8C, ++0x0F,0x00,0x05,0x3C, ++0xA9,0x45,0x00,0x0C, ++0x21,0x30,0x00,0x00, ++0x8E,0x46,0x00,0x08, ++0x0F,0x00,0x04,0x3C, ++0x25,0x00,0x02,0x2E, ++0xC7,0xFF,0x40,0x14, ++0x03,0x00,0x03,0x24, ++0x1C,0x00,0xBF,0x8F, ++0x18,0x00,0xB2,0x8F, ++0x14,0x00,0xB1,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x08,0x00,0xE0,0x03, ++0x20,0x00,0xBD,0x27, ++0xC1,0xFF,0x40,0x14, ++0x00,0x00,0x00,0x00, ++0x1C,0x00,0xBF,0x8F, ++0x18,0x00,0xB2,0x8F, ++0x14,0x00,0xB1,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x08,0x00,0xE0,0x03, ++0x20,0x00,0xBD,0x27, ++0x30,0x1F,0x22,0x26, ++0x34,0x1C,0x44,0x8C, ++0x0F,0x00,0x05,0x3C, ++0xA9,0x45,0x00,0x0C, ++0x0F,0x00,0x06,0x24, ++0xA5,0x46,0x00,0x08, ++0x00,0x08,0x04,0x24, ++0xCC,0xFF,0x80,0x14, ++0x30,0x1F,0x22,0x26, ++0x34,0x1C,0x44,0x8C, ++0x0F,0x00,0x05,0x24, ++0xA9,0x45,0x00,0x0C, ++0x0F,0x00,0x06,0x24, ++0xA5,0x46,0x00,0x08, ++0x00,0x08,0x04,0x24, ++0xAD,0xFF,0x80,0x14, ++0x00,0x00,0x00,0x00, ++0x30,0x1F,0x22,0x26, ++0x34,0x1C,0x44,0x8C, ++0x0F,0x00,0x05,0x24, ++0xA9,0x45,0x00,0x0C, ++0x21,0x30,0x00,0x00, ++0x8E,0x46,0x00,0x08, ++0x0F,0x00,0x04,0x3C, ++0xE8,0xFF,0xBD,0x27, ++0x10,0x00,0xB0,0xAF, ++0x21,0x80,0x80,0x00, ++0x14,0x00,0xBF,0xAF, ++0xDC,0x45,0x00,0x0C, ++0x21,0x20,0x00,0x00, ++0x40,0x01,0x44,0x34, ++0x21,0x18,0x40,0x00, ++0x1F,0x00,0x02,0x2E, ++0x00,0x23,0x04,0x00, ++0x10,0x00,0x40,0x10, ++0x10,0x00,0x05,0x2E, ++0x00,0x01,0x64,0x34, ++0x06,0x00,0xA0,0x10, ++0x00,0x23,0x04,0x00, ++0x21,0x10,0x00,0x02, ++0x14,0x00,0xBF,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x08,0x00,0xE0,0x03, ++0x18,0x00,0xBD,0x27, ++0xC6,0x45,0x00,0x0C, ++0xF1,0xFF,0x10,0x26, ++0x21,0x10,0x00,0x02, ++0x14,0x00,0xBF,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x08,0x00,0xE0,0x03, ++0x18,0x00,0xBD,0x27, ++0xC6,0x45,0x00,0x0C, ++0xE2,0xFF,0x10,0x26, ++0x21,0x10,0x00,0x02, ++0x14,0x00,0xBF,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x08,0x00,0xE0,0x03, ++0x18,0x00,0xBD,0x27, ++0xE0,0xFF,0xBD,0x27, ++0x25,0xB0,0x02,0x3C, ++0x18,0x00,0xBF,0xAF, ++0x14,0x00,0xB1,0xAF, ++0x10,0x00,0xB0,0xAF, ++0x21,0x20,0x82,0x00, ++0x00,0x00,0x90,0x8C, ++0x21,0x88,0xA0,0x00, ++0x9D,0x45,0x00,0x0C, ++0x21,0x20,0xA0,0x00, ++0x24,0x80,0x11,0x02, ++0x06,0x10,0x50,0x00, ++0x18,0x00,0xBF,0x8F, ++0x14,0x00,0xB1,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x08,0x00,0xE0,0x03, ++0x20,0x00,0xBD,0x27, ++0xD8,0xFF,0xBD,0x27, ++0x25,0xB0,0x02,0x3C, ++0x18,0x00,0xB2,0xAF, ++0x21,0x90,0x82,0x00, ++0xFF,0xFF,0x02,0x24, ++0x1C,0x00,0xB3,0xAF, ++0x14,0x00,0xB1,0xAF, ++0x20,0x00,0xBF,0xAF, ++0x10,0x00,0xB0,0xAF, ++0x21,0x88,0xA0,0x00, ++0x21,0x20,0xA0,0x00, ++0x21,0x18,0x40,0x02, ++0x10,0x00,0xA2,0x10, ++0x21,0x98,0xC0,0x00, ++0x00,0x00,0x50,0x8E, ++0x9D,0x45,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x27,0x18,0x11,0x00, ++0x24,0x18,0x70,0x00, ++0x04,0x10,0x53,0x00, ++0x25,0x18,0x62,0x00, ++0x00,0x00,0x43,0xAE, ++0x20,0x00,0xBF,0x8F, ++0x1C,0x00,0xB3,0x8F, ++0x18,0x00,0xB2,0x8F, ++0x14,0x00,0xB1,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x08,0x00,0xE0,0x03, ++0x28,0x00,0xBD,0x27, ++0x20,0x00,0xBF,0x8F, ++0x1C,0x00,0xB3,0x8F, ++0x18,0x00,0xB2,0x8F, ++0x14,0x00,0xB1,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x28,0x00,0xBD,0x27, ++0x00,0x00,0x66,0xAC, ++0x08,0x00,0xE0,0x03, ++0x00,0x00,0x00,0x00, ++0x25,0xB0,0x02,0x3C, ++0x21,0x38,0x82,0x00, ++0xFF,0xFF,0x02,0x24, ++0x27,0x40,0x05,0x00, ++0x08,0x00,0xA2,0x10, ++0x24,0x18,0xC5,0x00, ++0x00,0x00,0xE2,0x8C, ++0x00,0x00,0x00,0x00, ++0x24,0x10,0x02,0x01, ++0x25,0x10,0x43,0x00, ++0x00,0x00,0xE2,0xAC, ++0x08,0x00,0xE0,0x03, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0xE6,0xAC, ++0x08,0x00,0xE0,0x03, ++0x00,0x00,0x00,0x00, ++0x21,0x38,0xA0,0x00, ++0x25,0xB0,0x02,0x3C, ++0xFF,0xFF,0x03,0x24, ++0x27,0x48,0x05,0x00, ++0x24,0x40,0xC7,0x00, ++0x21,0x28,0xC0,0x00, ++0x05,0x00,0xE3,0x10, ++0x21,0x30,0x82,0x00, ++0x00,0x00,0xC5,0x8C, ++0x00,0x00,0x00,0x00, ++0x24,0x28,0x25,0x01, ++0x25,0x28,0xA8,0x00, ++0xDB,0x44,0x00,0x08, ++0x00,0x00,0x00,0x00, ++0x01,0x80,0x02,0x3C, ++0x25,0xB0,0x03,0x3C, ++0xD8,0xFF,0xBD,0x27, ++0x7C,0x1D,0x42,0x24, ++0x18,0x03,0x63,0x34, ++0x20,0x00,0xB4,0xAF, ++0x1C,0x00,0xB3,0xAF, ++0x14,0x00,0xB1,0xAF, ++0x24,0x00,0xBF,0xAF, ++0x18,0x00,0xB2,0xAF, ++0x10,0x00,0xB0,0xAF, ++0x00,0x00,0x62,0xAC, ++0x21,0x88,0xA0,0x00, ++0x21,0x98,0xC0,0x00, ++0x21,0xA0,0x80,0x00, ++0x00,0x60,0x12,0x40, ++0x01,0x00,0x41,0x36, ++0x01,0x00,0x21,0x38, ++0x00,0x60,0x81,0x40, ++0x0F,0x00,0x02,0x3C, ++0xFF,0xFF,0x42,0x34, ++0x0A,0x00,0x22,0x12, ++0x21,0x28,0xC0,0x00, ++0x0B,0x46,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x21,0x20,0x20,0x02, ++0x9D,0x45,0x00,0x0C, ++0x21,0x80,0x40,0x00, ++0x27,0x28,0x11,0x00, ++0x24,0x28,0xB0,0x00, ++0x04,0x10,0x53,0x00, ++0x25,0x28,0xA2,0x00, ++0x76,0x46,0x00,0x0C, ++0xFF,0x00,0x84,0x32, ++0x00,0x60,0x92,0x40, ++0x24,0x00,0xBF,0x8F, ++0x20,0x00,0xB4,0x8F, ++0x1C,0x00,0xB3,0x8F, ++0x18,0x00,0xB2,0x8F, ++0x14,0x00,0xB1,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x08,0x00,0xE0,0x03, ++0x28,0x00,0xBD,0x27, ++0x01,0x80,0x03,0x3C, ++0x25,0xB0,0x02,0x3C, ++0x28,0x1E,0x63,0x24, ++0x18,0x03,0x42,0x34, ++0xE0,0xFF,0xBD,0x27, ++0x00,0x00,0x43,0xAC, ++0x18,0x00,0xBF,0xAF, ++0x14,0x00,0xB1,0xAF, ++0x10,0x00,0xB0,0xAF, ++0x0B,0x46,0x00,0x0C, ++0x21,0x88,0xA0,0x00, ++0x21,0x80,0x40,0x00, ++0x9D,0x45,0x00,0x0C, ++0x21,0x20,0x20,0x02, ++0x24,0x80,0x11,0x02, ++0x06,0x10,0x50,0x00, ++0x18,0x00,0xBF,0x8F, ++0x14,0x00,0xB1,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x08,0x00,0xE0,0x03, ++0x20,0x00,0xBD,0x27, ++0xD0,0xFF,0xBD,0x27, ++0x24,0x00,0xB5,0xAF, ++0xFF,0x00,0x84,0x30, ++0x21,0xA8,0xC0,0x00, ++0x28,0x00,0xB6,0xAF, ++0x1C,0x00,0xB3,0xAF, ++0x2C,0x00,0xBF,0xAF, ++0x20,0x00,0xB4,0xAF, ++0x18,0x00,0xB2,0xAF, ++0x14,0x00,0xB1,0xAF, ++0x10,0x00,0xB0,0xAF, ++0x21,0xB0,0xA0,0x00, ++0xE6,0x44,0x00,0x0C, ++0x21,0x98,0x00,0x00, ++0x21,0x00,0xA0,0x16, ++0x80,0x10,0x13,0x00, ++0xDD,0x47,0x00,0x08, ++0x00,0x00,0x00,0x00, ++0xFD,0x00,0x02,0x24, ++0x23,0x00,0x02,0x12, ++0x05,0x00,0x04,0x24, ++0xFC,0x00,0x02,0x24, ++0x37,0x00,0x02,0x12, ++0x00,0x00,0x00,0x00, ++0xFB,0x00,0x02,0x24, ++0x30,0x00,0x02,0x12, ++0x32,0x00,0x04,0x24, ++0xFA,0x00,0x02,0x24, ++0x2D,0x00,0x02,0x12, ++0x05,0x00,0x04,0x24, ++0xF9,0x00,0x02,0x24, ++0x29,0x00,0x02,0x12, ++0x0F,0x00,0x05,0x3C, ++0x04,0x00,0xD1,0x8C, ++0xFF,0xFF,0xA5,0x34, ++0x21,0x20,0x00,0x02, ++0x5F,0x47,0x00,0x0C, ++0x21,0x30,0x20,0x02, ++0x25,0x22,0x00,0x0C, ++0x01,0x00,0x04,0x24, ++0x19,0x00,0x02,0x24, ++0x28,0x00,0x02,0x12, ++0x21,0x90,0x00,0x00, ++0x02,0x00,0x62,0x26, ++0xFF,0x00,0x53,0x30, ++0x2B,0x18,0x75,0x02, ++0x0F,0x00,0x60,0x10, ++0x80,0x10,0x13,0x00, ++0x21,0x30,0x56,0x00, ++0x00,0x00,0xD0,0x8C, ++0xFF,0x00,0x02,0x24, ++0x0A,0x00,0x02,0x12, ++0xFE,0x00,0x02,0x24, ++0xDC,0xFF,0x02,0x16, ++0x32,0x00,0x04,0x24, ++0x25,0x22,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x02,0x00,0x62,0x26, ++0xFF,0x00,0x53,0x30, ++0x2B,0x18,0x75,0x02, ++0xF3,0xFF,0x60,0x14, ++0x80,0x10,0x13,0x00, ++0x2C,0x00,0xBF,0x8F, ++0x28,0x00,0xB6,0x8F, ++0x24,0x00,0xB5,0x8F, ++0x20,0x00,0xB4,0x8F, ++0x1C,0x00,0xB3,0x8F, ++0x18,0x00,0xB2,0x8F, ++0x14,0x00,0xB1,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x01,0x00,0x02,0x24, ++0x08,0x00,0xE0,0x03, ++0x30,0x00,0xBD,0x27, ++0x01,0x00,0x04,0x24, ++0x54,0x22,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0xCB,0x47,0x00,0x08, ++0x02,0x00,0x62,0x26, ++0x25,0x22,0x00,0x0C, ++0x01,0x00,0x04,0x24, ++0xD9,0x47,0x00,0x08, ++0x02,0x00,0x62,0x26, ++0x0F,0x00,0x14,0x3C, ++0x21,0x20,0x00,0x02, ++0x8A,0x47,0x00,0x0C, ++0xFF,0xFF,0x85,0x36, ++0x21,0x20,0x00,0x02, ++0xFF,0xFF,0x85,0x36, ++0xD2,0xFF,0x51,0x10, ++0x21,0x30,0x20,0x02, ++0x5F,0x47,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x25,0x22,0x00,0x0C, ++0x01,0x00,0x04,0x24, ++0x01,0x00,0x42,0x26, ++0xFF,0x00,0x52,0x30, ++0x0A,0x00,0x43,0x2E, ++0xF2,0xFF,0x60,0x14, ++0x21,0x20,0x00,0x02, ++0xE6,0x44,0x00,0x0C, ++0x21,0x20,0x00,0x00, ++0x2C,0x00,0xBF,0x8F, ++0x28,0x00,0xB6,0x8F, ++0x24,0x00,0xB5,0x8F, ++0x20,0x00,0xB4,0x8F, ++0x1C,0x00,0xB3,0x8F, ++0x18,0x00,0xB2,0x8F, ++0x14,0x00,0xB1,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x21,0x10,0x00,0x00, ++0x08,0x00,0xE0,0x03, ++0x30,0x00,0xBD,0x27, ++0xB8,0xFF,0xBD,0x27, ++0x02,0x80,0x02,0x3C, ++0x44,0x00,0xBF,0xAF, ++0x40,0x00,0xBE,0xAF, ++0x3C,0x00,0xB7,0xAF, ++0x38,0x00,0xB6,0xAF, ++0x34,0x00,0xB5,0xAF, ++0x30,0x00,0xB4,0xAF, ++0x2C,0x00,0xB3,0xAF, ++0x28,0x00,0xB2,0xAF, ++0x24,0x00,0xB1,0xAF, ++0x20,0x00,0xB0,0xAF, ++0x30,0x1F,0x57,0x24, ++0x64,0x37,0xE3,0x96, ++0x02,0x80,0x02,0x3C, ++0x02,0x80,0x05,0x3C, ++0x25,0xA0,0x62,0x00, ++0xF0,0xDD,0xA5,0x24, ++0x24,0x00,0x84,0x26, ++0x06,0x00,0x06,0x24, ++0x02,0x80,0x02,0x3C, ++0x20,0x00,0x80,0xA6, ++0x10,0x52,0x00,0x0C, ++0x84,0x58,0x56,0x24, ++0x02,0x80,0x05,0x3C, ++0x18,0x3B,0xA5,0x24, ++0x2A,0x00,0x84,0x26, ++0x10,0x52,0x00,0x0C, ++0x06,0x00,0x06,0x24, ++0x02,0x80,0x05,0x3C, ++0x88,0x58,0xA5,0x24, ++0x06,0x00,0x06,0x24, ++0x10,0x52,0x00,0x0C, ++0x30,0x00,0x84,0x26, ++0x20,0x00,0x83,0x96, ++0x74,0x00,0xD0,0x26, ++0x21,0x20,0x00,0x02, ++0x03,0xFF,0x63,0x30, ++0x80,0x00,0x63,0x34, ++0x20,0x00,0x83,0xA6, ++0x20,0x00,0x1E,0x24, ++0x40,0x00,0x93,0x26, ++0x17,0x4F,0x00,0x0C, ++0x1C,0x00,0xBE,0xAF, ++0x21,0x28,0x40,0x00, ++0x21,0x20,0x60,0x02, ++0x10,0x52,0x00,0x0C, ++0x02,0x00,0x06,0x24, ++0x1C,0x00,0xA2,0x8F, ++0x21,0x20,0x00,0x02, ++0x42,0x00,0x93,0x26, ++0x02,0x00,0x42,0x24, ++0x32,0x4F,0x00,0x0C, ++0x1C,0x00,0xA2,0xAF, ++0x21,0x28,0x40,0x00, ++0x21,0x20,0x60,0x02, ++0x10,0x52,0x00,0x0C, ++0x02,0x00,0x06,0x24, ++0x1C,0x00,0xA2,0x8F, ++0x0C,0x00,0xC6,0x8E, ++0x1C,0x00,0xB0,0x27, ++0x21,0x28,0x00,0x00, ++0x10,0x00,0xC7,0x26, ++0x02,0x00,0x42,0x24, ++0x44,0x00,0x84,0x26, ++0x60,0x00,0xD1,0x26, ++0x1C,0x00,0xA2,0xAF, ++0x41,0x4F,0x00,0x0C, ++0x10,0x00,0xB0,0xAF, ++0x21,0x20,0x20,0x02, ++0x37,0x50,0x00,0x0C, ++0x21,0x98,0x40,0x00, ++0x09,0x00,0x52,0x2C, ++0x08,0x00,0x06,0x24, ++0x21,0x20,0x60,0x02, ++0x0B,0x30,0x52,0x00, ++0x21,0x38,0x20,0x02, ++0x01,0x00,0x05,0x24, ++0x21,0xA8,0x40,0x00, ++0x41,0x4F,0x00,0x0C, ++0x10,0x00,0xB0,0xAF, ++0x21,0x20,0x40,0x00, ++0x03,0x00,0x05,0x24, ++0x01,0x00,0x06,0x24, ++0x48,0x00,0xC7,0x26, ++0x41,0x4F,0x00,0x0C, ++0x10,0x00,0xB0,0xAF, ++0x21,0x20,0x40,0x00, ++0x06,0x00,0x05,0x24, ++0x02,0x00,0x06,0x24, ++0x18,0x00,0xA7,0x27, ++0x18,0x00,0xA0,0xA7, ++0x41,0x4F,0x00,0x0C, ++0x10,0x00,0xB0,0xAF, ++0x18,0x00,0xA5,0x97, ++0x02,0x80,0x04,0x3C, ++0x68,0xDF,0x84,0x24, ++0x2F,0x55,0x00,0x0C, ++0x21,0x98,0x40,0x00, ++0x13,0x00,0x40,0x12, ++0x21,0x20,0x60,0x02, ++0x1C,0x00,0xA2,0x8F, ++0x00,0x00,0x00,0x00, ++0x20,0x00,0x42,0x24, ++0x01,0x01,0x42,0x2C, ++0x18,0x00,0x40,0x14, ++0x21,0x20,0x80,0x02, ++0x44,0x00,0xBF,0x8F, ++0x40,0x00,0xBE,0x8F, ++0x3C,0x00,0xB7,0x8F, ++0x38,0x00,0xB6,0x8F, ++0x34,0x00,0xB5,0x8F, ++0x30,0x00,0xB4,0x8F, ++0x2C,0x00,0xB3,0x8F, ++0x28,0x00,0xB2,0x8F, ++0x24,0x00,0xB1,0x8F, ++0x20,0x00,0xB0,0x8F, ++0x08,0x00,0xE0,0x03, ++0x48,0x00,0xBD,0x27, ++0xF8,0xFF,0xA6,0x26, ++0x68,0x00,0xC7,0x26, ++0x32,0x00,0x05,0x24, ++0x41,0x4F,0x00,0x0C, ++0x10,0x00,0xB0,0xAF, ++0x1C,0x00,0xA2,0x8F, ++0x00,0x00,0x00,0x00, ++0x20,0x00,0x42,0x24, ++0x01,0x01,0x42,0x2C, ++0xEA,0xFF,0x40,0x10, ++0x21,0x20,0x80,0x02, ++0x21,0x28,0x00,0x00, ++0x08,0x52,0x00,0x0C, ++0x08,0x00,0x06,0x24, ++0x08,0x00,0x84,0x8E, ++0x04,0x00,0x85,0x8E, ++0xFF,0xDF,0x02,0x3C, ++0x10,0x00,0x86,0x8E, ++0x14,0x00,0x87,0x8E, ++0xFF,0xFF,0x42,0x34, ++0x1C,0x00,0xA8,0x8F, ++0x24,0x20,0x82,0x00, ++0x00,0x40,0x03,0x3C, ++0xFF,0xE0,0x02,0x24, ++0x24,0x28,0xA2,0x00, ++0x25,0x20,0x83,0x00, ++0x00,0x80,0x02,0x3C, ++0xFF,0x81,0x03,0x24, ++0x24,0x38,0xE3,0x00, ++0x25,0x30,0xC2,0x00, ++0x00,0x10,0xA5,0x34, ++0x80,0x00,0x84,0x34, ++0x08,0x00,0x84,0xAE, ++0x00,0x00,0x88,0xA6, ++0x02,0x00,0x9E,0xA2, ++0x14,0x00,0x87,0xAE, ++0x04,0x00,0x85,0xAE, ++0x10,0x00,0x86,0xAE, ++0xF8,0x36,0xE6,0x8E, ++0x64,0x37,0xE5,0x8E, ++0x01,0x00,0x04,0x24, ++0x00,0x01,0x07,0x24, ++0x01,0x00,0x02,0x24, ++0x73,0x01,0x00,0x0C, ++0x10,0x00,0xA2,0xAF, ++0xB0,0x01,0x00,0x0C, ++0x01,0x00,0x04,0x24, ++0x44,0x00,0xBF,0x8F, ++0x40,0x00,0xBE,0x8F, ++0x3C,0x00,0xB7,0x8F, ++0x38,0x00,0xB6,0x8F, ++0x34,0x00,0xB5,0x8F, ++0x30,0x00,0xB4,0x8F, ++0x2C,0x00,0xB3,0x8F, ++0x28,0x00,0xB2,0x8F, ++0x24,0x00,0xB1,0x8F, ++0x20,0x00,0xB0,0x8F, ++0x08,0x00,0xE0,0x03, ++0x48,0x00,0xBD,0x27, ++0xE8,0xFF,0xBD,0x27, ++0x10,0x00,0xB0,0xAF, ++0x14,0x00,0xBF,0xAF, ++0x25,0x24,0x00,0x0C, ++0x24,0x00,0x04,0x24, ++0x21,0x30,0x40,0x00, ++0x02,0x80,0x05,0x3C, ++0x02,0x80,0x02,0x3C, ++0x30,0x1F,0x50,0x24, ++0x21,0x20,0xC0,0x00, ++0x13,0x00,0xC0,0x10, ++0x48,0xEA,0xA5,0x24, ++0x04,0x00,0x02,0x24, ++0x09,0x00,0x03,0x24, ++0x0C,0x00,0xC2,0xAC, ++0x14,0x00,0xC3,0xAC, ++0x08,0x00,0xC5,0x94, ++0xA4,0x3B,0x03,0x8E, ++0x02,0x80,0x02,0x3C, ++0x25,0x28,0xA2,0x00, ++0x30,0x09,0x00,0x0C, ++0x20,0x00,0xA3,0xAC, ++0xA8,0x3B,0x06,0x8E, ++0xA4,0x3B,0x05,0x8E, ++0x02,0x80,0x04,0x3C, ++0x14,0x00,0xBF,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x80,0xDF,0x84,0x24, ++0x2F,0x55,0x00,0x08, ++0x18,0x00,0xBD,0x27, ++0x02,0x80,0x04,0x3C, ++0x14,0x00,0xBF,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x74,0xDF,0x84,0x24, ++0x2F,0x55,0x00,0x08, ++0x18,0x00,0xBD,0x27, ++0xD8,0xFF,0xBD,0x27, ++0x18,0x00,0xB2,0xAF, ++0x14,0x00,0xB1,0xAF, ++0x10,0x00,0xB0,0xAF, ++0x24,0x00,0xBF,0xAF, ++0x20,0x00,0xB4,0xAF, ++0x1C,0x00,0xB3,0xAF, ++0x02,0x00,0x82,0x90, ++0x02,0x80,0x12,0x3C, ++0x30,0x1F,0x51,0x26, ++0xB0,0x1B,0x25,0x96, ++0x0F,0x00,0x42,0x30, ++0xC0,0x10,0x02,0x00, ++0x21,0x80,0x44,0x00, ++0x00,0x01,0xA3,0x30, ++0x04,0x00,0x60,0x10, ++0x18,0x00,0x04,0x26, ++0x00,0x10,0xA2,0x30, ++0x0B,0x00,0x40,0x10, ++0x04,0x00,0xA2,0x30, ++0x21,0x18,0x00,0x00, ++0x24,0x00,0xBF,0x8F, ++0x20,0x00,0xB4,0x8F, ++0x1C,0x00,0xB3,0x8F, ++0x18,0x00,0xB2,0x8F, ++0x14,0x00,0xB1,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x21,0x10,0x60,0x00, ++0x08,0x00,0xE0,0x03, ++0x28,0x00,0xBD,0x27, ++0xF5,0xFF,0x40,0x14, ++0x00,0x00,0x00,0x00, ++0x55,0x50,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x02,0x80,0x04,0x3C, ++0x18,0x3B,0x84,0x24, ++0x21,0x28,0x40,0x00, ++0x39,0x52,0x00,0x0C, ++0x06,0x00,0x06,0x24, ++0xED,0xFF,0x40,0x14, ++0x21,0x18,0x00,0x00, ++0x02,0x80,0x02,0x3C, ++0x88,0x58,0x53,0x24, ++0x22,0x00,0x14,0x26, ++0x21,0x20,0x80,0x02, ++0x21,0x28,0x60,0x02, ++0x39,0x52,0x00,0x0C, ++0x06,0x00,0x06,0x24, ++0xE4,0xFF,0x40,0x14, ++0x21,0x18,0x00,0x00, ++0x28,0x00,0x04,0x26, ++0x21,0x28,0x60,0x02, ++0x39,0x52,0x00,0x0C, ++0x06,0x00,0x06,0x24, ++0xDE,0xFF,0x40,0x14, ++0x21,0x18,0x00,0x00, ++0x02,0x80,0x04,0x3C, ++0x2F,0x55,0x00,0x0C, ++0xE8,0xDF,0x84,0x24, ++0xB0,0x1B,0x24,0x96, ++0x00,0x00,0x00,0x00, ++0xFF,0xFF,0x83,0x30, ++0x01,0x00,0x62,0x30, ++0x08,0x00,0x40,0x10, ++0x00,0x20,0x62,0x30, ++0x15,0x00,0x40,0x10, ++0xFF,0xDE,0x82,0x30, ++0xFE,0xFF,0x04,0x24, ++0xB0,0x1B,0x22,0xA6, ++0xD0,0x38,0x20,0xAE, ++0x48,0x0E,0x00,0x0C, ++0xB4,0x38,0x20,0xAE, ++0x25,0xB0,0x02,0x3C, ++0x30,0x1F,0x50,0x26, ++0x4C,0x00,0x42,0x34, ++0x00,0x00,0x40,0xA0, ++0x21,0x20,0x00,0x00, ++0x21,0x28,0x00,0x00, ++0x12,0x0D,0x00,0x0C, ++0xA1,0x3B,0x00,0xA2, ++0x10,0x3E,0x00,0xAE, ++0xEC,0x38,0x00,0xAE, ++0x08,0x39,0x00,0xAE, ++0xA3,0x51,0x00,0x0C, ++0x50,0x3E,0x00,0xAE, ++0xFA,0x48,0x00,0x08, ++0x21,0x18,0x00,0x00, ++0x76,0x0E,0x00,0x0C, ++0x21,0x20,0x80,0x02, ++0xBB,0xFF,0x40,0x14, ++0xFF,0xFF,0x03,0x24, ++0xB0,0x1B,0x22,0x96, ++0x00,0x00,0x00,0x00, ++0xFF,0xFE,0x42,0x30, ++0x2D,0x49,0x00,0x08, ++0xB0,0x1B,0x22,0xA6, ++0xD0,0xFF,0xBD,0x27, ++0x20,0x00,0xB4,0xAF, ++0x02,0x80,0x14,0x3C, ++0x14,0x00,0xB1,0xAF, ++0x28,0x00,0xBF,0xAF, ++0x24,0x00,0xB5,0xAF, ++0x1C,0x00,0xB3,0xAF, ++0x18,0x00,0xB2,0xAF, ++0x10,0x00,0xB0,0xAF, ++0x30,0x1F,0x91,0x26, ++0xB0,0x1B,0x23,0x96, ++0x00,0x00,0x00,0x00, ++0x10,0x00,0x62,0x30, ++0x3A,0x00,0x40,0x14, ++0x00,0x01,0x62,0x30, ++0x2E,0x00,0x40,0x10, ++0x00,0x10,0x62,0x30, ++0x29,0x00,0x40,0x14, ++0x01,0x00,0x62,0x30, ++0x1D,0x00,0x40,0x14, ++0x04,0x00,0x62,0x30, ++0x25,0x00,0x40,0x10, ++0x02,0x80,0x02,0x3C, ++0x21,0x90,0x20,0x02, ++0x2B,0x3D,0x55,0x24, ++0x01,0x00,0x13,0x24, ++0xF0,0x00,0x10,0x24, ++0x65,0x49,0x00,0x08, ++0x19,0x00,0x11,0x24, ++0xFF,0xFF,0x31,0x26, ++0x1C,0x00,0x20,0x06, ++0x28,0x00,0x10,0x26, ++0x21,0x18,0x12,0x02, ++0xFA,0x1D,0x62,0x90, ++0x00,0x00,0x00,0x00, ++0xF9,0xFF,0x53,0x14, ++0x00,0x00,0x00,0x00, ++0x0C,0x1E,0x62,0x8C, ++0x00,0x00,0x00,0x00, ++0x33,0x00,0x40,0x10, ++0x21,0x20,0x15,0x02, ++0x00,0x60,0x02,0x40, ++0x01,0x00,0x41,0x34, ++0x01,0x00,0x21,0x38, ++0x00,0x60,0x81,0x40, ++0x0C,0x1E,0x60,0xAC, ++0x00,0x60,0x82,0x40, ++0x63,0x49,0x00,0x08, ++0xFF,0xFF,0x31,0x26, ++0xD4,0x1E,0x22,0x8E, ++0x00,0x00,0x00,0x00, ++0x2F,0x00,0x40,0x10, ++0x02,0x80,0x04,0x3C, ++0x00,0x60,0x02,0x40, ++0x01,0x00,0x41,0x34, ++0x01,0x00,0x21,0x38, ++0x00,0x60,0x81,0x40, ++0xD4,0x1E,0x20,0xAE, ++0x00,0x60,0x82,0x40, ++0x53,0x1E,0x00,0x0C, ++0x30,0x1F,0x90,0x26, ++0xEC,0x38,0x02,0xAE, ++0x28,0x00,0xBF,0x8F, ++0x24,0x00,0xB5,0x8F, ++0x20,0x00,0xB4,0x8F, ++0x1C,0x00,0xB3,0x8F, ++0x18,0x00,0xB2,0x8F, ++0x14,0x00,0xB1,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x21,0x10,0x00,0x00, ++0x08,0x00,0xE0,0x03, ++0x30,0x00,0xBD,0x27, ++0x02,0x80,0x04,0x3C, ++0x2F,0x55,0x00,0x0C, ++0xF8,0xDF,0x84,0x24, ++0xB0,0x1B,0x22,0x96, ++0xEC,0x38,0x20,0xAE, ++0xFD,0xFF,0x04,0x24, ++0xEF,0xDF,0x42,0x30, ++0x48,0x0E,0x00,0x0C, ++0xB0,0x1B,0x22,0xA6, ++0x28,0x00,0xBF,0x8F, ++0x24,0x00,0xB5,0x8F, ++0x20,0x00,0xB4,0x8F, ++0x1C,0x00,0xB3,0x8F, ++0x18,0x00,0xB2,0x8F, ++0x14,0x00,0xB1,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x21,0x10,0x00,0x00, ++0x08,0x00,0xE0,0x03, ++0x30,0x00,0xBD,0x27, ++0x8E,0x3E,0x42,0x92, ++0x00,0x00,0x00,0x00, ++0xFF,0xFF,0x42,0x24, ++0x8E,0x3E,0x42,0xA2, ++0x76,0x0E,0x00,0x0C, ++0xFA,0x1D,0x60,0xA0, ++0x63,0x49,0x00,0x08, ++0xFF,0xFF,0x31,0x26, ++0x2F,0x55,0x00,0x0C, ++0x18,0xE0,0x84,0x24, ++0xB0,0x1B,0x23,0x96, ++0x25,0xB0,0x02,0x3C, ++0x4C,0x00,0x42,0x34, ++0xFE,0xFE,0x63,0x30, ++0xB0,0x1B,0x23,0xA6, ++0x21,0x20,0x00,0x00, ++0x00,0x00,0x40,0xA0, ++0x21,0x28,0x00,0x00, ++0xA1,0x3B,0x20,0xA2, ++0x12,0x0D,0x00,0x0C, ++0xC2,0x1E,0x20,0xA2, ++0x02,0x80,0x04,0x3C, ++0x76,0x0E,0x00,0x0C, ++0x88,0x58,0x84,0x24, ++0x83,0x49,0x00,0x08, ++0x00,0x00,0x00,0x00, ++0x08,0x00,0xE0,0x03, ++0x21,0x10,0x00,0x00, ++0xA8,0xFF,0xBD,0x27, ++0x48,0x00,0xB6,0xAF, ++0x3C,0x00,0xB3,0xAF, ++0x38,0x00,0xB2,0xAF, ++0x30,0x00,0xB0,0xAF, ++0x54,0x00,0xBF,0xAF, ++0x50,0x00,0xBE,0xAF, ++0x4C,0x00,0xB7,0xAF, ++0x44,0x00,0xB5,0xAF, ++0x40,0x00,0xB4,0xAF, ++0x34,0x00,0xB1,0xAF, ++0x02,0x00,0x82,0x90, ++0x00,0x00,0x83,0x8C, ++0x21,0xB0,0x00,0x00, ++0x0F,0x00,0x42,0x30, ++0xC0,0x10,0x02,0x00, ++0x21,0x80,0x44,0x00, ++0x18,0x00,0x12,0x26, ++0x21,0x20,0x40,0x02, ++0x55,0x50,0x00,0x0C, ++0xFF,0x3F,0x73,0x30, ++0x02,0x80,0x04,0x3C, ++0x18,0x3B,0x84,0x24, ++0x21,0x28,0x40,0x00, ++0x39,0x52,0x00,0x0C, ++0x06,0x00,0x06,0x24, ++0x0B,0x00,0x40,0x14, ++0x02,0x80,0x15,0x3C, ++0x30,0x1F,0xB1,0x26, ++0xB0,0x1B,0x23,0x96, ++0x00,0x00,0x00,0x00, ++0x01,0x00,0x62,0x30, ++0x05,0x00,0x40,0x10, ++0x00,0x10,0x62,0x30, ++0x03,0x00,0x40,0x14, ++0x00,0x01,0x62,0x30, ++0x0E,0x00,0x40,0x10, ++0x20,0x00,0xB4,0x27, ++0x54,0x00,0xBF,0x8F, ++0x50,0x00,0xBE,0x8F, ++0x4C,0x00,0xB7,0x8F, ++0x48,0x00,0xB6,0x8F, ++0x44,0x00,0xB5,0x8F, ++0x40,0x00,0xB4,0x8F, ++0x3C,0x00,0xB3,0x8F, ++0x38,0x00,0xB2,0x8F, ++0x34,0x00,0xB1,0x8F, ++0x30,0x00,0xB0,0x8F, ++0x21,0x10,0x00,0x00, ++0x08,0x00,0xE0,0x03, ++0x58,0x00,0xBD,0x27, ++0x32,0x00,0x05,0x26, ++0x21,0x20,0x80,0x02, ++0x10,0x52,0x00,0x0C, ++0x02,0x00,0x06,0x24, ++0x20,0x00,0xA5,0x97, ++0x00,0x00,0x00,0x00, ++0xC2,0x00,0xA0,0x14, ++0x02,0x80,0x04,0x3C, ++0x21,0x20,0x80,0x02, ++0x34,0x00,0x05,0x26, ++0x10,0x52,0x00,0x0C, ++0x02,0x00,0x06,0x24, ++0x20,0x00,0xA2,0x97, ++0x21,0x20,0x80,0x02, ++0x30,0x00,0x05,0x26, ++0xFF,0x3F,0x42,0x30, ++0x02,0x00,0x06,0x24, ++0x50,0x39,0x22,0xA6, ++0x10,0x52,0x00,0x0C, ++0x28,0x00,0xA2,0xAF, ++0x20,0x00,0xA3,0x97, ++0x21,0x40,0x20,0x02, ++0x00,0x04,0x63,0x30, ++0x02,0x00,0x60,0x14, ++0x09,0x00,0x02,0x24, ++0x14,0x00,0x02,0x24, ++0x1E,0x00,0x5E,0x26, ++0xE2,0xFF,0x74,0x26, ++0x21,0x20,0xC0,0x03, ++0x01,0x00,0x05,0x24, ++0x24,0x00,0xA6,0x27, ++0x21,0x38,0x80,0x02, ++0x55,0x1D,0x00,0x0C, ++0x0C,0x3E,0x02,0xA1, ++0xA8,0x00,0x40,0x10, ++0x02,0x00,0x45,0x24, ++0x24,0x00,0xA6,0x8F, ++0x10,0x52,0x00,0x0C, ++0x10,0x00,0xA4,0x27, ++0x21,0x20,0xC0,0x03, ++0x32,0x00,0x05,0x24, ++0x24,0x00,0xA6,0x27, ++0x24,0x00,0xB7,0x8F, ++0x55,0x1D,0x00,0x0C, ++0x21,0x38,0x80,0x02, ++0x08,0x00,0x40,0x10, ++0x10,0x00,0xA4,0x27, ++0x24,0x00,0xA6,0x8F, ++0x21,0x20,0x97,0x00, ++0x10,0x52,0x00,0x0C, ++0x02,0x00,0x45,0x24, ++0x24,0x00,0xA3,0x8F, ++0x00,0x00,0x00,0x00, ++0x21,0xB8,0xE3,0x02, ++0x02,0x80,0x02,0x3C, ++0xEA,0x5D,0x44,0x90, ++0x02,0x00,0x03,0x24, ++0xE5,0x00,0x83,0x10, ++0x21,0x20,0xC0,0x03, ++0x30,0x1F,0xA4,0x26, ++0x10,0x3E,0x82,0x8C, ++0x00,0x00,0x00,0x00, ++0x22,0x00,0x40,0x10, ++0x30,0x1F,0xB1,0x26, ++0x02,0x80,0x02,0x3C, ++0xE6,0x5D,0x43,0x90, ++0x00,0x00,0x00,0x00, ++0x1D,0x00,0x60,0x14, ++0x23,0x10,0xD2,0x03, ++0x2B,0x10,0x53,0x00, ++0x1A,0x00,0x40,0x10, ++0x21,0x80,0xC0,0x03, ++0x02,0x80,0x11,0x3C, ++0x21,0x20,0x00,0x02, ++0xDD,0x00,0x05,0x24, ++0x24,0x00,0xA6,0x27, ++0x55,0x1D,0x00,0x0C, ++0x21,0x38,0x80,0x02, ++0x21,0x80,0x40,0x00, ++0x02,0x00,0x44,0x24, ++0xC8,0xDD,0x25,0x26, ++0x0E,0x01,0x40,0x10, ++0x06,0x00,0x06,0x24, ++0x39,0x52,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x10,0x01,0x40,0x10, ++0x00,0x00,0x00,0x00, ++0x24,0x00,0xA2,0x8F, ++0x00,0x00,0x00,0x00, ++0x21,0x18,0x02,0x02, ++0x02,0x00,0x70,0x24, ++0x23,0x20,0x12,0x02, ++0x03,0x01,0x40,0x10, ++0x2B,0x20,0x93,0x00, ++0xEB,0xFF,0x80,0x14, ++0x21,0x20,0x00,0x02, ++0x30,0x1F,0xB1,0x26, ++0x50,0x3E,0x22,0x8E, ++0x00,0x00,0x00,0x00, ++0x6A,0x00,0x40,0x14, ++0x24,0x00,0xA6,0x27, ++0x53,0x1E,0x00,0x0C, ++0x30,0x1F,0xB2,0x26, ++0x25,0xB0,0x14,0x3C, ++0xB0,0x1B,0x45,0x96, ++0x02,0x00,0x03,0x24, ++0x4C,0x00,0x84,0x36, ++0x00,0x00,0x83,0xA0, ++0xEC,0x38,0x42,0xAE, ++0x02,0x00,0x02,0x3C, ++0x00,0x01,0xA5,0x34, ++0x20,0xBF,0x42,0x34, ++0x08,0x39,0x42,0xAE, ++0x21,0x0E,0x00,0x0C, ++0xB0,0x1B,0x45,0xA6, ++0x10,0x00,0xA4,0x27, ++0x7D,0x50,0x00,0x0C, ++0x21,0x28,0xE0,0x02, ++0x0F,0x00,0x50,0x30, ++0x10,0x00,0xA4,0x27, ++0x96,0x50,0x00,0x0C, ++0x21,0x28,0xE0,0x02, ++0x40,0x02,0x13,0x36, ++0x02,0x80,0x04,0x3C, ++0x21,0x88,0x40,0x00, ++0x21,0x30,0x40,0x00, ++0x21,0x28,0x60,0x02, ++0x2F,0x55,0x00,0x0C, ++0x6C,0xE0,0x84,0x24, ++0x21,0x20,0x60,0x02, ++0xC1,0x5B,0x00,0x0C, ++0x21,0x28,0x20,0x02, ++0x21,0x28,0xE0,0x02, ++0xC2,0x50,0x00,0x0C, ++0x10,0x00,0xA4,0x27, ++0x21,0x88,0x40,0x00, ++0x50,0x3E,0x42,0x8E, ++0x00,0x00,0x00,0x00, ++0x16,0x00,0x40,0x10, ++0x50,0x00,0x13,0x36, ++0x5B,0x3E,0x42,0x92, ++0x5C,0x3E,0x43,0x92, ++0x0A,0x3E,0x44,0x92, ++0x00,0x13,0x02,0x00, ++0x00,0x1D,0x03,0x00, ++0x25,0x10,0x43,0x00, ++0x04,0x00,0x03,0x24, ++0xA0,0x00,0x83,0x10, ++0x25,0x88,0x22,0x02, ++0x54,0x3E,0x43,0x8E, ++0x00,0x00,0x00,0x00, ++0x07,0x00,0x60,0x14, ++0x01,0x00,0x02,0x24, ++0x58,0x3E,0x42,0x96, ++0x00,0x00,0x00,0x00, ++0x20,0x00,0x42,0x30, ++0xA1,0x00,0x40,0x14, ++0x00,0x10,0x02,0x3C, ++0x01,0x00,0x02,0x24, ++0x98,0x00,0x62,0x10, ++0x00,0x00,0x00,0x00, ++0x02,0x80,0x04,0x3C, ++0x80,0xE0,0x84,0x24, ++0x21,0x28,0x60,0x02, ++0x21,0x38,0xC0,0x02, ++0x2F,0x55,0x00,0x0C, ++0x21,0x30,0x20,0x02, ++0x21,0x20,0x60,0x02, ++0xC1,0x5B,0x00,0x0C, ++0x21,0x28,0x20,0x02, ++0x30,0x1F,0xA2,0x26, ++0xB0,0x1B,0x43,0x94, ++0x0A,0x3E,0x44,0x90, ++0xB4,0x38,0x40,0xAC, ++0xFF,0xDF,0x63,0x30, ++0xB0,0x1B,0x43,0xA4, ++0x04,0x00,0x03,0x24, ++0xD0,0x38,0x40,0xAC, ++0x94,0x3E,0x40,0xAC, ++0x06,0x00,0x83,0x10, ++0x98,0x3E,0x40,0xAC, ++0x28,0x00,0xA4,0x8F, ++0x48,0x0E,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0xE2,0x49,0x00,0x08, ++0x00,0x00,0x00,0x00, ++0x25,0xB0,0x06,0x3C, ++0x64,0x03,0xC6,0x34, ++0x30,0x1F,0xA4,0x8E, ++0x00,0x00,0xC5,0x90, ++0x0F,0xFF,0x02,0x24, ++0xFD,0xFF,0x03,0x24, ++0x24,0x20,0x82,0x00, ++0x24,0x28,0xA3,0x00, ++0x30,0x1F,0xA4,0xAE, ++0x00,0x00,0xC5,0xA0, ++0x28,0x00,0xA4,0x8F, ++0x48,0x0E,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0xE2,0x49,0x00,0x08, ++0x00,0x00,0x00,0x00, ++0x2F,0x55,0x00,0x0C, ++0x50,0xE0,0x84,0x24, ++0xFF,0xFF,0x02,0x24, ++0x99,0x4A,0x00,0x08, ++0x28,0x00,0xA2,0xAF, ++0x21,0x20,0xC0,0x03, ++0x2D,0x00,0x05,0x24, ++0x55,0x1D,0x00,0x0C, ++0x21,0x38,0x80,0x02, ++0x91,0x00,0x40,0x10, ++0x00,0x00,0x00,0x00, ++0x24,0x00,0xAB,0x8F, ++0x00,0x00,0x00,0x00, ++0x1F,0x00,0x60,0x19, ++0x21,0x40,0x00,0x00, ++0x02,0x00,0x49,0x24, ++0x21,0x50,0x20,0x02, ++0x02,0x00,0x0C,0x24, ++0xD5,0x4A,0x00,0x08, ++0x21,0x68,0x20,0x01, ++0x58,0x3E,0x82,0x90, ++0x00,0x00,0x23,0x91, ++0x00,0x00,0x00,0x00, ++0x24,0x10,0x43,0x00, ++0x58,0x3E,0x82,0xA0, ++0x01,0x00,0x08,0x25, ++0x2A,0x10,0x0B,0x01, ++0x11,0x00,0x40,0x10, ++0x01,0x00,0x29,0x25, ++0xF6,0xFF,0x0C,0x15, ++0x21,0x20,0x0A,0x01, ++0x5A,0x3E,0x43,0x91, ++0x00,0x00,0x25,0x91, ++0x02,0x00,0xA2,0x91, ++0x1C,0x00,0x64,0x30, ++0x1C,0x00,0xA5,0x30, ++0x03,0x00,0x42,0x30, ++0x03,0x00,0x63,0x30, ++0x2A,0x30,0x43,0x00, ++0x2A,0x38,0xA4,0x00, ++0x0A,0x10,0x66,0x00, ++0x0A,0x20,0xA7,0x00, ++0x25,0x10,0x44,0x00, ++0xD1,0x4A,0x00,0x08, ++0x5A,0x3E,0x42,0xA1, ++0x02,0x80,0x02,0x3C, ++0xDE,0x5D,0x43,0x90, ++0x02,0x80,0x02,0x3C, ++0x3C,0xE3,0x47,0x24, ++0x10,0x00,0x65,0x30, ++0x02,0x80,0x02,0x3C, ++0x02,0x80,0x03,0x3C, ++0x4C,0xE3,0x66,0x24, ++0x30,0x1F,0x44,0x24, ++0xF8,0x4A,0x00,0x08, ++0x21,0x40,0x00,0x00, ++0x00,0x00,0x43,0x90, ++0x5B,0x3E,0x82,0x90, ++0x01,0x00,0x08,0x25, ++0x24,0x10,0x43,0x00, ++0x5B,0x3E,0x82,0xA0, ++0x10,0x00,0x02,0x29, ++0x07,0x00,0x40,0x10, ++0x01,0x00,0x84,0x24, ++0x21,0x10,0x07,0x01, ++0xF6,0xFF,0xA0,0x14, ++0x21,0x18,0x06,0x01, ++0x00,0x00,0x63,0x90, ++0xF1,0x4A,0x00,0x08, ++0x00,0x00,0x00,0x00, ++0x21,0x20,0xC0,0x03, ++0x21,0x38,0x80,0x02, ++0x3D,0x00,0x05,0x24, ++0x55,0x1D,0x00,0x0C, ++0x24,0x00,0xA6,0x27, ++0x48,0x00,0x40,0x10, ++0x00,0x00,0x00,0x00, ++0x24,0x00,0xA6,0x8F, ++0x02,0x80,0x04,0x3C, ++0xA8,0x5D,0x84,0x24, ++0x10,0x52,0x00,0x0C, ++0x02,0x00,0x45,0x24, ++0x90,0x0D,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x54,0x4A,0x00,0x08, ++0x00,0x00,0x00,0x00, ++0x2A,0x00,0x05,0x24, ++0x24,0x00,0xA6,0x27, ++0x55,0x1D,0x00,0x0C, ++0x21,0x38,0x80,0x02, ++0x30,0x00,0x40,0x10, ++0x30,0x1F,0xA5,0x26, ++0x02,0x00,0x42,0x90, ++0x00,0x00,0x00,0x00, ++0x02,0x00,0x42,0x30, ++0x2B,0x00,0x40,0x10, ++0x02,0x80,0x02,0x3C, ++0xEB,0x5D,0x44,0x90, ++0x01,0x00,0x03,0x24, ++0x3E,0x00,0x83,0x10, ++0x30,0x1F,0xA2,0x26, ++0x10,0x23,0x43,0x8C, ++0xFF,0xEF,0x04,0x24, ++0x00,0x08,0x63,0x34, ++0x24,0x18,0x64,0x00, ++0x2A,0x4A,0x00,0x08, ++0x10,0x23,0x43,0xAC, ++0xF6,0x01,0x82,0x36, ++0x00,0x00,0x40,0xA4, ++0x91,0x4A,0x00,0x08, ++0x02,0x80,0x04,0x3C, ++0x58,0x3E,0x42,0x96, ++0x00,0x00,0x00,0x00, ++0x40,0x00,0x42,0x30, ++0x66,0xFF,0x40,0x10, ++0x02,0x80,0x04,0x3C, ++0x00,0x10,0x02,0x3C, ++0x25,0x88,0x22,0x02, ++0x0F,0x00,0x08,0x24, ++0x01,0x00,0x03,0x24, ++0x0C,0x00,0x02,0x25, ++0x04,0x10,0x43,0x00, ++0x24,0x10,0x51,0x00, ++0x16,0x00,0x40,0x14, ++0x00,0x00,0x00,0x00, ++0xFF,0xFF,0x08,0x25, ++0xFA,0xFF,0x01,0x05, ++0x0C,0x00,0x02,0x25, ++0x00,0x12,0x16,0x00, ++0x00,0x1B,0x16,0x00, ++0x25,0x18,0x62,0x00, ++0x00,0x21,0x16,0x00, ++0x25,0x18,0x64,0x00, ++0x25,0xB0,0x02,0x3C, ++0x25,0x18,0x76,0x00, ++0xF6,0x01,0x42,0x34, ++0x00,0x00,0x43,0xA4, ++0x91,0x4A,0x00,0x08, ++0x02,0x80,0x04,0x3C, ++0x10,0x23,0xA2,0x8C, ++0xFF,0xF7,0x03,0x24, ++0xFF,0xEF,0x04,0x24, ++0x24,0x10,0x43,0x00, ++0x24,0x10,0x44,0x00, ++0x2A,0x4A,0x00,0x08, ++0x10,0x23,0xA2,0xAC, ++0x38,0x4B,0x00,0x08, ++0xFF,0x00,0x16,0x31, ++0x30,0x1F,0xA2,0x26, ++0x54,0x4A,0x00,0x08, ++0x50,0x3E,0x40,0xAC, ++0x02,0x80,0x02,0x3C, ++0x30,0x1F,0x42,0x24, ++0x4F,0x4A,0x00,0x08, ++0x10,0x3E,0x40,0xAC, ++0x54,0x4A,0x00,0x08, ++0x50,0x3E,0x20,0xAE, ++0x21,0x20,0x00,0x02, ++0x78,0x0F,0x00,0x0C, ++0x21,0x28,0x00,0x00, ++0x50,0x4A,0x00,0x08, ++0x30,0x1F,0xB1,0x26, ++0x10,0x23,0x43,0x8C, ++0xFF,0xF7,0x04,0x24, ++0x24,0x18,0x64,0x00, ++0x00,0x10,0x63,0x34, ++0x2A,0x4A,0x00,0x08, ++0x10,0x23,0x43,0xAC, ++0xD8,0xFF,0xBD,0x27, ++0x1C,0x00,0xB1,0xAF, ++0x18,0x00,0xB0,0xAF, ++0x20,0x00,0xBF,0xAF, ++0x02,0x00,0x82,0x90, ++0x02,0x80,0x03,0x3C, ++0xE0,0x3A,0x65,0x94, ++0x0F,0x00,0x42,0x30, ++0x00,0x00,0x83,0x8C, ++0xC0,0x10,0x02,0x00, ++0x21,0x20,0x44,0x00, ++0x00,0x10,0xA8,0x30, ++0x02,0x80,0x02,0x3C, ++0x00,0x08,0xA5,0x30, ++0x84,0x58,0x51,0x24, ++0xFF,0x3F,0x63,0x30, ++0x06,0x00,0xA0,0x10, ++0x18,0x00,0x90,0x24, ++0xE8,0xFF,0x67,0x24, ++0x30,0x00,0x84,0x24, ++0x21,0x28,0x00,0x00, ++0x07,0x00,0x00,0x11, ++0x10,0x00,0xA6,0x27, ++0x20,0x00,0xBF,0x8F, ++0x1C,0x00,0xB1,0x8F, ++0x18,0x00,0xB0,0x8F, ++0x21,0x10,0x00,0x00, ++0x08,0x00,0xE0,0x03, ++0x28,0x00,0xBD,0x27, ++0x55,0x1D,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0xF7,0xFF,0x40,0x10, ++0x00,0x00,0x00,0x00, ++0x02,0x00,0x44,0x24, ++0x10,0x00,0xA2,0x8F, ++0x00,0x00,0x00,0x00, ++0x06,0x00,0x40,0x10, ++0x10,0x00,0x25,0x26, ++0x0C,0x00,0x26,0x8E, ++0x39,0x52,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0xED,0xFF,0x40,0x14, ++0x00,0x00,0x00,0x00, ++0x42,0x50,0x00,0x0C, ++0x21,0x20,0x00,0x02, ++0x01,0x10,0x00,0x0C, ++0x21,0x20,0x40,0x00, ++0x77,0x4B,0x00,0x08, ++0x00,0x00,0x00,0x00, ++0x08,0x00,0xE0,0x03, ++0x21,0x10,0x00,0x00, ++0xE8,0xFF,0xBD,0x27, ++0x10,0x00,0xBF,0xAF, ++0xE5,0x48,0x00,0x0C, ++0xFE,0xFF,0x05,0x24, ++0x10,0x00,0xBF,0x8F, ++0x21,0x10,0x00,0x00, ++0x08,0x00,0xE0,0x03, ++0x18,0x00,0xBD,0x27, ++0xE8,0xFF,0xBD,0x27, ++0x10,0x00,0xBF,0xAF, ++0xE5,0x48,0x00,0x0C, ++0xFF,0xFF,0x05,0x24, ++0x10,0x00,0xBF,0x8F, ++0x21,0x10,0x00,0x00, ++0x08,0x00,0xE0,0x03, ++0x18,0x00,0xBD,0x27, ++0x25,0xB0,0x03,0x3C, ++0x01,0x80,0x02,0x3C, ++0xB0,0x03,0x65,0x34, ++0x8C,0x2E,0x42,0x24, ++0x18,0x03,0x63,0x34, ++0x00,0x00,0x62,0xAC, ++0x00,0x00,0xA4,0xAC, ++0x00,0x00,0x83,0x8C, ++0x21,0x10,0x00,0x00, ++0xFF,0x3F,0x63,0x30, ++0x00,0x00,0xA3,0xAC, ++0x08,0x00,0xE0,0x03, ++0x00,0x00,0x00,0x00, ++0xE8,0xFF,0xBD,0x27, ++0x02,0x80,0x02,0x3C, ++0x10,0x00,0xB0,0xAF, ++0x14,0x00,0xBF,0xAF, ++0x30,0x1F,0x50,0x24, ++0x70,0x3D,0x03,0x8E, ++0xFE,0xFF,0x04,0x24, ++0x01,0x00,0x63,0x24, ++0x05,0x00,0x62,0x2C, ++0x12,0x00,0x40,0x10, ++0x70,0x3D,0x03,0xAE, ++0xB0,0x1B,0x02,0x96, ++0x00,0x00,0x00,0x00, ++0x00,0x01,0x42,0x30, ++0x05,0x00,0x40,0x10, ++0x00,0x00,0x00,0x00, ++0x14,0x00,0xBF,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x08,0x00,0xE0,0x03, ++0x18,0x00,0xBD,0x27, ++0xA5,0x12,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0xC8,0x00,0x03,0x24, ++0xD0,0x38,0x03,0xAE, ++0x14,0x00,0xBF,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x08,0x00,0xE0,0x03, ++0x18,0x00,0xBD,0x27, ++0xB0,0x1B,0x02,0x96, ++0x00,0x00,0x00,0x00, ++0xFF,0xDF,0x42,0x30, ++0x48,0x0E,0x00,0x0C, ++0xB0,0x1B,0x02,0xA6, ++0x14,0x00,0xBF,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x08,0x00,0xE0,0x03, ++0x18,0x00,0xBD,0x27, ++0xD0,0xFF,0xBD,0x27, ++0x28,0x00,0xB4,0xAF, ++0x24,0x00,0xB3,0xAF, ++0x20,0x00,0xB2,0xAF, ++0x1C,0x00,0xB1,0xAF, ++0x18,0x00,0xB0,0xAF, ++0x2C,0x00,0xBF,0xAF, ++0x02,0x00,0x82,0x90, ++0x02,0x80,0x14,0x3C, ++0x30,0x1F,0x92,0x26, ++0xB0,0x1B,0x43,0x96, ++0x00,0x00,0x85,0x8C, ++0x0F,0x00,0x42,0x30, ++0xC0,0x10,0x02,0x00, ++0x21,0x80,0x44,0x00, ++0x01,0x00,0x63,0x30, ++0xFF,0x3F,0xB3,0x30, ++0x18,0x00,0x11,0x26, ++0x0A,0x00,0x60,0x14, ++0x21,0x20,0x00,0x00, ++0x2C,0x00,0xBF,0x8F, ++0x28,0x00,0xB4,0x8F, ++0x24,0x00,0xB3,0x8F, ++0x20,0x00,0xB2,0x8F, ++0x1C,0x00,0xB1,0x8F, ++0x18,0x00,0xB0,0x8F, ++0x21,0x10,0x80,0x00, ++0x08,0x00,0xE0,0x03, ++0x30,0x00,0xBD,0x27, ++0x55,0x50,0x00,0x0C, ++0x21,0x20,0x20,0x02, ++0x02,0x80,0x04,0x3C, ++0x18,0x3B,0x84,0x24, ++0x21,0x28,0x40,0x00, ++0x39,0x52,0x00,0x0C, ++0x06,0x00,0x06,0x24, ++0xEF,0xFF,0x40,0x14, ++0x21,0x20,0x00,0x00, ++0xB0,0x1B,0x42,0x96, ++0x00,0x00,0x00,0x00, ++0x00,0x10,0x42,0x30, ++0xEA,0xFF,0x40,0x14, ++0x00,0x00,0x00,0x00, ++0x18,0x00,0x03,0x96, ++0x04,0x00,0x04,0x24, ++0x21,0x10,0x80,0x00, ++0x00,0x40,0x63,0x30, ++0x0A,0x10,0x03,0x00, ++0x21,0x10,0x22,0x02, ++0x1C,0x00,0x43,0x94, ++0x1A,0x00,0x45,0x94, ++0x2F,0x00,0x60,0x14, ++0x02,0x00,0x02,0x24, ++0x14,0x00,0xA2,0x10, ++0x01,0x00,0x02,0x24, ++0x0E,0x00,0xA4,0x14, ++0x02,0x80,0x04,0x3C, ++0x78,0x3D,0x43,0x8E, ++0x00,0x00,0x00,0x00, ++0x06,0x00,0x62,0x10, ++0x30,0x1F,0x83,0x26, ++0xB0,0x1B,0x62,0x94, ++0xFF,0xFF,0x04,0x24, ++0xFF,0xDF,0x42,0x30, ++0xE9,0x4B,0x00,0x08, ++0xB0,0x1B,0x62,0xA4, ++0x84,0x14,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0xE9,0x4B,0x00,0x08, ++0x21,0x20,0x00,0x00, ++0x2F,0x55,0x00,0x0C, ++0xEC,0xE1,0x84,0x24, ++0x12,0x4C,0x00,0x08, ++0x30,0x1F,0x83,0x26, ++0x78,0x3D,0x43,0x8E, ++0x00,0x00,0x00,0x00, ++0xF5,0xFF,0x62,0x14, ++0xE2,0xFF,0x67,0x26, ++0x36,0x00,0x04,0x26, ++0x10,0x00,0x05,0x24, ++0x55,0x1D,0x00,0x0C, ++0x10,0x00,0xA6,0x27, ++0x16,0x00,0x40,0x10, ++0x00,0x00,0x00,0x00, ++0x10,0x00,0xA6,0x8F, ++0x02,0x80,0x04,0x3C, ++0xB8,0x5C,0x84,0x24, ++0x10,0x52,0x00,0x0C, ++0x02,0x00,0x45,0x24, ++0xB0,0x1B,0x43,0x96, ++0x21,0x20,0x00,0x00, ++0x03,0x00,0x02,0x24, ++0xDF,0xFF,0x63,0x30, ++0x40,0x00,0x63,0x34, ++0xB0,0x1B,0x43,0xA6, ++0xBC,0x15,0x00,0x0C, ++0x74,0x3D,0x42,0xAE, ++0xE9,0x4B,0x00,0x08, ++0x21,0x20,0x00,0x00, ++0x02,0x80,0x04,0x3C, ++0xBC,0xE1,0x84,0x24, ++0x2F,0x55,0x00,0x0C, ++0x21,0x28,0x60,0x00, ++0x12,0x4C,0x00,0x08, ++0x30,0x1F,0x83,0x26, ++0x02,0x80,0x04,0x3C, ++0x2F,0x55,0x00,0x0C, ++0xD8,0xE1,0x84,0x24, ++0x12,0x4C,0x00,0x08, ++0x30,0x1F,0x83,0x26, ++0xE8,0xFF,0xBD,0x27, ++0x02,0x80,0x02,0x3C, ++0x10,0x00,0xB0,0xAF, ++0x14,0x00,0xBF,0xAF, ++0x30,0x1F,0x50,0x24, ++0x6C,0x3D,0x03,0x8E, ++0xFF,0xFF,0x04,0x24, ++0x01,0x00,0x63,0x24, ++0x05,0x00,0x62,0x2C, ++0x16,0x00,0x40,0x10, ++0x6C,0x3D,0x03,0xAE, ++0xB0,0x1B,0x03,0x96, ++0xBF,0xFF,0x02,0x24, ++0x21,0x20,0x00,0x00, ++0x24,0x10,0x62,0x00, ++0x80,0x00,0x63,0x30, ++0x05,0x00,0x60,0x10, ++0x20,0x00,0x45,0x34, ++0x14,0x00,0xBF,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x08,0x00,0xE0,0x03, ++0x18,0x00,0xBD,0x27, ++0x01,0x00,0x02,0x24, ++0x74,0x3D,0x02,0xAE, ++0xBC,0x15,0x00,0x0C, ++0xB0,0x1B,0x05,0xA6, ++0xC8,0x00,0x03,0x24, ++0xB4,0x38,0x03,0xAE, ++0x14,0x00,0xBF,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x08,0x00,0xE0,0x03, ++0x18,0x00,0xBD,0x27, ++0xB0,0x1B,0x02,0x96, ++0x00,0x00,0x00,0x00, ++0xFF,0xDF,0x42,0x30, ++0x48,0x0E,0x00,0x0C, ++0xB0,0x1B,0x02,0xA6, ++0x14,0x00,0xBF,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x08,0x00,0xE0,0x03, ++0x18,0x00,0xBD,0x27, ++0xD0,0xFF,0xBD,0x27, ++0x20,0x00,0xB2,0xAF, ++0x21,0x90,0x80,0x00, ++0x00,0x01,0x04,0x24, ++0x24,0x00,0xB3,0xAF, ++0x1C,0x00,0xB1,0xAF, ++0x21,0x98,0xA0,0x00, ++0x28,0x00,0xBF,0xAF, ++0x25,0x24,0x00,0x0C, ++0x18,0x00,0xB0,0xAF, ++0x02,0x80,0x04,0x3C, ++0x02,0x80,0x05,0x3C, ++0x21,0x88,0x40,0x00, ++0x20,0xE2,0x84,0x24, ++0x37,0x00,0x40,0x10, ++0x04,0xEB,0xA5,0x24, ++0x2F,0x55,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x08,0x00,0x30,0x96, ++0x02,0x80,0x02,0x3C, ++0x21,0x28,0x40,0x02, ++0x25,0x80,0x02,0x02, ++0x24,0x00,0x04,0x26, ++0x20,0x00,0x00,0xA6, ++0x10,0x52,0x00,0x0C, ++0x06,0x00,0x06,0x24, ++0x02,0x80,0x05,0x3C, ++0x2A,0x00,0x04,0x26, ++0x18,0x3B,0xA5,0x24, ++0x10,0x52,0x00,0x0C, ++0x06,0x00,0x06,0x24, ++0x02,0x80,0x05,0x3C, ++0x30,0x00,0x04,0x26, ++0x88,0x58,0xA5,0x24, ++0x10,0x52,0x00,0x0C, ++0x06,0x00,0x06,0x24, ++0x20,0x00,0x03,0x96, ++0x18,0x00,0x02,0x24, ++0x02,0x80,0x05,0x3C, ++0x03,0xFF,0x63,0x30, ++0xC0,0x00,0x63,0x34, ++0x20,0x00,0x03,0xA6, ++0x30,0x1F,0xA5,0x24, ++0x0C,0x00,0x22,0xAE, ++0xF8,0x1D,0xA3,0x94, ++0x20,0x00,0x07,0x26, ++0x38,0x00,0x04,0x26, ++0xFF,0x0F,0x62,0x30, ++0x00,0x11,0x02,0x00, ++0x02,0x32,0x02,0x00, ++0x01,0x00,0x63,0x24, ++0xF8,0x1D,0xA3,0xA4, ++0x17,0x00,0xE6,0xA0, ++0x16,0x00,0xE2,0xA0, ++0x10,0x00,0xA6,0x27, ++0x0C,0x00,0x27,0x26, ++0x02,0x00,0x05,0x24, ++0x68,0x4F,0x00,0x0C, ++0x10,0x00,0xB3,0xA7, ++0x21,0x20,0x20,0x02, ++0x21,0x28,0x00,0x00, ++0xB9,0x0C,0x00,0x0C, ++0x21,0x30,0x00,0x00, ++0x28,0x00,0xBF,0x8F, ++0x24,0x00,0xB3,0x8F, ++0x20,0x00,0xB2,0x8F, ++0x1C,0x00,0xB1,0x8F, ++0x18,0x00,0xB0,0x8F, ++0x08,0x00,0xE0,0x03, ++0x30,0x00,0xBD,0x27, ++0x02,0x80,0x04,0x3C, ++0x2F,0x55,0x00,0x0C, ++0x14,0xE2,0x84,0x24, ++0x28,0x00,0xBF,0x8F, ++0x24,0x00,0xB3,0x8F, ++0x20,0x00,0xB2,0x8F, ++0x1C,0x00,0xB1,0x8F, ++0x18,0x00,0xB0,0x8F, ++0x08,0x00,0xE0,0x03, ++0x30,0x00,0xBD,0x27, ++0xD0,0xFF,0xBD,0x27, ++0x20,0x00,0xB2,0xAF, ++0x21,0x90,0x80,0x00, ++0x00,0x01,0x04,0x24, ++0x24,0x00,0xB3,0xAF, ++0x1C,0x00,0xB1,0xAF, ++0x21,0x98,0xA0,0x00, ++0x28,0x00,0xBF,0xAF, ++0x25,0x24,0x00,0x0C, ++0x18,0x00,0xB0,0xAF, ++0x02,0x80,0x04,0x3C, ++0x02,0x80,0x05,0x3C, ++0x21,0x88,0x40,0x00, ++0x3C,0xE2,0x84,0x24, ++0x37,0x00,0x40,0x10, ++0x14,0xEB,0xA5,0x24, ++0x2F,0x55,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x08,0x00,0x30,0x96, ++0x02,0x80,0x02,0x3C, ++0x21,0x28,0x40,0x02, ++0x25,0x80,0x02,0x02, ++0x24,0x00,0x04,0x26, ++0x20,0x00,0x00,0xA6, ++0x10,0x52,0x00,0x0C, ++0x06,0x00,0x06,0x24, ++0x02,0x80,0x05,0x3C, ++0x2A,0x00,0x04,0x26, ++0x18,0x3B,0xA5,0x24, ++0x10,0x52,0x00,0x0C, ++0x06,0x00,0x06,0x24, ++0x02,0x80,0x05,0x3C, ++0x30,0x00,0x04,0x26, ++0x88,0x58,0xA5,0x24, ++0x10,0x52,0x00,0x0C, ++0x06,0x00,0x06,0x24, ++0x20,0x00,0x03,0x96, ++0x18,0x00,0x02,0x24, ++0x02,0x80,0x05,0x3C, ++0x03,0xFF,0x63,0x30, ++0xA0,0x00,0x63,0x34, ++0x20,0x00,0x03,0xA6, ++0x30,0x1F,0xA5,0x24, ++0x0C,0x00,0x22,0xAE, ++0xF8,0x1D,0xA3,0x94, ++0x20,0x00,0x07,0x26, ++0x38,0x00,0x04,0x26, ++0xFF,0x0F,0x62,0x30, ++0x00,0x11,0x02,0x00, ++0x02,0x32,0x02,0x00, ++0x01,0x00,0x63,0x24, ++0xF8,0x1D,0xA3,0xA4, ++0x17,0x00,0xE6,0xA0, ++0x16,0x00,0xE2,0xA0, ++0x10,0x00,0xA6,0x27, ++0x0C,0x00,0x27,0x26, ++0x02,0x00,0x05,0x24, ++0x68,0x4F,0x00,0x0C, ++0x10,0x00,0xB3,0xA7, ++0x21,0x20,0x20,0x02, ++0x21,0x28,0x00,0x00, ++0xB9,0x0C,0x00,0x0C, ++0x21,0x30,0x00,0x00, ++0x28,0x00,0xBF,0x8F, ++0x24,0x00,0xB3,0x8F, ++0x20,0x00,0xB2,0x8F, ++0x1C,0x00,0xB1,0x8F, ++0x18,0x00,0xB0,0x8F, ++0x08,0x00,0xE0,0x03, ++0x30,0x00,0xBD,0x27, ++0x02,0x80,0x04,0x3C, ++0x2F,0x55,0x00,0x0C, ++0x30,0xE2,0x84,0x24, ++0x28,0x00,0xBF,0x8F, ++0x24,0x00,0xB3,0x8F, ++0x20,0x00,0xB2,0x8F, ++0x1C,0x00,0xB1,0x8F, ++0x18,0x00,0xB0,0x8F, ++0x08,0x00,0xE0,0x03, ++0x30,0x00,0xBD,0x27, ++0xC8,0xFF,0xBD,0x27, ++0x2C,0x00,0xB1,0xAF, ++0xFF,0xFF,0x05,0x24, ++0x21,0x88,0x80,0x00, ++0x02,0x00,0x06,0x24, ++0x10,0x00,0xA4,0x27, ++0x34,0x00,0xBF,0xAF, ++0x30,0x00,0xB2,0xAF, ++0x08,0x52,0x00,0x0C, ++0x28,0x00,0xB0,0xAF, ++0x08,0x00,0x30,0x96, ++0x02,0x80,0x02,0x3C, ++0x21,0x28,0x00,0x00, ++0x25,0x80,0x02,0x02, ++0x21,0x20,0x00,0x02, ++0x08,0x52,0x00,0x0C, ++0x10,0x00,0x06,0x24, ++0x20,0x00,0x02,0x96, ++0x24,0x00,0x04,0x26, ++0x10,0x00,0xA5,0x27, ++0x03,0xFF,0x42,0x30, ++0xC8,0x00,0x42,0x34, ++0x20,0x00,0x02,0xA6, ++0x10,0x52,0x00,0x0C, ++0x06,0x00,0x06,0x24, ++0x25,0xB0,0x03,0x3C, ++0x50,0x00,0x62,0x34, ++0x00,0x00,0x44,0x8C, ++0x54,0x00,0x65,0x34, ++0x58,0x00,0x66,0x34, ++0x18,0x00,0xA4,0xAF, ++0x00,0x00,0xA2,0x8C, ++0x5C,0x00,0x63,0x34, ++0x2A,0x00,0x04,0x26, ++0x1C,0x00,0xA2,0xAF, ++0x00,0x00,0xC7,0x8C, ++0x18,0x00,0xA5,0x27, ++0x06,0x00,0x06,0x24, ++0x20,0x00,0xA7,0xAF, ++0x00,0x00,0x62,0x8C, ++0x1A,0x00,0x12,0x24, ++0x10,0x52,0x00,0x0C, ++0x24,0x00,0xA2,0xAF, ++0x30,0x00,0x04,0x26, ++0x20,0x00,0xA5,0x27, ++0x10,0x52,0x00,0x0C, ++0x06,0x00,0x06,0x24, ++0x13,0x00,0x03,0x24, ++0x14,0x00,0x23,0xAE, ++0x0C,0x00,0x32,0xAE, ++0x08,0x00,0x05,0x8E, ++0x04,0x00,0x04,0x8E, ++0xFF,0xDF,0x02,0x3C, ++0x14,0x00,0x06,0x8E, ++0xFF,0xFF,0x42,0x34, ++0x10,0x00,0x07,0x8E, ++0xFF,0xE0,0x03,0x24, ++0x24,0x28,0xA2,0x00, ++0x00,0x40,0x02,0x3C, ++0x24,0x20,0x83,0x00, ++0x25,0x28,0xA2,0x00, ++0xFF,0x81,0x03,0x24, ++0xFE,0xFF,0x02,0x3C, ++0x24,0x30,0xC3,0x00, ++0xFF,0xFF,0x42,0x34, ++0x00,0x12,0x84,0x34, ++0x00,0x80,0x03,0x3C, ++0x24,0x20,0x82,0x00, ++0x25,0x38,0xE3,0x00, ++0x00,0x26,0xC6,0x34, ++0x80,0x00,0xA5,0x34, ++0x20,0x00,0x02,0x24, ++0x00,0x00,0x12,0xA6, ++0x10,0x00,0x07,0xAE, ++0x02,0x00,0x02,0xA2, ++0x14,0x00,0x06,0xAE, ++0x04,0x00,0x04,0xAE, ++0x08,0x00,0x05,0xAE, ++0x34,0x00,0xBF,0x8F, ++0x30,0x00,0xB2,0x8F, ++0x2C,0x00,0xB1,0x8F, ++0x28,0x00,0xB0,0x8F, ++0x08,0x00,0xE0,0x03, ++0x38,0x00,0xBD,0x27, ++0xC8,0xFF,0xBD,0x27, ++0x1C,0x00,0xB1,0xAF, ++0x01,0x80,0x02,0x3C, ++0x25,0xB0,0x11,0x3C, ++0x18,0x03,0x23,0x36, ++0x80,0x35,0x42,0x24, ++0x28,0x00,0xB4,0xAF, ++0x20,0x00,0xB2,0xAF, ++0x21,0xA0,0x80,0x00, ++0x48,0x00,0xB2,0x93, ++0xFF,0x00,0xE4,0x30, ++0x00,0x00,0x62,0xAC, ++0x24,0x00,0xB3,0xAF, ++0x18,0x00,0xB0,0xAF, ++0x30,0x00,0xBF,0xAF, ++0x2C,0x00,0xB5,0xAF, ++0xFF,0x00,0xB3,0x30, ++0x0D,0x24,0x00,0x0C, ++0xFF,0x00,0xD0,0x30, ++0x66,0x00,0x40,0x10, ++0x10,0x00,0xA2,0xAF, ++0x08,0x00,0x44,0x8C, ++0xB0,0x03,0x22,0x36, ++0x00,0x00,0x44,0xAC, ++0x10,0x00,0xA3,0x8F, ++0x02,0x80,0x02,0x3C, ++0x08,0x00,0x64,0x94, ++0x00,0x00,0x00,0x00, ++0x25,0x88,0x82,0x00, ++0x41,0x00,0x40,0x16, ++0x20,0x00,0x24,0x26, ++0x48,0x00,0x02,0x24, ++0x43,0x00,0x02,0x12, ++0x20,0x00,0x30,0xA6, ++0x04,0x00,0x02,0x24, ++0x47,0x00,0x62,0x16, ++0x21,0x28,0x80,0x02, ++0xA4,0x00,0x02,0x24, ++0x61,0x00,0x02,0x12, ++0x02,0x80,0x02,0x3C, ++0x10,0x00,0xA2,0x8F, ++0x25,0xB0,0x10,0x3C, ++0xB0,0x03,0x10,0x36, ++0x0C,0x00,0x55,0xAC, ++0x10,0x00,0xA2,0x8F, ++0x12,0x00,0x03,0x24, ++0x21,0x28,0x00,0x00, ++0x14,0x00,0x43,0xAC, ++0x00,0x00,0x15,0xAE, ++0x10,0x00,0xA2,0x8F, ++0x08,0x00,0x06,0x24, ++0x08,0x00,0x43,0x8C, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x03,0xAE, ++0x10,0x00,0xA2,0x8F, ++0x02,0x80,0x03,0x3C, ++0x08,0x00,0x44,0x94, ++0x00,0x00,0x00,0x00, ++0x25,0x88,0x83,0x00, ++0x08,0x52,0x00,0x0C, ++0x21,0x20,0x20,0x02, ++0x14,0x00,0x25,0x8E, ++0x08,0x00,0x24,0x8E, ++0xFF,0xDF,0x02,0x3C, ++0xFF,0x81,0x03,0x24, ++0xFF,0xFF,0x42,0x34, ++0x24,0x28,0xA3,0x00, ++0x24,0x20,0x82,0x00, ++0x00,0x40,0x03,0x3C, ++0x25,0x20,0x83,0x00, ++0x20,0x00,0x02,0x24, ++0x00,0x24,0xA5,0x34, ++0x00,0x00,0x35,0xA6, ++0x02,0x00,0x22,0xA2, ++0x08,0x00,0x24,0xAE, ++0x14,0x00,0x25,0xAE, ++0x02,0x80,0x02,0x3C, ++0x10,0x00,0xA3,0x8F, ++0x74,0x57,0x42,0x24, ++0x04,0x00,0x44,0x8C, ++0x00,0x00,0x62,0xAC, ++0x04,0x00,0x43,0xAC, ++0x10,0x00,0xA2,0x27, ++0x00,0x00,0x83,0xAC, ++0x04,0x00,0x64,0xAC, ++0x30,0x00,0xBF,0x8F, ++0x00,0x00,0x02,0xAE, ++0x2C,0x00,0xB5,0x8F, ++0x28,0x00,0xB4,0x8F, ++0x24,0x00,0xB3,0x8F, ++0x20,0x00,0xB2,0x8F, ++0x1C,0x00,0xB1,0x8F, ++0x18,0x00,0xB0,0x8F, ++0x08,0x00,0xE0,0x03, ++0x38,0x00,0xBD,0x27, ++0x00,0x10,0x02,0x36, ++0x20,0x00,0x22,0xA6, ++0x48,0x00,0x02,0x24, ++0xC0,0xFF,0x02,0x16, ++0x04,0x00,0x02,0x24, ++0x20,0x00,0x22,0x96, ++0x00,0x00,0x00,0x00, ++0x00,0x01,0x42,0x34, ++0x20,0x00,0x22,0xA6, ++0x04,0x00,0x02,0x24, ++0xBB,0xFF,0x62,0x12, ++0x21,0x28,0x80,0x02, ++0x24,0x00,0x24,0x26, ++0x10,0x52,0x00,0x0C, ++0x06,0x00,0x06,0x24, ++0x02,0x80,0x05,0x3C, ++0x18,0x3B,0xA5,0x24, ++0x2A,0x00,0x24,0x26, ++0x10,0x52,0x00,0x0C, ++0x06,0x00,0x06,0x24, ++0x02,0x80,0x05,0x3C, ++0x30,0x00,0x24,0x26, ++0x88,0x58,0xA5,0x24, ++0x10,0x52,0x00,0x0C, ++0x06,0x00,0x06,0x24, ++0x88,0x4D,0x00,0x08, ++0x18,0x00,0x15,0x24, ++0x02,0x80,0x04,0x3C, ++0x02,0x80,0x05,0x3C, ++0x4C,0xE2,0x84,0x24, ++0x2F,0x55,0x00,0x0C, ++0x24,0xEB,0xA5,0x24, ++0x30,0x00,0xBF,0x8F, ++0x2C,0x00,0xB5,0x8F, ++0x28,0x00,0xB4,0x8F, ++0x24,0x00,0xB3,0x8F, ++0x20,0x00,0xB2,0x8F, ++0x1C,0x00,0xB1,0x8F, ++0x18,0x00,0xB0,0x8F, ++0x08,0x00,0xE0,0x03, ++0x38,0x00,0xBD,0x27, ++0x80,0x58,0x43,0x94, ++0x02,0x80,0x05,0x3C, ++0x88,0x58,0xA5,0x24, ++0x00,0xC0,0x63,0x24, ++0xFF,0xFF,0x63,0x30, ++0x02,0x12,0x03,0x00, ++0x02,0x00,0x83,0xA0, ++0x03,0x00,0x82,0xA0, ++0x06,0x00,0x06,0x24, ++0x10,0x52,0x00,0x0C, ++0x24,0x00,0x24,0x26, ++0x02,0x80,0x05,0x3C, ++0x2A,0x00,0x24,0x26, ++0x18,0x3B,0xA5,0x24, ++0x10,0x52,0x00,0x0C, ++0x06,0x00,0x06,0x24, ++0x88,0x4D,0x00,0x08, ++0x18,0x00,0x15,0x24, ++0xB0,0xFF,0xBD,0x27, ++0x3C,0x00,0xB5,0xAF, ++0x38,0x00,0xB4,0xAF, ++0xFF,0xFF,0xF5,0x30, ++0x25,0xB0,0x14,0x3C, ++0x01,0x80,0x02,0x3C, ++0x2C,0x00,0xB1,0xAF, ++0x18,0x03,0x83,0x36, ++0xE8,0x37,0x42,0x24, ++0x20,0x00,0xB1,0x26, ++0x44,0x00,0xB7,0xAF, ++0x34,0x00,0xB3,0xAF, ++0x21,0xB8,0x80,0x00, ++0x60,0x00,0xB3,0x93, ++0x21,0x20,0x20,0x02, ++0x00,0x00,0x62,0xAC, ++0x40,0x00,0xB6,0xAF, ++0x30,0x00,0xB2,0xAF, ++0x48,0x00,0xBF,0xAF, ++0x28,0x00,0xB0,0xAF, ++0xFF,0x00,0xB6,0x30, ++0x25,0x24,0x00,0x0C, ++0xFF,0x00,0xD2,0x30, ++0x11,0x00,0x40,0x14, ++0x20,0x00,0xA2,0xAF, ++0x02,0x80,0x04,0x3C, ++0x02,0x80,0x05,0x3C, ++0x58,0xE2,0x84,0x24, ++0x2F,0x55,0x00,0x0C, ++0x30,0xEB,0xA5,0x24, ++0x48,0x00,0xBF,0x8F, ++0x44,0x00,0xB7,0x8F, ++0x40,0x00,0xB6,0x8F, ++0x3C,0x00,0xB5,0x8F, ++0x38,0x00,0xB4,0x8F, ++0x34,0x00,0xB3,0x8F, ++0x30,0x00,0xB2,0x8F, ++0x2C,0x00,0xB1,0x8F, ++0x28,0x00,0xB0,0x8F, ++0x08,0x00,0xE0,0x03, ++0x50,0x00,0xBD,0x27, ++0x08,0x00,0x43,0x8C, ++0xB0,0x03,0x82,0x36, ++0x02,0x80,0x10,0x3C, ++0x00,0x00,0x43,0xAC, ++0x20,0x00,0xA2,0x8F, ++0x21,0x30,0x20,0x02, ++0x21,0x28,0x00,0x00, ++0x08,0x00,0x44,0x94, ++0xFF,0x51,0x00,0x0C, ++0x25,0x20,0x90,0x00, ++0x20,0x00,0xA3,0x8F, ++0x00,0x00,0x00,0x00, ++0x08,0x00,0x62,0x94, ++0x00,0x00,0x00,0x00, ++0x25,0x88,0x50,0x00, ++0x51,0x00,0x60,0x16, ++0x20,0x00,0x30,0x26, ++0x20,0x00,0x32,0xA6, ++0x48,0x00,0x02,0x24, ++0x6C,0x00,0x42,0x12, ++0x50,0x00,0x82,0x36, ++0x04,0x00,0x02,0x24, ++0x4D,0x00,0xC2,0x16, ++0x21,0x28,0xE0,0x02, ++0xA4,0x00,0x02,0x24, ++0x7E,0x00,0x42,0x12, ++0x02,0x80,0x02,0x3C, ++0x20,0x00,0xA2,0x8F, ++0x25,0xB0,0x10,0x3C, ++0xB0,0x03,0x10,0x36, ++0x0C,0x00,0x55,0xAC, ++0x20,0x00,0xA2,0x8F, ++0x12,0x00,0x03,0x24, ++0x21,0x28,0x00,0x00, ++0x14,0x00,0x43,0xAC, ++0x00,0x00,0x15,0xAE, ++0x20,0x00,0xA2,0x8F, ++0x08,0x00,0x06,0x24, ++0x08,0x00,0x43,0x8C, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x03,0xAE, ++0x20,0x00,0xA2,0x8F, ++0x02,0x80,0x03,0x3C, ++0x08,0x00,0x44,0x94, ++0x00,0x00,0x00,0x00, ++0x25,0x88,0x83,0x00, ++0x08,0x52,0x00,0x0C, ++0x21,0x20,0x20,0x02, ++0x04,0x00,0x25,0x8E, ++0x08,0x00,0x26,0x8E, ++0x14,0x00,0x27,0x8E, ++0x10,0x00,0x24,0x8E, ++0xFF,0xE0,0x03,0x24, ++0xFF,0xDF,0x02,0x3C, ++0x24,0x28,0xA3,0x00, ++0xFF,0xFF,0x42,0x34, ++0xFF,0x81,0x03,0x24, ++0x24,0x38,0xE3,0x00, ++0x24,0x30,0xC2,0x00, ++0x00,0x80,0x03,0x3C, ++0x00,0x40,0x02,0x3C, ++0x25,0x30,0xC2,0x00, ++0x25,0x20,0x83,0x00, ++0x00,0x12,0xA5,0x34, ++0x20,0x00,0x02,0x24, ++0x10,0x00,0x24,0xAE, ++0x00,0x00,0x35,0xA6, ++0x02,0x00,0x22,0xA2, ++0x04,0x00,0x25,0xAE, ++0x14,0x00,0x27,0xAE, ++0x08,0x00,0x26,0xAE, ++0x00,0x60,0x05,0x40, ++0x01,0x00,0xA1,0x34, ++0x01,0x00,0x21,0x38, ++0x00,0x60,0x81,0x40, ++0x02,0x80,0x02,0x3C, ++0x20,0x00,0xA3,0x8F, ++0x74,0x57,0x42,0x24, ++0x04,0x00,0x44,0x8C, ++0x00,0x00,0x62,0xAC, ++0x04,0x00,0x43,0xAC, ++0x20,0x00,0xA2,0x27, ++0x00,0x00,0x83,0xAC, ++0x04,0x00,0x64,0xAC, ++0x00,0x00,0x02,0xAE, ++0x00,0x60,0x85,0x40, ++0x48,0x00,0xBF,0x8F, ++0x44,0x00,0xB7,0x8F, ++0x40,0x00,0xB6,0x8F, ++0x3C,0x00,0xB5,0x8F, ++0x38,0x00,0xB4,0x8F, ++0x34,0x00,0xB3,0x8F, ++0x30,0x00,0xB2,0x8F, ++0x2C,0x00,0xB1,0x8F, ++0x28,0x00,0xB0,0x8F, ++0x08,0x00,0xE0,0x03, ++0x50,0x00,0xBD,0x27, ++0x00,0x10,0x42,0x36, ++0x35,0x4E,0x00,0x08, ++0x20,0x00,0x22,0xA6, ++0x24,0x00,0x24,0x26, ++0x10,0x52,0x00,0x0C, ++0x06,0x00,0x06,0x24, ++0x02,0x80,0x05,0x3C, ++0x18,0x3B,0xA5,0x24, ++0x2A,0x00,0x24,0x26, ++0x10,0x52,0x00,0x0C, ++0x06,0x00,0x06,0x24, ++0x02,0x80,0x05,0x3C, ++0x30,0x00,0x24,0x26, ++0x88,0x58,0xA5,0x24, ++0x10,0x52,0x00,0x0C, ++0x06,0x00,0x06,0x24, ++0x02,0x80,0x05,0x3C, ++0x30,0x1F,0xA5,0x24, ++0xF8,0x1D,0xA6,0x94, ++0x00,0x00,0x00,0x00, ++0x01,0x00,0xC2,0x24, ++0x00,0x21,0x06,0x00, ++0xFF,0xFF,0x46,0x30, ++0xFF,0xFF,0x84,0x30, ++0x00,0x10,0xC2,0x2C, ++0x0A,0x30,0x02,0x00, ++0x02,0x1A,0x04,0x00, ++0x17,0x00,0x03,0xA2, ++0x16,0x00,0x04,0xA2, ++0x3E,0x4E,0x00,0x08, ++0xF8,0x1D,0xA6,0xA4, ++0x00,0x00,0x43,0x8C, ++0x54,0x00,0x84,0x36, ++0x58,0x00,0x85,0x36, ++0x10,0x00,0xA3,0xAF, ++0x00,0x00,0x82,0x8C, ++0x5C,0x00,0x87,0x36, ++0x2A,0x00,0x24,0x26, ++0x14,0x00,0xA2,0xAF, ++0x00,0x00,0xA3,0x8C, ++0x06,0x00,0x06,0x24, ++0x10,0x00,0xA5,0x27, ++0x18,0x00,0xA3,0xAF, ++0x00,0x00,0xE2,0x8C, ++0x10,0x52,0x00,0x0C, ++0x1C,0x00,0xA2,0xAF, ++0x30,0x00,0x24,0x26, ++0x18,0x00,0xA5,0x27, ++0x10,0x52,0x00,0x0C, ++0x06,0x00,0x06,0x24, ++0x20,0x00,0x23,0x96, ++0x00,0x00,0x00,0x00, ++0x00,0x01,0x63,0x34, ++0x38,0x4E,0x00,0x08, ++0x20,0x00,0x23,0xA6, ++0x80,0x58,0x43,0x94, ++0x02,0x80,0x05,0x3C, ++0x24,0x00,0x24,0x26, ++0x00,0xC0,0x63,0x24, ++0xFF,0xFF,0x63,0x30, ++0x02,0x12,0x03,0x00, ++0x88,0x58,0xA5,0x24, ++0x03,0x00,0x02,0xA2, ++0x02,0x00,0x03,0xA2, ++0x10,0x52,0x00,0x0C, ++0x06,0x00,0x06,0x24, ++0x02,0x80,0x05,0x3C, ++0x2A,0x00,0x24,0x26, ++0x18,0x3B,0xA5,0x24, ++0x10,0x52,0x00,0x0C, ++0x06,0x00,0x06,0x24, ++0x3E,0x4E,0x00,0x08, ++0x00,0x00,0x00,0x00, ++0xE0,0xFF,0xBD,0x27, ++0x18,0x00,0xB0,0xAF, ++0xFF,0x00,0x90,0x30, ++0x02,0x80,0x04,0x3C, ++0x21,0x28,0x00,0x02, ++0x1C,0x00,0xBF,0xAF, ++0x2F,0x55,0x00,0x0C, ++0x64,0xE2,0x84,0x24, ++0x02,0x80,0x04,0x3C, ++0x88,0x58,0x84,0x24, ++0x08,0x00,0x05,0x24, ++0x48,0x00,0x06,0x24, ++0x18,0x00,0x07,0x24, ++0xFA,0x4D,0x00,0x0C, ++0x10,0x00,0xB0,0xAF, ++0x1C,0x00,0xBF,0x8F, ++0x18,0x00,0xB0,0x8F, ++0x08,0x00,0xE0,0x03, ++0x20,0x00,0xBD,0x27, ++0xE0,0xFF,0xBD,0x27, ++0x01,0x00,0x02,0x24, ++0x21,0x28,0x00,0x00, ++0x90,0x00,0x06,0x24, ++0x21,0x38,0x00,0x00, ++0x18,0x00,0xBF,0xAF, ++0x60,0x4D,0x00,0x0C, ++0x10,0x00,0xA2,0xAF, ++0x18,0x00,0xBF,0x8F, ++0x00,0x00,0x00,0x00, ++0x08,0x00,0xE0,0x03, ++0x20,0x00,0xBD,0x27, ++0xD8,0xFF,0xBD,0x27, ++0x20,0x00,0xB0,0xAF, ++0xFF,0xFF,0x05,0x24, ++0xFF,0x00,0x90,0x30, ++0x02,0x00,0x06,0x24, ++0x24,0x00,0xBF,0xAF, ++0x08,0x52,0x00,0x0C, ++0x18,0x00,0xA4,0x27, ++0x18,0x00,0xA4,0x27, ++0x08,0x00,0x05,0x24, ++0xC8,0x00,0x06,0x24, ++0x21,0x38,0x00,0x00, ++0x60,0x4D,0x00,0x0C, ++0x10,0x00,0xB0,0xAF, ++0x24,0x00,0xBF,0x8F, ++0x20,0x00,0xB0,0x8F, ++0x08,0x00,0xE0,0x03, ++0x28,0x00,0xBD,0x27, ++0xE0,0xFF,0xBD,0x27, ++0x02,0x80,0x05,0x3C, ++0x1C,0x00,0xBF,0xAF, ++0x18,0x00,0xB0,0xAF, ++0x30,0x1F,0xA5,0x24, ++0x50,0x39,0xA2,0x94, ++0x01,0x00,0x03,0x24, ++0xFF,0x00,0x90,0x30, ++0x00,0xC0,0x42,0x24, ++0xFF,0xFF,0x44,0x30, ++0xC2,0x34,0x00,0x0C, ++0x2A,0x1C,0xA3,0xA0, ++0x02,0x80,0x04,0x3C, ++0x88,0x58,0x84,0x24, ++0x04,0x00,0x05,0x24, ++0xA4,0x00,0x06,0x24, ++0x10,0x00,0x07,0x24, ++0xFA,0x4D,0x00,0x0C, ++0x10,0x00,0xB0,0xAF, ++0x1C,0x00,0xBF,0x8F, ++0x18,0x00,0xB0,0x8F, ++0x08,0x00,0xE0,0x03, ++0x20,0x00,0xBD,0x27, ++0x08,0x00,0xE0,0x03, ++0x21,0x10,0x80,0x00, ++0x08,0x00,0xE0,0x03, ++0x08,0x00,0x82,0x24, ++0xE0,0xFF,0xBD,0x27, ++0x18,0x00,0xBF,0xAF, ++0x17,0x4F,0x00,0x0C, ++0x74,0x00,0x84,0x24, ++0x21,0x28,0x40,0x00, ++0x10,0x00,0xA4,0x27, ++0x10,0x52,0x00,0x0C, ++0x02,0x00,0x06,0x24, ++0x10,0x00,0xA2,0x97, ++0x18,0x00,0xBF,0x8F, ++0x00,0x00,0x00,0x00, ++0x08,0x00,0xE0,0x03, ++0x20,0x00,0xBD,0x27, ++0xE0,0xFF,0xBD,0x27, ++0x18,0x00,0xBF,0xAF, ++0x17,0x4F,0x00,0x0C, ++0x10,0x00,0xA5,0xA7, ++0x21,0x20,0x40,0x00, ++0x10,0x00,0xA5,0x27, ++0x10,0x52,0x00,0x0C, ++0x02,0x00,0x06,0x24, ++0x18,0x00,0xBF,0x8F, ++0x00,0x00,0x00,0x00, ++0x08,0x00,0xE0,0x03, ++0x20,0x00,0xBD,0x27, ++0x08,0x00,0xE0,0x03, ++0x0A,0x00,0x82,0x24, ++0xE0,0xFF,0xBD,0x27, ++0x18,0x00,0xBF,0xAF, ++0x32,0x4F,0x00,0x0C, ++0x74,0x00,0x84,0x24, ++0x21,0x28,0x40,0x00, ++0x10,0x00,0xA4,0x27, ++0x10,0x52,0x00,0x0C, ++0x02,0x00,0x06,0x24, ++0x10,0x00,0xA2,0x97, ++0x18,0x00,0xBF,0x8F, ++0x00,0x00,0x00,0x00, ++0x08,0x00,0xE0,0x03, ++0x20,0x00,0xBD,0x27, ++0xE0,0xFF,0xBD,0x27, ++0x10,0x00,0xB0,0xAF, ++0x21,0x80,0x80,0x00, ++0x00,0x00,0x05,0xA2, ++0x01,0x00,0x06,0xA2, ++0x18,0x00,0xB2,0xAF, ++0x14,0x00,0xB1,0xAF, ++0x1C,0x00,0xBF,0xAF, ++0x21,0x88,0xC0,0x00, ++0x02,0x00,0x84,0x24, ++0x30,0x00,0xB2,0x8F, ++0x0D,0x00,0xC0,0x14, ++0x21,0x28,0xE0,0x00, ++0x00,0x00,0x43,0x8E, ++0x21,0x10,0x11,0x02, ++0x1C,0x00,0xBF,0x8F, ++0x21,0x18,0x71,0x00, ++0x02,0x00,0x63,0x24, ++0x00,0x00,0x43,0xAE, ++0x14,0x00,0xB1,0x8F, ++0x18,0x00,0xB2,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x02,0x00,0x42,0x24, ++0x08,0x00,0xE0,0x03, ++0x20,0x00,0xBD,0x27, ++0x10,0x52,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x43,0x8E, ++0x21,0x10,0x11,0x02, ++0x1C,0x00,0xBF,0x8F, ++0x21,0x18,0x71,0x00, ++0x02,0x00,0x63,0x24, ++0x00,0x00,0x43,0xAE, ++0x14,0x00,0xB1,0x8F, ++0x18,0x00,0xB2,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x02,0x00,0x42,0x24, ++0x08,0x00,0xE0,0x03, ++0x20,0x00,0xBD,0x27, ++0xE0,0xFF,0xBD,0x27, ++0x10,0x00,0xB0,0xAF, ++0x21,0x80,0xA0,0x00, ++0x18,0x00,0xB2,0xAF, ++0x21,0x28,0xC0,0x00, ++0x21,0x90,0xE0,0x00, ++0x21,0x30,0x00,0x02, ++0x1C,0x00,0xBF,0xAF, ++0x14,0x00,0xB1,0xAF, ++0x10,0x52,0x00,0x0C, ++0x21,0x88,0x80,0x00, ++0x00,0x00,0x43,0x8E, ++0x21,0x10,0x30,0x02, ++0x1C,0x00,0xBF,0x8F, ++0x21,0x18,0x70,0x00, ++0x00,0x00,0x43,0xAE, ++0x14,0x00,0xB1,0x8F, ++0x18,0x00,0xB2,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x08,0x00,0xE0,0x03, ++0x20,0x00,0xBD,0x27, ++0x7F,0x00,0x84,0x30, ++0x6D,0x00,0x82,0x2C, ++0x0A,0x00,0x40,0x10, ++0x21,0x28,0x00,0x00, ++0x02,0x80,0x03,0x3C, ++0x80,0x10,0x04,0x00, ++0x58,0xEB,0x63,0x24, ++0x21,0x10,0x43,0x00, ++0x00,0x00,0x44,0x8C, ++0x00,0x00,0x00,0x00, ++0x08,0x00,0x80,0x00, ++0x00,0x00,0x00,0x00, ++0x21,0x28,0x00,0x00, ++0x08,0x00,0xE0,0x03, ++0x21,0x10,0xA0,0x00, ++0x0B,0x00,0x05,0x24, ++0x08,0x00,0xE0,0x03, ++0x21,0x10,0xA0,0x00, ++0x0A,0x00,0x05,0x24, ++0x08,0x00,0xE0,0x03, ++0x21,0x10,0xA0,0x00, ++0x09,0x00,0x05,0x24, ++0x08,0x00,0xE0,0x03, ++0x21,0x10,0xA0,0x00, ++0x08,0x00,0x05,0x24, ++0x08,0x00,0xE0,0x03, ++0x21,0x10,0xA0,0x00, ++0x07,0x00,0x05,0x24, ++0x08,0x00,0xE0,0x03, ++0x21,0x10,0xA0,0x00, ++0x06,0x00,0x05,0x24, ++0x08,0x00,0xE0,0x03, ++0x21,0x10,0xA0,0x00, ++0x03,0x00,0x05,0x24, ++0x08,0x00,0xE0,0x03, ++0x21,0x10,0xA0,0x00, ++0x05,0x00,0x05,0x24, ++0x08,0x00,0xE0,0x03, ++0x21,0x10,0xA0,0x00, ++0x04,0x00,0x05,0x24, ++0x08,0x00,0xE0,0x03, ++0x21,0x10,0xA0,0x00, ++0x02,0x00,0x05,0x24, ++0x08,0x00,0xE0,0x03, ++0x21,0x10,0xA0,0x00, ++0x01,0x00,0x05,0x24, ++0x08,0x00,0xE0,0x03, ++0x21,0x10,0xA0,0x00, ++0x7F,0x00,0x84,0x30, ++0x0C,0x00,0x82,0x2C, ++0x0A,0x00,0x40,0x10, ++0x21,0x18,0x00,0x00, ++0x02,0x80,0x03,0x3C, ++0x80,0x10,0x04,0x00, ++0x0C,0xED,0x63,0x24, ++0x21,0x10,0x43,0x00, ++0x00,0x00,0x44,0x8C, ++0x00,0x00,0x00,0x00, ++0x08,0x00,0x80,0x00, ++0x00,0x00,0x00,0x00, ++0x6C,0x00,0x03,0x24, ++0x08,0x00,0xE0,0x03, ++0x21,0x10,0x60,0x00, ++0x60,0x00,0x03,0x24, ++0x08,0x00,0xE0,0x03, ++0x21,0x10,0x60,0x00, ++0x48,0x00,0x03,0x24, ++0x08,0x00,0xE0,0x03, ++0x21,0x10,0x60,0x00, ++0x30,0x00,0x03,0x24, ++0x08,0x00,0xE0,0x03, ++0x21,0x10,0x60,0x00, ++0x24,0x00,0x03,0x24, ++0x08,0x00,0xE0,0x03, ++0x21,0x10,0x60,0x00, ++0x18,0x00,0x03,0x24, ++0x08,0x00,0xE0,0x03, ++0x21,0x10,0x60,0x00, ++0x12,0x00,0x03,0x24, ++0x08,0x00,0xE0,0x03, ++0x21,0x10,0x60,0x00, ++0x0C,0x00,0x03,0x24, ++0x08,0x00,0xE0,0x03, ++0x21,0x10,0x60,0x00, ++0x16,0x00,0x03,0x24, ++0x08,0x00,0xE0,0x03, ++0x21,0x10,0x60,0x00, ++0x0B,0x00,0x03,0x24, ++0x08,0x00,0xE0,0x03, ++0x21,0x10,0x60,0x00, ++0x04,0x00,0x03,0x24, ++0x08,0x00,0xE0,0x03, ++0x21,0x10,0x60,0x00, ++0x02,0x00,0x03,0x24, ++0x08,0x00,0xE0,0x03, ++0x21,0x10,0x60,0x00, ++0xC8,0xFF,0xBD,0x27, ++0x24,0x00,0xB5,0xAF, ++0x02,0x80,0x15,0x3C, ++0x2C,0x00,0xB7,0xAF, ++0x28,0x00,0xB6,0xAF, ++0x20,0x00,0xB4,0xAF, ++0x1C,0x00,0xB3,0xAF, ++0x30,0x00,0xBF,0xAF, ++0x18,0x00,0xB2,0xAF, ++0x14,0x00,0xB1,0xAF, ++0x10,0x00,0xB0,0xAF, ++0x21,0xB8,0x80,0x00, ++0x21,0xA0,0x00,0x00, ++0x21,0x98,0x00,0x00, ++0x30,0x1F,0xB6,0x26, ++0x30,0x1F,0xA2,0x26, ++0x21,0x10,0x62,0x02, ++0xFB,0x1B,0x51,0x90, ++0xFE,0x00,0x03,0x24, ++0x1E,0x00,0x23,0x12, ++0xFF,0x00,0x02,0x24, ++0x21,0x00,0x22,0x12, ++0x21,0x10,0x80,0x02, ++0xAD,0x4F,0x00,0x0C, ++0x21,0x20,0x20,0x02, ++0x21,0x88,0x40,0x00, ++0x21,0x80,0x00,0x00, ++0x21,0x90,0xC0,0x02, ++0x21,0x10,0x12,0x02, ++0xEE,0x1B,0x44,0x90, ++0x00,0x00,0x00,0x00, ++0x02,0x00,0x82,0x24, ++0xFF,0x00,0x42,0x30, ++0x02,0x00,0x42,0x2C, ++0x05,0x00,0x40,0x14, ++0x01,0x00,0x10,0x26, ++0xAD,0x4F,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x05,0x00,0x51,0x10, ++0x01,0x00,0x03,0x24, ++0x0D,0x00,0x02,0x2A, ++0xF3,0xFF,0x40,0x14, ++0x21,0x10,0x12,0x02, ++0x21,0x18,0x00,0x00, ++0x01,0x00,0x02,0x24, ++0x14,0x00,0x62,0x10, ++0xFF,0x00,0x22,0x32, ++0x21,0x10,0xF4,0x02, ++0x00,0x00,0x51,0xA0, ++0x01,0x00,0x94,0x26, ++0x01,0x00,0x73,0x26, ++0x0D,0x00,0x62,0x2A, ++0xDB,0xFF,0x40,0x14, ++0x30,0x1F,0xA2,0x26, ++0x21,0x10,0x80,0x02, ++0x30,0x00,0xBF,0x8F, ++0x2C,0x00,0xB7,0x8F, ++0x28,0x00,0xB6,0x8F, ++0x24,0x00,0xB5,0x8F, ++0x20,0x00,0xB4,0x8F, ++0x1C,0x00,0xB3,0x8F, ++0x18,0x00,0xB2,0x8F, ++0x14,0x00,0xB1,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x08,0x00,0xE0,0x03, ++0x38,0x00,0xBD,0x27, ++0x0C,0x50,0x00,0x08, ++0x80,0x00,0x51,0x34, ++0xD0,0xFF,0xBD,0x27, ++0x24,0x00,0xB1,0xAF, ++0x20,0x00,0xB0,0xAF, ++0x21,0x88,0x80,0x00, ++0x21,0x80,0xA0,0x00, ++0x0D,0x00,0x06,0x24, ++0x21,0x28,0x00,0x00, ++0x28,0x00,0xBF,0xAF, ++0xFF,0x51,0x00,0x0C, ++0x10,0x00,0xA4,0x27, ++0xDD,0x4F,0x00,0x0C, ++0x10,0x00,0xA4,0x27, ++0x00,0x00,0x02,0xAE, ++0x21,0x20,0x20,0x02, ++0x10,0x00,0xA5,0x27, ++0x10,0x52,0x00,0x0C, ++0x21,0x30,0x40,0x00, ++0x28,0x00,0xBF,0x8F, ++0x24,0x00,0xB1,0x8F, ++0x20,0x00,0xB0,0x8F, ++0x08,0x00,0xE0,0x03, ++0x30,0x00,0xBD,0x27, ++0x21,0x28,0x00,0x00, ++0x21,0x10,0x85,0x00, ++0x00,0x00,0x43,0x90, ++0x00,0x00,0x00,0x00, ++0x04,0x00,0x60,0x10, ++0x0D,0x00,0xA2,0x2C, ++0xFA,0xFF,0x40,0x14, ++0x01,0x00,0xA5,0x24, ++0xFF,0xFF,0xA5,0x24, ++0x08,0x00,0xE0,0x03, ++0x21,0x10,0xA0,0x00, ++0x00,0x00,0x82,0x94, ++0x21,0x30,0x80,0x00, ++0x10,0x00,0x85,0x24, ++0x42,0x1A,0x02,0x00, ++0xC2,0x11,0x02,0x00, ++0x02,0x00,0x42,0x30, ++0x01,0x00,0x63,0x30, ++0x25,0x18,0x43,0x00, ++0x01,0x00,0x04,0x24, ++0x07,0x00,0x64,0x10, ++0x00,0x00,0x00,0x00, ++0x05,0x00,0x60,0x10, ++0x0A,0x00,0xC5,0x24, ++0x02,0x00,0x02,0x24, ++0x02,0x00,0x62,0x10, ++0x00,0x00,0x00,0x00, ++0x18,0x00,0xC5,0x24, ++0x08,0x00,0xE0,0x03, ++0x21,0x10,0xA0,0x00, ++0x00,0x00,0x82,0x94, ++0x21,0x30,0x80,0x00, ++0x04,0x00,0x85,0x24, ++0x42,0x1A,0x02,0x00, ++0xC2,0x11,0x02,0x00, ++0x02,0x00,0x42,0x30, ++0x01,0x00,0x63,0x30, ++0x25,0x18,0x43,0x00, ++0x01,0x00,0x04,0x24, ++0x04,0x00,0x64,0x10, ++0x00,0x00,0x00,0x00, ++0x02,0x00,0x60,0x10, ++0x00,0x00,0x00,0x00, ++0x10,0x00,0xC5,0x24, ++0x08,0x00,0xE0,0x03, ++0x21,0x10,0xA0,0x00, ++0x13,0x00,0xA0,0x18, ++0x21,0x30,0x00,0x00, ++0x02,0x00,0x07,0x24, ++0x04,0x00,0x08,0x24, ++0x0B,0x00,0x09,0x24, ++0x16,0x00,0x0A,0x24, ++0x21,0x10,0x86,0x00, ++0x00,0x00,0x43,0x90, ++0x01,0x00,0xC6,0x24, ++0x7F,0x00,0x63,0x30, ++0x07,0x00,0x67,0x10, ++0x2A,0x10,0xC5,0x00, ++0x05,0x00,0x68,0x10, ++0x00,0x00,0x00,0x00, ++0x03,0x00,0x69,0x10, ++0x00,0x00,0x00,0x00, ++0x05,0x00,0x6A,0x14, ++0x00,0x00,0x00,0x00, ++0xF3,0xFF,0x40,0x14, ++0x00,0x00,0x00,0x00, ++0x08,0x00,0xE0,0x03, ++0x01,0x00,0x02,0x24, ++0x08,0x00,0xE0,0x03, ++0x21,0x10,0x00,0x00, ++0xE8,0xFF,0xBD,0x27, ++0x10,0x00,0xB0,0xAF, ++0x14,0x00,0xBF,0xAF, ++0x02,0x80,0x02,0x3C, ++0x80,0x5D,0x43,0x8C, ++0x08,0x00,0x10,0x24, ++0x06,0x00,0xA0,0x14, ++0x0A,0x80,0x03,0x00, ++0x21,0x10,0x00,0x02, ++0x14,0x00,0xBF,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x08,0x00,0xE0,0x03, ++0x18,0x00,0xBD,0x27, ++0x65,0x50,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x01,0x00,0x03,0x36, ++0x01,0x00,0x42,0x38, ++0x03,0x00,0x04,0x36, ++0x21,0x80,0x60,0x00, ++0x0B,0x80,0x82,0x00, ++0x21,0x10,0x00,0x02, ++0x14,0x00,0xBF,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x08,0x00,0xE0,0x03, ++0x18,0x00,0xBD,0x27, ++0xD8,0xFF,0xBD,0x27, ++0x14,0x00,0xB1,0xAF, ++0x0E,0x00,0xA3,0x2C, ++0x21,0x88,0xA0,0x00, ++0x0D,0x00,0x02,0x24, ++0x0A,0x88,0x43,0x00, ++0x1C,0x00,0xB3,0xAF, ++0x18,0x00,0xB2,0xAF, ++0x10,0x00,0xB0,0xAF, ++0x24,0x00,0xBF,0xAF, ++0x20,0x00,0xB4,0xAF, ++0x21,0x98,0x80,0x00, ++0x21,0x90,0x00,0x00, ++0x15,0x00,0x20,0x12, ++0x21,0x80,0x00,0x00, ++0xAA,0x50,0x00,0x08, ++0x01,0x00,0x14,0x24, ++0x2B,0x10,0x11,0x02, ++0x11,0x00,0x40,0x10, ++0x21,0x10,0x40,0x02, ++0x21,0x18,0x70,0x02, ++0x00,0x00,0x62,0x90, ++0x00,0x00,0x00,0x00, ++0xFF,0x00,0x44,0x30, ++0x00,0x16,0x02,0x00, ++0x03,0x16,0x02,0x00, ++0xF6,0xFF,0x41,0x04, ++0x01,0x00,0x10,0x26, ++0x7D,0x4F,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x04,0x10,0x54,0x00, ++0x25,0x90,0x42,0x02, ++0x2B,0x10,0x11,0x02, ++0xF3,0xFF,0x40,0x14, ++0x21,0x18,0x70,0x02, ++0x21,0x10,0x40,0x02, ++0x24,0x00,0xBF,0x8F, ++0x20,0x00,0xB4,0x8F, ++0x1C,0x00,0xB3,0x8F, ++0x18,0x00,0xB2,0x8F, ++0x14,0x00,0xB1,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x08,0x00,0xE0,0x03, ++0x28,0x00,0xBD,0x27, ++0xD8,0xFF,0xBD,0x27, ++0x14,0x00,0xB1,0xAF, ++0x0E,0x00,0xA3,0x2C, ++0x21,0x88,0xA0,0x00, ++0x0D,0x00,0x02,0x24, ++0x0A,0x88,0x43,0x00, ++0x20,0x00,0xB4,0xAF, ++0x18,0x00,0xB2,0xAF, ++0x10,0x00,0xB0,0xAF, ++0x24,0x00,0xBF,0xAF, ++0x1C,0x00,0xB3,0xAF, ++0x21,0xA0,0x80,0x00, ++0x21,0x90,0x00,0x00, ++0x0A,0x00,0x20,0x12, ++0x21,0x80,0x00,0x00, ++0x01,0x00,0x13,0x24, ++0x21,0x10,0x90,0x02, ++0x00,0x00,0x44,0x90, ++0x7D,0x4F,0x00,0x0C, ++0x01,0x00,0x10,0x26, ++0x04,0x10,0x53,0x00, ++0x2B,0x18,0x11,0x02, ++0xF9,0xFF,0x60,0x14, ++0x25,0x90,0x42,0x02, ++0x21,0x10,0x40,0x02, ++0x24,0x00,0xBF,0x8F, ++0x20,0x00,0xB4,0x8F, ++0x1C,0x00,0xB3,0x8F, ++0x18,0x00,0xB2,0x8F, ++0x14,0x00,0xB1,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x08,0x00,0xE0,0x03, ++0x28,0x00,0xBD,0x27, ++0xE8,0xFF,0xBD,0x27, ++0xFF,0xFF,0x02,0x24, ++0x10,0x00,0xB0,0xAF, ++0x14,0x00,0xBF,0xAF, ++0x21,0x30,0xA0,0x00, ++0x1B,0x00,0x82,0x10, ++0x20,0x00,0x10,0x24, ++0x20,0x00,0x82,0x28, ++0x06,0x00,0x40,0x14, ++0x80,0x18,0x04,0x00, ++0x21,0x10,0x00,0x02, ++0x14,0x00,0xBF,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x08,0x00,0xE0,0x03, ++0x18,0x00,0xBD,0x27, ++0x21,0x18,0x64,0x00, ++0x21,0x80,0x80,0x00, ++0x02,0x80,0x02,0x3C, ++0x02,0x80,0x04,0x3C, ++0xC0,0x18,0x03,0x00, ++0x30,0x1F,0x42,0x24, ++0x2B,0x3D,0x84,0x24, ++0x21,0x20,0x64,0x00, ++0x21,0x18,0x62,0x00, ++0x01,0x00,0x02,0x24, ++0x06,0x00,0x06,0x24, ++0x10,0x52,0x00,0x0C, ++0xFA,0x1D,0x62,0xA0, ++0x21,0x10,0x00,0x02, ++0x14,0x00,0xBF,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x08,0x00,0xE0,0x03, ++0x18,0x00,0xBD,0x27, ++0x02,0x80,0x02,0x3C, ++0x30,0x1F,0x42,0x24, ++0xC8,0x00,0x47,0x24, ++0x05,0x00,0x10,0x24, ++0xC2,0x1E,0x43,0x24, ++0x10,0x51,0x00,0x08, ++0xC8,0x00,0x05,0x24, ++0x01,0x00,0x10,0x26, ++0x20,0x00,0x02,0x2E, ++0x28,0x00,0xA5,0x24, ++0xDE,0xFF,0x40,0x10, ++0x28,0x00,0xE7,0x24, ++0x00,0x00,0x62,0x90, ++0x00,0x00,0x00,0x00, ++0xF8,0xFF,0x40,0x14, ++0x28,0x00,0x63,0x24, ++0x02,0x80,0x04,0x3C, ++0x2B,0x3D,0x84,0x24, ++0x01,0x00,0x02,0x24, ++0x21,0x20,0xA4,0x00, ++0xFA,0x1D,0xE2,0xA0, ++0x21,0x28,0xC0,0x00, ++0x10,0x52,0x00,0x0C, ++0x06,0x00,0x06,0x24, ++0x00,0x51,0x00,0x08, ++0x21,0x10,0x00,0x02, ++0xE0,0xFF,0xBD,0x27, ++0x18,0x00,0xB2,0xAF, ++0x14,0x00,0xB1,0xAF, ++0x30,0x00,0xB2,0x8F, ++0x21,0x88,0x80,0x00, ++0x21,0x20,0xA0,0x00, ++0x21,0x28,0x20,0x02, ++0x10,0x00,0xB0,0xAF, ++0x1C,0x00,0xBF,0xAF, ++0xE3,0x50,0x00,0x0C, ++0xFF,0xFF,0xF0,0x30, ++0x20,0x00,0x03,0x24, ++0x21,0x20,0x40,0x00, ++0x21,0x28,0x00,0x02, ++0x21,0x30,0x20,0x02, ++0x07,0x00,0x43,0x10, ++0x21,0x38,0x40,0x02, ++0x1C,0x00,0xBF,0x8F, ++0x18,0x00,0xB2,0x8F, ++0x14,0x00,0xB1,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x4E,0x23,0x00,0x08, ++0x20,0x00,0xBD,0x27, ++0x1C,0x00,0xBF,0x8F, ++0x18,0x00,0xB2,0x8F, ++0x14,0x00,0xB1,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x08,0x00,0xE0,0x03, ++0x20,0x00,0xBD,0x27, ++0xD0,0xFF,0xBD,0x27, ++0x02,0x80,0x02,0x3C, ++0x02,0x80,0x03,0x3C, ++0x24,0x00,0xB5,0xAF, ++0x20,0x00,0xB4,0xAF, ++0x1C,0x00,0xB3,0xAF, ++0x18,0x00,0xB2,0xAF, ++0x14,0x00,0xB1,0xAF, ++0x10,0x00,0xB0,0xAF, ++0x21,0xA8,0x80,0x00, ++0x30,0x1F,0x54,0x24, ++0x2B,0x3D,0x73,0x24, ++0x05,0x00,0x11,0x24, ++0x01,0x00,0x12,0x24, ++0xC8,0x00,0x10,0x24, ++0x50,0x51,0x00,0x08, ++0x28,0x00,0xBF,0xAF, ++0x01,0x00,0x31,0x26, ++0x20,0x00,0x22,0x2A, ++0x0E,0x00,0x40,0x10, ++0x21,0x10,0x20,0x02, ++0x21,0x10,0x14,0x02, ++0xFA,0x1D,0x43,0x90, ++0x21,0x20,0x13,0x02, ++0x21,0x28,0xA0,0x02, ++0x06,0x00,0x06,0x24, ++0xF6,0xFF,0x72,0x14, ++0x28,0x00,0x10,0x26, ++0x39,0x52,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0xF3,0xFF,0x40,0x14, ++0x01,0x00,0x31,0x26, ++0xFF,0xFF,0x31,0x26, ++0x21,0x10,0x20,0x02, ++0x28,0x00,0xBF,0x8F, ++0x24,0x00,0xB5,0x8F, ++0x20,0x00,0xB4,0x8F, ++0x1C,0x00,0xB3,0x8F, ++0x18,0x00,0xB2,0x8F, ++0x14,0x00,0xB1,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x08,0x00,0xE0,0x03, ++0x30,0x00,0xBD,0x27, ++0xD0,0xFF,0xBD,0x27, ++0x02,0x80,0x02,0x3C, ++0x02,0x80,0x03,0x3C, ++0x28,0x00,0xB6,0xAF, ++0x24,0x00,0xB5,0xAF, ++0x20,0x00,0xB4,0xAF, ++0x1C,0x00,0xB3,0xAF, ++0x14,0x00,0xB1,0xAF, ++0x10,0x00,0xB0,0xAF, ++0x21,0x98,0x80,0x00, ++0x30,0x1F,0x56,0x24, ++0x2B,0x3D,0x75,0x24, ++0x21,0x88,0x00,0x00, ++0x01,0x00,0x14,0x24, ++0x21,0x80,0x00,0x00, ++0x2C,0x00,0xBF,0xAF, ++0x7C,0x51,0x00,0x08, ++0x18,0x00,0xB2,0xAF, ++0x01,0x00,0x31,0x26, ++0x20,0x00,0x22,0x2A, ++0x1E,0x00,0x40,0x10, ++0x00,0x00,0x00,0x00, ++0x21,0x90,0x16,0x02, ++0xFA,0x1D,0x42,0x92, ++0x21,0x20,0x15,0x02, ++0x21,0x28,0x60,0x02, ++0x06,0x00,0x06,0x24, ++0xF6,0xFF,0x54,0x14, ++0x28,0x00,0x10,0x26, ++0x39,0x52,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0xF3,0xFF,0x40,0x14, ++0x01,0x00,0x31,0x26, ++0xFF,0xFF,0x31,0x26, ++0x02,0x80,0x06,0x3C, ++0x02,0x80,0x07,0x3C, ++0x21,0x20,0x20,0x02, ++0xFA,0x1D,0x40,0xA2, ++0x2C,0x00,0xBF,0x8F, ++0x28,0x00,0xB6,0x8F, ++0x24,0x00,0xB5,0x8F, ++0x20,0x00,0xB4,0x8F, ++0x1C,0x00,0xB3,0x8F, ++0x18,0x00,0xB2,0x8F, ++0x14,0x00,0xB1,0x8F, ++0x10,0x00,0xB0,0x8F, ++0xE8,0xDD,0xC6,0x24, ++0xD8,0xDD,0xE7,0x24, ++0x21,0x28,0x00,0x00, ++0x4E,0x23,0x00,0x08, ++0x30,0x00,0xBD,0x27, ++0x2C,0x00,0xBF,0x8F, ++0x28,0x00,0xB6,0x8F, ++0x24,0x00,0xB5,0x8F, ++0x20,0x00,0xB4,0x8F, ++0x1C,0x00,0xB3,0x8F, ++0x18,0x00,0xB2,0x8F, ++0x14,0x00,0xB1,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x08,0x00,0xE0,0x03, ++0x30,0x00,0xBD,0x27, ++0xC8,0xFF,0xBD,0x27, ++0x02,0x80,0x02,0x3C, ++0x18,0x00,0xB2,0xAF, ++0x30,0x1F,0x52,0x24, ++0x30,0x00,0xBE,0xAF, ++0x2C,0x00,0xB7,0xAF, ++0x28,0x00,0xB6,0xAF, ++0x24,0x00,0xB5,0xAF, ++0x20,0x00,0xB4,0xAF, ++0x1C,0x00,0xB3,0xAF, ++0x14,0x00,0xB1,0xAF, ++0x10,0x00,0xB0,0xAF, ++0x34,0x00,0xBF,0xAF, ++0x21,0x80,0x00,0x00, ++0x02,0x80,0x1E,0x3C, ++0x02,0x80,0x17,0x3C, ++0x02,0x80,0x16,0x3C, ++0x01,0x00,0x13,0x24, ++0xFF,0xF7,0x15,0x24, ++0xFF,0xEF,0x14,0x24, ++0x21,0x88,0x40,0x02, ++0xFA,0x1D,0x22,0x92, ++0xC0,0x48,0x10,0x00, ++0xEA,0x5D,0xC7,0x93, ++0x41,0x00,0x53,0x10, ++0x21,0x30,0x32,0x01, ++0xE8,0x22,0xC2,0x8C, ++0xBF,0xFF,0x03,0x24, ++0x24,0x28,0x43,0x00, ++0x80,0x07,0xA3,0x34, ++0x24,0x10,0x75,0x00, ++0x31,0x00,0xF3,0x10, ++0x24,0x10,0x54,0x00, ++0xE8,0x22,0xC2,0xAC, ++0x21,0x48,0x32,0x01, ++0xE8,0x22,0x23,0x8D, ++0xFD,0xFF,0x02,0x3C, ++0xFF,0xFF,0x42,0x34, ++0x24,0x18,0x62,0x00, ++0xFB,0xFF,0x02,0x3C, ++0xFF,0xFF,0x42,0x34, ++0x24,0x18,0x62,0x00, ++0xE7,0xFF,0x02,0x3C, ++0xFF,0xFF,0x42,0x34, ++0x24,0x18,0x62,0x00, ++0xFF,0xFD,0x02,0x3C, ++0xFF,0xFF,0x42,0x34, ++0xEC,0x22,0x28,0x8D, ++0x24,0x18,0x62,0x00, ++0xFF,0xFB,0x02,0x3C, ++0xFF,0xFF,0x42,0x34, ++0x24,0x18,0x62,0x00, ++0xFF,0xE7,0x02,0x3C, ++0xFF,0xFF,0x42,0x34, ++0x1F,0x00,0x06,0x3C, ++0x00,0x80,0x08,0x35, ++0x24,0x18,0x62,0x00, ++0x25,0x40,0x06,0x01, ++0x21,0x20,0x00,0x02, ++0xE8,0x22,0x23,0xAD, ++0x01,0x00,0x10,0x26, ++0x21,0x28,0x00,0x00, ++0xE8,0xDD,0xE6,0x26, ++0xD8,0xDD,0xC7,0x26, ++0x4E,0x23,0x00,0x0C, ++0xEC,0x22,0x28,0xAD, ++0x20,0x00,0x03,0x2A, ++0xD1,0xFF,0x60,0x14, ++0x28,0x00,0x31,0x26, ++0x34,0x00,0xBF,0x8F, ++0x30,0x00,0xBE,0x8F, ++0x2C,0x00,0xB7,0x8F, ++0x28,0x00,0xB6,0x8F, ++0x24,0x00,0xB5,0x8F, ++0x20,0x00,0xB4,0x8F, ++0x1C,0x00,0xB3,0x8F, ++0x18,0x00,0xB2,0x8F, ++0x14,0x00,0xB1,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x08,0x00,0xE0,0x03, ++0x38,0x00,0xBD,0x27, ++0x02,0x80,0x02,0x3C, ++0xEB,0x5D,0x44,0x90, ++0x24,0x18,0x75,0x00, ++0x80,0x0F,0xA2,0x34, ++0x00,0x10,0x63,0x34, ++0xCA,0xFF,0x87,0x14, ++0x24,0x10,0x54,0x00, ++0xC5,0x51,0x00,0x08, ++0xE8,0x22,0xC3,0xAC, ++0xBD,0x51,0x00,0x08, ++0xFA,0x1D,0x20,0xA2, ++0x04,0x52,0x00,0x08, ++0xFF,0x00,0xA5,0x30, ++0x00,0x00,0x85,0xA0, ++0xFF,0xFF,0xC6,0x24, ++0x01,0x00,0x84,0x24, ++0xFC,0xFF,0xC0,0x14, ++0x00,0x00,0x00,0x00, ++0x08,0x00,0xE0,0x03, ++0x00,0x00,0x00,0x00, ++0x05,0x00,0xC0,0x10, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x85,0xAC, ++0xFF,0xFF,0xC6,0x24, ++0xFD,0xFF,0xC0,0x14, ++0x04,0x00,0x84,0x24, ++0x08,0x00,0xE0,0x03, ++0x00,0x00,0x00,0x00, ++0x21,0x38,0x80,0x00, ++0x08,0x00,0xC0,0x10, ++0xFF,0xFF,0xC3,0x24, ++0xFF,0xFF,0x06,0x24, ++0x00,0x00,0xA2,0x90, ++0xFF,0xFF,0x63,0x24, ++0x01,0x00,0xA5,0x24, ++0x00,0x00,0xE2,0xA0, ++0xFB,0xFF,0x66,0x14, ++0x01,0x00,0xE7,0x24, ++0x08,0x00,0xE0,0x03, ++0x21,0x10,0x80,0x00, ++0x2B,0x10,0xA4,0x00, ++0x0D,0x00,0x40,0x14, ++0xFF,0xFF,0x02,0x24, ++0xFF,0xFF,0xC6,0x24, ++0x08,0x00,0xC2,0x10, ++0x21,0x18,0x80,0x00, ++0xFF,0xFF,0x07,0x24, ++0x00,0x00,0xA2,0x90, ++0xFF,0xFF,0xC6,0x24, ++0x01,0x00,0xA5,0x24, ++0x00,0x00,0x62,0xA0, ++0xFB,0xFF,0xC7,0x14, ++0x01,0x00,0x63,0x24, ++0x08,0x00,0xE0,0x03, ++0x21,0x10,0x80,0x00, ++0x21,0x28,0xA6,0x00, ++0x21,0x18,0x86,0x00, ++0xFF,0xFF,0xC6,0x24, ++0xFA,0xFF,0xC2,0x10, ++0x00,0x00,0x00,0x00, ++0xFF,0xFF,0x07,0x24, ++0xFF,0xFF,0xA5,0x24, ++0x00,0x00,0xA2,0x90, ++0xFF,0xFF,0x63,0x24, ++0xFF,0xFF,0xC6,0x24, ++0xFB,0xFF,0xC7,0x14, ++0x00,0x00,0x62,0xA0, ++0x08,0x00,0xE0,0x03, ++0x21,0x10,0x80,0x00, ++0x0C,0x00,0xC0,0x10, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x82,0x90, ++0x00,0x00,0xA3,0x90, ++0x01,0x00,0x84,0x24, ++0x23,0x10,0x43,0x00, ++0x00,0x16,0x02,0x00, ++0x03,0x16,0x02,0x00, ++0x04,0x00,0x40,0x14, ++0x01,0x00,0xA5,0x24, ++0xFF,0xFF,0xC6,0x24, ++0xF6,0xFF,0xC0,0x14, ++0x00,0x00,0x00,0x00, ++0x08,0x00,0xE0,0x03, ++0x21,0x10,0xC0,0x00, ++0x4F,0x52,0x00,0x08, ++0x21,0x18,0x86,0x00, ++0x00,0x00,0x82,0x90, ++0x00,0x00,0x00,0x00, ++0x04,0x00,0x45,0x10, ++0x00,0x00,0x00,0x00, ++0x01,0x00,0x84,0x24, ++0xFA,0xFF,0x83,0x14, ++0x00,0x00,0x00,0x00, ++0x08,0x00,0xE0,0x03, ++0x21,0x10,0x80,0x00, ++0x09,0x00,0xC0,0x10, ++0xFF,0xFF,0xC3,0x24, ++0xFF,0x00,0xA5,0x30, ++0xFF,0xFF,0x06,0x24, ++0x00,0x00,0x82,0x90, ++0xFF,0xFF,0x63,0x24, ++0x05,0x00,0x45,0x10, ++0x01,0x00,0x84,0x24, ++0xFB,0xFF,0x66,0x14, ++0x00,0x00,0x00,0x00, ++0x08,0x00,0xE0,0x03, ++0x21,0x10,0x00,0x00, ++0x08,0x00,0xE0,0x03, ++0xFF,0xFF,0x82,0x24, ++0x21,0x38,0x00,0x00, ++0x1F,0x00,0xC0,0x10, ++0x21,0x18,0x00,0x00, ++0x02,0x80,0x02,0x3C, ++0x40,0xF2,0x4B,0x24, ++0x00,0x00,0x87,0x90, ++0x00,0x00,0xA3,0x90, ++0xFF,0xFF,0xC6,0x24, ++0x01,0x00,0x84,0x24, ++0x21,0x10,0xEB,0x00, ++0x16,0x00,0xE0,0x10, ++0x01,0x00,0xA5,0x24, ++0x14,0x00,0x60,0x10, ++0x21,0x48,0x6B,0x00, ++0x10,0x00,0xE3,0x10, ++0x20,0x00,0xE8,0x24, ++0x00,0x00,0x42,0x90, ++0x00,0x00,0x00,0x00, ++0x01,0x00,0x42,0x30, ++0x02,0x00,0x40,0x10, ++0x20,0x00,0x6A,0x24, ++0xFF,0x00,0x07,0x31, ++0x00,0x00,0x22,0x91, ++0x00,0x00,0x00,0x00, ++0x01,0x00,0x42,0x30, ++0x02,0x00,0x40,0x10, ++0xFF,0x00,0xE7,0x30, ++0xFF,0x00,0x43,0x31, ++0xFF,0x00,0x63,0x30, ++0x03,0x00,0xE3,0x14, ++0x00,0x00,0x00,0x00, ++0xE5,0xFF,0xC0,0x14, ++0x00,0x00,0x00,0x00, ++0x08,0x00,0xE0,0x03, ++0x23,0x10,0xE3,0x00, ++0x21,0x18,0x80,0x00, ++0x00,0x00,0xA2,0x90, ++0x01,0x00,0xA5,0x24, ++0x00,0x00,0x82,0xA0, ++0xFC,0xFF,0x40,0x14, ++0x01,0x00,0x84,0x24, ++0x08,0x00,0xE0,0x03, ++0x21,0x10,0x60,0x00, ++0x21,0x38,0x80,0x00, ++0xFF,0xFF,0x03,0x24, ++0xFF,0xFF,0xC6,0x24, ++0x06,0x00,0xC3,0x10, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0xA2,0x90, ++0x01,0x00,0xA5,0x24, ++0x00,0x00,0x82,0xA0, ++0xF9,0xFF,0x40,0x14, ++0x01,0x00,0x84,0x24, ++0x08,0x00,0xE0,0x03, ++0x21,0x10,0xE0,0x00, ++0x00,0x00,0x82,0x80, ++0x9E,0x52,0x00,0x08, ++0x21,0x18,0x80,0x00, ++0x01,0x00,0x84,0x24, ++0x00,0x00,0x82,0x80, ++0x00,0x00,0x00,0x00, ++0xFC,0xFF,0x40,0x14, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0xA2,0x90, ++0x01,0x00,0xA5,0x24, ++0x00,0x00,0x82,0xA0, ++0xFC,0xFF,0x40,0x14, ++0x01,0x00,0x84,0x24, ++0x08,0x00,0xE0,0x03, ++0x21,0x10,0x60,0x00, ++0x12,0x00,0xC0,0x10, ++0x21,0x18,0x80,0x00, ++0x00,0x00,0x82,0x80, ++0xAF,0x52,0x00,0x08, ++0x00,0x00,0x00,0x00, ++0x01,0x00,0x84,0x24, ++0x00,0x00,0x82,0x80, ++0x00,0x00,0x00,0x00, ++0xFC,0xFF,0x40,0x14, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0xA2,0x90, ++0x01,0x00,0xA5,0x24, ++0x00,0x00,0x82,0xA0, ++0x05,0x00,0x40,0x10, ++0x01,0x00,0x84,0x24, ++0xFF,0xFF,0xC6,0x24, ++0xF9,0xFF,0xC0,0x14, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x80,0xA0, ++0x08,0x00,0xE0,0x03, ++0x21,0x10,0x60,0x00, ++0x00,0x00,0x83,0x90, ++0x00,0x00,0xA2,0x90, ++0x01,0x00,0x84,0x24, ++0x23,0x10,0x62,0x00, ++0x00,0x16,0x02,0x00, ++0x03,0x16,0x02,0x00, ++0x03,0x00,0x40,0x14, ++0x01,0x00,0xA5,0x24, ++0xF7,0xFF,0x60,0x14, ++0x00,0x00,0x00,0x00, ++0x08,0x00,0xE0,0x03, ++0x00,0x00,0x00,0x00, ++0x21,0x10,0x00,0x00, ++0x0B,0x00,0xC0,0x10, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0xA2,0x90, ++0x00,0x00,0x83,0x90, ++0xFF,0xFF,0xC6,0x24, ++0x23,0x10,0x62,0x00, ++0x00,0x16,0x02,0x00, ++0x03,0x16,0x02,0x00, ++0x03,0x00,0x40,0x14, ++0x01,0x00,0xA5,0x24, ++0xF5,0xFF,0x60,0x14, ++0x01,0x00,0x84,0x24, ++0x08,0x00,0xE0,0x03, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x83,0x80, ++0x00,0x2E,0x05,0x00, ++0x21,0x10,0x80,0x00, ++0xE0,0x52,0x00,0x08, ++0x03,0x2E,0x05,0x00, ++0x07,0x00,0x60,0x10, ++0x01,0x00,0x42,0x24, ++0x00,0x00,0x43,0x80, ++0x00,0x00,0x00,0x00, ++0xFB,0xFF,0x65,0x14, ++0x00,0x00,0x00,0x00, ++0x08,0x00,0xE0,0x03, ++0x00,0x00,0x00,0x00, ++0x08,0x00,0xE0,0x03, ++0x21,0x10,0x00,0x00, ++0x00,0x00,0x82,0x80, ++0xEC,0x52,0x00,0x08, ++0x21,0x18,0x80,0x00, ++0x01,0x00,0x63,0x24, ++0x00,0x00,0x62,0x80, ++0x00,0x00,0x00,0x00, ++0xFC,0xFF,0x40,0x14, ++0x23,0x10,0x64,0x00, ++0x08,0x00,0xE0,0x03, ++0x00,0x00,0x00,0x00, ++0xE0,0xFF,0xBD,0x27, ++0x10,0x00,0xB0,0xAF, ++0x21,0x80,0xA0,0x00, ++0x14,0x00,0xB1,0xAF, ++0x18,0x00,0xBF,0xAF, ++0x21,0x88,0x80,0x00, ++0xE6,0x52,0x00,0x0C, ++0x00,0x86,0x10,0x00, ++0x21,0x18,0x51,0x00, ++0x03,0x86,0x10,0x00, ++0x00,0x00,0x62,0x80, ++0x00,0x00,0x00,0x00, ++0x0A,0x00,0x50,0x10, ++0x21,0x10,0x60,0x00, ++0xFF,0xFF,0x63,0x24, ++0x2B,0x10,0x71,0x00, ++0xF9,0xFF,0x40,0x10, ++0x21,0x10,0x00,0x00, ++0x18,0x00,0xBF,0x8F, ++0x14,0x00,0xB1,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x08,0x00,0xE0,0x03, ++0x20,0x00,0xBD,0x27, ++0x18,0x00,0xBF,0x8F, ++0x14,0x00,0xB1,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x08,0x00,0xE0,0x03, ++0x20,0x00,0xBD,0x27, ++0x21,0x30,0x80,0x00, ++0x0D,0x00,0xA0,0x10, ++0xFF,0xFF,0xA3,0x24, ++0x00,0x00,0x82,0x80, ++0x00,0x00,0x00,0x00, ++0x09,0x00,0x40,0x10, ++0x00,0x00,0x00,0x00, ++0xFF,0xFF,0x05,0x24, ++0xFF,0xFF,0x63,0x24, ++0x05,0x00,0x65,0x10, ++0x01,0x00,0xC6,0x24, ++0x00,0x00,0xC2,0x80, ++0x00,0x00,0x00,0x00, ++0xFA,0xFF,0x40,0x14, ++0x00,0x00,0x00,0x00, ++0x08,0x00,0xE0,0x03, ++0x23,0x10,0xC4,0x00, ++0x00,0x00,0x82,0x90, ++0x00,0x00,0x00,0x00, ++0x19,0x00,0x40,0x10, ++0x21,0x40,0x00,0x00, ++0x00,0x00,0xA9,0x80, ++0x00,0x00,0x00,0x00, ++0x17,0x00,0x20,0x11, ++0x21,0x30,0xA0,0x00, ++0x00,0x3E,0x02,0x00, ++0x03,0x3E,0x07,0x00, ++0x21,0x18,0x20,0x01, ++0x15,0x00,0xE3,0x10, ++0x00,0x00,0x00,0x00, ++0x01,0x00,0xC6,0x24, ++0x00,0x00,0xC2,0x90, ++0x00,0x00,0x00,0x00, ++0x00,0x1E,0x02,0x00, ++0x03,0x1E,0x03,0x00, ++0xF8,0xFF,0x60,0x14, ++0x00,0x16,0x02,0x00, ++0x03,0x16,0x02,0x00, ++0x06,0x00,0x40,0x10, ++0x00,0x00,0x00,0x00, ++0x01,0x00,0x84,0x24, ++0x00,0x00,0x82,0x90, ++0x00,0x00,0x00,0x00, ++0xEB,0xFF,0x40,0x14, ++0x01,0x00,0x08,0x25, ++0x08,0x00,0xE0,0x03, ++0x21,0x10,0x00,0x01, ++0x00,0x00,0xA2,0x90, ++0x31,0x53,0x00,0x08, ++0x00,0x16,0x02,0x00, ++0x00,0x00,0xC2,0x90, ++0x31,0x53,0x00,0x08, ++0x00,0x16,0x02,0x00, ++0x00,0x00,0x87,0x90, ++0x00,0x00,0x00,0x00, ++0x14,0x00,0xE0,0x10, ++0x21,0x10,0x80,0x00, ++0x00,0x00,0xA4,0x90, ++0x00,0x00,0x00,0x00, ++0x00,0x1E,0x04,0x00, ++0x03,0x1E,0x03,0x00, ++0x09,0x00,0x60,0x10, ++0x21,0x30,0xA0,0x00, ++0x00,0x3E,0x07,0x00, ++0x03,0x3E,0x07,0x00, ++0x0B,0x00,0xE3,0x10, ++0x01,0x00,0xC6,0x24, ++0x00,0x00,0xC3,0x80, ++0x00,0x00,0x00,0x00, ++0xFB,0xFF,0x60,0x14, ++0x00,0x00,0x00,0x00, ++0x01,0x00,0x42,0x24, ++0x00,0x00,0x47,0x90, ++0x00,0x00,0x00,0x00, ++0xF0,0xFF,0xE0,0x14, ++0x00,0x00,0x00,0x00, ++0x21,0x10,0x00,0x00, ++0x08,0x00,0xE0,0x03, ++0x00,0x00,0x00,0x00, ++0xE0,0xFF,0xBD,0x27, ++0x14,0x00,0xB1,0xAF, ++0x10,0x00,0xB0,0xAF, ++0x18,0x00,0xBF,0xAF, ++0x21,0x80,0x80,0x00, ++0x1D,0x00,0x80,0x10, ++0x21,0x88,0xA0,0x00, ++0x1D,0x53,0x00,0x0C, ++0x21,0x20,0x00,0x02, ++0x21,0x80,0x02,0x02, ++0x00,0x00,0x02,0x82, ++0x21,0x28,0x20,0x02, ++0x21,0x20,0x00,0x02, ++0x22,0x00,0x40,0x10, ++0x21,0x18,0x00,0x00, ++0x41,0x53,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x05,0x00,0x40,0x10, ++0x21,0x18,0x40,0x00, ++0x00,0x00,0x42,0x80, ++0x00,0x00,0x00,0x00, ++0x0A,0x00,0x40,0x14, ++0x00,0x00,0x00,0x00, ++0x02,0x80,0x02,0x3C, ++0x5C,0xF3,0x43,0xAC, ++0x21,0x18,0x00,0x02, ++0x18,0x00,0xBF,0x8F, ++0x14,0x00,0xB1,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x21,0x10,0x60,0x00, ++0x08,0x00,0xE0,0x03, ++0x20,0x00,0xBD,0x27, ++0x00,0x00,0x60,0xA0, ++0x72,0x53,0x00,0x08, ++0x01,0x00,0x63,0x24, ++0x02,0x80,0x02,0x3C, ++0x5C,0xF3,0x50,0x8C, ++0x00,0x00,0x00,0x00, ++0xF3,0xFF,0x00,0x12, ++0x21,0x18,0x00,0x00, ++0x1D,0x53,0x00,0x0C, ++0x21,0x20,0x00,0x02, ++0x21,0x80,0x02,0x02, ++0x00,0x00,0x02,0x82, ++0x21,0x28,0x20,0x02, ++0x21,0x20,0x00,0x02, ++0xE0,0xFF,0x40,0x14, ++0x21,0x18,0x00,0x00, ++0x18,0x00,0xBF,0x8F, ++0x14,0x00,0xB1,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x02,0x80,0x02,0x3C, ++0x5C,0xF3,0x40,0xAC, ++0x20,0x00,0xBD,0x27, ++0x08,0x00,0xE0,0x03, ++0x21,0x10,0x60,0x00, ++0xE0,0xFF,0xBD,0x27, ++0x18,0x00,0xB2,0xAF, ++0x14,0x00,0xB1,0xAF, ++0x1C,0x00,0xBF,0xAF, ++0x10,0x00,0xB0,0xAF, ++0x00,0x00,0x90,0x8C, ++0x21,0x90,0x80,0x00, ++0x21,0x88,0xA0,0x00, ++0x21,0x18,0x00,0x00, ++0x0F,0x00,0x00,0x12, ++0x21,0x20,0x00,0x02, ++0x1D,0x53,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x21,0x80,0x02,0x02, ++0x00,0x00,0x02,0x82, ++0x21,0x28,0x20,0x02, ++0x21,0x20,0x00,0x02, ++0x07,0x00,0x40,0x10, ++0x21,0x18,0x00,0x00, ++0x41,0x53,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x21,0x18,0x40,0x00, ++0x09,0x00,0x40,0x14, ++0x00,0x00,0x42,0xAE, ++0x21,0x18,0x00,0x02, ++0x1C,0x00,0xBF,0x8F, ++0x18,0x00,0xB2,0x8F, ++0x14,0x00,0xB1,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x21,0x10,0x60,0x00, ++0x08,0x00,0xE0,0x03, ++0x20,0x00,0xBD,0x27, ++0x00,0x00,0x42,0x80, ++0x00,0x00,0x00,0x00, ++0xF5,0xFF,0x40,0x10, ++0x01,0x00,0x64,0x24, ++0x00,0x00,0x60,0xA0, ++0xAB,0x53,0x00,0x08, ++0x00,0x00,0x44,0xAE, ++0xD8,0xFF,0xBD,0x27, ++0x14,0x00,0xB1,0xAF, ++0x21,0x88,0x80,0x00, ++0x21,0x20,0xA0,0x00, ++0x1C,0x00,0xB3,0xAF, ++0x18,0x00,0xB2,0xAF, ++0x20,0x00,0xBF,0xAF, ++0x10,0x00,0xB0,0xAF, ++0xE6,0x52,0x00,0x0C, ++0x21,0x98,0xA0,0x00, ++0x21,0x90,0x40,0x00, ++0x08,0x00,0x40,0x16, ++0x21,0x10,0x20,0x02, ++0x20,0x00,0xBF,0x8F, ++0x1C,0x00,0xB3,0x8F, ++0x18,0x00,0xB2,0x8F, ++0x14,0x00,0xB1,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x08,0x00,0xE0,0x03, ++0x28,0x00,0xBD,0x27, ++0xE6,0x52,0x00,0x0C, ++0x21,0x20,0x20,0x02, ++0x21,0x80,0x40,0x00, ++0x2A,0x10,0x52,0x00, ++0x0A,0x00,0x40,0x14, ++0x00,0x00,0x00,0x00, ++0x21,0x20,0x20,0x02, ++0x21,0x28,0x60,0x02, ++0x21,0x30,0x40,0x02, ++0x39,0x52,0x00,0x0C, ++0xFF,0xFF,0x10,0x26, ++0x0B,0x00,0x40,0x10, ++0x2A,0x18,0x12,0x02, ++0xF8,0xFF,0x60,0x10, ++0x01,0x00,0x31,0x26, ++0x20,0x00,0xBF,0x8F, ++0x1C,0x00,0xB3,0x8F, ++0x18,0x00,0xB2,0x8F, ++0x14,0x00,0xB1,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x21,0x10,0x00,0x00, ++0x08,0x00,0xE0,0x03, ++0x28,0x00,0xBD,0x27, ++0xC7,0x53,0x00,0x08, ++0x21,0x10,0x20,0x02, ++0x00,0x00,0x87,0x90, ++0x00,0x00,0x00,0x00, ++0x27,0x00,0xE0,0x10, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0xA6,0x90, ++0x00,0x00,0x00,0x00, ++0x0A,0x00,0xC0,0x10, ++0xDF,0xFF,0x02,0x24, ++0x24,0x18,0xC2,0x00, ++0x24,0x10,0xE2,0x00, ++0x00,0x16,0x02,0x00, ++0x00,0x1E,0x03,0x00, ++0x03,0x16,0x02,0x00, ++0x03,0x1E,0x03,0x00, ++0x0A,0x00,0x43,0x10, ++0x00,0x00,0x00,0x00, ++0xDF,0xFF,0x02,0x24, ++0x24,0x18,0xC2,0x00, ++0x24,0x10,0xE2,0x00, ++0x00,0x16,0x02,0x00, ++0x00,0x1E,0x03,0x00, ++0x03,0x1E,0x03,0x00, ++0x03,0x16,0x02,0x00, ++0x08,0x00,0xE0,0x03, ++0x23,0x10,0x43,0x00, ++0x0A,0x54,0x00,0x08, ++0xDF,0xFF,0x08,0x24, ++0x00,0x00,0xA6,0x90, ++0x00,0x00,0x00,0x00, ++0x24,0x10,0x06,0x01, ++0x00,0x16,0x02,0x00, ++0xF0,0xFF,0xC0,0x10, ++0x03,0x16,0x02,0x00, ++0xEF,0xFF,0x62,0x14, ++0xDF,0xFF,0x02,0x24, ++0x01,0x00,0x84,0x24, ++0x00,0x00,0x87,0x90, ++0x01,0x00,0xA5,0x24, ++0x24,0x10,0x07,0x01, ++0x00,0x1E,0x02,0x00, ++0xF2,0xFF,0xE0,0x14, ++0x03,0x1E,0x03,0x00, ++0x00,0x00,0xA6,0x90, ++0xDF,0xFF,0x02,0x24, ++0x24,0x18,0xC2,0x00, ++0x24,0x10,0xE2,0x00, ++0x00,0x16,0x02,0x00, ++0x00,0x1E,0x03,0x00, ++0x03,0x1E,0x03,0x00, ++0x03,0x16,0x02,0x00, ++0x08,0x00,0xE0,0x03, ++0x23,0x10,0x43,0x00, ++0xA8,0xFF,0xBD,0x27, ++0x44,0x00,0xB5,0xAF, ++0x40,0x00,0xB4,0xAF, ++0x38,0x00,0xB2,0xAF, ++0x34,0x00,0xB1,0xAF, ++0x54,0x00,0xBF,0xAF, ++0x50,0x00,0xBE,0xAF, ++0x4C,0x00,0xB7,0xAF, ++0x48,0x00,0xB6,0xAF, ++0x3C,0x00,0xB3,0xAF, ++0x30,0x00,0xB0,0xAF, ++0x21,0x90,0xA0,0x00, ++0x00,0x00,0xA5,0x90, ++0x21,0xA0,0x80,0x00, ++0x21,0xA8,0xC0,0x00, ++0x00,0x26,0x05,0x00, ++0x03,0x26,0x04,0x00, ++0x11,0x00,0x80,0x10, ++0x21,0x88,0x80,0x02, ++0x25,0x00,0x02,0x24, ++0x29,0x00,0x82,0x10, ++0x0A,0x00,0x02,0x24, ++0x1B,0x00,0x82,0x10, ++0x00,0x00,0x00,0x00, ++0x1E,0x00,0x80,0x12, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x25,0xA2, ++0x01,0x00,0x31,0x26, ++0x01,0x00,0x52,0x26, ++0x00,0x00,0x45,0x92, ++0x00,0x00,0x00,0x00, ++0x00,0x26,0x05,0x00, ++0x03,0x26,0x04,0x00, ++0xF2,0xFF,0x80,0x14, ++0x25,0x00,0x02,0x24, ++0x02,0x00,0x80,0x12, ++0x23,0x10,0x34,0x02, ++0x00,0x00,0x20,0xA2, ++0x54,0x00,0xBF,0x8F, ++0x50,0x00,0xBE,0x8F, ++0x4C,0x00,0xB7,0x8F, ++0x48,0x00,0xB6,0x8F, ++0x44,0x00,0xB5,0x8F, ++0x40,0x00,0xB4,0x8F, ++0x3C,0x00,0xB3,0x8F, ++0x38,0x00,0xB2,0x8F, ++0x34,0x00,0xB1,0x8F, ++0x30,0x00,0xB0,0x8F, ++0x08,0x00,0xE0,0x03, ++0x58,0x00,0xBD,0x27, ++0xE7,0xFF,0x80,0x16, ++0x00,0x00,0x00,0x00, ++0x77,0x55,0x00,0x0C, ++0x0D,0x00,0x04,0x24, ++0x0A,0x00,0x04,0x24, ++0x77,0x55,0x00,0x0C, ++0x01,0x00,0x52,0x26, ++0x00,0x00,0x45,0x92, ++0x00,0x00,0x00,0x00, ++0x00,0x26,0x05,0x00, ++0x3C,0x54,0x00,0x08, ++0x03,0x26,0x04,0x00, ++0x01,0x00,0x52,0x26, ++0x00,0x00,0x45,0x92, ++0x73,0x00,0x02,0x24, ++0x00,0x1E,0x05,0x00, ++0x03,0x1E,0x03,0x00, ++0x2C,0x00,0x62,0x10, ++0x10,0x00,0xB3,0x27, ++0x23,0x00,0x02,0x24, ++0x21,0xF0,0x60,0x02, ++0x21,0x38,0x00,0x00, ++0x34,0x00,0x62,0x10, ++0x1C,0x00,0x04,0x24, ++0x00,0x16,0x05,0x00, ++0x03,0x16,0x02,0x00, ++0x68,0x00,0x03,0x24, ++0x36,0x00,0x43,0x10, ++0x00,0x00,0x00,0x00, ++0x00,0x16,0x05,0x00, ++0x03,0x16,0x02,0x00, ++0x39,0x00,0x43,0x10, ++0x00,0x00,0x00,0x00, ++0x20,0x00,0xA2,0x34, ++0x00,0x16,0x02,0x00, ++0x03,0x16,0x02,0x00, ++0x78,0x00,0x03,0x24, ++0x3C,0x00,0x43,0x10, ++0x20,0x00,0xA6,0x30, ++0x00,0x1E,0x05,0x00, ++0x03,0x1E,0x03,0x00, ++0x64,0x00,0x02,0x24, ++0x49,0x00,0x62,0x10, ++0x40,0x00,0x02,0x24, ++0x81,0x00,0x62,0x10, ++0x21,0x00,0x02,0x24, ++0x92,0x00,0x62,0x10, ++0x63,0x00,0x02,0x24, ++0xA2,0x00,0x62,0x10, ++0x11,0x00,0xB3,0x27, ++0x10,0x00,0xA5,0xA3, ++0x21,0x80,0xC0,0x03, ++0x2B,0x10,0x13,0x02, ++0xB4,0xFF,0x40,0x10, ++0x00,0x00,0x00,0x00, ++0x6C,0x00,0x80,0x12, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x02,0x92, ++0x01,0x00,0x10,0x26, ++0x00,0x00,0x22,0xA2, ++0x81,0x54,0x00,0x08, ++0x01,0x00,0x31,0x26, ++0x00,0x00,0xA2,0x8E, ++0x04,0x00,0xB5,0x26, ++0x21,0x80,0x40,0x00, ++0x00,0x00,0x02,0x92, ++0x00,0x00,0x00,0x00, ++0xA6,0xFF,0x40,0x10, ++0x00,0x00,0x00,0x00, ++0x63,0x00,0x80,0x12, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x22,0xA2, ++0x01,0x00,0x10,0x26, ++0x8E,0x54,0x00,0x08, ++0x01,0x00,0x31,0x26, ++0x01,0x00,0x52,0x26, ++0x00,0x00,0x45,0x92, ++0x68,0x00,0x03,0x24, ++0x00,0x16,0x05,0x00, ++0x03,0x16,0x02,0x00, ++0xCC,0xFF,0x43,0x14, ++0x01,0x00,0x07,0x24, ++0x01,0x00,0x52,0x26, ++0x00,0x00,0x45,0x92, ++0x00,0x00,0x00,0x00, ++0x00,0x16,0x05,0x00, ++0x03,0x16,0x02,0x00, ++0xC9,0xFF,0x43,0x14, ++0x0C,0x00,0x04,0x24, ++0x01,0x00,0x52,0x26, ++0x00,0x00,0x45,0x92, ++0x78,0x00,0x03,0x24, ++0x20,0x00,0xA2,0x34, ++0x00,0x16,0x02,0x00, ++0x03,0x16,0x02,0x00, ++0xC7,0xFF,0x43,0x14, ++0x04,0x00,0x04,0x24, ++0x20,0x00,0xA6,0x30, ++0x00,0x00,0xA5,0x8E, ++0x35,0x00,0xE0,0x14, ++0x04,0x00,0xB5,0x26, ++0xCD,0xFF,0x80,0x04, ++0x02,0x80,0x02,0x3C, ++0x48,0xED,0x42,0x24, ++0x00,0x00,0x47,0x8C, ++0x07,0x10,0x85,0x00, ++0x0F,0x00,0x42,0x30, ++0x21,0x10,0x47,0x00, ++0x00,0x00,0x43,0x90, ++0xFC,0xFF,0x84,0x24, ++0x25,0x18,0xC3,0x00, ++0x00,0x00,0x63,0xA2, ++0xF8,0xFF,0x81,0x04, ++0x01,0x00,0x73,0x26, ++0x81,0x54,0x00,0x08, ++0x21,0x80,0xC0,0x03, ++0x00,0x00,0xA2,0x8E, ++0x04,0x00,0xB5,0x26, ++0x28,0x00,0x40,0x04, ++0x21,0x28,0x40,0x00, ++0x21,0x80,0x60,0x02, ++0x02,0x80,0x02,0x3C, ++0x4C,0xED,0x42,0x24, ++0x00,0x00,0x46,0x8C, ++0x00,0x00,0x00,0x00, ++0x18,0x00,0xA6,0x00, ++0xC3,0x27,0x05,0x00, ++0x10,0x10,0x00,0x00, ++0x83,0x10,0x02,0x00, ++0x23,0x10,0x44,0x00, ++0x80,0x18,0x02,0x00, ++0x21,0x18,0x62,0x00, ++0x40,0x18,0x03,0x00, ++0x23,0x18,0xA3,0x00, ++0x30,0x00,0x63,0x24, ++0x00,0x00,0x63,0xA2, ++0x21,0x28,0x40,0x00, ++0xF3,0xFF,0x40,0x14, ++0x01,0x00,0x73,0x26, ++0xE1,0x54,0x00,0x08, ++0xFF,0xFF,0x63,0x26, ++0x00,0x00,0x65,0x80, ++0x00,0x00,0x02,0x92, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x62,0xA0, ++0x00,0x00,0x05,0xA2, ++0xFF,0xFF,0x63,0x24, ++0x01,0x00,0x10,0x26, ++0x2B,0x10,0x03,0x02, ++0xF7,0xFF,0x40,0x14, ++0x00,0x00,0x00,0x00, ++0x81,0x54,0x00,0x08, ++0x21,0x80,0xC0,0x03, ++0x58,0x00,0xC3,0x34, ++0x30,0x00,0x02,0x24, ++0x12,0x00,0xB3,0x27, ++0x10,0x00,0xA2,0xA3, ++0xB2,0x54,0x00,0x08, ++0x11,0x00,0xA3,0xA3, ++0x2D,0x00,0x02,0x24, ++0x23,0x28,0x05,0x00, ++0x11,0x00,0xB3,0x27, ++0xC5,0x54,0x00,0x08, ++0x10,0x00,0xA2,0xA3, ++0x00,0x00,0x04,0x82, ++0x77,0x55,0x00,0x0C, ++0x01,0x00,0x10,0x26, ++0x82,0x54,0x00,0x08, ++0x2B,0x10,0x13,0x02, ++0x00,0x00,0x04,0x82, ++0x77,0x55,0x00,0x0C, ++0x01,0x00,0x10,0x26, ++0x8E,0x54,0x00,0x08, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0xA3,0x8E, ++0x28,0x00,0xB0,0x27, ++0x2C,0x00,0xA4,0x27, ++0x2B,0x10,0x04,0x02, ++0x28,0x00,0xA3,0xAF, ++0x0B,0x00,0x40,0x10, ++0x04,0x00,0xB5,0x26, ++0x21,0xB8,0x80,0x00, ++0x02,0x80,0x16,0x3C, ++0x00,0x00,0x06,0x92, ++0x21,0x20,0x60,0x02, ++0x01,0x00,0x10,0x26, ++0x24,0x55,0x00,0x0C, ++0xD0,0xE3,0xC5,0x26, ++0x2B,0x18,0x17,0x02, ++0xF9,0xFF,0x60,0x14, ++0x21,0x98,0x62,0x02, ++0x80,0x54,0x00,0x08, ++0xFF,0xFF,0x73,0x26, ++0x00,0x00,0xA2,0x8E, ++0x00,0x00,0x00,0x00, ++0x06,0x00,0x56,0x24, ++0x21,0x80,0x40,0x00, ++0x2B,0x10,0x56,0x00, ++0xF8,0xFF,0x40,0x10, ++0x04,0x00,0xB5,0x26, ++0x02,0x80,0x17,0x3C, ++0x00,0x00,0x06,0x82, ++0x21,0x20,0x60,0x02, ++0x01,0x00,0x10,0x26, ++0x24,0x55,0x00,0x0C, ++0xD4,0xE3,0xE5,0x26, ++0x2B,0x18,0x16,0x02, ++0xF9,0xFF,0x60,0x14, ++0x21,0x98,0x62,0x02, ++0x80,0x54,0x00,0x08, ++0xFF,0xFF,0x73,0x26, ++0x00,0x00,0xA2,0x8E, ++0x04,0x00,0xB5,0x26, ++0x80,0x54,0x00,0x08, ++0x10,0x00,0xA2,0xA3, ++0xE8,0xFF,0xBD,0x27, ++0x20,0x00,0xA6,0xAF, ++0x20,0x00,0xA6,0x27, ++0x10,0x00,0xBF,0xAF, ++0x24,0x00,0xA7,0xAF, ++0x1B,0x54,0x00,0x0C, ++0x1C,0x00,0xA5,0xAF, ++0x10,0x00,0xBF,0x8F, ++0x00,0x00,0x00,0x00, ++0x08,0x00,0xE0,0x03, ++0x18,0x00,0xBD,0x27, ++0xE0,0xFF,0xBD,0x27, ++0x18,0x00,0xBF,0xAF, ++0x14,0x00,0xB1,0xAF, ++0x10,0x00,0xB0,0xAF, ++0x24,0x00,0xA5,0xAF, ++0x28,0x00,0xA6,0xAF, ++0x2C,0x00,0xA7,0xAF, ++0x20,0x00,0xA4,0xAF, ++0x00,0x60,0x11,0x40, ++0x01,0x00,0x21,0x36, ++0x01,0x00,0x21,0x38, ++0x00,0x60,0x81,0x40, ++0x25,0x24,0x00,0x0C, ++0xA0,0x00,0x04,0x24, ++0x19,0x00,0x40,0x10, ++0x21,0x80,0x40,0x00, ++0x08,0x00,0x44,0x94, ++0x20,0x00,0xA5,0x8F, ++0x02,0x80,0x02,0x3C, ++0x25,0x20,0x82,0x00, ++0x20,0x00,0x84,0x24, ++0x1B,0x54,0x00,0x0C, ++0x24,0x00,0xA6,0x27, ++0x01,0x00,0x42,0x24, ++0x13,0x00,0x03,0x24, ++0x81,0x00,0x44,0x2C, ++0x14,0x00,0x03,0xAE, ++0x17,0x00,0x80,0x14, ++0x0C,0x00,0x02,0xAE, ++0x00,0x60,0x01,0x40, ++0x01,0x00,0x21,0x34, ++0x01,0x00,0x21,0x38, ++0x00,0x60,0x81,0x40, ++0x88,0x88,0x03,0x3C, ++0x25,0xB0,0x02,0x3C, ++0x88,0x88,0x63,0x34, ++0x18,0x03,0x42,0x34, ++0x00,0x00,0x43,0xAC, ++0x55,0x55,0x00,0x08, ++0x00,0x00,0x00,0x00, ++0x00,0x60,0x91,0x40, ++0x99,0x99,0x03,0x3C, ++0x25,0xB0,0x02,0x3C, ++0x99,0x99,0x63,0x34, ++0x18,0x03,0x42,0x34, ++0x00,0x00,0x43,0xAC, ++0x18,0x00,0xBF,0x8F, ++0x14,0x00,0xB1,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x08,0x00,0xE0,0x03, ++0x20,0x00,0xBD,0x27, ++0x30,0x09,0x00,0x0C, ++0x21,0x20,0x00,0x02, ++0x00,0x60,0x91,0x40, ++0x5D,0x55,0x00,0x08, ++0x00,0x00,0x00,0x00, ++0xE8,0xFF,0xBD,0x27, ++0x10,0x00,0xBF,0xAF, ++0x02,0x80,0x06,0x3C, ++0x60,0xF3,0xC5,0x8C, ++0x02,0x80,0x02,0x3C, ++0x40,0xF3,0x42,0x24, ++0x03,0x00,0xA3,0x30, ++0x21,0x18,0x62,0x00, ++0x00,0x00,0x64,0x80, ++0x01,0x00,0xA5,0x24, ++0x77,0x55,0x00,0x0C, ++0x60,0xF3,0xC5,0xAC, ++0x10,0x00,0xBF,0x8F, ++0x08,0x00,0x04,0x24, ++0x77,0x55,0x00,0x08, ++0x18,0x00,0xBD,0x27, ++0x00,0x26,0x04,0x00, ++0x03,0x26,0x04,0x00, ++0x00,0x00,0x84,0x48, ++0x08,0x00,0xE0,0x03, ++0x00,0x00,0x00,0x00, ++0x00,0x26,0x04,0x00, ++0x03,0x26,0x04,0x00, ++0xF7,0xFF,0x82,0x24, ++0x05,0x00,0x42,0x2C, ++0x06,0x00,0x40,0x14, ++0x21,0x18,0x00,0x00, ++0x20,0x00,0x02,0x24, ++0x03,0x00,0x82,0x10, ++0x00,0x00,0x00,0x00, ++0x08,0x00,0xE0,0x03, ++0x21,0x10,0x60,0x00, ++0x01,0x00,0x03,0x24, ++0x08,0x00,0xE0,0x03, ++0x21,0x10,0x60,0x00, ++0x00,0x60,0x02,0x40, ++0x01,0x00,0x41,0x34, ++0x01,0x00,0x21,0x38, ++0x00,0x60,0x81,0x40, ++0x02,0x80,0x03,0x3C, ++0xD4,0x5E,0x64,0xAC, ++0x00,0x60,0x82,0x40, ++0x08,0x00,0xE0,0x03, ++0x00,0x00,0x00,0x00, ++0x25,0xB0,0x05,0x3C, ++0x01,0x00,0x06,0x24, ++0x01,0x80,0x02,0x3C, ++0x04,0x30,0x86,0x00, ++0xF1,0x02,0xA7,0x34, ++0xED,0x02,0xA4,0x34, ++0x4C,0x56,0x42,0x24, ++0x18,0x03,0xA5,0x34, ++0x08,0x00,0x03,0x24, ++0x00,0x00,0xA2,0xAC, ++0x00,0x00,0xE3,0xA0, ++0x00,0x00,0x80,0xA0, ++0x00,0x00,0x86,0xA0, ++0x00,0x00,0x80,0xA0, ++0x00,0x00,0x86,0xA0, ++0x00,0x00,0x80,0xA0, ++0x00,0x00,0x86,0xA0, ++0x00,0x00,0x80,0xA0, ++0x00,0x00,0x86,0xA0, ++0x00,0x00,0x80,0xA0, ++0x00,0x00,0xE0,0xA0, ++0x08,0x00,0xE0,0x03, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x82,0x8C, ++0x08,0x00,0xE0,0x03, ++0x00,0x00,0x00,0x00, ++0xFF,0xFF,0xC6,0x30, ++0x10,0x00,0x02,0x24, ++0x0C,0x00,0xC2,0x10, ++0x11,0x00,0xC3,0x28, ++0x06,0x00,0x60,0x10, ++0x20,0x00,0x02,0x24, ++0x08,0x00,0x02,0x24, ++0x0D,0x00,0xC2,0x10, ++0x00,0x00,0x00,0x00, ++0x08,0x00,0xE0,0x03, ++0x00,0x00,0x00,0x00, ++0x06,0x00,0xC2,0x10, ++0x00,0x00,0x00,0x00, ++0x08,0x00,0xE0,0x03, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x85,0xA4, ++0x08,0x00,0xE0,0x03, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x85,0xAC, ++0x08,0x00,0xE0,0x03, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x85,0xA0, ++0x08,0x00,0xE0,0x03, ++0x00,0x00,0x00,0x00, ++0x08,0x00,0xE0,0x03, ++0x21,0x10,0x00,0x00, ++0x08,0x00,0xE0,0x03, ++0x21,0x10,0x00,0x00, ++0x25,0xB0,0x02,0x3C, ++0x0A,0x00,0x42,0x34, ++0x00,0x00,0x43,0x90, ++0xFF,0xFF,0xA5,0x24, ++0x00,0x2C,0x05,0x00, ++0xFD,0x00,0x63,0x30, ++0x03,0x2C,0x05,0x00, ++0xFF,0xFF,0x87,0x30, ++0x00,0x00,0x43,0xA0, ++0x1A,0x00,0xA0,0x04, ++0x00,0x00,0x00,0x00, ++0x21,0x30,0x40,0x00, ++0x07,0x10,0xA7,0x00, ++0x01,0x00,0x42,0x30, ++0xFD,0x00,0x64,0x30, ++0x00,0x00,0x42,0x38, ++0x02,0x00,0x63,0x34, ++0x0A,0x18,0x82,0x00, ++0x00,0x00,0xC3,0xA0, ++0x04,0x00,0x63,0x34, ++0x00,0x00,0xC3,0xA0, ++0x09,0x00,0x02,0x24, ++0xFF,0xFF,0x42,0x24, ++0xFF,0xFF,0x41,0x04, ++0xFF,0xFF,0x42,0x24, ++0xFB,0x00,0x63,0x30, ++0x00,0x00,0xC3,0xA0, ++0x04,0x00,0x02,0x24, ++0xFF,0xFF,0x42,0x24, ++0xFF,0xFF,0x41,0x04, ++0xFF,0xFF,0x42,0x24, ++0xFF,0xFF,0xA2,0x24, ++0x00,0x2C,0x02,0x00, ++0x03,0x2C,0x05,0x00, ++0xEA,0xFF,0xA1,0x04, ++0x07,0x10,0xA7,0x00, ++0x08,0x00,0xE0,0x03, ++0x00,0x00,0x00,0x00, ++0x25,0xB0,0x02,0x3C, ++0x0A,0x00,0x42,0x34, ++0x00,0x00,0x43,0x90, ++0xFF,0xFF,0x84,0x24, ++0x00,0x24,0x04,0x00, ++0x03,0x24,0x04,0x00, ++0xFF,0x00,0x65,0x30, ++0x1D,0x00,0x80,0x04, ++0x21,0x38,0x00,0x00, ++0x21,0x30,0x40,0x00, ++0x01,0x00,0x08,0x24, ++0x04,0x00,0xA5,0x34, ++0x00,0x00,0xC5,0xA0, ++0x00,0x00,0xC2,0x90, ++0x00,0x00,0x00,0x00, ++0xFF,0x00,0x45,0x30, ++0x01,0x00,0xA3,0x30, ++0x05,0x00,0x60,0x10, ++0x04,0x00,0x02,0x24, ++0x04,0x10,0x88,0x00, ++0x25,0x10,0x47,0x00, ++0xFF,0xFF,0x47,0x30, ++0x04,0x00,0x02,0x24, ++0xFF,0xFF,0x42,0x24, ++0xFF,0xFF,0x41,0x04, ++0xFF,0xFF,0x42,0x24, ++0xFB,0x00,0xA5,0x30, ++0x00,0x00,0xC5,0xA0, ++0x09,0x00,0x02,0x24, ++0xFF,0xFF,0x42,0x24, ++0xFF,0xFF,0x41,0x04, ++0xFF,0xFF,0x42,0x24, ++0xFF,0xFF,0x82,0x24, ++0x00,0x24,0x02,0x00, ++0x03,0x24,0x04,0x00, ++0xE7,0xFF,0x81,0x04, ++0x00,0x00,0x00,0x00, ++0x08,0x00,0xE0,0x03, ++0x21,0x10,0xE0,0x00, ++0xE0,0xFF,0xBD,0x27, ++0x10,0x00,0xB0,0xAF, ++0x25,0xB0,0x10,0x3C, ++0x0A,0x00,0x10,0x36, ++0x18,0x00,0xBF,0xAF, ++0x14,0x00,0xB1,0xAF, ++0x00,0x00,0x02,0x92, ++0xFF,0xFF,0x91,0x30, ++0x03,0x00,0x05,0x24, ++0xC0,0x00,0x42,0x30, ++0x80,0x00,0x43,0x34, ++0x00,0x00,0x03,0xA2, ++0x04,0x00,0x63,0x34, ++0x00,0x00,0x03,0xA2, ++0xFB,0x00,0x63,0x30, ++0x00,0x00,0x03,0xA2, ++0x08,0x00,0x63,0x34, ++0x00,0x00,0x03,0xA2, ++0x04,0x00,0x63,0x34, ++0x00,0x00,0x03,0xA2, ++0xFB,0x00,0x63,0x30, ++0x00,0x00,0x03,0xA2, ++0xC9,0x55,0x00,0x0C, ++0x06,0x00,0x04,0x24, ++0x42,0x20,0x11,0x00, ++0xC9,0x55,0x00,0x0C, ++0x06,0x00,0x05,0x24, ++0xEF,0x55,0x00,0x0C, ++0x10,0x00,0x04,0x24, ++0x00,0x00,0x03,0x92, ++0x18,0x00,0xBF,0x8F, ++0x14,0x00,0xB1,0x8F, ++0xC0,0x00,0x63,0x30, ++0x00,0x00,0x03,0xA2, ++0x10,0x00,0xB0,0x8F, ++0x08,0x00,0xE0,0x03, ++0x20,0x00,0xBD,0x27, ++0xE0,0xFF,0xBD,0x27, ++0x14,0x00,0xB1,0xAF, ++0xFF,0xFF,0xB1,0x30, ++0x18,0x00,0xB2,0xAF, ++0x10,0x00,0xB0,0xAF, ++0x1C,0x00,0xBF,0xAF, ++0x21,0x90,0xC0,0x00, ++0x0A,0x00,0x20,0x12, ++0xFF,0xFF,0x90,0x30, ++0x16,0x56,0x00,0x0C, ++0x21,0x20,0x00,0x02, ++0xFE,0xFF,0x23,0x26, ++0x02,0x00,0x04,0x26, ++0x00,0x00,0x42,0xA6, ++0xFF,0xFF,0x71,0x30, ++0xFF,0xFF,0x90,0x30, ++0xF8,0xFF,0x20,0x16, ++0x02,0x00,0x52,0x26, ++0x1C,0x00,0xBF,0x8F, ++0x18,0x00,0xB2,0x8F, ++0x14,0x00,0xB1,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x08,0x00,0xE0,0x03, ++0x20,0x00,0xBD,0x27, ++0xC8,0xFF,0xBD,0x27, ++0x25,0xB0,0x03,0x3C, ++0x1C,0x00,0xB3,0xAF, ++0x18,0x00,0xB2,0xAF, ++0x14,0x00,0xB1,0xAF, ++0x10,0x00,0xB0,0xAF, ++0x34,0x00,0xBF,0xAF, ++0x30,0x00,0xBE,0xAF, ++0x2C,0x00,0xB7,0xAF, ++0x28,0x00,0xB6,0xAF, ++0x24,0x00,0xB5,0xAF, ++0x20,0x00,0xB4,0xAF, ++0x0A,0x00,0x67,0x34, ++0x00,0x00,0xE2,0x90, ++0xFF,0xFF,0xB2,0x30, ++0x21,0x98,0xC0,0x00, ++0xFF,0x00,0x91,0x30, ++0x20,0x00,0x40,0x12, ++0xFF,0x00,0x50,0x30, ++0x21,0xA0,0xE0,0x00, ++0x0C,0x00,0x77,0x34, ++0x0B,0x00,0x76,0x34, ++0x21,0xF0,0xE0,0x00, ++0xC0,0xFF,0x15,0x24, ++0x25,0x10,0x15,0x02, ++0xFF,0x00,0x50,0x30, ++0x00,0x00,0xD1,0xA2, ++0x00,0x00,0x90,0xA2, ++0x00,0x00,0x82,0x92, ++0x00,0x00,0x00,0x00, ++0xFF,0x00,0x50,0x30, ++0xC0,0x00,0x03,0x32, ++0x07,0x00,0x60,0x10, ++0x21,0x20,0xC0,0x03, ++0x00,0x00,0x82,0x90, ++0x00,0x00,0x00,0x00, ++0xFF,0x00,0x50,0x30, ++0xC0,0x00,0x03,0x32, ++0xFB,0xFF,0x60,0x14, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0xE2,0x8E, ++0x04,0x00,0x23,0x26, ++0x64,0x00,0x04,0x24, ++0x00,0x00,0x62,0xAE, ++0x25,0x22,0x00,0x0C, ++0xFF,0x00,0x71,0x30, ++0xFC,0xFF,0x42,0x26, ++0xFF,0xFF,0x52,0x30, ++0xE7,0xFF,0x40,0x16, ++0x04,0x00,0x73,0x26, ++0x34,0x00,0xBF,0x8F, ++0x30,0x00,0xBE,0x8F, ++0x2C,0x00,0xB7,0x8F, ++0x28,0x00,0xB6,0x8F, ++0x24,0x00,0xB5,0x8F, ++0x20,0x00,0xB4,0x8F, ++0x1C,0x00,0xB3,0x8F, ++0x18,0x00,0xB2,0x8F, ++0x14,0x00,0xB1,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x08,0x00,0xE0,0x03, ++0x38,0x00,0xBD,0x27, ++0x25,0xB0,0x06,0x3C, ++0x31,0x00,0xC2,0x34, ++0xFF,0xFF,0x84,0x30, ++0x00,0x00,0x44,0xA0, ++0x32,0x00,0xC7,0x34, ++0x00,0x00,0xE3,0x90, ++0xFC,0xFF,0x02,0x24, ++0x02,0x22,0x04,0x00, ++0x24,0x18,0x62,0x00, ++0x03,0x00,0x84,0x30, ++0x25,0x20,0x83,0x00, ++0x33,0x00,0xC6,0x34, ++0x72,0x00,0x02,0x24, ++0x00,0x00,0xE4,0xA0, ++0x00,0x00,0xC2,0xA0, ++0x00,0x00,0xC3,0x90, ++0x00,0x00,0x00,0x00, ++0x00,0x1E,0x03,0x00, ++0x03,0x1E,0x03,0x00, ++0x05,0x00,0x61,0x04, ++0x21,0x10,0x00,0x00, ++0xB5,0x56,0x00,0x08, ++0x25,0xB0,0x02,0x3C, ++0x11,0x00,0x80,0x10, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0xC3,0x90, ++0x01,0x00,0x42,0x24, ++0xFF,0x00,0x42,0x30, ++0x00,0x1E,0x03,0x00, ++0x03,0x1E,0x03,0x00, ++0xF8,0xFF,0x61,0x04, ++0x64,0x00,0x44,0x2C, ++0x64,0x00,0x44,0x2C, ++0x07,0x00,0x80,0x10, ++0x00,0x00,0x00,0x00, ++0x25,0xB0,0x02,0x3C, ++0x30,0x00,0x42,0x34, ++0x00,0x00,0x43,0x90, ++0x01,0x00,0x02,0x24, ++0x08,0x00,0xE0,0x03, ++0x00,0x00,0xA3,0xA0, ++0xFF,0xFF,0x02,0x24, ++0x00,0x00,0xA2,0xA0, ++0x08,0x00,0xE0,0x03, ++0x21,0x10,0x00,0x00, ++0x25,0xB0,0x06,0x3C, ++0x31,0x00,0xC2,0x34, ++0xFF,0xFF,0x84,0x30, ++0x00,0x00,0x44,0xA0, ++0x32,0x00,0xC3,0x34, ++0x00,0x00,0x62,0x90, ++0x02,0x22,0x04,0x00, ++0x03,0x00,0x84,0x30, ++0x25,0x20,0x82,0x00, ++0x00,0x00,0x64,0xA0, ++0x33,0x00,0xC7,0x34, ++0xFF,0x00,0xA5,0x30, ++0x30,0x00,0xC6,0x34, ++0xF2,0xFF,0x03,0x24, ++0x00,0x00,0xC5,0xA0, ++0x00,0x00,0xE3,0xA0, ++0x00,0x00,0xE2,0x90, ++0x00,0x00,0x00,0x00, ++0x00,0x16,0x02,0x00, ++0x03,0x16,0x02,0x00, ++0x03,0x00,0x40,0x04, ++0x21,0x20,0x00,0x00, ++0x08,0x00,0xE0,0x03, ++0x01,0x00,0x02,0x24, ++0xDA,0x56,0x00,0x08, ++0x21,0x30,0xE0,0x00, ++0x0B,0x00,0x40,0x10, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0xC3,0x90, ++0x01,0x00,0x82,0x24, ++0xFF,0x00,0x44,0x30, ++0x00,0x1E,0x03,0x00, ++0x03,0x1E,0x03,0x00, ++0xF8,0xFF,0x60,0x04, ++0x64,0x00,0x82,0x2C, ++0x64,0x00,0x82,0x2C, ++0xF1,0xFF,0x40,0x14, ++0x00,0x00,0x00,0x00, ++0x08,0x00,0xE0,0x03, ++0x21,0x10,0x00,0x00, ++0xE0,0xFF,0xBD,0x27, ++0x25,0xB0,0x02,0x3C, ++0x18,0x00,0xB0,0xAF, ++0xF8,0x02,0x45,0x34, ++0x25,0xB0,0x10,0x3C, ++0xFF,0x00,0x83,0x30, ++0x01,0x00,0x02,0x24, ++0x1C,0x00,0xBF,0xAF, ++0x03,0x00,0x06,0x36, ++0x0A,0x00,0x62,0x10, ++0x0A,0x00,0x04,0x24, ++0x00,0x00,0xA2,0x90, ++0x1C,0x00,0xBF,0x8F, ++0x18,0x00,0xB0,0x8F, ++0xFE,0xFF,0x03,0x24, ++0x24,0x10,0x43,0x00, ++0x20,0x00,0xBD,0x27, ++0x00,0x00,0xA2,0xA0, ++0x08,0x00,0xE0,0x03, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0xC2,0x90, ++0x00,0x00,0x00,0x00, ++0xFF,0x00,0x42,0x30, ++0x20,0x00,0x43,0x34, ++0x20,0x00,0x42,0x30, ++0x02,0x00,0x40,0x14, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0xC3,0xA0, ++0x25,0x22,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x01,0x00,0x04,0x36, ++0x00,0x00,0x82,0x90, ++0xFE,0xFF,0x03,0x24, ++0xF8,0x02,0x06,0x36, ++0x24,0x10,0x43,0x00, ++0x00,0x00,0x82,0xA0, ++0x00,0x00,0xC3,0x90, ++0x10,0x00,0xA5,0x27, ++0x21,0x20,0x00,0x00, ++0x03,0x00,0x63,0x34, ++0x00,0x00,0xC3,0xA0, ++0x91,0x56,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x1C,0x00,0xBF,0x8F, ++0x18,0x00,0xB0,0x8F, ++0x08,0x00,0xE0,0x03, ++0x20,0x00,0xBD,0x27, ++0xFF,0x00,0x84,0x30, ++0x21,0x38,0x00,0x00, ++0x21,0x28,0x00,0x00, ++0x01,0x00,0xA3,0x24, ++0x07,0x10,0xA4,0x00, ++0x01,0x00,0x42,0x30, ++0xFF,0x00,0x65,0x30, ++0x01,0x00,0xE6,0x24, ++0x02,0x00,0x40,0x14, ++0x04,0x00,0xA3,0x2C, ++0xFF,0x00,0xC7,0x30, ++0xF7,0xFF,0x60,0x14, ++0x21,0x10,0xE0,0x00, ++0x08,0x00,0xE0,0x03, ++0x00,0x00,0x00,0x00, ++0xFF,0x00,0x8C,0x30, ++0x21,0x48,0x00,0x00, ++0x21,0x38,0x00,0x00, ++0x40,0x10,0x07,0x00, ++0xFF,0x00,0x42,0x30, ++0x21,0x50,0x46,0x00, ++0x01,0x00,0xE3,0x24, ++0x07,0x10,0xEC,0x00, ++0x01,0x00,0x42,0x30, ++0xFF,0x00,0x67,0x30, ++0x21,0x58,0x25,0x01, ++0x01,0x00,0x24,0x25, ++0x09,0x00,0x40,0x14, ++0x04,0x00,0xE8,0x2C, ++0x00,0x00,0x63,0x91, ++0xFF,0x00,0x89,0x30, ++0x21,0x20,0x25,0x01, ++0x00,0x00,0x43,0xA1, ++0x00,0x00,0x83,0x90, ++0x01,0x00,0x22,0x25, ++0xFF,0x00,0x49,0x30, ++0x01,0x00,0x43,0xA1, ++0xED,0xFF,0x00,0x15, ++0x40,0x10,0x07,0x00, ++0x08,0x00,0xE0,0x03, ++0x00,0x00,0x00,0x00, ++0xD8,0xFF,0xBD,0x27, ++0x20,0x00,0xB2,0xAF, ++0x1C,0x00,0xB1,0xAF, ++0x18,0x00,0xB0,0xAF, ++0x24,0x00,0xBF,0xAF, ++0x01,0x00,0x12,0x24, ++0x21,0x80,0x00,0x00, ++0x57,0x57,0x00,0x08, ++0xFF,0x00,0x11,0x24, ++0x91,0x56,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x10,0x00,0x40,0x10, ++0x00,0x02,0x03,0x2E, ++0x0F,0x00,0x60,0x10, ++0x21,0x10,0x00,0x02, ++0x10,0x00,0xA2,0x93, ++0x00,0x00,0x00,0x00, ++0x0A,0x00,0x51,0x10, ++0x0F,0x00,0x44,0x30, ++0x15,0x57,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x40,0x10,0x02,0x00, ++0x21,0x10,0x50,0x00, ++0x01,0x00,0x42,0x24, ++0xFF,0xFF,0x50,0x30, ++0x21,0x20,0x00,0x02, ++0xEE,0xFF,0x40,0x16, ++0x10,0x00,0xA5,0x27, ++0x21,0x10,0x00,0x02, ++0x24,0x00,0xBF,0x8F, ++0x20,0x00,0xB2,0x8F, ++0x1C,0x00,0xB1,0x8F, ++0x18,0x00,0xB0,0x8F, ++0x08,0x00,0xE0,0x03, ++0x28,0x00,0xBD,0x27, ++0xB8,0xFF,0xBD,0x27, ++0x3C,0x00,0xB7,0xAF, ++0x38,0x00,0xB6,0xAF, ++0x34,0x00,0xB5,0xAF, ++0x30,0x00,0xB4,0xAF, ++0x2C,0x00,0xB3,0xAF, ++0x24,0x00,0xB1,0xAF, ++0x20,0x00,0xB0,0xAF, ++0x44,0x00,0xBF,0xAF, ++0x40,0x00,0xBE,0xAF, ++0x28,0x00,0xB2,0xAF, ++0x21,0x98,0xA0,0x00, ++0xFF,0x00,0x96,0x30, ++0x01,0x00,0x10,0x24, ++0x01,0x00,0x17,0x24, ++0x21,0xA0,0x00,0x00, ++0x21,0x88,0x00,0x00, ++0x21,0xA8,0x00,0x00, ++0x04,0x00,0xA0,0x10, ++0x21,0x18,0x00,0x00, ++0x10,0x00,0xC2,0x2E, ++0x0E,0x00,0x40,0x14, ++0x21,0x20,0xA0,0x00, ++0x44,0x00,0xBF,0x8F, ++0x40,0x00,0xBE,0x8F, ++0x3C,0x00,0xB7,0x8F, ++0x38,0x00,0xB6,0x8F, ++0x34,0x00,0xB5,0x8F, ++0x30,0x00,0xB4,0x8F, ++0x2C,0x00,0xB3,0x8F, ++0x28,0x00,0xB2,0x8F, ++0x24,0x00,0xB1,0x8F, ++0x20,0x00,0xB0,0x8F, ++0x21,0x10,0x60,0x00, ++0x08,0x00,0xE0,0x03, ++0x48,0x00,0xBD,0x27, ++0x08,0x00,0x06,0x24, ++0xFF,0x51,0x00,0x0C, ++0xFF,0x00,0x05,0x24, ++0x18,0x00,0xA4,0x27, ++0xFF,0x00,0x05,0x24, ++0xFF,0x51,0x00,0x0C, ++0x08,0x00,0x06,0x24, ++0xE6,0x56,0x00,0x0C, ++0x01,0x00,0x04,0x24, ++0x96,0x57,0x00,0x08, ++0x10,0x00,0xBE,0x27, ++0x1C,0x00,0x40,0x14, ++0x21,0x20,0xA0,0x02, ++0x37,0x00,0xE0,0x12, ++0x00,0x02,0x22,0x2E, ++0x35,0x00,0x40,0x10, ++0x00,0x00,0x00,0x00, ++0x01,0x00,0x02,0x32, ++0xF8,0xFF,0x40,0x10, ++0x20,0x00,0x02,0x32, ++0x21,0x20,0x20,0x02, ++0x91,0x56,0x00,0x0C, ++0x10,0x00,0xA5,0x27, ++0x2D,0x00,0x40,0x10, ++0xFF,0x00,0x02,0x24, ++0x10,0x00,0xB0,0x93, ++0x00,0x00,0x00,0x00, ++0x29,0x00,0x02,0x12, ++0x0F,0x00,0x15,0x32, ++0x15,0x57,0x00,0x0C, ++0x21,0x20,0xA0,0x02, ++0x02,0x81,0x10,0x00, ++0x10,0x00,0x16,0x12, ++0x21,0xA0,0x40,0x00, ++0x40,0x10,0x14,0x00, ++0x21,0x10,0x51,0x00, ++0x01,0x00,0x42,0x24, ++0xFF,0xFF,0x51,0x30, ++0x92,0x57,0x00,0x08, ++0x01,0x00,0x10,0x24, ++0x18,0x00,0xA5,0x27, ++0x24,0x57,0x00,0x0C, ++0x21,0x30,0x60,0x02, ++0x40,0x10,0x14,0x00, ++0x21,0x10,0x51,0x00, ++0x01,0x00,0x42,0x24, ++0xFF,0xFF,0x51,0x30, ++0x92,0x57,0x00,0x08, ++0x01,0x00,0x10,0x24, ++0x40,0x90,0x02,0x00, ++0x10,0x00,0x40,0x1A, ++0x21,0x80,0x00,0x00, ++0x21,0x20,0x30,0x02, ++0x01,0x00,0x84,0x24, ++0xFF,0xFF,0x84,0x30, ++0x91,0x56,0x00,0x0C, ++0x10,0x00,0xA5,0x27, ++0x01,0x00,0x03,0x26, ++0x21,0x20,0xD0,0x03, ++0xFF,0x00,0x70,0x30, ++0x04,0x00,0x40,0x10, ++0x2A,0x18,0x12,0x02, ++0x10,0x00,0xA2,0x93, ++0x00,0x00,0x00,0x00, ++0x08,0x00,0x82,0xA0, ++0xF3,0xFF,0x60,0x14, ++0x21,0x20,0x30,0x02, ++0x92,0x57,0x00,0x08, ++0x20,0x00,0x10,0x24, ++0xE6,0x56,0x00,0x0C, ++0x21,0x20,0x00,0x00, ++0x00,0x00,0x63,0x92, ++0xFF,0x00,0x02,0x24, ++0x0F,0x00,0x62,0x10, ++0x00,0x00,0x00,0x00, ++0x01,0x00,0x03,0x24, ++0x44,0x00,0xBF,0x8F, ++0x40,0x00,0xBE,0x8F, ++0x3C,0x00,0xB7,0x8F, ++0x38,0x00,0xB6,0x8F, ++0x34,0x00,0xB5,0x8F, ++0x30,0x00,0xB4,0x8F, ++0x2C,0x00,0xB3,0x8F, ++0x28,0x00,0xB2,0x8F, ++0x24,0x00,0xB1,0x8F, ++0x20,0x00,0xB0,0x8F, ++0x21,0x10,0x60,0x00, ++0x08,0x00,0xE0,0x03, ++0x48,0x00,0xBD,0x27, ++0x01,0x00,0x62,0x92, ++0x00,0x00,0x00,0x00, ++0xF0,0xFF,0x43,0x14, ++0x01,0x00,0x03,0x24, ++0x02,0x00,0x63,0x92, ++0x00,0x00,0x00,0x00, ++0xEB,0xFF,0x62,0x14, ++0x00,0x00,0x00,0x00, ++0x03,0x00,0x62,0x92, ++0x00,0x00,0x00,0x00, ++0xE8,0xFF,0x43,0x14, ++0x01,0x00,0x03,0x24, ++0x04,0x00,0x63,0x92, ++0x00,0x00,0x00,0x00, ++0xE3,0xFF,0x62,0x14, ++0x00,0x00,0x00,0x00, ++0x05,0x00,0x62,0x92, ++0x00,0x00,0x00,0x00, ++0xDF,0xFF,0x43,0x14, ++0x00,0x00,0x00,0x00, ++0x06,0x00,0x67,0x92, ++0x00,0x00,0x00,0x00, ++0xDC,0xFF,0xE2,0x14, ++0x01,0x00,0x03,0x24, ++0x07,0x00,0x62,0x92, ++0x00,0x00,0x00,0x00, ++0x7F,0xFF,0x47,0x10, ++0x21,0x18,0x00,0x00, ++0xD1,0x57,0x00,0x08, ++0x01,0x00,0x03,0x24, ++0xC0,0xFF,0xBD,0x27, ++0x38,0x00,0xBE,0xAF, ++0x30,0x00,0xB6,0xAF, ++0x2C,0x00,0xB5,0xAF, ++0x21,0xF0,0xC0,0x00, ++0xFF,0x00,0xB6,0x30, ++0xFF,0xFF,0x95,0x30, ++0xFF,0x00,0x05,0x24, ++0x10,0x00,0xA4,0x27, ++0x08,0x00,0x06,0x24, ++0x34,0x00,0xB7,0xAF, ++0x24,0x00,0xB3,0xAF, ++0x3C,0x00,0xBF,0xAF, ++0x28,0x00,0xB4,0xAF, ++0x20,0x00,0xB2,0xAF, ++0x1C,0x00,0xB1,0xAF, ++0x18,0x00,0xB0,0xAF, ++0xFF,0x51,0x00,0x0C, ++0x0F,0x00,0x17,0x24, ++0x21,0x98,0x00,0x00, ++0x40,0x10,0x13,0x00, ++0xFF,0x00,0x52,0x30, ++0x07,0x10,0x76,0x02, ++0x01,0x00,0x42,0x30, ++0x21,0xA0,0x5E,0x02, ++0x21,0x88,0xA0,0x02, ++0x21,0x20,0xA0,0x02, ++0x13,0x00,0x40,0x10, ++0x01,0x00,0xA3,0x26, ++0x01,0x00,0x62,0x26, ++0xFF,0x00,0x53,0x30, ++0x04,0x00,0x63,0x2E, ++0xF4,0xFF,0x60,0x14, ++0x40,0x10,0x13,0x00, ++0x21,0x10,0xE0,0x02, ++0x3C,0x00,0xBF,0x8F, ++0x38,0x00,0xBE,0x8F, ++0x34,0x00,0xB7,0x8F, ++0x30,0x00,0xB6,0x8F, ++0x2C,0x00,0xB5,0x8F, ++0x28,0x00,0xB4,0x8F, ++0x24,0x00,0xB3,0x8F, ++0x20,0x00,0xB2,0x8F, ++0x1C,0x00,0xB1,0x8F, ++0x18,0x00,0xB0,0x8F, ++0x08,0x00,0xE0,0x03, ++0x40,0x00,0xBD,0x27, ++0x00,0x00,0x85,0x92, ++0xFF,0xFF,0x75,0x30, ++0xBE,0x56,0x00,0x0C, ++0x21,0x80,0xA0,0x02, ++0x01,0x00,0x85,0x92, ++0x21,0x20,0xA0,0x02, ++0x01,0x00,0xA2,0x26, ++0xBE,0x56,0x00,0x0C, ++0xFF,0xFF,0x55,0x30, ++0x10,0x00,0xA3,0x27, ++0x21,0x90,0x72,0x00, ++0x21,0x20,0x20,0x02, ++0x91,0x56,0x00,0x0C, ++0x21,0x28,0x40,0x02, ++0x21,0x20,0x00,0x02, ++0x91,0x56,0x00,0x0C, ++0x01,0x00,0x45,0x26, ++0x00,0x00,0x84,0x92, ++0x00,0x00,0x42,0x92, ++0x01,0x00,0x03,0x24, ++0x04,0x18,0x63,0x02, ++0x03,0x00,0x82,0x10, ++0x27,0x30,0x03,0x00, ++0x19,0x58,0x00,0x08, ++0x24,0xB8,0xD7,0x00, ++0x01,0x00,0x83,0x92, ++0x01,0x00,0x42,0x92, ++0x00,0x00,0x00,0x00, ++0xD2,0xFF,0x62,0x10, ++0x01,0x00,0x62,0x26, ++0x1A,0x58,0x00,0x08, ++0x24,0xB8,0xD7,0x00, ++0x98,0xFF,0xBD,0x27, ++0x50,0x00,0xB4,0xAF, ++0xFF,0x00,0x94,0x30, ++0x01,0x00,0x04,0x24, ++0x64,0x00,0xBF,0xAF, ++0x60,0x00,0xBE,0xAF, ++0x5C,0x00,0xB7,0xAF, ++0x58,0x00,0xB6,0xAF, ++0x4C,0x00,0xB3,0xAF, ++0x48,0x00,0xB2,0xAF, ++0x44,0x00,0xB1,0xAF, ++0x21,0x98,0xC0,0x00, ++0xFF,0x00,0xB1,0x30, ++0x54,0x00,0xB5,0xAF, ++0xE6,0x56,0x00,0x0C, ++0x40,0x00,0xB0,0xAF, ++0x3E,0x57,0x00,0x0C, ++0x01,0x00,0x16,0x24, ++0x21,0x18,0x40,0x00, ++0xFF,0x01,0x42,0x2C, ++0x01,0x00,0x17,0x24, ++0x01,0x00,0x1E,0x24, ++0x21,0x90,0x00,0x00, ++0x0E,0x00,0x40,0x14, ++0x21,0x20,0x00,0x00, ++0x64,0x00,0xBF,0x8F, ++0x60,0x00,0xBE,0x8F, ++0x5C,0x00,0xB7,0x8F, ++0x58,0x00,0xB6,0x8F, ++0x54,0x00,0xB5,0x8F, ++0x50,0x00,0xB4,0x8F, ++0x4C,0x00,0xB3,0x8F, ++0x48,0x00,0xB2,0x8F, ++0x44,0x00,0xB1,0x8F, ++0x40,0x00,0xB0,0x8F, ++0x21,0x10,0x80,0x00, ++0x08,0x00,0xE0,0x03, ++0x68,0x00,0xBD,0x27, ++0xFF,0x01,0x02,0x24, ++0x23,0x10,0x43,0x00, ++0x1A,0x00,0xA4,0x27, ++0xFF,0x00,0x05,0x24, ++0x08,0x00,0x06,0x24, ++0xFF,0xFF,0x50,0x30, ++0x18,0x00,0xB4,0xA3, ++0xFF,0x51,0x00,0x0C, ++0x19,0x00,0xB1,0xA3, ++0x21,0x20,0x20,0x02, ++0x21,0x28,0x60,0x02, ++0x24,0x57,0x00,0x0C, ++0x1A,0x00,0xA6,0x27, ++0x19,0x00,0xA4,0x93, ++0x15,0x57,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x21,0xA8,0x40,0x00, ++0xFF,0xFF,0x42,0x30, ++0x2B,0x10,0x02,0x02, ++0xDF,0xFF,0x40,0x14, ++0x21,0x20,0x00,0x00, ++0x01,0x00,0x02,0x24, ++0x09,0x00,0xC2,0x12, ++0x20,0x00,0x02,0x24, ++0x22,0x00,0xC2,0x12, ++0x00,0x00,0x00,0x00, ++0x3B,0x00,0xE0,0x12, ++0x00,0x02,0x42,0x2E, ++0x39,0x00,0x40,0x10, ++0x01,0x00,0x02,0x24, ++0xF9,0xFF,0xC2,0x16, ++0x20,0x00,0x02,0x24, ++0x21,0x20,0x40,0x02, ++0x10,0x00,0xA5,0x27, ++0x91,0x56,0x00,0x0C, ++0x01,0x00,0x13,0x24, ++0x41,0x00,0x40,0x10, ++0xFF,0x00,0x02,0x24, ++0x10,0x00,0xA5,0x93, ++0x00,0x00,0x00,0x00, ++0xFF,0x00,0xA4,0x30, ++0x3C,0x00,0x82,0x10, ++0x0F,0x00,0xA3,0x30, ++0x02,0x11,0x04,0x00, ++0x21,0x20,0x60,0x00, ++0x29,0x00,0xA3,0xA3, ++0x28,0x00,0xA2,0xA3, ++0x15,0x57,0x00,0x0C, ++0x11,0x00,0xA5,0xA3, ++0x21,0x80,0x40,0x00, ++0x28,0x00,0xA3,0x93, ++0x18,0x00,0xA2,0x93, ++0x00,0x00,0x00,0x00, ++0x5F,0x00,0x62,0x10, ++0x40,0x10,0x10,0x00, ++0x21,0x10,0x52,0x00, ++0x01,0x00,0x42,0x24, ++0x8B,0x58,0x00,0x08, ++0xFF,0xFF,0x52,0x30, ++0x19,0x00,0xA5,0x93, ++0x01,0x00,0x44,0x26, ++0xFF,0xFF,0x84,0x30, ++0xFC,0x57,0x00,0x0C, ++0x1A,0x00,0xA6,0x27, ++0x21,0x28,0x40,0x00, ++0x0F,0x00,0x43,0x30, ++0x0F,0x00,0x02,0x24, ++0x12,0x00,0x62,0x10, ++0x40,0x10,0x15,0x00, ++0x21,0x10,0x52,0x00, ++0x01,0x00,0x42,0x24, ++0x21,0x20,0xA0,0x00, ++0xFF,0xFF,0x52,0x30, ++0x18,0x00,0xB4,0xA3, ++0x15,0x57,0x00,0x0C, ++0x19,0x00,0xA5,0xA3, ++0x21,0xA8,0x40,0x00, ++0x02,0x80,0x03,0x3C, ++0x04,0xE4,0x62,0x8C, ++0x02,0x80,0x04,0x3C, ++0x01,0x00,0x16,0x24, ++0x01,0x00,0x42,0x24, ++0x04,0x00,0x43,0x28, ++0xC6,0xFF,0x60,0x14, ++0x04,0xE4,0x82,0xAC, ++0x21,0xF0,0x00,0x00, ++0xE6,0x56,0x00,0x0C, ++0x21,0x20,0x00,0x00, ++0x21,0x20,0xC0,0x03, ++0x64,0x00,0xBF,0x8F, ++0x60,0x00,0xBE,0x8F, ++0x5C,0x00,0xB7,0x8F, ++0x58,0x00,0xB6,0x8F, ++0x54,0x00,0xB5,0x8F, ++0x50,0x00,0xB4,0x8F, ++0x4C,0x00,0xB3,0x8F, ++0x48,0x00,0xB2,0x8F, ++0x44,0x00,0xB1,0x8F, ++0x40,0x00,0xB0,0x8F, ++0x21,0x10,0x80,0x00, ++0x08,0x00,0xE0,0x03, ++0x68,0x00,0xBD,0x27, ++0x3E,0x57,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0xFF,0x01,0x03,0x24, ++0x23,0x18,0x62,0x00, ++0xFF,0xFF,0x70,0x30, ++0xFF,0xFF,0xA2,0x32, ++0x2B,0x10,0x02,0x02, ++0xE7,0xFF,0x40,0x14, ++0x21,0x20,0x40,0x02, ++0x18,0x00,0xB0,0x93, ++0x19,0x00,0xA2,0x93, ++0x00,0x81,0x10,0x00, ++0x25,0x80,0x02,0x02, ++0xFF,0x00,0x10,0x32, ++0xBE,0x56,0x00,0x0C, ++0x21,0x28,0x00,0x02, ++0x21,0x20,0x40,0x02, ++0x91,0x56,0x00,0x0C, ++0x11,0x00,0xA5,0x27, ++0x11,0x00,0xA3,0x93, ++0x00,0x00,0x00,0x00, ++0xFF,0x00,0x64,0x30, ++0x9D,0xFF,0x90,0x10, ++0x20,0x00,0x16,0x24, ++0xFF,0x00,0x02,0x24, ++0xCD,0xFF,0x82,0x10, ++0x0F,0x00,0x63,0x30, ++0x02,0x11,0x04,0x00, ++0x21,0x20,0x60,0x00, ++0x29,0x00,0xA3,0xA3, ++0x15,0x57,0x00,0x0C, ++0x28,0x00,0xA2,0xA3, ++0x38,0x00,0xA4,0x27, ++0xFF,0x00,0x05,0x24, ++0x08,0x00,0x06,0x24, ++0xFF,0x51,0x00,0x0C, ++0x21,0x80,0x40,0x00, ++0x28,0x00,0xA4,0x93, ++0x61,0x57,0x00,0x0C, ++0x38,0x00,0xA5,0x27, ++0x1F,0x00,0x40,0x14, ++0x01,0x00,0x44,0x26, ++0x40,0x10,0x10,0x00, ++0x21,0x10,0x52,0x00, ++0x01,0x00,0x42,0x24, ++0xBE,0x58,0x00,0x08, ++0xFF,0xFF,0x52,0x30, ++0x40,0x88,0x10,0x00, ++0x27,0x00,0x20,0x1A, ++0x21,0x80,0x00,0x00, ++0xFF,0x00,0x16,0x24, ++0x21,0x20,0x50,0x02, ++0x01,0x00,0x84,0x24, ++0xFF,0xFF,0x84,0x30, ++0x91,0x56,0x00,0x0C, ++0x10,0x00,0xA5,0x27, ++0x01,0x00,0x03,0x26, ++0xFF,0x00,0x70,0x30, ++0x05,0x00,0x40,0x10, ++0x2A,0x18,0x11,0x02, ++0x10,0x00,0xA2,0x93, ++0x00,0x00,0x00,0x00, ++0x26,0x10,0x56,0x00, ++0x0B,0x98,0x02,0x00, ++0xF3,0xFF,0x60,0x14, ++0x21,0x20,0x50,0x02, ++0x15,0x00,0x60,0x16, ++0x21,0x10,0x32,0x02, ++0x01,0x00,0x42,0x24, ++0xFF,0xFF,0x52,0x30, ++0x8B,0x58,0x00,0x08, ++0x01,0x00,0x16,0x24, ++0x29,0x00,0xA5,0x93, ++0xFF,0xFF,0x84,0x30, ++0xFC,0x57,0x00,0x0C, ++0x38,0x00,0xA6,0x27, ++0x21,0x28,0x40,0x00, ++0x0F,0x00,0x43,0x30, ++0x0F,0x00,0x02,0x24, ++0xDB,0xFF,0x62,0x10, ++0x40,0x10,0x10,0x00, ++0x28,0x00,0xA4,0x93, ++0x4B,0x58,0x00,0x0C, ++0x38,0x00,0xA6,0x27, ++0x3E,0x57,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0xBE,0x58,0x00,0x08, ++0x21,0x90,0x40,0x00, ++0x19,0x00,0xA3,0x93, ++0x29,0x00,0xA6,0x93, ++0x0F,0x00,0x13,0x24, ++0x0E,0x00,0x10,0x24, ++0x25,0x18,0x66,0x00, ++0x01,0x00,0x62,0x30, ++0x0A,0x98,0x02,0x02, ++0x02,0x00,0x64,0x30, ++0xFD,0x00,0x62,0x32, ++0x0A,0x98,0x44,0x00, ++0x04,0x00,0x65,0x30, ++0xFB,0x00,0x62,0x32, ++0x0A,0x98,0x45,0x00, ++0x08,0x00,0x63,0x30, ++0xF7,0x00,0x62,0x32, ++0x0A,0x98,0x43,0x00, ++0x0F,0x00,0x64,0x32, ++0x0F,0x00,0x16,0x24, ++0x25,0x00,0x96,0x10, ++0x21,0x28,0xC0,0x00, ++0x01,0x00,0x44,0x26, ++0xFF,0xFF,0x84,0x30, ++0xFC,0x57,0x00,0x0C, ++0x1A,0x00,0xA6,0x27, ++0x21,0x28,0x40,0x00, ++0x0F,0x00,0x42,0x30, ++0x03,0x00,0x56,0x10, ++0x21,0x20,0x80,0x02, ++0x4B,0x58,0x00,0x0C, ++0x38,0x00,0xA6,0x27, ++0x19,0x00,0xA5,0x93, ++0x00,0x00,0x00,0x00, ++0x26,0x10,0x65,0x02, ++0x01,0x00,0x42,0x30, ++0x0A,0x80,0xC2,0x02, ++0x26,0x18,0x65,0x02, ++0x02,0x00,0x63,0x30, ++0xFD,0x00,0x04,0x32, ++0x0B,0x80,0x83,0x00, ++0x26,0x10,0x65,0x02, ++0x04,0x00,0x42,0x30, ++0xFB,0x00,0x03,0x32, ++0x0B,0x80,0x62,0x00, ++0x26,0x28,0x65,0x02, ++0x08,0x00,0xA5,0x30, ++0xF7,0x00,0x02,0x32, ++0x0B,0x80,0x45,0x00, ++0x0F,0x00,0x03,0x32, ++0x0D,0x00,0x76,0x10, ++0x00,0x00,0x00,0x00, ++0x3E,0x57,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x21,0x90,0x40,0x00, ++0x19,0x00,0xB0,0xA3, ++0xBE,0x58,0x00,0x08, ++0x18,0x00,0xB4,0xA3, ++0x21,0x10,0x32,0x02, ++0x01,0x00,0x42,0x24, ++0xFF,0xFF,0x52,0x30, ++0x01,0x00,0x16,0x24, ++0x8B,0x58,0x00,0x08, ++0x18,0x00,0xB4,0xA3, ++0xBE,0x58,0x00,0x08, ++0x21,0xB8,0x00,0x00, ++0x01,0x80,0x02,0x3C, ++0x25,0xB0,0x03,0x3C, ++0xBC,0x65,0x42,0x24, ++0x18,0x03,0x63,0x34, ++0x00,0x00,0x62,0xAC, ++0x00,0x00,0x83,0x90, ++0x30,0x00,0x02,0x24, ++0x05,0x00,0x62,0x10, ++0x21,0x20,0x00,0x00, ++0x31,0x00,0x02,0x24, ++0x02,0x00,0x62,0x10, ++0x01,0x00,0x04,0x24, ++0x07,0x00,0x04,0x24, ++0x93,0x55,0x00,0x08, ++0x00,0x00,0x00,0x00, ++0x01,0x80,0x02,0x3C, ++0x25,0xB0,0x03,0x3C, ++0xF8,0x65,0x42,0x24, ++0x18,0x03,0x63,0x34, ++0x02,0x80,0x04,0x3C, ++0x00,0x00,0x62,0xAC, ++0x08,0x00,0xE0,0x03, ++0x14,0x5E,0x80,0xAC, ++0x42,0xB0,0x02,0x3C, ++0x03,0x00,0x47,0x34, ++0x00,0x00,0xE3,0x90, ++0xFF,0x00,0x84,0x30, ++0x04,0x00,0x84,0x24, ++0xFF,0x00,0x65,0x30, ++0x01,0x00,0x02,0x24, ++0x04,0x30,0x82,0x00, ++0x07,0x18,0x85,0x00, ++0x25,0xB0,0x02,0x3C, ++0xE8,0x03,0x42,0x34, ++0x01,0x00,0x63,0x30, ++0x21,0x20,0xC0,0x00, ++0x00,0x00,0x45,0xA0, ++0x02,0x00,0x60,0x10, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0xE6,0xA0, ++0x08,0x00,0xE0,0x03, ++0x24,0x10,0x85,0x00, ++0x00,0x60,0x03,0x40, ++0x01,0x00,0x61,0x34, ++0x01,0x00,0x21,0x38, ++0x00,0x60,0x81,0x40, ++0x02,0x80,0x02,0x3C, ++0x08,0xE4,0x42,0x24, ++0x04,0x00,0x45,0x8C, ++0x00,0x00,0x82,0xAC, ++0x04,0x00,0x44,0xAC, ++0x00,0x00,0xA4,0xAC, ++0x04,0x00,0x85,0xAC, ++0x00,0x60,0x83,0x40, ++0x08,0x00,0xE0,0x03, ++0x00,0x00,0x00,0x00, ++0x00,0x60,0x03,0x40, ++0x01,0x00,0x61,0x34, ++0x01,0x00,0x21,0x38, ++0x00,0x60,0x81,0x40, ++0x04,0x00,0x85,0x8C, ++0x00,0x00,0x82,0x8C, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0xA2,0xAC, ++0x04,0x00,0x45,0xAC, ++0x00,0x00,0x84,0xAC, ++0x04,0x00,0x84,0xAC, ++0x00,0x60,0x83,0x40, ++0x08,0x00,0xE0,0x03, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x85,0xAC, ++0x21,0x10,0x00,0x00, ++0x01,0x00,0x42,0x24, ++0xFF,0x00,0x42,0x30, ++0x06,0x00,0x43,0x2C, ++0xFC,0xFF,0x60,0x14, ++0x00,0x00,0x00,0x00, ++0x08,0x00,0xE0,0x03, ++0x00,0x00,0x00,0x00, ++0x02,0x24,0x04,0x00, ++0xFF,0x00,0x84,0x30, ++0xC0,0x18,0x04,0x00, ++0x21,0x18,0x64,0x00, ++0x80,0x18,0x03,0x00, ++0x21,0x18,0x64,0x00, ++0x02,0x80,0x02,0x3C, ++0x30,0x1F,0x42,0x24, ++0x80,0x18,0x03,0x00, ++0x21,0x18,0x62,0x00, ++0x1C,0x24,0x64,0x8C, ++0xFF,0xF1,0x02,0x24, ++0x24,0x20,0x82,0x00, ++0x08,0x00,0xE0,0x03, ++0x1C,0x24,0x64,0xAC, ++0x02,0x24,0x04,0x00, ++0xFF,0x00,0x84,0x30, ++0xC0,0x18,0x04,0x00, ++0x21,0x18,0x64,0x00, ++0x80,0x18,0x03,0x00, ++0x21,0x18,0x64,0x00, ++0x02,0x80,0x02,0x3C, ++0x30,0x1F,0x42,0x24, ++0x80,0x18,0x03,0x00, ++0x21,0x18,0x62,0x00, ++0x1C,0x24,0x64,0x8C, ++0xFF,0xF1,0x02,0x24, ++0x24,0x20,0x82,0x00, ++0x00,0x02,0x84,0x34, ++0x08,0x00,0xE0,0x03, ++0x1C,0x24,0x64,0xAC, ++0xE0,0xFF,0xBD,0x27, ++0x10,0x00,0xB0,0xAF, ++0xC0,0x80,0x04,0x00, ++0x21,0x80,0x04,0x02, ++0x80,0x80,0x10,0x00, ++0x21,0x80,0x04,0x02, ++0x02,0x80,0x02,0x3C, ++0x30,0x1F,0x42,0x24, ++0x80,0x80,0x10,0x00, ++0x21,0x80,0x02,0x02, ++0x1C,0x00,0xBF,0xAF, ++0x18,0x00,0xB2,0xAF, ++0x14,0x00,0xB1,0xAF, ++0x1C,0x24,0x05,0x8E, ++0xFF,0x1F,0x02,0x3C, ++0x25,0xB0,0x12,0x3C, ++0xFF,0xFF,0x42,0x34, ++0x14,0x24,0x02,0xAE, ++0x84,0x01,0x43,0x36, ++0xF8,0xFF,0x02,0x24, ++0x00,0x00,0x66,0x8C, ++0x24,0x28,0xA2,0x00, ++0xFF,0xFE,0x02,0x24, ++0x24,0x28,0xA2,0x00, ++0xFF,0xEF,0x03,0x24, ++0x24,0x28,0xA3,0x00, ++0x18,0x24,0x06,0xAE, ++0x1C,0x24,0x05,0xAE, ++0xC9,0x24,0x00,0x0C, ++0x21,0x88,0x80,0x00, ++0x1E,0x24,0x02,0x92, ++0x21,0x88,0x32,0x02, ++0x1C,0x00,0xBF,0x8F, ++0x60,0x01,0x22,0xA2, ++0x18,0x00,0xB2,0x8F, ++0x08,0x24,0x00,0xAE, ++0xEC,0x23,0x00,0xAE, ++0xF0,0x23,0x00,0xAE, ++0xF4,0x23,0x00,0xAE, ++0xF8,0x23,0x00,0xAE, ++0xFC,0x23,0x00,0xAE, ++0x00,0x24,0x00,0xAE, ++0x04,0x24,0x00,0xAE, ++0x14,0x00,0xB1,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x08,0x00,0xE0,0x03, ++0x20,0x00,0xBD,0x27, ++0xFF,0x00,0xA5,0x30, ++0xC0,0x10,0x05,0x00, ++0x21,0x10,0x45,0x00, ++0x80,0x10,0x02,0x00, ++0x21,0x10,0x45,0x00, ++0x02,0x80,0x03,0x3C, ++0x30,0x1F,0x63,0x24, ++0x80,0x10,0x02,0x00, ++0x21,0x10,0x43,0x00, ++0x1C,0x24,0x43,0x8C, ++0x25,0xB0,0x05,0x3C, ++0xFF,0x00,0xC6,0x30, ++0x21,0x30,0xC5,0x00, ++0xAF,0x01,0xC2,0x90, ++0x07,0x00,0x63,0x30, ++0x80,0x18,0x03,0x00, ++0x21,0x18,0x65,0x00, ++0xFF,0x00,0x88,0x30, ++0xFF,0x00,0x49,0x30, ++0x84,0x01,0x66,0x8C, ++0x21,0x50,0x00,0x00, ++0x21,0x58,0x00,0x00, ++0x2B,0x00,0x20,0x11, ++0x21,0x20,0x00,0x01, ++0x2B,0x00,0xC0,0x10, ++0x2B,0x10,0x09,0x01, ++0x21,0x28,0x00,0x00, ++0x2D,0x5A,0x00,0x08, ++0x01,0x00,0x07,0x24, ++0xFF,0x00,0x65,0x30, ++0x1D,0x00,0xA2,0x2C, ++0x07,0x00,0x40,0x10, ++0xFF,0xFF,0x02,0x25, ++0x04,0x10,0xA7,0x00, ++0x24,0x10,0x46,0x00, ++0xF9,0xFF,0x40,0x10, ++0x01,0x00,0xA3,0x24, ++0x21,0x58,0xA0,0x00, ++0xFF,0xFF,0x02,0x25, ++0xFF,0x00,0x45,0x30, ++0x2B,0x18,0xAB,0x00, ++0x0F,0x00,0x60,0x14, ++0x2B,0x10,0x49,0x01, ++0x01,0x00,0x04,0x24, ++0x04,0x10,0xA4,0x00, ++0x24,0x10,0x46,0x00, ++0xFF,0xFF,0xA7,0x24, ++0x04,0x00,0x40,0x10, ++0x01,0x00,0x43,0x25, ++0x17,0x00,0x49,0x11, ++0xFF,0x00,0x6A,0x30, ++0x21,0x40,0xA0,0x00, ++0xFF,0x00,0xE5,0x30, ++0x2B,0x10,0xAB,0x00, ++0xF6,0xFF,0x40,0x10, ++0x04,0x10,0xA4,0x00, ++0x2B,0x10,0x49,0x01, ++0x08,0x00,0x40,0x10, ++0x21,0x20,0x00,0x01, ++0x23,0x10,0x2A,0x01, ++0x2A,0x10,0x62,0x01, ++0x04,0x00,0x40,0x14, ++0x21,0x20,0x00,0x00, ++0x23,0x10,0x69,0x01, ++0x21,0x10,0x4A,0x00, ++0xFF,0x00,0x44,0x30, ++0x08,0x00,0xE0,0x03, ++0x21,0x10,0x80,0x00, ++0xFD,0xFF,0x40,0x14, ++0x21,0x20,0x00,0x00, ++0x23,0x10,0x09,0x01, ++0x4E,0x5A,0x00,0x08, ++0xFF,0x00,0x44,0x30, ++0x21,0x20,0x00,0x01, ++0x08,0x00,0xE0,0x03, ++0x21,0x10,0x80,0x00, ++0xFF,0x00,0x84,0x30, ++0xC0,0x10,0x04,0x00, ++0x21,0x10,0x44,0x00, ++0x80,0x10,0x02,0x00, ++0x21,0x10,0x44,0x00, ++0x02,0x80,0x03,0x3C, ++0x30,0x1F,0x63,0x24, ++0x80,0x10,0x02,0x00, ++0x21,0x10,0x43,0x00, ++0x25,0xB0,0x06,0x3C, ++0x1C,0x24,0x43,0x8C, ++0xFF,0x00,0xA5,0x30, ++0x21,0x20,0x86,0x00, ++0x21,0x28,0xA6,0x00, ++0x60,0x01,0x82,0x90, ++0xAF,0x01,0xA4,0x90, ++0x07,0x00,0x63,0x30, ++0x80,0x18,0x03,0x00, ++0x21,0x18,0x66,0x00, ++0xFF,0x00,0x48,0x30, ++0xFF,0x00,0x89,0x30, ++0x84,0x01,0x66,0x8C, ++0x21,0x50,0x00,0x00, ++0x21,0x58,0x00,0x00, ++0x2B,0x00,0x20,0x11, ++0x21,0x20,0x00,0x01, ++0x2B,0x00,0xC0,0x10, ++0x2B,0x10,0x09,0x01, ++0x21,0x28,0x00,0x00, ++0x7B,0x5A,0x00,0x08, ++0x01,0x00,0x07,0x24, ++0xFF,0x00,0x65,0x30, ++0x1D,0x00,0xA2,0x2C, ++0x07,0x00,0x40,0x10, ++0xFF,0xFF,0x02,0x25, ++0x04,0x10,0xA7,0x00, ++0x24,0x10,0x46,0x00, ++0xF9,0xFF,0x40,0x10, ++0x01,0x00,0xA3,0x24, ++0x21,0x58,0xA0,0x00, ++0xFF,0xFF,0x02,0x25, ++0xFF,0x00,0x45,0x30, ++0x2B,0x18,0xAB,0x00, ++0x0F,0x00,0x60,0x14, ++0x2B,0x10,0x49,0x01, ++0x01,0x00,0x04,0x24, ++0x04,0x10,0xA4,0x00, ++0x24,0x10,0x46,0x00, ++0xFF,0xFF,0xA7,0x24, ++0x04,0x00,0x40,0x10, ++0x01,0x00,0x43,0x25, ++0x17,0x00,0x49,0x11, ++0xFF,0x00,0x6A,0x30, ++0x21,0x40,0xA0,0x00, ++0xFF,0x00,0xE5,0x30, ++0x2B,0x10,0xAB,0x00, ++0xF6,0xFF,0x40,0x10, ++0x04,0x10,0xA4,0x00, ++0x2B,0x10,0x49,0x01, ++0x08,0x00,0x40,0x10, ++0x21,0x20,0x00,0x01, ++0x23,0x10,0x2A,0x01, ++0x2A,0x10,0x62,0x01, ++0x04,0x00,0x40,0x14, ++0x21,0x20,0x00,0x00, ++0x23,0x10,0x69,0x01, ++0x21,0x10,0x4A,0x00, ++0xFF,0x00,0x44,0x30, ++0x08,0x00,0xE0,0x03, ++0x21,0x10,0x80,0x00, ++0xFD,0xFF,0x40,0x14, ++0x21,0x20,0x00,0x00, ++0x23,0x10,0x09,0x01, ++0x9C,0x5A,0x00,0x08, ++0xFF,0x00,0x44,0x30, ++0x21,0x20,0x00,0x01, ++0x08,0x00,0xE0,0x03, ++0x21,0x10,0x80,0x00, ++0xE0,0xFF,0xBD,0x27, ++0x02,0x80,0x02,0x3C, ++0x10,0x00,0xB0,0xAF, ++0x30,0x1F,0x50,0x24, ++0x18,0x00,0xB2,0xAF, ++0x14,0x00,0xB1,0xAF, ++0x1C,0x00,0xBF,0xAF, ++0x21,0x88,0x00,0x00, ++0x21,0x90,0x00,0x02, ++0xDD,0x59,0x00,0x0C, ++0x21,0x20,0x20,0x02, ++0x1E,0x24,0x02,0x92, ++0x21,0x28,0x00,0x00, ++0x80,0x10,0x02,0x00, ++0x21,0x10,0x52,0x00, ++0x60,0x05,0x44,0x8C, ++0xD4,0x05,0x43,0x8C, ++0x00,0x00,0x00,0x00, ++0x21,0x18,0x64,0x00, ++0x42,0x18,0x03,0x00, ++0xE8,0x23,0x03,0xAE, ++0x21,0x10,0x05,0x02, ++0x01,0x00,0xA5,0x24, ++0x1D,0x00,0xA3,0x28, ++0x5A,0x24,0x40,0xA0, ++0x20,0x24,0x40,0xA0, ++0xFA,0xFF,0x60,0x14, ++0x3D,0x24,0x40,0xA0, ++0x01,0x00,0x31,0x26, ++0x20,0x00,0x22,0x2A, ++0x78,0x24,0x00,0xAE, ++0xE9,0xFF,0x40,0x14, ++0x94,0x00,0x10,0x26, ++0x1C,0x00,0xBF,0x8F, ++0x18,0x00,0xB2,0x8F, ++0x14,0x00,0xB1,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x08,0x00,0xE0,0x03, ++0x20,0x00,0xBD,0x27, ++0xD0,0xFF,0xBD,0x27, ++0x28,0x00,0xB6,0xAF, ++0x02,0x80,0x16,0x3C, ++0x24,0x00,0xB5,0xAF, ++0x30,0x1F,0xC6,0x26, ++0x2C,0x00,0xBF,0xAF, ++0x20,0x00,0xB4,0xAF, ++0x1C,0x00,0xB3,0xAF, ++0x18,0x00,0xB2,0xAF, ++0x14,0x00,0xB1,0xAF, ++0x10,0x00,0xB0,0xAF, ++0x30,0x38,0xC2,0x8C, ++0xFF,0x00,0x8D,0x30, ++0xFF,0x00,0x03,0x24, ++0xFF,0xFF,0x42,0x38, ++0x21,0xA8,0x00,0x00, ++0xFF,0xFF,0x04,0x34, ++0x0A,0xA8,0x62,0x00, ++0xA4,0x00,0xA0,0x11, ++0x30,0x38,0xC4,0xAC, ++0x02,0x80,0x02,0x3C, ++0xE4,0xE7,0x45,0x24, ++0x04,0x05,0xC4,0x24, ++0xEB,0x5A,0x00,0x08, ++0x21,0x80,0x00,0x00, ++0x01,0x00,0x10,0x26, ++0x00,0x00,0x82,0xA0, ++0x1D,0x00,0x02,0x2A, ++0x0B,0x00,0x40,0x10, ++0x01,0x00,0x84,0x24, ++0x21,0x10,0x05,0x02, ++0x00,0x00,0x42,0x90, ++0x00,0x00,0x00,0x00, ++0xF7,0xFF,0x40,0x10, ++0xFD,0xFF,0x43,0x24, ++0x01,0x00,0x10,0x26, ++0x1D,0x00,0x02,0x2A, ++0x00,0x00,0x83,0xA0, ++0xF7,0xFF,0x40,0x14, ++0x01,0x00,0x84,0x24, ++0x02,0x80,0x02,0x3C, ++0x30,0x1F,0x4A,0x24, ++0x02,0x80,0x03,0x3C, ++0x02,0x80,0x02,0x3C, ++0x7C,0xE5,0x6C,0x24, ++0x04,0xE5,0x4B,0x24, ++0x21,0x80,0x00,0x00, ++0x21,0x48,0x00,0x00, ++0x21,0x30,0x00,0x00, ++0x21,0x40,0x2A,0x01, ++0x21,0x38,0x2C,0x01, ++0x21,0x10,0xE6,0x00, ++0x91,0x00,0x44,0x90, ++0x00,0x00,0x45,0x90, ++0x21,0x18,0x06,0x01, ++0x01,0x00,0xC6,0x24, ++0x05,0x00,0xC2,0x28, ++0x39,0x04,0x64,0xA0, ++0xF8,0xFF,0x40,0x14, ++0xA8,0x03,0x65,0xA0, ++0x21,0x10,0x0B,0x02, ++0x1D,0x00,0x44,0x90, ++0x00,0x00,0x45,0x90, ++0x21,0x18,0x0A,0x02, ++0x01,0x00,0x10,0x26, ++0x1D,0x00,0x02,0x2A, ++0xE7,0x04,0x64,0xA0, ++0xCA,0x04,0x65,0xA0, ++0xEB,0xFF,0x40,0x14, ++0x05,0x00,0x29,0x25, ++0x9A,0x00,0xA0,0x11, ++0x02,0x80,0x02,0x3C, ++0x30,0x1F,0x48,0x24, ++0x02,0x80,0x03,0x3C, ++0x02,0x80,0x02,0x3C, ++0x78,0xE8,0x69,0x24, ++0x04,0xE8,0x47,0x24, ++0x21,0x80,0x00,0x00, ++0x80,0x18,0x10,0x00, ++0x21,0x10,0x69,0x00, ++0x21,0x20,0x67,0x00, ++0x00,0x00,0x46,0x8C, ++0x00,0x00,0x85,0x8C, ++0x01,0x00,0x10,0x26, ++0x21,0x18,0x68,0x00, ++0x04,0x00,0x02,0x2A, ++0x60,0x05,0x65,0xAC, ++0xF6,0xFF,0x40,0x14, ++0xD4,0x05,0x66,0xAC, ++0x02,0x80,0x02,0x3C, ++0x30,0x1F,0x49,0x24, ++0x02,0x80,0x03,0x3C, ++0x02,0x80,0x02,0x3C, ++0x78,0xE8,0x68,0x24, ++0x04,0xE8,0x47,0x24, ++0x04,0x00,0x10,0x24, ++0x80,0x20,0x10,0x00, ++0x21,0x10,0x88,0x00, ++0x21,0x30,0x87,0x00, ++0x00,0x00,0x45,0x8C, ++0x00,0x00,0xC3,0x8C, ++0x01,0x00,0x10,0x26, ++0x21,0x20,0x89,0x00, ++0x82,0x28,0x05,0x00, ++0x82,0x18,0x03,0x00, ++0x1D,0x00,0x02,0x2A, ++0x60,0x05,0x83,0xAC, ++0xF4,0xFF,0x40,0x14, ++0xD4,0x05,0x85,0xAC, ++0x02,0x80,0x02,0x3C, ++0x30,0x1F,0x53,0x24, ++0x21,0x80,0x00,0x00, ++0x21,0xA0,0x60,0x02, ++0x21,0x90,0x00,0x00, ++0x46,0x5B,0x00,0x08, ++0x21,0x88,0x60,0x02, ++0x01,0x00,0x10,0x26, ++0x20,0x00,0x02,0x2A, ++0x94,0x00,0x31,0x26, ++0x32,0x00,0x40,0x10, ++0x94,0x00,0x52,0x26, ++0x1C,0x24,0x24,0x8E, ++0x01,0x00,0x03,0x24, ++0x02,0x13,0x04,0x00, ++0x01,0x00,0x42,0x30, ++0xF6,0xFF,0x43,0x14, ++0x07,0x00,0x82,0x30, ++0x25,0xB0,0x03,0x3C, ++0x80,0x10,0x02,0x00, ++0x21,0x10,0x43,0x00, ++0x84,0x01,0x45,0x8C, ++0x14,0x24,0x23,0x8E, ++0x21,0x20,0x00,0x02, ++0x24,0x28,0xA3,0x00, ++0xC9,0x24,0x00,0x0C, ++0x18,0x24,0x25,0xAE, ++0x1E,0x24,0x24,0x92, ++0x57,0x24,0x00,0x0C, ++0xFF,0x00,0x05,0x32, ++0x1E,0x24,0x23,0x92, ++0xEC,0x23,0x20,0xAE, ++0xF0,0x23,0x20,0xAE, ++0x80,0x18,0x03,0x00, ++0xF4,0x23,0x20,0xAE, ++0xF8,0x23,0x20,0xAE, ++0xFC,0x23,0x20,0xAE, ++0x00,0x24,0x20,0xAE, ++0x04,0x24,0x20,0xAE, ++0x08,0x24,0x20,0xAE, ++0x21,0x18,0x74,0x00, ++0x60,0x05,0x64,0x8C, ++0xD4,0x05,0x62,0x8C, ++0x21,0x30,0x00,0x00, ++0x21,0x28,0x53,0x02, ++0x21,0x10,0x44,0x00, ++0x42,0x10,0x02,0x00, ++0xE8,0x23,0x22,0xAE, ++0x21,0x10,0xA6,0x00, ++0x01,0x00,0xC6,0x24, ++0x1D,0x00,0xC3,0x28, ++0x5A,0x24,0x40,0xA0, ++0x20,0x24,0x40,0xA0, ++0xFA,0xFF,0x60,0x14, ++0x3D,0x24,0x40,0xA0, ++0x01,0x00,0x10,0x26, ++0x20,0x00,0x02,0x2A, ++0x78,0x24,0xA0,0xAC, ++0x94,0x00,0x31,0x26, ++0xD0,0xFF,0x40,0x14, ++0x94,0x00,0x52,0x26, ++0x02,0x00,0xA0,0x16, ++0x30,0x1F,0xC2,0x26, ++0x30,0x38,0x40,0xAC, ++0x2C,0x00,0xBF,0x8F, ++0x28,0x00,0xB6,0x8F, ++0x24,0x00,0xB5,0x8F, ++0x20,0x00,0xB4,0x8F, ++0x1C,0x00,0xB3,0x8F, ++0x18,0x00,0xB2,0x8F, ++0x14,0x00,0xB1,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x08,0x00,0xE0,0x03, ++0x30,0x00,0xBD,0x27, ++0x02,0x80,0x02,0x3C, ++0xE4,0xE7,0x45,0x24, ++0x04,0x05,0xC4,0x24, ++0x21,0x80,0x00,0x00, ++0x21,0x10,0x05,0x02, ++0x00,0x00,0x43,0x90, ++0x01,0x00,0x10,0x26, ++0x1D,0x00,0x02,0x2A, ++0x00,0x00,0x83,0xA0, ++0xFA,0xFF,0x40,0x14, ++0x01,0x00,0x84,0x24, ++0x02,0x80,0x02,0x3C, ++0x30,0x1F,0x4A,0x24, ++0x02,0x80,0x03,0x3C, ++0x02,0x80,0x02,0x3C, ++0xA0,0xE6,0x6C,0x24, ++0x40,0xE5,0x4B,0x24, ++0x21,0x80,0x00,0x00, ++0x21,0x48,0x00,0x00, ++0x21,0x30,0x00,0x00, ++0x21,0x40,0x2A,0x01, ++0x21,0x38,0x2C,0x01, ++0x21,0x10,0xE6,0x00, ++0x91,0x00,0x44,0x90, ++0x00,0x00,0x45,0x90, ++0x21,0x18,0x06,0x01, ++0x01,0x00,0xC6,0x24, ++0x05,0x00,0xC2,0x28, ++0x39,0x04,0x64,0xA0, ++0xF8,0xFF,0x40,0x14, ++0xA8,0x03,0x65,0xA0, ++0x21,0x10,0x0B,0x02, ++0x1D,0x00,0x44,0x90, ++0x00,0x00,0x45,0x90, ++0x21,0x18,0x0A,0x02, ++0x01,0x00,0x10,0x26, ++0x1D,0x00,0x02,0x2A, ++0xE7,0x04,0x64,0xA0, ++0xCA,0x04,0x65,0xA0, ++0xEB,0xFF,0x40,0x14, ++0x05,0x00,0x29,0x25, ++0x02,0x80,0x02,0x3C, ++0x30,0x1F,0x49,0x24, ++0x02,0x80,0x03,0x3C, ++0x02,0x80,0x02,0x3C, ++0x78,0xE8,0x68,0x24, ++0x04,0xE8,0x47,0x24, ++0x21,0x80,0x00,0x00, ++0x80,0x18,0x10,0x00, ++0x21,0x10,0x68,0x00, ++0x21,0x20,0x67,0x00, ++0x00,0x00,0x46,0x8C, ++0x00,0x00,0x85,0x8C, ++0x01,0x00,0x10,0x26, ++0x21,0x18,0x69,0x00, ++0x1D,0x00,0x02,0x2A, ++0x60,0x05,0x65,0xAC, ++0xF6,0xFF,0x40,0x14, ++0xD4,0x05,0x66,0xAC, ++0x3B,0x5B,0x00,0x08, ++0x02,0x80,0x02,0x3C, ++0xD8,0xFF,0xBD,0x27, ++0xFF,0xFF,0x84,0x30, ++0x18,0x00,0xB2,0xAF, ++0xF0,0x01,0x92,0x30, ++0x02,0x91,0x12,0x00, ++0x14,0x00,0xB1,0xAF, ++0xC0,0x88,0x12,0x00, ++0x21,0x88,0x32,0x02, ++0x80,0x88,0x11,0x00, ++0x21,0x88,0x32,0x02, ++0x02,0x80,0x02,0x3C, ++0x30,0x1F,0x42,0x24, ++0x80,0x88,0x11,0x00, ++0x21,0x88,0x22,0x02, ++0x20,0x00,0xBF,0xAF, ++0x1C,0x00,0xB3,0xAF, ++0x10,0x00,0xB0,0xAF, ++0x1C,0x24,0x30,0x8E, ++0x00,0x02,0x82,0x30, ++0xFF,0xFE,0x03,0x24, ++0x2B,0x10,0x02,0x00, ++0x00,0x10,0x10,0x36, ++0x24,0x80,0x03,0x02, ++0x00,0x12,0x02,0x00, ++0x25,0x80,0x02,0x02, ++0x14,0x24,0x25,0xAE, ++0x1C,0x24,0x30,0xAE, ++0x76,0x25,0x00,0x0C, ++0x21,0x98,0xA0,0x00, ++0xF8,0xFF,0x03,0x24, ++0x24,0x80,0x03,0x02, ++0x07,0x00,0x42,0x30, ++0x25,0x80,0x02,0x02, ++0x07,0x00,0x03,0x32, ++0x25,0xB0,0x02,0x3C, ++0x80,0x18,0x03,0x00, ++0x1C,0x24,0x30,0xAE, ++0x21,0x18,0x62,0x00, ++0x84,0x01,0x62,0x8C, ++0x21,0x20,0x40,0x02, ++0x24,0x10,0x53,0x00, ++0xC9,0x24,0x00,0x0C, ++0x18,0x24,0x22,0xAE, ++0x1E,0x24,0x24,0x92, ++0x21,0x28,0x40,0x02, ++0x20,0x00,0xBF,0x8F, ++0x1C,0x00,0xB3,0x8F, ++0x18,0x00,0xB2,0x8F, ++0x14,0x00,0xB1,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x57,0x24,0x00,0x08, ++0x28,0x00,0xBD,0x27, ++0xDD,0x59,0x00,0x08, ++0xFF,0x00,0x84,0x30, ++0x02,0x80,0x02,0x3C, ++0x30,0x1F,0x43,0x24, ++0x1F,0x00,0x04,0x24, ++0x1C,0x24,0x62,0x8C, ++0xFF,0xFF,0x84,0x24, ++0x00,0x10,0x42,0x34, ++0x1C,0x24,0x62,0xAC, ++0xFB,0xFF,0x81,0x04, ++0x94,0x00,0x63,0x24, ++0x08,0x00,0xE0,0x03, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x85,0xAC, ++0x21,0x10,0x00,0x00, ++0x01,0x00,0x42,0x24, ++0xFF,0x00,0x42,0x30, ++0x06,0x00,0x43,0x2C, ++0xFC,0xFF,0x60,0x14, ++0x00,0x00,0x00,0x00, ++0x08,0x00,0xE0,0x03, ++0x00,0x00,0x00,0x00, ++0xE0,0xFF,0xBD,0x27, ++0x44,0x00,0x02,0x24, ++0x10,0x00,0xA2,0xA3, ++0x49,0x00,0x03,0x24, ++0x47,0x00,0x02,0x24, ++0x02,0x80,0x07,0x3C, ++0xD4,0xF3,0xE7,0x24, ++0x11,0x00,0xA3,0xA3, ++0x12,0x00,0xA2,0xA3, ++0x10,0x27,0x03,0x24, ++0x01,0x00,0x02,0x24, ++0x01,0x80,0x06,0x3C, ++0x10,0x00,0xA5,0x27, ++0x21,0x20,0xE0,0x00, ++0x20,0x73,0xC6,0x24, ++0x0C,0x00,0xE3,0xAC, ++0x14,0x00,0xE2,0xA0, ++0x18,0x00,0xBF,0xAF, ++0xA2,0x23,0x00,0x0C, ++0x13,0x00,0xA0,0xA3, ++0x18,0x00,0xBF,0x8F, ++0x00,0x00,0x00,0x00, ++0x08,0x00,0xE0,0x03, ++0x20,0x00,0xBD,0x27, ++0xD0,0xFF,0xBD,0x27, ++0x25,0xB0,0x03,0x3C, ++0x20,0x00,0xB4,0xAF, ++0x1C,0x00,0xB3,0xAF, ++0x2C,0x00,0xBF,0xAF, ++0x28,0x00,0xB6,0xAF, ++0x24,0x00,0xB5,0xAF, ++0x18,0x00,0xB2,0xAF, ++0x14,0x00,0xB1,0xAF, ++0x10,0x00,0xB0,0xAF, ++0x03,0x0D,0x64,0x34, ++0x00,0x00,0x82,0x90, ++0x00,0x00,0x00,0x00, ++0xFF,0x00,0x54,0x30, ++0x70,0x00,0x93,0x32, ++0x5D,0x00,0x60,0x12, ++0x42,0x00,0x63,0x34, ++0x8F,0x00,0x82,0x32, ++0x00,0x00,0x82,0xA0, ++0x21,0x10,0x00,0x00, ++0x01,0x00,0x42,0x24, ++0xFF,0x00,0x42,0x30, ++0x06,0x00,0x43,0x2C, ++0xFD,0xFF,0x60,0x14, ++0x01,0x00,0x42,0x24, ++0x55,0x00,0x60,0x12, ++0x00,0x00,0x00,0x00, ++0x00,0x60,0x12,0x40, ++0x01,0x00,0x41,0x36, ++0x01,0x00,0x21,0x38, ++0x00,0x60,0x81,0x40, ++0x0F,0x00,0x11,0x3C, ++0x21,0x20,0x00,0x00, ++0x8A,0x47,0x00,0x0C, ++0xFF,0xFF,0x25,0x36, ++0x21,0xA8,0x40,0x00, ++0x00,0x60,0x92,0x40, ++0x54,0x22,0x00,0x0C, ++0x64,0x00,0x04,0x24, ++0xE6,0x44,0x00,0x0C, ++0x01,0x00,0x04,0x24, ++0x00,0x60,0x12,0x40, ++0x01,0x00,0x41,0x36, ++0x01,0x00,0x21,0x38, ++0x00,0x60,0x81,0x40, ++0x21,0x20,0x00,0x00, ++0x8A,0x47,0x00,0x0C, ++0xFF,0xFF,0x25,0x36, ++0x21,0xB0,0x40,0x00, ++0x00,0x60,0x92,0x40, ++0x64,0x00,0x04,0x24, ++0x54,0x22,0x00,0x0C, ++0x08,0x00,0x10,0x3C, ++0xFF,0xFF,0x10,0x36, ++0xE6,0x44,0x00,0x0C, ++0x21,0x20,0x00,0x00, ++0x01,0x00,0x12,0x3C, ++0x24,0x30,0xB0,0x02, ++0x25,0x30,0xD2,0x00, ++0xFF,0xFF,0x25,0x36, ++0x5F,0x47,0x00,0x0C, ++0x21,0x20,0x00,0x00, ++0x54,0x22,0x00,0x0C, ++0x64,0x00,0x04,0x24, ++0x24,0x80,0xD0,0x02, ++0xE6,0x44,0x00,0x0C, ++0x01,0x00,0x04,0x24, ++0x25,0x30,0x12,0x02, ++0xFF,0xFF,0x25,0x36, ++0x5F,0x47,0x00,0x0C, ++0x21,0x20,0x00,0x00, ++0x54,0x22,0x00,0x0C, ++0x64,0x00,0x04,0x24, ++0xE6,0x44,0x00,0x0C, ++0x21,0x20,0x00,0x00, ++0x00,0x60,0x12,0x40, ++0x01,0x00,0x41,0x36, ++0x01,0x00,0x21,0x38, ++0x00,0x60,0x81,0x40, ++0x0F,0x00,0x10,0x3C, ++0x18,0x00,0x04,0x24, ++0x8A,0x47,0x00,0x0C, ++0xFF,0xFF,0x05,0x36, ++0x21,0x88,0x40,0x00, ++0x00,0x60,0x92,0x40, ++0x54,0x22,0x00,0x0C, ++0x64,0x00,0x04,0x24, ++0x18,0x00,0x04,0x24, ++0xFF,0xFF,0x05,0x36, ++0x5F,0x47,0x00,0x0C, ++0x00,0x80,0x26,0x36, ++0x25,0x22,0x00,0x0C, ++0x03,0x00,0x04,0x24, ++0x25,0x00,0x60,0x16, ++0x25,0xB0,0x02,0x3C, ++0x2C,0x00,0xBF,0x8F, ++0x28,0x00,0xB6,0x8F, ++0x24,0x00,0xB5,0x8F, ++0x20,0x00,0xB4,0x8F, ++0x1C,0x00,0xB3,0x8F, ++0x18,0x00,0xB2,0x8F, ++0x14,0x00,0xB1,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x25,0xB0,0x02,0x3C, ++0x42,0x00,0x42,0x34, ++0x30,0x00,0xBD,0x27, ++0x00,0x00,0x40,0xA0, ++0x08,0x00,0xE0,0x03, ++0x00,0x00,0x00,0x00, ++0xFF,0xFF,0x02,0x24, ++0x00,0x00,0x62,0xA0, ++0x00,0x60,0x12,0x40, ++0x01,0x00,0x41,0x36, ++0x01,0x00,0x21,0x38, ++0x00,0x60,0x81,0x40, ++0x0F,0x00,0x10,0x3C, ++0x18,0x00,0x04,0x24, ++0x8A,0x47,0x00,0x0C, ++0xFF,0xFF,0x05,0x36, ++0x21,0x88,0x40,0x00, ++0x00,0x60,0x92,0x40, ++0x54,0x22,0x00,0x0C, ++0x64,0x00,0x04,0x24, ++0x18,0x00,0x04,0x24, ++0xFF,0xFF,0x05,0x36, ++0x5F,0x47,0x00,0x0C, ++0x00,0x80,0x26,0x36, ++0x25,0x22,0x00,0x0C, ++0x03,0x00,0x04,0x24, ++0xDD,0xFF,0x60,0x12, ++0x25,0xB0,0x02,0x3C, ++0x03,0x0D,0x42,0x34, ++0x00,0x00,0x54,0xA0, ++0x21,0x10,0x00,0x00, ++0x01,0x00,0x42,0x24, ++0xFF,0x00,0x42,0x30, ++0x06,0x00,0x43,0x2C, ++0xFD,0xFF,0x60,0x14, ++0x01,0x00,0x42,0x24, ++0x0F,0x00,0x10,0x3C, ++0x21,0x30,0xA0,0x02, ++0xFF,0xFF,0x05,0x36, ++0x5F,0x47,0x00,0x0C, ++0x21,0x20,0x00,0x00, ++0x54,0x22,0x00,0x0C, ++0x64,0x00,0x04,0x24, ++0xE6,0x44,0x00,0x0C, ++0x01,0x00,0x04,0x24, ++0xFF,0xFF,0x05,0x36, ++0x21,0x30,0xC0,0x02, ++0x5F,0x47,0x00,0x0C, ++0x21,0x20,0x00,0x00, ++0x54,0x22,0x00,0x0C, ++0x64,0x00,0x04,0x24, ++0x2C,0x00,0xBF,0x8F, ++0x28,0x00,0xB6,0x8F, ++0x24,0x00,0xB5,0x8F, ++0x20,0x00,0xB4,0x8F, ++0x1C,0x00,0xB3,0x8F, ++0x18,0x00,0xB2,0x8F, ++0x14,0x00,0xB1,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x21,0x20,0x00,0x00, ++0xE6,0x44,0x00,0x08, ++0x30,0x00,0xBD,0x27, ++0xC8,0xFF,0xBD,0x27, ++0x28,0x00,0xB4,0xAF, ++0x02,0x80,0x14,0x3C, ++0x30,0x00,0xB6,0xAF, ++0x34,0x00,0xBF,0xAF, ++0x2C,0x00,0xB5,0xAF, ++0x24,0x00,0xB3,0xAF, ++0x20,0x00,0xB2,0xAF, ++0x1C,0x00,0xB1,0xAF, ++0x18,0x00,0xB0,0xAF, ++0x30,0x1F,0x85,0x26, ++0x0C,0x00,0xA2,0x8C, ++0x00,0x00,0x00,0x00, ++0x82,0x17,0x02,0x00, ++0x01,0x00,0x42,0x30, ++0x08,0x00,0x40,0x14, ++0x06,0x00,0x16,0x24, ++0x08,0x00,0xA2,0x8C, ++0x01,0x00,0x03,0x24, ++0x42,0x17,0x02,0x00, ++0x03,0x00,0x42,0x30, ++0x57,0x00,0x43,0x10, ++0x25,0xB0,0x02,0x3C, ++0x30,0x1F,0x85,0x26, ++0x0C,0x00,0xA2,0x8C, ++0x01,0x00,0x03,0x24, ++0x82,0x17,0x02,0x00, ++0x01,0x00,0x44,0x30, ++0x0B,0x00,0x83,0x10, ++0x21,0x10,0x00,0x00, ++0x34,0x00,0xBF,0x8F, ++0x30,0x00,0xB6,0x8F, ++0x2C,0x00,0xB5,0x8F, ++0x28,0x00,0xB4,0x8F, ++0x24,0x00,0xB3,0x8F, ++0x20,0x00,0xB2,0x8F, ++0x1C,0x00,0xB1,0x8F, ++0x18,0x00,0xB0,0x8F, ++0x08,0x00,0xE0,0x03, ++0x38,0x00,0xBD,0x27, ++0x08,0x00,0xA2,0x8C, ++0x00,0x00,0x00,0x00, ++0x42,0x17,0x02,0x00, ++0x03,0x00,0x43,0x30, ++0xF1,0xFF,0x64,0x14, ++0x21,0x10,0x00,0x00, ++0x10,0x00,0xA2,0x8C, ++0x00,0x00,0x00,0x00, ++0x82,0x17,0x02,0x00, ++0x50,0x02,0x43,0x10, ++0x25,0xB0,0x02,0x3C, ++0xC7,0x02,0xB3,0x90, ++0x62,0x0C,0x42,0x34, ++0xFF,0x00,0x63,0x32, ++0x00,0x00,0x43,0xA0, ++0x21,0x10,0x00,0x00, ++0x01,0x00,0x42,0x24, ++0xFF,0x00,0x42,0x30, ++0x06,0x00,0x43,0x2C, ++0xFD,0xFF,0x60,0x14, ++0x01,0x00,0x42,0x24, ++0x30,0x1F,0x90,0x26, ++0xC6,0x02,0x02,0x92, ++0x00,0x00,0x00,0x00, ++0x83,0x00,0x40,0x10, ++0x01,0x00,0x02,0x24, ++0x25,0xB0,0x11,0x3C, ++0x03,0x0D,0x23,0x36, ++0x00,0x00,0x62,0x90, ++0x00,0x00,0x00,0x00, ++0x70,0x00,0x42,0x30, ++0xA9,0x00,0x40,0x14, ++0xCC,0x00,0x02,0x24, ++0xC4,0x02,0x02,0x96, ++0x00,0x00,0x00,0x00, ++0x23,0x20,0x53,0x00, ++0x2B,0x18,0x53,0x00, ++0x23,0x10,0x62,0x02, ++0x0A,0x10,0x83,0x00, ++0x03,0x00,0x42,0x2C, ++0x76,0x00,0x40,0x10, ++0x00,0x00,0x00,0x00, ++0xC4,0x02,0x03,0x92, ++0x63,0x0C,0x22,0x36, ++0x21,0x20,0x00,0x00, ++0x00,0x00,0x43,0xA0, ++0x01,0x00,0x82,0x24, ++0xFF,0x00,0x44,0x30, ++0x06,0x00,0x83,0x2C, ++0xFD,0xFF,0x60,0x14, ++0x01,0x00,0x82,0x24, ++0x30,0x1F,0x83,0x26, ++0xC3,0x02,0x62,0x90, ++0x08,0x00,0x66,0x8C, ++0xC2,0x02,0x73,0xA0, ++0x23,0x20,0x53,0x00, ++0x02,0x2C,0x06,0x00, ++0x2B,0x40,0x62,0x02, ++0x23,0x90,0x62,0x02, ++0x0B,0x90,0x88,0x00, ++0x3F,0x00,0xA7,0x30, ++0x3F,0x00,0xC6,0x30, ++0x24,0x00,0x02,0x24, ++0x20,0x00,0x03,0x24, ++0x23,0x10,0x46,0x00, ++0x91,0x00,0x40,0x16, ++0x23,0x20,0x67,0x00, ++0xE6,0x5C,0x00,0x08, ++0x00,0x00,0x00,0x00, ++0x80,0x0C,0x42,0x34, ++0x00,0x00,0x43,0x8C, ++0x21,0x30,0xA0,0x00, ++0xC0,0xFF,0x02,0x3C, ++0x24,0x20,0x62,0x00, ++0x21,0x88,0x00,0x00, ++0xC0,0xFF,0x05,0x3C, ++0x42,0x5D,0x00,0x08, ++0x18,0x00,0xC3,0x24, ++0x01,0x00,0x31,0x26, ++0x25,0x00,0x22,0x2E, ++0x0D,0x00,0x40,0x10, ++0x02,0x80,0x02,0x3C, ++0x00,0x00,0x62,0x8C, ++0x00,0x00,0x00,0x00, ++0x24,0x10,0x45,0x00, ++0xF8,0xFF,0x44,0x14, ++0x04,0x00,0x63,0x24, ++0x08,0x00,0xC2,0x8C, ++0xC0,0xFF,0x03,0x24, ++0x3F,0x00,0x24,0x32, ++0x24,0x10,0x43,0x00, ++0x25,0x10,0x44,0x00, ++0x08,0x00,0xC2,0xAC, ++0x02,0x80,0x02,0x3C, ++0xDE,0x5D,0x44,0x90, ++0x22,0x00,0x03,0x24, ++0x42,0x00,0x83,0x10, ++0x92,0x00,0x02,0x24, ++0x41,0x00,0x82,0x10, ++0x25,0xB0,0x02,0x3C, ++0x25,0xB0,0x02,0x3C, ++0x24,0x0A,0x42,0x34, ++0x00,0x00,0x44,0x8C, ++0x3F,0x3F,0x03,0x3C, ++0x3F,0x3F,0x63,0x34, ++0x24,0x20,0x83,0x00, ++0x02,0x80,0x02,0x3C, ++0x02,0x80,0x03,0x3C, ++0xDE,0x1F,0x53,0x24, ++0xE6,0x20,0x72,0x24, ++0x21,0x88,0x00,0x00, ++0x69,0x5D,0x00,0x08, ++0x10,0x00,0xA4,0xAF, ++0x39,0x52,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x4B,0x00,0x40,0x10, ++0x30,0x1F,0x85,0x26, ++0x01,0x00,0x31,0x26, ++0x21,0x00,0x22,0x2E, ++0x17,0x00,0x40,0x10, ++0x30,0x1F,0x82,0x26, ++0xC0,0x80,0x11,0x00, ++0x10,0x00,0xA4,0x27, ++0x21,0x28,0x13,0x02, ++0x39,0x52,0x00,0x0C, ++0x04,0x00,0x06,0x24, ++0x21,0x28,0x12,0x02, ++0x10,0x00,0xA4,0x27, ++0xF0,0xFF,0x40,0x14, ++0x04,0x00,0x06,0x24, ++0x30,0x1F,0x85,0x26, ++0x08,0x00,0xA3,0x8C, ++0xC0,0xFF,0x02,0x3C, ++0xFF,0xFF,0x42,0x34, ++0x3F,0x00,0x24,0x32, ++0x24,0x18,0x62,0x00, ++0x00,0x24,0x04,0x00, ++0xFF,0x7F,0x02,0x3C, ++0x25,0x18,0x64,0x00, ++0xFF,0xFF,0x42,0x34, ++0x24,0x18,0x62,0x00, ++0x08,0x00,0xA3,0xAC, ++0x30,0x1F,0x82,0x26, ++0x0C,0x00,0x43,0x8C, ++0x00,0x40,0x04,0x3C, ++0x30,0x1F,0x85,0x26, ++0x25,0x18,0x64,0x00, ++0x0C,0x00,0x43,0xAC, ++0x0C,0x00,0xA2,0x8C, ++0x01,0x00,0x03,0x24, ++0x82,0x17,0x02,0x00, ++0x01,0x00,0x44,0x30, ++0x5D,0xFF,0x83,0x14, ++0x21,0x10,0x00,0x00, ++0xF0,0x5C,0x00,0x08, ++0x00,0x00,0x00,0x00, ++0xC6,0x02,0x02,0xA2, ++0x0A,0x5D,0x00,0x08, ++0xC4,0x02,0x13,0xA6, ++0x23,0x5C,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x1A,0x5D,0x00,0x08, ++0xC4,0x02,0x13,0xA6, ++0x25,0xB0,0x02,0x3C, ++0x88,0x0C,0x42,0x34, ++0x00,0x00,0x44,0x8C, ++0x02,0x80,0x03,0x3C, ++0x30,0x1F,0x66,0x24, ++0xC0,0xFF,0x02,0x3C, ++0x24,0x20,0x82,0x00, ++0x21,0x88,0x00,0x00, ++0xC0,0xFF,0x05,0x3C, ++0xA2,0x5D,0x00,0x08, ++0x18,0x00,0xC3,0x24, ++0x01,0x00,0x31,0x26, ++0x25,0x00,0x22,0x2E, ++0xB4,0xFF,0x40,0x10, ++0x25,0xB0,0x02,0x3C, ++0x00,0x00,0x62,0x8C, ++0x00,0x00,0x00,0x00, ++0x24,0x10,0x45,0x00, ++0xF8,0xFF,0x44,0x14, ++0x04,0x00,0x63,0x24, ++0x08,0x00,0xC2,0x8C, ++0x3F,0x00,0x23,0x32, ++0xFF,0xC0,0x04,0x24, ++0x24,0x10,0x44,0x00, ++0x00,0x1A,0x03,0x00, ++0x25,0x10,0x43,0x00, ++0x54,0x5D,0x00,0x08, ++0x08,0x00,0xC2,0xAC, ++0x08,0x00,0xA3,0x8C, ++0xC0,0xFF,0x02,0x3C, ++0xFF,0xFF,0x42,0x34, ++0x3F,0x00,0x24,0x32, ++0x24,0x18,0x62,0x00, ++0x00,0x24,0x04,0x00, ++0x25,0x18,0x64,0x00, ++0x00,0x80,0x02,0x3C, ++0x7D,0x5D,0x00,0x08, ++0x25,0x18,0x62,0x00, ++0x63,0x0C,0x23,0x36, ++0x00,0x00,0x62,0xA0, ++0x21,0x10,0x00,0x00, ++0x01,0x00,0x42,0x24, ++0xFF,0x00,0x42,0x30, ++0x06,0x00,0x43,0x2C, ++0xFD,0xFF,0x60,0x14, ++0x01,0x00,0x42,0x24, ++0x24,0x5D,0x00,0x08, ++0x30,0x1F,0x83,0x26, ++0x71,0x01,0x00,0x11, ++0x23,0x28,0xF2,0x00, ++0x2B,0x10,0x42,0x02, ++0x21,0x18,0xD2,0x00, ++0x00,0x00,0x42,0x38, ++0x24,0x00,0x08,0x24, ++0x2B,0x20,0x44,0x02, ++0x0B,0x40,0x62,0x00, ++0x06,0x00,0x80,0x10, ++0x20,0x00,0x15,0x24, ++0x30,0x1F,0x83,0x26, ++0x0A,0x00,0x62,0x94, ++0x00,0x00,0x00,0x00, ++0x3F,0x00,0x42,0x30, ++0x21,0xA8,0x52,0x00, ++0x2B,0x28,0xC8,0x02, ++0x5E,0x01,0xA0,0x10, ++0x30,0x1F,0x82,0x26, ++0x80,0x10,0x08,0x00, ++0x30,0x1F,0x83,0x26, ++0x21,0x10,0x43,0x00, ++0x18,0x00,0x44,0x8C, ++0x00,0x00,0x00,0x00, ++0x82,0x25,0x04,0x00, ++0x30,0x1F,0x86,0x26, ++0x0C,0x00,0xC3,0x8C, ++0x00,0x00,0x00,0x00, ++0xFF,0x03,0x67,0x30, ++0x47,0x01,0xE0,0x10, ++0x00,0x02,0x62,0x30, ++0x04,0x00,0x40,0x10, ++0x18,0x00,0xE4,0x00, ++0x00,0xFC,0x02,0x24, ++0x25,0x38,0xE2,0x00, ++0x18,0x00,0xE4,0x00, ++0x82,0x82,0x03,0x00, ++0xFF,0x03,0x10,0x32, ++0x00,0x02,0x03,0x32, ++0x12,0x10,0x00,0x00, ++0x02,0x12,0x02,0x00, ++0x03,0x00,0x60,0x10, ++0xFF,0x03,0x45,0x30, ++0x00,0xFC,0x02,0x24, ++0x25,0x80,0x02,0x02, ++0x18,0x00,0x04,0x02, ++0x80,0x1D,0x04,0x00, ++0x25,0xB0,0x11,0x3C, ++0x80,0x0C,0x24,0x36, ++0x94,0x0C,0x31,0x36, ++0x12,0x80,0x00,0x00, ++0x02,0x82,0x10,0x00, ++0x3F,0x00,0x02,0x32, ++0x00,0x14,0x02,0x00, ++0x25,0x18,0x62,0x00, ++0x25,0x18,0x65,0x00, ++0x21,0x28,0x60,0x00, ++0x02,0x5C,0x00,0x0C, ++0x10,0x00,0xA3,0xAF, ++0x00,0x00,0x23,0x8E, ++0xFF,0x0F,0x02,0x3C, ++0xC0,0x03,0x10,0x32, ++0xFF,0xFF,0x42,0x34, ++0x24,0x18,0x62,0x00, ++0x80,0x85,0x10,0x00, ++0x25,0x18,0x70,0x00, ++0x21,0x20,0x20,0x02, ++0x21,0x28,0x60,0x00, ++0x10,0x00,0xA3,0xAF, ++0x02,0x5C,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x30,0x1F,0x83,0x26, ++0x08,0x00,0x62,0x8C, ++0x00,0x00,0x00,0x00, ++0xB9,0x00,0x40,0x04, ++0xC0,0x28,0x15,0x00, ++0x21,0x10,0xA3,0x00, ++0xAC,0x00,0x44,0x90, ++0x25,0xB0,0x03,0x3C, ++0x22,0x0A,0x63,0x34, ++0x00,0x00,0x64,0xA0, ++0x21,0x10,0x00,0x00, ++0x01,0x00,0x42,0x24, ++0xFF,0x00,0x42,0x30, ++0x06,0x00,0x43,0x2C, ++0xFD,0xFF,0x60,0x14, ++0x01,0x00,0x42,0x24, ++0x30,0x1F,0x82,0x26, ++0x21,0x10,0xA2,0x00, ++0xAD,0x00,0x44,0x90, ++0x25,0xB0,0x03,0x3C, ++0x23,0x0A,0x63,0x34, ++0x00,0x00,0x64,0xA0, ++0x21,0x10,0x00,0x00, ++0x01,0x00,0x42,0x24, ++0xFF,0x00,0x42,0x30, ++0x06,0x00,0x43,0x2C, ++0xFD,0xFF,0x60,0x14, ++0x01,0x00,0x42,0x24, ++0x30,0x1F,0x82,0x26, ++0x21,0x10,0xA2,0x00, ++0xAE,0x00,0x44,0x90, ++0x25,0xB0,0x03,0x3C, ++0x24,0x0A,0x63,0x34, ++0x00,0x00,0x64,0xA0, ++0x21,0x10,0x00,0x00, ++0x01,0x00,0x42,0x24, ++0xFF,0x00,0x42,0x30, ++0x06,0x00,0x43,0x2C, ++0xFD,0xFF,0x60,0x14, ++0x01,0x00,0x42,0x24, ++0x30,0x1F,0x82,0x26, ++0x21,0x10,0xA2,0x00, ++0xAF,0x00,0x44,0x90, ++0x25,0xB0,0x03,0x3C, ++0x25,0x0A,0x63,0x34, ++0x00,0x00,0x64,0xA0, ++0x21,0x10,0x00,0x00, ++0x01,0x00,0x42,0x24, ++0xFF,0x00,0x42,0x30, ++0x06,0x00,0x43,0x2C, ++0xFD,0xFF,0x60,0x14, ++0x01,0x00,0x42,0x24, ++0x30,0x1F,0x82,0x26, ++0x21,0x10,0xA2,0x00, ++0xB0,0x00,0x44,0x90, ++0x25,0xB0,0x03,0x3C, ++0x26,0x0A,0x63,0x34, ++0x00,0x00,0x64,0xA0, ++0x21,0x10,0x00,0x00, ++0x01,0x00,0x42,0x24, ++0xFF,0x00,0x42,0x30, ++0x06,0x00,0x43,0x2C, ++0xFD,0xFF,0x60,0x14, ++0x01,0x00,0x42,0x24, ++0x30,0x1F,0x82,0x26, ++0x21,0x10,0xA2,0x00, ++0xB1,0x00,0x44,0x90, ++0x25,0xB0,0x03,0x3C, ++0x27,0x0A,0x63,0x34, ++0x00,0x00,0x64,0xA0, ++0x21,0x10,0x00,0x00, ++0x01,0x00,0x42,0x24, ++0xFF,0x00,0x42,0x30, ++0x06,0x00,0x43,0x2C, ++0xFD,0xFF,0x60,0x14, ++0x01,0x00,0x42,0x24, ++0x30,0x1F,0x82,0x26, ++0x21,0x10,0xA2,0x00, ++0xB2,0x00,0x44,0x90, ++0x25,0xB0,0x03,0x3C, ++0x28,0x0A,0x63,0x34, ++0x00,0x00,0x64,0xA0, ++0x21,0x10,0x00,0x00, ++0x01,0x00,0x42,0x24, ++0xFF,0x00,0x42,0x30, ++0x06,0x00,0x43,0x2C, ++0xFD,0xFF,0x60,0x14, ++0x01,0x00,0x42,0x24, ++0x30,0x1F,0x82,0x26, ++0x21,0x10,0xA2,0x00, ++0xB3,0x00,0x44,0x90, ++0x25,0xB0,0x03,0x3C, ++0x29,0x0A,0x63,0x34, ++0x00,0x00,0x64,0xA0, ++0x21,0x10,0x00,0x00, ++0x01,0x00,0x42,0x24, ++0xFF,0x00,0x42,0x30, ++0x06,0x00,0x43,0x2C, ++0xFD,0xFF,0x60,0x14, ++0x01,0x00,0x42,0x24, ++0x02,0x80,0x02,0x3C, ++0xDE,0x5D,0x44,0x90, ++0x22,0x00,0x03,0x24, ++0x03,0x00,0x83,0x10, ++0x92,0x00,0x02,0x24, ++0x73,0xFE,0x82,0x14, ++0x21,0x10,0x00,0x00, ++0x30,0x1F,0x82,0x26, ++0x08,0x00,0x43,0x8C, ++0x01,0x00,0x44,0x3A, ++0x24,0x00,0x02,0x24, ++0x02,0x1A,0x03,0x00, ++0x3F,0x00,0x63,0x30, ++0x01,0x00,0x84,0x30, ++0xF3,0x00,0x80,0x10, ++0x23,0x28,0x43,0x00, ++0x42,0x18,0x12,0x00, ++0x40,0x10,0x03,0x00, ++0x21,0x90,0x43,0x00, ++0x30,0x1F,0x83,0x26, ++0xC3,0x02,0x62,0x90, ++0x00,0x00,0x00,0x00, ++0x2B,0x10,0x62,0x02, ++0xB8,0x00,0x40,0x10, ++0x2B,0x10,0x45,0x02, ++0x06,0x00,0x40,0x10, ++0x24,0x00,0x06,0x24, ++0x08,0x00,0x62,0x8C, ++0x00,0x00,0x00,0x00, ++0x02,0x12,0x02,0x00, ++0x3F,0x00,0x42,0x30, ++0x21,0x30,0x52,0x00, ++0x2B,0x28,0xC6,0x02, ++0xB8,0x00,0xA0,0x10, ++0x30,0x1F,0x82,0x26, ++0x80,0x10,0x06,0x00, ++0x30,0x1F,0x83,0x26, ++0x21,0x10,0x43,0x00, ++0x18,0x00,0x44,0x8C, ++0x00,0x00,0x00,0x00, ++0x82,0x25,0x04,0x00, ++0x30,0x1F,0x83,0x26, ++0x10,0x00,0x70,0x8C, ++0x00,0x00,0x00,0x00, ++0x82,0x3A,0x10,0x00, ++0xFF,0x03,0xE7,0x30, ++0xC5,0x00,0xE0,0x10, ++0x00,0x02,0xE2,0x30, ++0x04,0x00,0x40,0x10, ++0x18,0x00,0xE4,0x00, ++0x00,0xFC,0x02,0x24, ++0x25,0x38,0xE2,0x00, ++0x18,0x00,0xE4,0x00, ++0x02,0x85,0x10,0x00, ++0xFF,0x03,0x10,0x32, ++0x00,0x02,0x03,0x32, ++0x12,0x10,0x00,0x00, ++0x02,0x12,0x02,0x00, ++0x03,0x00,0x60,0x10, ++0xFF,0x03,0x45,0x30, ++0x00,0xFC,0x02,0x24, ++0x25,0x80,0x02,0x02, ++0x18,0x00,0x04,0x02, ++0x80,0x1D,0x04,0x00, ++0x25,0xB0,0x11,0x3C, ++0x88,0x0C,0x24,0x36, ++0x9C,0x0C,0x31,0x36, ++0x12,0x80,0x00,0x00, ++0x02,0x82,0x10,0x00, ++0x3F,0x00,0x02,0x32, ++0x00,0x14,0x02,0x00, ++0x25,0x18,0x62,0x00, ++0x25,0x18,0x65,0x00, ++0x21,0x28,0x60,0x00, ++0x02,0x5C,0x00,0x0C, ++0x10,0x00,0xA3,0xAF, ++0x00,0x00,0x23,0x8E, ++0xFF,0x0F,0x02,0x3C, ++0xFF,0xFF,0x42,0x34, ++0xC0,0x03,0x10,0x32, ++0x24,0x18,0x62,0x00, ++0x80,0x85,0x10,0x00, ++0x25,0x18,0x70,0x00, ++0x21,0x20,0x20,0x02, ++0x21,0x28,0x60,0x00, ++0x02,0x5C,0x00,0x0C, ++0x10,0x00,0xA3,0xAF, ++0xE6,0x5C,0x00,0x08, ++0x21,0x10,0x00,0x00, ++0x21,0x10,0xA3,0x00, ++0xB4,0x01,0x44,0x90, ++0x25,0xB0,0x03,0x3C, ++0x22,0x0A,0x63,0x34, ++0x00,0x00,0x64,0xA0, ++0x21,0x10,0x00,0x00, ++0x01,0x00,0x42,0x24, ++0xFF,0x00,0x42,0x30, ++0x06,0x00,0x43,0x2C, ++0xFD,0xFF,0x60,0x14, ++0x01,0x00,0x42,0x24, ++0x30,0x1F,0x82,0x26, ++0x21,0x10,0xA2,0x00, ++0xB5,0x01,0x44,0x90, ++0x25,0xB0,0x03,0x3C, ++0x23,0x0A,0x63,0x34, ++0x00,0x00,0x64,0xA0, ++0x21,0x10,0x00,0x00, ++0x01,0x00,0x42,0x24, ++0xFF,0x00,0x42,0x30, ++0x06,0x00,0x43,0x2C, ++0xFD,0xFF,0x60,0x14, ++0x01,0x00,0x42,0x24, ++0x30,0x1F,0x82,0x26, ++0x21,0x10,0xA2,0x00, ++0xB6,0x01,0x44,0x90, ++0x25,0xB0,0x03,0x3C, ++0x24,0x0A,0x63,0x34, ++0x00,0x00,0x64,0xA0, ++0x21,0x10,0x00,0x00, ++0x01,0x00,0x42,0x24, ++0xFF,0x00,0x42,0x30, ++0x06,0x00,0x43,0x2C, ++0xFD,0xFF,0x60,0x14, ++0x01,0x00,0x42,0x24, ++0x30,0x1F,0x82,0x26, ++0x21,0x10,0xA2,0x00, ++0xB7,0x01,0x44,0x90, ++0x25,0xB0,0x03,0x3C, ++0x25,0x0A,0x63,0x34, ++0x00,0x00,0x64,0xA0, ++0x21,0x10,0x00,0x00, ++0x01,0x00,0x42,0x24, ++0xFF,0x00,0x42,0x30, ++0x06,0x00,0x43,0x2C, ++0xFD,0xFF,0x60,0x14, ++0x01,0x00,0x42,0x24, ++0x30,0x1F,0x82,0x26, ++0x21,0x10,0xA2,0x00, ++0xB8,0x01,0x44,0x90, ++0x25,0xB0,0x03,0x3C, ++0x26,0x0A,0x63,0x34, ++0x00,0x00,0x64,0xA0, ++0x21,0x10,0x00,0x00, ++0x01,0x00,0x42,0x24, ++0xFF,0x00,0x42,0x30, ++0x06,0x00,0x43,0x2C, ++0xFD,0xFF,0x60,0x14, ++0x01,0x00,0x42,0x24, ++0x30,0x1F,0x82,0x26, ++0x21,0x10,0xA2,0x00, ++0xB9,0x01,0x44,0x90, ++0x25,0xB0,0x03,0x3C, ++0x27,0x0A,0x63,0x34, ++0x00,0x00,0x64,0xA0, ++0x21,0x10,0x00,0x00, ++0x01,0x00,0x42,0x24, ++0xFF,0x00,0x42,0x30, ++0x06,0x00,0x43,0x2C, ++0xFD,0xFF,0x60,0x14, ++0x01,0x00,0x42,0x24, ++0x30,0x1F,0x82,0x26, ++0x21,0x10,0xA2,0x00, ++0xBA,0x01,0x44,0x90, ++0x25,0xB0,0x03,0x3C, ++0x28,0x0A,0x63,0x34, ++0x00,0x00,0x64,0xA0, ++0x21,0x10,0x00,0x00, ++0x01,0x00,0x42,0x24, ++0xFF,0x00,0x42,0x30, ++0x06,0x00,0x43,0x2C, ++0xFD,0xFF,0x60,0x14, ++0x01,0x00,0x42,0x24, ++0x30,0x1F,0x82,0x26, ++0x21,0x10,0xA2,0x00, ++0xBB,0x01,0x44,0x90, ++0x25,0xB0,0x03,0x3C, ++0x29,0x0A,0x63,0x34, ++0x00,0x00,0x64,0xA0, ++0x21,0x10,0x00,0x00, ++0x01,0x00,0x42,0x24, ++0xFF,0x00,0x42,0x30, ++0x06,0x00,0x43,0x2C, ++0xFC,0xFF,0x60,0x14, ++0x00,0x00,0x00,0x00, ++0x6E,0x5E,0x00,0x08, ++0x02,0x80,0x02,0x3C, ++0x36,0x00,0xA0,0x10, ++0x80,0x10,0x08,0x00, ++0x21,0x10,0x46,0x00, ++0x18,0x00,0x45,0x8C, ++0x25,0xB0,0x04,0x3C, ++0x02,0x5C,0x00,0x0C, ++0x80,0x0C,0x84,0x34, ++0x25,0xB0,0x04,0x3C, ++0x94,0x0C,0x84,0x34, ++0x07,0x5E,0x00,0x08, ++0x21,0x28,0x00,0x00, ++0x30,0x00,0x43,0x8C, ++0xDB,0x5D,0x00,0x08, ++0x82,0x25,0x03,0x00, ++0x23,0x20,0xD2,0x00, ++0x2B,0x10,0x46,0x02, ++0x2B,0x18,0x47,0x02, ++0x21,0x40,0x00,0x00, ++0x21,0xA8,0x00,0x00, ++0x0B,0x40,0x82,0x00, ++0xD2,0x5D,0x00,0x08, ++0x0B,0xA8,0xA3,0x00, ++0x08,0x00,0x62,0x8C, ++0x00,0x00,0x00,0x00, ++0x02,0x12,0x02,0x00, ++0x3F,0x00,0x42,0x30, ++0x2B,0x18,0x42,0x02, ++0x4A,0xFF,0x60,0x14, ++0x23,0x30,0x52,0x00, ++0x21,0x30,0x00,0x00, ++0x21,0x28,0x00,0x00, ++0x30,0x1F,0x82,0x26, ++0x30,0x00,0x43,0x8C, ++0x96,0x5E,0x00,0x08, ++0x82,0x25,0x03,0x00, ++0x0F,0x00,0x11,0x3C, ++0xFF,0xFF,0x25,0x36, ++0x60,0x00,0x06,0x24, ++0x5F,0x47,0x00,0x0C, ++0x24,0x00,0x04,0x24, ++0x25,0x22,0x00,0x0C, ++0xE8,0x03,0x04,0x24, ++0x00,0x60,0x10,0x40, ++0x01,0x00,0x01,0x36, ++0x01,0x00,0x21,0x38, ++0x00,0x60,0x81,0x40, ++0x24,0x00,0x04,0x24, ++0x8A,0x47,0x00,0x0C, ++0xFF,0xFF,0x25,0x36, ++0x1F,0x00,0x53,0x30, ++0x00,0x60,0x90,0x40, ++0x54,0x22,0x00,0x0C, ++0x64,0x00,0x04,0x24, ++0x06,0x5D,0x00,0x08, ++0x30,0x1F,0x90,0x26, ++0x30,0x00,0xC5,0x8C, ++0x2C,0x5F,0x00,0x08, ++0x25,0xB0,0x04,0x3C, ++0x13,0x00,0xA0,0x10, ++0x00,0x00,0x00,0x00, ++0x80,0x10,0x06,0x00, ++0x21,0x10,0x43,0x00, ++0x18,0x00,0x45,0x8C, ++0x25,0xB0,0x04,0x3C, ++0x02,0x5C,0x00,0x0C, ++0x88,0x0C,0x84,0x34, ++0x25,0xB0,0x04,0x3C, ++0x9C,0x0C,0x84,0x34, ++0x02,0x5C,0x00,0x0C, ++0x21,0x28,0x00,0x00, ++0xE6,0x5C,0x00,0x08, ++0x21,0x10,0x00,0x00, ++0xFF,0xFF,0x43,0x26, ++0x42,0x18,0x03,0x00, ++0x40,0x10,0x03,0x00, ++0x21,0x10,0x43,0x00, ++0x80,0x5E,0x00,0x08, ++0x01,0x00,0x52,0x24, ++0x30,0x00,0x65,0x8C, ++0x67,0x5F,0x00,0x08, ++0x25,0xB0,0x04,0x3C, ++0x00,0xFF,0x84,0x30, ++0x02,0x22,0x04,0x00, ++0x08,0x00,0x80,0x10, ++0x02,0x80,0x02,0x3C, ++0xFF,0x00,0x02,0x24, ++0x04,0x00,0x82,0x10, ++0xCC,0xFF,0x03,0x24, ++0x02,0x80,0x02,0x3C, ++0x08,0x00,0xE0,0x03, ++0x16,0x22,0x43,0xA0, ++0x02,0x80,0x02,0x3C, ++0x08,0x00,0xE0,0x03, ++0x16,0x22,0x44,0xA0, ++0x02,0x24,0x04,0x00, ++0xFF,0x00,0x84,0x30, ++0xC0,0x10,0x04,0x00, ++0x21,0x10,0x44,0x00, ++0x80,0x10,0x02,0x00, ++0x21,0x10,0x44,0x00, ++0x02,0x80,0x03,0x3C, ++0x80,0x10,0x02,0x00, ++0x30,0x1F,0x63,0x24, ++0x20,0x00,0x84,0x2C, ++0x09,0x00,0x80,0x10, ++0x21,0x10,0x43,0x00, ++0x0C,0x24,0x43,0x8C, ++0x25,0xB0,0x02,0x3C, ++0x74,0x03,0x42,0x34, ++0x02,0x19,0x03,0x00, ++0x7F,0x00,0x63,0x30, ++0x00,0x00,0x43,0xAC, ++0x08,0x00,0xE0,0x03, ++0x00,0x00,0x00,0x00, ++0x02,0x80,0x02,0x3C, ++0xB0,0x55,0x43,0x8C, ++0x25,0xB0,0x02,0x3C, ++0x74,0x03,0x42,0x34, ++0x02,0x19,0x03,0x00, ++0x7F,0x00,0x63,0x30, ++0x00,0x00,0x43,0xAC, ++0x08,0x00,0xE0,0x03, ++0x00,0x00,0x00,0x00, ++0xFF,0x00,0x85,0x30, ++0xD2,0xFF,0xA3,0x24, ++0xFE,0xFF,0xA2,0x24, ++0xDA,0xFF,0xA4,0x24, ++0x04,0x00,0x63,0x2C, ++0x08,0x00,0x84,0x2C, ++0x06,0x00,0x60,0x14, ++0xFF,0x00,0x42,0x30, ++0xF0,0xFF,0xA2,0x24, ++0xFC,0xFF,0xA3,0x24, ++0x16,0x00,0x46,0x2C, ++0x03,0x00,0x80,0x10, ++0xFF,0x00,0x62,0x30, ++0x08,0x00,0xE0,0x03, ++0x00,0x00,0x00,0x00, ++0xFA,0xFF,0xA3,0x24, ++0xFC,0xFF,0xC0,0x10, ++0x21,0x10,0xA0,0x00, ++0x08,0x00,0xE0,0x03, ++0xFF,0x00,0x62,0x30, ++0x25,0xB0,0x03,0x3C, ++0x03,0x0D,0x63,0x34, ++0x00,0x00,0x62,0x90, ++0x21,0x20,0x00,0x00, ++0xFF,0x00,0x42,0x30, ++0x08,0x00,0x42,0x34, ++0x00,0x00,0x62,0xA0, ++0x01,0x00,0x82,0x24, ++0xFF,0x00,0x44,0x30, ++0x06,0x00,0x83,0x2C, ++0xFD,0xFF,0x60,0x14, ++0x01,0x00,0x82,0x24, ++0x25,0xB0,0x03,0x3C, ++0x03,0x0D,0x63,0x34, ++0x00,0x00,0x62,0x90, ++0x21,0x20,0x00,0x00, ++0xF7,0x00,0x42,0x30, ++0x00,0x00,0x62,0xA0, ++0x01,0x00,0x82,0x24, ++0xFF,0x00,0x44,0x30, ++0x06,0x00,0x83,0x2C, ++0xFD,0xFF,0x60,0x14, ++0x01,0x00,0x82,0x24, ++0x25,0xB0,0x03,0x3C, ++0x2D,0x0A,0x63,0x34, ++0x00,0x00,0x62,0x90, ++0x21,0x20,0x00,0x00, ++0x3F,0x00,0x42,0x30, ++0x00,0x00,0x62,0xA0, ++0x01,0x00,0x82,0x24, ++0xFF,0x00,0x44,0x30, ++0x06,0x00,0x83,0x2C, ++0xFD,0xFF,0x60,0x14, ++0x01,0x00,0x82,0x24, ++0x25,0xB0,0x03,0x3C, ++0x2D,0x0A,0x63,0x34, ++0x00,0x00,0x62,0x90, ++0x21,0x20,0x00,0x00, ++0xFF,0x00,0x42,0x30, ++0x80,0x00,0x42,0x34, ++0x00,0x00,0x62,0xA0, ++0x01,0x00,0x82,0x24, ++0xFF,0x00,0x44,0x30, ++0x06,0x00,0x83,0x2C, ++0xFC,0xFF,0x60,0x14, ++0x00,0x00,0x00,0x00, ++0x08,0x00,0xE0,0x03, ++0x00,0x00,0x00,0x00, ++0x25,0xB0,0x02,0x3C, ++0xFF,0x00,0x03,0x3C, ++0x82,0x01,0x49,0x34, ++0x81,0x01,0x48,0x34, ++0x24,0x10,0x83,0x00, ++0x02,0x3C,0x02,0x00, ++0x00,0xFF,0x63,0x34, ++0x02,0x80,0x02,0x3C, ++0x30,0x1F,0x45,0x24, ++0x02,0x32,0x04,0x00, ++0x01,0x00,0x02,0x24, ++0x24,0x20,0x83,0x00, ++0xE6,0x1D,0xA2,0xA0, ++0xD4,0x1D,0xA0,0xAC, ++0xD8,0x1D,0xA0,0xAC, ++0xDC,0x1D,0xA0,0xAC, ++0x06,0x00,0x80,0x14, ++0xE0,0x1D,0xA0,0xAC, ++0x00,0x00,0x02,0x91, ++0x00,0x00,0x23,0x91, ++0xE4,0x1D,0xA2,0xA0, ++0x08,0x00,0xE0,0x03, ++0xE5,0x1D,0xA3,0xA0, ++0xE5,0x1D,0xA7,0xA0, ++0x08,0x00,0xE0,0x03, ++0xE4,0x1D,0xA6,0xA0, ++0x02,0x80,0x03,0x3C, ++0x30,0x1F,0x63,0x24, ++0xE5,0x1D,0x66,0x90, ++0xE4,0x1D,0x65,0x90, ++0x25,0xB0,0x02,0x3C, ++0x82,0x01,0x44,0x34, ++0x81,0x01,0x42,0x34, ++0x00,0x00,0x45,0xA0, ++0x00,0x00,0x86,0xA0, ++0x08,0x00,0xE0,0x03, ++0xE6,0x1D,0x60,0xA0, ++0x02,0x80,0x08,0x3C, ++0x30,0x1F,0x04,0x25, ++0xE6,0x1D,0x82,0x90, ++0x00,0x00,0x00,0x00, ++0x15,0x00,0x40,0x10, ++0x21,0x18,0x00,0x00, ++0xD8,0x1D,0x82,0x8C, ++0xD4,0x1D,0x85,0x8C, ++0x25,0xB0,0x03,0x3C, ++0x40,0x11,0x02,0x00, ++0x2B,0x10,0xA2,0x00, ++0x82,0x01,0x67,0x34, ++0x0F,0x00,0x40,0x10, ++0x81,0x01,0x66,0x34, ++0xE5,0x1D,0x83,0x90, ++0xE4,0x1D,0x82,0x90, ++0xF0,0x00,0x63,0x30, ++0x1F,0x00,0x42,0x30, ++0x00,0x00,0xC2,0xA0, ++0x00,0x00,0xE3,0xA0, ++0x30,0x1F,0x02,0x25, ++0x01,0x00,0x03,0x24, ++0xE0,0x1D,0x40,0xAC, ++0xD4,0x1D,0x40,0xAC, ++0xD8,0x1D,0x40,0xAC, ++0xDC,0x1D,0x40,0xAC, ++0x08,0x00,0xE0,0x03, ++0x21,0x10,0x60,0x00, ++0xDC,0x1D,0x82,0x8C, ++0x25,0xB0,0x03,0x3C, ++0x82,0x01,0x69,0x34, ++0x40,0x11,0x02,0x00, ++0x2B,0x10,0xA2,0x00, ++0x0E,0x00,0x40,0x14, ++0x81,0x01,0x66,0x34, ++0xE0,0x1D,0x82,0x8C, ++0x00,0x00,0x00,0x00, ++0x40,0x11,0x02,0x00, ++0x2B,0x10,0xA2,0x00, ++0x08,0x00,0x40,0x14, ++0x00,0x00,0x00,0x00, ++0xE5,0x1D,0x83,0x90, ++0xE4,0x1D,0x82,0x90, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0xC2,0xA0, ++0x00,0x00,0x23,0xA1, ++0x20,0x60,0x00,0x08, ++0x30,0x1F,0x02,0x25, ++0xE5,0x1D,0x83,0x90, ++0xE4,0x1D,0x82,0x90, ++0xF0,0x00,0x63,0x30, ++0x7F,0x00,0x42,0x30, ++0x00,0x00,0xC2,0xA0, ++0x00,0x00,0x23,0xA1, ++0x20,0x60,0x00,0x08, ++0x30,0x1F,0x02,0x25, ++0x00,0x00,0x85,0xAC, ++0x21,0x10,0x00,0x00, ++0x01,0x00,0x42,0x24, ++0xFF,0x00,0x42,0x30, ++0x06,0x00,0x43,0x2C, ++0xFC,0xFF,0x60,0x14, ++0x00,0x00,0x00,0x00, ++0x08,0x00,0xE0,0x03, ++0x00,0x00,0x00,0x00, ++0x25,0xB0,0x03,0x3C, ++0x33,0x02,0x65,0x34, ++0x00,0x11,0x04,0x00, ++0x00,0x00,0xA2,0xA0, ++0x30,0x02,0x63,0x34, ++0x00,0x00,0x65,0x8C, ++0x0F,0x00,0x02,0x3C, ++0xFF,0xFF,0x42,0x34, ++0x24,0x28,0xA2,0x00, ++0x01,0x00,0x03,0x24, ++0x04,0x18,0x83,0x00, ++0x02,0x00,0xA0,0x10, ++0x21,0x10,0x00,0x00, ++0xFF,0xFF,0x62,0x30, ++0x08,0x00,0xE0,0x03, ++0x00,0x00,0x00,0x00, ++0xE0,0xFF,0xBD,0x27, ++0x14,0x00,0xB1,0xAF, ++0x25,0xB0,0x11,0x3C, ++0x18,0x00,0xB2,0xAF, ++0x4C,0x00,0x22,0x36, ++0x1C,0x00,0xBF,0xAF, ++0x10,0x00,0xB0,0xAF, ++0x00,0x00,0x44,0x90, ++0x02,0x80,0x03,0x3C, ++0x02,0x00,0x02,0x24, ++0xFF,0x00,0x84,0x30, ++0x07,0x00,0x82,0x10, ++0x30,0x1F,0x72,0x24, ++0x1C,0x00,0xBF,0x8F, ++0x18,0x00,0xB2,0x8F, ++0x14,0x00,0xB1,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x08,0x00,0xE0,0x03, ++0x20,0x00,0xBD,0x27, ++0x8A,0x36,0x43,0x96, ++0x01,0x00,0x02,0x24, ++0xF7,0xFF,0x62,0x14, ++0x00,0x00,0x00,0x00, ++0x02,0x80,0x02,0x3C, ++0xF4,0x5E,0x43,0x90, ++0x00,0x00,0x00,0x00, ++0xF2,0xFF,0x60,0x14, ++0x21,0x20,0x00,0x00, ++0x4C,0x60,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x04,0x00,0x04,0x24, ++0x4C,0x60,0x00,0x0C, ++0x21,0x80,0x40,0x00, ++0x25,0x80,0x02,0x02, ++0x02,0x80,0x04,0x3C, ++0x33,0x02,0x23,0x36, ++0x08,0x00,0x02,0x24, ++0xFF,0xFF,0x10,0x32, ++0x40,0x00,0x27,0x36, ++0xEC,0xE8,0x84,0x24, ++0x00,0x00,0x62,0xA0, ++0xE3,0xFF,0x00,0x16, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0xE2,0x94, ++0x88,0x36,0x43,0x96, ++0xFF,0xDF,0x42,0x30, ++0x01,0x00,0x63,0x24, ++0x00,0x20,0x46,0x34, ++0x88,0x36,0x43,0xA6, ++0xFF,0xFF,0x65,0x30, ++0x00,0x00,0xE2,0xA4, ++0x00,0x00,0xE6,0xA4, ++0x2F,0x55,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x69,0x60,0x00,0x08, ++0x00,0x00,0x00,0x00, ++0x25,0xB0,0x02,0x3C, ++0x21,0x20,0x82,0x00, ++0x00,0x00,0x85,0xAC, ++0x21,0x10,0x00,0x00, ++0x01,0x00,0x42,0x24, ++0xFF,0x00,0x42,0x30, ++0x06,0x00,0x43,0x2C, ++0xFC,0xFF,0x60,0x14, ++0x00,0x00,0x00,0x00, ++0x08,0x00,0xE0,0x03, ++0x00,0x00,0x00,0x00, ++0xE8,0xFF,0xBD,0x27, ++0x10,0x00,0xBF,0xAF, ++0xDF,0x2F,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x10,0x00,0xBF,0x8F, ++0x02,0x80,0x02,0x3C, ++0xE8,0x03,0x03,0x24, ++0x34,0x5F,0x43,0xAC, ++0x18,0x00,0xBD,0x27, ++0x08,0x00,0xE0,0x03, ++0x21,0x10,0x00,0x00, ++0x08,0x00,0xE0,0x03, ++0x00,0x00,0x00,0x00, ++0x08,0x00,0xE0,0x03, ++0x00,0x00,0x00,0x00, ++0x08,0x00,0xE0,0x03, ++0x00,0x00,0x00,0x00, ++0x08,0x00,0xE0,0x03, ++0x00,0x00,0x00,0x00, ++0x08,0x00,0xE0,0x03, ++0x00,0x00,0x00,0x00, ++0x08,0x00,0xE0,0x03, ++0x00,0x00,0x00,0x00, ++0x02,0x80,0x02,0x3C, ++0xFA,0x5E,0x40,0xA0, ++0xFF,0x00,0x85,0x30, ++0x02,0x80,0x03,0x3C, ++0x02,0x80,0x02,0x3C, ++0x0C,0x5F,0x60,0xA0, ++0x08,0x00,0xA4,0x2C, ++0x0E,0x5F,0x40,0xA0, ++0x02,0x80,0x03,0x3C, ++0x02,0x80,0x02,0x3C, ++0x16,0x5F,0x60,0xA0, ++0xF4,0x5E,0x45,0xA0, ++0x2C,0x00,0x80,0x10, ++0x02,0x80,0x03,0x3C, ++0x80,0x10,0x05,0x00, ++0x94,0xF0,0x63,0x24, ++0x21,0x10,0x43,0x00, ++0x00,0x00,0x44,0x8C, ++0x00,0x00,0x00,0x00, ++0x08,0x00,0x80,0x00, ++0x00,0x00,0x00,0x00, ++0x02,0x80,0x05,0x3C, ++0x30,0x1F,0xA5,0x24, ++0xD0,0x1B,0xA4,0x8C, ++0x00,0x70,0x02,0x3C, ++0x02,0x00,0x42,0x34, ++0x25,0x20,0x82,0x00, ++0x41,0xB0,0x03,0x3C, ++0x00,0x00,0x64,0xAC, ++0x08,0x00,0xE0,0x03, ++0xD0,0x1B,0xA4,0xAC, ++0x02,0x80,0x05,0x3C, ++0x30,0x1F,0xA5,0x24, ++0xD0,0x1B,0xA4,0x8C, ++0x00,0x70,0x02,0x3C, ++0x02,0x00,0x42,0x34, ++0x27,0x10,0x02,0x00, ++0x24,0x20,0x82,0x00, ++0x41,0xB0,0x03,0x3C, ++0x00,0x00,0x64,0xAC, ++0x08,0x00,0xE0,0x03, ++0xD0,0x1B,0xA4,0xAC, ++0x02,0x80,0x05,0x3C, ++0x30,0x1F,0xA5,0x24, ++0xD0,0x1B,0xA4,0x8C, ++0x00,0x70,0x02,0x3C, ++0x27,0x10,0x02,0x00, ++0x24,0x20,0x82,0x00, ++0x02,0x80,0x07,0x3C, ++0x41,0xB0,0x02,0x3C, ++0x01,0x00,0x03,0x24, ++0x00,0x00,0x44,0xAC, ++0x10,0x5F,0xE3,0xA0, ++0x10,0x5F,0xE6,0x90, ++0x02,0x80,0x02,0x3C, ++0xD0,0x1B,0xA4,0xAC, ++0x11,0x5F,0x46,0xA0, ++0x08,0x00,0xE0,0x03, ++0x00,0x00,0x00,0x00, ++0x02,0x80,0x05,0x3C, ++0x30,0x1F,0xA5,0x24, ++0xD0,0x1B,0xA4,0x8C, ++0x00,0x70,0x02,0x3C, ++0x27,0x10,0x02,0x00, ++0x24,0x20,0x82,0x00, ++0x41,0xB0,0x03,0x3C, ++0x00,0x00,0x64,0xAC, ++0x08,0x00,0xE0,0x03, ++0xD0,0x1B,0xA4,0xAC, ++0xE0,0xFF,0xBD,0x27, ++0x10,0x00,0xB0,0xAF, ++0x02,0x80,0x10,0x3C, ++0xF4,0x5E,0x02,0x92, ++0x18,0x00,0xB2,0xAF, ++0x14,0x00,0xB1,0xAF, ++0x1C,0x00,0xBF,0xAF, ++0x21,0x90,0x80,0x00, ++0x1C,0x00,0x40,0x10, ++0xFF,0x00,0xB1,0x30, ++0x02,0x80,0x03,0x3C, ++0xDE,0x5D,0x62,0x90, ++0x00,0x00,0x00,0x00, ++0x02,0x00,0x42,0x30, ++0x1C,0x00,0x40,0x14, ++0x00,0x00,0x00,0x00, ++0x00,0x08,0x04,0x24, ++0x00,0x02,0x05,0x3C, ++0xA9,0x45,0x00,0x0C, ++0x01,0x00,0x06,0x24, ++0x02,0x80,0x03,0x3C, ++0xF6,0x5E,0x62,0x90, ++0x00,0x00,0x00,0x00, ++0x0F,0x00,0x42,0x30, ++0x0C,0x00,0x42,0x28, ++0x06,0x00,0x40,0x10, ++0x08,0x00,0x02,0x24, ++0x00,0x00,0x44,0x96, ++0x00,0x00,0x00,0x00, ++0x0C,0x00,0x83,0x30, ++0x1B,0x00,0x62,0x10, ++0x02,0x80,0x02,0x3C, ++0xF4,0x5E,0x02,0x92, ++0x05,0x00,0x03,0x24, ++0xFF,0x00,0x42,0x30, ++0x0B,0x00,0x43,0x10, ++0x02,0x80,0x03,0x3C, ++0x1C,0x00,0xBF,0x8F, ++0x18,0x00,0xB2,0x8F, ++0x14,0x00,0xB1,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x08,0x00,0xE0,0x03, ++0x20,0x00,0xBD,0x27, ++0x9B,0x30,0x00,0x0C, ++0x01,0x00,0x04,0x24, ++0x0C,0x61,0x00,0x08, ++0x00,0x08,0x04,0x24, ++0x0F,0x5F,0x62,0x90, ++0x00,0x00,0x00,0x00, ++0x24,0x10,0x22,0x02, ++0xF2,0xFF,0x40,0x10, ++0x02,0x80,0x03,0x3C, ++0x0E,0x5F,0x62,0x90, ++0x00,0x00,0x00,0x00, ++0x04,0x00,0x42,0x34, ++0x0E,0x5F,0x62,0xA0, ++0x20,0x61,0x00,0x08, ++0x00,0x00,0x00,0x00, ++0x0D,0x5F,0x43,0x90, ++0x00,0x00,0x00,0x00, ++0x03,0x00,0x60,0x14, ++0x00,0x10,0x82,0x34, ++0x1B,0x61,0x00,0x08, ++0x00,0x00,0x42,0xA6, ++0x0C,0x00,0x04,0x24, ++0x64,0x31,0x00,0x0C, ++0x21,0x28,0x00,0x00, ++0x1B,0x61,0x00,0x08, ++0x00,0x00,0x00,0x00, ++0xE8,0xFF,0xBD,0x27, ++0xFF,0x00,0xA5,0x30, ++0x10,0x00,0xB0,0xAF, ++0x14,0x00,0xBF,0xAF, ++0x18,0x00,0xA0,0x14, ++0xFF,0x00,0x90,0x30, ++0x2C,0x00,0x00,0x12, ++0x01,0x00,0x05,0x24, ++0x02,0x80,0x03,0x3C, ++0x01,0x00,0x07,0x24, ++0x0C,0x5F,0x67,0xA0, ++0x02,0x80,0x08,0x3C, ++0x0E,0x5F,0x02,0x91, ++0x02,0x00,0x04,0x24, ++0x21,0x28,0x00,0x00, ++0x02,0x00,0x42,0x34, ++0x00,0xF0,0x06,0x34, ++0x0E,0x5F,0x02,0xA1, ++0x8C,0x23,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x14,0x00,0xBF,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x42,0xB0,0x02,0x3C, ++0x44,0x00,0x03,0x24, ++0x03,0x00,0x42,0x34, ++0x18,0x00,0xBD,0x27, ++0x00,0x00,0x43,0xA0, ++0x08,0x00,0xE0,0x03, ++0x00,0x00,0x00,0x00, ++0x01,0x00,0x03,0x24, ++0x02,0x80,0x02,0x3C, ++0x0C,0x5F,0x43,0xA0, ++0x02,0x80,0x02,0x3C, ++0x0F,0x5F,0x43,0x90, ++0x0F,0x00,0x02,0x24, ++0x02,0x80,0x05,0x3C, ++0x0F,0x00,0x63,0x30, ++0x07,0x00,0x62,0x10, ++0x01,0x00,0x04,0x24, ++0x0E,0x5F,0xA2,0x90, ++0x00,0x00,0x00,0x00, ++0x01,0x00,0x42,0x34, ++0x0E,0x5F,0xA2,0xA0, ++0xFE,0x4E,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0xDB,0xFF,0x00,0x16, ++0x02,0x80,0x03,0x3C, ++0x14,0x00,0xBF,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x08,0x00,0xE0,0x03, ++0x18,0x00,0xBD,0x27, ++0x02,0x80,0x02,0x3C, ++0x0C,0x5F,0x40,0xA0, ++0x02,0x80,0x03,0x3C, ++0xF5,0x5E,0x64,0x90, ++0x14,0x00,0xBF,0x8F, ++0x10,0x00,0xB0,0x8F, ++0xFF,0x00,0x84,0x30, ++0x64,0x31,0x00,0x08, ++0x18,0x00,0xBD,0x27, ++0xE0,0xFF,0xBD,0x27, ++0xFF,0x00,0xA5,0x30, ++0x14,0x00,0xB1,0xAF, ++0x18,0x00,0xBF,0xAF, ++0x10,0x00,0xB0,0xAF, ++0x03,0x00,0xA0,0x14, ++0xFF,0x00,0x91,0x30, ++0x3A,0x00,0x20,0x12, ++0x02,0x80,0x02,0x3C, ++0x02,0x80,0x10,0x3C, ++0x0E,0x5F,0x02,0x92, ++0xFB,0xFF,0x03,0x24, ++0x24,0x10,0x43,0x00, ++0x0E,0x5F,0x02,0xA2, ++0x10,0x00,0xA0,0x14, ++0x02,0x80,0x03,0x3C, ++0x0E,0x5F,0x02,0x92, ++0xFE,0xFF,0x03,0x24, ++0x24,0x10,0x43,0x00, ++0x0E,0x5F,0x02,0xA2, ++0x19,0x00,0x20,0x16, ++0x02,0x80,0x02,0x3C, ++0x0E,0x5F,0x02,0x92, ++0xFD,0xFF,0x03,0x24, ++0x18,0x00,0xBF,0x8F, ++0x24,0x10,0x43,0x00, ++0x0E,0x5F,0x02,0xA2, ++0x14,0x00,0xB1,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x08,0x00,0xE0,0x03, ++0x20,0x00,0xBD,0x27, ++0x01,0x00,0x04,0x24, ++0x0C,0x5F,0x64,0xA0, ++0x0E,0x5F,0x02,0x92, ++0x02,0x80,0x03,0x3C, ++0x01,0x00,0x42,0x34, ++0x0E,0x5F,0x02,0xA2, ++0x0D,0x5F,0x62,0x90, ++0x02,0x00,0x03,0x24, ++0xFF,0x00,0x42,0x30, ++0x23,0x00,0x43,0x10, ++0x00,0x00,0x00,0x00, ++0xFE,0x4E,0x00,0x0C, ++0x01,0x00,0x04,0x24, ++0xE9,0xFF,0x20,0x12, ++0x02,0x80,0x02,0x3C, ++0x01,0x00,0x04,0x24, ++0x0C,0x5F,0x44,0xA0, ++0x0E,0x5F,0x03,0x92, ++0x02,0x00,0x04,0x24, ++0x21,0x28,0x00,0x00, ++0x02,0x00,0x63,0x34, ++0x00,0xF0,0x06,0x34, ++0x0E,0x5F,0x03,0xA2, ++0x8C,0x23,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x18,0x00,0xBF,0x8F, ++0x14,0x00,0xB1,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x42,0xB0,0x02,0x3C, ++0x44,0x00,0x03,0x24, ++0x03,0x00,0x42,0x34, ++0x20,0x00,0xBD,0x27, ++0x00,0x00,0x43,0xA0, ++0x08,0x00,0xE0,0x03, ++0x00,0x00,0x00,0x00, ++0x0C,0x5F,0x40,0xA0, ++0x02,0x80,0x03,0x3C, ++0xF5,0x5E,0x64,0x90, ++0x18,0x00,0xBF,0x8F, ++0x14,0x00,0xB1,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x01,0x00,0x05,0x24, ++0xFF,0x00,0x84,0x30, ++0x64,0x31,0x00,0x08, ++0x20,0x00,0xBD,0x27, ++0x0D,0x30,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x0C,0x00,0x04,0x24, ++0x64,0x31,0x00,0x0C, ++0x01,0x00,0x05,0x24, ++0x90,0x61,0x00,0x08, ++0x00,0x00,0x00,0x00, ++0xE8,0xFF,0xBD,0x27, ++0x10,0x00,0xB2,0xAF, ++0x0C,0x00,0xB1,0xAF, ++0x08,0x00,0xB0,0xAF, ++0x21,0x40,0xE0,0x00, ++0x21,0x90,0xA0,0x03, ++0x21,0x60,0xC0,0x00, ++0x21,0x78,0x80,0x00, ++0x45,0x00,0xE0,0x14, ++0x21,0x50,0xA0,0x00, ++0x2B,0x10,0xA6,0x00, ++0x78,0x00,0x40,0x10, ++0xFF,0xFF,0x02,0x34, ++0x2B,0x10,0x46,0x00, ++0x8F,0x01,0x40,0x10, ++0x21,0x28,0xC0,0x00, ++0xFF,0x00,0x02,0x3C, ++0xFF,0xFF,0x42,0x34, ++0x10,0x00,0x03,0x24, ++0x2B,0x10,0x46,0x00, ++0x18,0x00,0x04,0x24, ++0x21,0x30,0x60,0x00, ++0x0B,0x30,0x82,0x00, ++0x02,0x80,0x03,0x3C, ++0x06,0x10,0xC5,0x00, ++0xB4,0xF0,0x63,0x24, ++0x21,0x10,0x43,0x00, ++0x00,0x00,0x44,0x90, ++0x20,0x00,0x02,0x24, ++0x21,0x20,0x86,0x00, ++0x23,0x30,0x44,0x00, ++0x08,0x00,0xC0,0x10, ++0x02,0x4C,0x0C,0x00, ++0x23,0x10,0x46,0x00, ++0x06,0x10,0x4F,0x00, ++0x04,0x18,0xCA,0x00, ++0x25,0x50,0x62,0x00, ++0x04,0x60,0xCC,0x00, ++0x04,0x78,0xCF,0x00, ++0x02,0x4C,0x0C,0x00, ++0x1B,0x00,0x49,0x01, ++0x02,0x00,0x20,0x15, ++0x00,0x00,0x00,0x00, ++0x0D,0x00,0x07,0x00, ++0xFF,0xFF,0x87,0x31, ++0x02,0x24,0x0F,0x00, ++0x12,0x18,0x00,0x00, ++0x10,0x28,0x00,0x00, ++0x00,0x14,0x05,0x00, ++0x25,0x28,0x44,0x00, ++0x18,0x00,0x67,0x00, ++0x12,0x58,0x00,0x00, ++0x2B,0x18,0xAB,0x00, ++0x00,0x00,0x00,0x00, ++0x1B,0x00,0x49,0x01, ++0x02,0x00,0x20,0x15, ++0x00,0x00,0x00,0x00, ++0x0D,0x00,0x07,0x00, ++0x08,0x00,0x60,0x10, ++0x00,0x00,0x00,0x00, ++0x21,0x28,0xAC,0x00, ++0x2B,0x10,0xAC,0x00, ++0x04,0x00,0x40,0x14, ++0x2B,0x10,0xAB,0x00, ++0x00,0x00,0x42,0x38, ++0x21,0x18,0xAC,0x00, ++0x0B,0x28,0x62,0x00, ++0x23,0x28,0xAB,0x00, ++0x1B,0x00,0xA9,0x00, ++0x02,0x00,0x20,0x15, ++0x00,0x00,0x00,0x00, ++0x0D,0x00,0x07,0x00, ++0xFF,0xFF,0xE4,0x31, ++0x12,0x18,0x00,0x00, ++0x10,0x40,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x8F,0x62,0x00,0x08, ++0x18,0x00,0x67,0x00, ++0x2B,0x10,0xA7,0x00, ++0x0A,0x00,0x40,0x10, ++0xFF,0xFF,0x02,0x34, ++0x10,0x00,0xB2,0x8F, ++0x0C,0x00,0xB1,0x8F, ++0x08,0x00,0xB0,0x8F, ++0x21,0x10,0x80,0x00, ++0x21,0x18,0xA0,0x00, ++0x00,0x00,0xA4,0xAF, ++0x04,0x00,0xA5,0xAF, ++0x08,0x00,0xE0,0x03, ++0x18,0x00,0xBD,0x27, ++0x2B,0x10,0x47,0x00, ++0xD2,0x00,0x40,0x10, ++0x00,0x01,0xE3,0x2C, ++0xFF,0x00,0x02,0x3C, ++0x10,0x00,0x03,0x24, ++0xFF,0xFF,0x42,0x34, ++0x2B,0x10,0x47,0x00, ++0x18,0x00,0x04,0x24, ++0x21,0x28,0x60,0x00, ++0x0B,0x28,0x82,0x00, ++0x06,0x10,0xA8,0x00, ++0x02,0x80,0x03,0x3C, ++0xB4,0xF0,0x63,0x24, ++0x21,0x10,0x43,0x00, ++0x00,0x00,0x44,0x90, ++0x20,0x00,0x02,0x24, ++0x21,0x20,0x85,0x00, ++0x23,0x30,0x44,0x00, ++0xCE,0x00,0xC0,0x14, ++0x23,0x38,0x46,0x00, ++0x2B,0x10,0x0A,0x01, ++0x04,0x00,0x40,0x14, ++0x23,0x20,0xEC,0x01, ++0x2B,0x10,0xEC,0x01, ++0x05,0x00,0x40,0x14, ++0x00,0x00,0x00,0x00, ++0x2B,0x10,0xE4,0x01, ++0x23,0x18,0x48,0x01, ++0x23,0x50,0x62,0x00, ++0x21,0x78,0x80,0x00, ++0x04,0x00,0x40,0x12, ++0x21,0xC0,0xE0,0x01, ++0x21,0xC8,0x40,0x01, ++0x00,0x00,0x58,0xAE, ++0x04,0x00,0x59,0xAE, ++0x00,0x00,0xA2,0x8F, ++0x04,0x00,0xA3,0x8F, ++0x10,0x00,0xB2,0x8F, ++0x0C,0x00,0xB1,0x8F, ++0x08,0x00,0xB0,0x8F, ++0x08,0x00,0xE0,0x03, ++0x18,0x00,0xBD,0x27, ++0x53,0x00,0xC0,0x10, ++0x01,0x00,0x02,0x24, ++0xFF,0xFF,0x02,0x34, ++0x2B,0x10,0x4C,0x00, ++0x59,0x00,0x40,0x14, ++0xFF,0x00,0x02,0x3C, ++0x00,0x01,0x83,0x2D, ++0x08,0x00,0x02,0x24, ++0x21,0x28,0x00,0x00, ++0x0A,0x28,0x43,0x00, ++0x06,0x10,0xAC,0x00, ++0x02,0x80,0x03,0x3C, ++0xB4,0xF0,0x63,0x24, ++0x21,0x10,0x43,0x00, ++0x00,0x00,0x44,0x90, ++0x20,0x00,0x02,0x24, ++0x21,0x20,0x85,0x00, ++0x23,0x30,0x44,0x00, ++0x5B,0x00,0xC0,0x14, ++0x00,0x00,0x00,0x00, ++0x23,0x50,0x4C,0x01, ++0x02,0x4C,0x0C,0x00, ++0xFF,0xFF,0x8D,0x31, ++0x1B,0x00,0x49,0x01, ++0x02,0x00,0x20,0x15, ++0x00,0x00,0x00,0x00, ++0x0D,0x00,0x07,0x00, ++0x02,0x24,0x0F,0x00, ++0x12,0x18,0x00,0x00, ++0x10,0x28,0x00,0x00, ++0x00,0x14,0x05,0x00, ++0x25,0x28,0x44,0x00, ++0x18,0x00,0x6D,0x00, ++0x12,0x58,0x00,0x00, ++0x2B,0x18,0xAB,0x00, ++0x00,0x00,0x00,0x00, ++0x1B,0x00,0x49,0x01, ++0x02,0x00,0x20,0x15, ++0x00,0x00,0x00,0x00, ++0x0D,0x00,0x07,0x00, ++0x08,0x00,0x60,0x10, ++0x00,0x00,0x00,0x00, ++0x21,0x28,0xAC,0x00, ++0x2B,0x10,0xAC,0x00, ++0x04,0x00,0x40,0x14, ++0x2B,0x10,0xAB,0x00, ++0x00,0x00,0x42,0x38, ++0x21,0x18,0xAC,0x00, ++0x0B,0x28,0x62,0x00, ++0x23,0x28,0xAB,0x00, ++0x1B,0x00,0xA9,0x00, ++0x02,0x00,0x20,0x15, ++0x00,0x00,0x00,0x00, ++0x0D,0x00,0x07,0x00, ++0xFF,0xFF,0xE4,0x31, ++0x12,0x18,0x00,0x00, ++0x10,0x40,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x18,0x00,0x6D,0x00, ++0x00,0x14,0x08,0x00, ++0x12,0x58,0x00,0x00, ++0x25,0x40,0x44,0x00, ++0x2B,0x18,0x0B,0x01, ++0x1B,0x00,0xA9,0x00, ++0x02,0x00,0x20,0x15, ++0x00,0x00,0x00,0x00, ++0x0D,0x00,0x07,0x00, ++0x08,0x00,0x60,0x10, ++0x00,0x00,0x00,0x00, ++0x21,0x40,0x0C,0x01, ++0x2B,0x10,0x0C,0x01, ++0x04,0x00,0x40,0x14, ++0x2B,0x10,0x0B,0x01, ++0x21,0x18,0x0C,0x01, ++0x00,0x00,0x42,0x38, ++0x0B,0x40,0x62,0x00, ++0xAB,0xFF,0x40,0x12, ++0x23,0x78,0x0B,0x01, ++0x06,0xC0,0xCF,0x00, ++0x21,0xC8,0x00,0x00, ++0x00,0x00,0x58,0xAE, ++0x4C,0x62,0x00,0x08, ++0x04,0x00,0x59,0xAE, ++0x1B,0x00,0x47,0x00, ++0x02,0x00,0xE0,0x14, ++0x00,0x00,0x00,0x00, ++0x0D,0x00,0x07,0x00, ++0xFF,0xFF,0x02,0x34, ++0x12,0x60,0x00,0x00, ++0x2B,0x10,0x4C,0x00, ++0xAB,0xFF,0x40,0x10, ++0x00,0x01,0x83,0x2D, ++0xFF,0x00,0x02,0x3C, ++0x10,0x00,0x03,0x24, ++0xFF,0xFF,0x42,0x34, ++0x2B,0x10,0x4C,0x00, ++0x18,0x00,0x04,0x24, ++0x21,0x28,0x60,0x00, ++0x0B,0x28,0x82,0x00, ++0x02,0x80,0x03,0x3C, ++0x06,0x10,0xAC,0x00, ++0xB4,0xF0,0x63,0x24, ++0x21,0x10,0x43,0x00, ++0x00,0x00,0x44,0x90, ++0x20,0x00,0x02,0x24, ++0x21,0x20,0x85,0x00, ++0x23,0x30,0x44,0x00, ++0xA7,0xFF,0xC0,0x10, ++0x00,0x00,0x00,0x00, ++0x23,0x38,0x46,0x00, ++0x04,0x60,0xCC,0x00, ++0x06,0x58,0xEA,0x00, ++0x02,0x4C,0x0C,0x00, ++0x1B,0x00,0x69,0x01, ++0x02,0x00,0x20,0x15, ++0x00,0x00,0x00,0x00, ++0x0D,0x00,0x07,0x00, ++0xFF,0xFF,0x8D,0x31, ++0x06,0x18,0xEF,0x00, ++0x04,0x10,0xCA,0x00, ++0x25,0x50,0x43,0x00, ++0x02,0x24,0x0A,0x00, ++0x12,0x28,0x00,0x00, ++0x10,0x40,0x00,0x00, ++0x00,0x14,0x08,0x00, ++0x25,0x40,0x44,0x00, ++0x18,0x00,0xAD,0x00, ++0x12,0x28,0x00,0x00, ++0x2B,0x18,0x05,0x01, ++0x00,0x00,0x00,0x00, ++0x1B,0x00,0x69,0x01, ++0x02,0x00,0x20,0x15, ++0x00,0x00,0x00,0x00, ++0x0D,0x00,0x07,0x00, ++0x05,0x00,0x60,0x10, ++0x04,0x78,0xCF,0x00, ++0x21,0x40,0x0C,0x01, ++0x2B,0x10,0x0C,0x01, ++0x93,0x00,0x40,0x10, ++0x2B,0x10,0x05,0x01, ++0x23,0x40,0x05,0x01, ++0x1B,0x00,0x09,0x01, ++0x02,0x00,0x20,0x15, ++0x00,0x00,0x00,0x00, ++0x0D,0x00,0x07,0x00, ++0xFF,0xFF,0x44,0x31, ++0x12,0x18,0x00,0x00, ++0x10,0x58,0x00,0x00, ++0x00,0x14,0x0B,0x00, ++0x25,0x58,0x44,0x00, ++0x18,0x00,0x6D,0x00, ++0x12,0x28,0x00,0x00, ++0x2B,0x18,0x65,0x01, ++0x00,0x00,0x00,0x00, ++0x1B,0x00,0x09,0x01, ++0x02,0x00,0x20,0x15, ++0x00,0x00,0x00,0x00, ++0x0D,0x00,0x07,0x00, ++0x77,0xFF,0x60,0x10, ++0x23,0x50,0x65,0x01, ++0x21,0x58,0x6C,0x01, ++0x2B,0x10,0x6C,0x01, ++0x04,0x00,0x40,0x14, ++0x2B,0x10,0x65,0x01, ++0x00,0x00,0x42,0x38, ++0x21,0x18,0x6C,0x01, ++0x0B,0x58,0x62,0x00, ++0x6A,0x62,0x00,0x08, ++0x23,0x50,0x65,0x01, ++0x08,0x00,0x02,0x24, ++0x21,0x28,0x00,0x00, ++0x0A,0x28,0x43,0x00, ++0x02,0x80,0x03,0x3C, ++0x06,0x10,0xA8,0x00, ++0xB4,0xF0,0x63,0x24, ++0x21,0x10,0x43,0x00, ++0x00,0x00,0x44,0x90, ++0x20,0x00,0x02,0x24, ++0x21,0x20,0x85,0x00, ++0x23,0x30,0x44,0x00, ++0x34,0xFF,0xC0,0x10, ++0x23,0x38,0x46,0x00, ++0x06,0x10,0xEC,0x00, ++0x04,0x18,0xC8,0x00, ++0x25,0x40,0x62,0x00, ++0x06,0x58,0xEA,0x00, ++0x02,0x6C,0x08,0x00, ++0x1B,0x00,0x6D,0x01, ++0x02,0x00,0xA0,0x15, ++0x00,0x00,0x00,0x00, ++0x0D,0x00,0x07,0x00, ++0xFF,0xFF,0x11,0x31, ++0x06,0x10,0xEF,0x00, ++0x04,0x18,0xCA,0x00, ++0x25,0x50,0x62,0x00, ++0x02,0x24,0x0A,0x00, ++0x04,0x60,0xCC,0x00, ++0x12,0x80,0x00,0x00, ++0x10,0x48,0x00,0x00, ++0x00,0x14,0x09,0x00, ++0x25,0x48,0x44,0x00, ++0x12,0x28,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x18,0x00,0x11,0x02, ++0x12,0x70,0x00,0x00, ++0x2B,0x18,0x2E,0x01, ++0x00,0x00,0x00,0x00, ++0x1B,0x00,0x6D,0x01, ++0x02,0x00,0xA0,0x15, ++0x00,0x00,0x00,0x00, ++0x0D,0x00,0x07,0x00, ++0x0A,0x00,0x60,0x10, ++0x04,0x78,0xCF,0x00, ++0x21,0x48,0x28,0x01, ++0x2B,0x10,0x28,0x01, ++0x06,0x00,0x40,0x14, ++0xFF,0xFF,0xB0,0x24, ++0x2B,0x10,0x2E,0x01, ++0x03,0x00,0x40,0x10, ++0x00,0x00,0x00,0x00, ++0xFF,0xFF,0x10,0x26, ++0x21,0x48,0x28,0x01, ++0x23,0x48,0x2E,0x01, ++0x1B,0x00,0x2D,0x01, ++0x02,0x00,0xA0,0x15, ++0x00,0x00,0x00,0x00, ++0x0D,0x00,0x07,0x00, ++0xFF,0xFF,0x44,0x31, ++0x12,0x28,0x00,0x00, ++0x10,0x58,0x00,0x00, ++0x00,0x14,0x0B,0x00, ++0x25,0x58,0x44,0x00, ++0x18,0x00,0xB1,0x00, ++0x12,0x70,0x00,0x00, ++0x2B,0x18,0x6E,0x01, ++0x00,0x00,0x00,0x00, ++0x1B,0x00,0x2D,0x01, ++0x02,0x00,0xA0,0x15, ++0x00,0x00,0x00,0x00, ++0x0D,0x00,0x07,0x00, ++0x0B,0x00,0x60,0x10, ++0x00,0x14,0x10,0x00, ++0x21,0x58,0x68,0x01, ++0x2B,0x10,0x68,0x01, ++0x06,0x00,0x40,0x14, ++0xFF,0xFF,0xA5,0x24, ++0x2B,0x10,0x6E,0x01, ++0x04,0x00,0x40,0x10, ++0x00,0x14,0x10,0x00, ++0xFF,0xFF,0xA5,0x24, ++0x21,0x58,0x68,0x01, ++0x00,0x14,0x10,0x00, ++0x25,0x10,0x45,0x00, ++0x23,0x58,0x6E,0x01, ++0x19,0x00,0x4C,0x00, ++0x10,0x28,0x00,0x00, ++0x2B,0x18,0x65,0x01, ++0x12,0x48,0x00,0x00, ++0x05,0x00,0x60,0x14, ++0x23,0x20,0x2C,0x01, ++0x07,0x00,0xAB,0x14, ++0x2B,0x10,0xE9,0x01, ++0x05,0x00,0x40,0x10, ++0x00,0x00,0x00,0x00, ++0x2B,0x10,0x24,0x01, ++0x23,0x18,0xA8,0x00, ++0x23,0x28,0x62,0x00, ++0x21,0x48,0x80,0x00, ++0xEA,0xFE,0x40,0x12, ++0x23,0x18,0xE9,0x01, ++0x23,0x20,0x65,0x01, ++0x2B,0x10,0xE3,0x01, ++0x23,0x50,0x82,0x00, ++0x04,0x28,0xEA,0x00, ++0x06,0x18,0xC3,0x00, ++0x25,0xC0,0xA3,0x00, ++0x06,0xC8,0xCA,0x00, ++0x00,0x00,0x58,0xAE, ++0x4C,0x62,0x00,0x08, ++0x04,0x00,0x59,0xAE, ++0x00,0x01,0xC3,0x2C, ++0x08,0x00,0x02,0x24, ++0x21,0x30,0x00,0x00, ++0xE6,0x61,0x00,0x08, ++0x0A,0x30,0x43,0x00, ++0x00,0x00,0x42,0x38, ++0x21,0x18,0x0C,0x01, ++0xE0,0x62,0x00,0x08, ++0x0B,0x40,0x62,0x00, ++0x25,0xB0,0x02,0x3C, ++0xFF,0x00,0x03,0x3C, ++0xEC,0x02,0x42,0x34, ++0x00,0x00,0x43,0xAC, ++0x08,0x00,0xE0,0x03, ++0x00,0x00,0x00,0x00, ++0x02,0x80,0x03,0x3C, ++0x25,0xB0,0x02,0x3C, ++0xF0,0x8D,0x63,0x24, ++0x18,0x03,0x42,0x34, ++0x00,0x00,0x43,0xAC, ++0x08,0x00,0xE0,0x03, ++0x00,0x00,0x00,0x00, ++0x7F,0x00,0x02,0x3C, ++0x0D,0xB8,0x44,0x34, ++0x80,0x04,0x03,0x3C, ++0x25,0x20,0x83,0x00, ++0x00,0x08,0x02,0x3C, ++0x25,0x20,0x82,0x00, ++0x00,0x30,0x03,0x3C, ++0x02,0x80,0x02,0x3C, ++0x30,0x1F,0x42,0x24, ++0x25,0x20,0x83,0x00, ++0x41,0xB0,0x03,0x3C, ++0x00,0x00,0x64,0xAC, ++0xD8,0x1B,0x44,0xAC, ++0xD0,0x1B,0x44,0xAC, ++0x08,0x00,0x63,0x34, ++0x86,0x00,0x04,0x24, ++0x00,0x00,0x64,0xA4, ++0xDC,0x1B,0x44,0xA4, ++0xD4,0x1B,0x40,0xAC, ++0xDE,0x1B,0x40,0xA4, ++0x08,0x00,0xE0,0x03, ++0xE0,0x1B,0x44,0xA4, ++0x99,0x63,0x00,0x08, ++0x00,0x00,0x00,0x00, ++0x42,0xB0,0x03,0x3C, ++0x01,0x00,0x63,0x34, ++0x02,0x00,0x02,0x24, ++0xE8,0xFF,0xBD,0x27, ++0x00,0x00,0x62,0xA0, ++0x10,0x00,0xBF,0xAF, ++0xDF,0x2F,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x21,0x20,0x00,0x00, ++0x01,0x00,0x05,0x24, ++0x8C,0x23,0x00,0x0C, ++0x00,0x50,0x06,0x24, ++0x1F,0x00,0x06,0x3C, ++0x10,0x00,0xBF,0x8F, ++0x00,0x40,0xC6,0x34, ++0x03,0x00,0x04,0x24, ++0x01,0x00,0x05,0x24, ++0x8C,0x23,0x00,0x08, ++0x18,0x00,0xBD,0x27, ++0x25,0xB0,0x03,0x3C, ++0x02,0x80,0x02,0x3C, ++0xC8,0xFF,0xBD,0x27, ++0x18,0x03,0x64,0x34, ++0xB8,0x8E,0x42,0x24, ++0x00,0x00,0x82,0xAC, ++0x30,0x00,0xBE,0xAF, ++0x2C,0x00,0xB7,0xAF, ++0x28,0x00,0xB6,0xAF, ++0x24,0x00,0xB5,0xAF, ++0x20,0x00,0xB4,0xAF, ++0x1C,0x00,0xB3,0xAF, ++0x18,0x00,0xB2,0xAF, ++0x14,0x00,0xB1,0xAF, ++0x10,0x00,0xB0,0xAF, ++0x34,0x00,0xBF,0xAF, ++0xB6,0x00,0x63,0x34, ++0x00,0x00,0x62,0x90, ++0x02,0x80,0x03,0x3C, ++0x30,0x1F,0x70,0x24, ++0xAB,0x1B,0x02,0xA2, ++0x28,0x6B,0x00,0x0C, ++0x7A,0x36,0x00,0xA2, ++0x48,0x01,0x03,0x24, ++0x84,0x36,0x03,0xAE, ++0x80,0x36,0x03,0xAE, ++0xFD,0xFF,0x02,0x3C, ++0xFB,0xFF,0x03,0x3C, ++0x21,0x98,0x00,0x02, ++0x21,0xA0,0x00,0x02, ++0xFF,0xFF,0x55,0x34, ++0xFF,0xFF,0x76,0x34, ++0x21,0x88,0x00,0x00, ++0x02,0x80,0x1E,0x3C, ++0x02,0x80,0x17,0x3C, ++0x21,0x90,0x00,0x02, ++0x80,0x10,0x11,0x00, ++0x21,0x10,0x51,0x00, ++0xC0,0x10,0x02,0x00, ++0x21,0x10,0x53,0x00, ++0xE8,0x1D,0x42,0x24, ++0x07,0x00,0x03,0x24, ++0xFF,0xFF,0x63,0x24, ++0x00,0x00,0x40,0xA4, ++0xFD,0xFF,0x61,0x04, ++0x02,0x00,0x42,0x24, ++0xC0,0x80,0x11,0x00, ++0x18,0x42,0xC4,0x27, ++0x21,0x20,0x04,0x02, ++0x21,0x28,0x00,0x00, ++0x02,0x00,0x06,0x24, ++0xF8,0x1D,0x40,0xA6, ++0x08,0x52,0x00,0x0C, ++0xFA,0x1D,0x40,0xA2, ++0x21,0x20,0x13,0x02, ++0xE8,0x22,0x83,0x8C, ++0xEA,0x5D,0xE7,0x92, ++0xBF,0xFF,0x02,0x24, ++0x24,0x28,0x62,0x00, ++0x01,0x00,0x02,0x24, ++0x63,0x00,0xE2,0x10, ++0x80,0x07,0xA6,0x34, ++0xFF,0xF7,0x03,0x24, ++0x24,0x10,0xC3,0x00, ++0xFF,0xEF,0x03,0x24, ++0x24,0x10,0x43,0x00, ++0xE8,0x22,0x82,0xAC, ++0x21,0x30,0x14,0x02, ++0xE8,0x22,0xC4,0x8C, ++0xE7,0xFF,0x02,0x3C, ++0xFF,0xFF,0x42,0x34, ++0x24,0x20,0x95,0x00, ++0x24,0x20,0x96,0x00, ++0xFF,0xFD,0x03,0x3C, ++0x24,0x20,0x82,0x00, ++0xFF,0xFF,0x63,0x34, ++0xFF,0xFB,0x02,0x3C, ++0x24,0x20,0x83,0x00, ++0xEC,0x22,0xC5,0x8C, ++0xFF,0xFF,0x42,0x34, ++0xFF,0xE7,0x03,0x3C, ++0x24,0x20,0x82,0x00, ++0xFF,0xFF,0x63,0x34, ++0xFF,0xFF,0x02,0x3C, ++0x24,0x20,0x83,0x00, ++0xFF,0x7F,0x42,0x34, ++0xC0,0xFF,0x03,0x24, ++0x24,0x28,0xA2,0x00, ++0x24,0x20,0x83,0x00, ++0x1F,0x00,0x02,0x3C, ++0x01,0x00,0x31,0x26, ++0x25,0x28,0xA2,0x00, ++0x08,0x00,0x84,0x34, ++0x20,0x00,0x22,0x2A, ++0xE8,0x22,0xC4,0xAC, ++0xEC,0x22,0xC5,0xAC, ++0xC3,0xFF,0x40,0x14, ++0x28,0x00,0x52,0x26, ++0x25,0xB0,0x02,0x3C, ++0x10,0x00,0x03,0x24, ++0xB0,0x03,0x42,0x34, ++0x02,0x80,0x04,0x3C, ++0x00,0x00,0x43,0xAC, ++0x58,0x22,0x84,0x24, ++0x21,0x28,0x00,0x00, ++0x08,0x52,0x00,0x0C, ++0x20,0x00,0x06,0x24, ++0x02,0x80,0x02,0x3C, ++0xE9,0x5D,0x43,0x90, ++0x00,0x00,0x00,0x00, ++0x3A,0x00,0x60,0x10, ++0x02,0x80,0x02,0x3C, ++0x30,0x1F,0x50,0x24, ++0x24,0x03,0x00,0xA2, ++0x38,0x70,0x00,0x0C, ++0x25,0x03,0x00,0xA2, ++0x02,0x80,0x09,0x3C, ++0x64,0x57,0x22,0x25, ++0x02,0x80,0x0A,0x3C, ++0x02,0x80,0x0B,0x3C, ++0x02,0x80,0x0C,0x3C, ++0x02,0x80,0x0D,0x3C, ++0x02,0x80,0x0E,0x3C, ++0x02,0x80,0x0F,0x3C, ++0x04,0x00,0x42,0xAC, ++0x64,0x57,0x22,0xAD, ++0x6C,0x57,0x43,0x25, ++0x74,0x57,0x64,0x25, ++0x7C,0x57,0x85,0x25, ++0x84,0x57,0xA6,0x25, ++0x8C,0x57,0xC7,0x25, ++0x94,0x57,0xE8,0x25, ++0x09,0x00,0x02,0x24, ++0x04,0x00,0x63,0xAC, ++0x6C,0x57,0x43,0xAD, ++0x04,0x00,0x84,0xAC, ++0x74,0x57,0x64,0xAD, ++0x04,0x00,0xA5,0xAC, ++0x7C,0x57,0x85,0xAD, ++0x04,0x00,0xC6,0xAC, ++0x84,0x57,0xA6,0xAD, ++0x04,0x00,0xE7,0xAC, ++0x8C,0x57,0xC7,0xAD, ++0x94,0x57,0xE8,0xAD, ++0x04,0x00,0x08,0xAD, ++0x34,0x00,0xBF,0x8F, ++0x0C,0x3E,0x02,0xA2, ++0x32,0x3B,0x00,0xA6, ++0x8E,0x3E,0x00,0xA2, ++0x30,0x00,0xBE,0x8F, ++0x2C,0x00,0xB7,0x8F, ++0x28,0x00,0xB6,0x8F, ++0x24,0x00,0xB5,0x8F, ++0x20,0x00,0xB4,0x8F, ++0x1C,0x00,0xB3,0x8F, ++0x18,0x00,0xB2,0x8F, ++0x14,0x00,0xB1,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x08,0x00,0xE0,0x03, ++0x38,0x00,0xBD,0x27, ++0x02,0x80,0x02,0x3C, ++0xEB,0x5D,0x43,0x90, ++0x00,0x00,0x00,0x00, ++0x9C,0xFF,0x67,0x14, ++0x80,0x0F,0xA2,0x34, ++0xFF,0xF7,0x03,0x24, ++0x24,0x10,0xC3,0x00, ++0xF0,0x63,0x00,0x08, ++0x00,0x10,0x42,0x34, ++0xFA,0x6B,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x50,0x6E,0x00,0x0C, ++0x30,0x38,0x80,0xAE, ++0x6E,0x6F,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x02,0x80,0x03,0x3C, ++0xDE,0x5D,0x64,0x90, ++0x92,0x00,0x02,0x24, ++0x03,0x00,0x82,0x10, ++0x00,0x00,0x00,0x00, ++0xCA,0x6F,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0xB0,0x6F,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x6A,0x6E,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x01,0x00,0x03,0x24, ++0x8A,0x36,0x83,0xA6, ++0x1E,0x70,0x00,0x0C, ++0x88,0x36,0x80,0xA6, ++0x1E,0x64,0x00,0x08, ++0x02,0x80,0x02,0x3C, ++0x02,0x80,0x03,0x3C, ++0x25,0xB0,0x02,0x3C, ++0xC8,0xFF,0xBD,0x27, ++0xB8,0x91,0x63,0x24, ++0x18,0x03,0x42,0x34, ++0x18,0x00,0xB0,0xAF, ++0x34,0x00,0xBF,0xAF, ++0x30,0x00,0xB6,0xAF, ++0x2C,0x00,0xB5,0xAF, ++0x28,0x00,0xB4,0xAF, ++0x24,0x00,0xB3,0xAF, ++0x20,0x00,0xB2,0xAF, ++0x1C,0x00,0xB1,0xAF, ++0x00,0x00,0x43,0xAC, ++0x21,0x80,0x00,0x00, ++0x01,0x00,0x02,0x26, ++0xFF,0xFF,0x50,0x30, ++0x64,0x00,0x03,0x2E, ++0xFD,0xFF,0x60,0x14, ++0x01,0x00,0x02,0x26, ++0x02,0x80,0x03,0x3C, ++0xDB,0x5D,0x68,0x90, ++0x02,0x80,0x02,0x3C, ++0x02,0x80,0x03,0x3C, ++0xD8,0x5D,0x4B,0x94, ++0xF3,0x5D,0x6A,0x90, ++0x02,0x80,0x02,0x3C, ++0x02,0x80,0x03,0x3C, ++0x02,0x80,0x14,0x3C, ++0xFA,0x5D,0x67,0x90, ++0xE8,0x5D,0x49,0x90, ++0xDA,0x5D,0x83,0x92, ++0x02,0x80,0x0C,0x3C, ++0x02,0x80,0x02,0x3C, ++0xF5,0x5D,0x46,0x90, ++0xF8,0x5D,0x85,0x91, ++0x25,0xB0,0x04,0x3C, ++0xB0,0x03,0x82,0x34, ++0x00,0x00,0x4B,0xAC, ++0x00,0x00,0x48,0xAC, ++0x00,0x00,0x49,0xAC, ++0x00,0x00,0x43,0xAC, ++0x02,0x80,0x03,0x3C, ++0x00,0x00,0x4A,0xAC, ++0x0A,0x00,0x88,0x34, ++0x00,0x00,0x46,0xAC, ++0x00,0x00,0x45,0xAC, ++0x00,0x00,0x47,0xAC, ++0x1A,0x5E,0x60,0xA4, ++0x00,0x00,0x06,0x91, ++0x02,0x80,0x02,0x3C, ++0x0B,0x00,0x04,0x24, ++0x02,0x80,0x16,0x3C, ++0xE5,0x5D,0x44,0xA0, ++0x02,0x80,0x02,0x3C, ++0x30,0x1F,0xC5,0x26, ++0x00,0x78,0x03,0x24, ++0x08,0x5E,0x40,0xA0, ++0xF0,0xFF,0x02,0x24, ++0x01,0x00,0x07,0x24, ++0x02,0x80,0x15,0x3C, ++0xAC,0x1B,0xA3,0xA4, ++0xAA,0x1B,0xA2,0xA0, ++0xFF,0x07,0x03,0x24, ++0xFF,0xFF,0x02,0x24, ++0x20,0x00,0xC6,0x30, ++0xF8,0x5D,0x87,0xA1, ++0xA8,0x1B,0xA7,0xA0, ++0xAE,0x1B,0xA3,0xA4, ++0x48,0xF3,0xA2,0xA2, ++0xB1,0x00,0xC0,0x10, ++0xB0,0x1B,0xA0,0xA4, ++0x00,0x00,0x02,0x91, ++0x00,0x00,0x00,0x00, ++0x10,0x00,0x42,0x30, ++0xFB,0x00,0x40,0x14, ++0x02,0x80,0x13,0x3C, ++0x21,0x80,0x00,0x00, ++0x21,0x88,0x00,0x00, ++0xB8,0xF1,0x72,0x26, ++0xFF,0x00,0x24,0x32, ++0x61,0x57,0x00,0x0C, ++0x21,0x28,0x12,0x02, ++0x08,0x00,0x03,0x26, ++0xFF,0xFF,0x70,0x30, ++0x01,0x00,0x22,0x26, ++0x80,0x00,0x03,0x2E, ++0xF8,0xFF,0x60,0x14, ++0xFF,0xFF,0x51,0x30, ++0xDA,0x5D,0x83,0x92, ++0x00,0x00,0x00,0x00, ++0x02,0x00,0x62,0x30, ++0xC1,0x00,0x40,0x14, ++0x04,0x00,0x62,0x30, ++0x9A,0x00,0x40,0x10, ++0x25,0xB0,0x03,0x3C, ++0x25,0xB0,0x04,0x3C, ++0x02,0x80,0x05,0x3C, ++0x06,0x00,0x06,0x24, ++0x50,0x00,0x84,0x34, ++0x10,0x52,0x00,0x0C, ++0x07,0xF2,0xA5,0x24, ++0xB8,0xF1,0x63,0x26, ++0x7B,0x00,0x66,0x90, ++0x00,0x00,0x00,0x00, ++0x02,0x00,0xC2,0x2C, ++0x04,0x00,0x40,0x14, ++0x02,0x00,0x0B,0x24, ++0x79,0x00,0x62,0x90, ++0x00,0x00,0x00,0x00, ++0x03,0x00,0x4B,0x30, ++0x04,0x00,0xC2,0x2C, ++0xDC,0x00,0x40,0x10, ++0xB8,0xF1,0x62,0x26, ++0x02,0x80,0x02,0x3C, ++0x4A,0xF3,0x40,0xA0, ++0x02,0x80,0x02,0x3C, ++0xE7,0x5D,0x43,0x90, ++0x01,0x00,0x02,0x24, ++0x02,0x00,0x62,0x10, ++0xFC,0xFF,0x08,0x24, ++0x21,0x40,0x00,0x00, ++0x02,0x80,0x02,0x3C, ++0x02,0x80,0x03,0x3C, ++0xB8,0xF1,0x4A,0x24, ++0x30,0x1F,0x69,0x24, ++0x21,0x60,0x00,0x00, ++0x21,0x80,0x00,0x00, ++0x01,0x00,0x02,0x26, ++0x21,0x30,0x30,0x01, ++0x03,0x00,0x03,0x2E, ++0x08,0x00,0x04,0x2E, ++0xFF,0xFF,0x50,0x30, ++0x0E,0x00,0x07,0x2E, ++0x04,0x00,0x60,0x14, ++0x21,0x88,0x00,0x00, ++0x01,0x00,0x11,0x24, ++0x02,0x00,0x02,0x24, ++0x0A,0x88,0x44,0x00, ++0x21,0x10,0x51,0x01, ++0x61,0x00,0x43,0x90, ++0x55,0x00,0x44,0x90, ++0x5B,0x00,0x45,0x90, ++0x21,0x18,0x03,0x01, ++0x21,0x20,0x04,0x01, ++0x21,0x28,0x05,0x01, ++0x9C,0x1D,0xC3,0xA0, ++0x64,0x1D,0xC4,0xA0, ++0xEB,0xFF,0xE0,0x14, ++0x80,0x1D,0xC5,0xA0, ++0x01,0x00,0x8C,0x25, ++0x02,0x00,0x82,0x2D, ++0x0E,0x00,0x29,0x25, ++0xE5,0xFF,0x40,0x14, ++0x03,0x00,0x4A,0x25, ++0x02,0x80,0x02,0x3C, ++0x02,0x80,0x03,0x3C, ++0x30,0x1F,0x47,0x24, ++0xB8,0xF1,0x66,0x24, ++0x21,0x80,0x00,0x00, ++0x03,0x00,0x02,0x2E, ++0x21,0x20,0x07,0x02, ++0xB9,0x00,0x40,0x10, ++0x08,0x00,0x03,0x2E, ++0x71,0x00,0xC3,0x90, ++0x6E,0x00,0xC2,0x90, ++0x00,0x00,0x00,0x00, ++0xC6,0x1D,0x82,0xA0, ++0xB8,0x1D,0x83,0xA0, ++0x01,0x00,0x02,0x26, ++0xFF,0xFF,0x50,0x30, ++0x0E,0x00,0x03,0x2E, ++0xF4,0xFF,0x60,0x14, ++0x03,0x00,0x02,0x2E, ++0x03,0x00,0x02,0x24, ++0x2A,0x00,0x62,0x15, ++0x02,0x80,0x02,0x3C, ++0x02,0x80,0x03,0x3C, ++0xB8,0xF1,0x4E,0x24, ++0x34,0xD9,0x6F,0x24, ++0x21,0x60,0x00,0x00, ++0x21,0x68,0x00,0x00, ++0x21,0x10,0xAE,0x01, ++0x74,0x00,0x43,0x90, ++0x21,0x80,0x00,0x00, ++0x0F,0x00,0x6A,0x30, ++0x02,0x49,0x03,0x00, ++0x21,0x10,0xB0,0x01, ++0x00,0x11,0x02,0x00, ++0x21,0x58,0x4F,0x00, ++0x21,0x38,0x00,0x00, ++0x21,0x40,0x67,0x01, ++0x00,0x00,0x03,0x91, ++0x00,0x31,0x09,0x00, ++0x01,0x00,0xE7,0x24, ++0x02,0x11,0x03,0x00, ++0x00,0x21,0x02,0x00, ++0x0F,0x00,0x63,0x30, ++0x2B,0x10,0x49,0x00, ++0x0A,0x20,0xC2,0x00, ++0x2B,0x28,0x6A,0x00, ++0x00,0x00,0xA5,0x38, ++0x25,0x18,0x83,0x00, ++0xFF,0xFF,0xE7,0x30, ++0x25,0x20,0x8A,0x00, ++0x0A,0x18,0x85,0x00, ++0x10,0x00,0xE2,0x2C, ++0xEF,0xFF,0x40,0x14, ++0x00,0x00,0x03,0xA1, ++0x01,0x00,0x02,0x26, ++0xFF,0xFF,0x50,0x30, ++0x03,0x00,0x03,0x2E, ++0xE7,0xFF,0x60,0x14, ++0x21,0x10,0xB0,0x01, ++0x01,0x00,0x8C,0x25, ++0x02,0x00,0x82,0x2D, ++0xDD,0xFF,0x40,0x14, ++0x03,0x00,0xAD,0x25, ++0xE6,0x56,0x00,0x0C, ++0x01,0x00,0x04,0x24, ++0x48,0xF3,0xA5,0x26, ++0x91,0x56,0x00,0x0C, ++0xFA,0x01,0x04,0x24, ++0xE6,0x56,0x00,0x0C, ++0x21,0x20,0x00,0x00, ++0x02,0x80,0x04,0x3C, ++0x25,0xB0,0x05,0x3C, ++0x18,0x3B,0x84,0x24, ++0x50,0x00,0xA5,0x34, ++0x10,0x52,0x00,0x0C, ++0x06,0x00,0x06,0x24, ++0x30,0x1F,0xC5,0x26, ++0x01,0x00,0x02,0x24, ++0x06,0x00,0x03,0x24, ++0x05,0x00,0x04,0x24, ++0x33,0x1C,0xA2,0xA0, ++0x8A,0x55,0x00,0x0C, ++0x30,0x3B,0xA3,0xA0, ++0x34,0x00,0xBF,0x8F, ++0x30,0x00,0xB6,0x8F, ++0x2C,0x00,0xB5,0x8F, ++0x28,0x00,0xB4,0x8F, ++0x24,0x00,0xB3,0x8F, ++0x20,0x00,0xB2,0x8F, ++0x1C,0x00,0xB1,0x8F, ++0x18,0x00,0xB0,0x8F, ++0x08,0x00,0xE0,0x03, ++0x38,0x00,0xBD,0x27, ++0x25,0xB0,0x03,0x3C, ++0x4C,0x87,0x02,0x3C, ++0x54,0x00,0x65,0x34, ++0x00,0xE0,0x42,0x34, ++0x50,0x00,0x63,0x34, ++0x00,0x00,0x62,0xAC, ++0x12,0x01,0x04,0x24, ++0x02,0x80,0x02,0x3C, ++0x00,0x00,0xA4,0xAC, ++0x30,0x1F,0x46,0x24, ++0x21,0x60,0x00,0x00, ++0x10,0x00,0x05,0x24, ++0x21,0x80,0x00,0x00, ++0x01,0x00,0x02,0x26, ++0x21,0x18,0xD0,0x00, ++0xFF,0xFF,0x50,0x30, ++0x0E,0x00,0x04,0x2E, ++0x80,0x1D,0x65,0xA0, ++0x64,0x1D,0x65,0xA0, ++0xF9,0xFF,0x80,0x14, ++0x9C,0x1D,0x65,0xA0, ++0x01,0x00,0x8C,0x25, ++0x02,0x00,0x82,0x2D, ++0xF4,0xFF,0x40,0x14, ++0x0E,0x00,0xC6,0x24, ++0x02,0x80,0x02,0x3C, ++0x30,0x1F,0x46,0x24, ++0x21,0x80,0x00,0x00, ++0x04,0x00,0x05,0x24, ++0x01,0x00,0x02,0x26, ++0x21,0x18,0x06,0x02, ++0xFF,0xFF,0x50,0x30, ++0x0E,0x00,0x04,0x2E, ++0xC6,0x1D,0x60,0xA0, ++0xFA,0xFF,0x80,0x14, ++0xB8,0x1D,0x65,0xA0, ++0x48,0x65,0x00,0x08, ++0x00,0x00,0x00,0x00, ++0x25,0xB0,0x04,0x3C, ++0x02,0x80,0x05,0x3C, ++0x50,0x00,0x84,0x34, ++0xCA,0xF1,0xA5,0x24, ++0x10,0x52,0x00,0x0C, ++0x06,0x00,0x06,0x24, ++0xB8,0xF1,0x62,0x92, ++0xB8,0xF1,0x64,0x26, ++0x01,0x00,0x85,0x90, ++0x21,0x18,0x40,0x00, ++0x10,0x00,0xA2,0xA3, ++0x29,0x00,0x02,0x24, ++0x11,0x00,0xA5,0xA3, ++0x50,0x00,0x86,0x90, ++0x3B,0x00,0x62,0x10, ++0xFF,0x00,0xA3,0x30, ++0xB8,0xF1,0x65,0x26, ++0x68,0x00,0xA2,0x90, ++0x02,0x80,0x03,0x3C, ++0x04,0x00,0xC4,0x2C, ++0x1F,0x00,0x42,0x30, ++0x24,0x00,0x80,0x14, ++0x49,0xF3,0x62,0xA0, ++0x7A,0x00,0xA2,0x90, ++0x79,0x00,0xA4,0x90, ++0x02,0x80,0x03,0x3C, ++0x04,0x00,0x42,0x30, ++0x83,0x10,0x02,0x00, ++0x03,0x00,0x8B,0x30, ++0x4A,0xF3,0x62,0xA0, ++0x06,0x00,0xC2,0x2C, ++0x37,0xFF,0x40,0x14, ++0x02,0x80,0x02,0x3C, ++0xB8,0xF1,0x63,0x26, ++0x69,0x00,0x62,0x90, ++0x00,0x00,0x00,0x00, ++0x01,0x00,0x42,0x30, ++0x31,0xFF,0x40,0x14, ++0x02,0x80,0x02,0x3C, ++0xE8,0x64,0x00,0x08, ++0x21,0x40,0x00,0x00, ++0x21,0x20,0x00,0x00, ++0x80,0x00,0x05,0x24, ++0x53,0x56,0x00,0x0C, ++0xB8,0xF1,0x66,0x26, ++0xC7,0x64,0x00,0x08, ++0x00,0x00,0x00,0x00, ++0x7D,0x00,0x43,0x90, ++0x69,0x00,0x44,0x90, ++0x02,0x80,0x02,0x3C, ++0x04,0x00,0x63,0x30, ++0x01,0x00,0x84,0x30, ++0x83,0x18,0x03,0x00, ++0x01,0x00,0x84,0x2C, ++0x1F,0xFF,0x80,0x10, ++0x4A,0xF3,0x43,0xA0, ++0xE8,0x64,0x00,0x08, ++0x21,0x40,0x00,0x00, ++0x02,0x80,0x02,0x3C, ++0x02,0x00,0x0B,0x24, ++0xAA,0x65,0x00,0x08, ++0x4A,0xF3,0x40,0xA0, ++0x21,0x28,0x07,0x02, ++0x06,0x00,0x60,0x10, ++0x21,0x20,0xA0,0x00, ++0x67,0x00,0xC3,0x90, ++0x6F,0x00,0xC2,0x90, ++0xB8,0x1D,0xA3,0xA0, ++0x17,0x65,0x00,0x08, ++0xC6,0x1D,0xA2,0xA0, ++0x72,0x00,0xC3,0x90, ++0x70,0x00,0xC2,0x90, ++0x16,0x65,0x00,0x08, ++0xC6,0x1D,0x82,0xA0, ++0x81,0x00,0x02,0x24, ++0xC4,0xFF,0x62,0x14, ++0x01,0x00,0x02,0x24, ++0x54,0x00,0x83,0x90, ++0x00,0x00,0x00,0x00, ++0x0A,0x00,0x62,0x10, ++0x02,0x00,0x02,0x24, ++0x04,0x00,0x62,0x10, ++0x11,0x00,0x03,0x24, ++0x02,0x80,0x02,0x3C, ++0x9C,0x65,0x00,0x08, ++0xDE,0x5D,0x43,0xA0, ++0x22,0x00,0x03,0x24, ++0x02,0x80,0x02,0x3C, ++0x9C,0x65,0x00,0x08, ++0xDE,0x5D,0x43,0xA0, ++0x12,0x00,0x03,0x24, ++0x02,0x80,0x02,0x3C, ++0x9C,0x65,0x00,0x08, ++0xDE,0x5D,0x43,0xA0, ++0xD8,0xFF,0xBD,0x27, ++0x18,0x00,0xB0,0xAF, ++0x02,0x80,0x02,0x3C, ++0x25,0xB0,0x10,0x3C, ++0x18,0x03,0x03,0x36, ++0xA8,0x97,0x42,0x24, ++0x00,0x00,0x62,0xAC, ++0x20,0x00,0xB2,0xAF, ++0x02,0x80,0x12,0x3C, ++0x24,0x00,0xBF,0xAF, ++0x6E,0x64,0x00,0x0C, ++0x1C,0x00,0xB1,0xAF, ++0x9C,0x66,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x36,0x69,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x1A,0x6A,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x7C,0x6C,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x82,0x69,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x30,0x1F,0x43,0x26, ++0x30,0x3B,0x64,0x90, ++0x0D,0x0C,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x76,0x63,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x64,0x40,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x44,0x00,0x03,0x36, ++0x00,0x00,0x62,0x94, ++0x00,0x00,0x00,0x00, ++0x40,0x00,0x42,0x34, ++0x00,0x00,0x62,0xA4, ++0xAE,0x63,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x7C,0x63,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x9B,0x63,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0xE6,0x69,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0xA3,0x69,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x00,0x80,0x04,0x3C, ++0x74,0x6A,0x84,0x24, ++0x03,0x6A,0x00,0x0C, ++0x01,0x00,0x05,0x24, ++0x00,0x80,0x04,0x3C, ++0x6C,0x72,0x84,0x24, ++0x03,0x6A,0x00,0x0C, ++0x02,0x00,0x05,0x24, ++0x00,0x80,0x04,0x3C, ++0x48,0x7B,0x84,0x24, ++0x03,0x6A,0x00,0x0C, ++0x04,0x00,0x05,0x24, ++0x7E,0x59,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x01,0x80,0x04,0x3C, ++0xB8,0x8E,0x84,0x24, ++0x03,0x6A,0x00,0x0C, ++0x03,0x00,0x05,0x24, ++0x02,0x80,0x03,0x3C, ++0xE8,0x5D,0x63,0x90, ++0x00,0x00,0x00,0x00, ++0x60,0x00,0x60,0x10, ++0x43,0x00,0x02,0x36, ++0x07,0x00,0x02,0x24, ++0x0C,0x00,0x62,0x10, ++0x03,0x00,0x02,0x24, ++0x25,0xB0,0x04,0x3C, ++0x43,0x00,0x85,0x34, ++0x10,0x02,0x86,0x34, ++0x10,0x00,0x03,0x24, ++0x00,0x00,0xA2,0xA0, ++0xD8,0x00,0x84,0x34, ++0x00,0x00,0xC3,0xA0, ++0x00,0x00,0x82,0x90, ++0x80,0xFF,0x03,0x24, ++0x25,0x10,0x43,0x00, ++0x00,0x00,0x82,0xA0, ++0xE0,0x6A,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x42,0xB0,0x03,0x3C, ++0x00,0x00,0x62,0x90, ++0x25,0xB0,0x10,0x3C, ++0x02,0x80,0x11,0x3C, ++0x01,0x00,0x42,0x34, ++0x00,0x00,0x62,0xA0, ++0x83,0x63,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x44,0x00,0x05,0x36, ++0x00,0x00,0xA2,0x94, ++0x02,0x80,0x03,0x3C, ++0x8C,0xC6,0x64,0x8C, ++0xC0,0x00,0x42,0x34, ++0x00,0x00,0xA2,0xA4, ++0x2F,0x55,0x00,0x0C, ++0x80,0x0C,0x10,0x36, ++0x02,0x80,0x02,0x3C, ++0x02,0x80,0x03,0x3C, ++0xDA,0x5D,0x45,0x90, ++0xDF,0x5D,0x66,0x90, ++0x02,0x80,0x04,0x3C, ++0x2F,0x55,0x00,0x0C, ++0x90,0xC6,0x84,0x24, ++0x02,0x80,0x02,0x3C, ++0x02,0x80,0x03,0x3C, ++0xDE,0x5D,0x45,0x90, ++0x48,0xF3,0x66,0x90, ++0x02,0x80,0x02,0x3C, ++0x02,0x80,0x03,0x3C, ++0xE7,0x5D,0x47,0x90, ++0x4A,0xF3,0x62,0x90, ++0x02,0x80,0x04,0x3C, ++0xA4,0xC6,0x84,0x24, ++0x2F,0x55,0x00,0x0C, ++0x10,0x00,0xA2,0xAF, ++0x02,0x80,0x02,0x3C, ++0x00,0x00,0x07,0x8E, ++0xE6,0x5D,0x46,0x90, ++0xE9,0x5D,0x25,0x92, ++0x02,0x80,0x04,0x3C, ++0x2F,0x55,0x00,0x0C, ++0xC0,0xC6,0x84,0x24, ++0x02,0x80,0x03,0x3C, ++0x02,0x80,0x02,0x3C, ++0xEB,0x5D,0x66,0x90, ++0xEA,0x5D,0x45,0x90, ++0x02,0x80,0x04,0x3C, ++0x30,0x1F,0x50,0x26, ++0x2F,0x55,0x00,0x0C, ++0xDC,0xC6,0x84,0x24, ++0xA0,0x3E,0x06,0x8E, ++0xA4,0x3E,0x05,0x8E, ++0x02,0x80,0x04,0x3C, ++0x2F,0x55,0x00,0x0C, ++0xF0,0xC6,0x84,0x24, ++0x02,0x80,0x02,0x3C, ++0x49,0xF3,0x45,0x90, ++0x02,0x80,0x04,0x3C, ++0x2F,0x55,0x00,0x0C, ++0x10,0xC7,0x84,0x24, ++0xE9,0x5D,0x23,0x92, ++0x10,0x27,0x02,0x24, ++0x02,0x80,0x04,0x3C, ++0x0B,0x10,0x03,0x00, ++0x40,0x39,0x02,0xAE, ++0x08,0x00,0x84,0x24, ++0x21,0x28,0x00,0x00, ++0x21,0x30,0x00,0x00, ++0x91,0x3C,0x00,0x0C, ++0x21,0x38,0x00,0x00, ++0x99,0x63,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x24,0x00,0xBF,0x8F, ++0x20,0x00,0xB2,0x8F, ++0x1C,0x00,0xB1,0x8F, ++0x18,0x00,0xB0,0x8F, ++0x01,0x00,0x02,0x24, ++0x08,0x00,0xE0,0x03, ++0x28,0x00,0xBD,0x27, ++0xD8,0x00,0x04,0x36, ++0x00,0x00,0x40,0xA0, ++0x38,0x66,0x00,0x08, ++0x00,0x00,0x00,0x00, ++0x21,0x20,0x00,0x00, ++0x20,0xB0,0x06,0x3C, ++0xFF,0xFF,0x05,0x34, ++0x21,0x18,0x86,0x00, ++0x04,0x00,0x84,0x24, ++0x2A,0x10,0xA4,0x00, ++0x00,0x00,0x60,0xAC, ++0xFB,0xFF,0x40,0x10, ++0x00,0x00,0x00,0x00, ++0x08,0x00,0xE0,0x03, ++0x00,0x00,0x00,0x00, ++0xB8,0xFF,0xBD,0x27, ++0x24,0x00,0xB1,0xAF, ++0x44,0x00,0xBF,0xAF, ++0x40,0x00,0xBE,0xAF, ++0x3C,0x00,0xB7,0xAF, ++0x38,0x00,0xB6,0xAF, ++0x34,0x00,0xB5,0xAF, ++0x30,0x00,0xB4,0xAF, ++0x2C,0x00,0xB3,0xAF, ++0x28,0x00,0xB2,0xAF, ++0x20,0x00,0xB0,0xAF, ++0x02,0x80,0x02,0x3C, ++0xDA,0x5D,0x42,0x90, ++0x25,0xB0,0x11,0x3C, ++0x58,0x00,0x25,0x36, ++0x10,0x00,0xA2,0xAF, ++0x4C,0x81,0x02,0x3C, ++0x00,0xE0,0x42,0x34, ++0x00,0x00,0xA2,0xAC, ++0xFF,0xFF,0x04,0x24, ++0x96,0x01,0x03,0x24, ++0x28,0x28,0x02,0x24, ++0x5C,0x00,0x26,0x36, ++0x60,0x00,0x27,0x36, ++0x64,0x00,0x28,0x36, ++0x8A,0x00,0x29,0x36, ++0x00,0x00,0xC3,0xAC, ++0x00,0x00,0xE4,0xAC, ++0x00,0x00,0x04,0xAD, ++0x00,0x00,0x22,0xA5, ++0x0E,0x0E,0x02,0x3C, ++0x09,0x00,0x03,0x24, ++0x0A,0x0A,0x42,0x34, ++0x89,0x00,0x2A,0x36, ++0x8C,0x00,0x2B,0x36, ++0x00,0x00,0x43,0xA1, ++0x90,0x00,0x2C,0x36, ++0x00,0x00,0x62,0xAD, ++0x13,0x00,0x03,0x24, ++0x30,0x00,0x02,0x24, ++0x91,0x00,0x2D,0x36, ++0x00,0x00,0x83,0xA1, ++0x92,0x00,0x2E,0x36, ++0x00,0x00,0xA2,0xA1, ++0x3A,0x01,0x03,0x24, ++0x21,0x00,0x02,0x24, ++0xB5,0x00,0x2F,0x36, ++0x00,0x00,0xC3,0xA5, ++0x00,0x00,0xE2,0xA1, ++0x10,0x00,0xA2,0x8F, ++0x12,0x00,0x03,0x24, ++0x89,0x01,0x43,0x10, ++0x07,0x07,0x02,0x3C, ++0x07,0x07,0x42,0x34, ++0xA0,0x00,0x24,0x36, ++0x00,0x00,0x82,0xAC, ++0xA4,0x00,0x25,0x36, ++0x00,0x07,0x03,0x24, ++0x00,0xC0,0x02,0x3C, ++0xA8,0x00,0x26,0x36, ++0x00,0x00,0xA3,0xAC, ++0x00,0xC4,0x42,0x34, ++0x00,0x00,0xC2,0xAC, ++0x02,0x80,0x03,0x3C, ++0x30,0x1F,0x62,0x24, ++0xAC,0x1B,0x45,0x94, ++0xAE,0x1B,0x46,0x94, ++0xAA,0x1B,0x42,0x90, ++0x02,0x80,0x03,0x3C, ++0x21,0xB0,0x07,0x3C, ++0x14,0x00,0xA2,0xA3, ++0xE9,0x5D,0x63,0x90, ++0x20,0xB0,0x02,0x3C, ++0xFF,0xFF,0x42,0x34, ++0x18,0x00,0xA3,0xAF, ++0x23,0xB0,0x03,0x3C, ++0xFF,0xFF,0x63,0x34, ++0x24,0xB0,0x08,0x3C, ++0xFF,0x1F,0x04,0x3C, ++0x25,0xB0,0x1E,0x3C, ++0xFF,0xFF,0x84,0x34, ++0x21,0x38,0xA7,0x00, ++0x21,0x40,0xC8,0x00, ++0x21,0x28,0xA2,0x00, ++0x21,0x30,0xC3,0x00, ++0x24,0x40,0x04,0x01, ++0x24,0x28,0xA4,0x00, ++0x24,0x38,0xE4,0x00, ++0x24,0x30,0xC4,0x00, ++0x35,0x00,0x02,0x24, ++0x20,0x00,0xC4,0x37, ++0x00,0x00,0x82,0xA0, ++0x22,0x00,0x03,0x24, ++0x09,0x00,0x02,0x24, ++0x03,0x05,0xC9,0x37, ++0x60,0x05,0xCA,0x37, ++0xAC,0x00,0xCB,0x37, ++0xF8,0x00,0xCC,0x37, ++0xB0,0x00,0xCD,0x37, ++0x08,0x01,0xCE,0x37, ++0xD8,0x00,0xCF,0x37, ++0x00,0x00,0x23,0xA1, ++0x00,0x00,0x42,0xA1, ++0x00,0x00,0x65,0xAD, ++0x00,0x00,0x87,0xAD, ++0x00,0x00,0xA6,0xAD, ++0x00,0x00,0xC8,0xAD, ++0x00,0x00,0xE0,0xA1, ++0x14,0x00,0xA3,0x93, ++0x25,0xB0,0x02,0x3C, ++0xB4,0x00,0x42,0x34, ++0x00,0x00,0x43,0xA0, ++0xB6,0x00,0xD1,0x37, ++0x04,0x00,0x02,0x24, ++0x25,0xB0,0x03,0x3C, ++0x00,0x00,0x22,0xA2, ++0xB9,0x00,0x63,0x34, ++0xFF,0xFF,0x02,0x24, ++0x00,0x00,0x62,0xA0, ++0x25,0xB0,0x03,0x3C, ++0x0F,0x00,0x02,0x24, ++0xBA,0x00,0x63,0x34, ++0x00,0x00,0x62,0xA4, ++0x16,0x01,0xD4,0x37, ++0x3F,0x3F,0x03,0x24, ++0x2F,0x00,0x02,0x3C, ++0x00,0x00,0x83,0xA6, ++0x17,0x32,0x42,0x34, ++0xFF,0xCF,0x03,0x24, ++0x18,0x01,0xD5,0x37, ++0x1A,0x01,0xD6,0x37, ++0xDC,0x00,0xD7,0x37, ++0xD0,0x01,0xD8,0x37, ++0x00,0x00,0xA0,0xA6, ++0x00,0x00,0xC0,0xA6, ++0x00,0x00,0xE3,0xAE, ++0x00,0x00,0x02,0xAF, ++0x5E,0x00,0x03,0x3C, ++0x25,0xB0,0x02,0x3C, ++0x17,0x43,0x63,0x34, ++0xD4,0x01,0x42,0x34, ++0x00,0x00,0x43,0xAC, ++0x10,0x00,0x02,0x3C, ++0x20,0x53,0x42,0x34, ++0xD8,0x01,0xDF,0x37, ++0x00,0x00,0xE2,0xAF, ++0x25,0xB0,0x02,0x3C, ++0x44,0xA4,0x03,0x34, ++0xDC,0x01,0x42,0x34, ++0x00,0x00,0x43,0xAC, ++0x25,0xB0,0x03,0x3C, ++0x1A,0x06,0x02,0x24, ++0xE0,0x01,0x63,0x34, ++0x00,0x00,0x62,0xA4, ++0xC2,0x00,0x02,0x3C, ++0x30,0x30,0x03,0x24, ++0x51,0x10,0x42,0x34, ++0xF4,0x01,0xD0,0x37, ++0xF8,0x01,0xD3,0x37, ++0x00,0x00,0x03,0xA6, ++0x00,0x02,0xD2,0x37, ++0x00,0x00,0x62,0xAE, ++0x26,0x00,0x03,0x24, ++0x03,0x02,0xD9,0x37, ++0x04,0x00,0x02,0x24, ++0x00,0x00,0x43,0xA6, ++0x00,0x00,0x22,0xA3, ++0x18,0x00,0xA3,0x8F, ++0x00,0x00,0x00,0x00, ++0xE5,0x00,0x60,0x14, ++0x36,0x02,0xC2,0x37, ++0x04,0x00,0x03,0x24, ++0x00,0x00,0x43,0xA0, ++0x02,0x80,0x0B,0x3C, ++0xDE,0x5D,0x66,0x91, ++0x25,0xB0,0x09,0x3C, ++0x80,0x00,0x02,0x24, ++0x34,0x02,0x24,0x35, ++0x00,0x00,0x82,0xA4, ++0x37,0x02,0x25,0x35, ++0x53,0x00,0x03,0x24, ++0x22,0x00,0x02,0x24, ++0x00,0x00,0xA3,0xA0, ++0xE6,0x00,0xC2,0x10, ++0x1B,0x1B,0x02,0x3C, ++0x13,0x13,0x02,0x3C, ++0x13,0x13,0x42,0x34, ++0x60,0x01,0x23,0x35, ++0x64,0x01,0x24,0x35, ++0x68,0x01,0x25,0x35, ++0x7C,0x01,0x2A,0x35, ++0x6C,0x01,0x26,0x35, ++0x70,0x01,0x27,0x35, ++0x74,0x01,0x28,0x35, ++0x78,0x01,0x29,0x35, ++0x00,0x00,0x62,0xAC, ++0x00,0x00,0x82,0xAC, ++0x00,0x00,0xA2,0xAC, ++0x00,0x00,0xC2,0xAC, ++0x00,0x00,0xE2,0xAC, ++0x00,0x00,0x02,0xAD, ++0x00,0x00,0x22,0xAD, ++0x00,0x00,0x42,0xAD, ++0xDE,0x5D,0x65,0x91, ++0x25,0xB0,0x0C,0x3C, ++0x01,0x00,0x03,0x3C, ++0x80,0x01,0x82,0x35, ++0x08,0x5F,0x63,0x34, ++0x22,0x00,0x04,0x24, ++0x00,0x00,0x43,0xAC, ++0xE5,0x00,0xA4,0x10, ++0x0F,0x1F,0x02,0x3C, ++0x92,0x00,0x02,0x24, ++0xE2,0x00,0xA2,0x10, ++0x0F,0x1F,0x02,0x3C, ++0x0F,0x10,0x02,0x3C, ++0x00,0xF0,0x4F,0x34, ++0xF7,0x01,0x91,0x35, ++0x15,0xF0,0x4D,0x34, ++0x77,0x00,0x0E,0x24, ++0x84,0x01,0x87,0x35, ++0x88,0x01,0x88,0x35, ++0x10,0xF0,0x44,0x34, ++0x8C,0x01,0x85,0x35, ++0x05,0xF0,0x42,0x34, ++0x00,0x00,0xED,0xAC, ++0x90,0x01,0x83,0x35, ++0x00,0x00,0x04,0xAD, ++0x94,0x01,0x86,0x35, ++0x00,0x00,0xA2,0xAC, ++0xF5,0x0F,0x02,0x24, ++0x00,0x00,0x6F,0xAC, ++0x98,0x01,0x89,0x35, ++0x00,0x00,0xC2,0xAC, ++0x9C,0x01,0x8A,0x35, ++0xA0,0x01,0x8B,0x35, ++0xF0,0x0F,0x03,0x24, ++0xF6,0x01,0x8C,0x35, ++0x0D,0x00,0x02,0x24, ++0x00,0x00,0x23,0xAD, ++0x00,0x00,0x42,0xAD, ++0x00,0x00,0x6D,0xAD, ++0x02,0x80,0x02,0x3C, ++0x00,0x00,0x8E,0xA1, ++0x00,0x00,0x2E,0xA2, ++0xFB,0x5D,0x42,0x90, ++0x25,0xB0,0x1F,0x3C, ++0xA7,0x01,0xE7,0x37, ++0x1C,0x00,0xA2,0xAF, ++0xFF,0xFF,0x02,0x24, ++0x00,0x00,0xE2,0xA0, ++0x05,0x06,0x03,0x3C, ++0x25,0xB0,0x02,0x3C, ++0x03,0x04,0x63,0x34, ++0x0C,0x00,0x04,0x24, ++0xFF,0xFF,0x05,0x24, ++0x01,0x02,0x06,0x3C, ++0xC2,0x01,0x42,0x34, ++0xA8,0x01,0xE8,0x37, ++0xAC,0x01,0xE9,0x37, ++0xB0,0x01,0xEA,0x37, ++0xB4,0x01,0xEB,0x37, ++0xB8,0x01,0xEC,0x37, ++0xBC,0x01,0xED,0x37, ++0xC0,0x01,0xEE,0x37, ++0xC1,0x01,0xEF,0x37, ++0x00,0x00,0x05,0xAD, ++0x00,0x00,0x25,0xAD, ++0x00,0x00,0x46,0xAD, ++0x00,0x00,0x63,0xAD, ++0x00,0x00,0x86,0xAD, ++0x00,0x00,0xA3,0xAD, ++0x00,0x00,0xC4,0xA1, ++0x25,0xB0,0x03,0x3C, ++0x00,0x00,0xE4,0xA1, ++0x00,0x00,0x44,0xA0, ++0x25,0xB0,0x02,0x3C, ++0x0D,0x00,0x17,0x24, ++0x0E,0x00,0x18,0x24, ++0xC4,0x01,0x63,0x34, ++0xC5,0x01,0x42,0x34, ++0xC3,0x01,0xF1,0x37, ++0x00,0x00,0x37,0xA2, ++0xC6,0x01,0xF4,0x37, ++0x00,0x00,0x77,0xA0, ++0xC7,0x01,0xF5,0x37, ++0x00,0x00,0x58,0xA0, ++0x0F,0x00,0x02,0x24, ++0x00,0x00,0x98,0xA2, ++0x00,0x00,0xA2,0xA2, ++0xD3,0x01,0x02,0x3C, ++0x46,0x00,0xF6,0x37, ++0x48,0x00,0xFE,0x37, ++0x0E,0xF0,0x42,0x34, ++0x00,0x00,0xC0,0xA6, ++0x00,0x00,0xC2,0xAF, ++0x1C,0x00,0xA3,0x8F, ++0x00,0x00,0x00,0x00, ++0x09,0x00,0x60,0x10, ++0x44,0x00,0xF7,0x37, ++0x00,0x00,0xE2,0x8E, ++0x00,0x02,0x03,0x3C, ++0x25,0x10,0x43,0x00, ++0x00,0x00,0xE2,0xAE, ++0x00,0x00,0xC3,0x8F, ++0x00,0x04,0x02,0x3C, ++0x25,0x18,0x62,0x00, ++0x00,0x00,0xC3,0xAF, ++0x4C,0x00,0xE2,0x37, ++0x00,0x00,0x40,0xA0, ++0x4D,0x00,0xE3,0x37, ++0xF1,0x02,0xE4,0x37, ++0x08,0x00,0x02,0x24, ++0x00,0x00,0x60,0xA0, ++0x40,0x00,0xE6,0x37, ++0x00,0x00,0x82,0xA0, ++0x64,0x03,0xE5,0x37, ++0xBC,0x00,0x03,0x24, ++0xFC,0x37,0x02,0x24, ++0x00,0x00,0xC3,0xA4, ++0x00,0x00,0xA0,0xA0, ++0x00,0x00,0xC2,0xA4, ++0x02,0x80,0x02,0x3C, ++0xD8,0x00,0xE9,0x37, ++0x30,0x1F,0x43,0x24, ++0x00,0x00,0x26,0x91, ++0xAA,0x1B,0x64,0x90, ++0x2A,0xB0,0x05,0x3C, ++0xA0,0xFF,0x02,0x24, ++0x26,0xB0,0x07,0x3C, ++0x25,0x30,0xC2,0x00, ++0x30,0x00,0xAD,0x34, ++0x34,0x00,0xA8,0x34, ++0x01,0x00,0x83,0x24, ++0x38,0x00,0xA5,0x34, ++0x20,0x20,0x02,0x24, ++0x00,0x00,0x26,0xA1, ++0x79,0x00,0xEA,0x34, ++0x00,0x00,0x03,0xA1, ++0x00,0x00,0xA2,0xA4, ++0x40,0x00,0x03,0x24, ++0x16,0x00,0x02,0x24, ++0x00,0x00,0xA3,0xA1, ++0x94,0x00,0xEB,0x37, ++0x00,0x00,0x42,0xA1, ++0x98,0x00,0xEC,0x37, ++0x64,0x00,0x03,0x24, ++0x22,0x00,0x02,0x24, ++0x00,0x00,0x63,0xA5, ++0x7C,0x00,0xF4,0x34, ++0x00,0x00,0x82,0xA5, ++0x7A,0x00,0xE7,0x34, ++0x04,0x00,0x03,0x24, ++0x20,0x0C,0x02,0x24, ++0x00,0x00,0xE3,0xA0, ++0x9C,0x00,0xEE,0x37, ++0x00,0x00,0x82,0xA6, ++0x9A,0x00,0xEF,0x37, ++0x0A,0x00,0x03,0x24, ++0xFF,0x03,0x02,0x24, ++0x00,0x00,0xC3,0xA1, ++0x00,0x00,0xE2,0xA5, ++0x25,0xB0,0x02,0x3C, ++0x02,0x00,0x03,0x24, ++0x96,0x00,0x42,0x34, ++0x00,0x00,0x43,0xA4, ++0x89,0x00,0xF5,0x37, ++0xB7,0x00,0xF1,0x37, ++0x20,0x00,0x02,0x24, ++0x09,0x00,0x03,0x24, ++0x00,0x00,0x22,0xA2, ++0x00,0x00,0xA3,0xA2, ++0x00,0x00,0xE2,0x96, ++0xFF,0xFD,0x03,0x24, ++0x04,0x02,0x05,0x24, ++0x24,0x10,0x43,0x00, ++0x00,0x00,0xE2,0xA6, ++0x00,0x00,0xE3,0x96, ++0x29,0xB0,0x02,0x3C, ++0x40,0x00,0x42,0x34, ++0x00,0x02,0x63,0x34, ++0x00,0x00,0xE3,0xA6, ++0xFF,0x00,0x84,0x30, ++0x00,0x00,0x45,0xA4, ++0x73,0x22,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x44,0x00,0xBF,0x8F, ++0x40,0x00,0xBE,0x8F, ++0x3C,0x00,0xB7,0x8F, ++0x38,0x00,0xB6,0x8F, ++0x34,0x00,0xB5,0x8F, ++0x30,0x00,0xB4,0x8F, ++0x2C,0x00,0xB3,0x8F, ++0x28,0x00,0xB2,0x8F, ++0x24,0x00,0xB1,0x8F, ++0x20,0x00,0xB0,0x8F, ++0x01,0x00,0x02,0x24, ++0x08,0x00,0xE0,0x03, ++0x48,0x00,0xBD,0x27, ++0xFF,0xFF,0x03,0x24, ++0x00,0x00,0x43,0xA0, ++0x02,0x80,0x0B,0x3C, ++0xDE,0x5D,0x66,0x91, ++0x25,0xB0,0x09,0x3C, ++0x80,0x00,0x02,0x24, ++0x34,0x02,0x24,0x35, ++0x00,0x00,0x82,0xA4, ++0x37,0x02,0x25,0x35, ++0x53,0x00,0x03,0x24, ++0x22,0x00,0x02,0x24, ++0x00,0x00,0xA3,0xA0, ++0x1E,0xFF,0xC2,0x14, ++0x13,0x13,0x02,0x3C, ++0x1B,0x1B,0x02,0x3C, ++0x1B,0x1B,0x42,0x34, ++0x60,0x01,0x23,0x35, ++0x64,0x01,0x24,0x35, ++0x68,0x01,0x25,0x35, ++0x7C,0x01,0x2A,0x35, ++0x6C,0x01,0x26,0x35, ++0x70,0x01,0x27,0x35, ++0x74,0x01,0x28,0x35, ++0x78,0x01,0x29,0x35, ++0x00,0x00,0x62,0xAC, ++0x00,0x00,0x82,0xAC, ++0x00,0x00,0xA2,0xAC, ++0x00,0x00,0xC2,0xAC, ++0x00,0x00,0xE2,0xAC, ++0x00,0x00,0x02,0xAD, ++0x00,0x00,0x22,0xAD, ++0x00,0x00,0x42,0xAD, ++0xDE,0x5D,0x65,0x91, ++0x25,0xB0,0x0C,0x3C, ++0x01,0x00,0x03,0x3C, ++0x80,0x01,0x82,0x35, ++0x08,0x5F,0x63,0x34, ++0x22,0x00,0x04,0x24, ++0x00,0x00,0x43,0xAC, ++0x1D,0xFF,0xA4,0x14, ++0x0F,0x1F,0x02,0x3C, ++0x00,0xF0,0x4F,0x34, ++0xF7,0x01,0x91,0x35, ++0x15,0xF0,0x4D,0x34, ++0x78,0x67,0x00,0x08, ++0xFF,0xFF,0x0E,0x24, ++0x02,0x80,0x02,0x3C, ++0xDF,0x5D,0x44,0x90, ++0x06,0x00,0x03,0x24, ++0x0C,0x00,0x83,0x10, ++0x00,0x1C,0x02,0x3C, ++0x00,0x1C,0x42,0x34, ++0xA0,0x00,0x24,0x36, ++0x00,0x00,0x82,0xAC, ++0x00,0xE0,0x02,0x3C, ++0xA4,0x00,0x25,0x36, ++0x00,0x04,0x03,0x24, ++0xA8,0x00,0x26,0x36, ++0x00,0xB0,0x42,0x34, ++0x00,0x00,0xA3,0xAC, ++0xDA,0x66,0x00,0x08, ++0x00,0x00,0x00,0x00, ++0x16,0x16,0x02,0x3C, ++0x07,0x07,0x42,0x34, ++0xA0,0x00,0x23,0x36, ++0x00,0x00,0x62,0xAC, ++0x00,0xC0,0x02,0x3C, ++0xA8,0x00,0x25,0x36, ++0xA4,0x00,0x24,0x36, ++0x00,0xB4,0x42,0x34, ++0x00,0x00,0x80,0xAC, ++0x00,0x00,0xA2,0xAC, ++0xDC,0x66,0x00,0x08, ++0x02,0x80,0x03,0x3C, ++0xE8,0xFF,0xBD,0x27, ++0x01,0x00,0x06,0x24, ++0xE8,0x0E,0x04,0x24, ++0x10,0x00,0xBF,0xAF, ++0xA9,0x45,0x00,0x0C, ++0x00,0x10,0x05,0x3C, ++0x60,0x08,0x04,0x24, ++0xCB,0x45,0x00,0x0C, ++0xFF,0xFF,0x05,0x24, ++0x20,0x04,0x06,0x3C, ++0x20,0x04,0xC6,0x34, ++0x25,0x30,0x46,0x00, ++0x60,0x08,0x04,0x24, ++0xA9,0x45,0x00,0x0C, ++0xFF,0xFF,0x05,0x24, ++0x70,0x08,0x04,0x24, ++0x00,0x04,0x05,0x24, ++0xA9,0x45,0x00,0x0C, ++0x21,0x30,0x00,0x00, ++0x00,0x20,0x06,0x3C, ++0x80,0x00,0xC6,0x34, ++0x80,0x0C,0x04,0x24, ++0xA9,0x45,0x00,0x0C, ++0xFF,0xFF,0x05,0x24, ++0x00,0x40,0x06,0x3C, ++0x10,0x00,0xBF,0x8F, ++0x00,0x01,0xC6,0x34, ++0x88,0x0C,0x04,0x24, ++0xFF,0xFF,0x05,0x24, ++0xA9,0x45,0x00,0x08, ++0x18,0x00,0xBD,0x27, ++0x10,0x00,0xA0,0x10, ++0x21,0x38,0x00,0x00, ++0x25,0xB0,0x08,0x3C, ++0x00,0x00,0x82,0x8C, ++0x04,0x00,0x83,0x8C, ++0x21,0x30,0x00,0x00, ++0x21,0x10,0x48,0x00, ++0x00,0x00,0x43,0xAC, ++0x01,0x00,0xC2,0x24, ++0xFF,0x00,0x46,0x30, ++0x06,0x00,0xC3,0x2C, ++0xFD,0xFF,0x60,0x14, ++0x01,0x00,0xC2,0x24, ++0x02,0x00,0xE7,0x24, ++0x2B,0x10,0xE5,0x00, ++0xF3,0xFF,0x40,0x14, ++0x08,0x00,0x84,0x24, ++0x08,0x00,0xE0,0x03, ++0x00,0x00,0x00,0x00, ++0xE0,0xFF,0xBD,0x27, ++0x18,0x00,0xB2,0xAF, ++0x14,0x00,0xB1,0xAF, ++0x1C,0x00,0xBF,0xAF, ++0x10,0x00,0xB0,0xAF, ++0x21,0x90,0xA0,0x00, ++0x0B,0x00,0xA0,0x10, ++0x21,0x88,0x00,0x00, ++0x21,0x80,0x80,0x00, ++0x00,0x00,0x04,0x8E, ++0x04,0x00,0x05,0x8E, ++0x08,0x00,0x06,0x8E, ++0x03,0x00,0x31,0x26, ++0xA9,0x45,0x00,0x0C, ++0x0C,0x00,0x10,0x26, ++0x2B,0x10,0x32,0x02, ++0xF8,0xFF,0x40,0x14, ++0x00,0x00,0x00,0x00, ++0x1C,0x00,0xBF,0x8F, ++0x18,0x00,0xB2,0x8F, ++0x14,0x00,0xB1,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x08,0x00,0xE0,0x03, ++0x20,0x00,0xBD,0x27, ++0x21,0x40,0x80,0x00, ++0x21,0x48,0x00,0x00, ++0x1E,0x00,0xA0,0x10, ++0x21,0x38,0x00,0x00, ++0x80,0x30,0x07,0x00, ++0x21,0x10,0xC8,0x00, ++0x00,0x00,0x43,0x8C, ++0x00,0x00,0x00,0x00, ++0x00,0xF2,0x63,0x24, ++0x1D,0x00,0x62,0x2C, ++0x12,0x00,0x40,0x10, ++0x80,0x10,0x03,0x00, ++0x02,0x80,0x03,0x3C, ++0x64,0xE9,0x63,0x24, ++0x21,0x10,0x43,0x00, ++0x00,0x00,0x44,0x8C, ++0x00,0x00,0x00,0x00, ++0x08,0x00,0x80,0x00, ++0x00,0x00,0x00,0x00, ++0x21,0x10,0xC8,0x00, ++0xC0,0x18,0x09,0x00, ++0x23,0x18,0x69,0x00, ++0x08,0x00,0x44,0x8C, ++0x02,0x80,0x02,0x3C, ++0x80,0x18,0x03,0x00, ++0x30,0x1F,0x42,0x24, ++0x21,0x18,0x62,0x00, ++0x04,0x1D,0x64,0xAC, ++0x01,0x00,0x29,0x25, ++0x03,0x00,0xE7,0x24, ++0x2B,0x10,0xE5,0x00, ++0xE5,0xFF,0x40,0x14, ++0x80,0x30,0x07,0x00, ++0x08,0x00,0xE0,0x03, ++0x00,0x00,0x00,0x00, ++0x21,0x10,0xC8,0x00, ++0xC0,0x18,0x09,0x00, ++0x08,0x00,0x44,0x8C, ++0x23,0x18,0x69,0x00, ++0x02,0x80,0x02,0x3C, ++0x30,0x1F,0x42,0x24, ++0x80,0x18,0x03,0x00, ++0x03,0x00,0xE7,0x24, ++0x21,0x18,0x62,0x00, ++0x2B,0x10,0xE5,0x00, ++0xD6,0xFF,0x40,0x14, ++0x00,0x1D,0x64,0xAC, ++0xE0,0x68,0x00,0x08, ++0x00,0x00,0x00,0x00, ++0x21,0x10,0xC8,0x00, ++0xC0,0x18,0x09,0x00, ++0x08,0x00,0x44,0x8C, ++0x23,0x18,0x69,0x00, ++0x02,0x80,0x02,0x3C, ++0x30,0x1F,0x42,0x24, ++0x80,0x18,0x03,0x00, ++0x03,0x00,0xE7,0x24, ++0x21,0x18,0x62,0x00, ++0x2B,0x10,0xE5,0x00, ++0xC8,0xFF,0x40,0x14, ++0xFC,0x1C,0x64,0xAC, ++0xE0,0x68,0x00,0x08, ++0x00,0x00,0x00,0x00, ++0x21,0x10,0xC8,0x00, ++0xC0,0x18,0x09,0x00, ++0x08,0x00,0x44,0x8C, ++0x23,0x18,0x69,0x00, ++0x02,0x80,0x02,0x3C, ++0x30,0x1F,0x42,0x24, ++0x80,0x18,0x03,0x00, ++0x03,0x00,0xE7,0x24, ++0x21,0x18,0x62,0x00, ++0x2B,0x10,0xE5,0x00, ++0xBA,0xFF,0x40,0x14, ++0xF8,0x1C,0x64,0xAC, ++0xE0,0x68,0x00,0x08, ++0x00,0x00,0x00,0x00, ++0x21,0x10,0xC8,0x00, ++0xC0,0x18,0x09,0x00, ++0x08,0x00,0x44,0x8C, ++0x23,0x18,0x69,0x00, ++0x02,0x80,0x02,0x3C, ++0x30,0x1F,0x42,0x24, ++0x80,0x18,0x03,0x00, ++0x03,0x00,0xE7,0x24, ++0x21,0x18,0x62,0x00, ++0x2B,0x10,0xE5,0x00, ++0xAC,0xFF,0x40,0x14, ++0x08,0x1D,0x64,0xAC, ++0xE0,0x68,0x00,0x08, ++0x00,0x00,0x00,0x00, ++0x21,0x10,0xC8,0x00, ++0xC0,0x18,0x09,0x00, ++0x08,0x00,0x44,0x8C, ++0x23,0x18,0x69,0x00, ++0x02,0x80,0x02,0x3C, ++0x30,0x1F,0x42,0x24, ++0x80,0x18,0x03,0x00, ++0x03,0x00,0xE7,0x24, ++0x21,0x18,0x62,0x00, ++0x2B,0x10,0xE5,0x00, ++0x9E,0xFF,0x40,0x14, ++0xF4,0x1C,0x64,0xAC, ++0xE0,0x68,0x00,0x08, ++0x00,0x00,0x00,0x00, ++0x21,0x10,0xC8,0x00, ++0xC0,0x18,0x09,0x00, ++0x08,0x00,0x44,0x8C, ++0x23,0x18,0x69,0x00, ++0x02,0x80,0x02,0x3C, ++0x30,0x1F,0x42,0x24, ++0x80,0x18,0x03,0x00, ++0x03,0x00,0xE7,0x24, ++0x21,0x18,0x62,0x00, ++0x2B,0x10,0xE5,0x00, ++0x90,0xFF,0x40,0x14, ++0xF0,0x1C,0x64,0xAC, ++0xE0,0x68,0x00,0x08, ++0x00,0x00,0x00,0x00, ++0x25,0xB0,0x02,0x3C, ++0xFC,0x37,0x03,0x24, ++0x40,0x00,0x42,0x34, ++0x02,0x80,0x04,0x3C, ++0x00,0x00,0x43,0xA4, ++0xE8,0xFF,0xBD,0x27, ++0xA4,0xCF,0x84,0x24, ++0x10,0x00,0xBF,0xAF, ++0x94,0x68,0x00,0x0C, ++0x74,0x01,0x05,0x24, ++0x02,0x80,0x02,0x3C, ++0xDE,0x5D,0x44,0x90, ++0x12,0x00,0x03,0x24, ++0x34,0x00,0x83,0x10, ++0x13,0x00,0x82,0x28, ++0x17,0x00,0x40,0x14, ++0x11,0x00,0x02,0x24, ++0x22,0x00,0x02,0x24, ++0x36,0x00,0x82,0x10, ++0x02,0x80,0x04,0x3C, ++0x02,0x80,0x04,0x3C, ++0x2C,0xCC,0x84,0x24, ++0xBF,0x68,0x00,0x0C, ++0x54,0x00,0x05,0x24, ++0x02,0x80,0x02,0x3C, ++0x4A,0xF3,0x44,0x90, ++0x01,0x00,0x03,0x24, ++0x1A,0x00,0x83,0x10, ++0x00,0x00,0x00,0x00, ++0x02,0x80,0x04,0x3C, ++0x2C,0xC7,0x84,0x24, ++0x94,0x68,0x00,0x0C, ++0x40,0x01,0x05,0x24, ++0x10,0x00,0xBF,0x8F, ++0x84,0x08,0x04,0x24, ++0xFF,0x00,0x05,0x24, ++0x58,0x00,0x06,0x24, ++0x1B,0x47,0x00,0x08, ++0x18,0x00,0xBD,0x27, ++0xED,0xFF,0x82,0x14, ++0x02,0x80,0x04,0x3C, ++0x02,0x80,0x04,0x3C, ++0xE4,0xCE,0x84,0x24, ++0xA7,0x68,0x00,0x0C, ++0x30,0x00,0x05,0x24, ++0x02,0x80,0x04,0x3C, ++0x2C,0xCC,0x84,0x24, ++0xBF,0x68,0x00,0x0C, ++0x54,0x00,0x05,0x24, ++0x02,0x80,0x02,0x3C, ++0x4A,0xF3,0x44,0x90, ++0x01,0x00,0x03,0x24, ++0xE8,0xFF,0x83,0x14, ++0x00,0x00,0x00,0x00, ++0x75,0x68,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x02,0x80,0x04,0x3C, ++0x2C,0xC7,0x84,0x24, ++0x94,0x68,0x00,0x0C, ++0x40,0x01,0x05,0x24, ++0x10,0x00,0xBF,0x8F, ++0x84,0x08,0x04,0x24, ++0xFF,0x00,0x05,0x24, ++0x58,0x00,0x06,0x24, ++0x1B,0x47,0x00,0x08, ++0x18,0x00,0xBD,0x27, ++0x02,0x80,0x04,0x3C, ++0x30,0xCE,0x84,0x24, ++0x2D,0x00,0x05,0x24, ++0xA7,0x68,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x64,0x69,0x00,0x08, ++0x02,0x80,0x04,0x3C, ++0x7C,0xCD,0x84,0x24, ++0x7B,0x69,0x00,0x08, ++0x2D,0x00,0x05,0x24, ++0xE8,0xFF,0xBD,0x27, ++0x10,0x00,0xB0,0xAF, ++0x50,0x0C,0x04,0x24, ++0xFF,0x00,0x05,0x24, ++0x02,0x80,0x10,0x3C, ++0x14,0x00,0xBF,0xAF, ++0x0A,0x47,0x00,0x0C, ++0x30,0x1F,0x10,0x26, ++0x60,0x1D,0x02,0xA2, ++0x58,0x0C,0x04,0x24, ++0x0A,0x47,0x00,0x0C, ++0xFF,0x00,0x05,0x24, ++0x61,0x1D,0x02,0xA2, ++0x60,0x0C,0x04,0x24, ++0x0A,0x47,0x00,0x0C, ++0xFF,0x00,0x05,0x24, ++0x62,0x1D,0x02,0xA2, ++0x68,0x0C,0x04,0x24, ++0x0A,0x47,0x00,0x0C, ++0xFF,0x00,0x05,0x24, ++0x63,0x1D,0x02,0xA2, ++0x38,0x0C,0x04,0x24, ++0x0A,0x47,0x00,0x0C, ++0xFF,0x00,0x05,0x24, ++0xE8,0x1C,0x02,0xA2, ++0x34,0x0C,0x04,0x24, ++0x0A,0x47,0x00,0x0C, ++0xFF,0xFF,0x05,0x24, ++0xEC,0x1C,0x02,0xAE, ++0x14,0x00,0xBF,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x08,0x00,0xE0,0x03, ++0x18,0x00,0xBD,0x27, ++0x02,0x80,0x02,0x3C, ++0x02,0x80,0x05,0x3C, ++0x02,0x80,0x03,0x3C, ++0x84,0xA7,0x42,0x24, ++0xBC,0x5E,0x60,0xAC, ++0x1C,0x5E,0xA2,0xAC, ++0x02,0x80,0x03,0x3C, ++0x00,0x80,0x02,0x3C, ++0xC0,0x5E,0x60,0xA4, ++0x1C,0x5E,0xA4,0x24, ++0x88,0x0D,0x42,0x24, ++0x02,0x80,0x03,0x3C, ++0xC2,0x5E,0x60,0xA4, ++0x08,0x00,0x82,0xAC, ++0x00,0x80,0x03,0x3C, ++0x00,0x80,0x02,0x3C, ++0x02,0x80,0x06,0x3C, ++0x88,0x10,0x42,0x24, ++0xA4,0x0D,0x63,0x24, ++0xC4,0x5E,0xC7,0x24, ++0x14,0x00,0x82,0xAC, ++0x10,0x00,0x83,0xAC, ++0x02,0x80,0x02,0x3C, ++0x02,0x80,0x03,0x3C, ++0xC4,0x5E,0xC0,0xAC, ++0x04,0x00,0xE0,0xAC, ++0xCC,0x5E,0x40,0xA0, ++0xD0,0x5E,0x60,0xAC, ++0x01,0x80,0x02,0x3C, ++0x30,0xD2,0x42,0x24, ++0x7C,0x00,0x82,0xAC, ++0x00,0x80,0x03,0x3C, ++0x00,0x80,0x02,0x3C, ++0xA4,0x10,0x63,0x24, ++0x64,0x13,0x42,0x24, ++0x1C,0x00,0x83,0xAC, ++0x20,0x00,0x82,0xAC, ++0x00,0x80,0x03,0x3C, ++0x00,0x80,0x02,0x3C, ++0x2C,0x16,0x63,0x24, ++0xF0,0x18,0x42,0x24, ++0x24,0x00,0x83,0xAC, ++0x28,0x00,0x82,0xAC, ++0x00,0x80,0x03,0x3C, ++0x01,0x80,0x02,0x3C, ++0xC8,0x2A,0x63,0x24, ++0x98,0x01,0x42,0x24, ++0x2C,0x00,0x83,0xAC, ++0x50,0x00,0x82,0xAC, ++0x00,0x80,0x03,0x3C, ++0x00,0x80,0x02,0x3C, ++0x10,0x1C,0x63,0x24, ++0xFC,0x1D,0x42,0x24, ++0x30,0x00,0x83,0xAC, ++0x38,0x00,0x82,0xAC, ++0x00,0x80,0x03,0x3C, ++0x00,0x80,0x02,0x3C, ++0x00,0x03,0x63,0x24, ++0xB4,0x1B,0x42,0x24, ++0x4C,0x00,0x83,0xAC, ++0x08,0x00,0xE0,0x03, ++0x3C,0x00,0x82,0xAC, ++0x25,0xB0,0x02,0x3C, ++0x08,0x00,0x42,0x34, ++0x00,0x00,0x43,0x8C, ++0x08,0x00,0xE0,0x03, ++0x00,0x00,0x00,0x00, ++0x02,0x80,0x0E,0x3C, ++0x02,0x80,0x08,0x3C, ++0x02,0x80,0x02,0x3C, ++0x02,0x80,0x03,0x3C, ++0xF8,0x03,0x4D,0x24, ++0x00,0x1C,0x6C,0x24, ++0x01,0x00,0x07,0x24, ++0x00,0x00,0xCB,0x25, ++0xFF,0xFF,0x0A,0x24, ++0x00,0x04,0x09,0x25, ++0x80,0x1A,0x07,0x00, ++0x21,0x10,0x6B,0x00, ++0x00,0x00,0x42,0xAC, ++0x90,0x00,0x4A,0xAC, ++0x00,0x04,0x04,0x8D, ++0x01,0x00,0xE7,0x24, ++0x08,0x00,0x45,0x24, ++0x21,0x18,0x6D,0x00, ++0x07,0x00,0xE6,0x28, ++0x04,0x00,0x82,0xAC, ++0x00,0x00,0x44,0xAC, ++0x04,0x00,0x49,0xAC, ++0x00,0x04,0x02,0xAD, ++0x8C,0x00,0x40,0xAC, ++0x6C,0x00,0xA3,0xAC, ++0xF0,0xFF,0xC0,0x14, ++0x68,0x00,0xAC,0xAC, ++0x08,0x00,0xE0,0x03, ++0x00,0x00,0xC9,0xAD, ++0x07,0x00,0xA2,0x2C, ++0x13,0x00,0x40,0x10, ++0xFF,0xFF,0x07,0x24, ++0x02,0x80,0x02,0x3C, ++0x80,0x1A,0x05,0x00, ++0x00,0x00,0x42,0x24, ++0x0E,0x00,0xA0,0x10, ++0x21,0x30,0x62,0x00, ++0x90,0x00,0xC3,0x8C, ++0xFF,0xFF,0x02,0x24, ++0x0A,0x00,0x62,0x14, ++0x00,0x00,0x00,0x00, ++0x8C,0x00,0xC2,0x8C, ++0x00,0x00,0x00,0x00, ++0x06,0x00,0x40,0x14, ++0x00,0x00,0x00,0x00, ++0x01,0x00,0x02,0x24, ++0x88,0x00,0xC4,0xAC, ++0x8C,0x00,0xC2,0xAC, ++0x90,0x00,0xC5,0xAC, ++0x21,0x38,0xA0,0x00, ++0x08,0x00,0xE0,0x03, ++0x21,0x10,0xE0,0x00, ++0x25,0xB0,0x06,0x3C, ++0x02,0x80,0x02,0x3C, ++0xE0,0xFF,0xBD,0x27, ++0x68,0xA8,0x42,0x24, ++0xDB,0xFF,0x03,0x24, ++0x18,0x03,0xC4,0x34, ++0x27,0x00,0xC5,0x34, ++0x00,0x00,0x82,0xAC, ++0x1C,0x00,0xBF,0xAF, ++0x18,0x00,0xB2,0xAF, ++0x14,0x00,0xB1,0xAF, ++0x10,0x00,0xB0,0xAF, ++0x00,0x00,0xA3,0xA0, ++0x06,0x00,0xC2,0x34, ++0x00,0x00,0x43,0x90, ++0x00,0x00,0x00,0x00, ++0x0F,0x00,0x63,0x30, ++0x5A,0x00,0x60,0x14, ++0x01,0x00,0x02,0x24, ++0x1B,0x00,0xC3,0x34, ++0x07,0x00,0x02,0x24, ++0x00,0x00,0x62,0xA0, ++0xE6,0x44,0x00,0x0C, ++0x21,0x20,0x00,0x00, ++0x02,0x80,0x02,0x3C, ++0x30,0x1F,0x50,0x24, ++0x34,0x1C,0x04,0x8E, ++0xCB,0x45,0x00,0x0C, ++0x10,0x00,0x05,0x24, ++0x40,0x1C,0x04,0x8E, ++0x10,0x00,0x05,0x3C, ++0x01,0x00,0x06,0x24, ++0xA9,0x45,0x00,0x0C, ++0x21,0x90,0x40,0x00, ++0x3C,0x1C,0x04,0x8E, ++0x10,0x00,0x05,0x24, ++0xA9,0x45,0x00,0x0C, ++0x01,0x00,0x06,0x24, ++0x58,0x1C,0x04,0x8E, ++0x00,0x04,0x05,0x24, ++0xA9,0x45,0x00,0x0C, ++0x21,0x30,0x00,0x00, ++0x58,0x1C,0x04,0x8E, ++0x00,0x08,0x05,0x24, ++0xA9,0x45,0x00,0x0C, ++0x21,0x30,0x00,0x00, ++0x02,0x80,0x05,0x3C, ++0xEC,0xD9,0xA5,0x24, ++0x21,0x20,0x00,0x00, ++0x9F,0x47,0x00,0x0C, ++0xCA,0x00,0x06,0x24, ++0x31,0x00,0x40,0x10, ++0x21,0x18,0x00,0x00, ++0x02,0x80,0x02,0x3C, ++0xE7,0x5D,0x43,0x90, ++0x01,0x00,0x11,0x24, ++0x57,0x00,0x71,0x10, ++0x02,0x80,0x05,0x3C, ++0x02,0x80,0x02,0x3C, ++0x4A,0xF3,0x43,0x90, ++0x00,0x00,0x00,0x00, ++0x58,0x00,0x71,0x10, ++0x02,0x80,0x05,0x3C, ++0x34,0x1C,0x04,0x8E, ++0x21,0x30,0x40,0x02, ++0x10,0x00,0x05,0x24, ++0xA9,0x45,0x00,0x0C, ++0x02,0x80,0x11,0x3C, ++0xDE,0x5D,0x23,0x92, ++0x11,0x00,0x02,0x24, ++0x2E,0x00,0x62,0x10, ++0x00,0x08,0x04,0x24, ++0xE6,0x44,0x00,0x0C, ++0x01,0x00,0x04,0x24, ++0x34,0x1C,0x04,0x8E, ++0xCB,0x45,0x00,0x0C, ++0x10,0x00,0x05,0x3C, ++0x40,0x1C,0x04,0x8E, ++0x10,0x00,0x05,0x3C, ++0x01,0x00,0x06,0x24, ++0xA9,0x45,0x00,0x0C, ++0x21,0x90,0x40,0x00, ++0x3C,0x1C,0x04,0x8E, ++0x10,0x00,0x05,0x24, ++0xA9,0x45,0x00,0x0C, ++0x01,0x00,0x06,0x24, ++0x58,0x1C,0x04,0x8E, ++0x00,0x04,0x05,0x24, ++0xA9,0x45,0x00,0x0C, ++0x21,0x30,0x00,0x00, ++0x58,0x1C,0x04,0x8E, ++0x00,0x08,0x05,0x24, ++0xA9,0x45,0x00,0x0C, ++0x21,0x30,0x00,0x00, ++0x02,0x80,0x05,0x3C, ++0x94,0xD9,0xA5,0x24, ++0x01,0x00,0x04,0x24, ++0x9F,0x47,0x00,0x0C, ++0x16,0x00,0x06,0x24, ++0x0C,0x00,0x40,0x14, ++0x21,0x18,0x00,0x00, ++0x1C,0x00,0xBF,0x8F, ++0x18,0x00,0xB2,0x8F, ++0x14,0x00,0xB1,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x21,0x10,0x60,0x00, ++0x08,0x00,0xE0,0x03, ++0x20,0x00,0xBD,0x27, ++0xA9,0xFF,0x62,0x14, ++0x1F,0x00,0xC3,0x34, ++0x2F,0x6A,0x00,0x08, ++0x07,0x00,0x02,0x24, ++0x34,0x1C,0x04,0x8E, ++0x21,0x30,0x40,0x02, ++0xA9,0x45,0x00,0x0C, ++0x10,0x00,0x05,0x3C, ++0x00,0x08,0x04,0x24, ++0x00,0x01,0x05,0x3C, ++0xA9,0x45,0x00,0x0C, ++0x01,0x00,0x06,0x24, ++0x00,0x08,0x04,0x24, ++0x00,0x02,0x05,0x3C, ++0xA9,0x45,0x00,0x0C, ++0x01,0x00,0x06,0x24, ++0xDE,0x5D,0x23,0x92, ++0x11,0x00,0x02,0x24, ++0x1D,0x00,0x62,0x10, ++0x00,0x08,0x04,0x24, ++0xE6,0x44,0x00,0x0C, ++0x21,0x20,0x00,0x00, ++0x0F,0x00,0x05,0x3C, ++0x0C,0x00,0x06,0x3C, ++0xFF,0xFF,0xA5,0x34, ++0x00,0xB4,0xC6,0x34, ++0x5F,0x47,0x00,0x0C, ++0x08,0x00,0x04,0x24, ++0x1C,0x00,0xBF,0x8F, ++0x18,0x00,0xB2,0x8F, ++0x14,0x00,0xB1,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x01,0x00,0x03,0x24, ++0x21,0x10,0x60,0x00, ++0x08,0x00,0xE0,0x03, ++0x20,0x00,0xBD,0x27, ++0x84,0xD8,0xA5,0x24, ++0x21,0x20,0x00,0x00, ++0x9F,0x47,0x00,0x0C, ++0x16,0x00,0x06,0x24, ++0x55,0x6A,0x00,0x08, ++0x02,0x80,0x02,0x3C, ++0xDC,0xD8,0xA5,0x24, ++0x21,0x20,0x00,0x00, ++0x9F,0x47,0x00,0x0C, ++0x16,0x00,0x06,0x24, ++0x59,0x6A,0x00,0x08, ++0x00,0x00,0x00,0x00, ++0x00,0xFF,0x05,0x3C, ++0xA9,0x45,0x00,0x0C, ++0x03,0x00,0x06,0x24, ++0x9A,0x6A,0x00,0x08, ++0x00,0x00,0x00,0x00, ++0x08,0x00,0xE0,0x03, ++0x00,0x00,0x00,0x00, ++0xE8,0xFF,0xBD,0x27, ++0x10,0x00,0xBF,0xAF, ++0x02,0x80,0x02,0x3C, ++0x61,0x5A,0x47,0x90, ++0x02,0x80,0x04,0x3C, ++0x02,0x80,0x05,0x3C, ++0x03,0x00,0x03,0x24, ++0x1E,0x3B,0x84,0x24, ++0xAC,0xE3,0xA5,0x24, ++0x0F,0x00,0xE3,0x10, ++0x0D,0x00,0x06,0x24, ++0x02,0x80,0x04,0x3C, ++0x02,0x80,0x05,0x3C, ++0x1E,0x3B,0x84,0x24, ++0x5C,0xE3,0xA5,0x24, ++0x10,0x52,0x00,0x0C, ++0x0D,0x00,0x06,0x24, ++0x02,0x80,0x04,0x3C, ++0x02,0x80,0x05,0x3C, ++0x10,0x00,0xBF,0x8F, ++0x2B,0x3B,0x84,0x24, ++0x6C,0xE3,0xA5,0x24, ++0x0D,0x00,0x06,0x24, ++0x10,0x52,0x00,0x08, ++0x18,0x00,0xBD,0x27, ++0x10,0x52,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x02,0x80,0x04,0x3C, ++0x02,0x80,0x05,0x3C, ++0x10,0x00,0xBF,0x8F, ++0x2B,0x3B,0x84,0x24, ++0x9C,0xE3,0xA5,0x24, ++0x0D,0x00,0x06,0x24, ++0x10,0x52,0x00,0x08, ++0x18,0x00,0xBD,0x27, ++0xE0,0xFF,0xBD,0x27, ++0x14,0x00,0xB1,0xAF, ++0x10,0x00,0xB0,0xAF, ++0x02,0x80,0x11,0x3C, ++0x02,0x80,0x05,0x3C, ++0x02,0x80,0x10,0x3C, ++0x30,0x1F,0x10,0x26, ++0x64,0x5A,0x24,0x26, ++0x14,0xDD,0xA5,0x24, ++0x34,0x00,0x06,0x24, ++0x18,0x00,0xBF,0xAF, ++0x10,0x52,0x00,0x0C, ++0x64,0x5A,0x31,0x26, ++0xBD,0x6A,0x00,0x0C, ++0x68,0x3B,0x11,0xAE, ++0x02,0x00,0x11,0x24, ++0x02,0x80,0x04,0x3C, ++0x00,0x80,0x06,0x3C, ++0xA0,0x38,0x11,0xA2, ++0xBC,0x57,0x84,0x24, ++0xFC,0x64,0xC6,0x24, ++0x21,0x28,0x00,0x00, ++0xA2,0x23,0x00,0x0C, ++0x98,0x38,0x00,0xAE, ++0x02,0x80,0x04,0x3C, ++0x01,0x80,0x06,0x3C, ++0xBC,0x38,0x11,0xA2, ++0xD8,0x57,0x84,0x24, ++0x0C,0x31,0xC6,0x24, ++0x21,0x28,0x00,0x00, ++0xA2,0x23,0x00,0x0C, ++0xB4,0x38,0x00,0xAE, ++0x02,0x80,0x04,0x3C, ++0x01,0x80,0x06,0x3C, ++0xD8,0x38,0x11,0xA2, ++0xF4,0x57,0x84,0x24, ++0xC0,0x2E,0xC6,0x24, ++0x21,0x28,0x00,0x00, ++0xA2,0x23,0x00,0x0C, ++0xD0,0x38,0x00,0xAE, ++0x02,0x80,0x04,0x3C, ++0x01,0x80,0x06,0x3C, ++0xF4,0x38,0x11,0xA2, ++0x10,0x58,0x84,0x24, ++0x14,0x25,0xC6,0x24, ++0x21,0x28,0x00,0x00, ++0xA2,0x23,0x00,0x0C, ++0xEC,0x38,0x00,0xAE, ++0x02,0x80,0x04,0x3C, ++0x00,0x80,0x06,0x3C, ++0x10,0x39,0x11,0xA2, ++0x2C,0x58,0x84,0x24, ++0x58,0x64,0xC6,0x24, ++0x21,0x28,0x00,0x00, ++0xA2,0x23,0x00,0x0C, ++0x08,0x39,0x00,0xAE, ++0x02,0x80,0x04,0x3C, ++0x00,0x80,0x06,0x3C, ++0x48,0x39,0x11,0xA2, ++0x40,0x39,0x00,0xAE, ++0x64,0x58,0x84,0x24, ++0x38,0x3B,0xC6,0x24, ++0xA2,0x23,0x00,0x0C, ++0x21,0x28,0x00,0x00, ++0x02,0x80,0x02,0x3C, ++0x49,0xF3,0x43,0x90, ++0x18,0x00,0xBF,0x8F, ++0x14,0x00,0xB1,0x8F, ++0x9C,0x3E,0x03,0xA2, ++0x10,0x00,0xB0,0x8F, ++0x08,0x00,0xE0,0x03, ++0x20,0x00,0xBD,0x27, ++0x03,0x80,0x05,0x3C, ++0x00,0x80,0xA5,0x24, ++0x40,0x10,0x0D,0x3C, ++0xFF,0xFF,0xA5,0x30, ++0x02,0x80,0x02,0x3C, ++0x30,0x1F,0x42,0x24, ++0x25,0xC8,0xAD,0x00, ++0x38,0x37,0x59,0xAC, ++0x00,0x01,0x39,0x27, ++0xE0,0xFF,0xBD,0x27, ++0x44,0x37,0x59,0xAC, ++0x00,0x01,0x39,0x27, ++0x1C,0x00,0xB7,0xAF, ++0x18,0x00,0xB6,0xAF, ++0x14,0x00,0xB5,0xAF, ++0x10,0x00,0xB4,0xAF, ++0x0C,0x00,0xB3,0xAF, ++0x08,0x00,0xB2,0xAF, ++0x04,0x00,0xB1,0xAF, ++0x00,0x00,0xB0,0xAF, ++0x50,0x37,0x59,0xAC, ++0x00,0x01,0x39,0x27, ++0x5C,0x37,0x59,0xAC, ++0xAA,0x1B,0x44,0x90, ++0x00,0x01,0x39,0x27, ++0x68,0x37,0x59,0xAC, ++0x00,0x01,0x39,0x27, ++0x74,0x37,0x59,0xAC, ++0x20,0xB0,0x06,0x3C, ++0x44,0x37,0x48,0x8C, ++0x50,0x37,0x49,0x8C, ++0x5C,0x37,0x4A,0x8C, ++0x68,0x37,0x4B,0x8C, ++0x74,0x37,0x4C,0x8C, ++0x00,0x22,0x04,0x00, ++0x00,0x01,0xC7,0x34, ++0xFF,0x1F,0x03,0x3C, ++0x00,0x01,0x39,0x27, ++0xFF,0xFF,0x63,0x34, ++0x21,0x38,0x87,0x00, ++0x21,0x20,0x86,0x00, ++0x24,0x38,0xE3,0x00, ++0x20,0x10,0x06,0x3C, ++0x24,0x20,0x83,0x00, ++0x80,0x37,0x59,0xAC, ++0x21,0x78,0x20,0x03, ++0x25,0x28,0xAD,0x00, ++0x25,0xB0,0x0E,0x3C, ++0x00,0x01,0x39,0x27, ++0x34,0x37,0x45,0xAC, ++0x40,0x37,0x48,0xAC, ++0x4C,0x37,0x49,0xAC, ++0x58,0x37,0x4A,0xAC, ++0xF8,0x36,0x44,0xAC, ++0x64,0x37,0x4B,0xAC, ++0x04,0x37,0x47,0xAC, ++0x70,0x37,0x4C,0xAC, ++0xAC,0x00,0xC3,0x35, ++0xCC,0x36,0x46,0xAC, ++0xC8,0x36,0x46,0xAC, ++0xD8,0x36,0x46,0xAC, ++0xD4,0x36,0x46,0xAC, ++0xE4,0x36,0x46,0xAC, ++0x8C,0x37,0x59,0xAC, ++0xFC,0x36,0x44,0xAC, ++0x08,0x37,0x47,0xAC, ++0x7C,0x37,0x4F,0xAC, ++0xE0,0x36,0x46,0xAC, ++0xF0,0x36,0x46,0xAC, ++0xEC,0x36,0x46,0xAC, ++0x14,0x37,0x46,0xAC, ++0x10,0x37,0x46,0xAC, ++0x00,0x02,0x39,0x27, ++0x00,0x00,0x68,0x8C, ++0xAC,0x1B,0x47,0x94, ++0xA4,0x37,0x59,0xAC, ++0xB0,0x00,0xC3,0x35, ++0x00,0x00,0x75,0x8C, ++0x21,0x10,0x05,0x3C, ++0x8C,0x37,0x52,0x8C, ++0x23,0x10,0x0B,0x3C, ++0x22,0x10,0x0F,0x3C, ++0x02,0x80,0x14,0x3C, ++0x02,0x80,0x16,0x3C, ++0x02,0x80,0x17,0x3C, ++0x02,0x80,0x18,0x3C, ++0x00,0x80,0xA4,0x34, ++0x21,0x98,0x20,0x03, ++0x23,0x20,0x87,0x00, ++0x00,0x04,0x39,0x27, ++0x24,0x10,0x07,0x3C, ++0x9C,0x57,0x8A,0x26, ++0xA4,0x57,0xC9,0x26, ++0xAC,0x57,0xEC,0x26, ++0xB4,0x57,0x0D,0x27, ++0x00,0x04,0x70,0x35, ++0x01,0x00,0x08,0x25, ++0x00,0x40,0xF1,0x35, ++0x00,0x01,0xCE,0x35, ++0x01,0x00,0x03,0x24, ++0x88,0x37,0x52,0xAC, ++0x91,0x37,0x43,0xA0, ++0xA0,0x37,0x53,0xAC, ++0x08,0x38,0x50,0xAC, ++0xCC,0x37,0x48,0xAC, ++0xD8,0x37,0x44,0xAC, ++0xFC,0x37,0x51,0xAC, ++0xF0,0x37,0x55,0xAC, ++0x00,0x00,0xC7,0xAD, ++0xEC,0x37,0x47,0xAC, ++0x0C,0x38,0x46,0xAC, ++0x20,0x37,0x46,0xAC, ++0x1C,0x37,0x46,0xAC, ++0xAA,0x37,0x40,0xA4, ++0xA9,0x37,0x40,0xA0, ++0xA8,0x37,0x40,0xA0, ++0x00,0x38,0x4B,0xAC, ++0x04,0x38,0x4B,0xAC, ++0xC4,0x37,0x45,0xAC, ++0xC8,0x37,0x45,0xAC, ++0xD0,0x37,0x45,0xAC, ++0xD4,0x37,0x45,0xAC, ++0xF4,0x37,0x4F,0xAC, ++0xF8,0x37,0x4F,0xAC, ++0xE8,0x37,0x47,0xAC, ++0x10,0x38,0x46,0xAC, ++0x1C,0x38,0x59,0xAC, ++0x18,0x38,0x59,0xAC, ++0x04,0x00,0x4A,0xAD, ++0x9C,0x57,0x8A,0xAE, ++0x04,0x00,0x8C,0xAD, ++0xA4,0x57,0xC9,0xAE, ++0x04,0x00,0xAD,0xAD, ++0xAC,0x57,0xEC,0xAE, ++0xB4,0x57,0x0D,0xAF, ++0x04,0x00,0x29,0xAD, ++0x02,0x80,0x02,0x3C, ++0x00,0x1C,0x43,0x24, ++0x01,0x00,0x05,0x24, ++0x21,0x20,0x20,0x01, ++0x0F,0x00,0x06,0x24, ++0x21,0x10,0x80,0x00, ++0xFF,0xFF,0xC6,0x24, ++0x08,0x00,0x79,0xAC, ++0x00,0x00,0x63,0xAC, ++0x10,0x00,0x65,0xAC, ++0x00,0x00,0x69,0xAC, ++0x21,0x20,0x60,0x00, ++0x04,0x00,0x62,0xAC, ++0x00,0x00,0x43,0xAC, ++0x00,0x01,0x39,0x27, ++0xF5,0xFF,0xC1,0x04, ++0x18,0x00,0x63,0x24, ++0x02,0x80,0x02,0x3C, ++0xAC,0x57,0x48,0x24, ++0x02,0x80,0x03,0x3C, ++0x02,0x80,0x02,0x3C, ++0x04,0x00,0x07,0x8D, ++0x80,0x1D,0x4B,0x24, ++0x04,0x00,0x24,0xAD, ++0x00,0x1C,0x6A,0x24, ++0x02,0x00,0x09,0x24, ++0x21,0x28,0x00,0x00, ++0x0F,0x00,0x06,0x24, ++0x21,0x20,0xAB,0x00, ++0x21,0x10,0xAA,0x00, ++0xFF,0xFF,0xC6,0x24, ++0x88,0x01,0x59,0xAC, ++0x90,0x01,0x49,0xAC, ++0x18,0x00,0xA5,0x24, ++0x00,0x00,0x88,0xAC, ++0x04,0x00,0x87,0xAC, ++0x00,0x00,0xE4,0xAC, ++0x00,0x02,0x39,0x27, ++0xF5,0xFF,0xC1,0x04, ++0x21,0x38,0x80,0x00, ++0x02,0x80,0x02,0x3C, ++0xB4,0x57,0x49,0x24, ++0x02,0x80,0x03,0x3C, ++0x02,0x80,0x02,0x3C, ++0x04,0x00,0x27,0x8D, ++0x00,0x1F,0x4B,0x24, ++0x04,0x00,0x04,0xAD, ++0x00,0x1C,0x6A,0x24, ++0x03,0x00,0x08,0x24, ++0x21,0x28,0x00,0x00, ++0x01,0x00,0x06,0x24, ++0x21,0x20,0xAB,0x00, ++0x21,0x10,0xAA,0x00, ++0xFF,0xFF,0xC6,0x24, ++0x08,0x03,0x59,0xAC, ++0x10,0x03,0x48,0xAC, ++0x18,0x00,0xA5,0x24, ++0x00,0x00,0x89,0xAC, ++0x04,0x00,0x87,0xAC, ++0x00,0x00,0xE4,0xAC, ++0x00,0x08,0x39,0x27, ++0xF5,0xFF,0xC1,0x04, ++0x21,0x38,0x80,0x00, ++0x1C,0x00,0xB7,0x8F, ++0x18,0x00,0xB6,0x8F, ++0x14,0x00,0xB5,0x8F, ++0x10,0x00,0xB4,0x8F, ++0x0C,0x00,0xB3,0x8F, ++0x08,0x00,0xB2,0x8F, ++0x04,0x00,0xB1,0x8F, ++0x00,0x00,0xB0,0x8F, ++0x20,0x00,0xBD,0x27, ++0x08,0x00,0xE0,0x03, ++0x04,0x00,0x24,0xAD, ++0xD0,0xFF,0xBD,0x27, ++0x02,0x80,0x02,0x3C, ++0x20,0x00,0xB2,0xAF, ++0x02,0x80,0x03,0x3C, ++0x78,0xE8,0x52,0x24, ++0x02,0x80,0x02,0x3C, ++0x28,0x00,0xB4,0xAF, ++0x24,0x00,0xB3,0xAF, ++0x1C,0x00,0xB1,0xAF, ++0x18,0x00,0xB0,0xAF, ++0x2C,0x00,0xBF,0xAF, ++0x04,0xE8,0x73,0x24, ++0x30,0x1F,0x50,0x24, ++0x21,0x88,0x00,0x00, ++0x02,0x80,0x14,0x3C, ++0xDD,0x59,0x00,0x0C, ++0x21,0x20,0x20,0x02, ++0x1C,0x24,0x05,0x8E, ++0x6C,0x00,0x66,0x8E, ++0xE4,0xE7,0x82,0x26, ++0x6C,0x00,0x43,0x8E, ++0x1B,0x00,0x44,0x90, ++0xFF,0xF1,0x02,0x24, ++0x21,0x18,0x66,0x00, ++0x24,0x28,0xA2,0x00, ++0x00,0x21,0x04,0x00, ++0x42,0x18,0x03,0x00, ++0x00,0x02,0xA5,0x34, ++0xE8,0x23,0x03,0xAE, ++0x0C,0x24,0x04,0xAE, ++0x1C,0x24,0x05,0xAE, ++0x10,0x24,0x04,0xAE, ++0x21,0x30,0x00,0x00, ++0x21,0x10,0x06,0x02, ++0x01,0x00,0xC6,0x24, ++0x1D,0x00,0xC3,0x28, ++0x3D,0x24,0x40,0xA0, ++0x20,0x24,0x40,0xA0, ++0xFA,0xFF,0x60,0x14, ++0x5A,0x24,0x40,0xA0, ++0x01,0x00,0x31,0x26, ++0x20,0x00,0x22,0x2A, ++0x78,0x24,0x00,0xAE, ++0xE3,0xFF,0x40,0x14, ++0x94,0x00,0x10,0x26, ++0x02,0x80,0x02,0x3C, ++0x02,0x80,0x03,0x3C, ++0x30,0x1F,0x4B,0x24, ++0x02,0x80,0x02,0x3C, ++0x78,0xE8,0x6F,0x24, ++0x04,0xE8,0x4D,0x24, ++0x02,0x80,0x03,0x3C, ++0x02,0x80,0x02,0x3C, ++0xE4,0xE7,0x6E,0x24, ++0xC4,0xE7,0x4C,0x24, ++0x21,0x88,0x00,0x00, ++0x80,0x18,0x11,0x00, ++0x21,0x20,0x6D,0x00, ++0x21,0x10,0x6F,0x00, ++0x21,0x28,0x2E,0x02, ++0x21,0x30,0x2C,0x02, ++0x00,0x00,0x88,0x8C, ++0x00,0x00,0xA9,0x90, ++0x00,0x00,0xC7,0x90, ++0x00,0x00,0x4A,0x8C, ++0x21,0x10,0x2B,0x02, ++0x01,0x00,0x31,0x26, ++0x21,0x18,0x6B,0x00, ++0x1D,0x00,0x24,0x2A, ++0x60,0x05,0x68,0xAC, ++0x3E,0x05,0x47,0xA0, ++0xD4,0x05,0x6A,0xAC, ++0xEF,0xFF,0x80,0x14, ++0x04,0x05,0x49,0xA0, ++0x02,0x80,0x02,0x3C, ++0x30,0x1F,0x4A,0x24, ++0x02,0x80,0x03,0x3C, ++0x02,0x80,0x02,0x3C, ++0xA0,0xE6,0x6B,0x24, ++0x40,0xE5,0x4C,0x24, ++0x21,0x88,0x00,0x00, ++0x21,0x48,0x00,0x00, ++0x21,0x30,0x00,0x00, ++0x21,0x40,0x2A,0x01, ++0x21,0x38,0x2B,0x01, ++0x21,0x10,0xE6,0x00, ++0x91,0x00,0x44,0x90, ++0x00,0x00,0x45,0x90, ++0x21,0x18,0x06,0x01, ++0x01,0x00,0xC6,0x24, ++0x05,0x00,0xC2,0x28, ++0x39,0x04,0x64,0xA0, ++0xF8,0xFF,0x40,0x14, ++0xA8,0x03,0x65,0xA0, ++0x21,0x10,0x2C,0x02, ++0x1D,0x00,0x44,0x90, ++0x00,0x00,0x45,0x90, ++0x21,0x18,0x2A,0x02, ++0x01,0x00,0x31,0x26, ++0x1D,0x00,0x22,0x2A, ++0xE7,0x04,0x64,0xA0, ++0xCA,0x04,0x65,0xA0, ++0xEB,0xFF,0x40,0x14, ++0x05,0x00,0x29,0x25, ++0x52,0x00,0x02,0x24, ++0x10,0x00,0xA2,0xA3, ++0x41,0x00,0x03,0x24, ++0x4D,0x00,0x02,0x24, ++0x02,0x80,0x07,0x3C, ++0x64,0xF3,0xE7,0x24, ++0x11,0x00,0xA3,0xA3, ++0x12,0x00,0xA2,0xA3, ++0xE8,0x03,0x03,0x24, ++0x01,0x00,0x02,0x24, ++0x01,0x80,0x06,0x3C, ++0x10,0x00,0xA5,0x27, ++0x21,0x20,0xE0,0x00, ++0xDC,0x93,0xC6,0x24, ++0x0C,0x00,0xE3,0xAC, ++0x14,0x00,0xE2,0xA0, ++0xA2,0x23,0x00,0x0C, ++0x13,0x00,0xA0,0xA3, ++0x2C,0x00,0xBF,0x8F, ++0x28,0x00,0xB4,0x8F, ++0x24,0x00,0xB3,0x8F, ++0x20,0x00,0xB2,0x8F, ++0x1C,0x00,0xB1,0x8F, ++0x18,0x00,0xB0,0x8F, ++0x08,0x00,0xE0,0x03, ++0x30,0x00,0xBD,0x27, ++0x90,0xFF,0xBD,0x27, ++0x48,0x00,0xB0,0xAF, ++0x25,0xB0,0x10,0x3C, ++0x6C,0x00,0xBF,0xAF, ++0x68,0x00,0xBE,0xAF, ++0x64,0x00,0xB7,0xAF, ++0x58,0x00,0xB4,0xAF, ++0x54,0x00,0xB3,0xAF, ++0x50,0x00,0xB2,0xAF, ++0x4C,0x00,0xB1,0xAF, ++0x60,0x00,0xB6,0xAF, ++0x5C,0x00,0xB5,0xAF, ++0xE0,0x0E,0x02,0x36, ++0x21,0x20,0x40,0x00, ++0x00,0x00,0x42,0x8C, ++0xDC,0x0E,0x12,0x36, ++0x70,0x0E,0x13,0x36, ++0x10,0x00,0xA2,0xAF, ++0x00,0x00,0x42,0x8E, ++0x78,0x0E,0x1E,0x36, ++0x7C,0x0E,0x14,0x36, ++0x14,0x00,0xA2,0xAF, ++0x00,0x00,0x63,0x8E, ++0x25,0xB0,0x02,0x3C, ++0x74,0x0E,0x42,0x34, ++0x18,0x00,0xA3,0xAF, ++0x00,0x00,0x42,0x8C, ++0xD4,0x0E,0x10,0x36, ++0xED,0x3F,0x11,0x3C, ++0x1C,0x00,0xA2,0xAF, ++0x00,0x00,0xC3,0x8F, ++0xFB,0x92,0x25,0x36, ++0x25,0xB0,0x17,0x3C, ++0x20,0x00,0xA3,0xAF, ++0x00,0x00,0x82,0x8E, ++0x25,0xB0,0x03,0x3C, ++0x80,0x0E,0x63,0x34, ++0x24,0x00,0xA2,0xAF, ++0x00,0x00,0x63,0x8C, ++0x25,0xB0,0x02,0x3C, ++0x84,0x0E,0x42,0x34, ++0x28,0x00,0xA3,0xAF, ++0x00,0x00,0x42,0x8C, ++0x25,0xB0,0x03,0x3C, ++0x88,0x0E,0x63,0x34, ++0x2C,0x00,0xA2,0xAF, ++0x00,0x00,0x63,0x8C, ++0x25,0xB0,0x02,0x3C, ++0x8C,0x0E,0x42,0x34, ++0x30,0x00,0xA3,0xAF, ++0x00,0x00,0x42,0x8C, ++0x25,0xB0,0x03,0x3C, ++0xD0,0x0E,0x63,0x34, ++0x34,0x00,0xA2,0xAF, ++0x00,0x00,0x63,0x8C, ++0x00,0x00,0x00,0x00, ++0x38,0x00,0xA3,0xAF, ++0x00,0x00,0x02,0x8E, ++0x25,0xB0,0x03,0x3C, ++0xD8,0x0E,0x63,0x34, ++0x3C,0x00,0xA2,0xAF, ++0x00,0x00,0x63,0x8C, ++0x02,0x5C,0x00,0x0C, ++0x40,0x00,0xA3,0xAF, ++0x21,0x20,0x40,0x02, ++0x02,0x5C,0x00,0x0C, ++0xFB,0x92,0x25,0x36, ++0x21,0x20,0x60,0x02, ++0x02,0x5C,0x00,0x0C, ++0xFB,0x92,0x25,0x36, ++0x02,0x80,0x05,0x3C, ++0xC0,0xED,0xA5,0x24, ++0x00,0x00,0xA4,0x8C, ++0xFB,0x92,0x25,0x36, ++0x02,0x5C,0x00,0x0C, ++0x00,0x01,0x13,0x3C, ++0xFB,0x92,0x25,0x36, ++0x02,0x5C,0x00,0x0C, ++0x21,0x20,0xC0,0x03, ++0xFB,0x92,0x25,0x36, ++0x02,0x5C,0x00,0x0C, ++0x21,0x20,0x80,0x02, ++0x02,0x80,0x02,0x3C, ++0xC4,0xED,0x42,0x24, ++0x00,0x00,0x44,0x8C, ++0xFB,0x92,0x25,0x36, ++0x02,0x5C,0x00,0x0C, ++0xA0,0x00,0x12,0x3C, ++0x02,0x80,0x03,0x3C, ++0xC8,0xED,0x63,0x24, ++0x00,0x00,0x64,0x8C, ++0x02,0x5C,0x00,0x0C, ++0xFB,0x92,0x25,0x36, ++0x02,0x80,0x05,0x3C, ++0xCC,0xED,0xA5,0x24, ++0x00,0x00,0xA4,0x8C, ++0x02,0x5C,0x00,0x0C, ++0xFB,0x92,0x25,0x36, ++0x02,0x80,0x02,0x3C, ++0xD0,0xED,0x42,0x24, ++0x00,0x00,0x44,0x8C, ++0x02,0x5C,0x00,0x0C, ++0xFB,0x92,0x25,0x36, ++0x02,0x80,0x03,0x3C, ++0xD4,0xED,0x63,0x24, ++0x00,0x00,0x64,0x8C, ++0x02,0x5C,0x00,0x0C, ++0xFB,0x92,0x25,0x36, ++0x21,0x20,0x00,0x02, ++0x02,0x5C,0x00,0x0C, ++0xFB,0x92,0x25,0x36, ++0x02,0x80,0x05,0x3C, ++0xD8,0xED,0xA5,0x24, ++0x00,0x00,0xA4,0x8C, ++0xFB,0x92,0x25,0x36, ++0x02,0x5C,0x00,0x0C, ++0x21,0x80,0x00,0x00, ++0x14,0x02,0x11,0x3C, ++0x20,0x08,0xE4,0x36, ++0x02,0x5C,0x00,0x0C, ++0x00,0x01,0x65,0x36, ++0x28,0x08,0xE4,0x36, ++0x02,0x5C,0x00,0x0C, ++0x00,0x01,0x65,0x36, ++0x30,0x54,0x45,0x36, ++0x02,0x5C,0x00,0x0C, ++0x04,0x0C,0xE4,0x36, ++0x54,0x22,0x00,0x0C, ++0x05,0x00,0x04,0x24, ++0x08,0x00,0x05,0x3C, ++0xE4,0x00,0xA5,0x34, ++0x02,0x5C,0x00,0x0C, ++0x08,0x0C,0xE4,0x36, ++0x54,0x22,0x00,0x0C, ++0x05,0x00,0x04,0x24, ++0x80,0x80,0x05,0x3C, ++0x02,0x5C,0x00,0x0C, ++0x28,0x0E,0xE4,0x36, ++0x54,0x22,0x00,0x0C, ++0x05,0x00,0x04,0x24, ++0x02,0x01,0x25,0x36, ++0x02,0x5C,0x00,0x0C, ++0x40,0x0E,0xE4,0x36, ++0x54,0x22,0x00,0x0C, ++0x05,0x00,0x04,0x24, ++0x16,0x68,0x05,0x3C, ++0xC2,0x04,0xA5,0x34, ++0x02,0x5C,0x00,0x0C, ++0x44,0x0E,0xE4,0x36, ++0x54,0x22,0x00,0x0C, ++0x05,0x00,0x04,0x24, ++0xD1,0x28,0x05,0x24, ++0x02,0x5C,0x00,0x0C, ++0x4C,0x0E,0xE4,0x36, ++0x54,0x22,0x00,0x0C, ++0x05,0x00,0x04,0x24, ++0x02,0x01,0x25,0x36, ++0x02,0x5C,0x00,0x0C, ++0x60,0x0E,0xE4,0x36, ++0x54,0x22,0x00,0x0C, ++0x05,0x00,0x04,0x24, ++0x16,0x28,0x05,0x3C, ++0x05,0x0D,0xA5,0x34, ++0x02,0x5C,0x00,0x0C, ++0x64,0x0E,0xE4,0x36, ++0x54,0x22,0x00,0x0C, ++0x05,0x00,0x04,0x24, ++0x00,0xFB,0x05,0x3C, ++0x02,0x5C,0x00,0x0C, ++0x48,0x0E,0xE4,0x36, ++0x54,0x22,0x00,0x0C, ++0x05,0x00,0x04,0x24, ++0x00,0xF8,0x05,0x3C, ++0x02,0x5C,0x00,0x0C, ++0x48,0x0E,0xE4,0x36, ++0x54,0x22,0x00,0x0C, ++0x05,0x00,0x04,0x24, ++0x25,0x22,0x00,0x0C, ++0x02,0x00,0x04,0x24, ++0x00,0x02,0x05,0x3C, ++0xD1,0x28,0xA5,0x34, ++0x02,0x5C,0x00,0x0C, ++0x6C,0x0E,0xE4,0x36, ++0x54,0x22,0x00,0x0C, ++0x05,0x00,0x04,0x24, ++0x00,0xFB,0x05,0x3C, ++0x02,0x5C,0x00,0x0C, ++0x48,0x0E,0xE4,0x36, ++0x54,0x22,0x00,0x0C, ++0x05,0x00,0x04,0x24, ++0x00,0xF8,0x05,0x3C, ++0x02,0x5C,0x00,0x0C, ++0x48,0x0E,0xE4,0x36, ++0x25,0x22,0x00,0x0C, ++0x02,0x00,0x04,0x24, ++0x33,0x54,0x45,0x36, ++0x02,0x5C,0x00,0x0C, ++0x04,0x0C,0xE4,0x36, ++0x54,0x22,0x00,0x0C, ++0x05,0x00,0x04,0x24, ++0xE4,0x00,0x05,0x24, ++0x02,0x5C,0x00,0x0C, ++0x08,0x0C,0xE4,0x36, ++0x54,0x22,0x00,0x0C, ++0x05,0x00,0x04,0x24, ++0x28,0x0E,0xE4,0x36, ++0x02,0x5C,0x00,0x0C, ++0x21,0x28,0x00,0x00, ++0x20,0x08,0xE4,0x36, ++0x02,0x5C,0x00,0x0C, ++0x00,0x01,0x05,0x3C, ++0x28,0x08,0xE4,0x36, ++0x02,0x5C,0x00,0x0C, ++0x00,0x01,0x05,0x3C, ++0x25,0xB0,0x02,0x3C, ++0xAC,0x0E,0x42,0x34, ++0x00,0x00,0x5E,0x8C, ++0x00,0xD8,0x02,0x3C, ++0x24,0x10,0xC2,0x03, ++0x37,0x00,0x40,0x10, ++0x01,0x00,0x10,0x26, ++0x0A,0x00,0x02,0x2E, ++0x97,0xFF,0x40,0x14, ++0x00,0x00,0x00,0x00, ++0x10,0x00,0xA5,0x8F, ++0x25,0xB0,0x10,0x3C, ++0x02,0x5C,0x00,0x0C, ++0xE0,0x0E,0x04,0x36, ++0x14,0x00,0xA5,0x8F, ++0x02,0x5C,0x00,0x0C, ++0xDC,0x0E,0x04,0x36, ++0x18,0x00,0xA5,0x8F, ++0x02,0x5C,0x00,0x0C, ++0x70,0x0E,0x04,0x36, ++0x1C,0x00,0xA5,0x8F, ++0x02,0x5C,0x00,0x0C, ++0x74,0x0E,0x04,0x36, ++0x20,0x00,0xA5,0x8F, ++0x02,0x5C,0x00,0x0C, ++0x78,0x0E,0x04,0x36, ++0x24,0x00,0xA5,0x8F, ++0x02,0x5C,0x00,0x0C, ++0x7C,0x0E,0x04,0x36, ++0x28,0x00,0xA5,0x8F, ++0x02,0x5C,0x00,0x0C, ++0x80,0x0E,0x04,0x36, ++0x2C,0x00,0xA5,0x8F, ++0x02,0x5C,0x00,0x0C, ++0x84,0x0E,0x04,0x36, ++0x30,0x00,0xA5,0x8F, ++0x02,0x5C,0x00,0x0C, ++0x88,0x0E,0x04,0x36, ++0x34,0x00,0xA5,0x8F, ++0x02,0x5C,0x00,0x0C, ++0x8C,0x0E,0x04,0x36, ++0x38,0x00,0xA5,0x8F, ++0x02,0x5C,0x00,0x0C, ++0xD0,0x0E,0x04,0x36, ++0x3C,0x00,0xA5,0x8F, ++0x02,0x5C,0x00,0x0C, ++0xD4,0x0E,0x04,0x36, ++0x40,0x00,0xA5,0x8F, ++0x88,0x0E,0x04,0x36, ++0x6C,0x00,0xBF,0x8F, ++0x68,0x00,0xBE,0x8F, ++0x64,0x00,0xB7,0x8F, ++0x60,0x00,0xB6,0x8F, ++0x5C,0x00,0xB5,0x8F, ++0x58,0x00,0xB4,0x8F, ++0x54,0x00,0xB3,0x8F, ++0x50,0x00,0xB2,0x8F, ++0x4C,0x00,0xB1,0x8F, ++0x48,0x00,0xB0,0x8F, ++0x02,0x5C,0x00,0x08, ++0x70,0x00,0xBD,0x27, ++0x80,0x0C,0xF1,0x36, ++0x94,0x0E,0xE3,0x36, ++0x00,0x00,0x24,0x8E, ++0x00,0x00,0x62,0x8C, ++0xFF,0x03,0x03,0x3C, ++0xFF,0x03,0x95,0x30, ++0x24,0x10,0x43,0x00, ++0x02,0x14,0x02,0x00, ++0x18,0x00,0x55,0x00, ++0x02,0x80,0x10,0x3C, ++0x30,0x1F,0x10,0x26, ++0x0C,0x00,0x02,0x8E, ++0x00,0xFC,0x12,0x24, ++0x00,0x00,0x3E,0x8E, ++0x24,0x10,0x52,0x00, ++0x21,0x20,0x20,0x02, ++0x24,0x30,0xD2,0x03, ++0xFF,0xFF,0x13,0x3C, ++0xFF,0x03,0x73,0x36, ++0x12,0x18,0x00,0x00, ++0x02,0x1A,0x03,0x00, ++0xFF,0x03,0x63,0x30, ++0x25,0x10,0x43,0x00, ++0xFF,0x03,0x45,0x30, ++0x25,0x28,0xC5,0x00, ++0x02,0x5C,0x00,0x0C, ++0x0C,0x00,0x02,0xAE, ++0x54,0x22,0x00,0x0C, ++0x05,0x00,0x04,0x24, ++0x9C,0x0E,0xE3,0x36, ++0x00,0x00,0x62,0x8C, ++0xFF,0x03,0x03,0x3C, ++0x0C,0x00,0x06,0x8E, ++0x24,0x10,0x43,0x00, ++0x02,0xB4,0x02,0x00, ++0x18,0x00,0xD5,0x02, ++0xF0,0xFF,0x02,0x3C, ++0xFF,0x03,0x42,0x34, ++0x24,0x30,0xC2,0x00, ++0x00,0x00,0x3E,0x8E, ++0xC0,0xFF,0x04,0x3C, ++0xFF,0xFF,0x84,0x34, ++0x24,0x10,0xC4,0x03, ++0x21,0x20,0x20,0x02, ++0xFF,0x0F,0x11,0x3C, ++0xFF,0xFF,0x31,0x36, ++0x12,0x18,0x00,0x00, ++0x02,0x1A,0x03,0x00, ++0xFF,0x03,0x63,0x30, ++0x80,0x1A,0x03,0x00, ++0x25,0x30,0xC3,0x00, ++0x82,0x2A,0x06,0x00, ++0x3F,0x00,0xA5,0x30, ++0x00,0x2C,0x05,0x00, ++0x0C,0x00,0x06,0xAE, ++0x02,0x5C,0x00,0x0C, ++0x25,0x28,0x45,0x00, ++0x94,0x0C,0xE4,0x36, ++0x00,0x00,0x9E,0x8C, ++0x82,0x29,0x16,0x00, ++0x00,0x2F,0x05,0x00, ++0x24,0x10,0xD1,0x03, ++0x02,0x5C,0x00,0x0C, ++0x25,0x28,0x45,0x00, ++0x54,0x22,0x00,0x0C, ++0x05,0x00,0x04,0x24, ++0x25,0xB0,0x05,0x3C, ++0xA4,0x0E,0xE3,0x36, ++0x14,0x0C,0xA5,0x34, ++0x00,0x00,0xBE,0x8C, ++0x00,0x00,0x62,0x8C, ++0xFF,0x03,0x05,0x3C, ++0x02,0x80,0x03,0x3C, ++0xDC,0xED,0x63,0x24, ++0x24,0x10,0x45,0x00, ++0x00,0x00,0x64,0x8C, ++0x02,0x14,0x02,0x00, ++0x24,0x18,0xD2,0x03, ++0x25,0xF0,0x62,0x00, ++0x02,0x5C,0x00,0x0C, ++0x21,0x28,0xC0,0x03, ++0x25,0xB0,0x02,0x3C, ++0xAC,0x0E,0x42,0x34, ++0x00,0x00,0x45,0x8C, ++0x3F,0x00,0x03,0x3C, ++0x24,0x10,0xD3,0x03, ++0x24,0x28,0xA3,0x00, ++0x82,0x29,0x05,0x00, ++0x25,0x28,0x45,0x00, ++0x02,0x80,0x02,0x3C, ++0xDC,0xED,0x42,0x24, ++0x00,0x00,0x44,0x8C, ++0x02,0x5C,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0x54,0x22,0x00,0x0C, ++0x05,0x00,0x04,0x24, ++0x25,0xB0,0x05,0x3C, ++0xB4,0x0E,0xE3,0x36, ++0x88,0x0C,0xA5,0x34, ++0x00,0x00,0xA4,0x8C, ++0x00,0x00,0x62,0x8C, ++0xFF,0x03,0x03,0x3C, ++0xFF,0x03,0x95,0x30, ++0x24,0x10,0x43,0x00, ++0x02,0x14,0x02,0x00, ++0x18,0x00,0x55,0x00, ++0x0C,0x00,0x06,0x8E, ++0x00,0x00,0xBE,0x8C, ++0x02,0x80,0x02,0x3C, ++0x24,0x30,0xD2,0x00, ++0xE0,0xED,0x42,0x24, ++0x00,0x00,0x44,0x8C, ++0x24,0x10,0xD2,0x03, ++0x12,0x18,0x00,0x00, ++0x02,0x1A,0x03,0x00, ++0xFF,0x03,0x63,0x30, ++0x25,0x30,0xC3,0x00, ++0xFF,0x03,0xC5,0x30, ++0x25,0x28,0x45,0x00, ++0x02,0x5C,0x00,0x0C, ++0x0C,0x00,0x06,0xAE, ++0x54,0x22,0x00,0x0C, ++0x05,0x00,0x04,0x24, ++0xBC,0x0E,0xE2,0x36, ++0x00,0x00,0x43,0x8C, ++0xFF,0x03,0x05,0x3C, ++0x0C,0x00,0x06,0x8E, ++0x24,0x18,0x65,0x00, ++0x02,0xB4,0x03,0x00, ++0x18,0x00,0xD5,0x02, ++0x25,0xB0,0x04,0x3C, ++0x88,0x0C,0x84,0x34, ++0xF0,0xFF,0x03,0x3C, ++0x00,0x00,0x9E,0x8C, ++0xFF,0x03,0x63,0x34, ++0x24,0x30,0xC3,0x00, ++0xC0,0xFF,0x04,0x3C, ++0x02,0x80,0x05,0x3C, ++0xFF,0xFF,0x84,0x34, ++0xE0,0xED,0xA5,0x24, ++0x24,0xF0,0xC4,0x03, ++0x00,0x00,0xA4,0x8C, ++0x44,0x00,0xBE,0xAF, ++0x12,0x10,0x00,0x00, ++0x02,0x12,0x02,0x00, ++0xFF,0x03,0x42,0x30, ++0x80,0x12,0x02,0x00, ++0x25,0x30,0xC2,0x00, ++0x82,0x2A,0x06,0x00, ++0x3F,0x00,0xA5,0x30, ++0x00,0x2C,0x05,0x00, ++0x0C,0x00,0x06,0xAE, ++0x02,0x5C,0x00,0x0C, ++0x25,0x28,0xC5,0x03, ++0x9C,0x0C,0xE4,0x36, ++0x00,0x00,0x9E,0x8C, ++0x82,0x29,0x16,0x00, ++0x00,0x2F,0x05,0x00, ++0x24,0x88,0xD1,0x03, ++0x02,0x5C,0x00,0x0C, ++0x25,0x28,0x25,0x02, ++0x54,0x22,0x00,0x0C, ++0x05,0x00,0x04,0x24, ++0x25,0xB0,0x02,0x3C, ++0xC4,0x0E,0xE3,0x36, ++0x1C,0x0C,0x42,0x34, ++0x00,0x00,0x5E,0x8C, ++0x00,0x00,0x62,0x8C, ++0xFF,0x03,0x05,0x3C, ++0x02,0x80,0x03,0x3C, ++0xE4,0xED,0x63,0x24, ++0x24,0x10,0x45,0x00, ++0x00,0x00,0x64,0x8C, ++0x02,0x14,0x02,0x00, ++0x24,0x90,0xD2,0x03, ++0x25,0xF0,0x42,0x02, ++0x02,0x5C,0x00,0x0C, ++0x21,0x28,0xC0,0x03, ++0xCC,0x0E,0xE2,0x36, ++0x00,0x00,0x45,0x8C, ++0x02,0x80,0x02,0x3C, ++0xE4,0xED,0x42,0x24, ++0x3F,0x00,0x03,0x3C, ++0x00,0x00,0x44,0x8C, ++0x24,0x28,0xA3,0x00, ++0x24,0x98,0xD3,0x03, ++0x82,0x29,0x05,0x00, ++0x02,0x5C,0x00,0x0C, ++0x25,0x28,0x65,0x02, ++0x54,0x22,0x00,0x0C, ++0x05,0x00,0x04,0x24, ++0x5C,0x6D,0x00,0x08, ++0x00,0x00,0x00,0x00, ++0xE0,0xFF,0xBD,0x27, ++0x02,0x80,0x02,0x3C, ++0x42,0x00,0x03,0x24, ++0x10,0x00,0xA3,0xA3, ++0xF1,0x3A,0x40,0xA0, ++0x4E,0x00,0x03,0x24, ++0x43,0x00,0x02,0x24, ++0x02,0x80,0x07,0x3C, ++0x9C,0xF3,0xE7,0x24, ++0x11,0x00,0xA2,0xA3, ++0x12,0x00,0xA3,0xA3, ++0xD0,0x07,0x02,0x24, ++0x01,0x00,0x03,0x24, ++0x01,0x80,0x06,0x3C, ++0x10,0x00,0xA5,0x27, ++0x21,0x20,0xE0,0x00, ++0xDC,0xAC,0xC6,0x24, ++0x0C,0x00,0xE2,0xAC, ++0x14,0x00,0xE3,0xA0, ++0x18,0x00,0xBF,0xAF, ++0xA2,0x23,0x00,0x0C, ++0x13,0x00,0xA0,0xA3, ++0x18,0x00,0xBF,0x8F, ++0x00,0x00,0x00,0x00, ++0x08,0x00,0xE0,0x03, ++0x20,0x00,0xBD,0x27, ++0x02,0x80,0x02,0x3C, ++0x48,0xFD,0xBD,0x27, ++0xE8,0xED,0x46,0x24, ++0x02,0x80,0x03,0x3C, ++0xB0,0x02,0xB2,0xAF, ++0xAC,0x02,0xB1,0xAF, ++0xA8,0x02,0xB0,0xAF, ++0x33,0x1F,0x60,0xA0, ++0x21,0x38,0xA0,0x03, ++0x90,0x00,0xC8,0x24, ++0x00,0x00,0xC2,0x8C, ++0x04,0x00,0xC3,0x8C, ++0x08,0x00,0xC4,0x8C, ++0x0C,0x00,0xC5,0x8C, ++0x10,0x00,0xC6,0x24, ++0x00,0x00,0xE2,0xAC, ++0x04,0x00,0xE3,0xAC, ++0x08,0x00,0xE4,0xAC, ++0x0C,0x00,0xE5,0xAC, ++0xF6,0xFF,0xC8,0x14, ++0x10,0x00,0xE7,0x24, ++0x00,0x00,0xC3,0x8C, ++0x02,0x80,0x02,0x3C, ++0x7C,0xEE,0x58,0x24, ++0x00,0x00,0xE3,0xAC, ++0x98,0x00,0xB9,0x27, ++0x00,0x01,0x12,0x27, ++0x01,0x00,0x02,0x93, ++0x05,0x00,0x03,0x93, ++0x09,0x00,0x04,0x93, ++0x0D,0x00,0x05,0x93, ++0x00,0x00,0x11,0x93, ++0x02,0x00,0x0D,0x93, ++0x04,0x00,0x10,0x93, ++0x06,0x00,0x0C,0x93, ++0x08,0x00,0x0F,0x93, ++0x0A,0x00,0x07,0x93, ++0x0C,0x00,0x0E,0x93, ++0x0E,0x00,0x06,0x93, ++0x03,0x00,0x08,0x93, ++0x07,0x00,0x09,0x93, ++0x0B,0x00,0x0A,0x93, ++0x0F,0x00,0x0B,0x93, ++0x00,0x12,0x02,0x00, ++0x00,0x1A,0x03,0x00, ++0x00,0x22,0x04,0x00, ++0x00,0x2A,0x05,0x00, ++0x25,0x10,0x51,0x00, ++0x25,0x18,0x70,0x00, ++0x25,0x20,0x8F,0x00, ++0x25,0x28,0xAE,0x00, ++0x00,0x6C,0x0D,0x00, ++0x00,0x64,0x0C,0x00, ++0x00,0x3C,0x07,0x00, ++0x00,0x34,0x06,0x00, ++0x25,0x68,0xA2,0x01, ++0x25,0x60,0x83,0x01, ++0x25,0x38,0xE4,0x00, ++0x25,0x30,0xC5,0x00, ++0x00,0x46,0x08,0x00, ++0x00,0x4E,0x09,0x00, ++0x00,0x56,0x0A,0x00, ++0x00,0x5E,0x0B,0x00, ++0x25,0x40,0x0D,0x01, ++0x25,0x48,0x2C,0x01, ++0x25,0x50,0x47,0x01, ++0x25,0x58,0x66,0x01, ++0x10,0x00,0x18,0x27, ++0x00,0x00,0x28,0xAF, ++0x04,0x00,0x29,0xAF, ++0x08,0x00,0x2A,0xAF, ++0x0C,0x00,0x2B,0xAF, ++0xD2,0xFF,0x12,0x17, ++0x10,0x00,0x39,0x27, ++0x01,0x00,0x02,0x93, ++0x05,0x00,0x03,0x93, ++0x00,0x00,0x09,0x93, ++0x02,0x00,0x04,0x93, ++0x04,0x00,0x08,0x93, ++0x06,0x00,0x05,0x93, ++0x07,0x00,0x06,0x93, ++0x03,0x00,0x07,0x93, ++0x00,0x12,0x02,0x00, ++0x00,0x1A,0x03,0x00, ++0x25,0x10,0x49,0x00, ++0x25,0x18,0x68,0x00, ++0x00,0x24,0x04,0x00, ++0x00,0x2C,0x05,0x00, ++0x25,0x20,0x82,0x00, ++0x25,0x28,0xA3,0x00, ++0x00,0x3E,0x07,0x00, ++0x00,0x36,0x06,0x00, ++0x02,0x80,0x02,0x3C, ++0x25,0x38,0xE4,0x00, ++0x25,0x30,0xC5,0x00, ++0x84,0xEF,0x58,0x24, ++0x04,0x00,0x26,0xAF, ++0x00,0x00,0x27,0xAF, ++0x00,0x01,0x12,0x27, ++0xA0,0x01,0xB9,0x27, ++0x01,0x00,0x02,0x93, ++0x05,0x00,0x03,0x93, ++0x09,0x00,0x04,0x93, ++0x0D,0x00,0x05,0x93, ++0x00,0x00,0x11,0x93, ++0x02,0x00,0x0D,0x93, ++0x04,0x00,0x10,0x93, ++0x06,0x00,0x0C,0x93, ++0x08,0x00,0x0F,0x93, ++0x0A,0x00,0x07,0x93, ++0x0C,0x00,0x0E,0x93, ++0x0E,0x00,0x06,0x93, ++0x03,0x00,0x08,0x93, ++0x07,0x00,0x09,0x93, ++0x0B,0x00,0x0A,0x93, ++0x0F,0x00,0x0B,0x93, ++0x00,0x12,0x02,0x00, ++0x00,0x1A,0x03,0x00, ++0x00,0x22,0x04,0x00, ++0x00,0x2A,0x05,0x00, ++0x25,0x10,0x51,0x00, ++0x25,0x18,0x70,0x00, ++0x25,0x20,0x8F,0x00, ++0x25,0x28,0xAE,0x00, ++0x00,0x6C,0x0D,0x00, ++0x00,0x64,0x0C,0x00, ++0x00,0x3C,0x07,0x00, ++0x00,0x34,0x06,0x00, ++0x25,0x68,0xA2,0x01, ++0x25,0x60,0x83,0x01, ++0x25,0x38,0xE4,0x00, ++0x25,0x30,0xC5,0x00, ++0x00,0x46,0x08,0x00, ++0x00,0x4E,0x09,0x00, ++0x00,0x56,0x0A,0x00, ++0x00,0x5E,0x0B,0x00, ++0x25,0x40,0x0D,0x01, ++0x25,0x48,0x2C,0x01, ++0x25,0x50,0x47,0x01, ++0x25,0x58,0x66,0x01, ++0x10,0x00,0x18,0x27, ++0x00,0x00,0x28,0xAF, ++0x04,0x00,0x29,0xAF, ++0x08,0x00,0x2A,0xAF, ++0x0C,0x00,0x2B,0xAF, ++0xD2,0xFF,0x12,0x17, ++0x10,0x00,0x39,0x27, ++0x01,0x00,0x02,0x93, ++0x05,0x00,0x03,0x93, ++0x00,0x00,0x09,0x93, ++0x02,0x00,0x04,0x93, ++0x04,0x00,0x08,0x93, ++0x06,0x00,0x05,0x93, ++0x07,0x00,0x06,0x93, ++0x03,0x00,0x07,0x93, ++0x00,0x12,0x02,0x00, ++0x00,0x1A,0x03,0x00, ++0x25,0x10,0x49,0x00, ++0x25,0x18,0x68,0x00, ++0x00,0x24,0x04,0x00, ++0x00,0x2C,0x05,0x00, ++0x25,0x20,0x82,0x00, ++0x25,0x28,0xA3,0x00, ++0x00,0x3E,0x07,0x00, ++0x00,0x36,0x06,0x00, ++0x25,0x30,0xC5,0x00, ++0x25,0x38,0xE4,0x00, ++0x02,0x80,0x02,0x3C, ++0x04,0x00,0x26,0xAF, ++0x00,0x00,0x27,0xAF, ++0x30,0x1F,0x46,0x24, ++0x21,0x50,0x00,0x00, ++0x80,0x20,0x0A,0x00, ++0x21,0x10,0x9D,0x00, ++0x00,0x00,0x45,0x8C, ++0x01,0x00,0x43,0x25, ++0xFF,0x00,0x6A,0x30, ++0x21,0x20,0x86,0x00, ++0x25,0x00,0x42,0x2D, ++0xF8,0xFF,0x40,0x14, ++0x18,0x00,0x85,0xAC, ++0x02,0x80,0x02,0x3C, ++0x30,0x1F,0x4B,0x24, ++0x21,0x50,0x00,0x00, ++0xC0,0x10,0x0A,0x00, ++0x21,0x48,0x5D,0x00, ++0x21,0x38,0x00,0x00, ++0x21,0x40,0x4B,0x00, ++0x21,0x10,0x27,0x01, ++0xA0,0x01,0x46,0x90, ++0x98,0x00,0x45,0x90, ++0x01,0x00,0xE4,0x24, ++0x21,0x18,0x07,0x01, ++0xFF,0x00,0x87,0x30, ++0x08,0x00,0xE2,0x2C, ++0xB4,0x01,0x66,0xA0, ++0xF7,0xFF,0x40,0x14, ++0xAC,0x00,0x65,0xA0, ++0x01,0x00,0x42,0x25, ++0xFF,0x00,0x4A,0x30, ++0x21,0x00,0x43,0x2D, ++0xEF,0xFF,0x60,0x14, ++0xC0,0x10,0x0A,0x00, ++0x08,0x00,0x64,0x8D, ++0xFF,0x7F,0x07,0x3C, ++0xFF,0xFF,0xE7,0x34, ++0xC0,0xFF,0x02,0x24, ++0x24,0x20,0x87,0x00, ++0x24,0x20,0x82,0x00, ++0x0C,0x00,0x84,0x34, ++0xFF,0xC0,0x02,0x24, ++0x24,0x20,0x82,0x00, ++0xC0,0xFF,0x02,0x3C, ++0xFF,0xFF,0x42,0x34, ++0x00,0x18,0x84,0x34, ++0xBF,0xFF,0x03,0x3C, ++0x24,0x20,0x82,0x00, ++0xFF,0xFF,0x63,0x34, ++0x7F,0xFF,0x02,0x3C, ++0x24,0x20,0x83,0x00, ++0xFF,0xFF,0x42,0x34, ++0x24,0x20,0x82,0x00, ++0x0C,0x00,0x65,0x8D, ++0x7F,0xFF,0x03,0x24, ++0x40,0x40,0x84,0x34, ++0xFF,0xFF,0x02,0x3C, ++0x24,0x20,0x83,0x00, ++0xFF,0x7F,0x42,0x34, ++0xFF,0xBF,0x03,0x3C, ++0x10,0x00,0x66,0x8D, ++0x24,0x20,0x82,0x00, ++0xFF,0xFF,0x63,0x34, ++0xFF,0x9F,0x02,0x3C, ++0x24,0x28,0xA3,0x00, ++0xFF,0xFF,0x42,0x34, ++0xFF,0x3F,0x03,0x3C, ++0x24,0x20,0x82,0x00, ++0xFF,0xFF,0x63,0x34, ++0x12,0x00,0x02,0x24, ++0xB0,0x02,0xB2,0x8F, ++0xAC,0x02,0xB1,0x8F, ++0xA8,0x02,0xB0,0x8F, ++0x24,0x30,0xC3,0x00, ++0xC7,0x02,0x62,0xA1, ++0x1F,0x00,0x03,0x24, ++0x01,0x00,0x02,0x24, ++0x24,0x28,0xA7,0x00, ++0xBE,0x02,0x63,0xA1, ++0xC0,0x02,0x62,0xA1, ++0xFF,0x00,0x03,0x24, ++0xFF,0xFF,0x02,0x24, ++0xB8,0x02,0xBD,0x27, ++0x08,0x00,0x64,0xAD, ++0x10,0x00,0x66,0xAD, ++0x0C,0x00,0x65,0xAD, ++0xC2,0x02,0x62,0xA1, ++0xC4,0x02,0x63,0xA5, ++0xBF,0x02,0x60,0xA1, ++0x08,0x00,0xE0,0x03, ++0xC6,0x02,0x60,0xA1, ++0x02,0x80,0x0B,0x3C, ++0x30,0x1F,0x67,0x25, ++0xE0,0xFF,0xBD,0x27, ++0xE6,0x02,0xE0,0xA0, ++0x18,0x00,0xBF,0xAF, ++0xE4,0x02,0xE8,0x8C, ++0xFF,0xCF,0x02,0x3C, ++0xFF,0xFF,0x42,0x34, ++0x30,0x1F,0x69,0x8D, ++0x24,0x40,0x02,0x01, ++0xFF,0xBF,0x02,0x3C, ++0xFF,0xFF,0x42,0x34, ++0xF0,0xFF,0x03,0x24, ++0x24,0x40,0x02,0x01, ++0xFF,0x7F,0x02,0x3C, ++0x24,0x48,0x23,0x01, ++0xFF,0xFF,0x42,0x34, ++0xFF,0xF0,0x03,0x24, ++0x24,0x48,0x23,0x01, ++0x24,0x40,0x02,0x01, ++0x20,0x00,0x03,0x24, ++0x0A,0x00,0x02,0x24, ++0x30,0x1F,0x69,0xAD, ++0xD2,0x02,0xE2,0xA0, ++0xD7,0x02,0xE3,0xA0, ++0x20,0x00,0x02,0x24, ++0x00,0x01,0x03,0x24, ++0xC8,0x02,0xE2,0xA4, ++0xCA,0x02,0xE3,0xA4, ++0x00,0x02,0x02,0x24, ++0x49,0x00,0x03,0x24, ++0x02,0x80,0x0A,0x3C, ++0xE4,0x02,0xE8,0xAC, ++0x80,0xF3,0x4A,0x25, ++0xFF,0xFF,0x0D,0x34, ++0x3E,0x00,0x0E,0x24, ++0x1C,0x00,0x0F,0x24, ++0x01,0x00,0x0C,0x24, ++0x11,0x00,0xA3,0xA3, ++0xCC,0x02,0xE2,0xA4, ++0xD0,0x07,0x03,0x24, ++0x44,0x00,0x02,0x24, ++0x01,0x80,0x06,0x3C, ++0x10,0x00,0xA2,0xA3, ++0x10,0x00,0xA5,0x27, ++0x47,0x00,0x02,0x24, ++0x21,0x20,0x40,0x01, ++0x94,0xAD,0xC6,0x24, ++0x04,0x00,0xED,0xAC, ++0xD0,0x02,0xEE,0xA0, ++0xD1,0x02,0xEF,0xA0, ++0x02,0x00,0xEC,0xA0, ++0x0C,0x00,0x43,0xAD, ++0x14,0x00,0x4C,0xA1, ++0x80,0x36,0xED,0xAC, ++0xCE,0x02,0xEE,0xA0, ++0xCF,0x02,0xEF,0xA0, ++0xD6,0x02,0xE0,0xA0, ++0xD4,0x02,0xE0,0xA0, ++0x12,0x00,0xA2,0xA3, ++0xA2,0x23,0x00,0x0C, ++0x13,0x00,0xA0,0xA3, ++0x18,0x00,0xBF,0x8F, ++0x00,0x00,0x00,0x00, ++0x08,0x00,0xE0,0x03, ++0x20,0x00,0xBD,0x27, ++0xE0,0xFF,0xBD,0x27, ++0x02,0x80,0x02,0x3C, ++0x50,0x00,0x03,0x24, ++0x10,0x00,0xA3,0xA3, ++0x16,0x3D,0x40,0xA0, ++0x41,0x00,0x03,0x24, ++0x52,0x00,0x02,0x24, ++0x02,0x80,0x07,0x3C, ++0x0C,0xF4,0xE7,0x24, ++0x11,0x00,0xA2,0xA3, ++0x12,0x00,0xA3,0xA3, ++0xD0,0x07,0x02,0x24, ++0x01,0x00,0x03,0x24, ++0x02,0x80,0x06,0x3C, ++0x10,0x00,0xA5,0x27, ++0x21,0x20,0xE0,0x00, ++0x2C,0x80,0xC6,0x24, ++0x0C,0x00,0xE2,0xAC, ++0x14,0x00,0xE3,0xA0, ++0x18,0x00,0xBF,0xAF, ++0xA2,0x23,0x00,0x0C, ++0x13,0x00,0xA0,0xA3, ++0x18,0x00,0xBF,0x8F, ++0x00,0x00,0x00,0x00, ++0x08,0x00,0xE0,0x03, ++0x20,0x00,0xBD,0x27, ++0x02,0x80,0x09,0x3C, ++0x30,0x1F,0x23,0x8D, ++0xFF,0xFF,0x02,0x24, ++0xFF,0x00,0x4B,0x30, ++0x0F,0xFF,0x02,0x24, ++0x24,0x18,0x62,0x00, ++0xFF,0xFF,0x02,0x3C, ++0xFF,0x0F,0x42,0x34, ++0x24,0x18,0x62,0x00, ++0xD8,0xFF,0xBD,0x27, ++0x30,0x1F,0x23,0xAD, ++0x47,0x00,0x02,0x24, ++0x3B,0x00,0x03,0x24, ++0x02,0x80,0x08,0x3C, ++0x28,0xF4,0x08,0x25, ++0x18,0x00,0xB0,0xAF, ++0x10,0x00,0xA2,0xA3, ++0x30,0x1F,0x30,0x25, ++0x11,0x00,0xA3,0xA3, ++0xD0,0x07,0x02,0x24, ++0x01,0x00,0x03,0x24, ++0x01,0x00,0x07,0x3C, ++0x01,0x80,0x06,0x3C, ++0x04,0x03,0x0B,0xAE, ++0x1C,0x00,0xB1,0xAF, ++0x56,0x30,0xEA,0x34, ++0x43,0x00,0x11,0x24, ++0xF4,0x98,0xE7,0x34, ++0x10,0x00,0xA5,0x27, ++0x0C,0x00,0x02,0xAD, ++0x14,0x00,0x03,0xA1, ++0x21,0x20,0x00,0x01, ++0x1C,0xB9,0xC6,0x24, ++0x20,0x00,0xBF,0xAF, ++0x12,0x00,0xB1,0xA3, ++0x0C,0x03,0x07,0xAE, ++0x10,0x03,0x0A,0xAE, ++0x13,0x00,0xA0,0xA3, ++0x08,0x03,0x00,0xAE, ++0x14,0x03,0x00,0xAE, ++0xA2,0x23,0x00,0x0C, ++0x18,0x03,0x00,0xAE, ++0x1E,0x00,0x02,0x24, ++0x21,0x03,0x02,0xA2, ++0x4A,0x00,0x03,0x24, ++0x45,0x00,0x02,0x24, ++0x1C,0x03,0x03,0xA2, ++0x1D,0x03,0x02,0xA2, ++0x23,0x00,0x03,0x24, ++0x3E,0x00,0x02,0x24, ++0x1E,0x03,0x11,0xA2, ++0x1F,0x03,0x02,0xA2, ++0x20,0x03,0x03,0xA2, ++0x20,0x00,0xBF,0x8F, ++0x1C,0x00,0xB1,0x8F, ++0x18,0x00,0xB0,0x8F, ++0x08,0x00,0xE0,0x03, ++0x28,0x00,0xBD,0x27, ++0xE0,0xFF,0xBD,0x27, ++0x3B,0x00,0x02,0x24, ++0x43,0x00,0x03,0x24, ++0x10,0x00,0xA2,0xA3, ++0x11,0x00,0xA3,0xA3, ++0x36,0x00,0x02,0x24, ++0x02,0x80,0x03,0x3C, ++0x02,0x80,0x07,0x3C, ++0x44,0xF4,0xE7,0x24, ++0x12,0x00,0xA2,0xA3, ++0x03,0x22,0x60,0xA0, ++0xD0,0x07,0x02,0x24, ++0x01,0x00,0x03,0x24, ++0x01,0x80,0x06,0x3C, ++0x10,0x00,0xA5,0x27, ++0x21,0x20,0xE0,0x00, ++0x50,0xBD,0xC6,0x24, ++0x0C,0x00,0xE2,0xAC, ++0x14,0x00,0xE3,0xA0, ++0x18,0x00,0xBF,0xAF, ++0xA2,0x23,0x00,0x0C, ++0x13,0x00,0xA0,0xA3, ++0x18,0x00,0xBF,0x8F, ++0x00,0x00,0x00,0x00, ++0x08,0x00,0xE0,0x03, ++0x20,0x00,0xBD,0x27, ++0xE0,0xFF,0xBD,0x27, ++0x02,0x80,0x02,0x3C, ++0x52,0x00,0x03,0x24, ++0x10,0x00,0xA3,0xA3, ++0xB8,0x55,0x40,0xA4, ++0x54,0x00,0x03,0x24, ++0x53,0x00,0x02,0x24, ++0x02,0x80,0x07,0x3C, ++0x7C,0xF4,0xE7,0x24, ++0x11,0x00,0xA2,0xA3, ++0x12,0x00,0xA3,0xA3, ++0xF4,0x01,0x02,0x24, ++0x01,0x00,0x03,0x24, ++0x02,0x80,0x06,0x3C, ++0x10,0x00,0xA5,0x27, ++0x21,0x20,0xE0,0x00, ++0x70,0x81,0xC6,0x24, ++0x0C,0x00,0xE2,0xAC, ++0x14,0x00,0xE3,0xA0, ++0x18,0x00,0xBF,0xAF, ++0xA2,0x23,0x00,0x0C, ++0x13,0x00,0xA0,0xA3, ++0x18,0x00,0xBF,0x8F, ++0x00,0x00,0x00,0x00, ++0x08,0x00,0xE0,0x03, ++0x20,0x00,0xBD,0x27, ++0xD8,0xFF,0xBD,0x27, ++0x02,0x80,0x03,0x3C, ++0x20,0x00,0xBF,0xAF, ++0x1C,0x00,0xB1,0xAF, ++0x18,0x00,0xB0,0xAF, ++0x58,0xE9,0x62,0x24, ++0x58,0xE9,0x67,0x94, ++0x02,0x00,0x48,0x90, ++0x02,0x80,0x02,0x3C, ++0xD8,0x5E,0x42,0x24, ++0x02,0x00,0x11,0x24, ++0x01,0x80,0x06,0x3C, ++0x21,0x20,0x40,0x00, ++0x14,0x00,0x51,0xA0, ++0x10,0x00,0xA5,0x27, ++0x6C,0xCE,0xC6,0x24, ++0x02,0x80,0x10,0x3C, ++0x10,0x00,0xA7,0xA7, ++0x28,0x5F,0x10,0x26, ++0x12,0x00,0xA8,0xA3, ++0xA2,0x23,0x00,0x0C, ++0x13,0x00,0xA0,0xA3, ++0x02,0x80,0x06,0x3C, ++0x21,0x20,0x00,0x02, ++0x10,0x00,0xA5,0x27, ++0x14,0x00,0x11,0xA2, ++0xA2,0x23,0x00,0x0C, ++0x7C,0x82,0xC6,0x24, ++0x02,0x80,0x03,0x3C, ++0xDE,0x5D,0x62,0x90, ++0x02,0x00,0x07,0x24, ++0x0C,0x00,0x04,0x24, ++0x02,0x00,0x42,0x30, ++0x01,0x00,0x42,0x2C, ++0x23,0x38,0xE2,0x00, ++0xE8,0x03,0x02,0x24, ++0x0C,0x00,0x02,0xAE, ++0x02,0x80,0x03,0x3C, ++0x02,0x80,0x02,0x3C, ++0xF4,0x5E,0x60,0xA0, ++0xF5,0x5E,0x44,0xA0, ++0x02,0x80,0x03,0x3C, ++0x02,0x80,0x02,0x3C, ++0xF6,0x5E,0x64,0xA0, ++0x0D,0x5F,0x40,0xA0, ++0x02,0x80,0x03,0x3C, ++0x02,0x80,0x02,0x3C, ++0x13,0x5F,0x60,0xA0, ++0x01,0x00,0x06,0x24, ++0x14,0x5F,0x40,0xA0, ++0x02,0x80,0x03,0x3C, ++0x02,0x80,0x02,0x3C, ++0xF8,0x5E,0x66,0xA0, ++0x0F,0x00,0x04,0x24, ++0x15,0x5F,0x40,0xA0, ++0x02,0x80,0x03,0x3C, ++0x02,0x80,0x02,0x3C, ++0xF7,0x5E,0x66,0xA0, ++0xF9,0x5E,0x44,0xA0, ++0x02,0x80,0x03,0x3C, ++0x08,0x00,0x04,0x24, ++0x02,0x80,0x02,0x3C, ++0xFA,0x5E,0x60,0xA0, ++0x64,0x00,0x05,0x24, ++0x04,0x5F,0x44,0xA4, ++0x02,0x80,0x03,0x3C, ++0x01,0x00,0x02,0x3C, ++0xFC,0x5E,0x65,0xA4, ++0x00,0x90,0x42,0x34, ++0x02,0x80,0x03,0x3C, ++0x00,0x5F,0x62,0xAC, ++0x02,0x80,0x04,0x3C, ++0x02,0x80,0x02,0x3C, ++0x08,0x5F,0x80,0xAC, ++0x02,0x80,0x03,0x3C, ++0x0C,0x5F,0x40,0xA0, ++0x02,0x80,0x02,0x3C, ++0x0E,0x5F,0x60,0xA0, ++0x16,0x5F,0x40,0xA0, ++0x02,0x80,0x03,0x3C, ++0x02,0x80,0x02,0x3C, ++0x44,0x5F,0x67,0xA0, ++0x20,0x00,0xBF,0x8F, ++0x0F,0x5F,0x40,0xA0, ++0x02,0x80,0x03,0x3C, ++0x02,0x80,0x02,0x3C, ++0x1C,0x00,0xB1,0x8F, ++0x18,0x00,0xB0,0x8F, ++0x10,0x5F,0x66,0xA0, ++0x11,0x5F,0x46,0xA0, ++0x02,0x80,0x03,0x3C, ++0x02,0x80,0x02,0x3C, ++0x12,0x5F,0x60,0xA0, ++0x21,0x20,0x00,0x00, ++0x18,0x5F,0x40,0xAC, ++0x02,0x80,0x03,0x3C, ++0x02,0x80,0x02,0x3C, ++0x21,0x28,0x00,0x00, ++0x28,0x00,0xBD,0x27, ++0x1C,0x5F,0x60,0xAC, ++0x20,0x5F,0x44,0xAC, ++0x24,0x5F,0x45,0xAC, ++0x08,0x00,0xE0,0x03, ++0x00,0x00,0x00,0x00, ++0xD8,0xFF,0xBD,0x27, ++0x1C,0x00,0xB3,0xAF, ++0x18,0x00,0xB2,0xAF, ++0x14,0x00,0xB1,0xAF, ++0x10,0x00,0xB0,0xAF, ++0x20,0x00,0xBF,0xAF, ++0x21,0x80,0x80,0x00, ++0x21,0x98,0xA0,0x00, ++0x21,0x88,0xC0,0x00, ++0x21,0x90,0x00,0x00, ++0x00,0x00,0x04,0x82, ++0x7C,0x55,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0xFC,0xFF,0x40,0x14, ++0x01,0x00,0x10,0x26, ++0xFF,0xFF,0x10,0x26, ++0x00,0x00,0x04,0x92, ++0x2B,0x00,0x02,0x24, ++0x00,0x1E,0x04,0x00, ++0x03,0x1E,0x03,0x00, ++0x41,0x00,0x62,0x10, ++0x00,0x00,0x00,0x00, ++0x10,0x00,0x02,0x24, ++0x30,0x00,0x22,0x12, ++0x00,0x1E,0x04,0x00, ++0x07,0x00,0x20,0x16, ++0x21,0x18,0x80,0x00, ++0x00,0x1E,0x04,0x00, ++0x03,0x1E,0x03,0x00, ++0x30,0x00,0x02,0x24, ++0x3B,0x00,0x62,0x10, ++0x0A,0x00,0x11,0x24, ++0x21,0x18,0x80,0x00, ++0x00,0x16,0x03,0x00, ++0x03,0x16,0x02,0x00, ++0x1A,0x00,0x40,0x10, ++0xFF,0x00,0x64,0x30, ++0xA9,0xFF,0x82,0x24, ++0x61,0x00,0x83,0x2C, ++0xFF,0x00,0x45,0x30, ++0x09,0x00,0x60,0x10, ++0x41,0x00,0x86,0x2C, ++0xC9,0xFF,0x82,0x24, ++0xFF,0x00,0x45,0x30, ++0x05,0x00,0xC0,0x10, ++0x3A,0x00,0x87,0x2C, ++0xD0,0xFF,0x82,0x24, ++0x02,0x00,0xE0,0x10, ++0xFF,0x00,0x05,0x24, ++0xFF,0x00,0x45,0x30, ++0x2A,0x10,0xB1,0x00, ++0x0A,0x00,0x40,0x10, ++0x18,0x00,0x51,0x02, ++0x01,0x00,0x10,0x26, ++0x12,0x10,0x00,0x00, ++0x2B,0x18,0x52,0x00, ++0x23,0x00,0x60,0x14, ++0x21,0x90,0xA2,0x00, ++0x00,0x00,0x03,0x92, ++0x00,0x00,0x00,0x00, ++0xE8,0xFF,0x60,0x14, ++0xFF,0x00,0x64,0x30, ++0x02,0x00,0x60,0x12, ++0x21,0x10,0x40,0x02, ++0x00,0x00,0x70,0xAE, ++0x20,0x00,0xBF,0x8F, ++0x1C,0x00,0xB3,0x8F, ++0x18,0x00,0xB2,0x8F, ++0x14,0x00,0xB1,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x08,0x00,0xE0,0x03, ++0x28,0x00,0xBD,0x27, ++0x03,0x1E,0x03,0x00, ++0x30,0x00,0x02,0x24, ++0xCE,0xFF,0x62,0x14, ++0x00,0x00,0x00,0x00, ++0x01,0x00,0x03,0x82, ++0x78,0x00,0x02,0x24, ++0x03,0x00,0x62,0x10, ++0x58,0x00,0x02,0x24, ++0xD0,0xFF,0x62,0x14, ++0x21,0x18,0x80,0x00, ++0x02,0x00,0x10,0x26, ++0x00,0x00,0x04,0x92, ++0xC0,0x70,0x00,0x08, ++0x10,0x00,0x11,0x24, ++0x01,0x00,0x10,0x26, ++0x00,0x00,0x04,0x92, ++0xB7,0x70,0x00,0x08, ++0x10,0x00,0x02,0x24, ++0xEC,0x70,0x00,0x08, ++0x08,0x00,0x11,0x24, ++0x20,0x00,0xBF,0x8F, ++0x1C,0x00,0xB3,0x8F, ++0x18,0x00,0xB2,0x8F, ++0x14,0x00,0xB1,0x8F, ++0x10,0x00,0xB0,0x8F, ++0xFF,0xFF,0x02,0x24, ++0x08,0x00,0xE0,0x03, ++0x28,0x00,0xBD,0x27, ++0x21,0x48,0x80,0x00, ++0x31,0x00,0xC0,0x14, ++0x21,0x50,0x00,0x00, ++0x00,0x00,0x87,0x90, ++0x30,0x00,0x02,0x24, ++0x00,0x1E,0x07,0x00, ++0x03,0x1E,0x03,0x00, ++0x2E,0x00,0x62,0x10, ++0x0A,0x00,0x06,0x24, ++0x02,0x80,0x02,0x3C, ++0x40,0xF2,0x4B,0x24, ++0xFF,0x00,0xE8,0x30, ++0x21,0x10,0x0B,0x01, ++0x00,0x00,0x44,0x90, ++0x00,0x1E,0x07,0x00, ++0x03,0x1E,0x03,0x00, ++0x44,0x00,0x82,0x30, ++0x02,0x00,0x87,0x30, ++0xD0,0xFF,0x63,0x24, ++0x1A,0x00,0x40,0x10, ++0x04,0x00,0x84,0x30, ++0x07,0x00,0x80,0x14, ++0x2B,0x10,0x66,0x00, ++0x21,0x10,0x00,0x01, ++0x02,0x00,0xE0,0x10, ++0xE0,0xFF,0x03,0x25, ++0xFF,0x00,0x62,0x30, ++0xC9,0xFF,0x43,0x24, ++0x2B,0x10,0x66,0x00, ++0x10,0x00,0x40,0x10, ++0x18,0x00,0x46,0x01, ++0x01,0x00,0x29,0x25, ++0x00,0x00,0x27,0x91, ++0x00,0x00,0x00,0x00, ++0xFF,0x00,0xE8,0x30, ++0x12,0x10,0x00,0x00, ++0x21,0x50,0x43,0x00, ++0x21,0x10,0x0B,0x01, ++0x00,0x00,0x44,0x90, ++0x00,0x1E,0x07,0x00, ++0x03,0x1E,0x03,0x00, ++0x44,0x00,0x82,0x30, ++0x02,0x00,0x87,0x30, ++0xD0,0xFF,0x63,0x24, ++0xE8,0xFF,0x40,0x14, ++0x04,0x00,0x84,0x30, ++0x02,0x00,0xA0,0x10, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0xA9,0xAC, ++0x08,0x00,0xE0,0x03, ++0x21,0x10,0x40,0x01, ++0x00,0x00,0x87,0x90, ++0x0E,0x71,0x00,0x08, ++0x02,0x80,0x02,0x3C, ++0x01,0x00,0x89,0x24, ++0x00,0x00,0x27,0x91, ++0x78,0x00,0x02,0x24, ++0x00,0x1E,0x07,0x00, ++0x03,0x1E,0x03,0x00, ++0xCD,0xFF,0x62,0x14, ++0x08,0x00,0x06,0x24, ++0x01,0x00,0x22,0x91, ++0x02,0x80,0x03,0x3C, ++0x40,0xF2,0x63,0x24, ++0x21,0x10,0x43,0x00, ++0x00,0x00,0x44,0x90, ++0x00,0x00,0x00,0x00, ++0x44,0x00,0x84,0x30, ++0xC5,0xFF,0x80,0x10, ++0x02,0x80,0x02,0x3C, ++0x01,0x00,0x29,0x25, ++0x00,0x00,0x27,0x91, ++0x0E,0x71,0x00,0x08, ++0x10,0x00,0x06,0x24, ++0xE8,0xFF,0xBD,0x27, ++0x10,0x00,0xBF,0xAF, ++0x00,0x00,0x83,0x80, ++0x2D,0x00,0x02,0x24, ++0x04,0x00,0x62,0x10, ++0x00,0x00,0x00,0x00, ++0x10,0x00,0xBF,0x8F, ++0x04,0x71,0x00,0x08, ++0x18,0x00,0xBD,0x27, ++0x04,0x71,0x00,0x0C, ++0x01,0x00,0x84,0x24, ++0x10,0x00,0xBF,0x8F, ++0x23,0x10,0x02,0x00, ++0x08,0x00,0xE0,0x03, ++0x18,0x00,0xBD,0x27, ++0xD8,0xFF,0xBD,0x27, ++0x1C,0x00,0xB3,0xAF, ++0x18,0x00,0xB2,0xAF, ++0x14,0x00,0xB1,0xAF, ++0x10,0x00,0xB0,0xAF, ++0x20,0x00,0xBF,0xAF, ++0x21,0x80,0x80,0x00, ++0x21,0x90,0xA0,0x00, ++0x21,0x98,0xC0,0x00, ++0x21,0x88,0x00,0x00, ++0x00,0x00,0x04,0x82, ++0x7C,0x55,0x00,0x0C, ++0x00,0x00,0x00,0x00, ++0xFC,0xFF,0x40,0x14, ++0x01,0x00,0x10,0x26, ++0xFF,0xFF,0x10,0x26, ++0x00,0x00,0x03,0x82, ++0x2D,0x00,0x02,0x24, ++0x0F,0x00,0x62,0x10, ++0x21,0x20,0x00,0x02, ++0x21,0x28,0x40,0x02, ++0xA0,0x70,0x00,0x0C, ++0x21,0x30,0x60,0x02, ++0x12,0x00,0x40,0x04, ++0x21,0x18,0x40,0x00, ++0x23,0x10,0x02,0x00, ++0x0A,0x10,0x71,0x00, ++0x20,0x00,0xBF,0x8F, ++0x1C,0x00,0xB3,0x8F, ++0x18,0x00,0xB2,0x8F, ++0x14,0x00,0xB1,0x8F, ++0x10,0x00,0xB0,0x8F, ++0x08,0x00,0xE0,0x03, ++0x28,0x00,0xBD,0x27, ++0x01,0x00,0x10,0x26, ++0x21,0x20,0x00,0x02, ++0x21,0x28,0x40,0x02, ++0xA0,0x70,0x00,0x0C, ++0x21,0x30,0x60,0x02, ++0xFF,0xFF,0x11,0x24, ++0xF0,0xFF,0x41,0x04, ++0x21,0x18,0x40,0x00, ++0xF0,0xFF,0x20,0x16, ++0x00,0x80,0x02,0x3C, ++0x20,0x00,0xBF,0x8F, ++0x1C,0x00,0xB3,0x8F, ++0x18,0x00,0xB2,0x8F, ++0x14,0x00,0xB1,0x8F, ++0x10,0x00,0xB0,0x8F, ++0xFF,0x7F,0x02,0x3C, ++0xFF,0xFF,0x42,0x34, ++0x08,0x00,0xE0,0x03, ++0x28,0x00,0xBD,0x27, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x52,0x54,0x4C,0x38, ++0x37,0x31,0x32,0x20, ++0x46,0x57,0x20,0x76, ++0x65,0x72,0x73,0x69, ++0x6F,0x6E,0x20,0x30, ++0x2E,0x30,0x2E,0x31, ++0x23,0x20,0xE4,0xB8, ++0x89,0x20,0x31,0x30, ++0xE6,0x9C,0x88,0x20, ++0x32,0x38,0x20,0x31, ++0x37,0x3A,0x34,0x31, ++0x3A,0x34,0x37,0x20, ++0x43,0x53,0x54,0x20, ++0x32,0x30,0x30,0x39, ++0x0A,0x00,0x00,0x00, ++0x50,0xC6,0x01,0x80, ++0x48,0x43,0x49,0x20, ++0x74,0x79,0x70,0x65, ++0x3A,0x20,0x25,0x78, ++0x28,0x25,0x78,0x29, ++0x0A,0x00,0x00,0x00, ++0x72,0x66,0x5F,0x63, ++0x6F,0x66,0x69,0x67, ++0x3A,0x20,0x25,0x78, ++0x28,0x25,0x78,0x2C, ++0x20,0x25,0x78,0x2C, ++0x20,0x25,0x78,0x29, ++0x0A,0x00,0x00,0x00, ++0x6D,0x70,0x5F,0x6D, ++0x6F,0x64,0x65,0x3A, ++0x20,0x25,0x78,0x28, ++0x25,0x78,0x29,0x2C, ++0x20,0x49,0x51,0x4B, ++0x3A,0x20,0x25,0x78, ++0x0A,0x00,0x00,0x00, ++0x76,0x63,0x73,0x20, ++0x74,0x79,0x70,0x65, ++0x3A,0x20,0x25,0x78, ++0x28,0x25,0x78,0x29, ++0x0A,0x00,0x00,0x00, ++0x33,0x32,0x6B,0x20, ++0x63,0x61,0x6C,0x69, ++0x62,0x72,0x61,0x3A, ++0x20,0x25,0x64,0x2C, ++0x20,0x33,0x32,0x4B, ++0x20,0x54,0x53,0x46, ++0x3A,0x20,0x25,0x78, ++0x00,0x00,0x00,0x00, ++0x74,0x61,0x72,0x67, ++0x65,0x74,0x20,0x74, ++0x68,0x65,0x72,0x6D, ++0x61,0x6C,0x3A,0x20, ++0x25,0x78,0x0A,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x78,0x0C,0x00,0x00, ++0x01,0x00,0x00,0x7F, ++0x78,0x0C,0x00,0x00, ++0x01,0x00,0x01,0x7F, ++0x78,0x0C,0x00,0x00, ++0x01,0x00,0x02,0x7E, ++0x78,0x0C,0x00,0x00, ++0x01,0x00,0x03,0x7D, ++0x78,0x0C,0x00,0x00, ++0x01,0x00,0x04,0x7C, ++0x78,0x0C,0x00,0x00, ++0x01,0x00,0x05,0x7B, ++0x78,0x0C,0x00,0x00, ++0x01,0x00,0x06,0x7A, ++0x78,0x0C,0x00,0x00, ++0x01,0x00,0x07,0x79, ++0x78,0x0C,0x00,0x00, ++0x01,0x00,0x08,0x78, ++0x78,0x0C,0x00,0x00, ++0x01,0x00,0x09,0x77, ++0x78,0x0C,0x00,0x00, ++0x01,0x00,0x0A,0x76, ++0x78,0x0C,0x00,0x00, ++0x01,0x00,0x0B,0x75, ++0x78,0x0C,0x00,0x00, ++0x01,0x00,0x0C,0x74, ++0x78,0x0C,0x00,0x00, ++0x01,0x00,0x0D,0x73, ++0x78,0x0C,0x00,0x00, ++0x01,0x00,0x0E,0x72, ++0x78,0x0C,0x00,0x00, ++0x01,0x00,0x0F,0x71, ++0x78,0x0C,0x00,0x00, ++0x01,0x00,0x10,0x70, ++0x78,0x0C,0x00,0x00, ++0x01,0x00,0x11,0x6F, ++0x78,0x0C,0x00,0x00, ++0x01,0x00,0x12,0x6F, ++0x78,0x0C,0x00,0x00, ++0x01,0x00,0x13,0x6E, ++0x78,0x0C,0x00,0x00, ++0x01,0x00,0x14,0x6D, ++0x78,0x0C,0x00,0x00, ++0x01,0x00,0x15,0x6D, ++0x78,0x0C,0x00,0x00, ++0x01,0x00,0x16,0x6C, ++0x78,0x0C,0x00,0x00, ++0x01,0x00,0x17,0x6B, ++0x78,0x0C,0x00,0x00, ++0x01,0x00,0x18,0x6A, ++0x78,0x0C,0x00,0x00, ++0x01,0x00,0x19,0x6A, ++0x78,0x0C,0x00,0x00, ++0x01,0x00,0x1A,0x69, ++0x78,0x0C,0x00,0x00, ++0x01,0x00,0x1B,0x68, ++0x78,0x0C,0x00,0x00, ++0x01,0x00,0x1C,0x67, ++0x78,0x0C,0x00,0x00, ++0x01,0x00,0x1D,0x66, ++0x78,0x0C,0x00,0x00, ++0x01,0x00,0x1E,0x65, ++0x78,0x0C,0x00,0x00, ++0x01,0x00,0x1F,0x64, ++0x78,0x0C,0x00,0x00, ++0x01,0x00,0x20,0x63, ++0x78,0x0C,0x00,0x00, ++0x01,0x00,0x21,0x4C, ++0x78,0x0C,0x00,0x00, ++0x01,0x00,0x22,0x4B, ++0x78,0x0C,0x00,0x00, ++0x01,0x00,0x23,0x4A, ++0x78,0x0C,0x00,0x00, ++0x01,0x00,0x24,0x49, ++0x78,0x0C,0x00,0x00, ++0x01,0x00,0x25,0x48, ++0x78,0x0C,0x00,0x00, ++0x01,0x00,0x26,0x47, ++0x78,0x0C,0x00,0x00, ++0x01,0x00,0x27,0x46, ++0x78,0x0C,0x00,0x00, ++0x01,0x00,0x28,0x45, ++0x78,0x0C,0x00,0x00, ++0x01,0x00,0x29,0x44, ++0x78,0x0C,0x00,0x00, ++0x01,0x00,0x2A,0x2C, ++0x78,0x0C,0x00,0x00, ++0x01,0x00,0x2B,0x2B, ++0x78,0x0C,0x00,0x00, ++0x01,0x00,0x2C,0x2A, ++0x78,0x0C,0x00,0x00, ++0x01,0x00,0x2D,0x29, ++0x78,0x0C,0x00,0x00, ++0x01,0x00,0x2E,0x28, ++0x78,0x0C,0x00,0x00, ++0x01,0x00,0x2F,0x27, ++0x78,0x0C,0x00,0x00, ++0x01,0x00,0x30,0x26, ++0x78,0x0C,0x00,0x00, ++0x01,0x00,0x31,0x25, ++0x78,0x0C,0x00,0x00, ++0x01,0x00,0x32,0x24, ++0x78,0x0C,0x00,0x00, ++0x01,0x00,0x33,0x23, ++0x78,0x0C,0x00,0x00, ++0x01,0x00,0x34,0x22, ++0x78,0x0C,0x00,0x00, ++0x01,0x00,0x35,0x09, ++0x78,0x0C,0x00,0x00, ++0x01,0x00,0x36,0x08, ++0x78,0x0C,0x00,0x00, ++0x01,0x00,0x37,0x07, ++0x78,0x0C,0x00,0x00, ++0x01,0x00,0x38,0x06, ++0x78,0x0C,0x00,0x00, ++0x01,0x00,0x39,0x05, ++0x78,0x0C,0x00,0x00, ++0x01,0x00,0x3A,0x04, ++0x78,0x0C,0x00,0x00, ++0x01,0x00,0x3B,0x03, ++0x78,0x0C,0x00,0x00, ++0x01,0x00,0x3C,0x02, ++0x78,0x0C,0x00,0x00, ++0x01,0x00,0x3D,0x01, ++0x78,0x0C,0x00,0x00, ++0x01,0x00,0x3E,0x00, ++0x78,0x0C,0x00,0x00, ++0x01,0x00,0x3F,0x00, ++0x78,0x0C,0x00,0x00, ++0x01,0x00,0x40,0x7F, ++0x78,0x0C,0x00,0x00, ++0x01,0x00,0x41,0x7F, ++0x78,0x0C,0x00,0x00, ++0x01,0x00,0x42,0x7E, ++0x78,0x0C,0x00,0x00, ++0x01,0x00,0x43,0x7D, ++0x78,0x0C,0x00,0x00, ++0x01,0x00,0x44,0x7C, ++0x78,0x0C,0x00,0x00, ++0x01,0x00,0x45,0x7B, ++0x78,0x0C,0x00,0x00, ++0x01,0x00,0x46,0x7A, ++0x78,0x0C,0x00,0x00, ++0x01,0x00,0x47,0x79, ++0x78,0x0C,0x00,0x00, ++0x01,0x00,0x48,0x78, ++0x78,0x0C,0x00,0x00, ++0x01,0x00,0x49,0x77, ++0x78,0x0C,0x00,0x00, ++0x01,0x00,0x4A,0x76, ++0x78,0x0C,0x00,0x00, ++0x01,0x00,0x4B,0x75, ++0x78,0x0C,0x00,0x00, ++0x01,0x00,0x4C,0x74, ++0x78,0x0C,0x00,0x00, ++0x01,0x00,0x4D,0x73, ++0x78,0x0C,0x00,0x00, ++0x01,0x00,0x4E,0x72, ++0x78,0x0C,0x00,0x00, ++0x01,0x00,0x4F,0x71, ++0x78,0x0C,0x00,0x00, ++0x01,0x00,0x50,0x70, ++0x78,0x0C,0x00,0x00, ++0x01,0x00,0x51,0x6F, ++0x78,0x0C,0x00,0x00, ++0x01,0x00,0x52,0x6F, ++0x78,0x0C,0x00,0x00, ++0x01,0x00,0x53,0x6E, ++0x78,0x0C,0x00,0x00, ++0x01,0x00,0x54,0x6D, ++0x78,0x0C,0x00,0x00, ++0x01,0x00,0x55,0x6D, ++0x78,0x0C,0x00,0x00, ++0x01,0x00,0x56,0x6C, ++0x78,0x0C,0x00,0x00, ++0x01,0x00,0x57,0x6B, ++0x78,0x0C,0x00,0x00, ++0x01,0x00,0x58,0x6A, ++0x78,0x0C,0x00,0x00, ++0x01,0x00,0x59,0x6A, ++0x78,0x0C,0x00,0x00, ++0x01,0x00,0x5A,0x69, ++0x78,0x0C,0x00,0x00, ++0x01,0x00,0x5B,0x68, ++0x78,0x0C,0x00,0x00, ++0x01,0x00,0x5C,0x67, ++0x78,0x0C,0x00,0x00, ++0x01,0x00,0x5D,0x66, ++0x78,0x0C,0x00,0x00, ++0x01,0x00,0x5E,0x65, ++0x78,0x0C,0x00,0x00, ++0x01,0x00,0x5F,0x64, ++0x78,0x0C,0x00,0x00, ++0x01,0x00,0x60,0x63, ++0x78,0x0C,0x00,0x00, ++0x01,0x00,0x61,0x4C, ++0x78,0x0C,0x00,0x00, ++0x01,0x00,0x62,0x4B, ++0x78,0x0C,0x00,0x00, ++0x01,0x00,0x63,0x4A, ++0x78,0x0C,0x00,0x00, ++0x01,0x00,0x64,0x49, ++0x78,0x0C,0x00,0x00, ++0x01,0x00,0x65,0x48, ++0x78,0x0C,0x00,0x00, ++0x01,0x00,0x66,0x47, ++0x78,0x0C,0x00,0x00, ++0x01,0x00,0x67,0x46, ++0x78,0x0C,0x00,0x00, ++0x01,0x00,0x68,0x45, ++0x78,0x0C,0x00,0x00, ++0x01,0x00,0x69,0x44, ++0x78,0x0C,0x00,0x00, ++0x01,0x00,0x6A,0x2C, ++0x78,0x0C,0x00,0x00, ++0x01,0x00,0x6B,0x2B, ++0x78,0x0C,0x00,0x00, ++0x01,0x00,0x6C,0x2A, ++0x78,0x0C,0x00,0x00, ++0x01,0x00,0x6D,0x29, ++0x78,0x0C,0x00,0x00, ++0x01,0x00,0x6E,0x28, ++0x78,0x0C,0x00,0x00, ++0x01,0x00,0x6F,0x27, ++0x78,0x0C,0x00,0x00, ++0x01,0x00,0x70,0x26, ++0x78,0x0C,0x00,0x00, ++0x01,0x00,0x71,0x25, ++0x78,0x0C,0x00,0x00, ++0x01,0x00,0x72,0x24, ++0x78,0x0C,0x00,0x00, ++0x01,0x00,0x73,0x23, ++0x78,0x0C,0x00,0x00, ++0x01,0x00,0x74,0x22, ++0x78,0x0C,0x00,0x00, ++0x01,0x00,0x75,0x09, ++0x78,0x0C,0x00,0x00, ++0x01,0x00,0x76,0x08, ++0x78,0x0C,0x00,0x00, ++0x01,0x00,0x77,0x07, ++0x78,0x0C,0x00,0x00, ++0x01,0x00,0x78,0x06, ++0x78,0x0C,0x00,0x00, ++0x01,0x00,0x79,0x05, ++0x78,0x0C,0x00,0x00, ++0x01,0x00,0x7A,0x04, ++0x78,0x0C,0x00,0x00, ++0x01,0x00,0x7B,0x03, ++0x78,0x0C,0x00,0x00, ++0x01,0x00,0x7C,0x02, ++0x78,0x0C,0x00,0x00, ++0x01,0x00,0x7D,0x01, ++0x78,0x0C,0x00,0x00, ++0x01,0x00,0x7E,0x00, ++0x78,0x0C,0x00,0x00, ++0x01,0x00,0x7F,0x00, ++0x78,0x0C,0x00,0x00, ++0x1E,0x00,0x00,0x30, ++0x78,0x0C,0x00,0x00, ++0x1E,0x00,0x01,0x30, ++0x78,0x0C,0x00,0x00, ++0x1E,0x00,0x02,0x30, ++0x78,0x0C,0x00,0x00, ++0x1E,0x00,0x03,0x30, ++0x78,0x0C,0x00,0x00, ++0x1E,0x00,0x04,0x30, ++0x78,0x0C,0x00,0x00, ++0x1E,0x00,0x05,0x34, ++0x78,0x0C,0x00,0x00, ++0x1E,0x00,0x06,0x38, ++0x78,0x0C,0x00,0x00, ++0x1E,0x00,0x07,0x3E, ++0x78,0x0C,0x00,0x00, ++0x1E,0x00,0x08,0x3E, ++0x78,0x0C,0x00,0x00, ++0x1E,0x00,0x09,0x44, ++0x78,0x0C,0x00,0x00, ++0x1E,0x00,0x0A,0x46, ++0x78,0x0C,0x00,0x00, ++0x1E,0x00,0x0B,0x48, ++0x78,0x0C,0x00,0x00, ++0x1E,0x00,0x0C,0x48, ++0x78,0x0C,0x00,0x00, ++0x1E,0x00,0x0D,0x4E, ++0x78,0x0C,0x00,0x00, ++0x1E,0x00,0x0E,0x56, ++0x78,0x0C,0x00,0x00, ++0x1E,0x00,0x0F,0x5A, ++0x78,0x0C,0x00,0x00, ++0x1E,0x00,0x10,0x5E, ++0x78,0x0C,0x00,0x00, ++0x1E,0x00,0x11,0x62, ++0x78,0x0C,0x00,0x00, ++0x1E,0x00,0x12,0x6C, ++0x78,0x0C,0x00,0x00, ++0x1E,0x00,0x13,0x72, ++0x78,0x0C,0x00,0x00, ++0x1E,0x00,0x14,0x72, ++0x78,0x0C,0x00,0x00, ++0x1E,0x00,0x15,0x72, ++0x78,0x0C,0x00,0x00, ++0x1E,0x00,0x16,0x72, ++0x78,0x0C,0x00,0x00, ++0x1E,0x00,0x17,0x72, ++0x78,0x0C,0x00,0x00, ++0x1E,0x00,0x18,0x72, ++0x78,0x0C,0x00,0x00, ++0x1E,0x00,0x19,0x72, ++0x78,0x0C,0x00,0x00, ++0x1E,0x00,0x1A,0x72, ++0x78,0x0C,0x00,0x00, ++0x1E,0x00,0x1B,0x72, ++0x78,0x0C,0x00,0x00, ++0x1E,0x00,0x1C,0x72, ++0x78,0x0C,0x00,0x00, ++0x1E,0x00,0x1D,0x72, ++0x78,0x0C,0x00,0x00, ++0x1E,0x00,0x1E,0x72, ++0x78,0x0C,0x00,0x00, ++0x1E,0x00,0x1F,0x72, ++0x00,0x0E,0x00,0x00, ++0xFF,0xFF,0xFF,0xFF, ++0x06,0x06,0x06,0x04, ++0x04,0x0E,0x00,0x00, ++0xFF,0xFF,0xFF,0xFF, ++0x04,0x02,0x02,0x00, ++0x08,0x0E,0x00,0x00, ++0x00,0xFF,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x10,0x0E,0x00,0x00, ++0xFF,0xFF,0xFF,0xFF, ++0x0A,0x08,0x08,0x04, ++0x14,0x0E,0x00,0x00, ++0xFF,0xFF,0xFF,0xFF, ++0x04,0x02,0x02,0x00, ++0x18,0x0E,0x00,0x00, ++0xFF,0xFF,0xFF,0xFF, ++0x0A,0x08,0x08,0x04, ++0x1C,0x0E,0x00,0x00, ++0xFF,0xFF,0xFF,0xFF, ++0x04,0x02,0x02,0x00, ++0x00,0x0E,0x00,0x00, ++0xFF,0xFF,0xFF,0xFF, ++0x00,0x00,0x00,0x00, ++0x04,0x0E,0x00,0x00, ++0xFF,0xFF,0xFF,0xFF, ++0x00,0x00,0x00,0x00, ++0x08,0x0E,0x00,0x00, ++0x00,0xFF,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x10,0x0E,0x00,0x00, ++0xFF,0xFF,0xFF,0xFF, ++0x00,0x00,0x00,0x00, ++0x14,0x0E,0x00,0x00, ++0xFF,0xFF,0xFF,0xFF, ++0x00,0x00,0x00,0x00, ++0x18,0x0E,0x00,0x00, ++0xFF,0xFF,0xFF,0xFF, ++0x00,0x00,0x00,0x00, ++0x1C,0x0E,0x00,0x00, ++0xFF,0xFF,0xFF,0xFF, ++0x00,0x00,0x00,0x00, ++0x00,0x0E,0x00,0x00, ++0xFF,0xFF,0xFF,0xFF, ++0x00,0x00,0x00,0x00, ++0x04,0x0E,0x00,0x00, ++0xFF,0xFF,0xFF,0xFF, ++0x00,0x00,0x00,0x00, ++0x08,0x0E,0x00,0x00, ++0x00,0xFF,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x10,0x0E,0x00,0x00, ++0xFF,0xFF,0xFF,0xFF, ++0x00,0x00,0x00,0x00, ++0x14,0x0E,0x00,0x00, ++0xFF,0xFF,0xFF,0xFF, ++0x00,0x00,0x00,0x00, ++0x18,0x0E,0x00,0x00, ++0xFF,0xFF,0xFF,0xFF, ++0x00,0x00,0x00,0x00, ++0x1C,0x0E,0x00,0x00, ++0xFF,0xFF,0xFF,0xFF, ++0x00,0x00,0x00,0x00, ++0x00,0x0E,0x00,0x00, ++0xFF,0xFF,0xFF,0xFF, ++0x00,0x00,0x00,0x00, ++0x04,0x0E,0x00,0x00, ++0xFF,0xFF,0xFF,0xFF, ++0x00,0x00,0x00,0x00, ++0x08,0x0E,0x00,0x00, ++0x00,0xFF,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x10,0x0E,0x00,0x00, ++0xFF,0xFF,0xFF,0xFF, ++0x00,0x00,0x00,0x00, ++0x14,0x0E,0x00,0x00, ++0xFF,0xFF,0xFF,0xFF, ++0x00,0x00,0x00,0x00, ++0x18,0x0E,0x00,0x00, ++0xFF,0xFF,0xFF,0xFF, ++0x00,0x00,0x00,0x00, ++0x1C,0x0E,0x00,0x00, ++0xFF,0xFF,0xFF,0xFF, ++0x00,0x00,0x00,0x00, ++0x04,0x08,0x00,0x00, ++0x0F,0x00,0x00,0x00, ++0x03,0x00,0x00,0x00, ++0x24,0x08,0x00,0x00, ++0x0F,0x00,0xF0,0x00, ++0x04,0x00,0x30,0x00, ++0x2C,0x08,0x00,0x00, ++0x0F,0x00,0xF0,0x00, ++0x04,0x00,0x30,0x00, ++0x70,0x08,0x00,0x00, ++0x00,0x00,0x00,0x04, ++0x01,0x00,0x00,0x00, ++0x64,0x08,0x00,0x00, ++0x00,0x04,0x00,0x00, ++0x01,0x00,0x00,0x00, ++0x78,0x08,0x00,0x00, ++0x0F,0x00,0x0F,0x00, ++0x02,0x00,0x02,0x00, ++0x74,0x0E,0x00,0x00, ++0x00,0x00,0x00,0x0F, ++0x06,0x00,0x00,0x00, ++0x78,0x0E,0x00,0x00, ++0x00,0x00,0x00,0x0F, ++0x06,0x00,0x00,0x00, ++0x7C,0x0E,0x00,0x00, ++0x00,0x00,0x00,0x0F, ++0x06,0x00,0x00,0x00, ++0x80,0x0E,0x00,0x00, ++0x00,0x00,0x00,0x0F, ++0x06,0x00,0x00,0x00, ++0x0C,0x09,0x00,0x00, ++0xFF,0x00,0x00,0x00, ++0x33,0x00,0x00,0x00, ++0x04,0x0C,0x00,0x00, ++0xFF,0x00,0x00,0x00, ++0x33,0x00,0x00,0x00, ++0x04,0x0D,0x00,0x00, ++0x0F,0x00,0x00,0x00, ++0x03,0x00,0x00,0x00, ++0xF4,0x01,0x00,0x00, ++0x00,0x00,0xFF,0xFF, ++0xFF,0xFF,0x00,0x00, ++0x34,0x02,0x00,0x00, ++0x00,0x00,0x00,0xF8, ++0x13,0x00,0x00,0x00, ++0x04,0x08,0x00,0x00, ++0x0F,0x00,0x00,0x00, ++0x03,0x00,0x00,0x00, ++0x24,0x08,0x00,0x00, ++0x0F,0x00,0xF0,0x00, ++0x04,0x00,0x30,0x00, ++0x2C,0x08,0x00,0x00, ++0x0F,0x00,0xF0,0x00, ++0x02,0x00,0x30,0x00, ++0x70,0x08,0x00,0x00, ++0x00,0x00,0x00,0x04, ++0x01,0x00,0x00,0x00, ++0x64,0x08,0x00,0x00, ++0x00,0x04,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x78,0x08,0x00,0x00, ++0x0F,0x00,0x0F,0x00, ++0x02,0x00,0x00,0x00, ++0x74,0x0E,0x00,0x00, ++0x00,0x00,0x00,0x0F, ++0x02,0x00,0x00,0x00, ++0x78,0x0E,0x00,0x00, ++0x00,0x00,0x00,0x0F, ++0x02,0x00,0x00,0x00, ++0x7C,0x0E,0x00,0x00, ++0x00,0x00,0x00,0x0F, ++0x02,0x00,0x00,0x00, ++0x80,0x0E,0x00,0x00, ++0x00,0x00,0x00,0x0F, ++0x02,0x00,0x00,0x00, ++0x0C,0x09,0x00,0x00, ++0xFF,0x00,0x00,0x00, ++0x11,0x00,0x00,0x00, ++0x04,0x0C,0x00,0x00, ++0xFF,0x00,0x00,0x00, ++0x33,0x00,0x00,0x00, ++0x04,0x0D,0x00,0x00, ++0x0F,0x00,0x00,0x00, ++0x03,0x00,0x00,0x00, ++0xF4,0x01,0x00,0x00, ++0x00,0x00,0xFF,0xFF, ++0x77,0x77,0x00,0x00, ++0x34,0x02,0x00,0x00, ++0x00,0x00,0x00,0xF8, ++0x0A,0x00,0x00,0x00, ++0x44,0x08,0x00,0x00, ++0xFF,0xFF,0xFF,0xFF, ++0x00,0x00,0x01,0x00, ++0x04,0x08,0x00,0x00, ++0x0F,0x00,0x00,0x00, ++0x01,0x00,0x00,0x00, ++0x24,0x08,0x00,0x00, ++0x0F,0x00,0xF0,0x00, ++0x04,0x00,0x30,0x00, ++0x2C,0x08,0x00,0x00, ++0x0F,0x00,0xF0,0x00, ++0x02,0x00,0x10,0x00, ++0x70,0x08,0x00,0x00, ++0x00,0x00,0x00,0x04, ++0x01,0x00,0x00,0x00, ++0x64,0x08,0x00,0x00, ++0x00,0x04,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x78,0x08,0x00,0x00, ++0x0F,0x00,0x0F,0x00, ++0x02,0x00,0x00,0x00, ++0x74,0x0E,0x00,0x00, ++0x00,0x00,0x00,0x0F, ++0x02,0x00,0x00,0x00, ++0x78,0x0E,0x00,0x00, ++0x00,0x00,0x00,0x0F, ++0x02,0x00,0x00,0x00, ++0x7C,0x0E,0x00,0x00, ++0x00,0x00,0x00,0x0F, ++0x02,0x00,0x00,0x00, ++0x80,0x0E,0x00,0x00, ++0x00,0x00,0x00,0x0F, ++0x02,0x00,0x00,0x00, ++0x0C,0x09,0x00,0x00, ++0xFF,0x00,0x00,0x00, ++0x11,0x00,0x00,0x00, ++0x04,0x0C,0x00,0x00, ++0xFF,0x00,0x00,0x00, ++0x11,0x00,0x00,0x00, ++0x04,0x0D,0x00,0x00, ++0x0F,0x00,0x00,0x00, ++0x01,0x00,0x00,0x00, ++0xF4,0x01,0x00,0x00, ++0x00,0x00,0xFF,0xFF, ++0x77,0x77,0x00,0x00, ++0x34,0x02,0x00,0x00, ++0x00,0x00,0x00,0xF8, ++0x0A,0x00,0x00,0x00, ++0x1C,0x00,0x00,0x00, ++0x00,0x00,0x00,0x07, ++0x00,0x08,0x00,0x00, ++0x00,0x00,0x04,0x00, ++0x04,0x08,0x00,0x00, ++0x03,0x80,0x00,0x00, ++0x08,0x08,0x00,0x00, ++0x00,0xFC,0x00,0x00, ++0x0C,0x08,0x00,0x00, ++0x0A,0x00,0x00,0x00, ++0x10,0x08,0x00,0x00, ++0x88,0x50,0x00,0x10, ++0x14,0x08,0x00,0x00, ++0x10,0x3D,0x0C,0x02, ++0x18,0x08,0x00,0x00, ++0x85,0x01,0x20,0x00, ++0x1C,0x08,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x20,0x08,0x00,0x00, ++0x00,0x00,0x00,0x01, ++0x24,0x08,0x00,0x00, ++0x04,0x00,0x39,0x00, ++0x28,0x08,0x00,0x00, ++0x00,0x00,0x00,0x01, ++0x2C,0x08,0x00,0x00, ++0x04,0x00,0x39,0x00, ++0x30,0x08,0x00,0x00, ++0x04,0x00,0x00,0x00, ++0x34,0x08,0x00,0x00, ++0x00,0x02,0x69,0x00, ++0x38,0x08,0x00,0x00, ++0x04,0x00,0x00,0x00, ++0x3C,0x08,0x00,0x00, ++0x00,0x02,0x69,0x00, ++0x40,0x08,0x00,0x00, ++0x00,0x00,0x01,0x00, ++0x44,0x08,0x00,0x00, ++0x00,0x00,0x01,0x00, ++0x48,0x08,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x4C,0x08,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x50,0x08,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x54,0x08,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x58,0x08,0x00,0x00, ++0x48,0x48,0x48,0x48, ++0x5C,0x08,0x00,0x00, ++0xA9,0x65,0xA9,0x65, ++0x60,0x08,0x00,0x00, ++0x30,0x01,0x7F,0x0F, ++0x64,0x08,0x00,0x00, ++0x30,0x01,0x7F,0x0F, ++0x68,0x08,0x00,0x00, ++0x30,0x01,0x7F,0x0F, ++0x6C,0x08,0x00,0x00, ++0x30,0x01,0x7F,0x0F, ++0x70,0x08,0x00,0x00, ++0x00,0x07,0x00,0x03, ++0x74,0x08,0x00,0x00, ++0x00,0x03,0x00,0x03, ++0x78,0x08,0x00,0x00, ++0x02,0x00,0x02,0x00, ++0x7C,0x08,0x00,0x00, ++0x01,0x02,0x4F,0x00, ++0x80,0x08,0x00,0x00, ++0xC1,0x0A,0x30,0xA8, ++0x84,0x08,0x00,0x00, ++0x58,0x00,0x00,0x00, ++0x88,0x08,0x00,0x00, ++0x08,0x00,0x00,0x00, ++0x8C,0x08,0x00,0x00, ++0x04,0x00,0x00,0x00, ++0x90,0x08,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x94,0x08,0x00,0x00, ++0xFE,0xFF,0xFF,0xFF, ++0x98,0x08,0x00,0x00, ++0x10,0x20,0x30,0x40, ++0x9C,0x08,0x00,0x00, ++0x50,0x60,0x70,0x00, ++0xB0,0x08,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0xE0,0x08,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0xE4,0x08,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x0E,0x00,0x00, ++0x33,0x33,0x33,0x30, ++0x04,0x0E,0x00,0x00, ++0x2F,0x2E,0x2D,0x2A, ++0x08,0x0E,0x00,0x00, ++0x32,0x32,0x00,0x00, ++0x10,0x0E,0x00,0x00, ++0x33,0x33,0x33,0x30, ++0x14,0x0E,0x00,0x00, ++0x2F,0x2E,0x2D,0x2A, ++0x18,0x0E,0x00,0x00, ++0x33,0x33,0x33,0x30, ++0x1C,0x0E,0x00,0x00, ++0x2F,0x2E,0x2D,0x2A, ++0x30,0x0E,0x00,0x00, ++0x00,0x7C,0x00,0x01, ++0x34,0x0E,0x00,0x00, ++0x00,0x48,0x00,0x01, ++0x38,0x0E,0x00,0x00, ++0x1F,0xDC,0x00,0x10, ++0x3C,0x0E,0x00,0x00, ++0x1F,0x8C,0x00,0x10, ++0x40,0x0E,0x00,0x00, ++0xA0,0x00,0x14,0x02, ++0x44,0x0E,0x00,0x00, ++0xA0,0x00,0x16,0x28, ++0x48,0x0E,0x00,0x00, ++0x01,0x00,0x00,0xF8, ++0x4C,0x0E,0x00,0x00, ++0x10,0x29,0x00,0x00, ++0x50,0x0E,0x00,0x00, ++0x00,0x7C,0x00,0x01, ++0x54,0x0E,0x00,0x00, ++0x00,0x48,0x00,0x01, ++0x58,0x0E,0x00,0x00, ++0x1F,0xDC,0x00,0x10, ++0x5C,0x0E,0x00,0x00, ++0x1F,0x8C,0x00,0x10, ++0x60,0x0E,0x00,0x00, ++0xA0,0x00,0x14,0x02, ++0x64,0x0E,0x00,0x00, ++0xA0,0x00,0x16,0x28, ++0x6C,0x0E,0x00,0x00, ++0x10,0x29,0x00,0x00, ++0x70,0x0E,0x00,0x00, ++0xFB,0x92,0xED,0x31, ++0x74,0x0E,0x00,0x00, ++0xFB,0x36,0x15,0x36, ++0x78,0x0E,0x00,0x00, ++0xFB,0x36,0x15,0x36, ++0x7C,0x0E,0x00,0x00, ++0xFB,0x36,0x15,0x36, ++0x80,0x0E,0x00,0x00, ++0xFB,0x36,0x15,0x36, ++0x84,0x0E,0x00,0x00, ++0xFB,0x92,0x0D,0x00, ++0x88,0x0E,0x00,0x00, ++0xFB,0x92,0x0D,0x00, ++0x8C,0x0E,0x00,0x00, ++0xFB,0x92,0xED,0x31, ++0xD0,0x0E,0x00,0x00, ++0xFB,0x92,0xED,0x31, ++0xD4,0x0E,0x00,0x00, ++0xFB,0x92,0xED,0x31, ++0xD8,0x0E,0x00,0x00, ++0xFB,0x92,0x0D,0x00, ++0xDC,0x0E,0x00,0x00, ++0xFB,0x92,0x0D,0x00, ++0xE0,0x0E,0x00,0x00, ++0xFB,0x92,0x0D,0x00, ++0xE4,0x0E,0x00,0x00, ++0x48,0x54,0x5E,0x01, ++0xE8,0x0E,0x00,0x00, ++0x48,0x54,0x55,0x21, ++0x00,0x09,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x04,0x09,0x00,0x00, ++0x23,0x00,0x00,0x00, ++0x08,0x09,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x0C,0x09,0x00,0x00, ++0x13,0x13,0x12,0x01, ++0x00,0x0A,0x00,0x00, ++0xC8,0x47,0xD0,0x00, ++0x04,0x0A,0x00,0x00, ++0x08,0x00,0xFF,0x80, ++0x08,0x0A,0x00,0x00, ++0x00,0x83,0xCD,0x88, ++0x0C,0x0A,0x00,0x00, ++0x0F,0x12,0x62,0x2E, ++0x10,0x0A,0x00,0x00, ++0x78,0xBB,0x00,0x95, ++0x14,0x0A,0x00,0x00, ++0x28,0x40,0x14,0x11, ++0x18,0x0A,0x00,0x00, ++0x17,0x11,0x88,0x00, ++0x1C,0x0A,0x00,0x00, ++0x00,0x0F,0x14,0x89, ++0x20,0x0A,0x00,0x00, ++0x00,0x00,0x1B,0x1A, ++0x24,0x0A,0x00,0x00, ++0x17,0x13,0x0E,0x09, ++0x28,0x0A,0x00,0x00, ++0x04,0x02,0x00,0x00, ++0x2C,0x0A,0x00,0x00, ++0x00,0x00,0xD3,0x10, ++0x00,0x0C,0x00,0x00, ++0x40,0x1D,0x07,0x40, ++0x04,0x0C,0x00,0x00, ++0x33,0x56,0xA0,0x00, ++0x08,0x0C,0x00,0x00, ++0xE4,0x00,0x00,0x00, ++0x0C,0x0C,0x00,0x00, ++0x6C,0x6C,0x6C,0x6C, ++0x10,0x0C,0x00,0x00, ++0x00,0x00,0x80,0x08, ++0x14,0x0C,0x00,0x00, ++0x00,0x01,0x00,0x40, ++0x18,0x0C,0x00,0x00, ++0x00,0x00,0x00,0x08, ++0x1C,0x0C,0x00,0x00, ++0x00,0x01,0x00,0x40, ++0x20,0x0C,0x00,0x00, ++0x00,0x00,0x00,0x08, ++0x24,0x0C,0x00,0x00, ++0x00,0x01,0x00,0x40, ++0x28,0x0C,0x00,0x00, ++0x00,0x00,0x00,0x08, ++0x2C,0x0C,0x00,0x00, ++0x00,0x01,0x00,0x40, ++0x30,0x0C,0x00,0x00, ++0x44,0xAC,0xE9,0x6D, ++0x34,0x0C,0x00,0x00, ++0xCF,0x52,0x96,0x46, ++0x38,0x0C,0x00,0x00, ++0x94,0x59,0x79,0x49, ++0x3C,0x0C,0x00,0x00, ++0x64,0x97,0x97,0x0A, ++0x40,0x0C,0x00,0x00, ++0x3F,0x40,0x7C,0x1F, ++0x44,0x0C,0x00,0x00, ++0xB7,0x00,0x01,0x00, ++0x48,0x0C,0x00,0x00, ++0x00,0x00,0x02,0xEC, ++0x4C,0x0C,0x00,0x00, ++0x7F,0x03,0x7F,0x00, ++0x50,0x0C,0x00,0x00, ++0x20,0x34,0x54,0x69, ++0x54,0x0C,0x00,0x00, ++0x94,0x00,0x3C,0x43, ++0x58,0x0C,0x00,0x00, ++0x20,0x34,0x54,0x69, ++0x5C,0x0C,0x00,0x00, ++0x94,0x00,0x3C,0x43, ++0x60,0x0C,0x00,0x00, ++0x20,0x34,0x54,0x69, ++0x64,0x0C,0x00,0x00, ++0x94,0x00,0x3C,0x43, ++0x68,0x0C,0x00,0x00, ++0x20,0x34,0x54,0x69, ++0x6C,0x0C,0x00,0x00, ++0x94,0x00,0x3C,0x43, ++0x70,0x0C,0x00,0x00, ++0x0D,0x00,0x7F,0x2C, ++0x74,0x0C,0x00,0x00, ++0x5B,0x17,0x86,0x01, ++0x78,0x0C,0x00,0x00, ++0x1F,0x00,0x00,0x00, ++0x7C,0x0C,0x00,0x00, ++0x12,0x16,0xB9,0x00, ++0x80,0x0C,0x00,0x00, ++0x00,0x01,0x00,0x40, ++0x84,0x0C,0x00,0x00, ++0x00,0x00,0xF6,0x20, ++0x88,0x0C,0x00,0x00, ++0x80,0x00,0x00,0x20, ++0x8C,0x0C,0x00,0x00, ++0x00,0x00,0x20,0x20, ++0x90,0x0C,0x00,0x00, ++0x00,0x01,0x00,0x40, ++0x94,0x0C,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x98,0x0C,0x00,0x00, ++0x00,0x01,0x00,0x40, ++0x9C,0x0C,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0xA0,0x0C,0x00,0x00, ++0x92,0x24,0x49,0x00, ++0xA4,0x0C,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0xA8,0x0C,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0xAC,0x0C,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0xB0,0x0C,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0xB4,0x0C,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0xB8,0x0C,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0xBC,0x0C,0x00,0x00, ++0x00,0x00,0x00,0x28, ++0xC0,0x0C,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0xC4,0x0C,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0xC8,0x0C,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0xCC,0x0C,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0xD0,0x0C,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0xD4,0x0C,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0xD8,0x0C,0x00,0x00, ++0x27,0x24,0xB2,0x64, ++0xDC,0x0C,0x00,0x00, ++0x32,0x69,0x76,0x00, ++0xE0,0x0C,0x00,0x00, ++0x22,0x22,0x22,0x00, ++0xE4,0x0C,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0xE8,0x0C,0x00,0x00, ++0x02,0x43,0x64,0x37, ++0xEC,0x0C,0x00,0x00, ++0x0C,0xD4,0x97,0x2F, ++0x00,0x0D,0x00,0x00, ++0x50,0x07,0x00,0x00, ++0x04,0x0D,0x00,0x00, ++0x03,0x04,0x00,0x00, ++0x08,0x0D,0x00,0x00, ++0x7F,0x90,0x00,0x00, ++0x0C,0x0D,0x00,0x00, ++0x01,0x00,0x00,0x00, ++0x10,0x0D,0x00,0x00, ++0x33,0x33,0x63,0xA0, ++0x14,0x0D,0x00,0x00, ++0x63,0x3C,0x33,0x33, ++0x18,0x0D,0x00,0x00, ++0x6B,0x5B,0x8F,0x6A, ++0x1C,0x0D,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x20,0x0D,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x24,0x0D,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x28,0x0D,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x2C,0x0D,0x00,0x00, ++0x75,0x99,0x97,0xCC, ++0x30,0x0D,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x34,0x0D,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x38,0x0D,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x3C,0x0D,0x00,0x00, ++0x93,0x72,0x02,0x00, ++0x40,0x0D,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x44,0x0D,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x48,0x0D,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x50,0x0D,0x00,0x00, ++0x0A,0x14,0x37,0x64, ++0x54,0x0D,0x00,0x00, ++0x02,0xBD,0x4D,0x02, ++0x58,0x0D,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x5C,0x0D,0x00,0x00, ++0x64,0x20,0x03,0x30, ++0x60,0x0D,0x00,0x00, ++0x68,0xDE,0x53,0x46, ++0x64,0x0D,0x00,0x00, ++0x3C,0x8A,0x51,0x00, ++0x68,0x0D,0x00,0x00, ++0x01,0x21,0x00,0x00, ++0x14,0x0F,0x00,0x00, ++0x03,0x00,0x00,0x00, ++0x4C,0x0F,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x0F,0x00,0x00, ++0x00,0x03,0x00,0x00, ++0x40,0x01,0x00,0x00, ++0x04,0x00,0x00,0x00, ++0xFF,0x00,0x00,0x00, ++0x10,0x00,0x00,0x00, ++0x0C,0x02,0x01,0x80, ++0x10,0x00,0x00,0x00, ++0x3C,0x02,0x01,0x80, ++0x10,0x00,0x00,0x00, ++0x2C,0x08,0x01,0x80, ++0x10,0x00,0x00,0x00, ++0x34,0x08,0x01,0x80, ++0x10,0x00,0x00,0x00, ++0x3C,0x08,0x01,0x80, ++0x10,0x00,0x00,0x00, ++0x44,0x08,0x01,0x80, ++0x10,0x00,0x00,0x00, ++0x1C,0x08,0x01,0x80, ++0x10,0x00,0x00,0x00, ++0x24,0x08,0x01,0x80, ++0x10,0x00,0x00,0x00, ++0x7C,0x08,0x01,0x80, ++0x10,0x00,0x00,0x00, ++0x84,0x08,0x01,0x80, ++0x10,0x00,0x00,0x00, ++0xE0,0x03,0x01,0x80, ++0x10,0x00,0x00,0x00, ++0xD8,0x03,0x01,0x80, ++0x10,0x00,0x00,0x00, ++0x8C,0x08,0x01,0x80, ++0x10,0x00,0x00,0x00, ++0x94,0x08,0x01,0x80, ++0xDC,0x01,0x00,0x00, ++0x54,0x25,0x00,0x80, ++0x04,0x00,0x00,0x00, ++0x10,0x06,0x01,0x80, ++0xDC,0x01,0x00,0x00, ++0x54,0x25,0x00,0x80, ++0x04,0x00,0x00,0x00, ++0xD0,0x27,0x00,0x80, ++0x30,0x00,0x00,0x00, ++0xD8,0x27,0x00,0x80, ++0x04,0x00,0x00,0x00, ++0x64,0x2A,0x00,0x80, ++0x13,0x00,0x00,0x00, ++0xE8,0x06,0x01,0x80, ++0x17,0x00,0x00,0x00, ++0x3C,0x07,0x01,0x80, ++0x06,0x00,0x00,0x00, ++0xC4,0x07,0x01,0x80, ++0x06,0x00,0x00,0x00, ++0xCC,0x07,0x01,0x80, ++0x08,0x00,0x00,0x00, ++0xD4,0x07,0x01,0x80, ++0x0C,0x00,0x00,0x00, ++0xDC,0x07,0x01,0x80, ++0x04,0x00,0x00,0x00, ++0xE4,0x07,0x01,0x80, ++0x0E,0x00,0x00,0x00, ++0xEC,0x07,0x01,0x80, ++0x01,0x00,0x00,0x00, ++0xF4,0x07,0x01,0x80, ++0x38,0x00,0x00,0x00, ++0xFC,0x07,0x01,0x80, ++0x04,0x00,0x00,0x00, ++0x04,0x08,0x01,0x80, ++0x02,0x00,0x00,0x00, ++0x0C,0x08,0x01,0x80, ++0x04,0x00,0x00,0x00, ++0x14,0x08,0x01,0x80, ++0x01,0x00,0x00,0x00, ++0x54,0x08,0x01,0x80, ++0x01,0x00,0x00,0x00, ++0x5C,0x08,0x01,0x80, ++0x0C,0x00,0x00,0x00, ++0xE8,0x03,0x01,0x80, ++0x0E,0x00,0x00,0x00, ++0xF0,0x03,0x01,0x80, ++0x0C,0x00,0x00,0x00, ++0x08,0x06,0x01,0x80, ++0x34,0x00,0x00,0x00, ++0x64,0x08,0x01,0x80, ++0x04,0x00,0x00,0x00, ++0x6C,0x08,0x01,0x80, ++0x04,0x00,0x00,0x00, ++0x9C,0x08,0x01,0x80, ++0x04,0x00,0x00,0x00, ++0xA4,0x08,0x01,0x80, ++0x04,0x00,0x00,0x00, ++0xAC,0x08,0x01,0x80, ++0x04,0x00,0x00,0x00, ++0x74,0x08,0x01,0x80, ++0x08,0x00,0x00,0x00, ++0x40,0x03,0x01,0x80, ++0x04,0x00,0x00,0x00, ++0xB4,0x08,0x01,0x80, ++0x04,0x00,0x00,0x00, ++0x2C,0x09,0x01,0x80, ++0x04,0x00,0x00,0x00, ++0x38,0x09,0x01,0x80, ++0x04,0x00,0x00,0x00, ++0xEC,0x09,0x01,0x80, ++0x04,0x00,0x00,0x00, ++0x50,0x0C,0x01,0x80, ++0x04,0x00,0x00,0x00, ++0x60,0x0C,0x01,0x80, ++0x04,0x00,0x00,0x00, ++0xC8,0x0D,0x01,0x80, ++0x04,0x00,0x00,0x00, ++0xF4,0x0E,0x01,0x80, ++0x04,0x00,0x00,0x00, ++0x30,0x10,0x01,0x80, ++0x04,0x00,0x00,0x00, ++0x48,0x12,0x01,0x80, ++0x51,0x73,0x65,0x6C, ++0x20,0x45,0x72,0x72, ++0x6F,0x72,0x2C,0x20, ++0x25,0x78,0x00,0x00, ++0x72,0x65,0x70,0x65, ++0x61,0x74,0x65,0x64, ++0x20,0x65,0x6C,0x65, ++0x6D,0x65,0x6E,0x74, ++0x20,0x49,0x44,0x3A, ++0x20,0x25,0x78,0x2C, ++0x20,0x63,0x6D,0x64, ++0x20,0x73,0x65,0x71, ++0x3D,0x25,0x78,0x2C, ++0x20,0x68,0x32,0x64, ++0x73,0x65,0x71,0x3D, ++0x25,0x78,0x0A,0x00, ++0x69,0x6E,0x76,0x61, ++0x6C,0x69,0x64,0x20, ++0x63,0x6D,0x64,0x20, ++0x69,0x64,0x3A,0x20, ++0x25,0x78,0x0A,0x00, ++0x48,0x32,0x43,0x3A, ++0x20,0x25,0x78,0x0A, ++0x00,0x00,0x00,0x00, ++0x67,0x65,0x74,0x20, ++0x6A,0x6F,0x69,0x6E, ++0x20,0x63,0x6D,0x64, ++0x0A,0x00,0x00,0x00, ++0x4E,0x6F,0x20,0x69, ++0x72,0x70,0x20,0x25, ++0x73,0x0A,0x00,0x00, ++0x67,0x65,0x74,0x20, ++0x73,0x75,0x72,0x76, ++0x65,0x79,0x20,0x63, ++0x6D,0x64,0x0A,0x00, ++0x53,0x53,0x49,0x44, ++0x3A,0x20,0x25,0x73, ++0x0A,0x00,0x00,0x00, ++0x73,0x65,0x74,0x41, ++0x75,0x74,0x68,0x3A, ++0x20,0x25,0x78,0x0A, ++0x00,0x00,0x00,0x00, ++0x72,0x63,0x76,0x20, ++0x73,0x65,0x74,0x5F, ++0x73,0x74,0x61,0x6B, ++0x65,0x79,0x0A,0x00, ++0x53,0x65,0x74,0x53, ++0x69,0x6E,0x67,0x6C, ++0x65,0x43,0x61,0x72, ++0x72,0x69,0x65,0x72, ++0x54,0x78,0x5F,0x68, ++0x64,0x6C,0x0A,0x00, ++0x53,0x65,0x74,0x53, ++0x69,0x6E,0x67,0x6C, ++0x65,0x54,0x6F,0x6E, ++0x65,0x54,0x78,0x5F, ++0x68,0x64,0x6C,0x0A, ++0x00,0x00,0x00,0x00, ++0x53,0x65,0x74,0x43, ++0x61,0x72,0x72,0x69, ++0x65,0x72,0x53,0x75, ++0x70,0x70,0x72,0x65, ++0x73,0x73,0x69,0x6F, ++0x6E,0x54,0x78,0x5F, ++0x68,0x64,0x6C,0x0A, ++0x00,0x00,0x00,0x00, ++0x53,0x65,0x74,0x43, ++0x6F,0x6E,0x74,0x69, ++0x6E,0x75,0x6F,0x75, ++0x73,0x54,0x78,0x5F, ++0x68,0x64,0x6C,0x0A, ++0x00,0x00,0x00,0x00, ++0x53,0x65,0x74,0x43, ++0x43,0x4B,0x43,0x6F, ++0x6E,0x74,0x69,0x6E, ++0x75,0x6F,0x75,0x73, ++0x54,0x78,0x0A,0x00, ++0x53,0x65,0x74,0x4F, ++0x46,0x44,0x4D,0x43, ++0x6F,0x6E,0x74,0x69, ++0x6E,0x75,0x6F,0x75, ++0x73,0x54,0x78,0x0A, ++0x00,0x00,0x00,0x00, ++0x13,0x00,0x00,0x00, ++0xF8,0x9E,0x02,0x00, ++0x13,0x00,0x00,0x00, ++0xC8,0x5E,0x02,0x00, ++0x13,0x00,0x00,0x00, ++0xF8,0x0E,0x02,0x00, ++0x13,0x00,0x00,0x00, ++0xC8,0xCE,0x01,0x00, ++0x13,0x00,0x00,0x00, ++0xD4,0x8E,0x01,0x00, ++0x13,0x00,0x00,0x00, ++0xA4,0x4E,0x01,0x00, ++0x13,0x00,0x00,0x00, ++0xD0,0x0E,0x01,0x00, ++0x13,0x00,0x00,0x00, ++0xA0,0xCE,0x00,0x00, ++0x13,0x00,0x00,0x00, ++0xD0,0x86,0x00,0x00, ++0x13,0x00,0x00,0x00, ++0xA0,0x46,0x00,0x00, ++0x13,0x00,0x00,0x00, ++0x70,0x06,0x00,0x00, ++0x13,0x00,0x00,0x00, ++0xA4,0x9E,0x02,0x00, ++0x13,0x00,0x00,0x00, ++0x74,0x5E,0x02,0x00, ++0x13,0x00,0x00,0x00, ++0xA4,0x0E,0x02,0x00, ++0x13,0x00,0x00,0x00, ++0xD0,0xCE,0x01,0x00, ++0x13,0x00,0x00,0x00, ++0x40,0x9F,0x01,0x00, ++0x13,0x00,0x00,0x00, ++0x70,0x4E,0x01,0x00, ++0x13,0x00,0x00,0x00, ++0xA0,0x06,0x01,0x00, ++0x13,0x00,0x00,0x00, ++0x70,0xC6,0x00,0x00, ++0x13,0x00,0x00,0x00, ++0xA0,0x82,0x00,0x00, ++0x13,0x00,0x00,0x00, ++0x70,0x42,0x00,0x00, ++0x13,0x00,0x00,0x00, ++0x40,0x02,0x00,0x00, ++0xAA,0x88,0x88,0x44, ++0x44,0x22,0x22,0x00, ++0xAA,0x88,0x88,0x44, ++0x44,0x22,0x22,0x00, ++0xAA,0x88,0x88,0x44, ++0x44,0x22,0x22,0x00, ++0xAA,0x88,0x88,0x44, ++0x44,0x22,0x22,0x00, ++0xAA,0x88,0x88,0x44, ++0x44,0x22,0x22,0x00, ++0xAA,0x88,0x88,0x44, ++0x44,0x22,0x22,0x00, ++0xAA,0x88,0x88,0x44, ++0x44,0x22,0x22,0x00, ++0xAA,0x88,0x88,0x44, ++0x44,0x22,0x22,0x00, ++0xAA,0x88,0x88,0x44, ++0x44,0x22,0x22,0x00, ++0xAA,0x88,0x88,0x44, ++0x44,0x22,0x22,0x00, ++0xAA,0x88,0x88,0x44, ++0x44,0x22,0x22,0x00, ++0xAA,0x88,0x88,0x44, ++0x44,0x22,0x22,0x00, ++0x00,0x00,0x00,0x00, ++0x59,0x01,0x03,0x00, ++0x01,0x00,0x00,0x00, ++0x41,0x10,0x00,0x00, ++0x02,0x00,0x00,0x00, ++0x00,0x10,0x01,0x00, ++0x05,0x00,0x00,0x00, ++0xC0,0x0F,0x08,0x00, ++0x07,0x00,0x00,0x00, ++0x03,0xC8,0x0F,0x00, ++0x13,0x00,0x00,0x00, ++0xB0,0x7C,0x01,0x00, ++0x13,0x00,0x00,0x00, ++0xC0,0x1C,0x01,0x00, ++0x13,0x00,0x00,0x00, ++0x60,0xDC,0x00,0x00, ++0x13,0x00,0x00,0x00, ++0x60,0x8C,0x00,0x00, ++0x13,0x00,0x00,0x00, ++0x50,0x44,0x00,0x00, ++0x13,0x00,0x00,0x00, ++0x20,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x59,0x01,0x03,0x00, ++0x01,0x00,0x00,0x00, ++0x50,0x02,0x03,0x00, ++0x02,0x00,0x00,0x00, ++0x00,0x00,0x01,0x00, ++0x10,0x00,0x00,0x00, ++0x0F,0x00,0x08,0x00, ++0x11,0x00,0x00,0x00, ++0xFC,0x31,0x02,0x00, ++0x10,0x00,0x00,0x00, ++0x0F,0x00,0x0C,0x00, ++0x11,0x00,0x00,0x00, ++0xF8,0xF9,0x03,0x00, ++0x10,0x00,0x00,0x00, ++0x0F,0x00,0x02,0x00, ++0x11,0x00,0x00,0x00, ++0x01,0x01,0x02,0x00, ++0x14,0x00,0x00,0x00, ++0x3E,0x09,0x01,0x00, ++0x14,0x00,0x00,0x00, ++0x3E,0x09,0x09,0x00, ++0x15,0x00,0x00,0x00, ++0xF4,0x98,0x01,0x00, ++0x17,0x00,0x00,0x00, ++0x00,0x65,0x0F,0x00, ++0x1A,0x00,0x00,0x00, ++0x56,0x30,0x01,0x00, ++0x1B,0x00,0x00,0x00, ++0x00,0x00,0x06,0x00, ++0x1C,0x00,0x00,0x00, ++0x00,0x03,0x00,0x00, ++0x1E,0x00,0x00,0x00, ++0x59,0x10,0x03,0x00, ++0x21,0x00,0x00,0x00, ++0x00,0x40,0x05,0x00, ++0x22,0x00,0x00,0x00, ++0x3C,0x08,0x00,0x00, ++0x23,0x00,0x00,0x00, ++0x58,0x15,0x00,0x00, ++0x24,0x00,0x00,0x00, ++0x60,0x00,0x00,0x00, ++0x25,0x00,0x00,0x00, ++0x83,0x25,0x02,0x00, ++0x26,0x00,0x00,0x00, ++0x00,0xF2,0x00,0x00, ++0x27,0x00,0x00,0x00, ++0xF1,0xAC,0x0E,0x00, ++0x28,0x00,0x00,0x00, ++0x54,0xBD,0x09,0x00, ++0x29,0x00,0x00,0x00, ++0x82,0x45,0x00,0x00, ++0x2A,0x00,0x00,0x00, ++0x01,0x00,0x00,0x00, ++0x2B,0x00,0x00,0x00, ++0x34,0x13,0x02,0x00, ++0x2A,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x2B,0x00,0x00,0x00, ++0x0A,0x00,0x00,0x00, ++0x2A,0x00,0x00,0x00, ++0x01,0x00,0x00,0x00, ++0x2B,0x00,0x00,0x00, ++0x08,0x08,0x00,0x00, ++0x2B,0x00,0x00,0x00, ++0x33,0x33,0x05,0x00, ++0x2C,0x00,0x00,0x00, ++0x0C,0x00,0x00,0x00, ++0x2A,0x00,0x00,0x00, ++0x02,0x00,0x00,0x00, ++0x2B,0x00,0x00,0x00, ++0x08,0x08,0x00,0x00, ++0x2B,0x00,0x00,0x00, ++0x33,0xB3,0x05,0x00, ++0x2C,0x00,0x00,0x00, ++0x0D,0x00,0x00,0x00, ++0x2A,0x00,0x00,0x00, ++0x03,0x00,0x00,0x00, ++0x2B,0x00,0x00,0x00, ++0x08,0x08,0x00,0x00, ++0x2B,0x00,0x00,0x00, ++0x33,0x33,0x06,0x00, ++0x2C,0x00,0x00,0x00, ++0x0D,0x00,0x00,0x00, ++0x2A,0x00,0x00,0x00, ++0x04,0x00,0x00,0x00, ++0x2B,0x00,0x00,0x00, ++0x08,0x08,0x00,0x00, ++0x2B,0x00,0x00,0x00, ++0x33,0xB3,0x06,0x00, ++0x2C,0x00,0x00,0x00, ++0x0D,0x00,0x00,0x00, ++0x2A,0x00,0x00,0x00, ++0x05,0x00,0x00,0x00, ++0x2B,0x00,0x00,0x00, ++0x09,0x07,0x00,0x00, ++0x2B,0x00,0x00,0x00, ++0x33,0x33,0x05,0x00, ++0x2C,0x00,0x00,0x00, ++0x0D,0x00,0x00,0x00, ++0x2A,0x00,0x00,0x00, ++0x06,0x00,0x00,0x00, ++0x2B,0x00,0x00,0x00, ++0x09,0x07,0x00,0x00, ++0x2B,0x00,0x00,0x00, ++0x33,0xB3,0x05,0x00, ++0x2C,0x00,0x00,0x00, ++0x0D,0x00,0x00,0x00, ++0x2A,0x00,0x00,0x00, ++0x07,0x00,0x00,0x00, ++0x2B,0x00,0x00,0x00, ++0x09,0x07,0x00,0x00, ++0x2B,0x00,0x00,0x00, ++0x33,0x33,0x06,0x00, ++0x2C,0x00,0x00,0x00, ++0x0D,0x00,0x00,0x00, ++0x2A,0x00,0x00,0x00, ++0x08,0x00,0x00,0x00, ++0x2B,0x00,0x00,0x00, ++0x09,0x07,0x00,0x00, ++0x2B,0x00,0x00,0x00, ++0x33,0xB3,0x06,0x00, ++0x2C,0x00,0x00,0x00, ++0x0D,0x00,0x00,0x00, ++0x2A,0x00,0x00,0x00, ++0x09,0x00,0x00,0x00, ++0x2B,0x00,0x00,0x00, ++0x0A,0x06,0x00,0x00, ++0x2B,0x00,0x00,0x00, ++0x33,0x33,0x05,0x00, ++0x2C,0x00,0x00,0x00, ++0x0D,0x00,0x00,0x00, ++0x2A,0x00,0x00,0x00, ++0x0A,0x00,0x00,0x00, ++0x2B,0x00,0x00,0x00, ++0x0A,0x06,0x00,0x00, ++0x2B,0x00,0x00,0x00, ++0x33,0xB3,0x05,0x00, ++0x2C,0x00,0x00,0x00, ++0x0D,0x00,0x00,0x00, ++0x2A,0x00,0x00,0x00, ++0x0B,0x00,0x00,0x00, ++0x2B,0x00,0x00,0x00, ++0x0A,0x06,0x00,0x00, ++0x2B,0x00,0x00,0x00, ++0x33,0x33,0x06,0x00, ++0x2C,0x00,0x00,0x00, ++0x0D,0x00,0x00,0x00, ++0x2A,0x00,0x00,0x00, ++0x0C,0x00,0x00,0x00, ++0x2B,0x00,0x00,0x00, ++0x0A,0x06,0x00,0x00, ++0x2B,0x00,0x00,0x00, ++0x33,0xB3,0x06,0x00, ++0x2C,0x00,0x00,0x00, ++0x0D,0x00,0x00,0x00, ++0x2A,0x00,0x00,0x00, ++0x0D,0x00,0x00,0x00, ++0x2B,0x00,0x00,0x00, ++0x0B,0x05,0x00,0x00, ++0x2B,0x00,0x00,0x00, ++0x33,0x33,0x05,0x00, ++0x2C,0x00,0x00,0x00, ++0x0D,0x00,0x00,0x00, ++0x2A,0x00,0x00,0x00, ++0x0E,0x00,0x00,0x00, ++0x2B,0x00,0x00,0x00, ++0x0B,0x05,0x00,0x00, ++0x2B,0x00,0x00,0x00, ++0x23,0x66,0x06,0x00, ++0x2C,0x00,0x00,0x00, ++0x1A,0x00,0x00,0x00, ++0x2A,0x00,0x00,0x00, ++0x00,0x40,0x0E,0x00, ++0x30,0x00,0x00,0x00, ++0x00,0x00,0x02,0x00, ++0x31,0x00,0x00,0x00, ++0x31,0x96,0x0B,0x00, ++0x32,0x00,0x00,0x00, ++0x0D,0x13,0x00,0x00, ++0x33,0x00,0x00,0x00, ++0x87,0x01,0x00,0x00, ++0x13,0x00,0x00,0x00, ++0x6C,0x9E,0x01,0x00, ++0x13,0x00,0x00,0x00, ++0x94,0x5E,0x01,0x00, ++0x00,0x00,0x00,0x00, ++0x59,0x01,0x01,0x00, ++0x18,0x00,0x00,0x00, ++0x01,0xF4,0x00,0x00, ++0xFE,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x1E,0x00,0x00,0x00, ++0x5B,0x10,0x03,0x00, ++0xFE,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x59,0x01,0x03,0x00, ++0x10,0x00,0x00,0x00, ++0x0F,0x00,0x04,0x00, ++0x11,0x00,0x00,0x00, ++0xF9,0x03,0x02,0x00, ++0x6C,0x09,0x00,0x00, ++0x01,0x02,0x03,0x04, ++0x05,0x06,0x07,0x08, ++0x09,0x0A,0x0B,0x00, ++0x00,0x00,0x00,0x12, ++0x12,0x12,0x12,0x12, ++0x12,0x12,0x12,0x12, ++0x12,0x12,0x00,0x00, ++0x00,0x00,0x0F,0x0F, ++0x0F,0x0F,0x0F,0x0F, ++0x0F,0x0F,0x0F,0x0F, ++0x0F,0x00,0x00,0x00, ++0x00,0x17,0x05,0x03, ++0x22,0x43,0x5E,0x00, ++0x4F,0xA4,0x00,0x00, ++0x4F,0xA4,0x00,0x00, ++0x22,0x43,0x5E,0x00, ++0x4F,0xA4,0x00,0x00, ++0x22,0x43,0x5E,0x00, ++0x4F,0xA4,0x3E,0x00, ++0x30,0xA6,0x00,0x00, ++0x4F,0xA4,0x3E,0x00, ++0x2B,0xA4,0x5E,0x00, ++0x2B,0xA4,0x00,0x00, ++0x2B,0xA4,0x5E,0x00, ++0x22,0xA4,0x5E,0x00, ++0x4F,0xA4,0x00,0x00, ++0x4F,0xA4,0x00,0x00, ++0x4F,0xA4,0x5E,0x00, ++0x4F,0xA4,0x5E,0x00, ++0x4F,0xA4,0x5E,0x00, ++0x4F,0xA4,0x5E,0x00, ++0x4F,0xA4,0x00,0x00, ++0x4F,0xA4,0x5E,0x00, ++0x00,0xE0,0x4C,0x02, ++0x01,0x20,0x00,0x00, ++0x00,0xE0,0x4C,0x00, ++0x00,0x0C,0x43,0x00, ++0x00,0x50,0x43,0x00, ++0x00,0x40,0x96,0x00, ++0x00,0x05,0xB5,0x00, ++0x00,0x0A,0xF7,0x00, ++0x00,0x10,0x18,0x00, ++0x00,0x13,0x74,0x00, ++0x00,0x03,0x7F,0x00, ++0x00,0x50,0xF2,0x02, ++0x01,0x01,0x00,0x00, ++0x00,0x50,0xF2,0x02, ++0x00,0x01,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0xFF,0xFF,0xFF,0xFF, ++0xFF,0xFF,0x00,0x00, ++0x4F,0x6E,0x41,0x73, ++0x73,0x6F,0x63,0x52, ++0x65,0x71,0x00,0x00, ++0x4F,0x6E,0x41,0x73, ++0x73,0x6F,0x63,0x52, ++0x73,0x70,0x00,0x00, ++0x4F,0x6E,0x52,0x65, ++0x41,0x73,0x73,0x6F, ++0x63,0x52,0x65,0x71, ++0x00,0x00,0x00,0x00, ++0x4F,0x6E,0x52,0x65, ++0x41,0x73,0x73,0x6F, ++0x63,0x52,0x73,0x70, ++0x00,0x00,0x00,0x00, ++0x4F,0x6E,0x50,0x72, ++0x6F,0x62,0x65,0x52, ++0x65,0x71,0x00,0x00, ++0x4F,0x6E,0x50,0x72, ++0x6F,0x62,0x65,0x52, ++0x73,0x70,0x00,0x00, ++0x4F,0x6E,0x42,0x65, ++0x61,0x63,0x6F,0x6E, ++0x00,0x00,0x00,0x00, ++0x4F,0x6E,0x41,0x54, ++0x49,0x4D,0x00,0x00, ++0x4F,0x6E,0x44,0x69, ++0x73,0x61,0x73,0x73, ++0x6F,0x63,0x00,0x00, ++0x4F,0x6E,0x41,0x75, ++0x74,0x68,0x00,0x00, ++0x4F,0x6E,0x44,0x65, ++0x41,0x75,0x74,0x68, ++0x00,0x00,0x00,0x00, ++0x4F,0x6E,0x41,0x63, ++0x74,0x69,0x6F,0x6E, ++0x00,0x00,0x00,0x00, ++0x4F,0x6E,0x45,0x78, ++0x63,0x65,0x70,0x74, ++0x69,0x6F,0x6E,0x00, ++0x00,0x00,0x00,0x00, ++0xF8,0xDD,0x01,0x80, ++0xE8,0x26,0x01,0x80, ++0x10,0x00,0x00,0x00, ++0x04,0xDE,0x01,0x80, ++0xF0,0x26,0x01,0x80, ++0x20,0x00,0x00,0x00, ++0x10,0xDE,0x01,0x80, ++0xE8,0x26,0x01,0x80, ++0x30,0x00,0x00,0x00, ++0x20,0xDE,0x01,0x80, ++0xF0,0x26,0x01,0x80, ++0x40,0x00,0x00,0x00, ++0x30,0xDE,0x01,0x80, ++0x80,0x2D,0x01,0x80, ++0x50,0x00,0x00,0x00, ++0x3C,0xDE,0x01,0x80, ++0x28,0x4A,0x00,0x80, ++0x80,0x00,0x00,0x00, ++0x48,0xDE,0x01,0x80, ++0x90,0x59,0x00,0x80, ++0x90,0x00,0x00,0x00, ++0x54,0xDE,0x01,0x80, ++0x44,0x2E,0x01,0x80, ++0xA0,0x00,0x00,0x00, ++0x5C,0xDE,0x01,0x80, ++0x4C,0x2E,0x01,0x80, ++0xB0,0x00,0x00,0x00, ++0x68,0xDE,0x01,0x80, ++0x54,0x2F,0x01,0x80, ++0xC0,0x00,0x00,0x00, ++0x70,0xDE,0x01,0x80, ++0x6C,0x2E,0x01,0x80, ++0xD0,0x00,0x00,0x00, ++0x7C,0xDE,0x01,0x80, ++0xF0,0x54,0x00,0x80, ++0x0C,0x00,0x00,0x00, ++0x88,0xDE,0x01,0x80, ++0x8C,0x2E,0x01,0x80, ++0x73,0x77,0x69,0x74, ++0x63,0x68,0x20,0x74, ++0x6F,0x20,0x34,0x30, ++0x4D,0x20,0x48,0x7A, ++0x20,0x6D,0x6F,0x64, ++0x65,0x28,0x25,0x78, ++0x2C,0x20,0x25,0x78, ++0x29,0x0A,0x00,0x00, ++0x73,0x77,0x69,0x74, ++0x63,0x68,0x20,0x74, ++0x6F,0x20,0x32,0x30, ++0x4D,0x20,0x48,0x7A, ++0x20,0x6D,0x6F,0x64, ++0x65,0x0A,0x00,0x00, ++0x41,0x54,0x49,0x4D, ++0x3A,0x20,0x25,0x78, ++0x0A,0x00,0x00,0x00, ++0x4E,0x6F,0x20,0x69, ++0x72,0x70,0x20,0x25, ++0x73,0x0A,0x00,0x00, ++0x73,0x75,0x72,0x76, ++0x65,0x79,0x20,0x64, ++0x6F,0x6E,0x65,0x28, ++0x25,0x78,0x2C,0x20, ++0x25,0x78,0x29,0x0A, ++0x00,0x00,0x00,0x00, ++0x4E,0x6F,0x20,0x69, ++0x72,0x70,0x20,0x25, ++0x73,0x0A,0x00,0x00, ++0x6A,0x6F,0x69,0x6E, ++0x20,0x72,0x65,0x73, ++0x28,0x25,0x78,0x29, ++0x0A,0x00,0x00,0x00, ++0x4E,0x6F,0x20,0x69, ++0x72,0x70,0x20,0x25, ++0x73,0x0A,0x00,0x00, ++0x64,0x65,0x6C,0x20, ++0x73,0x74,0x61,0x0A, ++0x00,0x00,0x00,0x00, ++0x4E,0x6F,0x20,0x69, ++0x72,0x70,0x20,0x25, ++0x73,0x0A,0x00,0x00, ++0x61,0x64,0x64,0x20, ++0x73,0x74,0x61,0x3A, ++0x25,0x78,0x2C,0x20, ++0x25,0x78,0x0A,0x00, ++0x72,0x63,0x76,0x20, ++0x64,0x69,0x73,0x63, ++0x6F,0x6E,0x6E,0x65, ++0x63,0x74,0x0A,0x00, ++0x64,0x69,0x73,0x63, ++0x6F,0x6E,0x6E,0x65, ++0x63,0x74,0x20,0x74, ++0x69,0x6D,0x65,0x72, ++0x3A,0x20,0x6E,0x6F, ++0x20,0x62,0x65,0x61, ++0x63,0x6F,0x6E,0x0A, ++0x00,0x00,0x00,0x00, ++0x64,0x69,0x73,0x63, ++0x6F,0x6E,0x6E,0x65, ++0x63,0x74,0x20,0x74, ++0x69,0x6D,0x65,0x72, ++0x0A,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x4E,0x6F,0x20,0x69, ++0x72,0x70,0x20,0x40, ++0x25,0x73,0x0A,0x00, ++0x57,0x4D,0x4D,0x28, ++0x25,0x78,0x29,0x3A, ++0x20,0x25,0x78,0x2C, ++0x20,0x25,0x78,0x0A, ++0x00,0x00,0x00,0x00, ++0x61,0x73,0x73,0x6F, ++0x63,0x20,0x72,0x65, ++0x6A,0x65,0x63,0x74, ++0x2C,0x20,0x73,0x74, ++0x61,0x74,0x75,0x73, ++0x3A,0x20,0x25,0x64, ++0x0A,0x00,0x00,0x00, ++0x6D,0x61,0x63,0x20, ++0x69,0x64,0x20,0x23, ++0x34,0x3A,0x20,0x25, ++0x78,0x2C,0x20,0x25, ++0x78,0x0A,0x00,0x00, ++0x6D,0x61,0x63,0x20, ++0x69,0x64,0x20,0x23, ++0x35,0x3A,0x20,0x25, ++0x78,0x2C,0x20,0x25, ++0x78,0x2C,0x20,0x25, ++0x78,0x0A,0x00,0x00, ++0x4E,0x6F,0x20,0x69, ++0x72,0x70,0x20,0x40, ++0x25,0x73,0x0A,0x00, ++0x4E,0x6F,0x20,0x69, ++0x72,0x70,0x20,0x25, ++0x73,0x0A,0x00,0x00, ++0x63,0x75,0x72,0x20, ++0x63,0x68,0x61,0x6E, ++0x6E,0x65,0x6C,0x3A, ++0x20,0x25,0x78,0x2C, ++0x20,0x62,0x63,0x6E, ++0x20,0x69,0x6E,0x74, ++0x65,0x72,0x76,0x61, ++0x6C,0x3A,0x20,0x25, ++0x78,0x0A,0x00,0x00, ++0x49,0x42,0x53,0x53, ++0x20,0x6D,0x6F,0x64, ++0x65,0x2C,0x20,0x63, ++0x75,0x72,0x20,0x63, ++0x68,0x61,0x6E,0x6E, ++0x65,0x6C,0x3A,0x20, ++0x25,0x78,0x2C,0x20, ++0x62,0x63,0x6E,0x20, ++0x69,0x6E,0x74,0x65, ++0x72,0x76,0x61,0x6C, ++0x3A,0x20,0x25,0x78, ++0x0A,0x00,0x00,0x00, ++0x6D,0x61,0x63,0x20, ++0x69,0x64,0x20,0x23, ++0x34,0x3A,0x20,0x25, ++0x78,0x2C,0x20,0x25, ++0x78,0x0A,0x00,0x00, ++0x69,0x6E,0x76,0x61, ++0x6C,0x69,0x64,0x20, ++0x63,0x61,0x70,0x3A, ++0x25,0x78,0x0A,0x00, ++0x4E,0x6F,0x20,0x69, ++0x72,0x70,0x20,0x25, ++0x73,0x0A,0x00,0x00, ++0x69,0x73,0x73,0x75, ++0x65,0x20,0x61,0x73, ++0x73,0x6F,0x63,0x72, ++0x65,0x71,0x28,0x25, ++0x78,0x29,0x0A,0x00, ++0x5B,0x57,0x41,0x50, ++0x49,0x5D,0x20,0x67, ++0x65,0x74,0x20,0x77, ++0x61,0x70,0x69,0x20, ++0x49,0x45,0x0A,0x00, ++0x4E,0x6F,0x20,0x69, ++0x72,0x70,0x20,0x25, ++0x73,0x0A,0x00,0x00, ++0x69,0x73,0x73,0x75, ++0x65,0x20,0x61,0x63, ++0x74,0x69,0x6F,0x6E, ++0x3A,0x20,0x25,0x78, ++0x2C,0x20,0x25,0x78, ++0x2C,0x20,0x25,0x78, ++0x20,0x0A,0x00,0x00, ++0x41,0x44,0x44,0x42, ++0x41,0x20,0x52,0x53, ++0x50,0x3A,0x20,0x25, ++0x78,0x0A,0x00,0x00, ++0x44,0x45,0x4C,0x42, ++0x41,0x3A,0x20,0x25, ++0x78,0x28,0x25,0x78, ++0x29,0x0A,0x00,0x00, ++0x4E,0x6F,0x20,0x69, ++0x72,0x70,0x20,0x25, ++0x73,0x0A,0x00,0x00, ++0x69,0x73,0x73,0x75, ++0x65,0x20,0x61,0x75, ++0x74,0x68,0x0A,0x00, ++0x63,0x6C,0x6E,0x74, ++0x20,0x61,0x75,0x74, ++0x68,0x20,0x66,0x61, ++0x69,0x6C,0x2C,0x20, ++0x73,0x74,0x61,0x74, ++0x75,0x73,0x3A,0x20, ++0x25,0x64,0x0A,0x00, ++0x6E,0x6F,0x20,0x63, ++0x68,0x61,0x6C,0x6C, ++0x65,0x6E,0x67,0x65, ++0x20,0x74,0x65,0x78, ++0x74,0x3F,0x0A,0x00, ++0x63,0x6C,0x6E,0x74, ++0x20,0x61,0x75,0x74, ++0x68,0x20,0x66,0x61, ++0x69,0x6C,0x65,0x64, ++0x20,0x64,0x75,0x65, ++0x20,0x74,0x6F,0x20, ++0x69,0x6C,0x6C,0x65, ++0x67,0x61,0x6C,0x20, ++0x73,0x65,0x71,0x3D, ++0x25,0x78,0x0A,0x00, ++0x4E,0x6F,0x20,0x69, ++0x72,0x70,0x20,0x25, ++0x73,0x0A,0x00,0x00, ++0x69,0x73,0x73,0x75, ++0x65,0x5F,0x64,0x65, ++0x61,0x75,0x74,0x68, ++0x0A,0x00,0x00,0x00, ++0x4E,0x6F,0x20,0x69, ++0x72,0x70,0x20,0x25, ++0x73,0x0A,0x00,0x00, ++0x69,0x73,0x73,0x75, ++0x65,0x5F,0x64,0x69, ++0x73,0x61,0x73,0x73, ++0x6F,0x63,0x0A,0x00, ++0x4E,0x6F,0x20,0x69, ++0x72,0x70,0x20,0x25, ++0x73,0x0A,0x00,0x00, ++0x4E,0x6F,0x20,0x69, ++0x72,0x70,0x20,0x25, ++0x73,0x0A,0x00,0x00, ++0x69,0x73,0x73,0x75, ++0x65,0x20,0x6E,0x75, ++0x6C,0x6C,0x20,0x64, ++0x61,0x74,0x61,0x28, ++0x25,0x64,0x29,0x00, ++0x6C,0x69,0x6E,0x6B, ++0x20,0x74,0x6F,0x20, ++0x41,0x72,0x74,0x68, ++0x65,0x72,0x6F,0x73, ++0x20,0x41,0x50,0x0A, ++0x00,0x00,0x00,0x00, ++0x6C,0x69,0x6E,0x6B, ++0x20,0x74,0x6F,0x20, ++0x42,0x72,0x6F,0x61, ++0x64,0x63,0x6F,0x6D, ++0x20,0x41,0x50,0x0A, ++0x00,0x00,0x00,0x00, ++0x6C,0x69,0x6E,0x6B, ++0x20,0x74,0x6F,0x20, ++0x4D,0x61,0x72,0x76, ++0x65,0x6C,0x6C,0x20, ++0x41,0x50,0x0A,0x00, ++0x6C,0x69,0x6E,0x6B, ++0x20,0x74,0x6F,0x20, ++0x52,0x61,0x6C,0x69, ++0x6E,0x6B,0x20,0x41, ++0x50,0x0A,0x00,0x00, ++0x6C,0x69,0x6E,0x6B, ++0x20,0x74,0x6F,0x20, ++0x43,0x69,0x73,0x63, ++0x6F,0x20,0x41,0x50, ++0x0A,0x00,0x00,0x00, ++0x6C,0x69,0x6E,0x6B, ++0x20,0x74,0x6F,0x20, ++0x52,0x65,0x61,0x6C, ++0x74,0x65,0x6B,0x20, ++0x39,0x36,0x42,0x20, ++0x41,0x50,0x0A,0x00, ++0x6C,0x69,0x6E,0x6B, ++0x20,0x74,0x6F,0x20, ++0x75,0x6E,0x6B,0x6E, ++0x6F,0x77,0x6E,0x20, ++0x41,0x50,0x0A,0x00, ++0x6D,0x61,0x63,0x20, ++0x69,0x64,0x20,0x23, ++0x25,0x78,0x3A,0x20, ++0x25,0x78,0x2C,0x20, ++0x25,0x78,0x0A,0x00, ++0x64,0x72,0x6F,0x70, ++0x20,0x64,0x75,0x65, ++0x20,0x74,0x6F,0x20, ++0x64,0x65,0x63,0x61, ++0x63,0x68,0x65,0x0A, ++0x00,0x00,0x00,0x00, ++0xFF,0x00,0x00,0x00, ++0x01,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0xFF,0xFF,0x00,0x00, ++0x01,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x01,0x02,0x03, ++0xFF,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x01,0x02,0x03, ++0x04,0x05,0x06,0x07, ++0x08,0x09,0x0A,0x0B, ++0xFF,0x00,0x00,0x00, ++0x04,0x05,0x06,0x07, ++0x08,0x09,0x0A,0x0B, ++0xFF,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x04,0x05,0x06,0x07, ++0x08,0xFF,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x01,0x02,0x03, ++0xFF,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x01,0x01,0x03, ++0xFF,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x30,0x31,0x32,0x33, ++0x34,0x35,0x36,0x37, ++0x38,0x39,0x41,0x42, ++0x43,0x44,0x45,0x46, ++0x00,0x00,0x00,0x00, ++0x25,0x64,0x2E,0x00, ++0x25,0x68,0x68,0x58, ++0x3A,0x00,0x00,0x00, ++0x74,0x61,0x72,0x67, ++0x65,0x74,0x20,0x74, ++0x68,0x65,0x72,0x6D, ++0x61,0x6C,0x3A,0x20, ++0x25,0x78,0x2C,0x20, ++0x63,0x75,0x72,0x20, ++0x74,0x68,0x65,0x72, ++0x6D,0x61,0x6C,0x3A, ++0x20,0x25,0x78,0x0A, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x08,0xE4,0x01,0x80, ++0x08,0xE4,0x01,0x80, ++0x31,0x10,0x10,0x00, ++0x00,0x30,0x00,0x00, ++0x31,0x20,0x10,0x00, ++0x00,0x30,0x00,0x00, ++0x31,0x28,0x10,0x00, ++0x00,0x30,0x00,0x00, ++0x31,0x2C,0x10,0x10, ++0x00,0x30,0x00,0x00, ++0x31,0x2F,0x10,0x10, ++0x00,0x30,0x00,0x00, ++0x31,0x30,0x18,0x00, ++0x00,0x30,0x00,0x00, ++0x31,0x30,0x20,0x10, ++0x00,0x30,0x00,0x00, ++0x22,0x20,0x18,0x08, ++0x00,0x20,0x00,0x00, ++0x22,0x21,0x14,0x08, ++0x00,0x20,0x00,0x00, ++0x22,0x21,0x1C,0x08, ++0x00,0x20,0x00,0x00, ++0x22,0x21,0x20,0x08, ++0x00,0x20,0x00,0x00, ++0x22,0x21,0x20,0x10, ++0x00,0x20,0x00,0x00, ++0x22,0x21,0x20,0x18, ++0x00,0x20,0x00,0x00, ++0x1A,0x19,0x18,0x10, ++0x00,0x18,0x00,0x00, ++0x12,0x11,0x10,0x08, ++0x00,0x10,0x00,0x00, ++0x0A,0x09,0x08,0x00, ++0x00,0x08,0x00,0x00, ++0x0A,0x09,0x08,0x02, ++0x00,0x08,0x00,0x00, ++0x0A,0x09,0x08,0x04, ++0x00,0x08,0x00,0x00, ++0x0A,0x09,0x08,0x06, ++0x00,0x08,0x00,0x00, ++0x08,0x07,0x06,0x04, ++0x00,0x06,0x00,0x00, ++0x06,0x05,0x04,0x02, ++0x00,0x04,0x00,0x00, ++0x06,0x05,0x04,0x03, ++0x00,0x04,0x00,0x00, ++0x05,0x04,0x03,0x02, ++0x00,0x03,0x00,0x00, ++0x09,0x08,0x07,0x06, ++0x07,0x06,0x06,0x05, ++0x05,0x04,0x04,0x03, ++0x06,0x05,0x05,0x04, ++0x04,0x03,0x03,0x03, ++0x05,0x04,0x04,0x03, ++0x03,0x02,0x02,0x02, ++0x00,0x09,0x08,0x07, ++0x06,0x07,0x06,0x06, ++0x05,0x05,0x04,0x04, ++0x03,0x05,0x04,0x04, ++0x03,0x03,0x02,0x02, ++0x02,0x04,0x03,0x03, ++0x02,0x02,0x01,0x01, ++0x01,0x00,0x00,0x00, ++0x08,0x08,0x08,0x08, ++0x08,0x08,0x08,0x08, ++0x08,0x10,0x10,0x20, ++0x08,0x08,0x08,0x08, ++0x20,0x20,0x20,0x20, ++0x08,0x08,0x08,0x08, ++0x08,0x20,0x20,0x20, ++0x30,0x08,0x08,0x08, ++0x08,0x18,0x18,0x18, ++0x18,0x18,0x20,0x30, ++0x30,0x10,0x20,0x20, ++0x20,0x20,0x20,0x30, ++0x30,0x08,0x10,0x20, ++0x30,0x30,0x30,0x30, ++0x30,0x30,0x00,0x00, ++0x08,0x08,0x08,0x08, ++0x08,0x08,0x08,0x08, ++0x08,0x10,0x10,0x20, ++0x08,0x08,0x08,0x08, ++0x08,0x20,0x20,0x20, ++0x08,0x08,0x08,0x08, ++0x08,0x20,0x20,0x20, ++0x20,0x08,0x08,0x08, ++0x08,0x18,0x18,0x18, ++0x18,0x18,0x20,0x30, ++0x30,0x10,0x20,0x20, ++0x20,0x20,0x20,0x30, ++0x30,0x08,0x10,0x20, ++0x30,0x30,0x30,0x30, ++0x30,0x30,0x00,0x00, ++0x0A,0x09,0x08,0x04, ++0x00,0x0A,0x09,0x08, ++0x04,0x00,0x0A,0x09, ++0x08,0x04,0x00,0x0A, ++0x09,0x08,0x04,0x00, ++0x0A,0x09,0x08,0x00, ++0x00,0x0A,0x09,0x08, ++0x00,0x00,0x0A,0x09, ++0x08,0x00,0x00,0x0A, ++0x09,0x08,0x00,0x00, ++0x0A,0x09,0x08,0x00, ++0x00,0x12,0x11,0x10, ++0x08,0x00,0x12,0x11, ++0x10,0x08,0x00,0x22, ++0x21,0x20,0x18,0x00, ++0x0A,0x09,0x08,0x00, ++0x00,0x0A,0x09,0x08, ++0x00,0x00,0x0A,0x09, ++0x08,0x00,0x00,0x0A, ++0x09,0x08,0x00,0x00, ++0x22,0x21,0x20,0x18, ++0x00,0x22,0x21,0x20, ++0x18,0x00,0x22,0x21, ++0x1C,0x08,0x00,0x22, ++0x20,0x18,0x08,0x00, ++0x0A,0x09,0x08,0x02, ++0x00,0x0A,0x09,0x08, ++0x02,0x00,0x0A,0x09, ++0x08,0x02,0x00,0x0A, ++0x09,0x08,0x02,0x00, ++0x0A,0x09,0x08,0x00, ++0x00,0x22,0x21,0x20, ++0x10,0x00,0x22,0x21, ++0x20,0x08,0x00,0x22, ++0x21,0x1C,0x08,0x00, ++0x31,0x30,0x18,0x00, ++0x00,0x0A,0x09,0x08, ++0x04,0x00,0x0A,0x09, ++0x08,0x04,0x00,0x0A, ++0x09,0x08,0x04,0x00, ++0x0A,0x09,0x08,0x04, ++0x00,0x1A,0x19,0x18, ++0x10,0x00,0x1A,0x19, ++0x18,0x10,0x00,0x1A, ++0x19,0x18,0x10,0x00, ++0x1A,0x19,0x18,0x10, ++0x00,0x1A,0x19,0x18, ++0x10,0x00,0x22,0x21, ++0x20,0x08,0x00,0x31, ++0x2C,0x10,0x10,0x00, ++0x31,0x28,0x10,0x00, ++0x00,0x12,0x11,0x10, ++0x08,0x00,0x22,0x21, ++0x20,0x18,0x00,0x22, ++0x21,0x20,0x18,0x00, ++0x22,0x21,0x20,0x08, ++0x00,0x22,0x21,0x14, ++0x08,0x00,0x22,0x20, ++0x18,0x08,0x00,0x31, ++0x30,0x20,0x10,0x00, ++0x31,0x2C,0x10,0x10, ++0x00,0x0A,0x09,0x08, ++0x00,0x00,0x12,0x11, ++0x10,0x08,0x00,0x22, ++0x21,0x20,0x18,0x00, ++0x22,0x21,0x20,0x18, ++0x00,0x31,0x30,0x20, ++0x10,0x00,0x31,0x2F, ++0x10,0x10,0x00,0x31, ++0x2F,0x10,0x10,0x00, ++0x31,0x10,0x10,0x00, ++0x00,0x31,0x2C,0x10, ++0x10,0x00,0x00,0x00, ++0x0A,0x09,0x08,0x04, ++0x00,0x0A,0x09,0x08, ++0x04,0x00,0x0A,0x09, ++0x08,0x04,0x00,0x0A, ++0x09,0x08,0x04,0x00, ++0x0A,0x09,0x08,0x00, ++0x00,0x0A,0x09,0x08, ++0x00,0x00,0x0A,0x09, ++0x08,0x00,0x00,0x0A, ++0x09,0x08,0x00,0x00, ++0x0A,0x09,0x08,0x00, ++0x00,0x12,0x11,0x10, ++0x08,0x00,0x12,0x11, ++0x10,0x08,0x00,0x22, ++0x21,0x20,0x18,0x00, ++0x0A,0x09,0x08,0x04, ++0x00,0x0A,0x09,0x08, ++0x04,0x00,0x0A,0x09, ++0x08,0x02,0x00,0x0A, ++0x09,0x08,0x00,0x00, ++0x0A,0x09,0x08,0x00, ++0x00,0x22,0x21,0x20, ++0x18,0x00,0x22,0x21, ++0x1C,0x08,0x00,0x22, ++0x21,0x14,0x08,0x00, ++0x0A,0x09,0x08,0x02, ++0x00,0x0A,0x09,0x08, ++0x02,0x00,0x0A,0x09, ++0x08,0x02,0x00,0x0A, ++0x09,0x08,0x02,0x00, ++0x0A,0x09,0x08,0x00, ++0x00,0x22,0x21,0x20, ++0x10,0x00,0x22,0x21, ++0x20,0x08,0x00,0x22, ++0x21,0x14,0x08,0x00, ++0x22,0x21,0x14,0x08, ++0x00,0x0A,0x09,0x08, ++0x04,0x00,0x0A,0x09, ++0x08,0x04,0x00,0x0A, ++0x09,0x08,0x04,0x00, ++0x0A,0x09,0x08,0x04, ++0x00,0x1A,0x19,0x18, ++0x10,0x00,0x1A,0x19, ++0x18,0x10,0x00,0x1A, ++0x19,0x18,0x10,0x00, ++0x1A,0x19,0x18,0x10, ++0x00,0x1A,0x19,0x18, ++0x10,0x00,0x22,0x21, ++0x20,0x08,0x00,0x31, ++0x2C,0x10,0x10,0x00, ++0x31,0x28,0x10,0x00, ++0x00,0x12,0x11,0x10, ++0x08,0x00,0x22,0x21, ++0x20,0x18,0x00,0x22, ++0x21,0x20,0x18,0x00, ++0x22,0x21,0x20,0x08, ++0x00,0x22,0x21,0x14, ++0x08,0x00,0x22,0x20, ++0x18,0x08,0x00,0x31, ++0x30,0x20,0x10,0x00, ++0x31,0x2C,0x10,0x10, ++0x00,0x0A,0x09,0x08, ++0x00,0x00,0x12,0x11, ++0x10,0x08,0x00,0x22, ++0x21,0x20,0x18,0x00, ++0x22,0x21,0x20,0x18, ++0x00,0x31,0x30,0x20, ++0x10,0x00,0x31,0x2F, ++0x10,0x10,0x00,0x31, ++0x2F,0x10,0x10,0x00, ++0x31,0x10,0x10,0x00, ++0x00,0x31,0x2C,0x10, ++0x10,0x00,0x00,0x00, ++0x01,0x02,0x04,0x08, ++0x02,0x04,0x08,0x0C, ++0x10,0x18,0x20,0x30, ++0x02,0x04,0x08,0x0C, ++0x10,0x18,0x20,0x30, ++0x06,0x0C,0x10,0x18, ++0x24,0x30,0x3C,0x48, ++0x48,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x25,0x27,0x2C, ++0x19,0x1B,0x1E,0x20, ++0x23,0x29,0x2A,0x2B, ++0x00,0x00,0x00,0x00, ++0x25,0x29,0x2B,0x2E, ++0x2E,0x00,0x00,0x00, ++0x04,0x00,0x00,0x00, ++0x04,0x00,0x00,0x00, ++0x08,0x00,0x00,0x00, ++0x10,0x00,0x00,0x00, ++0x18,0x00,0x00,0x00, ++0x24,0x00,0x00,0x00, ++0x30,0x00,0x00,0x00, ++0x48,0x00,0x00,0x00, ++0x60,0x00,0x00,0x00, ++0x90,0x00,0x00,0x00, ++0xC0,0x00,0x00,0x00, ++0xD8,0x00,0x00,0x00, ++0x50,0x00,0x00,0x00, ++0x78,0x00,0x00,0x00, ++0xA0,0x00,0x00,0x00, ++0xC8,0x00,0x00,0x00, ++0x40,0x01,0x00,0x00, ++0x90,0x01,0x00,0x00, ++0xE0,0x01,0x00,0x00, ++0x30,0x02,0x00,0x00, ++0x2C,0x01,0x00,0x00, ++0x40,0x01,0x00,0x00, ++0xE0,0x01,0x00,0x00, ++0xD0,0x02,0x00,0x00, ++0x80,0x0C,0x00,0x00, ++0x80,0x0C,0x00,0x00, ++0x80,0x0C,0x00,0x00, ++0xA0,0x0F,0x00,0x00, ++0xA0,0x0F,0x00,0x00, ++0x02,0x00,0x00,0x00, ++0x02,0x00,0x00,0x00, ++0x04,0x00,0x00,0x00, ++0x08,0x00,0x00,0x00, ++0x0C,0x00,0x00,0x00, ++0x12,0x00,0x00,0x00, ++0x18,0x00,0x00,0x00, ++0x24,0x00,0x00,0x00, ++0x30,0x00,0x00,0x00, ++0x48,0x00,0x00,0x00, ++0x60,0x00,0x00,0x00, ++0x6C,0x00,0x00,0x00, ++0x28,0x00,0x00,0x00, ++0x3C,0x00,0x00,0x00, ++0x50,0x00,0x00,0x00, ++0x64,0x00,0x00,0x00, ++0xA0,0x00,0x00,0x00, ++0xC8,0x00,0x00,0x00, ++0xF0,0x00,0x00,0x00, ++0x18,0x01,0x00,0x00, ++0x64,0x00,0x00,0x00, ++0xA0,0x00,0x00,0x00, ++0xF0,0x00,0x00,0x00, ++0x68,0x01,0x00,0x00, ++0x40,0x06,0x00,0x00, ++0x40,0x06,0x00,0x00, ++0x40,0x06,0x00,0x00, ++0xD0,0x07,0x00,0x00, ++0xD0,0x07,0x00,0x00, ++0x72,0x65,0x73,0x65, ++0x74,0x28,0x25,0x78, ++0x29,0x0A,0x00,0x00, ++0xC8,0x82,0x01,0x80, ++0xC8,0xD0,0x00,0x80, ++0xC8,0xD0,0x00,0x80, ++0xC8,0xD0,0x00,0x80, ++0xC8,0xD0,0x00,0x80, ++0x14,0xCF,0x00,0x80, ++0xD0,0x82,0x01,0x80, ++0xC8,0x82,0x01,0x80, ++0xC8,0x82,0x01,0x80, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0xF0,0x85,0x01,0x80, ++0xF0,0x85,0x01,0x80, ++0xF0,0x85,0x01,0x80, ++0xF0,0x85,0x01,0x80, ++0xA8,0x82,0x01,0x80, ++0x00,0x85,0x01,0x80, ++0xB0,0x82,0x01,0x80, ++0xB8,0x82,0x01,0x80, ++0xC0,0x82,0x01,0x80, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x08,0x04,0x04,0x08, ++0x02,0x02,0x01,0x01, ++0x50,0x53,0x00,0x00, ++0x80,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0xA0,0xA4,0x01,0x80, ++0x70,0xA3,0x01,0x80, ++0x70,0xA3,0x01,0x80, ++0x70,0xA3,0x01,0x80, ++0x68,0xA4,0x01,0x80, ++0x70,0xA3,0x01,0x80, ++0x70,0xA3,0x01,0x80, ++0x70,0xA3,0x01,0x80, ++0x30,0xA4,0x01,0x80, ++0x70,0xA3,0x01,0x80, ++0x70,0xA3,0x01,0x80, ++0x70,0xA3,0x01,0x80, ++0x70,0xA3,0x01,0x80, ++0x70,0xA3,0x01,0x80, ++0x70,0xA3,0x01,0x80, ++0x70,0xA3,0x01,0x80, ++0xF8,0xA3,0x01,0x80, ++0x70,0xA3,0x01,0x80, ++0x70,0xA3,0x01,0x80, ++0x70,0xA3,0x01,0x80, ++0xC0,0xA3,0x01,0x80, ++0x70,0xA3,0x01,0x80, ++0x70,0xA3,0x01,0x80, ++0x70,0xA3,0x01,0x80, ++0x88,0xA3,0x01,0x80, ++0x70,0xA3,0x01,0x80, ++0x70,0xA3,0x01,0x80, ++0x70,0xA3,0x01,0x80, ++0x48,0xA3,0x01,0x80, ++0xB8,0x06,0x00,0x80, ++0xAC,0x06,0x00,0x80, ++0xA0,0x06,0x00,0x80, ++0x94,0x06,0x00,0x80, ++0x88,0x06,0x00,0x80, ++0x7C,0x06,0x00,0x80, ++0x70,0x06,0x00,0x80, ++0x64,0x06,0x00,0x80, ++0x58,0x06,0x00,0x80, ++0x4C,0x06,0x00,0x80, ++0x04,0x06,0x00,0x80, ++0x30,0x1F,0x02,0x80, ++0xB0,0x03,0x25,0xB0, ++0x30,0x1F,0x02,0x80, ++0x30,0x1F,0x02,0x80, ++0x30,0x1F,0x02,0x80, ++0x30,0x1F,0x02,0x80, ++0x6A,0x6F,0x69,0x6E, ++0x62,0x73,0x73,0x5F, ++0x68,0x64,0x6C,0x00, ++0x00,0x0E,0x04,0x0E, ++0x10,0x0E,0x14,0x0E, ++0x18,0x0E,0x1C,0x0E, ++0x02,0x04,0x04,0x07, ++0x07,0x0D,0x0D,0x0D, ++0x02,0x07,0x07,0x0D, ++0x0D,0x0F,0x0F,0x0F, ++0x0F,0x00,0x00,0x00, ++0x72,0x65,0x70,0x6F, ++0x72,0x74,0x5F,0x73, ++0x75,0x72,0x76,0x65, ++0x79,0x5F,0x64,0x6F, ++0x6E,0x65,0x00,0x00, ++0x72,0x65,0x70,0x6F, ++0x72,0x74,0x5F,0x6A, ++0x6F,0x69,0x6E,0x5F, ++0x72,0x65,0x73,0x00, ++0x72,0x65,0x70,0x6F, ++0x72,0x74,0x5F,0x64, ++0x65,0x6C,0x5F,0x73, ++0x74,0x61,0x5F,0x65, ++0x76,0x65,0x6E,0x74, ++0x00,0x00,0x00,0x00, ++0x72,0x65,0x70,0x6F, ++0x72,0x74,0x5F,0x61, ++0x64,0x64,0x5F,0x73, ++0x74,0x61,0x5F,0x65, ++0x76,0x65,0x6E,0x74, ++0x00,0x00,0x00,0x00, ++0x69,0x73,0x73,0x75, ++0x65,0x5F,0x70,0x72, ++0x6F,0x62,0x65,0x72, ++0x65,0x71,0x00,0x00, ++0x69,0x73,0x73,0x75, ++0x65,0x5F,0x70,0x72, ++0x6F,0x62,0x65,0x72, ++0x73,0x70,0x00,0x00, ++0x72,0x65,0x70,0x6F, ++0x72,0x74,0x5F,0x42, ++0x53,0x53,0x49,0x44, ++0x5F,0x69,0x6E,0x66, ++0x6F,0x00,0x00,0x00, ++0x00,0x50,0xF2,0x01, ++0x69,0x73,0x73,0x75, ++0x65,0x5F,0x61,0x73, ++0x73,0x6F,0x63,0x72, ++0x65,0x71,0x00,0x00, ++0x00,0x50,0xF2,0x04, ++0x69,0x73,0x73,0x75, ++0x65,0x5F,0x61,0x63, ++0x74,0x69,0x6F,0x6E, ++0x00,0x00,0x00,0x00, ++0x69,0x73,0x73,0x75, ++0x65,0x5F,0x61,0x75, ++0x74,0x68,0x00,0x00, ++0x69,0x73,0x73,0x75, ++0x65,0x5F,0x64,0x65, ++0x61,0x75,0x74,0x68, ++0x00,0x00,0x00,0x00, ++0x69,0x73,0x73,0x75, ++0x65,0x5F,0x64,0x69, ++0x73,0x61,0x73,0x73, ++0x6F,0x63,0x00,0x00, ++0x69,0x73,0x73,0x75, ++0x65,0x5F,0x66,0x72, ++0x61,0x6D,0x65,0x00, ++0x69,0x73,0x73,0x75, ++0x65,0x5F,0x66,0x72, ++0x61,0x6D,0x65,0x5F, ++0x6C,0x65,0x6E,0x00, ++0x30,0x1F,0x02,0x80, ++0xB0,0x03,0x25,0xB0, ++0xF8,0x00,0x25,0xB0, ++0x18,0x03,0x25,0xB0, ++0x44,0x44,0x33,0x33, ++0x06,0x00,0x2A,0xB0, ++0x28,0x3E,0x01,0x80, ++0x28,0x3E,0x01,0x80, ++0x24,0x3E,0x01,0x80, ++0x28,0x3E,0x01,0x80, ++0xA8,0x3E,0x01,0x80, ++0x28,0x3E,0x01,0x80, ++0x28,0x3E,0x01,0x80, ++0x28,0x3E,0x01,0x80, ++0x28,0x3E,0x01,0x80, ++0x28,0x3E,0x01,0x80, ++0x28,0x3E,0x01,0x80, ++0x9C,0x3E,0x01,0x80, ++0x90,0x3E,0x01,0x80, ++0x28,0x3E,0x01,0x80, ++0x28,0x3E,0x01,0x80, ++0x28,0x3E,0x01,0x80, ++0x28,0x3E,0x01,0x80, ++0x28,0x3E,0x01,0x80, ++0x84,0x3E,0x01,0x80, ++0x28,0x3E,0x01,0x80, ++0x28,0x3E,0x01,0x80, ++0x28,0x3E,0x01,0x80, ++0x78,0x3E,0x01,0x80, ++0x28,0x3E,0x01,0x80, ++0x6C,0x3E,0x01,0x80, ++0x28,0x3E,0x01,0x80, ++0x28,0x3E,0x01,0x80, ++0x28,0x3E,0x01,0x80, ++0x28,0x3E,0x01,0x80, ++0x28,0x3E,0x01,0x80, ++0x28,0x3E,0x01,0x80, ++0x28,0x3E,0x01,0x80, ++0x28,0x3E,0x01,0x80, ++0x28,0x3E,0x01,0x80, ++0x28,0x3E,0x01,0x80, ++0x28,0x3E,0x01,0x80, ++0x60,0x3E,0x01,0x80, ++0x28,0x3E,0x01,0x80, ++0x28,0x3E,0x01,0x80, ++0x28,0x3E,0x01,0x80, ++0x28,0x3E,0x01,0x80, ++0x28,0x3E,0x01,0x80, ++0x28,0x3E,0x01,0x80, ++0x28,0x3E,0x01,0x80, ++0x28,0x3E,0x01,0x80, ++0x28,0x3E,0x01,0x80, ++0x28,0x3E,0x01,0x80, ++0x28,0x3E,0x01,0x80, ++0x54,0x3E,0x01,0x80, ++0x28,0x3E,0x01,0x80, ++0x28,0x3E,0x01,0x80, ++0x28,0x3E,0x01,0x80, ++0x28,0x3E,0x01,0x80, ++0x28,0x3E,0x01,0x80, ++0x28,0x3E,0x01,0x80, ++0x28,0x3E,0x01,0x80, ++0x28,0x3E,0x01,0x80, ++0x28,0x3E,0x01,0x80, ++0x28,0x3E,0x01,0x80, ++0x28,0x3E,0x01,0x80, ++0x28,0x3E,0x01,0x80, ++0x28,0x3E,0x01,0x80, ++0x28,0x3E,0x01,0x80, ++0x28,0x3E,0x01,0x80, ++0x28,0x3E,0x01,0x80, ++0x28,0x3E,0x01,0x80, ++0x28,0x3E,0x01,0x80, ++0x28,0x3E,0x01,0x80, ++0x28,0x3E,0x01,0x80, ++0x28,0x3E,0x01,0x80, ++0x28,0x3E,0x01,0x80, ++0x28,0x3E,0x01,0x80, ++0x48,0x3E,0x01,0x80, ++0x28,0x3E,0x01,0x80, ++0x28,0x3E,0x01,0x80, ++0x28,0x3E,0x01,0x80, ++0x28,0x3E,0x01,0x80, ++0x28,0x3E,0x01,0x80, ++0x28,0x3E,0x01,0x80, ++0x28,0x3E,0x01,0x80, ++0x28,0x3E,0x01,0x80, ++0x28,0x3E,0x01,0x80, ++0x28,0x3E,0x01,0x80, ++0x28,0x3E,0x01,0x80, ++0x28,0x3E,0x01,0x80, ++0x28,0x3E,0x01,0x80, ++0x28,0x3E,0x01,0x80, ++0x28,0x3E,0x01,0x80, ++0x28,0x3E,0x01,0x80, ++0x28,0x3E,0x01,0x80, ++0x28,0x3E,0x01,0x80, ++0x28,0x3E,0x01,0x80, ++0x28,0x3E,0x01,0x80, ++0x28,0x3E,0x01,0x80, ++0x28,0x3E,0x01,0x80, ++0x28,0x3E,0x01,0x80, ++0x3C,0x3E,0x01,0x80, ++0x28,0x3E,0x01,0x80, ++0x28,0x3E,0x01,0x80, ++0x28,0x3E,0x01,0x80, ++0x28,0x3E,0x01,0x80, ++0x28,0x3E,0x01,0x80, ++0x28,0x3E,0x01,0x80, ++0x28,0x3E,0x01,0x80, ++0x28,0x3E,0x01,0x80, ++0x28,0x3E,0x01,0x80, ++0x28,0x3E,0x01,0x80, ++0x28,0x3E,0x01,0x80, ++0x30,0x3E,0x01,0x80, ++0x68,0x3F,0x01,0x80, ++0x5C,0x3F,0x01,0x80, ++0x50,0x3F,0x01,0x80, ++0x44,0x3F,0x01,0x80, ++0x38,0x3F,0x01,0x80, ++0x2C,0x3F,0x01,0x80, ++0x20,0x3F,0x01,0x80, ++0x14,0x3F,0x01,0x80, ++0x08,0x3F,0x01,0x80, ++0xFC,0x3E,0x01,0x80, ++0xF0,0x3E,0x01,0x80, ++0xE4,0x3E,0x01,0x80, ++0x00,0x50,0xF2,0x01, ++0x00,0x50,0xF2,0x02, ++0x00,0x0F,0xAC,0x02, ++0xBC,0xE3,0x01,0x80, ++0x67,0x66,0x66,0x66, ++0x7C,0x88,0x00,0x80, ++0x64,0x88,0x00,0x80, ++0x4C,0x88,0x00,0x80, ++0x34,0x88,0x00,0x80, ++0x1C,0x88,0x00,0x80, ++0x04,0x88,0x00,0x80, ++0xE0,0x87,0x00,0x80, ++0x00,0x02,0x00,0x00, ++0x08,0x09,0x00,0x00, ++0x18,0x96,0x00,0x80, ++0x24,0x96,0x00,0x80, ++0x30,0x96,0x00,0x80, ++0x3C,0x96,0x00,0x80, ++0x18,0x96,0x00,0x80, ++0x18,0x96,0x00,0x80, ++0x18,0x96,0x00,0x80, ++0x18,0x96,0x00,0x80, ++0x48,0x96,0x00,0x80, ++0x54,0x96,0x00,0x80, ++0x60,0x96,0x00,0x80, ++0x6C,0x96,0x00,0x80, ++0x30,0x1F,0x02,0x80, ++0x84,0x0E,0x25,0xB0, ++0x88,0x0E,0x25,0xB0, ++0x8C,0x0E,0x25,0xB0, ++0xD0,0x0E,0x25,0xB0, ++0xD8,0x0E,0x25,0xB0, ++0x20,0x08,0x25,0xB0, ++0x74,0x0E,0x25,0xB0, ++0x80,0x0E,0x25,0xB0, ++0x84,0x0E,0x25,0xB0, ++0x88,0x0E,0x25,0xB0, ++0x8C,0x0E,0x25,0xB0, ++0xD0,0x0E,0x25,0xB0, ++0xD8,0x0E,0x25,0xB0, ++0x14,0x0C,0x25,0xB0, ++0x88,0x0C,0x25,0xB0, ++0x1C,0x0C,0x25,0xB0, ++0xFE,0x01,0x80,0x7F, ++0xE2,0x01,0x80,0x78, ++0xC7,0x01,0xC0,0x71, ++0xAE,0x01,0x80,0x6B, ++0x95,0x01,0x40,0x65, ++0x7F,0x01,0xC0,0x5F, ++0x69,0x01,0x40,0x5A, ++0x55,0x01,0x40,0x55, ++0x42,0x01,0x80,0x50, ++0x30,0x01,0x00,0x4C, ++0x1F,0x01,0xC0,0x47, ++0x0F,0x01,0xC0,0x43, ++0x00,0x01,0x00,0x40, ++0xF2,0x00,0x80,0x3C, ++0xE4,0x00,0x00,0x39, ++0xD7,0x00,0xC0,0x35, ++0xCB,0x00,0xC0,0x32, ++0xC0,0x00,0x00,0x30, ++0xB5,0x00,0x40,0x2D, ++0xAB,0x00,0xC0,0x2A, ++0xA2,0x00,0x80,0x28, ++0x98,0x00,0x00,0x26, ++0x90,0x00,0x00,0x24, ++0x88,0x00,0x00,0x22, ++0x80,0x00,0x00,0x20, ++0x79,0x00,0x40,0x1E, ++0x72,0x00,0x80,0x1C, ++0x6C,0x00,0x00,0x1B, ++0x66,0x00,0x80,0x19, ++0x60,0x00,0x00,0x18, ++0x5B,0x00,0xC0,0x16, ++0x56,0x00,0x80,0x15, ++0x51,0x00,0x40,0x14, ++0x4C,0x00,0x00,0x13, ++0x48,0x00,0x00,0x12, ++0x44,0x00,0x00,0x11, ++0x40,0x00,0x00,0x10, ++0x36,0x35,0x2E,0x25, ++0x1C,0x12,0x09,0x04, ++0x33,0x32,0x2B,0x23, ++0x1A,0x11,0x08,0x04, ++0x30,0x2F,0x29,0x21, ++0x19,0x10,0x08,0x03, ++0x2D,0x2D,0x27,0x1F, ++0x18,0x0F,0x08,0x03, ++0x2B,0x2A,0x25,0x1E, ++0x16,0x0E,0x07,0x03, ++0x28,0x28,0x22,0x1C, ++0x15,0x0D,0x07,0x03, ++0x26,0x25,0x21,0x1B, ++0x14,0x0D,0x06,0x03, ++0x24,0x23,0x1F,0x19, ++0x13,0x0C,0x06,0x03, ++0x22,0x21,0x1D,0x18, ++0x11,0x0B,0x06,0x02, ++0x20,0x20,0x1B,0x16, ++0x11,0x08,0x05,0x02, ++0x1F,0x1E,0x1A,0x15, ++0x10,0x0A,0x05,0x02, ++0x1D,0x1C,0x18,0x14, ++0x0F,0x0A,0x05,0x02, ++0x1B,0x1A,0x17,0x13, ++0x0E,0x09,0x04,0x02, ++0x1A,0x19,0x16,0x12, ++0x0D,0x09,0x04,0x02, ++0x18,0x17,0x15,0x11, ++0x0C,0x08,0x04,0x02, ++0x17,0x16,0x13,0x10, ++0x0C,0x08,0x04,0x02, ++0x16,0x15,0x12,0x0F, ++0x0B,0x07,0x04,0x01, ++0x14,0x14,0x11,0x0E, ++0x0B,0x07,0x03,0x02, ++0x13,0x13,0x10,0x0D, ++0x0A,0x06,0x03,0x01, ++0x12,0x12,0x0F,0x0C, ++0x09,0x06,0x03,0x01, ++0x11,0x11,0x0F,0x0C, ++0x09,0x06,0x03,0x01, ++0x10,0x10,0x0E,0x0B, ++0x08,0x05,0x03,0x01, ++0x0F,0x0F,0x0D,0x0B, ++0x08,0x05,0x03,0x01, ++0x0E,0x0E,0x0C,0x0A, ++0x08,0x05,0x02,0x01, ++0x0D,0x0D,0x0C,0x0A, ++0x07,0x05,0x02,0x01, ++0x0D,0x0C,0x0B,0x09, ++0x07,0x04,0x02,0x01, ++0x0C,0x0C,0x0A,0x09, ++0x06,0x04,0x02,0x01, ++0x0B,0x0B,0x0A,0x08, ++0x06,0x04,0x02,0x01, ++0x0B,0x0A,0x09,0x08, ++0x06,0x04,0x02,0x01, ++0x0A,0x0A,0x09,0x07, ++0x05,0x03,0x02,0x01, ++0x0A,0x09,0x08,0x07, ++0x05,0x03,0x02,0x01, ++0x09,0x09,0x08,0x06, ++0x05,0x03,0x01,0x01, ++0x09,0x08,0x07,0x06, ++0x04,0x03,0x01,0x01, ++0x36,0x35,0x2E,0x1B, ++0x00,0x00,0x00,0x00, ++0x33,0x32,0x2B,0x19, ++0x00,0x00,0x00,0x00, ++0x30,0x2F,0x29,0x18, ++0x00,0x00,0x00,0x00, ++0x2D,0x2D,0x17,0x17, ++0x00,0x00,0x00,0x00, ++0x2B,0x2A,0x25,0x15, ++0x00,0x00,0x00,0x00, ++0x28,0x28,0x24,0x14, ++0x00,0x00,0x00,0x00, ++0x26,0x25,0x21,0x13, ++0x00,0x00,0x00,0x00, ++0x24,0x23,0x1F,0x12, ++0x00,0x00,0x00,0x00, ++0x22,0x21,0x1D,0x11, ++0x00,0x00,0x00,0x00, ++0x20,0x20,0x1B,0x10, ++0x00,0x00,0x00,0x00, ++0x1F,0x1E,0x1A,0x0F, ++0x00,0x00,0x00,0x00, ++0x1D,0x1C,0x18,0x0E, ++0x00,0x00,0x00,0x00, ++0x1B,0x1A,0x17,0x0E, ++0x00,0x00,0x00,0x00, ++0x1A,0x19,0x16,0x0D, ++0x00,0x00,0x00,0x00, ++0x18,0x17,0x15,0x0C, ++0x00,0x00,0x00,0x00, ++0x17,0x16,0x13,0x0B, ++0x00,0x00,0x00,0x00, ++0x16,0x15,0x12,0x0B, ++0x00,0x00,0x00,0x00, ++0x14,0x14,0x11,0x0A, ++0x00,0x00,0x00,0x00, ++0x13,0x13,0x10,0x0A, ++0x00,0x00,0x00,0x00, ++0x12,0x12,0x0F,0x09, ++0x00,0x00,0x00,0x00, ++0x11,0x11,0x0F,0x09, ++0x00,0x00,0x00,0x00, ++0x10,0x10,0x0E,0x08, ++0x00,0x00,0x00,0x00, ++0x0F,0x0F,0x0D,0x08, ++0x00,0x00,0x00,0x00, ++0x0E,0x0E,0x0C,0x07, ++0x00,0x00,0x00,0x00, ++0x0D,0x0D,0x0C,0x07, ++0x00,0x00,0x00,0x00, ++0x0D,0x0C,0x0B,0x06, ++0x00,0x00,0x00,0x00, ++0x0C,0x0C,0x0A,0x06, ++0x00,0x00,0x00,0x00, ++0x0B,0x0B,0x0A,0x06, ++0x00,0x00,0x00,0x00, ++0x0B,0x0A,0x09,0x05, ++0x00,0x00,0x00,0x00, ++0x0A,0x0A,0x09,0x05, ++0x00,0x00,0x00,0x00, ++0x0A,0x09,0x08,0x05, ++0x00,0x00,0x00,0x00, ++0x09,0x09,0x08,0x05, ++0x00,0x00,0x00,0x00, ++0x09,0x08,0x07,0x04, ++0x00,0x00,0x00,0x00, ++0x06,0x00,0x2A,0xB0, ++0x05,0x00,0x2A,0xB0, ++0x54,0x83,0x01,0x80, ++0xC4,0x83,0x01,0x80, ++0x80,0x83,0x01,0x80, ++0xC4,0x83,0x01,0x80, ++0xC4,0x83,0x01,0x80, ++0xC4,0x83,0x01,0x80, ++0xC4,0x83,0x01,0x80, ++0x2C,0x83,0x01,0x80, ++0x00,0x01,0x02,0x02, ++0x03,0x03,0x03,0x03, ++0x04,0x04,0x04,0x04, ++0x04,0x04,0x04,0x04, ++0x05,0x05,0x05,0x05, ++0x05,0x05,0x05,0x05, ++0x05,0x05,0x05,0x05, ++0x05,0x05,0x05,0x05, ++0x06,0x06,0x06,0x06, ++0x06,0x06,0x06,0x06, ++0x06,0x06,0x06,0x06, ++0x06,0x06,0x06,0x06, ++0x06,0x06,0x06,0x06, ++0x06,0x06,0x06,0x06, ++0x06,0x06,0x06,0x06, ++0x06,0x06,0x06,0x06, ++0x07,0x07,0x07,0x07, ++0x07,0x07,0x07,0x07, ++0x07,0x07,0x07,0x07, ++0x07,0x07,0x07,0x07, ++0x07,0x07,0x07,0x07, ++0x07,0x07,0x07,0x07, ++0x07,0x07,0x07,0x07, ++0x07,0x07,0x07,0x07, ++0x07,0x07,0x07,0x07, ++0x07,0x07,0x07,0x07, ++0x07,0x07,0x07,0x07, ++0x07,0x07,0x07,0x07, ++0x07,0x07,0x07,0x07, ++0x07,0x07,0x07,0x07, ++0x07,0x07,0x07,0x07, ++0x07,0x07,0x07,0x07, ++0x08,0x08,0x08,0x08, ++0x08,0x08,0x08,0x08, ++0x08,0x08,0x08,0x08, ++0x08,0x08,0x08,0x08, ++0x08,0x08,0x08,0x08, ++0x08,0x08,0x08,0x08, ++0x08,0x08,0x08,0x08, ++0x08,0x08,0x08,0x08, ++0x08,0x08,0x08,0x08, ++0x08,0x08,0x08,0x08, ++0x08,0x08,0x08,0x08, ++0x08,0x08,0x08,0x08, ++0x08,0x08,0x08,0x08, ++0x08,0x08,0x08,0x08, ++0x08,0x08,0x08,0x08, ++0x08,0x08,0x08,0x08, ++0x08,0x08,0x08,0x08, ++0x08,0x08,0x08,0x08, ++0x08,0x08,0x08,0x08, ++0x08,0x08,0x08,0x08, ++0x08,0x08,0x08,0x08, ++0x08,0x08,0x08,0x08, ++0x08,0x08,0x08,0x08, ++0x08,0x08,0x08,0x08, ++0x08,0x08,0x08,0x08, ++0x08,0x08,0x08,0x08, ++0x08,0x08,0x08,0x08, ++0x08,0x08,0x08,0x08, ++0x08,0x08,0x08,0x08, ++0x08,0x08,0x08,0x08, ++0x08,0x08,0x08,0x08, ++0x08,0x08,0x08,0x08, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x08,0x08,0x08,0x08, ++0x08,0x08,0x08,0x08, ++0x08,0x28,0x28,0x28, ++0x28,0x28,0x08,0x08, ++0x08,0x08,0x08,0x08, ++0x08,0x08,0x08,0x08, ++0x08,0x08,0x08,0x08, ++0x08,0x08,0x08,0x08, ++0xA0,0x10,0x10,0x10, ++0x10,0x10,0x10,0x10, ++0x10,0x10,0x10,0x10, ++0x10,0x10,0x10,0x10, ++0x04,0x04,0x04,0x04, ++0x04,0x04,0x04,0x04, ++0x04,0x04,0x10,0x10, ++0x10,0x10,0x10,0x10, ++0x10,0x41,0x41,0x41, ++0x41,0x41,0x41,0x01, ++0x01,0x01,0x01,0x01, ++0x01,0x01,0x01,0x01, ++0x01,0x01,0x01,0x01, ++0x01,0x01,0x01,0x01, ++0x01,0x01,0x01,0x10, ++0x10,0x10,0x10,0x10, ++0x10,0x42,0x42,0x42, ++0x42,0x42,0x42,0x02, ++0x02,0x02,0x02,0x02, ++0x02,0x02,0x02,0x02, ++0x02,0x02,0x02,0x02, ++0x02,0x02,0x02,0x02, ++0x02,0x02,0x02,0x10, ++0x10,0x10,0x10,0x08, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0xA0,0x10,0x10,0x10, ++0x10,0x10,0x10,0x10, ++0x10,0x10,0x10,0x10, ++0x10,0x10,0x10,0x10, ++0x10,0x10,0x10,0x10, ++0x10,0x10,0x10,0x10, ++0x10,0x10,0x10,0x10, ++0x10,0x10,0x10,0x10, ++0x01,0x01,0x01,0x01, ++0x01,0x01,0x01,0x01, ++0x01,0x01,0x01,0x01, ++0x01,0x01,0x01,0x01, ++0x01,0x01,0x01,0x01, ++0x01,0x01,0x01,0x10, ++0x01,0x01,0x01,0x01, ++0x01,0x01,0x01,0x02, ++0x02,0x02,0x02,0x02, ++0x02,0x02,0x02,0x02, ++0x02,0x02,0x02,0x02, ++0x02,0x02,0x02,0x02, ++0x02,0x02,0x02,0x02, ++0x02,0x02,0x02,0x10, ++0x02,0x02,0x02,0x02, ++0x02,0x02,0x02,0x00, ++0x2D,0x5C,0x7C,0x2F, ++0x00,0x00,0x00,0x00, ++0xFD,0xFA,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x45,0xC4,0xF0, ++0x00,0x45,0xC4,0xF0, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x00,0x45,0xB5,0x60, ++0xFF,0xFF,0xFF,0xFF, ++0x00,0x00,0x00,0x02, ++0x00,0x00,0x00,0x00, ++0x00,0x00,0x00,0x00, ++0x08,0xFB,0x90,0xB8, ++0xFF,0xFF,0xFF,0xFF, ++}; +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/include/h2clbk.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/include/h2clbk.h 2013-07-26 19:36:06.000000000 +0000 +@@ -0,0 +1,35 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++ ++ ++#define _H2CLBK_H_ ++ ++ ++#include ++#include ++ ++ ++void _lbk_cmd(PADAPTER Adapter); ++ ++void _lbk_rsp(PADAPTER Adapter); ++ ++void _lbk_evt(IN PADAPTER Adapter); ++ ++void h2c_event_callback(unsigned char *dev, unsigned char *pbuf); +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/include/hal_init.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/include/hal_init.h 2013-07-26 19:36:06.000000000 +0000 +@@ -0,0 +1,305 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef __HAL_INIT_H__ ++#define __HAL_INIT_H__ ++ ++#include ++#include ++#include ++ ++#ifdef CONFIG_PCI_HCI ++#include ++#endif ++ ++ ++enum RTL871X_HCI_TYPE { ++ ++ RTW_SDIO, ++ RTW_USB, ++ RTW_PCIE ++}; ++ ++enum _CHIP_TYPE { ++ ++ NULL_CHIP_TYPE, ++ RTL8712_8188S_8191S_8192S, ++ RTL8188C_8192C, ++ RTL8192D, ++ MAX_CHIP_TYPE ++}; ++ ++ ++typedef enum _HW_VARIABLES{ ++ HW_VAR_MEDIA_STATUS, ++ HW_VAR_MEDIA_STATUS1, ++ HW_VAR_SET_OPMODE, ++ HW_VAR_MAC_ADDR, ++ HW_VAR_BSSID, ++ HW_VAR_INIT_RTS_RATE, ++ HW_VAR_BASIC_RATE, ++ HW_VAR_TXPAUSE, ++ HW_VAR_BCN_FUNC, ++ HW_VAR_CORRECT_TSF, ++ HW_VAR_CHECK_BSSID, ++ HW_VAR_MLME_DISCONNECT, ++ HW_VAR_MLME_SITESURVEY, ++ HW_VAR_MLME_JOIN, ++ HW_VAR_BEACON_INTERVAL, ++ HW_VAR_SLOT_TIME, ++ HW_VAR_SIFS, ++ HW_VAR_ACK_PREAMBLE, ++ HW_VAR_SEC_CFG, ++ HW_VAR_TX_BCN_DONE, ++ HW_VAR_RF_TYPE, ++ HW_VAR_DM_FLAG, ++ HW_VAR_DM_FUNC_OP, ++ HW_VAR_DM_FUNC_SET, ++ HW_VAR_DM_FUNC_CLR, ++ HW_VAR_CAM_EMPTY_ENTRY, ++ HW_VAR_CAM_INVALID_ALL, ++ HW_VAR_CAM_WRITE, ++ HW_VAR_AC_PARAM_VO, ++ HW_VAR_AC_PARAM_VI, ++ HW_VAR_AC_PARAM_BE, ++ HW_VAR_AC_PARAM_BK, ++ HW_VAR_ACM_CTRL, ++ HW_VAR_AMPDU_MIN_SPACE, ++ HW_VAR_AMPDU_FACTOR, ++ HW_VAR_RXDMA_AGG_PG_TH, ++ HW_VAR_SET_RPWM, ++ HW_VAR_H2C_FW_PWRMODE, ++ HW_VAR_H2C_FW_JOINBSSRPT, ++ HW_VAR_FWLPS_RF_ON, ++ HW_VAR_H2C_FW_P2P_PS_OFFLOAD, ++ HW_VAR_TDLS_WRCR, ++ HW_VAR_TDLS_INIT_CH_SEN, ++ HW_VAR_TDLS_RS_RCR, ++ HW_VAR_TDLS_DONE_CH_SEN, ++ HW_VAR_INITIAL_GAIN, ++ HW_VAR_TRIGGER_GPIO_0, ++ HW_VAR_BT_SET_COEXIST, ++ HW_VAR_BT_ISSUE_DELBA, ++ HW_VAR_CURRENT_ANTENNA, ++ HW_VAR_ANTENNA_DIVERSITY_LINK, ++ HW_VAR_ANTENNA_DIVERSITY_SELECT, ++ HW_VAR_SWITCH_EPHY_WoWLAN, ++ HW_VAR_EFUSE_BYTES, ++ HW_VAR_FIFO_CLEARN_UP, ++ HW_VAR_CHECK_TXBUF, ++ HW_VAR_APFM_ON_MAC, //Auto FSM to Turn On, include clock, isolation, power control for MAC only HW_VAR_WOWLAN,}HW_VARIABLES; ++ HW_VAR_WOWLAN, ++}HW_VARIABLES; ++ ++typedef enum _HAL_DEF_VARIABLE{ ++ HAL_DEF_UNDERCORATEDSMOOTHEDPWDB, ++ HAL_DEF_IS_SUPPORT_ANT_DIV, ++ HAL_DEF_CURRENT_ANTENNA, ++ HAL_DEF_DRVINFO_SZ, ++ HAL_DEF_MAX_RECVBUF_SZ, ++ HAL_DEF_RX_PACKET_OFFSET, ++ HAL_DEF_DBG_DUMP_RXPKT,//for dbg ++ HAL_DEF_DBG_DM_FUNC,//for dbg ++}HAL_DEF_VARIABLE; ++ ++typedef enum _HAL_INTF_PS_FUNC{ ++ HAL_USB_SELECT_SUSPEND, ++ HAL_MAX_ID, ++}HAL_INTF_PS_FUNC; ++ ++struct hal_ops { ++ u32 (*hal_init)(PADAPTER Adapter); ++ u32 (*hal_deinit)(PADAPTER Adapter); ++ ++ void (*free_hal_data)(PADAPTER Adapter); ++ ++ u32 (*inirp_init)(PADAPTER Adapter); ++ u32 (*inirp_deinit)(PADAPTER Adapter); ++ ++ s32 (*init_xmit_priv)(PADAPTER Adapter); ++ void (*free_xmit_priv)(PADAPTER Adapter); ++ ++ s32 (*init_recv_priv)(PADAPTER Adapter); ++ void (*free_recv_priv)(PADAPTER Adapter); ++ ++ void (*InitSwLeds)(PADAPTER Adapter); ++ void (*DeInitSwLeds)(PADAPTER Adapter); ++ ++ void (*dm_init)(PADAPTER Adapter); ++ void (*dm_deinit)(PADAPTER Adapter); ++ void (*read_chip_version)(PADAPTER Adapter); ++ ++ void (*init_default_value)(PADAPTER Adapter); ++ ++ void (*intf_chip_configure)(PADAPTER Adapter); ++ ++ void (*read_adapter_info)(PADAPTER Adapter); ++ ++ void (*enable_interrupt)(PADAPTER Adapter); ++ void (*disable_interrupt)(PADAPTER Adapter); ++ s32 (*interrupt_handler)(PADAPTER Adapter); ++ ++ void (*set_bwmode_handler)(PADAPTER Adapter, HT_CHANNEL_WIDTH Bandwidth, u8 Offset); ++ void (*set_channel_handler)(PADAPTER Adapter, u8 channel); ++ ++ void (*hal_dm_watchdog)(PADAPTER Adapter); ++ ++ void (*SetHwRegHandler)(PADAPTER Adapter, u8 variable,u8* val); ++ void (*GetHwRegHandler)(PADAPTER Adapter, u8 variable,u8* val); ++ ++ u8 (*GetHalDefVarHandler)(PADAPTER Adapter, HAL_DEF_VARIABLE eVariable, PVOID pValue); ++ u8 (*SetHalDefVarHandler)(PADAPTER Adapter, HAL_DEF_VARIABLE eVariable, PVOID pValue); ++ ++ void (*UpdateRAMaskHandler)(PADAPTER Adapter, u32 mac_id); ++ void (*SetBeaconRelatedRegistersHandler)(PADAPTER Adapter); ++ ++ void (*Add_RateATid)(PADAPTER Adapter, u32 bitmap, u8 arg, u8 mac_id); ++ ++#ifdef CONFIG_ANTENNA_DIVERSITY ++ u8 (*SwAntDivBeforeLinkHandler)(PADAPTER Adapter); ++ void (*SwAntDivCompareHandler)(PADAPTER Adapter, WLAN_BSSID_EX *dst, WLAN_BSSID_EX *src); ++#endif ++ u8 (*interface_ps_func)(PADAPTER Adapter,HAL_INTF_PS_FUNC efunc_id, u8* val); ++ ++ s32 (*hal_xmit)(PADAPTER Adapter, struct xmit_frame *pxmitframe); ++ void (*mgnt_xmit)(PADAPTER Adapter, struct xmit_frame *pmgntframe); ++ ++ u32 (*read_bbreg)(PADAPTER Adapter, u32 RegAddr, u32 BitMask); ++ void (*write_bbreg)(PADAPTER Adapter, u32 RegAddr, u32 BitMask, u32 Data); ++ u32 (*read_rfreg)(PADAPTER Adapter, u32 eRFPath, u32 RegAddr, u32 BitMask); ++ void (*write_rfreg)(PADAPTER Adapter, u32 eRFPath, u32 RegAddr, u32 BitMask, u32 Data); ++ ++#ifdef CONFIG_HOSTAPD_MLME ++ s32 (*hostap_mgnt_xmit_entry)(PADAPTER Adapter, _pkt *pkt); ++#endif ++ void (*EfusePowerSwitch)(PADAPTER pAdapter, u8 bWrite, u8 PwrState); ++ void (*ReadEFuse)(PADAPTER Adapter, u8 efuseType, u16 _offset, u16 _size_byte, u8 *pbuf, BOOLEAN bPseudoTest); ++ void (*EFUSEGetEfuseDefinition)(PADAPTER pAdapter, u8 efuseType, u8 type, PVOID *pOut, BOOLEAN bPseudoTest); ++ u16 (*EfuseGetCurrentSize)(PADAPTER pAdapter, u8 efuseType, BOOLEAN bPseudoTest); ++ int (*Efuse_PgPacketRead)(PADAPTER pAdapter, u8 offset, u8 *data, BOOLEAN bPseudoTest); ++ int (*Efuse_PgPacketWrite)(PADAPTER pAdapter, u8 offset, u8 word_en, u8 *data, BOOLEAN bPseudoTest); ++ u8 (*Efuse_WordEnableDataWrite)(PADAPTER pAdapter, u16 efuse_addr, u8 word_en, u8 *data, BOOLEAN bPseudoTest); ++ ++#ifdef DBG_CONFIG_ERROR_DETECT ++ void (*sreset_init_value)(_adapter *padapter); ++ void (*sreset_reset_value)(_adapter *padapter); ++ void (*silentreset)(_adapter *padapter); ++ void (*sreset_xmit_status_check)(_adapter *padapter); ++ void (*sreset_linked_status_check) (_adapter *padapter); ++ u8 (*sreset_get_wifi_status)(_adapter *padapter); ++#endif ++ ++#ifdef CONFIG_IOL ++ int (*IOL_exec_cmds_sync)(ADAPTER *adapter, struct xmit_frame *xmit_frame, u32 max_wating_ms); ++#endif ++}; ++ ++typedef enum _RT_EEPROM_TYPE{ ++ EEPROM_93C46, ++ EEPROM_93C56, ++ EEPROM_BOOT_EFUSE, ++}RT_EEPROM_TYPE,*PRT_EEPROM_TYPE; ++ ++#define USB_HIGH_SPEED_BULK_SIZE 512 ++#define USB_FULL_SPEED_BULK_SIZE 64 ++ ++#define RF_CHANGE_BY_INIT 0 ++#define RF_CHANGE_BY_IPS BIT28 ++#define RF_CHANGE_BY_PS BIT29 ++#define RF_CHANGE_BY_HW BIT30 ++#define RF_CHANGE_BY_SW BIT31 ++ ++typedef enum _HARDWARE_TYPE{ ++ HARDWARE_TYPE_RTL8180, ++ HARDWARE_TYPE_RTL8185, ++ HARDWARE_TYPE_RTL8187, ++ HARDWARE_TYPE_RTL8188, ++ HARDWARE_TYPE_RTL8190P, ++ HARDWARE_TYPE_RTL8192E, ++ HARDWARE_TYPE_RTL819xU, ++ HARDWARE_TYPE_RTL8192SE, ++ HARDWARE_TYPE_RTL8192SU, ++ HARDWARE_TYPE_RTL8192CE, ++ HARDWARE_TYPE_RTL8192CU, ++ HARDWARE_TYPE_RTL8192DE, ++ HARDWARE_TYPE_RTL8192DU, ++ HARDWARE_TYPE_RTL8723E, ++ HARDWARE_TYPE_RTL8723U, ++}HARDWARE_TYPE; ++ ++#define IS_HARDWARE_TYPE_8192CE(_Adapter) (((PADAPTER)_Adapter)->HardwareType==HARDWARE_TYPE_RTL8192CE) ++#define IS_HARDWARE_TYPE_8192CU(_Adapter) (((PADAPTER)_Adapter)->HardwareType==HARDWARE_TYPE_RTL8192CU) ++ ++#define IS_HARDWARE_TYPE_8192DE(_Adapter) (((PADAPTER)_Adapter)->HardwareType==HARDWARE_TYPE_RTL8192DE) ++#define IS_HARDWARE_TYPE_8192DU(_Adapter) (((PADAPTER)_Adapter)->HardwareType==HARDWARE_TYPE_RTL8192DU) ++ ++#define IS_HARDWARE_TYPE_8723E(_Adapter) (((PADAPTER)_Adapter)->HardwareType==HARDWARE_TYPE_RTL8723E) ++#define IS_HARDWARE_TYPE_8723U(_Adapter) (((PADAPTER)_Adapter)->HardwareType==HARDWARE_TYPE_RTL8723U) ++ ++#define IS_HARDWARE_TYPE_8192C(_Adapter) \ ++(IS_HARDWARE_TYPE_8192CE(_Adapter) || IS_HARDWARE_TYPE_8192CU(_Adapter)) ++ ++#define IS_HARDWARE_TYPE_8192D(_Adapter) \ ++(IS_HARDWARE_TYPE_8192DE(_Adapter) || IS_HARDWARE_TYPE_8192DU(_Adapter)) ++ ++#define IS_HARDWARE_TYPE_8723(_Adapter) \ ++(IS_HARDWARE_TYPE_8723E(_Adapter) || IS_HARDWARE_TYPE_8723U(_Adapter)) ++ ++ ++typedef struct eeprom_priv EEPROM_EFUSE_PRIV, *PEEPROM_EFUSE_PRIV; ++#define GET_EEPROM_EFUSE_PRIV(priv) (&priv->eeprompriv) ++ ++typedef enum _wowlan_subcode{ ++ WOWLAN_PATTERN_MATCH = 1, ++ WOWLAN_MAGIC_PACKET = 2, ++ WOWLAN_UNICAST = 3, ++ WOWLAN_SET_PATTERN = 4, ++ WOWLAN_DUMP_REG = 5, ++ WOWLAN_ENABLE = 6, ++ WOWLAN_DISABLE = 7, ++ WOWLAN_STATUS = 8, ++ WOWLAN_DEBUG_RELOAD_FW = 9, ++ WOWLAN_DEBUG_1 =10, ++ WOWLAN_DEBUG_2 =11 ++}wowlan_subcode; ++ ++struct wowlan_ioctl_param{ ++ unsigned int subcode; ++ unsigned int subcode_value; ++ unsigned int wakeup_reason; ++ unsigned int len; ++ unsigned char pattern[0]; ++}; ++void rtw_dm_init(_adapter *padapter); ++void rtw_sw_led_init(_adapter *padapter); ++void rtw_sw_led_deinit(_adapter *padapter); ++ ++uint rtw_hal_init(_adapter *padapter); ++uint rtw_hal_deinit(_adapter *padapter); ++void rtw_hal_stop(_adapter *padapter); ++ ++void intf_chip_configure(_adapter *padapter); ++void intf_read_chip_info(_adapter *padapter); ++void intf_read_chip_version(_adapter *padapter); ++#ifdef DBG_CONFIG_ERROR_DETECT ++void rtw_sreset_init(_adapter *padapter); ++#endif ++ ++#endif //__HAL_INIT_H__ ++ +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/include/ieee80211.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/include/ieee80211.h 2013-07-26 19:36:06.000000000 +0000 +@@ -0,0 +1,1461 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef __IEEE80211_H ++#define __IEEE80211_H ++ ++ ++#ifndef CONFIG_RTL8711FW ++ ++ #include ++ #include ++ #include ++ #include "wifi.h" ++ ++ #if defined PLATFORM_OS_XP ++ #include ++ #endif ++ #if defined PLATFORM_LINUX ++ #include ++ #endif ++#else ++ ++ #include ++ ++#endif ++ ++#define MGMT_QUEUE_NUM 5 ++ ++#define ETH_ALEN 6 ++ ++#ifdef CONFIG_AP_MODE ++ ++#define RTL_IOCTL_HOSTAPD (SIOCIWFIRSTPRIV + 28) ++ ++/* RTL871X_IOCTL_HOSTAPD ioctl() cmd: */ ++enum { ++ RTL871X_HOSTAPD_FLUSH = 1, ++ RTL871X_HOSTAPD_ADD_STA = 2, ++ RTL871X_HOSTAPD_REMOVE_STA = 3, ++ RTL871X_HOSTAPD_GET_INFO_STA = 4, ++ /* REMOVED: PRISM2_HOSTAPD_RESET_TXEXC_STA = 5, */ ++ RTL871X_HOSTAPD_GET_WPAIE_STA = 5, ++ RTL871X_SET_ENCRYPTION = 6, ++ RTL871X_GET_ENCRYPTION = 7, ++ RTL871X_HOSTAPD_SET_FLAGS_STA = 8, ++ RTL871X_HOSTAPD_GET_RID = 9, ++ RTL871X_HOSTAPD_SET_RID = 10, ++ RTL871X_HOSTAPD_SET_ASSOC_AP_ADDR = 11, ++ RTL871X_HOSTAPD_SET_GENERIC_ELEMENT = 12, ++ RTL871X_HOSTAPD_MLME = 13, ++ RTL871X_HOSTAPD_SCAN_REQ = 14, ++ RTL871X_HOSTAPD_STA_CLEAR_STATS = 15, ++ RTL871X_HOSTAPD_SET_BEACON=16, ++ RTL871X_HOSTAPD_SET_WPS_BEACON = 17, ++ RTL871X_HOSTAPD_SET_WPS_PROBE_RESP = 18, ++ RTL871X_HOSTAPD_SET_WPS_ASSOC_RESP = 19, ++ RTL871X_HOSTAPD_SET_HIDDEN_SSID = 20, ++}; ++ ++/* STA flags */ ++#define WLAN_STA_AUTH BIT(0) ++#define WLAN_STA_ASSOC BIT(1) ++#define WLAN_STA_PS BIT(2) ++#define WLAN_STA_TIM BIT(3) ++#define WLAN_STA_PERM BIT(4) ++#define WLAN_STA_AUTHORIZED BIT(5) ++#define WLAN_STA_PENDING_POLL BIT(6) /* pending activity poll not ACKed */ ++#define WLAN_STA_SHORT_PREAMBLE BIT(7) ++#define WLAN_STA_PREAUTH BIT(8) ++#define WLAN_STA_WME BIT(9) ++#define WLAN_STA_MFP BIT(10) ++#define WLAN_STA_HT BIT(11) ++#define WLAN_STA_WPS BIT(12) ++#define WLAN_STA_MAYBE_WPS BIT(13) ++#define WLAN_STA_NONERP BIT(31) ++ ++#endif ++ ++#define IEEE_CMD_SET_WPA_PARAM 1 ++#define IEEE_CMD_SET_WPA_IE 2 ++#define IEEE_CMD_SET_ENCRYPTION 3 ++#define IEEE_CMD_MLME 4 ++ ++#define IEEE_PARAM_WPA_ENABLED 1 ++#define IEEE_PARAM_TKIP_COUNTERMEASURES 2 ++#define IEEE_PARAM_DROP_UNENCRYPTED 3 ++#define IEEE_PARAM_PRIVACY_INVOKED 4 ++#define IEEE_PARAM_AUTH_ALGS 5 ++#define IEEE_PARAM_IEEE_802_1X 6 ++#define IEEE_PARAM_WPAX_SELECT 7 ++ ++#define AUTH_ALG_OPEN_SYSTEM 0x1 ++#define AUTH_ALG_SHARED_KEY 0x2 ++#define AUTH_ALG_LEAP 0x00000004 ++ ++#define IEEE_MLME_STA_DEAUTH 1 ++#define IEEE_MLME_STA_DISASSOC 2 ++ ++#define IEEE_CRYPT_ERR_UNKNOWN_ALG 2 ++#define IEEE_CRYPT_ERR_UNKNOWN_ADDR 3 ++#define IEEE_CRYPT_ERR_CRYPT_INIT_FAILED 4 ++#define IEEE_CRYPT_ERR_KEY_SET_FAILED 5 ++#define IEEE_CRYPT_ERR_TX_KEY_SET_FAILED 6 ++#define IEEE_CRYPT_ERR_CARD_CONF_FAILED 7 ++ ++ ++#define IEEE_CRYPT_ALG_NAME_LEN 16 ++ ++#define WPA_CIPHER_NONE BIT(0) ++#define WPA_CIPHER_WEP40 BIT(1) ++#define WPA_CIPHER_WEP104 BIT(2) ++#define WPA_CIPHER_TKIP BIT(3) ++#define WPA_CIPHER_CCMP BIT(4) ++ ++ ++ ++#define WPA_SELECTOR_LEN 4 ++static u8 WPA_OUI_TYPE[] = { 0x00, 0x50, 0xf2, 1 }; ++static u16 WPA_VERSION = 1; ++static u8 WPA_AUTH_KEY_MGMT_NONE[] = { 0x00, 0x50, 0xf2, 0 }; ++static u8 WPA_AUTH_KEY_MGMT_UNSPEC_802_1X[] = { 0x00, 0x50, 0xf2, 1 }; ++static u8 WPA_AUTH_KEY_MGMT_PSK_OVER_802_1X[] = { 0x00, 0x50, 0xf2, 2 }; ++static u8 WPA_CIPHER_SUITE_NONE[] = { 0x00, 0x50, 0xf2, 0 }; ++static u8 WPA_CIPHER_SUITE_WEP40[] = { 0x00, 0x50, 0xf2, 1 }; ++static u8 WPA_CIPHER_SUITE_TKIP[] = { 0x00, 0x50, 0xf2, 2 }; ++//static u8 WPA_CIPHER_SUITE_WRAP[] = { 0x00, 0x50, 0xf2, 3 }; ++static u8 WPA_CIPHER_SUITE_CCMP[] = { 0x00, 0x50, 0xf2, 4 }; ++static u8 WPA_CIPHER_SUITE_WEP104[] = { 0x00, 0x50, 0xf2, 5 }; ++ ++ ++#define RSN_HEADER_LEN 4 ++#define RSN_SELECTOR_LEN 4 ++static u16 RSN_VERSION = 1; ++static u8 RSN_AUTH_KEY_MGMT_UNSPEC_802_1X[] = { 0x00, 0x0f, 0xac, 1 }; ++static u8 RSN_AUTH_KEY_MGMT_PSK_OVER_802_1X[] = { 0x00, 0x0f, 0xac, 2 }; ++static u8 RSN_CIPHER_SUITE_NONE[] = { 0x00, 0x0f, 0xac, 0 }; ++static u8 RSN_CIPHER_SUITE_WEP40[] = { 0x00, 0x0f, 0xac, 1 }; ++static u8 RSN_CIPHER_SUITE_TKIP[] = { 0x00, 0x0f, 0xac, 2 }; ++//static u8 RSN_CIPHER_SUITE_WRAP[] = { 0x00, 0x0f, 0xac, 3 }; ++static u8 RSN_CIPHER_SUITE_CCMP[] = { 0x00, 0x0f, 0xac, 4 }; ++static u8 RSN_CIPHER_SUITE_WEP104[] = { 0x00, 0x0f, 0xac, 5 }; ++ ++ ++enum NETWORK_TYPE ++{ ++ WIRELESS_INVALID = 0, ++ //Sub-Element ++ WIRELESS_11B = BIT(0), // tx: cck only , rx: cck only, hw: cck ++ WIRELESS_11G = BIT(1), // tx: ofdm only, rx: ofdm & cck, hw: cck & ofdm ++ WIRELESS_11A = BIT(2), // tx: ofdm only, rx: ofdm only, hw: ofdm only ++ WIRELESS_11_24N = BIT(3), // tx: MCS only, rx: MCS & cck, hw: MCS & cck ++ WIRELESS_11_5N = BIT(4), // tx: MCS only, rx: MCS & ofdm, hw: ofdm only ++ ++ //Combination ++ WIRELESS_11BG = (WIRELESS_11B|WIRELESS_11G), // tx: cck & ofdm, rx: cck & ofdm & MCS, hw: cck & ofdm ++ WIRELESS_11G_24N = (WIRELESS_11G|WIRELESS_11_24N), // tx: ofdm & MCS, rx: ofdm & cck & MCS, hw: cck & ofdm ++ WIRELESS_11A_5N = (WIRELESS_11A|WIRELESS_11_5N), // tx: ofdm & MCS, rx: ofdm & MCS, hw: ofdm only ++ WIRELESS_11BG_24N = (WIRELESS_11B|WIRELESS_11G|WIRELESS_11_24N), // tx: ofdm & cck & MCS, rx: ofdm & cck & MCS, hw: ofdm & cck ++ WIRELESS_11ABGN = (WIRELESS_11A|WIRELESS_11B|WIRELESS_11G|WIRELESS_11_24N|WIRELESS_11_5N), ++}; ++ ++#define SUPPORTED_24G_NETTYPE_MSK (WIRELESS_11B | WIRELESS_11G | WIRELESS_11_24N) ++#define SUPPORTED_5G_NETTYPE_MSK (WIRELESS_11A | WIRELESS_11_5N) ++ ++#define IsSupported24G(NetType) ((NetType) & SUPPORTED_24G_NETTYPE_MSK ? _TRUE : _FALSE) ++#define IsSupported5G(NetType) ((NetType) & SUPPORTED_5G_NETTYPE_MSK ? _TRUE : _FALSE) ++ ++#define IsEnableHWCCK(NetType) IsSupported24G(NetType) ++#define IsEnableHWOFDM(NetType) ((NetType) & (WIRELESS_11G|WIRELESS_11_24N|SUPPORTED_5G_NETTYPE_MSK) ? _TRUE : _FALSE) ++ ++#define IsSupportedRxCCK(NetType) IsEnableHWCCK(NetType) ++#define IsSupportedRxOFDM(NetType) IsEnableHWOFDM(NetType) ++#define IsSupportedRxMCS(NetType) IsEnableHWOFDM(NetType) ++ ++#define IsSupportedTxCCK(NetType) ((NetType) & (WIRELESS_11B) ? _TRUE : _FALSE) ++#define IsSupportedTxOFDM(NetType) ((NetType) & (WIRELESS_11G|WIRELESS_11A) ? _TRUE : _FALSE) ++#define IsSupportedTxMCS(NetType) ((NetType) & (WIRELESS_11_24N|WIRELESS_11_5N) ? _TRUE : _FALSE) ++ ++ ++typedef struct ieee_param { ++ u32 cmd; ++ u8 sta_addr[ETH_ALEN]; ++ union { ++ struct { ++ u8 name; ++ u32 value; ++ } wpa_param; ++ struct { ++ u32 len; ++ u8 reserved[32]; ++ u8 data[0]; ++ } wpa_ie; ++ struct{ ++ int command; ++ int reason_code; ++ } mlme; ++ struct { ++ u8 alg[IEEE_CRYPT_ALG_NAME_LEN]; ++ u8 set_tx; ++ u32 err; ++ u8 idx; ++ u8 seq[8]; /* sequence counter (set: RX, get: TX) */ ++ u16 key_len; ++ u8 key[0]; ++ } crypt; ++#ifdef CONFIG_AP_MODE ++ struct { ++ u16 aid; ++ u16 capability; ++ int flags; ++ u8 tx_supp_rates[16]; ++ struct rtw_ieee80211_ht_cap ht_cap; ++ } add_sta; ++ struct { ++ u8 reserved[2];//for set max_num_sta ++ u8 buf[0]; ++ } bcn_ie; ++#endif ++ ++ } u; ++}ieee_param; ++ ++ ++#if WIRELESS_EXT < 17 ++#define IW_QUAL_QUAL_INVALID 0x10 ++#define IW_QUAL_LEVEL_INVALID 0x20 ++#define IW_QUAL_NOISE_INVALID 0x40 ++#define IW_QUAL_QUAL_UPDATED 0x1 ++#define IW_QUAL_LEVEL_UPDATED 0x2 ++#define IW_QUAL_NOISE_UPDATED 0x4 ++#endif ++ ++#define IEEE80211_DATA_LEN 2304 ++/* Maximum size for the MA-UNITDATA primitive, 802.11 standard section ++ 6.2.1.1.2. ++ ++ The figure in section 7.1.2 suggests a body size of up to 2312 ++ bytes is allowed, which is a bit confusing, I suspect this ++ represents the 2304 bytes of real data, plus a possible 8 bytes of ++ WEP IV and ICV. (this interpretation suggested by Ramiro Barreiro) */ ++ ++ ++#define IEEE80211_HLEN 30 ++#define IEEE80211_FRAME_LEN (IEEE80211_DATA_LEN + IEEE80211_HLEN) ++ ++ ++/* this is stolen from ipw2200 driver */ ++#define IEEE_IBSS_MAC_HASH_SIZE 31 ++ ++struct ieee_ibss_seq { ++ u8 mac[ETH_ALEN]; ++ u16 seq_num; ++ u16 frag_num; ++ unsigned long packet_time; ++ _list list; ++}; ++ ++#if defined(PLATFORM_LINUX) || defined(CONFIG_RTL8711FW) ++ ++struct rtw_ieee80211_hdr { ++ u16 frame_ctl; ++ u16 duration_id; ++ u8 addr1[ETH_ALEN]; ++ u8 addr2[ETH_ALEN]; ++ u8 addr3[ETH_ALEN]; ++ u16 seq_ctl; ++ u8 addr4[ETH_ALEN]; ++} __attribute__ ((packed)); ++ ++struct rtw_ieee80211_hdr_3addr { ++ u16 frame_ctl; ++ u16 duration_id; ++ u8 addr1[ETH_ALEN]; ++ u8 addr2[ETH_ALEN]; ++ u8 addr3[ETH_ALEN]; ++ u16 seq_ctl; ++} __attribute__ ((packed)); ++ ++ ++struct rtw_ieee80211_hdr_qos { ++ u16 frame_ctl; ++ u16 duration_id; ++ u8 addr1[ETH_ALEN]; ++ u8 addr2[ETH_ALEN]; ++ u8 addr3[ETH_ALEN]; ++ u16 seq_ctl; ++ u8 addr4[ETH_ALEN]; ++ u16 qc; ++} __attribute__ ((packed)); ++ ++struct rtw_ieee80211_hdr_3addr_qos { ++ u16 frame_ctl; ++ u16 duration_id; ++ u8 addr1[ETH_ALEN]; ++ u8 addr2[ETH_ALEN]; ++ u8 addr3[ETH_ALEN]; ++ u16 seq_ctl; ++ u16 qc; ++} __attribute__ ((packed)); ++ ++struct eapol { ++ u8 snap[6]; ++ u16 ethertype; ++ u8 version; ++ u8 type; ++ u16 length; ++} __attribute__ ((packed)); ++ ++#endif ++ ++ ++ ++#ifdef PLATFORM_WINDOWS ++ ++#pragma pack(1) ++struct rtw_ieee80211_hdr { ++ u16 frame_ctl; ++ u16 duration_id; ++ u8 addr1[ETH_ALEN]; ++ u8 addr2[ETH_ALEN]; ++ u8 addr3[ETH_ALEN]; ++ u16 seq_ctl; ++ u8 addr4[ETH_ALEN]; ++}; ++ ++struct rtw_ieee80211_hdr_3addr { ++ u16 frame_ctl; ++ u16 duration_id; ++ u8 addr1[ETH_ALEN]; ++ u8 addr2[ETH_ALEN]; ++ u8 addr3[ETH_ALEN]; ++ u16 seq_ctl; ++}; ++ ++ ++struct rtw_ieee80211_hdr_qos { ++ struct rtw_ieee80211_hdr wlan_hdr; ++ u16 qc; ++}; ++ ++struct rtw_ieee80211_hdr_3addr_qos { ++ struct rtw_ieee80211_hdr_3addr wlan_hdr; ++ u16 qc; ++}; ++ ++struct eapol { ++ u8 snap[6]; ++ u16 ethertype; ++ u8 version; ++ u8 type; ++ u16 length; ++}; ++#pragma pack() ++ ++#endif ++ ++ ++ ++enum eap_type { ++ EAP_PACKET = 0, ++ EAPOL_START, ++ EAPOL_LOGOFF, ++ EAPOL_KEY, ++ EAPOL_ENCAP_ASF_ALERT ++}; ++ ++#define IEEE80211_3ADDR_LEN 24 ++#define IEEE80211_4ADDR_LEN 30 ++#define IEEE80211_FCS_LEN 4 ++ ++#define MIN_FRAG_THRESHOLD 256U ++#define MAX_FRAG_THRESHOLD 2346U ++ ++/* Frame control field constants */ ++#define RTW_IEEE80211_FCTL_VERS 0x0002 ++#define RTW_IEEE80211_FCTL_FTYPE 0x000c ++#define RTW_IEEE80211_FCTL_STYPE 0x00f0 ++#define RTW_IEEE80211_FCTL_TODS 0x0100 ++#define RTW_IEEE80211_FCTL_FROMDS 0x0200 ++#define RTW_IEEE80211_FCTL_MOREFRAGS 0x0400 ++#define RTW_IEEE80211_FCTL_RETRY 0x0800 ++#define RTW_IEEE80211_FCTL_PM 0x1000 ++#define RTW_IEEE80211_FCTL_MOREDATA 0x2000 ++#define RTW_IEEE80211_FCTL_WEP 0x4000 ++#define RTW_IEEE80211_FCTL_ORDER 0x8000 ++ ++#define RTW_IEEE80211_FTYPE_MGMT 0x0000 ++#define RTW_IEEE80211_FTYPE_CTL 0x0004 ++#define RTW_IEEE80211_FTYPE_DATA 0x0008 ++ ++/* management */ ++#define RTW_IEEE80211_STYPE_ASSOC_REQ 0x0000 ++#define RTW_IEEE80211_STYPE_ASSOC_RESP 0x0010 ++#define RTW_IEEE80211_STYPE_REASSOC_REQ 0x0020 ++#define RTW_IEEE80211_STYPE_REASSOC_RESP 0x0030 ++#define RTW_IEEE80211_STYPE_PROBE_REQ 0x0040 ++#define RTW_IEEE80211_STYPE_PROBE_RESP 0x0050 ++#define RTW_IEEE80211_STYPE_BEACON 0x0080 ++#define RTW_IEEE80211_STYPE_ATIM 0x0090 ++#define RTW_IEEE80211_STYPE_DISASSOC 0x00A0 ++#define RTW_IEEE80211_STYPE_AUTH 0x00B0 ++#define RTW_IEEE80211_STYPE_DEAUTH 0x00C0 ++ ++/* control */ ++#define RTW_IEEE80211_STYPE_PSPOLL 0x00A0 ++#define RTW_IEEE80211_STYPE_RTS 0x00B0 ++#define RTW_IEEE80211_STYPE_CTS 0x00C0 ++#define RTW_IEEE80211_STYPE_ACK 0x00D0 ++#define RTW_IEEE80211_STYPE_CFEND 0x00E0 ++#define RTW_IEEE80211_STYPE_CFENDACK 0x00F0 ++ ++/* data */ ++#define RTW_IEEE80211_STYPE_DATA 0x0000 ++#define RTW_IEEE80211_STYPE_DATA_CFACK 0x0010 ++#define RTW_IEEE80211_STYPE_DATA_CFPOLL 0x0020 ++#define RTW_IEEE80211_STYPE_DATA_CFACKPOLL 0x0030 ++#define RTW_IEEE80211_STYPE_NULLFUNC 0x0040 ++#define RTW_IEEE80211_STYPE_CFACK 0x0050 ++#define RTW_IEEE80211_STYPE_CFPOLL 0x0060 ++#define RTW_IEEE80211_STYPE_CFACKPOLL 0x0070 ++#define RTW_IEEE80211_QOS_DATAGRP 0x0080 ++#define RTW_IEEE80211_QoS_DATAGRP RTW_IEEE80211_QOS_DATAGRP ++ ++#define RTW_IEEE80211_SCTL_FRAG 0x000F ++#define RTW_IEEE80211_SCTL_SEQ 0xFFF0 ++ ++/* QoS,QOS */ ++#define NORMAL_ACK 0 ++#define NO_ACK 1 ++#define NON_EXPLICIT_ACK 2 ++#define BLOCK_ACK 3 ++ ++#ifndef ETH_P_PAE ++#define ETH_P_PAE 0x888E /* Port Access Entity (IEEE 802.1X) */ ++#endif /* ETH_P_PAE */ ++ ++#define ETH_P_PREAUTH 0x88C7 /* IEEE 802.11i pre-authentication */ ++ ++#define ETH_P_ECONET 0x0018 ++ ++#ifndef ETH_P_80211_RAW ++#define ETH_P_80211_RAW (ETH_P_ECONET + 1) ++#endif ++ ++/* IEEE 802.11 defines */ ++ ++#define P80211_OUI_LEN 3 ++ ++#if defined(PLATFORM_LINUX) || defined(CONFIG_RTL8711FW) ++ ++struct ieee80211_snap_hdr { ++ ++ u8 dsap; /* always 0xAA */ ++ u8 ssap; /* always 0xAA */ ++ u8 ctrl; /* always 0x03 */ ++ u8 oui[P80211_OUI_LEN]; /* organizational universal id */ ++ ++} __attribute__ ((packed)); ++ ++#endif ++ ++#ifdef PLATFORM_WINDOWS ++ ++#pragma pack(1) ++struct ieee80211_snap_hdr { ++ ++ u8 dsap; /* always 0xAA */ ++ u8 ssap; /* always 0xAA */ ++ u8 ctrl; /* always 0x03 */ ++ u8 oui[P80211_OUI_LEN]; /* organizational universal id */ ++ ++}; ++#pragma pack() ++ ++#endif ++ ++ ++#define SNAP_SIZE sizeof(struct ieee80211_snap_hdr) ++ ++#define WLAN_FC_GET_TYPE(fc) ((fc) & RTW_IEEE80211_FCTL_FTYPE) ++#define WLAN_FC_GET_STYPE(fc) ((fc) & RTW_IEEE80211_FCTL_STYPE) ++ ++#define WLAN_QC_GET_TID(qc) ((qc) & 0x0f) ++ ++#define WLAN_GET_SEQ_FRAG(seq) ((seq) & RTW_IEEE80211_SCTL_FRAG) ++#define WLAN_GET_SEQ_SEQ(seq) ((seq) & RTW_IEEE80211_SCTL_SEQ) ++ ++/* Authentication algorithms */ ++#define WLAN_AUTH_OPEN 0 ++#define WLAN_AUTH_SHARED_KEY 1 ++ ++#define WLAN_AUTH_CHALLENGE_LEN 128 ++ ++#define WLAN_CAPABILITY_BSS (1<<0) ++#define WLAN_CAPABILITY_IBSS (1<<1) ++#define WLAN_CAPABILITY_CF_POLLABLE (1<<2) ++#define WLAN_CAPABILITY_CF_POLL_REQUEST (1<<3) ++#define WLAN_CAPABILITY_PRIVACY (1<<4) ++#define WLAN_CAPABILITY_SHORT_PREAMBLE (1<<5) ++#define WLAN_CAPABILITY_PBCC (1<<6) ++#define WLAN_CAPABILITY_CHANNEL_AGILITY (1<<7) ++#define WLAN_CAPABILITY_SHORT_SLOT (1<<10) ++ ++/* Status codes */ ++#define WLAN_STATUS_SUCCESS 0 ++#define WLAN_STATUS_UNSPECIFIED_FAILURE 1 ++#define WLAN_STATUS_CAPS_UNSUPPORTED 10 ++#define WLAN_STATUS_REASSOC_NO_ASSOC 11 ++#define WLAN_STATUS_ASSOC_DENIED_UNSPEC 12 ++#define WLAN_STATUS_NOT_SUPPORTED_AUTH_ALG 13 ++#define WLAN_STATUS_UNKNOWN_AUTH_TRANSACTION 14 ++#define WLAN_STATUS_CHALLENGE_FAIL 15 ++#define WLAN_STATUS_AUTH_TIMEOUT 16 ++#define WLAN_STATUS_AP_UNABLE_TO_HANDLE_NEW_STA 17 ++#define WLAN_STATUS_ASSOC_DENIED_RATES 18 ++/* 802.11b */ ++#define WLAN_STATUS_ASSOC_DENIED_NOSHORT 19 ++#define WLAN_STATUS_ASSOC_DENIED_NOPBCC 20 ++#define WLAN_STATUS_ASSOC_DENIED_NOAGILITY 21 ++ ++/* Reason codes */ ++#define WLAN_REASON_UNSPECIFIED 1 ++#define WLAN_REASON_PREV_AUTH_NOT_VALID 2 ++#define WLAN_REASON_DEAUTH_LEAVING 3 ++#define WLAN_REASON_DISASSOC_DUE_TO_INACTIVITY 4 ++#define WLAN_REASON_DISASSOC_AP_BUSY 5 ++#define WLAN_REASON_CLASS2_FRAME_FROM_NONAUTH_STA 6 ++#define WLAN_REASON_CLASS3_FRAME_FROM_NONASSOC_STA 7 ++#define WLAN_REASON_DISASSOC_STA_HAS_LEFT 8 ++#define WLAN_REASON_STA_REQ_ASSOC_WITHOUT_AUTH 9 ++#define WLAN_REASON_JOIN_WRONG_CHANNEL 65534 ++ ++/* Information Element IDs */ ++#define WLAN_EID_SSID 0 ++#define WLAN_EID_SUPP_RATES 1 ++#define WLAN_EID_FH_PARAMS 2 ++#define WLAN_EID_DS_PARAMS 3 ++#define WLAN_EID_CF_PARAMS 4 ++#define WLAN_EID_TIM 5 ++#define WLAN_EID_IBSS_PARAMS 6 ++#define WLAN_EID_CHALLENGE 16 ++/* EIDs defined by IEEE 802.11h - START */ ++#define WLAN_EID_PWR_CONSTRAINT 32 ++#define WLAN_EID_PWR_CAPABILITY 33 ++#define WLAN_EID_TPC_REQUEST 34 ++#define WLAN_EID_TPC_REPORT 35 ++#define WLAN_EID_SUPPORTED_CHANNELS 36 ++#define WLAN_EID_CHANNEL_SWITCH 37 ++#define WLAN_EID_MEASURE_REQUEST 38 ++#define WLAN_EID_MEASURE_REPORT 39 ++#define WLAN_EID_QUITE 40 ++#define WLAN_EID_IBSS_DFS 41 ++/* EIDs defined by IEEE 802.11h - END */ ++#define WLAN_EID_ERP_INFO 42 ++#define WLAN_EID_HT_CAP 45 ++#define WLAN_EID_RSN 48 ++#define WLAN_EID_EXT_SUPP_RATES 50 ++#define WLAN_EID_MOBILITY_DOMAIN 54 ++#define WLAN_EID_FAST_BSS_TRANSITION 55 ++#define WLAN_EID_TIMEOUT_INTERVAL 56 ++#define WLAN_EID_RIC_DATA 57 ++#define WLAN_EID_HT_OPERATION 61 ++#define WLAN_EID_SECONDARY_CHANNEL_OFFSET 62 ++#define WLAN_EID_20_40_BSS_COEXISTENCE 72 ++#define WLAN_EID_20_40_BSS_INTOLERANT 73 ++#define WLAN_EID_OVERLAPPING_BSS_SCAN_PARAMS 74 ++#define WLAN_EID_MMIE 76 ++#define WLAN_EID_VENDOR_SPECIFIC 221 ++#define WLAN_EID_GENERIC (WLAN_EID_VENDOR_SPECIFIC) ++ ++#define IEEE80211_MGMT_HDR_LEN 24 ++#define IEEE80211_DATA_HDR3_LEN 24 ++#define IEEE80211_DATA_HDR4_LEN 30 ++ ++ ++#define IEEE80211_STATMASK_SIGNAL (1<<0) ++#define IEEE80211_STATMASK_RSSI (1<<1) ++#define IEEE80211_STATMASK_NOISE (1<<2) ++#define IEEE80211_STATMASK_RATE (1<<3) ++#define IEEE80211_STATMASK_WEMASK 0x7 ++ ++ ++#define IEEE80211_CCK_MODULATION (1<<0) ++#define IEEE80211_OFDM_MODULATION (1<<1) ++ ++#define IEEE80211_24GHZ_BAND (1<<0) ++#define IEEE80211_52GHZ_BAND (1<<1) ++ ++#define IEEE80211_CCK_RATE_LEN 4 ++#define IEEE80211_NUM_OFDM_RATESLEN 8 ++ ++ ++#define IEEE80211_CCK_RATE_1MB 0x02 ++#define IEEE80211_CCK_RATE_2MB 0x04 ++#define IEEE80211_CCK_RATE_5MB 0x0B ++#define IEEE80211_CCK_RATE_11MB 0x16 ++#define IEEE80211_OFDM_RATE_LEN 8 ++#define IEEE80211_OFDM_RATE_6MB 0x0C ++#define IEEE80211_OFDM_RATE_9MB 0x12 ++#define IEEE80211_OFDM_RATE_12MB 0x18 ++#define IEEE80211_OFDM_RATE_18MB 0x24 ++#define IEEE80211_OFDM_RATE_24MB 0x30 ++#define IEEE80211_OFDM_RATE_36MB 0x48 ++#define IEEE80211_OFDM_RATE_48MB 0x60 ++#define IEEE80211_OFDM_RATE_54MB 0x6C ++#define IEEE80211_BASIC_RATE_MASK 0x80 ++ ++#define IEEE80211_CCK_RATE_1MB_MASK (1<<0) ++#define IEEE80211_CCK_RATE_2MB_MASK (1<<1) ++#define IEEE80211_CCK_RATE_5MB_MASK (1<<2) ++#define IEEE80211_CCK_RATE_11MB_MASK (1<<3) ++#define IEEE80211_OFDM_RATE_6MB_MASK (1<<4) ++#define IEEE80211_OFDM_RATE_9MB_MASK (1<<5) ++#define IEEE80211_OFDM_RATE_12MB_MASK (1<<6) ++#define IEEE80211_OFDM_RATE_18MB_MASK (1<<7) ++#define IEEE80211_OFDM_RATE_24MB_MASK (1<<8) ++#define IEEE80211_OFDM_RATE_36MB_MASK (1<<9) ++#define IEEE80211_OFDM_RATE_48MB_MASK (1<<10) ++#define IEEE80211_OFDM_RATE_54MB_MASK (1<<11) ++ ++#define IEEE80211_CCK_RATES_MASK 0x0000000F ++#define IEEE80211_CCK_BASIC_RATES_MASK (IEEE80211_CCK_RATE_1MB_MASK | \ ++ IEEE80211_CCK_RATE_2MB_MASK) ++#define IEEE80211_CCK_DEFAULT_RATES_MASK (IEEE80211_CCK_BASIC_RATES_MASK | \ ++ IEEE80211_CCK_RATE_5MB_MASK | \ ++ IEEE80211_CCK_RATE_11MB_MASK) ++ ++#define IEEE80211_OFDM_RATES_MASK 0x00000FF0 ++#define IEEE80211_OFDM_BASIC_RATES_MASK (IEEE80211_OFDM_RATE_6MB_MASK | \ ++ IEEE80211_OFDM_RATE_12MB_MASK | \ ++ IEEE80211_OFDM_RATE_24MB_MASK) ++#define IEEE80211_OFDM_DEFAULT_RATES_MASK (IEEE80211_OFDM_BASIC_RATES_MASK | \ ++ IEEE80211_OFDM_RATE_9MB_MASK | \ ++ IEEE80211_OFDM_RATE_18MB_MASK | \ ++ IEEE80211_OFDM_RATE_36MB_MASK | \ ++ IEEE80211_OFDM_RATE_48MB_MASK | \ ++ IEEE80211_OFDM_RATE_54MB_MASK) ++#define IEEE80211_DEFAULT_RATES_MASK (IEEE80211_OFDM_DEFAULT_RATES_MASK | \ ++ IEEE80211_CCK_DEFAULT_RATES_MASK) ++ ++#define IEEE80211_NUM_OFDM_RATES 8 ++#define IEEE80211_NUM_CCK_RATES 4 ++#define IEEE80211_OFDM_SHIFT_MASK_A 4 ++ ++ ++ ++ ++/* NOTE: This data is for statistical purposes; not all hardware provides this ++ * information for frames received. Not setting these will not cause ++ * any adverse affects. */ ++struct ieee80211_rx_stats { ++ //u32 mac_time[2]; ++ s8 rssi; ++ u8 signal; ++ u8 noise; ++ u8 received_channel; ++ u16 rate; /* in 100 kbps */ ++ //u8 control; ++ u8 mask; ++ u8 freq; ++ u16 len; ++}; ++ ++/* IEEE 802.11 requires that STA supports concurrent reception of at least ++ * three fragmented frames. This define can be increased to support more ++ * concurrent frames, but it should be noted that each entry can consume about ++ * 2 kB of RAM and increasing cache size will slow down frame reassembly. */ ++#define IEEE80211_FRAG_CACHE_LEN 4 ++ ++struct ieee80211_frag_entry { ++ u32 first_frag_time; ++ uint seq; ++ uint last_frag; ++ uint qos; //jackson ++ uint tid; //jackson ++ struct sk_buff *skb; ++ u8 src_addr[ETH_ALEN]; ++ u8 dst_addr[ETH_ALEN]; ++}; ++ ++struct ieee80211_stats { ++ uint tx_unicast_frames; ++ uint tx_multicast_frames; ++ uint tx_fragments; ++ uint tx_unicast_octets; ++ uint tx_multicast_octets; ++ uint tx_deferred_transmissions; ++ uint tx_single_retry_frames; ++ uint tx_multiple_retry_frames; ++ uint tx_retry_limit_exceeded; ++ uint tx_discards; ++ uint rx_unicast_frames; ++ uint rx_multicast_frames; ++ uint rx_fragments; ++ uint rx_unicast_octets; ++ uint rx_multicast_octets; ++ uint rx_fcs_errors; ++ uint rx_discards_no_buffer; ++ uint tx_discards_wrong_sa; ++ uint rx_discards_undecryptable; ++ uint rx_message_in_msg_fragments; ++ uint rx_message_in_bad_msg_fragments; ++}; ++ ++struct ieee80211_softmac_stats{ ++ uint rx_ass_ok; ++ uint rx_ass_err; ++ uint rx_probe_rq; ++ uint tx_probe_rs; ++ uint tx_beacons; ++ uint rx_auth_rq; ++ uint rx_auth_rs_ok; ++ uint rx_auth_rs_err; ++ uint tx_auth_rq; ++ uint no_auth_rs; ++ uint no_ass_rs; ++ uint tx_ass_rq; ++ uint rx_ass_rq; ++ uint tx_probe_rq; ++ uint reassoc; ++ uint swtxstop; ++ uint swtxawake; ++}; ++ ++#define SEC_KEY_1 (1<<0) ++#define SEC_KEY_2 (1<<1) ++#define SEC_KEY_3 (1<<2) ++#define SEC_KEY_4 (1<<3) ++#define SEC_ACTIVE_KEY (1<<4) ++#define SEC_AUTH_MODE (1<<5) ++#define SEC_UNICAST_GROUP (1<<6) ++#define SEC_LEVEL (1<<7) ++#define SEC_ENABLED (1<<8) ++ ++#define SEC_LEVEL_0 0 /* None */ ++#define SEC_LEVEL_1 1 /* WEP 40 and 104 bit */ ++#define SEC_LEVEL_2 2 /* Level 1 + TKIP */ ++#define SEC_LEVEL_2_CKIP 3 /* Level 1 + CKIP */ ++#define SEC_LEVEL_3 4 /* Level 2 + CCMP */ ++ ++#define WEP_KEYS 4 ++#define WEP_KEY_LEN 13 ++ ++ ++ ++#if defined(PLATFORM_LINUX) || defined(CONFIG_RTL8711FW) ++ ++struct ieee80211_security { ++ u16 active_key:2, ++ enabled:1, ++ auth_mode:2, ++ auth_algo:4, ++ unicast_uses_group:1; ++ u8 key_sizes[WEP_KEYS]; ++ u8 keys[WEP_KEYS][WEP_KEY_LEN]; ++ u8 level; ++ u16 flags; ++} __attribute__ ((packed)); ++ ++#endif ++ ++#ifdef PLATFORM_WINDOWS ++ ++#pragma pack(1) ++struct ieee80211_security { ++ u16 active_key:2, ++ enabled:1, ++ auth_mode:2, ++ auth_algo:4, ++ unicast_uses_group:1; ++ u8 key_sizes[WEP_KEYS]; ++ u8 keys[WEP_KEYS][WEP_KEY_LEN]; ++ u8 level; ++ u16 flags; ++} ; ++#pragma pack() ++ ++#endif ++ ++/* ++ ++ 802.11 data frame from AP ++ ++ ,-------------------------------------------------------------------. ++Bytes | 2 | 2 | 6 | 6 | 6 | 2 | 0..2312 | 4 | ++ |------|------|---------|---------|---------|------|---------|------| ++Desc. | ctrl | dura | DA/RA | TA | SA | Sequ | frame | fcs | ++ | | tion | (BSSID) | | | ence | data | | ++ `-------------------------------------------------------------------' ++ ++Total: 28-2340 bytes ++ ++*/ ++ ++struct ieee80211_header_data { ++ u16 frame_ctl; ++ u16 duration_id; ++ u8 addr1[6]; ++ u8 addr2[6]; ++ u8 addr3[6]; ++ u16 seq_ctrl; ++}; ++ ++#define BEACON_PROBE_SSID_ID_POSITION 12 ++ ++/* Management Frame Information Element Types */ ++#define MFIE_TYPE_SSID 0 ++#define MFIE_TYPE_RATES 1 ++#define MFIE_TYPE_FH_SET 2 ++#define MFIE_TYPE_DS_SET 3 ++#define MFIE_TYPE_CF_SET 4 ++#define MFIE_TYPE_TIM 5 ++#define MFIE_TYPE_IBSS_SET 6 ++#define MFIE_TYPE_CHALLENGE 16 ++#define MFIE_TYPE_ERP 42 ++#define MFIE_TYPE_RSN 48 ++#define MFIE_TYPE_RATES_EX 50 ++#define MFIE_TYPE_GENERIC 221 ++ ++#if defined(PLATFORM_LINUX) || defined(CONFIG_RTL8711FW) ++ ++struct ieee80211_info_element_hdr { ++ u8 id; ++ u8 len; ++} __attribute__ ((packed)); ++ ++struct ieee80211_info_element { ++ u8 id; ++ u8 len; ++ u8 data[0]; ++} __attribute__ ((packed)); ++#endif ++ ++#ifdef CONFIG_TDLS ++/* TDLS */ ++#define TDLS_MIC_LEN 16 ++#define WPA_NONCE_LEN 32 ++#define TDLS_TIMEOUT_LEN 4 ++ ++struct wpa_tdls_ftie { ++ u8 ie_type; /* FTIE */ ++ u8 ie_len; ++ u8 mic_ctrl[2]; ++ u8 mic[TDLS_MIC_LEN]; ++ u8 Anonce[WPA_NONCE_LEN]; /* Responder Nonce in TDLS */ ++ u8 Snonce[WPA_NONCE_LEN]; /* Initiator Nonce in TDLS */ ++ /* followed by optional elements */ ++} ; ++ ++struct wpa_tdls_timeoutie { ++ u8 ie_type; /* Timeout IE */ ++ u8 ie_len; ++ u8 interval_type; ++ u8 value[TDLS_TIMEOUT_LEN]; ++} ; ++ ++struct wpa_tdls_lnkid { ++ u8 ie_type; /* Link Identifier IE */ ++ u8 ie_len; ++ u8 bssid[ETH_ALEN]; ++ u8 init_sta[ETH_ALEN]; ++ u8 resp_sta[ETH_ALEN]; ++} ; ++ ++static u8 TDLS_RSNIE[]={ 0x01, 0x00, //version shall be set to 1 ++ 0x00, 0x0f, 0xac, 0x07, //group sipher suite ++ 0x01, 0x00, //pairwise cipher suite count ++ 0x00, 0x0f, 0xac, 0x04, //pairwise cipher suite list; CCMP only ++ 0x01, 0x00, //AKM suite count ++ 0x00, 0x0f, 0xac, 0x07, //TPK Handshake ++ 0x00, 0x02, ++ //PMKID shall not be present ++ }; ++ ++static u8 TDLS_WMMIE[]={0x00, 0x50, 0xf2, 0x02, 0x00, 0x01, 0x00}; //Qos info all set zero ++ ++static u8 TDLS_EXT_CAPIE[] = {0x00, 0x00, 0x00, 0x50, 0x20}; //bit(28), bit(30), bit(37) ++#endif ++ ++#ifdef PLATFORM_WINDOWS ++ ++#pragma pack(1) ++struct ieee80211_info_element_hdr { ++ u8 id; ++ u8 len; ++} ; ++ ++struct ieee80211_info_element { ++ u8 id; ++ u8 len; ++ u8 data[0]; ++} ; ++#pragma pack() ++ ++#endif ++ ++ ++/* ++ * These are the data types that can make up management packets ++ * ++ u16 auth_algorithm; ++ u16 auth_sequence; ++ u16 beacon_interval; ++ u16 capability; ++ u8 current_ap[ETH_ALEN]; ++ u16 listen_interval; ++ struct { ++ u16 association_id:14, reserved:2; ++ } __attribute__ ((packed)); ++ u32 time_stamp[2]; ++ u16 reason; ++ u16 status; ++*/ ++ ++#define IEEE80211_DEFAULT_TX_ESSID "Penguin" ++#define IEEE80211_DEFAULT_BASIC_RATE 10 ++ ++ ++#if defined(PLATFORM_LINUX) || defined(CONFIG_RTL8711FW) ++ ++ ++struct ieee80211_authentication { ++ struct ieee80211_header_data header; ++ u16 algorithm; ++ u16 transaction; ++ u16 status; ++ //struct ieee80211_info_element_hdr info_element; ++} __attribute__ ((packed)); ++ ++ ++struct ieee80211_probe_response { ++ struct ieee80211_header_data header; ++ u32 time_stamp[2]; ++ u16 beacon_interval; ++ u16 capability; ++ struct ieee80211_info_element info_element; ++} __attribute__ ((packed)); ++ ++struct ieee80211_probe_request { ++ struct ieee80211_header_data header; ++ /*struct ieee80211_info_element info_element;*/ ++} __attribute__ ((packed)); ++ ++struct ieee80211_assoc_request_frame { ++ struct rtw_ieee80211_hdr_3addr header; ++ u16 capability; ++ u16 listen_interval; ++ //u8 current_ap[ETH_ALEN]; ++ struct ieee80211_info_element_hdr info_element; ++} __attribute__ ((packed)); ++ ++struct ieee80211_assoc_response_frame { ++ struct rtw_ieee80211_hdr_3addr header; ++ u16 capability; ++ u16 status; ++ u16 aid; ++// struct ieee80211_info_element info_element; /* supported rates */ ++} __attribute__ ((packed)); ++#endif ++ ++ ++ ++#ifdef PLATFORM_WINDOWS ++ ++#pragma pack(1) ++ ++struct ieee80211_authentication { ++ struct ieee80211_header_data header; ++ u16 algorithm; ++ u16 transaction; ++ u16 status; ++ //struct ieee80211_info_element_hdr info_element; ++} ; ++ ++ ++struct ieee80211_probe_response { ++ struct ieee80211_header_data header; ++ u32 time_stamp[2]; ++ u16 beacon_interval; ++ u16 capability; ++ struct ieee80211_info_element info_element; ++} ; ++ ++struct ieee80211_probe_request { ++ struct ieee80211_header_data header; ++ /*struct ieee80211_info_element info_element;*/ ++} ; ++ ++struct ieee80211_assoc_request_frame { ++ struct rtw_ieee80211_hdr_3addr header; ++ u16 capability; ++ u16 listen_interval; ++ //u8 current_ap[ETH_ALEN]; ++ struct ieee80211_info_element_hdr info_element; ++} ; ++ ++struct ieee80211_assoc_response_frame { ++ struct rtw_ieee80211_hdr_3addr header; ++ u16 capability; ++ u16 status; ++ u16 aid; ++// struct ieee80211_info_element info_element; /* supported rates */ ++}; ++ ++#pragma pack() ++ ++#endif ++ ++ ++ ++ ++struct ieee80211_txb { ++ u8 nr_frags; ++ u8 encrypted; ++ u16 reserved; ++ u16 frag_size; ++ u16 payload_size; ++ struct sk_buff *fragments[0]; ++}; ++ ++ ++/* SWEEP TABLE ENTRIES NUMBER*/ ++#define MAX_SWEEP_TAB_ENTRIES 42 ++#define MAX_SWEEP_TAB_ENTRIES_PER_PACKET 7 ++/* MAX_RATES_LENGTH needs to be 12. The spec says 8, and many APs ++ * only use 8, and then use extended rates for the remaining supported ++ * rates. Other APs, however, stick all of their supported rates on the ++ * main rates information element... */ ++#define MAX_RATES_LENGTH ((u8)12) ++#define MAX_RATES_EX_LENGTH ((u8)16) ++#define MAX_NETWORK_COUNT 128 ++#define MAX_CHANNEL_NUMBER 161 ++#define IEEE80211_SOFTMAC_SCAN_TIME 400 ++//(HZ / 2) ++#define IEEE80211_SOFTMAC_ASSOC_RETRY_TIME (HZ * 2) ++ ++#define CRC_LENGTH 4U ++ ++#define MAX_WPA_IE_LEN (128) ++#define MAX_WPS_IE_LEN (512) ++#define MAX_P2P_IE_LEN (256) ++#define MAX_WFD_IE_LEN (128) ++ ++#define NETWORK_EMPTY_ESSID (1<<0) ++#define NETWORK_HAS_OFDM (1<<1) ++#define NETWORK_HAS_CCK (1<<2) ++ ++#define IEEE80211_DTIM_MBCAST 4 ++#define IEEE80211_DTIM_UCAST 2 ++#define IEEE80211_DTIM_VALID 1 ++#define IEEE80211_DTIM_INVALID 0 ++ ++#define IEEE80211_PS_DISABLED 0 ++#define IEEE80211_PS_UNICAST IEEE80211_DTIM_UCAST ++#define IEEE80211_PS_MBCAST IEEE80211_DTIM_MBCAST ++#define IW_ESSID_MAX_SIZE 32 ++#if 0 ++struct ieee80211_network { ++ /* These entries are used to identify a unique network */ ++ u8 bssid[ETH_ALEN]; ++ u8 channel; ++ /* Ensure null-terminated for any debug msgs */ ++ u8 ssid[IW_ESSID_MAX_SIZE + 1]; ++ u8 ssid_len; ++ u8 rssi; //relative signal strength ++ u8 sq; //signal quality ++ ++ /* These are network statistics */ ++ //struct ieee80211_rx_stats stats; ++ u16 capability; ++ u16 aid; ++ u8 rates[MAX_RATES_LENGTH]; ++ u8 rates_len; ++ u8 rates_ex[MAX_RATES_EX_LENGTH]; ++ u8 rates_ex_len; ++ ++ u8 edca_parmsets[18]; ++ ++ u8 mode; ++ u8 flags; ++ u8 time_stamp[8]; ++ u16 beacon_interval; ++ u16 listen_interval; ++ u16 atim_window; ++ u8 wpa_ie[MAX_WPA_IE_LEN]; ++ size_t wpa_ie_len; ++ u8 rsn_ie[MAX_WPA_IE_LEN]; ++ size_t rsn_ie_len; ++ u8 country[6]; ++ u8 dtim_period; ++ u8 dtim_data; ++ u8 power_constraint; ++ u8 qosinfo; ++ u8 qbssload[5]; ++ u8 network_type; ++ int join_res; ++ unsigned long last_scanned; ++}; ++#endif ++/* ++join_res: ++-1: authentication fail ++-2: association fail ++> 0: TID ++*/ ++ ++enum ieee80211_state { ++ ++ /* the card is not linked at all */ ++ IEEE80211_NOLINK = 0, ++ ++ /* IEEE80211_ASSOCIATING* are for BSS client mode ++ * the driver shall not perform RX filtering unless ++ * the state is LINKED. ++ * The driver shall just check for the state LINKED and ++ * defaults to NOLINK for ALL the other states (including ++ * LINKED_SCANNING) ++ */ ++ ++ /* the association procedure will start (wq scheduling)*/ ++ IEEE80211_ASSOCIATING, ++ IEEE80211_ASSOCIATING_RETRY, ++ ++ /* the association procedure is sending AUTH request*/ ++ IEEE80211_ASSOCIATING_AUTHENTICATING, ++ ++ /* the association procedure has successfully authentcated ++ * and is sending association request ++ */ ++ IEEE80211_ASSOCIATING_AUTHENTICATED, ++ ++ /* the link is ok. the card associated to a BSS or linked ++ * to a ibss cell or acting as an AP and creating the bss ++ */ ++ IEEE80211_LINKED, ++ ++ /* same as LINKED, but the driver shall apply RX filter ++ * rules as we are in NO_LINK mode. As the card is still ++ * logically linked, but it is doing a syncro site survey ++ * then it will be back to LINKED state. ++ */ ++ IEEE80211_LINKED_SCANNING, ++ ++}; ++ ++#define DEFAULT_MAX_SCAN_AGE (15 * HZ) ++#define DEFAULT_FTS 2346 ++#define MAC_FMT "%02x:%02x:%02x:%02x:%02x:%02x" ++#define MAC_ARG(x) ((u8*)(x))[0],((u8*)(x))[1],((u8*)(x))[2],((u8*)(x))[3],((u8*)(x))[4],((u8*)(x))[5] ++ ++extern __inline int is_multicast_mac_addr(const u8 *addr) ++{ ++ return ((addr[0] != 0xff) && (0x01 & addr[0])); ++} ++ ++extern __inline int is_broadcast_mac_addr(const u8 *addr) ++{ ++ return ((addr[0] == 0xff) && (addr[1] == 0xff) && (addr[2] == 0xff) && \ ++ (addr[3] == 0xff) && (addr[4] == 0xff) && (addr[5] == 0xff)); ++} ++ ++#define CFG_IEEE80211_RESERVE_FCS (1<<0) ++#define CFG_IEEE80211_COMPUTE_FCS (1<<1) ++ ++typedef struct tx_pending_t{ ++ int frag; ++ struct ieee80211_txb *txb; ++}tx_pending_t; ++ ++ ++ ++#define MAXTID 16 ++ ++#define IEEE_A (1<<0) ++#define IEEE_B (1<<1) ++#define IEEE_G (1<<2) ++#define IEEE_MODE_MASK (IEEE_A|IEEE_B|IEEE_G) ++ ++extern __inline int ieee80211_is_empty_essid(const char *essid, int essid_len) ++{ ++ /* Single white space is for Linksys APs */ ++ if (essid_len == 1 && essid[0] == ' ') ++ return 1; ++ ++ /* Otherwise, if the entire essid is 0, we assume it is hidden */ ++ while (essid_len) { ++ essid_len--; ++ if (essid[essid_len] != '\0') ++ return 0; ++ } ++ ++ return 1; ++} ++ ++extern __inline int ieee80211_get_hdrlen(u16 fc) ++{ ++ int hdrlen = 24; ++ ++ switch (WLAN_FC_GET_TYPE(fc)) { ++ case RTW_IEEE80211_FTYPE_DATA: ++ if (fc & RTW_IEEE80211_QOS_DATAGRP) ++ hdrlen += 2; ++ if ((fc & RTW_IEEE80211_FCTL_FROMDS) && (fc & RTW_IEEE80211_FCTL_TODS)) ++ hdrlen += 6; /* Addr4 */ ++ break; ++ case RTW_IEEE80211_FTYPE_CTL: ++ switch (WLAN_FC_GET_STYPE(fc)) { ++ case RTW_IEEE80211_STYPE_CTS: ++ case RTW_IEEE80211_STYPE_ACK: ++ hdrlen = 10; ++ break; ++ default: ++ hdrlen = 16; ++ break; ++ } ++ break; ++ } ++ ++ return hdrlen; ++} ++ ++#if 0 ++/* Action frame categories (IEEE 802.11-2007, 7.3.1.11, Table 7-24) */ ++#define WLAN_ACTION_SPECTRUM_MGMT 0 ++#define WLAN_ACTION_QOS 1 ++#define WLAN_ACTION_DLS 2 ++#define WLAN_ACTION_BLOCK_ACK 3 ++#define WLAN_ACTION_RADIO_MEASUREMENT 5 ++#define WLAN_ACTION_FT 6 ++#define WLAN_ACTION_SA_QUERY 8 ++#define WLAN_ACTION_WMM 17 ++#endif ++ ++ ++/* Action category code */ ++enum rtw_ieee80211_category { ++ RTW_WLAN_CATEGORY_SPECTRUM_MGMT = 0, ++ RTW_WLAN_CATEGORY_QOS = 1, ++ RTW_WLAN_CATEGORY_DLS = 2, ++ RTW_WLAN_CATEGORY_BACK = 3, ++ RTW_WLAN_CATEGORY_PUBLIC = 4, //IEEE 802.11 public action frames ++ RTW_WLAN_CATEGORY_RADIO_MEASUREMENT = 5, ++ RTW_WLAN_CATEGORY_FT = 6, ++ RTW_WLAN_CATEGORY_HT = 7, ++ RTW_WLAN_CATEGORY_SA_QUERY = 8, ++ RTW_WLAN_CATEGORY_TDLS = 12, ++ RTW_WLAN_CATEGORY_WMM = 17, ++ RTW_WLAN_CATEGORY_P2P = 0x7f,//P2P action frames ++}; ++ ++/* SPECTRUM_MGMT action code */ ++enum rtw_ieee80211_spectrum_mgmt_actioncode { ++ RTW_WLAN_ACTION_SPCT_MSR_REQ = 0, ++ RTW_WLAN_ACTION_SPCT_MSR_RPRT = 1, ++ RTW_WLAN_ACTION_SPCT_TPC_REQ = 2, ++ RTW_WLAN_ACTION_SPCT_TPC_RPRT = 3, ++ RTW_WLAN_ACTION_SPCT_CHL_SWITCH = 4, ++ RTW_WLAN_ACTION_SPCT_EXT_CHL_SWITCH = 5, ++}; ++ ++enum _PUBLIC_ACTION{ ++ ACT_PUBLIC_BSSCOEXIST = 0, // 20/40 BSS Coexistence ++ ACT_PUBLIC_MP = 7, // Measurement Pilot ++ ACT_PUBLIC_P2P = 9, // WIFI_DIRECT ++}; ++ ++#ifdef CONFIG_TDLS ++enum TDLS_ACTION_FIELD{ ++ TDLS_SETUP_REQUEST = 0, ++ TDLS_SETUP_RESPONSE = 1, ++ TDLS_SETUP_CONFIRM = 2, ++ TDLS_TEARDOWN = 3, ++ TDLS_PEER_TRAFFIC_INDICATION = 4, ++ TDLS_CHANNEL_SWITCH_REQUEST = 5, ++ TDLS_CHANNEL_SWITCH_RESPONSE = 6, ++ TDLS_PEER_PSM_REQUEST = 7, ++ TDLS_PEER_PSM_RESPONSE = 8, ++ TDLS_PEER_TRAFFIC_RESPONSE = 9, ++ TDLS_DISCOVERY_REQUEST = 10, ++ TDLS_DISCOVERY_RESPONSE = 14, //it's used in public action frame ++}; ++#endif ++ ++/* BACK action code */ ++enum rtw_ieee80211_back_actioncode { ++ RTW_WLAN_ACTION_ADDBA_REQ = 0, ++ RTW_WLAN_ACTION_ADDBA_RESP = 1, ++ RTW_WLAN_ACTION_DELBA = 2, ++}; ++ ++/* HT features action code */ ++enum rtw_ieee80211_ht_actioncode { ++ RTW_WLAN_ACTION_NOTIFY_CH_WIDTH = 0, ++ RTW_WLAN_ACTION_SM_PS = 1, ++ RTW_WLAN_ACTION_PSPM = 2, ++ RTW_WLAN_ACTION_PCO_PHASE = 3, ++ RTW_WLAN_ACTION_MIMO_CSI_MX = 4, ++ RTW_WLAN_ACTION_MIMO_NONCP_BF = 5, ++ RTW_WLAN_ACTION_MIMP_CP_BF = 6, ++ RTW_WLAN_ACTION_ASEL_INDICATES_FB = 7, ++ RTW_WLAN_ACTION_HI_INFO_EXCHG = 8, ++}; ++ ++/* BACK (block-ack) parties */ ++enum rtw_ieee80211_back_parties { ++ RTW_WLAN_BACK_RECIPIENT = 0, ++ RTW_WLAN_BACK_INITIATOR = 1, ++ RTW_WLAN_BACK_TIMER = 2, ++}; ++ ++ ++#define OUI_MICROSOFT 0x0050f2 /* Microsoft (also used in Wi-Fi specs) ++ * 00:50:F2 */ ++ ++#define WME_OUI_TYPE 2 ++#define WME_OUI_SUBTYPE_INFORMATION_ELEMENT 0 ++#define WME_OUI_SUBTYPE_PARAMETER_ELEMENT 1 ++#define WME_OUI_SUBTYPE_TSPEC_ELEMENT 2 ++#define WME_VERSION 1 ++ ++#define WME_ACTION_CODE_SETUP_REQUEST 0 ++#define WME_ACTION_CODE_SETUP_RESPONSE 1 ++#define WME_ACTION_CODE_TEARDOWN 2 ++ ++#define WME_SETUP_RESPONSE_STATUS_ADMISSION_ACCEPTED 0 ++#define WME_SETUP_RESPONSE_STATUS_INVALID_PARAMETERS 1 ++#define WME_SETUP_RESPONSE_STATUS_REFUSED 3 ++ ++#define WME_TSPEC_DIRECTION_UPLINK 0 ++#define WME_TSPEC_DIRECTION_DOWNLINK 1 ++#define WME_TSPEC_DIRECTION_BI_DIRECTIONAL 3 ++ ++ ++#define OUI_BROADCOM 0x00904c /* Broadcom (Epigram) */ ++ ++#define VENDOR_HT_CAPAB_OUI_TYPE 0x33 /* 00-90-4c:0x33 */ ++ ++/* Parsed Information Elements */ ++struct ieee802_11_elems { ++ u8 *ssid; ++ u8 ssid_len; ++ u8 *supp_rates; ++ u8 supp_rates_len; ++ u8 *fh_params; ++ u8 fh_params_len; ++ u8 *ds_params; ++ u8 ds_params_len; ++ u8 *cf_params; ++ u8 cf_params_len; ++ u8 *tim; ++ u8 tim_len; ++ u8 *ibss_params; ++ u8 ibss_params_len; ++ u8 *challenge; ++ u8 challenge_len; ++ u8 *erp_info; ++ u8 erp_info_len; ++ u8 *ext_supp_rates; ++ u8 ext_supp_rates_len; ++ u8 *wpa_ie; ++ u8 wpa_ie_len; ++ u8 *rsn_ie; ++ u8 rsn_ie_len; ++ u8 *wme; ++ u8 wme_len; ++ u8 *wme_tspec; ++ u8 wme_tspec_len; ++ u8 *wps_ie; ++ u8 wps_ie_len; ++ u8 *power_cap; ++ u8 power_cap_len; ++ u8 *supp_channels; ++ u8 supp_channels_len; ++ u8 *mdie; ++ u8 mdie_len; ++ u8 *ftie; ++ u8 ftie_len; ++ u8 *timeout_int; ++ u8 timeout_int_len; ++ u8 *ht_capabilities; ++ u8 ht_capabilities_len; ++ u8 *ht_operation; ++ u8 ht_operation_len; ++ u8 *vendor_ht_cap; ++ u8 vendor_ht_cap_len; ++}; ++ ++typedef enum { ParseOK = 0, ParseUnknown = 1, ParseFailed = -1 } ParseRes; ++ ++ParseRes rtw_ieee802_11_parse_elems(u8 *start, uint len, ++ struct ieee802_11_elems *elems, ++ int show_errors); ++ ++u8 *rtw_set_fixed_ie(unsigned char *pbuf, unsigned int len, unsigned char *source, unsigned int *frlen); ++u8 *rtw_set_ie(u8 *pbuf, sint index, uint len, u8 *source, uint *frlen); ++u8 *rtw_get_ie(u8*pbuf, sint index, sint *len, sint limit); ++void rtw_set_supported_rate(u8* SupportedRates, uint mode) ; ++ ++unsigned char *rtw_get_wpa_ie(unsigned char *pie, int *wpa_ie_len, int limit); ++unsigned char *rtw_get_wpa2_ie(unsigned char *pie, int *rsn_ie_len, int limit); ++int rtw_get_wpa_cipher_suite(u8 *s); ++int rtw_get_wpa2_cipher_suite(u8 *s); ++int rtw_parse_wpa_ie(u8* wpa_ie, int wpa_ie_len, int *group_cipher, int *pairwise_cipher); ++int rtw_parse_wpa2_ie(u8* wpa_ie, int wpa_ie_len, int *group_cipher, int *pairwise_cipher); ++ ++int rtw_get_sec_ie(u8 *in_ie,uint in_len,u8 *rsn_ie,u16 *rsn_len,u8 *wpa_ie,u16 *wpa_len); ++ ++u8 rtw_is_wps_ie(u8 *ie_ptr, uint *wps_ielen); ++u8 *rtw_get_wps_ie(u8 *in_ie, uint in_len, u8 *wps_ie, uint *wps_ielen); ++u8 *rtw_get_wps_attr(u8 *wps_ie, uint wps_ielen, u16 target_attr_id ,u8 *buf_attr, u32 *len_attr); ++u8 *rtw_get_wps_attr_content(u8 *wps_ie, uint wps_ielen, u16 target_attr_id ,u8 *buf_content, uint *len_content); ++ ++u8 *rtw_get_p2p_ie(u8 *in_ie, uint in_len, u8 *p2p_ie, uint *p2p_ielen); ++u8 *rtw_get_p2p_attr(u8 *p2p_ie, uint p2p_ielen, u8 target_attr_id ,u8 *buf_attr, u32 *len_attr); ++u8 *rtw_get_p2p_attr_content(u8 *p2p_ie, uint p2p_ielen, u8 target_attr_id ,u8 *buf_content, uint *len_content); ++u32 rtw_set_p2p_attr_content(u8 *pbuf, u8 attr_id, u16 attr_len, u8 *pdata_attr); ++ ++void dump_ies(u8 *buf, u32 buf_len); ++void dump_wps_ie(u8 *ie, u32 ie_len); ++#ifdef CONFIG_P2P ++void dump_p2p_ie(u8 *ie, u32 ie_len); ++void rtw_WLAN_BSSID_EX_remove_p2p_attr(WLAN_BSSID_EX *bss_ex, u8 attr_id); ++#endif ++#ifdef CONFIG_WFD ++int rtw_get_wfd_ie(u8 *in_ie, uint in_len, u8 *wfd_ie, uint *wfd_ielen); ++int rtw_get_wfd_attr_content(u8 *wfd_ie, uint wfd_ielen, u8 target_attr_id ,u8 *attr_content, uint *attr_contentlen); ++#endif // CONFIG_WFD ++ ++uint rtw_get_rateset_len(u8 *rateset); ++ ++struct registry_priv; ++int rtw_generate_ie(struct registry_priv *pregistrypriv); ++ ++ ++int rtw_get_bit_value_from_ieee_value(u8 val); ++ ++uint rtw_is_cckrates_included(u8 *rate); ++ ++uint rtw_is_cckratesonly_included(u8 *rate); ++ ++int rtw_check_network_type(unsigned char *rate, int ratelen, int channel); ++ ++void rtw_macaddr_cfg(u8 *mac_addr); ++#endif /* IEEE80211_H */ ++ +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/include/ieee80211_ext.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/include/ieee80211_ext.h 2013-07-26 19:36:06.000000000 +0000 +@@ -0,0 +1,477 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef __IEEE80211_EXT_H ++#define __IEEE80211_EXT_H ++ ++#include ++#include ++#include ++ ++#define WMM_OUI_TYPE 2 ++#define WMM_OUI_SUBTYPE_INFORMATION_ELEMENT 0 ++#define WMM_OUI_SUBTYPE_PARAMETER_ELEMENT 1 ++#define WMM_OUI_SUBTYPE_TSPEC_ELEMENT 2 ++#define WMM_VERSION 1 ++ ++#define WPA_PROTO_WPA BIT(0) ++#define WPA_PROTO_RSN BIT(1) ++ ++#define WPA_KEY_MGMT_IEEE8021X BIT(0) ++#define WPA_KEY_MGMT_PSK BIT(1) ++#define WPA_KEY_MGMT_NONE BIT(2) ++#define WPA_KEY_MGMT_IEEE8021X_NO_WPA BIT(3) ++#define WPA_KEY_MGMT_WPA_NONE BIT(4) ++ ++ ++#define WPA_CAPABILITY_PREAUTH BIT(0) ++#define WPA_CAPABILITY_MGMT_FRAME_PROTECTION BIT(6) ++#define WPA_CAPABILITY_PEERKEY_ENABLED BIT(9) ++ ++ ++#define PMKID_LEN 16 ++ ++ ++#ifdef PLATFORM_LINUX ++struct wpa_ie_hdr { ++ u8 elem_id; ++ u8 len; ++ u8 oui[4]; /* 24-bit OUI followed by 8-bit OUI type */ ++ u8 version[2]; /* little endian */ ++}__attribute__ ((packed)); ++ ++struct rsn_ie_hdr { ++ u8 elem_id; /* WLAN_EID_RSN */ ++ u8 len; ++ u8 version[2]; /* little endian */ ++}__attribute__ ((packed)); ++ ++struct wme_ac_parameter { ++#if defined(CONFIG_LITTLE_ENDIAN) ++ /* byte 1 */ ++ u8 aifsn:4, ++ acm:1, ++ aci:2, ++ reserved:1; ++ ++ /* byte 2 */ ++ u8 eCWmin:4, ++ eCWmax:4; ++#elif defined(CONFIG_BIG_ENDIAN) ++ /* byte 1 */ ++ u8 reserved:1, ++ aci:2, ++ acm:1, ++ aifsn:4; ++ ++ /* byte 2 */ ++ u8 eCWmax:4, ++ eCWmin:4; ++#else ++#error "Please fix " ++#endif ++ ++ /* bytes 3 & 4 */ ++ u16 txopLimit; ++} __attribute__ ((packed)); ++ ++struct wme_parameter_element { ++ /* required fields for WME version 1 */ ++ u8 oui[3]; ++ u8 oui_type; ++ u8 oui_subtype; ++ u8 version; ++ u8 acInfo; ++ u8 reserved; ++ struct wme_ac_parameter ac[4]; ++ ++} __attribute__ ((packed)); ++ ++#endif ++ ++#ifdef PLATFORM_WINDOWS ++ ++#pragma pack(1) ++ ++struct wpa_ie_hdr { ++ u8 elem_id; ++ u8 len; ++ u8 oui[4]; /* 24-bit OUI followed by 8-bit OUI type */ ++ u8 version[2]; /* little endian */ ++}; ++ ++struct rsn_ie_hdr { ++ u8 elem_id; /* WLAN_EID_RSN */ ++ u8 len; ++ u8 version[2]; /* little endian */ ++}; ++ ++#pragma pack() ++ ++#endif ++ ++#define WPA_PUT_LE16(a, val) \ ++ do { \ ++ (a)[1] = ((u16) (val)) >> 8; \ ++ (a)[0] = ((u16) (val)) & 0xff; \ ++ } while (0) ++ ++#define WPA_PUT_BE32(a, val) \ ++ do { \ ++ (a)[0] = (u8) ((((u32) (val)) >> 24) & 0xff); \ ++ (a)[1] = (u8) ((((u32) (val)) >> 16) & 0xff); \ ++ (a)[2] = (u8) ((((u32) (val)) >> 8) & 0xff); \ ++ (a)[3] = (u8) (((u32) (val)) & 0xff); \ ++ } while (0) ++ ++#define WPA_PUT_LE32(a, val) \ ++ do { \ ++ (a)[3] = (u8) ((((u32) (val)) >> 24) & 0xff); \ ++ (a)[2] = (u8) ((((u32) (val)) >> 16) & 0xff); \ ++ (a)[1] = (u8) ((((u32) (val)) >> 8) & 0xff); \ ++ (a)[0] = (u8) (((u32) (val)) & 0xff); \ ++ } while (0) ++ ++#define RSN_SELECTOR_PUT(a, val) WPA_PUT_BE32((u8 *) (a), (val)) ++//#define RSN_SELECTOR_PUT(a, val) WPA_PUT_LE32((u8 *) (a), (val)) ++ ++ ++ ++/* Action category code */ ++enum ieee80211_category { ++ WLAN_CATEGORY_SPECTRUM_MGMT = 0, ++ WLAN_CATEGORY_QOS = 1, ++ WLAN_CATEGORY_DLS = 2, ++ WLAN_CATEGORY_BACK = 3, ++ WLAN_CATEGORY_HT = 7, ++ WLAN_CATEGORY_WMM = 17, ++}; ++ ++/* SPECTRUM_MGMT action code */ ++enum ieee80211_spectrum_mgmt_actioncode { ++ WLAN_ACTION_SPCT_MSR_REQ = 0, ++ WLAN_ACTION_SPCT_MSR_RPRT = 1, ++ WLAN_ACTION_SPCT_TPC_REQ = 2, ++ WLAN_ACTION_SPCT_TPC_RPRT = 3, ++ WLAN_ACTION_SPCT_CHL_SWITCH = 4, ++ WLAN_ACTION_SPCT_EXT_CHL_SWITCH = 5, ++}; ++ ++/* BACK action code */ ++enum ieee80211_back_actioncode { ++ WLAN_ACTION_ADDBA_REQ = 0, ++ WLAN_ACTION_ADDBA_RESP = 1, ++ WLAN_ACTION_DELBA = 2, ++}; ++ ++/* HT features action code */ ++enum ieee80211_ht_actioncode { ++ WLAN_ACTION_NOTIFY_CH_WIDTH = 0, ++ WLAN_ACTION_SM_PS = 1, ++ WLAN_ACTION_PSPM = 2, ++ WLAN_ACTION_PCO_PHASE = 3, ++ WLAN_ACTION_MIMO_CSI_MX = 4, ++ WLAN_ACTION_MIMO_NONCP_BF = 5, ++ WLAN_ACTION_MIMP_CP_BF = 6, ++ WLAN_ACTION_ASEL_INDICATES_FB = 7, ++ WLAN_ACTION_HI_INFO_EXCHG = 8, ++}; ++ ++/* BACK (block-ack) parties */ ++enum ieee80211_back_parties { ++ WLAN_BACK_RECIPIENT = 0, ++ WLAN_BACK_INITIATOR = 1, ++ WLAN_BACK_TIMER = 2, ++}; ++ ++#ifdef PLATFORM_LINUX ++ ++struct ieee80211_mgmt { ++ u16 frame_control; ++ u16 duration; ++ u8 da[6]; ++ u8 sa[6]; ++ u8 bssid[6]; ++ u16 seq_ctrl; ++ union { ++ struct { ++ u16 auth_alg; ++ u16 auth_transaction; ++ u16 status_code; ++ /* possibly followed by Challenge text */ ++ u8 variable[0]; ++ } __attribute__ ((packed)) auth; ++ struct { ++ u16 reason_code; ++ } __attribute__ ((packed)) deauth; ++ struct { ++ u16 capab_info; ++ u16 listen_interval; ++ /* followed by SSID and Supported rates */ ++ u8 variable[0]; ++ } __attribute__ ((packed)) assoc_req; ++ struct { ++ u16 capab_info; ++ u16 status_code; ++ u16 aid; ++ /* followed by Supported rates */ ++ u8 variable[0]; ++ } __attribute__ ((packed)) assoc_resp, reassoc_resp; ++ struct { ++ u16 capab_info; ++ u16 listen_interval; ++ u8 current_ap[6]; ++ /* followed by SSID and Supported rates */ ++ u8 variable[0]; ++ } __attribute__ ((packed)) reassoc_req; ++ struct { ++ u16 reason_code; ++ } __attribute__ ((packed)) disassoc; ++ struct { ++ __le64 timestamp; ++ u16 beacon_int; ++ u16 capab_info; ++ /* followed by some of SSID, Supported rates, ++ * FH Params, DS Params, CF Params, IBSS Params, TIM */ ++ u8 variable[0]; ++ } __attribute__ ((packed)) beacon; ++ struct { ++ /* only variable items: SSID, Supported rates */ ++ u8 variable[0]; ++ } __attribute__ ((packed)) probe_req; ++ struct { ++ __le64 timestamp; ++ u16 beacon_int; ++ u16 capab_info; ++ /* followed by some of SSID, Supported rates, ++ * FH Params, DS Params, CF Params, IBSS Params */ ++ u8 variable[0]; ++ } __attribute__ ((packed)) probe_resp; ++ struct { ++ u8 category; ++ union { ++ struct { ++ u8 action_code; ++ u8 dialog_token; ++ u8 status_code; ++ u8 variable[0]; ++ } __attribute__ ((packed)) wme_action; ++#if 0 ++ struct{ ++ u8 action_code; ++ u8 element_id; ++ u8 length; ++ struct ieee80211_channel_sw_ie sw_elem; ++ } __attribute__ ((packed)) chan_switch; ++ struct{ ++ u8 action_code; ++ u8 dialog_token; ++ u8 element_id; ++ u8 length; ++ struct ieee80211_msrment_ie msr_elem; ++ } __attribute__ ((packed)) measurement; ++#endif ++ struct{ ++ u8 action_code; ++ u8 dialog_token; ++ u16 capab; ++ u16 timeout; ++ u16 start_seq_num; ++ } __attribute__ ((packed)) addba_req; ++ struct{ ++ u8 action_code; ++ u8 dialog_token; ++ u16 status; ++ u16 capab; ++ u16 timeout; ++ } __attribute__ ((packed)) addba_resp; ++ struct{ ++ u8 action_code; ++ u16 params; ++ u16 reason_code; ++ } __attribute__ ((packed)) delba; ++ struct{ ++ u8 action_code; ++ /* capab_info for open and confirm, ++ * reason for close ++ */ ++ u16 aux; ++ /* Followed in plink_confirm by status ++ * code, AID and supported rates, ++ * and directly by supported rates in ++ * plink_open and plink_close ++ */ ++ u8 variable[0]; ++ } __attribute__ ((packed)) plink_action; ++ struct{ ++ u8 action_code; ++ u8 variable[0]; ++ } __attribute__ ((packed)) mesh_action; ++ } __attribute__ ((packed)) u; ++ } __attribute__ ((packed)) action; ++ } __attribute__ ((packed)) u; ++}__attribute__ ((packed)); ++ ++#endif ++ ++ ++#ifdef PLATFORM_WINDOWS ++ ++#pragma pack(1) ++ ++struct ieee80211_mgmt { ++ u16 frame_control; ++ u16 duration; ++ u8 da[6]; ++ u8 sa[6]; ++ u8 bssid[6]; ++ u16 seq_ctrl; ++ union { ++ struct { ++ u16 auth_alg; ++ u16 auth_transaction; ++ u16 status_code; ++ /* possibly followed by Challenge text */ ++ u8 variable[0]; ++ } auth; ++ struct { ++ u16 reason_code; ++ } deauth; ++ struct { ++ u16 capab_info; ++ u16 listen_interval; ++ /* followed by SSID and Supported rates */ ++ u8 variable[0]; ++ } assoc_req; ++ struct { ++ u16 capab_info; ++ u16 status_code; ++ u16 aid; ++ /* followed by Supported rates */ ++ u8 variable[0]; ++ } assoc_resp, reassoc_resp; ++ struct { ++ u16 capab_info; ++ u16 listen_interval; ++ u8 current_ap[6]; ++ /* followed by SSID and Supported rates */ ++ u8 variable[0]; ++ } reassoc_req; ++ struct { ++ u16 reason_code; ++ } disassoc; ++#if 0 ++ struct { ++ __le64 timestamp; ++ u16 beacon_int; ++ u16 capab_info; ++ /* followed by some of SSID, Supported rates, ++ * FH Params, DS Params, CF Params, IBSS Params, TIM */ ++ u8 variable[0]; ++ } beacon; ++ struct { ++ /* only variable items: SSID, Supported rates */ ++ u8 variable[0]; ++ } probe_req; ++ ++ struct { ++ __le64 timestamp; ++ u16 beacon_int; ++ u16 capab_info; ++ /* followed by some of SSID, Supported rates, ++ * FH Params, DS Params, CF Params, IBSS Params */ ++ u8 variable[0]; ++ } probe_resp; ++#endif ++ struct { ++ u8 category; ++ union { ++ struct { ++ u8 action_code; ++ u8 dialog_token; ++ u8 status_code; ++ u8 variable[0]; ++ } wme_action; ++/* ++ struct{ ++ u8 action_code; ++ u8 element_id; ++ u8 length; ++ struct ieee80211_channel_sw_ie sw_elem; ++ } chan_switch; ++ struct{ ++ u8 action_code; ++ u8 dialog_token; ++ u8 element_id; ++ u8 length; ++ struct ieee80211_msrment_ie msr_elem; ++ } measurement; ++*/ ++ struct{ ++ u8 action_code; ++ u8 dialog_token; ++ u16 capab; ++ u16 timeout; ++ u16 start_seq_num; ++ } addba_req; ++ struct{ ++ u8 action_code; ++ u8 dialog_token; ++ u16 status; ++ u16 capab; ++ u16 timeout; ++ } addba_resp; ++ struct{ ++ u8 action_code; ++ u16 params; ++ u16 reason_code; ++ } delba; ++ struct{ ++ u8 action_code; ++ /* capab_info for open and confirm, ++ * reason for close ++ */ ++ u16 aux; ++ /* Followed in plink_confirm by status ++ * code, AID and supported rates, ++ * and directly by supported rates in ++ * plink_open and plink_close ++ */ ++ u8 variable[0]; ++ } plink_action; ++ struct{ ++ u8 action_code; ++ u8 variable[0]; ++ } mesh_action; ++ } u; ++ } action; ++ } u; ++} ; ++ ++#pragma pack() ++ ++#endif ++ ++/* mgmt header + 1 byte category code */ ++#define IEEE80211_MIN_ACTION_SIZE FIELD_OFFSET(struct ieee80211_mgmt, u.action.u) ++ ++ ++ ++#endif ++ +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/include/if_ether.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/include/if_ether.h 2013-07-26 19:36:06.000000000 +0000 +@@ -0,0 +1,112 @@ ++/* ++ * INET An implementation of the TCP/IP protocol suite for the LINUX ++ * operating system. INET is implemented using the BSD Socket ++ * interface as the means of communication with the user level. ++ * ++ * Global definitions for the Ethernet IEEE 802.3 interface. ++ * ++ * Version: @(#)if_ether.h 1.0.1a 02/08/94 ++ * ++ * Author: Fred N. van Kempen, ++ * Donald Becker, ++ * Alan Cox, ++ * Steve Whitehouse, ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * as published by the Free Software Foundation; either version ++ * 2 of the License, or (at your option) any later version. ++ */ ++ ++#ifndef _LINUX_IF_ETHER_H ++#define _LINUX_IF_ETHER_H ++ ++/* ++ * IEEE 802.3 Ethernet magic constants. The frame sizes omit the preamble ++ * and FCS/CRC (frame check sequence). ++ */ ++ ++#define ETH_ALEN 6 /* Octets in one ethernet addr */ ++#define ETH_HLEN 14 /* Total octets in header. */ ++#define ETH_ZLEN 60 /* Min. octets in frame sans FCS */ ++#define ETH_DATA_LEN 1500 /* Max. octets in payload */ ++#define ETH_FRAME_LEN 1514 /* Max. octets in frame sans FCS */ ++ ++/* ++ * These are the defined Ethernet Protocol ID's. ++ */ ++ ++#define ETH_P_LOOP 0x0060 /* Ethernet Loopback packet */ ++#define ETH_P_PUP 0x0200 /* Xerox PUP packet */ ++#define ETH_P_PUPAT 0x0201 /* Xerox PUP Addr Trans packet */ ++#define ETH_P_IP 0x0800 /* Internet Protocol packet */ ++#define ETH_P_X25 0x0805 /* CCITT X.25 */ ++#define ETH_P_ARP 0x0806 /* Address Resolution packet */ ++#define ETH_P_BPQ 0x08FF /* G8BPQ AX.25 Ethernet Packet [ NOT AN OFFICIALLY REGISTERED ID ] */ ++#define ETH_P_IEEEPUP 0x0a00 /* Xerox IEEE802.3 PUP packet */ ++#define ETH_P_IEEEPUPAT 0x0a01 /* Xerox IEEE802.3 PUP Addr Trans packet */ ++#define ETH_P_DEC 0x6000 /* DEC Assigned proto */ ++#define ETH_P_DNA_DL 0x6001 /* DEC DNA Dump/Load */ ++#define ETH_P_DNA_RC 0x6002 /* DEC DNA Remote Console */ ++#define ETH_P_DNA_RT 0x6003 /* DEC DNA Routing */ ++#define ETH_P_LAT 0x6004 /* DEC LAT */ ++#define ETH_P_DIAG 0x6005 /* DEC Diagnostics */ ++#define ETH_P_CUST 0x6006 /* DEC Customer use */ ++#define ETH_P_SCA 0x6007 /* DEC Systems Comms Arch */ ++#define ETH_P_RARP 0x8035 /* Reverse Addr Res packet */ ++#define ETH_P_ATALK 0x809B /* Appletalk DDP */ ++#define ETH_P_AARP 0x80F3 /* Appletalk AARP */ ++#define ETH_P_8021Q 0x8100 /* 802.1Q VLAN Extended Header */ ++#define ETH_P_IPX 0x8137 /* IPX over DIX */ ++#define ETH_P_IPV6 0x86DD /* IPv6 over bluebook */ ++#define ETH_P_PPP_DISC 0x8863 /* PPPoE discovery messages */ ++#define ETH_P_PPP_SES 0x8864 /* PPPoE session messages */ ++#define ETH_P_ATMMPOA 0x884c /* MultiProtocol Over ATM */ ++#define ETH_P_ATMFATE 0x8884 /* Frame-based ATM Transport ++ * over Ethernet ++ */ ++ ++/* ++ * Non DIX types. Won't clash for 1500 types. ++ */ ++ ++#define ETH_P_802_3 0x0001 /* Dummy type for 802.3 frames */ ++#define ETH_P_AX25 0x0002 /* Dummy protocol id for AX.25 */ ++#define ETH_P_ALL 0x0003 /* Every packet (be careful!!!) */ ++#define ETH_P_802_2 0x0004 /* 802.2 frames */ ++#define ETH_P_SNAP 0x0005 /* Internal only */ ++#define ETH_P_DDCMP 0x0006 /* DEC DDCMP: Internal only */ ++#define ETH_P_WAN_PPP 0x0007 /* Dummy type for WAN PPP frames*/ ++#define ETH_P_PPP_MP 0x0008 /* Dummy type for PPP MP frames */ ++#define ETH_P_LOCALTALK 0x0009 /* Localtalk pseudo type */ ++#define ETH_P_PPPTALK 0x0010 /* Dummy type for Atalk over PPP*/ ++#define ETH_P_TR_802_2 0x0011 /* 802.2 frames */ ++#define ETH_P_MOBITEX 0x0015 /* Mobitex (kaz@cafe.net) */ ++#define ETH_P_CONTROL 0x0016 /* Card specific control frames */ ++#define ETH_P_IRDA 0x0017 /* Linux-IrDA */ ++#define ETH_P_ECONET 0x0018 /* Acorn Econet */ ++ ++/* ++ * This is an Ethernet frame header. ++ */ ++ ++struct ethhdr ++{ ++ unsigned char h_dest[ETH_ALEN]; /* destination eth addr */ ++ unsigned char h_source[ETH_ALEN]; /* source ether addr */ ++ unsigned short h_proto; /* packet type ID field */ ++}; ++ ++struct _vlan { ++ unsigned short h_vlan_TCI; // Encapsulates priority and VLAN ID ++ unsigned short h_vlan_encapsulated_proto; ++}; ++ ++ ++ ++#define get_vlan_id(pvlan) ((ntohs((unsigned short )pvlan->h_vlan_TCI)) & 0xfff) ++#define get_vlan_priority(pvlan) ((ntohs((unsigned short )pvlan->h_vlan_TCI))>>13) ++#define get_vlan_encap_proto(pvlan) (ntohs((unsigned short )pvlan->h_vlan_encapsulated_proto)) ++ ++ ++#endif /* _LINUX_IF_ETHER_H */ +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/include/ioctl_cfg80211.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/include/ioctl_cfg80211.h 2013-07-26 19:36:06.000000000 +0000 +@@ -0,0 +1,81 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef __IOCTL_CFG80211_H__ ++#define __IOCTL_CFG80211_H__ ++ ++#if defined(CONFIG_IOCTL_CFG80211) && !defined(CONFIG_CFG80211) && !defined(CONFIG_CFG80211_MODULE) ++ #error "Can't define CONFIG_IOCTL_CFG80211 because neither CONFIG_CFG80211 nor CONFIG_CFG80211_MODULE is defined in kernel" ++#endif ++#if defined(CONFIG_IOCTL_CFG80211) && LINUX_VERSION_CODE < KERNEL_VERSION(2,6,35) ++ #error "We haven't verify our cfg80211 solution below kernel version 2.6.35" ++#endif ++ ++struct rtw_wdev_priv ++{ ++ struct wireless_dev *rtw_wdev; ++ ++ _adapter *padapter; ++ ++ struct cfg80211_scan_request *scan_request; ++ _lock scan_req_lock; ++ ++ struct net_device *pmon_ndev;//for monitor interface ++ char ifname_mon[IFNAMSIZ + 1]; //interface name for monitor interface ++ ++ u8 p2p_enabled; ++ ++ u8 provdisc_req_issued; ++ ++ bool block; ++ ++}; ++ ++#define wdev_to_priv(w) ((struct rtw_wdev_priv *)(wdev_priv(w))) ++ ++#define wiphy_to_adapter(x) (_adapter *)(((struct rtw_wdev_priv*)wiphy_priv(x))->padapter) ++ ++#define wiphy_to_wdev(x) (struct wireless_dev *)(((struct rtw_wdev_priv*)wiphy_priv(x))->rtw_wdev) ++ ++ ++ ++int rtw_wdev_alloc(_adapter *padapter, struct device *dev); ++void rtw_wdev_free(struct wireless_dev *wdev); ++ ++void rtw_cfg80211_init_wiphy(_adapter *padapter); ++ ++void rtw_cfg80211_surveydone_event_callback(_adapter *padapter); ++ ++void rtw_cfg80211_indicate_connect(_adapter *padapter); ++void rtw_cfg80211_indicate_disconnect(_adapter *padapter); ++void rtw_cfg80211_indicate_scan_done(struct rtw_wdev_priv *pwdev_priv, bool aborted); ++ ++#ifdef CONFIG_AP_MODE ++void rtw_cfg80211_indicate_sta_assoc(_adapter *padapter, u8 *pmgmt_frame, uint frame_len); ++void rtw_cfg80211_indicate_sta_disassoc(_adapter *padapter, unsigned char *da, unsigned short reason); ++#endif //CONFIG_AP_MODE ++ ++void rtw_cfg80211_issue_p2p_provision_request(_adapter *padapter, const u8 *buf, size_t len); ++void rtw_cfg80211_rx_p2p_action_public(_adapter *padapter, u8 *pmgmt_frame, uint frame_len); ++void rtw_cfg80211_rx_action_p2p(_adapter *padapter, u8 *pmgmt_frame, uint frame_len); ++ ++int rtw_cfg80211_set_mgnt_wpsp2pie(struct net_device *net, char *buf, int len, int type); ++ ++#endif //__IOCTL_CFG80211_H__ ++ +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/include/ip.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/include/ip.h 2013-07-26 19:36:06.000000000 +0000 +@@ -0,0 +1,138 @@ ++/* ++ * INET An implementation of the TCP/IP protocol suite for the LINUX ++ * operating system. INET is implemented using the BSD Socket ++ * interface as the means of communication with the user level. ++ * ++ * Definitions for the IP protocol. ++ * ++ * Version: @(#)ip.h 1.0.2 04/28/93 ++ * ++ * Authors: Fred N. van Kempen, ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License ++ * as published by the Free Software Foundation; either version ++ * 2 of the License, or (at your option) any later version. ++ */ ++#ifndef _LINUX_IP_H ++#define _LINUX_IP_H ++#include ++ ++/* SOL_IP socket options */ ++ ++#define IPTOS_TOS_MASK 0x1E ++#define IPTOS_TOS(tos) ((tos)&IPTOS_TOS_MASK) ++#define IPTOS_LOWDELAY 0x10 ++#define IPTOS_THROUGHPUT 0x08 ++#define IPTOS_RELIABILITY 0x04 ++#define IPTOS_MINCOST 0x02 ++ ++#define IPTOS_PREC_MASK 0xE0 ++#define IPTOS_PREC(tos) ((tos)&IPTOS_PREC_MASK) ++#define IPTOS_PREC_NETCONTROL 0xe0 ++#define IPTOS_PREC_INTERNETCONTROL 0xc0 ++#define IPTOS_PREC_CRITIC_ECP 0xa0 ++#define IPTOS_PREC_FLASHOVERRIDE 0x80 ++#define IPTOS_PREC_FLASH 0x60 ++#define IPTOS_PREC_IMMEDIATE 0x40 ++#define IPTOS_PREC_PRIORITY 0x20 ++#define IPTOS_PREC_ROUTINE 0x00 ++ ++ ++/* IP options */ ++#define IPOPT_COPY 0x80 ++#define IPOPT_CLASS_MASK 0x60 ++#define IPOPT_NUMBER_MASK 0x1f ++ ++#define IPOPT_COPIED(o) ((o)&IPOPT_COPY) ++#define IPOPT_CLASS(o) ((o)&IPOPT_CLASS_MASK) ++#define IPOPT_NUMBER(o) ((o)&IPOPT_NUMBER_MASK) ++ ++#define IPOPT_CONTROL 0x00 ++#define IPOPT_RESERVED1 0x20 ++#define IPOPT_MEASUREMENT 0x40 ++#define IPOPT_RESERVED2 0x60 ++ ++#define IPOPT_END (0 |IPOPT_CONTROL) ++#define IPOPT_NOOP (1 |IPOPT_CONTROL) ++#define IPOPT_SEC (2 |IPOPT_CONTROL|IPOPT_COPY) ++#define IPOPT_LSRR (3 |IPOPT_CONTROL|IPOPT_COPY) ++#define IPOPT_TIMESTAMP (4 |IPOPT_MEASUREMENT) ++#define IPOPT_RR (7 |IPOPT_CONTROL) ++#define IPOPT_SID (8 |IPOPT_CONTROL|IPOPT_COPY) ++#define IPOPT_SSRR (9 |IPOPT_CONTROL|IPOPT_COPY) ++#define IPOPT_RA (20|IPOPT_CONTROL|IPOPT_COPY) ++ ++#define IPVERSION 4 ++#define MAXTTL 255 ++#define IPDEFTTL 64 ++ ++/* struct timestamp, struct route and MAX_ROUTES are removed. ++ ++ REASONS: it is clear that nobody used them because: ++ - MAX_ROUTES value was wrong. ++ - "struct route" was wrong. ++ - "struct timestamp" had fatally misaligned bitfields and was completely unusable. ++ */ ++ ++#define IPOPT_OPTVAL 0 ++#define IPOPT_OLEN 1 ++#define IPOPT_OFFSET 2 ++#define IPOPT_MINOFF 4 ++#define MAX_IPOPTLEN 40 ++#define IPOPT_NOP IPOPT_NOOP ++#define IPOPT_EOL IPOPT_END ++#define IPOPT_TS IPOPT_TIMESTAMP ++ ++#define IPOPT_TS_TSONLY 0 /* timestamps only */ ++#define IPOPT_TS_TSANDADDR 1 /* timestamps and addresses */ ++#define IPOPT_TS_PRESPEC 3 /* specified modules only */ ++ ++#ifdef PLATFORM_LINUX ++ ++struct ip_options { ++ __u32 faddr; /* Saved first hop address */ ++ unsigned char optlen; ++ unsigned char srr; ++ unsigned char rr; ++ unsigned char ts; ++ unsigned char is_setbyuser:1, /* Set by setsockopt? */ ++ is_data:1, /* Options in __data, rather than skb */ ++ is_strictroute:1, /* Strict source route */ ++ srr_is_hit:1, /* Packet destination addr was our one */ ++ is_changed:1, /* IP checksum more not valid */ ++ rr_needaddr:1, /* Need to record addr of outgoing dev */ ++ ts_needtime:1, /* Need to record timestamp */ ++ ts_needaddr:1; /* Need to record addr of outgoing dev */ ++ unsigned char router_alert; ++ unsigned char __pad1; ++ unsigned char __pad2; ++ unsigned char __data[0]; ++}; ++ ++#define optlength(opt) (sizeof(struct ip_options) + opt->optlen) ++#endif ++ ++struct iphdr { ++#if defined(__LITTLE_ENDIAN_BITFIELD) ++ __u8 ihl:4, ++ version:4; ++#elif defined (__BIG_ENDIAN_BITFIELD) ++ __u8 version:4, ++ ihl:4; ++#else ++#error "Please fix " ++#endif ++ __u8 tos; ++ __u16 tot_len; ++ __u16 id; ++ __u16 frag_off; ++ __u8 ttl; ++ __u8 protocol; ++ __u16 check; ++ __u32 saddr; ++ __u32 daddr; ++ /*The options start here. */ ++}; ++ ++#endif /* _LINUX_IP_H */ +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/include/mlme_osdep.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/include/mlme_osdep.h 2013-07-26 19:36:06.000000000 +0000 +@@ -0,0 +1,44 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef __MLME_OSDEP_H_ ++#define __MLME_OSDEP_H_ ++ ++#include ++#include ++#include ++ ++#if defined(PLATFORM_WINDOWS) || defined(PLATFORM_MPIXEL) ++extern int time_after(u32 now, u32 old); ++#endif ++ ++extern void rtw_init_mlme_timer(_adapter *padapter); ++extern void rtw_os_indicate_disconnect( _adapter *adapter ); ++extern void rtw_os_indicate_connect( _adapter *adapter ); ++void rtw_os_indicate_scan_done( _adapter *padapter, bool aborted); ++extern void rtw_report_sec_ie(_adapter *adapter,u8 authmode,u8 *sec_ie); ++ ++#ifdef CONFIG_AP_MODE ++void rtw_indicate_sta_assoc_event(_adapter *padapter, struct sta_info *psta); ++void rtw_indicate_sta_disassoc_event(_adapter *padapter, struct sta_info *psta); ++#endif ++void rtw_reset_securitypriv( _adapter *adapter ); ++ ++#endif //_MLME_OSDEP_H_ ++ +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/include/mp_custom_oid.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/include/mp_custom_oid.h 2013-07-26 19:36:06.000000000 +0000 +@@ -0,0 +1,353 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef __CUSTOM_OID_H ++#define __CUSTOM_OID_H ++ ++// by Owen ++// 0xFF818000 - 0xFF81802F RTL8180 Mass Production Kit ++// 0xFF818500 - 0xFF81850F RTL8185 Setup Utility ++// 0xFF818580 - 0xFF81858F RTL8185 Phy Status Utility ++ ++// ++ ++// by Owen for Production Kit ++// For Production Kit with Agilent Equipments ++// in order to make our custom oids hopefully somewhat unique ++// we will use 0xFF (indicating implementation specific OID) ++// 81(first byte of non zero Realtek unique identifier) ++// 80 (second byte of non zero Realtek unique identifier) ++// XX (the custom OID number - providing 255 possible custom oids) ++ ++#define OID_RT_PRO_RESET_DUT 0xFF818000 ++#define OID_RT_PRO_SET_DATA_RATE 0xFF818001 ++#define OID_RT_PRO_START_TEST 0xFF818002 ++#define OID_RT_PRO_STOP_TEST 0xFF818003 ++#define OID_RT_PRO_SET_PREAMBLE 0xFF818004 ++#define OID_RT_PRO_SET_SCRAMBLER 0xFF818005 ++#define OID_RT_PRO_SET_FILTER_BB 0xFF818006 ++#define OID_RT_PRO_SET_MANUAL_DIVERSITY_BB 0xFF818007 ++#define OID_RT_PRO_SET_CHANNEL_DIRECT_CALL 0xFF818008 ++#define OID_RT_PRO_SET_SLEEP_MODE_DIRECT_CALL 0xFF818009 ++#define OID_RT_PRO_SET_WAKE_MODE_DIRECT_CALL 0xFF81800A ++ ++#define OID_RT_PRO_SET_TX_ANTENNA_BB 0xFF81800D ++#define OID_RT_PRO_SET_ANTENNA_BB 0xFF81800E ++#define OID_RT_PRO_SET_CR_SCRAMBLER 0xFF81800F ++#define OID_RT_PRO_SET_CR_NEW_FILTER 0xFF818010 ++#define OID_RT_PRO_SET_TX_POWER_CONTROL 0xFF818011 ++#define OID_RT_PRO_SET_CR_TX_CONFIG 0xFF818012 ++#define OID_RT_PRO_GET_TX_POWER_CONTROL 0xFF818013 ++#define OID_RT_PRO_GET_CR_SIGNAL_QUALITY 0xFF818014 ++#define OID_RT_PRO_SET_CR_SETPOINT 0xFF818015 ++#define OID_RT_PRO_SET_INTEGRATOR 0xFF818016 ++#define OID_RT_PRO_SET_SIGNAL_QUALITY 0xFF818017 ++#define OID_RT_PRO_GET_INTEGRATOR 0xFF818018 ++#define OID_RT_PRO_GET_SIGNAL_QUALITY 0xFF818019 ++#define OID_RT_PRO_QUERY_EEPROM_TYPE 0xFF81801A ++#define OID_RT_PRO_WRITE_MAC_ADDRESS 0xFF81801B ++#define OID_RT_PRO_READ_MAC_ADDRESS 0xFF81801C ++#define OID_RT_PRO_WRITE_CIS_DATA 0xFF81801D ++#define OID_RT_PRO_READ_CIS_DATA 0xFF81801E ++#define OID_RT_PRO_WRITE_POWER_CONTROL 0xFF81801F ++#define OID_RT_PRO_READ_POWER_CONTROL 0xFF818020 ++#define OID_RT_PRO_WRITE_EEPROM 0xFF818021 ++#define OID_RT_PRO_READ_EEPROM 0xFF818022 ++#define OID_RT_PRO_RESET_TX_PACKET_SENT 0xFF818023 ++#define OID_RT_PRO_QUERY_TX_PACKET_SENT 0xFF818024 ++#define OID_RT_PRO_RESET_RX_PACKET_RECEIVED 0xFF818025 ++#define OID_RT_PRO_QUERY_RX_PACKET_RECEIVED 0xFF818026 ++#define OID_RT_PRO_QUERY_RX_PACKET_CRC32_ERROR 0xFF818027 ++#define OID_RT_PRO_QUERY_CURRENT_ADDRESS 0xFF818028 ++#define OID_RT_PRO_QUERY_PERMANENT_ADDRESS 0xFF818029 ++#define OID_RT_PRO_SET_PHILIPS_RF_PARAMETERS 0xFF81802A ++#define OID_RT_PRO_RECEIVE_PACKET 0xFF81802C ++// added by Owen on 04/08/03 for Cameo's request ++#define OID_RT_PRO_WRITE_EEPROM_BYTE 0xFF81802D ++#define OID_RT_PRO_READ_EEPROM_BYTE 0xFF81802E ++#define OID_RT_PRO_SET_MODULATION 0xFF81802F ++// ++ ++//Sean ++#define OID_RT_DRIVER_OPTION 0xFF818080 ++#define OID_RT_RF_OFF 0xFF818081 ++#define OID_RT_AUTH_STATUS 0xFF818082 ++ ++//======================================================================== ++#define OID_RT_PRO_SET_CONTINUOUS_TX 0xFF81800B ++#define OID_RT_PRO_SET_SINGLE_CARRIER_TX 0xFF81800C ++#define OID_RT_PRO_SET_CARRIER_SUPPRESSION_TX 0xFF81802B ++#define OID_RT_PRO_SET_SINGLE_TONE_TX 0xFF818043 ++//======================================================================== ++ ++ ++// by Owen for RTL8185 Phy Status Report Utility ++#define OID_RT_UTILITY_FALSE_ALARM_COUNTERS 0xFF818580 ++#define OID_RT_UTILITY_SELECT_DEBUG_MODE 0xFF818581 ++#define OID_RT_UTILITY_SELECT_SUBCARRIER_NUMBER 0xFF818582 ++#define OID_RT_UTILITY_GET_RSSI_STATUS 0xFF818583 ++#define OID_RT_UTILITY_GET_FRAME_DETECTION_STATUS 0xFF818584 ++#define OID_RT_UTILITY_GET_AGC_AND_FREQUENCY_OFFSET_ESTIMATION_STATUS 0xFF818585 ++#define OID_RT_UTILITY_GET_CHANNEL_ESTIMATION_STATUS 0xFF818586 ++// ++ ++// by Owen on 03/09/19-03/09/22 for RTL8185 ++#define OID_RT_WIRELESS_MODE 0xFF818500 ++#define OID_RT_SUPPORTED_RATES 0xFF818501 ++#define OID_RT_DESIRED_RATES 0xFF818502 ++#define OID_RT_WIRELESS_MODE_STARTING_ADHOC 0xFF818503 ++// ++ ++#define OID_RT_GET_CONNECT_STATE 0xFF030001 ++#define OID_RT_RESCAN 0xFF030002 ++#define OID_RT_SET_KEY_LENGTH 0xFF030003 ++#define OID_RT_SET_DEFAULT_KEY_ID 0xFF030004 ++ ++#define OID_RT_SET_CHANNEL 0xFF010182 ++#define OID_RT_SET_SNIFFER_MODE 0xFF010183 ++#define OID_RT_GET_SIGNAL_QUALITY 0xFF010184 ++#define OID_RT_GET_SMALL_PACKET_CRC 0xFF010185 ++#define OID_RT_GET_MIDDLE_PACKET_CRC 0xFF010186 ++#define OID_RT_GET_LARGE_PACKET_CRC 0xFF010187 ++#define OID_RT_GET_TX_RETRY 0xFF010188 ++#define OID_RT_GET_RX_RETRY 0xFF010189 ++#define OID_RT_PRO_SET_FW_DIG_STATE 0xFF01018A//S ++#define OID_RT_PRO_SET_FW_RA_STATE 0xFF01018B//S ++ ++#define OID_RT_GET_RX_TOTAL_PACKET 0xFF010190 ++#define OID_RT_GET_TX_BEACON_OK 0xFF010191 ++#define OID_RT_GET_TX_BEACON_ERR 0xFF010192 ++#define OID_RT_GET_RX_ICV_ERR 0xFF010193 ++#define OID_RT_SET_ENCRYPTION_ALGORITHM 0xFF010194 ++#define OID_RT_SET_NO_AUTO_RESCAN 0xFF010195 ++#define OID_RT_GET_PREAMBLE_MODE 0xFF010196 ++#define OID_RT_GET_DRIVER_UP_DELTA_TIME 0xFF010197 ++#define OID_RT_GET_AP_IP 0xFF010198 ++#define OID_RT_GET_CHANNELPLAN 0xFF010199 ++#define OID_RT_SET_PREAMBLE_MODE 0xFF01019A ++#define OID_RT_SET_BCN_INTVL 0xFF01019B ++#define OID_RT_GET_RF_VENDER 0xFF01019C ++#define OID_RT_DEDICATE_PROBE 0xFF01019D ++#define OID_RT_PRO_RX_FILTER_PATTERN 0xFF01019E ++ ++#define OID_RT_GET_DCST_CURRENT_THRESHOLD 0xFF01019F ++ ++#define OID_RT_GET_CCA_ERR 0xFF0101A0 ++#define OID_RT_GET_CCA_UPGRADE_THRESHOLD 0xFF0101A1 ++#define OID_RT_GET_CCA_FALLBACK_THRESHOLD 0xFF0101A2 ++ ++#define OID_RT_GET_CCA_UPGRADE_EVALUATE_TIMES 0xFF0101A3 ++#define OID_RT_GET_CCA_FALLBACK_EVALUATE_TIMES 0xFF0101A4 ++ ++// by Owen on 03/31/03 for Cameo's request ++#define OID_RT_SET_RATE_ADAPTIVE 0xFF0101A5 ++// ++#define OID_RT_GET_DCST_EVALUATE_PERIOD 0xFF0101A5 ++#define OID_RT_GET_DCST_TIME_UNIT_INDEX 0xFF0101A6 ++#define OID_RT_GET_TOTAL_TX_BYTES 0xFF0101A7 ++#define OID_RT_GET_TOTAL_RX_BYTES 0xFF0101A8 ++#define OID_RT_CURRENT_TX_POWER_LEVEL 0xFF0101A9 ++#define OID_RT_GET_ENC_KEY_MISMATCH_COUNT 0xFF0101AA ++#define OID_RT_GET_ENC_KEY_MATCH_COUNT 0xFF0101AB ++#define OID_RT_GET_CHANNEL 0xFF0101AC ++ ++#define OID_RT_SET_CHANNELPLAN 0xFF0101AD ++#define OID_RT_GET_HARDWARE_RADIO_OFF 0xFF0101AE ++#define OID_RT_CHANNELPLAN_BY_COUNTRY 0xFF0101AF ++#define OID_RT_SCAN_AVAILABLE_BSSID 0xFF0101B0 ++#define OID_RT_GET_HARDWARE_VERSION 0xFF0101B1 ++#define OID_RT_GET_IS_ROAMING 0xFF0101B2 ++#define OID_RT_GET_IS_PRIVACY 0xFF0101B3 ++#define OID_RT_GET_KEY_MISMATCH 0xFF0101B4 ++#define OID_RT_SET_RSSI_ROAM_TRAFFIC_TH 0xFF0101B5 ++#define OID_RT_SET_RSSI_ROAM_SIGNAL_TH 0xFF0101B6 ++#define OID_RT_RESET_LOG 0xFF0101B7 ++#define OID_RT_GET_LOG 0xFF0101B8 ++#define OID_RT_SET_INDICATE_HIDDEN_AP 0xFF0101B9 ++#define OID_RT_GET_HEADER_FAIL 0xFF0101BA ++#define OID_RT_SUPPORTED_WIRELESS_MODE 0xFF0101BB ++#define OID_RT_GET_CHANNEL_LIST 0xFF0101BC ++#define OID_RT_GET_SCAN_IN_PROGRESS 0xFF0101BD ++#define OID_RT_GET_TX_INFO 0xFF0101BE ++#define OID_RT_RF_READ_WRITE_OFFSET 0xFF0101BF ++#define OID_RT_RF_READ_WRITE 0xFF0101C0 ++ ++// For Netgear request. 2005.01.13, by rcnjko. ++#define OID_RT_FORCED_DATA_RATE 0xFF0101C1 ++#define OID_RT_WIRELESS_MODE_FOR_SCAN_LIST 0xFF0101C2 ++// For Netgear request. 2005.02.17, by rcnjko. ++#define OID_RT_GET_BSS_WIRELESS_MODE 0xFF0101C3 ++// For AZ project. 2005.06.27, by rcnjko. ++#define OID_RT_SCAN_WITH_MAGIC_PACKET 0xFF0101C4 ++ ++// Vincent 8185MP ++#define OID_RT_PRO_RX_FILTER 0xFF0111C0 ++ ++//Andy TEST ++//#define OID_RT_PRO_WRITE_REGISTRY 0xFF0111C1 ++//#define OID_RT_PRO_READ_REGISTRY 0xFF0111C2 ++#define OID_CE_USB_WRITE_REGISTRY 0xFF0111C1 ++#define OID_CE_USB_READ_REGISTRY 0xFF0111C2 ++ ++ ++#define OID_RT_PRO_SET_INITIAL_GAIN 0xFF0111C3 ++#define OID_RT_PRO_SET_BB_RF_STANDBY_MODE 0xFF0111C4 ++#define OID_RT_PRO_SET_BB_RF_SHUTDOWN_MODE 0xFF0111C5 ++#define OID_RT_PRO_SET_TX_CHARGE_PUMP 0xFF0111C6 ++#define OID_RT_PRO_SET_RX_CHARGE_PUMP 0xFF0111C7 ++#define OID_RT_PRO_RF_WRITE_REGISTRY 0xFF0111C8 ++#define OID_RT_PRO_RF_READ_REGISTRY 0xFF0111C9 ++#define OID_RT_PRO_QUERY_RF_TYPE 0xFF0111CA ++ ++// AP OID ++#define OID_RT_AP_GET_ASSOCIATED_STATION_LIST 0xFF010300 ++#define OID_RT_AP_GET_CURRENT_TIME_STAMP 0xFF010301 ++#define OID_RT_AP_SWITCH_INTO_AP_MODE 0xFF010302 ++#define OID_RT_AP_SET_DTIM_PERIOD 0xFF010303 ++#define OID_RT_AP_SUPPORTED 0xFF010304 // Determine if driver supports AP mode. 2004.08.27, by rcnjko. ++#define OID_RT_AP_SET_PASSPHRASE 0xFF010305 // Set WPA-PSK passphrase into authenticator. 2005.07.08, byrcnjko. ++ ++// 8187MP. 2004.09.06, by rcnjko. ++#define OID_RT_PRO8187_WI_POLL 0xFF818780 ++#define OID_RT_PRO_WRITE_BB_REG 0xFF818781 ++#define OID_RT_PRO_READ_BB_REG 0xFF818782 ++#define OID_RT_PRO_WRITE_RF_REG 0xFF818783 ++#define OID_RT_PRO_READ_RF_REG 0xFF818784 ++ ++// Meeting House. added by Annie, 2005-07-20. ++#define OID_RT_MH_VENDER_ID 0xFFEDC100 ++ ++//8711 MP OID added 20051230. ++#define OID_RT_PRO8711_JOIN_BSS 0xFF871100//S ++ ++#define OID_RT_PRO_READ_REGISTER 0xFF871101 //Q ++#define OID_RT_PRO_WRITE_REGISTER 0xFF871102 //S ++ ++#define OID_RT_PRO_BURST_READ_REGISTER 0xFF871103 //Q ++#define OID_RT_PRO_BURST_WRITE_REGISTER 0xFF871104 //S ++ ++#define OID_RT_PRO_WRITE_TXCMD 0xFF871105 //S ++ ++#define OID_RT_PRO_READ16_EEPROM 0xFF871106 //Q ++#define OID_RT_PRO_WRITE16_EEPROM 0xFF871107 //S ++ ++#define OID_RT_PRO_H2C_SET_COMMAND 0xFF871108 //S ++#define OID_RT_PRO_H2C_QUERY_RESULT 0xFF871109 //Q ++ ++#define OID_RT_PRO8711_WI_POLL 0xFF87110A //Q ++#define OID_RT_PRO8711_PKT_LOSS 0xFF87110B //Q ++#define OID_RT_RD_ATTRIB_MEM 0xFF87110C//Q ++#define OID_RT_WR_ATTRIB_MEM 0xFF87110D//S ++ ++ ++//Method 2 for H2C/C2H ++#define OID_RT_PRO_H2C_CMD_MODE 0xFF871110 //S ++#define OID_RT_PRO_H2C_CMD_RSP_MODE 0xFF871111 //Q ++#define OID_RT_PRO_H2C_CMD_EVENT_MODE 0xFF871112 //S ++#define OID_RT_PRO_WAIT_C2H_EVENT 0xFF871113 //Q ++#define OID_RT_PRO_RW_ACCESS_PROTOCOL_TEST 0xFF871114//Q ++ ++#define OID_RT_PRO_SCSI_ACCESS_TEST 0xFF871115 //Q, S ++ ++#define OID_RT_PRO_SCSI_TCPIPOFFLOAD_OUT 0xFF871116 //S ++#define OID_RT_PRO_SCSI_TCPIPOFFLOAD_IN 0xFF871117 //Q,S ++#define OID_RT_RRO_RX_PKT_VIA_IOCTRL 0xFF871118 //Q ++#define OID_RT_RRO_RX_PKTARRAY_VIA_IOCTRL 0xFF871119 //Q ++ ++#define OID_RT_RPO_SET_PWRMGT_TEST 0xFF87111A //S ++#define OID_RT_PRO_QRY_PWRMGT_TEST 0XFF87111B //Q ++#define OID_RT_RPO_ASYNC_RWIO_TEST 0xFF87111C //S ++#define OID_RT_RPO_ASYNC_RWIO_POLL 0xFF87111D //Q ++#define OID_RT_PRO_SET_RF_INTFS 0xFF87111E //S ++#define OID_RT_POLL_RX_STATUS 0xFF87111F //Q ++ ++#define OID_RT_PRO_CFG_DEBUG_MESSAGE 0xFF871120 //Q,S ++#define OID_RT_PRO_SET_DATA_RATE_EX 0xFF871121//S ++#define OID_RT_PRO_SET_BASIC_RATE 0xFF871122//S ++#define OID_RT_PRO_READ_TSSI 0xFF871123//S ++#define OID_RT_PRO_SET_POWER_TRACKING 0xFF871124//S ++ ++ ++#define OID_RT_PRO_QRY_PWRSTATE 0xFF871150 //Q ++#define OID_RT_PRO_SET_PWRSTATE 0xFF871151 //S ++ ++//Method 2 , using workitem ++#define OID_RT_SET_READ_REG 0xFF871181 //S ++#define OID_RT_SET_WRITE_REG 0xFF871182 //S ++#define OID_RT_SET_BURST_READ_REG 0xFF871183 //S ++#define OID_RT_SET_BURST_WRITE_REG 0xFF871184 //S ++#define OID_RT_SET_WRITE_TXCMD 0xFF871185 //S ++#define OID_RT_SET_READ16_EEPROM 0xFF871186 //S ++#define OID_RT_SET_WRITE16_EEPROM 0xFF871187 //S ++#define OID_RT_QRY_POLL_WKITEM 0xFF871188 //Q ++ ++//For SDIO INTERFACE only ++#define OID_RT_PRO_SYNCPAGERW_SRAM 0xFF8711A0 //Q, S ++#define OID_RT_PRO_871X_DRV_EXT 0xFF8711A1 ++ ++//For USB INTERFACE only ++#define OID_RT_PRO_USB_VENDOR_REQ 0xFF8711B0 //Q, S ++#define OID_RT_PRO_SCSI_AUTO_TEST 0xFF8711B1 //S ++#define OID_RT_PRO_USB_MAC_AC_FIFO_WRITE 0xFF8711B2 //S ++#define OID_RT_PRO_USB_MAC_RX_FIFO_READ 0xFF8711B3 //Q ++#define OID_RT_PRO_USB_MAC_RX_FIFO_POLLING 0xFF8711B4 //Q ++ ++#define OID_RT_PRO_H2C_SET_RATE_TABLE 0xFF8711FB //S ++#define OID_RT_PRO_H2C_GET_RATE_TABLE 0xFF8711FC //S ++#define OID_RT_PRO_H2C_C2H_LBK_TEST 0xFF8711FE ++ ++#define OID_RT_PRO_ENCRYPTION_CTRL 0xFF871200 //Q, S ++#define OID_RT_PRO_ADD_STA_INFO 0xFF871201 //S ++#define OID_RT_PRO_DELE_STA_INFO 0xFF871202 //S ++#define OID_RT_PRO_QUERY_DR_VARIABLE 0xFF871203 //Q ++ ++#define OID_RT_PRO_RX_PACKET_TYPE 0xFF871204 //Q, S ++ ++#define OID_RT_PRO_READ_EFUSE 0xFF871205 //Q ++#define OID_RT_PRO_WRITE_EFUSE 0xFF871206 //S ++#define OID_RT_PRO_RW_EFUSE_PGPKT 0xFF871207 //Q, S ++#define OID_RT_GET_EFUSE_CURRENT_SIZE 0xFF871208 //Q ++ ++#define OID_RT_SET_BANDWIDTH 0xFF871209 //S ++#define OID_RT_SET_CRYSTAL_CAP 0xFF87120A //S ++ ++#define OID_RT_SET_RX_PACKET_TYPE 0xFF87120B //S ++ ++#define OID_RT_GET_EFUSE_MAX_SIZE 0xFF87120C //Q ++ ++#define OID_RT_PRO_SET_TX_AGC_OFFSET 0xFF87120D //S ++ ++#define OID_RT_PRO_SET_PKT_TEST_MODE 0xFF87120E //S ++ ++#define OID_RT_PRO_FOR_EVM_TEST_SETTING 0xFF87120F //S ++ ++#define OID_RT_PRO_GET_THERMAL_METER 0xFF871210 //Q ++ ++#define OID_RT_RESET_PHY_RX_PACKET_COUNT 0xFF871211 //S ++#define OID_RT_GET_PHY_RX_PACKET_RECEIVED 0xFF871212 //Q ++#define OID_RT_GET_PHY_RX_PACKET_CRC32_ERROR 0xFF871213 //Q ++ ++#define OID_RT_SET_POWER_DOWN 0xFF871214 //S ++ ++#define OID_RT_GET_POWER_MODE 0xFF871215 //Q ++ ++#define OID_RT_PRO_EFUSE 0xFF871216 //Q, S ++#define OID_RT_PRO_EFUSE_MAP 0xFF871217 //Q, S ++ ++#endif //#ifndef __CUSTOM_OID_H +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/include/nic_spec.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/include/nic_spec.h 2013-07-26 19:36:06.000000000 +0000 +@@ -0,0 +1,47 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++ ++ ++#ifndef __NIC_SPEC_H__ ++#define __NIC_SPEC_H__ ++ ++#include ++ ++#define RTL8711_MCTRL_ (0x20000) ++#define RTL8711_UART_ (0x30000) ++#define RTL8711_TIMER_ (0x40000) ++#define RTL8711_FINT_ (0x50000) ++#define RTL8711_HINT_ (0x50000) ++#define RTL8711_GPIO_ (0x60000) ++#define RTL8711_WLANCTRL_ (0x200000) ++#define RTL8711_WLANFF_ (0xe00000) ++#define RTL8711_HCICTRL_ (0x600000) ++#define RTL8711_SYSCFG_ (0x620000) ++#define RTL8711_SYSCTRL_ (0x620000) ++#define RTL8711_MCCTRL_ (0x020000) ++ ++ ++#include ++ ++#include ++ ++ ++#endif // __RTL8711_SPEC_H__ ++ +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/include/osdep_ce_service.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/include/osdep_ce_service.h 2013-07-26 19:36:06.000000000 +0000 +@@ -0,0 +1,171 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++ ++#ifndef __OSDEP_CE_SERVICE_H_ ++#define __OSDEP_CE_SERVICE_H_ ++ ++ ++#include ++#include ++ ++#ifdef CONFIG_SDIO_HCI ++#include "SDCardDDK.h" ++#endif ++ ++#ifdef CONFIG_USB_HCI ++#include ++#endif ++ ++typedef HANDLE _sema; ++typedef LIST_ENTRY _list; ++typedef NDIS_STATUS _OS_STATUS; ++ ++typedef NDIS_SPIN_LOCK _lock; ++ ++typedef HANDLE _rwlock; //Mutex ++ ++typedef u32 _irqL; ++ ++typedef NDIS_HANDLE _nic_hdl; ++ ++ ++typedef NDIS_MINIPORT_TIMER _timer; ++ ++struct __queue { ++ LIST_ENTRY queue; ++ _lock lock; ++}; ++ ++typedef NDIS_PACKET _pkt; ++typedef NDIS_BUFFER _buffer; ++typedef struct __queue _queue; ++ ++typedef HANDLE _thread_hdl_; ++typedef DWORD thread_return; ++typedef void* thread_context; ++typedef NDIS_WORK_ITEM _workitem; ++ ++#define thread_exit() ExitThread(STATUS_SUCCESS); return 0; ++ ++ ++#define SEMA_UPBND (0x7FFFFFFF) //8192 ++ ++__inline static _list *get_prev(_list *list) ++{ ++ return list->Blink; ++} ++ ++__inline static _list *get_next(_list *list) ++{ ++ return list->Flink; ++} ++ ++__inline static _list *get_list_head(_queue *queue) ++{ ++ return (&(queue->queue)); ++} ++ ++#define LIST_CONTAINOR(ptr, type, member) CONTAINING_RECORD(ptr, type, member) ++ ++__inline static void _enter_critical(_lock *plock, _irqL *pirqL) ++{ ++ NdisAcquireSpinLock(plock); ++} ++ ++__inline static void _exit_critical(_lock *plock, _irqL *pirqL) ++{ ++ NdisReleaseSpinLock(plock); ++} ++ ++__inline static _enter_critical_ex(_lock *plock, _irqL *pirqL) ++{ ++ NdisDprAcquireSpinLock(plock); ++} ++ ++__inline static _exit_critical_ex(_lock *plock, _irqL *pirqL) ++{ ++ NdisDprReleaseSpinLock(plock); ++} ++ ++ ++__inline static void _enter_hwio_critical(_rwlock *prwlock, _irqL *pirqL) ++{ ++ WaitForSingleObject(*prwlock, INFINITE ); ++ ++} ++ ++__inline static void _exit_hwio_critical(_rwlock *prwlock, _irqL *pirqL) ++{ ++ ReleaseMutex(*prwlock); ++} ++ ++__inline static void rtw_list_delete(_list *plist) ++{ ++ RemoveEntryList(plist); ++ InitializeListHead(plist); ++} ++ ++__inline static void _init_timer(_timer *ptimer,_nic_hdl nic_hdl,void *pfunc,PVOID cntx) ++{ ++ NdisMInitializeTimer(ptimer, nic_hdl, pfunc, cntx); ++} ++ ++__inline static void _set_timer(_timer *ptimer,u32 delay_time) ++{ ++ NdisMSetTimer(ptimer,delay_time); ++} ++ ++__inline static void _cancel_timer(_timer *ptimer,u8 *bcancelled) ++{ ++ NdisMCancelTimer(ptimer,bcancelled); ++} ++ ++__inline static void _init_workitem(_workitem *pwork, void *pfunc, PVOID cntx) ++{ ++ ++ NdisInitializeWorkItem(pwork, pfunc, cntx); ++} ++ ++__inline static void _set_workitem(_workitem *pwork) ++{ ++ NdisScheduleWorkItem(pwork); ++} ++ ++#define ATOMIC_INIT(i) { (i) } ++ ++// ++// Global Mutex: can only be used at PASSIVE level. ++// ++ ++#define ACQUIRE_GLOBAL_MUTEX(_MutexCounter) \ ++{ \ ++ while (NdisInterlockedIncrement((PULONG)&(_MutexCounter)) != 1)\ ++ { \ ++ NdisInterlockedDecrement((PULONG)&(_MutexCounter)); \ ++ NdisMSleep(10000); \ ++ } \ ++} ++ ++#define RELEASE_GLOBAL_MUTEX(_MutexCounter) \ ++{ \ ++ NdisInterlockedDecrement((PULONG)&(_MutexCounter)); \ ++} ++#endif ++ +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/include/osdep_intf.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/include/osdep_intf.h 2013-07-26 19:36:06.000000000 +0000 +@@ -0,0 +1,128 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++ ++#ifndef __OSDEP_INTF_H_ ++#define __OSDEP_INTF_H_ ++ ++#include ++#include ++#include ++ ++#define RND4(x) (((x >> 2) + (((x & 3) == 0) ? 0: 1)) << 2) ++ ++ ++struct intf_priv { ++ ++ u8 *intf_dev; ++ u32 max_iosz; //USB2.0: 128, USB1.1: 64, SDIO:64 ++ u32 max_xmitsz; //USB2.0: unlimited, SDIO:512 ++ u32 max_recvsz; //USB2.0: unlimited, SDIO:512 ++ ++ volatile u8 *io_rwmem; ++ volatile u8 *allocated_io_rwmem; ++ u32 io_wsz; //unit: 4bytes ++ u32 io_rsz;//unit: 4bytes ++ u8 intf_status; ++ ++ void (*_bus_io)(u8 *priv); ++ ++/* ++Under Sync. IRP (SDIO/USB) ++A protection mechanism is necessary for the io_rwmem(read/write protocol) ++ ++Under Async. IRP (SDIO/USB) ++The protection mechanism is through the pending queue. ++*/ ++ ++ _mutex ioctl_mutex; ++ ++ ++#ifdef PLATFORM_LINUX ++ #ifdef CONFIG_USB_HCI ++ // when in USB, IO is through interrupt in/out endpoints ++ struct usb_device *udev; ++ PURB piorw_urb; ++ u8 io_irp_cnt; ++ u8 bio_irp_pending; ++ _sema io_retevt; ++ _timer io_timer; ++ u8 bio_irp_timeout; ++ u8 bio_timer_cancel; ++ #endif ++#endif ++ ++#ifdef PLATFORM_OS_XP ++ #ifdef CONFIG_SDIO_HCI ++ // below is for io_rwmem... ++ PMDL pmdl; ++ PSDBUS_REQUEST_PACKET sdrp; ++ PSDBUS_REQUEST_PACKET recv_sdrp; ++ PSDBUS_REQUEST_PACKET xmit_sdrp; ++ ++ PIRP piorw_irp; ++ ++ #endif ++ #ifdef CONFIG_USB_HCI ++ PURB piorw_urb; ++ PIRP piorw_irp; ++ u8 io_irp_cnt; ++ u8 bio_irp_pending; ++ _sema io_retevt; ++ #endif ++#endif ++ ++}; ++ ++ ++#ifdef CONFIG_R871X_TEST ++int rtw_start_pseudo_adhoc(_adapter *padapter); ++int rtw_stop_pseudo_adhoc(_adapter *padapter); ++#endif ++ ++u8 rtw_init_drv_sw(_adapter *padapter); ++u8 rtw_free_drv_sw(_adapter *padapter); ++u8 rtw_reset_drv_sw(_adapter *padapter); ++ ++u32 rtw_start_drv_threads(_adapter *padapter); ++void rtw_stop_drv_threads (_adapter *padapter); ++void rtw_cancel_all_timer(_adapter *padapter); ++ ++#ifdef PLATFORM_LINUX ++int rtw_ioctl(struct net_device *dev, struct ifreq *rq, int cmd); ++ ++int rtw_init_netdev_name(struct net_device *pnetdev, const char *ifname); ++struct net_device *rtw_init_netdev(_adapter *padapter); ++ ++#ifdef CONFIG_PROC_DEBUG ++void rtw_proc_init_one(struct net_device *dev); ++void rtw_proc_remove_one(struct net_device *dev); ++#endif ++#endif ++ ++ ++void rtw_ips_dev_unload(_adapter *padapter); ++#ifdef CONFIG_IPS ++int rtw_ips_pwr_up(_adapter *padapter); ++void rtw_ips_pwr_down(_adapter *padapter); ++#endif ++ ++ ++#endif //_OSDEP_INTF_H_ ++ +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/include/osdep_service.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/include/osdep_service.h 2013-07-26 19:36:06.000000000 +0000 +@@ -0,0 +1,830 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef __OSDEP_SERVICE_H_ ++#define __OSDEP_SERVICE_H_ ++ ++#include ++#include ++//#include ++ ++#define _SUCCESS 1 ++#define _FAIL 0 ++//#define RTW_STATUS_TIMEDOUT -110 ++ ++#undef _TRUE ++#define _TRUE 1 ++ ++#undef _FALSE ++#define _FALSE 0 ++ ++ ++#ifdef PLATFORM_LINUX ++ #include ++ #include ++ #include ++ #include ++ #include ++ #include ++ #include ++ #include ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,5)) ++ #include ++#endif ++ //#include ++ #include ++ #include ++ #include ++ #include ++ #include ++ #include ++ #include ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,26)) ++ #include ++#else ++ #include ++#endif ++ #include ++ #include ++ #include ++ #include ++ #include ++ #include ++ #include ++ #include ++ #include // Necessary because we use the proc fs ++ ++#ifdef CONFIG_IOCTL_CFG80211 ++// #include ++ #include ++ #include ++#endif //CONFIG_IOCTL_CFG80211 ++ ++#ifdef CONFIG_TCP_CSUM_OFFLOAD_TX ++ #include ++ #include ++ #include ++#endif ++ ++#ifdef CONFIG_USB_HCI ++ #include ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,21)) ++ #include ++#else ++ #include ++#endif ++#endif ++ ++#ifdef CONFIG_SDIO_HCI ++ #include ++ #include ++#endif ++ ++#ifdef CONFIG_PCI_HCI ++ #include ++#endif ++ ++ ++#ifdef CONFIG_USB_HCI ++ typedef struct urb * PURB; ++#if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,22)) ++#ifdef CONFIG_USB_SUSPEND ++#define CONFIG_AUTOSUSPEND 1 ++#endif ++#endif ++#endif ++ ++ typedef struct semaphore _sema; ++ typedef spinlock_t _lock; ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) ++ typedef struct mutex _mutex; ++#else ++ typedef struct semaphore _mutex; ++#endif ++ typedef struct timer_list _timer; ++ ++ struct __queue { ++ struct list_head queue; ++ _lock lock; ++ }; ++ ++ typedef struct sk_buff _pkt; ++ typedef unsigned char _buffer; ++ ++ typedef struct __queue _queue; ++ typedef struct list_head _list; ++ typedef int _OS_STATUS; ++ //typedef u32 _irqL; ++ typedef unsigned long _irqL; ++ typedef struct net_device * _nic_hdl; ++ ++ typedef pid_t _thread_hdl_; ++ typedef int thread_return; ++ typedef void* thread_context; ++ ++ #define thread_exit() complete_and_exit(NULL, 0) ++ ++ typedef void timer_hdl_return; ++ typedef void* timer_hdl_context; ++ typedef struct work_struct _workitem; ++ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24)) ++ #define DMA_BIT_MASK(n) (((n) == 64) ? ~0ULL : ((1ULL<<(n))-1)) ++#endif ++ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,22)) ++ #define skb_tail_pointer(skb) skb->tail ++#endif ++ ++__inline static _list *get_next(_list *list) ++{ ++ return list->next; ++} ++ ++__inline static _list *get_list_head(_queue *queue) ++{ ++ return (&(queue->queue)); ++} ++ ++ ++#define LIST_CONTAINOR(ptr, type, member) \ ++ ((type *)((char *)(ptr)-(SIZE_T)(&((type *)0)->member))) ++ ++ ++__inline static void _enter_critical(_lock *plock, _irqL *pirqL) ++{ ++ spin_lock_irqsave(plock, *pirqL); ++} ++ ++__inline static void _exit_critical(_lock *plock, _irqL *pirqL) ++{ ++ spin_unlock_irqrestore(plock, *pirqL); ++} ++ ++__inline static void _enter_critical_ex(_lock *plock, _irqL *pirqL) ++{ ++ spin_lock_irqsave(plock, *pirqL); ++} ++ ++__inline static void _exit_critical_ex(_lock *plock, _irqL *pirqL) ++{ ++ spin_unlock_irqrestore(plock, *pirqL); ++} ++ ++__inline static void _enter_critical_bh(_lock *plock, _irqL *pirqL) ++{ ++ spin_lock_bh(plock); ++} ++ ++__inline static void _exit_critical_bh(_lock *plock, _irqL *pirqL) ++{ ++ spin_unlock_bh(plock); ++} ++ ++__inline static void _enter_critical_mutex(_mutex *pmutex, _irqL *pirqL) ++{ ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) ++ mutex_lock(pmutex); ++#else ++ down(pmutex); ++#endif ++} ++ ++ ++__inline static void _exit_critical_mutex(_mutex *pmutex, _irqL *pirqL) ++{ ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) ++ mutex_unlock(pmutex); ++#else ++ up(pmutex); ++#endif ++} ++ ++__inline static void rtw_list_delete(_list *plist) ++{ ++ list_del_init(plist); ++} ++ ++__inline static void _init_timer(_timer *ptimer,_nic_hdl nic_hdl,void *pfunc,void* cntx) ++{ ++ //setup_timer(ptimer, pfunc,(u32)cntx); ++ ptimer->function = pfunc; ++ ptimer->data = (unsigned long)cntx; ++ init_timer(ptimer); ++} ++ ++__inline static void _set_timer(_timer *ptimer,u32 delay_time) ++{ ++ mod_timer(ptimer , (jiffies+(delay_time*HZ/1000))); ++} ++ ++__inline static void _cancel_timer(_timer *ptimer,u8 *bcancelled) ++{ ++ del_timer_sync(ptimer); ++ *bcancelled= _TRUE;//TRUE ==1; FALSE==0 ++} ++ ++#ifdef PLATFORM_LINUX ++#define RTW_TIMER_HDL_ARGS void *FunctionContext ++#elif defined(PLATFORM_OS_CE) || defined(PLATFORM_WINDOWS) ++#define RTW_TIMER_HDL_ARGS IN PVOID SystemSpecific1, IN PVOID FunctionContext, IN PVOID SystemSpecific2, IN PVOID SystemSpecific3 ++#endif ++ ++#define RTW_TIMER_HDL_NAME(name) rtw_##name##_timer_hdl ++#define RTW_DECLARE_TIMER_HDL(name) void RTW_TIMER_HDL_NAME(name)(RTW_TIMER_HDL_ARGS) ++ ++ ++__inline static void _init_workitem(_workitem *pwork, void *pfunc, PVOID cntx) ++{ ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)) ++ INIT_WORK(pwork, pfunc); ++#else ++ INIT_WORK(pwork, pfunc,pwork); ++#endif ++} ++ ++__inline static void _set_workitem(_workitem *pwork) ++{ ++ schedule_work(pwork); ++} ++ ++// ++// Global Mutex: can only be used at PASSIVE level. ++// ++ ++#define ACQUIRE_GLOBAL_MUTEX(_MutexCounter) \ ++{ \ ++ while (atomic_inc_return((atomic_t *)&(_MutexCounter)) != 1)\ ++ { \ ++ atomic_dec((atomic_t *)&(_MutexCounter)); \ ++ msleep(10); \ ++ } \ ++} ++ ++#define RELEASE_GLOBAL_MUTEX(_MutexCounter) \ ++{ \ ++ atomic_dec((atomic_t *)&(_MutexCounter)); \ ++} ++ ++#endif // PLATFORM_LINUX ++ ++ ++#ifdef PLATFORM_OS_XP ++ ++ #include ++ #include ++ #include ++ #include ++ #include ++ ++#ifdef CONFIG_USB_HCI ++ #include ++ #include ++ #include ++#endif ++ ++ typedef KSEMAPHORE _sema; ++ typedef LIST_ENTRY _list; ++ typedef NDIS_STATUS _OS_STATUS; ++ ++ ++ typedef NDIS_SPIN_LOCK _lock; ++ ++ typedef KMUTEX _mutex; ++ ++ typedef KIRQL _irqL; ++ ++ // USB_PIPE for WINCE , but handle can be use just integer under windows ++ typedef NDIS_HANDLE _nic_hdl; ++ ++ ++ typedef NDIS_MINIPORT_TIMER _timer; ++ ++ struct __queue { ++ LIST_ENTRY queue; ++ _lock lock; ++ }; ++ ++ typedef NDIS_PACKET _pkt; ++ typedef NDIS_BUFFER _buffer; ++ typedef struct __queue _queue; ++ ++ typedef PKTHREAD _thread_hdl_; ++ typedef void thread_return; ++ typedef void* thread_context; ++ ++ typedef NDIS_WORK_ITEM _workitem; ++ ++ #define thread_exit() PsTerminateSystemThread(STATUS_SUCCESS); ++ ++ #define HZ 10000000 ++ #define SEMA_UPBND (0x7FFFFFFF) //8192 ++ ++__inline static _list *get_next(_list *list) ++{ ++ return list->Flink; ++} ++ ++__inline static _list *get_list_head(_queue *queue) ++{ ++ return (&(queue->queue)); ++} ++ ++ ++#define LIST_CONTAINOR(ptr, type, member) CONTAINING_RECORD(ptr, type, member) ++ ++ ++__inline static _enter_critical(_lock *plock, _irqL *pirqL) ++{ ++ NdisAcquireSpinLock(plock); ++} ++ ++__inline static _exit_critical(_lock *plock, _irqL *pirqL) ++{ ++ NdisReleaseSpinLock(plock); ++} ++ ++ ++__inline static _enter_critical_ex(_lock *plock, _irqL *pirqL) ++{ ++ NdisDprAcquireSpinLock(plock); ++} ++ ++__inline static _exit_critical_ex(_lock *plock, _irqL *pirqL) ++{ ++ NdisDprReleaseSpinLock(plock); ++} ++ ++__inline static void _enter_critical_bh(_lock *plock, _irqL *pirqL) ++{ ++ NdisDprAcquireSpinLock(plock); ++} ++ ++__inline static void _exit_critical_bh(_lock *plock, _irqL *pirqL) ++{ ++ NdisDprReleaseSpinLock(plock); ++} ++ ++__inline static _enter_critical_mutex(_mutex *pmutex, _irqL *pirqL) ++{ ++ KeWaitForSingleObject(pmutex, Executive, KernelMode, FALSE, NULL); ++} ++ ++ ++__inline static _exit_critical_mutex(_mutex *pmutex, _irqL *pirqL) ++{ ++ KeReleaseMutex(pmutex, FALSE); ++} ++ ++ ++__inline static void rtw_list_delete(_list *plist) ++{ ++ RemoveEntryList(plist); ++ InitializeListHead(plist); ++} ++ ++__inline static void _init_timer(_timer *ptimer,_nic_hdl nic_hdl,void *pfunc,PVOID cntx) ++{ ++ NdisMInitializeTimer(ptimer, nic_hdl, pfunc, cntx); ++} ++ ++__inline static void _set_timer(_timer *ptimer,u32 delay_time) ++{ ++ NdisMSetTimer(ptimer,delay_time); ++} ++ ++__inline static void _cancel_timer(_timer *ptimer,u8 *bcancelled) ++{ ++ NdisMCancelTimer(ptimer,bcancelled); ++} ++ ++__inline static void _init_workitem(_workitem *pwork, void *pfunc, PVOID cntx) ++{ ++ ++ NdisInitializeWorkItem(pwork, pfunc, cntx); ++} ++ ++__inline static void _set_workitem(_workitem *pwork) ++{ ++ NdisScheduleWorkItem(pwork); ++} ++ ++ ++#define ATOMIC_INIT(i) { (i) } ++ ++// ++// Global Mutex: can only be used at PASSIVE level. ++// ++ ++#define ACQUIRE_GLOBAL_MUTEX(_MutexCounter) \ ++{ \ ++ while (NdisInterlockedIncrement((PULONG)&(_MutexCounter)) != 1)\ ++ { \ ++ NdisInterlockedDecrement((PULONG)&(_MutexCounter)); \ ++ NdisMSleep(10000); \ ++ } \ ++} ++ ++#define RELEASE_GLOBAL_MUTEX(_MutexCounter) \ ++{ \ ++ NdisInterlockedDecrement((PULONG)&(_MutexCounter)); \ ++} ++ ++#endif // PLATFORM_OS_XP ++ ++ ++#ifdef PLATFORM_OS_CE ++#include ++#endif ++ ++#include ++ ++#ifndef BIT ++ #define BIT(x) ( 1 << (x)) ++#endif ++ ++extern int RTW_STATUS_CODE(int error_code); ++ ++#define CONFIG_USE_VMALLOC ++ ++#ifdef DBG_MEM_ALLOC ++void rtw_dump_mem_stat (void); ++extern u8* dbg_rtw_vmalloc(u32 sz, const char *func, int line); ++extern u8* dbg_rtw_zvmalloc(u32 sz, const char *func, int line); ++extern void dbg_rtw_vmfree(u8 *pbuf, u32 sz, const char *func, int line); ++extern u8* dbg_rtw_malloc(u32 sz, const char *func, int line); ++extern u8* dbg_rtw_zmalloc(u32 sz, const char *func, int line); ++extern void dbg_rtw_mfree(u8 *pbuf, u32 sz, const char *func, int line); ++#ifdef CONFIG_USE_VMALLOC ++#define rtw_vmalloc(sz) dbg_rtw_vmalloc((sz), __FUNCTION__, __LINE__) ++#define rtw_zvmalloc(sz) dbg_rtw_zvmalloc((sz), __FUNCTION__, __LINE__) ++#define rtw_vmfree(pbuf, sz) dbg_rtw_vmfree((pbuf), (sz), __FUNCTION__, __LINE__) ++#else //CONFIG_USE_VMALLOC ++#define rtw_vmalloc(sz) dbg_rtw_malloc((sz), __FUNCTION__, __LINE__) ++#define rtw_zvmalloc(sz) dbg_rtw_zmalloc((sz), __FUNCTION__, __LINE__) ++#define rtw_vmfree(pbuf, sz) dbg_rtw_mfree((pbuf), (sz), __FUNCTION__, __LINE__) ++#endif //CONFIG_USE_VMALLOC ++#define rtw_malloc(sz) dbg_rtw_malloc((sz), __FUNCTION__, __LINE__) ++#define rtw_zmalloc(sz) dbg_rtw_zmalloc((sz), __FUNCTION__, __LINE__) ++#define rtw_mfree(pbuf, sz) dbg_rtw_mfree((pbuf), (sz), __FUNCTION__, __LINE__) ++#else ++extern u8* _rtw_vmalloc(u32 sz); ++extern u8* _rtw_zvmalloc(u32 sz); ++extern void _rtw_vmfree(u8 *pbuf, u32 sz); ++extern u8* _rtw_zmalloc(u32 sz); ++extern u8* _rtw_malloc(u32 sz); ++extern void _rtw_mfree(u8 *pbuf, u32 sz); ++#ifdef CONFIG_USE_VMALLOC ++#define rtw_vmalloc(sz) _rtw_vmalloc((sz)) ++#define rtw_zvmalloc(sz) _rtw_zvmalloc((sz)) ++#define rtw_vmfree(pbuf, sz) _rtw_vmfree((pbuf), (sz)) ++#else //CONFIG_USE_VMALLOC ++#define rtw_vmalloc(sz) _rtw_malloc((sz)) ++#define rtw_zvmalloc(sz) _rtw_zmalloc((sz)) ++#define rtw_vmfree(pbuf, sz) _rtw_mfree((pbuf), (sz)) ++#endif //CONFIG_USE_VMALLOC ++#define rtw_malloc(sz) _rtw_malloc((sz)) ++#define rtw_zmalloc(sz) _rtw_zmalloc((sz)) ++#define rtw_mfree(pbuf, sz) _rtw_mfree((pbuf), (sz)) ++#endif ++ ++extern void _rtw_memcpy(void* dec, void* sour, u32 sz); ++extern int _rtw_memcmp(void *dst, void *src, u32 sz); ++extern void _rtw_memset(void *pbuf, int c, u32 sz); ++ ++extern void _rtw_init_listhead(_list *list); ++extern u32 rtw_is_list_empty(_list *phead); ++extern void rtw_list_insert_tail(_list *plist, _list *phead); ++extern void rtw_list_delete(_list *plist); ++ ++extern void _rtw_init_sema(_sema *sema, int init_val); ++extern void _rtw_free_sema(_sema *sema); ++extern void _rtw_up_sema(_sema *sema); ++extern u32 _rtw_down_sema(_sema *sema); ++extern void _rtw_mutex_init(_mutex *pmutex); ++extern void _rtw_mutex_free(_mutex *pmutex); ++extern void _rtw_spinlock_init(_lock *plock); ++extern void _rtw_spinlock_free(_lock *plock); ++extern void _rtw_spinlock(_lock *plock); ++extern void _rtw_spinunlock(_lock *plock); ++extern void _rtw_spinlock_ex(_lock *plock); ++extern void _rtw_spinunlock_ex(_lock *plock); ++ ++extern void _rtw_init_queue(_queue *pqueue); ++extern u32 _rtw_queue_empty(_queue *pqueue); ++extern u32 rtw_end_of_queue_search(_list *queue, _list *pelement); ++ ++extern u32 rtw_get_current_time(void); ++extern u32 rtw_systime_to_ms(u32 systime); ++extern s32 rtw_get_passing_time_ms(u32 start); ++extern s32 rtw_get_time_interval_ms(u32 start, u32 end); ++ ++extern void rtw_sleep_schedulable(int ms); ++ ++extern void rtw_msleep_os(int ms); ++extern void rtw_usleep_os(int us); ++ ++#ifdef DBG_DELAY_OS ++#define rtw_mdelay_os(ms) _rtw_mdelay_os((ms), __FUNCTION__, __LINE__) ++#define rtw_udelay_os(ms) _rtw_udelay_os((ms), __FUNCTION__, __LINE__) ++extern void _rtw_mdelay_os(int ms, const char *func, const int line); ++extern void _rtw_udelay_os(int us, const char *func, const int line); ++#else ++extern void rtw_mdelay_os(int ms); ++extern void rtw_udelay_os(int us); ++#endif ++ ++ ++ ++__inline static unsigned char _cancel_timer_ex(_timer *ptimer) ++{ ++#ifdef PLATFORM_LINUX ++ return del_timer_sync(ptimer); ++#endif ++ ++#ifdef PLATFORM_WINDOWS ++ u8 bcancelled; ++ ++ _cancel_timer(ptimer, &bcancelled); ++ ++ return bcancelled; ++#endif ++} ++ ++__inline static void thread_enter(void *context) ++{ ++#ifdef PLATFORM_LINUX ++ //struct net_device *pnetdev = (struct net_device *)context; ++ //daemonize("%s", pnetdev->name); ++ daemonize("%s", "RTKTHREAD"); ++ allow_signal(SIGTERM); ++#endif ++} ++ ++__inline static void flush_signals_thread(void) ++{ ++#ifdef PLATFORM_LINUX ++ if (signal_pending (current)) ++ { ++ flush_signals(current); ++ } ++#endif ++} ++ ++__inline static _OS_STATUS res_to_status(sint res) ++{ ++ ++ ++#if defined (PLATFORM_LINUX) || defined (PLATFORM_MPIXEL) ++ return res; ++#endif ++ ++#ifdef PLATFORM_WINDOWS ++ ++ if (res == _SUCCESS) ++ return NDIS_STATUS_SUCCESS; ++ else ++ return NDIS_STATUS_FAILURE; ++ ++#endif ++ ++} ++ ++__inline static u32 _RND4(u32 sz) ++{ ++ ++ u32 val; ++ ++ val = ((sz >> 2) + ((sz & 3) ? 1: 0)) << 2; ++ ++ return val; ++ ++} ++ ++__inline static u32 _RND8(u32 sz) ++{ ++ ++ u32 val; ++ ++ val = ((sz >> 3) + ((sz & 7) ? 1: 0)) << 3; ++ ++ return val; ++ ++} ++ ++__inline static u32 _RND128(u32 sz) ++{ ++ ++ u32 val; ++ ++ val = ((sz >> 7) + ((sz & 127) ? 1: 0)) << 7; ++ ++ return val; ++ ++} ++ ++__inline static u32 _RND256(u32 sz) ++{ ++ ++ u32 val; ++ ++ val = ((sz >> 8) + ((sz & 255) ? 1: 0)) << 8; ++ ++ return val; ++ ++} ++ ++__inline static u32 _RND512(u32 sz) ++{ ++ ++ u32 val; ++ ++ val = ((sz >> 9) + ((sz & 511) ? 1: 0)) << 9; ++ ++ return val; ++ ++} ++ ++__inline static u32 bitshift(u32 bitmask) ++{ ++ u32 i; ++ ++ for (i = 0; i <= 31; i++) ++ if (((bitmask>>i) & 0x1) == 1) break; ++ ++ return i; ++} ++ ++#ifndef MAC_FMT ++#define MAC_FMT "%02x:%02x:%02x:%02x:%02x:%02x" ++#endif ++#ifndef MAC_ARG ++#define MAC_ARG(x) ((u8*)(x))[0],((u8*)(x))[1],((u8*)(x))[2],((u8*)(x))[3],((u8*)(x))[4],((u8*)(x))[5] ++#endif ++ ++//#ifdef __GNUC__ ++#ifdef PLATFORM_LINUX ++#define STRUCT_PACKED __attribute__ ((packed)) ++#else ++#define STRUCT_PACKED ++#endif ++ ++ ++// limitation of path length ++#ifdef PLATFORM_LINUX ++ #define PATH_LENGTH_MAX PATH_MAX ++#elif defined(PLATFORM_WINDOWS) ++ #define PATH_LENGTH_MAX MAX_PATH ++#endif ++ ++ ++// Suspend lock prevent system from going suspend ++#ifdef CONFIG_WAKELOCK ++#include ++#elif defined(CONFIG_ANDROID_POWER) ++#include ++#endif ++ ++extern void rtw_suspend_lock_init(void); ++extern void rtw_suspend_lock_uninit(void); ++extern void rtw_lock_suspend(void); ++extern void rtw_unlock_suspend(void); ++ ++ ++//Atomic integer operations ++#ifdef PLATFORM_LINUX ++ #define ATOMIC_T atomic_t ++#elif defined(PLATFORM_WINDOWS) ++ #define ATOMIC_T LONG ++#endif ++ ++extern void ATOMIC_SET(ATOMIC_T *v, int i); ++extern int ATOMIC_READ(ATOMIC_T *v); ++extern void ATOMIC_ADD(ATOMIC_T *v, int i); ++extern void ATOMIC_SUB(ATOMIC_T *v, int i); ++extern void ATOMIC_INC(ATOMIC_T *v); ++extern void ATOMIC_DEC(ATOMIC_T *v); ++extern int ATOMIC_ADD_RETURN(ATOMIC_T *v, int i); ++extern int ATOMIC_SUB_RETURN(ATOMIC_T *v, int i); ++extern int ATOMIC_INC_RETURN(ATOMIC_T *v); ++extern int ATOMIC_DEC_RETURN(ATOMIC_T *v); ++ ++//File operation APIs, just for linux now ++extern int rtw_is_file_readable(char *path); ++extern int rtw_retrive_from_file(char *path, u8* buf, u32 sz); ++extern int rtw_store_to_file(char *path, u8* buf, u32 sz); ++ ++ ++ ++#if 1 //#ifdef MEM_ALLOC_REFINE_ADAPTOR ++struct rtw_netdev_priv_indicator { ++ void *priv; ++ u32 sizeof_priv; ++}; ++struct net_device *rtw_alloc_etherdev_with_old_priv(int sizeof_priv, void *old_priv); ++extern struct net_device * rtw_alloc_etherdev(int sizeof_priv); ++#define rtw_netdev_priv(netdev) ( ((struct rtw_netdev_priv_indicator *)netdev_priv(netdev))->priv ) ++extern void rtw_free_netdev(struct net_device * netdev); ++#else ++#define rtw_alloc_etherdev(sizeof_priv) alloc_etherdev((sizeof_priv)) ++#define rtw_netdev_priv(netdev) netdev_priv((netdev)) ++#define rtw_free_netdev(netdev) free_netdev((netdev)) ++#endif ++ ++#ifdef PLATFORM_LINUX ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,27)) ++#define rtw_signal_process(pid, sig) kill_pid(find_vpid((pid)),(sig), 1) ++#else ++#define rtw_signal_process(pid, sig) kill_proc((pid), (sig), 1) ++#endif ++#endif //PLATFORM_LINUX ++ ++extern u64 rtw_modular64(u64 x, u64 y); ++extern u64 rtw_division64(u64 x, u64 y); ++ ++ ++/* Macros for handling unaligned memory accesses */ ++ ++#define RTW_GET_BE16(a) ((u16) (((a)[0] << 8) | (a)[1])) ++#define RTW_PUT_BE16(a, val) \ ++ do { \ ++ (a)[0] = ((u16) (val)) >> 8; \ ++ (a)[1] = ((u16) (val)) & 0xff; \ ++ } while (0) ++ ++#define RTW_GET_LE16(a) ((u16) (((a)[1] << 8) | (a)[0])) ++#define RTW_PUT_LE16(a, val) \ ++ do { \ ++ (a)[1] = ((u16) (val)) >> 8; \ ++ (a)[0] = ((u16) (val)) & 0xff; \ ++ } while (0) ++ ++#define RTW_GET_BE24(a) ((((u32) (a)[0]) << 16) | (((u32) (a)[1]) << 8) | \ ++ ((u32) (a)[2])) ++#define RTW_PUT_BE24(a, val) \ ++ do { \ ++ (a)[0] = (u8) ((((u32) (val)) >> 16) & 0xff); \ ++ (a)[1] = (u8) ((((u32) (val)) >> 8) & 0xff); \ ++ (a)[2] = (u8) (((u32) (val)) & 0xff); \ ++ } while (0) ++ ++#define RTW_GET_BE32(a) ((((u32) (a)[0]) << 24) | (((u32) (a)[1]) << 16) | \ ++ (((u32) (a)[2]) << 8) | ((u32) (a)[3])) ++#define RTW_PUT_BE32(a, val) \ ++ do { \ ++ (a)[0] = (u8) ((((u32) (val)) >> 24) & 0xff); \ ++ (a)[1] = (u8) ((((u32) (val)) >> 16) & 0xff); \ ++ (a)[2] = (u8) ((((u32) (val)) >> 8) & 0xff); \ ++ (a)[3] = (u8) (((u32) (val)) & 0xff); \ ++ } while (0) ++ ++#define RTW_GET_LE32(a) ((((u32) (a)[3]) << 24) | (((u32) (a)[2]) << 16) | \ ++ (((u32) (a)[1]) << 8) | ((u32) (a)[0])) ++#define RTW_PUT_LE32(a, val) \ ++ do { \ ++ (a)[3] = (u8) ((((u32) (val)) >> 24) & 0xff); \ ++ (a)[2] = (u8) ((((u32) (val)) >> 16) & 0xff); \ ++ (a)[1] = (u8) ((((u32) (val)) >> 8) & 0xff); \ ++ (a)[0] = (u8) (((u32) (val)) & 0xff); \ ++ } while (0) ++ ++#define RTW_GET_BE64(a) ((((u64) (a)[0]) << 56) | (((u64) (a)[1]) << 48) | \ ++ (((u64) (a)[2]) << 40) | (((u64) (a)[3]) << 32) | \ ++ (((u64) (a)[4]) << 24) | (((u64) (a)[5]) << 16) | \ ++ (((u64) (a)[6]) << 8) | ((u64) (a)[7])) ++#define RTW_PUT_BE64(a, val) \ ++ do { \ ++ (a)[0] = (u8) (((u64) (val)) >> 56); \ ++ (a)[1] = (u8) (((u64) (val)) >> 48); \ ++ (a)[2] = (u8) (((u64) (val)) >> 40); \ ++ (a)[3] = (u8) (((u64) (val)) >> 32); \ ++ (a)[4] = (u8) (((u64) (val)) >> 24); \ ++ (a)[5] = (u8) (((u64) (val)) >> 16); \ ++ (a)[6] = (u8) (((u64) (val)) >> 8); \ ++ (a)[7] = (u8) (((u64) (val)) & 0xff); \ ++ } while (0) ++ ++#define RTW_GET_LE64(a) ((((u64) (a)[7]) << 56) | (((u64) (a)[6]) << 48) | \ ++ (((u64) (a)[5]) << 40) | (((u64) (a)[4]) << 32) | \ ++ (((u64) (a)[3]) << 24) | (((u64) (a)[2]) << 16) | \ ++ (((u64) (a)[1]) << 8) | ((u64) (a)[0])) ++ ++#endif ++ ++ +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/include/pci_hal.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/include/pci_hal.h 2013-07-26 19:36:06.000000000 +0000 +@@ -0,0 +1,168 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef __PCI_HAL_H__ ++#define __PCI_HAL_H__ ++ ++ ++#define INTEL_VENDOR_ID 0x8086 ++#define SIS_VENDOR_ID 0x1039 ++#define ATI_VENDOR_ID 0x1002 ++#define ATI_DEVICE_ID 0x7914 ++#define AMD_VENDOR_ID 0x1022 ++ ++#define PCI_MAX_BRIDGE_NUMBER 255 ++#define PCI_MAX_DEVICES 32 ++#define PCI_MAX_FUNCTION 8 ++ ++#define PCI_CONF_ADDRESS 0x0CF8 // PCI Configuration Space Address ++#define PCI_CONF_DATA 0x0CFC // PCI Configuration Space Data ++ ++#define PCI_CLASS_BRIDGE_DEV 0x06 ++#define PCI_SUBCLASS_BR_PCI_TO_PCI 0x04 ++ ++#define PCI_CAPABILITY_ID_PCI_EXPRESS 0x10 ++ ++#define U1DONTCARE 0xFF ++#define U2DONTCARE 0xFFFF ++#define U4DONTCARE 0xFFFFFFFF ++ ++#define PCI_VENDER_ID_REALTEK 0x10ec ++ ++#define HAL_HW_PCI_8180_DEVICE_ID 0x8180 ++#define HAL_HW_PCI_8185_DEVICE_ID 0x8185 //8185 or 8185b ++#define HAL_HW_PCI_8188_DEVICE_ID 0x8188 //8185b ++#define HAL_HW_PCI_8198_DEVICE_ID 0x8198 //8185b ++#define HAL_HW_PCI_8190_DEVICE_ID 0x8190 //8190 ++#define HAL_HW_PCI_8723E_DEVICE_ID 0x8723 //8723E ++#define HAL_HW_PCI_8192_DEVICE_ID 0x8192 //8192 PCI-E ++#define HAL_HW_PCI_8192SE_DEVICE_ID 0x8192 //8192 SE ++#define HAL_HW_PCI_8174_DEVICE_ID 0x8174 //8192 SE ++#define HAL_HW_PCI_8173_DEVICE_ID 0x8173 //8191 SE Crab ++#define HAL_HW_PCI_8172_DEVICE_ID 0x8172 //8191 SE RE ++#define HAL_HW_PCI_8171_DEVICE_ID 0x8171 //8191 SE Unicron ++#define HAL_HW_PCI_0045_DEVICE_ID 0x0045 //8190 PCI for Ceraga ++#define HAL_HW_PCI_0046_DEVICE_ID 0x0046 //8190 Cardbus for Ceraga ++#define HAL_HW_PCI_0044_DEVICE_ID 0x0044 //8192e PCIE for Ceraga ++#define HAL_HW_PCI_0047_DEVICE_ID 0x0047 //8192e Express Card for Ceraga ++#define HAL_HW_PCI_700F_DEVICE_ID 0x700F ++#define HAL_HW_PCI_701F_DEVICE_ID 0x701F ++#define HAL_HW_PCI_DLINK_DEVICE_ID 0x3304 ++#define HAL_HW_PCI_8192CET_DEVICE_ID 0x8191 //8192ce ++#define HAL_HW_PCI_8192CE_DEVICE_ID 0x8178 //8192ce ++#define HAL_HW_PCI_8191CE_DEVICE_ID 0x8177 //8192ce ++#define HAL_HW_PCI_8188CE_DEVICE_ID 0x8176 //8192ce ++#define HAL_HW_PCI_8192CU_DEVICE_ID 0x8191 //8192ce ++#define HAL_HW_PCI_8192DE_DEVICE_ID 0x8193 //8192de ++#define HAL_HW_PCI_002B_DEVICE_ID 0x002B //8192de, provided by HW SD ++ ++#define HAL_MEMORY_MAPPED_IO_RANGE_8190PCI 0x1000 //8190 support 16 pages of IO registers ++#define HAL_HW_PCI_REVISION_ID_8190PCI 0x00 ++#define HAL_MEMORY_MAPPED_IO_RANGE_8192PCIE 0x4000 //8192 support 16 pages of IO registers ++#define HAL_HW_PCI_REVISION_ID_8192PCIE 0x01 ++#define HAL_MEMORY_MAPPED_IO_RANGE_8192SE 0x4000 //8192 support 16 pages of IO registers ++#define HAL_HW_PCI_REVISION_ID_8192SE 0x10 ++#define HAL_HW_PCI_REVISION_ID_8192CE 0x1 ++#define HAL_MEMORY_MAPPED_IO_RANGE_8192CE 0x4000 //8192 support 16 pages of IO registers ++#define HAL_HW_PCI_REVISION_ID_8192DE 0x0 ++#define HAL_MEMORY_MAPPED_IO_RANGE_8192DE 0x4000 //8192 support 16 pages of IO registers ++ ++enum pci_bridge_vendor { ++ PCI_BRIDGE_VENDOR_INTEL = 0x0,//0b'0000,0001 ++ PCI_BRIDGE_VENDOR_ATI, //= 0x02,//0b'0000,0010 ++ PCI_BRIDGE_VENDOR_AMD, //= 0x04,//0b'0000,0100 ++ PCI_BRIDGE_VENDOR_SIS ,//= 0x08,//0b'0000,1000 ++ PCI_BRIDGE_VENDOR_UNKNOWN, //= 0x40,//0b'0100,0000 ++ PCI_BRIDGE_VENDOR_MAX ,//= 0x80 ++} ; ++ ++struct rt_pci_capabilities_header { ++ u8 capability_id; ++ u8 next; ++}; ++ ++struct pci_priv{ ++ u8 linkctrl_reg; ++ ++ u8 busnumber; ++ u8 devnumber; ++ u8 funcnumber; ++ ++ u8 pcibridge_busnum; ++ u8 pcibridge_devnum; ++ u8 pcibridge_funcnum; ++ u8 pcibridge_vendor; ++ u16 pcibridge_vendorid; ++ u16 pcibridge_deviceid; ++ u8 pcibridge_pciehdr_offset; ++ u8 pcibridge_linkctrlreg; ++ ++ u8 amd_l1_patch; ++}; ++ ++typedef struct _RT_ISR_CONTENT ++{ ++ union{ ++ u32 IntArray[2]; ++ u32 IntReg4Byte; ++ u16 IntReg2Byte; ++ }; ++}RT_ISR_CONTENT, *PRT_ISR_CONTENT; ++ ++//#define RegAddr(addr) (addr + 0xB2000000UL) ++//some platform macros will def here ++static inline void NdisRawWritePortUlong(u32 port, u32 val) ++{ ++ outl(val, port); ++ //writel(val, (u8 *)RegAddr(port)); ++} ++ ++static inline void NdisRawWritePortUchar(u32 port, u8 val) ++{ ++ outb(val, port); ++ //writeb(val, (u8 *)RegAddr(port)); ++} ++ ++static inline void NdisRawReadPortUchar(u32 port, u8 *pval) ++{ ++ *pval = inb(port); ++ //*pval = readb((u8 *)RegAddr(port)); ++} ++ ++static inline void NdisRawReadPortUshort(u32 port, u16 *pval) ++{ ++ *pval = inw(port); ++ //*pval = readw((u8 *)RegAddr(port)); ++} ++ ++static inline void NdisRawReadPortUlong(u32 port, u32 *pval) ++{ ++ *pval = inl(port); ++ //*pval = readl((u8 *)RegAddr(port)); ++} ++ ++#ifdef CONFIG_RTL8192C ++void rtl8192ce_set_hal_ops(_adapter * padapter); ++#endif ++#ifdef CONFIG_RTL8192D ++void rtl8192de_set_hal_ops(_adapter * padapter); ++#endif ++ ++#endif //__PCIE_HAL_H__ ++ +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/include/pci_ops.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/include/pci_ops.h 2013-07-26 19:36:06.000000000 +0000 +@@ -0,0 +1,58 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef __PCI_OPS_H_ ++#define __PCI_OPS_H_ ++ ++#include ++#include ++#include ++#include ++ ++#ifdef CONFIG_RTL8192C ++u32 rtl8192ce_init_desc_ring(_adapter * padapter); ++u32 rtl8192ce_free_desc_ring(_adapter * padapter); ++void rtl8192ce_reset_desc_ring(_adapter * padapter); ++#ifdef CONFIG_64BIT_DMA ++u8 PlatformEnable92CEDMA64(PADAPTER Adapter); ++#endif ++int rtl8192ce_interrupt(PADAPTER Adapter); ++void rtl8192ce_xmit_tasklet(void *priv); ++void rtl8192ce_recv_tasklet(void *priv); ++void rtl8192ce_prepare_bcn_tasklet(void *priv); ++void rtl8192ce_set_intf_ops(struct _io_ops *pops); ++#endif ++ ++#ifdef CONFIG_RTL8192D ++u32 rtl8192de_init_desc_ring(_adapter * padapter); ++u32 rtl8192de_free_desc_ring(_adapter * padapter); ++void rtl8192de_reset_desc_ring(_adapter * padapter); ++#ifdef CONFIG_64BIT_DMA ++u8 PlatformEnable92DEDMA64(PADAPTER Adapter); ++#endif ++int rtl8192de_interrupt(PADAPTER Adapter); ++void rtl8192de_xmit_tasklet(void *priv); ++void rtl8192de_recv_tasklet(void *priv); ++void rtl8192de_prepare_bcn_tasklet(void *priv); ++void rtl8192de_set_intf_ops(struct _io_ops *pops); ++u32 MpReadPCIDwordDBI8192D(IN PADAPTER Adapter, IN u16 Offset, IN u8 Direct); ++void MpWritePCIDwordDBI8192D(IN PADAPTER Adapter, IN u16 Offset, IN u32 Value, IN u8 Direct); ++#endif ++ ++#endif +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/include/pci_osintf.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/include/pci_osintf.h 2013-07-26 19:36:06.000000000 +0000 +@@ -0,0 +1,33 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef __PCI_OSINTF_H ++#define __PCI_OSINTF_H ++ ++#include ++#include ++#include ++ ++ ++void rtw_pci_disable_aspm(_adapter *padapter); ++void rtw_pci_enable_aspm(_adapter *padapter); ++ ++ ++#endif ++ +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/include/recv_osdep.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/include/recv_osdep.h 2013-07-26 19:36:06.000000000 +0000 +@@ -0,0 +1,58 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef __RECV_OSDEP_H_ ++#define __RECV_OSDEP_H_ ++ ++#include ++#include ++#include ++ ++ ++extern sint _rtw_init_recv_priv(struct recv_priv *precvpriv, _adapter *padapter); ++extern void _rtw_free_recv_priv (struct recv_priv *precvpriv); ++ ++ ++extern s32 rtw_recv_entry(union recv_frame *precv_frame); ++extern int rtw_recv_indicatepkt(_adapter *adapter, union recv_frame *precv_frame); ++extern void rtw_recv_returnpacket(IN _nic_hdl cnxt, IN _pkt *preturnedpkt); ++ ++extern void rtw_hostapd_mlme_rx(_adapter *padapter, union recv_frame *precv_frame); ++extern void rtw_handle_tkip_mic_err(_adapter *padapter,u8 bgroup); ++ ++ ++int rtw_init_recv_priv(struct recv_priv *precvpriv, _adapter *padapter); ++void rtw_free_recv_priv (struct recv_priv *precvpriv); ++ ++ ++int rtw_os_recv_resource_init(struct recv_priv *precvpriv, _adapter *padapter); ++int rtw_os_recv_resource_alloc(_adapter *padapter, union recv_frame *precvframe); ++void rtw_os_recv_resource_free(struct recv_priv *precvpriv); ++ ++ ++int rtw_os_recvbuf_resource_alloc(_adapter *padapter, struct recv_buf *precvbuf); ++int rtw_os_recvbuf_resource_free(_adapter *padapter, struct recv_buf *precvbuf); ++ ++void rtw_os_read_port(_adapter *padapter, struct recv_buf *precvbuf); ++ ++void rtw_init_recv_timer(struct recv_reorder_ctrl *preorder_ctrl); ++ ++ ++#endif // ++ +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/include/rtl8192c_cmd.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/include/rtl8192c_cmd.h 2013-07-26 19:36:06.000000000 +0000 +@@ -0,0 +1,153 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ++******************************************************************************/ ++#ifndef __RTL8192C_CMD_H_ ++#define __RTL8192C_CMD_H_ ++ ++ ++enum cmd_msg_element_id ++{ ++ NONE_CMDMSG_EID, ++ AP_OFFLOAD_EID=0, ++ SET_PWRMODE_EID=1, ++ JOINBSS_RPT_EID=2, ++ RSVD_PAGE_EID=3, ++ RSSI_4_EID = 4, ++ RSSI_SETTING_EID=5, ++ MACID_CONFIG_EID=6, ++ MACID_PS_MODE_EID=7, ++ P2P_PS_OFFLOAD_EID=8, ++ SELECTIVE_SUSPEND_ROF_CMD=9, ++ H2C_WO_WLAN_CMD = 26, // Wake on Wlan. ++ EXT_MACID_PERIOD_EID = 27, // support macid to 64 ++ MACID64_CONFIG_EID = 28, // support macid to 64 ++ P2P_PS_CTW_CMD_EID=32, ++ H2C_92C_IO_OFFLOAD=44, ++ KEEP_ALIVE_CONTROL_CMD=48, ++ DISCONNECT_DECISION_CTRL_CMD=49, ++ REMOTE_WAKE_CTRL_CMD=60, ++ H2C_92C_CMD_MAX}; ++ ++struct cmd_msg_parm { ++ u8 eid; //element id ++ u8 sz; // sz ++ u8 buf[6]; ++}; ++ ++enum evt_msg_element_id ++{ ++ EVT_DBG_EID=0, ++ EVT_TSF_EID=1, ++ EVT_AP_RPT_RSP_EID=2, ++ EVT_CCX_TXRPT_EID=3, ++ EVT_BT_RSSI_EID=4, ++ EVT_BT_OPMODE_EID=5, ++ EVT_EXT_RA_RPT_EID=6, ++ EVT_BT_TYPE_RPT_EID=7, ++ EVT_INIT_OFFLOAD_EID=8, ++ EVT_PSD_CONTROL_EID=9, ++ EVT_HW_INFO_EXCHGNGE_EID=10, ++ EVT_C2H_H2C_TEST_EID=11, ++ EVT_BT_INTO_EID=12, ++ EVT_BT_RPT_EID=13, ++ H2C_92C_EVT_MAX}; ++ ++ ++typedef struct _SETPWRMODE_PARM{ ++ u8 Mode; ++ u8 SmartPS; ++ u8 BcnPassTime; // unit: 100ms ++}SETPWRMODE_PARM, *PSETPWRMODE_PARM; ++ ++typedef struct _SETWOWLAN_PARM{ ++ u8 mode; ++ u8 gpio_index; ++ u8 gpio_duration; ++ u8 second_mode; ++ u8 reserve; ++}SETWOWLAN_PARM, *PSETWOWLAN_PARM; ++ ++#define FW_WOWLAN_FUN_EN BIT(0) ++#define FW_WOWLAN_PATTERN_MATCH BIT(1) ++#define FW_WOWLAN_MAGIC_PKT BIT(2) ++#define FW_WOWLAN_UNICAST BIT(3) ++#define FW_WOWLAN_ALL_PKT_DROP BIT(4) ++#define FW_WOWLAN_GPIO_ACTIVE BIT(5) ++#define FW_WOWLAN_REKEY_WAKEUP BIT(6) ++#define FW_WOWLAN_DEAUTH_WAKEUP BIT(7) ++ ++#define FW_WOWLAN_GPIO_WAKEUP_EN BIT(0) ++#define FW_FW_PARSE_MAGIC_PKT BIT(1) ++ ++struct H2C_SS_RFOFF_PARAM{ ++ u8 ROFOn; // 1: on, 0:off ++ u16 gpio_period; // unit: 1024 us ++}__attribute__ ((packed)); ++ ++ ++typedef struct JOINBSSRPT_PARM{ ++ u8 OpMode; // RT_MEDIA_STATUS ++}JOINBSSRPT_PARM, *PJOINBSSRPT_PARM; ++ ++typedef struct _RSVDPAGE_LOC{ ++ u8 LocProbeRsp; ++ u8 LocPsPoll; ++ u8 LocNullData; ++}RSVDPAGE_LOC, *PRSVDPAGE_LOC; ++ ++struct P2P_PS_Offload_t { ++ unsigned char Offload_En:1; ++ unsigned char role:1; // 1: Owner, 0: Client ++ unsigned char CTWindow_En:1; ++ unsigned char NoA0_En:1; ++ unsigned char NoA1_En:1; ++ unsigned char AllStaSleep:1; // Only valid in Owner ++ unsigned char discovery:1; ++ unsigned char rsvd:1; ++}; ++ ++struct P2P_PS_CTWPeriod_t { ++ unsigned char CTWPeriod; //TU ++}; ++ ++// host message to firmware cmd ++void rtl8192c_set_FwPwrMode_cmd(_adapter*padapter, u8 Mode); ++void rtl8192c_set_FwJoinBssReport_cmd(_adapter* padapter, u8 mstatus); ++u8 rtl8192c_set_rssi_cmd(_adapter*padapter, u8 *param); ++u8 rtl8192c_set_raid_cmd(_adapter*padapter, u32 mask, u8 arg); ++u8 rtl8192c_set_raid64_cmd(_adapter*padapter, u32 mask, u8 arg); ++void rtl8192c_Add_RateATid(PADAPTER pAdapter, u32 bitmap, u8 arg, u8 mac_id); ++u8 rtl8192c_set_FwSelectSuspend_cmd(_adapter*padapter,u8 bfwpoll, u16 period); ++#ifdef CONFIG_P2P ++void rtl8192c_set_p2p_ps_offload_cmd(_adapter* padapter, u8 p2p_ps_state); ++#endif //CONFIG_P2P ++ ++#ifdef CONFIG_IOL ++typedef struct _IO_OFFLOAD_LOC{ ++ u8 LocCmd; ++}IO_OFFLOAD_LOC, *PIO_OFFLOAD_LOC; ++int rtl8192c_IOL_exec_cmds_sync(ADAPTER *adapter, struct xmit_frame *xmit_frame, u32 max_wating_ms); ++#endif //CONFIG_IOL ++ ++#endif ++#ifdef CONFIG_WOWLAN ++void rtl8192c_set_wowlan_cmd(_adapter* padapter); ++void SetFwRelatedForWoWLAN8192CU(_adapter* padapter,u8 bHostIsGoingtoSleep); ++#endif // CONFIG_WOWLAN +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/include/rtl8192c_dm.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/include/rtl8192c_dm.h 2013-07-26 19:36:06.000000000 +0000 +@@ -0,0 +1,616 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ++******************************************************************************/ ++#ifndef __RTL8192C_DM_H__ ++#define __RTL8192C_DM_H__ ++//============================================================ ++// Description: ++// ++// This file is for 92CE/92CU dynamic mechanism only ++// ++// ++//============================================================ ++ ++#define RSSI_CCK 0 ++#define RSSI_OFDM 1 ++#define RSSI_DEFAULT 2 ++ ++#define OFDM_TABLE_SIZE 37 ++#define CCK_TABLE_SIZE 33 ++ ++static u32 OFDMSwingTable[OFDM_TABLE_SIZE] = { ++ 0x7f8001fe, // 0, +6.0dB ++ 0x788001e2, // 1, +5.5dB ++ 0x71c001c7, // 2, +5.0dB ++ 0x6b8001ae, // 3, +4.5dB ++ 0x65400195, // 4, +4.0dB ++ 0x5fc0017f, // 5, +3.5dB ++ 0x5a400169, // 6, +3.0dB ++ 0x55400155, // 7, +2.5dB ++ 0x50800142, // 8, +2.0dB ++ 0x4c000130, // 9, +1.5dB ++ 0x47c0011f, // 10, +1.0dB ++ 0x43c0010f, // 11, +0.5dB ++ 0x40000100, // 12, +0dB ++ 0x3c8000f2, // 13, -0.5dB ++ 0x390000e4, // 14, -1.0dB ++ 0x35c000d7, // 15, -1.5dB ++ 0x32c000cb, // 16, -2.0dB ++ 0x300000c0, // 17, -2.5dB ++ 0x2d4000b5, // 18, -3.0dB ++ 0x2ac000ab, // 19, -3.5dB ++ 0x288000a2, // 20, -4.0dB ++ 0x26000098, // 21, -4.5dB ++ 0x24000090, // 22, -5.0dB ++ 0x22000088, // 23, -5.5dB ++ 0x20000080, // 24, -6.0dB ++ 0x1e400079, // 25, -6.5dB ++ 0x1c800072, // 26, -7.0dB ++ 0x1b00006c, // 27. -7.5dB ++ 0x19800066, // 28, -8.0dB ++ 0x18000060, // 29, -8.5dB ++ 0x16c0005b, // 30, -9.0dB ++ 0x15800056, // 31, -9.5dB ++ 0x14400051, // 32, -10.0dB ++ 0x1300004c, // 33, -10.5dB ++ 0x12000048, // 34, -11.0dB ++ 0x11000044, // 35, -11.5dB ++ 0x10000040, // 36, -12.0dB ++}; ++ ++static u8 CCKSwingTable_Ch1_Ch13[CCK_TABLE_SIZE][8] = { ++{0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04}, // 0, +0dB ++{0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04}, // 1, -0.5dB ++{0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03}, // 2, -1.0dB ++{0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03}, // 3, -1.5dB ++{0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03}, // 4, -2.0dB ++{0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03}, // 5, -2.5dB ++{0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03}, // 6, -3.0dB ++{0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03}, // 7, -3.5dB ++{0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02}, // 8, -4.0dB ++{0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02}, // 9, -4.5dB ++{0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02}, // 10, -5.0dB ++{0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02}, // 11, -5.5dB ++{0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02}, // 12, -6.0dB ++{0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02}, // 13, -6.5dB ++{0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02}, // 14, -7.0dB ++{0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02}, // 15, -7.5dB ++{0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01}, // 16, -8.0dB ++{0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02}, // 17, -8.5dB ++{0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01}, // 18, -9.0dB ++{0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, // 19, -9.5dB ++{0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01}, // 20, -10.0dB ++{0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01}, // 21, -10.5dB ++{0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01}, // 22, -11.0dB ++{0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01}, // 23, -11.5dB ++{0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01}, // 24, -12.0dB ++{0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01}, // 25, -12.5dB ++{0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01}, // 26, -13.0dB ++{0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01}, // 27, -13.5dB ++{0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01}, // 28, -14.0dB ++{0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01}, // 29, -14.5dB ++{0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01}, // 30, -15.0dB ++{0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01}, // 31, -15.5dB ++{0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01} // 32, -16.0dB ++}; ++ ++static u8 CCKSwingTable_Ch14 [CCK_TABLE_SIZE][8]= { ++{0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00}, // 0, +0dB ++{0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00}, // 1, -0.5dB ++{0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00}, // 2, -1.0dB ++{0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00}, // 3, -1.5dB ++{0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00}, // 4, -2.0dB ++{0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00}, // 5, -2.5dB ++{0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00}, // 6, -3.0dB ++{0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00}, // 7, -3.5dB ++{0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00}, // 8, -4.0dB ++{0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00}, // 9, -4.5dB ++{0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00}, // 10, -5.0dB ++{0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00}, // 11, -5.5dB ++{0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00}, // 12, -6.0dB ++{0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00}, // 13, -6.5dB ++{0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00}, // 14, -7.0dB ++{0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00}, // 15, -7.5dB ++{0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00}, // 16, -8.0dB ++{0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00}, // 17, -8.5dB ++{0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00}, // 18, -9.0dB ++{0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, // 19, -9.5dB ++{0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00}, // 20, -10.0dB ++{0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00}, // 21, -10.5dB ++{0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00}, // 22, -11.0dB ++{0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, // 23, -11.5dB ++{0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00}, // 24, -12.0dB ++{0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00}, // 25, -12.5dB ++{0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, // 26, -13.0dB ++{0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00}, // 27, -13.5dB ++{0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, // 28, -14.0dB ++{0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00}, // 29, -14.5dB ++{0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, // 30, -15.0dB ++{0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00}, // 31, -15.5dB ++{0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00} // 32, -16.0dB ++}; ++ ++//============================================================ ++// structure and define ++//============================================================ ++ ++typedef struct _FALSE_ALARM_STATISTICS{ ++ u32 Cnt_Parity_Fail; ++ u32 Cnt_Rate_Illegal; ++ u32 Cnt_Crc8_fail; ++ u32 Cnt_Mcs_fail; ++ u32 Cnt_Ofdm_fail; ++ u32 Cnt_Cck_fail; ++ u32 Cnt_all; ++ u32 Cnt_Fast_Fsync; ++ u32 Cnt_SB_Search_fail; ++}FALSE_ALARM_STATISTICS, *PFALSE_ALARM_STATISTICS; ++ ++typedef struct _Dynamic_Power_Saving_ ++{ ++ u8 PreCCAState; ++ u8 CurCCAState; ++ ++ u8 PreRFState; ++ u8 CurRFState; ++ ++ s32 Rssi_val_min; ++ ++}PS_T; ++ ++typedef struct _Dynamic_Initial_Gain_Threshold_ ++{ ++ u8 Dig_Enable_Flag; ++ u8 Dig_Ext_Port_Stage; ++ ++ int RssiLowThresh; ++ int RssiHighThresh; ++ ++ u32 FALowThresh; ++ u32 FAHighThresh; ++ ++ u8 CurSTAConnectState; ++ u8 PreSTAConnectState; ++ u8 CurMultiSTAConnectState; ++ ++ u8 PreIGValue; ++ u8 CurIGValue; ++ u8 BackupIGValue; ++ ++ char BackoffVal; ++ char BackoffVal_range_max; ++ char BackoffVal_range_min; ++ u8 rx_gain_range_max; ++ u8 rx_gain_range_min; ++ u8 Rssi_val_min; ++ ++ u8 PreCCKPDState; ++ u8 CurCCKPDState; ++ u8 PreCCKFAState; ++ u8 CurCCKFAState; ++ u8 PreCCAState; ++ u8 CurCCAState; ++ ++ u8 LargeFAHit; ++ u8 ForbiddenIGI; ++ u32 Recover_cnt; ++ ++}DIG_T; ++ ++typedef enum tag_Dynamic_Init_Gain_Operation_Type_Definition ++{ ++ DIG_TYPE_THRESH_HIGH = 0, ++ DIG_TYPE_THRESH_LOW = 1, ++ DIG_TYPE_BACKOFF = 2, ++ DIG_TYPE_RX_GAIN_MIN = 3, ++ DIG_TYPE_RX_GAIN_MAX = 4, ++ DIG_TYPE_ENABLE = 5, ++ DIG_TYPE_DISABLE = 6, ++ DIG_OP_TYPE_MAX ++}DM_DIG_OP_E; ++ ++typedef enum tag_CCK_Packet_Detection_Threshold_Type_Definition ++{ ++ CCK_PD_STAGE_LowRssi = 0, ++ CCK_PD_STAGE_HighRssi = 1, ++ CCK_PD_STAGE_MAX = 3, ++}DM_CCK_PDTH_E; ++ ++typedef enum tag_1R_CCA_Type_Definition ++{ ++ CCA_1R =0, ++ CCA_2R = 1, ++ CCA_MAX = 2, ++}DM_1R_CCA_E; ++ ++typedef enum tag_RF_Type_Definition ++{ ++ RF_Save =0, ++ RF_Normal = 1, ++ RF_MAX = 2, ++}DM_RF_E; ++ ++typedef enum tag_DIG_EXT_PORT_ALGO_Definition ++{ ++ DIG_EXT_PORT_STAGE_0 = 0, ++ DIG_EXT_PORT_STAGE_1 = 1, ++ DIG_EXT_PORT_STAGE_2 = 2, ++ DIG_EXT_PORT_STAGE_3 = 3, ++ DIG_EXT_PORT_STAGE_MAX = 4, ++}DM_DIG_EXT_PORT_ALG_E; ++ ++ ++typedef enum tag_DIG_Connect_Definition ++{ ++ DIG_STA_DISCONNECT = 0, ++ DIG_STA_CONNECT = 1, ++ DIG_STA_BEFORE_CONNECT = 2, ++ DIG_MultiSTA_DISCONNECT = 3, ++ DIG_MultiSTA_CONNECT = 4, ++ DIG_CONNECT_MAX ++}DM_DIG_CONNECT_E; ++ ++ ++ ++typedef enum _BT_Ant_NUM{ ++ Ant_x2 = 0, ++ Ant_x1 = 1 ++} BT_Ant_NUM, *PBT_Ant_NUM; ++ ++typedef enum _BT_CoType{ ++ BT_2Wire = 0, ++ BT_ISSC_3Wire = 1, ++ BT_Accel = 2, ++ BT_CSR_BC4 = 3, ++ BT_CSR_BC8 = 4, ++ BT_RTL8756 = 5, ++} BT_CoType, *PBT_CoType; ++ ++typedef enum _BT_CurState{ ++ BT_OFF = 0, ++ BT_ON = 1, ++} BT_CurState, *PBT_CurState; ++ ++typedef enum _BT_ServiceType{ ++ BT_SCO = 0, ++ BT_A2DP = 1, ++ BT_HID = 2, ++ BT_HID_Idle = 3, ++ BT_Scan = 4, ++ BT_Idle = 5, ++ BT_OtherAction = 6, ++ BT_Busy = 7, ++ BT_OtherBusy = 8, ++ BT_PAN = 9, ++} BT_ServiceType, *PBT_ServiceType; ++ ++typedef enum _BT_RadioShared{ ++ BT_Radio_Shared = 0, ++ BT_Radio_Individual = 1, ++} BT_RadioShared, *PBT_RadioShared; ++ ++struct btcoexist_priv { ++ u8 BT_Coexist; ++ u8 BT_Ant_Num; ++ u8 BT_CoexistType; ++ u8 BT_State; ++ u8 BT_CUR_State; //0:on, 1:off ++ u8 BT_Ant_isolation; //0:good, 1:bad ++ u8 BT_PapeCtrl; //0:SW, 1:SW/HW dynamic ++ u8 BT_Service; ++ u8 BT_Ampdu; // 0:Disable BT control A-MPDU, 1:Enable BT control A-MPDU. ++ u8 BT_RadioSharedType; ++ u32 Ratio_Tx; ++ u32 Ratio_PRI; ++ u8 BtRfRegOrigin1E; ++ u8 BtRfRegOrigin1F; ++ u8 BtRssiState; ++ u32 BtEdcaUL; ++ u32 BtEdcaDL; ++ u32 BT_EDCA[2]; ++ u8 bCOBT; ++ ++ u8 bInitSet; ++ u8 bBTBusyTraffic; ++ u8 bBTTrafficModeSet; ++ u8 bBTNonTrafficModeSet; ++ //BTTraffic BT21TrafficStatistics; ++ u32 CurrentState; ++ u32 PreviousState; ++ u8 BtPreRssiState; ++ u8 bFWCoexistAllOff; ++ u8 bSWCoexistAllOff; ++}; ++ ++#define BW_AUTO_SWITCH_HIGH_LOW 25 ++#define BW_AUTO_SWITCH_LOW_HIGH 30 ++ ++#define DM_DIG_THRESH_HIGH 40 ++#define DM_DIG_THRESH_LOW 35 ++ ++#define DM_FALSEALARM_THRESH_LOW 400 ++#define DM_FALSEALARM_THRESH_HIGH 1000 ++ ++#define DM_DIG_MAX 0x3e ++#define DM_DIG_MIN 0x1e //0x22//0x1c ++ ++#define DM_DIG_FA_UPPER 0x32 ++#define DM_DIG_FA_LOWER 0x20 ++#define DM_DIG_FA_TH0 0x20 ++#define DM_DIG_FA_TH1 0x100 ++#define DM_DIG_FA_TH2 0x200 ++ ++#define DM_DIG_BACKOFF_MAX 12 ++#define DM_DIG_BACKOFF_MIN (-4) ++#define DM_DIG_BACKOFF_DEFAULT 10 ++ ++#define RxPathSelection_SS_TH_low 30 ++#define RxPathSelection_diff_TH 18 ++ ++#define DM_RATR_STA_INIT 0 ++#define DM_RATR_STA_HIGH 1 ++#define DM_RATR_STA_MIDDLE 2 ++#define DM_RATR_STA_LOW 3 ++ ++#define CTSToSelfTHVal 30 ++#define RegC38_TH 20 ++ ++#define WAIotTHVal 25 ++ ++//Dynamic Tx Power Control Threshold ++#define TX_POWER_NEAR_FIELD_THRESH_LVL2 74 ++#define TX_POWER_NEAR_FIELD_THRESH_LVL1 67 ++ ++#define TxHighPwrLevel_Normal 0 ++#define TxHighPwrLevel_Level1 1 ++#define TxHighPwrLevel_Level2 2 ++#define TxHighPwrLevel_BT1 3 ++#define TxHighPwrLevel_BT2 4 ++#define TxHighPwrLevel_15 5 ++#define TxHighPwrLevel_35 6 ++#define TxHighPwrLevel_50 7 ++#define TxHighPwrLevel_70 8 ++#define TxHighPwrLevel_100 9 ++ ++#define DM_Type_ByFW 0 ++#define DM_Type_ByDriver 1 ++ ++ ++typedef struct _RATE_ADAPTIVE ++{ ++ u8 RateAdaptiveDisabled; ++ u8 RATRState; ++ u16 reserve; ++ ++ u32 HighRSSIThreshForRA; ++ u32 High2LowRSSIThreshForRA; ++ u8 Low2HighRSSIThreshForRA40M; ++ u32 LowRSSIThreshForRA40M; ++ u8 Low2HighRSSIThreshForRA20M; ++ u32 LowRSSIThreshForRA20M; ++ u32 UpperRSSIThresholdRATR; ++ u32 MiddleRSSIThresholdRATR; ++ u32 LowRSSIThresholdRATR; ++ u32 LowRSSIThresholdRATR40M; ++ u32 LowRSSIThresholdRATR20M; ++ u8 PingRSSIEnable; //cosa add for Netcore long range ping issue ++ u32 PingRSSIRATR; //cosa add for Netcore long range ping issue ++ u32 PingRSSIThreshForRA;//cosa add for Netcore long range ping issue ++ u32 LastRATR; ++ u8 PreRATRState; ++ ++} RATE_ADAPTIVE, *PRATE_ADAPTIVE; ++ ++typedef enum tag_SW_Antenna_Switch_Definition ++{ ++ Antenna_B = 1, ++ Antenna_A = 2, ++ Antenna_MAX = 3, ++}DM_SWAS_E; ++ ++#ifdef CONFIG_ANTENNA_DIVERSITY ++// This indicates two different the steps. ++// In SWAW_STEP_PEAK, driver needs to switch antenna and listen to the signal on the air. ++// In SWAW_STEP_DETERMINE, driver just compares the signal captured in SWAW_STEP_PEAK ++// with original RSSI to determine if it is necessary to switch antenna. ++#define SWAW_STEP_PEAK 0 ++#define SWAW_STEP_DETERMINE 1 ++ ++#define TP_MODE 0 ++#define RSSI_MODE 1 ++#define TRAFFIC_LOW 0 ++#define TRAFFIC_HIGH 1 ++ ++typedef struct _SW_Antenna_Switch_ ++{ ++ u8 try_flag; ++ s32 PreRSSI; ++ u8 CurAntenna; ++ u8 PreAntenna; ++ u8 RSSI_Trying; ++ u8 TestMode; ++ u8 bTriggerAntennaSwitch; ++ u8 SelectAntennaMap; ++ // Before link Antenna Switch check ++ u8 SWAS_NoLink_State; ++ ++}SWAT_T; ++ ++ ++#endif ++ ++ ++struct dm_priv ++{ ++ u8 DM_Type; ++ u8 DMFlag, DMFlag_tmp; ++ ++ ++ //for DIG ++ u8 bDMInitialGainEnable; ++ u8 binitialized; // for dm_initial_gain_Multi_STA use. ++ DIG_T DM_DigTable; ++ ++ PS_T DM_PSTable; ++ ++ FALSE_ALARM_STATISTICS FalseAlmCnt; ++ ++ //for rate adaptive, in fact, 88c/92c fw will handle this ++ u8 bUseRAMask; ++ RATE_ADAPTIVE RateAdaptive; ++ ++ //* Upper and Lower Signal threshold for Rate Adaptive*/ ++ int UndecoratedSmoothedPWDB; ++ int UndecoratedSmoothedCCK; ++ int EntryMinUndecoratedSmoothedPWDB; ++ int EntryMaxUndecoratedSmoothedPWDB; ++ ++ ++ //for High Power ++ u8 bDynamicTxPowerEnable; ++ u8 LastDTPLvl; ++ u8 DynamicTxHighPowerLvl;//Add by Jacken Tx Power Control for Near/Far Range 2008/03/06 ++ ++ //for tx power tracking ++ //u8 bTXPowerTracking; ++ u8 TXPowercount; ++ u8 bTXPowerTrackingInit; ++ u8 TxPowerTrackControl; //for mp mode, turn off txpwrtracking as default ++ u8 TM_Trigger; ++ ++ u8 ThermalMeter[2]; // ThermalMeter, index 0 for RFIC0, and 1 for RFIC1 ++ u8 ThermalValue; ++ u8 ThermalValue_LCK; ++ u8 ThermalValue_IQK; ++ u8 ThermalValue_DPK; ++ ++ u8 bRfPiEnable; ++ ++ //for APK ++ u32 APKoutput[2][2]; //path A/B; output1_1a/output1_2a ++ u8 bAPKdone; ++ u8 bAPKThermalMeterIgnore; ++ u8 bDPdone; ++ u8 bDPPathAOK; ++ u8 bDPPathBOK; ++ ++ //for IQK ++ u32 RegC04; ++ u32 Reg874; ++ u32 RegC08; ++ u32 RegB68; ++ u32 RegB6C; ++ u32 Reg870; ++ u32 Reg860; ++ u32 Reg864; ++ u32 ADDA_backup[IQK_ADDA_REG_NUM]; ++ u32 IQK_MAC_backup[IQK_MAC_REG_NUM]; ++ u32 IQK_BB_backup_recover[9]; ++ u32 IQK_BB_backup[IQK_BB_REG_NUM]; ++ u8 PowerIndex_backup[6]; ++ ++ u8 bCCKinCH14; ++ ++ char CCK_index; ++ char OFDM_index[2]; ++ ++ BOOLEAN bDoneTxpower; ++ char CCK_index_HP; ++ char OFDM_index_HP[2]; ++ u8 ThermalValue_HP[HP_THERMAL_NUM]; ++ u8 ThermalValue_HP_index; ++ ++ //for TxPwrTracking ++ int RegE94; ++ int RegE9C; ++ int RegEB4; ++ int RegEBC; ++ ++ u32 TXPowerTrackingCallbackCnt; //cosa add for debug ++ ++ u32 prv_traffic_idx; // edca turbo ++ ++ // for dm_RF_Saving ++ u8 initialize; ++ u32 rf_saving_Reg874; ++ u32 rf_saving_RegC70; ++ u32 rf_saving_Reg85C; ++ u32 rf_saving_RegA74; ++ ++ //for Antenna diversity ++#ifdef CONFIG_ANTENNA_DIVERSITY ++ SWAT_T DM_SWAT_Table; ++#endif ++#ifdef CONFIG_SW_ANTENNA_DIVERSITY ++ _timer SwAntennaSwitchTimer; ++ ++ u64 lastTxOkCnt; ++ u64 lastRxOkCnt; ++ u64 TXByteCnt_A; ++ u64 TXByteCnt_B; ++ u64 RXByteCnt_A; ++ u64 RXByteCnt_B; ++ u8 DoubleComfirm; ++ u8 TrafficLoad; ++#endif ++ ++ s32 OFDM_Pkt_Cnt; ++ u8 RSSI_Select; ++ u8 DIG_Dynamic_MIN ; ++ ++ // Add for Reading Initial Data Rate SEL Register 0x484 during watchdog. Using for fill tx desc. 2011.3.21 by Thomas ++ u8 INIDATA_RATE[32]; ++}; ++ ++ ++/*------------------------Export global variable----------------------------*/ ++/*------------------------Export global variable----------------------------*/ ++/*------------------------Export Marco Definition---------------------------*/ ++//#define DM_MultiSTA_InitGainChangeNotify(Event) {DM_DigTable.CurMultiSTAConnectState = Event;} ++ ++ ++//============================================================ ++// function prototype ++//============================================================ ++void rtl8192c_init_dm_priv(IN PADAPTER Adapter); ++void rtl8192c_deinit_dm_priv(IN PADAPTER Adapter); ++void rtl8192c_InitHalDm(IN PADAPTER Adapter); ++void rtl8192c_HalDmWatchDog(IN PADAPTER Adapter); ++ ++VOID rtl8192c_dm_CheckTXPowerTracking(IN PADAPTER Adapter); ++ ++void rtl8192c_dm_RF_Saving(IN PADAPTER pAdapter, IN u8 bForceInNormal); ++ ++#ifdef CONFIG_BT_COEXIST ++void rtl8192c_set_dm_bt_coexist(_adapter *padapter, u8 bStart); ++void rtl8192c_issue_delete_ba(_adapter *padapter, u8 dir); ++#endif ++ ++#ifdef CONFIG_SW_ANTENNA_DIVERSITY ++void SwAntDivRSSICheck8192C(_adapter *padapter ,u32 RxPWDBAll); ++void SwAntDivRestAfterLink8192C(IN PADAPTER Adapter); ++#endif ++#ifdef CONFIG_ANTENNA_DIVERSITY ++void SwAntDivCompare8192C(PADAPTER Adapter, WLAN_BSSID_EX *dst, WLAN_BSSID_EX *src); ++u8 SwAntDivBeforeLink8192C(IN PADAPTER Adapter); ++#endif ++ ++#endif //__HAL8190PCIDM_H__ ++ +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/include/rtl8192c_event.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/include/rtl8192c_event.h 2013-07-26 19:36:06.000000000 +0000 +@@ -0,0 +1,29 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ++******************************************************************************/ ++#ifndef _RTL8192C_EVENT_H_ ++#define _RTL8192C_EVENT_H_ ++ ++ ++ ++ ++#endif ++ ++ +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/include/rtl8192c_hal.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/include/rtl8192c_hal.h 2013-07-26 19:36:06.000000000 +0000 +@@ -0,0 +1,887 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ++******************************************************************************/ ++#ifndef __RTL8192C_HAL_H__ ++#define __RTL8192C_HAL_H__ ++ ++#include "rtl8192c_spec.h" ++#include "Hal8192CPhyReg.h" ++#include "Hal8192CPhyCfg.h" ++#include "rtl8192c_rf.h" ++#include "rtl8192c_dm.h" ++#include "rtl8192c_recv.h" ++#include "rtl8192c_xmit.h" ++#include "rtl8192c_cmd.h" ++#ifdef DBG_CONFIG_ERROR_DETECT ++#include "rtl8192c_sreset.h" ++#endif ++ ++#ifdef CONFIG_PCI_HCI ++ ++ #include "Hal8192CEHWImg.h" ++ ++ #define RTL819X_DEFAULT_RF_TYPE RF_2T2R ++ //#define RTL819X_DEFAULT_RF_TYPE RF_1T2R ++ #define RTL819X_TOTAL_RF_PATH 2 ++ ++ //2TODO: The following need to check!! ++ #define RTL8192C_FW_TSMC_IMG "rtl8192CE\\rtl8192cfwT.bin" ++ #define RTL8192C_FW_UMC_IMG "rtl8192CE\\rtl8192cfwU.bin" ++ #define RTL8192C_FW_UMC_B_IMG "rtl8192CE\\rtl8192cfwU_B.bin" ++ ++ #define RTL8188C_PHY_REG "rtl8192CE\\PHY_REG_1T.txt" ++ #define RTL8188C_PHY_RADIO_A "rtl8192CE\\radio_a_1T.txt" ++ #define RTL8188C_PHY_RADIO_B "rtl8192CE\\radio_b_1T.txt" ++ #define RTL8188C_AGC_TAB "rtl8192CE\\AGC_TAB_1T.txt" ++ #define RTL8188C_PHY_MACREG "rtl8192CE\\MACREG_1T.txt" ++ ++ #define RTL8192C_PHY_REG "rtl8192CE\\PHY_REG_2T.txt" ++ #define RTL8192C_PHY_RADIO_A "rtl8192CE\\radio_a_2T.txt" ++ #define RTL8192C_PHY_RADIO_B "rtl8192CE\\radio_b_2T.txt" ++ #define RTL8192C_AGC_TAB "rtl8192CE\\AGC_TAB_2T.txt" ++ #define RTL8192C_PHY_MACREG "rtl8192CE\\MACREG_2T.txt" ++ ++ #define RTL819X_PHY_MACPHY_REG "rtl8192CE\\MACPHY_reg.txt" ++ #define RTL819X_PHY_MACPHY_REG_PG "rtl8192CE\\MACPHY_reg_PG.txt" ++ #define RTL819X_PHY_MACREG "rtl8192CE\\MAC_REG.txt" ++ #define RTL819X_PHY_REG "rtl8192CE\\PHY_REG.txt" ++ #define RTL819X_PHY_REG_1T2R "rtl8192CE\\PHY_REG_1T2R.txt" ++ #define RTL819X_PHY_REG_to1T1R "rtl8192CE\\phy_to1T1R_a.txt" ++ #define RTL819X_PHY_REG_to1T2R "rtl8192CE\\phy_to1T2R.txt" ++ #define RTL819X_PHY_REG_to2T2R "rtl8192CE\\phy_to2T2R.txt" ++ #define RTL819X_PHY_REG_PG "rtl8192CE\\PHY_REG_PG.txt" ++ #define RTL819X_AGC_TAB "rtl8192CE\\AGC_TAB.txt" ++ #define RTL819X_PHY_RADIO_A "rtl8192CE\\radio_a.txt" ++ #define RTL819X_PHY_RADIO_A_1T "rtl8192CE\\radio_a_1t.txt" ++ #define RTL819X_PHY_RADIO_A_2T "rtl8192CE\\radio_a_2t.txt" ++ #define RTL819X_PHY_RADIO_B "rtl8192CE\\radio_b.txt" ++ #define RTL819X_PHY_RADIO_B_GM "rtl8192CE\\radio_b_gm.txt" ++ #define RTL819X_PHY_RADIO_C "rtl8192CE\\radio_c.txt" ++ #define RTL819X_PHY_RADIO_D "rtl8192CE\\radio_d.txt" ++ #define RTL819X_EEPROM_MAP "rtl8192CE\\8192ce.map" ++ #define RTL819X_EFUSE_MAP "rtl8192CE\\8192ce.map" ++ ++//--------------------------------------------------------------------- ++// RTL8723E From file ++//--------------------------------------------------------------------- ++ #define RTL8723_FW_UMC_IMG "rtl8723E\\rtl8723fw.bin" ++ #define RTL8723_PHY_REG "rtl8723E\\PHY_REG_1T.txt" ++ #define RTL8723_PHY_RADIO_A "rtl8723E\\radio_a_1T.txt" ++ #define RTL8723_PHY_RADIO_B "rtl8723E\\radio_b_1T.txt" ++ #define RTL8723_AGC_TAB "rtl8723E\\AGC_TAB_1T.txt" ++ #define RTL8723_PHY_MACREG "rtl8723E\\MAC_REG.txt" ++ #define RTL8723_PHY_MACREG "rtl8723E\\MAC_REG.txt" ++ #define RTL8723_PHY_REG_PG "rtl8723E\\PHY_REG_PG.txt" ++ #define RTL8723_PHY_REG_MP "rtl8723E\\PHY_REG_MP.txt" ++ ++ // The file name "_2T" is for 92CE, "_1T" is for 88CE. Modified by tynli. 2009.11.24. ++ #define Rtl819XFwTSMCImageArray Rtl8192CEFwTSMCImgArray ++ #define Rtl819XFwUMCACutImageArray Rtl8192CEFwUMCACutImgArray ++ #define Rtl819XFwUMCBCutImageArray Rtl8192CEFwUMCBCutImgArray ++ ++ #define Rtl8723FwUMCImageArray Rtl8192CEFwUMC8723ImgArray ++ #define Rtl819XMAC_Array Rtl8192CEMAC_2T_Array ++ #define Rtl819XAGCTAB_2TArray Rtl8192CEAGCTAB_2TArray ++ #define Rtl819XAGCTAB_1TArray Rtl8192CEAGCTAB_1TArray ++ #define Rtl819XPHY_REG_2TArray Rtl8192CEPHY_REG_2TArray ++ #define Rtl819XPHY_REG_1TArray Rtl8192CEPHY_REG_1TArray ++ #define Rtl819XRadioA_2TArray Rtl8192CERadioA_2TArray ++ #define Rtl819XRadioA_1TArray Rtl8192CERadioA_1TArray ++ #define Rtl819XRadioB_2TArray Rtl8192CERadioB_2TArray ++ #define Rtl819XRadioB_1TArray Rtl8192CERadioB_1TArray ++ #define Rtl819XPHY_REG_Array_PG Rtl8192CEPHY_REG_Array_PG ++ #define Rtl819XPHY_REG_Array_MP Rtl8192CEPHY_REG_Array_MP ++ ++#elif defined(CONFIG_USB_HCI) ++ ++ #include "Hal8192CUHWImg.h" ++#ifdef CONFIG_WOWLAN ++ #include "Hal8192CUHWImg_wowlan.h" ++#endif //CONFIG_WOWLAN ++ //2TODO: We should define 8192S firmware related macro settings here!! ++ #define RTL819X_DEFAULT_RF_TYPE RF_1T2R ++ #define RTL819X_TOTAL_RF_PATH 2 ++ ++ //TODO: The following need to check!! ++ #define RTL8192C_FW_TSMC_IMG "rtl8192CU\\rtl8192cfwT.bin" ++ #define RTL8192C_FW_UMC_IMG "rtl8192CU\\rtl8192cfwU.bin" ++ #define RTL8192C_FW_UMC_B_IMG "rtl8192CU\\rtl8192cfwU_B.bin" ++ #define RTL8192C_FW_TSMC_WW_IMG "rtl8192CU\\rtl8192cfwTww.bin" ++ #define RTL8192C_FW_UMC_WW_IMG "rtl8192CU\\rtl8192cfwUww.bin" ++ #define RTL8192C_FW_UMC_B_WW_IMG "rtl8192CU\\rtl8192cfwU_Bww.bin" ++ //#define RTL819X_FW_BOOT_IMG "rtl8192CU\\boot.img" ++ //#define RTL819X_FW_MAIN_IMG "rtl8192CU\\main.img" ++ //#define RTL819X_FW_DATA_IMG "rtl8192CU\\data.img" ++ ++ #define RTL8188C_PHY_REG "rtl8188CU\\PHY_REG.txt" ++ #define RTL8188C_PHY_RADIO_A "rtl8188CU\\radio_a.txt" ++ #define RTL8188C_PHY_RADIO_B "rtl8188CU\\radio_b.txt" ++ #define RTL8188C_PHY_RADIO_A_mCard "rtl8192CU\\radio_a_1T_mCard.txt" ++ #define RTL8188C_PHY_RADIO_B_mCard "rtl8192CU\\radio_b_1T_mCard.txt" ++ #define RTL8188C_PHY_RADIO_A_HP "rtl8192CU\\radio_a_1T_HP.txt" ++ #define RTL8188C_AGC_TAB "rtl8188CU\\AGC_TAB.txt" ++ #define RTL8188C_PHY_MACREG "rtl8188CU\\MACREG.txt" ++ ++ #define RTL8192C_PHY_REG "rtl8192CU\\PHY_REG.txt" ++ #define RTL8192C_PHY_RADIO_A "rtl8192CU\\radio_a.txt" ++ #define RTL8192C_PHY_RADIO_B "rtl8192CU\\radio_b.txt" ++ #define RTL8192C_AGC_TAB "rtl8192CU\\AGC_TAB.txt" ++ #define RTL8192C_PHY_MACREG "rtl8192CU\\MACREG.txt" ++ ++ #define RTL819X_PHY_REG_PG "rtl8192CU\\PHY_REG_PG.txt" ++ ++//--------------------------------------------------------------------- ++// RTL8723U From file ++//--------------------------------------------------------------------- ++ #define RTL8723_FW_UMC_IMG "rtl8723U\\rtl8723fw.bin" ++ #define RTL8723_PHY_REG "rtl8723U\\PHY_REG_1T.txt" ++ #define RTL8723_PHY_RADIO_A "rtl8723U\\radio_a_1T.txt" ++ #define RTL8723_PHY_RADIO_B "rtl8723U\\radio_b_1T.txt" ++ #define RTL8723_AGC_TAB "rtl8723U\\AGC_TAB_1T.txt" ++ #define RTL8723_PHY_MACREG "rtl8723U\\MAC_REG.txt" ++ #define RTL8723_PHY_MACREG "rtl8723U\\MAC_REG.txt" ++ #define RTL8723_PHY_REG_PG "rtl8723U\\PHY_REG_PG.txt" ++ #define RTL8723_PHY_REG_MP "rtl8723U\\PHY_REG_MP.txt" ++ ++ // The file name "_2T" is for 92CU, "_1T" is for 88CU. Modified by tynli. 2009.11.24. ++ #define Rtl819XFwImageArray Rtl8192CUFwTSMCImgArray ++ #define Rtl819XFwTSMCImageArray Rtl8192CUFwTSMCImgArray ++ #define Rtl819XFwUMCACutImageArray Rtl8192CUFwUMCACutImgArray ++ #define Rtl819XFwUMCBCutImageArray Rtl8192CUFwUMCBCutImgArray ++#ifdef CONFIG_WOWLAN ++ #define Rtl8192C_FwTSMCWWImageArray Rtl8192CUFwTSMCWWImgArray ++ #define Rtl8192C_FwUMCWWImageArray Rtl8192CUFwUMCACutWWImgArray ++ #define Rtl8192C_FwUMCBCutWWImageArray Rtl8192CUFwUMCBCutWWImgArray ++#endif //CONFIG_WOWLAN ++ #define Rtl819XMAC_Array Rtl8192CUMAC_2T_Array ++ #define Rtl819XAGCTAB_2TArray Rtl8192CUAGCTAB_2TArray ++ #define Rtl819XAGCTAB_1TArray Rtl8192CUAGCTAB_1TArray ++ #define Rtl819XAGCTAB_1T_HPArray Rtl8192CUAGCTAB_1T_HPArray ++ #define Rtl819XPHY_REG_2TArray Rtl8192CUPHY_REG_2TArray ++ #define Rtl819XPHY_REG_1TArray Rtl8192CUPHY_REG_1TArray ++ #define Rtl819XPHY_REG_1T_mCardArray Rtl8192CUPHY_REG_1T_mCardArray ++ #define Rtl819XPHY_REG_2T_mCardArray Rtl8192CUPHY_REG_2T_mCardArray ++ #define Rtl819XPHY_REG_1T_HPArray Rtl8192CUPHY_REG_1T_HPArray ++ #define Rtl819XRadioA_2TArray Rtl8192CURadioA_2TArray ++ #define Rtl819XRadioA_1TArray Rtl8192CURadioA_1TArray ++ #define Rtl819XRadioA_1T_mCardArray Rtl8192CURadioA_1T_mCardArray ++ #define Rtl819XRadioB_2TArray Rtl8192CURadioB_2TArray ++ #define Rtl819XRadioB_1TArray Rtl8192CURadioB_1TArray ++ #define Rtl819XRadioB_1T_mCardArray Rtl8192CURadioB_1T_mCardArray ++ #define Rtl819XRadioA_1T_HPArray Rtl8192CURadioA_1T_HPArray ++ #define Rtl819XPHY_REG_Array_PG Rtl8192CUPHY_REG_Array_PG ++ #define Rtl819XPHY_REG_Array_PG_mCard Rtl8192CUPHY_REG_Array_PG_mCard ++ #define Rtl819XPHY_REG_Array_PG_HP Rtl8192CUPHY_REG_Array_PG_HP ++ #define Rtl819XPHY_REG_Array_MP Rtl8192CUPHY_REG_Array_MP ++#endif ++ ++#define DRVINFO_SZ 4 // unit is 8bytes ++#define PageNum_128(_Len) (u32)(((_Len)>>7) + ((_Len)&0x7F ? 1:0)) ++ ++#define FW_8192C_SIZE 16384+32//16k ++#define FW_8192C_START_ADDRESS 0x1000 ++//#define FW_8192C_END_ADDRESS 0x3FFF //Filen said this is for test chip ++#define FW_8192C_END_ADDRESS 0x1FFF ++ ++#define MAX_PAGE_SIZE 4096 // @ page : 4k bytes ++ ++#define IS_FW_HEADER_EXIST(_pFwHdr) ((le16_to_cpu(_pFwHdr->Signature)&0xFFF0) == 0x92C0 ||\ ++ (le16_to_cpu(_pFwHdr->Signature)&0xFFF0) == 0x88C0 ||\ ++ (le16_to_cpu(_pFwHdr->Signature)&0xFFF0) == 0x2300) ++ ++typedef enum _FIRMWARE_SOURCE{ ++ FW_SOURCE_IMG_FILE = 0, ++ FW_SOURCE_HEADER_FILE = 1, //from header file ++}FIRMWARE_SOURCE, *PFIRMWARE_SOURCE; ++ ++typedef struct _RT_FIRMWARE{ ++ FIRMWARE_SOURCE eFWSource; ++ u8* szFwBuffer; ++ u32 ulFwLength; ++#ifdef CONFIG_WOWLAN ++ u8* szWoWLANFwBuffer; ++ u32 ulWoWLANFwLength; ++#endif //CONFIG_WOWLAN ++}RT_FIRMWARE, *PRT_FIRMWARE, RT_FIRMWARE_92C, *PRT_FIRMWARE_92C; ++ ++// ++// This structure must be cared byte-ordering ++// ++// Added by tynli. 2009.12.04. ++typedef struct _RT_8192C_FIRMWARE_HDR {//8-byte alinment required ++ ++ //--- LONG WORD 0 ---- ++ u16 Signature; // 92C0: test chip; 92C, 88C0: test chip; 88C1: MP A-cut; 92C1: MP A-cut ++ u8 Category; // AP/NIC and USB/PCI ++ u8 Function; // Reserved for different FW function indcation, for further use when driver needs to download different FW in different conditions ++ u16 Version; // FW Version ++ u8 Subversion; // FW Subversion, default 0x00 ++ u16 Rsvd1; ++ ++ ++ //--- LONG WORD 1 ---- ++ u8 Month; // Release time Month field ++ u8 Date; // Release time Date field ++ u8 Hour; // Release time Hour field ++ u8 Minute; // Release time Minute field ++ u16 RamCodeSize; // The size of RAM code ++ u16 Rsvd2; ++ ++ //--- LONG WORD 2 ---- ++ u32 SvnIdx; // The SVN entry index ++ u32 Rsvd3; ++ ++ //--- LONG WORD 3 ---- ++ u32 Rsvd4; ++ u32 Rsvd5; ++ ++}RT_8192C_FIRMWARE_HDR, *PRT_8192C_FIRMWARE_HDR; ++ ++#define DRIVER_EARLY_INT_TIME 0x05 ++#define BCN_DMA_ATIME_INT_TIME 0x02 ++ ++#ifdef CONFIG_USB_RX_AGGREGATION ++ ++typedef enum _USB_RX_AGG_MODE{ ++ USB_RX_AGG_DISABLE, ++ USB_RX_AGG_DMA, ++ USB_RX_AGG_USB, ++ USB_RX_AGG_MIX ++}USB_RX_AGG_MODE; ++ ++#define MAX_RX_DMA_BUFFER_SIZE 10240 // 10K for 8192C RX DMA buffer ++ ++#endif ++ ++ ++#define TX_SELE_HQ BIT(0) // High Queue ++#define TX_SELE_LQ BIT(1) // Low Queue ++#define TX_SELE_NQ BIT(2) // Normal Queue ++ ++ ++// Note: We will divide number of page equally for each queue other than public queue! ++ ++#define TX_TOTAL_PAGE_NUMBER 0xF8 ++#define TX_PAGE_BOUNDARY (TX_TOTAL_PAGE_NUMBER + 1) ++ ++// For Normal Chip Setting ++// (HPQ + LPQ + NPQ + PUBQ) shall be TX_TOTAL_PAGE_NUMBER ++#define NORMAL_PAGE_NUM_PUBQ 0xE7 ++#define NORMAL_PAGE_NUM_HPQ 0x0C ++#define NORMAL_PAGE_NUM_LPQ 0x02 ++#define NORMAL_PAGE_NUM_NPQ 0x02 ++ ++ ++// For Test Chip Setting ++// (HPQ + LPQ + PUBQ) shall be TX_TOTAL_PAGE_NUMBER ++#define TEST_PAGE_NUM_PUBQ 0x7E ++ ++ ++// For Test Chip Setting ++#define WMM_TEST_TX_TOTAL_PAGE_NUMBER 0xF5 ++#define WMM_TEST_TX_PAGE_BOUNDARY (WMM_TEST_TX_TOTAL_PAGE_NUMBER + 1) //F6 ++ ++#define WMM_TEST_PAGE_NUM_PUBQ 0xA3 ++#define WMM_TEST_PAGE_NUM_HPQ 0x29 ++#define WMM_TEST_PAGE_NUM_LPQ 0x29 ++ ++ ++//Note: For Normal Chip Setting ,modify later ++#define WMM_NORMAL_TX_TOTAL_PAGE_NUMBER 0xF5 ++#define WMM_NORMAL_TX_PAGE_BOUNDARY (WMM_TEST_TX_TOTAL_PAGE_NUMBER + 1) //F6 ++ ++#define WMM_NORMAL_PAGE_NUM_PUBQ 0xB0 ++#define WMM_NORMAL_PAGE_NUM_HPQ 0x29 ++#define WMM_NORMAL_PAGE_NUM_LPQ 0x1C ++#define WMM_NORMAL_PAGE_NUM_NPQ 0x1C ++ ++//------------------------------------------------------------------------- ++// Chip specific ++//------------------------------------------------------------------------- ++#define CHIP_BONDING_IDENTIFIER(_value) (((_value)>>22)&0x3) ++#define CHIP_BONDING_92C_1T2R 0x1 ++#define CHIP_BONDING_88C_USB_MCARD 0x2 ++#define CHIP_BONDING_88C_USB_HP 0x1 ++ ++// ++// 2011.01.06. Define new structure of chip version for RTL8723 and so on. Added by tynli. ++// ++/* ++ | BIT15:12 | BIT11:8 | BIT 7 | BIT6:4 | BIT3 | BIT2:0 | ++ |-------------+-----------+-----------+-------+-----------+-------| ++ | IC version(CUT) | ROM version | Manufacturer | RF type | Chip type | IC Type | ++ | | | TSMC/UMC | | TEST/NORMAL| | ++*/ ++// [15:12] IC version(CUT): A-cut=0, B-cut=1, C-cut=2, D-cut=3 ++// [7] Manufacturer: TSMC=0, UMC=1 ++// [6:4] RF type: 1T1R=0, 1T2R=1, 2T2R=2 ++// [3] Chip type: TEST=0, NORMAL=1 ++// [2:0] IC type: 81xxC=0, 8723=1, 92D=2 ++ ++#define CHIP_8723 BIT(0) ++#define CHIP_92D BIT(1) ++#define NORMAL_CHIP BIT(3) ++#define RF_TYPE_1T1R (~(BIT(4)|BIT(5)|BIT(6))) ++#define RF_TYPE_1T2R BIT(4) ++#define RF_TYPE_2T2R BIT(5) ++#define CHIP_VENDOR_UMC BIT(7) ++#define B_CUT_VERSION BIT(12) ++#define C_CUT_VERSION BIT(13) ++#define D_CUT_VERSION ((BIT(13)|BIT(14))) ++ ++ ++// MASK ++#define IC_TYPE_MASK (BIT(0)|BIT(1)|BIT(2)) ++#define CHIP_TYPE_MASK BIT(3) ++#define RF_TYPE_MASK (BIT(4)|BIT(5)|BIT(6)) ++#define MANUFACTUER_MASK BIT(7) ++#define ROM_VERSION_MASK (BIT(11)|BIT(10)|BIT(9)|BIT(8)) ++#define CUT_VERSION_MASK (BIT(15)|BIT(14)|BIT(13)|BIT(12)) ++ ++// Get element ++#define GET_CVID_IC_TYPE(version) ((version) & IC_TYPE_MASK) ++#define GET_CVID_CHIP_TYPE(version) ((version) & CHIP_TYPE_MASK) ++#define GET_CVID_RF_TYPE(version) ((version) & RF_TYPE_MASK) ++#define GET_CVID_MANUFACTUER(version) ((version) & MANUFACTUER_MASK) ++#define GET_CVID_ROM_VERSION(version) ((version) & ROM_VERSION_MASK) ++#define GET_CVID_CUT_VERSION(version) ((version) & CUT_VERSION_MASK) ++ ++#define IS_81XXC(version) ((GET_CVID_IC_TYPE(version) == 0)? _TRUE : _FALSE) ++#define IS_8723_SERIES(version) ((GET_CVID_IC_TYPE(version) == CHIP_8723)? _TRUE : _FALSE) ++#define IS_92D(version) ((GET_CVID_IC_TYPE(version) == CHIP_92D)? _TRUE : _FALSE) ++#define IS_1T1R(version) ((GET_CVID_RF_TYPE(version))? _FALSE : _TRUE) ++#define IS_1T2R(version) ((GET_CVID_RF_TYPE(version) == RF_TYPE_1T2R)? _TRUE : _FALSE) ++#define IS_2T2R(version) ((GET_CVID_RF_TYPE(version) == RF_TYPE_2T2R)? _TRUE : _FALSE) ++#define IS_NORMAL_CHIP(version) ((GET_CVID_CHIP_TYPE(version))? _TRUE: _FALSE) ++#define IS_CHIP_VENDOR_UMC(version) ((GET_CVID_MANUFACTUER(version))? _TRUE: _FALSE) ++ ++#define IS_81XXC_TEST_CHIP(version) ((IS_81XXC(version) && (!IS_NORMAL_CHIP(version)))? _TRUE: _FALSE) ++#define IS_92D_TEST_CHIP(version) ((IS_92D(version) && (!IS_NORMAL_CHIP(version)))? _TRUE: _FALSE) ++#define IS_92C_SERIAL(version) ((IS_81XXC(version) && IS_2T2R(version)) ? _TRUE : _FALSE) ++#define IS_VENDOR_UMC_A_CUT(version) ((IS_CHIP_VENDOR_UMC(version)) ? ((GET_CVID_CUT_VERSION(version)) ? _FALSE : _TRUE) : _FALSE) ++#define IS_VENDOR_8723_A_CUT(version) ((IS_8723_SERIES(version)) ? ((GET_CVID_CUT_VERSION(version)) ? _FALSE : _TRUE) : _FALSE) ++// 88/92C UMC B-cut vendor is set to TSMC so we need to check CHIP_VENDOR_UMC bit is not 1. ++#define IS_81xxC_VENDOR_UMC_B_CUT(version) ((IS_CHIP_VENDOR_UMC(version)) ? ((GET_CVID_CUT_VERSION(version) == B_CUT_VERSION) ? _TRUE : _FALSE):_FALSE) ++#define IS_92D_SINGLEPHY(version) ((IS_92D(version)) ? (IS_2T2R(version) ? _TRUE: _FALSE) : _FALSE) ++#define IS_92D_C_CUT(version) ((IS_92D(version)) ? ((GET_CVID_CUT_VERSION(version) == 0x2) ? _TRUE : _FALSE) : _FALSE) ++#define IS_92D_D_CUT(version) ((IS_92D(version)) ? ((GET_CVID_CUT_VERSION(version) == 0x3) ? _TRUE : _FALSE) : _FALSE) ++ ++typedef enum _VERSION_8192C{ ++ VERSION_TEST_CHIP_88C = 0x0000, ++ VERSION_TEST_CHIP_92C = 0x0020, ++ VERSION_TEST_UMC_CHIP_8723 = 0x0081, ++ VERSION_NORMAL_TSMC_CHIP_88C = 0x0008, ++ VERSION_NORMAL_TSMC_CHIP_92C = 0x0028, ++ VERSION_NORMAL_TSMC_CHIP_92C_1T2R = 0x0018, ++ VERSION_NORMAL_UMC_CHIP_88C_A_CUT = 0x0088, ++ VERSION_NORMAL_UMC_CHIP_92C_A_CUT = 0x00a8, ++ VERSION_NORMAL_UMC_CHIP_92C_1T2R_A_CUT = 0x0098, ++ VERSION_NORMAL_UMC_CHIP_8723_1T1R_A_CUT = 0x0089, ++ VERSION_NORMAL_UMC_CHIP_8723_1T1R_B_CUT = 0x1089, ++ VERSION_NORMAL_UMC_CHIP_88C_B_CUT = 0x1088, ++ VERSION_NORMAL_UMC_CHIP_92C_B_CUT = 0x10a8, ++ VERSION_NORMAL_UMC_CHIP_92C_1T2R_B_CUT = 0x1090, ++ VERSION_TEST_CHIP_92D_SINGLEPHY= 0x0022, ++ VERSION_TEST_CHIP_92D_DUALPHY = 0x0002, ++ VERSION_NORMAL_CHIP_92D_SINGLEPHY= 0x002a, ++ VERSION_NORMAL_CHIP_92D_DUALPHY = 0x000a, ++ VERSION_NORMAL_CHIP_92D_C_CUT_SINGLEPHY = 0x202a, ++ VERSION_NORMAL_CHIP_92D_C_CUT_DUALPHY = 0x200a, ++ VERSION_NORMAL_CHIP_92D_D_CUT_SINGLEPHY = 0x302a, ++ VERSION_NORMAL_CHIP_92D_D_CUT_DUALPHY = 0x300a, ++}VERSION_8192C,*PVERSION_8192C; ++ ++ ++ ++//------------------------------------------------------------------------- ++// Channel Plan ++//------------------------------------------------------------------------- ++enum ChannelPlan{ ++ CHPL_FCC = 0, ++ CHPL_IC = 1, ++ CHPL_ETSI = 2, ++ CHPL_SPAIN = 3, ++ CHPL_FRANCE = 4, ++ CHPL_MKK = 5, ++ CHPL_MKK1 = 6, ++ CHPL_ISRAEL = 7, ++ CHPL_TELEC = 8, ++ CHPL_GLOBAL = 9, ++ CHPL_WORLD = 10, ++}; ++ ++typedef struct _TxPowerInfo{ ++ u8 CCKIndex[RF90_PATH_MAX][CHANNEL_GROUP_MAX]; ++ u8 HT40_1SIndex[RF90_PATH_MAX][CHANNEL_GROUP_MAX]; ++ u8 HT40_2SIndexDiff[RF90_PATH_MAX][CHANNEL_GROUP_MAX]; ++ u8 HT20IndexDiff[RF90_PATH_MAX][CHANNEL_GROUP_MAX]; ++ u8 OFDMIndexDiff[RF90_PATH_MAX][CHANNEL_GROUP_MAX]; ++ u8 HT40MaxOffset[RF90_PATH_MAX][CHANNEL_GROUP_MAX]; ++ u8 HT20MaxOffset[RF90_PATH_MAX][CHANNEL_GROUP_MAX]; ++ u8 TSSI_A; ++ u8 TSSI_B; ++}TxPowerInfo, *PTxPowerInfo; ++ ++#define EFUSE_REAL_CONTENT_LEN 512 ++#define EFUSE_MAP_LEN 128 ++#define EFUSE_MAX_SECTION 16 ++#define EFUSE_IC_ID_OFFSET 506 //For some inferiority IC purpose. added by Roger, 2009.09.02. ++#define AVAILABLE_EFUSE_ADDR(addr) (addr < EFUSE_REAL_CONTENT_LEN) ++// ++// To prevent out of boundary programming case, leave 1byte and program full section ++// 9bytes + 1byt + 5bytes and pre 1byte. ++// For worst case: ++// | 1byte|----8bytes----|1byte|--5bytes--| ++// | | Reserved(14bytes) | ++// ++#define EFUSE_OOB_PROTECT_BYTES 15 // PG data exclude header, dummy 6 bytes frome CP test and reserved 1byte. ++ ++ ++#define EFUSE_MAP_LEN_8723 256 ++#define EFUSE_MAX_SECTION_8723 32 ++ ++//======================================================== ++// EFUSE for BT definition ++//======================================================== ++#define EFUSE_BT_REAL_CONTENT_LEN 1536 // 512*3 ++#define EFUSE_BT_MAP_LEN 1024 // 1k bytes ++#define EFUSE_BT_MAX_SECTION 128 // 1024/8 ++ ++#define EFUSE_PROTECT_BYTES_BANK 16 ++ ++// ++// For RTL8723 WiFi/BT/GPS multi-function configuration. 2010.10.06. ++// ++typedef enum _RT_MULTI_FUNC{ ++ RT_MULTI_FUNC_NONE = 0x00, ++ RT_MULTI_FUNC_WIFI = 0x01, ++ RT_MULTI_FUNC_BT = 0x02, ++ RT_MULTI_FUNC_GPS = 0x04, ++}RT_MULTI_FUNC,*PRT_MULTI_FUNC; ++ ++// ++// For RTL8723 WiFi PDn/GPIO polarity control configuration. 2010.10.08. ++// ++typedef enum _RT_POLARITY_CTL{ ++ RT_POLARITY_LOW_ACT = 0, ++ RT_POLARITY_HIGH_ACT = 1, ++}RT_POLARITY_CTL,*PRT_POLARITY_CTL; ++ ++// For RTL8723 regulator mode. by tynli. 2011.01.14. ++typedef enum _RT_REGULATOR_MODE{ ++ RT_SWITCHING_REGULATOR = 0, ++ RT_LDO_REGULATOR = 1, ++}RT_REGULATOR_MODE,*PRT_REGULATOR_MODE; ++ ++#ifdef CONFIG_PCI_HCI ++struct hal_data_8192ce ++{ ++ VERSION_8192C VersionID; ++ RT_MULTI_FUNC MultiFunc; // For multi-function consideration. ++ RT_POLARITY_CTL PolarityCtl; // For Wifi PDn Polarity control. ++ RT_REGULATOR_MODE RegulatorMode; // switching regulator or LDO ++ u16 CustomerID; ++ ++ u16 FirmwareVersion; ++ u16 FirmwareVersionRev; ++ u16 FirmwareSubVersion; ++ ++ u32 IntrMask[2]; ++ u32 IntrMaskToSet[2]; ++ ++ u32 DisabledFunctions; ++ ++ //current WIFI_PHY values ++ u32 ReceiveConfig; ++ u32 TransmitConfig; ++ WIRELESS_MODE CurrentWirelessMode; ++ HT_CHANNEL_WIDTH CurrentChannelBW; ++ u8 CurrentChannel; ++ u8 nCur40MhzPrimeSC;// Control channel sub-carrier ++ ++ u16 BasicRateSet; ++ ++ //rf_ctrl ++ _lock rf_lock; ++ u8 rf_chip; ++ u8 rf_type; ++ u8 NumTotalRFPath; ++ ++ INTERFACE_SELECT_8192CPCIe InterfaceSel; ++ ++ // ++ // EEPROM setting. ++ // ++ u16 EEPROMVID; ++ u16 EEPROMDID; ++ u16 EEPROMSVID; ++ u16 EEPROMSMID; ++ u16 EEPROMChannelPlan; ++ u16 EEPROMVersion; ++ ++ u8 EEPROMChnlAreaTxPwrCCK[2][3]; ++ u8 EEPROMChnlAreaTxPwrHT40_1S[2][3]; ++ u8 EEPROMChnlAreaTxPwrHT40_2SDiff[2][3]; ++ u8 EEPROMPwrLimitHT20[3]; ++ u8 EEPROMPwrLimitHT40[3]; ++ ++ u8 bTXPowerDataReadFromEEPORM; ++ u8 EEPROMThermalMeter; ++ u8 EEPROMTSSI[2]; ++ ++ u8 EEPROMCustomerID; ++ u8 EEPROMBoardType; ++ u8 EEPROMRegulatory; ++ ++ u8 bDefaultAntenna; ++ u8 bIQKInitialized; ++ ++ u8 TxPwrLevelCck[RF90_PATH_MAX][CHANNEL_MAX_NUMBER]; ++ u8 TxPwrLevelHT40_1S[RF90_PATH_MAX][CHANNEL_MAX_NUMBER]; // For HT 40MHZ pwr ++ u8 TxPwrLevelHT40_2S[RF90_PATH_MAX][CHANNEL_MAX_NUMBER]; // For HT 40MHZ pwr ++ u8 TxPwrHt20Diff[RF90_PATH_MAX][CHANNEL_MAX_NUMBER];// HT 20<->40 Pwr diff ++ u8 TxPwrLegacyHtDiff[RF90_PATH_MAX][CHANNEL_MAX_NUMBER];// For HT<->legacy pwr diff ++ // For power group ++ u8 PwrGroupHT20[RF90_PATH_MAX][CHANNEL_MAX_NUMBER]; ++ u8 PwrGroupHT40[RF90_PATH_MAX][CHANNEL_MAX_NUMBER]; ++ ++ u8 LegacyHTTxPowerDiff;// Legacy to HT rate power diff ++ ++#ifdef CONFIG_BT_COEXIST ++ struct btcoexist_priv bt_coexist; ++#endif ++ ++ // Read/write are allow for following hardware information variables ++ u8 framesync; ++ u32 framesyncC34; ++ u8 framesyncMonitor; ++ u8 DefaultInitialGain[4]; ++ u8 pwrGroupCnt; ++ u32 MCSTxPowerLevelOriginalOffset[7][16]; ++ u32 CCKTxPowerLevelOriginalOffset; ++ ++ u32 AntennaTxPath; // Antenna path Tx ++ u32 AntennaRxPath; // Antenna path Rx ++ u8 BluetoothCoexist; ++ u8 ExternalPA; ++ ++ //u32 LedControlNum; ++ //u32 LedControlMode; ++ u8 bLedOpenDrain; // Support Open-drain arrangement for controlling the LED. Added by Roger, 2009.10.16. ++ //u32 TxPowerTrackControl; ++ u8 b1x1RecvCombine; // for 1T1R receive combining ++ ++ u8 bCurrentTurboEDCA; ++ u32 AcParam_BE; //Original parameter for BE, use for EDCA turbo. ++ ++ //vivi, for tx power tracking, 20080407 ++ //u16 TSSI_13dBm; ++ //u32 Pwr_Track; ++ // The current Tx Power Level ++ u8 CurrentCckTxPwrIdx; ++ u8 CurrentOfdm24GTxPwrIdx; ++ ++ BB_REGISTER_DEFINITION_T PHYRegDef[4]; //Radio A/B/C/D ++ ++ BOOLEAN bRFPathRxEnable[4]; // We support 4 RF path now. ++ ++ u32 RfRegChnlVal[2]; ++ ++ u8 bCckHighPower; ++ ++ //RDG enable ++ BOOLEAN bRDGEnable; ++ ++ //for host message to fw ++ u8 LastHMEBoxNum; ++ ++ u8 fw_ractrl; ++ u8 RegTxPause; ++ // Beacon function related global variable. ++ u32 RegBcnCtrlVal; ++ u8 RegFwHwTxQCtrl; ++ u8 RegReg542; ++ u8 CurAntenna; ++ u8 AntDivCfg; ++ ++#ifdef CONFIG_SW_ANTENNA_DIVERSITY ++ //SW Antenna Switch ++ s32 RSSI_sum_A; ++ s32 RSSI_sum_B; ++ s32 RSSI_cnt_A; ++ s32 RSSI_cnt_B; ++ BOOLEAN RSSI_test; ++#endif ++#ifdef CONFIG_HW_ANTENNA_DIVERSITY ++ //Hybrid Antenna Diversity ++ u32 CCK_Ant1_Cnt; ++ u32 CCK_Ant2_Cnt; ++ u32 OFDM_Ant1_Cnt; ++ u32 OFDM_Ant2_Cnt; ++#endif ++ ++ struct dm_priv dmpriv; ++ u8 bDumpRxPkt;//for debug ++#ifdef DBG_CONFIG_ERROR_DETECT ++ struct sreset_priv srestpriv; ++#endif ++ u8 bInterruptMigration; ++ u8 bDisableTxInt; ++ u8 bGpioHwWpsPbc; ++ ++ u8 FwRsvdPageStartOffset; //2010.06.23. Added by tynli. Reserve page start offset except beacon in TxQ. ++ ++ u16 EfuseUsedBytes; ++ ++#ifdef CONFIG_P2P ++ struct P2P_PS_Offload_t p2p_ps_offload; ++#endif //CONFIG_P2P ++}; ++ ++typedef struct hal_data_8192ce HAL_DATA_TYPE, *PHAL_DATA_TYPE; ++ ++// ++// Function disabled. ++// ++#define DF_TX_BIT BIT0 ++#define DF_RX_BIT BIT1 ++#define DF_IO_BIT BIT2 ++#define DF_IO_D3_BIT BIT3 ++ ++#define RT_DF_TYPE u32 ++#define RT_DISABLE_FUNC(__pAdapter, __FuncBits) ((__pAdapter)->DisabledFunctions |= ((RT_DF_TYPE)(__FuncBits))) ++#define RT_ENABLE_FUNC(__pAdapter, __FuncBits) ((__pAdapter)->DisabledFunctions &= (~((RT_DF_TYPE)(__FuncBits)))) ++#define RT_IS_FUNC_DISABLED(__pAdapter, __FuncBits) ( (__pAdapter)->DisabledFunctions & (__FuncBits) ) ++#define IS_MULTI_FUNC_CHIP(_Adapter) (((((PHAL_DATA_TYPE)(_Adapter->HalData))->MultiFunc) & (RT_MULTI_FUNC_BT|RT_MULTI_FUNC_GPS)) ? _TRUE : _FALSE) ++ ++void InterruptRecognized8192CE(PADAPTER Adapter, PRT_ISR_CONTENT pIsrContent); ++VOID UpdateInterruptMask8192CE(PADAPTER Adapter, u32 AddMSR, u32 RemoveMSR); ++#endif ++ ++#ifdef CONFIG_USB_HCI ++struct hal_data_8192cu ++{ ++ VERSION_8192C VersionID; ++ RT_MULTI_FUNC MultiFunc; // For multi-function consideration. ++ RT_POLARITY_CTL PolarityCtl; // For Wifi PDn Polarity control. ++ RT_REGULATOR_MODE RegulatorMode; // switching regulator or LDO ++ u16 CustomerID; ++ ++ u16 FirmwareVersion; ++ u16 FirmwareVersionRev; ++ u16 FirmwareSubVersion; ++ ++ //current WIFI_PHY values ++ u32 ReceiveConfig; ++ WIRELESS_MODE CurrentWirelessMode; ++ HT_CHANNEL_WIDTH CurrentChannelBW; ++ u8 CurrentChannel; ++ u8 nCur40MhzPrimeSC;// Control channel sub-carrier ++ ++ u16 BasicRateSet; ++ ++ //rf_ctrl ++ u8 rf_chip; ++ u8 rf_type; ++ u8 NumTotalRFPath; ++ ++ u8 BoardType; ++ //INTERFACE_SELECT_8192CUSB InterfaceSel; ++ ++ // ++ // EEPROM setting. ++ // ++ u16 EEPROMVID; ++ u16 EEPROMPID; ++ u16 EEPROMSVID; ++ u16 EEPROMSDID; ++ u8 EEPROMCustomerID; ++ u8 EEPROMSubCustomerID; ++ u8 EEPROMVersion; ++ u8 EEPROMRegulatory; ++ ++ u8 bTXPowerDataReadFromEEPORM; ++ u8 EEPROMThermalMeter; ++ ++ u8 bIQKInitialized; ++ ++ u8 TxPwrLevelCck[RF90_PATH_MAX][CHANNEL_MAX_NUMBER]; ++ u8 TxPwrLevelHT40_1S[RF90_PATH_MAX][CHANNEL_MAX_NUMBER]; // For HT 40MHZ pwr ++ u8 TxPwrLevelHT40_2S[RF90_PATH_MAX][CHANNEL_MAX_NUMBER]; // For HT 40MHZ pwr ++ u8 TxPwrHt20Diff[RF90_PATH_MAX][CHANNEL_MAX_NUMBER];// HT 20<->40 Pwr diff ++ u8 TxPwrLegacyHtDiff[RF90_PATH_MAX][CHANNEL_MAX_NUMBER];// For HT<->legacy pwr diff ++ // For power group ++ u8 PwrGroupHT20[RF90_PATH_MAX][CHANNEL_MAX_NUMBER]; ++ u8 PwrGroupHT40[RF90_PATH_MAX][CHANNEL_MAX_NUMBER]; ++ ++ u8 LegacyHTTxPowerDiff;// Legacy to HT rate power diff ++ ++ // Read/write are allow for following hardware information variables ++ u8 framesync; ++ u32 framesyncC34; ++ u8 framesyncMonitor; ++ u8 DefaultInitialGain[4]; ++ u8 pwrGroupCnt; ++ u32 MCSTxPowerLevelOriginalOffset[7][16]; ++ u32 CCKTxPowerLevelOriginalOffset; ++ ++ u32 AntennaTxPath; // Antenna path Tx ++ u32 AntennaRxPath; // Antenna path Rx ++ u8 BluetoothCoexist; ++ u8 ExternalPA; ++ ++ u8 bLedOpenDrain; // Support Open-drain arrangement for controlling the LED. Added by Roger, 2009.10.16. ++ ++ //u32 LedControlNum; ++ //u32 LedControlMode; ++ //u32 TxPowerTrackControl; ++ u8 b1x1RecvCombine; // for 1T1R receive combining ++ ++ u8 bCurrentTurboEDCA; ++ u32 AcParam_BE; //Original parameter for BE, use for EDCA turbo. ++ ++ //vivi, for tx power tracking, 20080407 ++ //u16 TSSI_13dBm; ++ //u32 Pwr_Track; ++ // The current Tx Power Level ++ u8 CurrentCckTxPwrIdx; ++ u8 CurrentOfdm24GTxPwrIdx; ++ ++ BB_REGISTER_DEFINITION_T PHYRegDef[4]; //Radio A/B/C/D ++ ++ BOOLEAN bRFPathRxEnable[4]; // We support 4 RF path now. ++ ++ u32 RfRegChnlVal[2]; ++ ++ u8 bCckHighPower; ++ ++ //RDG enable ++ BOOLEAN bRDGEnable; ++ ++ //for host message to fw ++ u8 LastHMEBoxNum; ++ ++ u8 fw_ractrl; ++ u8 RegTxPause; ++ // Beacon function related global variable. ++ u32 RegBcnCtrlVal; ++ u8 RegFwHwTxQCtrl; ++ u8 RegReg542; ++ ++ struct dm_priv dmpriv; ++#ifdef DBG_CONFIG_ERROR_DETECT ++ struct sreset_priv srestpriv; ++#endif ++ ++#ifdef CONFIG_BT_COEXIST ++ struct btcoexist_priv bt_coexist; ++#endif ++ u8 CurAntenna; ++ u8 AntDivCfg; ++ ++#ifdef CONFIG_SW_ANTENNA_DIVERSITY ++ //SW Antenna Switch ++ s32 RSSI_sum_A; ++ s32 RSSI_sum_B; ++ s32 RSSI_cnt_A; ++ s32 RSSI_cnt_B; ++ BOOLEAN RSSI_test; ++#endif ++#ifdef CONFIG_HW_ANTENNA_DIVERSITY ++ //Hybrid Antenna Diversity ++ u32 CCK_Ant1_Cnt; ++ u32 CCK_Ant2_Cnt; ++ u32 OFDM_Ant1_Cnt; ++ u32 OFDM_Ant2_Cnt; ++#endif ++ ++ u8 bDumpRxPkt;//for debug ++ u8 FwRsvdPageStartOffset; //2010.06.23. Added by tynli. Reserve page start offset except beacon in TxQ. ++ ++ // 2010/08/09 MH Add CU power down mode. ++ BOOLEAN pwrdown; ++ ++ // For 92C USB endpoint setting ++ // ++ ++ u32 UsbBulkOutSize; ++ ++ int RtBulkOutPipe[3]; ++ int RtBulkInPipe; ++ int RtIntInPipe; ++ // Add for dual MAC 0--Mac0 1--Mac1 ++ u32 interfaceIndex; ++ ++ u8 OutEpQueueSel; ++ u8 OutEpNumber; ++ ++ u8 Queue2EPNum[8];//for out endpoint number mapping ++ ++#ifdef CONFIG_USB_TX_AGGREGATION ++ u8 UsbTxAggMode; ++ u8 UsbTxAggDescNum; ++#endif ++#ifdef CONFIG_USB_RX_AGGREGATION ++ u16 HwRxPageSize; // Hardware setting ++ u32 MaxUsbRxAggBlock; ++ ++ USB_RX_AGG_MODE UsbRxAggMode; ++ u8 UsbRxAggBlockCount; // USB Block count. Block size is 512-byte in hight speed and 64-byte in full speed ++ u8 UsbRxAggBlockTimeout; ++ u8 UsbRxAggPageCount; // 8192C DMA page count ++ u8 UsbRxAggPageTimeout; ++#endif ++ ++ // 2010/12/10 MH Add for USB aggreation mode dynamic shceme. ++ BOOLEAN UsbRxHighSpeedMode; ++ ++ // 2010/11/22 MH Add for slim combo debug mode selective. ++ // This is used for fix the drawback of CU TSMC-A/UMC-A cut. HW auto suspend ability. Close BT clock. ++ BOOLEAN SlimComboDbg; ++ ++ u16 EfuseUsedBytes; ++ ++#ifdef CONFIG_P2P ++ struct P2P_PS_Offload_t p2p_ps_offload; ++#endif //CONFIG_P2P ++}; ++ ++typedef struct hal_data_8192cu HAL_DATA_TYPE, *PHAL_DATA_TYPE; ++#endif ++ ++#define GET_HAL_DATA(__pAdapter) ((HAL_DATA_TYPE *)((__pAdapter)->HalData)) ++#define GET_RF_TYPE(priv) (GET_HAL_DATA(priv)->rf_type) ++ ++#define INCLUDE_MULTI_FUNC_BT(_Adapter) (GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_BT) ++#define INCLUDE_MULTI_FUNC_GPS(_Adapter) (GET_HAL_DATA(_Adapter)->MultiFunc & RT_MULTI_FUNC_GPS) ++ ++VOID rtl8192c_FirmwareSelfReset(IN PADAPTER Adapter); ++int FirmwareDownload92C(IN PADAPTER Adapter,IN BOOLEAN bUsedWoWLANFw); ++VOID InitializeFirmwareVars92C(PADAPTER Adapter); ++u8 GetEEPROMSize8192C(PADAPTER Adapter); ++RT_CHANNEL_DOMAIN _HalMapChannelPlan8192C(PADAPTER Adapter, u8 HalChannelPlan); ++VERSION_8192C rtl8192c_ReadChipVersion(IN PADAPTER Adapter); ++void rtl8192c_ReadBluetoothCoexistInfo(PADAPTER Adapter, u8 *PROMContent, BOOLEAN AutoloadFail); ++void rtl8192c_HalSetBrateCfg(PADAPTER Adapter, u8 *mBratesOS, u16 *pBrateCfg); ++//void rtl8192c_free_hal_data(_adapter * padapter); ++VOID rtl8192c_EfuseParseIDCode(PADAPTER pAdapter, u8 *hwinfo); ++void rtl8192c_set_hal_ops(struct hal_ops *pHalFunc); ++ ++#endif +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/include/rtl8192c_led.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/include/rtl8192c_led.h 2013-07-26 19:36:06.000000000 +0000 +@@ -0,0 +1,43 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ++******************************************************************************/ ++#ifndef __RTL8192C_LED_H_ ++#define __RTL8192C_LED_H_ ++ ++#include ++#include ++#include ++ ++ ++//================================================================================ ++// Interface to manipulate LED objects. ++//================================================================================ ++#ifdef CONFIG_USB_HCI ++void rtl8192cu_InitSwLeds(_adapter *padapter); ++void rtl8192cu_DeInitSwLeds(_adapter *padapter); ++#endif ++#ifdef CONFIG_PCI_HCI ++void rtl8192ce_gen_RefreshLedState(PADAPTER Adapter); ++void rtl8192ce_InitSwLeds(_adapter *padapter); ++void rtl8192ce_DeInitSwLeds(_adapter *padapter); ++#endif ++ ++#endif ++ +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/include/rtl8192c_recv.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/include/rtl8192c_recv.h 2013-07-26 19:36:06.000000000 +0000 +@@ -0,0 +1,180 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ++******************************************************************************/ ++#ifndef _RTL8192C_RECV_H_ ++#define _RTL8192C_RECV_H_ ++ ++#include ++#include ++#include ++ ++ ++#ifdef PLATFORM_OS_XP ++ #define NR_RECVBUFF (16) ++#elif defined(PLATFORM_OS_CE) ++ #define NR_RECVBUFF (4) ++#else ++ ++ #define NR_RECVBUFF (4) ++ ++ #define NR_PREALLOC_RECV_SKB (8) ++#endif ++ ++ ++#define RECV_BLK_SZ 512 ++#define RECV_BLK_CNT 16 ++#define RECV_BLK_TH RECV_BLK_CNT ++ ++#if defined(CONFIG_USB_HCI) ++ ++#ifdef PLATFORM_OS_CE ++#define MAX_RECVBUF_SZ (8192+1024) // 8K+1k ++#else ++ #ifndef CONFIG_MINIMAL_MEMORY_USAGE ++ //#define MAX_RECVBUF_SZ (32768) // 32k ++ //#define MAX_RECVBUF_SZ (16384) //16K ++ //#define MAX_RECVBUF_SZ (10240) //10K ++ #define MAX_RECVBUF_SZ (15360) // 15k < 16k ++ //#define MAX_RECVBUF_SZ (8192+1024) // 8K+1k ++ #else ++ #define MAX_RECVBUF_SZ (4000) // about 4K ++ #endif ++#endif ++ ++#elif defined(CONFIG_PCI_HCI) ++#ifndef CONFIG_MINIMAL_MEMORY_USAGE ++ #define MAX_RECVBUF_SZ (9100) ++#else ++ #define MAX_RECVBUF_SZ (4000) // about 4K ++#endif ++ ++#define RX_MPDU_QUEUE 0 ++#define RX_CMD_QUEUE 1 ++#define RX_MAX_QUEUE 2 ++#endif ++ ++ ++#define RECV_BULK_IN_ADDR 0x80 ++#define RECV_INT_IN_ADDR 0x81 ++ ++#define PHY_RSSI_SLID_WIN_MAX 100 ++#define PHY_LINKQUALITY_SLID_WIN_MAX 20 ++ ++ ++struct phy_stat ++{ ++ unsigned int phydw0; ++ ++ unsigned int phydw1; ++ ++ unsigned int phydw2; ++ ++ unsigned int phydw3; ++ ++ unsigned int phydw4; ++ ++ unsigned int phydw5; ++ ++ unsigned int phydw6; ++ ++ unsigned int phydw7; ++}; ++ ++typedef struct _Phy_OFDM_Rx_Status_Report_8192cd ++{ ++ unsigned char trsw_gain_X[4]; ++ unsigned char pwdb_all; ++ unsigned char cfosho_X[4]; ++ unsigned char cfotail_X[4]; ++ unsigned char rxevm_X[2]; ++ unsigned char rxsnr_X[4]; ++ unsigned char pdsnr_X[2]; ++ unsigned char csi_current_X[2]; ++ unsigned char csi_target_X[2]; ++ unsigned char sigevm; ++ unsigned char max_ex_pwr; ++//#ifdef RTL8192SE ++#ifdef CONFIG_LITTLE_ENDIAN ++ unsigned char ex_intf_flg:1; ++ unsigned char sgi_en:1; ++ unsigned char rxsc:2; ++ //unsigned char rsvd:4; ++ unsigned char idle_long:1; ++ unsigned char r_ant_train_en:1; ++ unsigned char ANTSELB:1; ++ unsigned char ANTSEL:1; ++#else // _BIG_ENDIAN_ ++ //unsigned char rsvd:4; ++ unsigned char ANTSEL:1; ++ unsigned char ANTSELB:1; ++ unsigned char r_ant_train_en:1; ++ unsigned char idle_long:1; ++ unsigned char rxsc:2; ++ unsigned char sgi_en:1; ++ unsigned char ex_intf_flg:1; ++#endif ++//#else // RTL8190, RTL8192E ++// unsigned char sgi_en; ++// unsigned char rxsc_sgien_exflg; ++//#endif ++} __attribute__ ((packed))PHY_STS_OFDM_8192CD_T,PHY_RX_DRIVER_INFO_8192CD; ++ ++typedef struct _Phy_CCK_Rx_Status_Report_8192cd ++{ ++ /* For CCK rate descriptor. This is a signed 8:1 variable. LSB bit presend ++ 0.5. And MSB 7 bts presend a signed value. Range from -64~+63.5. */ ++ u8 adc_pwdb_X[4]; ++ u8 SQ_rpt; ++ u8 cck_agc_rpt; ++} PHY_STS_CCK_8192CD_T; ++ ++ ++// Rx smooth factor ++#define Rx_Smooth_Factor (20) ++ ++ ++#ifdef CONFIG_USB_HCI ++typedef struct _INTERRUPT_MSG_FORMAT_EX{ ++ unsigned int C2H_MSG0; ++ unsigned int C2H_MSG1; ++ unsigned int C2H_MSG2; ++ unsigned int C2H_MSG3; ++ unsigned int HISR; // from HISR Reg0x124, read to clear ++ unsigned int HISRE;// from HISRE Reg0x12c, read to clear ++ unsigned int MSG_EX; ++}INTERRUPT_MSG_FORMAT_EX,*PINTERRUPT_MSG_FORMAT_EX; ++ ++void rtl8192cu_init_recvbuf(_adapter *padapter, struct recv_buf *precvbuf); ++int rtl8192cu_init_recv_priv(_adapter * padapter); ++void rtl8192cu_free_recv_priv(_adapter * padapter); ++void rtl8192cu_update_recvframe_attrib_from_recvstat(union recv_frame *precvframe, struct recv_stat *prxstat); ++#endif ++ ++#ifdef CONFIG_PCI_HCI ++int rtl8192ce_init_recv_priv(_adapter * padapter); ++void rtl8192ce_free_recv_priv(_adapter * padapter); ++void rtl8192ce_update_recvframe_attrib_from_recvstat(union recv_frame *precvframe, struct recv_stat *prxstat); ++#endif ++ ++void rtl8192c_query_rx_phy_status(union recv_frame *prframe, struct phy_stat *pphy_stat); ++void rtl8192c_process_phy_info(_adapter *padapter, void *prframe); ++ ++#endif ++ +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/include/rtl8192c_rf.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/include/rtl8192c_rf.h 2013-07-26 19:36:06.000000000 +0000 +@@ -0,0 +1,93 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ++******************************************************************************/ ++/****************************************************************************** ++ * ++ * ++ * Module: rtl8192c_rf.h ( Header File) ++ * ++ * Note: Collect every HAL RF type exter API or constant. ++ * ++ * Function: ++ * ++ * Export: ++ * ++ * Abbrev: ++ * ++ * History: ++ * Data Who Remark ++ * ++ * 09/25/2008 MHC Create initial version. ++ * ++ * ++******************************************************************************/ ++#ifndef _RTL8192C_RF_H_ ++#define _RTL8192C_RF_H_ ++/* Check to see if the file has been included already. */ ++ ++ ++/*--------------------------Define Parameters-------------------------------*/ ++ ++// ++// For RF 6052 Series ++// ++#define RF6052_MAX_TX_PWR 0x3F ++#define RF6052_MAX_REG 0x3F ++#define RF6052_MAX_PATH 2 ++/*--------------------------Define Parameters-------------------------------*/ ++ ++ ++/*------------------------------Define structure----------------------------*/ ++ ++/*------------------------------Define structure----------------------------*/ ++ ++ ++/*------------------------Export global variable----------------------------*/ ++/*------------------------Export global variable----------------------------*/ ++ ++/*------------------------Export Marco Definition---------------------------*/ ++ ++/*------------------------Export Marco Definition---------------------------*/ ++ ++ ++/*--------------------------Exported Function prototype---------------------*/ ++ ++// ++// RF RL6052 Series API ++// ++void rtl8192c_RF_ChangeTxPath( IN PADAPTER Adapter, ++ IN u16 DataRate); ++void rtl8192c_PHY_RF6052SetBandwidth( ++ IN PADAPTER Adapter, ++ IN HT_CHANNEL_WIDTH Bandwidth); ++VOID rtl8192c_PHY_RF6052SetCckTxPower( ++ IN PADAPTER Adapter, ++ IN u8* pPowerlevel); ++VOID rtl8192c_PHY_RF6052SetOFDMTxPower( ++ IN PADAPTER Adapter, ++ IN u8* pPowerLevel, ++ IN u8 Channel); ++int PHY_RF6052_Config8192C( IN PADAPTER Adapter ); ++ ++/*--------------------------Exported Function prototype---------------------*/ ++ ++ ++#endif/* End of HalRf.h */ ++ +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/include/rtl8192c_spec.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/include/rtl8192c_spec.h 2013-07-26 19:36:06.000000000 +0000 +@@ -0,0 +1,1899 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ++******************************************************************************/ ++#ifndef __RTL8192C_SPEC_H__ ++#define __RTL8192C_SPEC_H__ ++ ++#include ++ ++#ifndef BIT ++#define BIT(x) (1 << (x)) ++#endif ++ ++#define BIT0 0x00000001 ++#define BIT1 0x00000002 ++#define BIT2 0x00000004 ++#define BIT3 0x00000008 ++#define BIT4 0x00000010 ++#define BIT5 0x00000020 ++#define BIT6 0x00000040 ++#define BIT7 0x00000080 ++#define BIT8 0x00000100 ++#define BIT9 0x00000200 ++#define BIT10 0x00000400 ++#define BIT11 0x00000800 ++#define BIT12 0x00001000 ++#define BIT13 0x00002000 ++#define BIT14 0x00004000 ++#define BIT15 0x00008000 ++#define BIT16 0x00010000 ++#define BIT17 0x00020000 ++#define BIT18 0x00040000 ++#define BIT19 0x00080000 ++#define BIT20 0x00100000 ++#define BIT21 0x00200000 ++#define BIT22 0x00400000 ++#define BIT23 0x00800000 ++#define BIT24 0x01000000 ++#define BIT25 0x02000000 ++#define BIT26 0x04000000 ++#define BIT27 0x08000000 ++#define BIT28 0x10000000 ++#define BIT29 0x20000000 ++#define BIT30 0x40000000 ++#define BIT31 0x80000000 ++ ++ ++//============================================================ ++// 8192C Regsiter offset definition ++//============================================================ ++ ++ ++//============================================================ ++// ++//============================================================ ++ ++//----------------------------------------------------- ++// ++// 0x0000h ~ 0x00FFh System Configuration ++// ++//----------------------------------------------------- ++#define REG_SYS_ISO_CTRL 0x0000 ++#define REG_SYS_FUNC_EN 0x0002 ++#define REG_APS_FSMCO 0x0004 ++#define REG_SYS_CLKR 0x0008 ++#define REG_9346CR 0x000A ++#define REG_EE_VPD 0x000C ++#define REG_AFE_MISC 0x0010 ++#define REG_SPS0_CTRL 0x0011 ++#define REG_SPS_OCP_CFG 0x0018 ++#define REG_RSV_CTRL 0x001C ++#define REG_RF_CTRL 0x001F ++#define REG_LDOA15_CTRL 0x0020 ++#define REG_LDOV12D_CTRL 0x0021 ++#define REG_LDOHCI12_CTRL 0x0022 ++#define REG_LPLDO_CTRL 0x0023 ++#define REG_AFE_XTAL_CTRL 0x0024 ++#define REG_AFE_PLL_CTRL 0x0028 ++#define REG_EFUSE_CTRL 0x0030 ++#define REG_EFUSE_TEST 0x0034 ++#define REG_PWR_DATA 0x0038 ++#define REG_CAL_TIMER 0x003C ++#define REG_ACLK_MON 0x003E ++#define REG_GPIO_MUXCFG 0x0040 ++#define REG_GPIO_IO_SEL 0x0042 ++#define REG_MAC_PINMUX_CFG 0x0043 ++#define REG_GPIO_PIN_CTRL 0x0044 ++#define REG_GPIO_INTM 0x0048 ++#define REG_LEDCFG0 0x004C ++#define REG_LEDCFG1 0x004D ++#define REG_LEDCFG2 0x004E ++#define REG_LEDCFG3 0x004F ++#define REG_LEDCFG REG_LEDCFG2 ++#define REG_FSIMR 0x0050 ++#define REG_FSISR 0x0054 ++#define REG_HSIMR 0x0058 ++#define REG_HSISR 0x005c ++#define REG_GPIO_PIN_CTRL_2 0x0060 // RTL8723 WIFI/BT/GPS Multi-Function GPIO Pin Control. ++#define REG_GPIO_IO_SEL_2 0x0062 // RTL8723 WIFI/BT/GPS Multi-Function GPIO Select. ++#define REG_MULTI_FUNC_CTRL 0x0068 // RTL8723 WIFI/BT/GPS Multi-Function control source. ++#define REG_MCUFWDL 0x0080 ++#define REG_WOWLAN_REASON 0x0081 ++#define REG_HMEBOX_EXT_0 0x0088 ++#define REG_HMEBOX_EXT_1 0x008A ++#define REG_HMEBOX_EXT_2 0x008C ++#define REG_HMEBOX_EXT_3 0x008E ++#define REG_HOST_SUSP_CNT 0x00BC // Host suspend counter on FPGA platform ++#define REG_EFUSE_ACCESS 0x00CF // Efuse access protection for RTL8723 ++#define REG_BIST_SCAN 0x00D0 ++#define REG_BIST_RPT 0x00D4 ++#define REG_BIST_ROM_RPT 0x00D8 ++#define REG_USB_SIE_INTF 0x00E0 ++#define REG_PCIE_MIO_INTF 0x00E4 ++#define REG_PCIE_MIO_INTD 0x00E8 ++#define REG_HPON_FSM 0x00EC ++#define REG_SYS_CFG 0x00F0 ++#define REG_GPIO_OUTSTS 0x00F4 // For RTL8723 only. ++ ++//----------------------------------------------------- ++// ++// 0x0100h ~ 0x01FFh MACTOP General Configuration ++// ++//----------------------------------------------------- ++#define REG_CR 0x0100 ++#define REG_PBP 0x0104 ++#define REG_TRXDMA_CTRL 0x010C ++#define REG_TRXFF_BNDY 0x0114 ++#define REG_TRXFF_STATUS 0x0118 ++#define REG_RXFF_PTR 0x011C ++#define REG_HIMR 0x0120 ++#define REG_HISR 0x0124 ++#define REG_HIMRE 0x0128 ++#define REG_HISRE 0x012C ++#define REG_CPWM 0x012F ++#define REG_FWIMR 0x0130 ++#define REG_FWISR 0x0134 ++#define REG_PKTBUF_DBG_CTRL 0x0140 ++#define REG_PKTBUF_DBG_DATA_L 0x0144 ++#define REG_PKTBUF_DBG_DATA_H 0x0148 ++ ++#define REG_TC0_CTRL 0x0150 ++#define REG_TC1_CTRL 0x0154 ++#define REG_TC2_CTRL 0x0158 ++#define REG_TC3_CTRL 0x015C ++#define REG_TC4_CTRL 0x0160 ++#define REG_TCUNIT_BASE 0x0164 ++#define REG_MBIST_START 0x0174 ++#define REG_MBIST_DONE 0x0178 ++#define REG_MBIST_FAIL 0x017C ++#define REG_C2HEVT_MSG_NORMAL 0x01A0 ++#define REG_C2HEVT_CLEAR 0x01AF ++#define REG_C2HEVT_MSG_TEST 0x01B8 ++#define REG_MCUTST_1 0x01c0 ++#define REG_FMETHR 0x01C8 ++#define REG_HMETFR 0x01CC ++#define REG_HMEBOX_0 0x01D0 ++#define REG_HMEBOX_1 0x01D4 ++#define REG_HMEBOX_2 0x01D8 ++#define REG_HMEBOX_3 0x01DC ++ ++#define REG_LLT_INIT 0x01E0 ++#define REG_BB_ACCEESS_CTRL 0x01E8 ++#define REG_BB_ACCESS_DATA 0x01EC ++ ++ ++//----------------------------------------------------- ++// ++// 0x0200h ~ 0x027Fh TXDMA Configuration ++// ++//----------------------------------------------------- ++#define REG_RQPN 0x0200 ++#define REG_FIFOPAGE 0x0204 ++#define REG_TDECTRL 0x0208 ++#define REG_TXDMA_OFFSET_CHK 0x020C ++#define REG_TXDMA_STATUS 0x0210 ++#define REG_RQPN_NPQ 0x0214 ++ ++//----------------------------------------------------- ++// ++// 0x0280h ~ 0x02FFh RXDMA Configuration ++// ++//----------------------------------------------------- ++#define REG_RXDMA_AGG_PG_TH 0x0280 ++#define REG_RXPKT_NUM 0x0284 ++#define REG_RXDMA_STATUS 0x0288 ++ ++ ++//----------------------------------------------------- ++// ++// 0x0300h ~ 0x03FFh PCIe ++// ++//----------------------------------------------------- ++#define REG_PCIE_CTRL_REG 0x0300 ++#define REG_INT_MIG 0x0304 // Interrupt Migration ++#define REG_BCNQ_DESA 0x0308 // TX Beacon Descriptor Address ++#define REG_HQ_DESA 0x0310 // TX High Queue Descriptor Address ++#define REG_MGQ_DESA 0x0318 // TX Manage Queue Descriptor Address ++#define REG_VOQ_DESA 0x0320 // TX VO Queue Descriptor Address ++#define REG_VIQ_DESA 0x0328 // TX VI Queue Descriptor Address ++#define REG_BEQ_DESA 0x0330 // TX BE Queue Descriptor Address ++#define REG_BKQ_DESA 0x0338 // TX BK Queue Descriptor Address ++#define REG_RX_DESA 0x0340 // RX Queue Descriptor Address ++#define REG_DBI 0x0348 // Backdoor REG for Access Configuration ++#define REG_MDIO 0x0354 // MDIO for Access PCIE PHY ++#define REG_DBG_SEL 0x0360 // Debug Selection Register ++#define REG_PCIE_HRPWM 0x0361 //PCIe RPWM ++#define REG_PCIE_HCPWM 0x0363 //PCIe CPWM ++#define REG_UART_CTRL 0x0364 // UART Control ++#define REG_UART_TX_DESA 0x0370 // UART TX Descriptor Address ++#define REG_UART_RX_DESA 0x0378 // UART Rx Descriptor Address ++ ++ ++// spec version 11 ++//----------------------------------------------------- ++// ++// 0x0400h ~ 0x047Fh Protocol Configuration ++// ++//----------------------------------------------------- ++#define REG_VOQ_INFORMATION 0x0400 ++#define REG_VIQ_INFORMATION 0x0404 ++#define REG_BEQ_INFORMATION 0x0408 ++#define REG_BKQ_INFORMATION 0x040C ++#define REG_MGQ_INFORMATION 0x0410 ++#define REG_HGQ_INFORMATION 0x0414 ++#define REG_BCNQ_INFORMATION 0x0418 ++ ++ ++#define REG_CPU_MGQ_INFORMATION 0x041C ++#define REG_FWHW_TXQ_CTRL 0x0420 ++#define REG_HWSEQ_CTRL 0x0423 ++#define REG_TXPKTBUF_BCNQ_BDNY 0x0424 ++#define REG_TXPKTBUF_MGQ_BDNY 0x0425 ++#define REG_LIFETIME_EN 0x0426 ++#define REG_MULTI_BCNQ_OFFSET 0x0427 ++#define REG_SPEC_SIFS 0x0428 ++#define REG_RL 0x042A ++#define REG_DARFRC 0x0430 ++#define REG_RARFRC 0x0438 ++#define REG_RRSR 0x0440 ++#define REG_ARFR0 0x0444 ++#define REG_ARFR1 0x0448 ++#define REG_ARFR2 0x044C ++#define REG_ARFR3 0x0450 ++#define REG_AGGLEN_LMT 0x0458 ++#define REG_AMPDU_MIN_SPACE 0x045C ++#define REG_TXPKTBUF_WMAC_LBK_BF_HD 0x045D ++#define REG_FAST_EDCA_CTRL 0x0460 ++#define REG_RD_RESP_PKT_TH 0x0463 ++#define REG_INIRTS_RATE_SEL 0x0480 ++#define REG_INIDATA_RATE_SEL 0x0484 ++#define REG_POWER_STATUS 0x04A4 ++#define REG_POWER_STAGE1 0x04B4 ++#define REG_POWER_STAGE2 0x04B8 ++#define REG_PKT_VO_VI_LIFE_TIME 0x04C0 ++#define REG_PKT_BE_BK_LIFE_TIME 0x04C2 ++#define REG_STBC_SETTING 0x04C4 ++#define REG_PROT_MODE_CTRL 0x04C8 ++#define REG_MAX_AGGR_NUM 0x04CA ++#define REG_RTS_MAX_AGGR_NUM 0x04CB ++#define REG_BAR_MODE_CTRL 0x04CC ++#define REG_RA_TRY_RATE_AGG_LMT 0x04CF ++#define REG_NQOS_SEQ 0x04DC ++#define REG_QOS_SEQ 0x04DE ++#define REG_NEED_CPU_HANDLE 0x04E0 ++#define REG_PKT_LOSE_RPT 0x04E1 ++#define REG_PTCL_ERR_STATUS 0x04E2 ++#define REG_DUMMY 0x04FC ++ ++ ++ ++//----------------------------------------------------- ++// ++// 0x0500h ~ 0x05FFh EDCA Configuration ++// ++//----------------------------------------------------- ++#define REG_EDCA_VO_PARAM 0x0500 ++#define REG_EDCA_VI_PARAM 0x0504 ++#define REG_EDCA_BE_PARAM 0x0508 ++#define REG_EDCA_BK_PARAM 0x050C ++#define REG_BCNTCFG 0x0510 ++#define REG_PIFS 0x0512 ++#define REG_RDG_PIFS 0x0513 ++#define REG_SIFS_CCK 0x0514 ++#define REG_SIFS_OFDM 0x0516 ++#define REG_SIFS_CTX 0x0514 ++#define REG_SIFS_TRX 0x0516 ++#define REG_AGGR_BREAK_TIME 0x051A ++#define REG_SLOT 0x051B ++#define REG_TX_PTCL_CTRL 0x0520 ++#define REG_TXPAUSE 0x0522 ++#define REG_DIS_TXREQ_CLR 0x0523 ++#define REG_RD_CTRL 0x0524 ++#define REG_TBTT_PROHIBIT 0x0540 ++#define REG_RD_NAV_NXT 0x0544 ++#define REG_NAV_PROT_LEN 0x0546 ++#define REG_BCN_CTRL 0x0550 ++#define REG_BCN_CTRL_1 0x0551 ++#define REG_MBID_NUM 0x0552 ++#define REG_DUAL_TSF_RST 0x0553 ++#define REG_BCN_INTERVAL 0x0554 // The same as REG_MBSSID_BCN_SPACE ++#define REG_MBSSID_BCN_SPACE 0x0554 ++#define REG_DRVERLYINT 0x0558 ++#define REG_BCNDMATIM 0x0559 ++#define REG_ATIMWND 0x055A ++#define REG_BCN_MAX_ERR 0x055D ++#define REG_RXTSF_OFFSET_CCK 0x055E ++#define REG_RXTSF_OFFSET_OFDM 0x055F ++#define REG_TSFTR 0x0560 ++#define REG_INIT_TSFTR 0x0564 ++#define REG_PSTIMER 0x0580 ++#define REG_TIMER0 0x0584 ++#define REG_TIMER1 0x0588 ++#define REG_ACMHWCTRL 0x05C0 ++#define REG_ACMRSTCTRL 0x05C1 ++#define REG_ACMAVG 0x05C2 ++#define REG_VO_ADMTIME 0x05C4 ++#define REG_VI_ADMTIME 0x05C6 ++#define REG_BE_ADMTIME 0x05C8 ++#define REG_EDCA_RANDOM_GEN 0x05CC ++#define REG_SCH_TXCMD 0x05D0 ++ ++ ++//----------------------------------------------------- ++// ++// 0x0600h ~ 0x07FFh WMAC Configuration ++// ++//----------------------------------------------------- ++#define REG_APSD_CTRL 0x0600 ++#define REG_BWOPMODE 0x0603 ++#define REG_TCR 0x0604 ++#define REG_RCR 0x0608 ++#define REG_RX_PKT_LIMIT 0x060C ++#define REG_RX_DLK_TIME 0x060D ++#define REG_RX_DRVINFO_SZ 0x060F ++ ++#define REG_MACID 0x0610 ++#define REG_BSSID 0x0618 ++#define REG_MAR 0x0620 ++#define REG_MBIDCAMCFG 0x0628 ++ ++#define REG_USTIME_EDCA 0x0638 ++#define REG_MAC_SPEC_SIFS 0x063A ++ ++// 20100719 Joseph: Hardware register definition change. (HW datasheet v54) ++#define REG_R2T_SIFS 0x063C // [15:8]SIFS_R2T_OFDM, [7:0]SIFS_R2T_CCK ++#define REG_T2T_SIFS 0x063E // [15:8]SIFS_T2T_OFDM, [7:0]SIFS_T2T_CCK ++#define REG_ACKTO 0x0640 ++#define REG_CTS2TO 0x0641 ++#define REG_EIFS 0x0642 ++ ++//WMA, BA, CCX ++#define REG_NAV_CTRL 0x0650 ++#define REG_BACAMCMD 0x0654 ++#define REG_BACAMCONTENT 0x0658 ++#define REG_LBDLY 0x0660 ++#define REG_FWDLY 0x0661 ++#define REG_RXERR_RPT 0x0664 ++#define REG_WMAC_TRXPTCL_CTL 0x0668 ++ ++ ++// Security ++#define REG_CAMCMD 0x0670 ++#define REG_CAMWRITE 0x0674 ++#define REG_CAMREAD 0x0678 ++#define REG_CAMDBG 0x067C ++#define REG_SECCFG 0x0680 ++ ++// Power ++#define REG_WOW_CTRL 0x0690 ++#define REG_PSSTATUS 0x0691 ++#define REG_PS_RX_INFO 0x0692 ++#define REG_LPNAV_CTRL 0x0694 ++#define REG_WKFMCAM_CMD 0x0698 ++#define REG_WKFMCAM_RWD 0x069C ++#define REG_RXFLTMAP0 0x06A0 ++#define REG_RXFLTMAP1 0x06A2 ++#define REG_RXFLTMAP2 0x06A4 ++#define REG_BCN_PSR_RPT 0x06A8 ++#define REG_CALB32K_CTRL 0x06AC ++#define REG_PKT_MON_CTRL 0x06B4 ++#define REG_BT_COEX_TABLE 0x06C0 ++#define REG_WMAC_RESP_TXINFO 0x06D8 ++ ++ ++//----------------------------------------------------- ++// ++// 0xFE00h ~ 0xFE55h USB Configuration ++// ++//----------------------------------------------------- ++#define REG_USB_INFO 0xFE17 ++#define REG_USB_SPECIAL_OPTION 0xFE55 ++#define REG_USB_DMA_AGG_TO 0xFE5B ++#define REG_USB_AGG_TO 0xFE5C ++#define REG_USB_AGG_TH 0xFE5D ++ ++// For test chip ++#define REG_TEST_USB_TXQS 0xFE48 ++#define REG_TEST_SIE_VID 0xFE60 // 0xFE60~0xFE61 ++#define REG_TEST_SIE_PID 0xFE62 // 0xFE62~0xFE63 ++#define REG_TEST_SIE_OPTIONAL 0xFE64 ++#define REG_TEST_SIE_CHIRP_K 0xFE65 ++#define REG_TEST_SIE_PHY 0xFE66 // 0xFE66~0xFE6B ++#define REG_TEST_SIE_MAC_ADDR 0xFE70 // 0xFE70~0xFE75 ++#define REG_TEST_SIE_STRING 0xFE80 // 0xFE80~0xFEB9 ++ ++ ++// For normal chip ++#define REG_NORMAL_SIE_VID 0xFE60 // 0xFE60~0xFE61 ++#define REG_NORMAL_SIE_PID 0xFE62 // 0xFE62~0xFE63 ++#define REG_NORMAL_SIE_OPTIONAL 0xFE64 ++#define REG_NORMAL_SIE_EP 0xFE65 // 0xFE65~0xFE67 ++#define REG_NORMAL_SIE_PHY 0xFE68 // 0xFE68~0xFE6B ++#define REG_NORMAL_SIE_OPTIONAL2 0xFE6C ++#define REG_NORMAL_SIE_GPS_EP 0xFE6D // 0xFE6D, for RTL8723 only. ++#define REG_NORMAL_SIE_MAC_ADDR 0xFE70 // 0xFE70~0xFE75 ++#define REG_NORMAL_SIE_STRING 0xFE80 // 0xFE80~0xFEDF ++ ++ ++//----------------------------------------------------- ++// ++// Redifine 8192C register definition for compatibility ++// ++//----------------------------------------------------- ++ ++// TODO: use these definition when using REG_xxx naming rule. ++// NOTE: DO NOT Remove these definition. Use later. ++ ++#define SYS_ISO_CTRL REG_SYS_ISO_CTRL // System Isolation Interface Control. ++#define SYS_FUNC_EN REG_SYS_FUNC_EN // System Function Enable. ++#define SYS_CLK REG_SYS_CLKR ++#define CR9346 REG_9346CR // 93C46/93C56 Command Register. ++#define EFUSE_CTRL REG_EFUSE_CTRL // E-Fuse Control. ++#define EFUSE_TEST REG_EFUSE_TEST // E-Fuse Test. ++#define MSR (REG_CR + 2) // Media Status register ++#define ISR REG_HISR ++#define TSFR REG_TSFTR // Timing Sync Function Timer Register. ++ ++#define MACIDR0 REG_MACID // MAC ID Register, Offset 0x0050-0x0053 ++#define MACIDR4 (REG_MACID + 4) // MAC ID Register, Offset 0x0054-0x0055 ++ ++#define PBP REG_PBP ++ ++// Redifine MACID register, to compatible prior ICs. ++#define IDR0 MACIDR0 ++#define IDR4 MACIDR4 ++ ++ ++// ++// 9. Security Control Registers (Offset: ) ++// ++#define RWCAM REG_CAMCMD //IN 8190 Data Sheet is called CAMcmd ++#define WCAMI REG_CAMWRITE // Software write CAM input content ++#define RCAMO REG_CAMREAD // Software read/write CAM config ++#define CAMDBG REG_CAMDBG ++#define SECR REG_SECCFG //Security Configuration Register ++ ++// Unused register ++#define UnusedRegister 0x1BF ++#define DCAM UnusedRegister ++#define PSR UnusedRegister ++#define BBAddr UnusedRegister ++#define PhyDataR UnusedRegister ++ ++#define InvalidBBRFValue 0x12345678 ++ ++// Min Spacing related settings. ++#define MAX_MSS_DENSITY_2T 0x13 ++#define MAX_MSS_DENSITY_1T 0x0A ++ ++//---------------------------------------------------------------------------- ++// 8192C Cmd9346CR bits (Offset 0xA, 16bit) ++//---------------------------------------------------------------------------- ++#define CmdEEPROM_En BIT5 // EEPROM enable when set 1 ++#define CmdEERPOMSEL BIT4 // System EEPROM select, 0: boot from E-FUSE, 1: The EEPROM used is 9346 ++#define Cmd9346CR_9356SEL BIT4 ++#define AutoLoadEEPROM (CmdEEPROM_En|CmdEERPOMSEL) ++#define AutoLoadEFUSE CmdEEPROM_En ++ ++//---------------------------------------------------------------------------- ++// 8192C GPIO MUX Configuration Register (offset 0x40, 4 byte) ++//---------------------------------------------------------------------------- ++#define GPIOSEL_GPIO 0 ++#define GPIOSEL_ENBT BIT5 ++ ++//---------------------------------------------------------------------------- ++// 8192C GPIO PIN Control Register (offset 0x44, 4 byte) ++//---------------------------------------------------------------------------- ++#define GPIO_IN REG_GPIO_PIN_CTRL // GPIO pins input value ++#define GPIO_OUT (REG_GPIO_PIN_CTRL+1) // GPIO pins output value ++#define GPIO_IO_SEL (REG_GPIO_PIN_CTRL+2) // GPIO pins output enable when a bit is set to "1"; otherwise, input is configured. ++#define GPIO_MOD (REG_GPIO_PIN_CTRL+3) ++ ++//---------------------------------------------------------------------------- ++// 8192C (MSR) Media Status Register (Offset 0x4C, 8 bits) ++//---------------------------------------------------------------------------- ++/* ++Network Type ++00: No link ++01: Link in ad hoc network ++10: Link in infrastructure network ++11: AP mode ++Default: 00b. ++*/ ++#define MSR_NOLINK 0x00 ++#define MSR_ADHOC 0x01 ++#define MSR_INFRA 0x02 ++#define MSR_AP 0x03 ++ ++// ++// 6. Adaptive Control Registers (Offset: 0x0160 - 0x01CF) ++// ++//---------------------------------------------------------------------------- ++// 8192C Response Rate Set Register (offset 0x181, 24bits) ++//---------------------------------------------------------------------------- ++#define RRSR_RSC_OFFSET 21 ++#define RRSR_SHORT_OFFSET 23 ++#define RRSR_RSC_BW_40M 0x600000 ++#define RRSR_RSC_UPSUBCHNL 0x400000 ++#define RRSR_RSC_LOWSUBCHNL 0x200000 ++#define RRSR_SHORT 0x800000 ++#define RRSR_1M BIT0 ++#define RRSR_2M BIT1 ++#define RRSR_5_5M BIT2 ++#define RRSR_11M BIT3 ++#define RRSR_6M BIT4 ++#define RRSR_9M BIT5 ++#define RRSR_12M BIT6 ++#define RRSR_18M BIT7 ++#define RRSR_24M BIT8 ++#define RRSR_36M BIT9 ++#define RRSR_48M BIT10 ++#define RRSR_54M BIT11 ++#define RRSR_MCS0 BIT12 ++#define RRSR_MCS1 BIT13 ++#define RRSR_MCS2 BIT14 ++#define RRSR_MCS3 BIT15 ++#define RRSR_MCS4 BIT16 ++#define RRSR_MCS5 BIT17 ++#define RRSR_MCS6 BIT18 ++#define RRSR_MCS7 BIT19 ++#define BRSR_AckShortPmb BIT23 ++// CCK ACK: use Short Preamble or not ++ ++ ++//---------------------------------------------------------------------------- ++// 8192C Rate Definition ++//---------------------------------------------------------------------------- ++//CCK ++#define RATR_1M 0x00000001 ++#define RATR_2M 0x00000002 ++#define RATR_55M 0x00000004 ++#define RATR_11M 0x00000008 ++//OFDM ++#define RATR_6M 0x00000010 ++#define RATR_9M 0x00000020 ++#define RATR_12M 0x00000040 ++#define RATR_18M 0x00000080 ++#define RATR_24M 0x00000100 ++#define RATR_36M 0x00000200 ++#define RATR_48M 0x00000400 ++#define RATR_54M 0x00000800 ++//MCS 1 Spatial Stream ++#define RATR_MCS0 0x00001000 ++#define RATR_MCS1 0x00002000 ++#define RATR_MCS2 0x00004000 ++#define RATR_MCS3 0x00008000 ++#define RATR_MCS4 0x00010000 ++#define RATR_MCS5 0x00020000 ++#define RATR_MCS6 0x00040000 ++#define RATR_MCS7 0x00080000 ++//MCS 2 Spatial Stream ++#define RATR_MCS8 0x00100000 ++#define RATR_MCS9 0x00200000 ++#define RATR_MCS10 0x00400000 ++#define RATR_MCS11 0x00800000 ++#define RATR_MCS12 0x01000000 ++#define RATR_MCS13 0x02000000 ++#define RATR_MCS14 0x04000000 ++#define RATR_MCS15 0x08000000 ++ ++ ++// NOTE: For 92CU - Ziv ++//CCK ++#define RATE_1M BIT(0) ++#define RATE_2M BIT(1) ++#define RATE_5_5M BIT(2) ++#define RATE_11M BIT(3) ++//OFDM ++#define RATE_6M BIT(4) ++#define RATE_9M BIT(5) ++#define RATE_12M BIT(6) ++#define RATE_18M BIT(7) ++#define RATE_24M BIT(8) ++#define RATE_36M BIT(9) ++#define RATE_48M BIT(10) ++#define RATE_54M BIT(11) ++//MCS 1 Spatial Stream ++#define RATE_MCS0 BIT(12) ++#define RATE_MCS1 BIT(13) ++#define RATE_MCS2 BIT(14) ++#define RATE_MCS3 BIT(15) ++#define RATE_MCS4 BIT(16) ++#define RATE_MCS5 BIT(17) ++#define RATE_MCS6 BIT(18) ++#define RATE_MCS7 BIT(19) ++//MCS 2 Spatial Stream ++#define RATE_MCS8 BIT(20) ++#define RATE_MCS9 BIT(21) ++#define RATE_MCS10 BIT(22) ++#define RATE_MCS11 BIT(23) ++#define RATE_MCS12 BIT(24) ++#define RATE_MCS13 BIT(25) ++#define RATE_MCS14 BIT(26) ++#define RATE_MCS15 BIT(27) ++ ++ ++ ++ ++// ALL CCK Rate ++#define RATE_ALL_CCK RATR_1M|RATR_2M|RATR_55M|RATR_11M ++#define RATE_ALL_OFDM_AG RATR_6M|RATR_9M|RATR_12M|RATR_18M|RATR_24M|\ ++ RATR_36M|RATR_48M|RATR_54M ++#define RATE_ALL_OFDM_1SS RATR_MCS0|RATR_MCS1|RATR_MCS2|RATR_MCS3 |\ ++ RATR_MCS4|RATR_MCS5|RATR_MCS6 |RATR_MCS7 ++#define RATE_ALL_OFDM_2SS RATR_MCS8|RATR_MCS9 |RATR_MCS10|RATR_MCS11|\ ++ RATR_MCS12|RATR_MCS13|RATR_MCS14|RATR_MCS15 ++ ++//---------------------------------------------------------------------------- ++// 8192C BW_OPMODE bits (Offset 0x203, 8bit) ++//---------------------------------------------------------------------------- ++#define BW_OPMODE_20MHZ BIT2 ++#define BW_OPMODE_5G BIT1 ++#define BW_OPMODE_11J BIT0 ++ ++ ++//---------------------------------------------------------------------------- ++// 8192C CAM Config Setting (offset 0x250, 1 byte) ++//---------------------------------------------------------------------------- ++#define CAM_VALID BIT15 ++#define CAM_NOTVALID 0x0000 ++#define CAM_USEDK BIT5 ++ ++#define CAM_CONTENT_COUNT 8 ++ ++#define CAM_NONE 0x0 ++#define CAM_WEP40 0x01 ++#define CAM_TKIP 0x02 ++#define CAM_AES 0x04 ++#define CAM_WEP104 0x05 ++ ++#define TOTAL_CAM_ENTRY 32 ++#define HALF_CAM_ENTRY 16 ++ ++#define CAM_CONFIG_USEDK _TRUE ++#define CAM_CONFIG_NO_USEDK _FALSE ++ ++#define CAM_WRITE BIT16 ++#define CAM_READ 0x00000000 ++#define CAM_POLLINIG BIT31 ++ ++#define SCR_UseDK 0x01 ++#define SCR_TxSecEnable 0x02 ++#define SCR_RxSecEnable 0x04 ++ ++ ++// ++// 12. Host Interrupt Status Registers (Offset: 0x0300 - 0x030F) ++// ++//---------------------------------------------------------------------------- ++// 8190 IMR/ISR bits (offset 0xfd, 8bits) ++//---------------------------------------------------------------------------- ++#define IMR8190_DISABLED 0x0 ++// IMR DW0 Bit 0-31 ++#define IMR_BCNDMAINT6 BIT31 // Beacon DMA Interrupt 6 ++#define IMR_BCNDMAINT5 BIT30 // Beacon DMA Interrupt 5 ++#define IMR_BCNDMAINT4 BIT29 // Beacon DMA Interrupt 4 ++#define IMR_BCNDMAINT3 BIT28 // Beacon DMA Interrupt 3 ++#define IMR_BCNDMAINT2 BIT27 // Beacon DMA Interrupt 2 ++#define IMR_BCNDMAINT1 BIT26 // Beacon DMA Interrupt 1 ++#define IMR_BCNDOK8 BIT25 // Beacon Queue DMA OK Interrup 8 ++#define IMR_BCNDOK7 BIT24 // Beacon Queue DMA OK Interrup 7 ++#define IMR_BCNDOK6 BIT23 // Beacon Queue DMA OK Interrup 6 ++#define IMR_BCNDOK5 BIT22 // Beacon Queue DMA OK Interrup 5 ++#define IMR_BCNDOK4 BIT21 // Beacon Queue DMA OK Interrup 4 ++#define IMR_BCNDOK3 BIT20 // Beacon Queue DMA OK Interrup 3 ++#define IMR_BCNDOK2 BIT19 // Beacon Queue DMA OK Interrup 2 ++#define IMR_BCNDOK1 BIT18 // Beacon Queue DMA OK Interrup 1 ++#define IMR_TIMEOUT2 BIT17 // Timeout interrupt 2 ++#define IMR_TIMEOUT1 BIT16 // Timeout interrupt 1 ++#define IMR_TXFOVW BIT15 // Transmit FIFO Overflow ++#define IMR_PSTIMEOUT BIT14 // Power save time out interrupt ++#define IMR_BcnInt BIT13 // Beacon DMA Interrupt 0 ++#define IMR_RXFOVW BIT12 // Receive FIFO Overflow ++#define IMR_RDU BIT11 // Receive Descriptor Unavailable ++#define IMR_ATIMEND BIT10 // For 92C,ATIM Window End Interrupt ++#define IMR_BDOK BIT9 // Beacon Queue DMA OK Interrup ++#define IMR_HIGHDOK BIT8 // High Queue DMA OK Interrupt ++#define IMR_TBDOK BIT7 // Transmit Beacon OK interrup ++#define IMR_MGNTDOK BIT6 // Management Queue DMA OK Interrupt ++#define IMR_TBDER BIT5 // For 92C,Transmit Beacon Error Interrupt ++#define IMR_BKDOK BIT4 // AC_BK DMA OK Interrupt ++#define IMR_BEDOK BIT3 // AC_BE DMA OK Interrupt ++#define IMR_VIDOK BIT2 // AC_VI DMA OK Interrupt ++#define IMR_VODOK BIT1 // AC_VO DMA Interrupt ++#define IMR_ROK BIT0 // Receive DMA OK Interrupt ++ ++#define IMR_RX_MASK (IMR_ROK|IMR_RDU|IMR_RXFOVW) ++#define IMR_TX_MASK (IMR_VODOK|IMR_VIDOK|IMR_BEDOK|IMR_BKDOK|IMR_MGNTDOK|IMR_HIGHDOK|IMR_BDOK) ++ ++// 13. Host Interrupt Status Extension Register (Offset: 0x012C-012Eh) ++#define IMR_TXERR BIT11 ++#define IMR_RXERR BIT10 ++#define IMR_C2HCMD BIT9 ++#define IMR_CPWM BIT8 ++//RSVD [2-7] ++#define IMR_OCPINT BIT1 ++#define IMR_WLANOFF BIT0 ++ ++ ++ ++//---------------------------------------------------------------------------- ++// 8192C EFUSE ++//---------------------------------------------------------------------------- ++#define HWSET_MAX_SIZE 128 ++ ++ ++//---------------------------------------------------------------------------- ++// 8192C EEPROM/EFUSE share register definition. ++//---------------------------------------------------------------------------- ++ ++// ++// Default Value for EEPROM or EFUSE!!! ++// ++#define EEPROM_Default_TSSI 0x0 ++#define EEPROM_Default_TxPowerDiff 0x0 ++#define EEPROM_Default_CrystalCap 0x5 ++#define EEPROM_Default_BoardType 0x02 // Default: 2X2, RTL8192CE(QFPN68) ++#define EEPROM_Default_TxPower 0x1010 ++#define EEPROM_Default_HT2T_TxPwr 0x10 ++ ++#define EEPROM_Default_LegacyHTTxPowerDiff 0x3 ++#define EEPROM_Default_ThermalMeter 0x12 ++ ++#define EEPROM_Default_AntTxPowerDiff 0x0 ++#define EEPROM_Default_TxPwDiff_CrystalCap 0x5 ++#define EEPROM_Default_TxPowerLevel 0x22 ++#define EEPROM_Default_HT40_2SDiff 0x0 ++#define EEPROM_Default_HT20_Diff 2 // HT20<->40 default Tx Power Index Difference ++#define EEPROM_Default_LegacyHTTxPowerDiff 0x3 ++#define EEPROM_Default_HT40_PwrMaxOffset 0 ++#define EEPROM_Default_HT20_PwrMaxOffset 0 ++ ++// For debug ++#define EEPROM_Default_PID 0x1234 ++#define EEPROM_Default_VID 0x5678 ++#define EEPROM_Default_CustomerID 0xAB ++#define EEPROM_Default_SubCustomerID 0xCD ++#define EEPROM_Default_Version 0 ++ ++#define EEPROM_CHANNEL_PLAN_FCC 0x0 ++#define EEPROM_CHANNEL_PLAN_IC 0x1 ++#define EEPROM_CHANNEL_PLAN_ETSI 0x2 ++#define EEPROM_CHANNEL_PLAN_SPAIN 0x3 ++#define EEPROM_CHANNEL_PLAN_FRANCE 0x4 ++#define EEPROM_CHANNEL_PLAN_MKK 0x5 ++#define EEPROM_CHANNEL_PLAN_MKK1 0x6 ++#define EEPROM_CHANNEL_PLAN_ISRAEL 0x7 ++#define EEPROM_CHANNEL_PLAN_TELEC 0x8 ++#define EEPROM_CHANNEL_PLAN_GLOBAL_DOMAIN 0x9 ++#define EEPROM_CHANNEL_PLAN_WORLD_WIDE_13 0xA ++#define EEPROM_CHANNEL_PLAN_NCC 0xB ++#define EEPROM_USB_OPTIONAL1 0xE ++#define EEPROM_CHANNEL_PLAN_BY_HW_MASK 0x80 ++ ++ ++#define EEPROM_CID_DEFAULT 0x0 ++#define EEPROM_CID_TOSHIBA 0x4 ++#define EEPROM_CID_CCX 0x10 // CCX test. By Bruce, 2009-02-25. ++#define EEPROM_CID_QMI 0x0D ++#define EEPROM_CID_WHQL 0xFE // added by chiyoko for dtm, 20090108 ++ ++ ++#define RTL_EEPROM_ID 0x8129 ++ ++ ++#ifdef CONFIG_PCI_HCI ++#define RT_IBSS_INT_MASKS (IMR_BcnInt | IMR_TBDOK | IMR_TBDER) ++#define RT_AC_INT_MASKS (IMR_VIDOK | IMR_VODOK | IMR_BEDOK|IMR_BKDOK) ++#define RT_BSS_INT_MASKS (RT_IBSS_INT_MASKS) ++ ++// ++// Interface type. ++// ++typedef enum _INTERFACE_SELECT_8192CPCIe{ ++ INTF_SEL0_SOLO_MINICARD = 0, // WiFi solo-mCard ++ INTF_SEL1_BT_COMBO_MINICARD = 1, // WiFi+BT combo-mCard ++ INTF_SEL2_PCIe = 2, // PCIe Card ++} INTERFACE_SELECT_8192CPCIe, *PINTERFACE_SELECT_8192CPCIe; ++ ++#define RTL8190_EEPROM_ID 0x8129 // 0-1 ++#define EEPROM_HPON 0x02 // LDO settings.2-5 ++#define EEPROM_CLK 0x06 // Clock settings.6-7 ++#define EEPROM_TESTR 0x08 // SE Test mode.8 ++ ++#define EEPROM_VID 0x0A // SE Vendor ID.A-B ++#define EEPROM_DID 0x0C // SE Device ID. C-D ++#define EEPROM_SVID 0x0E // SE Vendor ID.E-F ++#define EEPROM_SMID 0x10 // SE PCI Subsystem ID. 10-11 ++ ++#define EEPROM_MAC_ADDR 0x16 // SEMAC Address. 12-17 ++ ++//---------------------------------------------------------------- ++// Ziv - Let PCIe and USB use the same define. Modify address mapping later. ++#define EEPROM_CCK_TX_PWR_INX 0x5A ++#define EEPROM_HT40_1S_TX_PWR_INX 0x60 ++#define EEPROM_HT40_2S_TX_PWR_INX_DIFF 0x66 ++#define EEPROM_HT20_TX_PWR_INX_DIFF 0x69 ++#define EEPROM_OFDM_TX_PWR_INX_DIFF 0x6C ++#define EEPROM_HT40_MAX_PWR_OFFSET 0x6F ++#define EEPROM_HT20_MAX_PWR_OFFSET 0x72 ++ ++#define EEPROM_CHANNEL_PLAN 0x75 ++#define EEPROM_TSSI_A 0x76 ++#define EEPROM_TSSI_B 0x77 ++#define EEPROM_THERMAL_METER 0x78 ++#define EEPROM_RF_OPT1 0x79 ++#define EEPROM_RF_OPT2 0x7A ++#define EEPROM_RF_OPT3 0x7B ++#define EEPROM_RF_OPT4 0x7C ++#define EEPROM_VERSION 0x7E ++#define EEPROM_CUSTOMER_ID 0x7F ++ ++#define EEPROM_NORMAL_BoardType EEPROM_RF_OPT1 //[7:5] ++ ++#endif ++ ++#ifdef CONFIG_USB_HCI ++ ++//should be renamed and moved to another file ++typedef enum _BOARD_TYPE_8192CUSB{ ++ BOARD_USB_DONGLE = 0, // USB dongle ++ BOARD_USB_High_PA = 1, // USB dongle with high power PA ++ BOARD_MINICARD = 2, // Minicard ++ BOARD_USB_SOLO = 3, // USB solo-Slim module ++ BOARD_USB_COMBO = 4, // USB Combo-Slim module ++} BOARD_TYPE_8192CUSB, *PBOARD_TYPE_8192CUSB; ++ ++#define SUPPORT_HW_RADIO_DETECT(pHalData) (pHalData->BoardType == BOARD_MINICARD||\ ++ pHalData->BoardType == BOARD_USB_SOLO||\ ++ pHalData->BoardType == BOARD_USB_COMBO) ++ ++//--------------------------------------------------------------- ++// EEPROM address for Test chip ++//--------------------------------------------------------------- ++#define EEPROM_TEST_USB_OPT 0x0E ++#define EEPROM_TEST_CHIRP_K 0x0F ++#define EEPROM_TEST_EP_SETTING 0x0E ++#define EEPROM_TEST_USB_PHY 0x10 ++ ++ ++//--------------------------------------------------------------- ++// EEPROM address for Normal chip ++//--------------------------------------------------------------- ++#define EEPROM_NORMAL_USB_OPT 0x0E ++#define EEPROM_NORMAL_CHIRP_K 0x0E // Changed ++#define EEPROM_NORMAL_EP_SETTING 0x0F // Changed ++#define EEPROM_NORMAL_USB_PHY 0x12 // Changed ++ ++ ++// Test chip and normal chip common define ++//--------------------------------------------------------------- ++// EEPROM address for both ++//--------------------------------------------------------------- ++#define EEPROM_ID0 0x00 ++#define EEPROM_ID1 0x01 ++#define EEPROM_RTK_RSV1 0x02 ++#define EEPROM_RTK_RSV2 0x03 ++#define EEPROM_RTK_RSV3 0x04 ++#define EEPROM_RTK_RSV4 0x05 ++#define EEPROM_RTK_RSV5 0x06 ++#define EEPROM_DBG_SEL 0x07 ++#define EEPROM_RTK_RSV6 0x08 ++#define EEPROM_VID 0x0A ++#define EEPROM_PID 0x0C ++ ++#define EEPROM_MAC_ADDR 0x16 ++#define EEPROM_STRING 0x1C ++#define EEPROM_SUBCUSTOMER_ID 0x59 ++#define EEPROM_CCK_TX_PWR_INX 0x5A ++#define EEPROM_HT40_1S_TX_PWR_INX 0x60 ++#define EEPROM_HT40_2S_TX_PWR_INX_DIFF 0x66 ++#define EEPROM_HT20_TX_PWR_INX_DIFF 0x69 ++#define EEPROM_OFDM_TX_PWR_INX_DIFF 0x6C ++#define EEPROM_HT40_MAX_PWR_OFFSET 0x6F ++#define EEPROM_HT20_MAX_PWR_OFFSET 0x72 ++ ++#define EEPROM_CHANNEL_PLAN 0x75 ++#define EEPROM_TSSI_A 0x76 ++#define EEPROM_TSSI_B 0x77 ++#define EEPROM_THERMAL_METER 0x78 ++#define EEPROM_RF_OPT1 0x79 ++#define EEPROM_RF_OPT2 0x7A ++#define EEPROM_RF_OPT3 0x7B ++#define EEPROM_RF_OPT4 0x7C ++#define EEPROM_VERSION 0x7E ++#define EEPROM_CUSTOMER_ID 0x7F ++ ++#define EEPROM_BoardType 0x54 //0x0: RTL8188SU, 0x1: RTL8191SU, 0x2: RTL8192SU, 0x3: RTL8191GU ++#define EEPROM_TxPwIndex 0x5C //0x5C-0x76, Tx Power index. ++#define EEPROM_PwDiff 0x67 // Difference of gain index between legacy and high throughput OFDM. ++ ++#define EEPROM_TxPowerCCK 0x5A // CCK Tx Power ++ ++// 2009/02/09 Cosa Add for SD3 requirement ++#define EEPROM_TX_PWR_HT20_DIFF 0x6e// HT20 Tx Power Index Difference ++#define DEFAULT_HT20_TXPWR_DIFF 2 // HT20<->40 default Tx Power Index Difference ++#define EEPROM_TX_PWR_OFDM_DIFF 0x71// OFDM Tx Power Index Difference ++ ++#define EEPROM_TxPWRGroup 0x73// Power diff for channel group ++#define EEPROM_Regulatory 0x79// Check if power safety is need ++ ++#define EEPROM_BLUETOOTH_COEXIST 0x7E // 92cu, 0x7E[4] ++#define EEPROM_NORMAL_BoardType EEPROM_RF_OPT1 //[7:5] ++#define BOARD_TYPE_NORMAL_MASK 0xE0 ++#define BOARD_TYPE_TEST_MASK 0x0F ++#define EEPROM_EASY_REPLACEMENT 0x50//BIT0 1 for build-in module, 0 for external dongle ++//------------------------------------------------------------- ++// EEPROM content definitions ++//------------------------------------------------------------- ++#define OS_LINK_SPEED BIT(5) ++ ++#define BOARD_TYPE_MASK 0xF ++ ++#define BT_COEXISTENCE BIT(4) ++#define BT_CO_SHIFT 4 ++ ++#define EP_NUMBER_MASK 0x30 //bit 4:5 0Eh ++#define EP_NUMBER_SHIFT 4 ++ ++ ++#define USB_PHY_PARA_SIZE 5 ++ ++ ++//------------------------------------------------------------- ++// EEPROM default value definitions ++//------------------------------------------------------------- ++// Use 0xABCD instead of 0x8192 for debug ++#define EEPROM_DEF_ID_0 0xCD // Byte 0x00 ++#define EEPROM_DEF_ID_1 0xAB // Byte 0x01 ++ ++#define EEPROM_DEF_RTK_RSV_A3 0x74 // Byte 0x03 ++#define EEPROM_DEF_RTK_RSV_A4 0x6D // Byte 0x04 ++#define EEPROM_DEF_RTK_RSV_A8 0xFF // Byte 0x08 ++ ++#define EEPROM_DEF_VID_0 0x0A // Byte 0x0A ++#define EEPROM_DEF_VID_1 0x0B ++ ++#define EEPROM_DEF_PID_0 0x92 // Byte 0x0C ++#define EEPROM_DEF_PID_1 0x81 ++ ++ ++#define EEPROM_TEST_DEF_USB_OPT 0x80 // Byte 0x0E ++#define EEPROM_NORMAL_DEF_USB_OPT 0x00 // Byte 0x0E ++ ++#define EEPROM_DEF_CHIRPK 0x15 // Byte 0x0F ++ ++#define EEPROM_DEF_USB_PHY_0 0x85 // Byte 0x10 ++#define EEPROM_DEF_USB_PHY_1 0x62 // Byte 0x11 ++#define EEPROM_DEF_USB_PHY_2 0x9E // Byte 0x12 ++#define EEPROM_DEF_USB_PHY_3 0x06 // Byte 0x13 ++ ++#define EEPROM_DEF_TSSI_A 0x09 // Byte 0x78 ++#define EEPROM_DEF_TSSI_B 0x09 // Byte 0x79 ++ ++ ++#define EEPROM_DEF_THERMAL_METER 0x12 // Byte 0x7A ++ ++#define RF_OPTION1 0x79// Check if power safety spec is need ++#define RF_OPTION2 0x7A ++#define RF_OPTION3 0x7B ++#define RF_OPTION4 0x7C ++ ++ ++#define EEPROM_USB_SN BIT(0) ++#define EEPROM_USB_REMOTE_WAKEUP BIT(1) ++#define EEPROM_USB_DEVICE_PWR BIT(2) ++#define EEPROM_EP_NUMBER (BIT(3)|BIT(4)) ++ ++#if 0 ++#define EEPROM_CHANNEL_PLAN_FCC 0x0 ++#define EEPROM_CHANNEL_PLAN_IC 0x1 ++#define EEPROM_CHANNEL_PLAN_ETSI 0x2 ++#define EEPROM_CHANNEL_PLAN_SPAIN 0x3 ++#define EEPROM_CHANNEL_PLAN_FRANCE 0x4 ++#define EEPROM_CHANNEL_PLAN_MKK 0x5 ++#define EEPROM_CHANNEL_PLAN_MKK1 0x6 ++#define EEPROM_CHANNEL_PLAN_ISRAEL 0x7 ++#define EEPROM_CHANNEL_PLAN_TELEC 0x8 ++#define EEPROM_CHANNEL_PLAN_GLOBAL_DOMAIN 0x9 ++#define EEPROM_CHANNEL_PLAN_WORLD_WIDE_13 0xA ++#define EEPROM_CHANNEL_PLAN_BY_HW_MASK 0x80 ++ ++#define EEPROM_CID_DEFAULT 0x0 ++ ++#define EEPROM_CID_WHQL 0xFE // added by chiyoko for dtm, 20090108 ++ ++ ++#define EEPROM_CID_CCX 0x10 // CCX test. By Bruce, 2009-02-25. ++#endif ++ ++#endif ++ ++ ++/*=================================================================== ++===================================================================== ++Here the register defines are for 92C. When the define is as same with 92C, ++we will use the 92C's define for the consistency ++So the following defines for 92C is not entire!!!!!! ++===================================================================== ++=====================================================================*/ ++/* ++Based on Datasheet V33---090401 ++Register Summary ++Current IOREG MAP ++0x0000h ~ 0x00FFh System Configuration (256 Bytes) ++0x0100h ~ 0x01FFh MACTOP General Configuration (256 Bytes) ++0x0200h ~ 0x027Fh TXDMA Configuration (128 Bytes) ++0x0280h ~ 0x02FFh RXDMA Configuration (128 Bytes) ++0x0300h ~ 0x03FFh PCIE EMAC Reserved Region (256 Bytes) ++0x0400h ~ 0x04FFh Protocol Configuration (256 Bytes) ++0x0500h ~ 0x05FFh EDCA Configuration (256 Bytes) ++0x0600h ~ 0x07FFh WMAC Configuration (512 Bytes) ++0x2000h ~ 0x3FFFh 8051 FW Download Region (8196 Bytes) ++*/ ++ ++//---------------------------------------------------------------------------- ++// 8192C (RCR) Receive Configuration Register (Offset 0x608, 32 bits) ++//---------------------------------------------------------------------------- ++#define RCR_APPFCS BIT31 //WMAC append FCS after pauload ++#define RCR_APP_MIC BIT30 // ++#define RCR_APP_PHYSTS BIT28// ++#define RCR_APP_ICV BIT29 // ++#define RCR_APP_PHYST_RXFF BIT28 // ++#define RCR_APP_BA_SSN BIT27 //Accept BA SSN ++#define RCR_ENMBID BIT24 //Enable Multiple BssId. ++#define RCR_LSIGEN BIT23 ++#define RCR_MFBEN BIT22 ++#define RCR_HTC_LOC_CTRL BIT14 //MFC<--HTC=1 MFC-->HTC=0 ++#define RCR_AMF BIT13 //Accept management type frame ++#define RCR_ACF BIT12 //Accept control type frame ++#define RCR_ADF BIT11 //Accept data type frame ++#define RCR_AICV BIT9 //Accept ICV error packet ++#define RCR_ACRC32 BIT8 //Accept CRC32 error packet ++#define RCR_CBSSID_BCN BIT7 //Accept BSSID match packet (Rx beacon, probe rsp) ++#define RCR_CBSSID_DATA BIT6 //Accept BSSID match packet (Data) ++#define RCR_CBSSID RCR_CBSSID_DATA //Accept BSSID match packet ++#define RCR_APWRMGT BIT5 //Accept power management packet ++#define RCR_ADD3 BIT4 //Accept address 3 match packet ++#define RCR_AB BIT3 //Accept broadcast packet ++#define RCR_AM BIT2 //Accept multicast packet ++#define RCR_APM BIT1 //Accept physical match packet ++#define RCR_AAP BIT0 //Accept all unicast packet ++#define RCR_MXDMA_OFFSET 8 ++#define RCR_FIFO_OFFSET 13 ++ ++ ++ ++//============================================================================ ++// 8192c USB specific Regsiter Offset and Content definition, ++// 2009.08.18, added by vivi. for merge 92c and 92C into one driver ++//============================================================================ ++//#define APS_FSMCO 0x0004 same with 92Ce ++#define RSV_CTRL 0x001C ++#define RD_CTRL 0x0524 ++ ++//----------------------------------------------------- ++// ++// 0xFE00h ~ 0xFE55h USB Configuration ++// ++//----------------------------------------------------- ++#define REG_USB_INFO 0xFE17 ++#define REG_USB_SPECIAL_OPTION 0xFE55 ++#define REG_USB_DMA_AGG_TO 0xFE5B ++#define REG_USB_AGG_TO 0xFE5C ++#define REG_USB_AGG_TH 0xFE5D ++ ++#define REG_USB_VID 0xFE60 ++#define REG_USB_PID 0xFE62 ++#define REG_USB_OPTIONAL 0xFE64 ++#define REG_USB_CHIRP_K 0xFE65 ++#define REG_USB_PHY 0xFE66 ++#define REG_USB_MAC_ADDR 0xFE70 ++ ++#define REG_USB_HRPWM 0xFE58 ++#define REG_USB_HCPWM 0xFE57 ++ ++#define InvalidBBRFValue 0x12345678 ++ ++//============================================================================ ++// 8192C Regsiter Bit and Content definition ++//============================================================================ ++//----------------------------------------------------- ++// ++// 0x0000h ~ 0x00FFh System Configuration ++// ++//----------------------------------------------------- ++ ++//2 SPS0_CTRL ++#define SW18_FPWM BIT(3) ++ ++ ++//2 SYS_ISO_CTRL ++#define ISO_MD2PP BIT(0) ++#define ISO_UA2USB BIT(1) ++#define ISO_UD2CORE BIT(2) ++#define ISO_PA2PCIE BIT(3) ++#define ISO_PD2CORE BIT(4) ++#define ISO_IP2MAC BIT(5) ++#define ISO_DIOP BIT(6) ++#define ISO_DIOE BIT(7) ++#define ISO_EB2CORE BIT(8) ++#define ISO_DIOR BIT(9) ++ ++#define PWC_EV25V BIT(14) ++#define PWC_EV12V BIT(15) ++ ++ ++//2 SYS_FUNC_EN ++#define FEN_BBRSTB BIT(0) ++#define FEN_BB_GLB_RSTn BIT(1) ++#define FEN_USBA BIT(2) ++#define FEN_UPLL BIT(3) ++#define FEN_USBD BIT(4) ++#define FEN_DIO_PCIE BIT(5) ++#define FEN_PCIEA BIT(6) ++#define FEN_PPLL BIT(7) ++#define FEN_PCIED BIT(8) ++#define FEN_DIOE BIT(9) ++#define FEN_CPUEN BIT(10) ++#define FEN_DCORE BIT(11) ++#define FEN_ELDR BIT(12) ++#define FEN_DIO_RF BIT(13) ++#define FEN_HWPDN BIT(14) ++#define FEN_MREGEN BIT(15) ++ ++//2 APS_FSMCO ++#define PFM_LDALL BIT(0) ++#define PFM_ALDN BIT(1) ++#define PFM_LDKP BIT(2) ++#define PFM_WOWL BIT(3) ++#define EnPDN BIT(4) ++#define PDN_PL BIT(5) ++#define APFM_ONMAC BIT(8) ++#define APFM_OFF BIT(9) ++#define APFM_RSM BIT(10) ++#define AFSM_HSUS BIT(11) ++#define AFSM_PCIE BIT(12) ++#define APDM_MAC BIT(13) ++#define APDM_HOST BIT(14) ++#define APDM_HPDN BIT(15) ++#define RDY_MACON BIT(16) ++#define SUS_HOST BIT(17) ++#define ROP_ALD BIT(20) ++#define ROP_PWR BIT(21) ++#define ROP_SPS BIT(22) ++#define SOP_MRST BIT(25) ++#define SOP_FUSE BIT(26) ++#define SOP_ABG BIT(27) ++#define SOP_AMB BIT(28) ++#define SOP_RCK BIT(29) ++#define SOP_A8M BIT(30) ++#define XOP_BTCK BIT(31) ++ ++//2 SYS_CLKR ++#define ANAD16V_EN BIT(0) ++#define ANA8M BIT(1) ++#define MACSLP BIT(4) ++#define LOADER_CLK_EN BIT(5) ++#define _80M_SSC_DIS BIT(7) ++#define _80M_SSC_EN_HO BIT(8) ++#define PHY_SSC_RSTB BIT(9) ++#define SEC_CLK_EN BIT(10) ++#define MAC_CLK_EN BIT(11) ++#define SYS_CLK_EN BIT(12) ++#define RING_CLK_EN BIT(13) ++ ++ ++//2 9346CR ++ ++ ++#define EEDO BIT(0) ++#define EEDI BIT(1) ++#define EESK BIT(2) ++#define EECS BIT(3) ++//#define EERPROMSEL BIT(4) ++//#define EEPROM_EN BIT(5) ++#define BOOT_FROM_EEPROM BIT(4) ++#define EEPROM_EN BIT(5) ++#define EEM0 BIT(6) ++#define EEM1 BIT(7) ++ ++ ++//2 AFE_MISC ++#define AFE_BGEN BIT(0) ++#define AFE_MBEN BIT(1) ++#define MAC_ID_EN BIT(7) ++ ++ ++//2 SPS0_CTRL ++ ++ ++//2 SPS_OCP_CFG ++ ++ ++//2 RSV_CTRL ++#define WLOCK_ALL BIT(0) ++#define WLOCK_00 BIT(1) ++#define WLOCK_04 BIT(2) ++#define WLOCK_08 BIT(3) ++#define WLOCK_40 BIT(4) ++#define R_DIS_PRST_0 BIT(5) ++#define R_DIS_PRST_1 BIT(6) ++#define LOCK_ALL_EN BIT(7) ++ ++//2 RF_CTRL ++#define RF_EN BIT(0) ++#define RF_RSTB BIT(1) ++#define RF_SDMRSTB BIT(2) ++ ++ ++ ++//2 LDOA15_CTRL ++#define LDA15_EN BIT(0) ++#define LDA15_STBY BIT(1) ++#define LDA15_OBUF BIT(2) ++#define LDA15_REG_VOS BIT(3) ++#define _LDA15_VOADJ(x) (((x) & 0x7) << 4) ++ ++ ++ ++//2 LDOV12D_CTRL ++#define LDV12_EN BIT(0) ++#define LDV12_SDBY BIT(1) ++#define LPLDO_HSM BIT(2) ++#define LPLDO_LSM_DIS BIT(3) ++#define _LDV12_VADJ(x) (((x) & 0xF) << 4) ++ ++ ++//2 AFE_XTAL_CTRL ++#define XTAL_EN BIT(0) ++#define XTAL_BSEL BIT(1) ++#define _XTAL_BOSC(x) (((x) & 0x3) << 2) ++#define _XTAL_CADJ(x) (((x) & 0xF) << 4) ++#define XTAL_GATE_USB BIT(8) ++#define _XTAL_USB_DRV(x) (((x) & 0x3) << 9) ++#define XTAL_GATE_AFE BIT(11) ++#define _XTAL_AFE_DRV(x) (((x) & 0x3) << 12) ++#define XTAL_RF_GATE BIT(14) ++#define _XTAL_RF_DRV(x) (((x) & 0x3) << 15) ++#define XTAL_GATE_DIG BIT(17) ++#define _XTAL_DIG_DRV(x) (((x) & 0x3) << 18) ++#define XTAL_BT_GATE BIT(20) ++#define _XTAL_BT_DRV(x) (((x) & 0x3) << 21) ++#define _XTAL_GPIO(x) (((x) & 0x7) << 23) ++ ++ ++#define CKDLY_AFE BIT(26) ++#define CKDLY_USB BIT(27) ++#define CKDLY_DIG BIT(28) ++#define CKDLY_BT BIT(29) ++ ++ ++//2 AFE_PLL_CTRL ++#define APLL_EN BIT(0) ++#define APLL_320_EN BIT(1) ++#define APLL_FREF_SEL BIT(2) ++#define APLL_EDGE_SEL BIT(3) ++#define APLL_WDOGB BIT(4) ++#define APLL_LPFEN BIT(5) ++ ++#define APLL_REF_CLK_13MHZ 0x1 ++#define APLL_REF_CLK_19_2MHZ 0x2 ++#define APLL_REF_CLK_20MHZ 0x3 ++#define APLL_REF_CLK_25MHZ 0x4 ++#define APLL_REF_CLK_26MHZ 0x5 ++#define APLL_REF_CLK_38_4MHZ 0x6 ++#define APLL_REF_CLK_40MHZ 0x7 ++ ++#define APLL_320EN BIT(14) ++#define APLL_80EN BIT(15) ++#define APLL_1MEN BIT(24) ++ ++ ++//2 EFUSE_CTRL ++#define ALD_EN BIT(18) ++#define EF_PD BIT(19) ++#define EF_FLAG BIT(31) ++ ++//2 EFUSE_TEST (For RTL8723 partially) ++#define EF_TRPT BIT(7) ++#define EF_CELL_SEL (BIT(8)|BIT(9)) // 00: Wifi Efuse, 01: BT Efuse0, 10: BT Efuse1, 11: BT Efuse2 ++#define LDOE25_EN BIT(31) ++#define EFUSE_SEL(x) (((x) & 0x3) << 8) ++#define EFUSE_SEL_MASK 0x300 ++#define EFUSE_WIFI_SEL_0 0x0 ++#define EFUSE_BT_SEL_0 0x1 ++#define EFUSE_BT_SEL_1 0x2 ++#define EFUSE_BT_SEL_2 0x3 ++ ++#define EFUSE_ACCESS_ON 0x69 // For RTL8723 only. ++#define EFUSE_ACCESS_OFF 0x00 // For RTL8723 only. ++ ++//2 PWR_DATA ++ ++//2 CAL_TIMER ++ ++//2 ACLK_MON ++#define RSM_EN BIT(0) ++#define Timer_EN BIT(4) ++ ++ ++//2 GPIO_MUXCFG ++#define TRSW0EN BIT(2) ++#define TRSW1EN BIT(3) ++#define EROM_EN BIT(4) ++#define EnBT BIT(5) ++#define EnUart BIT(8) ++#define Uart_910 BIT(9) ++#define EnPMAC BIT(10) ++#define SIC_SWRST BIT(11) ++#define EnSIC BIT(12) ++#define SIC_23 BIT(13) ++#define EnHDP BIT(14) ++#define SIC_LBK BIT(15) ++ ++//2 GPIO_PIN_CTRL ++ ++// GPIO BIT ++#define HAL_8192C_HW_GPIO_WPS_BIT BIT(2) ++ ++//2 GPIO_INTM ++ ++//2 LEDCFG ++#define LED0PL BIT(4) ++#define LED0DIS BIT(7) ++#define LED1DIS BIT(15) ++#define LED1PL BIT(12) ++ ++#define SECCAM_CLR BIT(30) ++ ++ ++//2 FSIMR ++ ++//2 FSISR ++ ++ ++//2 8051FWDL ++//2 MCUFWDL ++#define MCUFWDL_EN BIT(0) ++#define MCUFWDL_RDY BIT(1) ++#define FWDL_ChkSum_rpt BIT(2) ++#define MACINI_RDY BIT(3) ++#define BBINI_RDY BIT(4) ++#define RFINI_RDY BIT(5) ++#define WINTINI_RDY BIT(6) ++#define CPRST BIT(23) ++ ++//2REG_HPON_FSM ++#define BOND92CE_1T2R_CFG BIT(22) ++ ++ ++//2 REG_SYS_CFG ++#define XCLK_VLD BIT(0) ++#define ACLK_VLD BIT(1) ++#define UCLK_VLD BIT(2) ++#define PCLK_VLD BIT(3) ++#define PCIRSTB BIT(4) ++#define V15_VLD BIT(5) ++#define TRP_B15V_EN BIT(7) ++#define SIC_IDLE BIT(8) ++#define BD_MAC2 BIT(9) ++#define BD_MAC1 BIT(10) ++#define IC_MACPHY_MODE BIT(11) ++#define CHIP_VER (BIT(12)|BIT(13)|BIT(14)|BIT(15)) ++#define BT_FUNC BIT(16) ++#define VENDOR_ID BIT(19) ++#define PAD_HWPD_IDN BIT(22) ++#define TRP_VAUX_EN BIT(23) ++#define TRP_BT_EN BIT(24) ++#define BD_PKG_SEL BIT(25) ++#define BD_HCI_SEL BIT(26) ++#define TYPE_ID BIT(27) ++ ++#define CHIP_VER_RTL_MASK 0xF000 //Bit 12 ~ 15 ++#define CHIP_VER_RTL_SHIFT 12 ++ ++//2REG_GPIO_OUTSTS (For RTL8723 only) ++#define EFS_HCI_SEL (BIT(0)|BIT(1)) ++#define PAD_HCI_SEL (BIT(2)|BIT(3)) ++#define HCI_SEL (BIT(4)|BIT(5)) ++#define PKG_SEL_HCI BIT(6) ++#define FEN_GPS BIT(7) ++#define FEN_BT BIT(8) ++#define FEN_WL BIT(9) ++#define FEN_PCI BIT(10) ++#define FEN_USB BIT(11) ++#define BTRF_HWPDN_N BIT(12) ++#define WLRF_HWPDN_N BIT(13) ++#define PDN_BT_N BIT(14) ++#define PDN_GPS_N BIT(15) ++#define BT_CTL_HWPDN BIT(16) ++#define GPS_CTL_HWPDN BIT(17) ++#define PPHY_SUSB BIT(20) ++#define UPHY_SUSB BIT(21) ++#define PCI_SUSEN BIT(22) ++#define USB_SUSEN BIT(23) ++#define RF_RL_ID (BIT(31)|BIT(30)|BIT(29)|BIT(28)) ++ ++//----------------------------------------------------- ++// ++// 0x0100h ~ 0x01FFh MACTOP General Configuration ++// ++//----------------------------------------------------- ++ ++ ++//2 Function Enable Registers ++//2 CR ++ ++#define REG_LBMODE (REG_CR + 3) ++ ++ ++#define HCI_TXDMA_EN BIT(0) ++#define HCI_RXDMA_EN BIT(1) ++#define TXDMA_EN BIT(2) ++#define RXDMA_EN BIT(3) ++#define PROTOCOL_EN BIT(4) ++#define SCHEDULE_EN BIT(5) ++#define MACTXEN BIT(6) ++#define MACRXEN BIT(7) ++#define ENSWBCN BIT(8) ++#define ENSEC BIT(9) ++ ++// Network type ++#define _NETTYPE(x) (((x) & 0x3) << 16) ++#define MASK_NETTYPE 0x30000 ++#define NT_NO_LINK 0x0 ++#define NT_LINK_AD_HOC 0x1 ++#define NT_LINK_AP 0x2 ++#define NT_AS_AP 0x3 ++ ++#define _LBMODE(x) (((x) & 0xF) << 24) ++#define MASK_LBMODE 0xF000000 ++#define LOOPBACK_NORMAL 0x0 ++#define LOOPBACK_IMMEDIATELY 0xB ++#define LOOPBACK_MAC_DELAY 0x3 ++#define LOOPBACK_PHY 0x1 ++#define LOOPBACK_DMA 0x7 ++ ++ ++//2 PBP - Page Size Register ++#define GET_RX_PAGE_SIZE(value) ((value) & 0xF) ++#define GET_TX_PAGE_SIZE(value) (((value) & 0xF0) >> 4) ++#define _PSRX_MASK 0xF ++#define _PSTX_MASK 0xF0 ++#define _PSRX(x) (x) ++#define _PSTX(x) ((x) << 4) ++ ++#define PBP_64 0x0 ++#define PBP_128 0x1 ++#define PBP_256 0x2 ++#define PBP_512 0x3 ++#define PBP_1024 0x4 ++ ++ ++//2 TX/RXDMA ++#define RXDMA_ARBBW_EN BIT(0) ++#define RXSHFT_EN BIT(1) ++#define RXDMA_AGG_EN BIT(2) ++#define QS_VO_QUEUE BIT(8) ++#define QS_VI_QUEUE BIT(9) ++#define QS_BE_QUEUE BIT(10) ++#define QS_BK_QUEUE BIT(11) ++#define QS_MANAGER_QUEUE BIT(12) ++#define QS_HIGH_QUEUE BIT(13) ++ ++#define HQSEL_VOQ BIT(0) ++#define HQSEL_VIQ BIT(1) ++#define HQSEL_BEQ BIT(2) ++#define HQSEL_BKQ BIT(3) ++#define HQSEL_MGTQ BIT(4) ++#define HQSEL_HIQ BIT(5) ++ ++// For normal driver, 0x10C ++#define _TXDMA_HIQ_MAP(x) (((x)&0x3) << 14) ++#define _TXDMA_MGQ_MAP(x) (((x)&0x3) << 12) ++#define _TXDMA_BKQ_MAP(x) (((x)&0x3) << 10) ++#define _TXDMA_BEQ_MAP(x) (((x)&0x3) << 8 ) ++#define _TXDMA_VIQ_MAP(x) (((x)&0x3) << 6 ) ++#define _TXDMA_VOQ_MAP(x) (((x)&0x3) << 4 ) ++ ++#define QUEUE_LOW 1 ++#define QUEUE_NORMAL 2 ++#define QUEUE_HIGH 3 ++ ++ ++ ++//2 TRXFF_BNDY ++ ++ ++//2 LLT_INIT ++#define _LLT_NO_ACTIVE 0x0 ++#define _LLT_WRITE_ACCESS 0x1 ++#define _LLT_READ_ACCESS 0x2 ++ ++#define _LLT_INIT_DATA(x) ((x) & 0xFF) ++#define _LLT_INIT_ADDR(x) (((x) & 0xFF) << 8) ++#define _LLT_OP(x) (((x) & 0x3) << 30) ++#define _LLT_OP_VALUE(x) (((x) >> 30) & 0x3) ++ ++ ++//2 BB_ACCESS_CTRL ++#define BB_WRITE_READ_MASK (BIT(31) | BIT(30)) ++#define BB_WRITE_EN BIT(30) ++#define BB_READ_EN BIT(31) ++//#define BB_ADDR_MASK 0xFFF ++//#define _BB_ADDR(x) ((x) & BB_ADDR_MASK) ++ ++//----------------------------------------------------- ++// ++// 0x0200h ~ 0x027Fh TXDMA Configuration ++// ++//----------------------------------------------------- ++//2 RQPN ++#define _HPQ(x) ((x) & 0xFF) ++#define _LPQ(x) (((x) & 0xFF) << 8) ++#define _PUBQ(x) (((x) & 0xFF) << 16) ++#define _NPQ(x) ((x) & 0xFF) // NOTE: in RQPN_NPQ register ++ ++ ++#define HPQ_PUBLIC_DIS BIT(24) ++#define LPQ_PUBLIC_DIS BIT(25) ++#define LD_RQPN BIT(31) ++ ++ ++//2 TDECTRL ++#define BCN_VALID BIT(16) ++#define BCN_HEAD(x) (((x) & 0xFF) << 8) ++#define BCN_HEAD_MASK 0xFF00 ++ ++//2 TDECTL ++#define BLK_DESC_NUM_SHIFT 4 ++#define BLK_DESC_NUM_MASK 0xF ++ ++ ++//2 TXDMA_OFFSET_CHK ++#define DROP_DATA_EN BIT(9) ++ ++//----------------------------------------------------- ++// ++// 0x0400h ~ 0x047Fh Protocol Configuration ++// ++//----------------------------------------------------- ++//2 FWHW_TXQ_CTRL ++#define EN_AMPDU_RTY_NEW BIT(7) ++ ++//2 INIRTSMCS_SEL ++#define _INIRTSMCS_SEL(x) ((x) & 0x3F) ++ ++ ++//2 SPEC SIFS ++#define _SPEC_SIFS_CCK(x) ((x) & 0xFF) ++#define _SPEC_SIFS_OFDM(x) (((x) & 0xFF) << 8) ++ ++ ++//2 RRSR ++ ++#define RATE_REG_BITMAP_ALL 0xFFFFF ++ ++#define _RRSC_BITMAP(x) ((x) & 0xFFFFF) ++ ++#define _RRSR_RSC(x) (((x) & 0x3) << 21) ++#define RRSR_RSC_RESERVED 0x0 ++#define RRSR_RSC_UPPER_SUBCHANNEL 0x1 ++#define RRSR_RSC_LOWER_SUBCHANNEL 0x2 ++#define RRSR_RSC_DUPLICATE_MODE 0x3 ++ ++ ++//2 ARFR ++#define USE_SHORT_G1 BIT(20) ++ ++//2 AGGLEN_LMT_L ++#define _AGGLMT_MCS0(x) ((x) & 0xF) ++#define _AGGLMT_MCS1(x) (((x) & 0xF) << 4) ++#define _AGGLMT_MCS2(x) (((x) & 0xF) << 8) ++#define _AGGLMT_MCS3(x) (((x) & 0xF) << 12) ++#define _AGGLMT_MCS4(x) (((x) & 0xF) << 16) ++#define _AGGLMT_MCS5(x) (((x) & 0xF) << 20) ++#define _AGGLMT_MCS6(x) (((x) & 0xF) << 24) ++#define _AGGLMT_MCS7(x) (((x) & 0xF) << 28) ++ ++ ++//2 RL ++#define RETRY_LIMIT_SHORT_SHIFT 8 ++#define RETRY_LIMIT_LONG_SHIFT 0 ++ ++ ++//2 DARFRC ++#define _DARF_RC1(x) ((x) & 0x1F) ++#define _DARF_RC2(x) (((x) & 0x1F) << 8) ++#define _DARF_RC3(x) (((x) & 0x1F) << 16) ++#define _DARF_RC4(x) (((x) & 0x1F) << 24) ++// NOTE: shift starting from address (DARFRC + 4) ++#define _DARF_RC5(x) ((x) & 0x1F) ++#define _DARF_RC6(x) (((x) & 0x1F) << 8) ++#define _DARF_RC7(x) (((x) & 0x1F) << 16) ++#define _DARF_RC8(x) (((x) & 0x1F) << 24) ++ ++ ++//2 RARFRC ++#define _RARF_RC1(x) ((x) & 0x1F) ++#define _RARF_RC2(x) (((x) & 0x1F) << 8) ++#define _RARF_RC3(x) (((x) & 0x1F) << 16) ++#define _RARF_RC4(x) (((x) & 0x1F) << 24) ++// NOTE: shift starting from address (RARFRC + 4) ++#define _RARF_RC5(x) ((x) & 0x1F) ++#define _RARF_RC6(x) (((x) & 0x1F) << 8) ++#define _RARF_RC7(x) (((x) & 0x1F) << 16) ++#define _RARF_RC8(x) (((x) & 0x1F) << 24) ++ ++ ++ ++ ++//----------------------------------------------------- ++// ++// 0x0500h ~ 0x05FFh EDCA Configuration ++// ++//----------------------------------------------------- ++ ++ ++ ++//2 EDCA setting ++#define AC_PARAM_TXOP_LIMIT_OFFSET 16 ++#define AC_PARAM_ECW_MAX_OFFSET 12 ++#define AC_PARAM_ECW_MIN_OFFSET 8 ++#define AC_PARAM_AIFS_OFFSET 0 ++ ++ ++//2 EDCA_VO_PARAM ++#define _AIFS(x) (x) ++#define _ECW_MAX_MIN(x) ((x) << 8) ++#define _TXOP_LIMIT(x) ((x) << 16) ++ ++ ++#define _BCNIFS(x) ((x) & 0xFF) ++#define _BCNECW(x) (((x) & 0xF))<< 8) ++ ++ ++#define _LRL(x) ((x) & 0x3F) ++#define _SRL(x) (((x) & 0x3F) << 8) ++ ++ ++//2 SIFS_CCK ++#define _SIFS_CCK_CTX(x) ((x) & 0xFF) ++#define _SIFS_CCK_TRX(x) (((x) & 0xFF) << 8); ++ ++ ++//2 SIFS_OFDM ++#define _SIFS_OFDM_CTX(x) ((x) & 0xFF) ++#define _SIFS_OFDM_TRX(x) (((x) & 0xFF) << 8); ++ ++ ++//2 TBTT PROHIBIT ++#define _TBTT_PROHIBIT_HOLD(x) (((x) & 0xFF) << 8) ++ ++ ++//2 REG_RD_CTRL ++#define DIS_EDCA_CNT_DWN BIT(11) ++ ++ ++//2 BCN_CTRL ++#define EN_MBSSID BIT(1) ++#define EN_TXBCN_RPT BIT(2) ++#define EN_BCN_FUNCTION BIT(3) ++ ++// The same function but different bit field. ++#define DIS_TSF_UDT0_NORMAL_CHIP BIT(4) ++#define DIS_TSF_UDT0_TEST_CHIP BIT(5) ++ ++//2 ACMHWCTRL ++#define AcmHw_HwEn BIT(0) ++#define AcmHw_BeqEn BIT(1) ++#define AcmHw_ViqEn BIT(2) ++#define AcmHw_VoqEn BIT(3) ++#define AcmHw_BeqStatus BIT(4) ++#define AcmHw_ViqStatus BIT(5) ++#define AcmHw_VoqStatus BIT(6) ++ ++ ++ ++//----------------------------------------------------- ++// ++// 0x0600h ~ 0x07FFh WMAC Configuration ++// ++//----------------------------------------------------- ++ ++//2 APSD_CTRL ++#define APSDOFF BIT(6) ++#define APSDOFF_STATUS BIT(7) ++ ++ ++//2 BWOPMODE ++#define BW_20MHZ BIT(2) ++//#define BW_OPMODE_20MHZ BIT(2) // For compability ++ ++ ++#define RATE_BITMAP_ALL 0xFFFFF ++ ++// Only use CCK 1M rate for ACK ++#define RATE_RRSR_CCK_ONLY_1M 0xFFFF1 ++ ++//2 TCR ++#define TSFRST BIT(0) ++#define DIS_GCLK BIT(1) ++#define PAD_SEL BIT(2) ++#define PWR_ST BIT(6) ++#define PWRBIT_OW_EN BIT(7) ++#define ACRC BIT(8) ++#define CFENDFORM BIT(9) ++#define ICV BIT(10) ++ ++ ++ ++//2 RCR ++#define AAP BIT(0) ++#define APM BIT(1) ++#define AM BIT(2) ++#define AB BIT(3) ++#define ADD3 BIT(4) ++#define APWRMGT BIT(5) ++#define CBSSID BIT(6) ++#define CBSSID_BCN BIT(7) ++#define ACRC32 BIT(8) ++#define AICV BIT(9) ++#define ADF BIT(11) ++#define ACF BIT(12) ++#define AMF BIT(13) ++#define HTC_LOC_CTRL BIT(14) ++#define UC_DATA_EN BIT(16) ++#define BM_DATA_EN BIT(17) ++#define MFBEN BIT(22) ++#define LSIGEN BIT(23) ++#define EnMBID BIT(24) ++#define APP_BASSN BIT(27) ++#define APP_PHYSTS BIT(28) ++#define APP_ICV BIT(29) ++#define APP_MIC BIT(30) ++#define APP_FCS BIT(31) ++ ++//2 RX_PKT_LIMIT ++ ++//2 RX_DLK_TIME ++ ++//2 MBIDCAMCFG ++ ++ ++ ++//2 AMPDU_MIN_SPACE ++#define _MIN_SPACE(x) ((x) & 0x7) ++#define _SHORT_GI_PADDING(x) (((x) & 0x1F) << 3) ++ ++ ++//2 RXERR_RPT ++#define RXERR_TYPE_OFDM_PPDU 0 ++#define RXERR_TYPE_OFDM_FALSE_ALARM 1 ++#define RXERR_TYPE_OFDM_MPDU_OK 2 ++#define RXERR_TYPE_OFDM_MPDU_FAIL 3 ++#define RXERR_TYPE_CCK_PPDU 4 ++#define RXERR_TYPE_CCK_FALSE_ALARM 5 ++#define RXERR_TYPE_CCK_MPDU_OK 6 ++#define RXERR_TYPE_CCK_MPDU_FAIL 7 ++#define RXERR_TYPE_HT_PPDU 8 ++#define RXERR_TYPE_HT_FALSE_ALARM 9 ++#define RXERR_TYPE_HT_MPDU_TOTAL 10 ++#define RXERR_TYPE_HT_MPDU_OK 11 ++#define RXERR_TYPE_HT_MPDU_FAIL 12 ++#define RXERR_TYPE_RX_FULL_DROP 15 ++ ++#define RXERR_COUNTER_MASK 0xFFFFF ++#define RXERR_RPT_RST BIT(27) ++#define _RXERR_RPT_SEL(type) ((type) << 28) ++ ++ ++//2 SECCFG ++#define SCR_TxUseDK BIT(0) //Force Tx Use Default Key ++#define SCR_RxUseDK BIT(1) //Force Rx Use Default Key ++#define SCR_TxEncEnable BIT(2) //Enable Tx Encryption ++#define SCR_RxDecEnable BIT(3) //Enable Rx Decryption ++#define SCR_SKByA2 BIT(4) //Search kEY BY A2 ++#define SCR_NoSKMC BIT(5) //No Key Search Multicast ++ ++ ++ ++//----------------------------------------------------- ++// ++// 0xFE00h ~ 0xFE55h USB Configuration ++// ++//----------------------------------------------------- ++ ++//2 USB Information (0xFE17) ++#define USB_IS_HIGH_SPEED 0 ++#define USB_IS_FULL_SPEED 1 ++#define USB_SPEED_MASK BIT(5) ++ ++#define USB_NORMAL_SIE_EP_MASK 0xF ++#define USB_NORMAL_SIE_EP_SHIFT 4 ++ ++#define USB_TEST_EP_MASK 0x30 ++#define USB_TEST_EP_SHIFT 4 ++ ++//2 Special Option ++#define USB_AGG_EN BIT(3) ++ ++ ++//2REG_C2HEVT_CLEAR ++#define C2H_EVT_HOST_CLOSE 0x00 // Set by driver and notify FW that the driver has read the C2H command message ++#define C2H_EVT_FW_CLOSE 0xFF // Set by FW indicating that FW had set the C2H command message and it's not yet read by driver. ++ ++ ++//2REG_MULTI_FUNC_CTRL(For RTL8723 Only) ++#define WL_HWPDN_EN BIT0 // Enable GPIO[9] as WiFi HW PDn source ++#define WL_HWPDN_SL BIT1 // WiFi HW PDn polarity control ++#define WL_FUNC_EN BIT2 // WiFi function enable ++#define WL_HWROF_EN BIT3 // Enable GPIO[9] as WiFi RF HW PDn source ++#define BT_HWPDN_EN BIT16 // Enable GPIO[11] as BT HW PDn source ++#define BT_HWPDN_SL BIT17 // BT HW PDn polarity control ++#define BT_FUNC_EN BIT18 // BT function enable ++#define BT_HWROF_EN BIT19 // Enable GPIO[11] as BT/GPS RF HW PDn source ++#define GPS_HWPDN_EN BIT20 // Enable GPIO[10] as GPS HW PDn source ++#define GPS_HWPDN_SL BIT21 // GPS HW PDn polarity control ++#define GPS_FUNC_EN BIT22 // GPS function enable ++ ++//3 REG_LIFECTRL_CTRL ++#define HAL92C_EN_PKT_LIFE_TIME_BK BIT3 ++#define HAL92C_EN_PKT_LIFE_TIME_BE BIT2 ++#define HAL92C_EN_PKT_LIFE_TIME_VI BIT1 ++#define HAL92C_EN_PKT_LIFE_TIME_VO BIT0 ++ ++#define HAL92C_MSDU_LIFE_TIME_UNIT 128 // in us, said by Tim. ++ ++//======================================================== ++// General definitions ++//======================================================== ++ ++#define MAC_ADDR_LEN 6 ++#define LAST_ENTRY_OF_TX_PKT_BUFFER 255 ++ ++#define POLLING_LLT_THRESHOLD 20 ++#define POLLING_READY_TIMEOUT_COUNT 1000 ++ ++// Min Spacing related settings. ++#define MAX_MSS_DENSITY_2T 0x13 ++#define MAX_MSS_DENSITY_1T 0x0A ++ ++//---------------------------------------------------------------------------- ++// 8192C GPIO MUX Configuration Register (offset 0x40, 4 byte) ++//---------------------------------------------------------------------------- ++#define GPIOSEL_GPIO 0 ++#define GPIOSEL_ENBT BIT5 ++ ++//---------------------------------------------------------------------------- ++// 8192C GPIO PIN Control Register (offset 0x44, 4 byte) ++//---------------------------------------------------------------------------- ++#define GPIO_IN REG_GPIO_PIN_CTRL // GPIO pins input value ++#define GPIO_OUT (REG_GPIO_PIN_CTRL+1) // GPIO pins output value ++#define GPIO_IO_SEL (REG_GPIO_PIN_CTRL+2) // GPIO pins output enable when a bit is set to "1"; otherwise, input is configured. ++#define GPIO_MOD (REG_GPIO_PIN_CTRL+3) ++ ++ ++ ++#include "basic_types.h" ++ ++#endif ++ +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/include/rtl8192c_sreset.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/include/rtl8192c_sreset.h 2013-07-26 19:36:06.000000000 +0000 +@@ -0,0 +1,54 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ++******************************************************************************/ ++#ifndef _RTL8192C_SRESET_C_ ++#define _RTL8192C_SRESET_C_ ++ ++#include ++#include ++#include ++ ++#ifdef DBG_CONFIG_ERROR_DETECT ++#define WIFI_STATUS_SUCCESS 0 ++#define USB_VEN_REQ_CMD_FAIL BIT0 ++#define USB_READ_PORT_FAIL BIT1 ++#define USB_WRITE_PORT_FAIL BIT2 ++#define WIFI_MAC_TXDMA_ERROR BIT3 ++#define WIFI_TX_HANG BIT4 ++#define WIFI_RX_HANG BIT5 ++#define WIFI_IF_NOT_EXIST BIT6 ++ ++struct sreset_priv { ++ _mutex silentreset_mutex; ++ u8 silent_reset_inprogress; ++ u8 Wifi_Error_Status; ++ unsigned long last_tx_time; ++ unsigned long last_tx_complete_time; ++}; ++ ++ ++extern void rtl8192c_sreset_init_value(_adapter *padapter); ++extern void rtl8192c_sreset_reset_value(_adapter *padapter); ++extern void rtl8192c_silentreset_for_specific_platform(_adapter *padapter); ++extern void rtl8192c_sreset_xmit_status_check(_adapter *padapter); ++extern void rtl8192c_sreset_linked_status_check(_adapter *padapter); ++extern u8 rtl8192c_sreset_get_wifi_status(_adapter *padapter); ++#endif ++#endif +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/include/rtl8192c_xmit.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/include/rtl8192c_xmit.h 2013-07-26 19:36:06.000000000 +0000 +@@ -0,0 +1,91 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ++******************************************************************************/ ++#ifndef _RTL8192C_XMIT_H_ ++#define _RTL8192C_XMIT_H_ ++ ++#define VO_QUEUE_INX 0 ++#define VI_QUEUE_INX 1 ++#define BE_QUEUE_INX 2 ++#define BK_QUEUE_INX 3 ++#define BCN_QUEUE_INX 4 ++#define MGT_QUEUE_INX 5 ++#define HIGH_QUEUE_INX 6 ++#define TXCMD_QUEUE_INX 7 ++ ++#define HW_QUEUE_ENTRY 8 ++ ++// ++// Queue Select Value in TxDesc ++// ++#define QSLT_BK 0x2//0x01 ++#define QSLT_BE 0x0 ++#define QSLT_VI 0x5//0x4 ++#define QSLT_VO 0x7//0x6 ++#define QSLT_BEACON 0x10 ++#define QSLT_HIGH 0x11 ++#define QSLT_MGNT 0x12 ++#define QSLT_CMD 0x13 ++ ++#ifdef CONFIG_USB_HCI ++ ++#ifdef CONFIG_USB_TX_AGGREGATION ++#define MAX_TX_AGG_PACKET_NUMBER 0xFF ++#endif ++ ++s32 rtl8192cu_init_xmit_priv(_adapter * padapter); ++ ++void rtl8192cu_free_xmit_priv(_adapter * padapter); ++ ++void rtl8192cu_cal_txdesc_chksum(struct tx_desc *ptxdesc); ++ ++s32 rtl8192cu_xmitframe_complete(_adapter *padapter, struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf); ++ ++void rtl8192cu_mgnt_xmit(_adapter *padapter, struct xmit_frame *pmgntframe); ++ ++s32 rtl8192cu_hal_xmit(_adapter *padapter, struct xmit_frame *pxmitframe); ++ ++#ifdef CONFIG_HOSTAPD_MLME ++s32 rtl8192cu_hostap_mgnt_xmit_entry(_adapter *padapter, _pkt *pkt); ++#endif ++ ++#endif ++ ++#ifdef CONFIG_PCI_HCI ++s32 rtl8192ce_init_xmit_priv(_adapter * padapter); ++void rtl8192ce_free_xmit_priv(_adapter * padapter); ++ ++s32 rtl8192ce_enqueue_xmitbuf(struct rtw_tx_ring *ring, struct xmit_buf *pxmitbuf); ++struct xmit_buf *rtl8192ce_dequeue_xmitbuf(struct rtw_tx_ring *ring); ++ ++void rtl8192ce_xmitframe_resume(_adapter *padapter); ++ ++void rtl8192ce_mgnt_xmit(_adapter *padapter, struct xmit_frame *pmgntframe); ++ ++s32 rtl8192ce_hal_xmit(_adapter *padapter, struct xmit_frame *pxmitframe); ++ ++#ifdef CONFIG_HOSTAPD_MLME ++s32 rtl8192ce_hostap_mgnt_xmit_entry(_adapter *padapter, _pkt *pkt); ++#endif ++ ++#endif ++ ++#endif ++ +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/include/rtl8192d_cmd.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/include/rtl8192d_cmd.h 2013-07-26 19:36:06.000000000 +0000 +@@ -0,0 +1,133 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ++******************************************************************************/ ++#ifndef __RTL8192D_CMD_H_ ++#define __RTL8192D_CMD_H_ ++ ++ ++//-------------------------------------------- ++//3 Host Message Box ++//-------------------------------------------- ++ ++// User Define Message [31:8] ++ ++//_SETPWRMODE_PARM ++#define SET_H2CCMD_PWRMODE_PARM_MODE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value) ++#define SET_H2CCMD_PWRMODE_PARM_SMART_PS(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value) ++#define SET_H2CCMD_PWRMODE_PARM_BCN_PASS_TIME(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value) ++ ++//JOINBSSRPT_PARM ++#define SET_H2CCMD_JOINBSSRPT_PARM_OPMODE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value) ++ ++//_RSVDPAGE_LOC ++#define SET_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 8, __Value) ++#define SET_H2CCMD_RSVDPAGE_LOC_PSPOLL(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+1, 0, 8, __Value) ++#define SET_H2CCMD_RSVDPAGE_LOC_NULL_DATA(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE((__pH2CCmd)+2, 0, 8, __Value) ++ ++//P2P_PS_OFFLOAD ++ ++struct P2P_PS_Offload_t { ++ unsigned char Offload_En:1; ++ unsigned char role:1; // 1: Owner, 0: Client ++ unsigned char CTWindow_En:1; ++ unsigned char NoA0_En:1; ++ unsigned char NoA1_En:1; ++ unsigned char AllStaSleep:1; // Only valid in Owner ++ unsigned char discovery:1; ++ unsigned char rsvd:1; ++}; ++ ++#define SET_H2CCMD_P2P_PS_OFFLOAD_EN(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 0, 1, __Value) ++#define SET_H2CCMD_P2P_PS_OFFLOAD_ROLE(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 1, 1, __Value) ++#define SET_H2CCMD_P2P_PS_OFFLOAD_CTW(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 2, 1, __Value) ++#define SET_H2CCMD_P2P_PS_OFFLOAD_NOA0(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 3, 1, __Value) ++#define SET_H2CCMD_P2P_PS_OFFLOAD_NOA1(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 4, 1, __Value) ++#define SET_H2CCMD_P2P_PS_OFFLOAD_ALLSTASLEEP(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 5, 1, __Value) ++#define SET_H2CCMD_P2P_PS_OFFLOAD_DISCOVERY(__pH2CCmd, __Value) SET_BITS_TO_LE_1BYTE(__pH2CCmd, 6, 1, __Value) ++ ++// Description: Determine the types of H2C commands that are the same in driver and Fw. ++// Fisrt constructed by tynli. 2009.10.09. ++typedef enum _RTL8192D_H2C_CMD ++{ ++ H2C_AP_OFFLOAD = 0, /*0*/ ++ H2C_SETPWRMODE = 1, /*1*/ ++ H2C_JOINBSSRPT = 2, /*2*/ ++ H2C_RSVDPAGE = 3, ++ H2C_RSSI_REPORT = 5, ++ H2C_RA_MASK = 6, ++ H2C_P2P_PS_OFFLOAD = 8, ++ H2C_MAC_MODE_SEL = 9, ++ H2C_PWRM=15, ++ H2C_WO_WLAN_CMD = 20, // Wake on Wlan. ++ H2C_P2P_PS_CTW_CMD = 24, ++ H2C_PathDiv = 26, //PathDiv--NeilChen--2011.07.15 ++ KEEP_ALIVE_CONTROL_CMD=31, //keep alive for wake on wlan ++ DISCONNECT_DECISION_CTRL_CMD=32, ++ REMOTE_WAKE_CTRL_CMD=34, ++ H2C_CMD_MAX ++}RTL8192D_H2C_CMD; ++ ++struct cmd_msg_parm { ++ u8 eid; //element id ++ u8 sz; // sz ++ u8 buf[6]; ++}; ++ ++ ++void FillH2CCmd92D(_adapter* padapter, u8 ElementID, u32 CmdLen, u8* pCmdBuffer); ++ ++// host message to firmware cmd ++void rtl8192d_set_FwPwrMode_cmd(_adapter*padapter, u8 Mode); ++void rtl8192d_set_FwJoinBssReport_cmd(_adapter* padapter, u8 mstatus); ++u8 rtl8192d_set_rssi_cmd(_adapter*padapter, u8 *param); ++u8 rtl8192d_set_raid_cmd(_adapter*padapter, u32 mask, u8 arg); ++void rtl8192d_Add_RateATid(PADAPTER pAdapter, u32 bitmap, u8 arg, u8 mac_id); ++#ifdef CONFIG_P2P ++void rtl8192d_set_p2p_ps_offload_cmd(_adapter* padapter, u8 p2p_ps_state); ++#endif //CONFIG_P2P ++ ++#endif ++ ++#ifdef CONFIG_WOWLAN ++typedef struct _SETWOWLAN_PARM{ ++ u8 mode; ++ u8 gpio_index; ++ u8 gpio_duration; ++ u8 second_mode; ++ u8 reserve; ++}SETWOWLAN_PARM, *PSETWOWLAN_PARM; ++ ++#define FW_WOWLAN_FUN_EN BIT(0) ++#define FW_WOWLAN_PATTERN_MATCH BIT(1) ++#define FW_WOWLAN_MAGIC_PKT BIT(2) ++#define FW_WOWLAN_UNICAST BIT(3) ++#define FW_WOWLAN_ALL_PKT_DROP BIT(4) ++#define FW_WOWLAN_GPIO_ACTIVE BIT(5) ++#define FW_WOWLAN_REKEY_WAKEUP BIT(6) ++#define FW_WOWLAN_DEAUTH_WAKEUP BIT(7) ++ ++#define FW_WOWLAN_GPIO_WAKEUP_EN BIT(0) ++#define FW_FW_PARSE_MAGIC_PKT BIT(1) ++ ++void rtl8192d_set_wowlan_cmd(_adapter* padapter); ++void SetFwRelatedForWoWLAN8192DU(_adapter* padapter,u8 bHostIsGoingtoSleep); ++#endif // CONFIG_WOWLAN ++ ++ +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/include/rtl8192d_dm.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/include/rtl8192d_dm.h 2013-07-26 19:36:06.000000000 +0000 +@@ -0,0 +1,414 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++******************************************************************************/ ++#ifndef __RTL8192D_DM_H__ ++#define __RTL8192D_DM_H__ ++//============================================================ ++// Description: ++// ++// This file is for 92CE/92CU dynamic mechanism only ++// ++// ++//============================================================ ++//============================================================ ++// Global var ++//============================================================ ++ ++extern u32 EDCAParam[maxAP][3] ; ++ ++#define OFDM_TABLE_SIZE 37 ++#define OFDM_TABLE_SIZE_92D 43 ++#define CCK_TABLE_SIZE 33 ++extern u32 OFDMSwingTable[OFDM_TABLE_SIZE_92D] ; ++ ++extern u8 CCKSwingTable_Ch1_Ch13[CCK_TABLE_SIZE][8]; ++ ++extern u8 CCKSwingTable_Ch14 [CCK_TABLE_SIZE][8]; ++ ++//============================================================ ++// structure and define ++//============================================================ ++ ++typedef struct _FALSE_ALARM_STATISTICS{ ++ u32 Cnt_Parity_Fail; ++ u32 Cnt_Rate_Illegal; ++ u32 Cnt_Crc8_fail; ++ u32 Cnt_Mcs_fail; ++ u32 Cnt_Ofdm_fail; ++ u32 Cnt_Cck_fail; ++ u32 Cnt_all; ++ u32 Cnt_Fast_Fsync; ++ u32 Cnt_SB_Search_fail; ++}FALSE_ALARM_STATISTICS, *PFALSE_ALARM_STATISTICS; ++ ++typedef struct _Dynamic_Power_Saving_ ++{ ++ u8 PreCCAState; ++ u8 CurCCAState; ++ ++ u8 PreRFState; ++ u8 CurRFState; ++ ++ //int Rssi_val_min; ++ ++}PS_T,*pPS_T; ++ ++typedef struct _Dynamic_Initial_Gain_Threshold_ ++{ ++ u8 Dig_Enable_Flag; ++ u8 Dig_Ext_Port_Stage; ++ ++ int RssiLowThresh; ++ int RssiHighThresh; ++ ++ u32 FALowThresh; ++ u32 FAHighThresh; ++ ++ u8 CurSTAConnectState; ++ u8 PreSTAConnectState; ++ u8 CurMultiSTAConnectState; ++ ++ u8 PreIGValue; ++ u8 CurIGValue; ++ u8 BackupIGValue; ++ ++ char BackoffVal; ++ char BackoffVal_range_max; ++ char BackoffVal_range_min; ++ u8 rx_gain_range_max; ++ u8 rx_gain_range_min; ++ u8 Rssi_val_min; ++ ++ u8 PreCCKPDState; ++ u8 CurCCKPDState; ++ ++ u8 LargeFAHit; ++ u8 ForbiddenIGI; ++ u32 Recover_cnt; ++}DIG_T,*pDIG_T; ++typedef enum tag_Dynamic_Init_Gain_Operation_Type_Definition ++{ ++ DIG_TYPE_THRESH_HIGH = 0, ++ DIG_TYPE_THRESH_LOW = 1, ++ DIG_TYPE_BACKOFF = 2, ++ DIG_TYPE_RX_GAIN_MIN = 3, ++ DIG_TYPE_RX_GAIN_MAX = 4, ++ DIG_TYPE_ENABLE = 5, ++ DIG_TYPE_DISABLE = 6, ++ DIG_OP_TYPE_MAX ++}DM_DIG_OP_E; ++ ++typedef enum tag_CCK_Packet_Detection_Threshold_Type_Definition ++{ ++ CCK_PD_STAGE_LowRssi = 0, ++ CCK_PD_STAGE_HighRssi = 1, ++ CCK_PD_STAGE_MAX = 3, ++}DM_CCK_PDTH_E; ++ ++typedef enum tag_1R_CCA_Type_Definition ++{ ++ CCA_MIN = 0, ++ CCA_1R =1, ++ CCA_2R = 2, ++ CCA_MAX = 3, ++}DM_1R_CCA_E; ++ ++typedef enum tag_RF_Type_Definition ++{ ++ RF_Save =0, ++ RF_Normal = 1, ++ RF_MAX = 2, ++}DM_RF_E; ++ ++typedef enum tag_DIG_EXT_PORT_ALGO_Definition ++{ ++ DIG_EXT_PORT_STAGE_0 = 0, ++ DIG_EXT_PORT_STAGE_1 = 1, ++ DIG_EXT_PORT_STAGE_2 = 2, ++ DIG_EXT_PORT_STAGE_3 = 3, ++ DIG_EXT_PORT_STAGE_MAX = 4, ++}DM_DIG_EXT_PORT_ALG_E; ++ ++ ++typedef enum tag_DIG_Connect_Definition ++{ ++ DIG_STA_DISCONNECT = 0, ++ DIG_STA_CONNECT = 1, ++ DIG_STA_BEFORE_CONNECT = 2, ++ DIG_MultiSTA_DISCONNECT = 3, ++ DIG_MultiSTA_CONNECT = 4, ++ DIG_CONNECT_MAX ++}DM_DIG_CONNECT_E; ++ ++ ++#define DM_DIG_THRESH_HIGH 40 ++#define DM_DIG_THRESH_LOW 35 ++ ++#define DM_FALSEALARM_THRESH_LOW 400 ++#define DM_FALSEALARM_THRESH_HIGH 1000 ++ ++#define DM_DIG_MAX 0x3e ++#define DM_DIG_MIN 0x1e //0x22//0x1c ++ ++#define DM_DIG_FA_UPPER 0x32 ++#define DM_DIG_FA_LOWER 0x20 ++ ++//vivi 92c&92d has different definition, 20110504 ++//this is for 92c ++#define DM_DIG_FA_TH0 0x200//0x20 ++#define DM_DIG_FA_TH1 0x300//0x100 ++#define DM_DIG_FA_TH2 0x400//0x200 ++//this is for 92d ++#define DM_DIG_FA_TH0_92D 0x100 ++#define DM_DIG_FA_TH1_92D 0x400 ++#define DM_DIG_FA_TH2_92D 0x600 ++ ++#define DM_DIG_BACKOFF_MAX 12 ++#define DM_DIG_BACKOFF_MIN (-4) ++#define DM_DIG_BACKOFF_DEFAULT 10 ++ ++#define RxPathSelection_SS_TH_low 30 ++#define RxPathSelection_diff_TH 18 ++ ++#define DM_RATR_STA_INIT 0 ++#define DM_RATR_STA_HIGH 1 ++#define DM_RATR_STA_MIDDLE 2 ++#define DM_RATR_STA_LOW 3 ++ ++#define CTSToSelfTHVal 30 ++#define RegC38_TH 20 ++ ++#define WAIotTHVal 25 ++ ++//Dynamic Tx Power Control Threshold ++#define TX_POWER_NEAR_FIELD_THRESH_LVL2 74 ++#define TX_POWER_NEAR_FIELD_THRESH_LVL1 67 ++ ++#define TxHighPwrLevel_Normal 0 ++#define TxHighPwrLevel_Level1 1 ++#define TxHighPwrLevel_Level2 2 ++#define TxHighPwrLevel_BT1 3 ++#define TxHighPwrLevel_BT2 4 ++#define TxHighPwrLevel_15 5 ++#define TxHighPwrLevel_35 6 ++#define TxHighPwrLevel_50 7 ++#define TxHighPwrLevel_70 8 ++#define TxHighPwrLevel_100 9 ++ ++#define DM_Type_ByFW 0 ++#define DM_Type_ByDriver 1 ++ ++typedef struct _RATE_ADAPTIVE ++{ ++ u8 RateAdaptiveDisabled; ++ u8 RATRState; ++ u16 reserve; ++ ++ u32 HighRSSIThreshForRA; ++ u32 High2LowRSSIThreshForRA; ++ u8 Low2HighRSSIThreshForRA40M; ++ u32 LowRSSIThreshForRA40M; ++ u8 Low2HighRSSIThreshForRA20M; ++ u32 LowRSSIThreshForRA20M; ++ u32 UpperRSSIThresholdRATR; ++ u32 MiddleRSSIThresholdRATR; ++ u32 LowRSSIThresholdRATR; ++ u32 LowRSSIThresholdRATR40M; ++ u32 LowRSSIThresholdRATR20M; ++ u8 PingRSSIEnable; //cosa add for Netcore long range ping issue ++ u32 PingRSSIRATR; //cosa add for Netcore long range ping issue ++ u32 PingRSSIThreshForRA;//cosa add for Netcore long range ping issue ++ u32 LastRATR; ++ u8 PreRATRState; ++ ++} RATE_ADAPTIVE, *PRATE_ADAPTIVE; ++ ++typedef enum tag_SW_Antenna_Switch_Definition ++{ ++ Antenna_B = 1, ++ Antenna_A = 2, ++ Antenna_MAX = 3, ++}DM_SWAS_E; ++ ++// 20100514 Joseph: Add definition for antenna switching test after link. ++// This indicates two different the steps. ++// In SWAW_STEP_PEAK, driver needs to switch antenna and listen to the signal on the air. ++// In SWAW_STEP_DETERMINE, driver just compares the signal captured in SWAW_STEP_PEAK ++// with original RSSI to determine if it is necessary to switch antenna. ++#define SWAW_STEP_PEAK 0 ++#define SWAW_STEP_DETERMINE 1 ++ ++#define TP_MODE 0 ++#define RSSI_MODE 1 ++#define TRAFFIC_LOW 0 ++#define TRAFFIC_HIGH 1 ++ ++//============================= ++//Neil Chen---2011--06--15-- ++//============================== ++//3 PathDiv ++typedef struct _SW_Antenna_Switch_ ++{ ++ u8 try_flag; ++ s32 PreRSSI; ++ u8 CurAntenna; ++ u8 PreAntenna; ++ u8 RSSI_Trying; ++ u8 TestMode; ++ u8 bTriggerAntennaSwitch; ++ u8 SelectAntennaMap; ++ ++ // Before link Antenna Switch check ++ u8 SWAS_NoLink_State; ++ u32 SWAS_NoLink_BK_Reg860; ++}SWAT_T, *pSWAT_T; ++//======================================== ++ ++struct dm_priv ++{ ++ u8 DM_Type; ++ u8 DMFlag, DMFlag_tmp; ++ ++ //for DIG ++ u8 bDMInitialGainEnable; ++ //u8 binitialized; // for dm_initial_gain_Multi_STA use. ++ DIG_T DM_DigTable; ++ ++ PS_T DM_PSTable; ++ ++ FALSE_ALARM_STATISTICS FalseAlmCnt; ++ ++ //for rate adaptive, in fact, 88c/92c fw will handle this ++ u8 bUseRAMask; ++ RATE_ADAPTIVE RateAdaptive; ++ ++ //* Upper and Lower Signal threshold for Rate Adaptive*/ ++ int UndecoratedSmoothedPWDB; ++ int EntryMinUndecoratedSmoothedPWDB; ++ int EntryMaxUndecoratedSmoothedPWDB; ++ int MinUndecoratedPWDBForDM; ++ int LastMinUndecoratedPWDBForDM; ++ ++ //for High Power ++ u8 bDynamicTxPowerEnable; ++ u8 LastDTPLvl; ++ u8 DynamicTxHighPowerLvl;//Add by Jacken Tx Power Control for Near/Far Range 2008/03/06 ++ ++ //for tx power tracking ++ u8 bTXPowerTracking; ++ u8 TXPowercount; ++ u8 bTXPowerTrackingInit; ++ u8 TxPowerTrackControl; //for mp mode, turn off txpwrtracking as default ++ u8 TM_Trigger; ++ ++ u8 ThermalMeter[2]; // ThermalMeter, index 0 for RFIC0, and 1 for RFIC1 ++ u8 ThermalValue; ++ u8 ThermalValue_LCK; ++ u8 ThermalValue_IQK; ++ u8 ThermalValue_AVG[AVG_THERMAL_NUM]; ++ u8 ThermalValue_AVG_index; ++ u8 ThermalValue_RxGain; ++ u8 ThermalValue_Crystal; ++ u8 Delta_IQK; ++ u8 Delta_LCK; ++ u8 bRfPiEnable; ++ u8 bReloadtxpowerindex; ++ u8 bDoneTxpower; ++ ++ //for APK ++ u32 APKoutput[2][2]; //path A/B; output1_1a/output1_2a ++ u8 bAPKdone; ++ u8 bAPKThermalMeterIgnore; ++ BOOLEAN bDPKdone[2]; ++ BOOLEAN bDPKstore; ++ BOOLEAN bDPKworking; ++ u8 OFDM_min_index_internalPA_DPK[2]; ++ u8 TxPowerLevelDPK[2]; ++ ++ u32 RegA24; ++ ++ //for IQK ++ u32 Reg874; ++ u32 RegC08; ++ u32 Reg88C; ++ u8 Reg522; ++ u8 Reg550; ++ u8 Reg551; ++ u32 Reg870; ++ u32 ADDA_backup[IQK_ADDA_REG_NUM]; ++ u32 IQK_MAC_backup[IQK_MAC_REG_NUM]; ++ u32 IQK_BB_backup[IQK_BB_REG_NUM]; ++ ++ u8 bCCKinCH14; ++ ++ char CCK_index; ++ //u8 Record_CCK_20Mindex; ++ //u8 Record_CCK_40Mindex; ++ char OFDM_index[2]; ++ ++ SWAT_T DM_SWAT_Table; ++ ++ //Neil Chen----2011--06--23----- ++ //3 Path Diversity ++ BOOLEAN bPathDiv_Enable; //For 92D Non-interrupt Antenna Diversity by Neil ,add by wl.2011.07.19 ++ BOOLEAN RSSI_test; ++ s32 RSSI_sum_A; ++ s32 RSSI_cnt_A; ++ s32 RSSI_sum_B; ++ s32 RSSI_cnt_B; ++ struct sta_info *RSSI_target; ++ _timer PathDivSwitchTimer; ++ ++ //for TxPwrTracking ++ int RegE94; ++ int RegE9C; ++ int RegEB4; ++ int RegEBC; ++#if MP_DRIVER == 1 ++ u8 RegC04_MP; ++ u32 RegD04_MP; ++#endif ++ u32 TXPowerTrackingCallbackCnt; //cosa add for debug ++ ++ u32 prv_traffic_idx; // edca turbo ++ ++ u32 RegRF3C[2]; //pathA / pathB ++ ++ // Add for Reading Initial Data Rate SEL Register 0x484 during watchdog. Using for fill tx desc. 2011.3.21 by Thomas ++ u8 INIDATA_RATE[32]; ++}; ++ ++ ++/*------------------------Export global variable----------------------------*/ ++/*------------------------Export global variable----------------------------*/ ++/*------------------------Export Marco Definition---------------------------*/ ++//#define DM_MultiSTA_InitGainChangeNotify(Event) {DM_DigTable.CurMultiSTAConnectState = Event;} ++ ++ ++//============================================================ ++// function prototype ++//============================================================ ++void rtl8192d_init_dm_priv(IN PADAPTER Adapter); ++void rtl8192d_deinit_dm_priv(IN PADAPTER Adapter); ++void rtl8192d_InitHalDm(IN PADAPTER Adapter); ++void rtl8192d_HalDmWatchDog(IN PADAPTER Adapter); ++ ++VOID rtl8192d_dm_CheckTXPowerTracking(IN PADAPTER Adapter); ++ ++#endif //__HAL8190PCIDM_H__ +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/include/rtl8192d_hal.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/include/rtl8192d_hal.h 2013-07-26 19:36:06.000000000 +0000 +@@ -0,0 +1,983 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef __RTL8192D_HAL_H__ ++#define __RTL8192D_HAL_H__ ++ ++#include "rtl8192d_spec.h" ++#include "Hal8192DPhyReg.h" ++#include "Hal8192DPhyCfg.h" ++#include "rtl8192d_rf.h" ++#include "rtl8192d_dm.h" ++#include "rtl8192d_recv.h" ++#include "rtl8192d_xmit.h" ++#include "rtl8192d_cmd.h" ++ ++#ifdef CONFIG_PCI_HCI ++ #include ++ #include "Hal8192DEHWImg.h" ++ ++ #define RTL819X_DEFAULT_RF_TYPE RF_2T2R ++ ++//--------------------------------------------------------------------- ++// RTL8192DE From file ++//--------------------------------------------------------------------- ++ #define RTL8192D_FW_IMG "rtl8192DE\\rtl8192dfw.bin" ++ ++ #define RTL8192D_PHY_REG "rtl8192DE\\PHY_REG.txt" ++ #define RTL8192D_PHY_REG_PG "rtl8192DE\\PHY_REG_PG.txt" ++ #define RTL8192D_PHY_REG_MP "rtl8192DE\\PHY_REG_MP.txt" ++ ++ #define RTL8192D_AGC_TAB "rtl8192DE\\AGC_TAB.txt" ++ #define RTL8192D_AGC_TAB_2G "rtl8192DE\\AGC_TAB_2G.txt" ++ #define RTL8192D_AGC_TAB_5G "rtl8192DE\\AGC_TAB_5G.txt" ++ #define RTL8192D_PHY_RADIO_A "rtl8192DE\\radio_a.txt" ++ #define RTL8192D_PHY_RADIO_B "rtl8192DE\\radio_b.txt" ++ #define RTL8192D_PHY_RADIO_A_intPA "rtl8192DE\\radio_a_intPA.txt" ++ #define RTL8192D_PHY_RADIO_B_intPA "rtl8192DE\\radio_b_intPA.txt" ++ #define RTL8192D_PHY_MACREG "rtl8192DE\\MAC_REG.txt" ++ ++//--------------------------------------------------------------------- ++// RTL8192DE From header ++//--------------------------------------------------------------------- ++ ++ // Fw Array ++ #define Rtl8192D_FwImageArray Rtl8192DEFwImgArray ++ ++ // MAC/BB/PHY Array ++ #define Rtl8192D_MAC_Array Rtl8192DEMAC_2T_Array ++ #define Rtl8192D_AGCTAB_Array Rtl8192DEAGCTAB_Array ++ #define Rtl8192D_AGCTAB_5GArray Rtl8192DEAGCTAB_5GArray ++ #define Rtl8192D_AGCTAB_2GArray Rtl8192DEAGCTAB_2GArray ++ #define Rtl8192D_AGCTAB_2TArray Rtl8192DEAGCTAB_2TArray ++ #define Rtl8192D_AGCTAB_1TArray Rtl8192DEAGCTAB_1TArray ++ #define Rtl8192D_PHY_REG_2TArray Rtl8192DEPHY_REG_2TArray ++ #define Rtl8192D_PHY_REG_1TArray Rtl8192DEPHY_REG_1TArray ++ #define Rtl8192D_PHY_REG_Array_PG Rtl8192DEPHY_REG_Array_PG ++ #define Rtl8192D_PHY_REG_Array_MP Rtl8192DEPHY_REG_Array_MP ++ #define Rtl8192D_RadioA_2TArray Rtl8192DERadioA_2TArray ++ #define Rtl8192D_RadioA_1TArray Rtl8192DERadioA_1TArray ++ #define Rtl8192D_RadioB_2TArray Rtl8192DERadioB_2TArray ++ #define Rtl8192D_RadioB_1TArray Rtl8192DERadioB_1TArray ++ #define Rtl8192D_RadioA_2T_intPAArray Rtl8192DERadioA_2T_intPAArray ++ #define Rtl8192D_RadioB_2T_intPAArray Rtl8192DERadioB_2T_intPAArray ++ ++ // Array length ++ #define Rtl8192D_FwImageArrayLength Rtl8192DEImgArrayLength ++ #define Rtl8192D_MAC_ArrayLength Rtl8192DEMAC_2T_ArrayLength ++ #define Rtl8192D_AGCTAB_5GArrayLength Rtl8192DEAGCTAB_5GArrayLength ++ #define Rtl8192D_AGCTAB_2GArrayLength Rtl8192DEAGCTAB_2GArrayLength ++ #define Rtl8192D_AGCTAB_2TArrayLength Rtl8192DEAGCTAB_2TArrayLength ++ #define Rtl8192D_AGCTAB_1TArrayLength Rtl8192DEAGCTAB_1TArrayLength ++ #define Rtl8192D_AGCTAB_ArrayLength Rtl8192DEAGCTAB_ArrayLength ++ #define Rtl8192D_PHY_REG_2TArrayLength Rtl8192DEPHY_REG_2TArrayLength ++ #define Rtl8192D_PHY_REG_1TArrayLength Rtl8192DEPHY_REG_1TArrayLength ++ #define Rtl8192D_PHY_REG_Array_PGLength Rtl8192DEPHY_REG_Array_PGLength ++ #define Rtl8192D_PHY_REG_Array_MPLength Rtl8192DEPHY_REG_Array_MPLength ++ #define Rtl8192D_RadioA_2TArrayLength Rtl8192DERadioA_2TArrayLength ++ #define Rtl8192D_RadioB_2TArrayLength Rtl8192DERadioB_2TArrayLength ++ #define Rtl8192D_RadioA_2T_intPAArrayLength Rtl8192DERadioA_2T_intPAArrayLength ++ #define Rtl8192D_RadioB_2T_intPAArrayLength Rtl8192DERadioB_2T_intPAArrayLength ++ ++#elif defined(CONFIG_USB_HCI) ++ ++ #include "Hal8192DUHWImg.h" ++#ifdef CONFIG_WOWLAN ++ #include "Hal8192DUHWImg_wowlan.h" ++#endif //CONFIG_WOWLAN ++ #define RTL819X_DEFAULT_RF_TYPE RF_1T2R ++ ++//--------------------------------------------------------------------- ++// RTL8192DU From file ++//--------------------------------------------------------------------- ++ #define RTL8192D_FW_IMG "rtl8192DU\\rtl8192dfw.bin" ++ ++ #define RTL8192D_PHY_REG "rtl8192DU\\PHY_REG.txt" ++ #define RTL8192D_PHY_REG_PG "rtl8192DU\\PHY_REG_PG.txt" ++ #define RTL8192D_PHY_REG_MP "rtl8192DU\\PHY_REG_MP.txt" ++ ++ #define RTL8192D_AGC_TAB "rtl8192DU\\AGC_TAB.txt" ++ #define RTL8192D_AGC_TAB_2G "rtl8192DU\\AGC_TAB_2G.txt" ++ #define RTL8192D_AGC_TAB_5G "rtl8192DU\\AGC_TAB_5G.txt" ++ #define RTL8192D_PHY_RADIO_A "rtl8192DU\\radio_a.txt" ++ #define RTL8192D_PHY_RADIO_B "rtl8192DU\\radio_b.txt" ++ #define RTL8192D_PHY_RADIO_A_intPA "rtl8192DU\\radio_a_intPA.txt" ++ #define RTL8192D_PHY_RADIO_B_intPA "rtl8192DU\\radio_b_intPA.txt" ++ #define RTL8192D_PHY_MACREG "rtl8192DU\\MAC_REG.txt" ++ ++//--------------------------------------------------------------------- ++// RTL8192DU From header ++//--------------------------------------------------------------------- ++ ++ // Fw Array ++ #define Rtl8192D_FwImageArray Rtl8192DUFwImgArray ++#ifdef CONFIG_WOWLAN ++ #define Rtl8192D_FwWWImageArray Rtl8192DUFwWWImgArray ++#endif //CONFIG_WOWLAN ++ // MAC/BB/PHY Array ++ #define Rtl8192D_MAC_Array Rtl8192DUMAC_2T_Array ++ #define Rtl8192D_AGCTAB_Array Rtl8192DUAGCTAB_Array ++ #define Rtl8192D_AGCTAB_5GArray Rtl8192DUAGCTAB_5GArray ++ #define Rtl8192D_AGCTAB_2GArray Rtl8192DUAGCTAB_2GArray ++ #define Rtl8192D_AGCTAB_2TArray Rtl8192DUAGCTAB_2TArray ++ #define Rtl8192D_AGCTAB_1TArray Rtl8192DUAGCTAB_1TArray ++ #define Rtl8192D_PHY_REG_2TArray Rtl8192DUPHY_REG_2TArray ++ #define Rtl8192D_PHY_REG_1TArray Rtl8192DUPHY_REG_1TArray ++ #define Rtl8192D_PHY_REG_Array_PG Rtl8192DUPHY_REG_Array_PG ++ #define Rtl8192D_PHY_REG_Array_MP Rtl8192DUPHY_REG_Array_MP ++ #define Rtl8192D_RadioA_2TArray Rtl8192DURadioA_2TArray ++ #define Rtl8192D_RadioA_1TArray Rtl8192DURadioA_1TArray ++ #define Rtl8192D_RadioB_2TArray Rtl8192DURadioB_2TArray ++ #define Rtl8192D_RadioB_1TArray Rtl8192DURadioB_1TArray ++ #define Rtl8192D_RadioA_2T_intPAArray Rtl8192DURadioA_2T_intPAArray ++ #define Rtl8192D_RadioB_2T_intPAArray Rtl8192DURadioB_2T_intPAArray ++ ++ // Array length ++ #define Rtl8192D_FwImageArrayLength Rtl8192DUImgArrayLength ++ #define Rtl8192D_MAC_ArrayLength Rtl8192DUMAC_2T_ArrayLength ++ #define Rtl8192D_AGCTAB_5GArrayLength Rtl8192DUAGCTAB_5GArrayLength ++ #define Rtl8192D_AGCTAB_2GArrayLength Rtl8192DUAGCTAB_2GArrayLength ++ #define Rtl8192D_AGCTAB_2TArrayLength Rtl8192DUAGCTAB_2TArrayLength ++ #define Rtl8192D_AGCTAB_1TArrayLength Rtl8192DUAGCTAB_1TArrayLength ++ #define Rtl8192D_AGCTAB_ArrayLength Rtl8192DUAGCTAB_ArrayLength ++ #define Rtl8192D_PHY_REG_2TArrayLength Rtl8192DUPHY_REG_2TArrayLength ++ #define Rtl8192D_PHY_REG_1TArrayLength Rtl8192DUPHY_REG_1TArrayLength ++ #define Rtl8192D_PHY_REG_Array_PGLength Rtl8192DUPHY_REG_Array_PGLength ++ #define Rtl8192D_PHY_REG_Array_MPLength Rtl8192DUPHY_REG_Array_MPLength ++ #define Rtl8192D_RadioA_2TArrayLength Rtl8192DURadioA_2TArrayLength ++ #define Rtl8192D_RadioB_2TArrayLength Rtl8192DURadioB_2TArrayLength ++ #define Rtl8192D_RadioA_2T_intPAArrayLength Rtl8192DURadioA_2T_intPAArrayLength ++ #define Rtl8192D_RadioB_2T_intPAArrayLength Rtl8192DURadioB_2T_intPAArrayLength ++ ++ // The file name "_2T" is for 92CU, "_1T" is for 88CU. Modified by tynli. 2009.11.24. ++/* #define Rtl819XFwImageArray Rtl8192DUFwImgArray ++ #define Rtl819XMAC_Array Rtl8192DUMAC_2TArray ++ #define Rtl819XAGCTAB_Array Rtl8192DUAGCTAB_Array ++ #define Rtl819XAGCTAB_5GArray Rtl8192DUAGCTAB_5GArray ++ #define Rtl819XAGCTAB_2GArray Rtl8192DUAGCTAB_2GArray ++ #define Rtl819XPHY_REG_2TArray Rtl8192DUPHY_REG_2TArray ++ #define Rtl819XPHY_REG_1TArray Rtl8192DUPHY_REG_1TArray ++ #define Rtl819XRadioA_2TArray Rtl8192DURadioA_2TArray ++ #define Rtl819XRadioA_1TArray Rtl8192DURadioA_1TArray ++ #define Rtl819XRadioA_2T_intPAArray Rtl8192DURadioA_2T_intPAArray ++ #define Rtl819XRadioB_2TArray Rtl8192DURadioB_2TArray ++ #define Rtl819XRadioB_1TArray Rtl8192DURadioB_1TArray ++ #define Rtl819XRadioB_2T_intPAArray Rtl8192DURadioB_2T_intPAArray ++ #define Rtl819XPHY_REG_Array_PG Rtl8192DUPHY_REG_Array_PG ++ #define Rtl819XPHY_REG_Array_MP Rtl8192DUPHY_REG_Array_MP ++ ++ #define Rtl819XAGCTAB_2TArray Rtl8192DUAGCTAB_2TArray ++ #define Rtl819XAGCTAB_1TArray Rtl8192DUAGCTAB_1TArray*/ ++ ++#endif ++ ++#define DRVINFO_SZ 4 // unit is 8bytes ++#define PageNum_128(_Len) (u32)(((_Len)>>7) + ((_Len)&0x7F ? 1:0)) ++ ++// ++// Check if FW header exists. We do not consider the lower 4 bits in this case. ++// By tynli. 2009.12.04. ++// ++#define IS_FW_HEADER_EXIST(_pFwHdr) ((le16_to_cpu(_pFwHdr->Signature)&0xFFF0) == 0x92C0 ||\ ++ (le16_to_cpu(_pFwHdr->Signature)&0xFFF0) == 0x88C0 ||\ ++ (le16_to_cpu(_pFwHdr->Signature)&0xFFFF) == 0x92D0 ||\ ++ (le16_to_cpu(_pFwHdr->Signature)&0xFFFF) == 0x92D1 ||\ ++ (le16_to_cpu(_pFwHdr->Signature)&0xFFFF) == 0x92D2 ||\ ++ (le16_to_cpu(_pFwHdr->Signature)&0xFFFF) == 0x92D3 ) ++ ++#define FW_8192D_SIZE 0x8000 ++#define FW_8192D_START_ADDRESS 0x1000 ++ ++#define MAX_PAGE_SIZE 4096 // @ page : 4k bytes ++ ++typedef enum _FIRMWARE_SOURCE{ ++ FW_SOURCE_IMG_FILE = 0, ++ FW_SOURCE_HEADER_FILE = 1, //from header file ++}FIRMWARE_SOURCE, *PFIRMWARE_SOURCE; ++ ++typedef struct _RT_FIRMWARE{ ++ FIRMWARE_SOURCE eFWSource; ++ u8* szFwBuffer; ++ u32 ulFwLength; ++#ifdef CONFIG_WOWLAN ++ u8* szWoWLANFwBuffer; ++ u32 ulWoWLANFwLength; ++#endif //CONFIG_WOWLAN ++}RT_FIRMWARE, *PRT_FIRMWARE, RT_FIRMWARE_92D, *PRT_FIRMWARE_92D; ++ ++// ++// This structure must be cared byte-ordering ++// ++// Added by tynli. 2009.12.04. ++typedef struct _RT_8192D_FIRMWARE_HDR {//8-byte alinment required ++ ++ //--- LONG WORD 0 ---- ++ u16 Signature; // 92C0: test chip; 92C, 88C0: test chip; 88C1: MP A-cut; 92C1: MP A-cut ++ u8 Category; // AP/NIC and USB/PCI ++ u8 Function; // Reserved for different FW function indcation, for further use when driver needs to download different FW in different conditions ++ u16 Version; // FW Version ++ u8 Subversion; // FW Subversion, default 0x00 ++ u8 Rsvd1; ++ ++ ++ //--- LONG WORD 1 ---- ++ u8 Month; // Release time Month field ++ u8 Date; // Release time Date field ++ u8 Hour; // Release time Hour field ++ u8 Minute; // Release time Minute field ++ u16 RamCodeSize; // The size of RAM code ++ u16 Rsvd2; ++ ++ //--- LONG WORD 2 ---- ++ u32 SvnIdx; // The SVN entry index ++ u32 Rsvd3; ++ ++ //--- LONG WORD 3 ---- ++ u32 Rsvd4; ++ u32 Rsvd5; ++ ++}RT_8192D_FIRMWARE_HDR, *PRT_8192D_FIRMWARE_HDR; ++ ++#define DRIVER_EARLY_INT_TIME 0x05 ++#define BCN_DMA_ATIME_INT_TIME 0x02 ++ ++typedef enum _BT_CoType{ ++ BT_2Wire = 0, ++ BT_ISSC_3Wire = 1, ++ BT_Accel = 2, ++ BT_CSR = 3, ++ BT_CSR_ENHAN = 4, ++ BT_RTL8756 = 5, ++} BT_CoType, *PBT_CoType; ++ ++typedef enum _BT_CurState{ ++ BT_OFF = 0, ++ BT_ON = 1, ++} BT_CurState, *PBT_CurState; ++ ++typedef enum _BT_ServiceType{ ++ BT_SCO = 0, ++ BT_A2DP = 1, ++ BT_HID = 2, ++ BT_HID_Idle = 3, ++ BT_Scan = 4, ++ BT_Idle = 5, ++ BT_OtherAction = 6, ++ BT_Busy = 7, ++ BT_OtherBusy = 8, ++} BT_ServiceType, *PBT_ServiceType; ++ ++typedef enum _BT_RadioShared{ ++ BT_Radio_Shared = 0, ++ BT_Radio_Individual = 1, ++} BT_RadioShared, *PBT_RadioShared; ++ ++typedef struct _BT_COEXIST_STR{ ++ u8 BluetoothCoexist; ++ u8 BT_Ant_Num; ++ u8 BT_CoexistType; ++ u8 BT_State; ++ u8 BT_CUR_State; //0:on, 1:off ++ u8 BT_Ant_isolation; //0:good, 1:bad ++ u8 BT_PapeCtrl; //0:SW, 1:SW/HW dynamic ++ u8 BT_Service; ++ u8 BT_RadioSharedType; ++ u8 Ratio_Tx; ++ u8 Ratio_PRI; ++}BT_COEXIST_STR, *PBT_COEXIST_STR; ++ ++//Added for 92D IQK setting. ++typedef struct _IQK_MATRIX_REGS_SETTING{ ++ BOOLEAN bIQKDone; ++#if 1 ++ int Value[1][IQK_Matrix_REG_NUM]; ++#else ++ u32 Mark[IQK_Matrix_REG_NUM]; ++ u32 Value[IQK_Matrix_REG_NUM]; ++#endif ++}IQK_MATRIX_REGS_SETTING,*PIQK_MATRIX_REGS_SETTING; ++ ++#ifdef CONFIG_USB_RX_AGGREGATION ++ ++typedef enum _USB_RX_AGG_MODE{ ++ USB_RX_AGG_DISABLE, ++ USB_RX_AGG_DMA, ++ USB_RX_AGG_USB, ++ USB_RX_AGG_DMA_USB ++}USB_RX_AGG_MODE; ++ ++#define MAX_RX_DMA_BUFFER_SIZE 10240 // 10K for 8192C RX DMA buffer ++ ++#endif ++ ++ ++#define TX_SELE_HQ BIT(0) // High Queue ++#define TX_SELE_LQ BIT(1) // Low Queue ++#define TX_SELE_NQ BIT(2) // Normal Queue ++ ++ ++// Note: We will divide number of page equally for each queue other than public queue! ++ ++#define TX_TOTAL_PAGE_NUMBER 0xF8 ++#define TX_PAGE_BOUNDARY (TX_TOTAL_PAGE_NUMBER + 1) ++ ++// For Normal Chip Setting ++// (HPQ + LPQ + NPQ + PUBQ) shall be TX_TOTAL_PAGE_NUMBER ++#define NORMAL_PAGE_NUM_PUBQ 0x56 ++ ++ ++// For Test Chip Setting ++// (HPQ + LPQ + PUBQ) shall be TX_TOTAL_PAGE_NUMBER ++#define TEST_PAGE_NUM_PUBQ 0x89 ++#define TX_TOTAL_PAGE_NUMBER_92D_DUAL_MAC 0x7A ++#define NORMAL_PAGE_NUM_PUBQ_92D_DUAL_MAC 0x5A ++#define NORMAL_PAGE_NUM_HPQ_92D_DUAL_MAC 0x10 ++#define NORMAL_PAGE_NUM_LPQ_92D_DUAL_MAC 0x10 ++#define NORMAL_PAGE_NUM_NORMALQ_92D_DUAL_MAC 0 ++ ++#define TX_PAGE_BOUNDARY_DUAL_MAC (TX_TOTAL_PAGE_NUMBER_92D_DUAL_MAC + 1) ++ ++// For Test Chip Setting ++#define WMM_TEST_TX_TOTAL_PAGE_NUMBER 0xF5 ++#define WMM_TEST_TX_PAGE_BOUNDARY (WMM_TEST_TX_TOTAL_PAGE_NUMBER + 1) //F6 ++ ++#define WMM_TEST_PAGE_NUM_PUBQ 0xA3 ++#define WMM_TEST_PAGE_NUM_HPQ 0x29 ++#define WMM_TEST_PAGE_NUM_LPQ 0x29 ++ ++ ++//Note: For Normal Chip Setting ,modify later ++#define WMM_NORMAL_TX_TOTAL_PAGE_NUMBER 0xF5 ++#define WMM_NORMAL_TX_PAGE_BOUNDARY (WMM_TEST_TX_TOTAL_PAGE_NUMBER + 1) //F6 ++ ++#define WMM_NORMAL_PAGE_NUM_PUBQ 0xB0 ++#define WMM_NORMAL_PAGE_NUM_HPQ 0x29 ++#define WMM_NORMAL_PAGE_NUM_LPQ 0x1C ++#define WMM_NORMAL_PAGE_NUM_NPQ 0x1C ++ ++#define WMM_NORMAL_PAGE_NUM_PUBQ_92D 0X65//0x82 ++#define WMM_NORMAL_PAGE_NUM_HPQ_92D 0X30//0x29 ++#define WMM_NORMAL_PAGE_NUM_LPQ_92D 0X30 ++#define WMM_NORMAL_PAGE_NUM_NPQ_92D 0X30 ++ ++//------------------------------------------------------------------------- ++// Chip specific ++//------------------------------------------------------------------------- ++ ++#define CHIP_BONDING_IDENTIFIER(_value) (((_value)>>22)&0x3) ++#define CHIP_BONDING_92C_1T2R 0x1 ++#define CHIP_BONDING_88C_USB_MCARD 0x2 ++#define CHIP_BONDING_88C_USB_HP 0x1 ++ ++// ++// 2011.01.06. Define new structure of chip version for RTL8723 and so on. Added by tynli. ++// ++/* ++ | BIT15:12 | BIT11:8 | BIT 7 | BIT6:4 | BIT3 | BIT2:0 | ++ |-------------+-----------+-----------+-------+-----------+-------| ++ | IC version(CUT) | ROM version | Manufacturer | RF type | Chip type | IC Type | ++ | | | TSMC/UMC | | TEST/NORMAL| | ++*/ ++// [15:12] IC version(CUT): A-cut=0, B-cut=1, C-cut=2, D-cut=3 ++// [7] Manufacturer: TSMC=0, UMC=1 ++// [6:4] RF type: 1T1R=0, 1T2R=1, 2T2R=2 ++// [3] Chip type: TEST=0, NORMAL=1 ++// [2:0] IC type: 81xxC=0, 8723=1, 92D=2 ++ ++#define CHIP_8723 BIT(0) ++#define CHIP_92D BIT(1) ++#define NORMAL_CHIP BIT(3) ++#define RF_TYPE_1T1R (~(BIT(4)|BIT(5)|BIT(6))) ++#define RF_TYPE_1T2R BIT(4) ++#define RF_TYPE_2T2R BIT(5) ++#define CHIP_VENDOR_UMC BIT(7) ++#define B_CUT_VERSION BIT(12) ++#define C_CUT_VERSION BIT(13) ++#define D_CUT_VERSION ((BIT(12)|BIT(13))) ++#define E_CUT_VERSION BIT(14) ++ ++ ++// MASK ++#define IC_TYPE_MASK (BIT(0)|BIT(1)|BIT(2)) ++#define CHIP_TYPE_MASK BIT(3) ++#define RF_TYPE_MASK (BIT(4)|BIT(5)|BIT(6)) ++#define MANUFACTUER_MASK BIT(7) ++#define ROM_VERSION_MASK (BIT(11)|BIT(10)|BIT(9)|BIT(8)) ++#define CUT_VERSION_MASK (BIT(15)|BIT(14)|BIT(13)|BIT(12)) ++ ++// Get element ++#define GET_CVID_IC_TYPE(version) ((version) & IC_TYPE_MASK) ++#define GET_CVID_CHIP_TYPE(version) ((version) & CHIP_TYPE_MASK) ++#define GET_CVID_RF_TYPE(version) ((version) & RF_TYPE_MASK) ++#define GET_CVID_MANUFACTUER(version) ((version) & MANUFACTUER_MASK) ++#define GET_CVID_ROM_VERSION(version) ((version) & ROM_VERSION_MASK) ++#define GET_CVID_CUT_VERSION(version) ((version) & CUT_VERSION_MASK) ++ ++#define IS_81XXC(version) ((GET_CVID_IC_TYPE(version) == 0)? _TRUE : _FALSE) ++#define IS_8723_SERIES(version) ((GET_CVID_IC_TYPE(version) == CHIP_8723)? _TRUE : _FALSE) ++#define IS_92D(version) ((GET_CVID_IC_TYPE(version) == CHIP_92D)? _TRUE : _FALSE) ++#define IS_1T1R(version) ((GET_CVID_RF_TYPE(version))? _FALSE : _TRUE) ++#define IS_1T2R(version) ((GET_CVID_RF_TYPE(version) == RF_TYPE_1T2R)? _TRUE : _FALSE) ++#define IS_2T2R(version) ((GET_CVID_RF_TYPE(version) == RF_TYPE_2T2R)? _TRUE : _FALSE) ++#define IS_CHIP_VENDOR_UMC(version) ((GET_CVID_MANUFACTUER(version))? _TRUE: _FALSE) ++ ++#define IS_92C_SERIAL(version) ((IS_81XXC(version) && IS_2T2R(version)) ? _TRUE : _FALSE) ++#define IS_VENDOR_UMC_A_CUT(version) ((IS_CHIP_VENDOR_UMC(version)) ? ((GET_CVID_CUT_VERSION(version)) ? _FALSE : _TRUE) : _FALSE) ++#define IS_VENDOR_8723_A_CUT(version) ((IS_8723_SERIES(version)) ? ((GET_CVID_CUT_VERSION(version)) ? _FALSE : _TRUE) : _FALSE) ++// 88/92C UMC B-cut vendor is set to TSMC so we need to check CHIP_VENDOR_UMC bit is not 1. ++#define IS_81xxC_VENDOR_UMC_B_CUT(version) ((IS_CHIP_VENDOR_UMC(version)) ? ((GET_CVID_CUT_VERSION(version) == B_CUT_VERSION) ? _TRUE : _FALSE):_FALSE) ++#define IS_92D_SINGLEPHY(version) ((IS_92D(version)) ? (IS_2T2R(version) ? _TRUE: _FALSE) : _FALSE) ++ ++#define IS_92D_C_CUT(version) ((IS_92D(version)) ? ((GET_CVID_CUT_VERSION(version) == C_CUT_VERSION) ? _TRUE : _FALSE) : _FALSE) ++#define IS_92D_D_CUT(version) ((IS_92D(version)) ? ((GET_CVID_CUT_VERSION(version) == D_CUT_VERSION) ? _TRUE : _FALSE) : _FALSE) ++#define IS_92D_E_CUT(version) ((IS_92D(version)) ? ((GET_CVID_CUT_VERSION(version) == E_CUT_VERSION) ? _TRUE : _FALSE) : _FALSE) ++#define IS_NORMAL_CHIP92D(version) ((GET_CVID_CHIP_TYPE(version))? _TRUE: _FALSE) ++ ++typedef enum _VERSION_8192D{ ++ VERSION_TEST_CHIP_88C = 0x0000, ++ VERSION_TEST_CHIP_92C = 0x0020, ++ VERSION_TEST_UMC_CHIP_8723 = 0x0081, ++ VERSION_NORMAL_TSMC_CHIP_88C = 0x0008, ++ VERSION_NORMAL_TSMC_CHIP_92C = 0x0028, ++ VERSION_NORMAL_TSMC_CHIP_92C_1T2R = 0x0018, ++ VERSION_NORMAL_UMC_CHIP_88C_A_CUT = 0x0088, ++ VERSION_NORMAL_UMC_CHIP_92C_A_CUT = 0x00a8, ++ VERSION_NORMAL_UMC_CHIP_92C_1T2R_A_CUT = 0x0098, ++ VERSION_NORMAL_UMC_CHIP_8723_1T1R_A_CUT = 0x0089, ++ VERSION_NORMAL_UMC_CHIP_8723_1T1R_B_CUT = 0x1089, ++ VERSION_NORMAL_UMC_CHIP_88C_B_CUT = 0x1088, ++ VERSION_NORMAL_UMC_CHIP_92C_B_CUT = 0x10a8, ++ VERSION_NORMAL_UMC_CHIP_92C_1T2R_B_CUT = 0x1090, ++ VERSION_TEST_CHIP_92D_SINGLEPHY= 0x0022, ++ VERSION_TEST_CHIP_92D_DUALPHY = 0x0002, ++ VERSION_NORMAL_CHIP_92D_SINGLEPHY= 0x002a, ++ VERSION_NORMAL_CHIP_92D_DUALPHY = 0x000a, ++ VERSION_NORMAL_CHIP_92D_C_CUT_SINGLEPHY = 0x202a, ++ VERSION_NORMAL_CHIP_92D_C_CUT_DUALPHY = 0x200a, ++ VERSION_NORMAL_CHIP_92D_D_CUT_SINGLEPHY = 0x302a, ++ VERSION_NORMAL_CHIP_92D_D_CUT_DUALPHY = 0x300a, ++ VERSION_NORMAL_CHIP_92D_E_CUT_SINGLEPHY = 0x402a, ++ VERSION_NORMAL_CHIP_92D_E_CUT_DUALPHY = 0x400a, ++}VERSION_8192D,*PVERSION_8192D; ++ ++ ++//------------------------------------------------------------------------- ++// Channel Plan ++//------------------------------------------------------------------------- ++enum ChannelPlan{ ++ CHPL_FCC = 0, ++ CHPL_IC = 1, ++ CHPL_ETSI = 2, ++ CHPL_SPAIN = 3, ++ CHPL_FRANCE = 4, ++ CHPL_MKK = 5, ++ CHPL_MKK1 = 6, ++ CHPL_ISRAEL = 7, ++ CHPL_TELEC = 8, ++ CHPL_GLOBAL = 9, ++ CHPL_WORLD = 10, ++}; ++ ++typedef struct _TxPowerInfo{ ++ u8 CCKIndex[RF_PATH_MAX][CHANNEL_GROUP_MAX]; ++ u8 HT40_1SIndex[RF_PATH_MAX][CHANNEL_GROUP_MAX]; ++ u8 HT40_2SIndexDiff[RF_PATH_MAX][CHANNEL_GROUP_MAX]; ++ s8 HT20IndexDiff[RF_PATH_MAX][CHANNEL_GROUP_MAX]; ++ u8 OFDMIndexDiff[RF_PATH_MAX][CHANNEL_GROUP_MAX]; ++ u8 HT40MaxOffset[RF_PATH_MAX][CHANNEL_GROUP_MAX]; ++ u8 HT20MaxOffset[RF_PATH_MAX][CHANNEL_GROUP_MAX]; ++ u8 TSSI_A[3]; ++ u8 TSSI_B[3]; ++ u8 TSSI_A_5G[3]; //5GL/5GM/5GH ++ u8 TSSI_B_5G[3]; ++}TxPowerInfo, *PTxPowerInfo; ++ ++#define EFUSE_REAL_CONTENT_LEN 1024 ++#define EFUSE_MAP_LEN 256 ++#define EFUSE_MAX_SECTION 32 ++#define EFUSE_MAX_SECTION_BASE 16 ++// To prevent out of boundary programming case, leave 1byte and program full section ++// 9bytes + 1byt + 5bytes and pre 1byte. ++// For worst case: ++// | 2byte|----8bytes----|1byte|--7bytes--| //92D ++#define EFUSE_OOB_PROTECT_BYTES 18 // PG data exclude header, dummy 7 bytes frome CP test and reserved 1byte. ++ ++typedef enum _PA_MODE { ++ PA_MODE_EXTERNAL = 0x00, ++ PA_MODE_INTERNAL_SP3T = 0x01, ++ PA_MODE_INTERNAL_SPDT = 0x02 ++} PA_MODE; ++ ++#ifdef CONFIG_PCI_HCI ++struct hal_data_8192de ++{ ++ VERSION_8192D VersionID; ++ ++ // add for 92D Phy mode/mac/Band mode ++ MACPHY_MODE_8192D MacPhyMode92D; ++ BAND_TYPE CurrentBandType92D; //0:2.4G, 1:5G ++ BAND_TYPE BandSet92D; ++ BOOLEAN bIsVS; ++ BOOLEAN bSupportRemoteWakeUp; ++ u8 AutoLoadStatusFor8192D; ++ ++ BOOLEAN bNOPG; ++ ++ BOOLEAN bMasterOfDMSP; ++ BOOLEAN bSlaveOfDMSP; ++ ++ u16 CustomerID; ++ ++ u16 FirmwareVersion; ++ u16 FirmwareVersionRev; ++ u16 FirmwareSubVersion; ++ ++ u32 IntrMask[2]; ++ u32 IntrMaskToSet[2]; ++ ++ u32 DisabledFunctions; ++ ++ //current WIFI_PHY values ++ u32 ReceiveConfig; ++ u32 TransmitConfig; ++ WIRELESS_MODE CurrentWirelessMode; ++ HT_CHANNEL_WIDTH CurrentChannelBW; ++ u8 CurrentChannel; ++ u8 nCur40MhzPrimeSC;// Control channel sub-carrier ++ u16 BasicRateSet; ++ ++ //rf_ctrl ++ u8 rf_chip; ++ u8 rf_type; ++ u8 NumTotalRFPath; ++ ++ // ++ // EEPROM setting. ++ // ++ u16 EEPROMVID; ++ u16 EEPROMDID; ++ u16 EEPROMSVID; ++ u16 EEPROMSMID; ++ u16 EEPROMChannelPlan; ++ u16 EEPROMVersion; ++ ++ u8 EEPROMCustomerID; ++ u8 EEPROMBoardType; ++ u8 EEPROMRegulatory; ++ ++ u8 EEPROMThermalMeter; ++ ++ u8 EEPROMC9; ++ u8 EEPROMCC; ++ u8 PAMode; ++ ++ u8 TxPwrLevelCck[RF_PATH_MAX][CHANNEL_MAX_NUMBER_2G]; ++ u8 TxPwrLevelHT40_1S[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; // For HT 40MHZ pwr ++ u8 TxPwrLevelHT40_2S[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; // For HT 40MHZ pwr ++ s8 TxPwrHt20Diff[RF_PATH_MAX][CHANNEL_MAX_NUMBER];// HT 20<->40 Pwr diff ++ u8 TxPwrLegacyHtDiff[RF_PATH_MAX][CHANNEL_MAX_NUMBER];// For HT<->legacy pwr diff ++ // For power group ++ u8 PwrGroupHT20[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; ++ u8 PwrGroupHT40[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; ++ ++ u8 LegacyHTTxPowerDiff;// Legacy to HT rate power diff ++ ++ u8 CrystalCap; // CrystalCap. ++ ++#ifdef CONFIG_BT_COEXIST ++ struct btcoexist_priv bt_coexist; ++#endif ++ ++ // Read/write are allow for following hardware information variables ++ u8 framesync; ++ u32 framesyncC34; ++ u8 framesyncMonitor; ++ u8 DefaultInitialGain[4]; ++ u8 pwrGroupCnt; ++ u32 MCSTxPowerLevelOriginalOffset[MAX_PG_GROUP][16]; ++ u32 CCKTxPowerLevelOriginalOffset; ++ ++ u32 AntennaTxPath; // Antenna path Tx ++ u32 AntennaRxPath; // Antenna path Rx ++ u8 BluetoothCoexist; ++ u8 ExternalPA; ++ u8 InternalPA5G[2]; //pathA / pathB ++ ++ //u32 LedControlNum; ++ //u32 LedControlMode; ++ //u32 TxPowerTrackControl; ++ u8 b1x1RecvCombine; // for 1T1R receive combining ++ ++ u8 bCurrentTurboEDCA; ++ u32 AcParam_BE; //Original parameter for BE, use for EDCA turbo. ++ ++ //vivi, for tx power tracking, 20080407 ++ //u16 TSSI_13dBm; ++ //u32 Pwr_Track; ++ // The current Tx Power Level ++ u8 CurrentCckTxPwrIdx; ++ u8 CurrentOfdm24GTxPwrIdx; ++ ++ BB_REGISTER_DEFINITION_T PHYRegDef[4]; //Radio A/B/C/D ++ ++ BOOLEAN bRFPathRxEnable[4]; // We support 4 RF path now. ++ ++ u32 RfRegChnlVal[2]; ++ ++ u8 bCckHighPower; ++ ++ BOOLEAN bPhyValueInitReady; ++ ++ BOOLEAN bTXPowerDataReadFromEEPORM; ++ ++ BOOLEAN bInSetPower; ++ ++ //RDG enable ++ BOOLEAN bRDGEnable; ++ ++ BOOLEAN bLoadIMRandIQKSettingFor2G;// True if IMR or IQK have done for 2.4G in scan progress ++ BOOLEAN bNeedIQK; ++ ++ BOOLEAN bLCKInProgress; ++ ++ BOOLEAN bEarlyModeEnable; ++ ++ ATOMIC_T IQKRdyForXmit;// Tx must wait for IQK done ++ ++#if 1 ++ IQK_MATRIX_REGS_SETTING IQKMatrixRegSetting[IQK_Matrix_Settings_NUM]; ++#else ++ //regc80¡¢regc94¡¢regc4c¡¢regc88¡¢regc9c¡¢regc14¡¢regca0¡¢regc1c¡¢regc78 ++ u4Byte IQKMatrixReg[IQK_Matrix_REG_NUM]; ++ IQK_MATRIX_REGS_SETTING IQKMatrixRegSetting[IQK_Matrix_Settings_NUM]; // 1->2G,24->5G 20M channel,21->5G 40M channel. ++#endif ++ ++ //for host message to fw ++ u8 LastHMEBoxNum; ++ ++ u8 fw_ractrl; ++ // Beacon function related global variable. ++ u32 RegBcnCtrlVal; ++ u8 RegTxPause; ++ u8 RegFwHwTxQCtrl; ++ u8 RegReg542; ++ u8 RegCR_1; ++ ++ struct dm_priv dmpriv; ++ ++ u8 bInterruptMigration; ++ ++ u8 FwRsvdPageStartOffset; //2010.06.23. Added by tynli. Reserve page start offset except beacon in TxQ. ++ ++ // Add for dual MAC 0--Mac0 1--Mac1 ++ u32 interfaceIndex; ++ ++ u16 RegRRSR; ++ ++ u16 EfuseUsedBytes; ++ u8 RTSInitRate; // 2010.11.24.by tynli. ++#ifdef CONFIG_P2P ++ struct P2P_PS_Offload_t p2p_ps_offload; ++#endif //CONFIG_P2P ++}; ++ ++typedef struct hal_data_8192de HAL_DATA_TYPE, *PHAL_DATA_TYPE; ++ ++// ++// Function disabled. ++// ++#define DF_TX_BIT BIT0 ++#define DF_RX_BIT BIT1 ++#define DF_IO_BIT BIT2 ++#define DF_IO_D3_BIT BIT3 ++ ++#define RT_DF_TYPE u32 ++#define RT_DISABLE_FUNC(__pAdapter, __FuncBits) ((__pAdapter)->DisabledFunctions |= ((RT_DF_TYPE)(__FuncBits))) ++#define RT_ENABLE_FUNC(__pAdapter, __FuncBits) ((__pAdapter)->DisabledFunctions &= (~((RT_DF_TYPE)(__FuncBits)))) ++#define RT_IS_FUNC_DISABLED(__pAdapter, __FuncBits) ( (__pAdapter)->DisabledFunctions & (__FuncBits) ) ++ ++void InterruptRecognized8192DE(PADAPTER Adapter, PRT_ISR_CONTENT pIsrContent); ++VOID UpdateInterruptMask8192DE(PADAPTER Adapter, u32 AddMSR, u32 RemoveMSR); ++#endif ++ ++#ifdef CONFIG_USB_HCI ++ ++//should be renamed and moved to another file ++typedef enum _INTERFACE_SELECT_8192DUSB{ ++ INTF_SEL0_USB = 0, // USB ++ INTF_SEL1_MINICARD = 1, // Minicard ++ INTF_SEL2_EKB_PRO = 2, // Eee keyboard proprietary ++ INTF_SEL3_PRO = 3, // Customized proprietary ++} INTERFACE_SELECT_8192DUSB, *PINTERFACE_SELECT_8192DUSB; ++ ++typedef INTERFACE_SELECT_8192DUSB INTERFACE_SELECT_USB; ++ ++struct hal_data_8192du ++{ ++ VERSION_8192D VersionID; ++ ++ // add for 92D Phy mode/mac/Band mode ++ MACPHY_MODE_8192D MacPhyMode92D; ++ BAND_TYPE CurrentBandType92D; //0:2.4G, 1:5G ++ BAND_TYPE BandSet92D; ++ BOOLEAN bIsVS; ++ ++ BOOLEAN bNOPG; ++ ++ BOOLEAN bSupportRemoteWakeUp; ++ BOOLEAN bMasterOfDMSP; ++ BOOLEAN bSlaveOfDMSP; ++#ifdef CONFIG_DUALMAC_CONCURRENT ++ BOOLEAN bInModeSwitchProcess; ++#endif ++ ++ u16 CustomerID; ++ ++ u16 FirmwareVersion; ++ u16 FirmwareVersionRev; ++ u16 FirmwareSubVersion; ++ ++ //current WIFI_PHY values ++ u32 ReceiveConfig; ++ WIRELESS_MODE CurrentWirelessMode; ++ HT_CHANNEL_WIDTH CurrentChannelBW; ++ u8 CurrentChannel; ++ u8 nCur40MhzPrimeSC;// Control channel sub-carrier ++ u16 BasicRateSet; ++ ++ INTERFACE_SELECT_8192DUSB InterfaceSel; ++ ++ //rf_ctrl ++ u8 rf_chip; ++ u8 rf_type; ++ u8 NumTotalRFPath; ++ ++ // ++ // EEPROM setting. ++ // ++ u8 EEPROMVersion; ++ u16 EEPROMVID; ++ u16 EEPROMPID; ++ u16 EEPROMSVID; ++ u16 EEPROMSDID; ++ u8 EEPROMCustomerID; ++ u8 EEPROMSubCustomerID; ++ u8 EEPROMRegulatory; ++ ++ u8 EEPROMThermalMeter; ++ ++ u8 EEPROMC9; ++ u8 EEPROMCC; ++ u8 PAMode; ++ ++ u8 TxPwrLevelCck[RF_PATH_MAX][CHANNEL_MAX_NUMBER_2G]; ++ u8 TxPwrLevelHT40_1S[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; // For HT 40MHZ pwr ++ u8 TxPwrLevelHT40_2S[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; // For HT 40MHZ pwr ++ s8 TxPwrHt20Diff[RF_PATH_MAX][CHANNEL_MAX_NUMBER];// HT 20<->40 Pwr diff ++ u8 TxPwrLegacyHtDiff[RF_PATH_MAX][CHANNEL_MAX_NUMBER];// For HT<->legacy pwr diff ++ // For power group ++ u8 PwrGroupHT20[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; ++ u8 PwrGroupHT40[RF_PATH_MAX][CHANNEL_MAX_NUMBER]; ++ ++ u8 LegacyHTTxPowerDiff;// Legacy to HT rate power diff ++ ++ u8 CrystalCap; // CrystalCap. ++ ++#ifdef CONFIG_BT_COEXIST ++ struct btcoexist_priv bt_coexist; ++#endif ++ ++ // Read/write are allow for following hardware information variables ++ u8 framesync; ++ u32 framesyncC34; ++ u8 framesyncMonitor; ++ u8 DefaultInitialGain[4]; ++ u8 pwrGroupCnt; ++ u32 MCSTxPowerLevelOriginalOffset[MAX_PG_GROUP][16]; ++ u32 CCKTxPowerLevelOriginalOffset; ++ ++ u32 AntennaTxPath; // Antenna path Tx ++ u32 AntennaRxPath; // Antenna path Rx ++ u8 BluetoothCoexist; ++ u8 ExternalPA; ++ u8 InternalPA5G[2]; //pathA / pathB ++ ++ //u32 LedControlNum; ++ //u32 LedControlMode; ++ //u32 TxPowerTrackControl; ++ u8 b1x1RecvCombine; // for 1T1R receive combining ++ ++ u8 bCurrentTurboEDCA; ++ u32 AcParam_BE; //Original parameter for BE, use for EDCA turbo. ++ ++ //vivi, for tx power tracking, 20080407 ++ //u16 TSSI_13dBm; ++ //u32 Pwr_Track; ++ // The current Tx Power Level ++ u8 CurrentCckTxPwrIdx; ++ u8 CurrentOfdm24GTxPwrIdx; ++ ++ BB_REGISTER_DEFINITION_T PHYRegDef[4]; //Radio A/B/C/D ++ ++ BOOLEAN bRFPathRxEnable[4]; // We support 4 RF path now. ++ ++ u32 RfRegChnlVal[2]; ++ ++ u8 bCckHighPower; ++ ++ BOOLEAN bPhyValueInitReady; ++ ++ BOOLEAN bTXPowerDataReadFromEEPORM; ++ ++ BOOLEAN bInSetPower; ++ ++ //RDG enable ++ BOOLEAN bRDGEnable; ++ ++ BOOLEAN bLoadIMRandIQKSettingFor2G;// True if IMR or IQK have done for 2.4G in scan progress ++ BOOLEAN bNeedIQK; ++ ++ BOOLEAN bLCKInProgress; ++ ++ BOOLEAN bEarlyModeEnable; ++ ++ ATOMIC_T IQKRdyForXmit;// Tx must wait for IQK done ++ ++#if 1 ++ IQK_MATRIX_REGS_SETTING IQKMatrixRegSetting[IQK_Matrix_Settings_NUM]; ++#else ++ //regc80¡¢regc94¡¢regc4c¡¢regc88¡¢regc9c¡¢regc14¡¢regca0¡¢regc1c¡¢regc78 ++ u4Byte IQKMatrixReg[IQK_Matrix_REG_NUM]; ++ IQK_MATRIX_REGS_SETTING IQKMatrixRegSetting[IQK_Matrix_Settings_NUM]; // 1->2G,24->5G 20M channel,21->5G 40M channel. ++#endif ++ ++ //for host message to fw ++ u8 LastHMEBoxNum; ++ ++ u8 fw_ractrl; ++ // Beacon function related global variable. ++ u32 RegBcnCtrlVal; ++ u8 RegTxPause; ++ u8 RegFwHwTxQCtrl; ++ u8 RegReg542; ++ u8 RegCR_1; ++ ++ struct dm_priv dmpriv; ++ ++ u8 FwRsvdPageStartOffset; //2010.06.23. Added by tynli. Reserve page start offset except beacon in TxQ. ++ ++ //Query RF by FW ++ BOOLEAN bReadRFbyFW; ++ ++ // For 92C USB endpoint setting ++ // ++ ++ u32 UsbBulkOutSize; ++ ++ int RtBulkOutPipe[3]; ++ int RtBulkInPipe; ++ int RtIntInPipe; ++ ++ // Add for dual MAC 0--Mac0 1--Mac1 ++ u32 interfaceIndex; ++ ++ u8 OutEpQueueSel; ++ u8 OutEpNumber; ++ ++ u8 Queue2EPNum[8];//for out endpoint number mapping ++ ++#ifdef CONFIG_USB_TX_AGGREGATION ++ u8 UsbTxAggMode; ++ u8 UsbTxAggDescNum; ++#endif ++#ifdef CONFIG_USB_RX_AGGREGATION ++ u16 HwRxPageSize; // Hardware setting ++ u32 MaxUsbRxAggBlock; ++ ++ USB_RX_AGG_MODE UsbRxAggMode; ++ u8 UsbRxAggBlockCount; // USB Block count. Block size is 512-byte in hight speed and 64-byte in full speed ++ u8 UsbRxAggBlockTimeout; ++ u8 UsbRxAggPageCount; // 8192C DMA page count ++ u8 UsbRxAggPageTimeout; ++#endif ++ ++ u16 RegRRSR; ++ ++ u16 EfuseUsedBytes; ++ u8 RTSInitRate; // 2010.11.24.by tynli. ++#ifdef CONFIG_P2P ++ struct P2P_PS_Offload_t p2p_ps_offload; ++#endif //CONFIG_P2P ++}; ++ ++typedef struct hal_data_8192du HAL_DATA_TYPE, *PHAL_DATA_TYPE; ++#endif ++ ++#define GET_HAL_DATA(__pAdapter) ((HAL_DATA_TYPE *)((__pAdapter)->HalData)) ++#define GET_RF_TYPE(priv) (GET_HAL_DATA(priv)->rf_type) ++ ++int FirmwareDownload92D(IN PADAPTER Adapter,IN BOOLEAN bUsedWoWLANFw); ++VOID rtl8192d_FirmwareSelfReset(IN PADAPTER Adapter); ++void rtl8192d_ReadChipVersion(IN PADAPTER Adapter); ++VOID rtl8192d_ReadChannelPlan(PADAPTER Adapter, u8* PROMContent, BOOLEAN AutoLoadFail); ++VOID rtl8192d_ReadTxPowerInfo(PADAPTER Adapter, u8* PROMContent, BOOLEAN AutoLoadFail); ++VOID rtl8192d_ResetDualMacSwitchVariables(IN PADAPTER Adapter); ++u8 GetEEPROMSize8192D(PADAPTER Adapter); ++void rtl8192d_HalSetBrateCfg(PADAPTER Adapter, u8 *mBratesOS, u16 *pBrateCfg); ++BOOLEAN PHY_CheckPowerOffFor8192D(PADAPTER Adapter); ++VOID PHY_SetPowerOnFor8192D(PADAPTER Adapter); ++//void PHY_ConfigMacPhyMode92D(PADAPTER Adapter); ++void rtl8192d_free_hal_data(_adapter * padapter); ++void rtl8192d_set_hal_ops(struct hal_ops *pHalFunc); ++ ++#endif ++ ++#ifdef CONFIG_MP_INCLUDED ++ ++ ++extern void Hal_SetAntenna(PADAPTER pAdapter); ++extern void Hal_SetBandwidth(PADAPTER pAdapter); ++ ++extern void Hal_SetTxPower(PADAPTER pAdapter); ++extern void Hal_SetCarrierSuppressionTx(PADAPTER pAdapter, u8 bStart); ++extern void Hal_SetSingleToneTx ( PADAPTER pAdapter , u8 bStart ); ++extern void Hal_SetSingleCarrierTx (PADAPTER pAdapter, u8 bStart); ++extern void Hal_SetContinuousTx (PADAPTER pAdapter, u8 bStart); ++extern void Hal_SetBandwidth(PADAPTER pAdapter); ++ ++extern void Hal_SetDataRate(PADAPTER pAdapter); ++extern void Hal_SetChannel(PADAPTER pAdapter); ++extern void Hal_SetAntennaPathPower(PADAPTER pAdapter); ++extern s32 Hal_SetThermalMeter(PADAPTER pAdapter, u8 target_ther); ++extern s32 Hal_SetPowerTracking(PADAPTER padapter, u8 enable); ++extern void Hal_GetPowerTracking(PADAPTER padapter, u8 * enable); ++extern void Hal_GetThermalMeter(PADAPTER pAdapter, u8 *value); ++extern void Hal_mpt_SwitchRfSetting(PADAPTER pAdapter); ++extern void Hal_MPT_CCKTxPowerAdjust(PADAPTER Adapter, BOOLEAN bInCH14); ++extern void Hal_MPT_CCKTxPowerAdjustbyIndex(PADAPTER pAdapter, BOOLEAN beven); ++extern void Hal_SetCCKTxPower(PADAPTER pAdapter, u8 * TxPower); ++extern void Hal_SetOFDMTxPower(PADAPTER pAdapter, u8 * TxPower); ++extern void Hal_TriggerRFThermalMeter(PADAPTER pAdapter); ++extern u8 Hal_ReadRFThermalMeter(PADAPTER pAdapter); ++extern void Hal_SetCCKContinuousTx(PADAPTER pAdapter, u8 bStart); ++extern void Hal_SetOFDMContinuousTx(PADAPTER pAdapter, u8 bStart); ++ ++ ++#endif //end CONFIG_MP_INCLUDED ++ +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/include/rtl8192d_led.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/include/rtl8192d_led.h 2013-07-26 19:36:06.000000000 +0000 +@@ -0,0 +1,44 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ++******************************************************************************/ ++#ifndef __RTL8192D_LED_H_ ++#define __RTL8192D_LED_H_ ++ ++#include ++#include ++#include ++ ++ ++//================================================================================ ++// Interface to manipulate LED objects. ++//================================================================================ ++#ifdef CONFIG_USB_HCI ++void rtl8192du_InitSwLeds(_adapter *padapter); ++void rtl8192du_DeInitSwLeds(_adapter *padapter); ++#endif ++ ++#ifdef CONFIG_PCI_HCI ++void rtl8192de_gen_RefreshLedState(PADAPTER Adapter); ++void rtl8192de_InitSwLeds(_adapter *padapter); ++void rtl8192de_DeInitSwLeds(_adapter *padapter); ++#endif ++ ++#endif ++ +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/include/rtl8192d_recv.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/include/rtl8192d_recv.h 2013-07-26 19:36:06.000000000 +0000 +@@ -0,0 +1,179 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef _RTL8192D_RECV_H_ ++#define _RTL8192D_RECV_H_ ++ ++#include ++#include ++#include ++ ++ ++#ifdef PLATFORM_OS_XP ++ #ifdef CONFIG_SDIO_HCI ++ #define NR_RECVBUFF 1024//512//128 ++ #else ++ #define NR_RECVBUFF (16) ++ #endif ++#elif defined(PLATFORM_OS_CE) ++ #ifdef CONFIG_SDIO_HCI ++ #define NR_RECVBUFF (128) ++ #else ++ #define NR_RECVBUFF (4) ++ #endif ++#else ++ #define NR_RECVBUFF (4) ++ #define NR_PREALLOC_RECV_SKB (8) ++#endif ++ ++ ++ ++#define RECV_BLK_SZ 512 ++#define RECV_BLK_CNT 16 ++#define RECV_BLK_TH RECV_BLK_CNT ++ ++#if defined(CONFIG_USB_HCI) ++ ++#ifdef PLATFORM_OS_CE ++#define MAX_RECVBUF_SZ (8192+1024) // 8K+1k ++#else ++ #ifndef CONFIG_MINIMAL_MEMORY_USAGE ++ //#define MAX_RECVBUF_SZ (32768) // 32k ++ //#define MAX_RECVBUF_SZ (16384) //16K ++ //#define MAX_RECVBUF_SZ (10240) //10K ++ #define MAX_RECVBUF_SZ (15360) // 15k < 16k ++ #else ++ #define MAX_RECVBUF_SZ (4000) // about 4K ++ #endif ++#endif ++ ++#elif defined(CONFIG_PCI_HCI) ++//#ifndef CONFIG_MINIMAL_MEMORY_USAGE ++// #define MAX_RECVBUF_SZ (9100) ++//#else ++ #define MAX_RECVBUF_SZ (4000) // about 4K ++//#endif ++ ++#define RX_MPDU_QUEUE 0 ++#define RX_CMD_QUEUE 1 ++#define RX_MAX_QUEUE 2 ++#endif ++ ++#define RECV_BULK_IN_ADDR 0x80 ++#define RECV_INT_IN_ADDR 0x81 ++ ++#define PHY_RSSI_SLID_WIN_MAX 100 ++#define PHY_LINKQUALITY_SLID_WIN_MAX 20 ++ ++struct phy_stat ++{ ++ unsigned int phydw0; ++ ++ unsigned int phydw1; ++ ++ unsigned int phydw2; ++ ++ unsigned int phydw3; ++ ++ unsigned int phydw4; ++ ++ unsigned int phydw5; ++ ++ unsigned int phydw6; ++ ++ unsigned int phydw7; ++}; ++ ++typedef struct _Phy_OFDM_Rx_Status_Report_8192cd ++{ ++ unsigned char trsw_gain_X[4]; ++ unsigned char pwdb_all; ++ unsigned char cfosho_X[4]; ++ unsigned char cfotail_X[4]; ++ unsigned char rxevm_X[2]; ++ unsigned char rxsnr_X[4]; ++ unsigned char pdsnr_X[2]; ++ unsigned char csi_current_X[2]; ++ unsigned char csi_target_X[2]; ++ unsigned char sigevm; ++ unsigned char max_ex_pwr; ++//#ifdef RTL8192SE ++#ifdef CONFIG_LITTLE_ENDIAN ++ unsigned char ex_intf_flg:1; ++ unsigned char sgi_en:1; ++ unsigned char rxsc:2; ++ //unsigned char rsvd:4; ++ unsigned char idle_long:1; ++ unsigned char r_ant_train_en:1; ++ unsigned char ANTSELB:1; ++ unsigned char ANTSEL:1; ++#else // _BIG_ENDIAN_ ++ //unsigned char rsvd:4; ++ unsigned char ANTSEL:1; ++ unsigned char ANTSELB:1; ++ unsigned char r_ant_train_en:1; ++ unsigned char idle_long:1; ++ unsigned char rxsc:2; ++ unsigned char sgi_en:1; ++ unsigned char ex_intf_flg:1; ++#endif ++//#else // RTL8190, RTL8192E ++// unsigned char sgi_en; ++// unsigned char rxsc_sgien_exflg; ++//#endif ++}__attribute__ ((packed)) PHY_STS_OFDM_8192CD_T,PHY_RX_DRIVER_INFO_8192CD; ++ ++typedef struct _Phy_CCK_Rx_Status_Report_8192cd ++{ ++ /* For CCK rate descriptor. This is a signed 8:1 variable. LSB bit presend ++ 0.5. And MSB 7 bts presend a signed value. Range from -64~+63.5. */ ++ u8 adc_pwdb_X[4]; ++ u8 SQ_rpt; ++ u8 cck_agc_rpt; ++} PHY_STS_CCK_8192CD_T; ++ ++// Rx smooth factor ++#define Rx_Smooth_Factor (20) ++ ++#ifdef CONFIG_USB_HCI ++typedef struct _INTERRUPT_MSG_FORMAT_EX{ ++ unsigned int C2H_MSG0; ++ unsigned int C2H_MSG1; ++ unsigned int C2H_MSG2; ++ unsigned int C2H_MSG3; ++ unsigned int HISR; // from HISR Reg0x124, read to clear ++ unsigned int HISRE;// from HISRE Reg0x12c, read to clear ++ unsigned int MSG_EX; ++}INTERRUPT_MSG_FORMAT_EX,*PINTERRUPT_MSG_FORMAT_EX; ++ ++void rtl8192du_init_recvbuf(_adapter *padapter, struct recv_buf *precvbuf); ++int rtl8192du_init_recv_priv(_adapter * padapter); ++void rtl8192du_free_recv_priv(_adapter * padapter); ++#endif ++ ++#ifdef CONFIG_PCI_HCI ++int rtl8192de_init_recv_priv(_adapter * padapter); ++void rtl8192de_free_recv_priv(_adapter * padapter); ++#endif ++ ++void rtl8192d_translate_rx_signal_stuff(union recv_frame *precvframe, struct phy_stat *pphy_info); ++void rtl8192d_query_rx_desc_status(union recv_frame *precvframe, struct recv_stat *pdesc); ++ ++#endif ++ +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/include/rtl8192d_rf.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/include/rtl8192d_rf.h 2013-07-26 19:36:06.000000000 +0000 +@@ -0,0 +1,98 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ++******************************************************************************/ ++/****************************************************************************** ++ * ++ * ++ * Module: rtl8192d_rf.h ( Header File) ++ * ++ * Note: Collect every HAL RF type exter API or constant. ++ * ++ * Function: ++ * ++ * Export: ++ * ++ * Abbrev: ++ * ++ * History: ++ * Data Who Remark ++ * ++ * 09/25/2008 MHC Create initial version. ++ * ++ * ++******************************************************************************/ ++#ifndef _RTL8192D_RF_H_ ++#define _RTL8192D_RF_H_ ++/* Check to see if the file has been included already. */ ++ ++ ++/*--------------------------Define Parameters-------------------------------*/ ++ ++// ++// For RF 6052 Series ++// ++#define RF6052_MAX_TX_PWR 0x3F ++#define RF6052_MAX_REG 0x3F ++#define RF6052_MAX_PATH 2 ++/*--------------------------Define Parameters-------------------------------*/ ++ ++ ++/*------------------------------Define structure----------------------------*/ ++ ++/*------------------------------Define structure----------------------------*/ ++ ++ ++/*------------------------Export global variable----------------------------*/ ++/*------------------------Export global variable----------------------------*/ ++ ++/*------------------------Export Marco Definition---------------------------*/ ++ ++/*------------------------Export Marco Definition---------------------------*/ ++ ++ ++/*--------------------------Exported Function prototype---------------------*/ ++ ++// ++// RF RL6052 Series API ++// ++void rtl8192d_RF_ChangeTxPath( IN PADAPTER Adapter, ++ IN u16 DataRate); ++void rtl8192d_PHY_RF6052SetBandwidth( ++ IN PADAPTER Adapter, ++ IN HT_CHANNEL_WIDTH Bandwidth); ++VOID rtl8192d_PHY_RF6052SetCckTxPower( ++ IN PADAPTER Adapter, ++ IN u8* pPowerlevel); ++VOID rtl8192d_PHY_RF6052SetOFDMTxPower( ++ IN PADAPTER Adapter, ++ IN u8* pPowerLevel, ++ IN u8 Channel); ++int PHY_RF6052_Config8192D( IN PADAPTER Adapter ); ++ ++BOOLEAN rtl8192d_PHY_EnableAnotherPHY(IN PADAPTER Adapter, IN BOOLEAN bMac0); ++ ++void rtl8192d_PHY_PowerDownAnotherPHY(IN PADAPTER Adapter, IN BOOLEAN bMac0); ++ ++ ++/*--------------------------Exported Function prototype---------------------*/ ++ ++ ++#endif/* End of HalRf.h */ ++ +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/include/rtl8192d_spec.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/include/rtl8192d_spec.h 2013-07-26 19:36:06.000000000 +0000 +@@ -0,0 +1,1879 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++ ++#ifndef __RTL8192D_SPEC_H__ ++#define __RTL8192D_SPEC_H__ ++ ++#include ++ ++#ifndef BIT ++#define BIT(x) (1 << (x)) ++#endif ++ ++#define BIT0 0x00000001 ++#define BIT1 0x00000002 ++#define BIT2 0x00000004 ++#define BIT3 0x00000008 ++#define BIT4 0x00000010 ++#define BIT5 0x00000020 ++#define BIT6 0x00000040 ++#define BIT7 0x00000080 ++#define BIT8 0x00000100 ++#define BIT9 0x00000200 ++#define BIT10 0x00000400 ++#define BIT11 0x00000800 ++#define BIT12 0x00001000 ++#define BIT13 0x00002000 ++#define BIT14 0x00004000 ++#define BIT15 0x00008000 ++#define BIT16 0x00010000 ++#define BIT17 0x00020000 ++#define BIT18 0x00040000 ++#define BIT19 0x00080000 ++#define BIT20 0x00100000 ++#define BIT21 0x00200000 ++#define BIT22 0x00400000 ++#define BIT23 0x00800000 ++#define BIT24 0x01000000 ++#define BIT25 0x02000000 ++#define BIT26 0x04000000 ++#define BIT27 0x08000000 ++#define BIT28 0x10000000 ++#define BIT29 0x20000000 ++#define BIT30 0x40000000 ++#define BIT31 0x80000000 ++ ++ ++//============================================================ ++// 8192D Regsiter offset definition ++//============================================================ ++ ++ ++//============================================================ ++// ++//============================================================ ++ ++//----------------------------------------------------- ++// ++// 0x0000h ~ 0x00FFh System Configuration ++// ++//----------------------------------------------------- ++#define REG_SYS_ISO_CTRL 0x0000 ++#define REG_SYS_FUNC_EN 0x0002 ++#define REG_APS_FSMCO 0x0004 ++#define REG_SYS_CLKR 0x0008 ++#define REG_9346CR 0x000A ++#define REG_EE_VPD 0x000C ++#define REG_AFE_MISC 0x0010 ++#define REG_SPS0_CTRL 0x0011 ++#define REG_POWER_OFF_IN_PROCESS 0x0017 ++#define REG_SPS_OCP_CFG 0x0018 ++#define REG_RSV_CTRL 0x001C ++#define REG_RF_CTRL 0x001F ++#define REG_LDOA15_CTRL 0x0020 ++#define REG_LDOV12D_CTRL 0x0021 ++#define REG_LDOHCI12_CTRL 0x0022 ++#define REG_LPLDO_CTRL 0x0023 ++#define REG_AFE_XTAL_CTRL 0x0024 ++#define REG_AFE_PLL_CTRL 0x0028 ++#define REG_MAC_PHY_CTRL 0x002c //for 92d, DMDP,SMSP,DMSP contrl ++#define REG_EFUSE_CTRL 0x0030 ++#define REG_EFUSE_TEST 0x0034 ++#define REG_PWR_DATA 0x0038 ++#define REG_CAL_TIMER 0x003C ++#define REG_ACLK_MON 0x003E ++#define REG_GPIO_MUXCFG 0x0040 ++//#define REG_GPIO_MUXCFG 0x0041 ++#define REG_GPIO_IO_SEL 0x0042 ++#define REG_MAC_PINMUX_CFG 0x0043 ++#define REG_GPIO_PIN_CTRL 0x0044 ++#define REG_GPIO_INTM 0x0048 ++#define REG_LEDCFG0 0x004C ++#define REG_LEDCFG1 0x004D ++#define REG_LEDCFG2 0x004E ++#define REG_LEDCFG3 0x004F ++#define REG_FSIMR 0x0050 ++#define REG_FSISR 0x0054 ++ ++#define REG_MCUFWDL 0x0080 ++#define REG_WOWLAN_REASON 0x0081 ++#define REG_HMEBOX_EXT_0 0x0088 ++#define REG_HMEBOX_EXT_1 0x008A ++#define REG_HMEBOX_EXT_2 0x008C ++#define REG_HMEBOX_EXT_3 0x008E ++ ++#define REG_BIST_SCAN 0x00D0 ++#define REG_BIST_RPT 0x00D4 ++#define REG_BIST_ROM_RPT 0x00D8 ++#define REG_USB_SIE_INTF 0x00E0 ++#define REG_PCIE_MIO_INTF 0x00E4 ++#define REG_PCIE_MIO_INTD 0x00E8 ++#define REG_HPON_FSM 0x00EC ++#define REG_SYS_CFG 0x00F0 ++#define REG_MAC_PHY_CTRL_NORMAL 0x00f8 ++ ++#define REG_MAC0 0x0081 ++#define REG_MAC1 0x0053 ++#define FW_MAC0_ready 0x18 ++#define FW_MAC1_ready 0x1A ++#define MAC0_ON BIT7 ++#define MAC1_ON BIT0 ++#define mac0_ready BIT0 ++#define mac1_ready BIT0 ++ ++ ++//----------------------------------------------------- ++// ++// 0x0100h ~ 0x01FFh MACTOP General Configuration ++// ++//----------------------------------------------------- ++#define REG_CR 0x0100 ++#define REG_PBP 0x0104 ++#define REG_TRXDMA_CTRL 0x010C ++#define REG_TRXFF_BNDY 0x0114 ++#define REG_TRXFF_STATUS 0x0118 ++#define REG_RXFF_PTR 0x011C ++#define REG_HIMR 0x0120 ++#define REG_HISR 0x0124 ++#define REG_HIMRE 0x0128 ++#define REG_HISRE 0x012C ++#define REG_CPWM 0x012F ++#define REG_FWIMR 0x0130 ++#define REG_FWISR 0x0134 ++#define REG_FTIMR 0x0138 ++#define REG_PKTBUF_DBG_CTRL 0x0140 ++#define REG_PKTBUF_DBG_DATA_L 0x0144 ++#define REG_PKTBUF_DBG_DATA_H 0x0148 ++ ++#define REG_TC0_CTRL 0x0150 ++#define REG_TC1_CTRL 0x0154 ++#define REG_TC2_CTRL 0x0158 ++#define REG_TC3_CTRL 0x015C ++#define REG_TC4_CTRL 0x0160 ++#define REG_TCUNIT_BASE 0x0164 ++#define REG_MBIST_START 0x0174 ++#define REG_MBIST_DONE 0x0178 ++#define REG_MBIST_FAIL 0x017C ++#define REG_C2HEVT_MSG_NORMAL 0x01A0 ++#define REG_C2HEVT_CLEAR 0x01AF ++#define REG_C2HEVT_MSG_TEST 0x01B8 ++#define REG_MCUTST_1 0x01c0 ++#define REG_FMETHR 0x01C8 ++#define REG_HMETFR 0x01CC ++#define REG_HMEBOX_0 0x01D0 ++#define REG_HMEBOX_1 0x01D4 ++#define REG_HMEBOX_2 0x01D8 ++#define REG_HMEBOX_3 0x01DC ++ ++#define REG_LLT_INIT 0x01E0 ++#define REG_BB_ACCEESS_CTRL 0x01E8 ++#define REG_BB_ACCESS_DATA 0x01EC ++ ++ ++//----------------------------------------------------- ++// ++// 0x0200h ~ 0x027Fh TXDMA Configuration ++// ++//----------------------------------------------------- ++#define REG_RQPN 0x0200 ++#define REG_FIFOPAGE 0x0204 ++#define REG_TDECTRL 0x0208 ++#define REG_TXDMA_OFFSET_CHK 0x020C ++#define REG_TXDMA_STATUS 0x0210 ++#define REG_RQPN_NPQ 0x0214 ++ ++//----------------------------------------------------- ++// ++// 0x0280h ~ 0x02FFh RXDMA Configuration ++// ++//----------------------------------------------------- ++#define REG_RXDMA_AGG_PG_TH 0x0280 ++#define REG_RXPKT_NUM 0x0284 ++#define REG_RXDMA_STATUS 0x0288 ++ ++ ++//----------------------------------------------------- ++// ++// 0x0300h ~ 0x03FFh PCIe ++// ++//----------------------------------------------------- ++#define REG_PCIE_CTRL_REG 0x0300 ++#define REG_INT_MIG 0x0304 // Interrupt Migration ++#define REG_BCNQ_DESA 0x0308 // TX Beacon Descriptor Address ++#define REG_HQ_DESA 0x0310 // TX High Queue Descriptor Address ++#define REG_MGQ_DESA 0x0318 // TX Manage Queue Descriptor Address ++#define REG_VOQ_DESA 0x0320 // TX VO Queue Descriptor Address ++#define REG_VIQ_DESA 0x0328 // TX VI Queue Descriptor Address ++#define REG_BEQ_DESA 0x0330 // TX BE Queue Descriptor Address ++#define REG_BKQ_DESA 0x0338 // TX BK Queue Descriptor Address ++#define REG_RX_DESA 0x0340 // RX Queue Descriptor Address ++#define REG_DBI 0x0348 // Backdoor REG for Access Configuration ++//sherry added for DBI Read/Write 20091126 ++#define REG_DBI_WDATA 0x0348 // Backdoor REG for Access Configuration ++#define REG_DBI_RDATA 0x034C //Backdoor REG for Access Configuration ++#define REG_DBI_CTRL 0x0350 //Backdoor REG for Access Configuration ++#define REG_DBI_FLAG 0x0352 //Backdoor REG for Access Configuration#define REG_MDIO 0x0354 // MDIO for Access PCIE PHY ++#define REG_MDIO 0x0354 // MDIO for Access PCIE PHY ++#define REG_DBG_SEL 0x0360 // Debug Selection Register ++#define REG_PCIE_HRPWM 0x0361 //PCIe RPWM ++#define REG_PCIE_HCPWM 0x0363 //PCIe CPWM ++#define REG_UART_CTRL 0x0364 // UART Control ++#define REG_UART_TX_DESA 0x0370 // UART TX Descriptor Address ++#define REG_UART_RX_DESA 0x0378 // UART Rx Descriptor Address ++ ++ ++// spec version 11 ++//----------------------------------------------------- ++// ++// 0x0400h ~ 0x047Fh Protocol Configuration ++// ++//----------------------------------------------------- ++#define REG_VOQ_INFORMATION 0x0400 ++#define REG_VIQ_INFORMATION 0x0404 ++#define REG_BEQ_INFORMATION 0x0408 ++#define REG_BKQ_INFORMATION 0x040C ++#define REG_MGQ_INFORMATION 0x0410 ++#define REG_HGQ_INFORMATION 0x0414 ++#define REG_BCNQ_INFORMATION 0x0418 ++ ++ ++#define REG_CPU_MGQ_INFORMATION 0x041C ++#define REG_FWHW_TXQ_CTRL 0x0420 ++#define REG_HWSEQ_CTRL 0x0423 ++#define REG_TXPKTBUF_BCNQ_BDNY 0x0424 ++#define REG_TXPKTBUF_MGQ_BDNY 0x0425 ++#define REG_LIFETIME_EN 0x0426 ++#define REG_MULTI_BCNQ_OFFSET 0x0427 ++#define REG_SPEC_SIFS 0x0428 ++#define REG_RL 0x042A ++#define REG_DARFRC 0x0430 ++#define REG_RARFRC 0x0438 ++#define REG_RRSR 0x0440 ++#define REG_ARFR0 0x0444 ++#define REG_ARFR1 0x0448 ++#define REG_ARFR2 0x044C ++#define REG_ARFR3 0x0450 ++#define REG_AGGLEN_LMT 0x0458 ++#define REG_AMPDU_MIN_SPACE 0x045C ++#define REG_TXPKTBUF_WMAC_LBK_BF_HD 0x045D ++#define REG_FAST_EDCA_CTRL 0x0460 ++#define REG_RD_RESP_PKT_TH 0x0463 ++#define REG_INIRTS_RATE_SEL 0x0480 ++#define REG_INIDATA_RATE_SEL 0x0484 ++#define REG_POWER_STATUS 0x04A4 ++#define REG_POWER_STAGE1 0x04B4 ++#define REG_POWER_STAGE2 0x04B8 ++#define REG_PKT_VO_VI_LIFE_TIME 0x04C0 ++#define REG_PKT_BE_BK_LIFE_TIME 0x04C2 ++#define REG_STBC_SETTING 0x04C4 ++#define REG_PROT_MODE_CTRL 0x04C8 ++#define REG_MAX_AGGR_NUM 0x04CA ++#define REG_RTS_MAX_AGGR_NUM 0x04CB ++#define REG_BAR_MODE_CTRL 0x04CC ++#define REG_RA_TRY_RATE_AGG_LMT 0x04CF ++#define REG_EARLY_MODE_CONTROL 0x04D0 ++#define REG_NQOS_SEQ 0x04DC ++#define REG_QOS_SEQ 0x04DE ++#define REG_NEED_CPU_HANDLE 0x04E0 ++#define REG_PKT_LOSE_RPT 0x04E1 ++#define REG_PTCL_ERR_STATUS 0x04E2 ++#define REG_DUMMY 0x04FC ++ ++ ++ ++//----------------------------------------------------- ++// ++// 0x0500h ~ 0x05FFh EDCA Configuration ++// ++//----------------------------------------------------- ++#define REG_EDCA_VO_PARAM 0x0500 ++#define REG_EDCA_VI_PARAM 0x0504 ++#define REG_EDCA_BE_PARAM 0x0508 ++#define REG_EDCA_BK_PARAM 0x050C ++#define REG_BCNTCFG 0x0510 ++#define REG_PIFS 0x0512 ++#define REG_RDG_PIFS 0x0513 ++#define REG_SIFS_CTX 0x0514 ++#define REG_SIFS_TRX 0x0516 ++#define REG_TSFTR_SYN_OFFSET 0x0518 ++#define REG_AGGR_BREAK_TIME 0x051A ++#define REG_SLOT 0x051B ++#define REG_TX_PTCL_CTRL 0x0520 ++#define REG_TXPAUSE 0x0522 ++#define REG_DIS_TXREQ_CLR 0x0523 ++#define REG_RD_CTRL 0x0524 ++#define REG_TBTT_PROHIBIT 0x0540 ++#define REG_RD_NAV_NXT 0x0544 ++#define REG_NAV_PROT_LEN 0x0546 ++#define REG_BCN_CTRL 0x0550 ++#define REG_BCN_CTRL_1 0x0551 ++#define REG_MBID_NUM 0x0552 ++#define REG_DUAL_TSF_RST 0x0553 ++#define REG_BCN_INTERVAL 0x0554 // The same as REG_MBSSID_BCN_SPACE ++#define REG_MBSSID_BCN_SPACE 0x0554 ++#define REG_DRVERLYINT 0x0558 ++#define REG_BCNDMATIM 0x0559 ++#define REG_ATIMWND 0x055A ++#define REG_USTIME_TSF 0x055C ++#define REG_BCN_MAX_ERR 0x055D ++#define REG_RXTSF_OFFSET_CCK 0x055E ++#define REG_RXTSF_OFFSET_OFDM 0x055F ++#define REG_TSFTR 0x0560 ++#define REG_TSFTR1 0x0568 ++#define REG_INIT_TSFTR 0x0564 ++#define REG_ATIMWND_1 0x0570 ++#define REG_PSTIMER 0x0580 ++#define REG_TIMER0 0x0584 ++#define REG_TIMER1 0x0588 ++#define REG_ACMHWCTRL 0x05C0 ++#define REG_ACMRSTCTRL 0x05C1 ++#define REG_ACMAVG 0x05C2 ++#define REG_VO_ADMTIME 0x05C4 ++#define REG_VI_ADMTIME 0x05C6 ++#define REG_BE_ADMTIME 0x05C8 ++#define REG_EDCA_RANDOM_GEN 0x05CC ++#define REG_SCH_TXCMD 0x05D0 ++ ++#define REG_DMC 0x05F0 //Dual MAC Co-Existence Register ++ ++ ++//----------------------------------------------------- ++// ++// 0x0600h ~ 0x07FFh WMAC Configuration ++// ++//----------------------------------------------------- ++#define REG_APSD_CTRL 0x0600 ++#define REG_BWOPMODE 0x0603 ++#define REG_TCR 0x0604 ++#define REG_RCR 0x0608 ++#define REG_RX_PKT_LIMIT 0x060C ++#define REG_RX_DLK_TIME 0x060D ++#define REG_RX_DRVINFO_SZ 0x060F ++ ++#define REG_MACID 0x0610 ++#define REG_BSSID 0x0618 ++#define REG_MAR 0x0620 ++#define REG_MBIDCAMCFG 0x0628 ++ ++#define REG_USTIME_EDCA 0x0638 ++#define REG_MAC_SPEC_SIFS 0x063A ++#define REG_RESP_SIFS_CCK 0x063C ++#define REG_RESP_SIFS_OFDM 0x063E ++#define REG_ACKTO 0x0640 ++#define REG_CTS2TO 0x0641 ++#define REG_EIFS 0x0642 ++ ++ ++//WMA, BA, CCX ++#define REG_NAV_CTRL 0x0650 ++#define REG_BACAMCMD 0x0654 ++#define REG_BACAMCONTENT 0x0658 ++#define REG_LBDLY 0x0660 ++#define REG_FWDLY 0x0661 ++#define REG_RXERR_RPT 0x0664 ++#define REG_WMAC_TRXPTCL_CTL 0x0668 ++ ++ ++// Security ++#define REG_CAMCMD 0x0670 ++#define REG_CAMWRITE 0x0674 ++#define REG_CAMREAD 0x0678 ++#define REG_CAMDBG 0x067C ++#define REG_SECCFG 0x0680 ++ ++// Power ++#define REG_WOW_CTRL 0x0690 ++#define REG_PSSTATUS 0x0691 ++#define REG_PS_RX_INFO 0x0692 ++#define REG_LPNAV_CTRL 0x0694 ++#define REG_WKFMCAM_CMD 0x0698 ++#define REG_WKFMCAM_RWD 0x069C ++#define REG_RXFLTMAP0 0x06A0 ++#define REG_RXFLTMAP1 0x06A2 ++#define REG_RXFLTMAP2 0x06A4 ++#define REG_BCN_PSR_RPT 0x06A8 ++#define REG_CALB32K_CTRL 0x06AC ++#define REG_PKT_MON_CTRL 0x06B4 ++#define REG_BT_COEX_TABLE 0x06C0 ++#define REG_WMAC_RESP_TXINFO 0x06D8 ++ ++#define REG_MACID1 0x0700 ++#define REG_BSSID1 0x0708 ++ ++//----------------------------------------------------- ++// ++// 0xFE00h ~ 0xFE55h USB Configuration ++// ++//----------------------------------------------------- ++#define REG_USB_INFO 0xFE17 ++#define REG_USB_SPECIAL_OPTION 0xFE55 ++#define REG_USB_DMA_AGG_TO 0xFE5B ++#define REG_USB_AGG_TO 0xFE5C ++#define REG_USB_AGG_TH 0xFE5D ++ ++// for 92DU high_Queue low_Queue Normal_Queue select ++#define REG_USB_High_NORMAL_Queue_Select_MAC0 0xFE44 ++//#define REG_USB_LOW_Queue_Select_MAC0 0xFE45 ++#define REG_USB_High_NORMAL_Queue_Select_MAC1 0xFE47 ++//#define REG_USB_LOW_Queue_Select_MAC1 0xFE48 ++ ++// For test chip ++#define REG_TEST_USB_TXQS 0xFE48 ++#define REG_TEST_SIE_VID 0xFE60 // 0xFE60~0xFE61 ++#define REG_TEST_SIE_PID 0xFE62 // 0xFE62~0xFE63 ++#define REG_TEST_SIE_OPTIONAL 0xFE64 ++#define REG_TEST_SIE_CHIRP_K 0xFE65 ++#define REG_TEST_SIE_PHY 0xFE66 // 0xFE66~0xFE6B ++#define REG_TEST_SIE_MAC_ADDR 0xFE70 // 0xFE70~0xFE75 ++#define REG_TEST_SIE_STRING 0xFE80 // 0xFE80~0xFEB9 ++ ++ ++// For normal chip ++#define REG_NORMAL_SIE_VID 0xFE60 // 0xFE60~0xFE61 ++#define REG_NORMAL_SIE_PID 0xFE62 // 0xFE62~0xFE63 ++#define REG_NORMAL_SIE_OPTIONAL 0xFE64 ++#define REG_NORMAL_SIE_EP 0xFE65 // 0xFE65~0xFE67 ++#define REG_NORMAL_SIE_PHY 0xFE68 // 0xFE68~0xFE6B ++#define REG_NORMAL_SIE_MAC_ADDR 0xFE70 // 0xFE70~0xFE75 ++#define REG_NORMAL_SIE_STRING 0xFE80 // 0xFE80~0xFEDF ++ ++ ++//----------------------------------------------------- ++// ++// Redifine 8192C register definition for compatibility ++// ++//----------------------------------------------------- ++ ++// TODO: use these definition when using REG_xxx naming rule. ++// NOTE: DO NOT Remove these definition. Use later. ++ ++#define SYS_ISO_CTRL REG_SYS_ISO_CTRL // System Isolation Interface Control. ++#define SYS_FUNC_EN REG_SYS_FUNC_EN // System Function Enable. ++#define SYS_CLK REG_SYS_CLKR ++#define CR9346 REG_9346CR // 93C46/93C56 Command Register. ++#define EFUSE_CTRL REG_EFUSE_CTRL // E-Fuse Control. ++#define EFUSE_TEST REG_EFUSE_TEST // E-Fuse Test. ++#define MSR (REG_CR + 2) // Media Status register ++#define ISR REG_HISR ++#define TSFR REG_TSFTR // Timing Sync Function Timer Register. ++ ++#define MACIDR0 REG_MACID // MAC ID Register, Offset 0x0050-0x0053 ++#define MACIDR4 (REG_MACID + 4) // MAC ID Register, Offset 0x0054-0x0055 ++ ++#define PBP REG_PBP ++ ++// Redifine MACID register, to compatible prior ICs. ++#define IDR0 MACIDR0 ++#define IDR4 MACIDR4 ++ ++ ++// ++// 9. Security Control Registers (Offset: ) ++// ++#define RWCAM REG_CAMCMD //IN 8190 Data Sheet is called CAMcmd ++#define WCAMI REG_CAMWRITE // Software write CAM input content ++#define RCAMO REG_CAMREAD // Software read/write CAM config ++#define CAMDBG REG_CAMDBG ++#define SECR REG_SECCFG //Security Configuration Register ++ ++// Unused register ++#define UnusedRegister 0x1BF ++#define DCAM UnusedRegister ++#define PSR UnusedRegister ++#define BBAddr UnusedRegister ++#define PhyDataR UnusedRegister ++ ++#define InvalidBBRFValue 0x12345678 ++ ++// Min Spacing related settings. ++#define MAX_MSS_DENSITY_2T 0x13 ++#define MAX_MSS_DENSITY_1T 0x0A ++ ++//---------------------------------------------------------------------------- ++// 8192C Cmd9346CR bits (Offset 0xA, 16bit) ++//---------------------------------------------------------------------------- ++#define CmdEEPROM_En BIT5 // EEPROM enable when set 1 ++#define CmdEERPOMSEL BIT4 // System EEPROM select, 0: boot from E-FUSE, 1: The EEPROM used is 9346 ++#define Cmd9346CR_9356SEL BIT4 ++#define AutoLoadEEPROM (CmdEEPROM_En|CmdEERPOMSEL) ++#define AutoLoadEFUSE CmdEEPROM_En ++ ++// 8192C GPIO MUX Configuration Register (offset 0x40, 4 byte) ++//---------------------------------------------------------------------------- ++#define GPIOSEL_GPIO 0 ++#define GPIOSEL_ENBT BIT5 ++ ++//---------------------------------------------------------------------------- ++// 8192C GPIO PIN Control Register (offset 0x44, 4 byte) ++//---------------------------------------------------------------------------- ++#define GPIO_IN REG_GPIO_PIN_CTRL // GPIO pins input value ++#define GPIO_OUT (REG_GPIO_PIN_CTRL+1) // GPIO pins output value ++#define GPIO_IO_SEL (REG_GPIO_PIN_CTRL+2) // GPIO pins output enable when a bit is set to "1"; otherwise, input is configured. ++#define GPIO_MOD (REG_GPIO_PIN_CTRL+3) ++ ++ ++//---------------------------------------------------------------------------- ++// 8192C (MSR) Media Status Register (Offset 0x4C, 8 bits) ++//---------------------------------------------------------------------------- ++/* ++Network Type ++00: No link ++01: Link in ad hoc network ++10: Link in infrastructure network ++11: AP mode ++Default: 00b. ++*/ ++#define MSR_NOLINK 0x00 ++#define MSR_ADHOC 0x01 ++#define MSR_INFRA 0x02 ++#define MSR_AP 0x03 ++ ++// ++// 6. Adaptive Control Registers (Offset: 0x0160 - 0x01CF) ++// ++//---------------------------------------------------------------------------- ++// 8192C Response Rate Set Register (offset 0x181, 24bits) ++//---------------------------------------------------------------------------- ++#define RRSR_RSC_OFFSET 21 ++#define RRSR_SHORT_OFFSET 23 ++#define RRSR_RSC_BW_40M 0x600000 ++#define RRSR_RSC_UPSUBCHNL 0x400000 ++#define RRSR_RSC_LOWSUBCHNL 0x200000 ++#define RRSR_SHORT 0x800000 ++#define RRSR_1M BIT0 ++#define RRSR_2M BIT1 ++#define RRSR_5_5M BIT2 ++#define RRSR_11M BIT3 ++#define RRSR_6M BIT4 ++#define RRSR_9M BIT5 ++#define RRSR_12M BIT6 ++#define RRSR_18M BIT7 ++#define RRSR_24M BIT8 ++#define RRSR_36M BIT9 ++#define RRSR_48M BIT10 ++#define RRSR_54M BIT11 ++#define RRSR_MCS0 BIT12 ++#define RRSR_MCS1 BIT13 ++#define RRSR_MCS2 BIT14 ++#define RRSR_MCS3 BIT15 ++#define RRSR_MCS4 BIT16 ++#define RRSR_MCS5 BIT17 ++#define RRSR_MCS6 BIT18 ++#define RRSR_MCS7 BIT19 ++#define BRSR_AckShortPmb BIT23 ++// CCK ACK: use Short Preamble or not ++ ++ ++//---------------------------------------------------------------------------- ++// 8192C Rate Definition ++//---------------------------------------------------------------------------- ++//CCK ++#define RATR_1M 0x00000001 ++#define RATR_2M 0x00000002 ++#define RATR_55M 0x00000004 ++#define RATR_11M 0x00000008 ++//OFDM ++#define RATR_6M 0x00000010 ++#define RATR_9M 0x00000020 ++#define RATR_12M 0x00000040 ++#define RATR_18M 0x00000080 ++#define RATR_24M 0x00000100 ++#define RATR_36M 0x00000200 ++#define RATR_48M 0x00000400 ++#define RATR_54M 0x00000800 ++//MCS 1 Spatial Stream ++#define RATR_MCS0 0x00001000 ++#define RATR_MCS1 0x00002000 ++#define RATR_MCS2 0x00004000 ++#define RATR_MCS3 0x00008000 ++#define RATR_MCS4 0x00010000 ++#define RATR_MCS5 0x00020000 ++#define RATR_MCS6 0x00040000 ++#define RATR_MCS7 0x00080000 ++//MCS 2 Spatial Stream ++#define RATR_MCS8 0x00100000 ++#define RATR_MCS9 0x00200000 ++#define RATR_MCS10 0x00400000 ++#define RATR_MCS11 0x00800000 ++#define RATR_MCS12 0x01000000 ++#define RATR_MCS13 0x02000000 ++#define RATR_MCS14 0x04000000 ++#define RATR_MCS15 0x08000000 ++ ++ ++// NOTE: For 92CU - Ziv ++//CCK ++#define RATE_1M BIT(0) ++#define RATE_2M BIT(1) ++#define RATE_5_5M BIT(2) ++#define RATE_11M BIT(3) ++//OFDM ++#define RATE_6M BIT(4) ++#define RATE_9M BIT(5) ++#define RATE_12M BIT(6) ++#define RATE_18M BIT(7) ++#define RATE_24M BIT(8) ++#define RATE_36M BIT(9) ++#define RATE_48M BIT(10) ++#define RATE_54M BIT(11) ++//MCS 1 Spatial Stream ++#define RATE_MCS0 BIT(12) ++#define RATE_MCS1 BIT(13) ++#define RATE_MCS2 BIT(14) ++#define RATE_MCS3 BIT(15) ++#define RATE_MCS4 BIT(16) ++#define RATE_MCS5 BIT(17) ++#define RATE_MCS6 BIT(18) ++#define RATE_MCS7 BIT(19) ++//MCS 2 Spatial Stream ++#define RATE_MCS8 BIT(20) ++#define RATE_MCS9 BIT(21) ++#define RATE_MCS10 BIT(22) ++#define RATE_MCS11 BIT(23) ++#define RATE_MCS12 BIT(24) ++#define RATE_MCS13 BIT(25) ++#define RATE_MCS14 BIT(26) ++#define RATE_MCS15 BIT(27) ++ ++ ++ ++ ++// ALL CCK Rate ++#define RATE_ALL_CCK RATR_1M|RATR_2M|RATR_55M|RATR_11M ++#define RATE_ALL_OFDM_AG RATR_6M|RATR_9M|RATR_12M|RATR_18M|RATR_24M|\ ++ RATR_36M|RATR_48M|RATR_54M ++#define RATE_ALL_OFDM_1SS RATR_MCS0|RATR_MCS1|RATR_MCS2|RATR_MCS3 |\ ++ RATR_MCS4|RATR_MCS5|RATR_MCS6|RATR_MCS7 ++#define RATE_ALL_OFDM_2SS RATR_MCS8|RATR_MCS9|RATR_MCS10|RATR_MCS11|\ ++ RATR_MCS12|RATR_MCS13|RATR_MCS14|RATR_MCS15 ++ ++//---------------------------------------------------------------------------- ++// 8192C BW_OPMODE bits (Offset 0x203, 8bit) ++//---------------------------------------------------------------------------- ++#define BW_OPMODE_20MHZ BIT2 ++#define BW_OPMODE_5G BIT1 ++#define BW_OPMODE_11J BIT0 ++ ++ ++//---------------------------------------------------------------------------- ++// 8192C CAM Config Setting (offset 0x250, 1 byte) ++//---------------------------------------------------------------------------- ++#define CAM_VALID BIT15 ++#define CAM_NOTVALID 0x0000 ++#define CAM_USEDK BIT5 ++ ++#define CAM_CONTENT_COUNT 8 ++ ++#define CAM_NONE 0x0 ++#define CAM_WEP40 0x01 ++#define CAM_TKIP 0x02 ++#define CAM_AES 0x04 ++#define CAM_WEP104 0x05 ++#define CAM_SMS4 0x6 ++ ++ ++#define TOTAL_CAM_ENTRY 32 ++#define HALF_CAM_ENTRY 16 ++ ++#define CAM_CONFIG_USEDK _TRUE ++#define CAM_CONFIG_NO_USEDK _FALSE ++ ++#define CAM_WRITE BIT16 ++#define CAM_READ 0x00000000 ++#define CAM_POLLINIG BIT31 ++ ++#define SCR_UseDK 0x01 ++#define SCR_TxSecEnable 0x02 ++#define SCR_RxSecEnable 0x04 ++ ++ ++// ++// 12. Host Interrupt Status Registers (Offset: 0x0300 - 0x030F) ++// ++//---------------------------------------------------------------------------- ++// 8190 IMR/ISR bits (offset 0xfd, 8bits) ++//---------------------------------------------------------------------------- ++#define IMR8190_DISABLED 0x0 ++// IMR DW0 Bit 0-31 ++#define IMR_BCNDMAINT6 BIT31 // Beacon DMA Interrupt 6 ++#define IMR_BCNDMAINT5 BIT30 // Beacon DMA Interrupt 5 ++#define IMR_BCNDMAINT4 BIT29 // Beacon DMA Interrupt 4 ++#define IMR_BCNDMAINT3 BIT28 // Beacon DMA Interrupt 3 ++#define IMR_BCNDMAINT2 BIT27 // Beacon DMA Interrupt 2 ++#define IMR_BCNDMAINT1 BIT26 // Beacon DMA Interrupt 1 ++#define IMR_BCNDOK8 BIT25 // Beacon Queue DMA OK Interrup 8 ++#define IMR_BCNDOK7 BIT24 // Beacon Queue DMA OK Interrup 7 ++#define IMR_BCNDOK6 BIT23 // Beacon Queue DMA OK Interrup 6 ++#define IMR_BCNDOK5 BIT22 // Beacon Queue DMA OK Interrup 5 ++#define IMR_BCNDOK4 BIT21 // Beacon Queue DMA OK Interrup 4 ++#define IMR_BCNDOK3 BIT20 // Beacon Queue DMA OK Interrup 3 ++#define IMR_BCNDOK2 BIT19 // Beacon Queue DMA OK Interrup 2 ++#define IMR_BCNDOK1 BIT18 // Beacon Queue DMA OK Interrup 1 ++#define IMR_TIMEOUT2 BIT17 // Timeout interrupt 2 ++#define IMR_TIMEOUT1 BIT16 // Timeout interrupt 1 ++#define IMR_TXFOVW BIT15 // Transmit FIFO Overflow ++#define IMR_PSTIMEOUT BIT14 // Power save time out interrupt ++#define IMR_BcnInt BIT13 // Beacon DMA Interrupt 0 ++#define IMR_RXFOVW BIT12 // Receive FIFO Overflow ++#define IMR_RDU BIT11 // Receive Descriptor Unavailable ++#define IMR_ATIMEND BIT10 // For 92C,ATIM Window End Interrupt ++#define IMR_BDOK BIT9 // Beacon Queue DMA OK Interrup ++#define IMR_HIGHDOK BIT8 // High Queue DMA OK Interrupt ++#define IMR_TBDOK BIT7 // Transmit Beacon OK interrup ++#define IMR_MGNTDOK BIT6 // Management Queue DMA OK Interrupt ++#define IMR_TBDER BIT5 // For 92C,Transmit Beacon Error Interrupt ++#define IMR_BKDOK BIT4 // AC_BK DMA OK Interrupt ++#define IMR_BEDOK BIT3 // AC_BE DMA OK Interrupt ++#define IMR_VIDOK BIT2 // AC_VI DMA OK Interrupt ++#define IMR_VODOK BIT1 // AC_VO DMA Interrupt ++#define IMR_ROK BIT0 // Receive DMA OK Interrupt ++ ++// 13. Host Interrupt Status Extension Register (Offset: 0x012C-012Eh) ++#define IMR_TXERR BIT11 ++#define IMR_RXERR BIT10 ++#define IMR_C2HCMD BIT9 ++#define IMR_CPWM BIT8 ++//RSVD [2-7] ++#define IMR_OCPINT BIT1 ++#define IMR_WLANOFF BIT0 ++ ++ ++ ++//---------------------------------------------------------------------------- ++// 8192D EFUSE ++//---------------------------------------------------------------------------- ++#define HWSET_MAX_SIZE 256 ++ ++//---------------------------------------------------------------------------- ++// 8192C EEPROM/EFUSE share register definition. ++//---------------------------------------------------------------------------- ++ ++// ++// Default Value for EEPROM or EFUSE!!! ++// ++#define EEPROM_Default_TSSI 0x0 ++#define EEPROM_Default_TxPowerDiff 0x0 ++#define EEPROM_Default_CrystalCap 0x0 //92D default 0x0 ++#define EEPROM_Default_BoardType 0x02 // Default: 2X2, RTL8192CE(QFPN68) ++#define EEPROM_Default_TxPower 0x1010 ++#define EEPROM_Default_HT2T_TxPwr 0x10 ++ ++#define EEPROM_Default_LegacyHTTxPowerDiff 0x4 ++#define EEPROM_Default_ThermalMeter 0x12 ++ ++#define EEPROM_Default_AntTxPowerDiff 0x0 ++//#define EEPROM_Default_TxPwDiff_CrystalCap 0x5 ++#define EEPROM_Default_TxPowerLevel_2G 0x2C ++#define EEPROM_Default_TxPowerLevel_5G 0x22 ++ ++#define EEPROM_Default_HT40_2SDiff 0x0 ++#define EEPROM_Default_HT20_Diff 2 // HT20<->40 default Tx Power Index Difference ++#define EEPROM_Default_LegacyHTTxPowerDiff 0x4 //OFDM Tx Power index diff ++#define EEPROM_Default_HT40_PwrMaxOffset 0 ++#define EEPROM_Default_HT20_PwrMaxOffset 0 ++ ++// For debug ++#define EEPROM_Default_PID 0x1234 ++#define EEPROM_Default_VID 0x5678 ++#define EEPROM_Default_CustomerID 0xAB ++#define EEPROM_Default_SubCustomerID 0xCD ++#define EEPROM_Default_Version 0 ++ ++#define EEPROM_Default_externalPA_C9 0x00 ++#define EEPROM_Default_externalPA_CC 0xFF ++#define EEPROM_Default_internalPA_SP3T_C9 0xAA ++#define EEPROM_Default_internalPA_SP3T_CC 0xAF ++#define EEPROM_Default_internalPA_SPDT_C9 0xAA ++#ifdef CONFIG_PCI_HCI ++#define EEPROM_Default_internalPA_SPDT_CC 0xA0 ++#else ++#define EEPROM_Default_internalPA_SPDT_CC 0xFA ++#endif ++ ++#define EEPROM_CHANNEL_PLAN_FCC 0x0 ++#define EEPROM_CHANNEL_PLAN_IC 0x1 ++#define EEPROM_CHANNEL_PLAN_ETSI 0x2 ++#define EEPROM_CHANNEL_PLAN_SPAIN 0x3 ++#define EEPROM_CHANNEL_PLAN_FRANCE 0x4 ++#define EEPROM_CHANNEL_PLAN_MKK 0x5 ++#define EEPROM_CHANNEL_PLAN_MKK1 0x6 ++#define EEPROM_CHANNEL_PLAN_ISRAEL 0x7 ++#define EEPROM_CHANNEL_PLAN_TELEC 0x8 ++#define EEPROM_CHANNEL_PLAN_GLOBAL_DOMAIN 0x9 ++#define EEPROM_CHANNEL_PLAN_WORLD_WIDE_13 0xA ++#define EEPROM_CHANNEL_PLAN_NCC 0xB ++#define EEPROM_CHANNEL_PLAN_BY_HW_MASK 0x80 ++ ++ ++#define EEPROM_CID_DEFAULT 0x0 ++#define EEPROM_CID_TOSHIBA 0x4 ++#define EEPROM_CID_CCX 0x10 // CCX test. By Bruce, 2009-02-25. ++#define EEPROM_CID_QMI 0x0D ++#define EEPROM_CID_WHQL 0xFE // added by chiyoko for dtm, 20090108 ++ ++ ++#define RTL8192_EEPROM_ID 0x8129 ++#define EEPROM_WAPI_SUPPORT 0x78 ++ ++ ++#ifdef CONFIG_PCI_HCI ++#define RT_IBSS_INT_MASKS (IMR_BcnInt | IMR_TBDOK | IMR_TBDER) ++#define RT_AC_INT_MASKS (IMR_VIDOK | IMR_VODOK | IMR_BEDOK|IMR_BKDOK) ++#define RT_BSS_INT_MASKS (RT_IBSS_INT_MASKS) ++ ++#define RTL8190_EEPROM_ID 0x8129 // 0-1 ++#define EEPROM_HPON 0x02 // LDO settings.2-5 ++#define EEPROM_CLK 0x06 // Clock settings.6-7 ++#define EEPROM_MAC_FUNCTION 0x08 // SE Test mode.8 ++ ++#define EEPROM_VID 0x28 // SE Vendor ID.A-B ++#define EEPROM_DID 0x2A // SE Device ID. C-D ++#define EEPROM_SVID 0x2C // SE Vendor ID.E-F ++#define EEPROM_SMID 0x2E // SE PCI Subsystem ID. 10-11 ++ ++#define EEPROM_MAC_ADDR 0x16 // SEMAC Address. 12-17 ++#define EEPROM_MAC_ADDR_MAC0_92D 0x55 ++#define EEPROM_MAC_ADDR_MAC1_92D 0x5B ++//---------------------------------------------------------------- ++// 2.4G band Tx power index setting ++#define EEPROM_CCK_TX_PWR_INX_2G 0x61 ++#define EEPROM_HT40_1S_TX_PWR_INX_2G 0x67 ++#define EEPROM_HT40_2S_TX_PWR_INX_DIFF_2G 0x6D ++#define EEPROM_HT20_TX_PWR_INX_DIFF_2G 0x70 ++#define EEPROM_OFDM_TX_PWR_INX_DIFF_2G 0x73 ++#define EEPROM_HT40_MAX_PWR_OFFSET_2G 0x76 ++#define EEPROM_HT20_MAX_PWR_OFFSET_2G 0x79 ++ ++//5GL channel 32-64 ++#define EEPROM_HT40_1S_TX_PWR_INX_5GL 0x7C ++#define EEPROM_HT40_2S_TX_PWR_INX_DIFF_5GL 0x82 ++#define EEPROM_HT20_TX_PWR_INX_DIFF_5GL 0x85 ++#define EEPROM_OFDM_TX_PWR_INX_DIFF_5GL 0x88 ++#define EEPROM_HT40_MAX_PWR_OFFSET_5GL 0x8B ++#define EEPROM_HT20_MAX_PWR_OFFSET_5GL 0x8E ++ ++//5GM channel 100-140 ++#define EEPROM_HT40_1S_TX_PWR_INX_5GM 0x91 ++#define EEPROM_HT40_2S_TX_PWR_INX_DIFF_5GM 0x97 ++#define EEPROM_HT20_TX_PWR_INX_DIFF_5GM 0x9A ++#define EEPROM_OFDM_TX_PWR_INX_DIFF_5GM 0x9D ++#define EEPROM_HT40_MAX_PWR_OFFSET_5GM 0xA0 ++#define EEPROM_HT20_MAX_PWR_OFFSET_5GM 0xA3 ++ ++//5GH channel 149-165 ++#define EEPROM_HT40_1S_TX_PWR_INX_5GH 0xA6 ++#define EEPROM_HT40_2S_TX_PWR_INX_DIFF_5GH 0xAC ++#define EEPROM_HT20_TX_PWR_INX_DIFF_5GH 0xAF ++#define EEPROM_OFDM_TX_PWR_INX_DIFF_5GH 0xB2 ++#define EEPROM_HT40_MAX_PWR_OFFSET_5GH 0xB5 ++#define EEPROM_HT20_MAX_PWR_OFFSET_5GH 0xB8 ++ ++#define EEPROM_CHANNEL_PLAN 0xBB // Map of supported channels. ++#define EEPROM_IQK_DELTA 0xBC ++#define EEPROM_LCK_DELTA 0xBC ++#define EEPROM_XTAL_K 0xBD //[7:5] ++#define EEPROM_TSSI_A_5G 0xBE ++#define EEPROM_TSSI_B_5G 0xBF ++#define EEPROM_TSSI_AB_5G 0xC0 ++#define EEPROM_THERMAL_METER 0xC3 //[4:0] ++#define EEPROM_PATHDIV 0xC4 ++#define EEPROM_RF_OPT1 0xC4 ++#define EEPROM_RF_OPT2 0xC5 ++#define EEPROM_RF_OPT3 0xC6 ++#define EEPROM_RF_OPT4 0xC7 ++#define EEPROM_RF_OPT5 0xC8 ++#define EEPROM_RF_OPT6 0xC9 ++#define EEPROM_VERSION 0xCA ++#define EEPROM_CUSTOMER_ID 0xCB ++#define EEPROM_RF_OPT7 0xCC ++ ++#define EEPROM_WIDIPAIRING_ADDR 0xF0 ++#define EEPROM_WIDIPAIRING_KEY 0xF6 ++ ++#define EEPROM_DEF_PART_NO 0x3FD //Byte ++#define EEPROME_CHIP_VERSION_L 0x3FF ++#define EEPROME_CHIP_VERSION_H 0x3FE ++#endif ++ ++#ifdef CONFIG_USB_HCI ++#define RTL8190_EEPROM_ID 0x8129 // 0-1 ++#define EEPROM_HPON 0x02 // LDO settings.2-5 ++#define EEPROM_CLK 0x06 // Clock settings.6-7 ++#define EEPROM_MAC_FUNCTION 0x08 // SE Test mode.8 ++ ++#define EEPROM_VID 0xC // SE Vendor ID.A-B ++#define EEPROM_PID 0xE // SE Device ID. C-D ++#define EEPROM_ENDPOINT_SETTING 0x10 ++#define EEPROM_Option_Setting 0x11 ++#define EEPROM_CHIRP_K 0x12 // Changed ++#define EEPROM_USB_PHY 0x13 // Changed ++#define EEPROM_NORMAL_BoardType EEPROM_RF_OPT1 //[7:5] ++#define EEPROM_MAC_ADDR 0x16 // SEMAC Address. 12-17 ++#define EEPROM_STRING 0x1F ++#define EEPROM_SUBCUSTOMER_ID 0x59 ++ ++#define EEPROM_MAC_ADDR_MAC0_92D 0x19 ++#define EEPROM_MAC_ADDR_MAC1_92D 0x5B ++//---------------------------------------------------------------- ++// 2.4G band Tx power index setting ++#define EEPROM_CCK_TX_PWR_INX_2G 0x61 ++#define EEPROM_HT40_1S_TX_PWR_INX_2G 0x67 ++#define EEPROM_HT40_2S_TX_PWR_INX_DIFF_2G 0x6D ++#define EEPROM_HT20_TX_PWR_INX_DIFF_2G 0x70 ++#define EEPROM_OFDM_TX_PWR_INX_DIFF_2G 0x73 ++#define EEPROM_HT40_MAX_PWR_OFFSET_2G 0x76 ++#define EEPROM_HT20_MAX_PWR_OFFSET_2G 0x79 ++ ++//5GL channel 32-64 ++#define EEPROM_HT40_1S_TX_PWR_INX_5GL 0x7C ++#define EEPROM_HT40_2S_TX_PWR_INX_DIFF_5GL 0x82 ++#define EEPROM_HT20_TX_PWR_INX_DIFF_5GL 0x85 ++#define EEPROM_OFDM_TX_PWR_INX_DIFF_5GL 0x88 ++#define EEPROM_HT40_MAX_PWR_OFFSET_5GL 0x8B ++#define EEPROM_HT20_MAX_PWR_OFFSET_5GL 0x8E ++ ++//5GM channel 100-140 ++#define EEPROM_HT40_1S_TX_PWR_INX_5GM 0x91 ++#define EEPROM_HT40_2S_TX_PWR_INX_DIFF_5GM 0x97 ++#define EEPROM_HT20_TX_PWR_INX_DIFF_5GM 0x9A ++#define EEPROM_OFDM_TX_PWR_INX_DIFF_5GM 0x9D ++#define EEPROM_HT40_MAX_PWR_OFFSET_5GM 0xA0 ++#define EEPROM_HT20_MAX_PWR_OFFSET_5GM 0xA3 ++ ++//5GH channel 149-165 ++#define EEPROM_HT40_1S_TX_PWR_INX_5GH 0xA6 ++#define EEPROM_HT40_2S_TX_PWR_INX_DIFF_5GH 0xAC ++#define EEPROM_HT20_TX_PWR_INX_DIFF_5GH 0xAF ++#define EEPROM_OFDM_TX_PWR_INX_DIFF_5GH 0xB2 ++#define EEPROM_HT40_MAX_PWR_OFFSET_5GH 0xB5 ++#define EEPROM_HT20_MAX_PWR_OFFSET_5GH 0xB8 ++ ++#define EEPROM_CHANNEL_PLAN 0xBB // Map of supported channels. ++#define EEPROM_TEST_CHANNEL_PLAN 0xBB ++#define EEPROM_IQK_DELTA 0xBC ++#define EEPROM_LCK_DELTA 0xBC ++#define EEPROM_XTAL_K 0xBD //[7:5] ++#define EEPROM_TSSI_A_5G 0xBE ++#define EEPROM_TSSI_B_5G 0xBF ++#define EEPROM_TSSI_AB_5G 0xC0 ++#define EEPROM_THERMAL_METER 0xC3 //[4:0] ++#define EEPROM_RF_OPT1 0xC4 ++#define EEPROM_RF_OPT2 0xC5 ++#define EEPROM_RF_OPT3 0xC6 ++#define EEPROM_RF_OPT4 0xC7 ++#define EEPROM_RF_OPT5 0xC8 ++#define EEPROM_RF_OPT6 0xC9 ++#define EEPROM_VERSION 0xCA ++#define EEPROM_CUSTOMER_ID 0xCB ++#define EEPROM_RF_OPT7 0xCC ++ ++#define EEPROM_DEF_PART_NO 0x3FD //Byte ++#define EEPROME_CHIP_VERSION_L 0x3FF ++#define EEPROME_CHIP_VERSION_H 0x3FE ++ ++//------------------------------------------------------------- ++// EEPROM content definitions ++//------------------------------------------------------------- ++#define OS_LINK_SPEED_NORMAL_MASK BIT3 | BIT2 ++#define OS_LINK_SPEED_TEST_MASK BIT3 | BIT4 ++ ++#define BOARD_TYPE_NORMAL_MASK 0xE0 ++#define BOARD_TYPE_TEST_MASK 0xF ++ ++#define BT_COEXISTENCE_TEST BIT4 ++#define BT_COEXISTENCE_NORMAL BIT5 ++ ++#define BT_CO_SHIFT_TEST 4 ++#define BT_CO_SHIFT_NORMAL 5 ++ ++#define EP_NUMBER_MASK_TEST 0x30 //bit 4:5 0Eh ++#define EP_NUMBER_SHIFT_TEST 4 ++ ++#define USB_PHY_PARA_SIZE_TEST 6 ++#define USB_PHY_PARA_SIZE_NORMAL 4 ++ ++//------------------------------------------------------------- ++// EEPROM default value definitions ++//------------------------------------------------------------- ++// Use 0xABCD instead of 0x8192 for debug ++#define EEPROM_DEF_ID_0 0xCD // Byte 0x00 ++#define EEPROM_DEF_ID_1 0xAB // Byte 0x01 ++ ++#define EEPROM_DEF_RTK_RSV_A3 0x74 // Byte 0x03 ++#define EEPROM_DEF_RTK_RSV_A4 0x6D // Byte 0x04 ++#define EEPROM_DEF_RTK_RSV_A8 0xFF // Byte 0x08 ++ ++#define EEPROM_DEF_VID_0 0x0A // Byte 0x0A ++#define EEPROM_DEF_VID_1 0x0B ++ ++#define EEPROM_DEF_PID_0 0x92 // Byte 0x0C ++#define EEPROM_DEF_PID_1 0x81 ++ ++ ++#define EEPROM_TEST_DEF_USB_OPT 0x80 // Byte 0x0E ++#define EEPROM_NORMAL_DEF_USB_OPT 0x00 // Byte 0x0E ++ ++#define EEPROM_DEF_CHIRPK 0x15 // Byte 0x0F ++ ++#define EEPROM_DEF_USB_PHY_0 0x85 // Byte 0x10 ++#define EEPROM_DEF_USB_PHY_1 0x62 // Byte 0x11 ++#define EEPROM_DEF_USB_PHY_2 0x9E // Byte 0x12 ++#define EEPROM_DEF_USB_PHY_3 0x06 // Byte 0x13 ++ ++#define EEPROM_DEF_TSSI_A 0x09 // Byte 0x78 ++#define EEPROM_DEF_TSSI_B 0x09 // Byte 0x79 ++ ++ ++#define EEPROM_DEF_THERMAL_METER 0x12 // Byte 0x7A ++ ++ ++#define EEPROM_USB_SN BIT(0) ++#define EEPROM_USB_REMOTE_WAKEUP BIT(1) ++#define EEPROM_USB_DEVICE_PWR BIT(2) ++#define EEPROM_EP_NUMBER (BIT(3)|BIT(4)) ++ ++#if 0 ++#define EEPROM_CHANNEL_PLAN_FCC 0x0 ++#define EEPROM_CHANNEL_PLAN_IC 0x1 ++#define EEPROM_CHANNEL_PLAN_ETSI 0x2 ++#define EEPROM_CHANNEL_PLAN_SPAIN 0x3 ++#define EEPROM_CHANNEL_PLAN_FRANCE 0x4 ++#define EEPROM_CHANNEL_PLAN_MKK 0x5 ++#define EEPROM_CHANNEL_PLAN_MKK1 0x6 ++#define EEPROM_CHANNEL_PLAN_ISRAEL 0x7 ++#define EEPROM_CHANNEL_PLAN_TELEC 0x8 ++#define EEPROM_CHANNEL_PLAN_GLOBAL_DOMAIN 0x9 ++#define EEPROM_CHANNEL_PLAN_WORLD_WIDE_13 0xA ++#define EEPROM_CHANNEL_PLAN_BY_HW_MASK 0x80 ++ ++#define EEPROM_CID_DEFAULT 0x0 ++ ++#define EEPROM_CID_WHQL 0xFE // added by chiyoko for dtm, 20090108 ++ ++ ++#define EEPROM_CID_CCX 0x10 // CCX test. By Bruce, 2009-02-25. ++ ++#endif ++#endif ++ ++ ++/*=================================================================== ++===================================================================== ++Here the register defines are for 92C. When the define is as same with 92C, ++we will use the 92C's define for the consistency ++So the following defines for 92C is not entire!!!!!! ++===================================================================== ++=====================================================================*/ ++/* ++Based on Datasheet V33---090401 ++Register Summary ++Current IOREG MAP ++0x0000h ~ 0x00FFh System Configuration (256 Bytes) ++0x0100h ~ 0x01FFh MACTOP General Configuration (256 Bytes) ++0x0200h ~ 0x027Fh TXDMA Configuration (128 Bytes) ++0x0280h ~ 0x02FFh RXDMA Configuration (128 Bytes) ++0x0300h ~ 0x03FFh PCIE EMAC Reserved Region (256 Bytes) ++0x0400h ~ 0x04FFh Protocol Configuration (256 Bytes) ++0x0500h ~ 0x05FFh EDCA Configuration (256 Bytes) ++0x0600h ~ 0x07FFh WMAC Configuration (512 Bytes) ++0x2000h ~ 0x3FFFh 8051 FW Download Region (8196 Bytes) ++*/ ++ ++//---------------------------------------------------------------------------- ++// 8192C (RCR) Receive Configuration Register (Offset 0x608, 32 bits) ++//---------------------------------------------------------------------------- ++#define RCR_APPFCS BIT31 //WMAC append FCS after pauload ++#define RCR_APP_MIC BIT30 // ++#define RCR_APP_ICV BIT29 // ++#define RCR_APP_PHYST_RXFF BIT28 // ++#define RCR_APP_BA_SSN BIT27 //Accept BA SSN ++#define RCR_ENMBID BIT24 //Enable Multiple BssId. ++#define RCR_LSIGEN BIT23 ++#define RCR_MFBEN BIT22 ++#define RCR_HTC_LOC_CTRL BIT14 //MFC<--HTC=1 MFC-->HTC=0 ++#define RCR_AMF BIT13 //Accept management type frame ++#define RCR_ACF BIT12 //Accept control type frame ++#define RCR_ADF BIT11 //Accept data type frame ++#define RCR_AICV BIT9 //Accept ICV error packet ++#define RCR_ACRC32 BIT8 //Accept CRC32 error packet ++#define RCR_CBSSID_BCN BIT7 //Accept BSSID match packet (Rx beacon, probe rsp) ++#define RCR_CBSSID_DATA BIT6 //Accept BSSID match packet (Data) ++#define RCR_CBSSID RCR_CBSSID_DATA //Accept BSSID match packet ++#define RCR_APWRMGT BIT5 //Accept power management packet ++#define RCR_ADD3 BIT4 //Accept address 3 match packet ++#define RCR_AB BIT3 //Accept broadcast packet ++#define RCR_AM BIT2 //Accept multicast packet ++#define RCR_APM BIT1 //Accept physical match packet ++#define RCR_AAP BIT0 //Accept all unicast packet ++#define RCR_MXDMA_OFFSET 8 ++#define RCR_FIFO_OFFSET 13 ++ ++ ++ ++//============================================================================ ++// 8192c USB specific Regsiter Offset and Content definition, ++// 2009.08.18, added by vivi. for merge 92c and 92C into one driver ++//============================================================================ ++//#define APS_FSMCO 0x0004 same with 92Ce ++#define RSV_CTRL 0x001C ++#define RD_CTRL 0x0524 ++ ++//----------------------------------------------------- ++// ++// 0xFE00h ~ 0xFE55h USB Configuration ++// ++//----------------------------------------------------- ++#define REG_USB_INFO 0xFE17 ++#define REG_USB_SPECIAL_OPTION 0xFE55 ++#define REG_USB_DMA_AGG_TO 0xFE5B ++#define REG_USB_AGG_TO 0xFE5C ++#define REG_USB_AGG_TH 0xFE5D ++ ++#define REG_USB_VID 0xFE60 ++#define REG_USB_PID 0xFE62 ++#define REG_USB_OPTIONAL 0xFE64 ++#define REG_USB_CHIRP_K 0xFE65 ++#define REG_USB_PHY 0xFE66 ++#define REG_USB_MAC_ADDR 0xFE70 ++ ++#define REG_USB_HRPWM 0xFE58 ++#define REG_USB_HCPWM 0xFE57 ++ ++#define InvalidBBRFValue 0x12345678 ++ ++//============================================================================ ++// 8192C Regsiter Bit and Content definition ++//============================================================================ ++//----------------------------------------------------- ++// ++// 0x0000h ~ 0x00FFh System Configuration ++// ++//----------------------------------------------------- ++ ++//2 SPS0_CTRL ++#define SW18_FPWM BIT(3) ++ ++ ++//2 SYS_ISO_CTRL ++#define ISO_MD2PP BIT(0) ++#define ISO_UA2USB BIT(1) ++#define ISO_UD2CORE BIT(2) ++#define ISO_PA2PCIE BIT(3) ++#define ISO_PD2CORE BIT(4) ++#define ISO_IP2MAC BIT(5) ++#define ISO_DIOP BIT(6) ++#define ISO_DIOE BIT(7) ++#define ISO_EB2CORE BIT(8) ++#define ISO_DIOR BIT(9) ++ ++#define PWC_EV25V BIT(14) ++#define PWC_EV12V BIT(15) ++ ++ ++//2 SYS_FUNC_EN ++#define FEN_BBRSTB BIT(0) ++#define FEN_BB_GLB_RSTn BIT(1) ++#define FEN_USBA BIT(2) ++#define FEN_UPLL BIT(3) ++#define FEN_USBD BIT(4) ++#define FEN_DIO_PCIE BIT(5) ++#define FEN_PCIEA BIT(6) ++#define FEN_PPLL BIT(7) ++#define FEN_PCIED BIT(8) ++#define FEN_DIOE BIT(9) ++#define FEN_CPUEN BIT(10) ++#define FEN_DCORE BIT(11) ++#define FEN_ELDR BIT(12) ++#define FEN_DIO_RF BIT(13) ++#define FEN_HWPDN BIT(14) ++#define FEN_MREGEN BIT(15) ++ ++//2 APS_FSMCO ++#define PFM_LDALL BIT(0) ++#define PFM_ALDN BIT(1) ++#define PFM_LDKP BIT(2) ++#define PFM_WOWL BIT(3) ++#define EnPDN BIT(4) ++#define PDN_PL BIT(5) ++#define APFM_ONMAC BIT(8) ++#define APFM_OFF BIT(9) ++#define APFM_RSM BIT(10) ++#define AFSM_HSUS BIT(11) ++#define AFSM_PCIE BIT(12) ++#define APDM_MAC BIT(13) ++#define APDM_HOST BIT(14) ++#define APDM_HPDN BIT(15) ++#define RDY_MACON BIT(16) ++#define SUS_HOST BIT(17) ++#define ROP_ALD BIT(20) ++#define ROP_PWR BIT(21) ++#define ROP_SPS BIT(22) ++#define SOP_MRST BIT(25) ++#define SOP_FUSE BIT(26) ++#define SOP_ABG BIT(27) ++#define SOP_AMB BIT(28) ++#define SOP_RCK BIT(29) ++#define SOP_A8M BIT(30) ++#define XOP_BTCK BIT(31) ++ ++//2 SYS_CLKR ++#define ANAD16V_EN BIT(0) ++#define ANA8M BIT(1) ++#define MACSLP BIT(4) ++#define LOADER_CLK_EN BIT(5) ++#define _80M_SSC_DIS BIT(7) ++#define _80M_SSC_EN_HO BIT(8) ++#define PHY_SSC_RSTB BIT(9) ++#define SEC_CLK_EN BIT(10) ++#define MAC_CLK_EN BIT(11) ++#define SYS_CLK_EN BIT(12) ++#define RING_CLK_EN BIT(13) ++ ++ ++//2 9346CR ++ ++#define BOOT_FROM_EEPROM BIT(4) ++#define EEPROM_EN BIT(5) ++ ++ ++//2 AFE_MISC ++#define AFE_BGEN BIT(0) ++#define AFE_MBEN BIT(1) ++#define MAC_ID_EN BIT(7) ++ ++ ++//2 SPS0_CTRL ++ ++ ++//2 SPS_OCP_CFG ++ ++ ++//2 RSV_CTRL ++#define WLOCK_ALL BIT(0) ++#define WLOCK_00 BIT(1) ++#define WLOCK_04 BIT(2) ++#define WLOCK_08 BIT(3) ++#define WLOCK_40 BIT(4) ++#define R_DIS_PRST_0 BIT(5) ++#define R_DIS_PRST_1 BIT(6) ++#define LOCK_ALL_EN BIT(7) ++ ++//2 RF_CTRL ++#define RF_EN BIT(0) ++#define RF_RSTB BIT(1) ++#define RF_SDMRSTB BIT(2) ++ ++ ++ ++//2 LDOA15_CTRL ++#define LDA15_EN BIT(0) ++#define LDA15_STBY BIT(1) ++#define LDA15_OBUF BIT(2) ++#define LDA15_REG_VOS BIT(3) ++#define _LDA15_VOADJ(x) (((x) & 0x7) << 4) ++ ++ ++ ++//2 LDOV12D_CTRL ++#define LDV12_EN BIT(0) ++#define LDV12_SDBY BIT(1) ++#define LPLDO_HSM BIT(2) ++#define LPLDO_LSM_DIS BIT(3) ++#define _LDV12_VADJ(x) (((x) & 0xF) << 4) ++ ++ ++//2 AFE_XTAL_CTRL ++#define XTAL_EN BIT(0) ++#define XTAL_BSEL BIT(1) ++#define _XTAL_BOSC(x) (((x) & 0x3) << 2) ++#define _XTAL_CADJ(x) (((x) & 0xF) << 4) ++#define XTAL_GATE_USB BIT(8) ++#define _XTAL_USB_DRV(x) (((x) & 0x3) << 9) ++#define XTAL_GATE_AFE BIT(11) ++#define _XTAL_AFE_DRV(x) (((x) & 0x3) << 12) ++#define XTAL_RF_GATE BIT(14) ++#define _XTAL_RF_DRV(x) (((x) & 0x3) << 15) ++#define XTAL_GATE_DIG BIT(17) ++#define _XTAL_DIG_DRV(x) (((x) & 0x3) << 18) ++#define XTAL_BT_GATE BIT(20) ++#define _XTAL_BT_DRV(x) (((x) & 0x3) << 21) ++#define _XTAL_GPIO(x) (((x) & 0x7) << 23) ++ ++ ++#define CKDLY_AFE BIT(26) ++#define CKDLY_USB BIT(27) ++#define CKDLY_DIG BIT(28) ++#define CKDLY_BT BIT(29) ++ ++ ++//2 AFE_PLL_CTRL ++#define APLL_EN BIT(0) ++#define APLL_320_EN BIT(1) ++#define APLL_FREF_SEL BIT(2) ++#define APLL_EDGE_SEL BIT(3) ++#define APLL_WDOGB BIT(4) ++#define APLL_LPFEN BIT(5) ++ ++#define APLL_REF_CLK_13MHZ 0x1 ++#define APLL_REF_CLK_19_2MHZ 0x2 ++#define APLL_REF_CLK_20MHZ 0x3 ++#define APLL_REF_CLK_25MHZ 0x4 ++#define APLL_REF_CLK_26MHZ 0x5 ++#define APLL_REF_CLK_38_4MHZ 0x6 ++#define APLL_REF_CLK_40MHZ 0x7 ++ ++#define APLL_320EN BIT(14) ++#define APLL_80EN BIT(15) ++#define APLL_1MEN BIT(24) ++ ++ ++//2 EFUSE_CTRL ++#define ALD_EN BIT(18) ++#define EF_PD BIT(19) ++#define EF_FLAG BIT(31) ++ ++//2 EFUSE_TEST ++#define EF_TRPT BIT(7) ++#define LDOE25_EN BIT(31) ++ ++//2 PWR_DATA ++ ++//2 CAL_TIMER ++ ++//2 ACLK_MON ++#define RSM_EN BIT(0) ++#define Timer_EN BIT(4) ++ ++ ++//2 GPIO_MUXCFG ++#define TRSW0EN BIT(2) ++#define TRSW1EN BIT(3) ++#define EROM_EN BIT(4) ++#define EnBT BIT(5) ++#define EnUart BIT(8) ++#define Uart_910 BIT(9) ++#define EnPMAC BIT(10) ++#define SIC_SWRST BIT(11) ++#define EnSIC BIT(12) ++#define SIC_23 BIT(13) ++#define EnHDP BIT(14) ++#define SIC_LBK BIT(15) ++ ++//2 GPIO_PIN_CTRL ++ ++ ++ ++//2 GPIO_INTM ++ ++//2 LEDCFG ++#define LED0PL BIT(4) ++#define LED1PL BIT(12) ++#define LED0DIS BIT(7) ++ ++#define SECCAM_CLR BIT(30) ++ ++//2 FSIMR ++ ++//2 FSISR ++ ++ ++//2 8051FWDL ++//2 MCUFWDL ++#define MCUFWDL_EN BIT(0) ++#define MCUFWDL_RDY BIT(1) ++#define FWDL_ChkSum_rpt BIT(2) ++#define MACINI_RDY BIT(3) ++#define BBINI_RDY BIT(4) ++#define RFINI_RDY BIT(5) ++#define WINTINI_RDY BIT(6) ++#define MAC1_WINTINI_RDY BIT(11)// 0X81 BIT3 ++#define CPRST BIT(23) ++ ++ ++ ++ ++//2 REG_SYS_CFG ++#define XCLK_VLD BIT(0) ++#define ACLK_VLD BIT(1) ++#define UCLK_VLD BIT(2) ++#define PCLK_VLD BIT(3) ++#define PCIRSTB BIT(4) ++#define V15_VLD BIT(5) ++#define TRP_B15V_EN BIT(7) ++#define SIC_IDLE BIT(8) ++#define BD_MAC2 BIT(9) ++#define BD_MAC1 BIT(10) ++#define IC_MACPHY_MODE BIT(11) ++#define PAD_HWPD_IDN BIT(22) ++#define TRP_VAUX_EN BIT(23) ++#define TRP_BT_EN BIT(24) ++#define BD_PKG_SEL BIT(25) ++#define BD_HCI_SEL BIT(26) ++#define TYPE_ID BIT(27) ++ ++#define CHIP_VER_RTL_MASK 0xF000 //Bit 12 ~ 15 ++#define CHIP_VER_RTL_SHIFT 12 ++ ++//----------------------------------------------------- ++// ++// 0x0100h ~ 0x01FFh MACTOP General Configuration ++// ++//----------------------------------------------------- ++ ++ ++//2 Function Enable Registers ++//2 CR ++ ++#define REG_LBMODE (REG_CR + 3) ++ ++ ++#define HCI_TXDMA_EN BIT(0) ++#define HCI_RXDMA_EN BIT(1) ++#define TXDMA_EN BIT(2) ++#define RXDMA_EN BIT(3) ++#define PROTOCOL_EN BIT(4) ++#define SCHEDULE_EN BIT(5) ++#define MACTXEN BIT(6) ++#define MACRXEN BIT(7) ++#define ENSWBCN BIT(8) ++#define ENSEC BIT(9) ++ ++// Network type ++#define _NETTYPE(x) (((x) & 0x3) << 16) ++#define MASK_NETTYPE 0x30000 ++#define NT_NO_LINK 0x0 ++#define NT_LINK_AD_HOC 0x1 ++#define NT_LINK_AP 0x2 ++#define NT_AS_AP 0x3 ++ ++#define _LBMODE(x) (((x) & 0xF) << 24) ++#define MASK_LBMODE 0xF000000 ++#define LOOPBACK_NORMAL 0x0 ++#define LOOPBACK_IMMEDIATELY 0xB ++#define LOOPBACK_MAC_DELAY 0x3 ++#define LOOPBACK_PHY 0x1 ++#define LOOPBACK_DMA 0x7 ++ ++ ++//2 PBP - Page Size Register ++#define GET_RX_PAGE_SIZE(value) ((value) & 0xF) ++#define GET_TX_PAGE_SIZE(value) (((value) & 0xF0) >> 4) ++#define _PSRX_MASK 0xF ++#define _PSTX_MASK 0xF0 ++#define _PSRX(x) (x) ++#define _PSTX(x) ((x) << 4) ++ ++#define PBP_64 0x0 ++#define PBP_128 0x1 ++#define PBP_256 0x2 ++#define PBP_512 0x3 ++#define PBP_1024 0x4 ++ ++ ++//2 TX/RXDMA ++#define RXDMA_ARBBW_EN BIT(0) ++#define RXSHFT_EN BIT(1) ++#define RXDMA_AGG_EN BIT(2) ++#define QS_VO_QUEUE BIT(8) ++#define QS_VI_QUEUE BIT(9) ++#define QS_BE_QUEUE BIT(10) ++#define QS_BK_QUEUE BIT(11) ++#define QS_MANAGER_QUEUE BIT(12) ++#define QS_HIGH_QUEUE BIT(13) ++ ++#define HQSEL_VOQ BIT(0) ++#define HQSEL_VIQ BIT(1) ++#define HQSEL_BEQ BIT(2) ++#define HQSEL_BKQ BIT(3) ++#define HQSEL_MGTQ BIT(4) ++#define HQSEL_HIQ BIT(5) ++ ++// For normal driver, 0x10C ++#define _TXDMA_HIQ_MAP(x) (((x)&0x3) << 14) ++#define _TXDMA_MGQ_MAP(x) (((x)&0x3) << 12) ++#define _TXDMA_BKQ_MAP(x) (((x)&0x3) << 10) ++#define _TXDMA_BEQ_MAP(x) (((x)&0x3) << 8 ) ++#define _TXDMA_VIQ_MAP(x) (((x)&0x3) << 6 ) ++#define _TXDMA_VOQ_MAP(x) (((x)&0x3) << 4 ) ++ ++#define QUEUE_LOW 1 ++#define QUEUE_NORMAL 2 ++#define QUEUE_HIGH 3 ++ ++ ++ ++//2 TRXFF_BNDY ++ ++ ++//2 LLT_INIT ++#define _LLT_NO_ACTIVE 0x0 ++#define _LLT_WRITE_ACCESS 0x1 ++#define _LLT_READ_ACCESS 0x2 ++ ++#define _LLT_INIT_DATA(x) ((x) & 0xFF) ++#define _LLT_INIT_ADDR(x) (((x) & 0xFF) << 8) ++#define _LLT_OP(x) (((x) & 0x3) << 30) ++#define _LLT_OP_VALUE(x) (((x) >> 30) & 0x3) ++ ++ ++//2 BB_ACCESS_CTRL ++#define BB_WRITE_READ_MASK (BIT(31) | BIT(30)) ++#define BB_WRITE_EN BIT(30) ++#define BB_READ_EN BIT(31) ++//#define BB_ADDR_MASK 0xFFF ++//#define _BB_ADDR(x) ((x) & BB_ADDR_MASK) ++ ++//----------------------------------------------------- ++// ++// 0x0200h ~ 0x027Fh TXDMA Configuration ++// ++//----------------------------------------------------- ++//2 RQPN ++#define _HPQ(x) ((x) & 0xFF) ++#define _LPQ(x) (((x) & 0xFF) << 8) ++#define _PUBQ(x) (((x) & 0xFF) << 16) ++#define _NPQ(x) ((x) & 0xFF) // NOTE: in RQPN_NPQ register ++ ++ ++#define HPQ_PUBLIC_DIS BIT(24) ++#define LPQ_PUBLIC_DIS BIT(25) ++#define LD_RQPN BIT(31) ++ ++ ++//2 TDECTRL ++#define BCN_VALID BIT(16) ++#define BCN_HEAD(x) (((x) & 0xFF) << 8) ++#define BCN_HEAD_MASK 0xFF00 ++ ++//2 TDECTL ++#define BLK_DESC_NUM_SHIFT 4 ++#define BLK_DESC_NUM_MASK 0xF ++ ++ ++//2 TXDMA_OFFSET_CHK ++#define DROP_DATA_EN BIT(9) ++ ++//----------------------------------------------------- ++// ++// 0x0400h ~ 0x047Fh Protocol Configuration ++// ++//----------------------------------------------------- ++//2 FWHW_TXQ_CTRL ++#define EN_AMPDU_RTY_NEW BIT(7) ++ ++//2 INIRTSMCS_SEL ++#define _INIRTSMCS_SEL(x) ((x) & 0x3F) ++ ++ ++//2 SPEC SIFS ++#define _SPEC_SIFS_CCK(x) ((x) & 0xFF) ++#define _SPEC_SIFS_OFDM(x) (((x) & 0xFF) << 8) ++ ++ ++//2 RRSR ++ ++#define RATE_REG_BITMAP_ALL 0xFFFFF ++ ++#define _RRSC_BITMAP(x) ((x) & 0xFFFFF) ++ ++#define _RRSR_RSC(x) (((x) & 0x3) << 21) ++#define RRSR_RSC_RESERVED 0x0 ++#define RRSR_RSC_UPPER_SUBCHANNEL 0x1 ++#define RRSR_RSC_LOWER_SUBCHANNEL 0x2 ++#define RRSR_RSC_DUPLICATE_MODE 0x3 ++ ++ ++//2 ARFR ++#define USE_SHORT_G1 BIT(20) ++ ++//2 AGGLEN_LMT_L ++#define _AGGLMT_MCS0(x) ((x) & 0xF) ++#define _AGGLMT_MCS1(x) (((x) & 0xF) << 4) ++#define _AGGLMT_MCS2(x) (((x) & 0xF) << 8) ++#define _AGGLMT_MCS3(x) (((x) & 0xF) << 12) ++#define _AGGLMT_MCS4(x) (((x) & 0xF) << 16) ++#define _AGGLMT_MCS5(x) (((x) & 0xF) << 20) ++#define _AGGLMT_MCS6(x) (((x) & 0xF) << 24) ++#define _AGGLMT_MCS7(x) (((x) & 0xF) << 28) ++ ++ ++//2 RL ++#define RETRY_LIMIT_SHORT_SHIFT 8 ++#define RETRY_LIMIT_LONG_SHIFT 0 ++ ++ ++//2 DARFRC ++#define _DARF_RC1(x) ((x) & 0x1F) ++#define _DARF_RC2(x) (((x) & 0x1F) << 8) ++#define _DARF_RC3(x) (((x) & 0x1F) << 16) ++#define _DARF_RC4(x) (((x) & 0x1F) << 24) ++// NOTE: shift starting from address (DARFRC + 4) ++#define _DARF_RC5(x) ((x) & 0x1F) ++#define _DARF_RC6(x) (((x) & 0x1F) << 8) ++#define _DARF_RC7(x) (((x) & 0x1F) << 16) ++#define _DARF_RC8(x) (((x) & 0x1F) << 24) ++ ++ ++//2 RARFRC ++#define _RARF_RC1(x) ((x) & 0x1F) ++#define _RARF_RC2(x) (((x) & 0x1F) << 8) ++#define _RARF_RC3(x) (((x) & 0x1F) << 16) ++#define _RARF_RC4(x) (((x) & 0x1F) << 24) ++// NOTE: shift starting from address (RARFRC + 4) ++#define _RARF_RC5(x) ((x) & 0x1F) ++#define _RARF_RC6(x) (((x) & 0x1F) << 8) ++#define _RARF_RC7(x) (((x) & 0x1F) << 16) ++#define _RARF_RC8(x) (((x) & 0x1F) << 24) ++ ++ ++ ++ ++//----------------------------------------------------- ++// ++// 0x0500h ~ 0x05FFh EDCA Configuration ++// ++//----------------------------------------------------- ++ ++ ++ ++//2 EDCA setting ++#define AC_PARAM_TXOP_LIMIT_OFFSET 16 ++#define AC_PARAM_ECW_MAX_OFFSET 12 ++#define AC_PARAM_ECW_MIN_OFFSET 8 ++#define AC_PARAM_AIFS_OFFSET 0 ++ ++ ++//2 EDCA_VO_PARAM ++#define _AIFS(x) (x) ++#define _ECW_MAX_MIN(x) ((x) << 8) ++#define _TXOP_LIMIT(x) ((x) << 16) ++ ++ ++#define _BCNIFS(x) ((x) & 0xFF) ++#define _BCNECW(x) (((x) & 0xF))<< 8) ++ ++ ++#define _LRL(x) ((x) & 0x3F) ++#define _SRL(x) (((x) & 0x3F) << 8) ++ ++ ++//2 SIFS_CCK ++#define _SIFS_CCK_CTX(x) ((x) & 0xFF) ++#define _SIFS_CCK_TRX(x) (((x) & 0xFF) << 8); ++ ++ ++//2 SIFS_OFDM ++#define _SIFS_OFDM_CTX(x) ((x) & 0xFF) ++#define _SIFS_OFDM_TRX(x) (((x) & 0xFF) << 8); ++ ++ ++//2 TBTT PROHIBIT ++#define _TBTT_PROHIBIT_HOLD(x) (((x) & 0xFF) << 8) ++ ++ ++//2 REG_RD_CTRL ++#define DIS_EDCA_CNT_DWN BIT(11) ++ ++ ++//2 BCN_CTRL ++#define EN_MBSSID BIT(1) ++#define EN_TXBCN_RPT BIT(2) ++#define EN_BCN_FUNCTION BIT(3) ++ ++// The same function but different bit field. ++#define DIS_TSF_UDT0_NORMAL_CHIP BIT(4) ++#define DIS_TSF_UDT0_TEST_CHIP BIT(5) ++ ++//2 ACMHWCTRL ++#define AcmHw_HwEn BIT(0) ++#define AcmHw_BeqEn BIT(1) ++#define AcmHw_ViqEn BIT(2) ++#define AcmHw_VoqEn BIT(3) ++#define AcmHw_BeqStatus BIT(4) ++#define AcmHw_ViqStatus BIT(5) ++#define AcmHw_VoqStatus BIT(6) ++ ++ ++ ++//----------------------------------------------------- ++// ++// 0x0600h ~ 0x07FFh WMAC Configuration ++// ++//----------------------------------------------------- ++ ++//2 APSD_CTRL ++#define APSDOFF BIT(6) ++#define APSDOFF_STATUS BIT(7) ++ ++ ++//2 BWOPMODE ++#define BW_20MHZ BIT(2) ++//#define BW_OPMODE_20MHZ BIT(2) // For compability ++ ++ ++#define RATE_BITMAP_ALL 0xFFFFF ++ ++// Only use CCK 1M rate for ACK ++#define RATE_RRSR_CCK_ONLY_1M 0xFFFF1 ++#define RATE_RRSR_WITHOUT_CCK 0xFFFF0 ++ ++//2 TCR ++#define TSFRST BIT(0) ++#define DIS_GCLK BIT(1) ++#define PAD_SEL BIT(2) ++#define PWR_ST BIT(6) ++#define PWRBIT_OW_EN BIT(7) ++#define ACRC BIT(8) ++#define CFENDFORM BIT(9) ++#define ICV BIT(10) ++ ++ ++ ++//2 RCR ++#define AAP BIT(0) ++#define APM BIT(1) ++#define AM BIT(2) ++#define AB BIT(3) ++#define ADD3 BIT(4) ++#define APWRMGT BIT(5) ++#define CBSSID BIT(6) ++#define CBSSID_BCN BIT(7) ++#define ACRC32 BIT(8) ++#define AICV BIT(9) ++#define ADF BIT(11) ++#define ACF BIT(12) ++#define AMF BIT(13) ++#define HTC_LOC_CTRL BIT(14) ++#define UC_DATA_EN BIT(16) ++#define BM_DATA_EN BIT(17) ++#define MFBEN BIT(22) ++#define LSIGEN BIT(23) ++#define EnMBID BIT(24) ++#define APP_BASSN BIT(27) ++#define APP_PHYSTS BIT(28) ++#define APP_ICV BIT(29) ++#define APP_MIC BIT(30) ++#define APP_FCS BIT(31) ++ ++//2 RX_PKT_LIMIT ++ ++//2 RX_DLK_TIME ++ ++//2 MBIDCAMCFG ++ ++ ++ ++//2 AMPDU_MIN_SPACE ++#define _MIN_SPACE(x) ((x) & 0x7) ++#define _SHORT_GI_PADDING(x) (((x) & 0x1F) << 3) ++ ++ ++//2 RXERR_RPT ++#define RXERR_TYPE_OFDM_PPDU 0 ++#define RXERR_TYPE_OFDM_FALSE_ALARM 1 ++#define RXERR_TYPE_OFDM_MPDU_OK 2 ++#define RXERR_TYPE_OFDM_MPDU_FAIL 3 ++#define RXERR_TYPE_CCK_PPDU 4 ++#define RXERR_TYPE_CCK_FALSE_ALARM 5 ++#define RXERR_TYPE_CCK_MPDU_OK 6 ++#define RXERR_TYPE_CCK_MPDU_FAIL 7 ++#define RXERR_TYPE_HT_PPDU 8 ++#define RXERR_TYPE_HT_FALSE_ALARM 9 ++#define RXERR_TYPE_HT_MPDU_TOTAL 10 ++#define RXERR_TYPE_HT_MPDU_OK 11 ++#define RXERR_TYPE_HT_MPDU_FAIL 12 ++#define RXERR_TYPE_RX_FULL_DROP 15 ++ ++#define RXERR_COUNTER_MASK 0xFFFFF ++#define RXERR_RPT_RST BIT(27) ++#define _RXERR_RPT_SEL(type) ((type) << 28) ++ ++ ++//2 SECCFG ++#define SCR_TxUseDK BIT(0) //Force Tx Use Default Key ++#define SCR_RxUseDK BIT(1) //Force Rx Use Default Key ++#define SCR_TxEncEnable BIT(2) //Enable Tx Encryption ++#define SCR_RxDecEnable BIT(3) //Enable Rx Decryption ++#define SCR_SKByA2 BIT(4) //Search kEY BY A2 ++#define SCR_NoSKMC BIT(5) //No Key Search Multicast ++#define SCR_TXBCUSEDK BIT(6) // Force Tx Broadcast packets Use Default Key ++#define SCR_RXBCUSEDK BIT(7) // Force Rx Broadcast packets Use Default Key ++ ++//vivi added for new cam search flow, 20091028 ++#ifdef HW_EN_DE_CRYPTION_FOR_NEW_CAM_SEARCH_FLOW ++#define SCR_TxUseBroadcastDK BIT6 //Force Tx Use Broadcast Default Key ++#define SCR_RxUseBroadcastDK BIT7 //Force Rx Use Broadcast Default Key ++#endif ++ ++ ++//----------------------------------------------------- ++// ++// 0xFE00h ~ 0xFE55h USB Configuration ++// ++//----------------------------------------------------- ++ ++//2 USB Information (0xFE17) ++#define USB_IS_HIGH_SPEED 0 ++#define USB_IS_FULL_SPEED 1 ++#define USB_SPEED_MASK BIT(5) ++ ++#define USB_NORMAL_SIE_EP_MASK 0xF ++#define USB_NORMAL_SIE_EP_SHIFT 4 ++ ++#define USB_TEST_EP_MASK 0x30 ++#define USB_TEST_EP_SHIFT 4 ++ ++//2 Special Option ++#define USB_AGG_EN BIT(3) ++ ++ ++//2REG_C2HEVT_CLEAR ++#define C2H_EVT_HOST_CLOSE 0x00 // Set by driver and notify FW that the driver has read the C2H command message ++#define C2H_EVT_FW_CLOSE 0xFF // Set by FW indicating that FW had set the C2H command message and it's not yet read by driver. ++ ++//2 8192D PartNo. ++#define PARTNO_92D_NIC (BIT7|BIT6) ++#define PARTNO_92D_NIC_REMARK (BIT5|BIT4) ++#define PARTNO_SINGLE_BAND_VS BIT3 ++#define PARTNO_SINGLE_BAND_VS_REMARK BIT1 ++#define PARTNO_CONCURRENT_BAND_VC (BIT3|BIT2) ++#define PARTNO_CONCURRENT_BAND_VC_REMARK (BIT1|BIT0) ++//======================================================== ++// General definitions ++//======================================================== ++ ++#define MAC_ADDR_LEN 6 ++#define LAST_ENTRY_OF_TX_PKT_BUFFER 255 ++#define LAST_ENTRY_OF_TX_PKT_BUFFER_DUAL_MAC 127 ++ ++#define POLLING_LLT_THRESHOLD 20 ++#define POLLING_READY_TIMEOUT_COUNT 1000 ++ ++// Min Spacing related settings. ++#define MAX_MSS_DENSITY_2T 0x13 ++#define MAX_MSS_DENSITY_1T 0x0A ++// GPIO BIT ++#define HAL_8192C_HW_GPIO_WPS_BIT BIT2 ++ ++ ++#include "basic_types.h" ++ ++#endif ++ +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/include/rtl8192d_xmit.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/include/rtl8192d_xmit.h 2013-07-26 19:36:06.000000000 +0000 +@@ -0,0 +1,106 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ++******************************************************************************/ ++#ifndef _RTL8192D_XMIT_H_ ++#define _RTL8192D_XMIT_H_ ++ ++#define VO_QUEUE_INX 0 ++#define VI_QUEUE_INX 1 ++#define BE_QUEUE_INX 2 ++#define BK_QUEUE_INX 3 ++#define BCN_QUEUE_INX 4 ++#define MGT_QUEUE_INX 5 ++#define HIGH_QUEUE_INX 6 ++#define TXCMD_QUEUE_INX 7 ++ ++#define HW_QUEUE_ENTRY 8 ++ ++// ++// Queue Select Value in TxDesc ++// ++#define QSLT_BK 0x2//0x01 ++#define QSLT_BE 0x0 ++#define QSLT_VI 0x5//0x4 ++#define QSLT_VO 0x7//0x6 ++#define QSLT_BEACON 0x10 ++#define QSLT_HIGH 0x11 ++#define QSLT_MGNT 0x12 ++#define QSLT_CMD 0x13 ++ ++//Because we open EM for normal case, we just always insert 2*8 bytes.by wl ++#define USB_92D_DUMMY_OFFSET 2 ++#define USB_92D_DUMMY_LENGTH (USB_92D_DUMMY_OFFSET * PACKET_OFFSET_SZ) ++#define USB_HWDESC_HEADER_LEN (TXDESC_SIZE + USB_92D_DUMMY_LENGTH) ++ ++//For 92D early mode ++#define SET_EARLYMODE_PKTNUM(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 0, 3, __Value) ++#define SET_EARLYMODE_LEN0(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 4, 12, __Value) ++#define SET_EARLYMODE_LEN1(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 16, 12, __Value) ++#define SET_EARLYMODE_LEN2_1(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr, 28, 4, __Value) ++#define SET_EARLYMODE_LEN2_2(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 0, 8, __Value) ++#define SET_EARLYMODE_LEN3(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 8, 12, __Value) ++#define SET_EARLYMODE_LEN4(__pAddr, __Value) SET_BITS_TO_LE_4BYTE(__pAddr+4, 20, 12, __Value) ++ ++#ifdef CONFIG_USB_HCI ++ ++#ifdef CONFIG_USB_TX_AGGREGATION ++#define MAX_TX_AGG_PACKET_NUMBER 0xFF ++#endif ++ ++s32 rtl8192du_init_xmit_priv(_adapter * padapter); ++ ++void rtl8192du_free_xmit_priv(_adapter * padapter); ++ ++void rtl8192du_cal_txdesc_chksum(struct tx_desc *ptxdesc); ++ ++s32 rtl8192du_xmitframe_complete(_adapter *padapter, struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf); ++ ++void rtl8192du_mgnt_xmit(_adapter *padapter, struct xmit_frame *pmgntframe); ++ ++s32 rtl8192du_hal_xmit(_adapter *padapter, struct xmit_frame *pxmitframe); ++ ++#ifdef CONFIG_HOSTAPD_MLME ++s32 rtl8192du_hostap_mgnt_xmit_entry(_adapter *padapter, _pkt *pkt); ++#endif ++ ++#endif ++ ++#ifdef CONFIG_PCI_HCI ++s32 rtl8192de_init_xmit_priv(_adapter * padapter); ++void rtl8192de_free_xmit_priv(_adapter * padapter); ++ ++s32 rtl8192de_enqueue_xmitbuf(struct rtw_tx_ring *ring, struct xmit_buf *pxmitbuf); ++struct xmit_buf *rtl8192de_dequeue_xmitbuf(struct rtw_tx_ring *ring); ++ ++void rtl8192de_xmitframe_resume(_adapter *padapter); ++ ++void rtl8192de_mgnt_xmit(_adapter *padapter, struct xmit_frame *pmgntframe); ++ ++s32 rtl8192de_hal_xmit(_adapter *padapter, struct xmit_frame *pxmitframe); ++ ++#ifdef CONFIG_HOSTAPD_MLME ++s32 rtl8192de_hostap_mgnt_xmit_entry(_adapter *padapter, _pkt *pkt); ++#endif ++ ++#endif ++ ++ ++#endif ++ +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/include/rtw_android.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/include/rtw_android.h 2013-07-26 19:36:06.000000000 +0000 +@@ -0,0 +1,80 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++ ++#ifndef __RTW_ANDROID_H__ ++#define __RTW_ANDROID_H__ ++ ++#include ++#include ++ ++enum ANDROID_WIFI_CMD { ++ ANDROID_WIFI_CMD_START, ++ ANDROID_WIFI_CMD_STOP, ++ ANDROID_WIFI_CMD_SCAN_ACTIVE, ++ ANDROID_WIFI_CMD_SCAN_PASSIVE, ++ ANDROID_WIFI_CMD_RSSI, ++ ANDROID_WIFI_CMD_LINKSPEED, ++ ANDROID_WIFI_CMD_RXFILTER_START, ++ ANDROID_WIFI_CMD_RXFILTER_STOP, ++ ANDROID_WIFI_CMD_RXFILTER_ADD, ++ ANDROID_WIFI_CMD_RXFILTER_REMOVE, ++ ANDROID_WIFI_CMD_BTCOEXSCAN_START, ++ ANDROID_WIFI_CMD_BTCOEXSCAN_STOP, ++ ANDROID_WIFI_CMD_BTCOEXMODE, ++ ANDROID_WIFI_CMD_SETSUSPENDOPT, ++ ANDROID_WIFI_CMD_P2P_DEV_ADDR, ++ ANDROID_WIFI_CMD_SETFWPATH, ++ ANDROID_WIFI_CMD_SETBAND, ++ ANDROID_WIFI_CMD_GETBAND, ++ ANDROID_WIFI_CMD_COUNTRY, ++ ANDROID_WIFI_CMD_P2P_SET_NOA, ++ ANDROID_WIFI_CMD_P2P_GET_NOA, ++ ANDROID_WIFI_CMD_P2P_SET_PS, ++ ANDROID_WIFI_CMD_SET_AP_WPS_P2P_IE, ++#ifdef PNO_SUPPORT ++ ANDROID_WIFI_CMD_PNOSSIDCLR_SET, ++ ANDROID_WIFI_CMD_PNOSETUP_SET, ++ ANDROID_WIFI_CMD_PNOENABLE_SET, ++ ANDROID_WIFI_CMD_PNODEBUG_SET, ++#endif ++ ++ ANDROID_WIFI_CMD_MACADDR, ++ ++ ANDROID_WIFI_CMD_BLOCK, ++ ++ ANDROID_WIFI_CMD_MAX ++}; ++ ++int rtw_android_cmdstr_to_num(char *cmdstr); ++int rtw_android_priv_cmd(struct net_device *net, struct ifreq *ifr, int cmd); ++ ++#if defined(CONFIG_WIFI_CONTROL_FUNC) && 0 ++int wl_android_wifictrl_func_add(void); ++void wl_android_wifictrl_func_del(void); ++void* wl_android_prealloc(int section, unsigned long size); ++ ++int wifi_get_irq_number(unsigned long *irq_flags_ptr); ++int wifi_set_power(int on, unsigned long msec); ++int wifi_get_mac_addr(unsigned char *buf); ++void *wifi_get_country_code(char *ccode); ++#endif /* CONFIG_WIFI_CONTROL_FUNC */ ++ ++#endif //__RTW_ANDROID_H__ ++ +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/include/rtw_br_ext.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/include/rtw_br_ext.h 2013-07-26 19:36:06.000000000 +0000 +@@ -0,0 +1,76 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef _RTW_BR_EXT_H_ ++#define _RTW_BR_EXT_H_ ++ ++#if 1 // rtw_wifi_driver ++#define CL_IPV6_PASS 1 ++#define MACADDRLEN 6 ++#define _DEBUG_ERR printk ++#define _DEBUG_INFO //printk ++#define DEBUG_WARN printk ++#define DEBUG_INFO //printk ++#define DEBUG_ERR printk ++//#define GET_MY_HWADDR ((GET_MIB(priv))->dot11OperationEntry.hwaddr) ++#define GET_MY_HWADDR(padapter) ((padapter)->eeprompriv.mac_addr) ++#endif // rtw_wifi_driver ++ ++#define NAT25_HASH_BITS 4 ++#define NAT25_HASH_SIZE (1 << NAT25_HASH_BITS) ++#define NAT25_AGEING_TIME 300 ++ ++#ifdef CL_IPV6_PASS ++#define MAX_NETWORK_ADDR_LEN 17 ++#else ++#define MAX_NETWORK_ADDR_LEN 11 ++#endif ++ ++struct nat25_network_db_entry ++{ ++ struct nat25_network_db_entry *next_hash; ++ struct nat25_network_db_entry **pprev_hash; ++ atomic_t use_count; ++ unsigned char macAddr[6]; ++ unsigned long ageing_timer; ++ unsigned char networkAddr[MAX_NETWORK_ADDR_LEN]; ++}; ++ ++enum NAT25_METHOD { ++ NAT25_MIN, ++ NAT25_CHECK, ++ NAT25_INSERT, ++ NAT25_LOOKUP, ++ NAT25_PARSE, ++ NAT25_MAX ++}; ++ ++struct br_ext_info { ++ unsigned int nat25_disable; ++ unsigned int macclone_enable; ++ unsigned int dhcp_bcst_disable; ++ int addPPPoETag; // 1: Add PPPoE relay-SID, 0: disable ++ unsigned char nat25_dmzMac[MACADDRLEN]; ++ unsigned int nat25sc_disable; ++}; ++ ++void nat25_db_cleanup(_adapter *priv); ++ ++#endif // _RTW_BR_EXT_H_ ++ +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/include/rtw_byteorder.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/include/rtw_byteorder.h 2013-07-26 19:36:06.000000000 +0000 +@@ -0,0 +1,41 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ++******************************************************************************/ ++#ifndef _RTL871X_BYTEORDER_H_ ++#define _RTL871X_BYTEORDER_H_ ++ ++#include ++ ++#if defined (CONFIG_LITTLE_ENDIAN) && defined (CONFIG_BIG_ENDIAN) ++#error "Shall be CONFIG_LITTLE_ENDIAN or CONFIG_BIG_ENDIAN, but not both!\n" ++#endif ++ ++#if defined (CONFIG_LITTLE_ENDIAN) ++#ifndef CONFIG_PLATFORM_MSTAR389 ++# include ++#endif ++#elif defined (CONFIG_BIG_ENDIAN) ++# include ++#else ++# error "Must be LITTLE/BIG Endian Host" ++#endif ++ ++#endif /* _RTL871X_BYTEORDER_H_ */ ++ +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/include/rtw_cmd.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/include/rtw_cmd.h 2013-07-26 19:36:06.000000000 +0000 +@@ -0,0 +1,1132 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ++******************************************************************************/ ++#ifndef __RTW_CMD_H_ ++#define __RTW_CMD_H_ ++ ++#include ++#include ++#include ++#include ++ ++#define C2H_MEM_SZ (16*1024) ++ ++#ifndef CONFIG_RTL8711FW ++ ++ #include ++ #include // ++ ++ ++ #define FREE_CMDOBJ_SZ 128 ++ ++ #define MAX_CMDSZ 1024 ++ #define MAX_RSPSZ 512 ++ #define MAX_EVTSZ 1024 ++ ++#ifdef PLATFORM_OS_CE ++ #define CMDBUFF_ALIGN_SZ 4 ++#else ++ #define CMDBUFF_ALIGN_SZ 512 ++#endif ++ ++ struct cmd_obj { ++ u16 cmdcode; ++ u8 res; ++ u8 *parmbuf; ++ u32 cmdsz; ++ u8 *rsp; ++ u32 rspsz; ++ //_sema cmd_sem; ++ _list list; ++ }; ++ ++ struct cmd_priv { ++ _sema cmd_queue_sema; ++ //_sema cmd_done_sema; ++ _sema terminate_cmdthread_sema; ++ _queue cmd_queue; ++ u8 cmd_seq; ++ u8 *cmd_buf; //shall be non-paged, and 4 bytes aligned ++ u8 *cmd_allocated_buf; ++ u8 *rsp_buf; //shall be non-paged, and 4 bytes aligned ++ u8 *rsp_allocated_buf; ++ u32 cmd_issued_cnt; ++ u32 cmd_done_cnt; ++ u32 rsp_cnt; ++ u8 cmdthd_running; ++ _adapter *padapter; ++ }; ++ ++#ifdef CONFIG_EVENT_THREAD_MODE ++ struct evt_obj { ++ u16 evtcode; ++ u8 res; ++ u8 *parmbuf; ++ u32 evtsz; ++ _list list; ++ }; ++#endif ++ ++ struct evt_priv { ++#ifdef CONFIG_EVENT_THREAD_MODE ++ _sema evt_notify; ++ _sema terminate_evtthread_sema; ++ _queue evt_queue; ++#endif ++ ++#ifdef CONFIG_H2CLBK ++ _sema lbkevt_done; ++ u8 lbkevt_limit; ++ u8 lbkevt_num; ++ u8 *cmdevt_parm; ++#endif ++ ATOMIC_T event_seq; ++ u8 *evt_buf; //shall be non-paged, and 4 bytes aligned ++ u8 *evt_allocated_buf; ++ u32 evt_done_cnt; ++#ifdef CONFIG_SDIO_HCI ++ u8 *c2h_mem; ++ u8 *allocated_c2h_mem; ++#ifdef PLATFORM_OS_XP ++ PMDL pc2h_mdl; ++#endif ++#endif ++ ++ }; ++ ++#define init_h2fwcmd_w_parm_no_rsp(pcmd, pparm, code) \ ++do {\ ++ _rtw_init_listhead(&pcmd->list);\ ++ pcmd->cmdcode = code;\ ++ pcmd->parmbuf = (u8 *)(pparm);\ ++ pcmd->cmdsz = sizeof (*pparm);\ ++ pcmd->rsp = NULL;\ ++ pcmd->rspsz = 0;\ ++} while(0) ++ ++extern u32 rtw_enqueue_cmd(struct cmd_priv *pcmdpriv, struct cmd_obj *obj); ++extern struct cmd_obj *rtw_dequeue_cmd(struct cmd_priv *pcmdpriv); ++extern void rtw_free_cmd_obj(struct cmd_obj *pcmd); ++ ++#ifdef CONFIG_EVENT_THREAD_MODE ++extern u32 rtw_enqueue_evt(struct evt_priv *pevtpriv, struct evt_obj *obj); ++extern struct evt_obj *rtw_dequeue_evt(_queue *queue); ++extern void rtw_free_evt_obj(struct evt_obj *pcmd); ++#endif ++ ++thread_return rtw_cmd_thread(thread_context context); ++ ++extern u32 rtw_init_cmd_priv (struct cmd_priv *pcmdpriv); ++extern void rtw_free_cmd_priv (struct cmd_priv *pcmdpriv); ++ ++extern u32 rtw_init_evt_priv (struct evt_priv *pevtpriv); ++extern void rtw_free_evt_priv (struct evt_priv *pevtpriv); ++extern void rtw_cmd_clr_isr(struct cmd_priv *pcmdpriv); ++extern void rtw_evt_notify_isr(struct evt_priv *pevtpriv); ++#ifdef CONFIG_P2P ++u8 p2p_protocol_wk_cmd(_adapter*padapter, int intCmdType ); ++#endif //CONFIG_P2P ++ ++#else ++ #include ++#endif /* CONFIG_RTL8711FW */ ++ ++enum rtw_drvextra_cmd_id ++{ ++ NONE_WK_CID, ++ DYNAMIC_CHK_WK_CID, ++ DM_CTRL_WK_CID, ++ PBC_POLLING_WK_CID, ++ POWER_SAVING_CTRL_WK_CID,//IPS,AUTOSuspend ++ LPS_CTRL_WK_CID, ++ ANT_SELECT_WK_CID, ++ P2P_PS_WK_CID, ++ P2P_PROTO_WK_CID, ++ CHECK_HIQ_WK_CID,//for softap mode, check hi queue if empty ++ MAX_WK_CID ++}; ++ ++enum LPS_CTRL_TYPE ++{ ++ LPS_CTRL_SCAN=0, ++ LPS_CTRL_JOINBSS=1, ++ LPS_CTRL_CONNECT=2, ++ LPS_CTRL_DISCONNECT=3, ++ LPS_CTRL_SPECIAL_PACKET=4, ++}; ++ ++enum RFINTFS { ++ SWSI, ++ HWSI, ++ HWPI, ++}; ++ ++/* ++Caller Mode: Infra, Ad-HoC(C) ++ ++Notes: To enter USB suspend mode ++ ++Command Mode ++ ++*/ ++struct usb_suspend_parm { ++ u32 action;// 1: sleep, 0:resume ++}; ++ ++/* ++Caller Mode: Infra, Ad-HoC ++ ++Notes: To join a known BSS. ++ ++Command-Event Mode ++ ++*/ ++ ++/* ++Caller Mode: Infra, Ad-Hoc ++ ++Notes: To join the specified bss ++ ++Command Event Mode ++ ++*/ ++struct joinbss_parm { ++ WLAN_BSSID_EX network; ++}; ++ ++/* ++Caller Mode: Infra, Ad-HoC(C) ++ ++Notes: To disconnect the current associated BSS ++ ++Command Mode ++ ++*/ ++struct disconnect_parm { ++ u32 rsvd; ++}; ++ ++/* ++Caller Mode: AP, Ad-HoC(M) ++ ++Notes: To create a BSS ++ ++Command Mode ++*/ ++struct createbss_parm { ++ WLAN_BSSID_EX network; ++}; ++ ++/* ++Caller Mode: AP, Ad-HoC, Infra ++ ++Notes: To set the NIC mode of RTL8711 ++ ++Command Mode ++ ++The definition of mode: ++ ++#define IW_MODE_AUTO 0 // Let the driver decides which AP to join ++#define IW_MODE_ADHOC 1 // Single cell network (Ad-Hoc Clients) ++#define IW_MODE_INFRA 2 // Multi cell network, roaming, .. ++#define IW_MODE_MASTER 3 // Synchronisation master or Access Point ++#define IW_MODE_REPEAT 4 // Wireless Repeater (forwarder) ++#define IW_MODE_SECOND 5 // Secondary master/repeater (backup) ++#define IW_MODE_MONITOR 6 // Passive monitor (listen only) ++ ++*/ ++struct setopmode_parm { ++ u8 mode; ++ u8 rsvd[3]; ++}; ++ ++/* ++Caller Mode: AP, Ad-HoC, Infra ++ ++Notes: To ask RTL8711 performing site-survey ++ ++Command-Event Mode ++ ++*/ ++ ++#define RTW_SSID_SCAN_AMOUNT 9 // for WEXT_CSCAN_AMOUNT 9 ++struct sitesurvey_parm { ++ sint scan_mode; //active: 1, passive: 0 ++ sint bsslimit; // 1 ~ 48 ++ // for up to 9 probreq with specific ssid ++ NDIS_802_11_SSID ssid[RTW_SSID_SCAN_AMOUNT]; ++}; ++ ++/* ++Caller Mode: Any ++ ++Notes: To set the auth type of RTL8711. open/shared/802.1x ++ ++Command Mode ++ ++*/ ++struct setauth_parm { ++ u8 mode; //0: legacy open, 1: legacy shared 2: 802.1x ++ u8 _1x; //0: PSK, 1: TLS ++ u8 rsvd[2]; ++}; ++ ++/* ++Caller Mode: Infra ++ ++a. algorithm: wep40, wep104, tkip & aes ++b. keytype: grp key/unicast key ++c. key contents ++ ++when shared key ==> keyid is the camid ++when 802.1x ==> keyid [0:1] ==> grp key ++when 802.1x ==> keyid > 2 ==> unicast key ++ ++*/ ++struct setkey_parm { ++ u8 algorithm; // encryption algorithm, could be none, wep40, TKIP, CCMP, wep104 ++ u8 keyid; ++ u8 grpkey; // 1: this is the grpkey for 802.1x. 0: this is the unicast key for 802.1x ++ u8 set_tx; // 1: main tx key for wep. 0: other key. ++ u8 key[16]; // this could be 40 or 104 ++}; ++ ++/* ++When in AP or Ad-Hoc mode, this is used to ++allocate an sw/hw entry for a newly associated sta. ++ ++Command ++ ++when shared key ==> algorithm/keyid ++ ++*/ ++struct set_stakey_parm { ++ u8 addr[ETH_ALEN]; ++ u8 algorithm; ++ u8 key[16]; ++}; ++ ++struct set_stakey_rsp { ++ u8 addr[ETH_ALEN]; ++ u8 keyid; ++ u8 rsvd; ++}; ++ ++/* ++Caller Ad-Hoc/AP ++ ++Command -Rsp(AID == CAMID) mode ++ ++This is to force fw to add an sta_data entry per driver's request. ++ ++FW will write an cam entry associated with it. ++ ++*/ ++struct set_assocsta_parm { ++ u8 addr[ETH_ALEN]; ++}; ++ ++struct set_assocsta_rsp { ++ u8 cam_id; ++ u8 rsvd[3]; ++}; ++ ++/* ++ Caller Ad-Hoc/AP ++ ++ Command mode ++ ++ This is to force fw to del an sta_data entry per driver's request ++ ++ FW will invalidate the cam entry associated with it. ++ ++*/ ++struct del_assocsta_parm { ++ u8 addr[ETH_ALEN]; ++}; ++ ++/* ++Caller Mode: AP/Ad-HoC(M) ++ ++Notes: To notify fw that given staid has changed its power state ++ ++Command Mode ++ ++*/ ++struct setstapwrstate_parm { ++ u8 staid; ++ u8 status; ++ u8 hwaddr[6]; ++}; ++ ++/* ++Caller Mode: Any ++ ++Notes: To setup the basic rate of RTL8711 ++ ++Command Mode ++ ++*/ ++struct setbasicrate_parm { ++ u8 basicrates[NumRates]; ++}; ++ ++/* ++Caller Mode: Any ++ ++Notes: To read the current basic rate ++ ++Command-Rsp Mode ++ ++*/ ++struct getbasicrate_parm { ++ u32 rsvd; ++}; ++ ++struct getbasicrate_rsp { ++ u8 basicrates[NumRates]; ++}; ++ ++/* ++Caller Mode: Any ++ ++Notes: To setup the data rate of RTL8711 ++ ++Command Mode ++ ++*/ ++struct setdatarate_parm { ++#ifdef MP_FIRMWARE_OFFLOAD ++ u32 curr_rateidx; ++#else ++ u8 mac_id; ++ u8 datarates[NumRates]; ++#endif ++}; ++ ++/* ++Caller Mode: Any ++ ++Notes: To read the current data rate ++ ++Command-Rsp Mode ++ ++*/ ++struct getdatarate_parm { ++ u32 rsvd; ++ ++}; ++struct getdatarate_rsp { ++ u8 datarates[NumRates]; ++}; ++ ++ ++/* ++Caller Mode: Any ++AP: AP can use the info for the contents of beacon frame ++Infra: STA can use the info when sitesurveying ++Ad-HoC(M): Like AP ++Ad-HoC(C): Like STA ++ ++ ++Notes: To set the phy capability of the NIC ++ ++Command Mode ++ ++*/ ++ ++struct setphyinfo_parm { ++ struct regulatory_class class_sets[NUM_REGULATORYS]; ++ u8 status; ++}; ++ ++struct getphyinfo_parm { ++ u32 rsvd; ++}; ++ ++struct getphyinfo_rsp { ++ struct regulatory_class class_sets[NUM_REGULATORYS]; ++ u8 status; ++}; ++ ++/* ++Caller Mode: Any ++ ++Notes: To set the channel/modem/band ++This command will be used when channel/modem/band is changed. ++ ++Command Mode ++ ++*/ ++struct setphy_parm { ++ u8 rfchannel; ++ u8 modem; ++}; ++ ++/* ++Caller Mode: Any ++ ++Notes: To get the current setting of channel/modem/band ++ ++Command-Rsp Mode ++ ++*/ ++struct getphy_parm { ++ u32 rsvd; ++ ++}; ++struct getphy_rsp { ++ u8 rfchannel; ++ u8 modem; ++}; ++ ++struct readBB_parm { ++ u8 offset; ++}; ++struct readBB_rsp { ++ u8 value; ++}; ++ ++struct readTSSI_parm { ++ u8 offset; ++}; ++struct readTSSI_rsp { ++ u8 value; ++}; ++ ++struct writeBB_parm { ++ u8 offset; ++ u8 value; ++}; ++ ++struct readRF_parm { ++ u8 offset; ++}; ++struct readRF_rsp { ++ u32 value; ++}; ++ ++struct writeRF_parm { ++ u32 offset; ++ u32 value; ++}; ++ ++struct getrfintfs_parm { ++ u8 rfintfs; ++}; ++ ++ ++struct Tx_Beacon_param ++{ ++ WLAN_BSSID_EX network; ++}; ++ ++/* ++ Notes: This command is used for H2C/C2H loopback testing ++ ++ mac[0] == 0 ++ ==> CMD mode, return H2C_SUCCESS. ++ The following condition must be ture under CMD mode ++ mac[1] == mac[4], mac[2] == mac[3], mac[0]=mac[5]= 0; ++ s0 == 0x1234, s1 == 0xabcd, w0 == 0x78563412, w1 == 0x5aa5def7; ++ s2 == (b1 << 8 | b0); ++ ++ mac[0] == 1 ++ ==> CMD_RSP mode, return H2C_SUCCESS_RSP ++ ++ The rsp layout shall be: ++ rsp: parm: ++ mac[0] = mac[5]; ++ mac[1] = mac[4]; ++ mac[2] = mac[3]; ++ mac[3] = mac[2]; ++ mac[4] = mac[1]; ++ mac[5] = mac[0]; ++ s0 = s1; ++ s1 = swap16(s0); ++ w0 = swap32(w1); ++ b0 = b1 ++ s2 = s0 + s1 ++ b1 = b0 ++ w1 = w0 ++ ++ mac[0] == 2 ++ ==> CMD_EVENT mode, return H2C_SUCCESS ++ The event layout shall be: ++ event: parm: ++ mac[0] = mac[5]; ++ mac[1] = mac[4]; ++ mac[2] = event's sequence number, starting from 1 to parm's marc[3] ++ mac[3] = mac[2]; ++ mac[4] = mac[1]; ++ mac[5] = mac[0]; ++ s0 = swap16(s0) - event.mac[2]; ++ s1 = s1 + event.mac[2]; ++ w0 = swap32(w0); ++ b0 = b1 ++ s2 = s0 + event.mac[2] ++ b1 = b0 ++ w1 = swap32(w1) - event.mac[2]; ++ ++ parm->mac[3] is the total event counts that host requested. ++ ++ ++ event will be the same with the cmd's param. ++ ++*/ ++ ++#ifdef CONFIG_H2CLBK ++ ++struct seth2clbk_parm { ++ u8 mac[6]; ++ u16 s0; ++ u16 s1; ++ u32 w0; ++ u8 b0; ++ u16 s2; ++ u8 b1; ++ u32 w1; ++}; ++ ++struct geth2clbk_parm { ++ u32 rsv; ++}; ++ ++struct geth2clbk_rsp { ++ u8 mac[6]; ++ u16 s0; ++ u16 s1; ++ u32 w0; ++ u8 b0; ++ u16 s2; ++ u8 b1; ++ u32 w1; ++}; ++ ++#endif /* CONFIG_H2CLBK */ ++ ++// CMD param Formart for driver extra cmd handler ++struct drvextra_cmd_parm { ++ int ec_id; //extra cmd id ++ int type_size; // Can use this field as the type id or command size ++ unsigned char *pbuf; ++}; ++ ++/*------------------- Below are used for RF/BB tunning ---------------------*/ ++ ++struct setantenna_parm { ++ u8 tx_antset; ++ u8 rx_antset; ++ u8 tx_antenna; ++ u8 rx_antenna; ++}; ++ ++struct enrateadaptive_parm { ++ u32 en; ++}; ++ ++struct settxagctbl_parm { ++ u32 txagc[MAX_RATES_LENGTH]; ++}; ++ ++struct gettxagctbl_parm { ++ u32 rsvd; ++}; ++struct gettxagctbl_rsp { ++ u32 txagc[MAX_RATES_LENGTH]; ++}; ++ ++struct setagcctrl_parm { ++ u32 agcctrl; // 0: pure hw, 1: fw ++}; ++ ++ ++struct setssup_parm { ++ u32 ss_ForceUp[MAX_RATES_LENGTH]; ++}; ++ ++struct getssup_parm { ++ u32 rsvd; ++}; ++struct getssup_rsp { ++ u8 ss_ForceUp[MAX_RATES_LENGTH]; ++}; ++ ++ ++struct setssdlevel_parm { ++ u8 ss_DLevel[MAX_RATES_LENGTH]; ++}; ++ ++struct getssdlevel_parm { ++ u32 rsvd; ++}; ++struct getssdlevel_rsp { ++ u8 ss_DLevel[MAX_RATES_LENGTH]; ++}; ++ ++struct setssulevel_parm { ++ u8 ss_ULevel[MAX_RATES_LENGTH]; ++}; ++ ++struct getssulevel_parm { ++ u32 rsvd; ++}; ++struct getssulevel_rsp { ++ u8 ss_ULevel[MAX_RATES_LENGTH]; ++}; ++ ++ ++struct setcountjudge_parm { ++ u8 count_judge[MAX_RATES_LENGTH]; ++}; ++ ++struct getcountjudge_parm { ++ u32 rsvd; ++}; ++struct getcountjudge_rsp { ++ u8 count_judge[MAX_RATES_LENGTH]; ++}; ++ ++ ++struct setratable_parm { ++ u8 ss_ForceUp[NumRates]; ++ u8 ss_ULevel[NumRates]; ++ u8 ss_DLevel[NumRates]; ++ u8 count_judge[NumRates]; ++}; ++ ++struct getratable_parm { ++ uint rsvd; ++}; ++struct getratable_rsp { ++ u8 ss_ForceUp[NumRates]; ++ u8 ss_ULevel[NumRates]; ++ u8 ss_DLevel[NumRates]; ++ u8 count_judge[NumRates]; ++}; ++ ++ ++//to get TX,RX retry count ++struct gettxretrycnt_parm{ ++ unsigned int rsvd; ++}; ++struct gettxretrycnt_rsp{ ++ unsigned long tx_retrycnt; ++}; ++ ++struct getrxretrycnt_parm{ ++ unsigned int rsvd; ++}; ++struct getrxretrycnt_rsp{ ++ unsigned long rx_retrycnt; ++}; ++ ++//to get BCNOK,BCNERR count ++struct getbcnokcnt_parm{ ++ unsigned int rsvd; ++}; ++struct getbcnokcnt_rsp{ ++ unsigned long bcnokcnt; ++}; ++ ++struct getbcnerrcnt_parm{ ++ unsigned int rsvd; ++}; ++struct getbcnerrcnt_rsp{ ++ unsigned long bcnerrcnt; ++}; ++ ++// to get current TX power level ++struct getcurtxpwrlevel_parm{ ++ unsigned int rsvd; ++}; ++struct getcurtxpwrlevel_rsp{ ++ unsigned short tx_power; ++}; ++ ++struct setprobereqextraie_parm { ++ unsigned char e_id; ++ unsigned char ie_len; ++ unsigned char ie[0]; ++}; ++ ++struct setassocreqextraie_parm { ++ unsigned char e_id; ++ unsigned char ie_len; ++ unsigned char ie[0]; ++}; ++ ++struct setproberspextraie_parm { ++ unsigned char e_id; ++ unsigned char ie_len; ++ unsigned char ie[0]; ++}; ++ ++struct setassocrspextraie_parm { ++ unsigned char e_id; ++ unsigned char ie_len; ++ unsigned char ie[0]; ++}; ++ ++ ++struct addBaReq_parm ++{ ++ unsigned int tid; ++ u8 addr[ETH_ALEN]; ++}; ++ ++/*H2C Handler index: 46 */ ++struct SetChannel_parm ++{ ++ u32 curr_ch; ++}; ++ ++#ifdef MP_FIRMWARE_OFFLOAD ++/*H2C Handler index: 47 */ ++struct SetTxPower_parm ++{ ++ u8 TxPower; ++}; ++ ++/*H2C Handler index: 48 */ ++struct SwitchAntenna_parm ++{ ++ u16 antenna_tx; ++ u16 antenna_rx; ++// R_ANTENNA_SELECT_CCK cck_txrx; ++ u8 cck_txrx; ++}; ++ ++/*H2C Handler index: 49 */ ++struct SetCrystalCap_parm ++{ ++ u32 curr_crystalcap; ++}; ++ ++/*H2C Handler index: 50 */ ++struct SetSingleCarrierTx_parm ++{ ++ u8 bStart; ++}; ++ ++/*H2C Handler index: 51 */ ++struct SetSingleToneTx_parm ++{ ++ u8 bStart; ++ u8 curr_rfpath; ++}; ++ ++/*H2C Handler index: 52 */ ++struct SetCarrierSuppressionTx_parm ++{ ++ u8 bStart; ++ u32 curr_rateidx; ++}; ++ ++/*H2C Handler index: 53 */ ++struct SetContinuousTx_parm ++{ ++ u8 bStart; ++ u8 CCK_flag; /*1:CCK 2:OFDM*/ ++ u32 curr_rateidx; ++}; ++ ++/*H2C Handler index: 54 */ ++struct SwitchBandwidth_parm ++{ ++ u8 curr_bandwidth; ++}; ++ ++#endif /* MP_FIRMWARE_OFFLOAD */ ++ ++/*H2C Handler index: 59 */ ++struct SetChannelPlan_param ++{ ++ u8 channel_plan; ++}; ++ ++/*H2C Handler index: 60 */ ++struct LedBlink_param ++{ ++ PLED_871x pLed; ++}; ++ ++/*H2C Handler index: 61 */ ++struct SetChannelSwitch_param ++{ ++ u8 new_ch_no; ++}; ++ ++/*H2C Handler index: 62 */ ++struct TDLSoption_param ++{ ++ u8 addr[ETH_ALEN]; ++ u8 option; ++}; ++ ++#define GEN_CMD_CODE(cmd) cmd ## _CMD_ ++ ++ ++/* ++ ++Result: ++0x00: success ++0x01: sucess, and check Response. ++0x02: cmd ignored due to duplicated sequcne number ++0x03: cmd dropped due to invalid cmd code ++0x04: reserved. ++ ++*/ ++ ++#define H2C_RSP_OFFSET 512 ++ ++#define H2C_SUCCESS 0x00 ++#define H2C_SUCCESS_RSP 0x01 ++#define H2C_DUPLICATED 0x02 ++#define H2C_DROPPED 0x03 ++#define H2C_PARAMETERS_ERROR 0x04 ++#define H2C_REJECTED 0x05 ++#define H2C_CMD_OVERFLOW 0x06 ++#define H2C_RESERVED 0x07 ++ ++extern u8 rtw_setassocsta_cmd(_adapter *padapter, u8 *mac_addr); ++extern u8 rtw_setstandby_cmd(_adapter *padapter, uint action); ++extern u8 rtw_sitesurvey_cmd(_adapter *padapter, NDIS_802_11_SSID *pssid, int ssid_max_num); ++extern u8 rtw_createbss_cmd(_adapter *padapter); ++extern u8 rtw_createbss_cmd_ex(_adapter *padapter, unsigned char *pbss, unsigned int sz); ++extern u8 rtw_setphy_cmd(_adapter *padapter, u8 modem, u8 ch); ++extern u8 rtw_setstakey_cmd(_adapter *padapter, u8 *psta, u8 unicast_key); ++extern u8 rtw_joinbss_cmd(_adapter *padapter, struct wlan_network* pnetwork); ++extern u8 rtw_disassoc_cmd(_adapter *padapter); ++extern u8 rtw_setopmode_cmd(_adapter *padapter, NDIS_802_11_NETWORK_INFRASTRUCTURE networktype); ++extern u8 rtw_setdatarate_cmd(_adapter *padapter, u8 *rateset); ++extern u8 rtw_setbasicrate_cmd(_adapter *padapter, u8 *rateset); ++extern u8 rtw_setbbreg_cmd(_adapter * padapter, u8 offset, u8 val); ++extern u8 rtw_setrfreg_cmd(_adapter * padapter, u8 offset, u32 val); ++extern u8 rtw_getbbreg_cmd(_adapter * padapter, u8 offset, u8 * pval); ++extern u8 rtw_getrfreg_cmd(_adapter * padapter, u8 offset, u8 * pval); ++extern u8 rtw_setrfintfs_cmd(_adapter *padapter, u8 mode); ++extern u8 rtw_setrttbl_cmd(_adapter *padapter, struct setratable_parm *prate_table); ++extern u8 rtw_getrttbl_cmd(_adapter *padapter, struct getratable_rsp *pval); ++ ++extern u8 rtw_gettssi_cmd(_adapter *padapter, u8 offset,u8 *pval); ++extern u8 rtw_setfwdig_cmd(_adapter*padapter, u8 type); ++extern u8 rtw_setfwra_cmd(_adapter*padapter, u8 type); ++ ++extern u8 rtw_addbareq_cmd(_adapter*padapter, u8 tid, u8 *addr); ++ ++extern u8 rtw_dynamic_chk_wk_cmd(_adapter *adapter); ++ ++u8 rtw_lps_ctrl_wk_cmd(_adapter*padapter, u8 lps_ctrl_type, u8 enqueue); ++ ++#ifdef CONFIG_ANTENNA_DIVERSITY ++extern u8 rtw_antenna_select_cmd(_adapter*padapter, u8 antenna,u8 enqueue); ++#endif ++ ++extern u8 rtw_ps_cmd(_adapter*padapter); ++ ++ ++#ifdef CONFIG_AP_MODE ++u8 rtw_chk_hi_queue_cmd(_adapter*padapter); ++#endif ++ ++extern u8 rtw_set_chplan_cmd(_adapter*padapter, u8 chplan, u8 enaueue); ++extern u8 rtw_led_blink_cmd(_adapter*padapter, PLED_871x pLed); ++extern u8 rtw_set_csa_cmd(_adapter*padapter, u8 new_ch_no); ++extern u8 rtw_tdls_cmd(_adapter*padapter, u8 *addr, u8 option); ++ ++u8 rtw_drvextra_cmd_hdl(_adapter *padapter, unsigned char *pbuf); ++ ++extern void rtw_survey_cmd_callback(_adapter *padapter, struct cmd_obj *pcmd); ++extern void rtw_disassoc_cmd_callback(_adapter *padapter, struct cmd_obj *pcmd); ++extern void rtw_joinbss_cmd_callback(_adapter *padapter, struct cmd_obj *pcmd); ++extern void rtw_createbss_cmd_callback(_adapter *padapter, struct cmd_obj *pcmd); ++extern void rtw_getbbrfreg_cmdrsp_callback(_adapter *padapter, struct cmd_obj *pcmd); ++extern void rtw_readtssi_cmdrsp_callback(_adapter* padapter, struct cmd_obj *pcmd); ++ ++extern void rtw_setstaKey_cmdrsp_callback(_adapter *padapter, struct cmd_obj *pcmd); ++extern void rtw_setassocsta_cmdrsp_callback(_adapter *padapter, struct cmd_obj *pcmd); ++extern void rtw_getrttbl_cmdrsp_callback(_adapter *padapter, struct cmd_obj *pcmd); ++ ++ ++struct _cmd_callback { ++ u32 cmd_code; ++ void (*callback)(_adapter *padapter, struct cmd_obj *cmd); ++}; ++ ++enum rtw_h2c_cmd ++{ ++ GEN_CMD_CODE(_Read_MACREG) , /*0*/ ++ GEN_CMD_CODE(_Write_MACREG) , ++ GEN_CMD_CODE(_Read_BBREG) , ++ GEN_CMD_CODE(_Write_BBREG) , ++ GEN_CMD_CODE(_Read_RFREG) , ++ GEN_CMD_CODE(_Write_RFREG) , /*5*/ ++ GEN_CMD_CODE(_Read_EEPROM) , ++ GEN_CMD_CODE(_Write_EEPROM) , ++ GEN_CMD_CODE(_Read_EFUSE) , ++ GEN_CMD_CODE(_Write_EFUSE) , ++ ++ GEN_CMD_CODE(_Read_CAM) , /*10*/ ++ GEN_CMD_CODE(_Write_CAM) , ++ GEN_CMD_CODE(_setBCNITV), ++ GEN_CMD_CODE(_setMBIDCFG), ++ GEN_CMD_CODE(_JoinBss), /*14*/ ++ GEN_CMD_CODE(_DisConnect) , /*15*/ ++ GEN_CMD_CODE(_CreateBss) , ++ GEN_CMD_CODE(_SetOpMode) , ++ GEN_CMD_CODE(_SiteSurvey), /*18*/ ++ GEN_CMD_CODE(_SetAuth) , ++ ++ GEN_CMD_CODE(_SetKey) , /*20*/ ++ GEN_CMD_CODE(_SetStaKey) , ++ GEN_CMD_CODE(_SetAssocSta) , ++ GEN_CMD_CODE(_DelAssocSta) , ++ GEN_CMD_CODE(_SetStaPwrState) , ++ GEN_CMD_CODE(_SetBasicRate) , /*25*/ ++ GEN_CMD_CODE(_GetBasicRate) , ++ GEN_CMD_CODE(_SetDataRate) , ++ GEN_CMD_CODE(_GetDataRate) , ++ GEN_CMD_CODE(_SetPhyInfo) , ++ ++ GEN_CMD_CODE(_GetPhyInfo) , /*30*/ ++ GEN_CMD_CODE(_SetPhy) , ++ GEN_CMD_CODE(_GetPhy) , ++ GEN_CMD_CODE(_readRssi) , ++ GEN_CMD_CODE(_readGain) , ++ GEN_CMD_CODE(_SetAtim) , /*35*/ ++ GEN_CMD_CODE(_SetPwrMode) , ++ GEN_CMD_CODE(_JoinbssRpt), ++ GEN_CMD_CODE(_SetRaTable) , ++ GEN_CMD_CODE(_GetRaTable) , ++ ++ GEN_CMD_CODE(_GetCCXReport), /*40*/ ++ GEN_CMD_CODE(_GetDTMReport), ++ GEN_CMD_CODE(_GetTXRateStatistics), ++ GEN_CMD_CODE(_SetUsbSuspend), ++ GEN_CMD_CODE(_SetH2cLbk), ++ GEN_CMD_CODE(_AddBAReq) , /*45*/ ++ GEN_CMD_CODE(_SetChannel), /*46*/ ++ GEN_CMD_CODE(_SetTxPower), ++ GEN_CMD_CODE(_SwitchAntenna), ++ GEN_CMD_CODE(_SetCrystalCap), ++ GEN_CMD_CODE(_SetSingleCarrierTx), /*50*/ ++ ++ GEN_CMD_CODE(_SetSingleToneTx),/*51*/ ++ GEN_CMD_CODE(_SetCarrierSuppressionTx), ++ GEN_CMD_CODE(_SetContinuousTx), ++ GEN_CMD_CODE(_SwitchBandwidth), /*54*/ ++ GEN_CMD_CODE(_TX_Beacon), /*55*/ ++ ++ GEN_CMD_CODE(_Set_MLME_EVT), /*56*/ ++ GEN_CMD_CODE(_Set_Drv_Extra), /*57*/ ++ GEN_CMD_CODE(_Set_H2C_MSG), /*58*/ ++ ++ GEN_CMD_CODE(_SetChannelPlan), /*59*/ ++ GEN_CMD_CODE(_LedBlink), /*60*/ ++ ++ GEN_CMD_CODE(_SetChannelSwitch), /*61*/ ++ GEN_CMD_CODE(_TDLS), /*62*/ ++ ++ MAX_H2CCMD ++}; ++ ++#define _GetBBReg_CMD_ _Read_BBREG_CMD_ ++#define _SetBBReg_CMD_ _Write_BBREG_CMD_ ++#define _GetRFReg_CMD_ _Read_RFREG_CMD_ ++#define _SetRFReg_CMD_ _Write_RFREG_CMD_ ++ ++#ifdef _RTW_CMD_C_ ++struct _cmd_callback rtw_cmd_callback[] = ++{ ++ {GEN_CMD_CODE(_Read_MACREG), NULL}, /*0*/ ++ {GEN_CMD_CODE(_Write_MACREG), NULL}, ++ {GEN_CMD_CODE(_Read_BBREG), &rtw_getbbrfreg_cmdrsp_callback}, ++ {GEN_CMD_CODE(_Write_BBREG), NULL}, ++ {GEN_CMD_CODE(_Read_RFREG), &rtw_getbbrfreg_cmdrsp_callback}, ++ {GEN_CMD_CODE(_Write_RFREG), NULL}, /*5*/ ++ {GEN_CMD_CODE(_Read_EEPROM), NULL}, ++ {GEN_CMD_CODE(_Write_EEPROM), NULL}, ++ {GEN_CMD_CODE(_Read_EFUSE), NULL}, ++ {GEN_CMD_CODE(_Write_EFUSE), NULL}, ++ ++ {GEN_CMD_CODE(_Read_CAM), NULL}, /*10*/ ++ {GEN_CMD_CODE(_Write_CAM), NULL}, ++ {GEN_CMD_CODE(_setBCNITV), NULL}, ++ {GEN_CMD_CODE(_setMBIDCFG), NULL}, ++ {GEN_CMD_CODE(_JoinBss), &rtw_joinbss_cmd_callback}, /*14*/ ++ {GEN_CMD_CODE(_DisConnect), &rtw_disassoc_cmd_callback}, /*15*/ ++ {GEN_CMD_CODE(_CreateBss), &rtw_createbss_cmd_callback}, ++ {GEN_CMD_CODE(_SetOpMode), NULL}, ++ {GEN_CMD_CODE(_SiteSurvey), &rtw_survey_cmd_callback}, /*18*/ ++ {GEN_CMD_CODE(_SetAuth), NULL}, ++ ++ {GEN_CMD_CODE(_SetKey), NULL}, /*20*/ ++ {GEN_CMD_CODE(_SetStaKey), &rtw_setstaKey_cmdrsp_callback}, ++ {GEN_CMD_CODE(_SetAssocSta), &rtw_setassocsta_cmdrsp_callback}, ++ {GEN_CMD_CODE(_DelAssocSta), NULL}, ++ {GEN_CMD_CODE(_SetStaPwrState), NULL}, ++ {GEN_CMD_CODE(_SetBasicRate), NULL}, /*25*/ ++ {GEN_CMD_CODE(_GetBasicRate), NULL}, ++ {GEN_CMD_CODE(_SetDataRate), NULL}, ++ {GEN_CMD_CODE(_GetDataRate), NULL}, ++ {GEN_CMD_CODE(_SetPhyInfo), NULL}, ++ ++ {GEN_CMD_CODE(_GetPhyInfo), NULL}, /*30*/ ++ {GEN_CMD_CODE(_SetPhy), NULL}, ++ {GEN_CMD_CODE(_GetPhy), NULL}, ++ {GEN_CMD_CODE(_readRssi), NULL}, ++ {GEN_CMD_CODE(_readGain), NULL}, ++ {GEN_CMD_CODE(_SetAtim), NULL}, /*35*/ ++ {GEN_CMD_CODE(_SetPwrMode), NULL}, ++ {GEN_CMD_CODE(_JoinbssRpt), NULL}, ++ {GEN_CMD_CODE(_SetRaTable), NULL}, ++ {GEN_CMD_CODE(_GetRaTable) , NULL}, ++ ++ {GEN_CMD_CODE(_GetCCXReport), NULL}, /*40*/ ++ {GEN_CMD_CODE(_GetDTMReport), NULL}, ++ {GEN_CMD_CODE(_GetTXRateStatistics), NULL}, ++ {GEN_CMD_CODE(_SetUsbSuspend), NULL}, ++ {GEN_CMD_CODE(_SetH2cLbk), NULL}, ++ {GEN_CMD_CODE(_AddBAReq), NULL}, /*45*/ ++ {GEN_CMD_CODE(_SetChannel), NULL}, /*46*/ ++ {GEN_CMD_CODE(_SetTxPower), NULL}, ++ {GEN_CMD_CODE(_SwitchAntenna), NULL}, ++ {GEN_CMD_CODE(_SetCrystalCap), NULL}, ++ {GEN_CMD_CODE(_SetSingleCarrierTx), NULL}, /*50*/ ++ ++ {GEN_CMD_CODE(_SetSingleToneTx), NULL}, /*51*/ ++ {GEN_CMD_CODE(_SetCarrierSuppressionTx), NULL}, ++ {GEN_CMD_CODE(_SetContinuousTx), NULL}, ++ {GEN_CMD_CODE(_SwitchBandwidth), NULL}, /*54*/ ++ {GEN_CMD_CODE(_TX_Beacon), NULL},/*55*/ ++ ++ {GEN_CMD_CODE(_Set_MLME_EVT), NULL},/*56*/ ++ {GEN_CMD_CODE(_Set_Drv_Extra), NULL},/*57*/ ++ {GEN_CMD_CODE(_Set_H2C_MSG), NULL},/*58*/ ++ {GEN_CMD_CODE(_SetChannelPlan), NULL},/*59*/ ++ {GEN_CMD_CODE(_LedBlink), NULL},/*60*/ ++ {GEN_CMD_CODE(_SetChannelSwitch), NULL},/*61*/ ++ {GEN_CMD_CODE(_TDLS), NULL},/*62*/ ++}; ++#endif ++ ++#endif // _CMD_H_ ++ +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/include/rtw_debug.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/include/rtw_debug.h 2013-07-26 19:36:06.000000000 +0000 +@@ -0,0 +1,383 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef __RTW_DEBUG_H__ ++#define __RTW_DEBUG_H__ ++ ++#include ++#include ++#include ++ ++ ++#define _drv_emerg_ 1 ++#define _drv_alert_ 2 ++#define _drv_crit_ 3 ++#define _drv_err_ 4 ++#define _drv_warning_ 5 ++#define _drv_notice_ 6 ++#define _drv_info_ 7 ++#define _drv_dump_ 8 ++#define _drv_debug_ 9 ++ ++ ++#define _module_rtl871x_xmit_c_ BIT(0) ++#define _module_xmit_osdep_c_ BIT(1) ++#define _module_rtl871x_recv_c_ BIT(2) ++#define _module_recv_osdep_c_ BIT(3) ++#define _module_rtl871x_mlme_c_ BIT(4) ++#define _module_mlme_osdep_c_ BIT(5) ++#define _module_rtl871x_sta_mgt_c_ BIT(6) ++#define _module_rtl871x_cmd_c_ BIT(7) ++#define _module_cmd_osdep_c_ BIT(8) ++#define _module_rtl871x_io_c_ BIT(9) ++#define _module_io_osdep_c_ BIT(10) ++#define _module_os_intfs_c_ BIT(11) ++#define _module_rtl871x_security_c_ BIT(12) ++#define _module_rtl871x_eeprom_c_ BIT(13) ++#define _module_hal_init_c_ BIT(14) ++#define _module_hci_hal_init_c_ BIT(15) ++#define _module_rtl871x_ioctl_c_ BIT(16) ++#define _module_rtl871x_ioctl_set_c_ BIT(17) ++#define _module_rtl871x_ioctl_query_c_ BIT(18) ++#define _module_rtl871x_pwrctrl_c_ BIT(19) ++#define _module_hci_intfs_c_ BIT(20) ++#define _module_hci_ops_c_ BIT(21) ++#define _module_osdep_service_c_ BIT(22) ++#define _module_mp_ BIT(23) ++#define _module_hci_ops_os_c_ BIT(24) ++#define _module_rtl871x_ioctl_os_c BIT(25) ++#define _module_rtl8712_cmd_c_ BIT(26) ++//#define _module_efuse_ BIT(27) ++#define _module_rtl8192c_xmit_c_ BIT(28) ++#define _module_efuse_ BIT(29) ++#define _module_rtl8712_recv_c_ BIT(30) ++#define _module_rtl8712_led_c_ BIT(31) ++ ++#undef _MODULE_DEFINE_ ++ ++#if defined _RTL871X_XMIT_C_ ++ #define _MODULE_DEFINE_ _module_rtl871x_xmit_c_ ++#elif defined _XMIT_OSDEP_C_ ++ #define _MODULE_DEFINE_ _module_xmit_osdep_c_ ++#elif defined _RTL871X_RECV_C_ ++ #define _MODULE_DEFINE_ _module_rtl871x_recv_c_ ++#elif defined _RECV_OSDEP_C_ ++ #define _MODULE_DEFINE_ _module_recv_osdep_c_ ++#elif defined _RTL871X_MLME_C_ ++ #define _MODULE_DEFINE_ _module_rtl871x_mlme_c_ ++#elif defined _MLME_OSDEP_C_ ++ #define _MODULE_DEFINE_ _module_mlme_osdep_c_ ++#elif defined _RTL871X_STA_MGT_C_ ++ #define _MODULE_DEFINE_ _module_rtl871x_sta_mgt_c_ ++#elif defined _RTL871X_CMD_C_ ++ #define _MODULE_DEFINE_ _module_rtl871x_cmd_c_ ++#elif defined _CMD_OSDEP_C_ ++ #define _MODULE_DEFINE_ _module_cmd_osdep_c_ ++#elif defined _RTL871X_IO_C_ ++ #define _MODULE_DEFINE_ _module_rtl871x_io_c_ ++#elif defined _IO_OSDEP_C_ ++ #define _MODULE_DEFINE_ _module_io_osdep_c_ ++#elif defined _OS_INTFS_C_ ++ #define _MODULE_DEFINE_ _module_os_intfs_c_ ++#elif defined _RTL871X_SECURITY_C_ ++ #define _MODULE_DEFINE_ _module_rtl871x_security_c_ ++#elif defined _RTL871X_EEPROM_C_ ++ #define _MODULE_DEFINE_ _module_rtl871x_eeprom_c_ ++#elif defined _HAL_INIT_C_ ++ #define _MODULE_DEFINE_ _module_hal_init_c_ ++#elif defined _HCI_HAL_INIT_C_ ++ #define _MODULE_DEFINE_ _module_hci_hal_init_c_ ++#elif defined _RTL871X_IOCTL_C_ ++ #define _MODULE_DEFINE_ _module_rtl871x_ioctl_c_ ++#elif defined _RTL871X_IOCTL_SET_C_ ++ #define _MODULE_DEFINE_ _module_rtl871x_ioctl_set_c_ ++#elif defined _RTL871X_IOCTL_QUERY_C_ ++ #define _MODULE_DEFINE_ _module_rtl871x_ioctl_query_c_ ++#elif defined _RTL871X_PWRCTRL_C_ ++ #define _MODULE_DEFINE_ _module_rtl871x_pwrctrl_c_ ++#elif defined _HCI_INTF_C_ ++ #define _MODULE_DEFINE_ _module_hci_intfs_c_ ++#elif defined _HCI_OPS_C_ ++ #define _MODULE_DEFINE_ _module_hci_ops_c_ ++#elif defined _OSDEP_HCI_INTF_C_ ++ #define _MODULE_DEFINE_ _module_hci_intfs_c_ ++#elif defined _OSDEP_SERVICE_C_ ++ #define _MODULE_DEFINE_ _module_osdep_service_c_ ++#elif defined _HCI_OPS_OS_C_ ++ #define _MODULE_DEFINE_ _module_hci_ops_os_c_ ++#elif defined _RTL871X_IOCTL_LINUX_C_ ++ #define _MODULE_DEFINE_ _module_rtl871x_ioctl_os_c ++#elif defined _RTL8712_CMD_C_ ++ #define _MODULE_DEFINE_ _module_rtl8712_cmd_c_ ++#elif defined _RTL8192C_XMIT_C_ ++ #define _MODULE_DEFINE_ _module_rtl8192c_xmit_c_ ++#elif defined _RTL8712_RECV_C_ ++ #define _MODULE_DEFINE_ _module_rtl8712_recv_c_ ++#elif defined _RTL8192CU_RECV_C_ ++ #define _MODULE_DEFINE_ _module_rtl8712_recv_c_ ++#elif defined _RTL871X_MLME_EXT_C_ ++ #define _MODULE_DEFINE_ _module_mlme_osdep_c_ ++#elif defined _RTW_MP_C_ ++ #define _MODULE_DEFINE_ _module_mp_ ++#elif defined _RTW_MP_IOCTL_C_ ++ #define _MODULE_DEFINE_ _module_mp_ ++#elif defined _RTW_EFUSE_C_ ++ #define _MODULE_DEFINE_ _module_efuse_ ++#endif ++ ++#ifdef PLATFORM_OS_CE ++extern void rtl871x_cedbg(const char *fmt, ...); ++#endif ++ ++#define RT_TRACE(_Comp, _Level, Fmt) do{}while(0) ++#define _func_enter_ do{}while(0) ++#define _func_exit_ do{}while(0) ++#define RT_PRINT_DATA(_Comp, _Level, _TitleString, _HexData, _HexDataLen) do{}while(0) ++ ++#undef _dbgdump ++ ++#ifdef CONFIG_DEBUG_RTL871X ++ ++#ifndef _RTL871X_DEBUG_C_ ++ extern u32 GlobalDebugLevel; ++ extern u64 GlobalDebugComponents; ++#endif ++ ++#ifdef PLATFORM_WINDOWS ++ ++ #ifdef PLATFORM_OS_XP ++ ++ #define _dbgdump DbgPrint ++ ++ #elif defined PLATFORM_OS_CE ++ ++ #define _dbgdump rtl871x_cedbg ++ ++ #endif ++ ++ #elif defined PLATFORM_LINUX ++ ++ #define _dbgdump printk ++ ++#endif ++ ++#endif /* CONFIG_DEBUG_RTL871X */ ++ ++ ++#if defined (_dbgdump) && defined (_MODULE_DEFINE_) ++ ++ #undef RT_TRACE ++ #define RT_TRACE(_Comp, _Level, Fmt)\ ++ do {\ ++ if((_Comp & GlobalDebugComponents) && (_Level <= GlobalDebugLevel)) {\ ++ _dbgdump("%s [0x%08x,%d]", RTL871X_MODULE_NAME, (unsigned int)_Comp, _Level);\ ++ _dbgdump Fmt; \ ++ }\ ++ }while(0) ++ ++#endif ++ ++ ++#if defined (_dbgdump) ++ ++ #undef _func_enter_ ++ #define _func_enter_ \ ++ do { \ ++ if (GlobalDebugLevel >= _drv_debug_) \ ++ { \ ++ _dbgdump("\n %s : %s enters at %d\n", RTL871X_MODULE_NAME, __FUNCTION__, __LINE__);\ ++ } \ ++ } while(0) ++ ++ #undef _func_exit_ ++ #define _func_exit_ \ ++ do { \ ++ if (GlobalDebugLevel >= _drv_debug_) \ ++ { \ ++ _dbgdump("\n %s : %s exits at %d\n", RTL871X_MODULE_NAME, __FUNCTION__, __LINE__); \ ++ } \ ++ } while(0) ++ ++ #undef RT_PRINT_DATA ++ #define RT_PRINT_DATA(_Comp, _Level, _TitleString, _HexData, _HexDataLen) \ ++ if(((_Comp) & GlobalDebugComponents) && (_Level <= GlobalDebugLevel)) \ ++ { \ ++ int __i; \ ++ u8 *ptr = (u8 *)_HexData; \ ++ _dbgdump("Rtl871x: "); \ ++ _dbgdump(_TitleString); \ ++ for( __i=0; __i<(int)_HexDataLen; __i++ ) \ ++ { \ ++ _dbgdump("%02X%s", ptr[__i], (((__i + 1) % 4) == 0)?" ":" "); \ ++ if (((__i + 1) % 16) == 0) _dbgdump("\n"); \ ++ } \ ++ _dbgdump("\n"); \ ++ } ++#endif ++ ++ ++#ifdef CONFIG_DEBUG_RTL819X ++ #ifdef PLATFORM_WINDOWS ++ ++ #ifdef PLATFORM_OS_XP ++ #define _dbgdump DbgPrint ++ ++ #elif defined PLATFORM_OS_CE ++ #define _dbgdump rtl871x_cedbg ++ ++ #endif ++ ++ #elif defined PLATFORM_LINUX ++ #define _dbgdump printk ++ #endif ++#endif ++ ++#ifdef PLATFORM_WINDOWS ++ #define DBG_871X do {} while(0) ++ #define MSG_8192C do {} while(0) ++ #define DBG_8192C do {} while(0) ++ #define WRN_8192C do {} while(0) ++ #define ERR_8192C do {} while(0) ++#endif ++ ++#ifdef PLATFORM_LINUX ++ #define DBG_871X(x, ...) do {} while(0) ++ #define MSG_8192C(x, ...) do {} while(0) ++ #define DBG_8192C(x,...) do {} while(0) ++ #define WRN_8192C(x,...) do {} while(0) ++ #define ERR_8192C(x,...) do {} while(0) ++#endif ++ ++#if defined (_dbgdump) ++ #undef DBG_871X ++ #define DBG_871X _dbgdump ++ ++ #undef MSG_8192C ++ #define MSG_8192C _dbgdump ++ ++ #undef DBG_8192C ++ #define DBG_8192C _dbgdump ++ ++ #undef WRN_8192C ++ #define WRN_8192C _dbgdump ++ ++ #undef ERR_8192C ++ #define ERR_8192C _dbgdump ++#endif ++ ++ ++ ++#ifdef CONFIG_PROC_DEBUG ++ ++ int proc_get_drv_version(char *page, char **start, ++ off_t offset, int count, ++ int *eof, void *data); ++ ++ int proc_get_write_reg(char *page, char **start, ++ off_t offset, int count, ++ int *eof, void *data); ++ ++ int proc_set_write_reg(struct file *file, const char *buffer, ++ unsigned long count, void *data); ++ ++ int proc_get_read_reg(char *page, char **start, ++ off_t offset, int count, ++ int *eof, void *data); ++ ++ int proc_set_read_reg(struct file *file, const char *buffer, ++ unsigned long count, void *data); ++ ++ ++ int proc_get_fwstate(char *page, char **start, ++ off_t offset, int count, ++ int *eof, void *data); ++ ++ int proc_get_sec_info(char *page, char **start, ++ off_t offset, int count, ++ int *eof, void *data); ++ ++ int proc_get_mlmext_state(char *page, char **start, ++ off_t offset, int count, ++ int *eof, void *data); ++ ++ int proc_get_qos_option(char *page, char **start, ++ off_t offset, int count, ++ int *eof, void *data); ++ ++ int proc_get_ht_option(char *page, char **start, ++ off_t offset, int count, ++ int *eof, void *data); ++ ++ int proc_get_rf_info(char *page, char **start, ++ off_t offset, int count, ++ int *eof, void *data); ++ ++ int proc_get_ap_info(char *page, char **start, ++ off_t offset, int count, ++ int *eof, void *data); ++ ++ int proc_get_adapter_state(char *page, char **start, ++ off_t offset, int count, ++ int *eof, void *data); ++ ++ int proc_get_trx_info(char *page, char **start, ++ off_t offset, int count, ++ int *eof, void *data); ++ ++ ++#ifdef CONFIG_AP_MODE ++ ++ int proc_get_all_sta_info(char *page, char **start, ++ off_t offset, int count, ++ int *eof, void *data); ++ ++#endif ++ ++#ifdef DBG_MEMORY_LEAK ++ int proc_get_malloc_cnt(char *page, char **start, ++ off_t offset, int count, ++ int *eof, void *data); ++#endif ++ ++#ifdef CONFIG_FIND_BEST_CHANNEL ++ int proc_get_best_channel(char *page, char **start, ++ off_t offset, int count, ++ int *eof, void *data); ++#endif ++ ++ int proc_get_rx_signal(char *page, char **start, ++ off_t offset, int count, ++ int *eof, void *data); ++ ++ int proc_set_rx_signal(struct file *file, const char *buffer, ++ unsigned long count, void *data); ++ ++ ++ int proc_get_rssi_disp(char *page, char **start, ++ off_t offset, int count, ++ int *eof, void *data); ++ ++ int proc_set_rssi_disp(struct file *file, const char *buffer, ++ unsigned long count, void *data); ++ ++ ++#endif //CONFIG_PROC_DEBUG ++ ++#endif //__RTW_DEBUG_H__ ++ +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/include/rtw_eeprom.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/include/rtw_eeprom.h 2013-07-26 19:36:06.000000000 +0000 +@@ -0,0 +1,153 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ++******************************************************************************/ ++#ifndef __RTW_EEPROM_H__ ++#define __RTW_EEPROM_H__ ++ ++#include ++#include ++#include ++ ++#define RTL8712_EEPROM_ID 0x8712 ++#define EEPROM_MAX_SIZE 256 ++#define CLOCK_RATE 50 //100us ++ ++//- EEPROM opcodes ++#define EEPROM_READ_OPCODE 06 ++#define EEPROM_WRITE_OPCODE 05 ++#define EEPROM_ERASE_OPCODE 07 ++#define EEPROM_EWEN_OPCODE 19 // Erase/write enable ++#define EEPROM_EWDS_OPCODE 16 // Erase/write disable ++ ++//Country codes ++#define USA 0x555320 ++#define EUROPE 0x1 //temp, should be provided later ++#define JAPAN 0x2 //temp, should be provided later ++ ++#ifdef CONFIG_SDIO_HCI ++#define eeprom_cis0_sz 17 ++#define eeprom_cis1_sz 50 ++#endif ++ ++#define EEPROM_CID_DEFAULT 0x0 ++#define EEPROM_CID_ALPHA 0x1 ++#define EEPROM_CID_Senao 0x3 ++#define EEPROM_CID_NetCore 0x5 ++#define EEPROM_CID_CAMEO 0X8 ++#define EEPROM_CID_SITECOM 0x9 ++#define EEPROM_CID_COREGA 0xB ++#define EEPROM_CID_EDIMAX_BELKIN 0xC ++#define EEPROM_CID_SERCOMM_BELKIN 0xE ++#define EEPROM_CID_CAMEO1 0xF ++#define EEPROM_CID_WNC_COREGA 0x12 ++#define EEPROM_CID_CLEVO 0x13 ++#define EEPROM_CID_WHQL 0xFE // added by chiyoko for dtm, 20090108 ++ ++// ++// Customer ID, note that: ++// This variable is initiailzed through EEPROM or registry, ++// however, its definition may be different with that in EEPROM for ++// EEPROM size consideration. So, we have to perform proper translation between them. ++// Besides, CustomerID of registry has precedence of that of EEPROM. ++// defined below. 060703, by rcnjko. ++// ++typedef enum _RT_CUSTOMER_ID ++{ ++ RT_CID_DEFAULT = 0, ++ RT_CID_8187_ALPHA0 = 1, ++ RT_CID_8187_SERCOMM_PS = 2, ++ RT_CID_8187_HW_LED = 3, ++ RT_CID_8187_NETGEAR = 4, ++ RT_CID_WHQL = 5, ++ RT_CID_819x_CAMEO = 6, ++ RT_CID_819x_RUNTOP = 7, ++ RT_CID_819x_Senao = 8, ++ RT_CID_TOSHIBA = 9, // Merge by Jacken, 2008/01/31. ++ RT_CID_819x_Netcore = 10, ++ RT_CID_Nettronix = 11, ++ RT_CID_DLINK = 12, ++ RT_CID_PRONET = 13, ++ RT_CID_COREGA = 14, ++ RT_CID_CHINA_MOBILE = 15, ++ RT_CID_819x_ALPHA = 16, ++ RT_CID_819x_Sitecom = 17, ++ RT_CID_CCX = 18, // It's set under CCX logo test and isn't demanded for CCX functions, but for test behavior like retry limit and tx report. By Bruce, 2009-02-17. ++ RT_CID_819x_Lenovo = 19, ++ RT_CID_819x_QMI = 20, ++ RT_CID_819x_Edimax_Belkin = 21, ++ RT_CID_819x_Sercomm_Belkin = 22, ++ RT_CID_819x_CAMEO1 = 23, ++ RT_CID_819x_MSI = 24, ++ RT_CID_819x_Acer = 25, ++ RT_CID_819x_AzWave_ASUS = 26, ++ RT_CID_819x_AzWave = 27, // For AzWave in PCIe, The ID is AzWave use and not only Asus ++ RT_CID_819x_HP = 28, ++ RT_CID_819x_WNC_COREGA = 29, ++ RT_CID_819x_Arcadyan_Belkin = 30, ++ RT_CID_819x_SAMSUNG = 31, ++ RT_CID_819x_CLEVO = 32, ++ RT_CID_819x_DELL = 33, ++ RT_CID_819x_PRONETS = 34, ++ RT_CID_819x_Edimax_ASUS = 35, ++ RT_CID_819x_CAMEO_NETGEAR = 36, ++}RT_CUSTOMER_ID, *PRT_CUSTOMER_ID; ++ ++struct eeprom_priv ++{ ++ u8 bautoload_fail_flag; ++ //u8 bempty; ++ //u8 sys_config; ++ u8 mac_addr[6]; //PermanentAddress ++ //u8 config0; ++ u16 channel_plan; ++ //u8 country_string[3]; ++ //u8 tx_power_b[15]; ++ //u8 tx_power_g[15]; ++ //u8 tx_power_a[201]; ++ ++ u8 EepromOrEfuse; ++ ++ u8 efuse_eeprom_data[EEPROM_MAX_SIZE]; ++ ++#ifdef CONFIG_SDIO_HCI ++ u8 sdio_setting; ++ u32 ocr; ++ u8 cis0[eeprom_cis0_sz]; ++ u8 cis1[eeprom_cis1_sz]; ++#endif ++}; ++ ++ ++extern void eeprom_write16(_adapter *padapter, u16 reg, u16 data); ++extern u16 eeprom_read16(_adapter *padapter, u16 reg); ++extern void read_eeprom_content(_adapter *padapter); ++extern void eeprom_read_sz(_adapter * padapter, u16 reg,u8* data, u32 sz); ++ ++extern void read_eeprom_content_by_attrib(_adapter * padapter ); ++ ++#ifdef PLATFORM_LINUX ++#ifdef CONFIG_ADAPTOR_INFO_CACHING_FILE ++extern int isAdaptorInfoFileValid(void); ++extern int storeAdaptorInfoFile(char *path, struct eeprom_priv * eeprom_priv); ++extern int retriveAdaptorInfoFile(char *path, struct eeprom_priv * eeprom_priv); ++#endif //CONFIG_ADAPTOR_INFO_CACHING_FILE ++#endif //PLATFORM_LINUX ++ ++#endif //__RTL871X_EEPROM_H__ +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/include/rtw_efuse.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/include/rtw_efuse.h 2013-07-26 19:36:06.000000000 +0000 +@@ -0,0 +1,123 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef __RTW_EFUSE_H__ ++#define __RTW_EFUSE_H__ ++ ++#include ++#include ++ ++#define EFUSE_ERROE_HANDLE 1 ++ ++#define PG_STATE_HEADER 0x01 ++#define PG_STATE_WORD_0 0x02 ++#define PG_STATE_WORD_1 0x04 ++#define PG_STATE_WORD_2 0x08 ++#define PG_STATE_WORD_3 0x10 ++#define PG_STATE_DATA 0x20 ++ ++#define PG_SWBYTE_H 0x01 ++#define PG_SWBYTE_L 0x02 ++ ++#define PGPKT_DATA_SIZE 8 ++ ++#define EFUSE_WIFI 0 ++#define EFUSE_BT 1 ++ ++enum _EFUSE_DEF_TYPE { ++ TYPE_EFUSE_MAX_SECTION = 0, ++ TYPE_EFUSE_REAL_CONTENT_LEN = 1, ++ TYPE_AVAILABLE_EFUSE_BYTES_BANK = 2, ++ TYPE_AVAILABLE_EFUSE_BYTES_TOTAL = 3, ++ TYPE_EFUSE_MAP_LEN = 4, ++ TYPE_EFUSE_PROTECT_BYTES_BANK = 5, ++}; ++ ++#define EFUSE_MAX_MAP_LEN 256 ++#define EFUSE_MAX_HW_SIZE 512 ++#define EFUSE_MAX_SECTION_BASE 16 ++ ++#define EXT_HEADER(header) ((header & 0x1F ) == 0x0F) ++#define ALL_WORDS_DISABLED(wde) ((wde & 0x0F) == 0x0F) ++#define GET_HDR_OFFSET_2_0(header) ( (header & 0xE0) >> 5) ++ ++#define EFUSE_REPEAT_THRESHOLD_ 3 ++ ++//============================================= ++// The following is for BT Efuse definition ++//============================================= ++#define EFUSE_BT_MAX_MAP_LEN 1024 ++#define EFUSE_MAX_BANK 4 ++#define EFUSE_MAX_BT_BANK (EFUSE_MAX_BANK-1) ++//============================================= ++/*--------------------------Define Parameters-------------------------------*/ ++#define EFUSE_MAX_WORD_UNIT 4 ++ ++/*------------------------------Define structure----------------------------*/ ++typedef struct PG_PKT_STRUCT_A{ ++ u8 offset; ++ u8 word_en; ++ u8 data[8]; ++ u8 word_cnts; ++}PGPKT_STRUCT,*PPGPKT_STRUCT; ++/*------------------------------Define structure----------------------------*/ ++ ++ ++/*------------------------Export global variable----------------------------*/ ++extern u8 fakeEfuseBank; ++extern u32 fakeEfuseUsedBytes; ++extern u8 fakeEfuseContent[]; ++extern u8 fakeEfuseInitMap[]; ++extern u8 fakeEfuseModifiedMap[]; ++ ++extern u32 BTEfuseUsedBytes; ++extern u8 BTEfuseContent[EFUSE_MAX_BT_BANK][EFUSE_MAX_HW_SIZE]; ++extern u8 BTEfuseInitMap[]; ++extern u8 BTEfuseModifiedMap[]; ++ ++extern u32 fakeBTEfuseUsedBytes; ++extern u8 fakeBTEfuseContent[EFUSE_MAX_BT_BANK][EFUSE_MAX_HW_SIZE]; ++extern u8 fakeBTEfuseInitMap[]; ++extern u8 fakeBTEfuseModifiedMap[]; ++/*------------------------Export global variable----------------------------*/ ++ ++u8 efuse_GetCurrentSize(PADAPTER padapter, u16 *size); ++u16 efuse_GetMaxSize(PADAPTER padapter); ++u8 rtw_efuse_access(PADAPTER padapter, u8 bRead, u16 start_addr, u16 cnts, u8 *data); ++u8 rtw_efuse_map_read(PADAPTER padapter, u16 addr, u16 cnts, u8 *data); ++u8 rtw_efuse_map_write(PADAPTER padapter, u16 addr, u16 cnts, u8 *data); ++ ++u16 Efuse_GetCurrentSize(PADAPTER pAdapter, u8 efuseType, BOOLEAN bPseudoTest); ++u8 Efuse_CalculateWordCnts(u8 word_en); ++void ReadEFuseByte(PADAPTER Adapter, u16 _offset, u8 *pbuf, BOOLEAN bPseudoTest) ; ++void EFUSE_GetEfuseDefinition(PADAPTER pAdapter, u8 efuseType, u8 type, PVOID *pOut, BOOLEAN bPseudoTest); ++u8 efuse_OneByteRead(PADAPTER pAdapter, u16 addr, u8 *data, BOOLEAN bPseudoTest); ++u8 efuse_OneByteWrite(PADAPTER pAdapter, u16 addr, u8 data, BOOLEAN bPseudoTest); ++ ++void Efuse_PowerSwitch(PADAPTER pAdapter,u8 bWrite,u8 PwrState); ++int Efuse_PgPacketRead(PADAPTER pAdapter, u8 offset, u8 *data, BOOLEAN bPseudoTest); ++int Efuse_PgPacketWrite(PADAPTER pAdapter, u8 offset, u8 word_en, u8 *data, BOOLEAN bPseudoTest); ++void efuse_WordEnableDataRead(u8 word_en, u8 *sourdata, u8 *targetdata); ++u8 Efuse_WordEnableDataWrite(PADAPTER pAdapter, u16 efuse_addr, u8 word_en, u8 *data, BOOLEAN bPseudoTest); ++ ++u8 EFUSE_Read1Byte(PADAPTER pAdapter, u16 Address); ++void EFUSE_ShadowMapUpdate(PADAPTER pAdapter, u8 efuseType, BOOLEAN bPseudoTest); ++void EFUSE_ShadowRead(PADAPTER pAdapter, u8 Type, u16 Offset, u32 *Value); ++ ++#endif +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/include/rtw_event.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/include/rtw_event.h 2013-07-26 19:36:06.000000000 +0000 +@@ -0,0 +1,154 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ++******************************************************************************/ ++#ifndef _RTW_EVENT_H_ ++#define _RTW_EVENT_H_ ++#include ++#include ++ ++#ifndef CONFIG_RTL8711FW ++#ifdef PLATFORM_LINUX ++#include ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,26)) ++#include ++#else ++#include ++#endif ++#include ++#endif ++#else ++#include ++#endif//CONFIG_RTL8711FW ++ ++ ++ ++#ifdef CONFIG_H2CLBK ++#include ++#endif ++ ++/* ++Used to report a bss has been scanned ++ ++*/ ++struct survey_event { ++ WLAN_BSSID_EX bss; ++}; ++ ++/* ++Used to report that the requested site survey has been done. ++ ++bss_cnt indicates the number of bss that has been reported. ++ ++ ++*/ ++struct surveydone_event { ++ unsigned int bss_cnt; ++ ++}; ++ ++/* ++Used to report the link result of joinning the given bss ++ ++ ++join_res: ++-1: authentication fail ++-2: association fail ++> 0: TID ++ ++*/ ++struct joinbss_event { ++ struct wlan_network network; ++}; ++ ++/* ++Used to report a given STA has joinned the created BSS. ++It is used in AP/Ad-HoC(M) mode. ++ ++ ++*/ ++struct stassoc_event { ++ unsigned char macaddr[6]; ++ unsigned char rsvd[2]; ++ int cam_id; ++ ++}; ++ ++struct stadel_event { ++ unsigned char macaddr[6]; ++ unsigned char rsvd[2]; ++}; ++ ++struct addba_event ++{ ++ unsigned int tid; ++}; ++ ++ ++#ifdef CONFIG_H2CLBK ++struct c2hlbk_event{ ++ unsigned char mac[6]; ++ unsigned short s0; ++ unsigned short s1; ++ unsigned int w0; ++ unsigned char b0; ++ unsigned short s2; ++ unsigned char b1; ++ unsigned int w1; ++}; ++#endif//CONFIG_H2CLBK ++ ++#define GEN_EVT_CODE(event) event ## _EVT_ ++ ++ ++ ++struct fwevent { ++ u32 parmsize; ++ void (*event_callback)(_adapter *dev, u8 *pbuf); ++}; ++ ++ ++#define C2HEVENT_SZ 32 ++ ++struct event_node{ ++ unsigned char *node; ++ unsigned char evt_code; ++ unsigned short evt_sz; ++ volatile int *caller_ff_tail; ++ int caller_ff_sz; ++}; ++ ++struct c2hevent_queue { ++ volatile int head; ++ volatile int tail; ++ struct event_node nodes[C2HEVENT_SZ]; ++ unsigned char seq; ++}; ++ ++#define NETWORK_QUEUE_SZ 4 ++ ++struct network_queue { ++ volatile int head; ++ volatile int tail; ++ WLAN_BSSID_EX networks[NETWORK_QUEUE_SZ]; ++}; ++ ++ ++#endif // _WLANEVENT_H_ ++ +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/include/rtw_ht.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/include/rtw_ht.h 2013-07-26 19:36:06.000000000 +0000 +@@ -0,0 +1,51 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ++******************************************************************************/ ++#ifndef _RTW_HT_H_ ++#define _RTW_HT_H_ ++ ++#include ++#include ++#include "wifi.h" ++ ++struct ht_priv ++{ ++ u32 ht_option; ++ u32 ampdu_enable;//for enable Tx A-MPDU ++ //u8 baddbareq_issued[16]; ++ u32 tx_amsdu_enable;//for enable Tx A-MSDU ++ u32 tx_amdsu_maxlen; // 1: 8k, 0:4k ; default:8k, for tx ++ u32 rx_ampdu_maxlen; //for rx reordering ctrl win_sz, updated when join_callback. ++ ++ u8 bwmode;// ++ u8 ch_offset;//PRIME_CHNL_OFFSET ++ u8 sgi;//short GI ++ ++ //for processing Tx A-MPDU ++ u8 agg_enable_bitmap; ++ //u8 ADDBA_retry_count; ++ u8 candidate_tid_bitmap; ++ ++ struct rtw_ieee80211_ht_cap ht_cap; ++ ++}; ++ ++#endif //_RTL871X_HT_H_ ++ +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/include/rtw_io.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/include/rtw_io.h 2013-07-26 19:36:06.000000000 +0000 +@@ -0,0 +1,543 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ++******************************************************************************/ ++#ifndef _RTW_IO_H_ ++#define _RTW_IO_H_ ++ ++#include ++#include ++#include ++ ++#ifdef PLATFORM_LINUX ++#include ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,26)) ++#include ++#else ++#include ++#endif ++#include ++//#include ++#include ++#include ++ ++#ifdef CONFIG_USB_HCI ++#include ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,21)) ++#include ++#else ++#include ++#endif ++ ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,35)) ++#define rtw_usb_buffer_alloc(dev, size, mem_flags, dma) usb_alloc_coherent((dev), (size), (mem_flags), (dma)) ++#define rtw_usb_buffer_free(dev, size, addr, dma) usb_free_coherent((dev), (size), (addr), (dma)) ++#else ++#define rtw_usb_buffer_alloc(dev, size, mem_flags, dma) usb_buffer_alloc((dev), (size), (mem_flags), (dma)) ++#define rtw_usb_buffer_free(dev, size, addr, dma) usb_buffer_free((dev), (size), (addr), (dma)) ++#endif ++ ++ ++#endif //CONFIG_USB_HCI ++ ++#endif //PLATFORM_LINUX ++ ++ ++#define NUM_IOREQ 8 ++ ++#ifdef PLATFORM_WINDOWS ++#define MAX_PROT_SZ 64 ++#endif ++#ifdef PLATFORM_LINUX ++#define MAX_PROT_SZ (64-16) ++#endif ++ ++#define _IOREADY 0 ++#define _IO_WAIT_COMPLETE 1 ++#define _IO_WAIT_RSP 2 ++ ++// IO COMMAND TYPE ++#define _IOSZ_MASK_ (0x7F) ++#define _IO_WRITE_ BIT(7) ++#define _IO_FIXED_ BIT(8) ++#define _IO_BURST_ BIT(9) ++#define _IO_BYTE_ BIT(10) ++#define _IO_HW_ BIT(11) ++#define _IO_WORD_ BIT(12) ++#define _IO_SYNC_ BIT(13) ++#define _IO_CMDMASK_ (0x1F80) ++ ++ ++/* ++ For prompt mode accessing, caller shall free io_req ++ Otherwise, io_handler will free io_req ++*/ ++ ++ ++ ++// IO STATUS TYPE ++#define _IO_ERR_ BIT(2) ++#define _IO_SUCCESS_ BIT(1) ++#define _IO_DONE_ BIT(0) ++ ++ ++#define IO_RD32 (_IO_SYNC_ | _IO_WORD_) ++#define IO_RD16 (_IO_SYNC_ | _IO_HW_) ++#define IO_RD8 (_IO_SYNC_ | _IO_BYTE_) ++ ++#define IO_RD32_ASYNC (_IO_WORD_) ++#define IO_RD16_ASYNC (_IO_HW_) ++#define IO_RD8_ASYNC (_IO_BYTE_) ++ ++#define IO_WR32 (_IO_WRITE_ | _IO_SYNC_ | _IO_WORD_) ++#define IO_WR16 (_IO_WRITE_ | _IO_SYNC_ | _IO_HW_) ++#define IO_WR8 (_IO_WRITE_ | _IO_SYNC_ | _IO_BYTE_) ++ ++#define IO_WR32_ASYNC (_IO_WRITE_ | _IO_WORD_) ++#define IO_WR16_ASYNC (_IO_WRITE_ | _IO_HW_) ++#define IO_WR8_ASYNC (_IO_WRITE_ | _IO_BYTE_) ++ ++/* ++ ++ Only Sync. burst accessing is provided. ++ ++*/ ++ ++#define IO_WR_BURST(x) (_IO_WRITE_ | _IO_SYNC_ | _IO_BURST_ | ( (x) & _IOSZ_MASK_)) ++#define IO_RD_BURST(x) (_IO_SYNC_ | _IO_BURST_ | ( (x) & _IOSZ_MASK_)) ++ ++ ++ ++//below is for the intf_option bit defition... ++ ++#define _INTF_ASYNC_ BIT(0) //support async io ++ ++struct intf_priv; ++struct intf_hdl; ++struct io_queue; ++ ++struct _io_ops { ++ ++ ++ uint (*_sdbus_read_bytes_to_membuf)(struct intf_priv *pintfpriv, u32 addr, u32 cnt, u8 *pbuf); ++ uint (*_sdbus_read_blocks_to_membuf)(struct intf_priv *pintfpriv, u32 addr, u32 cnt, u8 *pbuf); ++ ++ void (*_attrib_read)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem); ++ ++ u8 (*_read8)(struct intf_hdl *pintfhdl, u32 addr); ++ ++ u16 (*_read16)(struct intf_hdl *pintfhdl, u32 addr); ++ ++ u32 (*_read32)(struct intf_hdl *pintfhdl, u32 addr); ++ ++ ++ uint (*_sdbus_write_blocks_from_membuf)(struct intf_priv *pintfpriv, u32 addr, u32 cnt, u8 *pbuf,u8 async); ++ ++ uint (*_sdbus_write_bytes_from_membuf)(struct intf_priv *pintfpriv, u32 addr, u32 cnt, u8 *pbuf); ++ u8 (*_cmd52r)(struct intf_priv *pintfpriv, u32 addr); ++ void (*_cmd52w)(struct intf_priv *pintfpriv, u32 addr, u8 val8); ++ u8 (*_cmdfunc152r)(struct intf_priv *pintfpriv, u32 addr); ++ void (*_cmdfunc152w)(struct intf_priv *pintfpriv, u32 addr, u8 val8); ++ ++ ++ void (*_attrib_write)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem); ++ ++ int (*_write8)(struct intf_hdl *pintfhdl, u32 addr, u8 val); ++ ++ int (*_write16)(struct intf_hdl *pintfhdl, u32 addr, u16 val); ++ ++ int (*_write32)(struct intf_hdl *pintfhdl, u32 addr, u32 val); ++ ++ int (*_writeN)(struct intf_hdl *pintfhdl, u32 addr, u32 length, u8 *pdata); ++ ++ int (*_write8_async)(struct intf_hdl *pintfhdl, u32 addr, u8 val); ++ ++ int (*_write16_async)(struct intf_hdl *pintfhdl, u32 addr, u16 val); ++ ++ int (*_write32_async)(struct intf_hdl *pintfhdl, u32 addr, u32 val); ++ ++ ++ void (*_read_mem)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem); ++ ++ void (*_write_mem)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem); ++ ++ void (*_sync_irp_protocol_rw)(struct io_queue *pio_q); ++ ++ ++ u32 (*_read_interrupt)(struct intf_hdl *pintfhdl, u32 addr); ++ ++ u32 (*_read_port)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem); ++ ++ u32 (*_write_port)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem); ++ ++ int (*_write_port_sync)(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *pmem); ++ ++ u32 (*_write_scsi)(struct intf_hdl *pintfhdl,u32 cnt, u8 *pmem); ++ ++ ++ void (*_read_port_cancel)(struct intf_hdl *pintfhdl); ++ ++ void (*_write_port_cancel)(struct intf_hdl *pintfhdl); ++ ++}; ++ ++struct io_req { ++ _list list; ++ u32 addr; ++ volatile u32 val; ++ u32 command; ++ u32 status; ++ u8 *pbuf; ++ _sema sema; ++ ++#ifdef PLATFORM_OS_CE ++#ifdef CONFIG_USB_HCI ++ // URB handler for rtw_write_mem ++ USB_TRANSFER usb_transfer_write_mem; ++#endif ++#endif ++ ++ void (*_async_io_callback)(_adapter *padater, struct io_req *pio_req, u8 *cnxt); ++ u8 *cnxt; ++ ++#ifdef PLATFORM_OS_XP ++ PMDL pmdl; ++ PIRP pirp; ++ ++#ifdef CONFIG_SDIO_HCI ++ PSDBUS_REQUEST_PACKET sdrp; ++#endif ++ ++#endif ++ ++ ++}; ++ ++struct intf_hdl { ++ ++/* ++ u32 intf_option; ++ u32 bus_status; ++ u32 do_flush; ++ u8 *adapter; ++ u8 *intf_dev; ++ struct intf_priv *pintfpriv; ++ u8 cnt; ++ void (*intf_hdl_init)(u8 *priv); ++ void (*intf_hdl_unload)(u8 *priv); ++ void (*intf_hdl_open)(u8 *priv); ++ void (*intf_hdl_close)(u8 *priv); ++ struct _io_ops io_ops; ++ //u8 intf_status;//moved to struct intf_priv ++ u16 len; ++ u16 done_len; ++*/ ++ _adapter *padapter; ++ struct dvobj_priv *pintf_dev;// pointer to &(padapter->dvobjpriv); ++ ++ struct _io_ops io_ops; ++ ++}; ++ ++struct reg_protocol_rd { ++ ++#ifdef CONFIG_LITTLE_ENDIAN ++ ++ //DW1 ++ u32 NumOfTrans:4; ++ u32 Reserved1:4; ++ u32 Reserved2:24; ++ //DW2 ++ u32 ByteCount:7; ++ u32 WriteEnable:1; //0:read, 1:write ++ u32 FixOrContinuous:1; //0:continuous, 1: Fix ++ u32 BurstMode:1; ++ u32 Byte1Access:1; ++ u32 Byte2Access:1; ++ u32 Byte4Access:1; ++ u32 Reserved3:3; ++ u32 Reserved4:16; ++ //DW3 ++ u32 BusAddress; ++ //DW4 ++ //u32 Value; ++#else ++ ++ ++//DW1 ++ u32 Reserved1 :4; ++ u32 NumOfTrans :4; ++ ++ u32 Reserved2 :24; ++ ++ //DW2 ++ u32 WriteEnable : 1; ++ u32 ByteCount :7; ++ ++ ++ u32 Reserved3 : 3; ++ u32 Byte4Access : 1; ++ ++ u32 Byte2Access : 1; ++ u32 Byte1Access : 1; ++ u32 BurstMode :1 ; ++ u32 FixOrContinuous : 1; ++ ++ u32 Reserved4 : 16; ++ ++ //DW3 ++ u32 BusAddress; ++ ++ //DW4 ++ //u32 Value; ++ ++#endif ++ ++}; ++ ++ ++struct reg_protocol_wt { ++ ++ ++#ifdef CONFIG_LITTLE_ENDIAN ++ ++ //DW1 ++ u32 NumOfTrans:4; ++ u32 Reserved1:4; ++ u32 Reserved2:24; ++ //DW2 ++ u32 ByteCount:7; ++ u32 WriteEnable:1; //0:read, 1:write ++ u32 FixOrContinuous:1; //0:continuous, 1: Fix ++ u32 BurstMode:1; ++ u32 Byte1Access:1; ++ u32 Byte2Access:1; ++ u32 Byte4Access:1; ++ u32 Reserved3:3; ++ u32 Reserved4:16; ++ //DW3 ++ u32 BusAddress; ++ //DW4 ++ u32 Value; ++ ++#else ++ //DW1 ++ u32 Reserved1 :4; ++ u32 NumOfTrans :4; ++ ++ u32 Reserved2 :24; ++ ++ //DW2 ++ u32 WriteEnable : 1; ++ u32 ByteCount :7; ++ ++ u32 Reserved3 : 3; ++ u32 Byte4Access : 1; ++ ++ u32 Byte2Access : 1; ++ u32 Byte1Access : 1; ++ u32 BurstMode :1 ; ++ u32 FixOrContinuous : 1; ++ ++ u32 Reserved4 : 16; ++ ++ //DW3 ++ u32 BusAddress; ++ ++ //DW4 ++ u32 Value; ++ ++#endif ++ ++}; ++ ++ ++ ++/* ++Below is the data structure used by _io_handler ++ ++*/ ++ ++struct io_queue { ++ _lock lock; ++ _list free_ioreqs; ++ _list pending; //The io_req list that will be served in the single protocol read/write. ++ _list processing; ++ u8 *free_ioreqs_buf; // 4-byte aligned ++ u8 *pallocated_free_ioreqs_buf; ++ struct intf_hdl intf; ++}; ++ ++struct io_priv{ ++ ++ _adapter *padapter; ++ ++ struct intf_hdl intf; ++ ++}; ++ ++extern uint ioreq_flush(_adapter *adapter, struct io_queue *ioqueue); ++extern void sync_ioreq_enqueue(struct io_req *preq,struct io_queue *ioqueue); ++extern uint sync_ioreq_flush(_adapter *adapter, struct io_queue *ioqueue); ++ ++ ++extern uint free_ioreq(struct io_req *preq, struct io_queue *pio_queue); ++extern struct io_req *alloc_ioreq(struct io_queue *pio_q); ++ ++extern uint register_intf_hdl(u8 *dev, struct intf_hdl *pintfhdl); ++extern void unregister_intf_hdl(struct intf_hdl *pintfhdl); ++ ++extern void _rtw_attrib_read(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem); ++extern void _rtw_attrib_write(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem); ++ ++extern u8 _rtw_read8(_adapter *adapter, u32 addr); ++extern u16 _rtw_read16(_adapter *adapter, u32 addr); ++extern u32 _rtw_read32(_adapter *adapter, u32 addr); ++extern void _rtw_read_mem(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem); ++extern void _rtw_read_port(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem); ++extern void _rtw_read_port_cancel(_adapter *adapter); ++ ++ ++extern int _rtw_write8(_adapter *adapter, u32 addr, u8 val); ++extern int _rtw_write16(_adapter *adapter, u32 addr, u16 val); ++extern int _rtw_write32(_adapter *adapter, u32 addr, u32 val); ++extern int _rtw_writeN(_adapter *adapter, u32 addr, u32 length, u8 *pdata); ++ ++extern int _rtw_write8_async(_adapter *adapter, u32 addr, u8 val); ++extern int _rtw_write16_async(_adapter *adapter, u32 addr, u16 val); ++extern int _rtw_write32_async(_adapter *adapter, u32 addr, u32 val); ++ ++extern void _rtw_write_mem(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem); ++extern void _rtw_write_port(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem); ++extern int _rtw_write_port_sync(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem); ++extern void _rtw_write_port_cancel(_adapter *adapter); ++ ++#ifdef DBG_IO ++extern int dbg_rtw_write8(_adapter *adapter, u32 addr, u8 val, const char *caller, const int line); ++extern int dbg_rtw_write16(_adapter *adapter, u32 addr, u16 val, const char *caller, const int line); ++extern int dbg_rtw_write32(_adapter *adapter, u32 addr, u32 val, const char *caller, const int line); ++extern int dbg_rtw_writeN(_adapter *adapter, u32 addr ,u32 length , u8 *data, const char *caller, const int line); ++ ++#define rtw_read8(adapter, addr) _rtw_read8((adapter), (addr)) ++#define rtw_read16(adapter, addr) _rtw_read16((adapter), (addr)) ++#define rtw_read32(adapter, addr) _rtw_read32((adapter), (addr)) ++#define rtw_read_mem(adapter, addr, cnt, mem) _rtw_read_mem((adapter), (addr), (cnt), (mem)) ++#define rtw_read_port(adapter, addr, cnt, mem) _rtw_read_port((adapter), (addr), (cnt), (mem)) ++#define rtw_read_port_cancel(adapter) _rtw_read_port_cancel((adapter)) ++ ++#define DBG_IO_WRITE_SNIFF_ADDR_START 0x24 //0x4c //0x4c // the starting address to sniff ++#define DBG_IO_WRITE_SNIFF_ADDR_END 0x27 //0x4c+ 1 // the ending address to sniff ++ ++#define rtw_write8(adapter, addr, val) dbg_rtw_write8((adapter), (addr), (val), __FUNCTION__, __LINE__) ++#define rtw_write16(adapter, addr, val) dbg_rtw_write16((adapter), (addr), (val), __FUNCTION__, __LINE__) ++#define rtw_write32(adapter, addr, val) dbg_rtw_write32((adapter), (addr), (val), __FUNCTION__, __LINE__) ++#define rtw_writeN(adapter, addr, length, data) dbg_rtw_writeN((adapter), (addr), (length), (data), __FUNCTION__, __LINE__) ++ ++#define rtw_write8_async(adapter, addr, val) _rtw_write8_async((adapter), (addr), (val)) ++#define rtw_write16_async(adapter, addr, val) _rtw_write16_async((adapter), (addr), (val)) ++#define rtw_write32_async(adapter, addr, val) _rtw_write32_async((adapter), (addr), (val)) ++ ++#define rtw_write_mem(adapter, addr, cnt, mem) _rtw_write_mem((adapter), addr, cnt, mem) ++#define rtw_write_port(adapter, addr, cnt, mem) _rtw_write_port(adapter, addr, cnt, mem) ++#define rtw_write_port_sync(adapter, addr, cnt, mem) _rtw_write_port_sync((adapter), (addr), (cnt), (mem)) ++#define rtw_write_port_cancel(adapter) _rtw_write_port_cancel(adapter) ++#else //DBG_IO ++#define rtw_read8(adapter, addr) _rtw_read8((adapter), (addr)) ++#define rtw_read16(adapter, addr) _rtw_read16((adapter), (addr)) ++#define rtw_read32(adapter, addr) _rtw_read32((adapter), (addr)) ++#define rtw_read_mem(adapter, addr, cnt, mem) _rtw_read_mem((adapter), (addr), (cnt), (mem)) ++#define rtw_read_port(adapter, addr, cnt, mem) _rtw_read_port((adapter), (addr), (cnt), (mem)) ++#define rtw_read_port_cancel(adapter) _rtw_read_port_cancel((adapter)) ++ ++#define rtw_write8(adapter, addr, val) _rtw_write8((adapter), (addr), (val)) ++#define rtw_write16(adapter, addr, val) _rtw_write16((adapter), (addr), (val)) ++#define rtw_write32(adapter, addr, val) _rtw_write32((adapter), (addr), (val)) ++#define rtw_writeN(adapter, addr, length, data) _rtw_writeN((adapter), (addr), (length), (data)) ++ ++#define rtw_write8_async(adapter, addr, val) _rtw_write8_async((adapter), (addr), (val)) ++#define rtw_write16_async(adapter, addr, val) _rtw_write16_async((adapter), (addr), (val)) ++#define rtw_write32_async(adapter, addr, val) _rtw_write32_async((adapter), (addr), (val)) ++ ++#define rtw_write_mem(adapter, addr, cnt, mem) _rtw_write_mem((adapter), (addr), (cnt), (mem)) ++#define rtw_write_port(adapter, addr, cnt, mem) _rtw_write_port((adapter), (addr), (cnt), (mem)) ++#define rtw_write_port_sync(adapter, addr, cnt, mem) _rtw_write_port_sync((adapter), (addr), (cnt), (mem)) ++#define rtw_write_port_cancel(adapter) _rtw_write_port_cancel((adapter)) ++#endif //DBG_IO ++ ++extern void rtw_write_scsi(_adapter *adapter, u32 cnt, u8 *pmem); ++ ++//ioreq ++extern void ioreq_read8(_adapter *adapter, u32 addr, u8 *pval); ++extern void ioreq_read16(_adapter *adapter, u32 addr, u16 *pval); ++extern void ioreq_read32(_adapter *adapter, u32 addr, u32 *pval); ++extern void ioreq_write8(_adapter *adapter, u32 addr, u8 val); ++extern void ioreq_write16(_adapter *adapter, u32 addr, u16 val); ++extern void ioreq_write32(_adapter *adapter, u32 addr, u32 val); ++ ++ ++extern uint async_read8(_adapter *adapter, u32 addr, u8 *pbuff, ++ void (*_async_io_callback)(_adapter *padater, struct io_req *pio_req, u8 *cnxt), u8 *cnxt); ++extern uint async_read16(_adapter *adapter, u32 addr, u8 *pbuff, ++ void (*_async_io_callback)(_adapter *padater, struct io_req *pio_req, u8 *cnxt), u8 *cnxt); ++extern uint async_read32(_adapter *adapter, u32 addr, u8 *pbuff, ++ void (*_async_io_callback)(_adapter *padater, struct io_req *pio_req, u8 *cnxt), u8 *cnxt); ++ ++extern void async_read_mem(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem); ++extern void async_read_port(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem); ++ ++extern void async_write8(_adapter *adapter, u32 addr, u8 val, ++ void (*_async_io_callback)(_adapter *padater, struct io_req *pio_req, u8 *cnxt), u8 *cnxt); ++extern void async_write16(_adapter *adapter, u32 addr, u16 val, ++ void (*_async_io_callback)(_adapter *padater, struct io_req *pio_req, u8 *cnxt), u8 *cnxt); ++extern void async_write32(_adapter *adapter, u32 addr, u32 val, ++ void (*_async_io_callback)(_adapter *padater, struct io_req *pio_req, u8 *cnxt), u8 *cnxt); ++ ++extern void async_write_mem(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem); ++extern void async_write_port(_adapter *adapter, u32 addr, u32 cnt, u8 *pmem); ++ ++ ++int rtw_init_io_priv(_adapter *padapter); ++ ++ ++extern uint alloc_io_queue(_adapter *adapter); ++extern void free_io_queue(_adapter *adapter); ++extern void async_bus_io(struct io_queue *pio_q); ++extern void bus_sync_io(struct io_queue *pio_q); ++extern u32 _ioreq2rwmem(struct io_queue *pio_q); ++extern void dev_power_down(_adapter * Adapter, u8 bpwrup); ++ ++/* ++#define RTL_R8(reg) rtw_read8(padapter, reg) ++#define RTL_R16(reg) rtw_read16(padapter, reg) ++#define RTL_R32(reg) rtw_read32(padapter, reg) ++#define RTL_W8(reg, val8) rtw_write8(padapter, reg, val8) ++#define RTL_W16(reg, val16) rtw_write16(padapter, reg, val16) ++#define RTL_W32(reg, val32) rtw_write32(padapter, reg, val32) ++*/ ++ ++/* ++#define RTL_W8_ASYNC(reg, val8) rtw_write32_async(padapter, reg, val8) ++#define RTL_W16_ASYNC(reg, val16) rtw_write32_async(padapter, reg, val16) ++#define RTL_W32_ASYNC(reg, val32) rtw_write32_async(padapter, reg, val32) ++ ++#define RTL_WRITE_BB(reg, val32) phy_SetUsbBBReg(padapter, reg, val32) ++#define RTL_READ_BB(reg) phy_QueryUsbBBReg(padapter, reg) ++*/ ++ ++#endif //_RTL8711_IO_H_ +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/include/rtw_ioctl.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/include/rtw_ioctl.h 2013-07-26 19:36:06.000000000 +0000 +@@ -0,0 +1,271 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ++******************************************************************************/ ++#ifndef _RTW_IOCTL_H_ ++#define _RTW_IOCTL_H_ ++ ++#include ++#include ++#include ++ ++#ifndef OID_802_11_CAPABILITY ++ #define OID_802_11_CAPABILITY 0x0d010122 ++#endif ++ ++#ifndef OID_802_11_PMKID ++ #define OID_802_11_PMKID 0x0d010123 ++#endif ++ ++ ++// For DDK-defined OIDs ++#define OID_NDIS_SEG1 0x00010100 ++#define OID_NDIS_SEG2 0x00010200 ++#define OID_NDIS_SEG3 0x00020100 ++#define OID_NDIS_SEG4 0x01010100 ++#define OID_NDIS_SEG5 0x01020100 ++#define OID_NDIS_SEG6 0x01020200 ++#define OID_NDIS_SEG7 0xFD010100 ++#define OID_NDIS_SEG8 0x0D010100 ++#define OID_NDIS_SEG9 0x0D010200 ++#define OID_NDIS_SEG10 0x0D020200 ++ ++#define SZ_OID_NDIS_SEG1 23 ++#define SZ_OID_NDIS_SEG2 3 ++#define SZ_OID_NDIS_SEG3 6 ++#define SZ_OID_NDIS_SEG4 6 ++#define SZ_OID_NDIS_SEG5 4 ++#define SZ_OID_NDIS_SEG6 8 ++#define SZ_OID_NDIS_SEG7 7 ++#define SZ_OID_NDIS_SEG8 36 ++#define SZ_OID_NDIS_SEG9 24 ++#define SZ_OID_NDIS_SEG10 19 ++ ++// For Realtek-defined OIDs ++#define OID_MP_SEG1 0xFF871100 ++#define OID_MP_SEG2 0xFF818000 ++ ++#define OID_MP_SEG3 0xFF818700 ++#define OID_MP_SEG4 0xFF011100 ++ ++#define DEBUG_OID(dbg, str) \ ++ if((!dbg)) \ ++ { \ ++ RT_TRACE(_module_rtl871x_ioctl_c_,_drv_info_,("%s(%d): %s", __FUNCTION__, __LINE__, str)); \ ++ } ++ ++ ++enum oid_type ++{ ++ QUERY_OID, ++ SET_OID ++}; ++ ++struct oid_funs_node { ++ unsigned int oid_start; //the starting number for OID ++ unsigned int oid_end; //the ending number for OID ++ struct oid_obj_priv *node_array; ++ unsigned int array_sz; //the size of node_array ++ int query_counter; //count the number of query hits for this segment ++ int set_counter; //count the number of set hits for this segment ++}; ++ ++struct oid_par_priv ++{ ++ void *adapter_context; ++ NDIS_OID oid; ++ void* information_buf; ++ u32 information_buf_len; ++ u32* bytes_rw; ++ u32* bytes_needed; ++ enum oid_type type_of_oid; ++ u32 dbg; ++}; ++ ++struct oid_obj_priv { ++ unsigned char dbg; // 0: without OID debug message 1: with OID debug message ++ NDIS_STATUS (*oidfuns)(struct oid_par_priv *poid_par_priv); ++}; ++ ++#ifdef CONFIG_MP_INCLUDED ++static NDIS_STATUS oid_null_function(struct oid_par_priv* poid_par_priv) ++{ ++ _func_enter_; ++ _func_exit_; ++ return NDIS_STATUS_SUCCESS; ++} ++#endif ++ ++#ifdef PLATFORM_WINDOWS ++ ++int TranslateNdisPsToRtPs(IN NDIS_802_11_POWER_MODE ndisPsMode); ++ ++//OID Handler for Segment 1 ++NDIS_STATUS oid_gen_supported_list_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_gen_hardware_status_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_gen_media_supported_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_gen_media_in_use_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_gen_maximum_lookahead_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_gen_maximum_frame_size_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_gen_link_speed_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_gen_transmit_buffer_space_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_gen_receive_buffer_space_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_gen_transmit_block_size_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_gen_receive_block_size_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_gen_vendor_id_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_gen_vendor_description_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_gen_current_packet_filter_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_gen_current_lookahead_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_gen_driver_version_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_gen_maximum_total_size_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_gen_protocol_options_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_gen_mac_options_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_gen_media_connect_status_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_gen_maximum_send_packets_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_gen_vendor_driver_version_hdl(struct oid_par_priv* poid_par_priv); ++ ++ ++//OID Handler for Segment 2 ++NDIS_STATUS oid_gen_physical_medium_hdl(struct oid_par_priv* poid_par_priv); ++ ++//OID Handler for Segment 3 ++NDIS_STATUS oid_gen_xmit_ok_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_gen_rcv_ok_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_gen_xmit_error_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_gen_rcv_error_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_gen_rcv_no_buffer_hdl(struct oid_par_priv* poid_par_priv); ++ ++ ++//OID Handler for Segment 4 ++NDIS_STATUS oid_802_3_permanent_address_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_802_3_current_address_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_802_3_multicast_list_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_802_3_maximum_list_size_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_802_3_mac_options_hdl(struct oid_par_priv* poid_par_priv); ++ ++ ++ ++//OID Handler for Segment 5 ++NDIS_STATUS oid_802_3_rcv_error_alignment_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_802_3_xmit_one_collision_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_802_3_xmit_more_collisions_hdl(struct oid_par_priv* poid_par_priv); ++ ++ ++//OID Handler for Segment 6 ++NDIS_STATUS oid_802_3_xmit_deferred_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_802_3_xmit_max_collisions_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_802_3_rcv_overrun_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_802_3_xmit_underrun_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_802_3_xmit_heartbeat_failure_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_802_3_xmit_times_crs_lost_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_802_3_xmit_late_collisions_hdl(struct oid_par_priv* poid_par_priv); ++ ++ ++ ++//OID Handler for Segment 7 ++NDIS_STATUS oid_pnp_capabilities_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_pnp_set_power_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_pnp_query_power_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_pnp_add_wake_up_pattern_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_pnp_remove_wake_up_pattern_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_pnp_wake_up_pattern_list_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_pnp_enable_wake_up_hdl(struct oid_par_priv* poid_par_priv); ++ ++ ++ ++//OID Handler for Segment 8 ++NDIS_STATUS oid_802_11_bssid_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_802_11_ssid_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_802_11_infrastructure_mode_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_802_11_add_wep_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_802_11_remove_wep_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_802_11_disassociate_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_802_11_authentication_mode_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_802_11_privacy_filter_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_802_11_bssid_list_scan_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_802_11_encryption_status_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_802_11_reload_defaults_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_802_11_add_key_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_802_11_remove_key_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_802_11_association_information_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_802_11_test_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_802_11_media_stream_mode_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_802_11_capability_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_802_11_pmkid_hdl(struct oid_par_priv* poid_par_priv); ++ ++ ++ ++ ++ ++//OID Handler for Segment 9 ++NDIS_STATUS oid_802_11_network_types_supported_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_802_11_network_type_in_use_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_802_11_tx_power_level_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_802_11_rssi_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_802_11_rssi_trigger_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_802_11_fragmentation_threshold_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_802_11_rts_threshold_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_802_11_number_of_antennas_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_802_11_rx_antenna_selected_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_802_11_tx_antenna_selected_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_802_11_supported_rates_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_802_11_desired_rates_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_802_11_configuration_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_802_11_power_mode_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_802_11_bssid_list_hdl(struct oid_par_priv* poid_par_priv); ++ ++ ++//OID Handler for Segment 10 ++NDIS_STATUS oid_802_11_statistics_hdl(struct oid_par_priv* poid_par_priv); ++ ++ ++//OID Handler for Segment ED ++NDIS_STATUS oid_rt_mh_vender_id_hdl(struct oid_par_priv* poid_par_priv); ++ ++void Set_802_3_MULTICAST_LIST(ADAPTER *pAdapter, UCHAR *MCListbuf, ULONG MCListlen, BOOLEAN bAcceptAllMulticast); ++ ++#endif// end of PLATFORM_WINDOWS ++ ++ ++#ifdef PLATFORM_LINUX ++ ++extern struct iw_handler_def rtw_handlers_def; ++ ++#endif ++ ++extern NDIS_STATUS drv_query_info( ++ IN _nic_hdl MiniportAdapterContext, ++ IN NDIS_OID Oid, ++ IN void * InformationBuffer, ++ IN u32 InformationBufferLength, ++ OUT u32* BytesWritten, ++ OUT u32* BytesNeeded ++ ); ++ ++extern NDIS_STATUS drv_set_info( ++ IN _nic_hdl MiniportAdapterContext, ++ IN NDIS_OID Oid, ++ IN void * InformationBuffer, ++ IN u32 InformationBufferLength, ++ OUT u32* BytesRead, ++ OUT u32* BytesNeeded ++ ); ++ ++#endif // #ifndef __INC_CEINFO_ ++ +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/include/rtw_ioctl_query.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/include/rtw_ioctl_query.h 2013-07-26 19:36:06.000000000 +0000 +@@ -0,0 +1,37 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ++******************************************************************************/ ++#ifndef _RTW_IOCTL_QUERY_H_ ++#define _RTW_IOCTL_QUERY_H_ ++ ++#include ++#include ++ ++ ++#ifdef PLATFORM_WINDOWS ++ ++u8 query_802_11_capability(_adapter* padapter,u8* pucBuf,u32 * pulOutLen); ++u8 query_802_11_association_information (_adapter * padapter, PNDIS_802_11_ASSOCIATION_INFORMATION pAssocInfo); ++ ++#endif ++ ++ ++#endif ++ +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/include/rtw_ioctl_rtl.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/include/rtw_ioctl_rtl.h 2013-07-26 19:36:06.000000000 +0000 +@@ -0,0 +1,84 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ++******************************************************************************/ ++#ifndef _RTW_IOCTL_RTL_H_ ++#define _RTW_IOCTL_RTL_H_ ++ ++#include ++#include ++#include ++ ++//************** oid_rtl_seg_01_01 ************** ++NDIS_STATUS oid_rt_get_signal_quality_hdl(struct oid_par_priv* poid_par_priv);//84 ++NDIS_STATUS oid_rt_get_small_packet_crc_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_get_middle_packet_crc_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_get_large_packet_crc_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_get_tx_retry_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_get_rx_retry_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_get_rx_total_packet_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_get_tx_beacon_ok_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_get_tx_beacon_err_hdl(struct oid_par_priv* poid_par_priv); ++ ++NDIS_STATUS oid_rt_pro_set_fw_dig_state_hdl(struct oid_par_priv* poid_par_priv); //8a ++NDIS_STATUS oid_rt_pro_set_fw_ra_state_hdl(struct oid_par_priv* poid_par_priv); //8b ++ ++NDIS_STATUS oid_rt_get_rx_icv_err_hdl(struct oid_par_priv* poid_par_priv);//93 ++NDIS_STATUS oid_rt_set_encryption_algorithm_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_get_preamble_mode_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_get_ap_ip_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_get_channelplan_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_set_channelplan_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_set_preamble_mode_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_set_bcn_intvl_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_dedicate_probe_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_get_total_tx_bytes_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_get_total_rx_bytes_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_current_tx_power_level_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_get_enc_key_mismatch_count_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_get_enc_key_match_count_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_get_channel_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_get_hardware_radio_off_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_get_key_mismatch_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_supported_wireless_mode_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_get_channel_list_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_get_scan_in_progress_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_forced_data_rate_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_wireless_mode_for_scan_list_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_get_bss_wireless_mode_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_scan_with_magic_packet_hdl(struct oid_par_priv* poid_par_priv); ++ ++//************** oid_rtl_seg_01_03 section start ************** ++NDIS_STATUS oid_rt_ap_get_associated_station_list_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_ap_switch_into_ap_mode_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_ap_supported_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_ap_set_passphrase_hdl(struct oid_par_priv* poid_par_priv); ++ ++// oid_rtl_seg_01_11 ++NDIS_STATUS oid_rt_pro_rf_write_registry_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_pro_rf_read_registry_hdl(struct oid_par_priv* poid_par_priv); ++ ++//************** oid_rtl_seg_03_00 section start ************** ++NDIS_STATUS oid_rt_get_connect_state_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_set_default_key_id_hdl(struct oid_par_priv* poid_par_priv); ++ ++ ++ ++ ++#endif +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/include/rtw_ioctl_set.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/include/rtw_ioctl_set.h 2013-07-26 19:36:06.000000000 +0000 +@@ -0,0 +1,78 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ++******************************************************************************/ ++#ifndef __RTW_IOCTL_SET_H_ ++#define __RTW_IOCTL_SET_H_ ++ ++#include ++#include ++ ++ ++typedef u8 NDIS_802_11_PMKID_VALUE[16]; ++ ++typedef struct _BSSIDInfo { ++ NDIS_802_11_MAC_ADDRESS BSSID; ++ NDIS_802_11_PMKID_VALUE PMKID; ++} BSSIDInfo, *PBSSIDInfo; ++ ++ ++#ifdef PLATFORM_OS_XP ++typedef struct _NDIS_802_11_PMKID { ++ u32 Length; ++ u32 BSSIDInfoCount; ++ BSSIDInfo BSSIDInfo[1]; ++} NDIS_802_11_PMKID, *PNDIS_802_11_PMKID; ++#endif ++ ++ ++#ifdef PLATFORM_WINDOWS ++u8 rtw_set_802_11_reload_defaults(_adapter * padapter, NDIS_802_11_RELOAD_DEFAULTS reloadDefaults); ++u8 rtw_set_802_11_test(_adapter * padapter, NDIS_802_11_TEST * test); ++u8 rtw_set_802_11_pmkid(_adapter *pdapter, NDIS_802_11_PMKID *pmkid); ++ ++u8 rtw_pnp_set_power_sleep(_adapter* padapter); ++u8 rtw_pnp_set_power_wakeup(_adapter* padapter); ++ ++void rtw_pnp_resume_wk(void *context); ++void rtw_pnp_sleep_wk(void * context); ++ ++#endif ++ ++u8 rtw_set_802_11_add_key(_adapter * padapter, NDIS_802_11_KEY * key); ++u8 rtw_set_802_11_authentication_mode(_adapter *pdapter, NDIS_802_11_AUTHENTICATION_MODE authmode); ++u8 rtw_set_802_11_bssid(_adapter* padapter, u8 *bssid); ++u8 rtw_set_802_11_add_wep(_adapter * padapter, NDIS_802_11_WEP * wep); ++u8 rtw_set_802_11_disassociate(_adapter * padapter); ++u8 rtw_set_802_11_bssid_list_scan(_adapter* padapter); ++u8 rtw_set_802_11_infrastructure_mode(_adapter * padapter, NDIS_802_11_NETWORK_INFRASTRUCTURE networktype); ++u8 rtw_set_802_11_remove_wep(_adapter * padapter, u32 keyindex); ++u8 rtw_set_802_11_ssid(_adapter * padapter, NDIS_802_11_SSID * ssid); ++u8 rtw_set_802_11_remove_key(_adapter * padapter, NDIS_802_11_REMOVE_KEY * key); ++ ++ ++u8 rtw_validate_ssid(NDIS_802_11_SSID *ssid); ++ ++u16 rtw_get_network_max_rate(_adapter *adapter, WLAN_BSSID_EX *bss); ++int rtw_set_scan_mode(_adapter *adapter, RT_SCAN_TYPE scan_mode); ++int rtw_set_channel_plan(_adapter *adapter, u8 channel_plan); ++int rtw_set_country(_adapter *adapter, const char *country_code); ++ ++#endif ++ +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/include/rtw_iol.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/include/rtw_iol.h 2013-07-26 19:36:06.000000000 +0000 +@@ -0,0 +1,89 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef __RTW_IOL_H_ ++#define __RTW_IOL_H_ ++ ++#include ++#include ++#include ++ ++typedef struct _io_offload_cmd { ++ u8 rsvd0; ++ u8 cmd; ++ u16 address; ++ u32 value; ++} IO_OFFLOAD_CMD, IOL_CMD; ++ ++#define IOL_CMD_LLT 0x00 ++//#define IOL_CMD_R_EFUSE 0x01 ++#define IOL_CMD_WB_REG 0x02 ++#define IOL_CMD_WW_REG 0x03 ++#define IOL_CMD_WD_REG 0x04 ++//#define IOL_CMD_W_RF 0x05 ++#define IOL_CMD_DELAY_US 0x80 ++#define IOL_CMD_DELAY_MS 0x81 ++//#define IOL_CMD_DELAY_S 0x82 ++#define IOL_CMD_END 0x83 ++ ++/***************************************************** ++CMD Address Value ++(B1) (B2/B3:H/L addr) (B4:B7 : MSB:LSB) ++****************************************************** ++IOL_CMD_LLT - B7: PGBNDY ++//IOL_CMD_R_EFUSE - - ++IOL_CMD_WB_REG 0x0~0xFFFF B7 ++IOL_CMD_WW_REG 0x0~0xFFFF B6~B7 ++IOL_CMD_WD_REG 0x0~0xFFFF B4~B7 ++//IOL_CMD_W_RF RF Reg B5~B7 ++IOL_CMD_DELAY_US - B6~B7 ++IOL_CMD_DELAY_MS - B6~B7 ++//IOL_CMD_DELAY_S - B6~B7 ++IOL_CMD_END - - ++******************************************************/ ++ ++struct xmit_frame *rtw_IOL_accquire_xmit_frame(ADAPTER *adapter); ++int rtw_IOL_append_cmds(struct xmit_frame *xmit_frame, u8 *IOL_cmds, u32 cmd_len); ++int rtw_IOL_append_LLT_cmd(struct xmit_frame *xmit_frame, u8 page_boundary); ++int _rtw_IOL_append_WB_cmd(struct xmit_frame *xmit_frame, u16 addr, u8 value); ++int _rtw_IOL_append_WW_cmd(struct xmit_frame *xmit_frame, u16 addr, u16 value); ++int _rtw_IOL_append_WD_cmd(struct xmit_frame *xmit_frame, u16 addr, u32 value); ++int rtw_IOL_append_DELAY_US_cmd(struct xmit_frame *xmit_frame, u16 us); ++int rtw_IOL_append_DELAY_MS_cmd(struct xmit_frame *xmit_frame, u16 ms); ++int rtw_IOL_append_END_cmd(struct xmit_frame *xmit_frame); ++int rtw_IOL_exec_cmds_sync(ADAPTER *adapter, struct xmit_frame *xmit_frame, u32 max_wating_ms); ++int rtw_IOL_exec_cmd_array_sync(PADAPTER adapter, u8 *IOL_cmds, u32 cmd_num, u32 max_wating_ms); ++int rtw_IOL_exec_empty_cmds_sync(ADAPTER *adapter, u32 max_wating_ms); ++ ++#ifdef DBG_IO ++int dbg_rtw_IOL_append_WB_cmd(struct xmit_frame *xmit_frame, u16 addr, u8 value, const char *caller, const int line); ++int dbg_rtw_IOL_append_WW_cmd(struct xmit_frame *xmit_frame, u16 addr, u16 value, const char *caller, const int line); ++int dbg_rtw_IOL_append_WD_cmd(struct xmit_frame *xmit_frame, u16 addr, u32 value, const char *caller, const int line); ++#define rtw_IOL_append_WB_cmd(xmit_frame, addr, value) dbg_rtw_IOL_append_WB_cmd((xmit_frame), (addr), (value), __FUNCTION__, __LINE__) ++#define rtw_IOL_append_WW_cmd(xmit_frame, addr, value) dbg_rtw_IOL_append_WW_cmd((xmit_frame), (addr), (value), __FUNCTION__, __LINE__) ++#define rtw_IOL_append_WD_cmd(xmit_frame, addr, value) dbg_rtw_IOL_append_WD_cmd((xmit_frame), (addr), (value), __FUNCTION__, __LINE__) ++#else ++#define rtw_IOL_append_WB_cmd(xmit_frame, addr, value) _rtw_IOL_append_WB_cmd((xmit_frame), (addr), (value)) ++#define rtw_IOL_append_WW_cmd(xmit_frame, addr, value) _rtw_IOL_append_WW_cmd((xmit_frame), (addr), (value)) ++#define rtw_IOL_append_WD_cmd(xmit_frame, addr, value) _rtw_IOL_append_WD_cmd((xmit_frame), (addr), (value)) ++#endif ++ ++bool rtw_IOL_applied(ADAPTER *adapter); ++ ++#endif //__RTW_IOL_H_ +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/include/rtw_led.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/include/rtw_led.h 2013-07-26 19:36:06.000000000 +0000 +@@ -0,0 +1,214 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ++******************************************************************************/ ++#ifndef __RTW_LED_H_ ++#define __RTW_LED_H_ ++ ++#include ++#include ++#include ++ ++#define MSECS(t) (HZ * ((t) / 1000) + (HZ * ((t) % 1000)) / 1000) ++ ++typedef enum _LED_CTL_MODE{ ++ LED_CTL_POWER_ON = 1, ++ LED_CTL_LINK = 2, ++ LED_CTL_NO_LINK = 3, ++ LED_CTL_TX = 4, ++ LED_CTL_RX = 5, ++ LED_CTL_SITE_SURVEY = 6, ++ LED_CTL_POWER_OFF = 7, ++ LED_CTL_START_TO_LINK = 8, ++ LED_CTL_START_WPS = 9, ++ LED_CTL_STOP_WPS = 10, ++ LED_CTL_START_WPS_BOTTON = 11, //added for runtop ++ LED_CTL_STOP_WPS_FAIL = 12, //added for ALPHA ++ LED_CTL_STOP_WPS_FAIL_OVERLAP = 13, //added for BELKIN ++}LED_CTL_MODE; ++ ++ ++#ifdef CONFIG_USB_HCI ++//================================================================================ ++// LED object. ++//================================================================================ ++ ++typedef enum _LED_STATE_871x{ ++ LED_UNKNOWN = 0, ++ LED_ON = 1, ++ LED_OFF = 2, ++ LED_BLINK_NORMAL = 3, ++ LED_BLINK_SLOWLY = 4, ++ LED_POWER_ON_BLINK = 5, ++ LED_SCAN_BLINK = 6, // LED is blinking during scanning period, the # of times to blink is depend on time for scanning. ++ LED_NO_LINK_BLINK = 7, // LED is blinking during no link state. ++ LED_BLINK_StartToBlink = 8,// Customzied for Sercomm Printer Server case ++ LED_BLINK_WPS = 9, // LED is blinkg during WPS communication ++ LED_TXRX_BLINK = 10, ++ LED_BLINK_WPS_STOP = 11, //for ALPHA ++ LED_BLINK_WPS_STOP_OVERLAP = 12, //for BELKIN ++}LED_STATE_871x; ++ ++#define IS_LED_WPS_BLINKING(_LED_871x) (((PLED_871x)_LED_871x)->CurrLedState==LED_BLINK_WPS \ ++ || ((PLED_871x)_LED_871x)->CurrLedState==LED_BLINK_WPS_STOP \ ++ || ((PLED_871x)_LED_871x)->bLedWPSBlinkInProgress) ++ ++#define IS_LED_BLINKING(_LED_871x) (((PLED_871x)_LED_871x)->bLedWPSBlinkInProgress \ ++ ||((PLED_871x)_LED_871x)->bLedScanBlinkInProgress) ++ ++typedef enum _LED_PIN_871x{ ++ LED_PIN_GPIO0, ++ LED_PIN_LED0, ++ LED_PIN_LED1 ++}LED_PIN_871x; ++ ++typedef struct _LED_871x{ ++ _adapter *padapter; ++ LED_PIN_871x LedPin; // Identify how to implement this SW led. ++ LED_STATE_871x CurrLedState; // Current LED state. ++ u8 bLedOn; // true if LED is ON, false if LED is OFF. ++ ++ u8 bSWLedCtrl; ++ ++ u8 bLedBlinkInProgress; // true if it is blinking, false o.w.. ++ // ALPHA, added by chiyoko, 20090106 ++ u8 bLedNoLinkBlinkInProgress; ++ u8 bLedLinkBlinkInProgress; ++ u8 bLedStartToLinkBlinkInProgress; ++ u8 bLedScanBlinkInProgress; ++ u8 bLedWPSBlinkInProgress; ++ ++ u32 BlinkTimes; // Number of times to toggle led state for blinking. ++ LED_STATE_871x BlinkingLedState; // Next state for blinking, either LED_ON or LED_OFF are. ++ ++ _timer BlinkTimer; // Timer object for led blinking. ++#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0) ++ _workitem BlinkWorkItem; // Workitem used by BlinkTimer to manipulate H/W to blink LED. ++#endif ++} LED_871x, *PLED_871x; ++ ++ ++//================================================================================ ++// LED customization. ++//================================================================================ ++ ++typedef enum _LED_STRATEGY_871x{ ++ SW_LED_MODE0, // SW control 1 LED via GPIO0. It is default option. ++ SW_LED_MODE1, // 2 LEDs, through LED0 and LED1. For ALPHA. ++ SW_LED_MODE2, // SW control 1 LED via GPIO0, customized for AzWave 8187 minicard. ++ SW_LED_MODE3, // SW control 1 LED via GPIO0, customized for Sercomm Printer Server case. ++ SW_LED_MODE4, //for Edimax / Belkin ++ SW_LED_MODE5, //for Sercomm / Belkin ++ SW_LED_MODE6, //for 88CU minicard, porting from ce SW_LED_MODE7 ++ HW_LED, // HW control 2 LEDs, LED0 and LED1 (there are 4 different control modes, see MAC.CONFIG1 for details.) ++}LED_STRATEGY_871x, *PLED_STRATEGY_871x; ++#endif //CONFIG_USB_HCI ++ ++#ifdef CONFIG_PCI_HCI ++//================================================================================ ++// LED object. ++//================================================================================ ++ ++typedef enum _LED_STATE_871x{ ++ LED_UNKNOWN = 0, ++ LED_ON = 1, ++ LED_OFF = 2, ++ LED_BLINK_NORMAL = 3, ++ LED_BLINK_SLOWLY = 4, ++ LED_POWER_ON_BLINK = 5, ++ LED_SCAN_BLINK = 6, // LED is blinking during scanning period, the # of times to blink is depend on time for scanning. ++ LED_NO_LINK_BLINK = 7, // LED is blinking during no link state. ++ LED_BLINK_StartToBlink = 8, ++ LED_BLINK_TXRX = 9, ++ LED_BLINK_RUNTOP = 10, // Customized for RunTop ++ LED_BLINK_CAMEO = 11, ++}LED_STATE_871x; ++ ++typedef enum _LED_PIN_871x{ ++ LED_PIN_GPIO0, ++ LED_PIN_LED0, ++ LED_PIN_LED1, ++ LED_PIN_LED2 ++}LED_PIN_871x; ++ ++typedef struct _LED_871x{ ++ _adapter *padapter; ++ ++ LED_PIN_871x LedPin; // Identify how to implement this SW led. ++ ++ LED_STATE_871x CurrLedState; // Current LED state. ++ u8 bLedOn; // TRUE if LED is ON, FALSE if LED is OFF. ++ ++ u8 bLedBlinkInProgress; // TRUE if it is blinking, FALSE o.w.. ++ u8 bLedWPSBlinkInProgress; // TRUE if it is blinking, FALSE o.w.. ++ ++ u8 bLedSlowBlinkInProgress;//added by vivi, for led new mode ++ u32 BlinkTimes; // Number of times to toggle led state for blinking. ++ LED_STATE_871x BlinkingLedState; // Next state for blinking, either LED_ON or LED_OFF are. ++ ++ _timer BlinkTimer; // Timer object for led blinking. ++} LED_871x, *PLED_871x; ++ ++ ++//================================================================================ ++// LED customization. ++//================================================================================ ++ ++typedef enum _LED_STRATEGY_871x{ ++ SW_LED_MODE0, // SW control 1 LED via GPIO0. It is default option. ++ SW_LED_MODE1, // SW control for PCI Express ++ SW_LED_MODE2, // SW control for Cameo. ++ SW_LED_MODE3, // SW contorl for RunTop. ++ SW_LED_MODE4, // SW control for Netcore ++ SW_LED_MODE5, //added by vivi, for led new mode, DLINK ++ SW_LED_MODE6, //added by vivi, for led new mode, PRONET ++ SW_LED_MODE7, //added by chiyokolin, for Lenovo, PCI Express Minicard Spec Rev.1.2 spec ++ SW_LED_MODE8, //added by chiyokolin, for QMI ++ SW_LED_MODE9, //added by chiyokolin, for BITLAND, PCI Express Minicard Spec Rev.1.1 ++ SW_LED_MODE10, //added by chiyokolin, for Edimax-ASUS ++ HW_LED, // HW control 2 LEDs, LED0 and LED1 (there are 4 different control modes) ++}LED_STRATEGY_871x, *PLED_STRATEGY_871x; ++ ++#define LED_CM8_BLINK_INTERVAL 500 //for QMI ++#endif //CONFIG_PCI_HCI ++ ++struct led_priv{ ++ /* add for led controll */ ++ LED_871x SwLed0; ++ LED_871x SwLed1; ++ LED_STRATEGY_871x LedStrategy; ++ u8 bRegUseLed; ++ void (*LedControlHandler)(_adapter *padapter, LED_CTL_MODE LedAction); ++ /* add for led controll */ ++}; ++ ++#ifdef CONFIG_SW_LED ++#define rtw_led_control(adapter, LedAction) \ ++ do { \ ++ if((adapter)->ledpriv.LedControlHandler) \ ++ (adapter)->ledpriv.LedControlHandler((adapter), (LedAction)); \ ++ } while(0) ++#else //CONFIG_SW_LED ++#define rtw_led_control(adapter, LedAction) ++#endif //CONFIG_SW_LED ++ ++extern void BlinkHandler(PLED_871x pLed); ++ ++#endif //__RTW_LED_H_ ++ +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/include/rtw_mlme.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/include/rtw_mlme.h 2013-07-26 19:36:06.000000000 +0000 +@@ -0,0 +1,664 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ++******************************************************************************/ ++#ifndef __RTW_MLME_H_ ++#define __RTW_MLME_H_ ++ ++#include ++#include ++#include ++#include ++ ++ ++#define MAX_BSS_CNT 64 ++//#define MAX_JOIN_TIMEOUT 2000 ++//#define MAX_JOIN_TIMEOUT 2500 ++#define MAX_JOIN_TIMEOUT 6500 ++ ++// Commented by Albert 20101105 ++// Increase the scanning timeout because of increasing the SURVEY_TO value. ++ ++#define SCANNING_TIMEOUT 8000 ++ ++#define SCAN_INTERVAL (30) // unit:2sec, 30*2=60sec ++ ++#ifdef PALTFORM_OS_WINCE ++#define SCANQUEUE_LIFETIME 12000000 // unit:us ++#else ++#define SCANQUEUE_LIFETIME 20 // unit:sec ++#endif ++ ++#define WIFI_NULL_STATE 0x00000000 ++#define WIFI_ASOC_STATE 0x00000001 // Under Linked state... ++#define WIFI_REASOC_STATE 0x00000002 ++#define WIFI_SLEEP_STATE 0x00000004 ++#define WIFI_STATION_STATE 0x00000008 ++#define WIFI_AP_STATE 0x00000010 ++#define WIFI_ADHOC_STATE 0x00000020 ++#define WIFI_ADHOC_MASTER_STATE 0x00000040 ++#define WIFI_UNDER_LINKING 0x00000080 ++//#define WIFI_UNDER_CMD 0x00000200 ++// ========== P2P Section Start =============== ++#define WIFI_P2P_LISTEN_STATE 0x00010000 ++#define WIFI_P2P_GROUP_FORMATION_STATE 0x00020000 ++// ========== P2P Section End =============== ++#define WIFI_SITE_MONITOR 0x00000800 //to indicate the station is under site surveying ++ ++#ifdef WDS ++#define WIFI_WDS 0x00001000 ++#define WIFI_WDS_RX_BEACON 0x00002000 // already rx WDS AP beacon ++#endif ++#ifdef AUTO_CONFIG ++#define WIFI_AUTOCONF 0x00004000 ++#define WIFI_AUTOCONF_IND 0x00008000 ++#endif ++ ++//#ifdef UNDER_MPTEST ++#define WIFI_MP_STATE 0x00010000 ++#define WIFI_MP_CTX_BACKGROUND 0x00020000 // in continous tx background ++#define WIFI_MP_CTX_ST 0x00040000 // in continous tx with single-tone ++#define WIFI_MP_CTX_BACKGROUND_PENDING 0x00080000 // pending in continous tx background due to out of skb ++#define WIFI_MP_CTX_CCK_HW 0x00100000 // in continous tx ++#define WIFI_MP_CTX_CCK_CS 0x00200000 // in continous tx with carrier suppression ++#define WIFI_MP_LPBK_STATE 0x00400000 ++//#endif ++ ++//#define _FW_UNDER_CMD WIFI_UNDER_CMD ++#define _FW_UNDER_LINKING WIFI_UNDER_LINKING ++#define _FW_LINKED WIFI_ASOC_STATE ++#define _FW_UNDER_SURVEY WIFI_SITE_MONITOR ++ ++enum dot11AuthAlgrthmNum { ++ dot11AuthAlgrthm_Open = 0, ++ dot11AuthAlgrthm_Shared, ++ dot11AuthAlgrthm_8021X, ++ dot11AuthAlgrthm_Auto, ++ dot11AuthAlgrthm_MaxNum ++}; ++ ++// Scan type including active and passive scan. ++typedef enum _RT_SCAN_TYPE ++{ ++ SCAN_PASSIVE, ++ SCAN_ACTIVE, ++ SCAN_MIX, ++}RT_SCAN_TYPE, *PRT_SCAN_TYPE; ++ ++/* ++ ++there are several "locks" in mlme_priv, ++since mlme_priv is a shared resource between many threads, ++like ISR/Call-Back functions, the OID handlers, and even timer functions. ++ ++ ++Each _queue has its own locks, already. ++Other items are protected by mlme_priv.lock. ++ ++To avoid possible dead lock, any thread trying to modifiying mlme_priv ++SHALL not lock up more than one locks at a time! ++ ++*/ ++ ++ ++#define traffic_threshold 10 ++#define traffic_scan_period 500 ++ ++struct sitesurvey_ctrl { ++ u64 last_tx_pkts; ++ uint last_rx_pkts; ++ sint traffic_busy; ++ _timer sitesurvey_ctrl_timer; ++}; ++ ++typedef struct _RT_LINK_DETECT_T{ ++ u32 NumTxOkInPeriod; ++ u32 NumRxOkInPeriod; ++ u32 NumRxUnicastOkInPeriod; ++ BOOLEAN bBusyTraffic; ++ BOOLEAN bTxBusyTraffic; ++ BOOLEAN bRxBusyTraffic; ++ BOOLEAN bHigherBusyTraffic; // For interrupt migration purpose. ++ BOOLEAN bHigherBusyRxTraffic; // We may disable Tx interrupt according as Rx traffic. ++}RT_LINK_DETECT_T, *PRT_LINK_DETECT_T; ++ ++struct profile_info { ++ u8 ssidlen; ++ u8 ssid[ WLAN_SSID_MAXLEN ]; ++ u8 peermac[ ETH_ALEN ]; ++}; ++ ++struct tx_invite_req_info{ ++ u8 token; ++ u8 ssid[ WLAN_SSID_MAXLEN ]; ++ u8 ssidlen; ++ u8 peer_operation_ch; ++}; ++ ++struct tx_invite_resp_info{ ++ u8 token; // Used to record the dialog token of p2p invitation request frame. ++}; ++ ++#ifdef CONFIG_WFD ++ ++struct wifi_display_info{ ++ u16 rtsp_ctrlport; // TCP port number at which the this WFD device listens for RTSP messages ++ u16 peer_rtsp_ctrlport; // TCP port number at which the peer WFD device listens for RTSP messages ++ // This filed should be filled when receiving the gropu negotiation request ++}; ++#endif //CONFIG_WFD ++ ++struct tx_provdisc_req_info{ ++ u16 wps_config_method_request; // Used when sending the provisioning request frame ++ u16 peer_channel_num[2]; // The channel number which the receiver stands. ++ NDIS_802_11_SSID ssid; ++ u8 peerDevAddr[ ETH_ALEN ]; // Peer device address ++ u8 peerIFAddr[ ETH_ALEN ]; // Peer interface address ++ u8 benable; // This provision discovery request frame is trigger to send or not ++}; ++ ++struct rx_provdisc_req_info{ //When peer device issue prov_disc_req first, we should store the following informations ++ u8 peerDevAddr[ ETH_ALEN ]; // Peer device address ++ u8 strconfig_method_desc_of_prov_disc_req[4]; // description for the config method located in the provisioning discovery request frame. ++ // The UI must know this information to know which config method the remote p2p device is requiring. ++}; ++ ++struct tx_nego_req_info{ ++ u16 peer_channel_num[2]; // The channel number which the receiver stands. ++ u8 peerDevAddr[ ETH_ALEN ]; // Peer device address ++ u8 benable; // This negoitation request frame is trigger to send or not ++}; ++ ++struct group_id_info{ ++ u8 go_device_addr[ ETH_ALEN ]; // The GO's device address of this P2P group ++ u8 ssid[ WLAN_SSID_MAXLEN ]; // The SSID of this P2P group ++}; ++ ++#ifdef CONFIG_IOCTL_CFG80211 ++struct cfg80211_wifidirect_info{ ++ _timer remain_on_ch_timer; ++ u8 restore_channel; ++ struct ieee80211_channel remain_on_ch_channel; ++ enum nl80211_channel_type remain_on_ch_type; ++ u64 remain_on_ch_cookie; ++ struct net_device *remain_on_ch_dev; ++ ++}; ++#endif //CONFIG_IOCTL_CFG80211 ++ ++struct wifidirect_info{ ++ _adapter* padapter; ++ _timer find_phase_timer; ++ _timer restore_p2p_state_timer; ++ ++ // Used to do the scanning. After confirming the peer is availalble, the driver transmits the P2P frame to peer. ++ _timer pre_tx_scan_timer; ++ struct tx_provdisc_req_info tx_prov_disc_info; ++ struct rx_provdisc_req_info rx_prov_disc_info; ++ struct tx_invite_req_info invitereq_info; ++ struct profile_info profileinfo[ P2P_MAX_PERSISTENT_GROUP_NUM ]; // Store the profile information of persistent group ++ struct tx_invite_resp_info inviteresp_info; ++ struct tx_nego_req_info nego_req_info; ++ struct group_id_info groupid_info; // Store the group id information when doing the group negotiation handshake. ++#ifdef CONFIG_WFD ++ struct wifi_display_info wfd_info; ++#endif ++ enum P2P_ROLE role; ++ enum P2P_STATE pre_p2p_state; ++ enum P2P_STATE p2p_state; ++ u8 device_addr[ETH_ALEN]; // The device address should be the mac address of this device. ++ u8 interface_addr[ETH_ALEN]; ++ u8 social_chan[4]; ++ u8 listen_channel; ++ u8 operating_channel; ++ u8 listen_dwell; // This value should be between 1 and 3 ++ u8 support_rate[8]; ++ u8 p2p_wildcard_ssid[P2P_WILDCARD_SSID_LEN]; ++ u8 intent; // should only include the intent value. ++ u8 p2p_peer_interface_addr[ ETH_ALEN ]; ++ u8 peer_intent; // Included the intent value and tie breaker value. ++ u8 device_name[ WPS_MAX_DEVICE_NAME_LEN ]; // Device name for displaying on searching device screen ++ u8 device_name_len; ++ u8 profileindex; // Used to point to the index of profileinfo array ++ u8 peer_operating_ch; ++ u8 find_phase_state_exchange_cnt; ++ u16 device_password_id_for_nego; // The device password ID for group negotation ++ u8 negotiation_dialog_token; ++ u8 nego_ssid[ WLAN_SSID_MAXLEN ]; // SSID information for group negotitation ++ u8 nego_ssidlen; ++ u8 p2p_group_ssid[WLAN_SSID_MAXLEN]; ++ u8 p2p_group_ssid_len; ++ ++ enum P2P_WPSINFO ui_got_wps_info; // This field will store the WPS value (PIN value or PBC) that UI had got from the user. ++ u16 supported_wps_cm; // This field describes the WPS config method which this driver supported. ++ // The value should be the combination of config method defined in page104 of WPS v2.0 spec. ++ u8 channel_cnt; // This field is the count number for P2P Channel List attribute of group negotitation response frame. ++ u8 channel_list[13]; // This field will contain the channel number of P2P Channel List attribute of group negotitation response frame. ++ // We will use the channel_cnt and channel_list fields when constructing the group negotitation confirm frame. ++ u8 p2p_ps_enable; ++ enum P2P_PS p2p_ps; // indicate p2p ps state ++ u8 noa_index; // Identifies and instance of Notice of Absence timing. ++ u8 ctwindow; // Client traffic window. A period of time in TU after TBTT. ++ u8 opp_ps; // opportunistic power save. ++ u8 noa_num; // number of NoA descriptor in P2P IE. ++ u8 noa_count[P2P_MAX_NOA_NUM]; // Count for owner, Type of client. ++ u32 noa_duration[P2P_MAX_NOA_NUM]; // Max duration for owner, preferred or min acceptable duration for client. ++ u32 noa_interval[P2P_MAX_NOA_NUM]; // Length of interval for owner, preferred or max acceptable interval of client. ++ u32 noa_start_time[P2P_MAX_NOA_NUM]; // schedule expressed in terms of the lower 4 bytes of the TSF timer. ++}; ++ ++struct tdls_ss_record{ //signal strength record ++ u8 macaddr[ETH_ALEN]; ++ u8 signal_strength; ++ u8 is_tdls_sta; // _TRUE: direct link sta, _FALSE: else ++}; ++ ++struct tdls_info{ ++ u8 ap_prohibited; ++ uint setup_state; ++ u8 sta_cnt; ++ u8 sta_maximum; // 1:tdls sta is equal (NUM_STA-1), reach max direct link number; 0: else; ++ struct tdls_ss_record ss_record; ++ u8 cam_entry_to_write; //cam entry that is empty to write ++ u8 cam_entry_to_clear; //cam entry that is trying to clear, using in direct link teardown ++ u8 ch_sensing; ++ u8 cur_channel; ++ u8 candidate_ch; ++ u8 collect_pkt_num[MAX_CHANNEL_NUM]; ++ _lock cmd_lock; ++ _lock hdl_lock; ++ _lock timer_lock; ++ u8 watchdog_count; ++}; ++ ++struct mlme_priv { ++ ++ _lock lock; ++ sint fw_state; //shall we protect this variable? maybe not necessarily... ++ ++ u8 to_join; //flag ++ #ifdef CONFIG_LAYER2_ROAMING ++ u8 to_roaming; // roaming trying times ++ #endif ++ ++ u8 *nic_hdl; ++ ++ _list *pscanned; ++ _queue free_bss_pool; ++ _queue scanned_queue; ++ u8 *free_bss_buf; ++ u32 num_of_scanned; ++ ++ NDIS_802_11_SSID assoc_ssid; ++ u8 assoc_bssid[6]; ++ ++ struct wlan_network cur_network; ++ ++ //uint wireless_mode; no used, remove it ++ ++ u32 scan_interval; ++ ++ _timer assoc_timer; ++ ++ uint assoc_by_bssid; ++ ++ _timer scan_to_timer; // driver itself handles scan_timeout status. ++ u32 scan_start_time; // used to evaluate the time spent in scanning ++ ++ #ifdef CONFIG_SET_SCAN_DENY_TIMER ++ _timer set_scan_deny_timer; ++ ATOMIC_T set_scan_deny; //0: allowed, 1: deny ++ #endif ++ ++ struct qos_priv qospriv; ++ ++#ifdef CONFIG_80211N_HT ++ ++ /* Number of non-HT AP/stations */ ++ int num_sta_no_ht; ++ ++ /* Number of HT AP/stations 20 MHz */ ++ //int num_sta_ht_20mhz; ++ ++ ++ int num_FortyMHzIntolerant; ++ ++ struct ht_priv htpriv; ++ ++#endif ++ ++ RT_LINK_DETECT_T LinkDetectInfo; ++ _timer dynamic_chk_timer; //dynamic/periodic check timer ++ ++ u8 key_mask; //use for ips to set wep key after ips_leave ++ u8 acm_mask; // for wmm acm mask ++ u8 ChannelPlan; ++ RT_SCAN_TYPE scan_mode; // active: 1, passive: 0 ++ ++ ++ u8 probereq_wpsie[MAX_WPS_IE_LEN];//added in probe req ++ int probereq_wpsie_len; ++ ++#if defined (CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME) ++ /* Number of associated Non-ERP stations (i.e., stations using 802.11b ++ * in 802.11g BSS) */ ++ int num_sta_non_erp; ++ ++ /* Number of associated stations that do not support Short Slot Time */ ++ int num_sta_no_short_slot_time; ++ ++ /* Number of associated stations that do not support Short Preamble */ ++ int num_sta_no_short_preamble; ++ ++ int olbc; /* Overlapping Legacy BSS Condition */ ++ ++ /* Number of HT associated stations that do not support greenfield */ ++ int num_sta_ht_no_gf; ++ ++ /* Number of associated non-HT stations */ ++ //int num_sta_no_ht; ++ ++ /* Number of HT associated stations 20 MHz */ ++ int num_sta_ht_20mhz; ++ ++ /* Overlapping BSS information */ ++ int olbc_ht; ++ ++#ifdef CONFIG_80211N_HT ++ u16 ht_op_mode; ++#endif /* CONFIG_80211N_HT */ ++ ++ u8 *wps_beacon_ie; ++ u8 *wps_probe_req_ie; ++ u8 *wps_probe_resp_ie; ++ u8 *wps_assoc_resp_ie; // for CONFIG_IOCTL_CFG80211, this IE could include p2p ie ++ ++ u32 wps_beacon_ie_len; ++ u32 wps_probe_req_ie_len; ++ u32 wps_probe_resp_ie_len; ++ u32 wps_assoc_resp_ie_len; ++ ++ u8 *p2p_beacon_ie; ++ u8 *p2p_probe_req_ie; ++ u8 *p2p_probe_resp_ie; ++ u8 *p2p_go_probe_resp_ie; //for GO ++ u8 *p2p_assoc_req_ie; ++ ++ u32 p2p_beacon_ie_len; ++ u32 p2p_probe_req_ie_len; ++ u32 p2p_probe_resp_ie_len; ++ u32 p2p_go_probe_resp_ie_len; //for GO ++ u32 p2p_assoc_req_ie_len; ++/* ++#if defined(CONFIG_P2P) && defined(CONFIG_IOCTL_CFG80211) ++ //u8 *wps_p2p_beacon_ie; ++ u8 *p2p_beacon_ie; ++ u8 *wps_p2p_probe_resp_ie; ++ u8 *wps_p2p_assoc_resp_ie; ++ //u32 wps_p2p_beacon_ie_len; ++ u32 p2p_beacon_ie_len; ++ u32 wps_p2p_probe_resp_ie_len; ++ u32 wps_p2p_assoc_resp_ie_len; ++#endif ++*/ ++ ++ _lock bcn_update_lock; ++ u8 update_bcn; ++ ++ ++#endif //#if defined (CONFIG_AP_MODE) && defined (CONFIG_NATIVEAP_MLME) ++ ++#ifdef RTK_DMP_PLATFORM ++ // DMP kobject_hotplug function signal need in passive level ++ _workitem Linkup_workitem; ++ _workitem Linkdown_workitem; ++#endif ++ ++}; ++ ++#ifdef CONFIG_AP_MODE ++ ++struct hostapd_priv ++{ ++ _adapter *padapter; ++ ++#ifdef CONFIG_HOSTAPD_MLME ++ struct net_device *pmgnt_netdev; ++ struct usb_anchor anchored; ++#endif ++ ++}; ++ ++extern int hostapd_mode_init(_adapter *padapter); ++extern void hostapd_mode_unload(_adapter *padapter); ++#endif ++ ++ ++extern void rtw_joinbss_event_prehandle(_adapter *adapter, u8 *pbuf); ++extern void rtw_survey_event_callback(_adapter *adapter, u8 *pbuf); ++extern void rtw_surveydone_event_callback(_adapter *adapter, u8 *pbuf); ++extern void rtw_joinbss_event_callback(_adapter *adapter, u8 *pbuf); ++extern void rtw_stassoc_event_callback(_adapter *adapter, u8 *pbuf); ++extern void rtw_stadel_event_callback(_adapter *adapter, u8 *pbuf); ++extern void rtw_atimdone_event_callback(_adapter *adapter, u8 *pbuf); ++extern void rtw_cpwm_event_callback(_adapter *adapter, u8 *pbuf); ++ ++#ifdef PLATFORM_WINDOWS ++extern thread_return event_thread(void *context); ++ ++extern void rtw_join_timeout_handler ( ++ IN PVOID SystemSpecific1, ++ IN PVOID FunctionContext, ++ IN PVOID SystemSpecific2, ++ IN PVOID SystemSpecific3 ++ ); ++ ++extern void _rtw_scan_timeout_handler ( ++ IN PVOID SystemSpecific1, ++ IN PVOID FunctionContext, ++ IN PVOID SystemSpecific2, ++ IN PVOID SystemSpecific3 ++ ); ++ ++#endif ++ ++#ifdef PLATFORM_LINUX ++extern int event_thread(void *context); ++extern void rtw_join_timeout_handler(void* FunctionContext); ++extern void _rtw_scan_timeout_handler(void* FunctionContext); ++#endif ++ ++extern void rtw_free_network_queue(_adapter *adapter,u8 isfreeall); ++extern int rtw_init_mlme_priv(_adapter *adapter);// (struct mlme_priv *pmlmepriv); ++ ++extern void rtw_free_mlme_priv (struct mlme_priv *pmlmepriv); ++ ++ ++extern sint rtw_select_and_join_from_scanned_queue(struct mlme_priv *pmlmepriv); ++extern sint rtw_set_key(_adapter *adapter,struct security_priv *psecuritypriv,sint keyid, u8 set_tx); ++extern sint rtw_set_auth(_adapter *adapter,struct security_priv *psecuritypriv); ++ ++__inline static u8 *get_bssid(struct mlme_priv *pmlmepriv) ++{ //if sta_mode:pmlmepriv->cur_network.network.MacAddress=> bssid ++ // if adhoc_mode:pmlmepriv->cur_network.network.MacAddress=> ibss mac address ++ return pmlmepriv->cur_network.network.MacAddress; ++} ++ ++__inline static sint check_fwstate(struct mlme_priv *pmlmepriv, sint state) ++{ ++ if (pmlmepriv->fw_state & state) ++ return _TRUE; ++ ++ return _FALSE; ++} ++ ++__inline static sint get_fwstate(struct mlme_priv *pmlmepriv) ++{ ++ return pmlmepriv->fw_state; ++} ++ ++/* ++ * No Limit on the calling context, ++ * therefore set it to be the critical section... ++ * ++ * ### NOTE:#### (!!!!) ++ * MUST TAKE CARE THAT BEFORE CALLING THIS FUNC, YOU SHOULD HAVE LOCKED pmlmepriv->lock ++ */ ++__inline static void set_fwstate(struct mlme_priv *pmlmepriv, sint state) ++{ ++ pmlmepriv->fw_state |= state; ++} ++ ++__inline static void _clr_fwstate_(struct mlme_priv *pmlmepriv, sint state) ++{ ++ pmlmepriv->fw_state &= ~state; ++} ++ ++/* ++ * No Limit on the calling context, ++ * therefore set it to be the critical section... ++ */ ++__inline static void clr_fwstate(struct mlme_priv *pmlmepriv, sint state) ++{ ++ _irqL irqL; ++ ++ _enter_critical_bh(&pmlmepriv->lock, &irqL); ++ if (check_fwstate(pmlmepriv, state) == _TRUE) ++ pmlmepriv->fw_state ^= state; ++ _exit_critical_bh(&pmlmepriv->lock, &irqL); ++} ++ ++__inline static void clr_fwstate_ex(struct mlme_priv *pmlmepriv, sint state) ++{ ++ _irqL irqL; ++ ++ _enter_critical_bh(&pmlmepriv->lock, &irqL); ++ _clr_fwstate_(pmlmepriv, state); ++ _exit_critical_bh(&pmlmepriv->lock, &irqL); ++} ++ ++__inline static void up_scanned_network(struct mlme_priv *pmlmepriv) ++{ ++ _irqL irqL; ++ ++ _enter_critical_bh(&pmlmepriv->lock, &irqL); ++ pmlmepriv->num_of_scanned++; ++ _exit_critical_bh(&pmlmepriv->lock, &irqL); ++} ++ ++__inline static void down_scanned_network(struct mlme_priv *pmlmepriv) ++{ ++ _irqL irqL; ++ ++ _enter_critical_bh(&pmlmepriv->lock, &irqL); ++ pmlmepriv->num_of_scanned--; ++ _exit_critical_bh(&pmlmepriv->lock, &irqL); ++} ++ ++__inline static void set_scanned_network_val(struct mlme_priv *pmlmepriv, sint val) ++{ ++ _irqL irqL; ++ ++ _enter_critical_bh(&pmlmepriv->lock, &irqL); ++ pmlmepriv->num_of_scanned = val; ++ _exit_critical_bh(&pmlmepriv->lock, &irqL); ++} ++ ++extern u16 rtw_get_capability(WLAN_BSSID_EX *bss); ++extern void rtw_update_scanned_network(_adapter *adapter, WLAN_BSSID_EX *target); ++extern void rtw_disconnect_hdl_under_linked(_adapter* adapter, struct sta_info *psta, u8 free_assoc); ++extern void rtw_generate_random_ibss(u8 *pibss); ++extern struct wlan_network* rtw_find_network(_queue *scanned_queue, u8 *addr); ++extern struct wlan_network* rtw_get_oldest_wlan_network(_queue *scanned_queue); ++ ++extern void rtw_free_assoc_resources(_adapter* adapter, int lock_scanned_queue); ++extern void rtw_indicate_disconnect(_adapter* adapter); ++extern void rtw_indicate_connect(_adapter* adapter); ++void rtw_indicate_scan_done( _adapter *padapter, bool aborted); ++ ++extern int rtw_restruct_sec_ie(_adapter *adapter,u8 *in_ie,u8 *out_ie,uint in_len); ++extern int rtw_restruct_wmm_ie(_adapter *adapter, u8 *in_ie, u8 *out_ie, uint in_len, uint initial_out_len); ++extern void rtw_init_registrypriv_dev_network(_adapter *adapter); ++ ++extern void rtw_update_registrypriv_dev_network(_adapter *adapter); ++ ++extern void rtw_get_encrypt_decrypt_from_registrypriv(_adapter *adapter); ++ ++extern void _rtw_join_timeout_handler(_adapter *adapter); ++extern void rtw_scan_timeout_handler(_adapter *adapter); ++ ++extern void rtw_dynamic_check_timer_handlder(_adapter *adapter); ++#ifdef CONFIG_SET_SCAN_DENY_TIMER ++extern void rtw_set_scan_deny_timer_hdl(_adapter *adapter); ++void rtw_set_scan_deny(struct mlme_priv *mlmepriv, u32 ms); ++#endif ++ ++ ++extern int _rtw_init_mlme_priv(_adapter *padapter); ++ ++void rtw_free_mlme_priv_ie_data(struct mlme_priv *pmlmepriv); ++ ++extern void _rtw_free_mlme_priv(struct mlme_priv *pmlmepriv); ++ ++extern int _rtw_enqueue_network(_queue *queue, struct wlan_network *pnetwork); ++ ++extern struct wlan_network* _rtw_dequeue_network(_queue *queue); ++ ++extern struct wlan_network* _rtw_alloc_network(struct mlme_priv *pmlmepriv); ++ ++ ++extern void _rtw_free_network(struct mlme_priv *pmlmepriv, struct wlan_network *pnetwork, u8 isfreeall); ++extern void _rtw_free_network_nolock(struct mlme_priv *pmlmepriv, struct wlan_network *pnetwork); ++ ++ ++extern struct wlan_network* _rtw_find_network(_queue *scanned_queue, u8 *addr); ++ ++extern void _rtw_free_network_queue(_adapter* padapter, u8 isfreeall); ++ ++extern sint rtw_if_up(_adapter *padapter); ++ ++ ++u8 *rtw_get_capability_from_ie(u8 *ie); ++u8 *rtw_get_timestampe_from_ie(u8 *ie); ++u8 *rtw_get_beacon_interval_from_ie(u8 *ie); ++ ++ ++void rtw_joinbss_reset(_adapter *padapter); ++ ++#ifdef CONFIG_80211N_HT ++unsigned int rtw_restructure_ht_ie(_adapter *padapter, u8 *in_ie, u8 *out_ie, uint in_len, uint *pout_len); ++void rtw_update_ht_cap(_adapter *padapter, u8 *pie, uint ie_len); ++void rtw_issue_addbareq_cmd(_adapter *padapter, struct xmit_frame *pxmitframe); ++#endif ++ ++int rtw_is_same_ibss(_adapter *adapter, struct wlan_network *pnetwork); ++ ++#ifdef CONFIG_LAYER2_ROAMING ++void rtw_roaming(_adapter *padapter, struct wlan_network *tgt_network); ++void _rtw_roaming(_adapter *padapter, struct wlan_network *tgt_network); ++#endif ++ ++ ++#ifdef CONFIG_INTEL_PROXIM ++void rtw_proxim_enable(_adapter *padapter); ++void rtw_proxim_disable(_adapter *padapter); ++void rtw_proxim_send_packet(_adapter *padapter,u8 *pbuf,u16 len,u8 hw_rate); ++#endif //CONFIG_INTEL_PROXIM ++#endif //__RTL871X_MLME_H_ ++ +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/include/rtw_mlme_ext.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/include/rtw_mlme_ext.h 2013-07-26 19:36:06.000000000 +0000 +@@ -0,0 +1,878 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ++******************************************************************************/ ++#ifndef __RTW_MLME_EXT_H_ ++#define __RTW_MLME_EXT_H_ ++ ++#include ++#include ++#include ++#include ++ ++ ++// Commented by Albert 20101105 ++// Increase the SURVEY_TO value from 100 to 150 ( 100ms to 150ms ) ++// The Realtek 8188CE SoftAP will spend around 100ms to send the probe response after receiving the probe request. ++// So, this driver tried to extend the dwell time for each scanning channel. ++// This will increase the chance to receive the probe response from SoftAP. ++ ++#define SURVEY_TO (100) ++#define REAUTH_TO (300) //(50) ++#define REASSOC_TO (300) //(50) ++//#define DISCONNECT_TO (3000) ++#define ADDBA_TO (2000) ++ ++#define LINKED_TO (1) //unit:2 sec, 1x2=2 sec ++ ++#define REAUTH_LIMIT (2) ++#define REASSOC_LIMIT (2) ++#define READDBA_LIMIT (2) ++ ++//#define IOCMD_REG0 0x10250370 ++//#define IOCMD_REG1 0x10250374 ++//#define IOCMD_REG2 0x10250378 ++ ++//#define FW_DYNAMIC_FUN_SWITCH 0x10250364 ++ ++//#define WRITE_BB_CMD 0xF0000001 ++//#define SET_CHANNEL_CMD 0xF3000000 ++//#define UPDATE_RA_CMD 0xFD0000A2 ++ ++#define DYNAMIC_FUNC_DISABLE (0x0) ++#define DYNAMIC_FUNC_DIG BIT(0) ++#define DYNAMIC_FUNC_HP BIT(1) ++#define DYNAMIC_FUNC_SS BIT(2) //Tx Power Tracking ++#define DYNAMIC_FUNC_BT BIT(3) ++#define DYNAMIC_FUNC_ANT_DIV BIT(4) ++ ++#define _HW_STATE_NOLINK_ 0x00 ++#define _HW_STATE_ADHOC_ 0x01 ++#define _HW_STATE_STATION_ 0x02 ++#define _HW_STATE_AP_ 0x03 ++ ++ ++#define _1M_RATE_ 0 ++#define _2M_RATE_ 1 ++#define _5M_RATE_ 2 ++#define _11M_RATE_ 3 ++#define _6M_RATE_ 4 ++#define _9M_RATE_ 5 ++#define _12M_RATE_ 6 ++#define _18M_RATE_ 7 ++#define _24M_RATE_ 8 ++#define _36M_RATE_ 9 ++#define _48M_RATE_ 10 ++#define _54M_RATE_ 11 ++ ++ ++// ++// Channel Plan Type. ++// Note: ++// We just add new channel plan when the new channel plan is different from any of the following ++// channel plan. ++// If you just wnat to customize the acitions(scan period or join actions) about one of the channel plan, ++// customize them in RT_CHANNEL_INFO in the RT_CHANNEL_LIST. ++// ++typedef enum _RT_CHANNEL_DOMAIN ++{ ++ //===== old channel plan mapping =====// ++ RT_CHANNEL_DOMAIN_FCC = 0x00, ++ RT_CHANNEL_DOMAIN_IC = 0x01, ++ RT_CHANNEL_DOMAIN_ETSI = 0x02, ++ RT_CHANNEL_DOMAIN_SPAIN = 0x03, ++ RT_CHANNEL_DOMAIN_FRANCE = 0x04, ++ RT_CHANNEL_DOMAIN_MKK = 0x05, ++ RT_CHANNEL_DOMAIN_MKK1 = 0x06, ++ RT_CHANNEL_DOMAIN_ISRAEL = 0x07, ++ RT_CHANNEL_DOMAIN_TELEC = 0x08, ++ RT_CHANNEL_DOMAIN_GLOBAL_DOAMIN = 0x09, ++ RT_CHANNEL_DOMAIN_WORLD_WIDE_13 = 0x0A, ++ RT_CHANNEL_DOMAIN_TAIWAN = 0x0B, ++ RT_CHANNEL_DOMAIN_CHINA = 0x0C, ++ RT_CHANNEL_DOMAIN_SINGAPORE_INDIA_MEXICO = 0x0D, ++ RT_CHANNEL_DOMAIN_KOREA = 0x0E, ++ RT_CHANNEL_DOMAIN_TURKEY = 0x0F, ++ RT_CHANNEL_DOMAIN_JAPAN = 0x10, ++ RT_CHANNEL_DOMAIN_FCC_NO_DFS = 0x11, ++ RT_CHANNEL_DOMAIN_JAPAN_NO_DFS = 0x12, ++ RT_CHANNEL_DOMAIN_WORLD_WIDE_5G = 0x13, ++ RT_CHANNEL_DOMAIN_TAIWAN_NO_DFS = 0x14, ++ ++ //===== new channel plan mapping, (2GDOMAIN_5GDOMAIN) =====// ++ RT_CHANNEL_DOMAIN_WORLD_NULL = 0x20, ++ RT_CHANNEL_DOMAIN_ETSI1_NULL = 0x21, ++ RT_CHANNEL_DOMAIN_FCC1_NULL = 0x22, ++ RT_CHANNEL_DOMAIN_MKK1_NULL = 0x23, ++ RT_CHANNEL_DOMAIN_ETSI2_NULL = 0x24, ++ RT_CHANNEL_DOMAIN_FCC1_FCC1 = 0x25, ++ RT_CHANNEL_DOMAIN_WORLD_ETSI1 = 0x26, ++ RT_CHANNEL_DOMAIN_MKK1_MKK1 = 0x27, ++ RT_CHANNEL_DOMAIN_WORLD_KCC1 = 0x28, ++ RT_CHANNEL_DOMAIN_WORLD_FCC2 = 0x29, ++ RT_CHANNEL_DOMAIN_WORLD_FCC3 = 0x30, ++ RT_CHANNEL_DOMAIN_WORLD_FCC4 = 0x31, ++ RT_CHANNEL_DOMAIN_WORLD_FCC5 = 0x32, ++ RT_CHANNEL_DOMAIN_WORLD_FCC6 = 0x33, ++ RT_CHANNEL_DOMAIN_FCC1_FCC7 = 0x34, ++ RT_CHANNEL_DOMAIN_WORLD_ETSI2 = 0x35, ++ RT_CHANNEL_DOMAIN_WORLD_ETSI3 = 0x36, ++ RT_CHANNEL_DOMAIN_MKK1_MKK2 = 0x37, ++ RT_CHANNEL_DOMAIN_MKK1_MKK3 = 0x38, ++ RT_CHANNEL_DOMAIN_FCC1_NCC1 = 0x39, ++ RT_CHANNEL_DOMAIN_FCC1_NCC2 = 0x40, ++ ++ //===== Add new channel plan above this line===============// ++ RT_CHANNEL_DOMAIN_MAX, ++ RT_CHANNEL_DOMAIN_REALTEK_DEFINE = 0x7F, ++}RT_CHANNEL_DOMAIN, *PRT_CHANNEL_DOMAIN; ++ ++typedef enum _RT_CHANNEL_DOMAIN_2G ++{ ++ RT_CHANNEL_DOMAIN_2G_WORLD = 0x00, //Worldwird 13 ++ RT_CHANNEL_DOMAIN_2G_ETSI1 = 0x01, //Europe ++ RT_CHANNEL_DOMAIN_2G_FCC1 = 0x02, //US ++ RT_CHANNEL_DOMAIN_2G_MKK1 = 0x03, //Japan ++ RT_CHANNEL_DOMAIN_2G_ETSI2 = 0x04, //France ++ //===== Add new channel plan above this line===============// ++ RT_CHANNEL_DOMAIN_2G_MAX, ++}RT_CHANNEL_DOMAIN_2G, *PRT_CHANNEL_DOMAIN_2G; ++ ++typedef enum _RT_CHANNEL_DOMAIN_5G ++{ ++ RT_CHANNEL_DOMAIN_5G_NULL = 0x00, ++ RT_CHANNEL_DOMAIN_5G_ETSI1 = 0x01, //Europe ++ RT_CHANNEL_DOMAIN_5G_ETSI2 = 0x02, //Australia, New Zealand ++ RT_CHANNEL_DOMAIN_5G_ETSI3 = 0x03, //Russia ++ RT_CHANNEL_DOMAIN_5G_FCC1 = 0x04, //US ++ RT_CHANNEL_DOMAIN_5G_FCC2 = 0x05, //FCC o/w DFS Channels ++ RT_CHANNEL_DOMAIN_5G_FCC3 = 0x06, //India, Mexico ++ RT_CHANNEL_DOMAIN_5G_FCC4 = 0x07, //Venezuela ++ RT_CHANNEL_DOMAIN_5G_FCC5 = 0x08, //China ++ RT_CHANNEL_DOMAIN_5G_FCC6 = 0x09, //Israel ++ RT_CHANNEL_DOMAIN_5G_FCC7_IC1 = 0x0A, //US, Canada ++ RT_CHANNEL_DOMAIN_5G_KCC1 = 0x0B, //Korea ++ RT_CHANNEL_DOMAIN_5G_MKK1 = 0x0C, //Japan ++ RT_CHANNEL_DOMAIN_5G_MKK2 = 0x0D, //Japan (W52, W53) ++ RT_CHANNEL_DOMAIN_5G_MKK3 = 0x0E, //Japan (W56) ++ RT_CHANNEL_DOMAIN_5G_NCC1 = 0x0F, //Taiwan ++ RT_CHANNEL_DOMAIN_5G_NCC2 = 0x10, //Taiwan o/w DFS ++ //===== Add new channel plan above this line===============// ++ //===== Driver Self Defined =====// ++ RT_CHANNEL_DOMAIN_5G_FCC = 0x11, ++ RT_CHANNEL_DOMAIN_5G_JAPAN_NO_DFS = 0x12, ++ RT_CHANNEL_DOMAIN_5G_MAX, ++}RT_CHANNEL_DOMAIN_5G, *PRT_CHANNEL_DOMAIN_5G; ++ ++#define rtw_is_channel_plan_valid(chplan) (chplan broadcast probe request ++// blnbc: 0 -> unicast probe request. The address 1 will be the BSSID. ++void issue_probereq(_adapter *padapter, NDIS_802_11_SSID *pssid, u8 blnbc); ++void issue_nulldata(_adapter *padapter, unsigned int power_mode); ++void issue_qos_nulldata(_adapter *padapter, unsigned char *da, u16 tid); ++void issue_deauth(_adapter *padapter, unsigned char *da, unsigned short reason); ++void issue_action_BA(_adapter *padapter, unsigned char *raddr, unsigned char action, unsigned short status); ++unsigned int send_delba(_adapter *padapter, u8 initiator, u8 *addr); ++unsigned int send_beacon(_adapter *padapter); ++ ++void start_clnt_assoc(_adapter *padapter); ++void start_clnt_auth(_adapter* padapter); ++void start_clnt_join(_adapter* padapter); ++void start_create_ibss(_adapter* padapter); ++ ++unsigned int OnAssocReq(_adapter *padapter, union recv_frame *precv_frame); ++unsigned int OnAssocRsp(_adapter *padapter, union recv_frame *precv_frame); ++unsigned int OnProbeReq(_adapter *padapter, union recv_frame *precv_frame); ++unsigned int OnProbeRsp(_adapter *padapter, union recv_frame *precv_frame); ++unsigned int DoReserved(_adapter *padapter, union recv_frame *precv_frame); ++unsigned int OnBeacon(_adapter *padapter, union recv_frame *precv_frame); ++unsigned int OnAtim(_adapter *padapter, union recv_frame *precv_frame); ++unsigned int OnDisassoc(_adapter *padapter, union recv_frame *precv_frame); ++unsigned int OnAuth(_adapter *padapter, union recv_frame *precv_frame); ++unsigned int OnAuthClient(_adapter *padapter, union recv_frame *precv_frame); ++unsigned int OnDeAuth(_adapter *padapter, union recv_frame *precv_frame); ++unsigned int OnAction(_adapter *padapter, union recv_frame *precv_frame); ++ ++unsigned int OnAction_qos(_adapter *padapter, union recv_frame *precv_frame); ++unsigned int OnAction_dls(_adapter *padapter, union recv_frame *precv_frame); ++unsigned int OnAction_back(_adapter *padapter, union recv_frame *precv_frame); ++unsigned int OnAction_public(_adapter *padapter, union recv_frame *precv_frame); ++unsigned int OnAction_ht(_adapter *padapter, union recv_frame *precv_frame); ++unsigned int OnAction_wmm(_adapter *padapter, union recv_frame *precv_frame); ++unsigned int OnAction_p2p(_adapter *padapter, union recv_frame *precv_frame); ++ ++ ++void mlmeext_joinbss_event_callback(_adapter *padapter, int join_res); ++void mlmeext_sta_del_event_callback(_adapter *padapter); ++void mlmeext_sta_add_event_callback(_adapter *padapter, struct sta_info *psta); ++ ++void linked_status_chk(_adapter *padapter); ++ ++void survey_timer_hdl (_adapter *padapter); ++void link_timer_hdl (_adapter *padapter); ++void addba_timer_hdl(struct sta_info *psta); ++//void reauth_timer_hdl(_adapter *padapter); ++//void reassoc_timer_hdl(_adapter *padapter); ++ ++#define set_survey_timer(mlmeext, ms) \ ++ do { \ ++ /*DBG_871X("%s set_survey_timer(%p, %d)\n", __FUNCTION__, (mlmeext), (ms));*/ \ ++ _set_timer(&(mlmeext)->survey_timer, (ms)); \ ++ } while(0) ++ ++#define set_link_timer(mlmeext, ms) \ ++ do { \ ++ /*DBG_871X("%s set_link_timer(%p, %d)\n", __FUNCTION__, (mlmeext), (ms));*/ \ ++ _set_timer(&(mlmeext)->link_timer, (ms)); \ ++ } while(0) ++ ++extern int cckrates_included(unsigned char *rate, int ratelen); ++extern int cckratesonly_included(unsigned char *rate, int ratelen); ++ ++extern void process_addba_req(_adapter *padapter, u8 *paddba_req, u8 *addr); ++ ++extern void update_TSF(struct mlme_ext_priv *pmlmeext, u8 *pframe, uint len); ++extern void correct_TSF(_adapter *padapter, struct mlme_ext_priv *pmlmeext); ++ ++#ifdef CONFIG_AP_MODE ++void init_mlme_ap_info(_adapter *padapter); ++void free_mlme_ap_info(_adapter *padapter); ++//void update_BCNTIM(_adapter *padapter); ++void update_beacon(_adapter *padapter, u8 ie_id, u8 *oui, u8 tx); ++void expire_timeout_chk(_adapter *padapter); ++void update_sta_info_apmode(_adapter *padapter, struct sta_info *psta); ++int rtw_check_beacon_data(_adapter *padapter, u8 *pbuf, int len); ++#ifdef CONFIG_NATIVEAP_MLME ++void bss_cap_update(_adapter *padapter, struct sta_info *psta); ++void sta_info_update(_adapter *padapter, struct sta_info *psta); ++void ap_sta_info_defer_update(_adapter *padapter, struct sta_info *psta); ++void ap_free_sta(_adapter *padapter, struct sta_info *psta); ++int rtw_sta_flush(_adapter *padapter); ++void start_ap_mode(_adapter *padapter); ++void stop_ap_mode(_adapter *padapter); ++#endif ++#endif //end of CONFIG_AP_MODE ++ ++struct cmd_hdl { ++ uint parmsize; ++ u8 (*h2cfuns)(struct _ADAPTER *padapter, u8 *pbuf); ++}; ++ ++ ++u8 read_macreg_hdl(_adapter *padapter, u8 *pbuf); ++u8 write_macreg_hdl(_adapter *padapter, u8 *pbuf); ++u8 read_bbreg_hdl(_adapter *padapter, u8 *pbuf); ++u8 write_bbreg_hdl(_adapter *padapter, u8 *pbuf); ++u8 read_rfreg_hdl(_adapter *padapter, u8 *pbuf); ++u8 write_rfreg_hdl(_adapter *padapter, u8 *pbuf); ++ ++ ++u8 NULL_hdl(_adapter *padapter, u8 *pbuf); ++u8 join_cmd_hdl(_adapter *padapter, u8 *pbuf); ++u8 disconnect_hdl(_adapter *padapter, u8 *pbuf); ++u8 createbss_hdl(_adapter *padapter, u8 *pbuf); ++u8 setopmode_hdl(_adapter *padapter, u8 *pbuf); ++u8 sitesurvey_cmd_hdl(_adapter *padapter, u8 *pbuf); ++u8 setauth_hdl(_adapter *padapter, u8 *pbuf); ++u8 setkey_hdl(_adapter *padapter, u8 *pbuf); ++u8 set_stakey_hdl(_adapter *padapter, u8 *pbuf); ++u8 set_assocsta_hdl(_adapter *padapter, u8 *pbuf); ++u8 del_assocsta_hdl(_adapter *padapter, u8 *pbuf); ++u8 add_ba_hdl(_adapter *padapter, unsigned char *pbuf); ++ ++u8 mlme_evt_hdl(_adapter *padapter, unsigned char *pbuf); ++u8 h2c_msg_hdl(_adapter *padapter, unsigned char *pbuf); ++u8 tx_beacon_hdl(_adapter *padapter, unsigned char *pbuf); ++u8 set_chplan_hdl(_adapter *padapter, unsigned char *pbuf); ++u8 led_blink_hdl(_adapter *padapter, unsigned char *pbuf); ++u8 set_csa_hdl(_adapter *padapter, unsigned char *pbuf); //Kurt: Handling DFS channel switch announcement ie. ++u8 tdls_hdl(_adapter *padapter, unsigned char *pbuf); ++ ++ ++#define GEN_DRV_CMD_HANDLER(size, cmd) {size, &cmd ## _hdl}, ++#define GEN_MLME_EXT_HANDLER(size, cmd) {size, cmd}, ++ ++#ifdef _RTW_CMD_C_ ++ ++struct cmd_hdl wlancmds[] = ++{ ++ GEN_DRV_CMD_HANDLER(0, NULL) /*0*/ ++ GEN_DRV_CMD_HANDLER(0, NULL) ++ GEN_DRV_CMD_HANDLER(0, NULL) ++ GEN_DRV_CMD_HANDLER(0, NULL) ++ GEN_DRV_CMD_HANDLER(0, NULL) ++ GEN_DRV_CMD_HANDLER(0, NULL) ++ GEN_MLME_EXT_HANDLER(0, NULL) ++ GEN_MLME_EXT_HANDLER(0, NULL) ++ GEN_MLME_EXT_HANDLER(0, NULL) ++ GEN_MLME_EXT_HANDLER(0, NULL) ++ GEN_MLME_EXT_HANDLER(0, NULL) /*10*/ ++ GEN_MLME_EXT_HANDLER(0, NULL) ++ GEN_MLME_EXT_HANDLER(0, NULL) ++ GEN_MLME_EXT_HANDLER(0, NULL) ++ GEN_MLME_EXT_HANDLER(sizeof (struct joinbss_parm), join_cmd_hdl) /*14*/ ++ GEN_MLME_EXT_HANDLER(sizeof (struct disconnect_parm), disconnect_hdl) ++ GEN_MLME_EXT_HANDLER(sizeof (struct createbss_parm), createbss_hdl) ++ GEN_MLME_EXT_HANDLER(sizeof (struct setopmode_parm), setopmode_hdl) ++ GEN_MLME_EXT_HANDLER(sizeof (struct sitesurvey_parm), sitesurvey_cmd_hdl) /*18*/ ++ GEN_MLME_EXT_HANDLER(sizeof (struct setauth_parm), setauth_hdl) ++ GEN_MLME_EXT_HANDLER(sizeof (struct setkey_parm), setkey_hdl) /*20*/ ++ GEN_MLME_EXT_HANDLER(sizeof (struct set_stakey_parm), set_stakey_hdl) ++ GEN_MLME_EXT_HANDLER(sizeof (struct set_assocsta_parm), NULL) ++ GEN_MLME_EXT_HANDLER(sizeof (struct del_assocsta_parm), NULL) ++ GEN_MLME_EXT_HANDLER(sizeof (struct setstapwrstate_parm), NULL) ++ GEN_MLME_EXT_HANDLER(sizeof (struct setbasicrate_parm), NULL) ++ GEN_MLME_EXT_HANDLER(sizeof (struct getbasicrate_parm), NULL) ++ GEN_MLME_EXT_HANDLER(sizeof (struct setdatarate_parm), NULL) ++ GEN_MLME_EXT_HANDLER(sizeof (struct getdatarate_parm), NULL) ++ GEN_MLME_EXT_HANDLER(sizeof (struct setphyinfo_parm), NULL) ++ GEN_MLME_EXT_HANDLER(sizeof (struct getphyinfo_parm), NULL) /*30*/ ++ GEN_MLME_EXT_HANDLER(sizeof (struct setphy_parm), NULL) ++ GEN_MLME_EXT_HANDLER(sizeof (struct getphy_parm), NULL) ++ GEN_MLME_EXT_HANDLER(0, NULL) ++ GEN_MLME_EXT_HANDLER(0, NULL) ++ GEN_MLME_EXT_HANDLER(0, NULL) ++ GEN_MLME_EXT_HANDLER(0, NULL) ++ GEN_MLME_EXT_HANDLER(0, NULL) ++ GEN_MLME_EXT_HANDLER(0, NULL) ++ GEN_MLME_EXT_HANDLER(0, NULL) ++ GEN_MLME_EXT_HANDLER(0, NULL) /*40*/ ++ GEN_MLME_EXT_HANDLER(0, NULL) ++ GEN_MLME_EXT_HANDLER(0, NULL) ++ GEN_MLME_EXT_HANDLER(0, NULL) ++ GEN_MLME_EXT_HANDLER(0, NULL) ++ GEN_MLME_EXT_HANDLER(sizeof(struct addBaReq_parm), add_ba_hdl) ++ GEN_MLME_EXT_HANDLER(0, NULL) ++ GEN_MLME_EXT_HANDLER(0, NULL) ++ GEN_MLME_EXT_HANDLER(0, NULL) ++ GEN_MLME_EXT_HANDLER(0, NULL) ++ GEN_MLME_EXT_HANDLER(0, NULL) /*50*/ ++ GEN_MLME_EXT_HANDLER(0, NULL) ++ GEN_MLME_EXT_HANDLER(0, NULL) ++ GEN_MLME_EXT_HANDLER(0, NULL) ++ GEN_MLME_EXT_HANDLER(0, NULL) ++ GEN_MLME_EXT_HANDLER(sizeof(struct Tx_Beacon_param), tx_beacon_hdl) /*55*/ ++ ++ GEN_MLME_EXT_HANDLER(0, mlme_evt_hdl) /*56*/ ++ GEN_MLME_EXT_HANDLER(0, rtw_drvextra_cmd_hdl) /*57*/ ++ ++ GEN_MLME_EXT_HANDLER(0, h2c_msg_hdl) /*58*/ ++ GEN_MLME_EXT_HANDLER(sizeof(struct SetChannelPlan_param), set_chplan_hdl) /*59*/ ++ GEN_MLME_EXT_HANDLER(sizeof(struct LedBlink_param), led_blink_hdl) /*60*/ ++ GEN_MLME_EXT_HANDLER(sizeof(struct SetChannelSwitch_param), set_csa_hdl) /*61*/ ++ GEN_MLME_EXT_HANDLER(sizeof(struct TDLSoption_param), tdls_hdl) /*62*/ ++}; ++ ++#endif ++ ++struct C2HEvent_Header ++{ ++ ++#ifdef CONFIG_LITTLE_ENDIAN ++ ++ unsigned int len:16; ++ unsigned int ID:8; ++ unsigned int seq:8; ++ ++#elif defined(CONFIG_BIG_ENDIAN) ++ ++ unsigned int seq:8; ++ unsigned int ID:8; ++ unsigned int len:16; ++ ++#else ++ ++# error "Must be LITTLE or BIG Endian" ++ ++#endif ++ ++ unsigned int rsvd; ++ ++}; ++ ++void rtw_dummy_event_callback(_adapter *adapter , u8 *pbuf); ++void rtw_fwdbg_event_callback(_adapter *adapter , u8 *pbuf); ++ ++enum rtw_c2h_event ++{ ++ GEN_EVT_CODE(_Read_MACREG)=0, /*0*/ ++ GEN_EVT_CODE(_Read_BBREG), ++ GEN_EVT_CODE(_Read_RFREG), ++ GEN_EVT_CODE(_Read_EEPROM), ++ GEN_EVT_CODE(_Read_EFUSE), ++ GEN_EVT_CODE(_Read_CAM), /*5*/ ++ GEN_EVT_CODE(_Get_BasicRate), ++ GEN_EVT_CODE(_Get_DataRate), ++ GEN_EVT_CODE(_Survey), /*8*/ ++ GEN_EVT_CODE(_SurveyDone), /*9*/ ++ ++ GEN_EVT_CODE(_JoinBss) , /*10*/ ++ GEN_EVT_CODE(_AddSTA), ++ GEN_EVT_CODE(_DelSTA), ++ GEN_EVT_CODE(_AtimDone) , ++ GEN_EVT_CODE(_TX_Report), ++ GEN_EVT_CODE(_CCX_Report), /*15*/ ++ GEN_EVT_CODE(_DTM_Report), ++ GEN_EVT_CODE(_TX_Rate_Statistics), ++ GEN_EVT_CODE(_C2HLBK), ++ GEN_EVT_CODE(_FWDBG), ++ GEN_EVT_CODE(_C2HFEEDBACK), /*20*/ ++ GEN_EVT_CODE(_ADDBA), ++ GEN_EVT_CODE(_C2HBCN), ++ GEN_EVT_CODE(_ReportPwrState), //filen: only for PCIE, USB ++ GEN_EVT_CODE(_CloseRF), //filen: only for PCIE, work around ASPM ++ MAX_C2HEVT ++}; ++ ++ ++#ifdef _RTW_MLME_EXT_C_ ++ ++static struct fwevent wlanevents[] = ++{ ++ {0, rtw_dummy_event_callback}, /*0*/ ++ {0, NULL}, ++ {0, NULL}, ++ {0, NULL}, ++ {0, NULL}, ++ {0, NULL}, ++ {0, NULL}, ++ {0, NULL}, ++ {0, &rtw_survey_event_callback}, /*8*/ ++ {sizeof (struct surveydone_event), &rtw_surveydone_event_callback}, /*9*/ ++ ++ {0, &rtw_joinbss_event_callback}, /*10*/ ++ {sizeof(struct stassoc_event), &rtw_stassoc_event_callback}, ++ {sizeof(struct stadel_event), &rtw_stadel_event_callback}, ++ {0, &rtw_atimdone_event_callback}, ++ {0, rtw_dummy_event_callback}, ++ {0, NULL}, /*15*/ ++ {0, NULL}, ++ {0, NULL}, ++ {0, NULL}, ++ {0, rtw_fwdbg_event_callback}, ++ {0, NULL}, /*20*/ ++ {0, NULL}, ++ {0, NULL}, ++ {0, &rtw_cpwm_event_callback}, ++}; ++ ++#endif//_RTL8192C_CMD_C_ ++ ++#endif ++ +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/include/rtw_mp.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/include/rtw_mp.h 2013-07-26 19:36:06.000000000 +0000 +@@ -0,0 +1,708 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef _RTW_MP_H_ ++#define _RTW_MP_H_ ++ ++#ifndef PLATFORM_WINDOWS ++// 00 - Success ++// 11 - Error ++#define STATUS_SUCCESS (0x00000000L) ++#define STATUS_PENDING (0x00000103L) ++ ++#define STATUS_UNSUCCESSFUL (0xC0000001L) ++#define STATUS_INSUFFICIENT_RESOURCES (0xC000009AL) ++#define STATUS_NOT_SUPPORTED (0xC00000BBL) ++ ++#define NDIS_STATUS_SUCCESS ((NDIS_STATUS)STATUS_SUCCESS) ++#define NDIS_STATUS_PENDING ((NDIS_STATUS)STATUS_PENDING) ++#define NDIS_STATUS_NOT_RECOGNIZED ((NDIS_STATUS)0x00010001L) ++#define NDIS_STATUS_NOT_COPIED ((NDIS_STATUS)0x00010002L) ++#define NDIS_STATUS_NOT_ACCEPTED ((NDIS_STATUS)0x00010003L) ++#define NDIS_STATUS_CALL_ACTIVE ((NDIS_STATUS)0x00010007L) ++ ++#define NDIS_STATUS_FAILURE ((NDIS_STATUS)STATUS_UNSUCCESSFUL) ++#define NDIS_STATUS_RESOURCES ((NDIS_STATUS)STATUS_INSUFFICIENT_RESOURCES) ++#define NDIS_STATUS_CLOSING ((NDIS_STATUS)0xC0010002L) ++#define NDIS_STATUS_BAD_VERSION ((NDIS_STATUS)0xC0010004L) ++#define NDIS_STATUS_BAD_CHARACTERISTICS ((NDIS_STATUS)0xC0010005L) ++#define NDIS_STATUS_ADAPTER_NOT_FOUND ((NDIS_STATUS)0xC0010006L) ++#define NDIS_STATUS_OPEN_FAILED ((NDIS_STATUS)0xC0010007L) ++#define NDIS_STATUS_DEVICE_FAILED ((NDIS_STATUS)0xC0010008L) ++#define NDIS_STATUS_MULTICAST_FULL ((NDIS_STATUS)0xC0010009L) ++#define NDIS_STATUS_MULTICAST_EXISTS ((NDIS_STATUS)0xC001000AL) ++#define NDIS_STATUS_MULTICAST_NOT_FOUND ((NDIS_STATUS)0xC001000BL) ++#define NDIS_STATUS_REQUEST_ABORTED ((NDIS_STATUS)0xC001000CL) ++#define NDIS_STATUS_RESET_IN_PROGRESS ((NDIS_STATUS)0xC001000DL) ++#define NDIS_STATUS_CLOSING_INDICATING ((NDIS_STATUS)0xC001000EL) ++#define NDIS_STATUS_NOT_SUPPORTED ((NDIS_STATUS)STATUS_NOT_SUPPORTED) ++#define NDIS_STATUS_INVALID_PACKET ((NDIS_STATUS)0xC001000FL) ++#define NDIS_STATUS_OPEN_LIST_FULL ((NDIS_STATUS)0xC0010010L) ++#define NDIS_STATUS_ADAPTER_NOT_READY ((NDIS_STATUS)0xC0010011L) ++#define NDIS_STATUS_ADAPTER_NOT_OPEN ((NDIS_STATUS)0xC0010012L) ++#define NDIS_STATUS_NOT_INDICATING ((NDIS_STATUS)0xC0010013L) ++#define NDIS_STATUS_INVALID_LENGTH ((NDIS_STATUS)0xC0010014L) ++#define NDIS_STATUS_INVALID_DATA ((NDIS_STATUS)0xC0010015L) ++#define NDIS_STATUS_BUFFER_TOO_SHORT ((NDIS_STATUS)0xC0010016L) ++#define NDIS_STATUS_INVALID_OID ((NDIS_STATUS)0xC0010017L) ++#define NDIS_STATUS_ADAPTER_REMOVED ((NDIS_STATUS)0xC0010018L) ++#define NDIS_STATUS_UNSUPPORTED_MEDIA ((NDIS_STATUS)0xC0010019L) ++#define NDIS_STATUS_GROUP_ADDRESS_IN_USE ((NDIS_STATUS)0xC001001AL) ++#define NDIS_STATUS_FILE_NOT_FOUND ((NDIS_STATUS)0xC001001BL) ++#define NDIS_STATUS_ERROR_READING_FILE ((NDIS_STATUS)0xC001001CL) ++#define NDIS_STATUS_ALREADY_MAPPED ((NDIS_STATUS)0xC001001DL) ++#define NDIS_STATUS_RESOURCE_CONFLICT ((NDIS_STATUS)0xC001001EL) ++#define NDIS_STATUS_NO_CABLE ((NDIS_STATUS)0xC001001FL) ++ ++#define NDIS_STATUS_INVALID_SAP ((NDIS_STATUS)0xC0010020L) ++#define NDIS_STATUS_SAP_IN_USE ((NDIS_STATUS)0xC0010021L) ++#define NDIS_STATUS_INVALID_ADDRESS ((NDIS_STATUS)0xC0010022L) ++#define NDIS_STATUS_VC_NOT_ACTIVATED ((NDIS_STATUS)0xC0010023L) ++#define NDIS_STATUS_DEST_OUT_OF_ORDER ((NDIS_STATUS)0xC0010024L) // cause 27 ++#define NDIS_STATUS_VC_NOT_AVAILABLE ((NDIS_STATUS)0xC0010025L) // cause 35,45 ++#define NDIS_STATUS_CELLRATE_NOT_AVAILABLE ((NDIS_STATUS)0xC0010026L) // cause 37 ++#define NDIS_STATUS_INCOMPATABLE_QOS ((NDIS_STATUS)0xC0010027L) // cause 49 ++#define NDIS_STATUS_AAL_PARAMS_UNSUPPORTED ((NDIS_STATUS)0xC0010028L) // cause 93 ++#define NDIS_STATUS_NO_ROUTE_TO_DESTINATION ((NDIS_STATUS)0xC0010029L) // cause 3 ++#endif /* #ifndef PLATFORM_WINDOWS */ ++ ++#if 0 ++#define MPT_NOOP 0 ++#define MPT_READ_MAC_1BYTE 1 ++#define MPT_READ_MAC_2BYTE 2 ++#define MPT_READ_MAC_4BYTE 3 ++#define MPT_WRITE_MAC_1BYTE 4 ++#define MPT_WRITE_MAC_2BYTE 5 ++#define MPT_WRITE_MAC_4BYTE 6 ++#define MPT_READ_BB_CCK 7 ++#define MPT_WRITE_BB_CCK 8 ++#define MPT_READ_BB_OFDM 9 ++#define MPT_WRITE_BB_OFDM 10 ++#define MPT_READ_RF 11 ++#define MPT_WRITE_RF 12 ++#define MPT_READ_EEPROM_1BYTE 13 ++#define MPT_WRITE_EEPROM_1BYTE 14 ++#define MPT_READ_EEPROM_2BYTE 15 ++#define MPT_WRITE_EEPROM_2BYTE 16 ++#define MPT_SET_CSTHRESHOLD 21 ++#define MPT_SET_INITGAIN 22 ++#define MPT_SWITCH_BAND 23 ++#define MPT_SWITCH_CHANNEL 24 ++#define MPT_SET_DATARATE 25 ++#define MPT_SWITCH_ANTENNA 26 ++#define MPT_SET_TX_POWER 27 ++#define MPT_SET_CONT_TX 28 ++#define MPT_SET_SINGLE_CARRIER 29 ++#define MPT_SET_CARRIER_SUPPRESSION 30 ++#define MPT_GET_RATE_TABLE 31 ++#define MPT_READ_TSSI 32 ++#define MPT_GET_THERMAL_METER 33 ++#endif ++ ++#define MAX_MP_XMITBUF_SZ 2048 ++#define NR_MP_XMITFRAME 8 ++ ++struct mp_xmit_frame ++{ ++ _list list; ++ ++ struct pkt_attrib attrib; ++ ++ _pkt *pkt; ++ ++ int frame_tag; ++ ++ _adapter *padapter; ++ ++#ifdef CONFIG_USB_HCI ++ ++ //insert urb, irp, and irpcnt info below... ++ //max frag_cnt = 8 ++ ++ u8 *mem_addr; ++ u32 sz[8]; ++ ++#if defined(PLATFORM_OS_XP) || defined(PLATFORM_LINUX) ++ PURB pxmit_urb[8]; ++#endif ++ ++#ifdef PLATFORM_OS_XP ++ PIRP pxmit_irp[8]; ++#endif ++ ++ u8 bpending[8]; ++ sint ac_tag[8]; ++ sint last[8]; ++ uint irpcnt; ++ uint fragcnt; ++#endif /* CONFIG_USB_HCI */ ++ ++ uint mem[(MAX_MP_XMITBUF_SZ >> 2)]; ++}; ++ ++struct mp_wiparam ++{ ++ u32 bcompleted; ++ u32 act_type; ++ u32 io_offset; ++ u32 io_value; ++}; ++ ++typedef void(*wi_act_func)(void* padapter); ++ ++#ifdef PLATFORM_WINDOWS ++struct mp_wi_cntx ++{ ++ u8 bmpdrv_unload; ++ ++ // Work Item ++ NDIS_WORK_ITEM mp_wi; ++ NDIS_EVENT mp_wi_evt; ++ _lock mp_wi_lock; ++ u8 bmp_wi_progress; ++ wi_act_func curractfunc; ++ // Variable needed in each implementation of CurrActFunc. ++ struct mp_wiparam param; ++}; ++#endif ++ ++struct mp_tx ++{ ++ u8 stop; ++ u32 count, sended; ++ u8 payload; ++ struct pkt_attrib attrib; ++ struct tx_desc desc; ++ u8 *pallocated_buf; ++ u8 *buf; ++ u32 buf_size, write_size; ++ _thread_hdl_ PktTxThread; ++}; ++ ++//#if (MP_DRIVER == 1) ++#if defined(CONFIG_RTL8192C) || defined(CONFIG_RTL8192D) || defined(CONFIG_RTL8723A) || defined(CONFIG_RTL8188E) ++#ifdef CONFIG_RTL8192C ++#include ++#endif ++#ifdef CONFIG_RTL8192D ++#include ++#endif ++#ifdef CONFIG_RTL8723A ++#include ++#endif ++#ifdef CONFIG_RTL8188E ++#include ++#endif ++#define MP_MAX_LINES 1000 ++#define MP_MAX_LINES_BYTES 256 ++#define u1Byte u8 ++#define s1Byte s8 ++#define u4Byte u32 ++#define s4Byte s32 ++typedef VOID (*MPT_WORK_ITEM_HANDLER)(IN PVOID Adapter); ++typedef struct _MPT_CONTEXT ++{ ++ // Indicate if we have started Mass Production Test. ++ BOOLEAN bMassProdTest; ++ ++ // Indicate if the driver is unloading or unloaded. ++ BOOLEAN bMptDrvUnload; ++ ++ /* 8190 PCI does not support NDIS_WORK_ITEM. */ ++ // Work Item for Mass Production Test. ++ //NDIS_WORK_ITEM MptWorkItem; ++// RT_WORK_ITEM MptWorkItem; ++ // Event used to sync the case unloading driver and MptWorkItem is still in progress. ++// NDIS_EVENT MptWorkItemEvent; ++ // To protect the following variables. ++// NDIS_SPIN_LOCK MptWorkItemSpinLock; ++ // Indicate a MptWorkItem is scheduled and not yet finished. ++ BOOLEAN bMptWorkItemInProgress; ++ // An instance which implements function and context of MptWorkItem. ++ MPT_WORK_ITEM_HANDLER CurrMptAct; ++ ++ // 1=Start, 0=Stop from UI. ++ ULONG MptTestStart; ++ // _TEST_MODE, defined in MPT_Req2.h ++ ULONG MptTestItem; ++ // Variable needed in each implementation of CurrMptAct. ++ ULONG MptActType; // Type of action performed in CurrMptAct. ++ // The Offset of IO operation is depend of MptActType. ++ ULONG MptIoOffset; ++ // The Value of IO operation is depend of MptActType. ++ ULONG MptIoValue; ++ // The RfPath of IO operation is depend of MptActType. ++ ULONG MptRfPath; ++ ++ WIRELESS_MODE MptWirelessModeToSw; // Wireless mode to switch. ++ u8 MptChannelToSw; // Channel to switch. ++ u8 MptInitGainToSet; // Initial gain to set. ++ //ULONG bMptAntennaA; // TRUE if we want to use antenna A. ++ ULONG MptBandWidth; // bandwidth to switch. ++ ULONG MptRateIndex; // rate index. ++ // Register value kept for Single Carrier Tx test. ++ u8 btMpCckTxPower; ++ // Register value kept for Single Carrier Tx test. ++ u8 btMpOfdmTxPower; ++ // For MP Tx Power index ++ u8 TxPwrLevel[2]; // rf-A, rf-B ++ ++ // Content of RCR Regsiter for Mass Production Test. ++ ULONG MptRCR; ++ // TRUE if we only receive packets with specific pattern. ++ BOOLEAN bMptFilterPattern; ++ // Rx OK count, statistics used in Mass Production Test. ++ ULONG MptRxOkCnt; ++ // Rx CRC32 error count, statistics used in Mass Production Test. ++ ULONG MptRxCrcErrCnt; ++ ++ BOOLEAN bCckContTx; // TRUE if we are in CCK Continuous Tx test. ++ BOOLEAN bOfdmContTx; // TRUE if we are in OFDM Continuous Tx test. ++ BOOLEAN bStartContTx; // TRUE if we have start Continuous Tx test. ++ // TRUE if we are in Single Carrier Tx test. ++ BOOLEAN bSingleCarrier; ++ // TRUE if we are in Carrier Suppression Tx Test. ++ BOOLEAN bCarrierSuppression; ++ //TRUE if we are in Single Tone Tx test. ++ BOOLEAN bSingleTone; ++ ++ // ACK counter asked by K.Y.. ++ BOOLEAN bMptEnableAckCounter; ++ ULONG MptAckCounter; ++ ++ // SD3 Willis For 8192S to save 1T/2T RF table for ACUT Only fro ACUT delete later ~~~! ++ //s1Byte BufOfLines[2][MAX_LINES_HWCONFIG_TXT][MAX_BYTES_LINE_HWCONFIG_TXT]; ++ //s1Byte BufOfLines[2][MP_MAX_LINES][MP_MAX_LINES_BYTES]; ++ //s4Byte RfReadLine[2]; ++ ++ u8 APK_bound[2]; //for APK path A/path B ++ BOOLEAN bMptIndexEven; ++ ++ u8 backup0xc50; ++ u8 backup0xc58; ++ u8 backup0xc30; ++}MPT_CONTEXT, *PMPT_CONTEXT; ++#endif ++//#endif ++ ++/* E-Fuse */ ++#ifdef CONFIG_RTL8192D ++#define EFUSE_MAP_SIZE 255 ++#endif ++#ifdef CONFIG_RTL8192C ++#define EFUSE_MAP_SIZE 128 ++#endif ++#ifdef CONFIG_RTL8723A ++#define EFUSE_MAP_SIZE 256 ++#endif ++#ifdef CONFIG_RTL8188E ++#define EFUSE_MAP_SIZE 256 ++#endif ++#define EFUSE_MAX_SIZE 512 ++ ++/* end of E-Fuse */ ++ ++//#define RTPRIV_IOCTL_MP ( SIOCIWFIRSTPRIV + 0x17) ++enum { ++ WRITE_REG = 1, ++ READ_REG, ++ WRITE_RF, ++ READ_RF, ++ MP_START, ++ MP_STOP, ++ MP_RATE, ++ MP_CHANNEL, ++ MP_BANDWIDTH, ++ MP_TXPOWER, ++ MP_ANT_TX, ++ MP_ANT_RX, ++ MP_CTX, ++ MP_QUERY, ++ MP_ARX, ++ MP_PSD, ++ MP_PWRTRK, ++ MP_THER, ++ MP_IOCTL, ++ EFUSE_GET, ++ EFUSE_SET, ++ MP_RESET_STATS, ++ MP_DUMP, ++ MP_PHYPARA, ++ MP_NULL, ++}; ++ ++struct mp_priv ++{ ++ _adapter *papdater; ++ ++ //Testing Flag ++ u32 mode;//0 for normal type packet, 1 for loopback packet (16bytes TXCMD) ++ ++ u32 prev_fw_state; ++ ++ //OID cmd handler ++ struct mp_wiparam workparam; ++// u8 act_in_progress; ++ ++ //Tx Section ++ u8 TID; ++ u32 tx_pktcount; ++ struct mp_tx tx; ++ ++ //Rx Section ++ u32 rx_pktcount; ++ u32 rx_crcerrpktcount; ++ u32 rx_pktloss; ++ ++ struct recv_stat rxstat; ++ ++ //RF/BB relative ++ u8 channel; ++ u8 bandwidth; ++ u8 prime_channel_offset; ++ u8 txpoweridx; ++ u8 txpoweridx_b; ++ u8 rateidx; ++ u32 preamble; ++// u8 modem; ++ u32 CrystalCap; ++// u32 curr_crystalcap; ++ ++ u16 antenna_tx; ++ u16 antenna_rx; ++// u8 curr_rfpath; ++ ++ u8 check_mp_pkt; ++ ++// uint ForcedDataRate; ++ ++ struct wlan_network mp_network; ++ NDIS_802_11_MAC_ADDRESS network_macaddr; ++ ++#ifdef PLATFORM_WINDOWS ++ u32 rx_testcnt; ++ u32 rx_testcnt1; ++ u32 rx_testcnt2; ++ u32 tx_testcnt; ++ u32 tx_testcnt1; ++ ++ struct mp_wi_cntx wi_cntx; ++ ++ u8 h2c_result; ++ u8 h2c_seqnum; ++ u16 h2c_cmdcode; ++ u8 h2c_resp_parambuf[512]; ++ _lock h2c_lock; ++ _lock wkitm_lock; ++ u32 h2c_cmdcnt; ++ NDIS_EVENT h2c_cmd_evt; ++ NDIS_EVENT c2h_set; ++ NDIS_EVENT h2c_clr; ++ NDIS_EVENT cpwm_int; ++ ++ NDIS_EVENT scsir_full_evt; ++ NDIS_EVENT scsiw_empty_evt; ++#endif ++ ++ u8 *pallocated_mp_xmitframe_buf; ++ u8 *pmp_xmtframe_buf; ++ _queue free_mp_xmitqueue; ++ u32 free_mp_xmitframe_cnt; ++ ++ MPT_CONTEXT MptCtx; ++}; ++ ++typedef struct _IOCMD_STRUCT_ { ++ u8 cmdclass; ++ u16 value; ++ u8 index; ++}IOCMD_STRUCT; ++ ++struct rf_reg_param { ++ u32 path; ++ u32 offset; ++ u32 value; ++}; ++ ++struct bb_reg_param { ++ u32 offset; ++ u32 value; ++}; ++//======================================================================= ++ ++#define LOWER _TRUE ++#define RAISE _FALSE ++ ++/* Hardware Registers */ ++#if 0 ++#if 0 ++#define IOCMD_CTRL_REG 0x102502C0 ++#define IOCMD_DATA_REG 0x102502C4 ++#else ++#define IOCMD_CTRL_REG 0x10250370 ++#define IOCMD_DATA_REG 0x10250374 ++#endif ++ ++#define IOCMD_GET_THERMAL_METER 0xFD000028 ++ ++#define IOCMD_CLASS_BB_RF 0xF0 ++#define IOCMD_BB_READ_IDX 0x00 ++#define IOCMD_BB_WRITE_IDX 0x01 ++#define IOCMD_RF_READ_IDX 0x02 ++#define IOCMD_RF_WRIT_IDX 0x03 ++#endif ++#define BB_REG_BASE_ADDR 0x800 ++ ++/* MP variables */ ++#if 0 ++#define _2MAC_MODE_ 0 ++#define _LOOPBOOK_MODE_ 1 ++#endif ++typedef enum _MP_MODE_ { ++ MP_OFF, ++ MP_ON, ++ MP_ERR, ++ MP_CONTINUOUS_TX, ++ MP_SINGLE_CARRIER_TX, ++ MP_CARRIER_SUPPRISSION_TX, ++ MP_SINGLE_TONE_TX, ++ MP_PACKET_TX, ++ MP_PACKET_RX ++} MP_MODE; ++ ++#ifdef CONFIG_RTL8192C ++#define RF_PATH_A RF_PATH_A ++#define RF_PATH_B RF_PATH_B ++#define RF_PATH_C RF_PATH_C ++#define RF_PATH_D RF_PATH_D ++ ++#define MAX_RF_PATH_NUMS RF_PATH_MAX ++#else ++#define RF_PATH_A 0 ++#define RF_PATH_B 1 ++#define RF_PATH_C 2 ++#define RF_PATH_D 3 ++ ++#define MAX_RF_PATH_NUMS 2 ++#endif ++ ++extern u8 mpdatarate[NumRates]; ++ ++/* MP set force data rate base on the definition. */ ++typedef enum _MPT_RATE_INDEX ++{ ++ /* CCK rate. */ ++ MPT_RATE_1M, /* 0 */ ++ MPT_RATE_2M, ++ MPT_RATE_55M, ++ MPT_RATE_11M, /* 3 */ ++ ++ /* OFDM rate. */ ++ MPT_RATE_6M, /* 4 */ ++ MPT_RATE_9M, ++ MPT_RATE_12M, ++ MPT_RATE_18M, ++ MPT_RATE_24M, ++ MPT_RATE_36M, ++ MPT_RATE_48M, ++ MPT_RATE_54M, /* 11 */ ++ ++ /* HT rate. */ ++ MPT_RATE_MCS0, /* 12 */ ++ MPT_RATE_MCS1, ++ MPT_RATE_MCS2, ++ MPT_RATE_MCS3, ++ MPT_RATE_MCS4, ++ MPT_RATE_MCS5, ++ MPT_RATE_MCS6, ++ MPT_RATE_MCS7, /* 19 */ ++ MPT_RATE_MCS8, ++ MPT_RATE_MCS9, ++ MPT_RATE_MCS10, ++ MPT_RATE_MCS11, ++ MPT_RATE_MCS12, ++ MPT_RATE_MCS13, ++ MPT_RATE_MCS14, ++ MPT_RATE_MCS15, /* 27 */ ++ MPT_RATE_LAST ++}MPT_RATE_E, *PMPT_RATE_E; ++ ++#if 0 ++// Represent Channel Width in HT Capabilities ++typedef enum _HT_CHANNEL_WIDTH { ++ HT_CHANNEL_WIDTH_20 = 0, ++ HT_CHANNEL_WIDTH_40 = 1, ++}HT_CHANNEL_WIDTH, *PHT_CHANNEL_WIDTH; ++#endif ++ ++#define MAX_TX_PWR_INDEX_N_MODE 64 // 0x3F ++ ++typedef enum _POWER_MODE_ { ++ POWER_LOW = 0, ++ POWER_NORMAL ++}POWER_MODE; ++ ++ ++#define RX_PKT_BROADCAST 1 ++#define RX_PKT_DEST_ADDR 2 ++#define RX_PKT_PHY_MATCH 3 ++ ++#if 0 ++#define RPTMaxCount 0x000FFFFF; ++ ++// parameter 1 : BitMask ++// bit 0 : OFDM PPDU ++// bit 1 : OFDM False Alarm ++// bit 2 : OFDM MPDU OK ++// bit 3 : OFDM MPDU Fail ++// bit 4 : CCK PPDU ++// bit 5 : CCK False Alarm ++// bit 6 : CCK MPDU ok ++// bit 7 : CCK MPDU fail ++// bit 8 : HT PPDU counter ++// bit 9 : HT false alarm ++// bit 10 : HT MPDU total ++// bit 11 : HT MPDU OK ++// bit 12 : HT MPDU fail ++// bit 15 : RX full drop ++typedef enum _RXPHY_BITMASK_ ++{ ++ OFDM_PPDU_BIT = 0, ++ OFDM_FALSE_BIT, ++ OFDM_MPDU_OK_BIT, ++ OFDM_MPDU_FAIL_BIT, ++ CCK_PPDU_BIT, ++ CCK_FALSE_BIT, ++ CCK_MPDU_OK_BIT, ++ CCK_MPDU_FAIL_BIT, ++ HT_PPDU_BIT, ++ HT_FALSE_BIT, ++ HT_MPDU_BIT, ++ HT_MPDU_OK_BIT, ++ HT_MPDU_FAIL_BIT, ++} RXPHY_BITMASK; ++#endif ++ ++typedef enum _ENCRY_CTRL_STATE_ { ++ HW_CONTROL, //hw encryption& decryption ++ SW_CONTROL, //sw encryption& decryption ++ HW_ENCRY_SW_DECRY, //hw encryption & sw decryption ++ SW_ENCRY_HW_DECRY //sw encryption & hw decryption ++}ENCRY_CTRL_STATE; ++ ++ ++//======================================================================= ++//extern struct mp_xmit_frame *alloc_mp_xmitframe(struct mp_priv *pmp_priv); ++//extern int free_mp_xmitframe(struct xmit_priv *pxmitpriv, struct mp_xmit_frame *pmp_xmitframe); ++ ++extern s32 init_mp_priv(PADAPTER padapter); ++extern void free_mp_priv(struct mp_priv *pmp_priv); ++extern s32 MPT_InitializeAdapter(PADAPTER padapter, u8 Channel); ++extern void MPT_DeInitAdapter(PADAPTER padapter); ++extern s32 mp_start_test(PADAPTER padapter); ++extern void mp_stop_test(PADAPTER padapter); ++ ++//======================================================================= ++//extern void IQCalibrateBcut(PADAPTER pAdapter); ++ ++//extern u32 bb_reg_read(PADAPTER Adapter, u16 offset); ++//extern u8 bb_reg_write(PADAPTER Adapter, u16 offset, u32 value); ++//extern u32 rf_reg_read(PADAPTER Adapter, u8 path, u8 offset); ++//extern u8 rf_reg_write(PADAPTER Adapter, u8 path, u8 offset, u32 value); ++ ++//extern u32 get_bb_reg(PADAPTER Adapter, u16 offset, u32 bitmask); ++//extern u8 set_bb_reg(PADAPTER Adapter, u16 offset, u32 bitmask, u32 value); ++//extern u32 get_rf_reg(PADAPTER Adapter, u8 path, u8 offset, u32 bitmask); ++//extern u8 set_rf_reg(PADAPTER Adapter, u8 path, u8 offset, u32 bitmask, u32 value); ++ ++extern u32 _read_rfreg(PADAPTER padapter, u8 rfpath, u32 addr, u32 bitmask); ++extern void _write_rfreg(PADAPTER padapter, u8 rfpath, u32 addr, u32 bitmask, u32 val); ++ ++extern u32 read_macreg(_adapter *padapter, u32 addr, u32 sz); ++extern void write_macreg(_adapter *padapter, u32 addr, u32 val, u32 sz); ++extern u32 read_bbreg(_adapter *padapter, u32 addr, u32 bitmask); ++extern void write_bbreg(_adapter *padapter, u32 addr, u32 bitmask, u32 val); ++extern u32 read_rfreg(PADAPTER padapter, u8 rfpath, u32 addr); ++extern void write_rfreg(PADAPTER padapter, u8 rfpath, u32 addr, u32 val); ++ ++extern void SetChannel(PADAPTER pAdapter); ++extern void SetBandwidth(PADAPTER pAdapter); ++extern void SetTxPower(PADAPTER pAdapter); ++extern void SetAntennaPathPower(PADAPTER pAdapter); ++//extern void SetTxAGCOffset(PADAPTER pAdapter, u32 ulTxAGCOffset); ++extern void SetDataRate(PADAPTER pAdapter); ++ ++extern void SetAntenna(PADAPTER pAdapter); ++ ++//extern void SetCrystalCap(PADAPTER pAdapter); ++ ++extern s32 SetThermalMeter(PADAPTER pAdapter, u8 target_ther); ++extern void GetThermalMeter(PADAPTER pAdapter, u8 *value); ++ ++extern void SetContinuousTx(PADAPTER pAdapter, u8 bStart); ++extern void SetSingleCarrierTx(PADAPTER pAdapter, u8 bStart); ++extern void SetSingleToneTx(PADAPTER pAdapter, u8 bStart); ++extern void SetCarrierSuppressionTx(PADAPTER pAdapter, u8 bStart); ++ ++extern void fill_txdesc_for_mp(PADAPTER padapter, struct tx_desc *ptxdesc); ++extern void SetPacketTx(PADAPTER padapter); ++extern void SetPacketRx(PADAPTER pAdapter, u8 bStartRx); ++ ++extern void ResetPhyRxPktCount(PADAPTER pAdapter); ++extern u32 GetPhyRxPktReceived(PADAPTER pAdapter); ++extern u32 GetPhyRxPktCRC32Error(PADAPTER pAdapter); ++ ++extern s32 SetPowerTracking(PADAPTER padapter, u8 enable); ++extern void GetPowerTracking(PADAPTER padapter, u8 *enable); ++ ++extern u32 mp_query_psd(PADAPTER pAdapter, u8 *data); ++ ++extern u32 rtw_atoi(u8 *s); ++ ++ ++extern void Hal_SetAntenna(PADAPTER pAdapter); ++extern void Hal_SetBandwidth(PADAPTER pAdapter); ++ ++extern void Hal_SetTxPower(PADAPTER pAdapter); ++extern void Hal_SetCarrierSuppressionTx(PADAPTER pAdapter, u8 bStart); ++extern void Hal_SetSingleToneTx ( PADAPTER pAdapter , u8 bStart ); ++extern void Hal_SetSingleCarrierTx (PADAPTER pAdapter, u8 bStart); ++extern void Hal_SetContinuousTx (PADAPTER pAdapter, u8 bStart); ++extern void Hal_SetBandwidth(PADAPTER pAdapter); ++ ++extern void Hal_SetDataRate(PADAPTER pAdapter); ++extern void Hal_SetChannel(PADAPTER pAdapter); ++extern void Hal_SetAntennaPathPower(PADAPTER pAdapter); ++extern s32 Hal_SetThermalMeter(PADAPTER pAdapter, u8 target_ther); ++extern s32 Hal_SetPowerTracking(PADAPTER padapter, u8 enable); ++extern void Hal_GetPowerTracking(PADAPTER padapter, u8 * enable); ++extern void Hal_GetThermalMeter(PADAPTER pAdapter, u8 *value); ++extern void Hal_mpt_SwitchRfSetting(PADAPTER pAdapter); ++extern void Hal_MPT_CCKTxPowerAdjust(PADAPTER Adapter, BOOLEAN bInCH14); ++extern void Hal_MPT_CCKTxPowerAdjustbyIndex(PADAPTER pAdapter, BOOLEAN beven); ++extern void Hal_SetCCKTxPower(PADAPTER pAdapter, u8 * TxPower); ++extern void Hal_SetOFDMTxPower(PADAPTER pAdapter, u8 * TxPower); ++extern void Hal_TriggerRFThermalMeter(PADAPTER pAdapter); ++extern u8 Hal_ReadRFThermalMeter(PADAPTER pAdapter); ++extern void Hal_SetCCKContinuousTx(PADAPTER pAdapter, u8 bStart); ++extern void Hal_SetOFDMContinuousTx(PADAPTER pAdapter, u8 bStart); ++extern void Hal_ProSetCrystalCap (PADAPTER pAdapter , u32 CrystalCapVal); ++ ++#endif //_RTW_MP_H_ ++ +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/include/rtw_mp_ioctl.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/include/rtw_mp_ioctl.h 2013-07-26 19:36:06.000000000 +0000 +@@ -0,0 +1,596 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef _RTW_MP_IOCTL_H_ ++#define _RTW_MP_IOCTL_H_ ++ ++//#include ++//#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#if 0 ++#define TESTFWCMDNUMBER 1000000 ++#define TEST_H2CINT_WAIT_TIME 500 ++#define TEST_C2HINT_WAIT_TIME 500 ++#define HCI_TEST_SYSCFG_HWMASK 1 ++#define _BUSCLK_40M (4 << 2) ++#endif ++//------------------------------------------------------------------------------ ++typedef struct CFG_DBG_MSG_STRUCT { ++ u32 DebugLevel; ++ u32 DebugComponent_H32; ++ u32 DebugComponent_L32; ++}CFG_DBG_MSG_STRUCT,*PCFG_DBG_MSG_STRUCT; ++ ++typedef struct _RW_REG { ++ u32 offset; ++ u32 width; ++ u32 value; ++}mp_rw_reg,RW_Reg, *pRW_Reg; ++ ++//for OID_RT_PRO_READ16_EEPROM & OID_RT_PRO_WRITE16_EEPROM ++typedef struct _EEPROM_RW_PARAM { ++ u32 offset; ++ u16 value; ++}eeprom_rw_param,EEPROM_RWParam, *pEEPROM_RWParam; ++ ++typedef struct _EFUSE_ACCESS_STRUCT_ { ++ u16 start_addr; ++ u16 cnts; ++ u8 data[0]; ++}EFUSE_ACCESS_STRUCT, *PEFUSE_ACCESS_STRUCT; ++ ++typedef struct _BURST_RW_REG { ++ u32 offset; ++ u32 len; ++ u8 Data[256]; ++}burst_rw_reg,Burst_RW_Reg, *pBurst_RW_Reg; ++ ++typedef struct _USB_VendorReq{ ++ u8 bRequest; ++ u16 wValue; ++ u16 wIndex; ++ u16 wLength; ++ u8 u8Dir;//0:OUT, 1:IN ++ u8 u8InData; ++}usb_vendor_req, USB_VendorReq, *pUSB_VendorReq; ++ ++typedef struct _DR_VARIABLE_STRUCT_ { ++ u8 offset; ++ u32 variable; ++}DR_VARIABLE_STRUCT; ++ ++//int mp_start_joinbss(_adapter *padapter, NDIS_802_11_SSID *pssid); ++ ++//void _irqlevel_changed_(_irqL *irqlevel, /*BOOLEAN*/unsigned char bLower); ++#ifdef PLATFORM_OS_XP ++static void _irqlevel_changed_(_irqL *irqlevel, u8 bLower) ++{ ++ ++ if (bLower == LOWER) { ++ *irqlevel = KeGetCurrentIrql(); ++ ++ if (*irqlevel > PASSIVE_LEVEL) { ++ KeLowerIrql(PASSIVE_LEVEL); ++ } ++ } else { ++ if (KeGetCurrentIrql() == PASSIVE_LEVEL) { ++ KeRaiseIrql(DISPATCH_LEVEL, irqlevel); ++ } ++ } ++ ++} ++#else ++#define _irqlevel_changed_(a,b) ++#endif ++ ++//oid_rtl_seg_81_80_00 ++NDIS_STATUS oid_rt_pro_set_data_rate_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_pro_start_test_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_pro_stop_test_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_pro_set_channel_direct_call_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_pro_set_antenna_bb_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_pro_set_tx_power_control_hdl(struct oid_par_priv* poid_par_priv); ++//oid_rtl_seg_81_80_20 ++NDIS_STATUS oid_rt_pro_query_tx_packet_sent_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_pro_query_rx_packet_received_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_pro_query_rx_packet_crc32_error_hdl(struct oid_par_priv* poid_par_priv); ++ ++NDIS_STATUS oid_rt_pro_reset_tx_packet_sent_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_pro_reset_rx_packet_received_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_pro_set_modulation_hdl(struct oid_par_priv* poid_par_priv); ++ ++NDIS_STATUS oid_rt_pro_set_continuous_tx_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_pro_set_single_carrier_tx_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_pro_set_carrier_suppression_tx_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_pro_set_single_tone_tx_hdl(struct oid_par_priv* poid_par_priv); ++ ++ ++//oid_rtl_seg_81_87 ++NDIS_STATUS oid_rt_pro_write_bb_reg_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_pro_read_bb_reg_hdl(struct oid_par_priv* poid_par_priv); ++ ++NDIS_STATUS oid_rt_pro_write_rf_reg_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_pro_read_rf_reg_hdl(struct oid_par_priv* poid_par_priv); ++ ++ ++//oid_rtl_seg_81_85 ++NDIS_STATUS oid_rt_wireless_mode_hdl(struct oid_par_priv* poid_par_priv); ++ ++ ++// oid_rtl_seg_87_11_00 ++NDIS_STATUS oid_rt_pro8711_join_bss_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_pro_read_register_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_pro_write_register_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_pro_burst_read_register_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_pro_burst_write_register_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_pro_write_txcmd_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_pro_read16_eeprom_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_pro_write16_eeprom_hdl (struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_pro8711_wi_poll_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_pro8711_pkt_loss_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_rd_attrib_mem_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_wr_attrib_mem_hdl (struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_pro_set_rf_intfs_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_poll_rx_status_hdl(struct oid_par_priv* poid_par_priv); ++// oid_rtl_seg_87_11_20 ++NDIS_STATUS oid_rt_pro_cfg_debug_message_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_pro_set_data_rate_ex_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_pro_set_basic_rate_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_pro_read_tssi_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_pro_set_power_tracking_hdl(struct oid_par_priv* poid_par_priv); ++//oid_rtl_seg_87_11_50 ++NDIS_STATUS oid_rt_pro_qry_pwrstate_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_pro_set_pwrstate_hdl(struct oid_par_priv* poid_par_priv); ++//oid_rtl_seg_87_11_F0 ++NDIS_STATUS oid_rt_pro_h2c_set_rate_table_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_pro_h2c_get_rate_table_hdl(struct oid_par_priv* poid_par_priv); ++ ++ ++//oid_rtl_seg_87_12_00 ++NDIS_STATUS oid_rt_pro_encryption_ctrl_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_pro_add_sta_info_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_pro_dele_sta_info_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_pro_query_dr_variable_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_pro_rx_packet_type_hdl(struct oid_par_priv* poid_par_priv); ++ ++NDIS_STATUS oid_rt_pro_read_efuse_hdl(struct oid_par_priv *poid_par_priv); ++NDIS_STATUS oid_rt_pro_write_efuse_hdl(struct oid_par_priv *poid_par_priv); ++NDIS_STATUS oid_rt_pro_rw_efuse_pgpkt_hdl(struct oid_par_priv *poid_par_priv); ++NDIS_STATUS oid_rt_get_efuse_current_size_hdl(struct oid_par_priv *poid_par_priv); ++NDIS_STATUS oid_rt_pro_efuse_hdl(struct oid_par_priv *poid_par_priv); ++NDIS_STATUS oid_rt_pro_efuse_map_hdl(struct oid_par_priv *poid_par_priv); ++ ++NDIS_STATUS oid_rt_set_bandwidth_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_set_crystal_cap_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_set_rx_packet_type_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_get_efuse_max_size_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_pro_set_tx_agc_offset_hdl(struct oid_par_priv* poid_par_priv); ++ ++NDIS_STATUS oid_rt_pro_set_pkt_test_mode_hdl(struct oid_par_priv* poid_par_priv); ++ ++NDIS_STATUS oid_rt_get_thermal_meter_hdl(struct oid_par_priv* poid_par_priv); ++ ++NDIS_STATUS oid_rt_reset_phy_rx_packet_count_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_get_phy_rx_packet_received_hdl(struct oid_par_priv* poid_par_priv); ++NDIS_STATUS oid_rt_get_phy_rx_packet_crc32_error_hdl(struct oid_par_priv* poid_par_priv); ++ ++NDIS_STATUS oid_rt_set_power_down_hdl(struct oid_par_priv* poid_par_priv); ++ ++NDIS_STATUS oid_rt_get_power_mode_hdl(struct oid_par_priv* poid_par_priv); ++ ++NDIS_STATUS oid_rt_pro_trigger_gpio_hdl(struct oid_par_priv *poid_par_priv); ++ ++#ifdef _RTW_MP_IOCTL_C_ ++ ++const struct oid_obj_priv oid_rtl_seg_81_80_00[] = ++{ ++ {1, &oid_null_function}, //0x00 OID_RT_PRO_RESET_DUT ++ {1, &oid_rt_pro_set_data_rate_hdl}, //0x01 ++ {1, &oid_rt_pro_start_test_hdl}, //0x02 ++ {1, &oid_rt_pro_stop_test_hdl}, //0x03 ++ {1, &oid_null_function}, //0x04 OID_RT_PRO_SET_PREAMBLE ++ {1, &oid_null_function}, //0x05 OID_RT_PRO_SET_SCRAMBLER ++ {1, &oid_null_function}, //0x06 OID_RT_PRO_SET_FILTER_BB ++ {1, &oid_null_function}, //0x07 OID_RT_PRO_SET_MANUAL_DIVERSITY_BB ++ {1, &oid_rt_pro_set_channel_direct_call_hdl}, //0x08 ++ {1, &oid_null_function}, //0x09 OID_RT_PRO_SET_SLEEP_MODE_DIRECT_CALL ++ {1, &oid_null_function}, //0x0A OID_RT_PRO_SET_WAKE_MODE_DIRECT_CALL ++ {1, &oid_rt_pro_set_continuous_tx_hdl}, //0x0B OID_RT_PRO_SET_TX_CONTINUOUS_DIRECT_CALL ++ {1, &oid_rt_pro_set_single_carrier_tx_hdl}, //0x0C OID_RT_PRO_SET_SINGLE_CARRIER_TX_CONTINUOUS ++ {1, &oid_null_function}, //0x0D OID_RT_PRO_SET_TX_ANTENNA_BB ++ {1, &oid_rt_pro_set_antenna_bb_hdl}, //0x0E ++ {1, &oid_null_function}, //0x0F OID_RT_PRO_SET_CR_SCRAMBLER ++ {1, &oid_null_function}, //0x10 OID_RT_PRO_SET_CR_NEW_FILTER ++ {1, &oid_rt_pro_set_tx_power_control_hdl}, //0x11 OID_RT_PRO_SET_TX_POWER_CONTROL ++ {1, &oid_null_function}, //0x12 OID_RT_PRO_SET_CR_TX_CONFIG ++ {1, &oid_null_function}, //0x13 OID_RT_PRO_GET_TX_POWER_CONTROL ++ {1, &oid_null_function}, //0x14 OID_RT_PRO_GET_CR_SIGNAL_QUALITY ++ {1, &oid_null_function}, //0x15 OID_RT_PRO_SET_CR_SETPOINT ++ {1, &oid_null_function}, //0x16 OID_RT_PRO_SET_INTEGRATOR ++ {1, &oid_null_function}, //0x17 OID_RT_PRO_SET_SIGNAL_QUALITY ++ {1, &oid_null_function}, //0x18 OID_RT_PRO_GET_INTEGRATOR ++ {1, &oid_null_function}, //0x19 OID_RT_PRO_GET_SIGNAL_QUALITY ++ {1, &oid_null_function}, //0x1A OID_RT_PRO_QUERY_EEPROM_TYPE ++ {1, &oid_null_function}, //0x1B OID_RT_PRO_WRITE_MAC_ADDRESS ++ {1, &oid_null_function}, //0x1C OID_RT_PRO_READ_MAC_ADDRESS ++ {1, &oid_null_function}, //0x1D OID_RT_PRO_WRITE_CIS_DATA ++ {1, &oid_null_function}, //0x1E OID_RT_PRO_READ_CIS_DATA ++ {1, &oid_null_function} //0x1F OID_RT_PRO_WRITE_POWER_CONTROL ++ ++}; ++ ++const struct oid_obj_priv oid_rtl_seg_81_80_20[] = ++{ ++ {1, &oid_null_function}, //0x20 OID_RT_PRO_READ_POWER_CONTROL ++ {1, &oid_null_function}, //0x21 OID_RT_PRO_WRITE_EEPROM ++ {1, &oid_null_function}, //0x22 OID_RT_PRO_READ_EEPROM ++ {1, &oid_rt_pro_reset_tx_packet_sent_hdl}, //0x23 ++ {1, &oid_rt_pro_query_tx_packet_sent_hdl}, //0x24 ++ {1, &oid_rt_pro_reset_rx_packet_received_hdl}, //0x25 ++ {1, &oid_rt_pro_query_rx_packet_received_hdl}, //0x26 ++ {1, &oid_rt_pro_query_rx_packet_crc32_error_hdl}, //0x27 ++ {1, &oid_null_function}, //0x28 OID_RT_PRO_QUERY_CURRENT_ADDRESS ++ {1, &oid_null_function}, //0x29 OID_RT_PRO_QUERY_PERMANENT_ADDRESS ++ {1, &oid_null_function}, //0x2A OID_RT_PRO_SET_PHILIPS_RF_PARAMETERS ++ {1, &oid_rt_pro_set_carrier_suppression_tx_hdl},//0x2B OID_RT_PRO_SET_CARRIER_SUPPRESSION_TX ++ {1, &oid_null_function}, //0x2C OID_RT_PRO_RECEIVE_PACKET ++ {1, &oid_null_function}, //0x2D OID_RT_PRO_WRITE_EEPROM_BYTE ++ {1, &oid_null_function}, //0x2E OID_RT_PRO_READ_EEPROM_BYTE ++ {1, &oid_rt_pro_set_modulation_hdl} //0x2F ++ ++}; ++ ++const struct oid_obj_priv oid_rtl_seg_81_80_40[] = ++{ ++ {1, &oid_null_function}, //0x40 ++ {1, &oid_null_function}, //0x41 ++ {1, &oid_null_function}, //0x42 ++ {1, &oid_rt_pro_set_single_tone_tx_hdl}, //0x43 ++ {1, &oid_null_function}, //0x44 ++ {1, &oid_null_function} //0x45 ++}; ++ ++const struct oid_obj_priv oid_rtl_seg_81_80_80[] = ++{ ++ {1, &oid_null_function}, //0x80 OID_RT_DRIVER_OPTION ++ {1, &oid_null_function}, //0x81 OID_RT_RF_OFF ++ {1, &oid_null_function} //0x82 OID_RT_AUTH_STATUS ++ ++}; ++ ++const struct oid_obj_priv oid_rtl_seg_81_85[] = ++{ ++ {1, &oid_rt_wireless_mode_hdl} //0x00 OID_RT_WIRELESS_MODE ++}; ++ ++struct oid_obj_priv oid_rtl_seg_81_87[] = ++{ ++ {1, &oid_null_function}, //0x80 OID_RT_PRO8187_WI_POLL ++ {1, &oid_rt_pro_write_bb_reg_hdl}, //0x81 ++ {1, &oid_rt_pro_read_bb_reg_hdl}, //0x82 ++ {1, &oid_rt_pro_write_rf_reg_hdl}, //0x82 ++ {1, &oid_rt_pro_read_rf_reg_hdl} //0x83 ++}; ++ ++struct oid_obj_priv oid_rtl_seg_87_11_00[] = ++{ ++ {1, &oid_rt_pro8711_join_bss_hdl}, //0x00 //S ++ {1, &oid_rt_pro_read_register_hdl}, //0x01 ++ {1, &oid_rt_pro_write_register_hdl}, //0x02 ++ {1, &oid_rt_pro_burst_read_register_hdl}, //0x03 ++ {1, &oid_rt_pro_burst_write_register_hdl}, //0x04 ++ {1, &oid_rt_pro_write_txcmd_hdl}, //0x05 ++ {1, &oid_rt_pro_read16_eeprom_hdl}, //0x06 ++ {1, &oid_rt_pro_write16_eeprom_hdl}, //0x07 ++ {1, &oid_null_function}, //0x08 OID_RT_PRO_H2C_SET_COMMAND ++ {1, &oid_null_function}, //0x09 OID_RT_PRO_H2C_QUERY_RESULT ++ {1, &oid_rt_pro8711_wi_poll_hdl}, //0x0A ++ {1, &oid_rt_pro8711_pkt_loss_hdl}, //0x0B ++ {1, &oid_rt_rd_attrib_mem_hdl}, //0x0C ++ {1, &oid_rt_wr_attrib_mem_hdl}, //0x0D ++ {1, &oid_null_function}, //0x0E ++ {1, &oid_null_function}, //0x0F ++ {1, &oid_null_function}, //0x10 OID_RT_PRO_H2C_CMD_MODE ++ {1, &oid_null_function}, //0x11 OID_RT_PRO_H2C_CMD_RSP_MODE ++ {1, &oid_null_function}, //0X12 OID_RT_PRO_WAIT_C2H_EVENT ++ {1, &oid_null_function}, //0X13 OID_RT_PRO_RW_ACCESS_PROTOCOL_TEST ++ {1, &oid_null_function}, //0X14 OID_RT_PRO_SCSI_ACCESS_TEST ++ {1, &oid_null_function}, //0X15 OID_RT_PRO_SCSI_TCPIPOFFLOAD_OUT ++ {1, &oid_null_function}, //0X16 OID_RT_PRO_SCSI_TCPIPOFFLOAD_IN ++ {1, &oid_null_function}, //0X17 OID_RT_RRO_RX_PKT_VIA_IOCTRL ++ {1, &oid_null_function}, //0X18 OID_RT_RRO_RX_PKTARRAY_VIA_IOCTRL ++ {1, &oid_null_function}, //0X19 OID_RT_RPO_SET_PWRMGT_TEST ++ {1, &oid_null_function}, //0X1A ++ {1, &oid_null_function}, //0X1B OID_RT_PRO_QRY_PWRMGT_TEST ++ {1, &oid_null_function}, //0X1C OID_RT_RPO_ASYNC_RWIO_TEST ++ {1, &oid_null_function}, //0X1D OID_RT_RPO_ASYNC_RWIO_POLL ++ {1, &oid_rt_pro_set_rf_intfs_hdl}, //0X1E ++ {1, &oid_rt_poll_rx_status_hdl} //0X1F ++}; ++ ++struct oid_obj_priv oid_rtl_seg_87_11_20[] = ++{ ++ {1, &oid_rt_pro_cfg_debug_message_hdl}, //0x20 ++ {1, &oid_rt_pro_set_data_rate_ex_hdl}, //0x21 ++ {1, &oid_rt_pro_set_basic_rate_hdl}, //0x22 ++ {1, &oid_rt_pro_read_tssi_hdl}, //0x23 ++ {1, &oid_rt_pro_set_power_tracking_hdl} //0x24 ++}; ++ ++ ++struct oid_obj_priv oid_rtl_seg_87_11_50[] = ++{ ++ {1, &oid_rt_pro_qry_pwrstate_hdl}, //0x50 ++ {1, &oid_rt_pro_set_pwrstate_hdl} //0x51 ++}; ++ ++struct oid_obj_priv oid_rtl_seg_87_11_80[] = ++{ ++ {1, &oid_null_function} //0x80 ++}; ++ ++struct oid_obj_priv oid_rtl_seg_87_11_B0[] = ++{ ++ {1, &oid_null_function} //0xB0 ++}; ++ ++struct oid_obj_priv oid_rtl_seg_87_11_F0[] = ++{ ++ {1, &oid_null_function}, //0xF0 ++ {1, &oid_null_function}, //0xF1 ++ {1, &oid_null_function}, //0xF2 ++ {1, &oid_null_function}, //0xF3 ++ {1, &oid_null_function}, //0xF4 ++ {1, &oid_null_function}, //0xF5 ++ {1, &oid_null_function}, //0xF6 ++ {1, &oid_null_function}, //0xF7 ++ {1, &oid_null_function}, //0xF8 ++ {1, &oid_null_function}, //0xF9 ++ {1, &oid_null_function}, //0xFA ++ {1, &oid_rt_pro_h2c_set_rate_table_hdl}, //0xFB ++ {1, &oid_rt_pro_h2c_get_rate_table_hdl}, //0xFC ++ {1, &oid_null_function}, //0xFD ++ {1, &oid_null_function}, //0xFE OID_RT_PRO_H2C_C2H_LBK_TEST ++ {1, &oid_null_function} //0xFF ++ ++}; ++ ++struct oid_obj_priv oid_rtl_seg_87_12_00[]= ++{ ++ {1, &oid_rt_pro_encryption_ctrl_hdl}, //0x00 Q&S ++ {1, &oid_rt_pro_add_sta_info_hdl}, //0x01 S ++ {1, &oid_rt_pro_dele_sta_info_hdl}, //0x02 S ++ {1, &oid_rt_pro_query_dr_variable_hdl}, //0x03 Q ++ {1, &oid_rt_pro_rx_packet_type_hdl}, //0x04 Q,S ++ {1, &oid_rt_pro_read_efuse_hdl}, //0x05 Q OID_RT_PRO_READ_EFUSE ++ {1, &oid_rt_pro_write_efuse_hdl}, //0x06 S OID_RT_PRO_WRITE_EFUSE ++ {1, &oid_rt_pro_rw_efuse_pgpkt_hdl}, //0x07 Q,S ++ {1, &oid_rt_get_efuse_current_size_hdl}, //0x08 Q ++ {1, &oid_rt_set_bandwidth_hdl}, //0x09 ++ {1, &oid_rt_set_crystal_cap_hdl}, //0x0a ++ {1, &oid_rt_set_rx_packet_type_hdl}, //0x0b S ++ {1, &oid_rt_get_efuse_max_size_hdl}, //0x0c ++ {1, &oid_rt_pro_set_tx_agc_offset_hdl}, //0x0d ++ {1, &oid_rt_pro_set_pkt_test_mode_hdl}, //0x0e ++ {1, &oid_null_function}, //0x0f OID_RT_PRO_FOR_EVM_TEST_SETTING ++ {1, &oid_rt_get_thermal_meter_hdl}, //0x10 Q OID_RT_PRO_GET_THERMAL_METER ++ {1, &oid_rt_reset_phy_rx_packet_count_hdl}, //0x11 S OID_RT_RESET_PHY_RX_PACKET_COUNT ++ {1, &oid_rt_get_phy_rx_packet_received_hdl}, //0x12 Q OID_RT_GET_PHY_RX_PACKET_RECEIVED ++ {1, &oid_rt_get_phy_rx_packet_crc32_error_hdl}, //0x13 Q OID_RT_GET_PHY_RX_PACKET_CRC32_ERROR ++ {1, &oid_rt_set_power_down_hdl}, //0x14 Q OID_RT_SET_POWER_DOWN ++ {1, &oid_rt_get_power_mode_hdl} //0x15 Q OID_RT_GET_POWER_MODE ++}; ++ ++#else /* _RTL871X_MP_IOCTL_C_ */ ++ ++extern struct oid_obj_priv oid_rtl_seg_81_80_00[32]; ++extern struct oid_obj_priv oid_rtl_seg_81_80_20[16]; ++extern struct oid_obj_priv oid_rtl_seg_81_80_40[6]; ++extern struct oid_obj_priv oid_rtl_seg_81_80_80[3]; ++ ++extern struct oid_obj_priv oid_rtl_seg_81_85[1]; ++extern struct oid_obj_priv oid_rtl_seg_81_87[5]; ++ ++extern struct oid_obj_priv oid_rtl_seg_87_11_00[32]; ++extern struct oid_obj_priv oid_rtl_seg_87_11_20[5]; ++extern struct oid_obj_priv oid_rtl_seg_87_11_50[2]; ++extern struct oid_obj_priv oid_rtl_seg_87_11_80[1]; ++extern struct oid_obj_priv oid_rtl_seg_87_11_B0[1]; ++extern struct oid_obj_priv oid_rtl_seg_87_11_F0[16]; ++ ++extern struct oid_obj_priv oid_rtl_seg_87_12_00[32]; ++ ++#endif /* _RTL871X_MP_IOCTL_C_ */ ++ ++struct rwreg_param{ ++ u32 offset; ++ u32 width; ++ u32 value; ++}; ++ ++struct bbreg_param{ ++ u32 offset; ++ u32 phymask; ++ u32 value; ++}; ++/* ++struct rfchannel_param{ ++ u32 ch; ++ u32 modem; ++}; ++*/ ++struct txpower_param{ ++ u32 pwr_index; ++}; ++ ++ ++struct datarate_param{ ++ u32 rate_index; ++}; ++ ++ ++struct rfintfs_parm { ++ u32 rfintfs; ++}; ++ ++typedef struct _mp_xmit_parm_ { ++ u8 enable; ++ u32 count; ++ u16 length; ++ u8 payload_type; ++ u8 da[ETH_ALEN]; ++}MP_XMIT_PARM, *PMP_XMIT_PARM; ++ ++struct mp_xmit_packet { ++ u32 len; ++ u32 mem[MAX_MP_XMITBUF_SZ >> 2]; ++}; ++ ++struct psmode_param { ++ u32 ps_mode; ++ u32 smart_ps; ++}; ++ ++//for OID_RT_PRO_READ16_EEPROM & OID_RT_PRO_WRITE16_EEPROM ++struct eeprom_rw_param { ++ u32 offset; ++ u16 value; ++}; ++ ++struct mp_ioctl_handler { ++ u32 paramsize; ++ u32 (*handler)(struct oid_par_priv* poid_par_priv); ++ u32 oid; ++}; ++ ++struct mp_ioctl_param{ ++ u32 subcode; ++ u32 len; ++ u8 data[0]; ++}; ++ ++#define GEN_MP_IOCTL_SUBCODE(code) _MP_IOCTL_ ## code ## _CMD_ ++ ++enum RTL871X_MP_IOCTL_SUBCODE { ++ GEN_MP_IOCTL_SUBCODE(MP_START), /*0*/ ++ GEN_MP_IOCTL_SUBCODE(MP_STOP), ++ GEN_MP_IOCTL_SUBCODE(READ_REG), ++ GEN_MP_IOCTL_SUBCODE(WRITE_REG), ++ GEN_MP_IOCTL_SUBCODE(READ_BB_REG), ++ GEN_MP_IOCTL_SUBCODE(WRITE_BB_REG), /*5*/ ++ GEN_MP_IOCTL_SUBCODE(READ_RF_REG), ++ GEN_MP_IOCTL_SUBCODE(WRITE_RF_REG), ++ GEN_MP_IOCTL_SUBCODE(SET_CHANNEL), ++ GEN_MP_IOCTL_SUBCODE(SET_TXPOWER), ++ GEN_MP_IOCTL_SUBCODE(SET_DATARATE), /*10*/ ++ GEN_MP_IOCTL_SUBCODE(SET_BANDWIDTH), ++ GEN_MP_IOCTL_SUBCODE(SET_ANTENNA), ++ GEN_MP_IOCTL_SUBCODE(CNTU_TX), ++ GEN_MP_IOCTL_SUBCODE(SC_TX), ++ GEN_MP_IOCTL_SUBCODE(CS_TX), /*15*/ ++ GEN_MP_IOCTL_SUBCODE(ST_TX), ++ GEN_MP_IOCTL_SUBCODE(IOCTL_XMIT_PACKET), ++ GEN_MP_IOCTL_SUBCODE(SET_RX_PKT_TYPE), ++ GEN_MP_IOCTL_SUBCODE(RESET_PHY_RX_PKT_CNT), ++ GEN_MP_IOCTL_SUBCODE(GET_PHY_RX_PKT_RECV), /*20*/ ++ GEN_MP_IOCTL_SUBCODE(GET_PHY_RX_PKT_ERROR), ++ GEN_MP_IOCTL_SUBCODE(READ16_EEPROM), ++ GEN_MP_IOCTL_SUBCODE(WRITE16_EEPROM), ++ GEN_MP_IOCTL_SUBCODE(EFUSE), ++ GEN_MP_IOCTL_SUBCODE(EFUSE_MAP), /*25*/ ++ GEN_MP_IOCTL_SUBCODE(GET_EFUSE_MAX_SIZE), ++ GEN_MP_IOCTL_SUBCODE(GET_EFUSE_CURRENT_SIZE), ++ GEN_MP_IOCTL_SUBCODE(GET_THERMAL_METER), ++ GEN_MP_IOCTL_SUBCODE(SET_PTM), ++ GEN_MP_IOCTL_SUBCODE(SET_POWER_DOWN), /*30*/ ++ GEN_MP_IOCTL_SUBCODE(TRIGGER_GPIO), ++ GEN_MP_IOCTL_SUBCODE(SET_DM_BT), /*35*/ ++ GEN_MP_IOCTL_SUBCODE(DEL_BA), /*36*/ ++ GEN_MP_IOCTL_SUBCODE(GET_WIFI_STATUS), /*37*/ ++ MAX_MP_IOCTL_SUBCODE, ++}; ++ ++u32 mp_ioctl_xmit_packet_hdl(struct oid_par_priv* poid_par_priv); ++ ++#ifdef _RTW_MP_IOCTL_C_ ++ ++#define GEN_MP_IOCTL_HANDLER(sz, hdl, oid) {sz, hdl, oid}, ++ ++#define EXT_MP_IOCTL_HANDLER(sz, subcode, oid) {sz, mp_ioctl_ ## subcode ## _hdl, oid}, ++ ++ ++struct mp_ioctl_handler mp_ioctl_hdl[] = { ++ ++/*0*/ GEN_MP_IOCTL_HANDLER(sizeof(u32), oid_rt_pro_start_test_hdl, OID_RT_PRO_START_TEST) ++ GEN_MP_IOCTL_HANDLER(sizeof(u32), oid_rt_pro_stop_test_hdl, OID_RT_PRO_STOP_TEST) ++ ++ GEN_MP_IOCTL_HANDLER(sizeof(struct rwreg_param), oid_rt_pro_read_register_hdl, OID_RT_PRO_READ_REGISTER) ++ GEN_MP_IOCTL_HANDLER(sizeof(struct rwreg_param), oid_rt_pro_write_register_hdl, OID_RT_PRO_WRITE_REGISTER) ++ GEN_MP_IOCTL_HANDLER(sizeof(struct bb_reg_param), oid_rt_pro_read_bb_reg_hdl, OID_RT_PRO_READ_BB_REG) ++/*5*/ GEN_MP_IOCTL_HANDLER(sizeof(struct bb_reg_param), oid_rt_pro_write_bb_reg_hdl, OID_RT_PRO_WRITE_BB_REG) ++ GEN_MP_IOCTL_HANDLER(sizeof(struct rf_reg_param), oid_rt_pro_read_rf_reg_hdl, OID_RT_PRO_RF_READ_REGISTRY) ++ GEN_MP_IOCTL_HANDLER(sizeof(struct rf_reg_param), oid_rt_pro_write_rf_reg_hdl, OID_RT_PRO_RF_WRITE_REGISTRY) ++ ++ GEN_MP_IOCTL_HANDLER(sizeof(u32), oid_rt_pro_set_channel_direct_call_hdl, OID_RT_PRO_SET_CHANNEL_DIRECT_CALL) ++ GEN_MP_IOCTL_HANDLER(sizeof(struct txpower_param), oid_rt_pro_set_tx_power_control_hdl, OID_RT_PRO_SET_TX_POWER_CONTROL) ++/*10*/ GEN_MP_IOCTL_HANDLER(sizeof(u32), oid_rt_pro_set_data_rate_hdl, OID_RT_PRO_SET_DATA_RATE) ++ GEN_MP_IOCTL_HANDLER(sizeof(u32), oid_rt_set_bandwidth_hdl, OID_RT_SET_BANDWIDTH) ++ GEN_MP_IOCTL_HANDLER(sizeof(u32), oid_rt_pro_set_antenna_bb_hdl, OID_RT_PRO_SET_ANTENNA_BB) ++ ++ GEN_MP_IOCTL_HANDLER(sizeof(u32), oid_rt_pro_set_continuous_tx_hdl, OID_RT_PRO_SET_CONTINUOUS_TX) ++ GEN_MP_IOCTL_HANDLER(sizeof(u32), oid_rt_pro_set_single_carrier_tx_hdl, OID_RT_PRO_SET_SINGLE_CARRIER_TX) ++/*15*/ GEN_MP_IOCTL_HANDLER(sizeof(u32), oid_rt_pro_set_carrier_suppression_tx_hdl, OID_RT_PRO_SET_CARRIER_SUPPRESSION_TX) ++ GEN_MP_IOCTL_HANDLER(sizeof(u32), oid_rt_pro_set_single_tone_tx_hdl, OID_RT_PRO_SET_SINGLE_TONE_TX) ++ ++ EXT_MP_IOCTL_HANDLER(0, xmit_packet, 0) ++ ++ GEN_MP_IOCTL_HANDLER(sizeof(u32), oid_rt_set_rx_packet_type_hdl, OID_RT_SET_RX_PACKET_TYPE) ++ GEN_MP_IOCTL_HANDLER(0, oid_rt_reset_phy_rx_packet_count_hdl, OID_RT_RESET_PHY_RX_PACKET_COUNT) ++/*20*/ GEN_MP_IOCTL_HANDLER(sizeof(u32), oid_rt_get_phy_rx_packet_received_hdl, OID_RT_GET_PHY_RX_PACKET_RECEIVED) ++ GEN_MP_IOCTL_HANDLER(sizeof(u32), oid_rt_get_phy_rx_packet_crc32_error_hdl, OID_RT_GET_PHY_RX_PACKET_CRC32_ERROR) ++ ++ GEN_MP_IOCTL_HANDLER(sizeof(struct eeprom_rw_param), NULL, 0) ++ GEN_MP_IOCTL_HANDLER(sizeof(struct eeprom_rw_param), NULL, 0) ++ GEN_MP_IOCTL_HANDLER(sizeof(EFUSE_ACCESS_STRUCT), oid_rt_pro_efuse_hdl, OID_RT_PRO_EFUSE) ++/*25*/ GEN_MP_IOCTL_HANDLER(0, oid_rt_pro_efuse_map_hdl, OID_RT_PRO_EFUSE_MAP) ++ GEN_MP_IOCTL_HANDLER(sizeof(u32), oid_rt_get_efuse_max_size_hdl, OID_RT_GET_EFUSE_MAX_SIZE) ++ GEN_MP_IOCTL_HANDLER(sizeof(u32), oid_rt_get_efuse_current_size_hdl, OID_RT_GET_EFUSE_CURRENT_SIZE) ++ ++ GEN_MP_IOCTL_HANDLER(sizeof(u32), oid_rt_get_thermal_meter_hdl, OID_RT_PRO_GET_THERMAL_METER) ++ GEN_MP_IOCTL_HANDLER(sizeof(u8), oid_rt_pro_set_power_tracking_hdl, OID_RT_PRO_SET_POWER_TRACKING) ++/*30*/ GEN_MP_IOCTL_HANDLER(sizeof(u8), oid_rt_set_power_down_hdl, OID_RT_SET_POWER_DOWN) ++/*31*/ GEN_MP_IOCTL_HANDLER(0, oid_rt_pro_trigger_gpio_hdl, 0) ++ ++ ++}; ++ ++#else /* _RTW_MP_IOCTL_C_ */ ++ ++extern struct mp_ioctl_handler mp_ioctl_hdl[]; ++ ++#endif /* _RTW_MP_IOCTL_C_ */ ++ ++#endif ++ +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/include/rtw_mp_phy_regdef.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/include/rtw_mp_phy_regdef.h 2013-07-26 19:36:06.000000000 +0000 +@@ -0,0 +1,1098 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ++******************************************************************************/ ++/***************************************************************************** ++ * ++ * Module: __RTW_MP_PHY_REGDEF_H_ ++ * ++ * ++ * Note: 1. Define PMAC/BB register map ++ * 2. Define RF register map ++ * 3. PMAC/BB register bit mask. ++ * 4. RF reg bit mask. ++ * 5. Other BB/RF relative definition. ++ * ++ * ++ * Export: Constants, macro, functions(API), global variables(None). ++ * ++ * Abbrev: ++ * ++ * History: ++ * Data Who Remark ++ * 08/07/2007 MHC 1. Porting from 9x series PHYCFG.h. ++ * 2. Reorganize code architecture. ++ * 09/25/2008 MH 1. Add RL6052 register definition ++ * ++ *****************************************************************************/ ++#ifndef __RTW_MP_PHY_REGDEF_H_ ++#define __RTW_MP_PHY_REGDEF_H_ ++ ++ ++/*--------------------------Define Parameters-------------------------------*/ ++ ++//============================================================ ++// 8192S Regsiter offset definition ++//============================================================ ++ ++// ++// BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF ++// 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF ++// 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00 ++// 3. RF register 0x00-2E ++// 4. Bit Mask for BB/RF register ++// 5. Other defintion for BB/RF R/W ++// ++ ++ ++// ++// 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF ++// 1. Page1(0x100) ++// ++#define rPMAC_Reset 0x100 ++#define rPMAC_TxStart 0x104 ++#define rPMAC_TxLegacySIG 0x108 ++#define rPMAC_TxHTSIG1 0x10c ++#define rPMAC_TxHTSIG2 0x110 ++#define rPMAC_PHYDebug 0x114 ++#define rPMAC_TxPacketNum 0x118 ++#define rPMAC_TxIdle 0x11c ++#define rPMAC_TxMACHeader0 0x120 ++#define rPMAC_TxMACHeader1 0x124 ++#define rPMAC_TxMACHeader2 0x128 ++#define rPMAC_TxMACHeader3 0x12c ++#define rPMAC_TxMACHeader4 0x130 ++#define rPMAC_TxMACHeader5 0x134 ++#define rPMAC_TxDataType 0x138 ++#define rPMAC_TxRandomSeed 0x13c ++#define rPMAC_CCKPLCPPreamble 0x140 ++#define rPMAC_CCKPLCPHeader 0x144 ++#define rPMAC_CCKCRC16 0x148 ++#define rPMAC_OFDMRxCRC32OK 0x170 ++#define rPMAC_OFDMRxCRC32Er 0x174 ++#define rPMAC_OFDMRxParityEr 0x178 ++#define rPMAC_OFDMRxCRC8Er 0x17c ++#define rPMAC_CCKCRxRC16Er 0x180 ++#define rPMAC_CCKCRxRC32Er 0x184 ++#define rPMAC_CCKCRxRC32OK 0x188 ++#define rPMAC_TxStatus 0x18c ++ ++// ++// 2. Page2(0x200) ++// ++// The following two definition are only used for USB interface. ++//#define RF_BB_CMD_ADDR 0x02c0 // RF/BB read/write command address. ++//#define RF_BB_CMD_DATA 0x02c4 // RF/BB read/write command data. ++ ++// ++// 3. Page8(0x800) ++// ++#define rFPGA0_RFMOD 0x800 //RF mode & CCK TxSC // RF BW Setting?? ++ ++#define rFPGA0_TxInfo 0x804 // Status report?? ++#define rFPGA0_PSDFunction 0x808 ++ ++#define rFPGA0_TxGainStage 0x80c // Set TX PWR init gain? ++ ++#define rFPGA0_RFTiming1 0x810 // Useless now ++#define rFPGA0_RFTiming2 0x814 ++//#define rFPGA0_XC_RFTiming 0x818 ++//#define rFPGA0_XD_RFTiming 0x81c ++ ++#define rFPGA0_XA_HSSIParameter1 0x820 // RF 3 wire register ++#define rFPGA0_XA_HSSIParameter2 0x824 ++#define rFPGA0_XB_HSSIParameter1 0x828 ++#define rFPGA0_XB_HSSIParameter2 0x82c ++#define rFPGA0_XC_HSSIParameter1 0x830 ++#define rFPGA0_XC_HSSIParameter2 0x834 ++#define rFPGA0_XD_HSSIParameter1 0x838 ++#define rFPGA0_XD_HSSIParameter2 0x83c ++#define rFPGA0_XA_LSSIParameter 0x840 ++#define rFPGA0_XB_LSSIParameter 0x844 ++#define rFPGA0_XC_LSSIParameter 0x848 ++#define rFPGA0_XD_LSSIParameter 0x84c ++ ++#define rFPGA0_RFWakeUpParameter 0x850 // Useless now ++#define rFPGA0_RFSleepUpParameter 0x854 ++ ++#define rFPGA0_XAB_SwitchControl 0x858 // RF Channel switch ++#define rFPGA0_XCD_SwitchControl 0x85c ++ ++#define rFPGA0_XA_RFInterfaceOE 0x860 // RF Channel switch ++#define rFPGA0_XB_RFInterfaceOE 0x864 ++#define rFPGA0_XC_RFInterfaceOE 0x868 ++#define rFPGA0_XD_RFInterfaceOE 0x86c ++ ++#define rFPGA0_XAB_RFInterfaceSW 0x870 // RF Interface Software Control ++#define rFPGA0_XCD_RFInterfaceSW 0x874 ++ ++#define rFPGA0_XAB_RFParameter 0x878 // RF Parameter ++#define rFPGA0_XCD_RFParameter 0x87c ++ ++#define rFPGA0_AnalogParameter1 0x880 // Crystal cap setting RF-R/W protection for parameter4?? ++#define rFPGA0_AnalogParameter2 0x884 ++#define rFPGA0_AnalogParameter3 0x888 // Useless now ++#define rFPGA0_AnalogParameter4 0x88c ++ ++#define rFPGA0_XA_LSSIReadBack 0x8a0 // Tranceiver LSSI Readback ++#define rFPGA0_XB_LSSIReadBack 0x8a4 ++#define rFPGA0_XC_LSSIReadBack 0x8a8 ++#define rFPGA0_XD_LSSIReadBack 0x8ac ++ ++#define rFPGA0_PSDReport 0x8b4 // Useless now ++#define rFPGA0_XAB_RFInterfaceRB 0x8e0 // Useless now // RF Interface Readback Value ++#define rFPGA0_XCD_RFInterfaceRB 0x8e4 // Useless now ++ ++// ++// 4. Page9(0x900) ++// ++#define rFPGA1_RFMOD 0x900 //RF mode & OFDM TxSC // RF BW Setting?? ++ ++#define rFPGA1_TxBlock 0x904 // Useless now ++#define rFPGA1_DebugSelect 0x908 // Useless now ++#define rFPGA1_TxInfo 0x90c // Useless now // Status report?? ++ ++// ++// 5. PageA(0xA00) ++// ++// Set Control channel to upper or lower. These settings are required only for 40MHz ++#define rCCK0_System 0xa00 ++ ++#define rCCK0_AFESetting 0xa04 // Disable init gain now // Select RX path by RSSI ++#define rCCK0_CCA 0xa08 // Disable init gain now // Init gain ++ ++#define rCCK0_RxAGC1 0xa0c //AGC default value, saturation level // Antenna Diversity, RX AGC, LNA Threshold, RX LNA Threshold useless now. Not the same as 90 series ++#define rCCK0_RxAGC2 0xa10 //AGC & DAGC ++ ++#define rCCK0_RxHP 0xa14 ++ ++#define rCCK0_DSPParameter1 0xa18 //Timing recovery & Channel estimation threshold ++#define rCCK0_DSPParameter2 0xa1c //SQ threshold ++ ++#define rCCK0_TxFilter1 0xa20 ++#define rCCK0_TxFilter2 0xa24 ++#define rCCK0_DebugPort 0xa28 //debug port and Tx filter3 ++#define rCCK0_FalseAlarmReport 0xa2c //0xa2d useless now 0xa30-a4f channel report ++#define rCCK0_TRSSIReport 0xa50 ++#define rCCK0_RxReport 0xa54 //0xa57 ++#define rCCK0_FACounterLower 0xa5c //0xa5b ++#define rCCK0_FACounterUpper 0xa58 //0xa5c ++ ++// ++// 6. PageC(0xC00) ++// ++#define rOFDM0_LSTF 0xc00 ++ ++#define rOFDM0_TRxPathEnable 0xc04 ++#define rOFDM0_TRMuxPar 0xc08 ++#define rOFDM0_TRSWIsolation 0xc0c ++ ++#define rOFDM0_XARxAFE 0xc10 //RxIQ DC offset, Rx digital filter, DC notch filter ++#define rOFDM0_XARxIQImbalance 0xc14 //RxIQ imblance matrix ++#define rOFDM0_XBRxAFE 0xc18 ++#define rOFDM0_XBRxIQImbalance 0xc1c ++#define rOFDM0_XCRxAFE 0xc20 ++#define rOFDM0_XCRxIQImbalance 0xc24 ++#define rOFDM0_XDRxAFE 0xc28 ++#define rOFDM0_XDRxIQImbalance 0xc2c ++ ++#define rOFDM0_RxDetector1 0xc30 //PD,BW & SBD // DM tune init gain ++#define rOFDM0_RxDetector2 0xc34 //SBD & Fame Sync. ++#define rOFDM0_RxDetector3 0xc38 //Frame Sync. ++#define rOFDM0_RxDetector4 0xc3c //PD, SBD, Frame Sync & Short-GI ++ ++#define rOFDM0_RxDSP 0xc40 //Rx Sync Path ++#define rOFDM0_CFOandDAGC 0xc44 //CFO & DAGC ++#define rOFDM0_CCADropThreshold 0xc48 //CCA Drop threshold ++#define rOFDM0_ECCAThreshold 0xc4c // energy CCA ++ ++#define rOFDM0_XAAGCCore1 0xc50 // DIG ++#define rOFDM0_XAAGCCore2 0xc54 ++#define rOFDM0_XBAGCCore1 0xc58 ++#define rOFDM0_XBAGCCore2 0xc5c ++#define rOFDM0_XCAGCCore1 0xc60 ++#define rOFDM0_XCAGCCore2 0xc64 ++#define rOFDM0_XDAGCCore1 0xc68 ++#define rOFDM0_XDAGCCore2 0xc6c ++ ++#define rOFDM0_AGCParameter1 0xc70 ++#define rOFDM0_AGCParameter2 0xc74 ++#define rOFDM0_AGCRSSITable 0xc78 ++#define rOFDM0_HTSTFAGC 0xc7c ++ ++#define rOFDM0_XATxIQImbalance 0xc80 // TX PWR TRACK and DIG ++#define rOFDM0_XATxAFE 0xc84 ++#define rOFDM0_XBTxIQImbalance 0xc88 ++#define rOFDM0_XBTxAFE 0xc8c ++#define rOFDM0_XCTxIQImbalance 0xc90 ++#define rOFDM0_XCTxAFE 0xc94 ++#define rOFDM0_XDTxIQImbalance 0xc98 ++#define rOFDM0_XDTxAFE 0xc9c ++#define rOFDM0_RxIQExtAnta 0xca0 ++ ++#define rOFDM0_RxHPParameter 0xce0 ++#define rOFDM0_TxPseudoNoiseWgt 0xce4 ++#define rOFDM0_FrameSync 0xcf0 ++#define rOFDM0_DFSReport 0xcf4 ++#define rOFDM0_TxCoeff1 0xca4 ++#define rOFDM0_TxCoeff2 0xca8 ++#define rOFDM0_TxCoeff3 0xcac ++#define rOFDM0_TxCoeff4 0xcb0 ++#define rOFDM0_TxCoeff5 0xcb4 ++#define rOFDM0_TxCoeff6 0xcb8 ++ ++ ++// ++// 7. PageD(0xD00) ++// ++#define rOFDM1_LSTF 0xd00 ++#define rOFDM1_TRxPathEnable 0xd04 ++ ++#define rOFDM1_CFO 0xd08 // No setting now ++#define rOFDM1_CSI1 0xd10 ++#define rOFDM1_SBD 0xd14 ++#define rOFDM1_CSI2 0xd18 ++#define rOFDM1_CFOTracking 0xd2c ++#define rOFDM1_TRxMesaure1 0xd34 ++#define rOFDM1_IntfDet 0xd3c ++#define rOFDM1_PseudoNoiseStateAB 0xd50 ++#define rOFDM1_PseudoNoiseStateCD 0xd54 ++#define rOFDM1_RxPseudoNoiseWgt 0xd58 ++ ++#define rOFDM_PHYCounter1 0xda0 //cca, parity fail ++#define rOFDM_PHYCounter2 0xda4 //rate illegal, crc8 fail ++#define rOFDM_PHYCounter3 0xda8 //MCS not support ++ ++#define rOFDM_ShortCFOAB 0xdac // No setting now ++#define rOFDM_ShortCFOCD 0xdb0 ++#define rOFDM_LongCFOAB 0xdb4 ++#define rOFDM_LongCFOCD 0xdb8 ++#define rOFDM_TailCFOAB 0xdbc ++#define rOFDM_TailCFOCD 0xdc0 ++#define rOFDM_PWMeasure1 0xdc4 ++#define rOFDM_PWMeasure2 0xdc8 ++#define rOFDM_BWReport 0xdcc ++#define rOFDM_AGCReport 0xdd0 ++#define rOFDM_RxSNR 0xdd4 ++#define rOFDM_RxEVMCSI 0xdd8 ++#define rOFDM_SIGReport 0xddc ++ ++ ++// ++// 8. PageE(0xE00) ++// ++#define rTxAGC_Rate18_06 0xe00 ++#define rTxAGC_Rate54_24 0xe04 ++#define rTxAGC_CCK_Mcs32 0xe08 ++#define rTxAGC_Mcs03_Mcs00 0xe10 ++#define rTxAGC_Mcs07_Mcs04 0xe14 ++#define rTxAGC_Mcs11_Mcs08 0xe18 ++#define rTxAGC_Mcs15_Mcs12 0xe1c ++ ++// Analog- control in RX_WAIT_CCA : REG: EE0 [Analog- Power & Control Register] ++#define rRx_Wait_CCCA 0xe70 ++#define rAnapar_Ctrl_BB 0xee0 ++ ++// ++// 7. RF Register 0x00-0x2E (RF 8256) ++// RF-0222D 0x00-3F ++// ++//Zebra1 ++#define RTL92SE_FPGA_VERIFY 0 ++#define rZebra1_HSSIEnable 0x0 // Useless now ++#define rZebra1_TRxEnable1 0x1 ++#define rZebra1_TRxEnable2 0x2 ++#define rZebra1_AGC 0x4 ++#define rZebra1_ChargePump 0x5 ++//#if (RTL92SE_FPGA_VERIFY == 1) ++#define rZebra1_Channel 0x7 // RF channel switch ++//#else ++ ++//#endif ++#define rZebra1_TxGain 0x8 // Useless now ++#define rZebra1_TxLPF 0x9 ++#define rZebra1_RxLPF 0xb ++#define rZebra1_RxHPFCorner 0xc ++ ++//Zebra4 ++#define rGlobalCtrl 0 // Useless now ++#define rRTL8256_TxLPF 19 ++#define rRTL8256_RxLPF 11 ++ ++//RTL8258 ++#define rRTL8258_TxLPF 0x11 // Useless now ++#define rRTL8258_RxLPF 0x13 ++#define rRTL8258_RSSILPF 0xa ++ ++// ++// RL6052 Register definition ++// ++#define RF_AC 0x00 // ++ ++#define RF_IQADJ_G1 0x01 // ++#define RF_IQADJ_G2 0x02 // ++#define RF_POW_TRSW 0x05 // ++ ++#define RF_GAIN_RX 0x06 // ++#define RF_GAIN_TX 0x07 // ++ ++#define RF_TXM_IDAC 0x08 // ++#define RF_BS_IQGEN 0x0F // ++ ++#define RF_MODE1 0x10 // ++#define RF_MODE2 0x11 // ++ ++#define RF_RX_AGC_HP 0x12 // ++#define RF_TX_AGC 0x13 // ++#define RF_BIAS 0x14 // ++#define RF_IPA 0x15 // ++#define RF_POW_ABILITY 0x17 // ++#define RF_MODE_AG 0x18 // ++#define rRfChannel 0x18 // RF channel and BW switch ++#define RF_CHNLBW 0x18 // RF channel and BW switch ++#define RF_TOP 0x19 // ++ ++#define RF_RX_G1 0x1A // ++#define RF_RX_G2 0x1B // ++ ++#define RF_RX_BB2 0x1C // ++#define RF_RX_BB1 0x1D // ++ ++#define RF_RCK1 0x1E // ++#define RF_RCK2 0x1F // ++ ++#define RF_TX_G1 0x20 // ++#define RF_TX_G2 0x21 // ++#define RF_TX_G3 0x22 // ++ ++#define RF_TX_BB1 0x23 // ++ ++#define RF_T_METER 0x24 // ++ ++#define RF_SYN_G1 0x25 // RF TX Power control ++#define RF_SYN_G2 0x26 // RF TX Power control ++#define RF_SYN_G3 0x27 // RF TX Power control ++#define RF_SYN_G4 0x28 // RF TX Power control ++#define RF_SYN_G5 0x29 // RF TX Power control ++#define RF_SYN_G6 0x2A // RF TX Power control ++#define RF_SYN_G7 0x2B // RF TX Power control ++#define RF_SYN_G8 0x2C // RF TX Power control ++ ++#define RF_RCK_OS 0x30 // RF TX PA control ++ ++#define RF_TXPA_G1 0x31 // RF TX PA control ++#define RF_TXPA_G2 0x32 // RF TX PA control ++#define RF_TXPA_G3 0x33 // RF TX PA control ++ ++// ++//Bit Mask ++// ++// 1. Page1(0x100) ++#define bBBResetB 0x100 // Useless now? ++#define bGlobalResetB 0x200 ++#define bOFDMTxStart 0x4 ++#define bCCKTxStart 0x8 ++#define bCRC32Debug 0x100 ++#define bPMACLoopback 0x10 ++#define bTxLSIG 0xffffff ++#define bOFDMTxRate 0xf ++#define bOFDMTxReserved 0x10 ++#define bOFDMTxLength 0x1ffe0 ++#define bOFDMTxParity 0x20000 ++#define bTxHTSIG1 0xffffff ++#define bTxHTMCSRate 0x7f ++#define bTxHTBW 0x80 ++#define bTxHTLength 0xffff00 ++#define bTxHTSIG2 0xffffff ++#define bTxHTSmoothing 0x1 ++#define bTxHTSounding 0x2 ++#define bTxHTReserved 0x4 ++#define bTxHTAggreation 0x8 ++#define bTxHTSTBC 0x30 ++#define bTxHTAdvanceCoding 0x40 ++#define bTxHTShortGI 0x80 ++#define bTxHTNumberHT_LTF 0x300 ++#define bTxHTCRC8 0x3fc00 ++#define bCounterReset 0x10000 ++#define bNumOfOFDMTx 0xffff ++#define bNumOfCCKTx 0xffff0000 ++#define bTxIdleInterval 0xffff ++#define bOFDMService 0xffff0000 ++#define bTxMACHeader 0xffffffff ++#define bTxDataInit 0xff ++#define bTxHTMode 0x100 ++#define bTxDataType 0x30000 ++#define bTxRandomSeed 0xffffffff ++#define bCCKTxPreamble 0x1 ++#define bCCKTxSFD 0xffff0000 ++#define bCCKTxSIG 0xff ++#define bCCKTxService 0xff00 ++#define bCCKLengthExt 0x8000 ++#define bCCKTxLength 0xffff0000 ++#define bCCKTxCRC16 0xffff ++#define bCCKTxStatus 0x1 ++#define bOFDMTxStatus 0x2 ++ ++#define IS_BB_REG_OFFSET_92S(_Offset) ((_Offset >= 0x800) && (_Offset <= 0xfff)) ++ ++// 2. Page8(0x800) ++#define bRFMOD 0x1 // Reg 0x800 rFPGA0_RFMOD ++#define bJapanMode 0x2 ++#define bCCKTxSC 0x30 ++#define bCCKEn 0x1000000 ++#define bOFDMEn 0x2000000 ++ ++#define bOFDMRxADCPhase 0x10000 // Useless now ++#define bOFDMTxDACPhase 0x40000 ++#define bXATxAGC 0x3f ++ ++#define bXBTxAGC 0xf00 // Reg 80c rFPGA0_TxGainStage ++#define bXCTxAGC 0xf000 ++#define bXDTxAGC 0xf0000 ++ ++#define bPAStart 0xf0000000 // Useless now ++#define bTRStart 0x00f00000 ++#define bRFStart 0x0000f000 ++#define bBBStart 0x000000f0 ++#define bBBCCKStart 0x0000000f ++#define bPAEnd 0xf //Reg0x814 ++#define bTREnd 0x0f000000 ++#define bRFEnd 0x000f0000 ++#define bCCAMask 0x000000f0 //T2R ++#define bR2RCCAMask 0x00000f00 ++#define bHSSI_R2TDelay 0xf8000000 ++#define bHSSI_T2RDelay 0xf80000 ++#define bContTxHSSI 0x400 //chane gain at continue Tx ++#define bIGFromCCK 0x200 ++#define bAGCAddress 0x3f ++#define bRxHPTx 0x7000 ++#define bRxHPT2R 0x38000 ++#define bRxHPCCKIni 0xc0000 ++#define bAGCTxCode 0xc00000 ++#define bAGCRxCode 0x300000 ++ ++#define b3WireDataLength 0x800 // Reg 0x820~84f rFPGA0_XA_HSSIParameter1 ++#define b3WireAddressLength 0x400 ++ ++#define b3WireRFPowerDown 0x1 // Useless now ++//#define bHWSISelect 0x8 ++#define b5GPAPEPolarity 0x40000000 ++#define b2GPAPEPolarity 0x80000000 ++#define bRFSW_TxDefaultAnt 0x3 ++#define bRFSW_TxOptionAnt 0x30 ++#define bRFSW_RxDefaultAnt 0x300 ++#define bRFSW_RxOptionAnt 0x3000 ++#define bRFSI_3WireData 0x1 ++#define bRFSI_3WireClock 0x2 ++#define bRFSI_3WireLoad 0x4 ++#define bRFSI_3WireRW 0x8 ++#define bRFSI_3Wire 0xf ++ ++#define bRFSI_RFENV 0x10 // Reg 0x870 rFPGA0_XAB_RFInterfaceSW ++ ++#define bRFSI_TRSW 0x20 // Useless now ++#define bRFSI_TRSWB 0x40 ++#define bRFSI_ANTSW 0x100 ++#define bRFSI_ANTSWB 0x200 ++#define bRFSI_PAPE 0x400 ++#define bRFSI_PAPE5G 0x800 ++#define bBandSelect 0x1 ++#define bHTSIG2_GI 0x80 ++#define bHTSIG2_Smoothing 0x01 ++#define bHTSIG2_Sounding 0x02 ++#define bHTSIG2_Aggreaton 0x08 ++#define bHTSIG2_STBC 0x30 ++#define bHTSIG2_AdvCoding 0x40 ++#define bHTSIG2_NumOfHTLTF 0x300 ++#define bHTSIG2_CRC8 0x3fc ++#define bHTSIG1_MCS 0x7f ++#define bHTSIG1_BandWidth 0x80 ++#define bHTSIG1_HTLength 0xffff ++#define bLSIG_Rate 0xf ++#define bLSIG_Reserved 0x10 ++#define bLSIG_Length 0x1fffe ++#define bLSIG_Parity 0x20 ++#define bCCKRxPhase 0x4 ++#if (RTL92SE_FPGA_VERIFY == 1) ++#define bLSSIReadAddress 0x3f000000 //LSSI "Read" Address // Reg 0x824 rFPGA0_XA_HSSIParameter2 ++#else ++#define bLSSIReadAddress 0x7f800000 // T65 RF ++#endif ++#define bLSSIReadEdge 0x80000000 //LSSI "Read" edge signal ++#if (RTL92SE_FPGA_VERIFY == 1) ++#define bLSSIReadBackData 0xfff // Reg 0x8a0 rFPGA0_XA_LSSIReadBack ++#else ++#define bLSSIReadBackData 0xfffff // T65 RF ++#endif ++#define bLSSIReadOKFlag 0x1000 // Useless now ++#define bCCKSampleRate 0x8 //0: 44MHz, 1:88MHz ++#define bRegulator0Standby 0x1 ++#define bRegulatorPLLStandby 0x2 ++#define bRegulator1Standby 0x4 ++#define bPLLPowerUp 0x8 ++#define bDPLLPowerUp 0x10 ++#define bDA10PowerUp 0x20 ++#define bAD7PowerUp 0x200 ++#define bDA6PowerUp 0x2000 ++#define bXtalPowerUp 0x4000 ++#define b40MDClkPowerUP 0x8000 ++#define bDA6DebugMode 0x20000 ++#define bDA6Swing 0x380000 ++ ++#define bADClkPhase 0x4000000 // Reg 0x880 rFPGA0_AnalogParameter1 20/40 CCK support switch 40/80 BB MHZ ++ ++#define b80MClkDelay 0x18000000 // Useless ++#define bAFEWatchDogEnable 0x20000000 ++ ++#define bXtalCap01 0xc0000000 // Reg 0x884 rFPGA0_AnalogParameter2 Crystal cap ++#define bXtalCap23 0x3 ++#define bXtalCap92x 0x0f000000 ++#define bXtalCap 0x0f000000 ++ ++#define bIntDifClkEnable 0x400 // Useless ++#define bExtSigClkEnable 0x800 ++#define bBandgapMbiasPowerUp 0x10000 ++#define bAD11SHGain 0xc0000 ++#define bAD11InputRange 0x700000 ++#define bAD11OPCurrent 0x3800000 ++#define bIPathLoopback 0x4000000 ++#define bQPathLoopback 0x8000000 ++#define bAFELoopback 0x10000000 ++#define bDA10Swing 0x7e0 ++#define bDA10Reverse 0x800 ++#define bDAClkSource 0x1000 ++#define bAD7InputRange 0x6000 ++#define bAD7Gain 0x38000 ++#define bAD7OutputCMMode 0x40000 ++#define bAD7InputCMMode 0x380000 ++#define bAD7Current 0xc00000 ++#define bRegulatorAdjust 0x7000000 ++#define bAD11PowerUpAtTx 0x1 ++#define bDA10PSAtTx 0x10 ++#define bAD11PowerUpAtRx 0x100 ++#define bDA10PSAtRx 0x1000 ++#define bCCKRxAGCFormat 0x200 ++#define bPSDFFTSamplepPoint 0xc000 ++#define bPSDAverageNum 0x3000 ++#define bIQPathControl 0xc00 ++#define bPSDFreq 0x3ff ++#define bPSDAntennaPath 0x30 ++#define bPSDIQSwitch 0x40 ++#define bPSDRxTrigger 0x400000 ++#define bPSDTxTrigger 0x80000000 ++#define bPSDSineToneScale 0x7f000000 ++#define bPSDReport 0xffff ++ ++// 3. Page9(0x900) ++#define bOFDMTxSC 0x30000000 // Useless ++#define bCCKTxOn 0x1 ++#define bOFDMTxOn 0x2 ++#define bDebugPage 0xfff //reset debug page and also HWord, LWord ++#define bDebugItem 0xff //reset debug page and LWord ++#define bAntL 0x10 ++#define bAntNonHT 0x100 ++#define bAntHT1 0x1000 ++#define bAntHT2 0x10000 ++#define bAntHT1S1 0x100000 ++#define bAntNonHTS1 0x1000000 ++ ++// 4. PageA(0xA00) ++#define bCCKBBMode 0x3 // Useless ++#define bCCKTxPowerSaving 0x80 ++#define bCCKRxPowerSaving 0x40 ++ ++#define bCCKSideBand 0x10 // Reg 0xa00 rCCK0_System 20/40 switch ++ ++#define bCCKScramble 0x8 // Useless ++#define bCCKAntDiversity 0x8000 ++#define bCCKCarrierRecovery 0x4000 ++#define bCCKTxRate 0x3000 ++#define bCCKDCCancel 0x0800 ++#define bCCKISICancel 0x0400 ++#define bCCKMatchFilter 0x0200 ++#define bCCKEqualizer 0x0100 ++#define bCCKPreambleDetect 0x800000 ++#define bCCKFastFalseCCA 0x400000 ++#define bCCKChEstStart 0x300000 ++#define bCCKCCACount 0x080000 ++#define bCCKcs_lim 0x070000 ++#define bCCKBistMode 0x80000000 ++#define bCCKCCAMask 0x40000000 ++#define bCCKTxDACPhase 0x4 ++#define bCCKRxADCPhase 0x20000000 //r_rx_clk ++#define bCCKr_cp_mode0 0x0100 ++#define bCCKTxDCOffset 0xf0 ++#define bCCKRxDCOffset 0xf ++#define bCCKCCAMode 0xc000 ++#define bCCKFalseCS_lim 0x3f00 ++#define bCCKCS_ratio 0xc00000 ++#define bCCKCorgBit_sel 0x300000 ++#define bCCKPD_lim 0x0f0000 ++#define bCCKNewCCA 0x80000000 ++#define bCCKRxHPofIG 0x8000 ++#define bCCKRxIG 0x7f00 ++#define bCCKLNAPolarity 0x800000 ++#define bCCKRx1stGain 0x7f0000 ++#define bCCKRFExtend 0x20000000 //CCK Rx Iinital gain polarity ++#define bCCKRxAGCSatLevel 0x1f000000 ++#define bCCKRxAGCSatCount 0xe0 ++#define bCCKRxRFSettle 0x1f //AGCsamp_dly ++#define bCCKFixedRxAGC 0x8000 ++//#define bCCKRxAGCFormat 0x4000 //remove to HSSI register 0x824 ++#define bCCKAntennaPolarity 0x2000 ++#define bCCKTxFilterType 0x0c00 ++#define bCCKRxAGCReportType 0x0300 ++#define bCCKRxDAGCEn 0x80000000 ++#define bCCKRxDAGCPeriod 0x20000000 ++#define bCCKRxDAGCSatLevel 0x1f000000 ++#define bCCKTimingRecovery 0x800000 ++#define bCCKTxC0 0x3f0000 ++#define bCCKTxC1 0x3f000000 ++#define bCCKTxC2 0x3f ++#define bCCKTxC3 0x3f00 ++#define bCCKTxC4 0x3f0000 ++#define bCCKTxC5 0x3f000000 ++#define bCCKTxC6 0x3f ++#define bCCKTxC7 0x3f00 ++#define bCCKDebugPort 0xff0000 ++#define bCCKDACDebug 0x0f000000 ++#define bCCKFalseAlarmEnable 0x8000 ++#define bCCKFalseAlarmRead 0x4000 ++#define bCCKTRSSI 0x7f ++#define bCCKRxAGCReport 0xfe ++#define bCCKRxReport_AntSel 0x80000000 ++#define bCCKRxReport_MFOff 0x40000000 ++#define bCCKRxRxReport_SQLoss 0x20000000 ++#define bCCKRxReport_Pktloss 0x10000000 ++#define bCCKRxReport_Lockedbit 0x08000000 ++#define bCCKRxReport_RateError 0x04000000 ++#define bCCKRxReport_RxRate 0x03000000 ++#define bCCKRxFACounterLower 0xff ++#define bCCKRxFACounterUpper 0xff000000 ++#define bCCKRxHPAGCStart 0xe000 ++#define bCCKRxHPAGCFinal 0x1c00 ++#define bCCKRxFalseAlarmEnable 0x8000 ++#define bCCKFACounterFreeze 0x4000 ++#define bCCKTxPathSel 0x10000000 ++#define bCCKDefaultRxPath 0xc000000 ++#define bCCKOptionRxPath 0x3000000 ++ ++// 5. PageC(0xC00) ++#define bNumOfSTF 0x3 // Useless ++#define bShift_L 0xc0 ++#define bGI_TH 0xc ++#define bRxPathA 0x1 ++#define bRxPathB 0x2 ++#define bRxPathC 0x4 ++#define bRxPathD 0x8 ++#define bTxPathA 0x1 ++#define bTxPathB 0x2 ++#define bTxPathC 0x4 ++#define bTxPathD 0x8 ++#define bTRSSIFreq 0x200 ++#define bADCBackoff 0x3000 ++#define bDFIRBackoff 0xc000 ++#define bTRSSILatchPhase 0x10000 ++#define bRxIDCOffset 0xff ++#define bRxQDCOffset 0xff00 ++#define bRxDFIRMode 0x1800000 ++#define bRxDCNFType 0xe000000 ++#define bRXIQImb_A 0x3ff ++#define bRXIQImb_B 0xfc00 ++#define bRXIQImb_C 0x3f0000 ++#define bRXIQImb_D 0xffc00000 ++#define bDC_dc_Notch 0x60000 ++#define bRxNBINotch 0x1f000000 ++#define bPD_TH 0xf ++#define bPD_TH_Opt2 0xc000 ++#define bPWED_TH 0x700 ++#define bIfMF_Win_L 0x800 ++#define bPD_Option 0x1000 ++#define bMF_Win_L 0xe000 ++#define bBW_Search_L 0x30000 ++#define bwin_enh_L 0xc0000 ++#define bBW_TH 0x700000 ++#define bED_TH2 0x3800000 ++#define bBW_option 0x4000000 ++#define bRatio_TH 0x18000000 ++#define bWindow_L 0xe0000000 ++#define bSBD_Option 0x1 ++#define bFrame_TH 0x1c ++#define bFS_Option 0x60 ++#define bDC_Slope_check 0x80 ++#define bFGuard_Counter_DC_L 0xe00 ++#define bFrame_Weight_Short 0x7000 ++#define bSub_Tune 0xe00000 ++#define bFrame_DC_Length 0xe000000 ++#define bSBD_start_offset 0x30000000 ++#define bFrame_TH_2 0x7 ++#define bFrame_GI2_TH 0x38 ++#define bGI2_Sync_en 0x40 ++#define bSarch_Short_Early 0x300 ++#define bSarch_Short_Late 0xc00 ++#define bSarch_GI2_Late 0x70000 ++#define bCFOAntSum 0x1 ++#define bCFOAcc 0x2 ++#define bCFOStartOffset 0xc ++#define bCFOLookBack 0x70 ++#define bCFOSumWeight 0x80 ++#define bDAGCEnable 0x10000 ++#define bTXIQImb_A 0x3ff ++#define bTXIQImb_B 0xfc00 ++#define bTXIQImb_C 0x3f0000 ++#define bTXIQImb_D 0xffc00000 ++#define bTxIDCOffset 0xff ++#define bTxQDCOffset 0xff00 ++#define bTxDFIRMode 0x10000 ++#define bTxPesudoNoiseOn 0x4000000 ++#define bTxPesudoNoise_A 0xff ++#define bTxPesudoNoise_B 0xff00 ++#define bTxPesudoNoise_C 0xff0000 ++#define bTxPesudoNoise_D 0xff000000 ++#define bCCADropOption 0x20000 ++#define bCCADropThres 0xfff00000 ++#define bEDCCA_H 0xf ++#define bEDCCA_L 0xf0 ++#define bLambda_ED 0x300 ++#define bRxInitialGain 0x7f ++#define bRxAntDivEn 0x80 ++#define bRxAGCAddressForLNA 0x7f00 ++#define bRxHighPowerFlow 0x8000 ++#define bRxAGCFreezeThres 0xc0000 ++#define bRxFreezeStep_AGC1 0x300000 ++#define bRxFreezeStep_AGC2 0xc00000 ++#define bRxFreezeStep_AGC3 0x3000000 ++#define bRxFreezeStep_AGC0 0xc000000 ++#define bRxRssi_Cmp_En 0x10000000 ++#define bRxQuickAGCEn 0x20000000 ++#define bRxAGCFreezeThresMode 0x40000000 ++#define bRxOverFlowCheckType 0x80000000 ++#define bRxAGCShift 0x7f ++#define bTRSW_Tri_Only 0x80 ++#define bPowerThres 0x300 ++#define bRxAGCEn 0x1 ++#define bRxAGCTogetherEn 0x2 ++#define bRxAGCMin 0x4 ++#define bRxHP_Ini 0x7 ++#define bRxHP_TRLNA 0x70 ++#define bRxHP_RSSI 0x700 ++#define bRxHP_BBP1 0x7000 ++#define bRxHP_BBP2 0x70000 ++#define bRxHP_BBP3 0x700000 ++#define bRSSI_H 0x7f0000 //the threshold for high power ++#define bRSSI_Gen 0x7f000000 //the threshold for ant diversity ++#define bRxSettle_TRSW 0x7 ++#define bRxSettle_LNA 0x38 ++#define bRxSettle_RSSI 0x1c0 ++#define bRxSettle_BBP 0xe00 ++#define bRxSettle_RxHP 0x7000 ++#define bRxSettle_AntSW_RSSI 0x38000 ++#define bRxSettle_AntSW 0xc0000 ++#define bRxProcessTime_DAGC 0x300000 ++#define bRxSettle_HSSI 0x400000 ++#define bRxProcessTime_BBPPW 0x800000 ++#define bRxAntennaPowerShift 0x3000000 ++#define bRSSITableSelect 0xc000000 ++#define bRxHP_Final 0x7000000 ++#define bRxHTSettle_BBP 0x7 ++#define bRxHTSettle_HSSI 0x8 ++#define bRxHTSettle_RxHP 0x70 ++#define bRxHTSettle_BBPPW 0x80 ++#define bRxHTSettle_Idle 0x300 ++#define bRxHTSettle_Reserved 0x1c00 ++#define bRxHTRxHPEn 0x8000 ++#define bRxHTAGCFreezeThres 0x30000 ++#define bRxHTAGCTogetherEn 0x40000 ++#define bRxHTAGCMin 0x80000 ++#define bRxHTAGCEn 0x100000 ++#define bRxHTDAGCEn 0x200000 ++#define bRxHTRxHP_BBP 0x1c00000 ++#define bRxHTRxHP_Final 0xe0000000 ++#define bRxPWRatioTH 0x3 ++#define bRxPWRatioEn 0x4 ++#define bRxMFHold 0x3800 ++#define bRxPD_Delay_TH1 0x38 ++#define bRxPD_Delay_TH2 0x1c0 ++#define bRxPD_DC_COUNT_MAX 0x600 ++//#define bRxMF_Hold 0x3800 ++#define bRxPD_Delay_TH 0x8000 ++#define bRxProcess_Delay 0xf0000 ++#define bRxSearchrange_GI2_Early 0x700000 ++#define bRxFrame_Guard_Counter_L 0x3800000 ++#define bRxSGI_Guard_L 0xc000000 ++#define bRxSGI_Search_L 0x30000000 ++#define bRxSGI_TH 0xc0000000 ++#define bDFSCnt0 0xff ++#define bDFSCnt1 0xff00 ++#define bDFSFlag 0xf0000 ++#define bMFWeightSum 0x300000 ++#define bMinIdxTH 0x7f000000 ++#define bDAFormat 0x40000 ++#define bTxChEmuEnable 0x01000000 ++#define bTRSWIsolation_A 0x7f ++#define bTRSWIsolation_B 0x7f00 ++#define bTRSWIsolation_C 0x7f0000 ++#define bTRSWIsolation_D 0x7f000000 ++#define bExtLNAGain 0x7c00 ++ ++// 6. PageE(0xE00) ++#define bSTBCEn 0x4 // Useless ++#define bAntennaMapping 0x10 ++#define bNss 0x20 ++#define bCFOAntSumD 0x200 ++#define bPHYCounterReset 0x8000000 ++#define bCFOReportGet 0x4000000 ++#define bOFDMContinueTx 0x10000000 ++#define bOFDMSingleCarrier 0x20000000 ++#define bOFDMSingleTone 0x40000000 ++//#define bRxPath1 0x01 ++//#define bRxPath2 0x02 ++//#define bRxPath3 0x04 ++//#define bRxPath4 0x08 ++//#define bTxPath1 0x10 ++//#define bTxPath2 0x20 ++#define bHTDetect 0x100 ++#define bCFOEn 0x10000 ++#define bCFOValue 0xfff00000 ++#define bSigTone_Re 0x3f ++#define bSigTone_Im 0x7f00 ++#define bCounter_CCA 0xffff ++#define bCounter_ParityFail 0xffff0000 ++#define bCounter_RateIllegal 0xffff ++#define bCounter_CRC8Fail 0xffff0000 ++#define bCounter_MCSNoSupport 0xffff ++#define bCounter_FastSync 0xffff ++#define bShortCFO 0xfff ++#define bShortCFOTLength 12 //total ++#define bShortCFOFLength 11 //fraction ++#define bLongCFO 0x7ff ++#define bLongCFOTLength 11 ++#define bLongCFOFLength 11 ++#define bTailCFO 0x1fff ++#define bTailCFOTLength 13 ++#define bTailCFOFLength 12 ++#define bmax_en_pwdB 0xffff ++#define bCC_power_dB 0xffff0000 ++#define bnoise_pwdB 0xffff ++#define bPowerMeasTLength 10 ++#define bPowerMeasFLength 3 ++#define bRx_HT_BW 0x1 ++#define bRxSC 0x6 ++#define bRx_HT 0x8 ++#define bNB_intf_det_on 0x1 ++#define bIntf_win_len_cfg 0x30 ++#define bNB_Intf_TH_cfg 0x1c0 ++#define bRFGain 0x3f ++#define bTableSel 0x40 ++#define bTRSW 0x80 ++#define bRxSNR_A 0xff ++#define bRxSNR_B 0xff00 ++#define bRxSNR_C 0xff0000 ++#define bRxSNR_D 0xff000000 ++#define bSNREVMTLength 8 ++#define bSNREVMFLength 1 ++#define bCSI1st 0xff ++#define bCSI2nd 0xff00 ++#define bRxEVM1st 0xff0000 ++#define bRxEVM2nd 0xff000000 ++#define bSIGEVM 0xff ++#define bPWDB 0xff00 ++#define bSGIEN 0x10000 ++ ++#define bSFactorQAM1 0xf // Useless ++#define bSFactorQAM2 0xf0 ++#define bSFactorQAM3 0xf00 ++#define bSFactorQAM4 0xf000 ++#define bSFactorQAM5 0xf0000 ++#define bSFactorQAM6 0xf0000 ++#define bSFactorQAM7 0xf00000 ++#define bSFactorQAM8 0xf000000 ++#define bSFactorQAM9 0xf0000000 ++#define bCSIScheme 0x100000 ++ ++#define bNoiseLvlTopSet 0x3 // Useless ++#define bChSmooth 0x4 ++#define bChSmoothCfg1 0x38 ++#define bChSmoothCfg2 0x1c0 ++#define bChSmoothCfg3 0xe00 ++#define bChSmoothCfg4 0x7000 ++#define bMRCMode 0x800000 ++#define bTHEVMCfg 0x7000000 ++ ++#define bLoopFitType 0x1 // Useless ++#define bUpdCFO 0x40 ++#define bUpdCFOOffData 0x80 ++#define bAdvUpdCFO 0x100 ++#define bAdvTimeCtrl 0x800 ++#define bUpdClko 0x1000 ++#define bFC 0x6000 ++#define bTrackingMode 0x8000 ++#define bPhCmpEnable 0x10000 ++#define bUpdClkoLTF 0x20000 ++#define bComChCFO 0x40000 ++#define bCSIEstiMode 0x80000 ++#define bAdvUpdEqz 0x100000 ++#define bUChCfg 0x7000000 ++#define bUpdEqz 0x8000000 ++ ++#define bTxAGCRate18_06 0x7f7f7f7f // Useless ++#define bTxAGCRate54_24 0x7f7f7f7f ++#define bTxAGCRateMCS32 0x7f ++#define bTxAGCRateCCK 0x7f00 ++#define bTxAGCRateMCS3_MCS0 0x7f7f7f7f ++#define bTxAGCRateMCS7_MCS4 0x7f7f7f7f ++#define bTxAGCRateMCS11_MCS8 0x7f7f7f7f ++#define bTxAGCRateMCS15_MCS12 0x7f7f7f7f ++ ++//Rx Pseduo noise ++#define bRxPesudoNoiseOn 0x20000000 // Useless ++#define bRxPesudoNoise_A 0xff ++#define bRxPesudoNoise_B 0xff00 ++#define bRxPesudoNoise_C 0xff0000 ++#define bRxPesudoNoise_D 0xff000000 ++#define bPesudoNoiseState_A 0xffff ++#define bPesudoNoiseState_B 0xffff0000 ++#define bPesudoNoiseState_C 0xffff ++#define bPesudoNoiseState_D 0xffff0000 ++ ++//7. RF Register ++//Zebra1 ++#define bZebra1_HSSIEnable 0x8 // Useless ++#define bZebra1_TRxControl 0xc00 ++#define bZebra1_TRxGainSetting 0x07f ++#define bZebra1_RxCorner 0xc00 ++#define bZebra1_TxChargePump 0x38 ++#define bZebra1_RxChargePump 0x7 ++#define bZebra1_ChannelNum 0xf80 ++#define bZebra1_TxLPFBW 0x400 ++#define bZebra1_RxLPFBW 0x600 ++ ++//Zebra4 ++#define bRTL8256RegModeCtrl1 0x100 // Useless ++#define bRTL8256RegModeCtrl0 0x40 ++#define bRTL8256_TxLPFBW 0x18 ++#define bRTL8256_RxLPFBW 0x600 ++ ++//RTL8258 ++#define bRTL8258_TxLPFBW 0xc // Useless ++#define bRTL8258_RxLPFBW 0xc00 ++#define bRTL8258_RSSILPFBW 0xc0 ++ ++ ++// ++// Other Definition ++// ++ ++//byte endable for sb_write ++#define bByte0 0x1 // Useless ++#define bByte1 0x2 ++#define bByte2 0x4 ++#define bByte3 0x8 ++#define bWord0 0x3 ++#define bWord1 0xc ++#define bDWord 0xf ++ ++//for PutRegsetting & GetRegSetting BitMask ++#define bMaskByte0 0xff // Reg 0xc50 rOFDM0_XAAGCCore~0xC6f ++#define bMaskByte1 0xff00 ++#define bMaskByte2 0xff0000 ++#define bMaskByte3 0xff000000 ++#define bMaskHWord 0xffff0000 ++#define bMaskLWord 0x0000ffff ++#define bMaskDWord 0xffffffff ++#define bMaskH4Bits 0xf0000000 ++#define bMaskOFDM_D 0xffc00000 ++#define bMaskCCK 0x3f3f3f3f ++#define bMask12Bits 0xfff ++ ++//for PutRFRegsetting & GetRFRegSetting BitMask ++#if (RTL92SE_FPGA_VERIFY == 1) ++//#define bMask12Bits 0xfff // RF Reg mask bits ++//#define bMask20Bits 0xfff // RF Reg mask bits T65 RF ++#define bRFRegOffsetMask 0xfff ++#else ++//#define bMask12Bits 0xfffff // RF Reg mask bits ++//#define bMask20Bits 0xfffff // RF Reg mask bits T65 RF ++#define bRFRegOffsetMask 0xfffff ++#endif ++#define bEnable 0x1 // Useless ++#define bDisable 0x0 ++ ++#define LeftAntenna 0x0 // Useless ++#define RightAntenna 0x1 ++ ++#define tCheckTxStatus 500 //500ms // Useless ++#define tUpdateRxCounter 100 //100ms ++ ++#define rateCCK 0 // Useless ++#define rateOFDM 1 ++#define rateHT 2 ++ ++//define Register-End ++#define bPMAC_End 0x1ff // Useless ++#define bFPGAPHY0_End 0x8ff ++#define bFPGAPHY1_End 0x9ff ++#define bCCKPHY0_End 0xaff ++#define bOFDMPHY0_End 0xcff ++#define bOFDMPHY1_End 0xdff ++ ++//define max debug item in each debug page ++//#define bMaxItem_FPGA_PHY0 0x9 ++//#define bMaxItem_FPGA_PHY1 0x3 ++//#define bMaxItem_PHY_11B 0x16 ++//#define bMaxItem_OFDM_PHY0 0x29 ++//#define bMaxItem_OFDM_PHY1 0x0 ++ ++#define bPMACControl 0x0 // Useless ++#define bWMACControl 0x1 ++#define bWNICControl 0x2 ++ ++#if 0 ++#define ANTENNA_A 0x1 // Useless ++#define ANTENNA_B 0x2 ++#define ANTENNA_AB 0x3 // ANTENNA_A|ANTENNA_B ++ ++#define ANTENNA_C 0x4 ++#define ANTENNA_D 0x8 ++#endif ++ ++#define RCR_AAP BIT(0) // accept all physical address ++#define RCR_APM BIT(1) // accept physical match ++#define RCR_AM BIT(2) // accept multicast ++#define RCR_AB BIT(3) // accept broadcast ++#define RCR_ACRC32 BIT(5) // accept error packet ++#define RCR_9356SEL BIT(6) ++#define RCR_AICV BIT(12) // Accept ICV error packet ++#define RCR_RXFTH0 (BIT(13)|BIT(14)|BIT(15)) // Rx FIFO threshold ++#define RCR_ADF BIT(18) // Accept Data(frame type) frame ++#define RCR_ACF BIT(19) // Accept control frame ++#define RCR_AMF BIT(20) // Accept management frame ++#define RCR_ADD3 BIT(21) ++#define RCR_APWRMGT BIT(22) // Accept power management packet ++#define RCR_CBSSID BIT(23) // Accept BSSID match packet ++#define RCR_ENMARP BIT(28) // enable mac auto reset phy ++#define RCR_EnCS1 BIT(29) // enable carrier sense method 1 ++#define RCR_EnCS2 BIT(30) // enable carrier sense method 2 ++#define RCR_OnlyErlPkt BIT(31) // Rx Early mode is performed for packet size greater than 1536 ++ ++/*--------------------------Define Parameters-------------------------------*/ ++ ++ ++#endif //__INC_HAL8192SPHYREG_H ++ +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/include/rtw_p2p.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/include/rtw_p2p.h 2013-07-26 19:36:06.000000000 +0000 +@@ -0,0 +1,139 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#ifndef __RTW_P2P_H_ ++#define __RTW_P2P_H_ ++ ++#include ++ ++u32 build_beacon_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pbuf); ++u32 build_probe_resp_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pbuf); ++u32 build_prov_disc_request_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pbuf, u8* pssid, u8 ussidlen, u8* pdev_raddr ); ++u32 build_assoc_resp_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pbuf, u8 status_code); ++u32 build_deauth_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pbuf); ++#ifdef CONFIG_WFD ++u32 build_probe_req_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf); ++u32 build_probe_resp_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf); ++u32 build_beacon_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf); ++u32 build_nego_req_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf); ++u32 build_nego_resp_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf); ++u32 build_nego_confirm_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf); ++u32 build_assoc_req_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf); ++u32 build_assoc_resp_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf); ++u32 build_provdisc_req_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf); ++u32 build_provdisc_resp_wfd_ie(struct wifidirect_info *pwdinfo, u8 *pbuf); ++#endif //CONFIG_WFD ++ ++u32 process_probe_req_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pframe, uint len); ++u32 process_assoc_req_p2p_ie(struct wifidirect_info *pwdinfo, u8 *pframe, uint len, struct sta_info *psta); ++u32 process_p2p_devdisc_req(struct wifidirect_info *pwdinfo, u8 *pframe, uint len); ++u32 process_p2p_devdisc_resp(struct wifidirect_info *pwdinfo, u8 *pframe, uint len); ++u8 process_p2p_provdisc_req(struct wifidirect_info *pwdinfo, u8 *pframe, uint len); ++u8 process_p2p_provdisc_resp(struct wifidirect_info *pwdinfo, u8 *pframe); ++u8 process_p2p_group_negotation_req( struct wifidirect_info *pwdinfo, u8 *pframe, uint len ); ++u8 process_p2p_group_negotation_resp( struct wifidirect_info *pwdinfo, u8 *pframe, uint len ); ++u8 process_p2p_group_negotation_confirm( struct wifidirect_info *pwdinfo, u8 *pframe, uint len ); ++u8 process_p2p_presence_req(struct wifidirect_info *pwdinfo, u8 *pframe, uint len); ++ ++void process_p2p_ps_ie(PADAPTER padapter, u8 *IEs, u32 IELength); ++void p2p_ps_wk_hdl(_adapter *padapter, u8 p2p_ps_state); ++void p2p_protocol_wk_hdl(_adapter *padapter, int intCmdType); ++u8 p2p_ps_wk_cmd(_adapter*padapter, u8 p2p_ps_state, u8 enqueue); ++ ++#ifdef CONFIG_IOCTL_CFG80211 ++void rtw_init_cfg80211_wifidirect_info( _adapter* padapter); ++int rtw_p2p_check_frames(_adapter *padapter, const u8 *buf, u32 len, u8 tx); ++#endif //CONFIG_IOCTL_CFG80211 ++ ++void init_wifidirect_info( _adapter* padapter, enum P2P_ROLE role); ++int rtw_p2p_enable(_adapter *padapter, enum P2P_ROLE role); ++ ++static inline void _rtw_p2p_set_state(struct wifidirect_info *wdinfo, enum P2P_STATE state) ++{ ++ if(wdinfo->p2p_state != state) { ++ //wdinfo->pre_p2p_state = wdinfo->p2p_state; ++ wdinfo->p2p_state = state; ++ } ++} ++static inline void _rtw_p2p_set_pre_state(struct wifidirect_info *wdinfo, enum P2P_STATE state) ++{ ++ if(wdinfo->pre_p2p_state != state) { ++ wdinfo->pre_p2p_state = state; ++ } ++} ++#if 0 ++static inline void _rtw_p2p_restore_state(struct wifidirect_info *wdinfo) ++{ ++ if(wdinfo->pre_p2p_state != -1) { ++ wdinfo->p2p_state = wdinfo->pre_p2p_state; ++ wdinfo->pre_p2p_state = -1; ++ } ++} ++#endif ++static inline void _rtw_p2p_set_role(struct wifidirect_info *wdinfo, enum P2P_ROLE role) ++{ ++ if(wdinfo->role != role) { ++ wdinfo->role = role; ++ } ++} ++static inline int _rtw_p2p_state(struct wifidirect_info *wdinfo) ++{ ++ return wdinfo->p2p_state; ++} ++static inline int _rtw_p2p_pre_state(struct wifidirect_info *wdinfo) ++{ ++ return wdinfo->pre_p2p_state; ++} ++static inline int _rtw_p2p_role(struct wifidirect_info *wdinfo) ++{ ++ return wdinfo->role; ++} ++static inline bool _rtw_p2p_chk_state(struct wifidirect_info *wdinfo, enum P2P_STATE state) ++{ ++ return wdinfo->p2p_state == state; ++} ++static inline bool _rtw_p2p_chk_role(struct wifidirect_info *wdinfo, enum P2P_ROLE role) ++{ ++ return wdinfo->role == role; ++} ++ ++#ifdef CONFIG_DBG_P2P ++void dbg_rtw_p2p_set_state(struct wifidirect_info *wdinfo, enum P2P_STATE state, const char *caller, int line); ++void dbg_rtw_p2p_set_pre_state(struct wifidirect_info *wdinfo, enum P2P_STATE state, const char *caller, int line); ++//void dbg_rtw_p2p_restore_state(struct wifidirect_info *wdinfo, const char *caller, int line); ++void dbg_rtw_p2p_set_role(struct wifidirect_info *wdinfo, enum P2P_ROLE role, const char *caller, int line); ++#define rtw_p2p_set_state(wdinfo, state) dbg_rtw_p2p_set_state(wdinfo, state, __FUNCTION__, __LINE__) ++#define rtw_p2p_set_pre_state(wdinfo, state) dbg_rtw_p2p_set_pre_state(wdinfo, state, __FUNCTION__, __LINE__) ++#define rtw_p2p_set_role(wdinfo, role) dbg_rtw_p2p_set_role(wdinfo, role, __FUNCTION__, __LINE__) ++//#define rtw_p2p_restore_state(wdinfo) dbg_rtw_p2p_restore_state(wdinfo, __FUNCTION__, __LINE__) ++#else //CONFIG_DBG_P2P ++#define rtw_p2p_set_state(wdinfo, state) _rtw_p2p_set_state(wdinfo, state) ++#define rtw_p2p_set_pre_state(wdinfo, state) _rtw_p2p_set_pre_state(wdinfo, state) ++#define rtw_p2p_set_role(wdinfo, role) _rtw_p2p_set_role(wdinfo, role) ++//#define rtw_p2p_restore_state(wdinfo) _rtw_p2p_restore_state(wdinfo) ++#endif //CONFIG_DBG_P2P ++ ++#define rtw_p2p_state(wdinfo) _rtw_p2p_state(wdinfo) ++#define rtw_p2p_pre_state(wdinfo) _rtw_p2p_pre_state(wdinfo) ++#define rtw_p2p_role(wdinfo) _rtw_p2p_role(wdinfo) ++#define rtw_p2p_chk_state(wdinfo, state) _rtw_p2p_chk_state(wdinfo, state) ++#define rtw_p2p_chk_role(wdinfo, role) _rtw_p2p_chk_role(wdinfo, role) ++ ++#endif ++ +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/include/rtw_pwrctrl.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/include/rtw_pwrctrl.h 2013-07-26 19:36:06.000000000 +0000 +@@ -0,0 +1,343 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ++******************************************************************************/ ++#ifndef __RTW_PWRCTRL_H_ ++#define __RTW_PWRCTRL_H_ ++ ++#include ++#include ++#include ++ ++#ifdef CONFIG_HAS_EARLYSUSPEND ++#include ++#endif //CONFIG_HAS_EARLYSUSPEND ++ ++ ++#define FW_PWR0 0 ++#define FW_PWR1 1 ++#define FW_PWR2 2 ++#define FW_PWR3 3 ++ ++ ++#define HW_PWR0 7 ++#define HW_PWR1 6 ++#define HW_PWR2 2 ++#define HW_PWR3 0 ++#define HW_PWR4 8 ++ ++#define FW_PWRMSK 0x7 ++ ++ ++#define XMIT_ALIVE BIT(0) ++#define RECV_ALIVE BIT(1) ++#define CMD_ALIVE BIT(2) ++#define EVT_ALIVE BIT(3) ++ ++ ++enum Power_Mgnt ++{ ++ PS_MODE_ACTIVE = 0 , ++ PS_MODE_MIN , ++ PS_MODE_MAX , ++ PS_MODE_DTIM , ++ PS_MODE_VOIP , ++ PS_MODE_UAPSD_WMM , ++ PS_MODE_UAPSD , ++ PS_MODE_IBSS , ++ PS_MODE_WWLAN , ++ PM_Radio_Off , ++ PM_Card_Disable , ++ PS_MODE_NUM ++}; ++ ++ ++/* ++ BIT[2:0] = HW state ++ BIT[3] = Protocol PS state, 0: register active state , 1: register sleep state ++ BIT[4] = sub-state ++*/ ++ ++#define PS_DPS BIT(0) ++#define PS_LCLK (PS_DPS) ++#define PS_RF_OFF BIT(1) ++#define PS_ALL_ON BIT(2) ++#define PS_ST_ACTIVE BIT(3) ++#define PS_LP BIT(4) // low performance ++ ++#define PS_STATE_MASK (0x0F) ++#define PS_STATE_HW_MASK (0x07) ++#define PS_SEQ_MASK (0xc0) ++ ++#define PS_STATE(x) (PS_STATE_MASK & (x)) ++#define PS_STATE_HW(x) (PS_STATE_HW_MASK & (x)) ++#define PS_SEQ(x) (PS_SEQ_MASK & (x)) ++ ++#define PS_STATE_S0 (PS_DPS) ++#define PS_STATE_S1 (PS_LCLK) ++#define PS_STATE_S2 (PS_RF_OFF) ++#define PS_STATE_S3 (PS_ALL_ON) ++#define PS_STATE_S4 ((PS_ST_ACTIVE) | (PS_ALL_ON)) ++ ++ ++#define PS_IS_RF_ON(x) ((x) & (PS_ALL_ON)) ++#define PS_IS_ACTIVE(x) ((x) & (PS_ST_ACTIVE)) ++#define CLR_PS_STATE(x) ((x) = ((x) & (0xF0))) ++ ++ ++struct reportpwrstate_parm { ++ unsigned char mode; ++ unsigned char state; //the CPWM value ++ unsigned short rsvd; ++}; ++ ++ ++typedef _sema _pwrlock; ++ ++ ++__inline static void _init_pwrlock(_pwrlock *plock) ++{ ++ _rtw_init_sema(plock, 1); ++} ++ ++__inline static void _free_pwrlock(_pwrlock *plock) ++{ ++ _rtw_free_sema(plock); ++} ++ ++ ++__inline static void _enter_pwrlock(_pwrlock *plock) ++{ ++ _rtw_down_sema(plock); ++} ++ ++ ++__inline static void _exit_pwrlock(_pwrlock *plock) ++{ ++ _rtw_up_sema(plock); ++} ++ ++#define LPS_DELAY_TIME 1*HZ // 1 sec ++ ++#define EXE_PWR_NONE 0x01 ++#define EXE_PWR_IPS 0x02 ++#define EXE_PWR_LPS 0x04 ++ ++// RF state. ++typedef enum _rt_rf_power_state ++{ ++ rf_on, // RF is on after RFSleep or RFOff ++ rf_sleep, // 802.11 Power Save mode ++ rf_off, // HW/SW Radio OFF or Inactive Power Save ++ //=====Add the new RF state above this line=====// ++ rf_max ++}rt_rf_power_state; ++ ++// RF Off Level for IPS or HW/SW radio off ++#define RT_RF_OFF_LEVL_ASPM BIT(0) // PCI ASPM ++#define RT_RF_OFF_LEVL_CLK_REQ BIT(1) // PCI clock request ++#define RT_RF_OFF_LEVL_PCI_D3 BIT(2) // PCI D3 mode ++#define RT_RF_OFF_LEVL_HALT_NIC BIT(3) // NIC halt, re-initialize hw parameters ++#define RT_RF_OFF_LEVL_FREE_FW BIT(4) // FW free, re-download the FW ++#define RT_RF_OFF_LEVL_FW_32K BIT(5) // FW in 32k ++#define RT_RF_PS_LEVEL_ALWAYS_ASPM BIT(6) // Always enable ASPM and Clock Req in initialization. ++#define RT_RF_LPS_DISALBE_2R BIT(30) // When LPS is on, disable 2R if no packet is received or transmittd. ++#define RT_RF_LPS_LEVEL_ASPM BIT(31) // LPS with ASPM ++ ++#define RT_IN_PS_LEVEL(ppsc, _PS_FLAG) ((ppsc->cur_ps_level & _PS_FLAG) ? _TRUE : _FALSE) ++#define RT_CLEAR_PS_LEVEL(ppsc, _PS_FLAG) (ppsc->cur_ps_level &= (~(_PS_FLAG))) ++#define RT_SET_PS_LEVEL(ppsc, _PS_FLAG) (ppsc->cur_ps_level |= _PS_FLAG) ++ ++ ++enum _PS_BBRegBackup_ { ++ PSBBREG_RF0 = 0, ++ PSBBREG_RF1, ++ PSBBREG_RF2, ++ PSBBREG_AFE0, ++ PSBBREG_TOTALCNT ++}; ++ ++enum { // for ips_mode ++ IPS_NORMAL = 0, ++ IPS_LEVEL_2, ++ IPS_NONE, ++}; ++ ++struct pwrctrl_priv { ++ _pwrlock lock; ++ volatile u8 rpwm; // requested power state for fw ++ volatile u8 cpwm; // fw current power state. updated when 1. read from HCPWM 2. driver lowers power level ++ volatile u8 tog; // toggling ++ volatile u8 cpwm_tog; // toggling ++ u8 pwr_mode; ++ u8 smart_ps; ++ uint alives; ++ ++ u8 b_hw_radio_off; ++ u8 reg_rfoff; ++ u8 reg_pdnmode; //powerdown mode ++ u32 rfoff_reason; ++ ++ //RF OFF Level ++ u32 cur_ps_level; ++ u32 reg_rfps_level; ++ ++ ++ ++#ifdef CONFIG_PCI_HCI ++ //just for PCIE ASPM ++ u8 b_support_aspm; // If it supports ASPM, Offset[560h] = 0x40, otherwise Offset[560h] = 0x00. ++ u8 b_support_backdoor; ++ ++ //just for PCIE ASPM ++ u8 const_amdpci_aspm; ++#endif ++ ++ //u8 ips_enable;//for dbg ++ //u8 lps_enable;//for dbg ++ ++ uint ips_enter_cnts; ++ uint ips_leave_cnts; ++ ++ _timer ips_check_timer; ++ ++ u8 ips_mode; ++ u8 ips_mode_req; // used to accept the mode setting request, will update to ipsmode later ++ ++ u8 bLeisurePs; ++ u8 LpsIdleCount; ++ u8 power_mgnt; ++ u8 bFwCurrentInPSMode; ++ u32 DelayLPSLastTimeStamp; ++ ++ s32 pnp_current_pwr_state; ++ u8 pnp_bstop_trx; ++ ++ ++ u8 bInternalAutoSuspend; ++ u8 bInSuspend; ++ u8 bSupportRemoteWakeup; ++ u8 wowlan_mode; ++ u8 wowlan_pattern; ++ u8 wowlan_magic; ++ u8 wowlan_unicast; ++ u8 wowlan_pattern_idx; ++ u32 wowlan_pattern_context[8][5]; ++ _timer pwr_state_check_timer; ++ int pwr_state_check_interval; ++ u8 pwr_state_check_cnts; ++ uint bips_processing; ++ ++ int ps_flag; ++ ++ rt_rf_power_state rf_pwrstate;//cur power state ++ //rt_rf_power_state current_rfpwrstate; ++ rt_rf_power_state change_rfpwrstate; ++ ++ u8 wepkeymask; ++ u8 bHWPowerdown;//if support hw power down ++ u8 bHWPwrPindetect; ++ u8 bkeepfwalive; ++ u8 brfoffbyhw; ++ unsigned long PS_BBRegBackup[PSBBREG_TOTALCNT]; ++ ++ #ifdef CONFIG_RESUME_IN_WORKQUEUE ++ struct workqueue_struct *rtw_workqueue; ++ _workitem resume_work; ++ #endif ++ ++ #ifdef CONFIG_HAS_EARLYSUSPEND ++ struct early_suspend early_suspend; ++ u8 do_late_resume; ++ #endif //CONFIG_HAS_EARLYSUSPEND ++ ++ #ifdef CONFIG_ANDROID_POWER ++ android_early_suspend_t early_suspend; ++ u8 do_late_resume; ++ #endif ++ ++ #ifdef CONFIG_INTEL_PROXIM ++ u8 stored_power_mgnt; ++ #endif ++}; ++ ++#define rtw_get_ips_mode_req(pwrctrlpriv) \ ++ (pwrctrlpriv)->ips_mode_req ++ ++#define rtw_ips_mode_req(pwrctrlpriv, ips_mode) \ ++ (pwrctrlpriv)->ips_mode_req = (ips_mode) ++ ++#define _rtw_set_pwr_state_check_timer(pwrctrlpriv, ms) \ ++ do { \ ++ /*DBG_871X("%s _rtw_set_pwr_state_check_timer(%p, %d)\n", __FUNCTION__, (pwrctrlpriv), (ms));*/ \ ++ _set_timer(&(pwrctrlpriv)->pwr_state_check_timer, (ms)); \ ++ } while(0) ++ ++#define rtw_set_pwr_state_check_timer(pwrctrlpriv) \ ++ _rtw_set_pwr_state_check_timer((pwrctrlpriv), (pwrctrlpriv)->pwr_state_check_interval) ++ ++extern void rtw_init_pwrctrl_priv(_adapter *adapter); ++extern void rtw_free_pwrctrl_priv(_adapter * adapter); ++extern sint rtw_register_tx_alive(_adapter *padapter); ++extern void rtw_unregister_tx_alive(_adapter *padapter); ++extern sint rtw_register_rx_alive(_adapter *padapter); ++extern void rtw_unregister_rx_alive(_adapter *padapter); ++extern sint rtw_register_cmd_alive(_adapter *padapter); ++extern void rtw_unregister_cmd_alive(_adapter *padapter); ++extern sint rtw_register_evt_alive(_adapter *padapter); ++extern void rtw_unregister_evt_alive(_adapter *padapter); ++extern void cpwm_int_hdl(_adapter *padapter, struct reportpwrstate_parm *preportpwrstate); ++extern void rtw_set_ps_mode(_adapter * padapter, u8 ps_mode, u8 smart_ps); ++extern void rtw_set_rpwm(_adapter * padapter, u8 val8); ++extern void LeaveAllPowerSaveMode(PADAPTER Adapter); ++#ifdef CONFIG_IPS ++void ips_enter(_adapter * padapter); ++int ips_leave(_adapter * padapter); ++#endif ++ ++void rtw_ps_processor(_adapter*padapter); ++ ++#ifdef CONFIG_AUTOSUSPEND ++int autoresume_enter(_adapter* padapter); ++#endif ++#ifdef SUPPORT_HW_RFOFF_DETECTED ++rt_rf_power_state RfOnOffDetect(IN PADAPTER pAdapter ); ++#endif ++ ++ ++#ifdef CONFIG_LPS ++void LPS_Enter(PADAPTER padapter); ++void LPS_Leave(PADAPTER padapter); ++#endif ++ ++#ifdef CONFIG_RESUME_IN_WORKQUEUE ++void rtw_resume_in_workqueue(struct pwrctrl_priv *pwrpriv); ++#endif //CONFIG_RESUME_IN_WORKQUEUE ++ ++#if defined(CONFIG_HAS_EARLYSUSPEND ) || defined(CONFIG_ANDROID_POWER) ++#define rtw_is_earlysuspend_registered(pwrpriv) (pwrpriv)->early_suspend.suspend ++void rtw_register_early_suspend(struct pwrctrl_priv *pwrpriv); ++void rtw_unregister_early_suspend(struct pwrctrl_priv *pwrpriv); ++#endif //CONFIG_HAS_EARLYSUSPEND || CONFIG_ANDROID_POWER ++ ++u8 rtw_interface_ps_func(_adapter *padapter,HAL_INTF_PS_FUNC efunc_id,u8* val); ++int _rtw_pwr_wakeup(_adapter *padapter, const char *caller); ++#define rtw_pwr_wakeup(adapter) _rtw_pwr_wakeup(adapter, __FUNCTION__) ++ ++#endif //__RTL871X_PWRCTRL_H_ +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/include/rtw_qos.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/include/rtw_qos.h 2013-07-26 19:36:06.000000000 +0000 +@@ -0,0 +1,41 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ++******************************************************************************/ ++ ++ ++#ifndef _RTW_QOS_H_ ++#define _RTW_QOS_H_ ++#include ++#include ++ ++ ++ ++ ++ ++ ++struct qos_priv { ++ ++ unsigned int qos_option; //bit mask option: u-apsd, s-apsd, ts, block ack... ++ ++}; ++ ++ ++#endif //_RTL871X_QOS_H_ ++ +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/include/rtw_recv.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/include/rtw_recv.h 2013-07-26 19:36:06.000000000 +0000 +@@ -0,0 +1,711 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ++******************************************************************************/ ++#ifndef _RTW_RECV_H_ ++#define _RTW_RECV_H_ ++ ++#include ++#include ++#include ++ ++ ++#define NR_RECVFRAME 256 ++ ++#define RXFRAME_ALIGN 8 ++#define RXFRAME_ALIGN_SZ (1<signal_stat_timer, (recvpriv)->signal_stat_sampling_interval) ++#endif //CONFIG_NEW_SIGNAL_STAT_PROCESS ++ ++struct sta_recv_priv { ++ ++ _lock lock; ++ sint option; ++ ++ //_queue blk_strms[MAX_RX_NUMBLKS]; ++ _queue defrag_q; //keeping the fragment frame until defrag ++ ++ struct stainfo_rxcache rxcache; ++ ++ //uint sta_rx_bytes; ++ //uint sta_rx_pkts; ++ //uint sta_rx_fail; ++ ++}; ++ ++ ++struct recv_buf{ ++ ++ _list list; ++ ++ _lock recvbuf_lock; ++ ++ u32 ref_cnt; ++ ++ _adapter *adapter; ++ ++#ifdef CONFIG_SDIO_HCI ++#ifdef PLATFORM_OS_XP ++ PMDL mdl_ptr; ++#endif ++ u8 cmd_fail; ++#endif ++ ++#ifdef CONFIG_USB_HCI ++ ++ #if defined(PLATFORM_OS_XP)||defined(PLATFORM_LINUX) ++ PURB purb; ++ dma_addr_t dma_transfer_addr; /* (in) dma addr for transfer_buffer */ ++ u32 alloc_sz; ++ #endif ++ ++ #ifdef PLATFORM_OS_XP ++ PIRP pirp; ++ #endif ++ ++ #ifdef PLATFORM_OS_CE ++ USB_TRANSFER usb_transfer_read_port; ++ #endif ++ ++ u8 irp_pending; ++ int transfer_len; ++ ++#endif ++ ++#ifdef PLATFORM_LINUX ++ _pkt *pskb; ++ u8 reuse; ++#endif ++ ++ uint len; ++ u8 *phead; ++ u8 *pdata; ++ u8 *ptail; ++ u8 *pend; ++ ++ u8 *pbuf; ++ u8 *pallocated_buf; ++ ++}; ++ ++ ++/* ++ head -----> ++ ++ data -----> ++ ++ payload ++ ++ tail -----> ++ ++ ++ end -----> ++ ++ len = (unsigned int )(tail - data); ++ ++*/ ++struct recv_frame_hdr{ ++ ++ _list list; ++ _pkt *pkt; ++ _pkt *pkt_newalloc; ++ ++ _adapter *adapter; ++ ++ u8 fragcnt; ++ ++ int frame_tag; ++ ++ struct rx_pkt_attrib attrib; ++ ++ uint len; ++ u8 *rx_head; ++ u8 *rx_data; ++ u8 *rx_tail; ++ u8 *rx_end; ++ ++ void *precvbuf; ++ ++ ++ // ++ struct sta_info *psta; ++ ++ //for A-MPDU Rx reordering buffer control ++ struct recv_reorder_ctrl *preorder_ctrl; ++ ++}; ++ ++ ++union recv_frame{ ++ ++ union{ ++ _list list; ++ struct recv_frame_hdr hdr; ++ uint mem[RECVFRAME_HDR_ALIGN>>2]; ++ }u; ++ ++ //uint mem[MAX_RXSZ>>2]; ++ ++}; ++ ++ ++extern union recv_frame *rtw_alloc_recvframe (_queue *pfree_recv_queue); //get a free recv_frame from pfree_recv_queue ++extern void rtw_init_recvframe(union recv_frame *precvframe ,struct recv_priv *precvpriv); ++extern int rtw_free_recvframe(union recv_frame *precvframe, _queue *pfree_recv_queue); ++extern union recv_frame *rtw_dequeue_recvframe (_queue *queue); ++extern int rtw_enqueue_recvframe(union recv_frame *precvframe, _queue *queue); ++extern void rtw_free_recvframe_queue(_queue *pframequeue, _queue *pfree_recv_queue); ++ ++sint rtw_enqueue_recvbuf(struct recv_buf *precvbuf, _queue *queue); ++struct recv_buf *rtw_dequeue_recvbuf (_queue *queue); ++ ++void rtw_reordering_ctrl_timeout_handler(void *pcontext); ++ ++__inline static u8 *get_rxmem(union recv_frame *precvframe) ++{ ++ //always return rx_head... ++ if(precvframe==NULL) ++ return NULL; ++ ++ return precvframe->u.hdr.rx_head; ++} ++ ++__inline static u8 *get_rx_status(union recv_frame *precvframe) ++{ ++ ++ return get_rxmem(precvframe); ++ ++} ++ ++__inline static u8 *get_recvframe_data(union recv_frame *precvframe) ++{ ++ ++ //alwasy return rx_data ++ if(precvframe==NULL) ++ return NULL; ++ ++ return precvframe->u.hdr.rx_data; ++ ++} ++ ++__inline static u8 *recvframe_push(union recv_frame *precvframe, sint sz) ++{ ++ // append data before rx_data ++ ++ /* add data to the start of recv_frame ++ * ++ * This function extends the used data area of the recv_frame at the buffer ++ * start. rx_data must be still larger than rx_head, after pushing. ++ */ ++ ++ if(precvframe==NULL) ++ return NULL; ++ ++ ++ precvframe->u.hdr.rx_data -= sz ; ++ if( precvframe->u.hdr.rx_data < precvframe->u.hdr.rx_head ) ++ { ++ precvframe->u.hdr.rx_data += sz ; ++ return NULL; ++ } ++ ++ precvframe->u.hdr.len +=sz; ++ ++ return precvframe->u.hdr.rx_data; ++ ++} ++ ++ ++__inline static u8 *recvframe_pull(union recv_frame *precvframe, sint sz) ++{ ++ // rx_data += sz; move rx_data sz bytes hereafter ++ ++ //used for extract sz bytes from rx_data, update rx_data and return the updated rx_data to the caller ++ ++ ++ if(precvframe==NULL) ++ return NULL; ++ ++ ++ precvframe->u.hdr.rx_data += sz; ++ ++ if(precvframe->u.hdr.rx_data > precvframe->u.hdr.rx_tail) ++ { ++ precvframe->u.hdr.rx_data -= sz; ++ return NULL; ++ } ++ ++ precvframe->u.hdr.len -=sz; ++ ++ return precvframe->u.hdr.rx_data; ++ ++} ++ ++__inline static u8 *recvframe_put(union recv_frame *precvframe, sint sz) ++{ ++ // rx_tai += sz; move rx_tail sz bytes hereafter ++ ++ //used for append sz bytes from ptr to rx_tail, update rx_tail and return the updated rx_tail to the caller ++ //after putting, rx_tail must be still larger than rx_end. ++ unsigned char * prev_rx_tail; ++ ++ if(precvframe==NULL) ++ return NULL; ++ ++ prev_rx_tail = precvframe->u.hdr.rx_tail; ++ ++ precvframe->u.hdr.rx_tail += sz; ++ ++ if(precvframe->u.hdr.rx_tail > precvframe->u.hdr.rx_end) ++ { ++ precvframe->u.hdr.rx_tail -= sz; ++ return NULL; ++ } ++ ++ precvframe->u.hdr.len +=sz; ++ ++ return precvframe->u.hdr.rx_tail; ++ ++} ++ ++ ++ ++__inline static u8 *recvframe_pull_tail(union recv_frame *precvframe, sint sz) ++{ ++ // rmv data from rx_tail (by yitsen) ++ ++ //used for extract sz bytes from rx_end, update rx_end and return the updated rx_end to the caller ++ //after pulling, rx_end must be still larger than rx_data. ++ ++ if(precvframe==NULL) ++ return NULL; ++ ++ precvframe->u.hdr.rx_tail -= sz; ++ ++ if(precvframe->u.hdr.rx_tail < precvframe->u.hdr.rx_data) ++ { ++ precvframe->u.hdr.rx_tail += sz; ++ return NULL; ++ } ++ ++ precvframe->u.hdr.len -=sz; ++ ++ return precvframe->u.hdr.rx_tail; ++ ++} ++ ++ ++ ++__inline static _buffer * get_rxbuf_desc(union recv_frame *precvframe) ++{ ++ _buffer * buf_desc; ++ ++ if(precvframe==NULL) ++ return NULL; ++#ifdef PLATFORM_WINDOWS ++ NdisQueryPacket(precvframe->u.hdr.pkt, NULL, NULL, &buf_desc, NULL); ++#endif ++ ++ return buf_desc; ++} ++ ++ ++__inline static union recv_frame *rxmem_to_recvframe(u8 *rxmem) ++{ ++ //due to the design of 2048 bytes alignment of recv_frame, we can reference the union recv_frame ++ //from any given member of recv_frame. ++ // rxmem indicates the any member/address in recv_frame ++ ++ return (union recv_frame*)(((uint)rxmem>>RXFRAME_ALIGN) <u.hdr.rx_head; ++ ++} ++ ++__inline static u8 *pkt_to_recvdata(_pkt *pkt) ++{ ++ // return the rx_data ++ ++ union recv_frame * precv_frame =pkt_to_recvframe(pkt); ++ ++ return precv_frame->u.hdr.rx_data; ++ ++} ++ ++ ++__inline static sint get_recvframe_len(union recv_frame *precvframe) ++{ ++ return precvframe->u.hdr.len; ++} ++ ++__inline static u8 query_rx_pwr_percentage(s8 antpower ) ++{ ++ if ((antpower <= -100) || (antpower >= 20)) ++ { ++ return 0; ++ } ++ else if (antpower >= 0) ++ { ++ return 100; ++ } ++ else ++ { ++ return (100+antpower); ++ } ++} ++__inline static s32 translate_percentage_to_dbm(u32 SignalStrengthIndex) ++{ ++ s32 SignalPower; // in dBm. ++ ++ // Translate to dBm (x=0.5y-95). ++ SignalPower = (s32)((SignalStrengthIndex + 1) >> 1); ++ SignalPower -= 95; ++ ++ return SignalPower; ++} ++ ++ ++struct sta_info; ++ ++extern void _rtw_init_sta_recv_priv(struct sta_recv_priv *psta_recvpriv); ++ ++extern void mgt_dispatcher(_adapter *padapter, union recv_frame *precv_frame); ++ ++#endif ++ +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/include/rtw_rf.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/include/rtw_rf.h 2013-07-26 19:36:06.000000000 +0000 +@@ -0,0 +1,152 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++******************************************************************************/ ++#ifndef __RTW_RF_H_ ++#define __RTW_RF_H_ ++ ++#include ++#include ++ ++#define OFDM_PHY 1 ++#define MIXED_PHY 2 ++#define CCK_PHY 3 ++ ++#define NumRates (13) ++ ++// slot time for 11g ++#define SHORT_SLOT_TIME 9 ++#define NON_SHORT_SLOT_TIME 20 ++ ++#define RTL8711_RF_MAX_SENS 6 ++#define RTL8711_RF_DEF_SENS 4 ++ ++// ++// We now define the following channels as the max channels in each channel plan. ++// 2G, total 14 chnls ++// {1,2,3,4,5,6,7,8,9,10,11,12,13,14} ++// 5G, total 24 chnls ++// {36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,128,132,136,140,149,153,157,161,165} ++#define MAX_CHANNEL_NUM_2G 14 ++#define MAX_CHANNEL_NUM_5G 24 ++#define MAX_CHANNEL_NUM 38//14+24 ++ ++//#define NUM_REGULATORYS 21 ++#define NUM_REGULATORYS 1 ++ ++//Country codes ++#define USA 0x555320 ++#define EUROPE 0x1 //temp, should be provided later ++#define JAPAN 0x2 //temp, should be provided later ++ ++struct regulatory_class { ++ u32 starting_freq; //MHz, ++ u8 channel_set[MAX_CHANNEL_NUM]; ++ u8 channel_cck_power[MAX_CHANNEL_NUM];//dbm ++ u8 channel_ofdm_power[MAX_CHANNEL_NUM];//dbm ++ u8 txpower_limit; //dbm ++ u8 channel_spacing; //MHz ++ u8 modem; ++}; ++ ++typedef enum _CAPABILITY{ ++ cESS = 0x0001, ++ cIBSS = 0x0002, ++ cPollable = 0x0004, ++ cPollReq = 0x0008, ++ cPrivacy = 0x0010, ++ cShortPreamble = 0x0020, ++ cPBCC = 0x0040, ++ cChannelAgility = 0x0080, ++ cSpectrumMgnt = 0x0100, ++ cQos = 0x0200, // For HCCA, use with CF-Pollable and CF-PollReq ++ cShortSlotTime = 0x0400, ++ cAPSD = 0x0800, ++ cRM = 0x1000, // RRM (Radio Request Measurement) ++ cDSSS_OFDM = 0x2000, ++ cDelayedBA = 0x4000, ++ cImmediateBA = 0x8000, ++}CAPABILITY, *PCAPABILITY; ++ ++enum _REG_PREAMBLE_MODE{ ++ PREAMBLE_LONG = 1, ++ PREAMBLE_AUTO = 2, ++ PREAMBLE_SHORT = 3, ++}; ++ ++ ++enum _RTL8712_RF_MIMO_CONFIG_{ ++ RTL8712_RFCONFIG_1T=0x10, ++ RTL8712_RFCONFIG_2T=0x20, ++ RTL8712_RFCONFIG_1R=0x01, ++ RTL8712_RFCONFIG_2R=0x02, ++ RTL8712_RFCONFIG_1T1R=0x11, ++ RTL8712_RFCONFIG_1T2R=0x12, ++ RTL8712_RFCONFIG_TURBO=0x92, ++ RTL8712_RFCONFIG_2T2R=0x22 ++}; ++ ++ ++// Bandwidth Offset ++#define HAL_PRIME_CHNL_OFFSET_DONT_CARE 0 ++#define HAL_PRIME_CHNL_OFFSET_LOWER 1 ++#define HAL_PRIME_CHNL_OFFSET_UPPER 2 ++ ++// Represent Channel Width in HT Capabilities ++// ++typedef enum _HT_CHANNEL_WIDTH { ++ HT_CHANNEL_WIDTH_20 = 0, ++ HT_CHANNEL_WIDTH_40 = 1, ++}HT_CHANNEL_WIDTH, *PHT_CHANNEL_WIDTH; ++ ++// ++// Represent Extention Channel Offset in HT Capabilities ++// This is available only in 40Mhz mode. ++// ++typedef enum _HT_EXTCHNL_OFFSET{ ++ HT_EXTCHNL_OFFSET_NO_EXT = 0, ++ HT_EXTCHNL_OFFSET_UPPER = 1, ++ HT_EXTCHNL_OFFSET_NO_DEF = 2, ++ HT_EXTCHNL_OFFSET_LOWER = 3, ++}HT_EXTCHNL_OFFSET, *PHT_EXTCHNL_OFFSET; ++ ++/* 2007/11/15 MH Define different RF type. */ ++typedef enum _RT_RF_TYPE_DEFINITION ++{ ++ RF_1T2R = 0, ++ RF_2T4R = 1, ++ RF_2T2R = 2, ++ RF_1T1R = 3, ++ RF_2T2R_GREEN = 4, ++ RF_819X_MAX_TYPE = 5, ++}RT_RF_TYPE_DEF_E; ++ ++typedef enum _RF_RADIO_PATH{ ++ RF_PATH_A = 0, //Radio Path A ++ RF_PATH_B = 1, //Radio Path B ++ RF_PATH_C = 2, //Radio Path C ++ RF_PATH_D = 3, //Radio Path D ++ //RF_PATH_MAX //Max RF number 90 support ++}RF_RADIO_PATH_E, *PRF_RADIO_PATH_E; ++ ++u32 rtw_ch2freq(u32 ch); ++u32 rtw_freq2ch(u32 freq); ++ ++ ++#endif //_RTL8711_RF_H_ ++ +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/include/rtw_security.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/include/rtw_security.h 2013-07-26 19:36:06.000000000 +0000 +@@ -0,0 +1,423 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ++******************************************************************************/ ++#ifndef __RTW_SECURITY_H_ ++#define __RTW_SECURITY_H_ ++ ++ ++#include ++#include ++#include ++ ++ ++#define _NO_PRIVACY_ 0x0 ++#define _WEP40_ 0x1 ++#define _TKIP_ 0x2 ++#define _TKIP_WTMIC_ 0x3 ++#define _AES_ 0x4 ++#define _WEP104_ 0x5 ++ ++#define _WPA_IE_ID_ 0xdd ++#define _WPA2_IE_ID_ 0x30 ++ ++#define SHA256_MAC_LEN 32 ++#define AES_BLOCK_SIZE 16 ++#define AES_PRIV_SIZE (4 * 44) ++ ++#ifndef Ndis802_11AuthModeWPA2 ++#define Ndis802_11AuthModeWPA2 (Ndis802_11AuthModeWPANone + 1) ++#endif ++ ++#ifndef Ndis802_11AuthModeWPA2PSK ++#define Ndis802_11AuthModeWPA2PSK (Ndis802_11AuthModeWPANone + 2) ++#endif ++ ++union pn48 { ++ ++ u64 val; ++ ++#ifdef CONFIG_LITTLE_ENDIAN ++ ++struct { ++ u8 TSC0; ++ u8 TSC1; ++ u8 TSC2; ++ u8 TSC3; ++ u8 TSC4; ++ u8 TSC5; ++ u8 TSC6; ++ u8 TSC7; ++} _byte_; ++ ++#elif defined(CONFIG_BIG_ENDIAN) ++ ++struct { ++ u8 TSC7; ++ u8 TSC6; ++ u8 TSC5; ++ u8 TSC4; ++ u8 TSC3; ++ u8 TSC2; ++ u8 TSC1; ++ u8 TSC0; ++} _byte_; ++ ++#endif ++ ++}; ++ ++union Keytype { ++ u8 skey[16]; ++ u32 lkey[4]; ++}; ++ ++ ++typedef struct _RT_PMKID_LIST ++{ ++ u8 bUsed; ++ u8 Bssid[6]; ++ u8 PMKID[16]; ++ u8 SsidBuf[33]; ++ u8* ssid_octet; ++ u16 ssid_length; ++} RT_PMKID_LIST, *PRT_PMKID_LIST; ++ ++ ++struct security_priv ++{ ++ u32 dot11AuthAlgrthm; // 802.11 auth, could be open, shared, 8021x and authswitch ++ u32 dot11PrivacyAlgrthm; // This specify the privacy for shared auth. algorithm. ++ ++ /* WEP */ ++ u32 dot11PrivacyKeyIndex; // this is only valid for legendary wep, 0~3 for key id. (tx key index) ++ union Keytype dot11DefKey[4]; // this is only valid for def. key ++ u32 dot11DefKeylen[4]; ++ ++ u32 dot118021XGrpPrivacy; // This specify the privacy algthm. used for Grp key ++ u32 dot118021XGrpKeyid; // key id used for Grp Key ( tx key index) ++ union Keytype dot118021XGrpKey[4]; // 802.1x Group Key, for inx0 and inx1 ++ union Keytype dot118021XGrptxmickey[4]; ++ union Keytype dot118021XGrprxmickey[4]; ++ union pn48 dot11Grptxpn; // PN48 used for Grp Key xmit. ++ union pn48 dot11Grprxpn; // PN48 used for Grp Key recv. ++ ++#ifdef CONFIG_AP_MODE ++ //extend security capabilities for AP_MODE ++ unsigned int dot8021xalg;//0:disable, 1:psk, 2:802.1x ++ unsigned int wpa_psk;//0:disable, bit(0): WPA, bit(1):WPA2 ++ unsigned int wpa_group_cipher; ++ unsigned int wpa2_group_cipher; ++ unsigned int wpa_pairwise_cipher; ++ unsigned int wpa2_pairwise_cipher; ++#endif ++ ++ u8 wps_phase;//for wps ++ u8 wps_ie[MAX_WPS_IE_LEN];//added in assoc req ++ int wps_ie_len; ++ ++ ++ u8 binstallGrpkey; ++ u8 busetkipkey; ++ //_timer tkip_timer; ++ u8 bcheck_grpkey; ++ u8 bgrpkey_handshake; ++ ++ //u8 packet_cnt;//unused, removed ++ ++ s32 sw_encrypt;//from registry_priv ++ s32 sw_decrypt;//from registry_priv ++ ++ s32 hw_decrypted;//if the rx packets is hw_decrypted==_FALSE, it means the hw has not been ready. ++ ++ ++ //keeps the auth_type & enc_status from upper layer ioctl(wpa_supplicant or wzc) ++ u32 ndisauthtype; // NDIS_802_11_AUTHENTICATION_MODE ++ u32 ndisencryptstatus; // NDIS_802_11_ENCRYPTION_STATUS ++ ++ WLAN_BSSID_EX sec_bss; //for joinbss (h2c buffer) usage ++ ++ NDIS_802_11_WEP ndiswep; ++#ifdef PLATFORM_WINDOWS ++ u8 KeyMaterial[16];// variable length depending on above field. ++#endif ++ ++ u8 assoc_info[600]; ++ u8 szofcapability[256]; //for wpa2 usage ++ u8 oidassociation[512]; //for wpa/wpa2 usage ++ u8 authenticator_ie[256]; //store ap security information element ++ u8 supplicant_ie[256]; //store sta security information element ++ ++ ++ //for tkip countermeasure ++ u32 last_mic_err_time; ++ u8 btkip_countermeasure; ++ u8 btkip_wait_report; ++ u32 btkip_countermeasure_time; ++ ++ //--------------------------------------------------------------------------- ++ // For WPA2 Pre-Authentication. ++ //--------------------------------------------------------------------------- ++ //u8 RegEnablePreAuth; // Default value: Pre-Authentication enabled or not, from registry "EnablePreAuth". Added by Annie, 2005-11-01. ++ //u8 EnablePreAuthentication; // Current Value: Pre-Authentication enabled or not. ++ RT_PMKID_LIST PMKIDList[NUM_PMKID_CACHE]; // Renamed from PreAuthKey[NUM_PRE_AUTH_KEY]. Annie, 2006-10-13. ++ u8 PMKIDIndex; ++ //u32 PMKIDCount; // Added by Annie, 2006-10-13. ++ //u8 szCapability[256]; // For WPA2-PSK using zero-config, by Annie, 2005-09-20. ++ ++}; ++ ++struct sha256_state { ++ u64 length; ++ u32 state[8], curlen; ++ u8 buf[64]; ++}; ++ ++#define GET_ENCRY_ALGO(psecuritypriv, psta, encry_algo, bmcst)\ ++do{\ ++ switch(psecuritypriv->dot11AuthAlgrthm)\ ++ {\ ++ case dot11AuthAlgrthm_Open:\ ++ case dot11AuthAlgrthm_Shared:\ ++ case dot11AuthAlgrthm_Auto:\ ++ encry_algo = (u8)psecuritypriv->dot11PrivacyAlgrthm;\ ++ break;\ ++ case dot11AuthAlgrthm_8021X:\ ++ if(bmcst)\ ++ encry_algo = (u8)psecuritypriv->dot118021XGrpPrivacy;\ ++ else\ ++ encry_algo =(u8) psta->dot118021XPrivacy;\ ++ break;\ ++ }\ ++}while(0) ++ ++ ++#define SET_ICE_IV_LEN( iv_len, icv_len, encrypt)\ ++do{\ ++ switch(encrypt)\ ++ {\ ++ case _WEP40_:\ ++ case _WEP104_:\ ++ iv_len = 4;\ ++ icv_len = 4;\ ++ break;\ ++ case _TKIP_:\ ++ iv_len = 8;\ ++ icv_len = 4;\ ++ break;\ ++ case _AES_:\ ++ iv_len = 8;\ ++ icv_len = 8;\ ++ break;\ ++ default:\ ++ iv_len = 0;\ ++ icv_len = 0;\ ++ break;\ ++ }\ ++}while(0) ++ ++ ++#define GET_TKIP_PN(iv,dot11txpn)\ ++do{\ ++ dot11txpn._byte_.TSC0=iv[2];\ ++ dot11txpn._byte_.TSC1=iv[0];\ ++ dot11txpn._byte_.TSC2=iv[4];\ ++ dot11txpn._byte_.TSC3=iv[5];\ ++ dot11txpn._byte_.TSC4=iv[6];\ ++ dot11txpn._byte_.TSC5=iv[7];\ ++}while(0) ++ ++ ++#define ROL32( A, n ) ( ((A) << (n)) | ( ((A)>>(32-(n))) & ( (1UL << (n)) - 1 ) ) ) ++#define ROR32( A, n ) ROL32( (A), 32-(n) ) ++ ++struct mic_data ++{ ++ u32 K0, K1; // Key ++ u32 L, R; // Current state ++ u32 M; // Message accumulator (single word) ++ u32 nBytesInM; // # bytes in M ++}; ++ ++extern const u32 Te0[256]; ++extern const u32 Te1[256]; ++extern const u32 Te2[256]; ++extern const u32 Te3[256]; ++extern const u32 Te4[256]; ++extern const u32 Td0[256]; ++extern const u32 Td1[256]; ++extern const u32 Td2[256]; ++extern const u32 Td3[256]; ++extern const u32 Td4[256]; ++extern const u32 rcon[10]; ++extern const u8 Td4s[256]; ++extern const u8 rcons[10]; ++ ++#define RCON(i) (rcons[(i)] << 24) ++ ++static inline u32 rotr(u32 val, int bits) ++{ ++ return (val >> bits) | (val << (32 - bits)); ++} ++ ++#define TE0(i) Te0[((i) >> 24) & 0xff] ++#define TE1(i) rotr(Te0[((i) >> 16) & 0xff], 8) ++#define TE2(i) rotr(Te0[((i) >> 8) & 0xff], 16) ++#define TE3(i) rotr(Te0[(i) & 0xff], 24) ++#define TE41(i) ((Te0[((i) >> 24) & 0xff] << 8) & 0xff000000) ++#define TE42(i) (Te0[((i) >> 16) & 0xff] & 0x00ff0000) ++#define TE43(i) (Te0[((i) >> 8) & 0xff] & 0x0000ff00) ++#define TE44(i) ((Te0[(i) & 0xff] >> 8) & 0x000000ff) ++#define TE421(i) ((Te0[((i) >> 16) & 0xff] << 8) & 0xff000000) ++#define TE432(i) (Te0[((i) >> 8) & 0xff] & 0x00ff0000) ++#define TE443(i) (Te0[(i) & 0xff] & 0x0000ff00) ++#define TE414(i) ((Te0[((i) >> 24) & 0xff] >> 8) & 0x000000ff) ++#define TE4(i) ((Te0[(i)] >> 8) & 0x000000ff) ++ ++#define TD0(i) Td0[((i) >> 24) & 0xff] ++#define TD1(i) rotr(Td0[((i) >> 16) & 0xff], 8) ++#define TD2(i) rotr(Td0[((i) >> 8) & 0xff], 16) ++#define TD3(i) rotr(Td0[(i) & 0xff], 24) ++#define TD41(i) (Td4s[((i) >> 24) & 0xff] << 24) ++#define TD42(i) (Td4s[((i) >> 16) & 0xff] << 16) ++#define TD43(i) (Td4s[((i) >> 8) & 0xff] << 8) ++#define TD44(i) (Td4s[(i) & 0xff]) ++#define TD0_(i) Td0[(i) & 0xff] ++#define TD1_(i) rotr(Td0[(i) & 0xff], 8) ++#define TD2_(i) rotr(Td0[(i) & 0xff], 16) ++#define TD3_(i) rotr(Td0[(i) & 0xff], 24) ++ ++#define GETU32(pt) (((u32)(pt)[0] << 24) ^ ((u32)(pt)[1] << 16) ^ \ ++ ((u32)(pt)[2] << 8) ^ ((u32)(pt)[3])) ++ ++#define PUTU32(ct, st) { \ ++(ct)[0] = (u8)((st) >> 24); (ct)[1] = (u8)((st) >> 16); \ ++(ct)[2] = (u8)((st) >> 8); (ct)[3] = (u8)(st); } ++ ++#define WPA_GET_BE32(a) ((((u32) (a)[0]) << 24) | (((u32) (a)[1]) << 16) | \ ++ (((u32) (a)[2]) << 8) | ((u32) (a)[3])) ++ ++#define WPA_PUT_LE16(a, val) \ ++ do { \ ++ (a)[1] = ((u16) (val)) >> 8; \ ++ (a)[0] = ((u16) (val)) & 0xff; \ ++ } while (0) ++ ++#define WPA_PUT_BE32(a, val) \ ++ do { \ ++ (a)[0] = (u8) ((((u32) (val)) >> 24) & 0xff); \ ++ (a)[1] = (u8) ((((u32) (val)) >> 16) & 0xff); \ ++ (a)[2] = (u8) ((((u32) (val)) >> 8) & 0xff); \ ++ (a)[3] = (u8) (((u32) (val)) & 0xff); \ ++ } while (0) ++ ++#define WPA_PUT_BE64(a, val) \ ++ do { \ ++ (a)[0] = (u8) (((u64) (val)) >> 56); \ ++ (a)[1] = (u8) (((u64) (val)) >> 48); \ ++ (a)[2] = (u8) (((u64) (val)) >> 40); \ ++ (a)[3] = (u8) (((u64) (val)) >> 32); \ ++ (a)[4] = (u8) (((u64) (val)) >> 24); \ ++ (a)[5] = (u8) (((u64) (val)) >> 16); \ ++ (a)[6] = (u8) (((u64) (val)) >> 8); \ ++ (a)[7] = (u8) (((u64) (val)) & 0xff); \ ++ } while (0) ++ ++/* ===== start - public domain SHA256 implementation ===== */ ++ ++/* This is based on SHA256 implementation in LibTomCrypt that was released into ++ * public domain by Tom St Denis. */ ++ ++/* the K array */ ++static const unsigned long K[64] = { ++ 0x428a2f98UL, 0x71374491UL, 0xb5c0fbcfUL, 0xe9b5dba5UL, 0x3956c25bUL, ++ 0x59f111f1UL, 0x923f82a4UL, 0xab1c5ed5UL, 0xd807aa98UL, 0x12835b01UL, ++ 0x243185beUL, 0x550c7dc3UL, 0x72be5d74UL, 0x80deb1feUL, 0x9bdc06a7UL, ++ 0xc19bf174UL, 0xe49b69c1UL, 0xefbe4786UL, 0x0fc19dc6UL, 0x240ca1ccUL, ++ 0x2de92c6fUL, 0x4a7484aaUL, 0x5cb0a9dcUL, 0x76f988daUL, 0x983e5152UL, ++ 0xa831c66dUL, 0xb00327c8UL, 0xbf597fc7UL, 0xc6e00bf3UL, 0xd5a79147UL, ++ 0x06ca6351UL, 0x14292967UL, 0x27b70a85UL, 0x2e1b2138UL, 0x4d2c6dfcUL, ++ 0x53380d13UL, 0x650a7354UL, 0x766a0abbUL, 0x81c2c92eUL, 0x92722c85UL, ++ 0xa2bfe8a1UL, 0xa81a664bUL, 0xc24b8b70UL, 0xc76c51a3UL, 0xd192e819UL, ++ 0xd6990624UL, 0xf40e3585UL, 0x106aa070UL, 0x19a4c116UL, 0x1e376c08UL, ++ 0x2748774cUL, 0x34b0bcb5UL, 0x391c0cb3UL, 0x4ed8aa4aUL, 0x5b9cca4fUL, ++ 0x682e6ff3UL, 0x748f82eeUL, 0x78a5636fUL, 0x84c87814UL, 0x8cc70208UL, ++ 0x90befffaUL, 0xa4506cebUL, 0xbef9a3f7UL, 0xc67178f2UL ++}; ++ ++ ++/* Various logical functions */ ++#define RORc(x, y) \ ++( ((((unsigned long) (x) & 0xFFFFFFFFUL) >> (unsigned long) ((y) & 31)) | \ ++ ((unsigned long) (x) << (unsigned long) (32 - ((y) & 31)))) & 0xFFFFFFFFUL) ++#define Ch(x,y,z) (z ^ (x & (y ^ z))) ++#define Maj(x,y,z) (((x | y) & z) | (x & y)) ++#define S(x, n) RORc((x), (n)) ++#define R(x, n) (((x)&0xFFFFFFFFUL)>>(n)) ++#define Sigma0(x) (S(x, 2) ^ S(x, 13) ^ S(x, 22)) ++#define Sigma1(x) (S(x, 6) ^ S(x, 11) ^ S(x, 25)) ++#define Gamma0(x) (S(x, 7) ^ S(x, 18) ^ R(x, 3)) ++#define Gamma1(x) (S(x, 17) ^ S(x, 19) ^ R(x, 10)) ++#ifndef MIN ++#define MIN(x, y) (((x) < (y)) ? (x) : (y)) ++#endif ++ ++void rtw_secmicsetkey(struct mic_data *pmicdata, u8 * key ); ++void rtw_secmicappendbyte(struct mic_data *pmicdata, u8 b ); ++void rtw_secmicappend(struct mic_data *pmicdata, u8 * src, u32 nBytes ); ++void rtw_secgetmic(struct mic_data *pmicdata, u8 * dst ); ++ ++void rtw_seccalctkipmic( ++ u8 * key, ++ u8 *header, ++ u8 *data, ++ u32 data_len, ++ u8 *Miccode, ++ u8 priority); ++ ++u32 rtw_aes_encrypt(_adapter *padapter, u8 *pxmitframe); ++u32 rtw_tkip_encrypt(_adapter *padapter, u8 *pxmitframe); ++void rtw_wep_encrypt(_adapter *padapter, u8 *pxmitframe); ++ ++u32 rtw_aes_decrypt(_adapter *padapter, u8 *precvframe); ++u32 rtw_tkip_decrypt(_adapter *padapter, u8 *precvframe); ++void rtw_wep_decrypt(_adapter *padapter, u8 *precvframe); ++ ++#ifdef CONFIG_TDLS ++void wpa_tdls_generate_tpk(_adapter *padapter, struct sta_info *psta); ++int wpa_tdls_ftie_mic(u8 *kck, u8 trans_seq, ++ u8 *lnkid, u8 *rsnie, u8 *timeoutie, u8 *ftie, ++ u8 *mic); ++int tdls_verify_mic(u8 *kck, u8 trans_seq, ++ u8 *lnkid, u8 *rsnie, u8 *timeoutie, u8 *ftie); ++#endif ++ ++#ifdef PLATFORM_WINDOWS ++void rtw_use_tkipkey_handler ( ++ IN PVOID SystemSpecific1, ++ IN PVOID FunctionContext, ++ IN PVOID SystemSpecific2, ++ IN PVOID SystemSpecific3 ++ ); ++#endif ++#ifdef PLATFORM_LINUX ++void rtw_use_tkipkey_handler(void* FunctionContext); ++#endif ++#endif //__RTL871X_SECURITY_H_ ++ +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/include/rtw_version.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/include/rtw_version.h 2013-07-26 19:36:06.000000000 +0000 +@@ -0,0 +1 @@ ++#define DRIVERVERSION "v3.4.3_4369.20120622" +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/include/rtw_xmit.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/include/rtw_xmit.h 2013-07-26 19:36:06.000000000 +0000 +@@ -0,0 +1,668 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++******************************************************************************/ ++#ifndef _RTW_XMIT_H_ ++#define _RTW_XMIT_H_ ++ ++#include ++#include ++#include ++#include ++ ++#ifdef CONFIG_SDIO_HCI ++#define MAX_XMITBUF_SZ (30720)// (2048) ++#define NR_XMITBUFF (16) ++ ++#elif defined (CONFIG_USB_HCI) ++#ifdef CONFIG_USB_TX_AGGREGATION ++#define MAX_XMITBUF_SZ 20480 // 20k ++#else ++#define MAX_XMITBUF_SZ (2048) ++#endif ++ ++#define NR_XMITBUFF (4) ++ ++#elif defined (CONFIG_PCI_HCI) ++#define MAX_XMITBUF_SZ (1664) ++#define NR_XMITBUFF (128) ++#endif ++ ++#ifdef PLATFORM_OS_CE ++#define XMITBUF_ALIGN_SZ 4 ++#else ++#ifdef CONFIG_PCI_HCI ++#define XMITBUF_ALIGN_SZ 4 ++#else ++#define XMITBUF_ALIGN_SZ 512 ++#endif ++#endif ++ ++// xmit extension buff defination ++#define MAX_XMIT_EXTBUF_SZ (2048) ++ ++#define NR_XMIT_EXTBUFF (32) ++ ++#define MAX_NUMBLKS (1) ++ ++#define XMIT_VO_QUEUE (0) ++#define XMIT_VI_QUEUE (1) ++#define XMIT_BE_QUEUE (2) ++#define XMIT_BK_QUEUE (3) ++ ++#ifdef CONFIG_PCI_HCI ++#define TXDESC_NUM 64 ++//#define TXDESC_NUM 128 ++#define TXDESC_NUM_BE_QUEUE 128 ++#endif ++ ++#define WEP_IV(pattrib_iv, dot11txpn, keyidx)\ ++do{\ ++ pattrib_iv[0] = dot11txpn._byte_.TSC0;\ ++ pattrib_iv[1] = dot11txpn._byte_.TSC1;\ ++ pattrib_iv[2] = dot11txpn._byte_.TSC2;\ ++ pattrib_iv[3] = ((keyidx & 0x3)<<6);\ ++ dot11txpn.val = (dot11txpn.val == 0xffffff) ? 0: (dot11txpn.val+1);\ ++}while(0) ++ ++ ++#define TKIP_IV(pattrib_iv, dot11txpn, keyidx)\ ++do{\ ++ pattrib_iv[0] = dot11txpn._byte_.TSC1;\ ++ pattrib_iv[1] = (dot11txpn._byte_.TSC1 | 0x20) & 0x7f;\ ++ pattrib_iv[2] = dot11txpn._byte_.TSC0;\ ++ pattrib_iv[3] = BIT(5) | ((keyidx & 0x3)<<6);\ ++ pattrib_iv[4] = dot11txpn._byte_.TSC2;\ ++ pattrib_iv[5] = dot11txpn._byte_.TSC3;\ ++ pattrib_iv[6] = dot11txpn._byte_.TSC4;\ ++ pattrib_iv[7] = dot11txpn._byte_.TSC5;\ ++ dot11txpn.val = dot11txpn.val == 0xffffffffffffULL ? 0: (dot11txpn.val+1);\ ++}while(0) ++ ++#define AES_IV(pattrib_iv, dot11txpn, keyidx)\ ++do{\ ++ pattrib_iv[0] = dot11txpn._byte_.TSC0;\ ++ pattrib_iv[1] = dot11txpn._byte_.TSC1;\ ++ pattrib_iv[2] = 0;\ ++ pattrib_iv[3] = BIT(5) | ((keyidx & 0x3)<<6);\ ++ pattrib_iv[4] = dot11txpn._byte_.TSC2;\ ++ pattrib_iv[5] = dot11txpn._byte_.TSC3;\ ++ pattrib_iv[6] = dot11txpn._byte_.TSC4;\ ++ pattrib_iv[7] = dot11txpn._byte_.TSC5;\ ++ dot11txpn.val = dot11txpn.val == 0xffffffffffffULL ? 0: (dot11txpn.val+1);\ ++}while(0) ++ ++ ++#define HWXMIT_ENTRY 4 ++ ++#define TXDESC_SIZE 32 ++#define PACKET_OFFSET_SZ (8) ++ ++#ifdef CONFIG_USB_HCI ++#define TXDESC_OFFSET (TXDESC_SIZE + PACKET_OFFSET_SZ) ++#endif ++ ++#ifdef CONFIG_PCI_HCI ++#define TXDESC_OFFSET 0 ++#define TX_DESC_NEXT_DESC_OFFSET 40 ++#endif ++ ++// ++//defined for TX DESC Operation ++// ++ ++#define MAX_TID (15) ++ ++//OFFSET 0 ++#define OFFSET_SZ 0 ++#define OFFSET_SHT 16 ++#define BMC BIT(24) ++#define LSG BIT(26) ++#define FSG BIT(27) ++#define OWN BIT(31) ++ ++//OFFSET 4 ++#define PKT_OFFSET_SZ 0 ++#define BK BIT(6) ++#define QSEL_SHT 8 ++#define Rate_ID_SHT 16 ++#define NAVUSEHDR BIT(20) ++#define PKT_OFFSET_SHT 26 ++#define HWPC BIT(31) ++ ++//OFFSET 8 ++#define AGG_EN BIT(29) ++ ++//OFFSET 12 ++#define SEQ_SHT 16 ++ ++//OFFSET 16 ++#define QoS BIT(6) ++#define HW_SEQ_EN BIT(7) ++#define USERATE BIT(8) ++#define DISDATAFB BIT(10) ++#define DATA_SHORT BIT(24) ++#define DATA_BW BIT(25) ++ ++//OFFSET 20 ++#define SGI BIT(6) ++ ++struct tx_desc{ ++ ++ //DWORD 0 ++ unsigned int txdw0; ++ ++ unsigned int txdw1; ++ ++ unsigned int txdw2; ++ ++ unsigned int txdw3; ++ ++ unsigned int txdw4; ++ ++ unsigned int txdw5; ++ ++ unsigned int txdw6; ++ ++ unsigned int txdw7; ++#ifdef CONFIG_PCI_HCI ++ unsigned int txdw8; ++ ++ unsigned int txdw9; ++ ++ unsigned int txdw10; ++ ++ unsigned int txdw11; ++ ++ // 2008/05/15 MH Because PCIE HW memory R/W 4K limit. And now, our descriptor ++ // size is 40 bytes. If you use more than 102 descriptor( 103*40>4096), HW will execute ++ // memoryR/W CRC error. And then all DMA fetch will fail. We must decrease descriptor ++ // number or enlarge descriptor size as 64 bytes. ++ unsigned int txdw12; ++ ++ unsigned int txdw13; ++ ++ unsigned int txdw14; ++ ++ unsigned int txdw15; ++#endif ++}; ++ ++ ++union txdesc { ++ struct tx_desc txdesc; ++ unsigned int value[TXDESC_SIZE>>2]; ++}; ++ ++#ifdef CONFIG_PCI_HCI ++#define PCI_MAX_TX_QUEUE_COUNT 8 ++ ++struct rtw_tx_ring { ++ struct tx_desc *desc; ++ dma_addr_t dma; ++ unsigned int idx; ++ unsigned int entries; ++ _queue queue; ++ u32 qlen; ++}; ++#endif ++ ++struct hw_xmit { ++ //_lock xmit_lock; ++ //_list pending; ++ _queue *sta_queue; ++ //struct hw_txqueue *phwtxqueue; ++ //sint txcmdcnt; ++ int accnt; ++}; ++ ++#if 0 ++struct pkt_attrib ++{ ++ u8 type; ++ u8 subtype; ++ u8 bswenc; ++ u8 dhcp_pkt; ++ u16 ether_type; ++ int pktlen; //the original 802.3 pkt raw_data len (not include ether_hdr data) ++ int pkt_hdrlen; //the original 802.3 pkt header len ++ int hdrlen; //the WLAN Header Len ++ int nr_frags; ++ int last_txcmdsz; ++ int encrypt; //when 0 indicate no encrypt. when non-zero, indicate the encrypt algorith ++ u8 iv[8]; ++ int iv_len; ++ u8 icv[8]; ++ int icv_len; ++ int priority; ++ int ack_policy; ++ int mac_id; ++ int vcs_mode; //virtual carrier sense method ++ ++ u8 dst[ETH_ALEN]; ++ u8 src[ETH_ALEN]; ++ u8 ta[ETH_ALEN]; ++ u8 ra[ETH_ALEN]; ++ ++ u8 key_idx; ++ ++ u8 qos_en; ++ u8 ht_en; ++ u8 raid;//rate adpative id ++ u8 bwmode; ++ u8 ch_offset;//PRIME_CHNL_OFFSET ++ u8 sgi;//short GI ++ u8 ampdu_en;//tx ampdu enable ++ u8 mdata;//more data bit ++ u8 eosp; ++ ++ u8 pctrl;//per packet txdesc control enable ++ u8 triggered;//for ap mode handling Power Saving sta ++ ++ u32 qsel; ++ u16 seqnum; ++ ++ struct sta_info * psta; ++#ifdef CONFIG_TCP_CSUM_OFFLOAD_TX ++ u8 hw_tcp_csum; ++#endif ++}; ++#else ++//reduce size ++struct pkt_attrib ++{ ++ u8 type; ++ u8 subtype; ++ u8 bswenc; ++ u8 dhcp_pkt; ++ u16 ether_type; ++ u16 seqnum; ++ u16 pkt_hdrlen; //the original 802.3 pkt header len ++ u16 hdrlen; //the WLAN Header Len ++ u32 pktlen; //the original 802.3 pkt raw_data len (not include ether_hdr data) ++ u32 last_txcmdsz; ++ u8 nr_frags; ++ u8 encrypt; //when 0 indicate no encrypt. when non-zero, indicate the encrypt algorith ++ u8 iv_len; ++ u8 icv_len; ++ u8 iv[8]; ++ u8 icv[8]; ++ u8 priority; ++ u8 ack_policy; ++ u8 mac_id; ++ u8 vcs_mode; //virtual carrier sense method ++ u8 dst[ETH_ALEN]; ++ u8 src[ETH_ALEN]; ++ u8 ta[ETH_ALEN]; ++ u8 ra[ETH_ALEN]; ++ u8 key_idx; ++ u8 qos_en; ++ u8 ht_en; ++ u8 raid;//rate adpative id ++ u8 bwmode; ++ u8 ch_offset;//PRIME_CHNL_OFFSET ++ u8 sgi;//short GI ++ u8 ampdu_en;//tx ampdu enable ++ u8 mdata;//more data bit ++ u8 pctrl;//per packet txdesc control enable ++ u8 triggered;//for ap mode handling Power Saving sta ++ u8 qsel; ++ u8 eosp; ++ u8 rate; ++ u8 intel_proxim; ++ u8 retry_ctrl; ++ struct sta_info * psta; ++#ifdef CONFIG_TCP_CSUM_OFFLOAD_TX ++ u8 hw_tcp_csum; ++#endif ++}; ++#endif ++ ++ ++#define WLANHDR_OFFSET 64 ++ ++#define NULL_FRAMETAG (0x0) ++#define DATA_FRAMETAG 0x01 ++#define L2_FRAMETAG 0x02 ++#define MGNT_FRAMETAG 0x03 ++#define AMSDU_FRAMETAG 0x04 ++ ++#define EII_FRAMETAG 0x05 ++#define IEEE8023_FRAMETAG 0x06 ++ ++#define MP_FRAMETAG 0x07 ++ ++#define TXAGG_FRAMETAG 0x08 ++ ++ ++struct xmit_buf ++{ ++ _list list; ++ ++ _adapter *padapter; ++ ++ u8 *pallocated_buf; ++ ++ u8 *pbuf; ++ ++ void *priv_data; ++ ++ u16 ext_tag; // 0: Normal xmitbuf, 1: extension xmitbuf. ++ u16 flags; ++ u32 alloc_sz; ++ ++#ifdef CONFIG_USB_HCI ++ ++ u32 sz[8]; ++ ++#if defined(PLATFORM_OS_XP)||defined(PLATFORM_LINUX) ++ PURB pxmit_urb[8]; ++ dma_addr_t dma_transfer_addr; /* (in) dma addr for transfer_buffer */ ++#endif ++ ++#ifdef PLATFORM_OS_XP ++ PIRP pxmit_irp[8]; ++#endif ++ ++#ifdef PLATFORM_OS_CE ++ USB_TRANSFER usb_transfer_write_port; ++#endif ++ ++#ifdef PLATFORM_LINUX ++ u8 isSync; //is this synchronous? ++ int status; // keeping urb status for synchronous call to access ++ struct completion done; // for wirte_port synchronously ++#endif ++ ++ u8 bpending[8]; ++ ++ sint last[8]; ++ ++#endif ++ ++#ifdef CONFIG_SDIO_HCI ++ u32 len; ++ u8 *phead; ++ u8 *pdata; ++ u8 *ptail; ++ u8 *pend; ++ u32 ff_hwaddr; ++#ifdef PLATFORM_OS_XP ++ PMDL pxmitbuf_mdl; ++ PIRP pxmitbuf_irp; ++ PSDBUS_REQUEST_PACKET pxmitbuf_sdrp; ++#endif ++#endif ++ ++#ifdef CONFIG_PCI_HCI ++ u32 len; ++#endif ++ ++#ifdef DBG_XMIT_BUF ++ u8 no; ++#endif ++ ++}; ++ ++struct xmit_frame ++{ ++ _list list; ++ ++ struct pkt_attrib attrib; ++ ++ _pkt *pkt; ++ ++ int frame_tag; ++ ++ _adapter *padapter; ++ ++ u8 *buf_addr; ++ ++ struct xmit_buf *pxmitbuf; ++ ++#ifdef CONFIG_SDIO_HCI ++ u8 pg_num; ++#endif ++ ++#ifdef CONFIG_USB_HCI ++#ifdef CONFIG_USB_TX_AGGREGATION ++ u8 agg_num; ++#endif ++ u8 pkt_offset; ++#ifdef CONFIG_RTL8192D ++ u8 EMPktNum; ++ u16 EMPktLen[5];//The max value by HW ++#endif ++#endif ++}; ++ ++struct tx_servq { ++ _list tx_pending; ++ _queue sta_pending; ++ int qcnt; ++}; ++ ++ ++ ++struct sta_xmit_priv ++{ ++ _lock lock; ++ sint option; ++ sint apsd_setting; //When bit mask is on, the associated edca queue supports APSD. ++ ++ ++ //struct tx_servq blk_q[MAX_NUMBLKS]; ++ struct tx_servq be_q; //priority == 0,3 ++ struct tx_servq bk_q; //priority == 1,2 ++ struct tx_servq vi_q; //priority == 4,5 ++ struct tx_servq vo_q; //priority == 6,7 ++ _list legacy_dz; ++ _list apsd; ++ ++ u16 txseq_tid[16]; ++ ++ //uint sta_tx_bytes; ++ //u64 sta_tx_pkts; ++ //uint sta_tx_fail; ++ ++}; ++ ++ ++struct hw_txqueue { ++ volatile sint head; ++ volatile sint tail; ++ volatile sint free_sz; //in units of 64 bytes ++ volatile sint free_cmdsz; ++ volatile sint txsz[8]; ++ uint ff_hwaddr; ++ uint cmd_hwaddr; ++ sint ac_tag; ++}; ++ ++ ++struct xmit_priv { ++ ++ _lock lock; ++ ++ _sema xmit_sema; ++ _sema terminate_xmitthread_sema; ++ ++ //_queue blk_strms[MAX_NUMBLKS]; ++ _queue be_pending; ++ _queue bk_pending; ++ _queue vi_pending; ++ _queue vo_pending; ++ _queue bm_pending; ++ ++ //_queue legacy_dz_queue; ++ //_queue apsd_queue; ++ ++ u8 *pallocated_frame_buf; ++ u8 *pxmit_frame_buf; ++ uint free_xmitframe_cnt; ++ ++ //uint mapping_addr; ++ //uint pkt_sz; ++ ++ _queue free_xmit_queue; ++ ++ //struct hw_txqueue be_txqueue; ++ //struct hw_txqueue bk_txqueue; ++ //struct hw_txqueue vi_txqueue; ++ //struct hw_txqueue vo_txqueue; ++ //struct hw_txqueue bmc_txqueue; ++ ++ uint frag_len; ++ ++ _adapter *adapter; ++ ++ u8 vcs_setting; ++ u8 vcs; ++ u8 vcs_type; ++ //u16 rts_thresh; ++ ++ u64 tx_bytes; ++ u64 tx_pkts; ++ u64 tx_drop; ++ u64 last_tx_bytes; ++ u64 last_tx_pkts; ++ ++ struct hw_xmit *hwxmits; ++ u8 hwxmit_entry; ++ ++#ifdef CONFIG_USB_HCI ++ _sema tx_retevt;//all tx return event; ++ u8 txirp_cnt;// ++ ++#ifdef PLATFORM_OS_CE ++ USB_TRANSFER usb_transfer_write_port; ++// USB_TRANSFER usb_transfer_write_mem; ++#endif ++#ifdef PLATFORM_LINUX ++ struct tasklet_struct xmit_tasklet; ++#endif ++ //per AC pending irp ++ int beq_cnt; ++ int bkq_cnt; ++ int viq_cnt; ++ int voq_cnt; ++ ++#endif ++ ++#ifdef CONFIG_SDIO_HCI ++ u8 free_pg[8]; ++ u8 public_pgsz; ++ u8 required_pgsz; ++ u8 used_pgsz; ++ u8 init_pgsz; ++#ifdef PLATFORM_OS_XP ++ PMDL prd_freesz_mdl[2]; ++ u8 brd_freesz_pending[2]; ++ PIRP prd_freesz_irp[2]; ++ PSDBUS_REQUEST_PACKET prd_freesz_sdrp[2]; ++ u8 rd_freesz_irp_idx; ++#endif ++ ++#endif ++ ++#ifdef CONFIG_PCI_HCI ++ // Tx ++ struct rtw_tx_ring tx_ring[PCI_MAX_TX_QUEUE_COUNT]; ++ int txringcount[PCI_MAX_TX_QUEUE_COUNT]; ++#ifdef PLATFORM_LINUX ++ struct tasklet_struct xmit_tasklet; ++#endif ++#endif ++ ++ _queue free_xmitbuf_queue; ++ _queue pending_xmitbuf_queue; // unused?? ++ u8 *pallocated_xmitbuf; ++ u8 *pxmitbuf; ++ uint free_xmitbuf_cnt; ++ ++ _queue free_xmit_extbuf_queue; ++ u8 *pallocated_xmit_extbuf; ++ u8 *pxmit_extbuf; ++ uint free_xmit_extbuf_cnt; ++ ++ u16 nqos_ssn; ++ ATOMIC_T HwRdyXmitData; // driver should wait hw setting done for join event callback, only for Data Frame. 1:done 0:not yet. ++}; ++ ++extern struct xmit_buf *rtw_alloc_xmitbuf_ext(struct xmit_priv *pxmitpriv); ++extern s32 rtw_free_xmitbuf_ext(struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf); ++ ++extern struct xmit_buf *rtw_alloc_xmitbuf(struct xmit_priv *pxmitpriv); ++extern s32 rtw_free_xmitbuf(struct xmit_priv *pxmitpriv, struct xmit_buf *pxmitbuf); ++ ++void rtw_count_tx_stats(_adapter *padapter, struct xmit_frame *pxmitframe, int sz); ++extern void rtw_update_protection(_adapter *padapter, u8 *ie, uint ie_len); ++extern s32 rtw_make_wlanhdr(_adapter *padapter, u8 *hdr, struct pkt_attrib *pattrib); ++extern s32 rtw_put_snap(u8 *data, u16 h_proto); ++ ++extern struct xmit_frame *rtw_alloc_xmitframe(struct xmit_priv *pxmitpriv); ++extern s32 rtw_free_xmitframe(struct xmit_priv *pxmitpriv, struct xmit_frame *pxmitframe); ++extern void rtw_free_xmitframe_queue(struct xmit_priv *pxmitpriv, _queue *pframequeue); ++struct tx_servq *rtw_get_sta_pending(_adapter *padapter, struct sta_info *psta, sint up, u8 *ac); ++extern s32 rtw_xmitframe_enqueue(_adapter *padapter, struct xmit_frame *pxmitframe); ++extern struct xmit_frame* rtw_dequeue_xframe(struct xmit_priv *pxmitpriv, struct hw_xmit *phwxmit_i, sint entry); ++ ++extern s32 rtw_xmit_classifier(_adapter *padapter, struct xmit_frame *pxmitframe); ++extern thread_return rtw_xmit_thread(thread_context context); ++extern s32 rtw_xmitframe_coalesce(_adapter *padapter, _pkt *pkt, struct xmit_frame *pxmitframe); ++#ifdef CONFIG_TDLS ++extern void rtw_tdls_dis_rsp_fr(_adapter * padapter, struct xmit_frame * pxmitframe, u8 *pframe, u8 dialog); ++extern s32 rtw_xmit_tdls_coalesce(_adapter *padapter, struct xmit_frame *pxmitframe, u8 action); ++void rtw_dump_xframe(_adapter *padapter, struct xmit_frame *pxmitframe); ++#endif ++#ifdef CONFIG_IOL ++void rtw_dump_xframe_sync(_adapter *padapter, struct xmit_frame *pxmitframe); ++#endif ++s32 _rtw_init_hw_txqueue(struct hw_txqueue* phw_txqueue, u8 ac_tag); ++void _rtw_init_sta_xmit_priv(struct sta_xmit_priv *psta_xmitpriv); ++ ++ ++s32 rtw_txframes_pending(_adapter *padapter); ++s32 rtw_txframes_sta_ac_pending(_adapter *padapter, struct pkt_attrib *pattrib); ++void rtw_init_hwxmits(struct hw_xmit *phwxmit, sint entry); ++ ++ ++s32 _rtw_init_xmit_priv(struct xmit_priv *pxmitpriv, _adapter *padapter); ++void _rtw_free_xmit_priv (struct xmit_priv *pxmitpriv); ++ ++ ++void rtw_alloc_hwxmits(_adapter *padapter); ++void rtw_free_hwxmits(_adapter *padapter); ++ ++s32 rtw_free_xmitframe_ex(struct xmit_priv *pxmitpriv, struct xmit_frame *pxmitframe); ++ ++s32 rtw_xmit(_adapter *padapter, _pkt **pkt); ++ ++#ifdef CONFIG_TDLS ++sint xmitframe_enqueue_for_tdls_sleeping_sta(_adapter *padapter, struct xmit_frame *pxmitframe); ++#endif ++ ++#ifdef CONFIG_AP_MODE ++sint xmitframe_enqueue_for_sleeping_sta(_adapter *padapter, struct xmit_frame *pxmitframe); ++void stop_sta_xmit(_adapter *padapter, struct sta_info *psta); ++void wakeup_sta_to_xmit(_adapter *padapter, struct sta_info *psta); ++void xmit_delivery_enabled_frames(_adapter *padapter, struct sta_info *psta); ++#endif ++ ++#endif //_RTL871X_XMIT_H_ ++ +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/include/sdio_hal.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/include/sdio_hal.h 2013-07-26 19:36:06.000000000 +0000 +@@ -0,0 +1,34 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ++******************************************************************************/ ++#ifndef __SDIO_HAL_H__ ++ ++#define __SDIO_HAL_H__ ++ ++extern u8 sd_hal_bus_init(_adapter * adapter); ++extern u8 sd_hal_bus_deinit(_adapter * adapter); ++ ++ ++u8 sd_int_isr (IN PADAPTER padapter); ++void sd_int_dpc(PADAPTER padapter); ++ ++ ++#endif //__SDIO_HAL_H__ ++ +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/include/sdio_ops.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/include/sdio_ops.h 2013-07-26 19:36:06.000000000 +0000 +@@ -0,0 +1,80 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ++******************************************************************************/ ++#ifndef __SDIO_OPS_H_ ++#define __SDIO_OPS_H_ ++ ++#include ++#include ++#include ++#include ++ ++#ifdef PLATFORM_LINUX ++#include ++#endif ++ ++ ++ ++#ifdef PLATFORM_WINDOWS ++ ++#ifdef PLATFORM_OS_XP ++#include ++struct async_context ++{ ++ PMDL pmdl; ++ PSDBUS_REQUEST_PACKET sdrp; ++ unsigned char* r_buf; ++ unsigned char* padapter; ++}; ++#endif ++#ifdef PLATFORM_OS_CE ++#include ++#endif ++#endif ++ ++ ++ ++extern void sdio_set_intf_option(u32 *poption); ++ ++extern void sdio_set_intf_funs(struct intf_hdl *pintf_hdl); ++ ++extern uint sdio_init_intf_priv(struct intf_priv *pintfpriv); ++ ++extern void sdio_unload_intf_priv(struct intf_priv *pintfpriv); ++ ++extern void sdio_intf_hdl_init(u8 *priv); ++ ++extern void sdio_intf_hdl_unload(u8 *priv); ++ ++extern void sdio_intf_hdl_open(u8 *priv); ++ ++extern void sdio_intf_hdl_close(u8 *priv); ++ ++extern void sdio_set_intf_ops(struct _io_ops *pops); ++ ++//extern void sdio_set_intf_callbacks(struct _io_callbacks *pcallbacks); ++extern void sdio_func1cmd52_read(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *rmem); ++extern void sdio_func1cmd52_write(struct intf_hdl *pintfhdl, u32 addr, u32 cnt, u8 *wmem); ++ ++extern uint __inline _cvrt2ftaddr(const u32 addr, u32 *pftaddr) ; ++ ++ ++#endif ++ +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/include/sdio_ops_ce.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/include/sdio_ops_ce.h 2013-07-26 19:36:06.000000000 +0000 +@@ -0,0 +1,56 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ++******************************************************************************/ ++#ifndef _SDIO_OPS_WINCE_H_ ++#define _SDIO_OPS_WINCE_H_ ++ ++#include ++#include ++#include ++#include ++ ++ ++#ifdef PLATFORM_OS_CE ++ ++ ++extern u8 sdbus_cmd52r_ce(struct intf_priv *pintfpriv, u32 addr); ++ ++ ++extern void sdbus_cmd52w_ce(struct intf_priv *pintfpriv, u32 addr,u8 val8); ++ ++ ++uint sdbus_read_blocks_to_membuf_ce(struct intf_priv *pintfpriv, u32 addr, u32 cnt, u8 *pbuf); ++ ++extern uint sdbus_read_bytes_to_membuf_ce(struct intf_priv *pintfpriv, u32 addr, u32 cnt, u8 *pbuf); ++ ++ ++extern uint sdbus_write_blocks_from_membuf_ce(struct intf_priv *pintfpriv, u32 addr, u32 cnt, u8 *pbuf,u8 async); ++ ++extern uint sdbus_write_bytes_from_membuf_ce(struct intf_priv *pintfpriv, u32 addr, u32 cnt, u8 *pbuf); ++extern u8 sdbus_func1cmd52r_ce(struct intf_priv *pintfpriv, u32 addr); ++extern void sdbus_func1cmd52w_ce(struct intf_priv *pintfpriv, u32 addr, u8 val8); ++extern uint sdbus_read_reg(struct intf_priv *pintfpriv, u32 addr, u32 cnt,void *pdata); ++extern uint sdbus_write_reg(struct intf_priv *pintfpriv, u32 addr, u32 cnt,void *pdata); ++extern void sdio_read_int(_adapter *padapter, u32 addr,u8 sz,void *pdata); ++ ++#endif ++ ++#endif ++ +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/include/sdio_ops_linux.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/include/sdio_ops_linux.h 2013-07-26 19:36:06.000000000 +0000 +@@ -0,0 +1,55 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ++******************************************************************************/ ++#ifndef _SDIO_OPS_LINUX_H_ ++#define _SDIO_OPS_LINUX_H_ ++ ++#include ++#include ++#include ++#include ++ ++ ++#ifdef PLATFORM_LINUX ++ ++ ++extern u8 sdbus_cmd52r(struct intf_priv *pintfpriv, u32 addr); ++ ++ ++extern void sdbus_cmd52w(struct intf_priv *pintfpriv, u32 addr,u8 val8); ++extern u8 sdbus_direct_read8(struct intf_priv *pintfpriv, u32 addr); ++extern void sdbus_direct_write8(struct intf_priv *pintfpriv, u32 addr, u8 val8); ++ ++extern uint sdbus_read_bytes_to_recvbuf(struct intf_priv *pintfpriv, u32 addr, u32 cnt, u8 *pbuf); ++extern uint sdbus_read_blocks_to_recvbuf(struct intf_priv *pintfpriv, u32 addr, u32 cnt, u8 *pbuf); ++ ++ ++extern uint sdbus_write_blocks_from_xmitbuf(struct intf_priv *pintfpriv, u32 addr, u32 cnt, u8 *pbuf,u8 async); ++ ++extern uint sdbus_write_bytes_from_xmitbuf(struct intf_priv *pintfpriv, u32 addr, u32 cnt, u8 *pbuf); ++ ++ ++extern uint sdbus_read_reg(struct intf_priv *pintfpriv, u32 addr, u32 cnt,void *pdata); ++extern uint sdbus_write_reg(struct intf_priv *pintfpriv, u32 addr, u32 cnt,void *pdata); ++extern void sdio_read_int(_adapter *padapter, u32 addr,u8 sz,void *pdata); ++#endif ++ ++#endif ++ +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/include/sdio_ops_xp.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/include/sdio_ops_xp.h 2013-07-26 19:36:06.000000000 +0000 +@@ -0,0 +1,56 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ++******************************************************************************/ ++#ifndef _SDIO_OPS_XP_H_ ++#define _SDIO_OPS_XP_H_ ++ ++#include ++#include ++#include ++#include ++ ++ ++#ifdef PLATFORM_OS_XP ++ ++ ++extern u8 sdbus_cmd52r_xp(struct intf_priv *pintfpriv, u32 addr); ++ ++ ++extern void sdbus_cmd52w_xp(struct intf_priv *pintfpriv, u32 addr,u8 val8); ++ ++ ++uint sdbus_read_blocks_to_membuf_xp(struct intf_priv *pintfpriv, u32 addr, u32 cnt, u8 *pbuf); ++ ++extern uint sdbus_read_bytes_to_membuf_xp(struct intf_priv *pintfpriv, u32 addr, u32 cnt, u8 *pbuf); ++ ++ ++extern uint sdbus_write_blocks_from_membuf_xp(struct intf_priv *pintfpriv, u32 addr, u32 cnt, u8 *pbuf,u8 async); ++ ++extern uint sdbus_write_bytes_from_membuf_xp(struct intf_priv *pintfpriv, u32 addr, u32 cnt, u8 *pbuf); ++extern u8 sdbus_func1cmd52r_xp(struct intf_priv *pintfpriv, u32 addr); ++extern void sdbus_func1cmd52w_xp(struct intf_priv *pintfpriv, u32 addr, u8 val8); ++extern uint sdbus_read_reg(struct intf_priv *pintfpriv, u32 addr, u32 cnt,void *pdata); ++extern uint sdbus_write_reg(struct intf_priv *pintfpriv, u32 addr, u32 cnt,void *pdata); ++extern void sdio_read_int(_adapter *padapter, u32 addr,u8 sz,void *pdata); ++ ++#endif ++ ++#endif ++ +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/include/sdio_osintf.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/include/sdio_osintf.h 2013-07-26 19:36:06.000000000 +0000 +@@ -0,0 +1,48 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ++******************************************************************************/ ++#ifndef __SDIO_OSINTF_H ++#define __SDIO_OSINTF_H ++ ++ ++#include ++#include ++#include ++ ++ ++extern unsigned int sd_dvobj_init(_adapter * adapter); ++extern void sd_dvobj_deinit(_adapter * adapter); ++ ++void rtl871x_intf_stop(_adapter *padapter); ++ ++u8 sd_hal_bus_init(_adapter * padapter); ++u8 sd_hal_bus_deinit(_adapter * padapter); ++void update_xmit_hw_res(_adapter * padapter); ++void sd_c2h_hdl( PADAPTER padapter); ++ ++#ifdef PLATFORM_OS_CE ++extern NDIS_STATUS ce_sd_get_dev_hdl(_adapter *padapter ); ++SD_API_STATUS ++ce_sd_int_callback(SD_DEVICE_HANDLE hDevice, _adapter* padapter); ++extern void sd_setup_irs(_adapter *padapter); ++#endif ++ ++#endif ++ +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/include/sta_info.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/include/sta_info.h 2013-07-26 19:36:06.000000000 +0000 +@@ -0,0 +1,353 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++******************************************************************************/ ++#ifndef __STA_INFO_H_ ++#define __STA_INFO_H_ ++ ++#include ++#include ++#include ++#include ++ ++#define IBSS_START_MAC_ID 2 ++#ifdef SUPPORT_64_STA ++#define NUM_STA 64 ++#else ++#define NUM_STA 32 ++#endif ++#define FW_CTRL_MACID 32 ++#define NUM_ACL 64 ++ ++ ++//if mode ==0, then the sta is allowed once the addr is hit. ++//if mode ==1, then the sta is rejected once the addr is non-hit. ++struct rtw_wlan_acl_node { ++ _list list; ++ u8 addr[ETH_ALEN]; ++ u8 mode; ++}; ++ ++struct wlan_acl_pool { ++ struct rtw_wlan_acl_node aclnode[NUM_ACL]; ++}; ++ ++typedef struct _RSSI_STA{ ++ int UndecoratedSmoothedPWDB; ++ int UndecoratedSmoothedCCK; ++}RSSI_STA, *PRSSI_STA; ++ ++struct stainfo_stats { ++ ++ //u64 rx_pkts; ++ u64 rx_mgnt_pkts; ++ u64 rx_ctrl_pkts; ++ u64 rx_data_pkts; ++ ++ //u64 last_rx_pkts; ++ u64 last_rx_mgnt_pkts; ++ u64 last_rx_ctrl_pkts; ++ u64 last_rx_data_pkts; ++ ++ u64 rx_bytes; ++ u64 rx_drops; ++ ++ u64 tx_pkts; ++ u64 tx_bytes; ++ u64 tx_drops; ++ ++}; ++ ++#ifdef CONFIG_TDLS ++struct TDLS_PeerKey { ++ u8 kck[16]; /* TPK-KCK */ ++ u8 tk[16]; /* TPK-TK; only CCMP will be used */ ++} ; ++#endif ++ ++struct sta_info { ++ ++ _lock lock; ++ _list list; //free_sta_queue ++ _list hash_list; //sta_hash ++ //_list asoc_list; //20061114 ++ //_list sleep_list;//sleep_q ++ //_list wakeup_list;//wakeup_q ++ ++ struct sta_xmit_priv sta_xmitpriv; ++ struct sta_recv_priv sta_recvpriv; ++ ++ _queue sleep_q; ++ unsigned int sleepq_len; ++ ++ uint state; ++ uint aid; ++ uint mac_id; ++ uint qos_option; ++ u8 hwaddr[ETH_ALEN]; ++ ++ uint ieee8021x_blocked; //0: allowed, 1:blocked ++ uint dot118021XPrivacy; //aes, tkip... ++ union Keytype dot11tkiptxmickey; ++ union Keytype dot11tkiprxmickey; ++ union Keytype dot118021x_UncstKey; ++ union pn48 dot11txpn; // PN48 used for Unicast xmit. ++ union pn48 dot11rxpn; // PN48 used for Unicast recv. ++ ++ ++ u8 bssrateset[16]; ++ u32 bssratelen; ++ s32 rssi; ++ s32 signal_quality; ++ ++ u8 cts2self; ++ u8 rtsen; ++ ++ u8 raid; ++ u8 init_rate; ++ u32 ra_mask; ++ struct stainfo_stats sta_stats; ++ ++#ifdef CONFIG_TDLS ++ u32 tdls_sta_state; ++ u8 dialog; ++ u8 SNonce[32]; ++ u8 ANonce[32]; ++ u32 TDLS_PeerKey_Lifetime; ++ u16 TPK_count; ++ _timer TPK_timer; ++ struct TDLS_PeerKey tpk; ++ _adapter *padapter; ++ u8 cam_entry; ++ u16 stat_code; ++ u8 off_ch; ++ u16 ch_switch_time; ++ u16 ch_switch_timeout; ++ u8 option; ++ _timer option_timer; ++ _timer base_ch_timer; ++ _timer off_ch_timer; ++ ++ _timer handshake_timer; ++ _timer alive_timer1; ++ _timer alive_timer2; ++ u8 timer_flag; ++ u8 alive_count; ++#endif ++ ++ //for A-MPDU TX, ADDBA timeout check ++ _timer addba_retry_timer; ++ ++ //for A-MPDU Rx reordering buffer control ++ struct recv_reorder_ctrl recvreorder_ctrl[16]; ++ ++ //for A-MPDU Tx ++ //unsigned char ampdu_txen_bitmap; ++ u16 BA_starting_seqctrl[16]; ++ ++ ++#ifdef CONFIG_80211N_HT ++ struct ht_priv htpriv; ++#endif ++ ++ //Notes: ++ //STA_Mode: ++ //curr_network(mlme_priv/security_priv/qos/ht) + sta_info: (STA & AP) CAP/INFO ++ //scan_q: AP CAP/INFO ++ ++ //AP_Mode: ++ //curr_network(mlme_priv/security_priv/qos/ht) : AP CAP/INFO ++ //sta_info: (AP & STA) CAP/INFO ++ ++#ifdef CONFIG_AP_MODE ++ ++ _list asoc_list; ++ _list auth_list; ++ ++ unsigned int expire_to; ++ unsigned int auth_seq; ++ unsigned int authalg; ++ unsigned char chg_txt[128]; ++ ++ u16 capability; ++ int flags; ++ ++ int dot8021xalg;//0:disable, 1:psk, 2:802.1x ++ int wpa_psk;//0:disable, bit(0): WPA, bit(1):WPA2 ++ int wpa_group_cipher; ++ int wpa2_group_cipher; ++ int wpa_pairwise_cipher; ++ int wpa2_pairwise_cipher; ++ ++ u8 bpairwise_key_installed; ++ ++#ifdef CONFIG_NATIVEAP_MLME ++ u8 wpa_ie[32]; ++ ++ u8 nonerp_set; ++ u8 no_short_slot_time_set; ++ u8 no_short_preamble_set; ++ u8 no_ht_gf_set; ++ u8 no_ht_set; ++ u8 ht_20mhz_set; ++#endif // CONFIG_NATIVEAP_MLME ++ ++ unsigned int tx_ra_bitmap; ++ u8 qos_info; ++ ++ u8 max_sp_len; ++ u8 uapsd_bk;//BIT(0): Delivery enabled, BIT(1): Trigger enabled ++ u8 uapsd_be; ++ u8 uapsd_vi; ++ u8 uapsd_vo; ++ ++ u8 has_legacy_ac; ++ unsigned int sleepq_ac_len; ++ ++#ifdef CONFIG_P2P ++ //p2p priv data ++ u8 is_p2p_device; ++ u8 p2p_status_code; ++ ++ //p2p client info ++ u8 dev_addr[ETH_ALEN]; ++ //u8 iface_addr[ETH_ALEN];//= hwaddr[ETH_ALEN] ++ u8 dev_cap; ++ u16 config_methods; ++ u8 primary_dev_type[8]; ++ u8 num_of_secdev_type; ++ u8 secdev_types_list[32];// 32/8 == 4; ++ u16 dev_name_len; ++ u8 dev_name[32]; ++#endif //CONFIG_P2P ++ ++#ifdef CONFIG_TX_MCAST2UNI ++ u8 under_exist_checking; ++#endif // CONFIG_TX_MCAST2UNI ++ ++#endif // CONFIG_AP_MODE ++ ++#ifdef CONFIG_IOCTL_CFG80211 ++ u8 *passoc_req; ++ u32 assoc_req_len; ++#endif ++ ++ //for DM ++ RSSI_STA rssi_stat; ++ ++ ++}; ++ ++#define sta_rx_pkts(sta) \ ++ (sta->sta_stats.rx_mgnt_pkts \ ++ + sta->sta_stats.rx_ctrl_pkts \ ++ + sta->sta_stats.rx_data_pkts) ++ ++#define sta_last_rx_pkts(sta) \ ++ (sta->sta_stats.last_rx_mgnt_pkts \ ++ + sta->sta_stats.last_rx_ctrl_pkts \ ++ + sta->sta_stats.last_rx_data_pkts) ++ ++#define sta_update_last_rx_pkts(sta) \ ++ do { \ ++ sta->sta_stats.last_rx_mgnt_pkts = sta->sta_stats.rx_mgnt_pkts; \ ++ sta->sta_stats.last_rx_ctrl_pkts = sta->sta_stats.rx_ctrl_pkts; \ ++ sta->sta_stats.last_rx_data_pkts = sta->sta_stats.rx_data_pkts; \ ++ } while(0) ++ ++#define STA_RX_PKTS_ARG(sta) \ ++ sta->sta_stats.rx_mgnt_pkts \ ++ , sta->sta_stats.rx_ctrl_pkts \ ++ , sta->sta_stats.rx_data_pkts ++ ++#define STA_LAST_RX_PKTS_ARG(sta) \ ++ sta->sta_stats.last_rx_mgnt_pkts \ ++ , sta->sta_stats.last_rx_ctrl_pkts \ ++ , sta->sta_stats.last_rx_data_pkts ++ ++#define STA_PKTS_FMT "(m:%llu, c:%llu, d:%llu)" ++ ++struct sta_priv { ++ ++ u8 *pallocated_stainfo_buf; ++ u8 *pstainfo_buf; ++ _queue free_sta_queue; ++ ++ _lock sta_hash_lock; ++ _list sta_hash[NUM_STA]; ++ int asoc_sta_count; ++ _queue sleep_q; ++ _queue wakeup_q; ++ ++ _adapter *padapter; ++ ++ ++#ifdef CONFIG_AP_MODE ++ _list asoc_list; ++ _list auth_list; ++ _lock asoc_list_lock; ++ _lock auth_list_lock; ++ ++ unsigned int auth_to; //sec, time to expire in authenticating. ++ unsigned int assoc_to; //sec, time to expire before associating. ++ unsigned int expire_to; //sec , time to expire after associated. ++ ++ /* pointers to STA info; based on allocated AID or NULL if AID free ++ * AID is in the range 1-2007, so sta_aid[0] corresponders to AID 1 ++ * and so on ++ */ ++ struct sta_info *sta_aid[NUM_STA]; ++ ++ u16 sta_dz_bitmap;//only support 15 stations, staion aid bitmap for sleeping sta. ++ u16 tim_bitmap;//only support 15 stations, aid=0~15 mapping bit0~bit15 ++ ++ u16 max_num_sta; ++#endif ++ ++}; ++ ++ ++__inline static u32 wifi_mac_hash(u8 *mac) ++{ ++ u32 x; ++ ++ x = mac[0]; ++ x = (x << 2) ^ mac[1]; ++ x = (x << 2) ^ mac[2]; ++ x = (x << 2) ^ mac[3]; ++ x = (x << 2) ^ mac[4]; ++ x = (x << 2) ^ mac[5]; ++ ++ x ^= x >> 8; ++ x = x & (NUM_STA - 1); ++ ++ return x; ++} ++ ++ ++extern u32 _rtw_init_sta_priv(struct sta_priv *pstapriv); ++extern u32 _rtw_free_sta_priv(struct sta_priv *pstapriv); ++extern struct sta_info *rtw_alloc_stainfo(struct sta_priv *pstapriv, u8 *hwaddr); ++extern u32 rtw_free_stainfo(_adapter *padapter , struct sta_info *psta); ++extern void rtw_free_all_stainfo(_adapter *padapter); ++extern struct sta_info *rtw_get_stainfo(struct sta_priv *pstapriv, u8 *hwaddr); ++extern u32 rtw_init_bcmc_stainfo(_adapter* padapter); ++extern struct sta_info* rtw_get_bcmc_stainfo(_adapter* padapter); ++extern u8 rtw_access_ctrl(struct wlan_acl_pool* pacl_list, u8 * mac_addr); ++ ++#endif //_STA_INFO_H_ +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/include/usb_hal.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/include/usb_hal.h 2013-07-26 19:36:06.000000000 +0000 +@@ -0,0 +1,32 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ++******************************************************************************/ ++#ifndef __USB_HAL_H__ ++#define __USB_HAL_H__ ++ ++ ++void rtl8192cu_set_hal_ops(_adapter * padapter); ++ ++void rtl8192du_set_hal_ops(_adapter * padapter); ++#ifdef CONFIG_INTEL_PROXIM ++extern _adapter *rtw_usb_get_sw_pointer(void); ++#endif //CONFIG_INTEL_PROXIM ++#endif //__USB_HAL_H__ ++ +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/include/usb_ops.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/include/usb_ops.h 2013-07-26 19:36:06.000000000 +0000 +@@ -0,0 +1,100 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ++******************************************************************************/ ++#ifndef __USB_OPS_H_ ++#define __USB_OPS_H_ ++ ++#include ++#include ++#include ++#include ++ ++#define REALTEK_USB_VENQT_READ 0xC0 ++#define REALTEK_USB_VENQT_WRITE 0x40 ++#define REALTEK_USB_VENQT_CMD_REQ 0x05 ++#define REALTEK_USB_VENQT_CMD_IDX 0x00 ++ ++enum{ ++ VENDOR_WRITE = 0x00, ++ VENDOR_READ = 0x01, ++}; ++#define ALIGNMENT_UNIT 16 ++#define MAX_VENDOR_REQ_CMD_SIZE 254 //8188cu SIE Support ++#define MAX_USB_IO_CTL_SIZE (MAX_VENDOR_REQ_CMD_SIZE +ALIGNMENT_UNIT) ++ ++#ifdef PLATFORM_LINUX ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,12)) ++#define rtw_usb_control_msg(dev, pipe, request, requesttype, value, index, data, size, timeout_ms) \ ++ usb_control_msg((dev), (pipe), (request), (requesttype), (value), (index), (data), (size), (timeout_ms)) ++#define rtw_usb_bulk_msg(usb_dev, pipe, data, len, actual_length, timeout_ms) \ ++ usb_bulk_msg((usb_dev), (pipe), (data), (len), (actual_length), (timeout_ms)) ++#else ++#define rtw_usb_control_msg(dev, pipe, request, requesttype, value, index, data, size,timeout_ms) \ ++ usb_control_msg((dev), (pipe), (request), (requesttype), (value), (index), (data), (size), \ ++ ((timeout_ms) == 0) ||((timeout_ms)*HZ/1000>0)?((timeout_ms)*HZ/1000):1) ++#define rtw_usb_bulk_msg(usb_dev, pipe, data, len, actual_length, timeout_ms) \ ++ usb_bulk_msg((usb_dev), (pipe), (data), (len), (actual_length), \ ++ ((timeout_ms) == 0) ||((timeout_ms)*HZ/1000>0)?((timeout_ms)*HZ/1000):1) ++#endif ++#endif //PLATFORM_LINUX ++ ++#ifdef CONFIG_RTL8192C ++void rtl8192cu_set_intf_ops(struct _io_ops *pops); ++ ++void rtl8192cu_recv_tasklet(void *priv); ++ ++void rtl8192cu_xmit_tasklet(void *priv); ++#endif ++ ++#ifdef CONFIG_RTL8192D ++void rtl8192du_set_intf_ops(struct _io_ops *pops); ++ ++void rtl8192du_recv_tasklet(void *priv); ++ ++void rtl8192du_xmit_tasklet(void *priv); ++#endif ++ ++/* ++* Increase and check if the continual_urb_error of this @param dvobjprive is larger than MAX_CONTINUAL_URB_ERR ++* @return _TRUE: ++* @return _FALSE: ++*/ ++static inline int rtw_inc_and_chk_continual_urb_error(struct dvobj_priv *dvobjpriv) ++{ ++ int ret = _FALSE; ++ int value; ++ if( (value=ATOMIC_INC_RETURN(&dvobjpriv->continual_urb_error)) > MAX_CONTINUAL_URB_ERR) { ++ DBG_871X("[dvobjpriv:%p][ERROR] continual_urb_error:%d > %d\n", dvobjpriv, value, MAX_CONTINUAL_URB_ERR); ++ ret = _TRUE; ++ } else { ++ //DBG_871X("[dvobjpriv:%p] continual_urb_error:%d\n", dvobjpriv, value); ++ } ++ return ret; ++} ++ ++/* ++* Set the continual_urb_error of this @param dvobjprive to 0 ++*/ ++static inline void rtw_reset_continual_urb_error(struct dvobj_priv *dvobjpriv) ++{ ++ ATOMIC_SET(&dvobjpriv->continual_urb_error, 0); ++} ++ ++#endif //__USB_OPS_H_ +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/include/usb_osintf.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/include/usb_osintf.h 2013-07-26 19:36:06.000000000 +0000 +@@ -0,0 +1,39 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ++******************************************************************************/ ++#ifndef __USB_OSINTF_H ++#define __USB_OSINTF_H ++ ++#include ++#include ++#include ++#include ++ ++#define USBD_HALTED(Status) ((ULONG)(Status) >> 30 == 3) ++ ++ ++//uint usb_dvobj_init(_adapter * adapter); ++//void usb_dvobj_deinit(_adapter * adapter); ++ ++u8 usbvendorrequest(struct dvobj_priv *pdvobjpriv, RT_USB_BREQUEST brequest, RT_USB_WVALUE wvalue, u8 windex, void* data, u8 datalen, u8 isdirectionin); ++ ++ ++#endif ++ +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/include/usb_vendor_req.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/include/usb_vendor_req.h 2013-07-26 19:36:06.000000000 +0000 +@@ -0,0 +1,60 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ++******************************************************************************/ ++#ifndef _USB_VENDOR_REQUEST_H_ ++#define _USB_VENDOR_REQUEST_H_ ++ ++//4 Set/Get Register related wIndex/Data ++#define RT_USB_RESET_MASK_OFF 0 ++#define RT_USB_RESET_MASK_ON 1 ++#define RT_USB_SLEEP_MASK_OFF 0 ++#define RT_USB_SLEEP_MASK_ON 1 ++#define RT_USB_LDO_ON 1 ++#define RT_USB_LDO_OFF 0 ++ ++//4 Set/Get SYSCLK related wValue or Data ++#define RT_USB_SYSCLK_32KHZ 0 ++#define RT_USB_SYSCLK_40MHZ 1 ++#define RT_USB_SYSCLK_60MHZ 2 ++ ++ ++typedef enum _RT_USB_BREQUEST { ++ RT_USB_SET_REGISTER = 1, ++ RT_USB_SET_SYSCLK = 2, ++ RT_USB_GET_SYSCLK = 3, ++ RT_USB_GET_REGISTER = 4 ++} RT_USB_BREQUEST; ++ ++ ++typedef enum _RT_USB_WVALUE { ++ RT_USB_RESET_MASK = 1, ++ RT_USB_SLEEP_MASK = 2, ++ RT_USB_USB_HRCPWM = 3, ++ RT_USB_LDO = 4, ++ RT_USB_BOOT_TYPE = 5 ++} RT_USB_WVALUE; ++ ++ ++//BOOLEAN usbvendorrequest(PCE_USB_DEVICE CEdevice, RT_USB_BREQUEST bRequest, RT_USB_WVALUE wValue, UCHAR wIndex, PVOID Data, UCHAR DataLength, BOOLEAN isDirectionIn); ++//BOOLEAN CEusbGetStatusRequest(PCE_USB_DEVICE CEdevice, IN USHORT Op, IN USHORT Index, PVOID Data); ++//BOOLEAN CEusbFeatureRequest(PCE_USB_DEVICE CEdevice, IN USHORT Op, IN USHORT FeatureSelector, IN USHORT Index); ++//BOOLEAN CEusbGetDescriptorRequest(PCE_USB_DEVICE CEdevice, IN short urbLength, IN UCHAR DescriptorType, IN UCHAR Index, IN USHORT LanguageId, IN PVOID TransferBuffer, IN ULONG TransferBufferLength); ++ ++#endif +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/include/wifi.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/include/wifi.h 2013-07-26 19:36:06.000000000 +0000 +@@ -0,0 +1,1185 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ++******************************************************************************/ ++#ifndef _WIFI_H_ ++#define _WIFI_H_ ++ ++#include ++ ++#ifdef BIT ++//#error "BIT define occurred earlier elsewhere!\n" ++#undef BIT ++#endif ++#define BIT(x) (1 << (x)) ++ ++ ++#define WLAN_ETHHDR_LEN 14 ++#define WLAN_ETHADDR_LEN 6 ++#define WLAN_IEEE_OUI_LEN 3 ++#define WLAN_ADDR_LEN 6 ++#define WLAN_CRC_LEN 4 ++#define WLAN_BSSID_LEN 6 ++#define WLAN_BSS_TS_LEN 8 ++#define WLAN_HDR_A3_LEN 24 ++#define WLAN_HDR_A4_LEN 30 ++#define WLAN_HDR_A3_QOS_LEN 26 ++#define WLAN_HDR_A4_QOS_LEN 32 ++#define WLAN_SSID_MAXLEN 32 ++#define WLAN_DATA_MAXLEN 2312 ++ ++#define WLAN_A3_PN_OFFSET 24 ++#define WLAN_A4_PN_OFFSET 30 ++ ++#define WLAN_MIN_ETHFRM_LEN 60 ++#define WLAN_MAX_ETHFRM_LEN 1514 ++#define WLAN_ETHHDR_LEN 14 ++ ++#define P80211CAPTURE_VERSION 0x80211001 ++ ++#ifdef GREEN_HILL ++#pragma pack(1) ++#endif ++ ++enum WIFI_FRAME_TYPE { ++ WIFI_MGT_TYPE = (0), ++ WIFI_CTRL_TYPE = (BIT(2)), ++ WIFI_DATA_TYPE = (BIT(3)), ++ WIFI_QOS_DATA_TYPE = (BIT(7)|BIT(3)), //!< QoS Data ++}; ++ ++enum WIFI_FRAME_SUBTYPE { ++ ++ // below is for mgt frame ++ WIFI_ASSOCREQ = (0 | WIFI_MGT_TYPE), ++ WIFI_ASSOCRSP = (BIT(4) | WIFI_MGT_TYPE), ++ WIFI_REASSOCREQ = (BIT(5) | WIFI_MGT_TYPE), ++ WIFI_REASSOCRSP = (BIT(5) | BIT(4) | WIFI_MGT_TYPE), ++ WIFI_PROBEREQ = (BIT(6) | WIFI_MGT_TYPE), ++ WIFI_PROBERSP = (BIT(6) | BIT(4) | WIFI_MGT_TYPE), ++ WIFI_BEACON = (BIT(7) | WIFI_MGT_TYPE), ++ WIFI_ATIM = (BIT(7) | BIT(4) | WIFI_MGT_TYPE), ++ WIFI_DISASSOC = (BIT(7) | BIT(5) | WIFI_MGT_TYPE), ++ WIFI_AUTH = (BIT(7) | BIT(5) | BIT(4) | WIFI_MGT_TYPE), ++ WIFI_DEAUTH = (BIT(7) | BIT(6) | WIFI_MGT_TYPE), ++ WIFI_ACTION = (BIT(7) | BIT(6) | BIT(4) | WIFI_MGT_TYPE), ++ ++ // below is for control frame ++ WIFI_PSPOLL = (BIT(7) | BIT(5) | WIFI_CTRL_TYPE), ++ WIFI_RTS = (BIT(7) | BIT(5) | BIT(4) | WIFI_CTRL_TYPE), ++ WIFI_CTS = (BIT(7) | BIT(6) | WIFI_CTRL_TYPE), ++ WIFI_ACK = (BIT(7) | BIT(6) | BIT(4) | WIFI_CTRL_TYPE), ++ WIFI_CFEND = (BIT(7) | BIT(6) | BIT(5) | WIFI_CTRL_TYPE), ++ WIFI_CFEND_CFACK = (BIT(7) | BIT(6) | BIT(5) | BIT(4) | WIFI_CTRL_TYPE), ++ ++ // below is for data frame ++ WIFI_DATA = (0 | WIFI_DATA_TYPE), ++ WIFI_DATA_CFACK = (BIT(4) | WIFI_DATA_TYPE), ++ WIFI_DATA_CFPOLL = (BIT(5) | WIFI_DATA_TYPE), ++ WIFI_DATA_CFACKPOLL = (BIT(5) | BIT(4) | WIFI_DATA_TYPE), ++ WIFI_DATA_NULL = (BIT(6) | WIFI_DATA_TYPE), ++ WIFI_CF_ACK = (BIT(6) | BIT(4) | WIFI_DATA_TYPE), ++ WIFI_CF_POLL = (BIT(6) | BIT(5) | WIFI_DATA_TYPE), ++ WIFI_CF_ACKPOLL = (BIT(6) | BIT(5) | BIT(4) | WIFI_DATA_TYPE), ++ WIFI_QOS_DATA_NULL = (BIT(6) | WIFI_QOS_DATA_TYPE), ++}; ++ ++enum WIFI_REASON_CODE { ++ _RSON_RESERVED_ = 0, ++ _RSON_UNSPECIFIED_ = 1, ++ _RSON_AUTH_NO_LONGER_VALID_ = 2, ++ _RSON_DEAUTH_STA_LEAVING_ = 3, ++ _RSON_INACTIVITY_ = 4, ++ _RSON_UNABLE_HANDLE_ = 5, ++ _RSON_CLS2_ = 6, ++ _RSON_CLS3_ = 7, ++ _RSON_DISAOC_STA_LEAVING_ = 8, ++ _RSON_ASOC_NOT_AUTH_ = 9, ++ ++ // WPA reason ++ _RSON_INVALID_IE_ = 13, ++ _RSON_MIC_FAILURE_ = 14, ++ _RSON_4WAY_HNDSHK_TIMEOUT_ = 15, ++ _RSON_GROUP_KEY_UPDATE_TIMEOUT_ = 16, ++ _RSON_DIFF_IE_ = 17, ++ _RSON_MLTCST_CIPHER_NOT_VALID_ = 18, ++ _RSON_UNICST_CIPHER_NOT_VALID_ = 19, ++ _RSON_AKMP_NOT_VALID_ = 20, ++ _RSON_UNSUPPORT_RSNE_VER_ = 21, ++ _RSON_INVALID_RSNE_CAP_ = 22, ++ _RSON_IEEE_802DOT1X_AUTH_FAIL_ = 23, ++ ++ //belowing are Realtek definition ++ _RSON_PMK_NOT_AVAILABLE_ = 24, ++ _RSON_TDLS_TEAR_TOOFAR_ = 25, ++ _RSON_TDLS_TEAR_UN_RSN_ = 26, ++}; ++ ++/* Reason codes (IEEE 802.11-2007, 7.3.1.7, Table 7-22) */ ++#if 0 ++#define WLAN_REASON_UNSPECIFIED 1 ++#define WLAN_REASON_PREV_AUTH_NOT_VALID 2 ++#define WLAN_REASON_DEAUTH_LEAVING 3 ++#define WLAN_REASON_DISASSOC_DUE_TO_INACTIVITY 4 ++#define WLAN_REASON_DISASSOC_AP_BUSY 5 ++#define WLAN_REASON_CLASS2_FRAME_FROM_NONAUTH_STA 6 ++#define WLAN_REASON_CLASS3_FRAME_FROM_NONASSOC_STA 7 ++#define WLAN_REASON_DISASSOC_STA_HAS_LEFT 8 ++#define WLAN_REASON_STA_REQ_ASSOC_WITHOUT_AUTH 9 ++#endif ++/* IEEE 802.11h */ ++#define WLAN_REASON_PWR_CAPABILITY_NOT_VALID 10 ++#define WLAN_REASON_SUPPORTED_CHANNEL_NOT_VALID 11 ++#if 0 ++/* IEEE 802.11i */ ++#define WLAN_REASON_INVALID_IE 13 ++#define WLAN_REASON_MICHAEL_MIC_FAILURE 14 ++#define WLAN_REASON_4WAY_HANDSHAKE_TIMEOUT 15 ++#define WLAN_REASON_GROUP_KEY_UPDATE_TIMEOUT 16 ++#define WLAN_REASON_IE_IN_4WAY_DIFFERS 17 ++#define WLAN_REASON_GROUP_CIPHER_NOT_VALID 18 ++#define WLAN_REASON_PAIRWISE_CIPHER_NOT_VALID 19 ++#define WLAN_REASON_AKMP_NOT_VALID 20 ++#define WLAN_REASON_UNSUPPORTED_RSN_IE_VERSION 21 ++#define WLAN_REASON_INVALID_RSN_IE_CAPAB 22 ++#define WLAN_REASON_IEEE_802_1X_AUTH_FAILED 23 ++#define WLAN_REASON_CIPHER_SUITE_REJECTED 24 ++#endif ++ ++enum WIFI_STATUS_CODE { ++ _STATS_SUCCESSFUL_ = 0, ++ _STATS_FAILURE_ = 1, ++ _STATS_CAP_FAIL_ = 10, ++ _STATS_NO_ASOC_ = 11, ++ _STATS_OTHER_ = 12, ++ _STATS_NO_SUPP_ALG_ = 13, ++ _STATS_OUT_OF_AUTH_SEQ_ = 14, ++ _STATS_CHALLENGE_FAIL_ = 15, ++ _STATS_AUTH_TIMEOUT_ = 16, ++ _STATS_UNABLE_HANDLE_STA_ = 17, ++ _STATS_RATE_FAIL_ = 18, ++}; ++ ++/* Status codes (IEEE 802.11-2007, 7.3.1.9, Table 7-23) */ ++#if 0 ++#define WLAN_STATUS_SUCCESS 0 ++#define WLAN_STATUS_UNSPECIFIED_FAILURE 1 ++#define WLAN_STATUS_CAPS_UNSUPPORTED 10 ++#define WLAN_STATUS_REASSOC_NO_ASSOC 11 ++#define WLAN_STATUS_ASSOC_DENIED_UNSPEC 12 ++#define WLAN_STATUS_NOT_SUPPORTED_AUTH_ALG 13 ++#define WLAN_STATUS_UNKNOWN_AUTH_TRANSACTION 14 ++#define WLAN_STATUS_CHALLENGE_FAIL 15 ++#define WLAN_STATUS_AUTH_TIMEOUT 16 ++#define WLAN_STATUS_AP_UNABLE_TO_HANDLE_NEW_STA 17 ++#define WLAN_STATUS_ASSOC_DENIED_RATES 18 ++#endif ++//entended ++/* IEEE 802.11b */ ++#define WLAN_STATUS_ASSOC_DENIED_NOSHORT 19 ++#define WLAN_STATUS_ASSOC_DENIED_NOPBCC 20 ++#define WLAN_STATUS_ASSOC_DENIED_NOAGILITY 21 ++/* IEEE 802.11h */ ++#define WLAN_STATUS_SPEC_MGMT_REQUIRED 22 ++#define WLAN_STATUS_PWR_CAPABILITY_NOT_VALID 23 ++#define WLAN_STATUS_SUPPORTED_CHANNEL_NOT_VALID 24 ++/* IEEE 802.11g */ ++#define WLAN_STATUS_ASSOC_DENIED_NO_SHORT_SLOT_TIME 25 ++#define WLAN_STATUS_ASSOC_DENIED_NO_ER_PBCC 26 ++#define WLAN_STATUS_ASSOC_DENIED_NO_DSSS_OFDM 27 ++/* IEEE 802.11w */ ++#define WLAN_STATUS_ASSOC_REJECTED_TEMPORARILY 30 ++#define WLAN_STATUS_ROBUST_MGMT_FRAME_POLICY_VIOLATION 31 ++/* IEEE 802.11i */ ++#define WLAN_STATUS_INVALID_IE 40 ++#define WLAN_STATUS_GROUP_CIPHER_NOT_VALID 41 ++#define WLAN_STATUS_PAIRWISE_CIPHER_NOT_VALID 42 ++#define WLAN_STATUS_AKMP_NOT_VALID 43 ++#define WLAN_STATUS_UNSUPPORTED_RSN_IE_VERSION 44 ++#define WLAN_STATUS_INVALID_RSN_IE_CAPAB 45 ++#define WLAN_STATUS_CIPHER_REJECTED_PER_POLICY 46 ++#define WLAN_STATUS_TS_NOT_CREATED 47 ++#define WLAN_STATUS_DIRECT_LINK_NOT_ALLOWED 48 ++#define WLAN_STATUS_DEST_STA_NOT_PRESENT 49 ++#define WLAN_STATUS_DEST_STA_NOT_QOS_STA 50 ++#define WLAN_STATUS_ASSOC_DENIED_LISTEN_INT_TOO_LARGE 51 ++/* IEEE 802.11r */ ++#define WLAN_STATUS_INVALID_FT_ACTION_FRAME_COUNT 52 ++#define WLAN_STATUS_INVALID_PMKID 53 ++#define WLAN_STATUS_INVALID_MDIE 54 ++#define WLAN_STATUS_INVALID_FTIE 55 ++ ++ ++enum WIFI_REG_DOMAIN { ++ DOMAIN_FCC = 1, ++ DOMAIN_IC = 2, ++ DOMAIN_ETSI = 3, ++ DOMAIN_SPAIN = 4, ++ DOMAIN_FRANCE = 5, ++ DOMAIN_MKK = 6, ++ DOMAIN_ISRAEL = 7, ++ DOMAIN_MKK1 = 8, ++ DOMAIN_MKK2 = 9, ++ DOMAIN_MKK3 = 10, ++ DOMAIN_MAX ++}; ++ ++#define _TO_DS_ BIT(8) ++#define _FROM_DS_ BIT(9) ++#define _MORE_FRAG_ BIT(10) ++#define _RETRY_ BIT(11) ++#define _PWRMGT_ BIT(12) ++#define _MORE_DATA_ BIT(13) ++#define _PRIVACY_ BIT(14) ++#define _ORDER_ BIT(15) ++ ++#define SetToDs(pbuf) \ ++ do { \ ++ *(unsigned short *)(pbuf) |= cpu_to_le16(_TO_DS_); \ ++ } while(0) ++ ++#define GetToDs(pbuf) (((*(unsigned short *)(pbuf)) & le16_to_cpu(_TO_DS_)) != 0) ++ ++#define ClearToDs(pbuf) \ ++ do { \ ++ *(unsigned short *)(pbuf) &= (~cpu_to_le16(_TO_DS_)); \ ++ } while(0) ++ ++#define SetFrDs(pbuf) \ ++ do { \ ++ *(unsigned short *)(pbuf) |= cpu_to_le16(_FROM_DS_); \ ++ } while(0) ++ ++#define GetFrDs(pbuf) (((*(unsigned short *)(pbuf)) & le16_to_cpu(_FROM_DS_)) != 0) ++ ++#define ClearFrDs(pbuf) \ ++ do { \ ++ *(unsigned short *)(pbuf) &= (~cpu_to_le16(_FROM_DS_)); \ ++ } while(0) ++ ++#define get_tofr_ds(pframe) ((GetToDs(pframe) << 1) | GetFrDs(pframe)) ++ ++ ++#define SetMFrag(pbuf) \ ++ do { \ ++ *(unsigned short *)(pbuf) |= cpu_to_le16(_MORE_FRAG_); \ ++ } while(0) ++ ++#define GetMFrag(pbuf) (((*(unsigned short *)(pbuf)) & le16_to_cpu(_MORE_FRAG_)) != 0) ++ ++#define ClearMFrag(pbuf) \ ++ do { \ ++ *(unsigned short *)(pbuf) &= (~cpu_to_le16(_MORE_FRAG_)); \ ++ } while(0) ++ ++#define SetRetry(pbuf) \ ++ do { \ ++ *(unsigned short *)(pbuf) |= cpu_to_le16(_RETRY_); \ ++ } while(0) ++ ++#define GetRetry(pbuf) (((*(unsigned short *)(pbuf)) & le16_to_cpu(_RETRY_)) != 0) ++ ++#define ClearRetry(pbuf) \ ++ do { \ ++ *(unsigned short *)(pbuf) &= (~cpu_to_le16(_RETRY_)); \ ++ } while(0) ++ ++#define SetPwrMgt(pbuf) \ ++ do { \ ++ *(unsigned short *)(pbuf) |= cpu_to_le16(_PWRMGT_); \ ++ } while(0) ++ ++#define GetPwrMgt(pbuf) (((*(unsigned short *)(pbuf)) & le16_to_cpu(_PWRMGT_)) != 0) ++ ++#define ClearPwrMgt(pbuf) \ ++ do { \ ++ *(unsigned short *)(pbuf) &= (~cpu_to_le16(_PWRMGT_)); \ ++ } while(0) ++ ++#define SetMData(pbuf) \ ++ do { \ ++ *(unsigned short *)(pbuf) |= cpu_to_le16(_MORE_DATA_); \ ++ } while(0) ++ ++#define GetMData(pbuf) (((*(unsigned short *)(pbuf)) & le16_to_cpu(_MORE_DATA_)) != 0) ++ ++#define ClearMData(pbuf) \ ++ do { \ ++ *(unsigned short *)(pbuf) &= (~cpu_to_le16(_MORE_DATA_)); \ ++ } while(0) ++ ++#define SetPrivacy(pbuf) \ ++ do { \ ++ *(unsigned short *)(pbuf) |= cpu_to_le16(_PRIVACY_); \ ++ } while(0) ++ ++#define GetPrivacy(pbuf) (((*(unsigned short *)(pbuf)) & le16_to_cpu(_PRIVACY_)) != 0) ++ ++#define ClearPrivacy(pbuf) \ ++ do { \ ++ *(unsigned short *)(pbuf) &= (~cpu_to_le16(_PRIVACY_)); \ ++ } while(0) ++ ++ ++#define GetOrder(pbuf) (((*(unsigned short *)(pbuf)) & le16_to_cpu(_ORDER_)) != 0) ++ ++#define GetFrameType(pbuf) (le16_to_cpu(*(unsigned short *)(pbuf)) & (BIT(3) | BIT(2))) ++ ++#define SetFrameType(pbuf,type) \ ++ do { \ ++ *(unsigned short *)(pbuf) &= __constant_cpu_to_le16(~(BIT(3) | BIT(2))); \ ++ *(unsigned short *)(pbuf) |= __constant_cpu_to_le16(type); \ ++ } while(0) ++ ++#define GetFrameSubType(pbuf) (cpu_to_le16(*(unsigned short *)(pbuf)) & (BIT(7) | BIT(6) | BIT(5) | BIT(4) | BIT(3) | BIT(2))) ++ ++#define SetFrameSubType(pbuf,type) \ ++ do { \ ++ *(unsigned short *)(pbuf) &= cpu_to_le16(~(BIT(7) | BIT(6) | BIT(5) | BIT(4) | BIT(3) | BIT(2))); \ ++ *(unsigned short *)(pbuf) |= cpu_to_le16(type); \ ++ } while(0) ++ ++#define GetSequence(pbuf) (cpu_to_le16(*(unsigned short *)((SIZE_PTR)(pbuf) + 22)) >> 4) ++ ++#define GetFragNum(pbuf) (cpu_to_le16(*(unsigned short *)((SIZE_PTR)(pbuf) + 22)) & 0x0f) ++ ++#define GetTupleCache(pbuf) (cpu_to_le16(*(unsigned short *)((SIZE_PTR)(pbuf) + 22))) ++ ++#define SetFragNum(pbuf, num) \ ++ do { \ ++ *(unsigned short *)((SIZE_PTR)(pbuf) + 22) = \ ++ ((*(unsigned short *)((SIZE_PTR)(pbuf) + 22)) & le16_to_cpu(~(0x000f))) | \ ++ cpu_to_le16(0x0f & (num)); \ ++ } while(0) ++ ++#define SetSeqNum(pbuf, num) \ ++ do { \ ++ *(unsigned short *)((SIZE_PTR)(pbuf) + 22) = \ ++ ((*(unsigned short *)((SIZE_PTR)(pbuf) + 22)) & le16_to_cpu((unsigned short)~0xfff0)) | \ ++ le16_to_cpu((unsigned short)(0xfff0 & (num << 4))); \ ++ } while(0) ++ ++#define SetDuration(pbuf, dur) \ ++ do { \ ++ *(unsigned short *)((SIZE_PTR)(pbuf) + 2) = cpu_to_le16(0xffff & (dur)); \ ++ } while(0) ++ ++ ++#define SetPriority(pbuf, tid) \ ++ do { \ ++ *(unsigned short *)(pbuf) |= cpu_to_le16(tid & 0xf); \ ++ } while(0) ++ ++#define GetPriority(pbuf) ((le16_to_cpu(*(unsigned short *)(pbuf))) & 0xf) ++ ++#define SetEOSP(pbuf, eosp) \ ++ do { \ ++ *(unsigned short *)(pbuf) |= cpu_to_le16( (eosp & 1) << 4); \ ++ } while(0) ++ ++#define SetAckpolicy(pbuf, ack) \ ++ do { \ ++ *(unsigned short *)(pbuf) |= cpu_to_le16( (ack & 3) << 5); \ ++ } while(0) ++ ++#define GetAckpolicy(pbuf) (((le16_to_cpu(*(unsigned short *)pbuf)) >> 5) & 0x3) ++ ++#define GetAMsdu(pbuf) (((le16_to_cpu(*(unsigned short *)pbuf)) >> 7) & 0x1) ++ ++#define SetAMsdu(pbuf, amsdu) \ ++ do { \ ++ *(unsigned short *)(pbuf) |= cpu_to_le16( (amsdu & 1) << 7); \ ++ } while(0) ++ ++#define GetAid(pbuf) (cpu_to_le16(*(unsigned short *)((SIZE_PTR)(pbuf) + 2)) & 0x3fff) ++ ++#define GetTid(pbuf) (cpu_to_le16(*(unsigned short *)((SIZE_PTR)(pbuf) + (((GetToDs(pbuf)<<1)|GetFrDs(pbuf))==3?30:24))) & 0x000f) ++ ++#define GetAddr1Ptr(pbuf) ((unsigned char *)((SIZE_PTR)(pbuf) + 4)) ++ ++#define GetAddr2Ptr(pbuf) ((unsigned char *)((SIZE_PTR)(pbuf) + 10)) ++ ++#define GetAddr3Ptr(pbuf) ((unsigned char *)((SIZE_PTR)(pbuf) + 16)) ++ ++#define GetAddr4Ptr(pbuf) ((unsigned char *)((SIZE_PTR)(pbuf) + 24)) ++ ++#define MacAddr_isBcst(addr) \ ++( \ ++ ( (addr[0] == 0xff) && (addr[1] == 0xff) && \ ++ (addr[2] == 0xff) && (addr[3] == 0xff) && \ ++ (addr[4] == 0xff) && (addr[5] == 0xff) ) ? _TRUE : _FALSE \ ++) ++ ++__inline static int IS_MCAST(unsigned char *da) ++{ ++ if ((*da) & 0x01) ++ return _TRUE; ++ else ++ return _FALSE; ++} ++ ++ ++__inline static unsigned char * get_da(unsigned char *pframe) ++{ ++ unsigned char *da; ++ unsigned int to_fr_ds = (GetToDs(pframe) << 1) | GetFrDs(pframe); ++ ++ switch (to_fr_ds) { ++ case 0x00: // ToDs=0, FromDs=0 ++ da = GetAddr1Ptr(pframe); ++ break; ++ case 0x01: // ToDs=0, FromDs=1 ++ da = GetAddr1Ptr(pframe); ++ break; ++ case 0x02: // ToDs=1, FromDs=0 ++ da = GetAddr3Ptr(pframe); ++ break; ++ default: // ToDs=1, FromDs=1 ++ da = GetAddr3Ptr(pframe); ++ break; ++ } ++ ++ return da; ++} ++ ++ ++__inline static unsigned char * get_sa(unsigned char *pframe) ++{ ++ unsigned char *sa; ++ unsigned int to_fr_ds = (GetToDs(pframe) << 1) | GetFrDs(pframe); ++ ++ switch (to_fr_ds) { ++ case 0x00: // ToDs=0, FromDs=0 ++ sa = GetAddr2Ptr(pframe); ++ break; ++ case 0x01: // ToDs=0, FromDs=1 ++ sa = GetAddr3Ptr(pframe); ++ break; ++ case 0x02: // ToDs=1, FromDs=0 ++ sa = GetAddr2Ptr(pframe); ++ break; ++ default: // ToDs=1, FromDs=1 ++ sa = GetAddr4Ptr(pframe); ++ break; ++ } ++ ++ return sa; ++} ++ ++__inline static unsigned char * get_hdr_bssid(unsigned char *pframe) ++{ ++ unsigned char *sa; ++ unsigned int to_fr_ds = (GetToDs(pframe) << 1) | GetFrDs(pframe); ++ ++ switch (to_fr_ds) { ++ case 0x00: // ToDs=0, FromDs=0 ++ sa = GetAddr3Ptr(pframe); ++ break; ++ case 0x01: // ToDs=0, FromDs=1 ++ sa = GetAddr2Ptr(pframe); ++ break; ++ case 0x02: // ToDs=1, FromDs=0 ++ sa = GetAddr1Ptr(pframe); ++ break; ++ case 0x03: // ToDs=1, FromDs=1 ++ sa = GetAddr1Ptr(pframe); ++ break; ++ default: ++ sa =NULL; //??????? ++ break; ++ } ++ ++ return sa; ++} ++ ++ ++__inline static int IsFrameTypeCtrl(unsigned char *pframe) ++{ ++ if(WIFI_CTRL_TYPE == GetFrameType(pframe)) ++ return _TRUE; ++ else ++ return _FALSE; ++} ++/*----------------------------------------------------------------------------- ++ Below is for the security related definition ++------------------------------------------------------------------------------*/ ++#define _RESERVED_FRAME_TYPE_ 0 ++#define _SKB_FRAME_TYPE_ 2 ++#define _PRE_ALLOCMEM_ 1 ++#define _PRE_ALLOCHDR_ 3 ++#define _PRE_ALLOCLLCHDR_ 4 ++#define _PRE_ALLOCICVHDR_ 5 ++#define _PRE_ALLOCMICHDR_ 6 ++ ++#define _SIFSTIME_ ((priv->pmib->dot11BssType.net_work_type&WIRELESS_11A)?16:10) ++#define _ACKCTSLNG_ 14 //14 bytes long, including crclng ++#define _CRCLNG_ 4 ++ ++#define _ASOCREQ_IE_OFFSET_ 4 // excluding wlan_hdr ++#define _ASOCRSP_IE_OFFSET_ 6 ++#define _REASOCREQ_IE_OFFSET_ 10 ++#define _REASOCRSP_IE_OFFSET_ 6 ++#define _PROBEREQ_IE_OFFSET_ 0 ++#define _PROBERSP_IE_OFFSET_ 12 ++#define _AUTH_IE_OFFSET_ 6 ++#define _DEAUTH_IE_OFFSET_ 0 ++#define _BEACON_IE_OFFSET_ 12 ++#define _PUBLIC_ACTION_IE_OFFSET_ 8 ++ ++#define _FIXED_IE_LENGTH_ _BEACON_IE_OFFSET_ ++ ++#define _SSID_IE_ 0 ++#define _SUPPORTEDRATES_IE_ 1 ++#define _DSSET_IE_ 3 ++#define _TIM_IE_ 5 ++#define _IBSS_PARA_IE_ 6 ++#define _COUNTRY_IE_ 7 ++#define _CHLGETXT_IE_ 16 ++#define _SUPPORTED_CH_IE_ 36 ++#define _CH_SWTICH_ANNOUNCE_ 37 //Secondary Channel Offset ++#define _RSN_IE_2_ 48 ++#define _SSN_IE_1_ 221 ++#define _ERPINFO_IE_ 42 ++#define _EXT_SUPPORTEDRATES_IE_ 50 ++ ++#define _HT_CAPABILITY_IE_ 45 ++#define _FTIE_ 55 ++#define _TIMEOUT_ITVL_IE_ 56 ++#define _HT_EXTRA_INFO_IE_ 61 ++#define _HT_ADD_INFO_IE_ 61 //_HT_EXTRA_INFO_IE_ ++ ++#define EID_BSSCoexistence 72 // 20/40 BSS Coexistence ++#define EID_BSSIntolerantChlReport 73 ++#define _RIC_Descriptor_IE_ 75 ++ ++#define _LINK_ID_IE_ 101 ++#define _CH_SWITCH_TIMING_ 104 ++#define _PTI_BUFFER_STATUS_ 106 ++#define _EXT_CAP_IE_ 127 ++#define _VENDOR_SPECIFIC_IE_ 221 ++ ++#define _RESERVED47_ 47 ++ ++/* --------------------------------------------------------------------------- ++ Below is the fixed elements... ++-----------------------------------------------------------------------------*/ ++#define _AUTH_ALGM_NUM_ 2 ++#define _AUTH_SEQ_NUM_ 2 ++#define _BEACON_ITERVAL_ 2 ++#define _CAPABILITY_ 2 ++#define _CURRENT_APADDR_ 6 ++#define _LISTEN_INTERVAL_ 2 ++#define _RSON_CODE_ 2 ++#define _ASOC_ID_ 2 ++#define _STATUS_CODE_ 2 ++#define _TIMESTAMP_ 8 ++ ++#define AUTH_ODD_TO 0 ++#define AUTH_EVEN_TO 1 ++ ++#define WLAN_ETHCONV_ENCAP 1 ++#define WLAN_ETHCONV_RFC1042 2 ++#define WLAN_ETHCONV_8021h 3 ++ ++#define cap_ESS BIT(0) ++#define cap_IBSS BIT(1) ++#define cap_CFPollable BIT(2) ++#define cap_CFRequest BIT(3) ++#define cap_Privacy BIT(4) ++#define cap_ShortPremble BIT(5) ++#define cap_PBCC BIT(6) ++#define cap_ChAgility BIT(7) ++#define cap_SpecMgmt BIT(8) ++#define cap_QoS BIT(9) ++#define cap_ShortSlot BIT(10) ++ ++/*----------------------------------------------------------------------------- ++ Below is the definition for 802.11i / 802.1x ++------------------------------------------------------------------------------*/ ++#define _IEEE8021X_MGT_ 1 // WPA ++#define _IEEE8021X_PSK_ 2 // WPA with pre-shared key ++ ++/* ++#define _NO_PRIVACY_ 0 ++#define _WEP_40_PRIVACY_ 1 ++#define _TKIP_PRIVACY_ 2 ++#define _WRAP_PRIVACY_ 3 ++#define _CCMP_PRIVACY_ 4 ++#define _WEP_104_PRIVACY_ 5 ++#define _WEP_WPA_MIXED_PRIVACY_ 6 // WEP + WPA ++*/ ++ ++/*----------------------------------------------------------------------------- ++ Below is the definition for WMM ++------------------------------------------------------------------------------*/ ++#define _WMM_IE_Length_ 7 // for WMM STA ++#define _WMM_Para_Element_Length_ 24 ++ ++ ++/*----------------------------------------------------------------------------- ++ Below is the definition for 802.11n ++------------------------------------------------------------------------------*/ ++ ++/* block-ack parameters */ ++#define IEEE80211_ADDBA_PARAM_POLICY_MASK 0x0002 ++#define IEEE80211_ADDBA_PARAM_TID_MASK 0x003C ++#define RTW_IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK 0xFFA0 ++#define IEEE80211_DELBA_PARAM_TID_MASK 0xF000 ++#define IEEE80211_DELBA_PARAM_INITIATOR_MASK 0x0800 ++ ++//#ifdef CONFIG_80211N_HT ++ ++#define SetOrderBit(pbuf) \ ++ do { \ ++ *(unsigned short *)(pbuf) |= cpu_to_le16(_ORDER_); \ ++ } while(0) ++ ++#define GetOrderBit(pbuf) (((*(unsigned short *)(pbuf)) & le16_to_cpu(_ORDER_)) != 0) ++ ++ ++/** ++ * struct ieee80211_bar - HT Block Ack Request ++ * ++ * This structure refers to "HT BlockAckReq" as ++ * described in 802.11n draft section 7.2.1.7.1 ++ */ ++ #if defined(PLATFORM_LINUX) || defined(CONFIG_RTL8712FW) ++struct rtw_ieee80211_bar { ++ unsigned short frame_control; ++ unsigned short duration; ++ unsigned char ra[6]; ++ unsigned char ta[6]; ++ unsigned short control; ++ unsigned short start_seq_num; ++} __attribute__((packed)); ++ #endif ++ ++/* 802.11 BAR control masks */ ++#define IEEE80211_BAR_CTRL_ACK_POLICY_NORMAL 0x0000 ++#define IEEE80211_BAR_CTRL_CBMTID_COMPRESSED_BA 0x0004 ++ ++ ++ #if defined(PLATFORM_LINUX) || defined(CONFIG_RTL8712FW) ++ ++ /** ++ * struct rtw_ieee80211_ht_cap - HT capabilities ++ * ++ * This structure refers to "HT capabilities element" as ++ * described in 802.11n draft section 7.3.2.52 ++ */ ++ ++struct rtw_ieee80211_ht_cap { ++ unsigned short cap_info; ++ unsigned char ampdu_params_info; ++ unsigned char supp_mcs_set[16]; ++ unsigned short extended_ht_cap_info; ++ unsigned int tx_BF_cap_info; ++ unsigned char antenna_selection_info; ++} __attribute__ ((packed)); ++ ++/** ++ * struct rtw_ieee80211_ht_cap - HT additional information ++ * ++ * This structure refers to "HT information element" as ++ * described in 802.11n draft section 7.3.2.53 ++ */ ++struct ieee80211_ht_addt_info { ++ unsigned char control_chan; ++ unsigned char ht_param; ++ unsigned short operation_mode; ++ unsigned short stbc_param; ++ unsigned char basic_set[16]; ++} __attribute__ ((packed)); ++ ++ ++struct HT_caps_element ++{ ++ union ++ { ++ struct ++ { ++ unsigned short HT_caps_info; ++ unsigned char AMPDU_para; ++ unsigned char MCS_rate[16]; ++ unsigned short HT_ext_caps; ++ unsigned int Beamforming_caps; ++ unsigned char ASEL_caps; ++ } HT_cap_element; ++ unsigned char HT_cap[26]; ++ }; ++} __attribute__ ((packed)); ++ ++struct HT_info_element ++{ ++ unsigned char primary_channel; ++ unsigned char infos[5]; ++ unsigned char MCS_rate[16]; ++} __attribute__ ((packed)); ++ ++struct AC_param ++{ ++ unsigned char ACI_AIFSN; ++ unsigned char CW; ++ unsigned short TXOP_limit; ++} __attribute__ ((packed)); ++ ++struct WMM_para_element ++{ ++ unsigned char QoS_info; ++ unsigned char reserved; ++ struct AC_param ac_param[4]; ++} __attribute__ ((packed)); ++ ++struct ADDBA_request ++{ ++ unsigned char dialog_token; ++ unsigned short BA_para_set; ++ unsigned short BA_timeout_value; ++ unsigned short BA_starting_seqctrl; ++} __attribute__ ((packed)); ++ ++ ++ ++#endif ++ ++ ++#ifdef PLATFORM_WINDOWS ++ ++#pragma pack(1) ++ ++struct rtw_ieee80211_ht_cap { ++ unsigned short cap_info; ++ unsigned char ampdu_params_info; ++ unsigned char supp_mcs_set[16]; ++ unsigned short extended_ht_cap_info; ++ unsigned int tx_BF_cap_info; ++ unsigned char antenna_selection_info; ++}; ++ ++ ++struct ieee80211_ht_addt_info { ++ unsigned char control_chan; ++ unsigned char ht_param; ++ unsigned short operation_mode; ++ unsigned short stbc_param; ++ unsigned char basic_set[16]; ++}; ++ ++struct HT_caps_element ++{ ++ union ++ { ++ struct ++ { ++ unsigned short HT_caps_info; ++ unsigned char AMPDU_para; ++ unsigned char MCS_rate[16]; ++ unsigned short HT_ext_caps; ++ unsigned int Beamforming_caps; ++ unsigned char ASEL_caps; ++ } HT_cap_element; ++ unsigned char HT_cap[26]; ++ }; ++}; ++ ++struct HT_info_element ++{ ++ unsigned char primary_channel; ++ unsigned char infos[5]; ++ unsigned char MCS_rate[16]; ++}; ++ ++struct AC_param ++{ ++ unsigned char ACI_AIFSN; ++ unsigned char CW; ++ unsigned short TXOP_limit; ++}; ++ ++struct WMM_para_element ++{ ++ unsigned char QoS_info; ++ unsigned char reserved; ++ struct AC_param ac_param[4]; ++}; ++ ++struct ADDBA_request ++{ ++ unsigned char dialog_token; ++ unsigned short BA_para_set; ++ unsigned short BA_timeout_value; ++ unsigned short BA_starting_seqctrl; ++}; ++ ++ ++#pragma pack() ++ ++#endif ++ ++ ++/* 802.11n HT capabilities masks */ ++#define IEEE80211_HT_CAP_SUP_WIDTH 0x0002 ++#define IEEE80211_HT_CAP_SM_PS 0x000C ++#define IEEE80211_HT_CAP_GRN_FLD 0x0010 ++#define IEEE80211_HT_CAP_SGI_20 0x0020 ++#define IEEE80211_HT_CAP_SGI_40 0x0040 ++#define IEEE80211_HT_CAP_TX_STBC 0x0080 ++#define IEEE80211_HT_CAP_RX_STBC 0x0300 ++#define IEEE80211_HT_CAP_DELAY_BA 0x0400 ++#define IEEE80211_HT_CAP_MAX_AMSDU 0x0800 ++#define IEEE80211_HT_CAP_DSSSCCK40 0x1000 ++/* 802.11n HT capability AMPDU settings */ ++#define IEEE80211_HT_CAP_AMPDU_FACTOR 0x03 ++#define IEEE80211_HT_CAP_AMPDU_DENSITY 0x1C ++/* 802.11n HT capability MSC set */ ++#define IEEE80211_SUPP_MCS_SET_UEQM 4 ++#define IEEE80211_HT_CAP_MAX_STREAMS 4 ++#define IEEE80211_SUPP_MCS_SET_LEN 10 ++/* maximum streams the spec allows */ ++#define IEEE80211_HT_CAP_MCS_TX_DEFINED 0x01 ++#define IEEE80211_HT_CAP_MCS_TX_RX_DIFF 0x02 ++#define IEEE80211_HT_CAP_MCS_TX_STREAMS 0x0C ++#define IEEE80211_HT_CAP_MCS_TX_UEQM 0x10 ++/* 802.11n HT IE masks */ ++#define IEEE80211_HT_IE_CHA_SEC_OFFSET 0x03 ++#define IEEE80211_HT_IE_CHA_SEC_NONE 0x00 ++#define IEEE80211_HT_IE_CHA_SEC_ABOVE 0x01 ++#define IEEE80211_HT_IE_CHA_SEC_BELOW 0x03 ++#define IEEE80211_HT_IE_CHA_WIDTH 0x04 ++#define IEEE80211_HT_IE_HT_PROTECTION 0x0003 ++#define IEEE80211_HT_IE_NON_GF_STA_PRSNT 0x0004 ++#define IEEE80211_HT_IE_NON_HT_STA_PRSNT 0x0010 ++ ++/* block-ack parameters */ ++#define IEEE80211_ADDBA_PARAM_POLICY_MASK 0x0002 ++#define IEEE80211_ADDBA_PARAM_TID_MASK 0x003C ++#define RTW_IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK 0xFFA0 ++#define IEEE80211_DELBA_PARAM_TID_MASK 0xF000 ++#define IEEE80211_DELBA_PARAM_INITIATOR_MASK 0x0800 ++ ++/* ++ * A-PMDU buffer sizes ++ * According to IEEE802.11n spec size varies from 8K to 64K (in powers of 2) ++ */ ++#define IEEE80211_MIN_AMPDU_BUF 0x8 ++#define IEEE80211_MAX_AMPDU_BUF 0x40 ++ ++ ++/* Spatial Multiplexing Power Save Modes */ ++#define WLAN_HT_CAP_SM_PS_STATIC 0 ++#define WLAN_HT_CAP_SM_PS_DYNAMIC 1 ++#define WLAN_HT_CAP_SM_PS_INVALID 2 ++#define WLAN_HT_CAP_SM_PS_DISABLED 3 ++ ++#ifdef CONFIG_AP_MODE ++#define OP_MODE_PURE 0 ++#define OP_MODE_MAY_BE_LEGACY_STAS 1 ++#define OP_MODE_20MHZ_HT_STA_ASSOCED 2 ++#define OP_MODE_MIXED 3 ++ ++#define HT_INFO_HT_PARAM_SECONDARY_CHNL_OFF_MASK ((u8) BIT(0) | BIT(1)) ++#define HT_INFO_HT_PARAM_SECONDARY_CHNL_ABOVE ((u8) BIT(0)) ++#define HT_INFO_HT_PARAM_SECONDARY_CHNL_BELOW ((u8) BIT(0) | BIT(1)) ++#define HT_INFO_HT_PARAM_REC_TRANS_CHNL_WIDTH ((u8) BIT(2)) ++#define HT_INFO_HT_PARAM_RIFS_MODE ((u8) BIT(3)) ++#define HT_INFO_HT_PARAM_CTRL_ACCESS_ONLY ((u8) BIT(4)) ++#define HT_INFO_HT_PARAM_SRV_INTERVAL_GRANULARITY ((u8) BIT(5)) ++ ++#define HT_INFO_OPERATION_MODE_OP_MODE_MASK \ ++ ((u16) (0x0001 | 0x0002)) ++#define HT_INFO_OPERATION_MODE_OP_MODE_OFFSET 0 ++#define HT_INFO_OPERATION_MODE_NON_GF_DEVS_PRESENT ((u8) BIT(2)) ++#define HT_INFO_OPERATION_MODE_TRANSMIT_BURST_LIMIT ((u8) BIT(3)) ++#define HT_INFO_OPERATION_MODE_NON_HT_STA_PRESENT ((u8) BIT(4)) ++ ++#define HT_INFO_STBC_PARAM_DUAL_BEACON ((u16) BIT(6)) ++#define HT_INFO_STBC_PARAM_DUAL_STBC_PROTECT ((u16) BIT(7)) ++#define HT_INFO_STBC_PARAM_SECONDARY_BCN ((u16) BIT(8)) ++#define HT_INFO_STBC_PARAM_LSIG_TXOP_PROTECT_ALLOWED ((u16) BIT(9)) ++#define HT_INFO_STBC_PARAM_PCO_ACTIVE ((u16) BIT(10)) ++#define HT_INFO_STBC_PARAM_PCO_PHASE ((u16) BIT(11)) ++#endif ++ ++ ++//#endif ++ ++// ===============WPS Section=============== ++// For WPSv1.0 ++#define WPSOUI 0x0050f204 ++// WPS attribute ID ++#define WPS_ATTR_VER1 0x104A ++#define WPS_ATTR_SIMPLE_CONF_STATE 0x1044 ++#define WPS_ATTR_RESP_TYPE 0x103B ++#define WPS_ATTR_UUID_E 0x1047 ++#define WPS_ATTR_MANUFACTURER 0x1021 ++#define WPS_ATTR_MODEL_NAME 0x1023 ++#define WPS_ATTR_MODEL_NUMBER 0x1024 ++#define WPS_ATTR_SERIAL_NUMBER 0x1042 ++#define WPS_ATTR_PRIMARY_DEV_TYPE 0x1054 ++#define WPS_ATTR_DEVICE_NAME 0x1011 ++#define WPS_ATTR_CONF_METHOD 0x1008 ++#define WPS_ATTR_RF_BANDS 0x103C ++#define WPS_ATTR_DEVICE_PWID 0x1012 ++#define WPS_ATTR_REQUEST_TYPE 0x103A ++#define WPS_ATTR_ASSOCIATION_STATE 0x1002 ++#define WPS_ATTR_CONFIG_ERROR 0x1009 ++#define WPS_ATTR_VENDOR_EXT 0x1049 ++#define WPA_ATTR_SELECTED_REGISTRAR 0x1041 ++ ++// Value of WPS attribute "WPS_ATTR_DEVICE_NAME ++#define WPS_MAX_DEVICE_NAME_LEN 32 ++ ++// Value of WPS Request Type Attribute ++#define WPS_REQ_TYPE_ENROLLEE_INFO_ONLY 0x00 ++#define WPS_REQ_TYPE_ENROLLEE_OPEN_8021X 0x01 ++#define WPS_REQ_TYPE_REGISTRAR 0x02 ++#define WPS_REQ_TYPE_WLAN_MANAGER_REGISTRAR 0x03 ++ ++// Value of WPS Response Type Attribute ++#define WPS_RESPONSE_TYPE_INFO_ONLY 0x00 ++#define WPS_RESPONSE_TYPE_8021X 0x01 ++#define WPS_RESPONSE_TYPE_REGISTRAR 0x02 ++#define WPS_RESPONSE_TYPE_AP 0x03 ++ ++// Value of WPS WiFi Simple Configuration State Attribute ++#define WPS_WSC_STATE_NOT_CONFIG 0x01 ++#define WPS_WSC_STATE_CONFIG 0x02 ++ ++// Value of WPS Version Attribute ++#define WPS_VERSION_1 0x10 ++ ++// Value of WPS Configuration Method Attribute ++#define WPS_CONFIG_METHOD_FLASH 0x0001 ++#define WPS_CONFIG_METHOD_ETHERNET 0x0002 ++#define WPS_CONFIG_METHOD_LABEL 0x0004 ++#define WPS_CONFIG_METHOD_DISPLAY 0x0008 ++#define WPS_CONFIG_METHOD_E_NFC 0x0010 ++#define WPS_CONFIG_METHOD_I_NFC 0x0020 ++#define WPS_CONFIG_METHOD_NFC 0x0040 ++#define WPS_CONFIG_METHOD_PBC 0x0080 ++#define WPS_CONFIG_METHOD_KEYPAD 0x0100 ++#define WPS_CONFIG_METHOD_VPBC 0x0280 ++#define WPS_CONFIG_METHOD_PPBC 0x0480 ++#define WPS_CONFIG_METHOD_VDISPLAY 0x2008 ++#define WPS_CONFIG_METHOD_PDISPLAY 0x4008 ++ ++// Value of Category ID of WPS Primary Device Type Attribute ++#define WPS_PDT_CID_MULIT_MEDIA 0x0008 ++#define WPS_PDT_CID_RTK_WIDI 0x001E ++ ++// Value of Sub Category ID of WPS Primary Device Type Attribute ++#define WPS_PDT_SCID_MEDIA_SERVER 0x0005 ++#define WPS_PDT_SCID_RTK_DMP 0x0001 ++ ++// Value of Device Password ID ++#define WPS_DPID_PIN 0x0000 ++#define WPS_DPID_USER_SPEC 0x0001 ++#define WPS_DPID_MACHINE_SPEC 0x0002 ++#define WPS_DPID_REKEY 0x0003 ++#define WPS_DPID_PBC 0x0004 ++#define WPS_DPID_REGISTRAR_SPEC 0x0005 ++ ++ ++// =====================P2P Section===================== ++// For P2P ++#define P2POUI 0x506F9A09 ++ ++// P2P Attribute ID ++#define P2P_ATTR_STATUS 0x00 ++#define P2P_ATTR_MINOR_REASON_CODE 0x01 ++#define P2P_ATTR_CAPABILITY 0x02 ++#define P2P_ATTR_DEVICE_ID 0x03 ++#define P2P_ATTR_GO_INTENT 0x04 ++#define P2P_ATTR_CONF_TIMEOUT 0x05 ++#define P2P_ATTR_LISTEN_CH 0x06 ++#define P2P_ATTR_GROUP_BSSID 0x07 ++#define P2P_ATTR_EX_LISTEN_TIMING 0x08 ++#define P2P_ATTR_INTENTED_IF_ADDR 0x09 ++#define P2P_ATTR_MANAGEABILITY 0x0A ++#define P2P_ATTR_CH_LIST 0x0B ++#define P2P_ATTR_NOA 0x0C ++#define P2P_ATTR_DEVICE_INFO 0x0D ++#define P2P_ATTR_GROUP_INFO 0x0E ++#define P2P_ATTR_GROUP_ID 0x0F ++#define P2P_ATTR_INTERFACE 0x10 ++#define P2P_ATTR_OPERATING_CH 0x11 ++#define P2P_ATTR_INVITATION_FLAGS 0x12 ++ ++// Value of Status Attribute ++#define P2P_STATUS_SUCCESS 0x00 ++#define P2P_STATUS_FAIL_INFO_UNAVAILABLE 0x01 ++#define P2P_STATUS_FAIL_INCOMPATIBLE_PARAM 0x02 ++#define P2P_STATUS_FAIL_LIMIT_REACHED 0x03 ++#define P2P_STATUS_FAIL_INVALID_PARAM 0x04 ++#define P2P_STATUS_FAIL_REQUEST_UNABLE 0x05 ++#define P2P_STATUS_FAIL_PREVOUS_PROTO_ERR 0x06 ++#define P2P_STATUS_FAIL_NO_COMMON_CH 0x07 ++#define P2P_STATUS_FAIL_UNKNOWN_P2PGROUP 0x08 ++#define P2P_STATUS_FAIL_BOTH_GOINTENT_15 0x09 ++#define P2P_STATUS_FAIL_INCOMPATIBLE_PROVSION 0x0A ++#define P2P_STATUS_FAIL_USER_REJECT 0x0B ++ ++// Value of Inviation Flags Attribute ++#define P2P_INVITATION_FLAGS_PERSISTENT BIT(0) ++ ++ ++// Value of Device Capability Bitmap ++#define P2P_DEVCAP_SERVICE_DISCOVERY BIT(0) ++#define P2P_DEVCAP_CLIENT_DISCOVERABILITY BIT(1) ++#define P2P_DEVCAP_CONCURRENT_OPERATION BIT(2) ++#define P2P_DEVCAP_INFRA_MANAGED BIT(3) ++#define P2P_DEVCAP_DEVICE_LIMIT BIT(4) ++#define P2P_DEVCAP_INVITATION_PROC BIT(5) ++ ++// Value of Group Capability Bitmap ++#define P2P_GRPCAP_GO BIT(0) ++#define P2P_GRPCAP_PERSISTENT_GROUP BIT(1) ++#define P2P_GRPCAP_GROUP_LIMIT BIT(2) ++#define P2P_GRPCAP_INTRABSS BIT(3) ++#define P2P_GRPCAP_CROSS_CONN BIT(4) ++#define P2P_GRPCAP_PERSISTENT_RECONN BIT(5) ++#define P2P_GRPCAP_GROUP_FORMATION BIT(6) ++ ++// P2P Public Action Frame ( Management Frame ) ++#define P2P_PUB_ACTION_ACTION 0x09 ++ ++// P2P Public Action Frame Type ++#define P2P_GO_NEGO_REQ 0 ++#define P2P_GO_NEGO_RESP 1 ++#define P2P_GO_NEGO_CONF 2 ++#define P2P_INVIT_REQ 3 ++#define P2P_INVIT_RESP 4 ++#define P2P_DEVDISC_REQ 5 ++#define P2P_DEVDISC_RESP 6 ++#define P2P_PROVISION_DISC_REQ 7 ++#define P2P_PROVISION_DISC_RESP 8 ++ ++// P2P Action Frame Type ++#define P2P_NOTICE_OF_ABSENCE 0 ++#define P2P_PRESENCE_REQUEST 1 ++#define P2P_PRESENCE_RESPONSE 2 ++#define P2P_GO_DISC_REQUEST 3 ++ ++ ++#define P2P_MAX_PERSISTENT_GROUP_NUM 10 ++ ++#define P2P_PROVISIONING_SCAN_CNT 3 ++ ++#define P2P_WILDCARD_SSID_LEN 7 ++#define P2P_FINDPHASE_EX_CNT 3 ++ ++#define P2P_PROVISION_TIMEOUT 5000 // 5 seconds timeout for sending the provision discovery request ++#define P2P_GO_NEGO_TIMEOUT 5000 // 5 seconds timeout for receiving the group negotation response ++#define P2P_TX_PRESCAN_TIMEOUT 100 // 100ms ++ ++#define P2P_MAX_INTENT 15 ++ ++#define P2P_MAX_NOA_NUM 2 ++ ++// WPS Configuration Method ++#define WPS_CM_NONE 0x0000 ++#define WPS_CM_LABEL 0x0004 ++#define WPS_CM_DISPLYA 0x0008 ++#define WPS_CM_EXTERNAL_NFC_TOKEN 0x0010 ++#define WPS_CM_INTEGRATED_NFC_TOKEN 0x0020 ++#define WPS_CM_NFC_INTERFACE 0x0040 ++#define WPS_CM_PUSH_BUTTON 0x0080 ++#define WPS_CM_KEYPAD 0x0100 ++#define WPS_CM_SW_PUHS_BUTTON 0x0280 ++#define WPS_CM_HW_PUHS_BUTTON 0x0480 ++#define WPS_CM_SW_DISPLAY_PIN 0x2008 ++#define WPS_CM_LCD_DISPLAY_PIN 0x4008 ++ ++enum P2P_ROLE { ++ P2P_ROLE_DISABLE = 0, ++ P2P_ROLE_DEVICE = 1, ++ P2P_ROLE_CLIENT = 2, ++ P2P_ROLE_GO = 3 ++}; ++ ++enum P2P_STATE { ++ P2P_STATE_NONE = 0, // P2P disable ++ P2P_STATE_IDLE = 1, // P2P had enabled and do nothing ++ P2P_STATE_LISTEN = 2, // In pure listen state ++ P2P_STATE_SCAN = 3, // In scan phase ++ P2P_STATE_FIND_PHASE_LISTEN = 4, // In the listen state of find phase ++ P2P_STATE_FIND_PHASE_SEARCH = 5, // In the search state of find phase ++ P2P_STATE_TX_PROVISION_DIS_REQ = 6, // In P2P provisioning discovery ++ P2P_STATE_RX_PROVISION_DIS_RSP = 7, ++ P2P_STATE_RX_PROVISION_DIS_REQ = 8, ++ P2P_STATE_GONEGO_ING = 9, // Doing the group owner negoitation handshake ++ P2P_STATE_GONEGO_OK = 10, // finish the group negoitation handshake with success ++ P2P_STATE_GONEGO_FAIL = 11, // finish the group negoitation handshake with failure ++ P2P_STATE_RECV_INVITE_REQ = 12, // receiving the P2P Inviation request ++ P2P_STATE_PROVISIONING_ING = 13, // Doing the P2P WPS ++ P2P_STATE_PROVISIONING_DONE = 14, // Finish the P2P WPS ++}; ++ ++enum P2P_WPSINFO { ++ P2P_NO_WPSINFO = 0, ++ P2P_GOT_WPSINFO_PEER_DISPLAY_PIN = 1, ++ P2P_GOT_WPSINFO_SELF_DISPLAY_PIN = 2, ++ P2P_GOT_WPSINFO_PBC = 3, ++}; ++ ++#define P2P_PRIVATE_IOCTL_SET_LEN 64 ++ ++enum P2P_PROTO_WK_ID ++{ ++ P2P_FIND_PHASE_WK = 0, ++ P2P_RESTORE_STATE_WK = 1, ++ P2P_PRE_TX_PROVDISC_PROCESS_WK = 2, ++ P2P_PRE_TX_NEGOREQ_PROCESS_WK = 3, ++ P2P_RO_CH_WK = 4, ++}; ++ ++enum P2P_PS ++{ ++ P2P_PS_DISABLE=0, ++ P2P_PS_ENABLE=1, ++ P2P_PS_SCAN=2, ++ P2P_PS_SCAN_DONE=3, ++ P2P_PS_ALLSTASLEEP=4, // for owner ++}; ++ ++// =====================WFD Section===================== ++// For Wi-Fi Display ++#define WFD_ATTR_DEVICE_INFO 0x00 ++#define WFD_ATTR_ASSOC_BSSID 0x01 ++#define WFD_ATTR_COUPLED_SINK_INFO 0x06 ++#define WFD_ATTR_SESSION_INFO 0x09 ++ ++// For WFD Device Information Attribute ++#define WFD_DEVINFO_SOURCE 0 ++#define WFD_DEVINFO_PRIARY_SINK 1 ++#define WFD_DEVINFO_SECARY_SINK 2 ++#define WFD_DEVINFO_SOURCE_PRIARY_SINK 3 ++ ++#define WFD_DEVINFO_NO_COUPLED_SINK 0 ++#define WFD_DEVINFO_COUPLED_SINK 4 ++ ++#ifdef CONFIG_TX_MCAST2UNI ++#define IP_MCAST_MAC(mac) ((mac[0]==0x01)&&(mac[1]==0x00)&&(mac[2]==0x5e)) ++#define ICMPV6_MCAST_MAC(mac) ((mac[0]==0x33)&&(mac[1]==0x33)&&(mac[2]!=0xff)) ++#endif // CONFIG_TX_MCAST2UNI ++ ++ ++ ++#endif // _WIFI_H_ ++ +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/include/wlan_bssdef.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/include/wlan_bssdef.h 2013-07-26 19:36:06.000000000 +0000 +@@ -0,0 +1,453 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ++******************************************************************************/ ++#ifndef __WLAN_BSSDEF_H__ ++#define __WLAN_BSSDEF_H__ ++ ++ ++#define MAX_IE_SZ 768 ++ ++ ++#ifdef PLATFORM_LINUX ++ ++#define NDIS_802_11_LENGTH_SSID 32 ++#define NDIS_802_11_LENGTH_RATES 8 ++#define NDIS_802_11_LENGTH_RATES_EX 16 ++ ++typedef unsigned char NDIS_802_11_MAC_ADDRESS[6]; ++typedef long NDIS_802_11_RSSI; // in dBm ++typedef unsigned char NDIS_802_11_RATES[NDIS_802_11_LENGTH_RATES]; // Set of 8 data rates ++typedef unsigned char NDIS_802_11_RATES_EX[NDIS_802_11_LENGTH_RATES_EX]; // Set of 16 data rates ++ ++ ++typedef ULONG NDIS_802_11_KEY_INDEX; ++typedef unsigned long long NDIS_802_11_KEY_RSC; ++ ++ ++typedef struct _NDIS_802_11_SSID ++{ ++ ULONG SsidLength; ++ UCHAR Ssid[32]; ++} NDIS_802_11_SSID, *PNDIS_802_11_SSID; ++ ++typedef enum _NDIS_802_11_NETWORK_TYPE ++{ ++ Ndis802_11FH, ++ Ndis802_11DS, ++ Ndis802_11OFDM5, ++ Ndis802_11OFDM24, ++ Ndis802_11NetworkTypeMax // not a real type, defined as an upper bound ++} NDIS_802_11_NETWORK_TYPE, *PNDIS_802_11_NETWORK_TYPE; ++ ++typedef struct _NDIS_802_11_CONFIGURATION_FH ++{ ++ ULONG Length; // Length of structure ++ ULONG HopPattern; // As defined by 802.11, MSB set ++ ULONG HopSet; // to one if non-802.11 ++ ULONG DwellTime; // units are Kusec ++} NDIS_802_11_CONFIGURATION_FH, *PNDIS_802_11_CONFIGURATION_FH; ++ ++ ++/* ++ FW will only save the channel number in DSConfig. ++ ODI Handler will convert the channel number to freq. number. ++*/ ++typedef struct _NDIS_802_11_CONFIGURATION ++{ ++ ULONG Length; // Length of structure ++ ULONG BeaconPeriod; // units are Kusec ++ ULONG ATIMWindow; // units are Kusec ++ ULONG DSConfig; // Frequency, units are kHz ++ NDIS_802_11_CONFIGURATION_FH FHConfig; ++} NDIS_802_11_CONFIGURATION, *PNDIS_802_11_CONFIGURATION; ++ ++ ++ ++typedef enum _NDIS_802_11_NETWORK_INFRASTRUCTURE ++{ ++ Ndis802_11IBSS, ++ Ndis802_11Infrastructure, ++ Ndis802_11AutoUnknown, ++ Ndis802_11InfrastructureMax, // Not a real value, defined as upper bound ++ Ndis802_11APMode ++} NDIS_802_11_NETWORK_INFRASTRUCTURE, *PNDIS_802_11_NETWORK_INFRASTRUCTURE; ++ ++ ++ ++ ++ ++typedef struct _NDIS_802_11_FIXED_IEs ++{ ++ UCHAR Timestamp[8]; ++ USHORT BeaconInterval; ++ USHORT Capabilities; ++} NDIS_802_11_FIXED_IEs, *PNDIS_802_11_FIXED_IEs; ++ ++ ++ ++typedef struct _NDIS_802_11_VARIABLE_IEs ++{ ++ UCHAR ElementID; ++ UCHAR Length; ++ UCHAR data[1]; ++} NDIS_802_11_VARIABLE_IEs, *PNDIS_802_11_VARIABLE_IEs; ++ ++ ++ ++/* ++ ++ ++ ++Length is the 4 bytes multiples of the sume of ++ sizeof (NDIS_802_11_MAC_ADDRESS) + 2 + sizeof (NDIS_802_11_SSID) + sizeof (ULONG) +++ sizeof (NDIS_802_11_RSSI) + sizeof (NDIS_802_11_NETWORK_TYPE) + sizeof (NDIS_802_11_CONFIGURATION) +++ sizeof (NDIS_802_11_RATES_EX) + IELength ++ ++Except the IELength, all other fields are fixed length. Therefore, we can define a marco to present the ++partial sum. ++ ++*/ ++#if 0 ++typedef struct _NDIS_WLAN_BSSID_EX ++{ ++ ULONG Length; ++ NDIS_802_11_MAC_ADDRESS MacAddress; ++ UCHAR Reserved[2];//[0]: IS beacon frame, [1]:optimum_antenna=>For antenna diversity; ++ NDIS_802_11_SSID Ssid; ++ ULONG Privacy; ++ NDIS_802_11_RSSI Rssi; ++ NDIS_802_11_NETWORK_TYPE NetworkTypeInUse; ++ NDIS_802_11_CONFIGURATION Configuration; ++ NDIS_802_11_NETWORK_INFRASTRUCTURE InfrastructureMode; ++ NDIS_802_11_RATES_EX SupportedRates; ++ ULONG IELength; ++ UCHAR IEs[MAX_IE_SZ]; //(timestamp, beacon interval, and capability information) ++} NDIS_WLAN_BSSID_EX, *PNDIS_WLAN_BSSID_EX; ++ ++ ++typedef struct _NDIS_802_11_BSSID_LIST_EX ++{ ++ ULONG NumberOfItems; ++ NDIS_WLAN_BSSID_EX Bssid[1]; ++} NDIS_802_11_BSSID_LIST_EX, *PNDIS_802_11_BSSID_LIST_EX; ++#endif ++ ++typedef enum _NDIS_802_11_AUTHENTICATION_MODE ++{ ++ Ndis802_11AuthModeOpen, ++ Ndis802_11AuthModeShared, ++ Ndis802_11AuthModeAutoSwitch, ++ Ndis802_11AuthModeWPA, ++ Ndis802_11AuthModeWPAPSK, ++ Ndis802_11AuthModeWPANone, ++ Ndis802_11AuthModeMax // Not a real mode, defined as upper bound ++} NDIS_802_11_AUTHENTICATION_MODE, *PNDIS_802_11_AUTHENTICATION_MODE; ++ ++typedef enum _NDIS_802_11_WEP_STATUS ++{ ++ Ndis802_11WEPEnabled, ++ Ndis802_11Encryption1Enabled = Ndis802_11WEPEnabled, ++ Ndis802_11WEPDisabled, ++ Ndis802_11EncryptionDisabled = Ndis802_11WEPDisabled, ++ Ndis802_11WEPKeyAbsent, ++ Ndis802_11Encryption1KeyAbsent = Ndis802_11WEPKeyAbsent, ++ Ndis802_11WEPNotSupported, ++ Ndis802_11EncryptionNotSupported = Ndis802_11WEPNotSupported, ++ Ndis802_11Encryption2Enabled, ++ Ndis802_11Encryption2KeyAbsent, ++ Ndis802_11Encryption3Enabled, ++ Ndis802_11Encryption3KeyAbsent ++} NDIS_802_11_WEP_STATUS, *PNDIS_802_11_WEP_STATUS, ++ NDIS_802_11_ENCRYPTION_STATUS, *PNDIS_802_11_ENCRYPTION_STATUS; ++ ++ ++#define NDIS_802_11_AI_REQFI_CAPABILITIES 1 ++#define NDIS_802_11_AI_REQFI_LISTENINTERVAL 2 ++#define NDIS_802_11_AI_REQFI_CURRENTAPADDRESS 4 ++ ++#define NDIS_802_11_AI_RESFI_CAPABILITIES 1 ++#define NDIS_802_11_AI_RESFI_STATUSCODE 2 ++#define NDIS_802_11_AI_RESFI_ASSOCIATIONID 4 ++ ++typedef struct _NDIS_802_11_AI_REQFI ++{ ++ USHORT Capabilities; ++ USHORT ListenInterval; ++ NDIS_802_11_MAC_ADDRESS CurrentAPAddress; ++} NDIS_802_11_AI_REQFI, *PNDIS_802_11_AI_REQFI; ++ ++typedef struct _NDIS_802_11_AI_RESFI ++{ ++ USHORT Capabilities; ++ USHORT StatusCode; ++ USHORT AssociationId; ++} NDIS_802_11_AI_RESFI, *PNDIS_802_11_AI_RESFI; ++ ++typedef struct _NDIS_802_11_ASSOCIATION_INFORMATION ++{ ++ ULONG Length; ++ USHORT AvailableRequestFixedIEs; ++ NDIS_802_11_AI_REQFI RequestFixedIEs; ++ ULONG RequestIELength; ++ ULONG OffsetRequestIEs; ++ USHORT AvailableResponseFixedIEs; ++ NDIS_802_11_AI_RESFI ResponseFixedIEs; ++ ULONG ResponseIELength; ++ ULONG OffsetResponseIEs; ++} NDIS_802_11_ASSOCIATION_INFORMATION, *PNDIS_802_11_ASSOCIATION_INFORMATION; ++ ++typedef enum _NDIS_802_11_RELOAD_DEFAULTS ++{ ++ Ndis802_11ReloadWEPKeys ++} NDIS_802_11_RELOAD_DEFAULTS, *PNDIS_802_11_RELOAD_DEFAULTS; ++ ++ ++// Key mapping keys require a BSSID ++typedef struct _NDIS_802_11_KEY ++{ ++ ULONG Length; // Length of this structure ++ ULONG KeyIndex; ++ ULONG KeyLength; // length of key in bytes ++ NDIS_802_11_MAC_ADDRESS BSSID; ++ NDIS_802_11_KEY_RSC KeyRSC; ++ UCHAR KeyMaterial[32]; // variable length depending on above field ++} NDIS_802_11_KEY, *PNDIS_802_11_KEY; ++ ++typedef struct _NDIS_802_11_REMOVE_KEY ++{ ++ ULONG Length; // Length of this structure ++ ULONG KeyIndex; ++ NDIS_802_11_MAC_ADDRESS BSSID; ++} NDIS_802_11_REMOVE_KEY, *PNDIS_802_11_REMOVE_KEY; ++ ++typedef struct _NDIS_802_11_WEP ++{ ++ ULONG Length; // Length of this structure ++ ULONG KeyIndex; // 0 is the per-client key, 1-N are the global keys ++ ULONG KeyLength; // length of key in bytes ++ UCHAR KeyMaterial[16];// variable length depending on above field ++} NDIS_802_11_WEP, *PNDIS_802_11_WEP; ++ ++typedef struct _NDIS_802_11_AUTHENTICATION_REQUEST ++{ ++ ULONG Length; // Length of structure ++ NDIS_802_11_MAC_ADDRESS Bssid; ++ ULONG Flags; ++} NDIS_802_11_AUTHENTICATION_REQUEST, *PNDIS_802_11_AUTHENTICATION_REQUEST; ++ ++typedef enum _NDIS_802_11_STATUS_TYPE ++{ ++ Ndis802_11StatusType_Authentication, ++ Ndis802_11StatusType_MediaStreamMode, ++ Ndis802_11StatusType_PMKID_CandidateList, ++ Ndis802_11StatusTypeMax // not a real type, defined as an upper bound ++} NDIS_802_11_STATUS_TYPE, *PNDIS_802_11_STATUS_TYPE; ++ ++typedef struct _NDIS_802_11_STATUS_INDICATION ++{ ++ NDIS_802_11_STATUS_TYPE StatusType; ++} NDIS_802_11_STATUS_INDICATION, *PNDIS_802_11_STATUS_INDICATION; ++ ++// mask for authentication/integrity fields ++#define NDIS_802_11_AUTH_REQUEST_AUTH_FIELDS 0x0f ++#define NDIS_802_11_AUTH_REQUEST_REAUTH 0x01 ++#define NDIS_802_11_AUTH_REQUEST_KEYUPDATE 0x02 ++#define NDIS_802_11_AUTH_REQUEST_PAIRWISE_ERROR 0x06 ++#define NDIS_802_11_AUTH_REQUEST_GROUP_ERROR 0x0E ++ ++// MIC check time, 60 seconds. ++#define MIC_CHECK_TIME 60000000 ++ ++typedef struct _NDIS_802_11_AUTHENTICATION_EVENT ++{ ++ NDIS_802_11_STATUS_INDICATION Status; ++ NDIS_802_11_AUTHENTICATION_REQUEST Request[1]; ++} NDIS_802_11_AUTHENTICATION_EVENT, *PNDIS_802_11_AUTHENTICATION_EVENT; ++ ++typedef struct _NDIS_802_11_TEST ++{ ++ ULONG Length; ++ ULONG Type; ++ union ++ { ++ NDIS_802_11_AUTHENTICATION_EVENT AuthenticationEvent; ++ NDIS_802_11_RSSI RssiTrigger; ++ }tt; ++} NDIS_802_11_TEST, *PNDIS_802_11_TEST; ++ ++ ++#endif //end of #ifdef PLATFORM_LINUX ++ ++#ifndef Ndis802_11APMode ++#define Ndis802_11APMode (Ndis802_11InfrastructureMax+1) ++#endif ++ ++typedef struct _WLAN_PHY_INFO ++{ ++ u8 SignalStrength;//(in percentage) ++ u8 SignalQuality;//(in percentage) ++ u8 Optimum_antenna; //for Antenna diversity ++ u8 Reserved_0; ++}WLAN_PHY_INFO,*PWLAN_PHY_INFO; ++ ++/* temporally add #pragma pack for structure alignment issue of ++* WLAN_BSSID_EX and get_WLAN_BSSID_EX_sz() ++*/ ++#ifdef PLATFORM_WINDOWS ++#pragma pack(push) ++#pragma pack(1) ++#endif ++typedef struct _WLAN_BSSID_EX ++{ ++ ULONG Length; ++ NDIS_802_11_MAC_ADDRESS MacAddress; ++ UCHAR Reserved[2];//[0]: IS beacon frame ++ NDIS_802_11_SSID Ssid; ++ ULONG Privacy; ++ NDIS_802_11_RSSI Rssi;//(in dBM,raw data ,get from PHY) ++ NDIS_802_11_NETWORK_TYPE NetworkTypeInUse; ++ NDIS_802_11_CONFIGURATION Configuration; ++ NDIS_802_11_NETWORK_INFRASTRUCTURE InfrastructureMode; ++ NDIS_802_11_RATES_EX SupportedRates; ++ WLAN_PHY_INFO PhyInfo; ++ ULONG IELength; ++ UCHAR IEs[MAX_IE_SZ]; //(timestamp, beacon interval, and capability information) ++} ++#ifndef PLATFORM_WINDOWS ++__attribute__((packed)) ++#endif ++WLAN_BSSID_EX, *PWLAN_BSSID_EX; ++#ifdef PLATFORM_WINDOWS ++#pragma pack(pop) ++#endif ++ ++__inline static uint get_WLAN_BSSID_EX_sz(WLAN_BSSID_EX *bss) ++{ ++ uint t_len; ++ ++ t_len = sizeof (ULONG) ++ + sizeof (NDIS_802_11_MAC_ADDRESS) ++ + 2 ++ + sizeof (NDIS_802_11_SSID) ++ + sizeof (ULONG) ++ + sizeof (NDIS_802_11_RSSI) ++ + sizeof (NDIS_802_11_NETWORK_TYPE) ++ + sizeof (NDIS_802_11_CONFIGURATION) ++ + sizeof (NDIS_802_11_NETWORK_INFRASTRUCTURE) ++ + sizeof (NDIS_802_11_RATES_EX) ++ //all new member add here ++ + sizeof(WLAN_PHY_INFO) ++ //all new member add here ++ + sizeof (ULONG) ++ + bss->IELength; ++ return t_len; ++ ++} ++ ++struct wlan_network { ++ _list list; ++ int network_type; //refer to ieee80211.h for WIRELESS_11A/B/G ++ int fixed; // set to fixed when not to be removed as site-surveying ++ unsigned long last_scanned; //timestamp for the network ++ int aid; //will only be valid when a BSS is joinned. ++ int join_res; ++ WLAN_BSSID_EX network; //must be the last item ++#ifdef PLATFORM_WINDOWS ++ unsigned char iebuf[MAX_IE_SZ]; ++#endif ++ ++}; ++ ++enum VRTL_CARRIER_SENSE ++{ ++ DISABLE_VCS, ++ ENABLE_VCS, ++ AUTO_VCS ++}; ++ ++enum VCS_TYPE ++{ ++ NONE_VCS, ++ RTS_CTS, ++ CTS_TO_SELF ++}; ++ ++ ++ ++ ++#define PWR_CAM 0 ++#define PWR_MINPS 1 ++#define PWR_MAXPS 2 ++#define PWR_UAPSD 3 ++#define PWR_VOIP 4 ++ ++ ++enum UAPSD_MAX_SP ++{ ++ NO_LIMIT, ++ TWO_MSDU, ++ FOUR_MSDU, ++ SIX_MSDU ++}; ++ ++ ++//john ++#define NUM_PRE_AUTH_KEY 16 ++#define NUM_PMKID_CACHE NUM_PRE_AUTH_KEY ++ ++/* ++* WPA2 ++*/ ++ ++#ifndef PLATFORM_OS_CE ++typedef struct _PMKID_CANDIDATE { ++ NDIS_802_11_MAC_ADDRESS BSSID; ++ ULONG Flags; ++} PMKID_CANDIDATE, *PPMKID_CANDIDATE; ++ ++typedef struct _NDIS_802_11_PMKID_CANDIDATE_LIST ++{ ++ ULONG Version; // Version of the structure ++ ULONG NumCandidates; // No. of pmkid candidates ++ PMKID_CANDIDATE CandidateList[1]; ++} NDIS_802_11_PMKID_CANDIDATE_LIST, *PNDIS_802_11_PMKID_CANDIDATE_LIST; ++ ++ ++typedef struct _NDIS_802_11_AUTHENTICATION_ENCRYPTION ++{ ++ NDIS_802_11_AUTHENTICATION_MODE AuthModeSupported; ++ NDIS_802_11_ENCRYPTION_STATUS EncryptStatusSupported; ++ ++} NDIS_802_11_AUTHENTICATION_ENCRYPTION, *PNDIS_802_11_AUTHENTICATION_ENCRYPTION; ++ ++typedef struct _NDIS_802_11_CAPABILITY ++{ ++ ULONG Length; ++ ULONG Version; ++ ULONG NoOfPMKIDs; ++ ULONG NoOfAuthEncryptPairsSupported; ++ NDIS_802_11_AUTHENTICATION_ENCRYPTION AuthenticationEncryptionSupported[1]; ++ ++} NDIS_802_11_CAPABILITY, *PNDIS_802_11_CAPABILITY; ++#endif ++ ++ ++#endif //#ifndef WLAN_BSSDEF_H_ ++ +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/include/xmit_osdep.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/include/xmit_osdep.h 2013-07-26 19:36:06.000000000 +0000 +@@ -0,0 +1,90 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ++******************************************************************************/ ++#ifndef __XMIT_OSDEP_H_ ++#define __XMIT_OSDEP_H_ ++ ++#include ++#include ++#include ++ ++struct pkt_file { ++ _pkt *pkt; ++ SIZE_T pkt_len; //the remainder length of the open_file ++ _buffer *cur_buffer; ++ u8 *buf_start; ++ u8 *cur_addr; ++ SIZE_T buf_len; ++}; ++ ++#ifdef PLATFORM_WINDOWS ++ ++#ifdef PLATFORM_OS_XP ++#ifdef CONFIG_USB_HCI ++#include ++#include ++#include ++#endif ++#endif ++ ++#define NR_XMITFRAME 128 ++ ++#define ETH_ALEN 6 ++ ++extern NDIS_STATUS rtw_xmit_entry( ++IN _nic_hdl cnxt, ++IN NDIS_PACKET *pkt, ++IN UINT flags ++); ++ ++#endif ++ ++ ++#ifdef PLATFORM_LINUX ++ ++#define NR_XMITFRAME 256 ++ ++struct xmit_priv; ++struct pkt_attrib; ++struct sta_xmit_priv; ++struct xmit_frame; ++struct xmit_buf; ++ ++extern int rtw_xmit_entry(_pkt *pkt, _nic_hdl pnetdev); ++ ++#endif ++ ++void rtw_os_xmit_schedule(_adapter *padapter); ++ ++int rtw_os_xmit_resource_alloc(_adapter *padapter, struct xmit_buf *pxmitbuf,u32 alloc_sz); ++void rtw_os_xmit_resource_free(_adapter *padapter, struct xmit_buf *pxmitbuf,u32 free_sz); ++ ++extern void rtw_set_tx_chksum_offload(_pkt *pkt, struct pkt_attrib *pattrib); ++ ++extern uint rtw_remainder_len(struct pkt_file *pfile); ++extern void _rtw_open_pktfile(_pkt *pkt, struct pkt_file *pfile); ++extern uint _rtw_pktfile_read (struct pkt_file *pfile, u8 *rmem, uint rlen); ++extern sint rtw_endofpktfile (struct pkt_file *pfile); ++ ++extern void rtw_os_pkt_complete(_adapter *padapter, _pkt *pkt); ++extern void rtw_os_xmit_complete(_adapter *padapter, struct xmit_frame *pxframe); ++ ++#endif // ++ +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/os_dep/linux/ioctl_cfg80211.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/os_dep/linux/ioctl_cfg80211.c 2013-07-26 19:36:06.000000000 +0000 +@@ -0,0 +1,4620 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#define _IOCTL_CFG80211_C_ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#ifdef CONFIG_IOCTL_CFG80211 ++ ++#include "ioctl_cfg80211.h" ++ ++#define RTW_SCAN_IE_LEN_MAX 2304 ++#define RTW_MAX_REMAIN_ON_CHANNEL_DURATION 65535 //ms ++#define RTW_MAX_NUM_PMKIDS 4 ++ ++#define RTW_CH_MAX_2G_CHANNEL 14 /* Max channel in 2G band */ ++ ++static const u32 rtw_cipher_suites[] = { ++ WLAN_CIPHER_SUITE_WEP40, ++ WLAN_CIPHER_SUITE_WEP104, ++ WLAN_CIPHER_SUITE_TKIP, ++ WLAN_CIPHER_SUITE_CCMP, ++}; ++ ++#define RATETAB_ENT(_rate, _rateid, _flags) \ ++ { \ ++ .bitrate = (_rate), \ ++ .hw_value = (_rateid), \ ++ .flags = (_flags), \ ++ } ++ ++#define CHAN2G(_channel, _freq, _flags) { \ ++ .band = IEEE80211_BAND_2GHZ, \ ++ .center_freq = (_freq), \ ++ .hw_value = (_channel), \ ++ .flags = (_flags), \ ++ .max_antenna_gain = 0, \ ++ .max_power = 30, \ ++} ++ ++#define CHAN5G(_channel, _flags) { \ ++ .band = IEEE80211_BAND_5GHZ, \ ++ .center_freq = 5000 + (5 * (_channel)), \ ++ .hw_value = (_channel), \ ++ .flags = (_flags), \ ++ .max_antenna_gain = 0, \ ++ .max_power = 30, \ ++} ++ ++static struct ieee80211_rate rtw_rates[] = { ++ RATETAB_ENT(10, 0x1, 0), ++ RATETAB_ENT(20, 0x2, 0), ++ RATETAB_ENT(55, 0x4, 0), ++ RATETAB_ENT(110, 0x8, 0), ++ RATETAB_ENT(60, 0x10, 0), ++ RATETAB_ENT(90, 0x20, 0), ++ RATETAB_ENT(120, 0x40, 0), ++ RATETAB_ENT(180, 0x80, 0), ++ RATETAB_ENT(240, 0x100, 0), ++ RATETAB_ENT(360, 0x200, 0), ++ RATETAB_ENT(480, 0x400, 0), ++ RATETAB_ENT(540, 0x800, 0), ++}; ++ ++#define rtw_a_rates (rtw_rates + 4) ++#define rtw_a_rates_size 8 ++#define rtw_g_rates (rtw_rates + 0) ++#define rtw_g_rates_size 12 ++ ++static struct ieee80211_channel rtw_2ghz_channels[] = { ++ CHAN2G(1, 2412, 0), ++ CHAN2G(2, 2417, 0), ++ CHAN2G(3, 2422, 0), ++ CHAN2G(4, 2427, 0), ++ CHAN2G(5, 2432, 0), ++ CHAN2G(6, 2437, 0), ++ CHAN2G(7, 2442, 0), ++ CHAN2G(8, 2447, 0), ++ CHAN2G(9, 2452, 0), ++ CHAN2G(10, 2457, 0), ++ CHAN2G(11, 2462, 0), ++ CHAN2G(12, 2467, 0), ++ CHAN2G(13, 2472, 0), ++ CHAN2G(14, 2484, 0), ++}; ++ ++//{{1,2,3,4,5,6,7,8,9,10,11,12,13,36,40,44,48,52,56,60,64,100,104,108,112,116,120,124,128,132,136,140,149,153,157,161,165},37}, // 0x12, RT_CHANNEL_DOMAIN_WORLD_WIDE37 ++ ++static struct ieee80211_channel rtw_5ghz_a_channels[] = { ++ CHAN5G(34, 0), CHAN5G(36, 0), ++ CHAN5G(38, 0), CHAN5G(40, 0), ++ CHAN5G(42, 0), CHAN5G(44, 0), ++ CHAN5G(46, 0), CHAN5G(48, 0), ++ CHAN5G(52, 0), CHAN5G(56, 0), ++ CHAN5G(60, 0), CHAN5G(64, 0), ++ CHAN5G(100, 0), CHAN5G(104, 0), ++ CHAN5G(108, 0), CHAN5G(112, 0), ++ CHAN5G(116, 0), CHAN5G(120, 0), ++ CHAN5G(124, 0), CHAN5G(128, 0), ++ CHAN5G(132, 0), CHAN5G(136, 0), ++ CHAN5G(140, 0), CHAN5G(149, 0), ++ CHAN5G(153, 0), CHAN5G(157, 0), ++ CHAN5G(161, 0), CHAN5G(165, 0), ++ CHAN5G(184, 0), CHAN5G(188, 0), ++ CHAN5G(192, 0), CHAN5G(196, 0), ++ CHAN5G(200, 0), CHAN5G(204, 0), ++ CHAN5G(208, 0), CHAN5G(212, 0), ++ CHAN5G(216, 0), ++}; ++ ++static struct ieee80211_supported_band rtw_band_2ghz = { ++ .band = IEEE80211_BAND_2GHZ, ++ .channels = rtw_2ghz_channels, ++ .n_channels = ARRAY_SIZE(rtw_2ghz_channels), ++ .bitrates = rtw_g_rates, ++ .n_bitrates = rtw_g_rates_size, ++}; ++ ++static struct ieee80211_supported_band rtw_band_5ghz = { ++ .band = IEEE80211_BAND_5GHZ, ++ .channels = rtw_5ghz_a_channels, ++ .n_channels = ARRAY_SIZE(rtw_5ghz_a_channels), ++ .bitrates = rtw_a_rates, ++ .n_bitrates = rtw_a_rates_size, ++}; ++ ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) ++static const struct ieee80211_txrx_stypes ++rtw_cfg80211_default_mgmt_stypes[NUM_NL80211_IFTYPES] = { ++ [NL80211_IFTYPE_ADHOC] = { ++ .tx = 0xffff, ++ .rx = BIT(IEEE80211_STYPE_ACTION >> 4) ++ }, ++ [NL80211_IFTYPE_STATION] = { ++ .tx = 0xffff, ++ .rx = BIT(IEEE80211_STYPE_ACTION >> 4) | ++ BIT(IEEE80211_STYPE_PROBE_REQ >> 4) ++ }, ++ [NL80211_IFTYPE_AP] = { ++ .tx = 0xffff, ++ .rx = BIT(IEEE80211_STYPE_ASSOC_REQ >> 4) | ++ BIT(IEEE80211_STYPE_REASSOC_REQ >> 4) | ++ BIT(IEEE80211_STYPE_PROBE_REQ >> 4) | ++ BIT(IEEE80211_STYPE_DISASSOC >> 4) | ++ BIT(IEEE80211_STYPE_AUTH >> 4) | ++ BIT(IEEE80211_STYPE_DEAUTH >> 4) | ++ BIT(IEEE80211_STYPE_ACTION >> 4) ++ }, ++ [NL80211_IFTYPE_AP_VLAN] = { ++ /* copy AP */ ++ .tx = 0xffff, ++ .rx = BIT(IEEE80211_STYPE_ASSOC_REQ >> 4) | ++ BIT(IEEE80211_STYPE_REASSOC_REQ >> 4) | ++ BIT(IEEE80211_STYPE_PROBE_REQ >> 4) | ++ BIT(IEEE80211_STYPE_DISASSOC >> 4) | ++ BIT(IEEE80211_STYPE_AUTH >> 4) | ++ BIT(IEEE80211_STYPE_DEAUTH >> 4) | ++ BIT(IEEE80211_STYPE_ACTION >> 4) ++ }, ++ [NL80211_IFTYPE_P2P_CLIENT] = { ++ .tx = 0xffff, ++ .rx = BIT(IEEE80211_STYPE_ACTION >> 4) | ++ BIT(IEEE80211_STYPE_PROBE_REQ >> 4) ++ }, ++ [NL80211_IFTYPE_P2P_GO] = { ++ .tx = 0xffff, ++ .rx = BIT(IEEE80211_STYPE_ASSOC_REQ >> 4) | ++ BIT(IEEE80211_STYPE_REASSOC_REQ >> 4) | ++ BIT(IEEE80211_STYPE_PROBE_REQ >> 4) | ++ BIT(IEEE80211_STYPE_DISASSOC >> 4) | ++ BIT(IEEE80211_STYPE_AUTH >> 4) | ++ BIT(IEEE80211_STYPE_DEAUTH >> 4) | ++ BIT(IEEE80211_STYPE_ACTION >> 4) ++ }, ++}; ++#endif ++ ++static int rtw_ieee80211_channel_to_frequency(int chan, int band) ++{ ++ /* see 802.11 17.3.8.3.2 and Annex J ++ * there are overlapping channel numbers in 5GHz and 2GHz bands */ ++ ++ if (band == IEEE80211_BAND_5GHZ) { ++ if (chan >= 182 && chan <= 196) ++ return 4000 + chan * 5; ++ else ++ return 5000 + chan * 5; ++ } else { /* IEEE80211_BAND_2GHZ */ ++ if (chan == 14) ++ return 2484; ++ else if (chan < 14) ++ return 2407 + chan * 5; ++ else ++ return 0; /* not supported */ ++ } ++} ++ ++static int rtw_cfg80211_inform_bss(_adapter *padapter, struct wlan_network *pnetwork) ++{ ++ int ret=0; ++ struct ieee80211_channel *notify_channel; ++ struct cfg80211_bss *bss; ++ //struct ieee80211_supported_band *band; ++ u16 channel; ++ u32 freq; ++ u64 notify_timestamp; ++ u16 notify_capability; ++ u16 notify_interval; ++ u8 *notify_ie; ++ size_t notify_ielen; ++ s32 notify_signal; ++ u8 buf[768], *pbuf; ++ size_t len; ++ struct rtw_ieee80211_hdr *pwlanhdr; ++ unsigned short *fctrl; ++ u8 bc_addr[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; ++ ++ struct wireless_dev *wdev = padapter->rtw_wdev; ++ struct wiphy *wiphy = wdev->wiphy; ++ ++ ++ //printk("%s\n", __func__); ++ ++ ++ channel = pnetwork->network.Configuration.DSConfig; ++ if (channel <= RTW_CH_MAX_2G_CHANNEL) ++ { ++ //band = wiphy->bands[IEEE80211_BAND_2GHZ]; ++ freq = rtw_ieee80211_channel_to_frequency(channel, IEEE80211_BAND_2GHZ); ++ } ++ else ++ { ++ //band = wiphy->bands[IEEE80211_BAND_5GHZ]; ++ freq = rtw_ieee80211_channel_to_frequency(channel, IEEE80211_BAND_5GHZ); ++ } ++ ++ notify_channel = ieee80211_get_channel(wiphy, freq); ++ ++ //rtw_get_timestampe_from_ie() ++ notify_timestamp = jiffies_to_msecs(jiffies)*1000; /* uSec */ ++ ++ notify_interval = le16_to_cpu(*(u16*)rtw_get_beacon_interval_from_ie(pnetwork->network.IEs)); ++ notify_capability = le16_to_cpu(*(u16*)rtw_get_capability_from_ie(pnetwork->network.IEs)); ++ ++ ++ notify_ie = pnetwork->network.IEs+_FIXED_IE_LENGTH_; ++ notify_ielen = pnetwork->network.IELength-_FIXED_IE_LENGTH_; ++ ++ //notify_signal = (s16)le16_to_cpu(bi->RSSI) * 100; ++ ++ //We've set wiphy's signal_type as CFG80211_SIGNAL_TYPE_MBM: signal strength in mBm (100*dBm) ++ notify_signal = 100*translate_percentage_to_dbm(pnetwork->network.PhyInfo.SignalStrength);//dbm ++ ++/* ++ printk("bssid: %2.2X:%2.2X:%2.2X:%2.2X:%2.2X:%2.2X\n", ++ pnetwork->network.MacAddress[0], pnetwork->network.MacAddress[1], pnetwork->network.MacAddress[2], ++ pnetwork->network.MacAddress[3], pnetwork->network.MacAddress[4], pnetwork->network.MacAddress[5]); ++ printk("Channel: %d(%d)\n", channel, freq); ++ printk("Capability: %X\n", notify_capability); ++ printk("Beacon interval: %d\n", notify_interval); ++ printk("Signal: %d\n", notify_signal); ++ printk("notify_timestamp: %#018llx\n", notify_timestamp); ++*/ ++ ++ pbuf = buf; ++ pwlanhdr = (struct rtw_ieee80211_hdr *)pbuf; ++ fctrl = &(pwlanhdr->frame_ctl); ++ *(fctrl) = 0; ++ ++ SetSeqNum(pwlanhdr, 0/*pmlmeext->mgnt_seq*/); ++ //pmlmeext->mgnt_seq++; ++ ++ if (pnetwork->network.Reserved[0] == 1) { // WIFI_BEACON ++ ++ _rtw_memcpy(pwlanhdr->addr1, bc_addr, ETH_ALEN); ++ ++ SetFrameSubType(pbuf, WIFI_BEACON); ++ ++ } else { ++ ++ _rtw_memcpy(pwlanhdr->addr1, myid(&(padapter->eeprompriv)), ETH_ALEN); ++ ++ SetFrameSubType(pbuf, WIFI_PROBERSP); ++ } ++ ++ _rtw_memcpy(pwlanhdr->addr2, pnetwork->network.MacAddress, ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr3, pnetwork->network.MacAddress, ETH_ALEN); ++ ++ ++ pbuf += sizeof(struct rtw_ieee80211_hdr_3addr); ++ len = sizeof (struct rtw_ieee80211_hdr_3addr); ++ ++ _rtw_memcpy(pbuf, pnetwork->network.IEs, pnetwork->network.IELength); ++ len += pnetwork->network.IELength; ++ ++ ++#if 1 ++ bss = cfg80211_inform_bss_frame(wiphy, notify_channel, (struct ieee80211_mgmt *)buf, ++ len, notify_signal, GFP_ATOMIC); ++#else ++ ++ bss = cfg80211_inform_bss(wiphy, notify_channel, (const u8 *)pnetwork->network.MacAddress, ++ notify_timestamp, notify_capability, notify_interval, notify_ie, ++ notify_ielen, notify_signal, GFP_ATOMIC/*GFP_KERNEL*/); ++#endif ++ ++ if (unlikely(!bss)) { ++ printk("rtw_cfg80211_inform_bss error\n"); ++ return -EINVAL; ++ } ++ ++ return ret; ++ ++} ++ ++void rtw_cfg80211_indicate_connect(_adapter *padapter) ++{ ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct wlan_network *cur_network = &(pmlmepriv->cur_network); ++ struct wireless_dev *pwdev = padapter->rtw_wdev; ++ struct wifidirect_info *pwdinfo= &(padapter->wdinfo); ++ ++ ++ printk("%s\n", __func__); ++ ++ if (pwdev->iftype != NL80211_IFTYPE_STATION ++ #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) ++ && pwdev->iftype != NL80211_IFTYPE_P2P_CLIENT ++ #endif ++ ) { ++ return; ++ } ++ ++ if(check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) ++ return; ++ ++ if(!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) ++ { ++ rtw_p2p_set_pre_state(pwdinfo, rtw_p2p_state(pwdinfo)); ++ rtw_p2p_set_role(pwdinfo, P2P_ROLE_CLIENT); ++ rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_OK); ++ printk("%s, role=%d, p2p_state=%d, pre_p2p_state=%d\n", __func__, rtw_p2p_role(pwdinfo), rtw_p2p_state(pwdinfo), rtw_p2p_pre_state(pwdinfo)); ++ } ++ ++ #ifdef CONFIG_LAYER2_ROAMING ++ if(pmlmepriv->to_roaming > 0) { ++ //rtw_cfg80211_inform_bss(padapter, cur_network); ++ DBG_871X("%s call cfg80211_roamed\n", __FUNCTION__); ++ cfg80211_roamed(padapter->pnetdev, ++ #if LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 39) ++ NULL, ++ #endif ++ cur_network->network.MacAddress, ++ cur_network->network.IEs+_FIXED_IE_LENGTH_, cur_network->network.IELength-_FIXED_IE_LENGTH_, ++ NULL, 0, GFP_ATOMIC ++ ); ++ } ++ else ++ #endif ++ { ++ cfg80211_connect_result(padapter->pnetdev, cur_network->network.MacAddress, NULL, 0, NULL, 0, ++ WLAN_STATUS_SUCCESS, GFP_ATOMIC/*GFP_KERNEL*/); ++ } ++} ++ ++void rtw_cfg80211_indicate_disconnect(_adapter *padapter) ++{ ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct wireless_dev *pwdev = padapter->rtw_wdev; ++ struct wifidirect_info *pwdinfo= &(padapter->wdinfo); ++ ++ printk("%s\n", __func__); ++ ++ if (pwdev->iftype != NL80211_IFTYPE_STATION ++ #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) ++ && pwdev->iftype != NL80211_IFTYPE_P2P_CLIENT ++ #endif ++ ) { ++ return; ++ } ++ ++ if(check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) ++ return; ++ ++ ++ if(!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) ++ { ++ _cancel_timer_ex( &pwdinfo->find_phase_timer ); ++ _cancel_timer_ex( &pwdinfo->restore_p2p_state_timer ); ++ _cancel_timer_ex( &pwdinfo->pre_tx_scan_timer); ++ ++ rtw_p2p_set_state(pwdinfo, rtw_p2p_pre_state(pwdinfo)); ++ rtw_p2p_set_role(pwdinfo, P2P_ROLE_DEVICE); ++ ++ printk("%s, role=%d, p2p_state=%d, pre_p2p_state=%d\n", __func__, rtw_p2p_role(pwdinfo), rtw_p2p_state(pwdinfo), rtw_p2p_pre_state(pwdinfo)); ++ } ++ ++ if(pwdev->sme_state==CFG80211_SME_CONNECTING) ++ cfg80211_connect_result(padapter->pnetdev, NULL, NULL, 0, NULL, 0, ++ WLAN_STATUS_UNSPECIFIED_FAILURE, GFP_ATOMIC/*GFP_KERNEL*/); ++ else if(pwdev->sme_state==CFG80211_SME_CONNECTED) ++ cfg80211_disconnected(padapter->pnetdev, 0, ++ NULL, 0, GFP_ATOMIC); ++ else ++ printk("pwdev->sme_state=%d\n", pwdev->sme_state); ++ ++} ++ ++ ++#ifdef CONFIG_AP_MODE ++static u8 set_pairwise_key(_adapter *padapter, struct sta_info *psta) ++{ ++ struct cmd_obj* ph2c; ++ struct set_stakey_parm *psetstakey_para; ++ struct cmd_priv *pcmdpriv=&padapter->cmdpriv; ++ u8 res=_SUCCESS; ++ ++ ph2c = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj)); ++ if ( ph2c == NULL){ ++ res= _FAIL; ++ goto exit; ++ } ++ ++ psetstakey_para = (struct set_stakey_parm*)rtw_zmalloc(sizeof(struct set_stakey_parm)); ++ if(psetstakey_para==NULL){ ++ rtw_mfree((u8 *) ph2c, sizeof(struct cmd_obj)); ++ res=_FAIL; ++ goto exit; ++ } ++ ++ init_h2fwcmd_w_parm_no_rsp(ph2c, psetstakey_para, _SetStaKey_CMD_); ++ ++ ++ psetstakey_para->algorithm = (u8)psta->dot118021XPrivacy; ++ ++ _rtw_memcpy(psetstakey_para->addr, psta->hwaddr, ETH_ALEN); ++ ++ _rtw_memcpy(psetstakey_para->key, &psta->dot118021x_UncstKey, 16); ++ ++ ++ res = rtw_enqueue_cmd(pcmdpriv, ph2c); ++ ++exit: ++ ++ return res; ++ ++} ++ ++static int set_group_key(_adapter *padapter, u8 *key, u8 alg, int keyid) ++{ ++ u8 keylen; ++ struct cmd_obj* pcmd; ++ struct setkey_parm *psetkeyparm; ++ struct cmd_priv *pcmdpriv=&(padapter->cmdpriv); ++ int res=_SUCCESS; ++ ++ DBG_8192C("%s\n", __FUNCTION__); ++ ++ pcmd = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj)); ++ if(pcmd==NULL){ ++ res= _FAIL; ++ goto exit; ++ } ++ psetkeyparm=(struct setkey_parm*)rtw_zmalloc(sizeof(struct setkey_parm)); ++ if(psetkeyparm==NULL){ ++ rtw_mfree((unsigned char *)pcmd, sizeof(struct cmd_obj)); ++ res= _FAIL; ++ goto exit; ++ } ++ ++ _rtw_memset(psetkeyparm, 0, sizeof(struct setkey_parm)); ++ ++ psetkeyparm->keyid=(u8)keyid; ++ ++ psetkeyparm->algorithm = alg; ++ ++ psetkeyparm->set_tx = 1; ++ ++ switch(alg) ++ { ++ case _WEP40_: ++ keylen = 5; ++ break; ++ case _WEP104_: ++ keylen = 13; ++ break; ++ case _TKIP_: ++ case _TKIP_WTMIC_: ++ case _AES_: ++ keylen = 16; ++ default: ++ keylen = 16; ++ } ++ ++ _rtw_memcpy(&(psetkeyparm->key[0]), key, keylen); ++ ++ pcmd->cmdcode = _SetKey_CMD_; ++ pcmd->parmbuf = (u8 *)psetkeyparm; ++ pcmd->cmdsz = (sizeof(struct setkey_parm)); ++ pcmd->rsp = NULL; ++ pcmd->rspsz = 0; ++ ++ ++ _rtw_init_listhead(&pcmd->list); ++ ++ res = rtw_enqueue_cmd(pcmdpriv, pcmd); ++ ++exit: ++ ++ return res; ++ ++ ++} ++ ++static int set_wep_key(_adapter *padapter, u8 *key, u8 keylen, int keyid) ++{ ++ u8 alg; ++ ++ switch(keylen) ++ { ++ case 5: ++ alg =_WEP40_; ++ break; ++ case 13: ++ alg =_WEP104_; ++ break; ++ default: ++ alg =_NO_PRIVACY_; ++ } ++ ++ return set_group_key(padapter, key, alg, keyid); ++ ++} ++ ++static int rtw_cfg80211_ap_set_encryption(struct net_device *dev, struct ieee_param *param, u32 param_len) ++{ ++ int ret = 0; ++ u32 wep_key_idx, wep_key_len,wep_total_len; ++ NDIS_802_11_WEP *pwep = NULL; ++ struct sta_info *psta = NULL, *pbcmc_sta = NULL; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct security_priv* psecuritypriv=&(padapter->securitypriv); ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ ++ DBG_8192C("%s\n", __FUNCTION__); ++ ++ param->u.crypt.err = 0; ++ param->u.crypt.alg[IEEE_CRYPT_ALG_NAME_LEN - 1] = '\0'; ++ ++ //sizeof(struct ieee_param) = 64 bytes; ++ //if (param_len != (u32) ((u8 *) param->u.crypt.key - (u8 *) param) + param->u.crypt.key_len) ++ if (param_len != sizeof(struct ieee_param) + param->u.crypt.key_len) ++ { ++ ret = -EINVAL; ++ goto exit; ++ } ++ ++ if (param->sta_addr[0] == 0xff && param->sta_addr[1] == 0xff && ++ param->sta_addr[2] == 0xff && param->sta_addr[3] == 0xff && ++ param->sta_addr[4] == 0xff && param->sta_addr[5] == 0xff) ++ { ++ if (param->u.crypt.idx >= WEP_KEYS) ++ { ++ ret = -EINVAL; ++ goto exit; ++ } ++ } ++ else ++ { ++ psta = rtw_get_stainfo(pstapriv, param->sta_addr); ++ if(!psta) ++ { ++ //ret = -EINVAL; ++ DBG_8192C("rtw_set_encryption(), sta has already been removed or never been added\n"); ++ goto exit; ++ } ++ } ++ ++ if (strcmp(param->u.crypt.alg, "none") == 0 && (psta==NULL)) ++ { ++ //todo:clear default encryption keys ++ ++ DBG_8192C("clear default encryption keys, keyid=%d\n", param->u.crypt.idx); ++ ++ goto exit; ++ } ++ ++ ++ if (strcmp(param->u.crypt.alg, "WEP") == 0 && (psta==NULL)) ++ { ++ DBG_8192C("r871x_set_encryption, crypt.alg = WEP\n"); ++ ++ wep_key_idx = param->u.crypt.idx; ++ wep_key_len = param->u.crypt.key_len; ++ ++ DBG_8192C("r871x_set_encryption, wep_key_idx=%d, len=%d\n", wep_key_idx, wep_key_len); ++ ++ if((wep_key_idx >= WEP_KEYS) || (wep_key_len<=0)) ++ { ++ ret = -EINVAL; ++ goto exit; ++ } ++ ++ ++ if (wep_key_len > 0) ++ { ++ wep_key_len = wep_key_len <= 5 ? 5 : 13; ++ wep_total_len = wep_key_len + FIELD_OFFSET(NDIS_802_11_WEP, KeyMaterial); ++ pwep =(NDIS_802_11_WEP *)rtw_malloc(wep_total_len); ++ if(pwep == NULL){ ++ DBG_8192C(" r871x_set_encryption: pwep allocate fail !!!\n"); ++ goto exit; ++ } ++ ++ _rtw_memset(pwep, 0, wep_total_len); ++ ++ pwep->KeyLength = wep_key_len; ++ pwep->Length = wep_total_len; ++ ++ } ++ ++ pwep->KeyIndex = wep_key_idx; ++ ++ _rtw_memcpy(pwep->KeyMaterial, param->u.crypt.key, pwep->KeyLength); ++ ++ if(param->u.crypt.set_tx) ++ { ++ DBG_8192C("wep, set_tx=1\n"); ++ ++ psecuritypriv->ndisencryptstatus = Ndis802_11Encryption1Enabled; ++ psecuritypriv->dot11PrivacyAlgrthm=_WEP40_; ++ psecuritypriv->dot118021XGrpPrivacy=_WEP40_; ++ ++ if(pwep->KeyLength==13) ++ { ++ psecuritypriv->dot11PrivacyAlgrthm=_WEP104_; ++ psecuritypriv->dot118021XGrpPrivacy=_WEP104_; ++ } ++ ++ ++ psecuritypriv->dot11PrivacyKeyIndex = wep_key_idx; ++ ++ _rtw_memcpy(&(psecuritypriv->dot11DefKey[wep_key_idx].skey[0]), pwep->KeyMaterial, pwep->KeyLength); ++ ++ psecuritypriv->dot11DefKeylen[wep_key_idx]=pwep->KeyLength; ++ ++ set_wep_key(padapter, pwep->KeyMaterial, pwep->KeyLength, wep_key_idx); ++ ++ ++ } ++ else ++ { ++ DBG_8192C("wep, set_tx=0\n"); ++ ++ //don't update "psecuritypriv->dot11PrivacyAlgrthm" and ++ //"psecuritypriv->dot11PrivacyKeyIndex=keyid", but can rtw_set_key to cam ++ ++ _rtw_memcpy(&(psecuritypriv->dot11DefKey[wep_key_idx].skey[0]), pwep->KeyMaterial, pwep->KeyLength); ++ ++ psecuritypriv->dot11DefKeylen[wep_key_idx] = pwep->KeyLength; ++ ++ set_wep_key(padapter, pwep->KeyMaterial, pwep->KeyLength, wep_key_idx); ++ ++ } ++ ++ goto exit; ++ ++ } ++ ++ ++ if(!psta && check_fwstate(pmlmepriv, WIFI_AP_STATE)) // //group key ++ { ++ //if(param->u.crypt.set_tx == 1) ++ if(param->u.crypt.set_tx == 0) ++ { ++ if(strcmp(param->u.crypt.alg, "WEP") == 0) ++ { ++ DBG_8192C("%s, set group_key, WEP\n", __FUNCTION__); ++ ++ _rtw_memcpy(psecuritypriv->dot118021XGrpKey[param->u.crypt.idx].skey, param->u.crypt.key, (param->u.crypt.key_len>16 ?16:param->u.crypt.key_len)); ++ ++ psecuritypriv->dot118021XGrpPrivacy = _WEP40_; ++ if(param->u.crypt.key_len==13) ++ { ++ psecuritypriv->dot118021XGrpPrivacy = _WEP104_; ++ } ++ ++ } ++ else if(strcmp(param->u.crypt.alg, "TKIP") == 0) ++ { ++ DBG_8192C("%s, set group_key, TKIP\n", __FUNCTION__); ++ ++ psecuritypriv->dot118021XGrpPrivacy = _TKIP_; ++ ++ _rtw_memcpy(psecuritypriv->dot118021XGrpKey[param->u.crypt.idx].skey, param->u.crypt.key, (param->u.crypt.key_len>16 ?16:param->u.crypt.key_len)); ++ ++ //DEBUG_ERR("set key length :param->u.crypt.key_len=%d\n", param->u.crypt.key_len); ++ //set mic key ++ _rtw_memcpy(psecuritypriv->dot118021XGrptxmickey[param->u.crypt.idx].skey, &(param->u.crypt.key[16]), 8); ++ _rtw_memcpy(psecuritypriv->dot118021XGrprxmickey[param->u.crypt.idx].skey, &(param->u.crypt.key[24]), 8); ++ ++ psecuritypriv->busetkipkey = _TRUE; ++ ++ } ++ else if(strcmp(param->u.crypt.alg, "CCMP") == 0) ++ { ++ DBG_8192C("%s, set group_key, CCMP\n", __FUNCTION__); ++ ++ psecuritypriv->dot118021XGrpPrivacy = _AES_; ++ ++ _rtw_memcpy(psecuritypriv->dot118021XGrpKey[param->u.crypt.idx].skey, param->u.crypt.key, (param->u.crypt.key_len>16 ?16:param->u.crypt.key_len)); ++ } ++ else ++ { ++ DBG_8192C("%s, set group_key, none\n", __FUNCTION__); ++ ++ psecuritypriv->dot118021XGrpPrivacy = _NO_PRIVACY_; ++ } ++ ++ psecuritypriv->dot118021XGrpKeyid = param->u.crypt.idx; ++ ++ psecuritypriv->binstallGrpkey = _TRUE; ++ ++ psecuritypriv->dot11PrivacyAlgrthm = psecuritypriv->dot118021XGrpPrivacy;//!!! ++ ++ set_group_key(padapter, param->u.crypt.key, psecuritypriv->dot118021XGrpPrivacy, param->u.crypt.idx); ++ ++ pbcmc_sta=rtw_get_bcmc_stainfo(padapter); ++ if(pbcmc_sta) ++ { ++ pbcmc_sta->ieee8021x_blocked = _FALSE; ++ pbcmc_sta->dot118021XPrivacy= psecuritypriv->dot118021XGrpPrivacy;//rx will use bmc_sta's dot118021XPrivacy ++ } ++ ++ } ++ ++ goto exit; ++ ++ } ++ ++ if(psecuritypriv->dot11AuthAlgrthm == dot11AuthAlgrthm_8021X && psta) // psk/802_1x ++ { ++ if(check_fwstate(pmlmepriv, WIFI_AP_STATE)) ++ { ++ if(param->u.crypt.set_tx ==1) ++ { ++ _rtw_memcpy(psta->dot118021x_UncstKey.skey, param->u.crypt.key, (param->u.crypt.key_len>16 ?16:param->u.crypt.key_len)); ++ ++ if(strcmp(param->u.crypt.alg, "WEP") == 0) ++ { ++ DBG_8192C("%s, set pairwise key, WEP\n", __FUNCTION__); ++ ++ psta->dot118021XPrivacy = _WEP40_; ++ if(param->u.crypt.key_len==13) ++ { ++ psta->dot118021XPrivacy = _WEP104_; ++ } ++ } ++ else if(strcmp(param->u.crypt.alg, "TKIP") == 0) ++ { ++ DBG_8192C("%s, set pairwise key, TKIP\n", __FUNCTION__); ++ ++ psta->dot118021XPrivacy = _TKIP_; ++ ++ //DEBUG_ERR("set key length :param->u.crypt.key_len=%d\n", param->u.crypt.key_len); ++ //set mic key ++ _rtw_memcpy(psta->dot11tkiptxmickey.skey, &(param->u.crypt.key[16]), 8); ++ _rtw_memcpy(psta->dot11tkiprxmickey.skey, &(param->u.crypt.key[24]), 8); ++ ++ psecuritypriv->busetkipkey = _TRUE; ++ ++ } ++ else if(strcmp(param->u.crypt.alg, "CCMP") == 0) ++ { ++ ++ DBG_8192C("%s, set pairwise key, CCMP\n", __FUNCTION__); ++ ++ psta->dot118021XPrivacy = _AES_; ++ } ++ else ++ { ++ DBG_8192C("%s, set pairwise key, none\n", __FUNCTION__); ++ ++ psta->dot118021XPrivacy = _NO_PRIVACY_; ++ } ++ ++ set_pairwise_key(padapter, psta); ++ ++ psta->ieee8021x_blocked = _FALSE; ++ ++ psta->bpairwise_key_installed = _TRUE; ++ ++ } ++ else//group key??? ++ { ++ if(strcmp(param->u.crypt.alg, "WEP") == 0) ++ { ++ _rtw_memcpy(psecuritypriv->dot118021XGrpKey[param->u.crypt.idx].skey, param->u.crypt.key, (param->u.crypt.key_len>16 ?16:param->u.crypt.key_len)); ++ ++ psecuritypriv->dot118021XGrpPrivacy = _WEP40_; ++ if(param->u.crypt.key_len==13) ++ { ++ psecuritypriv->dot118021XGrpPrivacy = _WEP104_; ++ } ++ } ++ else if(strcmp(param->u.crypt.alg, "TKIP") == 0) ++ { ++ psecuritypriv->dot118021XGrpPrivacy = _TKIP_; ++ ++ _rtw_memcpy(psecuritypriv->dot118021XGrpKey[param->u.crypt.idx].skey, param->u.crypt.key, (param->u.crypt.key_len>16 ?16:param->u.crypt.key_len)); ++ ++ //DEBUG_ERR("set key length :param->u.crypt.key_len=%d\n", param->u.crypt.key_len); ++ //set mic key ++ _rtw_memcpy(psecuritypriv->dot118021XGrptxmickey[param->u.crypt.idx].skey, &(param->u.crypt.key[16]), 8); ++ _rtw_memcpy(psecuritypriv->dot118021XGrprxmickey[param->u.crypt.idx].skey, &(param->u.crypt.key[24]), 8); ++ ++ psecuritypriv->busetkipkey = _TRUE; ++ ++ } ++ else if(strcmp(param->u.crypt.alg, "CCMP") == 0) ++ { ++ psecuritypriv->dot118021XGrpPrivacy = _AES_; ++ ++ _rtw_memcpy(psecuritypriv->dot118021XGrpKey[param->u.crypt.idx].skey, param->u.crypt.key, (param->u.crypt.key_len>16 ?16:param->u.crypt.key_len)); ++ } ++ else ++ { ++ psecuritypriv->dot118021XGrpPrivacy = _NO_PRIVACY_; ++ } ++ ++ psecuritypriv->dot118021XGrpKeyid = param->u.crypt.idx; ++ ++ psecuritypriv->binstallGrpkey = _TRUE; ++ ++ psecuritypriv->dot11PrivacyAlgrthm = psecuritypriv->dot118021XGrpPrivacy;//!!! ++ ++ set_group_key(padapter, param->u.crypt.key, psecuritypriv->dot118021XGrpPrivacy, param->u.crypt.idx); ++ ++ pbcmc_sta=rtw_get_bcmc_stainfo(padapter); ++ if(pbcmc_sta) ++ { ++ pbcmc_sta->ieee8021x_blocked = _FALSE; ++ pbcmc_sta->dot118021XPrivacy= psecuritypriv->dot118021XGrpPrivacy;//rx will use bmc_sta's dot118021XPrivacy ++ } ++ ++ } ++ ++ } ++ ++ } ++ ++exit: ++ ++ if(pwep) ++ { ++ rtw_mfree((u8 *)pwep, wep_total_len); ++ } ++ ++ return ret; ++ ++} ++#endif ++ ++static int rtw_cfg80211_set_encryption(struct net_device *dev, struct ieee_param *param, u32 param_len) ++{ ++ int ret = 0; ++ u32 wep_key_idx, wep_key_len,wep_total_len; ++ NDIS_802_11_WEP *pwep = NULL; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct security_priv *psecuritypriv = &padapter->securitypriv; ++#ifdef CONFIG_P2P ++ struct wifidirect_info* pwdinfo = &padapter->wdinfo; ++#endif //CONFIG_P2P ++ ++_func_enter_; ++ ++ printk("%s\n", __func__); ++ ++ param->u.crypt.err = 0; ++ param->u.crypt.alg[IEEE_CRYPT_ALG_NAME_LEN - 1] = '\0'; ++ ++ if (param_len < (u32) ((u8 *) param->u.crypt.key - (u8 *) param) + param->u.crypt.key_len) ++ { ++ ret = -EINVAL; ++ goto exit; ++ } ++ ++ if (param->sta_addr[0] == 0xff && param->sta_addr[1] == 0xff && ++ param->sta_addr[2] == 0xff && param->sta_addr[3] == 0xff && ++ param->sta_addr[4] == 0xff && param->sta_addr[5] == 0xff) ++ { ++ if (param->u.crypt.idx >= WEP_KEYS) ++ { ++ ret = -EINVAL; ++ goto exit; ++ } ++ } else { ++ ret = -EINVAL; ++ goto exit; ++ } ++ ++ if (strcmp(param->u.crypt.alg, "WEP") == 0) ++ { ++ RT_TRACE(_module_rtl871x_ioctl_os_c,_drv_err_,("wpa_set_encryption, crypt.alg = WEP\n")); ++ DBG_8192C("wpa_set_encryption, crypt.alg = WEP\n"); ++ ++ padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption1Enabled; ++ padapter->securitypriv.dot11PrivacyAlgrthm=_WEP40_; ++ padapter->securitypriv.dot118021XGrpPrivacy=_WEP40_; ++ ++ wep_key_idx = param->u.crypt.idx; ++ wep_key_len = param->u.crypt.key_len; ++ ++ RT_TRACE(_module_rtl871x_ioctl_os_c,_drv_info_,("(1)wep_key_idx=%d\n", wep_key_idx)); ++ DBG_8192C("(1)wep_key_idx=%d\n", wep_key_idx); ++ ++ if (wep_key_idx > WEP_KEYS) ++ return -EINVAL; ++ ++ RT_TRACE(_module_rtl871x_ioctl_os_c,_drv_info_,("(2)wep_key_idx=%d\n", wep_key_idx)); ++ ++ if (wep_key_len > 0) ++ { ++ wep_key_len = wep_key_len <= 5 ? 5 : 13; ++ wep_total_len = wep_key_len + FIELD_OFFSET(NDIS_802_11_WEP, KeyMaterial); ++ pwep =(NDIS_802_11_WEP *) rtw_malloc(wep_total_len); ++ if(pwep == NULL){ ++ RT_TRACE(_module_rtl871x_ioctl_os_c,_drv_err_,(" wpa_set_encryption: pwep allocate fail !!!\n")); ++ goto exit; ++ } ++ ++ _rtw_memset(pwep, 0, wep_total_len); ++ ++ pwep->KeyLength = wep_key_len; ++ pwep->Length = wep_total_len; ++ ++ if(wep_key_len==13) ++ { ++ padapter->securitypriv.dot11PrivacyAlgrthm=_WEP104_; ++ padapter->securitypriv.dot118021XGrpPrivacy=_WEP104_; ++ } ++ } ++ else { ++ ret = -EINVAL; ++ goto exit; ++ } ++ ++ pwep->KeyIndex = wep_key_idx; ++ pwep->KeyIndex |= 0x80000000; ++ ++ _rtw_memcpy(pwep->KeyMaterial, param->u.crypt.key, pwep->KeyLength); ++ ++ if(param->u.crypt.set_tx) ++ { ++ DBG_8192C("wep, set_tx=1\n"); ++ ++ if(rtw_set_802_11_add_wep(padapter, pwep) == (u8)_FAIL) ++ { ++ ret = -EOPNOTSUPP ; ++ } ++ } ++ else ++ { ++ DBG_8192C("wep, set_tx=0\n"); ++ ++ //don't update "psecuritypriv->dot11PrivacyAlgrthm" and ++ //"psecuritypriv->dot11PrivacyKeyIndex=keyid", but can rtw_set_key to fw/cam ++ ++ if (wep_key_idx >= WEP_KEYS) { ++ ret = -EOPNOTSUPP ; ++ goto exit; ++ } ++ ++ _rtw_memcpy(&(psecuritypriv->dot11DefKey[wep_key_idx].skey[0]), pwep->KeyMaterial, pwep->KeyLength); ++ psecuritypriv->dot11DefKeylen[wep_key_idx]=pwep->KeyLength; ++ rtw_set_key(padapter, psecuritypriv, wep_key_idx, 0); ++ } ++ ++ goto exit; ++ } ++ ++ if(padapter->securitypriv.dot11AuthAlgrthm == dot11AuthAlgrthm_8021X) // 802_1x ++ { ++ struct sta_info * psta,*pbcmc_sta; ++ struct sta_priv * pstapriv = &padapter->stapriv; ++ ++ //printk("%s, : dot11AuthAlgrthm == dot11AuthAlgrthm_8021X \n", __func__); ++ ++ if (check_fwstate(pmlmepriv, WIFI_STATION_STATE | WIFI_MP_STATE) == _TRUE) //sta mode ++ { ++ psta = rtw_get_stainfo(pstapriv, get_bssid(pmlmepriv)); ++ if (psta == NULL) { ++ //DEBUG_ERR( ("Set wpa_set_encryption: Obtain Sta_info fail \n")); ++ printk("%s, : Obtain Sta_info fail \n", __func__); ++ } ++ else ++ { ++ //Jeff: don't disable ieee8021x_blocked while clearing key ++ if (strcmp(param->u.crypt.alg, "none") != 0) ++ psta->ieee8021x_blocked = _FALSE; ++ ++ ++ if((padapter->securitypriv.ndisencryptstatus == Ndis802_11Encryption2Enabled)|| ++ (padapter->securitypriv.ndisencryptstatus == Ndis802_11Encryption3Enabled)) ++ { ++ psta->dot118021XPrivacy = padapter->securitypriv.dot11PrivacyAlgrthm; ++ } ++ ++ if(param->u.crypt.set_tx ==1)//pairwise key ++ { ++ ++ printk("%s, : param->u.crypt.set_tx ==1 \n", __func__); ++ ++ _rtw_memcpy(psta->dot118021x_UncstKey.skey, param->u.crypt.key, (param->u.crypt.key_len>16 ?16:param->u.crypt.key_len)); ++ ++ if(strcmp(param->u.crypt.alg, "TKIP") == 0)//set mic key ++ { ++ //DEBUG_ERR(("\nset key length :param->u.crypt.key_len=%d\n", param->u.crypt.key_len)); ++ _rtw_memcpy(psta->dot11tkiptxmickey.skey, &(param->u.crypt.key[16]), 8); ++ _rtw_memcpy(psta->dot11tkiprxmickey.skey, &(param->u.crypt.key[24]), 8); ++ ++ padapter->securitypriv.busetkipkey=_FALSE; ++ //_set_timer(&padapter->securitypriv.tkip_timer, 50); ++ } ++ ++ //DEBUG_ERR(("\n param->u.crypt.key_len=%d\n",param->u.crypt.key_len)); ++ //DEBUG_ERR(("\n ~~~~stastakey:unicastkey\n")); ++ DBG_871X("\n ~~~~stastakey:unicastkey\n"); ++ ++ rtw_setstakey_cmd(padapter, (unsigned char *)psta, _TRUE); ++ } ++ else//group key ++ { ++ _rtw_memcpy(padapter->securitypriv.dot118021XGrpKey[param->u.crypt.idx].skey, param->u.crypt.key,(param->u.crypt.key_len>16 ?16:param->u.crypt.key_len)); ++ _rtw_memcpy(padapter->securitypriv.dot118021XGrptxmickey[param->u.crypt.idx].skey,&(param->u.crypt.key[16]),8); ++ _rtw_memcpy(padapter->securitypriv.dot118021XGrprxmickey[param->u.crypt.idx].skey,&(param->u.crypt.key[24]),8); ++ padapter->securitypriv.binstallGrpkey = _TRUE; ++ //DEBUG_ERR(("\n param->u.crypt.key_len=%d\n", param->u.crypt.key_len)); ++ //DEBUG_ERR(("\n ~~~~stastakey:groupkey\n")); ++ DBG_871X("\n ~~~~stastakey:groupkey\n"); ++ ++ padapter->securitypriv.dot118021XGrpKeyid = param->u.crypt.idx; ++ ++ rtw_set_key(padapter,&padapter->securitypriv,param->u.crypt.idx, 1); ++#ifdef CONFIG_P2P ++ if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_PROVISIONING_ING)) ++ { ++ rtw_p2p_set_state(pwdinfo, P2P_STATE_PROVISIONING_DONE); ++ } ++#endif //CONFIG_P2P ++ ++ } ++ } ++ ++ pbcmc_sta=rtw_get_bcmc_stainfo(padapter); ++ if(pbcmc_sta==NULL) ++ { ++ //DEBUG_ERR( ("Set OID_802_11_ADD_KEY: bcmc stainfo is null \n")); ++ } ++ else ++ { ++ //Jeff: don't disable ieee8021x_blocked while clearing key ++ if (strcmp(param->u.crypt.alg, "none") != 0) ++ pbcmc_sta->ieee8021x_blocked = _FALSE; ++ ++ if((padapter->securitypriv.ndisencryptstatus == Ndis802_11Encryption2Enabled)|| ++ (padapter->securitypriv.ndisencryptstatus == Ndis802_11Encryption3Enabled)) ++ { ++ pbcmc_sta->dot118021XPrivacy = padapter->securitypriv.dot11PrivacyAlgrthm; ++ } ++ } ++ } ++ else if(check_fwstate(pmlmepriv, WIFI_ADHOC_STATE)) //adhoc mode ++ { ++ } ++ } ++ ++exit: ++ ++ printk("%s, ret=%d\n", __func__, ret); ++ ++ if (pwep) { ++ rtw_mfree((u8 *)pwep,wep_total_len); ++ } ++ ++ _func_exit_; ++ ++ return ret; ++} ++ ++static int cfg80211_rtw_add_key(struct wiphy *wiphy, struct net_device *ndev, ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) ++ u8 key_index, bool pairwise, const u8 *mac_addr, ++#else // (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) ++ u8 key_index, const u8 *mac_addr, ++#endif // (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) ++ struct key_params *params) ++{ ++ char *alg_name; ++ u32 param_len; ++ struct ieee_param *param = NULL; ++ int ret=0; ++ struct wireless_dev *rtw_wdev = wiphy_to_wdev(wiphy); ++ _adapter *padapter = wiphy_to_adapter(wiphy); ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ ++ ++ printk("%s, Adding key for %pM\n", __func__, mac_addr); ++ ++ printk("cipher=0x%x\n", params->cipher); ++ ++ printk("key_len=0x%x\n", params->key_len); ++ ++ printk("seq_len=0x%x\n", params->seq_len); ++ ++ printk("key_index=%d\n", key_index); ++ ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) ++ printk("pairwise=%d\n", pairwise); ++#endif // (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) ++ ++ ++ param_len = sizeof(struct ieee_param) + params->key_len; ++ param = (struct ieee_param *)rtw_malloc(param_len); ++ if (param == NULL) ++ return -1; ++ ++ _rtw_memset(param, 0, param_len); ++ ++ param->cmd = IEEE_CMD_SET_ENCRYPTION; ++ _rtw_memset(param->sta_addr, 0xff, ETH_ALEN); ++ ++ switch (params->cipher) { ++ case IW_AUTH_CIPHER_NONE: ++ //todo: remove key ++ //remove = 1; ++ alg_name = "none"; ++ break; ++ case WLAN_CIPHER_SUITE_WEP40: ++ case WLAN_CIPHER_SUITE_WEP104: ++ alg_name = "WEP"; ++ break; ++ case WLAN_CIPHER_SUITE_TKIP: ++ alg_name = "TKIP"; ++ break; ++ case WLAN_CIPHER_SUITE_CCMP: ++ alg_name = "CCMP"; ++ break; ++ default: ++ return -ENOTSUPP; ++ } ++ ++ strncpy((char *)param->u.crypt.alg, alg_name, IEEE_CRYPT_ALG_NAME_LEN); ++ ++ ++ if (!mac_addr || is_broadcast_ether_addr(mac_addr)) ++ { ++ param->u.crypt.set_tx = 0; ++ } else { ++ param->u.crypt.set_tx = 1; ++ } ++ ++ ++ //param->u.crypt.idx = key_index - 1; ++ param->u.crypt.idx = key_index; ++ ++ if (params->seq_len && params->seq) ++ { ++ _rtw_memcpy(param->u.crypt.seq, params->seq, params->seq_len); ++ } ++ ++ if(params->key_len && params->key) ++ { ++ param->u.crypt.key_len = params->key_len; ++ _rtw_memcpy(param->u.crypt.key, params->key, params->key_len); ++ } ++ ++ //if(rtw_wdev->iftype == NL80211_IFTYPE_STATION) ++ if(check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE) ++ { ++ ret = rtw_cfg80211_set_encryption(ndev, param, param_len); ++ } ++ else if(check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE)//else if(rtw_wdev->iftype == NL80211_IFTYPE_AP) ++ { ++#ifdef CONFIG_AP_MODE ++ if(mac_addr) ++ _rtw_memcpy(param->sta_addr, (void*)mac_addr, ETH_ALEN); ++ ++ ret = rtw_cfg80211_ap_set_encryption(ndev, param, param_len); ++#endif ++ } ++ else ++ { ++ printk("error! fw_state=0x%x, iftype=%d\n", pmlmepriv->fw_state, rtw_wdev->iftype); ++ ++ } ++ ++ if(param) ++ { ++ rtw_mfree((u8*)param, param_len); ++ } ++ ++ return ret; ++ ++} ++ ++static int cfg80211_rtw_get_key(struct wiphy *wiphy, struct net_device *ndev, ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) ++ u8 key_index, bool pairwise, const u8 *mac_addr, ++#else // (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) ++ u8 key_index, const u8 *mac_addr, ++#endif // (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) ++ void *cookie, ++ void (*callback)(void *cookie, ++ struct key_params*)) ++{ ++#if 0 ++ struct iwm_priv *iwm = ndev_to_iwm(ndev); ++ struct iwm_key *key = &iwm->keys[key_index]; ++ struct key_params params; ++ ++ IWM_DBG_WEXT(iwm, DBG, "Getting key %d\n", key_index); ++ ++ memset(¶ms, 0, sizeof(params)); ++ ++ params.cipher = key->cipher; ++ params.key_len = key->key_len; ++ params.seq_len = key->seq_len; ++ params.seq = key->seq; ++ params.key = key->key; ++ ++ callback(cookie, ¶ms); ++ ++ return key->key_len ? 0 : -ENOENT; ++#endif ++ printk("%s\n", __func__); ++ return 0; ++} ++ ++static int cfg80211_rtw_del_key(struct wiphy *wiphy, struct net_device *ndev, ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) ++ u8 key_index, bool pairwise, const u8 *mac_addr) ++#else // (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) ++ u8 key_index, const u8 *mac_addr) ++#endif // (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) ++{ ++#if 0 ++ struct iwm_priv *iwm = ndev_to_iwm(ndev); ++ struct iwm_key *key = &iwm->keys[key_index]; ++ ++ if (!iwm->keys[key_index].key_len) { ++ IWM_DBG_WEXT(iwm, DBG, "Key %d not used\n", key_index); ++ return 0; ++ } ++ ++ if (key_index == iwm->default_key) ++ iwm->default_key = -1; ++ ++ return iwm_set_key(iwm, 1, key); ++#endif ++ printk("%s\n", __func__); ++ return 0; ++} ++ ++static int cfg80211_rtw_set_default_key(struct wiphy *wiphy, ++ struct net_device *ndev, ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,38)) ++ u8 key_index, bool unicast, bool multicast) ++#else // (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,38)) ++ u8 key_index) ++#endif // (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,38)) ++{ ++#if 0 ++ struct iwm_priv *iwm = ndev_to_iwm(ndev); ++ ++ IWM_DBG_WEXT(iwm, DBG, "Default key index is: %d\n", key_index); ++ ++ if (!iwm->keys[key_index].key_len) { ++ IWM_ERR(iwm, "Key %d not used\n", key_index); ++ return -EINVAL; ++ } ++ ++ iwm->default_key = key_index; ++ ++ return iwm_set_tx_key(iwm, key_index); ++#endif ++ printk("%s\n", __func__); ++ return 0; ++} ++ ++static int cfg80211_rtw_get_station(struct wiphy *wiphy, ++ struct net_device *ndev, ++ u8 *mac, struct station_info *sinfo) ++{ ++ _adapter *padapter = wiphy_to_adapter(wiphy); ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ ++ if(!mac) { ++ DBG_871X("%s, mac==%p\n", __func__, mac); ++ return -ENOENT; ++ } ++ ++#ifdef CONFIG_DEBUG_CFG80211 ++ DBG_871X("%s, mac="MAC_FMT"\n", __func__, MAC_ARG(mac)); ++#endif ++ ++ //for infra./P2PClient mode ++ if(check_fwstate(pmlmepriv, WIFI_STATION_STATE) ++ && check_fwstate(pmlmepriv, _FW_LINKED) ++ ) ++ { ++ struct wlan_network *cur_network = &(pmlmepriv->cur_network); ++ ++ if (_rtw_memcmp(mac, cur_network->network.MacAddress, ETH_ALEN) == _FALSE) ++ { ++ DBG_871X("%s, mismatch bssid="MAC_FMT"\n", __func__, MAC_ARG(cur_network->network.MacAddress)); ++ return -ENOENT; ++ } ++ ++ sinfo->filled |= STATION_INFO_SIGNAL; ++ sinfo->signal = translate_percentage_to_dbm(padapter->recvpriv.signal_strength); ++ ++ sinfo->filled |= STATION_INFO_TX_BITRATE; ++ sinfo->txrate.legacy = 10 * rtw_get_network_max_rate(padapter, &pmlmepriv->cur_network.network); ++ } ++ ++ //for Ad-Hoc/AP mode ++ if ((check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) ++ ||check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) ++ ||check_fwstate(pmlmepriv, WIFI_AP_STATE) ) ++ && check_fwstate(pmlmepriv, _FW_LINKED) ++ ) ++ { ++ struct sta_info *psta = NULL; ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ ++ psta = rtw_get_stainfo(pstapriv, mac); ++ if(psta == NULL) ++ { ++ printk("%s, sta_info is null\n", __func__); ++ return -ENOENT; ++ } ++ ++ //TODO: should acquire station info... ++ } ++ ++ return 0; ++} ++ ++extern int netdev_open(struct net_device *pnetdev); ++ ++static int cfg80211_rtw_change_iface(struct wiphy *wiphy, ++ struct net_device *ndev, ++ enum nl80211_iftype type, u32 *flags, ++ struct vif_params *params) ++{ ++ enum nl80211_iftype old_type; ++ NDIS_802_11_NETWORK_INFRASTRUCTURE networkType ; ++ _adapter *padapter = wiphy_to_adapter(wiphy); ++ struct wireless_dev *rtw_wdev = wiphy_to_wdev(wiphy); ++ struct wifidirect_info *pwdinfo= &(padapter->wdinfo); ++ int ret = 0; ++ u8 change = _FALSE; ++ ++ ++ DBG_871X("%s call netdev_open\n", __FUNCTION__); ++ if(netdev_open(ndev) != 0) { ++ ret= -EPERM; ++ goto exit; ++ } ++ ++ if(_FAIL == rtw_pwr_wakeup(padapter)) { ++ ret= -EPERM; ++ goto exit; ++ } ++ ++ old_type = rtw_wdev->iftype; ++ printk("%s, old_iftype=%d, new_iftype=%d\n", __func__, old_type, type); ++ ++ ++ ++ if(old_type != type) ++ change = _TRUE; ++ ++ ++ switch (type) { ++ case NL80211_IFTYPE_ADHOC: ++ networkType = Ndis802_11IBSS; ++ break; ++ case NL80211_IFTYPE_STATION: ++ networkType = Ndis802_11Infrastructure; ++ if(change && rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) ++ { ++ ++ _cancel_timer_ex( &pwdinfo->find_phase_timer ); ++ _cancel_timer_ex( &pwdinfo->restore_p2p_state_timer ); ++ _cancel_timer_ex( &pwdinfo->pre_tx_scan_timer); ++ ++ //it means remove GO and change mode from AP(GO) to station(P2P DEVICE) ++ rtw_p2p_set_role(pwdinfo, P2P_ROLE_DEVICE); ++ rtw_p2p_set_state(pwdinfo, rtw_p2p_pre_state(pwdinfo)); ++ ++ printk("%s, role=%d, p2p_state=%d, pre_p2p_state=%d\n", __func__, rtw_p2p_role(pwdinfo), rtw_p2p_state(pwdinfo), rtw_p2p_pre_state(pwdinfo)); ++ ++ } ++ break; ++ case NL80211_IFTYPE_AP: ++ networkType = Ndis802_11APMode; ++ if(change && !rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) ++ { ++ //it means P2P Group created, we will be GO and change mode from P2P DEVICE to AP(GO) ++ rtw_p2p_set_role(pwdinfo, P2P_ROLE_GO); ++ } ++ break; ++ default: ++ return -EOPNOTSUPP; ++ } ++ ++ rtw_wdev->iftype = type; ++ ++ if (rtw_set_802_11_infrastructure_mode(padapter, networkType) ==_FALSE) ++ { ++ rtw_wdev->iftype = old_type; ++ ret = -EPERM; ++ goto exit; ++ } ++ ++ rtw_setopmode_cmd(padapter, networkType); ++ ++exit: ++ ++ return ret; ++} ++ ++void rtw_cfg80211_indicate_scan_done(struct rtw_wdev_priv *pwdev_priv, bool aborted) ++{ ++ _irqL irqL; ++ ++ _enter_critical_bh(&pwdev_priv->scan_req_lock, &irqL); ++ if(pwdev_priv->scan_request != NULL) ++ { ++ //struct cfg80211_scan_request *scan_request = pwdev_priv->scan_request; ++ ++#ifdef CONFIG_DEBUG_CFG80211 ++ DBG_871X("%s with scan req\n", __FUNCTION__); ++#endif ++ ++ //avoid WARN_ON(request != wiphy_to_dev(request->wiphy)->scan_req); ++ //if(scan_request == wiphy_to_dev(scan_request->wiphy)->scan_req) ++ ++ cfg80211_scan_done(pwdev_priv->scan_request, aborted); ++ pwdev_priv->scan_request = NULL; ++ ++ } else { ++ DBG_871X("%s without scan req\n", __FUNCTION__); ++ } ++ _exit_critical_bh(&pwdev_priv->scan_req_lock, &irqL); ++} ++ ++void rtw_cfg80211_surveydone_event_callback(_adapter *padapter) ++{ ++ _irqL irqL; ++ _list *plist, *phead; ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ _queue *queue = &(pmlmepriv->scanned_queue); ++ struct wlan_network *pnetwork = NULL; ++ u32 cnt=0; ++ u32 wait_for_surveydone; ++ sint wait_status; ++#ifdef CONFIG_P2P ++ struct wifidirect_info* pwdinfo = &padapter->wdinfo; ++#endif //CONFIG_P2P ++ struct rtw_wdev_priv *pwdev_priv = wdev_to_priv(padapter->rtw_wdev); ++ struct pwrctrl_priv *pwrpriv = &padapter->pwrctrlpriv; ++ ++#ifdef CONFIG_DEBUG_CFG80211 ++ printk("%s\n", __func__); ++#endif ++ ++#if 0 ++ if(padapter->pwrctrlpriv.brfoffbyhw && padapter->bDriverStopped) ++ { ++ return; ++ } ++ ++#ifdef CONFIG_P2P ++ if(!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) ++ { ++ // P2P is enabled ++ wait_for_surveydone = 200; ++ } ++ else ++ { ++ // P2P is disabled ++ wait_for_surveydone = 100; ++ } ++#else ++ { ++ wait_for_surveydone = 100; ++ } ++#endif //CONFIG_P2P ++ ++ ++ wait_status = _FW_UNDER_SURVEY ++ #ifndef CONFIG_ANDROID ++ |_FW_UNDER_LINKING ++ #endif ++ ; ++ ++ while(check_fwstate(pmlmepriv, wait_status) == _TRUE) ++ { ++ rtw_msleep_os(30); ++ cnt++; ++ if(cnt > wait_for_surveydone ) ++ break; ++ } ++#endif ++ ++ _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); ++ ++ phead = get_list_head(queue); ++ plist = get_next(phead); ++ ++ while(1) ++ { ++ if (rtw_end_of_queue_search(phead,plist)== _TRUE) ++ break; ++ ++ pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list); ++ ++ //report network only if the current channel set contains the channel to which this network belongs ++ if( _TRUE == rtw_is_channel_set_contains_channel(padapter->mlmeextpriv.channel_set, pnetwork->network.Configuration.DSConfig) ++ #ifdef CONFIG_VALIDATE_SSID ++ && _TRUE == rtw_validate_ssid(&(pnetwork->network.Ssid)) ++ #endif ++ ) ++ { ++ //ev=translate_scan(padapter, a, pnetwork, ev, stop); ++ rtw_cfg80211_inform_bss(padapter, pnetwork); ++ } ++ ++ plist = get_next(plist); ++ ++ } ++ ++ _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); ++ ++ #if 0 ++ // Disable P2P Listen State ++ if(!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) ++ { ++ _cancel_timer_ex( &pwdinfo->find_phase_timer ); ++ _cancel_timer_ex( &pwdinfo->restore_p2p_state_timer ); ++ _cancel_timer_ex( &pwdinfo->pre_tx_scan_timer); ++ ++ //rtw_p2p_set_state(pwdinfo, P2P_STATE_NONE); ++ rtw_p2p_set_state(pwdinfo, rtw_p2p_pre_state(pwdinfo)); ++#ifdef CONFIG_DEBUG_CFG80211 ++ printk("%s, role=%d, p2p_state=%d\n", __func__, rtw_p2p_role(pwdinfo), rtw_p2p_state(pwdinfo)); ++#endif ++ ++ if(pwrpriv->bips_processing == _FALSE){ ++ rtw_set_pwr_state_check_timer(pwrpriv); ++ } ++ } ++ #endif ++ ++ //call this after other things have been done ++ rtw_indicate_scan_done(padapter, _FALSE); ++ ++} ++ ++static int rtw_cfg80211_set_probe_req_wpsp2pie(struct net_device *net, char *buf, int len) ++{ ++ int ret = 0; ++ uint wps_ielen = 0; ++ u8 *wps_ie; ++ u32 p2p_ielen = 0; ++ u8 *p2p_ie; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(net); ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ ++#ifdef CONFIG_DEBUG_CFG80211 ++ printk("%s, ielen=%d\n", __func__, len); ++#endif ++ ++ if(len>0) ++ { ++ if((wps_ie = rtw_get_wps_ie(buf, len, NULL, &wps_ielen))) ++ { ++ #ifdef CONFIG_DEBUG_CFG80211 ++ printk("probe_req_wps_ielen=%d\n", wps_ielen); ++ #endif ++ ++ if(pmlmepriv->wps_probe_req_ie) ++ { ++ u32 free_len = pmlmepriv->wps_probe_req_ie_len; ++ pmlmepriv->wps_probe_req_ie_len = 0; ++ rtw_mfree(pmlmepriv->wps_probe_req_ie, free_len); ++ pmlmepriv->wps_probe_req_ie = NULL; ++ } ++ ++ pmlmepriv->wps_probe_req_ie = rtw_malloc(wps_ielen); ++ if ( pmlmepriv->wps_probe_req_ie == NULL) { ++ printk("%s()-%d: rtw_malloc() ERROR!\n", __FUNCTION__, __LINE__); ++ return -EINVAL; ++ ++ } ++ _rtw_memcpy(pmlmepriv->wps_probe_req_ie, wps_ie, wps_ielen); ++ pmlmepriv->wps_probe_req_ie_len = wps_ielen; ++ } ++ ++ buf += wps_ielen; ++ len -= wps_ielen; ++ if((p2p_ie=rtw_get_p2p_ie(buf, len, NULL, &p2p_ielen))) ++ { ++ #ifdef CONFIG_DEBUG_CFG80211 ++ printk("probe_req_p2p_ielen=%d\n", p2p_ielen); ++ #endif ++ ++ if(pmlmepriv->p2p_probe_req_ie) ++ { ++ u32 free_len = pmlmepriv->p2p_probe_req_ie_len; ++ pmlmepriv->p2p_probe_req_ie_len = 0; ++ rtw_mfree(pmlmepriv->p2p_probe_req_ie, free_len); ++ pmlmepriv->p2p_probe_req_ie = NULL; ++ } ++ ++ pmlmepriv->p2p_probe_req_ie = rtw_malloc(len); ++ if ( pmlmepriv->p2p_probe_req_ie == NULL) { ++ printk("%s()-%d: rtw_malloc() ERROR!\n", __FUNCTION__, __LINE__); ++ return -EINVAL; ++ ++ } ++ _rtw_memcpy(pmlmepriv->p2p_probe_req_ie, p2p_ie, p2p_ielen); ++ pmlmepriv->p2p_probe_req_ie_len = p2p_ielen; ++ } ++ ++ } ++ ++ return ret; ++ ++} ++ ++static void rtw_cfg80211_scan_abort(_adapter *padapter) ++{ ++ u32 cnt=0; ++ u32 wait_for_surveydone; ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); ++ ++#ifdef CONFIG_DEBUG_CFG80211 ++ printk("%s\n", __func__); ++#endif ++ ++ wait_for_surveydone = 10; ++ ++ pmlmeext->scan_abort = _TRUE; ++ ++ while(check_fwstate(pmlmepriv, _FW_UNDER_SURVEY) == _TRUE) ++ { ++ printk("%s : fw_state=_FW_UNDER_SURVEY!\n", __func__); ++ ++ rtw_msleep_os(20); ++ cnt++; ++ if(cnt > wait_for_surveydone ) ++ { ++ printk("waiting for scan_abort time out!\n"); ++ break; ++ } ++ } ++ ++ rtw_cfg80211_indicate_scan_done(wdev_to_priv(padapter->rtw_wdev), _TRUE); ++ ++} ++ ++static int cfg80211_rtw_scan(struct wiphy *wiphy, struct net_device *ndev, ++ struct cfg80211_scan_request *request) ++{ ++ int i; ++ u8 _status = _FALSE; ++ int ret = 0; ++ _adapter *padapter = wiphy_to_adapter(wiphy); ++ struct mlme_priv *pmlmepriv= &padapter->mlmepriv; ++ NDIS_802_11_SSID ssid[RTW_SSID_SCAN_AMOUNT]; ++ _irqL irqL; ++ u8 *wps_ie=NULL; ++ uint wps_ielen=0; ++ u8 *p2p_ie=NULL; ++ uint p2p_ielen=0; ++#ifdef CONFIG_P2P ++ struct wifidirect_info *pwdinfo= &(padapter->wdinfo); ++#endif //CONFIG_P2P ++ struct rtw_wdev_priv *pwdev_priv = wdev_to_priv(padapter->rtw_wdev); ++ struct cfg80211_ssid *ssids = request->ssids; ++ struct ieee80211_channel *pchannel = request->channels[0]; ++ int social_channel = 0, j = 0; ++ bool need_indicate_scan_done = _FALSE; ++ ++#ifdef CONFIG_DEBUG_CFG80211 ++ printk("%s\n", __func__); ++#endif ++ ++#ifdef CONFIG_MP_INCLUDED ++ if (check_fwstate(pmlmepriv, WIFI_MP_STATE) == _TRUE) ++ { ++ ret = -EPERM; ++ goto exit; ++ } ++#endif ++ ++ _enter_critical_bh(&pwdev_priv->scan_req_lock, &irqL); ++ pwdev_priv->scan_request = request; ++ _exit_critical_bh(&pwdev_priv->scan_req_lock, &irqL); ++ ++ if (check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) ++ { ++ //need_indicate_scan_done = _TRUE; ++ //goto check_need_indicate_scan_done; ++ } ++ ++ if(_FAIL == rtw_pwr_wakeup(padapter)) { ++ need_indicate_scan_done = _TRUE; ++ goto check_need_indicate_scan_done; ++ } ++ ++ if( ssids->ssid != NULL ) ++ { ++ if( _rtw_memcmp(ssids->ssid, "DIRECT-", 7) ++ && rtw_get_p2p_ie((u8 *)request->ie, request->ie_len, NULL, NULL) ++ ) ++ { ++ //if(!rtw_p2p_chk_role(pwdinfo, P2P_ROLE_CLIENT) && !rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) ++ if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) ++ { ++ rtw_p2p_enable(padapter, P2P_ROLE_DEVICE); ++ wdev_to_priv(padapter->rtw_wdev)->p2p_enabled = _TRUE; ++ } ++ else ++ { ++ rtw_p2p_set_pre_state(pwdinfo, rtw_p2p_state(pwdinfo)); ++ #ifdef CONFIG_DEBUG_CFG80211 ++ printk("%s, role=%d, p2p_state=%d\n", __func__, rtw_p2p_role(pwdinfo), rtw_p2p_state(pwdinfo)); ++ #endif ++ } ++ ++ rtw_p2p_set_state(pwdinfo, P2P_STATE_LISTEN); ++ ++ if(request->n_channels == 3 && ++ pchannel->center_freq == 2412 && ++ (pchannel+1)->center_freq == 2417 && ++ (pchannel+2)->center_freq == 2422 ++ ) ++ { ++ social_channel = 1; ++ } ++ } ++ } ++ ++ if(request->ie && request->ie_len>0) ++ { ++ rtw_cfg80211_set_probe_req_wpsp2pie( ndev, (u8 *)request->ie, request->ie_len ); ++ } ++ ++ if (pmlmepriv->LinkDetectInfo.bBusyTraffic == _TRUE) ++ { ++ printk("%s, bBusyTraffic == _TRUE\n", __func__); ++ need_indicate_scan_done = _TRUE; ++ goto check_need_indicate_scan_done; ++ } ++ ++ if (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY|_FW_UNDER_LINKING) == _TRUE) ++ { ++ printk("%s, fwstate=0x%x\n", __func__, pmlmepriv->fw_state); ++ need_indicate_scan_done = _TRUE; ++ goto check_need_indicate_scan_done; ++ } ++ ++ ++#ifdef CONFIG_P2P ++ if(!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE) && !rtw_p2p_chk_state(pwdinfo, P2P_STATE_IDLE)) ++ { ++ rtw_p2p_set_state(pwdinfo, P2P_STATE_FIND_PHASE_SEARCH); ++ rtw_free_network_queue(padapter, _TRUE); ++ ++ //Commented by Kurt 20120114 ++ //For pwdinfo->find_phase_state_exchange_cnt = 3 means we just do site survey on social channels ++ if(social_channel == 0) ++ pwdinfo->find_phase_state_exchange_cnt = 0; ++ else ++ pwdinfo->find_phase_state_exchange_cnt = 3; ++ } ++#endif //CONFIG_P2P ++ ++ ++ _rtw_memset(ssid, 0, sizeof(NDIS_802_11_SSID)*RTW_SSID_SCAN_AMOUNT); ++ //parsing request ssids, n_ssids ++ for (i = 0; i < request->n_ssids && i < RTW_SSID_SCAN_AMOUNT; i++) { ++ #ifdef CONFIG_DEBUG_CFG80211 ++ printk("ssid=%s, len=%d\n", ssids[i].ssid, ssids[i].ssid_len); ++ #endif ++ _rtw_memcpy(ssid[i].Ssid, ssids[i].ssid, ssids[i].ssid_len); ++ ssid[i].SsidLength = ssids[i].ssid_len; ++ } ++ ++ ++#ifdef CONFIG_DEBUG_CFG80211 ++ //parsing channels, n_channels ++ DBG_871X("%s n_channels:%u\n", __FUNCTION__, request->n_channels); ++#endif ++ ++ _enter_critical_bh(&pmlmepriv->lock, &irqL); ++ _status = rtw_sitesurvey_cmd(padapter, ssid, RTW_SSID_SCAN_AMOUNT); ++ _exit_critical_bh(&pmlmepriv->lock, &irqL); ++ ++ ++ if(_status == _FALSE) ++ { ++ ret = -1; ++ } ++ ++check_need_indicate_scan_done: ++ if(need_indicate_scan_done) ++ rtw_cfg80211_surveydone_event_callback(padapter); ++ ++exit: ++ ++ return ret; ++ ++} ++ ++static int cfg80211_rtw_set_wiphy_params(struct wiphy *wiphy, u32 changed) ++{ ++#if 0 ++ struct iwm_priv *iwm = wiphy_to_iwm(wiphy); ++ ++ if (changed & WIPHY_PARAM_RTS_THRESHOLD && ++ (iwm->conf.rts_threshold != wiphy->rts_threshold)) { ++ int ret; ++ ++ iwm->conf.rts_threshold = wiphy->rts_threshold; ++ ++ ret = iwm_umac_set_config_fix(iwm, UMAC_PARAM_TBL_CFG_FIX, ++ CFG_RTS_THRESHOLD, ++ iwm->conf.rts_threshold); ++ if (ret < 0) ++ return ret; ++ } ++ ++ if (changed & WIPHY_PARAM_FRAG_THRESHOLD && ++ (iwm->conf.frag_threshold != wiphy->frag_threshold)) { ++ int ret; ++ ++ iwm->conf.frag_threshold = wiphy->frag_threshold; ++ ++ ret = iwm_umac_set_config_fix(iwm, UMAC_PARAM_TBL_FA_CFG_FIX, ++ CFG_FRAG_THRESHOLD, ++ iwm->conf.frag_threshold); ++ if (ret < 0) ++ return ret; ++ } ++#endif ++ printk("%s\n", __func__); ++ return 0; ++} ++ ++static int cfg80211_rtw_join_ibss(struct wiphy *wiphy, struct net_device *dev, ++ struct cfg80211_ibss_params *params) ++{ ++#if 0 ++ struct iwm_priv *iwm = wiphy_to_iwm(wiphy); ++ struct ieee80211_channel *chan = params->channel; ++ ++ if (!test_bit(IWM_STATUS_READY, &iwm->status)) ++ return -EIO; ++ ++ /* UMAC doesn't support creating or joining an IBSS network ++ * with specified bssid. */ ++ if (params->bssid) ++ return -EOPNOTSUPP; ++ ++ iwm->channel = ieee80211_frequency_to_channel(chan->center_freq); ++ iwm->umac_profile->ibss.band = chan->band; ++ iwm->umac_profile->ibss.channel = iwm->channel; ++ iwm->umac_profile->ssid.ssid_len = params->ssid_len; ++ memcpy(iwm->umac_profile->ssid.ssid, params->ssid, params->ssid_len); ++ ++ return iwm_send_mlme_profile(iwm); ++#endif ++ printk("%s\n", __func__); ++ return 0; ++} ++ ++static int cfg80211_rtw_leave_ibss(struct wiphy *wiphy, struct net_device *dev) ++{ ++#if 0 ++ struct iwm_priv *iwm = wiphy_to_iwm(wiphy); ++ ++ if (iwm->umac_profile_active) ++ return iwm_invalidate_mlme_profile(iwm); ++#endif ++ printk("%s\n", __func__); ++ return 0; ++} ++ ++static int rtw_cfg80211_set_wpa_version(struct security_priv *psecuritypriv, u32 wpa_version) ++{ ++ printk("%s, wpa_version=%d\n", __func__, wpa_version); ++ ++ ++ if (!wpa_version) { ++ psecuritypriv->ndisauthtype = Ndis802_11AuthModeOpen; ++ return 0; ++ } ++ ++ ++ if (wpa_version & (NL80211_WPA_VERSION_1 | NL80211_WPA_VERSION_2)) ++ { ++ psecuritypriv->ndisauthtype = Ndis802_11AuthModeWPAPSK; ++ } ++ ++/* ++ if (wpa_version & NL80211_WPA_VERSION_2) ++ { ++ psecuritypriv->ndisauthtype = Ndis802_11AuthModeWPA2PSK; ++ } ++*/ ++ ++ return 0; ++ ++} ++ ++static int rtw_cfg80211_set_auth_type(struct security_priv *psecuritypriv, ++ enum nl80211_auth_type sme_auth_type) ++{ ++ printk("%s, nl80211_auth_type=%d\n", __func__, sme_auth_type); ++ ++ ++ switch (sme_auth_type) { ++ case NL80211_AUTHTYPE_AUTOMATIC: ++ ++ psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_Auto; ++ ++ break; ++ case NL80211_AUTHTYPE_OPEN_SYSTEM: ++ ++ psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_Open; ++ ++ if(psecuritypriv->ndisauthtype>Ndis802_11AuthModeWPA) ++ psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_8021X; ++ ++ break; ++ case NL80211_AUTHTYPE_SHARED_KEY: ++ ++ psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_Shared; ++ ++ psecuritypriv->ndisencryptstatus = Ndis802_11Encryption1Enabled; ++ ++ ++ break; ++ default: ++ psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_Open; ++ //return -ENOTSUPP; ++ } ++ ++ return 0; ++ ++} ++ ++static int rtw_cfg80211_set_cipher(struct security_priv *psecuritypriv, u32 cipher, bool ucast) ++{ ++ u32 ndisencryptstatus = Ndis802_11EncryptionDisabled; ++ ++ u32 *profile_cipher = ucast ? &psecuritypriv->dot11PrivacyAlgrthm : ++ &psecuritypriv->dot118021XGrpPrivacy; ++ ++ printk("%s, ucast=%d, cipher=0x%x\n", __func__, ucast, cipher); ++ ++ ++ if (!cipher) { ++ *profile_cipher = _NO_PRIVACY_; ++ psecuritypriv->ndisencryptstatus = ndisencryptstatus; ++ return 0; ++ } ++ ++ switch (cipher) { ++ case IW_AUTH_CIPHER_NONE: ++ *profile_cipher = _NO_PRIVACY_; ++ ndisencryptstatus = Ndis802_11EncryptionDisabled; ++ break; ++ case WLAN_CIPHER_SUITE_WEP40: ++ *profile_cipher = _WEP40_; ++ ndisencryptstatus = Ndis802_11Encryption1Enabled; ++ break; ++ case WLAN_CIPHER_SUITE_WEP104: ++ *profile_cipher = _WEP104_; ++ ndisencryptstatus = Ndis802_11Encryption1Enabled; ++ break; ++ case WLAN_CIPHER_SUITE_TKIP: ++ *profile_cipher = _TKIP_; ++ ndisencryptstatus = Ndis802_11Encryption2Enabled; ++ break; ++ case WLAN_CIPHER_SUITE_CCMP: ++ *profile_cipher = _AES_; ++ ndisencryptstatus = Ndis802_11Encryption3Enabled; ++ break; ++ default: ++ printk("Unsupported cipher: 0x%x\n", cipher); ++ return -ENOTSUPP; ++ } ++ ++ if(ucast) ++ { ++ psecuritypriv->ndisencryptstatus = ndisencryptstatus; ++ ++ //if(psecuritypriv->dot11PrivacyAlgrthm >= _AES_) ++ // psecuritypriv->ndisauthtype = Ndis802_11AuthModeWPA2PSK; ++ } ++ ++ return 0; ++} ++ ++static int rtw_cfg80211_set_key_mgt(struct security_priv *psecuritypriv, u32 key_mgt) ++{ ++ printk("%s, key_mgt=0x%x\n", __func__, key_mgt); ++ ++ if (key_mgt == WLAN_AKM_SUITE_8021X) ++ //*auth_type = UMAC_AUTH_TYPE_8021X; ++ psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_8021X; ++ else if (key_mgt == WLAN_AKM_SUITE_PSK) { ++ psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_8021X; ++ } else { ++ printk("Invalid key mgt: 0x%x\n", key_mgt); ++ //return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++static int rtw_cfg80211_set_wpa_ie(_adapter *padapter, u8 *pie, size_t ielen) ++{ ++ u8 *buf=NULL, *pos=NULL; ++ u32 left; ++ int group_cipher = 0, pairwise_cipher = 0; ++ int ret = 0; ++#ifdef CONFIG_P2P ++ struct wifidirect_info* pwdinfo = &padapter->wdinfo; ++#endif //CONFIG_P2P ++ int wpa_ielen=0; ++ int wpa2_ielen=0; ++ u8 *pwpa, *pwpa2; ++ ++ ++ if((ielen > MAX_WPA_IE_LEN+MAX_WPS_IE_LEN+MAX_P2P_IE_LEN) || (pie == NULL)){ ++ padapter->securitypriv.wps_phase = _FALSE; ++ if(pie == NULL) ++ return ret; ++ else ++ return -EINVAL; ++ } ++ ++ if(ielen) ++ { ++ buf = rtw_zmalloc(ielen); ++ if (buf == NULL){ ++ ret = -ENOMEM; ++ goto exit; ++ } ++ ++ _rtw_memcpy(buf, pie , ielen); ++ ++ //dump ++ { ++ int i; ++ DBG_8192C("set wpa_ie(length:%d):\n", ielen); ++ for(i=0;i= RSN_SELECTOR_LEN){ ++ pos += RSN_SELECTOR_LEN; ++ left -= RSN_SELECTOR_LEN; ++ } ++ else if (left > 0){ ++ RT_TRACE(_module_rtl871x_ioctl_os_c,_drv_err_,("Ie length mismatch, %u too much \n", left)); ++ ret =-1; ++ goto exit; ++ } ++#endif ++ ++ pwpa = rtw_get_wpa_ie(buf, &wpa_ielen, ielen); ++ pwpa2 = rtw_get_wpa2_ie(buf, &wpa2_ielen, ielen); ++ ++ if(pwpa && wpa_ielen>0) ++ { ++ if(rtw_parse_wpa_ie(pwpa, wpa_ielen+2, &group_cipher, &pairwise_cipher) == _SUCCESS) ++ { ++ padapter->securitypriv.dot11AuthAlgrthm= dot11AuthAlgrthm_8021X; ++ padapter->securitypriv.ndisauthtype=Ndis802_11AuthModeWPAPSK; ++ _rtw_memcpy(padapter->securitypriv.supplicant_ie, &pwpa[0], wpa_ielen+2); ++ ++ printk("got wpa_ie\n"); ++ } ++ } ++ ++ if(pwpa2 && wpa2_ielen>0) ++ { ++ if(rtw_parse_wpa2_ie(pwpa2, wpa2_ielen+2, &group_cipher, &pairwise_cipher) == _SUCCESS) ++ { ++ padapter->securitypriv.dot11AuthAlgrthm= dot11AuthAlgrthm_8021X; ++ padapter->securitypriv.ndisauthtype=Ndis802_11AuthModeWPA2PSK; ++ _rtw_memcpy(padapter->securitypriv.supplicant_ie, &pwpa2[0], wpa2_ielen+2); ++ ++ printk("got wpa2_ie\n"); ++ } ++ } ++ ++ switch(group_cipher) ++ { ++ case WPA_CIPHER_NONE: ++ padapter->securitypriv.dot118021XGrpPrivacy=_NO_PRIVACY_; ++ padapter->securitypriv.ndisencryptstatus=Ndis802_11EncryptionDisabled; ++ break; ++ case WPA_CIPHER_WEP40: ++ padapter->securitypriv.dot118021XGrpPrivacy=_WEP40_; ++ padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption1Enabled; ++ break; ++ case WPA_CIPHER_TKIP: ++ padapter->securitypriv.dot118021XGrpPrivacy=_TKIP_; ++ padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption2Enabled; ++ break; ++ case WPA_CIPHER_CCMP: ++ padapter->securitypriv.dot118021XGrpPrivacy=_AES_; ++ padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption3Enabled; ++ break; ++ case WPA_CIPHER_WEP104: ++ padapter->securitypriv.dot118021XGrpPrivacy=_WEP104_; ++ padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption1Enabled; ++ break; ++ } ++ ++ switch(pairwise_cipher) ++ { ++ case WPA_CIPHER_NONE: ++ padapter->securitypriv.dot11PrivacyAlgrthm=_NO_PRIVACY_; ++ padapter->securitypriv.ndisencryptstatus=Ndis802_11EncryptionDisabled; ++ break; ++ case WPA_CIPHER_WEP40: ++ padapter->securitypriv.dot11PrivacyAlgrthm=_WEP40_; ++ padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption1Enabled; ++ break; ++ case WPA_CIPHER_TKIP: ++ padapter->securitypriv.dot11PrivacyAlgrthm=_TKIP_; ++ padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption2Enabled; ++ break; ++ case WPA_CIPHER_CCMP: ++ padapter->securitypriv.dot11PrivacyAlgrthm=_AES_; ++ padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption3Enabled; ++ break; ++ case WPA_CIPHER_WEP104: ++ padapter->securitypriv.dot11PrivacyAlgrthm=_WEP104_; ++ padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption1Enabled; ++ break; ++ } ++ ++ ++ ++ padapter->securitypriv.wps_phase = _FALSE; ++ {//set wps_ie ++ u16 cnt = 0; ++ u8 eid, wps_oui[4]={0x0,0x50,0xf2,0x04}; ++ uint wps_ielen=0; ++ u8 *pwps; ++ ++ pwps = rtw_get_wps_ie(buf, ielen, NULL, &wps_ielen); ++ ++ //while( cnt < ielen ) ++ while( cnt < wps_ielen ) ++ { ++ //eid = buf[cnt]; ++ eid = pwps[cnt]; ++ ++ if((eid==_VENDOR_SPECIFIC_IE_)&&(_rtw_memcmp(&pwps[cnt+2], wps_oui, 4)==_TRUE)) ++ { ++ DBG_8192C("SET WPS_IE\n"); ++ ++ padapter->securitypriv.wps_ie_len = ( (pwps[cnt+1]+2) < (MAX_WPA_IE_LEN<<2)) ? (pwps[cnt+1]+2):(MAX_WPA_IE_LEN<<2); ++ ++ _rtw_memcpy(padapter->securitypriv.wps_ie, &pwps[cnt], padapter->securitypriv.wps_ie_len); ++ ++ if(pwpa==NULL && pwpa2==NULL) ++ { ++ padapter->securitypriv.wps_phase = _TRUE; ++ ++ DBG_8192C("SET WPS_IE, wps_phase==_TRUE\n"); ++ } ++#ifdef CONFIG_P2P ++ if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_GONEGO_OK)) ++ { ++ //rtw_p2p_set_state(pwdinfo, P2P_STATE_PROVISIONING_ING); ++ } ++#endif //CONFIG_P2P ++ ++ cnt += pwps[cnt+1]+2; ++ ++ break; ++ } else { ++ cnt += pwps[cnt+1]+2; //goto next ++ } ++ } ++ }//set wps_ie ++ ++ {//check p2p_ie for assoc req; ++ uint p2p_ielen=0; ++ u8 *p2p_ie; ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ ++ if((p2p_ie=rtw_get_p2p_ie(buf, ielen, NULL, &p2p_ielen))) ++ { ++ #ifdef CONFIG_DEBUG_CFG80211 ++ printk("%s p2p_assoc_req_ielen=%d\n", __FUNCTION__, p2p_ielen); ++ #endif ++ ++ if(pmlmepriv->p2p_assoc_req_ie) ++ { ++ u32 free_len = pmlmepriv->p2p_assoc_req_ie_len; ++ pmlmepriv->p2p_assoc_req_ie_len = 0; ++ rtw_mfree(pmlmepriv->p2p_assoc_req_ie, free_len); ++ pmlmepriv->p2p_assoc_req_ie = NULL; ++ } ++ ++ pmlmepriv->p2p_assoc_req_ie = rtw_malloc(p2p_ielen); ++ if ( pmlmepriv->p2p_assoc_req_ie == NULL) { ++ printk("%s()-%d: rtw_malloc() ERROR!\n", __FUNCTION__, __LINE__); ++ goto exit; ++ ++ } ++ _rtw_memcpy(pmlmepriv->p2p_assoc_req_ie, p2p_ie, p2p_ielen); ++ pmlmepriv->p2p_assoc_req_ie_len = p2p_ielen; ++ ++ } ++ } ++ ++ } ++ ++ ++ RT_TRACE(_module_rtl871x_ioctl_os_c, _drv_info_, ++ ("rtw_set_wpa_ie: pairwise_cipher=0x%08x padapter->securitypriv.ndisencryptstatus=%d padapter->securitypriv.ndisauthtype=%d\n", ++ pairwise_cipher, padapter->securitypriv.ndisencryptstatus, padapter->securitypriv.ndisauthtype)); ++ ++exit: ++ ++ if (buf) rtw_mfree(buf, ielen); ++ ++ return ret; ++} ++ ++static int cfg80211_rtw_connect(struct wiphy *wiphy, struct net_device *dev, ++ struct cfg80211_connect_params *sme) ++{ ++ int ret=0; ++ _irqL irqL; ++ _list *phead; ++ struct wlan_network *pnetwork = NULL; ++ NDIS_802_11_AUTHENTICATION_MODE authmode; ++ NDIS_802_11_SSID ndis_ssid; ++ u8 *dst_ssid, *src_ssid; ++ u8 *dst_bssid, *src_bssid; ++ //u8 matched_by_bssid=_FALSE; ++ //u8 matched_by_ssid=_FALSE; ++ u8 matched=_FALSE; ++ _adapter *padapter = wiphy_to_adapter(wiphy); ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct security_priv *psecuritypriv = &padapter->securitypriv; ++ _queue *queue = &pmlmepriv->scanned_queue; ++ ++ printk("\n=>%s\n",__FUNCTION__); ++ ++ ++ printk("privacy=%d, key=%p, key_len=%d, key_idx=%d\n", sme->privacy, sme->key, sme->key_len, sme->key_idx); ++ ++ ++ if(wdev_to_priv(padapter->rtw_wdev)->block == _TRUE) ++ { ++ ret = -EBUSY; ++ DBG_871X("%s wdev_priv.block is set\n", __FUNCTION__); ++ goto exit; ++ } ++ ++ if(_FAIL == rtw_pwr_wakeup(padapter)) { ++ ret= -EPERM; ++ goto exit; ++ } ++ ++ if(check_fwstate(pmlmepriv, WIFI_AP_STATE)) { ++ ret = -EPERM; ++ goto exit; ++ } ++ ++ if (!sme->ssid || !sme->ssid_len) ++ { ++ ret = -EINVAL; ++ goto exit; ++ } ++ ++ if (sme->ssid_len > IW_ESSID_MAX_SIZE){ ++ ++ ret= -E2BIG; ++ goto exit; ++ } ++ ++ ++ _rtw_memset(&ndis_ssid, 0, sizeof(NDIS_802_11_SSID)); ++ ndis_ssid.SsidLength = sme->ssid_len; ++ _rtw_memcpy(ndis_ssid.Ssid, sme->ssid, sme->ssid_len); ++ ++ DBG_8192C("ssid=%s, len=%d\n", ndis_ssid.Ssid, sme->ssid_len); ++ ++ ++ if (sme->bssid) ++ printk("bssid="MAC_FMT"\n", MAC_ARG(sme->bssid)); ++ ++ ++ if(check_fwstate(pmlmepriv, _FW_UNDER_SURVEY|_FW_UNDER_LINKING) == _TRUE) ++ { ++ ret = -EBUSY; ++ printk("%s, fw_state=0x%x, goto exit\n", __FUNCTION__, pmlmepriv->fw_state); ++ goto exit; ++ } ++ ++ ++ _enter_critical_bh(&queue->lock, &irqL); ++ ++ phead = get_list_head(queue); ++ pmlmepriv->pscanned = get_next(phead); ++ ++ while (1) ++ { ++ if (rtw_end_of_queue_search(phead, pmlmepriv->pscanned) == _TRUE) ++ { ++ break; ++ } ++ ++ pnetwork = LIST_CONTAINOR(pmlmepriv->pscanned, struct wlan_network, list); ++ pmlmepriv->pscanned = get_next(pmlmepriv->pscanned); ++ ++ dst_ssid = pnetwork->network.Ssid.Ssid; ++ dst_bssid = pnetwork->network.MacAddress; ++ ++ if(sme->bssid) { ++ if(_rtw_memcmp(pnetwork->network.MacAddress, sme->bssid, ETH_ALEN) == _FALSE) ++ continue; ++ } ++ ++ if(sme->ssid && sme->ssid_len) { ++ if( pnetwork->network.Ssid.SsidLength != sme->ssid_len ++ || _rtw_memcmp(pnetwork->network.Ssid.Ssid, sme->ssid, sme->ssid_len) == _FALSE ++ ) ++ continue; ++ } ++ ++ ++ if (sme->bssid) ++ { ++ src_bssid = sme->bssid; ++ ++ if ((_rtw_memcmp(dst_bssid, src_bssid, ETH_ALEN)) == _TRUE) ++ { ++ printk("matched by bssid\n"); ++ ++ ndis_ssid.SsidLength = pnetwork->network.Ssid.SsidLength; ++ _rtw_memcpy(ndis_ssid.Ssid, pnetwork->network.Ssid.Ssid, pnetwork->network.Ssid.SsidLength); ++ ++ matched=_TRUE; ++ break; ++ } ++ ++ } ++ else if (sme->ssid && sme->ssid_len) ++ { ++ src_ssid = ndis_ssid.Ssid; ++ ++ if ((_rtw_memcmp(dst_ssid, src_ssid, ndis_ssid.SsidLength) == _TRUE) && ++ (pnetwork->network.Ssid.SsidLength==ndis_ssid.SsidLength)) ++ { ++ printk("matched by ssid\n"); ++ matched=_TRUE; ++ break; ++ } ++ } ++ ++ } ++ ++ _exit_critical_bh(&queue->lock, &irqL); ++ ++ if((matched == _FALSE) || (pnetwork== NULL)) ++ { ++ ret = -EBUSY; ++ printk("connect, matched == _FALSE, goto exit\n"); ++ goto exit; ++ } ++ ++ ++ if (rtw_set_802_11_infrastructure_mode(padapter, pnetwork->network.InfrastructureMode) == _FALSE) ++ { ++ ret = -EPERM; ++ goto exit; ++ } ++ ++ ++ psecuritypriv->ndisencryptstatus = Ndis802_11EncryptionDisabled; ++ psecuritypriv->dot11PrivacyAlgrthm = _NO_PRIVACY_; ++ psecuritypriv->dot118021XGrpPrivacy = _NO_PRIVACY_; ++ psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_Open; //open system ++ psecuritypriv->ndisauthtype = Ndis802_11AuthModeOpen; ++ ++ ++ ret = rtw_cfg80211_set_wpa_version(psecuritypriv, sme->crypto.wpa_versions); ++ if (ret < 0) ++ goto exit; ++ ++ ret = rtw_cfg80211_set_auth_type(psecuritypriv, sme->auth_type); ++ if (ret < 0) ++ goto exit; ++ ++ ++ if (sme->crypto.n_ciphers_pairwise) { ++ ret = rtw_cfg80211_set_cipher(psecuritypriv, sme->crypto.ciphers_pairwise[0], _TRUE); ++ if (ret < 0) ++ goto exit; ++ } ++ ++ //For WEP Shared auth ++ if(psecuritypriv->dot11AuthAlgrthm == dot11AuthAlgrthm_Shared ++ || psecuritypriv->dot11AuthAlgrthm == dot11AuthAlgrthm_Auto ++ ) ++ { ++ u32 wep_key_idx, wep_key_len,wep_total_len; ++ NDIS_802_11_WEP *pwep = NULL; ++ DBG_871X("%s(): Shared/Auto WEP\n",__FUNCTION__); ++ ++ wep_key_idx = sme->key_idx; ++ wep_key_len = sme->key_len; ++ ++ if (sme->key_idx > WEP_KEYS) { ++ ret = -EINVAL; ++ goto exit; ++ } ++ ++ if (wep_key_len > 0) ++ { ++ wep_key_len = wep_key_len <= 5 ? 5 : 13; ++ wep_total_len = wep_key_len + FIELD_OFFSET(NDIS_802_11_WEP, KeyMaterial); ++ pwep =(NDIS_802_11_WEP *) rtw_malloc(wep_total_len); ++ if(pwep == NULL){ ++ DBG_871X(" wpa_set_encryption: pwep allocate fail !!!\n"); ++ ret = -ENOMEM; ++ goto exit; ++ } ++ ++ _rtw_memset(pwep, 0, wep_total_len); ++ ++ pwep->KeyLength = wep_key_len; ++ pwep->Length = wep_total_len; ++ ++ if(wep_key_len==13) ++ { ++ padapter->securitypriv.dot11PrivacyAlgrthm=_WEP104_; ++ padapter->securitypriv.dot118021XGrpPrivacy=_WEP104_; ++ } ++ } ++ else { ++ ret = -EINVAL; ++ goto exit; ++ } ++ ++ pwep->KeyIndex = wep_key_idx; ++ pwep->KeyIndex |= 0x80000000; ++ ++ _rtw_memcpy(pwep->KeyMaterial, (void *)sme->key, pwep->KeyLength); ++ ++ if(rtw_set_802_11_add_wep(padapter, pwep) == (u8)_FAIL) ++ { ++ ret = -EOPNOTSUPP ; ++ } ++ ++ if (pwep) { ++ rtw_mfree((u8 *)pwep,wep_total_len); ++ } ++ ++ if(ret < 0) ++ goto exit; ++ } ++ ++ ret = rtw_cfg80211_set_cipher(psecuritypriv, sme->crypto.cipher_group, _FALSE); ++ if (ret < 0) ++ return ret; ++ ++ if (sme->crypto.n_akm_suites) { ++ ret = rtw_cfg80211_set_key_mgt(psecuritypriv, sme->crypto.akm_suites[0]); ++ if (ret < 0) ++ goto exit; ++ } ++ ++ printk("%s, ie_len=%d\n", __func__, sme->ie_len); ++ ++ ret = rtw_cfg80211_set_wpa_ie(padapter, sme->ie, sme->ie_len); ++ if (ret < 0) ++ goto exit; ++ ++ authmode = psecuritypriv->ndisauthtype; ++ rtw_set_802_11_authentication_mode(padapter, authmode); ++ ++ //rtw_set_802_11_encryption_mode(padapter, padapter->securitypriv.ndisencryptstatus); ++ ++ if (rtw_set_802_11_ssid(padapter, &ndis_ssid) == _FALSE) { ++ ret = -1; ++ goto exit; ++ } ++ ++ ++ printk("set ssid:dot11AuthAlgrthm=%d, dot11PrivacyAlgrthm=%d, dot118021XGrpPrivacy=%d\n", psecuritypriv->dot11AuthAlgrthm, psecuritypriv->dot11PrivacyAlgrthm, psecuritypriv->dot118021XGrpPrivacy); ++ ++exit: ++ ++ DBG_8192C("<=%s, ret %d\n",__FUNCTION__, ret); ++ ++ return ret; ++} ++ ++static int cfg80211_rtw_disconnect(struct wiphy *wiphy, struct net_device *dev, ++ u16 reason_code) ++{ ++ _adapter *padapter = wiphy_to_adapter(wiphy); ++ ++ printk("\n%s\n", __func__); ++ ++ if(check_fwstate(&padapter->mlmepriv, _FW_LINKED)) ++ { ++ rtw_disassoc_cmd(padapter); ++ ++ DBG_871X("%s...call rtw_indicate_disconnect\n ", __FUNCTION__); ++ ++ rtw_indicate_disconnect(padapter); ++ ++ rtw_free_assoc_resources(padapter, 1); ++ } ++ ++ return 0; ++} ++ ++static int cfg80211_rtw_set_txpower(struct wiphy *wiphy, ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,36)) ++ enum nl80211_tx_power_setting type, int mbm) ++#else // (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,36)) ++ enum tx_power_setting type, int dbm) ++#endif // (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,36)) ++{ ++#if 0 ++ struct iwm_priv *iwm = wiphy_to_iwm(wiphy); ++ int ret; ++ ++ switch (type) { ++ case NL80211_TX_POWER_AUTOMATIC: ++ return 0; ++ case NL80211_TX_POWER_FIXED: ++ if (mbm < 0 || (mbm % 100)) ++ return -EOPNOTSUPP; ++ ++ if (!test_bit(IWM_STATUS_READY, &iwm->status)) ++ return 0; ++ ++ ret = iwm_umac_set_config_fix(iwm, UMAC_PARAM_TBL_CFG_FIX, ++ CFG_TX_PWR_LIMIT_USR, ++ MBM_TO_DBM(mbm) * 2); ++ if (ret < 0) ++ return ret; ++ ++ return iwm_tx_power_trigger(iwm); ++ default: ++ IWM_ERR(iwm, "Unsupported power type: %d\n", type); ++ return -EOPNOTSUPP; ++ } ++#endif ++ printk("%s\n", __func__); ++ return 0; ++} ++ ++static int cfg80211_rtw_get_txpower(struct wiphy *wiphy, int *dbm) ++{ ++ //_adapter *padapter = wiphy_to_adapter(wiphy); ++ ++ printk("%s\n", __func__); ++ ++ *dbm = (12); ++ ++ return 0; ++} ++ ++static int cfg80211_rtw_set_power_mgmt(struct wiphy *wiphy, ++ struct net_device *dev, ++ bool enabled, int timeout) ++{ ++#if 0 ++ struct iwm_priv *iwm = wiphy_to_iwm(wiphy); ++ u32 power_index; ++ ++ if (enabled) ++ power_index = IWM_POWER_INDEX_DEFAULT; ++ else ++ power_index = IWM_POWER_INDEX_MIN; ++ ++ if (power_index == iwm->conf.power_index) ++ return 0; ++ ++ iwm->conf.power_index = power_index; ++ ++ return iwm_umac_set_config_fix(iwm, UMAC_PARAM_TBL_CFG_FIX, ++ CFG_POWER_INDEX, iwm->conf.power_index); ++#endif ++ ++ printk("%s\n", __func__); ++ ++ return 0; ++} ++ ++static int cfg80211_rtw_set_pmksa(struct wiphy *wiphy, ++ struct net_device *netdev, ++ struct cfg80211_pmksa *pmksa) ++{ ++ //struct iwm_priv *iwm = wiphy_to_iwm(wiphy); ++ _adapter *padapter = wiphy_to_adapter(wiphy); ++ ++ printk("%s\n", __func__); ++ ++ //return iwm_send_pmkid_update(iwm, pmksa, IWM_CMD_PMKID_ADD); ++ return 0; ++} ++ ++static int cfg80211_rtw_del_pmksa(struct wiphy *wiphy, ++ struct net_device *netdev, ++ struct cfg80211_pmksa *pmksa) ++{ ++ //struct iwm_priv *iwm = wiphy_to_iwm(wiphy); ++ _adapter *padapter = wiphy_to_adapter(wiphy); ++ ++ printk("%s\n", __func__); ++ ++ //return iwm_send_pmkid_update(iwm, pmksa, IWM_CMD_PMKID_DEL); ++ return 0; ++} ++ ++static int cfg80211_rtw_flush_pmksa(struct wiphy *wiphy, ++ struct net_device *netdev) ++{ ++ //struct iwm_priv *iwm = wiphy_to_iwm(wiphy); ++ _adapter *padapter = wiphy_to_adapter(wiphy); ++ struct cfg80211_pmksa pmksa; ++ ++ printk("%s\n", __func__); ++ ++ memset(&pmksa, 0, sizeof(struct cfg80211_pmksa)); ++ ++ ++ //return iwm_send_pmkid_update(iwm, &pmksa, IWM_CMD_PMKID_FLUSH); ++ return 0; ++} ++ ++#ifdef CONFIG_AP_MODE ++void rtw_cfg80211_indicate_sta_assoc(_adapter *padapter, u8 *pmgmt_frame, uint frame_len) ++{ ++ s32 freq; ++ int channel; ++ struct wireless_dev *pwdev = padapter->rtw_wdev; ++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); ++ ++ printk("%s\n", __func__); ++ ++ channel = pmlmeext->cur_channel; ++ ++ if (channel <= RTW_CH_MAX_2G_CHANNEL) ++ { ++ freq = rtw_ieee80211_channel_to_frequency(channel, IEEE80211_BAND_2GHZ); ++ } ++ else ++ { ++ freq = rtw_ieee80211_channel_to_frequency(channel, IEEE80211_BAND_5GHZ); ++ } ++ ++ ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) && !defined(CONFIG_CFG80211_FORCE_COMPATIBLE_2_6_37_UNDER) ++ cfg80211_rx_mgmt(padapter->pnetdev, freq, pmgmt_frame, frame_len, GFP_ATOMIC); ++#else ++ //to avoid WARN_ON(wdev->iftype != NL80211_IFTYPE_STATION) when calling cfg80211_send_rx_assoc() ++ pwdev->iftype = NL80211_IFTYPE_STATION; ++ cfg80211_send_rx_assoc(padapter->pnetdev, pmgmt_frame, frame_len); ++ pwdev->iftype = NL80211_IFTYPE_AP; ++ //cfg80211_rx_action(padapter->pnetdev, freq, pmgmt_frame, frame_len, GFP_ATOMIC); ++#endif ++ ++} ++ ++void rtw_cfg80211_indicate_sta_disassoc(_adapter *padapter, unsigned char *da, unsigned short reason) ++{ ++ s32 freq; ++ int channel; ++ u8 *pmgmt_frame; ++ uint frame_len; ++ struct rtw_ieee80211_hdr *pwlanhdr; ++ unsigned short *fctrl; ++ u8 mgmt_buf[128] = {0}; ++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ ++ ++ printk("%s\n", __func__); ++ ++ channel = pmlmeext->cur_channel; ++ ++ if (channel <= RTW_CH_MAX_2G_CHANNEL) ++ { ++ freq = rtw_ieee80211_channel_to_frequency(channel, IEEE80211_BAND_2GHZ); ++ } ++ else ++ { ++ freq = rtw_ieee80211_channel_to_frequency(channel, IEEE80211_BAND_5GHZ); ++ } ++ ++ ++ pmgmt_frame = mgmt_buf; ++ pwlanhdr = (struct rtw_ieee80211_hdr *)pmgmt_frame; ++ ++ fctrl = &(pwlanhdr->frame_ctl); ++ *(fctrl) = 0; ++ ++ //_rtw_memcpy(pwlanhdr->addr1, da, ETH_ALEN); ++ //_rtw_memcpy(pwlanhdr->addr2, myid(&(padapter->eeprompriv)), ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr1, myid(&(padapter->eeprompriv)), ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr2, da, ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr3, get_my_bssid(&(pmlmeinfo->network)), ETH_ALEN); ++ ++ SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); ++ pmlmeext->mgnt_seq++; ++ SetFrameSubType(pmgmt_frame, WIFI_DEAUTH); ++ ++ pmgmt_frame += sizeof(struct rtw_ieee80211_hdr_3addr); ++ frame_len = sizeof(struct rtw_ieee80211_hdr_3addr); ++ ++ reason = cpu_to_le16(reason); ++ pmgmt_frame = rtw_set_fixed_ie(pmgmt_frame, _RSON_CODE_ , (unsigned char *)&reason, &frame_len); ++ ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) && !defined(CONFIG_CFG80211_FORCE_COMPATIBLE_2_6_37_UNDER) ++ cfg80211_rx_mgmt(padapter->pnetdev, freq, mgmt_buf, frame_len, GFP_ATOMIC); ++#else ++ cfg80211_send_disassoc(padapter->pnetdev, mgmt_buf, frame_len); ++ //cfg80211_rx_action(padapter->pnetdev, freq, mgmt_buf, frame_len, GFP_ATOMIC); ++#endif ++ ++} ++ ++static int rtw_cfg80211_monitor_if_open(struct net_device *ndev) ++{ ++ int ret = 0; ++ ++ printk("%s\n", __func__); ++ ++ return ret; ++} ++ ++static int rtw_cfg80211_monitor_if_close(struct net_device *ndev) ++{ ++ int ret = 0; ++ ++ printk("%s\n", __func__); ++ ++ return ret; ++} ++ ++static int rtw_cfg80211_monitor_if_xmit_entry(struct sk_buff *skb, struct net_device *ndev) ++{ ++ int ret = 0; ++ int rtap_len; ++ int qos_len = 0; ++ int dot11_hdr_len = 24; ++ int snap_len = 6; ++ unsigned char *pdata; ++ unsigned short frame_ctl; ++ unsigned char src_mac_addr[6]; ++ unsigned char dst_mac_addr[6]; ++ struct ieee80211_hdr *dot11_hdr; ++ struct ieee80211_radiotap_header *rtap_hdr; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(ndev); ++ ++ printk("%s\n", __func__); ++ ++ if (unlikely(skb->len < sizeof(struct ieee80211_radiotap_header))) ++ goto fail; ++ ++ rtap_hdr = (struct ieee80211_radiotap_header *)skb->data; ++ if (unlikely(rtap_hdr->it_version)) ++ goto fail; ++ ++ rtap_len = ieee80211_get_radiotap_len(skb->data); ++ if (unlikely(skb->len < rtap_len)) ++ goto fail; ++ ++ if(rtap_len != 14) ++ { ++ printk("radiotap len (should be 14): %d\n", rtap_len); ++ goto fail; ++ } ++ ++ /* Skip the ratio tap header */ ++ skb_pull(skb, rtap_len); ++ ++ dot11_hdr = (struct ieee80211_hdr *)skb->data; ++ frame_ctl = le16_to_cpu(dot11_hdr->frame_control); ++ /* Check if the QoS bit is set */ ++ if ((frame_ctl & IEEE80211_FCTL_FTYPE) == IEEE80211_FTYPE_DATA) { ++ /* Check if this ia a Wireless Distribution System (WDS) frame ++ * which has 4 MAC addresses ++ */ ++ if (dot11_hdr->frame_control & 0x0080) ++ qos_len = 2; ++ if ((dot11_hdr->frame_control & 0x0300) == 0x0300) ++ dot11_hdr_len += 6; ++ ++ memcpy(dst_mac_addr, dot11_hdr->addr1, sizeof(dst_mac_addr)); ++ memcpy(src_mac_addr, dot11_hdr->addr2, sizeof(src_mac_addr)); ++ ++ /* Skip the 802.11 header, QoS (if any) and SNAP, but leave spaces for ++ * for two MAC addresses ++ */ ++ skb_pull(skb, dot11_hdr_len + qos_len + snap_len - sizeof(src_mac_addr) * 2); ++ pdata = (unsigned char*)skb->data; ++ memcpy(pdata, dst_mac_addr, sizeof(dst_mac_addr)); ++ memcpy(pdata + sizeof(dst_mac_addr), src_mac_addr, sizeof(src_mac_addr)); ++ ++ printk("should be eapol packet\n"); ++ ++ /* Use the real net device to transmit the packet */ ++ ret = rtw_xmit_entry(skb, padapter->pnetdev); ++ ++ return ret; ++ ++ } ++ else if((frame_ctl & (IEEE80211_FCTL_FTYPE|IEEE80211_FCTL_STYPE)) == cpu_to_le16(IEEE80211_STYPE_ACTION)) ++ { ++ //only for action frames ++ struct xmit_frame *pmgntframe; ++ struct pkt_attrib *pattrib; ++ unsigned char *pframe; ++ //u8 category, action, OUI_Subtype, dialogToken=0; ++ //unsigned char *frame_body; ++ struct rtw_ieee80211_hdr *pwlanhdr; ++ struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); ++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); ++ u8 *buf = skb->data; ++ u32 len = skb->len; ++ ++ if(rtw_p2p_check_frames(padapter, buf, len, _TRUE) < 0) ++ { ++ goto fail; ++ } ++ ++/* ++ frame_body = (unsigned char *)(buf + sizeof(struct rtw_ieee80211_hdr_3addr)); ++ category = frame_body[0]; ++ //just for check ++ if(category == RTW_WLAN_CATEGORY_PUBLIC) ++ { ++ action = frame_body[ 1 ]; ++ OUI_Subtype = frame_body[ 6 ]; ++ dialogToken = frame_body[7]; ++ ++ if ( action == ACT_PUBLIC_P2P ) ++ { ++ printk("ACTION_CATEGORY_PUBLIC: ACT_PUBLIC_P2P, OUI=0x%x, OUI_Subtype=%d, dialogToken=%d\n", ++ cpu_to_be32( *( ( u32* ) ( frame_body + 2 ) ) ), OUI_Subtype, dialogToken); ++ } ++ else ++ { ++ printk("ACTION_CATEGORY_PUBLIC: action=%d, OUI=0x%x, OUI_Subtype=%d, dialogToken=%d\n", ++ action, cpu_to_be32( *( ( u32* ) ( frame_body + 2 ) ) ), OUI_Subtype, dialogToken); ++ } ++ ++ } ++ else if(category == RTW_WLAN_CATEGORY_P2P) ++ { ++ OUI_Subtype = frame_body[5]; ++ dialogToken = frame_body[6]; ++ ++ printk("ACTION_CATEGORY_P2P: OUI=0x%x, OUI_Subtype=%d, dialogToken=%d\n", ++ cpu_to_be32( *( ( u32* ) ( frame_body + 1 ) ) ), OUI_Subtype, dialogToken); ++ ++ } ++ else ++ { ++ printk("%s, action frame category=%d, drop!\n", __func__, category); ++ goto fail; ++ } ++*/ ++ ++ //starting alloc mgmt frame to dump it ++ if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL) ++ { ++ goto fail; ++ } ++ ++ //update attribute ++ pattrib = &pmgntframe->attrib; ++ update_mgntframe_attrib(padapter, pattrib); ++ pattrib->retry_ctrl = _FALSE; ++ ++ _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); ++ ++ pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; ++ ++ _rtw_memcpy(pframe, (void*)buf, len); ++ pattrib->pktlen = len; ++ ++ pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; ++ //update seq number ++ pmlmeext->mgnt_seq = GetSequence(pwlanhdr); ++ pattrib->seqnum = pmlmeext->mgnt_seq; ++ pmlmeext->mgnt_seq++; ++ ++ ++ pattrib->last_txcmdsz = pattrib->pktlen; ++ ++ dump_mgntframe(padapter, pmgntframe); ++ ++ ++ } ++ else ++ { ++ printk("frame_ctl=0x%x\n", frame_ctl & (IEEE80211_FCTL_FTYPE|IEEE80211_FCTL_STYPE)); ++ } ++ ++ ++fail: ++ ++ dev_kfree_skb(skb); ++ ++ return 0; ++ ++} ++ ++static void rtw_cfg80211_monitor_if_set_multicast_list(struct net_device *ndev) ++{ ++ printk("%s\n", __func__); ++} ++ ++static int rtw_cfg80211_monitor_if_set_mac_address(struct net_device *ndev, void *addr) ++{ ++ int ret = 0; ++ ++ printk("%s\n", __func__); ++ ++ return ret; ++} ++ ++#if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,29)) ++static const struct net_device_ops rtw_cfg80211_monitor_if_ops = { ++ .ndo_open = rtw_cfg80211_monitor_if_open, ++ .ndo_stop = rtw_cfg80211_monitor_if_close, ++ .ndo_start_xmit = rtw_cfg80211_monitor_if_xmit_entry, ++ .ndo_set_multicast_list = rtw_cfg80211_monitor_if_set_multicast_list, ++ .ndo_set_mac_address = rtw_cfg80211_monitor_if_set_mac_address, ++}; ++#endif ++ ++static struct net_device *rtw_cfg80211_add_monitor_if(_adapter *padapter, char *name) ++{ ++ int ret = 0; ++ struct net_device* ndev = NULL; ++ struct rtw_netdev_priv_indicator *pnpi; ++ struct rtw_wdev_priv *pwdev_priv = wdev_to_priv(padapter->rtw_wdev); ++ ++ printk("%s\n", __func__); ++ ++ if (!name ) { ++ ret = -EINVAL; ++ goto out; ++ } ++ ++ if((strnicmp(name, pwdev_priv->ifname_mon, strlen(name)) ==0) ++ && pwdev_priv->pmon_ndev) ++ { ++ ndev = pwdev_priv->pmon_ndev; ++ ++ printk("%s, monitor interface(%s) has existed\n", __func__, name); ++ ++ goto out; ++ } ++ ++ ++ ndev = alloc_etherdev(sizeof(struct rtw_netdev_priv_indicator)); ++ if (!ndev) { ++ ret = -ENOMEM; ++ goto out; ++ } ++ ++ ndev->type = ARPHRD_IEEE80211_RADIOTAP; ++ strncpy(ndev->name, name, IFNAMSIZ); ++ ndev->name[IFNAMSIZ - 1] = 0; ++ ++#if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,29)) ++ ndev->netdev_ops = &rtw_cfg80211_monitor_if_ops; ++#else ++ ndev->open = rtw_cfg80211_monitor_if_open; ++ ndev->stop = rtw_cfg80211_monitor_if_close; ++ ndev->hard_start_xmit = rtw_cfg80211_monitor_if_xmit_entry; ++ ndev->set_mac_address = rtw_cfg80211_monitor_if_set_mac_address; ++#endif ++ ++ pnpi = netdev_priv(ndev); ++ pnpi->priv = padapter; ++ pnpi->sizeof_priv = sizeof(_adapter); ++ ++ ret = register_netdevice(ndev); ++ if (ret) { ++ goto out; ++ } ++ ++ pwdev_priv->pmon_ndev = ndev; ++ _rtw_memcpy(pwdev_priv->ifname_mon, name, IFNAMSIZ+1); ++ ++out: ++ if (ret && ndev) ++ { ++ free_netdev(ndev); ++ ndev = NULL; ++ } ++ ++ ++ printk("%s, ndev=%p, pmon_ndev=%p, ret=%d\n", __func__, ndev, pwdev_priv->pmon_ndev, ret); ++ ++ return ndev; ++} ++ ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,38)) ++static struct net_device * cfg80211_rtw_add_virtual_intf(struct wiphy *wiphy, char *name, ++#else // (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,38)) ++static int cfg80211_rtw_add_virtual_intf(struct wiphy *wiphy, char *name, ++#endif // (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,38)) ++ enum nl80211_iftype type, u32 *flags, ++ struct vif_params *params) ++{ ++ struct net_device* ndev = NULL; ++ _adapter *padapter = wiphy_to_adapter(wiphy); ++ ++ printk("%s, ifname=%s, type=%d\n", __func__, name, type); ++ ++ ++ switch (type) { ++ case NL80211_IFTYPE_ADHOC: ++ case NL80211_IFTYPE_AP_VLAN: ++ case NL80211_IFTYPE_WDS: ++ case NL80211_IFTYPE_MESH_POINT: ++ ++ break; ++ case NL80211_IFTYPE_MONITOR: ++ ndev = rtw_cfg80211_add_monitor_if(padapter, name); ++ break; ++ ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) ++ case NL80211_IFTYPE_P2P_CLIENT: ++#endif ++ case NL80211_IFTYPE_STATION: ++ ++ break; ++ ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) ++ case NL80211_IFTYPE_P2P_GO: ++#endif ++ case NL80211_IFTYPE_AP: ++ ++ break; ++ default: ++ printk("Unsupported interface type\n"); ++ break; ++ } ++ ++ printk("ndev=%p\n", ndev); ++ ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,38)) ++ return ndev; ++#else // (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,38)) ++ return 0; ++#endif // (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,38)) ++ ++} ++ ++static int cfg80211_rtw_del_virtual_intf(struct wiphy *wiphy, struct net_device *dev) ++{ ++ _adapter *padapter = wiphy_to_adapter(wiphy); ++ struct rtw_wdev_priv *pwdev_priv = (struct rtw_wdev_priv *)wiphy_priv(wiphy); ++ ++ printk("%s\n", __func__); ++ ++ if(dev) ++ { ++ unregister_netdev(dev); ++ ++ free_netdev(dev); ++ ++ if(dev == pwdev_priv->pmon_ndev) ++ { ++ printk("remove monitor interface\n"); ++ pwdev_priv->pmon_ndev = NULL; ++ pwdev_priv->ifname_mon[0] = '\0'; ++ } ++ } ++ ++ return 0; ++} ++ ++static int cfg80211_rtw_add_beacon(struct wiphy *wiphy, struct net_device *dev, ++ struct beacon_parameters *info) ++{ ++ int ret=0; ++ u8 *pbuf = NULL; ++ uint len, wps_ielen=0; ++ uint p2p_ielen=0; ++ u8 *p2p_ie; ++ _adapter *padapter = wiphy_to_adapter(wiphy); ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ //struct sta_priv *pstapriv = &padapter->stapriv; ++ ++ ++ printk("%s, beacon_head_len=%d, beacon_tail_len=%d\n", __FUNCTION__, info->head_len, info->tail_len); ++ ++ ++ if(check_fwstate(pmlmepriv, WIFI_AP_STATE) != _TRUE) ++ return -EINVAL; ++ ++ if(info->head_len<24) ++ return -EINVAL; ++ ++ ++ pbuf = rtw_zmalloc(info->head_len+info->tail_len); ++ if(!pbuf) ++ return -ENOMEM; ++ ++ ++ //_rtw_memcpy(&pstapriv->max_num_sta, param->u.bcn_ie.reserved, 2); ++ ++ //if((pstapriv->max_num_sta>NUM_STA) || (pstapriv->max_num_sta<=0)) ++ // pstapriv->max_num_sta = NUM_STA; ++ ++ ++ _rtw_memcpy(pbuf, info->head+24, info->head_len-24);// 24=beacon header len. ++ _rtw_memcpy(pbuf+info->head_len-24, info->tail, info->tail_len); ++ ++ len = info->head_len+info->tail_len-24; ++ ++ //check wps ie if inclued ++ if(rtw_get_wps_ie(pbuf+_FIXED_IE_LENGTH_, len-_FIXED_IE_LENGTH_, NULL, &wps_ielen)) ++ printk("add bcn, wps_ielen=%d\n", wps_ielen); ++ ++ ++ //check p2p ie if inclued ++ if(rtw_get_p2p_ie(pbuf+_FIXED_IE_LENGTH_, len-_FIXED_IE_LENGTH_, NULL, &p2p_ielen)) ++ printk("got p2p_ie, len=%d\n", p2p_ielen); ++ ++ ++ ++ // pbss_network->IEs will not include p2p_ie ++ if(rtw_check_beacon_data(padapter, pbuf, len-p2p_ielen) == _SUCCESS) ++ //if(rtw_check_beacon_data(padapter, pbuf, len) == _SUCCESS) ++ { ++#ifdef CONFIG_P2P ++ //check p2p if enable ++ if((p2p_ie=rtw_get_p2p_ie(pbuf+_FIXED_IE_LENGTH_, len-_FIXED_IE_LENGTH_, NULL, &p2p_ielen))) ++ { ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct wifidirect_info *pwdinfo= &(padapter->wdinfo); ++ ++ if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) ++ { ++ printk("Enable P2P function for the first time\n"); ++ rtw_p2p_enable(padapter, P2P_ROLE_GO); ++ wdev_to_priv(padapter->rtw_wdev)->p2p_enabled = _TRUE; ++ } ++ else ++ { ++ _cancel_timer_ex( &pwdinfo->find_phase_timer ); ++ _cancel_timer_ex( &pwdinfo->restore_p2p_state_timer ); ++ _cancel_timer_ex( &pwdinfo->pre_tx_scan_timer); ++ ++ printk("enter GO Mode, p2p_ielen=%d\n", p2p_ielen); ++ ++ rtw_p2p_set_role(pwdinfo, P2P_ROLE_GO); ++ rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_OK); ++ pwdinfo->intent = 15; ++ } ++ ++ pwdinfo->operating_channel = pmlmeext->cur_channel; ++ ++ } ++#endif //CONFIG_P2P ++ ++ ret = 0; ++ ++ } ++ else ++ { ++ ret = -EINVAL; ++ } ++ ++ ++ rtw_mfree(pbuf, info->head_len+info->tail_len); ++ ++ return ret; ++ ++} ++ ++static int cfg80211_rtw_set_beacon(struct wiphy *wiphy, struct net_device *dev, ++ struct beacon_parameters *info) ++{ ++ _adapter *padapter = wiphy_to_adapter(wiphy); ++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); ++ ++ printk("%s\n", __func__); ++ ++ pmlmeext->bstart_bss = _TRUE; ++ ++ cfg80211_rtw_add_beacon(wiphy, dev, info); ++ ++ return 0; ++} ++ ++static int cfg80211_rtw_del_beacon(struct wiphy *wiphy, struct net_device *dev) ++{ ++ printk("%s\n", __func__); ++ ++ return 0; ++} ++ ++ ++static int cfg80211_rtw_add_station(struct wiphy *wiphy, struct net_device *dev, ++ u8 *mac, struct station_parameters *params) ++{ ++ printk("%s\n", __func__); ++ ++ return 0; ++} ++ ++static int cfg80211_rtw_del_station(struct wiphy *wiphy, struct net_device *dev, ++ u8 *mac) ++{ ++ int ret=0; ++ _irqL irqL; ++ _list *phead, *plist; ++ struct sta_info *psta = NULL; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ ++ printk("+%s\n", __func__); ++ ++ if(check_fwstate(pmlmepriv, (_FW_LINKED|WIFI_AP_STATE)) != _TRUE) ++ { ++ printk("%s, fw_state != FW_LINKED|WIFI_AP_STATE\n", __func__); ++ return -EINVAL; ++ } ++ ++ ++ if(!mac) ++ { ++ printk("flush all sta, and cam_entry\n"); ++ ++ flush_all_cam_entry(padapter); //clear CAM ++ ++ ret = rtw_sta_flush(padapter); ++ ++ return ret; ++ } ++ ++ ++ printk("free sta macaddr =" MAC_FMT "\n", MAC_ARG(mac)); ++ ++ if (mac[0] == 0xff && mac[1] == 0xff && ++ mac[2] == 0xff && mac[3] == 0xff && ++ mac[4] == 0xff && mac[5] == 0xff) ++ { ++ return -EINVAL; ++ } ++ ++ ++ _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL); ++ ++ phead = &pstapriv->asoc_list; ++ plist = get_next(phead); ++ ++ //check asoc_queue ++ while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) ++ { ++ psta = LIST_CONTAINOR(plist, struct sta_info, asoc_list); ++ ++ plist = get_next(plist); ++ ++ if(_rtw_memcmp(mac, psta->hwaddr, ETH_ALEN)) ++ { ++ if(psta->dot8021xalg == 1 && psta->bpairwise_key_installed == _FALSE) ++ { ++ DBG_8192C("%s, sta's dot8021xalg = 1 and key_installed = _FALSE\n", __func__); ++ } ++ else ++ { ++ DBG_8192C("free psta=%p, aid=%d\n", psta, psta->aid); ++ ++ rtw_list_delete(&psta->asoc_list); ++ ++ //_exit_critical_bh(&pstapriv->asoc_list_lock, &irqL); ++ ap_free_sta(padapter, psta); ++ //_enter_critical_bh(&pstapriv->asoc_list_lock, &irqL); ++ ++ psta = NULL; ++ ++ break; ++ } ++ ++ } ++ ++ } ++ ++ _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL); ++ ++ ++#if 0 ++ psta = rtw_get_stainfo(pstapriv, mac); ++ if(psta) ++ { ++ //DBG_8192C("free psta=%p, aid=%d\n", psta, psta->aid); ++ ++ _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL); ++ if(rtw_is_list_empty(&psta->asoc_list)==_FALSE) ++ { ++ rtw_list_delete(&psta->asoc_list); ++ ap_free_sta(padapter, psta); ++ ++ psta = NULL; ++ ++ } ++ _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL); ++ ++ } ++ else ++ { ++ DBG_8192C("cfg80211_rtw_del_station(), sta has already been removed or never been added\n"); ++ ++ //ret = -1; ++ } ++#endif ++ ++ printk("-%s\n", __func__); ++ ++ return ret; ++ ++} ++ ++static int cfg80211_rtw_change_station(struct wiphy *wiphy, struct net_device *dev, ++ u8 *mac, struct station_parameters *params) ++{ ++ printk("%s\n", __func__); ++ ++ return 0; ++} ++ ++static int cfg80211_rtw_dump_station(struct wiphy *wiphy, struct net_device *dev, ++ int idx, u8 *mac, struct station_info *sinfo) ++{ ++ printk("%s\n", __func__); ++ ++ return 0; ++} ++ ++static int cfg80211_rtw_change_bss(struct wiphy *wiphy, struct net_device *dev, ++ struct bss_parameters *params) ++{ ++ u8 i; ++ ++ printk("%s\n", __func__); ++/* ++ printk("use_cts_prot=%d\n", params->use_cts_prot); ++ printk("use_short_preamble=%d\n", params->use_short_preamble); ++ printk("use_short_slot_time=%d\n", params->use_short_slot_time); ++ printk("ap_isolate=%d\n", params->ap_isolate); ++ ++ printk("basic_rates_len=%d\n", params->basic_rates_len); ++ for(i=0; ibasic_rates_len; i++) ++ { ++ printk("basic_rates=%d\n", params->basic_rates[i]); ++ ++ } ++*/ ++ return 0; ++ ++} ++ ++static int cfg80211_rtw_set_channel(struct wiphy *wiphy, struct net_device *dev, ++ struct ieee80211_channel *chan, ++ enum nl80211_channel_type channel_type) ++{ ++ printk("%s\n", __func__); ++ ++ return 0; ++} ++ ++static int cfg80211_rtw_auth(struct wiphy *wiphy, struct net_device *dev, ++ struct cfg80211_auth_request *req) ++{ ++ printk("%s\n", __func__); ++ ++ return 0; ++} ++ ++static int cfg80211_rtw_assoc(struct wiphy *wiphy, struct net_device *dev, ++ struct cfg80211_assoc_request *req) ++{ ++ printk("%s\n", __func__); ++ ++ return 0; ++} ++#endif //CONFIG_AP_MODE ++ ++void rtw_cfg80211_rx_action_p2p(_adapter *padapter, u8 *pmgmt_frame, uint frame_len) ++{ ++ s32 freq; ++ int channel; ++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); ++ ++#ifdef CONFIG_DEBUG_CFG80211 ++ printk("%s\n", __func__); ++#endif ++ ++ rtw_p2p_check_frames(padapter, pmgmt_frame, frame_len, _FALSE); ++ ++ channel = pmlmeext->cur_channel; ++ ++ if (channel <= RTW_CH_MAX_2G_CHANNEL) ++ { ++ freq = rtw_ieee80211_channel_to_frequency(channel, IEEE80211_BAND_2GHZ); ++ } ++ else ++ { ++ freq = rtw_ieee80211_channel_to_frequency(channel, IEEE80211_BAND_5GHZ); ++ } ++ ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) ++ cfg80211_rx_mgmt(padapter->pnetdev, freq, pmgmt_frame, frame_len, GFP_ATOMIC); ++#else ++ cfg80211_rx_action(padapter->pnetdev, freq, pmgmt_frame, frame_len, GFP_ATOMIC); ++#endif ++ ++} ++ ++void rtw_cfg80211_rx_p2p_action_public(_adapter *padapter, u8 *pmgmt_frame, uint frame_len) ++{ ++ s32 freq; ++ int channel; ++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); ++ ++#ifdef CONFIG_DEBUG_CFG80211 ++ printk("%s\n", __func__); ++#endif ++ ++ rtw_p2p_check_frames(padapter, pmgmt_frame, frame_len, _FALSE); ++ ++ channel = pmlmeext->cur_channel; ++ ++ if (channel <= RTW_CH_MAX_2G_CHANNEL) ++ { ++ freq = rtw_ieee80211_channel_to_frequency(channel, IEEE80211_BAND_2GHZ); ++ } ++ else ++ { ++ freq = rtw_ieee80211_channel_to_frequency(channel, IEEE80211_BAND_5GHZ); ++ } ++ ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) ++ cfg80211_rx_mgmt(padapter->pnetdev, freq, pmgmt_frame, frame_len, GFP_ATOMIC); ++#else ++ cfg80211_rx_action(padapter->pnetdev, freq, pmgmt_frame, frame_len, GFP_ATOMIC); ++#endif ++ ++} ++ ++void rtw_cfg80211_issue_p2p_provision_request(_adapter *padapter, const u8 *buf, size_t len) ++{ ++ u16 wps_devicepassword_id = 0x0000; ++ uint wps_devicepassword_id_len = 0; ++ u8 wpsie[ 255 ] = { 0x00 }, p2p_ie[ 255 ] = { 0x00 }; ++ uint p2p_ielen = 0; ++ uint wpsielen = 0; ++ u32 devinfo_contentlen = 0; ++ u8 devinfo_content[64] = { 0x00 }; ++ u16 capability = 0; ++ uint capability_len = 0; ++ ++ unsigned char category = RTW_WLAN_CATEGORY_PUBLIC; ++ u8 action = P2P_PUB_ACTION_ACTION; ++ u8 dialogToken = 1; ++ u32 p2poui = cpu_to_be32(P2POUI); ++ u8 oui_subtype = P2P_PROVISION_DISC_REQ; ++ u32 p2pielen = 0; ++#ifdef CONFIG_WFD ++ u32 wfdielen = 0; ++#endif //CONFIG_WFD ++ ++ struct xmit_frame *pmgntframe; ++ struct pkt_attrib *pattrib; ++ unsigned char *pframe; ++ struct rtw_ieee80211_hdr *pwlanhdr; ++ unsigned short *fctrl; ++ struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); ++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ ++ struct wifidirect_info *pwdinfo = &(padapter->wdinfo); ++ u8 *frame_body = (unsigned char *)(buf + sizeof(struct rtw_ieee80211_hdr_3addr)); ++ size_t frame_body_len = len - sizeof(struct rtw_ieee80211_hdr_3addr); ++ ++ ++ DBG_871X( "[%s] In\n", __FUNCTION__ ); ++ ++ //prepare for building provision_request frame ++ _rtw_memcpy(pwdinfo->tx_prov_disc_info.peerIFAddr, GetAddr1Ptr(buf), ETH_ALEN); ++ _rtw_memcpy(pwdinfo->tx_prov_disc_info.peerDevAddr, GetAddr1Ptr(buf), ETH_ALEN); ++ ++ pwdinfo->tx_prov_disc_info.wps_config_method_request = WPS_CM_PUSH_BUTTON; ++ ++ rtw_get_wps_ie( frame_body + _PUBLIC_ACTION_IE_OFFSET_, frame_body_len - _PUBLIC_ACTION_IE_OFFSET_, wpsie, &wpsielen); ++ rtw_get_wps_attr_content( wpsie, wpsielen, WPS_ATTR_DEVICE_PWID, (u8*) &wps_devicepassword_id, &wps_devicepassword_id_len); ++ wps_devicepassword_id = be16_to_cpu( wps_devicepassword_id ); ++ ++ switch(wps_devicepassword_id) ++ { ++ case WPS_DPID_PIN: ++ pwdinfo->tx_prov_disc_info.wps_config_method_request = WPS_CM_LABEL; ++ break; ++ case WPS_DPID_USER_SPEC: ++ pwdinfo->tx_prov_disc_info.wps_config_method_request = WPS_CM_DISPLYA; ++ break; ++ case WPS_DPID_MACHINE_SPEC: ++ break; ++ case WPS_DPID_REKEY: ++ break; ++ case WPS_DPID_PBC: ++ pwdinfo->tx_prov_disc_info.wps_config_method_request = WPS_CM_PUSH_BUTTON; ++ break; ++ case WPS_DPID_REGISTRAR_SPEC: ++ pwdinfo->tx_prov_disc_info.wps_config_method_request = WPS_CM_KEYPAD; ++ break; ++ default: ++ break; ++ } ++ ++ ++ if ( rtw_get_p2p_ie( frame_body + _PUBLIC_ACTION_IE_OFFSET_, frame_body_len - _PUBLIC_ACTION_IE_OFFSET_, p2p_ie, &p2p_ielen ) ) ++ { ++ ++ rtw_get_p2p_attr_content( p2p_ie, p2p_ielen, P2P_ATTR_DEVICE_INFO, devinfo_content, &devinfo_contentlen); ++ rtw_get_p2p_attr_content( p2p_ie, p2p_ielen, P2P_ATTR_CAPABILITY, (u8*)&capability, &capability_len); ++ ++ } ++ ++ ++ //start to build provision_request frame ++ _rtw_memset(wpsie, 0, sizeof(wpsie)); ++ _rtw_memset(p2p_ie, 0, sizeof(p2p_ie)); ++ p2p_ielen = 0; ++ ++ if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL) ++ { ++ return; ++ } ++ ++ ++ //update attribute ++ pattrib = &pmgntframe->attrib; ++ update_mgntframe_attrib(padapter, pattrib); ++ ++ _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); ++ ++ pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; ++ pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; ++ ++ fctrl = &(pwlanhdr->frame_ctl); ++ *(fctrl) = 0; ++ ++ _rtw_memcpy(pwlanhdr->addr1, pwdinfo->tx_prov_disc_info.peerIFAddr, ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr2, myid(&(padapter->eeprompriv)), ETH_ALEN); ++ _rtw_memcpy(pwlanhdr->addr3, pwdinfo->tx_prov_disc_info.peerIFAddr, ETH_ALEN); ++ ++ SetSeqNum(pwlanhdr, pmlmeext->mgnt_seq); ++ pmlmeext->mgnt_seq++; ++ SetFrameSubType(pframe, WIFI_ACTION); ++ ++ pframe += sizeof(struct rtw_ieee80211_hdr_3addr); ++ pattrib->pktlen = sizeof(struct rtw_ieee80211_hdr_3addr); ++ ++ pframe = rtw_set_fixed_ie(pframe, 1, &(category), &(pattrib->pktlen)); ++ pframe = rtw_set_fixed_ie(pframe, 1, &(action), &(pattrib->pktlen)); ++ pframe = rtw_set_fixed_ie(pframe, 4, (unsigned char *) &(p2poui), &(pattrib->pktlen)); ++ pframe = rtw_set_fixed_ie(pframe, 1, &(oui_subtype), &(pattrib->pktlen)); ++ pframe = rtw_set_fixed_ie(pframe, 1, &(dialogToken), &(pattrib->pktlen)); ++ ++ ++ //build_prov_disc_request_p2p_ie ++ // P2P OUI ++ p2pielen = 0; ++ p2p_ie[ p2pielen++ ] = 0x50; ++ p2p_ie[ p2pielen++ ] = 0x6F; ++ p2p_ie[ p2pielen++ ] = 0x9A; ++ p2p_ie[ p2pielen++ ] = 0x09; // WFA P2P v1.0 ++ ++ // Commented by Albert 20110301 ++ // According to the P2P Specification, the provision discovery request frame should contain 3 P2P attributes ++ // 1. P2P Capability ++ // 2. Device Info ++ // 3. Group ID ( When joining an operating P2P Group ) ++ ++ // P2P Capability ATTR ++ // Type: ++ p2p_ie[ p2pielen++ ] = P2P_ATTR_CAPABILITY; ++ ++ // Length: ++ //*(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 0x0002 ); ++ RTW_PUT_LE16(p2p_ie + p2pielen, 0x0002); ++ p2pielen += 2; ++ ++ // Value: ++ // Device Capability Bitmap, 1 byte ++ // Be able to participate in additional P2P Groups and ++ // support the P2P Invitation Procedure ++ _rtw_memcpy(p2p_ie + p2pielen, &capability, 2); ++ p2pielen += 2; ++ ++ ++ // Device Info ATTR ++ // Type: ++ p2p_ie[ p2pielen++ ] = P2P_ATTR_DEVICE_INFO; ++ ++ // Length: ++ // 21 -> P2P Device Address (6bytes) + Config Methods (2bytes) + Primary Device Type (8bytes) ++ // + NumofSecondDevType (1byte) + WPS Device Name ID field (2bytes) + WPS Device Name Len field (2bytes) ++ //*(u16*) ( p2pie + p2pielen ) = cpu_to_le16( 21 + pwdinfo->device_name_len ); ++ RTW_PUT_LE16(p2p_ie + p2pielen, devinfo_contentlen); ++ p2pielen += 2; ++ ++ // Value: ++ _rtw_memcpy(p2p_ie + p2pielen, devinfo_content, devinfo_contentlen); ++ p2pielen += devinfo_contentlen; ++ ++ ++ pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, p2pielen, (unsigned char *) p2p_ie, &p2p_ielen); ++ //p2pielen = build_prov_disc_request_p2p_ie( pwdinfo, pframe, NULL, 0, pwdinfo->tx_prov_disc_info.peerDevAddr); ++ //pframe += p2pielen; ++ pattrib->pktlen += p2p_ielen; ++ ++ wpsielen = 0; ++ // WPS OUI ++ *(u32*) ( wpsie ) = cpu_to_be32( WPSOUI ); ++ wpsielen += 4; ++ ++ // WPS version ++ // Type: ++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_ATTR_VER1 ); ++ wpsielen += 2; ++ ++ // Length: ++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( 0x0001 ); ++ wpsielen += 2; ++ ++ // Value: ++ wpsie[wpsielen++] = WPS_VERSION_1; // Version 1.0 ++ ++ // Config Method ++ // Type: ++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( WPS_ATTR_CONF_METHOD ); ++ wpsielen += 2; ++ ++ // Length: ++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( 0x0002 ); ++ wpsielen += 2; ++ ++ // Value: ++ *(u16*) ( wpsie + wpsielen ) = cpu_to_be16( pwdinfo->tx_prov_disc_info.wps_config_method_request ); ++ wpsielen += 2; ++ ++ pframe = rtw_set_ie(pframe, _VENDOR_SPECIFIC_IE_, wpsielen, (unsigned char *) wpsie, &pattrib->pktlen ); ++ ++ ++#ifdef CONFIG_WFD ++ wfdielen = build_provdisc_req_wfd_ie(pwdinfo, pframe); ++ pframe += wfdielen; ++ pattrib->pktlen += wfdielen; ++#endif //CONFIG_WFD ++ ++ pattrib->last_txcmdsz = pattrib->pktlen; ++ ++ dump_mgntframe(padapter, pmgntframe); ++ ++ //if(wps_devicepassword_id == WPS_DPID_REGISTRAR_SPEC) ++ //{ ++ // printk("waiting for p2p peer key-in PIN CODE\n"); ++ // rtw_msleep_os(15000); // 15 sec for key in PIN CODE, workaround for GS2 before issuing Nego Req. ++ //} ++ ++} ++ ++static int cfg80211_rtw_mgmt_tx(struct wiphy *wiphy, struct net_device *dev, ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,38)) ++ struct ieee80211_channel *chan, bool offchan, ++ enum nl80211_channel_type channel_type, ++ bool channel_type_valid, unsigned int wait, ++#else //(LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,38)) ++ struct ieee80211_channel *chan, ++ enum nl80211_channel_type channel_type, ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) ++ bool channel_type_valid, ++#endif ++#endif //(LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,38)) ++ const u8 *buf, size_t len, u64 *cookie) ++{ ++ struct xmit_frame *pmgntframe; ++ struct pkt_attrib *pattrib; ++ unsigned char *pframe; ++ const struct ieee80211_mgmt *mgmt; ++ //u8 category, action, OUI_Subtype, dialogToken=0; ++ //unsigned char *frame_body; ++ int ret = 0; ++ int type = (-1); ++ u16 fc; ++ bool ack = _TRUE; ++ struct rtw_ieee80211_hdr *pwlanhdr; ++ _adapter *padapter = wiphy_to_adapter(wiphy); ++ struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); ++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); ++ ++ ++ /* cookie generation */ ++ *cookie = (unsigned long) buf; ++ ++ ++ printk("%s, len=%d, ch=%d, ch_type=%d\n", __func__, len, ++ ieee80211_frequency_to_channel(chan->center_freq), channel_type); ++ ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) ++ printk("channel_type_valid=%d\n", channel_type_valid); ++#endif ++ ++ mgmt = (const struct ieee80211_mgmt *) buf; ++ fc = mgmt->frame_control; ++ if (fc != IEEE80211_STYPE_ACTION) ++ { ++ if (fc == IEEE80211_STYPE_PROBE_RESP) ++ { ++ printk("%s, fc == IEEE80211_STYPE_PROBE_RESP\n", __func__); ++ } ++ else ++ { ++ printk("%s, frame_control == 0x%x\n", __func__, fc); ++ } ++ ++ //cfg80211_mgmt_tx_status(dev, *cookie, buf, len, ack, GFP_KERNEL); ++ ++ goto exit; ++ ++ } ++ else ++ { ++ u32 cnt=0; ++ u32 wait_for_surveydone; ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ ++#ifdef CONFIG_DEBUG_CFG80211 ++ printk("%s, do: scan_abort\n", __func__); ++#endif ++ ++ /* Abort the dwell time of any previous off-channel action frame that may ++ * be still in effect. Sending off-channel action frames relies on the ++ * driver's scan engine. If a previous off-channel action frame tx is ++ * still in progress (including the dwell time), then this new action ++ * frame will not be sent out. ++ */ ++ ++ rtw_cfg80211_scan_abort(padapter); ++ } ++#if 0 ++ if (wl->p2p->vif_created) { ++ wifi_p2p_pub_act_frame_t *act_frm = ++ (wifi_p2p_pub_act_frame_t *) (action_frame->data); ++ WL_DBG(("action_frame->len: %d chan %d category %d subtype %d\n", ++ action_frame->len, af_params->channel, ++ act_frm->category, act_frm->subtype)); ++ /* ++ * To make sure to send successfully action frame, we have to turn off mpc ++ */ ++ if ((act_frm->subtype == P2P_PAF_GON_REQ)|| ++ (act_frm->subtype == P2P_PAF_GON_RSP)) { ++ wldev_iovar_setint(dev, "mpc", 0); ++ } else if (act_frm->subtype == P2P_PAF_GON_CONF) { ++ wldev_iovar_setint(dev, "mpc", 1); ++ } else if (act_frm->subtype == P2P_PAF_DEVDIS_REQ) { ++ af_params->dwell_time = WL_LONG_DWELL_TIME; ++ } ++ } ++#endif ++ ++/* ++ frame_body = (unsigned char *)(buf + sizeof(struct rtw_ieee80211_hdr_3addr)); ++ category = frame_body[0]; ++ //just for check ++ if(category == RTW_WLAN_CATEGORY_PUBLIC) ++ { ++ action = frame_body[ 1 ]; ++ OUI_Subtype = frame_body[ 6 ]; ++ dialogToken = frame_body[7]; ++ ++ if ( action == ACT_PUBLIC_P2P ) ++ { ++ printk("ACTION_CATEGORY_PUBLIC: ACT_PUBLIC_P2P, OUI=0x%x, OUI_Subtype=%d, dialogToken=%d\n", ++ cpu_to_be32( *( ( u32* ) ( frame_body + 2 ) ) ), OUI_Subtype, dialogToken); ++ } ++ else ++ { ++ printk("ACTION_CATEGORY_PUBLIC: action=%d, OUI=0x%x, OUI_Subtype=%d, dialogToken=%d\n", ++ action, cpu_to_be32( *( ( u32* ) ( frame_body + 2 ) ) ), OUI_Subtype, dialogToken); ++ } ++ ++ } ++ else if(category == RTW_WLAN_CATEGORY_P2P) ++ { ++ OUI_Subtype = frame_body[5]; ++ dialogToken = frame_body[6]; ++ ++ printk("ACTION_CATEGORY_P2P: OUI=0x%x, OUI_Subtype=%d, dialogToken=%d\n", ++ cpu_to_be32( *( ( u32* ) ( frame_body + 1 ) ) ), OUI_Subtype, dialogToken); ++ ++ } ++ else ++ { ++ printk("%s, action frame category=%d\n", __func__, category); ++ ack = _FALSE; ++ goto exit; ++ } ++*/ ++ ++ if( ieee80211_frequency_to_channel(chan->center_freq) != pmlmeext->cur_channel ) ++ { ++ pmlmeext->cur_channel = ieee80211_frequency_to_channel(chan->center_freq); ++ set_channel_bwmode(padapter, pmlmeext->cur_channel, HAL_PRIME_CHNL_OFFSET_DONT_CARE, HT_CHANNEL_WIDTH_20); ++ } ++ ++ ++ if( (type = rtw_p2p_check_frames(padapter, buf, len, _TRUE)) < 0) ++ { ++ ack = _FALSE; ++ goto exit; ++ } ++ ++ ++ //if(type == P2P_GO_NEGO_REQ) ++ //{ ++ // rtw_cfg80211_issue_p2p_provision_request(padapter, buf, len); ++ //} ++ ++ ++ //starting alloc mgmt frame to dump it ++ if ((pmgntframe = alloc_mgtxmitframe(pxmitpriv)) == NULL) ++ { ++ ack = _FALSE; ++ ret = -ENOMEM; ++ goto exit; ++ } ++ ++ //update attribute ++ pattrib = &pmgntframe->attrib; ++ update_mgntframe_attrib(padapter, pattrib); ++ pattrib->retry_ctrl = _FALSE; ++ ++ _rtw_memset(pmgntframe->buf_addr, 0, WLANHDR_OFFSET + TXDESC_OFFSET); ++ ++ pframe = (u8 *)(pmgntframe->buf_addr) + TXDESC_OFFSET; ++ ++ _rtw_memcpy(pframe, (void*)buf, len); ++ pattrib->pktlen = len; ++ ++ pwlanhdr = (struct rtw_ieee80211_hdr *)pframe; ++ //update seq number ++ pmlmeext->mgnt_seq = GetSequence(pwlanhdr); ++ pattrib->seqnum = pmlmeext->mgnt_seq; ++ pmlmeext->mgnt_seq++; ++ ++ ++ pattrib->last_txcmdsz = pattrib->pktlen; ++ ++#ifdef CONFIG_DEBUG_CFG80211 ++ printk("%s, ack=%d, ok!\n", __func__, ack ); ++#endif ++ ++ //indicate ack before issue frame to avoid racing with rsp frame ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) ++ cfg80211_mgmt_tx_status(dev, *cookie, buf, len, ack, GFP_KERNEL); ++#elif (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,34) && LINUX_VERSION_CODE<=KERNEL_VERSION(2,6,35)) ++ cfg80211_action_tx_status(dev, *cookie, buf, len, ack, GFP_KERNEL); ++#endif ++ ++ dump_mgntframe(padapter, pmgntframe); ++ ++ return ret; ++ ++exit: ++ ++ printk("%s, ack=%d \n", __func__, ack ); ++ ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) ++ cfg80211_mgmt_tx_status(dev, *cookie, buf, len, ack, GFP_KERNEL); ++#elif (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,34) && LINUX_VERSION_CODE<=KERNEL_VERSION(2,6,35)) ++ cfg80211_action_tx_status(dev, *cookie, buf, len, ack, GFP_KERNEL); ++#endif ++ ++ return ret; ++ ++} ++ ++static s32 cfg80211_rtw_remain_on_channel(struct wiphy *wiphy, struct net_device *dev, ++ struct ieee80211_channel * channel, ++ enum nl80211_channel_type channel_type, ++ unsigned int duration, u64 *cookie) ++{ ++ s32 err = 0; ++ _adapter *padapter = wiphy_to_adapter(wiphy); ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct wifidirect_info *pwdinfo = &padapter->wdinfo; ++ struct cfg80211_wifidirect_info *pcfg80211_wdinfo = &padapter->cfg80211_wdinfo; ++ u8 remain_ch = (u8) ieee80211_frequency_to_channel(channel->center_freq); ++ ++ printk("%s channel %02u duration %d\n", __func__, remain_ch, duration); ++ ++ if(_FAIL == rtw_pwr_wakeup(padapter)) { ++ err = -EFAULT; ++ goto exit; ++ } ++ ++ pcfg80211_wdinfo->remain_on_ch_dev = dev; ++ _rtw_memcpy(&pcfg80211_wdinfo->remain_on_ch_channel, channel, sizeof(struct ieee80211_channel)); ++ pcfg80211_wdinfo->remain_on_ch_type= channel_type; ++ pcfg80211_wdinfo->remain_on_ch_cookie= *cookie; ++ cfg80211_ready_on_channel(dev, *cookie, channel, channel_type, duration, GFP_KERNEL); ++ ++ pcfg80211_wdinfo->restore_channel = pmlmeext->cur_channel; ++ ++ if(check_fwstate(&padapter->mlmepriv, _FW_UNDER_SURVEY)) ++ rtw_cfg80211_scan_abort(padapter); ++ ++ if( remain_ch != pmlmeext->cur_channel ) ++ { ++ if(rtw_is_channel_set_contains_channel(pmlmeext->channel_set, remain_ch)) { ++ pmlmeext->cur_channel = remain_ch; ++ set_channel_bwmode(padapter, pmlmeext->cur_channel, HAL_PRIME_CHNL_OFFSET_DONT_CARE, HT_CHANNEL_WIDTH_20); ++ } else { ++ DBG_871X("%s remain_ch:%u not in channel plan!!!!\n", __FUNCTION__, remain_ch); ++ } ++ } ++ ++ //if(!rtw_p2p_chk_role(pwdinfo, P2P_ROLE_CLIENT) && !rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) ++ if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) ++ { ++ rtw_p2p_enable(padapter, P2P_ROLE_DEVICE); ++ wdev_to_priv(padapter->rtw_wdev)->p2p_enabled = _TRUE; ++ } ++ else ++ { ++ rtw_p2p_set_pre_state(pwdinfo, rtw_p2p_state(pwdinfo)); ++#ifdef CONFIG_DEBUG_CFG80211 ++ printk("%s, role=%d, p2p_state=%d\n", __func__, rtw_p2p_role(pwdinfo), rtw_p2p_state(pwdinfo)); ++#endif ++ } ++ ++ rtw_p2p_set_state(pwdinfo, P2P_STATE_LISTEN); ++ pwdinfo->listen_channel = pmlmeext->cur_channel; ++ ++ //call this after other things have been done ++ _set_timer( &pcfg80211_wdinfo->remain_on_ch_timer, duration); ++ ++exit: ++ return err; ++} ++ ++static s32 cfg80211_rtw_cancel_remain_on_channel(struct wiphy *wiphy, struct net_device *dev, ++ u64 cookie) ++{ ++ s32 err = 0; ++ _adapter *padapter = wiphy_to_adapter(wiphy); ++ struct wifidirect_info *pwdinfo = &padapter->wdinfo; ++ struct pwrctrl_priv *pwrpriv = &padapter->pwrctrlpriv; ++ ++ printk("%s\n", __func__); ++ ++ //Modified bu Kurt 20120114 ++ _cancel_timer_ex(&padapter->cfg80211_wdinfo.remain_on_ch_timer); ++ ++ #if 0 ++ // Disable P2P Listen State ++ if(!rtw_p2p_chk_role(pwdinfo, P2P_ROLE_CLIENT) && !rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) ++ { ++ if(!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) ++ { ++ _cancel_timer_ex( &pwdinfo->find_phase_timer ); ++ _cancel_timer_ex( &pwdinfo->restore_p2p_state_timer ); ++ _cancel_timer_ex( &pwdinfo->pre_tx_scan_timer); ++ ++ rtw_p2p_set_state(pwdinfo, P2P_STATE_NONE); ++ _rtw_memset(pwdinfo, 0x00, sizeof(struct wifidirect_info)); ++ ++ if(pwrpriv->bips_processing == _FALSE){ ++ rtw_set_pwr_state_check_timer(pwrpriv); ++ } ++ } ++ } ++ else ++ #endif ++ { ++ rtw_p2p_set_state(pwdinfo, rtw_p2p_pre_state(pwdinfo)); ++#ifdef CONFIG_DEBUG_CFG80211 ++ printk("%s, role=%d, p2p_state=%d\n", __func__, rtw_p2p_role(pwdinfo), rtw_p2p_state(pwdinfo)); ++#endif ++ } ++ ++ return err; ++} ++ ++static void cfg80211_rtw_mgmt_frame_register(struct wiphy *wiphy, struct net_device *dev, ++ u16 frame_type, bool reg) ++{ ++ ++#ifdef CONFIG_DEBUG_CFG80211 ++ printk("%s: frame_type: %x, reg: %d\n", __func__, frame_type, reg); ++#endif ++ ++ if (frame_type != (IEEE80211_FTYPE_MGMT | IEEE80211_STYPE_PROBE_REQ)) ++ return; ++ ++ return; ++} ++ ++static int rtw_cfg80211_set_beacon_wpsp2pie(struct net_device *net, char *buf, int len) ++{ ++ int ret = 0; ++ uint wps_ielen = 0; ++ u8 *wps_ie; ++ u32 p2p_ielen = 0; ++ u8 wps_oui[8]={0x0,0x50,0xf2,0x04}; ++ u8 *p2p_ie; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(net); ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); ++ ++ printk("%s, ielen=%d\n", __func__, len); ++ ++ if(len>0) ++ { ++ if((wps_ie = rtw_get_wps_ie(buf, len, NULL, &wps_ielen))) ++ { ++ #ifdef CONFIG_DEBUG_CFG80211 ++ printk("bcn_wps_ielen=%d\n", wps_ielen); ++ #endif ++ ++ if(pmlmepriv->wps_beacon_ie) ++ { ++ u32 free_len = pmlmepriv->wps_beacon_ie_len; ++ pmlmepriv->wps_beacon_ie_len = 0; ++ rtw_mfree(pmlmepriv->wps_beacon_ie, free_len); ++ pmlmepriv->wps_beacon_ie = NULL; ++ } ++ ++ pmlmepriv->wps_beacon_ie = rtw_malloc(wps_ielen); ++ if ( pmlmepriv->wps_beacon_ie == NULL) { ++ printk("%s()-%d: rtw_malloc() ERROR!\n", __FUNCTION__, __LINE__); ++ return -EINVAL; ++ ++ } ++ ++ _rtw_memcpy(pmlmepriv->wps_beacon_ie, wps_ie, wps_ielen); ++ pmlmepriv->wps_beacon_ie_len = wps_ielen; ++ ++ update_beacon(padapter, _VENDOR_SPECIFIC_IE_, wps_oui, _TRUE); ++ ++ } ++ ++ buf += wps_ielen; ++ len -= wps_ielen; ++ ++ if((p2p_ie=rtw_get_p2p_ie(buf, len, NULL, &p2p_ielen))) ++ { ++ #ifdef CONFIG_DEBUG_CFG80211 ++ printk("bcn_p2p_ielen=%d\n", p2p_ielen); ++ #endif ++ ++ if(pmlmepriv->p2p_beacon_ie) ++ { ++ u32 free_len = pmlmepriv->p2p_beacon_ie_len; ++ pmlmepriv->p2p_beacon_ie_len = 0; ++ rtw_mfree(pmlmepriv->p2p_beacon_ie, free_len); ++ pmlmepriv->p2p_beacon_ie = NULL; ++ } ++ ++ pmlmepriv->p2p_beacon_ie = rtw_malloc(p2p_ielen); ++ if ( pmlmepriv->p2p_beacon_ie == NULL) { ++ printk("%s()-%d: rtw_malloc() ERROR!\n", __FUNCTION__, __LINE__); ++ return -EINVAL; ++ ++ } ++ ++ _rtw_memcpy(pmlmepriv->p2p_beacon_ie, p2p_ie, p2p_ielen); ++ pmlmepriv->p2p_beacon_ie_len = p2p_ielen; ++ ++ } ++ ++ pmlmeext->bstart_bss = _TRUE; ++ ++ } ++ ++ return ret; ++ ++} ++ ++static int rtw_cfg80211_set_probe_resp_wpsp2pie(struct net_device *net, char *buf, int len) ++{ ++ int ret = 0; ++ uint wps_ielen = 0; ++ u8 *wps_ie; ++ u32 p2p_ielen = 0; ++ u8 *p2p_ie; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(net); ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ ++#ifdef CONFIG_DEBUG_CFG80211 ++ printk("%s, ielen=%d\n", __func__, len); ++#endif ++ ++ if(len>0) ++ { ++ if((wps_ie = rtw_get_wps_ie(buf, len, NULL, &wps_ielen))) ++ { ++ uint attr_contentlen = 0; ++ u16 uconfig_method, *puconfig_method = NULL; ++ ++ #ifdef CONFIG_DEBUG_CFG80211 ++ printk("probe_resp_wps_ielen=%d\n", wps_ielen); ++ #endif ++ ++ if(pmlmepriv->wps_probe_resp_ie) ++ { ++ u32 free_len = pmlmepriv->wps_probe_resp_ie_len; ++ pmlmepriv->wps_probe_resp_ie_len = 0; ++ rtw_mfree(pmlmepriv->wps_probe_resp_ie, free_len); ++ pmlmepriv->wps_probe_resp_ie = NULL; ++ } ++ ++ pmlmepriv->wps_probe_resp_ie = rtw_malloc(wps_ielen); ++ if ( pmlmepriv->wps_probe_resp_ie == NULL) { ++ printk("%s()-%d: rtw_malloc() ERROR!\n", __FUNCTION__, __LINE__); ++ return -EINVAL; ++ ++ } ++ ++ //add PUSH_BUTTON config_method by driver self in wpsie of probe_resp at GO Mode ++ if ( (puconfig_method = (u16*)rtw_get_wps_attr_content( wps_ie, wps_ielen, WPS_ATTR_CONF_METHOD , NULL, &attr_contentlen)) != NULL ) ++ { ++ #ifdef CONFIG_DEBUG_CFG80211 ++ //printk("config_method in wpsie of probe_resp = 0x%x\n", be16_to_cpu(*puconfig_method)); ++ #endif ++ ++ uconfig_method = WPS_CM_PUSH_BUTTON; ++ uconfig_method = cpu_to_be16( uconfig_method ); ++ ++ *puconfig_method |= uconfig_method; ++ } ++ ++ _rtw_memcpy(pmlmepriv->wps_probe_resp_ie, wps_ie, wps_ielen); ++ pmlmepriv->wps_probe_resp_ie_len = wps_ielen; ++ ++ } ++ ++ buf += wps_ielen; ++ len -= wps_ielen; ++ ++ if((p2p_ie=rtw_get_p2p_ie(buf, len, NULL, &p2p_ielen))) ++ { ++ u8 is_GO = _FALSE; ++ u32 attr_contentlen = 0; ++ u16 cap_attr=0; ++ ++ #ifdef CONFIG_DEBUG_CFG80211 ++ printk("probe_resp_p2p_ielen=%d\n", p2p_ielen); ++ #endif ++ ++ //Check P2P Capability ATTR ++ if( rtw_get_p2p_attr_content( p2p_ie, p2p_ielen, P2P_ATTR_CAPABILITY, (u8*)&cap_attr, (uint*) &attr_contentlen) ) ++ { ++ u8 grp_cap=0; ++ //DBG_8192C( "[%s] Got P2P Capability Attr!!\n", __FUNCTION__ ); ++ cap_attr = le16_to_cpu(cap_attr); ++ grp_cap = (u8)((cap_attr >> 8)&0xff); ++ ++ is_GO = (grp_cap&BIT(0)) ? _TRUE:_FALSE; ++ ++ if(is_GO) ++ printk("Got P2P Capability Attr, grp_cap=0x%x, is_GO\n", grp_cap); ++ } ++ ++ ++ if(is_GO == _FALSE) ++ { ++ if(pmlmepriv->p2p_probe_resp_ie) ++ { ++ u32 free_len = pmlmepriv->p2p_probe_resp_ie_len; ++ pmlmepriv->p2p_probe_resp_ie_len = 0; ++ rtw_mfree(pmlmepriv->p2p_probe_resp_ie, free_len); ++ pmlmepriv->p2p_probe_resp_ie = NULL; ++ } ++ ++ pmlmepriv->p2p_probe_resp_ie = rtw_malloc(p2p_ielen); ++ if ( pmlmepriv->p2p_probe_resp_ie == NULL) { ++ printk("%s()-%d: rtw_malloc() ERROR!\n", __FUNCTION__, __LINE__); ++ return -EINVAL; ++ ++ } ++ _rtw_memcpy(pmlmepriv->p2p_probe_resp_ie, p2p_ie, p2p_ielen); ++ pmlmepriv->p2p_probe_resp_ie_len = p2p_ielen; ++ } ++ else ++ { ++ if(pmlmepriv->p2p_go_probe_resp_ie) ++ { ++ u32 free_len = pmlmepriv->p2p_go_probe_resp_ie_len; ++ pmlmepriv->p2p_go_probe_resp_ie_len = 0; ++ rtw_mfree(pmlmepriv->p2p_go_probe_resp_ie, free_len); ++ pmlmepriv->p2p_go_probe_resp_ie = NULL; ++ } ++ ++ pmlmepriv->p2p_go_probe_resp_ie = rtw_malloc(p2p_ielen); ++ if ( pmlmepriv->p2p_go_probe_resp_ie == NULL) { ++ printk("%s()-%d: rtw_malloc() ERROR!\n", __FUNCTION__, __LINE__); ++ return -EINVAL; ++ ++ } ++ _rtw_memcpy(pmlmepriv->p2p_go_probe_resp_ie, p2p_ie, p2p_ielen); ++ pmlmepriv->p2p_go_probe_resp_ie_len = p2p_ielen; ++ } ++ ++ } ++ ++ } ++ ++ return ret; ++ ++} ++ ++static int rtw_cfg80211_set_assoc_resp_wpsp2pie(struct net_device *net, char *buf, int len) ++{ ++ int ret = 0; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(net); ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ ++ printk("%s, ielen=%d\n", __func__, len); ++ ++ if(len>0) ++ { ++ if(pmlmepriv->wps_assoc_resp_ie) ++ { ++ u32 free_len = pmlmepriv->wps_assoc_resp_ie_len; ++ pmlmepriv->wps_assoc_resp_ie_len = 0; ++ rtw_mfree(pmlmepriv->wps_assoc_resp_ie, free_len); ++ pmlmepriv->wps_assoc_resp_ie = NULL; ++ } ++ ++ pmlmepriv->wps_assoc_resp_ie = rtw_malloc(len); ++ if ( pmlmepriv->wps_assoc_resp_ie == NULL) { ++ printk("%s()-%d: rtw_malloc() ERROR!\n", __FUNCTION__, __LINE__); ++ return -EINVAL; ++ ++ } ++ _rtw_memcpy(pmlmepriv->wps_assoc_resp_ie, buf, len); ++ pmlmepriv->wps_assoc_resp_ie_len = len; ++ } ++ ++ return ret; ++ ++} ++ ++int rtw_cfg80211_set_mgnt_wpsp2pie(struct net_device *net, char *buf, int len, ++ int type) ++{ ++ int ret = 0; ++ uint wps_ielen = 0; ++ u32 p2p_ielen = 0; ++ ++#ifdef CONFIG_DEBUG_CFG80211 ++ printk("%s, ielen=%d\n", __func__, len); ++#endif ++ ++ if((rtw_get_wps_ie(buf, len, NULL, &wps_ielen) && (wps_ielen>0)) || ++ (rtw_get_p2p_ie(buf, len, NULL, &p2p_ielen) && (p2p_ielen>0)) ) ++ { ++ if (net != NULL) ++ { ++ switch (type) ++ { ++ case 0x1: //BEACON ++ ret = rtw_cfg80211_set_beacon_wpsp2pie(net, buf, len); ++ break; ++ case 0x2: //PROBE_RESP ++ ret = rtw_cfg80211_set_probe_resp_wpsp2pie(net, buf, len); ++ break; ++ case 0x4: //ASSOC_RESP ++ ret = rtw_cfg80211_set_assoc_resp_wpsp2pie(net, buf, len); ++ break; ++ } ++ } ++ } ++ ++ return ret; ++ ++} ++ ++static struct cfg80211_ops rtw_cfg80211_ops = { ++ .change_virtual_intf = cfg80211_rtw_change_iface, ++ .add_key = cfg80211_rtw_add_key, ++ .get_key = cfg80211_rtw_get_key, ++ .del_key = cfg80211_rtw_del_key, ++ .set_default_key = cfg80211_rtw_set_default_key, ++ .get_station = cfg80211_rtw_get_station, ++ .scan = cfg80211_rtw_scan, ++ .set_wiphy_params = cfg80211_rtw_set_wiphy_params, ++ .connect = cfg80211_rtw_connect, ++ .disconnect = cfg80211_rtw_disconnect, ++ .join_ibss = cfg80211_rtw_join_ibss, ++ .leave_ibss = cfg80211_rtw_leave_ibss, ++ .set_tx_power = cfg80211_rtw_set_txpower, ++ .get_tx_power = cfg80211_rtw_get_txpower, ++ .set_power_mgmt = cfg80211_rtw_set_power_mgmt, ++ .set_pmksa = cfg80211_rtw_set_pmksa, ++ .del_pmksa = cfg80211_rtw_del_pmksa, ++ .flush_pmksa = cfg80211_rtw_flush_pmksa, ++#ifdef CONFIG_AP_MODE ++ .add_virtual_intf = cfg80211_rtw_add_virtual_intf, ++ .del_virtual_intf = cfg80211_rtw_del_virtual_intf, ++ .add_beacon = cfg80211_rtw_add_beacon, ++ .set_beacon = cfg80211_rtw_set_beacon, ++ .del_beacon = cfg80211_rtw_del_beacon, ++ .add_station = cfg80211_rtw_add_station, ++ .del_station = cfg80211_rtw_del_station, ++ .change_station = cfg80211_rtw_change_station, ++ .dump_station = cfg80211_rtw_dump_station, ++ .change_bss = cfg80211_rtw_change_bss, ++ .set_channel = cfg80211_rtw_set_channel, ++ //.auth = cfg80211_rtw_auth, ++ //.assoc = cfg80211_rtw_assoc, ++#endif //CONFIG_AP_MODE ++ .remain_on_channel = cfg80211_rtw_remain_on_channel, ++ .cancel_remain_on_channel = cfg80211_rtw_cancel_remain_on_channel, ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) ++ .mgmt_tx = cfg80211_rtw_mgmt_tx, ++ .mgmt_frame_register = cfg80211_rtw_mgmt_frame_register, ++#elif (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,34) && LINUX_VERSION_CODE<=KERNEL_VERSION(2,6,35)) ++ .action = cfg80211_rtw_mgmt_tx, ++#endif ++}; ++ ++static void rtw_cfg80211_init_ht_capab(struct ieee80211_sta_ht_cap *ht_cap, enum ieee80211_band band, u8 rf_type) ++{ ++ ++#define MAX_BIT_RATE_40MHZ_MCS15 300 /* Mbps */ ++#define MAX_BIT_RATE_40MHZ_MCS7 150 /* Mbps */ ++ ++ ht_cap->ht_supported = _TRUE; ++ ++ ht_cap->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 | ++ IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_SGI_20 | ++ IEEE80211_HT_CAP_DSSSCCK40 | IEEE80211_HT_CAP_MAX_AMSDU; ++ ++ /* ++ *Maximum length of AMPDU that the STA can receive. ++ *Length = 2 ^ (13 + max_ampdu_length_exp) - 1 (octets) ++ */ ++ ht_cap->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K; ++ ++ /*Minimum MPDU start spacing , */ ++ ht_cap->ampdu_density = IEEE80211_HT_MPDU_DENSITY_16; ++ ++ ht_cap->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED; ++ ++ /* ++ *hw->wiphy->bands[IEEE80211_BAND_2GHZ] ++ *base on ant_num ++ *rx_mask: RX mask ++ *if rx_ant =1 rx_mask[0]=0xff;==>MCS0-MCS7 ++ *if rx_ant =2 rx_mask[1]=0xff;==>MCS8-MCS15 ++ *if rx_ant >=3 rx_mask[2]=0xff; ++ *if BW_40 rx_mask[4]=0x01; ++ *highest supported RX rate ++ */ ++ if(rf_type == RF_1T1R) ++ { ++ ht_cap->mcs.rx_mask[0] = 0xFF; ++ ht_cap->mcs.rx_mask[1] = 0x00; ++ ht_cap->mcs.rx_mask[4] = 0x01; ++ ++ ht_cap->mcs.rx_highest = MAX_BIT_RATE_40MHZ_MCS7; ++ } ++ else if((rf_type == RF_1T2R) || (rf_type==RF_2T2R)) ++ { ++ ht_cap->mcs.rx_mask[0] = 0xFF; ++ ht_cap->mcs.rx_mask[1] = 0xFF; ++ ht_cap->mcs.rx_mask[4] = 0x01; ++ ++ ht_cap->mcs.rx_highest = MAX_BIT_RATE_40MHZ_MCS15; ++ } ++ else ++ { ++ printk("%s, error rf_type=%d\n", __func__, rf_type); ++ } ++ ++} ++ ++void rtw_cfg80211_init_wiphy(_adapter *padapter) ++{ ++ u8 rf_type; ++ struct ieee80211_supported_band *bands; ++ struct wireless_dev *pwdev = padapter->rtw_wdev; ++ struct wiphy *wiphy = pwdev->wiphy; ++ ++ padapter->HalFunc.GetHwRegHandler(padapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type)); ++ ++ printk("%s:rf_type=%d\n", __func__, rf_type); ++ ++ bands = wiphy->bands[IEEE80211_BAND_2GHZ]; ++ rtw_cfg80211_init_ht_capab(&bands->ht_cap, IEEE80211_BAND_2GHZ, rf_type); ++ ++ ++ bands = wiphy->bands[IEEE80211_BAND_5GHZ]; ++ rtw_cfg80211_init_ht_capab(&bands->ht_cap, IEEE80211_BAND_5GHZ, rf_type); ++} ++ ++static void rtw_cfg80211_preinit_wiphy(_adapter *padapter, struct wiphy *wiphy) ++{ ++ ++ wiphy->signal_type = CFG80211_SIGNAL_TYPE_MBM; ++ ++ wiphy->max_scan_ssids = RTW_SSID_SCAN_AMOUNT; ++ wiphy->max_scan_ie_len = RTW_SCAN_IE_LEN_MAX; ++ wiphy->max_num_pmkids = RTW_MAX_NUM_PMKIDS; ++ ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,38)) ++ wiphy->max_remain_on_channel_duration = RTW_MAX_REMAIN_ON_CHANNEL_DURATION; ++#endif ++ ++ wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) | ++ BIT(NL80211_IFTYPE_ADHOC) ++#ifdef CONFIG_AP_MODE ++ | BIT(NL80211_IFTYPE_AP) | BIT(NL80211_IFTYPE_MONITOR) ++#endif ++#if defined(CONFIG_P2P) && (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) ++ | BIT(NL80211_IFTYPE_P2P_CLIENT) | BIT(NL80211_IFTYPE_P2P_GO) ++#endif ++ ; ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) ++#ifdef CONFIG_AP_MODE ++ wiphy->mgmt_stypes = rtw_cfg80211_default_mgmt_stypes; ++#endif //CONFIG_AP_MODE ++#endif ++ ++ wiphy->cipher_suites = rtw_cipher_suites; ++ wiphy->n_cipher_suites = ARRAY_SIZE(rtw_cipher_suites); ++ ++ ++ wiphy->bands[IEEE80211_BAND_2GHZ] = &rtw_band_2ghz; ++ wiphy->bands[IEEE80211_BAND_5GHZ] = &rtw_band_5ghz; ++ ++} ++ ++int rtw_wdev_alloc(_adapter *padapter, struct device *dev) ++{ ++ int ret = 0; ++ struct wireless_dev *wdev; ++ struct rtw_wdev_priv *pwdev_priv; ++ struct net_device *pnetdev = padapter->pnetdev; ++ ++ printk("%s\n", __func__); ++ ++ wdev = (struct wireless_dev *)rtw_zmalloc(sizeof(struct wireless_dev)); ++ if (!wdev) { ++ printk("Couldn't allocate wireless device\n"); ++ return (-ENOMEM); ++ } ++ ++ wdev->wiphy = wiphy_new(&rtw_cfg80211_ops, sizeof(struct rtw_wdev_priv)); ++ if (!wdev->wiphy) { ++ printk("Couldn't allocate wiphy device\n"); ++ ret = -ENOMEM; ++ goto out_err_new; ++ } ++ ++ set_wiphy_dev(wdev->wiphy, dev); ++ ++ // ++ padapter->rtw_wdev = wdev; ++ pnetdev->ieee80211_ptr = wdev; ++ ++ //init pwdev_priv ++ pwdev_priv = wdev_to_priv(wdev); ++ pwdev_priv->pmon_ndev = NULL; ++ pwdev_priv->ifname_mon[0] = '\0'; ++ pwdev_priv->rtw_wdev = wdev; ++ pwdev_priv->padapter = padapter; ++ pwdev_priv->scan_request = NULL; ++ _rtw_spinlock_init(&pwdev_priv->scan_req_lock); ++ ++ pwdev_priv->p2p_enabled = _FALSE; ++ pwdev_priv->provdisc_req_issued = _FALSE; ++ ++ wdev->netdev = pnetdev; ++ wdev->iftype = NL80211_IFTYPE_MONITOR; ++ ++ rtw_cfg80211_preinit_wiphy(padapter, wdev->wiphy); ++ ++ ret = wiphy_register(wdev->wiphy); ++ if (ret < 0) { ++ printk("Couldn't register wiphy device\n"); ++ goto out_err_register; ++ } ++ ++ SET_NETDEV_DEV(pnetdev, wiphy_dev(wdev->wiphy)); ++ ++ return ret; ++ ++ out_err_register: ++ wiphy_free(wdev->wiphy); ++ ++ out_err_new: ++ rtw_mfree((u8*)wdev, sizeof(struct wireless_dev)); ++ ++ return ret; ++ ++} ++ ++void rtw_wdev_free(struct wireless_dev *wdev) ++{ ++ struct rtw_wdev_priv *pwdev_priv; ++ ++ printk("%s\n", __func__); ++ ++ if (!wdev) ++ return; ++ ++ pwdev_priv = wdev_to_priv(wdev); ++ ++ printk("%s, scan abort when device remove\n", __func__); ++ rtw_cfg80211_indicate_scan_done(pwdev_priv, _TRUE); ++ ++ if(pwdev_priv->pmon_ndev) ++ { ++ printk("%s, unregister monitor interface\n", __func__); ++ ++ unregister_netdev(pwdev_priv->pmon_ndev); ++ ++ free_netdev(pwdev_priv->pmon_ndev); ++ } ++ ++ ++ wiphy_unregister(wdev->wiphy); ++ wiphy_free(wdev->wiphy); ++ ++ rtw_mfree((u8*)wdev, sizeof(struct wireless_dev)); ++} ++ ++#endif //CONFIG_IOCTL_CFG80211 ++ +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/os_dep/linux/ioctl_linux.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/os_dep/linux/ioctl_linux.c 2013-07-26 19:36:07.000000000 +0000 +@@ -0,0 +1,9305 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#define _IOCTL_LINUX_C_ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++//#ifdef CONFIG_MP_INCLUDED ++#include ++//#endif ++ ++#ifdef CONFIG_USB_HCI ++#include ++#endif //CONFIG_USB_HCI ++#include ++ ++#ifdef CONFIG_MP_INCLUDED ++#include ++#endif ++ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,27)) ++#define iwe_stream_add_event(a, b, c, d, e) iwe_stream_add_event(b, c, d, e) ++#define iwe_stream_add_point(a, b, c, d, e) iwe_stream_add_point(b, c, d, e) ++#endif ++ ++ ++#define RTL_IOCTL_WPA_SUPPLICANT SIOCIWFIRSTPRIV+30 ++ ++#define SCAN_ITEM_SIZE 768 ++#define MAX_CUSTOM_LEN 64 ++#define RATE_COUNT 4 ++ ++#ifdef CONFIG_GLOBAL_UI_PID ++extern int ui_pid[3]; ++#endif ++ ++// combo scan ++#define WEXT_CSCAN_AMOUNT 9 ++#define WEXT_CSCAN_BUF_LEN 360 ++#define WEXT_CSCAN_HEADER "CSCAN S\x01\x00\x00S\x00" ++#define WEXT_CSCAN_HEADER_SIZE 12 ++#define WEXT_CSCAN_SSID_SECTION 'S' ++#define WEXT_CSCAN_CHANNEL_SECTION 'C' ++#define WEXT_CSCAN_NPROBE_SECTION 'N' ++#define WEXT_CSCAN_ACTV_DWELL_SECTION 'A' ++#define WEXT_CSCAN_PASV_DWELL_SECTION 'P' ++#define WEXT_CSCAN_HOME_DWELL_SECTION 'H' ++#define WEXT_CSCAN_TYPE_SECTION 'T' ++ ++ ++extern u8 key_2char2num(u8 hch, u8 lch); ++extern u8 str_2char2num(u8 hch, u8 lch); ++ ++int rfpwrstate_check(_adapter *padapter); ++ ++u32 rtw_rates[] = {1000000,2000000,5500000,11000000, ++ 6000000,9000000,12000000,18000000,24000000,36000000,48000000,54000000}; ++ ++static const char * const iw_operation_mode[] = ++{ ++ "Auto", "Ad-Hoc", "Managed", "Master", "Repeater", "Secondary", "Monitor" ++}; ++ ++static int hex2num_i(char c) ++{ ++ if (c >= '0' && c <= '9') ++ return c - '0'; ++ if (c >= 'a' && c <= 'f') ++ return c - 'a' + 10; ++ if (c >= 'A' && c <= 'F') ++ return c - 'A' + 10; ++ return -1; ++} ++ ++static int hex2byte_i(const char *hex) ++{ ++ int a, b; ++ a = hex2num_i(*hex++); ++ if (a < 0) ++ return -1; ++ b = hex2num_i(*hex++); ++ if (b < 0) ++ return -1; ++ return (a << 4) | b; ++} ++ ++/** ++ * hwaddr_aton - Convert ASCII string to MAC address ++ * @txt: MAC address as a string (e.g., "00:11:22:33:44:55") ++ * @addr: Buffer for the MAC address (ETH_ALEN = 6 bytes) ++ * Returns: 0 on success, -1 on failure (e.g., string not a MAC address) ++ */ ++static int hwaddr_aton_i(const char *txt, u8 *addr) ++{ ++ int i; ++ ++ for (i = 0; i < 6; i++) { ++ int a, b; ++ ++ a = hex2num_i(*txt++); ++ if (a < 0) ++ return -1; ++ b = hex2num_i(*txt++); ++ if (b < 0) ++ return -1; ++ *addr++ = (a << 4) | b; ++ if (i < 5 && *txt++ != ':') ++ return -1; ++ } ++ ++ return 0; ++} ++ ++static void indicate_wx_custom_event(_adapter *padapter, char *msg) ++{ ++ u8 *buff, *p; ++ union iwreq_data wrqu; ++ ++ if (strlen(msg) > IW_CUSTOM_MAX) { ++ DBG_871X("%s strlen(msg):%u > IW_CUSTOM_MAX:%u\n", __FUNCTION__ ,strlen(msg), IW_CUSTOM_MAX); ++ return; ++ } ++ ++ buff = rtw_zmalloc(IW_CUSTOM_MAX+1); ++ if(!buff) ++ return; ++ ++ _rtw_memcpy(buff, msg, strlen(msg)); ++ ++ _rtw_memset(&wrqu,0,sizeof(wrqu)); ++ wrqu.data.length = strlen(msg); ++ ++ DBG_8192C("%s %s\n", __FUNCTION__, buff); ++ wireless_send_event(padapter->pnetdev, IWEVCUSTOM, &wrqu, buff); ++ ++ rtw_mfree(buff, IW_CUSTOM_MAX+1); ++ ++} ++ ++ ++static void request_wps_pbc_event(_adapter *padapter) ++{ ++ u8 *buff, *p; ++ union iwreq_data wrqu; ++ ++ ++ buff = rtw_malloc(IW_CUSTOM_MAX); ++ if(!buff) ++ return; ++ ++ _rtw_memset(buff, 0, IW_CUSTOM_MAX); ++ ++ p=buff; ++ ++ p+=sprintf(p, "WPS_PBC_START.request=TRUE"); ++ ++ _rtw_memset(&wrqu,0,sizeof(wrqu)); ++ ++ wrqu.data.length = p-buff; ++ ++ wrqu.data.length = (wrqu.data.lengthpnetdev, IWEVCUSTOM, &wrqu, buff); ++ ++ if(buff) ++ { ++ rtw_mfree(buff, IW_CUSTOM_MAX); ++ } ++ ++} ++ ++ ++void indicate_wx_scan_complete_event(_adapter *padapter) ++{ ++ union iwreq_data wrqu; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ ++ _rtw_memset(&wrqu, 0, sizeof(union iwreq_data)); ++ ++ //DBG_8192C("+rtw_indicate_wx_scan_complete_event\n"); ++ wireless_send_event(padapter->pnetdev, SIOCGIWSCAN, &wrqu, NULL); ++} ++ ++ ++void rtw_indicate_wx_assoc_event(_adapter *padapter) ++{ ++ union iwreq_data wrqu; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ ++ _rtw_memset(&wrqu, 0, sizeof(union iwreq_data)); ++ ++ wrqu.ap_addr.sa_family = ARPHRD_ETHER; ++ ++ _rtw_memcpy(wrqu.ap_addr.sa_data, pmlmepriv->cur_network.network.MacAddress, ETH_ALEN); ++ ++ //DBG_8192C("+rtw_indicate_wx_assoc_event\n"); ++ wireless_send_event(padapter->pnetdev, SIOCGIWAP, &wrqu, NULL); ++} ++ ++void rtw_indicate_wx_disassoc_event(_adapter *padapter) ++{ ++ union iwreq_data wrqu; ++ ++ _rtw_memset(&wrqu, 0, sizeof(union iwreq_data)); ++ ++ wrqu.ap_addr.sa_family = ARPHRD_ETHER; ++ _rtw_memset(wrqu.ap_addr.sa_data, 0, ETH_ALEN); ++ ++ //DBG_8192C("+rtw_indicate_wx_disassoc_event\n"); ++ wireless_send_event(padapter->pnetdev, SIOCGIWAP, &wrqu, NULL); ++} ++ ++/* ++uint rtw_is_cckrates_included(u8 *rate) ++{ ++ u32 i = 0; ++ ++ while(rate[i]!=0) ++ { ++ if ( (((rate[i]) & 0x7f) == 2) || (((rate[i]) & 0x7f) == 4) || ++ (((rate[i]) & 0x7f) == 11) || (((rate[i]) & 0x7f) == 22) ) ++ return _TRUE; ++ i++; ++ } ++ ++ return _FALSE; ++} ++ ++uint rtw_is_cckratesonly_included(u8 *rate) ++{ ++ u32 i = 0; ++ ++ while(rate[i]!=0) ++ { ++ if ( (((rate[i]) & 0x7f) != 2) && (((rate[i]) & 0x7f) != 4) && ++ (((rate[i]) & 0x7f) != 11) && (((rate[i]) & 0x7f) != 22) ) ++ return _FALSE; ++ i++; ++ } ++ ++ return _TRUE; ++} ++*/ ++ ++static char *translate_scan(_adapter *padapter, ++ struct iw_request_info* info, struct wlan_network *pnetwork, ++ char *start, char *stop) ++{ ++ struct iw_event iwe; ++ u16 cap; ++ u32 ht_ielen = 0; ++ char custom[MAX_CUSTOM_LEN]; ++ char *p; ++ u16 max_rate=0, rate, ht_cap=_FALSE; ++ u32 i = 0; ++ char *current_val; ++ long rssi; ++ u8 bw_40MHz=0, short_GI=0; ++ u16 mcs_rate=0; ++ struct registry_priv *pregpriv = &padapter->registrypriv; ++#ifdef CONFIG_P2P ++ struct wifidirect_info *pwdinfo = &padapter->wdinfo; ++#endif //CONFIG_P2P ++ ++#ifdef CONFIG_P2P ++ if(!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE) && !rtw_p2p_chk_state(pwdinfo, P2P_STATE_IDLE)) ++ { ++ u32 blnGotP2PIE = _FALSE; ++ ++ // User is doing the P2P device discovery ++ // The prefix of SSID should be "DIRECT-" and the IE should contains the P2P IE. ++ // If not, the driver should ignore this AP and go to the next AP. ++ ++ // Verifying the SSID ++ if ( _rtw_memcmp( pnetwork->network.Ssid.Ssid, pwdinfo->p2p_wildcard_ssid, P2P_WILDCARD_SSID_LEN ) ) ++ { ++ u32 p2pielen = 0; ++ ++ // Verifying the P2P IE ++ if ( rtw_get_p2p_ie( &pnetwork->network.IEs[12], pnetwork->network.IELength - 12, NULL, &p2pielen) ) ++ { ++ blnGotP2PIE = _TRUE; ++ } ++ ++ } ++ ++ if ( blnGotP2PIE == _FALSE ) ++ { ++ return start; ++ } ++ ++ } ++ ++#endif //CONFIG_P2P ++ ++ /* AP MAC address */ ++ iwe.cmd = SIOCGIWAP; ++ iwe.u.ap_addr.sa_family = ARPHRD_ETHER; ++ ++ _rtw_memcpy(iwe.u.ap_addr.sa_data, pnetwork->network.MacAddress, ETH_ALEN); ++ start = iwe_stream_add_event(info, start, stop, &iwe, IW_EV_ADDR_LEN); ++ ++ /* Add the ESSID */ ++ iwe.cmd = SIOCGIWESSID; ++ iwe.u.data.flags = 1; ++ iwe.u.data.length = min((u16)pnetwork->network.Ssid.SsidLength, (u16)32); ++ start = iwe_stream_add_point(info, start, stop, &iwe, pnetwork->network.Ssid.Ssid); ++ ++ //parsing HT_CAP_IE ++ p = rtw_get_ie(&pnetwork->network.IEs[12], _HT_CAPABILITY_IE_, &ht_ielen, pnetwork->network.IELength-12); ++ ++ if(p && ht_ielen>0) ++ { ++ struct rtw_ieee80211_ht_cap *pht_capie; ++ ht_cap = _TRUE; ++ pht_capie = (struct rtw_ieee80211_ht_cap *)(p+2); ++ _rtw_memcpy(&mcs_rate , pht_capie->supp_mcs_set, 2); ++ bw_40MHz = (pht_capie->cap_info&IEEE80211_HT_CAP_SUP_WIDTH) ? 1:0; ++ short_GI = (pht_capie->cap_info&(IEEE80211_HT_CAP_SGI_20|IEEE80211_HT_CAP_SGI_40)) ? 1:0; ++ } ++ ++ /* Add the protocol name */ ++ iwe.cmd = SIOCGIWNAME; ++ if ((rtw_is_cckratesonly_included((u8*)&pnetwork->network.SupportedRates)) == _TRUE) ++ { ++ if(ht_cap == _TRUE) ++ snprintf(iwe.u.name, IFNAMSIZ, "IEEE 802.11bn"); ++ else ++ snprintf(iwe.u.name, IFNAMSIZ, "IEEE 802.11b"); ++ } ++ else if ((rtw_is_cckrates_included((u8*)&pnetwork->network.SupportedRates)) == _TRUE) ++ { ++ if(ht_cap == _TRUE) ++ snprintf(iwe.u.name, IFNAMSIZ, "IEEE 802.11bgn"); ++ else ++ snprintf(iwe.u.name, IFNAMSIZ, "IEEE 802.11bg"); ++ } ++ else ++ { ++ if(pnetwork->network.Configuration.DSConfig > 14) ++ { ++ if(ht_cap == _TRUE) ++ snprintf(iwe.u.name, IFNAMSIZ, "IEEE 802.11an"); ++ else ++ snprintf(iwe.u.name, IFNAMSIZ, "IEEE 802.11a"); ++ } ++ else ++ { ++ if(ht_cap == _TRUE) ++ snprintf(iwe.u.name, IFNAMSIZ, "IEEE 802.11gn"); ++ else ++ snprintf(iwe.u.name, IFNAMSIZ, "IEEE 802.11g"); ++ } ++ } ++ ++ start = iwe_stream_add_event(info, start, stop, &iwe, IW_EV_CHAR_LEN); ++ ++ /* Add mode */ ++ iwe.cmd = SIOCGIWMODE; ++ _rtw_memcpy((u8 *)&cap, rtw_get_capability_from_ie(pnetwork->network.IEs), 2); ++ ++ ++ cap = le16_to_cpu(cap); ++ ++ if(cap & (WLAN_CAPABILITY_IBSS |WLAN_CAPABILITY_BSS)){ ++ if (cap & WLAN_CAPABILITY_BSS) ++ iwe.u.mode = IW_MODE_MASTER; ++ else ++ iwe.u.mode = IW_MODE_ADHOC; ++ ++ start = iwe_stream_add_event(info, start, stop, &iwe, IW_EV_UINT_LEN); ++ } ++ ++ if(pnetwork->network.Configuration.DSConfig<1 /*|| pnetwork->network.Configuration.DSConfig>14*/) ++ pnetwork->network.Configuration.DSConfig = 1; ++ ++ /* Add frequency/channel */ ++ iwe.cmd = SIOCGIWFREQ; ++ iwe.u.freq.m = rtw_ch2freq(pnetwork->network.Configuration.DSConfig) * 100000; ++ iwe.u.freq.e = 1; ++ iwe.u.freq.i = pnetwork->network.Configuration.DSConfig; ++ start = iwe_stream_add_event(info, start, stop, &iwe, IW_EV_FREQ_LEN); ++ ++ /* Add encryption capability */ ++ iwe.cmd = SIOCGIWENCODE; ++ if (cap & WLAN_CAPABILITY_PRIVACY) ++ iwe.u.data.flags = IW_ENCODE_ENABLED | IW_ENCODE_NOKEY; ++ else ++ iwe.u.data.flags = IW_ENCODE_DISABLED; ++ iwe.u.data.length = 0; ++ start = iwe_stream_add_point(info, start, stop, &iwe, pnetwork->network.Ssid.Ssid); ++ ++ /*Add basic and extended rates */ ++ max_rate = 0; ++ p = custom; ++ p += snprintf(p, MAX_CUSTOM_LEN - (p - custom), " Rates (Mb/s): "); ++ while(pnetwork->network.SupportedRates[i]!=0) ++ { ++ rate = pnetwork->network.SupportedRates[i]&0x7F; ++ if (rate > max_rate) ++ max_rate = rate; ++ p += snprintf(p, MAX_CUSTOM_LEN - (p - custom), ++ "%d%s ", rate >> 1, (rate & 1) ? ".5" : ""); ++ i++; ++ } ++ ++ if(ht_cap == _TRUE) ++ { ++ if(mcs_rate&0x8000)//MCS15 ++ { ++ max_rate = (bw_40MHz) ? ((short_GI)?300:270):((short_GI)?144:130); ++ ++ } ++ else if(mcs_rate&0x0080)//MCS7 ++ { ++ max_rate = (bw_40MHz) ? ((short_GI)?150:135):((short_GI)?72:65); ++ } ++ else//default MCS7 ++ { ++ DBG_8192C("wx_get_scan, mcs_rate_bitmap=0x%x\n", mcs_rate); ++ max_rate = (bw_40MHz) ? ((short_GI)?150:135):((short_GI)?72:65); ++ } ++ ++ max_rate = max_rate*2;//Mbps/2; ++ } ++ ++ iwe.cmd = SIOCGIWRATE; ++ iwe.u.bitrate.fixed = iwe.u.bitrate.disabled = 0; ++ iwe.u.bitrate.value = max_rate * 500000; ++ start = iwe_stream_add_event(info, start, stop, &iwe, IW_EV_PARAM_LEN); ++ ++ //parsing WPA/WPA2 IE ++ { ++ u8 buf[MAX_WPA_IE_LEN]; ++ u8 wpa_ie[255],rsn_ie[255]; ++ u16 wpa_len=0,rsn_len=0; ++ u8 *p; ++ sint out_len=0; ++ out_len=rtw_get_sec_ie(pnetwork->network.IEs ,pnetwork->network.IELength,rsn_ie,&rsn_len,wpa_ie,&wpa_len); ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_info_,("rtw_wx_get_scan: ssid=%s\n",pnetwork->network.Ssid.Ssid)); ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_info_,("rtw_wx_get_scan: wpa_len=%d rsn_len=%d\n",wpa_len,rsn_len)); ++ ++ if (wpa_len > 0) ++ { ++ p=buf; ++ _rtw_memset(buf, 0, MAX_WPA_IE_LEN); ++ p += sprintf(p, "wpa_ie="); ++ for (i = 0; i < wpa_len; i++) { ++ p += sprintf(p, "%02x", wpa_ie[i]); ++ } ++ ++ _rtw_memset(&iwe, 0, sizeof(iwe)); ++ iwe.cmd = IWEVCUSTOM; ++ iwe.u.data.length = strlen(buf); ++ start = iwe_stream_add_point(info, start, stop, &iwe,buf); ++ ++ _rtw_memset(&iwe, 0, sizeof(iwe)); ++ iwe.cmd =IWEVGENIE; ++ iwe.u.data.length = wpa_len; ++ start = iwe_stream_add_point(info, start, stop, &iwe, wpa_ie); ++ } ++ if (rsn_len > 0) ++ { ++ p = buf; ++ _rtw_memset(buf, 0, MAX_WPA_IE_LEN); ++ p += sprintf(p, "rsn_ie="); ++ for (i = 0; i < rsn_len; i++) { ++ p += sprintf(p, "%02x", rsn_ie[i]); ++ } ++ _rtw_memset(&iwe, 0, sizeof(iwe)); ++ iwe.cmd = IWEVCUSTOM; ++ iwe.u.data.length = strlen(buf); ++ start = iwe_stream_add_point(info, start, stop, &iwe,buf); ++ ++ _rtw_memset(&iwe, 0, sizeof(iwe)); ++ iwe.cmd =IWEVGENIE; ++ iwe.u.data.length = rsn_len; ++ start = iwe_stream_add_point(info, start, stop, &iwe, rsn_ie); ++ } ++ } ++ ++ { //parsing WPS IE ++ int cnt = 0,total_ielen=0; ++ u8 *wpsie_ptr=NULL; ++ uint wps_ielen = 0; ++ ++ u8 *ie_ptr = pnetwork->network.IEs +_FIXED_IE_LENGTH_; ++ total_ielen= pnetwork->network.IELength - _FIXED_IE_LENGTH_; ++ if((ie_ptr) && (total_ielen>0)) ++ { ++ while(cnt < total_ielen) ++ { ++ if(rtw_is_wps_ie(&ie_ptr[cnt], &wps_ielen) && (wps_ielen>2)) ++ { ++ wpsie_ptr = &ie_ptr[cnt]; ++ iwe.cmd =IWEVGENIE; ++ iwe.u.data.length = (u16)wps_ielen; ++ start = iwe_stream_add_point(info, start, stop, &iwe, wpsie_ptr); ++ } ++ cnt+=ie_ptr[cnt+1]+2; //goto next ++ } ++ } ++ } ++ ++ /* Add quality statistics */ ++ iwe.cmd = IWEVQUAL; ++ rssi = pnetwork->network.Rssi;//dBM ++ ++#ifdef CONFIG_RTL8711 ++ rssi = (rssi*2) + 190; ++ if(rssi>100) rssi = 100; ++ if(rssi<0) rssi = 0; ++#endif ++ ++ //DBG_8192C("RSSI=0x%X%%\n", rssi); ++ ++ // we only update signal_level (signal strength) that is rssi. ++ iwe.u.qual.updated = IW_QUAL_QUAL_UPDATED | IW_QUAL_LEVEL_UPDATED | IW_QUAL_NOISE_INVALID ++#ifdef CONFIG_PLATFORM_MT53XX ++ ; ++ iwe.u.qual.level = (u8)pnetwork->network.PhyInfo.SignalStrength;//% ++#else ++ #ifdef CONFIG_SIGNAL_DISPLAY_DBM ++ | IW_QUAL_DBM ++ #endif ++ ; ++ ++ #ifdef CONFIG_SIGNAL_DISPLAY_DBM ++ iwe.u.qual.level = (u8) translate_percentage_to_dbm(pnetwork->network.PhyInfo.SignalStrength);//dbm ++ #else ++ iwe.u.qual.level = (u8)pnetwork->network.PhyInfo.SignalStrength;//% ++ #endif ++#endif ++ iwe.u.qual.qual = (u8)pnetwork->network.PhyInfo.SignalQuality; // signal quality ++ ++ #ifdef CONFIG_PLATFORM_ROCKCHIPS ++ iwe.u.qual.noise = -100; // noise level suggest by zhf@rockchips ++ #else ++ iwe.u.qual.noise = 0; // noise level ++ #endif //CONFIG_PLATFORM_ROCKCHIPS ++ ++ //DBG_8192C("iqual=%d, ilevel=%d, inoise=%d, iupdated=%d\n", iwe.u.qual.qual, iwe.u.qual.level , iwe.u.qual.noise, iwe.u.qual.updated); ++ ++ start = iwe_stream_add_event(info, start, stop, &iwe, IW_EV_QUAL_LEN); ++ ++ //how to translate rssi to ?% ++ //rssi = (iwe.u.qual.level*2) + 190; ++ //if(rssi>100) rssi = 100; ++ //if(rssi<0) rssi = 0; ++ ++ return start; ++} ++ ++static int wpa_set_auth_algs(struct net_device *dev, u32 value) ++{ ++ _adapter *padapter = (_adapter *) rtw_netdev_priv(dev); ++ int ret = 0; ++ ++ if ((value & AUTH_ALG_SHARED_KEY)&&(value & AUTH_ALG_OPEN_SYSTEM)) ++ { ++ DBG_8192C("wpa_set_auth_algs, AUTH_ALG_SHARED_KEY and AUTH_ALG_OPEN_SYSTEM [value:0x%x]\n",value); ++ padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption1Enabled; ++ padapter->securitypriv.ndisauthtype = Ndis802_11AuthModeAutoSwitch; ++ padapter->securitypriv.dot11AuthAlgrthm = dot11AuthAlgrthm_Auto; ++ } ++ else if (value & AUTH_ALG_SHARED_KEY) ++ { ++ DBG_8192C("wpa_set_auth_algs, AUTH_ALG_SHARED_KEY [value:0x%x]\n",value); ++ padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption1Enabled; ++ ++#ifdef CONFIG_PLATFORM_MT53XX ++ padapter->securitypriv.ndisauthtype = Ndis802_11AuthModeAutoSwitch; ++ padapter->securitypriv.dot11AuthAlgrthm = dot11AuthAlgrthm_Auto; ++#else ++ padapter->securitypriv.ndisauthtype = Ndis802_11AuthModeShared; ++ padapter->securitypriv.dot11AuthAlgrthm = dot11AuthAlgrthm_Shared; ++#endif ++ } ++ else if(value & AUTH_ALG_OPEN_SYSTEM) ++ { ++ DBG_8192C("wpa_set_auth_algs, AUTH_ALG_OPEN_SYSTEM\n"); ++ //padapter->securitypriv.ndisencryptstatus = Ndis802_11EncryptionDisabled; ++ if(padapter->securitypriv.ndisauthtype < Ndis802_11AuthModeWPAPSK) ++ { ++#ifdef CONFIG_PLATFORM_MT53XX ++ padapter->securitypriv.ndisauthtype = Ndis802_11AuthModeAutoSwitch; ++ padapter->securitypriv.dot11AuthAlgrthm = dot11AuthAlgrthm_Auto; ++#else ++ padapter->securitypriv.ndisauthtype = Ndis802_11AuthModeOpen; ++ padapter->securitypriv.dot11AuthAlgrthm = dot11AuthAlgrthm_Open; ++#endif ++ } ++ ++ } ++ else if(value & AUTH_ALG_LEAP) ++ { ++ DBG_8192C("wpa_set_auth_algs, AUTH_ALG_LEAP\n"); ++ } ++ else ++ { ++ DBG_8192C("wpa_set_auth_algs, error!\n"); ++ ret = -EINVAL; ++ } ++ ++ return ret; ++ ++} ++ ++static int wpa_set_encryption(struct net_device *dev, struct ieee_param *param, u32 param_len) ++{ ++ int ret = 0; ++ u32 wep_key_idx, wep_key_len,wep_total_len; ++ NDIS_802_11_WEP *pwep = NULL; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct security_priv *psecuritypriv = &padapter->securitypriv; ++#ifdef CONFIG_P2P ++ struct wifidirect_info* pwdinfo = &padapter->wdinfo; ++#endif //CONFIG_P2P ++ ++_func_enter_; ++ ++ param->u.crypt.err = 0; ++ param->u.crypt.alg[IEEE_CRYPT_ALG_NAME_LEN - 1] = '\0'; ++ ++ if (param_len < (u32) ((u8 *) param->u.crypt.key - (u8 *) param) + param->u.crypt.key_len) ++ { ++ ret = -EINVAL; ++ goto exit; ++ } ++ ++ if (param->sta_addr[0] == 0xff && param->sta_addr[1] == 0xff && ++ param->sta_addr[2] == 0xff && param->sta_addr[3] == 0xff && ++ param->sta_addr[4] == 0xff && param->sta_addr[5] == 0xff) ++ { ++ if (param->u.crypt.idx >= WEP_KEYS) ++ { ++ ret = -EINVAL; ++ goto exit; ++ } ++ } else { ++ ret = -EINVAL; ++ goto exit; ++ } ++ ++ if (strcmp(param->u.crypt.alg, "WEP") == 0) ++ { ++ RT_TRACE(_module_rtl871x_ioctl_os_c,_drv_err_,("wpa_set_encryption, crypt.alg = WEP\n")); ++ DBG_8192C("wpa_set_encryption, crypt.alg = WEP\n"); ++ ++ padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption1Enabled; ++ padapter->securitypriv.dot11PrivacyAlgrthm=_WEP40_; ++ padapter->securitypriv.dot118021XGrpPrivacy=_WEP40_; ++ ++ wep_key_idx = param->u.crypt.idx; ++ wep_key_len = param->u.crypt.key_len; ++ ++ RT_TRACE(_module_rtl871x_ioctl_os_c,_drv_info_,("(1)wep_key_idx=%d\n", wep_key_idx)); ++ DBG_8192C("(1)wep_key_idx=%d\n", wep_key_idx); ++ ++ if (wep_key_idx > WEP_KEYS) ++ return -EINVAL; ++ ++ RT_TRACE(_module_rtl871x_ioctl_os_c,_drv_info_,("(2)wep_key_idx=%d\n", wep_key_idx)); ++ ++ if (wep_key_len > 0) ++ { ++ wep_key_len = wep_key_len <= 5 ? 5 : 13; ++ wep_total_len = wep_key_len + FIELD_OFFSET(NDIS_802_11_WEP, KeyMaterial); ++ pwep =(NDIS_802_11_WEP *) rtw_malloc(wep_total_len); ++ if(pwep == NULL){ ++ RT_TRACE(_module_rtl871x_ioctl_os_c,_drv_err_,(" wpa_set_encryption: pwep allocate fail !!!\n")); ++ goto exit; ++ } ++ ++ _rtw_memset(pwep, 0, wep_total_len); ++ ++ pwep->KeyLength = wep_key_len; ++ pwep->Length = wep_total_len; ++ ++ if(wep_key_len==13) ++ { ++ padapter->securitypriv.dot11PrivacyAlgrthm=_WEP104_; ++ padapter->securitypriv.dot118021XGrpPrivacy=_WEP104_; ++ } ++ } ++ else { ++ ret = -EINVAL; ++ goto exit; ++ } ++ ++ pwep->KeyIndex = wep_key_idx; ++ pwep->KeyIndex |= 0x80000000; ++ ++ _rtw_memcpy(pwep->KeyMaterial, param->u.crypt.key, pwep->KeyLength); ++ ++ if(param->u.crypt.set_tx) ++ { ++ DBG_8192C("wep, set_tx=1\n"); ++ ++ if(rtw_set_802_11_add_wep(padapter, pwep) == (u8)_FAIL) ++ { ++ ret = -EOPNOTSUPP ; ++ } ++ } ++ else ++ { ++ DBG_8192C("wep, set_tx=0\n"); ++ ++ //don't update "psecuritypriv->dot11PrivacyAlgrthm" and ++ //"psecuritypriv->dot11PrivacyKeyIndex=keyid", but can rtw_set_key to fw/cam ++ ++ if (wep_key_idx >= WEP_KEYS) { ++ ret = -EOPNOTSUPP ; ++ goto exit; ++ } ++ ++ _rtw_memcpy(&(psecuritypriv->dot11DefKey[wep_key_idx].skey[0]), pwep->KeyMaterial, pwep->KeyLength); ++ psecuritypriv->dot11DefKeylen[wep_key_idx]=pwep->KeyLength; ++ rtw_set_key(padapter, psecuritypriv, wep_key_idx, 0); ++ } ++ ++ goto exit; ++ } ++ ++ if(padapter->securitypriv.dot11AuthAlgrthm == dot11AuthAlgrthm_8021X) // 802_1x ++ { ++ struct sta_info * psta,*pbcmc_sta; ++ struct sta_priv * pstapriv = &padapter->stapriv; ++ ++ if (check_fwstate(pmlmepriv, WIFI_STATION_STATE | WIFI_MP_STATE) == _TRUE) //sta mode ++ { ++ psta = rtw_get_stainfo(pstapriv, get_bssid(pmlmepriv)); ++ if (psta == NULL) { ++ //DEBUG_ERR( ("Set wpa_set_encryption: Obtain Sta_info fail \n")); ++ } ++ else ++ { ++ //Jeff: don't disable ieee8021x_blocked while clearing key ++ if (strcmp(param->u.crypt.alg, "none") != 0) ++ psta->ieee8021x_blocked = _FALSE; ++ ++ if((padapter->securitypriv.ndisencryptstatus == Ndis802_11Encryption2Enabled)|| ++ (padapter->securitypriv.ndisencryptstatus == Ndis802_11Encryption3Enabled)) ++ { ++ psta->dot118021XPrivacy = padapter->securitypriv.dot11PrivacyAlgrthm; ++ } ++ ++ if(param->u.crypt.set_tx ==1)//pairwise key ++ { ++ _rtw_memcpy(psta->dot118021x_UncstKey.skey, param->u.crypt.key, (param->u.crypt.key_len>16 ?16:param->u.crypt.key_len)); ++ ++ if(strcmp(param->u.crypt.alg, "TKIP") == 0)//set mic key ++ { ++ //DEBUG_ERR(("\nset key length :param->u.crypt.key_len=%d\n", param->u.crypt.key_len)); ++ _rtw_memcpy(psta->dot11tkiptxmickey.skey, &(param->u.crypt.key[16]), 8); ++ _rtw_memcpy(psta->dot11tkiprxmickey.skey, &(param->u.crypt.key[24]), 8); ++ ++ padapter->securitypriv.busetkipkey=_FALSE; ++ //_set_timer(&padapter->securitypriv.tkip_timer, 50); ++ } ++ ++ //DEBUG_ERR(("\n param->u.crypt.key_len=%d\n",param->u.crypt.key_len)); ++ //DEBUG_ERR(("\n ~~~~stastakey:unicastkey\n")); ++ DBG_871X("\n ~~~~stastakey:unicastkey\n"); ++ ++ rtw_setstakey_cmd(padapter, (unsigned char *)psta, _TRUE); ++ } ++ else//group key ++ { ++ _rtw_memcpy(padapter->securitypriv.dot118021XGrpKey[param->u.crypt.idx].skey, param->u.crypt.key,(param->u.crypt.key_len>16 ?16:param->u.crypt.key_len)); ++ _rtw_memcpy(padapter->securitypriv.dot118021XGrptxmickey[param->u.crypt.idx].skey,&(param->u.crypt.key[16]),8); ++ _rtw_memcpy(padapter->securitypriv.dot118021XGrprxmickey[param->u.crypt.idx].skey,&(param->u.crypt.key[24]),8); ++ padapter->securitypriv.binstallGrpkey = _TRUE; ++ //DEBUG_ERR(("\n param->u.crypt.key_len=%d\n", param->u.crypt.key_len)); ++ //DEBUG_ERR(("\n ~~~~stastakey:groupkey\n")); ++ DBG_871X("\n ~~~~stastakey:groupkey\n"); ++ ++ padapter->securitypriv.dot118021XGrpKeyid = param->u.crypt.idx; ++ ++ rtw_set_key(padapter,&padapter->securitypriv,param->u.crypt.idx, 1); ++#ifdef CONFIG_P2P ++ if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_PROVISIONING_ING)) ++ { ++ rtw_p2p_set_state(pwdinfo, P2P_STATE_PROVISIONING_DONE); ++ } ++#endif //CONFIG_P2P ++ ++ } ++ } ++ ++ pbcmc_sta=rtw_get_bcmc_stainfo(padapter); ++ if(pbcmc_sta==NULL) ++ { ++ //DEBUG_ERR( ("Set OID_802_11_ADD_KEY: bcmc stainfo is null \n")); ++ } ++ else ++ { ++ //Jeff: don't disable ieee8021x_blocked while clearing key ++ if (strcmp(param->u.crypt.alg, "none") != 0) ++ pbcmc_sta->ieee8021x_blocked = _FALSE; ++ ++ if((padapter->securitypriv.ndisencryptstatus == Ndis802_11Encryption2Enabled)|| ++ (padapter->securitypriv.ndisencryptstatus == Ndis802_11Encryption3Enabled)) ++ { ++ pbcmc_sta->dot118021XPrivacy = padapter->securitypriv.dot11PrivacyAlgrthm; ++ } ++ } ++ } ++ else if(check_fwstate(pmlmepriv, WIFI_ADHOC_STATE)) //adhoc mode ++ { ++ } ++ } ++ ++exit: ++ ++ if (pwep) { ++ rtw_mfree((u8 *)pwep,wep_total_len); ++ } ++ ++ _func_exit_; ++ ++ return ret; ++} ++ ++static int rtw_set_wpa_ie(_adapter *padapter, char *pie, unsigned short ielen) ++{ ++ u8 *buf=NULL, *pos=NULL; ++ u32 left; ++ int group_cipher = 0, pairwise_cipher = 0; ++ int ret = 0; ++#ifdef CONFIG_P2P ++ struct wifidirect_info* pwdinfo = &padapter->wdinfo; ++#endif //CONFIG_P2P ++ ++ if((ielen > MAX_WPA_IE_LEN) || (pie == NULL)){ ++ padapter->securitypriv.wps_phase = _FALSE; ++ if(pie == NULL) ++ return ret; ++ else ++ return -EINVAL; ++ } ++ ++ if(ielen) ++ { ++ buf = rtw_zmalloc(ielen); ++ if (buf == NULL){ ++ ret = -ENOMEM; ++ goto exit; ++ } ++ ++ _rtw_memcpy(buf, pie , ielen); ++ ++ //dump ++ { ++ int i; ++ DBG_8192C("\n wpa_ie(length:%d):\n", ielen); ++ for(i=0;i= RSN_SELECTOR_LEN){ ++ pos += RSN_SELECTOR_LEN; ++ left -= RSN_SELECTOR_LEN; ++ } ++ else if (left > 0){ ++ RT_TRACE(_module_rtl871x_ioctl_os_c,_drv_err_,("Ie length mismatch, %u too much \n", left)); ++ ret =-1; ++ goto exit; ++ } ++#endif ++ ++ if(rtw_parse_wpa_ie(buf, ielen, &group_cipher, &pairwise_cipher) == _SUCCESS) ++ { ++ padapter->securitypriv.dot11AuthAlgrthm= dot11AuthAlgrthm_8021X; ++ padapter->securitypriv.ndisauthtype=Ndis802_11AuthModeWPAPSK; ++ _rtw_memcpy(padapter->securitypriv.supplicant_ie, &buf[0], ielen); ++ } ++ ++ if(rtw_parse_wpa2_ie(buf, ielen, &group_cipher, &pairwise_cipher) == _SUCCESS) ++ { ++ padapter->securitypriv.dot11AuthAlgrthm= dot11AuthAlgrthm_8021X; ++ padapter->securitypriv.ndisauthtype=Ndis802_11AuthModeWPA2PSK; ++ _rtw_memcpy(padapter->securitypriv.supplicant_ie, &buf[0], ielen); ++ } ++ ++ switch(group_cipher) ++ { ++ case WPA_CIPHER_NONE: ++ padapter->securitypriv.dot118021XGrpPrivacy=_NO_PRIVACY_; ++ padapter->securitypriv.ndisencryptstatus=Ndis802_11EncryptionDisabled; ++ break; ++ case WPA_CIPHER_WEP40: ++ padapter->securitypriv.dot118021XGrpPrivacy=_WEP40_; ++ padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption1Enabled; ++ break; ++ case WPA_CIPHER_TKIP: ++ padapter->securitypriv.dot118021XGrpPrivacy=_TKIP_; ++ padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption2Enabled; ++ break; ++ case WPA_CIPHER_CCMP: ++ padapter->securitypriv.dot118021XGrpPrivacy=_AES_; ++ padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption3Enabled; ++ break; ++ case WPA_CIPHER_WEP104: ++ padapter->securitypriv.dot118021XGrpPrivacy=_WEP104_; ++ padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption1Enabled; ++ break; ++ } ++ ++ switch(pairwise_cipher) ++ { ++ case WPA_CIPHER_NONE: ++ padapter->securitypriv.dot11PrivacyAlgrthm=_NO_PRIVACY_; ++ padapter->securitypriv.ndisencryptstatus=Ndis802_11EncryptionDisabled; ++ break; ++ case WPA_CIPHER_WEP40: ++ padapter->securitypriv.dot11PrivacyAlgrthm=_WEP40_; ++ padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption1Enabled; ++ break; ++ case WPA_CIPHER_TKIP: ++ padapter->securitypriv.dot11PrivacyAlgrthm=_TKIP_; ++ padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption2Enabled; ++ break; ++ case WPA_CIPHER_CCMP: ++ padapter->securitypriv.dot11PrivacyAlgrthm=_AES_; ++ padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption3Enabled; ++ break; ++ case WPA_CIPHER_WEP104: ++ padapter->securitypriv.dot11PrivacyAlgrthm=_WEP104_; ++ padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption1Enabled; ++ break; ++ } ++ ++ padapter->securitypriv.wps_phase = _FALSE; ++ {//set wps_ie ++ u16 cnt = 0; ++ u8 eid, wps_oui[4]={0x0,0x50,0xf2,0x04}; ++ ++ while( cnt < ielen ) ++ { ++ eid = buf[cnt]; ++ ++ if((eid==_VENDOR_SPECIFIC_IE_)&&(_rtw_memcmp(&buf[cnt+2], wps_oui, 4)==_TRUE)) ++ { ++ DBG_8192C("SET WPS_IE\n"); ++ ++ padapter->securitypriv.wps_ie_len = ( (buf[cnt+1]+2) < (MAX_WPA_IE_LEN<<2)) ? (buf[cnt+1]+2):(MAX_WPA_IE_LEN<<2); ++ ++ _rtw_memcpy(padapter->securitypriv.wps_ie, &buf[cnt], padapter->securitypriv.wps_ie_len); ++ ++ padapter->securitypriv.wps_phase = _TRUE; ++ ++#ifdef CONFIG_P2P ++ if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_GONEGO_OK)) ++ { ++ rtw_p2p_set_state(pwdinfo, P2P_STATE_PROVISIONING_ING); ++ } ++#endif //CONFIG_P2P ++ DBG_8192C("SET WPS_IE, wps_phase==_TRUE\n"); ++ ++ cnt += buf[cnt+1]+2; ++ ++ break; ++ } else { ++ cnt += buf[cnt+1]+2; //goto next ++ } ++ } ++ } ++ } ++ ++ RT_TRACE(_module_rtl871x_ioctl_os_c, _drv_info_, ++ ("rtw_set_wpa_ie: pairwise_cipher=0x%08x padapter->securitypriv.ndisencryptstatus=%d padapter->securitypriv.ndisauthtype=%d\n", ++ pairwise_cipher, padapter->securitypriv.ndisencryptstatus, padapter->securitypriv.ndisauthtype)); ++ ++exit: ++ ++ if (buf) rtw_mfree(buf, ielen); ++ ++ return ret; ++} ++ ++static int rtw_wx_get_name(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ u16 cap; ++ u32 ht_ielen = 0; ++ char *p; ++ u8 ht_cap=_FALSE; ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ WLAN_BSSID_EX *pcur_bss = &pmlmepriv->cur_network.network; ++ NDIS_802_11_RATES_EX* prates = NULL; ++ ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_info_,("cmd_code=%x\n", info->cmd)); ++ ++ _func_enter_; ++ ++ if (check_fwstate(pmlmepriv, _FW_LINKED|WIFI_ADHOC_MASTER_STATE) == _TRUE) ++ { ++ //parsing HT_CAP_IE ++ p = rtw_get_ie(&pcur_bss->IEs[12], _HT_CAPABILITY_IE_, &ht_ielen, pcur_bss->IELength-12); ++ if(p && ht_ielen>0) ++ { ++ ht_cap = _TRUE; ++ } ++ ++ prates = &pcur_bss->SupportedRates; ++ ++ if (rtw_is_cckratesonly_included((u8*)prates) == _TRUE) ++ { ++ if(ht_cap == _TRUE) ++ snprintf(wrqu->name, IFNAMSIZ, "IEEE 802.11bn"); ++ else ++ snprintf(wrqu->name, IFNAMSIZ, "IEEE 802.11b"); ++ } ++ else if ((rtw_is_cckrates_included((u8*)prates)) == _TRUE) ++ { ++ if(ht_cap == _TRUE) ++ snprintf(wrqu->name, IFNAMSIZ, "IEEE 802.11bgn"); ++ else ++ snprintf(wrqu->name, IFNAMSIZ, "IEEE 802.11bg"); ++ } ++ else ++ { ++ if(pcur_bss->Configuration.DSConfig > 14) ++ { ++ if(ht_cap == _TRUE) ++ snprintf(wrqu->name, IFNAMSIZ, "IEEE 802.11an"); ++ else ++ snprintf(wrqu->name, IFNAMSIZ, "IEEE 802.11a"); ++ } ++ else ++ { ++ if(ht_cap == _TRUE) ++ snprintf(wrqu->name, IFNAMSIZ, "IEEE 802.11gn"); ++ else ++ snprintf(wrqu->name, IFNAMSIZ, "IEEE 802.11g"); ++ } ++ } ++ } ++ else ++ { ++ //prates = &padapter->registrypriv.dev_network.SupportedRates; ++ //snprintf(wrqu->name, IFNAMSIZ, "IEEE 802.11g"); ++ snprintf(wrqu->name, IFNAMSIZ, "unassociated"); ++ } ++ ++ _func_exit_; ++ ++ return 0; ++} ++ ++static int rtw_wx_set_freq(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ _func_enter_; ++ ++ RT_TRACE(_module_rtl871x_mlme_c_, _drv_notice_, ("+rtw_wx_set_freq\n")); ++ ++ _func_exit_; ++ ++ return 0; ++} ++ ++static int rtw_wx_get_freq(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ WLAN_BSSID_EX *pcur_bss = &pmlmepriv->cur_network.network; ++ ++ if(check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) ++ { ++ //wrqu->freq.m = ieee80211_wlan_frequencies[pcur_bss->Configuration.DSConfig-1] * 100000; ++ wrqu->freq.m = rtw_ch2freq(pcur_bss->Configuration.DSConfig) * 100000; ++ wrqu->freq.e = 1; ++ wrqu->freq.i = pcur_bss->Configuration.DSConfig; ++ ++ } ++ else{ ++ wrqu->freq.m = rtw_ch2freq(padapter->mlmeextpriv.cur_channel) * 100000; ++ wrqu->freq.e = 1; ++ wrqu->freq.i = padapter->mlmeextpriv.cur_channel; ++ } ++ ++ return 0; ++} ++ ++static int rtw_wx_set_mode(struct net_device *dev, struct iw_request_info *a, ++ union iwreq_data *wrqu, char *b) ++{ ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ NDIS_802_11_NETWORK_INFRASTRUCTURE networkType ; ++ int ret = 0; ++ ++ _func_enter_; ++ ++ if(_FAIL == rfpwrstate_check(padapter)) { ++ ret= -EPERM; ++ goto exit; ++ } ++ ++ if (padapter->hw_init_completed==_FALSE){ ++ ret = -EPERM; ++ goto exit; ++ } ++ ++ switch(wrqu->mode) ++ { ++ case IW_MODE_AUTO: ++ networkType = Ndis802_11AutoUnknown; ++ DBG_8192C("set_mode = IW_MODE_AUTO\n"); ++ break; ++ case IW_MODE_ADHOC: ++ networkType = Ndis802_11IBSS; ++ DBG_8192C("set_mode = IW_MODE_ADHOC\n"); ++ break; ++ case IW_MODE_MASTER: ++ networkType = Ndis802_11APMode; ++ DBG_8192C("set_mode = IW_MODE_MASTER\n"); ++ //rtw_setopmode_cmd(padapter, networkType); ++ break; ++ case IW_MODE_INFRA: ++ networkType = Ndis802_11Infrastructure; ++ DBG_8192C("set_mode = IW_MODE_INFRA\n"); ++ break; ++ ++ default : ++ ret = -EINVAL;; ++ RT_TRACE(_module_rtl871x_ioctl_os_c,_drv_err_,("\n Mode: %s is not supported \n", iw_operation_mode[wrqu->mode])); ++ goto exit; ++ } ++ ++/* ++ if(Ndis802_11APMode == networkType) ++ { ++ rtw_setopmode_cmd(padapter, networkType); ++ } ++ else ++ { ++ rtw_setopmode_cmd(padapter, Ndis802_11AutoUnknown); ++ } ++*/ ++ ++ if (rtw_set_802_11_infrastructure_mode(padapter, networkType) ==_FALSE){ ++ ++ ret = -EPERM; ++ goto exit; ++ ++ } ++ ++ rtw_setopmode_cmd(padapter, networkType); ++ ++exit: ++ ++ _func_exit_; ++ ++ return ret; ++ ++} ++ ++static int rtw_wx_get_mode(struct net_device *dev, struct iw_request_info *a, ++ union iwreq_data *wrqu, char *b) ++{ ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_info_,(" rtw_wx_get_mode \n")); ++ ++ _func_enter_; ++ ++ if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == _TRUE) ++ { ++ wrqu->mode = IW_MODE_INFRA; ++ } ++ else if ((check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE) || ++ (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE)) ++ ++ { ++ wrqu->mode = IW_MODE_ADHOC; ++ } ++ else if(check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) ++ { ++ wrqu->mode = IW_MODE_MASTER; ++ } ++ else ++ { ++ wrqu->mode = IW_MODE_AUTO; ++ } ++ ++ _func_exit_; ++ ++ return 0; ++ ++} ++ ++ ++static int rtw_wx_set_pmkid(struct net_device *dev, ++ struct iw_request_info *a, ++ union iwreq_data *wrqu, char *extra) ++{ ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ u8 j,blInserted = _FALSE; ++ int intReturn = _FALSE; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct security_priv *psecuritypriv = &padapter->securitypriv; ++ struct iw_pmksa* pPMK = ( struct iw_pmksa* ) extra; ++ u8 strZeroMacAddress[ ETH_ALEN ] = { 0x00 }; ++ u8 strIssueBssid[ ETH_ALEN ] = { 0x00 }; ++ ++/* ++ struct iw_pmksa ++ { ++ __u32 cmd; ++ struct sockaddr bssid; ++ __u8 pmkid[IW_PMKID_LEN]; //IW_PMKID_LEN=16 ++ } ++ There are the BSSID information in the bssid.sa_data array. ++ If cmd is IW_PMKSA_FLUSH, it means the wpa_suppplicant wants to clear all the PMKID information. ++ If cmd is IW_PMKSA_ADD, it means the wpa_supplicant wants to add a PMKID/BSSID to driver. ++ If cmd is IW_PMKSA_REMOVE, it means the wpa_supplicant wants to remove a PMKID/BSSID from driver. ++ */ ++ ++ _rtw_memcpy( strIssueBssid, pPMK->bssid.sa_data, ETH_ALEN); ++ if ( pPMK->cmd == IW_PMKSA_ADD ) ++ { ++ DBG_8192C( "[rtw_wx_set_pmkid] IW_PMKSA_ADD!\n" ); ++ if ( _rtw_memcmp( strIssueBssid, strZeroMacAddress, ETH_ALEN ) == _TRUE ) ++ { ++ return( intReturn ); ++ } ++ else ++ { ++ intReturn = _TRUE; ++ } ++ blInserted = _FALSE; ++ ++ //overwrite PMKID ++ for(j=0 ; jPMKIDList[j].Bssid, strIssueBssid, ETH_ALEN) ==_TRUE ) ++ { // BSSID is matched, the same AP => rewrite with new PMKID. ++ ++ DBG_8192C( "[rtw_wx_set_pmkid] BSSID exists in the PMKList.\n" ); ++ ++ _rtw_memcpy( psecuritypriv->PMKIDList[j].PMKID, pPMK->pmkid, IW_PMKID_LEN); ++ psecuritypriv->PMKIDList[ j ].bUsed = _TRUE; ++ psecuritypriv->PMKIDIndex = j+1; ++ blInserted = _TRUE; ++ break; ++ } ++ } ++ ++ if(!blInserted) ++ { ++ // Find a new entry ++ DBG_8192C( "[rtw_wx_set_pmkid] Use the new entry index = %d for this PMKID.\n", ++ psecuritypriv->PMKIDIndex ); ++ ++ _rtw_memcpy(psecuritypriv->PMKIDList[psecuritypriv->PMKIDIndex].Bssid, strIssueBssid, ETH_ALEN); ++ _rtw_memcpy(psecuritypriv->PMKIDList[psecuritypriv->PMKIDIndex].PMKID, pPMK->pmkid, IW_PMKID_LEN); ++ ++ psecuritypriv->PMKIDList[ psecuritypriv->PMKIDIndex ].bUsed = _TRUE; ++ psecuritypriv->PMKIDIndex++ ; ++ if(psecuritypriv->PMKIDIndex==16) ++ { ++ psecuritypriv->PMKIDIndex =0; ++ } ++ } ++ } ++ else if ( pPMK->cmd == IW_PMKSA_REMOVE ) ++ { ++ DBG_8192C( "[rtw_wx_set_pmkid] IW_PMKSA_REMOVE!\n" ); ++ intReturn = _TRUE; ++ for(j=0 ; jPMKIDList[j].Bssid, strIssueBssid, ETH_ALEN) ==_TRUE ) ++ { // BSSID is matched, the same AP => Remove this PMKID information and reset it. ++ _rtw_memset( psecuritypriv->PMKIDList[ j ].Bssid, 0x00, ETH_ALEN ); ++ psecuritypriv->PMKIDList[ j ].bUsed = _FALSE; ++ break; ++ } ++ } ++ } ++ else if ( pPMK->cmd == IW_PMKSA_FLUSH ) ++ { ++ DBG_8192C( "[rtw_wx_set_pmkid] IW_PMKSA_FLUSH!\n" ); ++ _rtw_memset( &psecuritypriv->PMKIDList[ 0 ], 0x00, sizeof( RT_PMKID_LIST ) * NUM_PMKID_CACHE ); ++ psecuritypriv->PMKIDIndex = 0; ++ intReturn = _TRUE; ++ } ++ return( intReturn ); ++} ++ ++static int rtw_wx_get_sens(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ #ifdef CONFIG_PLATFORM_ROCKCHIPS ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ ++ /* ++ * 20110311 Commented by Jeff ++ * For rockchip platform's wpa_driver_wext_get_rssi ++ */ ++ if(check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) { ++ //wrqu->sens.value=-padapter->recvpriv.signal_strength; ++ wrqu->sens.value=-padapter->recvpriv.rssi; ++ //DBG_871X("%s: %d\n", __FUNCTION__, wrqu->sens.value); ++ wrqu->sens.fixed = 0; /* no auto select */ ++ } else ++ #endif ++ { ++ wrqu->sens.value = 0; ++ wrqu->sens.fixed = 0; /* no auto select */ ++ wrqu->sens.disabled = 1; ++ } ++ return 0; ++} ++ ++static int rtw_wx_get_range(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ struct iw_range *range = (struct iw_range *)extra; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ ++ u16 val; ++ int i; ++ ++ _func_enter_; ++ ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_info_,("rtw_wx_get_range. cmd_code=%x\n", info->cmd)); ++ ++ wrqu->data.length = sizeof(*range); ++ _rtw_memset(range, 0, sizeof(*range)); ++ ++ /* Let's try to keep this struct in the same order as in ++ * linux/include/wireless.h ++ */ ++ ++ /* TODO: See what values we can set, and remove the ones we can't ++ * set, or fill them with some default data. ++ */ ++ ++ /* ~5 Mb/s real (802.11b) */ ++ range->throughput = 5 * 1000 * 1000; ++ ++ // TODO: Not used in 802.11b? ++// range->min_nwid; /* Minimal NWID we are able to set */ ++ // TODO: Not used in 802.11b? ++// range->max_nwid; /* Maximal NWID we are able to set */ ++ ++ /* Old Frequency (backward compat - moved lower ) */ ++// range->old_num_channels; ++// range->old_num_frequency; ++// range->old_freq[6]; /* Filler to keep "version" at the same offset */ ++ ++ /* signal level threshold range */ ++ ++ //percent values between 0 and 100. ++ range->max_qual.qual = 100; ++ range->max_qual.level = 100; ++ range->max_qual.noise = 100; ++ range->max_qual.updated = 7; /* Updated all three */ ++ ++ ++ range->avg_qual.qual = 92; /* > 8% missed beacons is 'bad' */ ++ /* TODO: Find real 'good' to 'bad' threshol value for RSSI */ ++ range->avg_qual.level = 20 + -98; ++ range->avg_qual.noise = 0; ++ range->avg_qual.updated = 7; /* Updated all three */ ++ ++ range->num_bitrates = RATE_COUNT; ++ ++ for (i = 0; i < RATE_COUNT && i < IW_MAX_BITRATES; i++) { ++ range->bitrate[i] = rtw_rates[i]; ++ } ++ ++ range->min_frag = MIN_FRAG_THRESHOLD; ++ range->max_frag = MAX_FRAG_THRESHOLD; ++ ++ range->pm_capa = 0; ++ ++ range->we_version_compiled = WIRELESS_EXT; ++ range->we_version_source = 16; ++ ++// range->retry_capa; /* What retry options are supported */ ++// range->retry_flags; /* How to decode max/min retry limit */ ++// range->r_time_flags; /* How to decode max/min retry life */ ++// range->min_retry; /* Minimal number of retries */ ++// range->max_retry; /* Maximal number of retries */ ++// range->min_r_time; /* Minimal retry lifetime */ ++// range->max_r_time; /* Maximal retry lifetime */ ++ ++ for (i = 0, val = 0; i < MAX_CHANNEL_NUM; i++) { ++ ++ // Include only legal frequencies for some countries ++ if(pmlmeext->channel_set[i].ChannelNum != 0) ++ { ++ range->freq[val].i = pmlmeext->channel_set[i].ChannelNum; ++ range->freq[val].m = rtw_ch2freq(pmlmeext->channel_set[i].ChannelNum) * 100000; ++ range->freq[val].e = 1; ++ val++; ++ } ++ ++ if (val == IW_MAX_FREQUENCIES) ++ break; ++ } ++ ++ range->num_channels = val; ++ range->num_frequency = val; ++ ++// Commented by Albert 2009/10/13 ++// The following code will proivde the security capability to network manager. ++// If the driver doesn't provide this capability to network manager, ++// the WPA/WPA2 routers can't be choosen in the network manager. ++ ++/* ++#define IW_SCAN_CAPA_NONE 0x00 ++#define IW_SCAN_CAPA_ESSID 0x01 ++#define IW_SCAN_CAPA_BSSID 0x02 ++#define IW_SCAN_CAPA_CHANNEL 0x04 ++#define IW_SCAN_CAPA_MODE 0x08 ++#define IW_SCAN_CAPA_RATE 0x10 ++#define IW_SCAN_CAPA_TYPE 0x20 ++#define IW_SCAN_CAPA_TIME 0x40 ++*/ ++ ++#if WIRELESS_EXT > 17 ++ range->enc_capa = IW_ENC_CAPA_WPA|IW_ENC_CAPA_WPA2| ++ IW_ENC_CAPA_CIPHER_TKIP|IW_ENC_CAPA_CIPHER_CCMP; ++#endif ++ ++#ifdef IW_SCAN_CAPA_ESSID //WIRELESS_EXT > 21 ++ range->scan_capa = IW_SCAN_CAPA_ESSID | IW_SCAN_CAPA_TYPE |IW_SCAN_CAPA_BSSID| ++ IW_SCAN_CAPA_CHANNEL|IW_SCAN_CAPA_MODE|IW_SCAN_CAPA_RATE; ++#endif ++ ++ ++ _func_exit_; ++ ++ return 0; ++ ++} ++ ++//set bssid flow ++//s1. rtw_set_802_11_infrastructure_mode() ++//s2. rtw_set_802_11_authentication_mode() ++//s3. set_802_11_encryption_mode() ++//s4. rtw_set_802_11_bssid() ++static int rtw_wx_set_wap(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *awrq, ++ char *extra) ++{ ++ _irqL irqL; ++ uint ret = 0; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct sockaddr *temp = (struct sockaddr *)awrq; ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ _list *phead; ++ u8 *dst_bssid, *src_bssid; ++ _queue *queue = &(pmlmepriv->scanned_queue); ++ struct wlan_network *pnetwork = NULL; ++ NDIS_802_11_AUTHENTICATION_MODE authmode; ++ ++ _func_enter_; ++ ++ if(_FAIL == rfpwrstate_check(padapter)) ++ { ++ ret= -1; ++ goto exit; ++ } ++ ++ if(!padapter->bup){ ++ ret = -1; ++ goto exit; ++ } ++ ++ ++ if (temp->sa_family != ARPHRD_ETHER){ ++ ret = -EINVAL; ++ goto exit; ++ } ++ ++ authmode = padapter->securitypriv.ndisauthtype; ++ _enter_critical_bh(&queue->lock, &irqL); ++ phead = get_list_head(queue); ++ pmlmepriv->pscanned = get_next(phead); ++ ++ while (1) ++ { ++ ++ if ((rtw_end_of_queue_search(phead, pmlmepriv->pscanned)) == _TRUE) ++ { ++#if 0 ++ ret = -EINVAL; ++ goto exit; ++ ++ if(check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE) ++ { ++ rtw_set_802_11_bssid(padapter, temp->sa_data); ++ goto exit; ++ } ++ else ++ { ++ ret = -EINVAL; ++ goto exit; ++ } ++#endif ++ ++ break; ++ } ++ ++ pnetwork = LIST_CONTAINOR(pmlmepriv->pscanned, struct wlan_network, list); ++ ++ pmlmepriv->pscanned = get_next(pmlmepriv->pscanned); ++ ++ dst_bssid = pnetwork->network.MacAddress; ++ ++ src_bssid = temp->sa_data; ++ ++ if ((_rtw_memcmp(dst_bssid, src_bssid, ETH_ALEN)) == _TRUE) ++ { ++ if(!rtw_set_802_11_infrastructure_mode(padapter, pnetwork->network.InfrastructureMode)) ++ { ++ ret = -1; ++ _exit_critical_bh(&queue->lock, &irqL); ++ goto exit; ++ } ++ ++ break; ++ } ++ ++ } ++ _exit_critical_bh(&queue->lock, &irqL); ++ ++ rtw_set_802_11_authentication_mode(padapter, authmode); ++ //set_802_11_encryption_mode(padapter, padapter->securitypriv.ndisencryptstatus); ++ if (rtw_set_802_11_bssid(padapter, temp->sa_data) == _FALSE) { ++ ret = -1; ++ goto exit; ++ } ++ ++exit: ++ ++ _func_exit_; ++ ++ return ret; ++} ++ ++static int rtw_wx_get_wap(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ WLAN_BSSID_EX *pcur_bss = &pmlmepriv->cur_network.network; ++ ++ wrqu->ap_addr.sa_family = ARPHRD_ETHER; ++ ++ _rtw_memset(wrqu->ap_addr.sa_data, 0, ETH_ALEN); ++ ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_info_,("rtw_wx_get_wap\n")); ++ ++ _func_enter_; ++ ++ if ( ((check_fwstate(pmlmepriv, _FW_LINKED)) == _TRUE) || ++ ((check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE)) == _TRUE) || ++ ((check_fwstate(pmlmepriv, WIFI_AP_STATE)) == _TRUE) ) ++ { ++ ++ _rtw_memcpy(wrqu->ap_addr.sa_data, pcur_bss->MacAddress, ETH_ALEN); ++ } ++ else ++ { ++ _rtw_memset(wrqu->ap_addr.sa_data, 0, ETH_ALEN); ++ } ++ ++ _func_exit_; ++ ++ return 0; ++ ++} ++ ++static int rtw_wx_set_mlme(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++#if 0 ++/* SIOCSIWMLME data */ ++struct iw_mlme ++{ ++ __u16 cmd; /* IW_MLME_* */ ++ __u16 reason_code; ++ struct sockaddr addr; ++}; ++#endif ++ ++ int ret=0; ++ u16 reason; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct iw_mlme *mlme = (struct iw_mlme *) extra; ++ ++ ++ if(mlme==NULL) ++ return -1; ++ ++ reason = cpu_to_le16(mlme->reason_code); ++ ++ switch (mlme->cmd) ++ { ++ case IW_MLME_DEAUTH: ++ if(!rtw_set_802_11_disassociate(padapter)) ++ ret = -1; ++ break; ++ ++ case IW_MLME_DISASSOC: ++ if(!rtw_set_802_11_disassociate(padapter)) ++ ret = -1; ++ ++ break; ++ ++ default: ++ return -EOPNOTSUPP; ++ } ++ ++ return ret; ++ ++} ++ ++int rfpwrstate_check(_adapter *padapter) ++{ ++ struct pwrctrl_priv *pwrpriv = &padapter->pwrctrlpriv; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ int ret = _SUCCESS; ++ ++ //block here for system suspend only ++ if((pwrpriv->bInternalAutoSuspend == _FALSE) && (_TRUE == pwrpriv->bInSuspend )){ ++ ret = _FAIL; ++ goto exit; ++ } ++ ++ if( pwrpriv->power_mgnt == PS_MODE_ACTIVE ) { ++ goto exit; ++ } ++ ++ if((pwrpriv->bInternalAutoSuspend == _TRUE) && (padapter->net_closed == _TRUE)) { ++ ret = _FAIL; ++ goto exit; ++ } ++ if (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) ++ { ++ ret = _SUCCESS; ++ goto exit; ++ } ++ ++ if(rf_off == pwrpriv->rf_pwrstate ) ++ { ++#ifdef CONFIG_USB_HCI ++#ifdef CONFIG_AUTOSUSPEND ++ if(pwrpriv->brfoffbyhw==_TRUE) ++ { ++ DBG_8192C("hw still in rf_off state ...........\n"); ++ ret = _FAIL; ++ goto exit; ++ } ++ else if(padapter->registrypriv.usbss_enable) ++ { ++ DBG_8192C("\n %s call autoresume_enter....\n",__FUNCTION__); ++ if(_FAIL == autoresume_enter(padapter)) ++ { ++ DBG_8192C("======> autoresume fail.............\n"); ++ ret = _FAIL; ++ goto exit; ++ } ++ } ++ else ++#endif ++#endif ++ { ++#ifdef CONFIG_IPS ++ DBG_8192C("\n %s call ips_leave....\n",__FUNCTION__); ++ if(_FAIL == ips_leave(padapter)) ++ { ++ DBG_8192C("======> ips_leave fail.............\n"); ++ ret = _FAIL; ++ goto exit; ++ } ++#endif ++ } ++ }else { ++ //Jeff: reset timer to avoid falling ips or selective suspend soon ++ if(pwrpriv->bips_processing == _FALSE) ++ rtw_set_pwr_state_check_timer(pwrpriv); ++ } ++ ++exit: ++ return ret; ++ ++} ++ ++static int rtw_wx_set_scan(struct net_device *dev, struct iw_request_info *a, ++ union iwreq_data *wrqu, char *extra) ++{ ++ u8 _status = _FALSE; ++ int ret = 0; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct mlme_priv *pmlmepriv= &padapter->mlmepriv; ++ NDIS_802_11_SSID ssid[RTW_SSID_SCAN_AMOUNT]; ++ _irqL irqL; ++ ++#ifdef CONFIG_P2P ++ struct wifidirect_info *pwdinfo= &(padapter->wdinfo); ++#endif //CONFIG_P2P ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_info_,("rtw_wx_set_scan\n")); ++ ++_func_enter_; ++ ++ #ifdef DBG_IOCTL ++ DBG_871X("DBG_IOCTL %s:%d\n",__FUNCTION__, __LINE__); ++ #endif ++ ++#ifdef CONFIG_MP_INCLUDED ++ if (check_fwstate(pmlmepriv, WIFI_MP_STATE) == _TRUE) ++ { ++ ret = -1; ++ goto exit; ++ } ++#endif ++ ++ if(_FAIL == rfpwrstate_check(padapter)) ++ { ++ ret= -1; ++ goto exit; ++ } ++ ++ if(padapter->bDriverStopped){ ++ DBG_8192C("bDriverStopped=%d\n", padapter->bDriverStopped); ++ ret= -1; ++ goto exit; ++ } ++ ++ if(!padapter->bup){ ++ ret = -1; ++ goto exit; ++ } ++ ++ if (padapter->hw_init_completed==_FALSE){ ++ ret = -1; ++ goto exit; ++ } ++ ++ // When Busy Traffic, driver do not site survey. So driver return success. ++ // wpa_supplicant will not issue SIOCSIWSCAN cmd again after scan timeout. ++ // modify by thomas 2011-02-22. ++ if (pmlmepriv->LinkDetectInfo.bBusyTraffic == _TRUE) ++ { ++ indicate_wx_scan_complete_event(padapter); ++ goto exit; ++ } ++ ++ if (check_fwstate(pmlmepriv, _FW_UNDER_SURVEY|_FW_UNDER_LINKING) == _TRUE) ++ { ++ indicate_wx_scan_complete_event(padapter); ++ goto exit; ++ } ++ ++// Mareded by Albert 20101103 ++// For the DMP WiFi Display project, the driver won't to scan because ++// the pmlmepriv->scan_interval is always equal to 3. ++// So, the wpa_supplicant won't find out the WPS SoftAP. ++ ++/* ++ if(pmlmepriv->scan_interval>10) ++ pmlmepriv->scan_interval = 0; ++ ++ if(pmlmepriv->scan_interval > 0) ++ { ++ DBG_8192C("scan done\n"); ++ ret = 0; ++ goto exit; ++ } ++ ++*/ ++#ifdef CONFIG_P2P ++ if(!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE) && !rtw_p2p_chk_state(pwdinfo, P2P_STATE_IDLE)) ++ { ++ rtw_p2p_set_state(pwdinfo, P2P_STATE_FIND_PHASE_SEARCH); ++ pwdinfo->find_phase_state_exchange_cnt = 0; ++ rtw_free_network_queue(padapter, _TRUE); ++ } ++#endif //CONFIG_P2P ++ ++ _rtw_memset(ssid, 0, sizeof(NDIS_802_11_SSID)*RTW_SSID_SCAN_AMOUNT); ++ ++#if WIRELESS_EXT >= 17 ++ if (wrqu->data.length == sizeof(struct iw_scan_req)) ++ { ++ struct iw_scan_req *req = (struct iw_scan_req *)extra; ++ ++ if (wrqu->data.flags & IW_SCAN_THIS_ESSID) ++ { ++ int len = min((int)req->essid_len, IW_ESSID_MAX_SIZE); ++ ++ _rtw_memcpy(ssid[0].Ssid, req->essid, len); ++ ssid[0].SsidLength = len; ++ ++ DBG_8192C("IW_SCAN_THIS_ESSID, ssid=%s, len=%d\n", req->essid, req->essid_len); ++ ++ _enter_critical_bh(&pmlmepriv->lock, &irqL); ++ ++ _status = rtw_sitesurvey_cmd(padapter, ssid, 1); ++ ++ _exit_critical_bh(&pmlmepriv->lock, &irqL); ++ ++ } ++ else if (req->scan_type == IW_SCAN_TYPE_PASSIVE) ++ { ++ DBG_8192C("rtw_wx_set_scan, req->scan_type == IW_SCAN_TYPE_PASSIVE\n"); ++ } ++ ++ } ++ else ++#endif ++ ++ if( wrqu->data.length >= WEXT_CSCAN_HEADER_SIZE ++ && _rtw_memcmp(extra, WEXT_CSCAN_HEADER, WEXT_CSCAN_HEADER_SIZE) == _TRUE ++ ) ++ { ++ int len = wrqu->data.length -WEXT_CSCAN_HEADER_SIZE; ++ char *pos = extra+WEXT_CSCAN_HEADER_SIZE; ++ char section; ++ char sec_len; ++ int ssid_index = 0; ++ ++ //DBG_871X("%s COMBO_SCAN header is recognized\n", __FUNCTION__); ++ ++ while(len >= 1) { ++ section = *(pos++); len-=1; ++ ++ switch(section) { ++ case WEXT_CSCAN_SSID_SECTION: ++ //DBG_871X("WEXT_CSCAN_SSID_SECTION\n"); ++ if(len < 1) { ++ len = 0; ++ break; ++ } ++ ++ sec_len = *(pos++); len-=1; ++ ++ if(sec_len>0 && sec_len<=len) { ++ ssid[ssid_index].SsidLength = sec_len; ++ _rtw_memcpy(ssid[ssid_index].Ssid, pos, ssid[ssid_index].SsidLength); ++ //DBG_871X("%s COMBO_SCAN with specific ssid:%s, %d\n", __FUNCTION__ ++ // , ssid[ssid_index].Ssid, ssid[ssid_index].SsidLength); ++ ssid_index++; ++ } ++ ++ pos+=sec_len; len-=sec_len; ++ break; ++ ++ ++ case WEXT_CSCAN_CHANNEL_SECTION: ++ //DBG_871X("WEXT_CSCAN_CHANNEL_SECTION\n"); ++ pos+=1; len-=1; ++ break; ++ case WEXT_CSCAN_ACTV_DWELL_SECTION: ++ //DBG_871X("WEXT_CSCAN_ACTV_DWELL_SECTION\n"); ++ pos+=2; len-=2; ++ break; ++ case WEXT_CSCAN_PASV_DWELL_SECTION: ++ //DBG_871X("WEXT_CSCAN_PASV_DWELL_SECTION\n"); ++ pos+=2; len-=2; ++ break; ++ case WEXT_CSCAN_HOME_DWELL_SECTION: ++ //DBG_871X("WEXT_CSCAN_HOME_DWELL_SECTION\n"); ++ pos+=2; len-=2; ++ break; ++ case WEXT_CSCAN_TYPE_SECTION: ++ //DBG_871X("WEXT_CSCAN_TYPE_SECTION\n"); ++ pos+=1; len-=1; ++ break; ++ #if 0 ++ case WEXT_CSCAN_NPROBE_SECTION: ++ DBG_871X("WEXT_CSCAN_NPROBE_SECTION\n"); ++ break; ++ #endif ++ ++ default: ++ //DBG_871X("Unknown CSCAN section %c\n", section); ++ len = 0; // stop parsing ++ } ++ //DBG_871X("len:%d\n", len); ++ ++ } ++ ++ //jeff: it has still some scan paramater to parse, we only do this now... ++ _enter_critical_bh(&pmlmepriv->lock, &irqL); ++ _status = rtw_sitesurvey_cmd(padapter, ssid, RTW_SSID_SCAN_AMOUNT); ++ _exit_critical_bh(&pmlmepriv->lock, &irqL); ++ ++ } else ++ ++ { ++ _status = rtw_set_802_11_bssid_list_scan(padapter); ++ } ++ ++ if(_status == _FALSE) ++ ret = -1; ++ ++exit: ++ #ifdef DBG_IOCTL ++ DBG_871X("DBG_IOCTL %s:%d return %d\n",__FUNCTION__, __LINE__, ret); ++ #endif ++ ++_func_exit_; ++ ++ return ret; ++} ++ ++static int rtw_wx_get_scan(struct net_device *dev, struct iw_request_info *a, ++ union iwreq_data *wrqu, char *extra) ++{ ++ _irqL irqL; ++ _list *plist, *phead; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ _queue *queue = &(pmlmepriv->scanned_queue); ++ struct wlan_network *pnetwork = NULL; ++ char *ev = extra; ++ char *stop = ev + wrqu->data.length; ++ u32 ret = 0; ++ u32 cnt=0; ++ u32 wait_for_surveydone; ++ sint wait_status; ++#ifdef CONFIG_P2P ++ struct wifidirect_info* pwdinfo = &padapter->wdinfo; ++#endif //CONFIG_P2P ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_info_,("rtw_wx_get_scan\n")); ++ RT_TRACE(_module_rtl871x_ioctl_os_c,_drv_info_, (" Start of Query SIOCGIWSCAN .\n")); ++ ++ _func_enter_; ++ ++ #ifdef DBG_IOCTL ++ DBG_871X("DBG_IOCTL %s:%d\n",__FUNCTION__, __LINE__); ++ #endif ++ ++ if(padapter->pwrctrlpriv.brfoffbyhw && padapter->bDriverStopped) ++ { ++ ret = -EINVAL; ++ goto exit; ++ } ++ ++#ifdef CONFIG_P2P ++ if(!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) ++ { ++ // P2P is enabled ++ wait_for_surveydone = 200; ++ } ++ else ++ { ++ // P2P is disabled ++ wait_for_surveydone = 100; ++ } ++#else ++ { ++ wait_for_surveydone = 100; ++ } ++#endif //CONFIG_P2P ++ ++ wait_status = _FW_UNDER_SURVEY ++ #ifndef CONFIG_ANDROID ++ |_FW_UNDER_LINKING ++ #endif ++ ; ++ ++ while(check_fwstate(pmlmepriv, wait_status) == _TRUE) ++ { ++ rtw_msleep_os(30); ++ cnt++; ++ if(cnt > wait_for_surveydone ) ++ break; ++ } ++ ++ _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); ++ ++ phead = get_list_head(queue); ++ plist = get_next(phead); ++ ++ while(1) ++ { ++ if (rtw_end_of_queue_search(phead,plist)== _TRUE) ++ break; ++ ++ if((stop - ev) < SCAN_ITEM_SIZE) { ++ ret = -E2BIG; ++ break; ++ } ++ ++ pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list); ++ ++ //report network only if the current channel set contains the channel to which this network belongs ++ if( _TRUE == rtw_is_channel_set_contains_channel(padapter->mlmeextpriv.channel_set, pnetwork->network.Configuration.DSConfig) ++ #ifdef CONFIG_VALIDATE_SSID ++ && _TRUE == rtw_validate_ssid(&(pnetwork->network.Ssid)) ++ #endif ++ ) ++ { ++ ev=translate_scan(padapter, a, pnetwork, ev, stop); ++ } ++ ++ plist = get_next(plist); ++ ++ } ++ ++ _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); ++ ++ wrqu->data.length = ev-extra; ++ wrqu->data.flags = 0; ++ ++exit: ++ ++ _func_exit_; ++ ++ #ifdef DBG_IOCTL ++ DBG_871X("DBG_IOCTL %s:%d return %d\n",__FUNCTION__, __LINE__, ret); ++ #endif ++ ++ return ret ; ++ ++} ++ ++//set ssid flow ++//s1. rtw_set_802_11_infrastructure_mode() ++//s2. set_802_11_authenticaion_mode() ++//s3. set_802_11_encryption_mode() ++//s4. rtw_set_802_11_ssid() ++static int rtw_wx_set_essid(struct net_device *dev, ++ struct iw_request_info *a, ++ union iwreq_data *wrqu, char *extra) ++{ ++ _irqL irqL; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ _queue *queue = &pmlmepriv->scanned_queue; ++ struct pwrctrl_priv *pwrpriv = &padapter->pwrctrlpriv; ++ _list *phead; ++ s8 status = _TRUE; ++ struct wlan_network *pnetwork = NULL; ++ ++ NDIS_802_11_AUTHENTICATION_MODE authmode; ++ NDIS_802_11_SSID ndis_ssid; ++ u8 *dst_ssid, *src_ssid; ++ ++ uint ret = 0, len; ++ ++ _func_enter_; ++ ++ #ifdef DBG_IOCTL ++ DBG_871X("DBG_IOCTL %s:%d\n",__FUNCTION__, __LINE__); ++ #endif ++ ++ RT_TRACE(_module_rtl871x_ioctl_os_c, _drv_info_, ++ ("+rtw_wx_set_essid: fw_state=0x%08x\n", get_fwstate(pmlmepriv))); ++ if(_FAIL == rfpwrstate_check(padapter)) ++ { ++ ret = -1; ++ goto exit; ++ } ++ ++ if(!padapter->bup){ ++ ret = -1; ++ goto exit; ++ } ++ ++#if WIRELESS_EXT <= 20 ++ if ((wrqu->essid.length-1) > IW_ESSID_MAX_SIZE){ ++#else ++ if (wrqu->essid.length > IW_ESSID_MAX_SIZE){ ++#endif ++ ret= -E2BIG; ++ goto exit; ++ } ++ ++ if(check_fwstate(pmlmepriv, WIFI_AP_STATE)) { ++ ret = -1; ++ goto exit; ++ } ++ ++ authmode = padapter->securitypriv.ndisauthtype; ++ DBG_8192C("=>%s\n",__FUNCTION__); ++ if (wrqu->essid.flags && wrqu->essid.length) ++ { ++ // Commented by Albert 20100519 ++ // We got the codes in "set_info" function of iwconfig source code. ++ // ========================================= ++ // wrq.u.essid.length = strlen(essid) + 1; ++ // if(we_kernel_version > 20) ++ // wrq.u.essid.length--; ++ // ========================================= ++ // That means, if the WIRELESS_EXT less than or equal to 20, the correct ssid len should subtract 1. ++#if WIRELESS_EXT <= 20 ++ len = ((wrqu->essid.length-1) < IW_ESSID_MAX_SIZE) ? (wrqu->essid.length-1) : IW_ESSID_MAX_SIZE; ++#else ++ len = (wrqu->essid.length < IW_ESSID_MAX_SIZE) ? wrqu->essid.length : IW_ESSID_MAX_SIZE; ++#endif ++ ++ DBG_8192C("ssid=%s, len=%d\n", extra, wrqu->essid.length); ++ ++ _rtw_memset(&ndis_ssid, 0, sizeof(NDIS_802_11_SSID)); ++ ndis_ssid.SsidLength = len; ++ _rtw_memcpy(ndis_ssid.Ssid, extra, len); ++ src_ssid = ndis_ssid.Ssid; ++ ++ RT_TRACE(_module_rtl871x_ioctl_os_c, _drv_info_, ("rtw_wx_set_essid: ssid=[%s]\n", src_ssid)); ++ _enter_critical_bh(&queue->lock, &irqL); ++ phead = get_list_head(queue); ++ pmlmepriv->pscanned = get_next(phead); ++ ++ while (1) ++ { ++ if (rtw_end_of_queue_search(phead, pmlmepriv->pscanned) == _TRUE) ++ { ++#if 0 ++ if(check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE) ++ { ++ rtw_set_802_11_ssid(padapter, &ndis_ssid); ++ ++ goto exit; ++ } ++ else ++ { ++ RT_TRACE(_module_rtl871x_ioctl_os_c,_drv_info_,("rtw_wx_set_ssid(): scanned_queue is empty\n")); ++ ret = -EINVAL; ++ goto exit; ++ } ++#endif ++ RT_TRACE(_module_rtl871x_ioctl_os_c, _drv_warning_, ++ ("rtw_wx_set_essid: scan_q is empty, set ssid to check if scanning again!\n")); ++ ++ break; ++ } ++ ++ pnetwork = LIST_CONTAINOR(pmlmepriv->pscanned, struct wlan_network, list); ++ ++ pmlmepriv->pscanned = get_next(pmlmepriv->pscanned); ++ ++ dst_ssid = pnetwork->network.Ssid.Ssid; ++ ++ RT_TRACE(_module_rtl871x_ioctl_os_c, _drv_info_, ++ ("rtw_wx_set_essid: dst_ssid=%s\n", ++ pnetwork->network.Ssid.Ssid)); ++ ++ if ((_rtw_memcmp(dst_ssid, src_ssid, ndis_ssid.SsidLength) == _TRUE) && ++ (pnetwork->network.Ssid.SsidLength==ndis_ssid.SsidLength)) ++ { ++ RT_TRACE(_module_rtl871x_ioctl_os_c, _drv_info_, ++ ("rtw_wx_set_essid: find match, set infra mode\n")); ++ ++ if(check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE) ++ { ++ if(pnetwork->network.InfrastructureMode != pmlmepriv->cur_network.network.InfrastructureMode) ++ continue; ++ } ++ ++ if (rtw_set_802_11_infrastructure_mode(padapter, pnetwork->network.InfrastructureMode) == _FALSE) ++ { ++ ret = -1; ++ _exit_critical_bh(&queue->lock, &irqL); ++ goto exit; ++ } ++ ++ break; ++ } ++ } ++ _exit_critical_bh(&queue->lock, &irqL); ++ RT_TRACE(_module_rtl871x_ioctl_os_c, _drv_info_, ++ ("set ssid: set_802_11_auth. mode=%d\n", authmode)); ++ rtw_set_802_11_authentication_mode(padapter, authmode); ++ //set_802_11_encryption_mode(padapter, padapter->securitypriv.ndisencryptstatus); ++ if (rtw_set_802_11_ssid(padapter, &ndis_ssid) == _FALSE) { ++ ret = -1; ++ goto exit; ++ } ++ } ++ ++exit: ++ ++ DBG_8192C("<=%s, ret %d\n",__FUNCTION__, ret); ++ ++ #ifdef DBG_IOCTL ++ DBG_871X("DBG_IOCTL %s:%d return %d\n",__FUNCTION__, __LINE__, ret); ++ #endif ++ ++ _func_exit_; ++ ++ return ret; ++} ++ ++static int rtw_wx_get_essid(struct net_device *dev, ++ struct iw_request_info *a, ++ union iwreq_data *wrqu, char *extra) ++{ ++ u32 len,ret = 0; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ WLAN_BSSID_EX *pcur_bss = &pmlmepriv->cur_network.network; ++ ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_info_,("rtw_wx_get_essid\n")); ++ ++ _func_enter_; ++ ++ if ( (check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) || ++ (check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE)) ++ { ++ len = pcur_bss->Ssid.SsidLength; ++ ++ wrqu->essid.length = len; ++ ++ _rtw_memcpy(extra, pcur_bss->Ssid.Ssid, len); ++ ++ wrqu->essid.flags = 1; ++ } ++ else ++ { ++ ret = -1; ++ goto exit; ++ } ++ ++exit: ++ ++ _func_exit_; ++ ++ return ret; ++ ++} ++ ++static int rtw_wx_set_rate(struct net_device *dev, ++ struct iw_request_info *a, ++ union iwreq_data *wrqu, char *extra) ++{ ++ int i, ret = 0; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ u8 datarates[NumRates]; ++ u32 target_rate = wrqu->bitrate.value; ++ u32 fixed = wrqu->bitrate.fixed; ++ u32 ratevalue = 0; ++ u8 mpdatarate[NumRates]={11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0, 0xff}; ++ ++_func_enter_; ++ ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_info_,(" rtw_wx_set_rate \n")); ++ RT_TRACE(_module_rtl871x_ioctl_os_c,_drv_info_,("target_rate = %d, fixed = %d\n",target_rate,fixed)); ++ ++ if(target_rate == -1){ ++ ratevalue = 11; ++ goto set_rate; ++ } ++ target_rate = target_rate/100000; ++ ++ switch(target_rate){ ++ case 10: ++ ratevalue = 0; ++ break; ++ case 20: ++ ratevalue = 1; ++ break; ++ case 55: ++ ratevalue = 2; ++ break; ++ case 60: ++ ratevalue = 3; ++ break; ++ case 90: ++ ratevalue = 4; ++ break; ++ case 110: ++ ratevalue = 5; ++ break; ++ case 120: ++ ratevalue = 6; ++ break; ++ case 180: ++ ratevalue = 7; ++ break; ++ case 240: ++ ratevalue = 8; ++ break; ++ case 360: ++ ratevalue = 9; ++ break; ++ case 480: ++ ratevalue = 10; ++ break; ++ case 540: ++ ratevalue = 11; ++ break; ++ default: ++ ratevalue = 11; ++ break; ++ } ++ ++set_rate: ++ ++ for(i=0; imlmepriv; ++ WLAN_BSSID_EX *pcur_bss = &pmlmepriv->cur_network.network; ++ struct rtw_ieee80211_ht_cap *pht_capie; ++ u8 bw_40MHz=0, short_GI=0; ++ u16 mcs_rate=0; ++ u8 rf_type = 0; ++ struct registry_priv *pregpriv = &padapter->registrypriv; ++ ++ ++ i=0; ++#ifdef CONFIG_MP_INCLUDED ++ if (check_fwstate(pmlmepriv, WIFI_MP_STATE) == _TRUE) ++ return -1; ++#endif ++ if((check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) || (check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE)) ++ { ++ p = rtw_get_ie(&pcur_bss->IEs[12], _HT_CAPABILITY_IE_, &ht_ielen, pcur_bss->IELength-12); ++ if(p && ht_ielen>0) ++ { ++ ht_cap = _TRUE; ++ ++ pht_capie = (struct rtw_ieee80211_ht_cap *)(p+2); ++ ++ _rtw_memcpy(&mcs_rate , pht_capie->supp_mcs_set, 2); ++ ++ bw_40MHz = (pht_capie->cap_info&IEEE80211_HT_CAP_SUP_WIDTH) ? 1:0; ++ ++ short_GI = (pht_capie->cap_info&(IEEE80211_HT_CAP_SGI_20|IEEE80211_HT_CAP_SGI_40)) ? 1:0; ++ } ++ ++ while( (pcur_bss->SupportedRates[i]!=0) && (pcur_bss->SupportedRates[i]!=0xFF)) ++ { ++ rate = pcur_bss->SupportedRates[i]&0x7F; ++ if(rate>max_rate) ++ max_rate = rate; ++ ++ wrqu->bitrate.fixed = 0; /* no auto select */ ++ //wrqu->bitrate.disabled = 1/; ++ ++ i++; ++ } ++ ++ if(ht_cap == _TRUE) ++ { ++#if 0 //have some issue,neet to debug - 20101008-georgia ++ if(mcs_rate&0x8000)//MCS15 ++ { ++ max_rate = (bw_40MHz) ? ((short_GI)?300:270):((short_GI)?144:130); ++ ++ } ++ else if(mcs_rate&0x0080)//MCS7 ++ { ++ max_rate = (bw_40MHz) ? ((short_GI)?150:135):((short_GI)?72:65); ++ } ++ else//default MCS7 ++ { ++ //DBG_8192C("wx_get_rate, mcs_rate_bitmap=0x%x\n", mcs_rate); ++ max_rate = (bw_40MHz) ? ((short_GI)?150:135):((short_GI)?72:65); ++ } ++#else ++ padapter->HalFunc.GetHwRegHandler(padapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type)); ++ if(rf_type == RF_1T1R) ++ max_rate = (bw_40MHz) ? ((short_GI)?150:135):((short_GI)?72:65); ++ else ++ max_rate = (bw_40MHz) ? ((short_GI)?300:270):((short_GI)?144:130); ++#endif ++ max_rate = max_rate*2;//Mbps/2 ++ wrqu->bitrate.value = max_rate*500000; ++ ++ } ++ else ++ { ++ wrqu->bitrate.value = max_rate*500000; ++ } ++ ++ } ++ else ++ { ++ return -1; ++ } ++ ++ return 0; ++ ++} ++ ++static int rtw_wx_get_rts(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ ++ _func_enter_; ++ RT_TRACE(_module_rtl871x_mlme_c_,_drv_info_,(" rtw_wx_get_rts \n")); ++ ++ wrqu->rts.value = padapter->registrypriv.rts_thresh; ++ wrqu->rts.fixed = 0; /* no auto select */ ++ //wrqu->rts.disabled = (wrqu->rts.value == DEFAULT_RTS_THRESHOLD); ++ ++ _func_exit_; ++ ++ return 0; ++} ++ ++static int rtw_wx_set_frag(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ ++ _func_enter_; ++ ++ if (wrqu->frag.disabled) ++ padapter->xmitpriv.frag_len = MAX_FRAG_THRESHOLD; ++ else { ++ if (wrqu->frag.value < MIN_FRAG_THRESHOLD || ++ wrqu->frag.value > MAX_FRAG_THRESHOLD) ++ return -EINVAL; ++ ++ padapter->xmitpriv.frag_len = wrqu->frag.value & ~0x1; ++ } ++ ++ _func_exit_; ++ ++ return 0; ++ ++} ++ ++ ++static int rtw_wx_get_frag(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ ++ _func_enter_; ++ ++ wrqu->frag.value = padapter->xmitpriv.frag_len; ++ wrqu->frag.fixed = 0; /* no auto select */ ++ //wrqu->frag.disabled = (wrqu->frag.value == DEFAULT_FRAG_THRESHOLD); ++ ++ _func_exit_; ++ ++ return 0; ++} ++ ++static int rtw_wx_get_retry(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ //_adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ ++ ++ wrqu->retry.value = 7; ++ wrqu->retry.fixed = 0; /* no auto select */ ++ wrqu->retry.disabled = 1; ++ ++ return 0; ++ ++} ++ ++#if 0 ++#define IW_ENCODE_INDEX 0x00FF /* Token index (if needed) */ ++#define IW_ENCODE_FLAGS 0xFF00 /* Flags defined below */ ++#define IW_ENCODE_MODE 0xF000 /* Modes defined below */ ++#define IW_ENCODE_DISABLED 0x8000 /* Encoding disabled */ ++#define IW_ENCODE_ENABLED 0x0000 /* Encoding enabled */ ++#define IW_ENCODE_RESTRICTED 0x4000 /* Refuse non-encoded packets */ ++#define IW_ENCODE_OPEN 0x2000 /* Accept non-encoded packets */ ++#define IW_ENCODE_NOKEY 0x0800 /* Key is write only, so not present */ ++#define IW_ENCODE_TEMP 0x0400 /* Temporary key */ ++/* ++iwconfig wlan0 key on -> flags = 0x6001 -> maybe it means auto ++iwconfig wlan0 key off -> flags = 0x8800 ++iwconfig wlan0 key open -> flags = 0x2800 ++iwconfig wlan0 key open 1234567890 -> flags = 0x2000 ++iwconfig wlan0 key restricted -> flags = 0x4800 ++iwconfig wlan0 key open [3] 1234567890 -> flags = 0x2003 ++iwconfig wlan0 key restricted [2] 1234567890 -> flags = 0x4002 ++iwconfig wlan0 key open [3] -> flags = 0x2803 ++iwconfig wlan0 key restricted [2] -> flags = 0x4802 ++*/ ++#endif ++ ++static int rtw_wx_set_enc(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *keybuf) ++{ ++ u32 key, ret = 0; ++ u32 keyindex_provided; ++ NDIS_802_11_WEP wep; ++ NDIS_802_11_AUTHENTICATION_MODE authmode; ++ ++ struct iw_point *erq = &(wrqu->encoding); ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct pwrctrl_priv *pwrpriv = &padapter->pwrctrlpriv; ++ DBG_8192C("+rtw_wx_set_enc, flags=0x%x\n", erq->flags); ++ ++ _rtw_memset(&wep, 0, sizeof(NDIS_802_11_WEP)); ++ ++ key = erq->flags & IW_ENCODE_INDEX; ++ ++ _func_enter_; ++ ++ if (erq->flags & IW_ENCODE_DISABLED) ++ { ++ DBG_8192C("EncryptionDisabled\n"); ++ padapter->securitypriv.ndisencryptstatus = Ndis802_11EncryptionDisabled; ++ padapter->securitypriv.dot11PrivacyAlgrthm=_NO_PRIVACY_; ++ padapter->securitypriv.dot118021XGrpPrivacy=_NO_PRIVACY_; ++ padapter->securitypriv.dot11AuthAlgrthm= dot11AuthAlgrthm_Open; //open system ++ authmode = Ndis802_11AuthModeOpen; ++ padapter->securitypriv.ndisauthtype=authmode; ++ ++ goto exit; ++ } ++ ++ if (key) { ++ if (key > WEP_KEYS) ++ return -EINVAL; ++ key--; ++ keyindex_provided = 1; ++ } ++ else ++ { ++ keyindex_provided = 0; ++ key = padapter->securitypriv.dot11PrivacyKeyIndex; ++ DBG_8192C("rtw_wx_set_enc, key=%d\n", key); ++ } ++ ++ //set authentication mode ++ if(erq->flags & IW_ENCODE_OPEN) ++ { ++ DBG_8192C("rtw_wx_set_enc():IW_ENCODE_OPEN\n"); ++ padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption1Enabled;//Ndis802_11EncryptionDisabled; ++ ++#ifdef CONFIG_PLATFORM_MT53XX ++ padapter->securitypriv.dot11AuthAlgrthm = dot11AuthAlgrthm_Auto; ++#else ++ padapter->securitypriv.dot11AuthAlgrthm= dot11AuthAlgrthm_Open; ++#endif ++ ++ padapter->securitypriv.dot11PrivacyAlgrthm=_NO_PRIVACY_; ++ padapter->securitypriv.dot118021XGrpPrivacy=_NO_PRIVACY_; ++ authmode = Ndis802_11AuthModeOpen; ++ padapter->securitypriv.ndisauthtype=authmode; ++ } ++ else if(erq->flags & IW_ENCODE_RESTRICTED) ++ { ++ DBG_8192C("rtw_wx_set_enc():IW_ENCODE_RESTRICTED\n"); ++ padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption1Enabled; ++ ++#ifdef CONFIG_PLATFORM_MT53XX ++ padapter->securitypriv.dot11AuthAlgrthm = dot11AuthAlgrthm_Auto; ++#else ++ padapter->securitypriv.dot11AuthAlgrthm= dot11AuthAlgrthm_Shared; ++#endif ++ ++ padapter->securitypriv.dot11PrivacyAlgrthm=_WEP40_; ++ padapter->securitypriv.dot118021XGrpPrivacy=_WEP40_; ++ authmode = Ndis802_11AuthModeShared; ++ padapter->securitypriv.ndisauthtype=authmode; ++ } ++ else ++ { ++ DBG_8192C("rtw_wx_set_enc():erq->flags=0x%x\n", erq->flags); ++ ++ padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption1Enabled;//Ndis802_11EncryptionDisabled; ++ padapter->securitypriv.dot11AuthAlgrthm= dot11AuthAlgrthm_Open; //open system ++ padapter->securitypriv.dot11PrivacyAlgrthm=_NO_PRIVACY_; ++ padapter->securitypriv.dot118021XGrpPrivacy=_NO_PRIVACY_; ++ authmode = Ndis802_11AuthModeOpen; ++ padapter->securitypriv.ndisauthtype=authmode; ++ } ++ ++ wep.KeyIndex = key; ++ if (erq->length > 0) ++ { ++ wep.KeyLength = erq->length <= 5 ? 5 : 13; ++ ++ wep.Length = wep.KeyLength + FIELD_OFFSET(NDIS_802_11_WEP, KeyMaterial); ++ } ++ else ++ { ++ wep.KeyLength = 0 ; ++ ++ if(keyindex_provided == 1)// set key_id only, no given KeyMaterial(erq->length==0). ++ { ++ padapter->securitypriv.dot11PrivacyKeyIndex = key; ++ ++ DBG_8192C("(keyindex_provided == 1), keyid=%d, key_len=%d\n", key, padapter->securitypriv.dot11DefKeylen[key]); ++ ++ switch(padapter->securitypriv.dot11DefKeylen[key]) ++ { ++ case 5: ++ padapter->securitypriv.dot11PrivacyAlgrthm=_WEP40_; ++ break; ++ case 13: ++ padapter->securitypriv.dot11PrivacyAlgrthm=_WEP104_; ++ break; ++ default: ++ padapter->securitypriv.dot11PrivacyAlgrthm=_NO_PRIVACY_; ++ break; ++ } ++ ++ goto exit; ++ ++ } ++ ++ } ++ ++ wep.KeyIndex |= 0x80000000; ++ ++ _rtw_memcpy(wep.KeyMaterial, keybuf, wep.KeyLength); ++ ++ if (rtw_set_802_11_add_wep(padapter, &wep) == _FALSE) { ++ if(rf_on == pwrpriv->rf_pwrstate ) ++ ret = -EOPNOTSUPP; ++ goto exit; ++ } ++ ++exit: ++ ++ _func_exit_; ++ ++ return ret; ++ ++} ++ ++static int rtw_wx_get_enc(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *keybuf) ++{ ++ uint key, ret =0; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct iw_point *erq = &(wrqu->encoding); ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ ++ _func_enter_; ++ ++ if(check_fwstate(pmlmepriv, _FW_LINKED) != _TRUE) ++ { ++ if(check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) != _TRUE) ++ { ++ erq->length = 0; ++ erq->flags |= IW_ENCODE_DISABLED; ++ return 0; ++ } ++ } ++ ++ ++ key = erq->flags & IW_ENCODE_INDEX; ++ ++ if (key) { ++ if (key > WEP_KEYS) ++ return -EINVAL; ++ key--; ++ } else ++ { ++ key = padapter->securitypriv.dot11PrivacyKeyIndex; ++ } ++ ++ erq->flags = key + 1; ++ ++ //if(padapter->securitypriv.ndisauthtype == Ndis802_11AuthModeOpen) ++ //{ ++ // erq->flags |= IW_ENCODE_OPEN; ++ //} ++ ++ switch(padapter->securitypriv.ndisencryptstatus) ++ { ++ case Ndis802_11EncryptionNotSupported: ++ case Ndis802_11EncryptionDisabled: ++ ++ erq->length = 0; ++ erq->flags |= IW_ENCODE_DISABLED; ++ ++ break; ++ ++ case Ndis802_11Encryption1Enabled: ++ ++ erq->length = padapter->securitypriv.dot11DefKeylen[key]; ++ ++ if(erq->length) ++ { ++ _rtw_memcpy(keybuf, padapter->securitypriv.dot11DefKey[key].skey, padapter->securitypriv.dot11DefKeylen[key]); ++ ++ erq->flags |= IW_ENCODE_ENABLED; ++ ++ if(padapter->securitypriv.ndisauthtype == Ndis802_11AuthModeOpen) ++ { ++ erq->flags |= IW_ENCODE_OPEN; ++ } ++ else if(padapter->securitypriv.ndisauthtype == Ndis802_11AuthModeShared) ++ { ++ erq->flags |= IW_ENCODE_RESTRICTED; ++ } ++ } ++ else ++ { ++ erq->length = 0; ++ erq->flags |= IW_ENCODE_DISABLED; ++ } ++ ++ break; ++ ++ case Ndis802_11Encryption2Enabled: ++ case Ndis802_11Encryption3Enabled: ++ ++ erq->length = 16; ++ erq->flags |= (IW_ENCODE_ENABLED | IW_ENCODE_OPEN | IW_ENCODE_NOKEY); ++ ++ break; ++ ++ default: ++ erq->length = 0; ++ erq->flags |= IW_ENCODE_DISABLED; ++ ++ break; ++ ++ } ++ ++ _func_exit_; ++ ++ return ret; ++ ++} ++ ++static int rtw_wx_get_power(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ //_adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ ++ wrqu->power.value = 0; ++ wrqu->power.fixed = 0; /* no auto select */ ++ wrqu->power.disabled = 1; ++ ++ return 0; ++ ++} ++ ++static int rtw_wx_set_gen_ie(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ int ret; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ ++ ret = rtw_set_wpa_ie(padapter, extra, wrqu->data.length); ++ ++ return ret; ++} ++ ++static int rtw_wx_set_auth(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct iw_param *param = (struct iw_param*)&(wrqu->param); ++ int ret = 0; ++ ++ switch (param->flags & IW_AUTH_INDEX) { ++ case IW_AUTH_WPA_VERSION: ++ break; ++ case IW_AUTH_CIPHER_PAIRWISE: ++ ++ break; ++ case IW_AUTH_CIPHER_GROUP: ++ ++ break; ++ case IW_AUTH_KEY_MGMT: ++ /* ++ * ??? does not use these parameters ++ */ ++ break; ++ ++ case IW_AUTH_TKIP_COUNTERMEASURES: ++ { ++ if ( param->value ) ++ { // wpa_supplicant is enabling the tkip countermeasure. ++ padapter->securitypriv.btkip_countermeasure = _TRUE; ++ } ++ else ++ { // wpa_supplicant is disabling the tkip countermeasure. ++ padapter->securitypriv.btkip_countermeasure = _FALSE; ++ } ++ break; ++ } ++ case IW_AUTH_DROP_UNENCRYPTED: ++ { ++ /* HACK: ++ * ++ * wpa_supplicant calls set_wpa_enabled when the driver ++ * is loaded and unloaded, regardless of if WPA is being ++ * used. No other calls are made which can be used to ++ * determine if encryption will be used or not prior to ++ * association being expected. If encryption is not being ++ * used, drop_unencrypted is set to false, else true -- we ++ * can use this to determine if the CAP_PRIVACY_ON bit should ++ * be set. ++ */ ++ ++ if(padapter->securitypriv.ndisencryptstatus == Ndis802_11Encryption1Enabled) ++ { ++ break;//it means init value, or using wep, ndisencryptstatus = Ndis802_11Encryption1Enabled, ++ // then it needn't reset it; ++ } ++ ++ if(param->value){ ++ padapter->securitypriv.ndisencryptstatus = Ndis802_11EncryptionDisabled; ++ padapter->securitypriv.dot11PrivacyAlgrthm=_NO_PRIVACY_; ++ padapter->securitypriv.dot118021XGrpPrivacy=_NO_PRIVACY_; ++ padapter->securitypriv.dot11AuthAlgrthm= dot11AuthAlgrthm_Open; //open system ++ padapter->securitypriv.ndisauthtype=Ndis802_11AuthModeOpen; ++ } ++ ++ break; ++ } ++ ++ case IW_AUTH_80211_AUTH_ALG: ++ ++ #if defined(CONFIG_ANDROID) || 1 ++ /* ++ * It's the starting point of a link layer connection using wpa_supplicant ++ */ ++ if(check_fwstate(&padapter->mlmepriv, _FW_LINKED)) { ++ rtw_disassoc_cmd(padapter); ++ DBG_871X("%s...call rtw_indicate_disconnect\n ",__FUNCTION__); ++ rtw_indicate_disconnect(padapter); ++ rtw_free_assoc_resources(padapter, 1); ++ } ++ #endif ++ ++ ++ ret = wpa_set_auth_algs(dev, (u32)param->value); ++ ++ break; ++ ++ case IW_AUTH_WPA_ENABLED: ++ ++ //if(param->value) ++ // padapter->securitypriv.dot11AuthAlgrthm = dot11AuthAlgrthm_8021X; //802.1x ++ //else ++ // padapter->securitypriv.dot11AuthAlgrthm = dot11AuthAlgrthm_Open;//open system ++ ++ //_disassociate(priv); ++ ++ break; ++ ++ case IW_AUTH_RX_UNENCRYPTED_EAPOL: ++ //ieee->ieee802_1x = param->value; ++ break; ++ ++ case IW_AUTH_PRIVACY_INVOKED: ++ //ieee->privacy_invoked = param->value; ++ break; ++ ++ default: ++ return -EOPNOTSUPP; ++ ++ } ++ ++ return ret; ++ ++} ++ ++static int rtw_wx_set_enc_ext(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ char *alg_name; ++ u32 param_len; ++ struct ieee_param *param = NULL; ++ struct iw_point *pencoding = &wrqu->encoding; ++ struct iw_encode_ext *pext = (struct iw_encode_ext *)extra; ++ int ret=0; ++ ++ param_len = sizeof(struct ieee_param) + pext->key_len; ++ param = (struct ieee_param *)rtw_malloc(param_len); ++ if (param == NULL) ++ return -1; ++ ++ _rtw_memset(param, 0, param_len); ++ ++ param->cmd = IEEE_CMD_SET_ENCRYPTION; ++ _rtw_memset(param->sta_addr, 0xff, ETH_ALEN); ++ ++ ++ switch (pext->alg) { ++ case IW_ENCODE_ALG_NONE: ++ //todo: remove key ++ //remove = 1; ++ alg_name = "none"; ++ break; ++ case IW_ENCODE_ALG_WEP: ++ alg_name = "WEP"; ++ break; ++ case IW_ENCODE_ALG_TKIP: ++ alg_name = "TKIP"; ++ break; ++ case IW_ENCODE_ALG_CCMP: ++ alg_name = "CCMP"; ++ break; ++ default: ++ return -1; ++ } ++ ++ strncpy((char *)param->u.crypt.alg, alg_name, IEEE_CRYPT_ALG_NAME_LEN); ++ ++ ++ if(pext->ext_flags & IW_ENCODE_EXT_GROUP_KEY)//? ++ { ++ param->u.crypt.set_tx = 0; ++ } ++ ++ if (pext->ext_flags & IW_ENCODE_EXT_SET_TX_KEY)//? ++ { ++ param->u.crypt.set_tx = 1; ++ } ++ ++ param->u.crypt.idx = (pencoding->flags&0x00FF) -1 ; ++ ++ if (pext->ext_flags & IW_ENCODE_EXT_RX_SEQ_VALID) ++ { ++ _rtw_memcpy(param->u.crypt.seq, pext->rx_seq, 8); ++ } ++ ++ if(pext->key_len) ++ { ++ param->u.crypt.key_len = pext->key_len; ++ //_rtw_memcpy(param + 1, pext + 1, pext->key_len); ++ _rtw_memcpy(param->u.crypt.key, pext + 1, pext->key_len); ++ } ++ ++ ++ if (pencoding->flags & IW_ENCODE_DISABLED) ++ { ++ //todo: remove key ++ //remove = 1; ++ } ++ ++ ret = wpa_set_encryption(dev, param, param_len); ++ ++ ++ if(param) ++ { ++ rtw_mfree((u8*)param, param_len); ++ } ++ ++ ++ return ret; ++ ++} ++ ++ ++static int rtw_wx_get_nick(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ //_adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ //struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ //struct security_priv *psecuritypriv = &padapter->securitypriv; ++ ++ if(extra) ++ { ++ wrqu->data.length = 14; ++ wrqu->data.flags = 1; ++ _rtw_memcpy(extra, "", 14); ++ } ++ ++ //rtw_signal_process(pid, SIGUSR1); //for test ++ ++ //dump debug info here ++/* ++ u32 dot11AuthAlgrthm; // 802.11 auth, could be open, shared, and 8021x ++ u32 dot11PrivacyAlgrthm; // This specify the privacy for shared auth. algorithm. ++ u32 dot118021XGrpPrivacy; // This specify the privacy algthm. used for Grp key ++ u32 ndisauthtype; ++ u32 ndisencryptstatus; ++*/ ++ ++ //DBG_8192C("auth_alg=0x%x, enc_alg=0x%x, auth_type=0x%x, enc_type=0x%x\n", ++ // psecuritypriv->dot11AuthAlgrthm, psecuritypriv->dot11PrivacyAlgrthm, ++ // psecuritypriv->ndisauthtype, psecuritypriv->ndisencryptstatus); ++ ++ //DBG_8192C("enc_alg=0x%x\n", psecuritypriv->dot11PrivacyAlgrthm); ++ //DBG_8192C("auth_type=0x%x\n", psecuritypriv->ndisauthtype); ++ //DBG_8192C("enc_type=0x%x\n", psecuritypriv->ndisencryptstatus); ++ ++#if 0 ++ DBG_8192C("dbg(0x210)=0x%x\n", rtw_read32(padapter, 0x210)); ++ DBG_8192C("dbg(0x608)=0x%x\n", rtw_read32(padapter, 0x608)); ++ DBG_8192C("dbg(0x280)=0x%x\n", rtw_read32(padapter, 0x280)); ++ DBG_8192C("dbg(0x284)=0x%x\n", rtw_read32(padapter, 0x284)); ++ DBG_8192C("dbg(0x288)=0x%x\n", rtw_read32(padapter, 0x288)); ++ ++ DBG_8192C("dbg(0x664)=0x%x\n", rtw_read32(padapter, 0x664)); ++ ++ ++ DBG_8192C("\n"); ++ ++ DBG_8192C("dbg(0x430)=0x%x\n", rtw_read32(padapter, 0x430)); ++ DBG_8192C("dbg(0x438)=0x%x\n", rtw_read32(padapter, 0x438)); ++ ++ DBG_8192C("dbg(0x440)=0x%x\n", rtw_read32(padapter, 0x440)); ++ ++ DBG_8192C("dbg(0x458)=0x%x\n", rtw_read32(padapter, 0x458)); ++ ++ DBG_8192C("dbg(0x484)=0x%x\n", rtw_read32(padapter, 0x484)); ++ DBG_8192C("dbg(0x488)=0x%x\n", rtw_read32(padapter, 0x488)); ++ ++ DBG_8192C("dbg(0x444)=0x%x\n", rtw_read32(padapter, 0x444)); ++ DBG_8192C("dbg(0x448)=0x%x\n", rtw_read32(padapter, 0x448)); ++ DBG_8192C("dbg(0x44c)=0x%x\n", rtw_read32(padapter, 0x44c)); ++ DBG_8192C("dbg(0x450)=0x%x\n", rtw_read32(padapter, 0x450)); ++#endif ++ ++ return 0; ++ ++} ++ ++static int rtw_wx_read32(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ ++ u32 addr; ++ u32 data32; ++ ++ ++ addr = *(u32*)extra; ++ data32 = rtw_read32(padapter, addr); ++ sprintf(extra, "0x%08x", data32); ++ ++ return 0; ++} ++ ++static int rtw_wx_write32(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ ++ u32 addr; ++ u32 data32; ++ ++ ++ addr = *(u32*)extra; ++ data32 = *((u32*)extra + 1); ++ rtw_write32(padapter, addr, data32); ++ ++ return 0; ++} ++ ++static int rtw_wx_read_rf(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ u32 path, addr, data32; ++ ++ ++ path = *(u32*)extra; ++ addr = *((u32*)extra + 1); ++ data32 = padapter->HalFunc.read_rfreg(padapter, path, addr, 0xFFFFF); ++// DBG_8192C("%s: path=%d addr=0x%02x data=0x%05x\n", __func__, path, addr, data32); ++ /* ++ * IMPORTANT!! ++ * Only when wireless private ioctl is at odd order, ++ * "extra" would be copied to user space. ++ */ ++ sprintf(extra, "0x%05x", data32); ++ ++ return 0; ++} ++ ++static int rtw_wx_write_rf(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ u32 path, addr, data32; ++ ++ ++ path = *(u32*)extra; ++ addr = *((u32*)extra + 1); ++ data32 = *((u32*)extra + 2); ++// DBG_8192C("%s: path=%d addr=0x%02x data=0x%05x\n", __func__, path, addr, data32); ++ padapter->HalFunc.write_rfreg(padapter, path, addr, 0xFFFFF, data32); ++ ++ return 0; ++} ++ ++static int rtw_wx_priv_null(struct net_device *dev, struct iw_request_info *a, ++ union iwreq_data *wrqu, char *b) ++{ ++ return -1; ++} ++ ++static int dummy(struct net_device *dev, struct iw_request_info *a, ++ union iwreq_data *wrqu, char *b) ++{ ++ //_adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ //struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ ++ //DBG_8192C("cmd_code=%x, fwstate=0x%x\n", a->cmd, get_fwstate(pmlmepriv)); ++ ++ return -1; ++ ++} ++ ++static int rtw_wx_set_channel_plan(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct registry_priv *pregistrypriv = &padapter->registrypriv; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ extern int rtw_channel_plan; ++ u8 channel_plan_req = (u8) (*((int *)wrqu)); ++ ++ #if 0 ++ rtw_channel_plan = (int)wrqu->data.pointer; ++ pregistrypriv->channel_plan = rtw_channel_plan; ++ pmlmepriv->ChannelPlan = pregistrypriv->channel_plan; ++ #endif ++ ++ if( _SUCCESS == rtw_set_chplan_cmd(padapter, channel_plan_req, 1) ) { ++ DBG_871X("\n======== Set channel_plan = 0x%02X ========\n", pmlmepriv->ChannelPlan); ++ } else ++ return -EPERM; ++ ++ return 0; ++} ++ ++static int rtw_wx_set_mtk_wps_probe_ie(struct net_device *dev, ++ struct iw_request_info *a, ++ union iwreq_data *wrqu, char *b) ++{ ++#ifdef CONFIG_PLATFORM_MT53XX ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ ++ RT_TRACE(_module_rtl871x_ioctl_os_c, _drv_notice_, ++ ("WLAN IOCTL: cmd_code=%x, fwstate=0x%x\n", ++ a->cmd, get_fwstate(pmlmepriv))); ++#endif ++ return 0; ++} ++ ++static int rtw_wx_get_sensitivity(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *buf) ++{ ++#ifdef CONFIG_PLATFORM_MT53XX ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ ++ // Modified by Albert 20110914 ++ // This is in dbm format for MTK platform. ++ wrqu->qual.level = padapter->recvpriv.rssi; ++ DBG_8192C(" level = %u\n", wrqu->qual.level ); ++#endif ++ return 0; ++} ++ ++static int rtw_wx_set_mtk_wps_ie(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++#ifdef CONFIG_PLATFORM_MT53XX ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ ++ return rtw_set_wpa_ie(padapter, wrqu->data.pointer, wrqu->data.length); ++#else ++ return 0; ++#endif ++} ++ ++/* ++typedef int (*iw_handler)(struct net_device *dev, struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra); ++*/ ++/* ++ * For all data larger than 16 octets, we need to use a ++ * pointer to memory allocated in user space. ++ */ ++static int rtw_drvext_hdl(struct net_device *dev, struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ ++ #if 0 ++struct iw_point ++{ ++ void __user *pointer; /* Pointer to the data (in user space) */ ++ __u16 length; /* number of fields or size in bytes */ ++ __u16 flags; /* Optional params */ ++}; ++ #endif ++ ++#ifdef CONFIG_DRVEXT_MODULE ++ u8 res; ++ struct drvext_handler *phandler; ++ struct drvext_oidparam *poidparam; ++ int ret; ++ u16 len; ++ u8 *pparmbuf, bset; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct iw_point *p = &wrqu->data; ++ ++ if( (!p->length) || (!p->pointer)){ ++ ret = -EINVAL; ++ goto _rtw_drvext_hdl_exit; ++ } ++ ++ ++ bset = (u8)(p->flags&0xFFFF); ++ len = p->length; ++ pparmbuf = (u8*)rtw_malloc(len); ++ if (pparmbuf == NULL){ ++ ret = -ENOMEM; ++ goto _rtw_drvext_hdl_exit; ++ } ++ ++ if(bset)//set info ++ { ++ if (copy_from_user(pparmbuf, p->pointer,len)) { ++ rtw_mfree(pparmbuf, len); ++ ret = -EFAULT; ++ goto _rtw_drvext_hdl_exit; ++ } ++ } ++ else//query info ++ { ++ ++ } ++ ++ ++ // ++ poidparam = (struct drvext_oidparam *)pparmbuf; ++ ++ RT_TRACE(_module_rtl871x_ioctl_os_c,_drv_info_,("drvext set oid subcode [%d], len[%d], InformationBufferLength[%d]\r\n", ++ poidparam->subcode, poidparam->len, len)); ++ ++ ++ //check subcode ++ if ( poidparam->subcode >= MAX_DRVEXT_HANDLERS) ++ { ++ RT_TRACE(_module_rtl871x_ioctl_os_c,_drv_err_,("no matching drvext handlers\r\n")); ++ ret = -EINVAL; ++ goto _rtw_drvext_hdl_exit; ++ } ++ ++ ++ if ( poidparam->subcode >= MAX_DRVEXT_OID_SUBCODES) ++ { ++ RT_TRACE(_module_rtl871x_ioctl_os_c,_drv_err_,("no matching drvext subcodes\r\n")); ++ ret = -EINVAL; ++ goto _rtw_drvext_hdl_exit; ++ } ++ ++ ++ phandler = drvextoidhandlers + poidparam->subcode; ++ ++ if (poidparam->len != phandler->parmsize) ++ { ++ RT_TRACE(_module_rtl871x_ioctl_os_c,_drv_err_,("no matching drvext param size %d vs %d\r\n", ++ poidparam->len , phandler->parmsize)); ++ ret = -EINVAL; ++ goto _rtw_drvext_hdl_exit; ++ } ++ ++ ++ res = phandler->handler(&padapter->drvextpriv, bset, poidparam->data); ++ ++ if(res==0) ++ { ++ ret = 0; ++ ++ if (bset == 0x00) {//query info ++ //_rtw_memcpy(p->pointer, pparmbuf, len); ++ if (copy_to_user(p->pointer, pparmbuf, len)) ++ ret = -EFAULT; ++ } ++ } ++ else ++ ret = -EFAULT; ++ ++ ++_rtw_drvext_hdl_exit: ++ ++ return ret; ++ ++#endif ++ ++ return 0; ++ ++} ++ ++static void rtw_dbg_mode_hdl(_adapter *padapter, u32 id, u8 *pdata, u32 len) ++{ ++ pRW_Reg RegRWStruct; ++ struct rf_reg_param *prfreg; ++ u8 path; ++ u8 offset; ++ u32 value; ++ ++ DBG_8192C("%s\n", __FUNCTION__); ++ ++ switch(id) ++ { ++ case GEN_MP_IOCTL_SUBCODE(MP_START): ++ DBG_8192C("871x_driver is only for normal mode, can't enter mp mode\n"); ++ break; ++ case GEN_MP_IOCTL_SUBCODE(READ_REG): ++ RegRWStruct = (pRW_Reg)pdata; ++ switch (RegRWStruct->width) ++ { ++ case 1: ++ RegRWStruct->value = rtw_read8(padapter, RegRWStruct->offset); ++ break; ++ case 2: ++ RegRWStruct->value = rtw_read16(padapter, RegRWStruct->offset); ++ break; ++ case 4: ++ RegRWStruct->value = rtw_read32(padapter, RegRWStruct->offset); ++ break; ++ default: ++ break; ++ } ++ ++ break; ++ case GEN_MP_IOCTL_SUBCODE(WRITE_REG): ++ RegRWStruct = (pRW_Reg)pdata; ++ switch (RegRWStruct->width) ++ { ++ case 1: ++ rtw_write8(padapter, RegRWStruct->offset, (u8)RegRWStruct->value); ++ break; ++ case 2: ++ rtw_write16(padapter, RegRWStruct->offset, (u16)RegRWStruct->value); ++ break; ++ case 4: ++ rtw_write32(padapter, RegRWStruct->offset, (u32)RegRWStruct->value); ++ break; ++ default: ++ break; ++ } ++ ++ break; ++ case GEN_MP_IOCTL_SUBCODE(READ_RF_REG): ++ ++ prfreg = (struct rf_reg_param *)pdata; ++ ++ path = (u8)prfreg->path; ++ offset = (u8)prfreg->offset; ++ ++ value = padapter->HalFunc.read_rfreg(padapter, path, offset, 0xffffffff); ++ ++ prfreg->value = value; ++ ++ break; ++ case GEN_MP_IOCTL_SUBCODE(WRITE_RF_REG): ++ ++ prfreg = (struct rf_reg_param *)pdata; ++ ++ path = (u8)prfreg->path; ++ offset = (u8)prfreg->offset; ++ value = prfreg->value; ++ ++ padapter->HalFunc.write_rfreg(padapter, path, offset, 0xffffffff, value); ++ ++ break; ++ case GEN_MP_IOCTL_SUBCODE(TRIGGER_GPIO): ++ DBG_8192C("==> trigger gpio 0\n"); ++ padapter->HalFunc.SetHwRegHandler(padapter, HW_VAR_TRIGGER_GPIO_0, 0); ++ break; ++#ifdef CONFIG_BT_COEXIST ++ case GEN_MP_IOCTL_SUBCODE(SET_DM_BT): ++ DBG_8192C("==> set dm_bt_coexist:%x\n",*(u8 *)pdata); ++ padapter->HalFunc.SetHwRegHandler(padapter, HW_VAR_BT_SET_COEXIST, pdata); ++ break; ++ case GEN_MP_IOCTL_SUBCODE(DEL_BA): ++ DBG_8192C("==> delete ba:%x\n",*(u8 *)pdata); ++ padapter->HalFunc.SetHwRegHandler(padapter, HW_VAR_BT_ISSUE_DELBA, pdata); ++ break; ++#endif ++#ifdef DBG_CONFIG_ERROR_DETECT ++ case GEN_MP_IOCTL_SUBCODE(GET_WIFI_STATUS): ++ if(padapter->HalFunc.sreset_get_wifi_status) ++ *pdata = padapter->HalFunc.sreset_get_wifi_status(padapter); ++ break; ++#endif ++ ++ default: ++ break; ++ } ++ ++} ++ ++static int rtw_mp_ioctl_hdl(struct net_device *dev, struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ int ret = 0; ++ u32 BytesRead, BytesWritten, BytesNeeded; ++ struct oid_par_priv oid_par; ++ struct mp_ioctl_handler *phandler; ++ struct mp_ioctl_param *poidparam; ++ uint status=0; ++ u16 len; ++ u8 *pparmbuf = NULL, bset; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct iw_point *p = &wrqu->data; ++ ++ //DBG_8192C("+rtw_mp_ioctl_hdl\n"); ++ ++ //mutex_lock(&ioctl_mutex); ++ ++ if ((!p->length) || (!p->pointer)) { ++ ret = -EINVAL; ++ goto _rtw_mp_ioctl_hdl_exit; ++ } ++ ++ pparmbuf = NULL; ++ bset = (u8)(p->flags & 0xFFFF); ++ len = p->length; ++ pparmbuf = (u8*)rtw_malloc(len); ++ if (pparmbuf == NULL){ ++ ret = -ENOMEM; ++ goto _rtw_mp_ioctl_hdl_exit; ++ } ++ ++ if (copy_from_user(pparmbuf, p->pointer, len)) { ++ ret = -EFAULT; ++ goto _rtw_mp_ioctl_hdl_exit; ++ } ++ ++ poidparam = (struct mp_ioctl_param *)pparmbuf; ++ RT_TRACE(_module_rtl871x_ioctl_os_c, _drv_info_, ++ ("rtw_mp_ioctl_hdl: subcode [%d], len[%d], buffer_len[%d]\r\n", ++ poidparam->subcode, poidparam->len, len)); ++ ++ if (poidparam->subcode >= MAX_MP_IOCTL_SUBCODE) { ++ RT_TRACE(_module_rtl871x_ioctl_os_c, _drv_err_, ("no matching drvext subcodes\r\n")); ++ ret = -EINVAL; ++ goto _rtw_mp_ioctl_hdl_exit; ++ } ++ ++ //DBG_8192C("%s: %d\n", __func__, poidparam->subcode); ++ ++#ifdef CONFIG_MP_INCLUDED ++ phandler = mp_ioctl_hdl + poidparam->subcode; ++ ++ if ((phandler->paramsize != 0) && (poidparam->len < phandler->paramsize)) ++ { ++ RT_TRACE(_module_rtl871x_ioctl_os_c, _drv_err_, ++ ("no matching drvext param size %d vs %d\r\n", ++ poidparam->len, phandler->paramsize)); ++ ret = -EINVAL; ++ goto _rtw_mp_ioctl_hdl_exit; ++ } ++ ++ if (phandler->handler) ++ { ++ oid_par.adapter_context = padapter; ++ oid_par.oid = phandler->oid; ++ oid_par.information_buf = poidparam->data; ++ oid_par.information_buf_len = poidparam->len; ++ oid_par.dbg = 0; ++ ++ BytesWritten = 0; ++ BytesNeeded = 0; ++ ++ if (bset) { ++ oid_par.bytes_rw = &BytesRead; ++ oid_par.bytes_needed = &BytesNeeded; ++ oid_par.type_of_oid = SET_OID; ++ } else { ++ oid_par.bytes_rw = &BytesWritten; ++ oid_par.bytes_needed = &BytesNeeded; ++ oid_par.type_of_oid = QUERY_OID; ++ } ++ ++ status = phandler->handler(&oid_par); ++ ++ //todo:check status, BytesNeeded, etc. ++ } ++ else { ++ DBG_8192C("rtw_mp_ioctl_hdl(): err!, subcode=%d, oid=%d, handler=%p\n", ++ poidparam->subcode, phandler->oid, phandler->handler); ++ ret = -EFAULT; ++ goto _rtw_mp_ioctl_hdl_exit; ++ } ++#else ++ ++ rtw_dbg_mode_hdl(padapter, poidparam->subcode, poidparam->data, poidparam->len); ++ ++#endif ++ ++ if (bset == 0x00) {//query info ++ if (copy_to_user(p->pointer, pparmbuf, len)) ++ ret = -EFAULT; ++ } ++ ++ if (status) { ++ ret = -EFAULT; ++ goto _rtw_mp_ioctl_hdl_exit; ++ } ++ ++_rtw_mp_ioctl_hdl_exit: ++ ++ if (pparmbuf) ++ rtw_mfree(pparmbuf, len); ++ ++ //mutex_unlock(&ioctl_mutex); ++ ++ return ret; ++} ++ ++static int rtw_get_ap_info(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ int bssid_match, ret = 0; ++ u32 cnt=0, wpa_ielen; ++ _irqL irqL; ++ _list *plist, *phead; ++ unsigned char *pbuf; ++ u8 bssid[ETH_ALEN]; ++ char data[32]; ++ struct wlan_network *pnetwork = NULL; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ _queue *queue = &(pmlmepriv->scanned_queue); ++ struct iw_point *pdata = &wrqu->data; ++ ++ DBG_8192C("+rtw_get_aplist_info\n"); ++ ++ if((padapter->bDriverStopped) || (pdata==NULL)) ++ { ++ ret= -EINVAL; ++ goto exit; ++ } ++ ++ while((check_fwstate(pmlmepriv, (_FW_UNDER_SURVEY|_FW_UNDER_LINKING))) == _TRUE) ++ { ++ rtw_msleep_os(30); ++ cnt++; ++ if(cnt > 100) ++ break; ++ } ++ ++ ++ //pdata->length = 0;//? ++ pdata->flags = 0; ++ if(pdata->length>=32) ++ { ++ if(copy_from_user(data, pdata->pointer, 32)) ++ { ++ ret= -EINVAL; ++ goto exit; ++ } ++ } ++ else ++ { ++ ret= -EINVAL; ++ goto exit; ++ } ++ ++ _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); ++ ++ phead = get_list_head(queue); ++ plist = get_next(phead); ++ ++ while(1) ++ { ++ if (rtw_end_of_queue_search(phead,plist)== _TRUE) ++ break; ++ ++ ++ pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list); ++ ++ //if(hwaddr_aton_i(pdata->pointer, bssid)) ++ if(hwaddr_aton_i(data, bssid)) ++ { ++ DBG_8192C("Invalid BSSID '%s'.\n", (u8*)data); ++ _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); ++ return -EINVAL; ++ } ++ ++ ++ if(_rtw_memcmp(bssid, pnetwork->network.MacAddress, ETH_ALEN) == _TRUE)//BSSID match, then check if supporting wpa/wpa2 ++ { ++ DBG_8192C("BSSID:" MAC_FMT "\n", MAC_ARG(bssid)); ++ ++ pbuf = rtw_get_wpa_ie(&pnetwork->network.IEs[12], &wpa_ielen, pnetwork->network.IELength-12); ++ if(pbuf && (wpa_ielen>0)) ++ { ++ pdata->flags = 1; ++ break; ++ } ++ ++ pbuf = rtw_get_wpa2_ie(&pnetwork->network.IEs[12], &wpa_ielen, pnetwork->network.IELength-12); ++ if(pbuf && (wpa_ielen>0)) ++ { ++ pdata->flags = 2; ++ break; ++ } ++ ++ } ++ ++ plist = get_next(plist); ++ ++ } ++ ++ _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); ++ ++ if(pdata->length>=34) ++ { ++ if(copy_to_user((u8*)pdata->pointer+32, (u8*)&pdata->flags, 1)) ++ { ++ ret= -EINVAL; ++ goto exit; ++ } ++ } ++ ++exit: ++ ++ return ret; ++ ++} ++ ++static int rtw_set_pid(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ ++ int ret = 0; ++ _adapter *padapter = rtw_netdev_priv(dev); ++ int *pdata = (int *)wrqu; ++ int selector; ++ ++ if((padapter->bDriverStopped) || (pdata==NULL)) ++ { ++ ret= -EINVAL; ++ goto exit; ++ } ++ ++ selector = *pdata; ++ if(selector < 3 && selector >=0) { ++ padapter->pid[selector] = *(pdata+1); ++ #ifdef CONFIG_GLOBAL_UI_PID ++ ui_pid[selector] = *(pdata+1); ++ #endif ++ DBG_871X("%s set pid[%d]=%d\n", __FUNCTION__, selector ,padapter->pid[selector]); ++ } ++ else ++ DBG_871X("%s selector %d error\n", __FUNCTION__, selector); ++ ++exit: ++ ++ return ret; ++ ++} ++ ++static int rtw_wps_start(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ ++ int ret = 0; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct iw_point *pdata = &wrqu->data; ++ u32 u32wps_start = 0; ++ unsigned int uintRet = 0; ++ ++ uintRet = copy_from_user( ( void* ) &u32wps_start, pdata->pointer, 4 ); ++ ++ if((padapter->bDriverStopped) || (pdata==NULL)) ++ { ++ ret= -EINVAL; ++ goto exit; ++ } ++ ++ if ( u32wps_start == 0 ) ++ { ++ u32wps_start = *extra; ++ } ++ ++ DBG_8192C( "[%s] wps_start = %d\n", __FUNCTION__, u32wps_start ); ++ ++ if ( u32wps_start == 1 ) // WPS Start ++ { ++ rtw_led_control(padapter, LED_CTL_START_WPS); ++ } ++ else if ( u32wps_start == 2 ) // WPS Stop because of wps success ++ { ++ rtw_led_control(padapter, LED_CTL_STOP_WPS); ++ } ++ else if ( u32wps_start == 3 ) // WPS Stop because of wps fail ++ { ++ rtw_led_control(padapter, LED_CTL_STOP_WPS_FAIL); ++ } ++exit: ++ ++ return ret; ++ ++} ++ ++#ifdef CONFIG_P2P ++ ++static int rtw_wext_p2p_enable(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ ++ int ret = 0; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ struct iw_point *pdata = &wrqu->data; ++ struct wifidirect_info *pwdinfo= &(padapter->wdinfo); ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct pwrctrl_priv *pwrpriv = &padapter->pwrctrlpriv; ++ enum P2P_ROLE init_role = P2P_ROLE_DISABLE; ++ ++ if(*extra == '0' ) ++ init_role = P2P_ROLE_DISABLE; ++ else if(*extra == '1') ++ init_role = P2P_ROLE_DEVICE; ++ else if(*extra == '2') ++ init_role = P2P_ROLE_CLIENT; ++ else if(*extra == '3') ++ init_role = P2P_ROLE_GO; ++ ++ if(_FAIL == rtw_p2p_enable(padapter, init_role)) ++ { ++ ret = -EFAULT; ++ goto exit; ++ } ++ ++ //set channel/bandwidth ++ if(init_role != P2P_ROLE_DISABLE) ++ { ++ u8 channel, ch_offset; ++ u16 bwmode; ++ ++ if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_LISTEN)) ++ { ++ // Stay at the listen state and wait for discovery. ++ channel = pwdinfo->listen_channel; ++ ch_offset = HAL_PRIME_CHNL_OFFSET_DONT_CARE; ++ bwmode = HT_CHANNEL_WIDTH_20; ++ } ++ else ++ { ++ pwdinfo->operating_channel = pmlmeext->cur_channel; ++ ++ channel = pwdinfo->operating_channel; ++ ch_offset = pmlmeext->cur_ch_offset; ++ bwmode = pmlmeext->cur_bwmode; ++ } ++ ++ set_channel_bwmode(padapter, channel, ch_offset, bwmode); ++ } ++ ++exit: ++ return ret; ++ ++} ++ ++static int rtw_p2p_set_go_nego_ssid(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ ++ int ret = 0; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ struct iw_point *pdata = &wrqu->data; ++ struct wifidirect_info *pwdinfo= &(padapter->wdinfo); ++ ++ DBG_8192C( "[%s] ssid = %s, len = %d\n", __FUNCTION__, extra, strlen( extra ) ); ++ _rtw_memcpy( pwdinfo->nego_ssid, extra, strlen( extra ) ); ++ pwdinfo->nego_ssidlen = strlen( extra ); ++ ++ return ret; ++ ++} ++ ++ ++static int rtw_p2p_set_intent(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ ++ int ret = 0; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ struct iw_point *pdata = &wrqu->data; ++ struct wifidirect_info *pwdinfo= &(padapter->wdinfo); ++ u8 intent = pwdinfo->intent; ++ ++ switch( wrqu->data.length ) ++ { ++ case 1: ++ { ++ intent = extra[ 0 ] - '0'; ++ break; ++ } ++ case 2: ++ { ++ intent = str_2char2num( extra[ 0 ], extra[ 1 ]); ++ break; ++ } ++ } ++ ++ if ( intent <= 15 ) ++ { ++ pwdinfo->intent= intent; ++ } ++ else ++ { ++ ret = -1; ++ } ++ ++ DBG_8192C( "[%s] intent = %d\n", __FUNCTION__, intent); ++ ++ return ret; ++ ++} ++ ++static int rtw_p2p_set_listen_ch(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ ++ int ret = 0; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ struct iw_point *pdata = &wrqu->data; ++ struct wifidirect_info *pwdinfo= &(padapter->wdinfo); ++ u8 listen_ch = pwdinfo->listen_channel; // Listen channel number ++ ++ switch( wrqu->data.length ) ++ { ++ case 1: ++ { ++ listen_ch = extra[ 0 ] - '0'; ++ break; ++ } ++ case 2: ++ { ++ listen_ch = str_2char2num( extra[ 0 ], extra[ 1 ]); ++ break; ++ } ++ } ++ ++ if ( listen_ch > 0 && listen_ch <= 13 ) ++ { ++ pwdinfo->listen_channel = listen_ch; ++ set_channel_bwmode(padapter, pwdinfo->listen_channel, HAL_PRIME_CHNL_OFFSET_DONT_CARE, HT_CHANNEL_WIDTH_20); ++ } ++ else ++ { ++ ret = -1; ++ } ++ ++ DBG_8192C( "[%s] listen_ch = %d\n", __FUNCTION__, pwdinfo->listen_channel ); ++ ++ return ret; ++ ++} ++ ++static int rtw_p2p_set_op_ch(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++// Commented by Albert 20110524 ++// This function is used to set the operating channel if the driver will become the group owner ++ ++ int ret = 0; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ struct iw_point *pdata = &wrqu->data; ++ struct wifidirect_info *pwdinfo= &(padapter->wdinfo); ++ u8 op_ch = pwdinfo->operating_channel; // Operating channel number ++ ++ switch( wrqu->data.length ) ++ { ++ case 1: ++ { ++ op_ch = extra[ 0 ] - '0'; ++ break; ++ } ++ case 2: ++ { ++ op_ch = str_2char2num( extra[ 0 ], extra[ 1 ]); ++ break; ++ } ++ } ++ ++ if ( op_ch > 0 && op_ch <= 13 ) ++ { ++ pwdinfo->operating_channel = op_ch; ++ } ++ else if(IsLegal5GChannel(padapter, op_ch)) ++ { ++ pwdinfo->operating_channel = op_ch; ++ } ++ else ++ { ++ ret = -1; ++ } ++ ++ DBG_8192C( "[%s] op_ch = %d\n", __FUNCTION__, pwdinfo->operating_channel ); ++ ++ return ret; ++ ++} ++ ++ ++static int rtw_p2p_profilefound(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ ++ int ret = 0; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ struct iw_point *pdata = &wrqu->data; ++ struct wifidirect_info *pwdinfo= &(padapter->wdinfo); ++ ++ // Comment by Albert 2010/10/13 ++ // Input data format: ++ // Ex: 0 ++ // Ex: 1XX:XX:XX:XX:XX:XXYYSSID ++ // 0 => Reflush the profile record list. ++ // 1 => Add the profile list ++ // XX:XX:XX:XX:XX:XX => peer's MAC Address ( ex: 00:E0:4C:00:00:01 ) ++ // YY => SSID Length ++ // SSID => SSID for persistence group ++ ++ DBG_8192C( "[%s] In value = %s, len = %d \n", __FUNCTION__, extra, wrqu->data.length -1); ++ ++ ++ // The upper application should pass the SSID to driver by using this rtw_p2p_profilefound function. ++ if(!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) ++ { ++ if ( extra[ 0 ] == '0' ) ++ { ++ // Remove all the profile information of wifidirect_info structure. ++ _rtw_memset( &pwdinfo->profileinfo[ 0 ], 0x00, sizeof( struct profile_info ) * P2P_MAX_PERSISTENT_GROUP_NUM ); ++ pwdinfo->profileindex = 0; ++ } ++ else ++ { ++ if ( pwdinfo->profileindex >= P2P_MAX_PERSISTENT_GROUP_NUM ) ++ { ++ ret = -1; ++ } ++ else ++ { ++ int jj, kk; ++ ++ // Add this profile information into pwdinfo->profileinfo ++ // Ex: 1XX:XX:XX:XX:XX:XXYYSSID ++ for( jj = 0, kk = 1; jj < ETH_ALEN; jj++, kk += 3 ) ++ { ++ pwdinfo->profileinfo[ pwdinfo->profileindex ].peermac[ jj ] = key_2char2num(extra[ kk ], extra[ kk+ 1 ]); ++ } ++ ++ pwdinfo->profileinfo[ pwdinfo->profileindex ].ssidlen = ( extra[18] - '0' ) * 10 + ( extra[ 19 ] - '0' ); ++ _rtw_memcpy( pwdinfo->profileinfo[ pwdinfo->profileindex ].ssid, &extra[ 20 ], pwdinfo->profileinfo[ pwdinfo->profileindex ].ssidlen ); ++ pwdinfo->profileindex++; ++ } ++ } ++ } ++ ++ return ret; ++ ++} ++ ++static int rtw_p2p_setDN(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ ++ int ret = 0; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ struct iw_point *pdata = &wrqu->data; ++ struct wifidirect_info *pwdinfo= &(padapter->wdinfo); ++ ++ ++ DBG_8192C( "[%s] %s %d\n", __FUNCTION__, extra, wrqu->data.length -1 ); ++ pwdinfo->device_name_len = wrqu->data.length - 1; ++ _rtw_memset( pwdinfo->device_name, 0x00, WPS_MAX_DEVICE_NAME_LEN ); ++ _rtw_memcpy( pwdinfo->device_name, extra, pwdinfo->device_name_len ); ++ ++ return ret; ++ ++} ++ ++ ++static int rtw_p2p_get_status(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ ++ int ret = 0; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct iw_point *pdata = &wrqu->data; ++ struct wifidirect_info *pwdinfo = &( padapter->wdinfo ); ++ ++ ++ DBG_8192C( "[%s] Role = %d, Status = %d, peer addr = %.2X:%.2X:%.2X:%.2X:%.2X:%.2X\n", __FUNCTION__, rtw_p2p_role(pwdinfo), rtw_p2p_state(pwdinfo), ++ pwdinfo->p2p_peer_interface_addr[ 0 ], pwdinfo->p2p_peer_interface_addr[ 1 ], pwdinfo->p2p_peer_interface_addr[ 2 ], ++ pwdinfo->p2p_peer_interface_addr[ 3 ], pwdinfo->p2p_peer_interface_addr[ 4 ], pwdinfo->p2p_peer_interface_addr[ 5 ]); ++ ++ // Commented by Albert 2010/10/12 ++ // Because of the output size limitation, I had removed the "Role" information. ++ // About the "Role" information, we will use the new private IOCTL to get the "Role" information. ++ sprintf( extra, "\n\nStatus=%.2d\n", rtw_p2p_state(pwdinfo) ); ++ wrqu->data.length = strlen( extra ); ++ ++ if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_LISTEN)) ++ { ++ // Stay at the listen state and wait for discovery. ++ set_channel_bwmode(padapter, pwdinfo->listen_channel, HAL_PRIME_CHNL_OFFSET_DONT_CARE, HT_CHANNEL_WIDTH_20); ++ } ++ ++ return ret; ++ ++} ++ ++// Commented by Albert 20110520 ++// This function will return the config method description ++// This config method description will show us which config method the remote P2P device is intented to use ++// by sending the provisioning discovery request frame. ++ ++static int rtw_p2p_get_req_cm(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ ++ int ret = 0; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct iw_point *pdata = &wrqu->data; ++ struct wifidirect_info *pwdinfo = &( padapter->wdinfo ); ++ ++ sprintf( extra, "\n\nCM=%s\n", pwdinfo->rx_prov_disc_info.strconfig_method_desc_of_prov_disc_req ); ++ wrqu->data.length = strlen( extra ); ++ return ret; ++ ++} ++ ++ ++static int rtw_p2p_get_role(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ ++ int ret = 0; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct iw_point *pdata = &wrqu->data; ++ struct wifidirect_info *pwdinfo = &( padapter->wdinfo ); ++ ++ ++ DBG_8192C( "[%s] Role = %d, Status = %d, peer addr = %.2X:%.2X:%.2X:%.2X:%.2X:%.2X\n", __FUNCTION__, rtw_p2p_role(pwdinfo), rtw_p2p_state(pwdinfo), ++ pwdinfo->p2p_peer_interface_addr[ 0 ], pwdinfo->p2p_peer_interface_addr[ 1 ], pwdinfo->p2p_peer_interface_addr[ 2 ], ++ pwdinfo->p2p_peer_interface_addr[ 3 ], pwdinfo->p2p_peer_interface_addr[ 4 ], pwdinfo->p2p_peer_interface_addr[ 5 ]); ++ ++ sprintf( extra, "\n\nRole=%.2d\n", rtw_p2p_role(pwdinfo) ); ++ wrqu->data.length = strlen( extra ); ++ return ret; ++ ++} ++ ++ ++static int rtw_p2p_get_peer_ifaddr(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ ++ int ret = 0; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct iw_point *pdata = &wrqu->data; ++ struct wifidirect_info *pwdinfo = &( padapter->wdinfo ); ++ ++ ++ DBG_8192C( "[%s] Role = %d, Status = %d, peer addr = %.2X:%.2X:%.2X:%.2X:%.2X:%.2X\n", __FUNCTION__, rtw_p2p_role(pwdinfo), rtw_p2p_state(pwdinfo), ++ pwdinfo->p2p_peer_interface_addr[ 0 ], pwdinfo->p2p_peer_interface_addr[ 1 ], pwdinfo->p2p_peer_interface_addr[ 2 ], ++ pwdinfo->p2p_peer_interface_addr[ 3 ], pwdinfo->p2p_peer_interface_addr[ 4 ], pwdinfo->p2p_peer_interface_addr[ 5 ]); ++ ++ sprintf( extra, "\nMAC %.2X:%.2X:%.2X:%.2X:%.2X:%.2X", ++ pwdinfo->p2p_peer_interface_addr[ 0 ], pwdinfo->p2p_peer_interface_addr[ 1 ], pwdinfo->p2p_peer_interface_addr[ 2 ], ++ pwdinfo->p2p_peer_interface_addr[ 3 ], pwdinfo->p2p_peer_interface_addr[ 4 ], pwdinfo->p2p_peer_interface_addr[ 5 ]); ++ wrqu->data.length = strlen( extra ); ++ return ret; ++ ++} ++ ++static int rtw_p2p_get_peer_devaddr(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++ ++{ ++ ++ int ret = 0; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct iw_point *pdata = &wrqu->data; ++ struct wifidirect_info *pwdinfo = &( padapter->wdinfo ); ++ ++ DBG_8192C( "[%s] Role = %d, Status = %d, peer addr = %.2X:%.2X:%.2X:%.2X:%.2X:%.2X\n", __FUNCTION__, rtw_p2p_role(pwdinfo), rtw_p2p_state(pwdinfo), ++ pwdinfo->rx_prov_disc_info.peerDevAddr[ 0 ], pwdinfo->rx_prov_disc_info.peerDevAddr[ 1 ], ++ pwdinfo->rx_prov_disc_info.peerDevAddr[ 2 ], pwdinfo->rx_prov_disc_info.peerDevAddr[ 3 ], ++ pwdinfo->rx_prov_disc_info.peerDevAddr[ 4 ], pwdinfo->rx_prov_disc_info.peerDevAddr[ 5 ]); ++ sprintf( extra, "\n%.2X%.2X%.2X%.2X%.2X%.2X", ++ pwdinfo->rx_prov_disc_info.peerDevAddr[ 0 ], pwdinfo->rx_prov_disc_info.peerDevAddr[ 1 ], ++ pwdinfo->rx_prov_disc_info.peerDevAddr[ 2 ], pwdinfo->rx_prov_disc_info.peerDevAddr[ 3 ], ++ pwdinfo->rx_prov_disc_info.peerDevAddr[ 4 ], pwdinfo->rx_prov_disc_info.peerDevAddr[ 5 ]); ++ wrqu->data.length = strlen( extra ); ++ return ret; ++ ++} ++ ++static int rtw_p2p_get_groupid(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++ ++{ ++ ++ int ret = 0; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct iw_point *pdata = &wrqu->data; ++ struct wifidirect_info *pwdinfo = &( padapter->wdinfo ); ++ ++ sprintf( extra, "\n%.2X:%.2X:%.2X:%.2X:%.2X:%.2X-%s", ++ pwdinfo->groupid_info.go_device_addr[ 0 ], pwdinfo->groupid_info.go_device_addr[ 1 ], ++ pwdinfo->groupid_info.go_device_addr[ 2 ], pwdinfo->groupid_info.go_device_addr[ 3 ], ++ pwdinfo->groupid_info.go_device_addr[ 4 ], pwdinfo->groupid_info.go_device_addr[ 5 ], ++ pwdinfo->groupid_info.ssid); ++ wrqu->data.length = strlen( extra ); ++ return ret; ++ ++} ++ ++ ++static int rtw_p2p_get_wps_configmethod(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ ++ int ret = 0; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct iw_point *pdata = &wrqu->data; ++ struct wifidirect_info *pwdinfo = &( padapter->wdinfo ); ++ u8 peerMAC[ ETH_ALEN ] = { 0x00 }; ++ int jj,kk; ++ u8 peerMACStr[ 17 ] = { 0x00 }; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ _irqL irqL; ++ _list *plist, *phead; ++ _queue *queue = &(pmlmepriv->scanned_queue); ++ struct wlan_network *pnetwork = NULL; ++ u8 blnMatch = 0; ++ u16 attr_content = 0; ++ uint attr_contentlen = 0; ++ //6 is the string "wpsCM=", 17 is the MAC addr, we have to clear it at wrqu->data.pointer ++ u8 attr_content_str[ 6 + 17 ] = { 0x00 }; ++ ++ ++ // Commented by Albert 20110727 ++ // The input data is the MAC address which the application wants to know its WPS config method. ++ // After knowing its WPS config method, the application can decide the config method for provisioning discovery. ++ // Format: iwpriv wlanx p2p_get_wpsCM 00:E0:4C:00:00:05 ++ ++ DBG_8192C( "[%s] data = %s\n", __FUNCTION__, ( char* ) extra ); ++ //_rtw_memcpy( peerMACStr , extra , 17 ); ++ ++ if ( copy_from_user(peerMACStr, wrqu->data.pointer + 6 , 17) ) { ++ return -EFAULT; ++ } ++ ++ for( jj = 0, kk = 0; jj < ETH_ALEN; jj++, kk += 3 ) ++ { ++ peerMAC[ jj ] = key_2char2num( peerMACStr[kk], peerMACStr[kk+ 1] ); ++ } ++ ++ _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); ++ ++ phead = get_list_head(queue); ++ plist = get_next(phead); ++ ++ while(1) ++ { ++ if (rtw_end_of_queue_search(phead,plist)== _TRUE) ++ break; ++ ++ pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list); ++ if ( _rtw_memcmp( pnetwork->network.MacAddress, peerMAC, ETH_ALEN ) ) ++ { ++ u8 *wpsie; ++ uint wpsie_len = 0; ++ ++ // The mac address is matched. ++ ++ if ( (wpsie=rtw_get_wps_ie( &pnetwork->network.IEs[ 12 ], pnetwork->network.IELength - 12, NULL, &wpsie_len )) ) ++ { ++ rtw_get_wps_attr_content( wpsie, wpsie_len, WPS_ATTR_CONF_METHOD, ( u8* ) &attr_content, &attr_contentlen); ++ if ( attr_contentlen ) ++ { ++ attr_content = be16_to_cpu( attr_content ); ++ sprintf( attr_content_str, "\n\nM=%.4d", attr_content ); ++ blnMatch = 1; ++ } ++ } ++ ++ break; ++ } ++ ++ plist = get_next(plist); ++ ++ } ++ ++ _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); ++ ++ if ( !blnMatch ) ++ { ++ sprintf( attr_content_str, "\n\nM=0000" ); ++ } ++ ++ if ( copy_to_user(wrqu->data.pointer, attr_content_str, 6 + 17)) { ++ return -EFAULT; ++ } ++ ++ return ret; ++ ++} ++ ++#ifdef CONFIG_WFD ++static int rtw_p2p_get_peer_WFD_port(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ ++ int ret = 0; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct iw_point *pdata = &wrqu->data; ++ struct wifidirect_info *pwdinfo = &( padapter->wdinfo ); ++ ++ DBG_871X( "[%s] p2p_state = %d\n", __FUNCTION__, rtw_p2p_state(pwdinfo) ); ++ ++ sprintf( extra, "\n\nPort=%d\n", pwdinfo->wfd_info.peer_rtsp_ctrlport ); ++ DBG_8192C( "[%s] remote port = %d\n", __FUNCTION__, pwdinfo->wfd_info.peer_rtsp_ctrlport ); ++ ++ wrqu->data.length = strlen( extra ); ++ return ret; ++ ++} ++#endif // CONFIG_WFD ++ ++static int rtw_p2p_get_device_name(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ ++ int ret = 0; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct iw_point *pdata = &wrqu->data; ++ struct wifidirect_info *pwdinfo = &( padapter->wdinfo ); ++ u8 peerMAC[ ETH_ALEN ] = { 0x00 }; ++ int jj,kk; ++ u8 peerMACStr[ 17 ] = { 0x00 }; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ _irqL irqL; ++ _list *plist, *phead; ++ _queue *queue = &(pmlmepriv->scanned_queue); ++ struct wlan_network *pnetwork = NULL; ++ u8 blnMatch = 0; ++ u8 dev_name[ WPS_MAX_DEVICE_NAME_LEN ] = { 0x00 }; ++ uint dev_len = 0; ++ u8 dev_name_str[ WPS_MAX_DEVICE_NAME_LEN + 5 ] = { 0x00 }; // +5 is for the str "devN=", we have to clear it at wrqu->data.pointer ++ ++ // Commented by Kurt 20110727 ++ // The input data is the MAC address which the application wants to know its device name. ++ // Such user interface could show peer device's device name instead of ssid. ++ // Format: iwpriv wlanx p2p_get_wpsCM 00:E0:4C:00:00:05 ++ ++ DBG_8192C( "[%s] data = %s\n", __FUNCTION__, ( char* ) extra ); ++ //_rtw_memcpy( peerMACStr , extra , 17 ); ++ ++ if ( copy_from_user(peerMACStr, wrqu->data.pointer + 5 , 17) ) { ++ return -EFAULT; ++ } ++ ++ for( jj = 0, kk = 0; jj < ETH_ALEN; jj++, kk += 3 ) ++ { ++ peerMAC[ jj ] = key_2char2num( peerMACStr[kk], peerMACStr[kk+ 1] ); ++ } ++ ++ _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); ++ ++ phead = get_list_head(queue); ++ plist = get_next(phead); ++ ++ while(1) ++ { ++ if (rtw_end_of_queue_search(phead,plist)== _TRUE) ++ break; ++ ++ pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list); ++ if ( _rtw_memcmp( pnetwork->network.MacAddress, peerMAC, ETH_ALEN ) ) ++ { ++ u8 *wpsie; ++ uint wpsie_len = 0; ++ ++ ++ // The mac address is matched. ++ ++ if ( (wpsie=rtw_get_wps_ie( &pnetwork->network.IEs[ 12 ], pnetwork->network.IELength - 12, NULL, &wpsie_len )) ) ++ { ++ rtw_get_wps_attr_content( wpsie, wpsie_len, WPS_ATTR_DEVICE_NAME, dev_name, &dev_len); ++ if ( dev_len ) ++ { ++ sprintf( dev_name_str, "\n\nN=%s", dev_name ); ++ blnMatch = 1; ++ } ++ } ++ break; ++ } ++ ++ plist = get_next(plist); ++ ++ } ++ ++ _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); ++ ++ if ( !blnMatch ) ++ { ++ sprintf( dev_name_str, "\n\nN=0000" ); ++ } ++ ++ if ( copy_to_user(wrqu->data.pointer, dev_name_str, 5+ (( dev_len > 17 )? dev_len : 17) )) { ++ return -EFAULT; ++ } ++ ++ return ret; ++ ++} ++ ++static int rtw_p2p_connect(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ ++ int ret = 0; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct iw_point *pdata = &wrqu->data; ++ struct wifidirect_info *pwdinfo = &( padapter->wdinfo ); ++ u8 peerMAC[ ETH_ALEN ] = { 0x00 }; ++ int jj,kk; ++ u8 peerMACStr[ ETH_ALEN * 2 ] = { 0x00 }; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ _irqL irqL; ++ _list *plist, *phead; ++ _queue *queue = &(pmlmepriv->scanned_queue); ++ struct wlan_network *pnetwork = NULL; ++ uint uintPeerChannel = 0; ++ ++ // Commented by Albert 20110304 ++ // The input data contains two informations. ++ // 1. First information is the MAC address which wants to formate with ++ // 2. Second information is the WPS PINCode or "pbc" string for push button method ++ // Format: 00:E0:4C:00:00:05 ++ // Format: 00:E0:4C:00:00:05 ++ ++ DBG_8192C( "[%s] data = %s\n", __FUNCTION__, extra ); ++ ++ if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE) || rtw_p2p_chk_state(pwdinfo, P2P_STATE_IDLE)) ++ { ++ DBG_8192C( "[%s] WiFi Direct is disable!\n", __FUNCTION__ ); ++ return ret; ++ } ++ ++ if ( pwdinfo->ui_got_wps_info == P2P_NO_WPSINFO ) ++ { ++ return -1; ++ } ++ ++ for( jj = 0, kk = 0; jj < ETH_ALEN; jj++, kk += 3 ) ++ { ++ peerMAC[ jj ] = key_2char2num( extra[kk], extra[kk+ 1] ); ++ } ++ ++ _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); ++ ++ phead = get_list_head(queue); ++ plist = get_next(phead); ++ ++ while(1) ++ { ++ if (rtw_end_of_queue_search(phead,plist)== _TRUE) ++ break; ++ ++ pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list); ++ if ( _rtw_memcmp( pnetwork->network.MacAddress, peerMAC, ETH_ALEN ) ) ++ { ++ uintPeerChannel = pnetwork->network.Configuration.DSConfig; ++ break; ++ } ++ ++ plist = get_next(plist); ++ ++ } ++ ++ _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); ++ ++ if ( uintPeerChannel ) ++ { ++ _rtw_memset( &pwdinfo->nego_req_info, 0x00, sizeof( struct tx_nego_req_info ) ); ++ _rtw_memset( &pwdinfo->groupid_info, 0x00, sizeof( struct group_id_info ) ); ++ ++ pwdinfo->nego_req_info.peer_channel_num[ 0 ] = uintPeerChannel; ++ _rtw_memcpy( pwdinfo->nego_req_info.peerDevAddr, pnetwork->network.MacAddress, ETH_ALEN ); ++ pwdinfo->nego_req_info.benable = _TRUE; ++ ++ rtw_p2p_set_pre_state(pwdinfo, rtw_p2p_state(pwdinfo)); ++ rtw_p2p_set_state(pwdinfo, P2P_STATE_GONEGO_ING); ++ ++ DBG_8192C( "[%s] Start PreTx Procedure!\n", __FUNCTION__ ); ++ _set_timer( &pwdinfo->pre_tx_scan_timer, P2P_TX_PRESCAN_TIMEOUT ); ++ _set_timer( &pwdinfo->restore_p2p_state_timer, P2P_GO_NEGO_TIMEOUT ); ++ } ++ else ++ { ++ DBG_8192C( "[%s] Not Found in Scanning Queue~\n", __FUNCTION__ ); ++ ret = -1; ++ } ++exit: ++ ++ return ret; ++} ++ ++static int rtw_p2p_prov_disc(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ ++ int ret = 0; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct iw_point *pdata = &wrqu->data; ++ struct wifidirect_info *pwdinfo = &( padapter->wdinfo ); ++ u8 peerMAC[ ETH_ALEN ] = { 0x00 }; ++ int jj,kk; ++ u8 peerMACStr[ ETH_ALEN * 2 ] = { 0x00 }; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ _list *plist, *phead; ++ _queue *queue = &(pmlmepriv->scanned_queue); ++ struct wlan_network *pnetwork = NULL; ++ uint uintPeerChannel = 0; ++ u8 attr_content[50] = { 0x00 }, _status = 0; ++ u8 *p2pie; ++ uint p2pielen = 0, attr_contentlen = 0; ++ _irqL irqL; ++ ++ // Commented by Albert 20110301 ++ // The input data contains two informations. ++ // 1. First information is the MAC address which wants to issue the provisioning discovery request frame. ++ // 2. Second information is the WPS configuration method which wants to discovery ++ // Format: 00:E0:4C:00:00:05_display ++ // Format: 00:E0:4C:00:00:05_keypad ++ // Format: 00:E0:4C:00:00:05_pbc ++ // Format: 00:E0:4C:00:00:05_label ++ ++ DBG_8192C( "[%s] data = %s\n", __FUNCTION__, extra ); ++ ++ if(rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE) || rtw_p2p_chk_state(pwdinfo, P2P_STATE_IDLE)) ++ { ++ DBG_8192C( "[%s] WiFi Direct is disable!\n", __FUNCTION__ ); ++ return ret; ++ } ++ else ++ { ++ // Reset the content of struct tx_provdisc_req_info excluded the wps_config_method_request. ++ _rtw_memset( pwdinfo->tx_prov_disc_info.peerDevAddr, 0x00, ETH_ALEN ); ++ _rtw_memset( pwdinfo->tx_prov_disc_info.peerIFAddr, 0x00, ETH_ALEN ); ++ _rtw_memset( &pwdinfo->tx_prov_disc_info.ssid, 0x00, sizeof( NDIS_802_11_SSID ) ); ++ pwdinfo->tx_prov_disc_info.peer_channel_num[ 0 ] = 0; ++ pwdinfo->tx_prov_disc_info.peer_channel_num[ 1 ] = 0; ++ pwdinfo->tx_prov_disc_info.benable = _FALSE; ++ } ++ ++ for( jj = 0, kk = 0; jj < ETH_ALEN; jj++, kk += 3 ) ++ { ++ peerMAC[ jj ] = key_2char2num( extra[kk], extra[kk+ 1] ); ++ } ++ ++ if ( _rtw_memcmp( &extra[ 18 ], "display", 7 ) ) ++ { ++ pwdinfo->tx_prov_disc_info.wps_config_method_request = WPS_CM_DISPLYA; ++ } ++ else if ( _rtw_memcmp( &extra[ 18 ], "keypad", 7 ) ) ++ { ++ pwdinfo->tx_prov_disc_info.wps_config_method_request = WPS_CM_KEYPAD; ++ } ++ else if ( _rtw_memcmp( &extra[ 18 ], "pbc", 3 ) ) ++ { ++ pwdinfo->tx_prov_disc_info.wps_config_method_request = WPS_CM_PUSH_BUTTON; ++ } ++ else if ( _rtw_memcmp( &extra[ 18 ], "label", 5 ) ) ++ { ++ pwdinfo->tx_prov_disc_info.wps_config_method_request = WPS_CM_LABEL; ++ } ++ else ++ { ++ DBG_8192C( "[%s] Unknown WPS config methodn", __FUNCTION__ ); ++ return( ret ); ++ } ++ ++ _enter_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); ++ ++ phead = get_list_head(queue); ++ plist = get_next(phead); ++ ++ while(1) ++ { ++ if (rtw_end_of_queue_search(phead,plist)== _TRUE) ++ break; ++ ++ pnetwork = LIST_CONTAINOR(plist, struct wlan_network, list); ++ ++ // Commented by Albert 2011/05/18 ++ // Match the device address located in the P2P IE ++ // This is for the case that the P2P device address is not the same as the P2P interface address. ++ ++ if ( (p2pie=rtw_get_p2p_ie( &pnetwork->network.IEs[12], pnetwork->network.IELength - 12, NULL, &p2pielen)) ) ++ { ++ // The P2P Device ID attribute is included in the Beacon frame. ++ // The P2P Device Info attribute is included in the probe response frame. ++ ++ if ( rtw_get_p2p_attr_content( p2pie, p2pielen, P2P_ATTR_DEVICE_ID, attr_content, &attr_contentlen) ) ++ { ++ // Handle the P2P Device ID attribute of Beacon first ++ if ( _rtw_memcmp( attr_content, peerMAC, ETH_ALEN ) ) ++ { ++ uintPeerChannel = pnetwork->network.Configuration.DSConfig; ++ break; ++ } ++ } ++ else if ( rtw_get_p2p_attr_content( p2pie, p2pielen, P2P_ATTR_DEVICE_INFO, attr_content, &attr_contentlen) ) ++ { ++ // Handle the P2P Device Info attribute of probe response ++ if ( _rtw_memcmp( attr_content, peerMAC, ETH_ALEN ) ) ++ { ++ uintPeerChannel = pnetwork->network.Configuration.DSConfig; ++ break; ++ } ++ } ++ ++ } ++ ++ plist = get_next(plist); ++ ++ } ++ ++ _exit_critical_bh(&(pmlmepriv->scanned_queue.lock), &irqL); ++ ++ if ( uintPeerChannel ) ++ { ++ _rtw_memcpy( pwdinfo->tx_prov_disc_info.peerIFAddr, pnetwork->network.MacAddress, ETH_ALEN ); ++ _rtw_memcpy( pwdinfo->tx_prov_disc_info.peerDevAddr, peerMAC, ETH_ALEN ); ++ pwdinfo->tx_prov_disc_info.peer_channel_num[0] = ( u16 ) uintPeerChannel; ++ pwdinfo->tx_prov_disc_info.benable = _TRUE; ++ rtw_p2p_set_pre_state(pwdinfo, rtw_p2p_state(pwdinfo)); ++ rtw_p2p_set_state(pwdinfo, P2P_STATE_TX_PROVISION_DIS_REQ); ++ ++ if(rtw_p2p_chk_role(pwdinfo, P2P_ROLE_CLIENT)) ++ { ++ _rtw_memcpy( &pwdinfo->tx_prov_disc_info.ssid, &pnetwork->network.Ssid, sizeof( NDIS_802_11_SSID ) ); ++ } ++ else if (rtw_p2p_chk_role(pwdinfo, P2P_ROLE_DEVICE) || rtw_p2p_chk_role(pwdinfo, P2P_ROLE_GO)) ++ { ++ _rtw_memcpy( pwdinfo->tx_prov_disc_info.ssid.Ssid, pwdinfo->p2p_wildcard_ssid, P2P_WILDCARD_SSID_LEN ); ++ pwdinfo->tx_prov_disc_info.ssid.SsidLength= P2P_WILDCARD_SSID_LEN; ++ } ++ ++ set_channel_bwmode(padapter, uintPeerChannel, HAL_PRIME_CHNL_OFFSET_DONT_CARE, HT_CHANNEL_WIDTH_20); ++ _set_timer( &pwdinfo->pre_tx_scan_timer, P2P_TX_PRESCAN_TIMEOUT ); ++ _set_timer( &pwdinfo->restore_p2p_state_timer, P2P_PROVISION_TIMEOUT ); ++ ++ } ++ else ++ { ++ DBG_8192C( "[%s] NOT Found in the Scanning Queue!\n", __FUNCTION__ ); ++ } ++exit: ++ ++ return ret; ++ ++} ++ ++// Added by Albert 20110328 ++// This function is used to inform the driver the user had specified the pin code value or pbc ++// to application. ++ ++static int rtw_p2p_got_wpsinfo(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ ++ int ret = 0; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct iw_point *pdata = &wrqu->data; ++ struct wifidirect_info *pwdinfo = &( padapter->wdinfo ); ++ ++ ++ DBG_8192C( "[%s] data = %s\n", __FUNCTION__, extra ); ++ // Added by Albert 20110328 ++ // if the input data is P2P_NO_WPSINFO -> reset the wpsinfo ++ // if the input data is P2P_GOT_WPSINFO_PEER_DISPLAY_PIN -> the utility just input the PIN code got from the peer P2P device. ++ // if the input data is P2P_GOT_WPSINFO_SELF_DISPLAY_PIN -> the utility just got the PIN code from itself. ++ // if the input data is P2P_GOT_WPSINFO_PBC -> the utility just determine to use the PBC ++ ++ if ( *extra == '0' ) ++ { ++ pwdinfo->ui_got_wps_info = P2P_NO_WPSINFO; ++ } ++ else if ( *extra == '1' ) ++ { ++ pwdinfo->ui_got_wps_info = P2P_GOT_WPSINFO_PEER_DISPLAY_PIN; ++ } ++ else if ( *extra == '2' ) ++ { ++ pwdinfo->ui_got_wps_info = P2P_GOT_WPSINFO_SELF_DISPLAY_PIN; ++ } ++ else if ( *extra == '3' ) ++ { ++ pwdinfo->ui_got_wps_info = P2P_GOT_WPSINFO_PBC; ++ } ++ else ++ { ++ pwdinfo->ui_got_wps_info = P2P_NO_WPSINFO; ++ } ++ ++ return ret; ++ ++} ++ ++#endif //CONFIG_P2P ++ ++static int rtw_p2p_set(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ ++ int ret = 0; ++#ifdef CONFIG_P2P ++ ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ struct iw_point *pdata = &wrqu->data; ++ struct wifidirect_info *pwdinfo= &(padapter->wdinfo); ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ ++ DBG_8192C( "[%s] extra = %s\n", __FUNCTION__, extra ); ++ ++ if ( _rtw_memcmp( extra, "enable=", 7 ) ) ++ { ++ rtw_wext_p2p_enable( dev, info, wrqu, &extra[7] ); ++ } ++ else if ( _rtw_memcmp( extra, "setDN=", 6 ) ) ++ { ++ wrqu->data.length -= 6; ++ rtw_p2p_setDN( dev, info, wrqu, &extra[6] ); ++ } ++ else if ( _rtw_memcmp( extra, "profilefound=", 13 ) ) ++ { ++ wrqu->data.length -= 13; ++ rtw_p2p_profilefound( dev, info, wrqu, &extra[13] ); ++ } ++ else if ( _rtw_memcmp( extra, "prov_disc=", 10 ) ) ++ { ++ wrqu->data.length -= 10; ++ rtw_p2p_prov_disc( dev, info, wrqu, &extra[10] ); ++ } ++ else if ( _rtw_memcmp( extra, "nego=", 5 ) ) ++ { ++ wrqu->data.length -= 5; ++ rtw_p2p_connect( dev, info, wrqu, &extra[5] ); ++ } ++ else if ( _rtw_memcmp( extra, "intent=", 7 ) ) ++ { ++ // Commented by Albert 2011/03/23 ++ // The wrqu->data.length will include the null character ++ // So, we will decrease 7 + 1 ++ wrqu->data.length -= 8; ++ rtw_p2p_set_intent( dev, info, wrqu, &extra[7] ); ++ } ++ else if ( _rtw_memcmp( extra, "ssid=", 5 ) ) ++ { ++ wrqu->data.length -= 5; ++ rtw_p2p_set_go_nego_ssid( dev, info, wrqu, &extra[5] ); ++ } ++ else if ( _rtw_memcmp( extra, "got_wpsinfo=", 12 ) ) ++ { ++ wrqu->data.length -= 12; ++ rtw_p2p_got_wpsinfo( dev, info, wrqu, &extra[12] ); ++ } ++ else if ( _rtw_memcmp( extra, "listen_ch=", 10 ) ) ++ { ++ // Commented by Albert 2011/05/24 ++ // The wrqu->data.length will include the null character ++ // So, we will decrease (10 + 1) ++ wrqu->data.length -= 11; ++ rtw_p2p_set_listen_ch( dev, info, wrqu, &extra[10] ); ++ } ++ else if ( _rtw_memcmp( extra, "op_ch=", 6 ) ) ++ { ++ // Commented by Albert 2011/05/24 ++ // The wrqu->data.length will include the null character ++ // So, we will decrease (6 + 1) ++ wrqu->data.length -= 7; ++ rtw_p2p_set_op_ch( dev, info, wrqu, &extra[6] ); ++ } ++ ++ ++#endif //CONFIG_P2P ++ ++ return ret; ++ ++} ++ ++static int rtw_p2p_get(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ ++ int ret = 0; ++ ++#ifdef CONFIG_P2P ++ ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ struct iw_point *pdata = &wrqu->data; ++ struct wifidirect_info *pwdinfo= &(padapter->wdinfo); ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ ++ DBG_8192C( "[%s] extra = %s\n", __FUNCTION__, (char*) wrqu->data.pointer ); ++ ++ if ( _rtw_memcmp( wrqu->data.pointer, "status", 6 ) ) ++ { ++ rtw_p2p_get_status( dev, info, wrqu, extra ); ++ } ++ else if ( _rtw_memcmp( wrqu->data.pointer, "role", 4 ) ) ++ { ++ rtw_p2p_get_role( dev, info, wrqu, extra); ++ } ++ else if ( _rtw_memcmp( wrqu->data.pointer, "peer_ifa", 8 ) ) ++ { ++ rtw_p2p_get_peer_ifaddr( dev, info, wrqu, extra); ++ } ++ else if ( _rtw_memcmp( wrqu->data.pointer, "req_cm", 6 ) ) ++ { ++ rtw_p2p_get_req_cm( dev, info, wrqu, extra); ++ } ++ else if ( _rtw_memcmp( wrqu->data.pointer, "peer_deva", 9 ) ) ++ { ++ rtw_p2p_get_peer_devaddr( dev, info, wrqu, extra); ++ } ++ else if ( _rtw_memcmp( wrqu->data.pointer, "group_id", 8 ) ) ++ { ++ rtw_p2p_get_groupid( dev, info, wrqu, extra); ++ } ++#ifdef CONFIG_WFD ++ else if ( _rtw_memcmp( wrqu->data.pointer, "peer_port", 9 ) ) ++ { ++ rtw_p2p_get_peer_WFD_port( dev, info, wrqu, extra ); ++ } ++#endif // CONFIG_WFD ++ ++#endif //CONFIG_P2P ++ ++ return ret; ++ ++} ++ ++static int rtw_p2p_get2(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ ++ int ret = 0; ++ ++#ifdef CONFIG_P2P ++ ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ struct iw_point *pdata = &wrqu->data; ++ struct wifidirect_info *pwdinfo= &(padapter->wdinfo); ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ ++ DBG_8192C( "[%s] extra = %s\n", __FUNCTION__, (char*) wrqu->data.pointer ); ++ ++ if ( _rtw_memcmp( extra, "wpsCM=", 6 ) ) ++ { ++ wrqu->data.length -= 6; ++ rtw_p2p_get_wps_configmethod( dev, info, wrqu, &extra[6]); ++ } ++ else if ( _rtw_memcmp( extra, "devN=", 5 ) ) ++ { ++ wrqu->data.length -= 5; ++ rtw_p2p_get_device_name( dev, info, wrqu, &extra[5] ); ++ } ++ ++#endif //CONFIG_P2P ++ ++ return ret; ++ ++} ++ ++extern char *ifname; ++extern int rtw_change_ifname(_adapter *padapter, const char *ifname); ++static int rtw_rereg_nd_name(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ int ret = 0; ++ _adapter *padapter = rtw_netdev_priv(dev); ++ struct rereg_nd_name_data *rereg_priv = &padapter->rereg_nd_name_priv; ++ char new_ifname[IFNAMSIZ]; ++ ++ if(rereg_priv->old_ifname[0] == 0) { ++ strncpy(rereg_priv->old_ifname, ifname, IFNAMSIZ); ++ rereg_priv->old_ifname[IFNAMSIZ-1] = 0; ++ } ++ ++ //DBG_871X("%s wrqu->data.length:%d\n", __FUNCTION__, wrqu->data.length); ++ if(wrqu->data.length > IFNAMSIZ) ++ return -EFAULT; ++ ++ if ( copy_from_user(new_ifname, wrqu->data.pointer, IFNAMSIZ) ) { ++ return -EFAULT; ++ } ++ ++ if( 0 == strcmp(rereg_priv->old_ifname, new_ifname) ) { ++ return ret; ++ } ++ ++ DBG_871X("%s new_ifname:%s\n", __FUNCTION__, new_ifname); ++ if( 0 != (ret = rtw_change_ifname(padapter, new_ifname)) ) { ++ goto exit; ++ } ++ ++ if(_rtw_memcmp(rereg_priv->old_ifname, "disable%d", 9) == _TRUE) { ++ padapter->ledpriv.bRegUseLed= rereg_priv->old_bRegUseLed; ++ rtw_sw_led_init(padapter); ++ rtw_ips_mode_req(&padapter->pwrctrlpriv, rereg_priv->old_ips_mode); ++ } ++ ++ strncpy(rereg_priv->old_ifname, new_ifname, IFNAMSIZ); ++ rereg_priv->old_ifname[IFNAMSIZ-1] = 0; ++ ++ if(_rtw_memcmp(new_ifname, "disable%d", 9) == _TRUE) { ++ ++ DBG_871X("%s disable\n", __FUNCTION__); ++ // free network queue for Android's timming issue ++ rtw_free_network_queue(padapter, _TRUE); ++ ++ // close led ++ rtw_led_control(padapter, LED_CTL_POWER_OFF); ++ rereg_priv->old_bRegUseLed = padapter->ledpriv.bRegUseLed; ++ padapter->ledpriv.bRegUseLed= _FALSE; ++ rtw_sw_led_deinit(padapter); ++ ++ // the interface is being "disabled", we can do deeper IPS ++ rereg_priv->old_ips_mode = rtw_get_ips_mode_req(&padapter->pwrctrlpriv); ++ rtw_ips_mode_req(&padapter->pwrctrlpriv, IPS_NORMAL); ++ } ++exit: ++ return ret; ++ ++} ++ ++#if 0 ++void mac_reg_dump(_adapter *padapter) ++{ ++ int i,j=1; ++ DBG_8192C("\n======= MAC REG =======\n"); ++ for(i=0x0;i<0x300;i+=4) ++ { ++ if(j%4==1) DBG_8192C("0x%02x",i); ++ DBG_8192C(" 0x%08x ",rtw_read32(padapter,i)); ++ if((j++)%4 == 0) DBG_8192C("\n"); ++ } ++ for(i=0x400;i<0x800;i+=4) ++ { ++ if(j%4==1) DBG_8192C("0x%02x",i); ++ DBG_8192C(" 0x%08x ",rtw_read32(padapter,i)); ++ if((j++)%4 == 0) DBG_8192C("\n"); ++ } ++} ++void bb_reg_dump(_adapter *padapter) ++{ ++ int i,j=1; ++ DBG_8192C("\n======= BB REG =======\n"); ++ for(i=0x800;i<0x1000;i+=4) ++ { ++ if(j%4==1) DBG_8192C("0x%02x",i); ++ ++ DBG_8192C(" 0x%08x ",rtw_read32(padapter,i)); ++ if((j++)%4 == 0) DBG_8192C("\n"); ++ } ++} ++void rf_reg_dump(_adapter *padapter) ++{ ++ int i,j=1,path; ++ u32 value; ++ DBG_8192C("\n======= RF REG =======\n"); ++ for(path=0;path<2;path++) ++ { ++ DBG_8192C("\nRF_Path(%x)\n",path); ++ for(i=0;i<0x100;i++) ++ { ++ value = PHY_QueryRFReg(padapter, (RF90_RADIO_PATH_E)path,i, bMaskDWord); ++ if(j%4==1) DBG_8192C("0x%02x ",i); ++ DBG_8192C(" 0x%08x ",value); ++ if((j++)%4==0) DBG_8192C("\n"); ++ } ++ } ++} ++ ++#endif ++ ++void mac_reg_dump(_adapter *padapter) ++{ ++ int i,j=1; ++ DBG_8192C("\n======= MAC REG =======\n"); ++ for(i=0x0;i<0x300;i+=4) ++ { ++ if(j%4==1) DBG_8192C("0x%02x",i); ++ DBG_8192C(" 0x%08x ",rtw_read32(padapter,i)); ++ if((j++)%4 == 0) DBG_8192C("\n"); ++ } ++ for(i=0x400;i<0x800;i+=4) ++ { ++ if(j%4==1) DBG_8192C("0x%02x",i); ++ DBG_8192C(" 0x%08x ",rtw_read32(padapter,i)); ++ if((j++)%4 == 0) DBG_8192C("\n"); ++ } ++} ++void bb_reg_dump(_adapter *padapter) ++{ ++ int i,j=1; ++ DBG_8192C("\n======= BB REG =======\n"); ++ for(i=0x800;i<0x1000;i+=4) ++ { ++ if(j%4==1) DBG_8192C("0x%02x",i); ++ ++ DBG_8192C(" 0x%08x ",rtw_read32(padapter,i)); ++ if((j++)%4 == 0) DBG_8192C("\n"); ++ } ++} ++void rf_reg_dump(_adapter *padapter) ++{ ++ int i,j=1,path; ++ u32 value; ++ u8 rf_type,path_nums = 0; ++ padapter->HalFunc.GetHwRegHandler(padapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type)); ++ ++ DBG_8192C("\n======= RF REG =======\n"); ++ if((RF_1T2R == rf_type) ||(RF_1T1R ==rf_type )) ++ path_nums = 1; ++ else ++ path_nums = 2; ++ ++ for(path=0;pathHalFunc.read_rfreg(padapter, path, i, 0xffffffff); ++ if(j%4==1) DBG_8192C("0x%02x ",i); ++ DBG_8192C(" 0x%08x ",value); ++ if((j++)%4==0) DBG_8192C("\n"); ++ } ++ } ++} ++ ++#ifdef CONFIG_IOL ++#include ++#endif ++static int rtw_dbg_port(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ _irqL irqL; ++ int ret = 0; ++ u8 major_cmd, minor_cmd; ++ u16 arg; ++ u32 extra_arg, *pdata, val32; ++ struct sta_info *psta; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ struct security_priv *psecuritypriv = &padapter->securitypriv; ++ struct wlan_network *cur_network = &(pmlmepriv->cur_network); ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ ++ ++ pdata = (u32*)&wrqu->data; ++ ++ val32 = *pdata; ++ arg = (u16)(val32&0x0000ffff); ++ major_cmd = (u8)(val32>>24); ++ minor_cmd = (u8)((val32>>16)&0x00ff); ++ ++ extra_arg = *(pdata+1); ++ ++ switch(major_cmd) ++ { ++ case 0x70://read_reg ++ switch(minor_cmd) ++ { ++ case 1: ++ DBG_8192C("rtw_read8(0x%x)=0x%02x\n", arg, rtw_read8(padapter, arg)); ++ break; ++ case 2: ++ DBG_8192C("rtw_read16(0x%x)=0x%04x\n", arg, rtw_read16(padapter, arg)); ++ break; ++ case 4: ++ DBG_8192C("rtw_read32(0x%x)=0x%08x\n", arg, rtw_read32(padapter, arg)); ++ break; ++ } ++ break; ++ case 0x71://write_reg ++ switch(minor_cmd) ++ { ++ case 1: ++ rtw_write8(padapter, arg, extra_arg); ++ DBG_8192C("rtw_write8(0x%x)=0x%02x\n", arg, rtw_read8(padapter, arg)); ++ break; ++ case 2: ++ rtw_write16(padapter, arg, extra_arg); ++ DBG_8192C("rtw_write16(0x%x)=0x%04x\n", arg, rtw_read16(padapter, arg)); ++ break; ++ case 4: ++ rtw_write32(padapter, arg, extra_arg); ++ DBG_8192C("rtw_write32(0x%x)=0x%08x\n", arg, rtw_read32(padapter, arg)); ++ break; ++ } ++ break; ++ case 0x72://read_bb ++ DBG_8192C("read_bbreg(0x%x)=0x%x\n", arg, padapter->HalFunc.read_bbreg(padapter, arg, 0xffffffff)); ++ break; ++ case 0x73://write_bb ++ padapter->HalFunc.write_bbreg(padapter, arg, 0xffffffff, extra_arg); ++ DBG_8192C("write_bbreg(0x%x)=0x%x\n", arg, padapter->HalFunc.read_bbreg(padapter, arg, 0xffffffff)); ++ break; ++ case 0x74://read_rf ++ DBG_8192C("read RF_reg path(0x%02x),offset(0x%x),value(0x%08x)\n",minor_cmd,arg,padapter->HalFunc.read_rfreg(padapter, minor_cmd, arg, 0xffffffff)); ++ break; ++ case 0x75://write_rf ++ padapter->HalFunc.write_rfreg(padapter, minor_cmd, arg, 0xffffffff, extra_arg); ++ DBG_8192C("write RF_reg path(0x%02x),offset(0x%x),value(0x%08x)\n",minor_cmd,arg, padapter->HalFunc.read_rfreg(padapter, minor_cmd, arg, 0xffffffff)); ++ break; ++ ++ case 0x76: ++ switch(minor_cmd) ++ { ++ case 0x00: //normal mode, ++ padapter->recvpriv.is_signal_dbg = 0; ++ break; ++ case 0x01: //dbg mode ++ padapter->recvpriv.is_signal_dbg = 1; ++ extra_arg = extra_arg>100?100:extra_arg; ++ extra_arg = extra_arg<0?0:extra_arg; ++ padapter->recvpriv.signal_strength_dbg=extra_arg; ++ break; ++ } ++ break; ++ case 0x78: //IOL test ++ switch(minor_cmd) ++ { ++ #ifdef CONFIG_IOL ++ case 0x04: //LLT table initialization test ++ { ++ u8 page_boundary = 0xf9; ++ { ++ struct xmit_frame *xmit_frame; ++ ++ if((xmit_frame=rtw_IOL_accquire_xmit_frame(padapter)) == NULL) { ++ ret = -ENOMEM; ++ break; ++ } ++ ++ rtw_IOL_append_LLT_cmd(xmit_frame, page_boundary); ++ ++ ++ if(_SUCCESS != rtw_IOL_exec_cmds_sync(padapter, xmit_frame, 500) ) ++ ret = -EPERM; ++ } ++ } ++ break; ++ case 0x05: //blink LED test ++ { ++ u16 reg = 0x4c; ++ u32 blink_num = 50; ++ u32 blink_delay_ms = 200; ++ int i; ++ ++ { ++ struct xmit_frame *xmit_frame; ++ ++ if((xmit_frame=rtw_IOL_accquire_xmit_frame(padapter)) == NULL) { ++ ret = -ENOMEM; ++ break; ++ } ++ ++ for(i=0;idot11AuthAlgrthm, psecuritypriv->dot11PrivacyAlgrthm, ++ psecuritypriv->ndisauthtype, psecuritypriv->ndisencryptstatus); ++ break; ++ case 0x02: ++ DBG_8192C("pmlmeinfo->state=0x%x\n", pmlmeinfo->state); ++ break; ++ case 0x03: ++ DBG_8192C("qos_option=%d\n", pmlmepriv->qospriv.qos_option); ++ DBG_8192C("ht_option=%d\n", pmlmepriv->htpriv.ht_option); ++ break; ++ case 0x04: ++ DBG_8192C("cur_ch=%d\n", pmlmeext->cur_channel); ++ DBG_8192C("cur_bw=%d\n", pmlmeext->cur_bwmode); ++ DBG_8192C("cur_ch_off=%d\n", pmlmeext->cur_ch_offset); ++ break; ++ case 0x05: ++ psta = rtw_get_stainfo(pstapriv, cur_network->network.MacAddress); ++ if(psta) ++ { ++ int i; ++ struct recv_reorder_ctrl *preorder_ctrl; ++ ++ DBG_8192C("sta's macaddr:" MAC_FMT "\n", MAC_ARG(psta->hwaddr)); ++ DBG_8192C("rtsen=%d, cts2slef=%d\n", psta->rtsen, psta->cts2self); ++ DBG_8192C("qos_en=%d, ht_en=%d, init_rate=%d\n", psta->qos_option, psta->htpriv.ht_option, psta->init_rate); ++ DBG_8192C("state=0x%x, aid=%d, macid=%d, raid=%d\n", psta->state, psta->aid, psta->mac_id, psta->raid); ++ DBG_8192C("bwmode=%d, ch_offset=%d, sgi=%d\n", psta->htpriv.bwmode, psta->htpriv.ch_offset, psta->htpriv.sgi); ++ DBG_8192C("ampdu_enable = %d\n", psta->htpriv.ampdu_enable); ++ DBG_8192C("agg_enable_bitmap=%x, candidate_tid_bitmap=%x\n", psta->htpriv.agg_enable_bitmap, psta->htpriv.candidate_tid_bitmap); ++ ++ for(i=0;i<16;i++) ++ { ++ preorder_ctrl = &psta->recvreorder_ctrl[i]; ++ if(preorder_ctrl->enable) ++ { ++ DBG_8192C("tid=%d, indicate_seq=%d\n", i, preorder_ctrl->indicate_seq); ++ } ++ } ++ ++ } ++ else ++ { ++ DBG_8192C("can't get sta's macaddr, cur_network's macaddr:" MAC_FMT "\n", MAC_ARG(cur_network->network.MacAddress)); ++ } ++ break; ++ case 0x06: ++ { ++ u8 DMFlag; ++ padapter->HalFunc.GetHwRegHandler(padapter, HW_VAR_DM_FLAG, (u8 *)(&DMFlag)); ++ DBG_8192C("(B)DMFlag=0x%x, arg=0x%x\n", DMFlag, arg); ++ DMFlag = (u8)(0x0f&arg); ++ DBG_8192C("(A)DMFlag=0x%x\n", DMFlag); ++ padapter->HalFunc.SetHwRegHandler(padapter, HW_VAR_DM_FLAG, (u8 *)(&DMFlag)); ++ } ++ break; ++ case 0x07: ++ DBG_8192C("bSurpriseRemoved=%d, bDriverStopped=%d\n", ++ padapter->bSurpriseRemoved, padapter->bDriverStopped); ++ break; ++ case 0x08: ++ { ++ struct xmit_priv *pxmitpriv = &padapter->xmitpriv; ++ struct recv_priv *precvpriv = &padapter->recvpriv; ++ ++ DBG_8192C("free_xmitbuf_cnt=%d, free_xmitframe_cnt=%d\n", ++ pxmitpriv->free_xmitbuf_cnt, pxmitpriv->free_xmitframe_cnt); ++ #ifdef CONFIG_USB_HCI ++ DBG_8192C("rx_urb_pending_cn=%d\n", precvpriv->rx_pending_cnt); ++ #endif ++ } ++ break; ++ case 0x09: ++ { ++ int i, j; ++ _list *plist, *phead; ++ struct recv_reorder_ctrl *preorder_ctrl; ++ ++#ifdef CONFIG_AP_MODE ++ DBG_8192C("sta_dz_bitmap=0x%x, tim_bitmap=0x%x\n", pstapriv->sta_dz_bitmap, pstapriv->tim_bitmap); ++#endif ++ _enter_critical_bh(&pstapriv->sta_hash_lock, &irqL); ++ ++ for(i=0; i< NUM_STA; i++) ++ { ++ phead = &(pstapriv->sta_hash[i]); ++ plist = get_next(phead); ++ ++ while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) ++ { ++ psta = LIST_CONTAINOR(plist, struct sta_info, hash_list); ++ ++ plist = get_next(plist); ++ ++ if(extra_arg == psta->aid) ++ { ++ DBG_8192C("sta's macaddr:" MAC_FMT "\n", MAC_ARG(psta->hwaddr)); ++ DBG_8192C("rtsen=%d, cts2slef=%d\n", psta->rtsen, psta->cts2self); ++ DBG_8192C("qos_en=%d, ht_en=%d, init_rate=%d\n", psta->qos_option, psta->htpriv.ht_option, psta->init_rate); ++ DBG_8192C("state=0x%x, aid=%d, macid=%d, raid=%d\n", psta->state, psta->aid, psta->mac_id, psta->raid); ++ DBG_8192C("bwmode=%d, ch_offset=%d, sgi=%d\n", psta->htpriv.bwmode, psta->htpriv.ch_offset, psta->htpriv.sgi); ++ DBG_8192C("ampdu_enable = %d\n", psta->htpriv.ampdu_enable); ++ DBG_8192C("agg_enable_bitmap=%x, candidate_tid_bitmap=%x\n", psta->htpriv.agg_enable_bitmap, psta->htpriv.candidate_tid_bitmap); ++ DBG_8192C("capability=0x%x\n", psta->capability); ++ DBG_8192C("flags=0x%x\n", psta->flags); ++ DBG_8192C("wpa_psk=0x%x\n", psta->wpa_psk); ++ DBG_8192C("wpa2_group_cipher=0x%x\n", psta->wpa2_group_cipher); ++ DBG_8192C("wpa2_pairwise_cipher=0x%x\n", psta->wpa2_pairwise_cipher); ++ DBG_8192C("qos_info=0x%x\n", psta->qos_info); ++ DBG_8192C("dot118021XPrivacy=0x%x\n", psta->dot118021XPrivacy); ++ ++ ++ ++ for(j=0;j<16;j++) ++ { ++ preorder_ctrl = &psta->recvreorder_ctrl[j]; ++ if(preorder_ctrl->enable) ++ { ++ DBG_8192C("tid=%d, indicate_seq=%d\n", j, preorder_ctrl->indicate_seq); ++ } ++ } ++ ++ } ++ ++ } ++ } ++ ++ _exit_critical_bh(&pstapriv->sta_hash_lock, &irqL); ++ ++ } ++ break; ++ ++ case 0x0c://dump rx packet ++ { ++ DBG_8192C("dump rx packet (%d)\n",extra_arg); ++ //pHalData->bDumpRxPkt =extra_arg; ++ padapter->HalFunc.SetHalDefVarHandler(padapter, HAL_DEF_DBG_DUMP_RXPKT, &(extra_arg)); ++ } ++ break; ++#if 0 ++ case 0x0d://dump cam ++ { ++ //u8 entry = (u8) extra_arg; ++ u8 entry=0; ++ //dump cam ++ for(entry=0;entry<32;entry++) ++ read_cam(padapter,entry); ++ } ++ break; ++#endif ++ #ifdef DBG_CONFIG_ERROR_DETECT ++ case 0x0f: ++ { ++ if(extra_arg == 0){ ++ DBG_8192C("###### silent reset test.......#####\n"); ++ if(padapter->HalFunc.silentreset) ++ padapter->HalFunc.silentreset(padapter); ++ } ++ ++ } ++ break; ++ case 0x12: ++ { ++ struct pwrctrl_priv *pwrpriv = &padapter->pwrctrlpriv; ++ DBG_8192C("==>silent resete cnts:%d\n",pwrpriv->ips_enter_cnts); ++ } ++ break; ++ ++ #endif ++ ++ case 0x10:// driver version display ++ DBG_8192C("rtw driver version=%s\n", DRIVERVERSION); ++ break; ++ case 0x11: ++ { ++ DBG_8192C("turn %s Rx RSSI display function\n",(extra_arg==1)?"on":"off"); ++ padapter->bRxRSSIDisplay = extra_arg ; ++ } ++ break; ++#if 1 ++ case 0xdd://registers dump , 0 for mac reg,1 for bb reg, 2 for rf reg ++ { ++ if(extra_arg==0){ ++ mac_reg_dump(padapter); ++ } ++ else if(extra_arg==1){ ++ bb_reg_dump(padapter); ++ } ++ else if(extra_arg==2){ ++ rf_reg_dump(padapter); ++ } ++ ++ } ++ break; ++#endif ++ case 0xee://turn on/off dynamic funcs ++ { ++ u8 dm_flag; ++ ++ if(0xf==extra_arg){ ++ padapter->HalFunc.GetHalDefVarHandler(padapter, HAL_DEF_DBG_DM_FUNC,&dm_flag); ++ DBG_8192C(" === DMFlag(0x%02x) === \n",dm_flag); ++ DBG_8192C("extra_arg = 0 - disable all dynamic func \n"); ++ DBG_8192C("extra_arg = 1 - disable DIG- BIT(0)\n"); ++ DBG_8192C("extra_arg = 2 - disable High power - BIT(1)\n"); ++ DBG_8192C("extra_arg = 3 - disable tx power tracking - BIT(2)\n"); ++ DBG_8192C("extra_arg = 4 - disable BT coexistence - BIT(3)\n"); ++ DBG_8192C("extra_arg = 5 - disable antenna diversity - BIT(4)\n"); ++ DBG_8192C("extra_arg = 6 - enable all dynamic func \n"); ++ } ++ else{ ++ /* extra_arg = 0 - disable all dynamic func ++ extra_arg = 1 - disable DIG ++ extra_arg = 2 - disable tx power tracking ++ extra_arg = 3 - turn on all dynamic func ++ */ ++ padapter->HalFunc.SetHalDefVarHandler(padapter, HAL_DEF_DBG_DM_FUNC, &(extra_arg)); ++ padapter->HalFunc.GetHalDefVarHandler(padapter, HAL_DEF_DBG_DM_FUNC,&dm_flag); ++ DBG_8192C(" === DMFlag(0x%02x) === \n",dm_flag); ++ } ++ } ++ break; ++ ++ case 0xfd: ++ rtw_write8(padapter, 0xc50, arg); ++ DBG_8192C("wr(0xc50)=0x%x\n", rtw_read8(padapter, 0xc50)); ++ rtw_write8(padapter, 0xc58, arg); ++ DBG_8192C("wr(0xc58)=0x%x\n", rtw_read8(padapter, 0xc58)); ++ break; ++ case 0xfe: ++ DBG_8192C("rd(0xc50)=0x%x\n", rtw_read8(padapter, 0xc50)); ++ DBG_8192C("rd(0xc58)=0x%x\n", rtw_read8(padapter, 0xc58)); ++ break; ++ case 0xff: ++ { ++ DBG_8192C("dbg(0x210)=0x%x\n", rtw_read32(padapter, 0x210)); ++ DBG_8192C("dbg(0x608)=0x%x\n", rtw_read32(padapter, 0x608)); ++ DBG_8192C("dbg(0x280)=0x%x\n", rtw_read32(padapter, 0x280)); ++ DBG_8192C("dbg(0x284)=0x%x\n", rtw_read32(padapter, 0x284)); ++ DBG_8192C("dbg(0x288)=0x%x\n", rtw_read32(padapter, 0x288)); ++ ++ DBG_8192C("dbg(0x664)=0x%x\n", rtw_read32(padapter, 0x664)); ++ ++ ++ DBG_8192C("\n"); ++ ++ DBG_8192C("dbg(0x430)=0x%x\n", rtw_read32(padapter, 0x430)); ++ DBG_8192C("dbg(0x438)=0x%x\n", rtw_read32(padapter, 0x438)); ++ ++ DBG_8192C("dbg(0x440)=0x%x\n", rtw_read32(padapter, 0x440)); ++ ++ DBG_8192C("dbg(0x458)=0x%x\n", rtw_read32(padapter, 0x458)); ++ ++ DBG_8192C("dbg(0x484)=0x%x\n", rtw_read32(padapter, 0x484)); ++ DBG_8192C("dbg(0x488)=0x%x\n", rtw_read32(padapter, 0x488)); ++ ++ DBG_8192C("dbg(0x444)=0x%x\n", rtw_read32(padapter, 0x444)); ++ DBG_8192C("dbg(0x448)=0x%x\n", rtw_read32(padapter, 0x448)); ++ DBG_8192C("dbg(0x44c)=0x%x\n", rtw_read32(padapter, 0x44c)); ++ DBG_8192C("dbg(0x450)=0x%x\n", rtw_read32(padapter, 0x450)); ++ } ++ break; ++ } ++ break; ++ default: ++ DBG_8192C("error dbg cmd!\n"); ++ break; ++ } ++ ++ ++ return ret; ++ ++} ++ ++static int wpa_set_param(struct net_device *dev, u8 name, u32 value) ++{ ++ uint ret=0; ++ u32 flags; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ ++ switch (name){ ++ case IEEE_PARAM_WPA_ENABLED: ++ ++ padapter->securitypriv.dot11AuthAlgrthm= dot11AuthAlgrthm_8021X; //802.1x ++ ++ //ret = ieee80211_wpa_enable(ieee, value); ++ ++ switch((value)&0xff) ++ { ++ case 1 : //WPA ++ padapter->securitypriv.ndisauthtype = Ndis802_11AuthModeWPAPSK; //WPA_PSK ++ padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption2Enabled; ++ break; ++ case 2: //WPA2 ++ padapter->securitypriv.ndisauthtype = Ndis802_11AuthModeWPA2PSK; //WPA2_PSK ++ padapter->securitypriv.ndisencryptstatus = Ndis802_11Encryption3Enabled; ++ break; ++ } ++ ++ RT_TRACE(_module_rtl871x_ioctl_os_c,_drv_info_,("wpa_set_param:padapter->securitypriv.ndisauthtype=%d\n", padapter->securitypriv.ndisauthtype)); ++ ++ break; ++ ++ case IEEE_PARAM_TKIP_COUNTERMEASURES: ++ //ieee->tkip_countermeasures=value; ++ break; ++ ++ case IEEE_PARAM_DROP_UNENCRYPTED: ++ { ++ /* HACK: ++ * ++ * wpa_supplicant calls set_wpa_enabled when the driver ++ * is loaded and unloaded, regardless of if WPA is being ++ * used. No other calls are made which can be used to ++ * determine if encryption will be used or not prior to ++ * association being expected. If encryption is not being ++ * used, drop_unencrypted is set to false, else true -- we ++ * can use this to determine if the CAP_PRIVACY_ON bit should ++ * be set. ++ */ ++ ++#if 0 ++ struct ieee80211_security sec = { ++ .flags = SEC_ENABLED, ++ .enabled = value, ++ }; ++ ieee->drop_unencrypted = value; ++ /* We only change SEC_LEVEL for open mode. Others ++ * are set by ipw_wpa_set_encryption. ++ */ ++ if (!value) { ++ sec.flags |= SEC_LEVEL; ++ sec.level = SEC_LEVEL_0; ++ } ++ else { ++ sec.flags |= SEC_LEVEL; ++ sec.level = SEC_LEVEL_1; ++ } ++ if (ieee->set_security) ++ ieee->set_security(ieee->dev, &sec); ++#endif ++ break; ++ ++ } ++ case IEEE_PARAM_PRIVACY_INVOKED: ++ ++ //ieee->privacy_invoked=value; ++ ++ break; ++ ++ case IEEE_PARAM_AUTH_ALGS: ++ ++ ret = wpa_set_auth_algs(dev, value); ++ ++ break; ++ ++ case IEEE_PARAM_IEEE_802_1X: ++ ++ //ieee->ieee802_1x=value; ++ ++ break; ++ ++ case IEEE_PARAM_WPAX_SELECT: ++ ++ // added for WPA2 mixed mode ++ //DBG_8192C(KERN_WARNING "------------------------>wpax value = %x\n", value); ++ /* ++ spin_lock_irqsave(&ieee->wpax_suitlist_lock,flags); ++ ieee->wpax_type_set = 1; ++ ieee->wpax_type_notify = value; ++ spin_unlock_irqrestore(&ieee->wpax_suitlist_lock,flags); ++ */ ++ ++ break; ++ ++ default: ++ ++ ++ ++ ret = -EOPNOTSUPP; ++ ++ ++ break; ++ ++ } ++ ++ return ret; ++ ++} ++ ++static int wpa_mlme(struct net_device *dev, u32 command, u32 reason) ++{ ++ int ret = 0; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ ++ switch (command) ++ { ++ case IEEE_MLME_STA_DEAUTH: ++ ++ if(!rtw_set_802_11_disassociate(padapter)) ++ ret = -1; ++ ++ break; ++ ++ case IEEE_MLME_STA_DISASSOC: ++ ++ if(!rtw_set_802_11_disassociate(padapter)) ++ ret = -1; ++ ++ break; ++ ++ default: ++ ret = -EOPNOTSUPP; ++ break; ++ } ++ ++ return ret; ++ ++} ++ ++static int wpa_supplicant_ioctl(struct net_device *dev, struct iw_point *p) ++{ ++ struct ieee_param *param; ++ uint ret=0; ++ ++ //down(&ieee->wx_sem); ++ ++ if (p->length < sizeof(struct ieee_param) || !p->pointer){ ++ ret = -EINVAL; ++ goto out; ++ } ++ ++ param = (struct ieee_param *)rtw_malloc(p->length); ++ if (param == NULL) ++ { ++ ret = -ENOMEM; ++ goto out; ++ } ++ ++ if (copy_from_user(param, p->pointer, p->length)) ++ { ++ rtw_mfree((u8*)param, p->length); ++ ret = -EFAULT; ++ goto out; ++ } ++ ++ switch (param->cmd) { ++ ++ case IEEE_CMD_SET_WPA_PARAM: ++ ret = wpa_set_param(dev, param->u.wpa_param.name, param->u.wpa_param.value); ++ break; ++ ++ case IEEE_CMD_SET_WPA_IE: ++ //ret = wpa_set_wpa_ie(dev, param, p->length); ++ ret = rtw_set_wpa_ie((_adapter *)rtw_netdev_priv(dev), (char*)param->u.wpa_ie.data, (u16)param->u.wpa_ie.len); ++ break; ++ ++ case IEEE_CMD_SET_ENCRYPTION: ++ ret = wpa_set_encryption(dev, param, p->length); ++ break; ++ ++ case IEEE_CMD_MLME: ++ ret = wpa_mlme(dev, param->u.mlme.command, param->u.mlme.reason_code); ++ break; ++ ++ default: ++ DBG_8192C("Unknown WPA supplicant request: %d\n", param->cmd); ++ ret = -EOPNOTSUPP; ++ break; ++ ++ } ++ ++ if (ret == 0 && copy_to_user(p->pointer, param, p->length)) ++ ret = -EFAULT; ++ ++ rtw_mfree((u8 *)param, p->length); ++ ++out: ++ ++ //up(&ieee->wx_sem); ++ ++ return ret; ++ ++} ++ ++#ifdef CONFIG_AP_MODE ++static u8 set_pairwise_key(_adapter *padapter, struct sta_info *psta) ++{ ++ struct cmd_obj* ph2c; ++ struct set_stakey_parm *psetstakey_para; ++ struct cmd_priv *pcmdpriv=&padapter->cmdpriv; ++ u8 res=_SUCCESS; ++ ++ ph2c = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj)); ++ if ( ph2c == NULL){ ++ res= _FAIL; ++ goto exit; ++ } ++ ++ psetstakey_para = (struct set_stakey_parm*)rtw_zmalloc(sizeof(struct set_stakey_parm)); ++ if(psetstakey_para==NULL){ ++ rtw_mfree((u8 *) ph2c, sizeof(struct cmd_obj)); ++ res=_FAIL; ++ goto exit; ++ } ++ ++ init_h2fwcmd_w_parm_no_rsp(ph2c, psetstakey_para, _SetStaKey_CMD_); ++ ++ ++ psetstakey_para->algorithm = (u8)psta->dot118021XPrivacy; ++ ++ _rtw_memcpy(psetstakey_para->addr, psta->hwaddr, ETH_ALEN); ++ ++ _rtw_memcpy(psetstakey_para->key, &psta->dot118021x_UncstKey, 16); ++ ++ ++ res = rtw_enqueue_cmd(pcmdpriv, ph2c); ++ ++exit: ++ ++ return res; ++ ++} ++ ++static int set_group_key(_adapter *padapter, u8 *key, u8 alg, int keyid) ++{ ++ u8 keylen; ++ struct cmd_obj* pcmd; ++ struct setkey_parm *psetkeyparm; ++ struct cmd_priv *pcmdpriv=&(padapter->cmdpriv); ++ int res=_SUCCESS; ++ ++ DBG_8192C("%s\n", __FUNCTION__); ++ ++ pcmd = (struct cmd_obj*)rtw_zmalloc(sizeof(struct cmd_obj)); ++ if(pcmd==NULL){ ++ res= _FAIL; ++ goto exit; ++ } ++ psetkeyparm=(struct setkey_parm*)rtw_zmalloc(sizeof(struct setkey_parm)); ++ if(psetkeyparm==NULL){ ++ rtw_mfree((unsigned char *)pcmd, sizeof(struct cmd_obj)); ++ res= _FAIL; ++ goto exit; ++ } ++ ++ _rtw_memset(psetkeyparm, 0, sizeof(struct setkey_parm)); ++ ++ psetkeyparm->keyid=(u8)keyid; ++ ++ psetkeyparm->algorithm = alg; ++ ++ psetkeyparm->set_tx = 1; ++ ++ switch(alg) ++ { ++ case _WEP40_: ++ keylen = 5; ++ break; ++ case _WEP104_: ++ keylen = 13; ++ break; ++ case _TKIP_: ++ case _TKIP_WTMIC_: ++ case _AES_: ++ keylen = 16; ++ default: ++ keylen = 16; ++ } ++ ++ _rtw_memcpy(&(psetkeyparm->key[0]), key, keylen); ++ ++ pcmd->cmdcode = _SetKey_CMD_; ++ pcmd->parmbuf = (u8 *)psetkeyparm; ++ pcmd->cmdsz = (sizeof(struct setkey_parm)); ++ pcmd->rsp = NULL; ++ pcmd->rspsz = 0; ++ ++ ++ _rtw_init_listhead(&pcmd->list); ++ ++ res = rtw_enqueue_cmd(pcmdpriv, pcmd); ++ ++exit: ++ ++ return res; ++ ++ ++} ++ ++static int set_wep_key(_adapter *padapter, u8 *key, u8 keylen, int keyid) ++{ ++ u8 alg; ++ ++ switch(keylen) ++ { ++ case 5: ++ alg =_WEP40_; ++ break; ++ case 13: ++ alg =_WEP104_; ++ break; ++ default: ++ alg =_NO_PRIVACY_; ++ } ++ ++ return set_group_key(padapter, key, alg, keyid); ++ ++} ++ ++ ++static int rtw_set_encryption(struct net_device *dev, struct ieee_param *param, u32 param_len) ++{ ++ int ret = 0; ++ u32 wep_key_idx, wep_key_len,wep_total_len; ++ NDIS_802_11_WEP *pwep = NULL; ++ struct sta_info *psta = NULL, *pbcmc_sta = NULL; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct security_priv* psecuritypriv=&(padapter->securitypriv); ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ ++ DBG_8192C("%s\n", __FUNCTION__); ++ ++ param->u.crypt.err = 0; ++ param->u.crypt.alg[IEEE_CRYPT_ALG_NAME_LEN - 1] = '\0'; ++ ++ //sizeof(struct ieee_param) = 64 bytes; ++ //if (param_len != (u32) ((u8 *) param->u.crypt.key - (u8 *) param) + param->u.crypt.key_len) ++ if (param_len != sizeof(struct ieee_param) + param->u.crypt.key_len) ++ { ++ ret = -EINVAL; ++ goto exit; ++ } ++ ++ if (param->sta_addr[0] == 0xff && param->sta_addr[1] == 0xff && ++ param->sta_addr[2] == 0xff && param->sta_addr[3] == 0xff && ++ param->sta_addr[4] == 0xff && param->sta_addr[5] == 0xff) ++ { ++ if (param->u.crypt.idx >= WEP_KEYS) ++ { ++ ret = -EINVAL; ++ goto exit; ++ } ++ } ++ else ++ { ++ psta = rtw_get_stainfo(pstapriv, param->sta_addr); ++ if(!psta) ++ { ++ //ret = -EINVAL; ++ DBG_8192C("rtw_set_encryption(), sta has already been removed or never been added\n"); ++ goto exit; ++ } ++ } ++ ++ if (strcmp(param->u.crypt.alg, "none") == 0 && (psta==NULL)) ++ { ++ //todo:clear default encryption keys ++ ++ DBG_8192C("clear default encryption keys, keyid=%d\n", param->u.crypt.idx); ++ ++ goto exit; ++ } ++ ++ ++ if (strcmp(param->u.crypt.alg, "WEP") == 0 && (psta==NULL)) ++ { ++ DBG_8192C("r871x_set_encryption, crypt.alg = WEP\n"); ++ ++ wep_key_idx = param->u.crypt.idx; ++ wep_key_len = param->u.crypt.key_len; ++ ++ DBG_8192C("r871x_set_encryption, wep_key_idx=%d, len=%d\n", wep_key_idx, wep_key_len); ++ ++ if((wep_key_idx >= WEP_KEYS) || (wep_key_len<=0)) ++ { ++ ret = -EINVAL; ++ goto exit; ++ } ++ ++ ++ if (wep_key_len > 0) ++ { ++ wep_key_len = wep_key_len <= 5 ? 5 : 13; ++ wep_total_len = wep_key_len + FIELD_OFFSET(NDIS_802_11_WEP, KeyMaterial); ++ pwep =(NDIS_802_11_WEP *)rtw_malloc(wep_total_len); ++ if(pwep == NULL){ ++ DBG_8192C(" r871x_set_encryption: pwep allocate fail !!!\n"); ++ goto exit; ++ } ++ ++ _rtw_memset(pwep, 0, wep_total_len); ++ ++ pwep->KeyLength = wep_key_len; ++ pwep->Length = wep_total_len; ++ ++ } ++ ++ pwep->KeyIndex = wep_key_idx; ++ ++ _rtw_memcpy(pwep->KeyMaterial, param->u.crypt.key, pwep->KeyLength); ++ ++ if(param->u.crypt.set_tx) ++ { ++ DBG_8192C("wep, set_tx=1\n"); ++ ++ psecuritypriv->ndisencryptstatus = Ndis802_11Encryption1Enabled; ++ psecuritypriv->dot11PrivacyAlgrthm=_WEP40_; ++ psecuritypriv->dot118021XGrpPrivacy=_WEP40_; ++ ++ if(pwep->KeyLength==13) ++ { ++ psecuritypriv->dot11PrivacyAlgrthm=_WEP104_; ++ psecuritypriv->dot118021XGrpPrivacy=_WEP104_; ++ } ++ ++ ++ psecuritypriv->dot11PrivacyKeyIndex = wep_key_idx; ++ ++ _rtw_memcpy(&(psecuritypriv->dot11DefKey[wep_key_idx].skey[0]), pwep->KeyMaterial, pwep->KeyLength); ++ ++ psecuritypriv->dot11DefKeylen[wep_key_idx]=pwep->KeyLength; ++ ++ set_wep_key(padapter, pwep->KeyMaterial, pwep->KeyLength, wep_key_idx); ++ ++ ++ } ++ else ++ { ++ DBG_8192C("wep, set_tx=0\n"); ++ ++ //don't update "psecuritypriv->dot11PrivacyAlgrthm" and ++ //"psecuritypriv->dot11PrivacyKeyIndex=keyid", but can rtw_set_key to cam ++ ++ _rtw_memcpy(&(psecuritypriv->dot11DefKey[wep_key_idx].skey[0]), pwep->KeyMaterial, pwep->KeyLength); ++ ++ psecuritypriv->dot11DefKeylen[wep_key_idx] = pwep->KeyLength; ++ ++ set_wep_key(padapter, pwep->KeyMaterial, pwep->KeyLength, wep_key_idx); ++ ++ } ++ ++ goto exit; ++ ++ } ++ ++ ++ if(!psta && check_fwstate(pmlmepriv, WIFI_AP_STATE)) // //group key ++ { ++ if(param->u.crypt.set_tx ==1) ++ { ++ if(strcmp(param->u.crypt.alg, "WEP") == 0) ++ { ++ DBG_8192C("%s, set group_key, WEP\n", __FUNCTION__); ++ ++ _rtw_memcpy(psecuritypriv->dot118021XGrpKey[param->u.crypt.idx].skey, param->u.crypt.key, (param->u.crypt.key_len>16 ?16:param->u.crypt.key_len)); ++ ++ psecuritypriv->dot118021XGrpPrivacy = _WEP40_; ++ if(param->u.crypt.key_len==13) ++ { ++ psecuritypriv->dot118021XGrpPrivacy = _WEP104_; ++ } ++ ++ } ++ else if(strcmp(param->u.crypt.alg, "TKIP") == 0) ++ { ++ DBG_8192C("%s, set group_key, TKIP\n", __FUNCTION__); ++ ++ psecuritypriv->dot118021XGrpPrivacy = _TKIP_; ++ ++ _rtw_memcpy(psecuritypriv->dot118021XGrpKey[param->u.crypt.idx].skey, param->u.crypt.key, (param->u.crypt.key_len>16 ?16:param->u.crypt.key_len)); ++ ++ //DEBUG_ERR("set key length :param->u.crypt.key_len=%d\n", param->u.crypt.key_len); ++ //set mic key ++ _rtw_memcpy(psecuritypriv->dot118021XGrptxmickey[param->u.crypt.idx].skey, &(param->u.crypt.key[16]), 8); ++ _rtw_memcpy(psecuritypriv->dot118021XGrprxmickey[param->u.crypt.idx].skey, &(param->u.crypt.key[24]), 8); ++ ++ psecuritypriv->busetkipkey = _TRUE; ++ ++ } ++ else if(strcmp(param->u.crypt.alg, "CCMP") == 0) ++ { ++ DBG_8192C("%s, set group_key, CCMP\n", __FUNCTION__); ++ ++ psecuritypriv->dot118021XGrpPrivacy = _AES_; ++ ++ _rtw_memcpy(psecuritypriv->dot118021XGrpKey[param->u.crypt.idx].skey, param->u.crypt.key, (param->u.crypt.key_len>16 ?16:param->u.crypt.key_len)); ++ } ++ else ++ { ++ DBG_8192C("%s, set group_key, none\n", __FUNCTION__); ++ ++ psecuritypriv->dot118021XGrpPrivacy = _NO_PRIVACY_; ++ } ++ ++ psecuritypriv->dot118021XGrpKeyid = param->u.crypt.idx; ++ ++ psecuritypriv->binstallGrpkey = _TRUE; ++ ++ psecuritypriv->dot11PrivacyAlgrthm = psecuritypriv->dot118021XGrpPrivacy;//!!! ++ ++ set_group_key(padapter, param->u.crypt.key, psecuritypriv->dot118021XGrpPrivacy, param->u.crypt.idx); ++ ++ pbcmc_sta=rtw_get_bcmc_stainfo(padapter); ++ if(pbcmc_sta) ++ { ++ pbcmc_sta->ieee8021x_blocked = _FALSE; ++ pbcmc_sta->dot118021XPrivacy= psecuritypriv->dot118021XGrpPrivacy;//rx will use bmc_sta's dot118021XPrivacy ++ } ++ ++ } ++ ++ goto exit; ++ ++ } ++ ++ if(psecuritypriv->dot11AuthAlgrthm == dot11AuthAlgrthm_8021X && psta) // psk/802_1x ++ { ++ if(check_fwstate(pmlmepriv, WIFI_AP_STATE)) ++ { ++ if(param->u.crypt.set_tx ==1) ++ { ++ _rtw_memcpy(psta->dot118021x_UncstKey.skey, param->u.crypt.key, (param->u.crypt.key_len>16 ?16:param->u.crypt.key_len)); ++ ++ if(strcmp(param->u.crypt.alg, "WEP") == 0) ++ { ++ DBG_8192C("%s, set pairwise key, WEP\n", __FUNCTION__); ++ ++ psta->dot118021XPrivacy = _WEP40_; ++ if(param->u.crypt.key_len==13) ++ { ++ psta->dot118021XPrivacy = _WEP104_; ++ } ++ } ++ else if(strcmp(param->u.crypt.alg, "TKIP") == 0) ++ { ++ DBG_8192C("%s, set pairwise key, TKIP\n", __FUNCTION__); ++ ++ psta->dot118021XPrivacy = _TKIP_; ++ ++ //DEBUG_ERR("set key length :param->u.crypt.key_len=%d\n", param->u.crypt.key_len); ++ //set mic key ++ _rtw_memcpy(psta->dot11tkiptxmickey.skey, &(param->u.crypt.key[16]), 8); ++ _rtw_memcpy(psta->dot11tkiprxmickey.skey, &(param->u.crypt.key[24]), 8); ++ ++ psecuritypriv->busetkipkey = _TRUE; ++ ++ } ++ else if(strcmp(param->u.crypt.alg, "CCMP") == 0) ++ { ++ ++ DBG_8192C("%s, set pairwise key, CCMP\n", __FUNCTION__); ++ ++ psta->dot118021XPrivacy = _AES_; ++ } ++ else ++ { ++ DBG_8192C("%s, set pairwise key, none\n", __FUNCTION__); ++ ++ psta->dot118021XPrivacy = _NO_PRIVACY_; ++ } ++ ++ set_pairwise_key(padapter, psta); ++ ++ psta->ieee8021x_blocked = _FALSE; ++ ++ } ++ else//group key??? ++ { ++ if(strcmp(param->u.crypt.alg, "WEP") == 0) ++ { ++ _rtw_memcpy(psecuritypriv->dot118021XGrpKey[param->u.crypt.idx].skey, param->u.crypt.key, (param->u.crypt.key_len>16 ?16:param->u.crypt.key_len)); ++ ++ psecuritypriv->dot118021XGrpPrivacy = _WEP40_; ++ if(param->u.crypt.key_len==13) ++ { ++ psecuritypriv->dot118021XGrpPrivacy = _WEP104_; ++ } ++ } ++ else if(strcmp(param->u.crypt.alg, "TKIP") == 0) ++ { ++ psecuritypriv->dot118021XGrpPrivacy = _TKIP_; ++ ++ _rtw_memcpy(psecuritypriv->dot118021XGrpKey[param->u.crypt.idx].skey, param->u.crypt.key, (param->u.crypt.key_len>16 ?16:param->u.crypt.key_len)); ++ ++ //DEBUG_ERR("set key length :param->u.crypt.key_len=%d\n", param->u.crypt.key_len); ++ //set mic key ++ _rtw_memcpy(psecuritypriv->dot118021XGrptxmickey[param->u.crypt.idx].skey, &(param->u.crypt.key[16]), 8); ++ _rtw_memcpy(psecuritypriv->dot118021XGrprxmickey[param->u.crypt.idx].skey, &(param->u.crypt.key[24]), 8); ++ ++ psecuritypriv->busetkipkey = _TRUE; ++ ++ } ++ else if(strcmp(param->u.crypt.alg, "CCMP") == 0) ++ { ++ psecuritypriv->dot118021XGrpPrivacy = _AES_; ++ ++ _rtw_memcpy(psecuritypriv->dot118021XGrpKey[param->u.crypt.idx].skey, param->u.crypt.key, (param->u.crypt.key_len>16 ?16:param->u.crypt.key_len)); ++ } ++ else ++ { ++ psecuritypriv->dot118021XGrpPrivacy = _NO_PRIVACY_; ++ } ++ ++ psecuritypriv->dot118021XGrpKeyid = param->u.crypt.idx; ++ ++ psecuritypriv->binstallGrpkey = _TRUE; ++ ++ psecuritypriv->dot11PrivacyAlgrthm = psecuritypriv->dot118021XGrpPrivacy;//!!! ++ ++ set_group_key(padapter, param->u.crypt.key, psecuritypriv->dot118021XGrpPrivacy, param->u.crypt.idx); ++ ++ pbcmc_sta=rtw_get_bcmc_stainfo(padapter); ++ if(pbcmc_sta) ++ { ++ pbcmc_sta->ieee8021x_blocked = _FALSE; ++ pbcmc_sta->dot118021XPrivacy= psecuritypriv->dot118021XGrpPrivacy;//rx will use bmc_sta's dot118021XPrivacy ++ } ++ ++ } ++ ++ } ++ ++ } ++ ++exit: ++ ++ if(pwep) ++ { ++ rtw_mfree((u8 *)pwep, wep_total_len); ++ } ++ ++ return ret; ++ ++} ++ ++static int rtw_set_beacon(struct net_device *dev, struct ieee_param *param, int len) ++{ ++ int ret=0; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ unsigned char *pbuf = param->u.bcn_ie.buf; ++ ++ ++ DBG_8192C("%s, len=%d\n", __FUNCTION__, len); ++ ++ if(check_fwstate(pmlmepriv, WIFI_AP_STATE) != _TRUE) ++ return -EINVAL; ++ ++ _rtw_memcpy(&pstapriv->max_num_sta, param->u.bcn_ie.reserved, 2); ++#ifdef SUPPORT_64_STA ++ pstapriv->max_num_sta = NUM_STA; ++#else //SUPPORT_64_STA ++ if((pstapriv->max_num_sta>NUM_STA) || (pstapriv->max_num_sta<=0)) ++ pstapriv->max_num_sta = NUM_STA; ++#endif//SUPPORT_64_STA ++ ++ if(rtw_check_beacon_data(padapter, pbuf, (len-12-2)) == _SUCCESS)// 12 = param header, 2:no packed ++ ret = 0; ++ else ++ ret = -EINVAL; ++ ++ ++ return ret; ++ ++} ++ ++static int rtw_hostapd_sta_flush(struct net_device *dev) ++{ ++ //_irqL irqL; ++ //_list *phead, *plist; ++ int ret=0; ++ //struct sta_info *psta = NULL; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ //struct sta_priv *pstapriv = &padapter->stapriv; ++ ++ DBG_8192C("%s\n", __FUNCTION__); ++ ++ flush_all_cam_entry(padapter); //clear CAM ++ ++#if 0 ++ phead = &pstapriv->asoc_list; ++ plist = get_next(phead); ++ ++ //free sta asoc_queue ++ while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) ++ { ++ psta = LIST_CONTAINOR(plist, struct sta_info, asoc_list); ++ ++ plist = get_next(plist); ++ ++ rtw_list_delete(&psta->asoc_list); ++ ++ //tear down Rx AMPDU ++ send_delba(padapter, 0, psta->hwaddr);// recipient ++ ++ //tear down TX AMPDU ++ send_delba(padapter, 1, psta->hwaddr);// // originator ++ psta->htpriv.agg_enable_bitmap = 0x0;//reset ++ psta->htpriv.candidate_tid_bitmap = 0x0;//reset ++ ++ issue_deauth(padapter, psta->hwaddr, WLAN_REASON_DEAUTH_LEAVING); ++ ++ _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL); ++ rtw_free_stainfo(padapter, psta); ++ _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL); ++ ++ } ++#endif ++ ++ ret = rtw_sta_flush(padapter); ++ ++ return ret; ++ ++} ++ ++static int rtw_add_sta(struct net_device *dev, struct ieee_param *param) ++{ ++ _irqL irqL; ++ int ret=0; ++ struct sta_info *psta = NULL; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ ++ DBG_8192C("rtw_add_sta(aid=%d)=" MAC_FMT "\n", param->u.add_sta.aid, MAC_ARG(param->sta_addr)); ++ ++ if(check_fwstate(pmlmepriv, (_FW_LINKED|WIFI_AP_STATE)) != _TRUE) ++ { ++ return -EINVAL; ++ } ++ ++ if (param->sta_addr[0] == 0xff && param->sta_addr[1] == 0xff && ++ param->sta_addr[2] == 0xff && param->sta_addr[3] == 0xff && ++ param->sta_addr[4] == 0xff && param->sta_addr[5] == 0xff) ++ { ++ return -EINVAL; ++ } ++ ++/* ++ psta = rtw_get_stainfo(pstapriv, param->sta_addr); ++ if(psta) ++ { ++ DBG_8192C("rtw_add_sta(), free has been added psta=%p\n", psta); ++ _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL); ++ rtw_free_stainfo(padapter, psta); ++ _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL); ++ ++ psta = NULL; ++ } ++*/ ++ //psta = rtw_alloc_stainfo(pstapriv, param->sta_addr); ++ psta = rtw_get_stainfo(pstapriv, param->sta_addr); ++ if(psta) ++ { ++ int flags = param->u.add_sta.flags; ++ ++ //DBG_8192C("rtw_add_sta(), init sta's variables, psta=%p\n", psta); ++ ++ psta->aid = param->u.add_sta.aid;//aid=1~2007 ++ ++ _rtw_memcpy(psta->bssrateset, param->u.add_sta.tx_supp_rates, 16); ++ ++ ++ //check wmm cap. ++ if(WLAN_STA_WME&flags) ++ psta->qos_option = 1; ++ else ++ psta->qos_option = 0; ++ ++ if(pmlmepriv->qospriv.qos_option == 0) ++ psta->qos_option = 0; ++ ++ ++#ifdef CONFIG_80211N_HT ++ //chec 802.11n ht cap. ++ if(WLAN_STA_HT&flags) ++ { ++ psta->htpriv.ht_option = _TRUE; ++ psta->qos_option = 1; ++ _rtw_memcpy((void*)&psta->htpriv.ht_cap, (void*)¶m->u.add_sta.ht_cap, sizeof(struct rtw_ieee80211_ht_cap)); ++ } ++ else ++ { ++ psta->htpriv.ht_option = _FALSE; ++ } ++ ++ if(pmlmepriv->htpriv.ht_option == _FALSE) ++ psta->htpriv.ht_option = _FALSE; ++#endif ++ ++ ++ update_sta_info_apmode(padapter, psta); ++ ++ ++ } ++ else ++ { ++ ret = -ENOMEM; ++ } ++ ++ return ret; ++ ++} ++ ++static int rtw_del_sta(struct net_device *dev, struct ieee_param *param) ++{ ++ _irqL irqL; ++ int ret=0; ++ struct sta_info *psta = NULL; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ ++ DBG_8192C("rtw_del_sta=" MAC_FMT "\n", MAC_ARG(param->sta_addr)); ++ ++ if(check_fwstate(pmlmepriv, (_FW_LINKED|WIFI_AP_STATE)) != _TRUE) ++ { ++ return -EINVAL; ++ } ++ ++ if (param->sta_addr[0] == 0xff && param->sta_addr[1] == 0xff && ++ param->sta_addr[2] == 0xff && param->sta_addr[3] == 0xff && ++ param->sta_addr[4] == 0xff && param->sta_addr[5] == 0xff) ++ { ++ return -EINVAL; ++ } ++ ++ psta = rtw_get_stainfo(pstapriv, param->sta_addr); ++ if(psta) ++ { ++ //DBG_8192C("free psta=%p, aid=%d\n", psta, psta->aid); ++ ++#if 0 ++ //tear down Rx AMPDU ++ send_delba(padapter, 0, psta->hwaddr);// recipient ++ ++ //tear down TX AMPDU ++ send_delba(padapter, 1, psta->hwaddr);// // originator ++ psta->htpriv.agg_enable_bitmap = 0x0;//reset ++ psta->htpriv.candidate_tid_bitmap = 0x0;//reset ++ ++ issue_deauth(padapter, psta->hwaddr, WLAN_REASON_DEAUTH_LEAVING); ++ ++ _enter_critical_bh(&(pstapriv->sta_hash_lock), &irqL); ++ rtw_free_stainfo(padapter, psta); ++ _exit_critical_bh(&(pstapriv->sta_hash_lock), &irqL); ++ ++ pstapriv->sta_dz_bitmap &=~BIT(psta->aid); ++ pstapriv->tim_bitmap &=~BIT(psta->aid); ++#endif ++ ++ _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL); ++ if(rtw_is_list_empty(&psta->asoc_list)==_FALSE) ++ { ++ rtw_list_delete(&psta->asoc_list); ++ ap_free_sta(padapter, psta); ++ ++ } ++ _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL); ++ ++ psta = NULL; ++ ++ } ++ else ++ { ++ DBG_8192C("rtw_del_sta(), sta has already been removed or never been added\n"); ++ ++ //ret = -1; ++ } ++ ++ ++ return ret; ++ ++} ++ ++static int rtw_get_sta_wpaie(struct net_device *dev, struct ieee_param *param) ++{ ++ int ret=0; ++ struct sta_info *psta = NULL; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ ++ DBG_8192C("rtw_get_sta_wpaie, sta_addr: " MAC_FMT "\n", MAC_ARG(param->sta_addr)); ++ ++ if(check_fwstate(pmlmepriv, (_FW_LINKED|WIFI_AP_STATE)) != _TRUE) ++ { ++ return -EINVAL; ++ } ++ ++ if (param->sta_addr[0] == 0xff && param->sta_addr[1] == 0xff && ++ param->sta_addr[2] == 0xff && param->sta_addr[3] == 0xff && ++ param->sta_addr[4] == 0xff && param->sta_addr[5] == 0xff) ++ { ++ return -EINVAL; ++ } ++ ++ psta = rtw_get_stainfo(pstapriv, param->sta_addr); ++ if(psta) ++ { ++ if((psta->wpa_ie[0] == WLAN_EID_RSN) || (psta->wpa_ie[0] == WLAN_EID_GENERIC)) ++ { ++ int wpa_ie_len; ++ int copy_len; ++ ++ wpa_ie_len = psta->wpa_ie[1]; ++ ++ copy_len = ((wpa_ie_len+2) > sizeof(psta->wpa_ie)) ? (sizeof(psta->wpa_ie)):(wpa_ie_len+2); ++ ++ param->u.wpa_ie.len = copy_len; ++ ++ _rtw_memcpy(param->u.wpa_ie.reserved, psta->wpa_ie, copy_len); ++ } ++ else ++ { ++ //ret = -1; ++ DBG_8192C("sta's wpa_ie is NONE\n"); ++ } ++ } ++ else ++ { ++ ret = -1; ++ } ++ ++ return ret; ++ ++} ++ ++static int rtw_set_wps_beacon(struct net_device *dev, struct ieee_param *param, int len) ++{ ++ int ret=0; ++ unsigned char wps_oui[4]={0x0,0x50,0xf2,0x04}; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ int ie_len; ++ ++ DBG_8192C("%s, len=%d\n", __FUNCTION__, len); ++ ++ if(check_fwstate(pmlmepriv, WIFI_AP_STATE) != _TRUE) ++ return -EINVAL; ++ ++ ie_len = len-12-2;// 12 = param header, 2:no packed ++ ++ ++ if(pmlmepriv->wps_beacon_ie) ++ { ++ rtw_mfree(pmlmepriv->wps_beacon_ie, pmlmepriv->wps_beacon_ie_len); ++ pmlmepriv->wps_beacon_ie = NULL; ++ } ++ ++ if(ie_len>0) ++ { ++ pmlmepriv->wps_beacon_ie = rtw_malloc(ie_len); ++ pmlmepriv->wps_beacon_ie_len = ie_len; ++ if ( pmlmepriv->wps_beacon_ie == NULL) { ++ DBG_8192C("%s()-%d: rtw_malloc() ERROR!\n", __FUNCTION__, __LINE__); ++ return -EINVAL; ++ } ++ ++ _rtw_memcpy(pmlmepriv->wps_beacon_ie, param->u.bcn_ie.buf, ie_len); ++ ++ update_beacon(padapter, _VENDOR_SPECIFIC_IE_, wps_oui, _TRUE); ++ ++ pmlmeext->bstart_bss = _TRUE; ++ ++ } ++ ++ ++ return ret; ++ ++} ++ ++static int rtw_set_wps_probe_resp(struct net_device *dev, struct ieee_param *param, int len) ++{ ++ int ret=0; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ int ie_len; ++ ++ DBG_8192C("%s, len=%d\n", __FUNCTION__, len); ++ ++ if(check_fwstate(pmlmepriv, WIFI_AP_STATE) != _TRUE) ++ return -EINVAL; ++ ++ ie_len = len-12-2;// 12 = param header, 2:no packed ++ ++ ++ if(pmlmepriv->wps_probe_resp_ie) ++ { ++ rtw_mfree(pmlmepriv->wps_probe_resp_ie, pmlmepriv->wps_probe_resp_ie_len); ++ pmlmepriv->wps_probe_resp_ie = NULL; ++ } ++ ++ if(ie_len>0) ++ { ++ pmlmepriv->wps_probe_resp_ie = rtw_malloc(ie_len); ++ pmlmepriv->wps_probe_resp_ie_len = ie_len; ++ if ( pmlmepriv->wps_probe_resp_ie == NULL) { ++ DBG_8192C("%s()-%d: rtw_malloc() ERROR!\n", __FUNCTION__, __LINE__); ++ return -EINVAL; ++ } ++ _rtw_memcpy(pmlmepriv->wps_probe_resp_ie, param->u.bcn_ie.buf, ie_len); ++ } ++ ++ ++ return ret; ++ ++} ++ ++static int rtw_set_hidden_ssid(struct net_device *dev, struct ieee_param *param, int len) ++{ ++ int ret=0; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ ++ u8 value; ++ ++ if(check_fwstate(pmlmepriv, WIFI_AP_STATE) != _TRUE) ++ return -EINVAL; ++ ++ if(param->u.wpa_param.name != 0) //dummy test... ++ { ++ DBG_871X("%s name(%u) != 0\n", __FUNCTION__, param->u.wpa_param.name); ++ } ++ ++ value = param->u.wpa_param.value; ++ ++ //use the same definition of hostapd's ignore_broadcast_ssid ++ if(value != 1 && value != 2) ++ value = 0; ++ ++ DBG_871X("%s value(%u)\n", __FUNCTION__, value); ++ pmlmeinfo->hidden_ssid_mode = value; ++ ++ return ret; ++ ++} ++ ++ ++static int rtw_set_wps_assoc_resp(struct net_device *dev, struct ieee_param *param, int len) ++{ ++ int ret=0; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ int ie_len; ++ ++ DBG_8192C("%s, len=%d\n", __FUNCTION__, len); ++ ++ if(check_fwstate(pmlmepriv, WIFI_AP_STATE) != _TRUE) ++ return -EINVAL; ++ ++ ie_len = len-12-2;// 12 = param header, 2:no packed ++ ++ ++ if(pmlmepriv->wps_assoc_resp_ie) ++ { ++ rtw_mfree(pmlmepriv->wps_assoc_resp_ie, pmlmepriv->wps_assoc_resp_ie_len); ++ pmlmepriv->wps_assoc_resp_ie = NULL; ++ } ++ ++ if(ie_len>0) ++ { ++ pmlmepriv->wps_assoc_resp_ie = rtw_malloc(ie_len); ++ pmlmepriv->wps_assoc_resp_ie_len = ie_len; ++ if ( pmlmepriv->wps_assoc_resp_ie == NULL) { ++ DBG_8192C("%s()-%d: rtw_malloc() ERROR!\n", __FUNCTION__, __LINE__); ++ return -EINVAL; ++ } ++ ++ _rtw_memcpy(pmlmepriv->wps_assoc_resp_ie, param->u.bcn_ie.buf, ie_len); ++ } ++ ++ ++ return ret; ++ ++} ++ ++static int rtw_hostapd_ioctl(struct net_device *dev, struct iw_point *p) ++{ ++ struct ieee_param *param; ++ int ret=0; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ ++ //DBG_8192C("%s\n", __FUNCTION__); ++ ++ /* ++ * this function is expect to call in master mode, which allows no power saving ++ * so, we just check hw_init_completed instead of call rfpwrstate_check() ++ */ ++ ++ if (padapter->hw_init_completed==_FALSE){ ++ ret = -EPERM; ++ goto out; ++ } ++ ++ ++ //if (p->length < sizeof(struct ieee_param) || !p->pointer){ ++ if(!p->pointer){ ++ ret = -EINVAL; ++ goto out; ++ } ++ ++ param = (struct ieee_param *)rtw_malloc(p->length); ++ if (param == NULL) ++ { ++ ret = -ENOMEM; ++ goto out; ++ } ++ ++ if (copy_from_user(param, p->pointer, p->length)) ++ { ++ rtw_mfree((u8*)param, p->length); ++ ret = -EFAULT; ++ goto out; ++ } ++ ++ //DBG_8192C("%s, cmd=%d\n", __FUNCTION__, param->cmd); ++ ++ switch (param->cmd) ++ { ++ case RTL871X_HOSTAPD_FLUSH: ++ ++ ret = rtw_hostapd_sta_flush(dev); ++ ++ break; ++ ++ case RTL871X_HOSTAPD_ADD_STA: ++ ++ ret = rtw_add_sta(dev, param); ++ ++ break; ++ ++ case RTL871X_HOSTAPD_REMOVE_STA: ++ ++ ret = rtw_del_sta(dev, param); ++ ++ break; ++ ++ case RTL871X_HOSTAPD_SET_BEACON: ++ ++ ret = rtw_set_beacon(dev, param, p->length); ++ ++ break; ++ ++ case RTL871X_SET_ENCRYPTION: ++ ++ ret = rtw_set_encryption(dev, param, p->length); ++ ++ break; ++ ++ case RTL871X_HOSTAPD_GET_WPAIE_STA: ++ ++ ret = rtw_get_sta_wpaie(dev, param); ++ ++ break; ++ ++ case RTL871X_HOSTAPD_SET_WPS_BEACON: ++ ++ ret = rtw_set_wps_beacon(dev, param, p->length); ++ ++ break; ++ ++ case RTL871X_HOSTAPD_SET_WPS_PROBE_RESP: ++ ++ ret = rtw_set_wps_probe_resp(dev, param, p->length); ++ ++ break; ++ ++ case RTL871X_HOSTAPD_SET_WPS_ASSOC_RESP: ++ ++ ret = rtw_set_wps_assoc_resp(dev, param, p->length); ++ ++ break; ++ ++ case RTL871X_HOSTAPD_SET_HIDDEN_SSID: ++ ++ ret = rtw_set_hidden_ssid(dev, param, p->length); ++ ++ break; ++ ++ default: ++ DBG_8192C("Unknown hostapd request: %d\n", param->cmd); ++ ret = -EOPNOTSUPP; ++ break; ++ ++ } ++ ++ if (ret == 0 && copy_to_user(p->pointer, param, p->length)) ++ ret = -EFAULT; ++ ++ ++ rtw_mfree((u8 *)param, p->length); ++ ++out: ++ ++ return ret; ++ ++} ++#endif ++ ++#include ++static int rtw_wx_set_priv(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *awrq, ++ char *extra) ++{ ++ ++#ifdef CONFIG_DEBUG_RTW_WX_SET_PRIV ++ char *ext_dbg; ++#endif ++ ++ int ret = 0; ++ int len = 0; ++ char *ext; ++ int i; ++ ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct iw_point *dwrq = (struct iw_point*)awrq; ++ ++ //RT_TRACE(_module_rtl871x_ioctl_os_c, _drv_notice_, ("+rtw_wx_set_priv\n")); ++ ++ len = dwrq->length; ++ if (!(ext = rtw_vmalloc(len))) ++ return -ENOMEM; ++ ++ if (copy_from_user(ext, dwrq->pointer, len)) { ++ rtw_vmfree(ext, len); ++ return -EFAULT; ++ } ++ ++ ++ //RT_TRACE(_module_rtl871x_ioctl_os_c, _drv_notice_, ++ // ("rtw_wx_set_priv: %s req=%s\n", ++ // dev->name, ext)); ++ ++ #ifdef CONFIG_DEBUG_RTW_WX_SET_PRIV ++ if (!(ext_dbg = rtw_vmalloc(len))) ++ { ++ rtw_vmfree(ext, len); ++ return -ENOMEM; ++ } ++ ++ _rtw_memcpy(ext_dbg, ext, len); ++ #endif ++ ++ //added for wps2.0 @20110524 ++ if(dwrq->flags == 0x8766 && len > 8) ++ { ++ u32 cp_sz; ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ u8 *probereq_wpsie = ext; ++ int probereq_wpsie_len = len; ++ u8 wps_oui[4]={0x0,0x50,0xf2,0x04}; ++ ++ if((_VENDOR_SPECIFIC_IE_ == probereq_wpsie[0]) && ++ (_rtw_memcmp(&probereq_wpsie[2], wps_oui, 4) ==_TRUE)) ++ { ++ ++ cp_sz = probereq_wpsie_len>MAX_WPS_IE_LEN ? MAX_WPS_IE_LEN:probereq_wpsie_len; ++ ++ _rtw_memcpy(pmlmepriv->probereq_wpsie, probereq_wpsie, cp_sz); ++ pmlmepriv->probereq_wpsie_len = cp_sz; ++ ++ } ++ ++ goto FREE_EXT; ++ ++ } ++ ++ if( len >= WEXT_CSCAN_HEADER_SIZE ++ && _rtw_memcmp(ext, WEXT_CSCAN_HEADER, WEXT_CSCAN_HEADER_SIZE) == _TRUE ++ ){ ++ ret = rtw_wx_set_scan(dev, info, awrq, ext); ++ goto FREE_EXT; ++ } ++ ++#ifdef CONFIG_ANDROID ++ //DBG_871X("rtw_wx_set_priv: %s req=%s\n", dev->name, ext); ++ ++ i = rtw_android_cmdstr_to_num(ext); ++ ++ switch(i) { ++ case ANDROID_WIFI_CMD_START : ++ indicate_wx_custom_event(padapter, "START"); ++ break; ++ case ANDROID_WIFI_CMD_STOP : ++ indicate_wx_custom_event(padapter, "STOP"); ++ break; ++ case ANDROID_WIFI_CMD_RSSI : ++ { ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ struct wlan_network *pcur_network = &pmlmepriv->cur_network; ++ ++ if(check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) { ++ sprintf(ext, "%s rssi %d", pcur_network->network.Ssid.Ssid, padapter->recvpriv.rssi); ++ } else { ++ sprintf(ext, "OK"); ++ } ++ } ++ break; ++ case ANDROID_WIFI_CMD_LINKSPEED : ++ { ++ union iwreq_data wrqd; ++ int ret_inner; ++ int mbps; ++ ++ if( 0!=(ret_inner=rtw_wx_get_rate(dev, info, &wrqd, extra)) ){ ++ mbps=0; ++ } else { ++ mbps=wrqd.bitrate.value / 1000000; ++ } ++ ++ sprintf(ext, "LINKSPEED %d", mbps); ++ } ++ break; ++ case ANDROID_WIFI_CMD_MACADDR : ++ sprintf(ext, "MACADDR = " MAC_FMT, MAC_ARG(dev->dev_addr)); ++ break; ++ case ANDROID_WIFI_CMD_SCAN_ACTIVE : ++ { ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ pmlmepriv->scan_mode=SCAN_ACTIVE; ++ sprintf(ext, "OK"); ++ } ++ break; ++ case ANDROID_WIFI_CMD_SCAN_PASSIVE : ++ { ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ pmlmepriv->scan_mode=SCAN_PASSIVE; ++ sprintf(ext, "OK"); ++ } ++ break; ++ ++ case ANDROID_WIFI_CMD_COUNTRY : ++ { ++ char country_code[10]; ++ int channel_plan = RT_CHANNEL_DOMAIN_FCC; ++ union iwreq_data wrqd; ++ int ret_inner; ++ ++ sscanf(ext,"%*s %s",country_code); ++ ++ if(0 == strcmp(country_code, "US")) ++ channel_plan = RT_CHANNEL_DOMAIN_FCC; ++ else if(0 == strcmp(country_code, "EU")) ++ channel_plan = RT_CHANNEL_DOMAIN_ETSI; ++ else if(0 == strcmp(country_code, "JP")) ++ channel_plan = RT_CHANNEL_DOMAIN_MKK; ++ else if(0 == strcmp(country_code, "CN")) ++ channel_plan = RT_CHANNEL_DOMAIN_CHINA; ++ else ++ DBG_871X("%s unknown country_code:%s, set to RT_CHANNEL_DOMAIN_FCC\n", __FUNCTION__, country_code); ++ ++ _rtw_memcpy(&wrqd, &channel_plan, sizeof(int)); ++ ++ if( 0!=(ret_inner=rtw_wx_set_channel_plan(dev, info, &wrqd, extra)) ){ ++ DBG_871X("%s rtw_wx_set_channel_plan error\n", __FUNCTION__); ++ } ++ ++ sprintf(ext, "OK"); ++ } ++ break; ++ ++ default : ++ #ifdef CONFIG_DEBUG_RTW_WX_SET_PRIV ++ DBG_871X("%s: %s unknowned req=%s\n", __FUNCTION__, ++ dev->name, ext_dbg); ++ #endif ++ ++ sprintf(ext, "OK"); ++ ++ } ++ ++ if (copy_to_user(dwrq->pointer, ext, min(dwrq->length, (u16)(strlen(ext)+1)) ) ) ++ ret = -EFAULT; ++ ++ #ifdef CONFIG_DEBUG_RTW_WX_SET_PRIV ++ DBG_871X("%s: %s req=%s rep=%s dwrq->length=%d, strlen(ext)+1=%d\n", __FUNCTION__, ++ dev->name, ext_dbg ,ext, dwrq->length, (u16)(strlen(ext)+1)); ++ #endif ++#endif //end of CONFIG_ANDROID ++ ++ ++FREE_EXT: ++ ++ rtw_vmfree(ext, len); ++ #ifdef CONFIG_DEBUG_RTW_WX_SET_PRIV ++ rtw_vmfree(ext_dbg, len); ++ #endif ++ ++ //DBG_871X("rtw_wx_set_priv: (SIOCSIWPRIV) %s ret=%d\n", ++ // dev->name, ret); ++ ++ return ret; ++ ++} ++ ++static int rtw_mp_efuse_get(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wdata, char *extra) ++{ ++ struct iw_point *wrqu = (struct iw_point *)wdata; ++ PADAPTER padapter = rtw_netdev_priv(dev); ++ struct mp_priv *pmp_priv; ++ ++ int i,j =0; ++ u8 data[EFUSE_MAP_SIZE]; ++ u8 rawdata[EFUSE_MAX_SIZE]; ++ u16 mapLen=0; ++ char *pch, *ptmp, *token, *tmp[3]={0x00,0x00,0x00}; ++ u16 addr = 0, cnts = 0, max_available_size = 0,raw_cursize = 0 ,raw_maxsize = 0; ++ ++ _rtw_memset(data, '\0', sizeof(data)); ++ _rtw_memset(rawdata, '\0', sizeof(rawdata)); ++ ++ if (copy_from_user(extra, wrqu->pointer, wrqu->length)) ++ return -EFAULT; ++ ++ pch = extra; ++ DBG_8192C("%s: in=%s\n", __func__, extra); ++ ++ i=0; ++ //mac 16 "00e04c871200" rmap,00,2 ++ while ( (token = strsep (&pch,",") )!=NULL ) ++ { ++ if(i>2) break; ++ tmp[i] = token; ++ i++; ++ } ++ ++ if ( strcmp(tmp[0],"realmap") == 0 ) { ++ ++ DBG_8192C("strcmp OK = %s \n" ,tmp[0]); ++ ++ mapLen = EFUSE_MAP_SIZE; ++ ++ if (rtw_efuse_map_read(padapter, 0, mapLen, data) == _SUCCESS){ ++ DBG_8192C("\t rtw_efuse_map_read \n"); ++ }else { ++ DBG_8192C("\t rtw_efuse_map_read : Fail \n"); ++ return -EFAULT; ++ } ++ _rtw_memset(extra, '\0', sizeof(extra)); ++ DBG_8192C("\tOFFSET\tVALUE(hex)\n"); ++ sprintf(extra, "%s \n", extra); ++ for ( i = 0; i < EFUSE_MAP_SIZE; i += 16 ) ++ { ++ DBG_8192C("\t0x%02x\t", i); ++ sprintf(extra, "%s \t0x%02x\t", extra,i); ++ for (j = 0; j < 8; j++) ++ { ++ DBG_8192C("%02X ", data[i+j]); ++ sprintf(extra, "%s %02X", extra, data[i+j]); ++ } ++ DBG_8192C("\t"); ++ sprintf(extra,"%s\t",extra); ++ for (; j < 16; j++){ ++ DBG_8192C("%02X ", data[i+j]); ++ sprintf(extra, "%s %02X", extra, data[i+j]); ++ } ++ DBG_8192C("\n"); ++ sprintf(extra,"%s\n",extra); ++ } ++ DBG_8192C("\n"); ++ wrqu->length = strlen(extra); ++ ++ return 0; ++ } ++ else if ( strcmp(tmp[0],"rmap") == 0 ) { ++ if ( tmp[1]==NULL || tmp[2]==NULL ) return -EINVAL; ++ // rmap addr cnts ++ addr = simple_strtoul(tmp[1], &ptmp, 16); ++ ++ DBG_8192C("addr = %x \n" ,addr); ++ ++ cnts=simple_strtoul(tmp[2], &ptmp,10); ++ if(cnts==0) return -EINVAL; ++ ++ DBG_8192C("cnts = %d \n" ,cnts); ++ //_rtw_memset(extra, '\0', wrqu->data.length); ++ ++ EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_AVAILABLE_EFUSE_BYTES_TOTAL, (PVOID)&max_available_size, _FALSE); ++ if ((addr + cnts) > max_available_size) { ++ DBG_8192C("(addr + cnts parameter error \n"); ++ return -EFAULT; ++ } ++ ++ if (rtw_efuse_map_read(padapter, addr, cnts, data) == _FAIL) ++ { ++ DBG_8192C("rtw_efuse_access error \n"); ++ } ++ else{ ++ DBG_8192C("rtw_efuse_access ok \n"); ++ } ++ ++ _rtw_memset(extra, '\0', sizeof(extra)); ++ for ( i = 0; i < cnts; i ++) { ++ DBG_8192C("0x%02x", data[i]); ++ sprintf(extra, "%s 0x%02X", extra, data[i]); ++ DBG_8192C(" "); ++ sprintf(extra,"%s ",extra); ++ } ++ ++ wrqu->length = strlen(extra)+1; ++ ++ DBG_8192C("extra = %s ", extra); ++ ++ return 0; ++ } ++ else if ( strcmp(tmp[0],"realraw") == 0 ) { ++ addr=0; ++ mapLen = EFUSE_MAX_SIZE; ++ ++ if (rtw_efuse_access(padapter, _FALSE, addr, mapLen, rawdata) == _FAIL) ++ { ++ DBG_8192C("\t rtw_efuse_map_read : Fail \n"); ++ return -EFAULT; ++ } else ++ { ++ DBG_8192C("\t rtw_efuse_access raw ok \n"); ++ } ++ ++ _rtw_memset(extra, '\0', sizeof(extra)); ++ for ( i=0; ilength = strlen(extra); ++ return 0; ++ } ++ else if ( strcmp(tmp[0],"mac") == 0 ) { ++ if ( tmp[1]==NULL || tmp[2]==NULL ) return -EINVAL; ++ #ifdef CONFIG_RTL8192C ++ addr = 0x16; ++ cnts = 6; ++ #endif ++ #ifdef CONFIG_RTL8192D ++ addr = 0x19; ++ cnts = 6; ++ #endif ++ EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_AVAILABLE_EFUSE_BYTES_TOTAL, (PVOID)&max_available_size, _FALSE); ++ if ((addr + mapLen) > max_available_size) { ++ DBG_8192C("(addr + cnts parameter error \n"); ++ return -EFAULT; ++ } ++ if (rtw_efuse_map_read(padapter, addr, cnts, data) == _FAIL) ++ { ++ DBG_8192C("rtw_efuse_access error \n"); ++ } ++ else{ ++ DBG_8192C("rtw_efuse_access ok \n"); ++ } ++ _rtw_memset(extra, '\0', sizeof(extra)); ++ for ( i = 0; i < cnts; i ++) { ++ DBG_8192C("0x%02x", data[i]); ++ sprintf(extra, "%s 0x%02X", extra, data[i+j]); ++ DBG_8192C(" "); ++ sprintf(extra,"%s ",extra); ++ } ++ wrqu->length = strlen(extra); ++ return 0; ++ } ++ else if ( strcmp(tmp[0],"vidpid") == 0 ) { ++ if ( tmp[1]==NULL || tmp[2]==NULL ) return -EINVAL; ++ #ifdef CONFIG_RTL8192C ++ addr=0x0a; ++ #endif ++ #ifdef CONFIG_RTL8192D ++ addr = 0x0c; ++ #endif ++ cnts = 4; ++ EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_AVAILABLE_EFUSE_BYTES_TOTAL, (PVOID)&max_available_size, _FALSE); ++ if ((addr + mapLen) > max_available_size) { ++ DBG_8192C("(addr + cnts parameter error \n"); ++ return -EFAULT; ++ } ++ if (rtw_efuse_map_read(padapter, addr, cnts, data) == _FAIL) ++ { ++ DBG_8192C("rtw_efuse_access error \n"); ++ } ++ else{ ++ DBG_8192C("rtw_efuse_access ok \n"); ++ } ++ _rtw_memset(extra, '\0', sizeof(extra)); ++ for ( i = 0; i < cnts; i ++) { ++ DBG_8192C("0x%02x", data[i]); ++ sprintf(extra, "%s 0x%02X", extra, data[i+j]); ++ DBG_8192C(" "); ++ sprintf(extra,"%s ",extra); ++ } ++ wrqu->length = strlen(extra); ++ return 0; ++ } ++ else if ( strcmp(tmp[0],"ableraw") == 0 ) { ++ efuse_GetCurrentSize(padapter,&raw_cursize); ++ raw_maxsize = efuse_GetMaxSize(padapter); ++ sprintf(extra, "%s : [ available raw size] = %d",extra,raw_maxsize-raw_cursize); ++ wrqu->length = strlen(extra); ++ ++ return 0; ++ }else ++ { ++ sprintf(extra, "%s : Command not found\n",extra); ++ wrqu->length = strlen(extra); ++ return 0; ++ } ++ ++ return 0; ++} ++ ++static int rtw_mp_efuse_set(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wdata, char *extra) ++{ ++ struct iw_point *wrqu = (struct iw_point *)wdata; ++ PADAPTER padapter = rtw_netdev_priv(dev); ++ ++ u8 buffer[40]; ++ u32 i,jj,kk; ++ u8 setdata[EFUSE_MAP_SIZE]; ++ u8 setrawdata[EFUSE_MAX_SIZE]; ++ char *pch, *ptmp, *token, *edata,*tmp[3]={0x00,0x00,0x00}; ++ ++ u16 addr = 0, max_available_size = 0; ++ u32 cnts = 0; ++ ++ pch = extra; ++ DBG_8192C("%s: in=%s\n", __func__, extra); ++ ++ i=0; ++ while ( (token = strsep (&pch,",") )!=NULL ) ++ { ++ if(i>2) break; ++ tmp[i] = token; ++ i++; ++ } ++ ++ // tmp[0],[1],[2] ++ // wmap,addr,00e04c871200 ++ if ( strcmp(tmp[0],"wmap") == 0 ) { ++ if ( tmp[1]==NULL || tmp[2]==NULL ) return -EINVAL; ++ if ( ! strlen( tmp[2] )/2 > 1 ) return -EFAULT; ++ ++ addr = simple_strtoul( tmp[1], &ptmp, 16 ); ++ addr = addr & 0xFF; ++ DBG_8192C("addr = %x \n" ,addr); ++ ++ cnts = strlen( tmp[2] )/2; ++ if ( cnts == 0) return -EFAULT; ++ ++ DBG_8192C("cnts = %d \n" ,cnts); ++ DBG_8192C("target data = %s \n" ,tmp[2]); ++ ++ for( jj = 0, kk = 0; jj < cnts; jj++, kk += 2 ) ++ { ++ setdata[jj] = key_2char2num( tmp[2][kk], tmp[2][kk+ 1] ); ++ } ++ ++ EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_AVAILABLE_EFUSE_BYTES_TOTAL, (PVOID)&max_available_size, _FALSE); ++ ++ if ((addr + cnts) > max_available_size) { ++ DBG_8192C("parameter error \n"); ++ return -EFAULT; ++ } ++ if (rtw_efuse_map_write(padapter, addr, cnts, setdata) == _FAIL) { ++ DBG_8192C("rtw_efuse_map_write error \n"); ++ return -EFAULT; ++ } else ++ DBG_8192C("rtw_efuse_map_write ok \n"); ++ ++ return 0; ++ } ++ else if ( strcmp(tmp[0],"wraw") == 0 ) { ++ if ( tmp[1]==NULL || tmp[2]==NULL ) return -EINVAL; ++ if ( ! strlen( tmp[2] )/2 > 1 ) return -EFAULT; ++ addr = simple_strtoul( tmp[1], &ptmp, 16 ); ++ addr = addr & 0xFF; ++ DBG_8192C("addr = %x \n" ,addr); ++ ++ cnts=strlen( tmp[2] )/2; ++ if ( cnts == 0) return -EFAULT; ++ ++ DBG_8192C(" cnts = %d \n" ,cnts ); ++ DBG_8192C("target data = %s \n" ,tmp[2] ); ++ ++ for( jj = 0, kk = 0; jj < cnts; jj++, kk += 2 ) ++ { ++ setrawdata[jj] = key_2char2num( tmp[2][kk], tmp[2][kk+ 1] ); ++ } ++ ++ if ( rtw_efuse_access( padapter, _TRUE, addr, cnts, setrawdata ) == _FAIL ){ ++ DBG_8192C("\t rtw_efuse_map_read : Fail \n"); ++ return -EFAULT; ++ } else ++ DBG_8192C("\t rtw_efuse_access raw ok \n"); ++ ++ return 0; ++ } ++ else if ( strcmp(tmp[0],"mac") == 0 ) { ++ if ( tmp[1]==NULL || tmp[2]==NULL ) return -EINVAL; ++ //mac,00e04c871200 ++ #ifdef CONFIG_RTL8192C ++ addr = 0x16; ++ #endif ++ #ifdef CONFIG_RTL8192D ++ addr = 0x19; ++ #endif ++ cnts = strlen( tmp[1] )/2; ++ if ( cnts == 0) return -EFAULT; ++ if ( cnts > 6 ){ ++ DBG_8192C("error data for mac addr = %s \n" ,tmp[1]); ++ return -EFAULT; ++ } ++ ++ DBG_8192C("target data = %s \n" ,tmp[1]); ++ ++ for( jj = 0, kk = 0; jj < cnts; jj++, kk += 2 ) ++ { ++ setdata[jj] = key_2char2num(tmp[1][kk], tmp[1][kk+ 1]); ++ } ++ ++ EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_AVAILABLE_EFUSE_BYTES_TOTAL, (PVOID)&max_available_size, _FALSE); ++ ++ if ((addr + cnts) > max_available_size) { ++ DBG_8192C("parameter error \n"); ++ return -EFAULT; ++ } ++ if ( rtw_efuse_map_write(padapter, addr, cnts, setdata) == _FAIL ) { ++ DBG_8192C("rtw_efuse_map_write error \n"); ++ return -EFAULT; ++ } else ++ DBG_8192C("rtw_efuse_map_write ok \n"); ++ ++ return 0; ++ } ++ else if ( strcmp(tmp[0],"vidpid") == 0 ) { ++ if ( tmp[1]==NULL || tmp[2]==NULL ) return -EINVAL; ++ // pidvid,da0b7881 ++ #ifdef CONFIG_RTL8192C ++ addr=0x0a; ++ #endif ++ #ifdef CONFIG_RTL8192D ++ addr = 0x0c; ++ #endif ++ ++ cnts=strlen( tmp[1] )/2; ++ if ( cnts == 0) return -EFAULT; ++ DBG_8192C("target data = %s \n" ,tmp[1]); ++ ++ for( jj = 0, kk = 0; jj < cnts; jj++, kk += 2 ) ++ { ++ setdata[jj] = key_2char2num(tmp[1][kk], tmp[1][kk+ 1]); ++ } ++ ++ EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_AVAILABLE_EFUSE_BYTES_TOTAL, (PVOID)&max_available_size, _FALSE); ++ ++ if ((addr + cnts) > max_available_size) { ++ DBG_8192C("parameter error \n"); ++ return -EFAULT; ++ } ++ ++ if ( rtw_efuse_map_write(padapter, addr, cnts, setdata) == _FAIL ) { ++ DBG_8192C("rtw_efuse_map_write error \n"); ++ return -EFAULT; ++ } else ++ DBG_8192C("rtw_efuse_map_write ok \n"); ++ ++ return 0; ++ } ++ else{ ++ DBG_8192C("Command not found\n"); ++ return 0; ++ } ++ ++ return 0; ++} ++ ++ ++ ++#if defined(CONFIG_MP_INCLUDED) && defined(CONFIG_MP_IWPRIV_SUPPORT) ++ ++/* ++ * Input Format: %s,%d,%d ++ * %s is width, could be ++ * "b" for 1 byte ++ * "w" for WORD (2 bytes) ++ * "dw" for DWORD (4 bytes) ++ * 1st %d is address(offset) ++ * 2st %d is data to write ++ */ ++static int rtw_mp_write_reg(struct net_device *dev, ++ struct iw_request_info *info, ++ struct iw_point *wrqu, char *extra) ++{ ++ char *pch, *pnext, *ptmp; ++ char *width_str; ++ char width; ++ u32 addr, data; ++ int ret; ++ PADAPTER padapter = rtw_netdev_priv(dev); ++ ++ ++ pch = extra; ++ pnext = strpbrk(pch, " ,.-"); ++ if (pnext == NULL) return -EINVAL; ++ *pnext = 0; ++ width_str = pch; ++ ++ pch = pnext + 1; ++ pnext = strpbrk(pch, " ,.-"); ++ if (pnext == NULL) return -EINVAL; ++ *pnext = 0; ++ addr = simple_strtoul(pch, &ptmp, 16); ++ if (addr > 0x3FFF) return -EINVAL; ++ ++ pch = pnext + 1; ++ if ((pch - extra) >= wrqu->length) return -EINVAL; ++ data = simple_strtoul(pch, &ptmp, 16); ++ ++ ret = 0; ++ width = width_str[0]; ++ switch (width) { ++ case 'b': ++ // 1 byte ++ if (data > 0xFF) { ++ ret = -EINVAL; ++ break; ++ } ++ rtw_write8(padapter, addr, data); ++ break; ++ case 'w': ++ // 2 bytes ++ if (data > 0xFFFF) { ++ ret = -EINVAL; ++ break; ++ } ++ rtw_write16(padapter, addr, data); ++ break; ++ case 'd': ++ // 4 bytes ++ rtw_write32(padapter, addr, data); ++ break; ++ default: ++ ret = -EINVAL; ++ break; ++ } ++ ++ return ret; ++} ++ ++/* ++ * Input Format: %s,%d ++ * %s is width, could be ++ * "b" for 1 byte ++ * "w" for WORD (2 bytes) ++ * "dw" for DWORD (4 bytes) ++ * %d is address(offset) ++ * ++ * Return: ++ * %d for data readed ++ */ ++static int rtw_mp_read_reg(struct net_device *dev, ++ struct iw_request_info *info, ++ struct iw_point *wrqu, char *extra) ++{ ++ char input[wrqu->length]; ++ char *pch, *pnext, *ptmp; ++ char *width_str; ++ char width; ++ char data[20],tmp[20]; ++ u32 addr; ++ //u32 *data = (u32*)extra; ++ u32 ret, i=0, j=0, strtout=0; ++ PADAPTER padapter = rtw_netdev_priv(dev); ++ ++ ++ if (wrqu->length > 128) return -EFAULT; ++ ++ if (copy_from_user(input, wrqu->pointer, wrqu->length)) ++ return -EFAULT; ++ ++ pch = input; ++ pnext = strpbrk(pch, " ,.-"); ++ if (pnext == NULL) return -EINVAL; ++ *pnext = 0; ++ width_str = pch; ++ ++ pch = pnext + 1; ++ if ((pch - input) >= wrqu->length) return -EINVAL; ++ ++ addr = simple_strtoul(pch, &ptmp, 16); ++ if (addr > 0x3FFF) return -EINVAL; ++ ++ ret = 0; ++ width = width_str[0]; ++ switch (width) { ++ case 'b': ++ // 1 byte ++ // *(u8*)data = rtw_read8(padapter, addr); ++ sprintf(extra, "%d\n", rtw_read8(padapter, addr)); ++ wrqu->length = 4; ++ break; ++ case 'w': ++ // 2 bytes ++ //*(u16*)data = rtw_read16(padapter, addr); ++ sprintf(data, "%04d\n", rtw_read16(padapter, addr)); ++ for( i=0 ; i <= strlen(data) ; i++) ++ { ++ if( i%2==0 ) ++ { ++ tmp[j]=' '; ++ j++; ++ } ++ if ( data[i] != '\0' ) ++ tmp[j] = data[i]; ++ ++ j++; ++ } ++ pch = tmp; ++ DBG_8192C("pch=%s",pch); ++ ++ while( *pch != '\0' ) ++ { ++ pnext = strpbrk(pch, " "); ++ pnext++; ++ if ( *pnext != '\0' ) ++ { ++ strtout = simple_strtoul (pnext , &ptmp, 16); ++ sprintf( extra, "%s %d" ,extra ,strtout ); ++ } ++ else{ ++ break; ++ } ++ pch = pnext; ++ } ++ wrqu->length = 8; ++ break; ++ case 'd': ++ // 4 bytes ++ //*data = rtw_read32(padapter, addr); ++ sprintf(data, "%08x", rtw_read32(padapter, addr)); ++ //add read data format blank ++ for( i=0 ; i <= strlen(data) ; i++) ++ { ++ if( i%2==0 ) ++ { ++ tmp[j]=' '; ++ j++; ++ } ++ tmp[j] = data[i]; ++ j++; ++ } ++ pch = tmp; ++ DBG_8192C("pch=%s",pch); ++ ++ while( *pch != '\0' ) ++ { ++ pnext = strpbrk(pch, " "); ++ pnext++; ++ if ( *pnext != '\0' ) ++ { ++ strtout = simple_strtoul (pnext , &ptmp, 16); ++ sprintf( extra, "%s %d" ,extra ,strtout ); ++ } ++ else{ ++ break; ++ } ++ pch = pnext; ++ } ++ wrqu->length = 20; ++ break; ++ ++ default: ++ wrqu->length = 0; ++ ret = -EINVAL; ++ break; ++ ++ } ++ ++ return ret; ++} ++ ++/* ++ * Input Format: %d,%x,%x ++ * %d is RF path, should be smaller than MAX_RF_PATH_NUMS ++ * 1st %x is address(offset) ++ * 2st %x is data to write ++ */ ++ static int rtw_mp_write_rf(struct net_device *dev, ++ struct iw_request_info *info, ++ struct iw_point *wrqu, char *extra) ++{ ++/*static int rtw_mp_write_rf(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++*/ ++ u32 path, addr, data; ++ int ret; ++ PADAPTER padapter = rtw_netdev_priv(dev); ++ ++ ++ ret = sscanf(extra, "%d,%x,%x", &path, &addr, &data); ++ if (ret < 3) return -EINVAL; ++ ++ if (path >= MAX_RF_PATH_NUMS) return -EINVAL; ++ if (addr > 0xFF) return -EINVAL; ++ if (data > 0xFFFFF) return -EINVAL; ++ ++ write_rfreg(padapter, path, addr, data); ++ ++ return 0; ++} ++ ++/* ++ * Input Format: %d,%x ++ * %d is RF path, should be smaller than MAX_RF_PATH_NUMS ++ * %x is address(offset) ++ * ++ * Return: ++ * %d for data readed ++ */ ++static int rtw_mp_read_rf(struct net_device *dev, ++ struct iw_request_info *info, ++ struct iw_point *wrqu, char *extra) ++{ ++ char input[wrqu->length]; ++ char *pch, *pnext, *ptmp; ++ char data[20],tmp[20]; ++ //u32 *data = (u32*)extra; ++ u32 path, addr; ++ u32 ret,i=0 ,j=0,strtou=0; ++ PADAPTER padapter = rtw_netdev_priv(dev); ++ ++ ++ if (wrqu->length > 128) return -EFAULT; ++ if (copy_from_user(input, wrqu->pointer, wrqu->length)) ++ return -EFAULT; ++ ++ ret = sscanf(extra, "%d,%x", &path, &addr); ++ if (ret < 2) return -EINVAL; ++ ++ if (path >= MAX_RF_PATH_NUMS) return -EINVAL; ++ if (addr > 0xFF) return -EINVAL; ++ ++ //*data = read_rfreg(padapter, path, addr); ++ sprintf(data, "%08x", read_rfreg(padapter, path, addr)); ++ //add read data format blank ++ for( i=0 ; i <= strlen(data) ; i++) ++ { ++ if( i%2==0 ) ++ { ++ tmp[j]=' '; ++ j++; ++ } ++ tmp[j] = data[i]; ++ j++; ++ } ++ pch = tmp; ++ DBG_8192C("pch=%s",pch); ++ ++ while( *pch != '\0' ) ++ { ++ pnext = strpbrk(pch, " "); ++ pnext++; ++ if ( *pnext != '\0' ) ++ { ++ strtou = simple_strtoul (pnext , &ptmp, 16); ++ sprintf( extra, "%s %d" ,extra ,strtou ); ++ } ++ else{ ++ break; ++ } ++ pch = pnext; ++ } ++ wrqu->length = 10; ++ ++ return 0; ++} ++ ++static int rtw_mp_start(struct net_device *dev, ++ struct iw_request_info *info, ++ struct iw_point *wrqu, char *extra) ++{ ++ u8 val8; ++ PADAPTER padapter = rtw_netdev_priv(dev); ++ ++ ++ if (padapter->registrypriv.mp_mode == 0) ++ return -EPERM; ++ ++ if (padapter->mppriv.mode == MP_OFF) { ++ if (mp_start_test(padapter) == _FAIL) ++ return -EPERM; ++ padapter->mppriv.mode = MP_ON; ++ } ++ ++ return 0; ++} ++ ++static int rtw_mp_stop(struct net_device *dev, ++ struct iw_request_info *info, ++ struct iw_point *wrqu, char *extra) ++{ ++ PADAPTER padapter = rtw_netdev_priv(dev); ++ ++ ++ if (padapter->mppriv.mode != MP_OFF) { ++ mp_stop_test(padapter); ++ padapter->mppriv.mode = MP_OFF; ++ } ++ ++ return 0; ++} ++ ++extern int wifirate2_ratetbl_inx(unsigned char rate); ++ ++static int rtw_mp_rate(struct net_device *dev, ++ struct iw_request_info *info, ++ struct iw_point *wrqu, char *extra) ++{ ++ u32 rate = MPT_RATE_1M; ++ u8 input[wrqu->length]; ++ PADAPTER padapter = rtw_netdev_priv(dev); ++ ++ if (copy_from_user(input, wrqu->pointer, wrqu->length)) ++ return -EFAULT; ++ ++ rate = rtw_atoi(input); ++ sprintf( extra, "Set data rate to %d" , rate ); ++ ++ if(rate <= 0x7f) ++ rate = wifirate2_ratetbl_inx( (u8)rate); ++ else ++ rate =(rate-0x80+MPT_RATE_MCS0); ++ ++ //DBG_8192C("%s: rate=%d\n", __func__, rate); ++ ++ if (rate >= MPT_RATE_LAST ) ++ return -EINVAL; ++ ++ padapter->mppriv.rateidx = rate; ++ Hal_SetDataRate(padapter); ++ ++ wrqu->length = strlen(extra) + 1; ++ return 0; ++} ++ ++static int rtw_mp_channel(struct net_device *dev, ++ struct iw_request_info *info, ++ struct iw_point *wrqu, char *extra) ++{ ++ ++ PADAPTER padapter = rtw_netdev_priv(dev); ++ u8 input[wrqu->length]; ++ u32 channel = 1; ++ ++ if (copy_from_user(input, wrqu->pointer, wrqu->length)) ++ return -EFAULT; ++ ++ channel = rtw_atoi(input); ++ //DBG_8192C("%s: channel=%d\n", __func__, channel); ++ sprintf( extra, "Change channel %d to channel %d", padapter->mppriv.channel , channel ); ++ ++ padapter->mppriv.channel = channel; ++ Hal_SetChannel(padapter); ++ ++ wrqu->length = strlen(extra) + 1; ++ return 0; ++} ++ ++static int rtw_mp_bandwidth(struct net_device *dev, ++ struct iw_request_info *info, ++ struct iw_point *wrqu, char *extra) ++{ ++ u32 bandwidth=0, sg=0; ++ //u8 buffer[40]; ++ PADAPTER padapter = rtw_netdev_priv(dev); ++ //if (copy_from_user(buffer, (void*)wrqu->data.pointer, wrqu->data.length)) ++ // return -EFAULT; ++ ++ //DBG_8192C("%s:iwpriv in=%s\n", __func__, extra); ++ ++ sscanf(extra, "40M=%d,shortGI=%d", &bandwidth, &sg); ++ ++ if (bandwidth != HT_CHANNEL_WIDTH_40) ++ bandwidth = HT_CHANNEL_WIDTH_20; ++ ++ //DBG_8192C("%s: bw=%d sg=%d \n", __func__, bandwidth , sg); ++ ++ padapter->mppriv.bandwidth = (u8)bandwidth; ++ padapter->mppriv.preamble = sg; ++ ++ SetBandwidth(padapter); ++ ++ return 0; ++} ++ ++static int rtw_mp_txpower(struct net_device *dev, ++ struct iw_request_info *info, ++ struct iw_point *wrqu, char *extra) ++{ ++ u32 idx_a=0,idx_b=0; ++ u8 input[wrqu->length]; ++ ++ PADAPTER padapter = rtw_netdev_priv(dev); ++ ++ if (copy_from_user(input, wrqu->pointer, wrqu->length)) ++ return -EFAULT; ++ ++ sscanf(input,"patha=%d,pathb=%d",&idx_a,&idx_b); ++ //DBG_8192C("%s: tx_pwr_idx_a=%x b=%x\n", __func__, idx_a, idx_b); ++ ++ sprintf( extra, "Set power level path_A:%d path_B:%d", idx_a , idx_b ); ++ padapter->mppriv.txpoweridx = (u8)idx_a; ++ padapter->mppriv.txpoweridx_b = (u8)idx_b; ++ ++ Hal_SetAntennaPathPower(padapter); ++ ++ wrqu->length = strlen(extra) + 1; ++ return 0; ++} ++ ++static int rtw_mp_ant_tx(struct net_device *dev, ++ struct iw_request_info *info, ++ struct iw_point *wrqu, char *extra) ++{ ++ u8 i; ++ u8 input[wrqu->length]; ++ u16 antenna = 0; ++ PADAPTER padapter = rtw_netdev_priv(dev); ++ ++ if (copy_from_user(input, wrqu->pointer, wrqu->length)) ++ return -EFAULT; ++ ++ DBG_8192C("%s: input=%s\n", __func__, input); ++ ++ sprintf( extra, "switch Tx antenna to %s", input ); ++ ++ for (i=0; i < strlen(input); i++) ++ { ++ switch(input[i]) ++ { ++ case 'a' : ++ antenna|=ANTENNA_A; ++ break; ++ case 'b': ++ antenna|=ANTENNA_B; ++ break; ++ } ++ } ++ //antenna |= BIT(extra[i]-'a'); ++ DBG_8192C("%s: antenna=0x%x\n", __func__, antenna); ++ padapter->mppriv.antenna_tx = antenna; ++ DBG_8192C("%s:mppriv.antenna_rx=%d\n", __func__, padapter->mppriv.antenna_tx); ++ ++ Hal_SetAntenna(padapter); ++ ++ wrqu->length = strlen(extra) + 1; ++ return 0; ++} ++ ++static int rtw_mp_ant_rx(struct net_device *dev, ++ struct iw_request_info *info, ++ struct iw_point *wrqu, char *extra) ++{ ++ u8 i; ++ u16 antenna = 0; ++ u8 input[wrqu->length]; ++ PADAPTER padapter = rtw_netdev_priv(dev); ++ ++ if (copy_from_user(input, wrqu->pointer, wrqu->length)) ++ return -EFAULT; ++ //DBG_8192C("%s: input=%s\n", __func__, input); ++ ++ for (i=0; i < strlen(input); i++) { ++ ++ switch( input[i] ) ++ { ++ case 'a' : ++ antenna|=ANTENNA_A; ++ break; ++ case 'b': ++ antenna|=ANTENNA_B; ++ break; ++ } ++ } ++ ++ //DBG_8192C("%s: antenna=0x%x\n", __func__, antenna); ++ padapter->mppriv.antenna_rx = antenna; ++ //DBG_8192C("%s:mppriv.antenna_rx=%d\n", __func__, padapter->mppriv.antenna_rx); ++ Hal_SetAntenna(padapter); ++ wrqu->length = strlen(extra) + 1; ++ ++ return 0; ++} ++ ++static int rtw_mp_ctx(struct net_device *dev, ++ struct iw_request_info *info, ++ struct iw_point *wrqu, char *extra) ++{ ++ u32 pkTx = 1, countPkTx = 1, cotuTx = 1, CarrSprTx = 1, scTx = 1, sgleTx = 1, stop = 1; ++ u32 bStartTest = 1; ++ u32 count = 0; ++ struct mp_priv *pmp_priv; ++ struct pkt_attrib *pattrib; ++ ++ PADAPTER padapter = rtw_netdev_priv(dev); ++ ++ ++ pmp_priv = &padapter->mppriv; ++ ++ if (copy_from_user(extra, wrqu->pointer, wrqu->length)) ++ return -EFAULT; ++ ++ DBG_8192C("%s: in=%s\n", __func__, extra); ++ ++ countPkTx = strncmp(extra, "count=", 5); // strncmp TRUE is 0 ++ cotuTx = strncmp(extra, "background", 20); ++ CarrSprTx = strncmp(extra, "background,cs", 20); ++ scTx = strncmp(extra, "background,sc", 20); ++ sgleTx = strncmp(extra, "background,stone", 20); ++ pkTx = strncmp(extra, "background,pkt", 20); ++ stop = strncmp(extra, "stop", 5); ++ sscanf(extra, "count=%d,pkt", &count); ++ ++ //DBG_8192C("%s: count=%d countPkTx=%d cotuTx=%d CarrSprTx=%d scTx=%d sgleTx=%d pkTx=%d stop=%d\n", __func__, count, countPkTx, cotuTx, CarrSprTx, pkTx, sgleTx, scTx, stop); ++ _rtw_memset(extra, '\0', sizeof(extra)); ++ ++ if (stop == 0) { ++ bStartTest = 0; // To set Stop ++ pmp_priv->tx.stop = 1; ++ sprintf( extra, "Stop continuous Tx"); ++ } else { ++ bStartTest = 1; ++ if (pmp_priv->mode != MP_ON) { ++ if (pmp_priv->tx.stop != 1) { ++ DBG_8192C("%s: MP_MODE != ON %d\n", __func__, pmp_priv->mode); ++ return -EFAULT; ++ } ++ } ++ } ++ ++ if (pkTx == 0 || countPkTx == 0) ++ pmp_priv->mode = MP_PACKET_TX; ++ if (sgleTx == 0) ++ pmp_priv->mode = MP_SINGLE_TONE_TX; ++ if (cotuTx == 0) ++ pmp_priv->mode = MP_CONTINUOUS_TX; ++ if (CarrSprTx == 0) ++ pmp_priv->mode = MP_CARRIER_SUPPRISSION_TX; ++ if (scTx == 0) ++ pmp_priv->mode = MP_SINGLE_CARRIER_TX; ++ ++ switch (pmp_priv->mode) ++ { ++ case MP_PACKET_TX: ++ ++ //DBG_8192C("%s:pkTx %d\n", __func__,bStartTest); ++ if (bStartTest == 0) ++ { ++ pmp_priv->tx.stop = 1; ++ pmp_priv->mode = MP_ON; ++ sprintf( extra, "Stop continuous Tx"); ++ } ++ else if (pmp_priv->tx.stop == 1) ++ { ++ sprintf( extra, "Start continuous DA=ffffffffffff len=1500 count=%u,\n",count); ++ //DBG_8192C("%s:countPkTx %d\n", __func__,count); ++ pmp_priv->tx.stop = 0; ++ pmp_priv->tx.count = count; ++ pmp_priv->tx.payload = 2; ++ pattrib = &pmp_priv->tx.attrib; ++ pattrib->pktlen = 1460; ++ _rtw_memset(pattrib->dst, 0xFF, ETH_ALEN); ++ SetPacketTx(padapter); ++ } ++ else { ++ //DBG_8192C("%s: pkTx not stop\n", __func__); ++ return -EFAULT; ++ } ++ wrqu->length = strlen(extra); ++ return 0; ++ ++ case MP_SINGLE_TONE_TX: ++ //DBG_8192C("%s: sgleTx %d \n", __func__, bStartTest); ++ if (bStartTest != 0){ ++ sprintf( extra, "Start continuous DA=ffffffffffff len=1500 \n infinite=yes."); ++ Hal_SetSingleToneTx(padapter, (u8)bStartTest); ++ } ++ break; ++ ++ case MP_CONTINUOUS_TX: ++ //DBG_8192C("%s: cotuTx %d\n", __func__, bStartTest); ++ if (bStartTest != 0){ ++ sprintf( extra, "Start continuous DA=ffffffffffff len=1500 \n infinite=yes."); ++ Hal_SetContinuousTx(padapter, (u8)bStartTest); ++ } ++ break; ++ ++ case MP_CARRIER_SUPPRISSION_TX: ++ //DBG_8192C("%s: CarrSprTx %d\n", __func__, bStartTest); ++ if (bStartTest != 0){ ++ if( pmp_priv->rateidx <= MPT_RATE_11M ) ++ { ++ sprintf( extra, "Start continuous DA=ffffffffffff len=1500 \n infinite=yes."); ++ Hal_SetCarrierSuppressionTx(padapter, (u8)bStartTest); ++ }else ++ sprintf( extra, "Specify carrier suppression but not CCK rate"); ++ } ++ break; ++ ++ case MP_SINGLE_CARRIER_TX: ++ //DBG_8192C("%s: scTx %d\n", __func__, bStartTest); ++ if (bStartTest != 0){ ++ sprintf( extra, "Start continuous DA=ffffffffffff len=1500 \n infinite=yes."); ++ Hal_SetSingleCarrierTx(padapter, (u8)bStartTest); ++ } ++ break; ++ ++ default: ++ //DBG_8192C("%s:No Match MP_MODE\n", __func__); ++ sprintf( extra, "Error! Continuous-Tx is not on-going."); ++ return -EFAULT; ++ } ++ ++ if (bStartTest) { ++ struct mp_priv *pmp_priv = &padapter->mppriv; ++ if (pmp_priv->tx.stop == 0) { ++ pmp_priv->tx.stop = 1; ++ //DBG_8192C("%s: pkt tx is running...\n", __func__); ++ rtw_msleep_os(5); ++ } ++ pmp_priv->tx.stop = 0; ++ pmp_priv->tx.count = 1; ++ SetPacketTx(padapter); ++ } else { ++ pmp_priv->mode = MP_ON; ++ } ++ ++ wrqu->length = strlen(extra); ++ return 0; ++} ++ ++static int rtw_mp_arx(struct net_device *dev, ++ struct iw_request_info *info, ++ struct iw_point *wrqu, char *extra) ++{ ++ u8 bStartRx=0,bStopRx=0; ++ PADAPTER padapter = rtw_netdev_priv(dev); ++ u8 input[wrqu->length]; ++ ++ if (copy_from_user(input, wrqu->pointer, wrqu->length)) ++ return -EFAULT; ++ ++ DBG_8192C("%s: %s\n", __func__, input); ++ ++ bStartRx = (strncmp(input, "start", 5)==0)?1:0; // strncmp TRUE is 0 ++ bStopRx = (strncmp(input, "stop", 5)==0)?1:0; // strncmp TRUE is 0 ++ SetPacketRx(padapter, bStartRx); ++ ++ if(bStartRx) ++ { ++ sprintf( extra, "start"); ++ wrqu->length = strlen(extra) + 1; ++ } ++ else if(bStopRx) ++ { ++ sprintf( extra, "Received packet OK:%d CRC error:%d",padapter->mppriv.rx_pktcount, ++ padapter->mppriv.rx_crcerrpktcount); ++ wrqu->length = strlen(extra) + 1; ++ } ++ ++ ++ return 0; ++} ++ ++static int rtw_mp_trx_query(struct net_device *dev, ++ struct iw_request_info *info, ++ struct iw_point *wrqu, char *extra) ++{ ++ u32 txok,txfail,rxok,rxfail; ++ PADAPTER padapter = rtw_netdev_priv(dev); ++ //if (copy_from_user(extra, wrqu->data.pointer, wrqu->data.length)) ++ // return -EFAULT; ++ ++ txok=padapter->mppriv.tx.sended; ++ txfail=0; ++ rxok = padapter->mppriv.rx_pktcount; ++ rxfail = padapter->mppriv.rx_crcerrpktcount; ++ ++ _rtw_memset(extra, '\0', 128); ++ ++ sprintf(extra, "Tx OK:%d, Tx Fail:%d, Rx OK:%d, CRC error:%d ", txok, txfail,rxok,rxfail); ++ ++ wrqu->length=strlen(extra)+1; ++ ++ return 0; ++} ++ ++static int rtw_mp_pwrtrk(struct net_device *dev, ++ struct iw_request_info *info, ++ struct iw_point *wrqu, char *extra) ++{ ++ u8 enable; ++ u32 thermal; ++ s32 ret; ++ PADAPTER padapter = rtw_netdev_priv(dev); ++ ++ ++ enable = 1; ++ if (wrqu->length > 1) { // not empty string ++ if (strncmp(extra, "stop", 4) == 0) ++ enable = 0; ++ else { ++ if (sscanf(extra, "ther=%d", &thermal)) { ++ ret = Hal_SetThermalMeter(padapter, (u8)thermal); ++ if (ret == _FAIL) return -EPERM; ++ } else ++ return -EINVAL; ++ } ++ } ++ ++ ret = Hal_SetPowerTracking(padapter, enable); ++ if (ret == _FAIL) return -EPERM; ++ ++ return 0; ++} ++ ++static int rtw_mp_psd(struct net_device *dev, ++ struct iw_request_info *info, ++ struct iw_point *wrqu, char *extra) ++{ ++ PADAPTER padapter = rtw_netdev_priv(dev); ++ ++ ++ if (copy_from_user(extra, wrqu->pointer, wrqu->length)) ++ return -EFAULT; ++ ++ wrqu->length = mp_query_psd(padapter, extra); ++ ++ return 0; ++} ++ ++static int rtw_mp_thermal(struct net_device *dev, ++ struct iw_request_info *info, ++ struct iw_point *wrqu, char *extra) ++{ ++ u8 val; ++ u16 bwrite=1; ++ #ifdef CONFIG_RTL8192C ++ u16 addr=0x78; ++ #endif ++ #ifdef CONFIG_RTL8192D ++ u16 addr=0xc3; ++ #endif ++ u16 cnt=1; ++ u16 max_available_size=0; ++ PADAPTER padapter = rtw_netdev_priv(dev); ++ ++ if (copy_from_user(extra, wrqu->pointer, wrqu->length)) ++ return -EFAULT; ++ ++ //DBG_8192C("print extra %s \n",extra); ++ ++ bwrite = strncmp(extra, "write", 6); // strncmp TRUE is 0 ++ ++ Hal_GetThermalMeter(padapter, &val); ++ ++ if( bwrite == 0 ) ++ { ++ //DBG_8192C("to write val:%d",val); ++ EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_AVAILABLE_EFUSE_BYTES_TOTAL, (PVOID)&max_available_size, _FALSE); ++ if( 2 > max_available_size ) ++ { ++ DBG_8192C("no available efuse!\n"); ++ return -EFAULT; ++ } ++ if ( rtw_efuse_map_write(padapter, addr, cnt, &val) == _FAIL ) ++ { ++ DBG_8192C("rtw_efuse_map_write error \n"); ++ return -EFAULT; ++ } ++ else ++ { ++ sprintf(extra, " efuse write ok :%d", val); ++ } ++ } ++ else ++ { ++ sprintf(extra, "%d", val); ++ } ++ wrqu->length = strlen(extra); ++ ++ return 0; ++} ++ ++static int rtw_mp_reset_stats(struct net_device *dev, ++ struct iw_request_info *info, ++ struct iw_point *wrqu, char *extra) ++{ ++ struct mp_priv *pmp_priv; ++ struct pkt_attrib *pattrib; ++ PADAPTER padapter = rtw_netdev_priv(dev); ++ ++ pmp_priv = &padapter->mppriv; ++ ++ pmp_priv->tx.sended = 0; ++ padapter->mppriv.rx_pktcount = 0; ++ padapter->mppriv.rx_crcerrpktcount = 0; ++ ++ return 0; ++} ++ ++static int rtw_mp_dump(struct net_device *dev, ++ struct iw_request_info *info, ++ struct iw_point *wrqu, char *extra) ++{ ++ struct mp_priv *pmp_priv; ++ struct pkt_attrib *pattrib; ++ u32 value; ++ u8 rf_type,path_nums = 0; ++ u32 i,j=1,path; ++ PADAPTER padapter = rtw_netdev_priv(dev); ++ ++ pmp_priv = &padapter->mppriv; ++ ++ ++ //if (copy_from_user(extra, wrqu->data.pointer, wrqu->data.length)) ++ // return -EFAULT; ++ ++ if ( strncmp(extra, "all", 4)==0 ) ++ { ++ DBG_8192C("\n======= MAC REG =======\n"); ++ for ( i=0x0;i<0x300;i+=4 ) ++ { ++ if(j%4==1) DBG_8192C("0x%02x",i); ++ DBG_8192C(" 0x%08x ",rtw_read32(padapter,i)); ++ if((j++)%4 == 0) DBG_8192C("\n"); ++ } ++ for( i=0x400;i<0x800;i+=4 ) ++ { ++ if(j%4==1) DBG_8192C("0x%02x",i); ++ DBG_8192C(" 0x%08x ",rtw_read32(padapter,i)); ++ if((j++)%4 == 0) DBG_8192C("\n"); ++ } ++ ++ i,j=1; ++ padapter->HalFunc.GetHwRegHandler(padapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type)); ++ ++ DBG_8192C("\n======= RF REG =======\n"); ++ if(( RF_1T2R == rf_type ) ||( RF_1T1R ==rf_type )) ++ path_nums = 1; ++ else ++ path_nums = 2; ++ ++ for(path=0;pathHalFunc.read_rfreg(padapter, path, i, 0xffffffff); ++ if(j%4==1) DBG_8192C("0x%02x ",i); ++ DBG_8192C(" 0x%08x ",value); ++ if((j++)%4==0) DBG_8192C("\n"); ++ } ++ } ++ } ++ return 0; ++} ++ ++static int rtw_mp_phypara(struct net_device *dev, ++ struct iw_request_info *info, ++ struct iw_point *wrqu, char *extra) ++{ ++ ++ PADAPTER padapter = rtw_netdev_priv(dev); ++ char input[wrqu->length]; ++ u32 valxcap; ++ ++ if (copy_from_user(input, wrqu->pointer, wrqu->length)) ++ return -EFAULT; ++ ++ DBG_8192C("%s:iwpriv in=%s\n", __func__, input); ++ ++ sscanf(input, "xcap=%d", &valxcap); ++ ++ if (!IS_HARDWARE_TYPE_8192D(padapter)) ++ return 0; ++#ifdef CONFIG_RTL8192D ++ Hal_ProSetCrystalCap( padapter , valxcap ); ++#endif ++ ++ sprintf( extra, "Set xcap=%d",valxcap ); ++ wrqu->length = strlen(extra) + 1; ++ ++return 0; ++ ++} ++ ++ ++/* update Tx AGC offset */ ++static int rtw_mp_antBdiff(struct net_device *dev, ++ struct iw_request_info *info, ++ struct iw_point *wrqu, char *extra) ++{ ++ ++ ++ // MPT_ProSetTxAGCOffset ++ return 0; ++} ++ ++ ++static int rtw_mp_set(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wdata, char *extra) ++{ ++ struct iw_point *wrqu = (struct iw_point *)wdata; ++ u32 subcmd = wrqu->flags; ++ PADAPTER padapter = rtw_netdev_priv(dev); ++ ++ if (padapter == NULL) ++ { ++ return -ENETDOWN; ++ } ++ ++ //_rtw_memset(extra, 0x00, IW_PRIV_SIZE_MASK); ++ ++ if (extra == NULL) ++ { ++ wrqu->length = 0; ++ return -EIO; ++ } ++ ++ switch(subcmd) ++ { ++ case WRITE_REG : ++ rtw_mp_write_reg (dev,info,wrqu,extra); ++ break; ++ ++ case WRITE_RF: ++ rtw_mp_write_rf (dev,info,wrqu,extra); ++ break; ++ ++ case MP_START: ++ DBG_8192C("set case mp_start \n"); ++ rtw_mp_start (dev,info,wrqu,extra); ++ break; ++ ++ case MP_STOP: ++ DBG_8192C("set case mp_stop \n"); ++ rtw_mp_stop (dev,info,wrqu,extra); ++ break; ++ ++ case MP_BANDWIDTH: ++ DBG_8192C("set case mp_bandwidth \n"); ++ rtw_mp_bandwidth (dev,info,wrqu,extra); ++ break; ++ case MP_PWRTRK: ++ DBG_8192C("set case MP_PWRTRK \n"); ++ rtw_mp_pwrtrk (dev,info,wrqu,extra); ++ break; ++ ++ case MP_RESET_STATS: ++ DBG_8192C("set case MP_RESET_STATS \n"); ++ rtw_mp_reset_stats (dev,info,wrqu,extra); ++ break; ++ ++ case EFUSE_SET: ++ DBG_8192C("efuse set \n"); ++ rtw_mp_efuse_set (dev,info,wdata,extra); ++ break; ++ ++ } ++ ++ ++ return 0; ++} ++ ++ ++static int rtw_mp_get(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wdata, char *extra) ++{ ++ struct iw_point *wrqu = (struct iw_point *)wdata; ++ u32 subcmd = wrqu->flags; ++ PADAPTER padapter = rtw_netdev_priv(dev); ++ ++ DBG_8192C("in mp_get extra= %s \n",extra); ++ ++ if (padapter == NULL) ++ { ++ return -ENETDOWN; ++ } ++ if (extra == NULL) ++ { ++ wrqu->length = 0; ++ return -EIO; ++ } ++ ++ switch(subcmd) ++ { ++ case MP_PHYPARA: ++ DBG_8192C("mp_get MP_PHYPARA \n"); ++ rtw_mp_phypara(dev,info,wrqu,extra); ++ break; ++ ++ case MP_CHANNEL: ++ DBG_8192C("set case mp_channel \n"); ++ rtw_mp_channel (dev,info,wrqu,extra); ++ break; ++ ++ case READ_REG: ++ DBG_8192C("mp_get READ_REG \n"); ++ rtw_mp_read_reg (dev,info,wrqu,extra); ++ break; ++ case READ_RF: ++ DBG_8192C("mp_get READ_RF \n"); ++ rtw_mp_read_rf (dev,info,wrqu,extra); ++ break; ++ ++ case MP_RATE: ++ DBG_8192C("set case mp_rate \n"); ++ rtw_mp_rate (dev,info,wrqu,extra); ++ break; ++ ++ case MP_TXPOWER: ++ DBG_8192C("set case MP_TXPOWER \n"); ++ rtw_mp_txpower (dev,info,wrqu,extra); ++ break; ++ ++ case MP_ANT_TX: ++ DBG_8192C("set case MP_ANT_TX \n"); ++ rtw_mp_ant_tx (dev,info,wrqu,extra); ++ break; ++ ++ case MP_ANT_RX: ++ DBG_8192C("set case MP_ANT_RX \n"); ++ rtw_mp_ant_rx (dev,info,wrqu,extra); ++ break; ++ ++ case MP_QUERY: ++ DBG_8192C("mp_get mp_query MP_QUERY \n"); ++ rtw_mp_trx_query(dev,info,wrqu,extra); ++ break; ++ ++ case MP_CTX: ++ DBG_8192C("set case MP_CTX \n"); ++ rtw_mp_ctx (dev,info,wrqu,extra); ++ break; ++ ++ case MP_ARX: ++ DBG_8192C("set case MP_ARX \n"); ++ rtw_mp_arx (dev,info,wrqu,extra); ++ break; ++ ++ case EFUSE_GET: ++ DBG_8192C("efuse get EFUSE_GET \n"); ++ rtw_mp_efuse_get(dev,info,wdata,extra); ++ break; ++ ++ case MP_DUMP: ++ DBG_8192C("set case MP_DUMP \n"); ++ rtw_mp_dump (dev,info,wrqu,extra); ++ break; ++ case MP_PSD: ++ DBG_8192C("set case MP_PSD \n"); ++ rtw_mp_psd (dev,info,wrqu,extra); ++ break; ++ ++ case MP_THER: ++ DBG_8192C("set case MP_THER \n"); ++ rtw_mp_thermal (dev,info,wrqu,extra); ++ break; ++ ++ } ++ ++return 0; ++} ++ ++#endif //#if defined(CONFIG_MP_INCLUDED) && defined(CONFIG_MP_IWPRIV_SUPPORT) ++ ++ ++ ++static int rtw_tdls_setup(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ int ret = 0; ++ ++#ifdef CONFIG_TDLS ++ ++ u8 i, j; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ u8 mac_addr[ETH_ALEN]; ++ ++ DBG_8192C( "[%s] %s %d\n", __FUNCTION__, extra, wrqu->data.length -1 ); ++ ++ for( i=0, j=0 ; i < ETH_ALEN; i++, j+=3 ){ ++ mac_addr[i]=key_2char2num(*(extra+j), *(extra+j+1)); ++ } ++ ++ issue_tdls_setup_req(padapter, mac_addr); ++ ++#endif ++ ++ return ret; ++} ++ ++ ++static int rtw_tdls_teardown(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ int ret = 0; ++ ++#ifdef CONFIG_TDLS ++ ++ u8 i,j; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct sta_info *ptdls_sta = NULL; ++ u8 mac_addr[ETH_ALEN]; ++ ++ DBG_8192C( "[%s] %s %d\n", __FUNCTION__, extra, wrqu->data.length -1 ); ++ ++ for( i=0, j=0 ; i < ETH_ALEN; i++, j+=3 ){ ++ mac_addr[i]=key_2char2num(*(extra+j), *(extra+j+1)); ++ } ++ ++ ptdls_sta = rtw_get_stainfo( &(padapter->stapriv), mac_addr); ++ ++ if(ptdls_sta != NULL) ++ { ++ ptdls_sta->stat_code = _RSON_TDLS_TEAR_UN_RSN_; ++ issue_tdls_teardown(padapter, mac_addr); ++ } ++ ++#endif ++ ++ return ret; ++} ++ ++ ++static int rtw_tdls_discovery(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ int ret = 0; ++ ++#ifdef CONFIG_TDLS ++ ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ ++ DBG_8192C( "[%s] %s %d\n", __FUNCTION__, extra, wrqu->data.length -1 ); ++ ++ issue_tdls_dis_req(padapter, NULL); ++ ++#endif ++ ++ return ret; ++} ++ ++static int rtw_tdls_ch_switch(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ int ret = 0; ++ ++#ifdef CONFIG_TDLS ++ ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct tdls_info *ptdlsinfo = &padapter->tdlsinfo; ++ u8 i, j, mac_addr[ETH_ALEN]; ++ struct sta_info *ptdls_sta = NULL; ++ ++ DBG_8192C( "[%s] %s %d\n", __FUNCTION__, extra, wrqu->data.length -1 ); ++ ++ for( i=0, j=0 ; i < ETH_ALEN; i++, j+=3 ){ ++ mac_addr[i]=key_2char2num(*(extra+j), *(extra+j+1)); ++ } ++ ++ ptdls_sta = rtw_get_stainfo(&padapter->stapriv, mac_addr); ++ if( ptdls_sta == NULL ) ++ return ret; ++ ptdls_sta->option=4; ++ ptdlsinfo->ch_sensing=1; ++ ++ rtw_tdls_cmd(padapter, ptdls_sta->hwaddr, TDLS_INIT_CH_SEN); ++ ++#endif ++ ++ return ret; ++ } ++ ++static int rtw_tdls_pson(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ int ret = 0; ++ ++#ifdef CONFIG_TDLS ++ ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ u8 i, j, mac_addr[ETH_ALEN]; ++ struct sta_info *ptdls_sta = NULL; ++ ++ DBG_8192C( "[%s] %s %d\n", __FUNCTION__, extra, wrqu->data.length -1 ); ++ ++ for( i=0, j=0 ; i < ETH_ALEN; i++, j+=3 ){ ++ mac_addr[i]=key_2char2num(*(extra+j), *(extra+j+1)); ++ } ++ ++ ptdls_sta = rtw_get_stainfo(&padapter->stapriv, mac_addr); ++ ++ issue_nulldata_to_TDLS_peer_STA(padapter, ptdls_sta, 1); ++ ++#endif ++ ++ return ret; ++} ++ ++static int rtw_tdls_psoff(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ int ret = 0; ++ ++#ifdef CONFIG_TDLS ++ ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct mlme_ext_priv *pmlmeext = &(padapter->mlmeextpriv); ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ u8 i, j, mac_addr[ETH_ALEN]; ++ struct sta_info *ptdls_sta = NULL; ++ ++ DBG_8192C( "[%s] %s %d\n", __FUNCTION__, extra, wrqu->data.length -1 ); ++ ++ for( i=0, j=0 ; i < ETH_ALEN; i++, j+=3 ){ ++ mac_addr[i]=key_2char2num(*(extra+j), *(extra+j+1)); ++ } ++ ++ ptdls_sta = rtw_get_stainfo(&padapter->stapriv, mac_addr); ++ ++ issue_nulldata_to_TDLS_peer_STA(padapter, ptdls_sta, 0); ++ ++#endif ++ ++ return ret; ++} ++ ++static int rtw_tdls_ch_switch_off(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ int ret = 0; ++ ++#ifdef CONFIG_TDLS ++ ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ u8 i, j, mac_addr[ETH_ALEN]; ++ struct sta_info *ptdls_sta = NULL; ++ ++ DBG_8192C( "[%s] %s %d\n", __FUNCTION__, extra, wrqu->data.length -1 ); ++ ++ for( i=0, j=0 ; i < ETH_ALEN; i++, j+=3 ){ ++ mac_addr[i]=key_2char2num(*(extra+j), *(extra+j+1)); ++ } ++ ++ ptdls_sta = rtw_get_stainfo(&padapter->stapriv, mac_addr); ++ ++ ptdls_sta->tdls_sta_state |= TDLS_SW_OFF_STATE; ++/* ++ if((ptdls_sta->tdls_sta_state & TDLS_AT_OFF_CH_STATE) && (ptdls_sta->tdls_sta_state & TDLS_PEER_AT_OFF_STATE)){ ++ pmlmeinfo->tdls_candidate_ch= pmlmeext->cur_channel; ++ issue_tdls_ch_switch_req(padapter, mac_addr); ++ DBG_8192C("issue tdls ch switch req back to base channel\n"); ++ } ++*/ ++ ++#endif ++ ++ return ret; ++} ++ ++static int rtw_tdls(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ int ret = 0; ++ ++#ifdef CONFIG_TDLS ++ ++ DBG_8192C( "[%s] extra = %s\n", __FUNCTION__, extra ); ++ ++ if ( _rtw_memcmp( extra, "setup=", 6 ) ) ++ { ++ wrqu->data.length -=6; ++ rtw_tdls_setup( dev, info, wrqu, &extra[6] ); ++ } ++ else if (_rtw_memcmp( extra, "tear=", 5 ) ) ++ { ++ wrqu->data.length -= 5; ++ rtw_tdls_teardown( dev, info, wrqu, &extra[5] ); ++ } ++ else if (_rtw_memcmp( extra, "dis=", 4 ) ) ++ { ++ wrqu->data.length -= 4; ++ rtw_tdls_discovery( dev, info, wrqu, &extra[4] ); ++ } ++ else if (_rtw_memcmp( extra, "sw=", 3 ) ) ++ { ++ wrqu->data.length -= 3; ++ rtw_tdls_ch_switch( dev, info, wrqu, &extra[3] ); ++ } ++ else if (_rtw_memcmp( extra, "swoff=", 6 ) ) ++ { ++ wrqu->data.length -= 6; ++ rtw_tdls_ch_switch_off( dev, info, wrqu, &extra[6] ); ++ } ++ else if (_rtw_memcmp( extra, "pson=", 5 ) ) ++ { ++ wrqu->data.length -= 5; ++ rtw_tdls_pson( dev, info, wrqu, &extra[5] ); ++ } ++ else if (_rtw_memcmp( extra, "psoff=", 6 ) ) ++ { ++ wrqu->data.length -= 6; ++ rtw_tdls_psoff( dev, info, wrqu, &extra[6] ); ++ } ++#endif ++ ++ return ret; ++} ++ ++ ++static int rtw_pm_set_lps(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ ++ int ret = 0; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct pwrctrl_priv *pwrctrlpriv = &padapter->pwrctrlpriv; ++ u8 mode = 0; ++ ++ switch( wrqu->data.length -1 ) ++ { ++ case 1: ++ { ++ mode = extra[ 0 ] - '0'; ++ break; ++ } ++ case 2: ++ { ++ mode = str_2char2num( extra[ 0 ], extra[ 1 ]); ++ break; ++ } ++ } ++ ++ if ( mode < PS_MODE_NUM ) ++ { ++ if(pwrctrlpriv->power_mgnt !=mode) ++ { ++ if(PS_MODE_ACTIVE == mode) ++ { ++ LeaveAllPowerSaveMode(padapter); ++ } ++ else ++ { ++ pwrctrlpriv->LpsIdleCount = 2; ++ } ++ pwrctrlpriv->power_mgnt = mode; ++ pwrctrlpriv->bLeisurePs = (PS_MODE_ACTIVE != pwrctrlpriv->power_mgnt)?_TRUE:_FALSE; ++ } ++ } ++ else ++ { ++ ret = -1; ++ } ++ ++ return ret; ++ ++} ++ ++static int rtw_pm_set_ips(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ _adapter *padapter = rtw_netdev_priv(dev); ++ struct pwrctrl_priv *pwrctrlpriv = &padapter->pwrctrlpriv; ++ unsigned mode = 0; ++ ++ sscanf(extra, "%u", &mode); ++ ++ if( mode == IPS_NORMAL || mode == IPS_LEVEL_2 ) { ++ rtw_ips_mode_req(pwrctrlpriv, mode); ++ pwrctrlpriv->power_mgnt = PS_MODE_MIN; ++ rtw_set_pwr_state_check_timer(pwrctrlpriv); ++ DBG_871X("%s %s\n", __FUNCTION__, mode == IPS_NORMAL?"IPS_NORMAL":"IPS_LEVEL_2"); ++ return 0; ++ } ++ else if(mode ==IPS_NONE){ ++ if(_FAIL == rfpwrstate_check(padapter)) ++ { ++ return -EFAULT; ++ } ++ pwrctrlpriv->power_mgnt = PS_MODE_ACTIVE; ++ } ++ else { ++ return -EFAULT; ++ } ++ return 0; ++} ++ ++static int rtw_pm_set(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ int ret = 0; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ ++ DBG_8192C( "[%s] extra = %s\n", __FUNCTION__, extra ); ++ ++ if ( _rtw_memcmp( extra, "lps=", 4 ) ) ++ { ++ wrqu->data.length -= 4; ++ rtw_pm_set_lps( dev, info, wrqu, &extra[4] ); ++ } ++ if ( _rtw_memcmp( extra, "ips=", 4 ) ) ++ { ++ wrqu->data.length -= 4; ++ rtw_pm_set_ips(dev, info, wrqu, &extra[4]); ++ } ++ ++ return ret; ++} ++ ++static int rtw_wowlan_ctrl(struct net_device *dev, ++ struct iw_request_info *info, ++ union iwreq_data *wrqu, char *extra) ++{ ++ int ret = 0; ++ struct oid_par_priv oid_par; ++ struct wowlan_ioctl_param *poidparam; ++ uint status=0; ++ u16 len; ++ u8 *pparmbuf = NULL, bset; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ ++ struct iw_point *p = &wrqu->data; ++ ++ //DBG_871X("+rtw_wowlan_ctrl\n"); ++ ++ //mutex_lock(&ioctl_mutex); ++ ++ if ((!p->length) || (!p->pointer)) { ++ ret = -EINVAL; ++ goto _rtw_wowlan_ctrl_exit; ++ } ++ ++ pparmbuf = NULL; ++ bset = (u8)(p->flags & 0xFFFF); ++ len = p->length; ++ pparmbuf = (u8*)rtw_malloc(len); ++ if (pparmbuf == NULL){ ++ ret = -ENOMEM; ++ goto _rtw_wowlan_ctrl_exit; ++ } ++ ++ if (copy_from_user(pparmbuf, p->pointer, len)) { ++ ret = -EFAULT; ++ goto _rtw_wowlan_ctrl_exit_free; ++ } ++ poidparam = (struct wowlan_ioctl_param *)pparmbuf; ++ ++ if(padapter->pwrctrlpriv.bSupportRemoteWakeup==_FALSE){ ++ ret = -EPERM; ++ DBG_871X("+rtw_wowlan_ctrl: Device didn't support the remote wakeup!!\n"); ++ goto _rtw_wowlan_ctrl_exit_free; ++ } ++ padapter->HalFunc.SetHwRegHandler(padapter,HW_VAR_WOWLAN,(u8 *)poidparam); ++ ++ DBG_871X("rtw_wowlan_ctrl: subcode [%d], len[%d], buffer_len[%d]\r\n", ++ poidparam->subcode, poidparam->len, len); ++ ++ if (copy_to_user(p->pointer, pparmbuf, len)) { ++ ret = -EFAULT; ++ } ++ ++ ++_rtw_wowlan_ctrl_exit_free: ++ //DBG_871X("-rtw_wowlan_ctrl( subcode = %d)\n", poidparam->subcode); ++ rtw_mfree(pparmbuf, len); ++_rtw_wowlan_ctrl_exit: ++ ++ ++ return ret; ++} ++ ++ ++#include ++int rtw_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) ++{ ++ struct iwreq *wrq = (struct iwreq *)rq; ++ int ret=0; ++ ++ switch (cmd) ++ { ++ case RTL_IOCTL_WPA_SUPPLICANT: ++ ret = wpa_supplicant_ioctl(dev, &wrq->u.data); ++ break; ++#ifdef CONFIG_AP_MODE ++ case RTL_IOCTL_HOSTAPD: ++ ret = rtw_hostapd_ioctl(dev, &wrq->u.data); ++ break; ++#endif ++ case (SIOCDEVPRIVATE+1): ++ ret = rtw_android_priv_cmd(dev, rq, cmd); ++ break; ++ default: ++ ret = -EOPNOTSUPP; ++ break; ++ } ++ ++ return ret; ++} ++ ++static iw_handler rtw_handlers[] = ++{ ++ NULL, /* SIOCSIWCOMMIT */ ++ rtw_wx_get_name, /* SIOCGIWNAME */ ++ dummy, /* SIOCSIWNWID */ ++ dummy, /* SIOCGIWNWID */ ++ rtw_wx_set_freq, /* SIOCSIWFREQ */ ++ rtw_wx_get_freq, /* SIOCGIWFREQ */ ++ rtw_wx_set_mode, /* SIOCSIWMODE */ ++ rtw_wx_get_mode, /* SIOCGIWMODE */ ++ dummy, /* SIOCSIWSENS */ ++ rtw_wx_get_sens, /* SIOCGIWSENS */ ++ NULL, /* SIOCSIWRANGE */ ++ rtw_wx_get_range, /* SIOCGIWRANGE */ ++ rtw_wx_set_priv, /* SIOCSIWPRIV */ ++ NULL, /* SIOCGIWPRIV */ ++ NULL, /* SIOCSIWSTATS */ ++ NULL, /* SIOCGIWSTATS */ ++ dummy, /* SIOCSIWSPY */ ++ dummy, /* SIOCGIWSPY */ ++ NULL, /* SIOCGIWTHRSPY */ ++ NULL, /* SIOCWIWTHRSPY */ ++ rtw_wx_set_wap, /* SIOCSIWAP */ ++ rtw_wx_get_wap, /* SIOCGIWAP */ ++ rtw_wx_set_mlme, /* request MLME operation; uses struct iw_mlme */ ++ dummy, /* SIOCGIWAPLIST -- depricated */ ++ rtw_wx_set_scan, /* SIOCSIWSCAN */ ++ rtw_wx_get_scan, /* SIOCGIWSCAN */ ++ rtw_wx_set_essid, /* SIOCSIWESSID */ ++ rtw_wx_get_essid, /* SIOCGIWESSID */ ++ dummy, /* SIOCSIWNICKN */ ++ rtw_wx_get_nick, /* SIOCGIWNICKN */ ++ NULL, /* -- hole -- */ ++ NULL, /* -- hole -- */ ++ rtw_wx_set_rate, /* SIOCSIWRATE */ ++ rtw_wx_get_rate, /* SIOCGIWRATE */ ++ dummy, /* SIOCSIWRTS */ ++ rtw_wx_get_rts, /* SIOCGIWRTS */ ++ rtw_wx_set_frag, /* SIOCSIWFRAG */ ++ rtw_wx_get_frag, /* SIOCGIWFRAG */ ++ dummy, /* SIOCSIWTXPOW */ ++ dummy, /* SIOCGIWTXPOW */ ++ dummy, /* SIOCSIWRETRY */ ++ rtw_wx_get_retry, /* SIOCGIWRETRY */ ++ rtw_wx_set_enc, /* SIOCSIWENCODE */ ++ rtw_wx_get_enc, /* SIOCGIWENCODE */ ++ dummy, /* SIOCSIWPOWER */ ++ rtw_wx_get_power, /* SIOCGIWPOWER */ ++ NULL, /*---hole---*/ ++ NULL, /*---hole---*/ ++ rtw_wx_set_gen_ie, /* SIOCSIWGENIE */ ++ NULL, /* SIOCGWGENIE */ ++ rtw_wx_set_auth, /* SIOCSIWAUTH */ ++ NULL, /* SIOCGIWAUTH */ ++ rtw_wx_set_enc_ext, /* SIOCSIWENCODEEXT */ ++ NULL, /* SIOCGIWENCODEEXT */ ++ rtw_wx_set_pmkid, /* SIOCSIWPMKSA */ ++ NULL, /*---hole---*/ ++}; ++ ++#if defined(CONFIG_MP_INCLUDED) && defined(CONFIG_MP_IWPRIV_SUPPORT) ++ ++static const struct iw_priv_args rtw_private_args[] = ++{ ++ { SIOCIWFIRSTPRIV + 0x00, IW_PRIV_TYPE_CHAR | 1024, 0 , ""}, //set ++ { SIOCIWFIRSTPRIV + 0x01, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK , ""},//get ++/* --- sub-ioctls definitions --- */ ++ { MP_START , IW_PRIV_TYPE_CHAR | 1024, 0, "mp_start" }, //set ++ { MP_PHYPARA, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_phypara" },//get ++ { MP_STOP , IW_PRIV_TYPE_CHAR | 1024, 0, "mp_stop" }, //set ++ { MP_CHANNEL , IW_PRIV_TYPE_CHAR | 1024 , IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_channel" },//get ++ { MP_BANDWIDTH , IW_PRIV_TYPE_CHAR | 1024, 0, "mp_bandwidth"}, //set ++ { MP_RATE , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_rate" },//get ++ { MP_RESET_STATS , IW_PRIV_TYPE_CHAR | 1024, 0, "mp_reset_stats"}, ++ { MP_QUERY , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK , "mp_query"}, //get ++ { MP_NULL, IW_PRIV_TYPE_CHAR | 128, 0,"NULL"},//set ++ { READ_REG , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "read_reg" }, ++ { MP_NULL, IW_PRIV_TYPE_CHAR | 128, 0,"NULL"},//set ++ { MP_RATE , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_rate" }, ++ { MP_NULL, IW_PRIV_TYPE_CHAR | 128, 0,"NULL"},//set ++ { READ_RF , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "read_rf" }, ++ { MP_NULL, IW_PRIV_TYPE_CHAR | 128, 0,"NULL"},//set ++ { MP_PSD , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_psd"}, ++ { MP_NULL, IW_PRIV_TYPE_CHAR | 128, 0,"NULL"},//set ++ { MP_DUMP, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_dump" }, ++ { MP_NULL, IW_PRIV_TYPE_CHAR | 128, 0,"NULL"},//set ++ { MP_TXPOWER , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_txpower"}, ++ { MP_NULL, IW_PRIV_TYPE_CHAR | 128, 0,"NULL"},//set ++ { MP_ANT_TX , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_ant_tx"}, ++ { MP_NULL, IW_PRIV_TYPE_CHAR | 128, 0,"NULL"},//set ++ { MP_ANT_RX , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_ant_rx"}, ++ { MP_NULL, IW_PRIV_TYPE_CHAR | 128, 0,"NULL"},//set ++ { WRITE_REG , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "write_reg" }, ++ { MP_NULL, IW_PRIV_TYPE_CHAR | 128, 0,"NULL"},//set ++ { WRITE_RF , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "write_rf" }, ++ { MP_NULL, IW_PRIV_TYPE_CHAR | 128, 0,"NULL"},//set ++ { MP_CTX , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_ctx"}, ++ { MP_NULL, IW_PRIV_TYPE_CHAR | 128, 0,"NULL"},//set ++ { MP_ARX , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_arx"}, ++ { MP_ANT_RX , IW_PRIV_TYPE_CHAR | 1024, 0, "mp_ant_rx"}, ++ { MP_THER , IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "mp_ther"}, ++ { EFUSE_SET, IW_PRIV_TYPE_CHAR | 1024, 0, "efuse_set" }, ++ { EFUSE_GET, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK, "efuse_get" }, ++ { MP_PWRTRK , IW_PRIV_TYPE_CHAR | 1024, 0, "mp_pwrtrk"}, ++ { MP_IOCTL, IW_PRIV_TYPE_CHAR | 1024, 0, "mp_ioctl"}, // mp_ioctl ++ ++ ++ { SIOCIWFIRSTPRIV + 0x02, IW_PRIV_TYPE_CHAR | 1024, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_MASK , "test"},//set ++}; ++ ++ ++static iw_handler rtw_private_handler[] = ++{ ++ rtw_mp_set, ++ rtw_mp_get, ++}; ++ ++ ++#else // not inlucde MP ++ ++static const struct iw_priv_args rtw_private_args[] = { ++ { ++ SIOCIWFIRSTPRIV + 0x0, ++ IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 2, 0, "rtw_write32" ++ }, ++ { ++ SIOCIWFIRSTPRIV + 0x1, ++ IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_FIXED | IFNAMSIZ, "rtw_read32" ++ }, ++ { ++ SIOCIWFIRSTPRIV + 0x2, 0, 0, "driver_ext" ++ }, ++ { ++ SIOCIWFIRSTPRIV + 0x3, 0, 0, "" // mp_ioctl ++ }, ++ { ++ SIOCIWFIRSTPRIV + 0x4, ++ IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, 0, "apinfo" ++ }, ++ { ++ SIOCIWFIRSTPRIV + 0x5, ++ IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 2, 0, "setpid" ++ }, ++ { ++ SIOCIWFIRSTPRIV + 0x6, ++ IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, 0, "wps_start" ++ }, ++//for PLATFORM_MT53XX ++ { ++ SIOCIWFIRSTPRIV + 0x7, ++ IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, 0, "get_sensitivity" ++ }, ++ { ++ SIOCIWFIRSTPRIV + 0x8, ++ IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, 0, "wps_prob_req_ie" ++ }, ++ { ++ SIOCIWFIRSTPRIV + 0x9, ++ IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, 0, "wps_assoc_req_ie" ++ }, ++ ++//for RTK_DMP_PLATFORM ++ { ++ SIOCIWFIRSTPRIV + 0xA, ++ IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 1, 0, "channel_plan" ++ }, ++ ++ { ++ SIOCIWFIRSTPRIV + 0xB, ++ IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 2, 0, "dbg" ++ }, ++ { ++ SIOCIWFIRSTPRIV + 0xC, ++ IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 3, 0, "rfw" ++ }, ++ { ++ SIOCIWFIRSTPRIV + 0xD, ++ IW_PRIV_TYPE_INT | IW_PRIV_SIZE_FIXED | 2, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_FIXED | IFNAMSIZ, "rfr" ++ }, ++ ++ { ++ SIOCIWFIRSTPRIV + 0xE,0,0, "wowlan_ctrl" ++ }, ++ ++ { ++ SIOCIWFIRSTPRIV + 0x10, ++ IW_PRIV_TYPE_CHAR | P2P_PRIVATE_IOCTL_SET_LEN, 0, "p2p_set" ++ }, ++ { ++ SIOCIWFIRSTPRIV + 0x11, ++ IW_PRIV_TYPE_CHAR | P2P_PRIVATE_IOCTL_SET_LEN, IW_PRIV_TYPE_CHAR | IW_PRIV_SIZE_FIXED | P2P_PRIVATE_IOCTL_SET_LEN , "p2p_get" ++ }, ++ { ++ SIOCIWFIRSTPRIV + 0x12, ++ IW_PRIV_TYPE_CHAR | P2P_PRIVATE_IOCTL_SET_LEN, IW_PRIV_TYPE_CHAR | IFNAMSIZ , "p2p_get2" ++ }, ++#ifdef CONFIG_TDLS ++ {SIOCIWFIRSTPRIV + 0x13, IW_PRIV_TYPE_CHAR | 128, 0,"NULL"}, ++ { ++ SIOCIWFIRSTPRIV + 0x14, ++ IW_PRIV_TYPE_CHAR | 64, 0, "tdls" ++ }, ++#endif ++ { ++ SIOCIWFIRSTPRIV + 0x16, ++ IW_PRIV_TYPE_CHAR | P2P_PRIVATE_IOCTL_SET_LEN, 0, "pm_set" ++ }, ++ ++ {SIOCIWFIRSTPRIV + 0x18, IW_PRIV_TYPE_CHAR | IFNAMSIZ , 0 , "rereg_nd_name"}, ++ ++ {SIOCIWFIRSTPRIV + 0x1A, IW_PRIV_TYPE_CHAR | 128, 0, "efuse_set"}, ++ {SIOCIWFIRSTPRIV + 0x1B, IW_PRIV_TYPE_CHAR | 128, IW_PRIV_TYPE_CHAR |IW_PRIV_SIZE_FIXED |0x700 ,"efuse_get"}, ++ ++}; ++ ++static iw_handler rtw_private_handler[] = ++{ ++ rtw_wx_write32, //0x00 ++ rtw_wx_read32, //0x01 ++ rtw_drvext_hdl, //0x02 ++ rtw_mp_ioctl_hdl, //0x03 ++ ++// for MM DTV platform ++ rtw_get_ap_info, //0x04 ++ ++ rtw_set_pid, //0x05 ++ rtw_wps_start, //0x06 ++ ++// for PLATFORM_MT53XX ++ rtw_wx_get_sensitivity, //0x07 ++ rtw_wx_set_mtk_wps_probe_ie, //0x08 ++ rtw_wx_set_mtk_wps_ie, //0x09 ++ ++// for RTK_DMP_PLATFORM ++// Set Channel depend on the country code ++ rtw_wx_set_channel_plan, //0x0A ++ ++ rtw_dbg_port, //0x0B ++ rtw_wx_write_rf, //0x0C ++ rtw_wx_read_rf, //0x0D ++ ++ ++ rtw_wowlan_ctrl, //0x0E ++ ++ rtw_wx_priv_null, //0x0F ++ ++ rtw_p2p_set, //0x10 ++ rtw_p2p_get, //0x11 ++ rtw_p2p_get2, //0x12 ++ ++ NULL, //0x13 ++ rtw_tdls, //0x14 ++ rtw_wx_priv_null, //0x15 ++ ++ rtw_pm_set, //0x16 ++ rtw_wx_priv_null, //0x17 ++ rtw_rereg_nd_name, //0x18 ++ rtw_wx_priv_null, //0x19 ++ ++ rtw_mp_efuse_set, //0x1A ++ rtw_mp_efuse_get, //0x1B ++ // 0x1C is reserved for hostapd ++}; ++ ++#endif // #if defined(CONFIG_MP_INCLUDED) && defined(CONFIG_MP_IWPRIV_SUPPORT) ++ ++#if WIRELESS_EXT >= 17 ++static struct iw_statistics *rtw_get_wireless_stats(struct net_device *dev) ++{ ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(dev); ++ struct iw_statistics *piwstats=&padapter->iwstats; ++ int tmp_level = 0; ++ int tmp_qual = 0; ++ int tmp_noise = 0; ++ ++ if (check_fwstate(&padapter->mlmepriv, _FW_LINKED) != _TRUE) ++ { ++ piwstats->qual.qual = 0; ++ piwstats->qual.level = 0; ++ piwstats->qual.noise = 0; ++ //DBG_8192C("No link level:%d, qual:%d, noise:%d\n", tmp_level, tmp_qual, tmp_noise); ++ } ++ else{ ++ #ifdef CONFIG_SIGNAL_DISPLAY_DBM ++ tmp_level = translate_percentage_to_dbm(padapter->recvpriv.signal_strength); ++ #else ++ tmp_level = padapter->recvpriv.signal_strength; ++ #endif ++ ++ tmp_qual = padapter->recvpriv.signal_qual; ++ tmp_noise =padapter->recvpriv.noise; ++ //DBG_8192C("level:%d, qual:%d, noise:%d, rssi (%d)\n", tmp_level, tmp_qual, tmp_noise,padapter->recvpriv.rssi); ++ ++ piwstats->qual.level = tmp_level; ++ piwstats->qual.qual = tmp_qual; ++ piwstats->qual.noise = tmp_noise; ++ } ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,14)) ++ piwstats->qual.updated = IW_QUAL_ALL_UPDATED ;//|IW_QUAL_DBM; ++#else ++#ifdef RTK_DMP_PLATFORM ++ //IW_QUAL_DBM= 0x8, if driver use this flag, wireless extension will show value of dbm. ++ //remove this flag for show percentage 0~100 ++ piwstats->qual.updated = 0x07; ++#else ++ piwstats->qual.updated = 0x0f; ++#endif ++#endif ++ ++ #ifdef CONFIG_SIGNAL_DISPLAY_DBM ++ piwstats->qual.updated = piwstats->qual.updated | IW_QUAL_DBM; ++ #endif ++ ++ return &padapter->iwstats; ++} ++#endif ++ ++struct iw_handler_def rtw_handlers_def = ++{ ++ .standard = rtw_handlers, ++ .num_standard = sizeof(rtw_handlers) / sizeof(iw_handler), ++ .private = rtw_private_handler, ++ .private_args = (struct iw_priv_args *)rtw_private_args, ++ .num_private = sizeof(rtw_private_handler) / sizeof(iw_handler), ++ .num_private_args = sizeof(rtw_private_args) / sizeof(struct iw_priv_args), ++#if WIRELESS_EXT >= 17 ++ .get_wireless_stats = rtw_get_wireless_stats, ++#endif ++}; ++ +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/os_dep/linux/mlme_linux.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/os_dep/linux/mlme_linux.c 2013-07-26 19:36:07.000000000 +0000 +@@ -0,0 +1,740 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++ ++ ++#define _MLME_OSDEP_C_ ++ ++#include ++#include ++#include ++#include ++ ++ ++#ifdef RTK_DMP_PLATFORM ++void Linkup_workitem_callback(struct work_struct *work) ++{ ++ struct mlme_priv *pmlmepriv = container_of(work, struct mlme_priv, Linkup_workitem); ++ _adapter *padapter = container_of(pmlmepriv, _adapter, mlmepriv); ++ ++_func_enter_; ++ ++ RT_TRACE(_module_mlme_osdep_c_,_drv_info_,("+ Linkup_workitem_callback\n")); ++ ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,12)) ++ kobject_uevent(&padapter->pnetdev->dev.kobj, KOBJ_LINKUP); ++#else ++ kobject_hotplug(&padapter->pnetdev->class_dev.kobj, KOBJ_LINKUP); ++#endif ++ ++_func_exit_; ++} ++ ++void Linkdown_workitem_callback(struct work_struct *work) ++{ ++ struct mlme_priv *pmlmepriv = container_of(work, struct mlme_priv, Linkdown_workitem); ++ _adapter *padapter = container_of(pmlmepriv, _adapter, mlmepriv); ++ ++_func_enter_; ++ ++ RT_TRACE(_module_mlme_osdep_c_,_drv_info_,("+ Linkdown_workitem_callback\n")); ++ ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,12)) ++ kobject_uevent(&padapter->pnetdev->dev.kobj, KOBJ_LINKDOWN); ++#else ++ kobject_hotplug(&padapter->pnetdev->class_dev.kobj, KOBJ_LINKDOWN); ++#endif ++ ++_func_exit_; ++} ++#endif ++ ++ ++/* ++void sitesurvey_ctrl_handler(void *FunctionContext) ++{ ++ _adapter *adapter = (_adapter *)FunctionContext; ++ ++ _sitesurvey_ctrl_handler(adapter); ++ ++ _set_timer(&adapter->mlmepriv.sitesurveyctrl.sitesurvey_ctrl_timer, 3000); ++} ++*/ ++ ++void rtw_join_timeout_handler (void *FunctionContext) ++{ ++ _adapter *adapter = (_adapter *)FunctionContext; ++ _rtw_join_timeout_handler(adapter); ++} ++ ++ ++void _rtw_scan_timeout_handler (void *FunctionContext) ++{ ++ _adapter *adapter = (_adapter *)FunctionContext; ++ rtw_scan_timeout_handler(adapter); ++} ++ ++ ++void _dynamic_check_timer_handlder (void *FunctionContext) ++{ ++ _adapter *adapter = (_adapter *)FunctionContext; ++ ++ rtw_dynamic_check_timer_handlder(adapter); ++ ++ _set_timer(&adapter->mlmepriv.dynamic_chk_timer, 2000); ++} ++ ++#ifdef CONFIG_SET_SCAN_DENY_TIMER ++void _rtw_set_scan_deny_timer_hdl(void *FunctionContext) ++{ ++ _adapter *adapter = (_adapter *)FunctionContext; ++ rtw_set_scan_deny_timer_hdl(adapter); ++} ++#endif ++ ++ ++void rtw_init_mlme_timer(_adapter *padapter) ++{ ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ ++ _init_timer(&(pmlmepriv->assoc_timer), padapter->pnetdev, rtw_join_timeout_handler, padapter); ++ //_init_timer(&(pmlmepriv->sitesurveyctrl.sitesurvey_ctrl_timer), padapter->pnetdev, sitesurvey_ctrl_handler, padapter); ++ _init_timer(&(pmlmepriv->scan_to_timer), padapter->pnetdev, _rtw_scan_timeout_handler, padapter); ++ ++ _init_timer(&(pmlmepriv->dynamic_chk_timer), padapter->pnetdev, _dynamic_check_timer_handlder, padapter); ++ ++ #ifdef CONFIG_SET_SCAN_DENY_TIMER ++ _init_timer(&(pmlmepriv->set_scan_deny_timer), padapter->pnetdev, _rtw_set_scan_deny_timer_hdl, padapter); ++ #endif ++ ++#ifdef RTK_DMP_PLATFORM ++ _init_workitem(&(pmlmepriv->Linkup_workitem), Linkup_workitem_callback, padapter); ++ _init_workitem(&(pmlmepriv->Linkdown_workitem), Linkdown_workitem_callback, padapter); ++#endif ++ ++} ++ ++extern void rtw_indicate_wx_assoc_event(_adapter *padapter); ++extern void rtw_indicate_wx_disassoc_event(_adapter *padapter); ++ ++void rtw_os_indicate_connect(_adapter *adapter) ++{ ++ struct mlme_priv *pmlmepriv = &adapter->mlmepriv; ++ ++_func_enter_; ++ ++#ifdef CONFIG_IOCTL_CFG80211 ++ rtw_cfg80211_indicate_connect(adapter); ++#endif //CONFIG_IOCTL_CFG80211 ++ ++ rtw_indicate_wx_assoc_event(adapter); ++ ++ netif_carrier_on(adapter->pnetdev); ++ ++ if(adapter->pid[2] !=0) ++ rtw_signal_process(adapter->pid[2], SIGALRM); ++ ++#ifdef RTK_DMP_PLATFORM ++ _set_workitem(&pmlmepriv->Linkup_workitem); ++#endif ++ ++_func_exit_; ++ ++} ++ ++extern void indicate_wx_scan_complete_event(_adapter *padapter); ++void rtw_os_indicate_scan_done( _adapter *padapter, bool aborted) ++{ ++#ifdef CONFIG_IOCTL_CFG80211 ++ rtw_cfg80211_indicate_scan_done(wdev_to_priv(padapter->rtw_wdev), aborted); ++#endif ++ indicate_wx_scan_complete_event(padapter); ++} ++ ++static RT_PMKID_LIST backupPMKIDList[ NUM_PMKID_CACHE ]; ++void rtw_reset_securitypriv( _adapter *adapter ) ++{ ++ u8 backupPMKIDIndex = 0; ++ u8 backupTKIPCountermeasure = 0x00; ++ u32 backupTKIPcountermeasure_time = 0; ++ ++ if(adapter->securitypriv.dot11AuthAlgrthm == dot11AuthAlgrthm_8021X)//802.1x ++ { ++ // Added by Albert 2009/02/18 ++ // We have to backup the PMK information for WiFi PMK Caching test item. ++ // ++ // Backup the btkip_countermeasure information. ++ // When the countermeasure is trigger, the driver have to disconnect with AP for 60 seconds. ++ ++ _rtw_memset( &backupPMKIDList[ 0 ], 0x00, sizeof( RT_PMKID_LIST ) * NUM_PMKID_CACHE ); ++ ++ _rtw_memcpy( &backupPMKIDList[ 0 ], &adapter->securitypriv.PMKIDList[ 0 ], sizeof( RT_PMKID_LIST ) * NUM_PMKID_CACHE ); ++ backupPMKIDIndex = adapter->securitypriv.PMKIDIndex; ++ backupTKIPCountermeasure = adapter->securitypriv.btkip_countermeasure; ++ backupTKIPcountermeasure_time = adapter->securitypriv.btkip_countermeasure_time; ++ ++ _rtw_memset((unsigned char *)&adapter->securitypriv, 0, sizeof (struct security_priv)); ++ //_init_timer(&(adapter->securitypriv.tkip_timer),adapter->pnetdev, rtw_use_tkipkey_handler, adapter); ++ ++ // Added by Albert 2009/02/18 ++ // Restore the PMK information to securitypriv structure for the following connection. ++ _rtw_memcpy( &adapter->securitypriv.PMKIDList[ 0 ], &backupPMKIDList[ 0 ], sizeof( RT_PMKID_LIST ) * NUM_PMKID_CACHE ); ++ adapter->securitypriv.PMKIDIndex = backupPMKIDIndex; ++ adapter->securitypriv.btkip_countermeasure = backupTKIPCountermeasure; ++ adapter->securitypriv.btkip_countermeasure_time = backupTKIPcountermeasure_time; ++ ++ adapter->securitypriv.ndisauthtype = Ndis802_11AuthModeOpen; ++ adapter->securitypriv.ndisencryptstatus = Ndis802_11WEPDisabled; ++ ++ } ++ else //reset values in securitypriv ++ { ++ //if(adapter->mlmepriv.fw_state & WIFI_STATION_STATE) ++ //{ ++ struct security_priv *psec_priv=&adapter->securitypriv; ++ ++ psec_priv->dot11AuthAlgrthm =dot11AuthAlgrthm_Open; //open system ++ psec_priv->dot11PrivacyAlgrthm = _NO_PRIVACY_; ++ psec_priv->dot11PrivacyKeyIndex = 0; ++ ++ psec_priv->dot118021XGrpPrivacy = _NO_PRIVACY_; ++ psec_priv->dot118021XGrpKeyid = 1; ++ ++ psec_priv->ndisauthtype = Ndis802_11AuthModeOpen; ++ psec_priv->ndisencryptstatus = Ndis802_11WEPDisabled; ++ psec_priv->wps_phase = _FALSE; ++ //} ++ } ++} ++ ++void rtw_os_indicate_disconnect( _adapter *adapter ) ++{ ++ //RT_PMKID_LIST backupPMKIDList[ NUM_PMKID_CACHE ]; ++ ++_func_enter_; ++ ++#ifdef CONFIG_IOCTL_CFG80211 ++ rtw_cfg80211_indicate_disconnect(adapter); ++#endif //CONFIG_IOCTL_CFG80211 ++ ++ rtw_indicate_wx_disassoc_event(adapter); ++ netif_carrier_off(adapter->pnetdev); ++ ++#ifdef RTK_DMP_PLATFORM ++ _set_workitem(&adapter->mlmepriv.Linkdown_workitem); ++#endif ++ rtw_reset_securitypriv( adapter ); ++ ++_func_exit_; ++ ++} ++ ++void rtw_report_sec_ie(_adapter *adapter,u8 authmode,u8 *sec_ie) ++{ ++ uint len; ++ u8 *buff,*p,i; ++ union iwreq_data wrqu; ++ ++_func_enter_; ++ ++ RT_TRACE(_module_mlme_osdep_c_,_drv_info_,("+rtw_report_sec_ie, authmode=%d\n", authmode)); ++ ++ buff = NULL; ++ if(authmode==_WPA_IE_ID_) ++ { ++ RT_TRACE(_module_mlme_osdep_c_,_drv_info_,("rtw_report_sec_ie, authmode=%d\n", authmode)); ++ ++ buff = rtw_malloc(IW_CUSTOM_MAX); ++ ++ _rtw_memset(buff,0,IW_CUSTOM_MAX); ++ ++ p=buff; ++ ++ p+=sprintf(p,"ASSOCINFO(ReqIEs="); ++ ++ len = sec_ie[1]+2; ++ len = (len < IW_CUSTOM_MAX) ? len:IW_CUSTOM_MAX; ++ ++ for(i=0;ipnetdev,IWEVCUSTOM,&wrqu,buff); ++ ++ if(buff) ++ rtw_mfree(buff, IW_CUSTOM_MAX); ++ ++ } ++ ++_func_exit_; ++ ++} ++ ++void _survey_timer_hdl (void *FunctionContext) ++{ ++ _adapter *padapter = (_adapter *)FunctionContext; ++ ++ survey_timer_hdl(padapter); ++} ++ ++void _link_timer_hdl (void *FunctionContext) ++{ ++ _adapter *padapter = (_adapter *)FunctionContext; ++ link_timer_hdl(padapter); ++} ++ ++void _addba_timer_hdl(void *FunctionContext) ++{ ++ struct sta_info *psta = (struct sta_info *)FunctionContext; ++ addba_timer_hdl(psta); ++} ++ ++void init_addba_retry_timer(_adapter *padapter, struct sta_info *psta) ++{ ++ ++ _init_timer(&psta->addba_retry_timer, padapter->pnetdev, _addba_timer_hdl, psta); ++} ++ ++#ifdef CONFIG_TDLS ++void _TPK_timer_hdl(void *FunctionContext) ++{ ++ struct sta_info *ptdls_sta = (struct sta_info *)FunctionContext; ++ ++ ptdls_sta->TPK_count++; ++ //TPK_timer set 1000 as default ++ //retry timer should set at least 301 sec. ++ if(ptdls_sta->TPK_count==TPK_RESEND_COUNT){ ++ ptdls_sta->TPK_count=0; ++ issue_tdls_setup_req(ptdls_sta->padapter, ptdls_sta->hwaddr); ++ } ++ ++ _set_timer(&ptdls_sta->TPK_timer, ptdls_sta->TDLS_PeerKey_Lifetime/TPK_RESEND_COUNT); ++} ++ ++void init_TPK_timer(_adapter *padapter, struct sta_info *psta) ++{ ++ psta->padapter=padapter; ++ ++ _init_timer(&psta->TPK_timer, padapter->pnetdev, _TPK_timer_hdl, psta); ++} ++ ++// TDLS_DONE_CH_SEN: channel sensing and report candidate channel ++// TDLS_OFF_CH: first time set channel to off channel ++// TDLS_BASE_CH: when go back to the channel linked with AP, send null data to peer STA as an indication ++void _ch_switch_timer_hdl(void *FunctionContext) ++{ ++ ++ struct sta_info *ptdls_sta = (struct sta_info *)FunctionContext; ++ _adapter *padapter = ptdls_sta->padapter; ++ ++ if( ptdls_sta->option == TDLS_DONE_CH_SEN ){ ++ rtw_tdls_cmd(padapter, ptdls_sta->hwaddr, TDLS_DONE_CH_SEN); ++ }else if( ptdls_sta->option == TDLS_OFF_CH ){ ++ issue_nulldata_to_TDLS_peer_STA(ptdls_sta->padapter, ptdls_sta, 0); ++ _set_timer(&ptdls_sta->base_ch_timer, 500); ++ }else if( ptdls_sta->option == TDLS_BASE_CH){ ++ issue_nulldata_to_TDLS_peer_STA(ptdls_sta->padapter, ptdls_sta, 0); ++ } ++} ++ ++void init_ch_switch_timer(_adapter *padapter, struct sta_info *psta) ++{ ++ psta->padapter=padapter; ++ _init_timer(&psta->option_timer, padapter->pnetdev, _ch_switch_timer_hdl, psta); ++} ++ ++void _base_ch_timer_hdl(void *FunctionContext) ++{ ++ struct sta_info *ptdls_sta = (struct sta_info *)FunctionContext; ++ rtw_tdls_cmd(ptdls_sta->padapter, ptdls_sta->hwaddr, TDLS_P_OFF_CH); ++} ++ ++void init_base_ch_timer(_adapter *padapter, struct sta_info *psta) ++{ ++ psta->padapter=padapter; ++ _init_timer(&psta->base_ch_timer, padapter->pnetdev, _base_ch_timer_hdl, psta); ++} ++ ++void _off_ch_timer_hdl(void *FunctionContext) ++{ ++ struct sta_info *ptdls_sta = (struct sta_info *)FunctionContext; ++ rtw_tdls_cmd(ptdls_sta->padapter, ptdls_sta->hwaddr, TDLS_P_BASE_CH ); ++ } ++ ++void init_off_ch_timer(_adapter *padapter, struct sta_info *psta) ++{ ++ psta->padapter=padapter; ++ _init_timer(&psta->off_ch_timer, padapter->pnetdev, _off_ch_timer_hdl, psta); ++} ++ ++void _tdls_handshake_timer_hdl(void *FunctionContext) ++{ ++ struct sta_info *ptdls_sta = (struct sta_info *)FunctionContext; ++ ++ if(ptdls_sta != NULL) ++ { ++ if( !(ptdls_sta->tdls_sta_state & TDLS_LINKED_STATE) ) ++ { ++ printk("HANDSHAKE TIME OUT\n"); ++ free_tdls_sta(ptdls_sta->padapter, ptdls_sta); ++ } ++ } ++} ++ ++void init_handshake_timer(_adapter *padapter, struct sta_info *psta) ++{ ++ psta->padapter=padapter; ++ _init_timer(&psta->handshake_timer, padapter->pnetdev, _tdls_handshake_timer_hdl, psta); ++} ++ ++//Check tdls peer sta alive. ++void _tdls_alive_timer_phase1_hdl(void *FunctionContext) ++{ ++ _irqL irqL; ++ struct sta_info *ptdls_sta = (struct sta_info *)FunctionContext; ++ _adapter *padapter = ptdls_sta->padapter; ++ struct tdls_info *ptdlsinfo = &padapter->tdlsinfo; ++ ++ _enter_critical_bh(&ptdlsinfo->hdl_lock, &irqL); ++ ptdls_sta->timer_flag = 1; ++ _exit_critical_bh(&ptdlsinfo->hdl_lock, &irqL); ++ ++ ptdls_sta->tdls_sta_state &= (~TDLS_ALIVE_STATE); ++ ++ DBG_8192C("issue_tdls_dis_req to check alive\n"); ++ issue_tdls_dis_req( padapter, ptdls_sta->hwaddr); ++ rtw_tdls_cmd(padapter, ptdls_sta->hwaddr, TDLS_CKALV_PH1); ++ sta_update_last_rx_pkts(ptdls_sta); ++ ++ if ( ptdls_sta->timer_flag == 2 ) ++ rtw_tdls_cmd(padapter, ptdls_sta->hwaddr, TDLS_FREE_STA); ++ else ++ { ++ _enter_critical_bh(&ptdlsinfo->hdl_lock, &irqL); ++ ptdls_sta->timer_flag = 0; ++ _exit_critical_bh(&ptdlsinfo->hdl_lock, &irqL); ++ } ++ ++} ++ ++void _tdls_alive_timer_phase2_hdl(void *FunctionContext) ++{ ++ _irqL irqL; ++ struct sta_info *ptdls_sta = (struct sta_info *)FunctionContext; ++ _adapter *padapter = ptdls_sta->padapter; ++ struct tdls_info *ptdlsinfo = &padapter->tdlsinfo; ++ ++ _enter_critical_bh(&(ptdlsinfo->hdl_lock), &irqL); ++ ptdls_sta->timer_flag = 1; ++ _exit_critical_bh(&ptdlsinfo->hdl_lock, &irqL); ++ ++ if( (ptdls_sta->tdls_sta_state & TDLS_ALIVE_STATE) && ++ (sta_last_rx_pkts(ptdls_sta) + 3 <= sta_rx_pkts(ptdls_sta)) ) ++ { ++ DBG_8192C("TDLS STA ALIVE\n"); ++ ptdls_sta->alive_count = 0; ++ rtw_tdls_cmd(padapter, ptdls_sta->hwaddr, TDLS_CKALV_PH2); ++ } ++ else ++ { ++ DBG_8192C("TDLS STA TOO FAR\n"); ++ ptdls_sta->alive_count++; ++ if( ptdls_sta->alive_count == TDLS_ALIVE_COUNT ) ++ { ++ ptdls_sta->stat_code = _RSON_TDLS_TEAR_TOOFAR_; ++ issue_tdls_teardown(padapter, ptdls_sta->hwaddr); ++ } ++ else ++ { ++ rtw_tdls_cmd(padapter, ptdls_sta->hwaddr, TDLS_CKALV_PH2); ++ } ++} ++ ++ if ( ptdls_sta->timer_flag == 2 ) ++ rtw_tdls_cmd(padapter, ptdls_sta->hwaddr, TDLS_FREE_STA); ++ else ++{ ++ _enter_critical_bh(&(ptdlsinfo->hdl_lock), &irqL); ++ ptdls_sta->timer_flag = 0; ++ _exit_critical_bh(&ptdlsinfo->hdl_lock, &irqL); ++} ++ ++} ++ ++void init_tdls_alive_timer(_adapter *padapter, struct sta_info *psta) ++{ ++ psta->padapter=padapter; ++ _init_timer(&psta->alive_timer1, padapter->pnetdev, _tdls_alive_timer_phase1_hdl, psta); ++ _init_timer(&psta->alive_timer2, padapter->pnetdev, _tdls_alive_timer_phase2_hdl, psta); ++} ++#endif //CONFIG_TDLS ++ ++/* ++void _reauth_timer_hdl(void *FunctionContext) ++{ ++ _adapter *padapter = (_adapter *)FunctionContext; ++ reauth_timer_hdl(padapter); ++} ++ ++void _reassoc_timer_hdl(void *FunctionContext) ++{ ++ _adapter *padapter = (_adapter *)FunctionContext; ++ reassoc_timer_hdl(padapter); ++} ++*/ ++ ++void init_mlme_ext_timer(_adapter *padapter) ++{ ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ ++ _init_timer(&pmlmeext->survey_timer, padapter->pnetdev, _survey_timer_hdl, padapter); ++ _init_timer(&pmlmeext->link_timer, padapter->pnetdev, _link_timer_hdl, padapter); ++ //_init_timer(&pmlmeext->ADDBA_timer, padapter->pnetdev, _addba_timer_hdl, padapter); ++ ++ //_init_timer(&pmlmeext->reauth_timer, padapter->pnetdev, _reauth_timer_hdl, padapter); ++ //_init_timer(&pmlmeext->reassoc_timer, padapter->pnetdev, _reassoc_timer_hdl, padapter); ++} ++ ++#ifdef CONFIG_AP_MODE ++ ++void rtw_indicate_sta_assoc_event(_adapter *padapter, struct sta_info *psta) ++{ ++ union iwreq_data wrqu; ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ ++ if(psta==NULL) ++ return; ++ ++ if(psta->aid > NUM_STA) ++ return; ++ ++ if(pstapriv->sta_aid[psta->aid - 1] != psta) ++ return; ++ ++ ++ wrqu.addr.sa_family = ARPHRD_ETHER; ++ ++ _rtw_memcpy(wrqu.addr.sa_data, psta->hwaddr, ETH_ALEN); ++ ++ DBG_871X("+rtw_indicate_sta_assoc_event\n"); ++ ++ wireless_send_event(padapter->pnetdev, IWEVREGISTERED, &wrqu, NULL); ++ ++} ++ ++void rtw_indicate_sta_disassoc_event(_adapter *padapter, struct sta_info *psta) ++{ ++ union iwreq_data wrqu; ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ ++ if(psta==NULL) ++ return; ++ ++ if(psta->aid > NUM_STA) ++ return; ++ ++ if(pstapriv->sta_aid[psta->aid - 1] != psta) ++ return; ++ ++ ++ wrqu.addr.sa_family = ARPHRD_ETHER; ++ ++ _rtw_memcpy(wrqu.addr.sa_data, psta->hwaddr, ETH_ALEN); ++ ++ DBG_871X("+rtw_indicate_sta_disassoc_event\n"); ++ ++ wireless_send_event(padapter->pnetdev, IWEVEXPIRED, &wrqu, NULL); ++ ++} ++ ++ ++#ifdef CONFIG_HOSTAPD_MLME ++ ++static int mgnt_xmit_entry(struct sk_buff *skb, struct net_device *pnetdev) ++{ ++ struct hostapd_priv *phostapdpriv = rtw_netdev_priv(pnetdev); ++ _adapter *padapter = (_adapter *)phostapdpriv->padapter; ++ ++ //DBG_8192C("%s\n", __FUNCTION__); ++ ++ return padapter->HalFunc.hostap_mgnt_xmit_entry(padapter, skb); ++} ++ ++static int mgnt_netdev_open(struct net_device *pnetdev) ++{ ++ struct hostapd_priv *phostapdpriv = rtw_netdev_priv(pnetdev); ++ ++ DBG_8192C("mgnt_netdev_open: MAC Address:" MAC_FMT "\n", MAC_ARG(pnetdev->dev_addr)); ++ ++ ++ init_usb_anchor(&phostapdpriv->anchored); ++ ++ if(!netif_queue_stopped(pnetdev)) ++ netif_start_queue(pnetdev); ++ else ++ netif_wake_queue(pnetdev); ++ ++ ++ netif_carrier_on(pnetdev); ++ ++ //rtw_write16(phostapdpriv->padapter, 0x0116, 0x0100);//only excluding beacon ++ ++ return 0; ++} ++static int mgnt_netdev_close(struct net_device *pnetdev) ++{ ++ struct hostapd_priv *phostapdpriv = rtw_netdev_priv(pnetdev); ++ ++ DBG_8192C("%s\n", __FUNCTION__); ++ ++ usb_kill_anchored_urbs(&phostapdpriv->anchored); ++ ++ netif_carrier_off(pnetdev); ++ ++ if (!netif_queue_stopped(pnetdev)) ++ netif_stop_queue(pnetdev); ++ ++ //rtw_write16(phostapdpriv->padapter, 0x0116, 0x3f3f); ++ ++ return 0; ++} ++ ++#if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,29)) ++static const struct net_device_ops rtl871x_mgnt_netdev_ops = { ++ .ndo_open = mgnt_netdev_open, ++ .ndo_stop = mgnt_netdev_close, ++ .ndo_start_xmit = mgnt_xmit_entry, ++ //.ndo_set_mac_address = r871x_net_set_mac_address, ++ //.ndo_get_stats = r871x_net_get_stats, ++ //.ndo_do_ioctl = r871x_mp_ioctl, ++}; ++#endif ++ ++int hostapd_mode_init(_adapter *padapter) ++{ ++ unsigned char mac[ETH_ALEN]; ++ struct hostapd_priv *phostapdpriv; ++ struct net_device *pnetdev; ++ ++ pnetdev = rtw_alloc_etherdev(sizeof(struct hostapd_priv)); ++ if (!pnetdev) ++ return -ENOMEM; ++ ++ //SET_MODULE_OWNER(pnetdev); ++ ether_setup(pnetdev); ++ ++ //pnetdev->type = ARPHRD_IEEE80211; ++ ++ phostapdpriv = rtw_netdev_priv(pnetdev); ++ phostapdpriv->pmgnt_netdev = pnetdev; ++ phostapdpriv->padapter= padapter; ++ padapter->phostapdpriv = phostapdpriv; ++ ++ //pnetdev->init = NULL; ++ ++#if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,29)) ++ ++ DBG_8192C("register rtl871x_mgnt_netdev_ops to netdev_ops\n"); ++ ++ pnetdev->netdev_ops = &rtl871x_mgnt_netdev_ops; ++ ++#else ++ ++ pnetdev->open = mgnt_netdev_open; ++ ++ pnetdev->stop = mgnt_netdev_close; ++ ++ pnetdev->hard_start_xmit = mgnt_xmit_entry; ++ ++ //pnetdev->set_mac_address = r871x_net_set_mac_address; ++ ++ //pnetdev->get_stats = r871x_net_get_stats; ++ ++ //pnetdev->do_ioctl = r871x_mp_ioctl; ++ ++#endif ++ ++ pnetdev->watchdog_timeo = HZ; /* 1 second timeout */ ++ ++ //pnetdev->wireless_handlers = NULL; ++ ++#ifdef CONFIG_TCP_CSUM_OFFLOAD_TX ++ pnetdev->features |= NETIF_F_IP_CSUM; ++#endif ++ ++ ++ ++ if(dev_alloc_name(pnetdev,"mgnt.wlan%d") < 0) ++ { ++ DBG_8192C("hostapd_mode_init(): dev_alloc_name, fail! \n"); ++ } ++ ++ ++ //SET_NETDEV_DEV(pnetdev, pintfpriv->udev); ++ ++ ++ mac[0]=0x00; ++ mac[1]=0xe0; ++ mac[2]=0x4c; ++ mac[3]=0x87; ++ mac[4]=0x11; ++ mac[5]=0x12; ++ ++ _rtw_memcpy(pnetdev->dev_addr, mac, ETH_ALEN); ++ ++ ++ netif_carrier_off(pnetdev); ++ ++ ++ /* Tell the network stack we exist */ ++ if (register_netdev(pnetdev) != 0) ++ { ++ DBG_8192C("hostapd_mode_init(): register_netdev fail!\n"); ++ ++ if(pnetdev) ++ { ++ rtw_free_netdev(pnetdev); ++ } ++ } ++ ++ return 0; ++ ++} ++ ++void hostapd_mode_unload(_adapter *padapter) ++{ ++ struct hostapd_priv *phostapdpriv = padapter->phostapdpriv; ++ struct net_device *pnetdev = phostapdpriv->pmgnt_netdev; ++ ++ unregister_netdev(pnetdev); ++ rtw_free_netdev(pnetdev); ++ ++} ++ ++#endif ++#endif ++ +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/os_dep/linux/os_intfs.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/os_dep/linux/os_intfs.c 2013-07-26 19:36:07.000000000 +0000 +@@ -0,0 +1,1542 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#define _OS_INTFS_C_ ++ ++#include ++ ++#if defined (PLATFORM_LINUX) && defined (PLATFORM_WINDOWS) ++ ++#error "Shall be Linux or Windows, but not both!\n" ++ ++#endif ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#ifdef CONFIG_SDIO_HCI ++#include ++#endif ++ ++#ifdef CONFIG_USB_HCI ++#include ++#endif ++ ++#ifdef CONFIG_PCI_HCI ++#include ++#endif ++ ++#ifdef CONFIG_BR_EXT ++#include ++#endif //CONFIG_BR_EXT ++ ++MODULE_LICENSE("GPL"); ++MODULE_DESCRIPTION("Realtek Wireless Lan Driver"); ++MODULE_AUTHOR("Realtek Semiconductor Corp."); ++MODULE_VERSION(DRIVERVERSION); ++ ++/* module param defaults */ ++int rtw_chip_version = 0x00; ++int rtw_rfintfs = HWPI; ++int rtw_lbkmode = 0;//RTL8712_AIR_TRX; ++ ++ ++int rtw_network_mode = Ndis802_11IBSS;//Ndis802_11Infrastructure;//infra, ad-hoc, auto ++//NDIS_802_11_SSID ssid; ++int rtw_channel = 1;//ad-hoc support requirement ++int rtw_wireless_mode = WIRELESS_11BG_24N; ++int rtw_vrtl_carrier_sense = AUTO_VCS; ++int rtw_vcs_type = RTS_CTS;//* ++int rtw_rts_thresh = 2347;//* ++int rtw_frag_thresh = 2346;//* ++int rtw_preamble = PREAMBLE_LONG;//long, short, auto ++int rtw_scan_mode = 1;//active, passive ++int rtw_adhoc_tx_pwr = 1; ++int rtw_soft_ap = 0; ++//int smart_ps = 1; ++#ifdef CONFIG_POWER_SAVING ++int rtw_power_mgnt = 1; ++#else ++int rtw_power_mgnt = PS_MODE_ACTIVE; ++#endif ++ ++#ifdef CONFIG_IPS_LEVEL_2 ++int rtw_ips_mode = IPS_LEVEL_2; ++#else ++int rtw_ips_mode = IPS_NORMAL; ++#endif ++module_param(rtw_ips_mode, int, 0644); ++MODULE_PARM_DESC(rtw_ips_mode,"The default IPS mode"); ++ ++int rtw_radio_enable = 1; ++int rtw_long_retry_lmt = 7; ++int rtw_short_retry_lmt = 7; ++int rtw_busy_thresh = 40; ++//int qos_enable = 0; //* ++int rtw_ack_policy = NORMAL_ACK; ++#ifdef CONFIG_MP_INCLUDED ++int rtw_mp_mode = 1; ++#else ++int rtw_mp_mode = 0; ++#endif ++int rtw_software_encrypt = 0; ++int rtw_software_decrypt = 0; ++ ++int rtw_acm_method = 0;// 0:By SW 1:By HW. ++ ++int rtw_wmm_enable = 1;// default is set to enable the wmm. ++int rtw_uapsd_enable = 0; ++int rtw_uapsd_max_sp = NO_LIMIT; ++int rtw_uapsd_acbk_en = 0; ++int rtw_uapsd_acbe_en = 0; ++int rtw_uapsd_acvi_en = 0; ++int rtw_uapsd_acvo_en = 0; ++ ++#ifdef CONFIG_80211N_HT ++int rtw_ht_enable = 1; ++int rtw_cbw40_enable = 1; ++int rtw_ampdu_enable = 1;//for enable tx_ampdu ++int rtw_rx_stbc = 1;// 0: disable, bit(0):enable 2.4g, bit(1):enable 5g, default is set to enable 2.4GHZ for IOT issue with bufflao's AP at 5GHZ ++int rtw_ampdu_amsdu = 0;// 0: disabled, 1:enabled, 2:auto ++#endif ++ ++int rtw_lowrate_two_xmit = 1;//Use 2 path Tx to transmit MCS0~7 and legacy mode ++ ++//int rf_config = RF_1T2R; // 1T2R ++int rtw_rf_config = RF_819X_MAX_TYPE; //auto ++int rtw_low_power = 0; ++#ifdef CONFIG_WIFI_TEST ++int rtw_wifi_spec = 1;//for wifi test ++#else ++int rtw_wifi_spec = 0; ++#endif ++int rtw_channel_plan = RT_CHANNEL_DOMAIN_MAX; ++ ++#ifdef CONFIG_BT_COEXIST ++int rtw_bt_iso = 2;// 0:Low, 1:High, 2:From Efuse ++int rtw_bt_sco = 3;// 0:Idle, 1:None-SCO, 2:SCO, 3:From Counter, 4.Busy, 5.OtherBusy ++int rtw_bt_ampdu =1 ;// 0:Disable BT control A-MPDU, 1:Enable BT control A-MPDU. ++#endif ++int rtw_AcceptAddbaReq = _TRUE;// 0:Reject AP's Add BA req, 1:Accept AP's Add BA req. ++ ++int rtw_antdiv_cfg = 2; // 0:OFF , 1:ON, 2:decide by Efuse config ++ ++#ifdef CONFIG_USB_AUTOSUSPEND ++int rtw_enusbss = 1;//0:disable,1:enable ++#else ++int rtw_enusbss = 0;//0:disable,1:enable ++#endif ++ ++int rtw_hwpdn_mode=2;//0:disable,1:enable,2: by EFUSE config ++ ++#ifdef CONFIG_HW_PWRP_DETECTION ++int rtw_hwpwrp_detect = 1; ++#else ++int rtw_hwpwrp_detect = 0; //HW power ping detect 0:disable , 1:enable ++#endif ++ ++#ifdef CONFIG_USB_HCI ++int rtw_hw_wps_pbc = 1; ++#else ++int rtw_hw_wps_pbc = 0; ++#endif ++ ++#ifdef CONFIG_TX_MCAST2UNI ++int rtw_mc2u_disable = 0; ++#endif // CONFIG_TX_MCAST2UNI ++ ++char* ifname = "wlan%d"; ++ ++char* rtw_initmac = 0; // temp mac address if users want to use instead of the mac address in Efuse ++ ++module_param(ifname, charp, 0644); ++module_param(rtw_initmac, charp, 0644); ++module_param(rtw_channel_plan, int, 0644); ++module_param(rtw_chip_version, int, 0644); ++module_param(rtw_rfintfs, int, 0644); ++module_param(rtw_lbkmode, int, 0644); ++module_param(rtw_network_mode, int, 0644); ++module_param(rtw_channel, int, 0644); ++module_param(rtw_mp_mode, int, 0644); ++module_param(rtw_wmm_enable, int, 0644); ++module_param(rtw_vrtl_carrier_sense, int, 0644); ++module_param(rtw_vcs_type, int, 0644); ++module_param(rtw_busy_thresh, int, 0644); ++#ifdef CONFIG_80211N_HT ++module_param(rtw_ht_enable, int, 0644); ++module_param(rtw_cbw40_enable, int, 0644); ++module_param(rtw_ampdu_enable, int, 0644); ++module_param(rtw_rx_stbc, int, 0644); ++module_param(rtw_ampdu_amsdu, int, 0644); ++#endif ++ ++module_param(rtw_lowrate_two_xmit, int, 0644); ++ ++module_param(rtw_rf_config, int, 0644); ++module_param(rtw_power_mgnt, int, 0644); ++module_param(rtw_low_power, int, 0644); ++module_param(rtw_wifi_spec, int, 0644); ++ ++module_param(rtw_antdiv_cfg, int, 0644); ++ ++ ++module_param(rtw_enusbss, int, 0644); ++module_param(rtw_hwpdn_mode, int, 0644); ++module_param(rtw_hwpwrp_detect, int, 0644); ++ ++#ifdef CONFIG_ADAPTOR_INFO_CACHING_FILE ++char *rtw_adaptor_info_caching_file_path= "/data/misc/wifi/rtw_cache"; ++module_param(rtw_adaptor_info_caching_file_path, charp, 0644); ++MODULE_PARM_DESC(rtw_adaptor_info_caching_file_path, "The path of adapter info cache file"); ++#endif //CONFIG_ADAPTOR_INFO_CACHING_FILE ++ ++#ifdef CONFIG_LAYER2_ROAMING ++uint rtw_max_roaming_times=2; ++module_param(rtw_max_roaming_times, uint, 0644); ++MODULE_PARM_DESC(rtw_max_roaming_times,"The max roaming times to try"); ++#endif //CONFIG_LAYER2_ROAMING ++ ++#ifdef CONFIG_IOL ++bool rtw_force_iol=_FALSE; ++module_param(rtw_force_iol, bool, 0644); ++MODULE_PARM_DESC(rtw_force_iol,"Force to enable IOL"); ++#endif //CONFIG_IOL ++ ++#ifdef SUPPORT_64_STA ++uint rtw_bcmc_rate=8; ++module_param(rtw_bcmc_rate, uint, 0644); ++MODULE_PARM_DESC(rtw_bcmc_rate,"The bc/mc data rate"); ++#endif // SUPPORT_64_STA ++ ++uint rtw_intel_class_mode=0; ++module_param(rtw_intel_class_mode, uint, 0644); ++MODULE_PARM_DESC(rtw_intel_class_mode,"The intel class mode [0: off, 1: on]"); ++ ++#ifdef CONFIG_FILE_FWIMG ++char *rtw_fw_file_path= ""; ++module_param(rtw_fw_file_path, charp, 0644); ++MODULE_PARM_DESC(rtw_fw_file_path, "The path of fw image"); ++#endif //CONFIG_FILE_FWIMG ++ ++#ifdef CONFIG_TX_MCAST2UNI ++module_param(rtw_mc2u_disable, int, 0644); ++#endif // CONFIG_TX_MCAST2UNI ++ ++static uint loadparam( _adapter *padapter, _nic_hdl pnetdev); ++int netdev_open (struct net_device *pnetdev); ++static int netdev_close (struct net_device *pnetdev); ++ ++//#ifdef RTK_DMP_PLATFORM ++#ifdef CONFIG_PROC_DEBUG ++#define RTL8192C_PROC_NAME "rtl819xC" ++#define RTL8192D_PROC_NAME "rtl819xD" ++static char rtw_proc_name[IFNAMSIZ]; ++static struct proc_dir_entry *rtw_proc = NULL; ++static int rtw_proc_cnt = 0; ++ ++void rtw_proc_init_one(struct net_device *dev) ++{ ++ struct proc_dir_entry *dir_dev = NULL; ++ struct proc_dir_entry *entry=NULL; ++ _adapter *padapter = rtw_netdev_priv(dev); ++ ++ if(rtw_proc == NULL) ++ { ++ if(padapter->chip_type == RTL8188C_8192C) ++ { ++ _rtw_memcpy(rtw_proc_name, RTL8192C_PROC_NAME, sizeof(RTL8192C_PROC_NAME)); ++ } ++ else if(padapter->chip_type == RTL8192D) ++ { ++ _rtw_memcpy(rtw_proc_name, RTL8192D_PROC_NAME, sizeof(RTL8192D_PROC_NAME)); ++ } ++ ++#if(LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24)) ++ rtw_proc=create_proc_entry(rtw_proc_name, S_IFDIR, proc_net); ++#else ++ rtw_proc=create_proc_entry(rtw_proc_name, S_IFDIR, init_net.proc_net); ++#endif ++ if (rtw_proc == NULL) { ++ DBG_8192C(KERN_ERR "Unable to create rtw_proc directory\n"); ++ return; ++ } ++ ++ entry = create_proc_read_entry("ver_info", S_IFREG | S_IRUGO, rtw_proc, proc_get_drv_version, dev); ++ if (!entry) { ++ DBG_871X("Unable to create_proc_read_entry!\n"); ++ return; ++ } ++ } ++ ++ ++ ++ if(padapter->dir_dev == NULL) ++ { ++ padapter->dir_dev = create_proc_entry(dev->name, ++ S_IFDIR | S_IRUGO | S_IXUGO, ++ rtw_proc); ++ ++ dir_dev = padapter->dir_dev; ++ ++ if(dir_dev==NULL) ++ { ++ if(rtw_proc_cnt == 0) ++ { ++ if(rtw_proc){ ++#if(LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24)) ++ remove_proc_entry(rtw_proc_name, proc_net); ++#else ++ remove_proc_entry(rtw_proc_name, init_net.proc_net); ++#endif ++ rtw_proc = NULL; ++ } ++ } ++ ++ DBG_8192C("Unable to create dir_dev directory\n"); ++ return; ++ } ++ } ++ else ++ { ++ return; ++ } ++ ++ rtw_proc_cnt++; ++ ++ entry = create_proc_read_entry("write_reg", S_IFREG | S_IRUGO, ++ dir_dev, proc_get_write_reg, dev); ++ if (!entry) { ++ DBG_871X("Unable to create_proc_read_entry!\n"); ++ return; ++ } ++ entry->write_proc = proc_set_write_reg; ++ ++ entry = create_proc_read_entry("read_reg", S_IFREG | S_IRUGO, ++ dir_dev, proc_get_read_reg, dev); ++ if (!entry) { ++ DBG_871X("Unable to create_proc_read_entry!\n"); ++ return; ++ } ++ entry->write_proc = proc_set_read_reg; ++ ++ ++ entry = create_proc_read_entry("fwstate", S_IFREG | S_IRUGO, ++ dir_dev, proc_get_fwstate, dev); ++ if (!entry) { ++ DBG_871X("Unable to create_proc_read_entry!\n"); ++ return; ++ } ++ ++ ++ entry = create_proc_read_entry("sec_info", S_IFREG | S_IRUGO, ++ dir_dev, proc_get_sec_info, dev); ++ if (!entry) { ++ DBG_871X("Unable to create_proc_read_entry!\n"); ++ return; ++ } ++ ++ ++ entry = create_proc_read_entry("mlmext_state", S_IFREG | S_IRUGO, ++ dir_dev, proc_get_mlmext_state, dev); ++ if (!entry) { ++ DBG_871X("Unable to create_proc_read_entry!\n"); ++ return; ++ } ++ ++ ++ entry = create_proc_read_entry("qos_option", S_IFREG | S_IRUGO, ++ dir_dev, proc_get_qos_option, dev); ++ if (!entry) { ++ DBG_871X("Unable to create_proc_read_entry!\n"); ++ return; ++ } ++ ++ entry = create_proc_read_entry("ht_option", S_IFREG | S_IRUGO, ++ dir_dev, proc_get_ht_option, dev); ++ if (!entry) { ++ DBG_871X("Unable to create_proc_read_entry!\n"); ++ return; ++ } ++ ++ entry = create_proc_read_entry("rf_info", S_IFREG | S_IRUGO, ++ dir_dev, proc_get_rf_info, dev); ++ if (!entry) { ++ DBG_871X("Unable to create_proc_read_entry!\n"); ++ return; ++ } ++ ++ entry = create_proc_read_entry("ap_info", S_IFREG | S_IRUGO, ++ dir_dev, proc_get_ap_info, dev); ++ if (!entry) { ++ DBG_871X("Unable to create_proc_read_entry!\n"); ++ return; ++ } ++ ++ entry = create_proc_read_entry("adapter_state", S_IFREG | S_IRUGO, ++ dir_dev, proc_get_adapter_state, dev); ++ if (!entry) { ++ DBG_871X("Unable to create_proc_read_entry!\n"); ++ return; ++ } ++ ++ entry = create_proc_read_entry("trx_info", S_IFREG | S_IRUGO, ++ dir_dev, proc_get_trx_info, dev); ++ if (!entry) { ++ DBG_871X("Unable to create_proc_read_entry!\n"); ++ return; ++ } ++ ++#ifdef CONFIG_AP_MODE ++ ++ entry = create_proc_read_entry("all_sta_info", S_IFREG | S_IRUGO, ++ dir_dev, proc_get_all_sta_info, dev); ++ if (!entry) { ++ DBG_871X("Unable to create_proc_read_entry!\n"); ++ return; ++ } ++#endif ++ ++#ifdef DBG_MEMORY_LEAK ++ entry = create_proc_read_entry("_malloc_cnt", S_IFREG | S_IRUGO, ++ dir_dev, proc_get_malloc_cnt, dev); ++ if (!entry) { ++ DBG_871X("Unable to create_proc_read_entry!\n"); ++ return; ++ } ++#endif ++ ++#ifdef CONFIG_FIND_BEST_CHANNEL ++ entry = create_proc_read_entry("best_channel", S_IFREG | S_IRUGO, ++ dir_dev, proc_get_best_channel, dev); ++ if (!entry) { ++ DBG_871X("Unable to create_proc_read_entry!\n"); ++ return; ++ } ++#endif ++ ++ entry = create_proc_read_entry("rx_signal", S_IFREG | S_IRUGO, ++ dir_dev, proc_get_rx_signal, dev); ++ if (!entry) { ++ DBG_871X("Unable to create_proc_read_entry!\n"); ++ return; ++ } ++ entry->write_proc = proc_set_rx_signal; ++ ++ ++ entry = create_proc_read_entry("rssi_disp", S_IFREG | S_IRUGO, ++ dir_dev, proc_get_rssi_disp, dev); ++ if (!entry) { ++ DBG_871X("Unable to create_proc_read_entry!\n"); ++ return; ++ } ++ entry->write_proc = proc_set_rssi_disp; ++ ++} ++ ++void rtw_proc_remove_one(struct net_device *dev) ++{ ++ struct proc_dir_entry *dir_dev = NULL; ++ _adapter *padapter = rtw_netdev_priv(dev); ++ ++ ++ dir_dev = padapter->dir_dev; ++ padapter->dir_dev = NULL; ++ ++ if (dir_dev) { ++ ++ remove_proc_entry("write_reg", dir_dev); ++ remove_proc_entry("read_reg", dir_dev); ++ remove_proc_entry("fwstate", dir_dev); ++ remove_proc_entry("sec_info", dir_dev); ++ remove_proc_entry("mlmext_state", dir_dev); ++ remove_proc_entry("qos_option", dir_dev); ++ remove_proc_entry("ht_option", dir_dev); ++ remove_proc_entry("rf_info", dir_dev); ++ remove_proc_entry("ap_info", dir_dev); ++ remove_proc_entry("adapter_state", dir_dev); ++ remove_proc_entry("trx_info", dir_dev); ++ ++#ifdef CONFIG_AP_MODE ++ remove_proc_entry("all_sta_info", dir_dev); ++#endif ++ ++#ifdef DBG_MEMORY_LEAK ++ remove_proc_entry("_malloc_cnt", dir_dev); ++#endif ++ ++#ifdef CONFIG_FIND_BEST_CHANNEL ++ remove_proc_entry("best_channel", dir_dev); ++#endif ++ remove_proc_entry("rx_signal", dir_dev); ++ ++ remove_proc_entry("rssi_disp", dir_dev); ++ ++ remove_proc_entry(dev->name, rtw_proc); ++ dir_dev = NULL; ++ ++ } ++ else ++ { ++ return; ++ } ++ ++ rtw_proc_cnt--; ++ ++ if(rtw_proc_cnt == 0) ++ { ++ if(rtw_proc){ ++ remove_proc_entry("ver_info", rtw_proc); ++ ++#if(LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24)) ++ remove_proc_entry(rtw_proc_name, proc_net); ++#else ++ remove_proc_entry(rtw_proc_name, init_net.proc_net); ++#endif ++ rtw_proc = NULL; ++ } ++ } ++} ++#endif ++ ++uint loadparam( _adapter *padapter, _nic_hdl pnetdev) ++{ ++ ++ uint status = _SUCCESS; ++ struct registry_priv *registry_par = &padapter->registrypriv; ++ ++_func_enter_; ++ ++ registry_par->chip_version = (u8)rtw_chip_version; ++ registry_par->rfintfs = (u8)rtw_rfintfs; ++ registry_par->lbkmode = (u8)rtw_lbkmode; ++ //registry_par->hci = (u8)hci; ++ registry_par->network_mode = (u8)rtw_network_mode; ++ ++ _rtw_memcpy(registry_par->ssid.Ssid, "ANY", 3); ++ registry_par->ssid.SsidLength = 3; ++ ++ registry_par->channel = (u8)rtw_channel; ++ registry_par->wireless_mode = (u8)rtw_wireless_mode; ++ registry_par->vrtl_carrier_sense = (u8)rtw_vrtl_carrier_sense ; ++ registry_par->vcs_type = (u8)rtw_vcs_type; ++ registry_par->rts_thresh=(u16)rtw_rts_thresh; ++ registry_par->frag_thresh=(u16)rtw_frag_thresh; ++ registry_par->preamble = (u8)rtw_preamble; ++ registry_par->scan_mode = (u8)rtw_scan_mode; ++ registry_par->adhoc_tx_pwr = (u8)rtw_adhoc_tx_pwr; ++ registry_par->soft_ap= (u8)rtw_soft_ap; ++ //registry_par->smart_ps = (u8)rtw_smart_ps; ++ registry_par->power_mgnt = (u8)rtw_power_mgnt; ++ registry_par->ips_mode = (u8)rtw_ips_mode; ++ registry_par->radio_enable = (u8)rtw_radio_enable; ++ registry_par->long_retry_lmt = (u8)rtw_long_retry_lmt; ++ registry_par->short_retry_lmt = (u8)rtw_short_retry_lmt; ++ registry_par->busy_thresh = (u16)rtw_busy_thresh; ++ //registry_par->qos_enable = (u8)rtw_qos_enable; ++ registry_par->ack_policy = (u8)rtw_ack_policy; ++ registry_par->mp_mode = (u8)rtw_mp_mode; ++ registry_par->software_encrypt = (u8)rtw_software_encrypt; ++ registry_par->software_decrypt = (u8)rtw_software_decrypt; ++ ++ registry_par->acm_method = (u8)rtw_acm_method; ++ ++ //UAPSD ++ registry_par->wmm_enable = (u8)rtw_wmm_enable; ++ registry_par->uapsd_enable = (u8)rtw_uapsd_enable; ++ registry_par->uapsd_max_sp = (u8)rtw_uapsd_max_sp; ++ registry_par->uapsd_acbk_en = (u8)rtw_uapsd_acbk_en; ++ registry_par->uapsd_acbe_en = (u8)rtw_uapsd_acbe_en; ++ registry_par->uapsd_acvi_en = (u8)rtw_uapsd_acvi_en; ++ registry_par->uapsd_acvo_en = (u8)rtw_uapsd_acvo_en; ++ ++#ifdef CONFIG_80211N_HT ++ registry_par->ht_enable = (u8)rtw_ht_enable; ++ registry_par->cbw40_enable = (u8)rtw_cbw40_enable; ++ registry_par->ampdu_enable = (u8)rtw_ampdu_enable; ++ registry_par->rx_stbc = (u8)rtw_rx_stbc; ++ registry_par->ampdu_amsdu = (u8)rtw_ampdu_amsdu; ++#endif ++ ++ registry_par->lowrate_two_xmit = (u8)rtw_lowrate_two_xmit; ++ registry_par->rf_config = (u8)rtw_rf_config; ++ registry_par->low_power = (u8)rtw_low_power; ++ ++ ++ registry_par->wifi_spec = (u8)rtw_wifi_spec; ++ ++ registry_par->channel_plan = (u8)rtw_channel_plan; ++ ++#ifdef CONFIG_BT_COEXIST ++ registry_par->bt_iso = (u8)rtw_bt_iso; ++ registry_par->bt_sco = (u8)rtw_bt_sco; ++ registry_par->bt_ampdu = (u8)rtw_bt_ampdu; ++#endif ++ registry_par->bAcceptAddbaReq = (u8)rtw_AcceptAddbaReq; ++ ++ registry_par->antdiv_cfg = (u8)rtw_antdiv_cfg; ++ ++#ifdef CONFIG_AUTOSUSPEND ++ registry_par->usbss_enable = (u8)rtw_enusbss;//0:disable,1:enable ++#endif ++#ifdef SUPPORT_HW_RFOFF_DETECTED ++ registry_par->hwpdn_mode = (u8)rtw_hwpdn_mode;//0:disable,1:enable,2:by EFUSE config ++ registry_par->hwpwrp_detect = (u8)rtw_hwpwrp_detect;//0:disable,1:enable ++#endif ++ ++ registry_par->hw_wps_pbc = (u8)rtw_hw_wps_pbc; ++ ++#ifdef CONFIG_ADAPTOR_INFO_CACHING_FILE ++ snprintf(registry_par->adaptor_info_caching_file_path, PATH_LENGTH_MAX, "%s",rtw_adaptor_info_caching_file_path); ++ registry_par->adaptor_info_caching_file_path[PATH_LENGTH_MAX-1]=0; ++#endif ++ ++#ifdef CONFIG_LAYER2_ROAMING ++ registry_par->max_roaming_times = (u8)rtw_max_roaming_times; ++#endif ++ ++#ifdef CONFIG_IOL ++ registry_par->force_iol = rtw_force_iol; ++#endif ++ ++#ifdef SUPPORT_64_STA ++ registry_par->bcmc_rate= (u8)rtw_bcmc_rate; ++#endif ++ registry_par->intel_class_mode= (u8)rtw_intel_class_mode; ++_func_exit_; ++ ++ return status; ++ ++} ++ ++static int rtw_net_set_mac_address(struct net_device *pnetdev, void *p) ++{ ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(pnetdev); ++ struct sockaddr *addr = p; ++ ++ if(padapter->bup == _FALSE) ++ { ++ //DBG_8192C("r8711_net_set_mac_address(), MAC=%x:%x:%x:%x:%x:%x\n", addr->sa_data[0], addr->sa_data[1], addr->sa_data[2], addr->sa_data[3], ++ //addr->sa_data[4], addr->sa_data[5]); ++ _rtw_memcpy(padapter->eeprompriv.mac_addr, addr->sa_data, ETH_ALEN); ++ //_rtw_memcpy(pnetdev->dev_addr, addr->sa_data, ETH_ALEN); ++ //padapter->bset_hwaddr = _TRUE; ++ } ++ ++ return 0; ++} ++ ++static struct net_device_stats *rtw_net_get_stats(struct net_device *pnetdev) ++{ ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(pnetdev); ++ struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); ++ struct recv_priv *precvpriv = &(padapter->recvpriv); ++ ++ padapter->stats.tx_packets = pxmitpriv->tx_pkts;//pxmitpriv->tx_pkts++; ++ padapter->stats.rx_packets = precvpriv->rx_pkts;//precvpriv->rx_pkts++; ++ padapter->stats.tx_dropped = pxmitpriv->tx_drop; ++ padapter->stats.rx_dropped = precvpriv->rx_drop; ++ padapter->stats.tx_bytes = pxmitpriv->tx_bytes; ++ padapter->stats.rx_bytes = precvpriv->rx_bytes; ++ ++ return &padapter->stats; ++} ++ ++#if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,29)) ++static const struct net_device_ops rtw_netdev_ops = { ++ .ndo_open = netdev_open, ++ .ndo_stop = netdev_close, ++ .ndo_start_xmit = rtw_xmit_entry, ++ .ndo_set_mac_address = rtw_net_set_mac_address, ++ .ndo_get_stats = rtw_net_get_stats, ++ .ndo_do_ioctl = rtw_ioctl, ++}; ++#endif ++ ++int rtw_init_netdev_name(struct net_device *pnetdev, const char *ifname) ++{ ++ _adapter *padapter = rtw_netdev_priv(pnetdev); ++ ++#ifdef CONFIG_EASY_REPLACEMENT ++ struct net_device *TargetNetdev = NULL; ++ _adapter *TargetAdapter = NULL; ++ struct net *devnet = NULL; ++ ++ if(padapter->bDongle == 1) ++ { ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24)) ++ TargetNetdev = dev_get_by_name("wlan0"); ++#else ++ #if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,26)) ++ devnet = pnetdev->nd_net; ++ #else ++ devnet = dev_net(pnetdev); ++ #endif ++ TargetNetdev = dev_get_by_name(devnet, "wlan0"); ++#endif ++ if(TargetNetdev) { ++ DBG_8192C("Force onboard module driver disappear !!!\n"); ++ TargetAdapter = rtw_netdev_priv(TargetNetdev); ++ TargetAdapter->DriverState = DRIVER_DISAPPEAR; ++ ++ padapter->pid[0] = TargetAdapter->pid[0]; ++ padapter->pid[1] = TargetAdapter->pid[1]; ++ padapter->pid[2] = TargetAdapter->pid[2]; ++ ++ dev_put(TargetNetdev); ++ unregister_netdev(TargetNetdev); ++#ifdef CONFIG_PROC_DEBUG ++ if(TargetAdapter->chip_type == padapter->chip_type) ++ rtw_proc_remove_one(TargetNetdev); ++#endif ++ padapter->DriverState = DRIVER_REPLACE_DONGLE; ++ } ++ } ++#endif ++ ++ if(dev_alloc_name(pnetdev, ifname) < 0) ++ { ++ RT_TRACE(_module_os_intfs_c_,_drv_err_,("dev_alloc_name, fail! \n")); ++ } ++ ++ netif_carrier_off(pnetdev); ++ //netif_stop_queue(pnetdev); ++ ++ return 0; ++} ++ ++struct net_device *rtw_init_netdev(_adapter *old_padapter) ++{ ++ _adapter *padapter; ++ struct net_device *pnetdev; ++ ++ RT_TRACE(_module_os_intfs_c_,_drv_info_,("+init_net_dev\n")); ++ ++ if(old_padapter != NULL) ++ pnetdev = rtw_alloc_etherdev_with_old_priv(sizeof(_adapter), (void *)old_padapter); ++ else ++ pnetdev = rtw_alloc_etherdev(sizeof(_adapter)); ++ ++ if (!pnetdev) ++ return NULL; ++ ++ padapter = rtw_netdev_priv(pnetdev); ++ padapter->pnetdev = pnetdev; ++ ++#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24) ++ SET_MODULE_OWNER(pnetdev); ++#endif ++ ++ //pnetdev->init = NULL; ++ ++#if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,29)) ++ DBG_8192C("register rtw_netdev_ops to netdev_ops\n"); ++ pnetdev->netdev_ops = &rtw_netdev_ops; ++#else ++ pnetdev->open = netdev_open; ++ pnetdev->stop = netdev_close; ++ pnetdev->hard_start_xmit = rtw_xmit_entry; ++ pnetdev->set_mac_address = rtw_net_set_mac_address; ++ pnetdev->get_stats = rtw_net_get_stats; ++ pnetdev->do_ioctl = rtw_ioctl; ++#endif ++ ++ ++#ifdef CONFIG_TCP_CSUM_OFFLOAD_TX ++ pnetdev->features |= NETIF_F_IP_CSUM; ++#endif ++ //pnetdev->tx_timeout = NULL; ++ pnetdev->watchdog_timeo = HZ*3; /* 3 second timeout */ ++ ++ pnetdev->wireless_handlers = (struct iw_handler_def *)&rtw_handlers_def; ++ ++#ifdef WIRELESS_SPY ++ //priv->wireless_data.spy_data = &priv->spy_data; ++ //pnetdev->wireless_data = &priv->wireless_data; ++#endif ++ ++ //step 2. ++ loadparam(padapter, pnetdev); ++ ++ return pnetdev; ++ ++} ++ ++u32 rtw_start_drv_threads(_adapter *padapter) ++{ ++ ++ u32 _status = _SUCCESS; ++ ++ RT_TRACE(_module_os_intfs_c_,_drv_info_,("+rtw_start_drv_threads\n")); ++ ++#ifdef CONFIG_SDIO_HCI ++ padapter->xmitThread = kernel_thread(rtw_xmit_thread, padapter, CLONE_FS|CLONE_FILES); ++ if(padapter->xmitThread < 0) ++ _status = _FAIL; ++#endif ++ ++#ifdef CONFIG_RECV_THREAD_MODE ++ padapter->recvThread = kernel_thread(recv_thread, padapter, CLONE_FS|CLONE_FILES); ++ if(padapter->recvThread < 0) ++ _status = _FAIL; ++#endif ++ ++ padapter->cmdThread = kernel_thread(rtw_cmd_thread, padapter, CLONE_FS|CLONE_FILES); ++ if(padapter->cmdThread < 0) ++ _status = _FAIL; ++ else ++ _rtw_down_sema(&padapter->cmdpriv.terminate_cmdthread_sema); //wait for cmd_thread to run ++ ++ ++#ifdef CONFIG_EVENT_THREAD_MODE ++ padapter->evtThread = kernel_thread(event_thread, padapter, CLONE_FS|CLONE_FILES); ++ if(padapter->evtThread < 0) ++ _status = _FAIL; ++#endif ++ ++ return _status; ++ ++} ++ ++void rtw_stop_drv_threads (_adapter *padapter) ++{ ++ RT_TRACE(_module_os_intfs_c_,_drv_info_,("+rtw_stop_drv_threads\n")); ++ ++ //Below is to termindate rtw_cmd_thread & event_thread... ++ _rtw_up_sema(&padapter->cmdpriv.cmd_queue_sema); ++ //_rtw_up_sema(&padapter->cmdpriv.cmd_done_sema); ++ if(padapter->cmdThread){ ++ _rtw_down_sema(&padapter->cmdpriv.terminate_cmdthread_sema); ++ } ++ ++#ifdef CONFIG_EVENT_THREAD_MODE ++ _rtw_up_sema(&padapter->evtpriv.evt_notify); ++ if(padapter->evtThread){ ++ _rtw_down_sema(&padapter->evtpriv.terminate_evtthread_sema); ++ } ++#endif ++ ++#ifdef CONFIG_XMIT_THREAD_MODE ++ // Below is to termindate tx_thread... ++ _rtw_up_sema(&padapter->xmitpriv.xmit_sema); ++ _rtw_down_sema(&padapter->xmitpriv.terminate_xmitthread_sema); ++ RT_TRACE(_module_os_intfs_c_,_drv_info_,("\n drv_halt: rtw_xmit_thread can be terminated ! \n")); ++#endif ++ ++#ifdef CONFIG_RECV_THREAD_MODE ++ // Below is to termindate rx_thread... ++ _rtw_up_sema(&padapter->recvpriv.recv_sema); ++ _rtw_down_sema(&padapter->recvpriv.terminate_recvthread_sema); ++ RT_TRACE(_module_os_intfs_c_,_drv_info_,("\n drv_halt:recv_thread can be terminated! \n")); ++#endif ++ ++ ++} ++ ++u8 rtw_init_default_value(_adapter *padapter) ++{ ++ u8 ret = _SUCCESS; ++ struct registry_priv* pregistrypriv = &padapter->registrypriv; ++ struct xmit_priv *pxmitpriv = &padapter->xmitpriv; ++ struct recv_priv *precvpriv = &padapter->recvpriv; ++ struct mlme_priv *pmlmepriv= &padapter->mlmepriv; ++ struct security_priv *psecuritypriv = &padapter->securitypriv; ++ ++ //xmit_priv ++ pxmitpriv->vcs_setting = pregistrypriv->vrtl_carrier_sense; ++ pxmitpriv->vcs = pregistrypriv->vcs_type; ++ pxmitpriv->vcs_type = pregistrypriv->vcs_type; ++ //pxmitpriv->rts_thresh = pregistrypriv->rts_thresh; ++ pxmitpriv->frag_len = pregistrypriv->frag_thresh; ++ ++ ++ ++ //recv_priv ++ ++ ++ //mlme_priv ++ pmlmepriv->scan_interval = SCAN_INTERVAL;// 30*2 sec = 60sec ++ pmlmepriv->scan_mode = SCAN_ACTIVE; ++ ++ //qos_priv ++ //pmlmepriv->qospriv.qos_option = pregistrypriv->wmm_enable; ++ ++ //ht_priv ++#ifdef CONFIG_80211N_HT ++ pmlmepriv->htpriv.ampdu_enable = _FALSE;//set to disabled ++#endif ++ ++ //security_priv ++ //rtw_get_encrypt_decrypt_from_registrypriv(padapter); ++ psecuritypriv->binstallGrpkey = _FAIL; ++ psecuritypriv->sw_encrypt=pregistrypriv->software_encrypt; ++ psecuritypriv->sw_decrypt=pregistrypriv->software_decrypt; ++ ++ psecuritypriv->dot11AuthAlgrthm = dot11AuthAlgrthm_Open; //open system ++ psecuritypriv->dot11PrivacyAlgrthm = _NO_PRIVACY_; ++ ++ psecuritypriv->dot11PrivacyKeyIndex = 0; ++ ++ psecuritypriv->dot118021XGrpPrivacy = _NO_PRIVACY_; ++ psecuritypriv->dot118021XGrpKeyid = 1; ++ ++ psecuritypriv->ndisauthtype = Ndis802_11AuthModeOpen; ++ psecuritypriv->ndisencryptstatus = Ndis802_11WEPDisabled; ++ ++ ++ //pwrctrl_priv ++ ++ ++ //registry_priv ++ rtw_init_registrypriv_dev_network(padapter); ++ rtw_update_registrypriv_dev_network(padapter); ++ ++ ++ //hal_priv ++ padapter->HalFunc.init_default_value(padapter); ++ ++ //misc. ++ padapter->bReadPortCancel = _FALSE; ++ padapter->bWritePortCancel = _FALSE; ++ padapter->bRxRSSIDisplay = 0; ++ ++ return ret; ++} ++ ++u8 rtw_reset_drv_sw(_adapter *padapter) ++{ ++ u8 ret8=_SUCCESS; ++ struct mlme_priv *pmlmepriv= &padapter->mlmepriv; ++ struct pwrctrl_priv *pwrctrlpriv = &padapter->pwrctrlpriv; ++ ++ //hal_priv ++ padapter->HalFunc.init_default_value(padapter); ++ padapter->bReadPortCancel = _FALSE; ++ padapter->bWritePortCancel = _FALSE; ++ padapter->bRxRSSIDisplay = 0; ++ pmlmepriv->scan_interval = SCAN_INTERVAL;// 30*2 sec = 60sec ++ ++ pwrctrlpriv->bips_processing = _FALSE; ++ pwrctrlpriv->rf_pwrstate = rf_on; ++ pwrctrlpriv->bInSuspend = _FALSE; ++ ++ padapter->xmitpriv.tx_pkts = 0; ++ padapter->recvpriv.rx_pkts = 0; ++ ++ pmlmepriv->LinkDetectInfo.bBusyTraffic = _FALSE; ++ ++ _clr_fwstate_(pmlmepriv, _FW_UNDER_SURVEY |_FW_UNDER_LINKING); ++ ++#ifdef CONFIG_AUTOSUSPEND ++ #if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,22) && LINUX_VERSION_CODE<=KERNEL_VERSION(2,6,34)) ++ padapter->dvobjpriv.pusbdev->autosuspend_disabled = 1;//autosuspend disabled by the user ++ #endif ++#endif ++ ++#ifdef DBG_CONFIG_ERROR_DETECT ++ if(padapter->HalFunc.sreset_reset_value) ++ padapter->HalFunc.sreset_reset_value(padapter); ++#endif ++ pwrctrlpriv->pwr_state_check_cnts = 0; ++ ++ //mlmeextpriv ++ padapter->mlmeextpriv.sitesurvey_res.state= SCAN_DISABLE; ++ ++#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS ++ rtw_set_signal_stat_timer(&padapter->recvpriv); ++#endif ++ ++ return ret8; ++} ++ ++ ++u8 rtw_init_drv_sw(_adapter *padapter) ++{ ++ ++ u8 ret8=_SUCCESS; ++ ++_func_enter_; ++ ++ RT_TRACE(_module_os_intfs_c_,_drv_info_,("+rtw_init_drv_sw\n")); ++ ++ if ((rtw_init_cmd_priv(&padapter->cmdpriv)) == _FAIL) ++ { ++ RT_TRACE(_module_os_intfs_c_,_drv_err_,("\n Can't init cmd_priv\n")); ++ ret8=_FAIL; ++ goto exit; ++ } ++ ++ padapter->cmdpriv.padapter=padapter; ++ ++ if ((rtw_init_evt_priv(&padapter->evtpriv)) == _FAIL) ++ { ++ RT_TRACE(_module_os_intfs_c_,_drv_err_,("\n Can't init evt_priv\n")); ++ ret8=_FAIL; ++ goto exit; ++ } ++ ++ ++ if (rtw_init_mlme_priv(padapter) == _FAIL) ++ { ++ RT_TRACE(_module_os_intfs_c_,_drv_err_,("\n Can't init mlme_priv\n")); ++ ret8=_FAIL; ++ goto exit; ++ } ++ ++#ifdef CONFIG_IOCTL_CFG80211 ++#ifdef CONFIG_P2P ++ rtw_init_cfg80211_wifidirect_info(padapter); ++#endif //CONFIG_P2P ++#endif //CONFIG_IOCTL_CFG80211 ++ ++ if(init_mlme_ext_priv(padapter) == _FAIL) ++ { ++ RT_TRACE(_module_os_intfs_c_,_drv_err_,("\n Can't init mlme_ext_priv\n")); ++ ret8=_FAIL; ++ goto exit; ++ } ++ ++#ifdef CONFIG_TDLS ++ if(rtw_init_tdls_info(padapter) == _FAIL) ++ { ++ DBG_871X("Can't rtw_init_tdls_info\n"); ++ ret8=_FAIL; ++ goto exit; ++ } ++#endif //CONFIG_TDLS ++ ++ if(_rtw_init_xmit_priv(&padapter->xmitpriv, padapter) == _FAIL) ++ { ++ DBG_871X("Can't _rtw_init_xmit_priv\n"); ++ ret8=_FAIL; ++ goto exit; ++ } ++ ++ if(_rtw_init_recv_priv(&padapter->recvpriv, padapter) == _FAIL) ++ { ++ DBG_871X("Can't _rtw_init_recv_priv\n"); ++ ret8=_FAIL; ++ goto exit; ++ } ++ ++ // We don't need to memset padapter->XXX to zero, because adapter is allocated by rtw_zvmalloc(). ++ //_rtw_memset((unsigned char *)&padapter->securitypriv, 0, sizeof (struct security_priv)); ++ ++ //_init_timer(&(padapter->securitypriv.tkip_timer), padapter->pnetdev, rtw_use_tkipkey_handler, padapter); ++ ++ if(_rtw_init_sta_priv(&padapter->stapriv) == _FAIL) ++ { ++ DBG_871X("Can't _rtw_init_sta_priv\n"); ++ ret8=_FAIL; ++ goto exit; ++ } ++ ++ padapter->stapriv.padapter = padapter; ++ ++ rtw_init_bcmc_stainfo(padapter); ++ ++ rtw_init_pwrctrl_priv(padapter); ++ ++ //_rtw_memset((u8 *)&padapter->qospriv, 0, sizeof (struct qos_priv));//move to mlme_priv ++ ++#ifdef CONFIG_MP_INCLUDED ++ if (init_mp_priv(padapter) == _FAIL) { ++ ERR_8192C("%s: initialize MP private data Fail!\n", __func__); ++ } ++#endif ++ ++ ret8 = rtw_init_default_value(padapter); ++ ++ rtw_dm_init(padapter); ++ rtw_sw_led_init(padapter); ++ ++#ifdef DBG_CONFIG_ERROR_DETECT ++ rtw_sreset_init(padapter); ++#endif ++ ++ ++#ifdef CONFIG_BR_EXT ++ _rtw_spinlock_init(&padapter->br_ext_lock); ++#endif // CONFIG_BR_EXT ++ ++exit: ++ ++ RT_TRACE(_module_os_intfs_c_,_drv_info_,("-rtw_init_drv_sw\n")); ++ ++ _func_exit_; ++ ++ return ret8; ++ ++} ++ ++void rtw_cancel_all_timer(_adapter *padapter) ++{ ++ RT_TRACE(_module_os_intfs_c_,_drv_info_,("+rtw_cancel_all_timer\n")); ++ ++ _cancel_timer_ex(&padapter->mlmepriv.assoc_timer); ++ RT_TRACE(_module_os_intfs_c_,_drv_info_,("rtw_cancel_all_timer:cancel association timer complete! \n")); ++ ++ //_cancel_timer_ex(&padapter->securitypriv.tkip_timer); ++ //RT_TRACE(_module_os_intfs_c_,_drv_info_,("rtw_cancel_all_timer:cancel tkip_timer! \n")); ++ ++ _cancel_timer_ex(&padapter->mlmepriv.scan_to_timer); ++ RT_TRACE(_module_os_intfs_c_,_drv_info_,("rtw_cancel_all_timer:cancel scan_to_timer! \n")); ++ ++ _cancel_timer_ex(&padapter->mlmepriv.dynamic_chk_timer); ++ RT_TRACE(_module_os_intfs_c_,_drv_info_,("rtw_cancel_all_timer:cancel dynamic_chk_timer! \n")); ++ ++ // cancel sw led timer ++ rtw_sw_led_deinit(padapter); ++ RT_TRACE(_module_os_intfs_c_,_drv_info_,("rtw_cancel_all_timer:cancel DeInitSwLeds! \n")); ++ ++ _cancel_timer_ex(&padapter->pwrctrlpriv.pwr_state_check_timer); ++ ++#ifdef CONFIG_IOCTL_CFG80211 ++#ifdef CONFIG_P2P ++ _cancel_timer_ex(&padapter->cfg80211_wdinfo.remain_on_ch_timer); ++#endif //CONFIG_P2P ++#endif //CONFIG_IOCTL_CFG80211 ++ ++#ifdef CONFIG_SET_SCAN_DENY_TIMER ++ _cancel_timer_ex(&padapter->mlmepriv.set_scan_deny_timer); ++ RT_TRACE(_module_os_intfs_c_,_drv_info_,("rtw_cancel_all_timer:cancel set_scan_deny_timer! \n")); ++#endif ++ ++#ifdef CONFIG_NEW_SIGNAL_STAT_PROCESS ++ _cancel_timer_ex(&padapter->recvpriv.signal_stat_timer); ++#endif ++ ++ // cancel dm timer ++ padapter->HalFunc.dm_deinit(padapter); ++ ++} ++ ++u8 rtw_free_drv_sw(_adapter *padapter) ++{ ++ struct net_device *pnetdev = (struct net_device*)padapter->pnetdev; ++ ++ RT_TRACE(_module_os_intfs_c_,_drv_info_,("==>rtw_free_drv_sw")); ++ ++ ++ //we can call rtw_p2p_enable here, but: ++ // 1. rtw_p2p_enable may have IO operation ++ // 2. rtw_p2p_enable is bundled with wext interface ++ #ifdef CONFIG_P2P ++ { ++ struct wifidirect_info *pwdinfo = &padapter->wdinfo; ++ if(!rtw_p2p_chk_state(pwdinfo, P2P_STATE_NONE)) ++ { ++ _cancel_timer_ex( &pwdinfo->find_phase_timer ); ++ _cancel_timer_ex( &pwdinfo->restore_p2p_state_timer ); ++ _cancel_timer_ex( &pwdinfo->pre_tx_scan_timer); ++ rtw_p2p_set_state(pwdinfo, P2P_STATE_NONE); ++ } ++ } ++ #endif ++ ++ ++#ifdef CONFIG_BR_EXT ++ _rtw_spinlock_free(&padapter->br_ext_lock); ++#endif // CONFIG_BR_EXT ++ ++ ++ free_mlme_ext_priv(&padapter->mlmeextpriv); ++ ++#ifdef CONFIG_TDLS ++ //rtw_free_tdls_info(&padapter->tdlsinfo); ++#endif //CONFIG_TDLS ++ ++ rtw_free_cmd_priv(&padapter->cmdpriv); ++ ++ rtw_free_evt_priv(&padapter->evtpriv); ++ ++ rtw_free_mlme_priv(&padapter->mlmepriv); ++ ++ //free_io_queue(padapter); ++ ++ _rtw_free_xmit_priv(&padapter->xmitpriv); ++ ++ _rtw_free_sta_priv(&padapter->stapriv); //will free bcmc_stainfo here ++ ++ _rtw_free_recv_priv(&padapter->recvpriv); ++ ++ rtw_free_pwrctrl_priv(padapter); ++ ++ //rtw_mfree((void *)padapter, sizeof (padapter)); ++ ++#ifdef CONFIG_DRVEXT_MODULE ++ free_drvext(&padapter->drvextpriv); ++#endif ++ ++ padapter->HalFunc.free_hal_data(padapter); ++ ++ RT_TRACE(_module_os_intfs_c_,_drv_info_,("<==rtw_free_drv_sw\n")); ++ ++ //free the old_pnetdev ++ if(padapter->rereg_nd_name_priv.old_pnetdev) { ++ free_netdev(padapter->rereg_nd_name_priv.old_pnetdev); ++ padapter->rereg_nd_name_priv.old_pnetdev = NULL; ++ } ++ ++ if(pnetdev) ++ { ++ rtw_free_netdev(pnetdev); ++ } ++ ++ RT_TRACE(_module_os_intfs_c_,_drv_info_,("-rtw_free_drv_sw\n")); ++ ++ return _SUCCESS; ++ ++} ++ ++int netdev_open(struct net_device *pnetdev) ++{ ++ uint status; ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(pnetdev); ++ struct pwrctrl_priv *pwrctrlpriv = &padapter->pwrctrlpriv; ++ ++ RT_TRACE(_module_os_intfs_c_,_drv_info_,("+871x_drv - dev_open\n")); ++ DBG_8192C("+871x_drv - drv_open, bup=%d\n", padapter->bup); ++ ++ if(pwrctrlpriv->ps_flag == _TRUE){ ++ padapter->net_closed = _FALSE; ++ goto netdev_open_normal_process; ++ } ++ ++ if(padapter->bup == _FALSE) ++ { ++ padapter->bDriverStopped = _FALSE; ++ padapter->bSurpriseRemoved = _FALSE; ++ padapter->bCardDisableWOHSM = _FALSE; ++ ++ status = rtw_hal_init(padapter); ++ if (status ==_FAIL) ++ { ++ RT_TRACE(_module_os_intfs_c_,_drv_err_,("rtl871x_hal_init(): Can't init h/w!\n")); ++ goto netdev_open_error; ++ } ++ ++ DBG_8192C("MAC Address = "MAC_FMT"\n", MAC_ARG(pnetdev->dev_addr)); ++ ++ ++ status=rtw_start_drv_threads(padapter); ++ if(status ==_FAIL) ++ { ++ RT_TRACE(_module_os_intfs_c_,_drv_err_,("Initialize driver software resource Failed!\n")); ++ goto netdev_open_error; ++ } ++ ++ ++ if (init_hw_mlme_ext(padapter) == _FAIL) ++ { ++ RT_TRACE(_module_os_intfs_c_,_drv_err_,("can't init mlme_ext_priv\n")); ++ goto netdev_open_error; ++ } ++ ++ ++#ifdef CONFIG_DRVEXT_MODULE ++ init_drvext(padapter); ++#endif ++ ++ if(padapter->intf_start) ++ { ++ padapter->intf_start(padapter); ++ } ++ ++#ifdef CONFIG_PROC_DEBUG ++#ifndef RTK_DMP_PLATFORM ++ rtw_proc_init_one(pnetdev); ++#endif ++#endif ++ ++#ifdef CONFIG_IOCTL_CFG80211 ++ rtw_cfg80211_init_wiphy(padapter); ++#endif ++ ++ rtw_led_control(padapter, LED_CTL_NO_LINK); ++ ++ padapter->bup = _TRUE; ++ } ++ padapter->net_closed = _FALSE; ++ ++ _set_timer(&padapter->mlmepriv.dynamic_chk_timer, 2000); ++ ++ if(( pwrctrlpriv->power_mgnt != PS_MODE_ACTIVE ) ||(padapter->pwrctrlpriv.bHWPwrPindetect)) ++ { ++ padapter->pwrctrlpriv.bips_processing = _FALSE; ++ rtw_set_pwr_state_check_timer(&padapter->pwrctrlpriv); ++ } ++ ++ //netif_carrier_on(pnetdev);//call this func when rtw_joinbss_event_callback return success ++ if(!netif_queue_stopped(pnetdev)) ++ netif_start_queue(pnetdev); ++ else ++ netif_wake_queue(pnetdev); ++ ++#ifdef CONFIG_BR_EXT ++ ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 35)) ++ rcu_read_lock(); ++#endif // (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 35)) ++ ++ //if(check_fwstate(pmlmepriv, WIFI_STATION_STATE|WIFI_ADHOC_STATE) == _TRUE) ++ { ++ //struct net_bridge *br = pnetdev->br_port->br;//->dev->dev_addr; ++#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35)) ++ if (pnetdev->br_port) ++#else // (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35)) ++ if (rcu_dereference(padapter->pnetdev->rx_handler_data)) ++#endif // (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35)) ++ { ++ struct net_device *br_netdev; ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24)) ++ br_netdev = dev_get_by_name(CONFIG_BR_EXT_BRNAME); ++#else // (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24)) ++ struct net *devnet = NULL; ++ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,26)) ++ devnet = pnetdev->nd_net; ++#else // (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,26)) ++ devnet = dev_net(pnetdev); ++#endif // (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,26)) ++ ++ br_netdev = dev_get_by_name(devnet, CONFIG_BR_EXT_BRNAME); ++#endif // (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24)) ++ ++ if (br_netdev) { ++ memcpy(padapter->br_mac, br_netdev->dev_addr, ETH_ALEN); ++ dev_put(br_netdev); ++ } else ++ printk("%s()-%d: dev_get_by_name(%s) failed!", __FUNCTION__, __LINE__, CONFIG_BR_EXT_BRNAME); ++ } ++ ++ padapter->ethBrExtInfo.addPPPoETag = 1; ++ } ++ ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 35)) ++ rcu_read_unlock(); ++#endif // (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 35)) ++ ++#endif // CONFIG_BR_EXT ++ ++netdev_open_normal_process: ++ ++ RT_TRACE(_module_os_intfs_c_,_drv_info_,("-871x_drv - dev_open\n")); ++ DBG_8192C("-871x_drv - drv_open, bup=%d\n", padapter->bup); ++ ++ return 0; ++ ++netdev_open_error: ++ ++ padapter->bup = _FALSE; ++ ++ netif_carrier_off(pnetdev); ++ netif_stop_queue(pnetdev); ++ ++ RT_TRACE(_module_os_intfs_c_,_drv_err_,("-871x_drv - dev_open, fail!\n")); ++ DBG_8192C("-871x_drv - drv_open fail, bup=%d\n", padapter->bup); ++ ++ return (-1); ++ ++} ++ ++ ++ ++#ifdef CONFIG_IPS ++int ips_netdrv_open(_adapter *padapter) ++{ ++ int status = _SUCCESS; ++ padapter->net_closed = _FALSE; ++ DBG_8192C("===> %s.........\n",__FUNCTION__); ++ ++ ++ padapter->bDriverStopped = _FALSE; ++ padapter->bSurpriseRemoved = _FALSE; ++ padapter->bCardDisableWOHSM = _FALSE; ++ padapter->bup = _TRUE; ++ ++ status = rtw_hal_init(padapter); ++ if (status ==_FAIL) ++ { ++ RT_TRACE(_module_os_intfs_c_,_drv_err_,("ips_netdrv_open(): Can't init h/w!\n")); ++ goto netdev_open_error; ++ } ++ ++ if(padapter->intf_start) ++ { ++ padapter->intf_start(padapter); ++ } ++ ++ rtw_set_pwr_state_check_timer(&padapter->pwrctrlpriv); ++ _set_timer(&padapter->mlmepriv.dynamic_chk_timer,5000); ++ ++ return _SUCCESS; ++ ++netdev_open_error: ++ padapter->bup = _FALSE; ++ DBG_8192C("-ips_netdrv_open - drv_open failure, bup=%d\n", padapter->bup); ++ ++ return _FAIL; ++} ++ ++ ++int rtw_ips_pwr_up(_adapter *padapter) ++{ ++ int result; ++ u32 start_time = rtw_get_current_time(); ++ DBG_8192C("===> rtw_ips_pwr_up..............\n"); ++ rtw_reset_drv_sw(padapter); ++ result = ips_netdrv_open(padapter); ++ ++ rtw_led_control(padapter, LED_CTL_NO_LINK); ++ ++ DBG_8192C("<=== rtw_ips_pwr_up.............. in %dms\n", rtw_get_passing_time_ms(start_time)); ++ return result; ++ ++} ++ ++void rtw_ips_pwr_down(_adapter *padapter) ++{ ++ u32 start_time = rtw_get_current_time(); ++ DBG_8192C("===> rtw_ips_pwr_down...................\n"); ++ ++ padapter->bCardDisableWOHSM = _TRUE; ++ padapter->net_closed = _TRUE; ++ ++ rtw_led_control(padapter, LED_CTL_POWER_OFF); ++ ++ rtw_ips_dev_unload(padapter); ++ padapter->bCardDisableWOHSM = _FALSE; ++ DBG_8192C("<=== rtw_ips_pwr_down..................... in %dms\n", rtw_get_passing_time_ms(start_time)); ++} ++#endif ++void rtw_ips_dev_unload(_adapter *padapter) ++{ ++ struct net_device *pnetdev= (struct net_device*)padapter->pnetdev; ++ struct xmit_priv *pxmitpriv = &(padapter->xmitpriv); ++ DBG_8192C("====> %s...\n",__FUNCTION__); ++ ++ padapter->HalFunc.SetHwRegHandler(padapter, HW_VAR_FIFO_CLEARN_UP, 0); ++ ++ if(padapter->intf_stop) ++ { ++ padapter->intf_stop(padapter); ++ } ++ ++ //s5. ++ if(padapter->bSurpriseRemoved == _FALSE) ++ { ++ rtw_hal_deinit(padapter); ++ } ++ ++} ++ ++int pm_netdev_open(struct net_device *pnetdev,u8 bnormal) ++{ ++ int status; ++ if(bnormal) ++ status = netdev_open(pnetdev); ++#ifdef CONFIG_IPS ++ else ++ status = (_SUCCESS == ips_netdrv_open((_adapter *)rtw_netdev_priv(pnetdev)))?(0):(-1); ++#endif ++ ++ return status; ++} ++//extern int rfpwrstate_check(_adapter *padapter); ++static int netdev_close(struct net_device *pnetdev) ++{ ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(pnetdev); ++ ++ RT_TRACE(_module_os_intfs_c_,_drv_info_,("+871x_drv - drv_close\n")); ++ ++ if(padapter->pwrctrlpriv.bInternalAutoSuspend == _TRUE) ++ { ++ //rfpwrstate_check(padapter); ++ if(padapter->pwrctrlpriv.rf_pwrstate == rf_off) ++ padapter->pwrctrlpriv.ps_flag = _TRUE; ++ } ++ padapter->net_closed = _TRUE; ++ ++/* if(!padapter->hw_init_completed) ++ { ++ DBG_8192C("(1)871x_drv - drv_close, bup=%d, hw_init_completed=%d\n", padapter->bup, padapter->hw_init_completed); ++ ++ padapter->bDriverStopped = _TRUE; ++ ++ rtw_dev_unload(padapter); ++ } ++ else*/ ++ if(padapter->pwrctrlpriv.rf_pwrstate == rf_on){ ++ DBG_8192C("(2)871x_drv - drv_close, bup=%d, hw_init_completed=%d\n", padapter->bup, padapter->hw_init_completed); ++ ++ //s1. ++ if(pnetdev) ++ { ++ if (!netif_queue_stopped(pnetdev)) ++ netif_stop_queue(pnetdev); ++ } ++ ++#ifndef CONFIG_ANDROID ++ //s2. ++ //s2-1. issue rtw_disassoc_cmd to fw ++ rtw_disassoc_cmd(padapter); ++ //s2-2. indicate disconnect to os ++ rtw_indicate_disconnect(padapter); ++ //s2-3. ++ rtw_free_assoc_resources(padapter, 1); ++ //s2-4. ++ rtw_free_network_queue(padapter,_TRUE); ++#endif ++ // Close LED ++ rtw_led_control(padapter, LED_CTL_POWER_OFF); ++ } ++ ++#ifdef CONFIG_BR_EXT ++ //if (OPMODE & (WIFI_STATION_STATE | WIFI_ADHOC_STATE)) ++ { ++ //void nat25_db_cleanup(_adapter *priv); ++ nat25_db_cleanup(padapter); ++ } ++#endif // CONFIG_BR_EXT ++ ++#ifdef CONFIG_P2P ++ #ifdef CONFIG_IOCTL_CFG80211 ++ if(wdev_to_priv(padapter->rtw_wdev)->p2p_enabled == _TRUE) ++ wdev_to_priv(padapter->rtw_wdev)->p2p_enabled = _FALSE; ++ #endif ++ rtw_p2p_enable(padapter, P2P_ROLE_DISABLE); ++#endif //CONFIG_P2P ++ ++#ifdef CONFIG_IOCTL_CFG80211 ++ rtw_cfg80211_indicate_scan_done(wdev_to_priv(padapter->rtw_wdev), _TRUE); ++ padapter->rtw_wdev->iftype = NL80211_IFTYPE_MONITOR; //set this at the end ++#endif ++ ++ RT_TRACE(_module_os_intfs_c_,_drv_info_,("-871x_drv - drv_close\n")); ++ DBG_8192C("-871x_drv - drv_close, bup=%d\n", padapter->bup); ++ ++ return 0; ++ ++} ++ +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/os_dep/linux/pci_intf.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/os_dep/linux/pci_intf.c 2013-07-26 19:36:07.000000000 +0000 +@@ -0,0 +1,1889 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#define _HCI_INTF_C_ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#ifndef CONFIG_PCI_HCI ++ ++#error "CONFIG_PCI_HCI shall be on!\n" ++ ++#endif ++ ++#include ++#include ++#include ++ ++#if defined (PLATFORM_LINUX) && defined (PLATFORM_WINDOWS) ++ ++#error "Shall be Linux or Windows, but not both!\n" ++ ++#endif ++ ++#ifdef CONFIG_80211N_HT ++extern int rtw_ht_enable; ++extern int rtw_cbw40_enable; ++extern int rtw_ampdu_enable;//for enable tx_ampdu ++#endif ++ ++#ifdef CONFIG_PM ++extern int pm_netdev_open(struct net_device *pnetdev); ++static int rtw_suspend(struct pci_dev *pdev, pm_message_t state); ++static int rtw_resume(struct pci_dev *pdev); ++#endif ++ ++ ++static int rtw_drv_init(struct pci_dev *pdev, const struct pci_device_id *pdid); ++static void rtw_dev_remove(struct pci_dev *pdev); ++ ++static struct specific_device_id specific_device_id_tbl[] = { ++ {.idVendor=0x0b05, .idProduct=0x1791, .flags=SPEC_DEV_ID_DISABLE_HT}, ++ {.idVendor=0x13D3, .idProduct=0x3311, .flags=SPEC_DEV_ID_DISABLE_HT}, ++ {} ++}; ++ ++struct pci_device_id rtw_pci_id_tbl[] = { ++#ifdef CONFIG_RTL8192C ++ {PCI_DEVICE(PCI_VENDER_ID_REALTEK, 0x8191)}, ++ {PCI_DEVICE(PCI_VENDER_ID_REALTEK, 0x8178)}, ++ {PCI_DEVICE(PCI_VENDER_ID_REALTEK, 0x8177)}, ++ {PCI_DEVICE(PCI_VENDER_ID_REALTEK, 0x8176)}, ++#endif ++#ifdef CONFIG_RTL8192D ++ {PCI_DEVICE(PCI_VENDER_ID_REALTEK, 0x8193)}, ++ {PCI_DEVICE(PCI_VENDER_ID_REALTEK, 0x002B)}, ++#endif ++ {}, ++}; ++ ++typedef struct _driver_priv{ ++ ++ struct pci_driver rtw_pci_drv; ++ int drv_registered; ++ ++}drv_priv, *pdrv_priv; ++ ++ ++static drv_priv drvpriv = { ++ .rtw_pci_drv.name = (char*)DRV_NAME, ++ .rtw_pci_drv.probe = rtw_drv_init, ++ .rtw_pci_drv.remove = rtw_dev_remove, ++ .rtw_pci_drv.id_table = rtw_pci_id_tbl, ++#ifdef CONFIG_PM ++ .rtw_pci_drv.suspend = rtw_suspend, ++ .rtw_pci_drv.resume = rtw_resume, ++#else ++ .rtw_pci_drv.suspend = NULL, ++ .rtw_pci_drv.resume = NULL, ++#endif ++}; ++ ++ ++MODULE_DEVICE_TABLE(pci, rtw_pci_id_tbl); ++ ++ ++static u16 pcibridge_vendors[PCI_BRIDGE_VENDOR_MAX] = { ++ INTEL_VENDOR_ID, ++ ATI_VENDOR_ID, ++ AMD_VENDOR_ID, ++ SIS_VENDOR_ID ++}; ++ ++static u8 rtw_pci_platform_switch_device_pci_aspm(_adapter *padapter, u8 value) ++{ ++ struct dvobj_priv *pdvobjpriv = &padapter->dvobjpriv; ++ u8 bresult = _SUCCESS; ++ int error; ++ ++ value |= 0x40; ++ ++ error = pci_write_config_byte(pdvobjpriv->ppcidev, 0x80, value); ++ ++ if(error != 0) ++ { ++ bresult = _FALSE; ++ DBG_8192C("rtw_pci_platform_switch_device_pci_aspm error (%d)\n",error); ++ } ++ ++ return bresult; ++} ++ ++// ++// When we set 0x01 to enable clk request. Set 0x0 to disable clk req. ++// ++static u8 rtw_pci_switch_clk_req(_adapter *padapter, u8 value) ++{ ++ struct dvobj_priv *pdvobjpriv = &padapter->dvobjpriv; ++ u8 buffer, bresult = _SUCCESS; ++ int error; ++ ++ buffer = value; ++ ++ if(!padapter->hw_init_completed) ++ return bresult; ++ ++ error = pci_write_config_byte(pdvobjpriv->ppcidev, 0x81, value); ++ ++ if(error != 0) ++ { ++ bresult = _FALSE; ++ DBG_8192C("rtw_pci_switch_clk_req error (%d)\n",error); ++ } ++ ++ return bresult; ++} ++ ++#if 0 ++//Description: ++//Disable RTL8192SE ASPM & Disable Pci Bridge ASPM ++void rtw_pci_disable_aspm(_adapter *padapter) ++{ ++ struct dvobj_priv *pdvobjpriv = &padapter->dvobjpriv; ++ struct pwrctrl_priv *pwrpriv = &padapter->pwrctrlpriv; ++ struct pci_priv *pcipriv = &(pdvobjpriv->pcipriv); ++ u32 pcicfg_addrport = 0; ++ u8 num4bytes; ++ u8 linkctrl_reg; ++ u16 pcibridge_linkctrlreg, aspmlevel = 0; ++ ++ // When there exists anyone's busnum, devnum, and funcnum that are set to 0xff, ++ // we do not execute any action and return. ++ // if it is not intel bus then don't enable ASPM. ++ if ((pcipriv->busnumber == 0xff ++ && pcipriv->devnumber == 0xff ++ && pcipriv->funcnumber == 0xff) ++ || (pcipriv->pcibridge_busnum == 0xff ++ && pcipriv->pcibridge_devnum == 0xff ++ && pcipriv->pcibridge_funcnum == 0xff)) ++ { ++ DBG_8192C("PlatformEnableASPM(): Fail to enable ASPM. Cannot find the Bus of PCI(Bridge).\n"); ++ return; ++ } ++ ++ if (pcipriv->pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) { ++ DBG_8192C("%s(): Disable ASPM. Recognize the Bus of PCI(Bridge) as UNKNOWN.\n", __func__); ++ } ++ ++ if (pwrpriv->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) { ++ RT_CLEAR_PS_LEVEL(pwrpriv, RT_RF_OFF_LEVL_CLK_REQ); ++ rtw_pci_switch_clk_req(padapter, 0x0); ++ } ++ ++ { ++ // Suggested by SD1 for promising device will in L0 state after an I/O. ++ u8 tmp_u1b; ++ ++ pci_read_config_byte(pdvobjpriv->ppcidev, 0x80, &tmp_u1b); ++ } ++ ++ // Retrieve original configuration settings. ++ linkctrl_reg = pcipriv->linkctrl_reg; ++ pcibridge_linkctrlreg = pcipriv->pcibridge_linkctrlreg; ++ ++ // Set corresponding value. ++ aspmlevel |= BIT(0) | BIT(1); ++ linkctrl_reg &= ~aspmlevel; ++ pcibridge_linkctrlreg &= ~(BIT(0) | BIT(1)); ++ ++ rtw_pci_platform_switch_device_pci_aspm(padapter, linkctrl_reg); ++ rtw_udelay_os(50); ++ ++ //When there exists anyone's busnum, devnum, and funcnum that are set to 0xff, ++ // we do not execute any action and return. ++ if ((pcipriv->busnumber == 0xff && ++ pcipriv->devnumber == 0xff && ++ pcipriv->funcnumber == 0xff) || ++ (pcipriv->pcibridge_busnum == 0xff && ++ pcipriv->pcibridge_devnum == 0xff ++ && pcipriv->pcibridge_funcnum == 0xff)) ++ { ++ //Do Nothing!! ++ } ++ else ++ { ++ //4 //Disable Pci Bridge ASPM ++ pcicfg_addrport = (pcipriv->pcibridge_busnum << 16) | ++ (pcipriv->pcibridge_devnum << 11) | ++ (pcipriv->pcibridge_funcnum << 8) | (1 << 31); ++ num4bytes = (pcipriv->pcibridge_pciehdr_offset + 0x10) / 4; ++ ++ // set up address port at 0xCF8 offset field= 0 (dev|vend) ++ NdisRawWritePortUlong(PCI_CONF_ADDRESS, pcicfg_addrport + (num4bytes << 2)); ++ ++ // now grab data port with device|vendor 4 byte dword ++ NdisRawWritePortUchar(PCI_CONF_DATA, pcibridge_linkctrlreg); ++ ++ DBG_8192C("rtw_pci_disable_aspm():PciBridge busnumber[%x], DevNumbe[%x], funcnumber[%x], Write reg[%x] = %x\n", ++ pcipriv->pcibridge_busnum, pcipriv->pcibridge_devnum, ++ pcipriv->pcibridge_funcnum, ++ (pcipriv->pcibridge_pciehdr_offset+0x10), pcibridge_linkctrlreg); ++ ++ rtw_udelay_os(50); ++ } ++} ++ ++//[ASPM] ++//Description: ++// Enable RTL8192SE ASPM & Enable Pci Bridge ASPM for power saving ++// We should follow the sequence to enable RTL8192SE first then enable Pci Bridge ASPM ++// or the system will show bluescreen. ++void rtw_pci_enable_aspm(_adapter *padapter) ++{ ++ struct dvobj_priv *pdvobjpriv = &padapter->dvobjpriv; ++ struct pwrctrl_priv *pwrpriv = &padapter->pwrctrlpriv; ++ struct pci_priv *pcipriv = &(pdvobjpriv->pcipriv); ++ u16 aspmlevel = 0; ++ u32 pcicfg_addrport = 0; ++ u8 num4bytes; ++ u8 u_pcibridge_aspmsetting = 0; ++ u8 u_device_aspmsetting = 0; ++ ++ // When there exists anyone's busnum, devnum, and funcnum that are set to 0xff, ++ // we do not execute any action and return. ++ // if it is not intel bus then don't enable ASPM. ++ ++ if ((pcipriv->busnumber == 0xff ++ && pcipriv->devnumber == 0xff ++ && pcipriv->funcnumber == 0xff) ++ || (pcipriv->pcibridge_busnum == 0xff ++ && pcipriv->pcibridge_devnum == 0xff ++ && pcipriv->pcibridge_funcnum == 0xff)) ++ { ++ DBG_8192C("PlatformEnableASPM(): Fail to enable ASPM. Cannot find the Bus of PCI(Bridge).\n"); ++ return; ++ } ++ ++ //4 Enable Pci Bridge ASPM ++ pcicfg_addrport = (pcipriv->pcibridge_busnum << 16) ++ | (pcipriv->pcibridge_devnum << 11) ++ | (pcipriv->pcibridge_funcnum << 8) | (1 << 31); ++ num4bytes = (pcipriv->pcibridge_pciehdr_offset + 0x10) / 4; ++ // set up address port at 0xCF8 offset field= 0 (dev|vend) ++ NdisRawWritePortUlong(PCI_CONF_ADDRESS, pcicfg_addrport + (num4bytes << 2)); ++ // now grab data port with device|vendor 4 byte dword ++ ++ u_pcibridge_aspmsetting = pcipriv->pcibridge_linkctrlreg | pdvobjpriv->const_hostpci_aspm_setting; ++ ++ if (pcipriv->pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL || ++ pcipriv->pcibridge_vendor == PCI_BRIDGE_VENDOR_SIS) ++ u_pcibridge_aspmsetting &= ~BIT(0); ++ ++ NdisRawWritePortUchar(PCI_CONF_DATA, u_pcibridge_aspmsetting); ++ ++ DBG_8192C("PlatformEnableASPM():PciBridge busnumber[%x], DevNumbe[%x], funcnumber[%x], Write reg[%x] = %x\n", ++ pcipriv->pcibridge_busnum, ++ pcipriv->pcibridge_devnum, ++ pcipriv->pcibridge_funcnum, ++ (pcipriv->pcibridge_pciehdr_offset+0x10), ++ u_pcibridge_aspmsetting); ++ ++ rtw_udelay_os(50); ++ ++ // Get ASPM level (with/without Clock Req) ++ aspmlevel |= pdvobjpriv->const_devicepci_aspm_setting; ++ u_device_aspmsetting = pcipriv->linkctrl_reg; ++ u_device_aspmsetting |= aspmlevel; ++ ++ rtw_pci_platform_switch_device_pci_aspm(padapter, u_device_aspmsetting); //(priv->linkctrl_reg | ASPMLevel)); ++ ++ if (pwrpriv->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) { ++ rtw_pci_switch_clk_req(padapter, (pwrpriv->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) ? 1 : 0); ++ RT_SET_PS_LEVEL(pwrpriv, RT_RF_OFF_LEVL_CLK_REQ); ++ } ++ ++ rtw_udelay_os(50); ++} ++ ++// ++//Description: ++//To get link control field by searching from PCIe capability lists. ++// ++static u8 ++rtw_get_link_control_field(_adapter *padapter, u8 busnum, u8 devnum, ++ u8 funcnum) ++{ ++ struct dvobj_priv *pdvobjpriv = &padapter->dvobjpriv; ++ struct pci_priv *pcipriv = &(pdvobjpriv->pcipriv); ++ struct rt_pci_capabilities_header capability_hdr; ++ u8 capability_offset, num4bytes; ++ u32 pcicfg_addrport = 0; ++ u8 linkctrl_reg; ++ u8 status = _FALSE; ++ ++ //If busnum, devnum, funcnum are set to 0xff. ++ if (busnum == 0xff && devnum == 0xff && funcnum == 0xff) { ++ DBG_8192C("GetLinkControlField(): Fail to find PCIe Capability\n"); ++ return _FALSE; ++ } ++ ++ pcicfg_addrport = (busnum << 16) | (devnum << 11) | (funcnum << 8) | (1 << 31); ++ ++ //2PCIeCap ++ ++ // The device supports capability lists. Find the capabilities. ++ num4bytes = 0x34 / 4; ++ //get capability_offset ++ // set up address port at 0xCF8 offset field= 0 (dev|vend) ++ NdisRawWritePortUlong(PCI_CONF_ADDRESS, pcicfg_addrport + (num4bytes << 2)); ++ // now grab data port with device|vendor 4 byte dword ++ NdisRawReadPortUchar(PCI_CONF_DATA, &capability_offset); ++ ++ // Loop through the capabilities in search of the power management capability. ++ // The list is NULL-terminated, so the last offset will always be zero. ++ ++ while (capability_offset != 0) { ++ // First find the number of 4 Byte. ++ num4bytes = capability_offset / 4; ++ ++ // Read the header of the capability at this offset. If the retrieved capability is not ++ // the power management capability that we are looking for, follow the link to the ++ // next capability and continue looping. ++ ++ //4 get capability_hdr ++ // set up address port at 0xCF8 offset field= 0 (dev|vend) ++ NdisRawWritePortUlong(PCI_CONF_ADDRESS, pcicfg_addrport + (num4bytes << 2)); ++ // now grab data port with device|vendor 4 byte dword ++ NdisRawReadPortUshort(PCI_CONF_DATA, (u16 *) & capability_hdr); ++ ++ // Found the PCI express capability ++ if (capability_hdr.capability_id == PCI_CAPABILITY_ID_PCI_EXPRESS) ++ { ++ break; ++ } ++ else ++ { ++ // This is some other capability. Keep looking for the PCI express capability. ++ capability_offset = capability_hdr.next; ++ } ++ } ++ ++ if (capability_hdr.capability_id == PCI_CAPABILITY_ID_PCI_EXPRESS) // ++ { ++ num4bytes = (capability_offset + 0x10) / 4; ++ ++ //4 Read Link Control Register ++ // set up address port at 0xCF8 offset field= 0 (dev|vend) ++ NdisRawWritePortUlong(PCI_CONF_ADDRESS, pcicfg_addrport + (num4bytes << 2)); ++ // now grab data port with device|vendor 4 byte dword ++ NdisRawReadPortUchar(PCI_CONF_DATA, &linkctrl_reg); ++ ++ pcipriv->pcibridge_pciehdr_offset = capability_offset; ++ pcipriv->pcibridge_linkctrlreg = linkctrl_reg; ++ ++ status = _TRUE; ++ } ++ else ++ { ++ // We didn't find a PCIe capability. ++ DBG_8192C("GetLinkControlField(): Cannot Find PCIe Capability\n"); ++ } ++ ++ return status; ++} ++ ++// ++//Description: ++//To get PCI bus infomation and return busnum, devnum, and funcnum about ++//the bus(bridge) which the device binds. ++// ++static u8 ++rtw_get_pci_bus_info(_adapter *padapter, ++ u16 vendorid, ++ u16 deviceid, ++ u8 irql, u8 basecode, u8 subclass, u8 filed19val, ++ u8 * busnum, u8 * devnum, u8 * funcnum) ++{ ++ struct dvobj_priv *pdvobjpriv = &padapter->dvobjpriv; ++ struct pci_dev *pdev = pdvobjpriv->ppcidev; ++ u8 busnum_idx, devicenum_idx, functionnum_idx; ++ u32 pcicfg_addrport = 0; ++ u32 dev_venid = 0, classcode, field19, headertype; ++ u16 venId, devId; ++ u8 basec, subc, irqline; ++ u16 regoffset; ++ u8 b_singlefunc = _FALSE; ++ u8 b_bridgechk = _FALSE; ++ ++ *busnum = 0xFF; ++ *devnum = 0xFF; ++ *funcnum = 0xFF; ++ ++ //DBG_8192C("==============>vendorid:%x,deviceid:%x,irql:%x\n", vendorid,deviceid,irql); ++ if ((basecode == PCI_CLASS_BRIDGE_DEV) && ++ (subclass == PCI_SUBCLASS_BR_PCI_TO_PCI) ++ && (filed19val == U1DONTCARE)) ++ b_bridgechk = _TRUE; ++ ++ // perform a complete pci bus scan operation ++ for (busnum_idx = 0; busnum_idx < PCI_MAX_BRIDGE_NUMBER; busnum_idx++) //255 ++ { ++ for (devicenum_idx = 0; devicenum_idx < PCI_MAX_DEVICES; devicenum_idx++) //32 ++ { ++ b_singlefunc = _FALSE; ++ for (functionnum_idx = 0; functionnum_idx < PCI_MAX_FUNCTION; functionnum_idx++) //8 ++ { ++ // ++ // We have to skip redundant Bus scan to prevent unexpected system hang ++ // if single function is present in this device. ++ // 2009.02.26. ++ // ++ if (functionnum_idx == 0) { ++ //4 get header type (DWORD #3) ++ pcicfg_addrport = (busnum_idx << 16) | (devicenum_idx << 11) | (functionnum_idx << 8) | (1 << 31); ++ NdisRawWritePortUlong(PCI_CONF_ADDRESS, pcicfg_addrport + (3 << 2)); ++ NdisRawReadPortUlong(PCI_CONF_DATA, &headertype); ++ headertype = ((headertype >> 16) & 0x0080) >> 7; // address 0x0e[7]. ++ if (headertype == 0) //Single function ++ b_singlefunc = _TRUE; ++ } ++ else ++ {//By pass the following scan process. ++ if (b_singlefunc == _TRUE) ++ break; ++ } ++ ++ // Set access enable control. ++ pcicfg_addrport = (busnum_idx << 16) | (devicenum_idx << 11) | (functionnum_idx << 8) | (1 << 31); ++ ++ //4 // Get vendorid/ deviceid ++ // set up address port at 0xCF8 offset field= 0 (dev|vend) ++ NdisRawWritePortUlong(PCI_CONF_ADDRESS, pcicfg_addrport); ++ // now grab data port with device|vendor 4 byte dword ++ NdisRawReadPortUlong(PCI_CONF_DATA, &dev_venid); ++ ++ // if data port is full of 1s, no device is present ++ // some broken boards return 0 if a slot is empty: ++ if (dev_venid == 0xFFFFFFFF || dev_venid == 0) ++ continue; //PCI_INVALID_VENDORID ++ ++ // 4 // Get irql ++ regoffset = 0x3C; ++ pcicfg_addrport = (busnum_idx << 16) | (devicenum_idx << 11) | (functionnum_idx << 8) | (1 << 31) | (regoffset & 0xFFFFFFFC); ++ NdisRawWritePortUlong(PCI_CONF_ADDRESS, pcicfg_addrport); ++ NdisRawReadPortUchar((PCI_CONF_DATA +(regoffset & 0x3)), &irqline); ++ ++ venId = (u16) (dev_venid >> 0) & 0xFFFF; ++ devId = (u16) (dev_venid >> 16) & 0xFFFF; ++ ++ // Check Vendor ID ++ if (!b_bridgechk && (venId != vendorid) && (vendorid != U2DONTCARE)) ++ continue; ++ ++ // Check Device ID ++ if (!b_bridgechk && (devId != deviceid) && (deviceid != U2DONTCARE)) ++ continue; ++ ++ // Check irql ++ if (!b_bridgechk && (irqline != irql) && (irql != U1DONTCARE)) ++ continue; ++ ++ //4 get Class Code ++ pcicfg_addrport = (busnum_idx << 16) | (devicenum_idx << 11) | (functionnum_idx << 8) | (1 << 31); ++ NdisRawWritePortUlong(PCI_CONF_ADDRESS, pcicfg_addrport + (2 << 2)); ++ NdisRawReadPortUlong(PCI_CONF_DATA, &classcode); ++ classcode = classcode >> 8; ++ ++ basec = (u8) (classcode >> 16) & 0xFF; ++ subc = (u8) (classcode >> 8) & 0xFF; ++ if (b_bridgechk && (venId != vendorid) && (basec == basecode) && (subc == subclass)) ++ return _TRUE; ++ ++ // Check Vendor ID ++ if (b_bridgechk && (venId != vendorid) && (vendorid != U2DONTCARE)) ++ continue; ++ ++ // Check Device ID ++ if (b_bridgechk && (devId != deviceid) && (deviceid != U2DONTCARE)) ++ continue; ++ ++ // Check irql ++ if (b_bridgechk && (irqline != irql) && (irql != U1DONTCARE)) ++ continue; ++ ++ //4 get field 0x19 value (DWORD #6) ++ NdisRawWritePortUlong(PCI_CONF_ADDRESS, pcicfg_addrport + (6 << 2)); ++ NdisRawReadPortUlong(PCI_CONF_DATA, &field19); ++ field19 = (field19 >> 8) & 0xFF; ++ ++ //4 Matching Class Code and filed19. ++ if ((basec == basecode) && (subc == subclass) && ((field19 == filed19val) || (filed19val == U1DONTCARE))) { ++ *busnum = busnum_idx; ++ *devnum = devicenum_idx; ++ *funcnum = functionnum_idx; ++ ++ DBG_8192C("GetPciBusInfo(): Find Device(%X:%X) bus=%d dev=%d, func=%d\n", ++ vendorid, deviceid, busnum_idx, devicenum_idx, functionnum_idx); ++ return _TRUE; ++ } ++ } ++ } ++ } ++ ++ DBG_8192C("GetPciBusInfo(): Cannot Find Device(%X:%X:%X)\n", vendorid, deviceid, dev_venid); ++ ++ return _FALSE; ++} ++ ++static u8 ++rtw_get_pci_brideg_info(_adapter *padapter, ++ u8 basecode, ++ u8 subclass, ++ u8 filed19val, u8 * busnum, u8 * devnum, ++ u8 * funcnum, u16 * vendorid, u16 * deviceid) ++{ ++ u8 busnum_idx, devicenum_idx, functionnum_idx; ++ u32 pcicfg_addrport = 0; ++ u32 dev_venid, classcode, field19, headertype; ++ u16 venId, devId; ++ u8 basec, subc, irqline; ++ u16 regoffset; ++ u8 b_singlefunc = _FALSE; ++ ++ *busnum = 0xFF; ++ *devnum = 0xFF; ++ *funcnum = 0xFF; ++ ++ // perform a complete pci bus scan operation ++ for (busnum_idx = 0; busnum_idx < PCI_MAX_BRIDGE_NUMBER; busnum_idx++) //255 ++ { ++ for (devicenum_idx = 0; devicenum_idx < PCI_MAX_DEVICES; devicenum_idx++) //32 ++ { ++ b_singlefunc = _FALSE; ++ for (functionnum_idx = 0; functionnum_idx < PCI_MAX_FUNCTION; functionnum_idx++) //8 ++ { ++ // ++ // We have to skip redundant Bus scan to prevent unexpected system hang ++ // if single function is present in this device. ++ // 2009.02.26. ++ // ++ if (functionnum_idx == 0) ++ { ++ //4 get header type (DWORD #3) ++ pcicfg_addrport = (busnum_idx << 16) | (devicenum_idx << 11) | (functionnum_idx << 8) | (1 << 31); ++ //NdisRawWritePortUlong((ULONG_PTR)PCI_CONF_ADDRESS , pcicfg_addrport + (3 << 2)); ++ //NdisRawReadPortUlong((ULONG_PTR)PCI_CONF_DATA, &headertype); ++ NdisRawWritePortUlong(PCI_CONF_ADDRESS, pcicfg_addrport + (3 << 2)); ++ NdisRawReadPortUlong(PCI_CONF_DATA, &headertype); ++ headertype = ((headertype >> 16) & 0x0080) >> 7; // address 0x0e[7]. ++ if (headertype == 0) //Single function ++ b_singlefunc = _TRUE; ++ } ++ else ++ {//By pass the following scan process. ++ if (b_singlefunc == _TRUE) ++ break; ++ } ++ ++ pcicfg_addrport = (busnum_idx << 16) | (devicenum_idx << 11) | (functionnum_idx << 8) | (1 << 31); ++ ++ //4 // Get vendorid/ deviceid ++ // set up address port at 0xCF8 offset field= 0 (dev|vend) ++ NdisRawWritePortUlong(PCI_CONF_ADDRESS, pcicfg_addrport); ++ // now grab data port with device|vendor 4 byte dword ++ NdisRawReadPortUlong(PCI_CONF_DATA, &dev_venid); ++ ++ //4 Get irql ++ regoffset = 0x3C; ++ pcicfg_addrport = (busnum_idx << 16) | (devicenum_idx << 11) | (functionnum_idx << 8) | (1 << 31) | (regoffset & 0xFFFFFFFC); ++ NdisRawWritePortUlong(PCI_CONF_ADDRESS, pcicfg_addrport); ++ NdisRawReadPortUchar((PCI_CONF_DATA + (regoffset & 0x3)), &irqline); ++ ++ venId = (u16) (dev_venid >> 0) & 0xFFFF; ++ devId = (u16) (dev_venid >> 16) & 0xFFFF; ++ ++ //4 get Class Code ++ pcicfg_addrport = (busnum_idx << 16) | (devicenum_idx << 11) | (functionnum_idx << 8) | (1 << 31); ++ NdisRawWritePortUlong(PCI_CONF_ADDRESS, pcicfg_addrport + (2 << 2)); ++ NdisRawReadPortUlong(PCI_CONF_DATA, &classcode); ++ classcode = classcode >> 8; ++ ++ basec = (u8) (classcode >> 16) & 0xFF; ++ subc = (u8) (classcode >> 8) & 0xFF; ++ ++ //4 get field 0x19 value (DWORD #6) ++ NdisRawWritePortUlong(PCI_CONF_ADDRESS, pcicfg_addrport + (6 << 2)); ++ NdisRawReadPortUlong(PCI_CONF_DATA, &field19); ++ field19 = (field19 >> 8) & 0xFF; ++ ++ //4 Matching Class Code and filed19. ++ if ((basec == basecode) && (subc == subclass) && ((field19 == filed19val) || (filed19val == U1DONTCARE))) { ++ *busnum = busnum_idx; ++ *devnum = devicenum_idx; ++ *funcnum = functionnum_idx; ++ *vendorid = venId; ++ *deviceid = devId; ++ ++ DBG_8192C("GetPciBridegInfo : Find Device(%X:%X) bus=%d dev=%d, func=%d\n", ++ venId, devId, busnum_idx, devicenum_idx, functionnum_idx); ++ ++ return _TRUE; ++ } ++ } ++ } ++ } ++ ++ DBG_8192C("GetPciBridegInfo(): Cannot Find PciBridge for Device\n"); ++ ++ return _FALSE; ++} // end of GetPciBridegInfo ++ ++// ++//Description: ++//To find specific bridge information. ++// ++static void rtw_find_bridge_info(_adapter *padapter) ++{ ++ struct dvobj_priv *pdvobjpriv = &padapter->dvobjpriv; ++ struct pci_priv *pcipriv = &(pdvobjpriv->pcipriv); ++ u8 pcibridge_busnum = 0xff; ++ u8 pcibridge_devnum = 0xff; ++ u8 pcibridge_funcnum = 0xff; ++ u16 pcibridge_vendorid = 0xff; ++ u16 pcibridge_deviceid = 0xff; ++ u8 tmp = 0; ++ ++ rtw_get_pci_brideg_info(padapter, ++ PCI_CLASS_BRIDGE_DEV, ++ PCI_SUBCLASS_BR_PCI_TO_PCI, ++ pcipriv->busnumber, ++ &pcibridge_busnum, ++ &pcibridge_devnum, &pcibridge_funcnum, ++ &pcibridge_vendorid, &pcibridge_deviceid); ++ ++ // match the array of vendor id and regonize which chipset is used. ++ pcipriv->pcibridge_vendor = PCI_BRIDGE_VENDOR_UNKNOWN; ++ ++ for (tmp = 0; tmp < PCI_BRIDGE_VENDOR_MAX; tmp++) { ++ if (pcibridge_vendorid == pcibridge_vendors[tmp]) { ++ pcipriv->pcibridge_vendor = tmp; ++ DBG_8192C("Pci Bridge Vendor is found index: %d\n", tmp); ++ break; ++ } ++ } ++ DBG_8192C("Pci Bridge Vendor is %x\n", pcibridge_vendors[tmp]); ++ ++ // Update corresponding PCI bus info. ++ pcipriv->pcibridge_busnum = pcibridge_busnum; ++ pcipriv->pcibridge_devnum = pcibridge_devnum; ++ pcipriv->pcibridge_funcnum = pcibridge_funcnum; ++ pcipriv->pcibridge_vendorid = pcibridge_vendorid; ++ pcipriv->pcibridge_deviceid = pcibridge_deviceid; ++ ++} ++ ++static u8 ++rtw_get_amd_l1_patch(_adapter *padapter, u8 busnum, u8 devnum, ++ u8 funcnum) ++{ ++ u8 status = _FALSE; ++ u8 offset_e0; ++ unsigned offset_e4; ++ u32 pcicfg_addrport = 0; ++ ++ pcicfg_addrport = (busnum << 16) | (devnum << 11) | (funcnum << 8) | (1 << 31); ++ ++ NdisRawWritePortUlong(PCI_CONF_ADDRESS, pcicfg_addrport + 0xE0); ++ NdisRawWritePortUchar(PCI_CONF_DATA, 0xA0); ++ ++ NdisRawWritePortUlong(PCI_CONF_ADDRESS, pcicfg_addrport + 0xE0); ++ NdisRawReadPortUchar(PCI_CONF_DATA, &offset_e0); ++ ++ if (offset_e0 == 0xA0) ++ { ++ NdisRawWritePortUlong(PCI_CONF_ADDRESS, pcicfg_addrport + 0xE4); ++ NdisRawReadPortUlong(PCI_CONF_DATA, &offset_e4); ++ //DbgPrint("Offset E4 %x\n", offset_e4); ++ if (offset_e4 & BIT(23)) ++ status = _TRUE; ++ } ++ ++ return status; ++} ++#else ++/*Disable RTL8192SE ASPM & Disable Pci Bridge ASPM*/ ++void rtw_pci_disable_aspm(_adapter *padapter) ++{ ++ struct dvobj_priv *pdvobjpriv = &padapter->dvobjpriv; ++ struct pwrctrl_priv *pwrpriv = &padapter->pwrctrlpriv; ++ struct pci_dev *pdev = pdvobjpriv->ppcidev; ++ struct pci_dev *bridge_pdev = pdev->bus->self; ++ struct pci_priv *pcipriv = &(pdvobjpriv->pcipriv); ++ u8 linkctrl_reg; ++ u16 pcibridge_linkctrlreg; ++ u16 aspmlevel = 0; ++ ++ // We do not diable/enable ASPM by driver, in the future, the BIOS will enable host and NIC ASPM. ++ // Advertised by SD1 victorh. Added by tynli. 2009.11.23. ++ if(pdvobjpriv->const_pci_aspm == 0) ++ return; ++ ++ if(!padapter->hw_init_completed) ++ return; ++ ++ if (pcipriv->pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) { ++ RT_TRACE(_module_hci_intfs_c_, _drv_err_, ("%s(): PCI(Bridge) UNKNOWN.\n", __FUNCTION__)); ++ return; ++ } ++ ++ linkctrl_reg = pcipriv->linkctrl_reg; ++ pcibridge_linkctrlreg = pcipriv->pcibridge_linkctrlreg; ++ ++ // Set corresponding value. ++ aspmlevel |= BIT(0) | BIT(1); ++ linkctrl_reg &=~aspmlevel; ++ pcibridge_linkctrlreg &=~aspmlevel; ++ ++ if (pwrpriv->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) { ++ RT_CLEAR_PS_LEVEL(pwrpriv, RT_RF_OFF_LEVL_CLK_REQ); ++ rtw_pci_switch_clk_req(padapter, 0x0); ++ } ++ ++ { ++ /*for promising device will in L0 state after an I/O.*/ ++ u8 tmp_u1b; ++ pci_read_config_byte(pdev, 0x80, &tmp_u1b); ++ } ++ ++ rtw_pci_platform_switch_device_pci_aspm(padapter, linkctrl_reg); ++ rtw_udelay_os(50); ++ ++ //When there exists anyone's BusNum, DevNum, and FuncNum that are set to 0xff, ++ // we do not execute any action and return. Added by tynli. ++ if( (pcipriv->busnumber == 0xff && pcipriv->devnumber == 0xff && pcipriv->funcnumber == 0xff) || ++ (pcipriv->pcibridge_busnum == 0xff && pcipriv->pcibridge_devnum == 0xff && pcipriv->pcibridge_funcnum == 0xff) ) ++ { ++ // Do Nothing!! ++ } ++ else ++ { ++ /*Disable Pci Bridge ASPM*/ ++ //NdisRawWritePortUlong(PCI_CONF_ADDRESS, pcicfg_addrport + (num4bytes << 2)); ++ //NdisRawWritePortUchar(PCI_CONF_DATA, pcibridge_linkctrlreg); ++ pci_write_config_byte(bridge_pdev, pcipriv->pcibridge_pciehdr_offset + 0x10, pcibridge_linkctrlreg); ++ ++ DBG_8192C("rtw_pci_disable_aspm():PciBridge busnumber[%x], DevNumbe[%x], funcnumber[%x], Write reg[%x] = %x\n", ++ pcipriv->pcibridge_busnum, pcipriv->pcibridge_devnum, ++ pcipriv->pcibridge_funcnum, ++ (pcipriv->pcibridge_pciehdr_offset+0x10), pcibridge_linkctrlreg); ++ ++ rtw_udelay_os(50); ++ } ++ ++} ++ ++/*Enable RTL8192SE ASPM & Enable Pci Bridge ASPM for ++power saving We should follow the sequence to enable ++RTL8192SE first then enable Pci Bridge ASPM ++or the system will show bluescreen.*/ ++void rtw_pci_enable_aspm(_adapter *padapter) ++{ ++ struct dvobj_priv *pdvobjpriv = &padapter->dvobjpriv; ++ struct pwrctrl_priv *pwrpriv = &padapter->pwrctrlpriv; ++ struct pci_dev *pdev = pdvobjpriv->ppcidev; ++ struct pci_dev *bridge_pdev = pdev->bus->self; ++ struct pci_priv *pcipriv = &(pdvobjpriv->pcipriv); ++ u16 aspmlevel = 0; ++ u8 u_pcibridge_aspmsetting = 0; ++ u8 u_device_aspmsetting = 0; ++ u32 u_device_aspmsupportsetting = 0; ++ ++ // We do not diable/enable ASPM by driver, in the future, the BIOS will enable host and NIC ASPM. ++ // Advertised by SD1 victorh. Added by tynli. 2009.11.23. ++ if(pdvobjpriv->const_pci_aspm == 0) ++ return; ++ ++ //When there exists anyone's BusNum, DevNum, and FuncNum that are set to 0xff, ++ // we do not execute any action and return. Added by tynli. ++ if( (pcipriv->busnumber == 0xff && pcipriv->devnumber == 0xff && pcipriv->funcnumber == 0xff) || ++ (pcipriv->pcibridge_busnum == 0xff && pcipriv->pcibridge_devnum == 0xff && pcipriv->pcibridge_funcnum == 0xff) ) ++ { ++ DBG_8192C("rtw_pci_enable_aspm(): Fail to enable ASPM. Cannot find the Bus of PCI(Bridge).\n"); ++ return; ++ } ++ ++//Get Bridge ASPM Support ++//not to enable bridge aspm if bridge does not support ++//Added by sherry 20100803 ++ if (IS_HARDWARE_TYPE_8192DE(padapter)) ++ { ++ //PciCfgAddrPort = (pcipriv->pcibridge_busnum << 16)|(pcipriv->pcibridge_devnum<< 11)|(pcipriv->pcibridge_funcnum << 8)|(1 << 31); ++ //Num4Bytes = (pcipriv->pcibridge_pciehdr_offset+0x0C)/4; ++ //NdisRawWritePortUlong((ULONG_PTR)PCI_CONF_ADDRESS , PciCfgAddrPort+(Num4Bytes << 2)); ++ //NdisRawReadPortUlong((ULONG_PTR)PCI_CONF_DATA,&uDeviceASPMSupportSetting); ++ pci_read_config_dword(bridge_pdev, (pcipriv->pcibridge_pciehdr_offset+0x0C), &u_device_aspmsupportsetting); ++ DBG_8192C("rtw_pci_enable_aspm(): Bridge ASPM support %x \n",u_device_aspmsupportsetting); ++ if(((u_device_aspmsupportsetting & BIT(11)) != BIT(11)) || ((u_device_aspmsupportsetting & BIT(10)) != BIT(10))) ++ { ++ if(pdvobjpriv->const_devicepci_aspm_setting == 3) ++ { ++ DBG_8192C("rtw_pci_enable_aspm(): Bridge not support L0S or L1\n"); ++ return; ++ } ++ else if(pdvobjpriv->const_devicepci_aspm_setting == 2) ++ { ++ if((u_device_aspmsupportsetting & BIT(11)) != BIT(11)) ++ { ++ DBG_8192C("rtw_pci_enable_aspm(): Bridge not support L1 \n"); ++ return; ++ } ++ } ++ else if(pdvobjpriv->const_devicepci_aspm_setting == 1) ++ { ++ if((u_device_aspmsupportsetting & BIT(10)) != BIT(10)) ++ { ++ DBG_8192C("rtw_pci_enable_aspm(): Bridge not support L0s \n"); ++ return; ++ } ++ ++ } ++ } ++ else ++ { ++ DBG_8192C("rtw_pci_enable_aspm(): Bridge support L0s and L1 \n"); ++ } ++ } ++ ++ ++ /*Enable Pci Bridge ASPM*/ ++ //PciCfgAddrPort = (pcipriv->pcibridge_busnum << 16)|(pcipriv->pcibridge_devnum<< 11) |(pcipriv->pcibridge_funcnum << 8)|(1 << 31); ++ //Num4Bytes = (pcipriv->pcibridge_pciehdr_offset+0x10)/4; ++ // set up address port at 0xCF8 offset field= 0 (dev|vend) ++ //NdisRawWritePortUlong(PCI_CONF_ADDRESS, PciCfgAddrPort + (Num4Bytes << 2)); ++ // now grab data port with device|vendor 4 byte dword ++ ++ u_pcibridge_aspmsetting = pcipriv->pcibridge_linkctrlreg; ++ u_pcibridge_aspmsetting |= pdvobjpriv->const_hostpci_aspm_setting; ++ ++ if (pcipriv->pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL || ++ pcipriv->pcibridge_vendor == PCI_BRIDGE_VENDOR_SIS ) ++ u_pcibridge_aspmsetting &= ~BIT(0); // for intel host 42 device 43 ++ ++ //NdisRawWritePortUchar(PCI_CONF_DATA, u_pcibridge_aspmsetting); ++ pci_write_config_byte(bridge_pdev, (pcipriv->pcibridge_pciehdr_offset+0x10), u_pcibridge_aspmsetting); ++ ++ DBG_8192C("PlatformEnableASPM():PciBridge busnumber[%x], DevNumbe[%x], funcnumber[%x], Write reg[%x] = %x\n", ++ pcipriv->pcibridge_busnum, pcipriv->pcibridge_devnum, pcipriv->pcibridge_funcnum, ++ (pcipriv->pcibridge_pciehdr_offset+0x10), ++ u_pcibridge_aspmsetting); ++ ++ rtw_udelay_os(50); ++ ++ /*Get ASPM level (with/without Clock Req)*/ ++ aspmlevel |= pdvobjpriv->const_devicepci_aspm_setting; ++ u_device_aspmsetting = pcipriv->linkctrl_reg; ++ u_device_aspmsetting |= aspmlevel; // device 43 ++ ++ rtw_pci_platform_switch_device_pci_aspm(padapter, u_device_aspmsetting); ++ ++ if (pwrpriv->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) { ++ rtw_pci_switch_clk_req(padapter, (pwrpriv->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) ? 1 : 0); ++ RT_SET_PS_LEVEL(pwrpriv, RT_RF_OFF_LEVL_CLK_REQ); ++ } ++ ++ rtw_udelay_os(50); ++} ++ ++static u8 rtw_pci_get_amd_l1_patch(_adapter *padapter) ++{ ++ struct dvobj_priv *pdvobjpriv = &padapter->dvobjpriv; ++ struct pci_dev *pdev = pdvobjpriv->ppcidev; ++ struct pci_dev *bridge_pdev = pdev->bus->self; ++ u8 status = _FALSE; ++ u8 offset_e0; ++ u32 offset_e4; ++ ++ //NdisRawWritePortUlong(PCI_CONF_ADDRESS,pcicfg_addrport + 0xE0); ++ //NdisRawWritePortUchar(PCI_CONF_DATA, 0xA0); ++ pci_write_config_byte(bridge_pdev, 0xE0, 0xA0); ++ ++ //NdisRawWritePortUlong(PCI_CONF_ADDRESS,pcicfg_addrport + 0xE0); ++ //NdisRawReadPortUchar(PCI_CONF_DATA, &offset_e0); ++ pci_read_config_byte(bridge_pdev, 0xE0, &offset_e0); ++ ++ if (offset_e0 == 0xA0) { ++ //NdisRawWritePortUlong(PCI_CONF_ADDRESS, pcicfg_addrport + 0xE4); ++ //NdisRawReadPortUlong(PCI_CONF_DATA, &offset_e4); ++ pci_read_config_dword(bridge_pdev, 0xE4, &offset_e4); ++ if (offset_e4 & BIT(23)) ++ status = _TRUE; ++ } ++ ++ return status; ++} ++ ++static void rtw_pci_get_linkcontrol_field(_adapter *padapter) ++{ ++ struct dvobj_priv *pdvobjpriv = &padapter->dvobjpriv; ++ struct pci_priv *pcipriv = &(pdvobjpriv->pcipriv); ++ struct pci_dev *pdev = pdvobjpriv->ppcidev; ++ struct pci_dev *bridge_pdev = pdev->bus->self; ++ u8 capabilityoffset = pcipriv->pcibridge_pciehdr_offset; ++ u8 linkctrl_reg; ++ ++ /*Read Link Control Register*/ ++ pci_read_config_byte(bridge_pdev, capabilityoffset + PCI_EXP_LNKCTL, &linkctrl_reg); ++ ++ pcipriv->pcibridge_linkctrlreg = linkctrl_reg; ++} ++#endif ++ ++static void rtw_pci_parse_configuration(struct pci_dev *pdev, _adapter *padapter) ++{ ++ struct dvobj_priv *pdvobjpriv = &padapter->dvobjpriv; ++ struct pci_priv *pcipriv = &(pdvobjpriv->pcipriv); ++ u8 tmp; ++ int pos; ++ u8 linkctrl_reg; ++ ++ //Link Control Register ++ pos = pci_find_capability(pdev, PCI_CAP_ID_EXP); ++ pci_read_config_byte(pdev, pos + PCI_EXP_LNKCTL, &linkctrl_reg); ++ pcipriv->linkctrl_reg = linkctrl_reg; ++ ++ //DBG_8192C("Link Control Register = %x\n", pcipriv->linkctrl_reg); ++ ++ pci_read_config_byte(pdev, 0x98, &tmp); ++ tmp |= BIT(4); ++ pci_write_config_byte(pdev, 0x98, tmp); ++ ++ //tmp = 0x17; ++ //pci_write_config_byte(pdev, 0x70f, tmp); ++} ++ ++// ++// Update PCI dependent default settings. ++// ++static void rtw_pci_update_default_setting(_adapter *padapter) ++{ ++ struct dvobj_priv *pdvobjpriv = &padapter->dvobjpriv; ++ struct pci_priv *pcipriv = &(pdvobjpriv->pcipriv); ++ struct pwrctrl_priv *pwrpriv = &padapter->pwrctrlpriv; ++ ++ //reset pPSC->reg_rfps_level & priv->b_support_aspm ++ pwrpriv->reg_rfps_level = 0; ++ pwrpriv->b_support_aspm = 0; ++ ++ // Dynamic Mechanism, ++ //pAdapter->HalFunc.SetHalDefVarHandler(pAdapter, HAL_DEF_INIT_GAIN, &(pDevice->InitGainState)); ++ ++ // Update PCI ASPM setting ++ pwrpriv->const_amdpci_aspm = pdvobjpriv->const_amdpci_aspm; ++ switch (pdvobjpriv->const_pci_aspm) { ++ case 0: // No ASPM ++ break; ++ ++ case 1: // ASPM dynamically enabled/disable. ++ pwrpriv->reg_rfps_level |= RT_RF_LPS_LEVEL_ASPM; ++ break; ++ ++ case 2: // ASPM with Clock Req dynamically enabled/disable. ++ pwrpriv->reg_rfps_level |= (RT_RF_LPS_LEVEL_ASPM | RT_RF_OFF_LEVL_CLK_REQ); ++ break; ++ ++ case 3: // Always enable ASPM and Clock Req from initialization to halt. ++ pwrpriv->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM); ++ pwrpriv->reg_rfps_level |= (RT_RF_PS_LEVEL_ALWAYS_ASPM | RT_RF_OFF_LEVL_CLK_REQ); ++ break; ++ ++ case 4: // Always enable ASPM without Clock Req from initialization to halt. ++ pwrpriv->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM | RT_RF_OFF_LEVL_CLK_REQ); ++ pwrpriv->reg_rfps_level |= RT_RF_PS_LEVEL_ALWAYS_ASPM; ++ break; ++ } ++ ++ pwrpriv->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC; ++ ++ // Update Radio OFF setting ++ switch (pdvobjpriv->const_hwsw_rfoff_d3) { ++ case 1: ++ if (pwrpriv->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM) ++ pwrpriv->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM; ++ break; ++ ++ case 2: ++ if (pwrpriv->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM) ++ pwrpriv->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM; ++ pwrpriv->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC; ++ break; ++ ++ case 3: ++ pwrpriv->reg_rfps_level |= RT_RF_OFF_LEVL_PCI_D3; ++ break; ++ } ++ ++ // Update Rx 2R setting ++ //pPSC->reg_rfps_level |= ((pDevice->RegLPS2RDisable) ? RT_RF_LPS_DISALBE_2R : 0); ++ ++ // ++ // Set HW definition to determine if it supports ASPM. ++ // ++ switch (pdvobjpriv->const_support_pciaspm) { ++ case 0: // Not support ASPM. ++ { ++ u8 b_support_aspm = _FALSE; ++ pwrpriv->b_support_aspm = b_support_aspm; ++ } ++ break; ++ ++ case 1: // Support ASPM. ++ { ++ u8 b_support_aspm = _TRUE; ++ u8 b_support_backdoor = _TRUE; ++ ++ pwrpriv->b_support_aspm = b_support_aspm; ++ ++ /*if(pAdapter->MgntInfo.CustomerID == RT_CID_TOSHIBA && ++ pcipriv->pcibridge_vendor == PCI_BRIDGE_VENDOR_AMD && ++ !pcipriv->amd_l1_patch) ++ b_support_backdoor = _FALSE;*/ ++ ++ pwrpriv->b_support_backdoor = b_support_backdoor; ++ } ++ break; ++ ++ case 2: // Set by Chipset. ++ // ASPM value set by chipset. ++ if (pcipriv->pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL) { ++ u8 b_support_aspm = _TRUE; ++ pwrpriv->b_support_aspm = b_support_aspm; ++ } ++ break; ++ ++ default: ++ // Do nothing. Set when finding the chipset. ++ break; ++ } ++} ++ ++static void rtw_pci_initialize_adapter_common(_adapter *padapter) ++{ ++ struct pwrctrl_priv *pwrpriv = &padapter->pwrctrlpriv; ++ ++ rtw_pci_update_default_setting(padapter); ++ ++ if (pwrpriv->reg_rfps_level & RT_RF_PS_LEVEL_ALWAYS_ASPM) { ++ // Always enable ASPM & Clock Req. ++ rtw_pci_enable_aspm(padapter); ++ RT_SET_PS_LEVEL(pwrpriv, RT_RF_PS_LEVEL_ALWAYS_ASPM); ++ } ++ ++} ++ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)) || (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,18)) ++#define rtw_pci_interrupt(x,y,z) rtw_pci_interrupt(x,y) ++#endif ++ ++static irqreturn_t rtw_pci_interrupt(int irq, void *priv, struct pt_regs *regs) ++{ ++ _adapter *padapter = (_adapter *)priv; ++ struct dvobj_priv *pdvobjpriv = &padapter->dvobjpriv; ++ ++ ++ if (pdvobjpriv->irq_enabled == 0) { ++ return IRQ_HANDLED; ++ } ++ ++ if(padapter->HalFunc.interrupt_handler(padapter) == _FAIL) ++ return IRQ_HANDLED; ++ //return IRQ_NONE; ++ ++ return IRQ_HANDLED; ++} ++ ++static u32 pci_dvobj_init(_adapter *padapter) ++{ ++ u32 status = _SUCCESS; ++ struct dvobj_priv *pdvobjpriv = &padapter->dvobjpriv; ++ struct pci_priv *pcipriv = &(pdvobjpriv->pcipriv); ++ struct pci_dev *pdev = pdvobjpriv->ppcidev; ++ struct pci_dev *bridge_pdev = pdev->bus->self; ++ u8 tmp; ++ ++_func_enter_; ++ ++#if 1 ++ /*find bus info*/ ++ pcipriv->busnumber = pdev->bus->number; ++ pcipriv->devnumber = PCI_SLOT(pdev->devfn); ++ pcipriv->funcnumber = PCI_FUNC(pdev->devfn); ++ ++ /*find bridge info*/ ++ pcipriv->pcibridge_vendor = PCI_BRIDGE_VENDOR_UNKNOWN; ++ if(bridge_pdev){ ++ pcipriv->pcibridge_vendorid = bridge_pdev->vendor; ++ for (tmp = 0; tmp < PCI_BRIDGE_VENDOR_MAX; tmp++) { ++ if (bridge_pdev->vendor == pcibridge_vendors[tmp]) { ++ pcipriv->pcibridge_vendor = tmp; ++ DBG_8192C("Pci Bridge Vendor is found index: %d, %x\n", tmp, pcibridge_vendors[tmp]); ++ break; ++ } ++ } ++ } ++ ++ //if (pcipriv->pcibridge_vendor != PCI_BRIDGE_VENDOR_UNKNOWN) { ++ if(bridge_pdev){ ++ pcipriv->pcibridge_busnum = bridge_pdev->bus->number; ++ pcipriv->pcibridge_devnum = PCI_SLOT(bridge_pdev->devfn); ++ pcipriv->pcibridge_funcnum = PCI_FUNC(bridge_pdev->devfn); ++ ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,34)) ++ pcipriv->pcibridge_pciehdr_offset = pci_find_capability(bridge_pdev, PCI_CAP_ID_EXP); ++#else ++ pcipriv->pcibridge_pciehdr_offset = bridge_pdev->pcie_cap; ++#endif ++ ++ rtw_pci_get_linkcontrol_field(padapter); ++ ++ if (pcipriv->pcibridge_vendor == PCI_BRIDGE_VENDOR_AMD) { ++ pcipriv->amd_l1_patch = rtw_pci_get_amd_l1_patch(padapter); ++ } ++ } ++#else ++ // ++ // Find bridge related info. ++ // ++ rtw_get_pci_bus_info(padapter, ++ pdev->vendor, ++ pdev->device, ++ (u8) pdvobjpriv->irqline, ++ 0x02, 0x80, U1DONTCARE, ++ &pcipriv->busnumber, ++ &pcipriv->devnumber, ++ &pcipriv->funcnumber); ++ ++ rtw_find_bridge_info(padapter); ++ ++ if (pcipriv->pcibridge_vendor != PCI_BRIDGE_VENDOR_UNKNOWN) { ++ rtw_get_link_control_field(padapter, ++ pcipriv->pcibridge_busnum, ++ pcipriv->pcibridge_devnum, ++ pcipriv->pcibridge_funcnum); ++ ++ if (pcipriv->pcibridge_vendor == PCI_BRIDGE_VENDOR_AMD) { ++ pcipriv->amd_l1_patch = ++ rtw_get_amd_l1_patch(padapter, ++ pcipriv->pcibridge_busnum, ++ pcipriv->pcibridge_devnum, ++ pcipriv->pcibridge_funcnum); ++ } ++ } ++#endif ++ ++ // ++ // Allow the hardware to look at PCI config information. ++ // ++ rtw_pci_parse_configuration(pdev, padapter); ++ ++ DBG_8192C("pcidev busnumber:devnumber:funcnumber:" ++ "vendor:link_ctl %d:%d:%d:%x:%x\n", ++ pcipriv->busnumber, ++ pcipriv->devnumber, ++ pcipriv->funcnumber, ++ pdev->vendor, ++ pcipriv->linkctrl_reg); ++ ++ DBG_8192C("pci_bridge busnumber:devnumber:funcnumber:vendor:" ++ "pcie_cap:link_ctl_reg: %d:%d:%d:%x:%x:%x:%x\n", ++ pcipriv->pcibridge_busnum, ++ pcipriv->pcibridge_devnum, ++ pcipriv->pcibridge_funcnum, ++ pcibridge_vendors[pcipriv->pcibridge_vendor], ++ pcipriv->pcibridge_pciehdr_offset, ++ pcipriv->pcibridge_linkctrlreg, ++ pcipriv->amd_l1_patch); ++ ++ //.2 ++ if ((rtw_init_io_priv(padapter)) == _FAIL) ++ { ++ RT_TRACE(_module_hci_intfs_c_,_drv_err_,(" \n Can't init io_reqs\n")); ++ status = _FAIL; ++ } ++ ++ //.3 ++ intf_read_chip_version(padapter); ++ //.4 ++ intf_chip_configure(padapter); ++ ++_func_exit_; ++ ++ return status; ++} ++ ++static void pci_dvobj_deinit(_adapter * padapter) ++{ ++ //struct dvobj_priv *pdvobjpriv=&padapter->dvobjpriv; ++ ++_func_enter_; ++ ++_func_exit_; ++} ++ ++ ++static void decide_chip_type_by_pci_device_id(_adapter *padapter, struct pci_dev *pdev) ++{ ++ u16 venderid, deviceid, irqline; ++ u8 revisionid; ++ struct dvobj_priv *pdvobjpriv=&padapter->dvobjpriv; ++ ++ ++ venderid = pdev->vendor; ++ deviceid = pdev->device; ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,23)) ++ pci_read_config_byte(pdev, PCI_REVISION_ID, &revisionid); // PCI_REVISION_ID 0x08 ++#else ++ revisionid = pdev->revision; ++#endif ++ pci_read_config_word(pdev, PCI_INTERRUPT_LINE, &irqline); // PCI_INTERRUPT_LINE 0x3c ++ pdvobjpriv->irqline = irqline; ++ ++ ++ // ++ // Decide hardware type here. ++ // ++ if( deviceid == HAL_HW_PCI_8185_DEVICE_ID || ++ deviceid == HAL_HW_PCI_8188_DEVICE_ID || ++ deviceid == HAL_HW_PCI_8198_DEVICE_ID) ++ { ++ DBG_8192C("Adapter (8185/8185B) is found- VendorID/DeviceID=%x/%x\n", venderid, deviceid); ++ padapter->HardwareType=HARDWARE_TYPE_RTL8185; ++ } ++ else if (deviceid == HAL_HW_PCI_8190_DEVICE_ID || ++ deviceid == HAL_HW_PCI_0045_DEVICE_ID || ++ deviceid == HAL_HW_PCI_0046_DEVICE_ID || ++ deviceid == HAL_HW_PCI_DLINK_DEVICE_ID) ++ { ++ DBG_8192C("Adapter(8190 PCI) is found - vendorid/deviceid=%x/%x\n", venderid, deviceid); ++ padapter->HardwareType = HARDWARE_TYPE_RTL8190P; ++ } ++ else if (deviceid == HAL_HW_PCI_8192_DEVICE_ID || ++ deviceid == HAL_HW_PCI_0044_DEVICE_ID || ++ deviceid == HAL_HW_PCI_0047_DEVICE_ID || ++ deviceid == HAL_HW_PCI_8192SE_DEVICE_ID || ++ deviceid == HAL_HW_PCI_8174_DEVICE_ID || ++ deviceid == HAL_HW_PCI_8173_DEVICE_ID || ++ deviceid == HAL_HW_PCI_8172_DEVICE_ID || ++ deviceid == HAL_HW_PCI_8171_DEVICE_ID) ++ { ++ // 8192e and and 8192se may have the same device ID 8192. However, their Revision ++ // ID is different ++ // Added for 92DE. We deferentiate it from SVID,SDID. ++ if( pdev->subsystem_vendor == 0x10EC && pdev->subsystem_device == 0xE020){ ++ padapter->HardwareType = HARDWARE_TYPE_RTL8192DE; ++ DBG_8192C("Adapter(8192DE) is found - VendorID/DeviceID/RID=%X/%X/%X\n", venderid, deviceid, revisionid); ++ }else{ ++ switch (revisionid) { ++ case HAL_HW_PCI_REVISION_ID_8192PCIE: ++ DBG_8192C("Adapter(8192 PCI-E) is found - vendorid/deviceid=%x/%x\n", venderid, deviceid); ++ padapter->HardwareType = HARDWARE_TYPE_RTL8192E; ++ break; ++ case HAL_HW_PCI_REVISION_ID_8192SE: ++ DBG_8192C("Adapter(8192SE) is found - vendorid/deviceid=%x/%x\n", venderid, deviceid); ++ padapter->HardwareType = HARDWARE_TYPE_RTL8192SE; ++ break; ++ default: ++ DBG_8192C("Err: Unknown device - vendorid/deviceid=%x/%x\n", venderid, deviceid); ++ padapter->HardwareType = HARDWARE_TYPE_RTL8192SE; ++ break; ++ } ++ } ++ } ++ else if(deviceid==HAL_HW_PCI_8723E_DEVICE_ID ) ++ {//RTL8723E may have the same device ID with RTL8192CET ++ padapter->HardwareType = HARDWARE_TYPE_RTL8723E; ++ DBG_8192C("Adapter(8723 PCI-E) is found - VendorID/DeviceID=%x/%x\n", venderid, deviceid); ++ } ++ else if (deviceid == HAL_HW_PCI_8192CET_DEVICE_ID || ++ deviceid == HAL_HW_PCI_8192CE_DEVICE_ID || ++ deviceid == HAL_HW_PCI_8191CE_DEVICE_ID || ++ deviceid == HAL_HW_PCI_8188CE_DEVICE_ID) ++ { ++ DBG_8192C("Adapter(8192C PCI-E) is found - vendorid/deviceid=%x/%x\n", venderid, deviceid); ++ padapter->HardwareType = HARDWARE_TYPE_RTL8192CE; ++ } ++ else if (deviceid == HAL_HW_PCI_8192DE_DEVICE_ID || ++ deviceid == HAL_HW_PCI_002B_DEVICE_ID ){ ++ padapter->HardwareType = HARDWARE_TYPE_RTL8192DE; ++ DBG_8192C("Adapter(8192DE) is found - VendorID/DeviceID/RID=%X/%X/%X\n", venderid, deviceid, revisionid); ++ } ++ else ++ { ++ DBG_8192C("Err: Unknown device - vendorid/deviceid=%x/%x\n", venderid, deviceid); ++ //padapter->HardwareType = HAL_DEFAULT_HARDWARE_TYPE; ++ } ++ ++ ++ padapter->chip_type = NULL_CHIP_TYPE; ++ ++ //TODO: ++#ifdef CONFIG_RTL8192C ++ padapter->chip_type = RTL8188C_8192C; ++ padapter->HardwareType = HARDWARE_TYPE_RTL8192CE; ++#endif ++#ifdef CONFIG_RTL8192D ++ pdvobjpriv->InterfaceNumber = revisionid; ++ ++ padapter->chip_type = RTL8192D; ++ padapter->HardwareType = HARDWARE_TYPE_RTL8192DE; ++#endif ++ ++} ++ ++static void pci_intf_start(_adapter *padapter) ++{ ++ ++ RT_TRACE(_module_hci_intfs_c_,_drv_err_,("+pci_intf_start\n")); ++ DBG_8192C("+pci_intf_start\n"); ++ ++ //Enable hw interrupt ++ padapter->HalFunc.enable_interrupt(padapter); ++ ++ RT_TRACE(_module_hci_intfs_c_,_drv_err_,("-pci_intf_start\n")); ++ DBG_8192C("-pci_intf_start\n"); ++} ++ ++static void pci_intf_stop(_adapter *padapter) ++{ ++ ++ RT_TRACE(_module_hci_intfs_c_,_drv_err_,("+pci_intf_stop\n")); ++ ++ //Disable hw interrupt ++ if(padapter->bSurpriseRemoved == _FALSE) ++ { ++ //device still exists, so driver can do i/o operation ++ padapter->HalFunc.disable_interrupt(padapter); ++ RT_TRACE(_module_hci_intfs_c_,_drv_err_,("pci_intf_stop: SurpriseRemoved==_FALSE\n")); ++ } ++ else ++ { ++ // Clear irq_enabled to prevent handle interrupt function. ++ padapter->dvobjpriv.irq_enabled = 0; ++ } ++ ++ RT_TRACE(_module_hci_intfs_c_,_drv_err_,("-pci_intf_stop\n")); ++ ++} ++ ++ ++static void rtw_dev_unload(_adapter *padapter) ++{ ++ struct net_device *pnetdev= (struct net_device*)padapter->pnetdev; ++ ++ RT_TRACE(_module_hci_intfs_c_,_drv_err_,("+rtw_dev_unload\n")); ++ ++ if(padapter->bup == _TRUE) ++ { ++ DBG_8192C("+rtw_dev_unload\n"); ++ //s1. ++/* if(pnetdev) ++ { ++ netif_carrier_off(pnetdev); ++ netif_stop_queue(pnetdev); ++ } ++ ++ //s2. ++ //s2-1. issue rtw_disassoc_cmd to fw ++ rtw_disassoc_cmd(padapter); ++ //s2-2. indicate disconnect to os ++ rtw_indicate_disconnect(padapter); ++ //s2-3. ++ rtw_free_assoc_resources(padapter, 1); ++ //s2-4. ++ rtw_free_network_queue(padapter, _TRUE);*/ ++ ++ padapter->bDriverStopped = _TRUE; ++ ++ //s3. ++ if(padapter->intf_stop) ++ { ++ padapter->intf_stop(padapter); ++ } ++ ++ //s4. ++ rtw_stop_drv_threads(padapter); ++ ++ ++ //s5. ++ if(padapter->bSurpriseRemoved == _FALSE) ++ { ++ DBG_8192C("r871x_dev_unload()->rtl871x_hal_deinit()\n"); ++ rtw_hal_deinit(padapter); ++ ++ padapter->bSurpriseRemoved = _TRUE; ++ } ++ ++ padapter->bup = _FALSE; ++ ++ } ++ else ++ { ++ RT_TRACE(_module_hci_intfs_c_,_drv_err_,("r871x_dev_unload():padapter->bup == _FALSE\n" )); ++ } ++ ++ DBG_8192C("-rtw_dev_unload\n"); ++ ++ RT_TRACE(_module_hci_intfs_c_,_drv_err_,("-rtw_dev_unload\n")); ++ ++} ++ ++static void disable_ht_for_spec_devid(const struct pci_device_id *pdid) ++{ ++#ifdef CONFIG_80211N_HT ++ u16 vid, pid; ++ u32 flags; ++ int i; ++ int num = sizeof(specific_device_id_tbl)/sizeof(struct specific_device_id); ++ ++ for(i=0; ivendor==vid) && (pdid->device==pid) && (flags&SPEC_DEV_ID_DISABLE_HT)) ++ { ++ rtw_ht_enable = 0; ++ rtw_cbw40_enable = 0; ++ rtw_ampdu_enable = 0; ++ } ++ ++ } ++#endif ++} ++ ++#ifdef CONFIG_PM ++static int rtw_suspend(struct pci_dev *pdev, pm_message_t state) ++{ ++ _func_enter_; ++ ++ ++ _func_exit_; ++ return 0; ++} ++ ++static int rtw_resume(struct pci_dev *pdev) ++{ ++ _func_enter_; ++ ++ ++ _func_exit_; ++ ++ return 0; ++} ++#endif ++ ++#ifdef RTK_DMP_PLATFORM ++#define pci_iounmap(x,y) iounmap(y) ++#endif ++ ++extern char* ifname; ++ ++/* ++ * drv_init() - a device potentially for us ++ * ++ * notes: drv_init() is called when the bus driver has located a card for us to support. ++ * We accept the new device by returning 0. ++*/ ++static int rtw_drv_init(struct pci_dev *pdev, const struct pci_device_id *pdid) ++{ ++ int i, err = -ENODEV; ++ ++ uint status; ++ _adapter *padapter = NULL; ++ struct dvobj_priv *pdvobjpriv; ++ struct net_device *pnetdev; ++ unsigned long pmem_start, pmem_len, pmem_flags; ++ u8 bdma64 = _FALSE; ++ ++ RT_TRACE(_module_hci_intfs_c_, _drv_err_, ("+rtw_drv_init\n")); ++ //DBG_8192C("+rtw_drv_init\n"); ++ ++ err = pci_enable_device(pdev); ++ if (err) { ++ DBG_8192C(KERN_ERR "%s : Cannot enable new PCI device\n", pci_name(pdev)); ++ return err; ++ } ++ ++#ifdef CONFIG_64BIT_DMA ++ if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) { ++ DBG_8192C("RTL819xCE: Using 64bit DMA\n"); ++ if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) { ++ DBG_8192C(KERN_ERR "Unable to obtain 64bit DMA for consistent allocations\n"); ++ err = -ENOMEM; ++ pci_disable_device(pdev); ++ return err; ++ } ++ bdma64 = _TRUE; ++ } else ++#endif ++ { ++ if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) { ++ if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) { ++ DBG_8192C(KERN_ERR "Unable to obtain 32bit DMA for consistent allocations\n"); ++ err = -ENOMEM; ++ pci_disable_device(pdev); ++ return err; ++ } ++ } ++ } ++ ++ pci_set_master(pdev); ++ ++ //step 0. ++ disable_ht_for_spec_devid(pdid); ++ ++ ++ //step 1. set USB interface data ++ // init data ++ pnetdev = rtw_init_netdev(NULL); ++ if (!pnetdev){ ++ err = -ENOMEM; ++ goto fail1; ++ } ++ rtw_init_netdev_name(pnetdev,ifname); ++ ++ if(bdma64){ ++ pnetdev->features |= NETIF_F_HIGHDMA; ++ } ++ ++#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0) ++ SET_NETDEV_DEV(pnetdev, &pdev->dev); ++#endif ++ ++ padapter = rtw_netdev_priv(pnetdev); ++ pdvobjpriv = &padapter->dvobjpriv; ++ pdvobjpriv->padapter = padapter; ++ pdvobjpriv->ppcidev = pdev; ++ ++ // set data ++ pci_set_drvdata(pdev, pnetdev); ++ ++ err = pci_request_regions(pdev, DRV_NAME); ++ if (err) { ++ DBG_8192C(KERN_ERR "Can't obtain PCI resources\n"); ++ goto fail1; ++ } ++ //MEM map ++ pmem_start = pci_resource_start(pdev, 2); ++ pmem_len = pci_resource_len(pdev, 2); ++ pmem_flags = pci_resource_flags(pdev, 2); ++ ++#ifdef RTK_DMP_PLATFORM ++ pdvobjpriv->pci_mem_start = (unsigned long)ioremap_nocache( pmem_start, pmem_len); ++#else ++ pdvobjpriv->pci_mem_start = (unsigned long)pci_iomap(pdev, 2, pmem_len); // shared mem start ++#endif ++ if (pdvobjpriv->pci_mem_start == 0) { ++ DBG_8192C(KERN_ERR "Can't map PCI mem\n"); ++ goto fail2; ++ } ++ ++ DBG_8192C("Memory mapped space start: 0x%08lx len:%08lx flags:%08lx, after map:0x%08lx\n", ++ pmem_start, pmem_len, pmem_flags, pdvobjpriv->pci_mem_start); ++ ++ // Disable Clk Request */ ++ pci_write_config_byte(pdev, 0x81, 0); ++ // leave D3 mode */ ++ pci_write_config_byte(pdev, 0x44, 0); ++ pci_write_config_byte(pdev, 0x04, 0x06); ++ pci_write_config_byte(pdev, 0x04, 0x07); ++ ++ ++ //set interface_type to usb ++ padapter->interface_type = RTW_PCIE; ++ ++ //step 1-1., decide the chip_type via vid/pid ++ decide_chip_type_by_pci_device_id(padapter, pdev); ++ ++ //step 2. ++ if(padapter->chip_type== RTL8188C_8192C) ++ { ++#ifdef CONFIG_RTL8192C ++ rtl8192ce_set_hal_ops(padapter); ++#endif ++ } ++ else if(padapter->chip_type == RTL8192D) ++ { ++#ifdef CONFIG_RTL8192D ++ rtl8192de_set_hal_ops(padapter); ++#endif ++ } ++ else ++ { ++ status = _FAIL; ++ goto error; ++ } ++ ++ //step 3. initialize the dvobj_priv ++ padapter->dvobj_init=&pci_dvobj_init; ++ padapter->dvobj_deinit=&pci_dvobj_deinit; ++ padapter->intf_start=&pci_intf_start; ++ padapter->intf_stop=&pci_intf_stop; ++ ++ if (padapter->dvobj_init == NULL){ ++ RT_TRACE(_module_hci_intfs_c_,_drv_err_,("\n Initialize dvobjpriv.dvobj_init error!!!\n")); ++ goto error; ++ } ++ ++ status = padapter->dvobj_init(padapter); ++ if (status != _SUCCESS) { ++ RT_TRACE(_module_hci_intfs_c_, _drv_err_, ("initialize device object priv Failed!\n")); ++ goto error; ++ } ++ ++ pnetdev->irq = pdev->irq; ++ ++ //step 4. read efuse/eeprom data and get mac_addr ++ intf_read_chip_info(padapter); ++ ++ //step 5. ++ status = rtw_init_drv_sw(padapter); ++ if(status ==_FAIL){ ++ RT_TRACE(_module_hci_intfs_c_,_drv_err_,("Initialize driver software resource Failed!\n")); ++ goto error; ++ } ++ ++ status = padapter->HalFunc.inirp_init(padapter); ++ if(status ==_FAIL){ ++ RT_TRACE(_module_hci_intfs_c_,_drv_err_,("Initialize PCI desc ring Failed!\n")); ++ goto error; ++ } ++ ++ rtw_macaddr_cfg(padapter->eeprompriv.mac_addr); ++ ++ _rtw_memcpy(pnetdev->dev_addr, padapter->eeprompriv.mac_addr, ETH_ALEN); ++ DBG_8192C("MAC Address from pnetdev->dev_addr= "MAC_FMT"\n", MAC_ARG(pnetdev->dev_addr)); ++ ++ ++ padapter->HalFunc.disable_interrupt(padapter); ++ ++#if defined(IRQF_SHARED) ++ err = request_irq(pdev->irq, &rtw_pci_interrupt, IRQF_SHARED, DRV_NAME, padapter); ++#else ++ err = request_irq(pdev->irq, &rtw_pci_interrupt, SA_SHIRQ, DRV_NAME, padapter); ++#endif ++ if (err) { ++ DBG_8192C("Error allocating IRQ %d",pdev->irq); ++ goto error; ++ } else { ++ pdvobjpriv->irq_alloc = 1; ++ DBG_8192C("Request_irq OK, IRQ %d\n",pdev->irq); ++ } ++ ++ //step 6. Init pci related configuration ++ rtw_pci_initialize_adapter_common(padapter); ++ ++ //step 7. ++ /* Tell the network stack we exist */ ++ if (register_netdev(pnetdev) != 0) { ++ RT_TRACE(_module_hci_intfs_c_,_drv_err_,("register_netdev() failed\n")); ++ goto error; ++ } ++ ++ RT_TRACE(_module_hci_intfs_c_,_drv_err_,("-drv_init - Adapter->bDriverStopped=%d, Adapter->bSurpriseRemoved=%d\n",padapter->bDriverStopped, padapter->bSurpriseRemoved)); ++ RT_TRACE(_module_hci_intfs_c_,_drv_err_,("-871x_drv - drv_init, success!\n")); ++ //DBG_8192C("-871x_drv - drv_init, success!\n"); ++ ++#ifdef CONFIG_PROC_DEBUG ++#ifdef RTK_DMP_PLATFORM ++ rtw_proc_init_one(pnetdev); ++#endif ++#endif ++ ++#ifdef CONFIG_HOSTAPD_MLME ++ hostapd_mode_init(padapter); ++#endif ++ ++#ifdef CONFIG_PLATFORM_RTD2880B ++ DBG_8192C("wlan link up\n"); ++ rtd2885_wlan_netlink_sendMsg("linkup", "8712"); ++#endif ++ ++ return 0; ++ ++error: ++ ++ pci_set_drvdata(pdev, NULL); ++ ++ if (pdvobjpriv->irq_alloc) { ++ free_irq(pdev->irq, padapter); ++ pdvobjpriv->irq_alloc = 0; ++ } ++ ++ if (pdvobjpriv->pci_mem_start != 0) { ++ pci_iounmap(pdev, (void *)pdvobjpriv->pci_mem_start); ++ } ++ ++ pci_dvobj_deinit(padapter); ++ ++ if (pnetdev) ++ { ++ //unregister_netdev(pnetdev); ++ rtw_free_netdev(pnetdev); ++ } ++ ++fail2: ++ pci_release_regions(pdev); ++ ++fail1: ++ pci_disable_device(pdev); ++ ++ DBG_8192C("-871x_pci - drv_init, fail!\n"); ++ ++ return err; ++} ++ ++/* ++ * dev_remove() - our device is being removed ++*/ ++//rmmod module & unplug(SurpriseRemoved) will call r871xu_dev_remove() => how to recognize both ++static void rtw_dev_remove(struct pci_dev *pdev) ++{ ++ struct net_device *pnetdev=pci_get_drvdata(pdev); ++ _adapter *padapter = (_adapter*)rtw_netdev_priv(pnetdev); ++ struct dvobj_priv *pdvobjpriv = &padapter->dvobjpriv; ++ ++_func_exit_; ++ ++ if (unlikely(!padapter)) { ++ return; ++ } ++ ++ DBG_8192C("+rtw_dev_remove\n"); ++ ++#if defined(CONFIG_HAS_EARLYSUSPEND ) || defined(CONFIG_ANDROID_POWER) ++ rtw_unregister_early_suspend(&padapter->pwrctrlpriv); ++#endif ++ ++ LeaveAllPowerSaveMode(padapter); ++ ++#ifdef RTK_DMP_PLATFORM ++ padapter->bSurpriseRemoved = _FALSE; // always trate as device exists ++ // this will let the driver to disable it's interrupt ++#else ++ if(drvpriv.drv_registered == _TRUE) ++ { ++ //DBG_8192C("r871xu_dev_remove():padapter->bSurpriseRemoved == _TRUE\n"); ++ padapter->bSurpriseRemoved = _TRUE; ++ } ++ /*else ++ { ++ //DBG_8192C("r871xu_dev_remove():module removed\n"); ++ padapter->hw_init_completed = _FALSE; ++ }*/ ++#endif ++ ++ ++#ifdef CONFIG_AP_MODE ++ free_mlme_ap_info(padapter); ++#ifdef CONFIG_HOSTAPD_MLME ++ hostapd_mode_unload(padapter); ++#endif //CONFIG_HOSTAPD_MLME ++#endif //CONFIG_AP_MODE ++ ++ if(pnetdev){ ++ unregister_netdev(pnetdev); //will call netdev_close() ++#ifdef CONFIG_PROC_DEBUG ++ rtw_proc_remove_one(pnetdev); ++#endif ++ } ++ ++ rtw_cancel_all_timer(padapter); ++ ++ rtw_dev_unload(padapter); ++ ++ DBG_8192C("+r871xu_dev_remove, hw_init_completed=%d\n", padapter->hw_init_completed); ++ ++ if (pdvobjpriv->irq_alloc) { ++ free_irq(pdev->irq, padapter); ++ pdvobjpriv->irq_alloc = 0; ++ } ++ ++ if (pdvobjpriv->pci_mem_start != 0) { ++ pci_iounmap(pdev, (void *)pdvobjpriv->pci_mem_start); ++ pci_release_regions(pdev); ++ } ++ ++ pci_disable_device(pdev); ++ pci_set_drvdata(pdev, NULL); ++ ++ padapter->HalFunc.inirp_deinit(padapter); ++ //s6. ++ if(padapter->dvobj_deinit) ++ { ++ padapter->dvobj_deinit(padapter); ++ } ++ else ++ { ++ RT_TRACE(_module_hci_intfs_c_,_drv_err_,("Initialize hcipriv.hci_priv_init error!!!\n")); ++ } ++ ++ rtw_free_drv_sw(padapter); ++ ++ //after rtw_free_drv_sw(), padapter has beed freed, don't refer to it. ++ ++ DBG_8192C("-r871xu_dev_remove, done\n"); ++ ++#ifdef CONFIG_PLATFORM_RTD2880B ++ DBG_8192C("wlan link down\n"); ++ rtd2885_wlan_netlink_sendMsg("linkdown", "8712"); ++#endif ++ ++_func_exit_; ++ ++ return; ++ ++} ++ ++ ++static int __init rtw_drv_entry(void) ++{ ++ int ret = 0; ++ ++ RT_TRACE(_module_hci_intfs_c_,_drv_err_,("+rtw_drv_entry\n")); ++ DBG_871X("rtw driver version=%s \n", DRIVERVERSION); ++ DBG_871X("Build at: %s %s\n", __DATE__, __TIME__); ++ drvpriv.drv_registered = _TRUE; ++ ret = pci_register_driver(&drvpriv.rtw_pci_drv); ++ if (ret) { ++ RT_TRACE(_module_hci_intfs_c_, _drv_err_, (": No device found\n")); ++ } ++ ++ return ret; ++} ++ ++static void __exit rtw_drv_halt(void) ++{ ++ RT_TRACE(_module_hci_intfs_c_,_drv_err_,("+rtw_drv_halt\n")); ++ DBG_8192C("+rtw_drv_halt\n"); ++ drvpriv.drv_registered = _FALSE; ++ pci_unregister_driver(&drvpriv.rtw_pci_drv); ++ DBG_8192C("-rtw_drv_halt\n"); ++} ++ ++ ++module_init(rtw_drv_entry); ++module_exit(rtw_drv_halt); ++ +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/os_dep/linux/recv_linux.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/os_dep/linux/recv_linux.c 2013-07-26 19:36:07.000000000 +0000 +@@ -0,0 +1,462 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++#define _RECV_OSDEP_C_ ++ ++#include ++#include ++#include ++ ++#include ++#include ++ ++#include ++#include ++ ++#ifdef CONFIG_USB_HCI ++#include ++#endif ++ ++//init os related resource in struct recv_priv ++int rtw_os_recv_resource_init(struct recv_priv *precvpriv, _adapter *padapter) ++{ ++ int res=_SUCCESS; ++ ++ return res; ++} ++ ++//alloc os related resource in union recv_frame ++int rtw_os_recv_resource_alloc(_adapter *padapter, union recv_frame *precvframe) ++{ ++ int res=_SUCCESS; ++ ++ precvframe->u.hdr.pkt_newalloc = precvframe->u.hdr.pkt = NULL; ++ ++ return res; ++ ++} ++ ++//free os related resource in union recv_frame ++void rtw_os_recv_resource_free(struct recv_priv *precvpriv) ++{ ++ ++} ++ ++ ++//alloc os related resource in struct recv_buf ++int rtw_os_recvbuf_resource_alloc(_adapter *padapter, struct recv_buf *precvbuf) ++{ ++ int res=_SUCCESS; ++ ++#ifdef CONFIG_USB_HCI ++ struct dvobj_priv *pdvobjpriv = &padapter->dvobjpriv; ++ struct usb_device *pusbd = pdvobjpriv->pusbdev; ++ ++ precvbuf->irp_pending = _FALSE; ++ precvbuf->purb = usb_alloc_urb(0, GFP_KERNEL); ++ if(precvbuf->purb == NULL){ ++ res = _FAIL; ++ } ++ ++ precvbuf->pskb = NULL; ++ ++ precvbuf->reuse = _FALSE; ++ ++ precvbuf->pallocated_buf = precvbuf->pbuf = NULL; ++ ++ precvbuf->pdata = precvbuf->phead = precvbuf->ptail = precvbuf->pend = NULL; ++ ++ precvbuf->transfer_len = 0; ++ ++ precvbuf->len = 0; ++ ++ #ifdef CONFIG_USE_USB_BUFFER_ALLOC_RX ++ precvbuf->pallocated_buf = rtw_usb_buffer_alloc(pusbd, (size_t)precvbuf->alloc_sz, GFP_ATOMIC, &precvbuf->dma_transfer_addr); ++ precvbuf->pbuf = precvbuf->pallocated_buf; ++ if(precvbuf->pallocated_buf == NULL) ++ return _FAIL; ++ #endif //CONFIG_USE_USB_BUFFER_ALLOC_RX ++ ++#endif //CONFIG_USB_HCI ++ ++ ++#ifdef CONFIG_SDIO_HCI ++ precvbuf->pskb = NULL; ++ ++ precvbuf->pallocated_buf = precvbuf->pbuf = NULL; ++ ++ precvbuf->pdata = precvbuf->phead = precvbuf->ptail = precvbuf->pend = NULL; ++ ++ precvbuf->len = 0; ++#endif ++ return res; ++ ++} ++ ++//free os related resource in struct recv_buf ++int rtw_os_recvbuf_resource_free(_adapter *padapter, struct recv_buf *precvbuf) ++{ ++ int ret = _SUCCESS; ++ ++#ifdef CONFIG_USB_HCI ++ ++#ifdef CONFIG_USE_USB_BUFFER_ALLOC_RX ++ ++ struct dvobj_priv *pdvobjpriv = &padapter->dvobjpriv; ++ struct usb_device *pusbd = pdvobjpriv->pusbdev; ++ ++ rtw_usb_buffer_free(pusbd, (size_t)precvbuf->alloc_sz, precvbuf->pallocated_buf, precvbuf->dma_transfer_addr); ++ precvbuf->pallocated_buf = NULL; ++ precvbuf->dma_transfer_addr = 0; ++ ++#endif //CONFIG_USE_USB_BUFFER_ALLOC_RX ++ ++ if(precvbuf->purb) ++ { ++ //usb_kill_urb(precvbuf->purb); ++ usb_free_urb(precvbuf->purb); ++ } ++ ++#endif //CONFIG_USB_HCI ++ ++ ++ if(precvbuf->pskb) ++ dev_kfree_skb_any(precvbuf->pskb); ++ ++ ++ return ret; ++ ++} ++ ++void rtw_handle_tkip_mic_err(_adapter *padapter,u8 bgroup) ++{ ++#ifdef CONFIG_IOCTL_CFG80211 ++ enum nl80211_key_type key_type; ++#endif ++ union iwreq_data wrqu; ++ struct iw_michaelmicfailure ev; ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct security_priv *psecuritypriv = &padapter->securitypriv; ++ u32 cur_time = 0; ++ ++ if( psecuritypriv->last_mic_err_time == 0 ) ++ { ++ psecuritypriv->last_mic_err_time = rtw_get_current_time(); ++ } ++ else ++ { ++ cur_time = rtw_get_current_time(); ++ ++ if( cur_time - psecuritypriv->last_mic_err_time < 60*HZ ) ++ { ++ psecuritypriv->btkip_countermeasure = _TRUE; ++ psecuritypriv->last_mic_err_time = 0; ++ psecuritypriv->btkip_countermeasure_time = cur_time; ++ } ++ else ++ { ++ psecuritypriv->last_mic_err_time = rtw_get_current_time(); ++ } ++ } ++ ++#ifdef CONFIG_IOCTL_CFG80211 ++ if ( bgroup ) ++ { ++ key_type |= NL80211_KEYTYPE_GROUP; ++ } ++ else ++ { ++ key_type |= NL80211_KEYTYPE_PAIRWISE; ++ } ++ ++ cfg80211_michael_mic_failure(padapter->pnetdev, (u8 *)&pmlmepriv->assoc_bssid[ 0 ], key_type, -1, ++ NULL, GFP_ATOMIC); ++#endif ++ ++ _rtw_memset( &ev, 0x00, sizeof( ev ) ); ++ if ( bgroup ) ++ { ++ ev.flags |= IW_MICFAILURE_GROUP; ++ } ++ else ++ { ++ ev.flags |= IW_MICFAILURE_PAIRWISE; ++ } ++ ++ ev.src_addr.sa_family = ARPHRD_ETHER; ++ _rtw_memcpy( ev.src_addr.sa_data, &pmlmepriv->assoc_bssid[ 0 ], ETH_ALEN ); ++ ++ _rtw_memset( &wrqu, 0x00, sizeof( wrqu ) ); ++ wrqu.data.length = sizeof( ev ); ++ ++ wireless_send_event( padapter->pnetdev, IWEVMICHAELMICFAILURE, &wrqu, (char*) &ev ); ++} ++ ++void rtw_hostapd_mlme_rx(_adapter *padapter, union recv_frame *precv_frame) ++{ ++#ifdef CONFIG_HOSTAPD_MLME ++ _pkt *skb; ++ struct hostapd_priv *phostapdpriv = padapter->phostapdpriv; ++ struct net_device *pmgnt_netdev = phostapdpriv->pmgnt_netdev; ++ ++ RT_TRACE(_module_recv_osdep_c_, _drv_info_, ("+rtw_hostapd_mlme_rx\n")); ++ ++ skb = precv_frame->u.hdr.pkt; ++ ++ if (skb == NULL) ++ return; ++ ++ skb->data = precv_frame->u.hdr.rx_data; ++ skb->tail = precv_frame->u.hdr.rx_tail; ++ skb->len = precv_frame->u.hdr.len; ++ ++ //pskb_copy = skb_copy(skb, GFP_ATOMIC); ++// if(skb == NULL) goto _exit; ++ ++ skb->dev = pmgnt_netdev; ++ skb->ip_summed = CHECKSUM_NONE; ++ skb->pkt_type = PACKET_OTHERHOST; ++ //skb->protocol = __constant_htons(0x0019); /*ETH_P_80211_RAW*/ ++ skb->protocol = __constant_htons(0x0003); /*ETH_P_80211_RAW*/ ++ ++ //DBG_8192C("(1)data=0x%x, head=0x%x, tail=0x%x, mac_header=0x%x, len=%d\n", skb->data, skb->head, skb->tail, skb->mac_header, skb->len); ++ ++ //skb->mac.raw = skb->data; ++ skb_reset_mac_header(skb); ++ ++ //skb_pull(skb, 24); ++ _rtw_memset(skb->cb, 0, sizeof(skb->cb)); ++ ++ netif_rx(skb); ++ ++ precv_frame->u.hdr.pkt = NULL; // set pointer to NULL before rtw_free_recvframe() if call netif_rx() ++#endif ++} ++ ++int rtw_recv_indicatepkt(_adapter *padapter, union recv_frame *precv_frame) ++{ ++ struct recv_priv *precvpriv; ++ _queue *pfree_recv_queue; ++ _pkt *skb; ++ struct mlme_priv*pmlmepriv = &padapter->mlmepriv; ++#ifdef CONFIG_TCP_CSUM_OFFLOAD_RX ++ struct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib; ++#endif ++ ++#ifdef CONFIG_BR_EXT ++ void *br_port = NULL; ++#endif ++ ++_func_enter_; ++ ++ precvpriv = &(padapter->recvpriv); ++ pfree_recv_queue = &(precvpriv->free_recv_queue); ++ ++#ifdef CONFIG_DRVEXT_MODULE ++ if (drvext_rx_handler(padapter, precv_frame->u.hdr.rx_data, precv_frame->u.hdr.len) == _SUCCESS) ++ { ++ goto _recv_indicatepkt_drop; ++ } ++#endif ++ ++ skb = precv_frame->u.hdr.pkt; ++ if(skb == NULL) ++ { ++ RT_TRACE(_module_recv_osdep_c_,_drv_err_,("rtw_recv_indicatepkt():skb==NULL something wrong!!!!\n")); ++ goto _recv_indicatepkt_drop; ++ } ++ ++ RT_TRACE(_module_recv_osdep_c_,_drv_info_,("rtw_recv_indicatepkt():skb != NULL !!!\n")); ++ RT_TRACE(_module_recv_osdep_c_,_drv_info_,("rtw_recv_indicatepkt():precv_frame->u.hdr.rx_head=%p precv_frame->hdr.rx_data=%p\n", precv_frame->u.hdr.rx_head, precv_frame->u.hdr.rx_data)); ++ RT_TRACE(_module_recv_osdep_c_,_drv_info_,("precv_frame->hdr.rx_tail=%p precv_frame->u.hdr.rx_end=%p precv_frame->hdr.len=%d \n", precv_frame->u.hdr.rx_tail, precv_frame->u.hdr.rx_end, precv_frame->u.hdr.len)); ++ ++ skb->data = precv_frame->u.hdr.rx_data; ++ ++#ifdef NET_SKBUFF_DATA_USES_OFFSET ++ skb_set_tail_pointer(skb, precv_frame->u.hdr.len); ++#else ++ skb->tail = precv_frame->u.hdr.rx_tail; ++#endif ++ ++ skb->len = precv_frame->u.hdr.len; ++ ++ RT_TRACE(_module_recv_osdep_c_,_drv_info_,("\n skb->head=%p skb->data=%p skb->tail=%p skb->end=%p skb->len=%d\n", skb->head, skb->data, skb->tail, skb->end, skb->len)); ++ ++ if(check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE) ++ { ++ _pkt *pskb2=NULL; ++ struct sta_info *psta = NULL; ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ struct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib; ++ int bmcast = IS_MCAST(pattrib->dst); ++ ++ //DBG_871X("bmcast=%d\n", bmcast); ++ ++ if(_rtw_memcmp(pattrib->dst, myid(&padapter->eeprompriv), ETH_ALEN)==_FALSE) ++ { ++ //DBG_871X("not ap psta=%p, addr=%pM\n", psta, pattrib->dst); ++ ++ if(bmcast) ++ { ++ psta = rtw_get_bcmc_stainfo(padapter); ++ pskb2 = skb_clone(skb, GFP_ATOMIC); ++ } else { ++ psta = rtw_get_stainfo(pstapriv, pattrib->dst); ++ } ++ ++ if(psta) ++ { ++ //DBG_871X("directly forwarding to the rtw_xmit_entry\n"); ++ ++ //skb->ip_summed = CHECKSUM_NONE; ++ //skb->protocol = eth_type_trans(skb, pnetdev); ++ ++ skb->dev = padapter->pnetdev; ++ rtw_xmit_entry(skb, padapter->pnetdev); ++ ++ if(bmcast) ++ skb = pskb2; ++ else ++ goto _recv_indicatepkt_end; ++ } ++ ++ ++ } ++ else// to APself ++ { ++ //DBG_871X("to APSelf\n"); ++ } ++ } ++ ++ ++#ifdef CONFIG_BR_EXT ++ ++#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35)) ++ br_port = padapter->pnetdev->br_port; ++#else // (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35)) ++ rcu_read_lock(); ++ br_port = rcu_dereference(padapter->pnetdev->rx_handler_data); ++ rcu_read_unlock(); ++#endif // (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 35)) ++ ++ if( br_port && (check_fwstate(pmlmepriv, WIFI_STATION_STATE|WIFI_ADHOC_STATE) == _TRUE) ) ++ { ++ int nat25_handle_frame(_adapter *priv, struct sk_buff *skb); ++ if (nat25_handle_frame(padapter, skb) == -1) { ++ //priv->ext_stats.rx_data_drops++; ++ //DEBUG_ERR("RX DROP: nat25_handle_frame fail!\n"); ++ //return FAIL; ++#if 1 ++ // bypass this frame to upper layer!! ++#else ++ goto _recv_indicatepkt_drop; ++#endif ++ } ++ } ++ ++#endif // CONFIG_BR_EXT ++ ++ ++#ifdef CONFIG_TCP_CSUM_OFFLOAD_RX ++ if ( (pattrib->tcpchk_valid == 1) && (pattrib->tcp_chkrpt == 1) ) { ++ skb->ip_summed = CHECKSUM_UNNECESSARY; ++ //DBG_8192C("CHECKSUM_UNNECESSARY \n"); ++ } else { ++ skb->ip_summed = CHECKSUM_NONE; ++ //DBG_8192C("CHECKSUM_NONE(%d, %d) \n", pattrib->tcpchk_valid, pattrib->tcp_chkrpt); ++ } ++#else /* !CONFIG_TCP_CSUM_OFFLOAD_RX */ ++ ++ skb->ip_summed = CHECKSUM_NONE; ++ ++#endif ++ ++ skb->dev = padapter->pnetdev; ++ skb->protocol = eth_type_trans(skb, padapter->pnetdev); ++ ++ netif_rx(skb); ++ ++_recv_indicatepkt_end: ++ ++ precv_frame->u.hdr.pkt = NULL; // pointers to NULL before rtw_free_recvframe() ++ ++ rtw_free_recvframe(precv_frame, pfree_recv_queue); ++ ++ RT_TRACE(_module_recv_osdep_c_,_drv_info_,("\n rtw_recv_indicatepkt :after netif_rx!!!!\n")); ++ ++_func_exit_; ++ ++ return _SUCCESS; ++ ++_recv_indicatepkt_drop: ++ ++ //enqueue back to free_recv_queue ++ if(precv_frame) ++ rtw_free_recvframe(precv_frame, pfree_recv_queue); ++ ++ ++ precvpriv->rx_drop++; ++ ++ return _FAIL; ++ ++_func_exit_; ++ ++} ++ ++void rtw_os_read_port(_adapter *padapter, struct recv_buf *precvbuf) ++{ ++ struct recv_priv *precvpriv = &padapter->recvpriv; ++ ++#ifdef CONFIG_USB_HCI ++ ++ precvbuf->ref_cnt--; ++ ++ //free skb in recv_buf ++ dev_kfree_skb_any(precvbuf->pskb); ++ ++ precvbuf->pskb = NULL; ++ precvbuf->reuse = _FALSE; ++ ++ if(precvbuf->irp_pending == _FALSE) ++ { ++ rtw_read_port(padapter, precvpriv->ff_hwaddr, 0, (unsigned char *)precvbuf); ++ } ++ ++ ++#endif ++#ifdef CONFIG_SDIO_HCI ++ precvbuf->pskb = NULL; ++#endif ++ ++} ++void _rtw_reordering_ctrl_timeout_handler (void *FunctionContext); ++void _rtw_reordering_ctrl_timeout_handler (void *FunctionContext) ++{ ++ struct recv_reorder_ctrl *preorder_ctrl = (struct recv_reorder_ctrl *)FunctionContext; ++ rtw_reordering_ctrl_timeout_handler(preorder_ctrl); ++} ++ ++void rtw_init_recv_timer(struct recv_reorder_ctrl *preorder_ctrl) ++{ ++ _adapter *padapter = preorder_ctrl->padapter; ++ ++ _init_timer(&(preorder_ctrl->reordering_ctrl_timer), padapter->pnetdev, _rtw_reordering_ctrl_timeout_handler, preorder_ctrl); ++ ++} ++ +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/os_dep/linux/rtw_android.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/os_dep/linux/rtw_android.c 2013-07-26 19:36:07.000000000 +0000 +@@ -0,0 +1,713 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++ ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++ ++ ++#if defined(CONFIG_WIFI_CONTROL_FUNC) && 0 ++#include ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35)) ++#include ++#else ++#include ++#endif ++#endif /* CONFIG_WIFI_CONTROL_FUNC */ ++ ++const char *android_wifi_cmd_str[ANDROID_WIFI_CMD_MAX] = { ++ "START", ++ "STOP", ++ "SCAN-ACTIVE", ++ "SCAN-PASSIVE", ++ "RSSI", ++ "LINKSPEED", ++ "RXFILTER-START", ++ "RXFILTER-STOP", ++ "RXFILTER-ADD", ++ "RXFILTER-REMOVE", ++ "BTCOEXSCAN-START", ++ "BTCOEXSCAN-STOP", ++ "BTCOEXMODE", ++ "SETSUSPENDOPT", ++ "P2P_DEV_ADDR", ++ "SETFWPATH", ++ "SETBAND", ++ "GETBAND", ++ "COUNTRY", ++ "P2P_SET_NOA", ++ "P2P_GET_NOA", ++ "P2P_SET_PS", ++ "SET_AP_WPS_P2P_IE", ++#ifdef PNO_SUPPORT ++ "PNOSSIDCLR", ++ "PNOSETUP ", ++ "PNOFORCE", ++ "PNODEBUG", ++#endif ++ ++ "MACADDR", ++ ++ "BLOCK", ++ ++}; ++ ++#ifdef PNO_SUPPORT ++#define PNO_TLV_PREFIX 'S' ++#define PNO_TLV_VERSION '1' ++#define PNO_TLV_SUBVERSION '2' ++#define PNO_TLV_RESERVED '0' ++#define PNO_TLV_TYPE_SSID_IE 'S' ++#define PNO_TLV_TYPE_TIME 'T' ++#define PNO_TLV_FREQ_REPEAT 'R' ++#define PNO_TLV_FREQ_EXPO_MAX 'M' ++ ++typedef struct cmd_tlv { ++ char prefix; ++ char version; ++ char subver; ++ char reserved; ++} cmd_tlv_t; ++#endif /* PNO_SUPPORT */ ++ ++typedef struct android_wifi_priv_cmd { ++ char *buf; ++ int used_len; ++ int total_len; ++} android_wifi_priv_cmd; ++ ++ ++/** ++ * Local (static) functions and variables ++ */ ++ ++/* Initialize g_wifi_on to 1 so dhd_bus_start will be called for the first ++ * time (only) in dhd_open, subsequential wifi on will be handled by ++ * wl_android_wifi_on ++ */ ++static int g_wifi_on = _TRUE; ++ ++ ++#ifdef PNO_SUPPORT ++static int wl_android_set_pno_setup(struct net_device *dev, char *command, int total_len) ++{ ++ wlc_ssid_t ssids_local[MAX_PFN_LIST_COUNT]; ++ int res = -1; ++ int nssid = 0; ++ cmd_tlv_t *cmd_tlv_temp; ++ char *str_ptr; ++ int tlv_size_left; ++ int pno_time = 0; ++ int pno_repeat = 0; ++ int pno_freq_expo_max = 0; ++ ++#ifdef PNO_SET_DEBUG ++ int i; ++ char pno_in_example[] = { ++ 'P', 'N', 'O', 'S', 'E', 'T', 'U', 'P', ' ', ++ 'S', '1', '2', '0', ++ 'S', ++ 0x05, ++ 'd', 'l', 'i', 'n', 'k', ++ 'S', ++ 0x04, ++ 'G', 'O', 'O', 'G', ++ 'T', ++ '0', 'B', ++ 'R', ++ '2', ++ 'M', ++ '2', ++ 0x00 ++ }; ++#endif /* PNO_SET_DEBUG */ ++ ++ DHD_INFO(("%s: command=%s, len=%d\n", __FUNCTION__, command, total_len)); ++ ++ if (total_len < (strlen(CMD_PNOSETUP_SET) + sizeof(cmd_tlv_t))) { ++ DHD_ERROR(("%s argument=%d less min size\n", __FUNCTION__, total_len)); ++ goto exit_proc; ++ } ++ ++#ifdef PNO_SET_DEBUG ++ memcpy(command, pno_in_example, sizeof(pno_in_example)); ++ for (i = 0; i < sizeof(pno_in_example); i++) ++ printf("%02X ", command[i]); ++ printf("\n"); ++ total_len = sizeof(pno_in_example); ++#endif ++ ++ str_ptr = command + strlen(CMD_PNOSETUP_SET); ++ tlv_size_left = total_len - strlen(CMD_PNOSETUP_SET); ++ ++ cmd_tlv_temp = (cmd_tlv_t *)str_ptr; ++ memset(ssids_local, 0, sizeof(ssids_local)); ++ ++ if ((cmd_tlv_temp->prefix == PNO_TLV_PREFIX) && ++ (cmd_tlv_temp->version == PNO_TLV_VERSION) && ++ (cmd_tlv_temp->subver == PNO_TLV_SUBVERSION)) { ++ ++ str_ptr += sizeof(cmd_tlv_t); ++ tlv_size_left -= sizeof(cmd_tlv_t); ++ ++ if ((nssid = wl_iw_parse_ssid_list_tlv(&str_ptr, ssids_local, ++ MAX_PFN_LIST_COUNT, &tlv_size_left)) <= 0) { ++ DHD_ERROR(("SSID is not presented or corrupted ret=%d\n", nssid)); ++ goto exit_proc; ++ } else { ++ if ((str_ptr[0] != PNO_TLV_TYPE_TIME) || (tlv_size_left <= 1)) { ++ DHD_ERROR(("%s scan duration corrupted field size %d\n", ++ __FUNCTION__, tlv_size_left)); ++ goto exit_proc; ++ } ++ str_ptr++; ++ pno_time = simple_strtoul(str_ptr, &str_ptr, 16); ++ DHD_INFO(("%s: pno_time=%d\n", __FUNCTION__, pno_time)); ++ ++ if (str_ptr[0] != 0) { ++ if ((str_ptr[0] != PNO_TLV_FREQ_REPEAT)) { ++ DHD_ERROR(("%s pno repeat : corrupted field\n", ++ __FUNCTION__)); ++ goto exit_proc; ++ } ++ str_ptr++; ++ pno_repeat = simple_strtoul(str_ptr, &str_ptr, 16); ++ DHD_INFO(("%s :got pno_repeat=%d\n", __FUNCTION__, pno_repeat)); ++ if (str_ptr[0] != PNO_TLV_FREQ_EXPO_MAX) { ++ DHD_ERROR(("%s FREQ_EXPO_MAX corrupted field size\n", ++ __FUNCTION__)); ++ goto exit_proc; ++ } ++ str_ptr++; ++ pno_freq_expo_max = simple_strtoul(str_ptr, &str_ptr, 16); ++ DHD_INFO(("%s: pno_freq_expo_max=%d\n", ++ __FUNCTION__, pno_freq_expo_max)); ++ } ++ } ++ } else { ++ DHD_ERROR(("%s get wrong TLV command\n", __FUNCTION__)); ++ goto exit_proc; ++ } ++ ++ res = dhd_dev_pno_set(dev, ssids_local, nssid, pno_time, pno_repeat, pno_freq_expo_max); ++ ++exit_proc: ++ return res; ++} ++#endif /* PNO_SUPPORT */ ++ ++int rtw_android_cmdstr_to_num(char *cmdstr) ++{ ++ int cmd_num; ++ for(cmd_num=0 ; cmd_nummlmepriv); ++ struct wlan_network *pcur_network = &pmlmepriv->cur_network; ++ int bytes_written = 0; ++ ++ if(check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE) { ++ bytes_written += snprintf(&command[bytes_written], total_len, "%s rssi %d", ++ pcur_network->network.Ssid.Ssid, padapter->recvpriv.rssi); ++ } ++ ++ return bytes_written; ++} ++ ++int rtw_android_get_link_speed(struct net_device *net, char *command, int total_len) ++{ ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(net); ++ struct mlme_priv *pmlmepriv = &(padapter->mlmepriv); ++ struct wlan_network *pcur_network = &pmlmepriv->cur_network; ++ int bytes_written = 0; ++ u16 link_speed = 0; ++ ++ link_speed = rtw_get_network_max_rate(padapter, &pcur_network->network); ++ bytes_written = snprintf(command, total_len, "LinkSpeed %d", link_speed); ++ ++ return bytes_written; ++} ++ ++int rtw_android_get_macaddr(struct net_device *net, char *command, int total_len) ++{ ++ _adapter *adapter = (_adapter *)rtw_netdev_priv(net); ++ int bytes_written = 0; ++ ++ bytes_written = snprintf(command, total_len, "Macaddr = "MAC_FMT, MAC_ARG(net->dev_addr)); ++ return bytes_written; ++} ++ ++int rtw_android_set_country(struct net_device *net, char *command, int total_len) ++{ ++ _adapter *adapter = (_adapter *)rtw_netdev_priv(net); ++ char *country_code = command + strlen(android_wifi_cmd_str[ANDROID_WIFI_CMD_COUNTRY]) + 1; ++ int ret; ++ ++ ret = rtw_set_country(adapter, country_code); ++ ++ return (ret==_SUCCESS)?0:-1; ++} ++ ++int rtw_android_get_p2p_dev_addr(struct net_device *net, char *command, int total_len) ++{ ++ int ret; ++ int bytes_written = 0; ++ ++ //We use the same address as our HW MAC address ++ _rtw_memcpy(command, net->dev_addr, ETH_ALEN); ++ ++ bytes_written = ETH_ALEN; ++ return bytes_written; ++} ++ ++int rtw_android_set_block(struct net_device *net, char *command, int total_len) ++{ ++ int ret; ++ _adapter *adapter = (_adapter *)rtw_netdev_priv(net); ++ char *block_value = command + strlen(android_wifi_cmd_str[ANDROID_WIFI_CMD_BLOCK]) + 1; ++ ++ #ifdef CONFIG_IOCTL_CFG80211 ++ wdev_to_priv(adapter->rtw_wdev)->block = (*block_value=='0')?_FALSE:_TRUE; ++ #endif ++ ++ return 0; ++} ++ ++int rtw_android_priv_cmd(struct net_device *net, struct ifreq *ifr, int cmd) ++{ ++ int ret = 0; ++ char *command = NULL; ++ int cmd_num; ++ int bytes_written = 0; ++ android_wifi_priv_cmd priv_cmd; ++ ++ rtw_lock_suspend(); ++ ++ if (!ifr->ifr_data) { ++ ret = -EINVAL; ++ goto exit; ++ } ++ if (copy_from_user(&priv_cmd, ifr->ifr_data, sizeof(android_wifi_priv_cmd))) { ++ ret = -EFAULT; ++ goto exit; ++ } ++ command = kmalloc(priv_cmd.total_len, GFP_KERNEL); ++ if (!command) ++ { ++ DBG_871X("%s: failed to allocate memory\n", __FUNCTION__); ++ ret = -ENOMEM; ++ goto exit; ++ } ++ if (copy_from_user(command, priv_cmd.buf, priv_cmd.total_len)) { ++ ret = -EFAULT; ++ goto exit; ++ } ++ ++ DBG_871X("%s: Android private cmd \"%s\" on %s\n" ++ , __FUNCTION__, command, ifr->ifr_name); ++ ++ cmd_num = rtw_android_cmdstr_to_num(command); ++ ++ switch(cmd_num) { ++ case ANDROID_WIFI_CMD_START: ++ //bytes_written = wl_android_wifi_on(net); ++ goto response; ++ case ANDROID_WIFI_CMD_SETFWPATH: ++ goto response; ++ } ++ ++ if (!g_wifi_on) { ++ DBG_871X("%s: Ignore private cmd \"%s\" - iface %s is down\n" ++ ,__FUNCTION__, command, ifr->ifr_name); ++ ret = 0; ++ goto exit; ++ } ++ ++ switch(cmd_num) { ++ ++ case ANDROID_WIFI_CMD_STOP: ++ //bytes_written = wl_android_wifi_off(net); ++ break; ++ ++ case ANDROID_WIFI_CMD_SCAN_ACTIVE: ++ rtw_set_scan_mode((_adapter *)rtw_netdev_priv(net), SCAN_ACTIVE); ++ break; ++ case ANDROID_WIFI_CMD_SCAN_PASSIVE: ++ rtw_set_scan_mode((_adapter *)rtw_netdev_priv(net), SCAN_PASSIVE); ++ break; ++ ++ case ANDROID_WIFI_CMD_RSSI: ++ bytes_written = rtw_android_get_rssi(net, command, priv_cmd.total_len); ++ break; ++ case ANDROID_WIFI_CMD_LINKSPEED: ++ bytes_written = rtw_android_get_link_speed(net, command, priv_cmd.total_len); ++ break; ++ ++ case ANDROID_WIFI_CMD_MACADDR: ++ bytes_written = rtw_android_get_macaddr(net, command, priv_cmd.total_len); ++ break; ++ ++ case ANDROID_WIFI_CMD_BLOCK: ++ bytes_written = rtw_android_set_block(net, command, priv_cmd.total_len); ++ break; ++ ++ case ANDROID_WIFI_CMD_RXFILTER_START: ++ //bytes_written = net_os_set_packet_filter(net, 1); ++ break; ++ case ANDROID_WIFI_CMD_RXFILTER_STOP: ++ //bytes_written = net_os_set_packet_filter(net, 0); ++ break; ++ case ANDROID_WIFI_CMD_RXFILTER_ADD: ++ //int filter_num = *(command + strlen(CMD_RXFILTER_ADD) + 1) - '0'; ++ //bytes_written = net_os_rxfilter_add_remove(net, TRUE, filter_num); ++ break; ++ case ANDROID_WIFI_CMD_RXFILTER_REMOVE: ++ //int filter_num = *(command + strlen(CMD_RXFILTER_REMOVE) + 1) - '0'; ++ //bytes_written = net_os_rxfilter_add_remove(net, FALSE, filter_num); ++ break; ++ ++ case ANDROID_WIFI_CMD_BTCOEXSCAN_START: ++ /* TBD: BTCOEXSCAN-START */ ++ break; ++ case ANDROID_WIFI_CMD_BTCOEXSCAN_STOP: ++ /* TBD: BTCOEXSCAN-STOP */ ++ break; ++ case ANDROID_WIFI_CMD_BTCOEXMODE: ++ #if 0 ++ uint mode = *(command + strlen(CMD_BTCOEXMODE) + 1) - '0'; ++ if (mode == 1) ++ net_os_set_packet_filter(net, 0); /* DHCP starts */ ++ else ++ net_os_set_packet_filter(net, 1); /* DHCP ends */ ++#ifdef WL_CFG80211 ++ bytes_written = wl_cfg80211_set_btcoex_dhcp(net, command); ++#endif ++ #endif ++ break; ++ ++ case ANDROID_WIFI_CMD_SETSUSPENDOPT: ++ //bytes_written = wl_android_set_suspendopt(net, command, priv_cmd.total_len); ++ break; ++ ++ case ANDROID_WIFI_CMD_SETBAND: ++ //uint band = *(command + strlen(CMD_SETBAND) + 1) - '0'; ++ //bytes_written = wldev_set_band(net, band); ++ break; ++ case ANDROID_WIFI_CMD_GETBAND: ++ //bytes_written = wl_android_get_band(net, command, priv_cmd.total_len); ++ break; ++ ++ case ANDROID_WIFI_CMD_COUNTRY: ++ bytes_written = rtw_android_set_country(net, command, priv_cmd.total_len); ++ break; ++ ++#ifdef PNO_SUPPORT ++ case ANDROID_WIFI_CMD_PNOSSIDCLR_SET: ++ //bytes_written = dhd_dev_pno_reset(net); ++ break; ++ case ANDROID_WIFI_CMD_PNOSETUP_SET: ++ //bytes_written = wl_android_set_pno_setup(net, command, priv_cmd.total_len); ++ break; ++ case ANDROID_WIFI_CMD_PNOENABLE_SET: ++ //uint pfn_enabled = *(command + strlen(CMD_PNOENABLE_SET) + 1) - '0'; ++ //bytes_written = dhd_dev_pno_enable(net, pfn_enabled); ++ break; ++#endif ++ ++ case ANDROID_WIFI_CMD_P2P_DEV_ADDR: ++ bytes_written = rtw_android_get_p2p_dev_addr(net, command, priv_cmd.total_len); ++ break; ++ case ANDROID_WIFI_CMD_P2P_SET_NOA: ++ //int skip = strlen(CMD_P2P_SET_NOA) + 1; ++ //bytes_written = wl_cfg80211_set_p2p_noa(net, command + skip, priv_cmd.total_len - skip); ++ break; ++ case ANDROID_WIFI_CMD_P2P_GET_NOA: ++ //bytes_written = wl_cfg80211_get_p2p_noa(net, command, priv_cmd.total_len); ++ break; ++ case ANDROID_WIFI_CMD_P2P_SET_PS: ++ //int skip = strlen(CMD_P2P_SET_PS) + 1; ++ //bytes_written = wl_cfg80211_set_p2p_ps(net, command + skip, priv_cmd.total_len - skip); ++ break; ++ ++#ifdef CONFIG_IOCTL_CFG80211 ++ case ANDROID_WIFI_CMD_SET_AP_WPS_P2P_IE: ++ { ++ int skip = strlen(android_wifi_cmd_str[ANDROID_WIFI_CMD_SET_AP_WPS_P2P_IE]) + 3; ++ bytes_written = rtw_cfg80211_set_mgnt_wpsp2pie(net, command + skip, priv_cmd.total_len - skip, *(command + skip - 2) - '0'); ++ break; ++ } ++#endif //CONFIG_IOCTL_CFG80211 ++ ++ default: ++ DBG_871X("Unknown PRIVATE command %s - ignored\n", command); ++ snprintf(command, 3, "OK"); ++ bytes_written = strlen("OK"); ++ } ++ ++response: ++ if (bytes_written >= 0) { ++ if ((bytes_written == 0) && (priv_cmd.total_len > 0)) ++ command[0] = '\0'; ++ if (bytes_written >= priv_cmd.total_len) { ++ DBG_871X("%s: bytes_written = %d\n", __FUNCTION__, bytes_written); ++ bytes_written = priv_cmd.total_len; ++ } else { ++ bytes_written++; ++ } ++ priv_cmd.used_len = bytes_written; ++ if (copy_to_user(priv_cmd.buf, command, bytes_written)) { ++ DBG_871X("%s: failed to copy data to user buffer\n", __FUNCTION__); ++ ret = -EFAULT; ++ } ++ } ++ else { ++ ret = bytes_written; ++ } ++ ++exit: ++ rtw_unlock_suspend(); ++ if (command) { ++ kfree(command); ++ } ++ ++ return ret; ++} ++ ++ ++/** ++ * Functions for Android WiFi card detection ++ */ ++#if defined(CONFIG_WIFI_CONTROL_FUNC) && 0 ++ ++static int g_wifidev_registered = 0; ++static struct semaphore wifi_control_sem; ++static struct wifi_platform_data *wifi_control_data = NULL; ++static struct resource *wifi_irqres = NULL; ++ ++static int wifi_add_dev(void); ++static void wifi_del_dev(void); ++ ++int wl_android_wifictrl_func_add(void) ++{ ++ int ret = 0; ++ sema_init(&wifi_control_sem, 0); ++ ++ ret = wifi_add_dev(); ++ if (ret) { ++ DHD_ERROR(("%s: platform_driver_register failed\n", __FUNCTION__)); ++ return ret; ++ } ++ g_wifidev_registered = 1; ++ ++ /* Waiting callback after platform_driver_register is done or exit with error */ ++ if (down_timeout(&wifi_control_sem, msecs_to_jiffies(1000)) != 0) { ++ ret = -EINVAL; ++ DHD_ERROR(("%s: platform_driver_register timeout\n", __FUNCTION__)); ++ } ++ ++ return ret; ++} ++ ++void wl_android_wifictrl_func_del(void) ++{ ++ if (g_wifidev_registered) ++ { ++ wifi_del_dev(); ++ g_wifidev_registered = 0; ++ } ++} ++ ++void *wl_android_prealloc(int section, unsigned long size) ++{ ++ void *alloc_ptr = NULL; ++ if (wifi_control_data && wifi_control_data->mem_prealloc) { ++ alloc_ptr = wifi_control_data->mem_prealloc(section, size); ++ if (alloc_ptr) { ++ DHD_INFO(("success alloc section %d\n", section)); ++ if (size != 0L) ++ bzero(alloc_ptr, size); ++ return alloc_ptr; ++ } ++ } ++ ++ DHD_ERROR(("can't alloc section %d\n", section)); ++ return NULL; ++} ++ ++int wifi_get_irq_number(unsigned long *irq_flags_ptr) ++{ ++ if (wifi_irqres) { ++ *irq_flags_ptr = wifi_irqres->flags & IRQF_TRIGGER_MASK; ++ return (int)wifi_irqres->start; ++ } ++#ifdef CUSTOM_OOB_GPIO_NUM ++ return CUSTOM_OOB_GPIO_NUM; ++#else ++ return -1; ++#endif ++} ++ ++int wifi_set_power(int on, unsigned long msec) ++{ ++ DHD_ERROR(("%s = %d\n", __FUNCTION__, on)); ++ if (wifi_control_data && wifi_control_data->set_power) { ++ wifi_control_data->set_power(on); ++ } ++ if (msec) ++ msleep(msec); ++ return 0; ++} ++ ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35)) ++int wifi_get_mac_addr(unsigned char *buf) ++{ ++ DHD_ERROR(("%s\n", __FUNCTION__)); ++ if (!buf) ++ return -EINVAL; ++ if (wifi_control_data && wifi_control_data->get_mac_addr) { ++ return wifi_control_data->get_mac_addr(buf); ++ } ++ return -EOPNOTSUPP; ++} ++#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35)) */ ++ ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 39)) ++void *wifi_get_country_code(char *ccode) ++{ ++ DHD_TRACE(("%s\n", __FUNCTION__)); ++ if (!ccode) ++ return NULL; ++ if (wifi_control_data && wifi_control_data->get_country_code) { ++ return wifi_control_data->get_country_code(ccode); ++ } ++ return NULL; ++} ++#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 39)) */ ++ ++static int wifi_set_carddetect(int on) ++{ ++ DHD_ERROR(("%s = %d\n", __FUNCTION__, on)); ++ if (wifi_control_data && wifi_control_data->set_carddetect) { ++ wifi_control_data->set_carddetect(on); ++ } ++ return 0; ++} ++ ++static int wifi_probe(struct platform_device *pdev) ++{ ++ struct wifi_platform_data *wifi_ctrl = ++ (struct wifi_platform_data *)(pdev->dev.platform_data); ++ ++ DHD_ERROR(("## %s\n", __FUNCTION__)); ++ wifi_irqres = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "bcmdhd_wlan_irq"); ++ if (wifi_irqres == NULL) ++ wifi_irqres = platform_get_resource_byname(pdev, ++ IORESOURCE_IRQ, "bcm4329_wlan_irq"); ++ wifi_control_data = wifi_ctrl; ++ ++ wifi_set_power(1, 0); /* Power On */ ++ wifi_set_carddetect(1); /* CardDetect (0->1) */ ++ ++ up(&wifi_control_sem); ++ return 0; ++} ++ ++static int wifi_remove(struct platform_device *pdev) ++{ ++ struct wifi_platform_data *wifi_ctrl = ++ (struct wifi_platform_data *)(pdev->dev.platform_data); ++ ++ DHD_ERROR(("## %s\n", __FUNCTION__)); ++ wifi_control_data = wifi_ctrl; ++ ++ wifi_set_power(0, 0); /* Power Off */ ++ wifi_set_carddetect(0); /* CardDetect (1->0) */ ++ ++ up(&wifi_control_sem); ++ return 0; ++} ++ ++static int wifi_suspend(struct platform_device *pdev, pm_message_t state) ++{ ++ DHD_TRACE(("##> %s\n", __FUNCTION__)); ++#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 39)) && defined(OOB_INTR_ONLY) ++ bcmsdh_oob_intr_set(0); ++#endif ++ return 0; ++} ++ ++static int wifi_resume(struct platform_device *pdev) ++{ ++ DHD_TRACE(("##> %s\n", __FUNCTION__)); ++#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 39)) && defined(OOB_INTR_ONLY) ++ if (dhd_os_check_if_up(bcmsdh_get_drvdata())) ++ bcmsdh_oob_intr_set(1); ++#endif ++ return 0; ++} ++ ++static struct platform_driver wifi_device = { ++ .probe = wifi_probe, ++ .remove = wifi_remove, ++ .suspend = wifi_suspend, ++ .resume = wifi_resume, ++ .driver = { ++ .name = "bcmdhd_wlan", ++ } ++}; ++ ++static struct platform_driver wifi_device_legacy = { ++ .probe = wifi_probe, ++ .remove = wifi_remove, ++ .suspend = wifi_suspend, ++ .resume = wifi_resume, ++ .driver = { ++ .name = "bcm4329_wlan", ++ } ++}; ++ ++static int wifi_add_dev(void) ++{ ++ DHD_TRACE(("## Calling platform_driver_register\n")); ++ platform_driver_register(&wifi_device); ++ platform_driver_register(&wifi_device_legacy); ++ return 0; ++} ++ ++static void wifi_del_dev(void) ++{ ++ DHD_TRACE(("## Unregister platform_driver_register\n")); ++ platform_driver_unregister(&wifi_device); ++ platform_driver_unregister(&wifi_device_legacy); ++} ++#endif /* defined(CONFIG_WIFI_CONTROL_FUNC) */ ++ +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/os_dep/linux/sdio_intf.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/os_dep/linux/sdio_intf.c 2013-07-26 19:36:07.000000000 +0000 +@@ -0,0 +1,922 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ++******************************************************************************/ ++#define _HCI_INTF_C_ ++ ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++extern u32 rtw_start_drv_threads(_adapter *padapter); ++extern void rtw_stop_drv_threads (_adapter *padapter); ++extern u8 rtw_init_drv_sw(_adapter *padapter); ++extern u8 rtw_free_drv_sw(_adapter *padapter); ++extern void rtw_cancel_all_timer(_adapter *padapter); ++extern struct net_device *rtw_init_netdev(_adapter *old_padapter); ++extern void update_recvframe_attrib_from_recvstat(struct rx_pkt_attrib ++*pattrib, struct recv_stat *prxstat); ++static const struct sdio_device_id sdio_ids[] = { ++ { SDIO_DEVICE(0x024c, 0x8712) }, ++// { SDIO_DEVICE_CLASS(SDIO_CLASS_WLAN) }, ++// { /* end: all zeroes */ }, ++}; ++ ++typedef struct _driver_priv{ ++ struct sdio_driver r871xs_drv; ++}drv_priv, *pdrv_priv; ++ ++void sd_sync_int_hdl(struct sdio_func *func); ++ ++extern unsigned int sd_dvobj_init(_adapter * padapter){ ++ ++ struct dvobj_priv *psddev=&padapter->dvobjpriv; ++ struct sdio_func *func=psddev->func; ++ int ret; ++ _func_enter_; ++ //_rtw_init_sema(&psddev->init_finish,0); ++ sdio_claim_host(func); ++ ret=sdio_enable_func(func); ++ if(ret){ ++ RT_TRACE(_module_hci_intfs_c_,_drv_err_,("sd_dvobj_init: sdio_enable_func fail!!!!!\n")); ++ return _FAIL; ++ } ++ RT_TRACE(_module_hci_intfs_c_,_drv_err_,("sd_dvobj_init: sdio_enable_func success!!!!!\n")); ++ padapter->EepromAddressSize = 6; ++ psddev->tx_block_mode=1; ++ psddev->rx_block_mode=1; ++ sdio_set_block_size(func, 512); ++ psddev->block_transfer_len=512; ++ psddev->blk_shiftbits=9; ++ ret=sdio_claim_irq(func,sd_sync_int_hdl); ++ sdio_release_host(func); ++ psddev->sdio_himr=0xff; ++ if(ret) ++ return _FAIL; ++ _func_exit_; ++ return _SUCCESS; ++} ++ ++extern void sd_dvobj_deinit(_adapter * padapter) ++{ ++ unsigned char data; ++ struct dvobj_priv *psddev=&padapter->dvobjpriv; ++ struct sdio_func *func=psddev->func; ++ ++ RT_TRACE(_module_hci_intfs_c_,_drv_err_,("+SDIO deinit\n")); ++ if(func !=0){ ++ sdio_claim_host(func); ++ RT_TRACE(_module_hci_intfs_c_,_drv_err_,(" in sd_dvobj_deinit():sdio_claim_host !\n")); ++// sdio_release_irq(func); ++ RT_TRACE(_module_hci_intfs_c_,_drv_err_,(" in sd_dvobj_deinit():sdio_release_irq !\n")); ++ sdio_disable_func(func); ++ RT_TRACE(_module_hci_intfs_c_,_drv_err_,(" in sd_dvobj_deinit():sdio_disable_func !\n")); ++ sdio_release_host(func); ++ RT_TRACE(_module_hci_intfs_c_,_drv_err_,(" in sd_dvobj_deinit():sdio_release_host !\n")); ++ ++ ++ } ++ return; ++} ++ ++uint sdbus_read_reg_int(struct intf_priv *pintfpriv, u32 addr, u32 cnt, void *pdata) ++{ ++ struct dvobj_priv *pdvobjpriv = (struct dvobj_priv*)pintfpriv->intf_dev; ++ struct sdio_func *func = pdvobjpriv->func; ++ u8 *mem = NULL; ++ int status; ++ ++#ifdef CONFIG_IO_4B ++ u32 addr_org = addr, addr_offset = 0; ++ u32 cnt_org = cnt; ++#endif ++ ++_func_enter_; ++ ++#ifdef CONFIG_IO_4B ++ addr_offset = addr % 4; ++ if (addr_offset) { ++ addr = addr - addr_offset; ++ cnt = cnt + addr_offset; ++ } ++ if (cnt % 4) ++ cnt = ((cnt + 4) >> 2) << 2; ++#endif ++ ++ mem = rtw_malloc(cnt); ++ if (mem == NULL) { ++ RT_TRACE(_module_hci_ops_os_c_, _drv_emerg_, ++ ("SDIO_STATUS_NO_RESOURCES - memory alloc fail\n")); ++ return _FAIL; ++ } ++ ++ status = sdio_memcpy_fromio(func, mem, addr&0x1FFFF, cnt); ++ if (status) { ++ //error ++ RT_TRACE(_module_hci_ops_os_c_, _drv_emerg_, ++ ("sdbus_read_reg_int error 0x%x\n" ++ "***** Addr = %x *****\n" ++ "***** Length = %d *****\n", status, addr, cnt)); ++ status = _FAIL; ++ } else { ++#ifdef CONFIG_IO_4B ++ if (cnt != cnt_org) ++ _rtw_memcpy(pdata, mem + addr_offset, cnt_org); ++ else ++#endif ++ _rtw_memcpy(pdata, mem, cnt); ++ status = _SUCCESS; ++ } ++ ++ rtw_mfree(mem, cnt); ++ ++_func_exit_; ++ ++ return status; ++} ++ ++void sdio_read_int(_adapter *padapter, u32 addr, u8 sz, void *pdata) ++{ ++ struct io_queue *pio_queue = (struct io_queue*)padapter->pio_queue; ++ struct intf_hdl *pintfhdl = &pio_queue->intf; ++ struct intf_priv *pintfpriv = pintfhdl->pintfpriv; ++ u32 ftaddr = 0, res; ++ ++_func_enter_; ++ ++// RT_TRACE(_module_hci_ops_c_,_drv_err_,("sdio_read_int\n")); ++ ++ if ((_cvrt2ftaddr(addr, &ftaddr)) == _SUCCESS) { ++ res = sdbus_read_reg_int(pintfpriv, ftaddr, sz, pdata); ++ if (res != _SUCCESS) { ++ RT_TRACE(_module_hci_ops_c_, _drv_emerg_, ("sdio_read_int fail!!!\n")); ++ } ++ } else { ++ RT_TRACE(_module_hci_ops_c_, _drv_emerg_, (" sdio_read_int address translate error!!!\n")); ++ } ++ ++_func_exit_; ++} ++ ++uint sdbus_write_reg_int(struct intf_priv *pintfpriv, u32 addr, u32 cnt, void *pdata) ++{ ++ struct dvobj_priv *pdvobjpriv = (struct dvobj_priv*)pintfpriv->intf_dev; ++ struct sdio_func *func = pdvobjpriv->func; ++ int status; ++#ifdef CONFIG_IO_4B ++ u32 addr_org = addr, addr_offset = 0; ++ u32 cnt_org = cnt; ++ void *pdata_org = pdata; ++#endif ++ ++_func_enter_; ++ ++#ifdef CONFIG_IO_4B ++ addr_offset = addr % 4; ++ if (addr_offset) { ++ addr = addr - addr_offset; ++ cnt = cnt + addr_offset; ++ } ++ if (cnt % 4) ++ cnt = ((cnt + 4) >> 2) << 2; ++ if (cnt != cnt_org) { ++ pdata = rtw_malloc(cnt); ++ if (pdata == NULL) { ++ RT_TRACE(_module_hci_ops_os_c_, _drv_emerg_, ++ ("SDIO_STATUS_NO_RESOURCES - rtw_malloc fail\n")); ++ return _FAIL; ++ } ++ status = sdio_memcpy_fromio(func, pdata, addr&0x1FFFF, cnt); ++ if (status) { ++ RT_TRACE(_module_hci_ops_os_c_,_drv_emerg_, ++ ("sdbus_write_reg_int read failed 0x%x\n " ++ "***** Addr = %x *****\n" ++ "***** Length = %d *****\n", status, addr, cnt)); ++ rtw_mfree(pdata, cnt); ++ return _FAIL; ++ } ++ _rtw_memcpy(pdata + addr_offset, pdata_org, cnt_org); ++ /* if data been modify between this read and write, may cause a problem */ ++ } ++#endif ++ status = sdio_memcpy_toio(func, addr&0x1FFFF, pdata, cnt); ++ if (status) { ++ //error ++ RT_TRACE(_module_hci_ops_os_c_, _drv_emerg_, ++ ("sdbus_write_reg_int failed 0x%x\n" ++ "***** Addr = %x *****\n" ++ "***** Length = %d *****\n", status, addr, cnt)); ++ ++ status = _FAIL; ++ } else ++ status = _SUCCESS; ++ ++#ifdef CONFIG_IO_4B ++ if (cnt != cnt_org) ++ rtw_mfree(pdata, cnt); ++#endif ++ ++_func_exit_; ++ ++ return status; ++} ++ ++void sdio_write_int(_adapter *padapter, u32 addr, u32 val, u8 sz) ++{ ++ struct io_queue *pio_queue = (struct io_queue*)padapter->pio_queue; ++ struct intf_hdl *pintfhdl = &pio_queue->intf; ++ struct intf_priv *pintfpriv = pintfhdl->pintfpriv; ++ ++ u32 ftaddr = 0, res; ++ ++_func_enter_; ++ ++// RT_TRACE(_module_hci_ops_c_,_drv_err_,("sdio_write_int\n")); ++ ++ val = cpu_to_le32(val); ++ ++ if ((_cvrt2ftaddr(addr, &ftaddr)) == _SUCCESS) { ++ res = sdbus_write_reg_int(pintfpriv, ftaddr, sz, &val); ++ if (res != _SUCCESS) { ++ RT_TRACE(_module_hci_ops_c_, _drv_emerg_, ("sdio_write_int fail!!!\n")); ++ } ++ } else { ++ RT_TRACE(_module_hci_ops_c_, _drv_emerg_, ("sdio_write_int address translate error!!!\n")); ++ } ++ ++_func_exit_; ++} ++ ++int recvbuf2recvframe_s(_adapter *padapter, struct recv_buf *precvbuf) ++{ ++// _irqL irql; ++ u8 *pbuf; ++// u8 bsumbit = _FALSE; ++ uint pkt_len, pkt_offset; ++ int transfer_len; ++ struct recv_stat *prxstat; ++ u16 pkt_cnt, drvinfo_sz; ++ _queue *pfree_recv_queue; ++ union recv_frame *precvframe = NULL,*plast_recvframe = NULL; ++ struct recv_priv *precvpriv = &padapter->recvpriv; ++// struct intf_hdl *pintfhdl = &padapter->pio_queue->intf; ++ ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("+recvbuf2recvframe()\n")); ++ ++ pfree_recv_queue = &(precvpriv->free_recv_queue); ++ ++ pbuf = (u8*)precvbuf->pbuf; ++ ++ prxstat = (struct recv_stat *)pbuf; ++/* { ++ u8 i; ++ DBG_8192C("\n-----recvbuf-----\n"); ++ for (i=0;i<64;i=i+8) { ++ DBG_8192C("0x%.2x:0x%.2x:0x%.2x:0x%.2x:0x%.2x:0x%.2x:0x%.2x:0x%.2x\n",pbuf[i],pbuf[i+1],pbuf[i+2],pbuf[i+3],pbuf[i+4],pbuf[i+5],pbuf[i+6],pbuf[i+7]); ++ } ++ DBG_8192C("\n-----recvbuf end-----\n"); ++ }*/ ++ transfer_len = precvbuf->len; ++ precvbuf->ref_cnt = 1; ++ do { ++ precvframe = NULL; ++ precvframe = rtw_alloc_recvframe(pfree_recv_queue); ++ if (precvframe == NULL){ ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_err_,("recvbuf2recvframe(), precvframe==NULL\n")); ++ break; ++ } ++ if (plast_recvframe != NULL) { ++ if (rtw_recv_entry(plast_recvframe) != _SUCCESS) { ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("recvbuf2recvframe(), rtw_recv_entry(precvframe) != _SUCCESS\n")); ++ } ++ } ++ prxstat = (struct recv_stat*)pbuf; ++ pkt_len = le32_to_cpu(prxstat->rxdw0&0x00003fff); //pkt_len = prxstat->frame_length; ++ ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("rxdesc: offsset0:0x%08x, offsset4:0x%08x, offsset8:0x%08x, offssetc:0x%08x\n",prxstat->rxdw0, prxstat->rxdw1, prxstat->rxdw2, prxstat->rxdw4)); ++ ++ drvinfo_sz = le16_to_cpu((prxstat->rxdw0&0x000f0000)>>16);//uint 2^3 = 8 bytes ++ drvinfo_sz = drvinfo_sz << 3; ++ RT_TRACE(_module_rtl871x_recv_c_, _drv_info_, ("pkt_len=%d[0x%x] drvinfo_sz=%d[0x%x]\n", pkt_len, pkt_len, drvinfo_sz, drvinfo_sz)); ++ precvframe->u.hdr.precvbuf = precvbuf; ++ precvframe->u.hdr.adapter = padapter; ++ rtw_init_recvframe(precvframe, precvpriv); ++ ++ precvframe->u.hdr.rx_head = precvframe->u.hdr.rx_data = precvframe->u.hdr.rx_tail = pbuf; ++ precvframe->u.hdr.rx_end = precvbuf->pend; ++ update_recvframe_attrib_from_recvstat(&precvframe->u.hdr.attrib, prxstat); ++ pkt_offset = pkt_len + drvinfo_sz + RXDESC_SIZE; ++ ++ recvframe_put(precvframe, pkt_len + drvinfo_sz + RXDESC_SIZE); ++ recvframe_pull(precvframe, drvinfo_sz + RXDESC_SIZE); ++/* { ++ u8 i; ++ DBG_8192C("\n-----packet-----\n"); ++ for(i=0;i<32;i++){ ++ DBG_8192C("0x%.2x:0x%.2x:0x%.2x:0x%.2x:0x%.2x:0x%.2x:0x%.2x:0x%.2x\n",precvframe->u.hdr.rx_data[i],precvframe->u.hdr.rx_data[i+1],precvframe->u.hdr.rx_data[i+2],precvframe->u.hdr.rx_data[i+3],precvframe->u.hdr.rx_data[i+4],precvframe->u.hdr.rx_data[i+5],precvframe->u.hdr.rx_data[i+6],precvframe->u.hdr.rx_data[i+7]); ++ } ++ DBG_8192C("\n-----packet end-----\n"); ++ }*/ ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("\n precvframe->u.hdr.rx_head=%p precvframe->u.hdr.rx_data=%p precvframe->u.hdr.rx_tail=%p precvframe->u.hdr.rx_end=%p\n",precvframe->u.hdr.rx_head,precvframe->u.hdr.rx_data,precvframe->u.hdr.rx_tail,precvframe->u.hdr.rx_end)); ++ ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("\npkt_offset=%d [1]\n",pkt_offset)); ++ pkt_offset = _RND512(pkt_offset); ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("\npkt_offset=%d [2] transfer_len=%d\n",pkt_offset,transfer_len)); ++ transfer_len -= pkt_offset; ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("\n transfer_len=%d \n",transfer_len)); ++ pbuf += pkt_offset; ++ if (transfer_len > 0) ++ precvbuf->ref_cnt++; ++ plast_recvframe = precvframe; ++ precvframe = NULL; ++ } while (transfer_len > 0); ++ ++ if (plast_recvframe != NULL) { ++ if (rtw_recv_entry(plast_recvframe) != _SUCCESS) { ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("recvbuf2recvframe(), rtw_recv_entry(precvframe) != _SUCCESS\n")); ++ } ++ } ++ ++ dev_kfree_skb_any(precvbuf->pskb); ++ precvbuf->pskb = NULL; ++ return _SUCCESS; ++} ++ ++u32 read_pkt2recvbuf(PADAPTER padapter, u32 rd_cnt, struct recv_buf *precvbuf) ++{ ++ struct recv_priv *precvpriv = &padapter->recvpriv; ++ u32 skb_buf_sz; ++ if (rd_cnt < 1600) ++ skb_buf_sz = 1600; ++ else ++ skb_buf_sz = rd_cnt; ++ RT_TRACE(_module_rtl871x_recv_c_,_drv_info_,("\n read_pkt2recvbuf------skb_buf_sz=%d rd_cnt=%d\n",skb_buf_sz,rd_cnt)); ++// if (precvbuf->pskb != NULL) { ++// dev_kfree_skb_any(precvbuf->pskb ); ++// } ++ ++ //alloc skb ++ { ++#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,18)) // http://www.mail-archive.com/netdev@vger.kernel.org/msg17214.html ++ precvbuf->pskb = dev_alloc_skb(skb_buf_sz); ++#else ++ precvbuf->pskb = netdev_alloc_skb(padapter->pnetdev, skb_buf_sz); ++#endif ++ if (precvbuf->pskb == NULL) { ++ RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("==================init_recvbuf(): alloc_skb fail!\n")); ++ return _FAIL; ++ } ++ ++ precvbuf->phead = precvbuf->pskb->head; ++ precvbuf->pdata = precvbuf->pskb->data; ++ precvbuf->ptail = precvbuf->pskb->tail; ++ precvbuf->pend = precvbuf->pskb->end; ++ precvbuf->pbuf = precvbuf->pskb->data; ++ } ++// else { ++// RT_TRACE(_module_hci_ops_os_c_,_drv_err_,("after init_recvbuf(): skb !=NULL!\n")); ++// } ++ ++ rtw_read_port(padapter, RTL8712_DMA_RX0FF, rd_cnt, (u8*)precvbuf); ++ precvbuf->ptail = precvbuf->ptail + rd_cnt; ++ precvbuf->len = rd_cnt; ++ /*{ ++ u32 i; ++ DBG_8192C("-----After read port[%d]-----\n",skb_buf_sz); ++ for (i = 0; i < skb_buf_sz; i = i + 8) { ++ DBG_8192C("0x%x:0x%x:0x%x:0x%x:0x%x:0x%x:0x%x:0x%x\n",precvbuf->pbuf[i],precvbuf->pbuf[i+1],precvbuf->pbuf[i+2],precvbuf->pbuf[i+3],precvbuf->pbuf[i+4],precvbuf->pbuf[i+5],precvbuf->pbuf[i+6],precvbuf->pbuf[i+7]); ++ } ++ ++ DBG_8192C("-----------\n"); ++ }*/ ++#if 1 ++ recvbuf2recvframe_s(padapter, precvbuf); ++#else ++{ ++ dev_kfree_skb_any(precvbuf->pskb); ++ precvbuf->pskb = NULL; ++ rtw_list_delete(&(precvbuf->list)); ++ rtw_list_insert_tail(&precvbuf->list, get_list_head(&precvpriv->free_recv_buf_queue)); ++ precvpriv->free_recv_buf_queue_cnt++; ++} ++#endif ++ ++ return _SUCCESS; ++} ++ ++void sd_recv_rxfifo(PADAPTER padapter); ++#if 0 ++void sd_recv_rxfifo(PADAPTER padapter) ++{ ++// u8 *pdata, *ptail, *pfixed_tail,*pfixed_head,*pfixed_end,blk_shift_bit; ++ u16 rx_blknum; ++ u32 blk_sz, cnt;//,remain,tmp_cnt; ++ struct recv_priv *precvpriv; ++// struct recv_stat *prxstat; ++ //union recv_frame *precvframe, *ppreframe = NULL; ++// _queue *pfree_recv_queue, *ppending_recv_queue; ++// u8 tmp[2048]; ++ struct recv_buf *precvbuf; ++ _list *precvbuf_head, *precvbuf_list; ++ _irqL irql, rx_proc_irq; ++// uint pkt_len; ++// u16 drvinfo_sz; ++ ++ precvpriv = &padapter->recvpriv; ++ blk_sz = padapter->dvobjpriv.block_transfer_len; ++// blk_shift_bit= (u8)padapter->dvobjpriv.blk_shiftbits; ++// pfree_recv_queue = &(precvpriv->free_recv_queue); ++// ppending_recv_queue = &(precvpriv->recv_pending_queue); ++ ++ rx_blknum = padapter->dvobjpriv.rxblknum; ++// _enter_hwio_critical(&padapter->dvobjpriv.rx_protect, &rx_proc_irq); ++// padapter->dvobjpriv.rxblknum=rtw_read16(padapter, SDIO_RX0_RDYBLK_NUM); ++ sdio_read_int(padapter, SDIO_RX0_RDYBLK_NUM, 2, &padapter->dvobjpriv.rxblknum); ++ if (rx_blknum>padapter->dvobjpriv.rxblknum) { ++ cnt = (0x10000 - rx_blknum + padapter->dvobjpriv.rxblknum) * blk_sz; ++ } else { ++ cnt = (padapter->dvobjpriv.rxblknum-rx_blknum) * blk_sz; ++ } ++ RT_TRACE(_module_hci_intfs_c_,_drv_notice_,("=====================sd_recv_rxfifo padapter->dvobjpriv.rxblknum=%x Blk_Num = %x cnt=%d",padapter->dvobjpriv.rxblknum, rx_blknum,cnt)); ++ ++ if (cnt == 0) { ++// remain = 0; ++ precvbuf = NULL; ++ RT_TRACE(_module_hci_intfs_c_,_drv_info_,("---===============sd_recv_rxfifo padapter->dvobjpriv.rxblknum=0x%x padapter->dvobjpriv.rxblknum_rd=0x%x", padapter->dvobjpriv.rxblknum,padapter->dvobjpriv.rxblknum_rd)); ++ goto drop_pkt; ++ } ++ ++ if(_rtw_queue_empty(&precvpriv->free_recv_buf_queue) == _TRUE) ++ { ++ precvbuf = NULL; ++ RT_TRACE(_module_hci_intfs_c_,_drv_emerg_,("\n sd_recv_rxfifo : precvbuf= NULL precvpriv->free_recv_buf_queue_cnt=%d \n",precvpriv->free_recv_buf_queue_cnt)); ++ goto drop_pkt; ++ } ++ else ++ { ++ _enter_critical(&precvpriv->free_recv_buf_queue.lock, &irql); ++ precvbuf_head = get_list_head(&precvpriv->free_recv_buf_queue); ++ precvbuf_list = get_next(precvbuf_head); ++ precvbuf = LIST_CONTAINOR(precvbuf_list, struct recv_buf, list); ++ rtw_list_delete(&precvbuf->list); ++ precvpriv->free_recv_buf_queue_cnt--; ++ ++ RT_TRACE(_module_hci_intfs_c_,_drv_notice_,("\n sd_recv_rxfifo : precvbuf= 0x%p dequeue: free_recv_buf_queue_cnt=%d\n",precvbuf,precvpriv->free_recv_buf_queue_cnt)); ++ _exit_critical(&precvpriv->free_recv_buf_queue.lock, &irql); ++ } ++ read_pkt2recvbuf(padapter, cnt, precvbuf); ++ ++ return; ++ ++drop_pkt: ++ ++ if (cnt >0) { ++ do{ ++ if (cnt > MAX_RECVBUF_SZ) { ++ rtw_read_port(padapter, 0x10380000, MAX_RECVBUF_SZ, (u8 *)precvpriv->recvbuf_drop); ++ RT_TRACE(_module_hci_intfs_c_,_drv_notice_,("=========sd_recv_rxfifo precvbuf= NULL no recvbuf cnt=%d tmp read %d",cnt,MAX_RECVBUF_SZ)); ++ cnt=cnt-MAX_RECVBUF_SZ; ++ } else { ++ rtw_read_port(padapter, 0x10380000, cnt, (u8 *)precvpriv->recvbuf_drop); ++ RT_TRACE(_module_hci_intfs_c_,_drv_notice_,("=========sd_recv_rxfifo precvbuf= NULL no recvbuf cnt=%d tmp read(@) %d",cnt,cnt)); ++ cnt=0; ++ } ++ } while(cnt > 0); ++ } ++ ++ return; ++} ++#endif ++#if 0 ++void sd_c2h_hdl(PADAPTER padapter) ++{ ++ u8 cmd_seq, pkt_num = 0; ++ u16 tmp16, sz, cmd_len = 0; ++ u32 rd_sz=0, cmd_sz = 0;//,ptr; ++ struct evt_priv *pevtpriv = &padapter->evtpriv; ++ pkt_num = rtw_read8(padapter, 0x102500BF); ++// RT_TRACE(_module_hci_intfs_c_, _drv_err_, ("@ sd_c2h_hdl:pkt_num=%d",pkt_num)); ++get_next: ++// ptr=rtw_read32(padapter,0x102500e8); ++// RT_TRACE(_module_hci_intfs_c_, _drv_err_, ("@ sd_c2h_hdl:C2H fifo RDPTR=0x%x",ptr)); ++// ptr=rtw_read32(padapter,0x102500ec); ++// RT_TRACE(_module_hci_intfs_c_, _drv_err_, ("@ sd_c2h_hdl:C2H fifo WTPTR=0x%x",ptr)); ++// if(pkt_num==0x0 ){ ++// RT_TRACE(_module_hci_intfs_c_, _drv_err_, ("@ sd_c2h_hdl:cmd_pkt num=0x%x!",pkt_num)); ++// return; ++// } ++ RT_TRACE(_module_hci_intfs_c_, _drv_err_, ("@ sd_c2h_hdl:pkt_num=%d",pkt_num)); ++ //memset(pevtpriv->c2h_mem,0,512); ++ rtw_read_port(padapter, RTL8712_DMA_C2HCMD, 512, pevtpriv->c2h_mem); ++ cmd_sz = *(u16 *)&pevtpriv->c2h_mem[0]; ++ cmd_sz &= 0x3fff; ++ RT_TRACE(_module_hci_intfs_c_, _drv_err_, ("sd_c2h_hdl: cmd_sz=%d[0x%x]!",cmd_sz,cmd_sz)); ++ tmp16 = *(u16 *)&pevtpriv->c2h_mem[4]; ++ tmp16 &= 0x01ff; ++ if (tmp16 !=0x1ff) { ++ RT_TRACE(_module_hci_intfs_c_, _drv_err_, ("sd_c2h_hdl: 0x1ff error[0x%x]!",pevtpriv->c2h_mem[4])); ++ goto exit; ++ } ++ if((cmd_sz+24) >512){ ++ rtw_read_port(padapter, RTL8712_DMA_C2HCMD, (cmd_sz+24-512), pevtpriv->c2h_mem+512); ++ RT_TRACE(_module_hci_intfs_c_, _drv_err_, ("sd_c2h_hdl: read the second part of c2h event!")); ++ } ++ cmd_seq = pevtpriv->c2h_mem[27]; ++ cmd_seq &= 0x7f; ++ if (pevtpriv->event_seq != cmd_seq) { ++ RT_TRACE(_module_hci_intfs_c_, _drv_err_, ("sd_c2h_hdl: pevtpriv->event_seq (%d) != c2hbuf seq(%d)",pevtpriv->event_seq,cmd_seq)); ++ } else { ++ RT_TRACE(_module_hci_intfs_c_, _drv_notice_, ("sd_c2h_hdl: pevtpriv->event_seq (%d) == c2hbuf seq(%d)",pevtpriv->event_seq,cmd_seq)); ++ } ++ cmd_len = *(u16 *)&pevtpriv->c2h_mem[0]; ++ cmd_len &= 0x3ff; ++ RT_TRACE(_module_hci_intfs_c_, _drv_err_, ("@sd_c2h_hdl: cmd_len=%d",cmd_len)); ++// if(cmd_len){ ++// memset(pevtpriv->c2h_mem+cmd_len,0,cmd_len); ++// rtw_read_port(padapter, RTL8712_DMA_C2HCMD, cmd_len, pevtpriv->c2h_mem+cmd_len); ++// } ++// pevtpriv->event_seq=pevtpriv->event_seq++; ++// if(pevtpriv->event_seq>127) ++// pevtpriv->event_seq=0; ++ ++ RT_TRACE(_module_hci_intfs_c_, _drv_err_, ("sd_c2h_hdl:!")); ++ rxcmd_event_hdl(padapter,pevtpriv->c2h_mem); ++ if (pkt_num > 1) { ++ pkt_num--; ++ RT_TRACE(_module_hci_intfs_c_, _drv_err_, ("sd_c2h_hdl: pkt_num=%d",pkt_num)); ++ goto get_next; ++ } ++ ++exit: ++ ++ return; ++} ++#endif ++void update_free_ffsz_int(_adapter *padapter ) ++{ ++ struct xmit_priv *pxmitpriv=&padapter->xmitpriv; ++ RT_TRACE(_module_hci_ops_c_,_drv_err_,("\n====(before)=padapter->xmitpriv.public_pgsz=0x%x====update_free_ffsz: free_pg=0x%x:0x%x:0x%x:0x%x:0x%x:0x%x:0x%x:0x%x \n", ++ padapter->xmitpriv.public_pgsz, ++ pxmitpriv->free_pg[0],pxmitpriv->free_pg[1],pxmitpriv->free_pg[2],pxmitpriv->free_pg[3], ++ pxmitpriv->free_pg[4],pxmitpriv->free_pg[5],pxmitpriv->free_pg[6],pxmitpriv->free_pg[7])); ++// rtw_read_mem(padapter,SDIO_BCNQ_FREEPG,8,pxmitpriv->free_pg); ++ sdio_read_int(padapter, SDIO_BCNQ_FREEPG, 8, pxmitpriv->free_pg); ++ padapter->xmitpriv.public_pgsz = pxmitpriv->free_pg[0]; ++ if (pxmitpriv->public_pgsz > pxmitpriv->init_pgsz) { ++ pxmitpriv->init_pgsz = pxmitpriv->public_pgsz; ++ } ++ ++ { ++ u8 diff; ++ if (pxmitpriv->public_pgsz > (pxmitpriv->init_pgsz - pxmitpriv->used_pgsz)) { ++ RT_TRACE(_module_hci_ops_c_,_drv_err_,("\n====(0)=====update_free_ffsz: pxmitpriv->public_pgsz=0x%x pxmitpriv->init_pgsz=0x%x pxmitpriv->used_pgsz=0x%x \n",pxmitpriv->public_pgsz ,pxmitpriv->init_pgsz, pxmitpriv->used_pgsz)); ++ diff = pxmitpriv->public_pgsz - (pxmitpriv->init_pgsz - pxmitpriv->used_pgsz); ++ pxmitpriv->used_pgsz = pxmitpriv->used_pgsz - diff; ++// pxmitpriv->required_pgsz = pxmitpriv->required_pgsz - diff; ++ RT_TRACE(_module_hci_ops_c_,_drv_err_,("\n====(1)=====update_free_ffsz: pxmitpriv->public_pgsz =0x%x diff=0x%x pxmitpriv->used_pgsz=0x%x pxmitpriv->required_pgsz=0x%x\n",pxmitpriv->public_pgsz,diff,pxmitpriv->used_pgsz,pxmitpriv->required_pgsz) ); ++ } else { ++ ++ } ++ } ++ ++ RT_TRACE(_module_hci_ops_c_,_drv_err_,("\n====(after)=====update_free_ffsz: free_pg=0x%x:0x%x:0x%x:0x%x:0x%x:0x%x:0x%x:0x%x \n", ++ pxmitpriv->free_pg[0],pxmitpriv->free_pg[1],pxmitpriv->free_pg[2],pxmitpriv->free_pg[3], ++ pxmitpriv->free_pg[4],pxmitpriv->free_pg[5],pxmitpriv->free_pg[6],pxmitpriv->free_pg[7])); ++ ++ return; ++} ++ ++void sd_int_dpc(PADAPTER padapter); ++#if 0 ++void sd_int_dpc(PADAPTER padapter) ++{ ++ uint tasks= (padapter->IsrContent /*& padapter->ImrContent*/); ++// rtw_write16(padapter,SDIO_HIMR,0); ++ ++ RT_TRACE(_module_hci_intfs_c_,_drv_notice_,(" sd_int_dpc[0x%x] ",padapter->IsrContent)); ++ ++ if ((tasks & _VOQ_AVAL_IND) || (tasks & _VIQ_AVAL_IND) || (tasks & _BEQ_AVAL_IND) || (tasks & _BKQ_AVAL_IND) || (tasks & _BMCQ_AVAL_IND)) { ++ RT_TRACE(_module_hci_intfs_c_,_drv_notice_,("==============INT : _TXDONE")); ++ update_free_ffsz_int(padapter); ++ } else { ++ if (((padapter->xmitpriv.init_pgsz - padapter->xmitpriv.used_pgsz) > 0 && (padapter->xmitpriv.init_pgsz - padapter->xmitpriv.used_pgsz) < 0x2f) || padapter->xmitpriv.required_pgsz > 0) { ++ RT_TRACE(_module_hci_intfs_c_,_drv_notice_,("==============padapter->xmitpriv.public_pgsz[0x%x] <30 ",padapter->xmitpriv.public_pgsz)); ++ update_free_ffsz_int(padapter); ++ } ++ } ++ ++ if(tasks & _C2HCMD) ++ { ++// RT_TRACE(_module_hci_intfs_c_,_drv_err_,("======C2H_CMD========")); ++ padapter->IsrContent ^= _C2HCMD; ++ sd_c2h_hdl(padapter); ++// RT_TRACE(_module_hci_intfs_c_,_drv_err_,("======C2H_CMD[end]========")); ++ } ++ ++ if(tasks & _RXDONE) ++ { ++ RT_TRACE(_module_hci_intfs_c_,_drv_notice_,("==============INT : _RXDONE")); ++ padapter->IsrContent ^= _RXDONE; ++ sd_recv_rxfifo(padapter); ++ } ++ ++} ++#endif ++void sd_sync_int_hdl(struct sdio_func *func) ++{ ++ struct dvobj_priv *psdpriv = sdio_get_drvdata(func); ++ _adapter *padapter = (_adapter*)psdpriv->padapter; ++ u16 tmp16; ++// uint tasks; ++ ++_func_enter_; ++ ++ if ((padapter->bDriverStopped ==_TRUE) || (padapter->bSurpriseRemoved == _TRUE)) { ++ goto exit; ++ } ++ ++ //padapter->IsrContent=rtw_read16(padapter, SDIO_HISR); ++ sdio_read_int(padapter, SDIO_HISR, 2, &psdpriv->sdio_hisr); ++ ++ if (psdpriv->sdio_hisr & psdpriv->sdio_himr) ++ { ++ sdio_write_int(padapter, SDIO_HIMR, 0, 2); ++ sd_int_dpc(padapter); ++ sdio_write_int(padapter, SDIO_HIMR, psdpriv->sdio_himr, 2); ++ ++ sdio_read_int(padapter, SDIO_HIMR, 2, &tmp16); ++ if (tmp16 != psdpriv->sdio_himr) ++ sdio_write_int(padapter, SDIO_HIMR, psdpriv->sdio_himr, 2); ++ } else { ++ RT_TRACE(_module_hci_intfs_c_, _drv_info_, ("<=========== sd_sync_int_hdl(): not our INT")); ++ } ++exit: ++ ++_func_exit_; ++ ++ return; ++} ++ ++static int r871xs_drv_init(struct sdio_func *func, const struct sdio_device_id *id) ++{ ++ _adapter *padapter = NULL; ++ struct dvobj_priv *pdvobjpriv; ++ struct net_device *pnetdev; ++ ++ RT_TRACE(_module_hci_intfs_c_,_drv_alert_,("+871x - drv_init:id=0x%p func->vendor=0x%x func->device=0x%x\n",id,func->vendor,func->device)); ++ ++ //step 1. ++ pnetdev = rtw_init_netdev(NULL); ++ if (!pnetdev) ++ goto error; ++ ++ padapter = rtw_netdev_priv(pnetdev); ++ pdvobjpriv = &padapter->dvobjpriv; ++ pdvobjpriv->padapter = padapter; ++ pdvobjpriv->func = func; ++ sdio_set_drvdata(func, pdvobjpriv); ++ SET_NETDEV_DEV(pnetdev, &func->dev); ++ ++ ++ //step 2. ++ if (alloc_io_queue(padapter) == _FAIL) { ++ RT_TRACE(_module_hci_intfs_c_,_drv_err_,("Can't init io_reqs\n")); ++ goto error; ++ } ++ ++ ++#if 0 //temp remove ++ //step 3. ++ if (loadparam(padapter, pnetdev) == _FAIL) { ++ RT_TRACE(_module_hci_intfs_c_,_drv_err_,("Read Parameter Failed!\n")); ++ goto error; ++ } ++#endif ++ ++ //step 4. ++ //dvobj_init(padapter); ++ padapter->dvobj_init = &sd_dvobj_init; ++ padapter->dvobj_deinit = &sd_dvobj_deinit; ++ padapter->halpriv.hal_bus_init = &sd_hal_bus_init; ++ padapter->halpriv.hal_bus_deinit = &sd_hal_bus_deinit; ++ ++ if (padapter->dvobj_init == NULL) { ++ RT_TRACE(_module_hci_intfs_c_,_drv_err_,("\n Initialize dvobjpriv.dvobj_init error!!!\n")); ++ goto error; ++ } ++ ++ if (padapter->dvobj_init(padapter) == _FAIL) { ++ RT_TRACE(_module_hci_intfs_c_,_drv_err_,("\n initialize device object priv Failed!\n")); ++ goto error; ++ } ++ ++ ++ //step 6. ++ if (rtw_init_drv_sw(padapter) == _FAIL) { ++ RT_TRACE(_module_hci_intfs_c_,_drv_err_,("Initialize driver software resource Failed!\n")); ++ goto error; ++ } ++ ++#if 1 ++{ ++ //step 7. ++ u8 mac[6]; ++ mac[0]=0x00; ++ mac[1]=0xe0; ++ mac[2]=0x4c; ++ mac[3]=0x87; ++ mac[4]=0x66; ++ mac[5]=0x55; ++ ++ _rtw_memcpy(pnetdev->dev_addr, mac/*padapter->eeprompriv.mac_addr*/, ETH_ALEN); ++ RT_TRACE(_module_hci_intfs_c_,_drv_info_,("pnetdev->dev_addr=0x%x:0x%x:0x%x:0x%x:0x%x:0x%x\n",pnetdev->dev_addr[0],pnetdev->dev_addr[1],pnetdev->dev_addr[2],pnetdev->dev_addr[3],pnetdev->dev_addr[4],pnetdev->dev_addr[5])); ++} ++#endif ++ //step 8. ++ /* Tell the network stack we exist */ ++ if (register_netdev(pnetdev) != 0) { ++ RT_TRACE(_module_hci_intfs_c_,_drv_err_,("register_netdev() failed\n")); ++ goto error; ++ } ++ RT_TRACE(_module_hci_intfs_c_,_drv_info_,("register_netdev() success\n")); ++ RT_TRACE(_module_hci_intfs_c_,_drv_notice_,("-drv_init - Adapter->bDriverStopped=%d, Adapter->bSurpriseRemoved=%d\n",padapter->bDriverStopped, padapter->bSurpriseRemoved)); ++ RT_TRACE(_module_hci_intfs_c_,_drv_info_,("-871xs_drv - drv_init, success!\n")); ++ ++ return 0; ++ ++error: ++ ++ if (padapter->dvobj_deinit == NULL) { ++ RT_TRACE(_module_hci_intfs_c_,_drv_err_,("\n Initialize dvobjpriv.dvobj_deinit error!!!\n")); ++ } else { ++ padapter->dvobj_deinit(padapter); ++ } ++ ++ if (pnetdev) { ++ unregister_netdev(pnetdev); ++ rtw_free_netdev(pnetdev); ++ } ++ ++ RT_TRACE(_module_hci_intfs_c_, _drv_emerg_, ("-871x_sdio - drv_init, fail!\n")); ++ ++ return -1; ++} ++ ++void rtl871x_intf_stop(_adapter *padapter) ++{ ++ // Disable interrupt, also done in rtl8712_hal_deinit ++// rtw_write16(padapter, SDIO_HIMR, 0x00); ++} ++ ++void r871x_dev_unload(_adapter *padapter) ++{ ++ struct net_device *pnetdev = (struct net_device*)padapter->pnetdev; ++ ++ RT_TRACE(_module_hci_intfs_c_, _drv_err_, ("+r871x_dev_unload\n")); ++ ++ if (padapter->bup == _TRUE) ++ { ++#if 0 ++ //s1. ++ if (pnetdev) { ++ netif_carrier_off(pnetdev); ++ netif_stop_queue(pnetdev); ++ } ++ RT_TRACE(_module_hci_intfs_c_,_drv_err_,("@ r871x_dev_unload:complelte s1!\n")); ++ ++ //s2. ++ // indicate-disconnect if necssary (free all assoc-resources) ++ // dis-assoc from assoc_sta (optional) ++ rtw_indicate_disconnect(padapter); ++ rtw_free_network_queue(padapter, _TRUE); ++#endif ++ ++ padapter->bDriverStopped = _TRUE; ++ RT_TRACE(_module_hci_intfs_c_,_drv_err_,("@ r871x_dev_unload:complete s2!\n")); ++ ++ //s3. ++ rtl871x_intf_stop(padapter); ++ RT_TRACE(_module_hci_intfs_c_,_drv_err_,("@ r871x_dev_unload:complete s3!\n")); ++ ++ //s4. ++ rtw_stop_drv_threads(padapter); ++ RT_TRACE(_module_hci_intfs_c_,_drv_err_,("@ r871x_dev_unload:complete s4!\n")); ++ ++ //s5. ++ if (padapter->bSurpriseRemoved == _FALSE) { ++ rtl871x_hal_deinit(padapter); ++ padapter->bSurpriseRemoved = _TRUE; ++ } ++ RT_TRACE(_module_hci_intfs_c_,_drv_err_,("@ r871x_dev_unload:complelt s5!\n")); ++ ++ ++ RT_TRACE(_module_hci_intfs_c_,_drv_err_,("@ r871x_dev_unload:complete s6!\n")); ++ ++ padapter->bup = _FALSE; ++ } ++ else { ++ RT_TRACE(_module_hci_intfs_c_,_drv_err_,("r871x_dev_unload():padapter->bup == _FALSE\n" )); ++ } ++ ++ RT_TRACE(_module_hci_intfs_c_,_drv_err_,("-r871x_dev_unload\n")); ++} ++ ++static void r8712s_dev_remove(struct sdio_func *func) ++{ ++ _adapter *padapter = (_adapter*) (((struct dvobj_priv*)sdio_get_drvdata(func))->padapter); ++ struct net_device *pnetdev = (struct net_device *)padapter->pnetdev; ++ ++_func_exit_; ++ ++ if (padapter) ++ { ++ RT_TRACE(_module_hci_intfs_c_, _drv_err_, ("+dev_remove()\n")); ++ ++// padapter->bSurpriseRemoved = _TRUE; ++ ++ if (pnetdev) ++ unregister_netdev(pnetdev); //will call netdev_close() ++ ++ rtw_cancel_all_timer(padapter); ++ ++ r871x_dev_unload(padapter); ++ //s6. ++ if (padapter->dvobj_deinit) { ++ padapter->dvobj_deinit(padapter); // call sd_dvobj_deinit() ++ } else { ++ RT_TRACE(_module_hci_intfs_c_,_drv_err_,("Initialize hcipriv.hci_priv_init error!!!\n")); ++ } ++ ++ rtw_free_drv_sw(padapter); ++ //after rtw_free_drv_sw(), padapter has beed freed, don't refer to it. ++ ++ sdio_claim_host(func); ++ RT_TRACE(_module_hci_intfs_c_,_drv_err_,(" in dev_remove():sdio_claim_host !\n")); ++ sdio_release_irq(func); ++ RT_TRACE(_module_hci_intfs_c_,_drv_err_,(" in dev_remove():sdio_release_irq !\n")); ++ sdio_disable_func(func); ++ RT_TRACE(_module_hci_intfs_c_,_drv_err_,(" in dev_remove():sdio_disable_func !\n")); ++ sdio_release_host(func); ++ RT_TRACE(_module_hci_intfs_c_,_drv_err_,(" in dev_remove():sdio_release_host !\n")); ++ } ++ RT_TRACE(_module_hci_intfs_c_,_drv_err_,("-dev_remove()\n")); ++ ++_func_exit_; ++ ++ return; ++} ++ ++static drv_priv drvpriv = { ++ .r871xs_drv.probe = r871xs_drv_init, ++ .r871xs_drv.remove = r8712s_dev_remove, ++ .r871xs_drv.name = "rtl871x_sdio_wlan", ++ .r871xs_drv.id_table = sdio_ids, ++}; ++ ++ ++static int __init r8712s_drv_entry(void) ++{ ++ int status; ++ RT_TRACE(_module_hci_intfs_c_,_drv_err_,("+8712s_sdio - drv_entry\n")); ++ status = sdio_register_driver(&drvpriv.r871xs_drv); ++ RT_TRACE(_module_hci_intfs_c_,_drv_err_,("-8712_sdio - drv_entry, status=%d\n", status)); ++ ++ return status; ++} ++ ++static void __exit r8712s_drv_halt(void) ++{ ++ int ret; ++ ++ RT_TRACE(_module_hci_intfs_c_,_drv_err_,("+8712_sdio - drv_halt\n")); ++ sdio_unregister_driver(&drvpriv.r871xs_drv); // call r8712s_dev_remove() ++ RT_TRACE(_module_hci_intfs_c_,_drv_err_,("-8712_sdio - drv_halt\n")); ++ ++} ++ ++ ++module_init(r8712s_drv_entry); ++module_exit(r8712s_drv_halt); +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/os_dep/linux/usb_intf.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/os_dep/linux/usb_intf.c 2013-07-26 19:36:07.000000000 +0000 +@@ -0,0 +1,1524 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ++******************************************************************************/ ++#define _HCI_INTF_C_ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#ifndef CONFIG_USB_HCI ++ ++#error "CONFIG_USB_HCI shall be on!\n" ++ ++#endif ++ ++#include ++#include ++#include ++#include ++#ifdef CONFIG_PLATFORM_RTK_DMP ++#include ++#endif ++ ++#if defined (PLATFORM_LINUX) && defined (PLATFORM_WINDOWS) ++ ++#error "Shall be Linux or Windows, but not both!\n" ++ ++#endif ++ ++#ifdef CONFIG_80211N_HT ++extern int rtw_ht_enable; ++extern int rtw_cbw40_enable; ++extern int rtw_ampdu_enable;//for enable tx_ampdu ++#endif ++ ++#ifdef CONFIG_GLOBAL_UI_PID ++int ui_pid[3] = {0, 0, 0}; ++#endif ++ ++ ++extern int pm_netdev_open(struct net_device *pnetdev,u8 bnormal); ++static int rtw_suspend(struct usb_interface *intf, pm_message_t message); ++static int rtw_resume(struct usb_interface *intf); ++int rtw_resume_process(struct usb_interface *pusb_intf); ++ ++ ++static int rtw_drv_init(struct usb_interface *pusb_intf,const struct usb_device_id *pdid); ++static void rtw_dev_remove(struct usb_interface *pusb_intf); ++ ++#define USB_VENDER_ID_REALTEK 0x0BDA ++ ++//DID_USB_v82_20110808 ++static struct usb_device_id rtw_usb_id_tbl[] ={ ++#ifdef CONFIG_RTL8192C ++ /*=== Realtek demoboard ===*/ ++ {USB_DEVICE(0x0BDA, 0x8191)},//Default ID ++ ++ /****** 8188CUS ********/ ++ {USB_DEVICE(USB_VENDER_ID_REALTEK, 0x8176)},//8188cu 1*1 dongole ++ {USB_DEVICE(USB_VENDER_ID_REALTEK, 0x8170)},//8188CE-VAU USB minCard ++ {USB_DEVICE(USB_VENDER_ID_REALTEK, 0x817E)},//8188CE-VAU USB minCard ++ {USB_DEVICE(USB_VENDER_ID_REALTEK, 0x817A)},//8188cu Slim Solo ++ {USB_DEVICE(USB_VENDER_ID_REALTEK, 0x817B)},//8188cu Slim Combo ++ {USB_DEVICE(USB_VENDER_ID_REALTEK, 0x817D)},//8188RU High-power USB Dongle ++ {USB_DEVICE(USB_VENDER_ID_REALTEK, 0x8754)},//8188 Combo for BC4 ++ {USB_DEVICE(USB_VENDER_ID_REALTEK, 0x817F)},//8188RU ++ {USB_DEVICE(USB_VENDER_ID_REALTEK, 0x818A)},//RTL8188CUS-VL ++ {USB_DEVICE(USB_VENDER_ID_REALTEK, 0x018A)},//RTL8188CTV ++ ++ /****** 8192CUS ********/ ++ {USB_DEVICE(USB_VENDER_ID_REALTEK, 0x8177)},//8191cu 1*2 ++ {USB_DEVICE(USB_VENDER_ID_REALTEK, 0x8178)},//8192cu 2*2 ++ {USB_DEVICE(USB_VENDER_ID_REALTEK, 0x817C)},//8192CE-VAU USB minCard ++ ++ ++ /*=== Customer ID ===*/ ++ /****** 8188CUS Dongle ********/ ++ {USB_DEVICE(0x2019, 0xED17)},//PCI - Edimax ++ {USB_DEVICE(0x0DF6, 0x0052)},//Sitecom - Edimax ++ {USB_DEVICE(0x7392, 0x7811)},//Edimax - Edimax ++ {USB_DEVICE(0x07B8, 0x8189)},//Abocom - Abocom ++ {USB_DEVICE(0x0EB0, 0x9071)},//NO Brand - Etop ++ {USB_DEVICE(0x06F8, 0xE033)},//Hercules - Edimax ++ {USB_DEVICE(0x103C, 0x1629)},//HP - Lite-On ,8188CUS Slim Combo ++ {USB_DEVICE(0x2001, 0x3308)},//D-Link - Alpha ++ {USB_DEVICE(0x050D, 0x1102)},//Belkin - Edimax ++ {USB_DEVICE(0x2019, 0xAB2A)},//Planex - Abocom ++ {USB_DEVICE(0x20F4, 0x648B)},//TRENDnet - Cameo ++ {USB_DEVICE(0x4855, 0x0090)},// - Feixun ++ {USB_DEVICE(0x13D3, 0x3357)},// - AzureWave ++ {USB_DEVICE(0x0DF6, 0x005C)},//Sitecom - Edimax ++ {USB_DEVICE(0x0BDA, 0x5088)},//Thinkware - CC&C ++ {USB_DEVICE(0x4856, 0x0091)},//NetweeN - Feixun ++ {USB_DEVICE(0x2019, 0x4902)},//Planex - Etop ++ {USB_DEVICE(0x2019, 0xAB2E)},//SW-WF02-AD15 -Abocom ++ {USB_DEVICE(0x0846, 0x9041)},//Netgear ++ ++ /****** 8188 RU ********/ ++ {USB_DEVICE(0x0BDA, 0x317F)},//Netcore,Netcore ++ ++ /****** 8188CE-VAU ********/ ++ {USB_DEVICE(0x13D3, 0x3359)},// - Azwave ++ {USB_DEVICE(0x13D3, 0x3358)},// - Azwave ++ ++ /****** 8188CUS Slim Solo********/ ++ {USB_DEVICE(0x04F2, 0xAFF7)},//XAVI - XAVI ++ {USB_DEVICE(0x04F2, 0xAFF9)},//XAVI - XAVI ++ {USB_DEVICE(0x04F2, 0xAFFA)},//XAVI - XAVI ++ ++ /****** 8188CUS Slim Combo ********/ ++ {USB_DEVICE(0x04F2, 0xAFF8)},//XAVI - XAVI ++ {USB_DEVICE(0x04F2, 0xAFFB)},//XAVI - XAVI ++ {USB_DEVICE(0x04F2, 0xAFFC)},//XAVI - XAVI ++ {USB_DEVICE(0x2019, 0x1201)},//Planex - Vencer ++ ++ /****** 8192CUS Dongle ********/ ++ {USB_DEVICE(0x2001, 0x3307)},//D-Link - Cameo ++ {USB_DEVICE(0x2001, 0x330A)},//D-Link - Alpha ++ {USB_DEVICE(0x2001, 0x3309)},//D-Link - Alpha ++ {USB_DEVICE(0x0586, 0x341F)},//Zyxel - Abocom ++ {USB_DEVICE(0x7392, 0x7822)},//Edimax - Edimax ++ {USB_DEVICE(0x2019, 0xAB2B)},//Planex - Abocom ++ {USB_DEVICE(0x07B8, 0x8178)},//Abocom - Abocom ++ {USB_DEVICE(0x07AA, 0x0056)},//ATKK - Gemtek ++ {USB_DEVICE(0x4855, 0x0091)},// - Feixun ++ {USB_DEVICE(0x2001, 0x3307)},//D-Link-Cameo ++ {USB_DEVICE(0x050D, 0x2102)},//Belkin - Sercomm ++ {USB_DEVICE(0x050D, 0x2103)},//Belkin - Edimax ++ {USB_DEVICE(0x20F4, 0x624D)},//TRENDnet ++ {USB_DEVICE(0x0DF6, 0x0061)},//Sitecom - Edimax ++ {USB_DEVICE(0x0B05, 0x17AB)},//ASUS - Edimax ++ {USB_DEVICE(0x0846, 0x9021)},//Netgear - Sercomm ++ {USB_DEVICE(0x0E66, 0x0019)},//Hawking,Edimax ++ ++ /****** 8192CE-VAU ********/ ++ {USB_DEVICE(USB_VENDER_ID_REALTEK, 0x8186)},//Intel-Xavi( Azwave) ++#endif ++#ifdef CONFIG_RTL8192D ++ /*=== Realtek demoboard ===*/ ++ /****** 8192DU ********/ ++ {USB_DEVICE(USB_VENDER_ID_REALTEK, 0x8193)},//8192DU-VC ++ {USB_DEVICE(USB_VENDER_ID_REALTEK, 0x8194)},//8192DU-VS ++ {USB_DEVICE(USB_VENDER_ID_REALTEK, 0x8111)},//Realtek 5G dongle for WiFi Display ++ {USB_DEVICE(USB_VENDER_ID_REALTEK, 0x0193)},//8192DE-VAU ++ {USB_DEVICE(USB_VENDER_ID_REALTEK, 0x8171)},//8192DU-VC ++ ++ /*=== Customer ID ===*/ ++ /****** 8192DU-VC ********/ ++ {USB_DEVICE(0x2019, 0xAB2C)},//PCI - Abocm ++ {USB_DEVICE(0x2019, 0x4903)},//PCI - ETOP ++ {USB_DEVICE(0x2019, 0x4904)},//PCI - ETOP ++ {USB_DEVICE(0x07B8, 0x8193)},//Abocom - Abocom ++ ++ /****** 8192DU-VS ********/ ++ {USB_DEVICE(0x20F4, 0x664B)},//TRENDnet ++ ++ /****** 8192DU-WiFi Display Dongle ********/ ++ {USB_DEVICE(0x2019, 0xAB2D)},//Planex - Abocom ,5G dongle for WiFi Display ++#endif ++ {} /* Terminating entry */ ++}; ++ ++int const rtw_usb_id_len = sizeof(rtw_usb_id_tbl) / sizeof(struct usb_device_id); ++ ++static struct specific_device_id specific_device_id_tbl[] = { ++ {.idVendor=USB_VENDER_ID_REALTEK, .idProduct=0x8177, .flags=SPEC_DEV_ID_DISABLE_HT},//8188cu 1*1 dongole, (b/g mode only) ++ {.idVendor=USB_VENDER_ID_REALTEK, .idProduct=0x817E, .flags=SPEC_DEV_ID_DISABLE_HT},//8188CE-VAU USB minCard (b/g mode only) ++ {.idVendor=0x0b05, .idProduct=0x1791, .flags=SPEC_DEV_ID_DISABLE_HT}, ++ {.idVendor=0x13D3, .idProduct=0x3311, .flags=SPEC_DEV_ID_DISABLE_HT}, ++ {.idVendor=0x13D3, .idProduct=0x3359, .flags=SPEC_DEV_ID_DISABLE_HT},//Russian customer -Azwave (8188CE-VAU g mode) ++#ifdef RTK_DMP_PLATFORM ++ {.idVendor=USB_VENDER_ID_REALTEK, .idProduct=0x8111, .flags=SPEC_DEV_ID_ASSIGN_IFNAME}, // Realtek 5G dongle for WiFi Display ++ {.idVendor=0x2019, .idProduct=0xAB2D, .flags=SPEC_DEV_ID_ASSIGN_IFNAME}, // PCI-Abocom 5G dongle for WiFi Display ++#endif /* RTK_DMP_PLATFORM */ ++ {} ++}; ++ ++typedef struct _driver_priv{ ++ ++ struct usb_driver rtw_usb_drv; ++ int drv_registered; ++ ++}drv_priv, *pdrv_priv; ++ ++ ++static drv_priv drvpriv = { ++ .rtw_usb_drv.name = (char*)DRV_NAME, ++ .rtw_usb_drv.probe = rtw_drv_init, ++ .rtw_usb_drv.disconnect = rtw_dev_remove, ++ .rtw_usb_drv.id_table = rtw_usb_id_tbl, ++ .rtw_usb_drv.suspend = rtw_suspend, ++ .rtw_usb_drv.resume = rtw_resume, ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 22)) ++ .rtw_usb_drv.reset_resume = rtw_resume, ++#endif ++#ifdef CONFIG_AUTOSUSPEND ++ .rtw_usb_drv.supports_autosuspend = 1, ++#endif ++}; ++ ++MODULE_DEVICE_TABLE(usb, rtw_usb_id_tbl); ++ ++ ++static inline int RT_usb_endpoint_dir_in(const struct usb_endpoint_descriptor *epd) ++{ ++ return ((epd->bEndpointAddress & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN); ++} ++ ++static inline int RT_usb_endpoint_dir_out(const struct usb_endpoint_descriptor *epd) ++{ ++ return ((epd->bEndpointAddress & USB_ENDPOINT_DIR_MASK) == USB_DIR_OUT); ++} ++ ++static inline int RT_usb_endpoint_xfer_int(const struct usb_endpoint_descriptor *epd) ++{ ++ return ((epd->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_INT); ++} ++ ++static inline int RT_usb_endpoint_xfer_bulk(const struct usb_endpoint_descriptor *epd) ++{ ++ return ((epd->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_BULK); ++} ++ ++static inline int RT_usb_endpoint_is_bulk_in(const struct usb_endpoint_descriptor *epd) ++{ ++ return (RT_usb_endpoint_xfer_bulk(epd) && RT_usb_endpoint_dir_in(epd)); ++} ++ ++static inline int RT_usb_endpoint_is_bulk_out(const struct usb_endpoint_descriptor *epd) ++{ ++ return (RT_usb_endpoint_xfer_bulk(epd) && RT_usb_endpoint_dir_out(epd)); ++} ++ ++static inline int RT_usb_endpoint_is_int_in(const struct usb_endpoint_descriptor *epd) ++{ ++ return (RT_usb_endpoint_xfer_int(epd) && RT_usb_endpoint_dir_in(epd)); ++} ++ ++static inline int RT_usb_endpoint_num(const struct usb_endpoint_descriptor *epd) ++{ ++ return epd->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK; ++} ++ ++u8 rtw_init_intf_priv(_adapter * padapter) ++{ ++ u8 rst = _SUCCESS; ++ ++ #ifdef CONFIG_USB_VENDOR_REQ_MUTEX ++ _rtw_mutex_init(&padapter->dvobjpriv.usb_vendor_req_mutex); ++ #endif ++ ++ ++#ifdef CONFIG_USB_VENDOR_REQ_BUFFER_PREALLOC ++ padapter->dvobjpriv.usb_alloc_vendor_req_buf = rtw_zmalloc(MAX_USB_IO_CTL_SIZE); ++ ++ if (padapter->dvobjpriv.usb_alloc_vendor_req_buf == NULL){ ++ padapter->dvobjpriv.usb_alloc_vendor_req_buf =NULL; ++ printk("alloc usb_vendor_req_buf failed... /n"); ++ rst = _FAIL; ++ goto exit; ++ } ++ padapter->dvobjpriv.usb_vendor_req_buf = ++ (u8 *)N_BYTE_ALIGMENT((SIZE_PTR)(padapter->dvobjpriv.usb_alloc_vendor_req_buf ), ALIGNMENT_UNIT); ++exit: ++#endif //CONFIG_USB_VENDOR_REQ_BUFFER_PREALLOC ++ ++ return rst; ++ ++} ++ ++u8 rtw_deinit_intf_priv(_adapter * padapter) ++{ ++ u8 rst = _SUCCESS; ++ ++ #ifdef CONFIG_USB_VENDOR_REQ_BUFFER_PREALLOC ++ if(padapter->dvobjpriv.usb_vendor_req_buf) ++ { ++ rtw_mfree(padapter->dvobjpriv.usb_alloc_vendor_req_buf,MAX_USB_IO_CTL_SIZE); ++ } ++ #endif //CONFIG_USB_VENDOR_REQ_BUFFER_PREALLOC ++ ++ ++ #ifdef CONFIG_USB_VENDOR_REQ_MUTEX ++ _rtw_mutex_free(&padapter->dvobjpriv.usb_vendor_req_mutex); ++ #endif ++ ++ return rst; ++ ++} ++ ++static u32 usb_dvobj_init(_adapter *padapter) ++{ ++ int i; ++ u8 val8; ++ int status = _SUCCESS; ++ struct usb_device_descriptor *pdev_desc; ++ struct usb_host_config *phost_conf; ++ struct usb_config_descriptor *pconf_desc; ++ struct usb_host_interface *phost_iface; ++ struct usb_interface_descriptor *piface_desc; ++ struct usb_host_endpoint *phost_endp; ++ struct usb_endpoint_descriptor *pendp_desc; ++ struct dvobj_priv *pdvobjpriv = &padapter->dvobjpriv; ++ struct usb_device *pusbd = pdvobjpriv->pusbdev; ++ struct usb_interface *pusb_interface = pdvobjpriv->pusbintf; ++ ++_func_enter_; ++ ++ pdvobjpriv->padapter = padapter; ++ ++ pdvobjpriv->RtNumInPipes = 0; ++ pdvobjpriv->RtNumOutPipes = 0; ++ ++ //padapter->EepromAddressSize = 6; ++ //pdvobjpriv->nr_endpoint = 6; ++ ++ pdev_desc = &pusbd->descriptor; ++ ++#if 0 ++ DBG_8192C("\n8712_usb_device_descriptor:\n"); ++ DBG_8192C("bLength=%x\n", pdev_desc->bLength); ++ DBG_8192C("bDescriptorType=%x\n", pdev_desc->bDescriptorType); ++ DBG_8192C("bcdUSB=%x\n", pdev_desc->bcdUSB); ++ DBG_8192C("bDeviceClass=%x\n", pdev_desc->bDeviceClass); ++ DBG_8192C("bDeviceSubClass=%x\n", pdev_desc->bDeviceSubClass); ++ DBG_8192C("bDeviceProtocol=%x\n", pdev_desc->bDeviceProtocol); ++ DBG_8192C("bMaxPacketSize0=%x\n", pdev_desc->bMaxPacketSize0); ++ DBG_8192C("idVendor=%x\n", pdev_desc->idVendor); ++ DBG_8192C("idProduct=%x\n", pdev_desc->idProduct); ++ DBG_8192C("bcdDevice=%x\n", pdev_desc->bcdDevice); ++ DBG_8192C("iManufacturer=%x\n", pdev_desc->iManufacturer); ++ DBG_8192C("iProduct=%x\n", pdev_desc->iProduct); ++ DBG_8192C("iSerialNumber=%x\n", pdev_desc->iSerialNumber); ++ DBG_8192C("bNumConfigurations=%x\n", pdev_desc->bNumConfigurations); ++#endif ++ ++ phost_conf = pusbd->actconfig; ++ pconf_desc = &phost_conf->desc; ++ ++#if 0 ++ DBG_8192C("\n8712_usb_configuration_descriptor:\n"); ++ DBG_8192C("bLength=%x\n", pconf_desc->bLength); ++ DBG_8192C("bDescriptorType=%x\n", pconf_desc->bDescriptorType); ++ DBG_8192C("wTotalLength=%x\n", pconf_desc->wTotalLength); ++ DBG_8192C("bNumInterfaces=%x\n", pconf_desc->bNumInterfaces); ++ DBG_8192C("bConfigurationValue=%x\n", pconf_desc->bConfigurationValue); ++ DBG_8192C("iConfiguration=%x\n", pconf_desc->iConfiguration); ++ DBG_8192C("bmAttributes=%x\n", pconf_desc->bmAttributes); ++ DBG_8192C("bMaxPower=%x\n", pconf_desc->bMaxPower); ++#endif ++ ++ //DBG_8192C("\n/****** num of altsetting = (%d) ******/\n", pusb_interface->num_altsetting); ++ ++ phost_iface = &pusb_interface->altsetting[0]; ++ piface_desc = &phost_iface->desc; ++ ++#if 0 ++ DBG_8192C("\n8712_usb_interface_descriptor:\n"); ++ DBG_8192C("bLength=%x\n", piface_desc->bLength); ++ DBG_8192C("bDescriptorType=%x\n", piface_desc->bDescriptorType); ++ DBG_8192C("bInterfaceNumber=%x\n", piface_desc->bInterfaceNumber); ++ DBG_8192C("bAlternateSetting=%x\n", piface_desc->bAlternateSetting); ++ DBG_8192C("bNumEndpoints=%x\n", piface_desc->bNumEndpoints); ++ DBG_8192C("bInterfaceClass=%x\n", piface_desc->bInterfaceClass); ++ DBG_8192C("bInterfaceSubClass=%x\n", piface_desc->bInterfaceSubClass); ++ DBG_8192C("bInterfaceProtocol=%x\n", piface_desc->bInterfaceProtocol); ++ DBG_8192C("iInterface=%x\n", piface_desc->iInterface); ++#endif ++ ++ pdvobjpriv->NumInterfaces = pconf_desc->bNumInterfaces; ++ pdvobjpriv->InterfaceNumber = piface_desc->bInterfaceNumber; ++ pdvobjpriv->nr_endpoint = piface_desc->bNumEndpoints; ++ ++ //DBG_8192C("\ndump usb_endpoint_descriptor:\n"); ++ ++ for (i = 0; i < pdvobjpriv->nr_endpoint; i++) ++ { ++ phost_endp = phost_iface->endpoint + i; ++ if (phost_endp) ++ { ++ pendp_desc = &phost_endp->desc; ++ ++ DBG_8192C("\nusb_endpoint_descriptor(%d):\n", i); ++ DBG_8192C("bLength=%x\n",pendp_desc->bLength); ++ DBG_8192C("bDescriptorType=%x\n",pendp_desc->bDescriptorType); ++ DBG_8192C("bEndpointAddress=%x\n",pendp_desc->bEndpointAddress); ++ //DBG_8192C("bmAttributes=%x\n",pendp_desc->bmAttributes); ++ //DBG_8192C("wMaxPacketSize=%x\n",pendp_desc->wMaxPacketSize); ++ DBG_8192C("wMaxPacketSize=%x\n",le16_to_cpu(pendp_desc->wMaxPacketSize)); ++ DBG_8192C("bInterval=%x\n",pendp_desc->bInterval); ++ //DBG_8192C("bRefresh=%x\n",pendp_desc->bRefresh); ++ //DBG_8192C("bSynchAddress=%x\n",pendp_desc->bSynchAddress); ++ ++ if (RT_usb_endpoint_is_bulk_in(pendp_desc)) ++ { ++ DBG_8192C("RT_usb_endpoint_is_bulk_in = %x\n", RT_usb_endpoint_num(pendp_desc)); ++ pdvobjpriv->RtNumInPipes++; ++ } ++ else if (RT_usb_endpoint_is_int_in(pendp_desc)) ++ { ++ DBG_8192C("RT_usb_endpoint_is_int_in = %x, Interval = %x\n", RT_usb_endpoint_num(pendp_desc),pendp_desc->bInterval); ++ pdvobjpriv->RtNumInPipes++; ++ } ++ else if (RT_usb_endpoint_is_bulk_out(pendp_desc)) ++ { ++ DBG_8192C("RT_usb_endpoint_is_bulk_out = %x\n", RT_usb_endpoint_num(pendp_desc)); ++ pdvobjpriv->RtNumOutPipes++; ++ } ++ pdvobjpriv->ep_num[i] = RT_usb_endpoint_num(pendp_desc); ++ } ++ } ++ ++ DBG_8192C("nr_endpoint=%d, in_num=%d, out_num=%d\n\n", pdvobjpriv->nr_endpoint, pdvobjpriv->RtNumInPipes, pdvobjpriv->RtNumOutPipes); ++ ++ if (pusbd->speed == USB_SPEED_HIGH) ++ { ++ pdvobjpriv->ishighspeed = _TRUE; ++ DBG_8192C("USB_SPEED_HIGH\n"); ++ } ++ else ++ { ++ pdvobjpriv->ishighspeed = _FALSE; ++ DBG_8192C("NON USB_SPEED_HIGH\n"); ++ } ++ ++ //.2 ++ if ((rtw_init_io_priv(padapter)) == _FAIL) ++ { ++ RT_TRACE(_module_hci_intfs_c_,_drv_err_,(" \n Can't init io_reqs\n")); ++ status = _FAIL; ++ } ++ ++ if((rtw_init_intf_priv(padapter) )== _FAIL) ++ { ++ RT_TRACE(_module_os_intfs_c_,_drv_err_,("\n Can't INIT rtw_init_intf_priv\n")); ++ status = _FAIL; ++ } ++ ++ //.3 misc ++ _rtw_init_sema(&(padapter->dvobjpriv.usb_suspend_sema), 0); ++ ++ intf_read_chip_version(padapter); ++ ++ //.4 usb endpoint mapping ++ intf_chip_configure(padapter); ++ ++ rtw_reset_continual_urb_error(pdvobjpriv); ++ ++_func_exit_; ++ ++ return status; ++} ++ ++static void usb_dvobj_deinit(_adapter * padapter){ ++ ++ struct dvobj_priv *pdvobjpriv=&padapter->dvobjpriv; ++ ++ _func_enter_; ++ ++ rtw_deinit_intf_priv(padapter); ++ ++ _func_exit_; ++} ++ ++static void decide_chip_type_by_usb_device_id(_adapter *padapter, const struct usb_device_id *pdid) ++{ ++ //u32 i; ++ //u16 vid, pid; ++ ++ padapter->chip_type = NULL_CHIP_TYPE; ++ ++ //vid = pdid->idVendor; ++ //pid = pdid->idProduct; ++ ++ //TODO: dynamic judge 92c or 92d according to usb vid and pid. ++#ifdef CONFIG_RTL8192C ++ padapter->chip_type = RTL8188C_8192C; ++ padapter->HardwareType = HARDWARE_TYPE_RTL8192CU; ++ DBG_8192C("CHIP TYPE: RTL8188C_8192C\n"); ++#endif ++ ++#ifdef CONFIG_RTL8192D ++ padapter->chip_type = RTL8192D; ++ padapter->HardwareType = HARDWARE_TYPE_RTL8192DU; ++ DBG_8192C("CHIP TYPE: RTL8192D\n"); ++#endif ++ ++} ++ ++static void usb_intf_start(_adapter *padapter) ++{ ++ ++ RT_TRACE(_module_hci_intfs_c_,_drv_err_,("+usb_intf_start\n")); ++ ++ if(padapter->HalFunc.inirp_init == NULL) ++ { ++ RT_TRACE(_module_os_intfs_c_,_drv_err_,("Initialize dvobjpriv.inirp_init error!!!\n")); ++ } ++ else ++ { ++ padapter->HalFunc.inirp_init(padapter); ++ } ++ ++ RT_TRACE(_module_hci_intfs_c_,_drv_err_,("-usb_intf_start\n")); ++ ++} ++ ++static void usb_intf_stop(_adapter *padapter) ++{ ++ ++ RT_TRACE(_module_hci_intfs_c_,_drv_err_,("+usb_intf_stop\n")); ++ ++ //disabel_hw_interrupt ++ if(padapter->bSurpriseRemoved == _FALSE) ++ { ++ //device still exists, so driver can do i/o operation ++ //TODO: ++ RT_TRACE(_module_hci_intfs_c_,_drv_err_,("SurpriseRemoved==_FALSE\n")); ++ } ++ ++ //cancel in irp ++ if(padapter->HalFunc.inirp_deinit !=NULL) ++ { ++ padapter->HalFunc.inirp_deinit(padapter); ++ } ++ ++ //cancel out irp ++ rtw_write_port_cancel(padapter); ++ ++ //todo:cancel other irps ++ ++ RT_TRACE(_module_hci_intfs_c_,_drv_err_,("-usb_intf_stop\n")); ++ ++} ++ ++static void rtw_dev_unload(_adapter *padapter) ++{ ++ struct net_device *pnetdev= (struct net_device*)padapter->pnetdev; ++ u8 val8; ++ RT_TRACE(_module_hci_intfs_c_,_drv_err_,("+rtw_dev_unload\n")); ++ ++ if(padapter->bup == _TRUE) ++ { ++ DBG_8192C("===> rtw_dev_unload\n"); ++ ++ padapter->bDriverStopped = _TRUE; ++ ++ //s3. ++ if(padapter->intf_stop) ++ { ++ padapter->intf_stop(padapter); ++ } ++ ++ //s4. ++ if(!padapter->pwrctrlpriv.bInternalAutoSuspend ) ++ rtw_stop_drv_threads(padapter); ++ ++ ++ //s5. ++ if(padapter->bSurpriseRemoved == _FALSE) ++ { ++ //DBG_8192C("r871x_dev_unload()->rtl871x_hal_deinit()\n"); ++ #ifdef CONFIG_WOWLAN ++ if((padapter->pwrctrlpriv.bSupportRemoteWakeup==_TRUE)&&(padapter->pwrctrlpriv.wowlan_mode==_TRUE)){ ++ DBG_8192C("%s bSupportWakeOnWlan==_TRUE do not run rtw_hal_deinit()\n",__FUNCTION__); ++ } ++ else ++ #endif //CONFIG_WOWLAN ++ { ++ rtw_hal_deinit(padapter); ++ } ++ padapter->bSurpriseRemoved = _TRUE; ++ } ++ ++ padapter->bup = _FALSE; ++ ++ } ++ else ++ { ++ RT_TRACE(_module_hci_intfs_c_,_drv_err_,("r871x_dev_unload():padapter->bup == _FALSE\n" )); ++ } ++ ++ DBG_8192C("<=== rtw_dev_unload\n"); ++ ++ RT_TRACE(_module_hci_intfs_c_,_drv_err_,("-rtw_dev_unload\n")); ++ ++} ++ ++static void process_spec_devid(const struct usb_device_id *pdid) ++{ ++ u16 vid, pid; ++ u32 flags; ++ int i; ++ int num = sizeof(specific_device_id_tbl)/sizeof(struct specific_device_id); ++ ++ for(i=0; iidVendor==vid) && (pdid->idProduct==pid) && (flags&SPEC_DEV_ID_DISABLE_HT)) ++ { ++ rtw_ht_enable = 0; ++ rtw_cbw40_enable = 0; ++ rtw_ampdu_enable = 0; ++ } ++#endif ++ ++#ifdef RTK_DMP_PLATFORM ++ // Change the ifname to wlan10 when PC side WFD dongle plugin on DMP platform. ++ // It is used to distinguish between normal and PC-side wifi dongle/module. ++ if((pdid->idVendor==vid) && (pdid->idProduct==pid) && (flags&SPEC_DEV_ID_ASSIGN_IFNAME)) ++ { ++ extern char* ifname; ++ strncpy(ifname, "wlan10", 6); ++ //DBG_8192C("%s()-%d: ifname=%s, vid=%04X, pid=%04X\n", __FUNCTION__, __LINE__, ifname, vid, pid); ++ } ++#endif /* RTK_DMP_PLATFORM */ ++ ++ } ++} ++ ++#ifdef SUPPORT_HW_RFOFF_DETECTED ++extern u8 disconnect_hdl(_adapter *padapter, u8 *pbuf); ++extern void rtw_os_indicate_disconnect( _adapter *adapter ); ++ ++int rtw_hw_suspend(_adapter *padapter ) ++{ ++ struct pwrctrl_priv *pwrpriv = &padapter->pwrctrlpriv; ++ struct usb_interface *pusb_intf = padapter->dvobjpriv.pusbintf; ++ struct net_device *pnetdev=usb_get_intfdata(pusb_intf); ++ ++ _func_enter_; ++ ++ if((!padapter->bup) || (padapter->bDriverStopped)||(padapter->bSurpriseRemoved)) ++ { ++ DBG_8192C("padapter->bup=%d bDriverStopped=%d bSurpriseRemoved = %d\n", ++ padapter->bup, padapter->bDriverStopped,padapter->bSurpriseRemoved); ++ goto error_exit; ++ } ++ ++ if(padapter)//system suspend ++ { ++ LeaveAllPowerSaveMode(padapter); ++ ++ DBG_8192C("==> rtw_hw_suspend\n"); ++ _enter_pwrlock(&pwrpriv->lock); ++ pwrpriv->bips_processing = _TRUE; ++ //padapter->net_closed = _TRUE; ++ //s1. ++ if(pnetdev) ++ { ++ netif_carrier_off(pnetdev); ++ netif_stop_queue(pnetdev); ++ } ++ ++ //s2. ++ //s2-1. issue rtw_disassoc_cmd to fw ++ //rtw_disassoc_cmd(padapter);//donnot enqueue cmd ++ disconnect_hdl(padapter, NULL); ++ ++ //s2-2. indicate disconnect to os ++ //rtw_indicate_disconnect(padapter); ++ { ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ ++ if(check_fwstate(pmlmepriv, _FW_LINKED)) ++ { ++ _clr_fwstate_(pmlmepriv, _FW_LINKED); ++ ++ rtw_led_control(padapter, LED_CTL_NO_LINK); ++ ++ rtw_os_indicate_disconnect(padapter); ++ ++ #ifdef CONFIG_LPS ++ //donnot enqueue cmd ++ rtw_lps_ctrl_wk_cmd(padapter, LPS_CTRL_DISCONNECT, 0); ++ #endif ++ } ++ ++ } ++ //s2-3. ++ rtw_free_assoc_resources(padapter, 1); ++ ++ //s2-4. ++ rtw_free_network_queue(padapter,_TRUE); ++ #ifdef CONFIG_IPS ++ rtw_ips_dev_unload(padapter); ++ #endif ++ pwrpriv->rf_pwrstate = rf_off; ++ pwrpriv->bips_processing = _FALSE; ++ ++ _exit_pwrlock(&pwrpriv->lock); ++ } ++ else ++ goto error_exit; ++ ++ _func_exit_; ++ return 0; ++ ++error_exit: ++ DBG_8192C("%s, failed \n",__FUNCTION__); ++ return (-1); ++ ++} ++ ++int rtw_hw_resume(_adapter *padapter) ++{ ++ struct pwrctrl_priv *pwrpriv = &padapter->pwrctrlpriv; ++ struct usb_interface *pusb_intf = padapter->dvobjpriv.pusbintf; ++ struct net_device *pnetdev=usb_get_intfdata(pusb_intf); ++ ++ _func_enter_; ++ ++ if(padapter)//system resume ++ { ++ DBG_8192C("==> rtw_hw_resume\n"); ++ _enter_pwrlock(&pwrpriv->lock); ++ pwrpriv->bips_processing = _TRUE; ++ rtw_reset_drv_sw(padapter); ++ ++ if(pm_netdev_open(pnetdev,_FALSE) != 0) ++ { ++ _exit_pwrlock(&pwrpriv->lock); ++ goto error_exit; ++ } ++ ++ netif_device_attach(pnetdev); ++ netif_carrier_on(pnetdev); ++ ++ if(!netif_queue_stopped(pnetdev)) ++ netif_start_queue(pnetdev); ++ else ++ netif_wake_queue(pnetdev); ++ ++ pwrpriv->bkeepfwalive = _FALSE; ++ pwrpriv->brfoffbyhw = _FALSE; ++ ++ pwrpriv->rf_pwrstate = rf_on; ++ pwrpriv->bips_processing = _FALSE; ++ ++ _exit_pwrlock(&pwrpriv->lock); ++ } ++ else ++ { ++ goto error_exit; ++ } ++ ++ _func_exit_; ++ ++ return 0; ++error_exit: ++ DBG_8192C("%s, Open net dev failed \n",__FUNCTION__); ++ return (-1); ++} ++#endif ++ ++static int rtw_suspend(struct usb_interface *pusb_intf, pm_message_t message) ++{ ++ struct net_device *pnetdev=usb_get_intfdata(pusb_intf); ++ _adapter *padapter = (_adapter*)rtw_netdev_priv(pnetdev); ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ struct pwrctrl_priv *pwrpriv = &padapter->pwrctrlpriv; ++ struct usb_device *usb_dev = interface_to_usbdev(pusb_intf); ++ struct wowlan_ioctl_param poidparam; ++ _func_enter_; ++ ++ if((!padapter->bup) || (padapter->bDriverStopped)||(padapter->bSurpriseRemoved)) ++ { ++ DBG_8192C("padapter->bup=%d bDriverStopped=%d bSurpriseRemoved = %d\n", ++ padapter->bup, padapter->bDriverStopped,padapter->bSurpriseRemoved); ++ return 0; ++ } ++ ++ DBG_8192C("########### rtw_suspend #################\n"); ++ ++ if(padapter)//system suspend ++ { ++ if(pwrpriv->bInternalAutoSuspend ) ++ { ++ #ifdef CONFIG_AUTOSUSPEND ++ #ifdef SUPPORT_HW_RFOFF_DETECTED ++ // The FW command register update must after MAC and FW init ready. ++ if((padapter->bFWReady) && ( padapter->pwrctrlpriv.bHWPwrPindetect ) && (padapter->registrypriv.usbss_enable )) ++ { ++ u8 bOpen = _TRUE; ++ rtw_interface_ps_func(padapter,HAL_USB_SELECT_SUSPEND,&bOpen); ++ //rtl8192c_set_FwSelectSuspend_cmd(padapter,_TRUE ,500);//note fw to support hw power down ping detect ++ } ++ #endif ++ #endif ++ } ++ pwrpriv->bInSuspend = _TRUE; ++ rtw_cancel_all_timer(padapter); ++ LeaveAllPowerSaveMode(padapter); ++ ++ _enter_pwrlock(&pwrpriv->lock); ++ //padapter->net_closed = _TRUE; ++ //s1. ++ if(pnetdev) ++ { ++ netif_carrier_off(pnetdev); ++ netif_stop_queue(pnetdev); ++ } ++#ifdef CONFIG_WOWLAN ++ if(padapter->pwrctrlpriv.bSupportRemoteWakeup==_TRUE&&padapter->pwrctrlpriv.wowlan_mode==_TRUE){ ++ u8 ps_mode=PS_MODE_MIN; ++ //set H2C command ++ poidparam.subcode=WOWLAN_ENABLE; ++ padapter->HalFunc.SetHwRegHandler(padapter,HW_VAR_WOWLAN,(u8 *)&poidparam); ++ padapter->HalFunc.SetHwRegHandler(padapter, HW_VAR_H2C_FW_PWRMODE, &ps_mode); ++ rtw_set_rpwm(padapter, PS_STATE_S2); ++ } ++ else ++#endif //CONFIG_WOWLAN ++ { ++ //s2. ++ //s2-1. issue rtw_disassoc_cmd to fw ++ disconnect_hdl(padapter, NULL); ++ //rtw_disassoc_cmd(padapter); ++ } ++ ++ ++#ifdef CONFIG_LAYER2_ROAMING_RESUME ++ if(check_fwstate(pmlmepriv, WIFI_STATION_STATE) && check_fwstate(pmlmepriv, _FW_LINKED) ) ++ { ++ //printk("%s:%d assoc_ssid:%s\n", __FUNCTION__, __LINE__, pmlmepriv->assoc_ssid.Ssid); ++ DBG_871X("%s:%d %s(" MAC_FMT "), length:%d assoc_ssid.length:%d\n",__FUNCTION__, __LINE__, ++ pmlmepriv->cur_network.network.Ssid.Ssid, ++ MAC_ARG(pmlmepriv->cur_network.network.MacAddress), ++ pmlmepriv->cur_network.network.Ssid.SsidLength, ++ pmlmepriv->assoc_ssid.SsidLength); ++ ++ pmlmepriv->to_roaming = 1; ++ } ++#endif ++ //s2-2. indicate disconnect to os ++ rtw_indicate_disconnect(padapter); ++ //s2-3. ++ rtw_free_assoc_resources(padapter, 1); ++#ifdef CONFIG_AUTOSUSPEND ++ if(!pwrpriv->bInternalAutoSuspend ) ++#endif ++ //s2-4. ++ rtw_free_network_queue(padapter, _TRUE); ++ ++ rtw_dev_unload(padapter); ++#ifdef CONFIG_AUTOSUSPEND ++ pwrpriv->rf_pwrstate = rf_off; ++ pwrpriv->bips_processing = _FALSE; ++#endif ++ _exit_pwrlock(&pwrpriv->lock); ++ ++ if(check_fwstate(pmlmepriv, _FW_UNDER_SURVEY)) ++ rtw_indicate_scan_done(padapter, 1); ++ ++ if(check_fwstate(pmlmepriv, _FW_UNDER_LINKING)) ++ rtw_indicate_disconnect(padapter); ++ } ++ else ++ goto error_exit; ++ ++ DBG_871X("########### rtw_suspend done #################\n"); ++ ++ _func_exit_; ++ return 0; ++ ++error_exit: ++ DBG_871X("########### rtw_suspend fail !! #################\n"); ++ return (-1); ++ ++} ++ ++static int rtw_resume(struct usb_interface *pusb_intf) ++{ ++ struct net_device *pnetdev=usb_get_intfdata(pusb_intf); ++ _adapter *padapter = (_adapter*)rtw_netdev_priv(pnetdev); ++ struct pwrctrl_priv *pwrpriv = &padapter->pwrctrlpriv; ++ int ret = 0; ++ ++ if(pwrpriv->bInternalAutoSuspend ){ ++ ret = rtw_resume_process(pusb_intf); ++ } else { ++#ifdef CONFIG_RESUME_IN_WORKQUEUE ++ rtw_resume_in_workqueue(pwrpriv); ++#elif defined(CONFIG_HAS_EARLYSUSPEND) || defined(CONFIG_ANDROID_POWER) ++ if(rtw_is_earlysuspend_registered(pwrpriv)) { ++ //jeff: bypass resume here, do in late_resume ++ pwrpriv->do_late_resume = _TRUE; ++ } else { ++ ret = rtw_resume_process(pusb_intf); ++ } ++#else // Normal resume process ++ ret = rtw_resume_process(pusb_intf); ++#endif //CONFIG_RESUME_IN_WORKQUEUE ++ } ++ ++ return ret; ++ ++} ++ ++ ++int rtw_resume_process(struct usb_interface *pusb_intf) ++{ ++ struct net_device *pnetdev; ++ struct usb_device *usb_dev; ++ _adapter *padapter; ++ struct pwrctrl_priv *pwrpriv; ++ ++ _func_enter_; ++ ++ DBG_8192C("########### rtw_resume #################\n"); ++ ++ if(pusb_intf) { ++ pnetdev=usb_get_intfdata(pusb_intf); ++ usb_dev = interface_to_usbdev(pusb_intf); ++ } else { ++ goto error_exit; ++ } ++ ++ padapter = (_adapter*)rtw_netdev_priv(pnetdev); ++ pwrpriv = &padapter->pwrctrlpriv; ++ ++ if(padapter)//system resume ++ { ++ _enter_pwrlock(&pwrpriv->lock); ++ rtw_reset_drv_sw(padapter); ++ pwrpriv->bkeepfwalive = _FALSE; ++ ++ DBG_8192C("bkeepfwalive(%x)\n",pwrpriv->bkeepfwalive); ++ if(pm_netdev_open(pnetdev,_TRUE) != 0) ++ goto error_exit; ++ ++ netif_device_attach(pnetdev); ++ netif_carrier_on(pnetdev); ++ ++#ifdef CONFIG_AUTOSUSPEND ++ if(pwrpriv->bInternalAutoSuspend ) ++ { ++ #ifdef CONFIG_AUTOSUSPEND ++ #ifdef SUPPORT_HW_RFOFF_DETECTED ++ // The FW command register update must after MAC and FW init ready. ++ if((padapter->bFWReady) && ( padapter->pwrctrlpriv.bHWPwrPindetect ) && (padapter->registrypriv.usbss_enable )) ++ { ++ //rtl8192c_set_FwSelectSuspend_cmd(padapter,_FALSE ,500);//note fw to support hw power down ping detect ++ u8 bOpen = _FALSE; ++ rtw_interface_ps_func(padapter,HAL_USB_SELECT_SUSPEND,&bOpen); ++ } ++ #endif ++ #endif ++ ++ pwrpriv->bInternalAutoSuspend = _FALSE; ++ pwrpriv->brfoffbyhw = _FALSE; ++ { ++ DBG_8192C("enc_algorithm(%x),wepkeymask(%x)\n", ++ padapter->securitypriv.dot11PrivacyAlgrthm,pwrpriv->wepkeymask); ++ if( (_WEP40_ == padapter->securitypriv.dot11PrivacyAlgrthm) || ++ (_WEP104_ == padapter->securitypriv.dot11PrivacyAlgrthm)) ++ { ++ sint keyid; ++ ++ for(keyid=0;keyid<4;keyid++){ ++ if(pwrpriv->wepkeymask & BIT(keyid)) { ++ if(keyid == padapter->securitypriv.dot11PrivacyKeyIndex) ++ rtw_set_key(padapter,&padapter->securitypriv, keyid, 1); ++ else ++ rtw_set_key(padapter,&padapter->securitypriv, keyid, 0); ++ } ++ } ++ } ++ } ++ } ++#endif ++ _exit_pwrlock(&pwrpriv->lock); ++ } ++ else ++ { ++ goto error_exit; ++ } ++ ++ if( padapter->pid[1]!=0) { ++ DBG_871X("pid[1]:%d\n",padapter->pid[1]); ++ rtw_signal_process(padapter->pid[1], SIGUSR2); ++ } ++ ++ #ifdef CONFIG_LAYER2_ROAMING_RESUME ++ rtw_roaming(padapter, NULL); ++ #endif ++ ++ DBG_871X("########### rtw_resume done#################\n"); ++ ++ #ifdef CONFIG_RESUME_IN_WORKQUEUE ++ rtw_unlock_suspend(); ++ #endif //CONFIG_RESUME_IN_WORKQUEUE ++ ++ _func_exit_; ++ ++ return 0; ++error_exit: ++ DBG_8192C("%s, Open net dev failed \n",__FUNCTION__); ++ ++ DBG_871X("########### rtw_resume done with error#################\n"); ++ ++ #ifdef CONFIG_RESUME_IN_WORKQUEUE ++ rtw_unlock_suspend(); ++ #endif //CONFIG_RESUME_IN_WORKQUEUE ++ ++ _func_exit_; ++ ++ return (-1); ++} ++ ++#ifdef CONFIG_AUTOSUSPEND ++void autosuspend_enter(_adapter* padapter) ++{ ++ struct pwrctrl_priv *pwrpriv = &padapter->pwrctrlpriv; ++ pwrpriv->bInternalAutoSuspend = _TRUE; ++ pwrpriv->bips_processing = _TRUE; ++ ++ DBG_8192C("==>autosuspend_enter...........\n"); ++ ++ if(rf_off == pwrpriv->change_rfpwrstate ) ++ { ++ #if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,35)) ++ usb_enable_autosuspend(padapter->dvobjpriv.pusbdev); ++ #else ++ padapter->dvobjpriv.pusbdev->autosuspend_disabled = 0;//autosuspend disabled by the user ++ #endif ++ ++ #if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,33)) ++ usb_autopm_put_interface(padapter->dvobjpriv.pusbintf); ++ #elif (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,20)) ++ usb_autopm_enable(padapter->dvobjpriv.pusbintf); ++ #else ++ usb_autosuspend_device(padapter->dvobjpriv.pusbdev, 1); ++ #endif ++ } ++ #if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,32)) ++ DBG_8192C("...pm_usage_cnt(%d).....\n",atomic_read(&(padapter->dvobjpriv.pusbintf->pm_usage_cnt))); ++ #else ++ DBG_8192C("...pm_usage_cnt(%d).....\n",padapter->dvobjpriv.pusbintf->pm_usage_cnt); ++ #endif ++ ++} ++int autoresume_enter(_adapter* padapter) ++{ ++ int result = _SUCCESS; ++ struct pwrctrl_priv *pwrpriv = &padapter->pwrctrlpriv; ++ struct security_priv* psecuritypriv=&(padapter->securitypriv); ++ struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; ++ struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); ++ ++ ++ DBG_8192C("====> autoresume_enter \n"); ++ ++ if(rf_off == pwrpriv->rf_pwrstate ) ++ { ++ pwrpriv->ps_flag = _FALSE; ++ #if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,33)) ++ if (usb_autopm_get_interface( padapter->dvobjpriv.pusbintf) < 0) ++ { ++ DBG_8192C( "can't get autopm: %d\n", result); ++ result = _FAIL; ++ goto error_exit; ++ } ++ #elif (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,20)) ++ usb_autopm_disable(padapter->dvobjpriv.pusbintf); ++ #else ++ usb_autoresume_device(padapter->dvobjpriv.pusbdev, 1); ++ #endif ++ ++ #if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,32)) ++ DBG_8192C("...pm_usage_cnt(%d).....\n",atomic_read(&(padapter->dvobjpriv.pusbintf->pm_usage_cnt))); ++ #else ++ DBG_8192C("...pm_usage_cnt(%d).....\n",padapter->dvobjpriv.pusbintf->pm_usage_cnt); ++ #endif ++ } ++ DBG_8192C("<==== autoresume_enter \n"); ++error_exit: ++ ++ return result; ++} ++#endif ++ ++extern char* ifname; ++/* ++ * drv_init() - a device potentially for us ++ * ++ * notes: drv_init() is called when the bus driver has located a card for us to support. ++ * We accept the new device by returning 0. ++*/ ++ ++_adapter *rtw_sw_export = NULL; ++ ++static int rtw_drv_init(struct usb_interface *pusb_intf, const struct usb_device_id *pdid) ++{ ++ int i; ++ ++ uint status; ++ _adapter *padapter = NULL; ++ struct dvobj_priv *pdvobjpriv; ++ struct net_device *pnetdev; ++ ++ RT_TRACE(_module_hci_intfs_c_, _drv_err_, ("+rtw_drv_init\n")); ++ //DBG_8192C("+rtw_drv_init\n"); ++ ++ //2009.8.13, by Thomas ++ // In this probe function, O.S. will provide the usb interface pointer to driver. ++ // We have to increase the reference count of the usb device structure by using the usb_get_dev function. ++ usb_get_dev(interface_to_usbdev(pusb_intf)); ++ ++ //step 0. ++ process_spec_devid(pdid); ++ ++ //step 1. set USB interface data ++ // init data ++ pnetdev = rtw_init_netdev(NULL); ++ if (!pnetdev) ++ goto error; ++ ++ SET_NETDEV_DEV(pnetdev, &pusb_intf->dev); ++ ++ padapter = rtw_netdev_priv(pnetdev); ++ padapter->bDriverStopped=_TRUE; ++ pdvobjpriv = &padapter->dvobjpriv; ++ pdvobjpriv->padapter = padapter; ++ pdvobjpriv->pusbintf = pusb_intf ; ++ pdvobjpriv->pusbdev = interface_to_usbdev(pusb_intf); ++ ++#ifdef CONFIG_IOCTL_CFG80211 ++ rtw_wdev_alloc(padapter, &pusb_intf->dev); ++#endif //CONFIG_IOCTL_CFG80211 ++ ++ ++ // set data ++ usb_set_intfdata(pusb_intf, pnetdev); ++ ++ //set interface_type to usb ++ padapter->interface_type = RTW_USB; ++ ++ //step 1-1., decide the chip_type via vid/pid ++ decide_chip_type_by_usb_device_id(padapter, pdid); ++ ++ //step 2. ++ if(padapter->chip_type == RTL8188C_8192C) ++ { ++#ifdef CONFIG_RTL8192C ++ rtl8192cu_set_hal_ops(padapter); ++#endif ++ } ++ else if(padapter->chip_type == RTL8192D) ++ { ++#ifdef CONFIG_RTL8192D ++ rtl8192du_set_hal_ops(padapter); ++#endif ++ } ++ else ++ { ++ DBG_8192C("Detect NULL_CHIP_TYPE\n"); ++ status = _FAIL; ++ goto error; ++ } ++ ++ //step 3. initialize the dvobj_priv ++ padapter->dvobj_init=&usb_dvobj_init; ++ padapter->dvobj_deinit=&usb_dvobj_deinit; ++ padapter->intf_start=&usb_intf_start; ++ padapter->intf_stop=&usb_intf_stop; ++ ++ //step 3. ++ //initialize the dvobj_priv ,include Chip version ++ if (padapter->dvobj_init == NULL){ ++ RT_TRACE(_module_hci_intfs_c_,_drv_err_,("\n Initialize dvobjpriv.dvobj_init error!!!\n")); ++ goto error; ++ } ++ ++ status = padapter->dvobj_init(padapter); ++ if (status != _SUCCESS) { ++ RT_TRACE(_module_hci_intfs_c_, _drv_err_, ("initialize device object priv Failed!\n")); ++ goto error; ++ } ++ ++ //step 4. read efuse/eeprom data and get mac_addr ++ intf_read_chip_info(padapter); ++ ++ //step 5. ++ status = rtw_init_drv_sw(padapter); ++ if(status ==_FAIL){ ++ RT_TRACE(_module_hci_intfs_c_,_drv_err_,("Initialize driver software resource Failed!\n")); ++ goto error; ++ } ++ ++#ifdef CONFIG_PM ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,18)) ++ if(padapter->pwrctrlpriv.bSupportRemoteWakeup) ++ { ++ pdvobjpriv->pusbdev->do_remote_wakeup=1; ++ pusb_intf->needs_remote_wakeup = 1; ++ device_init_wakeup(&pusb_intf->dev, 1); ++ DBG_8192C("\n padapter->pwrctrlpriv.bSupportRemoteWakeup~~~~~~\n"); ++ DBG_8192C("\n padapter->pwrctrlpriv.bSupportRemoteWakeup~~~[%d]~~~\n",device_may_wakeup(&pusb_intf->dev)); ++ } ++#endif ++#endif ++ ++#ifdef CONFIG_AUTOSUSPEND ++ if( padapter->registrypriv.power_mgnt != PS_MODE_ACTIVE ) ++ { ++ if(padapter->registrypriv.usbss_enable ){ /* autosuspend (2s delay) */ ++ #if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,38)) ++ pdvobjpriv->pusbdev->dev.power.autosuspend_delay = 0 * HZ;//15 * HZ; idle-delay time ++ #else ++ pdvobjpriv->pusbdev->autosuspend_delay = 0 * HZ;//15 * HZ; idle-delay time ++ #endif ++ ++ #if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,35)) ++ usb_enable_autosuspend(padapter->dvobjpriv.pusbdev); ++ #elif (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,22) && LINUX_VERSION_CODE<=KERNEL_VERSION(2,6,34)) ++ padapter->bDisableAutosuspend = padapter->dvobjpriv.pusbdev->autosuspend_disabled ; ++ padapter->dvobjpriv.pusbdev->autosuspend_disabled = 0;//autosuspend disabled by the user ++ #endif ++ ++ usb_autopm_get_interface(padapter->dvobjpriv.pusbintf );//init pm_usage_cnt ,let it start from 1 ++ ++ #if (LINUX_VERSION_CODE>=KERNEL_VERSION(2,6,32)) ++ DBG_8192C("%s...pm_usage_cnt(%d).....\n",__FUNCTION__,atomic_read(&(pdvobjpriv->pusbintf ->pm_usage_cnt))); ++ #else ++ DBG_8192C("%s...pm_usage_cnt(%d).....\n",__FUNCTION__,pdvobjpriv->pusbintf ->pm_usage_cnt); ++ #endif ++ } ++ } ++#endif ++ // alloc dev name after read efuse. ++ rtw_init_netdev_name(pnetdev, ifname); ++ ++ rtw_macaddr_cfg(padapter->eeprompriv.mac_addr); ++ ++ _rtw_memcpy(pnetdev->dev_addr, padapter->eeprompriv.mac_addr, ETH_ALEN); ++ DBG_8192C("MAC Address from pnetdev->dev_addr= " MAC_FMT "\n", MAC_ARG(pnetdev->dev_addr)); ++ ++ ++ //step 6. ++ /* Tell the network stack we exist */ ++ if (register_netdev(pnetdev) != 0) { ++ RT_TRACE(_module_hci_intfs_c_,_drv_err_,("register_netdev() failed\n")); ++ goto error; ++ } ++ ++ RT_TRACE(_module_hci_intfs_c_,_drv_err_,("-drv_init - Adapter->bDriverStopped=%d, Adapter->bSurpriseRemoved=%d\n",padapter->bDriverStopped, padapter->bSurpriseRemoved)); ++ RT_TRACE(_module_hci_intfs_c_,_drv_err_,("-871x_drv - drv_init, success!\n")); ++ //DBG_8192C("-871x_drv - drv_init, success!\n"); ++ ++#ifdef CONFIG_PROC_DEBUG ++#ifdef RTK_DMP_PLATFORM ++ rtw_proc_init_one(pnetdev); ++#endif ++#endif ++ ++#ifdef CONFIG_HOSTAPD_MLME ++ hostapd_mode_init(padapter); ++#endif ++ ++#ifdef CONFIG_PLATFORM_RTD2880B ++ DBG_8192C("wlan link up\n"); ++ rtd2885_wlan_netlink_sendMsg("linkup", "8712"); ++#endif ++ ++ ++#ifdef CONFIG_GLOBAL_UI_PID ++ if(ui_pid[1]!=0) { ++ DBG_871X("ui_pid[1]:%d\n",ui_pid[1]); ++ rtw_signal_process(ui_pid[1], SIGUSR2); ++ } ++#endif ++#ifdef CONFIG_INTEL_PROXIM ++ rtw_sw_export=padapter; ++#endif ++ ++ DBG_8192C("bDriverStopped:%d, bSurpriseRemoved:%d, bup:%d, hw_init_completed:%d\n" ++ ,padapter->bDriverStopped ++ ,padapter->bSurpriseRemoved ++ ,padapter->bup ++ ,padapter->hw_init_completed ++ ); ++ ++ return 0; ++ ++error: ++ ++ usb_put_dev(interface_to_usbdev(pusb_intf));//decrease the reference count of the usb device structure if driver fail on initialzation ++ ++ usb_set_intfdata(pusb_intf, NULL); ++ ++ usb_dvobj_deinit(padapter); ++ ++ if (pnetdev) ++ { ++ //unregister_netdev(pnetdev); ++ rtw_free_netdev(pnetdev); ++ } ++ ++ RT_TRACE(_module_hci_intfs_c_,_drv_err_,("-871x_usb - drv_init, fail!\n")); ++ //DBG_8192C("-871x_usb - drv_init, fail!\n"); ++ ++ return -ENODEV; ++} ++ ++/* ++ * dev_remove() - our device is being removed ++*/ ++//rmmod module & unplug(SurpriseRemoved) will call r871xu_dev_remove() => how to recognize both ++static void rtw_dev_remove(struct usb_interface *pusb_intf) ++{ ++ struct net_device *pnetdev=usb_get_intfdata(pusb_intf); ++ _adapter *padapter = (_adapter*)rtw_netdev_priv(pnetdev); ++ struct mlme_priv *pmlmepriv= &padapter->mlmepriv; ++ struct dvobj_priv *pdvobjpriv = &padapter->dvobjpriv; ++ u8 bResetDevice = _FALSE; ++ ++_func_exit_; ++ ++ usb_set_intfdata(pusb_intf, NULL); ++ ++ if(padapter) ++ { ++ ++#ifdef CONFIG_IOCTL_CFG80211 ++ struct wireless_dev *wdev = padapter->rtw_wdev; ++#endif //CONFIG_IOCTL_CFG80211 ++ ++ DBG_8192C("+rtw_dev_remove\n"); ++ RT_TRACE(_module_hci_intfs_c_,_drv_err_,("+dev_remove()\n")); ++#if defined(CONFIG_HAS_EARLYSUSPEND ) || defined(CONFIG_ANDROID_POWER) ++ rtw_unregister_early_suspend(&padapter->pwrctrlpriv); ++#endif ++ LeaveAllPowerSaveMode(padapter); ++ ++ if(check_fwstate(pmlmepriv, _FW_LINKED)) ++ disconnect_hdl(padapter, NULL); ++ ++ if(drvpriv.drv_registered == _TRUE) ++ { ++ //DBG_8192C("r871xu_dev_remove():padapter->bSurpriseRemoved == _TRUE\n"); ++ padapter->bSurpriseRemoved = _TRUE; ++ } ++ /*else ++ { ++ //DBG_8192C("r871xu_dev_remove():module removed\n"); ++ padapter->hw_init_completed = _FALSE; ++ }*/ ++ ++#ifdef CONFIG_AP_MODE ++ free_mlme_ap_info(padapter); ++#ifdef CONFIG_HOSTAPD_MLME ++ hostapd_mode_unload(padapter); ++#endif //CONFIG_HOSTAPD_MLME ++#endif //CONFIG_AP_MODE ++ ++ if(padapter->DriverState != DRIVER_DISAPPEAR) ++ { ++ if(pnetdev) { ++ unregister_netdev(pnetdev); //will call netdev_close() ++#ifdef CONFIG_PROC_DEBUG ++ rtw_proc_remove_one(pnetdev); ++#endif ++ } ++ } ++ ++ rtw_cancel_all_timer(padapter); ++#ifdef CONFIG_WOWLAN ++ padapter->pwrctrlpriv.wowlan_mode=_FALSE; ++#endif //CONFIG_WOWLAN ++ rtw_dev_unload(padapter); ++ ++ DBG_8192C("+r871xu_dev_remove, hw_init_completed=%d\n", padapter->hw_init_completed); ++ ++ //Modify condition for 92DU DMDP 2010.11.18, by Thomas ++ //move code to here, avoid access null pointer. 2011.05.25. ++ if((pdvobjpriv->NumInterfaces != 2) || (pdvobjpriv->InterfaceNumber == 1)) ++ bResetDevice = _TRUE; ++ ++ //s6. ++ if(padapter->dvobj_deinit) ++ { ++ padapter->dvobj_deinit(padapter); ++ } ++ else ++ { ++ RT_TRACE(_module_hci_intfs_c_,_drv_err_,("Initialize hcipriv.hci_priv_init error!!!\n")); ++ } ++ ++ //after rtw_free_drv_sw(), padapter has beed freed, don't refer to it. ++ rtw_free_drv_sw(padapter); ++ ++#ifdef CONFIG_IOCTL_CFG80211 ++ rtw_wdev_free(wdev); ++#endif //CONFIG_IOCTL_CFG80211 ++ ++ } ++ ++ usb_put_dev(interface_to_usbdev(pusb_intf));//decrease the reference count of the usb device structure when disconnect ++ ++ //If we didn't unplug usb dongle and remove/insert modlue, driver fails on sitesurvey for the first time when device is up . ++ //Reset usb port for sitesurvey fail issue. 2009.8.13, by Thomas ++ if(_TRUE == bResetDevice) ++ { ++ if(interface_to_usbdev(pusb_intf)->state != USB_STATE_NOTATTACHED) ++ { ++ DBG_8192C("usb attached..., try to reset usb device\n"); ++ usb_reset_device(interface_to_usbdev(pusb_intf)); ++ } ++ } ++ ++ RT_TRACE(_module_hci_intfs_c_,_drv_err_,("-dev_remove()\n")); ++ DBG_8192C("-r871xu_dev_remove, done\n"); ++ ++#ifdef CONFIG_PLATFORM_RTD2880B ++ DBG_8192C("wlan link down\n"); ++ rtd2885_wlan_netlink_sendMsg("linkdown", "8712"); ++#endif ++#ifdef CONFIG_INTEL_PROXIM ++ rtw_sw_export=NULL; ++#endif ++ #ifdef DBG_MEM_ALLOC ++ rtw_dump_mem_stat (); ++ #endif ++_func_exit_; ++ ++ return; ++ ++} ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,24)) ++extern int console_suspend_enabled; ++#endif ++ ++static int __init rtw_drv_entry(void) ++{ ++#ifdef CONFIG_PLATFORM_RTK_DMP ++ u32 tmp; ++ tmp=readl((volatile unsigned int*)0xb801a608); ++ tmp &= 0xffffff00; ++ tmp |= 0x55; ++ writel(tmp,(volatile unsigned int*)0xb801a608);//write dummy register for 1055 ++#endif ++ ++ ++ RT_TRACE(_module_hci_intfs_c_,_drv_err_,("+rtw_drv_entry\n")); ++ ++ DBG_871X("rtw driver version=%s \n", DRIVERVERSION); ++ DBG_871X("Build at: %s %s\n", __DATE__, __TIME__); ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,24)) ++ //console_suspend_enabled=0; ++#endif ++ ++ rtw_suspend_lock_init(); ++ ++ drvpriv.drv_registered = _TRUE; ++ return usb_register(&drvpriv.rtw_usb_drv); ++} ++ ++static void __exit rtw_drv_halt(void) ++{ ++ RT_TRACE(_module_hci_intfs_c_,_drv_err_,("+rtw_drv_halt\n")); ++ DBG_8192C("+rtw_drv_halt\n"); ++ ++ rtw_suspend_lock_uninit(); ++ ++ drvpriv.drv_registered = _FALSE; ++ usb_deregister(&drvpriv.rtw_usb_drv); ++ DBG_8192C("-rtw_drv_halt\n"); ++} ++ ++ ++module_init(rtw_drv_entry); ++module_exit(rtw_drv_halt); ++ ++ ++/* ++init (driver module)-> r8712u_drv_entry ++probe (sd device)-> r871xu_drv_init(dev_init) ++open (net_device) ->netdev_open ++close (net_device) ->netdev_close ++remove (sd device) ->r871xu_dev_remove ++exit (driver module)-> r8712u_drv_halt ++*/ ++ ++ ++/* ++r8711s_drv_entry() ++r8711u_drv_entry() ++r8712s_drv_entry() ++r8712u_drv_entry() ++*/ ++#ifdef CONFIG_INTEL_PROXIM ++_adapter *rtw_usb_get_sw_pointer(void) ++{ ++ return rtw_sw_export; ++} ++EXPORT_SYMBOL(rtw_usb_get_sw_pointer); ++#endif //CONFIG_INTEL_PROXIM ++ +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/os_dep/linux/xmit_linux.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/os_dep/linux/xmit_linux.c 2013-07-26 19:36:07.000000000 +0000 +@@ -0,0 +1,367 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++******************************************************************************/ ++#define _XMIT_OSDEP_C_ ++ ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++ ++uint rtw_remainder_len(struct pkt_file *pfile) ++{ ++ return (pfile->buf_len - ((SIZE_PTR)(pfile->cur_addr) - (SIZE_PTR)(pfile->buf_start))); ++} ++ ++void _rtw_open_pktfile (_pkt *pktptr, struct pkt_file *pfile) ++{ ++_func_enter_; ++ ++ pfile->pkt = pktptr; ++ pfile->cur_addr = pfile->buf_start = pktptr->data; ++ pfile->pkt_len = pfile->buf_len = pktptr->len; ++ ++ pfile->cur_buffer = pfile->buf_start ; ++ ++_func_exit_; ++} ++ ++uint _rtw_pktfile_read (struct pkt_file *pfile, u8 *rmem, uint rlen) ++{ ++ uint len = 0; ++ ++_func_enter_; ++ ++ len = rtw_remainder_len(pfile); ++ len = (rlen > len)? len: rlen; ++ ++ if(rmem) ++ skb_copy_bits(pfile->pkt, pfile->buf_len-pfile->pkt_len, rmem, len); ++ ++ pfile->cur_addr += len; ++ pfile->pkt_len -= len; ++ ++_func_exit_; ++ ++ return len; ++} ++ ++sint rtw_endofpktfile(struct pkt_file *pfile) ++{ ++_func_enter_; ++ ++ if (pfile->pkt_len == 0) { ++_func_exit_; ++ return _TRUE; ++ } ++ ++_func_exit_; ++ ++ return _FALSE; ++} ++ ++void rtw_set_tx_chksum_offload(_pkt *pkt, struct pkt_attrib *pattrib) ++{ ++ ++#ifdef CONFIG_TCP_CSUM_OFFLOAD_TX ++ struct sk_buff *skb = (struct sk_buff *)pkt; ++ pattrib->hw_tcp_csum = 0; ++ ++ if (skb->ip_summed == CHECKSUM_PARTIAL) { ++ if (skb_shinfo(skb)->nr_frags == 0) ++ { ++ const struct iphdr *ip = ip_hdr(skb); ++ if (ip->protocol == IPPROTO_TCP) { ++ // TCP checksum offload by HW ++ DBG_8192C("CHECKSUM_PARTIAL TCP\n"); ++ pattrib->hw_tcp_csum = 1; ++ //skb_checksum_help(skb); ++ } else if (ip->protocol == IPPROTO_UDP) { ++ //DBG_8192C("CHECKSUM_PARTIAL UDP\n"); ++#if 1 ++ skb_checksum_help(skb); ++#else ++ // Set UDP checksum = 0 to skip checksum check ++ struct udphdr *udp = skb_transport_header(skb); ++ udp->check = 0; ++#endif ++ } else { ++ DBG_8192C("%s-%d TCP CSUM offload Error!!\n", __FUNCTION__, __LINE__); ++ WARN_ON(1); /* we need a WARN() */ ++ } ++ } ++ else { // IP fragmentation case ++ DBG_8192C("%s-%d nr_frags != 0, using skb_checksum_help(skb);!!\n", __FUNCTION__, __LINE__); ++ skb_checksum_help(skb); ++ } ++ } ++#endif ++ ++} ++ ++int rtw_os_xmit_resource_alloc(_adapter *padapter, struct xmit_buf *pxmitbuf,u32 alloc_sz) ++{ ++#ifdef CONFIG_USB_HCI ++ int i; ++ struct dvobj_priv *pdvobjpriv = &padapter->dvobjpriv; ++ struct usb_device *pusbd = pdvobjpriv->pusbdev; ++ ++#ifdef CONFIG_USE_USB_BUFFER_ALLOC_TX ++ pxmitbuf->pallocated_buf = rtw_usb_buffer_alloc(pusbd, (size_t)alloc_sz, GFP_ATOMIC, &pxmitbuf->dma_transfer_addr); ++ pxmitbuf->pbuf = pxmitbuf->pallocated_buf; ++ if(pxmitbuf->pallocated_buf == NULL) ++ return _FAIL; ++#else // CONFIG_USE_USB_BUFFER_ALLOC_TX ++ ++ pxmitbuf->pallocated_buf = rtw_zmalloc(alloc_sz); ++ if (pxmitbuf->pallocated_buf == NULL) ++ { ++ return _FAIL; ++ } ++ ++ pxmitbuf->pbuf = (u8 *)N_BYTE_ALIGMENT((SIZE_PTR)(pxmitbuf->pallocated_buf), XMITBUF_ALIGN_SZ); ++ pxmitbuf->dma_transfer_addr = 0; ++ ++#endif // CONFIG_USE_USB_BUFFER_ALLOC_TX ++ ++ for(i=0; i<8; i++) ++ { ++ pxmitbuf->pxmit_urb[i] = usb_alloc_urb(0, GFP_KERNEL); ++ if(pxmitbuf->pxmit_urb[i] == NULL) ++ { ++ DBG_8192C("pxmitbuf->pxmit_urb[i]==NULL"); ++ return _FAIL; ++ } ++ ++ } ++#endif ++#ifdef CONFIG_PCI_HCI ++ pxmitbuf->pallocated_buf = rtw_zmalloc(alloc_sz); ++ if (pxmitbuf->pallocated_buf == NULL) ++ { ++ return _FAIL; ++ } ++ ++ pxmitbuf->pbuf = (u8 *)N_BYTE_ALIGMENT((SIZE_PTR)(pxmitbuf->pallocated_buf), XMITBUF_ALIGN_SZ); ++#endif ++ ++ return _SUCCESS; ++} ++ ++void rtw_os_xmit_resource_free(_adapter *padapter, struct xmit_buf *pxmitbuf,u32 free_sz) ++{ ++#ifdef CONFIG_USB_HCI ++ int i; ++ struct dvobj_priv *pdvobjpriv = &padapter->dvobjpriv; ++ struct usb_device *pusbd = pdvobjpriv->pusbdev; ++ ++ ++ for(i=0; i<8; i++) ++ { ++ if(pxmitbuf->pxmit_urb[i]) ++ { ++ //usb_kill_urb(pxmitbuf->pxmit_urb[i]); ++ usb_free_urb(pxmitbuf->pxmit_urb[i]); ++ } ++ } ++ ++#ifdef CONFIG_USE_USB_BUFFER_ALLOC_TX ++ rtw_usb_buffer_free(pusbd, (size_t)free_sz, pxmitbuf->pallocated_buf, pxmitbuf->dma_transfer_addr); ++ pxmitbuf->pallocated_buf = NULL; ++ pxmitbuf->dma_transfer_addr = 0; ++#else // CONFIG_USE_USB_BUFFER_ALLOC_TX ++ if(pxmitbuf->pallocated_buf) ++ rtw_mfree(pxmitbuf->pallocated_buf, free_sz); ++#endif // CONFIG_USE_USB_BUFFER_ALLOC_TX ++ ++#endif ++#ifdef CONFIG_PCI_HCI ++ if(pxmitbuf->pallocated_buf) ++ rtw_mfree(pxmitbuf->pallocated_buf, free_sz); ++#endif ++} ++ ++void rtw_os_pkt_complete(_adapter *padapter, _pkt *pkt) ++{ ++ if (netif_queue_stopped(padapter->pnetdev)) ++ netif_wake_queue(padapter->pnetdev); ++ ++ dev_kfree_skb_any(pkt); ++} ++ ++void rtw_os_xmit_complete(_adapter *padapter, struct xmit_frame *pxframe) ++{ ++ if(pxframe->pkt) ++ { ++ //RT_TRACE(_module_xmit_osdep_c_,_drv_err_,("linux : rtw_os_xmit_complete, dev_kfree_skb()\n")); ++ ++ //dev_kfree_skb_any(pxframe->pkt); ++ rtw_os_pkt_complete(padapter, pxframe->pkt); ++ ++ } ++ ++ pxframe->pkt = NULL; ++} ++ ++void rtw_os_xmit_schedule(_adapter *padapter) ++{ ++ _irqL irqL; ++ struct xmit_priv *pxmitpriv = &padapter->xmitpriv; ++ ++ _enter_critical_bh(&pxmitpriv->lock, &irqL); ++ ++ if(rtw_txframes_pending(padapter)) ++ { ++ tasklet_hi_schedule(&pxmitpriv->xmit_tasklet); ++ } ++ ++ _exit_critical_bh(&pxmitpriv->lock, &irqL); ++} ++ ++ ++ ++#ifdef CONFIG_TX_MCAST2UNI ++int rtw_mlcst2unicst(_adapter *padapter, struct sk_buff *skb) ++{ ++ struct sta_priv *pstapriv = &padapter->stapriv; ++ struct xmit_priv *pxmitpriv = &padapter->xmitpriv; ++ _irqL irqL; ++ _list *phead, *plist; ++ struct sk_buff *newskb; ++ struct sta_info *psta = NULL; ++ s32 res; ++ ++ _enter_critical_bh(&pstapriv->asoc_list_lock, &irqL); ++ phead = &pstapriv->asoc_list; ++ plist = get_next(phead); ++ ++ //free sta asoc_queue ++ while ((rtw_end_of_queue_search(phead, plist)) == _FALSE) ++ { ++ psta = LIST_CONTAINOR(plist, struct sta_info, asoc_list); ++ ++ plist = get_next(plist); ++ ++ /* avoid come from STA1 and send back STA1 */ ++ if (!memcmp(psta->hwaddr, &skb->data[6], 6)) ++ continue; ++ ++ newskb = skb_copy(skb, GFP_ATOMIC); ++ ++ if (newskb) { ++ memcpy(newskb->data, psta->hwaddr, 6); ++ res = rtw_xmit(padapter, &newskb); ++ if (res < 0) { ++ DBG_871X("%s()-%d: rtw_xmit() return error!\n", __FUNCTION__, __LINE__); ++ pxmitpriv->tx_drop++; ++ dev_kfree_skb_any(newskb); ++ } else ++ pxmitpriv->tx_pkts++; ++ } else { ++ DBG_871X("%s-%d: skb_copy() failed!\n", __FUNCTION__, __LINE__); ++ pxmitpriv->tx_drop++; ++ ++ _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL); ++ //dev_kfree_skb_any(skb); ++ return _FALSE; // Caller shall tx this multicast frame via normal way. ++ } ++ } ++ ++ _exit_critical_bh(&pstapriv->asoc_list_lock, &irqL); ++ dev_kfree_skb_any(skb); ++ return _TRUE; ++} ++#endif // CONFIG_TX_MCAST2UNI ++ ++ ++int rtw_xmit_entry(_pkt *pkt, _nic_hdl pnetdev) ++{ ++ _adapter *padapter = (_adapter *)rtw_netdev_priv(pnetdev); ++ struct xmit_priv *pxmitpriv = &padapter->xmitpriv; ++#ifdef CONFIG_TX_MCAST2UNI ++ struct mlme_priv *pmlmepriv = &padapter->mlmepriv; ++ extern int rtw_mc2u_disable; ++#endif // CONFIG_TX_MCAST2UNI ++ s32 res = 0; ++ int ret = 0; ++ ++_func_enter_; ++ ++ RT_TRACE(_module_rtl871x_mlme_c_, _drv_info_, ("+xmit_enry\n")); ++ ++ if (rtw_if_up(padapter) == _FALSE) { ++ RT_TRACE(_module_xmit_osdep_c_, _drv_err_, ("rtw_xmit_entry: rtw_if_up fail\n")); ++ #ifdef DBG_TX_DROP_FRAME ++ DBG_871X("DBG_TX_DROP_FRAME %s if_up fail\n", __FUNCTION__); ++ #endif ++ goto drop_packet; ++ } ++ ++#ifdef CONFIG_TX_MCAST2UNI ++ if ( !rtw_mc2u_disable ++ && check_fwstate(pmlmepriv, WIFI_AP_STATE) == _TRUE ++ && ( IP_MCAST_MAC(pkt->data) ++ || ICMPV6_MCAST_MAC(pkt->data) ) ++ ) ++ { ++ if ( pxmitpriv->free_xmitframe_cnt > (NR_XMITFRAME/4) ) { ++ res = rtw_mlcst2unicst(padapter, pkt); ++ if (res == _TRUE) { ++ goto exit; ++ } ++ } else { ++ //DBG_871X("Stop M2U(%d, %d)! ", pxmitpriv->free_xmitframe_cnt, pxmitpriv->free_xmitbuf_cnt); ++ //DBG_871X("!m2u ); ++ } ++ } ++#endif // CONFIG_TX_MCAST2UNI ++ ++ res = rtw_xmit(padapter, &pkt); ++ if (res < 0) { ++ #ifdef DBG_TX_DROP_FRAME ++ DBG_871X("DBG_TX_DROP_FRAME %s rtw_xmit fail\n", __FUNCTION__); ++ #endif ++ goto drop_packet; ++ } ++ pxmitpriv->tx_pkts++; ++ ++ RT_TRACE(_module_xmit_osdep_c_, _drv_info_, ("rtw_xmit_entry: tx_pkts=%d\n", (u32)pxmitpriv->tx_pkts)); ++ goto exit; ++ ++drop_packet: ++ pxmitpriv->tx_drop++; ++ dev_kfree_skb_any(pkt); ++ RT_TRACE(_module_xmit_osdep_c_, _drv_notice_, ("rtw_xmit_entry: drop, tx_drop=%d\n", (u32)pxmitpriv->tx_drop)); ++ ++exit: ++ ++_func_exit_; ++ ++ return 0; ++} ++ +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/os_dep/osdep_service.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/os_dep/osdep_service.c 2013-07-26 19:36:07.000000000 +0000 +@@ -0,0 +1,1555 @@ ++/****************************************************************************** ++ * ++ * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of version 2 of the GNU General Public License as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope that it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program; if not, write to the Free Software Foundation, Inc., ++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA ++ * ++ * ++ ******************************************************************************/ ++ ++ ++#define _OSDEP_SERVICE_C_ ++ ++#include ++#include ++#include ++#include ++#include ++ ++#ifdef RTK_DMP_PLATFORM ++#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,12)) ++#include ++#endif ++#endif ++ ++#define RT_TAG '1178' ++ ++#ifdef DBG_MEMORY_LEAK ++#ifdef PLATFORM_LINUX ++#include ++atomic_t _malloc_cnt = ATOMIC_INIT(0); ++atomic_t _malloc_size = ATOMIC_INIT(0); ++#endif ++#endif /* DBG_MEMORY_LEAK */ ++ ++ ++#if defined(PLATFORM_LINUX) ++/* ++* Translate the OS dependent @param error_code to OS independent RTW_STATUS_CODE ++* @return: one of RTW_STATUS_CODE ++*/ ++inline int RTW_STATUS_CODE(int error_code){ ++ if(error_code >=0) ++ return _SUCCESS; ++ ++ switch(error_code) { ++ //case -ETIMEDOUT: ++ // return RTW_STATUS_TIMEDOUT; ++ default: ++ return _FAIL; ++ } ++} ++#else ++inline int RTW_STATUS_CODE(int error_code){ ++ return error_code; ++} ++#endif ++ ++ ++inline u8* _rtw_vmalloc(u32 sz) ++{ ++ u8 *pbuf; ++#ifdef PLATFORM_LINUX ++ pbuf = vmalloc(sz); ++#endif ++ ++#ifdef PLATFORM_WINDOWS ++ NdisAllocateMemoryWithTag(&pbuf,sz, RT_TAG); ++#endif ++ ++#ifdef DBG_MEMORY_LEAK ++#ifdef PLATFORM_LINUX ++ if ( pbuf != NULL) { ++ atomic_inc(&_malloc_cnt); ++ atomic_add(sz, &_malloc_size); ++ } ++#endif ++#endif /* DBG_MEMORY_LEAK */ ++ ++ return pbuf; ++} ++ ++inline u8* _rtw_zvmalloc(u32 sz) ++{ ++ u8 *pbuf; ++#ifdef PLATFORM_LINUX ++ pbuf = _rtw_vmalloc(sz); ++ if (pbuf != NULL) ++ memset(pbuf, 0, sz); ++#endif ++ ++#ifdef PLATFORM_WINDOWS ++ NdisAllocateMemoryWithTag(&pbuf,sz, RT_TAG); ++ if (pbuf != NULL) ++ NdisFillMemory(pbuf, sz, 0); ++#endif ++ ++ return pbuf; ++} ++ ++inline void _rtw_vmfree(u8 *pbuf, u32 sz) ++{ ++#ifdef PLATFORM_LINUX ++ vfree(pbuf); ++#endif ++ ++#ifdef PLATFORM_WINDOWS ++ NdisFreeMemory(pbuf,sz, 0); ++#endif ++ ++#ifdef DBG_MEMORY_LEAK ++#ifdef PLATFORM_LINUX ++ atomic_dec(&_malloc_cnt); ++ atomic_sub(sz, &_malloc_size); ++#endif ++#endif /* DBG_MEMORY_LEAK */ ++} ++ ++u8* _rtw_malloc(u32 sz) ++{ ++ ++ u8 *pbuf=NULL; ++ ++#ifdef PLATFORM_LINUX ++#ifdef RTK_DMP_PLATFORM ++ if(sz > 0x4000) ++ pbuf = (u8 *)dvr_malloc(sz); ++ else ++#endif ++ pbuf = kmalloc(sz, /*GFP_KERNEL*/GFP_ATOMIC); ++ ++#endif ++ ++#ifdef PLATFORM_WINDOWS ++ ++ NdisAllocateMemoryWithTag(&pbuf,sz, RT_TAG); ++ ++#endif ++ ++#ifdef DBG_MEMORY_LEAK ++#ifdef PLATFORM_LINUX ++ if ( pbuf != NULL) { ++ atomic_inc(&_malloc_cnt); ++ atomic_add(sz, &_malloc_size); ++ } ++#endif ++#endif /* DBG_MEMORY_LEAK */ ++ ++ return pbuf; ++ ++} ++ ++ ++u8* _rtw_zmalloc(u32 sz) ++{ ++ u8 *pbuf = _rtw_malloc(sz); ++ ++ if (pbuf != NULL) { ++ ++#ifdef PLATFORM_LINUX ++ memset(pbuf, 0, sz); ++#endif ++ ++#ifdef PLATFORM_WINDOWS ++ NdisFillMemory(pbuf, sz, 0); ++#endif ++ ++ } ++ ++ return pbuf; ++ ++} ++ ++void _rtw_mfree(u8 *pbuf, u32 sz) ++{ ++ ++#ifdef PLATFORM_LINUX ++#ifdef RTK_DMP_PLATFORM ++ if(sz > 0x4000) ++ dvr_free(pbuf); ++ else ++#endif ++ kfree(pbuf); ++ ++#endif ++ ++#ifdef PLATFORM_WINDOWS ++ ++ NdisFreeMemory(pbuf,sz, 0); ++ ++#endif ++ ++#ifdef DBG_MEMORY_LEAK ++#ifdef PLATFORM_LINUX ++ atomic_dec(&_malloc_cnt); ++ atomic_sub(sz, &_malloc_size); ++#endif ++#endif /* DBG_MEMORY_LEAK */ ++ ++} ++ ++ ++#ifdef DBG_MEM_ALLOC ++ ++struct rtw_dbg_mem_stat { ++ ATOMIC_T vir_alloc; // the memory bytes we allocate now ++ ATOMIC_T vir_peak; // the peak memory bytes we allocate ++ ATOMIC_T vir_alloc_err; // the error times we fail to allocate memory ++ ++ ATOMIC_T phy_alloc; ++ ATOMIC_T phy_peak; ++ ATOMIC_T phy_alloc_err; ++} rtw_dbg_mem_stat; ++ ++enum { ++ MEM_STAT_VIR_ALLOC_SUCCESS, ++ MEM_STAT_VIR_ALLOC_FAIL, ++ MEM_STAT_VIR_FREE, ++ MEM_STAT_PHY_ALLOC_SUCCESS, ++ MEM_STAT_PHY_ALLOC_FAIL, ++ MEM_STAT_PHY_FREE ++}; ++ ++void rtw_dump_mem_stat (void) ++{ ++ int vir_alloc, vir_peak, vir_alloc_err, phy_alloc, phy_peak, phy_alloc_err; ++ ++ vir_alloc=ATOMIC_READ(&rtw_dbg_mem_stat.vir_alloc); ++ vir_peak=ATOMIC_READ(&rtw_dbg_mem_stat.vir_peak); ++ vir_alloc_err=ATOMIC_READ(&rtw_dbg_mem_stat.vir_alloc_err); ++ ++ phy_alloc=ATOMIC_READ(&rtw_dbg_mem_stat.phy_alloc); ++ phy_peak=ATOMIC_READ(&rtw_dbg_mem_stat.phy_peak); ++ phy_alloc_err=ATOMIC_READ(&rtw_dbg_mem_stat.phy_alloc_err); ++ ++ DBG_871X("vir_alloc:%d, vir_peak:%d,vir_alloc_err:%d, phy_alloc:%d, phy_peak:%d, phy_alloc_err:%d\n" ++ , vir_alloc, vir_peak, vir_alloc_err ++ , phy_alloc, phy_peak, phy_alloc_err ++ ); ++} ++ ++void rtw_update_mem_stat(u8 flag, u32 sz) ++{ ++ static u32 update_time = 0; ++ int peak, alloc; ++ ++ if(!update_time) { ++ ATOMIC_SET(&rtw_dbg_mem_stat.vir_alloc,0); ++ ATOMIC_SET(&rtw_dbg_mem_stat.vir_peak,0); ++ ATOMIC_SET(&rtw_dbg_mem_stat.vir_alloc_err,0); ++ ATOMIC_SET(&rtw_dbg_mem_stat.phy_alloc,0); ++ ATOMIC_SET(&rtw_dbg_mem_stat.phy_peak,0); ++ ATOMIC_SET(&rtw_dbg_mem_stat.phy_alloc_err,0); ++ } ++ ++ switch(flag) { ++ case MEM_STAT_VIR_ALLOC_SUCCESS: ++ alloc = ATOMIC_ADD_RETURN(&rtw_dbg_mem_stat.vir_alloc, sz); ++ peak=ATOMIC_READ(&rtw_dbg_mem_stat.vir_peak); ++ if (peak 5000) { ++ rtw_dump_mem_stat(); ++ update_time=rtw_get_current_time(); ++ } ++ ++ ++} ++ ++ ++inline u8* dbg_rtw_vmalloc(u32 sz, const char *func, int line) ++{ ++ u8 *p; ++ DBG_871X("DBG_MEM_ALLOC %s:%d %s(%d)\n", func, line, __FUNCTION__, (sz)); ++ ++ p=_rtw_vmalloc((sz)); ++ ++ rtw_update_mem_stat( ++ p ? MEM_STAT_VIR_ALLOC_SUCCESS : MEM_STAT_VIR_ALLOC_FAIL ++ , sz ++ ); ++ ++ return p; ++} ++ ++inline u8* dbg_rtw_zvmalloc(u32 sz, const char *func, int line) ++{ ++ u8 *p; ++ DBG_871X("DBG_MEM_ALLOC %s:%d %s(%d)\n", func, line, __FUNCTION__, (sz)); ++ ++ p=_rtw_zvmalloc((sz)); ++ ++ rtw_update_mem_stat( ++ p ? MEM_STAT_VIR_ALLOC_SUCCESS : MEM_STAT_VIR_ALLOC_FAIL ++ , sz ++ ); ++ ++ return p; ++} ++ ++inline void dbg_rtw_vmfree(u8 *pbuf, u32 sz, const char *func, int line) ++{ ++ DBG_871X("DBG_MEM_ALLOC %s:%d %s(%p,%d)\n", func, line, __FUNCTION__, (pbuf), (sz)); ++ ++ _rtw_vmfree((pbuf), (sz)); ++ ++ rtw_update_mem_stat( ++ MEM_STAT_VIR_FREE ++ , sz ++ ); ++ ++} ++ ++inline u8* dbg_rtw_malloc(u32 sz, const char *func, int line) ++{ ++ u8 *p; ++ ++ if((sz)>4096) ++ DBG_871X("DBG_MEM_ALLOC !!!!!!!!!!!!!! %s:%d %s(%d)\n", func, line, __FUNCTION__, (sz)); ++ ++ p=_rtw_malloc((sz)); ++ ++ rtw_update_mem_stat( ++ p ? MEM_STAT_PHY_ALLOC_SUCCESS : MEM_STAT_PHY_ALLOC_FAIL ++ , sz ++ ); ++ ++ return p; ++} ++ ++inline u8* dbg_rtw_zmalloc(u32 sz, const char *func, int line) ++{ ++ u8 *p; ++ ++ if((sz)>4096) ++ DBG_871X("DBG_MEM_ALLOC !!!!!!!!!!!!!! %s:%d %s(%d)\n", func, line, __FUNCTION__, (sz)); ++ ++ p = _rtw_zmalloc((sz)); ++ ++ rtw_update_mem_stat( ++ p ? MEM_STAT_PHY_ALLOC_SUCCESS : MEM_STAT_PHY_ALLOC_FAIL ++ , sz ++ ); ++ ++ return p; ++ ++} ++ ++inline void dbg_rtw_mfree(u8 *pbuf, u32 sz, const char *func, int line) ++{ ++ if((sz)>4096) ++ DBG_871X("DBG_MEM_ALLOC !!!!!!!!!!!!!! %s:%d %s(%p,%d)\n", func, line, __FUNCTION__, (pbuf), (sz)); ++ ++ _rtw_mfree((pbuf), (sz)); ++ ++ rtw_update_mem_stat( ++ MEM_STAT_PHY_FREE ++ , sz ++ ); ++} ++#endif ++ ++ ++void _rtw_memcpy(void* dst, void* src, u32 sz) ++{ ++ ++#ifdef PLATFORM_LINUX ++ ++ memcpy(dst, src, sz); ++ ++#endif ++ ++#ifdef PLATFORM_WINDOWS ++ ++ NdisMoveMemory(dst, src, sz); ++ ++#endif ++ ++} ++ ++int _rtw_memcmp(void *dst, void *src, u32 sz) ++{ ++ ++#ifdef PLATFORM_LINUX ++//under Linux/GNU/GLibc, the return value of memcmp for two same mem. chunk is 0 ++ ++ if (!(memcmp(dst, src, sz))) ++ return _TRUE; ++ else ++ return _FALSE; ++#endif ++ ++ ++#ifdef PLATFORM_WINDOWS ++//under Windows, the return value of NdisEqualMemory for two same mem. chunk is 1 ++ ++ if (NdisEqualMemory (dst, src, sz)) ++ return _TRUE; ++ else ++ return _FALSE; ++ ++#endif ++ ++ ++ ++} ++ ++void _rtw_memset(void *pbuf, int c, u32 sz) ++{ ++ ++#ifdef PLATFORM_LINUX ++ ++ memset(pbuf, c, sz); ++ ++#endif ++ ++#ifdef PLATFORM_WINDOWS ++#if 0 ++ NdisZeroMemory(pbuf, sz); ++ if (c != 0) memset(pbuf, c, sz); ++#else ++ NdisFillMemory(pbuf, sz, c); ++#endif ++#endif ++ ++} ++ ++void _rtw_init_listhead(_list *list) ++{ ++ ++#ifdef PLATFORM_LINUX ++ ++ INIT_LIST_HEAD(list); ++ ++#endif ++ ++#ifdef PLATFORM_WINDOWS ++ ++ NdisInitializeListHead(list); ++ ++#endif ++ ++} ++ ++ ++/* ++For the following list_xxx operations, ++caller must guarantee the atomic context. ++Otherwise, there will be racing condition. ++*/ ++u32 rtw_is_list_empty(_list *phead) ++{ ++ ++#ifdef PLATFORM_LINUX ++ ++ if (list_empty(phead)) ++ return _TRUE; ++ else ++ return _FALSE; ++ ++#endif ++ ++ ++#ifdef PLATFORM_WINDOWS ++ ++ if (IsListEmpty(phead)) ++ return _TRUE; ++ else ++ return _FALSE; ++ ++#endif ++ ++ ++} ++ ++ ++void rtw_list_insert_tail(_list *plist, _list *phead) ++{ ++ ++#ifdef PLATFORM_LINUX ++ ++ list_add_tail(plist, phead); ++ ++#endif ++ ++#ifdef PLATFORM_WINDOWS ++ ++ InsertTailList(phead, plist); ++ ++#endif ++ ++} ++ ++ ++/* ++ ++Caller must check if the list is empty before calling rtw_list_delete ++ ++*/ ++ ++ ++void _rtw_init_sema(_sema *sema, int init_val) ++{ ++ ++#ifdef PLATFORM_LINUX ++ ++ sema_init(sema, init_val); ++ ++#endif ++ ++#ifdef PLATFORM_OS_XP ++ ++ KeInitializeSemaphore(sema, init_val, SEMA_UPBND); // count=0; ++ ++#endif ++ ++#ifdef PLATFORM_OS_CE ++ if(*sema == NULL) ++ *sema = CreateSemaphore(NULL, init_val, SEMA_UPBND, NULL); ++#endif ++ ++} ++ ++void _rtw_free_sema(_sema *sema) ++{ ++ ++#ifdef PLATFORM_OS_CE ++ CloseHandle(*sema); ++#endif ++ ++} ++ ++void _rtw_up_sema(_sema *sema) ++{ ++ ++#ifdef PLATFORM_LINUX ++ ++ up(sema); ++ ++#endif ++ ++#ifdef PLATFORM_OS_XP ++ ++ KeReleaseSemaphore(sema, IO_NETWORK_INCREMENT, 1, FALSE ); ++ ++#endif ++ ++#ifdef PLATFORM_OS_CE ++ ReleaseSemaphore(*sema, 1, NULL ); ++#endif ++} ++ ++u32 _rtw_down_sema(_sema *sema) ++{ ++ ++#ifdef PLATFORM_LINUX ++ ++ if (down_interruptible(sema)) ++ return _FAIL; ++ else ++ return _SUCCESS; ++ ++#endif ++ ++#ifdef PLATFORM_OS_XP ++ ++ if(STATUS_SUCCESS == KeWaitForSingleObject(sema, Executive, KernelMode, TRUE, NULL)) ++ return _SUCCESS; ++ else ++ return _FAIL; ++#endif ++ ++#ifdef PLATFORM_OS_CE ++ if(WAIT_OBJECT_0 == WaitForSingleObject(*sema, INFINITE )) ++ return _SUCCESS; ++ else ++ return _FAIL; ++#endif ++} ++ ++ ++ ++void _rtw_mutex_init(_mutex *pmutex) ++{ ++#ifdef PLATFORM_LINUX ++ ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) ++ mutex_init(pmutex); ++#else ++ init_MUTEX(pmutex); ++#endif ++ ++#endif ++ ++#ifdef PLATFORM_OS_XP ++ ++ KeInitializeMutex(pmutex, 0); ++ ++#endif ++ ++#ifdef PLATFORM_OS_CE ++ *pmutex = CreateMutex( NULL, _FALSE, NULL); ++#endif ++} ++ ++ ++void _rtw_mutex_free(_mutex *pmutex) ++{ ++#ifdef PLATFORM_LINUX ++ ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37)) ++ mutex_destroy(pmutex); ++#else ++#endif ++ ++#endif ++ ++#ifdef PLATFORM_OS_XP ++ ++#endif ++ ++#ifdef PLATFORM_OS_CE ++ ++#endif ++} ++ ++void _rtw_spinlock_init(_lock *plock) ++{ ++ ++#ifdef PLATFORM_LINUX ++ ++ spin_lock_init(plock); ++ ++#endif ++ ++#ifdef PLATFORM_WINDOWS ++ ++ NdisAllocateSpinLock(plock); ++ ++#endif ++ ++} ++ ++void _rtw_spinlock_free(_lock *plock) ++{ ++ ++ ++#ifdef PLATFORM_WINDOWS ++ ++ NdisFreeSpinLock(plock); ++ ++#endif ++ ++} ++ ++ ++void _rtw_spinlock(_lock *plock) ++{ ++ ++#ifdef PLATFORM_LINUX ++ ++ spin_lock(plock); ++ ++#endif ++ ++#ifdef PLATFORM_WINDOWS ++ ++ NdisAcquireSpinLock(plock); ++ ++#endif ++ ++} ++ ++void _rtw_spinunlock(_lock *plock) ++{ ++ ++#ifdef PLATFORM_LINUX ++ ++ spin_unlock(plock); ++ ++#endif ++ ++#ifdef PLATFORM_WINDOWS ++ ++ NdisReleaseSpinLock(plock); ++ ++#endif ++} ++ ++ ++void _rtw_spinlock_ex(_lock *plock) ++{ ++ ++#ifdef PLATFORM_LINUX ++ ++ spin_lock(plock); ++ ++#endif ++ ++#ifdef PLATFORM_WINDOWS ++ ++ NdisDprAcquireSpinLock(plock); ++ ++#endif ++ ++} ++ ++void _rtw_spinunlock_ex(_lock *plock) ++{ ++ ++#ifdef PLATFORM_LINUX ++ ++ spin_unlock(plock); ++ ++#endif ++ ++#ifdef PLATFORM_WINDOWS ++ ++ NdisDprReleaseSpinLock(plock); ++ ++#endif ++} ++ ++ ++ ++void _rtw_init_queue(_queue *pqueue) ++{ ++ ++ _rtw_init_listhead(&(pqueue->queue)); ++ ++ _rtw_spinlock_init(&(pqueue->lock)); ++ ++} ++ ++u32 _rtw_queue_empty(_queue *pqueue) ++{ ++ return (rtw_is_list_empty(&(pqueue->queue))); ++} ++ ++ ++u32 rtw_end_of_queue_search(_list *head, _list *plist) ++{ ++ if (head == plist) ++ return _TRUE; ++ else ++ return _FALSE; ++} ++ ++ ++u32 rtw_get_current_time(void) ++{ ++ ++#ifdef PLATFORM_LINUX ++ return jiffies; ++#endif ++ ++#ifdef PLATFORM_WINDOWS ++ LARGE_INTEGER SystemTime; ++ NdisGetCurrentSystemTime(&SystemTime); ++ return (u32)(SystemTime.LowPart);// count of 100-nanosecond intervals ++#endif ++} ++ ++inline u32 rtw_systime_to_ms(u32 systime) ++{ ++#ifdef PLATFORM_LINUX ++ return systime*1000/HZ; ++#endif ++ ++#ifdef PLATFORM_WINDOWS ++ return systime /10000 ; ++#endif ++} ++ ++// the input parameter start use the same unit as returned by rtw_get_current_time ++inline s32 rtw_get_passing_time_ms(u32 start) ++{ ++#ifdef PLATFORM_LINUX ++ return rtw_systime_to_ms(jiffies-start); ++#endif ++ ++#ifdef PLATFORM_WINDOWS ++ LARGE_INTEGER SystemTime; ++ NdisGetCurrentSystemTime(&SystemTime); ++ return rtw_systime_to_ms((u32)(SystemTime.LowPart) - start) ; ++#endif ++} ++ ++inline s32 rtw_get_time_interval_ms(u32 start, u32 end) ++{ ++#ifdef PLATFORM_LINUX ++ return rtw_systime_to_ms(end-start); ++#endif ++ ++#ifdef PLATFORM_WINDOWS ++ return rtw_systime_to_ms(end-start); ++#endif ++} ++ ++ ++void rtw_sleep_schedulable(int ms) ++{ ++ ++#ifdef PLATFORM_LINUX ++ ++ u32 delta; ++ ++ delta = (ms * HZ)/1000;//(ms) ++ if (delta == 0) { ++ delta = 1;// 1 ms ++ } ++ set_current_state(TASK_INTERRUPTIBLE); ++ if (schedule_timeout(delta) != 0) { ++ return ; ++ } ++ return; ++ ++#endif ++ ++#ifdef PLATFORM_WINDOWS ++ ++ NdisMSleep(ms*1000); //(us)*1000=(ms) ++ ++#endif ++ ++} ++ ++ ++void rtw_msleep_os(int ms) ++{ ++ ++#ifdef PLATFORM_LINUX ++ ++ msleep((unsigned int)ms); ++ ++#endif ++ ++#ifdef PLATFORM_WINDOWS ++ ++ NdisMSleep(ms*1000); //(us)*1000=(ms) ++ ++#endif ++ ++ ++} ++void rtw_usleep_os(int us) ++{ ++ ++#ifdef PLATFORM_LINUX ++ ++ // msleep((unsigned int)us); ++ if ( 1 < (us/1000) ) ++ msleep(1); ++ else ++ msleep( (us/1000) + 1); ++ ++#endif ++ ++#ifdef PLATFORM_WINDOWS ++ ++ NdisMSleep(us); //(us) ++ ++#endif ++ ++ ++} ++ ++ ++#ifdef DBG_DELAY_OS ++void _rtw_mdelay_os(int ms, const char *func, const int line) ++{ ++ #if 0 ++ if(ms>10) ++ DBG_871X("%s:%d %s(%d)\n", func, line, __FUNCTION__, ms); ++ rtw_msleep_os(ms); ++ return; ++ #endif ++ ++ ++ DBG_871X("%s:%d %s(%d)\n", func, line, __FUNCTION__, ms); ++ ++#if defined(PLATFORM_LINUX) ++ ++ mdelay((unsigned long)ms); ++ ++#elif defined(PLATFORM_WINDOWS) ++ ++ NdisStallExecution(ms*1000); //(us)*1000=(ms) ++ ++#endif ++ ++ ++} ++void _rtw_udelay_os(int us, const char *func, const int line) ++{ ++ ++ #if 0 ++ if(us > 1000) { ++ DBG_871X("%s:%d %s(%d)\n", func, line, __FUNCTION__, us); ++ rtw_usleep_os(us); ++ return; ++ } ++ #endif ++ ++ ++ DBG_871X("%s:%d %s(%d)\n", func, line, __FUNCTION__, us); ++ ++ ++#if defined(PLATFORM_LINUX) ++ ++ udelay((unsigned long)us); ++ ++#elif defined(PLATFORM_WINDOWS) ++ ++ NdisStallExecution(us); //(us) ++ ++#endif ++ ++} ++#else ++void rtw_mdelay_os(int ms) ++{ ++ ++#ifdef PLATFORM_LINUX ++ ++ mdelay((unsigned long)ms); ++ ++#endif ++ ++#ifdef PLATFORM_WINDOWS ++ ++ NdisStallExecution(ms*1000); //(us)*1000=(ms) ++ ++#endif ++ ++ ++} ++void rtw_udelay_os(int us) ++{ ++ ++#ifdef PLATFORM_LINUX ++ ++ udelay((unsigned long)us); ++ ++#endif ++ ++#ifdef PLATFORM_WINDOWS ++ ++ NdisStallExecution(us); //(us) ++ ++#endif ++ ++} ++#endif ++ ++#define RTW_SUSPEND_LOCK_NAME "rtw_wifi" ++ ++#ifdef CONFIG_WAKELOCK ++static struct wake_lock rtw_suspend_lock; ++#elif defined(CONFIG_ANDROID_POWER) ++static android_suspend_lock_t rtw_suspend_lock ={ ++ .name = RTW_SUSPEND_LOCK_NAME ++}; ++#endif ++ ++inline void rtw_suspend_lock_init() ++{ ++ #if defined(CONFIG_WAKELOCK) || defined(CONFIG_ANDROID_POWER) ++ DBG_871X("##########%s ###########\n", __FUNCTION__); ++ #endif ++ ++ #ifdef CONFIG_WAKELOCK ++ wake_lock_init(&rtw_suspend_lock, WAKE_LOCK_SUSPEND, RTW_SUSPEND_LOCK_NAME); ++ #elif defined(CONFIG_ANDROID_POWER) ++ android_init_suspend_lock(&rtw_suspend_lock); ++ #endif ++ ++} ++ ++inline void rtw_suspend_lock_uninit() ++{ ++ ++ #if defined(CONFIG_WAKELOCK) || defined(CONFIG_ANDROID_POWER) ++ DBG_871X("##########%s###########\n", __FUNCTION__); ++ if(rtw_suspend_lock.link.next == LIST_POISON1 || rtw_suspend_lock.link.prev == LIST_POISON2) { ++ DBG_871X("##########%s########### list poison!!\n", __FUNCTION__); ++ return; ++ } ++ #endif ++ ++ #ifdef CONFIG_WAKELOCK ++ wake_lock_destroy(&rtw_suspend_lock); ++ #elif defined(CONFIG_ANDROID_POWER) ++ android_uninit_suspend_lock(&rtw_suspend_lock); ++ #endif ++} ++ ++ ++inline void rtw_lock_suspend() ++{ ++ ++ #if defined(CONFIG_WAKELOCK) || defined(CONFIG_ANDROID_POWER) ++ //DBG_871X("##########%s###########\n", __FUNCTION__); ++ if(rtw_suspend_lock.link.next == LIST_POISON1 || rtw_suspend_lock.link.prev == LIST_POISON2) { ++ DBG_871X("##########%s########### list poison!!\n", __FUNCTION__); ++ return; ++ } ++ #endif ++ ++ #ifdef CONFIG_WAKELOCK ++ wake_lock(&rtw_suspend_lock); ++ #elif defined(CONFIG_ANDROID_POWER) ++ android_lock_suspend(&rtw_suspend_lock); ++ #endif ++} ++ ++inline void rtw_unlock_suspend() ++{ ++ #if defined(CONFIG_WAKELOCK) || defined(CONFIG_ANDROID_POWER) ++ //DBG_871X("##########%s###########\n", __FUNCTION__); ++ if(rtw_suspend_lock.link.next == LIST_POISON1 || rtw_suspend_lock.link.prev == LIST_POISON2) { ++ DBG_871X("##########%s########### list poison!!\n", __FUNCTION__); ++ return; ++ } ++ #endif ++ ++ #ifdef CONFIG_WAKELOCK ++ wake_unlock(&rtw_suspend_lock); ++ #elif defined(CONFIG_ANDROID_POWER) ++ android_unlock_suspend(&rtw_suspend_lock); ++ #endif ++} ++ ++ ++inline void ATOMIC_SET(ATOMIC_T *v, int i) ++{ ++ #ifdef PLATFORM_LINUX ++ atomic_set(v,i); ++ #elif defined(PLATFORM_WINDOWS) ++ *v=i;// other choice???? ++ #endif ++} ++ ++inline int ATOMIC_READ(ATOMIC_T *v) ++{ ++ #ifdef PLATFORM_LINUX ++ return atomic_read(v); ++ #elif defined(PLATFORM_WINDOWS) ++ return *v; // other choice???? ++ #endif ++} ++ ++inline void ATOMIC_ADD(ATOMIC_T *v, int i) ++{ ++ #ifdef PLATFORM_LINUX ++ atomic_add(i,v); ++ #elif defined(PLATFORM_WINDOWS) ++ InterlockedAdd(v,i); ++ #endif ++} ++inline void ATOMIC_SUB(ATOMIC_T *v, int i) ++{ ++ #ifdef PLATFORM_LINUX ++ atomic_sub(i,v); ++ #elif defined(PLATFORM_WINDOWS) ++ InterlockedAdd(v,-i); ++ #endif ++} ++ ++inline void ATOMIC_INC(ATOMIC_T *v) ++{ ++ #ifdef PLATFORM_LINUX ++ atomic_inc(v); ++ #elif defined(PLATFORM_WINDOWS) ++ InterlockedIncrement(v); ++ #endif ++} ++ ++inline void ATOMIC_DEC(ATOMIC_T *v) ++{ ++ #ifdef PLATFORM_LINUX ++ atomic_dec(v); ++ #elif defined(PLATFORM_WINDOWS) ++ InterlockedDecrement(v); ++ #endif ++} ++ ++inline int ATOMIC_ADD_RETURN(ATOMIC_T *v, int i) ++{ ++ #ifdef PLATFORM_LINUX ++ return atomic_add_return(i,v); ++ #elif defined(PLATFORM_WINDOWS) ++ return InterlockedAdd(v,i); ++ #endif ++} ++ ++inline int ATOMIC_SUB_RETURN(ATOMIC_T *v, int i) ++{ ++ #ifdef PLATFORM_LINUX ++ return atomic_sub_return(i,v); ++ #elif defined(PLATFORM_WINDOWS) ++ return InterlockedAdd(v,-i); ++ #endif ++} ++ ++inline int ATOMIC_INC_RETURN(ATOMIC_T *v) ++{ ++ #ifdef PLATFORM_LINUX ++ return atomic_inc_return(v); ++ #elif defined(PLATFORM_WINDOWS) ++ return InterlockedIncrement(v); ++ #endif ++} ++ ++inline int ATOMIC_DEC_RETURN(ATOMIC_T *v) ++{ ++ #ifdef PLATFORM_LINUX ++ return atomic_dec_return(v); ++ #elif defined(PLATFORM_WINDOWS) ++ return InterlockedDecrement(v); ++ #endif ++} ++ ++ ++#ifdef PLATFORM_LINUX ++/* ++* Open a file with the specific @param path, @param flag, @param mode ++* @param fpp the pointer of struct file pointer to get struct file pointer while file opening is success ++* @param path the path of the file to open ++* @param flag file operation flags, please refer to linux document ++* @param mode please refer to linux document ++* @return Linux specific error code ++*/ ++static int openFile(struct file **fpp, char *path, int flag, int mode) ++{ ++ struct file *fp; ++ ++ fp=filp_open(path, flag, mode); ++ if(IS_ERR(fp)) { ++ *fpp=NULL; ++ return PTR_ERR(fp); ++ } ++ else { ++ *fpp=fp; ++ return 0; ++ } ++} ++ ++/* ++* Close the file with the specific @param fp ++* @param fp the pointer of struct file to close ++* @return always 0 ++*/ ++static int closeFile(struct file *fp) ++{ ++ filp_close(fp,NULL); ++ return 0; ++} ++ ++static int readFile(struct file *fp,char *buf,int len) ++{ ++ int rlen=0, sum=0; ++ ++ if (!fp->f_op || !fp->f_op->read) ++ return -EPERM; ++ ++ while(sumf_op->read(fp,buf+sum,len-sum, &fp->f_pos); ++ if(rlen>0) ++ sum+=rlen; ++ else if(0 != rlen) ++ return rlen; ++ else ++ break; ++ } ++ ++ return sum; ++ ++} ++ ++static int writeFile(struct file *fp,char *buf,int len) ++{ ++ int wlen=0, sum=0; ++ ++ if (!fp->f_op || !fp->f_op->write) ++ return -EPERM; ++ ++ while(sumf_op->write(fp,buf+sum,len-sum, &fp->f_pos); ++ if(wlen>0) ++ sum+=wlen; ++ else if(0 != wlen) ++ return wlen; ++ else ++ break; ++ } ++ ++ return sum; ++ ++} ++ ++/* ++* Test if the specifi @param path is a file and readable ++* @param path the path of the file to test ++* @return Linux specific error code ++*/ ++static int isFileReadable(char *path) ++{ ++ struct file *fp; ++ int ret = 0; ++ mm_segment_t oldfs; ++ char buf; ++ ++ fp=filp_open(path, O_RDONLY, 0); ++ if(IS_ERR(fp)) { ++ ret = PTR_ERR(fp); ++ } ++ else { ++ oldfs = get_fs(); set_fs(get_ds()); ++ ++ if(1!=readFile(fp, &buf, 1)) ++ ret = PTR_ERR(fp); ++ ++ set_fs(oldfs); ++ filp_close(fp,NULL); ++ } ++ return ret; ++} ++ ++/* ++* Open the file with @param path and retrive the file content into memory starting from @param buf for @param sz at most ++* @param path the path of the file to open and read ++* @param buf the starting address of the buffer to store file content ++* @param sz how many bytes to read at most ++* @return the byte we've read, or Linux specific error code ++*/ ++static int retriveFromFile(char *path, u8* buf, u32 sz) ++{ ++ int ret =-1; ++ mm_segment_t oldfs; ++ struct file *fp; ++ ++ if(path && buf) { ++ if( 0 == (ret=openFile(&fp,path, O_RDONLY, 0)) ){ ++ DBG_8192C("%s openFile path:%s fp=%p\n",__FUNCTION__, path ,fp); ++ ++ oldfs = get_fs(); set_fs(get_ds()); ++ ret=readFile(fp, buf, sz); ++ set_fs(oldfs); ++ closeFile(fp); ++ ++ DBG_8192C("%s readFile, ret:%d\n",__FUNCTION__, ret); ++ ++ } else { ++ DBG_8192C("%s openFile path:%s Fail, ret:%d\n",__FUNCTION__, path, ret); ++ } ++ } else { ++ DBG_8192C("%s NULL pointer\n",__FUNCTION__); ++ ret = -EINVAL; ++ } ++ return ret; ++} ++ ++/* ++* Open the file with @param path and wirte @param sz byte of data starting from @param buf into the file ++* @param path the path of the file to open and write ++* @param buf the starting address of the data to write into file ++* @param sz how many bytes to write at most ++* @return the byte we've written, or Linux specific error code ++*/ ++static int storeToFile(char *path, u8* buf, u32 sz) ++{ ++ int ret =0; ++ mm_segment_t oldfs; ++ struct file *fp; ++ ++ if(path && buf) { ++ if( 0 == (ret=openFile(&fp, path, O_CREAT|O_WRONLY, 0666)) ) { ++ DBG_8192C("%s openFile path:%s fp=%p\n",__FUNCTION__, path ,fp); ++ ++ oldfs = get_fs(); set_fs(get_ds()); ++ ret=writeFile(fp, buf, sz); ++ set_fs(oldfs); ++ closeFile(fp); ++ ++ DBG_8192C("%s writeFile, ret:%d\n",__FUNCTION__, ret); ++ ++ } else { ++ DBG_8192C("%s openFile path:%s Fail, ret:%d\n",__FUNCTION__, path, ret); ++ } ++ } else { ++ DBG_8192C("%s NULL pointer\n",__FUNCTION__); ++ ret = -EINVAL; ++ } ++ return ret; ++} ++#endif //PLATFORM_LINUX ++ ++/* ++* Test if the specifi @param path is a file and readable ++* @param path the path of the file to test ++* @return _TRUE or _FALSE ++*/ ++int rtw_is_file_readable(char *path) ++{ ++#ifdef PLATFORM_LINUX ++ if(isFileReadable(path) == 0) ++ return _TRUE; ++ else ++ return _FALSE; ++#else ++ //Todo... ++ return _FALSE; ++#endif ++} ++ ++/* ++* Open the file with @param path and retrive the file content into memory starting from @param buf for @param sz at most ++* @param path the path of the file to open and read ++* @param buf the starting address of the buffer to store file content ++* @param sz how many bytes to read at most ++* @return the byte we've read ++*/ ++int rtw_retrive_from_file(char *path, u8* buf, u32 sz) ++{ ++#ifdef PLATFORM_LINUX ++ int ret =retriveFromFile(path, buf, sz); ++ return ret>=0?ret:0; ++#else ++ //Todo... ++ return 0; ++#endif ++} ++ ++/* ++* Open the file with @param path and wirte @param sz byte of data starting from @param buf into the file ++* @param path the path of the file to open and write ++* @param buf the starting address of the data to write into file ++* @param sz how many bytes to write at most ++* @return the byte we've written ++*/ ++int rtw_store_to_file(char *path, u8* buf, u32 sz) ++{ ++#ifdef PLATFORM_LINUX ++ int ret =storeToFile(path, buf, sz); ++ return ret>=0?ret:0; ++#else ++ //Todo... ++ return 0; ++#endif ++} ++ ++#if 1 //#ifdef MEM_ALLOC_REFINE_ADAPTOR ++#ifdef PLATFORM_LINUX ++struct net_device *rtw_alloc_etherdev_with_old_priv(int sizeof_priv, void *old_priv) ++{ ++ struct net_device *pnetdev; ++ struct rtw_netdev_priv_indicator *pnpi; ++ ++ pnetdev = alloc_etherdev(sizeof(struct rtw_netdev_priv_indicator)); ++ if (!pnetdev) ++ goto RETURN; ++ ++ pnpi = netdev_priv(pnetdev); ++ pnpi->priv=old_priv; ++ pnpi->sizeof_priv=sizeof_priv; ++ ++RETURN: ++ return pnetdev; ++} ++ ++struct net_device *rtw_alloc_etherdev(int sizeof_priv) ++{ ++ struct net_device *pnetdev; ++ struct rtw_netdev_priv_indicator *pnpi; ++ ++ pnetdev = alloc_etherdev(sizeof(struct rtw_netdev_priv_indicator)); ++ if (!pnetdev) ++ goto RETURN; ++ ++ pnpi = netdev_priv(pnetdev); ++ ++ pnpi->priv = rtw_zvmalloc(sizeof_priv); ++ if (!pnpi->priv) { ++ free_netdev(pnetdev); ++ pnetdev = NULL; ++ goto RETURN; ++ } ++ ++ pnpi->sizeof_priv=sizeof_priv; ++RETURN: ++ return pnetdev; ++} ++ ++void rtw_free_netdev(struct net_device * netdev) ++{ ++ struct rtw_netdev_priv_indicator *pnpi; ++ ++ if(!netdev) ++ goto RETURN; ++ ++ pnpi = netdev_priv(netdev); ++ ++ if(!pnpi->priv) ++ goto RETURN; ++ ++ rtw_vmfree(pnpi->priv, pnpi->sizeof_priv); ++ free_netdev(netdev); ++ ++RETURN: ++ return; ++} ++ ++/* ++* Jeff: this function should be called under ioctl (rtnl_lock is accquired) while ++* LINUX_VERSION_CODE < KERNEL_VERSION(2,6,26) ++*/ ++int rtw_change_ifname(_adapter *padapter, const char *ifname) ++{ ++ struct net_device *pnetdev; ++ struct net_device *cur_pnetdev = padapter->pnetdev; ++ struct rereg_nd_name_data *rereg_priv; ++ int ret; ++ ++ if(!padapter) ++ goto error; ++ ++ rereg_priv = &padapter->rereg_nd_name_priv; ++ ++ //free the old_pnetdev ++ if(rereg_priv->old_pnetdev) { ++ free_netdev(rereg_priv->old_pnetdev); ++ rereg_priv->old_pnetdev = NULL; ++ } ++ ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,26)) ++ if(!rtnl_is_locked()) ++ unregister_netdev(cur_pnetdev); ++ else ++#endif ++ unregister_netdevice(cur_pnetdev); ++ ++ #ifdef CONFIG_PROC_DEBUG ++ rtw_proc_remove_one(cur_pnetdev); ++ #endif //CONFIG_PROC_DEBUG ++ ++ rereg_priv->old_pnetdev=cur_pnetdev; ++ ++ pnetdev = rtw_init_netdev(padapter); ++ if (!pnetdev) { ++ ret = -1; ++ goto error; ++ } ++ ++#ifdef CONFIG_USB_HCI ++ ++ SET_NETDEV_DEV(pnetdev, &padapter->dvobjpriv.pusbintf->dev); ++ ++ usb_set_intfdata(padapter->dvobjpriv.pusbintf, pnetdev); ++ ++#elif defined(CONFIG_PCI_HCI) ++ ++#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0) ++ SET_NETDEV_DEV(pnetdev, &padapter->dvobjpriv.ppcidev->dev); ++#endif ++ ++ pci_set_drvdata(padapter->dvobjpriv.ppcidev, pnetdev); ++ ++#endif ++ ++ rtw_init_netdev_name(pnetdev, ifname); ++ ++ _rtw_memcpy(pnetdev->dev_addr, padapter->eeprompriv.mac_addr, ETH_ALEN); ++ ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,26)) ++ if(!rtnl_is_locked()) ++ ret = register_netdev(pnetdev); ++ else ++#endif ++ ret = register_netdevice(pnetdev); ++ ++ if ( ret != 0) { ++ RT_TRACE(_module_hci_intfs_c_,_drv_err_,("register_netdev() failed\n")); ++ goto error; ++ } ++ ++ #ifdef CONFIG_PROC_DEBUG ++ rtw_proc_init_one(pnetdev); ++ #endif //CONFIG_PROC_DEBUG ++ ++ return 0; ++ ++error: ++ ++ return -1; ++ ++} ++#endif ++#endif //MEM_ALLOC_REFINE_ADAPTOR ++ ++u64 rtw_modular64(u64 x, u64 y) ++{ ++#ifdef PLATFORM_LINUX ++ return do_div(x, y); ++#elif defined(PLATFORM_WINDOWS) ++ return (x % y); ++#endif ++} ++ ++u64 rtw_division64(u64 x, u64 y) ++{ ++#ifdef PLATFORM_LINUX ++ do_div(x, y); ++ return x; ++#elif defined(PLATFORM_WINDOWS) ++ return (x / y); ++#endif ++} ++ +Index: linux-3.2.46/drivers/net/wireless/rtl8192cu/wlan0dhcp +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/net/wireless/rtl8192cu/wlan0dhcp 2013-07-26 19:36:07.000000000 +0000 +@@ -0,0 +1,16 @@ ++#!/bin/bash ++ ++var0=`ps aux|awk '/dhclient wlan0/'|awk '$11!="awk"{print $2}'` ++ ++kill $var0 ++cp ifcfg-wlan0 /etc/sysconfig/network-scripts/ ++ ++dhclient wlan0 ++ ++var1=`ifconfig wlan0 |awk '/inet/{print $2}'|awk -F: '{print $2}'` ++ ++ ++rm -f /etc/sysconfig/network-scripts/ifcfg-wlan0 ++ ++echo "get ip: $var1" ++ diff -Nru linux-3.2.46/debian/patches/rpi/rpi_238_78f82bc5324ac5032d33c4b718982e32e7c76c6b.patch linux-3.2.46/debian/patches/rpi/rpi_238_78f82bc5324ac5032d33c4b718982e32e7c76c6b.patch --- linux-3.2.46/debian/patches/rpi/rpi_238_78f82bc5324ac5032d33c4b718982e32e7c76c6b.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_238_78f82bc5324ac5032d33c4b718982e32e7c76c6b.patch 2013-07-26 19:36:25.000000000 +0000 @@ -0,0 +1,111 @@ +commit 78f82bc5324ac5032d33c4b718982e32e7c76c6b +Author: popcornmix +Date: Mon Sep 3 23:44:52 2012 +0100 + + Add verious user config requests. + CONFIG_DEVTMPFS_MOUNT, CONFIG_NFS_V4_1=y CONFIG_NFSD_V3_ACL=y CONFIG_NFSD_V4=y, drbd and IPSEC modules + +Index: linux-3.2.46/arch/arm/configs/bcmrpi_defconfig +=================================================================== +--- linux-3.2.46.orig/arch/arm/configs/bcmrpi_defconfig 2013-07-26 19:35:55.000000000 +0000 ++++ linux-3.2.46/arch/arm/configs/bcmrpi_defconfig 2013-07-26 19:36:24.000000000 +0000 +@@ -1,3 +1,4 @@ ++# CONFIG_ARM_PATCH_PHYS_VIRT is not set + CONFIG_EXPERIMENTAL=y + # CONFIG_LOCALVERSION_AUTO is not set + CONFIG_SYSVIPC=y +@@ -64,11 +65,19 @@ + CONFIG_IP_PNP_RARP=y + CONFIG_NET_IPIP=m + CONFIG_SYN_COOKIES=y +-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +-# CONFIG_INET_XFRM_MODE_TUNNEL is not set +-# CONFIG_INET_XFRM_MODE_BEET is not set +-# CONFIG_INET_DIAG is not set ++CONFIG_INET_AH=m ++CONFIG_INET_ESP=m ++CONFIG_INET_IPCOMP=m ++CONFIG_INET_XFRM_MODE_TRANSPORT=m ++CONFIG_INET_XFRM_MODE_TUNNEL=m ++CONFIG_INET_XFRM_MODE_BEET=m ++CONFIG_INET_LRO=m ++CONFIG_INET_DIAG=m + CONFIG_IPV6_PRIVACY=y ++CONFIG_INET6_AH=m ++CONFIG_INET6_ESP=m ++CONFIG_INET6_IPCOMP=m ++CONFIG_IPV6_MULTIPLE_TABLES=y + CONFIG_NETFILTER=y + CONFIG_NF_CONNTRACK=m + CONFIG_NF_CONNTRACK_ZONES=y +@@ -130,6 +139,7 @@ + CONFIG_NETFILTER_XT_MATCH_OSF=m + CONFIG_NETFILTER_XT_MATCH_OWNER=m + CONFIG_NETFILTER_XT_MATCH_POLICY=m ++CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m + CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m + CONFIG_NETFILTER_XT_MATCH_QUOTA=m + CONFIG_NETFILTER_XT_MATCH_RATEEST=m +@@ -312,8 +322,10 @@ + CONFIG_NFC=m + CONFIG_NFC_PN533=m + CONFIG_DEVTMPFS=y ++CONFIG_DEVTMPFS_MOUNT=y + CONFIG_BLK_DEV_LOOP=y + CONFIG_BLK_DEV_CRYPTOLOOP=m ++CONFIG_BLK_DEV_DRBD=m + CONFIG_BLK_DEV_NBD=m + CONFIG_BLK_DEV_RAM=y + CONFIG_CDROM_PKTCDVD=m +@@ -406,12 +418,12 @@ + CONFIG_RT73USB=m + CONFIG_RT2800USB=m + CONFIG_RT2800USB_RT53XX=y +-CONFIG_RTL8192CU=m + CONFIG_WL1251=m + CONFIG_WL12XX_MENU=m + CONFIG_ZD1211RW=m + CONFIG_MWIFIEX=m + CONFIG_MWIFIEX_SDIO=m ++CONFIG_RTL8192CU=m + CONFIG_WIMAX_I2400M_USB=m + CONFIG_INPUT_POLLDEV=m + # CONFIG_INPUT_MOUSEDEV_PSAUX is not set +@@ -470,6 +482,12 @@ + CONFIG_MEDIA_SUPPORT=m + CONFIG_VIDEO_DEV=m + CONFIG_DVB_CORE=m ++CONFIG_RC_ATI_REMOTE=m ++CONFIG_IR_IMON=m ++CONFIG_IR_MCEUSB=m ++CONFIG_IR_REDRAT3=m ++CONFIG_IR_STREAMZAP=m ++CONFIG_RC_LOOPBACK=m + CONFIG_MEDIA_ATTACH=y + CONFIG_USB_VIDEO_CLASS=m + CONFIG_USB_M5602=m +@@ -807,6 +825,8 @@ + CONFIG_ROOT_NFS=y + CONFIG_NFS_FSCACHE=y + CONFIG_NFSD=m ++CONFIG_NFSD_V3_ACL=y ++CONFIG_NFSD_V4=y + CONFIG_CIFS=m + CONFIG_CIFS_WEAK_PW_HASH=y + CONFIG_CIFS_XATTR=y +@@ -868,7 +888,6 @@ + CONFIG_KGDB_KDB=y + CONFIG_KDB_KEYBOARD=y + CONFIG_STRICT_DEVMEM=y +-CONFIG_CRYPTO_AUTHENC=m + CONFIG_CRYPTO_SEQIV=m + CONFIG_CRYPTO_CBC=y + CONFIG_CRYPTO_XTS=m +@@ -882,7 +901,6 @@ + CONFIG_CRYPTO_WP512=m + CONFIG_CRYPTO_CAST5=m + CONFIG_CRYPTO_DES=y +-CONFIG_CRYPTO_DEFLATE=m + # CONFIG_CRYPTO_ANSI_CPRNG is not set + # CONFIG_CRYPTO_HW is not set + CONFIG_CRC_ITU_T=y diff -Nru linux-3.2.46/debian/patches/rpi/rpi_239_202a7792fbdf8763e8c50805b2bc15f007484f04.patch linux-3.2.46/debian/patches/rpi/rpi_239_202a7792fbdf8763e8c50805b2bc15f007484f04.patch --- linux-3.2.46/debian/patches/rpi/rpi_239_202a7792fbdf8763e8c50805b2bc15f007484f04.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_239_202a7792fbdf8763e8c50805b2bc15f007484f04.patch 2013-07-26 19:36:26.000000000 +0000 @@ -0,0 +1,23 @@ +commit 202a7792fbdf8763e8c50805b2bc15f007484f04 +Author: popcornmix +Date: Sat Sep 8 14:49:16 2012 +0100 + + Don't believe KDIR is required when building as part of kernel + +Index: linux-3.2.46/drivers/usb/host/dwc_common_port/Makefile +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_common_port/Makefile 2013-07-26 19:34:39.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_common_port/Makefile 2013-07-26 19:36:25.000000000 +0000 +@@ -30,9 +30,9 @@ + + else + +-ifeq ($(KDIR),) +-$(error Must give "KDIR=/path/to/kernel/source" on command line or in environment) +-endif ++#ifeq ($(KDIR),) ++#$(error Must give "KDIR=/path/to/kernel/source" on command line or in environment) ++#endif + + ifeq ($(ARCH),) + $(error Must give "ARCH=" on command line or in environment. Also, if \ diff -Nru linux-3.2.46/debian/patches/rpi/rpi_240_55549f3998e7f8196dd6401933d895823a026ce5.patch linux-3.2.46/debian/patches/rpi/rpi_240_55549f3998e7f8196dd6401933d895823a026ce5.patch --- linux-3.2.46/debian/patches/rpi/rpi_240_55549f3998e7f8196dd6401933d895823a026ce5.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_240_55549f3998e7f8196dd6401933d895823a026ce5.patch 2013-07-26 19:36:27.000000000 +0000 @@ -0,0 +1,99 @@ +commit 55549f3998e7f8196dd6401933d895823a026ce5 +Author: popcornmix +Date: Sat Sep 8 15:17:53 2012 +0100 + + Avoid dynamic memory allocation for channel lock in USB driver. Thanks ddv2005. + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_hcd.c +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/dwc_otg_hcd.c 2013-07-26 19:35:59.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_hcd.c 2013-07-26 19:36:26.000000000 +0000 +@@ -822,6 +822,7 @@ + } else if (dwc_otg_hcd->status_buf != NULL) { + DWC_FREE(dwc_otg_hcd->status_buf); + } ++ DWC_SPINLOCK_FREE(dwc_otg_hcd->channel_lock); + DWC_SPINLOCK_FREE(dwc_otg_hcd->lock); + /* Set core_if's lock pointer to NULL */ + dwc_otg_hcd->core_if->lock = NULL; +@@ -848,6 +849,7 @@ + dwc_hc_t *channel; + + hcd->lock = DWC_SPINLOCK_ALLOC(); ++ hcd->channel_lock = DWC_SPINLOCK_ALLOC(); + DWC_DEBUGPL(DBG_HCDV, "init of HCD %p given core_if %p\n", + hcd, core_if); + if (!hcd->lock) { +@@ -1248,7 +1250,7 @@ + dwc_otg_qh_t *qh; + int num_channels; + dwc_irqflags_t flags; +- dwc_spinlock_t *channel_lock = DWC_SPINLOCK_ALLOC(); ++ dwc_spinlock_t *channel_lock = hcd->channel_lock; + dwc_otg_transaction_type_e ret_val = DWC_OTG_TRANSACTION_NONE; + + #ifdef DEBUG_SOF +@@ -1348,8 +1350,6 @@ + #ifdef DEBUG_HOST_CHANNELS + last_sel_trans_num_avail_hc_at_end = hcd->available_host_channels; + #endif /* DEBUG_HOST_CHANNELS */ +- +- DWC_SPINLOCK_FREE(channel_lock); + return ret_val; + } + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_hcd.h +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/dwc_otg_hcd.h 2013-07-26 19:35:59.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_hcd.h 2013-07-26 19:36:26.000000000 +0000 +@@ -548,7 +548,7 @@ + + /* */ + dwc_spinlock_t *lock; +- ++ dwc_spinlock_t *channel_lock; + /** + * Private data that could be used by OS wrapper. + */ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_hcd_ddma.c +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/dwc_otg_hcd_ddma.c 2013-07-26 19:35:16.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_hcd_ddma.c 2013-07-26 19:36:26.000000000 +0000 +@@ -276,7 +276,7 @@ + static void release_channel_ddma(dwc_otg_hcd_t * hcd, dwc_otg_qh_t * qh) + { + dwc_irqflags_t flags; +- dwc_spinlock_t *channel_lock = DWC_SPINLOCK_ALLOC(); ++ dwc_spinlock_t *channel_lock = hcd->channel_lock; + + dwc_hc_t *hc = qh->channel; + if (dwc_qh_is_non_per(qh)) { +@@ -306,7 +306,6 @@ + dwc_memset(qh->desc_list, 0x00, + sizeof(dwc_otg_host_dma_desc_t) * max_desc_num(qh)); + } +- DWC_SPINLOCK_FREE(channel_lock); + } + + /** +Index: linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c 2013-07-26 19:35:59.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c 2013-07-26 19:36:26.000000000 +0000 +@@ -922,7 +922,7 @@ + dwc_otg_transaction_type_e tr_type; + int free_qtd; + dwc_irqflags_t flags; +- dwc_spinlock_t *channel_lock = DWC_SPINLOCK_ALLOC(); ++ dwc_spinlock_t *channel_lock = hcd->channel_lock; + + DWC_DEBUGPL(DBG_HCDV, " %s: channel %d, halt_status %d, xfer_len %d\n", + __func__, hc->hc_num, halt_status, hc->xfer_len); +@@ -1009,7 +1009,6 @@ + if (tr_type != DWC_OTG_TRANSACTION_NONE) { + dwc_otg_hcd_queue_transactions(hcd, tr_type); + } +- DWC_SPINLOCK_FREE(channel_lock); + } + + /** diff -Nru linux-3.2.46/debian/patches/rpi/rpi_241_adae199d13754b7c0e61c14eac2a92a3a3f6afc1.patch linux-3.2.46/debian/patches/rpi/rpi_241_adae199d13754b7c0e61c14eac2a92a3a3f6afc1.patch --- linux-3.2.46/debian/patches/rpi/rpi_241_adae199d13754b7c0e61c14eac2a92a3a3f6afc1.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_241_adae199d13754b7c0e61c14eac2a92a3a3f6afc1.patch 2013-07-26 19:36:29.000000000 +0000 @@ -0,0 +1,514 @@ +commit adae199d13754b7c0e61c14eac2a92a3a3f6afc1 +Author: popcornmix +Date: Sun Sep 9 23:47:03 2012 +0100 + + Add cpufreq driver + +Index: linux-3.2.46/arch/arm/Kconfig +=================================================================== +--- linux-3.2.46.orig/arch/arm/Kconfig 2013-07-26 19:36:02.000000000 +0000 ++++ linux-3.2.46/arch/arm/Kconfig 2013-07-26 19:36:28.000000000 +0000 +@@ -965,6 +965,7 @@ + select HAVE_SCHED_CLOCK + select NEED_MACH_MEMORY_H + select CLKDEV_LOOKUP ++ select ARCH_HAS_CPUFREQ + select GENERIC_CLOCKEVENTS + select ARM_ERRATA_411920 + select MACH_BCM2708 +Index: linux-3.2.46/arch/arm/configs/bcmrpi_defconfig +=================================================================== +--- linux-3.2.46.orig/arch/arm/configs/bcmrpi_defconfig 2013-07-26 19:36:24.000000000 +0000 ++++ linux-3.2.46/arch/arm/configs/bcmrpi_defconfig 2013-07-26 19:36:28.000000000 +0000 +@@ -46,6 +46,12 @@ + CONFIG_ZBOOT_ROM_BSS=0x0 + CONFIG_CMDLINE="dwc_otg.lpm_enable=0 console=ttyAMA0,115200 kgdboc=ttyAMA0,115200 root=/dev/mmcblk0p2 rootfstype=ext3 rootwait" + CONFIG_KEXEC=y ++CONFIG_CPU_FREQ=y ++CONFIG_CPU_FREQ_STAT=m ++CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y ++CONFIG_CPU_FREQ_GOV_POWERSAVE=y ++CONFIG_CPU_FREQ_GOV_USERSPACE=y ++CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y + CONFIG_CPU_IDLE=y + CONFIG_VFP=y + CONFIG_BINFMT_MISC=m +Index: linux-3.2.46/arch/arm/mach-bcm2708/include/mach/vcio.h +=================================================================== +--- linux-3.2.46.orig/arch/arm/mach-bcm2708/include/mach/vcio.h 2013-07-26 19:35:43.000000000 +0000 ++++ linux-3.2.46/arch/arm/mach-bcm2708/include/mach/vcio.h 2013-07-26 19:36:28.000000000 +0000 +@@ -27,17 +27,82 @@ + #define BCM_VCIO_DRIVER_NAME "bcm2708_vcio" + + /* Constants shared with the ARM identifying separate mailbox channels */ +-#define MBOX_CHAN_POWER 0 /* for use by the power management interface */ +-#define MBOX_CHAN_FB 1 /* for use by the frame buffer */ +-#define MBOX_CHAN_VUART 2 /* for use by the virtual UART */ +-#define MBOX_CHAN_VCHIQ 3 /* for use by the VCHIQ interface */ +-#define MBOX_CHAN_LEDS 4 /* for use by the leds interface */ +-#define MBOX_CHAN_BUTTONS 5 /* for use by the buttons interface */ +-#define MBOX_CHAN_TOUCH 6 /* for use by the touchscreen interface */ ++#define MBOX_CHAN_POWER 0 /* for use by the power management interface */ ++#define MBOX_CHAN_FB 1 /* for use by the frame buffer */ ++#define MBOX_CHAN_VCHIQ 3 /* for use by the VCHIQ interface */ + #define MBOX_CHAN_PROPERTY 8 /* for use by the property channel */ +-#define MBOX_CHAN_COUNT 9 ++#define MBOX_CHAN_COUNT 9 ++ ++/* Mailbox property tags */ ++enum { ++ VCMSG_PROPERTY_END = 0x00000000, ++ VCMSG_GET_FIRMWARE_REVISION = 0x00000001, ++ VCMSG_GET_BOARD_MODEL = 0x00010001, ++ VCMSG_GET_BOARD_REVISION = 0x00020002, ++ VCMSG_GET_BOARD_MAC_ADDRESS = 0x00020003, ++ VCMSG_GET_BOARD_SERIAL = 0x00020004, ++ VCMSG_GET_ARM_MEMORY = 0x00020005, ++ VCMSG_GET_VC_MEMORY = 0x00020006, ++ VCMSG_GET_CLOCKS = 0x00020007, ++ VCMSG_GET_COMMAND_LINE = 0x00050001, ++ VCMSG_GET_DMA_CHANNELS = 0x00060001, ++ VCMSG_GET_POWER_STATE = 0x00020001, ++ VCMSG_GET_TIMING = 0x00020002, ++ VCMSG_SET_POWER_STATE = 0x00028001, ++ VCMSG_GET_CLOCK_STATE = 0x00030001, ++ VCMSG_SET_CLOCK_STATE = 0x00038001, ++ VCMSG_GET_CLOCK_RATE = 0x00030002, ++ VCMSG_SET_CLOCK_RATE = 0x00038002, ++ VCMSG_GET_VOLTAGE = 0x00030003, ++ VCMSG_SET_VOLTAGE = 0x00038003, ++ VCMSG_GET_MAX_CLOCK = 0x00030004, ++ VCMSG_GET_MAX_VOLTAGE = 0x00030005, ++ VCMSG_GET_TEMPERATURE = 0x00030006, ++ VCMSG_GET_MIN_CLOCK = 0x00030007, ++ VCMSG_GET_MIN_VOLTAGE = 0x00030008, ++ VCMSG_GET_TURBO = 0x00030009, ++ VCMSG_SET_TURBO = 0x00038009, ++ VCMSG_SET_ALLOCATE_BUFFER = 0x00040001, ++ VCMSG_SET_RELEASE_BUFFER = 0x00048001, ++ VCMSG_SET_BLANK_SCREEN = 0x00040002, ++ VCMSG_TST_BLANK_SCREEN = 0x00044002, ++ VCMSG_GET_PHYSICAL_WIDTH_HEIGHT = 0x00040003, ++ VCMSG_TST_PHYSICAL_WIDTH_HEIGHT = 0x00044003, ++ VCMSG_SET_PHYSICAL_WIDTH_HEIGHT = 0x00048003, ++ VCMSG_GET_VIRTUAL_WIDTH_HEIGHT = 0x00040004, ++ VCMSG_TST_VIRTUAL_WIDTH_HEIGHT = 0x00044004, ++ VCMSG_SET_VIRTUAL_WIDTH_HEIGHT = 0x00048004, ++ VCMSG_GET_DEPTH = 0x00040005, ++ VCMSG_TST_DEPTH = 0x00044005, ++ VCMSG_SET_DEPTH = 0x00048005, ++ VCMSG_GET_PIXEL_ORDER = 0x00040006, ++ VCMSG_TST_PIXEL_ORDER = 0x00044006, ++ VCMSG_SET_PIXEL_ORDER = 0x00048006, ++ VCMSG_GET_ALPHA_MODE = 0x00040007, ++ VCMSG_TST_ALPHA_MODE = 0x00044007, ++ VCMSG_SET_ALPHA_MODE = 0x00048007, ++ VCMSG_GET_PITCH = 0x00040008, ++ VCMSG_TST_PITCH = 0x00044008, ++ VCMSG_SET_PITCH = 0x00048008, ++ VCMSG_GET_VIRTUAL_OFFSET = 0x00040009, ++ VCMSG_TST_VIRTUAL_OFFSET = 0x00044009, ++ VCMSG_SET_VIRTUAL_OFFSET = 0x00048009, ++ VCMSG_GET_OVERSCAN = 0x0004000a, ++ VCMSG_TST_OVERSCAN = 0x0004400a, ++ VCMSG_SET_OVERSCAN = 0x0004800a, ++ VCMSG_GET_PALETTE = 0x0004000b, ++ VCMSG_TST_PALETTE = 0x0004400b, ++ VCMSG_SET_PALETTE = 0x0004800b, ++ VCMSG_GET_LAYER = 0x0004000c, ++ VCMSG_TST_LAYER = 0x0004400c, ++ VCMSG_SET_LAYER = 0x0004800c, ++ VCMSG_GET_TRANSFORM = 0x0004000d, ++ VCMSG_TST_TRANSFORM = 0x0004400d, ++ VCMSG_SET_TRANSFORM = 0x0004800d, ++}; + + extern int /*rc*/ bcm_mailbox_read(unsigned chan, uint32_t *data28); + extern int /*rc*/ bcm_mailbox_write(unsigned chan, uint32_t data28); ++extern int /*rc*/ bcm_mailbox_property(void *data, int size); + + #endif +Index: linux-3.2.46/arch/arm/mach-bcm2708/vc_mem.c +=================================================================== +--- linux-3.2.46.orig/arch/arm/mach-bcm2708/vc_mem.c 2013-07-26 19:35:43.000000000 +0000 ++++ linux-3.2.46/arch/arm/mach-bcm2708/vc_mem.c 2013-07-26 19:36:28.000000000 +0000 +@@ -128,44 +128,33 @@ + uint32_t end_tag; /* an end identifier, should be set to NULL */ + }; + +-#define VCMSG_GET_ARM_MEMORY 0x00010005 +-#define VCMSG_GET_VC_MEMORY 0x00010006 +- + static void vc_mem_update(void) + { +- uint32_t success; +- dma_addr_t vc_mem; /* the memory address accessed from videocore */ +- struct vc_set_msg *get_mem; /* the memory address accessed from driver */ +- +- /* allocate some memory for the messages to use throughout the lifetime of the driver, use the larger of the two message structures */ +- get_mem = (struct vc_set_msg *)dma_alloc_coherent(NULL, PAGE_ALIGN(sizeof(struct vc_set_msg)), &vc_mem, GFP_ATOMIC); +- /* clear any garbage */ +- memset(get_mem, 0, sizeof(struct vc_set_msg)); ++ struct vc_set_msg msg; /* the memory address accessed from driver */ ++ uint32_t s; ++ ++ memset(&msg, 0, sizeof msg); + /* create the message */ +- get_mem->msg_size = sizeof(struct vc_set_msg); +- get_mem->tag[0].tag_id = VCMSG_GET_VC_MEMORY; +- get_mem->tag[0].buffer_size = 8; +- get_mem->tag[0].data_size = 0; +- get_mem->tag[1].tag_id = VCMSG_GET_ARM_MEMORY; +- get_mem->tag[1].buffer_size = 8; +- get_mem->tag[1].data_size = 0; ++ msg.msg_size = sizeof msg; ++ msg.tag[0].tag_id = VCMSG_GET_VC_MEMORY; ++ msg.tag[0].buffer_size = 8; ++ msg.tag[0].data_size = 0; ++ msg.tag[1].tag_id = VCMSG_GET_ARM_MEMORY; ++ msg.tag[1].buffer_size = 8; ++ msg.tag[1].data_size = 0; + + /* send the message */ +- wmb(); +- bcm_mailbox_write(MBOX_CHAN_PROPERTY,(uint32_t)vc_mem); +- bcm_mailbox_read(MBOX_CHAN_PROPERTY, &success); +- rmb(); ++ s = bcm_mailbox_property(&msg, sizeof msg); + +- LOG_DBG("%s: resp %x, vcbase=%x vcsize=%x armbase=%x armsize=%x", __func__, get_mem->request_code, +- get_mem->tag[0].base, get_mem->tag[0].size, get_mem->tag[1].base, get_mem->tag[1].size); ++ LOG_DBG("%s: success=%d resp %x, vcbase=%x vcsize=%x armbase=%x armsize=%x", __func__, s, msg.request_code, ++ msg.tag[0].base, msg.tag[0].size, msg.tag[1].base, msg.tag[1].size); + + /* check we're all good */ +- if (get_mem->request_code & 0x80000000) { +- mm_vc_mem_base = get_mem->tag[0].base; +- mm_vc_mem_size = get_mem->tag[0].size+get_mem->tag[1].size; +- mm_vc_mem_phys_addr = get_mem->tag[1].base; ++ if (s == 0 && msg.request_code & 0x80000000) { ++ mm_vc_mem_base = msg.tag[0].base; ++ mm_vc_mem_size = msg.tag[0].size+msg.tag[1].size; ++ mm_vc_mem_phys_addr = msg.tag[1].base; + } +- dma_free_coherent(NULL, PAGE_ALIGN(sizeof(struct vc_set_msg)), (void *)get_mem, vc_mem); + } + + +Index: linux-3.2.46/arch/arm/mach-bcm2708/vcio.c +=================================================================== +--- linux-3.2.46.orig/arch/arm/mach-bcm2708/vcio.c 2013-07-26 19:34:05.000000000 +0000 ++++ linux-3.2.46/arch/arm/mach-bcm2708/vcio.c 2013-07-26 19:36:28.000000000 +0000 +@@ -216,6 +216,40 @@ + mbox_dev = dev; + } + ++extern int bcm_mailbox_property(void *data, int size) ++{ ++ uint32_t success; ++ dma_addr_t mem_bus; /* the memory address accessed from videocore */ ++ void *mem_kern; /* the memory address accessed from driver */ ++ int s = 0; ++ ++ /* allocate some memory for the messages communicating with GPU */ ++ mem_kern = dma_alloc_coherent(NULL, PAGE_ALIGN(size), &mem_bus, GFP_ATOMIC); ++ if (mem_kern) { ++ /* create the message */ ++ memcpy(mem_kern, data, size); ++ ++ /* send the message */ ++ wmb(); ++ s = bcm_mailbox_write(MBOX_CHAN_PROPERTY, (uint32_t)mem_bus); ++ if (s == 0) { ++ s = bcm_mailbox_read(MBOX_CHAN_PROPERTY, &success); ++ } ++ if (s == 0) { ++ /* copy the response */ ++ rmb(); ++ memcpy(data, mem_kern, size); ++ } ++ dma_free_coherent(NULL, PAGE_ALIGN(size), mem_kern, mem_bus); ++ } else { ++ s = -ENOMEM; ++ } ++ if (s != 0) ++ printk(KERN_ERR DRIVER_NAME ": %s failed (%d)\n", __func__, s); ++ return s; ++} ++EXPORT_SYMBOL_GPL(bcm_mailbox_property); ++ + /* ---------------------------------------------------------------------- + * Platform Device for Mailbox + * -------------------------------------------------------------------- */ +Index: linux-3.2.46/drivers/cpufreq/Kconfig.arm +=================================================================== +--- linux-3.2.46.orig/drivers/cpufreq/Kconfig.arm 2013-05-30 13:35:16.000000000 +0000 ++++ linux-3.2.46/drivers/cpufreq/Kconfig.arm 2013-07-26 19:36:28.000000000 +0000 +@@ -30,3 +30,11 @@ + SoC (S5PV310 or S5PC210). + + If in doubt, say N. ++ ++config ARM_BCM2835_CPUFREQ ++ bool "BCM2835 Driver" ++ default y ++ help ++ This adds the CPUFreq driver for BCM2835 ++ ++ If in doubt, say N. +Index: linux-3.2.46/drivers/cpufreq/Makefile +=================================================================== +--- linux-3.2.46.orig/drivers/cpufreq/Makefile 2013-05-30 13:35:16.000000000 +0000 ++++ linux-3.2.46/drivers/cpufreq/Makefile 2013-07-26 19:36:28.000000000 +0000 +@@ -43,6 +43,7 @@ + obj-$(CONFIG_ARM_S3C64XX_CPUFREQ) += s3c64xx-cpufreq.o + obj-$(CONFIG_ARM_S5PV210_CPUFREQ) += s5pv210-cpufreq.o + obj-$(CONFIG_ARM_EXYNOS4210_CPUFREQ) += exynos4210-cpufreq.o ++obj-$(CONFIG_ARM_BCM2835_CPUFREQ) += bcm2835-cpufreq.o + + ################################################################################## + # PowerPC platform drivers +Index: linux-3.2.46/drivers/cpufreq/bcm2835-cpufreq.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/cpufreq/bcm2835-cpufreq.c 2013-07-26 19:36:28.000000000 +0000 +@@ -0,0 +1,239 @@ ++/***************************************************************************** ++* Copyright 2011 Broadcom Corporation. All rights reserved. ++* ++* Unless you and Broadcom execute a separate written software license ++* agreement governing use of this software, this software is licensed to you ++* under the terms of the GNU General Public License version 2, available at ++* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). ++* ++* Notwithstanding the above, under no circumstances may you combine this ++* software in any way with any other Broadcom software provided under a ++* license other than the GPL, without Broadcom's express prior written ++* consent. ++*****************************************************************************/ ++ ++/***************************************************************************** ++* FILENAME: bcm2835-cpufreq.h ++* DESCRIPTION: This driver dynamically manages the CPU Frequency of the ARM ++* processor. Messages are sent to Videocore either setting or requesting the ++* frequency of the ARM in order to match an appropiate frequency to the current ++* usage of the processor. The policy which selects the frequency to use is ++* defined in the kernel .config file, but can be changed during runtime. ++*****************************************************************************/ ++ ++/* ---------- INCLUDES ---------- */ ++#include ++#include ++#include ++#include ++#include ++ ++/* ---------- DEFINES ---------- */ ++/*#define CPUFREQ_DEBUG_ENABLE*/ /* enable debugging */ ++#define MODULE_NAME "bcm2835-cpufreq" ++ ++#define VCMSG_ID_ARM_CLOCK 0x000000003 /* Clock/Voltage ID's */ ++ ++/* debug printk macros */ ++#ifdef CPUFREQ_DEBUG_ENABLE ++#define print_debug(fmt,...) pr_debug("%s:%s:%d: "fmt, MODULE_NAME, __func__, __LINE__, ##__VA_ARGS__) ++#else ++#define print_debug(fmt,...) ++#endif ++#define print_err(fmt,...) pr_err("%s:%s:%d: "fmt, MODULE_NAME, __func__,__LINE__, ##__VA_ARGS__) ++#define print_info(fmt,...) pr_info("%s: "fmt, MODULE_NAME, ##__VA_ARGS__) ++ ++/* tag part of the message */ ++struct vc_msg_tag { ++ uint32_t tag_id; /* the message id */ ++ uint32_t buffer_size; /* size of the buffer (which in this case is always 8 bytes) */ ++ uint32_t data_size; /* amount of data being sent or received */ ++ uint32_t dev_id; /* the ID of the clock/voltage to get or set */ ++ uint32_t val; /* the value (e.g. rate (in Hz)) to set */ ++}; ++ ++/* message structure to be sent to videocore */ ++struct vc_msg { ++ uint32_t msg_size; /* simply, sizeof(struct vc_msg) */ ++ uint32_t request_code; /* holds various information like the success and number of bytes returned (refer to mailboxes wiki) */ ++ struct vc_msg_tag tag; /* the tag structure above to make */ ++ uint32_t end_tag; /* an end identifier, should be set to NULL */ ++}; ++ ++/* ---------- GLOBALS ---------- */ ++static struct cpufreq_driver bcm2835_cpufreq_driver; /* the cpufreq driver global */ ++ ++/* ++ =============================================== ++ clk_rate either gets or sets the clock rates. ++ =============================================== ++*/ ++static uint32_t bcm2835_cpufreq_set_clock(int cur_rate, int arm_rate) ++{ ++ int s, actual_rate=0; ++ struct vc_msg msg; ++ ++ /* wipe all previous message data */ ++ memset(&msg, 0, sizeof msg); ++ ++ msg.msg_size = sizeof msg; ++ ++ msg.tag.tag_id = VCMSG_SET_CLOCK_RATE; ++ msg.tag.buffer_size = 8; ++ msg.tag.data_size = 8; /* we're sending the clock ID and the new rates which is a total of 2 words */ ++ msg.tag.dev_id = VCMSG_ID_ARM_CLOCK; ++ msg.tag.val = arm_rate * 1000; ++ ++ /* send the message */ ++ s = bcm_mailbox_property(&msg, sizeof msg); ++ ++ /* check if it was all ok and return the rate in KHz */ ++ if (s == 0 && (msg.request_code & 0x80000000)) ++ actual_rate = msg.tag.val/1000; ++ ++ print_debug("Setting new frequency = %d -> %d (actual %d)", cur_rate, arm_rate, actual_rate); ++ return actual_rate; ++} ++ ++static uint32_t bcm2835_cpufreq_get_clock(int tag) ++{ ++ int s; ++ int arm_rate = 0; ++ struct vc_msg msg; ++ ++ /* wipe all previous message data */ ++ memset(&msg, 0, sizeof msg); ++ ++ msg.msg_size = sizeof msg; ++ msg.tag.tag_id = tag; ++ msg.tag.buffer_size = 8; ++ msg.tag.data_size = 4; /* we're just sending the clock ID which is one word long */ ++ msg.tag.dev_id = VCMSG_ID_ARM_CLOCK; ++ ++ /* send the message */ ++ s = bcm_mailbox_property(&msg, sizeof msg); ++ ++ /* check if it was all ok and return the rate in KHz */ ++ if (s == 0 && (msg.request_code & 0x80000000)) ++ arm_rate = msg.tag.val/1000; ++ ++ print_debug("%s frequency = %d", ++ tag == VCMSG_GET_CLOCK_RATE ? "Current": ++ tag == VCMSG_GET_MIN_CLOCK ? "Min": ++ tag == VCMSG_GET_MAX_CLOCK ? "Max": ++ "Unexpected", arm_rate); ++ ++ return arm_rate; ++} ++ ++/* ++ ==================================================== ++ Module Initialisation registers the cpufreq driver ++ ==================================================== ++*/ ++static int __init bcm2835_cpufreq_module_init(void) ++{ ++ print_debug("IN"); ++ return cpufreq_register_driver(&bcm2835_cpufreq_driver); ++} ++ ++/* ++ ============= ++ Module exit ++ ============= ++*/ ++static void __exit bcm2835_cpufreq_module_exit(void) ++{ ++ print_debug("IN"); ++ cpufreq_unregister_driver(&bcm2835_cpufreq_driver); ++ return; ++} ++ ++/* ++ ============================================================== ++ Initialisation function sets up the CPU policy for first use ++ ============================================================== ++*/ ++static int bcm2835_cpufreq_driver_init(struct cpufreq_policy *policy) ++{ ++ /* measured value of how long it takes to change frequency */ ++ policy->cpuinfo.transition_latency = 355000; /* ns */ ++ ++ /* now find out what the maximum and minimum frequencies are */ ++ policy->min = policy->cpuinfo.min_freq = bcm2835_cpufreq_get_clock(VCMSG_GET_MIN_CLOCK); ++ policy->max = policy->cpuinfo.max_freq = bcm2835_cpufreq_get_clock(VCMSG_GET_MAX_CLOCK); ++ policy->cur = bcm2835_cpufreq_get_clock(VCMSG_GET_CLOCK_RATE); ++ ++ print_info("min=%d max=%d cur=%d", policy->min, policy->max, policy->cur); ++ return 0; ++} ++ ++/* ++ ================================================================================= ++ Target function chooses the most appropriate frequency from the table to enable ++ ================================================================================= ++*/ ++ ++static int bcm2835_cpufreq_driver_target(struct cpufreq_policy *policy, unsigned int target_freq, unsigned int relation) ++{ ++ unsigned int target = target_freq; ++ unsigned int cur = policy->cur; ++ print_debug("%s: min=%d max=%d cur=%d target=%d",policy->governor->name,policy->min,policy->max,policy->cur,target_freq); ++ ++ /* if we are above min and using ondemand, then just use max */ ++ if (strcmp("ondemand", policy->governor->name)==0 && target > policy->min) ++ target = policy->max; ++ /* if the frequency is the same, just quit */ ++ if (target == policy->cur) ++ return 0; ++ ++ /* otherwise were good to set the clock frequency */ ++ policy->cur = bcm2835_cpufreq_set_clock(policy->cur, target); ++ ++ if (!policy->cur) ++ { ++ print_err("Error occurred setting a new frequency (%d)!", target); ++ policy->cur = bcm2835_cpufreq_get_clock(VCMSG_GET_CLOCK_RATE); ++ return -EINVAL; ++ } ++ print_info("Freq %d->%d (min=%d max=%d target=%d request=%d)", cur, policy->cur, policy->min, policy->max, target_freq, target); ++ return 0; ++} ++ ++static unsigned int bcm2835_cpufreq_driver_get(unsigned int cpu) ++{ ++ unsigned int actual_rate = bcm2835_cpufreq_get_clock(VCMSG_GET_CLOCK_RATE); ++ print_debug("%d", actual_rate); ++ return actual_rate; ++} ++ ++/* ++ ================================================================================= ++ Verify ensures that when a policy is changed, it is suitable for the CPU to use ++ ================================================================================= ++*/ ++ ++static int bcm2835_cpufreq_driver_verify(struct cpufreq_policy *policy) ++{ ++ print_info("switching to governor %s", policy->governor->name); ++ return 0; ++} ++ ++ ++/* the CPUFreq driver */ ++static struct cpufreq_driver bcm2835_cpufreq_driver = { ++ .name = "BCM2835 CPUFreq", ++ .owner = THIS_MODULE, ++ .init = bcm2835_cpufreq_driver_init, ++ .verify = bcm2835_cpufreq_driver_verify, ++ .target = bcm2835_cpufreq_driver_target, ++ .get = bcm2835_cpufreq_driver_get ++}; ++ ++MODULE_AUTHOR("Dorian Peake and Dom Cobley"); ++MODULE_DESCRIPTION("CPU frequency driver for BCM2835 chip"); ++MODULE_LICENSE("GPL"); ++ ++module_init(bcm2835_cpufreq_module_init); ++module_exit(bcm2835_cpufreq_module_exit); ++ diff -Nru linux-3.2.46/debian/patches/rpi/rpi_242_fe1a4d0713cdcccd7f13b0df552f0bd65281d15d.patch linux-3.2.46/debian/patches/rpi/rpi_242_fe1a4d0713cdcccd7f13b0df552f0bd65281d15d.patch --- linux-3.2.46/debian/patches/rpi/rpi_242_fe1a4d0713cdcccd7f13b0df552f0bd65281d15d.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_242_fe1a4d0713cdcccd7f13b0df552f0bd65281d15d.patch 2013-07-26 19:36:31.000000000 +0000 @@ -0,0 +1,67 @@ +commit fe1a4d0713cdcccd7f13b0df552f0bd65281d15d +Author: popcornmix +Date: Sun Sep 9 23:47:27 2012 +0100 + + Tidy up debug messages + +Index: linux-3.2.46/sound/arm/bcm2835.c +=================================================================== +--- linux-3.2.46.orig/sound/arm/bcm2835.c 2013-07-26 19:34:22.000000000 +0000 ++++ linux-3.2.46/sound/arm/bcm2835.c 2013-07-26 19:36:30.000000000 +0000 +@@ -87,10 +87,7 @@ + bcm2835_chip_t *chip; + struct snd_card *card; + int err; +- printk(KERN_INFO "### snd_bcm2835_alsa_probe %p ###", pdev); +- +- printk +- ("############ PROBING FOR bcm2835 ALSA device (%d):(%d) ###############\n", ++ printk(KERN_INFO "Probing FOR bcm2835 ALSA device (%d):(%d)\n", + dev, enable[dev]); + + if (dev >= MAX_SUBSTREAMS) +@@ -114,7 +111,6 @@ + strcpy(g_card->shortname, "bcm2835 ALSA"); + sprintf(g_card->longname, "%s", g_card->shortname); + +- printk("Creating device/chip ..\n"); + err = snd_bcm2835_create(g_card, pdev, &chip); + if (err < 0) { + printk(KERN_ERR "Failed to create bcm2835 chip\n"); +@@ -128,7 +124,6 @@ + goto out_bcm2835_new_pcm; + } + +- printk("Adding controls ..\n"); + err = snd_bcm2835_new_ctl(chip); + if (err < 0) { + printk(KERN_ERR "Failed to create new BCM2835 ctl\n"); +@@ -145,7 +140,6 @@ + chip->pdev[dev] = pdev; + + if (dev == 0) { +- printk("Registering card ....\n"); + err = snd_card_register(card); + if (err < 0) { + printk(KERN_ERR +@@ -153,9 +147,9 @@ + goto out_card_register; + } + platform_set_drvdata(pdev, card); +- printk("bcm2835 ALSA CARD CREATED!\n"); ++ printk(KERN_INFO "bcm2835 ALSA card created!\n"); + } else { +- printk("bcm2835 ALSA CHIP CREATED!\n"); ++ printk(KERN_INFO "bcm2835 ALSA chip created!\n"); + platform_set_drvdata(pdev, (void *)dev); + } + +@@ -380,7 +374,7 @@ + printk("Error registering bcm2835_alsa7_driver %d .\n", err); + goto unregister_6; + } +- printk(KERN_INFO "### BCM2835 ALSA driver init %s ### \n", ++ printk(KERN_INFO "BCM2835 ALSA driver init %s\n", + err ? "FAILED" : "OK"); + + return 0; diff -Nru linux-3.2.46/debian/patches/rpi/rpi_243_87d5bc10fb0876be295314213ef4478a94c0e7bb.patch linux-3.2.46/debian/patches/rpi/rpi_243_87d5bc10fb0876be295314213ef4478a94c0e7bb.patch --- linux-3.2.46/debian/patches/rpi/rpi_243_87d5bc10fb0876be295314213ef4478a94c0e7bb.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_243_87d5bc10fb0876be295314213ef4478a94c0e7bb.patch 2013-07-26 19:36:32.000000000 +0000 @@ -0,0 +1,20 @@ +commit 87d5bc10fb0876be295314213ef4478a94c0e7bb +Author: popcornmix +Date: Tue Sep 11 00:58:31 2012 +0100 + + Fix for KALLSYMS_EXTRA_PASS requirement. Thanks asb for finding this. + +Index: linux-3.2.46/arch/arm/kernel/vmlinux.lds.S +=================================================================== +--- linux-3.2.46.orig/arch/arm/kernel/vmlinux.lds.S 2013-05-30 13:35:16.000000000 +0000 ++++ linux-3.2.46/arch/arm/kernel/vmlinux.lds.S 2013-07-26 19:36:31.000000000 +0000 +@@ -174,7 +174,9 @@ + } + #endif + ++#ifdef CONFIG_SMP + PERCPU_SECTION(32) ++#endif + + #ifdef CONFIG_XIP_KERNEL + __data_loc = ALIGN(4); /* location in binary */ diff -Nru linux-3.2.46/debian/patches/rpi/rpi_244_c8edb2381f299d9cc56ce99234f4e8d7061be3b2.patch linux-3.2.46/debian/patches/rpi/rpi_244_c8edb2381f299d9cc56ce99234f4e8d7061be3b2.patch --- linux-3.2.46/debian/patches/rpi/rpi_244_c8edb2381f299d9cc56ce99234f4e8d7061be3b2.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_244_c8edb2381f299d9cc56ce99234f4e8d7061be3b2.patch 2013-07-26 19:36:34.000000000 +0000 @@ -0,0 +1,203 @@ +commit c8edb2381f299d9cc56ce99234f4e8d7061be3b2 +Author: popcornmix +Date: Thu Sep 13 20:40:08 2012 +0100 + + Enable fiq fix by default. Add NAK holdoff scheme. Enabled by default, disable with dwc_otg.nak_holdoff_enable=0. Thanks gsh + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_driver.c +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/dwc_otg_driver.c 2013-07-26 19:35:59.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_driver.c 2013-07-26 19:36:32.000000000 +0000 +@@ -241,7 +241,10 @@ + }; + + //Global variable to switch the fiq fix on or off +-bool fiq_fix_enable = false; ++bool fiq_fix_enable = true; ++ ++//Global variable to switch the nak holdoff on or off ++bool nak_holdoff_enable = true; + + + /** +@@ -1086,6 +1089,7 @@ + return retval; + } + printk(KERN_DEBUG "dwc_otg: FIQ %s\n", fiq_fix_enable ? "enabled":"disabled"); ++ printk(KERN_DEBUG "dwc_otg: NAK holdoff %s\n", nak_holdoff_enable ? "enabled":"disabled"); + + error = driver_create_file(drv, &driver_attr_version); + #ifdef DEBUG +@@ -1366,9 +1370,10 @@ + module_param(microframe_schedule, bool, 0444); + MODULE_PARM_DESC(microframe_schedule, "Enable the microframe scheduler"); + +- + module_param(fiq_fix_enable, bool, 0444); + MODULE_PARM_DESC(fiq_fix_enable, "Enable the fiq fix"); ++module_param(nak_holdoff_enable, bool, 0444); ++MODULE_PARM_DESC(nak_holdoff_enable, "Enable the NAK holdoff"); + + /** @page "Module Parameters" + * +Index: linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_hcd.c +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/dwc_otg_hcd.c 2013-07-26 19:36:26.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_hcd.c 2013-07-26 19:36:32.000000000 +0000 +@@ -527,6 +527,8 @@ + { + dwc_otg_qh_t *qh; + dwc_otg_qtd_t *urb_qtd; ++ BUG_ON(!hcd); ++ BUG_ON(!dwc_otg_urb); + + #ifdef DEBUG /* integrity checks (Broadcom) */ + +@@ -543,14 +545,17 @@ + return -DWC_E_INVALID; + } + urb_qtd = dwc_otg_urb->qtd; ++ BUG_ON(!urb_qtd); + if (urb_qtd->qh == NULL) { + DWC_ERROR("**** DWC OTG HCD URB Dequeue with QTD with NULL Q handler\n"); + return -DWC_E_INVALID; + } + #else + urb_qtd = dwc_otg_urb->qtd; ++ BUG_ON(!urb_qtd); + #endif + qh = urb_qtd->qh; ++ BUG_ON(!qh); + if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) { + if (urb_qtd->in_process) { + dump_channel_info(hcd, qh); +@@ -1309,6 +1314,22 @@ + num_channels - hcd->periodic_channels) && + !DWC_CIRCLEQ_EMPTY(&hcd->free_hc_list)) { + ++ qh = DWC_LIST_ENTRY(qh_ptr, dwc_otg_qh_t, qh_list_entry); ++ ++ /* ++ * Check to see if this is a NAK'd retransmit, in which case ignore for retransmission ++ * we hold off on bulk retransmissions to reduce NAK interrupt overhead for ++ * cheeky devices that just hold off using NAKs ++ */ ++ if (dwc_full_frame_num(qh->nak_frame) == dwc_full_frame_num(dwc_otg_hcd_get_frame_number(hcd))) { ++ // Make fiq interrupt run on next frame (i.e. 8 uframes) ++ g_next_sched_frame = ((qh->nak_frame + 8) & ~7) & DWC_HFNUM_MAX_FRNUM; ++ qh_ptr = DWC_LIST_NEXT(qh_ptr); ++ continue; ++ } ++ else ++ qh->nak_frame = 0xffff; ++ + if (microframe_schedule) { + DWC_SPINLOCK_IRQSAVE(channel_lock, &flags); + if (hcd->available_host_channels < 1) { +@@ -1321,7 +1342,6 @@ + last_sel_trans_num_nonper_scheduled++; + #endif /* DEBUG_HOST_CHANNELS */ + } +- qh = DWC_LIST_ENTRY(qh_ptr, dwc_otg_qh_t, qh_list_entry); + + assign_and_init_hc(hcd, qh); + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_hcd.h +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/dwc_otg_hcd.h 2013-07-26 19:36:26.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_hcd.h 2013-07-26 19:36:32.000000000 +0000 +@@ -321,6 +321,11 @@ + */ + uint16_t sched_frame; + ++ /* ++ ** Frame a NAK was received on this queue head, used to minimise NAK retransmission ++ */ ++ uint16_t nak_frame; ++ + /** (micro)frame at which last start split was initialized. */ + uint16_t start_split_frame; + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c 2013-07-26 19:36:26.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c 2013-07-26 19:36:32.000000000 +0000 +@@ -56,7 +56,12 @@ + int g_next_sched_frame, g_np_count, g_np_sent, g_work_expected; + static int mphi_int_count = 0 ; + +-extern bool fiq_fix_enable; ++extern bool fiq_fix_enable, nak_holdoff_enable; ++ ++hcchar_data_t nak_hcchar; ++hctsiz_data_t nak_hctsiz; ++hcsplt_data_t nak_hcsplt; ++int nak_count; + + void __attribute__ ((naked)) dwc_otg_hcd_handle_fiq(void) + { +@@ -230,7 +235,7 @@ + DWC_WRITE_REG32(c_mphi_regs.ctrl, (1<<31)); + mphi_int_count = 0; + } +- int_done++; ++ int_done++; + if((jiffies / HZ) > last_time) + { + /* Once a second output the fiq and irq numbers, useful for debug */ +@@ -1419,6 +1424,18 @@ + "NAK Received--\n", hc->hc_num); + + /* ++ * When we get bulk NAKs then remember this so we holdoff on this qh until ++ * the beginning of the next frame ++ */ ++ switch(dwc_otg_hcd_get_pipe_type(&qtd->urb->pipe_info)) { ++ case UE_BULK: ++ //case UE_INTERRUPT: ++ //case UE_CONTROL: ++ if (nak_holdoff_enable) ++ hc->qh->nak_frame = dwc_otg_hcd_get_frame_number(hcd); ++ } ++ ++ /* + * Handle NAK for IN/OUT SSPLIT/CSPLIT transfers, bulk, control, and + * interrupt. Re-start the SSPLIT transfer. + */ +Index: linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_hcd_queue.c +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/dwc_otg_hcd_queue.c 2013-07-26 19:35:59.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_hcd_queue.c 2013-07-26 19:36:32.000000000 +0000 +@@ -181,6 +181,7 @@ + if (microframe_schedule) + qh->speed = dev_speed; + ++ qh->nak_frame = 0xffff; + + if (((dev_speed == USB_SPEED_LOW) || + (dev_speed == USB_SPEED_FULL)) && +@@ -764,6 +765,24 @@ + int sched_next_periodic_split) + { + if (dwc_qh_is_non_per(qh)) { ++ ++ dwc_otg_qh_t *qh_tmp; ++ dwc_list_link_t *qh_list; ++ DWC_LIST_FOREACH(qh_list, &hcd->non_periodic_sched_inactive) ++ { ++ qh_tmp = DWC_LIST_ENTRY(qh_list, struct dwc_otg_qh, qh_list_entry); ++ if(qh_tmp == qh) ++ { ++ /* ++ * FIQ is being disabled because this one nevers gets a np_count increment ++ * This is still not absolutely correct, but it should fix itself with ++ * just an unnecessary extra interrupt ++ */ ++ g_np_sent = g_np_count; ++ } ++ } ++ ++ + dwc_otg_hcd_qh_remove(hcd, qh); + if (!DWC_CIRCLEQ_EMPTY(&qh->qtd_list)) { + /* Add back to inactive non-periodic schedule. */ diff -Nru linux-3.2.46/debian/patches/rpi/rpi_245_e33263e7eab2d05349b438f6a4a8d1924686a824.patch linux-3.2.46/debian/patches/rpi/rpi_245_e33263e7eab2d05349b438f6a4a8d1924686a824.patch --- linux-3.2.46/debian/patches/rpi/rpi_245_e33263e7eab2d05349b438f6a4a8d1924686a824.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_245_e33263e7eab2d05349b438f6a4a8d1924686a824.patch 2013-07-26 19:36:35.000000000 +0000 @@ -0,0 +1,510 @@ +commit e33263e7eab2d05349b438f6a4a8d1924686a824 +Author: popcornmix +Date: Thu Sep 13 20:41:44 2012 +0100 + + Added hwmon/thermal driver for reporting core temperature. Thanks Dorian + +Index: linux-3.2.46/arch/arm/mach-bcm2708/bcm2708.c +=================================================================== +--- linux-3.2.46.orig/arch/arm/mach-bcm2708/bcm2708.c 2013-07-26 19:35:59.000000000 +0000 ++++ linux-3.2.46/arch/arm/mach-bcm2708/bcm2708.c 2013-07-26 19:36:34.000000000 +0000 +@@ -592,6 +592,14 @@ + .resource = bcm2708_bsc1_resources, + }; + ++static struct platform_device bcm2835_hwmon_device = { ++ .name = "bcm2835_hwmon", ++}; ++ ++static struct platform_device bcm2835_thermal_device = { ++ .name = "bcm2835_thermal", ++}; ++ + int __init bcm_register_device(struct platform_device *pdev) + { + int ret; +@@ -656,6 +664,9 @@ + bcm_register_device(&bcm2708_bsc0_device); + bcm_register_device(&bcm2708_bsc1_device); + ++ bcm_register_device(&bcm2835_hwmon_device); ++ bcm_register_device(&bcm2835_thermal_device); ++ + #ifdef CONFIG_BCM2708_VCMEM + { + extern void vc_mem_connected_init(void); +Index: linux-3.2.46/drivers/hwmon/Kconfig +=================================================================== +--- linux-3.2.46.orig/drivers/hwmon/Kconfig 2013-07-26 19:17:50.000000000 +0000 ++++ linux-3.2.46/drivers/hwmon/Kconfig 2013-07-26 19:36:34.000000000 +0000 +@@ -1361,6 +1361,15 @@ + help + Support for the A/D converter on MC13783 PMIC. + ++config SENSORS_BCM2835 ++ tristate "Broadcom BCM2835 HWMON Driver" ++ help ++ If you say yes here you get support for the hardware ++ monitoring features of the BCM2835 Chip ++ ++ This driver can also be built as a module. If so, the module ++ will be called bcm2835-hwmon. ++ + if ACPI + + comment "ACPI drivers" +Index: linux-3.2.46/drivers/hwmon/Makefile +=================================================================== +--- linux-3.2.46.orig/drivers/hwmon/Makefile 2013-05-30 13:35:16.000000000 +0000 ++++ linux-3.2.46/drivers/hwmon/Makefile 2013-07-26 19:36:34.000000000 +0000 +@@ -125,6 +125,7 @@ + obj-$(CONFIG_SENSORS_W83L786NG) += w83l786ng.o + obj-$(CONFIG_SENSORS_WM831X) += wm831x-hwmon.o + obj-$(CONFIG_SENSORS_WM8350) += wm8350-hwmon.o ++obj-$(CONFIG_SENSORS_BCM2835) += bcm2835-hwmon.o + + obj-$(CONFIG_PMBUS) += pmbus/ + +Index: linux-3.2.46/drivers/hwmon/bcm2835-hwmon.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/hwmon/bcm2835-hwmon.c 2013-07-26 19:36:34.000000000 +0000 +@@ -0,0 +1,211 @@ ++//bcm2835-hwmon.c ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define MODULE_NAME "bcm2835_hwmon" ++ ++/*#define HWMON_DEBUG_ENABLE*/ ++ ++#ifdef HWMON_DEBUG_ENABLE ++#define print_debug(fmt,...) printk(KERN_INFO "%s:%s:%d: "fmt"\n", MODULE_NAME, __func__, __LINE__, ##__VA_ARGS__) ++#else ++#define print_debug(fmt,...) ++#endif ++#define print_err(fmt,...) printk(KERN_ERR "%s:%s:%d: "fmt"\n", MODULE_NAME, __func__,__LINE__, ##__VA_ARGS__) ++#define print_info(fmt,...) printk(KERN_INFO "%s: "fmt"\n", MODULE_NAME, ##__VA_ARGS__) ++ ++#define VC_TAG_GET_TEMP 0x00030006 ++#define VC_TAG_GET_MAX_TEMP 0x0003000A ++struct bcm2835_hwmon_data { ++ struct device *hwmon_dev; ++}; ++ ++/* --- STRUCTS --- */ ++ ++/* tag part of the message */ ++struct vc_msg_tag { ++ uint32_t tag_id; /* the tag ID for the temperature */ ++ uint32_t buffer_size; /* size of the buffer (should be 8) */ ++ uint32_t request_code; /* identifies message as a request (should be 0) */ ++ uint32_t id; /* extra ID field (should be 0) */ ++ uint32_t val; /* returned value of the temperature */ ++}; ++ ++/* message structure to be sent to videocore */ ++struct vc_msg { ++ uint32_t msg_size; /* simply, sizeof(struct vc_msg) */ ++ uint32_t request_code; /* holds various information like the success and number of bytes returned (refer to mailboxes wiki) */ ++ struct vc_msg_tag tag; /* the tag structure above to make */ ++ uint32_t end_tag; /* an end identifier, should be set to NULL */ ++}; ++ ++typedef enum { ++ TEMP, ++ MAX_TEMP, ++} temp_type; ++ ++/* --- PROTOTYPES --- */ ++static ssize_t bcm2835_get_temp(struct device *dev, struct device_attribute *attr, char *buf); ++static ssize_t bcm2835_get_name(struct device *dev, struct device_attribute *attr, char *buf); ++ ++/* --- GLOBALS --- */ ++ ++static struct bcm2835_hwmon_data *bcm2835_data; ++static struct platform_driver bcm2835_hwmon_driver; ++ ++static SENSOR_DEVICE_ATTR(name, S_IRUGO,bcm2835_get_name,NULL,0); ++static SENSOR_DEVICE_ATTR(temp1_input,S_IRUGO,bcm2835_get_temp,NULL,TEMP); ++static SENSOR_DEVICE_ATTR(temp,S_IRUGO,bcm2835_get_temp,NULL,TEMP); ++static SENSOR_DEVICE_ATTR(temp1_max,S_IRUGO,bcm2835_get_temp,NULL,MAX_TEMP); ++static SENSOR_DEVICE_ATTR(trip_point_0_temp,S_IRUGO,bcm2835_get_temp,NULL,MAX_TEMP); ++ ++static struct attribute* bcm2835_attributes[] = { ++ &sensor_dev_attr_name.dev_attr.attr, ++ &sensor_dev_attr_temp1_input.dev_attr.attr, ++ &sensor_dev_attr_temp1_max.dev_attr.attr, ++ &sensor_dev_attr_temp.dev_attr.attr, ++ &sensor_dev_attr_trip_point_0_temp.dev_attr.attr, ++ NULL, ++}; ++ ++static struct attribute_group bcm2835_attr_group = { ++ .attrs = bcm2835_attributes, ++}; ++ ++/* --- FUNCTIONS --- */ ++ ++static ssize_t bcm2835_get_name(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ return sprintf(buf,"bcm2835_hwmon\n"); ++} ++ ++static ssize_t bcm2835_get_temp(struct device *dev, struct device_attribute *attr, char *buf) ++{ ++ struct vc_msg msg; ++ int result; ++ uint temp = 0; ++ int index = ((struct sensor_device_attribute*)to_sensor_dev_attr(attr))->index; ++ ++ print_debug("IN"); ++ ++ /* wipe all previous message data */ ++ memset(&msg, 0, sizeof msg); ++ ++ /* determine the message type */ ++ if(index == TEMP) ++ msg.tag.tag_id = VC_TAG_GET_TEMP; ++ else if (index == MAX_TEMP) ++ msg.tag.tag_id = VC_TAG_GET_MAX_TEMP; ++ else ++ { ++ print_debug("Unknown temperature message!"); ++ return -EINVAL; ++ } ++ ++ msg.msg_size = sizeof msg; ++ msg.tag.buffer_size = 8; ++ ++ /* send the message */ ++ result = bcm_mailbox_property(&msg, sizeof msg); ++ ++ /* check if it was all ok and return the rate in milli degrees C */ ++ if (result == 0 && (msg.request_code & 0x80000000)) ++ temp = (uint)msg.tag.val; ++ #ifdef HWMON_DEBUG_ENABLE ++ else ++ print_debug("Failed to get temperature!"); ++ #endif ++ print_debug("Got temperature as %u",temp); ++ print_debug("OUT"); ++ return sprintf(buf, "%u\n", temp); ++} ++ ++ ++static int bcm2835_hwmon_probe(struct platform_device *pdev) ++{ ++ int err; ++ ++ print_debug("IN"); ++ print_debug("HWMON Driver has been probed!"); ++ ++ /* check that the device isn't null!*/ ++ if(pdev == NULL) ++ { ++ print_debug("Platform device is empty!"); ++ return -ENODEV; ++ } ++ ++ /* allocate memory for neccessary data */ ++ bcm2835_data = kzalloc(sizeof(struct bcm2835_hwmon_data),GFP_KERNEL); ++ if(!bcm2835_data) ++ { ++ print_debug("Unable to allocate memory for hwmon data!"); ++ err = -ENOMEM; ++ goto kzalloc_error; ++ } ++ ++ /* create the sysfs files */ ++ if(sysfs_create_group(&pdev->dev.kobj, &bcm2835_attr_group)) ++ { ++ print_debug("Unable to create sysfs files!"); ++ err = -EFAULT; ++ goto sysfs_error; ++ } ++ ++ /* register the hwmon device */ ++ bcm2835_data->hwmon_dev = hwmon_device_register(&pdev->dev); ++ if (IS_ERR(bcm2835_data->hwmon_dev)) ++ { ++ err = PTR_ERR(bcm2835_data->hwmon_dev); ++ goto hwmon_error; ++ } ++ print_debug("OUT"); ++ return 0; ++ ++ /* error goto's */ ++ hwmon_error: ++ sysfs_remove_group(&pdev->dev.kobj, &bcm2835_attr_group); ++ ++ sysfs_error: ++ kfree(bcm2835_data); ++ ++ kzalloc_error: ++ ++ return err; ++ ++} ++ ++static int bcm2835_hwmon_remove(struct platform_device *pdev) ++{ ++ print_debug("IN"); ++ hwmon_device_unregister(bcm2835_data->hwmon_dev); ++ ++ sysfs_remove_group(&pdev->dev.kobj, &bcm2835_attr_group); ++ print_debug("OUT"); ++ return 0; ++} ++ ++/* Hwmon Driver */ ++static struct platform_driver bcm2835_hwmon_driver = { ++ .probe = bcm2835_hwmon_probe, ++ .remove = bcm2835_hwmon_remove, ++ .driver = { ++ .name = "bcm2835_hwmon", ++ .owner = THIS_MODULE, ++ }, ++}; ++ ++MODULE_LICENSE("GPL"); ++MODULE_AUTHOR("Dorian Peake"); ++MODULE_DESCRIPTION("HW Monitor driver for bcm2835 chip"); ++ ++module_platform_driver(bcm2835_hwmon_driver); +Index: linux-3.2.46/drivers/thermal/Kconfig +=================================================================== +--- linux-3.2.46.orig/drivers/thermal/Kconfig 2013-05-30 13:35:16.000000000 +0000 ++++ linux-3.2.46/drivers/thermal/Kconfig 2013-07-26 19:36:34.000000000 +0000 +@@ -18,3 +18,13 @@ + depends on THERMAL + depends on HWMON=y || HWMON=THERMAL + default y ++ ++if THERMAL ++ ++config THERMAL_BCM2835 ++ tristate "BCM2835 Thermal Driver" ++ help ++ This will enable temperature monitoring for the Broadcom BCM2835 ++ chip. If built as a module, it will be called 'bcm2835-thermal'. ++ ++endif # THERMAL_BCM2835 +Index: linux-3.2.46/drivers/thermal/Makefile +=================================================================== +--- linux-3.2.46.orig/drivers/thermal/Makefile 2013-05-30 13:35:16.000000000 +0000 ++++ linux-3.2.46/drivers/thermal/Makefile 2013-07-26 19:36:34.000000000 +0000 +@@ -3,3 +3,4 @@ + # + + obj-$(CONFIG_THERMAL) += thermal_sys.o ++obj-$(CONFIG_THERMAL_BCM2835) += bcm2835-thermal.o +Index: linux-3.2.46/drivers/thermal/bcm2835-thermal.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/thermal/bcm2835-thermal.c 2013-07-26 19:36:34.000000000 +0000 +@@ -0,0 +1,195 @@ ++//bcm2835-thermal.c ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++ ++/* --- DEFINITIONS --- */ ++#define MODULE_NAME "bcm2835_thermal" ++ ++/*#define THERMAL_DEBUG_ENABLE*/ ++ ++#ifdef THERMAL_DEBUG_ENABLE ++#define print_debug(fmt,...) printk(KERN_INFO "%s:%s:%d: "fmt"\n", MODULE_NAME, __func__, __LINE__, ##__VA_ARGS__) ++#else ++#define print_debug(fmt,...) ++#endif ++#define print_err(fmt,...) printk(KERN_ERR "%s:%s:%d: "fmt"\n", MODULE_NAME, __func__,__LINE__, ##__VA_ARGS__) ++#define print_info(fmt,...) printk(KERN_INFO "%s: "fmt"\n", MODULE_NAME, ##__VA_ARGS__) ++ ++#define VC_TAG_GET_TEMP 0x00030006 ++#define VC_TAG_GET_MAX_TEMP 0x0003000A ++ ++typedef enum { ++ TEMP, ++ MAX_TEMP, ++} temp_type; ++ ++/* --- STRUCTS --- */ ++/* tag part of the message */ ++struct vc_msg_tag { ++ uint32_t tag_id; /* the tag ID for the temperature */ ++ uint32_t buffer_size; /* size of the buffer (should be 8) */ ++ uint32_t request_code; /* identifies message as a request (should be 0) */ ++ uint32_t id; /* extra ID field (should be 0) */ ++ uint32_t val; /* returned value of the temperature */ ++}; ++ ++/* message structure to be sent to videocore */ ++struct vc_msg { ++ uint32_t msg_size; /* simply, sizeof(struct vc_msg) */ ++ uint32_t request_code; /* holds various information like the success and number of bytes returned (refer to mailboxes wiki) */ ++ struct vc_msg_tag tag; /* the tag structure above to make */ ++ uint32_t end_tag; /* an end identifier, should be set to NULL */ ++}; ++ ++struct bcm2835_thermal_data { ++ struct thermal_zone_device *thermal_dev; ++ struct vc_msg msg; ++}; ++ ++/* --- PROTOTYPES --- */ ++static int bcm2835_get_temp(struct thermal_zone_device *thermal_dev, unsigned long *); ++static int bcm2835_get_max_temp(struct thermal_zone_device *thermal_dev, int, unsigned long *); ++static int bcm2835_get_trip_type(struct thermal_zone_device *thermal_dev, int trip_num, enum thermal_trip_type *trip_type); ++static int bcm2835_get_mode(struct thermal_zone_device *thermal_dev, enum thermal_device_mode *dev_mode); ++ ++/* --- GLOBALS --- */ ++static struct bcm2835_thermal_data bcm2835_data; ++ ++/* Thermal Device Operations */ ++static struct thermal_zone_device_ops ops; ++ ++/* --- FUNCTIONS --- */ ++static int bcm2835_get_max_temp(struct thermal_zone_device *thermal_dev, int trip_num, unsigned long *temp) ++{ ++ int result; ++ ++ print_debug("IN"); ++ ++ /* wipe all previous message data */ ++ memset(&bcm2835_data.msg, 0, sizeof bcm2835_data.msg); ++ ++ /* prepare message */ ++ bcm2835_data.msg.msg_size = sizeof bcm2835_data.msg; ++ bcm2835_data.msg.tag.buffer_size = 8; ++ bcm2835_data.msg.tag.tag_id = VC_TAG_GET_MAX_TEMP; ++ ++ /* send the message */ ++ result = bcm_mailbox_property(&bcm2835_data.msg, sizeof bcm2835_data.msg); ++ ++ /* check if it was all ok and return the rate in milli degrees C */ ++ if (result == 0 && (bcm2835_data.msg.request_code & 0x80000000)) ++ *temp = (uint)bcm2835_data.msg.tag.val; ++ #ifdef THERMAL_DEBUG_ENABLE ++ else ++ print_debug("Failed to get temperature!"); ++ #endif ++ print_debug("Got temperature as %u",(uint)*temp); ++ print_debug("OUT"); ++ return 0; ++} ++ ++static int bcm2835_get_temp(struct thermal_zone_device *thermal_dev, unsigned long *temp) ++{ ++ int result; ++ ++ print_debug("IN"); ++ ++ /* wipe all previous message data */ ++ memset(&bcm2835_data.msg, 0, sizeof bcm2835_data.msg); ++ ++ /* prepare message */ ++ bcm2835_data.msg.msg_size = sizeof bcm2835_data.msg; ++ bcm2835_data.msg.tag.buffer_size = 8; ++ bcm2835_data.msg.tag.tag_id = VC_TAG_GET_TEMP; ++ ++ /* send the message */ ++ result = bcm_mailbox_property(&bcm2835_data.msg, sizeof bcm2835_data.msg); ++ ++ /* check if it was all ok and return the rate in milli degrees C */ ++ if (result == 0 && (bcm2835_data.msg.request_code & 0x80000000)) ++ *temp = (uint)bcm2835_data.msg.tag.val; ++ #ifdef THERMAL_DEBUG_ENABLE ++ else ++ print_debug("Failed to get temperature!"); ++ #endif ++ print_debug("Got temperature as %u",(uint)*temp); ++ print_debug("OUT"); ++ return 0; ++} ++ ++ ++static int bcm2835_get_trip_type(struct thermal_zone_device * thermal_dev, int trip_num, enum thermal_trip_type *trip_type) ++{ ++ *trip_type = THERMAL_TRIP_HOT; ++ return 0; ++} ++ ++ ++static int bcm2835_get_mode(struct thermal_zone_device *thermal_dev, enum thermal_device_mode *dev_mode) ++{ ++ *dev_mode = THERMAL_DEVICE_ENABLED; ++ return 0; ++} ++ ++ ++static int bcm2835_thermal_probe(struct platform_device *pdev) ++{ ++ print_debug("IN"); ++ print_debug("THERMAL Driver has been probed!"); ++ ++ /* check that the device isn't null!*/ ++ if(pdev == NULL) ++ { ++ print_debug("Platform device is empty!"); ++ return -ENODEV; ++ } ++ ++ if(!(bcm2835_data.thermal_dev = thermal_zone_device_register("bcm2835_thermal", 1, NULL, &ops,1,1,1000,1000))) ++ { ++ print_debug("Unable to register the thermal device!"); ++ return -EFAULT; ++ } ++ return 0; ++} ++ ++ ++static int bcm2835_thermal_remove(struct platform_device *pdev) ++{ ++ print_debug("IN"); ++ ++ thermal_zone_device_unregister(bcm2835_data.thermal_dev); ++ ++ print_debug("OUT"); ++ ++ return 0; ++} ++ ++static struct thermal_zone_device_ops ops = { ++ .get_temp = bcm2835_get_temp, ++ .get_trip_temp = bcm2835_get_max_temp, ++ .get_trip_type = bcm2835_get_trip_type, ++ .get_mode = bcm2835_get_mode, ++}; ++ ++/* Thermal Driver */ ++static struct platform_driver bcm2835_thermal_driver = { ++ .probe = bcm2835_thermal_probe, ++ .remove = bcm2835_thermal_remove, ++ .driver = { ++ .name = "bcm2835_thermal", ++ .owner = THIS_MODULE, ++ }, ++}; ++ ++MODULE_LICENSE("GPL"); ++MODULE_AUTHOR("Dorian Peake"); ++MODULE_DESCRIPTION("Thermal driver for bcm2835 chip"); ++ ++module_platform_driver(bcm2835_thermal_driver); diff -Nru linux-3.2.46/debian/patches/rpi/rpi_246_ce4ab6222b47270b1597ce3cd7c0a354346d348d.patch linux-3.2.46/debian/patches/rpi/rpi_246_ce4ab6222b47270b1597ce3cd7c0a354346d348d.patch --- linux-3.2.46/debian/patches/rpi/rpi_246_ce4ab6222b47270b1597ce3cd7c0a354346d348d.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_246_ce4ab6222b47270b1597ce3cd7c0a354346d348d.patch 2013-07-26 19:36:37.000000000 +0000 @@ -0,0 +1,158 @@ +commit ce4ab6222b47270b1597ce3cd7c0a354346d348d +Author: popcornmix +Date: Fri Sep 14 16:19:10 2012 +0100 + + Add config options for thermal sensor, L2TP, RT2800USB_UNKNOWN, and various I2C and SPI RTCs. Tidy of thermal driver. + +Index: linux-3.2.46/arch/arm/configs/bcmrpi_defconfig +=================================================================== +--- linux-3.2.46.orig/arch/arm/configs/bcmrpi_defconfig 2013-07-26 19:36:28.000000000 +0000 ++++ linux-3.2.46/arch/arm/configs/bcmrpi_defconfig 2013-07-26 19:36:36.000000000 +0000 +@@ -229,6 +229,7 @@ + CONFIG_BRIDGE_EBT_LOG=m + CONFIG_BRIDGE_EBT_ULOG=m + CONFIG_BRIDGE_EBT_NFLOG=m ++CONFIG_L2TP=m + CONFIG_BRIDGE=m + CONFIG_VLAN_8021Q=m + CONFIG_VLAN_8021Q_GVRP=y +@@ -424,6 +425,7 @@ + CONFIG_RT73USB=m + CONFIG_RT2800USB=m + CONFIG_RT2800USB_RT53XX=y ++CONFIG_RT2800USB_UNKNOWN=y + CONFIG_WL1251=m + CONFIG_WL12XX_MENU=m + CONFIG_ZD1211RW=m +@@ -483,6 +485,8 @@ + CONFIG_W1_SLAVE_DS2780=m + CONFIG_W1_SLAVE_BQ27000=m + # CONFIG_HWMON is not set ++CONFIG_THERMAL=y ++CONFIG_THERMAL_BCM2835=y + CONFIG_WATCHDOG=y + CONFIG_BCM2708_WDT=m + CONFIG_MEDIA_SUPPORT=m +@@ -769,6 +773,33 @@ + CONFIG_LEDS_TRIGGER_DEFAULT_ON=m + CONFIG_RTC_CLASS=y + CONFIG_RTC_DRV_DS1307=m ++CONFIG_RTC_DRV_DS1374=m ++CONFIG_RTC_DRV_DS1672=m ++CONFIG_RTC_DRV_DS3232=m ++CONFIG_RTC_DRV_MAX6900=m ++CONFIG_RTC_DRV_RS5C372=m ++CONFIG_RTC_DRV_ISL1208=m ++CONFIG_RTC_DRV_ISL12022=m ++CONFIG_RTC_DRV_X1205=m ++CONFIG_RTC_DRV_PCF8563=m ++CONFIG_RTC_DRV_PCF8583=m ++CONFIG_RTC_DRV_M41T80=m ++CONFIG_RTC_DRV_BQ32K=m ++CONFIG_RTC_DRV_S35390A=m ++CONFIG_RTC_DRV_FM3130=m ++CONFIG_RTC_DRV_RX8581=m ++CONFIG_RTC_DRV_RX8025=m ++CONFIG_RTC_DRV_EM3027=m ++CONFIG_RTC_DRV_RV3029C2=m ++CONFIG_RTC_DRV_M41T93=m ++CONFIG_RTC_DRV_M41T94=m ++CONFIG_RTC_DRV_DS1305=m ++CONFIG_RTC_DRV_DS1390=m ++CONFIG_RTC_DRV_MAX6902=m ++CONFIG_RTC_DRV_R9701=m ++CONFIG_RTC_DRV_RS5C348=m ++CONFIG_RTC_DRV_DS3234=m ++CONFIG_RTC_DRV_PCF2123=m + CONFIG_UIO=m + CONFIG_UIO_PDRV=m + CONFIG_UIO_PDRV_GENIRQ=m +Index: linux-3.2.46/drivers/hwmon/Kconfig +=================================================================== +--- linux-3.2.46.orig/drivers/hwmon/Kconfig 2013-07-26 19:36:34.000000000 +0000 ++++ linux-3.2.46/drivers/hwmon/Kconfig 2013-07-26 19:36:36.000000000 +0000 +@@ -1362,6 +1362,7 @@ + Support for the A/D converter on MC13783 PMIC. + + config SENSORS_BCM2835 ++ depends on THERMAL_BCM2835=n + tristate "Broadcom BCM2835 HWMON Driver" + help + If you say yes here you get support for the hardware +Index: linux-3.2.46/drivers/hwmon/bcm2835-hwmon.c +=================================================================== +--- linux-3.2.46.orig/drivers/hwmon/bcm2835-hwmon.c 2013-07-26 19:36:34.000000000 +0000 ++++ linux-3.2.46/drivers/hwmon/bcm2835-hwmon.c 2013-07-26 19:36:36.000000000 +0000 +@@ -1,4 +1,16 @@ +-//bcm2835-hwmon.c ++/***************************************************************************** ++* Copyright 2011 Broadcom Corporation. All rights reserved. ++* ++* Unless you and Broadcom execute a separate written software license ++* agreement governing use of this software, this software is licensed to you ++* under the terms of the GNU General Public License version 2, available at ++* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). ++* ++* Notwithstanding the above, under no circumstances may you combine this ++* software in any way with any other Broadcom software provided under a ++* license other than the GPL, without Broadcom's express prior written ++* consent. ++*****************************************************************************/ + + #include + #include +@@ -25,12 +37,12 @@ + + #define VC_TAG_GET_TEMP 0x00030006 + #define VC_TAG_GET_MAX_TEMP 0x0003000A ++ ++/* --- STRUCTS --- */ + struct bcm2835_hwmon_data { + struct device *hwmon_dev; + }; + +-/* --- STRUCTS --- */ +- + /* tag part of the message */ + struct vc_msg_tag { + uint32_t tag_id; /* the tag ID for the temperature */ +@@ -64,16 +76,12 @@ + + static SENSOR_DEVICE_ATTR(name, S_IRUGO,bcm2835_get_name,NULL,0); + static SENSOR_DEVICE_ATTR(temp1_input,S_IRUGO,bcm2835_get_temp,NULL,TEMP); +-static SENSOR_DEVICE_ATTR(temp,S_IRUGO,bcm2835_get_temp,NULL,TEMP); + static SENSOR_DEVICE_ATTR(temp1_max,S_IRUGO,bcm2835_get_temp,NULL,MAX_TEMP); +-static SENSOR_DEVICE_ATTR(trip_point_0_temp,S_IRUGO,bcm2835_get_temp,NULL,MAX_TEMP); + + static struct attribute* bcm2835_attributes[] = { + &sensor_dev_attr_name.dev_attr.attr, + &sensor_dev_attr_temp1_input.dev_attr.attr, + &sensor_dev_attr_temp1_max.dev_attr.attr, +- &sensor_dev_attr_temp.dev_attr.attr, +- &sensor_dev_attr_trip_point_0_temp.dev_attr.attr, + NULL, + }; + +Index: linux-3.2.46/drivers/thermal/bcm2835-thermal.c +=================================================================== +--- linux-3.2.46.orig/drivers/thermal/bcm2835-thermal.c 2013-07-26 19:36:34.000000000 +0000 ++++ linux-3.2.46/drivers/thermal/bcm2835-thermal.c 2013-07-26 19:36:36.000000000 +0000 +@@ -1,4 +1,17 @@ +-//bcm2835-thermal.c ++/***************************************************************************** ++* Copyright 2011 Broadcom Corporation. All rights reserved. ++* ++* Unless you and Broadcom execute a separate written software license ++* agreement governing use of this software, this software is licensed to you ++* under the terms of the GNU General Public License version 2, available at ++* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). ++* ++* Notwithstanding the above, under no circumstances may you combine this ++* software in any way with any other Broadcom software provided under a ++* license other than the GPL, without Broadcom's express prior written ++* consent. ++*****************************************************************************/ ++ + #include + #include + #include diff -Nru linux-3.2.46/debian/patches/rpi/rpi_247_d8a00ed27f71d12d5ba02d18f53c8834e5b2b319.patch linux-3.2.46/debian/patches/rpi/rpi_247_d8a00ed27f71d12d5ba02d18f53c8834e5b2b319.patch --- linux-3.2.46/debian/patches/rpi/rpi_247_d8a00ed27f71d12d5ba02d18f53c8834e5b2b319.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_247_d8a00ed27f71d12d5ba02d18f53c8834e5b2b319.patch 2013-07-26 19:36:38.000000000 +0000 @@ -0,0 +1,188 @@ +commit d8a00ed27f71d12d5ba02d18f53c8834e5b2b319 +Author: popcornmix +Date: Mon Sep 17 18:17:56 2012 +0100 + + Remove some unnecessary dmesg output. + +Index: linux-3.2.46/drivers/cpufreq/bcm2835-cpufreq.c +=================================================================== +--- linux-3.2.46.orig/drivers/cpufreq/bcm2835-cpufreq.c 2013-07-26 19:36:28.000000000 +0000 ++++ linux-3.2.46/drivers/cpufreq/bcm2835-cpufreq.c 2013-07-26 19:36:37.000000000 +0000 +@@ -196,7 +196,7 @@ + policy->cur = bcm2835_cpufreq_get_clock(VCMSG_GET_CLOCK_RATE); + return -EINVAL; + } +- print_info("Freq %d->%d (min=%d max=%d target=%d request=%d)", cur, policy->cur, policy->min, policy->max, target_freq, target); ++ print_debug("Freq %d->%d (min=%d max=%d target=%d request=%d)", cur, policy->cur, policy->min, policy->max, target_freq, target); + return 0; + } + +Index: linux-3.2.46/drivers/video/bcm2708_fb.c +=================================================================== +--- linux-3.2.46.orig/drivers/video/bcm2708_fb.c 2013-07-26 19:34:09.000000000 +0000 ++++ linux-3.2.46/drivers/video/bcm2708_fb.c 2013-07-26 19:36:37.000000000 +0000 +@@ -36,6 +36,12 @@ + #include + #include + ++#ifdef BCM2708_FB_DEBUG ++#define print_debug(fmt,...) pr_debug("%s:%s:%d: "fmt, MODULE_NAME, __func__, __LINE__, ##__VA_ARGS__) ++#else ++#define print_debug(fmt,...) ++#endif ++ + /* This is limited to 16 characters when displayed by X startup */ + static const char *bcm2708_name = "BCM2708 FB"; + +@@ -135,17 +141,15 @@ + { + /* info input, var output */ + int yres; +- /* memory size in pixels */ +- unsigned pixels = info->screen_size * 8 / var->bits_per_pixel; + + /* info input, var output */ +- pr_info("bcm2708_fb_check_var info(%p) %dx%d (%dx%d), %d, %d\n", info, ++ print_debug("bcm2708_fb_check_var info(%p) %dx%d (%dx%d), %d, %d\n", info, + info->var.xres, info->var.yres, info->var.xres_virtual, + info->var.yres_virtual, (int)info->screen_size, + info->var.bits_per_pixel); +- pr_info("bcm2708_fb_check_var var(%p) %dx%d (%dx%d), %d, %d\n", var, ++ print_debug("bcm2708_fb_check_var var(%p) %dx%d (%dx%d), %d\n", var, + var->xres, var->yres, var->xres_virtual, var->yres_virtual, +- var->bits_per_pixel, pixels); ++ var->bits_per_pixel); + + if (!var->bits_per_pixel) + var->bits_per_pixel = 16; +@@ -211,7 +215,7 @@ + fbinfo->base = 0; /* filled in by VC */ + fbinfo->pitch = 0; /* filled in by VC */ + +- pr_info("bcm2708_fb_set_par info(%p) %dx%d (%dx%d), %d, %d\n", info, ++ print_debug("bcm2708_fb_set_par info(%p) %dx%d (%dx%d), %d, %d\n", info, + info->var.xres, info->var.yres, info->var.xres_virtual, + info->var.yres_virtual, (int)info->screen_size, + info->var.bits_per_pixel); +@@ -251,7 +255,7 @@ + BUG(); /* what can we do here */ + } + } +- pr_info ++ print_debug + ("BCM2708FB: start = %p,%p width=%d, height=%d, bpp=%d, pitch=%d size=%d success=%d\n", + (void *)fb->fb.screen_base, (void *)fb->fb.fix.smem_start, + fbinfo->xres, fbinfo->yres, fbinfo->bpp, +@@ -274,7 +278,7 @@ + { + struct bcm2708_fb *fb = to_bcm2708(info); + +- /*pr_info("BCM2708FB: setcolreg %d:(%02x,%02x,%02x,%02x) %x\n", regno, red, green, blue, transp, fb->fb.fix.visual);*/ ++ /*print_debug("BCM2708FB: setcolreg %d:(%02x,%02x,%02x,%02x) %x\n", regno, red, green, blue, transp, fb->fb.fix.visual);*/ + if (fb->fb.var.bits_per_pixel <= 8) { + if (regno < 256) { + /* blue [0:4], green [5:10], red [11:15] */ +@@ -297,28 +301,28 @@ + + static int bcm2708_fb_blank(int blank_mode, struct fb_info *info) + { +- /*pr_info("bcm2708_fb_blank\n"); */ ++ /*print_debug("bcm2708_fb_blank\n"); */ + return -1; + } + + static void bcm2708_fb_fillrect(struct fb_info *info, + const struct fb_fillrect *rect) + { +- /* (is called) pr_info("bcm2708_fb_fillrect\n"); */ ++ /* (is called) print_debug("bcm2708_fb_fillrect\n"); */ + cfb_fillrect(info, rect); + } + + static void bcm2708_fb_copyarea(struct fb_info *info, + const struct fb_copyarea *region) + { +- /*pr_info("bcm2708_fb_copyarea\n"); */ ++ /*print_debug("bcm2708_fb_copyarea\n"); */ + cfb_copyarea(info, region); + } + + static void bcm2708_fb_imageblit(struct fb_info *info, + const struct fb_image *image) + { +- /* (is called) pr_info("bcm2708_fb_imageblit\n"); */ ++ /* (is called) print_debug("bcm2708_fb_imageblit\n"); */ + cfb_imageblit(info, image); + } + +@@ -393,15 +397,15 @@ + + fb_set_var(&fb->fb, &fb->fb.var); + +- pr_info("BCM2708FB: registering framebuffer (%dx%d@%d)\n", fbwidth, ++ print_debug("BCM2708FB: registering framebuffer (%dx%d@%d)\n", fbwidth, + fbheight, fbdepth); + + ret = register_framebuffer(&fb->fb); +- pr_info("BCM2708FB: register framebuffer (%d)\n", ret); ++ print_debug("BCM2708FB: register framebuffer (%d)\n", ret); + if (ret == 0) + goto out; + +- pr_info("BCM2708FB: cannot register framebuffer (%d)\n", ret); ++ print_debug("BCM2708FB: cannot register framebuffer (%d)\n", ret); + out: + return ret; + } +Index: linux-3.2.46/sound/arm/bcm2835-pcm.c +=================================================================== +--- linux-3.2.46.orig/sound/arm/bcm2835-pcm.c 2013-07-26 19:35:38.000000000 +0000 ++++ linux-3.2.46/sound/arm/bcm2835-pcm.c 2013-07-26 19:36:37.000000000 +0000 +@@ -98,7 +98,7 @@ + + audio_info(" .. IN (%d)\n", substream->number); + +- audio_warning("Alsa open (%d)\n", substream->number); ++ audio_info("Alsa open (%d)\n", substream->number); + idx = substream->number; + + if (idx > MAX_SUBSTREAMS) { +@@ -167,7 +167,7 @@ + bcm2835_alsa_stream_t *alsa_stream = runtime->private_data; + + audio_info(" .. IN\n"); +- audio_warning("Alsa close\n"); ++ audio_info("Alsa close\n"); + + /* + * Call stop if it's still running. This happens when app +Index: linux-3.2.46/sound/arm/bcm2835.c +=================================================================== +--- linux-3.2.46.orig/sound/arm/bcm2835.c 2013-07-26 19:36:30.000000000 +0000 ++++ linux-3.2.46/sound/arm/bcm2835.c 2013-07-26 19:36:37.000000000 +0000 +@@ -87,8 +87,6 @@ + bcm2835_chip_t *chip; + struct snd_card *card; + int err; +- printk(KERN_INFO "Probing FOR bcm2835 ALSA device (%d):(%d)\n", +- dev, enable[dev]); + + if (dev >= MAX_SUBSTREAMS) + return -ENODEV; +@@ -101,7 +99,6 @@ + if (dev > 0) + goto add_register_map; + +- printk("Creating card...\n"); + err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &g_card); + if (err < 0) + goto out; +@@ -374,8 +371,6 @@ + printk("Error registering bcm2835_alsa7_driver %d .\n", err); + goto unregister_6; + } +- printk(KERN_INFO "BCM2835 ALSA driver init %s\n", +- err ? "FAILED" : "OK"); + + return 0; + diff -Nru linux-3.2.46/debian/patches/rpi/rpi_248_807223a562933b1906c70f1c5249db7635dd4574.patch linux-3.2.46/debian/patches/rpi/rpi_248_807223a562933b1906c70f1c5249db7635dd4574.patch --- linux-3.2.46/debian/patches/rpi/rpi_248_807223a562933b1906c70f1c5249db7635dd4574.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_248_807223a562933b1906c70f1c5249db7635dd4574.patch 2013-07-26 19:36:40.000000000 +0000 @@ -0,0 +1,23 @@ +commit 807223a562933b1906c70f1c5249db7635dd4574 +Author: popcornmix +Date: Mon Sep 17 22:57:29 2012 +0100 + + Switch to powersave governor. We'll enable ondemand in the distribution + +Index: linux-3.2.46/arch/arm/configs/bcmrpi_defconfig +=================================================================== +--- linux-3.2.46.orig/arch/arm/configs/bcmrpi_defconfig 2013-07-26 19:36:36.000000000 +0000 ++++ linux-3.2.46/arch/arm/configs/bcmrpi_defconfig 2013-07-26 19:36:39.000000000 +0000 +@@ -48,9 +48,10 @@ + CONFIG_KEXEC=y + CONFIG_CPU_FREQ=y + CONFIG_CPU_FREQ_STAT=m +-CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y +-CONFIG_CPU_FREQ_GOV_POWERSAVE=y ++CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE=y ++CONFIG_CPU_FREQ_GOV_PERFORMANCE=y + CONFIG_CPU_FREQ_GOV_USERSPACE=y ++CONFIG_CPU_FREQ_GOV_ONDEMAND=y + CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y + CONFIG_CPU_IDLE=y + CONFIG_VFP=y diff -Nru linux-3.2.46/debian/patches/rpi/rpi_249_0875260c9a74e5b46a1a5052dd8472cfec8d1d22.patch linux-3.2.46/debian/patches/rpi/rpi_249_0875260c9a74e5b46a1a5052dd8472cfec8d1d22.patch --- linux-3.2.46/debian/patches/rpi/rpi_249_0875260c9a74e5b46a1a5052dd8472cfec8d1d22.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_249_0875260c9a74e5b46a1a5052dd8472cfec8d1d22.patch 2013-07-26 19:36:41.000000000 +0000 @@ -0,0 +1,59 @@ +commit 0875260c9a74e5b46a1a5052dd8472cfec8d1d22 +Author: popcornmix +Date: Thu Sep 20 21:45:25 2012 +0100 + + Enable multiple ALSA channels + +Index: linux-3.2.46/arch/arm/mach-bcm2708/bcm2708.c +=================================================================== +--- linux-3.2.46.orig/arch/arm/mach-bcm2708/bcm2708.c 2013-07-26 19:36:34.000000000 +0000 ++++ linux-3.2.46/arch/arm/mach-bcm2708/bcm2708.c 2013-07-26 19:36:40.000000000 +0000 +@@ -516,6 +516,48 @@ + .resource = 0, + .num_resources = 0, + }, ++ [1] = { ++ .name = "bcm2835_AUD1", ++ .id = 1, /* second audio device */ ++ .resource = 0, ++ .num_resources = 0, ++ }, ++ [2] = { ++ .name = "bcm2835_AUD2", ++ .id = 2, /* third audio device */ ++ .resource = 0, ++ .num_resources = 0, ++ }, ++ [3] = { ++ .name = "bcm2835_AUD3", ++ .id = 3, /* forth audio device */ ++ .resource = 0, ++ .num_resources = 0, ++ }, ++ [4] = { ++ .name = "bcm2835_AUD4", ++ .id = 4, /* fifth audio device */ ++ .resource = 0, ++ .num_resources = 0, ++ }, ++ [5] = { ++ .name = "bcm2835_AUD5", ++ .id = 5, /* sixth audio device */ ++ .resource = 0, ++ .num_resources = 0, ++ }, ++ [6] = { ++ .name = "bcm2835_AUD6", ++ .id = 6, /* seventh audio device */ ++ .resource = 0, ++ .num_resources = 0, ++ }, ++ [7] = { ++ .name = "bcm2835_AUD7", ++ .id = 7, /* eighth audio device */ ++ .resource = 0, ++ .num_resources = 0, ++ }, + }; + + static struct resource bcm2708_spi_resources[] = { diff -Nru linux-3.2.46/debian/patches/rpi/rpi_250_2be55e6cc980ce2473052f071902b7379b7344b9.patch linux-3.2.46/debian/patches/rpi/rpi_250_2be55e6cc980ce2473052f071902b7379b7344b9.patch --- linux-3.2.46/debian/patches/rpi/rpi_250_2be55e6cc980ce2473052f071902b7379b7344b9.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_250_2be55e6cc980ce2473052f071902b7379b7344b9.patch 2013-07-26 19:36:42.000000000 +0000 @@ -0,0 +1,381 @@ +commit 2be55e6cc980ce2473052f071902b7379b7344b9 +Author: popcornmix +Date: Thu Sep 20 21:46:14 2012 +0100 + + Remove vcos abstraction layer from ALSA driver. Thanks Dorian + +Index: linux-3.2.46/sound/arm/bcm2835-vchiq.c +=================================================================== +--- linux-3.2.46.orig/sound/arm/bcm2835-vchiq.c 2013-07-26 19:34:33.000000000 +0000 ++++ linux-3.2.46/sound/arm/bcm2835-vchiq.c 2013-07-26 19:36:41.000000000 +0000 +@@ -32,17 +32,10 @@ + /* ---- Include Files -------------------------------------------------------- */ + + #include "interface/vchi/vchi.h" +-#include "interface/vcos/vcos.h" +-#include "interface/vcos/vcos_logging.h" + #include "vc_vchi_audioserv_defs.h" + + /* ---- Private Constants and Types ------------------------------------------ */ + +-/* VCOS logging category for this service */ +-#define VCOS_LOG_CATEGORY (&audio_log_category) +- +-/* Default VCOS logging level */ +-#define LOG_LEVEL VCOS_LOG_WARN + /* Logging macros (for remapping to other logging mechanisms, i.e., printf) */ + #ifdef AUDIO_DEBUG_ENABLE + #define LOG_ERR( fmt, arg... ) pr_err( "%s:%d " fmt, __func__, __LINE__, ##arg) +@@ -50,26 +43,23 @@ + #define LOG_INFO( fmt, arg... ) pr_info( "%s:%d " fmt, __func__, __LINE__, ##arg) + #define LOG_DBG( fmt, arg... ) pr_info( "%s:%d " fmt, __func__, __LINE__, ##arg) + #else +- #define LOG_ERR( fmt, arg... ) vcos_log_error( "%s:%d " fmt, __func__, __LINE__, ##arg) +- #define LOG_WARN( fmt, arg... ) vcos_log_warn( "%s:%d " fmt, __func__, __LINE__, ##arg) +- #define LOG_INFO( fmt, arg... ) vcos_log_info( "%s:%d " fmt, __func__, __LINE__, ##arg) +- #define LOG_DBG( fmt, arg... ) vcos_log_info( "%s:%d " fmt, __func__, __LINE__, ##arg) ++ #define LOG_ERR( fmt, arg... ) ++ #define LOG_WARN( fmt, arg... ) ++ #define LOG_INFO( fmt, arg... ) ++ #define LOG_DBG( fmt, arg... ) + #endif + + typedef struct opaque_AUDIO_INSTANCE_T { + uint32_t num_connections; + VCHI_SERVICE_HANDLE_T vchi_handle[VCHI_MAX_NUM_CONNECTIONS]; +- VCOS_EVENT_T msg_avail_event; +- VCOS_MUTEX_T vchi_mutex; ++ struct semaphore msg_avail_event; ++ struct mutex vchi_mutex; + bcm2835_alsa_stream_t *alsa_stream; + int32_t result, got_result; + } AUDIO_INSTANCE_T; + + /* ---- Private Variables ---------------------------------------------------- */ + +-/* VCOS logging category for this service */ +-static VCOS_LOG_CAT_T audio_log_category; +- + /* ---- Private Function Prototypes ------------------------------------------ */ + + /* ---- Private Functions ---------------------------------------------------- */ +@@ -186,7 +176,7 @@ + BUG_ON(instance->got_result); + instance->result = m.u.result.success; + instance->got_result = 1; +- vcos_event_signal(&instance->msg_avail_event); ++ up(&instance->msg_avail_event); + } else if (m.type == VC_AUDIO_MSG_TYPE_COMPLETE) { + irq_handler_t callback = (irq_handler_t) m.u.complete.callback; + LOG_DBG +@@ -199,7 +189,7 @@ + LOG_DBG(" .. unexpected alsa_stream=%p, callback=%p\n", + alsa_stream, callback); + } +- vcos_event_signal(&instance->msg_avail_event); ++ up(&instance->msg_avail_event); + } else { + LOG_DBG(" .. unexpected m.type=%d\n", m.type); + } +@@ -212,7 +202,7 @@ + { + uint32_t i; + AUDIO_INSTANCE_T *instance; +- VCOS_STATUS_T status; ++ int status; + + LOG_DBG("%s: start", __func__); + +@@ -223,27 +213,16 @@ + return NULL; + } + /* Allocate memory for this instance */ +- instance = vcos_malloc(sizeof(*instance), "audio_instance"); ++ instance = kmalloc(sizeof(*instance), GFP_KERNEL); ++ + memset(instance, 0, sizeof(*instance)); + + instance->num_connections = num_connections; + /* Create the message available event */ +- status = +- vcos_event_create(&instance->msg_avail_event, "audio_msg_avail"); +- if (status != VCOS_SUCCESS) { +- LOG_ERR("%s: failed to create event (status=%d)", __func__, +- status); ++ sema_init(&instance->msg_avail_event,1); + +- goto err_free_mem; +- } + /* Create a lock for exclusive, serialized VCHI connection access */ +- status = vcos_mutex_create(&instance->vchi_mutex, "audio_vchi_mutex"); +- if (status != VCOS_SUCCESS) { +- LOG_ERR("%s: failed to create event (status=%d)", __func__, +- status); +- +- goto err_delete_event; +- } ++ mutex_init(&instance->vchi_mutex); + /* Open the VCHI service connections */ + for (i = 0; i < num_connections; i++) { + SERVICE_CREATION_T params = { +@@ -253,14 +232,14 @@ + 0, // tx fifo size (unused) + audio_vchi_callback, // service callback + instance, // service callback parameter +- VCOS_TRUE, //TODO: remove VCOS_FALSE, // unaligned bulk recieves +- VCOS_TRUE, //TODO: remove VCOS_FALSE, // unaligned bulk transmits +- VCOS_FALSE // want crc check on bulk transfers ++ 1, //TODO: remove VCOS_FALSE, // unaligned bulk recieves ++ 1, //TODO: remove VCOS_FALSE, // unaligned bulk transmits ++ 0 // want crc check on bulk transfers + }; + + status = vchi_service_open(vchi_instance, ¶ms, + &instance->vchi_handle[i]); +- if (status != VCOS_SUCCESS) { ++ if (status) { + LOG_ERR + ("%s: failed to open VCHI service connection (status=%d)", + __func__, status); +@@ -278,13 +257,7 @@ + vchi_service_close(instance->vchi_handle[i]); + } + +- vcos_mutex_delete(&instance->vchi_mutex); +- +-err_delete_event: +- vcos_event_delete(&instance->msg_avail_event); +- +-err_free_mem: +- vcos_free(instance); ++ kfree(instance); + + return NULL; + } +@@ -302,7 +275,11 @@ + } + + LOG_DBG(" .. about to lock (%d)\n", instance->num_connections); +- vcos_mutex_lock(&instance->vchi_mutex); ++ if(mutex_lock_interruptible(&instance->vchi_mutex)) ++ { ++ LOG_DBG("Interrupted whilst waiting for lock on (%d)\n",instance->num_connections); ++ return -EINTR; ++ } + + /* Close all VCHI service connections */ + for (i = 0; i < instance->num_connections; i++) { +@@ -318,16 +295,9 @@ + } + } + +- vcos_mutex_unlock(&instance->vchi_mutex); ++ mutex_unlock(&instance->vchi_mutex); + +- vcos_mutex_delete(&instance->vchi_mutex); +- +- vcos_event_delete(&instance->msg_avail_event); +- +- vcos_free(instance); +- +- /* Unregister the log category so we can add it back next time */ +- vcos_log_unregister(&audio_log_category); ++ kfree(instance); + + LOG_DBG(" .. OUT\n"); + +@@ -371,10 +341,6 @@ + goto err_free_mem; + } + +- /* Set up the VCOS logging */ +- vcos_log_set_level(VCOS_LOG_CATEGORY, LOG_LEVEL); +- vcos_log_register("audio", VCOS_LOG_CATEGORY); +- + /* Initialize an instance of the audio service */ + instance = vc_vchi_audio_init(vchi_instance, &vchi_connection, 1); + +@@ -412,7 +378,11 @@ + } + instance = alsa_stream->instance; + +- vcos_mutex_lock(&instance->vchi_mutex); ++ if(mutex_lock_interruptible(&instance->vchi_mutex)) ++ { ++ LOG_DBG("Interrupted whilst waiting for lock on (%d)\n",instance->num_connections); ++ return -EINTR; ++ } + vchi_service_use(instance->vchi_handle[0]); + + m.type = VC_AUDIO_MSG_TYPE_OPEN; +@@ -434,7 +404,7 @@ + + unlock: + vchi_service_release(instance->vchi_handle[0]); +- vcos_mutex_unlock(&instance->vchi_mutex); ++ mutex_unlock(&instance->vchi_mutex); + exit: + LOG_DBG(" .. OUT\n"); + return ret; +@@ -452,7 +422,11 @@ + LOG_INFO + (" Setting ALSA dest(%d), volume(%d)\n", chip->dest, chip->volume); + +- vcos_mutex_lock(&instance->vchi_mutex); ++ if(mutex_lock_interruptible(&instance->vchi_mutex)) ++ { ++ LOG_DBG("Interrupted whilst waiting for lock on (%d)\n",instance->num_connections); ++ return -EINTR; ++ } + vchi_service_use(instance->vchi_handle[0]); + + instance->got_result = 0; +@@ -477,8 +451,7 @@ + + /* We are expecting a reply from the videocore */ + while (!instance->got_result) { +- success = vcos_event_wait(&instance->msg_avail_event); +- if (success != VCOS_SUCCESS) { ++ if (down_interruptible(&instance->msg_avail_event)) { + LOG_ERR("%s: failed on waiting for event (status=%d)", + __func__, success); + +@@ -498,7 +471,7 @@ + + unlock: + vchi_service_release(instance->vchi_handle[0]); +- vcos_mutex_unlock(&instance->vchi_mutex); ++ mutex_unlock(&instance->vchi_mutex); + + LOG_DBG(" .. OUT\n"); + return ret; +@@ -552,7 +525,11 @@ + return -EINVAL; + } + +- vcos_mutex_lock(&instance->vchi_mutex); ++ if(mutex_lock_interruptible(&instance->vchi_mutex)) ++ { ++ LOG_DBG("Interrupted whilst waiting for lock on (%d)\n",instance->num_connections); ++ return -EINTR; ++ } + vchi_service_use(instance->vchi_handle[0]); + + instance->got_result = 0; +@@ -578,8 +555,7 @@ + + /* We are expecting a reply from the videocore */ + while (!instance->got_result) { +- success = vcos_event_wait(&instance->msg_avail_event); +- if (success != VCOS_SUCCESS) { ++ if (down_interruptible(&instance->msg_avail_event)) { + LOG_ERR("%s: failed on waiting for event (status=%d)", + __func__, success); + +@@ -599,7 +575,7 @@ + + unlock: + vchi_service_release(instance->vchi_handle[0]); +- vcos_mutex_unlock(&instance->vchi_mutex); ++ mutex_unlock(&instance->vchi_mutex); + + LOG_DBG(" .. OUT\n"); + return ret; +@@ -622,7 +598,11 @@ + int ret; + LOG_DBG(" .. IN\n"); + +- vcos_mutex_lock(&instance->vchi_mutex); ++ if(mutex_lock_interruptible(&instance->vchi_mutex)) ++ { ++ LOG_DBG("Interrupted whilst waiting for lock on (%d)\n",instance->num_connections); ++ return -EINTR; ++ } + vchi_service_use(instance->vchi_handle[0]); + + m.type = VC_AUDIO_MSG_TYPE_START; +@@ -644,7 +624,7 @@ + + unlock: + vchi_service_release(instance->vchi_handle[0]); +- vcos_mutex_unlock(&instance->vchi_mutex); ++ mutex_unlock(&instance->vchi_mutex); + LOG_DBG(" .. OUT\n"); + return ret; + } +@@ -657,7 +637,11 @@ + int ret; + LOG_DBG(" .. IN\n"); + +- vcos_mutex_lock(&instance->vchi_mutex); ++ if(mutex_lock_interruptible(&instance->vchi_mutex)) ++ { ++ LOG_DBG("Interrupted whilst waiting for lock on (%d)\n",instance->num_connections); ++ return -EINTR; ++ } + vchi_service_use(instance->vchi_handle[0]); + + m.type = VC_AUDIO_MSG_TYPE_STOP; +@@ -680,7 +664,7 @@ + + unlock: + vchi_service_release(instance->vchi_handle[0]); +- vcos_mutex_unlock(&instance->vchi_mutex); ++ mutex_unlock(&instance->vchi_mutex); + LOG_DBG(" .. OUT\n"); + return ret; + } +@@ -695,7 +679,11 @@ + + my_workqueue_quit(alsa_stream); + +- vcos_mutex_lock(&instance->vchi_mutex); ++ if(mutex_lock_interruptible(&instance->vchi_mutex)) ++ { ++ LOG_DBG("Interrupted whilst waiting for lock on (%d)\n",instance->num_connections); ++ return -EINTR; ++ } + vchi_service_use(instance->vchi_handle[0]); + + m.type = VC_AUDIO_MSG_TYPE_CLOSE; +@@ -712,8 +700,7 @@ + goto unlock; + } + while (!instance->got_result) { +- success = vcos_event_wait(&instance->msg_avail_event); +- if (success != VCOS_SUCCESS) { ++ if (down_interruptible(&instance->msg_avail_event)) { + LOG_ERR("%s: failed on waiting for event (status=%d)", + __func__, success); + +@@ -733,7 +720,7 @@ + + unlock: + vchi_service_release(instance->vchi_handle[0]); +- vcos_mutex_unlock(&instance->vchi_mutex); ++ mutex_unlock(&instance->vchi_mutex); + + /* Stop the audio service */ + if (instance) { +@@ -756,7 +743,11 @@ + + LOG_INFO(" Writing %d bytes from %p\n", count, src); + +- vcos_mutex_lock(&instance->vchi_mutex); ++ if(mutex_lock_interruptible(&instance->vchi_mutex)) ++ { ++ LOG_DBG("Interrupted whilst waiting for lock on (%d)\n",instance->num_connections); ++ return -EINTR; ++ } + vchi_service_use(instance->vchi_handle[0]); + + m.type = VC_AUDIO_MSG_TYPE_WRITE; +@@ -801,7 +792,7 @@ + + unlock: + vchi_service_release(instance->vchi_handle[0]); +- vcos_mutex_unlock(&instance->vchi_mutex); ++ mutex_unlock(&instance->vchi_mutex); + LOG_DBG(" .. OUT\n"); + return ret; + } diff -Nru linux-3.2.46/debian/patches/rpi/rpi_251_965b922076edccc530bd2a05e2fbabc1dd8b06a8.patch linux-3.2.46/debian/patches/rpi/rpi_251_965b922076edccc530bd2a05e2fbabc1dd8b06a8.patch --- linux-3.2.46/debian/patches/rpi/rpi_251_965b922076edccc530bd2a05e2fbabc1dd8b06a8.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_251_965b922076edccc530bd2a05e2fbabc1dd8b06a8.patch 2013-07-26 19:36:43.000000000 +0000 @@ -0,0 +1,42 @@ +commit 965b922076edccc530bd2a05e2fbabc1dd8b06a8 +Author: popcornmix +Date: Sat Sep 22 18:56:57 2012 +0100 + + Fix Kernel OOPS in SDHCI on boot with the llm patch. Thanks ddv2005 + +Index: linux-3.2.46/drivers/mmc/host/sdhci.c +=================================================================== +--- linux-3.2.46.orig/drivers/mmc/host/sdhci.c 2013-07-26 19:35:53.000000000 +0000 ++++ linux-3.2.46/drivers/mmc/host/sdhci.c 2013-07-26 19:36:43.000000000 +0000 +@@ -143,9 +143,9 @@ + if(enable_llm) + { + local_irq_disable(); +- enable_irq(host->irq); + if(host->second_irq) + enable_irq(host->second_irq); ++ enable_irq(host->irq); + } + #endif + spin_unlock(&host->lock); +@@ -177,9 +177,9 @@ + if(enable_llm) + { + local_irq_disable(); +- enable_irq(host->irq); + if(host->second_irq) + enable_irq(host->second_irq); ++ enable_irq(host->irq); + } + #endif + spin_unlock_irqrestore(&host->lock,flags); +@@ -292,9 +292,7 @@ + return; + } + timeout--; +- sdhci_spin_enable_schedule(host); + mdelay(1); +- sdhci_spin_disable_schedule(host); + } + + if (host->ops->platform_reset_exit) diff -Nru linux-3.2.46/debian/patches/rpi/rpi_252_c14ddd05972ac5aa822a9e9f487cf2c4a1b958a0.patch linux-3.2.46/debian/patches/rpi/rpi_252_c14ddd05972ac5aa822a9e9f487cf2c4a1b958a0.patch --- linux-3.2.46/debian/patches/rpi/rpi_252_c14ddd05972ac5aa822a9e9f487cf2c4a1b958a0.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_252_c14ddd05972ac5aa822a9e9f487cf2c4a1b958a0.patch 2013-07-26 19:36:45.000000000 +0000 @@ -0,0 +1,47 @@ +commit c14ddd05972ac5aa822a9e9f487cf2c4a1b958a0 +Author: popcornmix +Date: Mon Sep 24 23:40:21 2012 +0100 + + Use system timer for udelay, so unaffected by cpufreq + +Index: linux-3.2.46/arch/arm/mach-bcm2708/bcm2708.c +=================================================================== +--- linux-3.2.46.orig/arch/arm/mach-bcm2708/bcm2708.c 2013-07-26 19:36:40.000000000 +0000 ++++ linux-3.2.46/arch/arm/mach-bcm2708/bcm2708.c 2013-07-26 19:36:44.000000000 +0000 +@@ -859,6 +859,36 @@ + } + #endif + ++ ++/* The assembly versions in delay.S don't account for core freq changing in cpufreq driver */ ++/* Use 1MHz system timer for busy waiting */ ++void __udelay(unsigned long usecs) ++{ ++ unsigned long start = readl(__io_address(ST_BASE + 0x04)); ++ unsigned long now; ++ do { ++ now = readl(__io_address(ST_BASE + 0x04)); ++ } while ((long)(now - start) <= usecs); ++} ++ ++ ++void __const_udelay(unsigned long scaled_usecs) ++{ ++ /* want /107374, this is about 3% bigger. We know usecs is less than 2000, so shouldn't overflow */ ++ const unsigned long usecs = scaled_usecs * 10 >> 20; ++ unsigned long start = readl(__io_address(ST_BASE + 0x04)); ++ unsigned long now; ++ do { ++ now = readl(__io_address(ST_BASE + 0x04)); ++ } while ((long)(now - start) <= usecs); ++} ++ ++void __delay(int loops) ++{ ++ while (--loops > 0) ++ nop(); ++} ++ + MACHINE_START(BCM2708, "BCM2708") + /* Maintainer: Broadcom Europe Ltd. */ + .map_io = bcm2708_map_io,.init_irq = bcm2708_init_irq,.timer = diff -Nru linux-3.2.46/debian/patches/rpi/rpi_253_9245b4c35b99b3870e1f7dc598c5692b3c66a6f0.patch linux-3.2.46/debian/patches/rpi/rpi_253_9245b4c35b99b3870e1f7dc598c5692b3c66a6f0.patch --- linux-3.2.46/debian/patches/rpi/rpi_253_9245b4c35b99b3870e1f7dc598c5692b3c66a6f0.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_253_9245b4c35b99b3870e1f7dc598c5692b3c66a6f0.patch 2013-07-26 19:36:46.000000000 +0000 @@ -0,0 +1,61 @@ +commit 9245b4c35b99b3870e1f7dc598c5692b3c66a6f0 +Author: popcornmix +Date: Wed Sep 26 13:46:03 2012 +0100 + + Move __delay function into assembly to get accurate BogoMips + +Index: linux-3.2.46/arch/arm/mach-bcm2708/Makefile +=================================================================== +--- linux-3.2.46.orig/arch/arm/mach-bcm2708/Makefile 2013-07-26 19:31:51.000000000 +0000 ++++ linux-3.2.46/arch/arm/mach-bcm2708/Makefile 2013-07-26 19:36:45.000000000 +0000 +@@ -2,7 +2,7 @@ + # Makefile for the linux kernel. + # + +-obj-$(CONFIG_MACH_BCM2708) += clock.o bcm2708.o armctrl.o vcio.o power.o dma.o ++obj-$(CONFIG_MACH_BCM2708) += clock.o bcm2708.o armctrl.o vcio.o power.o dma.o delay.o + obj-$(CONFIG_BCM2708_GPIO) += bcm2708_gpio.o + obj-$(CONFIG_BCM2708_VCMEM) += vc_mem.o + +Index: linux-3.2.46/arch/arm/mach-bcm2708/bcm2708.c +=================================================================== +--- linux-3.2.46.orig/arch/arm/mach-bcm2708/bcm2708.c 2013-07-26 19:36:44.000000000 +0000 ++++ linux-3.2.46/arch/arm/mach-bcm2708/bcm2708.c 2013-07-26 19:36:45.000000000 +0000 +@@ -883,12 +883,6 @@ + } while ((long)(now - start) <= usecs); + } + +-void __delay(int loops) +-{ +- while (--loops > 0) +- nop(); +-} +- + MACHINE_START(BCM2708, "BCM2708") + /* Maintainer: Broadcom Europe Ltd. */ + .map_io = bcm2708_map_io,.init_irq = bcm2708_init_irq,.timer = +Index: linux-3.2.46/arch/arm/mach-bcm2708/delay.S +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/arch/arm/mach-bcm2708/delay.S 2013-07-26 19:36:45.000000000 +0000 +@@ -0,0 +1,20 @@ ++/* ++ * linux/arch/arm/lib/delay.S ++ * ++ * Copyright (C) 1995, 1996 Russell King ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++#include ++#include ++#include ++ ++ .text ++@ Delay routine ++ENTRY(__delay) ++ subs r0, r0, #1 ++ bhi __delay ++ mov pc, lr ++ENDPROC(__delay) diff -Nru linux-3.2.46/debian/patches/rpi/rpi_254_358395ed00fbb2854c0b7d6166888f3aff524ca4.patch linux-3.2.46/debian/patches/rpi/rpi_254_358395ed00fbb2854c0b7d6166888f3aff524ca4.patch --- linux-3.2.46/debian/patches/rpi/rpi_254_358395ed00fbb2854c0b7d6166888f3aff524ca4.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_254_358395ed00fbb2854c0b7d6166888f3aff524ca4.patch 2013-07-26 19:36:47.000000000 +0000 @@ -0,0 +1,69 @@ +commit 358395ed00fbb2854c0b7d6166888f3aff524ca4 +Author: popcornmix +Date: Wed Oct 3 20:08:19 2012 +0100 + + set i2c speed via module-parameter or menuconfig. Thanks FrankBoesing + +Index: linux-3.2.46/drivers/i2c/busses/Kconfig +=================================================================== +--- linux-3.2.46.orig/drivers/i2c/busses/Kconfig 2013-07-26 19:33:54.000000000 +0000 ++++ linux-3.2.46/drivers/i2c/busses/Kconfig 2013-07-26 19:36:46.000000000 +0000 +@@ -318,6 +318,17 @@ + support for the BCM2708. BSC is a Broadcom proprietary bus compatible + with I2C/TWI/SMBus. + ++config I2C_BCM2708_BAUDRATE ++ prompt "BCM2708 I2C baudrate" ++ depends on I2C_BCM2708 ++ int ++ default 100000 ++ help ++ Set the I2C baudrate. This will alter the default value. A ++ different baudrate can be set by using a module parameter as well. If ++ no parameter is provided when loading, this is the value that will be ++ used. ++ + config I2C_BLACKFIN_TWI + tristate "Blackfin TWI I2C support" + depends on BLACKFIN +Index: linux-3.2.46/drivers/i2c/busses/i2c-bcm2708.c +=================================================================== +--- linux-3.2.46.orig/drivers/i2c/busses/i2c-bcm2708.c 2013-07-26 19:33:55.000000000 +0000 ++++ linux-3.2.46/drivers/i2c/busses/i2c-bcm2708.c 2013-07-26 19:36:46.000000000 +0000 +@@ -66,11 +66,15 @@ + #define BSC_S_DONE 0x00000002 + #define BSC_S_TA 0x00000001 + +-#define I2C_CLOCK_HZ 100000 /* FIXME: get from DT */ + #define I2C_TIMEOUT_MS 150 + + #define DRV_NAME "bcm2708_i2c" + ++static unsigned int baudrate = CONFIG_I2C_BCM2708_BAUDRATE; ++module_param(baudrate, uint, S_IRUSR | S_IWUSR | S_IRGRP | S_IWGRP); ++MODULE_PARM_DESC(baudrate, "The I2C baudrate"); ++ ++ + struct bcm2708_i2c { + struct i2c_adapter adapter; + +@@ -148,7 +152,7 @@ + u32 c = BSC_C_I2CEN | BSC_C_INTD | BSC_C_ST | BSC_C_CLEAR_1; + + bus_hz = clk_get_rate(bi->clk); +- cdiv = bus_hz / I2C_CLOCK_HZ; ++ cdiv = bus_hz / baudrate; + + if (bi->msg->flags & I2C_M_RD) + c |= BSC_C_INTR | BSC_C_READ; +@@ -331,8 +335,8 @@ + goto out_free_irq; + } + +- dev_info(&pdev->dev, "BSC%d Controller at 0x%08lx (irq %d)\n", +- pdev->id, (unsigned long)regs->start, irq); ++ dev_info(&pdev->dev, "BSC%d Controller at 0x%08lx (irq %d) (baudrate %dk)\n", ++ pdev->id, (unsigned long)regs->start, irq, baudrate/1000); + + return 0; + diff -Nru linux-3.2.46/debian/patches/rpi/rpi_255_118e2d362a8dd0c1e6e4f5c4694ba193f77092ce.patch linux-3.2.46/debian/patches/rpi/rpi_255_118e2d362a8dd0c1e6e4f5c4694ba193f77092ce.patch --- linux-3.2.46/debian/patches/rpi/rpi_255_118e2d362a8dd0c1e6e4f5c4694ba193f77092ce.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_255_118e2d362a8dd0c1e6e4f5c4694ba193f77092ce.patch 2013-07-26 19:36:49.000000000 +0000 @@ -0,0 +1,36 @@ +commit 118e2d362a8dd0c1e6e4f5c4694ba193f77092ce +Author: popcornmix +Date: Wed Oct 3 21:31:48 2012 +0100 + + Allow the number of cycles delay between sdcard peripheral writes to be specified on command line with sdhci-bcm2708.cycle_delay + +Index: linux-3.2.46/drivers/mmc/host/sdhci-bcm2708.c +=================================================================== +--- linux-3.2.46.orig/drivers/mmc/host/sdhci-bcm2708.c 2013-07-26 19:35:57.000000000 +0000 ++++ linux-3.2.46/drivers/mmc/host/sdhci-bcm2708.c 2013-07-26 19:36:48.000000000 +0000 +@@ -82,6 +82,8 @@ + #define REG_EXRDFIFO_EN 0x80 + #define REG_EXRDFIFO_CFG 0x84 + ++int cycle_delay=2; ++ + /*****************************************************************************\ + * * + * Debug * +@@ -254,7 +256,7 @@ + /* host->clock is the clock freq in Hz */ + static hptime_t last_write_hpt; + hptime_t now = hptime(); +- ns_2clk = 2000000000/host->clock; ++ ns_2clk = cycle_delay*1000000/(host->clock/1000); + + if (now == last_write_hpt || now == last_write_hpt+1) { + /* we can't guarantee any significant time has +@@ -1517,6 +1519,7 @@ + module_param(sync_after_dma, bool, 0444); + module_param(missing_status, bool, 0444); + module_param(enable_llm, bool, 0444); ++module_param(cycle_delay, int, 0444); + + MODULE_DESCRIPTION("Secure Digital Host Controller Interface platform driver"); + MODULE_AUTHOR("Broadcom "); diff -Nru linux-3.2.46/debian/patches/rpi/rpi_256_2843e37f77f0b01001f5659906166c92ba3801d0.patch linux-3.2.46/debian/patches/rpi/rpi_256_2843e37f77f0b01001f5659906166c92ba3801d0.patch --- linux-3.2.46/debian/patches/rpi/rpi_256_2843e37f77f0b01001f5659906166c92ba3801d0.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_256_2843e37f77f0b01001f5659906166c92ba3801d0.patch 2013-07-26 19:36:50.000000000 +0000 @@ -0,0 +1,241 @@ +commit 2843e37f77f0b01001f5659906166c92ba3801d0 +Author: popcornmix +Date: Fri Oct 5 17:41:53 2012 +0100 + + Fix vc-mem by using module parameters + +Index: linux-3.2.46/arch/arm/mach-bcm2708/bcm2708.c +=================================================================== +--- linux-3.2.46.orig/arch/arm/mach-bcm2708/bcm2708.c 2013-07-26 19:36:45.000000000 +0000 ++++ linux-3.2.46/arch/arm/mach-bcm2708/bcm2708.c 2013-07-26 19:36:49.000000000 +0000 +@@ -77,6 +77,7 @@ + + /* command line parameters */ + static unsigned boardrev, serial; ++static unsigned uart_clock; + + static void __init bcm2708_init_led(void); + +@@ -669,8 +670,12 @@ + { + int i; + ++ printk("bcm2708.uart_clock = %d\n", uart_clock); + pm_power_off = bcm2708_power_off; + ++ if (uart_clock) ++ lookups[0].clk->rate = uart_clock; ++ + for (i = 0; i < ARRAY_SIZE(lookups); i++) + clkdev_add(&lookups[i]); + +@@ -709,12 +714,6 @@ + bcm_register_device(&bcm2835_hwmon_device); + bcm_register_device(&bcm2835_thermal_device); + +-#ifdef CONFIG_BCM2708_VCMEM +- { +- extern void vc_mem_connected_init(void); +- vc_mem_connected_init(); +- } +-#endif + for (i = 0; i < ARRAY_SIZE(amba_devs); i++) { + struct amba_device *d = amba_devs[i]; + amba_device_register(d, &iomem_resource); +@@ -885,7 +884,12 @@ + + MACHINE_START(BCM2708, "BCM2708") + /* Maintainer: Broadcom Europe Ltd. */ +- .map_io = bcm2708_map_io,.init_irq = bcm2708_init_irq,.timer = +- &bcm2708_timer,.init_machine = +- bcm2708_init, MACHINE_END module_param(boardrev, uint, 0644); ++ .map_io = bcm2708_map_io, ++ .init_irq = bcm2708_init_irq, ++ .timer =&bcm2708_timer, ++ .init_machine =bcm2708_init, ++MACHINE_END ++ ++module_param(boardrev, uint, 0644); + module_param(serial, uint, 0644); ++module_param(uart_clock, uint, 0644); +Index: linux-3.2.46/arch/arm/mach-bcm2708/vc_mem.c +=================================================================== +--- linux-3.2.46.orig/arch/arm/mach-bcm2708/vc_mem.c 2013-07-26 19:36:28.000000000 +0000 ++++ linux-3.2.46/arch/arm/mach-bcm2708/vc_mem.c 2013-07-26 19:36:49.000000000 +0000 +@@ -36,7 +36,7 @@ + #define DRIVER_NAME "vc-mem" + + // Uncomment to enable debug logging +-#define ENABLE_DBG ++// #define ENABLE_DBG + + #if defined(ENABLE_DBG) + #define LOG_DBG( fmt, ... ) printk( KERN_INFO fmt "\n", ##__VA_ARGS__ ) +@@ -77,6 +77,11 @@ + EXPORT_SYMBOL(mm_vc_mem_size); + EXPORT_SYMBOL(mm_vc_mem_base); + ++static uint phys_addr = 0; ++static uint mem_size = 0; ++static uint mem_base = 0; ++ ++ + /**************************************************************************** + * + * vc_mem_open +@@ -111,53 +116,6 @@ + return 0; + } + +- +-/* tag part of the message */ +-struct vc_msg_tag { +- uint32_t tag_id; /* the message id */ +- uint32_t buffer_size; /* size of the buffer (which in this case is always 8 bytes) */ +- uint32_t data_size; /* amount of data being sent or received */ +- uint32_t base; /* the address of memory base */ +- uint32_t size; /* the size of memory in bytes */ +-}; +- +-struct vc_set_msg { +- uint32_t msg_size; /* simply, sizeof(struct vc_msg) */ +- uint32_t request_code; /* holds various information like the success and number of bytes returned (refer to mailboxes wiki) */ +- struct vc_msg_tag tag[2]; /* the array of tag structures above to make */ +- uint32_t end_tag; /* an end identifier, should be set to NULL */ +-}; +- +-static void vc_mem_update(void) +-{ +- struct vc_set_msg msg; /* the memory address accessed from driver */ +- uint32_t s; +- +- memset(&msg, 0, sizeof msg); +- /* create the message */ +- msg.msg_size = sizeof msg; +- msg.tag[0].tag_id = VCMSG_GET_VC_MEMORY; +- msg.tag[0].buffer_size = 8; +- msg.tag[0].data_size = 0; +- msg.tag[1].tag_id = VCMSG_GET_ARM_MEMORY; +- msg.tag[1].buffer_size = 8; +- msg.tag[1].data_size = 0; +- +- /* send the message */ +- s = bcm_mailbox_property(&msg, sizeof msg); +- +- LOG_DBG("%s: success=%d resp %x, vcbase=%x vcsize=%x armbase=%x armsize=%x", __func__, s, msg.request_code, +- msg.tag[0].base, msg.tag[0].size, msg.tag[1].base, msg.tag[1].size); +- +- /* check we're all good */ +- if (s == 0 && msg.request_code & 0x80000000) { +- mm_vc_mem_base = msg.tag[0].base; +- mm_vc_mem_size = msg.tag[0].size+msg.tag[1].size; +- mm_vc_mem_phys_addr = msg.tag[1].base; +- } +-} +- +- + /**************************************************************************** + * + * vc_mem_get_size +@@ -167,7 +125,6 @@ + static void + vc_mem_get_size(void) + { +- vc_mem_update(); + } + + /**************************************************************************** +@@ -179,7 +136,6 @@ + static void + vc_mem_get_base(void) + { +- vc_mem_update(); + } + + /**************************************************************************** +@@ -191,7 +147,6 @@ + int + vc_mem_get_current_size(void) + { +- vc_mem_get_size(); + return mm_vc_mem_size; + } + +@@ -382,25 +337,26 @@ + + /**************************************************************************** + * +-* vc_mem_connected_init +-* +-* This function is called once the videocore has been connected. ++* vc_mem_init + * + ***************************************************************************/ + +-void +-vc_mem_connected_init(void) ++static int __init ++vc_mem_init(void) + { + int rc = -EFAULT; + struct device *dev; + + LOG_DBG("%s: called", __func__); + ++ mm_vc_mem_phys_addr = phys_addr; ++ mm_vc_mem_size = mem_size; ++ mm_vc_mem_base = mem_base; ++ + vc_mem_get_size(); + +- printk("vc-mem: mm_vc_mem_phys_addr = 0x%08lx\n", mm_vc_mem_phys_addr); +- printk("vc-mem: mm_vc_mem_size = 0x%08x (%u MiB)\n", +- mm_vc_mem_size, mm_vc_mem_size / (1024 * 1024)); ++ printk("vc-mem: phys_addr:0x%08lx mem_base=0x%08x mem_size:0x%08x(%u MiB)\n", ++ mm_vc_mem_phys_addr, mm_vc_mem_base, mm_vc_mem_size, mm_vc_mem_size / (1024 * 1024)); + + if ((rc = alloc_chrdev_region(&vc_mem_devnum, 0, 1, DRIVER_NAME)) < 0) { + LOG_ERR("%s: alloc_chrdev_region failed (rc=%d)", __func__, rc); +@@ -438,7 +394,7 @@ + vc_mem_proc_entry->write_proc = vc_mem_proc_write; + + vc_mem_inited = 1; +- return; ++ return 0; + + out_device_destroy: + device_destroy(vc_mem_class, vc_mem_devnum); +@@ -454,23 +410,7 @@ + unregister_chrdev_region(vc_mem_devnum, 1); + + out_err: +- return; +-} +- +-/**************************************************************************** +-* +-* vc_mem_init +-* +-***************************************************************************/ +- +-static int __init +-vc_mem_init(void) +-{ +- printk(KERN_INFO "vc-mem: Videocore memory driver\n"); +- +- //vchiq_add_connected_callback(vc_mem_connected_init); +- +- return 0; ++ return -1; + } + + /**************************************************************************** +@@ -497,3 +437,8 @@ + module_exit(vc_mem_exit); + MODULE_LICENSE("GPL"); + MODULE_AUTHOR("Broadcom Corporation"); ++ ++module_param(phys_addr, uint, 0644); ++module_param(mem_size, uint, 0644); ++module_param(mem_base, uint, 0644); ++ diff -Nru linux-3.2.46/debian/patches/rpi/rpi_257_eb0c5608f3fd94fa316135e71edfb2d359b73203.patch linux-3.2.46/debian/patches/rpi/rpi_257_eb0c5608f3fd94fa316135e71edfb2d359b73203.patch --- linux-3.2.46/debian/patches/rpi/rpi_257_eb0c5608f3fd94fa316135e71edfb2d359b73203.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_257_eb0c5608f3fd94fa316135e71edfb2d359b73203.patch 2013-07-26 19:36:57.000000000 +0000 @@ -0,0 +1,24914 @@ +commit eb0c5608f3fd94fa316135e71edfb2d359b73203 +Author: popcornmix +Date: Fri Oct 5 17:43:41 2012 +0100 + + Move to version 5 of VCHIQ. Note: this requires a corresponding start.elf and /opt/vc/lib update + +Index: linux-3.2.46/drivers/misc/vc04_services/Kconfig +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/Kconfig 2013-07-26 19:32:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/Kconfig 2013-07-26 19:36:51.000000000 +0000 +@@ -1,7 +1,10 @@ + config BCM2708_VCHIQ + tristate "Videocore VCHIQ" + depends on MACH_BCM2708 +- default y +- help +- Helper for communication for VideoCore. ++ default CONFIG_BCM_VC_SERVICES ++ help ++ Kernel to VideoCore communication interface for the ++ BCM2708 family of products. ++ Defaults to Y when the Broadcom Videocore services ++ are included in the build, N otherwise. + +Index: linux-3.2.46/drivers/misc/vc04_services/Makefile +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/Makefile 2013-07-26 19:32:28.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/Makefile 2013-07-26 19:36:51.000000000 +0000 +@@ -1,21 +1,101 @@ ++ifeq ($(CONFIG_MACH_BCM2708),y) ++ ++############################################################################## ++# ++# This section is for building the RaspberryPi model ++# ++############################################################################## ++ + obj-$(CONFIG_BCM2708_VCHIQ) += vchiq.o + + vchiq-objs := \ + interface/vchiq_arm/vchiq_core.o \ +- interface/vchiq_arm/vchiq_shim.o \ +- interface/vchiq_arm/vchiq_util.o \ + interface/vchiq_arm/vchiq_arm.o \ + interface/vchiq_arm/vchiq_kern_lib.o \ + interface/vchiq_arm/vchiq_2835_arm.o \ +- interface/vcos/linuxkernel/vcos_linuxkernel.o \ +- interface/vcos/linuxkernel/vcos_thread_map.o \ +- interface/vcos/linuxkernel/vcos_linuxkernel_cfg.o \ +- interface/vcos/generic/vcos_generic_event_flags.o \ +- interface/vcos/generic/vcos_logcat.o \ +- interface/vcos/generic/vcos_mem_from_malloc.o \ +- interface/vcos/generic/vcos_cmd.o ++ interface/vchiq_arm/vchiq_proc.o \ ++ interface/vchiq_arm/vchiq_shim.o \ ++ interface/vchiq_arm/vchiq_util.o \ ++ interface/vchiq_arm/vchiq_connected.o \ ++ ++EXTRA_CFLAGS += -DVCOS_VERIFY_BKPTS=1 -Idrivers/misc/vc04_services -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 ++ ++endif ++ ++ifeq ($(CONFIG_ARCH_KONA),y) ++ ++############################################################################## ++# ++# This section is for building the Capri/Island model ++# ++############################################################################## ++ ++# Remove the quotes from the platform config name ++VCHIQ_PLATFORM_CONFIG = $(patsubst "%",%,$(CONFIG_VCHIQ_PLATFORM_CFG_NAME)) ++ ++$(info VCHIQ_PLATFORM_CONFIG = $(VCHIQ_PLATFORM_CONFIG)) ++include $(srctree)/drivers/misc/vc04_services/interface/vchiq_arm/platform-cfg/$(VCHIQ_PLATFORM_CONFIG).mk ++ ++$(info Building for MAP build system) ++$(info CONFIG_ARCH_KONA = $(CONFIG_ARCH_KONA)) ++ ++EXTRA_CFLAGS += -Wall -Wstrict-prototypes -Wno-trigraphs -O2 -Wno-declaration-after-statement -Wno-parentheses ++ ++EXTRA_CFLAGS += -I"drivers/misc/vc04_services/" ++EXTRA_CFLAGS += -I"drivers/misc/vc04_services/interface/vchiq_arm" ++EXTRA_CFLAGS += -I"drivers/misc/vc04_services/interface/debug_sym" ++EXTRA_CFLAGS += -I"include/linux/broadcom" ++ ++EXTRA_CFLAGS += -Werror ++ ++VCHIQ_HOST_BUS_ALIGNMENT = 3 ++ ++EXTRA_CFLAGS += -DOS_ASSERT_FAILURE ++EXTRA_CFLAGS += -D__STDC_VERSION=199901L ++EXTRA_CFLAGS += -D__STDC_VERSION__=199901L ++EXTRA_CFLAGS += -D__VCCOREVER__=0 ++EXTRA_CFLAGS += -D__linux__ ++EXTRA_CFLAGS += -D__KERNEL__ ++EXTRA_CFLAGS += -DVCHIQ_HOST_BUS_ALIGNMENT=$(VCHIQ_HOST_BUS_ALIGNMENT) ++EXTRA_CFLAGS += -DVCHIQ_SLOT_PADDING=16 ++EXTRA_CFLAGS += -DVCHIQ_ARM_SIDE ++EXTRA_CFLAGS += -DUSE_VCHIQ_ARM ++ifeq ($(VCHIQ_SM_ALLOC),vcddr) ++EXTRA_CFLAGS += -DVCHIQ_SM_ALLOC_VCDDR ++endif ++ ++obj-$(CONFIG_KONA_VCHIQ) += vc-vchiq.o ++vc-vchiq-objs := \ ++ interface/vchiq_arm/vchiq_arm.o \ ++ interface/vchiq_arm/vchiq_connected.o \ ++ interface/vchiq_arm/vchiq_core.o \ ++ interface/vchiq_arm/vchiq_kern_lib.o \ ++ interface/vchiq_arm/vchiq_shim.o \ ++ interface/vchiq_arm/vchiq_util.o \ ++ interface/vchiq_arm/vchiq_kona_arm.o \ ++ interface/vchiq_arm/vchiq_$(VCHIQ_PLATFORM)_arm.o \ ++ interface/vchiq_arm/vchiq_version.o \ ++ interface/vchiq_arm/vchiq_proc.o ++ifeq ($(VCHIQ_SM_ALLOC),vcddr) ++vc-vchiq-objs += \ ++ interface/debug_sym/debug_sym.o ++endif ++ ++obj-$(CONFIG_KONA_VCHIQ_MEMDRV) += vc-vchiq-memdrv-kona.o ++vc-vchiq-memdrv-kona-objs := \ ++ interface/vchiq_arm/vchiq_memdrv_kona.o ++ ++genversion = drivers/misc/vc04_services/interface/vchiq_arm/vchiq_genversion + +-EXTRA_CFLAGS += -DVCOS_VERIFY_BKPTS=1 -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -Idrivers/misc/vc04_services -Idrivers/misc/vc04_services/interface/vcos/linuxkernel ++GENVERSION_SRC_ROOT_DIR = . ++ifeq ($(CONFIG_ANDROID),y) ++GENVERSION_SRC_ROOT_DIR = $(srctree) ++endif + ++$(obj)/interface/vchiq_arm/vchiq_version.c: $(genversion) FORCE ++ echo "(new) Generating $@ ..." ++ perl $(srctree)/$(genversion) vchiq $(GENVERSION_SRC_ROOT_DIR) > $@ + ++clean-files := vchiq_version.c + ++endif +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vchi/connections/connection.h +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vchi/connections/connection.h 2013-07-26 19:32:28.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vchi/connections/connection.h 2013-07-26 19:36:51.000000000 +0000 +@@ -1,5 +1,5 @@ + /* +- * Copyright (c) 2010-2011 Broadcom Corporation. All rights reserved. ++ * Copyright (c) 2010-2012 Broadcom. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by +@@ -19,6 +19,10 @@ + #ifndef CONNECTION_H_ + #define CONNECTION_H_ + ++#include ++#include ++#include ++ + #include "interface/vchi/vchi_cfg_internal.h" + #include "interface/vchi/vchi_common.h" + #include "interface/vchi/message_drivers/message.h" +@@ -50,15 +54,15 @@ + + // Routine to create a service + typedef int32_t (*VCHI_CONNECTION_SERVICE_CONNECT_T)( VCHI_CONNECTION_STATE_T *state_handle, +- vcos_fourcc_t service_id, ++ int32_t service_id, + uint32_t rx_fifo_size, + uint32_t tx_fifo_size, + int server, + VCHI_CALLBACK_T callback, + void *callback_param, +- vcos_bool_t want_crc, +- vcos_bool_t want_unaligned_bulk_rx, +- vcos_bool_t want_unaligned_bulk_tx, ++ int32_t want_crc, ++ int32_t want_unaligned_bulk_rx, ++ int32_t want_unaligned_bulk_tx, + VCHI_CONNECTION_SERVICE_HANDLE_T *service_handle ); + + // Routine to close a service +@@ -116,7 +120,7 @@ + uint32_t *rx_timestamp ); + + // Routine to check whether the iterator has a next message +-typedef vcos_bool_t (*VCHI_CONNECTION_MSG_ITER_HAS_NEXT_T)( VCHI_CONNECTION_SERVICE_HANDLE_T service, ++typedef int32_t (*VCHI_CONNECTION_MSG_ITER_HAS_NEXT_T)( VCHI_CONNECTION_SERVICE_HANDLE_T service, + const VCHI_MSG_ITER_T *iter ); + + // Routine to advance the iterator +@@ -149,7 +153,7 @@ + void *bulk_handle ); + + // Routine to report if a server is available +-typedef int32_t (*VCHI_CONNECTION_SERVER_PRESENT)( VCHI_CONNECTION_STATE_T *state, vcos_fourcc_t service_id, int32_t peer_flags ); ++typedef int32_t (*VCHI_CONNECTION_SERVER_PRESENT)( VCHI_CONNECTION_STATE_T *state, int32_t service_id, int32_t peer_flags ); + + // Routine to report the number of RX slots available + typedef int (*VCHI_CONNECTION_RX_SLOTS_AVAILABLE)( const VCHI_CONNECTION_STATE_T *state ); +@@ -159,7 +163,7 @@ + + // Callback to indicate that the other side has added a buffer to the rx bulk DMA FIFO + typedef void (*VCHI_CONNECTION_RX_BULK_BUFFER_ADDED)(VCHI_CONNECTION_STATE_T *state, +- vcos_fourcc_t service, ++ int32_t service, + uint32_t length, + MESSAGE_TX_CHANNEL_T channel, + uint32_t channel_params, +@@ -167,10 +171,10 @@ + uint32_t data_offset); + + // Callback to inform a service that a Xon or Xoff message has been received +-typedef void (*VCHI_CONNECTION_FLOW_CONTROL)(VCHI_CONNECTION_STATE_T *state, vcos_fourcc_t service_id, int32_t xoff); ++typedef void (*VCHI_CONNECTION_FLOW_CONTROL)(VCHI_CONNECTION_STATE_T *state, int32_t service_id, int32_t xoff); + + // Callback to inform a service that a server available reply message has been received +-typedef void (*VCHI_CONNECTION_SERVER_AVAILABLE_REPLY)(VCHI_CONNECTION_STATE_T *state, vcos_fourcc_t service_id, uint32_t flags); ++typedef void (*VCHI_CONNECTION_SERVER_AVAILABLE_REPLY)(VCHI_CONNECTION_STATE_T *state, int32_t service_id, uint32_t flags); + + // Callback to indicate that bulk auxiliary messages have arrived + typedef void (*VCHI_CONNECTION_BULK_AUX_RECEIVED)(VCHI_CONNECTION_STATE_T *state); +@@ -185,7 +189,7 @@ + typedef void (*VCHI_CONNECTION_DISCONNECT)(VCHI_CONNECTION_STATE_T *state, uint32_t flags); + + // Callback to inform of a power control request +-typedef void (*VCHI_CONNECTION_POWER_CONTROL)(VCHI_CONNECTION_STATE_T *state, MESSAGE_TX_CHANNEL_T channel, vcos_bool_t enable); ++typedef void (*VCHI_CONNECTION_POWER_CONTROL)(VCHI_CONNECTION_STATE_T *state, MESSAGE_TX_CHANNEL_T channel, int32_t enable); + + // allocate memory suitably aligned for this connection + typedef void * (*VCHI_BUFFER_ALLOCATE)(VCHI_CONNECTION_SERVICE_HANDLE_T service_handle, uint32_t * length); +@@ -299,7 +303,7 @@ + const VCHI_CONNECTION_API_T *api; + VCHI_CONNECTION_STATE_T *state; + #ifdef VCHI_COARSE_LOCKING +- VCOS_SEMAPHORE_T sem; ++ struct semaphore sem; + #endif + }; + +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vchi/message_drivers/message.h +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vchi/message_drivers/message.h 2013-07-26 19:32:28.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vchi/message_drivers/message.h 2013-07-26 19:36:51.000000000 +0000 +@@ -1,5 +1,5 @@ + /* +- * Copyright (c) 2010-2011 Broadcom Corporation. All rights reserved. ++ * Copyright (c) 2010-2012 Broadcom. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by +@@ -19,8 +19,11 @@ + #ifndef _VCHI_MESSAGE_H_ + #define _VCHI_MESSAGE_H_ + ++#include ++#include ++#include ++ + #include "interface/vchi/vchi_cfg_internal.h" +-#include "interface/vcos/vcos.h" + #include "interface/vchi/vchi_common.h" + + +@@ -63,7 +66,7 @@ + struct rx_msg_slot_info *next; + //struct slot_info *prev; + #if !defined VCHI_COARSE_LOCKING +- VCOS_SEMAPHORE_T sem; ++ struct semaphore sem; + #endif + + uint8_t *addr; // base address of slot +@@ -84,7 +87,7 @@ + typedef struct rx_bulk_slotinfo_t { + struct rx_bulk_slotinfo_t *next; + +- VCOS_SEMAPHORE_T *blocking; ++ struct semaphore *blocking; + + // needed by DMA + void *addr; +@@ -127,7 +130,7 @@ + uint16_t slot_delta; // whether this message indicated slot delta + uint32_t len; // length of message + RX_MSG_SLOTINFO_T *slot; // slot this message is in +- vcos_fourcc_t service; // service id this message is destined for ++ int32_t service; // service id this message is destined for + uint32_t tx_timestamp; // timestamp from the header + uint32_t rx_timestamp; // timestamp when we parsed it + } message; +@@ -156,14 +159,14 @@ + VCHI_MDRIVER_HANDLE_T *(*open)( VCHI_MESSAGE_DRIVER_OPEN_T *params, void *state ); + int32_t (*suspending)( VCHI_MDRIVER_HANDLE_T *handle ); + int32_t (*resumed)( VCHI_MDRIVER_HANDLE_T *handle ); +- int32_t (*power_control)( VCHI_MDRIVER_HANDLE_T *handle, MESSAGE_TX_CHANNEL_T, vcos_bool_t enable ); ++ int32_t (*power_control)( VCHI_MDRIVER_HANDLE_T *handle, MESSAGE_TX_CHANNEL_T, int32_t enable ); + int32_t (*add_msg_rx_slot)( VCHI_MDRIVER_HANDLE_T *handle, RX_MSG_SLOTINFO_T *slot ); // rx message + int32_t (*add_bulk_rx)( VCHI_MDRIVER_HANDLE_T *handle, void *data, uint32_t len, RX_BULK_SLOTINFO_T *slot ); // rx data (bulk) + int32_t (*send)( VCHI_MDRIVER_HANDLE_T *handle, MESSAGE_TX_CHANNEL_T channel, const void *data, uint32_t len, VCHI_MSG_FLAGS_T flags, void *send_handle ); // tx (message & bulk) + void (*next_event)( VCHI_MDRIVER_HANDLE_T *handle, MESSAGE_EVENT_T *event ); // get the next event from message_driver + int32_t (*enable)( VCHI_MDRIVER_HANDLE_T *handle ); +- int32_t (*form_message)( VCHI_MDRIVER_HANDLE_T *handle, vcos_fourcc_t service_id, VCHI_MSG_VECTOR_T *vector, uint32_t count, void +- *address, uint32_t length_avail, uint32_t max_total_length, vcos_bool_t pad_to_fill, vcos_bool_t allow_partial ); ++ int32_t (*form_message)( VCHI_MDRIVER_HANDLE_T *handle, int32_t service_id, VCHI_MSG_VECTOR_T *vector, uint32_t count, void ++ *address, uint32_t length_avail, uint32_t max_total_length, int32_t pad_to_fill, int32_t allow_partial ); + + int32_t (*update_message)( VCHI_MDRIVER_HANDLE_T *handle, void *dest, int16_t *slot_count ); + int32_t (*buffer_aligned)( VCHI_MDRIVER_HANDLE_T *handle, int tx, int uncached, const void *address, const uint32_t length ); +@@ -172,7 +175,7 @@ + int (*rx_slot_size)( VCHI_MDRIVER_HANDLE_T *handle, int msg_size ); + int (*tx_slot_size)( VCHI_MDRIVER_HANDLE_T *handle, int msg_size ); + +- vcos_bool_t (*tx_supports_terminate)( const VCHI_MDRIVER_HANDLE_T *handle, MESSAGE_TX_CHANNEL_T channel ); ++ int32_t (*tx_supports_terminate)( const VCHI_MDRIVER_HANDLE_T *handle, MESSAGE_TX_CHANNEL_T channel ); + uint32_t (*tx_bulk_chunk_size)( const VCHI_MDRIVER_HANDLE_T *handle, MESSAGE_TX_CHANNEL_T channel ); + int (*tx_alignment)( const VCHI_MDRIVER_HANDLE_T *handle, MESSAGE_TX_CHANNEL_T channel ); + int (*rx_alignment)( const VCHI_MDRIVER_HANDLE_T *handle, MESSAGE_RX_CHANNEL_T channel ); +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vchi/vchi.h +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vchi/vchi.h 2013-07-26 19:32:28.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vchi/vchi.h 2013-07-26 19:36:51.000000000 +0000 +@@ -1,5 +1,5 @@ + /* +- * Copyright (c) 2010-2011 Broadcom Corporation. All rights reserved. ++ * Copyright (c) 2010-2012 Broadcom. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by +@@ -16,14 +16,9 @@ + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +-/*============================================================================= +-Contains the protypes for the vchi functions. +-=============================================================================*/ +- + #ifndef VCHI_H_ + #define VCHI_H_ + +-#include "interface/vcos/vcos.h" + #include "interface/vchi/vchi_cfg.h" + #include "interface/vchi/vchi_common.h" + #include "interface/vchi/connections/connection.h" +@@ -44,6 +39,12 @@ + #define VCHI_BULK_ALIGNED(x) (((unsigned long)(x) & (VCHI_BULK_ALIGN-1)) == 0) + #endif + ++struct vchi_version { ++ uint32_t version; ++ uint32_t version_min; ++}; ++#define VCHI_VERSION(v_) { v_, v_ } ++#define VCHI_VERSION_EX(v_, m_) { v_, m_ } + + typedef enum + { +@@ -88,8 +89,8 @@ + // Construct an entry in a msg vector for a message handle (h), starting at offset (o) of length (l) + #define VCHI_VEC_HANDLE(h,o,l) VCHI_VEC_HANDLE, { { (h), (o), (l) } } + +-// Macros to manipulate fourcc_t values +-#define MAKE_FOURCC(x) ((fourcc_t)( (x[0] << 24) | (x[1] << 16) | (x[2] << 8) | x[3] )) ++// Macros to manipulate 'FOURCC' values ++#define MAKE_FOURCC(x) ((int32_t)( (x[0] << 24) | (x[1] << 16) | (x[2] << 8) | x[3] )) + #define FOURCC_TO_CHAR(x) (x >> 24) & 0xFF,(x >> 16) & 0xFF,(x >> 8) & 0xFF, x & 0xFF + + +@@ -108,15 +109,22 @@ + + // structure used to provide the information needed to open a server or a client + typedef struct { +- vcos_fourcc_t service_id; +- VCHI_CONNECTION_T *connection; +- uint32_t rx_fifo_size; +- uint32_t tx_fifo_size; +- VCHI_CALLBACK_T callback; +- void *callback_param; +- vcos_bool_t want_unaligned_bulk_rx; // client intends to receive bulk transfers of odd lengths or into unaligned buffers +- vcos_bool_t want_unaligned_bulk_tx; // client intends to transmit bulk transfers of odd lengths or out of unaligned buffers +- vcos_bool_t want_crc; // client wants to check CRCs on (bulk) transfers. Only needs to be set at 1 end - will do both directions. ++ struct vchi_version version; ++ int32_t service_id; ++ VCHI_CONNECTION_T *connection; ++ uint32_t rx_fifo_size; ++ uint32_t tx_fifo_size; ++ VCHI_CALLBACK_T callback; ++ void *callback_param; ++ /* client intends to receive bulk transfers of ++ odd lengths or into unaligned buffers */ ++ int32_t want_unaligned_bulk_rx; ++ /* client intends to transmit bulk transfers of ++ odd lengths or out of unaligned buffers */ ++ int32_t want_unaligned_bulk_tx; ++ /* client wants to check CRCs on (bulk) xfers. ++ Only needs to be set at 1 end - will do both directions. */ ++ int32_t want_crc; + } SERVICE_CREATION_T; + + // Opaque handle for a VCHI instance +@@ -269,7 +277,7 @@ + extern int32_t vchi_held_msg_release( VCHI_HELD_MSG_T *message ); + + // Indicates whether the iterator has a next message. +-extern vcos_bool_t vchi_msg_iter_has_next( const VCHI_MSG_ITER_T *iter ); ++extern int32_t vchi_msg_iter_has_next( const VCHI_MSG_ITER_T *iter ); + + // Return the pointer and length for the next message and advance the iterator. + extern int32_t vchi_msg_iter_next( VCHI_MSG_ITER_T *iter, +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vchi/vchi_cfg.h +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vchi/vchi_cfg.h 2013-07-26 19:32:28.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vchi/vchi_cfg.h 2013-07-26 19:36:51.000000000 +0000 +@@ -1,5 +1,5 @@ + /* +- * Copyright (c) 2010-2011 Broadcom Corporation. All rights reserved. ++ * Copyright (c) 2010-2012 Broadcom. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by +@@ -16,11 +16,6 @@ + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +-/*============================================================================= +-Contains the #defines for the number of servers / clients etc, these can be +-over-ridden from the platform makefile if needed +-=============================================================================*/ +- + #ifndef VCHI_CFG_H_ + #define VCHI_CFG_H_ + +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vchi/vchi_cfg_internal.h +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vchi/vchi_cfg_internal.h 2013-07-26 19:32:28.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vchi/vchi_cfg_internal.h 2013-07-26 19:36:51.000000000 +0000 +@@ -1,5 +1,5 @@ + /* +- * Copyright (c) 2010-2011 Broadcom Corporation. All rights reserved. ++ * Copyright (c) 2010-2012 Broadcom. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vchi/vchi_common.h +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vchi/vchi_common.h 2013-07-26 19:32:28.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vchi/vchi_common.h 2013-07-26 19:36:51.000000000 +0000 +@@ -1,5 +1,5 @@ + /* +- * Copyright (c) 2010-2011 Broadcom Corporation. All rights reserved. ++ * Copyright (c) 2010-2012 Broadcom. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by +@@ -16,10 +16,6 @@ + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +-/*============================================================================= +-Contains global defs used by submodules within vchi. +-=============================================================================*/ +- + #ifndef VCHI_COMMON_H_ + #define VCHI_COMMON_H_ + +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vchi/vchi_mh.h +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vchi/vchi_mh.h 2013-07-26 19:32:07.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vchi/vchi_mh.h 2013-07-26 19:36:51.000000000 +0000 +@@ -19,7 +19,7 @@ + #ifndef VCHI_MH_H_ + #define VCHI_MH_H_ + +-#include ++#include + + typedef int32_t VCHI_MEM_HANDLE_T; + #define VCHI_MEM_HANDLE_INVALID 0 +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq.h +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq.h 2013-07-26 19:32:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq.h 2013-07-26 19:36:51.000000000 +0000 +@@ -21,7 +21,6 @@ + + #include "vchiq_if.h" + #include "vchiq_util.h" +-#include "interface/vcos/vcos.h" + + #endif + +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_2835_arm.c +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_2835_arm.c 2013-07-26 19:32:28.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_2835_arm.c 2013-07-26 19:36:51.000000000 +0000 +@@ -24,9 +24,9 @@ + #include + #include + #include ++#include ++#include + #include +-#include +-#include + + #include + +@@ -40,10 +40,14 @@ + + #include "vchiq_arm.h" + #include "vchiq_2835.h" ++#include "vchiq_connected.h" + + #define MAX_FRAGMENTS (VCHIQ_NUM_CURRENT_BULKS * 2) + +-#define VCOS_LOG_CATEGORY (&vchiq_arm_log_category) ++typedef struct vchiq_2835_state_struct { ++ int inited; ++ VCHIQ_ARM_STATE_T arm_state; ++} VCHIQ_2835_ARM_STATE_T; + + static char *g_slot_mem; + static int g_slot_mem_size; +@@ -52,29 +56,21 @@ + static FRAGMENTS_T *g_free_fragments; + struct semaphore g_free_fragments_sema; + +-#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,36) ++extern int vchiq_arm_log_level; ++ + static DEFINE_SEMAPHORE(g_free_fragments_mutex); +-#else +-static DECLARE_MUTEX(g_free_fragments_mutex); +-#endif + + static irqreturn_t + vchiq_doorbell_irq(int irq, void *dev_id); + + static int + create_pagelist(char __user *buf, size_t count, unsigned short type, +- struct task_struct *task, PAGELIST_T ** ppagelist); ++ struct task_struct *task, PAGELIST_T ** ppagelist); + + static void + free_pagelist(PAGELIST_T *pagelist, int actual); + + int __init +-vchiq_platform_vcos_init(void) +-{ +- return (vcos_init() == VCOS_SUCCESS) ? 0 : -EINVAL; +-} +- +-int __init + vchiq_platform_init(VCHIQ_STATE_T *state) + { + VCHIQ_SLOT_ZERO_T *vchiq_slot_zero; +@@ -90,48 +86,49 @@ + &g_slot_phys, GFP_ATOMIC); + + if (!g_slot_mem) { +- vcos_log_error("Unable to allocate channel memory"); ++ vchiq_log_error(vchiq_arm_log_level, ++ "Unable to allocate channel memory"); + err = -ENOMEM; + goto failed_alloc; + } + +- vcos_assert(((int)g_slot_mem & (PAGE_SIZE - 1)) == 0); ++ WARN_ON(((int)g_slot_mem & (PAGE_SIZE - 1)) != 0); + + vchiq_slot_zero = vchiq_init_slots(g_slot_mem, g_slot_mem_size); +- if (!vchiq_slot_zero) +- { +- err = -EINVAL; +- goto failed_init_slots; ++ if (!vchiq_slot_zero) { ++ err = -EINVAL; ++ goto failed_init_slots; + } + +- vchiq_slot_zero->platform_data[VCHIQ_PLATFORM_FRAGMENTS_OFFSET_IDX] = (int)g_slot_phys + g_slot_mem_size; +- vchiq_slot_zero->platform_data[VCHIQ_PLATFORM_FRAGMENTS_COUNT_IDX] = MAX_FRAGMENTS; ++ vchiq_slot_zero->platform_data[VCHIQ_PLATFORM_FRAGMENTS_OFFSET_IDX] = ++ (int)g_slot_phys + g_slot_mem_size; ++ vchiq_slot_zero->platform_data[VCHIQ_PLATFORM_FRAGMENTS_COUNT_IDX] = ++ MAX_FRAGMENTS; + + g_fragments_base = (FRAGMENTS_T *)(g_slot_mem + g_slot_mem_size); + g_slot_mem_size += frag_mem_size; + + g_free_fragments = g_fragments_base; + for (i = 0; i < (MAX_FRAGMENTS - 1); i++) { +- *(FRAGMENTS_T **) & g_fragments_base[i] = ++ *(FRAGMENTS_T **)&g_fragments_base[i] = + &g_fragments_base[i + 1]; + } +- *(FRAGMENTS_T **) & g_fragments_base[i] = NULL; ++ *(FRAGMENTS_T **)&g_fragments_base[i] = NULL; + sema_init(&g_free_fragments_sema, MAX_FRAGMENTS); + + if (vchiq_init_state(state, vchiq_slot_zero, 0/*slave*/) != +- VCHIQ_SUCCESS) +- { ++ VCHIQ_SUCCESS) { + err = -EINVAL; + goto failed_vchiq_init; + } + + err = request_irq(VCHIQ_DOORBELL_IRQ, vchiq_doorbell_irq, +- IRQF_SAMPLE_RANDOM | IRQF_IRQPOLL, "VCHIQ doorbell", ++ IRQF_IRQPOLL, "VCHIQ doorbell", + state); +- if (err < 0) +- { +- printk( KERN_ERR "%s: failed to register irq=%d err=%d\n", __func__, +- VCHIQ_DOORBELL_IRQ, err ); ++ if (err < 0) { ++ vchiq_log_error(vchiq_arm_log_level, "%s: failed to register " ++ "irq=%d err=%d", __func__, ++ VCHIQ_DOORBELL_IRQ, err); + goto failed_request_irq; + } + +@@ -141,39 +138,67 @@ + + bcm_mailbox_write(MBOX_CHAN_VCHIQ, (unsigned int)g_slot_phys); + +- vcos_log_info("vchiq_init - done (slots %x, phys %x)", ++ vchiq_log_info(vchiq_arm_log_level, ++ "vchiq_init - done (slots %x, phys %x)", + (unsigned int)vchiq_slot_zero, g_slot_phys); + +- return 0; ++ vchiq_call_connected_callbacks(); ++ ++ return 0; + + failed_request_irq: + failed_vchiq_init: + failed_init_slots: +- dma_free_coherent(NULL, g_slot_mem_size, g_slot_mem, g_slot_phys); ++ dma_free_coherent(NULL, g_slot_mem_size, g_slot_mem, g_slot_phys); + + failed_alloc: +- return err; ++ return err; + } + + void __exit + vchiq_platform_exit(VCHIQ_STATE_T *state) + { +- free_irq(VCHIQ_DOORBELL_IRQ, state); +- dma_free_coherent(NULL, g_slot_mem_size, +- g_slot_mem, g_slot_phys); ++ free_irq(VCHIQ_DOORBELL_IRQ, state); ++ dma_free_coherent(NULL, g_slot_mem_size, ++ g_slot_mem, g_slot_phys); ++} ++ ++ ++VCHIQ_STATUS_T ++vchiq_platform_init_state(VCHIQ_STATE_T *state) ++{ ++ VCHIQ_STATUS_T status = VCHIQ_SUCCESS; ++ state->platform_state = kzalloc(sizeof(VCHIQ_2835_ARM_STATE_T), GFP_KERNEL); ++ ((VCHIQ_2835_ARM_STATE_T*)state->platform_state)->inited = 1; ++ status = vchiq_arm_init_state(state, &((VCHIQ_2835_ARM_STATE_T*)state->platform_state)->arm_state); ++ if(status != VCHIQ_SUCCESS) ++ { ++ ((VCHIQ_2835_ARM_STATE_T*)state->platform_state)->inited = 0; ++ } ++ return status; ++} ++ ++VCHIQ_ARM_STATE_T* ++vchiq_platform_get_arm_state(VCHIQ_STATE_T *state) ++{ ++ if(!((VCHIQ_2835_ARM_STATE_T*)state->platform_state)->inited) ++ { ++ BUG(); ++ } ++ return &((VCHIQ_2835_ARM_STATE_T*)state->platform_state)->arm_state; + } + + void + remote_event_signal(REMOTE_EVENT_T *event) + { ++ wmb(); ++ + event->fired = 1; + +- /* The test on the next line also ensures the write on the previous line +- has completed */ ++ dsb(); /* data barrier operation */ + + if (event->armed) { + /* trigger vc interrupt */ +- dsb(); /* data barrier operation */ + + writel(0, __io_address(ARM_0_BELL2)); + } +@@ -182,13 +207,10 @@ + int + vchiq_copy_from_user(void *dst, const void *src, int size) + { +- if ( (uint32_t)src < TASK_SIZE) +- { ++ if ((uint32_t)src < TASK_SIZE) { + return copy_from_user(dst, src, size); +- } +- else +- { +- memcpy( dst, src, size ); ++ } else { ++ memcpy(dst, src, size); + return 0; + } + } +@@ -200,7 +222,7 @@ + PAGELIST_T *pagelist; + int ret; + +- vcos_assert(memhandle == VCHI_MEM_HANDLE_INVALID); ++ WARN_ON(memhandle != VCHI_MEM_HANDLE_INVALID); + + ret = create_pagelist((char __user *)offset, size, + (dir == VCHIQ_BULK_RECEIVE) +@@ -224,7 +246,8 @@ + void + vchiq_complete_bulk(VCHIQ_BULK_T *bulk) + { +- free_pagelist((PAGELIST_T *)bulk->remote_data, bulk->actual); ++ if (bulk && bulk->remote_data && bulk->actual) ++ free_pagelist((PAGELIST_T *)bulk->remote_data, bulk->actual); + } + + void +@@ -234,83 +257,57 @@ + * This should only be called on the master (VideoCore) side, but + * provide an implementation to avoid the need for ifdefery. + */ +- vcos_assert(!"This code should not be called by the ARM on BCM2835"); ++ BUG(); + } + + void + vchiq_dump_platform_state(void *dump_context) + { +- char buf[80]; +- int len; +- len = vcos_snprintf(buf, sizeof(buf), +- " Platform: 2835 (VC master)"); +- vchiq_dump(dump_context, buf, len + 1); ++ char buf[80]; ++ int len; ++ len = snprintf(buf, sizeof(buf), ++ " Platform: 2835 (VC master)"); ++ vchiq_dump(dump_context, buf, len + 1); + } + + VCHIQ_STATUS_T + vchiq_platform_suspend(VCHIQ_STATE_T *state) + { +- vcos_unused(state); +- vcos_assert_msg(0, "Suspend/resume not supported"); + return VCHIQ_ERROR; + } + + VCHIQ_STATUS_T + vchiq_platform_resume(VCHIQ_STATE_T *state) + { +- vcos_unused(state); +- vcos_assert_msg(0, "Suspend/resume not supported"); +- return VCHIQ_ERROR; ++ return VCHIQ_SUCCESS; + } + + void + vchiq_platform_paused(VCHIQ_STATE_T *state) + { +- vcos_unused(state); +- vcos_assert_msg(0, "Suspend/resume not supported"); + } + + void + vchiq_platform_resumed(VCHIQ_STATE_T *state) + { +- vcos_unused(state); +- vcos_assert_msg(0, "Suspend/resume not supported"); + } + + int + vchiq_platform_videocore_wanted(VCHIQ_STATE_T* state) + { +- vcos_unused(state); + return 1; // autosuspend not supported - videocore always wanted + } + +-#if VCOS_HAVE_TIMER + int + vchiq_platform_use_suspend_timer(void) + { + return 0; + } +-#endif + void + vchiq_dump_platform_use_state(VCHIQ_STATE_T *state) + { +- vcos_unused(state); ++ vchiq_log_info((vchiq_arm_log_level>=VCHIQ_LOG_INFO),"Suspend timer not in use"); + } +- +-VCHIQ_STATUS_T +-vchiq_platform_init_state(VCHIQ_STATE_T *state) +-{ +- vcos_unused(state); +- return VCHIQ_SUCCESS; +-} +- +-VCHIQ_ARM_STATE_T* +-vchiq_platform_get_arm_state(VCHIQ_STATE_T *state) +-{ +- vcos_unused(state); +- return NULL; +-} +- + /* + * Local functions + */ +@@ -318,7 +315,7 @@ + static irqreturn_t + vchiq_doorbell_irq(int irq, void *dev_id) + { +- VCHIQ_STATE_T *state = dev_id; ++ VCHIQ_STATE_T *state = dev_id; + irqreturn_t ret = IRQ_NONE; + unsigned int status; + +@@ -334,17 +331,17 @@ + } + + /* There is a potential problem with partial cache lines (pages?) +- at the ends of the block when reading. If the CPU accessed anything in +- the same line (page?) then it may have pulled old data into the cache, +- obscuring the new data underneath. We can solve this by transferring the +- partial cache lines separately, and allowing the ARM to copy into the +- cached area. +- +- N.B. This implementation plays slightly fast and loose with the Linux +- driver programming rules, e.g. its use of __virt_to_bus instead of +- dma_map_single, but it isn't a multi-platform driver and it benefits +- from increased speed as a result. +- */ ++** at the ends of the block when reading. If the CPU accessed anything in ++** the same line (page?) then it may have pulled old data into the cache, ++** obscuring the new data underneath. We can solve this by transferring the ++** partial cache lines separately, and allowing the ARM to copy into the ++** cached area. ++ ++** N.B. This implementation plays slightly fast and loose with the Linux ++** driver programming rules, e.g. its use of __virt_to_bus instead of ++** dma_map_single, but it isn't a multi-platform driver and it benefits ++** from increased speed as a result. ++*/ + + static int + create_pagelist(char __user *buf, size_t count, unsigned short type, +@@ -363,13 +360,16 @@ + + *ppagelist = NULL; + +- /* Allocate enough storage to hold the page pointers and the page list */ +- pagelist = (PAGELIST_T *) kmalloc(sizeof(PAGELIST_T) + ++ /* Allocate enough storage to hold the page pointers and the page ++ ** list ++ */ ++ pagelist = kmalloc(sizeof(PAGELIST_T) + + (num_pages * sizeof(unsigned long)) + + (num_pages * sizeof(pages[0])), + GFP_KERNEL); + +- vcos_log_trace("create_pagelist - %x", (unsigned int)pagelist); ++ vchiq_log_trace(vchiq_arm_log_level, ++ "create_pagelist - %x", (unsigned int)pagelist); + if (!pagelist) + return -ENOMEM; + +@@ -380,17 +380,22 @@ + actual_pages = get_user_pages(task, task->mm, + (unsigned long)buf & ~(PAGE_SIZE - 1), num_pages, + (type == PAGELIST_READ) /*Write */ , 0 /*Force */ , +- pages, NULL /*vmas */ ); ++ pages, NULL /*vmas */); + up_read(&task->mm->mmap_sem); + +- if (actual_pages != num_pages) +- { +- for (i = 0; i < actual_pages; i++) { +- page_cache_release(pages[i]); +- } +- kfree(pagelist); +- return -EINVAL; +- } ++ if (actual_pages != num_pages) ++ { ++ /* This is probably due to the process being killed */ ++ while (actual_pages > 0) ++ { ++ actual_pages--; ++ page_cache_release(pages[actual_pages]); ++ } ++ kfree(pagelist); ++ if (actual_pages == 0) ++ actual_pages = -ENOMEM; ++ return actual_pages; ++ } + + pagelist->length = count; + pagelist->type = type; +@@ -423,7 +428,8 @@ + /* Partial cache lines (fragments) require special measures */ + if ((type == PAGELIST_READ) && + ((pagelist->offset & (CACHE_LINE_SIZE - 1)) || +- ((pagelist->offset + pagelist->length) & (CACHE_LINE_SIZE - 1)))) { ++ ((pagelist->offset + pagelist->length) & ++ (CACHE_LINE_SIZE - 1)))) { + FRAGMENTS_T *fragments; + + if (down_interruptible(&g_free_fragments_sema) != 0) { +@@ -431,11 +437,11 @@ + return -EINTR; + } + +- vcos_assert(g_free_fragments != NULL); ++ WARN_ON(g_free_fragments == NULL); + + down(&g_free_fragments_mutex); + fragments = (FRAGMENTS_T *) g_free_fragments; +- vcos_assert(fragments != NULL); ++ WARN_ON(fragments == NULL); + g_free_fragments = *(FRAGMENTS_T **) g_free_fragments; + up(&g_free_fragments_mutex); + pagelist->type = +@@ -459,39 +465,40 @@ + struct page **pages; + unsigned int num_pages, i; + +- vcos_log_trace("free_pagelist - %x, %d", (unsigned int)pagelist, actual); ++ vchiq_log_trace(vchiq_arm_log_level, ++ "free_pagelist - %x, %d", (unsigned int)pagelist, actual); + + num_pages = +- (pagelist->length + pagelist->offset + PAGE_SIZE - 1) / PAGE_SIZE; ++ (pagelist->length + pagelist->offset + PAGE_SIZE - 1) / ++ PAGE_SIZE; + + pages = (struct page **)(pagelist->addrs + num_pages); + + /* Deal with any partial cache lines (fragments) */ + if (pagelist->type >= PAGELIST_READ_WITH_FRAGMENTS) { +- FRAGMENTS_T *fragments = +- g_fragments_base + (pagelist->type - +- PAGELIST_READ_WITH_FRAGMENTS); ++ FRAGMENTS_T *fragments = g_fragments_base + ++ (pagelist->type - PAGELIST_READ_WITH_FRAGMENTS); + int head_bytes, tail_bytes; +- +- if (actual >= 0) +- { +- if ((head_bytes = (CACHE_LINE_SIZE - pagelist->offset) & (CACHE_LINE_SIZE - 1)) != 0) { +- if (head_bytes > actual) +- head_bytes = actual; +- +- memcpy((char *)page_address(pages[0]) + +- pagelist->offset, fragments->headbuf, +- head_bytes); +- } +- if ((head_bytes < actual) && +- (tail_bytes = +- (pagelist->offset + actual) & (CACHE_LINE_SIZE - +- 1)) != 0) { +- memcpy((char *)page_address(pages[num_pages - 1]) + +- ((pagelist->offset + actual) & (PAGE_SIZE - +- 1) & ~(CACHE_LINE_SIZE - 1)), +- fragments->tailbuf, tail_bytes); +- } ++ head_bytes = (CACHE_LINE_SIZE - pagelist->offset) & ++ (CACHE_LINE_SIZE - 1); ++ tail_bytes = (pagelist->offset + actual) & ++ (CACHE_LINE_SIZE - 1); ++ ++ if ((actual >= 0) && (head_bytes != 0)) { ++ if (head_bytes > actual) ++ head_bytes = actual; ++ ++ memcpy((char *)page_address(pages[0]) + ++ pagelist->offset, ++ fragments->headbuf, ++ head_bytes); ++ } ++ if ((actual >= 0) && (head_bytes < actual) && ++ (tail_bytes != 0)) { ++ memcpy((char *)page_address(pages[num_pages - 1]) + ++ ((pagelist->offset + actual) & ++ (PAGE_SIZE - 1) & ~(CACHE_LINE_SIZE - 1)), ++ fragments->tailbuf, tail_bytes); + } + + down(&g_free_fragments_mutex); +@@ -509,4 +516,3 @@ + + kfree(pagelist); + } +- +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_arm.c +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_arm.c 2013-07-26 19:32:49.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_arm.c 2013-07-26 19:36:51.000000000 +0000 +@@ -26,6 +26,10 @@ + #include + #include + #include ++#include ++#include ++#include ++#include + + #include "vchiq_core.h" + #include "vchiq_ioctl.h" +@@ -45,139 +49,128 @@ + #define MAX_ELEMENTS 8 + #define MSG_QUEUE_SIZE 64 + +-#define VCOS_LOG_CATEGORY (&vchiq_arm_log_category) ++#define KEEPALIVE_VER 1 ++#define KEEPALIVE_VER_MIN KEEPALIVE_VER + +-#define VCHIQ_ARM_VCSUSPEND_TASK_STACK 4096 ++/* Run time control of log level, based on KERN_XXX level. */ ++int vchiq_arm_log_level = VCHIQ_LOG_DEFAULT; ++int vchiq_susp_log_level = VCHIQ_LOG_DEFAULT; + +-#if VCOS_HAVE_TIMER + #define SUSPEND_TIMER_TIMEOUT_MS 100 +-static VCOS_TIMER_T g_suspend_timer; +-static void suspend_timer_callback(void *context); +-#endif +- +- +-typedef struct client_service_struct { +- VCHIQ_SERVICE_T *service; +- void *userdata; +- VCHIQ_INSTANCE_T instance; +- int handle; +- int is_vchi; +- volatile int dequeue_pending; +- volatile int message_available_pos; +- volatile int msg_insert; +- volatile int msg_remove; +- VCOS_EVENT_T insert_event; +- VCOS_EVENT_T remove_event; +- VCHIQ_HEADER_T *msg_queue[MSG_QUEUE_SIZE]; ++#define SUSPEND_RETRY_TIMER_TIMEOUT_MS 1000 ++ ++#define VC_SUSPEND_NUM_OFFSET 3 /* number of values before idle which are -ve */ ++static const char *const suspend_state_names[] = { ++ "VC_SUSPEND_FORCE_CANCELED", ++ "VC_SUSPEND_REJECTED", ++ "VC_SUSPEND_FAILED", ++ "VC_SUSPEND_IDLE", ++ "VC_SUSPEND_REQUESTED", ++ "VC_SUSPEND_IN_PROGRESS", ++ "VC_SUSPEND_SUSPENDED" ++}; ++#define VC_RESUME_NUM_OFFSET 1 /* number of values before idle which are -ve */ ++static const char *const resume_state_names[] = { ++ "VC_RESUME_FAILED", ++ "VC_RESUME_IDLE", ++ "VC_RESUME_REQUESTED", ++ "VC_RESUME_IN_PROGRESS", ++ "VC_RESUME_RESUMED" ++}; ++/* The number of times we allow force suspend to timeout before actually ++** _forcing_ suspend. This is to cater for SW which fails to release vchiq ++** correctly - we don't want to prevent ARM suspend indefinitely in this case. ++*/ ++#define FORCE_SUSPEND_FAIL_MAX 8 ++ ++/* The time in ms allowed for videocore to go idle when force suspend has been ++ * requested */ ++#define FORCE_SUSPEND_TIMEOUT_MS 200 ++ ++ ++static void suspend_timer_callback(unsigned long context); ++static int vchiq_proc_add_instance(VCHIQ_INSTANCE_T instance); ++static void vchiq_proc_remove_instance(VCHIQ_INSTANCE_T instance); ++ ++ ++typedef struct user_service_struct { ++ VCHIQ_SERVICE_T *service; ++ void *userdata; ++ VCHIQ_INSTANCE_T instance; ++ int is_vchi; ++ int dequeue_pending; ++ int message_available_pos; ++ int msg_insert; ++ int msg_remove; ++ struct semaphore insert_event; ++ struct semaphore remove_event; ++ VCHIQ_HEADER_T * msg_queue[MSG_QUEUE_SIZE]; + } USER_SERVICE_T; + ++struct bulk_waiter_node { ++ struct bulk_waiter bulk_waiter; ++ int pid; ++ struct list_head list; ++}; ++ + struct vchiq_instance_struct { +- VCHIQ_STATE_T *state; +- VCHIQ_COMPLETION_DATA_T completions[MAX_COMPLETIONS]; +- volatile int completion_insert; +- volatile int completion_remove; +- VCOS_EVENT_T insert_event; +- VCOS_EVENT_T remove_event; +- +- USER_SERVICE_T services[MAX_SERVICES]; +- +- int connected; +- int closing; +- int pid; +- int mark; ++ VCHIQ_STATE_T *state; ++ VCHIQ_COMPLETION_DATA_T completions[MAX_COMPLETIONS]; ++ int completion_insert; ++ int completion_remove; ++ struct semaphore insert_event; ++ struct semaphore remove_event; ++ struct mutex completion_mutex; ++ ++ int connected; ++ int closing; ++ int pid; ++ int mark; ++ ++ struct list_head bulk_waiter_list; ++ struct mutex bulk_waiter_list_mutex; ++ ++ struct proc_dir_entry *proc_entry; + }; + +-typedef struct dump_context_struct +-{ +- char __user *buf; +- size_t actual; +- size_t space; +- loff_t offset; ++typedef struct dump_context_struct { ++ char __user *buf; ++ size_t actual; ++ size_t space; ++ loff_t offset; + } DUMP_CONTEXT_T; + +-VCOS_LOG_CAT_T vchiq_arm_log_category; +- + static struct cdev vchiq_cdev; + static dev_t vchiq_devid; + static VCHIQ_STATE_T g_state; + static struct class *vchiq_class; + static struct device *vchiq_dev; ++static DEFINE_SPINLOCK(msg_queue_spinlock); + +-static const char *ioctl_names[] = +-{ +- "CONNECT", +- "SHUTDOWN", +- "CREATE_SERVICE", +- "REMOVE_SERVICE", +- "QUEUE_MESSAGE", +- "QUEUE_BULK_TRANSMIT", +- "QUEUE_BULK_RECEIVE", +- "AWAIT_COMPLETION", +- "DEQUEUE_MESSAGE", +- "GET_CLIENT_ID", +- "GET_CONFIG", +- "CLOSE_SERVICE", +- "USE_SERVICE", +- "RELEASE_SERVICE", +- "SET_SERVICE_OPTION", +- "DUMP_PHYS_MEM" ++static const char *const ioctl_names[] = { ++ "CONNECT", ++ "SHUTDOWN", ++ "CREATE_SERVICE", ++ "REMOVE_SERVICE", ++ "QUEUE_MESSAGE", ++ "QUEUE_BULK_TRANSMIT", ++ "QUEUE_BULK_RECEIVE", ++ "AWAIT_COMPLETION", ++ "DEQUEUE_MESSAGE", ++ "GET_CLIENT_ID", ++ "GET_CONFIG", ++ "CLOSE_SERVICE", ++ "USE_SERVICE", ++ "RELEASE_SERVICE", ++ "SET_SERVICE_OPTION", ++ "DUMP_PHYS_MEM" + }; + +-vcos_static_assert(vcos_countof(ioctl_names) == (VCHIQ_IOC_MAX + 1)); +- +-VCOS_LOG_LEVEL_T vchiq_default_arm_log_level = VCOS_LOG_ERROR; ++vchiq_static_assert((sizeof(ioctl_names)/sizeof(ioctl_names[0])) == ++ (VCHIQ_IOC_MAX + 1)); + + static void +-dump_phys_mem( void *virt_addr, uint32_t num_bytes ); +- +-/**************************************************************************** +-* +-* find_service_by_handle +-* +-***************************************************************************/ +- +-static inline USER_SERVICE_T *find_service_by_handle( +- VCHIQ_INSTANCE_T instance, int handle ) +-{ +- USER_SERVICE_T *user_service; +- +- if (( handle >= 0 ) +- && ( handle < MAX_SERVICES )) +- { +- user_service = &instance->services[ handle ]; +- +- if ( user_service->service != NULL ) +- { +- return user_service; +- } +- } +- +- return NULL; +-} +- +-/**************************************************************************** +-* +-* find_avail_service_handle +-* +-***************************************************************************/ +- +-static inline USER_SERVICE_T *find_avail_service_handle( +- VCHIQ_INSTANCE_T instance) +-{ +- int handle; +- +- for ( handle = 0; handle < MAX_SERVICES; handle++ ) +- { +- if ( instance->services[handle].service == NULL ) +- { +- instance->services[handle].instance = instance; +- instance->services[handle].handle = handle; +- +- return &instance->services[handle]; +- } +- } +- return NULL; +-} ++dump_phys_mem(void *virt_addr, uint32_t num_bytes); + + /**************************************************************************** + * +@@ -187,47 +180,58 @@ + + static VCHIQ_STATUS_T + add_completion(VCHIQ_INSTANCE_T instance, VCHIQ_REASON_T reason, +- VCHIQ_HEADER_T *header, USER_SERVICE_T *service, void *bulk_userdata) ++ VCHIQ_HEADER_T *header, USER_SERVICE_T *user_service, ++ void *bulk_userdata) + { +- VCHIQ_COMPLETION_DATA_T *completion; +- DEBUG_INITIALISE(g_state.local) ++ VCHIQ_COMPLETION_DATA_T *completion; ++ DEBUG_INITIALISE(g_state.local) + +- while (instance->completion_insert == +- (instance->completion_remove + MAX_COMPLETIONS)) { +- /* Out of space - wait for the client */ +- DEBUG_TRACE(SERVICE_CALLBACK_LINE); +- vcos_log_trace("add_completion - completion queue full"); +- DEBUG_COUNT(COMPLETION_QUEUE_FULL_COUNT); +- if (vcos_event_wait(&instance->remove_event) != VCOS_SUCCESS) { +- vcos_log_info("service_callback interrupted"); +- return VCHIQ_RETRY; +- } else if (instance->closing) { +- vcos_log_info("service_callback closing"); +- return VCHIQ_ERROR; +- } +- DEBUG_TRACE(SERVICE_CALLBACK_LINE); +- } +- +- completion = +- &instance-> +- completions[instance->completion_insert & (MAX_COMPLETIONS - 1)]; +- +- completion->header = header; +- completion->reason = reason; +- completion->service_userdata = service; +- completion->bulk_userdata = bulk_userdata; +- +- /* A write barrier is needed here to ensure that the entire completion +- record is written out before the insert point. */ +- vcos_wmb(&completion->bulk_userdata); +- +- if (reason == VCHIQ_MESSAGE_AVAILABLE) +- service->message_available_pos = instance->completion_insert; +- instance->completion_insert++; ++ while (instance->completion_insert == ++ (instance->completion_remove + MAX_COMPLETIONS)) { ++ /* Out of space - wait for the client */ ++ DEBUG_TRACE(SERVICE_CALLBACK_LINE); ++ vchiq_log_trace(vchiq_arm_log_level, ++ "add_completion - completion queue full"); ++ DEBUG_COUNT(COMPLETION_QUEUE_FULL_COUNT); ++ if (down_interruptible(&instance->remove_event) != 0) { ++ vchiq_log_info(vchiq_arm_log_level, ++ "service_callback interrupted"); ++ return VCHIQ_RETRY; ++ } else if (instance->closing) { ++ vchiq_log_info(vchiq_arm_log_level, ++ "service_callback closing"); ++ return VCHIQ_ERROR; ++ } ++ DEBUG_TRACE(SERVICE_CALLBACK_LINE); ++ } ++ ++ completion = ++ &instance->completions[instance->completion_insert & ++ (MAX_COMPLETIONS - 1)]; ++ ++ completion->header = header; ++ completion->reason = reason; ++ /* N.B. service_userdata is updated while processing AWAIT_COMPLETION */ ++ completion->service_userdata = user_service->service; ++ completion->bulk_userdata = bulk_userdata; ++ ++ if (reason == VCHIQ_SERVICE_CLOSED) ++ /* Take an extra reference, to be held until ++ this CLOSED notification is delivered. */ ++ lock_service(user_service->service); ++ ++ /* A write barrier is needed here to ensure that the entire completion ++ record is written out before the insert point. */ ++ wmb(); ++ ++ if (reason == VCHIQ_MESSAGE_AVAILABLE) ++ user_service->message_available_pos = ++ instance->completion_insert; ++ instance->completion_insert++; + +- vcos_event_signal(&instance->insert_event); ++ up(&instance->insert_event); + +- return VCHIQ_SUCCESS; ++ return VCHIQ_SUCCESS; + } + + /**************************************************************************** +@@ -238,90 +242,104 @@ + + static VCHIQ_STATUS_T + service_callback(VCHIQ_REASON_T reason, VCHIQ_HEADER_T *header, +- VCHIQ_SERVICE_HANDLE_T handle, void *bulk_userdata) ++ VCHIQ_SERVICE_HANDLE_T handle, void *bulk_userdata) + { +- /* How do we ensure the callback goes to the right client? +- The service_user data points to a USER_SERVICE_T record containing the +- original callback and the user state structure, which contains a circular +- buffer for completion records. +- */ +- USER_SERVICE_T *service = +- (USER_SERVICE_T *) VCHIQ_GET_SERVICE_USERDATA(handle); +- VCHIQ_INSTANCE_T instance = service->instance; +- DEBUG_INITIALISE(g_state.local) +- +- DEBUG_TRACE(SERVICE_CALLBACK_LINE); +- vcos_log_trace +- ("service_callback - service %lx(%d), reason %d, header %lx, " +- "instance %lx, bulk_userdata %lx", +- (unsigned long)service, ((VCHIQ_SERVICE_T *) handle)->localport, +- reason, (unsigned long)header, +- (unsigned long)instance, (unsigned long)bulk_userdata); +- +- if (!instance || instance->closing) { +- return VCHIQ_SUCCESS; +- } +- +- if (header && service->is_vchi) +- { +- while (service->msg_insert == (service->msg_remove + MSG_QUEUE_SIZE)) +- { +- DEBUG_TRACE(SERVICE_CALLBACK_LINE); +- DEBUG_COUNT(MSG_QUEUE_FULL_COUNT); +- vcos_log_trace("service_callback - msg queue full"); +- /* If there is no MESSAGE_AVAILABLE in the completion queue, add one */ +- if ((service->message_available_pos - instance->completion_remove) < 0) +- { +- VCHIQ_STATUS_T status; +- vcos_log_warn("Inserting extra MESSAGE_AVAILABLE"); +- DEBUG_TRACE(SERVICE_CALLBACK_LINE); +- status = add_completion(instance, reason, NULL, service, bulk_userdata); +- if (status != VCHIQ_SUCCESS) +- { +- DEBUG_TRACE(SERVICE_CALLBACK_LINE); +- return status; +- } +- } +- +- DEBUG_TRACE(SERVICE_CALLBACK_LINE); +- if (vcos_event_wait(&service->remove_event) != VCOS_SUCCESS) { +- vcos_log_info("service_callback interrupted"); +- DEBUG_TRACE(SERVICE_CALLBACK_LINE); +- return VCHIQ_RETRY; +- } else if (instance->closing) { +- vcos_log_info("service_callback closing"); +- DEBUG_TRACE(SERVICE_CALLBACK_LINE); +- return VCHIQ_ERROR; +- } +- DEBUG_TRACE(SERVICE_CALLBACK_LINE); +- } +- +- service->msg_queue[service->msg_insert & (MSG_QUEUE_SIZE - 1)] = +- header; +- +- /* A write memory barrier is needed to ensure that the store of header +- is completed before the insertion point is updated */ +- vcos_wmb(&service->msg_queue[service->msg_insert & (MSG_QUEUE_SIZE - 1)]); +- +- service->msg_insert++; +- vcos_event_signal(&service->insert_event); +- +- /* If there is a thread waiting in DEQUEUE_MESSAGE, or if +- there is a MESSAGE_AVAILABLE in the completion queue then +- bypass the completion queue. */ +- if (((service->message_available_pos - instance->completion_remove) >= 0) || +- service->dequeue_pending) +- { +- DEBUG_TRACE(SERVICE_CALLBACK_LINE); +- service->dequeue_pending = 0; +- return VCHIQ_SUCCESS; +- } +- +- header = NULL; +- } +- DEBUG_TRACE(SERVICE_CALLBACK_LINE); ++ /* How do we ensure the callback goes to the right client? ++ ** The service_user data points to a USER_SERVICE_T record containing ++ ** the original callback and the user state structure, which contains a ++ ** circular buffer for completion records. ++ */ ++ USER_SERVICE_T *user_service; ++ VCHIQ_SERVICE_T *service; ++ VCHIQ_INSTANCE_T instance; ++ DEBUG_INITIALISE(g_state.local) ++ ++ DEBUG_TRACE(SERVICE_CALLBACK_LINE); ++ ++ service = handle_to_service(handle); ++ BUG_ON(!service); ++ user_service = (USER_SERVICE_T *)service->base.userdata; ++ instance = user_service->instance; ++ ++ if (!instance || instance->closing) ++ return VCHIQ_SUCCESS; ++ ++ vchiq_log_trace(vchiq_arm_log_level, ++ "service_callback - service %lx(%d), reason %d, header %lx, " ++ "instance %lx, bulk_userdata %lx", ++ (unsigned long)user_service, ++ service->localport, ++ reason, (unsigned long)header, ++ (unsigned long)instance, (unsigned long)bulk_userdata); ++ ++ if (header && user_service->is_vchi) { ++ spin_lock(&msg_queue_spinlock); ++ while (user_service->msg_insert == ++ (user_service->msg_remove + MSG_QUEUE_SIZE)) { ++ spin_unlock(&msg_queue_spinlock); ++ DEBUG_TRACE(SERVICE_CALLBACK_LINE); ++ DEBUG_COUNT(MSG_QUEUE_FULL_COUNT); ++ vchiq_log_trace(vchiq_arm_log_level, ++ "service_callback - msg queue full"); ++ /* If there is no MESSAGE_AVAILABLE in the completion ++ ** queue, add one ++ */ ++ if ((user_service->message_available_pos - ++ instance->completion_remove) < 0) { ++ VCHIQ_STATUS_T status; ++ vchiq_log_info(vchiq_arm_log_level, ++ "Inserting extra MESSAGE_AVAILABLE"); ++ DEBUG_TRACE(SERVICE_CALLBACK_LINE); ++ status = add_completion(instance, reason, ++ NULL, user_service, bulk_userdata); ++ if (status != VCHIQ_SUCCESS) { ++ DEBUG_TRACE(SERVICE_CALLBACK_LINE); ++ return status; ++ } ++ } ++ ++ DEBUG_TRACE(SERVICE_CALLBACK_LINE); ++ if (down_interruptible(&user_service->remove_event) ++ != 0) { ++ vchiq_log_info(vchiq_arm_log_level, ++ "service_callback interrupted"); ++ DEBUG_TRACE(SERVICE_CALLBACK_LINE); ++ return VCHIQ_RETRY; ++ } else if (instance->closing) { ++ vchiq_log_info(vchiq_arm_log_level, ++ "service_callback closing"); ++ DEBUG_TRACE(SERVICE_CALLBACK_LINE); ++ return VCHIQ_ERROR; ++ } ++ DEBUG_TRACE(SERVICE_CALLBACK_LINE); ++ spin_lock(&msg_queue_spinlock); ++ } ++ ++ user_service->msg_queue[user_service->msg_insert & ++ (MSG_QUEUE_SIZE - 1)] = header; ++ user_service->msg_insert++; ++ spin_unlock(&msg_queue_spinlock); ++ ++ up(&user_service->insert_event); ++ ++ /* If there is a thread waiting in DEQUEUE_MESSAGE, or if ++ ** there is a MESSAGE_AVAILABLE in the completion queue then ++ ** bypass the completion queue. ++ */ ++ if (((user_service->message_available_pos - ++ instance->completion_remove) >= 0) || ++ user_service->dequeue_pending) { ++ DEBUG_TRACE(SERVICE_CALLBACK_LINE); ++ user_service->dequeue_pending = 0; ++ return VCHIQ_SUCCESS; ++ } ++ ++ header = NULL; ++ } ++ DEBUG_TRACE(SERVICE_CALLBACK_LINE); + +- return add_completion(instance, reason, header, service, bulk_userdata); ++ return add_completion(instance, reason, header, user_service, ++ bulk_userdata); + } + + /**************************************************************************** +@@ -333,603 +351,649 @@ + static long + vchiq_ioctl(struct file *file, unsigned int cmd, unsigned long arg) + { +- VCHIQ_INSTANCE_T instance = file->private_data; +- VCHIQ_STATUS_T status = VCHIQ_SUCCESS; +- long ret = 0; +- int i, rc; +- DEBUG_INITIALISE(g_state.local) +- +- vcos_log_trace("vchiq_ioctl - instance %x, cmd %s, arg %lx", +- (unsigned int)instance, +- ((_IOC_TYPE(cmd) == VCHIQ_IOC_MAGIC) && (_IOC_NR(cmd) <= VCHIQ_IOC_MAX)) ? +- ioctl_names[_IOC_NR(cmd)] : "", arg); +- +- switch (cmd) { +- case VCHIQ_IOC_SHUTDOWN: +- if (!instance->connected) +- break; +- +- /* Remove all services */ +- for (i = 0; i < MAX_SERVICES; i++) { +- USER_SERVICE_T *service = &instance->services[i]; +- if (service->service != NULL) { +- status = vchiq_remove_service(&service->service->base); +- if (status != VCHIQ_SUCCESS) +- break; +- service->service = NULL; +- } +- } +- +- if (status == VCHIQ_SUCCESS) { +- /* Wake the completion thread and ask it to exit */ +- instance->closing = 1; +- vcos_event_signal(&instance->insert_event); +- } +- +- break; +- +- case VCHIQ_IOC_CONNECT: +- if (instance->connected) { +- ret = -EINVAL; +- break; +- } +- if ((rc=vcos_mutex_lock(&instance->state->mutex)) != VCOS_SUCCESS) { +- vcos_log_error("vchiq: connect: could not lock mutex for state %d: %d", +- instance->state->id, rc); +- ret = -EINTR; +- break; +- } +- status = vchiq_connect_internal(instance->state, instance); +- vcos_mutex_unlock(&instance->state->mutex); +- +- if (status == VCHIQ_SUCCESS) +- instance->connected = 1; +- else +- vcos_log_error("vchiq: could not connect: %d", status); +- break; +- +- case VCHIQ_IOC_CREATE_SERVICE: +- { +- VCHIQ_CREATE_SERVICE_T args; +- VCHIQ_SERVICE_T *service = NULL; +- USER_SERVICE_T *user_service = NULL; +- void *userdata; +- int srvstate; +- +- if (copy_from_user +- (&args, (const void __user *)arg, +- sizeof(args)) != 0) { +- ret = -EFAULT; +- break; +- } +- +- for (i = 0; i < MAX_SERVICES; i++) { +- if (instance->services[i].service == NULL) { +- user_service = &instance->services[i]; +- break; +- } +- } +- +- if (!user_service) { +- ret = -EMFILE; +- break; +- } +- +- if (args.is_open) { +- if (instance->connected) +- srvstate = VCHIQ_SRVSTATE_OPENING; +- else { +- ret = -ENOTCONN; +- break; +- } +- } else { +- srvstate = +- instance->connected ? +- VCHIQ_SRVSTATE_LISTENING : +- VCHIQ_SRVSTATE_HIDDEN; +- } +- +- vcos_mutex_lock(&instance->state->mutex); +- +- userdata = args.params.userdata; +- args.params.callback = service_callback; +- args.params.userdata = user_service; +- service = +- vchiq_add_service_internal(instance->state, +- &args.params, srvstate, +- instance); +- +- vcos_mutex_unlock(&instance->state->mutex); +- +- if (service != NULL) { +- user_service->service = service; +- user_service->userdata = userdata; +- user_service->instance = instance; +- user_service->handle = i; +- user_service->is_vchi = args.is_vchi; +- user_service->dequeue_pending = 0; +- user_service->message_available_pos = instance->completion_remove - 1; +- user_service->msg_insert = 0; +- user_service->msg_remove = 0; +- vcos_event_create(&user_service->insert_event, "insert_event"); +- vcos_event_create(&user_service->remove_event, "remove_event"); +- +- if (args.is_open) { +- status = +- vchiq_open_service_internal +- (service, instance->pid); +- if (status != VCHIQ_SUCCESS) { +- vchiq_remove_service +- (&service->base); +- ret = +- (status == +- VCHIQ_RETRY) ? -EINTR : +- -EIO; +- user_service->service = NULL; +- user_service->instance = NULL; +- vcos_event_delete(&user_service->insert_event); +- vcos_event_delete(&user_service->remove_event); +- break; +- } +- } +- +- if (copy_to_user((void __user *) +- &(((VCHIQ_CREATE_SERVICE_T __user +- *) arg)->handle), +- (const void *)&user_service-> +- handle, +- sizeof(user_service-> +- handle)) != 0) +- ret = -EFAULT; +- } else { +- ret = -EEXIST; +- } +- } +- break; +- +- case VCHIQ_IOC_CLOSE_SERVICE: +- { +- USER_SERVICE_T *user_service; +- int handle = (int)arg; +- +- user_service = find_service_by_handle(instance, handle); +- if (user_service != NULL) +- { +- int is_server = (user_service->service->public_fourcc != VCHIQ_FOURCC_INVALID); +- +- status = +- vchiq_close_service(&user_service->service->base); +- if ((status == VCHIQ_SUCCESS) && !is_server) +- { +- vcos_event_delete(&user_service->insert_event); +- vcos_event_delete(&user_service->remove_event); +- user_service->service = NULL; +- } +- } else +- ret = -EINVAL; +- } +- break; +- +- case VCHIQ_IOC_REMOVE_SERVICE: +- { +- USER_SERVICE_T *user_service; +- int handle = (int)arg; +- +- user_service = find_service_by_handle(instance, handle); +- if (user_service != NULL) +- { +- status = +- vchiq_remove_service(&user_service->service->base); +- if (status == VCHIQ_SUCCESS) +- { +- vcos_event_delete(&user_service->insert_event); +- vcos_event_delete(&user_service->remove_event); +- user_service->service = NULL; +- } +- } else +- ret = -EINVAL; +- } +- break; +- +- case VCHIQ_IOC_USE_SERVICE: +- case VCHIQ_IOC_RELEASE_SERVICE: +- { +- USER_SERVICE_T *user_service; +- int handle = (int)arg; +- +- user_service = find_service_by_handle(instance, handle); +- if (user_service != NULL) +- { +- status = (cmd == VCHIQ_IOC_USE_SERVICE) ? vchiq_use_service(&user_service->service->base) : vchiq_release_service(&user_service->service->base); +- if (status != VCHIQ_SUCCESS) +- { +- ret = -EINVAL; /* ??? */ +- } +- } +- } +- break; +- +- case VCHIQ_IOC_QUEUE_MESSAGE: +- { +- VCHIQ_QUEUE_MESSAGE_T args; +- USER_SERVICE_T *user_service; +- +- if (copy_from_user +- (&args, (const void __user *)arg, +- sizeof(args)) != 0) { +- ret = -EFAULT; +- break; +- } +- user_service = find_service_by_handle(instance, args.handle); +- if ((user_service != NULL) && (args.count <= MAX_ELEMENTS)) +- { +- /* Copy elements into kernel space */ +- VCHIQ_ELEMENT_T elements[MAX_ELEMENTS]; +- if (copy_from_user +- (elements, args.elements, +- args.count * sizeof(VCHIQ_ELEMENT_T)) == 0) +- status = +- vchiq_queue_message +- (&user_service->service->base, +- elements, args.count); +- else +- ret = -EFAULT; +- } else { +- ret = -EINVAL; +- } +- } +- break; +- +- case VCHIQ_IOC_QUEUE_BULK_TRANSMIT: +- case VCHIQ_IOC_QUEUE_BULK_RECEIVE: +- { +- VCHIQ_QUEUE_BULK_TRANSFER_T args; +- USER_SERVICE_T *user_service; +- VCHIQ_BULK_DIR_T dir = +- (cmd == VCHIQ_IOC_QUEUE_BULK_TRANSMIT) ? +- VCHIQ_BULK_TRANSMIT : VCHIQ_BULK_RECEIVE; +- +- if (copy_from_user +- (&args, (const void __user *)arg, +- sizeof(args)) != 0) { +- ret = -EFAULT; +- break; +- } +- user_service = find_service_by_handle(instance, args.handle); +- if (user_service != NULL) +- { +- status = +- vchiq_bulk_transfer +- ((VCHIQ_SERVICE_T *)user_service->service, +- VCHI_MEM_HANDLE_INVALID, +- args.data, args.size, +- args.userdata, args.mode, +- dir); +- } else { +- ret = -EINVAL; +- } +- } +- break; +- +- case VCHIQ_IOC_AWAIT_COMPLETION: +- { +- VCHIQ_AWAIT_COMPLETION_T args; +- +- DEBUG_TRACE(AWAIT_COMPLETION_LINE); +- if (!instance->connected) { +- ret = -ENOTCONN; +- break; +- } +- +- if (copy_from_user +- (&args, (const void __user *)arg, +- sizeof(args)) != 0) { +- ret = -EFAULT; +- break; +- } +- DEBUG_TRACE(AWAIT_COMPLETION_LINE); +- while ((instance->completion_remove == +- instance->completion_insert) +- && !instance->closing) { +- DEBUG_TRACE(AWAIT_COMPLETION_LINE); +- if (vcos_event_wait(&instance->insert_event) != +- VCOS_SUCCESS) { +- DEBUG_TRACE(AWAIT_COMPLETION_LINE); +- vcos_log_info +- ("AWAIT_COMPLETION interrupted"); +- ret = -EINTR; +- break; +- } +- } +- DEBUG_TRACE(AWAIT_COMPLETION_LINE); +- +- /* A read memory barrier is needed to stop prefetch of a stale +- completion record */ +- vcos_rmb(); +- +- if (ret == 0) { +- int msgbufcount = args.msgbufcount; +- for (ret = 0; ret < args.count; ret++) { +- VCHIQ_COMPLETION_DATA_T *completion; +- USER_SERVICE_T *service; +- VCHIQ_HEADER_T *header; +- if (instance->completion_remove == +- instance->completion_insert) +- break; +- completion = +- &instance-> +- completions +- [instance->completion_remove & +- (MAX_COMPLETIONS - 1)]; +- +- service = (USER_SERVICE_T *)completion->service_userdata; +- completion->service_userdata = service->userdata; +- +- header = completion->header; +- if (header) +- { +- void __user *msgbuf; +- int msglen; +- +- msglen = header->size + sizeof(VCHIQ_HEADER_T); +- /* This must be a VCHIQ-style service */ +- if (args.msgbufsize < msglen) +- { +- vcos_log_error("header %x: msgbufsize %x < msglen %x", +- (unsigned int)header, args.msgbufsize, msglen); +- vcos_assert(0); +- if (ret == 0) +- ret = -EMSGSIZE; +- break; +- } +- if (msgbufcount <= 0) +- { +- /* Stall here for lack of a buffer for the message */ +- break; +- } +- /* Get the pointer from user space */ +- msgbufcount--; +- if (copy_from_user(&msgbuf, +- (const void __user *)&args.msgbufs[msgbufcount], +- sizeof(msgbuf)) != 0) +- { +- if (ret == 0) +- ret = -EFAULT; +- break; +- } +- +- /* Copy the message to user space */ +- if (copy_to_user(msgbuf, header, msglen) != 0) +- { +- if (ret == 0) +- ret = -EFAULT; +- break; +- } +- +- /* Now it has been copied, the message can be released. */ +- vchiq_release_message(&service->service->base, header); +- +- /* The completion must point to the msgbuf */ +- completion->header = msgbuf; +- } +- +- if (copy_to_user +- ((void __user *)((size_t) args.buf + +- ret * +- sizeof +- (VCHIQ_COMPLETION_DATA_T)), +- completion, +- sizeof(VCHIQ_COMPLETION_DATA_T)) != +- 0) { +- if (ret == 0) +- ret = -EFAULT; +- break; +- } +- instance->completion_remove++; +- } +- +- if (msgbufcount != args.msgbufcount) +- { +- if (copy_to_user((void __user *) +- &((VCHIQ_AWAIT_COMPLETION_T *)arg)->msgbufcount, +- &msgbufcount, sizeof(msgbufcount)) != 0) +- { +- ret = -EFAULT; +- break; +- } +- } +- } +- +- if (ret != 0) +- vcos_event_signal(&instance->remove_event); +- DEBUG_TRACE(AWAIT_COMPLETION_LINE); +- } +- break; +- +- case VCHIQ_IOC_DEQUEUE_MESSAGE: +- { +- VCHIQ_DEQUEUE_MESSAGE_T args; +- USER_SERVICE_T *user_service; +- VCHIQ_HEADER_T *header; +- +- DEBUG_TRACE(DEQUEUE_MESSAGE_LINE); +- if (copy_from_user +- (&args, (const void __user *)arg, +- sizeof(args)) != 0) { +- ret = -EFAULT; +- break; +- } +- user_service = &instance->services[args.handle]; +- if ((args.handle < 0) || (args.handle >= MAX_SERVICES) || +- (user_service->service == NULL) || +- (user_service->is_vchi == 0)) { +- ret = -EINVAL; +- break; +- } +- if (user_service->msg_remove == user_service->msg_insert) +- { +- if (!args.blocking) +- { +- DEBUG_TRACE(DEQUEUE_MESSAGE_LINE); +- ret = -EWOULDBLOCK; +- break; +- } +- user_service->dequeue_pending = 1; +- do { +- DEBUG_TRACE(DEQUEUE_MESSAGE_LINE); +- if (vcos_event_wait(&user_service->insert_event) != +- VCOS_SUCCESS) { +- vcos_log_info("DEQUEUE_MESSAGE interrupted"); +- ret = -EINTR; +- break; +- } +- } +- while (user_service->msg_remove == user_service->msg_insert); +- } +- +- /* A read memory barrier is needed to stop prefetch of a stale +- header value */ +- vcos_rmb(); +- +- header = user_service->msg_queue[user_service->msg_remove & +- (MSG_QUEUE_SIZE - 1)]; +- if (header == NULL) +- ret = -ENOTCONN; +- else if (header->size <= args.bufsize) +- { +- /* Copy to user space if msgbuf is not NULL */ +- if ((args.buf == NULL) || +- (copy_to_user((void __user *)args.buf, header->data, +- header->size) == 0)) +- { +- ret = header->size; +- vchiq_release_message(&user_service->service->base, +- header); +- user_service->msg_remove++; +- vcos_event_signal(&user_service->remove_event); +- } +- else +- ret = -EFAULT; +- } +- else +- { +- vcos_log_error("header %x: bufsize %x < size %x", +- (unsigned int)header, args.bufsize, header->size); +- vcos_assert(0); +- ret = -EMSGSIZE; +- } +- DEBUG_TRACE(DEQUEUE_MESSAGE_LINE); +- } +- break; +- +- case VCHIQ_IOC_GET_CLIENT_ID: +- { +- USER_SERVICE_T *user_service; +- int handle = (int)arg; +- +- user_service = find_service_by_handle(instance, handle); +- if (user_service != NULL) +- ret = vchiq_get_client_id(&user_service->service->base); +- else +- ret = 0; +- } +- break; +- +- case VCHIQ_IOC_GET_CONFIG: +- { +- VCHIQ_GET_CONFIG_T args; +- VCHIQ_CONFIG_T config; +- +- if (copy_from_user +- (&args, (const void __user *)arg, +- sizeof(args)) != 0) { +- ret = -EFAULT; +- break; +- } +- if (args.config_size > sizeof(config)) +- { +- ret = -EINVAL; +- break; +- } +- status = vchiq_get_config(instance, args.config_size, &config); +- if (status == VCHIQ_SUCCESS) +- { +- if (copy_to_user((void __user *)args.pconfig, +- &config, args.config_size) != 0) +- { +- ret = -EFAULT; +- break; +- } +- } +- } +- break; +- +- case VCHIQ_IOC_SET_SERVICE_OPTION: +- { +- VCHIQ_SET_SERVICE_OPTION_T args; +- USER_SERVICE_T *user_service; +- +- if (copy_from_user( +- &args, (const void __user *)arg, +- sizeof(args)) != 0) +- { +- ret = -EFAULT; +- break; +- } +- +- user_service = find_service_by_handle(instance, args.handle); +- if (user_service != NULL) +- { +- status = vchiq_set_service_option( +- &user_service->service->base, +- args.option, args.value); +- } +- else +- { +- ret = -EINVAL; +- } +- } +- break; +- +- case VCHIQ_IOC_DUMP_PHYS_MEM: +- { +- VCHIQ_DUMP_MEM_T args; +- +- if (copy_from_user +- (&args, (const void __user *)arg, +- sizeof(args)) != 0) { +- ret = -EFAULT; +- break; +- } +- dump_phys_mem( args.virt_addr, args.num_bytes ); +- } +- break; +- +- +- default: +- ret = -ENOTTY; +- break; +- } +- +- if (ret == 0) { +- if (status == VCHIQ_ERROR) +- ret = -EIO; +- else if (status == VCHIQ_RETRY) +- ret = -EINTR; +- } +- +- if ((ret < 0) && (ret != -EINTR) && (ret != -EWOULDBLOCK)) +- vcos_log_warn(" ioctl instance %lx, cmd %s -> status %d, %ld", +- (unsigned long)instance, +- (_IOC_NR(cmd) <= VCHIQ_IOC_MAX) ? ioctl_names[_IOC_NR(cmd)] : +- "", status, ret); +- else +- vcos_log_trace(" ioctl instance %lx, cmd %s -> status %d, %ld", +- (unsigned long)instance, +- (_IOC_NR(cmd) <= VCHIQ_IOC_MAX) ? ioctl_names[_IOC_NR(cmd)] : +- "", status, ret); ++ VCHIQ_INSTANCE_T instance = file->private_data; ++ VCHIQ_STATUS_T status = VCHIQ_SUCCESS; ++ VCHIQ_SERVICE_T *service = NULL; ++ long ret = 0; ++ int i, rc; ++ DEBUG_INITIALISE(g_state.local) ++ ++ vchiq_log_trace(vchiq_arm_log_level, ++ "vchiq_ioctl - instance %x, cmd %s, arg %lx", ++ (unsigned int)instance, ++ ((_IOC_TYPE(cmd) == VCHIQ_IOC_MAGIC) && ++ (_IOC_NR(cmd) <= VCHIQ_IOC_MAX)) ? ++ ioctl_names[_IOC_NR(cmd)] : "", arg); ++ ++ switch (cmd) { ++ case VCHIQ_IOC_SHUTDOWN: ++ if (!instance->connected) ++ break; ++ ++ /* Remove all services */ ++ i = 0; ++ while ((service = next_service_by_instance(instance->state, ++ instance, &i)) != NULL) { ++ status = vchiq_remove_service(service->handle); ++ unlock_service(service); ++ if (status != VCHIQ_SUCCESS) ++ break; ++ } ++ service = NULL; ++ ++ if (status == VCHIQ_SUCCESS) { ++ /* Wake the completion thread and ask it to exit */ ++ instance->closing = 1; ++ up(&instance->insert_event); ++ } ++ ++ break; ++ ++ case VCHIQ_IOC_CONNECT: ++ if (instance->connected) { ++ ret = -EINVAL; ++ break; ++ } ++ rc = mutex_lock_interruptible(&instance->state->mutex); ++ if (rc != 0) { ++ vchiq_log_error(vchiq_arm_log_level, ++ "vchiq: connect: could not lock mutex for " ++ "state %d: %d", ++ instance->state->id, rc); ++ ret = -EINTR; ++ break; ++ } ++ status = vchiq_connect_internal(instance->state, instance); ++ mutex_unlock(&instance->state->mutex); ++ ++ if (status == VCHIQ_SUCCESS) ++ instance->connected = 1; ++ else ++ vchiq_log_error(vchiq_arm_log_level, ++ "vchiq: could not connect: %d", status); ++ break; ++ ++ case VCHIQ_IOC_CREATE_SERVICE: { ++ VCHIQ_CREATE_SERVICE_T args; ++ USER_SERVICE_T *user_service = NULL; ++ void *userdata; ++ int srvstate; ++ ++ if (copy_from_user ++ (&args, (const void __user *)arg, ++ sizeof(args)) != 0) { ++ ret = -EFAULT; ++ break; ++ } ++ ++ user_service = kmalloc(sizeof(USER_SERVICE_T), GFP_KERNEL); ++ if (!user_service) { ++ ret = -ENOMEM; ++ break; ++ } ++ ++ if (args.is_open) { ++ if (!instance->connected) { ++ ret = -ENOTCONN; ++ break; ++ } ++ srvstate = VCHIQ_SRVSTATE_OPENING; ++ } else { ++ srvstate = ++ instance->connected ? ++ VCHIQ_SRVSTATE_LISTENING : ++ VCHIQ_SRVSTATE_HIDDEN; ++ } ++ ++ userdata = args.params.userdata; ++ args.params.callback = service_callback; ++ args.params.userdata = user_service; ++ service = vchiq_add_service_internal( ++ instance->state, ++ &args.params, srvstate, ++ instance); ++ ++ if (service != NULL) { ++ user_service->service = service; ++ user_service->userdata = userdata; ++ user_service->instance = instance; ++ user_service->is_vchi = args.is_vchi; ++ user_service->dequeue_pending = 0; ++ user_service->message_available_pos = ++ instance->completion_remove - 1; ++ user_service->msg_insert = 0; ++ user_service->msg_remove = 0; ++ sema_init(&user_service->insert_event, 0); ++ sema_init(&user_service->remove_event, 0); ++ ++ if (args.is_open) { ++ status = vchiq_open_service_internal ++ (service, instance->pid); ++ if (status != VCHIQ_SUCCESS) { ++ vchiq_remove_service(service->handle); ++ service = NULL; ++ ret = (status == VCHIQ_RETRY) ? ++ -EINTR : -EIO; ++ user_service->service = NULL; ++ user_service->instance = NULL; ++ break; ++ } ++ } ++ ++ if (copy_to_user((void __user *) ++ &(((VCHIQ_CREATE_SERVICE_T __user *) ++ arg)->handle), ++ (const void *)&service->handle, ++ sizeof(service->handle)) != 0) { ++ ret = -EFAULT; ++ vchiq_remove_service(service->handle); ++ kfree(user_service); ++ } ++ ++ service = NULL; ++ } else { ++ ret = -EEXIST; ++ kfree(user_service); ++ } ++ } break; ++ ++ case VCHIQ_IOC_CLOSE_SERVICE: { ++ VCHIQ_SERVICE_HANDLE_T handle = (VCHIQ_SERVICE_HANDLE_T)arg; ++ ++ service = find_service_for_instance(instance, handle); ++ if (service != NULL) ++ status = vchiq_close_service(service->handle); ++ else ++ ret = -EINVAL; ++ } break; ++ ++ case VCHIQ_IOC_REMOVE_SERVICE: { ++ VCHIQ_SERVICE_HANDLE_T handle = (VCHIQ_SERVICE_HANDLE_T)arg; ++ ++ service = find_service_for_instance(instance, handle); ++ if (service != NULL) ++ status = vchiq_remove_service(service->handle); ++ else ++ ret = -EINVAL; ++ } break; ++ ++ case VCHIQ_IOC_USE_SERVICE: ++ case VCHIQ_IOC_RELEASE_SERVICE: { ++ VCHIQ_SERVICE_HANDLE_T handle = (VCHIQ_SERVICE_HANDLE_T)arg; ++ ++ service = find_service_for_instance(instance, handle); ++ if (service != NULL) { ++ status = (cmd == VCHIQ_IOC_USE_SERVICE) ? ++ vchiq_use_service_internal(service) : ++ vchiq_release_service_internal(service); ++ if (status != VCHIQ_SUCCESS) { ++ vchiq_log_error(vchiq_susp_log_level, ++ "%s: cmd %s returned error %d for " ++ "service %c%c%c%c:%03d", ++ __func__, ++ (cmd == VCHIQ_IOC_USE_SERVICE) ? ++ "VCHIQ_IOC_USE_SERVICE" : ++ "VCHIQ_IOC_RELEASE_SERVICE", ++ status, ++ VCHIQ_FOURCC_AS_4CHARS( ++ service->base.fourcc), ++ service->client_id); ++ ret = -EINVAL; ++ } ++ } else ++ ret = -EINVAL; ++ } break; ++ ++ case VCHIQ_IOC_QUEUE_MESSAGE: { ++ VCHIQ_QUEUE_MESSAGE_T args; ++ if (copy_from_user ++ (&args, (const void __user *)arg, ++ sizeof(args)) != 0) { ++ ret = -EFAULT; ++ break; ++ } ++ ++ service = find_service_for_instance(instance, args.handle); ++ ++ if ((service != NULL) && (args.count <= MAX_ELEMENTS)) { ++ /* Copy elements into kernel space */ ++ VCHIQ_ELEMENT_T elements[MAX_ELEMENTS]; ++ if (copy_from_user(elements, args.elements, ++ args.count * sizeof(VCHIQ_ELEMENT_T)) == 0) ++ status = vchiq_queue_message ++ (args.handle, ++ elements, args.count); ++ else ++ ret = -EFAULT; ++ } else { ++ ret = -EINVAL; ++ } ++ } break; ++ ++ case VCHIQ_IOC_QUEUE_BULK_TRANSMIT: ++ case VCHIQ_IOC_QUEUE_BULK_RECEIVE: { ++ VCHIQ_QUEUE_BULK_TRANSFER_T args; ++ struct bulk_waiter_node *waiter = NULL; ++ VCHIQ_BULK_DIR_T dir = ++ (cmd == VCHIQ_IOC_QUEUE_BULK_TRANSMIT) ? ++ VCHIQ_BULK_TRANSMIT : VCHIQ_BULK_RECEIVE; ++ ++ if (copy_from_user ++ (&args, (const void __user *)arg, ++ sizeof(args)) != 0) { ++ ret = -EFAULT; ++ break; ++ } ++ ++ service = find_service_for_instance(instance, args.handle); ++ if (!service) { ++ ret = -EINVAL; ++ break; ++ } ++ ++ if (args.mode == VCHIQ_BULK_MODE_BLOCKING) { ++ waiter = kzalloc(sizeof(struct bulk_waiter_node), ++ GFP_KERNEL); ++ if (!waiter) { ++ ret = -ENOMEM; ++ break; ++ } ++ args.userdata = &waiter->bulk_waiter; ++ } else if (args.mode == VCHIQ_BULK_MODE_WAITING) { ++ struct list_head *pos; ++ mutex_lock(&instance->bulk_waiter_list_mutex); ++ list_for_each(pos, &instance->bulk_waiter_list) { ++ if (list_entry(pos, struct bulk_waiter_node, ++ list)->pid == current->pid) { ++ waiter = list_entry(pos, ++ struct bulk_waiter_node, ++ list); ++ list_del(pos); ++ break; ++ } ++ ++ } ++ mutex_unlock(&instance->bulk_waiter_list_mutex); ++ if (!waiter) { ++ vchiq_log_error(vchiq_arm_log_level, ++ "no bulk_waiter found for pid %d", ++ current->pid); ++ ret = -ESRCH; ++ break; ++ } ++ vchiq_log_info(vchiq_arm_log_level, ++ "found bulk_waiter %x for pid %d", ++ (unsigned int)waiter, current->pid); ++ args.userdata = &waiter->bulk_waiter; ++ } ++ status = vchiq_bulk_transfer ++ (args.handle, ++ VCHI_MEM_HANDLE_INVALID, ++ args.data, args.size, ++ args.userdata, args.mode, ++ dir); ++ if (!waiter) ++ break; ++ if ((status != VCHIQ_RETRY) || fatal_signal_pending(current) || ++ !waiter->bulk_waiter.bulk) { ++ if (waiter->bulk_waiter.bulk) { ++ /* Cancel the signal when the transfer ++ ** completes. */ ++ spin_lock(&bulk_waiter_spinlock); ++ waiter->bulk_waiter.bulk->userdata = NULL; ++ spin_unlock(&bulk_waiter_spinlock); ++ } ++ kfree(waiter); ++ } else { ++ const VCHIQ_BULK_MODE_T mode_waiting = ++ VCHIQ_BULK_MODE_WAITING; ++ waiter->pid = current->pid; ++ mutex_lock(&instance->bulk_waiter_list_mutex); ++ list_add(&waiter->list, &instance->bulk_waiter_list); ++ mutex_unlock(&instance->bulk_waiter_list_mutex); ++ vchiq_log_info(vchiq_arm_log_level, ++ "saved bulk_waiter %x for pid %d", ++ (unsigned int)waiter, current->pid); ++ ++ if (copy_to_user((void __user *) ++ &(((VCHIQ_QUEUE_BULK_TRANSFER_T __user *) ++ arg)->mode), ++ (const void *)&mode_waiting, ++ sizeof(mode_waiting)) != 0) ++ ret = -EFAULT; ++ } ++ } break; ++ ++ case VCHIQ_IOC_AWAIT_COMPLETION: { ++ VCHIQ_AWAIT_COMPLETION_T args; ++ ++ DEBUG_TRACE(AWAIT_COMPLETION_LINE); ++ if (!instance->connected) { ++ ret = -ENOTCONN; ++ break; ++ } ++ ++ if (copy_from_user(&args, (const void __user *)arg, ++ sizeof(args)) != 0) { ++ ret = -EFAULT; ++ break; ++ } ++ ++ mutex_lock(&instance->completion_mutex); ++ ++ DEBUG_TRACE(AWAIT_COMPLETION_LINE); ++ while ((instance->completion_remove == ++ instance->completion_insert) ++ && !instance->closing) { ++ int rc; ++ DEBUG_TRACE(AWAIT_COMPLETION_LINE); ++ mutex_unlock(&instance->completion_mutex); ++ rc = down_interruptible(&instance->insert_event); ++ mutex_lock(&instance->completion_mutex); ++ if (rc != 0) { ++ DEBUG_TRACE(AWAIT_COMPLETION_LINE); ++ vchiq_log_info(vchiq_arm_log_level, ++ "AWAIT_COMPLETION interrupted"); ++ ret = -EINTR; ++ break; ++ } ++ } ++ DEBUG_TRACE(AWAIT_COMPLETION_LINE); ++ ++ /* A read memory barrier is needed to stop prefetch of a stale ++ ** completion record ++ */ ++ rmb(); ++ ++ if ((ret == 0) && !instance->closing) { ++ int msgbufcount = args.msgbufcount; ++ for (ret = 0; ret < args.count; ret++) { ++ VCHIQ_COMPLETION_DATA_T *completion; ++ VCHIQ_SERVICE_T *service; ++ USER_SERVICE_T *user_service; ++ VCHIQ_HEADER_T *header; ++ if (instance->completion_remove == ++ instance->completion_insert) ++ break; ++ completion = &instance->completions[ ++ instance->completion_remove & ++ (MAX_COMPLETIONS - 1)]; ++ ++ service = completion->service_userdata; ++ user_service = service->base.userdata; ++ completion->service_userdata = ++ user_service->userdata; ++ ++ header = completion->header; ++ if (header) { ++ void __user *msgbuf; ++ int msglen; ++ ++ msglen = header->size + ++ sizeof(VCHIQ_HEADER_T); ++ /* This must be a VCHIQ-style service */ ++ if (args.msgbufsize < msglen) { ++ vchiq_log_error( ++ vchiq_arm_log_level, ++ "header %x: msgbufsize" ++ " %x < msglen %x", ++ (unsigned int)header, ++ args.msgbufsize, ++ msglen); ++ WARN(1, "invalid message " ++ "size\n"); ++ if (ret == 0) ++ ret = -EMSGSIZE; ++ break; ++ } ++ if (msgbufcount <= 0) ++ /* Stall here for lack of a ++ ** buffer for the message. */ ++ break; ++ /* Get the pointer from user space */ ++ msgbufcount--; ++ if (copy_from_user(&msgbuf, ++ (const void __user *) ++ &args.msgbufs[msgbufcount], ++ sizeof(msgbuf)) != 0) { ++ if (ret == 0) ++ ret = -EFAULT; ++ break; ++ } ++ ++ /* Copy the message to user space */ ++ if (copy_to_user(msgbuf, header, ++ msglen) != 0) { ++ if (ret == 0) ++ ret = -EFAULT; ++ break; ++ } ++ ++ /* Now it has been copied, the message ++ ** can be released. */ ++ vchiq_release_message(service->handle, ++ header); ++ ++ /* The completion must point to the ++ ** msgbuf. */ ++ completion->header = msgbuf; ++ } ++ ++ if (completion->reason == ++ VCHIQ_SERVICE_CLOSED) { ++ unlock_service(service); ++ kfree(user_service); ++ } ++ ++ if (copy_to_user((void __user *)( ++ (size_t)args.buf + ++ ret * sizeof(VCHIQ_COMPLETION_DATA_T)), ++ completion, ++ sizeof(VCHIQ_COMPLETION_DATA_T)) != 0) { ++ if (ret == 0) ++ ret = -EFAULT; ++ break; ++ } ++ ++ instance->completion_remove++; ++ } ++ ++ if (msgbufcount != args.msgbufcount) { ++ if (copy_to_user((void __user *) ++ &((VCHIQ_AWAIT_COMPLETION_T *)arg)-> ++ msgbufcount, ++ &msgbufcount, ++ sizeof(msgbufcount)) != 0) { ++ ret = -EFAULT; ++ } ++ } ++ } ++ ++ if (ret != 0) ++ up(&instance->remove_event); ++ mutex_unlock(&instance->completion_mutex); ++ DEBUG_TRACE(AWAIT_COMPLETION_LINE); ++ } break; ++ ++ case VCHIQ_IOC_DEQUEUE_MESSAGE: { ++ VCHIQ_DEQUEUE_MESSAGE_T args; ++ USER_SERVICE_T *user_service; ++ VCHIQ_HEADER_T *header; ++ ++ DEBUG_TRACE(DEQUEUE_MESSAGE_LINE); ++ if (copy_from_user ++ (&args, (const void __user *)arg, ++ sizeof(args)) != 0) { ++ ret = -EFAULT; ++ break; ++ } ++ service = find_service_for_instance(instance, args.handle); ++ if (!service) { ++ ret = -EINVAL; ++ break; ++ } ++ user_service = (USER_SERVICE_T *)service->base.userdata; ++ if (user_service->is_vchi == 0) { ++ ret = -EINVAL; ++ break; ++ } ++ ++ spin_lock(&msg_queue_spinlock); ++ if (user_service->msg_remove == user_service->msg_insert) { ++ if (!args.blocking) { ++ spin_unlock(&msg_queue_spinlock); ++ DEBUG_TRACE(DEQUEUE_MESSAGE_LINE); ++ ret = -EWOULDBLOCK; ++ break; ++ } ++ user_service->dequeue_pending = 1; ++ do { ++ spin_unlock(&msg_queue_spinlock); ++ DEBUG_TRACE(DEQUEUE_MESSAGE_LINE); ++ if (down_interruptible( ++ &user_service->insert_event) != 0) { ++ vchiq_log_info(vchiq_arm_log_level, ++ "DEQUEUE_MESSAGE interrupted"); ++ ret = -EINTR; ++ break; ++ } ++ spin_lock(&msg_queue_spinlock); ++ } while (user_service->msg_remove == ++ user_service->msg_insert); ++ ++ if (ret) ++ break; ++ } ++ ++ BUG_ON((int)(user_service->msg_insert - ++ user_service->msg_remove) < 0); ++ ++ header = user_service->msg_queue[user_service->msg_remove & ++ (MSG_QUEUE_SIZE - 1)]; ++ user_service->msg_remove++; ++ spin_unlock(&msg_queue_spinlock); ++ ++ up(&user_service->remove_event); ++ if (header == NULL) ++ ret = -ENOTCONN; ++ else if (header->size <= args.bufsize) { ++ /* Copy to user space if msgbuf is not NULL */ ++ if ((args.buf == NULL) || ++ (copy_to_user((void __user *)args.buf, ++ header->data, ++ header->size) == 0)) { ++ ret = header->size; ++ vchiq_release_message( ++ service->handle, ++ header); ++ } else ++ ret = -EFAULT; ++ } else { ++ vchiq_log_error(vchiq_arm_log_level, ++ "header %x: bufsize %x < size %x", ++ (unsigned int)header, args.bufsize, ++ header->size); ++ WARN(1, "invalid size\n"); ++ ret = -EMSGSIZE; ++ } ++ DEBUG_TRACE(DEQUEUE_MESSAGE_LINE); ++ } break; ++ ++ case VCHIQ_IOC_GET_CLIENT_ID: { ++ VCHIQ_SERVICE_HANDLE_T handle = (VCHIQ_SERVICE_HANDLE_T)arg; ++ ++ ret = vchiq_get_client_id(handle); ++ } break; ++ ++ case VCHIQ_IOC_GET_CONFIG: { ++ VCHIQ_GET_CONFIG_T args; ++ VCHIQ_CONFIG_T config; ++ ++ if (copy_from_user(&args, (const void __user *)arg, ++ sizeof(args)) != 0) { ++ ret = -EFAULT; ++ break; ++ } ++ if (args.config_size > sizeof(config)) { ++ ret = -EINVAL; ++ break; ++ } ++ status = vchiq_get_config(instance, args.config_size, &config); ++ if (status == VCHIQ_SUCCESS) { ++ if (copy_to_user((void __user *)args.pconfig, ++ &config, args.config_size) != 0) { ++ ret = -EFAULT; ++ break; ++ } ++ } ++ } break; ++ ++ case VCHIQ_IOC_SET_SERVICE_OPTION: { ++ VCHIQ_SET_SERVICE_OPTION_T args; ++ ++ if (copy_from_user( ++ &args, (const void __user *)arg, ++ sizeof(args)) != 0) { ++ ret = -EFAULT; ++ break; ++ } ++ ++ service = find_service_for_instance(instance, args.handle); ++ if (!service) { ++ ret = -EINVAL; ++ break; ++ } ++ ++ status = vchiq_set_service_option( ++ args.handle, args.option, args.value); ++ } break; ++ ++ case VCHIQ_IOC_DUMP_PHYS_MEM: { ++ VCHIQ_DUMP_MEM_T args; ++ ++ if (copy_from_user ++ (&args, (const void __user *)arg, ++ sizeof(args)) != 0) { ++ ret = -EFAULT; ++ break; ++ } ++ dump_phys_mem(args.virt_addr, args.num_bytes); ++ } break; ++ ++ default: ++ ret = -ENOTTY; ++ break; ++ } ++ ++ if (service) ++ unlock_service(service); ++ ++ if (ret == 0) { ++ if (status == VCHIQ_ERROR) ++ ret = -EIO; ++ else if (status == VCHIQ_RETRY) ++ ret = -EINTR; ++ } ++ ++ if ((status == VCHIQ_SUCCESS) && (ret < 0) && (ret != -EINTR) && ++ (ret != -EWOULDBLOCK)) ++ vchiq_log_info(vchiq_arm_log_level, ++ " ioctl instance %lx, cmd %s -> status %d, %ld", ++ (unsigned long)instance, ++ (_IOC_NR(cmd) <= VCHIQ_IOC_MAX) ? ++ ioctl_names[_IOC_NR(cmd)] : ++ "", ++ status, ret); ++ else ++ vchiq_log_trace(vchiq_arm_log_level, ++ " ioctl instance %lx, cmd %s -> status %d, %ld", ++ (unsigned long)instance, ++ (_IOC_NR(cmd) <= VCHIQ_IOC_MAX) ? ++ ioctl_names[_IOC_NR(cmd)] : ++ "", ++ status, ret); + +- return ret; ++ return ret; + } + + /**************************************************************************** +@@ -941,39 +1005,49 @@ + static int + vchiq_open(struct inode *inode, struct file *file) + { +- int dev = iminor(inode) & 0x0f; +- vcos_log_info("vchiq_open"); +- switch (dev) { +- case VCHIQ_MINOR: +- { +- VCHIQ_STATE_T *state = vchiq_get_state(); +- VCHIQ_INSTANCE_T instance; +- +- if (!state) +- { +- vcos_log_error( "vchiq has no connection to VideoCore"); +- return -ENOTCONN; +- } +- +- instance = kzalloc(sizeof(*instance), GFP_KERNEL); +- if (!instance) +- return -ENOMEM; +- +- instance->state = state; +- instance->pid = current->tgid; +- vcos_event_create(&instance->insert_event, DEVICE_NAME); +- vcos_event_create(&instance->remove_event, DEVICE_NAME); +- +- file->private_data = instance; +- } +- break; +- +- default: +- vcos_log_error("Unknown minor device: %d", dev); +- return -ENXIO; +- } ++ int dev = iminor(inode) & 0x0f; ++ vchiq_log_info(vchiq_arm_log_level, "vchiq_open"); ++ switch (dev) { ++ case VCHIQ_MINOR: { ++ int ret; ++ VCHIQ_STATE_T *state = vchiq_get_state(); ++ VCHIQ_INSTANCE_T instance; ++ ++ if (!state) { ++ vchiq_log_error(vchiq_arm_log_level, ++ "vchiq has no connection to VideoCore"); ++ return -ENOTCONN; ++ } ++ ++ instance = kzalloc(sizeof(*instance), GFP_KERNEL); ++ if (!instance) ++ return -ENOMEM; ++ ++ instance->state = state; ++ instance->pid = current->tgid; ++ ++ ret = vchiq_proc_add_instance(instance); ++ if (ret != 0) { ++ kfree(instance); ++ return ret; ++ } ++ ++ sema_init(&instance->insert_event, 0); ++ sema_init(&instance->remove_event, 0); ++ mutex_init(&instance->completion_mutex); ++ mutex_init(&instance->bulk_waiter_list_mutex); ++ INIT_LIST_HEAD(&instance->bulk_waiter_list); ++ ++ file->private_data = instance; ++ } break; ++ ++ default: ++ vchiq_log_error(vchiq_arm_log_level, ++ "Unknown minor device: %d", dev); ++ return -ENXIO; ++ } + +- return 0; ++ return 0; + } + + /**************************************************************************** +@@ -985,74 +1059,131 @@ + static int + vchiq_release(struct inode *inode, struct file *file) + { +- int dev = iminor(inode) & 0x0f; +- int ret = 0; +- switch (dev) { +- case VCHIQ_MINOR: +- { +- VCHIQ_INSTANCE_T instance = file->private_data; +- int i; +- +- vcos_log_info("vchiq_release: instance=%lx", +- (unsigned long)instance); +- +- instance->closing = 1; +- +- /* Wake the slot handler if the completion queue is full */ +- vcos_event_signal(&instance->remove_event); +- +- /* Mark all services for termination... */ +- +- for (i = 0; i < MAX_SERVICES; i++) { +- USER_SERVICE_T *user_service = +- &instance->services[i]; +- if (user_service->service != NULL) +- { +- /* Wake the slot handler if the msg queue is full */ +- vcos_event_signal(&user_service->remove_event); +- +- if ((user_service->service->srvstate != VCHIQ_SRVSTATE_CLOSEWAIT) && +- (user_service->service->srvstate != VCHIQ_SRVSTATE_LISTENING)) +- { +- vchiq_terminate_service_internal(user_service->service); +- } +- } +- } +- +- /* ...and wait for them to die */ +- +- for (i = 0; i < MAX_SERVICES; i++) { +- USER_SERVICE_T *user_service = +- &instance->services[i]; +- if (user_service->service != NULL) +- { +- /* Wait in this non-portable fashion because interruptible +- calls will not block in this context. */ +- while ((user_service->service->srvstate != VCHIQ_SRVSTATE_CLOSEWAIT) && +- (user_service->service->srvstate != VCHIQ_SRVSTATE_LISTENING)) +- { +- down(&user_service->service->remove_event); +- } +- +- vchiq_free_service_internal +- (user_service->service); +- } +- } +- +- vcos_event_delete(&instance->insert_event); +- vcos_event_delete(&instance->remove_event); +- +- kfree(instance); +- file->private_data = NULL; +- } +- break; +- +- default: +- vcos_log_error("Unknown minor device: %d", dev); +- ret = -ENXIO; +- } ++ int dev = iminor(inode) & 0x0f; ++ int ret = 0; ++ switch (dev) { ++ case VCHIQ_MINOR: { ++ VCHIQ_INSTANCE_T instance = file->private_data; ++ VCHIQ_STATE_T *state = vchiq_get_state(); ++ VCHIQ_SERVICE_T *service; ++ int i; ++ ++ vchiq_log_info(vchiq_arm_log_level, ++ "vchiq_release: instance=%lx", ++ (unsigned long)instance); ++ ++ if (state) { ++ /* Ensure videocore is awake to allow termination. */ ++ vchiq_use_internal(instance->state, NULL, ++ USE_TYPE_VCHIQ); ++ } ++ ++ mutex_lock(&instance->completion_mutex); ++ ++ /* Wake the completion thread and ask it to exit */ ++ instance->closing = 1; ++ up(&instance->insert_event); ++ ++ mutex_unlock(&instance->completion_mutex); ++ ++ /* Wake the slot handler if the completion queue is full. */ ++ up(&instance->remove_event); ++ ++ /* Mark all services for termination... */ ++ i = 0; ++ while ((service = next_service_by_instance(state, instance, ++ &i)) != NULL) { ++ USER_SERVICE_T *user_service = service->base.userdata; ++ ++ /* Wake the slot handler if the msg queue is full. */ ++ up(&user_service->remove_event); ++ ++ vchiq_terminate_service_internal(service); ++ unlock_service(service); ++ } ++ ++ /* ...and wait for them to die */ ++ i = 0; ++ while ((service = next_service_by_instance(state, instance, &i)) ++ != NULL) { ++ USER_SERVICE_T *user_service = service->base.userdata; ++ ++ down(&service->remove_event); ++ ++ BUG_ON(service->srvstate != VCHIQ_SRVSTATE_FREE); ++ ++ spin_lock(&msg_queue_spinlock); ++ ++ while (user_service->msg_remove != ++ user_service->msg_insert) { ++ VCHIQ_HEADER_T *header = user_service-> ++ msg_queue[user_service->msg_remove & ++ (MSG_QUEUE_SIZE - 1)]; ++ user_service->msg_remove++; ++ spin_unlock(&msg_queue_spinlock); ++ ++ if (header) ++ vchiq_release_message( ++ service->handle, ++ header); ++ spin_lock(&msg_queue_spinlock); ++ } ++ ++ spin_unlock(&msg_queue_spinlock); ++ ++ unlock_service(service); ++ kfree(user_service); ++ } ++ ++ /* Release any closed services */ ++ while (instance->completion_remove != ++ instance->completion_insert) { ++ VCHIQ_COMPLETION_DATA_T *completion; ++ VCHIQ_SERVICE_T *service; ++ completion = &instance->completions[ ++ instance->completion_remove & ++ (MAX_COMPLETIONS - 1)]; ++ service = completion->service_userdata; ++ if (completion->reason == VCHIQ_SERVICE_CLOSED) ++ unlock_service(service); ++ instance->completion_remove++; ++ } ++ ++ if (state) { ++ /* Release the PEER service count. */ ++ vchiq_release_internal(instance->state, NULL); ++ } ++ ++ { ++ struct list_head *pos, *next; ++ list_for_each_safe(pos, next, ++ &instance->bulk_waiter_list) { ++ struct bulk_waiter_node *waiter; ++ waiter = list_entry(pos, ++ struct bulk_waiter_node, ++ list); ++ list_del(pos); ++ vchiq_log_info(vchiq_arm_log_level, ++ "bulk_waiter - cleaned up %x " ++ "for pid %d", ++ (unsigned int)waiter, waiter->pid); ++ kfree(waiter); ++ } ++ } ++ ++ vchiq_proc_remove_instance(instance); ++ ++ kfree(instance); ++ file->private_data = NULL; ++ } break; ++ ++ default: ++ vchiq_log_error(vchiq_arm_log_level, ++ "Unknown minor device: %d", dev); ++ ret = -ENXIO; ++ } + +- return ret; ++ return ret; + } + + /**************************************************************************** +@@ -1064,40 +1195,37 @@ + void + vchiq_dump(void *dump_context, const char *str, int len) + { +- DUMP_CONTEXT_T *context = (DUMP_CONTEXT_T *)dump_context; ++ DUMP_CONTEXT_T *context = (DUMP_CONTEXT_T *)dump_context; + +- if ((context->actual >= 0) && (context->actual < context->space)) +- { +- int copy_bytes; +- if (context->offset > 0) +- { +- int skip_bytes = vcos_min(len, context->offset); +- str += skip_bytes; +- len -= skip_bytes; +- context->offset -= skip_bytes; +- if (context->offset > 0) +- return; +- } +- copy_bytes = vcos_min(len, context->space - context->actual); +- if (copy_bytes == 0) +- return; +- if (copy_to_user(context->buf + context->actual, str, copy_bytes)) +- context->actual = -EFAULT; +- context->actual += copy_bytes; +- len -= copy_bytes; +- +- /* If tne terminating NUL is included in the length, then it marks +- * the end of a line and should be replaced with a carriage return. +- */ +- if ((len == 0) && (str[copy_bytes - 1] == '\0')) +- { +- char cr = '\n'; +- if (copy_to_user(context->buf + context->actual - 1, &cr, 1)) +- { +- context->actual = -EFAULT; +- } +- } +- } ++ if ((context->actual >= 0) && (context->actual < context->space)) { ++ int copy_bytes; ++ if (context->offset > 0) { ++ int skip_bytes = min(len, (int)context->offset); ++ str += skip_bytes; ++ len -= skip_bytes; ++ context->offset -= skip_bytes; ++ if (context->offset > 0) ++ return; ++ } ++ copy_bytes = min(len, (int)(context->space - context->actual)); ++ if (copy_bytes == 0) ++ return; ++ if (copy_to_user(context->buf + context->actual, str, ++ copy_bytes)) ++ context->actual = -EFAULT; ++ context->actual += copy_bytes; ++ len -= copy_bytes; ++ ++ /* If tne terminating NUL is included in the length, then it ++ ** marks the end of a line and should be replaced with a ++ ** carriage return. */ ++ if ((len == 0) && (str[copy_bytes - 1] == '\0')) { ++ char cr = '\n'; ++ if (copy_to_user(context->buf + context->actual - 1, ++ &cr, 1)) ++ context->actual = -EFAULT; ++ } ++ } + } + + /**************************************************************************** +@@ -1109,49 +1237,48 @@ + void + vchiq_dump_platform_instances(void *dump_context) + { +- VCHIQ_STATE_T *state = vchiq_get_state(); +- char buf[80]; +- int len; +- int i; +- +- /* There is no list of instances, so instead scan all services, +- marking those that have been dumped. */ +- +- for (i = 0; i < state->unused_service; i++) +- { +- VCHIQ_SERVICE_T *service = state->services[i]; +- VCHIQ_INSTANCE_T instance; +- +- if (service +- && ((instance = service->instance) != NULL) +- && (service->base.callback == service_callback)) +- instance->mark = 0; +- } +- +- for (i = 0; i < state->unused_service; i++) +- { +- VCHIQ_SERVICE_T *service = state->services[i]; +- VCHIQ_INSTANCE_T instance; +- +- if (service +- && ((instance = service->instance) != NULL) +- && (service->base.callback == service_callback)) +- { +- if (!instance->mark) +- { +- len = vcos_snprintf(buf, sizeof(buf), +- "Instance %x: pid %d,%s completions %d/%d", +- (unsigned int)instance, instance->pid, +- instance->connected ? " connected," : "", +- instance->completion_insert - instance->completion_remove, +- MAX_COMPLETIONS); +- +- vchiq_dump(dump_context, buf, len + 1); +- +- instance->mark = 1; +- } +- } +- } ++ VCHIQ_STATE_T *state = vchiq_get_state(); ++ char buf[80]; ++ int len; ++ int i; ++ ++ /* There is no list of instances, so instead scan all services, ++ marking those that have been dumped. */ ++ ++ for (i = 0; i < state->unused_service; i++) { ++ VCHIQ_SERVICE_T *service = state->services[i]; ++ VCHIQ_INSTANCE_T instance; ++ ++ if (service && (service->base.callback == service_callback)) { ++ instance = service->instance; ++ if (instance) ++ instance->mark = 0; ++ } ++ } ++ ++ for (i = 0; i < state->unused_service; i++) { ++ VCHIQ_SERVICE_T *service = state->services[i]; ++ VCHIQ_INSTANCE_T instance; ++ ++ if (service && (service->base.callback == service_callback)) { ++ instance = service->instance; ++ if (instance && !instance->mark) { ++ len = snprintf(buf, sizeof(buf), ++ "Instance %x: pid %d,%s completions " ++ "%d/%d", ++ (unsigned int)instance, instance->pid, ++ instance->connected ? " connected, " : ++ "", ++ instance->completion_insert - ++ instance->completion_remove, ++ MAX_COMPLETIONS); ++ ++ vchiq_dump(dump_context, buf, len + 1); ++ ++ instance->mark = 1; ++ } ++ } ++ } + } + + /**************************************************************************** +@@ -1163,26 +1290,26 @@ + void + vchiq_dump_platform_service_state(void *dump_context, VCHIQ_SERVICE_T *service) + { +- USER_SERVICE_T *user_service = (USER_SERVICE_T *)service->base.userdata; +- char buf[80]; +- int len; +- +- len = vcos_snprintf(buf, sizeof(buf), " instance %x", +- service->instance); +- +- if ((service->base.callback == service_callback) && user_service->is_vchi) +- { +- len += vcos_snprintf(buf + len, sizeof(buf) - len, +- ", %d/%d messages", +- user_service->msg_insert - user_service->msg_remove, +- MSG_QUEUE_SIZE); +- +- if (user_service->dequeue_pending) +- len += vcos_snprintf(buf + len, sizeof(buf) - len, +- " (dequeue pending)"); +- } ++ USER_SERVICE_T *user_service = (USER_SERVICE_T *)service->base.userdata; ++ char buf[80]; ++ int len; ++ ++ len = snprintf(buf, sizeof(buf), " instance %x", ++ (unsigned int)service->instance); ++ ++ if ((service->base.callback == service_callback) && ++ user_service->is_vchi) { ++ len += snprintf(buf + len, sizeof(buf) - len, ++ ", %d/%d messages", ++ user_service->msg_insert - user_service->msg_remove, ++ MSG_QUEUE_SIZE); ++ ++ if (user_service->dequeue_pending) ++ len += snprintf(buf + len, sizeof(buf) - len, ++ " (dequeue pending)"); ++ } + +- vchiq_dump(dump_context, buf, len + 1); ++ vchiq_dump(dump_context, buf, len + 1); + } + + /**************************************************************************** +@@ -1192,79 +1319,82 @@ + ***************************************************************************/ + + static void +-dump_phys_mem( void *virt_addr, uint32_t num_bytes ) ++dump_phys_mem(void *virt_addr, uint32_t num_bytes) + { +- int rc; +- uint8_t *end_virt_addr = virt_addr + num_bytes; +- int num_pages; +- int offset; +- int end_offset; +- int page_idx; +- int prev_idx; +- struct page *page; +- struct page **pages; +- uint8_t *kmapped_virt_ptr; +- +- // Align virtAddr and endVirtAddr to 16 byte boundaries. +- +- virt_addr = (void *)((unsigned long)virt_addr & ~0x0fuL ); +- end_virt_addr = (void *)(( (unsigned long)end_virt_addr + 15uL ) & ~0x0fuL); +- +- offset = (int)(long)virt_addr & ( PAGE_SIZE - 1 ); +- end_offset = (int)(long)end_virt_addr & ( PAGE_SIZE - 1 ); +- +- num_pages = (offset + num_bytes + PAGE_SIZE - 1) / PAGE_SIZE; +- +- if (( pages = kmalloc( sizeof( struct page *) * num_pages, GFP_KERNEL )) == NULL ) +- { +- printk( KERN_ERR "Unable to allocation memory for %d pages\n", num_pages ); +- return; +- } +- +- down_read( ¤t->mm->mmap_sem ); +- rc = get_user_pages( current, /* task */ +- current->mm, /* mm */ +- (unsigned long)virt_addr, /* start */ +- num_pages, /* len */ +- 0, /* write */ +- 0, /* force */ +- pages, /* pages (array of pointers to page) */ +- NULL ); /* vmas */ +- up_read( ¤t->mm->mmap_sem ); +- +- prev_idx = -1; +- page = NULL; +- +- while ( offset < end_offset ) { +- +- int page_offset = offset % PAGE_SIZE; +- page_idx = offset / PAGE_SIZE; +- +- if ( page_idx != prev_idx ) { +- +- if (page != NULL) { +- kunmap( page ); +- } +- page = pages[page_idx]; +- kmapped_virt_ptr = kmap( page ); +- +- prev_idx = page_idx; +- } +- +- vcos_log_dump_mem_impl( &vchiq_arm_log_category, "ph", +- (uint32_t)(unsigned long)&kmapped_virt_ptr[page_offset], +- &kmapped_virt_ptr[page_offset], 16 ); +- +- offset += 16; +- } +- if (page != NULL) { +- kunmap( page ); +- } +- +- for ( page_idx = 0; page_idx < num_pages; page_idx++ ) { +- page_cache_release( pages[page_idx] ); +- } +- kfree( pages ); ++ int rc; ++ uint8_t *end_virt_addr = virt_addr + num_bytes; ++ int num_pages; ++ int offset; ++ int end_offset; ++ int page_idx; ++ int prev_idx; ++ struct page *page; ++ struct page **pages; ++ uint8_t *kmapped_virt_ptr; ++ ++ /* Align virtAddr and endVirtAddr to 16 byte boundaries. */ ++ ++ virt_addr = (void *)((unsigned long)virt_addr & ~0x0fuL); ++ end_virt_addr = (void *)(((unsigned long)end_virt_addr + 15uL) & ++ ~0x0fuL); ++ ++ offset = (int)(long)virt_addr & (PAGE_SIZE - 1); ++ end_offset = (int)(long)end_virt_addr & (PAGE_SIZE - 1); ++ ++ num_pages = (offset + num_bytes + PAGE_SIZE - 1) / PAGE_SIZE; ++ ++ pages = kmalloc(sizeof(struct page *) * num_pages, GFP_KERNEL); ++ if (pages == NULL) { ++ vchiq_log_error(vchiq_arm_log_level, ++ "Unable to allocation memory for %d pages\n", ++ num_pages); ++ return; ++ } ++ ++ down_read(¤t->mm->mmap_sem); ++ rc = get_user_pages(current, /* task */ ++ current->mm, /* mm */ ++ (unsigned long)virt_addr, /* start */ ++ num_pages, /* len */ ++ 0, /* write */ ++ 0, /* force */ ++ pages, /* pages (array of page pointers) */ ++ NULL); /* vmas */ ++ up_read(¤t->mm->mmap_sem); ++ ++ prev_idx = -1; ++ page = NULL; ++ ++ while (offset < end_offset) { ++ ++ page_idx = offset / PAGE_SIZE; ++ int page_offset = offset % PAGE_SIZE; ++ ++ if (page_idx != prev_idx) { ++ ++ if (page != NULL) ++ kunmap(page); ++ page = pages[page_idx]; ++ kmapped_virt_ptr = kmap(page); ++ ++ prev_idx = page_idx; ++ } ++ ++ if (vchiq_arm_log_level >= VCHIQ_LOG_TRACE) ++ vchiq_log_dump_mem("ph", ++ (uint32_t)(unsigned long)&kmapped_virt_ptr[ ++ page_offset], ++ &kmapped_virt_ptr[page_offset], 16); ++ ++ offset += 16; ++ } ++ if (page != NULL) ++ kunmap(page); ++ ++ for (page_idx = 0; page_idx < num_pages; page_idx++) ++ page_cache_release(pages[page_idx]); ++ ++ kfree(pages); + } + + /**************************************************************************** +@@ -1274,548 +1404,1182 @@ + ***************************************************************************/ + + static ssize_t +-vchiq_read(struct file * file, char __user * buf, +- size_t count, loff_t *ppos) ++vchiq_read(struct file *file, char __user *buf, ++ size_t count, loff_t *ppos) + { +- DUMP_CONTEXT_T context; +- context.buf = buf; +- context.actual = 0; +- context.space = count; +- context.offset = *ppos; ++ DUMP_CONTEXT_T context; ++ context.buf = buf; ++ context.actual = 0; ++ context.space = count; ++ context.offset = *ppos; + +- vchiq_dump_state(&context, &g_state); ++ vchiq_dump_state(&context, &g_state); + +- if (context.actual >= 0) +- *ppos += context.actual; ++ if (context.actual >= 0) ++ *ppos += context.actual; + +- return context.actual; ++ return context.actual; + } + + VCHIQ_STATE_T * + vchiq_get_state(void) + { + +- if (g_state.remote == NULL) +- { +- printk( "%s: g_state.remote == NULL\n", __func__ ); +- } +- else +- { +- if ( g_state.remote->initialised != 1) +- { +- printk( "%s: g_state.remote->initialised != 1 (%d)\n", __func__, g_state.remote->initialised ); +- } +- } ++ if (g_state.remote == NULL) ++ printk(KERN_ERR "%s: g_state.remote == NULL\n", __func__); ++ else if (g_state.remote->initialised != 1) ++ printk(KERN_ERR "%s: g_state.remote->initialised != 1 (%d)\n", ++ __func__, g_state.remote->initialised); + +- return ((g_state.remote != NULL) && +- (g_state.remote->initialised == 1)) ? &g_state : NULL; ++ return ((g_state.remote != NULL) && ++ (g_state.remote->initialised == 1)) ? &g_state : NULL; + } + + static const struct file_operations + vchiq_fops = { +- .owner = THIS_MODULE, +- .unlocked_ioctl = vchiq_ioctl, +- .open = vchiq_open, +- .release = vchiq_release, +- .read = vchiq_read ++ .owner = THIS_MODULE, ++ .unlocked_ioctl = vchiq_ioctl, ++ .open = vchiq_open, ++ .release = vchiq_release, ++ .read = vchiq_read + }; + + /* + * Autosuspend related functionality + */ + +-static int vchiq_videocore_wanted(VCHIQ_STATE_T* state) ++int ++vchiq_videocore_wanted(VCHIQ_STATE_T *state) ++{ ++ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state); ++ if (!arm_state) ++ /* autosuspend not supported - always return wanted */ ++ return 1; ++ else if (arm_state->blocked_count) ++ return 1; ++ else if (!arm_state->videocore_use_count) ++ /* usage count zero - check for override unless we're forcing */ ++ if (arm_state->resume_blocked) ++ return 0; ++ else ++ return vchiq_platform_videocore_wanted(state); ++ else ++ /* non-zero usage count - videocore still required */ ++ return 1; ++} ++static VCHIQ_STATUS_T vchiq_keepalive_vchiq_callback(VCHIQ_REASON_T reason, ++ VCHIQ_HEADER_T *header, ++ VCHIQ_SERVICE_HANDLE_T service_user, ++ void *bulk_user) ++{ ++ vchiq_log_error(vchiq_susp_log_level, ++ "%s callback reason %d", __func__, reason); ++ return 0; ++} ++ ++static int ++vchiq_keepalive_thread_func(void *v) + { +- VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state); +- if(!arm_state) +- { // autosuspend not supported - always return wanted +- return 1; +- } +- else if(!arm_state->videocore_use_count) +- { // usage count zero - check for override +- return vchiq_platform_videocore_wanted(state); +- } +- else +- { // non-zero usage count - videocore still required +- return 1; +- } +-} +- +- +-/* Called by the lp thread */ +-static void * +-lp_func(void *v) +-{ +- VCHIQ_STATE_T *state = (VCHIQ_STATE_T *) v; +- VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state); +- +- while (1) { +- vcos_event_wait(&arm_state->lp_evt); +- +- vcos_mutex_lock(&arm_state->use_count_mutex); +- if (!vchiq_videocore_wanted(state)) +- { +- arm_state->suspend_pending = 1; +- } +- vcos_mutex_unlock(&arm_state->use_count_mutex); +- +- vchiq_arm_vcsuspend(state); +- } +- return NULL; +-} +-/* Called by the hp thread */ +-static void * +-hp_func(void *v) +-{ +- VCHIQ_STATE_T *state = (VCHIQ_STATE_T *) v; +- VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state); +- int send_pending; +- +- while (1) { +- vcos_event_wait(&arm_state->hp_evt); +- +- send_pending = 0; +- +- vcos_mutex_lock(&arm_state->use_count_mutex); +- if (vchiq_videocore_wanted(state)) +- { +- vchiq_arm_vcresume(state); +- } +- if(arm_state->use_notify_pending) +- { +- send_pending = arm_state->use_notify_pending; +- arm_state->use_notify_pending=0; +- } +- vcos_mutex_unlock(&arm_state->use_count_mutex); +- while(send_pending--) +- { +- vcos_log_info( "%s sending VCHIQ_MSG_REMOTE_USE_ACTIVE", __func__); +- if ( vchiq_send_remote_use_active(state) != VCHIQ_SUCCESS) +- { +- BUG(); /* vc should be resumed, so shouldn't be a problem sending message */ +- } +- } +- } +- return NULL; ++ VCHIQ_STATE_T *state = (VCHIQ_STATE_T *) v; ++ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state); ++ ++ VCHIQ_STATUS_T status; ++ VCHIQ_INSTANCE_T instance; ++ VCHIQ_SERVICE_HANDLE_T ka_handle; ++ ++ VCHIQ_SERVICE_PARAMS_T params = { ++ .fourcc = VCHIQ_MAKE_FOURCC('K', 'E', 'E', 'P'), ++ .callback = vchiq_keepalive_vchiq_callback, ++ .version = KEEPALIVE_VER, ++ .version_min = KEEPALIVE_VER_MIN ++ }; ++ ++ status = vchiq_initialise(&instance); ++ if (status != VCHIQ_SUCCESS) { ++ vchiq_log_error(vchiq_susp_log_level, ++ "%s vchiq_initialise failed %d", __func__, status); ++ goto exit; ++ } ++ ++ status = vchiq_connect(instance); ++ if (status != VCHIQ_SUCCESS) { ++ vchiq_log_error(vchiq_susp_log_level, ++ "%s vchiq_connect failed %d", __func__, status); ++ goto shutdown; ++ } ++ ++ status = vchiq_add_service(instance, ¶ms, &ka_handle); ++ if (status != VCHIQ_SUCCESS) { ++ vchiq_log_error(vchiq_susp_log_level, ++ "%s vchiq_open_service failed %d", __func__, status); ++ goto shutdown; ++ } ++ ++ while (1) { ++ long rc = 0, uc = 0; ++ if (wait_for_completion_interruptible(&arm_state->ka_evt) ++ != 0) { ++ vchiq_log_error(vchiq_susp_log_level, ++ "%s interrupted", __func__); ++ flush_signals(current); ++ continue; ++ } ++ ++ /* read and clear counters. Do release_count then use_count to ++ * prevent getting more releases than uses */ ++ rc = atomic_xchg(&arm_state->ka_release_count, 0); ++ uc = atomic_xchg(&arm_state->ka_use_count, 0); ++ ++ /* Call use/release service the requisite number of times. ++ * Process use before release so use counts don't go negative */ ++ while (uc--) { ++ atomic_inc(&arm_state->ka_use_ack_count); ++ status = vchiq_use_service(ka_handle); ++ if (status != VCHIQ_SUCCESS) { ++ vchiq_log_error(vchiq_susp_log_level, ++ "%s vchiq_use_service error %d", ++ __func__, status); ++ } ++ } ++ while (rc--) { ++ status = vchiq_release_service(ka_handle); ++ if (status != VCHIQ_SUCCESS) { ++ vchiq_log_error(vchiq_susp_log_level, ++ "%s vchiq_release_service error %d", ++ __func__, status); ++ } ++ } ++ } ++ ++shutdown: ++ vchiq_shutdown(instance); ++exit: ++ return 0; + } + ++ + VCHIQ_STATUS_T +-vchiq_arm_init_state(VCHIQ_STATE_T* state, VCHIQ_ARM_STATE_T *arm_state) ++vchiq_arm_init_state(VCHIQ_STATE_T *state, VCHIQ_ARM_STATE_T *arm_state) + { +- VCHIQ_STATUS_T status = VCHIQ_SUCCESS; +- VCOS_THREAD_ATTR_T attrs; +- char threadname[10]; +- +- if(arm_state) +- { +- vcos_mutex_create(&arm_state->use_count_mutex, "v.use_count_mutex"); +- vcos_mutex_create(&arm_state->suspend_resume_mutex, "v.susp_res_mutex"); +- +- vcos_event_create(&arm_state->lp_evt, "LP_EVT"); +- vcos_event_create(&arm_state->hp_evt, "HP_EVT"); +- +- vcos_thread_attr_init(&attrs); +- vcos_thread_attr_setstacksize(&attrs, VCHIQ_ARM_VCSUSPEND_TASK_STACK); +- vcos_thread_attr_setpriority(&attrs, VCOS_THREAD_PRI_LOWEST); +- vcos_snprintf(threadname, sizeof(threadname), "VCHIQl-%d", state->id); +- if(vcos_thread_create(&arm_state->lp_thread, threadname, &attrs, lp_func, state) != VCOS_SUCCESS) +- { +- vcos_log_error("vchiq: FATAL: couldn't create thread %s", threadname); +- status = VCHIQ_ERROR; +- } +- else +- { +- vcos_thread_attr_init(&attrs); +- vcos_thread_attr_setstacksize(&attrs, VCHIQ_ARM_VCSUSPEND_TASK_STACK); +- vcos_thread_attr_setpriority(&attrs, VCOS_THREAD_PRI_HIGHEST); +- vcos_snprintf(threadname, sizeof(threadname), "VCHIQh-%d", state->id); +- +- if(vcos_thread_create(&arm_state->hp_thread, threadname, &attrs, hp_func, state) != VCOS_SUCCESS) +- { +- vcos_log_error("vchiq: FATAL: couldn't create thread %s", threadname); +- status = VCHIQ_ERROR; +- } +- } +- } +- return status; ++ VCHIQ_STATUS_T status = VCHIQ_SUCCESS; ++ char threadname[10]; ++ ++ if (arm_state) { ++ mutex_init(&arm_state->vc_use_cnt_mutex); ++ rwlock_init(&arm_state->susp_res_lock); ++ ++ init_completion(&arm_state->ka_evt); ++ atomic_set(&arm_state->ka_use_count, 0); ++ atomic_set(&arm_state->ka_use_ack_count, 0); ++ atomic_set(&arm_state->ka_release_count, 0); ++ ++ init_completion(&arm_state->vc_suspend_complete); ++ ++ init_completion(&arm_state->vc_resume_complete); ++ /* Initialise to 'done' state. We only want to block on resume ++ * completion while videocore is suspended. */ ++ set_resume_state(arm_state, VC_RESUME_RESUMED); ++ ++ init_completion(&arm_state->resume_blocker); ++ /* Initialise to 'done' state. We only want to block on this ++ * completion while resume is blocked */ ++ complete_all(&arm_state->resume_blocker); ++ ++ init_completion(&arm_state->blocked_blocker); ++ /* Initialise to 'done' state. We only want to block on this ++ * completion while things are waiting on the resume blocker */ ++ complete_all(&arm_state->blocked_blocker); ++ ++ snprintf(threadname, sizeof(threadname), "VCHIQka-%d", ++ state->id); ++ arm_state->ka_thread = kthread_create( ++ &vchiq_keepalive_thread_func, ++ (void *)state, ++ threadname); ++ if (arm_state->ka_thread == NULL) { ++ vchiq_log_error(vchiq_susp_log_level, ++ "vchiq: FATAL: couldn't create thread %s", ++ threadname); ++ status = VCHIQ_ERROR; ++ } ++ ++ arm_state->suspend_timer_timeout = SUSPEND_TIMER_TIMEOUT_MS; ++ arm_state->suspend_timer_running = 0; ++ init_timer(&arm_state->suspend_timer); ++ arm_state->suspend_timer.data = (unsigned long)(state); ++ arm_state->suspend_timer.function = suspend_timer_callback; ++ ++ arm_state->first_connect = 0; ++ ++ } ++ return status; + } + ++/* ++** Functions to modify the state variables; ++** set_suspend_state ++** set_resume_state ++** ++** There are more state variables than we might like, so ensure they remain in ++** step. Suspend and resume state are maintained separately, since most of ++** these state machines can operate independently. However, there are a few ++** states where state transitions in one state machine cause a reset to the ++** other state machine. In addition, there are some completion events which ++** need to occur on state machine reset and end-state(s), so these are also ++** dealt with in these functions. ++** ++** In all states we set the state variable according to the input, but in some ++** cases we perform additional steps outlined below; ++** ++** VC_SUSPEND_IDLE - Initialise the suspend completion at the same time. ++** The suspend completion is completed after any suspend ++** attempt. When we reset the state machine we also reset ++** the completion. This reset occurs when videocore is ++** resumed, and also if we initiate suspend after a suspend ++** failure. ++** ++** VC_SUSPEND_IN_PROGRESS - This state is considered the point of no return for ++** suspend - ie from this point on we must try to suspend ++** before resuming can occur. We therefore also reset the ++** resume state machine to VC_RESUME_IDLE in this state. ++** ++** VC_SUSPEND_SUSPENDED - Suspend has completed successfully. Also call ++** complete_all on the suspend completion to notify ++** anything waiting for suspend to happen. ++** ++** VC_SUSPEND_REJECTED - Videocore rejected suspend. Videocore will also ++** initiate resume, so no need to alter resume state. ++** We call complete_all on the suspend completion to notify ++** of suspend rejection. ++** ++** VC_SUSPEND_FAILED - We failed to initiate videocore suspend. We notify the ++** suspend completion and reset the resume state machine. ++** ++** VC_RESUME_IDLE - Initialise the resume completion at the same time. The ++** resume completion is in it's 'done' state whenever ++** videcore is running. Therfore, the VC_RESUME_IDLE state ++** implies that videocore is suspended. ++** Hence, any thread which needs to wait until videocore is ++** running can wait on this completion - it will only block ++** if videocore is suspended. ++** ++** VC_RESUME_RESUMED - Resume has completed successfully. Videocore is running. ++** Call complete_all on the resume completion to unblock ++** any threads waiting for resume. Also reset the suspend ++** state machine to it's idle state. ++** ++** VC_RESUME_FAILED - Currently unused - no mechanism to fail resume exists. ++*/ ++ ++inline void ++set_suspend_state(VCHIQ_ARM_STATE_T *arm_state, ++ enum vc_suspend_status new_state) ++{ ++ /* set the state in all cases */ ++ arm_state->vc_suspend_state = new_state; ++ ++ /* state specific additional actions */ ++ switch (new_state) { ++ case VC_SUSPEND_FORCE_CANCELED: ++ complete_all(&arm_state->vc_suspend_complete); ++ break; ++ case VC_SUSPEND_REJECTED: ++ complete_all(&arm_state->vc_suspend_complete); ++ break; ++ case VC_SUSPEND_FAILED: ++ complete_all(&arm_state->vc_suspend_complete); ++ arm_state->vc_resume_state = VC_RESUME_RESUMED; ++ complete_all(&arm_state->vc_resume_complete); ++ break; ++ case VC_SUSPEND_IDLE: ++ INIT_COMPLETION(arm_state->vc_suspend_complete); ++ break; ++ case VC_SUSPEND_REQUESTED: ++ break; ++ case VC_SUSPEND_IN_PROGRESS: ++ set_resume_state(arm_state, VC_RESUME_IDLE); ++ break; ++ case VC_SUSPEND_SUSPENDED: ++ complete_all(&arm_state->vc_suspend_complete); ++ break; ++ default: ++ BUG(); ++ break; ++ } ++} ++ ++inline void ++set_resume_state(VCHIQ_ARM_STATE_T *arm_state, ++ enum vc_resume_status new_state) ++{ ++ /* set the state in all cases */ ++ arm_state->vc_resume_state = new_state; ++ ++ /* state specific additional actions */ ++ switch (new_state) { ++ case VC_RESUME_FAILED: ++ break; ++ case VC_RESUME_IDLE: ++ INIT_COMPLETION(arm_state->vc_resume_complete); ++ break; ++ case VC_RESUME_REQUESTED: ++ break; ++ case VC_RESUME_IN_PROGRESS: ++ break; ++ case VC_RESUME_RESUMED: ++ complete_all(&arm_state->vc_resume_complete); ++ set_suspend_state(arm_state, VC_SUSPEND_IDLE); ++ break; ++ default: ++ BUG(); ++ break; ++ } ++} ++ ++ ++/* should be called with the write lock held */ ++inline void ++start_suspend_timer(VCHIQ_ARM_STATE_T *arm_state) ++{ ++ del_timer(&arm_state->suspend_timer); ++ arm_state->suspend_timer.expires = jiffies + ++ msecs_to_jiffies(arm_state-> ++ suspend_timer_timeout); ++ add_timer(&arm_state->suspend_timer); ++ arm_state->suspend_timer_running = 1; ++} ++ ++/* should be called with the write lock held */ ++static inline void ++stop_suspend_timer(VCHIQ_ARM_STATE_T *arm_state) ++{ ++ if (arm_state->suspend_timer_running) { ++ del_timer(&arm_state->suspend_timer); ++ arm_state->suspend_timer_running = 0; ++ } ++} ++ ++static inline int ++need_resume(VCHIQ_STATE_T *state) ++{ ++ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state); ++ return (arm_state->vc_suspend_state > VC_SUSPEND_IDLE) && ++ (arm_state->vc_resume_state < VC_RESUME_REQUESTED) && ++ vchiq_videocore_wanted(state); ++} + ++static int ++block_resume(VCHIQ_ARM_STATE_T *arm_state) ++{ ++ int status = VCHIQ_SUCCESS; ++ while (arm_state->blocked_count) { ++ INIT_COMPLETION(arm_state->blocked_blocker); ++ write_unlock_bh(&arm_state->susp_res_lock); ++ vchiq_log_info(vchiq_susp_log_level, "%s wait for previously " ++ "blocked clients", __func__); ++ if (wait_for_completion_interruptible_timeout( ++ &arm_state->blocked_blocker, ++ msecs_to_jiffies(FORCE_SUSPEND_TIMEOUT_MS)) ++ <= 0) { ++ vchiq_log_error(vchiq_susp_log_level, "%s wait for " ++ "previously blocked clients failed" , __func__); ++ status = VCHIQ_ERROR; ++ write_lock_bh(&arm_state->susp_res_lock); ++ goto out; ++ } ++ vchiq_log_info(vchiq_susp_log_level, "%s previously blocked " ++ "clients resumed", __func__); ++ write_lock_bh(&arm_state->susp_res_lock); ++ } ++ while (arm_state->vc_resume_state != VC_RESUME_RESUMED && ++ arm_state->vc_resume_state > VC_RESUME_IDLE) { ++ if (!try_wait_for_completion(&arm_state->vc_resume_complete)) { ++ write_unlock_bh(&arm_state->susp_res_lock); ++ vchiq_log_info(vchiq_susp_log_level, "%s wait for " ++ "resume", __func__); ++ if (wait_for_completion_interruptible_timeout( ++ &arm_state->vc_resume_complete, ++ msecs_to_jiffies( ++ FORCE_SUSPEND_TIMEOUT_MS)) ++ <= 0) { ++ vchiq_log_error(vchiq_susp_log_level, "%s wait " ++ "for resume failed (%s)", __func__, ++ resume_state_names[ ++ arm_state->vc_resume_state + ++ VC_RESUME_NUM_OFFSET]); ++ status = VCHIQ_ERROR; ++ write_lock_bh(&arm_state->susp_res_lock); ++ goto out; ++ } ++ vchiq_log_info(vchiq_susp_log_level, "%s resumed", ++ __func__); ++ write_lock_bh(&arm_state->susp_res_lock); ++ } ++ } ++ INIT_COMPLETION(arm_state->resume_blocker); ++ arm_state->resume_blocked = 1; ++ ++out: ++ return status; ++} ++ ++inline static void ++unblock_resume(VCHIQ_ARM_STATE_T *arm_state) ++{ ++ complete_all(&arm_state->resume_blocker); ++ arm_state->resume_blocked = 0; ++} ++ ++/* Initiate suspend via slot handler. Should be called with the write lock ++ * held */ + VCHIQ_STATUS_T + vchiq_arm_vcsuspend(VCHIQ_STATE_T *state) + { +- VCHIQ_STATUS_T status = VCHIQ_SUCCESS; +- VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state); ++ VCHIQ_STATUS_T status = VCHIQ_ERROR; ++ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state); ++ ++ if (!arm_state) ++ goto out; ++ ++ vchiq_log_trace(vchiq_susp_log_level, "%s", __func__); ++ status = VCHIQ_SUCCESS; ++ ++ ++ switch (arm_state->vc_suspend_state) { ++ case VC_SUSPEND_REQUESTED: ++ vchiq_log_info(vchiq_susp_log_level, "%s: suspend already " ++ "requested", __func__); ++ break; ++ case VC_SUSPEND_IN_PROGRESS: ++ vchiq_log_info(vchiq_susp_log_level, "%s: suspend already in " ++ "progress", __func__); ++ break; ++ ++ default: ++ /* We don't expect to be in other states, so log but continue ++ * anyway */ ++ vchiq_log_error(vchiq_susp_log_level, ++ "%s unexpected suspend state %s", __func__, ++ suspend_state_names[arm_state->vc_suspend_state + ++ VC_SUSPEND_NUM_OFFSET]); ++ /* fall through */ ++ case VC_SUSPEND_REJECTED: ++ case VC_SUSPEND_FAILED: ++ INIT_COMPLETION(arm_state->vc_suspend_complete); ++ /* fall through */ ++ case VC_SUSPEND_IDLE: ++ vchiq_log_info(vchiq_susp_log_level, ++ "%s: suspending", __func__); ++ set_suspend_state(arm_state, VC_SUSPEND_REQUESTED); ++ /* kick the slot handler thread to initiate suspend */ ++ request_poll(state, NULL, 0); ++ break; ++ } ++ ++out: ++ vchiq_log_trace(vchiq_susp_log_level, "%s exit %d", __func__, status); ++ return status; ++} ++ ++void ++vchiq_platform_check_suspend(VCHIQ_STATE_T *state) ++{ ++ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state); ++ int susp = 0; ++ ++ if (!arm_state) ++ goto out; ++ ++ vchiq_log_trace(vchiq_susp_log_level, "%s", __func__); ++ ++ write_lock_bh(&arm_state->susp_res_lock); ++ if (arm_state->vc_suspend_state == VC_SUSPEND_REQUESTED && ++ arm_state->vc_resume_state == VC_RESUME_RESUMED) { ++ set_suspend_state(arm_state, VC_SUSPEND_IN_PROGRESS); ++ susp = 1; ++ } ++ write_unlock_bh(&arm_state->susp_res_lock); + +- if (state->conn_state != VCHIQ_CONNSTATE_CONNECTED) +- return VCHIQ_ERROR; ++ if (susp) ++ vchiq_platform_suspend(state); + +- if(arm_state->suspend_pending) +- { +- vcos_mutex_lock(&arm_state->suspend_resume_mutex); +- if(arm_state->videocore_suspended) +- { +- vcos_log_info("%s - already suspended", __func__); +- } +- else +- { +- vcos_log_info("%s - suspending", __func__); +- +- status = vchiq_platform_suspend(state); +- arm_state->videocore_suspended = (status == VCHIQ_SUCCESS) ? 1 : 0; +- +- vcos_mutex_unlock(&arm_state->suspend_resume_mutex); +- +- vcos_mutex_lock(&arm_state->use_count_mutex); +- if(!arm_state->suspend_pending) +- { /* Something has changed the suspend_pending state while we were suspending. +- Run the HP task to check if we need to resume */ +- vcos_log_info( "%s trigger HP task to check resume", __func__); +- vcos_event_signal(&arm_state->hp_evt); +- } +- arm_state->suspend_pending = 0; +- vcos_mutex_unlock(&arm_state->use_count_mutex); +- } +- } +- else +- { +- vchiq_check_resume(state); +- } +- return status; ++out: ++ vchiq_log_trace(vchiq_susp_log_level, "%s exit", __func__); ++ return; + } + + ++ ++/* Try to get videocore into suspended state, regardless of autosuspend state. ++** We don't actually force suspend, since videocore may get into a bad state ++** if we force suspend at a bad time. Instead, we wait for autosuspend to ++** determine a good point to suspend. If this doesn't happen within 100ms we ++** report failure. ++** ++** Returns VCHIQ_SUCCESS if videocore suspended successfully, VCHIQ_RETRY if ++** videocore failed to suspend in time or VCHIQ_ERROR if interrupted. ++*/ + VCHIQ_STATUS_T +-vchiq_arm_vcresume(VCHIQ_STATE_T *state) ++vchiq_arm_force_suspend(VCHIQ_STATE_T *state) ++{ ++ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state); ++ VCHIQ_STATUS_T status = VCHIQ_ERROR; ++ long rc = 0; ++ int repeat = -1; ++ static int autosuspend_override; ++ ++ if (!arm_state) ++ goto out; ++ ++ vchiq_log_trace(vchiq_susp_log_level, "%s", __func__); ++ ++ write_lock_bh(&arm_state->susp_res_lock); ++ ++ status = block_resume(arm_state); ++ if (status != VCHIQ_SUCCESS) ++ goto unlock; ++ if (arm_state->vc_suspend_state == VC_SUSPEND_SUSPENDED) { ++ /* Already suspended - just block resume and exit */ ++ vchiq_log_info(vchiq_susp_log_level, "%s already " ++ "suspended", __func__); ++ status = VCHIQ_SUCCESS; ++ goto unlock; ++ } else if (arm_state->vc_suspend_state <= VC_SUSPEND_IDLE) { ++ /* initiate suspend immediately in the case that we're waiting ++ * for the timeout */ ++ stop_suspend_timer(arm_state); ++ if (!vchiq_videocore_wanted(state)) { ++ vchiq_log_info(vchiq_susp_log_level, "%s videocore " ++ "idle, initiating suspend", __func__); ++ status = vchiq_arm_vcsuspend(state); ++ } else if (autosuspend_override < FORCE_SUSPEND_FAIL_MAX) { ++ vchiq_log_info(vchiq_susp_log_level, "%s letting " ++ "videocore go idle", __func__); ++ status = VCHIQ_SUCCESS; ++ } else { ++ vchiq_log_warning(vchiq_susp_log_level, "%s failed too " ++ "many times - no more Mr Nice Guy... " ++ "initiating suspend", __func__); ++ status = vchiq_arm_vcsuspend(state); ++ } ++ } else { ++ vchiq_log_info(vchiq_susp_log_level, "%s videocore suspend " ++ "in progress - wait for completion", __func__); ++ status = VCHIQ_SUCCESS; ++ } ++ ++ /* Wait for suspend to happen due to system idle (not forced..) */ ++ if (status == VCHIQ_SUCCESS) { ++ do { ++ write_unlock_bh(&arm_state->susp_res_lock); ++ ++ rc = wait_for_completion_interruptible_timeout( ++ &arm_state->vc_suspend_complete, ++ msecs_to_jiffies(FORCE_SUSPEND_TIMEOUT_MS)); ++ ++ write_lock_bh(&arm_state->susp_res_lock); ++ if (rc < 0) { ++ vchiq_log_warning(vchiq_susp_log_level, "%s " ++ "interrupted waiting for suspend", ++ __func__); ++ status = VCHIQ_ERROR; ++ goto unblock_resume; ++ } else if (rc == 0) { ++ if (arm_state->vc_suspend_state > ++ VC_SUSPEND_IDLE) { ++ /* Repeat timeout once if in progress */ ++ if (repeat < 0) { ++ repeat = 1; ++ continue; ++ } ++ } ++ autosuspend_override++; ++ vchiq_log_warning(vchiq_susp_log_level, ++ "%s timed out waiting for vc suspend " ++ "(%d)", __func__, autosuspend_override); ++ status = VCHIQ_RETRY; ++ goto unblock_resume; ++ } ++ } while (0 < (repeat--)); ++ } else ++ goto unblock_resume; ++ ++ /* Check and report state in case we need to abort ARM suspend */ ++ if (arm_state->vc_suspend_state != VC_SUSPEND_SUSPENDED) { ++ status = VCHIQ_RETRY; ++ vchiq_log_error(vchiq_susp_log_level, ++ "%s videocore suspend failed (state %s)", __func__, ++ suspend_state_names[arm_state->vc_suspend_state + ++ VC_SUSPEND_NUM_OFFSET]); ++ /* Reset the state only if it's still in an error state. ++ * Something could have already initiated another suspend. */ ++ if (arm_state->vc_suspend_state < VC_SUSPEND_IDLE) ++ set_suspend_state(arm_state, VC_SUSPEND_IDLE); ++ ++ goto unblock_resume; ++ } ++ ++ /* successfully suspended - reset override counter, unlock and exit */ ++ autosuspend_override = 0; ++ goto unlock; ++ ++unblock_resume: ++ /* all error states need to unblock resume before exit */ ++ unblock_resume(arm_state); ++ ++unlock: ++ write_unlock_bh(&arm_state->susp_res_lock); ++ ++out: ++ vchiq_log_trace(vchiq_susp_log_level, "%s exit %d", __func__, status); ++ return status; ++} ++ ++void ++vchiq_check_suspend(VCHIQ_STATE_T *state) + { +- VCHIQ_STATUS_T status = VCHIQ_SUCCESS; +- VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state); +- vcos_mutex_lock(&arm_state->suspend_resume_mutex); ++ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state); + +- status = vchiq_platform_resume(state); +- arm_state->videocore_suspended = (status == VCHIQ_RETRY) ? 1 : 0; ++ if (!arm_state) ++ goto out; + +- vcos_mutex_unlock(&arm_state->suspend_resume_mutex); ++ vchiq_log_trace(vchiq_susp_log_level, "%s", __func__); + +- return status; ++ write_lock_bh(&arm_state->susp_res_lock); ++ if (arm_state->vc_suspend_state != VC_SUSPEND_SUSPENDED && ++ arm_state->first_connect && ++ !vchiq_videocore_wanted(state)) { ++ vchiq_arm_vcsuspend(state); ++ } ++ write_unlock_bh(&arm_state->susp_res_lock); ++ ++out: ++ vchiq_log_trace(vchiq_susp_log_level, "%s exit", __func__); ++ return; + } + +-void +-vchiq_check_resume(VCHIQ_STATE_T* state) ++ ++int ++vchiq_arm_allow_resume(VCHIQ_STATE_T *state) ++{ ++ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state); ++ int resume = 0; ++ int ret = -1; ++ ++ if (!arm_state) ++ goto out; ++ ++ vchiq_log_trace(vchiq_susp_log_level, "%s", __func__); ++ ++ write_lock_bh(&arm_state->susp_res_lock); ++ unblock_resume(arm_state); ++ resume = vchiq_check_resume(state); ++ write_unlock_bh(&arm_state->susp_res_lock); ++ ++ if (resume) { ++ wait_for_completion_interruptible( ++ &arm_state->vc_resume_complete); ++ } ++ ++ read_lock_bh(&arm_state->susp_res_lock); ++ if (arm_state->vc_suspend_state == VC_SUSPEND_SUSPENDED) { ++ vchiq_log_info(vchiq_susp_log_level, ++ "%s: Videocore remains suspended", __func__); ++ } else { ++ vchiq_log_info(vchiq_susp_log_level, ++ "%s: Videocore resumed", __func__); ++ ret = 0; ++ } ++ read_unlock_bh(&arm_state->susp_res_lock); ++out: ++ vchiq_log_trace(vchiq_susp_log_level, "%s exit %d", __func__, ret); ++ return ret; ++} ++ ++/* This function should be called with the write lock held */ ++int ++vchiq_check_resume(VCHIQ_STATE_T *state) + { +- VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state); +- vcos_mutex_lock(&arm_state->use_count_mutex); ++ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state); ++ int resume = 0; ++ ++ if (!arm_state) ++ goto out; + +- if (arm_state->videocore_suspended && vchiq_videocore_wanted(state)) +- { /* signal high priority task to resume vc */ +- vcos_event_signal(&arm_state->hp_evt); +- } ++ vchiq_log_trace(vchiq_susp_log_level, "%s", __func__); + +- vcos_mutex_unlock(&arm_state->use_count_mutex); ++ if (need_resume(state)) { ++ set_resume_state(arm_state, VC_RESUME_REQUESTED); ++ request_poll(state, NULL, 0); ++ resume = 1; ++ } ++ ++out: ++ vchiq_log_trace(vchiq_susp_log_level, "%s exit", __func__); ++ return resume; + } + + void +-vchiq_check_suspend(VCHIQ_STATE_T* state) ++vchiq_platform_check_resume(VCHIQ_STATE_T *state) + { +- VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state); ++ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state); ++ int res = 0; + +- vcos_mutex_lock(&arm_state->use_count_mutex); ++ if (!arm_state) ++ goto out; + +- if (!arm_state->videocore_suspended && !vchiq_videocore_wanted(state)) +- { /* signal low priority task to suspend vc */ +- vcos_event_signal(&arm_state->lp_evt); +- } ++ vchiq_log_trace(vchiq_susp_log_level, "%s", __func__); ++ ++ write_lock_bh(&arm_state->susp_res_lock); ++ if (arm_state->wake_address == 0) { ++ vchiq_log_info(vchiq_susp_log_level, ++ "%s: already awake", __func__); ++ goto unlock; ++ } ++ if (arm_state->vc_resume_state == VC_RESUME_IN_PROGRESS) { ++ vchiq_log_info(vchiq_susp_log_level, ++ "%s: already resuming", __func__); ++ goto unlock; ++ } ++ ++ if (arm_state->vc_resume_state == VC_RESUME_REQUESTED) { ++ set_resume_state(arm_state, VC_RESUME_IN_PROGRESS); ++ res = 1; ++ } else ++ vchiq_log_trace(vchiq_susp_log_level, ++ "%s: not resuming (resume state %s)", __func__, ++ resume_state_names[arm_state->vc_resume_state + ++ VC_RESUME_NUM_OFFSET]); ++ ++unlock: ++ write_unlock_bh(&arm_state->susp_res_lock); ++ ++ if (res) ++ vchiq_platform_resume(state); ++ ++out: ++ vchiq_log_trace(vchiq_susp_log_level, "%s exit", __func__); ++ return; + +- vcos_mutex_unlock(&arm_state->use_count_mutex); + } + + + +-static VCHIQ_STATUS_T +-vchiq_use_internal(VCHIQ_STATE_T *state, VCHIQ_SERVICE_T *service, int block_while_resume) ++VCHIQ_STATUS_T ++vchiq_use_internal(VCHIQ_STATE_T *state, VCHIQ_SERVICE_T *service, ++ enum USE_TYPE_E use_type) + { +- VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state); +- VCHIQ_STATUS_T ret = VCHIQ_SUCCESS; +- char entity[10]; +- int* entity_uc; +- +- if(arm_state) +- { +- vcos_mutex_lock(&arm_state->use_count_mutex); +- +- if (service) +- { +- sprintf(entity, "%c%c%c%c:%03d",VCHIQ_FOURCC_AS_4CHARS(service->base.fourcc), service->client_id); +- entity_uc = &service->service_use_count; +- } +- else +- { +- sprintf(entity, "PEER: "); +- entity_uc = &arm_state->peer_use_count; +- } +- +- if (!arm_state->videocore_suspended && !vchiq_videocore_wanted(state)) +- { +-#if VCOS_HAVE_TIMER +- if (vchiq_platform_use_suspend_timer()) +- { +- vcos_log_trace( "%s %s - cancel suspend timer", __func__, entity); +- } +- vcos_timer_cancel(&g_suspend_timer); +-#endif +- } +- +- arm_state->videocore_use_count++; +- (*entity_uc)++; +- arm_state->suspend_pending = 0; +- +- if (arm_state->videocore_suspended && vchiq_videocore_wanted(state)) +- { +- vcos_log_info( "%s %s count %d, state count %d", __func__, entity, *entity_uc, arm_state->videocore_use_count); +- if(block_while_resume) +- { +- ret = vchiq_arm_vcresume(state); +- } +- else +- { +- vcos_log_info( "%s trigger HP task to do resume", __func__); /* triggering is done below */ +- } +- } +- else +- { +- vcos_log_trace( "%s %s count %d, state count %d", __func__, entity, *entity_uc, arm_state->videocore_use_count); +- } +- if(!block_while_resume) +- { +- arm_state->use_notify_pending++; +- vcos_event_signal(&arm_state->hp_evt); /* hp task will check if we need to resume and also send use notify */ +- } +- +- if (ret == VCHIQ_RETRY) +- { /* if we're told to retry, decrement the counters. VCHIQ_ERROR probably means we're already resumed. */ +- (*entity_uc)--; +- arm_state->videocore_use_count--; +- } +- +- vcos_mutex_unlock(&arm_state->use_count_mutex); +- } +- return ret; ++ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state); ++ VCHIQ_STATUS_T ret = VCHIQ_SUCCESS; ++ char entity[16]; ++ int *entity_uc; ++ int local_uc, local_entity_uc; ++ ++ if (!arm_state) ++ goto out; ++ ++ vchiq_log_trace(vchiq_susp_log_level, "%s", __func__); ++ ++ if (use_type != USE_TYPE_SERVICE) { ++ sprintf(entity, "PEER: "); ++ entity_uc = &arm_state->peer_use_count; ++ } else if (service) { ++ sprintf(entity, "%c%c%c%c:%03d", ++ VCHIQ_FOURCC_AS_4CHARS(service->base.fourcc), ++ service->client_id); ++ entity_uc = &service->service_use_count; ++ } else { ++ vchiq_log_error(vchiq_susp_log_level, "%s null service " ++ "ptr", __func__); ++ ret = VCHIQ_ERROR; ++ goto out; ++ } ++ ++ write_lock_bh(&arm_state->susp_res_lock); ++ while (arm_state->resume_blocked) { ++ /* If we call 'use' while force suspend is waiting for suspend, ++ * then we're about to block the thread which the force is ++ * waiting to complete, so we're bound to just time out. In this ++ * case, set the suspend state such that the wait will be ++ * canceled, so we can complete as quickly as possible. */ ++ if (arm_state->resume_blocked && arm_state->vc_suspend_state == ++ VC_SUSPEND_IDLE) { ++ set_suspend_state(arm_state, VC_SUSPEND_FORCE_CANCELED); ++ break; ++ } ++ /* If suspend is already in progress then we need to block */ ++ if (!try_wait_for_completion(&arm_state->resume_blocker)) { ++ /* Indicate that there are threads waiting on the resume ++ * blocker. These need to be allowed to complete before ++ * a _second_ call to force suspend can complete, ++ * otherwise low priority threads might never actually ++ * continue */ ++ arm_state->blocked_count++; ++ write_unlock_bh(&arm_state->susp_res_lock); ++ vchiq_log_info(vchiq_susp_log_level, "%s %s resume " ++ "blocked - waiting...", __func__, entity); ++ if (wait_for_completion_killable( ++ &arm_state->resume_blocker) != 0) { ++ vchiq_log_error(vchiq_susp_log_level, "%s %s " ++ "wait for resume blocker interrupted", ++ __func__, entity); ++ ret = VCHIQ_ERROR; ++ write_lock_bh(&arm_state->susp_res_lock); ++ arm_state->blocked_count--; ++ write_unlock_bh(&arm_state->susp_res_lock); ++ goto out; ++ } ++ vchiq_log_info(vchiq_susp_log_level, "%s %s resume " ++ "unblocked", __func__, entity); ++ write_lock_bh(&arm_state->susp_res_lock); ++ if (--arm_state->blocked_count == 0) ++ complete_all(&arm_state->blocked_blocker); ++ } ++ } ++ ++ stop_suspend_timer(arm_state); ++ write_unlock_bh(&arm_state->susp_res_lock); ++ ++ mutex_lock(&arm_state->vc_use_cnt_mutex); ++ if (!arm_state->videocore_use_count) ++ pm_qos_add_request(&arm_state->qos_request, ++ PM_QOS_CPU_DMA_LATENCY, 100); ++ ++ local_uc = ++arm_state->videocore_use_count; ++ local_entity_uc = ++(*entity_uc); ++ mutex_unlock(&arm_state->vc_use_cnt_mutex); ++ ++ write_lock_bh(&arm_state->susp_res_lock); ++ ++ /* If there's a pending request which hasn't yet been serviced then ++ * just clear it. If we're past VC_SUSPEND_REQUESTED state then ++ * vc_resume_complete will block until we either resume or fail to ++ * suspend */ ++ if (arm_state->vc_suspend_state <= VC_SUSPEND_REQUESTED) ++ set_suspend_state(arm_state, VC_SUSPEND_IDLE); ++ ++ if (need_resume(state)) { ++ set_resume_state(arm_state, VC_RESUME_REQUESTED); ++ vchiq_log_info(vchiq_susp_log_level, ++ "%s %s count %d, state count %d", ++ __func__, entity, local_entity_uc, local_uc); ++ request_poll(state, NULL, 0); ++ } else ++ vchiq_log_trace(vchiq_susp_log_level, ++ "%s %s count %d, state count %d", ++ __func__, entity, *entity_uc, local_uc); ++ ++ ++ write_unlock_bh(&arm_state->susp_res_lock); ++ ++ /* Completion is in a done state when we're not suspended, so this won't ++ * block for the non-suspended case. */ ++ if (!try_wait_for_completion(&arm_state->vc_resume_complete)) { ++ vchiq_log_info(vchiq_susp_log_level, "%s %s wait for resume", ++ __func__, entity); ++ if (wait_for_completion_killable( ++ &arm_state->vc_resume_complete) != 0) { ++ vchiq_log_error(vchiq_susp_log_level, "%s %s wait for " ++ "resume interrupted", __func__, entity); ++ ret = VCHIQ_ERROR; ++ goto out; ++ } ++ vchiq_log_info(vchiq_susp_log_level, "%s %s resumed", __func__, ++ entity); ++ } ++ ++ if (ret == VCHIQ_SUCCESS) { ++ VCHIQ_STATUS_T status = VCHIQ_SUCCESS; ++ long ack_cnt = atomic_xchg(&arm_state->ka_use_ack_count, 0); ++ while (ack_cnt && (status == VCHIQ_SUCCESS)) { ++ /* Send the use notify to videocore */ ++ status = vchiq_send_remote_use_active(state); ++ if (status == VCHIQ_SUCCESS) ++ ack_cnt--; ++ else ++ atomic_add(ack_cnt, ++ &arm_state->ka_use_ack_count); ++ } ++ } ++ ++out: ++ vchiq_log_trace(vchiq_susp_log_level, "%s exit %d", __func__, ret); ++ return ret; + } + +-static VCHIQ_STATUS_T ++VCHIQ_STATUS_T + vchiq_release_internal(VCHIQ_STATE_T *state, VCHIQ_SERVICE_T *service) + { +- VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state); +- VCHIQ_STATUS_T ret = VCHIQ_SUCCESS; +- char entity[10]; +- int* entity_uc; +- +- if(arm_state) +- { +- vcos_mutex_lock(&arm_state->use_count_mutex); +- +- if (service) +- { +- sprintf(entity, "%c%c%c%c:%03d",VCHIQ_FOURCC_AS_4CHARS(service->base.fourcc), service->client_id); +- entity_uc = &service->service_use_count; +- } +- else +- { +- sprintf(entity, "PEER: "); +- entity_uc = &arm_state->peer_use_count; +- } +- +- if (*entity_uc && arm_state->videocore_use_count) +- { +- arm_state->videocore_use_count--; +- (*entity_uc)--; +- +- if (!vchiq_videocore_wanted(state)) +- { +-#if VCOS_HAVE_TIMER +- if (vchiq_platform_use_suspend_timer()) +- { +- vcos_log_trace( "%s %s count %d, state count %d - starting suspend timer", __func__, entity, *entity_uc, arm_state->videocore_use_count); +- vcos_timer_cancel(&g_suspend_timer); +- vcos_timer_set(&g_suspend_timer, SUSPEND_TIMER_TIMEOUT_MS); +- } +- else +-#endif +- { +- vcos_log_info( "%s %s count %d, state count %d - suspend pending", __func__, entity, *entity_uc, arm_state->videocore_use_count); +- vcos_event_signal(&arm_state->lp_evt); /* kick the lp thread to do the suspend */ +- } +- } +- else +- { +- vcos_log_trace( "%s %s count %d, state count %d", __func__, entity, *entity_uc, arm_state->videocore_use_count); +- } +- } +- else +- { +- vcos_log_error( "%s %s ERROR releasing service; count %d, state count %d", __func__, entity, *entity_uc, arm_state->videocore_use_count); +- ret = VCHIQ_ERROR; +- } +- +- vcos_mutex_unlock(&arm_state->use_count_mutex); +- } +- return ret; ++ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state); ++ VCHIQ_STATUS_T ret = VCHIQ_SUCCESS; ++ char entity[16]; ++ int *entity_uc; ++ int local_uc, local_entity_uc; ++ ++ if (!arm_state) ++ goto out; ++ ++ vchiq_log_trace(vchiq_susp_log_level, "%s", __func__); ++ ++ if (service) { ++ sprintf(entity, "%c%c%c%c:%03d", ++ VCHIQ_FOURCC_AS_4CHARS(service->base.fourcc), ++ service->client_id); ++ entity_uc = &service->service_use_count; ++ } else { ++ sprintf(entity, "PEER: "); ++ entity_uc = &arm_state->peer_use_count; ++ } ++ ++ write_lock_bh(&arm_state->susp_res_lock); ++ if (!arm_state->videocore_use_count || !(*entity_uc)) { ++ /* Don't use BUG_ON - don't allow user thread to crash kernel */ ++ WARN_ON(!arm_state->videocore_use_count); ++ WARN_ON(!(*entity_uc)); ++ ret = VCHIQ_ERROR; ++ goto unlock; ++ } ++ write_unlock_bh(&arm_state->susp_res_lock); ++ ++ mutex_lock(&arm_state->vc_use_cnt_mutex); ++ local_uc = --arm_state->videocore_use_count; ++ local_entity_uc = --(*entity_uc); ++ ++ if (!arm_state->videocore_use_count) ++ pm_qos_remove_request(&arm_state->qos_request); ++ mutex_unlock(&arm_state->vc_use_cnt_mutex); ++ ++ write_lock_bh(&arm_state->susp_res_lock); ++ if (!vchiq_videocore_wanted(state)) { ++ if (vchiq_platform_use_suspend_timer() && ++ !arm_state->resume_blocked) { ++ /* Only use the timer if we're not trying to force ++ * suspend (=> resume_blocked) */ ++ start_suspend_timer(arm_state); ++ } else { ++ vchiq_log_info(vchiq_susp_log_level, ++ "%s %s count %d, state count %d - suspending", ++ __func__, entity, *entity_uc, ++ arm_state->videocore_use_count); ++ vchiq_arm_vcsuspend(state); ++ } ++ } else ++ vchiq_log_trace(vchiq_susp_log_level, ++ "%s %s count %d, state count %d", ++ __func__, entity, *entity_uc, ++ arm_state->videocore_use_count); ++ ++unlock: ++ write_unlock_bh(&arm_state->susp_res_lock); ++ ++out: ++ vchiq_log_trace(vchiq_susp_log_level, "%s exit %d", __func__, ret); ++ return ret; + } + +-VCHIQ_STATUS_T ++void + vchiq_on_remote_use(VCHIQ_STATE_T *state) + { +- vcos_log_info("%s state %p", __func__, state); +- return state ? vchiq_use_internal(state, NULL, 0) : VCHIQ_ERROR; ++ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state); ++ vchiq_log_trace(vchiq_susp_log_level, "%s", __func__); ++ atomic_inc(&arm_state->ka_use_count); ++ complete(&arm_state->ka_evt); + } + +-VCHIQ_STATUS_T ++void + vchiq_on_remote_release(VCHIQ_STATE_T *state) + { +- vcos_log_info("%s state %p", __func__, state); +- return state ? vchiq_release_internal(state, NULL) : VCHIQ_ERROR; ++ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state); ++ vchiq_log_trace(vchiq_susp_log_level, "%s", __func__); ++ atomic_inc(&arm_state->ka_release_count); ++ complete(&arm_state->ka_evt); + } + + VCHIQ_STATUS_T + vchiq_use_service_internal(VCHIQ_SERVICE_T *service) + { +- VCHIQ_STATE_T* state = NULL; +- +- if (service) +- { +- state = service->state; +- } +- +- if (!service || !state) +- { +- return VCHIQ_ERROR; +- } +- return vchiq_use_internal(state, service, 1); ++ return vchiq_use_internal(service->state, service, USE_TYPE_SERVICE); + } + + VCHIQ_STATUS_T + vchiq_release_service_internal(VCHIQ_SERVICE_T *service) + { +- VCHIQ_STATE_T* state = NULL; +- +- if (service) +- { +- state = service->state; +- } +- +- if (!service || !state) +- { +- return VCHIQ_ERROR; +- } +- return vchiq_release_internal(state, service); ++ return vchiq_release_internal(service->state, service); + } + +- +-#if VCOS_HAVE_TIMER +-static void suspend_timer_callback(void* context) ++static void suspend_timer_callback(unsigned long context) + { +- VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state((VCHIQ_STATE_T*)context); +- vcos_log_info( "%s - suspend pending", __func__); +- vcos_event_signal(&arm_state->lp_evt); ++ VCHIQ_STATE_T *state = (VCHIQ_STATE_T *)context; ++ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state); ++ if (!arm_state) ++ goto out; ++ vchiq_log_info(vchiq_susp_log_level, ++ "%s - suspend timer expired - check suspend", __func__); ++ vchiq_check_suspend(state); ++out: ++ return; + } +-#endif + + VCHIQ_STATUS_T + vchiq_use_service(VCHIQ_SERVICE_HANDLE_T handle) + { +- VCHIQ_STATUS_T ret = VCHIQ_ERROR; +- VCHIQ_SERVICE_T *service = (VCHIQ_SERVICE_T *) handle; +- if (service) +- { +- ret = vchiq_use_service_internal(service); +- } +- return ret; ++ VCHIQ_STATUS_T ret = VCHIQ_ERROR; ++ VCHIQ_SERVICE_T *service = find_service_by_handle(handle); ++ if (service) { ++ ret = vchiq_use_internal(service->state, service, ++ USE_TYPE_SERVICE); ++ unlock_service(service); ++ } ++ return ret; + } + + VCHIQ_STATUS_T + vchiq_release_service(VCHIQ_SERVICE_HANDLE_T handle) + { +- VCHIQ_STATUS_T ret = VCHIQ_ERROR; +- VCHIQ_SERVICE_T *service = (VCHIQ_SERVICE_T *) handle; +- if (service) +- { +- ret = vchiq_release_service_internal(service); +- } +- return ret; ++ VCHIQ_STATUS_T ret = VCHIQ_ERROR; ++ VCHIQ_SERVICE_T *service = find_service_by_handle(handle); ++ if (service) { ++ ret = vchiq_release_internal(service->state, service); ++ unlock_service(service); ++ } ++ return ret; + } + + void + vchiq_dump_service_use_state(VCHIQ_STATE_T *state) + { +- VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state); +- int i; +- if(arm_state) +- { +- vcos_mutex_lock(&arm_state->suspend_resume_mutex); +- if (arm_state->videocore_suspended) +- { +- vcos_log_warn("--VIDEOCORE SUSPENDED--"); +- } +- else +- { +- vcos_log_warn("--VIDEOCORE AWAKE--"); +- } +- for (i = 0; i < state->unused_service; i++) { +- VCHIQ_SERVICE_T *service_ptr = state->services[i]; +- if (service_ptr && (service_ptr->srvstate != VCHIQ_SRVSTATE_FREE)) +- { +- if (service_ptr->service_use_count) +- vcos_log_error("----- %c%c%c%c:%d service count %d <-- preventing suspend", VCHIQ_FOURCC_AS_4CHARS(service_ptr->base.fourcc), service_ptr->client_id, service_ptr->service_use_count); +- else +- vcos_log_warn("----- %c%c%c%c:%d service count 0", VCHIQ_FOURCC_AS_4CHARS(service_ptr->base.fourcc), service_ptr->client_id); +- } +- } +- vcos_log_warn("----- PEER use count count %d", arm_state->peer_use_count); +- vcos_log_warn("--- Overall vchiq instance use count %d", arm_state->videocore_use_count); +- +- vchiq_dump_platform_use_state(state); ++ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state); ++ int i, j = 0; ++ /* Only dump 64 services */ ++ static const int local_max_services = 64; ++ /* If there's more than 64 services, only dump ones with ++ * non-zero counts */ ++ int only_nonzero = 0; ++ static const char *nz = "<-- preventing suspend"; ++ ++ enum vc_suspend_status vc_suspend_state; ++ enum vc_resume_status vc_resume_state; ++ int peer_count; ++ int vc_use_count; ++ int active_services; ++ struct service_data_struct { ++ int fourcc; ++ int clientid; ++ int use_count; ++ } service_data[local_max_services]; ++ ++ if (!arm_state) ++ return; ++ ++ read_lock_bh(&arm_state->susp_res_lock); ++ vc_suspend_state = arm_state->vc_suspend_state; ++ vc_resume_state = arm_state->vc_resume_state; ++ peer_count = arm_state->peer_use_count; ++ vc_use_count = arm_state->videocore_use_count; ++ active_services = state->unused_service; ++ if (active_services > local_max_services) ++ only_nonzero = 1; ++ ++ for (i = 0; (i < active_services) && (j < local_max_services); i++) { ++ VCHIQ_SERVICE_T *service_ptr = state->services[i]; ++ if (!service_ptr) ++ continue; ++ ++ if (only_nonzero && !service_ptr->service_use_count) ++ continue; ++ ++ if (service_ptr->srvstate != VCHIQ_SRVSTATE_FREE) { ++ service_data[j].fourcc = service_ptr->base.fourcc; ++ service_data[j].clientid = service_ptr->client_id; ++ service_data[j++].use_count = service_ptr-> ++ service_use_count; ++ } ++ } ++ ++ read_unlock_bh(&arm_state->susp_res_lock); ++ ++ vchiq_log_warning(vchiq_susp_log_level, ++ "-- Videcore suspend state: %s --", ++ suspend_state_names[vc_suspend_state + VC_SUSPEND_NUM_OFFSET]); ++ vchiq_log_warning(vchiq_susp_log_level, ++ "-- Videcore resume state: %s --", ++ resume_state_names[vc_resume_state + VC_RESUME_NUM_OFFSET]); ++ ++ if (only_nonzero) ++ vchiq_log_warning(vchiq_susp_log_level, "Too many active " ++ "services (%d). Only dumping up to first %d services " ++ "with non-zero use-count", active_services, ++ local_max_services); ++ ++ for (i = 0; i < j; i++) { ++ vchiq_log_error(vchiq_arm_log_level, ++ "----- %c%c%c%c:%d service count %d %s", ++ VCHIQ_FOURCC_AS_4CHARS(service_data[i].fourcc), ++ service_data[i].clientid, ++ service_data[i].use_count, ++ service_data[i].use_count ? nz : ""); ++ } ++ vchiq_log_warning(vchiq_susp_log_level, ++ "----- PEER use count count %d", peer_count); ++ vchiq_log_warning(vchiq_susp_log_level, ++ "--- Overall vchiq instance use count %d", vc_use_count); + +- vcos_mutex_unlock(&arm_state->suspend_resume_mutex); +- } ++ vchiq_dump_platform_use_state(state); + } + + VCHIQ_STATUS_T +-vchiq_check_service(VCHIQ_SERVICE_T * service) ++vchiq_check_service(VCHIQ_SERVICE_T *service) + { +- VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(service->state); +- VCHIQ_STATUS_T ret = VCHIQ_ERROR; +- /* on 2835 vchiq does not have an arm_state */ +- if (!arm_state) +- return VCHIQ_SUCCESS; +- if (service && arm_state) +- { +- vcos_mutex_lock(&arm_state->use_count_mutex); +- if (!service->service_use_count) +- { +- vcos_log_error( "%s ERROR - %c%c%c%c:%d service count %d, state count %d, videocore_suspended %d", __func__,VCHIQ_FOURCC_AS_4CHARS(service->base.fourcc), service->client_id, service->service_use_count, arm_state->videocore_use_count, arm_state->videocore_suspended); +- vchiq_dump_service_use_state(service->state); +- vcos_assert(0); // vcos_assert should kill the calling thread, so a user thread shouldn't be able to kill the kernel. +- } +- else +- { +- ret = VCHIQ_SUCCESS; +- } +- vcos_mutex_unlock(&arm_state->use_count_mutex); +- } +- return ret; ++ VCHIQ_ARM_STATE_T *arm_state = ++ vchiq_platform_get_arm_state(service->state); ++ VCHIQ_STATUS_T ret = VCHIQ_ERROR; ++ ++ if (!arm_state || !service) ++ goto out; ++ ++ vchiq_log_trace(vchiq_susp_log_level, "%s", __func__); ++ ++ read_lock_bh(&arm_state->susp_res_lock); ++ if (service->service_use_count) ++ ret = VCHIQ_SUCCESS; ++ read_unlock_bh(&arm_state->susp_res_lock); ++ ++ if (ret == VCHIQ_ERROR) { ++ vchiq_log_error(vchiq_susp_log_level, ++ "%s ERROR - %c%c%c%c:%d service count %d, " ++ "state count %d, videocore suspend state %s", __func__, ++ VCHIQ_FOURCC_AS_4CHARS(service->base.fourcc), ++ service->client_id, service->service_use_count, ++ arm_state->videocore_use_count, ++ suspend_state_names[arm_state->vc_suspend_state + ++ VC_SUSPEND_NUM_OFFSET]); ++ vchiq_dump_service_use_state(service->state); ++ } ++out: ++ return ret; + } + + /* stub functions */ + void vchiq_on_remote_use_active(VCHIQ_STATE_T *state) + { +- vcos_unused(state); ++ (void)state; + } + +-void vchiq_platform_conn_state_changed(VCHIQ_STATE_T *state, VCHIQ_CONNSTATE_T oldstate, VCHIQ_CONNSTATE_T newstate) ++void vchiq_platform_conn_state_changed(VCHIQ_STATE_T *state, ++ VCHIQ_CONNSTATE_T oldstate, VCHIQ_CONNSTATE_T newstate) + { +- vcos_unused(state); +- vcos_unused(oldstate); +- vcos_unused(oldstate); ++ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state); ++ vchiq_log_info(vchiq_susp_log_level, "%d: %s->%s", state->id, ++ get_conn_state_name(oldstate), get_conn_state_name(newstate)); ++ if (state->conn_state == VCHIQ_CONNSTATE_CONNECTED) { ++ write_lock_bh(&arm_state->susp_res_lock); ++ if (!arm_state->first_connect) { ++ arm_state->first_connect = 1; ++ write_unlock_bh(&arm_state->susp_res_lock); ++ wake_up_process(arm_state->ka_thread); ++ } else ++ write_unlock_bh(&arm_state->susp_res_lock); ++ } + } + + +@@ -1828,67 +2592,132 @@ + static int __init + vchiq_init(void) + { +- int err; +- void *ptr_err; ++ int err; ++ void *ptr_err; + +- err = vchiq_platform_vcos_init(); +- if (err != 0) +- goto failed_platform_vcos_init; +- +- vcos_log_set_level(VCOS_LOG_CATEGORY, vchiq_default_arm_log_level); +- vcos_log_register("vchiq_arm", VCOS_LOG_CATEGORY); +- +- if ((err = +- alloc_chrdev_region(&vchiq_devid, VCHIQ_MINOR, 1, +- DEVICE_NAME)) != 0) { +- vcos_log_error("Unable to allocate device number"); +- goto failed_alloc_chrdev; +- } +- cdev_init(&vchiq_cdev, &vchiq_fops); +- vchiq_cdev.owner = THIS_MODULE; +- if ((err = cdev_add(&vchiq_cdev, vchiq_devid, 1)) != 0) { +- vcos_log_error("Unable to register device"); +- goto failed_cdev_add; +- } +- +- /* create sysfs entries */ +- vchiq_class = class_create(THIS_MODULE, DEVICE_NAME); +- if (IS_ERR(ptr_err = vchiq_class)) +- goto failed_class_create; +- +- vchiq_dev = device_create(vchiq_class, NULL, +- vchiq_devid, NULL, "vchiq"); +- if (IS_ERR(ptr_err = vchiq_dev)) +- goto failed_device_create; +- +- err = vchiq_platform_init(&g_state); +- if (err != 0) +- goto failed_platform_init; +- +-#if VCOS_HAVE_TIMER +- vcos_timer_create( &g_suspend_timer, "suspend_timer", suspend_timer_callback, (void*)(&g_state)); +-#endif +- +- vcos_log_error("vchiq: initialised - version %d (min %d), device %d.%d", +- VCHIQ_VERSION, VCHIQ_VERSION_MIN, +- MAJOR(vchiq_devid), MINOR(vchiq_devid)); ++ /* create proc entries */ ++ err = vchiq_proc_init(); ++ if (err != 0) ++ goto failed_proc_init; ++ ++ err = alloc_chrdev_region(&vchiq_devid, VCHIQ_MINOR, 1, DEVICE_NAME); ++ if (err != 0) { ++ vchiq_log_error(vchiq_arm_log_level, ++ "Unable to allocate device number"); ++ goto failed_alloc_chrdev; ++ } ++ cdev_init(&vchiq_cdev, &vchiq_fops); ++ vchiq_cdev.owner = THIS_MODULE; ++ err = cdev_add(&vchiq_cdev, vchiq_devid, 1); ++ if (err != 0) { ++ vchiq_log_error(vchiq_arm_log_level, ++ "Unable to register device"); ++ goto failed_cdev_add; ++ } ++ ++ /* create sysfs entries */ ++ vchiq_class = class_create(THIS_MODULE, DEVICE_NAME); ++ ptr_err = vchiq_class; ++ if (IS_ERR(ptr_err)) ++ goto failed_class_create; ++ ++ vchiq_dev = device_create(vchiq_class, NULL, ++ vchiq_devid, NULL, "vchiq"); ++ ptr_err = vchiq_dev; ++ if (IS_ERR(ptr_err)) ++ goto failed_device_create; ++ ++ err = vchiq_platform_init(&g_state); ++ if (err != 0) ++ goto failed_platform_init; ++ ++ vchiq_log_info(vchiq_arm_log_level, ++ "vchiq: initialised - version %d (min %d), device %d.%d", ++ VCHIQ_VERSION, VCHIQ_VERSION_MIN, ++ MAJOR(vchiq_devid), MINOR(vchiq_devid)); + +- return 0; ++ return 0; + + failed_platform_init: +- device_destroy(vchiq_class, vchiq_devid); ++ device_destroy(vchiq_class, vchiq_devid); + failed_device_create: +- class_destroy(vchiq_class); ++ class_destroy(vchiq_class); + failed_class_create: +- cdev_del(&vchiq_cdev); +- err = PTR_ERR(ptr_err); ++ cdev_del(&vchiq_cdev); ++ err = PTR_ERR(ptr_err); + failed_cdev_add: +- unregister_chrdev_region(vchiq_devid, 1); ++ unregister_chrdev_region(vchiq_devid, 1); + failed_alloc_chrdev: +-failed_platform_vcos_init: +- printk(KERN_WARNING "could not load vchiq\n"); +- return err; ++ vchiq_proc_deinit(); ++failed_proc_init: ++ vchiq_log_warning(vchiq_arm_log_level, "could not load vchiq"); ++ return err; + } ++ ++static int vchiq_instance_get_use_count(VCHIQ_INSTANCE_T instance) ++{ ++ VCHIQ_SERVICE_T *service; ++ int use_count = 0, i; ++ i = 0; ++ while ((service = next_service_by_instance(instance->state, ++ instance, &i)) != NULL) { ++ use_count += service->service_use_count; ++ unlock_service(service); ++ } ++ return use_count; ++} ++ ++/* read the per-process use-count */ ++static int proc_read_use_count(char *page, char **start, ++ off_t off, int count, ++ int *eof, void *data) ++{ ++ VCHIQ_INSTANCE_T instance = data; ++ int len, use_count; ++ ++ use_count = vchiq_instance_get_use_count(instance); ++ len = snprintf(page+off, count, "%d\n", use_count); ++ ++ return len; ++} ++ ++/* add an instance (process) to the proc entries */ ++static int vchiq_proc_add_instance(VCHIQ_INSTANCE_T instance) ++{ ++ char pidstr[32]; ++ struct proc_dir_entry *top, *use_count; ++ struct proc_dir_entry *clients = vchiq_clients_top(); ++ int pid = instance->pid; ++ ++ snprintf(pidstr, sizeof(pidstr), "%d", pid); ++ top = proc_mkdir(pidstr, clients); ++ if (!top) ++ goto fail_top; ++ ++ use_count = create_proc_read_entry("use_count", ++ 0444, top, ++ proc_read_use_count, ++ instance); ++ if (!use_count) ++ goto fail_use_count; ++ ++ instance->proc_entry = top; ++ ++ return 0; ++ ++fail_use_count: ++ remove_proc_entry(top->name, clients); ++fail_top: ++ return -ENOMEM; ++} ++ ++static void vchiq_proc_remove_instance(VCHIQ_INSTANCE_T instance) ++{ ++ struct proc_dir_entry *clients = vchiq_clients_top(); ++ remove_proc_entry("use_count", instance->proc_entry); ++ remove_proc_entry(instance->proc_entry->name, clients); ++} ++ + /**************************************************************************** + * + * vchiq_exit - called when the module is unloaded. +@@ -1898,12 +2727,11 @@ + static void __exit + vchiq_exit(void) + { +- vchiq_platform_exit(&g_state); +- device_destroy(vchiq_class, vchiq_devid); +- class_destroy(vchiq_class); +- cdev_del(&vchiq_cdev); +- unregister_chrdev_region(vchiq_devid, 1); +- vcos_log_unregister(VCOS_LOG_CATEGORY); ++ vchiq_platform_exit(&g_state); ++ device_destroy(vchiq_class, vchiq_devid); ++ class_destroy(vchiq_class); ++ cdev_del(&vchiq_cdev); ++ unregister_chrdev_region(vchiq_devid, 1); + } + + module_init(vchiq_init); +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_arm.h +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_arm.h 2013-07-26 19:32:28.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_arm.h 2013-07-26 19:36:51.000000000 +0000 +@@ -19,46 +19,101 @@ + #ifndef VCHIQ_ARM_H + #define VCHIQ_ARM_H + ++#include ++#include ++//#include ++#define pm_qos_add_request(a,b,c) do {} while (0) ++#define pm_qos_remove_request(a) do {} while (0) ++struct pm_qos_request_list {int dummy;}; ++#include + #include "vchiq_core.h" + + +-typedef struct vchiq_arm_state_struct { +- +- VCOS_THREAD_T lp_thread; /* processes low priority messages (eg suspend) */ +- VCOS_THREAD_T hp_thread; /* processes high priority messages (eg resume) */ ++enum vc_suspend_status { ++ VC_SUSPEND_FORCE_CANCELED = -3, /* Force suspend canceled, too busy */ ++ VC_SUSPEND_REJECTED = -2, /* Videocore rejected suspend request */ ++ VC_SUSPEND_FAILED = -1, /* Videocore suspend failed */ ++ VC_SUSPEND_IDLE = 0, /* VC active, no suspend actions */ ++ VC_SUSPEND_REQUESTED, /* User has requested suspend */ ++ VC_SUSPEND_IN_PROGRESS, /* Slot handler has recvd suspend request */ ++ VC_SUSPEND_SUSPENDED /* Videocore suspend succeeded */ ++}; ++ ++enum vc_resume_status { ++ VC_RESUME_FAILED = -1, /* Videocore resume failed */ ++ VC_RESUME_IDLE = 0, /* VC suspended, no resume actions */ ++ VC_RESUME_REQUESTED, /* User has requested resume */ ++ VC_RESUME_IN_PROGRESS, /* Slot handler has received resume request */ ++ VC_RESUME_RESUMED /* Videocore resumed successfully (active) */ ++}; ++ ++ ++enum USE_TYPE_E { ++ USE_TYPE_SERVICE, ++ USE_TYPE_PEER, ++ USE_TYPE_VCHIQ ++}; + +- VCOS_EVENT_T lp_evt; +- VCOS_EVENT_T hp_evt; + +- VCOS_MUTEX_T use_count_mutex; +- VCOS_MUTEX_T suspend_resume_mutex; ++typedef struct vchiq_arm_state_struct { ++ /* Keepalive-related data */ ++ struct task_struct *ka_thread; ++ struct completion ka_evt; ++ atomic_t ka_use_count; ++ atomic_t ka_use_ack_count; ++ atomic_t ka_release_count; ++ ++ struct completion vc_suspend_complete; ++ struct completion vc_resume_complete; ++ ++ rwlock_t susp_res_lock; ++ enum vc_suspend_status vc_suspend_state; ++ enum vc_resume_status vc_resume_state; ++ ++ struct mutex vc_use_cnt_mutex; ++ unsigned int wake_address; ++ ++ struct timer_list suspend_timer; ++ int suspend_timer_timeout; ++ int suspend_timer_running; ++ ++ /* Global use count for videocore. ++ ** This is equal to the sum of the use counts for all services. When ++ ** this hits zero the videocore suspend procedure will be initiated. ++ */ ++ int videocore_use_count; ++ ++ /* Use count to track requests from videocore peer. ++ ** This use count is not associated with a service, so needs to be ++ ** tracked separately with the state. ++ */ ++ int peer_use_count; ++ ++ /* Flag to indicate whether resume is blocked. This happens when the ++ ** ARM is suspending ++ */ ++ struct completion resume_blocker; ++ int resume_blocked; ++ struct completion blocked_blocker; ++ int blocked_count; ++ ++ /* Flag to indicate that the first vchiq connect has made it through. ++ ** This means that both sides should be fully ready, and we should ++ ** be able to suspend after this point. ++ */ ++ int first_connect; ++ ++ struct pm_qos_request_list qos_request; ++ ++ unsigned long long suspend_start_time; ++ unsigned long long sleep_start_time; ++ unsigned long long resume_start_time; ++ unsigned long long last_wake_time; + +- int suspend_pending; +- +- /* Global use count for videocore. +- * This is equal to the sum of the use counts for all services. When this hits +- * zero the videocore suspend procedure will be initiated. */ +- int videocore_use_count; +- +- /* Use count to track requests from videocore peer. +- * This use count is not associated with a service, so needs to be tracked separately +- * with the state. +- */ +- int peer_use_count; +- +- /* Flag to indicate whether videocore is currently suspended */ +- int videocore_suspended; +- +- /* Flag to indicate whether a notification is pending back to videocore that it's +- * "remote use request" has been actioned */ +- int use_notify_pending; + } VCHIQ_ARM_STATE_T; + +- +-extern VCOS_LOG_CAT_T vchiq_arm_log_category; +- +-extern int __init +-vchiq_platform_vcos_init(void); ++extern int vchiq_arm_log_level; ++extern int vchiq_susp_log_level; + + extern int __init + vchiq_platform_init(VCHIQ_STATE_T *state); +@@ -73,16 +128,22 @@ + vchiq_arm_vcsuspend(VCHIQ_STATE_T *state); + + extern VCHIQ_STATUS_T ++vchiq_arm_force_suspend(VCHIQ_STATE_T *state); ++ ++extern int ++vchiq_arm_allow_resume(VCHIQ_STATE_T *state); ++ ++extern VCHIQ_STATUS_T + vchiq_arm_vcresume(VCHIQ_STATE_T *state); + + extern VCHIQ_STATUS_T + vchiq_arm_init_state(VCHIQ_STATE_T *state, VCHIQ_ARM_STATE_T *arm_state); + +-extern void +-vchiq_check_resume(VCHIQ_STATE_T* state); ++extern int ++vchiq_check_resume(VCHIQ_STATE_T *state); + + extern void +-vchiq_check_suspend(VCHIQ_STATE_T* state); ++vchiq_check_suspend(VCHIQ_STATE_T *state); + + extern VCHIQ_STATUS_T + vchiq_use_service(VCHIQ_SERVICE_HANDLE_T handle); +@@ -91,16 +152,13 @@ + vchiq_release_service(VCHIQ_SERVICE_HANDLE_T handle); + + extern VCHIQ_STATUS_T +-vchiq_check_service(VCHIQ_SERVICE_T * service); ++vchiq_check_service(VCHIQ_SERVICE_T *service); + + extern VCHIQ_STATUS_T + vchiq_platform_suspend(VCHIQ_STATE_T *state); + +-extern VCHIQ_STATUS_T +-vchiq_platform_resume(VCHIQ_STATE_T *state); +- + extern int +-vchiq_platform_videocore_wanted(VCHIQ_STATE_T* state); ++vchiq_platform_videocore_wanted(VCHIQ_STATE_T *state); + + extern int + vchiq_platform_use_suspend_timer(void); +@@ -114,5 +172,30 @@ + extern VCHIQ_ARM_STATE_T* + vchiq_platform_get_arm_state(VCHIQ_STATE_T *state); + ++extern int ++vchiq_videocore_wanted(VCHIQ_STATE_T *state); ++ ++extern VCHIQ_STATUS_T ++vchiq_use_internal(VCHIQ_STATE_T *state, VCHIQ_SERVICE_T *service, ++ enum USE_TYPE_E use_type); ++extern VCHIQ_STATUS_T ++vchiq_release_internal(VCHIQ_STATE_T *state, VCHIQ_SERVICE_T *service); ++ ++void ++set_suspend_state(VCHIQ_ARM_STATE_T *arm_state, ++ enum vc_suspend_status new_state); ++ ++void ++set_resume_state(VCHIQ_ARM_STATE_T *arm_state, ++ enum vc_resume_status new_state); ++ ++void ++start_suspend_timer(VCHIQ_ARM_STATE_T *arm_state); ++ ++extern int vchiq_proc_init(void); ++extern void vchiq_proc_deinit(void); ++extern struct proc_dir_entry *vchiq_proc_top(void); ++extern struct proc_dir_entry *vchiq_clients_top(void); ++ + + #endif /* VCHIQ_ARM_H */ +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_cfg.h +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_cfg.h 2013-07-26 19:32:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_cfg.h 2013-07-26 19:36:51.000000000 +0000 +@@ -19,12 +19,14 @@ + #ifndef VCHIQ_CFG_H + #define VCHIQ_CFG_H + +-#define VCHIQ_MAGIC VCHIQ_MAKE_FOURCC('V','C','H','I') ++#define VCHIQ_MAGIC VCHIQ_MAKE_FOURCC('V', 'C', 'H', 'I') + /* The version of VCHIQ - change with any non-trivial change */ +-#define VCHIQ_VERSION 2 +-/* The minimum compatible version - update to match VCHIQ_VERSION with any incompatible change */ +-#define VCHIQ_VERSION_MIN 2 ++#define VCHIQ_VERSION 5 ++/* The minimum compatible version - update to match VCHIQ_VERSION with any ++** incompatible change */ ++#define VCHIQ_VERSION_MIN 3 + ++#define VCHIQ_MAX_STATES 1 + #define VCHIQ_MAX_SERVICES 4096 + #define VCHIQ_MAX_SLOTS 128 + #define VCHIQ_MAX_SLOTS_PER_SIDE 64 +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_connected.c +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_connected.c 2013-07-26 19:32:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_connected.c 2013-07-26 19:36:51.000000000 +0000 +@@ -12,20 +12,18 @@ + * consent. + *****************************************************************************/ + +-#include "vcos.h" + #include "vchiq_connected.h" ++#include "vchiq_core.h" + #include ++#include + + #define MAX_CALLBACKS 10 + +-static int g_connected = 0; ++static int g_connected; + static int g_num_deferred_callbacks; +-static VCHIQ_CONNECTED_CALLBACK_T g_deferred_callback[ MAX_CALLBACKS ]; +-static VCOS_ONCE_T g_once_init; +-static VCOS_MUTEX_T g_connected_mutex; +- +-extern VCOS_LOG_CAT_T vchiq_core_log_category; +-#define VCOS_LOG_CATEGORY (&vchiq_core_log_category) ++static VCHIQ_CONNECTED_CALLBACK_T g_deferred_callback[MAX_CALLBACKS]; ++static int g_once_init; ++static struct mutex g_connected_mutex; + + /**************************************************************************** + * +@@ -33,9 +31,12 @@ + * + ***************************************************************************/ + +-static void connected_init( void ) ++static void connected_init(void) + { +- vcos_mutex_create( &g_connected_mutex, "connected_mutex"); ++ if (!g_once_init) { ++ mutex_init(&g_connected_mutex); ++ g_once_init = 1; ++ } + } + + /**************************************************************************** +@@ -47,32 +48,30 @@ + * + ***************************************************************************/ + +-void vchiq_add_connected_callback( VCHIQ_CONNECTED_CALLBACK_T callback ) ++void vchiq_add_connected_callback(VCHIQ_CONNECTED_CALLBACK_T callback) + { +- vcos_once( &g_once_init, connected_init ); ++ connected_init(); ++ ++ if (mutex_lock_interruptible(&g_connected_mutex) != 0) ++ return; + +- vcos_mutex_lock( &g_connected_mutex ); ++ if (g_connected) ++ /* We're already connected. Call the callback immediately. */ + +- if ( g_connected ) +- { +- // We're already connected. Call the callback immediately. +- +- callback(); +- } +- else +- { +- if ( g_num_deferred_callbacks >= MAX_CALLBACKS ) +- { +- vcos_log_error( "There already %d callback registered - please increase MAX_CALLBACKS", +- g_num_deferred_callbacks ); +- } +- else +- { +- g_deferred_callback[ g_num_deferred_callbacks ] = callback; +- g_num_deferred_callbacks++; +- } +- } +- vcos_mutex_unlock( &g_connected_mutex ); ++ callback(); ++ else { ++ if (g_num_deferred_callbacks >= MAX_CALLBACKS) ++ vchiq_log_error(vchiq_core_log_level, ++ "There already %d callback registered - " ++ "please increase MAX_CALLBACKS", ++ g_num_deferred_callbacks); ++ else { ++ g_deferred_callback[g_num_deferred_callbacks] = ++ callback; ++ g_num_deferred_callbacks++; ++ } ++ } ++ mutex_unlock(&g_connected_mutex); + } + + /**************************************************************************** +@@ -82,20 +81,20 @@ + * + ***************************************************************************/ + +-void vchiq_call_connected_callbacks( void ) ++void vchiq_call_connected_callbacks(void) + { +- int i; ++ int i; + +- vcos_once( &g_once_init, connected_init ); ++ connected_init(); + +- vcos_mutex_lock( &g_connected_mutex ); +- for ( i = 0; i < g_num_deferred_callbacks; i++ )\ +- { +- g_deferred_callback[i](); +- } +- g_num_deferred_callbacks = 0; +- g_connected = 1; +- vcos_mutex_unlock( &g_connected_mutex ); +-} ++ if (mutex_lock_interruptible(&g_connected_mutex) != 0) ++ return; + +-EXPORT_SYMBOL( vchiq_add_connected_callback ); ++ for (i = 0; i < g_num_deferred_callbacks; i++) ++ g_deferred_callback[i](); ++ ++ g_num_deferred_callbacks = 0; ++ g_connected = 1; ++ mutex_unlock(&g_connected_mutex); ++} ++EXPORT_SYMBOL(vchiq_add_connected_callback); +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_connected.h +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_connected.h 2013-07-26 19:32:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_connected.h 2013-07-26 19:36:51.000000000 +0000 +@@ -19,14 +19,14 @@ + + /* ---- Constants and Types ---------------------------------------------- */ + +-typedef void (*VCHIQ_CONNECTED_CALLBACK_T)( void ); ++typedef void (*VCHIQ_CONNECTED_CALLBACK_T)(void); + + /* ---- Variable Externs ------------------------------------------------- */ + + /* ---- Function Prototypes ---------------------------------------------- */ + +-void vchiq_add_connected_callback( VCHIQ_CONNECTED_CALLBACK_T callback ); +-void vchiq_call_connected_callbacks( void ); ++void vchiq_add_connected_callback(VCHIQ_CONNECTED_CALLBACK_T callback); ++void vchiq_call_connected_callbacks(void); + + #endif /* VCHIQ_CONNECTED_H */ + +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_core.c +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_core.c 2013-07-26 19:32:49.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_core.c 2013-07-26 19:36:51.000000000 +0000 +@@ -20,2698 +20,3741 @@ + + #define VCHIQ_SLOT_HANDLER_STACK 8192 + ++#define HANDLE_STATE_SHIFT 12 ++ + #define SLOT_INFO_FROM_INDEX(state, index) (state->slot_info + (index)) + #define SLOT_DATA_FROM_INDEX(state, index) (state->slot_data + (index)) +-#define SLOT_INDEX_FROM_DATA(state, data) (((unsigned int)((char *)data - (char *)state->slot_data)) / VCHIQ_SLOT_SIZE) +-#define SLOT_INDEX_FROM_INFO(state, info) ((unsigned int)(info - state->slot_info)) +-#define SLOT_QUEUE_INDEX_FROM_POS(pos) ((int)((unsigned int)(pos) / VCHIQ_SLOT_SIZE)) ++#define SLOT_INDEX_FROM_DATA(state, data) \ ++ (((unsigned int)((char *)data - (char *)state->slot_data)) / \ ++ VCHIQ_SLOT_SIZE) ++#define SLOT_INDEX_FROM_INFO(state, info) \ ++ ((unsigned int)(info - state->slot_info)) ++#define SLOT_QUEUE_INDEX_FROM_POS(pos) \ ++ ((int)((unsigned int)(pos) / VCHIQ_SLOT_SIZE)) + +-#define VCOS_LOG_CATEGORY (&vchiq_core_log_category) + + #define BULK_INDEX(x) (x & (VCHIQ_NUM_SERVICE_BULKS - 1)) + + +-/* Used to check use counts allow vchiq use. */ +-extern VCHIQ_STATUS_T vchiq_check_service(VCHIQ_SERVICE_T * service); +- ++struct vchiq_open_payload { ++ int fourcc; ++ int client_id; ++ short version; ++ short version_min; ++}; + +-typedef struct bulk_waiter_struct +-{ +- VCOS_EVENT_T event; +- int actual; +-} BULK_WAITER_T; +- +-typedef struct vchiq_open_payload_struct{ +- int fourcc; +- int client_id; +- short version; +- short version_min; +-} VCHIQ_OPEN_PAYLOAD_T; +- +-vcos_static_assert(sizeof(VCHIQ_HEADER_T) == 8); /* we require this for consistency between endpoints */ +-vcos_static_assert(IS_POW2(sizeof(VCHIQ_HEADER_T))); +-vcos_static_assert(IS_POW2(VCHIQ_NUM_CURRENT_BULKS)); +-vcos_static_assert(IS_POW2(VCHIQ_NUM_SERVICE_BULKS)); +- +-VCOS_LOG_CAT_T vchiq_core_log_category; +-VCOS_LOG_CAT_T vchiq_core_msg_log_category; +-VCOS_LOG_LEVEL_T vchiq_default_core_log_level = VCOS_LOG_WARN; +-VCOS_LOG_LEVEL_T vchiq_default_core_msg_log_level = VCOS_LOG_WARN; +- +-static const char *const srvstate_names[] = +-{ +- "FREE", +- "HIDDEN", +- "LISTENING", +- "OPENING", +- "OPEN", +- "CLOSESENT", +- "CLOSING", +- "CLOSEWAIT" ++/* we require this for consistency between endpoints */ ++vchiq_static_assert(sizeof(VCHIQ_HEADER_T) == 8); ++vchiq_static_assert(IS_POW2(sizeof(VCHIQ_HEADER_T))); ++vchiq_static_assert(IS_POW2(VCHIQ_NUM_CURRENT_BULKS)); ++vchiq_static_assert(IS_POW2(VCHIQ_NUM_SERVICE_BULKS)); ++vchiq_static_assert(IS_POW2(VCHIQ_MAX_SERVICES)); ++vchiq_static_assert(VCHIQ_VERSION >= VCHIQ_VERSION_MIN); ++ ++/* Run time control of log level, based on KERN_XXX level. */ ++int vchiq_core_log_level = VCHIQ_LOG_DEFAULT; ++int vchiq_core_msg_log_level = VCHIQ_LOG_DEFAULT; ++int vchiq_sync_log_level = VCHIQ_LOG_DEFAULT; ++ ++static atomic_t pause_bulks_count = ATOMIC_INIT(0); ++ ++static DEFINE_SPINLOCK(service_spinlock); ++DEFINE_SPINLOCK(bulk_waiter_spinlock); ++DEFINE_SPINLOCK(quota_spinlock); ++ ++VCHIQ_STATE_T *vchiq_states[VCHIQ_MAX_STATES]; ++static unsigned int handle_seq; ++ ++static const char *const srvstate_names[] = { ++ "FREE", ++ "HIDDEN", ++ "LISTENING", ++ "OPENING", ++ "OPEN", ++ "OPENSYNC", ++ "CLOSESENT", ++ "CLOSERECVD", ++ "CLOSEWAIT", ++ "CLOSED" + }; + +-static const char *const reason_names[] = +-{ +- "SERVICE_OPENED", +- "SERVICE_CLOSED", +- "MESSAGE_AVAILABLE", +- "BULK_TRANSMIT_DONE", +- "BULK_RECEIVE_DONE", +- "BULK_TRANSMIT_ABORTED", +- "BULK_RECEIVE_ABORTED" ++static const char *const reason_names[] = { ++ "SERVICE_OPENED", ++ "SERVICE_CLOSED", ++ "MESSAGE_AVAILABLE", ++ "BULK_TRANSMIT_DONE", ++ "BULK_RECEIVE_DONE", ++ "BULK_TRANSMIT_ABORTED", ++ "BULK_RECEIVE_ABORTED" + }; + +-static const char *const conn_state_names[] = +-{ +- "DISCONNECTED", +- "CONNECTED", +- "PAUSING", +- "PAUSE_SENT", +- "PAUSED", +- "RESUMING" ++static const char *const conn_state_names[] = { ++ "DISCONNECTED", ++ "CONNECTING", ++ "CONNECTED", ++ "PAUSING", ++ "PAUSE_SENT", ++ "PAUSED", ++ "RESUMING" + }; + +-static const char *msg_type_str( unsigned int msg_type ) ++ ++static void ++release_message_sync(VCHIQ_STATE_T *state, VCHIQ_HEADER_T *header); ++ ++static const char *msg_type_str(unsigned int msg_type) + { +- switch (msg_type) { +- case VCHIQ_MSG_PADDING: return "PADDING"; +- case VCHIQ_MSG_CONNECT: return "CONNECT"; +- case VCHIQ_MSG_OPEN: return "OPEN"; +- case VCHIQ_MSG_OPENACK: return "OPENACK"; +- case VCHIQ_MSG_CLOSE: return "CLOSE"; +- case VCHIQ_MSG_DATA: return "DATA"; +- case VCHIQ_MSG_BULK_RX: return "BULK_RX"; +- case VCHIQ_MSG_BULK_TX: return "BULK_TX"; +- case VCHIQ_MSG_BULK_RX_DONE: return "BULK_RX_DONE"; +- case VCHIQ_MSG_BULK_TX_DONE: return "BULK_TX_DONE"; +- case VCHIQ_MSG_PAUSE: return "PAUSE"; +- case VCHIQ_MSG_RESUME: return "RESUME"; +- } +- return "???"; ++ switch (msg_type) { ++ case VCHIQ_MSG_PADDING: return "PADDING"; ++ case VCHIQ_MSG_CONNECT: return "CONNECT"; ++ case VCHIQ_MSG_OPEN: return "OPEN"; ++ case VCHIQ_MSG_OPENACK: return "OPENACK"; ++ case VCHIQ_MSG_CLOSE: return "CLOSE"; ++ case VCHIQ_MSG_DATA: return "DATA"; ++ case VCHIQ_MSG_BULK_RX: return "BULK_RX"; ++ case VCHIQ_MSG_BULK_TX: return "BULK_TX"; ++ case VCHIQ_MSG_BULK_RX_DONE: return "BULK_RX_DONE"; ++ case VCHIQ_MSG_BULK_TX_DONE: return "BULK_TX_DONE"; ++ case VCHIQ_MSG_PAUSE: return "PAUSE"; ++ case VCHIQ_MSG_RESUME: return "RESUME"; ++ case VCHIQ_MSG_REMOTE_USE: return "REMOTE_USE"; ++ case VCHIQ_MSG_REMOTE_RELEASE: return "REMOTE_RELEASE"; ++ case VCHIQ_MSG_REMOTE_USE_ACTIVE: return "REMOTE_USE_ACTIVE"; ++ } ++ return "???"; + } + + static inline void + vchiq_set_service_state(VCHIQ_SERVICE_T *service, int newstate) + { +- vcos_log_info("%d: srv:%d %s->%s", service->state->id, service->localport, +- srvstate_names[service->srvstate], +- srvstate_names[newstate]); +- service->srvstate = newstate; ++ vchiq_log_info(vchiq_core_log_level, "%d: srv:%d %s->%s", ++ service->state->id, service->localport, ++ srvstate_names[service->srvstate], ++ srvstate_names[newstate]); ++ service->srvstate = newstate; + } + +-static inline int +-is_valid_service(VCHIQ_SERVICE_T *service) ++VCHIQ_SERVICE_T * ++find_service_by_handle(VCHIQ_SERVICE_HANDLE_T handle) ++{ ++ VCHIQ_SERVICE_T *service; ++ ++ spin_lock(&service_spinlock); ++ service = handle_to_service(handle); ++ if (service && (service->srvstate != VCHIQ_SRVSTATE_FREE) && ++ (service->handle == handle)) { ++ BUG_ON(service->ref_count == 0); ++ service->ref_count++; ++ } else ++ service = NULL; ++ spin_unlock(&service_spinlock); ++ ++ if (!service) ++ vchiq_log_info(vchiq_core_log_level, ++ "Invalid service handle 0x%x", handle); ++ ++ return service; ++} ++ ++VCHIQ_SERVICE_T * ++find_service_by_port(VCHIQ_STATE_T *state, int localport) ++{ ++ VCHIQ_SERVICE_T *service = NULL; ++ if ((unsigned int)localport <= VCHIQ_PORT_MAX) { ++ spin_lock(&service_spinlock); ++ service = state->services[localport]; ++ if (service && (service->srvstate != VCHIQ_SRVSTATE_FREE)) { ++ BUG_ON(service->ref_count == 0); ++ service->ref_count++; ++ } else ++ service = NULL; ++ spin_unlock(&service_spinlock); ++ } ++ ++ if (!service) ++ vchiq_log_info(vchiq_core_log_level, ++ "Invalid port %d", localport); ++ ++ return service; ++} ++ ++VCHIQ_SERVICE_T * ++find_service_for_instance(VCHIQ_INSTANCE_T instance, ++ VCHIQ_SERVICE_HANDLE_T handle) { ++ VCHIQ_SERVICE_T *service; ++ ++ spin_lock(&service_spinlock); ++ service = handle_to_service(handle); ++ if (service && (service->srvstate != VCHIQ_SRVSTATE_FREE) && ++ (service->handle == handle) && ++ (service->instance == instance)) { ++ BUG_ON(service->ref_count == 0); ++ service->ref_count++; ++ } else ++ service = NULL; ++ spin_unlock(&service_spinlock); ++ ++ if (!service) ++ vchiq_log_info(vchiq_core_log_level, ++ "Invalid service handle 0x%x", handle); ++ ++ return service; ++} ++ ++VCHIQ_SERVICE_T * ++next_service_by_instance(VCHIQ_STATE_T *state, VCHIQ_INSTANCE_T instance, ++ int *pidx) ++{ ++ VCHIQ_SERVICE_T *service = NULL; ++ int idx = *pidx; ++ ++ spin_lock(&service_spinlock); ++ while (idx < state->unused_service) { ++ VCHIQ_SERVICE_T *srv = state->services[idx++]; ++ if (srv && (srv->srvstate != VCHIQ_SRVSTATE_FREE) && ++ (srv->instance == instance)) { ++ service = srv; ++ BUG_ON(service->ref_count == 0); ++ service->ref_count++; ++ break; ++ } ++ } ++ spin_unlock(&service_spinlock); ++ ++ *pidx = idx; ++ ++ return service; ++} ++ ++void ++lock_service(VCHIQ_SERVICE_T *service) ++{ ++ spin_lock(&service_spinlock); ++ BUG_ON(!service || (service->ref_count == 0)); ++ if (service) ++ service->ref_count++; ++ spin_unlock(&service_spinlock); ++} ++ ++void ++unlock_service(VCHIQ_SERVICE_T *service) ++{ ++ VCHIQ_STATE_T *state = service->state; ++ spin_lock(&service_spinlock); ++ BUG_ON(!service || (service->ref_count == 0)); ++ if (service && service->ref_count) { ++ service->ref_count--; ++ if (!service->ref_count) { ++ BUG_ON(service->srvstate != VCHIQ_SRVSTATE_FREE); ++ state->services[service->localport] = NULL; ++ } ++ else ++ service = NULL; ++ } ++ spin_unlock(&service_spinlock); ++ ++ kfree(service); ++} ++ ++int ++vchiq_get_client_id(VCHIQ_SERVICE_HANDLE_T handle) ++{ ++ VCHIQ_SERVICE_T *service = find_service_by_handle(handle); ++ int id; ++ ++ id = service ? service->client_id : 0; ++ if (service) ++ unlock_service(service); ++ ++ return id; ++} ++ ++void * ++vchiq_get_service_userdata(VCHIQ_SERVICE_HANDLE_T handle) ++{ ++ VCHIQ_SERVICE_T *service = handle_to_service(handle); ++ ++ return service ? service->base.userdata : NULL; ++} ++ ++int ++vchiq_get_service_fourcc(VCHIQ_SERVICE_HANDLE_T handle) ++{ ++ VCHIQ_SERVICE_T *service = handle_to_service(handle); ++ ++ return service ? service->base.fourcc : 0; ++} ++ ++static void ++mark_service_closing(VCHIQ_SERVICE_T *service) + { +- return ((service != NULL) && +- (service->srvstate != VCHIQ_SRVSTATE_FREE)); ++ VCHIQ_STATE_T *state = service->state; ++ VCHIQ_SERVICE_QUOTA_T *service_quota; ++ ++ service->closing = 1; ++ ++ /* Synchronise with other threads. */ ++ mutex_lock(&state->recycle_mutex); ++ mutex_unlock(&state->recycle_mutex); ++ mutex_lock(&state->slot_mutex); ++ mutex_unlock(&state->slot_mutex); ++ ++ /* Unblock any sending thread. */ ++ service_quota = &state->service_quotas[service->localport]; ++ up(&service_quota->quota_event); + } + + static inline VCHIQ_STATUS_T + make_service_callback(VCHIQ_SERVICE_T *service, VCHIQ_REASON_T reason, +- VCHIQ_HEADER_T *header, void *bulk_userdata) ++ VCHIQ_HEADER_T *header, void *bulk_userdata) + { +- vcos_log_trace("%d: callback:%d (%s, %x, %x)", service->state->id, +- service->localport, reason_names[reason], +- (unsigned int)header, (unsigned int)bulk_userdata); +- return service->base.callback(reason, header, &service->base, bulk_userdata); ++ vchiq_log_trace(vchiq_core_log_level, "%d: callback:%d (%s, %x, %x)", ++ service->state->id, service->localport, reason_names[reason], ++ (unsigned int)header, (unsigned int)bulk_userdata); ++ return service->base.callback(reason, header, service->handle, ++ bulk_userdata); + } + + static inline void + vchiq_set_conn_state(VCHIQ_STATE_T *state, VCHIQ_CONNSTATE_T newstate) + { +- VCHIQ_CONNSTATE_T oldstate = state->conn_state; +- vcos_log_info("%d: %s->%s", state->id, +- conn_state_names[oldstate], +- conn_state_names[newstate]); +- state->conn_state = newstate; +- vchiq_platform_conn_state_changed(state, oldstate, newstate); ++ VCHIQ_CONNSTATE_T oldstate = state->conn_state; ++ vchiq_log_info(vchiq_core_log_level, "%d: %s->%s", state->id, ++ conn_state_names[oldstate], ++ conn_state_names[newstate]); ++ state->conn_state = newstate; ++ vchiq_platform_conn_state_changed(state, oldstate, newstate); + } + + static inline void + remote_event_create(REMOTE_EVENT_T *event) + { +- event->armed = 0; +- /* Don't clear the 'fired' flag because it may already have been set by the other side */ +- vcos_event_create(event->event, "vchiq"); ++ event->armed = 0; ++ /* Don't clear the 'fired' flag because it may already have been set ++ ** by the other side. */ ++ sema_init(event->event, 0); + } + + static inline void + remote_event_destroy(REMOTE_EVENT_T *event) + { +- vcos_event_delete(event->event); ++ (void)event; + } + + static inline int + remote_event_wait(REMOTE_EVENT_T *event) + { +- if (!event->fired) +- { +- event->armed = 1; +- if (event->fired) /* Also ensures the write has completed */ +- event->armed = 0; +- else if (vcos_event_wait(event->event) != VCOS_SUCCESS) +- return 0; +- } ++ if (!event->fired) { ++ event->armed = 1; ++ dsb(); ++ if (!event->fired) { ++ if (down_interruptible(event->event) != 0) { ++ event->armed = 0; ++ return 0; ++ } ++ } ++ event->armed = 0; ++ wmb(); ++ } + +- event->fired = 0; +- return 1; ++ event->fired = 0; ++ return 1; + } + + static inline void + remote_event_signal_local(REMOTE_EVENT_T *event) + { +- event->armed = 0; +- vcos_event_signal(event->event); ++ event->armed = 0; ++ up(event->event); + } + + static inline void + remote_event_poll(REMOTE_EVENT_T *event) + { +- if (event->armed) +- remote_event_signal_local(event); ++ if (event->fired && event->armed) ++ remote_event_signal_local(event); + } + + void + remote_event_pollall(VCHIQ_STATE_T *state) + { +- remote_event_poll(&state->local->trigger); +- remote_event_poll(&state->local->recycle); ++ remote_event_poll(&state->local->sync_trigger); ++ remote_event_poll(&state->local->sync_release); ++ remote_event_poll(&state->local->trigger); ++ remote_event_poll(&state->local->recycle); + } + + /* Round up message sizes so that any space at the end of a slot is always big +- enough for a header. This relies on header size being a power of two, which +- has been verified earlier by a static assertion. */ ++** enough for a header. This relies on header size being a power of two, which ++** has been verified earlier by a static assertion. */ + + static inline unsigned int + calc_stride(unsigned int size) + { +- /* Allow room for the header */ +- size += sizeof(VCHIQ_HEADER_T); ++ /* Allow room for the header */ ++ size += sizeof(VCHIQ_HEADER_T); + +- /* Round up */ +- return (size + sizeof(VCHIQ_HEADER_T) - 1) & ~(sizeof(VCHIQ_HEADER_T) - 1); ++ /* Round up */ ++ return (size + sizeof(VCHIQ_HEADER_T) - 1) & ~(sizeof(VCHIQ_HEADER_T) ++ - 1); + } + ++/* Called by the slot handler thread */ + static VCHIQ_SERVICE_T * + get_listening_service(VCHIQ_STATE_T *state, int fourcc) + { +- int i; ++ int i; + +- vcos_assert(fourcc != VCHIQ_FOURCC_INVALID); ++ WARN_ON(fourcc == VCHIQ_FOURCC_INVALID); + +- for (i = 0; i < state->unused_service; i++) +- { +- VCHIQ_SERVICE_T *service = state->services[i]; +- if (service && +- (service->public_fourcc == fourcc) && +- ((service->srvstate == VCHIQ_SRVSTATE_LISTENING) || +- ((service->srvstate == VCHIQ_SRVSTATE_OPEN) && +- (service->remoteport == VCHIQ_PORT_FREE)))) +- return service; +- } ++ for (i = 0; i < state->unused_service; i++) { ++ VCHIQ_SERVICE_T *service = state->services[i]; ++ if (service && ++ (service->public_fourcc == fourcc) && ++ ((service->srvstate == VCHIQ_SRVSTATE_LISTENING) || ++ ((service->srvstate == VCHIQ_SRVSTATE_OPEN) && ++ (service->remoteport == VCHIQ_PORT_FREE)))) { ++ lock_service(service); ++ return service; ++ } ++ } + +- return NULL; ++ return NULL; + } + ++/* Called by the slot handler thread */ + static VCHIQ_SERVICE_T * + get_connected_service(VCHIQ_STATE_T *state, unsigned int port) + { +- int i; +- for (i = 0; i < state->unused_service; i++) { +- VCHIQ_SERVICE_T *service = state->services[i]; +- if (service && (service->srvstate == VCHIQ_SRVSTATE_OPEN) +- && (service->remoteport == port)) { +- return service; +- } +- } +- return NULL; ++ int i; ++ for (i = 0; i < state->unused_service; i++) { ++ VCHIQ_SERVICE_T *service = state->services[i]; ++ if (service && (service->srvstate == VCHIQ_SRVSTATE_OPEN) ++ && (service->remoteport == port)) { ++ lock_service(service); ++ return service; ++ } ++ } ++ return NULL; + } + +-static inline void ++inline void + request_poll(VCHIQ_STATE_T *state, VCHIQ_SERVICE_T *service, int poll_type) + { +- if (service) +- { +- vcos_atomic_flags_or(&service->poll_flags, (1 << poll_type)); +- vcos_atomic_flags_or(&state->poll_services[service->localport>>5], +- (1 <<(service->localport & 0x1f))); +- } ++ uint32_t value; ++ ++ if (service) { ++ do { ++ value = atomic_read(&service->poll_flags); ++ } while (atomic_cmpxchg(&service->poll_flags, value, ++ value | (1 << poll_type)) != value); ++ ++ do { ++ value = atomic_read(&state->poll_services[ ++ service->localport>>5]); ++ } while (atomic_cmpxchg( ++ &state->poll_services[service->localport>>5], ++ value, value | (1 << (service->localport & 0x1f))) ++ != value); ++ } + +- state->poll_needed = 1; +- vcos_wmb(&state->poll_needed); ++ state->poll_needed = 1; ++ wmb(); + +- /* ... and ensure the slot handler runs. */ +- remote_event_signal_local(&state->local->trigger); ++ /* ... and ensure the slot handler runs. */ ++ remote_event_signal_local(&state->local->trigger); + } + + /* Called from queue_message, by the slot handler and application threads, +- with slot_mutex held */ ++** with slot_mutex held */ + static VCHIQ_HEADER_T * + reserve_space(VCHIQ_STATE_T *state, int space, int is_blocking) + { +- VCHIQ_SHARED_STATE_T *local = state->local; +- int tx_pos = state->local_tx_pos; +- int slot_space = VCHIQ_SLOT_SIZE - (tx_pos & VCHIQ_SLOT_MASK); +- +- if (space > slot_space) { +- VCHIQ_HEADER_T *header; +- /* Fill the remaining space with padding */ +- vcos_assert(state->tx_data != NULL); +- header = (VCHIQ_HEADER_T *) (state->tx_data + (tx_pos & VCHIQ_SLOT_MASK)); +- header->msgid = VCHIQ_MSGID_PADDING; +- header->size = slot_space - sizeof(VCHIQ_HEADER_T); +- +- tx_pos += slot_space; +- } +- +- /* If necessary, get the next slot. */ +- if ((tx_pos & VCHIQ_SLOT_MASK) == 0) +- { +- int slot_index; +- +- /* If there is no free slot... */ +- if (tx_pos == (state->slot_queue_available * VCHIQ_SLOT_SIZE)) +- { +- /* ...wait for one. */ +- VCHIQ_STATS_INC(state, slot_stalls); +- +- /* But first, flush through the last slot. */ +- local->tx_pos = tx_pos; +- remote_event_signal(&state->remote->trigger); +- +- do { +- if (!is_blocking || +- (vcos_event_wait(&state->slot_available_event) != VCOS_SUCCESS)) +- { +- return NULL; /* No space available now */ +- } +- } +- while (tx_pos == (state->slot_queue_available * VCHIQ_SLOT_SIZE)); +- } +- +- slot_index = local->slot_queue[SLOT_QUEUE_INDEX_FROM_POS(tx_pos) & VCHIQ_SLOT_QUEUE_MASK]; +- state->tx_data = (char *)SLOT_DATA_FROM_INDEX(state, slot_index); +- } ++ VCHIQ_SHARED_STATE_T *local = state->local; ++ int tx_pos = state->local_tx_pos; ++ int slot_space = VCHIQ_SLOT_SIZE - (tx_pos & VCHIQ_SLOT_MASK); ++ ++ if (space > slot_space) { ++ VCHIQ_HEADER_T *header; ++ /* Fill the remaining space with padding */ ++ WARN_ON(state->tx_data == NULL); ++ header = (VCHIQ_HEADER_T *) ++ (state->tx_data + (tx_pos & VCHIQ_SLOT_MASK)); ++ header->msgid = VCHIQ_MSGID_PADDING; ++ header->size = slot_space - sizeof(VCHIQ_HEADER_T); ++ ++ tx_pos += slot_space; ++ } ++ ++ /* If necessary, get the next slot. */ ++ if ((tx_pos & VCHIQ_SLOT_MASK) == 0) { ++ int slot_index; + +- state->local_tx_pos = tx_pos + space; ++ /* If there is no free slot... */ + +- return (VCHIQ_HEADER_T *)(state->tx_data + (tx_pos & VCHIQ_SLOT_MASK)); ++ if (down_trylock(&state->slot_available_event) != 0) { ++ /* ...wait for one. */ ++ ++ VCHIQ_STATS_INC(state, slot_stalls); ++ ++ /* But first, flush through the last slot. */ ++ state->local_tx_pos = tx_pos; ++ local->tx_pos = tx_pos; ++ remote_event_signal(&state->remote->trigger); ++ ++ if (!is_blocking || ++ (down_interruptible( ++ &state->slot_available_event) != 0)) ++ return NULL; /* No space available */ ++ } ++ ++ BUG_ON(tx_pos == ++ (state->slot_queue_available * VCHIQ_SLOT_SIZE)); ++ ++ slot_index = local->slot_queue[ ++ SLOT_QUEUE_INDEX_FROM_POS(tx_pos) & ++ VCHIQ_SLOT_QUEUE_MASK]; ++ state->tx_data = ++ (char *)SLOT_DATA_FROM_INDEX(state, slot_index); ++ } ++ ++ state->local_tx_pos = tx_pos + space; ++ ++ return (VCHIQ_HEADER_T *)(state->tx_data + (tx_pos & VCHIQ_SLOT_MASK)); + } + +-/* Called with slot_mutex held */ ++/* Called by the recycle thread. */ + static void + process_free_queue(VCHIQ_STATE_T *state) + { +- VCHIQ_SHARED_STATE_T *local = state->local; +- BITSET_T service_found[BITSET_SIZE(VCHIQ_MAX_SERVICES)]; +- int slot_queue_available; +- +- /* Use a read memory barrier to ensure that any state that may have +- been modified by another thread is not masked by stale prefetched +- values. */ +- vcos_rmb(); +- +- /* Find slots which have been freed by the other side, and return them to +- the available queue. */ +- slot_queue_available = state->slot_queue_available; +- +- while (slot_queue_available != local->slot_queue_recycle) +- { +- unsigned int pos; +- int slot_index = local->slot_queue[slot_queue_available++ & VCHIQ_SLOT_QUEUE_MASK]; +- char *data = (char *)SLOT_DATA_FROM_INDEX(state, slot_index); +- +- vcos_log_trace("%d: pfq %d=%x %x %x", state->id, slot_index, +- (unsigned int)data, local->slot_queue_recycle, +- slot_queue_available); +- +- /* Initialise the bitmask for services which have used this slot */ +- BITSET_ZERO(service_found); +- +- pos = 0; +- +- while (pos < VCHIQ_SLOT_SIZE) +- { +- VCHIQ_HEADER_T *header = (VCHIQ_HEADER_T *)(data + pos); +- int msgid = header->msgid; +- if (VCHIQ_MSG_TYPE(msgid) == VCHIQ_MSG_DATA) +- { +- int port = VCHIQ_MSG_SRCPORT(msgid); +- VCHIQ_SERVICE_QUOTA_T *service_quota = +- &state->service_quotas[port]; +- int count; +- count = service_quota->message_use_count; +- if (count > 0) +- { +- service_quota->message_use_count = count - 1; +- if (count == service_quota->message_quota) +- { +- /* Signal the service that it has dropped below its quota */ +- vcos_event_signal(&service_quota->quota_event); +- } +- } +- else +- { +- vcos_log_error("service %d message_use_count=%d (header %x," +- " msgid %x, header->msgid %x, header->size %x)", +- port, service_quota->message_use_count, +- (unsigned int)header, msgid, header->msgid, +- header->size); +- vcos_assert(0); +- } +- if (!BITSET_IS_SET(service_found, port)) +- { +- /* Set the found bit for this service */ +- BITSET_SET(service_found, port); +- +- count = service_quota->slot_use_count; +- if (count > 0) +- { +- service_quota->slot_use_count = count - 1; +- /* Signal the service in case it has dropped below its quota */ +- vcos_event_signal(&service_quota->quota_event); +- vcos_log_trace("%d: pfq:%d %x@%x - slot_use->%d", +- state->id, port, +- header->size, (unsigned int)header, +- service_quota->slot_use_count); +- } +- else +- { +- vcos_log_error("service %d slot_use_count=%d (header %x," +- " msgid %x, header->msgid %x, header->size %x)", +- port, service_quota->slot_use_count, +- (unsigned int)header, msgid, header->msgid, +- header->size); +- vcos_assert(0); +- } +- } +- } +- +- pos += calc_stride(header->size); +- if (pos > VCHIQ_SLOT_SIZE) +- { +- vcos_log_error("pfq - pos %x: header %x, msgid %x, header->msgid %x, header->size %x", +- pos, (unsigned int)header, msgid, header->msgid, header->size); +- vcos_assert(0); +- } +- } +- } +- +- if (slot_queue_available != state->slot_queue_available) +- { +- state->slot_queue_available = slot_queue_available; +- vcos_wmb(&state->slot_queue_available); +- vcos_event_signal(&state->slot_available_event); +- } ++ VCHIQ_SHARED_STATE_T *local = state->local; ++ BITSET_T service_found[BITSET_SIZE(VCHIQ_MAX_SERVICES)]; ++ int slot_queue_available; ++ ++ /* Use a read memory barrier to ensure that any state that may have ++ ** been modified by another thread is not masked by stale prefetched ++ ** values. */ ++ rmb(); ++ ++ /* Find slots which have been freed by the other side, and return them ++ ** to the available queue. */ ++ slot_queue_available = state->slot_queue_available; ++ ++ while (slot_queue_available != local->slot_queue_recycle) { ++ unsigned int pos; ++ int slot_index = local->slot_queue[slot_queue_available++ & ++ VCHIQ_SLOT_QUEUE_MASK]; ++ char *data = (char *)SLOT_DATA_FROM_INDEX(state, slot_index); ++ int data_found = 0; ++ ++ vchiq_log_trace(vchiq_core_log_level, "%d: pfq %d=%x %x %x", ++ state->id, slot_index, (unsigned int)data, ++ local->slot_queue_recycle, slot_queue_available); ++ ++ /* Initialise the bitmask for services which have used this ++ ** slot */ ++ BITSET_ZERO(service_found); ++ ++ pos = 0; ++ ++ while (pos < VCHIQ_SLOT_SIZE) { ++ VCHIQ_HEADER_T *header = ++ (VCHIQ_HEADER_T *)(data + pos); ++ int msgid = header->msgid; ++ if (VCHIQ_MSG_TYPE(msgid) == VCHIQ_MSG_DATA) { ++ int port = VCHIQ_MSG_SRCPORT(msgid); ++ VCHIQ_SERVICE_QUOTA_T *service_quota = ++ &state->service_quotas[port]; ++ int count; ++ spin_lock("a_spinlock); ++ count = service_quota->message_use_count; ++ if (count > 0) ++ service_quota->message_use_count = ++ count - 1; ++ spin_unlock("a_spinlock); ++ ++ if (count == service_quota->message_quota) ++ /* Signal the service that it ++ ** has dropped below its quota ++ */ ++ up(&service_quota->quota_event); ++ else if (count == 0) { ++ vchiq_log_error(vchiq_core_log_level, ++ "service %d " ++ "message_use_count=%d " ++ "(header %x, msgid %x, " ++ "header->msgid %x, " ++ "header->size %x)", ++ port, ++ service_quota-> ++ message_use_count, ++ (unsigned int)header, msgid, ++ header->msgid, ++ header->size); ++ WARN(1, "invalid message use count\n"); ++ } ++ if (!BITSET_IS_SET(service_found, port)) { ++ /* Set the found bit for this service */ ++ BITSET_SET(service_found, port); ++ ++ spin_lock("a_spinlock); ++ count = service_quota->slot_use_count; ++ if (count > 0) ++ service_quota->slot_use_count = ++ count - 1; ++ spin_unlock("a_spinlock); ++ ++ if (count > 0) { ++ /* Signal the service in case ++ ** it has dropped below its ++ ** quota */ ++ up(&service_quota->quota_event); ++ vchiq_log_trace( ++ vchiq_core_log_level, ++ "%d: pfq:%d %x@%x - " ++ "slot_use->%d", ++ state->id, port, ++ header->size, ++ (unsigned int)header, ++ count - 1); ++ } else { ++ vchiq_log_error( ++ vchiq_core_log_level, ++ "service %d " ++ "slot_use_count" ++ "=%d (header %x" ++ ", msgid %x, " ++ "header->msgid" ++ " %x, header->" ++ "size %x)", ++ port, count, ++ (unsigned int)header, ++ msgid, ++ header->msgid, ++ header->size); ++ WARN(1, "bad slot use count\n"); ++ } ++ } ++ ++ data_found = 1; ++ } ++ ++ pos += calc_stride(header->size); ++ if (pos > VCHIQ_SLOT_SIZE) { ++ vchiq_log_error(vchiq_core_log_level, ++ "pfq - pos %x: header %x, msgid %x, " ++ "header->msgid %x, header->size %x", ++ pos, (unsigned int)header, msgid, ++ header->msgid, header->size); ++ WARN(1, "invalid slot position\n"); ++ } ++ } ++ ++ if (data_found) { ++ int count; ++ spin_lock("a_spinlock); ++ count = state->data_use_count; ++ if (count > 0) ++ state->data_use_count = ++ count - 1; ++ spin_unlock("a_spinlock); ++ if (count == state->data_quota) ++ up(&state->data_quota_event); ++ } ++ ++ state->slot_queue_available = slot_queue_available; ++ up(&state->slot_available_event); ++ } + } + + /* Called by the slot handler and application threads */ + static VCHIQ_STATUS_T + queue_message(VCHIQ_STATE_T *state, VCHIQ_SERVICE_T *service, +- int msgid, const VCHIQ_ELEMENT_T *elements, +- int count, int size, int is_blocking) ++ int msgid, const VCHIQ_ELEMENT_T *elements, ++ int count, int size, int is_blocking) + { +- VCHIQ_SHARED_STATE_T *local; +- VCHIQ_SERVICE_QUOTA_T *service_quota = NULL; +- VCHIQ_HEADER_T *header; +- +- unsigned int stride; +- +- local = state->local; +- +- stride = calc_stride(size); +- +- vcos_assert(stride <= VCHIQ_SLOT_SIZE); +- +- /* On platforms where vcos_mutex_lock cannot fail, the return will never +- be taken and the compiler may optimise out that code. Let Coverity +- know this is intentional. +- */ +- /* coverity[constant_expression_result] */ +- if ((VCHIQ_MSG_TYPE(msgid) != VCHIQ_MSG_RESUME) && +- (vcos_mutex_lock(&state->slot_mutex) != VCOS_SUCCESS)) +- return VCHIQ_RETRY; +- +- if (service) +- { +- int tx_end_index = SLOT_QUEUE_INDEX_FROM_POS(state->local_tx_pos + stride - 1); +- +- if (service->srvstate != VCHIQ_SRVSTATE_OPEN) +- { +- /* The service has been closed, probably while waiting for the mutex */ +- vcos_mutex_unlock(&state->slot_mutex); +- return VCHIQ_ERROR; +- } +- +- service_quota = &state->service_quotas[service->localport]; +- +- /* ...ensure it doesn't use more than its quota of messages or slots */ +- while ((service_quota->message_use_count == service_quota->message_quota) || +- ((tx_end_index != service_quota->previous_tx_index) && +- (service_quota->slot_use_count == service_quota->slot_quota))) +- { +- vcos_log_trace("%d: qm:%d %s,%x - quota stall (msg %d, slot %d)", +- state->id, service->localport, +- msg_type_str(VCHIQ_MSG_TYPE(msgid)), size, +- service_quota->message_use_count, service_quota->slot_use_count); +- VCHIQ_SERVICE_STATS_INC(service, quota_stalls); +- vcos_mutex_unlock(&state->slot_mutex); +- if (vcos_event_wait(&service_quota->quota_event) != VCOS_SUCCESS) +- return VCHIQ_RETRY; +- if (vcos_mutex_lock(&state->slot_mutex) != VCOS_SUCCESS) +- return VCHIQ_RETRY; +- tx_end_index = SLOT_QUEUE_INDEX_FROM_POS(state->local_tx_pos + stride - 1); +- } +- } +- +- header = reserve_space(state, stride, is_blocking); +- +- if (!header) { +- if (service) +- VCHIQ_SERVICE_STATS_INC(service, slot_stalls); +- vcos_mutex_unlock(&state->slot_mutex); +- return VCHIQ_RETRY; +- } +- +- if (service) { +- int i, pos; +- int tx_end_index; +- +- vcos_log_info("%d: qm %s@%x,%x (%d->%d)", state->id, +- msg_type_str(VCHIQ_MSG_TYPE(msgid)), +- (unsigned int)header, size, +- VCHIQ_MSG_SRCPORT(msgid), +- VCHIQ_MSG_DSTPORT(msgid)); +- +- for (i = 0, pos = 0; i < (unsigned int)count; +- pos += elements[i++].size) +- if (elements[i].size) { +- if (vchiq_copy_from_user +- (header->data + pos, elements[i].data, +- (size_t) elements[i].size) != +- VCHIQ_SUCCESS) { +- vcos_mutex_unlock(&state->slot_mutex); +- VCHIQ_SERVICE_STATS_INC(service, error_count); +- return VCHIQ_ERROR; +- } +- if (i == 0) { +- vcos_log_dump_mem( &vchiq_core_msg_log_category, +- "Sent", 0, header->data + pos, +- vcos_min( 64, elements[0].size )); +- } +- } +- +- /* If this transmission can't fit in the last slot used by this service... */ +- tx_end_index = SLOT_QUEUE_INDEX_FROM_POS(state->local_tx_pos - 1); +- if (tx_end_index != service_quota->previous_tx_index) +- { +- service_quota->slot_use_count++; +- vcos_log_trace("%d: qm:%d %s,%x - slot_use->%d", +- state->id, service->localport, +- msg_type_str(VCHIQ_MSG_TYPE(msgid)), size, +- service_quota->slot_use_count); +- } +- +- service_quota->previous_tx_index = tx_end_index; +- service_quota->message_use_count++; +- VCHIQ_SERVICE_STATS_INC(service, ctrl_tx_count); +- VCHIQ_SERVICE_STATS_ADD(service, ctrl_tx_bytes, size); +- } else { +- vcos_log_info("%d: qm %s@%x,%x (%d->%d)", state->id, +- msg_type_str(VCHIQ_MSG_TYPE(msgid)), +- (unsigned int)header, size, +- VCHIQ_MSG_SRCPORT(msgid), +- VCHIQ_MSG_DSTPORT(msgid)); +- if (size != 0) +- { +- vcos_assert((count == 1) && (size == elements[0].size)); +- memcpy(header->data, elements[0].data, elements[0].size); +- } +- VCHIQ_STATS_INC(state, ctrl_tx_count); +- } +- +- header->msgid = msgid; +- header->size = size; +- +- if (vcos_is_log_enabled( &vchiq_core_msg_log_category, VCOS_LOG_INFO)) +- { +- int svc_fourcc; +- +- svc_fourcc = service +- ? service->base.fourcc +- : VCHIQ_MAKE_FOURCC('?','?','?','?'); +- +- vcos_log_impl( &vchiq_core_msg_log_category, +- VCOS_LOG_INFO, +- "Sent Msg %s(%u) to %c%c%c%c s:%u d:%d len:%d", +- msg_type_str(VCHIQ_MSG_TYPE(msgid)), +- VCHIQ_MSG_TYPE(msgid), +- VCHIQ_FOURCC_AS_4CHARS(svc_fourcc), +- VCHIQ_MSG_SRCPORT(msgid), +- VCHIQ_MSG_DSTPORT(msgid), +- size ); +- } +- +- /* Make the new tx_pos visible to the peer. */ +- local->tx_pos = state->local_tx_pos; +- vcos_wmb(&local->tx_pos); ++ VCHIQ_SHARED_STATE_T *local; ++ VCHIQ_SERVICE_QUOTA_T *service_quota = NULL; ++ VCHIQ_HEADER_T *header; ++ int type = VCHIQ_MSG_TYPE(msgid); ++ ++ unsigned int stride; ++ ++ local = state->local; ++ ++ stride = calc_stride(size); ++ ++ WARN_ON(!(stride <= VCHIQ_SLOT_SIZE)); ++ ++ if ((type != VCHIQ_MSG_RESUME) && ++ (mutex_lock_interruptible(&state->slot_mutex) != 0)) ++ return VCHIQ_RETRY; ++ ++ if (type == VCHIQ_MSG_DATA) { ++ int tx_end_index; ++ ++ BUG_ON(!service); ++ ++ if (service->closing) { ++ /* The service has been closed */ ++ mutex_unlock(&state->slot_mutex); ++ return VCHIQ_ERROR; ++ } ++ ++ service_quota = &state->service_quotas[service->localport]; ++ ++ spin_lock("a_spinlock); ++ ++ /* Ensure this service doesn't use more than its quota of ++ ** messages or slots */ ++ tx_end_index = SLOT_QUEUE_INDEX_FROM_POS( ++ state->local_tx_pos + stride - 1); ++ ++ /* Ensure data messages don't use more than their quota of ++ ** slots */ ++ while ((tx_end_index != state->previous_data_index) && ++ (state->data_use_count == state->data_quota)) { ++ VCHIQ_STATS_INC(state, data_stalls); ++ spin_unlock("a_spinlock); ++ mutex_unlock(&state->slot_mutex); ++ ++ if (down_interruptible(&state->data_quota_event) ++ != 0) ++ return VCHIQ_RETRY; ++ ++ mutex_lock(&state->slot_mutex); ++ spin_lock("a_spinlock); ++ tx_end_index = SLOT_QUEUE_INDEX_FROM_POS( ++ state->local_tx_pos + stride - 1); ++ if ((tx_end_index == state->previous_data_index) || ++ (state->data_use_count < state->data_quota)) { ++ /* Pass the signal on to other waiters */ ++ up(&state->data_quota_event); ++ break; ++ } ++ } ++ ++ while ((service_quota->message_use_count == ++ service_quota->message_quota) || ++ ((tx_end_index != service_quota->previous_tx_index) && ++ (service_quota->slot_use_count == ++ service_quota->slot_quota))) { ++ spin_unlock("a_spinlock); ++ vchiq_log_trace(vchiq_core_log_level, ++ "%d: qm:%d %s,%x - quota stall " ++ "(msg %d, slot %d)", ++ state->id, service->localport, ++ msg_type_str(type), size, ++ service_quota->message_use_count, ++ service_quota->slot_use_count); ++ VCHIQ_SERVICE_STATS_INC(service, quota_stalls); ++ mutex_unlock(&state->slot_mutex); ++ if (down_interruptible(&service_quota->quota_event) ++ != 0) ++ return VCHIQ_RETRY; ++ if (service->closing) ++ return VCHIQ_ERROR; ++ if (mutex_lock_interruptible(&state->slot_mutex) != 0) ++ return VCHIQ_RETRY; ++ if (service->srvstate != VCHIQ_SRVSTATE_OPEN) { ++ /* The service has been closed */ ++ mutex_unlock(&state->slot_mutex); ++ return VCHIQ_ERROR; ++ } ++ spin_lock("a_spinlock); ++ tx_end_index = SLOT_QUEUE_INDEX_FROM_POS( ++ state->local_tx_pos + stride - 1); ++ } ++ ++ spin_unlock("a_spinlock); ++ } ++ ++ header = reserve_space(state, stride, is_blocking); ++ ++ if (!header) { ++ if (service) ++ VCHIQ_SERVICE_STATS_INC(service, slot_stalls); ++ mutex_unlock(&state->slot_mutex); ++ return VCHIQ_RETRY; ++ } ++ ++ if (type == VCHIQ_MSG_DATA) { ++ int i, pos; ++ int tx_end_index; ++ int slot_use_count; ++ ++ vchiq_log_info(vchiq_core_log_level, ++ "%d: qm %s@%x,%x (%d->%d)", ++ state->id, ++ msg_type_str(VCHIQ_MSG_TYPE(msgid)), ++ (unsigned int)header, size, ++ VCHIQ_MSG_SRCPORT(msgid), ++ VCHIQ_MSG_DSTPORT(msgid)); ++ ++ BUG_ON(!service); ++ ++ for (i = 0, pos = 0; i < (unsigned int)count; ++ pos += elements[i++].size) ++ if (elements[i].size) { ++ if (vchiq_copy_from_user ++ (header->data + pos, elements[i].data, ++ (size_t) elements[i].size) != ++ VCHIQ_SUCCESS) { ++ mutex_unlock(&state->slot_mutex); ++ VCHIQ_SERVICE_STATS_INC(service, ++ error_count); ++ return VCHIQ_ERROR; ++ } ++ if (i == 0) { ++ if (vchiq_core_msg_log_level >= ++ VCHIQ_LOG_INFO) ++ vchiq_log_dump_mem("Sent", 0, ++ header->data + pos, ++ min(64, ++ elements[0].size)); ++ } ++ } ++ ++ spin_lock("a_spinlock); ++ service_quota->message_use_count++; ++ ++ tx_end_index = ++ SLOT_QUEUE_INDEX_FROM_POS(state->local_tx_pos - 1); ++ ++ /* If this transmission can't fit in the last slot used by any ++ ** service, the data_use_count must be increased. */ ++ if (tx_end_index != state->previous_data_index) { ++ state->previous_data_index = tx_end_index; ++ state->data_use_count++; ++ } ++ ++ /* If this isn't the same slot last used by this service, ++ ** the service's slot_use_count must be increased. */ ++ if (tx_end_index != service_quota->previous_tx_index) { ++ service_quota->previous_tx_index = tx_end_index; ++ slot_use_count = ++service_quota->slot_use_count; ++ } else { ++ slot_use_count = 0; ++ } ++ ++ spin_unlock("a_spinlock); ++ ++ if (slot_use_count) ++ vchiq_log_trace(vchiq_core_log_level, ++ "%d: qm:%d %s,%x - slot_use->%d (hdr %p)", ++ state->id, service->localport, ++ msg_type_str(VCHIQ_MSG_TYPE(msgid)), size, ++ slot_use_count, header); ++ ++ VCHIQ_SERVICE_STATS_INC(service, ctrl_tx_count); ++ VCHIQ_SERVICE_STATS_ADD(service, ctrl_tx_bytes, size); ++ } else { ++ vchiq_log_info(vchiq_core_log_level, ++ "%d: qm %s@%x,%x (%d->%d)", state->id, ++ msg_type_str(VCHIQ_MSG_TYPE(msgid)), ++ (unsigned int)header, size, ++ VCHIQ_MSG_SRCPORT(msgid), ++ VCHIQ_MSG_DSTPORT(msgid)); ++ if (size != 0) { ++ WARN_ON(!((count == 1) && (size == elements[0].size))); ++ memcpy(header->data, elements[0].data, ++ elements[0].size); ++ } ++ VCHIQ_STATS_INC(state, ctrl_tx_count); ++ } ++ ++ header->msgid = msgid; ++ header->size = size; ++ ++ { ++ int svc_fourcc; ++ ++ svc_fourcc = service ++ ? service->base.fourcc ++ : VCHIQ_MAKE_FOURCC('?', '?', '?', '?'); ++ ++ vchiq_log_info(vchiq_core_msg_log_level, ++ "Sent Msg %s(%u) to %c%c%c%c s:%u d:%d len:%d", ++ msg_type_str(VCHIQ_MSG_TYPE(msgid)), ++ VCHIQ_MSG_TYPE(msgid), ++ VCHIQ_FOURCC_AS_4CHARS(svc_fourcc), ++ VCHIQ_MSG_SRCPORT(msgid), ++ VCHIQ_MSG_DSTPORT(msgid), ++ size); ++ } ++ ++ /* Make sure the new header is visible to the peer. */ ++ wmb(); ++ ++ /* Make the new tx_pos visible to the peer. */ ++ local->tx_pos = state->local_tx_pos; ++ wmb(); ++ ++ if (service && (type == VCHIQ_MSG_CLOSE)) ++ vchiq_set_service_state(service, VCHIQ_SRVSTATE_CLOSESENT); + +- if (VCHIQ_MSG_TYPE(msgid) != VCHIQ_MSG_PAUSE) +- vcos_mutex_unlock(&state->slot_mutex); ++ if (VCHIQ_MSG_TYPE(msgid) != VCHIQ_MSG_PAUSE) ++ mutex_unlock(&state->slot_mutex); + +- remote_event_signal(&state->remote->trigger); ++ remote_event_signal(&state->remote->trigger); + +- return VCHIQ_SUCCESS; ++ return VCHIQ_SUCCESS; ++} ++ ++/* Called by the slot handler and application threads */ ++static VCHIQ_STATUS_T ++queue_message_sync(VCHIQ_STATE_T *state, VCHIQ_SERVICE_T *service, ++ int msgid, const VCHIQ_ELEMENT_T *elements, ++ int count, int size, int is_blocking) ++{ ++ VCHIQ_SHARED_STATE_T *local; ++ VCHIQ_HEADER_T *header; ++ ++ local = state->local; ++ ++ if ((VCHIQ_MSG_TYPE(msgid) != VCHIQ_MSG_RESUME) && ++ (mutex_lock_interruptible(&state->sync_mutex) != 0)) ++ return VCHIQ_RETRY; ++ ++ remote_event_wait(&local->sync_release); ++ ++ rmb(); ++ ++ header = (VCHIQ_HEADER_T *)SLOT_DATA_FROM_INDEX(state, ++ local->slot_sync); ++ ++ { ++ int oldmsgid = header->msgid; ++ if (oldmsgid != VCHIQ_MSGID_PADDING) ++ vchiq_log_error(vchiq_core_log_level, ++ "%d: qms - msgid %x, not PADDING", ++ state->id, oldmsgid); ++ } ++ ++ if (service) { ++ int i, pos; ++ ++ vchiq_log_info(vchiq_sync_log_level, ++ "%d: qms %s@%x,%x (%d->%d)", state->id, ++ msg_type_str(VCHIQ_MSG_TYPE(msgid)), ++ (unsigned int)header, size, ++ VCHIQ_MSG_SRCPORT(msgid), ++ VCHIQ_MSG_DSTPORT(msgid)); ++ ++ for (i = 0, pos = 0; i < (unsigned int)count; ++ pos += elements[i++].size) ++ if (elements[i].size) { ++ if (vchiq_copy_from_user ++ (header->data + pos, elements[i].data, ++ (size_t) elements[i].size) != ++ VCHIQ_SUCCESS) { ++ mutex_unlock(&state->sync_mutex); ++ VCHIQ_SERVICE_STATS_INC(service, ++ error_count); ++ return VCHIQ_ERROR; ++ } ++ if (i == 0) { ++ if (vchiq_sync_log_level >= ++ VCHIQ_LOG_TRACE) ++ vchiq_log_dump_mem("Sent Sync", ++ 0, header->data + pos, ++ min(64, ++ elements[0].size)); ++ } ++ } ++ ++ VCHIQ_SERVICE_STATS_INC(service, ctrl_tx_count); ++ VCHIQ_SERVICE_STATS_ADD(service, ctrl_tx_bytes, size); ++ } else { ++ vchiq_log_info(vchiq_sync_log_level, ++ "%d: qms %s@%x,%x (%d->%d)", state->id, ++ msg_type_str(VCHIQ_MSG_TYPE(msgid)), ++ (unsigned int)header, size, ++ VCHIQ_MSG_SRCPORT(msgid), ++ VCHIQ_MSG_DSTPORT(msgid)); ++ if (size != 0) { ++ WARN_ON(!((count == 1) && (size == elements[0].size))); ++ memcpy(header->data, elements[0].data, ++ elements[0].size); ++ } ++ VCHIQ_STATS_INC(state, ctrl_tx_count); ++ } ++ ++ header->size = size; ++ header->msgid = msgid; ++ ++ if (vchiq_sync_log_level >= VCHIQ_LOG_TRACE) { ++ int svc_fourcc; ++ ++ svc_fourcc = service ++ ? service->base.fourcc ++ : VCHIQ_MAKE_FOURCC('?', '?', '?', '?'); ++ ++ vchiq_log_trace(vchiq_sync_log_level, ++ "Sent Sync Msg %s(%u) to %c%c%c%c s:%u d:%d len:%d", ++ msg_type_str(VCHIQ_MSG_TYPE(msgid)), ++ VCHIQ_MSG_TYPE(msgid), ++ VCHIQ_FOURCC_AS_4CHARS(svc_fourcc), ++ VCHIQ_MSG_SRCPORT(msgid), ++ VCHIQ_MSG_DSTPORT(msgid), ++ size); ++ } ++ ++ /* Make sure the new header is visible to the peer. */ ++ wmb(); ++ ++ remote_event_signal(&state->remote->sync_trigger); ++ ++ if (VCHIQ_MSG_TYPE(msgid) != VCHIQ_MSG_PAUSE) ++ mutex_unlock(&state->sync_mutex); ++ ++ return VCHIQ_SUCCESS; + } + + static inline void + claim_slot(VCHIQ_SLOT_INFO_T *slot) + { +- slot->use_count++; ++ slot->use_count++; + } + + static void +-release_slot(VCHIQ_STATE_T *state, VCHIQ_SLOT_INFO_T *slot_info) ++release_slot(VCHIQ_STATE_T *state, VCHIQ_SLOT_INFO_T *slot_info, ++ VCHIQ_HEADER_T *header, VCHIQ_SERVICE_T *service) + { +- int release_count; +- vcos_mutex_lock(&state->recycle_mutex); ++ int release_count; + +- release_count = slot_info->release_count; +- slot_info->release_count = ++release_count; ++ mutex_lock(&state->recycle_mutex); + +- if (release_count == slot_info->use_count) +- { +- int slot_queue_recycle; +- /* Add to the freed queue */ +- +- /* A read barrier is necessary here to prevent speculative fetches of +- remote->slot_queue_recycle from overtaking the mutex. */ +- vcos_rmb(); +- +- slot_queue_recycle = state->remote->slot_queue_recycle; +- state->remote->slot_queue[slot_queue_recycle & VCHIQ_SLOT_QUEUE_MASK] = +- SLOT_INDEX_FROM_INFO(state, slot_info); +- state->remote->slot_queue_recycle = slot_queue_recycle + 1; +- vcos_log_info("%d: release_slot %d - recycle->%x", +- state->id, SLOT_INDEX_FROM_INFO(state, slot_info), +- state->remote->slot_queue_recycle); +- +- /* A write barrier is necessary, but remote_event_signal contains one. */ +- remote_event_signal(&state->remote->recycle); +- } ++ if (header) { ++ int msgid = header->msgid; ++ if (((msgid & VCHIQ_MSGID_CLAIMED) == 0) || ++ (service && service->closing)) { ++ mutex_unlock(&state->recycle_mutex); ++ return; ++ } ++ ++ /* Rewrite the message header to prevent a double ++ ** release */ ++ header->msgid = msgid & ~VCHIQ_MSGID_CLAIMED; ++ } ++ ++ release_count = slot_info->release_count; ++ slot_info->release_count = ++release_count; ++ ++ if (release_count == slot_info->use_count) { ++ int slot_queue_recycle; ++ /* Add to the freed queue */ ++ ++ /* A read barrier is necessary here to prevent speculative ++ ** fetches of remote->slot_queue_recycle from overtaking the ++ ** mutex. */ ++ rmb(); ++ ++ slot_queue_recycle = state->remote->slot_queue_recycle; ++ state->remote->slot_queue[slot_queue_recycle & ++ VCHIQ_SLOT_QUEUE_MASK] = ++ SLOT_INDEX_FROM_INFO(state, slot_info); ++ state->remote->slot_queue_recycle = slot_queue_recycle + 1; ++ vchiq_log_info(vchiq_core_log_level, ++ "%d: release_slot %d - recycle->%x", ++ state->id, SLOT_INDEX_FROM_INFO(state, slot_info), ++ state->remote->slot_queue_recycle); ++ ++ /* A write barrier is necessary, but remote_event_signal ++ ** contains one. */ ++ remote_event_signal(&state->remote->recycle); ++ } + +- vcos_mutex_unlock(&state->recycle_mutex); ++ mutex_unlock(&state->recycle_mutex); + } + + /* Called by the slot handler - don't hold the bulk mutex */ + static VCHIQ_STATUS_T +-notify_bulks(VCHIQ_SERVICE_T *service, VCHIQ_BULK_QUEUE_T *queue) ++notify_bulks(VCHIQ_SERVICE_T *service, VCHIQ_BULK_QUEUE_T *queue, ++ int retry_poll) + { +- VCHIQ_STATUS_T status = VCHIQ_SUCCESS; ++ VCHIQ_STATUS_T status = VCHIQ_SUCCESS; + +- vcos_log_trace("%d: nb:%d %cx - p=%x rn=%x r=%x", +- service->state->id, service->localport, +- (queue == &service->bulk_tx) ? 't' : 'r', +- queue->process, queue->remote_notify, queue->remove); +- +- if (service->state->is_master) +- { +- while (queue->remote_notify != queue->process) +- { +- VCHIQ_BULK_T *bulk = &queue->bulks[BULK_INDEX(queue->remote_notify)]; +- int msgtype = (bulk->dir == VCHIQ_BULK_TRANSMIT) ? +- VCHIQ_MSG_BULK_RX_DONE : VCHIQ_MSG_BULK_TX_DONE; +- int msgid = VCHIQ_MAKE_MSG(msgtype, service->localport, service->remoteport); +- VCHIQ_ELEMENT_T element = { &bulk->actual, 4 }; +- /* Only reply to non-dummy bulk requests */ +- if (bulk->remote_data) +- { +- status = queue_message(service->state, NULL, msgid, &element, 1, 4, 0); +- if (status != VCHIQ_SUCCESS) +- break; +- } +- queue->remote_notify++; +- } +- } +- else +- { +- queue->remote_notify = queue->process; +- } +- +- if (status == VCHIQ_SUCCESS) +- { +- while (queue->remove != queue->remote_notify) +- { +- VCHIQ_BULK_T *bulk = &queue->bulks[BULK_INDEX(queue->remove)]; +- +- /* Only generate callbacks for non-dummy bulk requests */ +- if (bulk->data) +- { +- if (bulk->actual != VCHIQ_BULK_ACTUAL_ABORTED) +- { +- if (bulk->dir == VCHIQ_BULK_TRANSMIT) +- { +- VCHIQ_SERVICE_STATS_INC(service, bulk_tx_count); +- VCHIQ_SERVICE_STATS_ADD(service, bulk_tx_bytes, bulk->actual); +- } +- else +- { +- VCHIQ_SERVICE_STATS_INC(service, bulk_rx_count); +- VCHIQ_SERVICE_STATS_ADD(service, bulk_rx_bytes, bulk->actual); +- } +- } +- else +- { +- VCHIQ_SERVICE_STATS_INC(service, bulk_aborted_count); +- } +- if (bulk->mode == VCHIQ_BULK_MODE_BLOCKING) +- { +- BULK_WAITER_T *waiter = (BULK_WAITER_T *)bulk->userdata; +- if (waiter) +- { +- waiter->actual = bulk->actual; +- vcos_event_signal(&waiter->event); +- } +- } +- else if (bulk->mode == VCHIQ_BULK_MODE_CALLBACK) +- { +- VCHIQ_REASON_T reason = (bulk->dir == VCHIQ_BULK_TRANSMIT) ? +- ((bulk->actual == VCHIQ_BULK_ACTUAL_ABORTED) ? +- VCHIQ_BULK_TRANSMIT_ABORTED : VCHIQ_BULK_TRANSMIT_DONE) : +- ((bulk->actual == VCHIQ_BULK_ACTUAL_ABORTED) ? +- VCHIQ_BULK_RECEIVE_ABORTED : VCHIQ_BULK_RECEIVE_DONE); +- status = make_service_callback(service, reason, +- NULL, bulk->userdata); +- if (status == VCHIQ_RETRY) +- break; +- } +- } +- +- queue->remove++; +- vcos_event_signal(&service->bulk_remove_event); +- } +- } +- +- if (status != VCHIQ_SUCCESS) +- request_poll(service->state, service, (queue == &service->bulk_tx) ? +- VCHIQ_POLL_TXNOTIFY : VCHIQ_POLL_RXNOTIFY); ++ vchiq_log_trace(vchiq_core_log_level, ++ "%d: nb:%d %cx - p=%x rn=%x r=%x", ++ service->state->id, service->localport, ++ (queue == &service->bulk_tx) ? 't' : 'r', ++ queue->process, queue->remote_notify, queue->remove); ++ ++ if (service->state->is_master) { ++ while (queue->remote_notify != queue->process) { ++ VCHIQ_BULK_T *bulk = ++ &queue->bulks[BULK_INDEX(queue->remote_notify)]; ++ int msgtype = (bulk->dir == VCHIQ_BULK_TRANSMIT) ? ++ VCHIQ_MSG_BULK_RX_DONE : VCHIQ_MSG_BULK_TX_DONE; ++ int msgid = VCHIQ_MAKE_MSG(msgtype, service->localport, ++ service->remoteport); ++ VCHIQ_ELEMENT_T element = { &bulk->actual, 4 }; ++ /* Only reply to non-dummy bulk requests */ ++ if (bulk->remote_data) { ++ status = queue_message(service->state, NULL, ++ msgid, &element, 1, 4, 0); ++ if (status != VCHIQ_SUCCESS) ++ break; ++ } ++ queue->remote_notify++; ++ } ++ } else { ++ queue->remote_notify = queue->process; ++ } ++ ++ if (status == VCHIQ_SUCCESS) { ++ while (queue->remove != queue->remote_notify) { ++ VCHIQ_BULK_T *bulk = ++ &queue->bulks[BULK_INDEX(queue->remove)]; ++ ++ /* Only generate callbacks for non-dummy bulk ++ ** requests, and non-terminated services */ ++ if (bulk->data && service->instance) { ++ if (bulk->actual != VCHIQ_BULK_ACTUAL_ABORTED) { ++ if (bulk->dir == VCHIQ_BULK_TRANSMIT) { ++ VCHIQ_SERVICE_STATS_INC(service, ++ bulk_tx_count); ++ VCHIQ_SERVICE_STATS_ADD(service, ++ bulk_tx_bytes, ++ bulk->actual); ++ } else { ++ VCHIQ_SERVICE_STATS_INC(service, ++ bulk_rx_count); ++ VCHIQ_SERVICE_STATS_ADD(service, ++ bulk_rx_bytes, ++ bulk->actual); ++ } ++ } else { ++ VCHIQ_SERVICE_STATS_INC(service, ++ bulk_aborted_count); ++ } ++ if (bulk->mode == VCHIQ_BULK_MODE_BLOCKING) { ++ struct bulk_waiter *waiter; ++ spin_lock(&bulk_waiter_spinlock); ++ waiter = bulk->userdata; ++ if (waiter) { ++ waiter->actual = bulk->actual; ++ up(&waiter->event); ++ } ++ spin_unlock(&bulk_waiter_spinlock); ++ } else if (bulk->mode == ++ VCHIQ_BULK_MODE_CALLBACK) { ++ VCHIQ_REASON_T reason = (bulk->dir == ++ VCHIQ_BULK_TRANSMIT) ? ++ ((bulk->actual == ++ VCHIQ_BULK_ACTUAL_ABORTED) ? ++ VCHIQ_BULK_TRANSMIT_ABORTED : ++ VCHIQ_BULK_TRANSMIT_DONE) : ++ ((bulk->actual == ++ VCHIQ_BULK_ACTUAL_ABORTED) ? ++ VCHIQ_BULK_RECEIVE_ABORTED : ++ VCHIQ_BULK_RECEIVE_DONE); ++ status = make_service_callback(service, ++ reason, NULL, bulk->userdata); ++ if (status == VCHIQ_RETRY) ++ break; ++ status = VCHIQ_SUCCESS; ++ } ++ } ++ ++ queue->remove++; ++ up(&service->bulk_remove_event); ++ } ++ if (!retry_poll) ++ status = VCHIQ_SUCCESS; ++ } ++ ++ if (status == VCHIQ_RETRY) ++ request_poll(service->state, service, ++ (queue == &service->bulk_tx) ? ++ VCHIQ_POLL_TXNOTIFY : VCHIQ_POLL_RXNOTIFY); + +- return status; ++ return status; + } + + /* Called by the slot handler thread */ + static void + poll_services(VCHIQ_STATE_T *state) + { +- int group, i; ++ int group, i; + +- for (group = 0; group < BITSET_SIZE(state->unused_service); group++) +- { +- uint32_t flags; +- flags = vcos_atomic_flags_get_and_clear(&state->poll_services[group]); +- for (i = 0; flags; i++) +- { +- if (flags & (1 << i)) +- { +- VCHIQ_SERVICE_T *service = state->services[(group<<5) + i]; +- uint32_t service_flags = +- vcos_atomic_flags_get_and_clear(&service->poll_flags); +- if (service_flags & (1 << VCHIQ_POLL_TERMINATE)) +- { +- vcos_log_info("%d: ps - terminate %d<->%d", state->id, service->localport, service->remoteport); +- if (vchiq_close_service_internal(service, 0/*!close_recvd*/) != VCHIQ_SUCCESS) +- request_poll(state, service, VCHIQ_POLL_TERMINATE); +- } +- if (service_flags & (1 << VCHIQ_POLL_TXNOTIFY)) +- notify_bulks(service, &service->bulk_tx); +- if (service_flags & (1 << VCHIQ_POLL_RXNOTIFY)) +- notify_bulks(service, &service->bulk_rx); +- flags &= ~(1 << i); +- } +- } +- } ++ for (group = 0; group < BITSET_SIZE(state->unused_service); group++) { ++ uint32_t flags; ++ flags = atomic_xchg(&state->poll_services[group], 0); ++ for (i = 0; flags; i++) { ++ if (flags & (1 << i)) { ++ VCHIQ_SERVICE_T *service = ++ find_service_by_port(state, ++ (group<<5) + i); ++ uint32_t service_flags; ++ flags &= ~(1 << i); ++ if (!service) ++ continue; ++ service_flags = ++ atomic_xchg(&service->poll_flags, 0); ++ if (service_flags & ++ (1 << VCHIQ_POLL_TERMINATE)) { ++ vchiq_log_info(vchiq_core_log_level, ++ "%d: ps - terminate %d<->%d", ++ state->id, service->localport, ++ service->remoteport); ++ if (vchiq_close_service_internal( ++ service, 0/*!close_recvd*/) != ++ VCHIQ_SUCCESS) ++ request_poll(state, service, ++ VCHIQ_POLL_TERMINATE); ++ } ++ if (service_flags & (1 << VCHIQ_POLL_TXNOTIFY)) ++ notify_bulks(service, ++ &service->bulk_tx, ++ 1/*retry_poll*/); ++ if (service_flags & (1 << VCHIQ_POLL_RXNOTIFY)) ++ notify_bulks(service, ++ &service->bulk_rx, ++ 1/*retry_poll*/); ++ unlock_service(service); ++ } ++ } ++ } + } + + /* Called by the slot handler or application threads, holding the bulk mutex. */ + static int + resolve_bulks(VCHIQ_SERVICE_T *service, VCHIQ_BULK_QUEUE_T *queue) + { +- VCHIQ_STATE_T *state = service->state; +- int resolved = 0; ++ VCHIQ_STATE_T *state = service->state; ++ int resolved = 0; + +- while ((queue->process != queue->local_insert) && +- (queue->process != queue->remote_insert)) +- { +- VCHIQ_BULK_T *bulk = &queue->bulks[BULK_INDEX(queue->process)]; +- +- vcos_log_trace("%d: rb:%d %cx - li=%x ri=%x p=%x", +- state->id, service->localport, +- (queue == &service->bulk_tx) ? 't' : 'r', +- queue->local_insert, queue->remote_insert, +- queue->process); +- +- vcos_assert((int)(queue->local_insert - queue->process) > 0); +- vcos_assert((int)(queue->remote_insert - queue->process) > 0); +- vchiq_transfer_bulk(bulk); +- +- if (vcos_is_log_enabled( &vchiq_core_msg_log_category, VCOS_LOG_INFO)) +- { +- const char *header = (queue == &service->bulk_tx) ? +- "Send Bulk to" : "Recv Bulk from"; +- if (bulk->actual != VCHIQ_BULK_ACTUAL_ABORTED) +- vcos_log_impl( &vchiq_core_msg_log_category, +- VCOS_LOG_INFO, +- "%s %c%c%c%c d:%d len:%d %x<->%x", +- header, +- VCHIQ_FOURCC_AS_4CHARS(service->base.fourcc), +- service->remoteport, +- bulk->size, +- (unsigned int)bulk->data, +- (unsigned int)bulk->remote_data ); +- else +- vcos_log_impl( &vchiq_core_msg_log_category, +- VCOS_LOG_INFO, +- "%s %c%c%c%c d:%d ABORTED - tx len:%d, rx len:%d %x<->%x", +- header, +- VCHIQ_FOURCC_AS_4CHARS(service->base.fourcc), +- service->remoteport, +- bulk->size, +- bulk->remote_size, +- (unsigned int)bulk->data, +- (unsigned int)bulk->remote_data ); +- } +- +- vchiq_complete_bulk(bulk); +- queue->process++; +- resolved++; +- } +- return resolved; ++ while ((queue->process != queue->local_insert) && ++ (queue->process != queue->remote_insert)) { ++ VCHIQ_BULK_T *bulk = &queue->bulks[BULK_INDEX(queue->process)]; ++ ++ vchiq_log_trace(vchiq_core_log_level, ++ "%d: rb:%d %cx - li=%x ri=%x p=%x", ++ state->id, service->localport, ++ (queue == &service->bulk_tx) ? 't' : 'r', ++ queue->local_insert, queue->remote_insert, ++ queue->process); ++ ++ WARN_ON(!((int)(queue->local_insert - queue->process) > 0)); ++ WARN_ON(!((int)(queue->remote_insert - queue->process) > 0)); ++ ++ mutex_lock(&state->bulk_transfer_mutex); ++ vchiq_transfer_bulk(bulk); ++ mutex_unlock(&state->bulk_transfer_mutex); ++ ++ if (vchiq_core_msg_log_level >= VCHIQ_LOG_INFO) { ++ const char *header = (queue == &service->bulk_tx) ? ++ "Send Bulk to" : "Recv Bulk from"; ++ if (bulk->actual != VCHIQ_BULK_ACTUAL_ABORTED) ++ vchiq_log_info(vchiq_core_msg_log_level, ++ "%s %c%c%c%c d:%d len:%d %x<->%x", ++ header, ++ VCHIQ_FOURCC_AS_4CHARS( ++ service->base.fourcc), ++ service->remoteport, ++ bulk->size, ++ (unsigned int)bulk->data, ++ (unsigned int)bulk->remote_data); ++ else ++ vchiq_log_info(vchiq_core_msg_log_level, ++ "%s %c%c%c%c d:%d ABORTED - tx len:%d," ++ " rx len:%d %x<->%x", ++ header, ++ VCHIQ_FOURCC_AS_4CHARS( ++ service->base.fourcc), ++ service->remoteport, ++ bulk->size, ++ bulk->remote_size, ++ (unsigned int)bulk->data, ++ (unsigned int)bulk->remote_data); ++ } ++ ++ vchiq_complete_bulk(bulk); ++ queue->process++; ++ resolved++; ++ } ++ return resolved; + } + + /* Called with the bulk_mutex held */ + static void + abort_outstanding_bulks(VCHIQ_SERVICE_T *service, VCHIQ_BULK_QUEUE_T *queue) + { +- int is_tx = (queue == &service->bulk_tx); +- vcos_log_trace("%d: aob:%d %cx - li=%x ri=%x p=%x", +- service->state->id, service->localport, is_tx ? 't' : 'r', +- queue->local_insert, queue->remote_insert, queue->process); +- +- vcos_assert((int)(queue->local_insert - queue->process) >= 0); +- vcos_assert((int)(queue->remote_insert - queue->process) >= 0); +- +- while ((queue->process != queue->local_insert) || +- (queue->process != queue->remote_insert)) +- { +- VCHIQ_BULK_T *bulk = &queue->bulks[BULK_INDEX(queue->process)]; +- +- if (queue->process == queue->remote_insert) +- { +- /* fabricate a matching dummy bulk */ +- bulk->remote_data = NULL; +- bulk->remote_size = 0; +- queue->remote_insert++; +- } +- +- if (queue->process != queue->local_insert) +- { +- vchiq_complete_bulk(bulk); +- +- if (vcos_is_log_enabled( &vchiq_core_msg_log_category, VCOS_LOG_INFO)) +- { +- vcos_log_impl( &vchiq_core_msg_log_category, +- VCOS_LOG_INFO, +- "%s %c%c%c%c d:%d ABORTED - tx len:%d, rx len:%d", +- is_tx ? "Send Bulk to" : "Recv Bulk from", +- VCHIQ_FOURCC_AS_4CHARS(service->base.fourcc), +- service->remoteport, +- bulk->size, +- bulk->remote_size ); +- } +- } +- else +- { +- /* fabricate a matching dummy bulk */ +- bulk->data = NULL; +- bulk->size = 0; +- bulk->actual = VCHIQ_BULK_ACTUAL_ABORTED; +- bulk->dir = is_tx ? VCHIQ_BULK_TRANSMIT : VCHIQ_BULK_RECEIVE; +- queue->local_insert++; +- } ++ int is_tx = (queue == &service->bulk_tx); ++ vchiq_log_trace(vchiq_core_log_level, ++ "%d: aob:%d %cx - li=%x ri=%x p=%x", ++ service->state->id, service->localport, is_tx ? 't' : 'r', ++ queue->local_insert, queue->remote_insert, queue->process); ++ ++ WARN_ON(!((int)(queue->local_insert - queue->process) >= 0)); ++ WARN_ON(!((int)(queue->remote_insert - queue->process) >= 0)); ++ ++ while ((queue->process != queue->local_insert) || ++ (queue->process != queue->remote_insert)) { ++ VCHIQ_BULK_T *bulk = &queue->bulks[BULK_INDEX(queue->process)]; ++ ++ if (queue->process == queue->remote_insert) { ++ /* fabricate a matching dummy bulk */ ++ bulk->remote_data = NULL; ++ bulk->remote_size = 0; ++ queue->remote_insert++; ++ } ++ ++ if (queue->process != queue->local_insert) { ++ vchiq_complete_bulk(bulk); ++ ++ vchiq_log_info(vchiq_core_msg_log_level, ++ "%s %c%c%c%c d:%d ABORTED - tx len:%d, " ++ "rx len:%d", ++ is_tx ? "Send Bulk to" : "Recv Bulk from", ++ VCHIQ_FOURCC_AS_4CHARS(service->base.fourcc), ++ service->remoteport, ++ bulk->size, ++ bulk->remote_size); ++ } else { ++ /* fabricate a matching dummy bulk */ ++ bulk->data = NULL; ++ bulk->size = 0; ++ bulk->actual = VCHIQ_BULK_ACTUAL_ABORTED; ++ bulk->dir = is_tx ? VCHIQ_BULK_TRANSMIT : ++ VCHIQ_BULK_RECEIVE; ++ queue->local_insert++; ++ } + +- queue->process++; +- } ++ queue->process++; ++ } + } + ++/* Called from the slot handler thread */ + static void + pause_bulks(VCHIQ_STATE_T *state) + { +- int i; ++ if (unlikely(atomic_inc_return(&pause_bulks_count) != 1)) { ++ WARN_ON_ONCE(1); ++ atomic_set(&pause_bulks_count, 1); ++ return; ++ } + +- /* Block bulk transfers from all services */ +- for (i = 0; i < state->unused_service; i++) +- { +- VCHIQ_SERVICE_T *service = state->services[i]; +- if (!service || (service->srvstate != VCHIQ_SRVSTATE_OPEN)) +- continue; +- +- vcos_log_trace("locking bulk_mutex for service %d", i); +- vcos_mutex_lock(&service->bulk_mutex); +- } ++ /* Block bulk transfers from all services */ ++ mutex_lock(&state->bulk_transfer_mutex); + } + ++/* Called from the slot handler thread */ + static void + resume_bulks(VCHIQ_STATE_T *state) + { +- int i; ++ if (unlikely(atomic_dec_return(&pause_bulks_count) != 0)) { ++ WARN_ON_ONCE(1); ++ atomic_set(&pause_bulks_count, 0); ++ return; ++ } + +- /* Poll all services in case any bulk transfers have been +- deferred */ +- for (i = 0; i < state->unused_service; i++) +- { +- VCHIQ_SERVICE_T *service = state->services[i]; +- if (!service || (service->srvstate != VCHIQ_SRVSTATE_OPEN)) +- continue; +- +- if (resolve_bulks(service, &service->bulk_tx)) +- request_poll(state, service, VCHIQ_POLL_TXNOTIFY); +- if (resolve_bulks(service, &service->bulk_rx)) +- request_poll(state, service, VCHIQ_POLL_RXNOTIFY); +- vcos_log_trace("unlocking bulk_mutex for service %d", i); +- vcos_mutex_unlock(&service->bulk_mutex); +- } ++ /* Allow bulk transfers from all services */ ++ mutex_unlock(&state->bulk_transfer_mutex); ++} ++ ++static int ++parse_open(VCHIQ_STATE_T *state, VCHIQ_HEADER_T *header) ++{ ++ VCHIQ_SERVICE_T *service = NULL; ++ int msgid, size; ++ int type; ++ unsigned int localport, remoteport; ++ ++ msgid = header->msgid; ++ size = header->size; ++ type = VCHIQ_MSG_TYPE(msgid); ++ localport = VCHIQ_MSG_DSTPORT(msgid); ++ remoteport = VCHIQ_MSG_SRCPORT(msgid); ++ if (size == sizeof(struct vchiq_open_payload)) { ++ const struct vchiq_open_payload *payload = ++ (struct vchiq_open_payload *)header->data; ++ unsigned int fourcc; ++ ++ fourcc = payload->fourcc; ++ vchiq_log_info(vchiq_core_log_level, ++ "%d: prs OPEN@%x (%d->'%c%c%c%c')", ++ state->id, (unsigned int)header, ++ localport, ++ VCHIQ_FOURCC_AS_4CHARS(fourcc)); ++ ++ service = get_listening_service(state, fourcc); ++ ++ if (service) { ++ /* A matching service exists */ ++ short version = payload->version; ++ short version_min = payload->version_min; ++ if ((service->version < version_min) || ++ (version < service->version_min)) { ++ /* Version mismatch */ ++ vchiq_loud_error_header(); ++ vchiq_loud_error("%d: service %d (%c%c%c%c) " ++ "version mismatch - local (%d, min %d)" ++ " vs. remote (%d, min %d)", ++ state->id, service->localport, ++ VCHIQ_FOURCC_AS_4CHARS(fourcc), ++ service->version, service->version_min, ++ version, version_min); ++ vchiq_loud_error_footer(); ++ goto fail_open; ++ } ++ if (service->srvstate == VCHIQ_SRVSTATE_LISTENING) { ++ /* Acknowledge the OPEN */ ++ if (service->sync) { ++ if (queue_message_sync(state, NULL, ++ VCHIQ_MAKE_MSG( ++ VCHIQ_MSG_OPENACK, ++ service->localport, ++ remoteport), ++ NULL, 0, 0, 0) == VCHIQ_RETRY) ++ goto bail_not_ready; ++ } else { ++ if (queue_message(state, NULL, ++ VCHIQ_MAKE_MSG( ++ VCHIQ_MSG_OPENACK, ++ service->localport, ++ remoteport), ++ NULL, 0, 0, 0) == VCHIQ_RETRY) ++ goto bail_not_ready; ++ } ++ ++ /* The service is now open */ ++ vchiq_set_service_state(service, ++ service->sync ? VCHIQ_SRVSTATE_OPENSYNC ++ : VCHIQ_SRVSTATE_OPEN); ++ } ++ ++ service->remoteport = remoteport; ++ service->client_id = ((int *)header->data)[1]; ++ if (make_service_callback(service, VCHIQ_SERVICE_OPENED, ++ NULL, NULL) == VCHIQ_RETRY) { ++ /* Bail out if not ready */ ++ service->remoteport = VCHIQ_PORT_FREE; ++ goto bail_not_ready; ++ } ++ ++ /* Success - the message has been dealt with */ ++ unlock_service(service); ++ return 1; ++ } ++ } ++ ++fail_open: ++ /* No available service, or an invalid request - send a CLOSE */ ++ if (queue_message(state, NULL, ++ VCHIQ_MAKE_MSG(VCHIQ_MSG_CLOSE, 0, VCHIQ_MSG_SRCPORT(msgid)), ++ NULL, 0, 0, 0) == VCHIQ_RETRY) ++ goto bail_not_ready; ++ ++ unlock_service(service); ++ ++ return 1; ++ ++bail_not_ready: ++ unlock_service(service); ++ ++ return 0; + } + + /* Called by the slot handler thread */ + static void + parse_rx_slots(VCHIQ_STATE_T *state) + { +- VCHIQ_SHARED_STATE_T *remote = state->remote; +- int tx_pos; +- DEBUG_INITIALISE(state->local) +- +- tx_pos = remote->tx_pos; +- +- while (state->rx_pos != tx_pos) { +- VCHIQ_SERVICE_T *service = NULL; +- VCHIQ_HEADER_T *header; +- int msgid, size; +- int type; +- unsigned int localport, remoteport; +- +- DEBUG_TRACE(PARSE_LINE); +- if (!state->rx_data) +- { +- int rx_index; +- vcos_assert((state->rx_pos & VCHIQ_SLOT_MASK) == 0); +- rx_index = remote->slot_queue[SLOT_QUEUE_INDEX_FROM_POS(state->rx_pos) & VCHIQ_SLOT_QUEUE_MASK]; +- state->rx_data = (char *)SLOT_DATA_FROM_INDEX(state, rx_index); +- state->rx_info = SLOT_INFO_FROM_INDEX(state, rx_index); +- +- /* Initialise use_count to one, and increment release_count at the end +- of the slot to avoid releasing the slot prematurely. */ +- state->rx_info->use_count = 1; +- state->rx_info->release_count = 0; +- } +- +- header = (VCHIQ_HEADER_T *)(state->rx_data + (state->rx_pos & VCHIQ_SLOT_MASK)); +- DEBUG_VALUE(PARSE_HEADER, (int)header); +- msgid = header->msgid; +- DEBUG_VALUE(PARSE_MSGID, msgid); +- size = header->size; +- type = VCHIQ_MSG_TYPE(msgid); +- localport = VCHIQ_MSG_DSTPORT(msgid); +- remoteport = VCHIQ_MSG_SRCPORT(msgid); +- +- if (type != VCHIQ_MSG_DATA) +- { +- VCHIQ_STATS_INC(state, ctrl_rx_count); +- } +- +- switch (type) +- { +- case VCHIQ_MSG_OPENACK: +- case VCHIQ_MSG_CLOSE: +- case VCHIQ_MSG_DATA: +- case VCHIQ_MSG_BULK_RX: +- case VCHIQ_MSG_BULK_TX: +- case VCHIQ_MSG_BULK_RX_DONE: +- case VCHIQ_MSG_BULK_TX_DONE: +- if (localport <= VCHIQ_PORT_MAX) +- { +- service = state->services[localport]; +- if (service && (service->srvstate == VCHIQ_SRVSTATE_FREE)) +- service = NULL; +- } +- if (!service) +- { +- vcos_log_error( +- "%d: prs %s@%x (%d->%d) - invalid/closed service %d", +- state->id, msg_type_str(type), (unsigned int)header, +- remoteport, localport, localport); +- goto skip_message; +- } +- default: +- break; +- } +- +- if ( vcos_is_log_enabled( &vchiq_core_msg_log_category, VCOS_LOG_INFO)) +- { +- int svc_fourcc; +- +- svc_fourcc = service +- ? service->base.fourcc +- : VCHIQ_MAKE_FOURCC('?','?','?','?'); +- vcos_log_impl( &vchiq_core_msg_log_category, +- VCOS_LOG_INFO, +- "Rcvd Msg %s(%u) from %c%c%c%c s:%d d:%d len:%d", +- msg_type_str(type), type, +- VCHIQ_FOURCC_AS_4CHARS(svc_fourcc), +- remoteport, localport, size ); +- if (size > 0) { +- vcos_log_dump_mem( &vchiq_core_msg_log_category, +- "Rcvd", 0, header->data, +- vcos_min( 64, size )); +- } +- } +- +- if (((unsigned int)header & VCHIQ_SLOT_MASK) + calc_stride(size) > VCHIQ_SLOT_SIZE) +- { +- vcos_log_error("header %x (msgid %x) - size %x too big for slot", +- (unsigned int)header, (unsigned int)msgid, (unsigned int)size); +- vcos_assert(0); +- } +- +- switch (type) { +- case VCHIQ_MSG_OPEN: +- vcos_assert(VCHIQ_MSG_DSTPORT(msgid) == 0); +- if (vcos_verify(size == sizeof(VCHIQ_OPEN_PAYLOAD_T))) { +- const VCHIQ_OPEN_PAYLOAD_T *payload = (VCHIQ_OPEN_PAYLOAD_T *)header->data; +- unsigned int fourcc; +- +- fourcc = payload->fourcc; +- vcos_log_info("%d: prs OPEN@%x (%d->'%c%c%c%c')", +- state->id, (unsigned int)header, +- localport, +- VCHIQ_FOURCC_AS_4CHARS(fourcc)); +- +- service = get_listening_service(state, fourcc); +- +- if (service) +- { +- /* A matching service exists */ +- short version = payload->version; +- short version_min = payload->version_min; +- if ((service->version < version_min) || +- (version < service->version_min)) +- { +- /* Version mismatch */ +- vcos_log_error("%d: service %d (%c%c%c%c) version mismatch -" +- " local (%d, min %d) vs. remote (%d, min %d)", +- state->id, service->localport, +- VCHIQ_FOURCC_AS_4CHARS(fourcc), +- service->version, service->version_min, +- version, version_min); +- goto fail_open; +- } +- if (service->srvstate == VCHIQ_SRVSTATE_LISTENING) +- { +- /* Acknowledge the OPEN */ +- if (queue_message(state, NULL, +- VCHIQ_MAKE_MSG(VCHIQ_MSG_OPENACK, service->localport, remoteport), +- NULL, 0, 0, 0) == VCHIQ_RETRY) +- return; /* Bail out if not ready */ +- +- /* The service is now open */ +- vchiq_set_service_state(service, VCHIQ_SRVSTATE_OPEN); +- } +- +- service->remoteport = remoteport; +- service->client_id = ((int *)header->data)[1]; +- if (make_service_callback(service, VCHIQ_SERVICE_OPENED, +- NULL, NULL) == VCHIQ_RETRY) +- { +- /* Bail out if not ready */ +- service->remoteport = VCHIQ_PORT_FREE; +- return; +- } +- +- /* Break out, and skip the failure handling */ +- break; +- } +- } +- fail_open: +- /* No available service, or an invalid request - send a CLOSE */ +- if (queue_message(state, NULL, +- VCHIQ_MAKE_MSG(VCHIQ_MSG_CLOSE, 0, VCHIQ_MSG_SRCPORT(msgid)), +- NULL, 0, 0, 0) == VCHIQ_RETRY) +- return; /* Bail out if not ready */ +- break; +- case VCHIQ_MSG_OPENACK: +- { +- vcos_log_info("%d: prs OPENACK@%x (%d->%d)", +- state->id, (unsigned int)header, +- remoteport, localport); +- if (service->srvstate == VCHIQ_SRVSTATE_OPENING) { +- service->remoteport = remoteport; +- vchiq_set_service_state(service, +- VCHIQ_SRVSTATE_OPEN); +- vcos_event_signal(&service->remove_event); +- } +- } +- break; +- case VCHIQ_MSG_CLOSE: +- { +- vcos_assert(size == 0); /* There should be no data */ +- +- vcos_log_info("%d: prs CLOSE@%x (%d->%d)", +- state->id, (unsigned int)header, +- remoteport, localport); +- +- if ((service->remoteport != remoteport) && +- VCHIQ_PORT_IS_VALID(service->remoteport)) { +- /* This could be from a client which hadn't yet received +- the OPENACK - look for the connected service */ +- service = get_connected_service(state, remoteport); +- if (!service) +- break; +- } +- +- if (vchiq_close_service_internal(service, +- 1/*close_recvd*/) == VCHIQ_RETRY) +- return; /* Bail out if not ready */ +- +- if (vcos_is_log_enabled( &vchiq_core_msg_log_category, VCOS_LOG_INFO)) +- { +- vcos_log_impl( &vchiq_core_msg_log_category, +- VCOS_LOG_INFO, +- "Close Service %c%c%c%c s:%u d:%d", +- VCHIQ_FOURCC_AS_4CHARS(service->base.fourcc), +- service->localport, +- service->remoteport ); +- } +- } +- break; +- case VCHIQ_MSG_DATA: +- { +- vcos_log_trace("%d: prs DATA@%x,%x (%d->%d)", +- state->id, (unsigned int)header, size, +- remoteport, localport); +- +- if ((service->remoteport == remoteport) +- && (service->srvstate == +- VCHIQ_SRVSTATE_OPEN)) { +- header->msgid = msgid | VCHIQ_MSGID_CLAIMED; +- claim_slot(state->rx_info); +- DEBUG_TRACE(PARSE_LINE); +- if (make_service_callback(service, +- VCHIQ_MESSAGE_AVAILABLE, header, +- NULL) == VCHIQ_RETRY) +- { +- DEBUG_TRACE(PARSE_LINE); +- return; /* Bail out if not ready */ +- } +- VCHIQ_SERVICE_STATS_INC(service, ctrl_rx_count); +- VCHIQ_SERVICE_STATS_ADD(service, ctrl_rx_bytes, size); +- } +- else +- { +- VCHIQ_STATS_INC(state, error_count); +- } +- } +- break; +- case VCHIQ_MSG_CONNECT: +- vcos_log_info("%d: prs CONNECT@%x", +- state->id, (unsigned int)header); +- vcos_event_signal(&state->connect); +- break; +- case VCHIQ_MSG_BULK_RX: +- case VCHIQ_MSG_BULK_TX: +- { +- VCHIQ_BULK_QUEUE_T *queue; +- vcos_assert(state->is_master); +- queue = (type == VCHIQ_MSG_BULK_RX) ? +- &service->bulk_tx : &service->bulk_rx; +- if ((service->remoteport == remoteport) +- && (service->srvstate == +- VCHIQ_SRVSTATE_OPEN)) +- { +- VCHIQ_BULK_T *bulk; +- int resolved; +- +- vcos_assert(queue->remote_insert < queue->remove + +- VCHIQ_NUM_SERVICE_BULKS); +- bulk = &queue->bulks[BULK_INDEX(queue->remote_insert)]; +- bulk->remote_data = (void *)((int *)header->data)[0]; +- bulk->remote_size = ((int *)header->data)[1]; +- +- vcos_log_info("%d: prs %s@%x (%d->%d) %x@%x", +- state->id, msg_type_str(type), +- (unsigned int)header, +- remoteport, localport, +- bulk->remote_size, +- (unsigned int)bulk->remote_data); +- +- queue->remote_insert++; +- +- if (state->conn_state != VCHIQ_CONNSTATE_CONNECTED) +- break; +- +- DEBUG_TRACE(PARSE_LINE); +- if (vcos_mutex_lock(&service->bulk_mutex) != VCOS_SUCCESS) +- { +- DEBUG_TRACE(PARSE_LINE); +- return; +- } +- DEBUG_TRACE(PARSE_LINE); +- resolved = resolve_bulks(service, queue); +- vcos_mutex_unlock(&service->bulk_mutex); +- if (resolved) +- notify_bulks(service, queue); +- } +- } +- break; +- case VCHIQ_MSG_BULK_RX_DONE: +- case VCHIQ_MSG_BULK_TX_DONE: +- { +- vcos_assert(!state->is_master); +- if ((service->remoteport == remoteport) +- && (service->srvstate != +- VCHIQ_SRVSTATE_FREE)) { +- VCHIQ_BULK_QUEUE_T *queue; +- VCHIQ_BULK_T *bulk; +- +- queue = (type == VCHIQ_MSG_BULK_RX_DONE) ? +- &service->bulk_rx : &service->bulk_tx; +- +- bulk = &queue->bulks[BULK_INDEX(queue->process)]; +- bulk->actual = *(int *)header->data; +- +- vcos_log_info("%d: prs %s@%x (%d->%d) %x@%x", +- state->id, msg_type_str(type), +- (unsigned int)header, +- remoteport, localport, +- bulk->actual, (unsigned int)bulk->data); +- +- vcos_log_trace("%d: prs:%d %cx li=%x ri=%x p=%x", +- state->id, localport, +- (type == VCHIQ_MSG_BULK_RX_DONE) ? 'r' : 't', +- queue->local_insert, +- queue->remote_insert, queue->process); +- +- DEBUG_TRACE(PARSE_LINE); +- if (vcos_mutex_lock(&service->bulk_mutex) != VCOS_SUCCESS) +- { +- DEBUG_TRACE(PARSE_LINE); +- return; +- } +- DEBUG_TRACE(PARSE_LINE); +- vcos_assert(queue->process != queue->local_insert); +- vchiq_complete_bulk(bulk); +- queue->process++; +- vcos_mutex_unlock(&service->bulk_mutex); +- DEBUG_TRACE(PARSE_LINE); +- notify_bulks(service, queue); +- DEBUG_TRACE(PARSE_LINE); +- } +- } +- break; +- case VCHIQ_MSG_PADDING: +- vcos_log_trace("%d: prs PADDING@%x,%x", +- state->id, (unsigned int)header, size); +- break; +- case VCHIQ_MSG_PAUSE: +- /* If initiated, signal the application thread */ +- vcos_log_trace("%d: prs PAUSE@%x,%x", +- state->id, (unsigned int)header, size); +- if (state->conn_state != VCHIQ_CONNSTATE_PAUSE_SENT) +- { +- /* Send a PAUSE in response */ +- if (queue_message(state, NULL, +- VCHIQ_MAKE_MSG(VCHIQ_MSG_PAUSE, 0, 0), +- NULL, 0, 0, 0) == VCHIQ_RETRY) +- return; /* Bail out if not ready */ +- if (state->is_master) +- pause_bulks(state); +- } +- /* At this point slot_mutex is held */ +- vchiq_set_conn_state(state, VCHIQ_CONNSTATE_PAUSED); +- vchiq_platform_paused(state); +- break; +- case VCHIQ_MSG_RESUME: +- vcos_log_trace("%d: prs RESUME@%x,%x", +- state->id, (unsigned int)header, size); +- /* Release the slot mutex */ +- vcos_mutex_unlock(&state->slot_mutex); +- if (state->is_master) +- resume_bulks(state); +- vchiq_set_conn_state(state, VCHIQ_CONNSTATE_CONNECTED); +- vchiq_platform_resumed(state); +- break; +- +- case VCHIQ_MSG_REMOTE_USE: +- vchiq_on_remote_use(state); +- break; +- case VCHIQ_MSG_REMOTE_RELEASE: +- vchiq_on_remote_release(state); +- break; +- case VCHIQ_MSG_REMOTE_USE_ACTIVE: +- vchiq_on_remote_use_active(state); +- break; +- +- default: +- vcos_log_error("%d: prs invalid msgid %x@%x,%x", +- state->id, msgid, (unsigned int)header, size); +- vcos_assert(0); +- break; +- } +- +- skip_message: +- state->rx_pos += calc_stride(size); +- +- DEBUG_TRACE(PARSE_LINE); +- /* Perform some housekeeping when the end of the slot is reached. */ +- if ((state->rx_pos & VCHIQ_SLOT_MASK) == 0) +- { +- /* Remove the extra reference count. */ +- release_slot(state, state->rx_info); +- state->rx_data = NULL; +- } +- } ++ VCHIQ_SHARED_STATE_T *remote = state->remote; ++ VCHIQ_SERVICE_T *service = NULL; ++ int tx_pos; ++ DEBUG_INITIALISE(state->local) ++ ++ tx_pos = remote->tx_pos; ++ ++ while (state->rx_pos != tx_pos) { ++ VCHIQ_HEADER_T *header; ++ int msgid, size; ++ int type; ++ unsigned int localport, remoteport; ++ ++ DEBUG_TRACE(PARSE_LINE); ++ if (!state->rx_data) { ++ int rx_index; ++ WARN_ON(!((state->rx_pos & VCHIQ_SLOT_MASK) == 0)); ++ rx_index = remote->slot_queue[ ++ SLOT_QUEUE_INDEX_FROM_POS(state->rx_pos) & ++ VCHIQ_SLOT_QUEUE_MASK]; ++ state->rx_data = (char *)SLOT_DATA_FROM_INDEX(state, ++ rx_index); ++ state->rx_info = SLOT_INFO_FROM_INDEX(state, rx_index); ++ ++ /* Initialise use_count to one, and increment ++ ** release_count at the end of the slot to avoid ++ ** releasing the slot prematurely. */ ++ state->rx_info->use_count = 1; ++ state->rx_info->release_count = 0; ++ } ++ ++ header = (VCHIQ_HEADER_T *)(state->rx_data + ++ (state->rx_pos & VCHIQ_SLOT_MASK)); ++ DEBUG_VALUE(PARSE_HEADER, (int)header); ++ msgid = header->msgid; ++ DEBUG_VALUE(PARSE_MSGID, msgid); ++ size = header->size; ++ type = VCHIQ_MSG_TYPE(msgid); ++ localport = VCHIQ_MSG_DSTPORT(msgid); ++ remoteport = VCHIQ_MSG_SRCPORT(msgid); ++ ++ if (type != VCHIQ_MSG_DATA) ++ VCHIQ_STATS_INC(state, ctrl_rx_count); ++ ++ switch (type) { ++ case VCHIQ_MSG_OPENACK: ++ case VCHIQ_MSG_CLOSE: ++ case VCHIQ_MSG_DATA: ++ case VCHIQ_MSG_BULK_RX: ++ case VCHIQ_MSG_BULK_TX: ++ case VCHIQ_MSG_BULK_RX_DONE: ++ case VCHIQ_MSG_BULK_TX_DONE: ++ service = find_service_by_port(state, localport); ++ if (!service) { ++ vchiq_log_error(vchiq_core_log_level, ++ "%d: prs %s@%x (%d->%d) - " ++ "invalid/closed service %d", ++ state->id, msg_type_str(type), ++ (unsigned int)header, ++ remoteport, localport, localport); ++ goto skip_message; ++ } ++ default: ++ break; ++ } ++ ++ if (vchiq_core_msg_log_level >= VCHIQ_LOG_INFO) { ++ int svc_fourcc; ++ ++ svc_fourcc = service ++ ? service->base.fourcc ++ : VCHIQ_MAKE_FOURCC('?', '?', '?', '?'); ++ vchiq_log_info(vchiq_core_msg_log_level, ++ "Rcvd Msg %s(%u) from %c%c%c%c s:%d d:%d " ++ "len:%d", ++ msg_type_str(type), type, ++ VCHIQ_FOURCC_AS_4CHARS(svc_fourcc), ++ remoteport, localport, size); ++ if (size > 0) ++ vchiq_log_dump_mem("Rcvd", 0, header->data, ++ min(64, size)); ++ } ++ ++ if (((unsigned int)header & VCHIQ_SLOT_MASK) + calc_stride(size) ++ > VCHIQ_SLOT_SIZE) { ++ vchiq_log_error(vchiq_core_log_level, ++ "header %x (msgid %x) - size %x too big for " ++ "slot", ++ (unsigned int)header, (unsigned int)msgid, ++ (unsigned int)size); ++ WARN(1, "oversized for slot\n"); ++ } ++ ++ switch (type) { ++ case VCHIQ_MSG_OPEN: ++ WARN_ON(!(VCHIQ_MSG_DSTPORT(msgid) == 0)); ++ if (!parse_open(state, header)) ++ goto bail_not_ready; ++ break; ++ case VCHIQ_MSG_OPENACK: ++ vchiq_log_info(vchiq_core_log_level, ++ "%d: prs OPENACK@%x (%d->%d)", ++ state->id, (unsigned int)header, ++ remoteport, localport); ++ if (service->srvstate == ++ VCHIQ_SRVSTATE_OPENING) { ++ service->remoteport = remoteport; ++ vchiq_set_service_state(service, ++ VCHIQ_SRVSTATE_OPEN); ++ up(&service->remove_event); ++ } else ++ vchiq_log_error(vchiq_core_log_level, ++ "OPENACK received in state %s", ++ srvstate_names[service->srvstate]); ++ break; ++ case VCHIQ_MSG_CLOSE: ++ WARN_ON(size != 0); /* There should be no data */ ++ ++ vchiq_log_info(vchiq_core_log_level, ++ "%d: prs CLOSE@%x (%d->%d)", ++ state->id, (unsigned int)header, ++ remoteport, localport); ++ ++ if ((service->remoteport != remoteport) && ++ VCHIQ_PORT_IS_VALID(service->remoteport)) { ++ /* This could be from a client which hadn't yet ++ ** received the OPENACK - look for the ++ ** connected service */ ++ service = get_connected_service(state, ++ remoteport); ++ if (!service) ++ break; ++ } ++ ++ mark_service_closing(service); ++ ++ if (vchiq_close_service_internal(service, ++ 1/*close_recvd*/) == VCHIQ_RETRY) ++ goto bail_not_ready; ++ ++ vchiq_log_info(vchiq_core_log_level, ++ "Close Service %c%c%c%c s:%u d:%d", ++ VCHIQ_FOURCC_AS_4CHARS(service->base.fourcc), ++ service->localport, ++ service->remoteport); ++ break; ++ case VCHIQ_MSG_DATA: ++ vchiq_log_trace(vchiq_core_log_level, ++ "%d: prs DATA@%x,%x (%d->%d)", ++ state->id, (unsigned int)header, size, ++ remoteport, localport); ++ ++ if ((service->remoteport == remoteport) ++ && (service->srvstate == ++ VCHIQ_SRVSTATE_OPEN)) { ++ header->msgid = msgid | VCHIQ_MSGID_CLAIMED; ++ claim_slot(state->rx_info); ++ DEBUG_TRACE(PARSE_LINE); ++ if (make_service_callback(service, ++ VCHIQ_MESSAGE_AVAILABLE, header, ++ NULL) == VCHIQ_RETRY) { ++ DEBUG_TRACE(PARSE_LINE); ++ goto bail_not_ready; ++ } ++ VCHIQ_SERVICE_STATS_INC(service, ctrl_rx_count); ++ VCHIQ_SERVICE_STATS_ADD(service, ctrl_rx_bytes, ++ size); ++ } else { ++ VCHIQ_STATS_INC(state, error_count); ++ } ++ break; ++ case VCHIQ_MSG_CONNECT: ++ vchiq_log_info(vchiq_core_log_level, ++ "%d: prs CONNECT@%x", ++ state->id, (unsigned int)header); ++ up(&state->connect); ++ break; ++ case VCHIQ_MSG_BULK_RX: ++ case VCHIQ_MSG_BULK_TX: { ++ VCHIQ_BULK_QUEUE_T *queue; ++ WARN_ON(!state->is_master); ++ queue = (type == VCHIQ_MSG_BULK_RX) ? ++ &service->bulk_tx : &service->bulk_rx; ++ if ((service->remoteport == remoteport) ++ && (service->srvstate == ++ VCHIQ_SRVSTATE_OPEN)) { ++ VCHIQ_BULK_T *bulk; ++ int resolved; ++ ++ WARN_ON(!(queue->remote_insert < queue->remove + ++ VCHIQ_NUM_SERVICE_BULKS)); ++ bulk = &queue->bulks[ ++ BULK_INDEX(queue->remote_insert)]; ++ bulk->remote_data = ++ (void *)((int *)header->data)[0]; ++ bulk->remote_size = ((int *)header->data)[1]; ++ wmb(); ++ ++ vchiq_log_info(vchiq_core_log_level, ++ "%d: prs %s@%x (%d->%d) %x@%x", ++ state->id, msg_type_str(type), ++ (unsigned int)header, ++ remoteport, localport, ++ bulk->remote_size, ++ (unsigned int)bulk->remote_data); ++ ++ queue->remote_insert++; ++ ++ if (state->conn_state != ++ VCHIQ_CONNSTATE_CONNECTED) ++ break; ++ ++ DEBUG_TRACE(PARSE_LINE); ++ if (mutex_lock_interruptible( ++ &service->bulk_mutex) != 0) { ++ DEBUG_TRACE(PARSE_LINE); ++ goto bail_not_ready; ++ } ++ DEBUG_TRACE(PARSE_LINE); ++ resolved = resolve_bulks(service, queue); ++ mutex_unlock(&service->bulk_mutex); ++ if (resolved) ++ notify_bulks(service, queue, ++ 1/*retry_poll*/); ++ } ++ } break; ++ case VCHIQ_MSG_BULK_RX_DONE: ++ case VCHIQ_MSG_BULK_TX_DONE: ++ WARN_ON(state->is_master); ++ if ((service->remoteport == remoteport) ++ && (service->srvstate != ++ VCHIQ_SRVSTATE_FREE)) { ++ VCHIQ_BULK_QUEUE_T *queue; ++ VCHIQ_BULK_T *bulk; ++ ++ queue = (type == VCHIQ_MSG_BULK_RX_DONE) ? ++ &service->bulk_rx : &service->bulk_tx; ++ ++ if ((int)(queue->remote_insert - ++ queue->local_insert) >= 0) { ++ vchiq_log_error(vchiq_core_log_level, ++ "%d: prs %s@%x (%d->%d) " ++ "unexpected", ++ state->id, msg_type_str(type), ++ (unsigned int)header, ++ remoteport, localport); ++ break; ++ } ++ ++ BUG_ON(queue->process == queue->local_insert); ++ BUG_ON(queue->process != queue->remote_insert); ++ ++ bulk = &queue->bulks[ ++ BULK_INDEX(queue->remote_insert)]; ++ bulk->actual = *(int *)header->data; ++ queue->remote_insert++; ++ ++ vchiq_log_info(vchiq_core_log_level, ++ "%d: prs %s@%x (%d->%d) %x@%x", ++ state->id, msg_type_str(type), ++ (unsigned int)header, ++ remoteport, localport, ++ bulk->actual, (unsigned int)bulk->data); ++ ++ vchiq_log_trace(vchiq_core_log_level, ++ "%d: prs:%d %cx li=%x ri=%x p=%x", ++ state->id, localport, ++ (type == VCHIQ_MSG_BULK_RX_DONE) ? ++ 'r' : 't', ++ queue->local_insert, ++ queue->remote_insert, queue->process); ++ ++ DEBUG_TRACE(PARSE_LINE); ++ if (mutex_lock_interruptible( ++ &service->bulk_mutex) != 0) { ++ DEBUG_TRACE(PARSE_LINE); ++ goto bail_not_ready; ++ } ++ DEBUG_TRACE(PARSE_LINE); ++ WARN_ON(queue->process == queue->local_insert); ++ vchiq_complete_bulk(bulk); ++ queue->process++; ++ mutex_unlock(&service->bulk_mutex); ++ DEBUG_TRACE(PARSE_LINE); ++ notify_bulks(service, queue, 1/*retry_poll*/); ++ DEBUG_TRACE(PARSE_LINE); ++ } ++ break; ++ case VCHIQ_MSG_PADDING: ++ vchiq_log_trace(vchiq_core_log_level, ++ "%d: prs PADDING@%x,%x", ++ state->id, (unsigned int)header, size); ++ break; ++ case VCHIQ_MSG_PAUSE: ++ /* If initiated, signal the application thread */ ++ vchiq_log_trace(vchiq_core_log_level, ++ "%d: prs PAUSE@%x,%x", ++ state->id, (unsigned int)header, size); ++ if (state->conn_state == VCHIQ_CONNSTATE_PAUSED) { ++ vchiq_log_error(vchiq_core_log_level, ++ "%d: PAUSE received in state PAUSED", ++ state->id); ++ break; ++ } ++ if (state->conn_state != VCHIQ_CONNSTATE_PAUSE_SENT) { ++ /* Send a PAUSE in response */ ++ if (queue_message(state, NULL, ++ VCHIQ_MAKE_MSG(VCHIQ_MSG_PAUSE, 0, 0), ++ NULL, 0, 0, 0) == VCHIQ_RETRY) ++ goto bail_not_ready; ++ if (state->is_master) ++ pause_bulks(state); ++ } ++ /* At this point slot_mutex is held */ ++ vchiq_set_conn_state(state, VCHIQ_CONNSTATE_PAUSED); ++ vchiq_platform_paused(state); ++ break; ++ case VCHIQ_MSG_RESUME: ++ vchiq_log_trace(vchiq_core_log_level, ++ "%d: prs RESUME@%x,%x", ++ state->id, (unsigned int)header, size); ++ /* Release the slot mutex */ ++ mutex_unlock(&state->slot_mutex); ++ if (state->is_master) ++ resume_bulks(state); ++ vchiq_set_conn_state(state, VCHIQ_CONNSTATE_CONNECTED); ++ vchiq_platform_resumed(state); ++ break; ++ ++ case VCHIQ_MSG_REMOTE_USE: ++ vchiq_on_remote_use(state); ++ break; ++ case VCHIQ_MSG_REMOTE_RELEASE: ++ vchiq_on_remote_release(state); ++ break; ++ case VCHIQ_MSG_REMOTE_USE_ACTIVE: ++ vchiq_on_remote_use_active(state); ++ break; ++ ++ default: ++ vchiq_log_error(vchiq_core_log_level, ++ "%d: prs invalid msgid %x@%x,%x", ++ state->id, msgid, (unsigned int)header, size); ++ WARN(1, "invalid message\n"); ++ break; ++ } ++ ++skip_message: ++ if (service) { ++ unlock_service(service); ++ service = NULL; ++ } ++ ++ state->rx_pos += calc_stride(size); ++ ++ DEBUG_TRACE(PARSE_LINE); ++ /* Perform some housekeeping when the end of the slot is ++ ** reached. */ ++ if ((state->rx_pos & VCHIQ_SLOT_MASK) == 0) { ++ /* Remove the extra reference count. */ ++ release_slot(state, state->rx_info, NULL, NULL); ++ state->rx_data = NULL; ++ } ++ } ++ ++bail_not_ready: ++ if (service) ++ unlock_service(service); + } + + /* Called by the slot handler thread */ +-static void * ++static int + slot_handler_func(void *v) + { +- VCHIQ_STATE_T *state = (VCHIQ_STATE_T *) v; +- VCHIQ_SHARED_STATE_T *local = state->local; +- DEBUG_INITIALISE(local) +- +- while (1) { +- DEBUG_COUNT(SLOT_HANDLER_COUNT); +- DEBUG_TRACE(SLOT_HANDLER_LINE); +- remote_event_wait(&local->trigger); +- +- vcos_rmb(); +- +- DEBUG_TRACE(SLOT_HANDLER_LINE); +- if (state->poll_needed) +- { +- state->poll_needed = 0; +- +- /* Handle service polling and other rare conditions here out +- of the mainline code */ +- switch (state->conn_state) +- { +- case VCHIQ_CONNSTATE_CONNECTED: +- /* Poll the services as requested */ +- poll_services(state); +- break; +- +- case VCHIQ_CONNSTATE_PAUSING: +- if (queue_message(state, NULL, +- VCHIQ_MAKE_MSG(VCHIQ_MSG_PAUSE, 0, 0), NULL, 0, 0, 0) +- != VCHIQ_RETRY) +- { +- if (state->is_master) +- pause_bulks(state); +- vchiq_set_conn_state(state, VCHIQ_CONNSTATE_PAUSE_SENT); +- } +- else +- { +- state->poll_needed = 1; /* Retry later */ +- } +- break; +- +- case VCHIQ_CONNSTATE_RESUMING: +- if (queue_message(state, NULL, +- VCHIQ_MAKE_MSG(VCHIQ_MSG_RESUME, 0, 0), NULL, 0, 0, 0) +- != VCHIQ_RETRY) +- { +- if (state->is_master) +- resume_bulks(state); +- vchiq_set_conn_state(state, VCHIQ_CONNSTATE_CONNECTED); +- vchiq_platform_resumed(state); +- } +- else +- { +- /* This should really be impossible, since the PAUSE should +- have flushed through outstanding messages. */ +- vcos_log_error("Failed to send RESUME message"); +- vcos_demand(0); +- } +- break; +- default: +- break; +- } +- } +- +- DEBUG_TRACE(SLOT_HANDLER_LINE); +- parse_rx_slots(state); +- } +- return NULL; ++ VCHIQ_STATE_T *state = (VCHIQ_STATE_T *) v; ++ VCHIQ_SHARED_STATE_T *local = state->local; ++ DEBUG_INITIALISE(local) ++ ++ while (1) { ++ DEBUG_COUNT(SLOT_HANDLER_COUNT); ++ DEBUG_TRACE(SLOT_HANDLER_LINE); ++ remote_event_wait(&local->trigger); ++ ++ rmb(); ++ ++ DEBUG_TRACE(SLOT_HANDLER_LINE); ++ if (state->poll_needed) { ++ /* Check if we need to suspend - may change our ++ * conn_state */ ++ vchiq_platform_check_suspend(state); ++ ++ state->poll_needed = 0; ++ ++ /* Handle service polling and other rare conditions here ++ ** out of the mainline code */ ++ switch (state->conn_state) { ++ case VCHIQ_CONNSTATE_CONNECTED: ++ /* Poll the services as requested */ ++ poll_services(state); ++ break; ++ ++ case VCHIQ_CONNSTATE_PAUSING: ++ if (state->is_master) ++ pause_bulks(state); ++ if (queue_message(state, NULL, ++ VCHIQ_MAKE_MSG(VCHIQ_MSG_PAUSE, 0, 0), ++ NULL, 0, 0, 0) != VCHIQ_RETRY) { ++ vchiq_set_conn_state(state, ++ VCHIQ_CONNSTATE_PAUSE_SENT); ++ } else { ++ if (state->is_master) ++ resume_bulks(state); ++ /* Retry later */ ++ state->poll_needed = 1; ++ } ++ break; ++ ++ case VCHIQ_CONNSTATE_PAUSED: ++ vchiq_platform_resume(state); ++ break; ++ ++ case VCHIQ_CONNSTATE_RESUMING: ++ if (queue_message(state, NULL, ++ VCHIQ_MAKE_MSG(VCHIQ_MSG_RESUME, 0, 0), ++ NULL, 0, 0, 0) != VCHIQ_RETRY) { ++ if (state->is_master) ++ resume_bulks(state); ++ vchiq_set_conn_state(state, ++ VCHIQ_CONNSTATE_CONNECTED); ++ vchiq_platform_resumed(state); ++ } else { ++ /* This should really be impossible, ++ ** since the PAUSE should have flushed ++ ** through outstanding messages. */ ++ vchiq_log_error(vchiq_core_log_level, ++ "Failed to send RESUME " ++ "message"); ++ BUG(); ++ } ++ break; ++ default: ++ break; ++ } ++ ++ ++ } ++ ++ DEBUG_TRACE(SLOT_HANDLER_LINE); ++ parse_rx_slots(state); ++ } ++ return 0; + } + + + /* Called by the recycle thread */ +-static void * ++static int + recycle_func(void *v) + { +- VCHIQ_STATE_T *state = (VCHIQ_STATE_T *) v; +- VCHIQ_SHARED_STATE_T *local = state->local; ++ VCHIQ_STATE_T *state = (VCHIQ_STATE_T *) v; ++ VCHIQ_SHARED_STATE_T *local = state->local; + +- while (1) { +- remote_event_wait(&local->recycle); ++ while (1) { ++ remote_event_wait(&local->recycle); + +- vcos_mutex_lock(&state->slot_mutex); ++ process_free_queue(state); ++ } ++ return 0; ++} ++ ++ ++/* Called by the sync thread */ ++static int ++sync_func(void *v) ++{ ++ VCHIQ_STATE_T *state = (VCHIQ_STATE_T *) v; ++ VCHIQ_SHARED_STATE_T *local = state->local; ++ VCHIQ_HEADER_T *header = (VCHIQ_HEADER_T *)SLOT_DATA_FROM_INDEX(state, ++ state->remote->slot_sync); ++ ++ while (1) { ++ VCHIQ_SERVICE_T *service; ++ int msgid, size; ++ int type; ++ unsigned int localport, remoteport; ++ ++ remote_event_wait(&local->sync_trigger); ++ ++ rmb(); ++ ++ msgid = header->msgid; ++ size = header->size; ++ type = VCHIQ_MSG_TYPE(msgid); ++ localport = VCHIQ_MSG_DSTPORT(msgid); ++ remoteport = VCHIQ_MSG_SRCPORT(msgid); ++ ++ service = find_service_by_port(state, localport); ++ ++ if (!service) { ++ vchiq_log_error(vchiq_sync_log_level, ++ "%d: sf %s@%x (%d->%d) - " ++ "invalid/closed service %d", ++ state->id, msg_type_str(type), ++ (unsigned int)header, ++ remoteport, localport, localport); ++ release_message_sync(state, header); ++ continue; ++ } ++ ++ if (vchiq_sync_log_level >= VCHIQ_LOG_TRACE) { ++ int svc_fourcc; ++ ++ svc_fourcc = service ++ ? service->base.fourcc ++ : VCHIQ_MAKE_FOURCC('?', '?', '?', '?'); ++ vchiq_log_trace(vchiq_sync_log_level, ++ "Rcvd Msg %s from %c%c%c%c s:%d d:%d len:%d", ++ msg_type_str(type), ++ VCHIQ_FOURCC_AS_4CHARS(svc_fourcc), ++ remoteport, localport, size); ++ if (size > 0) ++ vchiq_log_dump_mem("Rcvd", 0, header->data, ++ min(64, size)); ++ } ++ ++ switch (type) { ++ case VCHIQ_MSG_OPENACK: ++ vchiq_log_info(vchiq_sync_log_level, ++ "%d: sf OPENACK@%x (%d->%d)", ++ state->id, (unsigned int)header, ++ remoteport, localport); ++ if (service->srvstate == VCHIQ_SRVSTATE_OPENING) { ++ service->remoteport = remoteport; ++ vchiq_set_service_state(service, ++ VCHIQ_SRVSTATE_OPENSYNC); ++ up(&service->remove_event); ++ } ++ release_message_sync(state, header); ++ break; ++ ++ case VCHIQ_MSG_DATA: ++ vchiq_log_trace(vchiq_sync_log_level, ++ "%d: sf DATA@%x,%x (%d->%d)", ++ state->id, (unsigned int)header, size, ++ remoteport, localport); ++ ++ if ((service->remoteport == remoteport) && ++ (service->srvstate == ++ VCHIQ_SRVSTATE_OPENSYNC)) { ++ if (make_service_callback(service, ++ VCHIQ_MESSAGE_AVAILABLE, header, ++ NULL) == VCHIQ_RETRY) ++ vchiq_log_error(vchiq_sync_log_level, ++ "synchronous callback to " ++ "service %d returns " ++ "VCHIQ_RETRY", ++ localport); ++ } ++ break; ++ ++ default: ++ vchiq_log_error(vchiq_sync_log_level, ++ "%d: sf unexpected msgid %x@%x,%x", ++ state->id, msgid, (unsigned int)header, size); ++ release_message_sync(state, header); ++ break; ++ } + +- process_free_queue(state); ++ unlock_service(service); ++ } + +- vcos_mutex_unlock(&state->slot_mutex); +- } +- return NULL; ++ return 0; + } + + + static void + init_bulk_queue(VCHIQ_BULK_QUEUE_T *queue) + { +- queue->local_insert = 0; +- queue->remote_insert = 0; +- queue->process = 0; +- queue->remote_notify = 0; +- queue->remove = 0; ++ queue->local_insert = 0; ++ queue->remote_insert = 0; ++ queue->process = 0; ++ queue->remote_notify = 0; ++ queue->remove = 0; ++} ++ ++ ++inline const char * ++get_conn_state_name(VCHIQ_CONNSTATE_T conn_state) ++{ ++ return conn_state_names[conn_state]; + } + ++ + VCHIQ_SLOT_ZERO_T * + vchiq_init_slots(void *mem_base, int mem_size) + { +- int mem_align = (VCHIQ_SLOT_SIZE - (int)mem_base) & VCHIQ_SLOT_MASK; +- VCHIQ_SLOT_ZERO_T *slot_zero = (VCHIQ_SLOT_ZERO_T *)((char *)mem_base + mem_align); +- int num_slots = (mem_size - mem_align)/VCHIQ_SLOT_SIZE; +- int first_data_slot = VCHIQ_SLOT_ZERO_SLOTS; +- +- /* Ensure there is enough memory to run an absolutely minimum system */ +- num_slots -= first_data_slot; +- +- if (num_slots < 4) +- { +- vcos_log_error("vchiq_init_slots - insufficient memory %x bytes", mem_size); +- return NULL; +- } +- +- memset(slot_zero, 0, sizeof(VCHIQ_SLOT_ZERO_T)); +- +- slot_zero->magic = VCHIQ_MAGIC; +- slot_zero->version = VCHIQ_VERSION; +- slot_zero->version_min = VCHIQ_VERSION_MIN; +- slot_zero->slot_zero_size = sizeof(VCHIQ_SLOT_ZERO_T); +- slot_zero->slot_size = VCHIQ_SLOT_SIZE; +- slot_zero->max_slots = VCHIQ_MAX_SLOTS; +- slot_zero->max_slots_per_side = VCHIQ_MAX_SLOTS_PER_SIDE; +- +- slot_zero->master.slot_first = first_data_slot; +- slot_zero->slave.slot_first = first_data_slot + (num_slots/2); +- slot_zero->master.slot_last = slot_zero->slave.slot_first - 1; +- slot_zero->slave.slot_last = first_data_slot + num_slots - 1; +- +- return slot_zero; +-} +- +-VCHIQ_STATUS_T +-vchiq_init_state(VCHIQ_STATE_T *state, VCHIQ_SLOT_ZERO_T *slot_zero, int is_master) +-{ +- VCHIQ_SHARED_STATE_T *local; +- VCHIQ_SHARED_STATE_T *remote; +- VCOS_THREAD_ATTR_T attrs; +- VCHIQ_STATUS_T status; +- char threadname[10]; +- static int id = 0; +- int i; +- +- vcos_log_set_level(&vchiq_core_log_category, vchiq_default_core_log_level); +- vcos_log_set_level(&vchiq_core_msg_log_category, vchiq_default_core_msg_log_level); +- vcos_log_register("vchiq_core", &vchiq_core_log_category); +- vcos_log_register("vchiq_core_msg", &vchiq_core_msg_log_category); +- +- vcos_log_warn( "%s: slot_zero = 0x%08lx, is_master = %d", __func__, (unsigned long)slot_zero, is_master ); +- +- /* Check the input configuration */ +- +- if (slot_zero->magic != VCHIQ_MAGIC) +- { +- vcos_log_error("slot_zero=%x: magic=%x (expected %x)", +- (unsigned int)slot_zero, slot_zero->magic, VCHIQ_MAGIC); +- return VCHIQ_ERROR; +- } +- +- if (slot_zero->version < VCHIQ_VERSION_MIN) +- { +- vcos_log_error("slot_zero=%x: peer_version=%x (minimum %x)", +- (unsigned int)slot_zero, slot_zero->version, VCHIQ_VERSION_MIN); +- return VCHIQ_ERROR; +- } +- +- if (VCHIQ_VERSION < slot_zero->version_min) +- { +- vcos_log_error("slot_zero=%x: version=%x (peer minimum %x)", +- (unsigned int)slot_zero, VCHIQ_VERSION, slot_zero->version_min); +- return VCHIQ_ERROR; +- } +- +- if (slot_zero->slot_zero_size != sizeof(VCHIQ_SLOT_ZERO_T)) +- { +- vcos_log_error("slot_zero=%x: slot_zero_size=%x (expected %x)", +- (unsigned int)slot_zero, slot_zero->slot_zero_size, sizeof(VCHIQ_SLOT_ZERO_T)); +- return VCHIQ_ERROR; +- } +- +- if (slot_zero->slot_size != VCHIQ_SLOT_SIZE) +- { +- vcos_log_error("slot_zero=%x: slot_size=%d (expected %d", +- (unsigned int)slot_zero, slot_zero->slot_size, VCHIQ_SLOT_SIZE); +- return VCHIQ_ERROR; +- } +- +- if (slot_zero->max_slots != VCHIQ_MAX_SLOTS) +- { +- vcos_log_error("slot_zero=%x: max_slots=%d (expected %d)", +- (unsigned int)slot_zero, slot_zero->max_slots, VCHIQ_MAX_SLOTS); +- return VCHIQ_ERROR; +- } +- +- if (slot_zero->max_slots_per_side != VCHIQ_MAX_SLOTS_PER_SIDE) +- { +- vcos_log_error("slot_zero=%x: max_slots_per_side=%d (expected %d)", +- (unsigned int)slot_zero, slot_zero->max_slots_per_side, +- VCHIQ_MAX_SLOTS_PER_SIDE); +- return VCHIQ_ERROR; +- } +- +- if (is_master) +- { +- local = &slot_zero->master; +- remote = &slot_zero->slave; +- } +- else +- { +- local = &slot_zero->slave; +- remote = &slot_zero->master; +- } +- +- if (local->initialised) +- { +- if (remote->initialised) +- vcos_log_error("vchiq: FATAL: local state has already been initialised"); +- else +- vcos_log_error("vchiq: FATAL: master/slave mismatch - two %ss", is_master ? "master" : "slave"); +- return VCHIQ_ERROR; +- } +- +- memset(state, 0, sizeof(VCHIQ_STATE_T)); +- vcos_log_warn( "%s: called", __func__); +- state->id = id++; +- state->is_master = is_master; +- +- /* +- initialize shared state pointers +- */ +- +- state->local = local; +- state->remote = remote; +- state->slot_data = (VCHIQ_SLOT_T *)slot_zero; +- +- /* +- initialize events and mutexes +- */ +- +- vcos_event_create(&state->connect, "v.connect"); +- vcos_mutex_create(&state->mutex, "v.mutex"); +- vcos_event_create(&state->trigger_event, "v.trigger_event"); +- vcos_event_create(&state->recycle_event, "v.recycle_event"); +- +- vcos_mutex_create(&state->slot_mutex, "v.slot_mutex"); +- vcos_mutex_create(&state->recycle_mutex, "v.recycle_mutex"); +- +- vcos_event_create(&state->slot_available_event, "v.slot_available_event"); +- vcos_event_create(&state->slot_remove_event, "v.slot_remove_event"); +- +- state->slot_queue_available = 0; +- +- for (i = 0; i < VCHIQ_MAX_SERVICES; i++) +- { +- VCHIQ_SERVICE_QUOTA_T *service_quota = &state->service_quotas[i]; +- vcos_event_create(&service_quota->quota_event, "v.quota_event"); +- } +- +- for (i = local->slot_first; i <= local->slot_last; i++) +- { +- local->slot_queue[state->slot_queue_available++] = i; +- } +- +- state->default_slot_quota = state->slot_queue_available/2; +- state->default_message_quota = vcos_min(state->default_slot_quota * 256, (unsigned short)~0); +- +- local->trigger.event = &state->trigger_event; +- remote_event_create(&local->trigger); +- local->tx_pos = 0; +- +- local->recycle.event = &state->recycle_event; +- remote_event_create(&local->recycle); +- local->slot_queue_recycle = state->slot_queue_available; +- +- local->debug[DEBUG_ENTRIES] = DEBUG_MAX; +- +- /* +- bring up slot handler thread +- */ +- +- vcos_thread_attr_init(&attrs); +- vcos_thread_attr_setstacksize(&attrs, VCHIQ_SLOT_HANDLER_STACK); +- vcos_thread_attr_setpriority(&attrs, VCOS_THREAD_PRI_REALTIME); +- vcos_snprintf(threadname, sizeof(threadname), "VCHIQ-%d", state->id); +- if (vcos_thread_create(&state->slot_handler_thread, threadname, +- &attrs, slot_handler_func, state) != VCOS_SUCCESS) +- { +- vcos_log_error("vchiq: FATAL: couldn't create thread %s", threadname); +- return VCHIQ_ERROR; +- } +- +- vcos_thread_attr_init(&attrs); +- vcos_thread_attr_setstacksize(&attrs, VCHIQ_SLOT_HANDLER_STACK); +- vcos_thread_attr_setpriority(&attrs, VCOS_THREAD_PRI_REALTIME); +- vcos_snprintf(threadname, sizeof(threadname), "VCHIQr-%d", state->id); +- if (vcos_thread_create(&state->recycle_thread, threadname, +- &attrs, recycle_func, state) != VCOS_SUCCESS) +- { +- vcos_log_error("vchiq: FATAL: couldn't create thread %s", threadname); +- return VCHIQ_ERROR; +- } ++ int mem_align = (VCHIQ_SLOT_SIZE - (int)mem_base) & VCHIQ_SLOT_MASK; ++ VCHIQ_SLOT_ZERO_T *slot_zero = ++ (VCHIQ_SLOT_ZERO_T *)((char *)mem_base + mem_align); ++ int num_slots = (mem_size - mem_align)/VCHIQ_SLOT_SIZE; ++ int first_data_slot = VCHIQ_SLOT_ZERO_SLOTS; ++ ++ /* Ensure there is enough memory to run an absolutely minimum system */ ++ num_slots -= first_data_slot; ++ ++ if (num_slots < 4) { ++ vchiq_log_error(vchiq_core_log_level, ++ "vchiq_init_slots - insufficient memory %x bytes", ++ mem_size); ++ return NULL; ++ } ++ ++ memset(slot_zero, 0, sizeof(VCHIQ_SLOT_ZERO_T)); ++ ++ slot_zero->magic = VCHIQ_MAGIC; ++ slot_zero->version = VCHIQ_VERSION; ++ slot_zero->version_min = VCHIQ_VERSION_MIN; ++ slot_zero->slot_zero_size = sizeof(VCHIQ_SLOT_ZERO_T); ++ slot_zero->slot_size = VCHIQ_SLOT_SIZE; ++ slot_zero->max_slots = VCHIQ_MAX_SLOTS; ++ slot_zero->max_slots_per_side = VCHIQ_MAX_SLOTS_PER_SIDE; ++ ++ slot_zero->master.slot_sync = first_data_slot; ++ slot_zero->master.slot_first = first_data_slot + 1; ++ slot_zero->master.slot_last = first_data_slot + (num_slots/2) - 1; ++ slot_zero->slave.slot_sync = first_data_slot + (num_slots/2); ++ slot_zero->slave.slot_first = first_data_slot + (num_slots/2) + 1; ++ slot_zero->slave.slot_last = first_data_slot + num_slots - 1; ++ ++ return slot_zero; ++} ++ ++VCHIQ_STATUS_T ++vchiq_init_state(VCHIQ_STATE_T *state, VCHIQ_SLOT_ZERO_T *slot_zero, ++ int is_master) ++{ ++ VCHIQ_SHARED_STATE_T *local; ++ VCHIQ_SHARED_STATE_T *remote; ++ VCHIQ_STATUS_T status; ++ char threadname[10]; ++ static int id; ++ int i; ++ ++ vchiq_log_warning(vchiq_core_log_level, ++ "%s: slot_zero = 0x%08lx, is_master = %d", ++ __func__, (unsigned long)slot_zero, is_master); ++ ++ /* Check the input configuration */ ++ ++ if (slot_zero->magic != VCHIQ_MAGIC) { ++ vchiq_loud_error_header(); ++ vchiq_loud_error("Invalid VCHIQ magic value found."); ++ vchiq_loud_error("slot_zero=%x: magic=%x (expected %x)", ++ (unsigned int)slot_zero, slot_zero->magic, VCHIQ_MAGIC); ++ vchiq_loud_error_footer(); ++ return VCHIQ_ERROR; ++ } ++ ++ if (slot_zero->version < VCHIQ_VERSION_MIN) { ++ vchiq_loud_error_header(); ++ vchiq_loud_error("Incompatible VCHIQ versions found."); ++ vchiq_loud_error("slot_zero=%x: VideoCore version=%d " ++ "(minimum %d)", ++ (unsigned int)slot_zero, slot_zero->version, ++ VCHIQ_VERSION_MIN); ++ vchiq_loud_error("Restart with a newer VideoCore image."); ++ vchiq_loud_error_footer(); ++ return VCHIQ_ERROR; ++ } ++ ++ if (VCHIQ_VERSION < slot_zero->version_min) { ++ vchiq_loud_error_header(); ++ vchiq_loud_error("Incompatible VCHIQ versions found."); ++ vchiq_loud_error("slot_zero=%x: version=%d (VideoCore " ++ "minimum %d)", ++ (unsigned int)slot_zero, VCHIQ_VERSION, ++ slot_zero->version_min); ++ vchiq_loud_error("Restart with a newer kernel."); ++ vchiq_loud_error_footer(); ++ return VCHIQ_ERROR; ++ } ++ ++ if ((slot_zero->slot_zero_size != sizeof(VCHIQ_SLOT_ZERO_T)) || ++ (slot_zero->slot_size != VCHIQ_SLOT_SIZE) || ++ (slot_zero->max_slots != VCHIQ_MAX_SLOTS) || ++ (slot_zero->max_slots_per_side != VCHIQ_MAX_SLOTS_PER_SIDE)) { ++ vchiq_loud_error_header(); ++ if (slot_zero->slot_zero_size != sizeof(VCHIQ_SLOT_ZERO_T)) ++ vchiq_loud_error("slot_zero=%x: slot_zero_size=%x " ++ "(expected %x)", ++ (unsigned int)slot_zero, ++ slot_zero->slot_zero_size, ++ sizeof(VCHIQ_SLOT_ZERO_T)); ++ if (slot_zero->slot_size != VCHIQ_SLOT_SIZE) ++ vchiq_loud_error("slot_zero=%x: slot_size=%d " ++ "(expected %d", ++ (unsigned int)slot_zero, slot_zero->slot_size, ++ VCHIQ_SLOT_SIZE); ++ if (slot_zero->max_slots != VCHIQ_MAX_SLOTS) ++ vchiq_loud_error("slot_zero=%x: max_slots=%d " ++ "(expected %d)", ++ (unsigned int)slot_zero, slot_zero->max_slots, ++ VCHIQ_MAX_SLOTS); ++ if (slot_zero->max_slots_per_side != VCHIQ_MAX_SLOTS_PER_SIDE) ++ vchiq_loud_error("slot_zero=%x: max_slots_per_side=%d " ++ "(expected %d)", ++ (unsigned int)slot_zero, ++ slot_zero->max_slots_per_side, ++ VCHIQ_MAX_SLOTS_PER_SIDE); ++ vchiq_loud_error_footer(); ++ return VCHIQ_ERROR; ++ } ++ ++ if (is_master) { ++ local = &slot_zero->master; ++ remote = &slot_zero->slave; ++ } else { ++ local = &slot_zero->slave; ++ remote = &slot_zero->master; ++ } ++ ++ if (local->initialised) { ++ vchiq_loud_error_header(); ++ if (remote->initialised) ++ vchiq_loud_error("local state has already been " ++ "initialised"); ++ else ++ vchiq_loud_error("master/slave mismatch - two %ss", ++ is_master ? "master" : "slave"); ++ vchiq_loud_error_footer(); ++ return VCHIQ_ERROR; ++ } ++ ++ memset(state, 0, sizeof(VCHIQ_STATE_T)); ++ ++ state->id = id++; ++ state->is_master = is_master; ++ ++ /* ++ initialize shared state pointers ++ */ ++ ++ state->local = local; ++ state->remote = remote; ++ state->slot_data = (VCHIQ_SLOT_T *)slot_zero; ++ ++ /* ++ initialize events and mutexes ++ */ ++ ++ sema_init(&state->connect, 0); ++ mutex_init(&state->mutex); ++ sema_init(&state->trigger_event, 0); ++ sema_init(&state->recycle_event, 0); ++ sema_init(&state->sync_trigger_event, 0); ++ sema_init(&state->sync_release_event, 0); ++ ++ mutex_init(&state->slot_mutex); ++ mutex_init(&state->recycle_mutex); ++ mutex_init(&state->sync_mutex); ++ mutex_init(&state->bulk_transfer_mutex); ++ ++ sema_init(&state->slot_available_event, 0); ++ sema_init(&state->slot_remove_event, 0); ++ sema_init(&state->data_quota_event, 0); ++ ++ state->slot_queue_available = 0; ++ ++ for (i = 0; i < VCHIQ_MAX_SERVICES; i++) { ++ VCHIQ_SERVICE_QUOTA_T *service_quota = ++ &state->service_quotas[i]; ++ sema_init(&service_quota->quota_event, 0); ++ } ++ ++ for (i = local->slot_first; i <= local->slot_last; i++) { ++ local->slot_queue[state->slot_queue_available++] = i; ++ up(&state->slot_available_event); ++ } ++ ++ state->default_slot_quota = state->slot_queue_available/2; ++ state->default_message_quota = ++ min((unsigned short)(state->default_slot_quota * 256), ++ (unsigned short)~0); ++ ++ state->previous_data_index = -1; ++ state->data_use_count = 0; ++ state->data_quota = state->slot_queue_available - 1; ++ ++ local->trigger.event = &state->trigger_event; ++ remote_event_create(&local->trigger); ++ local->tx_pos = 0; ++ ++ local->recycle.event = &state->recycle_event; ++ remote_event_create(&local->recycle); ++ local->slot_queue_recycle = state->slot_queue_available; ++ ++ local->sync_trigger.event = &state->sync_trigger_event; ++ remote_event_create(&local->sync_trigger); ++ ++ local->sync_release.event = &state->sync_release_event; ++ remote_event_create(&local->sync_release); ++ ++ /* At start-of-day, the slot is empty and available */ ++ ((VCHIQ_HEADER_T *)SLOT_DATA_FROM_INDEX(state, local->slot_sync))->msgid ++ = VCHIQ_MSGID_PADDING; ++ remote_event_signal_local(&local->sync_release); ++ ++ local->debug[DEBUG_ENTRIES] = DEBUG_MAX; ++ ++ status = vchiq_platform_init_state(state); ++ ++ /* ++ bring up slot handler thread ++ */ ++ snprintf(threadname, sizeof(threadname), "VCHIQ-%d", state->id); ++ state->slot_handler_thread = kthread_create(&slot_handler_func, ++ (void *)state, ++ threadname); ++ ++ if (state->slot_handler_thread == NULL) { ++ vchiq_loud_error_header(); ++ vchiq_loud_error("couldn't create thread %s", threadname); ++ vchiq_loud_error_footer(); ++ return VCHIQ_ERROR; ++ } ++ set_user_nice(state->slot_handler_thread, -19); ++ wake_up_process(state->slot_handler_thread); ++ ++ snprintf(threadname, sizeof(threadname), "VCHIQr-%d", state->id); ++ state->recycle_thread = kthread_create(&recycle_func, ++ (void *)state, ++ threadname); ++ if (state->recycle_thread == NULL) { ++ vchiq_loud_error_header(); ++ vchiq_loud_error("couldn't create thread %s", threadname); ++ vchiq_loud_error_footer(); ++ return VCHIQ_ERROR; ++ } ++ set_user_nice(state->recycle_thread, -19); ++ wake_up_process(state->recycle_thread); ++ ++ snprintf(threadname, sizeof(threadname), "VCHIQs-%d", state->id); ++ state->sync_thread = kthread_create(&sync_func, ++ (void *)state, ++ threadname); ++ if (state->sync_thread == NULL) { ++ vchiq_loud_error_header(); ++ vchiq_loud_error("couldn't create thread %s", threadname); ++ vchiq_loud_error_footer(); ++ return VCHIQ_ERROR; ++ } ++ set_user_nice(state->sync_thread, -20); ++ wake_up_process(state->sync_thread); + +- status = vchiq_platform_init_state(state); ++ BUG_ON(state->id >= VCHIQ_MAX_STATES); ++ vchiq_states[state->id] = state; + +- /* Indicate readiness to the other side */ +- local->initialised = 1; ++ /* Indicate readiness to the other side */ ++ local->initialised = 1; + +- return status; ++ return status; + } + + /* Called from application thread when a client or server service is created. */ + VCHIQ_SERVICE_T * + vchiq_add_service_internal(VCHIQ_STATE_T *state, +- const VCHIQ_SERVICE_PARAMS_T *params, int srvstate, +- VCHIQ_INSTANCE_T instance) ++ const VCHIQ_SERVICE_PARAMS_T *params, int srvstate, ++ VCHIQ_INSTANCE_T instance) + { +- VCHIQ_SERVICE_T **pservice = NULL; +- VCHIQ_SERVICE_T *service = NULL; +- int i; +- +- /* Prepare to use a previously unused service */ +- if (state->unused_service < VCHIQ_MAX_SERVICES) +- { +- pservice = &state->services[state->unused_service]; +- } +- +- if (srvstate == VCHIQ_SRVSTATE_OPENING) { +- for (i = 0; i < state->unused_service; i++) { +- VCHIQ_SERVICE_T *srv = state->services[i]; +- if (!srv) +- { +- pservice = &state->services[i]; +- break; +- } +- if (srv->srvstate == VCHIQ_SRVSTATE_FREE) { +- service = srv; +- break; +- } +- } +- } else { +- for (i = (state->unused_service - 1); i >= 0; i--) { +- VCHIQ_SERVICE_T *srv = state->services[i]; +- if (!srv) +- pservice = &state->services[i]; +- else if (srv->srvstate == VCHIQ_SRVSTATE_FREE) { +- service = srv; +- } else if ((srv->public_fourcc == params->fourcc) && +- ((srv->instance != instance) +- || (srv->base.callback != params->callback))) { +- /* There is another server using this fourcc which doesn't match */ +- pservice = NULL; +- service = NULL; +- } +- } +- } +- +- if (pservice && !service) +- { +- service = vcos_malloc(sizeof(VCHIQ_SERVICE_T), "VCHIQ service"); +- if (service) +- { +- service->srvstate = VCHIQ_SRVSTATE_FREE; +- service->localport = (pservice - state->services); +- vcos_event_create(&service->remove_event, "v.remove_event"); +- vcos_event_create(&service->bulk_remove_event, "v.bulk_remove_event"); +- vcos_mutex_create(&service->bulk_mutex, "v.bulk_mutex"); +- *pservice = service; +- } +- else +- { +- vcos_log_error("vchiq: Out of memory"); +- } +- } +- +- if (service) { +- VCHIQ_SERVICE_QUOTA_T *service_quota = +- &state->service_quotas[service->localport]; +- if (vcos_is_log_enabled( &vchiq_core_msg_log_category, VCOS_LOG_INFO)) { +- vcos_log_impl( &vchiq_core_msg_log_category, +- VCOS_LOG_INFO, +- "%s Service %c%c%c%c SrcPort:%d", +- ( srvstate == VCHIQ_SRVSTATE_OPENING ) +- ? "Open" : "Add", +- VCHIQ_FOURCC_AS_4CHARS(params->fourcc), +- service->localport ); +- } +- service->state = state; +- service->base.fourcc = params->fourcc; +- service->base.callback = params->callback; +- service->base.userdata = params->userdata; +- service->version = params->version; +- service->version_min = params->version_min; +- vchiq_set_service_state(service, srvstate); +- service->public_fourcc = +- (srvstate == +- VCHIQ_SRVSTATE_OPENING) ? VCHIQ_FOURCC_INVALID : params->fourcc; +- service->instance = instance; +- service->remoteport = VCHIQ_PORT_FREE; +- service->client_id = 0; +- service->auto_close = 1; +- service->service_use_count = 0; +- init_bulk_queue(&service->bulk_tx); +- init_bulk_queue(&service->bulk_rx); +- service_quota->slot_quota = state->default_slot_quota; +- service_quota->message_quota = state->default_message_quota; +- if (service_quota->slot_use_count == 0) +- service_quota->previous_tx_index = +- SLOT_QUEUE_INDEX_FROM_POS(state->local_tx_pos) - 1; +- memset(&service->stats, 0, sizeof(service->stats)); +- vcos_atomic_flags_create(&service->poll_flags); +- +- /* Ensure the events are unsignalled */ +- while (vcos_event_try(&service->remove_event) == VCOS_SUCCESS) +- continue; +- while (vcos_event_try(&service_quota->quota_event) == VCOS_SUCCESS) +- continue; +- +- if (pservice == &state->services[state->unused_service]) +- state->unused_service++; +- } ++ VCHIQ_SERVICE_T *service; ++ ++ service = kmalloc(sizeof(VCHIQ_SERVICE_T), GFP_KERNEL); ++ if (service) { ++ service->base.fourcc = params->fourcc; ++ service->base.callback = params->callback; ++ service->base.userdata = params->userdata; ++ service->handle = VCHIQ_SERVICE_HANDLE_INVALID; ++ service->ref_count = 1; ++ service->srvstate = VCHIQ_SRVSTATE_FREE; ++ service->localport = VCHIQ_PORT_FREE; ++ service->remoteport = VCHIQ_PORT_FREE; ++ ++ service->public_fourcc = (srvstate == VCHIQ_SRVSTATE_OPENING) ? ++ VCHIQ_FOURCC_INVALID : params->fourcc; ++ service->client_id = 0; ++ service->auto_close = 1; ++ service->sync = 0; ++ service->closing = 0; ++ atomic_set(&service->poll_flags, 0); ++ service->version = params->version; ++ service->version_min = params->version_min; ++ service->state = state; ++ service->instance = instance; ++ service->service_use_count = 0; ++ init_bulk_queue(&service->bulk_tx); ++ init_bulk_queue(&service->bulk_rx); ++ sema_init(&service->remove_event, 0); ++ sema_init(&service->bulk_remove_event, 0); ++ mutex_init(&service->bulk_mutex); ++ memset(&service->stats, 0, sizeof(service->stats)); ++ } else { ++ vchiq_log_error(vchiq_core_log_level, ++ "Out of memory"); ++ } ++ ++ if (service) { ++ VCHIQ_SERVICE_T **pservice = NULL; ++ int i; ++ ++ /* Although it is perfectly possible to use service_spinlock ++ ** to protect the creation of services, it is overkill as it ++ ** disables interrupts while the array is searched. ++ ** The only danger is of another thread trying to create a ++ ** service - service deletion is safe. ++ ** Therefore it is preferable to use state->mutex which, ++ ** although slower to claim, doesn't block interrupts while ++ ** it is held. ++ */ ++ ++ mutex_lock(&state->mutex); ++ ++ /* Prepare to use a previously unused service */ ++ if (state->unused_service < VCHIQ_MAX_SERVICES) ++ pservice = &state->services[state->unused_service]; ++ ++ if (srvstate == VCHIQ_SRVSTATE_OPENING) { ++ for (i = 0; i < state->unused_service; i++) { ++ VCHIQ_SERVICE_T *srv = state->services[i]; ++ if (!srv) { ++ pservice = &state->services[i]; ++ break; ++ } ++ } ++ } else { ++ for (i = (state->unused_service - 1); i >= 0; i--) { ++ VCHIQ_SERVICE_T *srv = state->services[i]; ++ if (!srv) ++ pservice = &state->services[i]; ++ else if ((srv->public_fourcc == params->fourcc) ++ && ((srv->instance != instance) || ++ (srv->base.callback != ++ params->callback))) { ++ /* There is another server using this ++ ** fourcc which doesn't match. */ ++ pservice = NULL; ++ break; ++ } ++ } ++ } ++ ++ if (pservice) { ++ service->localport = (pservice - state->services); ++ if (!handle_seq) ++ handle_seq = VCHIQ_MAX_STATES * ++ VCHIQ_MAX_SERVICES; ++ service->handle = handle_seq | ++ (state->id * VCHIQ_MAX_SERVICES) | ++ service->localport; ++ handle_seq += VCHIQ_MAX_STATES * VCHIQ_MAX_SERVICES; ++ *pservice = service; ++ if (pservice == &state->services[state->unused_service]) ++ state->unused_service++; ++ } ++ ++ mutex_unlock(&state->mutex); ++ ++ if (!pservice) { ++ kfree(service); ++ service = NULL; ++ } ++ } ++ ++ if (service) { ++ VCHIQ_SERVICE_QUOTA_T *service_quota = ++ &state->service_quotas[service->localport]; ++ service_quota->slot_quota = state->default_slot_quota; ++ service_quota->message_quota = state->default_message_quota; ++ if (service_quota->slot_use_count == 0) ++ service_quota->previous_tx_index = ++ SLOT_QUEUE_INDEX_FROM_POS(state->local_tx_pos) ++ - 1; ++ ++ /* Bring this service online */ ++ vchiq_set_service_state(service, srvstate); ++ ++ vchiq_log_info(vchiq_core_msg_log_level, ++ "%s Service %c%c%c%c SrcPort:%d", ++ (srvstate == VCHIQ_SRVSTATE_OPENING) ++ ? "Open" : "Add", ++ VCHIQ_FOURCC_AS_4CHARS(params->fourcc), ++ service->localport); ++ } ++ ++ /* Don't unlock the service - leave it with a ref_count of 1. */ + +- return service; ++ return service; + } + + VCHIQ_STATUS_T + vchiq_open_service_internal(VCHIQ_SERVICE_T *service, int client_id) + { +- VCHIQ_OPEN_PAYLOAD_T payload = { +- service->base.fourcc, +- client_id, +- service->version, +- service->version_min +- }; +- VCHIQ_ELEMENT_T body = { &payload, sizeof(payload) }; +- VCHIQ_STATUS_T status = VCHIQ_SUCCESS; +- +- service->client_id = client_id; +- vchiq_use_service(&service->base); +- status = queue_message(service->state, NULL, +- VCHIQ_MAKE_MSG(VCHIQ_MSG_OPEN, service->localport, 0), +- &body, 1, sizeof(payload), 1); +- if (status == VCHIQ_SUCCESS) { +- if (vcos_event_wait(&service->remove_event) != VCOS_SUCCESS) { +- status = VCHIQ_RETRY; +- vchiq_release_service(&service->base); +- } else if (service->srvstate != VCHIQ_SRVSTATE_OPEN) { +- vcos_log_info("%d: osi - srvstate = %d", service->state->id, service->srvstate); +- vcos_assert(service->srvstate == VCHIQ_SRVSTATE_CLOSEWAIT); +- status = VCHIQ_ERROR; +- VCHIQ_SERVICE_STATS_INC(service, error_count); +- vchiq_release_service(&service->base); +- } +- } +- return status; ++ struct vchiq_open_payload payload = { ++ service->base.fourcc, ++ client_id, ++ service->version, ++ service->version_min ++ }; ++ VCHIQ_ELEMENT_T body = { &payload, sizeof(payload) }; ++ VCHIQ_STATUS_T status = VCHIQ_SUCCESS; ++ ++ service->client_id = client_id; ++ vchiq_use_service_internal(service); ++ status = queue_message(service->state, NULL, ++ VCHIQ_MAKE_MSG(VCHIQ_MSG_OPEN, service->localport, 0), ++ &body, 1, sizeof(payload), 1); ++ if (status == VCHIQ_SUCCESS) { ++ if (down_interruptible(&service->remove_event) != 0) { ++ status = VCHIQ_RETRY; ++ vchiq_release_service_internal(service); ++ } else if ((service->srvstate != VCHIQ_SRVSTATE_OPEN) && ++ (service->srvstate != VCHIQ_SRVSTATE_OPENSYNC)) { ++ if (service->srvstate != VCHIQ_SRVSTATE_CLOSEWAIT) ++ vchiq_log_error(vchiq_core_log_level, ++ "%d: osi - srvstate = %s (ref %d)", ++ service->state->id, ++ srvstate_names[service->srvstate], ++ service->ref_count); ++ status = VCHIQ_ERROR; ++ VCHIQ_SERVICE_STATS_INC(service, error_count); ++ vchiq_release_service_internal(service); ++ } ++ } ++ return status; ++} ++ ++static void ++release_service_messages(VCHIQ_SERVICE_T *service) ++{ ++ VCHIQ_STATE_T *state = service->state; ++ int slot_last = state->remote->slot_last; ++ int i; ++ ++ /* Release any claimed messages */ ++ for (i = state->remote->slot_first; i <= slot_last; i++) { ++ VCHIQ_SLOT_INFO_T *slot_info = ++ SLOT_INFO_FROM_INDEX(state, i); ++ if (slot_info->release_count != slot_info->use_count) { ++ char *data = ++ (char *)SLOT_DATA_FROM_INDEX(state, i); ++ unsigned int pos, end; ++ ++ end = VCHIQ_SLOT_SIZE; ++ if (data == state->rx_data) ++ /* This buffer is still being read from - stop ++ ** at the current read position */ ++ end = state->rx_pos & VCHIQ_SLOT_MASK; ++ ++ pos = 0; ++ ++ while (pos < end) { ++ VCHIQ_HEADER_T *header = ++ (VCHIQ_HEADER_T *)(data + pos); ++ int msgid = header->msgid; ++ int port = VCHIQ_MSG_DSTPORT(msgid); ++ if ((port == service->localport) && ++ (msgid & VCHIQ_MSGID_CLAIMED)) { ++ vchiq_log_info(vchiq_core_log_level, ++ " fsi - hdr %x", ++ (unsigned int)header); ++ release_slot(state, slot_info, header, ++ NULL); ++ } ++ pos += calc_stride(header->size); ++ if (pos > VCHIQ_SLOT_SIZE) { ++ vchiq_log_error(vchiq_core_log_level, ++ "fsi - pos %x: header %x, " ++ "msgid %x, header->msgid %x, " ++ "header->size %x", ++ pos, (unsigned int)header, ++ msgid, header->msgid, ++ header->size); ++ WARN(1, "invalid slot position\n"); ++ } ++ } ++ } ++ } ++} ++ ++static int ++do_abort_bulks(VCHIQ_SERVICE_T *service) ++{ ++ VCHIQ_STATUS_T status; ++ ++ /* Abort any outstanding bulk transfers */ ++ if (mutex_lock_interruptible(&service->bulk_mutex) != 0) ++ return 0; ++ abort_outstanding_bulks(service, &service->bulk_tx); ++ abort_outstanding_bulks(service, &service->bulk_rx); ++ mutex_unlock(&service->bulk_mutex); ++ ++ status = notify_bulks(service, &service->bulk_tx, 0/*!retry_poll*/); ++ if (status == VCHIQ_SUCCESS) ++ status = notify_bulks(service, &service->bulk_rx, ++ 0/*!retry_poll*/); ++ return (status == VCHIQ_SUCCESS); ++} ++ ++static VCHIQ_STATUS_T ++close_service_complete(VCHIQ_SERVICE_T *service, int failstate) ++{ ++ VCHIQ_STATUS_T status; ++ int is_server = (service->public_fourcc != VCHIQ_FOURCC_INVALID); ++ int newstate; ++ ++ switch (service->srvstate) { ++ case VCHIQ_SRVSTATE_OPEN: ++ case VCHIQ_SRVSTATE_CLOSESENT: ++ case VCHIQ_SRVSTATE_CLOSERECVD: ++ if (is_server) ++ newstate = (service->auto_close ? ++ VCHIQ_SRVSTATE_LISTENING : ++ VCHIQ_SRVSTATE_CLOSEWAIT); ++ else ++ newstate = VCHIQ_SRVSTATE_CLOSED; ++ vchiq_set_service_state(service, newstate); ++ break; ++ default: ++ break; ++ } ++ ++ status = make_service_callback(service, ++ VCHIQ_SERVICE_CLOSED, NULL, NULL); ++ ++ if (status != VCHIQ_RETRY) { ++ int uc = service->service_use_count; ++ int i; ++ /* Complete the close process */ ++ for (i = 0; i < uc; i++) ++ /* cater for cases where close is forced and the ++ ** client may not close all it's handles */ ++ vchiq_release_service_internal(service); ++ ++ service->client_id = 0; ++ if (status == VCHIQ_ERROR) ++ /* Signal an error (fatal, since the other end ++ ** will probably have closed) */ ++ vchiq_set_service_state(service, VCHIQ_SRVSTATE_OPEN); ++ ++ if (service->srvstate == VCHIQ_SRVSTATE_CLOSED) ++ vchiq_free_service_internal(service); ++ else { ++ if (is_server) ++ service->closing = 0; ++ ++ up(&service->remove_event); ++ } ++ } else ++ vchiq_set_service_state(service, failstate); ++ ++ return status; + } + + /* Called by the slot handler */ + VCHIQ_STATUS_T + vchiq_close_service_internal(VCHIQ_SERVICE_T *service, int close_recvd) + { +- VCHIQ_STATE_T *state = service->state; +- VCHIQ_STATUS_T status = VCHIQ_SUCCESS; ++ VCHIQ_STATE_T *state = service->state; ++ VCHIQ_STATUS_T status = VCHIQ_SUCCESS; + +- vcos_log_trace("%d: csi:%d (%s)", +- service->state->id, service->localport, +- srvstate_names[service->srvstate]); +- +- switch (service->srvstate) +- { +- case VCHIQ_SRVSTATE_OPENING: +- if (close_recvd) +- { +- /* The open was rejected - tell the user */ +- vchiq_set_service_state(service, VCHIQ_SRVSTATE_CLOSEWAIT); +- vcos_event_signal(&service->remove_event); +- } +- else +- { +- /* Shutdown mid-open - let the other side know */ +- status = queue_message(state, NULL, +- VCHIQ_MAKE_MSG +- (VCHIQ_MSG_CLOSE, +- service->localport, +- VCHIQ_MSG_DSTPORT(service->remoteport)), +- NULL, 0, 0, 0); +- +- if (status == VCHIQ_SUCCESS) +- vchiq_set_service_state(service, VCHIQ_SRVSTATE_CLOSESENT); +- } +- break; +- +- case VCHIQ_SRVSTATE_OPEN: +- if (state->is_master) +- { +- /* Abort any outstanding bulk transfers */ +- vcos_mutex_lock(&service->bulk_mutex); +- abort_outstanding_bulks(service, &service->bulk_tx); +- abort_outstanding_bulks(service, &service->bulk_rx); +- status = notify_bulks(service, &service->bulk_tx); +- if (status == VCHIQ_SUCCESS) +- status = notify_bulks(service, &service->bulk_rx); +- vcos_mutex_unlock(&service->bulk_mutex); +- } +- +- if (status == VCHIQ_SUCCESS) +- status = queue_message(state, NULL, +- VCHIQ_MAKE_MSG +- (VCHIQ_MSG_CLOSE, +- service->localport, +- VCHIQ_MSG_DSTPORT(service->remoteport)), +- NULL, 0, 0, 0); +- +- if (status == VCHIQ_SUCCESS) +- { +- if (close_recvd) +- vchiq_set_service_state(service, VCHIQ_SRVSTATE_CLOSING); +- else +- vchiq_set_service_state(service, VCHIQ_SRVSTATE_CLOSESENT); +- } +- break; +- +- case VCHIQ_SRVSTATE_CLOSESENT: +- vcos_assert(close_recvd); +- +- if (!state->is_master) +- { +- /* Abort any outstanding bulk transfers */ +- vcos_mutex_lock(&service->bulk_mutex); +- abort_outstanding_bulks(service, &service->bulk_tx); +- abort_outstanding_bulks(service, &service->bulk_rx); +- status = notify_bulks(service, &service->bulk_tx); +- if (status == VCHIQ_SUCCESS) +- status = notify_bulks(service, &service->bulk_rx); +- vcos_mutex_unlock(&service->bulk_mutex); +- } +- +- if (status == VCHIQ_SUCCESS) +- vchiq_set_service_state(service, VCHIQ_SRVSTATE_CLOSING); +- break; +- +- case VCHIQ_SRVSTATE_CLOSING: +- /* We may come here after a retry */ +- vcos_assert(!close_recvd); +- break; +- +- default: +- vcos_log_error("vchiq_close_service_internal(%d) called in state %s", +- close_recvd, srvstate_names[service->srvstate]); +- vcos_assert(0); +- break; +- } +- +- if (service->srvstate == VCHIQ_SRVSTATE_CLOSING) +- { +- int i; +- int uc = service->service_use_count; +- /* Complete the close process */ +- for( i=0; iclient_id = 0; +- +- /* Now tell the client that the services is closed */ +- if (service->instance) +- { +- int oldstate = service->srvstate; +- +- /* Change the service state now for the benefit of the callback */ +- vchiq_set_service_state(service, +- ((service->public_fourcc == VCHIQ_FOURCC_INVALID) || +- !service->auto_close) ? +- VCHIQ_SRVSTATE_CLOSEWAIT : +- VCHIQ_SRVSTATE_LISTENING); +- +- status = make_service_callback(service, VCHIQ_SERVICE_CLOSED, NULL, NULL); +- +- if (status == VCHIQ_RETRY) +- { +- /* Restore the old state, to be retried later */ +- vchiq_set_service_state(service, oldstate); +- } +- else +- { +- if (status == VCHIQ_ERROR) { +- /* Signal an error (fatal, since the other end will probably have closed) */ +- vchiq_set_service_state(service, VCHIQ_SRVSTATE_OPEN); +- } +- } +- } +- +- if (status != VCHIQ_RETRY) +- { +- if (service->srvstate == VCHIQ_SRVSTATE_CLOSING) +- vchiq_set_service_state(service, VCHIQ_SRVSTATE_CLOSEWAIT); +- vcos_event_signal(&service->remove_event); +- } +- } ++ vchiq_log_info(vchiq_core_log_level, "%d: csi:%d,%d (%s)", ++ service->state->id, service->localport, close_recvd, ++ srvstate_names[service->srvstate]); ++ ++ switch (service->srvstate) { ++ case VCHIQ_SRVSTATE_CLOSED: ++ case VCHIQ_SRVSTATE_HIDDEN: ++ case VCHIQ_SRVSTATE_LISTENING: ++ case VCHIQ_SRVSTATE_CLOSEWAIT: ++ if (close_recvd) ++ vchiq_log_error(vchiq_core_log_level, ++ "vchiq_close_service_internal(1) called " ++ "in state %s", ++ srvstate_names[service->srvstate]); ++ else ++ vchiq_free_service_internal(service); ++ break; ++ case VCHIQ_SRVSTATE_OPENING: ++ if (close_recvd) { ++ /* The open was rejected - tell the user */ ++ vchiq_set_service_state(service, ++ VCHIQ_SRVSTATE_CLOSEWAIT); ++ up(&service->remove_event); ++ } else { ++ /* Shutdown mid-open - let the other side know */ ++ status = queue_message(state, service, ++ VCHIQ_MAKE_MSG ++ (VCHIQ_MSG_CLOSE, ++ service->localport, ++ VCHIQ_MSG_DSTPORT(service->remoteport)), ++ NULL, 0, 0, 0); ++ } ++ break; ++ ++ case VCHIQ_SRVSTATE_OPENSYNC: ++ mutex_lock(&state->sync_mutex); ++ /* Drop through */ ++ ++ case VCHIQ_SRVSTATE_OPEN: ++ if (state->is_master || close_recvd) { ++ if (!do_abort_bulks(service)) ++ status = VCHIQ_RETRY; ++ } ++ ++ release_service_messages(service); ++ ++ if (status == VCHIQ_SUCCESS) ++ status = queue_message(state, service, ++ VCHIQ_MAKE_MSG ++ (VCHIQ_MSG_CLOSE, ++ service->localport, ++ VCHIQ_MSG_DSTPORT(service->remoteport)), ++ NULL, 0, 0, 0); ++ ++ if (status == VCHIQ_SUCCESS) { ++ if (!close_recvd) ++ break; ++ } else if (service->srvstate == VCHIQ_SRVSTATE_OPENSYNC) { ++ mutex_unlock(&state->sync_mutex); ++ break; ++ } else ++ break; ++ ++ status = close_service_complete(service, ++ VCHIQ_SRVSTATE_CLOSERECVD); ++ break; ++ ++ case VCHIQ_SRVSTATE_CLOSESENT: ++ if (!close_recvd) ++ /* This happens when a process is killed mid-close */ ++ break; ++ ++ if (!state->is_master) { ++ if (!do_abort_bulks(service)) { ++ status = VCHIQ_RETRY; ++ break; ++ } ++ } ++ ++ if (status == VCHIQ_SUCCESS) ++ status = close_service_complete(service, ++ VCHIQ_SRVSTATE_CLOSERECVD); ++ break; ++ ++ case VCHIQ_SRVSTATE_CLOSERECVD: ++ if (!close_recvd && ++ (service->public_fourcc != VCHIQ_FOURCC_INVALID)) ++ /* Force into LISTENING mode */ ++ vchiq_set_service_state(service, ++ VCHIQ_SRVSTATE_LISTENING); ++ status = close_service_complete(service, ++ VCHIQ_SRVSTATE_CLOSERECVD); ++ break; ++ ++ default: ++ vchiq_log_error(vchiq_core_log_level, ++ "vchiq_close_service_internal(%d) called in state %s", ++ close_recvd, srvstate_names[service->srvstate]); ++ break; ++ } + +- return status; ++ return status; + } + + /* Called from the application process upon process death */ + void + vchiq_terminate_service_internal(VCHIQ_SERVICE_T *service) + { +- VCHIQ_STATE_T *state = service->state; ++ VCHIQ_STATE_T *state = service->state; + +- vcos_log_info("%d: tsi - (%d<->%d)", state->id, service->localport, service->remoteport); ++ vchiq_log_info(vchiq_core_log_level, "%d: tsi - (%d<->%d)", ++ state->id, service->localport, service->remoteport); + +- /* Disconnect from the instance, to prevent any callbacks */ +- service->instance = NULL; ++ /* Make it look like a client, because it must be removed and not ++ left in the LISTENING state. */ ++ service->public_fourcc = VCHIQ_FOURCC_INVALID; + +- /* Mark the service for termination by the slot handler */ +- request_poll(state, service, VCHIQ_POLL_TERMINATE); ++ mark_service_closing(service); ++ ++ /* Mark the service for termination by the slot handler */ ++ request_poll(state, service, VCHIQ_POLL_TERMINATE); + } + +-/* Called from the application process upon process death, and from +- vchiq_remove_service */ ++/* Called from the slot handler */ + void + vchiq_free_service_internal(VCHIQ_SERVICE_T *service) + { +- VCHIQ_STATE_T *state = service->state; +- int slot_last = state->remote->slot_last; +- int i; +- +- vcos_log_info("%d: fsi - (%d)", state->id, service->localport); +- +- vcos_mutex_lock(&state->mutex); +- +- /* Release any claimed messages */ +- for (i = state->remote->slot_first; i <= slot_last; i++) +- { +- VCHIQ_SLOT_INFO_T *slot_info = SLOT_INFO_FROM_INDEX(state, i); +- if (slot_info->release_count != slot_info->use_count) +- { +- char *data = (char *)SLOT_DATA_FROM_INDEX(state, i); +- unsigned int pos, end; +- +- end = VCHIQ_SLOT_SIZE; +- if (data == state->rx_data) +- { +- /* This buffer is still being read from - stop at the current read position */ +- end = state->rx_pos & VCHIQ_SLOT_MASK; +- } +- +- pos = 0; +- +- while (pos < end) +- { +- VCHIQ_HEADER_T *header = (VCHIQ_HEADER_T *)(data + pos); +- int msgid = header->msgid; +- int port = VCHIQ_MSG_DSTPORT(msgid); +- if (port == service->localport) +- { +- if (msgid & VCHIQ_MSGID_CLAIMED) +- { +- header->msgid = msgid & ~VCHIQ_MSGID_CLAIMED; +- vcos_log_info(" fsi - hdr %x", (unsigned int)header); +- release_slot(state, slot_info); +- } +- } +- pos += calc_stride(header->size); +- if (pos > VCHIQ_SLOT_SIZE) +- { +- vcos_log_error("fsi - pos %x: header %x, msgid %x, header->msgid %x, header->size %x", +- pos, (unsigned int)header, msgid, header->msgid, header->size); +- vcos_assert(0); +- } +- } +- } +- } +- +- vcos_assert(state->services[service->localport] == service); +- vchiq_set_service_state(service, VCHIQ_SRVSTATE_FREE); +- state->services[service->localport] = NULL; +- vcos_free(service); +- vcos_mutex_unlock(&state->mutex); ++ VCHIQ_STATE_T *state = service->state; ++ ++ vchiq_log_info(vchiq_core_log_level, "%d: fsi - (%d)", ++ state->id, service->localport); ++ ++ switch (service->srvstate) { ++ case VCHIQ_SRVSTATE_OPENING: ++ case VCHIQ_SRVSTATE_CLOSED: ++ case VCHIQ_SRVSTATE_HIDDEN: ++ case VCHIQ_SRVSTATE_LISTENING: ++ case VCHIQ_SRVSTATE_CLOSEWAIT: ++ break; ++ default: ++ vchiq_log_error(vchiq_core_log_level, ++ "%d: fsi - (%d) in state %s", ++ state->id, service->localport, ++ srvstate_names[service->srvstate]); ++ return; ++ } ++ ++ vchiq_set_service_state(service, VCHIQ_SRVSTATE_FREE); ++ ++ up(&service->remove_event); ++ ++ /* Release the initial lock */ ++ unlock_service(service); + } + + VCHIQ_STATUS_T + vchiq_connect_internal(VCHIQ_STATE_T *state, VCHIQ_INSTANCE_T instance) + { +- int i; +- +- /* Find all services registered to this client and enable them. */ +- for (i = 0; i < state->unused_service; i++) +- { +- VCHIQ_SERVICE_T *service = state->services[i]; +- if (service && (service->instance == instance)) { +- if (service->srvstate == VCHIQ_SRVSTATE_HIDDEN) +- vchiq_set_service_state(service, +- VCHIQ_SRVSTATE_LISTENING); +- } +- } +- +- if (state->conn_state == VCHIQ_CONNSTATE_DISCONNECTED) { +- if (queue_message(state, NULL, +- VCHIQ_MAKE_MSG(VCHIQ_MSG_CONNECT, 0, 0), NULL, 0, +- 0, 1) == VCHIQ_RETRY) +- return VCHIQ_RETRY; +- vcos_event_wait(&state->connect); ++ VCHIQ_SERVICE_T *service; ++ int i; + +- vchiq_set_conn_state(state, VCHIQ_CONNSTATE_CONNECTED); +- } ++ /* Find all services registered to this client and enable them. */ ++ i = 0; ++ while ((service = next_service_by_instance(state, instance, ++ &i)) != NULL) { ++ if (service->srvstate == VCHIQ_SRVSTATE_HIDDEN) ++ vchiq_set_service_state(service, ++ VCHIQ_SRVSTATE_LISTENING); ++ unlock_service(service); ++ } ++ ++ if (state->conn_state == VCHIQ_CONNSTATE_DISCONNECTED) { ++ if (queue_message(state, NULL, ++ VCHIQ_MAKE_MSG(VCHIQ_MSG_CONNECT, 0, 0), NULL, 0, ++ 0, 1) == VCHIQ_RETRY) ++ return VCHIQ_RETRY; ++ ++ vchiq_set_conn_state(state, VCHIQ_CONNSTATE_CONNECTING); ++ } ++ ++ if (state->conn_state == VCHIQ_CONNSTATE_CONNECTING) { ++ if (down_interruptible(&state->connect) != 0) ++ return VCHIQ_RETRY; ++ ++ vchiq_set_conn_state(state, VCHIQ_CONNSTATE_CONNECTED); ++ up(&state->connect); ++ } + +- return VCHIQ_SUCCESS; ++ return VCHIQ_SUCCESS; + } + + VCHIQ_STATUS_T + vchiq_shutdown_internal(VCHIQ_STATE_T *state, VCHIQ_INSTANCE_T instance) + { +- VCHIQ_STATUS_T status = VCHIQ_SUCCESS; +- int i; ++ VCHIQ_SERVICE_T *service; ++ int i; + +- /* Find all services registered to this client and close them. */ +- for (i = 0; i < state->unused_service; i++) +- { +- VCHIQ_SERVICE_T *service = state->services[i]; +- if (service && (service->instance == instance) && +- ((service->srvstate == VCHIQ_SRVSTATE_OPEN) || +- (service->srvstate == VCHIQ_SRVSTATE_LISTENING))) +- { +- status = vchiq_remove_service(&service->base); +- if (status != VCHIQ_SUCCESS) +- break; +- } +- } ++ /* Find all services registered to this client and enable them. */ ++ i = 0; ++ while ((service = next_service_by_instance(state, instance, ++ &i)) != NULL) { ++ (void)vchiq_remove_service(service->handle); ++ unlock_service(service); ++ } + +- return status; ++ return VCHIQ_SUCCESS; + } + + VCHIQ_STATUS_T + vchiq_pause_internal(VCHIQ_STATE_T *state) + { +- VCHIQ_STATUS_T status = VCHIQ_SUCCESS; ++ VCHIQ_STATUS_T status = VCHIQ_SUCCESS; + +- switch (state->conn_state) +- { +- case VCHIQ_CONNSTATE_CONNECTED: +- /* Request a pause */ +- vchiq_set_conn_state(state, VCHIQ_CONNSTATE_PAUSING); +- request_poll(state, NULL, 0); +- break; +- case VCHIQ_CONNSTATE_PAUSED: +- break; +- default: +- status = VCHIQ_ERROR; +- VCHIQ_STATS_INC(state, error_count); +- break; +- } ++ switch (state->conn_state) { ++ case VCHIQ_CONNSTATE_CONNECTED: ++ /* Request a pause */ ++ vchiq_set_conn_state(state, VCHIQ_CONNSTATE_PAUSING); ++ request_poll(state, NULL, 0); ++ break; ++ default: ++ vchiq_log_error(vchiq_core_log_level, ++ "vchiq_pause_internal in state %s\n", ++ conn_state_names[state->conn_state]); ++ status = VCHIQ_ERROR; ++ VCHIQ_STATS_INC(state, error_count); ++ break; ++ } + +- return status; ++ return status; + } + + VCHIQ_STATUS_T + vchiq_resume_internal(VCHIQ_STATE_T *state) + { +- VCHIQ_STATUS_T status = VCHIQ_SUCCESS; ++ VCHIQ_STATUS_T status = VCHIQ_SUCCESS; + +- if (state->conn_state == VCHIQ_CONNSTATE_PAUSED) +- { +- vchiq_set_conn_state(state, VCHIQ_CONNSTATE_RESUMING); +- request_poll(state, NULL, 0); +- } +- else +- { +- status = VCHIQ_ERROR; +- VCHIQ_STATS_INC(state, error_count); +- } ++ if (state->conn_state == VCHIQ_CONNSTATE_PAUSED) { ++ vchiq_set_conn_state(state, VCHIQ_CONNSTATE_RESUMING); ++ request_poll(state, NULL, 0); ++ } else { ++ status = VCHIQ_ERROR; ++ VCHIQ_STATS_INC(state, error_count); ++ } + +- return status; ++ return status; + } + + VCHIQ_STATUS_T + vchiq_close_service(VCHIQ_SERVICE_HANDLE_T handle) + { +- /* Unregister the service */ +- VCHIQ_SERVICE_T *service = (VCHIQ_SERVICE_T *) handle; +- VCHIQ_STATUS_T status = VCHIQ_ERROR; +- +- if (!is_valid_service(service)) +- return VCHIQ_ERROR; +- +- vcos_log_info("%d: close_service:%d", service->state->id, service->localport); +- +- if (service->public_fourcc != VCHIQ_FOURCC_INVALID) +- { +- if (service->srvstate == VCHIQ_SRVSTATE_CLOSEWAIT) +- { +- /* This is a non-auto-close server */ +- vchiq_set_service_state(service, VCHIQ_SRVSTATE_LISTENING); +- status = VCHIQ_SUCCESS; +- } +- } +- else +- { +- /* For clients, make it an alias of vchiq_remove_service */ +- status = vchiq_remove_service(handle); +- } ++ /* Unregister the service */ ++ VCHIQ_SERVICE_T *service = find_service_by_handle(handle); ++ VCHIQ_STATUS_T status = VCHIQ_ERROR; ++ ++ if (!service) ++ return VCHIQ_ERROR; ++ ++ vchiq_log_info(vchiq_core_log_level, ++ "%d: close_service:%d", ++ service->state->id, service->localport); ++ ++ mark_service_closing(service); ++ ++ /* Mark the service for termination by the slot handler */ ++ request_poll(service->state, service, VCHIQ_POLL_TERMINATE); ++ ++ while (1) { ++ if (down_interruptible(&service->remove_event) != 0) { ++ status = VCHIQ_RETRY; ++ break; ++ } ++ ++ if ((service->srvstate == VCHIQ_SRVSTATE_FREE) || ++ (service->srvstate == VCHIQ_SRVSTATE_LISTENING) || ++ (service->srvstate == VCHIQ_SRVSTATE_OPEN)) ++ break; ++ ++ vchiq_log_warning(vchiq_core_log_level, ++ "%d: close_service:%d - waiting in state %s", ++ service->state->id, service->localport, ++ srvstate_names[service->srvstate]); ++ } ++ ++ if ((status == VCHIQ_SUCCESS) && ++ (service->srvstate != VCHIQ_SRVSTATE_FREE) && ++ (service->srvstate != VCHIQ_SRVSTATE_LISTENING)) ++ status = VCHIQ_ERROR; + +- return status; ++ unlock_service(service); ++ ++ return status; + } + + VCHIQ_STATUS_T + vchiq_remove_service(VCHIQ_SERVICE_HANDLE_T handle) + { +- /* Unregister the service */ +- VCHIQ_SERVICE_T *service = (VCHIQ_SERVICE_T *) handle; +- VCHIQ_STATUS_T status = VCHIQ_SUCCESS; +- +- if (!is_valid_service(service)) +- return VCHIQ_ERROR; +- +- vcos_log_info("%d: remove_service:%d", service->state->id, service->localport); +- +- switch (service->srvstate) +- { +- case VCHIQ_SRVSTATE_OPENING: +- case VCHIQ_SRVSTATE_OPEN: +- /* Mark the service for termination by the slot handler */ +- request_poll(service->state, service, VCHIQ_POLL_TERMINATE); +- +- /* Drop through... */ +- case VCHIQ_SRVSTATE_CLOSESENT: +- case VCHIQ_SRVSTATE_CLOSING: +- while ((service->srvstate != VCHIQ_SRVSTATE_CLOSEWAIT) && +- (service->srvstate != VCHIQ_SRVSTATE_LISTENING)) +- { +- if (vcos_event_wait(&service->remove_event) != VCOS_SUCCESS) { +- status = VCHIQ_RETRY; +- break; +- } +- } +- break; +- +- default: +- break; +- } +- +- if (status == VCHIQ_SUCCESS) { +- if (service->srvstate == VCHIQ_SRVSTATE_OPEN) +- status = VCHIQ_ERROR; +- else +- { +- service->instance = NULL; +- vchiq_free_service_internal(service); +- } +- } +- +- return status; +-} +- +- +-VCHIQ_STATUS_T +-vchiq_bulk_transfer(VCHIQ_SERVICE_T *service, +- VCHI_MEM_HANDLE_T memhandle, void *offset, int size, void *userdata, +- VCHIQ_BULK_MODE_T mode, VCHIQ_BULK_DIR_T dir) +-{ +- VCHIQ_BULK_QUEUE_T *queue = (dir == VCHIQ_BULK_TRANSMIT) ? +- &service->bulk_tx : &service->bulk_rx; +- VCHIQ_BULK_T *bulk; +- VCHIQ_STATE_T *state; +- BULK_WAITER_T bulk_waiter; +- const char dir_char = (dir == VCHIQ_BULK_TRANSMIT) ? 't' : 'r'; +- const int dir_msgtype = (dir == VCHIQ_BULK_TRANSMIT) ? VCHIQ_MSG_BULK_TX : VCHIQ_MSG_BULK_RX; +- VCHIQ_STATUS_T status = VCHIQ_ERROR; +- +- if (!is_valid_service(service) || +- (service->srvstate != VCHIQ_SRVSTATE_OPEN) || +- ((memhandle == VCHI_MEM_HANDLE_INVALID) && (offset == NULL)) || +- (vchiq_check_service(service) != VCHIQ_SUCCESS)) +- return VCHIQ_ERROR; +- +- state = service->state; +- +- if (vcos_mutex_lock(&service->bulk_mutex) != VCOS_SUCCESS) +- return VCHIQ_RETRY; +- +- if (queue->local_insert == queue->remove + VCHIQ_NUM_SERVICE_BULKS) +- { +- VCHIQ_SERVICE_STATS_INC(service, bulk_stalls); +- do { +- vcos_mutex_unlock(&service->bulk_mutex); +- if (vcos_event_wait(&service->bulk_remove_event) != VCOS_SUCCESS) +- return VCHIQ_RETRY; +- if (vcos_mutex_lock(&service->bulk_mutex) != VCOS_SUCCESS) +- return VCHIQ_RETRY; +- } while (queue->local_insert == queue->remove + VCHIQ_NUM_SERVICE_BULKS); +- } +- +- bulk = &queue->bulks[BULK_INDEX(queue->local_insert)]; +- +- if (mode == VCHIQ_BULK_MODE_BLOCKING) +- { +- vcos_event_create(&bulk_waiter.event, "bulk_waiter"); +- bulk_waiter.actual = 0; +- userdata = &bulk_waiter; +- } +- +- bulk->mode = mode; +- bulk->dir = dir; +- bulk->userdata = userdata; +- bulk->size = size; +- bulk->actual = VCHIQ_BULK_ACTUAL_ABORTED; +- +- if (vchiq_prepare_bulk_data(bulk, memhandle, offset, size, dir) != VCHIQ_SUCCESS) +- { +- goto error_exit; +- } +- +- vcos_log_info("%d: bt (%d->%d) %cx %x@%x %x", state->id, +- service->localport, service->remoteport, dir_char, +- size, (unsigned int)bulk->data, (unsigned int)userdata); +- +- if (state->is_master) +- { +- queue->local_insert++; +- if (resolve_bulks(service, queue)) +- request_poll(state, service, (dir == VCHIQ_BULK_TRANSMIT) ? +- VCHIQ_POLL_TXNOTIFY : VCHIQ_POLL_RXNOTIFY); +- } +- else +- { +- int payload[2] = { (int)bulk->data, bulk->size }; +- VCHIQ_ELEMENT_T element = { payload, sizeof(payload) }; +- +- if (queue_message(state, NULL, +- VCHIQ_MAKE_MSG(dir_msgtype, +- service->localport, service->remoteport), +- &element, 1, sizeof(payload), 1) != VCHIQ_SUCCESS) +- { +- vchiq_complete_bulk(bulk); +- goto error_exit; +- } +- queue->local_insert++; +- queue->remote_insert++; +- } +- +- vcos_mutex_unlock(&service->bulk_mutex); +- +- vcos_log_trace("%d: bt:%d %cx li=%x ri=%x p=%x", state->id, +- service->localport, dir_char, +- queue->local_insert, queue->remote_insert, queue->process); +- +- status = VCHIQ_SUCCESS; +- +- if (mode == VCHIQ_BULK_MODE_BLOCKING) +- { +- if (vcos_event_wait(&bulk_waiter.event) != VCOS_SUCCESS) +- { +- vcos_log_info("bulk wait interrupted"); +- /* Stop notify_bulks signalling a non-existent waiter */ +- bulk->userdata = NULL; +- status = VCHIQ_ERROR; +- } +- else if (bulk_waiter.actual == VCHIQ_BULK_ACTUAL_ABORTED) +- status = VCHIQ_ERROR; ++ /* Unregister the service */ ++ VCHIQ_SERVICE_T *service = find_service_by_handle(handle); ++ VCHIQ_STATUS_T status = VCHIQ_SUCCESS; ++ ++ if (!service) ++ return VCHIQ_ERROR; ++ ++ vchiq_log_info(vchiq_core_log_level, ++ "%d: remove_service:%d", ++ service->state->id, service->localport); ++ ++ /* Make it look like a client, because it must be removed and not ++ left in the LISTENING state. */ ++ service->public_fourcc = VCHIQ_FOURCC_INVALID; ++ ++ mark_service_closing(service); ++ ++ /* Mark the service for termination by the slot handler */ ++ request_poll(service->state, service, VCHIQ_POLL_TERMINATE); ++ ++ while (1) { ++ if (down_interruptible(&service->remove_event) != 0) { ++ status = VCHIQ_RETRY; ++ break; ++ } ++ ++ if ((service->srvstate == VCHIQ_SRVSTATE_FREE) || ++ (service->srvstate == VCHIQ_SRVSTATE_OPEN)) ++ break; ++ ++ vchiq_log_warning(vchiq_core_log_level, ++ "%d: remove_service:%d - waiting in state %s", ++ service->state->id, service->localport, ++ srvstate_names[service->srvstate]); ++ } ++ ++ if ((status == VCHIQ_SUCCESS) && ++ (service->srvstate != VCHIQ_SRVSTATE_FREE)) ++ status = VCHIQ_ERROR; ++ ++ unlock_service(service); ++ ++ return status; ++} ++ ++ ++/* This function may be called by kernel threads or user threads. ++ * User threads may receive VCHIQ_RETRY to indicate that a signal has been ++ * received and the call should be retried after being returned to user ++ * context. ++ * When called in blocking mode, the userdata field points to a bulk_waiter ++ * structure. ++ */ ++VCHIQ_STATUS_T ++vchiq_bulk_transfer(VCHIQ_SERVICE_HANDLE_T handle, ++ VCHI_MEM_HANDLE_T memhandle, void *offset, int size, void *userdata, ++ VCHIQ_BULK_MODE_T mode, VCHIQ_BULK_DIR_T dir) ++{ ++ VCHIQ_SERVICE_T *service = find_service_by_handle(handle); ++ VCHIQ_BULK_QUEUE_T *queue; ++ VCHIQ_BULK_T *bulk; ++ VCHIQ_STATE_T *state; ++ struct bulk_waiter *bulk_waiter = NULL; ++ const char dir_char = (dir == VCHIQ_BULK_TRANSMIT) ? 't' : 'r'; ++ const int dir_msgtype = (dir == VCHIQ_BULK_TRANSMIT) ? ++ VCHIQ_MSG_BULK_TX : VCHIQ_MSG_BULK_RX; ++ VCHIQ_STATUS_T status = VCHIQ_ERROR; ++ ++ if (!service || ++ (service->srvstate != VCHIQ_SRVSTATE_OPEN) || ++ ((memhandle == VCHI_MEM_HANDLE_INVALID) && (offset == NULL)) || ++ (vchiq_check_service(service) != VCHIQ_SUCCESS)) ++ goto error_exit; ++ ++ switch (mode) { ++ case VCHIQ_BULK_MODE_NOCALLBACK: ++ case VCHIQ_BULK_MODE_CALLBACK: ++ break; ++ case VCHIQ_BULK_MODE_BLOCKING: ++ bulk_waiter = (struct bulk_waiter *)userdata; ++ sema_init(&bulk_waiter->event, 0); ++ bulk_waiter->actual = 0; ++ bulk_waiter->bulk = NULL; ++ break; ++ case VCHIQ_BULK_MODE_WAITING: ++ bulk_waiter = (struct bulk_waiter *)userdata; ++ bulk = bulk_waiter->bulk; ++ goto waiting; ++ default: ++ goto error_exit; ++ } ++ ++ state = service->state; ++ ++ queue = (dir == VCHIQ_BULK_TRANSMIT) ? ++ &service->bulk_tx : &service->bulk_rx; ++ ++ if (mutex_lock_interruptible(&service->bulk_mutex) != 0) { ++ status = VCHIQ_RETRY; ++ goto error_exit; ++ } ++ ++ if (queue->local_insert == queue->remove + VCHIQ_NUM_SERVICE_BULKS) { ++ VCHIQ_SERVICE_STATS_INC(service, bulk_stalls); ++ do { ++ mutex_unlock(&service->bulk_mutex); ++ if (down_interruptible(&service->bulk_remove_event) ++ != 0) { ++ status = VCHIQ_RETRY; ++ goto error_exit; ++ } ++ if (mutex_lock_interruptible(&service->bulk_mutex) ++ != 0) { ++ status = VCHIQ_RETRY; ++ goto error_exit; ++ } ++ } while (queue->local_insert == queue->remove + ++ VCHIQ_NUM_SERVICE_BULKS); ++ } ++ ++ bulk = &queue->bulks[BULK_INDEX(queue->local_insert)]; ++ ++ bulk->mode = mode; ++ bulk->dir = dir; ++ bulk->userdata = userdata; ++ bulk->size = size; ++ bulk->actual = VCHIQ_BULK_ACTUAL_ABORTED; ++ ++ if (vchiq_prepare_bulk_data(bulk, memhandle, offset, size, dir) != ++ VCHIQ_SUCCESS) ++ goto unlock_error_exit; ++ ++ wmb(); ++ ++ vchiq_log_info(vchiq_core_log_level, ++ "%d: bt (%d->%d) %cx %x@%x %x", ++ state->id, ++ service->localport, service->remoteport, dir_char, ++ size, (unsigned int)bulk->data, (unsigned int)userdata); ++ ++ if (state->is_master) { ++ queue->local_insert++; ++ if (resolve_bulks(service, queue)) ++ request_poll(state, service, ++ (dir == VCHIQ_BULK_TRANSMIT) ? ++ VCHIQ_POLL_TXNOTIFY : VCHIQ_POLL_RXNOTIFY); ++ } else { ++ int payload[2] = { (int)bulk->data, bulk->size }; ++ VCHIQ_ELEMENT_T element = { payload, sizeof(payload) }; ++ ++ status = queue_message(state, NULL, ++ VCHIQ_MAKE_MSG(dir_msgtype, ++ service->localport, service->remoteport), ++ &element, 1, sizeof(payload), 1); ++ if (status != VCHIQ_SUCCESS) { ++ vchiq_complete_bulk(bulk); ++ goto unlock_error_exit; ++ } ++ queue->local_insert++; ++ } ++ ++ mutex_unlock(&service->bulk_mutex); ++ ++ vchiq_log_trace(vchiq_core_log_level, ++ "%d: bt:%d %cx li=%x ri=%x p=%x", ++ state->id, ++ service->localport, dir_char, ++ queue->local_insert, queue->remote_insert, queue->process); ++ ++waiting: ++ unlock_service(service); ++ ++ status = VCHIQ_SUCCESS; ++ ++ if (bulk_waiter) { ++ bulk_waiter->bulk = bulk; ++ if (down_interruptible(&bulk_waiter->event) != 0) ++ status = VCHIQ_RETRY; ++ else if (bulk_waiter->actual == VCHIQ_BULK_ACTUAL_ABORTED) ++ status = VCHIQ_ERROR; ++ } + +- vcos_event_delete(&bulk_waiter.event); +- } ++ return status; + +- return status; ++unlock_error_exit: ++ mutex_unlock(&service->bulk_mutex); + + error_exit: +- if (mode == VCHIQ_BULK_MODE_BLOCKING) +- vcos_event_delete(&bulk_waiter.event); +- vcos_mutex_unlock(&service->bulk_mutex); +- +- return status; ++ if (service) ++ unlock_service(service); ++ return status; + } + + VCHIQ_STATUS_T + vchiq_queue_bulk_transmit(VCHIQ_SERVICE_HANDLE_T handle, +- const void *data, int size, void *userdata) ++ const void *data, int size, void *userdata) + { +- return vchiq_bulk_transfer((VCHIQ_SERVICE_T *)handle, +- VCHI_MEM_HANDLE_INVALID, (void *)data, size, userdata, +- VCHIQ_BULK_MODE_CALLBACK, VCHIQ_BULK_TRANSMIT); ++ return vchiq_bulk_transfer(handle, ++ VCHI_MEM_HANDLE_INVALID, (void *)data, size, userdata, ++ VCHIQ_BULK_MODE_CALLBACK, VCHIQ_BULK_TRANSMIT); + } + + VCHIQ_STATUS_T + vchiq_queue_bulk_receive(VCHIQ_SERVICE_HANDLE_T handle, void *data, int size, +- void *userdata) ++ void *userdata) + { +- return vchiq_bulk_transfer((VCHIQ_SERVICE_T *)handle, +- VCHI_MEM_HANDLE_INVALID, data, size, userdata, +- VCHIQ_BULK_MODE_CALLBACK, VCHIQ_BULK_RECEIVE); ++ return vchiq_bulk_transfer(handle, ++ VCHI_MEM_HANDLE_INVALID, data, size, userdata, ++ VCHIQ_BULK_MODE_CALLBACK, VCHIQ_BULK_RECEIVE); + } + + VCHIQ_STATUS_T + vchiq_queue_bulk_transmit_handle(VCHIQ_SERVICE_HANDLE_T handle, +- VCHI_MEM_HANDLE_T memhandle, const void *offset, int size, void *userdata) ++ VCHI_MEM_HANDLE_T memhandle, const void *offset, int size, ++ void *userdata) + { +- return vchiq_bulk_transfer((VCHIQ_SERVICE_T *)handle, +- memhandle, (void *)offset, size, userdata, +- VCHIQ_BULK_MODE_CALLBACK, VCHIQ_BULK_TRANSMIT); ++ return vchiq_bulk_transfer(handle, ++ memhandle, (void *)offset, size, userdata, ++ VCHIQ_BULK_MODE_CALLBACK, VCHIQ_BULK_TRANSMIT); + } + + VCHIQ_STATUS_T + vchiq_queue_bulk_receive_handle(VCHIQ_SERVICE_HANDLE_T handle, +- VCHI_MEM_HANDLE_T memhandle, void *offset, int size, void *userdata) ++ VCHI_MEM_HANDLE_T memhandle, void *offset, int size, ++ void *userdata) + { +- return vchiq_bulk_transfer((VCHIQ_SERVICE_T *)handle, +- memhandle, offset, size, userdata, +- VCHIQ_BULK_MODE_CALLBACK, VCHIQ_BULK_RECEIVE); ++ return vchiq_bulk_transfer(handle, ++ memhandle, offset, size, userdata, ++ VCHIQ_BULK_MODE_CALLBACK, VCHIQ_BULK_RECEIVE); + } + + VCHIQ_STATUS_T + vchiq_bulk_transmit(VCHIQ_SERVICE_HANDLE_T handle, const void *data, int size, +- void *userdata, VCHIQ_BULK_MODE_T mode) ++ void *userdata, VCHIQ_BULK_MODE_T mode) + { +- return vchiq_bulk_transfer((VCHIQ_SERVICE_T *)handle, +- VCHI_MEM_HANDLE_INVALID, (void *)data, size, userdata, +- mode, VCHIQ_BULK_TRANSMIT); ++ struct bulk_waiter bulk_waiter; ++ VCHIQ_STATUS_T status; ++ ++ switch (mode) { ++ case VCHIQ_BULK_MODE_NOCALLBACK: ++ case VCHIQ_BULK_MODE_CALLBACK: ++ break; ++ case VCHIQ_BULK_MODE_BLOCKING: ++ userdata = &bulk_waiter; ++ break; ++ default: ++ return VCHIQ_ERROR; ++ } ++ ++ status = vchiq_bulk_transfer(handle, ++ VCHI_MEM_HANDLE_INVALID, (void *)data, size, userdata, ++ mode, VCHIQ_BULK_TRANSMIT); ++ ++ /* This call is for kernel thread use and should not be interrupted */ ++ BUG_ON(status == VCHIQ_RETRY); ++ return status; + } + + VCHIQ_STATUS_T + vchiq_bulk_receive(VCHIQ_SERVICE_HANDLE_T handle, void *data, int size, +- void *userdata, VCHIQ_BULK_MODE_T mode) ++ void *userdata, VCHIQ_BULK_MODE_T mode) + { +- return vchiq_bulk_transfer((VCHIQ_SERVICE_T *)handle, +- VCHI_MEM_HANDLE_INVALID, data, size, userdata, +- mode, VCHIQ_BULK_RECEIVE); ++ struct bulk_waiter bulk_waiter; ++ VCHIQ_STATUS_T status; ++ ++ switch (mode) { ++ case VCHIQ_BULK_MODE_NOCALLBACK: ++ case VCHIQ_BULK_MODE_CALLBACK: ++ break; ++ case VCHIQ_BULK_MODE_BLOCKING: ++ userdata = &bulk_waiter; ++ break; ++ default: ++ return VCHIQ_ERROR; ++ } ++ ++ status = vchiq_bulk_transfer(handle, ++ VCHI_MEM_HANDLE_INVALID, data, size, userdata, ++ mode, VCHIQ_BULK_RECEIVE); ++ ++ /* This call is for kernel thread use and should not be interrupted */ ++ BUG_ON(status == VCHIQ_RETRY); ++ return status; + } + + VCHIQ_STATUS_T + vchiq_bulk_transmit_handle(VCHIQ_SERVICE_HANDLE_T handle, +- VCHI_MEM_HANDLE_T memhandle, const void *offset, int size, void *userdata, +- VCHIQ_BULK_MODE_T mode) ++ VCHI_MEM_HANDLE_T memhandle, const void *offset, int size, ++ void *userdata, VCHIQ_BULK_MODE_T mode) + { +- return vchiq_bulk_transfer((VCHIQ_SERVICE_T *)handle, +- memhandle, (void *)offset, size, userdata, +- mode, VCHIQ_BULK_TRANSMIT); ++ struct bulk_waiter bulk_waiter; ++ VCHIQ_STATUS_T status; ++ ++ switch (mode) { ++ case VCHIQ_BULK_MODE_NOCALLBACK: ++ case VCHIQ_BULK_MODE_CALLBACK: ++ break; ++ case VCHIQ_BULK_MODE_BLOCKING: ++ userdata = &bulk_waiter; ++ break; ++ default: ++ return VCHIQ_ERROR; ++ } ++ ++ status = vchiq_bulk_transfer(handle, ++ memhandle, (void *)offset, size, userdata, ++ mode, VCHIQ_BULK_TRANSMIT); ++ ++ /* This call is for kernel thread use and should not be interrupted */ ++ BUG_ON(status == VCHIQ_RETRY); ++ return status; + } + + VCHIQ_STATUS_T + vchiq_bulk_receive_handle(VCHIQ_SERVICE_HANDLE_T handle, +- VCHI_MEM_HANDLE_T memhandle, void *offset, int size, void *userdata, +- VCHIQ_BULK_MODE_T mode) ++ VCHI_MEM_HANDLE_T memhandle, void *offset, int size, void *userdata, ++ VCHIQ_BULK_MODE_T mode) + { +- return vchiq_bulk_transfer((VCHIQ_SERVICE_T *)handle, +- memhandle, offset, size, userdata, +- mode, VCHIQ_BULK_RECEIVE); ++ struct bulk_waiter bulk_waiter; ++ VCHIQ_STATUS_T status; ++ ++ switch (mode) { ++ case VCHIQ_BULK_MODE_NOCALLBACK: ++ case VCHIQ_BULK_MODE_CALLBACK: ++ break; ++ case VCHIQ_BULK_MODE_BLOCKING: ++ userdata = &bulk_waiter; ++ break; ++ default: ++ return VCHIQ_ERROR; ++ } ++ ++ status = vchiq_bulk_transfer(handle, ++ memhandle, offset, size, userdata, ++ mode, VCHIQ_BULK_RECEIVE); ++ ++ /* This call is for kernel thread use and should not be interrupted */ ++ BUG_ON(status == VCHIQ_RETRY); ++ return status; + } + + VCHIQ_STATUS_T + vchiq_queue_message(VCHIQ_SERVICE_HANDLE_T handle, +- const VCHIQ_ELEMENT_T *elements, int count) ++ const VCHIQ_ELEMENT_T *elements, int count) + { +- VCHIQ_SERVICE_T *service = (VCHIQ_SERVICE_T *) handle; ++ VCHIQ_SERVICE_T *service = find_service_by_handle(handle); ++ VCHIQ_STATUS_T status = VCHIQ_ERROR; ++ ++ unsigned int size = 0; ++ unsigned int i; + +- unsigned int size = 0; +- unsigned int i; ++ if (!service || ++ (vchiq_check_service(service) != VCHIQ_SUCCESS)) ++ goto error_exit; ++ ++ for (i = 0; i < (unsigned int)count; i++) { ++ if (elements[i].size) { ++ if (elements[i].data == NULL) { ++ VCHIQ_SERVICE_STATS_INC(service, error_count); ++ goto error_exit; ++ } ++ size += elements[i].size; ++ } ++ } ++ ++ if (size > VCHIQ_MAX_MSG_SIZE) { ++ VCHIQ_SERVICE_STATS_INC(service, error_count); ++ goto error_exit; ++ } ++ ++ switch (service->srvstate) { ++ case VCHIQ_SRVSTATE_OPEN: ++ status = queue_message(service->state, service, ++ VCHIQ_MAKE_MSG(VCHIQ_MSG_DATA, ++ service->localport, ++ service->remoteport), ++ elements, count, size, 1); ++ break; ++ case VCHIQ_SRVSTATE_OPENSYNC: ++ status = queue_message_sync(service->state, service, ++ VCHIQ_MAKE_MSG(VCHIQ_MSG_DATA, ++ service->localport, ++ service->remoteport), ++ elements, count, size, 1); ++ break; ++ default: ++ status = VCHIQ_ERROR; ++ break; ++ } ++ ++error_exit: ++ if (service) ++ unlock_service(service); + +- if (!is_valid_service(service) || +- (service->srvstate != VCHIQ_SRVSTATE_OPEN) || +- (vchiq_check_service(service) != VCHIQ_SUCCESS)) +- return VCHIQ_ERROR; +- +- for (i = 0; i < (unsigned int)count; i++) +- { +- if (elements[i].size) +- { +- if (elements[i].data == NULL) +- { +- VCHIQ_SERVICE_STATS_INC(service, error_count); +- return VCHIQ_ERROR; +- } +- size += elements[i].size; +- } +- } +- +- if (size > VCHIQ_MAX_MSG_SIZE) +- { +- VCHIQ_SERVICE_STATS_INC(service, error_count); +- return VCHIQ_ERROR; +- } +- +- return queue_message(service->state, service, +- VCHIQ_MAKE_MSG(VCHIQ_MSG_DATA, service->localport, +- service->remoteport), elements, count, size, 1); ++ return status; + } + + void + vchiq_release_message(VCHIQ_SERVICE_HANDLE_T handle, VCHIQ_HEADER_T *header) + { +- VCHIQ_SERVICE_T *service = (VCHIQ_SERVICE_T *)handle; +- VCHIQ_STATE_T *state; +- int slot_index; +- int msgid; ++ VCHIQ_SERVICE_T *service = find_service_by_handle(handle); ++ VCHIQ_SHARED_STATE_T *remote; ++ VCHIQ_STATE_T *state; ++ int slot_index; ++ ++ if (!service) ++ return; ++ ++ state = service->state; ++ remote = state->remote; ++ ++ slot_index = SLOT_INDEX_FROM_DATA(state, (void *)header); ++ ++ if ((slot_index >= remote->slot_first) && ++ (slot_index <= remote->slot_last)) { ++ int msgid = header->msgid; ++ if (msgid & VCHIQ_MSGID_CLAIMED) { ++ VCHIQ_SLOT_INFO_T *slot_info = ++ SLOT_INFO_FROM_INDEX(state, slot_index); ++ ++ release_slot(state, slot_info, header, service); ++ } ++ } else if (slot_index == remote->slot_sync) ++ release_message_sync(state, header); + +- if (!is_valid_service(service)) +- return; +- +- state = service->state; +- +- slot_index = SLOT_INDEX_FROM_DATA(state, (void *)header); +- +- if ((slot_index >= state->remote->slot_first) && +- (slot_index <= state->remote->slot_last) && +- ((msgid = header->msgid) & VCHIQ_MSGID_CLAIMED)) +- { +- VCHIQ_SLOT_INFO_T *slot_info = SLOT_INFO_FROM_INDEX(state, slot_index); +- +- /* Rewrite the message header to prevent a double release */ +- header->msgid = msgid & ~VCHIQ_MSGID_CLAIMED; +- +- release_slot(state, slot_info); +- } ++ unlock_service(service); + } + +-int +-vchiq_get_client_id(VCHIQ_SERVICE_HANDLE_T handle) ++static void ++release_message_sync(VCHIQ_STATE_T *state, VCHIQ_HEADER_T *header) + { +- VCHIQ_SERVICE_T *service = (VCHIQ_SERVICE_T *)handle; +- return service ? service->client_id : 0; ++ header->msgid = VCHIQ_MSGID_PADDING; ++ wmb(); ++ remote_event_signal(&state->remote->sync_release); + } + + VCHIQ_STATUS_T + vchiq_get_config(VCHIQ_INSTANCE_T instance, +- int config_size, VCHIQ_CONFIG_T *pconfig) ++ int config_size, VCHIQ_CONFIG_T *pconfig) + { +- VCHIQ_CONFIG_T config; ++ VCHIQ_CONFIG_T config; + +- vcos_unused(instance); ++ (void)instance; + +- config.max_msg_size = VCHIQ_MAX_MSG_SIZE; +- config.bulk_threshold = VCHIQ_MAX_MSG_SIZE; +- config.max_outstanding_bulks = VCHIQ_NUM_SERVICE_BULKS; +- config.max_services = VCHIQ_MAX_SERVICES; +- config.version = VCHIQ_VERSION; +- config.version_min = VCHIQ_VERSION_MIN; ++ config.max_msg_size = VCHIQ_MAX_MSG_SIZE; ++ config.bulk_threshold = VCHIQ_MAX_MSG_SIZE; ++ config.max_outstanding_bulks = VCHIQ_NUM_SERVICE_BULKS; ++ config.max_services = VCHIQ_MAX_SERVICES; ++ config.version = VCHIQ_VERSION; ++ config.version_min = VCHIQ_VERSION_MIN; + +- if (config_size > sizeof(VCHIQ_CONFIG_T)) +- return VCHIQ_ERROR; ++ if (config_size > sizeof(VCHIQ_CONFIG_T)) ++ return VCHIQ_ERROR; + +- memcpy(pconfig, &config, vcos_min(config_size, sizeof(VCHIQ_CONFIG_T))); ++ memcpy(pconfig, &config, ++ min(config_size, (int)(sizeof(VCHIQ_CONFIG_T)))); + +- return VCHIQ_SUCCESS; ++ return VCHIQ_SUCCESS; + } + + VCHIQ_STATUS_T + vchiq_set_service_option(VCHIQ_SERVICE_HANDLE_T handle, +- VCHIQ_SERVICE_OPTION_T option, int value) ++ VCHIQ_SERVICE_OPTION_T option, int value) + { +- VCHIQ_SERVICE_T *service = (VCHIQ_SERVICE_T *)handle; +- VCHIQ_STATUS_T status = VCHIQ_ERROR; ++ VCHIQ_SERVICE_T *service = find_service_by_handle(handle); ++ VCHIQ_STATUS_T status = VCHIQ_ERROR; + +- if (is_valid_service(service)) +- { +- switch (option) +- { +- case VCHIQ_SERVICE_OPTION_AUTOCLOSE: +- service->auto_close = value; +- status = VCHIQ_SUCCESS; +- break; +- +- case VCHIQ_SERVICE_OPTION_SLOT_QUOTA: +- { +- VCHIQ_SERVICE_QUOTA_T *service_quota = +- &service->state->service_quotas[service->localport]; +- if (value == 0) +- value = service->state->default_slot_quota; +- if ((value >= service_quota->slot_use_count) && +- (value < (unsigned short)~0)) +- { +- service_quota->slot_quota = value; +- if ((value >= service_quota->slot_use_count) && +- (service_quota->message_quota >= service_quota->message_use_count)) +- { +- /* Signal the service that it may have dropped below its quota */ +- vcos_event_signal(&service_quota->quota_event); +- } +- status = VCHIQ_SUCCESS; +- } +- } +- break; +- +- case VCHIQ_SERVICE_OPTION_MESSAGE_QUOTA: +- { +- VCHIQ_SERVICE_QUOTA_T *service_quota = +- &service->state->service_quotas[service->localport]; +- if (value == 0) +- value = service->state->default_message_quota; +- if ((value >= service_quota->message_use_count) && +- (value < (unsigned short)~0)) +- { +- service_quota->message_quota = value; +- if ((value >= service_quota->message_use_count) && +- (service_quota->slot_quota >= service_quota->slot_use_count)) +- { +- /* Signal the service that it may have dropped below its quota */ +- vcos_event_signal(&service_quota->quota_event); +- } +- status = VCHIQ_SUCCESS; +- } +- } +- break; +- +- default: +- break; +- } +- } ++ if (service) { ++ switch (option) { ++ case VCHIQ_SERVICE_OPTION_AUTOCLOSE: ++ service->auto_close = value; ++ status = VCHIQ_SUCCESS; ++ break; ++ ++ case VCHIQ_SERVICE_OPTION_SLOT_QUOTA: { ++ VCHIQ_SERVICE_QUOTA_T *service_quota = ++ &service->state->service_quotas[ ++ service->localport]; ++ if (value == 0) ++ value = service->state->default_slot_quota; ++ if ((value >= service_quota->slot_use_count) && ++ (value < (unsigned short)~0)) { ++ service_quota->slot_quota = value; ++ if ((value >= service_quota->slot_use_count) && ++ (service_quota->message_quota >= ++ service_quota->message_use_count)) { ++ /* Signal the service that it may have ++ ** dropped below its quota */ ++ up(&service_quota->quota_event); ++ } ++ status = VCHIQ_SUCCESS; ++ } ++ } break; ++ ++ case VCHIQ_SERVICE_OPTION_MESSAGE_QUOTA: { ++ VCHIQ_SERVICE_QUOTA_T *service_quota = ++ &service->state->service_quotas[ ++ service->localport]; ++ if (value == 0) ++ value = service->state->default_message_quota; ++ if ((value >= service_quota->message_use_count) && ++ (value < (unsigned short)~0)) { ++ service_quota->message_quota = value; ++ if ((value >= ++ service_quota->message_use_count) && ++ (service_quota->slot_quota >= ++ service_quota->slot_use_count)) ++ /* Signal the service that it may have ++ ** dropped below its quota */ ++ up(&service_quota->quota_event); ++ status = VCHIQ_SUCCESS; ++ } ++ } break; ++ ++ case VCHIQ_SERVICE_OPTION_SYNCHRONOUS: ++ if ((service->srvstate == VCHIQ_SRVSTATE_HIDDEN) || ++ (service->srvstate == ++ VCHIQ_SRVSTATE_LISTENING)) { ++ service->sync = value; ++ status = VCHIQ_SUCCESS; ++ } ++ break; ++ ++ default: ++ break; ++ } ++ unlock_service(service); ++ } + +- return status; ++ return status; + } + + void + vchiq_dump_shared_state(void *dump_context, VCHIQ_STATE_T *state, +- VCHIQ_SHARED_STATE_T *shared, const char *label) ++ VCHIQ_SHARED_STATE_T *shared, const char *label) + { +- static const char *const debug_names[] = +- { +- "", +- "SLOT_HANDLER_COUNT", +- "SLOT_HANDLER_LINE", +- "PARSE_LINE", +- "PARSE_HEADER", +- "PARSE_MSGID", +- "AWAIT_COMPLETION_LINE", +- "DEQUEUE_MESSAGE_LINE", +- "SERVICE_CALLBACK_LINE", +- "MSG_QUEUE_FULL_COUNT", +- "COMPLETION_QUEUE_FULL_COUNT" +- }; +- int i; +- +- char buf[80]; +- int len; +- len = vcos_snprintf(buf, sizeof(buf), +- " %s: slots %d-%d tx_pos=%x recycle=%x", +- label, shared->slot_first, shared->slot_last, +- shared->tx_pos, shared->slot_queue_recycle); +- vchiq_dump(dump_context, buf, len + 1); +- +- len = vcos_snprintf(buf, sizeof(buf), +- " Slots claimed:"); +- vchiq_dump(dump_context, buf, len + 1); +- +- for (i = shared->slot_first; i <= shared->slot_last; i++) +- { +- VCHIQ_SLOT_INFO_T slot_info = *SLOT_INFO_FROM_INDEX(state, i); +- if (slot_info.use_count != slot_info.release_count) +- { +- len = vcos_snprintf(buf, sizeof(buf), +- " %d: %d/%d", i, slot_info.use_count, slot_info.release_count); +- vchiq_dump(dump_context, buf, len + 1); +- } +- } +- +- for (i = 1; i < shared->debug[DEBUG_ENTRIES]; i++) +- { +- len = vcos_snprintf(buf, sizeof(buf), " DEBUG: %s = %d(%x)", +- debug_names[i], shared->debug[i], shared->debug[i]); +- vchiq_dump(dump_context, buf, len + 1); +- } ++ static const char *const debug_names[] = { ++ "", ++ "SLOT_HANDLER_COUNT", ++ "SLOT_HANDLER_LINE", ++ "PARSE_LINE", ++ "PARSE_HEADER", ++ "PARSE_MSGID", ++ "AWAIT_COMPLETION_LINE", ++ "DEQUEUE_MESSAGE_LINE", ++ "SERVICE_CALLBACK_LINE", ++ "MSG_QUEUE_FULL_COUNT", ++ "COMPLETION_QUEUE_FULL_COUNT" ++ }; ++ int i; ++ ++ char buf[80]; ++ int len; ++ len = snprintf(buf, sizeof(buf), ++ " %s: slots %d-%d tx_pos=%x recycle=%x", ++ label, shared->slot_first, shared->slot_last, ++ shared->tx_pos, shared->slot_queue_recycle); ++ vchiq_dump(dump_context, buf, len + 1); ++ ++ len = snprintf(buf, sizeof(buf), ++ " Slots claimed:"); ++ vchiq_dump(dump_context, buf, len + 1); ++ ++ for (i = shared->slot_first; i <= shared->slot_last; i++) { ++ VCHIQ_SLOT_INFO_T slot_info = *SLOT_INFO_FROM_INDEX(state, i); ++ if (slot_info.use_count != slot_info.release_count) { ++ len = snprintf(buf, sizeof(buf), ++ " %d: %d/%d", i, slot_info.use_count, ++ slot_info.release_count); ++ vchiq_dump(dump_context, buf, len + 1); ++ } ++ } ++ ++ for (i = 1; i < shared->debug[DEBUG_ENTRIES]; i++) { ++ len = snprintf(buf, sizeof(buf), " DEBUG: %s = %d(%x)", ++ debug_names[i], shared->debug[i], shared->debug[i]); ++ vchiq_dump(dump_context, buf, len + 1); ++ } + } + + void + vchiq_dump_state(void *dump_context, VCHIQ_STATE_T *state) + { +- char buf[80]; +- int len; +- int i; +- +- len = vcos_snprintf(buf, sizeof(buf), "State %d: %s", state->id, +- conn_state_names[state->conn_state]); +- vchiq_dump(dump_context, buf, len + 1); +- +- len = vcos_snprintf(buf, sizeof(buf), +- " tx_pos=%x(@%x), rx_pos=%x(@%x)", +- state->id, state->local->tx_pos, +- (uint32_t)state->tx_data + (state->local_tx_pos & VCHIQ_SLOT_MASK), +- state->rx_pos, +- (uint32_t)state->rx_data + (state->rx_pos & VCHIQ_SLOT_MASK)); +- vchiq_dump(dump_context, buf, len + 1); +- +- len = vcos_snprintf(buf, sizeof(buf), +- " Version: %d (min %d)", +- VCHIQ_VERSION, VCHIQ_VERSION_MIN); +- vchiq_dump(dump_context, buf, len + 1); +- +- if (VCHIQ_ENABLE_STATS) +- { +- len = vcos_snprintf(buf, sizeof(buf), +- " Stats: ctrl_tx_count=%d, ctrl_rx_count=%d, error_count=%d", +- state->stats.ctrl_tx_count, state->stats.ctrl_rx_count, +- state->stats.slot_stalls); +- vchiq_dump(dump_context, buf, len + 1); +- } +- +- len = vcos_snprintf(buf, sizeof(buf), +- " Slots: %d available, %d recyclable, %d stalls", +- state->slot_queue_available - SLOT_QUEUE_INDEX_FROM_POS(state->local_tx_pos), +- state->local->slot_queue_recycle - state->slot_queue_available, +- state->stats.slot_stalls); +- vchiq_dump(dump_context, buf, len + 1); +- +- vchiq_dump_platform_state(dump_context); +- +- vchiq_dump_shared_state(dump_context, state, state->local, "Local"); +- vchiq_dump_shared_state(dump_context, state, state->remote, "Remote"); +- +- vchiq_dump_platform_instances(dump_context); +- +- for (i = 0; i < state->unused_service; i++) { +- VCHIQ_SERVICE_T *service = state->services[i]; +- +- if (service && (service->srvstate != VCHIQ_SRVSTATE_FREE)) +- vchiq_dump_service_state(dump_context, service); +- } ++ char buf[80]; ++ int len; ++ int i; ++ ++ len = snprintf(buf, sizeof(buf), "State %d: %s", state->id, ++ conn_state_names[state->conn_state]); ++ vchiq_dump(dump_context, buf, len + 1); ++ ++ len = snprintf(buf, sizeof(buf), ++ " tx_pos=%x(@%x), rx_pos=%x(@%x)", ++ state->local->tx_pos, ++ (uint32_t)state->tx_data + ++ (state->local_tx_pos & VCHIQ_SLOT_MASK), ++ state->rx_pos, ++ (uint32_t)state->rx_data + ++ (state->rx_pos & VCHIQ_SLOT_MASK)); ++ vchiq_dump(dump_context, buf, len + 1); ++ ++ len = snprintf(buf, sizeof(buf), ++ " Version: %d (min %d)", ++ VCHIQ_VERSION, VCHIQ_VERSION_MIN); ++ vchiq_dump(dump_context, buf, len + 1); ++ ++ if (VCHIQ_ENABLE_STATS) { ++ len = snprintf(buf, sizeof(buf), ++ " Stats: ctrl_tx_count=%d, ctrl_rx_count=%d, " ++ "error_count=%d", ++ state->stats.ctrl_tx_count, state->stats.ctrl_rx_count, ++ state->stats.error_count); ++ vchiq_dump(dump_context, buf, len + 1); ++ } ++ ++ len = snprintf(buf, sizeof(buf), ++ " Slots: %d available (%d data), %d recyclable, %d stalls (%d data)", ++ state->slot_queue_available - ++ SLOT_QUEUE_INDEX_FROM_POS(state->local_tx_pos), ++ state->data_quota - state->data_use_count, ++ state->local->slot_queue_recycle - state->slot_queue_available, ++ state->stats.slot_stalls, state->stats.data_stalls); ++ vchiq_dump(dump_context, buf, len + 1); ++ ++ vchiq_dump_platform_state(dump_context); ++ ++ vchiq_dump_shared_state(dump_context, state, state->local, "Local"); ++ vchiq_dump_shared_state(dump_context, state, state->remote, "Remote"); ++ ++ vchiq_dump_platform_instances(dump_context); ++ ++ for (i = 0; i < state->unused_service; i++) { ++ VCHIQ_SERVICE_T *service = find_service_by_port(state, i); ++ ++ if (service) { ++ vchiq_dump_service_state(dump_context, service); ++ unlock_service(service); ++ } ++ } + } + + void + vchiq_dump_service_state(void *dump_context, VCHIQ_SERVICE_T *service) + { +- char buf[80]; +- int len; ++ char buf[80]; ++ int len; ++ ++ len = snprintf(buf, sizeof(buf), "Service %d: %s (ref %u)", ++ service->localport, srvstate_names[service->srvstate], ++ service->ref_count - 1); /*Don't include the lock just taken*/ ++ ++ if (service->srvstate != VCHIQ_SRVSTATE_FREE) { ++ char remoteport[30]; ++ VCHIQ_SERVICE_QUOTA_T *service_quota = ++ &service->state->service_quotas[service->localport]; ++ int fourcc = service->base.fourcc; ++ int tx_pending, rx_pending; ++ if (service->remoteport != VCHIQ_PORT_FREE) { ++ int len2 = snprintf(remoteport, sizeof(remoteport), ++ "%d", service->remoteport); ++ if (service->public_fourcc != VCHIQ_FOURCC_INVALID) ++ snprintf(remoteport + len2, ++ sizeof(remoteport) - len2, ++ " (client %x)", service->client_id); ++ } else ++ strcpy(remoteport, "n/a"); ++ ++ len += snprintf(buf + len, sizeof(buf) - len, ++ " '%c%c%c%c' remote %s (msg use %d/%d, slot use %d/%d)", ++ VCHIQ_FOURCC_AS_4CHARS(fourcc), ++ remoteport, ++ service_quota->message_use_count, ++ service_quota->message_quota, ++ service_quota->slot_use_count, ++ service_quota->slot_quota); ++ ++ vchiq_dump(dump_context, buf, len + 1); ++ ++ tx_pending = service->bulk_tx.local_insert - ++ service->bulk_tx.remote_insert; ++ ++ rx_pending = service->bulk_rx.local_insert - ++ service->bulk_rx.remote_insert; ++ ++ len = snprintf(buf, sizeof(buf), ++ " Bulk: tx_pending=%d (size %d)," ++ " rx_pending=%d (size %d)", ++ tx_pending, ++ tx_pending ? service->bulk_tx.bulks[ ++ BULK_INDEX(service->bulk_tx.remove)].size : 0, ++ rx_pending, ++ rx_pending ? service->bulk_rx.bulks[ ++ BULK_INDEX(service->bulk_rx.remove)].size : 0); ++ ++ if (VCHIQ_ENABLE_STATS) { ++ vchiq_dump(dump_context, buf, len + 1); ++ ++ len = snprintf(buf, sizeof(buf), ++ " Ctrl: tx_count=%d, tx_bytes=%llu, " ++ "rx_count=%d, rx_bytes=%llu", ++ service->stats.ctrl_tx_count, ++ service->stats.ctrl_tx_bytes, ++ service->stats.ctrl_rx_count, ++ service->stats.ctrl_rx_bytes); ++ vchiq_dump(dump_context, buf, len + 1); ++ ++ len = snprintf(buf, sizeof(buf), ++ " Bulk: tx_count=%d, tx_bytes=%llu, " ++ "rx_count=%d, rx_bytes=%llu", ++ service->stats.bulk_tx_count, ++ service->stats.bulk_tx_bytes, ++ service->stats.bulk_rx_count, ++ service->stats.bulk_rx_bytes); ++ vchiq_dump(dump_context, buf, len + 1); ++ ++ len = snprintf(buf, sizeof(buf), ++ " %d quota stalls, %d slot stalls, " ++ "%d bulk stalls, %d aborted, %d errors", ++ service->stats.quota_stalls, ++ service->stats.slot_stalls, ++ service->stats.bulk_stalls, ++ service->stats.bulk_aborted_count, ++ service->stats.error_count); ++ } ++ } + +- len = vcos_snprintf(buf, sizeof(buf), "Service %d: %s", +- service->localport, srvstate_names[service->srvstate]); ++ vchiq_dump(dump_context, buf, len + 1); + +- if (service->srvstate != VCHIQ_SRVSTATE_FREE) +- { +- char remoteport[30]; +- VCHIQ_SERVICE_QUOTA_T *service_quota = +- &service->state->service_quotas[service->localport]; +- int fourcc = service->base.fourcc; +- if (service->remoteport != VCHIQ_PORT_FREE) +- { +- int len2 = vcos_snprintf(remoteport, sizeof(remoteport), "%d", +- service->remoteport); +- if (service->public_fourcc != VCHIQ_FOURCC_INVALID) +- vcos_snprintf(remoteport + len2, sizeof(remoteport) - len2, +- " (client %x)", service->client_id); +- } +- else +- vcos_strcpy(remoteport, "n/a"); +- +- len += vcos_snprintf(buf + len, sizeof(buf) - len, +- " '%c%c%c%c' remote %s (msg use %d/%d, slot use %d/%d)", +- VCHIQ_FOURCC_AS_4CHARS(fourcc), +- remoteport, +- service_quota->message_use_count, +- service_quota->message_quota, +- service_quota->slot_use_count, +- service_quota->slot_quota); +- +- if (VCHIQ_ENABLE_STATS) +- { +- vchiq_dump(dump_context, buf, len + 1); +- +- len = vcos_snprintf(buf, sizeof(buf), +- " Ctrl: tx_count=%d, tx_bytes=%" PRIu64 ", rx_count=%d, rx_bytes=%" PRIu64, +- service->stats.ctrl_tx_count, service->stats.ctrl_tx_bytes, +- service->stats.ctrl_rx_count, service->stats.ctrl_rx_bytes); +- vchiq_dump(dump_context, buf, len + 1); +- +- len = vcos_snprintf(buf, sizeof(buf), +- " Bulk: tx_count=%d, tx_bytes=%" PRIu64 ", rx_count=%d, rx_bytes=%" PRIu64, +- service->stats.bulk_tx_count, service->stats.bulk_tx_bytes, +- service->stats.bulk_rx_count, service->stats.bulk_rx_bytes); +- vchiq_dump(dump_context, buf, len + 1); +- +- len = vcos_snprintf(buf, sizeof(buf), +- " %d quota stalls, %d slot stalls, %d bulk stalls, %d aborted, %d errors", +- service->stats.quota_stalls, service->stats.slot_stalls, +- service->stats.bulk_stalls, service->stats.bulk_aborted_count, +- service->stats.error_count); +- } +- } +- +- vchiq_dump(dump_context, buf, len + 1); +- +- vchiq_dump_platform_service_state(dump_context, service); +-} +- +- +-VCHIQ_STATUS_T vchiq_send_remote_use(VCHIQ_STATE_T * state) +-{ +- VCHIQ_STATUS_T status = VCHIQ_RETRY; +- if(state->conn_state != VCHIQ_CONNSTATE_DISCONNECTED) +- { +- status = queue_message(state, NULL, VCHIQ_MAKE_MSG(VCHIQ_MSG_REMOTE_USE, 0, 0), NULL, 0, 0, 0); +- } +- return status; +-} +- +-VCHIQ_STATUS_T vchiq_send_remote_release(VCHIQ_STATE_T * state) +-{ +- VCHIQ_STATUS_T status = VCHIQ_RETRY; +- if(state->conn_state != VCHIQ_CONNSTATE_DISCONNECTED) +- { +- status = queue_message(state, NULL, VCHIQ_MAKE_MSG(VCHIQ_MSG_REMOTE_RELEASE, 0, 0), NULL, 0, 0, 0); +- } +- return status; +-} +- +-VCHIQ_STATUS_T vchiq_send_remote_use_active(VCHIQ_STATE_T * state) +-{ +- VCHIQ_STATUS_T status = VCHIQ_RETRY; +- if(state->conn_state != VCHIQ_CONNSTATE_DISCONNECTED) +- { +- status = queue_message(state, NULL, VCHIQ_MAKE_MSG(VCHIQ_MSG_REMOTE_USE_ACTIVE, 0, 0), NULL, 0, 0, 0); +- } +- return status; ++ if (service->srvstate != VCHIQ_SRVSTATE_FREE) ++ vchiq_dump_platform_service_state(dump_context, service); ++} ++ ++ ++void ++vchiq_loud_error_header(void) ++{ ++ vchiq_log_error(vchiq_core_log_level, ++ "============================================================" ++ "================"); ++ vchiq_log_error(vchiq_core_log_level, ++ "============================================================" ++ "================"); ++ vchiq_log_error(vchiq_core_log_level, "====="); ++} ++ ++void ++vchiq_loud_error_footer(void) ++{ ++ vchiq_log_error(vchiq_core_log_level, "====="); ++ vchiq_log_error(vchiq_core_log_level, ++ "============================================================" ++ "================"); ++ vchiq_log_error(vchiq_core_log_level, ++ "============================================================" ++ "================"); ++} ++ ++ ++VCHIQ_STATUS_T vchiq_send_remote_use(VCHIQ_STATE_T *state) ++{ ++ VCHIQ_STATUS_T status = VCHIQ_RETRY; ++ if (state->conn_state != VCHIQ_CONNSTATE_DISCONNECTED) ++ status = queue_message(state, NULL, ++ VCHIQ_MAKE_MSG(VCHIQ_MSG_REMOTE_USE, 0, 0), ++ NULL, 0, 0, 0); ++ return status; ++} ++ ++VCHIQ_STATUS_T vchiq_send_remote_release(VCHIQ_STATE_T *state) ++{ ++ VCHIQ_STATUS_T status = VCHIQ_RETRY; ++ if (state->conn_state != VCHIQ_CONNSTATE_DISCONNECTED) ++ status = queue_message(state, NULL, ++ VCHIQ_MAKE_MSG(VCHIQ_MSG_REMOTE_RELEASE, 0, 0), ++ NULL, 0, 0, 0); ++ return status; ++} ++ ++VCHIQ_STATUS_T vchiq_send_remote_use_active(VCHIQ_STATE_T *state) ++{ ++ VCHIQ_STATUS_T status = VCHIQ_RETRY; ++ if (state->conn_state != VCHIQ_CONNSTATE_DISCONNECTED) ++ status = queue_message(state, NULL, ++ VCHIQ_MAKE_MSG(VCHIQ_MSG_REMOTE_USE_ACTIVE, 0, 0), ++ NULL, 0, 0, 0); ++ return status; ++} ++ ++void vchiq_log_dump_mem(const char *label, uint32_t addr, const void *voidMem, ++ size_t numBytes) ++{ ++ const uint8_t *mem = (const uint8_t *)voidMem; ++ size_t offset; ++ char lineBuf[100]; ++ char *s; ++ ++ while (numBytes > 0) { ++ s = lineBuf; ++ ++ for (offset = 0; offset < 16; offset++) { ++ if (offset < numBytes) ++ s += snprintf(s, 4, "%02x ", mem[offset]); ++ else ++ s += snprintf(s, 4, " "); ++ } ++ ++ for (offset = 0; offset < 16; offset++) { ++ if (offset < numBytes) { ++ uint8_t ch = mem[offset]; ++ ++ if ((ch < ' ') || (ch > '~')) ++ ch = '.'; ++ *s++ = (char)ch; ++ } ++ } ++ *s++ = '\0'; ++ ++ if ((label != NULL) && (*label != '\0')) ++ vchiq_log_trace(VCHIQ_LOG_TRACE, ++ "%s: %08x: %s", label, addr, lineBuf); ++ else ++ vchiq_log_trace(VCHIQ_LOG_TRACE, ++ "%08x: %s", addr, lineBuf); ++ ++ addr += 16; ++ mem += 16; ++ if (numBytes > 16) ++ numBytes -= 16; ++ else ++ numBytes = 0; ++ } + } +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_core.h +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_core.h 2013-07-26 19:32:49.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_core.h 2013-07-26 19:36:51.000000000 +0000 +@@ -19,58 +19,105 @@ + #ifndef VCHIQ_CORE_H + #define VCHIQ_CORE_H + ++#include ++#include ++#include ++ + #include "vchiq_cfg.h" + + #include "vchiq.h" + ++/* Run time control of log level, based on KERN_XXX level. */ ++#define VCHIQ_LOG_DEFAULT 4 ++#define VCHIQ_LOG_ERROR 3 ++#define VCHIQ_LOG_WARNING 4 ++#define VCHIQ_LOG_INFO 6 ++#define VCHIQ_LOG_TRACE 7 ++ ++#define VCHIQ_LOG_PREFIX KERN_INFO "vchiq: " ++ ++#ifndef vchiq_log_error ++#define vchiq_log_error(cat, fmt, ...) \ ++ do { if (cat >= VCHIQ_LOG_ERROR) \ ++ printk(VCHIQ_LOG_PREFIX fmt "\n", ##__VA_ARGS__); } while (0) ++#endif ++#ifndef vchiq_log_warning ++#define vchiq_log_warning(cat, fmt, ...) \ ++ do { if (cat >= VCHIQ_LOG_WARNING) \ ++ printk(VCHIQ_LOG_PREFIX fmt "\n", ##__VA_ARGS__); } while (0) ++#endif ++#ifndef vchiq_log_info ++#define vchiq_log_info(cat, fmt, ...) \ ++ do { if (cat >= VCHIQ_LOG_INFO) \ ++ printk(VCHIQ_LOG_PREFIX fmt "\n", ##__VA_ARGS__); } while (0) ++#endif ++#ifndef vchiq_log_trace ++#define vchiq_log_trace(cat, fmt, ...) \ ++ do { if (cat >= VCHIQ_LOG_TRACE) \ ++ printk(VCHIQ_LOG_PREFIX fmt "\n", ##__VA_ARGS__); } while (0) ++#endif ++ ++#define vchiq_loud_error(...) \ ++ vchiq_log_error(vchiq_core_log_level, "===== " __VA_ARGS__) ++ ++#ifndef vchiq_static_assert ++#define vchiq_static_assert(cond) __attribute__((unused)) \ ++ extern int vchiq_static_assert[(cond) ? 1 : -1] ++#endif ++ + #define IS_POW2(x) (x && ((x & (x - 1)) == 0)) + + /* Ensure that the slot size and maximum number of slots are powers of 2 */ +-vcos_static_assert(IS_POW2(VCHIQ_SLOT_SIZE)); +-vcos_static_assert(IS_POW2(VCHIQ_MAX_SLOTS)); +-vcos_static_assert(IS_POW2(VCHIQ_MAX_SLOTS_PER_SIDE)); ++vchiq_static_assert(IS_POW2(VCHIQ_SLOT_SIZE)); ++vchiq_static_assert(IS_POW2(VCHIQ_MAX_SLOTS)); ++vchiq_static_assert(IS_POW2(VCHIQ_MAX_SLOTS_PER_SIDE)); + + #define VCHIQ_SLOT_MASK (VCHIQ_SLOT_SIZE - 1) + #define VCHIQ_SLOT_QUEUE_MASK (VCHIQ_MAX_SLOTS_PER_SIDE - 1) + #define VCHIQ_SLOT_ZERO_SLOTS ((sizeof(VCHIQ_SLOT_ZERO_T) + \ +- VCHIQ_SLOT_SIZE - 1) / VCHIQ_SLOT_SIZE) ++ VCHIQ_SLOT_SIZE - 1) / VCHIQ_SLOT_SIZE) + +-#define VCHIQ_MSG_PADDING 0 // - +-#define VCHIQ_MSG_CONNECT 1 // - +-#define VCHIQ_MSG_OPEN 2 // + (srcport, -), fourcc, client_id +-#define VCHIQ_MSG_OPENACK 3 // + (srcport, dstport) +-#define VCHIQ_MSG_CLOSE 4 // + (srcport, dstport) +-#define VCHIQ_MSG_DATA 5 // + (srcport, dstport) +-#define VCHIQ_MSG_BULK_RX 6 // + (srcport, dstport), data, size +-#define VCHIQ_MSG_BULK_TX 7 // + (srcport, dstport), data, size +-#define VCHIQ_MSG_BULK_RX_DONE 8 // + (srcport, dstport), actual +-#define VCHIQ_MSG_BULK_TX_DONE 9 // + (srcport, dstport), actual +-#define VCHIQ_MSG_PAUSE 10 // - +-#define VCHIQ_MSG_RESUME 11 // - +-#define VCHIQ_MSG_REMOTE_USE 12 // - +-#define VCHIQ_MSG_REMOTE_RELEASE 13 // - +-#define VCHIQ_MSG_REMOTE_USE_ACTIVE 14 // - ++#define VCHIQ_MSG_PADDING 0 /* - */ ++#define VCHIQ_MSG_CONNECT 1 /* - */ ++#define VCHIQ_MSG_OPEN 2 /* + (srcport, -), fourcc, client_id */ ++#define VCHIQ_MSG_OPENACK 3 /* + (srcport, dstport) */ ++#define VCHIQ_MSG_CLOSE 4 /* + (srcport, dstport) */ ++#define VCHIQ_MSG_DATA 5 /* + (srcport, dstport) */ ++#define VCHIQ_MSG_BULK_RX 6 /* + (srcport, dstport), data, size */ ++#define VCHIQ_MSG_BULK_TX 7 /* + (srcport, dstport), data, size */ ++#define VCHIQ_MSG_BULK_RX_DONE 8 /* + (srcport, dstport), actual */ ++#define VCHIQ_MSG_BULK_TX_DONE 9 /* + (srcport, dstport), actual */ ++#define VCHIQ_MSG_PAUSE 10 /* - */ ++#define VCHIQ_MSG_RESUME 11 /* - */ ++#define VCHIQ_MSG_REMOTE_USE 12 /* - */ ++#define VCHIQ_MSG_REMOTE_RELEASE 13 /* - */ ++#define VCHIQ_MSG_REMOTE_USE_ACTIVE 14 /* - */ + + #define VCHIQ_PORT_MAX (VCHIQ_MAX_SERVICES - 1) + #define VCHIQ_PORT_FREE 0x1000 + #define VCHIQ_PORT_IS_VALID(port) (port < VCHIQ_PORT_FREE) +-#define VCHIQ_MAKE_MSG(type,srcport,dstport) ((type<<24) | (srcport<<12) | (dstport<<0)) ++#define VCHIQ_MAKE_MSG(type, srcport, dstport) \ ++ ((type<<24) | (srcport<<12) | (dstport<<0)) + #define VCHIQ_MSG_TYPE(msgid) ((unsigned int)msgid >> 24) +-#define VCHIQ_MSG_SRCPORT(msgid) (unsigned short)(((unsigned int)msgid >> 12) & 0xfff) +-#define VCHIQ_MSG_DSTPORT(msgid) ((unsigned short)msgid & 0xfff) ++#define VCHIQ_MSG_SRCPORT(msgid) \ ++ (unsigned short)(((unsigned int)msgid >> 12) & 0xfff) ++#define VCHIQ_MSG_DSTPORT(msgid) \ ++ ((unsigned short)msgid & 0xfff) + + #define VCHIQ_FOURCC_AS_4CHARS(fourcc) \ +- ((fourcc) >> 24) & 0xff, \ +- ((fourcc) >> 16) & 0xff, \ +- ((fourcc) >> 8) & 0xff, \ +- ((fourcc) ) & 0xff ++ ((fourcc) >> 24) & 0xff, \ ++ ((fourcc) >> 16) & 0xff, \ ++ ((fourcc) >> 8) & 0xff, \ ++ (fourcc) & 0xff + + /* Ensure the fields are wide enough */ +-vcos_static_assert(VCHIQ_MSG_SRCPORT(VCHIQ_MAKE_MSG(0,0,VCHIQ_PORT_MAX)) == 0); +-vcos_static_assert(VCHIQ_MSG_TYPE(VCHIQ_MAKE_MSG(0,VCHIQ_PORT_MAX,0)) == 0); +-vcos_static_assert((unsigned int)VCHIQ_PORT_MAX < (unsigned int)VCHIQ_PORT_FREE); ++vchiq_static_assert(VCHIQ_MSG_SRCPORT(VCHIQ_MAKE_MSG(0, 0, VCHIQ_PORT_MAX)) ++ == 0); ++vchiq_static_assert(VCHIQ_MSG_TYPE(VCHIQ_MAKE_MSG(0, VCHIQ_PORT_MAX, 0)) == 0); ++vchiq_static_assert((unsigned int)VCHIQ_PORT_MAX < ++ (unsigned int)VCHIQ_PORT_FREE); + +-#define VCHIQ_MSGID_PADDING VCHIQ_MAKE_MSG(VCHIQ_MSG_PADDING,0,0) ++#define VCHIQ_MSGID_PADDING VCHIQ_MAKE_MSG(VCHIQ_MSG_PADDING, 0, 0) + #define VCHIQ_MSGID_CLAIMED 0x40000000 + + #define VCHIQ_FOURCC_INVALID 0x00000000 +@@ -80,7 +127,7 @@ + + typedef uint32_t BITSET_T; + +-vcos_static_assert((sizeof(BITSET_T) * 8) == 32); ++vchiq_static_assert((sizeof(BITSET_T) * 8) == 32); + + #define BITSET_SIZE(b) ((b + 31) >> 5) + #define BITSET_WORD(b) (b >> 5) +@@ -91,314 +138,380 @@ + #define BITSET_CLR(bs, b) (bs[BITSET_WORD(b)] &= ~BITSET_BIT(b)) + + #if VCHIQ_ENABLE_STATS +-#define VCHIQ_STATS_INC(state, stat) (state->stats. stat ++) +-#define VCHIQ_SERVICE_STATS_INC(service, stat) (service->stats. stat ++) +-#define VCHIQ_SERVICE_STATS_ADD(service, stat, addend) (service->stats. stat += addend) ++#define VCHIQ_STATS_INC(state, stat) (state->stats. stat++) ++#define VCHIQ_SERVICE_STATS_INC(service, stat) (service->stats. stat++) ++#define VCHIQ_SERVICE_STATS_ADD(service, stat, addend) \ ++ (service->stats. stat += addend) + #else + #define VCHIQ_STATS_INC(state, stat) ((void)0) + #define VCHIQ_SERVICE_STATS_INC(service, stat) ((void)0) + #define VCHIQ_SERVICE_STATS_ADD(service, stat, addend) ((void)0) + #endif + +-enum +-{ +- DEBUG_ENTRIES, ++enum { ++ DEBUG_ENTRIES, + #if VCHIQ_ENABLE_DEBUG +- DEBUG_SLOT_HANDLER_COUNT, +- DEBUG_SLOT_HANDLER_LINE, +- DEBUG_PARSE_LINE, +- DEBUG_PARSE_HEADER, +- DEBUG_PARSE_MSGID, +- DEBUG_AWAIT_COMPLETION_LINE, +- DEBUG_DEQUEUE_MESSAGE_LINE, +- DEBUG_SERVICE_CALLBACK_LINE, +- DEBUG_MSG_QUEUE_FULL_COUNT, +- DEBUG_COMPLETION_QUEUE_FULL_COUNT, ++ DEBUG_SLOT_HANDLER_COUNT, ++ DEBUG_SLOT_HANDLER_LINE, ++ DEBUG_PARSE_LINE, ++ DEBUG_PARSE_HEADER, ++ DEBUG_PARSE_MSGID, ++ DEBUG_AWAIT_COMPLETION_LINE, ++ DEBUG_DEQUEUE_MESSAGE_LINE, ++ DEBUG_SERVICE_CALLBACK_LINE, ++ DEBUG_MSG_QUEUE_FULL_COUNT, ++ DEBUG_COMPLETION_QUEUE_FULL_COUNT, + #endif +- DEBUG_MAX ++ DEBUG_MAX + }; + + #if VCHIQ_ENABLE_DEBUG + +-#define DEBUG_INITIALISE(local) volatile int *debug_ptr = (local)->debug; +-#define DEBUG_TRACE(d) debug_ptr[DEBUG_ ## d] = __LINE__ +-#define DEBUG_VALUE(d,v) debug_ptr[DEBUG_ ## d] = (v) +-#define DEBUG_COUNT(d) debug_ptr[DEBUG_ ## d]++ ++#define DEBUG_INITIALISE(local) int *debug_ptr = (local)->debug; ++#define DEBUG_TRACE(d) \ ++ do { debug_ptr[DEBUG_ ## d] = __LINE__; dsb(); } while (0) ++#define DEBUG_VALUE(d, v) \ ++ do { debug_ptr[DEBUG_ ## d] = (v); dsb(); } while (0) ++#define DEBUG_COUNT(d) \ ++ do { debug_ptr[DEBUG_ ## d]++; dsb(); } while (0) + + #else /* VCHIQ_ENABLE_DEBUG */ + + #define DEBUG_INITIALISE(local) + #define DEBUG_TRACE(d) +-#define DEBUG_VALUE(d,v) ++#define DEBUG_VALUE(d, v) + #define DEBUG_COUNT(d) + + #endif /* VCHIQ_ENABLE_DEBUG */ + +-typedef enum +-{ +- VCHIQ_CONNSTATE_DISCONNECTED, +- VCHIQ_CONNSTATE_CONNECTED, +- VCHIQ_CONNSTATE_PAUSING, +- VCHIQ_CONNSTATE_PAUSE_SENT, +- VCHIQ_CONNSTATE_PAUSED, +- VCHIQ_CONNSTATE_RESUMING ++typedef enum { ++ VCHIQ_CONNSTATE_DISCONNECTED, ++ VCHIQ_CONNSTATE_CONNECTING, ++ VCHIQ_CONNSTATE_CONNECTED, ++ VCHIQ_CONNSTATE_PAUSING, ++ VCHIQ_CONNSTATE_PAUSE_SENT, ++ VCHIQ_CONNSTATE_PAUSED, ++ VCHIQ_CONNSTATE_RESUMING + } VCHIQ_CONNSTATE_T; + +-enum +-{ +- VCHIQ_SRVSTATE_FREE, +- VCHIQ_SRVSTATE_HIDDEN, +- VCHIQ_SRVSTATE_LISTENING, +- VCHIQ_SRVSTATE_OPENING, +- VCHIQ_SRVSTATE_OPEN, +- VCHIQ_SRVSTATE_CLOSESENT, +- VCHIQ_SRVSTATE_CLOSING, +- VCHIQ_SRVSTATE_CLOSEWAIT ++enum { ++ VCHIQ_SRVSTATE_FREE, ++ VCHIQ_SRVSTATE_HIDDEN, ++ VCHIQ_SRVSTATE_LISTENING, ++ VCHIQ_SRVSTATE_OPENING, ++ VCHIQ_SRVSTATE_OPEN, ++ VCHIQ_SRVSTATE_OPENSYNC, ++ VCHIQ_SRVSTATE_CLOSESENT, ++ VCHIQ_SRVSTATE_CLOSERECVD, ++ VCHIQ_SRVSTATE_CLOSEWAIT, ++ VCHIQ_SRVSTATE_CLOSED + }; + +-enum +-{ +- VCHIQ_POLL_TERMINATE, +- VCHIQ_POLL_TXNOTIFY, +- VCHIQ_POLL_RXNOTIFY, +- VCHIQ_POLL_COUNT ++enum { ++ VCHIQ_POLL_TERMINATE, ++ VCHIQ_POLL_TXNOTIFY, ++ VCHIQ_POLL_RXNOTIFY, ++ VCHIQ_POLL_COUNT + }; + +-typedef enum +-{ +- VCHIQ_BULK_TRANSMIT, +- VCHIQ_BULK_RECEIVE ++typedef enum { ++ VCHIQ_BULK_TRANSMIT, ++ VCHIQ_BULK_RECEIVE + } VCHIQ_BULK_DIR_T; + + typedef struct vchiq_bulk_struct { +- short mode; +- short dir; +- void *userdata; +- VCHI_MEM_HANDLE_T handle; +- void *data; +- int size; +- void *remote_data; +- int remote_size; +- int actual; ++ short mode; ++ short dir; ++ void *userdata; ++ VCHI_MEM_HANDLE_T handle; ++ void *data; ++ int size; ++ void *remote_data; ++ int remote_size; ++ int actual; + } VCHIQ_BULK_T; + + typedef struct vchiq_bulk_queue_struct { +- int local_insert; /* Where to insert the next local bulk */ +- int remote_insert; /* Where to insert the next remote bulk (master) */ +- int process; /* Bulk to transfer next */ +- int remote_notify; /* Bulk to notify the remote client of next (master) */ +- int remove; /* Bulk to notify the local client of, and remove, next */ +- VCHIQ_BULK_T bulks[VCHIQ_NUM_SERVICE_BULKS]; ++ int local_insert; /* Where to insert the next local bulk */ ++ int remote_insert; /* Where to insert the next remote bulk (master) */ ++ int process; /* Bulk to transfer next */ ++ int remote_notify; /* Bulk to notify the remote client of next (mstr) */ ++ int remove; /* Bulk to notify the local client of, and remove, ++ ** next */ ++ VCHIQ_BULK_T bulks[VCHIQ_NUM_SERVICE_BULKS]; + } VCHIQ_BULK_QUEUE_T; + + typedef struct remote_event_struct { +- volatile int armed; +- volatile int fired; +- VCOS_EVENT_T * event; ++ int armed; ++ int fired; ++ struct semaphore *event; + } REMOTE_EVENT_T; + +-typedef struct opaque_platform_state_t* VCHIQ_PLATFORM_STATE_T; ++typedef struct opaque_platform_state_t *VCHIQ_PLATFORM_STATE_T; + + typedef struct vchiq_state_struct VCHIQ_STATE_T; + + typedef struct vchiq_slot_struct { +- char data[VCHIQ_SLOT_SIZE]; ++ char data[VCHIQ_SLOT_SIZE]; + } VCHIQ_SLOT_T; + + typedef struct vchiq_slot_info_struct { +- /* Use two counters rather than one to avoid the need for a mutex. */ +- volatile short use_count; +- volatile short release_count; ++ /* Use two counters rather than one to avoid the need for a mutex. */ ++ short use_count; ++ short release_count; + } VCHIQ_SLOT_INFO_T; + + typedef struct vchiq_service_struct { +- VCHIQ_SERVICE_BASE_T base; +- volatile int srvstate; +- unsigned int localport; +- unsigned int remoteport; +- int public_fourcc; +- int client_id; +- int auto_close; +- VCOS_ATOMIC_FLAGS_T poll_flags; +- short version; +- short version_min; +- +- VCHIQ_STATE_T *state; +- VCHIQ_INSTANCE_T instance; +- +- int service_use_count; +- +- VCHIQ_BULK_QUEUE_T bulk_tx; +- VCHIQ_BULK_QUEUE_T bulk_rx; +- +- VCOS_EVENT_T remove_event; +- VCOS_EVENT_T bulk_remove_event; +- VCOS_MUTEX_T bulk_mutex; +- +- struct service_stats_struct +- { +- int quota_stalls; +- int slot_stalls; +- int bulk_stalls; +- int error_count; +- int ctrl_tx_count; +- int ctrl_rx_count; +- int bulk_tx_count; +- int bulk_rx_count; +- int bulk_aborted_count; +- uint64_t ctrl_tx_bytes; +- uint64_t ctrl_rx_bytes; +- uint64_t bulk_tx_bytes; +- uint64_t bulk_rx_bytes; +- } stats; ++ VCHIQ_SERVICE_BASE_T base; ++ VCHIQ_SERVICE_HANDLE_T handle; ++ unsigned int ref_count; ++ int srvstate; ++ unsigned int localport; ++ unsigned int remoteport; ++ int public_fourcc; ++ int client_id; ++ char auto_close; ++ char sync; ++ char closing; ++ atomic_t poll_flags; ++ short version; ++ short version_min; ++ ++ VCHIQ_STATE_T *state; ++ VCHIQ_INSTANCE_T instance; ++ ++ int service_use_count; ++ ++ VCHIQ_BULK_QUEUE_T bulk_tx; ++ VCHIQ_BULK_QUEUE_T bulk_rx; ++ ++ struct semaphore remove_event; ++ struct semaphore bulk_remove_event; ++ struct mutex bulk_mutex; ++ ++ struct service_stats_struct { ++ int quota_stalls; ++ int slot_stalls; ++ int bulk_stalls; ++ int error_count; ++ int ctrl_tx_count; ++ int ctrl_rx_count; ++ int bulk_tx_count; ++ int bulk_rx_count; ++ int bulk_aborted_count; ++ uint64_t ctrl_tx_bytes; ++ uint64_t ctrl_rx_bytes; ++ uint64_t bulk_tx_bytes; ++ uint64_t bulk_rx_bytes; ++ } stats; + } VCHIQ_SERVICE_T; + + /* The quota information is outside VCHIQ_SERVICE_T so that it can be +- statically allocated, since for accounting reasons a service's slot +- usage is carried over between users of the same port number. ++ statically allocated, since for accounting reasons a service's slot ++ usage is carried over between users of the same port number. + */ + typedef struct vchiq_service_quota_struct { +- unsigned short slot_quota; +- unsigned short slot_use_count; +- unsigned short message_quota; +- unsigned short message_use_count; +- VCOS_EVENT_T quota_event; +- int previous_tx_index; ++ unsigned short slot_quota; ++ unsigned short slot_use_count; ++ unsigned short message_quota; ++ unsigned short message_use_count; ++ struct semaphore quota_event; ++ int previous_tx_index; + } VCHIQ_SERVICE_QUOTA_T; + + typedef struct vchiq_shared_state_struct { + +- /* A non-zero value here indicates that the content is valid. */ +- int initialised; ++ /* A non-zero value here indicates that the content is valid. */ ++ int initialised; ++ ++ /* The first and last (inclusive) slots allocated to the owner. */ ++ int slot_first; ++ int slot_last; ++ ++ /* The slot allocated to synchronous messages from the owner. */ ++ int slot_sync; ++ ++ /* Signalling this event indicates that owner's slot handler thread ++ ** should run. */ ++ REMOTE_EVENT_T trigger; + +- /* The first and last (inclusive) slots allocated to the owner. */ +- int slot_first; +- int slot_last; ++ /* Indicates the byte position within the stream where the next message ++ ** will be written. The least significant bits are an index into the ++ ** slot. The next bits are the index of the slot in slot_queue. */ ++ int tx_pos; + +- /* Signalling this event indicates that owner's slot handler thread should +- run. */ +- REMOTE_EVENT_T trigger; ++ /* This event should be signalled when a slot is recycled. */ ++ REMOTE_EVENT_T recycle; + +- /* Indicates the byte position within the stream where the next message +- will be written. The least significant bits are an index into the slot. +- The next bits are the index of the slot in slot_queue. */ +- volatile int tx_pos; ++ /* The slot_queue index where the next recycled slot will be written. */ ++ int slot_queue_recycle; + +- /* This event should be signalled when a slot is recycled. */ +- REMOTE_EVENT_T recycle; ++ /* This event should be signalled when a synchronous message is sent. */ ++ REMOTE_EVENT_T sync_trigger; + +- /* The slot_queue index where the next recycled slot will be written. */ +- volatile int slot_queue_recycle; ++ /* This event should be signalled when a synchronous message has been ++ ** released. */ ++ REMOTE_EVENT_T sync_release; + +- /* A circular buffer of slot indexes. */ +- int slot_queue[VCHIQ_MAX_SLOTS_PER_SIDE]; ++ /* A circular buffer of slot indexes. */ ++ int slot_queue[VCHIQ_MAX_SLOTS_PER_SIDE]; + +- /* Debugging state */ +- volatile int debug[DEBUG_MAX]; ++ /* Debugging state */ ++ int debug[DEBUG_MAX]; + } VCHIQ_SHARED_STATE_T; + + typedef struct vchiq_slot_zero_struct { +- int magic; +- short version; +- short version_min; +- int slot_zero_size; +- int slot_size; +- int max_slots; +- int max_slots_per_side; +- int platform_data[2]; +- VCHIQ_SHARED_STATE_T master; +- VCHIQ_SHARED_STATE_T slave; +- VCHIQ_SLOT_INFO_T slots[VCHIQ_MAX_SLOTS]; ++ int magic; ++ short version; ++ short version_min; ++ int slot_zero_size; ++ int slot_size; ++ int max_slots; ++ int max_slots_per_side; ++ int platform_data[2]; ++ VCHIQ_SHARED_STATE_T master; ++ VCHIQ_SHARED_STATE_T slave; ++ VCHIQ_SLOT_INFO_T slots[VCHIQ_MAX_SLOTS]; + } VCHIQ_SLOT_ZERO_T; + + struct vchiq_state_struct { +- int id; +- int initialised; +- VCHIQ_CONNSTATE_T conn_state; +- int is_master; ++ int id; ++ int initialised; ++ VCHIQ_CONNSTATE_T conn_state; ++ int is_master; + +- VCHIQ_SHARED_STATE_T *local; +- VCHIQ_SHARED_STATE_T *remote; +- VCHIQ_SLOT_T *slot_data; ++ VCHIQ_SHARED_STATE_T *local; ++ VCHIQ_SHARED_STATE_T *remote; ++ VCHIQ_SLOT_T *slot_data; + +- unsigned short default_slot_quota; +- unsigned short default_message_quota; ++ unsigned short default_slot_quota; ++ unsigned short default_message_quota; + +- VCOS_EVENT_T connect; // event indicating connect message received +- VCOS_MUTEX_T mutex; // mutex protecting services +- VCHIQ_INSTANCE_T *instance; ++ /* Event indicating connect message received */ ++ struct semaphore connect; + +- VCOS_THREAD_T slot_handler_thread; // processes incoming messages +- VCOS_THREAD_T recycle_thread; // processes recycled slots ++ /* Mutex protecting services */ ++ struct mutex mutex; ++ VCHIQ_INSTANCE_T *instance; + +- /* Local implementation of the trigger remote event */ +- VCOS_EVENT_T trigger_event; ++ /* Processes incoming messages */ ++ struct task_struct *slot_handler_thread; + +- /* Local implementation of the recycle remote event */ +- VCOS_EVENT_T recycle_event; ++ /* Processes recycled slots */ ++ struct task_struct *recycle_thread; + +- char *tx_data; +- char *rx_data; +- VCHIQ_SLOT_INFO_T *rx_info; ++ /* Processes synchronous messages */ ++ struct task_struct *sync_thread; + +- VCOS_MUTEX_T slot_mutex; ++ /* Local implementation of the trigger remote event */ ++ struct semaphore trigger_event; + +- VCOS_MUTEX_T recycle_mutex; ++ /* Local implementation of the recycle remote event */ ++ struct semaphore recycle_event; + +- /* Indicates the byte position within the stream from where the next message +- will be read. The least significant bits are an index into the slot. +- The next bits are the index of the slot in remote->slot_queue. */ +- int rx_pos; ++ /* Local implementation of the sync trigger remote event */ ++ struct semaphore sync_trigger_event; + +- /* A cached copy of local->tx_pos. Only write to local->tx_pos, and read +- from remote->tx_pos. */ +- int local_tx_pos; ++ /* Local implementation of the sync release remote event */ ++ struct semaphore sync_release_event; + +- /* The slot_queue index of the slot to become available next. */ +- int slot_queue_available; ++ char *tx_data; ++ char *rx_data; ++ VCHIQ_SLOT_INFO_T *rx_info; + +- /* A flag to indicate if any poll has been requested */ +- int poll_needed; ++ struct mutex slot_mutex; + +- /* An array of bit sets indicating which services must be polled. */ +- VCOS_ATOMIC_FLAGS_T poll_services[BITSET_SIZE(VCHIQ_MAX_SERVICES)]; ++ struct mutex recycle_mutex; + +- /* The number of the first unused service */ +- int unused_service; ++ struct mutex sync_mutex; + +- /* Signalled when a free slot becomes available. */ +- VCOS_EVENT_T slot_available_event; ++ struct mutex bulk_transfer_mutex; + +- VCOS_EVENT_T slot_remove_event; ++ /* Indicates the byte position within the stream from where the next ++ ** message will be read. The least significant bits are an index into ++ ** the slot.The next bits are the index of the slot in ++ ** remote->slot_queue. */ ++ int rx_pos; + +- struct state_stats_struct +- { +- int slot_stalls; +- int ctrl_tx_count; +- int ctrl_rx_count; +- int error_count; +- } stats; ++ /* A cached copy of local->tx_pos. Only write to local->tx_pos, and read ++ from remote->tx_pos. */ ++ int local_tx_pos; + +- VCHIQ_SERVICE_T *services[VCHIQ_MAX_SERVICES]; +- VCHIQ_SERVICE_QUOTA_T service_quotas[VCHIQ_MAX_SERVICES]; +- VCHIQ_SLOT_INFO_T slot_info[VCHIQ_MAX_SLOTS]; ++ /* The slot_queue index of the slot to become available next. */ ++ int slot_queue_available; + +- VCHIQ_PLATFORM_STATE_T platform_state; ++ /* A flag to indicate if any poll has been requested */ ++ int poll_needed; ++ ++ /* Ths index of the previous slot used for data messages. */ ++ int previous_data_index; ++ ++ /* The number of slots occupied by data messages. */ ++ unsigned short data_use_count; ++ ++ /* The maximum number of slots to be occupied by data messages. */ ++ unsigned short data_quota; ++ ++ /* An array of bit sets indicating which services must be polled. */ ++ atomic_t poll_services[BITSET_SIZE(VCHIQ_MAX_SERVICES)]; ++ ++ /* The number of the first unused service */ ++ int unused_service; ++ ++ /* Signalled when a free slot becomes available. */ ++ struct semaphore slot_available_event; ++ ++ struct semaphore slot_remove_event; ++ ++ /* Signalled when a free data slot becomes available. */ ++ struct semaphore data_quota_event; ++ ++ struct state_stats_struct { ++ int slot_stalls; ++ int data_stalls; ++ int ctrl_tx_count; ++ int ctrl_rx_count; ++ int error_count; ++ } stats; ++ ++ VCHIQ_SERVICE_T * services[VCHIQ_MAX_SERVICES]; ++ VCHIQ_SERVICE_QUOTA_T service_quotas[VCHIQ_MAX_SERVICES]; ++ VCHIQ_SLOT_INFO_T slot_info[VCHIQ_MAX_SLOTS]; ++ ++ VCHIQ_PLATFORM_STATE_T platform_state; ++}; ++ ++struct bulk_waiter { ++ VCHIQ_BULK_T *bulk; ++ struct semaphore event; ++ int actual; + }; + ++extern spinlock_t bulk_waiter_spinlock; ++ ++extern int vchiq_core_log_level; ++extern int vchiq_core_msg_log_level; ++extern int vchiq_sync_log_level; ++ ++extern VCHIQ_STATE_T *vchiq_states[VCHIQ_MAX_STATES]; ++ ++extern const char * ++get_conn_state_name(VCHIQ_CONNSTATE_T conn_state); ++ + extern VCHIQ_SLOT_ZERO_T * + vchiq_init_slots(void *mem_base, int mem_size); + + extern VCHIQ_STATUS_T +-vchiq_init_state(VCHIQ_STATE_T *state, VCHIQ_SLOT_ZERO_T *slot_zero, int is_master); ++vchiq_init_state(VCHIQ_STATE_T *state, VCHIQ_SLOT_ZERO_T *slot_zero, ++ int is_master); + + extern VCHIQ_STATUS_T + vchiq_connect_internal(VCHIQ_STATE_T *state, VCHIQ_INSTANCE_T instance); + + extern VCHIQ_SERVICE_T * + vchiq_add_service_internal(VCHIQ_STATE_T *state, +- const VCHIQ_SERVICE_PARAMS_T *params, int srvstate, +- VCHIQ_INSTANCE_T instance); ++ const VCHIQ_SERVICE_PARAMS_T *params, int srvstate, ++ VCHIQ_INSTANCE_T instance); + + extern VCHIQ_STATUS_T + vchiq_open_service_internal(VCHIQ_SERVICE_T *service, int client_id); +@@ -425,9 +538,9 @@ + remote_event_pollall(VCHIQ_STATE_T *state); + + extern VCHIQ_STATUS_T +-vchiq_bulk_transfer(VCHIQ_SERVICE_T *service, +- VCHI_MEM_HANDLE_T memhandle, void *offset, int size, void *userdata, +- VCHIQ_BULK_MODE_T mode, VCHIQ_BULK_DIR_T dir); ++vchiq_bulk_transfer(VCHIQ_SERVICE_HANDLE_T handle, ++ VCHI_MEM_HANDLE_T memhandle, void *offset, int size, void *userdata, ++ VCHIQ_BULK_MODE_T mode, VCHIQ_BULK_DIR_T dir); + + extern void + vchiq_dump_state(void *dump_context, VCHIQ_STATE_T *state); +@@ -435,12 +548,52 @@ + extern void + vchiq_dump_service_state(void *dump_context, VCHIQ_SERVICE_T *service); + ++extern void ++vchiq_loud_error_header(void); ++ ++extern void ++vchiq_loud_error_footer(void); ++ ++extern void ++request_poll(VCHIQ_STATE_T *state, VCHIQ_SERVICE_T *service, int poll_type); ++ ++static inline VCHIQ_SERVICE_T * ++handle_to_service(VCHIQ_SERVICE_HANDLE_T handle) ++{ ++ VCHIQ_STATE_T *state = vchiq_states[(handle / VCHIQ_MAX_SERVICES) & ++ (VCHIQ_MAX_STATES - 1)]; ++ if (!state) ++ return NULL; ++ ++ return state->services[handle & (VCHIQ_MAX_SERVICES - 1)]; ++} ++ ++extern VCHIQ_SERVICE_T * ++find_service_by_handle(VCHIQ_SERVICE_HANDLE_T handle); ++ ++extern VCHIQ_SERVICE_T * ++find_service_by_port(VCHIQ_STATE_T *state, int localport); ++ ++extern VCHIQ_SERVICE_T * ++find_service_for_instance(VCHIQ_INSTANCE_T instance, ++ VCHIQ_SERVICE_HANDLE_T handle); ++ ++extern VCHIQ_SERVICE_T * ++next_service_by_instance(VCHIQ_STATE_T *state, VCHIQ_INSTANCE_T instance, ++ int *pidx); ++ ++extern void ++lock_service(VCHIQ_SERVICE_T *service); ++ ++extern void ++unlock_service(VCHIQ_SERVICE_T *service); ++ + /* The following functions are called from vchiq_core, and external +- implementations must be provided. */ ++** implementations must be provided. */ + + extern VCHIQ_STATUS_T + vchiq_prepare_bulk_data(VCHIQ_BULK_T *bulk, +- VCHI_MEM_HANDLE_T memhandle, void *offset, int size, int dir); ++ VCHI_MEM_HANDLE_T memhandle, void *offset, int size, int dir); + + extern void + vchiq_transfer_bulk(VCHIQ_BULK_T *bulk); +@@ -454,9 +607,15 @@ + extern void + remote_event_signal(REMOTE_EVENT_T *event); + ++void ++vchiq_platform_check_suspend(VCHIQ_STATE_T *state); ++ + extern void + vchiq_platform_paused(VCHIQ_STATE_T *state); + ++extern VCHIQ_STATUS_T ++vchiq_platform_resume(VCHIQ_STATE_T *state); ++ + extern void + vchiq_platform_resumed(VCHIQ_STATE_T *state); + +@@ -471,7 +630,7 @@ + + extern void + vchiq_dump_platform_service_state(void *dump_context, +- VCHIQ_SERVICE_T *service); ++ VCHIQ_SERVICE_T *service); + + extern VCHIQ_STATUS_T + vchiq_use_service_internal(VCHIQ_SERVICE_T *service); +@@ -479,28 +638,36 @@ + extern VCHIQ_STATUS_T + vchiq_release_service_internal(VCHIQ_SERVICE_T *service); + +-extern VCHIQ_STATUS_T ++extern void + vchiq_on_remote_use(VCHIQ_STATE_T *state); + +-extern VCHIQ_STATUS_T ++extern void + vchiq_on_remote_release(VCHIQ_STATE_T *state); + + extern VCHIQ_STATUS_T + vchiq_platform_init_state(VCHIQ_STATE_T *state); + ++extern VCHIQ_STATUS_T ++vchiq_check_service(VCHIQ_SERVICE_T *service); ++ + extern void + vchiq_on_remote_use_active(VCHIQ_STATE_T *state); + + extern VCHIQ_STATUS_T +-vchiq_send_remote_use(VCHIQ_STATE_T * state); ++vchiq_send_remote_use(VCHIQ_STATE_T *state); + + extern VCHIQ_STATUS_T +-vchiq_send_remote_release(VCHIQ_STATE_T * state); ++vchiq_send_remote_release(VCHIQ_STATE_T *state); + + extern VCHIQ_STATUS_T +-vchiq_send_remote_use_active(VCHIQ_STATE_T * state); ++vchiq_send_remote_use_active(VCHIQ_STATE_T *state); ++ ++extern void ++vchiq_platform_conn_state_changed(VCHIQ_STATE_T *state, ++ VCHIQ_CONNSTATE_T oldstate, VCHIQ_CONNSTATE_T newstate); + + extern void +-vchiq_platform_conn_state_changed(VCHIQ_STATE_T* state, VCHIQ_CONNSTATE_T oldstate, VCHIQ_CONNSTATE_T newstate); ++vchiq_log_dump_mem(const char *label, uint32_t addr, const void *voidMem, ++ size_t numBytes); + + #endif +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_if.h +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_if.h 2013-07-26 19:32:28.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_if.h 2013-07-26 19:36:51.000000000 +0000 +@@ -21,135 +21,145 @@ + + #include "interface/vchi/vchi_mh.h" + +-#define VCHIQ_SLOT_SIZE 4096 +-#define VCHIQ_MAX_MSG_SIZE (VCHIQ_SLOT_SIZE - sizeof(VCHIQ_HEADER_T)) +-#define VCHIQ_CHANNEL_SIZE VCHIQ_MAX_MSG_SIZE /* For backwards compatibility */ +- +-#define VCHIQ_MAKE_FOURCC(x0, x1, x2, x3) (((x0) << 24) | ((x1) << 16) | ((x2) << 8) | (x3)) +-#define VCHIQ_GET_SERVICE_USERDATA(service) (service->userdata) +-#define VCHIQ_GET_SERVICE_FOURCC(service) (service->fourcc) ++#define VCHIQ_SERVICE_HANDLE_INVALID 0 ++ ++#define VCHIQ_SLOT_SIZE 4096 ++#define VCHIQ_MAX_MSG_SIZE (VCHIQ_SLOT_SIZE - sizeof(VCHIQ_HEADER_T)) ++#define VCHIQ_CHANNEL_SIZE VCHIQ_MAX_MSG_SIZE /* For backwards compatibility */ ++ ++#define VCHIQ_MAKE_FOURCC(x0, x1, x2, x3) \ ++ (((x0) << 24) | ((x1) << 16) | ((x2) << 8) | (x3)) ++#define VCHIQ_GET_SERVICE_USERDATA(service) vchiq_get_service_userdata(service) ++#define VCHIQ_GET_SERVICE_FOURCC(service) vchiq_get_service_fourcc(service) + + typedef enum { +- VCHIQ_SERVICE_OPENED, // service, -, - +- VCHIQ_SERVICE_CLOSED, // service, -, - +- VCHIQ_MESSAGE_AVAILABLE, // service, header, - +- VCHIQ_BULK_TRANSMIT_DONE, // service, -, bulk_userdata +- VCHIQ_BULK_RECEIVE_DONE, // service, -, bulk_userdata +- VCHIQ_BULK_TRANSMIT_ABORTED, // service, -, bulk_userdata +- VCHIQ_BULK_RECEIVE_ABORTED // service, -, bulk_userdata ++ VCHIQ_SERVICE_OPENED, /* service, -, - */ ++ VCHIQ_SERVICE_CLOSED, /* service, -, - */ ++ VCHIQ_MESSAGE_AVAILABLE, /* service, header, - */ ++ VCHIQ_BULK_TRANSMIT_DONE, /* service, -, bulk_userdata */ ++ VCHIQ_BULK_RECEIVE_DONE, /* service, -, bulk_userdata */ ++ VCHIQ_BULK_TRANSMIT_ABORTED, /* service, -, bulk_userdata */ ++ VCHIQ_BULK_RECEIVE_ABORTED /* service, -, bulk_userdata */ + } VCHIQ_REASON_T; + +-typedef enum +-{ +- VCHIQ_ERROR = -1, +- VCHIQ_SUCCESS = 0, +- VCHIQ_RETRY = 1 ++typedef enum { ++ VCHIQ_ERROR = -1, ++ VCHIQ_SUCCESS = 0, ++ VCHIQ_RETRY = 1 + } VCHIQ_STATUS_T; + +-typedef enum +-{ +- VCHIQ_BULK_MODE_CALLBACK, +- VCHIQ_BULK_MODE_BLOCKING, +- VCHIQ_BULK_MODE_NOCALLBACK ++typedef enum { ++ VCHIQ_BULK_MODE_CALLBACK, ++ VCHIQ_BULK_MODE_BLOCKING, ++ VCHIQ_BULK_MODE_NOCALLBACK, ++ VCHIQ_BULK_MODE_WAITING /* Reserved for internal use */ + } VCHIQ_BULK_MODE_T; + +-typedef enum +-{ +- VCHIQ_SERVICE_OPTION_AUTOCLOSE, +- VCHIQ_SERVICE_OPTION_SLOT_QUOTA, +- VCHIQ_SERVICE_OPTION_MESSAGE_QUOTA ++typedef enum { ++ VCHIQ_SERVICE_OPTION_AUTOCLOSE, ++ VCHIQ_SERVICE_OPTION_SLOT_QUOTA, ++ VCHIQ_SERVICE_OPTION_MESSAGE_QUOTA, ++ VCHIQ_SERVICE_OPTION_SYNCHRONOUS + } VCHIQ_SERVICE_OPTION_T; + +-#ifdef __HIGHC__ +-/* Allow zero-sized arrays without warnings */ +-#pragma warning (push) +-#pragma warning (disable : 4200) +-#endif +- + typedef struct vchiq_header_struct { +- /* The message identifier - opaque to applications. */ +- int msgid; ++ /* The message identifier - opaque to applications. */ ++ int msgid; + +- /* Size of message data. */ +- unsigned int size; ++ /* Size of message data. */ ++ unsigned int size; + +- char data[0]; /* message */ ++ char data[0]; /* message */ + } VCHIQ_HEADER_T; + +-#ifdef __HIGHC__ +-#pragma warning (pop) +-#endif +- + typedef struct { +- const void *data; +- int size; ++ const void *data; ++ int size; + } VCHIQ_ELEMENT_T; + +-typedef const struct vchiq_service_base_struct *VCHIQ_SERVICE_HANDLE_T; ++typedef unsigned int VCHIQ_SERVICE_HANDLE_T; + +-typedef VCHIQ_STATUS_T (*VCHIQ_CALLBACK_T)(VCHIQ_REASON_T, VCHIQ_HEADER_T *, VCHIQ_SERVICE_HANDLE_T, void *); ++typedef VCHIQ_STATUS_T (*VCHIQ_CALLBACK_T)(VCHIQ_REASON_T, VCHIQ_HEADER_T *, ++ VCHIQ_SERVICE_HANDLE_T, void *); + + typedef struct vchiq_service_base_struct { +- int fourcc; +- VCHIQ_CALLBACK_T callback; +- void *userdata; ++ int fourcc; ++ VCHIQ_CALLBACK_T callback; ++ void *userdata; + } VCHIQ_SERVICE_BASE_T; + + typedef struct vchiq_service_params_struct { +- int fourcc; +- VCHIQ_CALLBACK_T callback; +- void *userdata; +- short version; /* Increment for non-trivial changes */ +- short version_min; /* Update for incompatible changes */ ++ int fourcc; ++ VCHIQ_CALLBACK_T callback; ++ void *userdata; ++ short version; /* Increment for non-trivial changes */ ++ short version_min; /* Update for incompatible changes */ + } VCHIQ_SERVICE_PARAMS_T; + + typedef struct vchiq_config_struct { +- int max_msg_size; +- int bulk_threshold; /* The message size aboce which it is better to use +- a bulk transfer (<= max_msg_size) */ +- int max_outstanding_bulks; +- int max_services; +- short version; /* The version of VCHIQ */ +- short version_min; /* The minimum compatible version of VCHIQ */ ++ int max_msg_size; ++ int bulk_threshold; /* The message size aboce which it is better to use ++ a bulk transfer (<= max_msg_size) */ ++ int max_outstanding_bulks; ++ int max_services; ++ short version; /* The version of VCHIQ */ ++ short version_min; /* The minimum compatible version of VCHIQ */ + } VCHIQ_CONFIG_T; + + typedef struct vchiq_instance_struct *VCHIQ_INSTANCE_T; +-typedef void (*VCHIQ_REMOTE_USE_CALLBACK_T)(void* cb_arg); +- ++typedef void (*VCHIQ_REMOTE_USE_CALLBACK_T)(void *cb_arg); + + extern VCHIQ_STATUS_T vchiq_initialise(VCHIQ_INSTANCE_T *pinstance); + extern VCHIQ_STATUS_T vchiq_shutdown(VCHIQ_INSTANCE_T instance); + extern VCHIQ_STATUS_T vchiq_connect(VCHIQ_INSTANCE_T instance); +-extern VCHIQ_STATUS_T vchiq_add_service(VCHIQ_INSTANCE_T instance, int fourcc, VCHIQ_CALLBACK_T callback, void *userdata, VCHIQ_SERVICE_HANDLE_T *pservice); +-extern VCHIQ_STATUS_T vchiq_open_service(VCHIQ_INSTANCE_T instance, int fourcc, VCHIQ_CALLBACK_T callback, void *userdata, VCHIQ_SERVICE_HANDLE_T *pservice); +-extern VCHIQ_STATUS_T vchiq_add_service_params(VCHIQ_INSTANCE_T instance, +- const VCHIQ_SERVICE_PARAMS_T *params, +- VCHIQ_SERVICE_HANDLE_T *pservice); +-extern VCHIQ_STATUS_T vchiq_open_service_params(VCHIQ_INSTANCE_T instance, +- const VCHIQ_SERVICE_PARAMS_T *params, +- VCHIQ_SERVICE_HANDLE_T *pservice); ++extern VCHIQ_STATUS_T vchiq_add_service(VCHIQ_INSTANCE_T instance, ++ const VCHIQ_SERVICE_PARAMS_T *params, ++ VCHIQ_SERVICE_HANDLE_T *pservice); ++extern VCHIQ_STATUS_T vchiq_open_service(VCHIQ_INSTANCE_T instance, ++ const VCHIQ_SERVICE_PARAMS_T *params, ++ VCHIQ_SERVICE_HANDLE_T *pservice); + extern VCHIQ_STATUS_T vchiq_close_service(VCHIQ_SERVICE_HANDLE_T service); + extern VCHIQ_STATUS_T vchiq_remove_service(VCHIQ_SERVICE_HANDLE_T service); + extern VCHIQ_STATUS_T vchiq_use_service(VCHIQ_SERVICE_HANDLE_T service); + extern VCHIQ_STATUS_T vchiq_release_service(VCHIQ_SERVICE_HANDLE_T service); + +-extern VCHIQ_STATUS_T vchiq_queue_message(VCHIQ_SERVICE_HANDLE_T service, const VCHIQ_ELEMENT_T *elements, int count); +-extern void vchiq_release_message(VCHIQ_SERVICE_HANDLE_T service, VCHIQ_HEADER_T *header); +-extern VCHIQ_STATUS_T vchiq_queue_bulk_transmit(VCHIQ_SERVICE_HANDLE_T service, const void *data, int size, void *userdata); +-extern VCHIQ_STATUS_T vchiq_queue_bulk_receive(VCHIQ_SERVICE_HANDLE_T service, void *data, int size, void *userdata); +-extern VCHIQ_STATUS_T vchiq_queue_bulk_transmit_handle(VCHIQ_SERVICE_HANDLE_T service, VCHI_MEM_HANDLE_T handle, const void *offset, int size, void *userdata); +-extern VCHIQ_STATUS_T vchiq_queue_bulk_receive_handle(VCHIQ_SERVICE_HANDLE_T service, VCHI_MEM_HANDLE_T handle, void *offset, int size, void *userdata); +-extern VCHIQ_STATUS_T vchiq_bulk_transmit(VCHIQ_SERVICE_HANDLE_T service, const void *data, int size, void *userdata, VCHIQ_BULK_MODE_T mode); +-extern VCHIQ_STATUS_T vchiq_bulk_receive(VCHIQ_SERVICE_HANDLE_T service, void *data, int size, void *userdata, VCHIQ_BULK_MODE_T mode); +-extern VCHIQ_STATUS_T vchiq_bulk_transmit_handle(VCHIQ_SERVICE_HANDLE_T service, VCHI_MEM_HANDLE_T handle, const void *offset, int size, void *userdata, VCHIQ_BULK_MODE_T mode); +-extern VCHIQ_STATUS_T vchiq_bulk_receive_handle(VCHIQ_SERVICE_HANDLE_T service, VCHI_MEM_HANDLE_T handle, void *offset, int size, void *userdata, VCHIQ_BULK_MODE_T mode); +-extern int vchiq_get_client_id(VCHIQ_SERVICE_HANDLE_T service); +-extern VCHIQ_STATUS_T vchiq_get_config(VCHIQ_INSTANCE_T instance, int config_size, VCHIQ_CONFIG_T *pconfig); +-extern VCHIQ_STATUS_T vchiq_set_service_option(VCHIQ_SERVICE_HANDLE_T service, VCHIQ_SERVICE_OPTION_T option, int value); ++extern VCHIQ_STATUS_T vchiq_queue_message(VCHIQ_SERVICE_HANDLE_T service, ++ const VCHIQ_ELEMENT_T *elements, int count); ++extern void vchiq_release_message(VCHIQ_SERVICE_HANDLE_T service, ++ VCHIQ_HEADER_T *header); ++extern VCHIQ_STATUS_T vchiq_queue_bulk_transmit(VCHIQ_SERVICE_HANDLE_T service, ++ const void *data, int size, void *userdata); ++extern VCHIQ_STATUS_T vchiq_queue_bulk_receive(VCHIQ_SERVICE_HANDLE_T service, ++ void *data, int size, void *userdata); ++extern VCHIQ_STATUS_T vchiq_queue_bulk_transmit_handle( ++ VCHIQ_SERVICE_HANDLE_T service, VCHI_MEM_HANDLE_T handle, ++ const void *offset, int size, void *userdata); ++extern VCHIQ_STATUS_T vchiq_queue_bulk_receive_handle( ++ VCHIQ_SERVICE_HANDLE_T service, VCHI_MEM_HANDLE_T handle, ++ void *offset, int size, void *userdata); ++extern VCHIQ_STATUS_T vchiq_bulk_transmit(VCHIQ_SERVICE_HANDLE_T service, ++ const void *data, int size, void *userdata, VCHIQ_BULK_MODE_T mode); ++extern VCHIQ_STATUS_T vchiq_bulk_receive(VCHIQ_SERVICE_HANDLE_T service, ++ void *data, int size, void *userdata, VCHIQ_BULK_MODE_T mode); ++extern VCHIQ_STATUS_T vchiq_bulk_transmit_handle(VCHIQ_SERVICE_HANDLE_T service, ++ VCHI_MEM_HANDLE_T handle, const void *offset, int size, void *userdata, ++ VCHIQ_BULK_MODE_T mode); ++extern VCHIQ_STATUS_T vchiq_bulk_receive_handle(VCHIQ_SERVICE_HANDLE_T service, ++ VCHI_MEM_HANDLE_T handle, void *offset, int size, void *userdata, ++ VCHIQ_BULK_MODE_T mode); ++extern int vchiq_get_client_id(VCHIQ_SERVICE_HANDLE_T service); ++extern void *vchiq_get_service_userdata(VCHIQ_SERVICE_HANDLE_T service); ++extern int vchiq_get_service_fourcc(VCHIQ_SERVICE_HANDLE_T service); ++extern VCHIQ_STATUS_T vchiq_get_config(VCHIQ_INSTANCE_T instance, ++ int config_size, VCHIQ_CONFIG_T *pconfig); ++extern VCHIQ_STATUS_T vchiq_set_service_option(VCHIQ_SERVICE_HANDLE_T service, ++ VCHIQ_SERVICE_OPTION_T option, int value); + +-extern VCHIQ_STATUS_T vchiq_remote_use(VCHIQ_INSTANCE_T instance, VCHIQ_REMOTE_USE_CALLBACK_T callback, void* cb_arg); ++extern VCHIQ_STATUS_T vchiq_remote_use(VCHIQ_INSTANCE_T instance, ++ VCHIQ_REMOTE_USE_CALLBACK_T callback, void *cb_arg); + extern VCHIQ_STATUS_T vchiq_remote_release(VCHIQ_INSTANCE_T instance); + +-extern VCHIQ_STATUS_T vchiq_dump_phys_mem( VCHIQ_SERVICE_HANDLE_T service, void *ptr, size_t num_bytes ); ++extern VCHIQ_STATUS_T vchiq_dump_phys_mem(VCHIQ_SERVICE_HANDLE_T service, ++ void *ptr, size_t num_bytes); + + #endif /* VCHIQ_IF_H */ +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_ioctl.h +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_ioctl.h 2013-07-26 19:32:49.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_ioctl.h 2013-07-26 19:36:51.000000000 +0000 +@@ -26,80 +26,89 @@ + #define VCHIQ_INVALID_HANDLE -1 + + typedef struct { +- VCHIQ_SERVICE_PARAMS_T params; +- int is_open; +- int is_vchi; +- int handle; /* OUT */ ++ VCHIQ_SERVICE_PARAMS_T params; ++ int is_open; ++ int is_vchi; ++ int handle; /* OUT */ + } VCHIQ_CREATE_SERVICE_T; + + typedef struct { +- int handle; +- int count; +- const VCHIQ_ELEMENT_T *elements; ++ int handle; ++ int count; ++ const VCHIQ_ELEMENT_T *elements; + } VCHIQ_QUEUE_MESSAGE_T; + + typedef struct { +- int handle; +- void *data; +- int size; +- void *userdata; +- VCHIQ_BULK_MODE_T mode; ++ int handle; ++ void *data; ++ int size; ++ void *userdata; ++ VCHIQ_BULK_MODE_T mode; + } VCHIQ_QUEUE_BULK_TRANSFER_T; + + typedef struct { +- VCHIQ_REASON_T reason; +- VCHIQ_HEADER_T *header; +- void *service_userdata; +- void *bulk_userdata; ++ VCHIQ_REASON_T reason; ++ VCHIQ_HEADER_T *header; ++ void *service_userdata; ++ void *bulk_userdata; + } VCHIQ_COMPLETION_DATA_T; + + typedef struct { +- int count; +- VCHIQ_COMPLETION_DATA_T *buf; +- int msgbufsize; +- int msgbufcount; /* IN/OUT */ +- void **msgbufs; ++ int count; ++ VCHIQ_COMPLETION_DATA_T *buf; ++ int msgbufsize; ++ int msgbufcount; /* IN/OUT */ ++ void **msgbufs; + } VCHIQ_AWAIT_COMPLETION_T; + + typedef struct { +- int handle; +- int blocking; +- int bufsize; +- void *buf; ++ int handle; ++ int blocking; ++ int bufsize; ++ void *buf; + } VCHIQ_DEQUEUE_MESSAGE_T; + + typedef struct { +- int config_size; +- VCHIQ_CONFIG_T *pconfig; ++ int config_size; ++ VCHIQ_CONFIG_T *pconfig; + } VCHIQ_GET_CONFIG_T; + + typedef struct { +- int handle; +- VCHIQ_SERVICE_OPTION_T option; +- int value; ++ int handle; ++ VCHIQ_SERVICE_OPTION_T option; ++ int value; + } VCHIQ_SET_SERVICE_OPTION_T; + + typedef struct { +- void *virt_addr; +- size_t num_bytes; ++ void *virt_addr; ++ size_t num_bytes; + } VCHIQ_DUMP_MEM_T; + + #define VCHIQ_IOC_CONNECT _IO(VCHIQ_IOC_MAGIC, 0) + #define VCHIQ_IOC_SHUTDOWN _IO(VCHIQ_IOC_MAGIC, 1) +-#define VCHIQ_IOC_CREATE_SERVICE _IOWR(VCHIQ_IOC_MAGIC, 2, VCHIQ_CREATE_SERVICE_T) ++#define VCHIQ_IOC_CREATE_SERVICE \ ++ _IOWR(VCHIQ_IOC_MAGIC, 2, VCHIQ_CREATE_SERVICE_T) + #define VCHIQ_IOC_REMOVE_SERVICE _IO(VCHIQ_IOC_MAGIC, 3) +-#define VCHIQ_IOC_QUEUE_MESSAGE _IOW(VCHIQ_IOC_MAGIC, 4, VCHIQ_QUEUE_MESSAGE_T) +-#define VCHIQ_IOC_QUEUE_BULK_TRANSMIT _IOW(VCHIQ_IOC_MAGIC, 5, VCHIQ_QUEUE_BULK_TRANSFER_T) +-#define VCHIQ_IOC_QUEUE_BULK_RECEIVE _IOW(VCHIQ_IOC_MAGIC, 6, VCHIQ_QUEUE_BULK_TRANSFER_T) +-#define VCHIQ_IOC_AWAIT_COMPLETION _IOWR(VCHIQ_IOC_MAGIC, 7, VCHIQ_AWAIT_COMPLETION_T) +-#define VCHIQ_IOC_DEQUEUE_MESSAGE _IOWR(VCHIQ_IOC_MAGIC, 8, VCHIQ_DEQUEUE_MESSAGE_T) ++#define VCHIQ_IOC_QUEUE_MESSAGE \ ++ _IOW(VCHIQ_IOC_MAGIC, 4, VCHIQ_QUEUE_MESSAGE_T) ++#define VCHIQ_IOC_QUEUE_BULK_TRANSMIT \ ++ _IOWR(VCHIQ_IOC_MAGIC, 5, VCHIQ_QUEUE_BULK_TRANSFER_T) ++#define VCHIQ_IOC_QUEUE_BULK_RECEIVE \ ++ _IOWR(VCHIQ_IOC_MAGIC, 6, VCHIQ_QUEUE_BULK_TRANSFER_T) ++#define VCHIQ_IOC_AWAIT_COMPLETION \ ++ _IOWR(VCHIQ_IOC_MAGIC, 7, VCHIQ_AWAIT_COMPLETION_T) ++#define VCHIQ_IOC_DEQUEUE_MESSAGE \ ++ _IOWR(VCHIQ_IOC_MAGIC, 8, VCHIQ_DEQUEUE_MESSAGE_T) + #define VCHIQ_IOC_GET_CLIENT_ID _IO(VCHIQ_IOC_MAGIC, 9) +-#define VCHIQ_IOC_GET_CONFIG _IOWR(VCHIQ_IOC_MAGIC, 10, VCHIQ_GET_CONFIG_T) ++#define VCHIQ_IOC_GET_CONFIG \ ++ _IOWR(VCHIQ_IOC_MAGIC, 10, VCHIQ_GET_CONFIG_T) + #define VCHIQ_IOC_CLOSE_SERVICE _IO(VCHIQ_IOC_MAGIC, 11) + #define VCHIQ_IOC_USE_SERVICE _IO(VCHIQ_IOC_MAGIC, 12) + #define VCHIQ_IOC_RELEASE_SERVICE _IO(VCHIQ_IOC_MAGIC, 13) +-#define VCHIQ_IOC_SET_SERVICE_OPTION _IOW(VCHIQ_IOC_MAGIC, 14, VCHIQ_SET_SERVICE_OPTION_T) +-#define VCHIQ_IOC_DUMP_PHYS_MEM _IOW(VCHIQ_IOC_MAGIC, 15, VCHIQ_DUMP_MEM_T) ++#define VCHIQ_IOC_SET_SERVICE_OPTION \ ++ _IOW(VCHIQ_IOC_MAGIC, 14, VCHIQ_SET_SERVICE_OPTION_T) ++#define VCHIQ_IOC_DUMP_PHYS_MEM \ ++ _IOW(VCHIQ_IOC_MAGIC, 15, VCHIQ_DUMP_MEM_T) + #define VCHIQ_IOC_MAX 15 + + #endif +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_kern_lib.c +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_kern_lib.c 2013-07-26 19:32:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_kern_lib.c 2013-07-26 19:36:51.000000000 +0000 +@@ -16,22 +16,19 @@ + + #include + #include ++#include + + #include "vchiq_core.h" + #include "vchiq_arm.h" +-#include "interface/vcos/vcos_logging.h" + + /* ---- Public Variables ------------------------------------------------- */ + +-extern VCOS_LOG_CAT_T vchiq_core_log_category; +-#define VCOS_LOG_CATEGORY (&vchiq_core_log_category) +- + /* ---- Private Constants and Types -------------------------------------- */ + + struct vchiq_instance_struct { +- VCHIQ_STATE_T *state; ++ VCHIQ_STATE_T *state; + +- int connected; ++ int connected; + }; + + /**************************************************************************** +@@ -40,40 +37,42 @@ + * + ***************************************************************************/ + +-VCHIQ_STATUS_T vchiq_initialise( VCHIQ_INSTANCE_T *instanceOut ) ++VCHIQ_STATUS_T vchiq_initialise(VCHIQ_INSTANCE_T *instanceOut) + { +- VCHIQ_STATUS_T status = VCHIQ_ERROR; +- VCHIQ_STATE_T *state; +- VCHIQ_INSTANCE_T instance = NULL; +- +- vcos_log_trace( "%s called", __func__ ); +- +- state = vchiq_get_state(); +- if (!state) +- { +- printk( KERN_ERR "%s: videocore not initialized\n", __func__ ); +- goto failed; +- } +- +- instance = kzalloc( sizeof(*instance), GFP_KERNEL ); +- if( !instance ) +- { +- printk( KERN_ERR "%s: error allocating vchiq instance\n", __func__ ); +- goto failed; +- } +- +- instance->connected = 0; +- instance->state = state; +- +- *instanceOut = instance; +- +- status = VCHIQ_SUCCESS; ++ VCHIQ_STATUS_T status = VCHIQ_ERROR; ++ VCHIQ_STATE_T *state; ++ VCHIQ_INSTANCE_T instance = NULL; ++ ++ vchiq_log_trace(vchiq_core_log_level, "%s called", __func__); ++ ++ state = vchiq_get_state(); ++ if (!state) { ++ vchiq_log_error(vchiq_core_log_level, ++ "%s: videocore not initialized\n", __func__); ++ goto failed; ++ } ++ ++ instance = kzalloc(sizeof(*instance), GFP_KERNEL); ++ if (!instance) { ++ vchiq_log_error(vchiq_core_log_level, ++ "%s: error allocating vchiq instance\n", __func__); ++ goto failed; ++ } ++ ++ instance->connected = 0; ++ instance->state = state; ++ ++ *instanceOut = instance; ++ ++ status = VCHIQ_SUCCESS; + + failed: +- vcos_log_trace( "%s(%p): returning %d", __func__, instance, status ); ++ vchiq_log_trace(vchiq_core_log_level, ++ "%s(%p): returning %d", __func__, instance, status); + +- return status; ++ return status; + } ++EXPORT_SYMBOL(vchiq_initialise); + + /**************************************************************************** + * +@@ -81,27 +80,31 @@ + * + ***************************************************************************/ + +-VCHIQ_STATUS_T vchiq_shutdown( VCHIQ_INSTANCE_T instance ) ++VCHIQ_STATUS_T vchiq_shutdown(VCHIQ_INSTANCE_T instance) + { +- VCHIQ_STATUS_T status; +- VCHIQ_STATE_T *state = instance->state; ++ VCHIQ_STATUS_T status; ++ VCHIQ_STATE_T *state = instance->state; + +- vcos_log_trace( "%s(%p) called", __func__, instance ); ++ vchiq_log_trace(vchiq_core_log_level, ++ "%s(%p) called", __func__, instance); + +- vcos_mutex_lock(&state->mutex); ++ if (mutex_lock_interruptible(&state->mutex) != 0) ++ return VCHIQ_RETRY; + +- /* Remove all services */ +- status = vchiq_shutdown_internal(state, instance); ++ /* Remove all services */ ++ status = vchiq_shutdown_internal(state, instance); + +- vcos_mutex_unlock(&state->mutex); ++ mutex_unlock(&state->mutex); + +- if (status == VCHIQ_SUCCESS) +- kfree(instance); ++ if (status == VCHIQ_SUCCESS) ++ kfree(instance); + +- vcos_log_trace( "%s(%p): returning %d", __func__, instance, status ); ++ vchiq_log_trace(vchiq_core_log_level, ++ "%s(%p): returning %d", __func__, instance, status); + +- return status; ++ return status; + } ++EXPORT_SYMBOL(vchiq_shutdown); + + /**************************************************************************** + * +@@ -111,7 +114,7 @@ + + int vchiq_is_connected(VCHIQ_INSTANCE_T instance) + { +- return instance->connected; ++ return instance->connected; + } + + /**************************************************************************** +@@ -122,28 +125,32 @@ + + VCHIQ_STATUS_T vchiq_connect(VCHIQ_INSTANCE_T instance) + { +- VCHIQ_STATUS_T status; +- VCHIQ_STATE_T *state = instance->state; ++ VCHIQ_STATUS_T status; ++ VCHIQ_STATE_T *state = instance->state; + +- vcos_log_trace( "%s(%p) called", __func__, instance ); ++ vchiq_log_trace(vchiq_core_log_level, ++ "%s(%p) called", __func__, instance); + +- if (vcos_mutex_lock(&state->mutex) != VCOS_SUCCESS) { +- vcos_log_trace( "%s: call to vcos_mutex_lock failed", __func__ ); +- status = VCHIQ_RETRY; +- goto failed; +- } +- status = vchiq_connect_internal(state, instance); ++ if (mutex_lock_interruptible(&state->mutex) != 0) { ++ vchiq_log_trace(vchiq_core_log_level, ++ "%s: call to mutex_lock failed", __func__); ++ status = VCHIQ_RETRY; ++ goto failed; ++ } ++ status = vchiq_connect_internal(state, instance); + +- if (status == VCHIQ_SUCCESS) +- instance->connected = 1; ++ if (status == VCHIQ_SUCCESS) ++ instance->connected = 1; + +- vcos_mutex_unlock(&state->mutex); ++ mutex_unlock(&state->mutex); + + failed: +- vcos_log_trace( "%s(%p): returning %d", __func__, instance, status ); ++ vchiq_log_trace(vchiq_core_log_level, ++ "%s(%p): returning %d", __func__, instance, status); + +- return status; ++ return status; + } ++EXPORT_SYMBOL(vchiq_connect); + + /**************************************************************************** + * +@@ -152,22 +159,42 @@ + ***************************************************************************/ + + VCHIQ_STATUS_T vchiq_add_service( +- VCHIQ_INSTANCE_T instance, +- int fourcc, +- VCHIQ_CALLBACK_T callback, +- void *userdata, +- VCHIQ_SERVICE_HANDLE_T *pservice) +-{ +- VCHIQ_SERVICE_PARAMS_T params; ++ VCHIQ_INSTANCE_T instance, ++ const VCHIQ_SERVICE_PARAMS_T *params, ++ VCHIQ_SERVICE_HANDLE_T *phandle) ++{ ++ VCHIQ_STATUS_T status; ++ VCHIQ_STATE_T *state = instance->state; ++ VCHIQ_SERVICE_T *service = NULL; ++ int srvstate; ++ ++ vchiq_log_trace(vchiq_core_log_level, ++ "%s(%p) called", __func__, instance); ++ ++ *phandle = VCHIQ_SERVICE_HANDLE_INVALID; ++ ++ srvstate = vchiq_is_connected(instance) ++ ? VCHIQ_SRVSTATE_LISTENING ++ : VCHIQ_SRVSTATE_HIDDEN; ++ ++ service = vchiq_add_service_internal( ++ state, ++ params, ++ srvstate, ++ instance); ++ ++ if (service) { ++ *phandle = service->handle; ++ status = VCHIQ_SUCCESS; ++ } else ++ status = VCHIQ_ERROR; + +- params.fourcc = fourcc; +- params.callback = callback; +- params.userdata = userdata; +- params.version = 0; +- params.version_min = 0; ++ vchiq_log_trace(vchiq_core_log_level, ++ "%s(%p): returning %d", __func__, instance, status); + +- return vchiq_add_service_params(instance, ¶ms, pservice); ++ return status; + } ++EXPORT_SYMBOL(vchiq_add_service); + + /**************************************************************************** + * +@@ -176,122 +203,39 @@ + ***************************************************************************/ + + VCHIQ_STATUS_T vchiq_open_service( +- VCHIQ_INSTANCE_T instance, +- int fourcc, +- VCHIQ_CALLBACK_T callback, +- void *userdata, +- VCHIQ_SERVICE_HANDLE_T *pservice) +-{ +- VCHIQ_SERVICE_PARAMS_T params; +- +- params.fourcc = fourcc; +- params.callback = callback; +- params.userdata = userdata; +- params.version = 0; +- params.version_min = 0; +- +- return vchiq_open_service_params(instance, ¶ms, pservice); +-} +- +-/**************************************************************************** +-* +-* vchiq_add_service_params +-* +-***************************************************************************/ +- +-VCHIQ_STATUS_T vchiq_add_service_params( +- VCHIQ_INSTANCE_T instance, +- const VCHIQ_SERVICE_PARAMS_T *params, +- VCHIQ_SERVICE_HANDLE_T *pservice) +-{ +- VCHIQ_STATUS_T status; +- VCHIQ_STATE_T *state = instance->state; +- VCHIQ_SERVICE_T *service; +- int srvstate; +- +- vcos_log_trace( "%s(%p) called", __func__, instance ); +- +- *pservice = NULL; +- +- srvstate = vchiq_is_connected( instance ) +- ? VCHIQ_SRVSTATE_LISTENING +- : VCHIQ_SRVSTATE_HIDDEN; +- +- vcos_mutex_lock(&state->mutex); +- +- service = vchiq_add_service_internal( +- state, +- params, +- srvstate, +- instance); +- +- vcos_mutex_unlock(&state->mutex); +- +- if ( service ) +- { +- *pservice = &service->base; +- status = VCHIQ_SUCCESS; +- } +- else +- { +- status = VCHIQ_ERROR; +- } +- +- vcos_log_trace( "%s(%p): returning %d", __func__, instance, status ); +- +- return status; +-} +- +-/**************************************************************************** +-* +-* vchiq_open_service_params +-* +-***************************************************************************/ +- +-VCHIQ_STATUS_T vchiq_open_service_params( +- VCHIQ_INSTANCE_T instance, +- const VCHIQ_SERVICE_PARAMS_T *params, +- VCHIQ_SERVICE_HANDLE_T *pservice) +-{ +- VCHIQ_STATUS_T status = VCHIQ_ERROR; +- VCHIQ_STATE_T *state = instance->state; +- VCHIQ_SERVICE_T *service; +- +- vcos_log_trace( "%s(%p) called", __func__, instance ); +- +- *pservice = NULL; +- +- if (!vchiq_is_connected(instance)) +- goto failed; +- +- vcos_mutex_lock(&state->mutex); +- +- service = vchiq_add_service_internal(state, +- params, +- VCHIQ_SRVSTATE_OPENING, +- instance); +- +- vcos_mutex_unlock(&state->mutex); +- +- if ( service ) +- { +- status = vchiq_open_service_internal(service, current->pid); +- if ( status == VCHIQ_SUCCESS ) +- *pservice = &service->base; +- else +- vchiq_remove_service(&service->base); +- } ++ VCHIQ_INSTANCE_T instance, ++ const VCHIQ_SERVICE_PARAMS_T *params, ++ VCHIQ_SERVICE_HANDLE_T *phandle) ++{ ++ VCHIQ_STATUS_T status = VCHIQ_ERROR; ++ VCHIQ_STATE_T *state = instance->state; ++ VCHIQ_SERVICE_T *service = NULL; ++ ++ vchiq_log_trace(vchiq_core_log_level, ++ "%s(%p) called", __func__, instance); ++ ++ *phandle = VCHIQ_SERVICE_HANDLE_INVALID; ++ ++ if (!vchiq_is_connected(instance)) ++ goto failed; ++ ++ service = vchiq_add_service_internal(state, ++ params, ++ VCHIQ_SRVSTATE_OPENING, ++ instance); ++ ++ if (service) { ++ status = vchiq_open_service_internal(service, current->pid); ++ if (status == VCHIQ_SUCCESS) ++ *phandle = service->handle; ++ else ++ vchiq_remove_service(service->handle); ++ } + + failed: +- vcos_log_trace( "%s(%p): returning %d", __func__, instance, status ); ++ vchiq_log_trace(vchiq_core_log_level, ++ "%s(%p): returning %d", __func__, instance, status); + +- return status; ++ return status; + } +- +-EXPORT_SYMBOL(vchiq_initialise); +-EXPORT_SYMBOL(vchiq_shutdown); +-EXPORT_SYMBOL(vchiq_connect); +-EXPORT_SYMBOL(vchiq_add_service); + EXPORT_SYMBOL(vchiq_open_service); +-EXPORT_SYMBOL(vchiq_add_service_params); +-EXPORT_SYMBOL(vchiq_open_service_params); +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_lib.c +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_lib.c 2013-07-26 19:32:28.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,1628 +0,0 @@ +-/* +- * Copyright (c) 2010-2011 Broadcom Corporation. All rights reserved. +- * +- * This program is free software; you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation; either version 2 of the License, or +- * (at your option) any later version. +- * +- * This program is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with this program; if not, write to the Free Software +- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +- */ +- +-#include +-#include +-#include +-#include +- +-#include "vchiq.h" +-#include "vchiq_cfg.h" +-#include "vchiq_ioctl.h" +-#include "interface/vchi/vchi.h" +-#include "interface/vchi/common/endian.h" +-#include "interface/vcos/vcos.h" +- +-#define VCHIQ_MAX_INSTANCE_SERVICES 32 +-#define MSGBUF_SIZE (VCHIQ_MAX_MSG_SIZE + sizeof(VCHIQ_HEADER_T)) +- +-#define RETRY(r,x) do { r = x; } while ((r == -1) && (errno == EINTR)) +- +-#define VCOS_LOG_CATEGORY (&vchiq_lib_log_category) +- +-typedef struct vchiq_service_struct +-{ +- VCHIQ_SERVICE_BASE_T base; +- int handle; +- int fd; +- VCHI_CALLBACK_T vchi_callback; +- void *peek_buf; +- int peek_size; +- int client_id; +-} VCHIQ_SERVICE_T; +- +-typedef struct vchiq_service_struct VCHI_SERVICE_T; +- +-struct vchiq_instance_struct +-{ +- int fd; +- int initialised; +- int connected; +- VCOS_THREAD_T completion_thread; +- VCOS_MUTEX_T mutex; +- int used_services; +- VCHIQ_SERVICE_T services[VCHIQ_MAX_INSTANCE_SERVICES]; +-} vchiq_instance; +- +-typedef struct vchiq_instance_struct VCHI_STATE_T; +- +-/* Local data */ +-static VCOS_LOG_LEVEL_T vchiq_default_lib_log_level = VCOS_LOG_WARN; +-static VCOS_LOG_CAT_T vchiq_lib_log_category; +-static VCOS_MUTEX_T vchiq_lib_mutex; +-static void *free_msgbufs; +- +- +-/* Local utility functions */ +-static VCHIQ_INSTANCE_T +-vchiq_lib_init(void); +- +-static void *completion_thread(void *); +- +-static VCHIQ_STATUS_T +-create_service(VCHIQ_INSTANCE_T instance, +- const VCHIQ_SERVICE_PARAMS_T *params, +- VCHI_CALLBACK_T vchi_callback, +- int is_open, +- VCHIQ_SERVICE_HANDLE_T *pservice); +- +-static int +-fill_peek_buf(VCHI_SERVICE_T *service, +- VCHI_FLAGS_T flags); +- +-static void * +-alloc_msgbuf(void); +- +-static void +-free_msgbuf(void *buf); +- +-static __inline int +-is_valid_instance(VCHIQ_INSTANCE_T instance) +-{ +- return (instance == &vchiq_instance) && (instance->initialised > 0); +-} +- +-static __inline int +-is_valid_service(VCHIQ_SERVICE_T *service) +-{ +- return ((service != NULL) && (service->fd != VCHIQ_INVALID_HANDLE)); +-} +- +-/* +- * VCHIQ API +- */ +- +-VCHIQ_STATUS_T +-vchiq_initialise(VCHIQ_INSTANCE_T *pinstance) +-{ +- VCHIQ_INSTANCE_T instance; +- +- instance = vchiq_lib_init(); +- +- vcos_log_trace( "%s: returning instance handle %p", __func__, instance ); +- +- *pinstance = instance; +- +- return (instance != NULL) ? VCHIQ_SUCCESS : VCHIQ_ERROR; +-} +- +-VCHIQ_STATUS_T +-vchiq_shutdown(VCHIQ_INSTANCE_T instance) +-{ +- vcos_log_trace( "%s called", __func__ ); +- +- if (!is_valid_instance(instance)) +- return VCHIQ_ERROR; +- +- vcos_mutex_lock(&instance->mutex); +- +- if (instance->initialised == 1) +- { +- int i; +- +- instance->initialised = -1; /* Enter limbo */ +- +- /* Remove all services */ +- +- for (i = 0; i < instance->used_services; i++) +- { +- if (instance->services[i].handle != VCHIQ_INVALID_HANDLE) +- { +- vchiq_remove_service(&instance->services[i].base); +- instance->services[i].handle = VCHIQ_INVALID_HANDLE; +- } +- } +- +- if (instance->connected) +- { +- int ret; +- RETRY(ret, ioctl(instance->fd, VCHIQ_IOC_SHUTDOWN, 0)); +- vcos_assert(ret == 0); +- vcos_thread_join(&instance->completion_thread, NULL); +- instance->connected = 0; +- } +- +- close(instance->fd); +- instance->fd = -1; +- } +- else if (instance->initialised > 1) +- { +- instance->initialised--; +- } +- +- vcos_mutex_unlock(&instance->mutex); +- +- vcos_global_lock(); +- +- if (instance->initialised == -1) +- { +- vcos_mutex_delete(&instance->mutex); +- instance->initialised = 0; +- } +- +- vcos_global_unlock(); +- +- vcos_log_trace( "%s returning", __func__ ); +- +- return VCHIQ_SUCCESS; +-} +- +-VCHIQ_STATUS_T +-vchiq_connect(VCHIQ_INSTANCE_T instance) +-{ +- VCHIQ_STATUS_T status = VCHIQ_SUCCESS; +- +- vcos_log_trace( "%s called", __func__ ); +- +- if (!is_valid_instance(instance)) +- return VCHIQ_ERROR; +- +- vcos_mutex_lock(&instance->mutex); +- +- if (!instance->connected) +- { +- int ret = ioctl(instance->fd, VCHIQ_IOC_CONNECT, 0); +- if (ret == 0) +- { +- VCOS_THREAD_ATTR_T attrs; +- instance->connected = 1; +- vcos_thread_attr_init(&attrs); +- vcos_thread_create(&instance->completion_thread, "VCHIQ completion", +- &attrs, completion_thread, instance); +- } +- else +- { +- status = VCHIQ_ERROR; +- } +- } +- +- vcos_mutex_unlock(&instance->mutex); +- +- return status; +-} +- +-VCHIQ_STATUS_T +-vchiq_add_service(VCHIQ_INSTANCE_T instance, +- int fourcc, +- VCHIQ_CALLBACK_T callback, +- void *userdata, +- VCHIQ_SERVICE_HANDLE_T *pservice) +-{ +- VCHIQ_SERVICE_PARAMS_T params; +- +- params.fourcc = fourcc; +- params.callback = callback; +- params.userdata = userdata; +- params.version = 0; +- params.version_min = 0; +- +- return vchiq_add_service_params(instance, ¶ms, pservice); +-} +- +-VCHIQ_STATUS_T +-vchiq_open_service(VCHIQ_INSTANCE_T instance, +- int fourcc, +- VCHIQ_CALLBACK_T callback, +- void *userdata, +- VCHIQ_SERVICE_HANDLE_T *pservice) +-{ +- VCHIQ_SERVICE_PARAMS_T params; +- +- params.fourcc = fourcc; +- params.callback = callback; +- params.userdata = userdata; +- params.version = 0; +- params.version_min = 0; +- +- return vchiq_open_service_params(instance, ¶ms, pservice); +-} +- +-VCHIQ_STATUS_T +-vchiq_add_service_params(VCHIQ_INSTANCE_T instance, +- const VCHIQ_SERVICE_PARAMS_T *params, +- VCHIQ_SERVICE_HANDLE_T *pservice) +-{ +- VCHIQ_STATUS_T status; +- +- vcos_log_trace( "%s called fourcc = 0x%08x (%c%c%c%c)", +- __func__, +- params->fourcc, +- (params->fourcc >> 24) & 0xff, +- (params->fourcc >> 16) & 0xff, +- (params->fourcc >> 8) & 0xff, +- (params->fourcc ) & 0xff ); +- +- if (!params->callback) +- return VCHIQ_ERROR; +- +- if (!is_valid_instance(instance)) +- return VCHIQ_ERROR; +- +- status = create_service(instance, +- params, +- NULL/*vchi_callback*/, +- 0/*!open*/, +- pservice); +- +- vcos_log_trace( "%s returning service handle = 0x%08x", __func__, (uint32_t)*pservice ); +- +- return status; +-} +- +-VCHIQ_STATUS_T +-vchiq_open_service_params(VCHIQ_INSTANCE_T instance, +- const VCHIQ_SERVICE_PARAMS_T *params, +- VCHIQ_SERVICE_HANDLE_T *pservice) +-{ +- VCHIQ_STATUS_T status; +- +- vcos_log_trace( "%s called fourcc = 0x%08x (%c%c%c%c)", +- __func__, +- params->fourcc, +- (params->fourcc >> 24) & 0xff, +- (params->fourcc >> 16) & 0xff, +- (params->fourcc >> 8) & 0xff, +- (params->fourcc ) & 0xff ); +- +- if (!params->callback) +- return VCHIQ_ERROR; +- +- if (!is_valid_instance(instance)) +- return VCHIQ_ERROR; +- +- status = create_service(instance, +- params, +- NULL/*vchi_callback*/, +- 1/*open*/, +- pservice); +- +- vcos_log_trace( "%s returning service handle = 0x%08x", __func__, (uint32_t)*pservice ); +- +- return status; +-} +- +-VCHIQ_STATUS_T +-vchiq_close_service(VCHIQ_SERVICE_HANDLE_T handle) +-{ +- VCHIQ_SERVICE_T *service = (VCHIQ_SERVICE_T *)handle; +- int ret; +- +- vcos_log_trace( "%s called service handle = 0x%08x", __func__, (uint32_t)handle ); +- +- if (!is_valid_service(service)) +- return VCHIQ_ERROR; +- +- RETRY(ret,ioctl(service->fd, VCHIQ_IOC_CLOSE_SERVICE, service->handle)); +- +- if (ret != 0) +- return VCHIQ_ERROR; +- +- service->handle = VCHIQ_INVALID_HANDLE; +- return VCHIQ_SUCCESS; +-} +- +-VCHIQ_STATUS_T +-vchiq_remove_service(VCHIQ_SERVICE_HANDLE_T handle) +-{ +- VCHIQ_SERVICE_T *service = (VCHIQ_SERVICE_T *)handle; +- int ret; +- +- vcos_log_trace( "%s called service handle = 0x%08x", __func__, (uint32_t)handle ); +- +- if (!is_valid_service(service)) +- return VCHIQ_ERROR; +- +- RETRY(ret,ioctl(service->fd, VCHIQ_IOC_REMOVE_SERVICE, service->handle)); +- +- if (ret != 0) +- return VCHIQ_ERROR; +- +- service->handle = VCHIQ_INVALID_HANDLE; +- return VCHIQ_SUCCESS; +-} +- +-VCHIQ_STATUS_T +-vchiq_queue_message(VCHIQ_SERVICE_HANDLE_T handle, +- const VCHIQ_ELEMENT_T *elements, +- int count) +-{ +- VCHIQ_SERVICE_T *service = (VCHIQ_SERVICE_T *)handle; +- VCHIQ_QUEUE_MESSAGE_T args; +- int ret; +- +- vcos_log_trace( "%s called service handle = 0x%08x", __func__, (uint32_t)handle ); +- +- if (!is_valid_service(service)) +- return VCHIQ_ERROR; +- +- args.handle = service->handle; +- args.elements = elements; +- args.count = count; +- RETRY(ret, ioctl(service->fd, VCHIQ_IOC_QUEUE_MESSAGE, &args)); +- +- return (ret >= 0) ? VCHIQ_SUCCESS : VCHIQ_ERROR; +-} +- +-void +-vchiq_release_message(VCHIQ_SERVICE_HANDLE_T handle, +- VCHIQ_HEADER_T *header) +-{ +- vcos_log_trace( "%s handle=%08x, header=%x", __func__, (uint32_t)handle, (uint32_t)header ); +- +- free_msgbuf(header); +-} +- +-VCHIQ_STATUS_T +-vchiq_queue_bulk_transmit(VCHIQ_SERVICE_HANDLE_T handle, +- const void *data, +- int size, +- void *userdata) +-{ +- VCHIQ_SERVICE_T *service = (VCHIQ_SERVICE_T *)handle; +- VCHIQ_QUEUE_BULK_TRANSFER_T args; +- int ret; +- +- vcos_log_trace( "%s called service handle = 0x%08x", __func__, (uint32_t)handle ); +- +- if (!is_valid_service(service)) +- return VCHIQ_ERROR; +- +- args.handle = service->handle; +- args.data = (void *)data; +- args.size = size; +- args.userdata = userdata; +- args.mode = VCHIQ_BULK_MODE_CALLBACK; +- RETRY(ret, ioctl(service->fd, VCHIQ_IOC_QUEUE_BULK_TRANSMIT, &args)); +- +- return (ret >= 0) ? VCHIQ_SUCCESS : VCHIQ_ERROR; +-} +- +-VCHIQ_STATUS_T +-vchiq_queue_bulk_receive(VCHIQ_SERVICE_HANDLE_T handle, +- void *data, +- int size, +- void *userdata) +-{ +- VCHIQ_SERVICE_T *service = (VCHIQ_SERVICE_T *)handle; +- VCHIQ_QUEUE_BULK_TRANSFER_T args; +- int ret; +- +- vcos_log_trace( "%s called service handle = 0x%08x", __func__, (uint32_t)handle ); +- +- if (!is_valid_service(service)) +- return VCHIQ_ERROR; +- +- args.handle = service->handle; +- args.data = data; +- args.size = size; +- args.userdata = userdata; +- args.mode = VCHIQ_BULK_MODE_CALLBACK; +- RETRY(ret, ioctl(service->fd, VCHIQ_IOC_QUEUE_BULK_RECEIVE, &args)); +- +- return (ret >= 0) ? VCHIQ_SUCCESS : VCHIQ_ERROR; +-} +- +-VCHIQ_STATUS_T +-vchiq_queue_bulk_transmit_handle(VCHIQ_SERVICE_HANDLE_T handle, +- VCHI_MEM_HANDLE_T memhandle, +- const void *offset, +- int size, +- void *userdata) +-{ +- vcos_assert(memhandle == VCHI_MEM_HANDLE_INVALID); +- +- vcos_log_trace( "%s called service handle = 0x%08x", __func__, (uint32_t)handle ); +- +- return vchiq_queue_bulk_transmit(handle, offset, size, userdata); +-} +- +-VCHIQ_STATUS_T +-vchiq_queue_bulk_receive_handle(VCHIQ_SERVICE_HANDLE_T handle, +- VCHI_MEM_HANDLE_T memhandle, +- void *offset, +- int size, +- void *userdata) +-{ +- vcos_assert(memhandle == VCHI_MEM_HANDLE_INVALID); +- +- vcos_log_trace( "%s called service handle = 0x%08x", __func__, (uint32_t)handle ); +- +- return vchiq_queue_bulk_receive(handle, offset, size, userdata); +-} +- +-VCHIQ_STATUS_T +-vchiq_bulk_transmit(VCHIQ_SERVICE_HANDLE_T handle, +- const void *data, +- int size, +- void *userdata, +- VCHIQ_BULK_MODE_T mode) +-{ +- VCHIQ_SERVICE_T *service = (VCHIQ_SERVICE_T *)handle; +- VCHIQ_QUEUE_BULK_TRANSFER_T args; +- int ret; +- +- vcos_log_trace( "%s called service handle = 0x%08x", __func__, (uint32_t)handle ); +- +- if (!is_valid_service(service)) +- return VCHIQ_ERROR; +- +- args.handle = service->handle; +- args.data = (void *)data; +- args.size = size; +- args.userdata = userdata; +- args.mode = mode; +- RETRY(ret, ioctl(service->fd, VCHIQ_IOC_QUEUE_BULK_TRANSMIT, &args)); +- +- return (ret >= 0) ? VCHIQ_SUCCESS : VCHIQ_ERROR; +-} +- +-VCHIQ_STATUS_T +-vchiq_bulk_receive(VCHIQ_SERVICE_HANDLE_T handle, +- void *data, +- int size, +- void *userdata, +- VCHIQ_BULK_MODE_T mode) +-{ +- VCHIQ_SERVICE_T *service = (VCHIQ_SERVICE_T *)handle; +- VCHIQ_QUEUE_BULK_TRANSFER_T args; +- int ret; +- +- vcos_log_trace( "%s called service handle = 0x%08x", __func__, (uint32_t)handle ); +- +- if (!is_valid_service(service)) +- return VCHIQ_ERROR; +- +- args.handle = service->handle; +- args.data = data; +- args.size = size; +- args.userdata = userdata; +- args.mode = mode; +- RETRY(ret, ioctl(service->fd, VCHIQ_IOC_QUEUE_BULK_RECEIVE, &args)); +- +- return (ret >= 0) ? VCHIQ_SUCCESS : VCHIQ_ERROR; +-} +- +-VCHIQ_STATUS_T +-vchiq_bulk_transmit_handle(VCHIQ_SERVICE_HANDLE_T handle, +- VCHI_MEM_HANDLE_T memhandle, +- const void *offset, +- int size, +- void *userdata, +- VCHIQ_BULK_MODE_T mode) +-{ +- vcos_assert(memhandle == VCHI_MEM_HANDLE_INVALID); +- +- return vchiq_bulk_transmit(handle, offset, size, userdata, mode); +-} +- +-VCHIQ_STATUS_T +-vchiq_bulk_receive_handle(VCHIQ_SERVICE_HANDLE_T handle, +- VCHI_MEM_HANDLE_T memhandle, +- void *offset, +- int size, +- void *userdata, +- VCHIQ_BULK_MODE_T mode) +-{ +- vcos_assert(memhandle == VCHI_MEM_HANDLE_INVALID); +- +- return vchiq_bulk_receive(handle, offset, size, userdata, mode); +-} +- +-int +-vchiq_get_client_id(VCHIQ_SERVICE_HANDLE_T handle) +-{ +- VCHIQ_SERVICE_T *service = (VCHIQ_SERVICE_T *)handle; +- +- if (!is_valid_service(service)) +- return VCHIQ_ERROR; +- +- return ioctl(service->fd, VCHIQ_IOC_GET_CLIENT_ID, service->handle); +-} +- +-VCHIQ_STATUS_T +-vchiq_get_config(VCHIQ_INSTANCE_T instance, +- int config_size, +- VCHIQ_CONFIG_T *pconfig) +-{ +- VCHIQ_GET_CONFIG_T args; +- int ret; +- +- if (!is_valid_instance(instance)) +- return VCHIQ_ERROR; +- +- args.config_size = config_size; +- args.pconfig = pconfig; +- +- RETRY(ret, ioctl(instance->fd, VCHIQ_IOC_GET_CONFIG, &args)); +- +- return (ret >= 0) ? VCHIQ_SUCCESS : VCHIQ_ERROR; +-} +- +-int32_t +-vchiq_use_service( const VCHIQ_SERVICE_HANDLE_T handle ) +-{ +- VCHIQ_SERVICE_T *service = (VCHIQ_SERVICE_T *)handle; +- int ret; +- +- if (!is_valid_service(service)) +- return VCHIQ_ERROR; +- +- RETRY(ret,ioctl(service->fd, VCHIQ_IOC_USE_SERVICE, service->handle)); +- return ret; +-} +- +-int32_t +-vchiq_release_service( const VCHIQ_SERVICE_HANDLE_T handle ) +-{ +- VCHIQ_SERVICE_T *service = (VCHIQ_SERVICE_T *)handle; +- int ret; +- RETRY(ret,ioctl(service->fd, VCHIQ_IOC_RELEASE_SERVICE, service->handle)); +- return ret; +-} +- +-VCHIQ_STATUS_T +-vchiq_set_service_option(VCHIQ_SERVICE_HANDLE_T handle, +- VCHIQ_SERVICE_OPTION_T option, int value) +-{ +- VCHIQ_SET_SERVICE_OPTION_T args; +- VCHIQ_SERVICE_T *service = (VCHIQ_SERVICE_T *)handle; +- int ret; +- +- if (!is_valid_service(service)) +- return VCHIQ_ERROR; +- +- args.handle = service->handle; +- args.option = option; +- args.value = value; +- +- RETRY(ret, ioctl(service->fd, VCHIQ_IOC_SET_SERVICE_OPTION, &args)); +- +- return (ret >= 0) ? VCHIQ_SUCCESS : VCHIQ_ERROR; +-} +- +-/* +- * VCHI API +- */ +- +-/* ---------------------------------------------------------------------- +- * return pointer to the mphi message driver function table +- * -------------------------------------------------------------------- */ +-const VCHI_MESSAGE_DRIVER_T * +-vchi_mphi_message_driver_func_table( void ) +-{ +- return NULL; +-} +- +-/* ---------------------------------------------------------------------- +- * return a pointer to the 'single' connection driver fops +- * -------------------------------------------------------------------- */ +-const VCHI_CONNECTION_API_T * +-single_get_func_table( void ) +-{ +- return NULL; +-} +- +-VCHI_CONNECTION_T * +-vchi_create_connection( const VCHI_CONNECTION_API_T * function_table, +- const VCHI_MESSAGE_DRIVER_T * low_level ) +-{ +- vcos_unused(function_table); +- vcos_unused(low_level); +- +- return NULL; +-} +- +-/*********************************************************** +- * Name: vchi_msg_peek +- * +- * Arguments: const VCHI_SERVICE_HANDLE_T handle, +- * void **data, +- * uint32_t *msg_size, +- * VCHI_FLAGS_T flags +- * +- * Description: Routine to return a pointer to the current message (to allow in place processing) +- * The message can be removed using vchi_msg_remove when you're finished +- * +- * Returns: int32_t - success == 0 +- * +- ***********************************************************/ +-int32_t +-vchi_msg_peek( VCHI_SERVICE_HANDLE_T handle, +- void **data, +- uint32_t *msg_size, +- VCHI_FLAGS_T flags ) +-{ +- VCHI_SERVICE_T *service = (VCHI_SERVICE_T *)handle; +- int ret; +- +- if (!is_valid_service(service)) +- return VCHIQ_ERROR; +- +- ret = fill_peek_buf(service, flags); +- +- if (ret == 0) +- { +- *data = service->peek_buf; +- *msg_size = service->peek_size; +- } +- +- return ret; +-} +- +-/*********************************************************** +- * Name: vchi_msg_remove +- * +- * Arguments: const VCHI_SERVICE_HANDLE_T handle, +- * +- * Description: Routine to remove a message (after it has been read with vchi_msg_peek) +- * +- * Returns: int32_t - success == 0 +- * +- ***********************************************************/ +-int32_t +-vchi_msg_remove( VCHI_SERVICE_HANDLE_T handle ) +-{ +- VCHI_SERVICE_T *service = (VCHI_SERVICE_T *)handle; +- +- if (!is_valid_service(service)) +- return VCHIQ_ERROR; +- +- /* Why would you call vchi_msg_remove without calling vchi_msg_peek first? */ +- vcos_assert(service->peek_size >= 0); +- +- /* Invalidate the content but reuse the buffer */ +- service->peek_size = -1; +- +- return 0; +-} +- +-/*********************************************************** +- * Name: vchi_msg_queue +- * +- * Arguments: VCHI_SERVICE_HANDLE_T handle, +- * const void *data, +- * uint32_t data_size, +- * VCHI_FLAGS_T flags, +- * void *msg_handle, +- * +- * Description: Thin wrapper to queue a message onto a connection +- * +- * Returns: int32_t - success == 0 +- * +- ***********************************************************/ +-int32_t +-vchi_msg_queue( VCHI_SERVICE_HANDLE_T handle, +- const void * data, +- uint32_t data_size, +- VCHI_FLAGS_T flags, +- void * msg_handle ) +-{ +- VCHI_SERVICE_T *service = (VCHI_SERVICE_T *)handle; +- VCHIQ_QUEUE_MESSAGE_T args; +- VCHIQ_ELEMENT_T element = {data, data_size}; +- int ret; +- +- vcos_unused(msg_handle); +- vcos_assert(flags == VCHI_FLAGS_BLOCK_UNTIL_QUEUED); +- +- if (!is_valid_service(service)) +- return VCHIQ_ERROR; +- +- args.handle = service->handle; +- args.elements = &element; +- args.count = 1; +- RETRY(ret, ioctl(service->fd, VCHIQ_IOC_QUEUE_MESSAGE, &args)); +- +- return ret; +-} +- +-/*********************************************************** +- * Name: vchi_bulk_queue_receive +- * +- * Arguments: VCHI_BULK_HANDLE_T handle, +- * void *data_dst, +- * const uint32_t data_size, +- * VCHI_FLAGS_T flags +- * void *bulk_handle +- * +- * Description: Routine to setup a rcv buffer +- * +- * Returns: int32_t - success == 0 +- * +- ***********************************************************/ +-int32_t +-vchi_bulk_queue_receive( VCHI_SERVICE_HANDLE_T handle, +- void * data_dst, +- uint32_t data_size, +- VCHI_FLAGS_T flags, +- void * bulk_handle ) +-{ +- VCHI_SERVICE_T *service = (VCHI_SERVICE_T *)handle; +- VCHIQ_QUEUE_BULK_TRANSFER_T args; +- int ret; +- +- if (!is_valid_service(service)) +- return VCHIQ_ERROR; +- +- switch ((int)flags) { +- case VCHI_FLAGS_CALLBACK_WHEN_OP_COMPLETE | VCHI_FLAGS_BLOCK_UNTIL_QUEUED: +- args.mode = VCHIQ_BULK_MODE_CALLBACK; +- break; +- case VCHI_FLAGS_BLOCK_UNTIL_OP_COMPLETE: +- args.mode = VCHIQ_BULK_MODE_BLOCKING; +- break; +- case VCHI_FLAGS_BLOCK_UNTIL_QUEUED: +- case VCHI_FLAGS_NONE: +- args.mode = VCHIQ_BULK_MODE_NOCALLBACK; +- break; +- default: +- vcos_assert(0); +- break; +- } +- +- args.handle = service->handle; +- args.data = data_dst; +- args.size = data_size; +- args.userdata = bulk_handle; +- RETRY(ret, ioctl(service->fd, VCHIQ_IOC_QUEUE_BULK_RECEIVE, &args)); +- +- return ret; +-} +- +-/*********************************************************** +- * Name: vchi_bulk_queue_transmit +- * +- * Arguments: VCHI_BULK_HANDLE_T handle, +- * const void *data_src, +- * uint32_t data_size, +- * VCHI_FLAGS_T flags, +- * void *bulk_handle +- * +- * Description: Routine to transmit some data +- * +- * Returns: int32_t - success == 0 +- * +- ***********************************************************/ +-int32_t +-vchi_bulk_queue_transmit( VCHI_SERVICE_HANDLE_T handle, +- const void * data_src, +- uint32_t data_size, +- VCHI_FLAGS_T flags, +- void * bulk_handle ) +-{ +- VCHI_SERVICE_T *service = (VCHI_SERVICE_T *)handle; +- VCHIQ_QUEUE_BULK_TRANSFER_T args; +- int ret; +- +- if (!is_valid_service(service)) +- return VCHIQ_ERROR; +- +- switch ((int)flags) { +- case VCHI_FLAGS_CALLBACK_WHEN_OP_COMPLETE | VCHI_FLAGS_BLOCK_UNTIL_QUEUED: +- args.mode = VCHIQ_BULK_MODE_CALLBACK; +- break; +- case VCHI_FLAGS_BLOCK_UNTIL_DATA_READ: +- case VCHI_FLAGS_BLOCK_UNTIL_OP_COMPLETE: +- args.mode = VCHIQ_BULK_MODE_BLOCKING; +- break; +- case VCHI_FLAGS_BLOCK_UNTIL_QUEUED: +- case VCHI_FLAGS_NONE: +- args.mode = VCHIQ_BULK_MODE_NOCALLBACK; +- break; +- default: +- vcos_assert(0); +- break; +- } +- +- args.handle = service->handle; +- args.data = (void *)data_src; +- args.size = data_size; +- args.userdata = bulk_handle; +- RETRY(ret, ioctl(service->fd, VCHIQ_IOC_QUEUE_BULK_TRANSMIT, &args)); +- +- return ret; +-} +- +-/*********************************************************** +- * Name: vchi_msg_dequeue +- * +- * Arguments: VCHI_SERVICE_HANDLE_T handle, +- * void *data, +- * uint32_t max_data_size_to_read, +- * uint32_t *actual_msg_size +- * VCHI_FLAGS_T flags +- * +- * Description: Routine to dequeue a message into the supplied buffer +- * +- * Returns: int32_t - success == 0 +- * +- ***********************************************************/ +-int32_t +-vchi_msg_dequeue( VCHI_SERVICE_HANDLE_T handle, +- void *data, +- uint32_t max_data_size_to_read, +- uint32_t *actual_msg_size, +- VCHI_FLAGS_T flags ) +-{ +- VCHI_SERVICE_T *service = (VCHI_SERVICE_T *)handle; +- VCHIQ_DEQUEUE_MESSAGE_T args; +- int ret; +- +- vcos_assert(flags == VCHI_FLAGS_NONE || flags == VCHI_FLAGS_BLOCK_UNTIL_OP_COMPLETE); +- +- if (!is_valid_service(service)) +- return VCHIQ_ERROR; +- +- if (service->peek_size >= 0) +- { +- fprintf(stderr, "vchi_msg_dequeue -> using peek buffer\n"); +- if ((uint32_t)service->peek_size <= max_data_size_to_read) +- { +- memcpy(data, service->peek_buf, service->peek_size); +- *actual_msg_size = service->peek_size; +- /* Invalidate the peek data, but retain the buffer */ +- service->peek_size = -1; +- ret = 0; +- } +- else +- { +- ret = -1; +- } +- } +- else +- { +- args.handle = service->handle; +- args.blocking = (flags == VCHI_FLAGS_BLOCK_UNTIL_OP_COMPLETE); +- args.bufsize = max_data_size_to_read; +- args.buf = data; +- RETRY(ret, ioctl(service->fd, VCHIQ_IOC_DEQUEUE_MESSAGE, &args)); +- if (ret >= 0) +- { +- *actual_msg_size = ret; +- ret = 0; +- } +- } +- +- if ((ret < 0) && (errno != EWOULDBLOCK)) +- fprintf(stderr, "vchi_msg_dequeue -> %d(%d)\n", ret, errno); +- +- return ret; +-} +- +-/*********************************************************** +- * Name: vchi_msg_queuev +- * +- * Arguments: VCHI_SERVICE_HANDLE_T handle, +- * const void *data, +- * uint32_t data_size, +- * VCHI_FLAGS_T flags, +- * void *msg_handle +- * +- * Description: Thin wrapper to queue a message onto a connection +- * +- * Returns: int32_t - success == 0 +- * +- ***********************************************************/ +- +-vcos_static_assert(sizeof(VCHI_MSG_VECTOR_T) == sizeof(VCHIQ_ELEMENT_T)); +-vcos_static_assert(offsetof(VCHI_MSG_VECTOR_T, vec_base) == offsetof(VCHIQ_ELEMENT_T, data)); +-vcos_static_assert(offsetof(VCHI_MSG_VECTOR_T, vec_len) == offsetof(VCHIQ_ELEMENT_T, size)); +- +-int32_t +-vchi_msg_queuev( VCHI_SERVICE_HANDLE_T handle, +- VCHI_MSG_VECTOR_T * vector, +- uint32_t count, +- VCHI_FLAGS_T flags, +- void *msg_handle ) +-{ +- VCHI_SERVICE_T *service = (VCHI_SERVICE_T *)handle; +- VCHIQ_QUEUE_MESSAGE_T args; +- int ret; +- +- vcos_unused(msg_handle); +- +- vcos_assert(flags == VCHI_FLAGS_BLOCK_UNTIL_QUEUED); +- +- if (!is_valid_service(service)) +- return VCHIQ_ERROR; +- +- args.handle = service->handle; +- args.elements = (const VCHIQ_ELEMENT_T *)vector; +- args.count = count; +- RETRY(ret, ioctl(service->fd, VCHIQ_IOC_QUEUE_MESSAGE, &args)); +- +- return ret; +-} +- +-/*********************************************************** +- * Name: vchi_held_msg_release +- * +- * Arguments: VCHI_HELD_MSG_T *message +- * +- * Description: Routine to release a held message (after it has been read with vchi_msg_hold) +- * +- * Returns: int32_t - success == 0 +- * +- ***********************************************************/ +-int32_t +-vchi_held_msg_release( VCHI_HELD_MSG_T *message ) +-{ +- int ret = -1; +- +- if (message && message->message && !message->service) +- { +- free_msgbuf(message->message); +- ret = 0; +- } +- +- return ret; +-} +- +-/*********************************************************** +- * Name: vchi_msg_hold +- * +- * Arguments: VCHI_SERVICE_HANDLE_T handle, +- * void **data, +- * uint32_t *msg_size, +- * VCHI_FLAGS_T flags, +- * VCHI_HELD_MSG_T *message_handle +- * +- * Description: Routine to return a pointer to the current message (to allow in place processing) +- * The message is dequeued - don't forget to release the message using +- * vchi_held_msg_release when you're finished +- * +- * Returns: int32_t - success == 0 +- * +- ***********************************************************/ +-int32_t +-vchi_msg_hold( VCHI_SERVICE_HANDLE_T handle, +- void **data, +- uint32_t *msg_size, +- VCHI_FLAGS_T flags, +- VCHI_HELD_MSG_T *message_handle ) +-{ +- VCHI_SERVICE_T *service = (VCHI_SERVICE_T *)handle; +- int ret; +- +- if (!is_valid_service(service)) +- return VCHIQ_ERROR; +- +- ret = fill_peek_buf(service, flags); +- +- if (ret == 0) +- { +- *data = service->peek_buf; +- *msg_size = service->peek_size; +- +- message_handle->message = service->peek_buf; +- message_handle->service = NULL; +- +- service->peek_size = -1; +- service->peek_buf = NULL; +- } +- +- return 0; +-} +- +-/*********************************************************** +- * Name: vchi_initialise +- * +- * Arguments: VCHI_INSTANCE_T *instance_handle +- * VCHI_CONNECTION_T **connections +- * const uint32_t num_connections +- * +- * Description: Initialises the hardware but does not transmit anything +- * When run as a Host App this will be called twice hence the need +- * to malloc the state information +- * +- * Returns: 0 if successful, failure otherwise +- * +- ***********************************************************/ +-int32_t +-vchi_initialise( VCHI_INSTANCE_T *instance_handle ) +-{ +- VCHIQ_INSTANCE_T instance; +- +- instance = vchiq_lib_init(); +- +- vcos_log_trace( "%s: returning instance handle %p", __func__, instance ); +- +- *instance_handle = (VCHI_INSTANCE_T)instance; +- +- return (instance != NULL) ? 0 : -1; +-} +- +-/*********************************************************** +- * Name: vchi_connect +- * +- * Arguments: VCHI_CONNECTION_T **connections +- * const uint32_t num_connections +- * VCHI_INSTANCE_T instance_handle ) +- * +- * Description: Starts the command service on each connection, +- * causing INIT messages to be pinged back and forth +- * +- * Returns: 0 if successful, failure otherwise +- * +- ***********************************************************/ +-int32_t +-vchi_connect( VCHI_CONNECTION_T **connections, +- const uint32_t num_connections, +- VCHI_INSTANCE_T instance_handle ) +-{ +- VCHIQ_STATUS_T status; +- +- vcos_unused(connections); +- vcos_unused(num_connections); +- +- status = vchiq_connect((VCHIQ_INSTANCE_T)instance_handle); +- +- return (status == VCHIQ_SUCCESS) ? 0 : -1; +-} +- +- +-/*********************************************************** +- * Name: vchi_disconnect +- * +- * Arguments: VCHI_INSTANCE_T instance_handle +- * +- * Description: Stops the command service on each connection, +- * causing DE-INIT messages to be pinged back and forth +- * +- * Returns: 0 if successful, failure otherwise +- * +- ***********************************************************/ +-int32_t +-vchi_disconnect( VCHI_INSTANCE_T instance_handle ) +-{ +- VCHIQ_STATUS_T status; +- +- status = vchiq_shutdown((VCHIQ_INSTANCE_T)instance_handle); +- +- return (status == VCHIQ_SUCCESS) ? 0 : -1; +-} +- +- +-/*********************************************************** +- * Name: vchi_service_open +- * Name: vchi_service_create +- * +- * Arguments: VCHI_INSTANCE_T *instance_handle +- * SERVICE_CREATION_T *setup, +- * VCHI_SERVICE_HANDLE_T *handle +- * +- * Description: Routine to open a service +- * +- * Returns: int32_t - success == 0 +- * +- ***********************************************************/ +-int32_t +-vchi_service_open( VCHI_INSTANCE_T instance_handle, +- SERVICE_CREATION_T *setup, +- VCHI_SERVICE_HANDLE_T *handle ) +-{ +- VCHIQ_SERVICE_PARAMS_T params; +- VCHIQ_STATUS_T status; +- +- memset(¶ms, 0, sizeof(params)); +- params.fourcc = setup->service_id; +- params.userdata = setup->callback_param; +- +- status = create_service((VCHIQ_INSTANCE_T)instance_handle, +- ¶ms, +- setup->callback, +- 1/*open*/, +- (VCHIQ_SERVICE_HANDLE_T *)handle); +- +- return (status == VCHIQ_SUCCESS) ? 0 : -1; +-} +- +-int32_t +-vchi_service_create( VCHI_INSTANCE_T instance_handle, +- SERVICE_CREATION_T *setup, VCHI_SERVICE_HANDLE_T *handle ) +-{ +- VCHIQ_SERVICE_PARAMS_T params; +- VCHIQ_STATUS_T status; +- +- memset(¶ms, 0, sizeof(params)); +- params.fourcc = setup->service_id; +- params.userdata = setup->callback_param; +- +- status = create_service((VCHIQ_INSTANCE_T)instance_handle, +- ¶ms, +- setup->callback, +- 0/*!open*/, +- (VCHIQ_SERVICE_HANDLE_T *)handle); +- +- return (status == VCHIQ_SUCCESS) ? 0 : -1; +-} +- +-int32_t +-vchi_service_close( const VCHI_SERVICE_HANDLE_T handle ) +-{ +- VCHI_SERVICE_T *service = (VCHI_SERVICE_T *)handle; +- int ret; +- +- if (!is_valid_service(service)) +- return VCHIQ_ERROR; +- +- RETRY(ret,ioctl(service->fd, VCHIQ_IOC_REMOVE_SERVICE, service->handle)); +- +- if (ret == 0) +- service->handle = VCHIQ_INVALID_HANDLE; +- +- return ret; +-} +- +-int32_t +-vchi_service_destroy( const VCHI_SERVICE_HANDLE_T handle ) +-{ +- VCHI_SERVICE_T *service = (VCHI_SERVICE_T *)handle; +- int ret; +- +- if (!is_valid_service(service)) +- return VCHIQ_ERROR; +- +- RETRY(ret,ioctl(service->fd, VCHIQ_IOC_REMOVE_SERVICE, service->handle)); +- +- if (ret == 0) +- service->handle = VCHIQ_INVALID_HANDLE; +- +- return ret; +-} +- +-/* ---------------------------------------------------------------------- +- * read a uint32_t from buffer. +- * network format is defined to be little endian +- * -------------------------------------------------------------------- */ +-uint32_t +-vchi_readbuf_uint32( const void *_ptr ) +-{ +- const unsigned char *ptr = _ptr; +- return ptr[0] | (ptr[1] << 8) | (ptr[2] << 16) | (ptr[3] << 24); +-} +- +-/* ---------------------------------------------------------------------- +- * write a uint32_t to buffer. +- * network format is defined to be little endian +- * -------------------------------------------------------------------- */ +-void +-vchi_writebuf_uint32( void *_ptr, uint32_t value ) +-{ +- unsigned char *ptr = _ptr; +- ptr[0] = (unsigned char)((value >> 0) & 0xFF); +- ptr[1] = (unsigned char)((value >> 8) & 0xFF); +- ptr[2] = (unsigned char)((value >> 16) & 0xFF); +- ptr[3] = (unsigned char)((value >> 24) & 0xFF); +-} +- +-/* ---------------------------------------------------------------------- +- * read a uint16_t from buffer. +- * network format is defined to be little endian +- * -------------------------------------------------------------------- */ +-uint16_t +-vchi_readbuf_uint16( const void *_ptr ) +-{ +- const unsigned char *ptr = _ptr; +- return ptr[0] | (ptr[1] << 8); +-} +- +-/* ---------------------------------------------------------------------- +- * write a uint16_t into the buffer. +- * network format is defined to be little endian +- * -------------------------------------------------------------------- */ +-void +-vchi_writebuf_uint16( void *_ptr, uint16_t value ) +-{ +- unsigned char *ptr = _ptr; +- ptr[0] = (value >> 0) & 0xFF; +- ptr[1] = (value >> 8) & 0xFF; +-} +- +-/*********************************************************** +- * Name: vchi_service_use +- * +- * Arguments: const VCHI_SERVICE_HANDLE_T handle +- * +- * Description: Routine to increment refcount on a service +- * +- * Returns: void +- * +- ***********************************************************/ +-int32_t +-vchi_service_use( const VCHI_SERVICE_HANDLE_T handle ) +-{ +- VCHI_SERVICE_T *service = (VCHI_SERVICE_T *)handle; +- int ret; +- +- if (!is_valid_service(service)) +- return VCHIQ_ERROR; +- +- RETRY(ret,ioctl(service->fd, VCHIQ_IOC_USE_SERVICE, service->handle)); +- return ret; +-} +- +-/*********************************************************** +- * Name: vchi_service_release +- * +- * Arguments: const VCHI_SERVICE_HANDLE_T handle +- * +- * Description: Routine to decrement refcount on a service +- * +- * Returns: void +- * +- ***********************************************************/ +-int32_t vchi_service_release( const VCHI_SERVICE_HANDLE_T handle ) +-{ +- VCHI_SERVICE_T *service = (VCHI_SERVICE_T *)handle; +- int ret; +- +- if (!is_valid_service(service)) +- return VCHIQ_ERROR; +- +- RETRY(ret,ioctl(service->fd, VCHIQ_IOC_RELEASE_SERVICE, service->handle)); +- return ret; +-} +- +-/*********************************************************** +- * Name: vchiq_dump_phys_mem +- * +- * Arguments: const VCHI_SERVICE_HANDLE_T handle +- * void *buffer +- * size_t num_bytes +- * +- * Description: Dumps the physical memory associated with +- * a buffer. +- * +- * Returns: void +- * +- ***********************************************************/ +-VCHIQ_STATUS_T vchiq_dump_phys_mem( VCHIQ_SERVICE_HANDLE_T handle, +- void *ptr, +- size_t num_bytes ) +-{ +- VCHIQ_SERVICE_T *service = (VCHIQ_SERVICE_T *)handle; +- VCHIQ_DUMP_MEM_T dump_mem; +- int ret; +- +- if (!is_valid_service(service)) +- return VCHIQ_ERROR; +- +- dump_mem.virt_addr = ptr; +- dump_mem.num_bytes = num_bytes; +- +- RETRY(ret,ioctl(service->fd, VCHIQ_IOC_DUMP_PHYS_MEM, &dump_mem)); +- return (ret >= 0) ? VCHIQ_SUCCESS : VCHIQ_ERROR; +-} +- +- +- +-/* +- * Support functions +- */ +- +-static VCHIQ_INSTANCE_T +-vchiq_lib_init(void) +-{ +- static int mutex_initialised = 0; +- static VCOS_MUTEX_T vchiq_lib_mutex; +- VCHIQ_INSTANCE_T instance = &vchiq_instance; +- +- vcos_global_lock(); +- if (!mutex_initialised) +- { +- vcos_mutex_create(&vchiq_lib_mutex, "vchiq-init"); +- +- vcos_log_set_level( &vchiq_lib_log_category, vchiq_default_lib_log_level ); +- vcos_log_register( "vchiq_lib", &vchiq_lib_log_category ); +- +- mutex_initialised = 1; +- } +- vcos_global_unlock(); +- +- vcos_mutex_lock(&vchiq_lib_mutex); +- +- if (instance->initialised == 0) +- { +- instance->fd = open("/dev/vchiq", O_RDWR); +- if (instance->fd >= 0) +- { +- VCHIQ_GET_CONFIG_T args; +- VCHIQ_CONFIG_T config; +- int ret; +- args.config_size = sizeof(config); +- args.pconfig = &config; +- RETRY(ret, ioctl(instance->fd, VCHIQ_IOC_GET_CONFIG, &args)); +- if ((ret == 0) && (config.version >= VCHIQ_VERSION_MIN) && (config.version_min <= VCHIQ_VERSION)) +- { +- instance->used_services = 0; +- vcos_mutex_create(&instance->mutex, "VCHIQ instance"); +- instance->initialised = 1; +- } +- else +- { +- if (ret == 0) +- { +- vcos_log_error("Incompatible VCHIQ library - driver version %d (min %d), library version %d (min %d)", +- config.version, config.version_min, VCHIQ_VERSION, VCHIQ_VERSION_MIN); +- } +- else +- { +- vcos_log_error("Very incompatible VCHIQ library - cannot retrieve driver version"); +- } +- close(instance->fd); +- instance = NULL; +- } +- } +- else +- { +- instance = NULL; +- } +- } +- else if (instance->initialised > 0) +- { +- instance->initialised++; +- } +- +- vcos_mutex_unlock(&vchiq_lib_mutex); +- +- return instance; +-} +- +-static void * +-completion_thread(void *arg) +-{ +- VCHIQ_INSTANCE_T instance = (VCHIQ_INSTANCE_T)arg; +- VCHIQ_AWAIT_COMPLETION_T args; +- VCHIQ_COMPLETION_DATA_T completions[8]; +- void *msgbufs[8]; +- +- static const VCHI_CALLBACK_REASON_T vchiq_reason_to_vchi[] = +- { +- VCHI_CALLBACK_SERVICE_OPENED, // VCHIQ_SERVICE_OPENED +- VCHI_CALLBACK_SERVICE_CLOSED, // VCHIQ_SERVICE_CLOSED +- VCHI_CALLBACK_MSG_AVAILABLE, // VCHIQ_MESSAGE_AVAILABLE +- VCHI_CALLBACK_BULK_SENT, // VCHIQ_BULK_TRANSMIT_DONE +- VCHI_CALLBACK_BULK_RECEIVED, // VCHIQ_BULK_RECEIVE_DONE +- VCHI_CALLBACK_BULK_TRANSMIT_ABORTED, // VCHIQ_BULK_TRANSMIT_ABORTED +- VCHI_CALLBACK_BULK_RECEIVE_ABORTED, // VCHIQ_BULK_RECEIVE_ABORTED +- }; +- +- args.count = vcos_countof(completions); +- args.buf = completions; +- args.msgbufsize = MSGBUF_SIZE; +- args.msgbufcount = 0; +- args.msgbufs = msgbufs; +- +- while (1) +- { +- int ret, i; +- +- while ((unsigned int)args.msgbufcount < vcos_countof(msgbufs)) +- { +- void *msgbuf = alloc_msgbuf(); +- if (msgbuf) +- { +- msgbufs[args.msgbufcount++] = msgbuf; +- } +- else +- { +- fprintf(stderr, "vchiq_lib: failed to allocate a message buffer\n"); +- vcos_demand(args.msgbufcount != 0); +- } +- } +- +- RETRY(ret, ioctl(instance->fd, VCHIQ_IOC_AWAIT_COMPLETION, &args)); +- +- if (ret <= 0) +- break; +- +- for (i = 0; i < ret; i++) +- { +- VCHIQ_COMPLETION_DATA_T *completion = &completions[i]; +- VCHIQ_SERVICE_T *service = (VCHIQ_SERVICE_T *)completion->service_userdata; +- if (service->base.callback) +- { +- vcos_log_trace( "callback(%x, %x, %x, %x)", +- completion->reason, (uint32_t)completion->header, +- (uint32_t)&service->base, (uint32_t)completion->bulk_userdata ); +- service->base.callback(completion->reason, completion->header, +- &service->base, completion->bulk_userdata); +- } +- else if (service->vchi_callback) +- { +- VCHI_CALLBACK_REASON_T vchi_reason = +- vchiq_reason_to_vchi[completion->reason]; +- service->vchi_callback(service->base.userdata, vchi_reason, completion->bulk_userdata); +- } +- } +- } +- return NULL; +-} +- +-static VCHIQ_STATUS_T +-create_service(VCHIQ_INSTANCE_T instance, +- const VCHIQ_SERVICE_PARAMS_T *params, +- VCHI_CALLBACK_T vchi_callback, +- int is_open, +- VCHIQ_SERVICE_HANDLE_T *pservice) +-{ +- VCHIQ_SERVICE_T *service = NULL; +- VCHIQ_STATUS_T status = VCHIQ_SUCCESS; +- int i; +- +- if (!is_valid_instance(instance)) +- return VCHIQ_ERROR; +- +- vcos_mutex_lock(&instance->mutex); +- +- /* Find a free service */ +- if (is_open) +- { +- /* Find a free service */ +- for (i = 0; i < instance->used_services; i++) +- { +- if (instance->services[i].handle == VCHIQ_INVALID_HANDLE) +- { +- service = &instance->services[i]; +- break; +- } +- } +- } +- else +- { +- for (i = (instance->used_services - 1); i >= 0; i--) +- { +- VCHIQ_SERVICE_T *srv = &instance->services[i]; +- if (srv->handle == VCHIQ_INVALID_HANDLE) +- { +- service = srv; +- } +- else if ( +- (srv->base.fourcc == params->fourcc) && +- ((srv->base.callback != params->callback) || +- (srv->vchi_callback != vchi_callback))) +- { +- /* There is another server using this fourcc which doesn't match */ +- service = NULL; +- status = VCHIQ_ERROR; +- break; +- } +- } +- } +- +- if (!service && (status == VCHIQ_SUCCESS) && +- (instance->used_services < VCHIQ_MAX_INSTANCE_SERVICES)) +- service = &instance->services[instance->used_services++]; +- +- if (service) +- { +- VCHIQ_CREATE_SERVICE_T args; +- int ret; +- service->base.fourcc = params->fourcc; +- service->base.callback = params->callback; +- service->vchi_callback = vchi_callback; +- service->base.userdata = params->userdata; +- service->fd = instance->fd; +- service->peek_size = -1; +- service->peek_buf = NULL; +- +- args.params = *params; +- args.params.userdata = service; +- args.is_open = is_open; +- args.is_vchi = (params->callback == NULL); +- args.handle = -1; /* OUT parameter */ +- RETRY(ret, ioctl(instance->fd, VCHIQ_IOC_CREATE_SERVICE, &args)); +- if (ret == 0) +- service->handle = args.handle; +- else +- status = VCHIQ_ERROR; +- } +- +- *pservice = (status == VCHIQ_SUCCESS) ? &service->base : NULL; +- +- vcos_mutex_unlock(&instance->mutex); +- +- return status; +-} +- +-static int +-fill_peek_buf(VCHI_SERVICE_T *service, +- VCHI_FLAGS_T flags) +-{ +- VCHIQ_DEQUEUE_MESSAGE_T args; +- int ret = 0; +- +- vcos_assert(flags == VCHI_FLAGS_NONE || flags == VCHI_FLAGS_BLOCK_UNTIL_OP_COMPLETE); +- +- if (service->peek_size < 0) +- { +- if (!service->peek_buf) +- service->peek_buf = alloc_msgbuf(); +- +- if (service->peek_buf) +- { +- args.handle = service->handle; +- args.blocking = (flags == VCHI_FLAGS_BLOCK_UNTIL_OP_COMPLETE); +- args.bufsize = MSGBUF_SIZE; +- args.buf = service->peek_buf; +- +- RETRY(ret, ioctl(service->fd, VCHIQ_IOC_DEQUEUE_MESSAGE, &args)); +- +- if (ret >= 0) +- { +- service->peek_size = ret; +- ret = 0; +- } +- else +- { +- ret = -1; +- } +- } +- else +- { +- ret = -1; +- } +- } +- +- return ret; +-} +- +- +-static void * +-alloc_msgbuf(void) +-{ +- void *msgbuf; +- vcos_mutex_lock(&vchiq_lib_mutex); +- msgbuf = free_msgbufs; +- if (msgbuf) +- free_msgbufs = *(void **)msgbuf; +- vcos_mutex_unlock(&vchiq_lib_mutex); +- if (!msgbuf) +- msgbuf = malloc(MSGBUF_SIZE); +- return msgbuf; +-} +- +-static void +-free_msgbuf(void *buf) +-{ +- vcos_mutex_lock(&vchiq_lib_mutex); +- *(void **)buf = free_msgbufs; +- free_msgbufs = buf; +- vcos_mutex_unlock(&vchiq_lib_mutex); +-} +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_memdrv.h +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_memdrv.h 2013-07-26 19:32:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_memdrv.h 2013-07-26 19:36:51.000000000 +0000 +@@ -22,24 +22,31 @@ + + /* ---- Constants and Types ---------------------------------------------- */ + +-typedef struct +-{ +- void *armSharedMemVirt; +- dma_addr_t armSharedMemPhys; +- size_t armSharedMemSize; +- +- void *vcSharedMemVirt; +- dma_addr_t vcSharedMemPhys; +- size_t vcSharedMemSize; +- ++typedef struct { ++ void *armSharedMemVirt; ++ dma_addr_t armSharedMemPhys; ++ size_t armSharedMemSize; ++ ++ void *vcSharedMemVirt; ++ dma_addr_t vcSharedMemPhys; ++ size_t vcSharedMemSize; + } VCHIQ_SHARED_MEM_INFO_T; + + /* ---- Variable Externs ------------------------------------------------- */ + + /* ---- Function Prototypes ---------------------------------------------- */ + +-void vchiq_get_shared_mem_info( VCHIQ_SHARED_MEM_INFO_T *info ); ++void vchiq_get_shared_mem_info(VCHIQ_SHARED_MEM_INFO_T *info); + + VCHIQ_STATUS_T vchiq_memdrv_initialise(void); + ++VCHIQ_STATUS_T vchiq_userdrv_create_instance( ++ const VCHIQ_PLATFORM_DATA_T * platform_data); ++ ++VCHIQ_STATUS_T vchiq_userdrv_suspend( ++ const VCHIQ_PLATFORM_DATA_T * platform_data); ++ ++VCHIQ_STATUS_T vchiq_userdrv_resume( ++ const VCHIQ_PLATFORM_DATA_T * platform_data); ++ + #endif +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_shim.c +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_shim.c 2013-07-26 19:32:28.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_shim.c 2013-07-26 19:36:51.000000000 +0000 +@@ -15,6 +15,8 @@ + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ ++#include ++#include + + #include "interface/vchi/vchi.h" + #include "vchiq.h" +@@ -24,56 +26,42 @@ + + #include + +-#if defined(__KERNEL__) +-#include +-#endif +- + #define vchiq_status_to_vchi(status) ((int32_t)status) + + typedef struct { +- VCHIQ_SERVICE_HANDLE_T handle; ++ VCHIQ_SERVICE_HANDLE_T handle; + +- VCHIU_QUEUE_T queue; ++ VCHIU_QUEUE_T queue; + +- VCHI_CALLBACK_T callback; +- void *callback_param; ++ VCHI_CALLBACK_T callback; ++ void *callback_param; + } SHIM_SERVICE_T; + + /* ---------------------------------------------------------------------- + * return pointer to the mphi message driver function table + * -------------------------------------------------------------------- */ +-#ifdef WIN32 + const VCHI_MESSAGE_DRIVER_T * +-mphi_get_func_table( void ) ++vchi_mphi_message_driver_func_table(void) + { +- return NULL; +-} +-#endif +- +-/* ---------------------------------------------------------------------- +- * return pointer to the mphi message driver function table +- * -------------------------------------------------------------------- */ +-const VCHI_MESSAGE_DRIVER_T * +-vchi_mphi_message_driver_func_table( void ) +-{ +- return NULL; ++ return NULL; + } + + /* ---------------------------------------------------------------------- + * return a pointer to the 'single' connection driver fops + * -------------------------------------------------------------------- */ + const VCHI_CONNECTION_API_T * +-single_get_func_table( void ) ++single_get_func_table(void) + { +- return NULL; ++ return NULL; + } + +-VCHI_CONNECTION_T * vchi_create_connection( const VCHI_CONNECTION_API_T * function_table, +- const VCHI_MESSAGE_DRIVER_T * low_level) ++VCHI_CONNECTION_T *vchi_create_connection( ++ const VCHI_CONNECTION_API_T *function_table, ++ const VCHI_MESSAGE_DRIVER_T *low_level) + { +- vcos_unused(function_table); +- vcos_unused(low_level); +- return NULL; ++ (void)function_table; ++ (void)low_level; ++ return NULL; + } + + /*********************************************************** +@@ -82,57 +70,64 @@ + * Arguments: const VCHI_SERVICE_HANDLE_T handle, + * void **data, + * uint32_t *msg_size, ++ ++ + * VCHI_FLAGS_T flags + * +- * Description: Routine to return a pointer to the current message (to allow in place processing) +- * The message can be removed using vchi_msg_remove when you're finished ++ * Description: Routine to return a pointer to the current message (to allow in ++ * place processing). The message can be removed using ++ * vchi_msg_remove when you're finished + * + * Returns: int32_t - success == 0 + * + ***********************************************************/ +-int32_t vchi_msg_peek( VCHI_SERVICE_HANDLE_T handle, +- void **data, +- uint32_t *msg_size, +- VCHI_FLAGS_T flags ) ++int32_t vchi_msg_peek(VCHI_SERVICE_HANDLE_T handle, ++ void **data, ++ uint32_t *msg_size, ++ VCHI_FLAGS_T flags) + { +- SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle; +- VCHIQ_HEADER_T *header; ++ SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle; ++ VCHIQ_HEADER_T *header; + +- vcos_assert(flags == VCHI_FLAGS_NONE || flags == VCHI_FLAGS_BLOCK_UNTIL_OP_COMPLETE); ++ WARN_ON((flags != VCHI_FLAGS_NONE) && ++ (flags != VCHI_FLAGS_BLOCK_UNTIL_OP_COMPLETE)); + +- if (flags == VCHI_FLAGS_NONE) +- if (vchiu_queue_is_empty(&service->queue)) +- return -1; ++ if (flags == VCHI_FLAGS_NONE) ++ if (vchiu_queue_is_empty(&service->queue)) ++ return -1; + +- header = vchiu_queue_peek(&service->queue); ++ header = vchiu_queue_peek(&service->queue); + +- *data = header->data; +- *msg_size = header->size; ++ *data = header->data; ++ *msg_size = header->size; + +- return 0; ++ return 0; + } ++EXPORT_SYMBOL(vchi_msg_peek); + + /*********************************************************** + * Name: vchi_msg_remove + * + * Arguments: const VCHI_SERVICE_HANDLE_T handle, + * +- * Description: Routine to remove a message (after it has been read with vchi_msg_peek) ++ * Description: Routine to remove a message (after it has been read with ++ * vchi_msg_peek) + * + * Returns: int32_t - success == 0 + * + ***********************************************************/ +-int32_t vchi_msg_remove( VCHI_SERVICE_HANDLE_T handle ) ++int32_t vchi_msg_remove(VCHI_SERVICE_HANDLE_T handle) + { +- SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle; +- VCHIQ_HEADER_T *header; ++ SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle; ++ VCHIQ_HEADER_T *header; + +- header = vchiu_queue_pop(&service->queue); ++ header = vchiu_queue_pop(&service->queue); + +- vchiq_release_message(service->handle, header); ++ vchiq_release_message(service->handle, header); + +- return 0; ++ return 0; + } ++EXPORT_SYMBOL(vchi_msg_remove); + + /*********************************************************** + * Name: vchi_msg_queue +@@ -148,33 +143,34 @@ + * Returns: int32_t - success == 0 + * + ***********************************************************/ +-int32_t vchi_msg_queue( VCHI_SERVICE_HANDLE_T handle, +- const void * data, +- uint32_t data_size, +- VCHI_FLAGS_T flags, +- void * msg_handle ) +-{ +- SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle; +- VCHIQ_ELEMENT_T element = {data, data_size}; +- VCHIQ_STATUS_T status; +- +- vcos_unused(msg_handle); +- +- vcos_assert(flags == VCHI_FLAGS_BLOCK_UNTIL_QUEUED); +- +- status = vchiq_queue_message(service->handle, &element, 1); +- +- // On some platforms, like linux kernel, vchiq_queue_message() may return +- // VCHIQ_RETRY, so we need to implment a retry mechanism since this +- // function is supposed to block until queued +- while ( status == VCHIQ_RETRY ) +- { +- vcos_sleep( 1 ); +- status = vchiq_queue_message(service->handle, &element, 1); +- } ++int32_t vchi_msg_queue(VCHI_SERVICE_HANDLE_T handle, ++ const void *data, ++ uint32_t data_size, ++ VCHI_FLAGS_T flags, ++ void *msg_handle) ++{ ++ SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle; ++ VCHIQ_ELEMENT_T element = {data, data_size}; ++ VCHIQ_STATUS_T status; ++ ++ (void)msg_handle; ++ ++ WARN_ON(flags != VCHI_FLAGS_BLOCK_UNTIL_QUEUED); ++ ++ status = vchiq_queue_message(service->handle, &element, 1); ++ ++ /* vchiq_queue_message() may return VCHIQ_RETRY, so we need to ++ ** implement a retry mechanism since this function is supposed ++ ** to block until queued ++ */ ++ while (status == VCHIQ_RETRY) { ++ msleep(1); ++ status = vchiq_queue_message(service->handle, &element, 1); ++ } + +- return vchiq_status_to_vchi(status); ++ return vchiq_status_to_vchi(status); + } ++EXPORT_SYMBOL(vchi_msg_queue); + + /*********************************************************** + * Name: vchi_bulk_queue_receive +@@ -190,107 +186,50 @@ + * Returns: int32_t - success == 0 + * + ***********************************************************/ +-int32_t vchi_bulk_queue_receive( VCHI_SERVICE_HANDLE_T handle, +- void * data_dst, +- uint32_t data_size, +- VCHI_FLAGS_T flags, +- void * bulk_handle ) +-{ +- SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle; +- VCHIQ_BULK_MODE_T mode; +- VCHIQ_STATUS_T status; +- +- switch ((int)flags) { +- case VCHI_FLAGS_CALLBACK_WHEN_OP_COMPLETE | VCHI_FLAGS_BLOCK_UNTIL_QUEUED: +- vcos_assert(service->callback); +- mode = VCHIQ_BULK_MODE_CALLBACK; +- break; +- case VCHI_FLAGS_BLOCK_UNTIL_OP_COMPLETE: +- mode = VCHIQ_BULK_MODE_BLOCKING; +- break; +- case VCHI_FLAGS_BLOCK_UNTIL_QUEUED: +- case VCHI_FLAGS_NONE: +- mode = VCHIQ_BULK_MODE_NOCALLBACK; +- break; +- default: +- vcos_assert(0); +- return vchiq_status_to_vchi(VCHIQ_ERROR); +- } +- +- status = vchiq_bulk_receive(service->handle, data_dst, data_size, +- bulk_handle, mode); +- +- // On some platforms, like linux kernel, vchiq_bulk_receive() may return +- // VCHIQ_RETRY, so we need to implment a retry mechanism since this +- // function is supposed to block until queued +- while ( status == VCHIQ_RETRY ) +- { +- vcos_sleep( 1 ); +- status = vchiq_bulk_receive(service->handle, data_dst, data_size, +- bulk_handle, mode); +- } +- +- return vchiq_status_to_vchi(status); +-} +- +-/*********************************************************** +- * Name: vchi_bulk_queue_receive_reloc +- * +- * Arguments: VCHI_BULK_HANDLE_T handle, +- * VCHI_MEM_HANDLE_T h +- * uint32_t offset +- * const uint32_t data_size, +- * VCHI_FLAGS_T flags +- * void *bulk_handle +- * +- * Description: Routine to setup a relocatable rcv buffer +- * +- * Returns: int32_t - success == 0 +- * +- ***********************************************************/ +-int32_t vchi_bulk_queue_receive_reloc( const VCHI_SERVICE_HANDLE_T handle, +- VCHI_MEM_HANDLE_T h, +- uint32_t offset, +- uint32_t data_size, +- const VCHI_FLAGS_T flags, +- void * const bulk_handle ) +-{ +- SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle; +- VCHIQ_BULK_MODE_T mode; +- VCHIQ_STATUS_T status; +- +- switch ((int)flags) { +- case VCHI_FLAGS_CALLBACK_WHEN_OP_COMPLETE | VCHI_FLAGS_BLOCK_UNTIL_QUEUED: +- vcos_assert(service->callback); +- mode = VCHIQ_BULK_MODE_CALLBACK; +- break; +- case VCHI_FLAGS_BLOCK_UNTIL_OP_COMPLETE: +- mode = VCHIQ_BULK_MODE_BLOCKING; +- break; +- case VCHI_FLAGS_BLOCK_UNTIL_QUEUED: +- case VCHI_FLAGS_NONE: +- mode = VCHIQ_BULK_MODE_NOCALLBACK; +- break; +- default: +- vcos_assert(0); +- return vchiq_status_to_vchi(VCHIQ_ERROR); +- } +- +- status = vchiq_bulk_receive_handle(service->handle, h, (void*)offset, +- data_size, bulk_handle, mode); +- +- // On some platforms, like linux kernel, vchiq_bulk_receive_handle() may +- // return VCHIQ_RETRY, so we need to implment a retry mechanism since +- // this function is supposed to block until queued +- while ( status == VCHIQ_RETRY ) +- { +- vcos_sleep( 1 ); +- status = vchiq_bulk_receive_handle(service->handle, h, (void*)offset, +- data_size, bulk_handle, mode); +- } ++int32_t vchi_bulk_queue_receive(VCHI_SERVICE_HANDLE_T handle, ++ void *data_dst, ++ uint32_t data_size, ++ VCHI_FLAGS_T flags, ++ void *bulk_handle) ++{ ++ SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle; ++ VCHIQ_BULK_MODE_T mode; ++ VCHIQ_STATUS_T status; ++ ++ switch ((int)flags) { ++ case VCHI_FLAGS_CALLBACK_WHEN_OP_COMPLETE ++ | VCHI_FLAGS_BLOCK_UNTIL_QUEUED: ++ WARN_ON(!service->callback); ++ mode = VCHIQ_BULK_MODE_CALLBACK; ++ break; ++ case VCHI_FLAGS_BLOCK_UNTIL_OP_COMPLETE: ++ mode = VCHIQ_BULK_MODE_BLOCKING; ++ break; ++ case VCHI_FLAGS_BLOCK_UNTIL_QUEUED: ++ case VCHI_FLAGS_NONE: ++ mode = VCHIQ_BULK_MODE_NOCALLBACK; ++ break; ++ default: ++ WARN(1, "unsupported message\n"); ++ return vchiq_status_to_vchi(VCHIQ_ERROR); ++ } ++ ++ status = vchiq_bulk_receive(service->handle, data_dst, data_size, ++ bulk_handle, mode); ++ ++ /* vchiq_bulk_receive() may return VCHIQ_RETRY, so we need to ++ ** implement a retry mechanism since this function is supposed ++ ** to block until queued ++ */ ++ while (status == VCHIQ_RETRY) { ++ msleep(1); ++ status = vchiq_bulk_receive(service->handle, data_dst, ++ data_size, bulk_handle, mode); ++ } + +- return vchiq_status_to_vchi(status); ++ return vchiq_status_to_vchi(status); + } ++EXPORT_SYMBOL(vchi_bulk_queue_receive); + + /*********************************************************** + * Name: vchi_bulk_queue_transmit +@@ -306,110 +245,51 @@ + * Returns: int32_t - success == 0 + * + ***********************************************************/ +-int32_t vchi_bulk_queue_transmit( VCHI_SERVICE_HANDLE_T handle, +- const void * data_src, +- uint32_t data_size, +- VCHI_FLAGS_T flags, +- void * bulk_handle ) +-{ +- SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle; +- VCHIQ_BULK_MODE_T mode; +- VCHIQ_STATUS_T status; +- +- switch ((int)flags) { +- case VCHI_FLAGS_CALLBACK_WHEN_OP_COMPLETE | VCHI_FLAGS_BLOCK_UNTIL_QUEUED: +- vcos_assert(service->callback); +- mode = VCHIQ_BULK_MODE_CALLBACK; +- break; +- case VCHI_FLAGS_BLOCK_UNTIL_DATA_READ: +- case VCHI_FLAGS_BLOCK_UNTIL_OP_COMPLETE: +- mode = VCHIQ_BULK_MODE_BLOCKING; +- break; +- case VCHI_FLAGS_BLOCK_UNTIL_QUEUED: +- case VCHI_FLAGS_NONE: +- mode = VCHIQ_BULK_MODE_NOCALLBACK; +- break; +- default: +- vcos_assert(0); +- return vchiq_status_to_vchi(VCHIQ_ERROR); +- } +- +- status = vchiq_bulk_transmit(service->handle, data_src, data_size, +- bulk_handle, mode); +- +- // On some platforms, like linux kernel, vchiq_bulk_transmit() may return +- // VCHIQ_RETRY, so we need to implment a retry mechanism since this +- // function is supposed to block until queued +- while ( status == VCHIQ_RETRY ) +- { +- vcos_sleep( 1 ); +- status = vchiq_bulk_transmit(service->handle, data_src, data_size, +- bulk_handle, mode); +- } ++int32_t vchi_bulk_queue_transmit(VCHI_SERVICE_HANDLE_T handle, ++ const void *data_src, ++ uint32_t data_size, ++ VCHI_FLAGS_T flags, ++ void *bulk_handle) ++{ ++ SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle; ++ VCHIQ_BULK_MODE_T mode; ++ VCHIQ_STATUS_T status; ++ ++ switch ((int)flags) { ++ case VCHI_FLAGS_CALLBACK_WHEN_OP_COMPLETE ++ | VCHI_FLAGS_BLOCK_UNTIL_QUEUED: ++ WARN_ON(!service->callback); ++ mode = VCHIQ_BULK_MODE_CALLBACK; ++ break; ++ case VCHI_FLAGS_BLOCK_UNTIL_DATA_READ: ++ case VCHI_FLAGS_BLOCK_UNTIL_OP_COMPLETE: ++ mode = VCHIQ_BULK_MODE_BLOCKING; ++ break; ++ case VCHI_FLAGS_BLOCK_UNTIL_QUEUED: ++ case VCHI_FLAGS_NONE: ++ mode = VCHIQ_BULK_MODE_NOCALLBACK; ++ break; ++ default: ++ WARN(1, "unsupported message\n"); ++ return vchiq_status_to_vchi(VCHIQ_ERROR); ++ } ++ ++ status = vchiq_bulk_transmit(service->handle, data_src, data_size, ++ bulk_handle, mode); ++ ++ /* vchiq_bulk_transmit() may return VCHIQ_RETRY, so we need to ++ ** implement a retry mechanism since this function is supposed ++ ** to block until queued ++ */ ++ while (status == VCHIQ_RETRY) { ++ msleep(1); ++ status = vchiq_bulk_transmit(service->handle, data_src, ++ data_size, bulk_handle, mode); ++ } + +- return vchiq_status_to_vchi(status); +-} +- +-/*********************************************************** +- * Name: vchi_bulk_queue_transmit_reloc +- * +- * Arguments: VCHI_BULK_HANDLE_T handle, +- * VCHI_MEM_HANDLE_T h_src, +- * uint32_t offset, +- * uint32_t data_size, +- * VCHI_FLAGS_T flags, +- * void *bulk_handle +- * +- * Description: Routine to transmit some data from a relocatable buffer +- * +- * Returns: int32_t - success == 0 +- * +- ***********************************************************/ +- +-int32_t vchi_bulk_queue_transmit_reloc( VCHI_SERVICE_HANDLE_T handle, +- VCHI_MEM_HANDLE_T h_src, +- uint32_t offset, +- uint32_t data_size, +- VCHI_FLAGS_T flags, +- void * const bulk_handle ) +-{ +- SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle; +- VCHIQ_BULK_MODE_T mode; +- VCHIQ_STATUS_T status; +- +- switch ((int)flags) { +- case VCHI_FLAGS_CALLBACK_WHEN_OP_COMPLETE | VCHI_FLAGS_BLOCK_UNTIL_QUEUED: +- vcos_assert(service->callback); +- mode = VCHIQ_BULK_MODE_CALLBACK; +- break; +- case VCHI_FLAGS_BLOCK_UNTIL_DATA_READ: +- case VCHI_FLAGS_BLOCK_UNTIL_OP_COMPLETE: +- mode = VCHIQ_BULK_MODE_BLOCKING; +- break; +- case VCHI_FLAGS_BLOCK_UNTIL_QUEUED: +- case VCHI_FLAGS_NONE: +- mode = VCHIQ_BULK_MODE_NOCALLBACK; +- break; +- default: +- vcos_assert(0); +- return vchiq_status_to_vchi(VCHIQ_ERROR); +- } +- +- status = vchiq_bulk_transmit_handle(service->handle, h_src, (void*)offset, +- data_size, bulk_handle, mode); +- +- // On some platforms, like linux kernel, vchiq_bulk_transmit_handle() may +- // return VCHIQ_RETRY, so we need to implment a retry mechanism since this +- // function is supposed to block until queued +- while ( status == VCHIQ_RETRY ) +- { +- vcos_sleep( 1 ); +- status = vchiq_bulk_transmit_handle(service->handle, h_src, (void*)offset, +- data_size, bulk_handle, mode); +- } +- +- return vchiq_status_to_vchi(status); ++ return vchiq_status_to_vchi(status); + } ++EXPORT_SYMBOL(vchi_bulk_queue_transmit); + + /*********************************************************** + * Name: vchi_msg_dequeue +@@ -425,38 +305,41 @@ + * Returns: int32_t - success == 0 + * + ***********************************************************/ +-int32_t vchi_msg_dequeue( VCHI_SERVICE_HANDLE_T handle, +- void *data, +- uint32_t max_data_size_to_read, +- uint32_t *actual_msg_size, +- VCHI_FLAGS_T flags ) ++int32_t vchi_msg_dequeue(VCHI_SERVICE_HANDLE_T handle, ++ void *data, ++ uint32_t max_data_size_to_read, ++ uint32_t *actual_msg_size, ++ VCHI_FLAGS_T flags) + { +- SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle; +- VCHIQ_HEADER_T *header; ++ SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle; ++ VCHIQ_HEADER_T *header; + +- vcos_assert(flags == VCHI_FLAGS_NONE || flags == VCHI_FLAGS_BLOCK_UNTIL_OP_COMPLETE); ++ WARN_ON((flags != VCHI_FLAGS_NONE) && ++ (flags != VCHI_FLAGS_BLOCK_UNTIL_OP_COMPLETE)); + +- if (flags == VCHI_FLAGS_NONE) +- if (vchiu_queue_is_empty(&service->queue)) +- return -1; ++ if (flags == VCHI_FLAGS_NONE) ++ if (vchiu_queue_is_empty(&service->queue)) ++ return -1; + +- header = vchiu_queue_pop(&service->queue); ++ header = vchiu_queue_pop(&service->queue); + +- memcpy(data, header->data, header->size < max_data_size_to_read ? header->size : max_data_size_to_read); ++ memcpy(data, header->data, header->size < max_data_size_to_read ? ++ header->size : max_data_size_to_read); + +- *actual_msg_size = header->size; ++ *actual_msg_size = header->size; + +- vchiq_release_message(service->handle, header); ++ vchiq_release_message(service->handle, header); + +- return 0; ++ return 0; + } ++EXPORT_SYMBOL(vchi_msg_dequeue); + + /*********************************************************** + * Name: vchi_msg_queuev + * + * Arguments: VCHI_SERVICE_HANDLE_T handle, +- * const void *data, +- * uint32_t data_size, ++ * VCHI_MSG_VECTOR_T *vector, ++ * uint32_t count, + * VCHI_FLAGS_T flags, + * void *msg_handle + * +@@ -466,151 +349,46 @@ + * + ***********************************************************/ + +-vcos_static_assert(sizeof(VCHI_MSG_VECTOR_T) == sizeof(VCHIQ_ELEMENT_T)); +-vcos_static_assert(offsetof(VCHI_MSG_VECTOR_T, vec_base) == offsetof(VCHIQ_ELEMENT_T, data)); +-vcos_static_assert(offsetof(VCHI_MSG_VECTOR_T, vec_len) == offsetof(VCHIQ_ELEMENT_T, size)); +- +-int32_t vchi_msg_queuev( VCHI_SERVICE_HANDLE_T handle, +- VCHI_MSG_VECTOR_T * vector, +- uint32_t count, +- VCHI_FLAGS_T flags, +- void *msg_handle ) ++vchiq_static_assert(sizeof(VCHI_MSG_VECTOR_T) == sizeof(VCHIQ_ELEMENT_T)); ++vchiq_static_assert(offsetof(VCHI_MSG_VECTOR_T, vec_base) == ++ offsetof(VCHIQ_ELEMENT_T, data)); ++vchiq_static_assert(offsetof(VCHI_MSG_VECTOR_T, vec_len) == ++ offsetof(VCHIQ_ELEMENT_T, size)); ++ ++int32_t vchi_msg_queuev(VCHI_SERVICE_HANDLE_T handle, ++ VCHI_MSG_VECTOR_T *vector, ++ uint32_t count, ++ VCHI_FLAGS_T flags, ++ void *msg_handle) + { +- SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle; ++ SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle; + +- vcos_unused(msg_handle); ++ (void)msg_handle; + +- vcos_assert(flags == VCHI_FLAGS_BLOCK_UNTIL_QUEUED); ++ WARN_ON(flags != VCHI_FLAGS_BLOCK_UNTIL_QUEUED); + +- return vchiq_status_to_vchi(vchiq_queue_message(service->handle, (const VCHIQ_ELEMENT_T *)vector, count)); ++ return vchiq_status_to_vchi(vchiq_queue_message(service->handle, ++ (const VCHIQ_ELEMENT_T *)vector, count)); + } +- +-#ifdef USE_MEMMGR +- +-/*********************************************************** +- * Name: vchi_msg_queuev_ex +- * +- * Arguments: VCHI_SERVICE_HANDLE_T handle, +- * VCHI_MSG_VECTOR_EX_T *vector +- * uint32_t count +- * VCHI_FLAGS_T flags, +- * void *msg_handle +- * +- * Description: Thin wrapper to queue an array of messages onto a connection +- * Supports resolving MEM_HANDLE's at last possible moment to avoid deadlocks. +- * +- * Currently just a shim, so deadlocks are still possible! +- * +- * Returns: int32_t - success == 0 +- * +- ***********************************************************/ +-int32_t vchi_msg_queuev_ex( const VCHI_SERVICE_HANDLE_T handle, +- VCHI_MSG_VECTOR_EX_T * const vector, +- const uint32_t count, +- const VCHI_FLAGS_T flags, +- void * const msg_handle ) +-{ +- int32_t success = -1; +- // For now, we don't actually support sending anything other than +- // a pointer, so handles have to be patched up; this is likely +- // to cause deadlocks. This code is not designed to be either +- // pretty, efficient, or deadlock-free. +- +- #define max_vecs 16 +- VCHI_MSG_VECTOR_T copy[max_vecs]; +- const uint8_t *orig[max_vecs]; +- +- int i; +- vcos_unused(msg_handle); +- +- if (count > sizeof(copy)/sizeof(copy[0])) +- { +- vcos_assert(0); +- return -1; +- } +- +- for (i=0; iu.ptr.vec_base; +- copy[i].vec_len = v->u.ptr.vec_len; +- break; +- case VCHI_VEC_HANDLE: +- vcos_assert(v->u.handle.offset+v->u.handle.vec_len <= mem_get_size(v->u.handle.handle)); +- copy[i].vec_base = (uint8_t*)mem_lock(v->u.handle.handle) + v->u.handle.offset; +- orig[i] = copy[i].vec_base; +- copy[i].vec_len = v->u.handle.vec_len; +- break; +- case VCHI_VEC_LIST: +- vcos_assert(0); // FIXME: implement this +- break; +- default: +- vcos_assert(0); +- } +- } +- success = vchi_msg_queuev( handle, +- copy, +- count, +- flags &~ VCHI_FLAGS_INTERNAL, +- msg_handle ); +- if (vcos_verify(success == 0)) +- { +- // now we need to patch up the vectors if any have been only partially consumed, and +- // unlock memory handles. +- +- for (i=0; iu.ptr.vec_base = copy[i].vec_base; +- v->u.ptr.vec_len = copy[i].vec_len; +- } +- break; +- case VCHI_VEC_HANDLE: +- mem_unlock(v->u.handle.handle); +- if (flags & VCHI_FLAGS_ALLOW_PARTIAL) +- { +- const uint8_t *old = orig[i]; +- uint32_t change = (const uint8_t*)copy[i].vec_base-old; +- v->u.handle.offset += change; +- v->u.handle.vec_len -= change; +- } +- break; +- default: +- vcos_assert(0); +- } +- } +- } +- +- return vchiq_status_to_vchi(success); +-} +- +-#endif ++EXPORT_SYMBOL(vchi_msg_queuev); + + /*********************************************************** + * Name: vchi_held_msg_release + * + * Arguments: VCHI_HELD_MSG_T *message + * +- * Description: Routine to release a held message (after it has been read with vchi_msg_hold) ++ * Description: Routine to release a held message (after it has been read with ++ * vchi_msg_hold) + * + * Returns: int32_t - success == 0 + * + ***********************************************************/ +-int32_t vchi_held_msg_release( VCHI_HELD_MSG_T *message ) ++int32_t vchi_held_msg_release(VCHI_HELD_MSG_T *message) + { +- vchiq_release_message((VCHIQ_SERVICE_HANDLE_T)message->service, (VCHIQ_HEADER_T *)message->message); ++ vchiq_release_message((VCHIQ_SERVICE_HANDLE_T)message->service, ++ (VCHIQ_HEADER_T *)message->message); + +- return 0; ++ return 0; + } + + /*********************************************************** +@@ -622,37 +400,40 @@ + * VCHI_FLAGS_T flags, + * VCHI_HELD_MSG_T *message_handle + * +- * Description: Routine to return a pointer to the current message (to allow in place processing) +- * The message is dequeued - don't forget to release the message using +- * vchi_held_msg_release when you're finished ++ * Description: Routine to return a pointer to the current message (to allow ++ * in place processing). The message is dequeued - don't forget ++ * to release the message using vchi_held_msg_release when you're ++ * finished. + * + * Returns: int32_t - success == 0 + * + ***********************************************************/ +-int32_t vchi_msg_hold( VCHI_SERVICE_HANDLE_T handle, +- void **data, +- uint32_t *msg_size, +- VCHI_FLAGS_T flags, +- VCHI_HELD_MSG_T *message_handle ) ++int32_t vchi_msg_hold(VCHI_SERVICE_HANDLE_T handle, ++ void **data, ++ uint32_t *msg_size, ++ VCHI_FLAGS_T flags, ++ VCHI_HELD_MSG_T *message_handle) + { +- SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle; +- VCHIQ_HEADER_T *header; ++ SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle; ++ VCHIQ_HEADER_T *header; + +- vcos_assert(flags == VCHI_FLAGS_NONE || flags == VCHI_FLAGS_BLOCK_UNTIL_OP_COMPLETE); ++ WARN_ON((flags != VCHI_FLAGS_NONE) && ++ (flags != VCHI_FLAGS_BLOCK_UNTIL_OP_COMPLETE)); + +- if (flags == VCHI_FLAGS_NONE) +- if (vchiu_queue_is_empty(&service->queue)) +- return -1; ++ if (flags == VCHI_FLAGS_NONE) ++ if (vchiu_queue_is_empty(&service->queue)) ++ return -1; + +- header = vchiu_queue_pop(&service->queue); ++ header = vchiu_queue_pop(&service->queue); + +- *data = header->data; +- *msg_size = header->size; ++ *data = header->data; ++ *msg_size = header->size; + +- message_handle->service = (struct opaque_vchi_service_t *)service->handle; +- message_handle->message = header; ++ message_handle->service = ++ (struct opaque_vchi_service_t *)service->handle; ++ message_handle->message = header; + +- return 0; ++ return 0; + } + + /*********************************************************** +@@ -670,24 +451,25 @@ + * + ***********************************************************/ + +-int32_t vchi_initialise( VCHI_INSTANCE_T *instance_handle ) ++int32_t vchi_initialise(VCHI_INSTANCE_T *instance_handle) + { +- VCHIQ_INSTANCE_T instance; +- VCHIQ_STATUS_T status; ++ VCHIQ_INSTANCE_T instance; ++ VCHIQ_STATUS_T status; + +- status = vchiq_initialise(&instance); ++ status = vchiq_initialise(&instance); + +- *instance_handle = (VCHI_INSTANCE_T)instance; ++ *instance_handle = (VCHI_INSTANCE_T)instance; + +- return vchiq_status_to_vchi(status); ++ return vchiq_status_to_vchi(status); + } ++EXPORT_SYMBOL(vchi_initialise); + + /*********************************************************** + * Name: vchi_connect + * + * Arguments: VCHI_CONNECTION_T **connections + * const uint32_t num_connections +- * VCHI_INSTANCE_T instance_handle ) ++ * VCHI_INSTANCE_T instance_handle) + * + * Description: Starts the command service on each connection, + * causing INIT messages to be pinged back and forth +@@ -695,17 +477,18 @@ + * Returns: 0 if successful, failure otherwise + * + ***********************************************************/ +-int32_t vchi_connect( VCHI_CONNECTION_T **connections, +- const uint32_t num_connections, +- VCHI_INSTANCE_T instance_handle ) ++int32_t vchi_connect(VCHI_CONNECTION_T **connections, ++ const uint32_t num_connections, ++ VCHI_INSTANCE_T instance_handle) + { +- VCHIQ_INSTANCE_T instance = (VCHIQ_INSTANCE_T)instance_handle; ++ VCHIQ_INSTANCE_T instance = (VCHIQ_INSTANCE_T)instance_handle; + +- vcos_unused(connections); +- vcos_unused(num_connections); ++ (void)connections; ++ (void)num_connections; + +- return vchiq_connect(instance); ++ return vchiq_connect(instance); + } ++EXPORT_SYMBOL(vchi_connect); + + + /*********************************************************** +@@ -719,11 +502,12 @@ + * Returns: 0 if successful, failure otherwise + * + ***********************************************************/ +-int32_t vchi_disconnect( VCHI_INSTANCE_T instance_handle ) ++int32_t vchi_disconnect(VCHI_INSTANCE_T instance_handle) + { +- VCHIQ_INSTANCE_T instance = (VCHIQ_INSTANCE_T)instance_handle; +- return vchiq_status_to_vchi(vchiq_shutdown(instance)); ++ VCHIQ_INSTANCE_T instance = (VCHIQ_INSTANCE_T)instance_handle; ++ return vchiq_status_to_vchi(vchiq_shutdown(instance)); + } ++EXPORT_SYMBOL(vchi_disconnect); + + + /*********************************************************** +@@ -740,168 +524,188 @@ + * + ***********************************************************/ + +-static VCHIQ_STATUS_T shim_callback(VCHIQ_REASON_T reason, VCHIQ_HEADER_T *header, VCHIQ_SERVICE_HANDLE_T handle, void *bulk_user) ++static VCHIQ_STATUS_T shim_callback(VCHIQ_REASON_T reason, ++ VCHIQ_HEADER_T *header, VCHIQ_SERVICE_HANDLE_T handle, void *bulk_user) + { +- SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)VCHIQ_GET_SERVICE_USERDATA(handle); ++ SHIM_SERVICE_T *service = ++ (SHIM_SERVICE_T *)VCHIQ_GET_SERVICE_USERDATA(handle); + +- switch (reason) { +- case VCHIQ_MESSAGE_AVAILABLE: +- vchiu_queue_push(&service->queue, header); +- +- if (service->callback) +- service->callback(service->callback_param, VCHI_CALLBACK_MSG_AVAILABLE, NULL); +- break; +- case VCHIQ_BULK_TRANSMIT_DONE: +- if (service->callback) +- service->callback(service->callback_param, VCHI_CALLBACK_BULK_SENT, bulk_user); +- break; +- case VCHIQ_BULK_RECEIVE_DONE: +- if (service->callback) +- service->callback(service->callback_param, VCHI_CALLBACK_BULK_RECEIVED, bulk_user); +- break; +- case VCHIQ_SERVICE_CLOSED: +- if (service->callback) +- service->callback(service->callback_param, VCHI_CALLBACK_SERVICE_CLOSED, NULL); +- break; +- case VCHIQ_SERVICE_OPENED: +- /* No equivalent VCHI reason */ +- break; +- case VCHIQ_BULK_TRANSMIT_ABORTED: +- if (service->callback) +- service->callback(service->callback_param, VCHI_CALLBACK_BULK_TRANSMIT_ABORTED, bulk_user); +- break; +- case VCHIQ_BULK_RECEIVE_ABORTED: +- if (service->callback) +- service->callback(service->callback_param, VCHI_CALLBACK_BULK_RECEIVE_ABORTED, bulk_user); +- break; +- default: +- vcos_assert(0); +- break; +- } ++ switch (reason) { ++ case VCHIQ_MESSAGE_AVAILABLE: ++ vchiu_queue_push(&service->queue, header); ++ ++ if (service->callback) ++ service->callback(service->callback_param, ++ VCHI_CALLBACK_MSG_AVAILABLE, NULL); ++ break; ++ case VCHIQ_BULK_TRANSMIT_DONE: ++ if (service->callback) ++ service->callback(service->callback_param, ++ VCHI_CALLBACK_BULK_SENT, bulk_user); ++ break; ++ case VCHIQ_BULK_RECEIVE_DONE: ++ if (service->callback) ++ service->callback(service->callback_param, ++ VCHI_CALLBACK_BULK_RECEIVED, bulk_user); ++ break; ++ case VCHIQ_SERVICE_CLOSED: ++ if (service->callback) ++ service->callback(service->callback_param, ++ VCHI_CALLBACK_SERVICE_CLOSED, NULL); ++ break; ++ case VCHIQ_SERVICE_OPENED: ++ /* No equivalent VCHI reason */ ++ break; ++ case VCHIQ_BULK_TRANSMIT_ABORTED: ++ if (service->callback) ++ service->callback(service->callback_param, ++ VCHI_CALLBACK_BULK_TRANSMIT_ABORTED, bulk_user); ++ break; ++ case VCHIQ_BULK_RECEIVE_ABORTED: ++ if (service->callback) ++ service->callback(service->callback_param, ++ VCHI_CALLBACK_BULK_RECEIVE_ABORTED, bulk_user); ++ break; ++ default: ++ WARN(1, "not supported\n"); ++ break; ++ } + +- return VCHIQ_SUCCESS; ++ return VCHIQ_SUCCESS; + } + + static SHIM_SERVICE_T *service_alloc(VCHIQ_INSTANCE_T instance, +- SERVICE_CREATION_T *setup) ++ SERVICE_CREATION_T *setup) + { +- SHIM_SERVICE_T *service = vcos_calloc(1, sizeof(SHIM_SERVICE_T), "vchiq_shim"); ++ SHIM_SERVICE_T *service = kzalloc(sizeof(SHIM_SERVICE_T), GFP_KERNEL); + +- vcos_unused(instance); ++ (void)instance; + +- if (service) +- { +- if (vchiu_queue_init(&service->queue, 64)) +- { +- service->callback = setup->callback; +- service->callback_param = setup->callback_param; +- } +- else +- { +- vcos_free(service); +- service = NULL; +- } +- } ++ if (service) { ++ if (vchiu_queue_init(&service->queue, 64)) { ++ service->callback = setup->callback; ++ service->callback_param = setup->callback_param; ++ } else { ++ kfree(service); ++ service = NULL; ++ } ++ } + +- return service; ++ return service; + } + + static void service_free(SHIM_SERVICE_T *service) + { +- if (service) +- { +- vchiu_queue_delete(&service->queue); +- vcos_free((void*)service); +- } +-} +- +-int32_t vchi_service_open( VCHI_INSTANCE_T instance_handle, +- SERVICE_CREATION_T *setup, +- VCHI_SERVICE_HANDLE_T *handle) +-{ +- VCHIQ_INSTANCE_T instance = (VCHIQ_INSTANCE_T)instance_handle; +- SHIM_SERVICE_T *service = service_alloc(instance, setup); +- if (service) +- { +- VCHIQ_STATUS_T status = vchiq_open_service(instance, setup->service_id, shim_callback, service, &service->handle); +- if (status != VCHIQ_SUCCESS) +- { +- service_free(service); +- service = NULL; +- } +- } +- +- *handle = (VCHI_SERVICE_HANDLE_T)service; +- +- return (service != NULL) ? 0 : -1; +-} +- +-int32_t vchi_service_create( VCHI_INSTANCE_T instance_handle, +- SERVICE_CREATION_T *setup, +- VCHI_SERVICE_HANDLE_T *handle ) +-{ +- VCHIQ_INSTANCE_T instance = (VCHIQ_INSTANCE_T)instance_handle; +- SHIM_SERVICE_T *service = service_alloc(instance, setup); +- if (service) +- { +- VCHIQ_STATUS_T status = vchiq_add_service(instance, setup->service_id, shim_callback, service, &service->handle); +- if (status != VCHIQ_SUCCESS) +- { +- service_free(service); +- service = NULL; +- } +- } +- +- *handle = (VCHI_SERVICE_HANDLE_T)service; +- +- return (service != NULL) ? 0 : -1; +-} +- +-int32_t vchi_service_close( const VCHI_SERVICE_HANDLE_T handle ) +-{ +- int32_t ret = -1; +- SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle; +- if(service) +- { +- VCHIQ_STATUS_T status = vchiq_close_service(service->handle); +- if (status == VCHIQ_SUCCESS) +- { +- service_free(service); +- service = NULL; +- } +- +- ret = vchiq_status_to_vchi( status ); +- } +- return ret; +-} +- +-int32_t vchi_service_destroy( const VCHI_SERVICE_HANDLE_T handle ) +-{ +- int32_t ret = -1; +- SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle; +- if(service) +- { +- VCHIQ_STATUS_T status = vchiq_remove_service(service->handle); +- if (status == VCHIQ_SUCCESS) +- { +- service_free(service); +- service = NULL; +- } +- +- ret = vchiq_status_to_vchi( status ); +- } +- return ret; ++ if (service) { ++ vchiu_queue_delete(&service->queue); ++ kfree(service); ++ } ++} ++ ++int32_t vchi_service_open(VCHI_INSTANCE_T instance_handle, ++ SERVICE_CREATION_T *setup, ++ VCHI_SERVICE_HANDLE_T *handle) ++{ ++ VCHIQ_INSTANCE_T instance = (VCHIQ_INSTANCE_T)instance_handle; ++ SHIM_SERVICE_T *service = service_alloc(instance, setup); ++ if (service) { ++ VCHIQ_SERVICE_PARAMS_T params; ++ VCHIQ_STATUS_T status; ++ ++ memset(¶ms, 0, sizeof(params)); ++ params.fourcc = setup->service_id; ++ params.callback = shim_callback; ++ params.userdata = service; ++ params.version = setup->version.version; ++ params.version_min = setup->version.version_min; ++ ++ status = vchiq_open_service(instance, ¶ms, ++ &service->handle); ++ if (status != VCHIQ_SUCCESS) { ++ service_free(service); ++ service = NULL; ++ } ++ } ++ ++ *handle = (VCHI_SERVICE_HANDLE_T)service; ++ ++ return (service != NULL) ? 0 : -1; + } ++EXPORT_SYMBOL(vchi_service_open); ++ ++int32_t vchi_service_create(VCHI_INSTANCE_T instance_handle, ++ SERVICE_CREATION_T *setup, ++ VCHI_SERVICE_HANDLE_T *handle) ++{ ++ VCHIQ_INSTANCE_T instance = (VCHIQ_INSTANCE_T)instance_handle; ++ SHIM_SERVICE_T *service = service_alloc(instance, setup); ++ if (service) { ++ VCHIQ_SERVICE_PARAMS_T params; ++ VCHIQ_STATUS_T status; ++ ++ memset(¶ms, 0, sizeof(params)); ++ params.fourcc = setup->service_id; ++ params.callback = shim_callback; ++ params.userdata = service; ++ params.version = setup->version.version; ++ params.version_min = setup->version.version_min; ++ status = vchiq_add_service(instance, ¶ms, &service->handle); ++ ++ if (status != VCHIQ_SUCCESS) { ++ service_free(service); ++ service = NULL; ++ } ++ } ++ ++ *handle = (VCHI_SERVICE_HANDLE_T)service; ++ ++ return (service != NULL) ? 0 : -1; ++} ++EXPORT_SYMBOL(vchi_service_create); ++ ++int32_t vchi_service_close(const VCHI_SERVICE_HANDLE_T handle) ++{ ++ int32_t ret = -1; ++ SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle; ++ if (service) { ++ VCHIQ_STATUS_T status = vchiq_close_service(service->handle); ++ if (status == VCHIQ_SUCCESS) { ++ service_free(service); ++ service = NULL; ++ } ++ ++ ret = vchiq_status_to_vchi(status); ++ } ++ return ret; ++} ++EXPORT_SYMBOL(vchi_service_close); ++ ++int32_t vchi_service_destroy(const VCHI_SERVICE_HANDLE_T handle) ++{ ++ int32_t ret = -1; ++ SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle; ++ if (service) { ++ VCHIQ_STATUS_T status = vchiq_remove_service(service->handle); ++ if (status == VCHIQ_SUCCESS) { ++ service_free(service); ++ service = NULL; ++ } ++ ++ ret = vchiq_status_to_vchi(status); ++ } ++ return ret; ++} ++EXPORT_SYMBOL(vchi_service_destroy); + + /* ---------------------------------------------------------------------- + * read a uint32_t from buffer. + * network format is defined to be little endian + * -------------------------------------------------------------------- */ + uint32_t +-vchi_readbuf_uint32( const void *_ptr ) ++vchi_readbuf_uint32(const void *_ptr) + { +- const unsigned char *ptr = _ptr; +- return ptr[0] | (ptr[1] << 8) | (ptr[2] << 16) | (ptr[3] << 24); ++ const unsigned char *ptr = _ptr; ++ return ptr[0] | (ptr[1] << 8) | (ptr[2] << 16) | (ptr[3] << 24); + } + + /* ---------------------------------------------------------------------- +@@ -909,13 +713,13 @@ + * network format is defined to be little endian + * -------------------------------------------------------------------- */ + void +-vchi_writebuf_uint32( void *_ptr, uint32_t value ) ++vchi_writebuf_uint32(void *_ptr, uint32_t value) + { +- unsigned char *ptr = _ptr; +- ptr[0] = (unsigned char)((value >> 0) & 0xFF); +- ptr[1] = (unsigned char)((value >> 8) & 0xFF); +- ptr[2] = (unsigned char)((value >> 16) & 0xFF); +- ptr[3] = (unsigned char)((value >> 24) & 0xFF); ++ unsigned char *ptr = _ptr; ++ ptr[0] = (unsigned char)((value >> 0) & 0xFF); ++ ptr[1] = (unsigned char)((value >> 8) & 0xFF); ++ ptr[2] = (unsigned char)((value >> 16) & 0xFF); ++ ptr[3] = (unsigned char)((value >> 24) & 0xFF); + } + + /* ---------------------------------------------------------------------- +@@ -923,10 +727,10 @@ + * network format is defined to be little endian + * -------------------------------------------------------------------- */ + uint16_t +-vchi_readbuf_uint16( const void *_ptr ) ++vchi_readbuf_uint16(const void *_ptr) + { +- const unsigned char *ptr = _ptr; +- return ptr[0] | (ptr[1] << 8); ++ const unsigned char *ptr = _ptr; ++ return ptr[0] | (ptr[1] << 8); + } + + /* ---------------------------------------------------------------------- +@@ -934,11 +738,11 @@ + * network format is defined to be little endian + * -------------------------------------------------------------------- */ + void +-vchi_writebuf_uint16( void *_ptr, uint16_t value ) ++vchi_writebuf_uint16(void *_ptr, uint16_t value) + { +- unsigned char *ptr = _ptr; +- ptr[0] = (value >> 0) & 0xFF; +- ptr[1] = (value >> 8) & 0xFF; ++ unsigned char *ptr = _ptr; ++ ptr[0] = (value >> 0) & 0xFF; ++ ptr[1] = (value >> 8) & 0xFF; + } + + /*********************************************************** +@@ -951,16 +755,15 @@ + * Returns: void + * + ***********************************************************/ +-int32_t vchi_service_use( const VCHI_SERVICE_HANDLE_T handle ) ++int32_t vchi_service_use(const VCHI_SERVICE_HANDLE_T handle) + { +- int32_t ret = -1; +- SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle; +- if(service) +- { +- ret = vchiq_status_to_vchi(vchiq_use_service(service->handle)); +- } +- return ret; ++ int32_t ret = -1; ++ SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle; ++ if (service) ++ ret = vchiq_status_to_vchi(vchiq_use_service(service->handle)); ++ return ret; + } ++EXPORT_SYMBOL(vchi_service_use); + + /*********************************************************** + * Name: vchi_service_release +@@ -972,30 +775,13 @@ + * Returns: void + * + ***********************************************************/ +-int32_t vchi_service_release( const VCHI_SERVICE_HANDLE_T handle ) ++int32_t vchi_service_release(const VCHI_SERVICE_HANDLE_T handle) + { +- int32_t ret = -1; +- SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle; +- if(service) +- { +- ret = vchiq_status_to_vchi(vchiq_release_service(service->handle)); +- } +- return ret; ++ int32_t ret = -1; ++ SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle; ++ if (service) ++ ret = vchiq_status_to_vchi( ++ vchiq_release_service(service->handle)); ++ return ret; + } +- +-#if defined(__KERNEL__) +-EXPORT_SYMBOL(vchi_initialise); +-EXPORT_SYMBOL(vchi_connect); +-EXPORT_SYMBOL(vchi_bulk_queue_transmit); +-EXPORT_SYMBOL(vchi_msg_dequeue); +-EXPORT_SYMBOL(vchi_msg_queue); +-EXPORT_SYMBOL(vchi_msg_queuev); +-EXPORT_SYMBOL(vchi_msg_peek); +-EXPORT_SYMBOL(vchi_msg_remove); +-EXPORT_SYMBOL(vchi_service_close); +-EXPORT_SYMBOL(vchi_service_open); +-EXPORT_SYMBOL(vchi_service_create); +-EXPORT_SYMBOL(vchi_service_destroy); +-EXPORT_SYMBOL(vchi_service_use); + EXPORT_SYMBOL(vchi_service_release); +-#endif +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_util.c +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_util.c 2013-07-26 19:32:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_util.c 2013-07-26 19:36:51.000000000 +0000 +@@ -18,80 +18,88 @@ + + #include "vchiq_util.h" + +-#if !defined(__KERNEL__) +-#include +-#endif +- +-static __inline int is_pow2(int i) ++static inline int is_pow2(int i) + { +- return i && !(i & (i - 1)); ++ return i && !(i & (i - 1)); + } + + int vchiu_queue_init(VCHIU_QUEUE_T *queue, int size) + { +- vcos_assert(is_pow2(size)); ++ WARN_ON(!is_pow2(size)); + +- queue->size = size; +- queue->read = 0; +- queue->write = 0; +- +- vcos_event_create(&queue->pop, "vchiu"); +- vcos_event_create(&queue->push, "vchiu"); +- +- queue->storage = vcos_malloc(size * sizeof(VCHIQ_HEADER_T *), VCOS_FUNCTION); +- if (queue->storage == NULL) +- { +- vchiu_queue_delete(queue); +- return 0; +- } +- return 1; ++ queue->size = size; ++ queue->read = 0; ++ queue->write = 0; ++ ++ sema_init(&queue->pop, 0); ++ sema_init(&queue->push, 0); ++ ++ queue->storage = kzalloc(size * sizeof(VCHIQ_HEADER_T *), GFP_KERNEL); ++ if (queue->storage == NULL) { ++ vchiu_queue_delete(queue); ++ return 0; ++ } ++ return 1; + } + + void vchiu_queue_delete(VCHIU_QUEUE_T *queue) + { +- vcos_event_delete(&queue->pop); +- vcos_event_delete(&queue->push); +- if (queue->storage != NULL) +- vcos_free(queue->storage); ++ if (queue->storage != NULL) ++ kfree(queue->storage); + } + + int vchiu_queue_is_empty(VCHIU_QUEUE_T *queue) + { +- return queue->read == queue->write; ++ return queue->read == queue->write; ++} ++ ++int vchiu_queue_is_full(VCHIU_QUEUE_T *queue) ++{ ++ return queue->write == queue->read + queue->size; + } + + void vchiu_queue_push(VCHIU_QUEUE_T *queue, VCHIQ_HEADER_T *header) + { +- while (queue->write == queue->read + queue->size) +- vcos_event_wait(&queue->pop); ++ while (queue->write == queue->read + queue->size) { ++ if (down_interruptible(&queue->pop) != 0) { ++ flush_signals(current); ++ } ++ } + +- queue->storage[queue->write & (queue->size - 1)] = header; ++ queue->storage[queue->write & (queue->size - 1)] = header; + +- queue->write++; ++ queue->write++; + +- vcos_event_signal(&queue->push); ++ up(&queue->push); + } + + VCHIQ_HEADER_T *vchiu_queue_peek(VCHIU_QUEUE_T *queue) + { +- while (queue->write == queue->read) +- vcos_event_wait(&queue->push); ++ while (queue->write == queue->read) { ++ if (down_interruptible(&queue->push) != 0) { ++ flush_signals(current); ++ } ++ } + +- return queue->storage[queue->read & (queue->size - 1)]; ++ up(&queue->push); // We haven't removed anything from the queue. ++ return queue->storage[queue->read & (queue->size - 1)]; + } + + VCHIQ_HEADER_T *vchiu_queue_pop(VCHIU_QUEUE_T *queue) + { +- VCHIQ_HEADER_T *header; ++ VCHIQ_HEADER_T *header; + +- while (queue->write == queue->read) +- vcos_event_wait(&queue->push); ++ while (queue->write == queue->read) { ++ if (down_interruptible(&queue->push) != 0) { ++ flush_signals(current); ++ } ++ } + +- header = queue->storage[queue->read & (queue->size - 1)]; ++ header = queue->storage[queue->read & (queue->size - 1)]; + +- queue->read++; ++ queue->read++; + +- vcos_event_signal(&queue->pop); ++ up(&queue->pop); + +- return header; ++ return header; + } +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_util.h +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_util.h 2013-07-26 19:32:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_util.h 2013-07-26 19:36:51.000000000 +0000 +@@ -19,24 +19,44 @@ + #ifndef VCHIQ_UTIL_H + #define VCHIQ_UTIL_H + ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include /* for time_t */ ++#include ++#include ++ + #include "vchiq_if.h" +-#include "interface/vcos/vcos.h" + + typedef struct { +- int size; +- int read; +- int write; ++ int size; ++ int read; ++ int write; + +- VCOS_EVENT_T pop; +- VCOS_EVENT_T push; ++ struct semaphore pop; ++ struct semaphore push; + +- VCHIQ_HEADER_T **storage; ++ VCHIQ_HEADER_T **storage; + } VCHIU_QUEUE_T; + + extern int vchiu_queue_init(VCHIU_QUEUE_T *queue, int size); + extern void vchiu_queue_delete(VCHIU_QUEUE_T *queue); + + extern int vchiu_queue_is_empty(VCHIU_QUEUE_T *queue); ++extern int vchiu_queue_is_full(VCHIU_QUEUE_T *queue); + + extern void vchiu_queue_push(VCHIU_QUEUE_T *queue, VCHIQ_HEADER_T *header); + +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/generic/vcos_cmd.c +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vcos/generic/vcos_cmd.c 2013-07-26 19:32:00.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,681 +0,0 @@ +-/***************************************************************************** +-* Copyright 2009 - 2011 Broadcom Corporation. All rights reserved. +-* +-* Unless you and Broadcom execute a separate written software license +-* agreement governing use of this software, this software is licensed to you +-* under the terms of the GNU General Public License version 2, available at +-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). +-* +-* Notwithstanding the above, under no circumstances may you combine this +-* software in any way with any other Broadcom software provided under a +-* license other than the GPL, without Broadcom's express prior written +-* consent. +-*****************************************************************************/ +- +-/***************************************************************************** +-* +-* This file provides a generic command line interface which allows +-* vcos internals to be manipulated and/or displayed. +-* +-*****************************************************************************/ +- +-/* ---- Include Files ---------------------------------------------------- */ +- +-#include "interface/vcos/vcos.h" +- +-#ifdef HAVE_VCOS_VERSION +-#include "interface/vcos/vcos_build_info.h" +-#endif +- +- #ifdef _VIDEOCORE +-#include vcfw/logging/logging.h +-#endif +- +-/* ---- Public Variables ------------------------------------------------- */ +- +-/* ---- Private Constants and Types -------------------------------------- */ +- +-#define VCOS_LOG_CATEGORY (&vcos_cmd_log_category) +-VCOS_LOG_CAT_T vcos_cmd_log_category; +- +-/* ---- Private Variables ------------------------------------------------ */ +- +-static struct VCOS_CMD_GLOBALS_T +-{ +- VCOS_MUTEX_T lock; +- VCOS_ONCE_T initialized; +- +- unsigned num_cmd_entries; +- unsigned num_cmd_alloc; +- VCOS_CMD_T *cmd_entry; +- +- VCOS_LOG_CAT_T *log_category; +-} cmd_globals; +- +-/* ---- Private Function Prototypes -------------------------------------- */ +- +-static VCOS_STATUS_T help_cmd( VCOS_CMD_PARAM_T *param ); +- +-/* ---- Functions ------------------------------------------------------- */ +- +-/***************************************************************************** +-* +-* Walks through the commands looking for a particular command +-* +-*****************************************************************************/ +- +-static VCOS_CMD_T *find_cmd( VCOS_CMD_T *cmd_entry, const char *name ) +-{ +- VCOS_CMD_T *scan_entry = cmd_entry; +- +- while ( scan_entry->name != NULL ) +- { +- if ( vcos_strcmp( scan_entry->name, name ) == 0 ) +- { +- return scan_entry; +- } +- scan_entry++; +- } +- +- return NULL; +-} +- +-/***************************************************************************** +-* +-* Saves away +-* each line individually. +-* +-*****************************************************************************/ +- +-void vcos_cmd_always_log_output( VCOS_LOG_CAT_T *log_category ) +-{ +- cmd_globals.log_category = log_category; +-} +- +-/***************************************************************************** +-* +-* Walks through a buffer containing newline separated lines, and logs +-* each line individually. +-* +-*****************************************************************************/ +- +-static void cmd_log_results( VCOS_CMD_PARAM_T *param ) +-{ +- char *start; +- char *end; +- +- start = end = param->result_buf; +- +- while ( *start != '\0' ) +- { +- while (( *end != '\0' ) && ( *end != '\n' )) +- end++; +- +- if ( *end == '\n' ) +- { +- *end++ = '\0'; +- } +- +- if ( cmd_globals.log_category != NULL ) +- { +- if ( vcos_is_log_enabled( cmd_globals.log_category, VCOS_LOG_INFO )) +- { +- vcos_log_impl( cmd_globals.log_category, VCOS_LOG_INFO, "%s", start ); +- } +- } +- else +- { +- vcos_log_info( "%s", start ); +- } +- +- start = end; +- } +- +- /* Since we logged the buffer, reset the pointer back to the beginning. */ +- +- param->result_ptr = param->result_buf; +- param->result_buf[0] = '\0'; +-} +- +-/***************************************************************************** +-* +-* Since we may have limited output space, we create a generic routine +-* which tries to use the result space, but will switch over to using +-* logging if the output is too large. +-* +-*****************************************************************************/ +- +-void vcos_cmd_vprintf( VCOS_CMD_PARAM_T *param, const char *fmt, va_list args ) +-{ +- int bytes_written; +- int bytes_remaining; +- +- bytes_remaining = (int)(param->result_size - ( param->result_ptr - param->result_buf )); +- +- bytes_written = vcos_vsnprintf( param->result_ptr, bytes_remaining, fmt, args ); +- +- if ( cmd_globals.log_category != NULL ) +- { +- /* We're going to log each line as we encounter it. If the buffer +- * doesn't end in a newline, then we'll wait for one first. +- */ +- +- if ( (( bytes_written + 1 ) >= bytes_remaining ) +- || ( param->result_ptr[ bytes_written - 1 ] == '\n' )) +- { +- cmd_log_results( param ); +- } +- else +- { +- param->result_ptr += bytes_written; +- } +- } +- else +- { +- if (( bytes_written + 1 ) >= bytes_remaining ) +- { +- /* Output doesn't fit - switch over to logging */ +- +- param->use_log = 1; +- +- *param->result_ptr = '\0'; /* Zap the partial line that didn't fit above. */ +- +- cmd_log_results( param ); /* resets result_ptr */ +- +- bytes_written = vcos_vsnprintf( param->result_ptr, bytes_remaining, fmt, args ); +- } +- param->result_ptr += bytes_written; +- } +-} +- +-/***************************************************************************** +-* +-* Prints the output. +-* +-*****************************************************************************/ +- +-void vcos_cmd_printf( VCOS_CMD_PARAM_T *param, const char *fmt, ... ) +-{ +- va_list args; +- +- va_start( args, fmt ); +- vcos_cmd_vprintf( param, fmt, args ); +- va_end( args ); +-} +- +-/***************************************************************************** +-* +-* Prints the arguments which were on the command line prior to ours. +-* +-*****************************************************************************/ +- +-static void print_argument_prefix( VCOS_CMD_PARAM_T *param ) +-{ +- int arg_idx; +- +- for ( arg_idx = 0; ¶m->argv_orig[arg_idx] != param->argv; arg_idx++ ) +- { +- vcos_cmd_printf( param, "%s ", param->argv_orig[arg_idx] ); +- } +-} +- +-/***************************************************************************** +-* +-* Prints an error message, prefixed by the command chain required to get +-* to where we're at. +-* +-*****************************************************************************/ +- +-void vcos_cmd_error( VCOS_CMD_PARAM_T *param, const char *fmt, ... ) +-{ +- va_list args; +- +- print_argument_prefix( param ); +- +- va_start( args, fmt ); +- vcos_cmd_vprintf( param, fmt, args ); +- va_end( args ); +- vcos_cmd_printf( param, "\n" ); +-} +- +-/**************************************************************************** +-* +-* usage - prints command usage for an array of commands. +-* +-***************************************************************************/ +- +-static void usage( VCOS_CMD_PARAM_T *param, VCOS_CMD_T *cmd_entry ) +-{ +- int cmd_idx; +- int nameWidth = 0; +- int argsWidth = 0; +- VCOS_CMD_T *scan_entry; +- +- vcos_cmd_printf( param, "Usage: " ); +- print_argument_prefix( param ); +- vcos_cmd_printf( param, "command [args ...]\n" ); +- vcos_cmd_printf( param, "\n" ); +- vcos_cmd_printf( param, "Where command is one of the following:\n" ); +- +- for ( cmd_idx = 0; cmd_entry[cmd_idx].name != NULL; cmd_idx++ ) +- { +- int aw; +- int nw; +- +- scan_entry = &cmd_entry[cmd_idx]; +- +- nw = vcos_strlen( scan_entry->name ); +- aw = vcos_strlen( scan_entry->args ); +- +- if ( nw > nameWidth ) +- { +- nameWidth = nw; +- } +- if ( aw > argsWidth ) +- { +- argsWidth = aw; +- } +- } +- +- for ( cmd_idx = 0; cmd_entry[cmd_idx].name != NULL; cmd_idx++ ) +- { +- scan_entry = &cmd_entry[cmd_idx]; +- +- vcos_cmd_printf( param, " %-*s %-*s - %s\n", +- nameWidth, scan_entry->name, +- argsWidth, scan_entry->args, +- scan_entry->descr ); +- } +-} +- +-/**************************************************************************** +-* +-* Prints the usage for the current command. +-* +-***************************************************************************/ +- +-void vcos_cmd_usage( VCOS_CMD_PARAM_T *param ) +-{ +- VCOS_CMD_T *cmd_entry; +- +- cmd_entry = param->cmd_entry; +- +- if ( cmd_entry->sub_cmd_entry != NULL ) +- { +- /* This command is command with sub-commands */ +- +- usage( param, param->cmd_entry->sub_cmd_entry ); +- } +- else +- { +- vcos_cmd_printf( param, "Usage: " ); +- print_argument_prefix( param ); +- vcos_cmd_printf( param, "%s - %s\n", +- param->cmd_entry->args, +- param->cmd_entry->descr ); +- } +-} +- +-/***************************************************************************** +-* +-* Command to print out the help +-* +-* This help command is only called from the main menu. +-* +-*****************************************************************************/ +- +-static VCOS_STATUS_T help_cmd( VCOS_CMD_PARAM_T *param ) +-{ +- VCOS_CMD_T *found_entry; +- +-#if 0 +- { +- int arg_idx; +- +- vcos_log_trace( "%s: argc = %d", __func__, param->argc ); +- for ( arg_idx = 0; arg_idx < param->argc; arg_idx++ ) +- { +- vcos_log_trace( "%s: argv[%d] = '%s'", __func__, arg_idx, param->argv[arg_idx] ); +- } +- } +-#endif +- +- /* If there is an argument after the word help, then we want to print +- * help for that command. +- */ +- +- if ( param->argc == 1 ) +- { +- if ( param->cmd_parent_entry == cmd_globals.cmd_entry ) +- { +- /* Bare help - print the command usage for the root */ +- +- usage( param, cmd_globals.cmd_entry ); +- return VCOS_SUCCESS; +- } +- +- /* For all other cases help requires an argument */ +- +- vcos_cmd_error( param, "%s requires an argument", param->argv[0] ); +- return VCOS_EINVAL; +- } +- +- /* We were given an argument. */ +- +- if (( found_entry = find_cmd( param->cmd_parent_entry, param->argv[1] )) != NULL ) +- { +- /* Make it look like the command that was specified is the one that's +- * currently running +- */ +- +- param->cmd_entry = found_entry; +- param->argv[0] = param->argv[1]; +- param->argv++; +- param->argc--; +- +- vcos_cmd_usage( param ); +- return VCOS_SUCCESS; +- } +- +- vcos_cmd_error( param, "- unrecognized command: '%s'", param->argv[1] ); +- return VCOS_ENOENT; +-} +- +-/***************************************************************************** +-* +-* Command to print out the version/build information. +-* +-*****************************************************************************/ +- +-#ifdef HAVE_VCOS_VERSION +- +-static VCOS_STATUS_T version_cmd( VCOS_CMD_PARAM_T *param ) +-{ +- static const char* copyright = "Copyright (c) 2011 Broadcom"; +- +- vcos_cmd_printf( param, "%s %s\n%s\nversion %s\n", +- vcos_get_build_date(), +- vcos_get_build_time(), +- copyright, +- vcos_get_build_version() ); +- +- return VCOS_SUCCESS; +-} +- +-#endif +- +-/***************************************************************************** +-* +-* Internal commands +-* +-*****************************************************************************/ +- +-static VCOS_CMD_T cmd_help = { "help", "[command]", help_cmd, NULL, "Prints command help information" }; +- +-#ifdef HAVE_VCOS_VERSION +-static VCOS_CMD_T cmd_version = { "version", "", version_cmd, NULL, "Prints build/version information" }; +-#endif +- +-/***************************************************************************** +-* +-* Walks the command table and executes the commands +-* +-*****************************************************************************/ +- +-static VCOS_STATUS_T execute_cmd( VCOS_CMD_PARAM_T *param, VCOS_CMD_T *cmd_entry ) +-{ +- const char *cmdStr; +- VCOS_CMD_T *found_entry; +- +-#if 0 +- { +- int arg_idx; +- +- vcos_cmd_printf( param, "%s: argc = %d", __func__, param->argc ); +- for ( arg_idx = 0; arg_idx < param->argc; arg_idx++ ) +- { +- vcos_cmd_printf( param, " argv[%d] = '%s'", arg_idx, param->argv[arg_idx] ); +- } +- vcos_cmd_printf( param, "\n" ); +- } +-#endif +- +- if ( param->argc <= 1 ) +- { +- /* No command specified */ +- +- vcos_cmd_error( param, "%s - no command specified", param->argv[0] ); +- return VCOS_EINVAL; +- } +- +- /* argv[0] is the command/program that caused us to get invoked, so we strip +- * it off. +- */ +- +- param->argc--; +- param->argv++; +- param->cmd_parent_entry = cmd_entry; +- +- /* Not the help command, scan for the command and execute it. */ +- +- cmdStr = param->argv[0]; +- +- if (( found_entry = find_cmd( cmd_entry, cmdStr )) != NULL ) +- { +- if ( found_entry->sub_cmd_entry != NULL ) +- { +- return execute_cmd( param, found_entry->sub_cmd_entry ); +- } +- +- param->cmd_entry = found_entry; +- return found_entry->cmd_fn( param ); +- } +- +- /* Unrecognized command - check to see if it was the help command */ +- +- if ( vcos_strcmp( cmdStr, cmd_help.name ) == 0 ) +- { +- return help_cmd( param ); +- } +- +- vcos_cmd_error( param, "- unrecognized command: '%s'", cmdStr ); +- return VCOS_ENOENT; +-} +- +-/***************************************************************************** +-* +-* Initializes the command line parser. +-* +-*****************************************************************************/ +- +-static void vcos_cmd_init( void ) +-{ +- vcos_mutex_create( &cmd_globals.lock, "vcos_cmd" ); +- +- cmd_globals.num_cmd_entries = 0; +- cmd_globals.num_cmd_alloc = 0; +- cmd_globals.cmd_entry = NULL; +-} +- +-/***************************************************************************** +-* +-* Command line processor. +-* +-*****************************************************************************/ +- +-VCOS_STATUS_T vcos_cmd_execute( int argc, char **argv, size_t result_size, char *result_buf ) +-{ +- VCOS_STATUS_T rc = VCOS_EINVAL; +- VCOS_CMD_PARAM_T param; +- +- vcos_once( &cmd_globals.initialized, vcos_cmd_init ); +- +- param.argc = argc; +- param.argv = param.argv_orig = argv; +- +- param.use_log = 0; +- param.result_size = result_size; +- param.result_ptr = result_buf; +- param.result_buf = result_buf; +- +- result_buf[0] = '\0'; +- +- vcos_mutex_lock( &cmd_globals.lock ); +- +- rc = execute_cmd( ¶m, cmd_globals.cmd_entry ); +- +- if ( param.use_log ) +- { +- cmd_log_results( ¶m ); +- vcos_snprintf( result_buf, result_size, "results logged" ); +- } +- else +- if ( cmd_globals.log_category != NULL ) +- { +- if ( result_buf[0] != '\0' ) +- { +- /* There is a partial line still buffered. */ +- +- vcos_cmd_printf( ¶m, "\n" ); +- } +- } +- +- vcos_mutex_unlock( &cmd_globals.lock ); +- +- return rc; +-} +- +-/***************************************************************************** +-* +-* Registers a command entry with the command line processor +-* +-*****************************************************************************/ +- +-VCOS_STATUS_T vcos_cmd_register( VCOS_CMD_T *cmd_entry ) +-{ +- VCOS_STATUS_T rc; +- VCOS_UNSIGNED new_num_cmd_alloc; +- VCOS_CMD_T *new_cmd_entry; +- VCOS_CMD_T *old_cmd_entry; +- VCOS_CMD_T *scan_entry; +- +- vcos_once( &cmd_globals.initialized, vcos_cmd_init ); +- +- vcos_assert( cmd_entry != NULL ); +- vcos_assert( cmd_entry->name != NULL ); +- +- vcos_log_trace( "%s: cmd '%s'", __FUNCTION__, cmd_entry->name ); +- +- vcos_assert( cmd_entry->args != NULL ); +- vcos_assert(( cmd_entry->cmd_fn != NULL ) || ( cmd_entry->sub_cmd_entry != NULL )); +- vcos_assert( cmd_entry->descr != NULL ); +- +- /* We expect vcos_cmd_init to be called before vcos_logging_init, so we +- * need to defer registering our logging category until someplace +- * like right here. +- */ +- +- if ( vcos_cmd_log_category.name == NULL ) +- { +- /* +- * If you're using the command interface, you pretty much always want +- * log messages from this file to show up. So we change the default +- * from ERROR to be the more reasonable INFO level. +- */ +- +- vcos_log_set_level(&vcos_cmd_log_category, VCOS_LOG_INFO); +- vcos_log_register("vcos_cmd", &vcos_cmd_log_category); +- +- /* We register a help command so that it shows up in the usage. */ +- +- vcos_cmd_register( &cmd_help ); +-#ifdef HAVE_VCOS_VERSION +- vcos_cmd_register( &cmd_version ); +-#endif +- } +- +- vcos_mutex_lock( &cmd_globals.lock ); +- +- if ( cmd_globals.num_cmd_entries >= cmd_globals.num_cmd_alloc ) +- { +- if ( cmd_globals.num_cmd_alloc == 0 ) +- { +- /* We haven't allocated a table yet */ +- } +- +- /* The number 8 is rather arbitrary. */ +- +- new_num_cmd_alloc = cmd_globals.num_cmd_alloc + 8; +- +- /* The + 1 is to ensure that we always have a NULL entry at the end. */ +- +- new_cmd_entry = (VCOS_CMD_T *)vcos_calloc( new_num_cmd_alloc + 1, sizeof( *cmd_entry ), "vcos_cmd_entries" ); +- if ( new_cmd_entry == NULL ) +- { +- rc = VCOS_ENOMEM; +- goto out; +- } +- memcpy( new_cmd_entry, cmd_globals.cmd_entry, cmd_globals.num_cmd_entries * sizeof( *cmd_entry )); +- cmd_globals.num_cmd_alloc = new_num_cmd_alloc; +- old_cmd_entry = cmd_globals.cmd_entry; +- cmd_globals.cmd_entry = new_cmd_entry; +- vcos_free( old_cmd_entry ); +- } +- +- if ( cmd_globals.num_cmd_entries == 0 ) +- { +- /* This is the first command being registered */ +- +- cmd_globals.cmd_entry[0] = *cmd_entry; +- } +- else +- { +- /* Keep the list in alphabetical order. We start at the end and work backwards +- * shuffling entries up one until we find an insertion point. +- */ +- +- for ( scan_entry = &cmd_globals.cmd_entry[cmd_globals.num_cmd_entries - 1]; +- scan_entry >= cmd_globals.cmd_entry; scan_entry-- ) +- { +- if ( vcos_strcmp( cmd_entry->name, scan_entry->name ) > 0 ) +- { +- /* We found an insertion point. */ +- +- break; +- } +- +- scan_entry[1] = scan_entry[0]; +- } +- scan_entry[1] = *cmd_entry; +- } +- cmd_globals.num_cmd_entries++; +- +- rc = VCOS_SUCCESS; +- +-out: +- +- vcos_mutex_unlock( &cmd_globals.lock ); +- return rc; +-} +- +-/***************************************************************************** +-* +-* Registers multiple commands. +-* +-*****************************************************************************/ +- +-VCOS_STATUS_T vcos_cmd_register_multiple( VCOS_CMD_T *cmd_entry ) +-{ +- VCOS_STATUS_T status; +- +- while ( cmd_entry->name != NULL ) +- { +- if (( status = vcos_cmd_register( cmd_entry )) != VCOS_SUCCESS ) +- { +- return status; +- } +- cmd_entry++; +- } +- return VCOS_SUCCESS; +-} +- +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/generic/vcos_common.h +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vcos/generic/vcos_common.h 2013-07-26 19:32:07.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,87 +0,0 @@ +-/* +- * Copyright (c) 2010-2011 Broadcom. All rights reserved. +- * +- * This program is free software; you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation; either version 2 of the License, or +- * (at your option) any later version. +- * +- * This program is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with this program; if not, write to the Free Software +- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +- */ +- +-/*============================================================================= +-VideoCore OS Abstraction Layer - common postamble code +-=============================================================================*/ +- +-/** \file +- * +- * Postamble code included by the platform-specific header files +- */ +- +-#define VCOS_THREAD_PRI_DEFAULT VCOS_THREAD_PRI_NORMAL +- +-#if !defined(VCOS_THREAD_PRI_INCREASE) +-#error Which way to thread priorities go? +-#endif +- +-#if VCOS_THREAD_PRI_INCREASE < 0 +-/* smaller numbers are higher priority */ +-#define VCOS_THREAD_PRI_LESS(x) ((x)VCOS_THREAD_PRI_MIN?(x)-1:VCOS_THREAD_PRI_MIN) +-#else +-/* bigger numbers are lower priority */ +-#define VCOS_THREAD_PRI_MORE(x) ((x)VCOS_THREAD_PRI_MIN?(x)-1:VCOS_THREAD_PRI_MIN) +-#endif +- +-/* Convenience for Brits: */ +-#define VCOS_APPLICATION_INITIALISE VCOS_APPLICATION_INITIALIZE +- +-/* +- * Check for constant definitions +- */ +-#ifndef VCOS_TICKS_PER_SECOND +-#error VCOS_TICKS_PER_SECOND not defined +-#endif +- +-#if !defined(VCOS_THREAD_PRI_MIN) || !defined(VCOS_THREAD_PRI_MAX) +-#error Priority range not defined +-#endif +- +-#if !defined(VCOS_THREAD_PRI_HIGHEST) || !defined(VCOS_THREAD_PRI_LOWEST) || !defined(VCOS_THREAD_PRI_NORMAL) +-#error Priority ordering not defined +-#endif +- +-#if !defined(VCOS_CAN_SET_STACK_ADDR) +-#error Can stack addresses be set on this platform? Please set this macro to either 0 or 1. +-#endif +- +-#if (_VCOS_AFFINITY_CPU0|_VCOS_AFFINITY_CPU1) & (~_VCOS_AFFINITY_MASK) +-#error _VCOS_AFFINITY_CPUxxx values are not consistent with _VCOS_AFFINITY_MASK +-#endif +- +-/** Append to the end of a singly-linked queue, O(1). Works with +- * any structure where list has members 'head' and 'tail' and +- * item has a 'next' pointer. +- */ +-#define VCOS_QUEUE_APPEND_TAIL(list, item) {\ +- (item)->next = NULL;\ +- if (!(list)->head) {\ +- (list)->head = (list)->tail = (item); \ +- } else {\ +- (list)->tail->next = (item); \ +- (list)->tail = (item); \ +- } \ +-} +- +-#ifndef VCOS_HAVE_TIMER +-VCOSPRE_ void VCOSPOST_ vcos_timer_init(void); +-#endif +- +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/generic/vcos_generic_blockpool.h +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vcos/generic/vcos_generic_blockpool.h 2013-07-26 19:32:07.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,271 +0,0 @@ +-/* +- * Copyright (c) 2010-2011 Broadcom. All rights reserved. +- * +- * This program is free software; you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation; either version 2 of the License, or +- * (at your option) any later version. +- * +- * This program is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with this program; if not, write to the Free Software +- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +- */ +- +-/*============================================================================= +-VideoCore OS Abstraction Layer - event flags implemented via a semaphore +-=============================================================================*/ +- +-#ifndef VCOS_GENERIC_BLOCKPOOL_H +-#define VCOS_GENERIC_BLOCKPOOL_H +- +-/** +- * \file +- * +- * This provides a generic, thread safe implementation of a VCOS block pool +- * fixed size memory allocator. +- */ +- +-#ifdef __cplusplus +-extern "C" { +-#endif +- +-#include "interface/vcos/vcos_types.h" +- +-/** Bits 0 to (VCOS_BLOCKPOOL_SUBPOOL_BITS - 1) are used to store the +- * subpool id. */ +-#define VCOS_BLOCKPOOL_SUBPOOL_BITS 3 +-#define VCOS_BLOCKPOOL_MAX_SUBPOOLS (1 << VCOS_BLOCKPOOL_SUBPOOL_BITS) +- +-/* Make zero an invalid handle at the cost of decreasing the maximum +- * number of blocks (2^28) by 1. Alternatively, a spare bit could be +- * used to indicated valid blocks but there are likely to be better +- * uses for spare bits. e.g. allowing more subpools +- */ +-#define INDEX_OFFSET 1 +- +-#define VCOS_BLOCKPOOL_HANDLE_GET_INDEX(h) \ +- (((h) >> VCOS_BLOCKPOOL_SUBPOOL_BITS) - INDEX_OFFSET) +- +-#define VCOS_BLOCKPOOL_HANDLE_GET_SUBPOOL(h) \ +- ((h) & ((1 << VCOS_BLOCKPOOL_SUBPOOL_BITS) - 1)) +- +-#define VCOS_BLOCKPOOL_HANDLE_CREATE(i,s) \ +- ((((i) + INDEX_OFFSET) << VCOS_BLOCKPOOL_SUBPOOL_BITS) | (s)) +- +-#define VCOS_BLOCKPOOL_INVALID_HANDLE 0 +- +-typedef struct VCOS_BLOCKPOOL_HEADER_TAG +-{ +- /* Blocks either refer to to the pool if they are allocated +- * or the free list if they are available. +- */ +- union { +- struct VCOS_BLOCKPOOL_HEADER_TAG *next; +- struct VCOS_BLOCKPOOL_SUBPOOL_TAG* subpool; +- } owner; +-} VCOS_BLOCKPOOL_HEADER_T; +- +-typedef struct VCOS_BLOCKPOOL_SUBPOOL_TAG +-{ +- /** VCOS_BLOCKPOOL_SUBPOOL_MAGIC */ +- uint32_t magic; +- VCOS_BLOCKPOOL_HEADER_T* free_list; +- /* The start of the pool memory */ +- void *mem; +- /* Address of the first block header */ +- void *start; +- /** The number of blocks in this sub-pool */ +- VCOS_UNSIGNED num_blocks; +- /** Current number of available blocks in this sub-pool */ +- VCOS_UNSIGNED available_blocks; +- /** Pointers to the pool that owns this sub-pool */ +- struct VCOS_BLOCKPOOL_TAG* owner; +- /** Define properties such as memory ownership */ +- uint32_t flags; +-} VCOS_BLOCKPOOL_SUBPOOL_T; +- +-typedef struct VCOS_BLOCKPOOL_TAG +-{ +- /** VCOS_BLOCKPOOL_MAGIC */ +- uint32_t magic; +- /** Thread safety for Alloc, Free, Delete, Stats */ +- VCOS_MUTEX_T mutex; +- /** The size of the block data */ +- size_t block_data_size; +- /** Block size inc overheads */ +- size_t block_size; +- /** Name for debugging */ +- const char *name; +- /* The number of subpools that may be used */ +- VCOS_UNSIGNED num_subpools; +- /** Number of blocks in each dynamically allocated subpool */ +- VCOS_UNSIGNED num_extension_blocks; +- /** Array of subpools. Subpool zero is is not deleted until the pool is +- * destroed. If the index of the pool is < num_subpools and +- * subpool[index.mem] is null then the subpool entry is valid but +- * "not currently allocated" */ +- VCOS_BLOCKPOOL_SUBPOOL_T subpools[VCOS_BLOCKPOOL_MAX_SUBPOOLS]; +-} VCOS_BLOCKPOOL_T; +- +-#define VCOS_BLOCKPOOL_ROUND_UP(x,s) (((x) + ((s) - 1)) & ~((s) - 1)) +-/** +- * Calculates the size in bytes required for a block pool containing +- * num_blocks of size block_size plus any overheads. +- * +- * The block pool header (VCOS_BLOCKPOOL_T) is allocated separately +- * +- * Overheads: +- * block_size + header must be a multiple of sizeof(void*) +- * The start of the first block may need to be up to wordsize - 1 bytes +- * into the given buffer because statically allocated buffers within structures +- * are not guaranteed to be word aligned. +- */ +-#define VCOS_BLOCKPOOL_SIZE(num_blocks, block_size) \ +- ((VCOS_BLOCKPOOL_ROUND_UP((block_size) + sizeof(VCOS_BLOCKPOOL_HEADER_T), \ +- sizeof(void*)) * (num_blocks)) + sizeof(void*)) +- +-/** +- * Sanity check to verify whether a handle is potentially a blockpool handle +- * when the pool pointer is not available. +- * +- * If the pool pointer is availabe use vcos_blockpool_elem_to_handle instead. +- * +- * @param handle the handle to verify +- * @param max_blocks the expected maximum number of block in the pool +- * that the handle belongs to. +- */ +-#define VCOS_BLOCKPOOL_IS_VALID_HANDLE_FORMAT(handle, max_blocks) \ +- ((handle) != VCOS_BLOCKPOOL_INVALID_HANDLE \ +- && VCOS_BLOCKPOOL_HANDLE_GET_INDEX((handle)) < (max_blocks)) +- +-VCOSPRE_ +- VCOS_STATUS_T VCOSPOST_ vcos_generic_blockpool_init(VCOS_BLOCKPOOL_T *pool, +- VCOS_UNSIGNED num_blocks, VCOS_UNSIGNED block_size, +- void *start, VCOS_UNSIGNED pool_size, const char *name); +- +-VCOSPRE_ +- VCOS_STATUS_T VCOSPOST_ vcos_generic_blockpool_create_on_heap( +- VCOS_BLOCKPOOL_T *pool, VCOS_UNSIGNED num_blocks, +- VCOS_UNSIGNED block_size, const char *name); +- +-VCOSPRE_ +- VCOS_STATUS_T VCOSPOST_ vcos_generic_blockpool_extend(VCOS_BLOCKPOOL_T *pool, +- VCOS_UNSIGNED num_extensions, VCOS_UNSIGNED num_blocks); +- +-VCOSPRE_ void VCOSPOST_ *vcos_generic_blockpool_alloc(VCOS_BLOCKPOOL_T *pool); +- +-VCOSPRE_ void VCOSPOST_ *vcos_generic_blockpool_calloc(VCOS_BLOCKPOOL_T *pool); +- +-VCOSPRE_ void VCOSPOST_ vcos_generic_blockpool_free(void *block); +- +-VCOSPRE_ +- VCOS_UNSIGNED VCOSPOST_ vcos_generic_blockpool_available_count( +- VCOS_BLOCKPOOL_T *pool); +- +-VCOSPRE_ +- VCOS_UNSIGNED VCOSPOST_ vcos_generic_blockpool_used_count( +- VCOS_BLOCKPOOL_T *pool); +- +-VCOSPRE_ void VCOSPOST_ vcos_generic_blockpool_delete(VCOS_BLOCKPOOL_T *pool); +- +-VCOSPRE_ uint32_t VCOSPOST_ vcos_generic_blockpool_elem_to_handle(void *block); +- +-VCOSPRE_ void VCOSPOST_ +- *vcos_generic_blockpool_elem_from_handle( +- VCOS_BLOCKPOOL_T *pool, uint32_t handle); +- +-VCOSPRE_ uint32_t VCOSPOST_ +- vcos_generic_blockpool_is_valid_elem( +- VCOS_BLOCKPOOL_T *pool, const void *block); +-#if defined(VCOS_INLINE_BODIES) +- +-VCOS_INLINE_IMPL +-VCOS_STATUS_T vcos_blockpool_init(VCOS_BLOCKPOOL_T *pool, +- VCOS_UNSIGNED num_blocks, VCOS_UNSIGNED block_size, +- void *start, VCOS_UNSIGNED pool_size, const char *name) +-{ +- return vcos_generic_blockpool_init(pool, num_blocks, block_size, +- start, pool_size, name); +-} +- +-VCOS_INLINE_IMPL +-VCOS_STATUS_T vcos_blockpool_create_on_heap(VCOS_BLOCKPOOL_T *pool, +- VCOS_UNSIGNED num_blocks, VCOS_UNSIGNED block_size, const char *name) +-{ +- return vcos_generic_blockpool_create_on_heap( +- pool, num_blocks, block_size, name); +-} +- +-VCOS_INLINE_IMPL +- VCOS_STATUS_T VCOSPOST_ vcos_blockpool_extend(VCOS_BLOCKPOOL_T *pool, +- VCOS_UNSIGNED num_extensions, VCOS_UNSIGNED num_blocks) +-{ +- return vcos_generic_blockpool_extend(pool, num_extensions, num_blocks); +-} +- +-VCOS_INLINE_IMPL +-void *vcos_blockpool_alloc(VCOS_BLOCKPOOL_T *pool) +-{ +- return vcos_generic_blockpool_alloc(pool); +-} +- +-VCOS_INLINE_IMPL +-void *vcos_blockpool_calloc(VCOS_BLOCKPOOL_T *pool) +-{ +- return vcos_generic_blockpool_calloc(pool); +-} +- +-VCOS_INLINE_IMPL +-void vcos_blockpool_free(void *block) +-{ +- vcos_generic_blockpool_free(block); +-} +- +-VCOS_INLINE_IMPL +-VCOS_UNSIGNED vcos_blockpool_available_count(VCOS_BLOCKPOOL_T *pool) +-{ +- return vcos_generic_blockpool_available_count(pool); +-} +- +-VCOS_INLINE_IMPL +-VCOS_UNSIGNED vcos_blockpool_used_count(VCOS_BLOCKPOOL_T *pool) +-{ +- return vcos_generic_blockpool_used_count(pool); +-} +- +-VCOS_INLINE_IMPL +-void vcos_blockpool_delete(VCOS_BLOCKPOOL_T *pool) +-{ +- vcos_generic_blockpool_delete(pool); +-} +- +-VCOS_INLINE_IMPL +-uint32_t vcos_blockpool_elem_to_handle(void *block) +-{ +- return vcos_generic_blockpool_elem_to_handle(block); +-} +- +-VCOS_INLINE_IMPL +-void *vcos_blockpool_elem_from_handle(VCOS_BLOCKPOOL_T *pool, uint32_t handle) +-{ +- return vcos_generic_blockpool_elem_from_handle(pool, handle); +-} +- +-VCOS_INLINE_IMPL +-uint32_t vcos_blockpool_is_valid_elem(VCOS_BLOCKPOOL_T *pool, const void *block) +-{ +- return vcos_generic_blockpool_is_valid_elem(pool, block); +-} +-#endif /* VCOS_INLINE_BODIES */ +- +- +-#ifdef __cplusplus +-} +-#endif +-#endif /* VCOS_GENERIC_BLOCKPOOL_H */ +- +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/generic/vcos_generic_event_flags.c +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vcos/generic/vcos_generic_event_flags.c 2013-07-26 19:32:07.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,311 +0,0 @@ +-/* +- * Copyright (c) 2010-2011 Broadcom. All rights reserved. +- * +- * This program is free software; you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation; either version 2 of the License, or +- * (at your option) any later version. +- * +- * This program is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with this program; if not, write to the Free Software +- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +- */ +- +-/*============================================================================= +-VideoCore OS Abstraction Layer - event flags implemented via mutexes +-=============================================================================*/ +- +-#include "interface/vcos/vcos.h" +-#include "interface/vcos/generic/vcos_generic_event_flags.h" +- +-#include +- +-/** A structure created by a thread that waits on the event flags +- * for a particular combination of flags to arrive. +- */ +-typedef struct VCOS_EVENT_WAITER_T +-{ +- VCOS_UNSIGNED requested_events; /**< The events wanted */ +- VCOS_UNSIGNED actual_events; /**< Actual events found */ +- VCOS_UNSIGNED op; /**< The event operation to be used */ +- VCOS_STATUS_T return_status; /**< The return status the waiter should pass back */ +- VCOS_EVENT_FLAGS_T *flags; /**< Pointer to the original 'flags' structure */ +- VCOS_THREAD_T *thread; /**< Thread waiting */ +- struct VCOS_EVENT_WAITER_T *next; +-} VCOS_EVENT_WAITER_T; +- +-#ifndef NDEBUG +-static int waiter_list_valid(VCOS_EVENT_FLAGS_T *flags); +-#endif +-static void event_flags_timer_expired(void *cxt); +- +-VCOS_STATUS_T vcos_generic_event_flags_create(VCOS_EVENT_FLAGS_T *flags, const char *name) +-{ +- VCOS_STATUS_T rc; +- if ((rc=vcos_mutex_create(&flags->lock, name)) != VCOS_SUCCESS) +- { +- return rc; +- } +- +- flags->events = 0; +- flags->waiters.head = flags->waiters.tail = 0; +- return rc; +-} +- +-void vcos_generic_event_flags_set(VCOS_EVENT_FLAGS_T *flags, +- VCOS_UNSIGNED bitmask, +- VCOS_OPTION op) +-{ +- vcos_assert(flags); +- vcos_mutex_lock(&flags->lock); +- if (op == VCOS_OR) +- { +- flags->events |= bitmask; +- } +- else if (op == VCOS_AND) +- { +- flags->events &= bitmask; +- } +- else +- { +- vcos_assert(0); +- } +- +- /* Now wake up any threads that have now become signalled. */ +- if (flags->waiters.head != NULL) +- { +- VCOS_UNSIGNED consumed_events = 0; +- VCOS_EVENT_WAITER_T **pcurrent_waiter = &flags->waiters.head; +- VCOS_EVENT_WAITER_T *prev_waiter = NULL; +- +- /* Walk the chain of tasks suspend on this event flag group to determine +- * if any of their requests can be satisfied. +- */ +- while ((*pcurrent_waiter) != NULL) +- { +- VCOS_EVENT_WAITER_T *curr_waiter = *pcurrent_waiter; +- +- /* Determine if this request has been satisfied */ +- +- /* First, find the event flags in common. */ +- VCOS_UNSIGNED waiter_satisfied = flags->events & curr_waiter->requested_events; +- +- /* Second, determine if all the event flags must match */ +- if (curr_waiter->op & VCOS_AND) +- { +- /* All requested events must be present */ +- waiter_satisfied = (waiter_satisfied == curr_waiter->requested_events); +- } +- +- /* Wake this one up? */ +- if (waiter_satisfied) +- { +- +- if (curr_waiter->op & VCOS_CONSUME) +- { +- consumed_events |= curr_waiter->requested_events; +- } +- +- /* remove this block from the list, taking care at the end */ +- *pcurrent_waiter = curr_waiter->next; +- if (curr_waiter->next == NULL) +- flags->waiters.tail = prev_waiter; +- +- vcos_assert(waiter_list_valid(flags)); +- +- curr_waiter->return_status = VCOS_SUCCESS; +- curr_waiter->actual_events = flags->events; +- +- _vcos_thread_sem_post(curr_waiter->thread); +- } +- else +- { +- /* move to next element in the list */ +- prev_waiter = *pcurrent_waiter; +- pcurrent_waiter = &(curr_waiter->next); +- } +- } +- +- flags->events &= ~consumed_events; +- +- } +- +- vcos_mutex_unlock(&flags->lock); +-} +- +-void vcos_generic_event_flags_delete(VCOS_EVENT_FLAGS_T *flags) +-{ +- vcos_mutex_delete(&flags->lock); +-} +- +-extern VCOS_STATUS_T vcos_generic_event_flags_get(VCOS_EVENT_FLAGS_T *flags, +- VCOS_UNSIGNED bitmask, +- VCOS_OPTION op, +- VCOS_UNSIGNED suspend, +- VCOS_UNSIGNED *retrieved_bits) +-{ +- VCOS_EVENT_WAITER_T waitreq; +- VCOS_STATUS_T rc = VCOS_EAGAIN; +- int satisfied = 0; +- +- vcos_assert(flags); +- +- /* default retrieved bits to 0 */ +- *retrieved_bits = 0; +- +- vcos_mutex_lock(&flags->lock); +- switch (op & VCOS_EVENT_FLAG_OP_MASK) +- { +- case VCOS_AND: +- if ((flags->events & bitmask) == bitmask) +- { +- *retrieved_bits = flags->events; +- rc = VCOS_SUCCESS; +- satisfied = 1; +- if (op & VCOS_CONSUME) +- flags->events &= ~bitmask; +- } +- break; +- +- case VCOS_OR: +- if (flags->events & bitmask) +- { +- *retrieved_bits = flags->events; +- rc = VCOS_SUCCESS; +- satisfied = 1; +- if (op & VCOS_CONSUME) +- flags->events &= ~bitmask; +- } +- break; +- +- default: +- vcos_assert(0); +- rc = VCOS_EINVAL; +- break; +- } +- +- if (!satisfied && suspend) +- { +- /* Have to go to sleep. +- * +- * Append to tail so we get FIFO ordering. +- */ +- waitreq.requested_events = bitmask; +- waitreq.op = op; +- waitreq.return_status = VCOS_EAGAIN; +- waitreq.flags = flags; +- waitreq.actual_events = 0; +- waitreq.thread = vcos_thread_current(); +- waitreq.next = 0; +- vcos_assert(waitreq.thread != (VCOS_THREAD_T*)-1); +- VCOS_QUEUE_APPEND_TAIL(&flags->waiters, &waitreq); +- +- if (suspend != (VCOS_UNSIGNED)-1) +- _vcos_task_timer_set(event_flags_timer_expired, &waitreq, suspend); +- +- vcos_mutex_unlock(&flags->lock); +- /* go to sleep and wait to be signalled or timeout */ +- +- _vcos_thread_sem_wait(); +- +- *retrieved_bits = waitreq.actual_events; +- rc = waitreq.return_status; +- +- /* cancel the timer - do not do this while holding the mutex as it +- * might be waiting for the timeout function to complete, which will +- * try to take the mutex. +- */ +- if (suspend != (VCOS_UNSIGNED)-1) +- _vcos_task_timer_cancel(); +- } +- else +- { +- vcos_mutex_unlock(&flags->lock); +- } +- +- return rc; +-} +- +- +-/** Called when a get call times out. Remove this thread's +- * entry from the waiting queue, then resume the thread. +- */ +-static void event_flags_timer_expired(void *cxt) +-{ +- VCOS_EVENT_WAITER_T *waitreq = (VCOS_EVENT_WAITER_T *)cxt; +- VCOS_EVENT_FLAGS_T *flags = waitreq->flags; +- VCOS_EVENT_WAITER_T **plist; +- VCOS_EVENT_WAITER_T *prev = NULL; +- VCOS_THREAD_T *thread = 0; +- +- vcos_assert(flags); +- +- vcos_mutex_lock(&flags->lock); +- +- /* walk the list of waiting threads on this event group, and remove +- * the one that has expired. +- * +- * FIXME: could use doubly-linked list if lots of threads are found +- * to be waiting on a single event flag instance. +- */ +- plist = &flags->waiters.head; +- while (*plist != NULL) +- { +- if (*plist == waitreq) +- { +- int at_end; +- /* found it */ +- thread = (*plist)->thread; +- at_end = ((*plist)->next == NULL); +- +- /* link past */ +- *plist = (*plist)->next; +- if (at_end) +- flags->waiters.tail = prev; +- +- break; +- } +- prev = *plist; +- plist = &(*plist)->next; +- } +- vcos_assert(waiter_list_valid(flags)); +- +- vcos_mutex_unlock(&flags->lock); +- +- if (thread) +- { +- _vcos_thread_sem_post(thread); +- } +-} +- +-#ifndef NDEBUG +- +-static int waiter_list_valid(VCOS_EVENT_FLAGS_T *flags) +-{ +- int valid; +- /* Either both head and tail are NULL, or neither are NULL */ +- if (flags->waiters.head == NULL) +- { +- valid = (flags->waiters.tail == NULL); +- } +- else +- { +- valid = (flags->waiters.tail != NULL); +- } +- +- /* If head and tail point at the same non-NULL element, then there +- * is only one element in the list. +- */ +- if (flags->waiters.head && (flags->waiters.head == flags->waiters.tail)) +- { +- valid = (flags->waiters.head->next == NULL); +- } +- return valid; +-} +- +-#endif +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/generic/vcos_generic_event_flags.h +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vcos/generic/vcos_generic_event_flags.h 2013-07-26 19:32:07.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,118 +0,0 @@ +-/* +- * Copyright (c) 2010-2011 Broadcom. All rights reserved. +- * +- * This program is free software; you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation; either version 2 of the License, or +- * (at your option) any later version. +- * +- * This program is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with this program; if not, write to the Free Software +- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +- */ +- +-/*============================================================================= +-VideoCore OS Abstraction Layer - event flags implemented via a semaphore +-=============================================================================*/ +- +-#ifndef VCOS_GENERIC_EVENT_FLAGS_H +-#define VCOS_GENERIC_EVENT_FLAGS_H +- +-#ifdef __cplusplus +-extern "C" { +-#endif +- +-#include "interface/vcos/vcos_types.h" +- +-/** +- * \file +- * +- * This provides event flags (as per Nucleus Event Groups) based on a +- * mutex, a semaphore (per waiting thread) and a timer (per waiting +- * thread). +- * +- * The data structure is a 32 bit unsigned int (the current set of +- * flags) and a linked list of clients waiting to be 'satisfied'. +- * +- * The mutex merely locks access to the data structure. If a client +- * calls vcos_event_flags_get() and the requested bits are not already +- * present, it then sleeps on its per-thread semaphore after adding +- * this semaphore to the queue waiting. It also sets up a timer. +- * +- * The per-thread semaphore and timer are actually stored in the +- * thread context (joinable thread). In future it may become necessary +- * to support non-VCOS threads by using thread local storage to +- * create these objects and associate them with the thread. +- */ +- +-struct VCOS_EVENT_WAITER_T; +- +-typedef struct VCOS_EVENT_FLAGS_T +-{ +- VCOS_UNSIGNED events; /**< Events currently set */ +- VCOS_MUTEX_T lock; /**< Serialize access */ +- struct +- { +- struct VCOS_EVENT_WAITER_T *head; /**< List of threads waiting */ +- struct VCOS_EVENT_WAITER_T *tail; /**< List of threads waiting */ +- } waiters; +-} VCOS_EVENT_FLAGS_T; +- +-#define VCOS_OR 1 +-#define VCOS_AND 2 +-#define VCOS_CONSUME 4 +-#define VCOS_OR_CONSUME (VCOS_OR | VCOS_CONSUME) +-#define VCOS_AND_CONSUME (VCOS_AND | VCOS_CONSUME) +-#define VCOS_EVENT_FLAG_OP_MASK (VCOS_OR|VCOS_AND) +- +-VCOSPRE_ VCOS_STATUS_T VCOSPOST_ vcos_generic_event_flags_create(VCOS_EVENT_FLAGS_T *flags, const char *name); +-VCOSPRE_ void VCOSPOST_ vcos_generic_event_flags_set(VCOS_EVENT_FLAGS_T *flags, +- VCOS_UNSIGNED events, +- VCOS_OPTION op); +-VCOSPRE_ void VCOSPOST_ vcos_generic_event_flags_delete(VCOS_EVENT_FLAGS_T *); +-VCOSPRE_ VCOS_STATUS_T VCOSPOST_ vcos_generic_event_flags_get(VCOS_EVENT_FLAGS_T *flags, +- VCOS_UNSIGNED requested_events, +- VCOS_OPTION op, +- VCOS_UNSIGNED suspend, +- VCOS_UNSIGNED *retrieved_events); +- +-#ifdef VCOS_INLINE_BODIES +- +-VCOS_INLINE_IMPL +-VCOS_STATUS_T vcos_event_flags_create(VCOS_EVENT_FLAGS_T *flags, const char *name) { +- return vcos_generic_event_flags_create(flags, name); +-} +- +-VCOS_INLINE_IMPL +-void vcos_event_flags_set(VCOS_EVENT_FLAGS_T *flags, +- VCOS_UNSIGNED events, +- VCOS_OPTION op) { +- vcos_generic_event_flags_set(flags, events, op); +-} +- +-VCOS_INLINE_IMPL +-void vcos_event_flags_delete(VCOS_EVENT_FLAGS_T *f) { +- vcos_generic_event_flags_delete(f); +-} +- +-VCOS_INLINE_IMPL +-VCOS_STATUS_T vcos_event_flags_get(VCOS_EVENT_FLAGS_T *flags, +- VCOS_UNSIGNED requested_events, +- VCOS_OPTION op, +- VCOS_UNSIGNED suspend, +- VCOS_UNSIGNED *retrieved_events) { +- return vcos_generic_event_flags_get(flags, requested_events, op, suspend, retrieved_events); +-} +- +-#endif /* VCOS_INLINE_BODIES */ +- +-#ifdef __cplusplus +-} +-#endif +-#endif +- +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/generic/vcos_generic_named_sem.h +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vcos/generic/vcos_generic_named_sem.h 2013-07-26 19:32:07.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,92 +0,0 @@ +-/* +- * Copyright (c) 2010-2011 Broadcom. All rights reserved. +- * +- * This program is free software; you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation; either version 2 of the License, or +- * (at your option) any later version. +- * +- * This program is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with this program; if not, write to the Free Software +- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +- */ +- +-/*============================================================================= +-VideoCore OS Abstraction Layer - named semaphores +-=============================================================================*/ +- +-#ifndef VCOS_GENERIC_NAMED_SEM_H +-#define VCOS_GENERIC_NAMED_SEM_H +- +-#ifdef __cplusplus +-extern "C" { +-#endif +- +-#include "interface/vcos/vcos_types.h" +- +-/** +- * \file +- * +- * Generic support for named semaphores, using regular ones. This is only +- * suitable for emulating them on an embedded MMUless system, since there is +- * no support for opening semaphores across process boundaries. +- * +- */ +- +-#define VCOS_NAMED_SEMAPHORE_NAMELEN 64 +- +-/* In theory we could use the name facility provided within Nucleus. However, this +- * is hard to do as semaphores are constantly being created and destroyed; we +- * would need to stop everything while allocating the memory for the semaphore +- * list and then walking it. So keep our own list. +- */ +-typedef struct VCOS_NAMED_SEMAPHORE_T +-{ +- struct VCOS_NAMED_SEMAPHORE_IMPL_T *actual; /**< There are 'n' named semaphores per 1 actual semaphore */ +- VCOS_SEMAPHORE_T *sem; /**< Pointer to actual underlying semaphore */ +-} VCOS_NAMED_SEMAPHORE_T; +- +-VCOSPRE_ VCOS_STATUS_T VCOSPOST_ +-vcos_generic_named_semaphore_create(VCOS_NAMED_SEMAPHORE_T *sem, const char *name, VCOS_UNSIGNED count); +- +-VCOSPRE_ void VCOSPOST_ vcos_named_semaphore_delete(VCOS_NAMED_SEMAPHORE_T *sem); +- +-VCOSPRE_ VCOS_STATUS_T VCOSPOST_ _vcos_named_semaphore_init(void); +-VCOSPRE_ void VCOSPOST_ _vcos_named_semaphore_deinit(void); +- +-#if defined(VCOS_INLINE_BODIES) +- +-VCOS_INLINE_IMPL +-VCOS_STATUS_T vcos_named_semaphore_create(VCOS_NAMED_SEMAPHORE_T *sem, const char *name, VCOS_UNSIGNED count) { +- return vcos_generic_named_semaphore_create(sem, name, count); +-} +- +-VCOS_INLINE_IMPL +-void vcos_named_semaphore_wait(VCOS_NAMED_SEMAPHORE_T *sem) { +- vcos_semaphore_wait(sem->sem); +-} +- +-VCOS_INLINE_IMPL +-VCOS_STATUS_T vcos_named_semaphore_trywait(VCOS_NAMED_SEMAPHORE_T *sem) { +- return vcos_semaphore_trywait(sem->sem); +-} +- +-VCOS_INLINE_IMPL +-void vcos_named_semaphore_post(VCOS_NAMED_SEMAPHORE_T *sem) { +- vcos_semaphore_post(sem->sem); +-} +- +- +-#endif +- +-#ifdef __cplusplus +-} +-#endif +-#endif +- +- +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/generic/vcos_generic_quickslow_mutex.h +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vcos/generic/vcos_generic_quickslow_mutex.h 2013-07-26 19:32:07.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,86 +0,0 @@ +-/* +- * Copyright (c) 2010-2011 Broadcom. All rights reserved. +- * +- * This program is free software; you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation; either version 2 of the License, or +- * (at your option) any later version. +- * +- * This program is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with this program; if not, write to the Free Software +- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +- */ +- +-/*============================================================================= +-VideoCore OS Abstraction Layer - reentrant mutexes created from regular ones. +-=============================================================================*/ +- +-#ifndef VCOS_GENERIC_QUICKSLOW_MUTEX_H +-#define VCOS_GENERIC_QUICKSLOW_MUTEX_H +- +-#ifdef __cplusplus +-extern "C" { +-#endif +- +-#include "interface/vcos/vcos_types.h" +- +-/** +- * \file +- * +- * Quickslow Mutexes implemented as regular ones (i.e. quick and slow modes are the same). +- * +- */ +- +-typedef VCOS_MUTEX_T VCOS_QUICKSLOW_MUTEX_T; +- +-#if defined(VCOS_INLINE_BODIES) +-VCOS_INLINE_IMPL +-VCOS_STATUS_T vcos_quickslow_mutex_create(VCOS_QUICKSLOW_MUTEX_T *m, const char *name) +-{ +- return vcos_mutex_create(m, name); +-} +- +-VCOS_INLINE_IMPL +-void vcos_quickslow_mutex_delete(VCOS_QUICKSLOW_MUTEX_T *m) +-{ +- vcos_mutex_delete(m); +-} +- +-VCOS_INLINE_IMPL +-void vcos_quickslow_mutex_lock(VCOS_QUICKSLOW_MUTEX_T *m) +-{ +- while (vcos_mutex_lock(m) == VCOS_EAGAIN); +-} +- +-VCOS_INLINE_IMPL +-void vcos_quickslow_mutex_unlock(VCOS_QUICKSLOW_MUTEX_T *m) +-{ +- vcos_mutex_unlock(m); +-} +- +-VCOS_INLINE_IMPL +-void vcos_quickslow_mutex_lock_quick(VCOS_QUICKSLOW_MUTEX_T *m) +-{ +- while (vcos_mutex_lock(m) == VCOS_EAGAIN); +-} +- +-VCOS_INLINE_IMPL +-void vcos_quickslow_mutex_unlock_quick(VCOS_QUICKSLOW_MUTEX_T *m) +-{ +- vcos_mutex_unlock(m); +-} +- +-#endif +- +- +-#ifdef __cplusplus +-} +-#endif +-#endif +- +- +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/generic/vcos_generic_reentrant_mtx.h +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vcos/generic/vcos_generic_reentrant_mtx.h 2013-07-26 19:32:07.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,86 +0,0 @@ +-/* +- * Copyright (c) 2010-2011 Broadcom. All rights reserved. +- * +- * This program is free software; you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation; either version 2 of the License, or +- * (at your option) any later version. +- * +- * This program is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with this program; if not, write to the Free Software +- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +- */ +- +-/*============================================================================= +-VideoCore OS Abstraction Layer - reentrant mutexes created from regular ones. +-=============================================================================*/ +- +-#ifndef VCOS_GENERIC_REENTRANT_MUTEX_H +-#define VCOS_GENERIC_REENTRANT_MUTEX_H +- +-#ifdef __cplusplus +-extern "C" { +-#endif +- +-#include "interface/vcos/vcos_types.h" +- +-/** +- * \file +- * +- * Reentrant Mutexes from regular ones. +- * +- */ +- +-typedef struct VCOS_REENTRANT_MUTEX_T +-{ +- VCOS_MUTEX_T mutex; +- VCOS_THREAD_T *owner; +- unsigned count; +-} VCOS_REENTRANT_MUTEX_T; +- +-/* Extern definitions of functions that do the actual work */ +- +-VCOSPRE_ VCOS_STATUS_T VCOSPOST_ vcos_generic_reentrant_mutex_create(VCOS_REENTRANT_MUTEX_T *m, const char *name); +- +-VCOSPRE_ void VCOSPOST_ vcos_generic_reentrant_mutex_delete(VCOS_REENTRANT_MUTEX_T *m); +- +-VCOSPRE_ void VCOSPOST_ vcos_generic_reentrant_mutex_lock(VCOS_REENTRANT_MUTEX_T *m); +- +-VCOSPRE_ void VCOSPOST_ vcos_generic_reentrant_mutex_unlock(VCOS_REENTRANT_MUTEX_T *m); +- +-/* Inline forwarding functions */ +- +-#if defined(VCOS_INLINE_BODIES) +- +-VCOS_INLINE_IMPL +-VCOS_STATUS_T vcos_reentrant_mutex_create(VCOS_REENTRANT_MUTEX_T *m, const char *name) { +- return vcos_generic_reentrant_mutex_create(m,name); +-} +- +-VCOS_INLINE_IMPL +-void vcos_reentrant_mutex_delete(VCOS_REENTRANT_MUTEX_T *m) { +- vcos_generic_reentrant_mutex_delete(m); +-} +- +-VCOS_INLINE_IMPL +-void vcos_reentrant_mutex_lock(VCOS_REENTRANT_MUTEX_T *m) { +- vcos_generic_reentrant_mutex_lock(m); +-} +- +-VCOS_INLINE_IMPL +-void vcos_reentrant_mutex_unlock(VCOS_REENTRANT_MUTEX_T *m) { +- vcos_generic_reentrant_mutex_unlock(m); +-} +-#endif +- +-#ifdef __cplusplus +-} +-#endif +-#endif +- +- +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/generic/vcos_generic_tls.h +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vcos/generic/vcos_generic_tls.h 2013-07-26 19:32:07.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,155 +0,0 @@ +-/* +- * Copyright (c) 2010-2011 Broadcom. All rights reserved. +- * +- * This program is free software; you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation; either version 2 of the License, or +- * (at your option) any later version. +- * +- * This program is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with this program; if not, write to the Free Software +- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +- */ +- +-/*============================================================================= +-VideoCore OS Abstraction Layer - generic thread local storage +-=============================================================================*/ +- +-#ifndef VCOS_GENERIC_TLS_H +-#define VCOS_GENERIC_TLS_H +- +-#ifdef __cplusplus +-extern "C" { +-#endif +- +-#include "interface/vcos/vcos_types.h" +- +-/** +- * \file +- * +- * Do an emulation of Thread Local Storage. The platform needs to +- * provide a way to set and get a per-thread pointer which is +- * where the TLS data itself is stored. +- * +- * +- * Each thread that wants to join in this scheme needs to call +- * vcos_tls_thread_register(). +- * +- * The platform needs to support the macros/functions +- * _vcos_tls_thread_ptr_set() and _vcos_tls_thread_ptr_get(). +- */ +- +-#ifndef VCOS_WANT_TLS_EMULATION +-#error Should not be included unless TLS emulation is defined +-#endif +- +-/** Number of slots to reserve per thread. This results in an overhead +- * of this many words per thread. +- */ +-#define VCOS_TLS_MAX_SLOTS 4 +- +-/** TLS key. Allocating one of these reserves the client one of the +- * available slots. +- */ +-typedef VCOS_UNSIGNED VCOS_TLS_KEY_T; +- +-/** TLS per-thread structure. Each thread gets one of these +- * if TLS emulation (rather than native TLS support) is +- * being used. +- */ +-typedef struct VCOS_TLS_THREAD_T +-{ +- void *slots[VCOS_TLS_MAX_SLOTS]; +-} VCOS_TLS_THREAD_T; +- +-/* +- * Internal APIs +- */ +- +-/** Register this thread's TLS storage area. */ +-VCOSPRE_ void VCOSPOST_ vcos_tls_thread_register(VCOS_TLS_THREAD_T *); +- +-/** Create a new TLS key */ +-VCOSPRE_ VCOS_STATUS_T VCOSPOST_ vcos_generic_tls_create(VCOS_TLS_KEY_T *key); +- +-/** Delete a TLS key */ +-VCOSPRE_ void VCOSPOST_ vcos_generic_tls_delete(VCOS_TLS_KEY_T tls); +- +-/** Initialise the TLS library */ +-VCOSPRE_ VCOS_STATUS_T VCOSPOST_ vcos_tls_init(void); +- +-/** Deinitialise the TLS library */ +-VCOSPRE_ void VCOSPOST_ vcos_tls_deinit(void); +- +-#if defined(VCOS_INLINE_BODIES) +- +-#undef VCOS_ASSERT_LOGGING_DISABLE +-#define VCOS_ASSERT_LOGGING_DISABLE 1 +- +-/* +- * Implementations of public API functions +- */ +- +-/** Set the given value. Since everything is per-thread, there is no need +- * for any locking. +- */ +-VCOS_INLINE_IMPL +-VCOS_STATUS_T vcos_tls_set(VCOS_TLS_KEY_T tls, void *v) { +- VCOS_TLS_THREAD_T *tlsdata = _vcos_tls_thread_ptr_get(); +- vcos_assert(tlsdata); /* Fires if this thread has not been registered */ +- if (tlsslots[tls] = v; +- return VCOS_SUCCESS; +- } +- else +- { +- vcos_assert(0); +- return VCOS_EINVAL; +- } +-} +- +-/** Get the given value. No locking required. +- */ +-VCOS_INLINE_IMPL +-void *vcos_tls_get(VCOS_TLS_KEY_T tls) { +- VCOS_TLS_THREAD_T *tlsdata = _vcos_tls_thread_ptr_get(); +- vcos_assert(tlsdata); /* Fires if this thread has not been registered */ +- if (tlsslots[tls]; +- } +- else +- { +- vcos_assert(0); +- return NULL; +- } +-} +- +-VCOS_INLINE_IMPL +-VCOS_STATUS_T vcos_tls_create(VCOS_TLS_KEY_T *key) { +- return vcos_generic_tls_create(key); +-} +- +-VCOS_INLINE_IMPL +-void vcos_tls_delete(VCOS_TLS_KEY_T tls) { +- vcos_generic_tls_delete(tls); +-} +- +-#undef VCOS_ASSERT_LOGGING_DISABLE +-#define VCOS_ASSERT_LOGGING_DISABLE 0 +- +-#endif /* VCOS_INLINE_BODIES */ +- +-#ifdef __cplusplus +-} +-#endif +- +-#endif +- +- +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/generic/vcos_joinable_thread_from_plain.h +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vcos/generic/vcos_joinable_thread_from_plain.h 2013-07-26 19:32:07.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,214 +0,0 @@ +-/* +- * Copyright (c) 2010-2011 Broadcom. All rights reserved. +- * +- * This program is free software; you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation; either version 2 of the License, or +- * (at your option) any later version. +- * +- * This program is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with this program; if not, write to the Free Software +- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +- */ +- +-/*============================================================================= +-VideoCore OS Abstraction Layer - implementation: joinable thread from plain +-=============================================================================*/ +- +-/** \file +- * +- * Header file for platforms creating the joinable thread from a lowlevel +- * thread. +- * +- * In addition to the actual thread, the following are also created: +- * +- * - a semaphore to wait on when joining the thread +- * - a semaphore to support counted suspend/resume (used by event group) +- * - a per-thread timer (used by event group, but could be removed) +- */ +- +-#ifndef VCOS_JOINABLE_THREAD_FROM_PLAIN_H +-#define VCOS_JOINABLE_THREAD_FROM_PLAIN_H +- +-#ifdef __cplusplus +-extern "C" { +-#endif +- +-#include "interface/vcos/vcos_semaphore.h" +-#include "interface/vcos/vcos_lowlevel_thread.h" +-#include "interface/vcos/vcos_timer.h" +- +-#ifdef VCOS_WANT_TLS_EMULATION +-#include "interface/vcos/generic/vcos_generic_tls.h" +-#endif +- +-#define VCOS_THREAD_MAGIC 0x56436a74 +- +-#define VCOS_THREAD_VALID(t) (t->magic == VCOS_THREAD_MAGIC) +-#define VCOS_HAVE_THREAD_AT_EXIT 1 +- +-/** Thread attribute structure. Clients should not manipulate this directly, but +- * should instead use the provided functions. +- */ +-typedef struct VCOS_THREAD_ATTR_T +-{ +- void *ta_stackaddr; +- VCOS_UNSIGNED ta_stacksz; +- VCOS_UNSIGNED ta_priority; +- VCOS_UNSIGNED ta_affinity; +- VCOS_UNSIGNED ta_timeslice; +- VCOS_UNSIGNED legacy; +- VCOS_UNSIGNED ta_autostart; +-} VCOS_THREAD_ATTR_T; +- +-/** Each thread gets a timer, which is for internal VCOS use. +- */ +-typedef struct _VCOS_THREAD_TIMER_T +-{ +- VCOS_TIMER_T timer; +- void (*pfn)(void *); +- void *cxt; +-} _VCOS_THREAD_TIMER_T; +- +-typedef void (*VCOS_THREAD_EXIT_HANDLER_T)(void *); +-/** Called at thread exit. +- */ +-typedef struct VCOS_THREAD_EXIT_T +-{ +- VCOS_THREAD_EXIT_HANDLER_T pfn; +- void *cxt; +-} VCOS_THREAD_EXIT_T; +-#define VCOS_MAX_EXIT_HANDLERS 8 +- +-/* The name field isn't used for anything, so we can just copy the +- * the pointer. Nucleus makes its own copy. +- */ +-typedef const char * VCOS_LLTHREAD_T_NAME; +-#define _VCOS_LLTHREAD_NAME(dst,src) (dst)=(src) +- +-/* +- * Simulated TLS support +- */ +- +- +-/** Thread structure. +- * +- * \warning Do not access the members of this structure directly! +- */ +-typedef struct VCOS_THREAD_T +-{ +- VCOS_LLTHREAD_T thread; /**< The underlying thread */ +- char name[16]; /**< The name */ +- unsigned int magic; /**< For debug */ +- void *exit_data; /**< Exit data passed out in vcos_joinable_thread_exit() */ +- void *stack; /**< Stack, if not supplied by caller */ +- VCOS_SEMAPHORE_T wait; /**< Semaphore to wait on at join */ +- VCOS_SEMAPHORE_T suspend; /**< Semaphore to wait on for counted suspend */ +- int16_t joined; /**< Joined yet? For debug. */ +- VCOS_UNSIGNED legacy; /**< Use (argc,argv) for entry point arguments */ +- void *(*entry)(void*); /**< Entry point */ +- void *arg; /**< Argument passed to entry point */ +- void *(*term)(void*); /**< Termination function, used by reaper */ +- void *term_arg; /**< Argument passed to termination function */ +- _VCOS_THREAD_TIMER_T _timer; /**< Internal timer, mainly for event groups */ +-#ifdef VCOS_WANT_TLS_EMULATION +- VCOS_TLS_THREAD_T _tls; /**< TLS data when native TLS not available, or NULL */ +-#endif +- /** Array of functions to call at thread exit */ +- VCOS_THREAD_EXIT_T at_exit[VCOS_MAX_EXIT_HANDLERS]; +- +- struct VCOS_THREAD_T *next; /**< For linked lists of threads */ +-} VCOS_THREAD_T; +- +-#if defined(VCOS_INLINE_BODIES) +- +-VCOS_INLINE_IMPL +-void vcos_thread_attr_setstack(VCOS_THREAD_ATTR_T *attrs, void *addr, VCOS_UNSIGNED stacksz) { +- attrs->ta_stackaddr = addr; +- attrs->ta_stacksz = stacksz; +-} +- +-VCOS_INLINE_IMPL +-void vcos_thread_attr_setstacksize(VCOS_THREAD_ATTR_T *attrs, VCOS_UNSIGNED stacksz) { +- attrs->ta_stacksz = stacksz; +-} +- +-VCOS_INLINE_IMPL +-void vcos_thread_attr_setpriority(VCOS_THREAD_ATTR_T *attrs, VCOS_UNSIGNED pri) { +- attrs->ta_priority = pri; +-} +- +-VCOS_INLINE_IMPL +-void vcos_thread_attr_setaffinity(VCOS_THREAD_ATTR_T *attrs, VCOS_UNSIGNED affinity) { +- attrs->ta_affinity = affinity; +-} +- +-VCOS_INLINE_IMPL +-void vcos_thread_attr_settimeslice(VCOS_THREAD_ATTR_T *attrs, VCOS_UNSIGNED ts) { +- attrs->ta_timeslice = ts; +-} +- +-VCOS_INLINE_IMPL +-void _vcos_thread_attr_setlegacyapi(VCOS_THREAD_ATTR_T *attrs, VCOS_UNSIGNED legacy) { +- attrs->legacy = legacy; +-} +- +-VCOS_INLINE_IMPL +-void vcos_thread_attr_setautostart(VCOS_THREAD_ATTR_T *attrs, VCOS_UNSIGNED autostart) { +- attrs->ta_autostart = autostart; +-} +- +-VCOS_INLINE_IMPL +-VCOS_THREAD_T *vcos_thread_current(void) { +- VCOS_THREAD_T *ret = (VCOS_THREAD_T*)vcos_llthread_current(); +- /*If we're called from a non-vcos thread, this assert will fail. +- *XXX FIXME why is this commented out? +- *vcos_assert(ret->magic == VCOS_THREAD_MAGIC); +- */ +- return ret; +-} +- +-VCOS_INLINE_IMPL +-int vcos_thread_running(VCOS_THREAD_T *thread) { +- return vcos_llthread_running(&thread->thread); +-} +- +-VCOS_INLINE_IMPL +-void vcos_thread_resume(VCOS_THREAD_T *thread) { +- vcos_llthread_resume(&thread->thread); +-} +- +-#endif /* VCOS_INLINE_BODIES */ +- +-/** +- * \brief Create a VCOS_THREAD_T for the current thread. This is so we can have +- * VCOS_THREAD_Ts even for threads not originally created by VCOS (eg the +- * thread that calls vcos_init) +- */ +-extern VCOS_STATUS_T _vcos_thread_create_attach(VCOS_THREAD_T *thread, +- const char *name); +- +-/** +- * \brief Deletes the VCOS_THREAD_T, but does not wait for the underlying +- * thread to exit. This will cleanup everything created by +- * _vcos_thread_create_attach +- */ +-extern void _vcos_thread_delete(VCOS_THREAD_T *thread); +- +-/** Register a function to be called when the current thread exits. +- */ +-extern VCOS_STATUS_T vcos_thread_at_exit(void (*pfn)(void*), void *cxt); +- +-/** Deregister a previously registered at-exit function. +- */ +-extern void vcos_thread_deregister_at_exit(void (*pfn)(void*), void *cxt); +- +-#ifdef __cplusplus +-} +-#endif +-#endif /* VCOS_JOINABLE_THREAD_FROM_PLAIN_H */ +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/generic/vcos_latch_from_sem.h +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vcos/generic/vcos_latch_from_sem.h 2013-07-26 19:32:07.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,59 +0,0 @@ +-/* +- * Copyright (c) 2010-2011 Broadcom. All rights reserved. +- * +- * This program is free software; you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation; either version 2 of the License, or +- * (at your option) any later version. +- * +- * This program is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with this program; if not, write to the Free Software +- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +- */ +- +-/*============================================================================= +-VideoCore OS Abstraction Layer - Construct a latch from a semaphore +-=============================================================================*/ +- +-/** FIXME: rename to vcos_mutex_from_sem.c +- */ +- +-typedef struct VCOS_MUTEX_T { +- VCOS_SEMAPHORE_T sem; +- struct VCOS_THREAD_T *owner; +-} VCOS_MUTEX_T; +- +-extern VCOS_STATUS_T vcos_generic_mutex_create(VCOS_MUTEX_T *latch, const char *name); +-extern void vcos_generic_mutex_delete(VCOS_MUTEX_T *latch); +-extern VCOS_STATUS_T vcos_generic_mutex_lock(VCOS_MUTEX_T *latch); +-extern void vcos_generic_mutex_unlock(VCOS_MUTEX_T *latch); +- +-#if defined(VCOS_INLINE_BODIES) +- +-VCOS_INLINE_IMPL +-VCOS_STATUS_T vcos_mutex_create(VCOS_MUTEX_T *latch, const char *name) { +- return vcos_generic_mutex_create(latch,name); +-} +- +-VCOS_INLINE_IMPL +-void vcos_mutex_delete(VCOS_MUTEX_T *latch) { +- vcos_generic_mutex_delete(latch); +-} +- +-VCOS_INLINE_IMPL +-VCOS_STATUS_T vcos_mutex_lock(VCOS_MUTEX_T *latch) { +- return vcos_generic_mutex_lock(latch); +-} +- +-VCOS_INLINE_IMPL +-void vcos_mutex_unlock(VCOS_MUTEX_T *latch) { +- vcos_generic_mutex_unlock(latch); +-} +- +-#endif /* VCOS_INLINE_BODIES */ +- +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/generic/vcos_logcat.c +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vcos/generic/vcos_logcat.c 2013-07-26 19:32:07.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,560 +0,0 @@ +-/* +- * Copyright (c) 2010-2011 Broadcom. All rights reserved. +- * +- * This program is free software; you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation; either version 2 of the License, or +- * (at your option) any later version. +- * +- * This program is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with this program; if not, write to the Free Software +- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +- */ +- +-/*============================================================================= +-Categorized logging for VCOS - a generic implementation. +-=============================================================================*/ +- +-#include "interface/vcos/vcos.h" +-#include "interface/vcos/vcos_ctype.h" +-#include "interface/vcos/vcos_string.h" +- +-static VCOS_MUTEX_T lock; +-static int warned_loglevel; /* only warn about invalid log level once */ +-static VCOS_VLOG_IMPL_FUNC_T vcos_vlog_impl_func = vcos_vlog_default_impl; +- +-#define VCOS_LOG_CATEGORY (&dflt_log_category) +-static VCOS_LOG_CAT_T dflt_log_category; +-VCOS_LOG_CAT_T *vcos_logging_categories = NULL; +-static int inited; +- +-#if VCOS_HAVE_CMD +- +-/* +- * For kernel or videocore purposes, we generally want the log command. For +- * user-space apps, they might want to provide their own log command, so we +- * don't include the built in on. +- * +- * So pthreads/vcos_platform.h defines VCOS_WANT_LOG_CMD to be 0. It is +- * undefined elsewhere. +- */ +- +-# if !defined( VCOS_WANT_LOG_CMD ) +-# define VCOS_WANT_LOG_CMD 1 +-# endif +-#else +-# define VCOS_WANT_LOG_CMD 0 +-#endif +- +-#if VCOS_WANT_LOG_CMD +- +-/***************************************************************************** +-* +-* Does a vcos_assert(0), which is useful to test logging. +-* +-*****************************************************************************/ +- +-VCOS_STATUS_T vcos_log_assert_cmd( VCOS_CMD_PARAM_T *param ) +-{ +- (void)param; +- +-#if defined( NDEBUG ) && !defined( VCOS_RELEASE_ASSERTS ) +- vcos_log_error( "vcos_asserts have been compiled out" ); +- vcos_cmd_printf( param, "vcos_asserts have been compiled out - did a vcos_log_error instead\n" ); +-#else +- vcos_assert(0); +- vcos_cmd_printf( param, "Executed vcos_assert(0)\n" ); +-#endif +- +- return VCOS_SUCCESS; +-} +- +-/***************************************************************************** +-* +-* Sets a vcos logging level +-* +-*****************************************************************************/ +- +-VCOS_STATUS_T vcos_log_set_cmd( VCOS_CMD_PARAM_T *param ) +-{ +- VCOS_LOG_CAT_T *cat; +- char *name; +- char *levelStr; +- VCOS_LOG_LEVEL_T level; +- VCOS_STATUS_T status; +- +- if ( param->argc != 3 ) +- { +- vcos_cmd_usage( param ); +- return VCOS_EINVAL; +- } +- +- name = param->argv[1]; +- levelStr = param->argv[2]; +- +- if ( vcos_string_to_log_level( levelStr, &level ) != VCOS_SUCCESS ) +- { +- vcos_cmd_printf( param, "Unrecognized logging level: '%s'\n", levelStr ); +- return VCOS_EINVAL; +- } +- +- vcos_mutex_lock(&lock); +- +- status = VCOS_SUCCESS; +- for ( cat = vcos_logging_categories; cat != NULL; cat = cat->next ) +- { +- if ( vcos_strcmp( name, cat->name ) == 0 ) +- { +- cat->level = level; +- vcos_cmd_printf( param, "Category %s level set to %s\n", name, levelStr ); +- break; +- } +- } +- if ( cat == NULL ) +- { +- vcos_cmd_printf( param, "Unrecognized category: '%s'\n", name ); +- status = VCOS_ENOENT; +- } +- +- vcos_mutex_unlock(&lock); +- +- return status; +-} +- +-/***************************************************************************** +-* +-* Prints out the current settings for a given category (or all cvategories) +-* +-*****************************************************************************/ +- +-VCOS_STATUS_T vcos_log_status_cmd( VCOS_CMD_PARAM_T *param ) +-{ +- VCOS_LOG_CAT_T *cat; +- VCOS_STATUS_T status; +- +- vcos_mutex_lock(&lock); +- +- if ( param->argc == 1) +- { +- int nw; +- int nameWidth = 0; +- +- /* Print information about all of the categories. */ +- +- for ( cat = vcos_logging_categories; cat != NULL; cat = cat->next ) +- { +- nw = (int)strlen( cat->name ); +- +- if ( nw > nameWidth ) +- { +- nameWidth = nw; +- } +- } +- +- for ( cat = vcos_logging_categories; cat != NULL; cat = cat->next ) +- { +- vcos_cmd_printf( param, "%-*s - %s\n", nameWidth, cat->name, vcos_log_level_to_string( cat->level )); +- } +- } +- else +- { +- /* Print information about a particular category */ +- +- for ( cat = vcos_logging_categories; cat != NULL; cat = cat->next ) +- { +- if ( vcos_strcmp( cat->name, param->argv[1] ) == 0 ) +- { +- vcos_cmd_printf( param, "%s - %s\n", cat->name, vcos_log_level_to_string( cat->level )); +- break; +- } +- } +- if ( cat == NULL ) +- { +- vcos_cmd_printf( param, "Unrecognized logging category: '%s'\n", param->argv[1] ); +- status = VCOS_ENOENT; +- goto out; +- } +- } +- +- status = VCOS_SUCCESS; +-out: +- vcos_mutex_unlock(&lock); +- +- return status; +-} +- +-/***************************************************************************** +-* +-* Prints out the current settings for a given category (or all cvategories) +-* +-*****************************************************************************/ +- +-VCOS_STATUS_T vcos_log_test_cmd( VCOS_CMD_PARAM_T *param ) +-{ +- if ( param->argc == 1 ) +- { +- static int seq_num = 100; +- +- /* No additional arguments - generate a message with an incrementing number */ +- +- vcos_log_error( "Test message %d", seq_num ); +- +- seq_num++; +- vcos_cmd_printf( param, "Logged 'Test message %d'\n", seq_num ); +- } +- else +- { +- int arg_idx; +- +- /* Arguments supplied - log these */ +- +- for ( arg_idx = 0; arg_idx < param->argc; arg_idx++ ) +- { +- vcos_log_error( "argv[%d] = '%s'", arg_idx, param->argv[arg_idx] ); +- } +- vcos_cmd_printf( param, "Logged %d line(s) of test data\n", param->argc ); +- } +- return VCOS_SUCCESS; +-} +- +-/***************************************************************************** +-* +-* Internal commands +-* +-*****************************************************************************/ +- +-static VCOS_CMD_T log_cmd_entry[] = +-{ +- { "assert", "", vcos_log_assert_cmd, NULL, "Does a vcos_assert(0) to test logging" }, +- { "set", "category level", vcos_log_set_cmd, NULL, "Sets the vcos logging level for a category" }, +- { "status", "[category]", vcos_log_status_cmd, NULL, "Prints the vcos log status for a (or all) categories" }, +- { "test", "[arbitrary text]", vcos_log_test_cmd, NULL, "Does a vcos_log to test logging" }, +- +- { NULL, NULL, NULL, NULL, NULL } +-}; +- +-static VCOS_CMD_T cmd_log = +- { "log", "command [args]", NULL, log_cmd_entry, "Commands related to vcos logging" }; +- +-#endif +- +-void vcos_logging_init(void) +-{ +- if (inited) +- { +- /* FIXME: should print a warning or something here */ +- return; +- } +- vcos_mutex_create(&lock, "vcos_log"); +- +- vcos_log_platform_init(); +- +- vcos_log_register("default", &dflt_log_category); +- +-#if VCOS_WANT_LOG_CMD +- vcos_cmd_register( &cmd_log ); +-#endif +- +- vcos_assert(!inited); +- inited = 1; +-} +- +-/** Read an alphanumeric token, returning True if we succeeded. +- */ +- +-static int read_tok(char *tok, size_t toklen, const char **pstr, char sep) +-{ +- const char *str = *pstr; +- size_t n = 0; +- char ch; +- +- /* skip past any whitespace */ +- while (str[0] && isspace((int)(str[0]))) +- str++; +- +- while ((ch = *str) != '\0' && +- ch != sep && +- (isalnum((int)ch) || (ch == '_')) && +- n != toklen-1) +- { +- tok[n++] = ch; +- str++; +- } +- +- /* did it work out? */ +- if (ch == '\0' || ch == sep) +- { +- if (ch) str++; /* move to next token if not at end */ +- /* yes */ +- tok[n] = '\0'; +- *pstr = str; +- return 1; +- } +- else +- { +- /* no */ +- return 0; +- } +-} +- +-const char *vcos_log_level_to_string( VCOS_LOG_LEVEL_T level ) +-{ +- switch (level) +- { +- case VCOS_LOG_UNINITIALIZED: return "uninit"; +- case VCOS_LOG_NEVER: return "never"; +- case VCOS_LOG_ERROR: return "error"; +- case VCOS_LOG_WARN: return "warn"; +- case VCOS_LOG_INFO: return "info"; +- case VCOS_LOG_TRACE: return "trace"; +- } +- return "???"; +-} +- +-VCOS_STATUS_T vcos_string_to_log_level( const char *str, VCOS_LOG_LEVEL_T *level ) +-{ +- if (strcmp(str,"error") == 0) +- *level = VCOS_LOG_ERROR; +- else if (strcmp(str,"never") == 0) +- *level = VCOS_LOG_NEVER; +- else if (strcmp(str,"warn") == 0) +- *level = VCOS_LOG_WARN; +- else if (strcmp(str,"warning") == 0) +- *level = VCOS_LOG_WARN; +- else if (strcmp(str,"info") == 0) +- *level = VCOS_LOG_INFO; +- else if (strcmp(str,"trace") == 0) +- *level = VCOS_LOG_TRACE; +- else +- return VCOS_EINVAL; +- +- return VCOS_SUCCESS; +-} +- +-static int read_level(VCOS_LOG_LEVEL_T *level, const char **pstr, char sep) +-{ +- char buf[16]; +- int ret = 1; +- if (read_tok(buf,sizeof(buf),pstr,sep)) +- { +- if (vcos_string_to_log_level(buf,level) != VCOS_SUCCESS) +- { +- vcos_log("Invalid trace level '%s'\n", buf); +- ret = 0; +- } +- } +- else +- { +- ret = 0; +- } +- return ret; +-} +- +-void vcos_log_register(const char *name, VCOS_LOG_CAT_T *category) +-{ +- const char *env; +- VCOS_LOG_CAT_T *i; +- +- category->name = name; +- if ( category->level == VCOS_LOG_UNINITIALIZED ) +- { +- category->level = VCOS_LOG_ERROR; +- } +- category->flags.want_prefix = (category != &dflt_log_category ); +- +- vcos_mutex_lock(&lock); +- +- /* is it already registered? */ +- for (i = vcos_logging_categories; i ; i = i->next ) +- { +- if (i == category) +- { +- i->refcount++; +- break; +- } +- } +- +- if (!i) +- { +- /* not yet registered */ +- category->next = vcos_logging_categories; +- vcos_logging_categories = category; +- category->refcount++; +- +- vcos_log_platform_register(category); +- } +- +- vcos_mutex_unlock(&lock); +- +- /* Check to see if this log level has been enabled. Look for +- * (,)* +- * +- * VC_LOGLEVEL=ilcs:info,vchiq:warn +- */ +- +- env = _VCOS_LOG_LEVEL(); +- if (env) +- { +- do +- { +- char env_name[64]; +- VCOS_LOG_LEVEL_T level; +- if (read_tok(env_name, sizeof(env_name), &env, ':') && +- read_level(&level, &env, ',')) +- { +- if (strcmp(env_name, name) == 0) +- { +- category->level = level; +- break; +- } +- } +- else +- { +- if (!warned_loglevel) +- { +- vcos_log("VC_LOGLEVEL format invalid at %s\n", env); +- warned_loglevel = 1; +- } +- return; +- } +- } while (env[0] != '\0'); +- } +- +- vcos_log_info( "Registered log category '%s' with level %s", +- category->name, +- vcos_log_level_to_string( category->level )); +-} +- +-void vcos_log_unregister(VCOS_LOG_CAT_T *category) +-{ +- VCOS_LOG_CAT_T **pcat; +- vcos_mutex_lock(&lock); +- category->refcount--; +- if (category->refcount == 0) +- { +- pcat = &vcos_logging_categories; +- while (*pcat != category) +- { +- if (!*pcat) +- break; /* possibly deregistered twice? */ +- if ((*pcat)->next == NULL) +- { +- vcos_assert(0); /* already removed! */ +- vcos_mutex_unlock(&lock); +- return; +- } +- pcat = &(*pcat)->next; +- } +- if (*pcat) +- *pcat = category->next; +- +- vcos_log_platform_unregister(category); +- } +- vcos_mutex_unlock(&lock); +-} +- +-VCOSPRE_ const VCOS_LOG_CAT_T * VCOSPOST_ vcos_log_get_default_category(void) +-{ +- return &dflt_log_category; +-} +- +-void vcos_set_log_options(const char *opt) +-{ +- (void)opt; +-} +- +-void vcos_log_dump_mem_impl( const VCOS_LOG_CAT_T *cat, +- const char *label, +- uint32_t addr, +- const void *voidMem, +- size_t numBytes ) +-{ +- const uint8_t *mem = (const uint8_t *)voidMem; +- size_t offset; +- char lineBuf[ 100 ]; +- char *s; +- +- while ( numBytes > 0 ) +- { +- s = lineBuf; +- +- for ( offset = 0; offset < 16; offset++ ) +- { +- if ( offset < numBytes ) +- { +- s += vcos_snprintf( s, 4, "%02x ", mem[ offset ]); +- } +- else +- { +- s += vcos_snprintf( s, 4, " " ); +- } +- } +- +- for ( offset = 0; offset < 16; offset++ ) +- { +- if ( offset < numBytes ) +- { +- uint8_t ch = mem[ offset ]; +- +- if (( ch < ' ' ) || ( ch > '~' )) +- { +- ch = '.'; +- } +- *s++ = (char)ch; +- } +- } +- *s++ = '\0'; +- +- if (( label != NULL ) && ( *label != '\0' )) +- { +- vcos_log_impl( cat, VCOS_LOG_INFO, "%s: %08x: %s", label, addr, lineBuf ); +- } +- else +- { +- vcos_log_impl( cat, VCOS_LOG_INFO, "%08x: %s", addr, lineBuf ); +- } +- +- addr += 16; +- mem += 16; +- if ( numBytes > 16 ) +- { +- numBytes -= 16; +- } +- else +- { +- numBytes = 0; +- } +- } +- +-} +- +-void vcos_log_impl(const VCOS_LOG_CAT_T *cat, VCOS_LOG_LEVEL_T _level, const char *fmt, ...) +-{ +- va_list ap; +- va_start(ap,fmt); +- vcos_vlog_impl( cat, _level, fmt, ap ); +- va_end(ap); +-} +- +-void vcos_vlog_impl(const VCOS_LOG_CAT_T *cat, VCOS_LOG_LEVEL_T _level, const char *fmt, va_list args) +-{ +- vcos_vlog_impl_func( cat, _level, fmt, args ); +-} +- +-void vcos_set_vlog_impl( VCOS_VLOG_IMPL_FUNC_T vlog_impl_func ) +-{ +- if ( vlog_impl_func == NULL ) +- { +- vcos_vlog_impl_func = vcos_vlog_default_impl; +- } +- else +- { +- vcos_vlog_impl_func = vlog_impl_func; +- } +-} +- +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/generic/vcos_mem_from_malloc.c +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vcos/generic/vcos_mem_from_malloc.c 2013-07-26 19:32:07.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,84 +0,0 @@ +-/* +- * Copyright (c) 2010-2011 Broadcom. All rights reserved. +- * +- * This program is free software; you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation; either version 2 of the License, or +- * (at your option) any later version. +- * +- * This program is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with this program; if not, write to the Free Software +- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +- */ +- +-/*============================================================================= +-VideoCore OS Abstraction Layer - memory alloc implementation +-=============================================================================*/ +- +-#include "interface/vcos/vcos.h" +- +-#ifndef _vcos_platform_malloc +-#include +-#define _vcos_platform_malloc malloc +-#define _vcos_platform_free free +-#endif +- +-typedef struct malloc_header_s { +- uint32_t guardword; +- uint32_t size; +- const char *description; +- void *ptr; +-} MALLOC_HEADER_T; +- +- +-#define MIN_ALIGN sizeof(MALLOC_HEADER_T) +- +-#define GUARDWORDHEAP 0xa55a5aa5 +- +-void *vcos_generic_mem_alloc_aligned(VCOS_UNSIGNED size, VCOS_UNSIGNED align, const char *desc) +-{ +- int local_align = align == 0 ? 1 : align; +- int required_size = size + local_align + sizeof(MALLOC_HEADER_T); +- void *ptr = _vcos_platform_malloc(required_size); +- void *ret = (void *)VCOS_ALIGN_UP(((char *)ptr)+sizeof(MALLOC_HEADER_T), local_align); +- MALLOC_HEADER_T *h = ((MALLOC_HEADER_T *)ret)-1; +- +- h->size = size; +- h->description = desc; +- h->guardword = GUARDWORDHEAP; +- h->ptr = ptr; +- +- return ret; +-} +- +-void *vcos_generic_mem_alloc(VCOS_UNSIGNED size, const char *desc) +-{ +- return vcos_generic_mem_alloc_aligned(size,MIN_ALIGN,desc); +-} +- +-void *vcos_generic_mem_calloc(VCOS_UNSIGNED count, VCOS_UNSIGNED sz, const char *desc) +-{ +- uint32_t size = count*sz; +- void *ptr = vcos_generic_mem_alloc_aligned(size,MIN_ALIGN,desc); +- if (ptr) +- { +- memset(ptr, 0, size); +- } +- return ptr; +-} +- +-void vcos_generic_mem_free(void *ptr) +-{ +- MALLOC_HEADER_T *h; +- if (! ptr) return; +- +- h = ((MALLOC_HEADER_T *)ptr)-1; +- vcos_assert(h->guardword == GUARDWORDHEAP); +- _vcos_platform_free(h->ptr); +-} +- +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/generic/vcos_mem_from_malloc.h +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vcos/generic/vcos_mem_from_malloc.h 2013-07-26 19:32:07.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,65 +0,0 @@ +-/* +- * Copyright (c) 2010-2011 Broadcom. All rights reserved. +- * +- * This program is free software; you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation; either version 2 of the License, or +- * (at your option) any later version. +- * +- * This program is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with this program; if not, write to the Free Software +- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +- */ +- +-/*============================================================================= +-Create the vcos_malloc API from the regular system malloc/free +-=============================================================================*/ +- +-/** +- * \file +- * +- * Create the vcos malloc API from a regular system malloc/free library. +- * +- * The API lets callers specify an alignment. +- * +- * Under VideoCore this is not needed, as we can simply use the rtos_malloc routines. +- * But on host platforms that won't be the case. +- * +- */ +- +-VCOSPRE_ void * VCOSPOST_ vcos_generic_mem_alloc(VCOS_UNSIGNED sz, const char *desc); +-VCOSPRE_ void * VCOSPOST_ vcos_generic_mem_calloc(VCOS_UNSIGNED count, VCOS_UNSIGNED sz, const char *descr); +-VCOSPRE_ void VCOSPOST_ vcos_generic_mem_free(void *ptr); +-VCOSPRE_ void * VCOSPOST_ vcos_generic_mem_alloc_aligned(VCOS_UNSIGNED sz, VCOS_UNSIGNED align, const char *desc); +- +-#ifdef VCOS_INLINE_BODIES +- +-VCOS_INLINE_IMPL +-void *vcos_malloc(VCOS_UNSIGNED size, const char *description) { +- return vcos_generic_mem_alloc(size, description); +-} +- +-VCOS_INLINE_IMPL +-void *vcos_calloc(VCOS_UNSIGNED num, VCOS_UNSIGNED size, const char *description) { +- return vcos_generic_mem_calloc(num, size, description); +-} +- +-VCOS_INLINE_IMPL +-void vcos_free(void *ptr) { +- vcos_generic_mem_free(ptr); +-} +- +-VCOS_INLINE_IMPL +-void * vcos_malloc_aligned(VCOS_UNSIGNED size, VCOS_UNSIGNED align, const char *description) { +- return vcos_generic_mem_alloc_aligned(size, align, description); +-} +- +- +-#endif /* VCOS_INLINE_BODIES */ +- +- +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/generic/vcos_mutexes_are_reentrant.h +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vcos/generic/vcos_mutexes_are_reentrant.h 2013-07-26 19:32:07.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,79 +0,0 @@ +-/* +- * Copyright (c) 2010-2011 Broadcom. All rights reserved. +- * +- * This program is free software; you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation; either version 2 of the License, or +- * (at your option) any later version. +- * +- * This program is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with this program; if not, write to the Free Software +- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +- */ +- +-/*============================================================================= +-VideoCore OS Abstraction Layer - reentrant mutexes mapped directly to regular ones +-=============================================================================*/ +- +-#ifndef VCOS_GENERIC_REENTRANT_MUTEX_H +-#define VCOS_GENERIC_REENTRANT_MUTEX_H +- +-#ifdef __cplusplus +-extern "C" { +-#endif +- +-#include "interface/vcos/vcos_types.h" +-#include "interface/vcos/vcos_mutex.h" +- +-/** +- * \file +- * +- * Reentrant Mutexes directly using the native re-entrant mutex. +- * +- */ +- +-typedef VCOS_MUTEX_T VCOS_REENTRANT_MUTEX_T; +- +-/* Inline forwarding functions */ +- +-#if defined(VCOS_INLINE_BODIES) +- +-VCOS_INLINE_IMPL +-VCOS_STATUS_T vcos_reentrant_mutex_create(VCOS_REENTRANT_MUTEX_T *m, const char *name) { +- return vcos_mutex_create(m,name); +-} +- +-VCOS_INLINE_IMPL +-void vcos_reentrant_mutex_delete(VCOS_REENTRANT_MUTEX_T *m) { +- vcos_mutex_delete(m); +-} +- +-VCOS_INLINE_IMPL +-void vcos_reentrant_mutex_lock(VCOS_REENTRANT_MUTEX_T *m) { +- vcos_mutex_lock(m); +-} +- +-VCOS_INLINE_IMPL +-void vcos_reentrant_mutex_unlock(VCOS_REENTRANT_MUTEX_T *m) { +- vcos_mutex_unlock(m); +-} +- +-VCOS_INLINE_IMPL +-int vcos_reentrant_mutex_is_locked(VCOS_REENTRANT_MUTEX_T *m) { +- return vcos_mutex_is_locked(m); +-} +- +-#endif +- +-#ifdef __cplusplus +-} +-#endif +-#endif +- +- +- +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/generic/vcos_thread_reaper.h +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vcos/generic/vcos_thread_reaper.h 2013-07-26 19:32:07.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,46 +0,0 @@ +-/* +- * Copyright (c) 2010-2011 Broadcom. All rights reserved. +- * +- * This program is free software; you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation; either version 2 of the License, or +- * (at your option) any later version. +- * +- * This program is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with this program; if not, write to the Free Software +- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +- */ +- +-/*============================================================================= +-VideoCore OS Abstraction Layer - thread reaping +-=============================================================================*/ +- +-#ifndef VCOS_THREAD_REAPER_H +-#define VCOS_THREAD_REAPER_H +- +-#define VCOS_HAVE_THREAD_REAPER +- +-/** Initialise the thread reaper. +- */ +-VCOS_STATUS_T vcos_thread_reaper_init(void); +- +-/** Reap a thread. Arranges for the thread to be automatically +- * joined. +- * +- * @sa vcos_thread_join(). +- * +- * @param thread the thread to terminate +- * @param on_terminated called after the thread has exited +- * @param cxt pass back to the callback +- * +- */ +-void vcos_thread_reap(VCOS_THREAD_T *thread, void (*on_terminated)(void*), void *cxt); +- +-#endif +- +- +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/linuxkernel/stdint.h +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vcos/linuxkernel/stdint.h 2013-07-26 19:32:07.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,31 +0,0 @@ +-/* +- * Copyright (c) 2010-2011 Broadcom. All rights reserved. +- * +- * This program is free software; you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation; either version 2 of the License, or +- * (at your option) any later version. +- * +- * This program is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with this program; if not, write to the Free Software +- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +- */ +- +-/*============================================================================= +-VideoCore OS fAbstraction Layer - stdint.h C standard header +-=============================================================================*/ +- +-#ifndef _VCOS_PLATFORM_LINUX_STDINT_H +-#define _VCOS_PLATFORM_LINUX_STDINT_H +- +-/* The Linux kernel does not have a so we have to provide one of +- our own. */ +- +-#include /* includes integer types */ +- +-#endif /* _VCOS_PLATFORM_LINUX_STDINT_H */ +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/linuxkernel/vcos_linuxkernel.c +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vcos/linuxkernel/vcos_linuxkernel.c 2013-07-26 19:32:07.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,627 +0,0 @@ +-/* +- * Copyright (c) 2010-2011 Broadcom. All rights reserved. +- * +- * This program is free software; you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation; either version 2 of the License, or +- * (at your option) any later version. +- * +- * This program is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with this program; if not, write to the Free Software +- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +- */ +- +-/*============================================================================= +-VideoCore OS Abstraction Layer - pthreads types +-=============================================================================*/ +- +-#define VCOS_INLINE_BODIES +-#include +-#include +-#include +-#include +-#include +-#include +- +-#if defined( CONFIG_BCM_KNLLOG_SUPPORT ) +-#include +-#endif +-#include "interface/vcos/vcos.h" +-#ifdef HAVE_VCOS_VERSION +-#include "interface/vcos/vcos_build_info.h" +-#endif +- +-VCOS_CFG_ENTRY_T vcos_cfg_dir; +-VCOS_CFG_ENTRY_T vcos_logging_cfg_dir; +-VCOS_CFG_ENTRY_T vcos_version_cfg; +- +-#ifndef VCOS_DEFAULT_STACK_SIZE +-#define VCOS_DEFAULT_STACK_SIZE 4096 +-#endif +- +-static VCOS_THREAD_ATTR_T default_attrs = { +- 0, +- VCOS_DEFAULT_STACK_SIZE, +-}; +- +-#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,36) +-static DEFINE_SEMAPHORE(lock); +-#else +-static DECLARE_MUTEX(lock); +-#endif +- +-typedef void (*LEGACY_ENTRY_FN_T)(int, void *); +- +-/** Wrapper function around the real thread function. Posts the semaphore +- * when completed. +- */ +-static int vcos_thread_wrapper(void *arg) +-{ +- void *ret; +- VCOS_THREAD_T *thread = arg; +- +- vcos_assert(thread->magic == VCOS_THREAD_MAGIC); +- +- thread->thread.thread = current; +- +- vcos_add_thread(thread); +- +-#ifdef VCOS_WANT_TLS_EMULATION +- vcos_tls_thread_register(&thread->_tls); +-#endif +- +- if (thread->legacy) +- { +- LEGACY_ENTRY_FN_T fn = (LEGACY_ENTRY_FN_T)thread->entry; +- fn(0,thread->arg); +- ret = 0; +- } +- else +- { +- ret = thread->entry(thread->arg); +- } +- +- thread->exit_data = ret; +- +- vcos_remove_thread(current); +- +- /* For join and cleanup */ +- vcos_semaphore_post(&thread->wait); +- +- return 0; +-} +- +-VCOS_STATUS_T vcos_thread_create(VCOS_THREAD_T *thread, +- const char *name, +- VCOS_THREAD_ATTR_T *attrs, +- VCOS_THREAD_ENTRY_FN_T entry, +- void *arg) +-{ +- VCOS_STATUS_T st; +- struct task_struct *kthread; +- +- memset(thread, 0, sizeof(*thread)); +- thread->magic = VCOS_THREAD_MAGIC; +- strlcpy( thread->name, name, sizeof( thread->name )); +- thread->legacy = attrs ? attrs->legacy : 0; +- thread->entry = entry; +- thread->arg = arg; +- +- if (!name) +- { +- vcos_assert(0); +- return VCOS_EINVAL; +- } +- +- st = vcos_semaphore_create(&thread->wait, NULL, 0); +- if (st != VCOS_SUCCESS) +- { +- return st; +- } +- +- st = vcos_semaphore_create(&thread->suspend, NULL, 0); +- if (st != VCOS_SUCCESS) +- { +- return st; +- } +- +- /*required for event groups */ +- vcos_timer_create(&thread->_timer.timer, thread->name, NULL, NULL); +- +- kthread = kthread_create((int (*)(void *))vcos_thread_wrapper, (void*)thread, name); +- vcos_assert(kthread != NULL); +- set_user_nice(kthread, attrs->ta_priority); +- thread->thread.thread = kthread; +- wake_up_process(kthread); +- return VCOS_SUCCESS; +-} +- +-void vcos_thread_join(VCOS_THREAD_T *thread, +- void **pData) +-{ +- vcos_assert(thread); +- vcos_assert(thread->magic == VCOS_THREAD_MAGIC); +- +- thread->joined = 1; +- +- vcos_semaphore_wait(&thread->wait); +- +- if (pData) +- { +- *pData = thread->exit_data; +- } +- +- /* Clean up */ +- if (thread->stack) +- vcos_free(thread->stack); +- +- vcos_semaphore_delete(&thread->wait); +- vcos_semaphore_delete(&thread->suspend); +- +-} +- +-uint32_t vcos_getmicrosecs( void ) +-{ +- struct timeval tv; +-/*XXX FIX ME! switch to ktime_get_ts to use MONOTONIC clock */ +- do_gettimeofday(&tv); +- return (tv.tv_sec*1000000) + tv.tv_usec; +-} +- +-VCOS_STATUS_T vcos_timer_init(void) +-{ +- return VCOS_SUCCESS; +-} +- +-static const char *log_prefix[] = +-{ +- "", /* VCOS_LOG_UNINITIALIZED */ +- "", /* VCOS_LOG_NEVER */ +- KERN_ERR, /* VCOS_LOG_ERROR */ +- KERN_WARNING, /* VCOS_LOG_WARN */ +- KERN_INFO, /* VCOS_LOG_INFO */ +- KERN_INFO /* VCOS_LOG_TRACE */ +-}; +- +-void vcos_vlog_default_impl(const VCOS_LOG_CAT_T *cat, VCOS_LOG_LEVEL_T _level, const char *fmt, va_list args) +-{ +- char *newline = strchr( fmt, '\n' ); +- const char *prefix; +- const char *real_fmt; +- +- preempt_disable(); +- { +- if ( *fmt == '<' ) +- { +- prefix = fmt; +- real_fmt= &fmt[3]; +- } +- else +- { +- prefix = log_prefix[_level]; +- real_fmt = fmt; +- } +-#if defined( CONFIG_BCM_KNLLOG_SUPPORT ) +- knllog_ventry( "vcos", real_fmt, args ); +-#endif +- printk( "%.3svcos: [%d]: ", prefix, current->pid ); +- vprintk( real_fmt, args ); +- +- if ( newline == NULL ) +- { +- printk("\n"); +- } +- } +- preempt_enable(); +-} +- +- +-const char * _vcos_log_level(void) +-{ +- return NULL; +-} +- +-/***************************************************************************** +-* +-* Displays the version information in /proc/vcos/version +-* +-*****************************************************************************/ +- +-#ifdef HAVE_VCOS_VERSION +- +-static void show_version( VCOS_CFG_BUF_T buf, void *data ) +-{ +- static const char* copyright = "Copyright (c) 2011 Broadcom"; +- +- vcos_cfg_buf_printf( buf, "Built %s %s on %s\n%s\nversion %s\n", +- vcos_get_build_date(), +- vcos_get_build_time(), +- vcos_get_build_hostname(), +- copyright, +- vcos_get_build_version() ); +-} +- +-#endif +- +-/***************************************************************************** +-* +-* Initialises vcos +-* +-*****************************************************************************/ +- +-VCOS_STATUS_T vcos_init(void) +-{ +- if ( vcos_cfg_mkdir( &vcos_cfg_dir, NULL, "vcos" ) != VCOS_SUCCESS ) +- { +- printk( KERN_ERR "%s: Unable to create vcos cfg entry\n", __func__ ); +- } +- vcos_logging_init(); +- +-#ifdef HAVE_VCOS_VERSION +- if ( vcos_cfg_create_entry( &vcos_version_cfg, &vcos_cfg_dir, "version", +- show_version, NULL, NULL ) != VCOS_SUCCESS ) +- { +- printk( KERN_ERR "%s: Unable to create vcos cfg entry 'version'\n", __func__ ); +- } +-#endif +- +- return VCOS_SUCCESS; +-} +- +-/***************************************************************************** +-* +-* Deinitializes vcos +-* +-*****************************************************************************/ +- +-void vcos_deinit(void) +-{ +-#ifdef HAVE_VCOS_VERSION +- vcos_cfg_remove_entry( &vcos_version_cfg ); +-#endif +- vcos_cfg_remove_entry( &vcos_cfg_dir ); +-} +- +-void vcos_global_lock(void) +-{ +- down(&lock); +-} +- +-void vcos_global_unlock(void) +-{ +- up(&lock); +-} +- +-/* vcos_thread_exit() doesn't really stop this thread here +- * +- * At the moment, call to do_exit() will leak task_struct for +- * current thread, so we let the vcos_thread_wrapper() do the +- * cleanup and exit job, and we return w/o actually stopping the thread. +- * +- * ToDo: Kernel v2.6.31 onwards, it is considered safe to call do_exit() +- * from kthread, the implementation of which is combined in 2 patches +- * with commit-ids "63706172" and "cdd140bd" in oss Linux kernel tree +- */ +- +-void vcos_thread_exit(void *arg) +-{ +- VCOS_THREAD_T *thread = vcos_thread_current(); +- +- vcos_assert(thread); +- vcos_assert(thread->magic == VCOS_THREAD_MAGIC); +- +- thread->exit_data = arg; +-} +- +-void vcos_thread_attr_init(VCOS_THREAD_ATTR_T *attrs) +-{ +- *attrs = default_attrs; +-} +- +-void _vcos_task_timer_set(void (*pfn)(void *), void *cxt, VCOS_UNSIGNED ms) +-{ +- VCOS_THREAD_T *self = vcos_thread_current(); +- vcos_assert(self); +- vcos_assert(self->_timer.pfn == NULL); +- +- vcos_timer_create( &self->_timer.timer, "TaskTimer", pfn, cxt ); +- vcos_timer_set(&self->_timer.timer, ms); +-} +- +-void _vcos_task_timer_cancel(void) +-{ +- VCOS_THREAD_T *self = vcos_thread_current(); +- if (self->_timer.timer.linux_timer.function) +- { +- vcos_timer_cancel(&self->_timer.timer); +- vcos_timer_delete(&self->_timer.timer); +- } +-} +- +-int vcos_vsnprintf( char *buf, size_t buflen, const char *fmt, va_list ap ) +-{ +- return vsnprintf( buf, buflen, fmt, ap ); +-} +- +-int vcos_snprintf(char *buf, size_t buflen, const char *fmt, ...) +-{ +- int ret; +- va_list ap; +- va_start(ap,fmt); +- ret = vsnprintf(buf, buflen, fmt, ap); +- va_end(ap); +- return ret; +-} +- +-int vcos_llthread_running(VCOS_LLTHREAD_T *t) { +- vcos_assert(0); /* this function only exists as a nasty hack for the video codecs! */ +- return 1; +-} +- +-static int vcos_verify_bkpts = 1; +- +-int vcos_verify_bkpts_enabled(void) +-{ +- return vcos_verify_bkpts; +-} +- +-/***************************************************************************** +-* +-* _vcos_log_platform_init is called from vcos_logging_init +-* +-*****************************************************************************/ +- +-void _vcos_log_platform_init(void) +-{ +- if ( vcos_cfg_mkdir( &vcos_logging_cfg_dir, &vcos_cfg_dir, "logging" ) != VCOS_SUCCESS ) +- { +- printk( KERN_ERR "%s: Unable to create logging cfg entry\n", __func__ ); +- } +-} +- +-/***************************************************************************** +-* +-* Called to display the contents of a logging category. +-* +-*****************************************************************************/ +- +-static void logging_show_category( VCOS_CFG_BUF_T buf, void *data ) +-{ +- VCOS_LOG_CAT_T *category = data; +- +- vcos_cfg_buf_printf( buf, "%s\n", vcos_log_level_to_string( category->level )); +-} +- +-/***************************************************************************** +-* +-* Called to parse content for a logging category. +-* +-*****************************************************************************/ +- +-static void logging_parse_category( VCOS_CFG_BUF_T buf, void *data ) +-{ +- VCOS_LOG_CAT_T *category = data; +- const char *str = vcos_cfg_buf_get_str( buf ); +- VCOS_LOG_LEVEL_T level; +- +- if ( vcos_string_to_log_level( str, &level ) == VCOS_SUCCESS ) +- { +- category->level = level; +- } +- else +- { +- printk( KERN_ERR "%s: Unrecognized logging level: '%s'\n", +- __func__, str ); +- } +-} +- +-/***************************************************************************** +-* +-* _vcos_log_platform_register is called from vcos_log_register whenever +-* a new category is registered. +-* +-*****************************************************************************/ +- +-void _vcos_log_platform_register(VCOS_LOG_CAT_T *category) +-{ +- VCOS_CFG_ENTRY_T entry; +- +- if ( vcos_cfg_create_entry( &entry, &vcos_logging_cfg_dir, category->name, +- logging_show_category, logging_parse_category, +- category ) != VCOS_SUCCESS ) +- { +- printk( KERN_ERR "%s: Unable to create cfg entry for logging category '%s'\n", +- __func__, category->name ); +- category->platform_data = NULL; +- } +- else +- { +- category->platform_data = entry; +- } +-} +- +-/***************************************************************************** +-* +-* _vcos_log_platform_unregister is called from vcos_log_unregister whenever +-* a new category is unregistered. +-* +-*****************************************************************************/ +- +-void _vcos_log_platform_unregister(VCOS_LOG_CAT_T *category) +-{ +- VCOS_CFG_ENTRY_T entry; +- +- entry = category->platform_data; +- if ( entry != NULL ) +- { +- if ( vcos_cfg_remove_entry( &entry ) != VCOS_SUCCESS ) +- { +- printk( KERN_ERR "%s: Unable to remove cfg entry for logging category '%s'\n", +- __func__, category->name ); +- } +- } +-} +- +-/***************************************************************************** +-* +-* Allocate memory. +-* +-*****************************************************************************/ +- +-void *vcos_platform_malloc( VCOS_UNSIGNED required_size ) +-{ +- if ( required_size >= ( 2 * PAGE_SIZE )) +- { +- /* For larger allocations, use vmalloc, whose underlying allocator +- * returns pages +- */ +- +- return vmalloc( required_size ); +- } +- +- /* For smaller allocation, use kmalloc */ +- +- return kmalloc( required_size, GFP_KERNEL ); +-} +- +-/***************************************************************************** +-* +-* Free previously allocated memory +-* +-*****************************************************************************/ +- +-void vcos_platform_free( void *ptr ) +-{ +- if (((unsigned long)ptr >= VMALLOC_START ) +- && ((unsigned long)ptr < VMALLOC_END )) +- { +- vfree( ptr ); +- } +- else +- { +- kfree( ptr ); +- } +-} +- +-/***************************************************************************** +-* +-* Execute a routine exactly once. +-* +-*****************************************************************************/ +- +-VCOS_STATUS_T vcos_once(VCOS_ONCE_T *once_control, +- void (*init_routine)(void)) +-{ +- /* In order to be thread-safe we need to re-test *once_control +- * inside the lock. The outer test is basically an optimization +- * so that once it is initialized we don't need to waste time +- * trying to acquire the lock. +- */ +- +- if ( *once_control == 0 ) +- { +- vcos_global_lock(); +- if ( *once_control == 0 ) +- { +- init_routine(); +- *once_control = 1; +- } +- vcos_global_unlock(); +- } +- +- return VCOS_SUCCESS; +-} +- +-/***************************************************************************** +-* +-* String duplication routine. +-* +-*****************************************************************************/ +- +-char *vcos_strdup(const char *str) +-{ +- return kstrdup(str, GFP_KERNEL); +-} +- +- +-/* Export functions for modules to use */ +-EXPORT_SYMBOL( vcos_init ); +- +-EXPORT_SYMBOL( vcos_semaphore_trywait ); +-EXPORT_SYMBOL( vcos_semaphore_post ); +-EXPORT_SYMBOL( vcos_semaphore_create ); +-EXPORT_SYMBOL( vcos_semaphore_wait ); +-EXPORT_SYMBOL( vcos_semaphore_delete ); +- +-EXPORT_SYMBOL( vcos_log_impl ); +-EXPORT_SYMBOL( vcos_vlog_impl ); +-EXPORT_SYMBOL( vcos_vlog_default_impl ); +-EXPORT_SYMBOL( vcos_log_get_default_category ); +-EXPORT_SYMBOL( vcos_log_register ); +-EXPORT_SYMBOL( vcos_log_unregister ); +-EXPORT_SYMBOL( vcos_logging_init ); +-EXPORT_SYMBOL( vcos_log_level_to_string ); +-EXPORT_SYMBOL( vcos_string_to_log_level ); +-EXPORT_SYMBOL( vcos_log_dump_mem_impl ); +- +-EXPORT_SYMBOL( vcos_event_create ); +-EXPORT_SYMBOL( vcos_event_delete ); +-EXPORT_SYMBOL( vcos_event_flags_set ); +-EXPORT_SYMBOL( vcos_event_signal ); +-EXPORT_SYMBOL( vcos_event_wait ); +-EXPORT_SYMBOL( vcos_event_try ); +- +-EXPORT_SYMBOL( vcos_getmicrosecs ); +- +-EXPORT_SYMBOL( vcos_strcasecmp ); +-EXPORT_SYMBOL( vcos_snprintf ); +-EXPORT_SYMBOL( vcos_vsnprintf ); +- +-EXPORT_SYMBOL( vcos_thread_current ); +-EXPORT_SYMBOL( vcos_thread_join ); +-EXPORT_SYMBOL( vcos_thread_create ); +-EXPORT_SYMBOL( vcos_thread_set_priority ); +-EXPORT_SYMBOL( vcos_thread_exit ); +-EXPORT_SYMBOL( vcos_once ); +- +-EXPORT_SYMBOL( vcos_thread_attr_init ); +-EXPORT_SYMBOL( vcos_thread_attr_setpriority ); +-EXPORT_SYMBOL( vcos_thread_attr_settimeslice ); +-EXPORT_SYMBOL( vcos_thread_attr_setstacksize ); +-EXPORT_SYMBOL( _vcos_thread_attr_setlegacyapi ); +- +-EXPORT_SYMBOL( vcos_event_flags_create ); +-EXPORT_SYMBOL( vcos_event_flags_delete ); +-EXPORT_SYMBOL( vcos_event_flags_get ); +- +-EXPORT_SYMBOL( vcos_sleep ); +- +-EXPORT_SYMBOL( vcos_calloc ); +-EXPORT_SYMBOL( vcos_malloc ); +-EXPORT_SYMBOL( vcos_malloc_aligned ); +-EXPORT_SYMBOL( vcos_free ); +- +-EXPORT_SYMBOL( vcos_mutex_create ); +-EXPORT_SYMBOL( vcos_mutex_delete ); +-EXPORT_SYMBOL( vcos_mutex_lock ); +-EXPORT_SYMBOL( vcos_mutex_unlock ); +-EXPORT_SYMBOL( vcos_mutex_trylock ); +- +-EXPORT_SYMBOL( vcos_timer_cancel ); +-EXPORT_SYMBOL( vcos_timer_create ); +-EXPORT_SYMBOL( vcos_timer_delete ); +-EXPORT_SYMBOL( vcos_timer_set ); +- +-EXPORT_SYMBOL( vcos_atomic_flags_create ); +-EXPORT_SYMBOL( vcos_atomic_flags_delete ); +-EXPORT_SYMBOL( vcos_atomic_flags_or ); +-EXPORT_SYMBOL( vcos_atomic_flags_get_and_clear ); +- +-EXPORT_SYMBOL( vcos_verify_bkpts_enabled ); +- +-EXPORT_SYMBOL( vcos_strdup ); +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/linuxkernel/vcos_linuxkernel_cfg.c +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vcos/linuxkernel/vcos_linuxkernel_cfg.c 2013-07-26 19:32:00.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,332 +0,0 @@ +-/***************************************************************************** +-* Copyright 2009 - 2010 Broadcom Corporation. All rights reserved. +-* +-* Unless you and Broadcom execute a separate written software license +-* agreement governing use of this software, this software is licensed to you +-* under the terms of the GNU General Public License version 2, available at +-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). +-* +-* Notwithstanding the above, under no circumstances may you combine this +-* software in any way with any other Broadcom software provided under a +-* license other than the GPL, without Broadcom's express prior written +-* consent. +-*****************************************************************************/ +- +-#include "interface/vcos/vcos.h" +-#include +-#include +-#include +-#include +- +-struct opaque_vcos_cfg_buf_t +-{ +- struct seq_file *seq; +- char *charBuf; +-}; +- +-struct opaque_vcos_cfg_entry_t +-{ +- struct proc_dir_entry *pde; +- struct proc_dir_entry *parent_pde; +- VCOS_CFG_SHOW_FPTR showFunc; +- VCOS_CFG_PARSE_FPTR parseFunc; +- void *data; +- const char *name; +-}; +- +-/***************************************************************************** +-* +-* cfg_proc_show +-* +-*****************************************************************************/ +- +-static int cfg_proc_show( struct seq_file *s, void *v ) +-{ +- VCOS_CFG_ENTRY_T entry; +- struct opaque_vcos_cfg_buf_t buf; +- +- entry = s->private; +- +- if ( entry->showFunc ) +- { +- memset( &buf, 0, sizeof( buf )); +- buf.seq = s; +- +- entry->showFunc( &buf, entry->data ); +- } +- +- return 0; +-} +- +-/***************************************************************************** +-* +-* cfg_proc_write +-* +-*****************************************************************************/ +- +-static ssize_t cfg_proc_write( struct file *file, const char __user *buffer, size_t count, loff_t *ppos) +-{ +- VCOS_CFG_ENTRY_T entry = PDE(file->f_path.dentry->d_inode)->data; +- char *charBuf; +- struct opaque_vcos_cfg_buf_t buf; +- size_t len; +- +- if ( entry->parseFunc != NULL ) +- { +- /* The number 4000 is rather arbitrary. It just needs to be bigger than any input +- * string we expect to use. +- */ +- +- len = count; +- if ( count > 4000 ) +- { +- len = 4000; +- } +- +- /* Allocate a kernel buffer to contain the string being written. */ +- +- charBuf = kmalloc( len + 1, GFP_KERNEL ); +- if ( copy_from_user( charBuf, buffer, len )) +- { +- kfree( charBuf ); +- return -EFAULT; +- } +- +- /* echo puts a trailing newline in the buffer - strip it out. */ +- +- if (( len > 0 ) && ( charBuf[ len - 1 ] == '\n' )) +- { +- len--; +- } +- charBuf[len] = '\0'; +- +- memset( &buf, 0, sizeof( buf )); +- buf.charBuf = charBuf; +- +- entry->parseFunc( &buf, entry->data ); +- kfree( charBuf ); +- } +- return count; +-} +- +-/***************************************************************************** +-* +-* cfg_proc_open +-* +-*****************************************************************************/ +- +-static int cfg_proc_open( struct inode *inode, struct file *file ) +-{ +- return single_open( file, cfg_proc_show, PDE(inode)->data ); +-} +- +-static const struct file_operations cfg_proc_fops = +-{ +- .open = cfg_proc_open, +- .read = seq_read, +- .llseek = seq_lseek, +- .release = single_release, +- .write = cfg_proc_write, +-}; +- +-/***************************************************************************** +-* +-* vcos_cfg_mkdir +-* +-*****************************************************************************/ +- +-VCOS_STATUS_T vcos_cfg_mkdir( VCOS_CFG_ENTRY_T *entryp, +- VCOS_CFG_ENTRY_T *parent, +- const char *dirName ) +-{ +- VCOS_CFG_ENTRY_T entry; +- +- if (( entry = kzalloc( sizeof( *entry ), GFP_KERNEL )) == NULL ) +- { +- return VCOS_ENOMEM; +- } +- +- if ( parent == NULL ) +- { +- entry->pde = proc_mkdir( dirName, NULL ); +- } +- else +- { +- entry->pde = proc_mkdir( dirName, (*parent)->pde ); +- entry->parent_pde = (*parent)->pde; +- } +- if ( entry->pde == NULL ) +- { +- kfree( entry ); +- return VCOS_ENOMEM; +- } +- +- entry->name = dirName; +- +- *entryp = entry; +- return VCOS_SUCCESS; +-} +- +-/***************************************************************************** +-* +-* vcos_cfg_create_entry +-* +-*****************************************************************************/ +- +-VCOS_STATUS_T vcos_cfg_create_entry( VCOS_CFG_ENTRY_T *entryp, +- VCOS_CFG_ENTRY_T *parent, +- const char *entryName, +- VCOS_CFG_SHOW_FPTR showFunc, +- VCOS_CFG_PARSE_FPTR parseFunc, +- void *data ) +-{ +- VCOS_CFG_ENTRY_T entry; +- mode_t mode; +- +- *entryp = NULL; +- +- if (( entry = kzalloc( sizeof( *entry ), GFP_KERNEL )) == NULL ) +- { +- return VCOS_ENOMEM; +- } +- +- mode = 0; +- if ( showFunc != NULL ) +- { +- mode |= 0444; +- } +- if ( parseFunc != NULL ) +- { +- mode |= 0200; +- } +- +- if ( parent == NULL ) +- { +- entry->pde = create_proc_entry( entryName, mode, NULL ); +- } +- else +- { +- entry->pde = create_proc_entry( entryName, mode, (*parent)->pde ); +- entry->parent_pde = (*parent)->pde; +- } +- if ( entry->pde == NULL ) +- { +- kfree( entry ); +- return -ENOMEM; +- } +- entry->showFunc = showFunc; +- entry->parseFunc = parseFunc; +- entry->data = data; +- entry->name = entryName; +- +- entry->pde->data = entry; +- entry->pde->proc_fops = &cfg_proc_fops; +- +- *entryp = entry; +- return VCOS_SUCCESS; +-} +- +-/***************************************************************************** +-* +-* vcos_cfg_remove_entry +-* +-*****************************************************************************/ +- +-VCOS_STATUS_T vcos_cfg_remove_entry( VCOS_CFG_ENTRY_T *entryp ) +-{ +- if (( entryp != NULL ) && ( *entryp != NULL )) +- { +- remove_proc_entry( (*entryp)->name, (*entryp)->parent_pde ); +- +- kfree( *entryp ); +- *entryp = NULL; +- } +- +- return VCOS_SUCCESS; +-} +- +-/***************************************************************************** +-* +-* vcos_cfg_is_entry_created +-* +-*****************************************************************************/ +- +-int vcos_cfg_is_entry_created( VCOS_CFG_ENTRY_T entry ) +-{ +- return ( entry != NULL ) && ( entry->pde != NULL ); +-} +- +-/***************************************************************************** +-* +-* vcos_cfg_buf_printf +-* +-*****************************************************************************/ +- +-void vcos_cfg_buf_printf( VCOS_CFG_BUF_T buf, const char *fmt, ... ) +-{ +- struct seq_file *m = buf->seq; +- +- /* Bah - there is no seq_vprintf */ +- +- va_list args; +- int len; +- +- if (m->count < m->size) { +- va_start(args, fmt); +- len = vsnprintf(m->buf + m->count, m->size - m->count, fmt, args); +- va_end(args); +- if (m->count + len < m->size) { +- m->count += len; +- return; +- } +- } +- m->count = m->size; +-} +- +-/***************************************************************************** +-* +-* vcos_cfg_buf_get_str +-* +-*****************************************************************************/ +- +-char *vcos_cfg_buf_get_str( VCOS_CFG_BUF_T buf ) +-{ +- return buf->charBuf; +-} +- +-/***************************************************************************** +-* +-* vcos_cfg_get_proc_entry +-* +-* This function is only created for a couple of backwards compatibility ' +-* issues and shouldn't normally be used. +-* +-*****************************************************************************/ +- +-void *vcos_cfg_get_proc_entry( VCOS_CFG_ENTRY_T entry ) +-{ +- return entry->pde; +-} +- +-/***************************************************************************** +-* +-* vcos_cfg_get_entry_name +-* +-*****************************************************************************/ +- +-const char *vcos_cfg_get_entry_name( VCOS_CFG_ENTRY_T entry ) +-{ +- return entry->pde->name; +-} +- +- +-EXPORT_SYMBOL( vcos_cfg_mkdir ); +-EXPORT_SYMBOL( vcos_cfg_create_entry ); +-EXPORT_SYMBOL( vcos_cfg_remove_entry ); +-EXPORT_SYMBOL( vcos_cfg_get_entry_name ); +-EXPORT_SYMBOL( vcos_cfg_is_entry_created ); +-EXPORT_SYMBOL( vcos_cfg_buf_printf ); +-EXPORT_SYMBOL( vcos_cfg_buf_get_str ); +- +-EXPORT_SYMBOL_GPL( vcos_cfg_get_proc_entry ); +- +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/linuxkernel/vcos_linuxkernel_misc.c +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vcos/linuxkernel/vcos_linuxkernel_misc.c 2013-07-26 19:32:07.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,111 +0,0 @@ +-/***************************************************************************** +-* Copyright 2009 - 2010 Broadcom Corporation. All rights reserved. +-* +-* Unless you and Broadcom execute a separate written software license +-* agreement governing use of this software, this software is licensed to you +-* under the terms of the GNU General Public License version 2, available at +-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). +-* +-* Notwithstanding the above, under no circumstances may you combine this +-* software in any way with any other Broadcom software provided under a +-* license other than the GPL, without Broadcom's express prior written +-* consent. +-*****************************************************************************/ +- +-#include "interface/vcos/vcos.h" +-#include +-#include +-#include +-#include +-#include +- +-/***************************************************************************** +-* +-* vcos_semaphore_wait_freezable +-* +-*****************************************************************************/ +- +-VCOS_STATUS_T vcos_semaphore_wait_freezable(VCOS_SEMAPHORE_T *sem) +-{ +- int rval, sig_pended = 0; +- unsigned long flags; +- struct task_struct *task = current; +- +- while (1) { +- rval = down_interruptible((struct semaphore *)sem); +- if (rval == 0) { /* down now */ +- break; +- } else { +- if (freezing(current)) { +- try_to_freeze(); +- } else { +- spin_lock_irqsave(&task->sighand->siglock, flags); +- if (test_tsk_thread_flag(task, TIF_SIGPENDING)) { +- clear_tsk_thread_flag(task, TIF_SIGPENDING); +- sig_pended = 1; +- } +- spin_unlock_irqrestore(&task->sighand->siglock, flags); +- } +- } +- } +- +- if (sig_pended) { +- spin_lock_irqsave(&task->sighand->siglock, flags); +- set_tsk_thread_flag(task, TIF_SIGPENDING); +- spin_unlock_irqrestore(&task->sighand->siglock, flags); +- } +- +- return 0; +-} +- +-EXPORT_SYMBOL( vcos_semaphore_wait_freezable ); +- +-/***************************************************************************** +-* +-* vcos_kmalloc +-* +-* We really need to convert malloc to do kmalloc or vmalloc based on the +-* size, but for now we'll add a separate function. +-* +-*****************************************************************************/ +- +-void *vcos_kmalloc(VCOS_UNSIGNED size, const char *description) +-{ +- (void)description; +- +- return kmalloc( size, GFP_KERNEL ); +-} +- +-/***************************************************************************** +-* +-* vcos_kmalloc +-* +-* We really need to convert malloc to do kmalloc or vmalloc based on the +-* size, but for now we'll add a separate function. +-* +-*****************************************************************************/ +- +-void *vcos_kcalloc(VCOS_UNSIGNED num, VCOS_UNSIGNED size, const char *description) +-{ +- (void)description; +- +- return kzalloc( num * size, GFP_KERNEL ); +-} +- +-/***************************************************************************** +-* +-* vcos_kfree +-* +-*****************************************************************************/ +- +-void vcos_kfree(void *ptr) +-{ +- kfree( ptr ); +-} +- +-EXPORT_SYMBOL( vcos_kmalloc ); +-EXPORT_SYMBOL( vcos_kcalloc ); +-EXPORT_SYMBOL( vcos_kfree ); +- +-// END ######################################################################### +-// ############################################################################# +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/linuxkernel/vcos_mod_init.c +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vcos/linuxkernel/vcos_mod_init.c 2013-07-26 19:32:00.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,64 +0,0 @@ +-/***************************************************************************** +-* Copyright 2006 - 2008 Broadcom Corporation. All rights reserved. +-* +-* Unless you and Broadcom execute a separate written software license +-* agreement governing use of this software, this software is licensed to you +-* under the terms of the GNU General Public License version 2, available at +-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). +-* +-* Notwithstanding the above, under no circumstances may you combine this +-* software in any way with any other Broadcom software provided under a +-* license other than the GPL, without Broadcom's express prior written +-* consent. +-****************************************************************************/ +- +-/* ---- Include Files ---------------------------------------------------- */ +- +-#include "interface/vcos/vcos.h" +-#include +- +-/* ---- Public Variables ------------------------------------------------- */ +- +-/* ---- Private Constants and Types -------------------------------------- */ +- +-/* ---- Private Variables ------------------------------------------------ */ +- +-/* ---- Private Function Prototypes -------------------------------------- */ +- +-/* ---- Functions -------------------------------------------------------- */ +- +-/**************************************************************************** +-* +-* Called to perform module initialization when the module is loaded +-* +-***************************************************************************/ +- +-static int __init vcos_mod_init( void ) +-{ +- printk( KERN_INFO "VCOS Module\n" ); +- +- vcos_init(); +- return 0; +-} +- +-/**************************************************************************** +-* +-* Called to perform module cleanup when the module is unloaded. +-* +-***************************************************************************/ +- +-static void __exit vcos_mod_exit( void ) +-{ +- vcos_deinit(); +-} +- +-/****************************************************************************/ +- +-module_init( vcos_mod_init ); +-module_exit( vcos_mod_exit ); +- +-MODULE_AUTHOR("Broadcom"); +-MODULE_DESCRIPTION( "VCOS Module Functions" ); +-MODULE_LICENSE( "GPL" ); +-MODULE_VERSION( "1.0" ); +- +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/linuxkernel/vcos_platform.h +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vcos/linuxkernel/vcos_platform.h 2013-07-26 19:32:07.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,507 +0,0 @@ +-/* +- * Copyright (c) 2010-2011 Broadcom. All rights reserved. +- * +- * This program is free software; you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation; either version 2 of the License, or +- * (at your option) any later version. +- * +- * This program is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with this program; if not, write to the Free Software +- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +- */ +- +-/*============================================================================= +-VideoCore OS Abstraction Layer - Linux kernel (partial) implementation. +-=============================================================================*/ +- +-/* Do not include this file directly - instead include it via vcos.h */ +- +-/** @file +- * +- * Linux kernel (partial) implementation of VCOS. +- * +- */ +- +-#ifndef VCOS_PLATFORM_H +-#define VCOS_PLATFORM_H +- +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include /* for time_t */ +-#include +-#include +- +-#define VCOS_HAVE_RTOS 1 +-#define VCOS_HAVE_SEMAPHORE 1 +-#define VCOS_HAVE_EVENT 1 +-#define VCOS_HAVE_QUEUE 0 +-#define VCOS_HAVE_LEGACY_ISR 0 +-#define VCOS_HAVE_TIMER 1 +-#define VCOS_HAVE_CANCELLATION_SAFE_TIMER 0 +-#define VCOS_HAVE_MEMPOOL 0 +-#define VCOS_HAVE_ISR 0 +-#define VCOS_HAVE_ATOMIC_FLAGS 1 +-#define VCOS_HAVE_BLOCK_POOL 0 +-#define VCOS_HAVE_ONCE 1 +-#define VCOS_HAVE_FILE 0 +-#define VCOS_HAVE_USER_BUF 0 +-#define VCOS_HAVE_CFG 1 +-#define VCOS_HAVE_SPINLOCK 0 +-#define VCOS_HAVE_CMD 1 +-#define VCOS_HAVE_EVENT_FLAGS 1 +- +-/* Exclude many VCOS classes which don't have predicates */ +-#define VCOS_TLS_H +-#define VCOS_NAMED_MUTEX_H +-#define VCOS_REENTRANT_MUTEX_H +-#define VCOS_NAMED_SEMAPHORE_H +-#define VCOS_QUICKSLOW_MUTEX_H +-/*#define VCOS_INIT_H */ +-/*#define VCOS_MEM_H */ +-/*#define VCOS_STRING_H */ +- +-typedef struct semaphore VCOS_SEMAPHORE_T; +-typedef struct semaphore VCOS_EVENT_T; +-typedef struct mutex VCOS_MUTEX_T; +-typedef volatile int VCOS_ONCE_T; +- +-typedef unsigned int VCOS_UNSIGNED; +-typedef unsigned int VCOS_OPTION; +-typedef atomic_t VCOS_ATOMIC_FLAGS_T; +- +-typedef struct +-{ +- struct timer_list linux_timer; +- void *context; +- void (*expiration_routine)(void *context); +- +-} VCOS_TIMER_T; +- +-typedef struct VCOS_LLTHREAD_T +-{ +- struct task_struct *thread; /**< The thread itself */ +- VCOS_SEMAPHORE_T suspend; /**< For support event groups and similar - a per thread semaphore */ +-} VCOS_LLTHREAD_T; +- +-typedef enum +-{ +- VCOS_O_RDONLY = 00000000, +- VCOS_O_WRONLY = 00000001, +- VCOS_O_RDWR = 00000002, +- VCOS_O_TRUNC = 00001000, +-} VCOS_FILE_FLAGS_T; +- +-typedef struct file *VCOS_FILE_T; +- +-#define VCOS_SUSPEND -1 +-#define VCOS_NO_SUSPEND 0 +- +-#define VCOS_START 1 +-#define VCOS_NO_START 0 +- +-#define VCOS_THREAD_PRI_MIN -20 +-#define VCOS_THREAD_PRI_MAX 19 +- +-#define VCOS_THREAD_PRI_INCREASE -1 +-#define VCOS_THREAD_PRI_HIGHEST VCOS_THREAD_PRI_MIN +-#define VCOS_THREAD_PRI_LOWEST VCOS_THREAD_PRI_MAX +-#define VCOS_THREAD_PRI_NORMAL ((VCOS_THREAD_PRI_MAX+VCOS_THREAD_PRI_MIN)/2) +-#define VCOS_THREAD_PRI_ABOVE_NORMAL (VCOS_THREAD_PRI_NORMAL + VCOS_THREAD_PRI_INCREASE) +-#define VCOS_THREAD_PRI_REALTIME VCOS_THREAD_PRI_HIGHEST +- +-#define _VCOS_AFFINITY_DEFAULT 0 +-#define _VCOS_AFFINITY_CPU0 0 +-#define _VCOS_AFFINITY_CPU1 0 +-#define _VCOS_AFFINITY_MASK 0 +-#define VCOS_CAN_SET_STACK_ADDR 0 +- +-#define VCOS_TICKS_PER_SECOND HZ +- +-#include "interface/vcos/generic/vcos_generic_event_flags.h" +-#include "interface/vcos/generic/vcos_mem_from_malloc.h" +-#include "interface/vcos/generic/vcos_joinable_thread_from_plain.h" +- +-/*********************************************************** +- * +- * Memory allcoation +- * +- ***********************************************************/ +- +-#define _vcos_platform_malloc vcos_platform_malloc +-#define _vcos_platform_free vcos_platform_free +- +-void *vcos_platform_malloc( VCOS_UNSIGNED required_size ); +-void vcos_platform_free( void *ptr ); +- +-#if defined(VCOS_INLINE_BODIES) +- +-#undef VCOS_ASSERT_LOGGING_DISABLE +-#define VCOS_ASSERT_LOGGING_DISABLE 1 +- +-/*********************************************************** +- * +- * Counted Semaphores +- * +- ***********************************************************/ +- +-VCOS_INLINE_IMPL +-VCOS_STATUS_T vcos_semaphore_wait(VCOS_SEMAPHORE_T *sem) { +- int ret = down_interruptible(sem); +- if ( ret == 0 ) +- /* Success */ +- return VCOS_SUCCESS; +- else if ( ret == -EINTR ) +- /* Interrupted */ +- return VCOS_EINTR; +- else +- /* Default (timeout) */ +- return VCOS_EAGAIN; +-} +- +-VCOS_INLINE_IMPL +-VCOS_STATUS_T vcos_semaphore_trywait(VCOS_SEMAPHORE_T *sem) { +- if (down_trylock(sem) != 0) +- return VCOS_EAGAIN; +- return VCOS_SUCCESS; +-} +- +-VCOS_INLINE_IMPL +-VCOS_STATUS_T vcos_semaphore_create(VCOS_SEMAPHORE_T *sem, +- const char *name, +- VCOS_UNSIGNED initial_count) { +- sema_init(sem, initial_count); +- return VCOS_SUCCESS; +-} +- +-VCOS_INLINE_IMPL +-void vcos_semaphore_delete(VCOS_SEMAPHORE_T *sem) { +-} +- +-VCOS_INLINE_IMPL +-VCOS_STATUS_T vcos_semaphore_post(VCOS_SEMAPHORE_T *sem) { +- up(sem); +- return VCOS_SUCCESS; +-} +- +-/*********************************************************** +- * +- * Threads +- * +- ***********************************************************/ +- +-#include "vcos_thread_map.h" +- +-VCOS_INLINE_IMPL +-VCOS_LLTHREAD_T *vcos_llthread_current(void) { +- return &vcos_kthread_current()->thread; +-} +- +-VCOS_INLINE_IMPL +-void vcos_llthread_resume(VCOS_LLTHREAD_T *thread) { +- vcos_assert(0); +-} +- +-VCOS_INLINE_IMPL +-void vcos_sleep(uint32_t ms) { +- msleep(ms); +-} +- +-VCOS_INLINE_IMPL +-void vcos_thread_set_priority(VCOS_THREAD_T *thread, VCOS_UNSIGNED p) { +- /* not implemented */ +-} +-VCOS_INLINE_IMPL +-VCOS_UNSIGNED vcos_thread_get_priority(VCOS_THREAD_T *thread) { +- /* not implemented */ +- return 0; +-} +- +-/*********************************************************** +- * +- * Miscellaneous +- * +- ***********************************************************/ +- +-VCOS_INLINE_IMPL +-int vcos_strcasecmp(const char *s1, const char *s2) { +- return strcasecmp(s1,s2); +-} +- +- +-/*********************************************************** +- * +- * Mutexes +- * +- ***********************************************************/ +- +-VCOS_INLINE_IMPL +-VCOS_STATUS_T vcos_mutex_create(VCOS_MUTEX_T *m, const char *name) { +- mutex_init(m); +- return VCOS_SUCCESS; +-} +- +-VCOS_INLINE_IMPL +-void vcos_mutex_delete(VCOS_MUTEX_T *m) { +-} +- +-VCOS_INLINE_IMPL +-VCOS_STATUS_T vcos_mutex_lock(VCOS_MUTEX_T *m) { +- int ret = mutex_lock_interruptible(m); +- if ( ret == 0 ) +- /* Success */ +- return VCOS_SUCCESS; +- else if ( ret == -EINTR ) +- /* Interrupted */ +- return VCOS_EINTR; +- else +- /* Default */ +- return VCOS_EAGAIN; +-} +- +-VCOS_INLINE_IMPL +-void vcos_mutex_unlock(VCOS_MUTEX_T *m) { +- mutex_unlock(m); +-} +- +-VCOS_INLINE_IMPL +-int vcos_mutex_is_locked(VCOS_MUTEX_T *m) { +- if (mutex_trylock(m) != 0) +- return 1; /* it was locked */ +- mutex_unlock(m); +- /* it wasn't locked */ +- return 0; +-} +- +-VCOS_INLINE_IMPL +-VCOS_STATUS_T vcos_mutex_trylock(VCOS_MUTEX_T *m) { +- if (mutex_trylock(m) == 0) +- return VCOS_SUCCESS; +- else +- return VCOS_EAGAIN; +-} +- +-/* For supporting event groups - per thread semaphore */ +-VCOS_INLINE_IMPL +-void _vcos_thread_sem_wait(void) { +- VCOS_THREAD_T *t = vcos_thread_current(); +- vcos_semaphore_wait(&t->suspend); +-} +- +-VCOS_INLINE_IMPL +-void _vcos_thread_sem_post(VCOS_THREAD_T *target) { +- vcos_semaphore_post(&target->suspend); +-} +- +-/*********************************************************** +- * +- * Events +- * +- ***********************************************************/ +- +-VCOS_INLINE_IMPL +-VCOS_STATUS_T vcos_event_create(VCOS_EVENT_T *event, const char *debug_name) +-{ +- sema_init(event, 0); +- return VCOS_SUCCESS; +-} +- +-VCOS_INLINE_IMPL +-void vcos_event_signal(VCOS_EVENT_T *event) +-{ +- up(event); +-} +- +-VCOS_INLINE_IMPL +-VCOS_STATUS_T vcos_event_wait(VCOS_EVENT_T *event) +-{ +- int ret = down_interruptible(event); +- if ( ret == -EINTR ) +- /* Interrupted */ +- return VCOS_EINTR; +- else if (ret != 0) +- /* Default (timeout) */ +- return VCOS_EAGAIN; +- /* Emulate a maximum count of 1 by removing any extra upness */ +- while (down_trylock(event) == 0) continue; +- return VCOS_SUCCESS; +-} +- +-VCOS_INLINE_DECL +-VCOS_STATUS_T vcos_event_try(VCOS_EVENT_T *event) +-{ +- return (down_trylock(event) == 0) ? VCOS_SUCCESS : VCOS_EAGAIN; +-} +- +-VCOS_INLINE_IMPL +-void vcos_event_delete(VCOS_EVENT_T *event) +-{ +-} +- +-/*********************************************************** +- * +- * Timers +- * +- ***********************************************************/ +- +-VCOS_INLINE_DECL +-void vcos_timer_linux_func(unsigned long data) +-{ +- VCOS_TIMER_T *vcos_timer = (VCOS_TIMER_T *)data; +- +- vcos_timer->expiration_routine( vcos_timer->context ); +-} +- +-VCOS_INLINE_DECL +-VCOS_STATUS_T vcos_timer_create(VCOS_TIMER_T *timer, +- const char *name, +- void (*expiration_routine)(void *context), +- void *context) { +- init_timer(&timer->linux_timer); +- timer->linux_timer.data = (unsigned long)timer; +- timer->linux_timer.function = vcos_timer_linux_func; +- +- timer->context = context; +- timer->expiration_routine = expiration_routine; +- +- return VCOS_SUCCESS; +-} +- +-VCOS_INLINE_IMPL +-void vcos_timer_set(VCOS_TIMER_T *timer, VCOS_UNSIGNED delay_ms) { +- timer->linux_timer.expires = jiffies + msecs_to_jiffies(delay_ms); +- add_timer(&timer->linux_timer); +-} +- +-VCOS_INLINE_IMPL +-void vcos_timer_cancel(VCOS_TIMER_T *timer) { +- del_timer(&timer->linux_timer); +-} +- +-VCOS_INLINE_IMPL +-void vcos_timer_reset(VCOS_TIMER_T *timer, VCOS_UNSIGNED delay_ms) { +- del_timer_sync(&timer->linux_timer); +- timer->linux_timer.expires = jiffies + msecs_to_jiffies(delay_ms); +- add_timer(&timer->linux_timer); +-} +- +-VCOS_INLINE_IMPL +-void vcos_timer_delete(VCOS_TIMER_T *timer) { +- timer->context = NULL; +- timer->expiration_routine = NULL; +- timer->linux_timer.function = NULL; +- timer->linux_timer.data = 0; +- return; +-} +- +-VCOS_INLINE_IMPL +-VCOS_UNSIGNED vcos_process_id_current(void) { +- return (VCOS_UNSIGNED)current->pid; +-} +- +- +-VCOS_INLINE_IMPL +-int vcos_in_interrupt(void) { +- return in_interrupt(); +-} +- +-/*********************************************************** +- * +- * Atomic flags +- * +- ***********************************************************/ +- +-VCOS_INLINE_IMPL +-VCOS_STATUS_T vcos_atomic_flags_create(VCOS_ATOMIC_FLAGS_T *atomic_flags) +-{ +- atomic_set(atomic_flags, 0); +- return VCOS_SUCCESS; +-} +- +-VCOS_INLINE_IMPL +-void vcos_atomic_flags_or(VCOS_ATOMIC_FLAGS_T *atomic_flags, uint32_t flags) +-{ +- uint32_t value; +- do { +- value = atomic_read(atomic_flags); +- } while (atomic_cmpxchg(atomic_flags, value, value | flags) != value); +-} +- +-VCOS_INLINE_IMPL +-uint32_t vcos_atomic_flags_get_and_clear(VCOS_ATOMIC_FLAGS_T *atomic_flags) +-{ +- return atomic_xchg(atomic_flags, 0); +-} +- +-VCOS_INLINE_IMPL +-void vcos_atomic_flags_delete(VCOS_ATOMIC_FLAGS_T *atomic_flags) +-{ +-} +- +-#undef VCOS_ASSERT_LOGGING_DISABLE +-#define VCOS_ASSERT_LOGGING_DISABLE 0 +- +-#endif /* VCOS_INLINE_BODIES */ +- +-VCOS_INLINE_DECL void _vcos_thread_sem_wait(void); +-VCOS_INLINE_DECL void _vcos_thread_sem_post(VCOS_THREAD_T *); +- +-/*********************************************************** +- * +- * Misc +- * +- ***********************************************************/ +-VCOS_INLINE_DECL char *vcos_strdup(const char *str); +- +-/*********************************************************** +- * +- * Logging +- * +- ***********************************************************/ +- +-VCOSPRE_ const char * VCOSPOST_ _vcos_log_level(void); +-#define _VCOS_LOG_LEVEL() _vcos_log_level() +- +-#define vcos_log_platform_init() _vcos_log_platform_init() +-#define vcos_log_platform_register(category) _vcos_log_platform_register(category) +-#define vcos_log_platform_unregister(category) _vcos_log_platform_unregister(category) +- +-struct VCOS_LOG_CAT_T; /* Forward declaration since vcos_logging.h hasn't been included yet */ +- +-void _vcos_log_platform_init(void); +-void _vcos_log_platform_register(struct VCOS_LOG_CAT_T *category); +-void _vcos_log_platform_unregister(struct VCOS_LOG_CAT_T *category); +- +-/*********************************************************** +- * +- * Memory barriers +- * +- ***********************************************************/ +- +-#define vcos_wmb(x) wmb() +-#define vcos_rmb() rmb() +- +-#include "interface/vcos/generic/vcos_common.h" +-/*#include "interface/vcos/generic/vcos_generic_quickslow_mutex.h" */ +- +-#endif /* VCOS_PLATFORM_H */ +- +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/linuxkernel/vcos_platform_types.h +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vcos/linuxkernel/vcos_platform_types.h 2013-07-26 19:34:23.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,59 +0,0 @@ +-/* +- * Copyright (c) 2010-2011 Broadcom. All rights reserved. +- * +- * This program is free software; you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation; either version 2 of the License, or +- * (at your option) any later version. +- * +- * This program is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with this program; if not, write to the Free Software +- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +- */ +- +-/*============================================================================= +-VideoCore OS Abstraction Layer - platform-specific types and defines +-=============================================================================*/ +- +-#ifndef VCOS_PLATFORM_TYPES_H +-#define VCOS_PLATFORM_TYPES_H +- +-#include +-#include +-#include +-#include +- +-#define VCOSPRE_ extern +-#define VCOSPOST_ +- +-#if defined(__GNUC__) && (( __GNUC__ > 2 ) || (( __GNUC__ == 2 ) && ( __GNUC_MINOR__ >= 3 ))) +-#define VCOS_FORMAT_ATTR_(ARCHETYPE, STRING_INDEX, FIRST_TO_CHECK) __attribute__ ((format (ARCHETYPE, STRING_INDEX, FIRST_TO_CHECK))) +-#else +-#define VCOS_FORMAT_ATTR_(ARCHETYPE, STRING_INDEX, FIRST_TO_CHECK) +-#endif +- +-#if !defined( __STDC_VERSION__ ) +-#define __STDC_VERSION__ 199901L +-#endif +- +-#if !defined( __STDC_VERSION ) +-#define __STDC_VERSION __STDC_VERSION__ +-#endif +- +-static inline void __vcos_bkpt( void ) { BUG(); } +-#define VCOS_BKPT __vcos_bkpt() +- +-#define VCOS_ASSERT_MSG(...) printk( KERN_ERR "vcos_assert: " __VA_ARGS__ ) +- +-#define PRId64 "lld" +-#define PRIi64 "lli" +-#define PRIo64 "llo" +-#define PRIu64 "llu" +-#define PRIx64 "llx" +- +-#endif +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/linuxkernel/vcos_thread_map.c +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vcos/linuxkernel/vcos_thread_map.c 2013-07-26 19:32:00.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,129 +0,0 @@ +-/***************************************************************************** +-* Copyright 2009 - 2010 Broadcom Corporation. All rights reserved. +-* +-* Unless you and Broadcom execute a separate written software license +-* agreement governing use of this software, this software is licensed to you +-* under the terms of the GNU General Public License version 2, available at +-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). +-* +-* Notwithstanding the above, under no circumstances may you combine this +-* software in any way with any other Broadcom software provided under a +-* license other than the GPL, without Broadcom's express prior written +-* consent. +-*****************************************************************************/ +- +-/** Support to allow VCOS thread-related functions to be called from +- * threads that were not created by VCOS. +- */ +- +-#include +-#include +-#include +-#include +- +-#include "vcos_thread_map.h" +-#include "interface/vcos/vcos_logging.h" +- +-/* +- * Store the vcos_thread pointer at the end of +- * current kthread stack, right after the thread_info +- * structure. +- * +- * I belive we should be safe here to steal these 4 bytes +- * from the stack, as long as the vcos thread does not use up +- * all the stack available +- * +- * NOTE: This scheme will not work on architectures with stack growing up +- */ +- +-/* Shout, if we are not being compiled for ARM kernel */ +- +-#ifndef CONFIG_ARM +-#error " **** The vcos kthread implementation may not work for non-ARM kernel ****" +-#endif +- +-static inline void *to_current_vcos_thread(void) +-{ +- unsigned long *vcos_data; +- +- vcos_data = (unsigned long *)((char *)current_thread_info() + sizeof(struct thread_info)); +- +- return (void *)vcos_data; +-} +- +- +-static inline void *to_vcos_thread(struct task_struct *tsk) +-{ +- unsigned long *vcos_data; +- +- vcos_data = (unsigned long *)((char *)tsk->stack + sizeof(struct thread_info)); +- +- return (void *)vcos_data; +-} +- +-/** +- @fn uint32_t vcos_add_thread(THREAD_MAP_T *vcos_thread); +-*/ +-uint32_t vcos_add_thread(VCOS_THREAD_T *vcos_thread) +-{ +- VCOS_THREAD_T **vcos_thread_storage = (VCOS_THREAD_T **)to_current_vcos_thread(); +- +- *vcos_thread_storage = vcos_thread; +- +- return(0); +-} +- +- +-/** +- @fn uint32_t vcos_remove_thread(struct task_struct * thread_id); +-*/ +-uint32_t vcos_remove_thread(struct task_struct *thread_id) +-{ +- /* Remove thread_id -> VCOS_THREAD_T relationship */ +- VCOS_THREAD_T **vcos_thread_storage; +- +- /* +- * We want to be able to build vcos as a loadable module, which +- * means that we can't call get_task_struct. So we assert if we're +- * ever called with thread_id != current. +- */ +- +- BUG_ON( thread_id != current ); +- +- vcos_thread_storage = (VCOS_THREAD_T **)to_vcos_thread(thread_id); +- +- *(unsigned long *)vcos_thread_storage = 0xCAFEBABE; +- +- return(0); +-} +- +- +-VCOS_THREAD_T *vcos_kthread_current(void) +-{ +- VCOS_THREAD_T **vcos_thread_storage = (VCOS_THREAD_T **)to_current_vcos_thread(); +- +- /* If we find this, either the thread is already dead or stack pages of a +- * dead vcos thread are re-allocated to this one. +- * +- * Since there's no way to differentiate between these 2 cases, we just dump +- * the current task name to the log. +- * +- * If the current thread is created using VCOS API, you should *never* see this +- * print. +- * +- * If its a non-VCOS thread, just let it go ... +- * +- * To debug VCOS, uncomment printk's under the "if" condition below +- * +- */ +- if (*vcos_thread_storage == (void *)0xCAFEBABE) +- { +- #if 0 +- printk(KERN_DEBUG"****************************************************\n"); +- printk(KERN_DEBUG"%s : You have a problem, if \"%s\" is a VCOS thread\n",__func__, current->comm); +- printk(KERN_DEBUG"****************************************************\n"); +- #endif +- } +- +- return *vcos_thread_storage; +-} +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/linuxkernel/vcos_thread_map.h +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vcos/linuxkernel/vcos_thread_map.h 2013-07-26 19:32:00.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,39 +0,0 @@ +-/***************************************************************************** +-* Copyright 2009 - 2010 Broadcom Corporation. All rights reserved. +-* +-* Unless you and Broadcom execute a separate written software license +-* agreement governing use of this software, this software is licensed to you +-* under the terms of the GNU General Public License version 2, available at +-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). +-* +-* Notwithstanding the above, under no circumstances may you combine this +-* software in any way with any other Broadcom software provided under a +-* license other than the GPL, without Broadcom's express prior written +-* consent. +-*****************************************************************************/ +- +- +-#ifndef VCOS_THREAD_MAP_H +-#define VCOS_THREAD_MAP_H +- +-#include +- +-#include "vcos_platform.h" +- +-static inline void vcos_thread_map_init(void) +-{ +- return; +-} +- +-static inline void vcos_thread_map_cleanup(void) +-{ +- return; +-} +- +-uint32_t vcos_add_thread(VCOS_THREAD_T *vcos_thread); +- +-uint32_t vcos_remove_thread(struct task_struct *thread_id); +- +-VCOS_THREAD_T *vcos_kthread_current(void); +- +-#endif /*VCOS_THREAD_MAP_H */ +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos.h +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vcos/vcos.h 2013-07-26 19:32:07.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,212 +0,0 @@ +-/* +- * Copyright (c) 2010-2011 Broadcom. All rights reserved. +- * +- * This program is free software; you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation; either version 2 of the License, or +- * (at your option) any later version. +- * +- * This program is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with this program; if not, write to the Free Software +- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +- */ +- +-/*============================================================================= +-VideoCore OS Abstraction Layer - public header file +-=============================================================================*/ +- +-/** +- * \mainpage OS Abstraction Layer +- * +- * \section intro Introduction +- * +- * This abstraction layer is here to allow the underlying OS to be easily changed (e.g. from +- * Nucleus to ThreadX) and to aid in porting host applications to new targets. +- * +- * \subsection error Error handling +- * +- * Wherever possible, VCOS functions assert internally and return void. The only exceptions +- * are creation functions (which might fail due to lack of resources) and functions that +- * might timeout or fail due to lack of space. Errors that might be reported by the underlying +- * OS API (e.g. invalid mutex) are treated as a programming error, and are merely asserted on. +- * +- * \section thread_synch Threads and synchronisation +- * +- * \subsection thread Threads +- * +- * The thread API is somewhat different to that found in Nucleus. In particular, threads +- * cannot just be destroyed at arbitrary times and nor can they merely exit. This is so +- * that the same API can be implemented across all interesting platforms without too much +- * difficulty. See vcos_thread.h for details. Thread attributes are configured via +- * the VCOS_THREAD_ATTR_T structure, found in vcos_thread_attr.h. +- * +- * \subsection sema Semaphores +- * +- * Counted semaphores (c.f. Nucleus NU_SEMAPHORE) are created with VCOS_SEMAPHORE_T. +- * Under ThreadX on VideoCore, semaphores are implemented using VideoCore spinlocks, and +- * so are quite a lot faster than ordinary ThreadX semaphores. See vcos_semaphore.h. +- * +- * \subsection mtx Mutexes +- * +- * Mutexes are used for locking. Attempts to take a mutex twice, or to unlock it +- * in a different thread to the one in which it was locked should be expected to fail. +- * Mutexes are not re-entrant (see vcos_reentrant_mutex.h for a slightly slower +- * re-entrant mutex). +- * +- * \subsection evflags Event flags +- * +- * Event flags (the ThreadX name - also known as event groups under Nucleus) provide +- * 32 flags which can be waited on by multiple clients, and signalled by multiple clients. +- * A timeout can be specified. See vcos_event_flags.h. An alternative to this is the +- * VCOS_EVENT_T (see vcos_event.h) which is akin to the Win32 auto-reset event, or a +- * saturating counted semaphore. +- * +- * \subsection event Events +- * +- * A VCOS_EVENT_T is a bit like a saturating semaphore. No matter how many times it +- * is signalled, the waiter will only wake up once. See vcos_event.h. You might think this +- * is useful if you suspect that the cost of reading the semaphore count (perhaps via a +- * system call) is expensive on your platform. +- * +- * \subsection tls Thread local storage +- * +- * Thread local storage is supported using vcos_tls.h. This is emulated on Nucleus +- * and ThreadX. +- * +- * \section int Interrupts +- * +- * The legacy LISR/HISR scheme found in Nucleus is supported via the legacy ISR API, +- * which is also supported on ThreadX. New code should avoid this, and old code should +- * be migrated away from it, since it is slow. See vcos_legacy_isr.h. +- * +- * Registering an interrupt handler, and disabling/restoring interrupts, is handled +- * using the functions in vcos_isr.h. +- * +- */ +- +-/** +- * \file vcos.h +- * +- * This is the top level header file. Clients include this. It pulls in the platform-specific +- * header file (vcos_platform.h) together with header files defining the expected APIs, such +- * as vcos_mutex.h, vcos_semaphore.h, etc. It is also possible to include these header files +- * directly. +- * +- */ +- +-#ifndef VCOS_H +-#define VCOS_H +- +-#include "interface/vcos/vcos_assert.h" +-#include "vcos_types.h" +-#include "vcos_platform.h" +- +-#ifndef VCOS_INIT_H +-#include "interface/vcos/vcos_init.h" +-#endif +- +-#ifndef VCOS_SEMAPHORE_H +-#include "interface/vcos/vcos_semaphore.h" +-#endif +- +-#ifndef VCOS_THREAD_H +-#include "interface/vcos/vcos_thread.h" +-#endif +- +-#ifndef VCOS_MUTEX_H +-#include "interface/vcos/vcos_mutex.h" +-#endif +- +-#ifndef VCOS_MEM_H +-#include "interface/vcos/vcos_mem.h" +-#endif +- +-#ifndef VCOS_LOGGING_H +-#include "interface/vcos/vcos_logging.h" +-#endif +- +-#ifndef VCOS_STRING_H +-#include "interface/vcos/vcos_string.h" +-#endif +- +-#ifndef VCOS_EVENT_H +-#include "interface/vcos/vcos_event.h" +-#endif +- +-#ifndef VCOS_THREAD_ATTR_H +-#include "interface/vcos/vcos_thread_attr.h" +-#endif +- +-#ifndef VCOS_TLS_H +-#include "interface/vcos/vcos_tls.h" +-#endif +- +-#ifndef VCOS_REENTRANT_MUTEX_H +-#include "interface/vcos/vcos_reentrant_mutex.h" +-#endif +- +-#ifndef VCOS_NAMED_SEMAPHORE_H +-#include "interface/vcos/vcos_named_semaphore.h" +-#endif +- +-#ifndef VCOS_QUICKSLOW_MUTEX_H +-#include "interface/vcos/vcos_quickslow_mutex.h" +-#endif +- +-/* Headers with predicates */ +- +-#if VCOS_HAVE_EVENT_FLAGS +-#include "interface/vcos/vcos_event_flags.h" +-#endif +- +-#if VCOS_HAVE_QUEUE +-#include "interface/vcos/vcos_queue.h" +-#endif +- +-#if VCOS_HAVE_LEGACY_ISR +-#include "interface/vcos/vcos_legacy_isr.h" +-#endif +- +-#if VCOS_HAVE_TIMER +-#include "interface/vcos/vcos_timer.h" +-#endif +- +-#if VCOS_HAVE_MEMPOOL +-#include "interface/vcos/vcos_mempool.h" +-#endif +- +-#if VCOS_HAVE_ISR +-#include "interface/vcos/vcos_isr.h" +-#endif +- +-#if VCOS_HAVE_ATOMIC_FLAGS +-#include "interface/vcos/vcos_atomic_flags.h" +-#endif +- +-#if VCOS_HAVE_ONCE +-#include "interface/vcos/vcos_once.h" +-#endif +- +-#if VCOS_HAVE_BLOCK_POOL +-#include "interface/vcos/vcos_blockpool.h" +-#endif +- +-#if VCOS_HAVE_FILE +-#include "interface/vcos/vcos_file.h" +-#endif +- +-#if VCOS_HAVE_CFG +-#include "interface/vcos/vcos_cfg.h" +-#endif +- +-#if VCOS_HAVE_CMD +-#include "interface/vcos/vcos_cmd.h" +-#endif +- +-#endif /* VCOS_H */ +- +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_assert.h +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vcos/vcos_assert.h 2013-07-26 19:32:07.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,280 +0,0 @@ +-/* +- * Copyright (c) 2010-2011 Broadcom. All rights reserved. +- * +- * This program is free software; you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation; either version 2 of the License, or +- * (at your option) any later version. +- * +- * This program is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with this program; if not, write to the Free Software +- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +- */ +- +-/*============================================================================= +-VideoCore OS Abstraction Layer - Assertion and error-handling macros. +-=============================================================================*/ +- +- +-#ifndef VCOS_ASSERT_H +-#define VCOS_ASSERT_H +- +-/* +- * Macro: +- * vcos_assert(cond) +- * vcos_assert_msg(cond, fmt, ...) +- * Use: +- * Detecting programming errors by ensuring that assumptions are correct. +- * On failure: +- * Performs a platform-dependent "breakpoint", usually with an assert-style +- * message. The '_msg' variant expects a printf-style format string and +- * parameters. +- * If a failure is detected, the code should be fixed and rebuilt. +- * In release builds: +- * Generates no code, i.e. does not evaluate 'cond'. +- * Returns: +- * Nothing. +- * +- * Macro: +- * vcos_demand(cond) +- * vcos_demand_msg(cond, fmt, ...) +- * Use: +- * Detecting fatal system errors that require a reboot. +- * On failure: +- * Performs a platform-dependent "breakpoint", usually with an assert-style +- * message, then calls vcos_abort (see below). +- * In release builds: +- * Calls vcos_abort() if 'cond' is false. +- * Returns: +- * Nothing (never, on failure). +- * +- * Macro: +- * vcos_verify(cond) +- * vcos_verify_msg(cond, fmt, ...) +- * Use: +- * Detecting run-time errors and interesting conditions, normally within an +- * 'if' statement to catch the failures, i.e. +- * if (!vcos_verify(cond)) handle_error(); +- * On failure: +- * Generates a message and optionally stops at a platform-dependent +- * "breakpoint" (usually disabled). See vcos_verify_bkpts_enable below. +- * In release builds: +- * Just evaluates and returns 'cond'. +- * Returns: +- * Non-zero if 'cond' is true, otherwise zero. +- * +- * Macro: +- * vcos_static_assert(cond) +- * Use: +- * Detecting compile-time errors. +- * On failure: +- * Generates a compiler error. +- * In release builds: +- * Generates a compiler error. +- * +- * Function: +- * void vcos_abort(void) +- * Use: +- * Invokes the fatal error handling mechanism, alerting the host where +- * applicable. +- * Returns: +- * Never. +- * +- * Macro: +- * VCOS_VERIFY_BKPTS +- * Use: +- * Define in a module (before including vcos.h) to specify an alternative +- * flag to control breakpoints on vcos_verify() failures. +- * Returns: +- * Non-zero values enable breakpoints. +- * +- * Function: +- * int vcos_verify_bkpts_enable(int enable); +- * Use: +- * Sets the global flag controlling breakpoints on vcos_verify failures, +- * enabling the breakpoints iff 'enable' is non-zero. +- * Returns: +- * The previous state of the flag. +- * +- * Function: +- * int vcos_verify_bkpts_enabled(void); +- * Use: +- * Queries the state of the global flag enabling breakpoints on vcos_verify +- * failures. +- * Returns: +- * The current state of the flag. +- * +- * Examples: +- * +- * int my_breakpoint_enable_flag = 1; +- * +- * #define VCOS_VERIFY_BKPTS my_breakpoint_enable_flag +- * +- * #include "interface/vcos/vcos.h" +- * +- * vcos_static_assert((sizeof(object) % 32) == 0); +- * +- * // ... +- * +- * vcos_assert_msg(postcondition_is_true, "Coding error"); +- * +- * if (!vcos_verify_msg(buf, "Buffer allocation failed (%d bytes)", size)) +- * { +- * // Tidy up +- * // ... +- * return OUT_OF_MEMORY; +- * } +- * +- * vcos_demand(*p++==GUARDWORDHEAP); +- */ +- +-#ifdef __cplusplus +-extern "C" { +-#endif +- +-#include "interface/vcos/vcos_types.h" +- +-#ifdef __COVERITY__ +-#undef VCOS_ASSERT_BKPT +-#define VCOS_ASSERT_BKPT __coverity_panic__() +-#endif +- +-#ifndef VCOS_VERIFY_BKPTS +-#define VCOS_VERIFY_BKPTS vcos_verify_bkpts_enabled() +-#endif +- +-#ifndef VCOS_BKPT +-#if defined(__VIDEOCORE__) && !defined(VCOS_ASSERT_NO_BKPTS) +-#define VCOS_BKPT _bkpt() +-#else +-#define VCOS_BKPT (void )0 +-#endif +-#endif +- +-#ifndef VCOS_ASSERT_BKPT +-#define VCOS_ASSERT_BKPT VCOS_BKPT +-#endif +- +-#ifndef VCOS_VERIFY_BKPT +-#define VCOS_VERIFY_BKPT (VCOS_VERIFY_BKPTS ? VCOS_BKPT : (void)0) +-#endif +- +-VCOSPRE_ int VCOSPOST_ vcos_verify_bkpts_enabled(void); +-VCOSPRE_ int VCOSPOST_ vcos_verify_bkpts_enable(int enable); +-VCOSPRE_ void VCOSPOST_ vcos_abort(void); +- +-#ifndef VCOS_ASSERT_MSG +-#ifdef LOGGING +-extern void logging_assert(const char *file, const char *func, int line, const char *format, ...); +-#define VCOS_ASSERT_MSG(...) ((VCOS_ASSERT_LOGGING && !VCOS_ASSERT_LOGGING_DISABLE) ? logging_assert(__FILE__, __func__, __LINE__, __VA_ARGS__) : (void)0) +-#else +-#define VCOS_ASSERT_MSG(...) ((void)0) +-#endif +-#endif +- +-#ifndef VCOS_VERIFY_MSG +-#define VCOS_VERIFY_MSG(...) VCOS_ASSERT_MSG(__VA_ARGS__) +-#endif +- +-#ifndef VCOS_ASSERT_LOGGING +-#define VCOS_ASSERT_LOGGING 0 +-#endif +- +-#ifndef VCOS_ASSERT_LOGGING_DISABLE +-#define VCOS_ASSERT_LOGGING_DISABLE 0 +-#endif +- +-#if !defined(NDEBUG) || defined(VCOS_RELEASE_ASSERTS) +- +-#ifndef vcos_assert +-#define vcos_assert(cond) \ +- ( (cond) ? (void)0 : (VCOS_ASSERT_MSG("%s", #cond), VCOS_ASSERT_BKPT) ) +-#endif +- +-#ifndef vcos_assert_msg +-#define vcos_assert_msg(cond, ...) \ +- ( (cond) ? (void)0 : (VCOS_ASSERT_MSG(__VA_ARGS__), VCOS_ASSERT_BKPT) ) +-#endif +- +-#else /* !defined(NDEBUG) || defined(VCOS_RELEASE_ASSERTS) */ +- +-#ifndef vcos_assert +-#define vcos_assert(cond) (void)0 +-#endif +- +-#ifndef vcos_assert_msg +-#define vcos_assert_msg(cond, ...) (void)0 +-#endif +- +-#endif /* !defined(NDEBUG) || defined(VCOS_RELEASE_ASSERTS) */ +- +-#if !defined(NDEBUG) +- +-#ifndef vcos_demand +-#define vcos_demand(cond) \ +- ( (cond) ? (void)0 : (VCOS_ASSERT_MSG("%s", #cond), VCOS_ASSERT_BKPT, vcos_abort()) ) +-#endif +- +-#ifndef vcos_demand_msg +-#define vcos_demand_msg(cond, ...) \ +- ( (cond) ? (void)0 : (VCOS_ASSERT_MSG(__VA_ARGS__), VCOS_ASSERT_BKPT, vcos_abort()) ) +-#endif +- +-#ifndef vcos_verify +-#define vcos_verify(cond) \ +- ( (cond) ? 1 : (VCOS_VERIFY_MSG("%s", #cond), VCOS_VERIFY_BKPT, 0) ) +-#endif +- +-#ifndef vcos_verify_msg +-#define vcos_verify_msg(cond, ...) \ +- ( (cond) ? 1 : (VCOS_VERIFY_MSG(__VA_ARGS__), VCOS_VERIFY_BKPT, 0) ) +-#endif +- +-#else /* !defined(NDEBUG) */ +- +-#ifndef vcos_demand +-#define vcos_demand(cond) \ +- ( (cond) ? (void)0 : vcos_abort() ) +-#endif +- +-#ifndef vcos_demand_msg +-#define vcos_demand_msg(cond, ...) \ +- ( (cond) ? (void)0 : vcos_abort() ) +-#endif +- +-#ifndef vcos_verify +-#define vcos_verify(cond) (cond) +-#endif +- +-#ifndef vcos_verify_msg +-#define vcos_verify_msg(cond, ...) (cond) +-#endif +- +-#endif /* !defined(NDEBUG) */ +- +-#ifndef vcos_static_assert +-#if defined(__GNUC__) +-#define vcos_static_assert(cond) __attribute__((unused)) extern int vcos_static_assert[(cond)?1:-1] +-#else +-#define vcos_static_assert(cond) extern int vcos_static_assert[(cond)?1:-1] +-#endif +-#endif +- +-#ifndef vc_assert +-#define vc_assert(cond) vcos_assert(cond) +-#endif +- +-/** Print out a backtrace, on supported platforms. +- */ +-extern void vcos_backtrace_self(void); +- +-#ifdef __cplusplus +-} +-#endif +- +-#endif /* VCOS_ASSERT_H */ +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_atomic_flags.h +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vcos/vcos_atomic_flags.h 2013-07-26 19:32:07.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,83 +0,0 @@ +-/* +- * Copyright (c) 2010-2011 Broadcom. All rights reserved. +- * +- * This program is free software; you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation; either version 2 of the License, or +- * (at your option) any later version. +- * +- * This program is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with this program; if not, write to the Free Software +- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +- */ +- +-/*============================================================================= +-VideoCore OS Abstraction Layer - public header file +-=============================================================================*/ +- +-#ifndef VCOS_ATOMIC_FLAGS_H +-#define VCOS_ATOMIC_FLAGS_H +- +-#ifdef __cplusplus +-extern "C" { +-#endif +- +-#include "interface/vcos/vcos_types.h" +-#include "vcos_platform.h" +- +-/** +- * \file vcos_atomic_flags.h +- * +- * Defines atomic flags API. +- * +- * 32 flags. Atomic "or" and "get and clear" operations +- */ +- +-/** +- * Create an atomic flags instance. +- * +- * @param atomic_flags Pointer to atomic flags instance, filled in on return +- * +- * @return VCOS_SUCCESS if succeeded. +- */ +-VCOS_INLINE_DECL +-VCOS_STATUS_T vcos_atomic_flags_create(VCOS_ATOMIC_FLAGS_T *atomic_flags); +- +-/** +- * Atomically set the specified flags. +- * +- * @param atomic_flags Instance to set flags on +- * @param flags Mask of flags to set +- */ +-VCOS_INLINE_DECL +-void vcos_atomic_flags_or(VCOS_ATOMIC_FLAGS_T *atomic_flags, uint32_t flags); +- +-/** +- * Retrieve the current flags and then clear them. The entire operation is +- * atomic. +- * +- * @param atomic_flags Instance to get/clear flags from/on +- * +- * @return Mask of flags which were set (and we cleared) +- */ +-VCOS_INLINE_DECL +-uint32_t vcos_atomic_flags_get_and_clear(VCOS_ATOMIC_FLAGS_T *atomic_flags); +- +-/** +- * Delete an atomic flags instance. +- * +- * @param atomic_flags Instance to delete +- */ +-VCOS_INLINE_DECL +-void vcos_atomic_flags_delete(VCOS_ATOMIC_FLAGS_T *atomic_flags); +- +-#ifdef __cplusplus +-} +-#endif +- +-#endif +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_build_info.h +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vcos/vcos_build_info.h 2013-07-26 19:32:07.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,23 +0,0 @@ +-/* +- * Copyright (c) 2010-2011 Broadcom. All rights reserved. +- * +- * This program is free software; you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation; either version 2 of the License, or +- * (at your option) any later version. +- * +- * This program is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with this program; if not, write to the Free Software +- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +- */ +- +-const char *vcos_get_build_hostname( void ); +-const char *vcos_get_build_version( void ); +-const char *vcos_get_build_time( void ); +-const char *vcos_get_build_date( void ); +- +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_cfg.h +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vcos/vcos_cfg.h 2013-07-26 19:32:00.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,113 +0,0 @@ +-/***************************************************************************** +-* Copyright 2009 - 2011 Broadcom Corporation. All rights reserved. +-* +-* Unless you and Broadcom execute a separate written software license +-* agreement governing use of this software, this software is licensed to you +-* under the terms of the GNU General Public License version 2, available at +-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). +-* +-* Notwithstanding the above, under no circumstances may you combine this +-* software in any way with any other Broadcom software provided under a +-* license other than the GPL, without Broadcom's express prior written +-* consent. +-*****************************************************************************/ +- +-#if !defined( VCOS_CFG_H ) +-#define VCOS_CFG_H +- +-#ifdef __cplusplus +-extern "C" { +-#endif +- +-#include "interface/vcos/vcos_types.h" +-#include "vcos_platform.h" +- +-typedef struct opaque_vcos_cfg_buf_t *VCOS_CFG_BUF_T; +-typedef struct opaque_vcos_cfg_entry_t *VCOS_CFG_ENTRY_T; +- +-/** \file vcos_file.h +- * +- * API for accessing configuration/statistics information. This +- * is loosely modelled on the linux proc entries. +- */ +- +-typedef void (*VCOS_CFG_SHOW_FPTR)( VCOS_CFG_BUF_T buf, void *data ); +-typedef void (*VCOS_CFG_PARSE_FPTR)( VCOS_CFG_BUF_T buf, void *data ); +- +-/** Create a configuration directory. +- * +- * @param entry Place to store the created config entry. +- * @param parent Parent entry (for directory like config +- * options). +- * @param entryName Name of the directory. +- */ +- +-VCOS_STATUS_T vcos_cfg_mkdir( VCOS_CFG_ENTRY_T *entry, +- VCOS_CFG_ENTRY_T *parent, +- const char *dirName ); +- +-/** Create a configuration entry. +- * +- * @param entry Place to store the created config entry. +- * @param parent Parent entry (for directory like config +- * options). +- * @param entryName Name of the configuration entry. +- * @param showFunc Function pointer to show configuration +- * data. +- * @param parseFunc Function pointer to parse new data. +- */ +- +-VCOS_STATUS_T vcos_cfg_create_entry( VCOS_CFG_ENTRY_T *entry, +- VCOS_CFG_ENTRY_T *parent, +- const char *entryName, +- VCOS_CFG_SHOW_FPTR showFunc, +- VCOS_CFG_PARSE_FPTR parseFunc, +- void *data ); +- +-/** Determines if a configuration entry has been created or not. +- * +- * @param entry Configuration entry to query. +- */ +- +-int vcos_cfg_is_entry_created( VCOS_CFG_ENTRY_T entry ); +- +-/** Returns the name of a configuration entry. +- * +- * @param entry Configuration entry to query. +- */ +- +-const char *vcos_cfg_get_entry_name( VCOS_CFG_ENTRY_T entry ); +- +-/** Removes a configuration entry. +- * +- * @param entry Configuration entry to remove. +- */ +- +-VCOS_STATUS_T vcos_cfg_remove_entry( VCOS_CFG_ENTRY_T *entry ); +- +- +-/** Writes data into a configuration buffer. Only valid inside +- * the show function. +- * +- * @param buf Buffer to write data into. +- * @param fmt printf style format string. +- */ +- +-void vcos_cfg_buf_printf( VCOS_CFG_BUF_T buf, const char *fmt, ... ); +- +-/** Retrieves a null terminated string of the data associated +- * with the buffer. Only valid inside the parse function. +- * +- * @param buf Buffer to get data from. +- * @param fmt printf style format string. +- */ +- +-char *vcos_cfg_buf_get_str( VCOS_CFG_BUF_T buf ); +- +-void *vcos_cfg_get_proc_entry( VCOS_CFG_ENTRY_T entry ); +- +-#ifdef __cplusplus +-} +-#endif +-#endif +- +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_cmd.h +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vcos/vcos_cmd.h 2013-07-26 19:32:00.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,98 +0,0 @@ +-/***************************************************************************** +-* Copyright 2009 - 2011 Broadcom Corporation. All rights reserved. +-* +-* Unless you and Broadcom execute a separate written software license +-* agreement governing use of this software, this software is licensed to you +-* under the terms of the GNU General Public License version 2, available at +-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). +-* +-* Notwithstanding the above, under no circumstances may you combine this +-* software in any way with any other Broadcom software provided under a +-* license other than the GPL, without Broadcom's express prior written +-* consent. +-*****************************************************************************/ +- +-#if !defined( VCOS_CMD_H ) +-#define VCOS_CMD_H +- +-/* ---- Include Files ----------------------------------------------------- */ +- +-#include "interface/vcos/vcos.h" +-#include "interface/vcos/vcos_stdint.h" +- +- +-/* ---- Constants and Types ---------------------------------------------- */ +- +-struct VCOS_CMD_S; +-typedef struct VCOS_CMD_S VCOS_CMD_T; +- +-typedef struct +-{ +- int argc; /* Number of arguments (includes the command/sub-command) */ +- char **argv; /* Array of arguments */ +- char **argv_orig; /* Original array of arguments */ +- +- VCOS_CMD_T *cmd_entry; +- VCOS_CMD_T *cmd_parent_entry; +- +- int use_log; /* Output being logged? */ +- size_t result_size; /* Size of result buffer. */ +- char *result_ptr; /* Next place to put output. */ +- char *result_buf; /* Start of the buffer. */ +- +-} VCOS_CMD_PARAM_T; +- +-typedef VCOS_STATUS_T (*VCOS_CMD_FUNC_T)( VCOS_CMD_PARAM_T *param ); +- +-struct VCOS_CMD_S +-{ +- const char *name; +- const char *args; +- VCOS_CMD_FUNC_T cmd_fn; +- VCOS_CMD_T *sub_cmd_entry; +- const char *descr; +- +-}; +- +-/* ---- Variable Externs ------------------------------------------------- */ +- +-/* ---- Function Prototypes ---------------------------------------------- */ +- +-/* +- * Common printing routine for generating command output. +- */ +-VCOSPRE_ void VCOSPOST_ vcos_cmd_error( VCOS_CMD_PARAM_T *param, const char *fmt, ... ) VCOS_FORMAT_ATTR_(printf, 2, 3); +-VCOSPRE_ void VCOSPOST_ vcos_cmd_printf( VCOS_CMD_PARAM_T *param, const char *fmt, ... ) VCOS_FORMAT_ATTR_(printf, 2, 3); +-VCOSPRE_ void VCOSPOST_ vcos_cmd_vprintf( VCOS_CMD_PARAM_T *param, const char *fmt, va_list args ) VCOS_FORMAT_ATTR_(printf, 2, 0); +- +-/* +- * Cause vcos_cmd_error, printf and vprintf to always log to the provided +- * category. When this call is made, the results buffer passed into +- * vcos_cmd_execute is used as a line buffer and does not need to be +- * output by the caller. +- */ +-VCOSPRE_ void VCOSPOST_ vcos_cmd_always_log_output( VCOS_LOG_CAT_T *log_category ); +- +-/* +- * Prints command usage for the current command. +- */ +-VCOSPRE_ void VCOSPOST_ vcos_cmd_usage( VCOS_CMD_PARAM_T *param ); +- +-/* +- * Register commands to be processed +- */ +-VCOSPRE_ VCOS_STATUS_T VCOSPOST_ vcos_cmd_register( VCOS_CMD_T *cmd_entry ); +- +-/* +- * Registers multiple commands to be processed. The array should +- * be terminated by an entry with all zeros. +- */ +-VCOSPRE_ VCOS_STATUS_T VCOSPOST_ vcos_cmd_register_multiple( VCOS_CMD_T *cmd_entry ); +- +-/* +- * Executes a command based on a command line. +- */ +-VCOSPRE_ VCOS_STATUS_T VCOSPOST_ vcos_cmd_execute( int argc, char **argv, size_t result_size, char *result_buf ); +- +-#endif /* VCOS_CMD_H */ +- +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_ctype.h +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vcos/vcos_ctype.h 2013-07-26 19:32:07.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,40 +0,0 @@ +-/* +- * Copyright (c) 2010-2011 Broadcom. All rights reserved. +- * +- * This program is free software; you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation; either version 2 of the License, or +- * (at your option) any later version. +- * +- * This program is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with this program; if not, write to the Free Software +- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +- */ +- +-/*============================================================================= +-VideoCore OS Abstraction Layer - public header file +-=============================================================================*/ +- +-#ifndef VCOS_CTYPE_H +-#define VCOS_CTYPE_H +- +-/** +- * \file +- * +- * ctype functions. +- * +- */ +- +-#ifdef __KERNEL__ +-#include +-#else +-#include +-#endif +- +-#endif +- +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_dlfcn.h +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vcos/vcos_dlfcn.h 2013-07-26 19:32:07.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,80 +0,0 @@ +-/* +- * Copyright (c) 2010-2011 Broadcom. All rights reserved. +- * +- * This program is free software; you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation; either version 2 of the License, or +- * (at your option) any later version. +- * +- * This program is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with this program; if not, write to the Free Software +- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +- */ +- +-/*============================================================================= +-VCOS - abstraction over dynamic library opening +-=============================================================================*/ +- +-#ifndef VCOS_DLFCN_H +-#define VCOS_DLFCN_H +- +-#include "interface/vcos/vcos_types.h" +-#include "vcos_platform.h" +- +-#ifdef __cplusplus +-extern "C" { +-#endif +- +-#define VCOS_DL_LAZY 1 +-#define VCOS_DL_NOW 2 +- +-/** +- * \file +- * +- * Loading dynamic libraries. See also dlfcn.h. +- */ +- +-/** Open a dynamic library. +- * +- * @param name name of the library +- * @param mode Load lazily or immediately (VCOS_DL_LAZY, VCOS_DL_NOW). +- * +- * @return A handle for use in subsequent calls. +- */ +-VCOSPRE_ void * VCOSPOST_ vcos_dlopen(const char *name, int mode); +- +-/** Look up a symbol. +- * +- * @param handle Handle to open +- * @param name Name of function +- * +- * @return Function pointer, or NULL. +- */ +-VCOSPRE_ void VCOSPOST_ (*vcos_dlsym(void *handle, const char *name))(void); +- +-/** Close a library +- * +- * @param handle Handle to close +- */ +-VCOSPRE_ int VCOSPOST_ vcos_dlclose (void *handle); +- +-/** Return error message from library. +- * +- * @param err On return, set to non-zero if an error has occurred +- * @param buf Buffer to write error to +- * @param len Size of buffer (including terminating NUL). +- */ +-VCOSPRE_ int VCOSPOST_ vcos_dlerror(int *err, char *buf, size_t buflen); +- +- +-#ifdef __cplusplus +-} +-#endif +-#endif +- +- +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_event.h +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vcos/vcos_event.h 2013-07-26 19:32:07.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,108 +0,0 @@ +-/* +- * Copyright (c) 2010-2011 Broadcom. All rights reserved. +- * +- * This program is free software; you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation; either version 2 of the License, or +- * (at your option) any later version. +- * +- * This program is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with this program; if not, write to the Free Software +- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +- */ +- +-/*============================================================================= +-VideoCore OS Abstraction Layer - public header file for events +-=============================================================================*/ +- +-#ifndef VCOS_EVENT_H +-#define VCOS_EVENT_H +- +-#ifdef __cplusplus +-extern "C" { +-#endif +- +-#include "interface/vcos/vcos_types.h" +-#include "vcos_platform.h" +- +-/** +- * \file +- * +- * An event is akin to the Win32 auto-reset event. +- * +- * +- * Signalling an event will wake up one waiting thread only. Once one +- * thread has been woken the event atomically returns to the unsignalled +- * state. +- * +- * If no threads are waiting on the event when it is signalled it remains +- * signalled. +- * +- * This is almost, but not quite, completely unlike the "event flags" +- * object based on Nucleus event groups and ThreadX event flags. +- * +- * In particular, it should be similar in speed to a semaphore, unlike +- * the event flags. +- */ +- +-/** +- * Create an event instance. +- * +- * @param event Filled in with constructed event. +- * @param name Name of the event (for debugging) +- * +- * @return VCOS_SUCCESS on success, or error code. +- */ +-VCOS_INLINE_DECL +-VCOS_STATUS_T vcos_event_create(VCOS_EVENT_T *event, const char *name); +- +-#ifndef vcos_event_signal +- +-/** +- * Signal the event. The event will return to being unsignalled +- * after exactly one waiting thread has been woken up. If no +- * threads are waiting it remains signalled. +- * +- * @param event The event to signal +- */ +-VCOS_INLINE_DECL +-void vcos_event_signal(VCOS_EVENT_T *event); +- +-/** +- * Wait for the event. +- * +- * @param event The event to wait for +- * @return VCOS_SUCCESS on success, VCOS_EAGAIN if the wait was interrupted. +- */ +-VCOS_INLINE_DECL +-VCOS_STATUS_T vcos_event_wait(VCOS_EVENT_T *event); +- +-/** +- * Try event, but don't block. +- * +- * @param event The event to try +- * @return VCOS_SUCCESS on success, VCOS_EAGAIN if the event is not currently signalled +- */ +-VCOS_INLINE_DECL +-VCOS_STATUS_T vcos_event_try(VCOS_EVENT_T *event); +- +-#endif +- +-/* +- * Destroy an event. +- */ +-VCOS_INLINE_DECL +-void vcos_event_delete(VCOS_EVENT_T *event); +- +-#ifdef __cplusplus +-} +-#endif +- +-#endif +- +- +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_event_flags.h +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vcos/vcos_event_flags.h 2013-07-26 19:32:07.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,109 +0,0 @@ +-/* +- * Copyright (c) 2010-2011 Broadcom. All rights reserved. +- * +- * This program is free software; you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation; either version 2 of the License, or +- * (at your option) any later version. +- * +- * This program is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with this program; if not, write to the Free Software +- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +- */ +- +-/*============================================================================= +-VideoCore OS Abstraction Layer - public header file +-=============================================================================*/ +- +-#ifndef VCOS_EVENT_FLAGS_H +-#define VCOS_EVENT_FLAGS_H +- +- +-#ifdef __cplusplus +-extern "C" { +-#endif +- +-#include "interface/vcos/vcos_types.h" +-#include "vcos_platform.h" +- +-#define VCOS_EVENT_FLAGS_SUSPEND VCOS_SUSPEND +-#define VCOS_EVENT_FLAGS_NO_SUSPEND VCOS_NO_SUSPEND +-typedef VCOS_OPTION VCOS_EVENTGROUP_OPERATION_T; +- +-/** +- * \file vcos_event_flags.h +- * +- * Defines event flags API. +- * +- * Similar to Nucleus event groups. +- * +- * These have the same semantics as Nucleus event groups and ThreadX event +- * flags. As such, they are quite complex internally; if speed is important +- * they might not be your best choice. +- * +- */ +- +-/** +- * Create an event flags instance. +- * +- * @param flags Pointer to event flags instance, filled in on return. +- * @param name Name for the event flags, used for debug. +- * +- * @return VCOS_SUCCESS if succeeded. +- */ +- +-VCOS_INLINE_DECL +-VCOS_STATUS_T vcos_event_flags_create(VCOS_EVENT_FLAGS_T *flags, const char *name); +- +-/** +- * Set some events. +- * +- * @param flags Instance to set flags on +- * @param events Bitmask of the flags to actually set +- * @param op How the flags should be set. VCOS_OR will OR in the flags; VCOS_AND +- * will AND them in, possibly clearing existing flags. +- */ +-VCOS_INLINE_DECL +-void vcos_event_flags_set(VCOS_EVENT_FLAGS_T *flags, +- VCOS_UNSIGNED events, +- VCOS_OPTION op); +- +-/** +- * Retrieve some events. +- * +- * Waits until the specified events have been set. +- * +- * @param flags Instance to wait on +- * @param requested_events The bitmask to wait for +- * @param op VCOS_OR - get any; VCOS_AND - get all. +- * @param ms_suspend How long to wait, in milliseconds +- * @param retrieved_events the events actually retrieved. +- * +- * @return VCOS_SUCCESS if events were retrieved. VCOS_EAGAIN if the +- * timeout expired. +- */ +-VCOS_INLINE_DECL +-VCOS_STATUS_T vcos_event_flags_get(VCOS_EVENT_FLAGS_T *flags, +- VCOS_UNSIGNED requested_events, +- VCOS_OPTION op, +- VCOS_UNSIGNED ms_suspend, +- VCOS_UNSIGNED *retrieved_events); +- +- +-/** +- * Delete an event flags instance. +- */ +-VCOS_INLINE_DECL +-void vcos_event_flags_delete(VCOS_EVENT_FLAGS_T *); +- +-#ifdef __cplusplus +-} +-#endif +- +-#endif +- +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_init.h +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vcos/vcos_init.h 2013-07-26 19:32:07.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,54 +0,0 @@ +-/* +- * Copyright (c) 2010-2011 Broadcom. All rights reserved. +- * +- * This program is free software; you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation; either version 2 of the License, or +- * (at your option) any later version. +- * +- * This program is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with this program; if not, write to the Free Software +- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +- */ +- +-/*============================================================================= +-VideoCore OS Abstraction Layer - initialization routines +-=============================================================================*/ +- +- +-#include "interface/vcos/vcos_types.h" +-#include "vcos_platform.h" +- +-#ifdef __cplusplus +-extern "C" { +-#endif +- +-/** \file +- * +- * Some OS support libraries need some initialization. To support this, call this +- * function at the start of day. +- */ +- +-VCOSPRE_ VCOS_STATUS_T VCOSPOST_ vcos_init(void); +-VCOSPRE_ void VCOSPOST_ vcos_deinit(void); +-VCOSPRE_ void VCOSPOST_ vcos_global_lock(void); +-VCOSPRE_ void VCOSPOST_ vcos_global_unlock(void); +- +-/** Pass in the argv/argc arguments passed to main() */ +-VCOSPRE_ void VCOSPOST_ vcos_set_args(int argc, const char **argv); +- +-/** Return argc. */ +-VCOSPRE_ int VCOSPOST_ vcos_get_argc(void); +- +-/** Return argv. */ +-VCOSPRE_ const char ** VCOSPOST_ vcos_get_argv(void); +- +-#ifdef __cplusplus +-} +-#endif +- +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_logging.h +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vcos/vcos_logging.h 2013-07-26 19:32:07.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,290 +0,0 @@ +-/* +- * Copyright (c) 2010-2011 Broadcom. All rights reserved. +- * +- * This program is free software; you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation; either version 2 of the License, or +- * (at your option) any later version. +- * +- * This program is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with this program; if not, write to the Free Software +- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +- */ +- +-/*============================================================================= +-VideoCore OS Abstraction Layer - logging support +-=============================================================================*/ +- +-#ifndef VCOS_LOGGING_H +-#define VCOS_LOGGING_H +- +-#ifdef __cplusplus +-extern "C" { +-#endif +- +-#include +- +-#include "interface/vcos/vcos_types.h" +-#include "vcos_platform.h" +- +-/** +- * \file +- * +- * Logging support +- * +- * This provides categorised logging. Clients register +- * a category, and then get a number of logging levels for +- * that category. +- * +- * The logging level flag is tested using a flag *before* the +- * function call, which makes logging very fast when disabled - there +- * is no function call overhead just to find out that this log +- * message is disabled. +- * +- * \section VCOS_LOG_CATEGORY +- * +- * As a convenience, clients define VCOS_LOG_CATEGORY to point to +- * their category; the various vcos_log_xxx() macros then expand to +- * use this. +- * +- * e.g. +- * +- * #define VCOS_LOG_CATEGORY (&my_category) +- * +- * #include +- * +- * VCOS_LOG_CAT_T my_category; +- * +- * .... +- * +- * vcos_log_trace("Stuff happened: %d", n_stuff); +- * +- */ +- +-/** Logging levels */ +-typedef enum VCOS_LOG_LEVEL_T +-{ +- VCOS_LOG_UNINITIALIZED = 0, +- VCOS_LOG_NEVER, +- VCOS_LOG_ERROR, +- VCOS_LOG_WARN, +- VCOS_LOG_INFO, +- VCOS_LOG_TRACE, +-} VCOS_LOG_LEVEL_T; +- +- +-/** Initialize a logging category without going through vcos_log_register(). +- * +- * This is useful for the case where there is no obvious point to do the +- * registration (no initialization function for the module). However, it +- * means that your logging category is not registered, so cannot be easily +- * changed at run-time. +- */ +-#define VCOS_LOG_INIT(n,l) { l, n, 0, {0}, 0, 0 } +- +-/** A registered logging category. +- */ +-typedef struct VCOS_LOG_CAT_T +-{ +- VCOS_LOG_LEVEL_T level; /** Which levels are enabled for this category */ +- const char *name; /** Name for this category. */ +- struct VCOS_LOG_CAT_T *next; +- struct { +- unsigned int want_prefix:1; +- } flags; +- unsigned int refcount; +- void *platform_data; /** platform specific data */ +-} VCOS_LOG_CAT_T; +- +-typedef void (*VCOS_VLOG_IMPL_FUNC_T)(const VCOS_LOG_CAT_T *cat, VCOS_LOG_LEVEL_T _level, const char *fmt, va_list args); +- +-/** Convert a VCOS_LOG_LEVEL_T into a printable string. +- * The platform needs to implement this function. +- */ +-VCOSPRE_ const char * VCOSPOST_ vcos_log_level_to_string( VCOS_LOG_LEVEL_T level ); +- +-/** Convert a string into a VCOS_LOG_LEVEL_T +- * The platform needs to implement this function. +- */ +-VCOSPRE_ VCOS_STATUS_T VCOSPOST_ vcos_string_to_log_level( const char *str, VCOS_LOG_LEVEL_T *level ); +- +-/** Log a message. Basic API. Normal code should not use this. +- * The platform needs to implement this function. +- */ +-VCOSPRE_ void VCOSPOST_ vcos_log_impl(const VCOS_LOG_CAT_T *cat, VCOS_LOG_LEVEL_T _level, const char *fmt, ...) VCOS_FORMAT_ATTR_(printf, 3, 4); +- +-/** Log a message using a varargs parameter list. Normal code should +- * not use this. +- */ +-VCOSPRE_ void VCOSPOST_ vcos_vlog_impl(const VCOS_LOG_CAT_T *cat, VCOS_LOG_LEVEL_T _level, const char *fmt, va_list args) VCOS_FORMAT_ATTR_(printf, 3, 0); +- +-/** Set the function which does the actual logging output. +- * Passing in NULL causes the default logging function to be +- * used. +- */ +-VCOSPRE_ void VCOSPOST_ vcos_set_vlog_impl( VCOS_VLOG_IMPL_FUNC_T vlog_impl_func ); +- +-/** The default logging function, which is provided by each +- * platform. +- */ +- +-VCOSPRE_ void VCOSPOST_ vcos_vlog_default_impl(const VCOS_LOG_CAT_T *cat, VCOS_LOG_LEVEL_T _level, const char *fmt, va_list args) VCOS_FORMAT_ATTR_(printf, 3, 0); +- +-/* +- * Initialise the logging subsystem. This is called from +- * vcos_init() so you don't normally need to call it. +- */ +-VCOSPRE_ void VCOSPOST_ vcos_logging_init(void); +- +-/** Register a logging category. +- * +- * @param name the name of this category. +- * @param category the category to register. +- */ +-VCOSPRE_ void VCOSPOST_ vcos_log_register(const char *name, VCOS_LOG_CAT_T *category); +- +-/** Unregister a logging category. +- */ +-VCOSPRE_ void VCOSPOST_ vcos_log_unregister(VCOS_LOG_CAT_T *category); +- +-/** Return a default logging category, for people too lazy to create their own. +- * +- * Using the default category will be slow (there's an extra function +- * call overhead). Don't do this in normal code. +- */ +-VCOSPRE_ const VCOS_LOG_CAT_T * VCOSPOST_ vcos_log_get_default_category(void); +- +-VCOSPRE_ void VCOSPOST_ vcos_set_log_options(const char *opt); +- +-/** Set the logging level for a category at run time. Without this, the level +- * will be that set by vcos_log_register from a platform-specific source. +- * +- * @param category the category to modify. +- * @param level the new logging level for this category. +- */ +-VCOS_STATIC_INLINE void vcos_log_set_level(VCOS_LOG_CAT_T *category, VCOS_LOG_LEVEL_T level) +-{ +- category->level = level; +-} +- +-#define vcos_log_dump_mem(cat,label,addr,voidMem,numBytes) do { if (vcos_is_log_enabled(cat,VCOS_LOG_TRACE)) vcos_log_dump_mem_impl(cat,label,addr,voidMem,numBytes); } while (0) +- +-void vcos_log_dump_mem_impl( const VCOS_LOG_CAT_T *cat, +- const char *label, +- uint32_t addr, +- const void *voidMem, +- size_t numBytes ); +- +-/* +- * Platform specific hooks (optional). +- */ +-#ifndef vcos_log_platform_init +-#define vcos_log_platform_init() (void)0 +-#endif +- +-#ifndef vcos_log_platform_register +-#define vcos_log_platform_register(category) (void)0 +-#endif +- +-#ifndef vcos_log_platform_unregister +-#define vcos_log_platform_unregister(category) (void)0 +-#endif +- +-/* VCOS_TRACE() - deprecated macro which just outputs in a debug build and +- * is a no-op in a release build. +- * +- * _VCOS_LOG_X() - internal macro which outputs if the current level for the +- * particular category is higher than the supplied message level. +- */ +- +-#define VCOS_LOG_DFLT_CATEGORY vcos_log_get_default_category() +- +-#define _VCOS_LEVEL(x) (x) +- +-#define vcos_is_log_enabled(cat,_level) (_VCOS_LEVEL((cat)->level) >= _VCOS_LEVEL(_level)) +- +-#if defined(_VCOS_METAWARE) || defined(__GNUC__) +- +-# if !defined(NDEBUG) || defined(VCOS_ALWAYS_WANT_LOGGING) +-# define VCOS_LOGGING_ENABLED +-# define _VCOS_LOG_X(cat, _level, fmt...) do { if (vcos_is_log_enabled(cat,_level)) vcos_log_impl(cat,_level,fmt); } while (0) +-# define _VCOS_VLOG_X(cat, _level, fmt, ap) do { if (vcos_is_log_enabled(cat,_level)) vcos_vlog_impl(cat,_level,fmt,ap); } while (0) +-# else +-# define _VCOS_LOG_X(cat, _level, fmt...) (void)0 +-# define _VCOS_VLOG_X(cat, _level, fmt, ap) (void)0 +-# endif +- +- +- +-# define vcos_log_error(...) _VCOS_LOG_X(VCOS_LOG_CATEGORY, VCOS_LOG_ERROR, __VA_ARGS__) +-# define vcos_log_warn(...) _VCOS_LOG_X(VCOS_LOG_CATEGORY, VCOS_LOG_WARN, __VA_ARGS__) +-# define vcos_log_info(...) _VCOS_LOG_X(VCOS_LOG_CATEGORY, VCOS_LOG_INFO, __VA_ARGS__) +-# define vcos_log_trace(...) _VCOS_LOG_X(VCOS_LOG_CATEGORY, VCOS_LOG_TRACE, __VA_ARGS__) +- +-# define vcos_vlog_error(fmt,ap) _VCOS_VLOG_X(VCOS_LOG_CATEGORY, VCOS_LOG_ERROR, fmt, ap) +-# define vcos_vlog_warn(fmt,ap) _VCOS_VLOG_X(VCOS_LOG_CATEGORY, VCOS_LOG_WARN, fmt, ap) +-# define vcos_vlog_info(fmt,ap) _VCOS_VLOG_X(VCOS_LOG_CATEGORY, VCOS_LOG_INFO, fmt, ap) +-# define vcos_vlog_trace(fmt,ap) _VCOS_VLOG_X(VCOS_LOG_CATEGORY, VCOS_LOG_TRACE, fmt, ap) +- +-# define vcos_log(...) _VCOS_LOG_X(VCOS_LOG_DFLT_CATEGORY, VCOS_LOG_INFO, __VA_ARGS__) +-# define vcos_vlog(fmt,ap) _VCOS_VLOG_X(VCOS_LOG_DFLT_CATEGORY, VCOS_LOG_INFO, fmt, ap) +-# define VCOS_ALERT(...) _VCOS_LOG_X(VCOS_LOG_DFLT_CATEGORY, VCOS_LOG_ERROR, __VA_ARGS__) +-# define VCOS_TRACE(...) _VCOS_LOG_X(VCOS_LOG_DFLT_CATEGORY, VCOS_LOG_INFO, __VA_ARGS__) +- +-/* +- * MS Visual Studio - pre 2005 does not grok variadic macros +- */ +-#elif defined(_MSC_VER) +- +-# if _MSC_VER >= 1400 +- +-# if !defined(NDEBUG) || defined(VCOS_ALWAYS_WANT_LOGGING) +-# define VCOS_LOGGING_ENABLED +-# define _VCOS_LOG_X(cat, _level, fmt,...) do { if (vcos_is_log_enabled(cat,_level)) vcos_log_impl(cat, _level, fmt, __VA_ARGS__); } while (0) +-# else +-# define _VCOS_LOG_X(cat, _level, fmt,...) (void)0 +-# endif +- +-# define vcos_log_error(fmt,...) _VCOS_LOG_X(VCOS_LOG_CATEGORY, VCOS_LOG_ERROR, fmt, __VA_ARGS__) +-# define vcos_log_warn(fmt,...) _VCOS_LOG_X(VCOS_LOG_CATEGORY, VCOS_LOG_WARN, fmt, __VA_ARGS__) +-# define vcos_log_info(fmt,...) _VCOS_LOG_X(VCOS_LOG_CATEGORY, VCOS_LOG_INFO, fmt, __VA_ARGS__) +-# define vcos_log_trace(fmt,...) _VCOS_LOG_X(VCOS_LOG_CATEGORY, VCOS_LOG_TRACE, fmt, __VA_ARGS__) +- +-# define vcos_log(fmt,...) _VCOS_LOG_X(VCOS_LOG_DFLT_CATEGORY, VCOS_LOG_INFO, fmt) +-# define VCOS_ALERT(fmt,...) _VCOS_LOG_X(VCOS_LOG_DFLT_CATEGORY, VCOS_LOG_ERROR, fmt) +-# define VCOS_TRACE(fmt,...) _VCOS_LOG_X(VCOS_LOG_DFLT_CATEGORY, VCOS_LOG_INFO, fmt) +- +-# else /* _MSC_VER >= 1400 */ +- +-/* do not define these */ +- +-# endif /* _MSC_VER >= 1400 */ +- +-#endif +- +-#if VCOS_HAVE_CMD +- +-#include "interface/vcos/vcos_cmd.h" +- +-/* +- * These are the log sub-commands. They're exported here for user-mode apps which +- * may want to call these, since the "log" command isn't registered for user-mode +- * apps (vcdbg for example, has its own log command). +- */ +-VCOSPRE_ VCOS_STATUS_T VCOSPOST_ vcos_log_assert_cmd( VCOS_CMD_PARAM_T *param ); +-VCOSPRE_ VCOS_STATUS_T VCOSPOST_ vcos_log_set_cmd( VCOS_CMD_PARAM_T *param ); +-VCOSPRE_ VCOS_STATUS_T VCOSPOST_ vcos_log_status_cmd( VCOS_CMD_PARAM_T *param ); +-VCOSPRE_ VCOS_STATUS_T VCOSPOST_ vcos_log_test_cmd( VCOS_CMD_PARAM_T *param ); +-#endif +- +-#ifdef __cplusplus +-} +-#endif +-#endif /* VCOS_LOGGING_H */ +- +- +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_lowlevel_thread.h +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vcos/vcos_lowlevel_thread.h 2013-07-26 19:32:07.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,118 +0,0 @@ +-/* +- * Copyright (c) 2010-2011 Broadcom. All rights reserved. +- * +- * This program is free software; you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation; either version 2 of the License, or +- * (at your option) any later version. +- * +- * This program is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with this program; if not, write to the Free Software +- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +- */ +- +-/*============================================================================= +-VideoCore OS Abstraction Layer - low level thread support +-=============================================================================*/ +- +-#ifndef VCOS_LOWLEVEL_THREAD_H +-#define VCOS_LOWLEVEL_THREAD_H +- +-#ifdef __cplusplus +-extern "C" { +-#endif +- +-#include "interface/vcos/vcos_types.h" +-#include "vcos_platform.h" +- +-/** +- * \file +- * +- * This defines a low level thread API that is supported by *some* operating systems +- * and can be used to construct the regular "joinable thread" API on those operating +- * systems. +- * +- * Most clients will not need to use this code. +- * +- * \sa vcos_joinable_thread.h +- */ +- +-/** +- * \brief Create a thread. +- * +- * This creates a thread which can be stopped either by returning from the +- * entry point function or by calling vcos_llthread_exit from within the entry +- * point function. The thread must be cleaned up by calling +- * vcos_llthread_delete. vcos_llthread_delete may or may not terminate the +- * thread. +- * +- * The preemptible parameter familiar from Nucleus is removed, as it is unused in +- * VideoCore code. Affinity is added, since we do use this. +- * +- * @param thread Filled in with thread instance +- * @param name An optional name for the thread. "" may be used (but +- * a name will aid in debugging). +- * @param entry Entry point +- * @param arg A single argument passed to the entry point function +- * @param stack Pointer to stack address +- * @param stacksz Size of stack in bytes +- * @param priority Priority of task, between VCOS_PRI_LOW and VCOS_PRI_HIGH +- * @param affinity CPU affinity +- * +- * @sa vcos_llthread_terminate vcos_llthread_delete +- */ +-VCOSPRE_ VCOS_STATUS_T VCOSPOST_ vcos_llthread_create(VCOS_LLTHREAD_T *thread, +- const char *name, +- VCOS_LLTHREAD_ENTRY_FN_T entry, +- void *arg, +- void *stack, +- VCOS_UNSIGNED stacksz, +- VCOS_UNSIGNED priority, +- VCOS_UNSIGNED affinity, +- VCOS_UNSIGNED timeslice, +- VCOS_UNSIGNED autostart); +- +-/** +- * \brief Exits the current thread. +- */ +-VCOSPRE_ void VCOSPOST_ vcos_llthread_exit(void); +- +-/** +- * \brief Delete a thread. This must be called to cleanup after +- * vcos_llthread_create. This may or may not terminate the thread. +- * It does not clean up any resources that may have been +- * allocated by the thread. +- */ +-VCOSPRE_ void VCOSPOST_ vcos_llthread_delete(VCOS_LLTHREAD_T *thread); +- +-/** +- * \brief Return current lowlevel thread pointer. +- */ +-VCOS_INLINE_DECL +-VCOS_LLTHREAD_T *vcos_llthread_current(void); +- +-/** +- * Resume a thread. +- */ +-VCOS_INLINE_DECL +-void vcos_llthread_resume(VCOS_LLTHREAD_T *thread); +- +-VCOSPRE_ int VCOSPOST_ vcos_llthread_running(VCOS_LLTHREAD_T *thread); +- +-/** +- * \brief Create a VCOS_LLTHREAD_T for the current thread. This is so we can +- * have VCOS_LLTHREAD_Ts even for threads not originally created by VCOS (eg +- * the thread that calls vcos_init). +- */ +-extern VCOS_STATUS_T _vcos_llthread_create_attach(VCOS_LLTHREAD_T *thread); +- +-#ifdef __cplusplus +-} +-#endif +-#endif +- +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_mem.h +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vcos/vcos_mem.h 2013-07-26 19:32:07.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,92 +0,0 @@ +-/* +- * Copyright (c) 2010-2011 Broadcom. All rights reserved. +- * +- * This program is free software; you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation; either version 2 of the License, or +- * (at your option) any later version. +- * +- * This program is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with this program; if not, write to the Free Software +- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +- */ +- +-/*============================================================================= +-VideoCore OS Abstraction Layer - memory support +-=============================================================================*/ +- +-#ifndef VCOS_MEM_H +-#define VCOS_MEM_H +- +-#ifdef __cplusplus +-extern "C" { +-#endif +- +-#include "interface/vcos/vcos_types.h" +-#include "vcos_platform.h" +- +-/** \file +- * +- * Memory allocation api (malloc/free equivalents) is for benefit of host +- * applications. VideoCore code should use rtos_XXX functions. +- * +- */ +- +- +-/** Allocate memory +- * +- * @param size Size of memory to allocate +- * @param description Description, to aid in debugging. May be ignored internally on some platforms. +- */ +-VCOS_INLINE_DECL +-void *vcos_malloc(VCOS_UNSIGNED size, const char *description); +- +-void *vcos_kmalloc(VCOS_UNSIGNED size, const char *description); +-void *vcos_kcalloc(VCOS_UNSIGNED num, VCOS_UNSIGNED size, const char *description); +- +-/** Allocate cleared memory +- * +- * @param num Number of items to allocate. +- * @param size Size of each item in bytes. +- * @param description Description, to aid in debugging. May be ignored internally on some platforms. +- */ +-VCOS_INLINE_DECL +-void *vcos_calloc(VCOS_UNSIGNED num, VCOS_UNSIGNED size, const char *description); +- +-/** Free memory +- * +- * Free memory that has been allocated. +- */ +-VCOS_INLINE_DECL +-void vcos_free(void *ptr); +- +-void vcos_kfree(void *ptr); +- +-/** Allocate aligned memory +- * +- * Allocate memory aligned on the specified boundary. +- * +- * @param size Size of memory to allocate +- * @param description Description, to aid in debugging. May be ignored internally on some platforms. +- */ +-VCOS_INLINE_DECL +-void *vcos_malloc_aligned(VCOS_UNSIGNED size, VCOS_UNSIGNED align, const char *description); +- +-/** Return the amount of free heap memory +- * +- */ +-VCOS_INLINE_DECL +-unsigned long vcos_get_free_mem(void); +- +-#ifdef __cplusplus +-} +-#endif +- +-#endif +- +- +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_msgqueue.h +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vcos/vcos_msgqueue.h 2013-07-26 19:32:07.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,168 +0,0 @@ +-/* +- * Copyright (c) 2010-2011 Broadcom. All rights reserved. +- * +- * This program is free software; you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation; either version 2 of the License, or +- * (at your option) any later version. +- * +- * This program is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with this program; if not, write to the Free Software +- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +- */ +- +-/*============================================================================= +-VCOS - packet-like messages, based loosely on those found in TRIPOS. +-=============================================================================*/ +- +-#ifndef VCOS_MSGQUEUE_H +-#define VCOS_MSGQUEUE_H +- +-#ifdef __cplusplus +-extern "C" { +-#endif +- +-#include "interface/vcos/vcos_types.h" +-#include "vcos_platform.h" +- +-/** +- * \file +- * +- * Packet-like messages, based loosely on those found in TRIPOS and +- * derivatives thereof. +- * +- * A task can send a message *pointer* to another task, where it is +- * queued on a linked list and the task woken up. The receiving task +- * consumes all of the messages on its input queue, and optionally +- * sends back replies using the original message memory. +- * +- * A caller can wait for the reply to a specific message - any other +- * messages that arrive in the meantime are queued separately. +- * +- * +- * All messages have a standard common layout, but the payload area can +- * be used freely to extend this. +- */ +- +-/** Map the payload portion of a message to a structure pointer. +- */ +-#define VCOS_MSG_DATA(_msg) (void*)((_msg)->data) +- +-/** Standard message ids - FIXME - these need to be done properly! */ +-#define VCOS_MSG_N_QUIT 1 +-#define VCOS_MSG_N_OPEN 2 +-#define VCOS_MSG_N_CLOSE 3 +-#define VCOS_MSG_N_PRIVATE (1<<20) +- +-#define VCOS_MSG_REPLY_BIT (1<<31) +- +-/** Make gnuc compiler be happy about pointer punning */ +-#ifdef __GNUC__ +-#define __VCOS_MAY_ALIAS __attribute__((__may_alias__)) +-#else +-#define __VCOS_MAY_ALIAS +-#endif +- +-/** A single message queue. +- */ +-typedef struct VCOS_MSGQUEUE_T +-{ +- struct VCOS_MSG_T *head; /**< head of linked list of messages waiting on this queue */ +- struct VCOS_MSG_T *tail; /**< tail of message queue */ +- VCOS_SEMAPHORE_T sem; /**< thread waits on this for new messages */ +- VCOS_MUTEX_T lock; /**< locks the messages list */ +-} VCOS_MSGQUEUE_T; +- +-/** A single message +- */ +-typedef struct VCOS_MSG_T +-{ +- uint32_t code; /**< message code */ +- int error; /**< error status signalled back to caller */ +- VCOS_MSGQUEUE_T *dst; /**< destination queue */ +- VCOS_MSGQUEUE_T *src; /**< source; replies go back to here */ +- struct VCOS_MSG_T *next; /**< next in queue */ +- VCOS_THREAD_T *src_thread; /**< for debug */ +- uint32_t data[25]; /**< payload area */ +-} VCOS_MSG_T; +- +-/** An endpoint +- */ +-typedef struct VCOS_MSG_ENDPOINT_T +-{ +- VCOS_MSGQUEUE_T primary; /**< incoming messages */ +- VCOS_MSGQUEUE_T secondary; /**< this is used for waitspecific */ +- char name[32]; /**< name of this endpoint, for find() */ +- struct VCOS_MSG_ENDPOINT_T *next; /**< next in global list of endpoints */ +-} VCOS_MSG_ENDPOINT_T; +-#define MSG_REPLY_BIT (1<<31) +- +-/** Initalise the library. Normally called from vcos_init(). +- */ +-extern VCOS_STATUS_T vcos_msgq_init(void); +- +-/** Find a message queue by name and get a handle to it. +- * +- * @param name the name of the queue to find +- * +- * @return The message queue, or NULL if not found. +- */ +-VCOSPRE_ VCOS_MSGQUEUE_T VCOSPOST_ *vcos_msgq_find(const char *name); +- +-/** Wait for a message queue to come into existence. If it already exists, +- * return immediately, otherwise block. +- * +- * On the whole, if you find yourself using this, it is probably a sign +- * of poor design, since you should create all the server threads first, +- * and then the client threads. But it is sometimes useful. +- * +- * @param name the name of the queue to find +- * @return The message queue +- */ +-VCOSPRE_ VCOS_MSGQUEUE_T VCOSPOST_ *vcos_msgq_wait(const char *name); +- +-/** Send a message. +- */ +-VCOSPRE_ void VCOSPOST_ vcos_msg_send(VCOS_MSGQUEUE_T *dest, uint32_t code, VCOS_MSG_T *msg); +- +-/** Send a message and wait for a reply. +- */ +-VCOSPRE_ void VCOSPOST_ vcos_msg_sendwait(VCOS_MSGQUEUE_T *queue, uint32_t code, VCOS_MSG_T *msg); +- +-/** Wait for a message on this thread's endpoint. +- */ +-VCOSPRE_ VCOS_MSG_T * VCOSPOST_ vcos_msg_wait(void); +- +-/** Wait for a specific message. +- */ +-VCOS_MSG_T * vcos_msg_wait_specific(VCOS_MSGQUEUE_T *queue, VCOS_MSG_T *msg); +- +-/** Peek for a message on this thread's endpoint, if a message is not available, NULL is +- returned. If a message is available it will be removed from the endpoint and returned. +- */ +-VCOSPRE_ VCOS_MSG_T * VCOSPOST_ vcos_msg_peek(void); +- +-/** Send a reply to a message +- */ +-VCOSPRE_ void VCOSPOST_ vcos_msg_reply(VCOS_MSG_T *msg); +- +-/** Create an endpoint. Each thread should need no more than one of these - if you +- * find yourself needing a second one, you've done something wrong. +- */ +-VCOSPRE_ VCOS_STATUS_T VCOSPOST_ vcos_msgq_endpoint_create(VCOS_MSG_ENDPOINT_T *ep, const char *name); +- +-/** Destroy an endpoint. +- */ +-VCOSPRE_ void VCOSPOST_ vcos_msgq_endpoint_delete(VCOS_MSG_ENDPOINT_T *ep); +- +-#ifdef __cplusplus +-} +-#endif +-#endif +- +- +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_mutex.h +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vcos/vcos_mutex.h 2013-07-26 19:32:07.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,103 +0,0 @@ +-/* +- * Copyright (c) 2010-2011 Broadcom. All rights reserved. +- * +- * This program is free software; you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation; either version 2 of the License, or +- * (at your option) any later version. +- * +- * This program is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with this program; if not, write to the Free Software +- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +- */ +- +-/*============================================================================= +-VideoCore OS Abstraction Layer - mutex public header file +-=============================================================================*/ +- +-#ifndef VCOS_MUTEX_H +-#define VCOS_MUTEX_H +- +-#ifdef __cplusplus +-extern "C" { +-#endif +- +-#include "interface/vcos/vcos_types.h" +-#include "vcos_platform.h" +- +-/** +- * \file vcos_mutex.h +- * +- * Mutex API. Mutexes are not re-entrant, as supporting this adds extra code +- * that slows down clients which have been written sensibly. +- * +- * \sa vcos_reentrant_mutex.h +- * +- */ +- +-/** Create a mutex. +- * +- * @param m Filled in with mutex on return +- * @param name A non-null name for the mutex, used for diagnostics. +- * +- * @return VCOS_SUCCESS if mutex was created, or error code. +- */ +-VCOS_INLINE_DECL +-VCOS_STATUS_T vcos_mutex_create(VCOS_MUTEX_T *m, const char *name); +- +-/** Delete the mutex. +- */ +-VCOS_INLINE_DECL +-void vcos_mutex_delete(VCOS_MUTEX_T *m); +- +-/** +- * \brief Wait to claim the mutex. +- * +- * On most platforms this always returns VCOS_SUCCESS, and so would ideally be +- * a void function, however some platforms allow a wait to be interrupted so +- * it remains non-void. +- * +- * Try to obtain the mutex. +- * @param m Mutex to wait on +- * @return VCOS_SUCCESS - mutex was taken. +- * VCOS_EAGAIN - could not take mutex. +- */ +-#ifndef vcos_mutex_lock +-VCOS_INLINE_DECL +-VCOS_STATUS_T vcos_mutex_lock(VCOS_MUTEX_T *m); +- +-/** Release the mutex. +- */ +-VCOS_INLINE_DECL +-void vcos_mutex_unlock(VCOS_MUTEX_T *m); +-#endif +- +-/** Test if the mutex is already locked. +- * +- * @return 1 if mutex is locked, 0 if it is unlocked. +- */ +-VCOS_INLINE_DECL +-int vcos_mutex_is_locked(VCOS_MUTEX_T *m); +- +-/** Obtain the mutex if possible. +- * +- * @param m the mutex to try to obtain +- * +- * @return VCOS_SUCCESS if mutex is succesfully obtained, or VCOS_EAGAIN +- * if it is already in use by another thread. +- */ +-#ifndef vcos_mutex_trylock +-VCOS_INLINE_DECL +-VCOS_STATUS_T vcos_mutex_trylock(VCOS_MUTEX_T *m); +-#endif +- +- +-#ifdef __cplusplus +-} +-#endif +-#endif +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_once.h +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vcos/vcos_once.h 2013-07-26 19:32:07.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,53 +0,0 @@ +-/* +- * Copyright (c) 2010-2011 Broadcom. All rights reserved. +- * +- * This program is free software; you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation; either version 2 of the License, or +- * (at your option) any later version. +- * +- * This program is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with this program; if not, write to the Free Software +- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +- */ +- +-/*============================================================================= +-VideoCore OS Abstraction Layer - 'once' +-=============================================================================*/ +- +-#ifndef VCOS_ONCE_H +-#define VCOS_ONCE_H +- +-#ifdef __cplusplus +-extern "C" { +-#endif +- +-#include "interface/vcos/vcos_types.h" +-#include "vcos_platform.h" +- +-/** +- * \file vcos_once.h +- * +- * Ensure something is called only once. +- * +- * Initialize once_control to VCOS_ONCE_INIT. The first +- * time this is called, the init_routine will be called. Thereafter +- * it won't. +- * +- * \sa pthread_once() +- * +- */ +- +-VCOS_STATUS_T vcos_once(VCOS_ONCE_T *once_control, +- void (*init_routine)(void)); +- +-#ifdef __cplusplus +-} +-#endif +-#endif +- +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_semaphore.h +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vcos/vcos_semaphore.h 2013-07-26 19:32:07.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,126 +0,0 @@ +-/* +- * Copyright (c) 2010-2011 Broadcom. All rights reserved. +- * +- * This program is free software; you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation; either version 2 of the License, or +- * (at your option) any later version. +- * +- * This program is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with this program; if not, write to the Free Software +- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +- */ +- +-/*============================================================================= +-VideoCore OS Abstraction Layer - public header file +-=============================================================================*/ +- +-#ifndef VCOS_SEMAPHORE_H +-#define VCOS_SEMAPHORE_H +- +-#ifdef __cplusplus +-extern "C" { +-#endif +- +-#include "interface/vcos/vcos_types.h" +-#include "vcos_platform.h" +- +-/** +- * \file vcos_semaphore.h +- * +- * \section sem Semaphores +- * +- * This provides counting semaphores. Semaphores are not re-entrant. On sensible +- * operating systems a semaphore can always be posted but can only be taken in +- * thread (not interrupt) context. Under Nucleus, a LISR cannot post a semaphore, +- * although it would not be hard to lift this restriction. +- * +- * \subsection timeout Timeout +- * +- * On both Nucleus and ThreadX a semaphore can be taken with a timeout. This is +- * not supported by VCOS because it makes the non-timeout code considerably more +- * complicated (and hence slower). In the unlikely event that you need a timeout +- * with a semaphore, and you cannot simply redesign your code to avoid it, use +- * an event flag (vcos_event_flags.h). +- * +- * \subsection sem_nucleus Changes from Nucleus: +- * +- * Semaphores are always "FIFO" - i.e. sleeping threads are woken in FIFO order. That's +- * because: +- * \arg there's no support for NU_PRIORITY in threadx (though it can be emulated, slowly) +- * \arg we don't appear to actually consciously use it - for example, Dispmanx uses +- * it, but all threads waiting are the same priority. +- * +- */ +- +-/** +- * \brief Create a semaphore. +- * +- * Create a semaphore. +- * +- * @param sem Pointer to memory to be initialized +- * @param name A name for this semaphore. The name may be truncated internally. +- * @param count The initial count for the semaphore. +- * +- * @return VCOS_SUCCESS if the semaphore was created. +- * +- */ +-VCOS_INLINE_DECL +-VCOS_STATUS_T vcos_semaphore_create(VCOS_SEMAPHORE_T *sem, const char *name, VCOS_UNSIGNED count); +- +-/** +- * \brief Wait on a semaphore. +- * +- * There is no timeout option on a semaphore, as adding this will slow down +- * implementations on some platforms. If you need that kind of behaviour, use +- * an event group. +- * +- * On most platforms this always returns VCOS_SUCCESS, and so would ideally be +- * a void function, however some platforms allow a wait to be interrupted so +- * it remains non-void. +- * +- * @param sem Semaphore to wait on +- * @return VCOS_SUCCESS - semaphore was taken. +- * VCOS_EAGAIN - could not take semaphore +- * +- */ +-VCOS_INLINE_DECL +-VCOS_STATUS_T vcos_semaphore_wait(VCOS_SEMAPHORE_T *sem); +- +-/** +- * \brief Try to wait for a semaphore. +- * +- * Try to obtain the semaphore. If it is already taken, return VCOS_TIMEOUT. +- * @param sem Semaphore to wait on +- * @return VCOS_SUCCESS - semaphore was taken. +- * VCOS_EAGAIN - could not take semaphore +- */ +-VCOS_INLINE_DECL +-VCOS_STATUS_T vcos_semaphore_trywait(VCOS_SEMAPHORE_T *sem); +- +-/** +- * \brief Post a semaphore. +- * +- * @param sem Semaphore to wait on +- */ +-VCOS_INLINE_DECL +-VCOS_STATUS_T vcos_semaphore_post(VCOS_SEMAPHORE_T *sem); +- +-/** +- * \brief Delete a semaphore, releasing any resources consumed by it. +- * +- * @param sem Semaphore to wait on +- */ +-VCOS_INLINE_DECL +-void vcos_semaphore_delete(VCOS_SEMAPHORE_T *sem); +- +-#ifdef __cplusplus +-} +-#endif +-#endif +- +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_stdbool.h +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vcos/vcos_stdbool.h 2013-07-26 19:32:07.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,34 +0,0 @@ +-/* +- * Copyright (c) 2010-2011 Broadcom. All rights reserved. +- * +- * This program is free software; you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation; either version 2 of the License, or +- * (at your option) any later version. +- * +- * This program is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with this program; if not, write to the Free Software +- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +- */ +-#ifndef VCOS_STDBOOL_H +-#define VCOS_STDBOOL_H +- +-#ifndef __cplusplus +- +-#if defined(__STDC__) && (__STDC_VERSION__ >= 199901L) +-#include +-#else +-typedef enum { +- false, +- true +-} bool; +-#endif +- +-#endif /* __cplusplus */ +- +-#endif +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_stdint.h +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vcos/vcos_stdint.h 2013-07-26 19:32:07.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,203 +0,0 @@ +-/* +- * Copyright (c) 2010-2011 Broadcom. All rights reserved. +- * +- * This program is free software; you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation; either version 2 of the License, or +- * (at your option) any later version. +- * +- * This program is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with this program; if not, write to the Free Software +- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +- */ +- +-#ifndef VCOS_STDINT_H +-#define VCOS_STDINT_H +- +-/* Attempt to provide the types defined in stdint.h. +- * +- * Ideally this would either call out to a platform-specific +- * header file (e.g. stdint.h) or define the types on a +- * per-architecture/compiler basis. But for now we just +- * use #ifdefs. +- */ +- +-#ifdef __cplusplus +-extern "C" { +-#endif +- +-#ifdef __SYMBIAN32__ +- +-typedef signed char int8_t; +-typedef unsigned char uint8_t; +- +-typedef signed short int16_t; +-typedef unsigned short uint16_t; +- +-typedef int16_t int_least16_t; +- +-typedef signed long int32_t; +-typedef unsigned long uint32_t; +- +-typedef signed long long int64_t; +-typedef unsigned long long uint64_t; +- +-typedef int32_t intptr_t; +-typedef uint32_t uintptr_t; +- +-typedef int64_t intmax_t; +-typedef uint64_t uintmax_t; +- +-#define INT8_MIN SCHAR_MIN +-#define INT8_MAX SCHAR_MAX +-#define UINT8_MAX UCHAR_MAX +-#define INT16_MIN SHRT_MIN +-#define INT16_MAX SHRT_MAX +-#define UINT16_MAX USHRT_MAX +-#define INT32_MIN LONG_MIN +-#define INT32_MAX LONG_MAX +-#define UINT32_MAX ULONG_MAX +-#define INT64_MIN LLONG_MIN +-#define INT64_MAX LLONG_MAX +-#define UINT64_MAX ULLONG_MAX +- +-#define INTPTR_MIN INT32_MIN +-#define INTPTR_MAX INT32_MAX +-#define UINTPTR_MAX UINT32_MAX +-#define INTMAX_MIN INT64_MIN +-#define INTMAX_MAX INT64_MAX +-#define INT_LEAST16_MAX INT16_MAX +-#define INT_LEAST16_MAX INT16_MAX +- +-/*{{{ C99 types - THIS WHOLE SECTION IS INCOMPATIBLE WITH C99. IT SHOULD RESIDE IN A STDINT.H SINCE THIS FILE GETS USED ON HOST SIDE */ +- +-#elif defined( __STDC__ ) && __STDC_VERSION__ >= 199901L +- +-#include +- +-#elif defined( __GNUC__ ) +- +-#include +- +-#elif defined(_MSC_VER) /* Visual C define equivalent types */ +- +-#include /* Avoids intptr_t being defined in vadefs.h */ +- +-typedef __int8 int8_t; +-typedef unsigned __int8 uint8_t; +- +-typedef __int16 int16_t; +-typedef unsigned __int16 uint16_t; +- +-typedef __int32 int32_t; +-typedef unsigned __int32 uint32_t; +- +-typedef __int64 int64_t; +-typedef unsigned __int64 uint64_t; +-typedef uint32_t uintptr_t; +-typedef int64_t intmax_t; +-typedef uint64_t uintmax_t; +-typedef int16_t int_least16_t; +- +-#elif defined (VCMODS_LCC) +-#include +- +-typedef signed char int8_t; +-typedef unsigned char uint8_t; +- +-typedef signed short int16_t; +-typedef unsigned short uint16_t; +- +-typedef signed long int32_t; +-typedef unsigned long uint32_t; +- +-typedef signed long int64_t; /*!!!! PFCD, this means code using 64bit numbers will be broken on the VCE */ +-typedef unsigned long uint64_t; /* !!!! PFCD */ +- +-typedef int32_t intptr_t; +-typedef uint32_t uintptr_t; +-typedef int64_t intmax_t; +-typedef uint64_t uintmax_t; +-typedef int16_t int_least16_t; +- +-#define INT8_MIN SCHAR_MIN +-#define INT8_MAX SCHAR_MAX +-#define UINT8_MAX UCHAR_MAX +-#define INT16_MIN SHRT_MIN +-#define INT16_MAX SHRT_MAX +-#define UINT16_MAX USHRT_MAX +-#define INT32_MIN LONG_MIN +-#define INT32_MAX LONG_MAX +-#define UINT32_MAX ULONG_MAX +-#define INT64_MIN LONG_MIN /* !!!! PFCD */ +-#define INT64_MAX LONG_MAX /* !!!! PFCD */ +-#define UINT64_MAX ULONG_MAX /* !!!! PFCD */ +- +-#define INTPTR_MIN INT32_MIN +-#define INTPTR_MAX INT32_MAX +-#define UINTPTR_MAX UINT32_MAX +-#define INTMAX_MIN INT64_MIN +-#define INTMAX_MIN INT64_MIN +-#define INT_LEAST16_MAX INT16_MAX +-#define INT_LEAST16_MAX INT16_MAX +- +-#elif defined(__VIDEOCORE__) +- +-typedef signed char int8_t; +-typedef unsigned char uint8_t; +- +-typedef signed short int16_t; +-typedef unsigned short uint16_t; +- +-typedef signed long int32_t; +-typedef unsigned long uint32_t; +- +-typedef signed long long int64_t; +-typedef unsigned long long uint64_t; +- +-typedef int32_t intptr_t; +-typedef uint32_t uintptr_t; +-typedef int64_t intmax_t; +-typedef uint64_t uintmax_t; +-typedef int16_t int_least16_t; +- +-#define INT8_MIN SCHAR_MIN +-#define INT8_MAX SCHAR_MAX +-#define UINT8_MAX UCHAR_MAX +-#define INT16_MIN SHRT_MIN +-#define INT16_MAX SHRT_MAX +-#define UINT16_MAX USHRT_MAX +-#define INT32_MIN LONG_MIN +-#define INT32_MAX LONG_MAX +-#define UINT32_MAX ULONG_MAX +-#define INT64_MIN LLONG_MIN +-#define INT64_MAX LLONG_MAX +-#define UINT64_MAX ULLONG_MAX +- +-#define INTPTR_MIN INT32_MIN +-#define INTPTR_MAX INT32_MAX +-#define UINTPTR_MAX UINT32_MAX +-#define INTMAX_MIN INT64_MIN +-#define INTMAX_MAX INT64_MAX +-#define INT_LEAST16_MAX INT16_MAX +-#define INT_LEAST16_MAX INT16_MAX +- +-#elif defined (__HIGHC__) && defined(_I386) +- +-#include +- +-#else +-#error Unknown platform +-#endif +- +-#ifdef __cplusplus +-} +-#endif +-#endif /* VCOS_STDINT_H */ +- +- +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_string.h +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vcos/vcos_string.h 2013-07-26 19:32:07.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,84 +0,0 @@ +-/* +- * Copyright (c) 2010-2011 Broadcom. All rights reserved. +- * +- * This program is free software; you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation; either version 2 of the License, or +- * (at your option) any later version. +- * +- * This program is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with this program; if not, write to the Free Software +- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +- */ +- +-/*============================================================================= +-VideoCore OS Abstraction Layer - public header file +-=============================================================================*/ +- +-#ifndef VCOS_STRING_H +-#define VCOS_STRING_H +- +-/** +- * \file +- * +- * String functions. +- * +- */ +- +-#ifdef __cplusplus +-extern "C" { +-#endif +- +-#include "interface/vcos/vcos_types.h" +-#include "vcos_platform.h" +- +-#ifdef __KERNEL__ +-#include +-#else +-#include +-#endif +- +-/** Case insensitive string comparison. +- * +- */ +- +-VCOS_INLINE_DECL +-int vcos_strcasecmp(const char *s1, const char *s2); +- +-VCOS_INLINE_DECL +-int vcos_strncasecmp(const char *s1, const char *s2, size_t n); +- +-VCOSPRE_ int VCOSPOST_ vcos_vsnprintf( char *buf, size_t buflen, const char *fmt, va_list ap ); +- +-VCOSPRE_ int VCOSPOST_ vcos_snprintf(char *buf, size_t buflen, const char *fmt, ...); +- +-VCOS_STATIC_INLINE +-int vcos_strlen(const char *s) { return (int)strlen(s); } +- +-VCOS_STATIC_INLINE +-int vcos_strcmp(const char *s1, const char *s2) { return strcmp(s1,s2); } +- +-VCOS_STATIC_INLINE +-int vcos_strncmp(const char *cs, const char *ct, size_t count) { return strncmp(cs, ct, count); } +- +-VCOS_STATIC_INLINE +-char *vcos_strcpy(char *dst, const char *src) { return strcpy(dst, src); } +- +-VCOS_STATIC_INLINE +-char *vcos_strncpy(char *dst, const char *src, size_t count) { return strncpy(dst, src, count); } +- +-VCOS_STATIC_INLINE +-void *vcos_memcpy(void *dst, const void *src, size_t n) { memcpy(dst, src, n); return dst; } +- +-VCOS_STATIC_INLINE +-void *vcos_memset(void *p, int c, size_t n) { return memset(p, c, n); } +- +-#ifdef __cplusplus +-} +-#endif +-#endif +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_thread.h +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vcos/vcos_thread.h 2013-07-26 19:32:07.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,270 +0,0 @@ +-/* +- * Copyright (c) 2010-2011 Broadcom. All rights reserved. +- * +- * This program is free software; you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation; either version 2 of the License, or +- * (at your option) any later version. +- * +- * This program is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with this program; if not, write to the Free Software +- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +- */ +- +-/*============================================================================= +-VideoCore OS Abstraction Layer - public header file +-=============================================================================*/ +- +-#ifndef VCOS_THREAD_H +-#define VCOS_THREAD_H +- +-#ifdef __cplusplus +-extern "C" { +-#endif +- +-#include "interface/vcos/vcos_types.h" +-#include "vcos_platform.h" +- +-/** +- * \file vcos_thread.h +- * +- * \section thread Threads +- * +- * Under Nucleus, a thread is created by NU_Create_Task, passing in the stack +- * and various other parameters. To stop the thread, NU_Terminate_Thread() and +- * NU_Delete_Thread() are called. +- * +- * Unfortunately it's not possible to emulate this API under some fairly common +- * operating systems. Under Windows you can't pass in the stack, and you can't +- * safely terminate a thread. +- * +- * Therefore, an API which is similar to the pthreads API is used instead. This +- * API can (mostly) be emulated under all interesting operating systems. +- * +- * Obviously this makes the code somewhat more complicated on VideoCore than it +- * would otherwise be - we end up with an extra mutex per thread, and some code +- * that waits for it. The benefit is that we have a single way of creating +- * threads that works consistently on all platforms (apart from stack supplying). +- * +- * \subsection stack Stack +- * +- * It's still not possible to pass in the stack address, but this can be made +- * much more obvious in the API: the relevant function is missing and the +- * CPP symbol VCOS_CAN_SET_STACK_ADDR is zero rather than one. +- * +- * \subsection thr_create Creating a thread +- * +- * The simplest way to create a thread is with vcos_thread_create() passing in a +- * NULL thread parameter argument. To wait for the thread to exit, call +- * vcos_thread_join(). +- * +- * \subsection back Backward compatibility +- * +- * To ease migration, a "classic" thread creation API is provided for code +- * that used to make use of Nucleus, vcos_thread_create_classic(). The +- * arguments are not exactly the same, as the PREEMPT parameter is dropped. +- * +- */ +- +-#define VCOS_AFFINITY_CPU0 _VCOS_AFFINITY_CPU0 +-#define VCOS_AFFINITY_CPU1 _VCOS_AFFINITY_CPU1 +-#define VCOS_AFFINITY_MASK _VCOS_AFFINITY_MASK +-#define VCOS_AFFINITY_DEFAULT _VCOS_AFFINITY_DEFAULT +-#define VCOS_AFFINITY_THISCPU _VCOS_AFFINITY_THISCPU +- +-/** Report whether or not we have an RTOS at all, and hence the ability to +- * create threads. +- */ +-VCOSPRE_ int VCOSPOST_ vcos_have_rtos(void); +- +-/** Create a thread. It must be cleaned up by calling vcos_thread_join(). +- * +- * @param thread Filled in on return with thread +- * @param name A name for the thread. May be the empty string. +- * @param attrs Attributes; default attributes will be used if this is NULL. +- * @param entry Entry point. +- * @param arg Argument passed to the entry point. +- */ +-VCOSPRE_ VCOS_STATUS_T VCOSPOST_ vcos_thread_create(VCOS_THREAD_T *thread, +- const char *name, +- VCOS_THREAD_ATTR_T *attrs, +- VCOS_THREAD_ENTRY_FN_T entry, +- void *arg); +- +-/** Exit the thread from within the thread function itself. +- * Resources must still be cleaned up via a call to thread_join(). +- * +- * The thread can also be terminated by simply exiting the thread function. +- * +- * @param data Data passed to thread_join. May be NULL. +- */ +-VCOSPRE_ void VCOSPOST_ vcos_thread_exit(void *data); +- +-/** Wait for a thread to terminate and then clean up its resources. +- * +- * @param thread Thread to wait for +- * @param pData Updated to point at data provided in vcos_thread_exit or exit +- * code of thread function. +- */ +-VCOSPRE_ void VCOSPOST_ vcos_thread_join(VCOS_THREAD_T *thread, +- void **pData); +- +- +-/** +- * \brief Create a thread using an API similar to the one "traditionally" +- * used under Nucleus. +- * +- * This creates a thread which must be cleaned up by calling vcos_thread_join(). +- * The thread cannot be simply terminated (as in Nucleus and ThreadX) as thread +- * termination is not universally supported. +- * +- * @param thread Filled in with thread instance +- * @param name An optional name for the thread. NULL or "" may be used (but +- * a name will aid in debugging). +- * @param entry Entry point +- * @param arg A single argument passed to the entry point function +- * @param stack Pointer to stack address +- * @param stacksz Size of stack in bytes +- * @param priaff Priority of task, between VCOS_PRI_LOW and VCOS_PRI_HIGH, ORed with the CPU affinity +- * @param autostart If non-zero the thread will start immediately. +- * @param timeslice Timeslice (system ticks) for this thread. +- * +- * @sa vcos_thread_terminate vcos_thread_delete +- */ +-VCOSPRE_ VCOS_STATUS_T VCOSPOST_ vcos_thread_create_classic(VCOS_THREAD_T *thread, +- const char *name, +- void *(*entry)(void *arg), +- void *arg, +- void *stack, +- VCOS_UNSIGNED stacksz, +- VCOS_UNSIGNED priaff, +- VCOS_UNSIGNED timeslice, +- VCOS_UNSIGNED autostart); +- +-/** +- * \brief Set a thread's priority +- * +- * Set the priority for a thread. +- * +- * @param thread The thread +- * @param pri Thread priority in VCOS_PRI_MASK bits; affinity in VCOS_AFFINITY_MASK bits. +- */ +-VCOS_INLINE_DECL +-void vcos_thread_set_priority(VCOS_THREAD_T *thread, VCOS_UNSIGNED pri); +- +-/** +- * \brief Return the currently executing thread. +- * +- */ +-VCOS_INLINE_DECL +-VCOS_THREAD_T *vcos_thread_current(void); +- +-/** +- * \brief Return the thread's priority. +- */ +-VCOS_INLINE_DECL +-VCOS_UNSIGNED vcos_thread_get_priority(VCOS_THREAD_T *thread); +- +-/** +- * \brief Return the thread's cpu affinity. +- */ +-VCOS_INLINE_DECL +-VCOS_UNSIGNED vcos_thread_get_affinity(VCOS_THREAD_T *thread); +- +-/** +- * \brief Set the thread's cpu affinity. +- */ +- +-VCOS_INLINE_DECL +-void vcos_thread_set_affinity(VCOS_THREAD_T *thread, VCOS_UNSIGNED affinity); +- +-/** +- * \brief Query whether we are in an interrupt. +- * +- * @return 1 if in interrupt context. +- */ +-VCOS_INLINE_DECL +-int vcos_in_interrupt(void); +- +-/** +- * \brief Sleep a while. +- * +- * @param ms Number of milliseconds to sleep for +- * +- * This may actually sleep a whole number of ticks. +- */ +-VCOS_INLINE_DECL +-void vcos_sleep(uint32_t ms); +- +-/** +- * \brief Return the value of the hardware microsecond counter. +- * +- */ +-VCOS_INLINE_DECL +-uint32_t vcos_getmicrosecs(void); +- +-#define vcos_get_ms() (vcos_getmicrosecs()/1000) +- +-/** +- * \brief Return a unique identifier for the current process +- * +- */ +-VCOS_INLINE_DECL +-VCOS_UNSIGNED vcos_process_id_current(void); +- +-/** Relinquish this time slice. */ +-VCOS_INLINE_DECL +-void vcos_thread_relinquish(void); +- +-/** Return the name of the given thread. +- */ +-VCOSPRE_ const char * VCOSPOST_ vcos_thread_get_name(const VCOS_THREAD_T *thread); +- +-/** Change preemption. This is almost certainly not what you want, as it won't +- * work reliably in a multicore system: although you can affect the preemption +- * on *this* core, you won't affect what's happening on the other core(s). +- * +- * It's mainly here to ease migration. If you're using it in new code, you +- * probably need to think again. +- * +- * @param pe New preemption, VCOS_PREEMPT or VCOS_NO_PREEMPT +- * @return Old value of preemption. +- */ +-VCOS_INLINE_DECL +-VCOS_UNSIGNED vcos_change_preemption(VCOS_UNSIGNED pe); +- +-/** Is a thread still running, or has it exited? +- * +- * Note: this exists for some fairly scary code in the video codec tests. Don't +- * try to use it for anything else, as it may well not do what you expect. +- * +- * @param thread thread to query +- * @return non-zero if thread is running, or zero if it has exited. +- */ +-VCOS_INLINE_DECL +-int vcos_thread_running(VCOS_THREAD_T *thread); +- +-/** Resume a thread. +- * +- * @param thread thread to resume +- */ +-VCOS_INLINE_DECL +-void vcos_thread_resume(VCOS_THREAD_T *thread); +- +-/* +- * Internal APIs - may not always be present and should not be used in +- * client code. +- */ +- +-extern void _vcos_task_timer_set(void (*pfn)(void*), void *, VCOS_UNSIGNED ms); +-extern void _vcos_task_timer_cancel(void); +- +-#ifdef __cplusplus +-} +-#endif +-#endif +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_thread_attr.h +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vcos/vcos_thread_attr.h 2013-07-26 19:32:07.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,87 +0,0 @@ +-/* +- * Copyright (c) 2010-2011 Broadcom. All rights reserved. +- * +- * This program is free software; you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation; either version 2 of the License, or +- * (at your option) any later version. +- * +- * This program is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with this program; if not, write to the Free Software +- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +- */ +- +-/*============================================================================= +-VideoCore OS Abstraction Layer - thread attributes +-=============================================================================*/ +- +-#ifndef VCOS_THREAD_ATTR_H +-#define VCOS_THREAD_ATTR_H +- +-#ifdef __cplusplus +-extern "C" { +-#endif +- +-/** +- * \file +- * +- * Attributes for thread creation. +- * +- */ +- +-/** Initialize thread attribute struct. This call does not allocate memory, +- * and so cannot fail. +- * +- */ +-VCOSPRE_ void VCOSPOST_ vcos_thread_attr_init(VCOS_THREAD_ATTR_T *attrs); +- +-/** Set the stack address and size. If not set, a stack will be allocated automatically. +- * +- * This can only be set on some platforms. It will always be possible to set the stack +- * address on VideoCore, but on host platforms, support may well not be available. +- */ +-#if VCOS_CAN_SET_STACK_ADDR +-VCOS_INLINE_DECL +-void vcos_thread_attr_setstack(VCOS_THREAD_ATTR_T *attrs, void *addr, VCOS_UNSIGNED sz); +-#endif +- +-/** Set the stack size. If not set, a default size will be used. Attempting to call this after having +- * set the stack location with vcos_thread_attr_setstack() will result in undefined behaviour. +- */ +-VCOS_INLINE_DECL +-void vcos_thread_attr_setstacksize(VCOS_THREAD_ATTR_T *attrs, VCOS_UNSIGNED sz); +- +-/** Set the task priority. If not set, a default value will be used. +- */ +-VCOS_INLINE_DECL +-void vcos_thread_attr_setpriority(VCOS_THREAD_ATTR_T *attrs, VCOS_UNSIGNED pri); +- +-/** Set the task cpu affinity. If not set, the default will be used. +- */ +-VCOS_INLINE_DECL +-void vcos_thread_attr_setaffinity(VCOS_THREAD_ATTR_T *attrs, VCOS_UNSIGNED aff); +- +-/** Set the timeslice. If not set the default will be used. +- */ +-VCOS_INLINE_DECL +-void vcos_thread_attr_settimeslice(VCOS_THREAD_ATTR_T *attrs, VCOS_UNSIGNED ts); +- +-/** The thread entry function takes (argc,argv), as per Nucleus, with +- * argc being 0. This may be withdrawn in a future release and should not +- * be used in new code. +- */ +-VCOS_INLINE_DECL +-void _vcos_thread_attr_setlegacyapi(VCOS_THREAD_ATTR_T *attrs, VCOS_UNSIGNED legacy); +- +-VCOS_INLINE_DECL +-void vcos_thread_attr_setautostart(VCOS_THREAD_ATTR_T *attrs, VCOS_UNSIGNED autostart); +- +-#ifdef __cplusplus +-} +-#endif +-#endif +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_timer.h +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vcos/vcos_timer.h 2013-07-26 19:32:07.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,106 +0,0 @@ +-/* +- * Copyright (c) 2010-2011 Broadcom. All rights reserved. +- * +- * This program is free software; you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation; either version 2 of the License, or +- * (at your option) any later version. +- * +- * This program is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with this program; if not, write to the Free Software +- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +- */ +- +-/*============================================================================= +-VideoCore OS Abstraction Layer - timer support +-=============================================================================*/ +- +-#ifndef VCOS_TIMER_H +-#define VCOS_TIMER_H +- +-#ifdef __cplusplus +-extern "C" { +-#endif +- +-#include "interface/vcos/vcos_types.h" +-#include "vcos_platform.h" +- +-/** \file vcos_timer.h +- * +- * Timers are single shot. +- * +- * Timer times are in milliseconds. +- * +- * \note that timer callback functions are called from an arbitrary thread +- * context. The expiration function should do its work as quickly as possible; +- * blocking should be avoided. +- * +- * \note On Windows, the separate function vcos_timer_init() must be called +- * as timer initialization from DllMain is not possible. +- */ +- +-/** Perform timer subsystem initialization. This function is not needed +- * on non-Windows platforms but is still present so that it can be +- * called. On Windows it is needed because vcos_init() gets called +- * from DLL initialization where it is not possible to create a +- * time queue (deadlock occurs if you try). +- * +- * @return VCOS_SUCCESS on success. VCOS_EEXIST if this has already been called +- * once. VCOS_ENOMEM if resource allocation failed. +- */ +-VCOSPRE_ VCOS_STATUS_T VCOSPOST_ vcos_timer_init(void); +- +-/** Create a timer in a disabled state. +- * +- * The timer is initially disabled. +- * +- * @param timer timer handle +- * @param name name for timer +- * @param expiration_routine function to call when timer expires +- * @param context context passed to expiration routine +- * +- */ +-VCOS_INLINE_DECL +-VCOS_STATUS_T vcos_timer_create(VCOS_TIMER_T *timer, +- const char *name, +- void (*expiration_routine)(void *context), +- void *context); +- +- +- +-/** Start a timer running. +- * +- * Timer must be stopped. +- * +- * @param timer timer handle +- * @param delay Delay to wait for, in ms +- */ +-VCOS_INLINE_DECL +-void vcos_timer_set(VCOS_TIMER_T *timer, VCOS_UNSIGNED delay); +- +-/** Stop an already running timer. +- * +- * @param timer timer handle +- */ +-VCOS_INLINE_DECL +-void vcos_timer_cancel(VCOS_TIMER_T *timer); +- +-/** Stop a timer and restart it. +- * @param timer timer handle +- * @param delay delay in ms +- */ +-VCOS_INLINE_DECL +-void vcos_timer_reset(VCOS_TIMER_T *timer, VCOS_UNSIGNED delay); +- +-VCOS_INLINE_DECL +-void vcos_timer_delete(VCOS_TIMER_T *timer); +- +-#ifdef __cplusplus +-} +-#endif +-#endif +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_types.h +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vcos/vcos_types.h 2013-07-26 19:32:07.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,211 +0,0 @@ +-/* +- * Copyright (c) 2010-2011 Broadcom. All rights reserved. +- * +- * This program is free software; you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation; either version 2 of the License, or +- * (at your option) any later version. +- * +- * This program is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with this program; if not, write to the Free Software +- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +- */ +- +-/*============================================================================= +-VideoCore OS Abstraction Layer - basic types +-=============================================================================*/ +- +-#ifndef VCOS_TYPES_H +-#define VCOS_TYPES_H +- +-#define VCOS_VERSION 1 +- +-#include "vcos_platform_types.h" +- +-#if !defined(VCOSPRE_) || !defined(VCOSPOST_) +-#error VCOSPRE_ and VCOSPOST_ not defined! +-#endif +- +-/* Redefine these here; this means that existing header files can carry on +- * using the VCHPOST/VCHPRE macros rather than having huge changes, which +- * could cause nasty merge problems. +- */ +-#ifndef VCHPOST_ +-#define VCHPOST_ VCOSPOST_ +-#endif +-#ifndef VCHPRE_ +-#define VCHPRE_ VCOSPRE_ +-#endif +- +-/** Entry function for a lowlevel thread. +- * +- * Returns void for consistency with Nucleus/ThreadX. +- */ +-typedef void (*VCOS_LLTHREAD_ENTRY_FN_T)(void *); +- +-/** Thread entry point. Returns a void* for consistency +- * with pthreads. +- */ +-typedef void *(*VCOS_THREAD_ENTRY_FN_T)(void*); +- +- +-/* Error return codes - chosen to be similar to errno values */ +-typedef enum +-{ +- VCOS_SUCCESS, +- VCOS_EAGAIN, +- VCOS_ENOENT, +- VCOS_ENOSPC, +- VCOS_EINVAL, +- VCOS_EACCESS, +- VCOS_ENOMEM, +- VCOS_ENOSYS, +- VCOS_EEXIST, +- VCOS_ENXIO, +- VCOS_EINTR +-} VCOS_STATUS_T; +- +-/* Some compilers (MetaWare) won't inline with -g turned on, which then results +- * in a lot of code bloat. To overcome this, inline functions are forward declared +- * with the prefix VCOS_INLINE_DECL, and implemented with the prefix VCOS_INLINE_IMPL. +- * +- * That then means that in a release build, "static inline" can be used in the obvious +- * way, but in a debug build the implementations can be skipped in all but one file, +- * by using VCOS_INLINE_BODIES. +- * +- * VCOS_INLINE_DECL - put this at the start of an inline forward declaration of a VCOS +- * function. +- * +- * VCOS_INLINE_IMPL - put this at the start of an inlined implementation of a VCOS +- * function. +- * +- */ +- +-/* VCOS_EXPORT - it turns out that in some circumstances we need the implementation of +- * a function even if it is usually inlined. +- * +- * In particular, if we have a codec that is usually provided in object form, if it +- * was built for a debug build it will be full of calls to vcos_XXX(). If this is used +- * in a *release* build, then there won't be any of these calls around in the main image +- * as they will all have been inlined. The problem also exists for vcos functions called +- * from assembler. +- * +- * VCOS_EXPORT ensures that the named function will be emitted as a regular (not static-inline) +- * function inside vcos_.c so that it can be linked against. Doing this for every +- * VCOS function would be a bit code-bloat-tastic, so it is only done for those that need it. +- * +- */ +- +-#ifdef __cplusplus +-#define _VCOS_INLINE inline +-#else +-#define _VCOS_INLINE __inline +-#endif +- +-#if defined(NDEBUG) +- +-#ifdef __GNUC__ +-# define VCOS_INLINE_DECL extern __inline__ +-# define VCOS_INLINE_IMPL static __inline__ +-#else +-# define VCOS_INLINE_DECL static _VCOS_INLINE /* declare a func */ +-# define VCOS_INLINE_IMPL static _VCOS_INLINE /* implement a func inline */ +-#endif +- +-# if defined(VCOS_WANT_IMPL) +-# define VCOS_EXPORT +-# else +-# define VCOS_EXPORT VCOS_INLINE_IMPL +-# endif /* VCOS_WANT_IMPL */ +- +-#define VCOS_INLINE_BODIES +- +-#else /* NDEBUG */ +- +-#if !defined(VCOS_INLINE_DECL) +- #define VCOS_INLINE_DECL extern +-#endif +-#if !defined(VCOS_INLINE_IMPL) +- #define VCOS_INLINE_IMPL +-#endif +-#define VCOS_EXPORT VCOS_INLINE_IMPL +-#endif +- +-#define VCOS_STATIC_INLINE static _VCOS_INLINE +- +-#if defined(__HIGHC__) || defined(__HIGHC_ANSI__) +-#define _VCOS_METAWARE +-#endif +- +-/** It seems that __FUNCTION__ isn't standard! +- */ +-#if __STDC_VERSION__ < 199901L +-# if __GNUC__ >= 2 || defined(__VIDEOCORE__) +-# define VCOS_FUNCTION __FUNCTION__ +-# else +-# define VCOS_FUNCTION "" +-# endif +-#else +-# define VCOS_FUNCTION __func__ +-#endif +- +-#define _VCOS_MS_PER_TICK (1000/VCOS_TICKS_PER_SECOND) +- +-/* Convert a number of milliseconds to a tick count. Internal use only - fails to +- * convert VCOS_SUSPEND correctly. +- */ +-#define _VCOS_MS_TO_TICKS(ms) (((ms)+_VCOS_MS_PER_TICK-1)/_VCOS_MS_PER_TICK) +- +-#define VCOS_TICKS_TO_MS(ticks) ((ticks) * _VCOS_MS_PER_TICK) +- +-/** VCOS version of DATESTR, from pcdisk.h. Used by the hostreq service. +- */ +-typedef struct vcos_datestr +-{ +- uint8_t cmsec; /**< Centesimal mili second */ +- uint16_t date; /**< Date */ +- uint16_t time; /**< Time */ +- +-} VCOS_DATESTR; +- +-/* Compile-time assert - declares invalid array length if condition +- * not met, or array of length one if OK. +- */ +-#define VCOS_CASSERT(e) extern char vcos_compile_time_check[1/(e)] +- +-#define vcos_min(x,y) ((x) < (y) ? (x) : (y)) +-#define vcos_max(x,y) ((x) > (y) ? (x) : (y)) +- +-/** Return the count of an array. FIXME: under gcc we could make +- * this report an error for pointers using __builtin_types_compatible(). +- */ +-#define vcos_countof(x) (sizeof((x)) / sizeof((x)[0])) +- +-/* for backward compatibility */ +-#define countof(x) (sizeof((x)) / sizeof((x)[0])) +- +-#define VCOS_ALIGN_DOWN(p,n) (((ptrdiff_t)(p)) & ~((n)-1)) +-#define VCOS_ALIGN_UP(p,n) VCOS_ALIGN_DOWN((ptrdiff_t)(p)+(n)-1,(n)) +- +-/** bool_t is not a POSIX type so cannot rely on it. Define it here. +- * It's not even defined in stdbool.h. +- */ +-typedef int32_t vcos_bool_t; +-typedef int32_t vcos_fourcc_t; +- +-#define VCOS_FALSE 0 +-#define VCOS_TRUE (!VCOS_FALSE) +- +-/** Mark unused arguments to keep compilers quiet */ +-#define vcos_unused(x) (void)(x) +- +-/** For backward compatibility */ +-typedef vcos_fourcc_t fourcc_t; +-typedef vcos_fourcc_t FOURCC_T; +- +-#endif +Index: linux-3.2.46/sound/arm/bcm2835-vchiq.c +=================================================================== +--- linux-3.2.46.orig/sound/arm/bcm2835-vchiq.c 2013-07-26 19:36:41.000000000 +0000 ++++ linux-3.2.46/sound/arm/bcm2835-vchiq.c 2013-07-26 19:36:51.000000000 +0000 +@@ -226,6 +226,7 @@ + /* Open the VCHI service connections */ + for (i = 0; i < num_connections; i++) { + SERVICE_CREATION_T params = { ++ VCHI_VERSION(VC_AUDIOSERV_VER), // version + VC_AUDIO_SERVER_NAME, // 4cc service code + vchi_connections[i], // passed in fn pointers + 0, // rx fifo size (unused) +Index: linux-3.2.46/sound/arm/vc_vchi_audioserv_defs.h +=================================================================== +--- linux-3.2.46.orig/sound/arm/vc_vchi_audioserv_defs.h 2013-07-26 19:32:35.000000000 +0000 ++++ linux-3.2.46/sound/arm/vc_vchi_audioserv_defs.h 2013-07-26 19:36:51.000000000 +0000 +@@ -15,6 +15,8 @@ + #ifndef _VC_AUDIO_DEFS_H_ + #define _VC_AUDIO_DEFS_H_ + ++#define VC_AUDIOSERV_VER 1 ++ + // FourCC code used for VCHI connection + #define VC_AUDIO_SERVER_NAME MAKE_FOURCC("AUDS") + diff -Nru linux-3.2.46/debian/patches/rpi/rpi_258_a542809e00a8e14984866a73547e0f1efcce57c3.patch linux-3.2.46/debian/patches/rpi/rpi_258_a542809e00a8e14984866a73547e0f1efcce57c3.patch --- linux-3.2.46/debian/patches/rpi/rpi_258_a542809e00a8e14984866a73547e0f1efcce57c3.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_258_a542809e00a8e14984866a73547e0f1efcce57c3.patch 2013-07-26 19:36:58.000000000 +0000 @@ -0,0 +1,385 @@ +commit a542809e00a8e14984866a73547e0f1efcce57c3 +Author: popcornmix +Date: Fri Oct 5 17:44:36 2012 +0100 + + Add in missed vchiq files + +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_build_info.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_build_info.h 2013-07-26 19:36:57.000000000 +0000 +@@ -0,0 +1,22 @@ ++/* ++ * Copyright (c) 2010-2011 Broadcom. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++const char *vchiq_get_build_hostname(void); ++const char *vchiq_get_build_version(void); ++const char *vchiq_get_build_time(void); ++const char *vchiq_get_build_date(void); +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_genversion +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_genversion 2013-07-26 19:36:57.000000000 +0000 +@@ -0,0 +1,87 @@ ++#!/usr/bin/perl -w ++ ++use strict; ++ ++# ++# Generate a version from available information ++# ++ ++my $prefix = shift @ARGV; ++my $root = shift @ARGV; ++ ++ ++if ( not defined $root ) { ++ die "usage: $0 prefix root-dir\n"; ++} ++ ++if ( ! -d $root ) { ++ die "root directory $root not found\n"; ++} ++ ++my $version = "unknown"; ++my $tainted = ""; ++ ++if ( -d "$root/.git" ) { ++ # attempt to work out git version. only do so ++ # on a linux build host, as cygwin builds are ++ # already slow enough ++ ++ if ( -f "/usr/bin/git" || -f "/usr/local/bin/git" ) { ++ if (not open(F, "git --git-dir $root/.git rev-parse --verify HEAD|")) { ++ $version = "no git version"; ++ } ++ else { ++ $version = ; ++ $version =~ s/[ \r\n]*$//; # chomp may not be enough (cygwin). ++ $version =~ s/^[ \r\n]*//; # chomp may not be enough (cygwin). ++ } ++ ++ if (open(G, "git --git-dir $root/.git status --porcelain|")) { ++ $tainted = ; ++ $tainted =~ s/[ \r\n]*$//; # chomp may not be enough (cygwin). ++ $tainted =~ s/^[ \r\n]*//; # chomp may not be enough (cygwin). ++ if (length $tainted) { ++ $version = join ' ', $version, "(tainted)"; ++ } ++ else { ++ $version = join ' ', $version, "(clean)"; ++ } ++ } ++ } ++} ++ ++my $hostname = `hostname`; ++$hostname =~ s/[ \r\n]*$//; # chomp may not be enough (cygwin). ++$hostname =~ s/^[ \r\n]*//; # chomp may not be enough (cygwin). ++ ++ ++print STDERR "Version $version\n"; ++print < ++ ++VC_DEBUG_DECLARE_STRING_VAR( ${prefix}_build_hostname, "$hostname" ); ++VC_DEBUG_DECLARE_STRING_VAR( ${prefix}_build_version, "$version" ); ++VC_DEBUG_DECLARE_STRING_VAR( ${prefix}_build_time, __TIME__ ); ++VC_DEBUG_DECLARE_STRING_VAR( ${prefix}_build_date, __DATE__ ); ++ ++const char *vchiq_get_build_hostname( void ) ++{ ++ return vchiq_build_hostname; ++} ++ ++const char *vchiq_get_build_version( void ) ++{ ++ return vchiq_build_version; ++} ++ ++const char *vchiq_get_build_date( void ) ++{ ++ return vchiq_build_date; ++} ++ ++const char *vchiq_get_build_time( void ) ++{ ++ return vchiq_build_time; ++} ++EOF +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_proc.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_proc.c 2013-07-26 19:36:57.000000000 +0000 +@@ -0,0 +1,223 @@ ++/* ++ * Copyright (c) 2012 Broadcom Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++ ++#include ++#include "vchiq_core.h" ++#include "vchiq_arm.h" ++ ++struct vchiq_proc_info { ++ /* Global 'vc' proc entry used by all instances */ ++ struct proc_dir_entry *vc_cfg_dir; ++ ++ /* one entry per client process */ ++ struct proc_dir_entry *clients; ++ ++ /* log categories */ ++ struct proc_dir_entry *log_categories; ++}; ++ ++static struct vchiq_proc_info proc_info; ++ ++struct proc_dir_entry *vchiq_proc_top(void) ++{ ++ BUG_ON(proc_info.vc_cfg_dir == NULL); ++ return proc_info.vc_cfg_dir; ++} ++ ++/**************************************************************************** ++* ++* log category entries ++* ++***************************************************************************/ ++#define PROC_WRITE_BUF_SIZE 256 ++ ++#define VCHIQ_LOG_ERROR_STR "error" ++#define VCHIQ_LOG_WARNING_STR "warning" ++#define VCHIQ_LOG_INFO_STR "info" ++#define VCHIQ_LOG_TRACE_STR "trace" ++ ++static int log_cfg_read(char *buffer, ++ char **start, ++ off_t off, ++ int count, ++ int *eof, ++ void *data) ++{ ++ int len = 0; ++ char *log_value = NULL; ++ ++ switch (*((int *)data)) { ++ case VCHIQ_LOG_ERROR: ++ log_value = VCHIQ_LOG_ERROR_STR; ++ break; ++ case VCHIQ_LOG_WARNING: ++ log_value = VCHIQ_LOG_WARNING_STR; ++ break; ++ case VCHIQ_LOG_INFO: ++ log_value = VCHIQ_LOG_INFO_STR; ++ break; ++ case VCHIQ_LOG_TRACE: ++ log_value = VCHIQ_LOG_TRACE_STR; ++ break; ++ default: ++ break; ++ } ++ ++ len += sprintf(buffer + len, ++ "%s\n", ++ log_value ? log_value : "(null)"); ++ ++ return len; ++} ++ ++ ++static int log_cfg_write(struct file *file, ++ const char __user *buffer, ++ unsigned long count, ++ void *data) ++{ ++ int *log_module = data; ++ char kbuf[PROC_WRITE_BUF_SIZE + 1]; ++ ++ (void)file; ++ ++ memset(kbuf, 0, PROC_WRITE_BUF_SIZE + 1); ++ if (count >= PROC_WRITE_BUF_SIZE) ++ count = PROC_WRITE_BUF_SIZE; ++ ++ if (copy_from_user(kbuf, ++ buffer, ++ count) != 0) ++ return -EFAULT; ++ kbuf[count - 1] = 0; ++ ++ if (strncmp("error", kbuf, strlen("error")) == 0) ++ *log_module = VCHIQ_LOG_ERROR; ++ else if (strncmp("warning", kbuf, strlen("warning")) == 0) ++ *log_module = VCHIQ_LOG_WARNING; ++ else if (strncmp("info", kbuf, strlen("info")) == 0) ++ *log_module = VCHIQ_LOG_INFO; ++ else if (strncmp("trace", kbuf, strlen("trace")) == 0) ++ *log_module = VCHIQ_LOG_TRACE; ++ else ++ *log_module = VCHIQ_LOG_DEFAULT; ++ ++ return count; ++} ++ ++/* Log category proc entries */ ++struct vchiq_proc_log_entry { ++ const char *name; ++ int *plevel; ++ struct proc_dir_entry *dir; ++}; ++ ++static struct vchiq_proc_log_entry vchiq_proc_log_entries[] = { ++ { "core", &vchiq_core_log_level }, ++ { "msg", &vchiq_core_msg_log_level }, ++ { "sync", &vchiq_sync_log_level }, ++ { "arm", &vchiq_arm_log_level }, ++}; ++static int n_log_entries = ++ sizeof(vchiq_proc_log_entries)/sizeof(vchiq_proc_log_entries[0]); ++ ++/* create an entry under /proc/vc/log for each log category */ ++static int vchiq_proc_create_log_entries(struct proc_dir_entry *top) ++{ ++ struct proc_dir_entry *dir; ++ size_t i; ++ int ret = 0; ++ ++ dir = proc_mkdir("log", proc_info.vc_cfg_dir); ++ if (!dir) ++ return -ENOMEM; ++ proc_info.log_categories = dir; ++ ++ for (i = 0; i < n_log_entries; i++) { ++ dir = create_proc_entry(vchiq_proc_log_entries[i].name, ++ 0644, ++ proc_info.log_categories); ++ if (!dir) { ++ ret = -ENOMEM; ++ break; ++ } ++ ++ dir->read_proc = &log_cfg_read; ++ dir->write_proc = &log_cfg_write; ++ dir->data = (void *)vchiq_proc_log_entries[i].plevel; ++ ++ vchiq_proc_log_entries[i].dir = dir; ++ } ++ return ret; ++} ++ ++ ++int vchiq_proc_init(void) ++{ ++ BUG_ON(proc_info.vc_cfg_dir != NULL); ++ ++ proc_info.vc_cfg_dir = proc_mkdir("vc", NULL); ++ if (proc_info.vc_cfg_dir == NULL) ++ goto fail; ++ ++ proc_info.clients = proc_mkdir("clients", ++ proc_info.vc_cfg_dir); ++ if (!proc_info.clients) ++ goto fail; ++ ++ if (vchiq_proc_create_log_entries(proc_info.vc_cfg_dir) != 0) ++ goto fail; ++ ++ return 0; ++ ++fail: ++ vchiq_proc_deinit(); ++ vchiq_log_error(vchiq_arm_log_level, ++ "%s: failed to create proc directory", ++ __func__); ++ ++ return -ENOMEM; ++} ++ ++/* remove all the proc entries */ ++void vchiq_proc_deinit(void) ++{ ++ /* log category entries */ ++ if (proc_info.log_categories) { ++ size_t i; ++ for (i = 0; i < n_log_entries; i++) ++ if (vchiq_proc_log_entries[i].dir) ++ remove_proc_entry( ++ vchiq_proc_log_entries[i].name, ++ proc_info.log_categories); ++ ++ remove_proc_entry(proc_info.log_categories->name, ++ proc_info.vc_cfg_dir); ++ } ++ if (proc_info.clients) ++ remove_proc_entry(proc_info.clients->name, ++ proc_info.vc_cfg_dir); ++ if (proc_info.vc_cfg_dir) ++ remove_proc_entry(proc_info.vc_cfg_dir->name, NULL); ++} ++ ++struct proc_dir_entry *vchiq_clients_top(void) ++{ ++ return proc_info.clients; ++} +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_version.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_version.c 2013-07-26 19:36:57.000000000 +0000 +@@ -0,0 +1,27 @@ ++#include "vchiq_build_info.h" ++#include ++ ++VC_DEBUG_DECLARE_STRING_VAR( vchiq_build_hostname, "dc4-arm-01" ); ++VC_DEBUG_DECLARE_STRING_VAR( vchiq_build_version, "9245b4c35b99b3870e1f7dc598c5692b3c66a6f0 (tainted)" ); ++VC_DEBUG_DECLARE_STRING_VAR( vchiq_build_time, __TIME__ ); ++VC_DEBUG_DECLARE_STRING_VAR( vchiq_build_date, __DATE__ ); ++ ++const char *vchiq_get_build_hostname( void ) ++{ ++ return vchiq_build_hostname; ++} ++ ++const char *vchiq_get_build_version( void ) ++{ ++ return vchiq_build_version; ++} ++ ++const char *vchiq_get_build_date( void ) ++{ ++ return vchiq_build_date; ++} ++ ++const char *vchiq_get_build_time( void ) ++{ ++ return vchiq_build_time; ++} diff -Nru linux-3.2.46/debian/patches/rpi/rpi_259_63bbe8a30dadec5dc1c0bd59e93ae3b83b931d14.patch linux-3.2.46/debian/patches/rpi/rpi_259_63bbe8a30dadec5dc1c0bd59e93ae3b83b931d14.patch --- linux-3.2.46/debian/patches/rpi/rpi_259_63bbe8a30dadec5dc1c0bd59e93ae3b83b931d14.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_259_63bbe8a30dadec5dc1c0bd59e93ae3b83b931d14.patch 2013-07-26 19:37:00.000000000 +0000 @@ -0,0 +1,116 @@ +commit 63bbe8a30dadec5dc1c0bd59e93ae3b83b931d14 +Author: popcornmix +Date: Fri Oct 5 22:30:10 2012 +0100 + + Make vchiq enabled by default. Tidy Kconfig file. + +Index: linux-3.2.46/drivers/misc/vc04_services/Kconfig +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/Kconfig 2013-07-26 19:36:51.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/Kconfig 2013-07-26 19:36:59.000000000 +0000 +@@ -1,7 +1,7 @@ + config BCM2708_VCHIQ + tristate "Videocore VCHIQ" + depends on MACH_BCM2708 +- default CONFIG_BCM_VC_SERVICES ++ default y + help + Kernel to VideoCore communication interface for the + BCM2708 family of products. +Index: linux-3.2.46/drivers/misc/vc04_services/Makefile +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/Makefile 2013-07-26 19:36:51.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/Makefile 2013-07-26 19:36:59.000000000 +0000 +@@ -1,11 +1,5 @@ + ifeq ($(CONFIG_MACH_BCM2708),y) + +-############################################################################## +-# +-# This section is for building the RaspberryPi model +-# +-############################################################################## +- + obj-$(CONFIG_BCM2708_VCHIQ) += vchiq.o + + vchiq-objs := \ +@@ -22,80 +16,3 @@ + + endif + +-ifeq ($(CONFIG_ARCH_KONA),y) +- +-############################################################################## +-# +-# This section is for building the Capri/Island model +-# +-############################################################################## +- +-# Remove the quotes from the platform config name +-VCHIQ_PLATFORM_CONFIG = $(patsubst "%",%,$(CONFIG_VCHIQ_PLATFORM_CFG_NAME)) +- +-$(info VCHIQ_PLATFORM_CONFIG = $(VCHIQ_PLATFORM_CONFIG)) +-include $(srctree)/drivers/misc/vc04_services/interface/vchiq_arm/platform-cfg/$(VCHIQ_PLATFORM_CONFIG).mk +- +-$(info Building for MAP build system) +-$(info CONFIG_ARCH_KONA = $(CONFIG_ARCH_KONA)) +- +-EXTRA_CFLAGS += -Wall -Wstrict-prototypes -Wno-trigraphs -O2 -Wno-declaration-after-statement -Wno-parentheses +- +-EXTRA_CFLAGS += -I"drivers/misc/vc04_services/" +-EXTRA_CFLAGS += -I"drivers/misc/vc04_services/interface/vchiq_arm" +-EXTRA_CFLAGS += -I"drivers/misc/vc04_services/interface/debug_sym" +-EXTRA_CFLAGS += -I"include/linux/broadcom" +- +-EXTRA_CFLAGS += -Werror +- +-VCHIQ_HOST_BUS_ALIGNMENT = 3 +- +-EXTRA_CFLAGS += -DOS_ASSERT_FAILURE +-EXTRA_CFLAGS += -D__STDC_VERSION=199901L +-EXTRA_CFLAGS += -D__STDC_VERSION__=199901L +-EXTRA_CFLAGS += -D__VCCOREVER__=0 +-EXTRA_CFLAGS += -D__linux__ +-EXTRA_CFLAGS += -D__KERNEL__ +-EXTRA_CFLAGS += -DVCHIQ_HOST_BUS_ALIGNMENT=$(VCHIQ_HOST_BUS_ALIGNMENT) +-EXTRA_CFLAGS += -DVCHIQ_SLOT_PADDING=16 +-EXTRA_CFLAGS += -DVCHIQ_ARM_SIDE +-EXTRA_CFLAGS += -DUSE_VCHIQ_ARM +-ifeq ($(VCHIQ_SM_ALLOC),vcddr) +-EXTRA_CFLAGS += -DVCHIQ_SM_ALLOC_VCDDR +-endif +- +-obj-$(CONFIG_KONA_VCHIQ) += vc-vchiq.o +-vc-vchiq-objs := \ +- interface/vchiq_arm/vchiq_arm.o \ +- interface/vchiq_arm/vchiq_connected.o \ +- interface/vchiq_arm/vchiq_core.o \ +- interface/vchiq_arm/vchiq_kern_lib.o \ +- interface/vchiq_arm/vchiq_shim.o \ +- interface/vchiq_arm/vchiq_util.o \ +- interface/vchiq_arm/vchiq_kona_arm.o \ +- interface/vchiq_arm/vchiq_$(VCHIQ_PLATFORM)_arm.o \ +- interface/vchiq_arm/vchiq_version.o \ +- interface/vchiq_arm/vchiq_proc.o +-ifeq ($(VCHIQ_SM_ALLOC),vcddr) +-vc-vchiq-objs += \ +- interface/debug_sym/debug_sym.o +-endif +- +-obj-$(CONFIG_KONA_VCHIQ_MEMDRV) += vc-vchiq-memdrv-kona.o +-vc-vchiq-memdrv-kona-objs := \ +- interface/vchiq_arm/vchiq_memdrv_kona.o +- +-genversion = drivers/misc/vc04_services/interface/vchiq_arm/vchiq_genversion +- +-GENVERSION_SRC_ROOT_DIR = . +-ifeq ($(CONFIG_ANDROID),y) +-GENVERSION_SRC_ROOT_DIR = $(srctree) +-endif +- +-$(obj)/interface/vchiq_arm/vchiq_version.c: $(genversion) FORCE +- echo "(new) Generating $@ ..." +- perl $(srctree)/$(genversion) vchiq $(GENVERSION_SRC_ROOT_DIR) > $@ +- +-clean-files := vchiq_version.c +- +-endif diff -Nru linux-3.2.46/debian/patches/rpi/rpi_260_22cb6e26206c3e0e7bfb8e2adf86e9b10f9187a6.patch linux-3.2.46/debian/patches/rpi/rpi_260_22cb6e26206c3e0e7bfb8e2adf86e9b10f9187a6.patch --- linux-3.2.46/debian/patches/rpi/rpi_260_22cb6e26206c3e0e7bfb8e2adf86e9b10f9187a6.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_260_22cb6e26206c3e0e7bfb8e2adf86e9b10f9187a6.patch 2013-07-26 19:37:01.000000000 +0000 @@ -0,0 +1,43 @@ +commit 22cb6e26206c3e0e7bfb8e2adf86e9b10f9187a6 +Author: popcornmix +Date: Fri Oct 5 22:44:47 2012 +0100 + + Support dummy vc-mem ioctl used by vcdbg + +Index: linux-3.2.46/arch/arm/mach-bcm2708/include/mach/vc_mem.h +=================================================================== +--- linux-3.2.46.orig/arch/arm/mach-bcm2708/include/mach/vc_mem.h 2013-07-26 19:32:37.000000000 +0000 ++++ linux-3.2.46/arch/arm/mach-bcm2708/include/mach/vc_mem.h 2013-07-26 19:37:00.000000000 +0000 +@@ -22,6 +22,7 @@ + #define VC_MEM_IOC_MEM_PHYS_ADDR _IOR( VC_MEM_IOC_MAGIC, 0, unsigned long ) + #define VC_MEM_IOC_MEM_SIZE _IOR( VC_MEM_IOC_MAGIC, 1, unsigned int ) + #define VC_MEM_IOC_MEM_BASE _IOR( VC_MEM_IOC_MAGIC, 2, unsigned int ) ++#define VC_MEM_IOC_MEM_LOAD _IOR( VC_MEM_IOC_MAGIC, 3, unsigned int ) + + #if defined( __KERNEL__ ) + #define VC_MEM_TO_ARM_ADDR_MASK 0x3FFFFFFF +Index: linux-3.2.46/arch/arm/mach-bcm2708/vc_mem.c +=================================================================== +--- linux-3.2.46.orig/arch/arm/mach-bcm2708/vc_mem.c 2013-07-26 19:36:49.000000000 +0000 ++++ linux-3.2.46/arch/arm/mach-bcm2708/vc_mem.c 2013-07-26 19:37:00.000000000 +0000 +@@ -208,6 +208,20 @@ + } + break; + } ++ case VC_MEM_IOC_MEM_LOAD: ++ { ++ // Get the videocore memory base ++ vc_mem_get_base(); ++ ++ LOG_DBG("%s: VC_MEM_IOC_MEM_LOAD=%u", __func__, ++ mm_vc_mem_base); ++ ++ if (copy_to_user((void *) arg, &mm_vc_mem_base, ++ sizeof (mm_vc_mem_base)) != 0) { ++ rc = -EFAULT; ++ } ++ break; ++ } + default: + { + return -ENOTTY; diff -Nru linux-3.2.46/debian/patches/rpi/rpi_261_8bccc7a0340404cc14f831dd9c06d3528b5ebcff.patch linux-3.2.46/debian/patches/rpi/rpi_261_8bccc7a0340404cc14f831dd9c06d3528b5ebcff.patch --- linux-3.2.46/debian/patches/rpi/rpi_261_8bccc7a0340404cc14f831dd9c06d3528b5ebcff.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_261_8bccc7a0340404cc14f831dd9c06d3528b5ebcff.patch 2013-07-26 19:37:02.000000000 +0000 @@ -0,0 +1,19 @@ +commit 8bccc7a0340404cc14f831dd9c06d3528b5ebcff +Author: popcornmix +Date: Sat Oct 6 16:18:27 2012 +0100 + + Remove BUG() call from vchiq that is trigger when alsa is killed + +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_core.c +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_core.c 2013-07-26 19:36:51.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_core.c 2013-07-26 19:37:01.000000000 +0000 +@@ -3180,7 +3180,7 @@ + mode, VCHIQ_BULK_TRANSMIT); + + /* This call is for kernel thread use and should not be interrupted */ +- BUG_ON(status == VCHIQ_RETRY); ++ // dc4: remove as it does happen: BUG_ON(status == VCHIQ_RETRY); + return status; + } + diff -Nru linux-3.2.46/debian/patches/rpi/rpi_262_7aa8d823bd9feb758c2e0755d7d3589481bf6b36.patch linux-3.2.46/debian/patches/rpi/rpi_262_7aa8d823bd9feb758c2e0755d7d3589481bf6b36.patch --- linux-3.2.46/debian/patches/rpi/rpi_262_7aa8d823bd9feb758c2e0755d7d3589481bf6b36.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_262_7aa8d823bd9feb758c2e0755d7d3589481bf6b36.patch 2013-07-26 19:37:04.000000000 +0000 @@ -0,0 +1,16 @@ +commit 7aa8d823bd9feb758c2e0755d7d3589481bf6b36 +Author: Stephan Raue +Date: Mon Oct 8 16:33:17 2012 +0200 + + fix build with CONFIG_BCM2708_VCHIQ is disabled + +Index: linux-3.2.46/drivers/misc/Makefile +=================================================================== +--- linux-3.2.46.orig/drivers/misc/Makefile 2013-07-26 19:32:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/Makefile 2013-07-26 19:37:03.000000000 +0000 +@@ -48,4 +48,4 @@ + obj-y += carma/ + obj-$(CONFIG_USB_SWITCH_FSA9480) += fsa9480.o + obj-$(CONFIG_ALTERA_STAPL) +=altera-stapl/ +-obj-y += vc04_services/ ++obj-$(CONFIG_BCM2708_VCHIQ) += vc04_services/ diff -Nru linux-3.2.46/debian/patches/rpi/rpi_263_3cb5f1d392bef25dd965b71ca881f4c50beec59c.patch linux-3.2.46/debian/patches/rpi/rpi_263_3cb5f1d392bef25dd965b71ca881f4c50beec59c.patch --- linux-3.2.46/debian/patches/rpi/rpi_263_3cb5f1d392bef25dd965b71ca881f4c50beec59c.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_263_3cb5f1d392bef25dd965b71ca881f4c50beec59c.patch 2013-07-26 19:37:05.000000000 +0000 @@ -0,0 +1,18 @@ +commit 3cb5f1d392bef25dd965b71ca881f4c50beec59c +Author: popcornmix +Date: Mon Oct 15 18:54:42 2012 +0100 + + Revert "fix build with CONFIG_BCM2708_VCHIQ is disabled" + + This reverts commit 7aa8d823bd9feb758c2e0755d7d3589481bf6b36. + +Index: linux-3.2.46/drivers/misc/Makefile +=================================================================== +--- linux-3.2.46.orig/drivers/misc/Makefile 2013-07-26 19:37:03.000000000 +0000 ++++ linux-3.2.46/drivers/misc/Makefile 2013-07-26 19:37:04.000000000 +0000 +@@ -48,4 +48,4 @@ + obj-y += carma/ + obj-$(CONFIG_USB_SWITCH_FSA9480) += fsa9480.o + obj-$(CONFIG_ALTERA_STAPL) +=altera-stapl/ +-obj-$(CONFIG_BCM2708_VCHIQ) += vc04_services/ ++obj-y += vc04_services/ diff -Nru linux-3.2.46/debian/patches/rpi/rpi_264_d14d37193873888b207a992abe4a5848a5023ff6.patch linux-3.2.46/debian/patches/rpi/rpi_264_d14d37193873888b207a992abe4a5848a5023ff6.patch --- linux-3.2.46/debian/patches/rpi/rpi_264_d14d37193873888b207a992abe4a5848a5023ff6.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_264_d14d37193873888b207a992abe4a5848a5023ff6.patch 2013-07-26 19:37:06.000000000 +0000 @@ -0,0 +1,21 @@ +commit d14d37193873888b207a992abe4a5848a5023ff6 +Author: popcornmix +Date: Mon Oct 15 18:54:45 2012 +0100 + + Revert "Remove BUG() call from vchiq that is trigger when alsa is killed" + + This reverts commit 8bccc7a0340404cc14f831dd9c06d3528b5ebcff. + +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_core.c +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_core.c 2013-07-26 19:37:01.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_core.c 2013-07-26 19:37:05.000000000 +0000 +@@ -3180,7 +3180,7 @@ + mode, VCHIQ_BULK_TRANSMIT); + + /* This call is for kernel thread use and should not be interrupted */ +- // dc4: remove as it does happen: BUG_ON(status == VCHIQ_RETRY); ++ BUG_ON(status == VCHIQ_RETRY); + return status; + } + diff -Nru linux-3.2.46/debian/patches/rpi/rpi_265_fb241d04df64152a6d85d16b47ad978d8015a61c.patch linux-3.2.46/debian/patches/rpi/rpi_265_fb241d04df64152a6d85d16b47ad978d8015a61c.patch --- linux-3.2.46/debian/patches/rpi/rpi_265_fb241d04df64152a6d85d16b47ad978d8015a61c.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_265_fb241d04df64152a6d85d16b47ad978d8015a61c.patch 2013-07-26 19:37:08.000000000 +0000 @@ -0,0 +1,45 @@ +commit fb241d04df64152a6d85d16b47ad978d8015a61c +Author: popcornmix +Date: Mon Oct 15 18:54:47 2012 +0100 + + Revert "Support dummy vc-mem ioctl used by vcdbg" + + This reverts commit 22cb6e26206c3e0e7bfb8e2adf86e9b10f9187a6. + +Index: linux-3.2.46/arch/arm/mach-bcm2708/include/mach/vc_mem.h +=================================================================== +--- linux-3.2.46.orig/arch/arm/mach-bcm2708/include/mach/vc_mem.h 2013-07-26 19:37:00.000000000 +0000 ++++ linux-3.2.46/arch/arm/mach-bcm2708/include/mach/vc_mem.h 2013-07-26 19:37:07.000000000 +0000 +@@ -22,7 +22,6 @@ + #define VC_MEM_IOC_MEM_PHYS_ADDR _IOR( VC_MEM_IOC_MAGIC, 0, unsigned long ) + #define VC_MEM_IOC_MEM_SIZE _IOR( VC_MEM_IOC_MAGIC, 1, unsigned int ) + #define VC_MEM_IOC_MEM_BASE _IOR( VC_MEM_IOC_MAGIC, 2, unsigned int ) +-#define VC_MEM_IOC_MEM_LOAD _IOR( VC_MEM_IOC_MAGIC, 3, unsigned int ) + + #if defined( __KERNEL__ ) + #define VC_MEM_TO_ARM_ADDR_MASK 0x3FFFFFFF +Index: linux-3.2.46/arch/arm/mach-bcm2708/vc_mem.c +=================================================================== +--- linux-3.2.46.orig/arch/arm/mach-bcm2708/vc_mem.c 2013-07-26 19:37:00.000000000 +0000 ++++ linux-3.2.46/arch/arm/mach-bcm2708/vc_mem.c 2013-07-26 19:37:07.000000000 +0000 +@@ -208,20 +208,6 @@ + } + break; + } +- case VC_MEM_IOC_MEM_LOAD: +- { +- // Get the videocore memory base +- vc_mem_get_base(); +- +- LOG_DBG("%s: VC_MEM_IOC_MEM_LOAD=%u", __func__, +- mm_vc_mem_base); +- +- if (copy_to_user((void *) arg, &mm_vc_mem_base, +- sizeof (mm_vc_mem_base)) != 0) { +- rc = -EFAULT; +- } +- break; +- } + default: + { + return -ENOTTY; diff -Nru linux-3.2.46/debian/patches/rpi/rpi_266_6a84a910cb0564a3581ee7764bb255126657c4cb.patch linux-3.2.46/debian/patches/rpi/rpi_266_6a84a910cb0564a3581ee7764bb255126657c4cb.patch --- linux-3.2.46/debian/patches/rpi/rpi_266_6a84a910cb0564a3581ee7764bb255126657c4cb.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_266_6a84a910cb0564a3581ee7764bb255126657c4cb.patch 2013-07-26 19:37:09.000000000 +0000 @@ -0,0 +1,118 @@ +commit 6a84a910cb0564a3581ee7764bb255126657c4cb +Author: popcornmix +Date: Mon Oct 15 18:54:48 2012 +0100 + + Revert "Make vchiq enabled by default. Tidy Kconfig file." + + This reverts commit 63bbe8a30dadec5dc1c0bd59e93ae3b83b931d14. + +Index: linux-3.2.46/drivers/misc/vc04_services/Kconfig +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/Kconfig 2013-07-26 19:36:59.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/Kconfig 2013-07-26 19:37:08.000000000 +0000 +@@ -1,7 +1,7 @@ + config BCM2708_VCHIQ + tristate "Videocore VCHIQ" + depends on MACH_BCM2708 +- default y ++ default CONFIG_BCM_VC_SERVICES + help + Kernel to VideoCore communication interface for the + BCM2708 family of products. +Index: linux-3.2.46/drivers/misc/vc04_services/Makefile +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/Makefile 2013-07-26 19:36:59.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/Makefile 2013-07-26 19:37:08.000000000 +0000 +@@ -1,5 +1,11 @@ + ifeq ($(CONFIG_MACH_BCM2708),y) + ++############################################################################## ++# ++# This section is for building the RaspberryPi model ++# ++############################################################################## ++ + obj-$(CONFIG_BCM2708_VCHIQ) += vchiq.o + + vchiq-objs := \ +@@ -16,3 +22,80 @@ + + endif + ++ifeq ($(CONFIG_ARCH_KONA),y) ++ ++############################################################################## ++# ++# This section is for building the Capri/Island model ++# ++############################################################################## ++ ++# Remove the quotes from the platform config name ++VCHIQ_PLATFORM_CONFIG = $(patsubst "%",%,$(CONFIG_VCHIQ_PLATFORM_CFG_NAME)) ++ ++$(info VCHIQ_PLATFORM_CONFIG = $(VCHIQ_PLATFORM_CONFIG)) ++include $(srctree)/drivers/misc/vc04_services/interface/vchiq_arm/platform-cfg/$(VCHIQ_PLATFORM_CONFIG).mk ++ ++$(info Building for MAP build system) ++$(info CONFIG_ARCH_KONA = $(CONFIG_ARCH_KONA)) ++ ++EXTRA_CFLAGS += -Wall -Wstrict-prototypes -Wno-trigraphs -O2 -Wno-declaration-after-statement -Wno-parentheses ++ ++EXTRA_CFLAGS += -I"drivers/misc/vc04_services/" ++EXTRA_CFLAGS += -I"drivers/misc/vc04_services/interface/vchiq_arm" ++EXTRA_CFLAGS += -I"drivers/misc/vc04_services/interface/debug_sym" ++EXTRA_CFLAGS += -I"include/linux/broadcom" ++ ++EXTRA_CFLAGS += -Werror ++ ++VCHIQ_HOST_BUS_ALIGNMENT = 3 ++ ++EXTRA_CFLAGS += -DOS_ASSERT_FAILURE ++EXTRA_CFLAGS += -D__STDC_VERSION=199901L ++EXTRA_CFLAGS += -D__STDC_VERSION__=199901L ++EXTRA_CFLAGS += -D__VCCOREVER__=0 ++EXTRA_CFLAGS += -D__linux__ ++EXTRA_CFLAGS += -D__KERNEL__ ++EXTRA_CFLAGS += -DVCHIQ_HOST_BUS_ALIGNMENT=$(VCHIQ_HOST_BUS_ALIGNMENT) ++EXTRA_CFLAGS += -DVCHIQ_SLOT_PADDING=16 ++EXTRA_CFLAGS += -DVCHIQ_ARM_SIDE ++EXTRA_CFLAGS += -DUSE_VCHIQ_ARM ++ifeq ($(VCHIQ_SM_ALLOC),vcddr) ++EXTRA_CFLAGS += -DVCHIQ_SM_ALLOC_VCDDR ++endif ++ ++obj-$(CONFIG_KONA_VCHIQ) += vc-vchiq.o ++vc-vchiq-objs := \ ++ interface/vchiq_arm/vchiq_arm.o \ ++ interface/vchiq_arm/vchiq_connected.o \ ++ interface/vchiq_arm/vchiq_core.o \ ++ interface/vchiq_arm/vchiq_kern_lib.o \ ++ interface/vchiq_arm/vchiq_shim.o \ ++ interface/vchiq_arm/vchiq_util.o \ ++ interface/vchiq_arm/vchiq_kona_arm.o \ ++ interface/vchiq_arm/vchiq_$(VCHIQ_PLATFORM)_arm.o \ ++ interface/vchiq_arm/vchiq_version.o \ ++ interface/vchiq_arm/vchiq_proc.o ++ifeq ($(VCHIQ_SM_ALLOC),vcddr) ++vc-vchiq-objs += \ ++ interface/debug_sym/debug_sym.o ++endif ++ ++obj-$(CONFIG_KONA_VCHIQ_MEMDRV) += vc-vchiq-memdrv-kona.o ++vc-vchiq-memdrv-kona-objs := \ ++ interface/vchiq_arm/vchiq_memdrv_kona.o ++ ++genversion = drivers/misc/vc04_services/interface/vchiq_arm/vchiq_genversion ++ ++GENVERSION_SRC_ROOT_DIR = . ++ifeq ($(CONFIG_ANDROID),y) ++GENVERSION_SRC_ROOT_DIR = $(srctree) ++endif ++ ++$(obj)/interface/vchiq_arm/vchiq_version.c: $(genversion) FORCE ++ echo "(new) Generating $@ ..." ++ perl $(srctree)/$(genversion) vchiq $(GENVERSION_SRC_ROOT_DIR) > $@ ++ ++clean-files := vchiq_version.c ++ ++endif diff -Nru linux-3.2.46/debian/patches/rpi/rpi_267_91f1cdccb0b70e2bed1ab68a237ba1629c5af5f8.patch linux-3.2.46/debian/patches/rpi/rpi_267_91f1cdccb0b70e2bed1ab68a237ba1629c5af5f8.patch --- linux-3.2.46/debian/patches/rpi/rpi_267_91f1cdccb0b70e2bed1ab68a237ba1629c5af5f8.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_267_91f1cdccb0b70e2bed1ab68a237ba1629c5af5f8.patch 2013-07-26 19:37:10.000000000 +0000 @@ -0,0 +1,387 @@ +commit 91f1cdccb0b70e2bed1ab68a237ba1629c5af5f8 +Author: popcornmix +Date: Mon Oct 15 18:54:50 2012 +0100 + + Revert "Add in missed vchiq files" + + This reverts commit a542809e00a8e14984866a73547e0f1efcce57c3. + +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_build_info.h +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_build_info.h 2013-07-26 19:36:57.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,22 +0,0 @@ +-/* +- * Copyright (c) 2010-2011 Broadcom. All rights reserved. +- * +- * This program is free software; you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation; either version 2 of the License, or +- * (at your option) any later version. +- * +- * This program is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with this program; if not, write to the Free Software +- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +- */ +- +-const char *vchiq_get_build_hostname(void); +-const char *vchiq_get_build_version(void); +-const char *vchiq_get_build_time(void); +-const char *vchiq_get_build_date(void); +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_genversion +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_genversion 2013-07-26 19:36:57.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,87 +0,0 @@ +-#!/usr/bin/perl -w +- +-use strict; +- +-# +-# Generate a version from available information +-# +- +-my $prefix = shift @ARGV; +-my $root = shift @ARGV; +- +- +-if ( not defined $root ) { +- die "usage: $0 prefix root-dir\n"; +-} +- +-if ( ! -d $root ) { +- die "root directory $root not found\n"; +-} +- +-my $version = "unknown"; +-my $tainted = ""; +- +-if ( -d "$root/.git" ) { +- # attempt to work out git version. only do so +- # on a linux build host, as cygwin builds are +- # already slow enough +- +- if ( -f "/usr/bin/git" || -f "/usr/local/bin/git" ) { +- if (not open(F, "git --git-dir $root/.git rev-parse --verify HEAD|")) { +- $version = "no git version"; +- } +- else { +- $version = ; +- $version =~ s/[ \r\n]*$//; # chomp may not be enough (cygwin). +- $version =~ s/^[ \r\n]*//; # chomp may not be enough (cygwin). +- } +- +- if (open(G, "git --git-dir $root/.git status --porcelain|")) { +- $tainted = ; +- $tainted =~ s/[ \r\n]*$//; # chomp may not be enough (cygwin). +- $tainted =~ s/^[ \r\n]*//; # chomp may not be enough (cygwin). +- if (length $tainted) { +- $version = join ' ', $version, "(tainted)"; +- } +- else { +- $version = join ' ', $version, "(clean)"; +- } +- } +- } +-} +- +-my $hostname = `hostname`; +-$hostname =~ s/[ \r\n]*$//; # chomp may not be enough (cygwin). +-$hostname =~ s/^[ \r\n]*//; # chomp may not be enough (cygwin). +- +- +-print STDERR "Version $version\n"; +-print < +- +-VC_DEBUG_DECLARE_STRING_VAR( ${prefix}_build_hostname, "$hostname" ); +-VC_DEBUG_DECLARE_STRING_VAR( ${prefix}_build_version, "$version" ); +-VC_DEBUG_DECLARE_STRING_VAR( ${prefix}_build_time, __TIME__ ); +-VC_DEBUG_DECLARE_STRING_VAR( ${prefix}_build_date, __DATE__ ); +- +-const char *vchiq_get_build_hostname( void ) +-{ +- return vchiq_build_hostname; +-} +- +-const char *vchiq_get_build_version( void ) +-{ +- return vchiq_build_version; +-} +- +-const char *vchiq_get_build_date( void ) +-{ +- return vchiq_build_date; +-} +- +-const char *vchiq_get_build_time( void ) +-{ +- return vchiq_build_time; +-} +-EOF +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_proc.c +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_proc.c 2013-07-26 19:36:57.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,223 +0,0 @@ +-/* +- * Copyright (c) 2012 Broadcom Corporation. All rights reserved. +- * +- * This program is free software; you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation; either version 2 of the License, or +- * (at your option) any later version. +- * +- * This program is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- * +- * You should have received a copy of the GNU General Public License +- * along with this program; if not, write to the Free Software +- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +- */ +- +- +-#include +-#include "vchiq_core.h" +-#include "vchiq_arm.h" +- +-struct vchiq_proc_info { +- /* Global 'vc' proc entry used by all instances */ +- struct proc_dir_entry *vc_cfg_dir; +- +- /* one entry per client process */ +- struct proc_dir_entry *clients; +- +- /* log categories */ +- struct proc_dir_entry *log_categories; +-}; +- +-static struct vchiq_proc_info proc_info; +- +-struct proc_dir_entry *vchiq_proc_top(void) +-{ +- BUG_ON(proc_info.vc_cfg_dir == NULL); +- return proc_info.vc_cfg_dir; +-} +- +-/**************************************************************************** +-* +-* log category entries +-* +-***************************************************************************/ +-#define PROC_WRITE_BUF_SIZE 256 +- +-#define VCHIQ_LOG_ERROR_STR "error" +-#define VCHIQ_LOG_WARNING_STR "warning" +-#define VCHIQ_LOG_INFO_STR "info" +-#define VCHIQ_LOG_TRACE_STR "trace" +- +-static int log_cfg_read(char *buffer, +- char **start, +- off_t off, +- int count, +- int *eof, +- void *data) +-{ +- int len = 0; +- char *log_value = NULL; +- +- switch (*((int *)data)) { +- case VCHIQ_LOG_ERROR: +- log_value = VCHIQ_LOG_ERROR_STR; +- break; +- case VCHIQ_LOG_WARNING: +- log_value = VCHIQ_LOG_WARNING_STR; +- break; +- case VCHIQ_LOG_INFO: +- log_value = VCHIQ_LOG_INFO_STR; +- break; +- case VCHIQ_LOG_TRACE: +- log_value = VCHIQ_LOG_TRACE_STR; +- break; +- default: +- break; +- } +- +- len += sprintf(buffer + len, +- "%s\n", +- log_value ? log_value : "(null)"); +- +- return len; +-} +- +- +-static int log_cfg_write(struct file *file, +- const char __user *buffer, +- unsigned long count, +- void *data) +-{ +- int *log_module = data; +- char kbuf[PROC_WRITE_BUF_SIZE + 1]; +- +- (void)file; +- +- memset(kbuf, 0, PROC_WRITE_BUF_SIZE + 1); +- if (count >= PROC_WRITE_BUF_SIZE) +- count = PROC_WRITE_BUF_SIZE; +- +- if (copy_from_user(kbuf, +- buffer, +- count) != 0) +- return -EFAULT; +- kbuf[count - 1] = 0; +- +- if (strncmp("error", kbuf, strlen("error")) == 0) +- *log_module = VCHIQ_LOG_ERROR; +- else if (strncmp("warning", kbuf, strlen("warning")) == 0) +- *log_module = VCHIQ_LOG_WARNING; +- else if (strncmp("info", kbuf, strlen("info")) == 0) +- *log_module = VCHIQ_LOG_INFO; +- else if (strncmp("trace", kbuf, strlen("trace")) == 0) +- *log_module = VCHIQ_LOG_TRACE; +- else +- *log_module = VCHIQ_LOG_DEFAULT; +- +- return count; +-} +- +-/* Log category proc entries */ +-struct vchiq_proc_log_entry { +- const char *name; +- int *plevel; +- struct proc_dir_entry *dir; +-}; +- +-static struct vchiq_proc_log_entry vchiq_proc_log_entries[] = { +- { "core", &vchiq_core_log_level }, +- { "msg", &vchiq_core_msg_log_level }, +- { "sync", &vchiq_sync_log_level }, +- { "arm", &vchiq_arm_log_level }, +-}; +-static int n_log_entries = +- sizeof(vchiq_proc_log_entries)/sizeof(vchiq_proc_log_entries[0]); +- +-/* create an entry under /proc/vc/log for each log category */ +-static int vchiq_proc_create_log_entries(struct proc_dir_entry *top) +-{ +- struct proc_dir_entry *dir; +- size_t i; +- int ret = 0; +- +- dir = proc_mkdir("log", proc_info.vc_cfg_dir); +- if (!dir) +- return -ENOMEM; +- proc_info.log_categories = dir; +- +- for (i = 0; i < n_log_entries; i++) { +- dir = create_proc_entry(vchiq_proc_log_entries[i].name, +- 0644, +- proc_info.log_categories); +- if (!dir) { +- ret = -ENOMEM; +- break; +- } +- +- dir->read_proc = &log_cfg_read; +- dir->write_proc = &log_cfg_write; +- dir->data = (void *)vchiq_proc_log_entries[i].plevel; +- +- vchiq_proc_log_entries[i].dir = dir; +- } +- return ret; +-} +- +- +-int vchiq_proc_init(void) +-{ +- BUG_ON(proc_info.vc_cfg_dir != NULL); +- +- proc_info.vc_cfg_dir = proc_mkdir("vc", NULL); +- if (proc_info.vc_cfg_dir == NULL) +- goto fail; +- +- proc_info.clients = proc_mkdir("clients", +- proc_info.vc_cfg_dir); +- if (!proc_info.clients) +- goto fail; +- +- if (vchiq_proc_create_log_entries(proc_info.vc_cfg_dir) != 0) +- goto fail; +- +- return 0; +- +-fail: +- vchiq_proc_deinit(); +- vchiq_log_error(vchiq_arm_log_level, +- "%s: failed to create proc directory", +- __func__); +- +- return -ENOMEM; +-} +- +-/* remove all the proc entries */ +-void vchiq_proc_deinit(void) +-{ +- /* log category entries */ +- if (proc_info.log_categories) { +- size_t i; +- for (i = 0; i < n_log_entries; i++) +- if (vchiq_proc_log_entries[i].dir) +- remove_proc_entry( +- vchiq_proc_log_entries[i].name, +- proc_info.log_categories); +- +- remove_proc_entry(proc_info.log_categories->name, +- proc_info.vc_cfg_dir); +- } +- if (proc_info.clients) +- remove_proc_entry(proc_info.clients->name, +- proc_info.vc_cfg_dir); +- if (proc_info.vc_cfg_dir) +- remove_proc_entry(proc_info.vc_cfg_dir->name, NULL); +-} +- +-struct proc_dir_entry *vchiq_clients_top(void) +-{ +- return proc_info.clients; +-} +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_version.c +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_version.c 2013-07-26 19:36:57.000000000 +0000 ++++ /dev/null 1970-01-01 00:00:00.000000000 +0000 +@@ -1,27 +0,0 @@ +-#include "vchiq_build_info.h" +-#include +- +-VC_DEBUG_DECLARE_STRING_VAR( vchiq_build_hostname, "dc4-arm-01" ); +-VC_DEBUG_DECLARE_STRING_VAR( vchiq_build_version, "9245b4c35b99b3870e1f7dc598c5692b3c66a6f0 (tainted)" ); +-VC_DEBUG_DECLARE_STRING_VAR( vchiq_build_time, __TIME__ ); +-VC_DEBUG_DECLARE_STRING_VAR( vchiq_build_date, __DATE__ ); +- +-const char *vchiq_get_build_hostname( void ) +-{ +- return vchiq_build_hostname; +-} +- +-const char *vchiq_get_build_version( void ) +-{ +- return vchiq_build_version; +-} +- +-const char *vchiq_get_build_date( void ) +-{ +- return vchiq_build_date; +-} +- +-const char *vchiq_get_build_time( void ) +-{ +- return vchiq_build_time; +-} diff -Nru linux-3.2.46/debian/patches/rpi/rpi_268_10182a3bc434b27740f81c2b836a1af943060241.patch linux-3.2.46/debian/patches/rpi/rpi_268_10182a3bc434b27740f81c2b836a1af943060241.patch --- linux-3.2.46/debian/patches/rpi/rpi_268_10182a3bc434b27740f81c2b836a1af943060241.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_268_10182a3bc434b27740f81c2b836a1af943060241.patch 2013-07-26 19:37:17.000000000 +0000 @@ -0,0 +1,24916 @@ +commit 10182a3bc434b27740f81c2b836a1af943060241 +Author: popcornmix +Date: Mon Oct 15 18:54:52 2012 +0100 + + Revert "Move to version 5 of VCHIQ. Note: this requires a corresponding start.elf and /opt/vc/lib update" + + This reverts commit eb0c5608f3fd94fa316135e71edfb2d359b73203. + +Index: linux-3.2.46/drivers/misc/vc04_services/Kconfig +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/Kconfig 2013-07-26 19:37:08.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/Kconfig 2013-07-26 19:37:11.000000000 +0000 +@@ -1,10 +1,7 @@ + config BCM2708_VCHIQ + tristate "Videocore VCHIQ" + depends on MACH_BCM2708 +- default CONFIG_BCM_VC_SERVICES +- help +- Kernel to VideoCore communication interface for the +- BCM2708 family of products. +- Defaults to Y when the Broadcom Videocore services +- are included in the build, N otherwise. ++ default y ++ help ++ Helper for communication for VideoCore. + +Index: linux-3.2.46/drivers/misc/vc04_services/Makefile +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/Makefile 2013-07-26 19:37:08.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/Makefile 2013-07-26 19:37:11.000000000 +0000 +@@ -1,101 +1,21 @@ +-ifeq ($(CONFIG_MACH_BCM2708),y) +- +-############################################################################## +-# +-# This section is for building the RaspberryPi model +-# +-############################################################################## +- + obj-$(CONFIG_BCM2708_VCHIQ) += vchiq.o + + vchiq-objs := \ + interface/vchiq_arm/vchiq_core.o \ ++ interface/vchiq_arm/vchiq_shim.o \ ++ interface/vchiq_arm/vchiq_util.o \ + interface/vchiq_arm/vchiq_arm.o \ + interface/vchiq_arm/vchiq_kern_lib.o \ + interface/vchiq_arm/vchiq_2835_arm.o \ +- interface/vchiq_arm/vchiq_proc.o \ +- interface/vchiq_arm/vchiq_shim.o \ +- interface/vchiq_arm/vchiq_util.o \ +- interface/vchiq_arm/vchiq_connected.o \ +- +-EXTRA_CFLAGS += -DVCOS_VERIFY_BKPTS=1 -Idrivers/misc/vc04_services -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 +- +-endif +- +-ifeq ($(CONFIG_ARCH_KONA),y) +- +-############################################################################## +-# +-# This section is for building the Capri/Island model +-# +-############################################################################## +- +-# Remove the quotes from the platform config name +-VCHIQ_PLATFORM_CONFIG = $(patsubst "%",%,$(CONFIG_VCHIQ_PLATFORM_CFG_NAME)) +- +-$(info VCHIQ_PLATFORM_CONFIG = $(VCHIQ_PLATFORM_CONFIG)) +-include $(srctree)/drivers/misc/vc04_services/interface/vchiq_arm/platform-cfg/$(VCHIQ_PLATFORM_CONFIG).mk +- +-$(info Building for MAP build system) +-$(info CONFIG_ARCH_KONA = $(CONFIG_ARCH_KONA)) +- +-EXTRA_CFLAGS += -Wall -Wstrict-prototypes -Wno-trigraphs -O2 -Wno-declaration-after-statement -Wno-parentheses +- +-EXTRA_CFLAGS += -I"drivers/misc/vc04_services/" +-EXTRA_CFLAGS += -I"drivers/misc/vc04_services/interface/vchiq_arm" +-EXTRA_CFLAGS += -I"drivers/misc/vc04_services/interface/debug_sym" +-EXTRA_CFLAGS += -I"include/linux/broadcom" +- +-EXTRA_CFLAGS += -Werror +- +-VCHIQ_HOST_BUS_ALIGNMENT = 3 +- +-EXTRA_CFLAGS += -DOS_ASSERT_FAILURE +-EXTRA_CFLAGS += -D__STDC_VERSION=199901L +-EXTRA_CFLAGS += -D__STDC_VERSION__=199901L +-EXTRA_CFLAGS += -D__VCCOREVER__=0 +-EXTRA_CFLAGS += -D__linux__ +-EXTRA_CFLAGS += -D__KERNEL__ +-EXTRA_CFLAGS += -DVCHIQ_HOST_BUS_ALIGNMENT=$(VCHIQ_HOST_BUS_ALIGNMENT) +-EXTRA_CFLAGS += -DVCHIQ_SLOT_PADDING=16 +-EXTRA_CFLAGS += -DVCHIQ_ARM_SIDE +-EXTRA_CFLAGS += -DUSE_VCHIQ_ARM +-ifeq ($(VCHIQ_SM_ALLOC),vcddr) +-EXTRA_CFLAGS += -DVCHIQ_SM_ALLOC_VCDDR +-endif +- +-obj-$(CONFIG_KONA_VCHIQ) += vc-vchiq.o +-vc-vchiq-objs := \ +- interface/vchiq_arm/vchiq_arm.o \ +- interface/vchiq_arm/vchiq_connected.o \ +- interface/vchiq_arm/vchiq_core.o \ +- interface/vchiq_arm/vchiq_kern_lib.o \ +- interface/vchiq_arm/vchiq_shim.o \ +- interface/vchiq_arm/vchiq_util.o \ +- interface/vchiq_arm/vchiq_kona_arm.o \ +- interface/vchiq_arm/vchiq_$(VCHIQ_PLATFORM)_arm.o \ +- interface/vchiq_arm/vchiq_version.o \ +- interface/vchiq_arm/vchiq_proc.o +-ifeq ($(VCHIQ_SM_ALLOC),vcddr) +-vc-vchiq-objs += \ +- interface/debug_sym/debug_sym.o +-endif +- +-obj-$(CONFIG_KONA_VCHIQ_MEMDRV) += vc-vchiq-memdrv-kona.o +-vc-vchiq-memdrv-kona-objs := \ +- interface/vchiq_arm/vchiq_memdrv_kona.o +- +-genversion = drivers/misc/vc04_services/interface/vchiq_arm/vchiq_genversion ++ interface/vcos/linuxkernel/vcos_linuxkernel.o \ ++ interface/vcos/linuxkernel/vcos_thread_map.o \ ++ interface/vcos/linuxkernel/vcos_linuxkernel_cfg.o \ ++ interface/vcos/generic/vcos_generic_event_flags.o \ ++ interface/vcos/generic/vcos_logcat.o \ ++ interface/vcos/generic/vcos_mem_from_malloc.o \ ++ interface/vcos/generic/vcos_cmd.o + +-GENVERSION_SRC_ROOT_DIR = . +-ifeq ($(CONFIG_ANDROID),y) +-GENVERSION_SRC_ROOT_DIR = $(srctree) +-endif ++EXTRA_CFLAGS += -DVCOS_VERIFY_BKPTS=1 -DUSE_VCHIQ_ARM -D__VCCOREVER__=0x04000000 -Idrivers/misc/vc04_services -Idrivers/misc/vc04_services/interface/vcos/linuxkernel + +-$(obj)/interface/vchiq_arm/vchiq_version.c: $(genversion) FORCE +- echo "(new) Generating $@ ..." +- perl $(srctree)/$(genversion) vchiq $(GENVERSION_SRC_ROOT_DIR) > $@ + +-clean-files := vchiq_version.c + +-endif +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vchi/connections/connection.h +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vchi/connections/connection.h 2013-07-26 19:36:51.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vchi/connections/connection.h 2013-07-26 19:37:11.000000000 +0000 +@@ -1,5 +1,5 @@ + /* +- * Copyright (c) 2010-2012 Broadcom. All rights reserved. ++ * Copyright (c) 2010-2011 Broadcom Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by +@@ -19,10 +19,6 @@ + #ifndef CONNECTION_H_ + #define CONNECTION_H_ + +-#include +-#include +-#include +- + #include "interface/vchi/vchi_cfg_internal.h" + #include "interface/vchi/vchi_common.h" + #include "interface/vchi/message_drivers/message.h" +@@ -54,15 +50,15 @@ + + // Routine to create a service + typedef int32_t (*VCHI_CONNECTION_SERVICE_CONNECT_T)( VCHI_CONNECTION_STATE_T *state_handle, +- int32_t service_id, ++ vcos_fourcc_t service_id, + uint32_t rx_fifo_size, + uint32_t tx_fifo_size, + int server, + VCHI_CALLBACK_T callback, + void *callback_param, +- int32_t want_crc, +- int32_t want_unaligned_bulk_rx, +- int32_t want_unaligned_bulk_tx, ++ vcos_bool_t want_crc, ++ vcos_bool_t want_unaligned_bulk_rx, ++ vcos_bool_t want_unaligned_bulk_tx, + VCHI_CONNECTION_SERVICE_HANDLE_T *service_handle ); + + // Routine to close a service +@@ -120,7 +116,7 @@ + uint32_t *rx_timestamp ); + + // Routine to check whether the iterator has a next message +-typedef int32_t (*VCHI_CONNECTION_MSG_ITER_HAS_NEXT_T)( VCHI_CONNECTION_SERVICE_HANDLE_T service, ++typedef vcos_bool_t (*VCHI_CONNECTION_MSG_ITER_HAS_NEXT_T)( VCHI_CONNECTION_SERVICE_HANDLE_T service, + const VCHI_MSG_ITER_T *iter ); + + // Routine to advance the iterator +@@ -153,7 +149,7 @@ + void *bulk_handle ); + + // Routine to report if a server is available +-typedef int32_t (*VCHI_CONNECTION_SERVER_PRESENT)( VCHI_CONNECTION_STATE_T *state, int32_t service_id, int32_t peer_flags ); ++typedef int32_t (*VCHI_CONNECTION_SERVER_PRESENT)( VCHI_CONNECTION_STATE_T *state, vcos_fourcc_t service_id, int32_t peer_flags ); + + // Routine to report the number of RX slots available + typedef int (*VCHI_CONNECTION_RX_SLOTS_AVAILABLE)( const VCHI_CONNECTION_STATE_T *state ); +@@ -163,7 +159,7 @@ + + // Callback to indicate that the other side has added a buffer to the rx bulk DMA FIFO + typedef void (*VCHI_CONNECTION_RX_BULK_BUFFER_ADDED)(VCHI_CONNECTION_STATE_T *state, +- int32_t service, ++ vcos_fourcc_t service, + uint32_t length, + MESSAGE_TX_CHANNEL_T channel, + uint32_t channel_params, +@@ -171,10 +167,10 @@ + uint32_t data_offset); + + // Callback to inform a service that a Xon or Xoff message has been received +-typedef void (*VCHI_CONNECTION_FLOW_CONTROL)(VCHI_CONNECTION_STATE_T *state, int32_t service_id, int32_t xoff); ++typedef void (*VCHI_CONNECTION_FLOW_CONTROL)(VCHI_CONNECTION_STATE_T *state, vcos_fourcc_t service_id, int32_t xoff); + + // Callback to inform a service that a server available reply message has been received +-typedef void (*VCHI_CONNECTION_SERVER_AVAILABLE_REPLY)(VCHI_CONNECTION_STATE_T *state, int32_t service_id, uint32_t flags); ++typedef void (*VCHI_CONNECTION_SERVER_AVAILABLE_REPLY)(VCHI_CONNECTION_STATE_T *state, vcos_fourcc_t service_id, uint32_t flags); + + // Callback to indicate that bulk auxiliary messages have arrived + typedef void (*VCHI_CONNECTION_BULK_AUX_RECEIVED)(VCHI_CONNECTION_STATE_T *state); +@@ -189,7 +185,7 @@ + typedef void (*VCHI_CONNECTION_DISCONNECT)(VCHI_CONNECTION_STATE_T *state, uint32_t flags); + + // Callback to inform of a power control request +-typedef void (*VCHI_CONNECTION_POWER_CONTROL)(VCHI_CONNECTION_STATE_T *state, MESSAGE_TX_CHANNEL_T channel, int32_t enable); ++typedef void (*VCHI_CONNECTION_POWER_CONTROL)(VCHI_CONNECTION_STATE_T *state, MESSAGE_TX_CHANNEL_T channel, vcos_bool_t enable); + + // allocate memory suitably aligned for this connection + typedef void * (*VCHI_BUFFER_ALLOCATE)(VCHI_CONNECTION_SERVICE_HANDLE_T service_handle, uint32_t * length); +@@ -303,7 +299,7 @@ + const VCHI_CONNECTION_API_T *api; + VCHI_CONNECTION_STATE_T *state; + #ifdef VCHI_COARSE_LOCKING +- struct semaphore sem; ++ VCOS_SEMAPHORE_T sem; + #endif + }; + +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vchi/message_drivers/message.h +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vchi/message_drivers/message.h 2013-07-26 19:36:51.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vchi/message_drivers/message.h 2013-07-26 19:37:11.000000000 +0000 +@@ -1,5 +1,5 @@ + /* +- * Copyright (c) 2010-2012 Broadcom. All rights reserved. ++ * Copyright (c) 2010-2011 Broadcom Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by +@@ -19,11 +19,8 @@ + #ifndef _VCHI_MESSAGE_H_ + #define _VCHI_MESSAGE_H_ + +-#include +-#include +-#include +- + #include "interface/vchi/vchi_cfg_internal.h" ++#include "interface/vcos/vcos.h" + #include "interface/vchi/vchi_common.h" + + +@@ -66,7 +63,7 @@ + struct rx_msg_slot_info *next; + //struct slot_info *prev; + #if !defined VCHI_COARSE_LOCKING +- struct semaphore sem; ++ VCOS_SEMAPHORE_T sem; + #endif + + uint8_t *addr; // base address of slot +@@ -87,7 +84,7 @@ + typedef struct rx_bulk_slotinfo_t { + struct rx_bulk_slotinfo_t *next; + +- struct semaphore *blocking; ++ VCOS_SEMAPHORE_T *blocking; + + // needed by DMA + void *addr; +@@ -130,7 +127,7 @@ + uint16_t slot_delta; // whether this message indicated slot delta + uint32_t len; // length of message + RX_MSG_SLOTINFO_T *slot; // slot this message is in +- int32_t service; // service id this message is destined for ++ vcos_fourcc_t service; // service id this message is destined for + uint32_t tx_timestamp; // timestamp from the header + uint32_t rx_timestamp; // timestamp when we parsed it + } message; +@@ -159,14 +156,14 @@ + VCHI_MDRIVER_HANDLE_T *(*open)( VCHI_MESSAGE_DRIVER_OPEN_T *params, void *state ); + int32_t (*suspending)( VCHI_MDRIVER_HANDLE_T *handle ); + int32_t (*resumed)( VCHI_MDRIVER_HANDLE_T *handle ); +- int32_t (*power_control)( VCHI_MDRIVER_HANDLE_T *handle, MESSAGE_TX_CHANNEL_T, int32_t enable ); ++ int32_t (*power_control)( VCHI_MDRIVER_HANDLE_T *handle, MESSAGE_TX_CHANNEL_T, vcos_bool_t enable ); + int32_t (*add_msg_rx_slot)( VCHI_MDRIVER_HANDLE_T *handle, RX_MSG_SLOTINFO_T *slot ); // rx message + int32_t (*add_bulk_rx)( VCHI_MDRIVER_HANDLE_T *handle, void *data, uint32_t len, RX_BULK_SLOTINFO_T *slot ); // rx data (bulk) + int32_t (*send)( VCHI_MDRIVER_HANDLE_T *handle, MESSAGE_TX_CHANNEL_T channel, const void *data, uint32_t len, VCHI_MSG_FLAGS_T flags, void *send_handle ); // tx (message & bulk) + void (*next_event)( VCHI_MDRIVER_HANDLE_T *handle, MESSAGE_EVENT_T *event ); // get the next event from message_driver + int32_t (*enable)( VCHI_MDRIVER_HANDLE_T *handle ); +- int32_t (*form_message)( VCHI_MDRIVER_HANDLE_T *handle, int32_t service_id, VCHI_MSG_VECTOR_T *vector, uint32_t count, void +- *address, uint32_t length_avail, uint32_t max_total_length, int32_t pad_to_fill, int32_t allow_partial ); ++ int32_t (*form_message)( VCHI_MDRIVER_HANDLE_T *handle, vcos_fourcc_t service_id, VCHI_MSG_VECTOR_T *vector, uint32_t count, void ++ *address, uint32_t length_avail, uint32_t max_total_length, vcos_bool_t pad_to_fill, vcos_bool_t allow_partial ); + + int32_t (*update_message)( VCHI_MDRIVER_HANDLE_T *handle, void *dest, int16_t *slot_count ); + int32_t (*buffer_aligned)( VCHI_MDRIVER_HANDLE_T *handle, int tx, int uncached, const void *address, const uint32_t length ); +@@ -175,7 +172,7 @@ + int (*rx_slot_size)( VCHI_MDRIVER_HANDLE_T *handle, int msg_size ); + int (*tx_slot_size)( VCHI_MDRIVER_HANDLE_T *handle, int msg_size ); + +- int32_t (*tx_supports_terminate)( const VCHI_MDRIVER_HANDLE_T *handle, MESSAGE_TX_CHANNEL_T channel ); ++ vcos_bool_t (*tx_supports_terminate)( const VCHI_MDRIVER_HANDLE_T *handle, MESSAGE_TX_CHANNEL_T channel ); + uint32_t (*tx_bulk_chunk_size)( const VCHI_MDRIVER_HANDLE_T *handle, MESSAGE_TX_CHANNEL_T channel ); + int (*tx_alignment)( const VCHI_MDRIVER_HANDLE_T *handle, MESSAGE_TX_CHANNEL_T channel ); + int (*rx_alignment)( const VCHI_MDRIVER_HANDLE_T *handle, MESSAGE_RX_CHANNEL_T channel ); +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vchi/vchi.h +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vchi/vchi.h 2013-07-26 19:36:51.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vchi/vchi.h 2013-07-26 19:37:11.000000000 +0000 +@@ -1,5 +1,5 @@ + /* +- * Copyright (c) 2010-2012 Broadcom. All rights reserved. ++ * Copyright (c) 2010-2011 Broadcom Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by +@@ -16,9 +16,14 @@ + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + ++/*============================================================================= ++Contains the protypes for the vchi functions. ++=============================================================================*/ ++ + #ifndef VCHI_H_ + #define VCHI_H_ + ++#include "interface/vcos/vcos.h" + #include "interface/vchi/vchi_cfg.h" + #include "interface/vchi/vchi_common.h" + #include "interface/vchi/connections/connection.h" +@@ -39,12 +44,6 @@ + #define VCHI_BULK_ALIGNED(x) (((unsigned long)(x) & (VCHI_BULK_ALIGN-1)) == 0) + #endif + +-struct vchi_version { +- uint32_t version; +- uint32_t version_min; +-}; +-#define VCHI_VERSION(v_) { v_, v_ } +-#define VCHI_VERSION_EX(v_, m_) { v_, m_ } + + typedef enum + { +@@ -89,8 +88,8 @@ + // Construct an entry in a msg vector for a message handle (h), starting at offset (o) of length (l) + #define VCHI_VEC_HANDLE(h,o,l) VCHI_VEC_HANDLE, { { (h), (o), (l) } } + +-// Macros to manipulate 'FOURCC' values +-#define MAKE_FOURCC(x) ((int32_t)( (x[0] << 24) | (x[1] << 16) | (x[2] << 8) | x[3] )) ++// Macros to manipulate fourcc_t values ++#define MAKE_FOURCC(x) ((fourcc_t)( (x[0] << 24) | (x[1] << 16) | (x[2] << 8) | x[3] )) + #define FOURCC_TO_CHAR(x) (x >> 24) & 0xFF,(x >> 16) & 0xFF,(x >> 8) & 0xFF, x & 0xFF + + +@@ -109,22 +108,15 @@ + + // structure used to provide the information needed to open a server or a client + typedef struct { +- struct vchi_version version; +- int32_t service_id; +- VCHI_CONNECTION_T *connection; +- uint32_t rx_fifo_size; +- uint32_t tx_fifo_size; +- VCHI_CALLBACK_T callback; +- void *callback_param; +- /* client intends to receive bulk transfers of +- odd lengths or into unaligned buffers */ +- int32_t want_unaligned_bulk_rx; +- /* client intends to transmit bulk transfers of +- odd lengths or out of unaligned buffers */ +- int32_t want_unaligned_bulk_tx; +- /* client wants to check CRCs on (bulk) xfers. +- Only needs to be set at 1 end - will do both directions. */ +- int32_t want_crc; ++ vcos_fourcc_t service_id; ++ VCHI_CONNECTION_T *connection; ++ uint32_t rx_fifo_size; ++ uint32_t tx_fifo_size; ++ VCHI_CALLBACK_T callback; ++ void *callback_param; ++ vcos_bool_t want_unaligned_bulk_rx; // client intends to receive bulk transfers of odd lengths or into unaligned buffers ++ vcos_bool_t want_unaligned_bulk_tx; // client intends to transmit bulk transfers of odd lengths or out of unaligned buffers ++ vcos_bool_t want_crc; // client wants to check CRCs on (bulk) transfers. Only needs to be set at 1 end - will do both directions. + } SERVICE_CREATION_T; + + // Opaque handle for a VCHI instance +@@ -277,7 +269,7 @@ + extern int32_t vchi_held_msg_release( VCHI_HELD_MSG_T *message ); + + // Indicates whether the iterator has a next message. +-extern int32_t vchi_msg_iter_has_next( const VCHI_MSG_ITER_T *iter ); ++extern vcos_bool_t vchi_msg_iter_has_next( const VCHI_MSG_ITER_T *iter ); + + // Return the pointer and length for the next message and advance the iterator. + extern int32_t vchi_msg_iter_next( VCHI_MSG_ITER_T *iter, +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vchi/vchi_cfg.h +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vchi/vchi_cfg.h 2013-07-26 19:36:51.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vchi/vchi_cfg.h 2013-07-26 19:37:11.000000000 +0000 +@@ -1,5 +1,5 @@ + /* +- * Copyright (c) 2010-2012 Broadcom. All rights reserved. ++ * Copyright (c) 2010-2011 Broadcom Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by +@@ -16,6 +16,11 @@ + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + ++/*============================================================================= ++Contains the #defines for the number of servers / clients etc, these can be ++over-ridden from the platform makefile if needed ++=============================================================================*/ ++ + #ifndef VCHI_CFG_H_ + #define VCHI_CFG_H_ + +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vchi/vchi_cfg_internal.h +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vchi/vchi_cfg_internal.h 2013-07-26 19:36:51.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vchi/vchi_cfg_internal.h 2013-07-26 19:37:11.000000000 +0000 +@@ -1,5 +1,5 @@ + /* +- * Copyright (c) 2010-2012 Broadcom. All rights reserved. ++ * Copyright (c) 2010-2011 Broadcom Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vchi/vchi_common.h +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vchi/vchi_common.h 2013-07-26 19:36:51.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vchi/vchi_common.h 2013-07-26 19:37:11.000000000 +0000 +@@ -1,5 +1,5 @@ + /* +- * Copyright (c) 2010-2012 Broadcom. All rights reserved. ++ * Copyright (c) 2010-2011 Broadcom Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by +@@ -16,6 +16,10 @@ + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + ++/*============================================================================= ++Contains global defs used by submodules within vchi. ++=============================================================================*/ ++ + #ifndef VCHI_COMMON_H_ + #define VCHI_COMMON_H_ + +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vchi/vchi_mh.h +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vchi/vchi_mh.h 2013-07-26 19:36:51.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vchi/vchi_mh.h 2013-07-26 19:37:11.000000000 +0000 +@@ -19,7 +19,7 @@ + #ifndef VCHI_MH_H_ + #define VCHI_MH_H_ + +-#include ++#include + + typedef int32_t VCHI_MEM_HANDLE_T; + #define VCHI_MEM_HANDLE_INVALID 0 +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq.h +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq.h 2013-07-26 19:36:51.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq.h 2013-07-26 19:37:11.000000000 +0000 +@@ -21,6 +21,7 @@ + + #include "vchiq_if.h" + #include "vchiq_util.h" ++#include "interface/vcos/vcos.h" + + #endif + +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_2835_arm.c +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_2835_arm.c 2013-07-26 19:36:51.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_2835_arm.c 2013-07-26 19:37:11.000000000 +0000 +@@ -24,9 +24,9 @@ + #include + #include + #include +-#include +-#include + #include ++#include ++#include + + #include + +@@ -40,14 +40,10 @@ + + #include "vchiq_arm.h" + #include "vchiq_2835.h" +-#include "vchiq_connected.h" + + #define MAX_FRAGMENTS (VCHIQ_NUM_CURRENT_BULKS * 2) + +-typedef struct vchiq_2835_state_struct { +- int inited; +- VCHIQ_ARM_STATE_T arm_state; +-} VCHIQ_2835_ARM_STATE_T; ++#define VCOS_LOG_CATEGORY (&vchiq_arm_log_category) + + static char *g_slot_mem; + static int g_slot_mem_size; +@@ -56,21 +52,29 @@ + static FRAGMENTS_T *g_free_fragments; + struct semaphore g_free_fragments_sema; + +-extern int vchiq_arm_log_level; +- ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,36) + static DEFINE_SEMAPHORE(g_free_fragments_mutex); ++#else ++static DECLARE_MUTEX(g_free_fragments_mutex); ++#endif + + static irqreturn_t + vchiq_doorbell_irq(int irq, void *dev_id); + + static int + create_pagelist(char __user *buf, size_t count, unsigned short type, +- struct task_struct *task, PAGELIST_T ** ppagelist); ++ struct task_struct *task, PAGELIST_T ** ppagelist); + + static void + free_pagelist(PAGELIST_T *pagelist, int actual); + + int __init ++vchiq_platform_vcos_init(void) ++{ ++ return (vcos_init() == VCOS_SUCCESS) ? 0 : -EINVAL; ++} ++ ++int __init + vchiq_platform_init(VCHIQ_STATE_T *state) + { + VCHIQ_SLOT_ZERO_T *vchiq_slot_zero; +@@ -86,49 +90,48 @@ + &g_slot_phys, GFP_ATOMIC); + + if (!g_slot_mem) { +- vchiq_log_error(vchiq_arm_log_level, +- "Unable to allocate channel memory"); ++ vcos_log_error("Unable to allocate channel memory"); + err = -ENOMEM; + goto failed_alloc; + } + +- WARN_ON(((int)g_slot_mem & (PAGE_SIZE - 1)) != 0); ++ vcos_assert(((int)g_slot_mem & (PAGE_SIZE - 1)) == 0); + + vchiq_slot_zero = vchiq_init_slots(g_slot_mem, g_slot_mem_size); +- if (!vchiq_slot_zero) { +- err = -EINVAL; +- goto failed_init_slots; ++ if (!vchiq_slot_zero) ++ { ++ err = -EINVAL; ++ goto failed_init_slots; + } + +- vchiq_slot_zero->platform_data[VCHIQ_PLATFORM_FRAGMENTS_OFFSET_IDX] = +- (int)g_slot_phys + g_slot_mem_size; +- vchiq_slot_zero->platform_data[VCHIQ_PLATFORM_FRAGMENTS_COUNT_IDX] = +- MAX_FRAGMENTS; ++ vchiq_slot_zero->platform_data[VCHIQ_PLATFORM_FRAGMENTS_OFFSET_IDX] = (int)g_slot_phys + g_slot_mem_size; ++ vchiq_slot_zero->platform_data[VCHIQ_PLATFORM_FRAGMENTS_COUNT_IDX] = MAX_FRAGMENTS; + + g_fragments_base = (FRAGMENTS_T *)(g_slot_mem + g_slot_mem_size); + g_slot_mem_size += frag_mem_size; + + g_free_fragments = g_fragments_base; + for (i = 0; i < (MAX_FRAGMENTS - 1); i++) { +- *(FRAGMENTS_T **)&g_fragments_base[i] = ++ *(FRAGMENTS_T **) & g_fragments_base[i] = + &g_fragments_base[i + 1]; + } +- *(FRAGMENTS_T **)&g_fragments_base[i] = NULL; ++ *(FRAGMENTS_T **) & g_fragments_base[i] = NULL; + sema_init(&g_free_fragments_sema, MAX_FRAGMENTS); + + if (vchiq_init_state(state, vchiq_slot_zero, 0/*slave*/) != +- VCHIQ_SUCCESS) { ++ VCHIQ_SUCCESS) ++ { + err = -EINVAL; + goto failed_vchiq_init; + } + + err = request_irq(VCHIQ_DOORBELL_IRQ, vchiq_doorbell_irq, +- IRQF_IRQPOLL, "VCHIQ doorbell", ++ IRQF_SAMPLE_RANDOM | IRQF_IRQPOLL, "VCHIQ doorbell", + state); +- if (err < 0) { +- vchiq_log_error(vchiq_arm_log_level, "%s: failed to register " +- "irq=%d err=%d", __func__, +- VCHIQ_DOORBELL_IRQ, err); ++ if (err < 0) ++ { ++ printk( KERN_ERR "%s: failed to register irq=%d err=%d\n", __func__, ++ VCHIQ_DOORBELL_IRQ, err ); + goto failed_request_irq; + } + +@@ -138,67 +141,39 @@ + + bcm_mailbox_write(MBOX_CHAN_VCHIQ, (unsigned int)g_slot_phys); + +- vchiq_log_info(vchiq_arm_log_level, +- "vchiq_init - done (slots %x, phys %x)", ++ vcos_log_info("vchiq_init - done (slots %x, phys %x)", + (unsigned int)vchiq_slot_zero, g_slot_phys); + +- vchiq_call_connected_callbacks(); +- +- return 0; ++ return 0; + + failed_request_irq: + failed_vchiq_init: + failed_init_slots: +- dma_free_coherent(NULL, g_slot_mem_size, g_slot_mem, g_slot_phys); ++ dma_free_coherent(NULL, g_slot_mem_size, g_slot_mem, g_slot_phys); + + failed_alloc: +- return err; ++ return err; + } + + void __exit + vchiq_platform_exit(VCHIQ_STATE_T *state) + { +- free_irq(VCHIQ_DOORBELL_IRQ, state); +- dma_free_coherent(NULL, g_slot_mem_size, +- g_slot_mem, g_slot_phys); +-} +- +- +-VCHIQ_STATUS_T +-vchiq_platform_init_state(VCHIQ_STATE_T *state) +-{ +- VCHIQ_STATUS_T status = VCHIQ_SUCCESS; +- state->platform_state = kzalloc(sizeof(VCHIQ_2835_ARM_STATE_T), GFP_KERNEL); +- ((VCHIQ_2835_ARM_STATE_T*)state->platform_state)->inited = 1; +- status = vchiq_arm_init_state(state, &((VCHIQ_2835_ARM_STATE_T*)state->platform_state)->arm_state); +- if(status != VCHIQ_SUCCESS) +- { +- ((VCHIQ_2835_ARM_STATE_T*)state->platform_state)->inited = 0; +- } +- return status; +-} +- +-VCHIQ_ARM_STATE_T* +-vchiq_platform_get_arm_state(VCHIQ_STATE_T *state) +-{ +- if(!((VCHIQ_2835_ARM_STATE_T*)state->platform_state)->inited) +- { +- BUG(); +- } +- return &((VCHIQ_2835_ARM_STATE_T*)state->platform_state)->arm_state; ++ free_irq(VCHIQ_DOORBELL_IRQ, state); ++ dma_free_coherent(NULL, g_slot_mem_size, ++ g_slot_mem, g_slot_phys); + } + + void + remote_event_signal(REMOTE_EVENT_T *event) + { +- wmb(); +- + event->fired = 1; + +- dsb(); /* data barrier operation */ ++ /* The test on the next line also ensures the write on the previous line ++ has completed */ + + if (event->armed) { + /* trigger vc interrupt */ ++ dsb(); /* data barrier operation */ + + writel(0, __io_address(ARM_0_BELL2)); + } +@@ -207,10 +182,13 @@ + int + vchiq_copy_from_user(void *dst, const void *src, int size) + { +- if ((uint32_t)src < TASK_SIZE) { ++ if ( (uint32_t)src < TASK_SIZE) ++ { + return copy_from_user(dst, src, size); +- } else { +- memcpy(dst, src, size); ++ } ++ else ++ { ++ memcpy( dst, src, size ); + return 0; + } + } +@@ -222,7 +200,7 @@ + PAGELIST_T *pagelist; + int ret; + +- WARN_ON(memhandle != VCHI_MEM_HANDLE_INVALID); ++ vcos_assert(memhandle == VCHI_MEM_HANDLE_INVALID); + + ret = create_pagelist((char __user *)offset, size, + (dir == VCHIQ_BULK_RECEIVE) +@@ -246,8 +224,7 @@ + void + vchiq_complete_bulk(VCHIQ_BULK_T *bulk) + { +- if (bulk && bulk->remote_data && bulk->actual) +- free_pagelist((PAGELIST_T *)bulk->remote_data, bulk->actual); ++ free_pagelist((PAGELIST_T *)bulk->remote_data, bulk->actual); + } + + void +@@ -257,57 +234,83 @@ + * This should only be called on the master (VideoCore) side, but + * provide an implementation to avoid the need for ifdefery. + */ +- BUG(); ++ vcos_assert(!"This code should not be called by the ARM on BCM2835"); + } + + void + vchiq_dump_platform_state(void *dump_context) + { +- char buf[80]; +- int len; +- len = snprintf(buf, sizeof(buf), +- " Platform: 2835 (VC master)"); +- vchiq_dump(dump_context, buf, len + 1); ++ char buf[80]; ++ int len; ++ len = vcos_snprintf(buf, sizeof(buf), ++ " Platform: 2835 (VC master)"); ++ vchiq_dump(dump_context, buf, len + 1); + } + + VCHIQ_STATUS_T + vchiq_platform_suspend(VCHIQ_STATE_T *state) + { ++ vcos_unused(state); ++ vcos_assert_msg(0, "Suspend/resume not supported"); + return VCHIQ_ERROR; + } + + VCHIQ_STATUS_T + vchiq_platform_resume(VCHIQ_STATE_T *state) + { +- return VCHIQ_SUCCESS; ++ vcos_unused(state); ++ vcos_assert_msg(0, "Suspend/resume not supported"); ++ return VCHIQ_ERROR; + } + + void + vchiq_platform_paused(VCHIQ_STATE_T *state) + { ++ vcos_unused(state); ++ vcos_assert_msg(0, "Suspend/resume not supported"); + } + + void + vchiq_platform_resumed(VCHIQ_STATE_T *state) + { ++ vcos_unused(state); ++ vcos_assert_msg(0, "Suspend/resume not supported"); + } + + int + vchiq_platform_videocore_wanted(VCHIQ_STATE_T* state) + { ++ vcos_unused(state); + return 1; // autosuspend not supported - videocore always wanted + } + ++#if VCOS_HAVE_TIMER + int + vchiq_platform_use_suspend_timer(void) + { + return 0; + } ++#endif + void + vchiq_dump_platform_use_state(VCHIQ_STATE_T *state) + { +- vchiq_log_info((vchiq_arm_log_level>=VCHIQ_LOG_INFO),"Suspend timer not in use"); ++ vcos_unused(state); + } ++ ++VCHIQ_STATUS_T ++vchiq_platform_init_state(VCHIQ_STATE_T *state) ++{ ++ vcos_unused(state); ++ return VCHIQ_SUCCESS; ++} ++ ++VCHIQ_ARM_STATE_T* ++vchiq_platform_get_arm_state(VCHIQ_STATE_T *state) ++{ ++ vcos_unused(state); ++ return NULL; ++} ++ + /* + * Local functions + */ +@@ -315,7 +318,7 @@ + static irqreturn_t + vchiq_doorbell_irq(int irq, void *dev_id) + { +- VCHIQ_STATE_T *state = dev_id; ++ VCHIQ_STATE_T *state = dev_id; + irqreturn_t ret = IRQ_NONE; + unsigned int status; + +@@ -331,17 +334,17 @@ + } + + /* There is a potential problem with partial cache lines (pages?) +-** at the ends of the block when reading. If the CPU accessed anything in +-** the same line (page?) then it may have pulled old data into the cache, +-** obscuring the new data underneath. We can solve this by transferring the +-** partial cache lines separately, and allowing the ARM to copy into the +-** cached area. +- +-** N.B. This implementation plays slightly fast and loose with the Linux +-** driver programming rules, e.g. its use of __virt_to_bus instead of +-** dma_map_single, but it isn't a multi-platform driver and it benefits +-** from increased speed as a result. +-*/ ++ at the ends of the block when reading. If the CPU accessed anything in ++ the same line (page?) then it may have pulled old data into the cache, ++ obscuring the new data underneath. We can solve this by transferring the ++ partial cache lines separately, and allowing the ARM to copy into the ++ cached area. ++ ++ N.B. This implementation plays slightly fast and loose with the Linux ++ driver programming rules, e.g. its use of __virt_to_bus instead of ++ dma_map_single, but it isn't a multi-platform driver and it benefits ++ from increased speed as a result. ++ */ + + static int + create_pagelist(char __user *buf, size_t count, unsigned short type, +@@ -360,16 +363,13 @@ + + *ppagelist = NULL; + +- /* Allocate enough storage to hold the page pointers and the page +- ** list +- */ +- pagelist = kmalloc(sizeof(PAGELIST_T) + ++ /* Allocate enough storage to hold the page pointers and the page list */ ++ pagelist = (PAGELIST_T *) kmalloc(sizeof(PAGELIST_T) + + (num_pages * sizeof(unsigned long)) + + (num_pages * sizeof(pages[0])), + GFP_KERNEL); + +- vchiq_log_trace(vchiq_arm_log_level, +- "create_pagelist - %x", (unsigned int)pagelist); ++ vcos_log_trace("create_pagelist - %x", (unsigned int)pagelist); + if (!pagelist) + return -ENOMEM; + +@@ -380,22 +380,17 @@ + actual_pages = get_user_pages(task, task->mm, + (unsigned long)buf & ~(PAGE_SIZE - 1), num_pages, + (type == PAGELIST_READ) /*Write */ , 0 /*Force */ , +- pages, NULL /*vmas */); ++ pages, NULL /*vmas */ ); + up_read(&task->mm->mmap_sem); + +- if (actual_pages != num_pages) +- { +- /* This is probably due to the process being killed */ +- while (actual_pages > 0) +- { +- actual_pages--; +- page_cache_release(pages[actual_pages]); +- } +- kfree(pagelist); +- if (actual_pages == 0) +- actual_pages = -ENOMEM; +- return actual_pages; +- } ++ if (actual_pages != num_pages) ++ { ++ for (i = 0; i < actual_pages; i++) { ++ page_cache_release(pages[i]); ++ } ++ kfree(pagelist); ++ return -EINVAL; ++ } + + pagelist->length = count; + pagelist->type = type; +@@ -428,8 +423,7 @@ + /* Partial cache lines (fragments) require special measures */ + if ((type == PAGELIST_READ) && + ((pagelist->offset & (CACHE_LINE_SIZE - 1)) || +- ((pagelist->offset + pagelist->length) & +- (CACHE_LINE_SIZE - 1)))) { ++ ((pagelist->offset + pagelist->length) & (CACHE_LINE_SIZE - 1)))) { + FRAGMENTS_T *fragments; + + if (down_interruptible(&g_free_fragments_sema) != 0) { +@@ -437,11 +431,11 @@ + return -EINTR; + } + +- WARN_ON(g_free_fragments == NULL); ++ vcos_assert(g_free_fragments != NULL); + + down(&g_free_fragments_mutex); + fragments = (FRAGMENTS_T *) g_free_fragments; +- WARN_ON(fragments == NULL); ++ vcos_assert(fragments != NULL); + g_free_fragments = *(FRAGMENTS_T **) g_free_fragments; + up(&g_free_fragments_mutex); + pagelist->type = +@@ -465,40 +459,39 @@ + struct page **pages; + unsigned int num_pages, i; + +- vchiq_log_trace(vchiq_arm_log_level, +- "free_pagelist - %x, %d", (unsigned int)pagelist, actual); ++ vcos_log_trace("free_pagelist - %x, %d", (unsigned int)pagelist, actual); + + num_pages = +- (pagelist->length + pagelist->offset + PAGE_SIZE - 1) / +- PAGE_SIZE; ++ (pagelist->length + pagelist->offset + PAGE_SIZE - 1) / PAGE_SIZE; + + pages = (struct page **)(pagelist->addrs + num_pages); + + /* Deal with any partial cache lines (fragments) */ + if (pagelist->type >= PAGELIST_READ_WITH_FRAGMENTS) { +- FRAGMENTS_T *fragments = g_fragments_base + +- (pagelist->type - PAGELIST_READ_WITH_FRAGMENTS); ++ FRAGMENTS_T *fragments = ++ g_fragments_base + (pagelist->type - ++ PAGELIST_READ_WITH_FRAGMENTS); + int head_bytes, tail_bytes; +- head_bytes = (CACHE_LINE_SIZE - pagelist->offset) & +- (CACHE_LINE_SIZE - 1); +- tail_bytes = (pagelist->offset + actual) & +- (CACHE_LINE_SIZE - 1); +- +- if ((actual >= 0) && (head_bytes != 0)) { +- if (head_bytes > actual) +- head_bytes = actual; +- +- memcpy((char *)page_address(pages[0]) + +- pagelist->offset, +- fragments->headbuf, +- head_bytes); +- } +- if ((actual >= 0) && (head_bytes < actual) && +- (tail_bytes != 0)) { +- memcpy((char *)page_address(pages[num_pages - 1]) + +- ((pagelist->offset + actual) & +- (PAGE_SIZE - 1) & ~(CACHE_LINE_SIZE - 1)), +- fragments->tailbuf, tail_bytes); ++ ++ if (actual >= 0) ++ { ++ if ((head_bytes = (CACHE_LINE_SIZE - pagelist->offset) & (CACHE_LINE_SIZE - 1)) != 0) { ++ if (head_bytes > actual) ++ head_bytes = actual; ++ ++ memcpy((char *)page_address(pages[0]) + ++ pagelist->offset, fragments->headbuf, ++ head_bytes); ++ } ++ if ((head_bytes < actual) && ++ (tail_bytes = ++ (pagelist->offset + actual) & (CACHE_LINE_SIZE - ++ 1)) != 0) { ++ memcpy((char *)page_address(pages[num_pages - 1]) + ++ ((pagelist->offset + actual) & (PAGE_SIZE - ++ 1) & ~(CACHE_LINE_SIZE - 1)), ++ fragments->tailbuf, tail_bytes); ++ } + } + + down(&g_free_fragments_mutex); +@@ -516,3 +509,4 @@ + + kfree(pagelist); + } ++ +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_arm.c +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_arm.c 2013-07-26 19:36:51.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_arm.c 2013-07-26 19:37:11.000000000 +0000 +@@ -26,10 +26,6 @@ + #include + #include + #include +-#include +-#include +-#include +-#include + + #include "vchiq_core.h" + #include "vchiq_ioctl.h" +@@ -49,128 +45,139 @@ + #define MAX_ELEMENTS 8 + #define MSG_QUEUE_SIZE 64 + +-#define KEEPALIVE_VER 1 +-#define KEEPALIVE_VER_MIN KEEPALIVE_VER ++#define VCOS_LOG_CATEGORY (&vchiq_arm_log_category) + +-/* Run time control of log level, based on KERN_XXX level. */ +-int vchiq_arm_log_level = VCHIQ_LOG_DEFAULT; +-int vchiq_susp_log_level = VCHIQ_LOG_DEFAULT; ++#define VCHIQ_ARM_VCSUSPEND_TASK_STACK 4096 + ++#if VCOS_HAVE_TIMER + #define SUSPEND_TIMER_TIMEOUT_MS 100 +-#define SUSPEND_RETRY_TIMER_TIMEOUT_MS 1000 +- +-#define VC_SUSPEND_NUM_OFFSET 3 /* number of values before idle which are -ve */ +-static const char *const suspend_state_names[] = { +- "VC_SUSPEND_FORCE_CANCELED", +- "VC_SUSPEND_REJECTED", +- "VC_SUSPEND_FAILED", +- "VC_SUSPEND_IDLE", +- "VC_SUSPEND_REQUESTED", +- "VC_SUSPEND_IN_PROGRESS", +- "VC_SUSPEND_SUSPENDED" +-}; +-#define VC_RESUME_NUM_OFFSET 1 /* number of values before idle which are -ve */ +-static const char *const resume_state_names[] = { +- "VC_RESUME_FAILED", +- "VC_RESUME_IDLE", +- "VC_RESUME_REQUESTED", +- "VC_RESUME_IN_PROGRESS", +- "VC_RESUME_RESUMED" +-}; +-/* The number of times we allow force suspend to timeout before actually +-** _forcing_ suspend. This is to cater for SW which fails to release vchiq +-** correctly - we don't want to prevent ARM suspend indefinitely in this case. +-*/ +-#define FORCE_SUSPEND_FAIL_MAX 8 +- +-/* The time in ms allowed for videocore to go idle when force suspend has been +- * requested */ +-#define FORCE_SUSPEND_TIMEOUT_MS 200 +- +- +-static void suspend_timer_callback(unsigned long context); +-static int vchiq_proc_add_instance(VCHIQ_INSTANCE_T instance); +-static void vchiq_proc_remove_instance(VCHIQ_INSTANCE_T instance); +- +- +-typedef struct user_service_struct { +- VCHIQ_SERVICE_T *service; +- void *userdata; +- VCHIQ_INSTANCE_T instance; +- int is_vchi; +- int dequeue_pending; +- int message_available_pos; +- int msg_insert; +- int msg_remove; +- struct semaphore insert_event; +- struct semaphore remove_event; +- VCHIQ_HEADER_T * msg_queue[MSG_QUEUE_SIZE]; ++static VCOS_TIMER_T g_suspend_timer; ++static void suspend_timer_callback(void *context); ++#endif ++ ++ ++typedef struct client_service_struct { ++ VCHIQ_SERVICE_T *service; ++ void *userdata; ++ VCHIQ_INSTANCE_T instance; ++ int handle; ++ int is_vchi; ++ volatile int dequeue_pending; ++ volatile int message_available_pos; ++ volatile int msg_insert; ++ volatile int msg_remove; ++ VCOS_EVENT_T insert_event; ++ VCOS_EVENT_T remove_event; ++ VCHIQ_HEADER_T *msg_queue[MSG_QUEUE_SIZE]; + } USER_SERVICE_T; + +-struct bulk_waiter_node { +- struct bulk_waiter bulk_waiter; +- int pid; +- struct list_head list; +-}; +- + struct vchiq_instance_struct { +- VCHIQ_STATE_T *state; +- VCHIQ_COMPLETION_DATA_T completions[MAX_COMPLETIONS]; +- int completion_insert; +- int completion_remove; +- struct semaphore insert_event; +- struct semaphore remove_event; +- struct mutex completion_mutex; +- +- int connected; +- int closing; +- int pid; +- int mark; +- +- struct list_head bulk_waiter_list; +- struct mutex bulk_waiter_list_mutex; +- +- struct proc_dir_entry *proc_entry; ++ VCHIQ_STATE_T *state; ++ VCHIQ_COMPLETION_DATA_T completions[MAX_COMPLETIONS]; ++ volatile int completion_insert; ++ volatile int completion_remove; ++ VCOS_EVENT_T insert_event; ++ VCOS_EVENT_T remove_event; ++ ++ USER_SERVICE_T services[MAX_SERVICES]; ++ ++ int connected; ++ int closing; ++ int pid; ++ int mark; + }; + +-typedef struct dump_context_struct { +- char __user *buf; +- size_t actual; +- size_t space; +- loff_t offset; ++typedef struct dump_context_struct ++{ ++ char __user *buf; ++ size_t actual; ++ size_t space; ++ loff_t offset; + } DUMP_CONTEXT_T; + ++VCOS_LOG_CAT_T vchiq_arm_log_category; ++ + static struct cdev vchiq_cdev; + static dev_t vchiq_devid; + static VCHIQ_STATE_T g_state; + static struct class *vchiq_class; + static struct device *vchiq_dev; +-static DEFINE_SPINLOCK(msg_queue_spinlock); + +-static const char *const ioctl_names[] = { +- "CONNECT", +- "SHUTDOWN", +- "CREATE_SERVICE", +- "REMOVE_SERVICE", +- "QUEUE_MESSAGE", +- "QUEUE_BULK_TRANSMIT", +- "QUEUE_BULK_RECEIVE", +- "AWAIT_COMPLETION", +- "DEQUEUE_MESSAGE", +- "GET_CLIENT_ID", +- "GET_CONFIG", +- "CLOSE_SERVICE", +- "USE_SERVICE", +- "RELEASE_SERVICE", +- "SET_SERVICE_OPTION", +- "DUMP_PHYS_MEM" ++static const char *ioctl_names[] = ++{ ++ "CONNECT", ++ "SHUTDOWN", ++ "CREATE_SERVICE", ++ "REMOVE_SERVICE", ++ "QUEUE_MESSAGE", ++ "QUEUE_BULK_TRANSMIT", ++ "QUEUE_BULK_RECEIVE", ++ "AWAIT_COMPLETION", ++ "DEQUEUE_MESSAGE", ++ "GET_CLIENT_ID", ++ "GET_CONFIG", ++ "CLOSE_SERVICE", ++ "USE_SERVICE", ++ "RELEASE_SERVICE", ++ "SET_SERVICE_OPTION", ++ "DUMP_PHYS_MEM" + }; + +-vchiq_static_assert((sizeof(ioctl_names)/sizeof(ioctl_names[0])) == +- (VCHIQ_IOC_MAX + 1)); ++vcos_static_assert(vcos_countof(ioctl_names) == (VCHIQ_IOC_MAX + 1)); ++ ++VCOS_LOG_LEVEL_T vchiq_default_arm_log_level = VCOS_LOG_ERROR; + + static void +-dump_phys_mem(void *virt_addr, uint32_t num_bytes); ++dump_phys_mem( void *virt_addr, uint32_t num_bytes ); ++ ++/**************************************************************************** ++* ++* find_service_by_handle ++* ++***************************************************************************/ ++ ++static inline USER_SERVICE_T *find_service_by_handle( ++ VCHIQ_INSTANCE_T instance, int handle ) ++{ ++ USER_SERVICE_T *user_service; ++ ++ if (( handle >= 0 ) ++ && ( handle < MAX_SERVICES )) ++ { ++ user_service = &instance->services[ handle ]; ++ ++ if ( user_service->service != NULL ) ++ { ++ return user_service; ++ } ++ } ++ ++ return NULL; ++} ++ ++/**************************************************************************** ++* ++* find_avail_service_handle ++* ++***************************************************************************/ ++ ++static inline USER_SERVICE_T *find_avail_service_handle( ++ VCHIQ_INSTANCE_T instance) ++{ ++ int handle; ++ ++ for ( handle = 0; handle < MAX_SERVICES; handle++ ) ++ { ++ if ( instance->services[handle].service == NULL ) ++ { ++ instance->services[handle].instance = instance; ++ instance->services[handle].handle = handle; ++ ++ return &instance->services[handle]; ++ } ++ } ++ return NULL; ++} + + /**************************************************************************** + * +@@ -180,58 +187,47 @@ + + static VCHIQ_STATUS_T + add_completion(VCHIQ_INSTANCE_T instance, VCHIQ_REASON_T reason, +- VCHIQ_HEADER_T *header, USER_SERVICE_T *user_service, +- void *bulk_userdata) ++ VCHIQ_HEADER_T *header, USER_SERVICE_T *service, void *bulk_userdata) + { +- VCHIQ_COMPLETION_DATA_T *completion; +- DEBUG_INITIALISE(g_state.local) ++ VCHIQ_COMPLETION_DATA_T *completion; ++ DEBUG_INITIALISE(g_state.local) + +- while (instance->completion_insert == +- (instance->completion_remove + MAX_COMPLETIONS)) { +- /* Out of space - wait for the client */ +- DEBUG_TRACE(SERVICE_CALLBACK_LINE); +- vchiq_log_trace(vchiq_arm_log_level, +- "add_completion - completion queue full"); +- DEBUG_COUNT(COMPLETION_QUEUE_FULL_COUNT); +- if (down_interruptible(&instance->remove_event) != 0) { +- vchiq_log_info(vchiq_arm_log_level, +- "service_callback interrupted"); +- return VCHIQ_RETRY; +- } else if (instance->closing) { +- vchiq_log_info(vchiq_arm_log_level, +- "service_callback closing"); +- return VCHIQ_ERROR; +- } +- DEBUG_TRACE(SERVICE_CALLBACK_LINE); +- } +- +- completion = +- &instance->completions[instance->completion_insert & +- (MAX_COMPLETIONS - 1)]; +- +- completion->header = header; +- completion->reason = reason; +- /* N.B. service_userdata is updated while processing AWAIT_COMPLETION */ +- completion->service_userdata = user_service->service; +- completion->bulk_userdata = bulk_userdata; +- +- if (reason == VCHIQ_SERVICE_CLOSED) +- /* Take an extra reference, to be held until +- this CLOSED notification is delivered. */ +- lock_service(user_service->service); +- +- /* A write barrier is needed here to ensure that the entire completion +- record is written out before the insert point. */ +- wmb(); +- +- if (reason == VCHIQ_MESSAGE_AVAILABLE) +- user_service->message_available_pos = +- instance->completion_insert; +- instance->completion_insert++; ++ while (instance->completion_insert == ++ (instance->completion_remove + MAX_COMPLETIONS)) { ++ /* Out of space - wait for the client */ ++ DEBUG_TRACE(SERVICE_CALLBACK_LINE); ++ vcos_log_trace("add_completion - completion queue full"); ++ DEBUG_COUNT(COMPLETION_QUEUE_FULL_COUNT); ++ if (vcos_event_wait(&instance->remove_event) != VCOS_SUCCESS) { ++ vcos_log_info("service_callback interrupted"); ++ return VCHIQ_RETRY; ++ } else if (instance->closing) { ++ vcos_log_info("service_callback closing"); ++ return VCHIQ_ERROR; ++ } ++ DEBUG_TRACE(SERVICE_CALLBACK_LINE); ++ } ++ ++ completion = ++ &instance-> ++ completions[instance->completion_insert & (MAX_COMPLETIONS - 1)]; ++ ++ completion->header = header; ++ completion->reason = reason; ++ completion->service_userdata = service; ++ completion->bulk_userdata = bulk_userdata; ++ ++ /* A write barrier is needed here to ensure that the entire completion ++ record is written out before the insert point. */ ++ vcos_wmb(&completion->bulk_userdata); ++ ++ if (reason == VCHIQ_MESSAGE_AVAILABLE) ++ service->message_available_pos = instance->completion_insert; ++ instance->completion_insert++; + +- up(&instance->insert_event); ++ vcos_event_signal(&instance->insert_event); + +- return VCHIQ_SUCCESS; ++ return VCHIQ_SUCCESS; + } + + /**************************************************************************** +@@ -242,104 +238,90 @@ + + static VCHIQ_STATUS_T + service_callback(VCHIQ_REASON_T reason, VCHIQ_HEADER_T *header, +- VCHIQ_SERVICE_HANDLE_T handle, void *bulk_userdata) ++ VCHIQ_SERVICE_HANDLE_T handle, void *bulk_userdata) + { +- /* How do we ensure the callback goes to the right client? +- ** The service_user data points to a USER_SERVICE_T record containing +- ** the original callback and the user state structure, which contains a +- ** circular buffer for completion records. +- */ +- USER_SERVICE_T *user_service; +- VCHIQ_SERVICE_T *service; +- VCHIQ_INSTANCE_T instance; +- DEBUG_INITIALISE(g_state.local) +- +- DEBUG_TRACE(SERVICE_CALLBACK_LINE); +- +- service = handle_to_service(handle); +- BUG_ON(!service); +- user_service = (USER_SERVICE_T *)service->base.userdata; +- instance = user_service->instance; +- +- if (!instance || instance->closing) +- return VCHIQ_SUCCESS; +- +- vchiq_log_trace(vchiq_arm_log_level, +- "service_callback - service %lx(%d), reason %d, header %lx, " +- "instance %lx, bulk_userdata %lx", +- (unsigned long)user_service, +- service->localport, +- reason, (unsigned long)header, +- (unsigned long)instance, (unsigned long)bulk_userdata); +- +- if (header && user_service->is_vchi) { +- spin_lock(&msg_queue_spinlock); +- while (user_service->msg_insert == +- (user_service->msg_remove + MSG_QUEUE_SIZE)) { +- spin_unlock(&msg_queue_spinlock); +- DEBUG_TRACE(SERVICE_CALLBACK_LINE); +- DEBUG_COUNT(MSG_QUEUE_FULL_COUNT); +- vchiq_log_trace(vchiq_arm_log_level, +- "service_callback - msg queue full"); +- /* If there is no MESSAGE_AVAILABLE in the completion +- ** queue, add one +- */ +- if ((user_service->message_available_pos - +- instance->completion_remove) < 0) { +- VCHIQ_STATUS_T status; +- vchiq_log_info(vchiq_arm_log_level, +- "Inserting extra MESSAGE_AVAILABLE"); +- DEBUG_TRACE(SERVICE_CALLBACK_LINE); +- status = add_completion(instance, reason, +- NULL, user_service, bulk_userdata); +- if (status != VCHIQ_SUCCESS) { +- DEBUG_TRACE(SERVICE_CALLBACK_LINE); +- return status; +- } +- } +- +- DEBUG_TRACE(SERVICE_CALLBACK_LINE); +- if (down_interruptible(&user_service->remove_event) +- != 0) { +- vchiq_log_info(vchiq_arm_log_level, +- "service_callback interrupted"); +- DEBUG_TRACE(SERVICE_CALLBACK_LINE); +- return VCHIQ_RETRY; +- } else if (instance->closing) { +- vchiq_log_info(vchiq_arm_log_level, +- "service_callback closing"); +- DEBUG_TRACE(SERVICE_CALLBACK_LINE); +- return VCHIQ_ERROR; +- } +- DEBUG_TRACE(SERVICE_CALLBACK_LINE); +- spin_lock(&msg_queue_spinlock); +- } +- +- user_service->msg_queue[user_service->msg_insert & +- (MSG_QUEUE_SIZE - 1)] = header; +- user_service->msg_insert++; +- spin_unlock(&msg_queue_spinlock); +- +- up(&user_service->insert_event); +- +- /* If there is a thread waiting in DEQUEUE_MESSAGE, or if +- ** there is a MESSAGE_AVAILABLE in the completion queue then +- ** bypass the completion queue. +- */ +- if (((user_service->message_available_pos - +- instance->completion_remove) >= 0) || +- user_service->dequeue_pending) { +- DEBUG_TRACE(SERVICE_CALLBACK_LINE); +- user_service->dequeue_pending = 0; +- return VCHIQ_SUCCESS; +- } +- +- header = NULL; +- } +- DEBUG_TRACE(SERVICE_CALLBACK_LINE); ++ /* How do we ensure the callback goes to the right client? ++ The service_user data points to a USER_SERVICE_T record containing the ++ original callback and the user state structure, which contains a circular ++ buffer for completion records. ++ */ ++ USER_SERVICE_T *service = ++ (USER_SERVICE_T *) VCHIQ_GET_SERVICE_USERDATA(handle); ++ VCHIQ_INSTANCE_T instance = service->instance; ++ DEBUG_INITIALISE(g_state.local) ++ ++ DEBUG_TRACE(SERVICE_CALLBACK_LINE); ++ vcos_log_trace ++ ("service_callback - service %lx(%d), reason %d, header %lx, " ++ "instance %lx, bulk_userdata %lx", ++ (unsigned long)service, ((VCHIQ_SERVICE_T *) handle)->localport, ++ reason, (unsigned long)header, ++ (unsigned long)instance, (unsigned long)bulk_userdata); ++ ++ if (!instance || instance->closing) { ++ return VCHIQ_SUCCESS; ++ } ++ ++ if (header && service->is_vchi) ++ { ++ while (service->msg_insert == (service->msg_remove + MSG_QUEUE_SIZE)) ++ { ++ DEBUG_TRACE(SERVICE_CALLBACK_LINE); ++ DEBUG_COUNT(MSG_QUEUE_FULL_COUNT); ++ vcos_log_trace("service_callback - msg queue full"); ++ /* If there is no MESSAGE_AVAILABLE in the completion queue, add one */ ++ if ((service->message_available_pos - instance->completion_remove) < 0) ++ { ++ VCHIQ_STATUS_T status; ++ vcos_log_warn("Inserting extra MESSAGE_AVAILABLE"); ++ DEBUG_TRACE(SERVICE_CALLBACK_LINE); ++ status = add_completion(instance, reason, NULL, service, bulk_userdata); ++ if (status != VCHIQ_SUCCESS) ++ { ++ DEBUG_TRACE(SERVICE_CALLBACK_LINE); ++ return status; ++ } ++ } ++ ++ DEBUG_TRACE(SERVICE_CALLBACK_LINE); ++ if (vcos_event_wait(&service->remove_event) != VCOS_SUCCESS) { ++ vcos_log_info("service_callback interrupted"); ++ DEBUG_TRACE(SERVICE_CALLBACK_LINE); ++ return VCHIQ_RETRY; ++ } else if (instance->closing) { ++ vcos_log_info("service_callback closing"); ++ DEBUG_TRACE(SERVICE_CALLBACK_LINE); ++ return VCHIQ_ERROR; ++ } ++ DEBUG_TRACE(SERVICE_CALLBACK_LINE); ++ } ++ ++ service->msg_queue[service->msg_insert & (MSG_QUEUE_SIZE - 1)] = ++ header; ++ ++ /* A write memory barrier is needed to ensure that the store of header ++ is completed before the insertion point is updated */ ++ vcos_wmb(&service->msg_queue[service->msg_insert & (MSG_QUEUE_SIZE - 1)]); ++ ++ service->msg_insert++; ++ vcos_event_signal(&service->insert_event); ++ ++ /* If there is a thread waiting in DEQUEUE_MESSAGE, or if ++ there is a MESSAGE_AVAILABLE in the completion queue then ++ bypass the completion queue. */ ++ if (((service->message_available_pos - instance->completion_remove) >= 0) || ++ service->dequeue_pending) ++ { ++ DEBUG_TRACE(SERVICE_CALLBACK_LINE); ++ service->dequeue_pending = 0; ++ return VCHIQ_SUCCESS; ++ } ++ ++ header = NULL; ++ } ++ DEBUG_TRACE(SERVICE_CALLBACK_LINE); + +- return add_completion(instance, reason, header, user_service, +- bulk_userdata); ++ return add_completion(instance, reason, header, service, bulk_userdata); + } + + /**************************************************************************** +@@ -351,649 +333,603 @@ + static long + vchiq_ioctl(struct file *file, unsigned int cmd, unsigned long arg) + { +- VCHIQ_INSTANCE_T instance = file->private_data; +- VCHIQ_STATUS_T status = VCHIQ_SUCCESS; +- VCHIQ_SERVICE_T *service = NULL; +- long ret = 0; +- int i, rc; +- DEBUG_INITIALISE(g_state.local) +- +- vchiq_log_trace(vchiq_arm_log_level, +- "vchiq_ioctl - instance %x, cmd %s, arg %lx", +- (unsigned int)instance, +- ((_IOC_TYPE(cmd) == VCHIQ_IOC_MAGIC) && +- (_IOC_NR(cmd) <= VCHIQ_IOC_MAX)) ? +- ioctl_names[_IOC_NR(cmd)] : "", arg); +- +- switch (cmd) { +- case VCHIQ_IOC_SHUTDOWN: +- if (!instance->connected) +- break; +- +- /* Remove all services */ +- i = 0; +- while ((service = next_service_by_instance(instance->state, +- instance, &i)) != NULL) { +- status = vchiq_remove_service(service->handle); +- unlock_service(service); +- if (status != VCHIQ_SUCCESS) +- break; +- } +- service = NULL; +- +- if (status == VCHIQ_SUCCESS) { +- /* Wake the completion thread and ask it to exit */ +- instance->closing = 1; +- up(&instance->insert_event); +- } +- +- break; +- +- case VCHIQ_IOC_CONNECT: +- if (instance->connected) { +- ret = -EINVAL; +- break; +- } +- rc = mutex_lock_interruptible(&instance->state->mutex); +- if (rc != 0) { +- vchiq_log_error(vchiq_arm_log_level, +- "vchiq: connect: could not lock mutex for " +- "state %d: %d", +- instance->state->id, rc); +- ret = -EINTR; +- break; +- } +- status = vchiq_connect_internal(instance->state, instance); +- mutex_unlock(&instance->state->mutex); +- +- if (status == VCHIQ_SUCCESS) +- instance->connected = 1; +- else +- vchiq_log_error(vchiq_arm_log_level, +- "vchiq: could not connect: %d", status); +- break; +- +- case VCHIQ_IOC_CREATE_SERVICE: { +- VCHIQ_CREATE_SERVICE_T args; +- USER_SERVICE_T *user_service = NULL; +- void *userdata; +- int srvstate; +- +- if (copy_from_user +- (&args, (const void __user *)arg, +- sizeof(args)) != 0) { +- ret = -EFAULT; +- break; +- } +- +- user_service = kmalloc(sizeof(USER_SERVICE_T), GFP_KERNEL); +- if (!user_service) { +- ret = -ENOMEM; +- break; +- } +- +- if (args.is_open) { +- if (!instance->connected) { +- ret = -ENOTCONN; +- break; +- } +- srvstate = VCHIQ_SRVSTATE_OPENING; +- } else { +- srvstate = +- instance->connected ? +- VCHIQ_SRVSTATE_LISTENING : +- VCHIQ_SRVSTATE_HIDDEN; +- } +- +- userdata = args.params.userdata; +- args.params.callback = service_callback; +- args.params.userdata = user_service; +- service = vchiq_add_service_internal( +- instance->state, +- &args.params, srvstate, +- instance); +- +- if (service != NULL) { +- user_service->service = service; +- user_service->userdata = userdata; +- user_service->instance = instance; +- user_service->is_vchi = args.is_vchi; +- user_service->dequeue_pending = 0; +- user_service->message_available_pos = +- instance->completion_remove - 1; +- user_service->msg_insert = 0; +- user_service->msg_remove = 0; +- sema_init(&user_service->insert_event, 0); +- sema_init(&user_service->remove_event, 0); +- +- if (args.is_open) { +- status = vchiq_open_service_internal +- (service, instance->pid); +- if (status != VCHIQ_SUCCESS) { +- vchiq_remove_service(service->handle); +- service = NULL; +- ret = (status == VCHIQ_RETRY) ? +- -EINTR : -EIO; +- user_service->service = NULL; +- user_service->instance = NULL; +- break; +- } +- } +- +- if (copy_to_user((void __user *) +- &(((VCHIQ_CREATE_SERVICE_T __user *) +- arg)->handle), +- (const void *)&service->handle, +- sizeof(service->handle)) != 0) { +- ret = -EFAULT; +- vchiq_remove_service(service->handle); +- kfree(user_service); +- } +- +- service = NULL; +- } else { +- ret = -EEXIST; +- kfree(user_service); +- } +- } break; +- +- case VCHIQ_IOC_CLOSE_SERVICE: { +- VCHIQ_SERVICE_HANDLE_T handle = (VCHIQ_SERVICE_HANDLE_T)arg; +- +- service = find_service_for_instance(instance, handle); +- if (service != NULL) +- status = vchiq_close_service(service->handle); +- else +- ret = -EINVAL; +- } break; +- +- case VCHIQ_IOC_REMOVE_SERVICE: { +- VCHIQ_SERVICE_HANDLE_T handle = (VCHIQ_SERVICE_HANDLE_T)arg; +- +- service = find_service_for_instance(instance, handle); +- if (service != NULL) +- status = vchiq_remove_service(service->handle); +- else +- ret = -EINVAL; +- } break; +- +- case VCHIQ_IOC_USE_SERVICE: +- case VCHIQ_IOC_RELEASE_SERVICE: { +- VCHIQ_SERVICE_HANDLE_T handle = (VCHIQ_SERVICE_HANDLE_T)arg; +- +- service = find_service_for_instance(instance, handle); +- if (service != NULL) { +- status = (cmd == VCHIQ_IOC_USE_SERVICE) ? +- vchiq_use_service_internal(service) : +- vchiq_release_service_internal(service); +- if (status != VCHIQ_SUCCESS) { +- vchiq_log_error(vchiq_susp_log_level, +- "%s: cmd %s returned error %d for " +- "service %c%c%c%c:%03d", +- __func__, +- (cmd == VCHIQ_IOC_USE_SERVICE) ? +- "VCHIQ_IOC_USE_SERVICE" : +- "VCHIQ_IOC_RELEASE_SERVICE", +- status, +- VCHIQ_FOURCC_AS_4CHARS( +- service->base.fourcc), +- service->client_id); +- ret = -EINVAL; +- } +- } else +- ret = -EINVAL; +- } break; +- +- case VCHIQ_IOC_QUEUE_MESSAGE: { +- VCHIQ_QUEUE_MESSAGE_T args; +- if (copy_from_user +- (&args, (const void __user *)arg, +- sizeof(args)) != 0) { +- ret = -EFAULT; +- break; +- } +- +- service = find_service_for_instance(instance, args.handle); +- +- if ((service != NULL) && (args.count <= MAX_ELEMENTS)) { +- /* Copy elements into kernel space */ +- VCHIQ_ELEMENT_T elements[MAX_ELEMENTS]; +- if (copy_from_user(elements, args.elements, +- args.count * sizeof(VCHIQ_ELEMENT_T)) == 0) +- status = vchiq_queue_message +- (args.handle, +- elements, args.count); +- else +- ret = -EFAULT; +- } else { +- ret = -EINVAL; +- } +- } break; +- +- case VCHIQ_IOC_QUEUE_BULK_TRANSMIT: +- case VCHIQ_IOC_QUEUE_BULK_RECEIVE: { +- VCHIQ_QUEUE_BULK_TRANSFER_T args; +- struct bulk_waiter_node *waiter = NULL; +- VCHIQ_BULK_DIR_T dir = +- (cmd == VCHIQ_IOC_QUEUE_BULK_TRANSMIT) ? +- VCHIQ_BULK_TRANSMIT : VCHIQ_BULK_RECEIVE; +- +- if (copy_from_user +- (&args, (const void __user *)arg, +- sizeof(args)) != 0) { +- ret = -EFAULT; +- break; +- } +- +- service = find_service_for_instance(instance, args.handle); +- if (!service) { +- ret = -EINVAL; +- break; +- } +- +- if (args.mode == VCHIQ_BULK_MODE_BLOCKING) { +- waiter = kzalloc(sizeof(struct bulk_waiter_node), +- GFP_KERNEL); +- if (!waiter) { +- ret = -ENOMEM; +- break; +- } +- args.userdata = &waiter->bulk_waiter; +- } else if (args.mode == VCHIQ_BULK_MODE_WAITING) { +- struct list_head *pos; +- mutex_lock(&instance->bulk_waiter_list_mutex); +- list_for_each(pos, &instance->bulk_waiter_list) { +- if (list_entry(pos, struct bulk_waiter_node, +- list)->pid == current->pid) { +- waiter = list_entry(pos, +- struct bulk_waiter_node, +- list); +- list_del(pos); +- break; +- } +- +- } +- mutex_unlock(&instance->bulk_waiter_list_mutex); +- if (!waiter) { +- vchiq_log_error(vchiq_arm_log_level, +- "no bulk_waiter found for pid %d", +- current->pid); +- ret = -ESRCH; +- break; +- } +- vchiq_log_info(vchiq_arm_log_level, +- "found bulk_waiter %x for pid %d", +- (unsigned int)waiter, current->pid); +- args.userdata = &waiter->bulk_waiter; +- } +- status = vchiq_bulk_transfer +- (args.handle, +- VCHI_MEM_HANDLE_INVALID, +- args.data, args.size, +- args.userdata, args.mode, +- dir); +- if (!waiter) +- break; +- if ((status != VCHIQ_RETRY) || fatal_signal_pending(current) || +- !waiter->bulk_waiter.bulk) { +- if (waiter->bulk_waiter.bulk) { +- /* Cancel the signal when the transfer +- ** completes. */ +- spin_lock(&bulk_waiter_spinlock); +- waiter->bulk_waiter.bulk->userdata = NULL; +- spin_unlock(&bulk_waiter_spinlock); +- } +- kfree(waiter); +- } else { +- const VCHIQ_BULK_MODE_T mode_waiting = +- VCHIQ_BULK_MODE_WAITING; +- waiter->pid = current->pid; +- mutex_lock(&instance->bulk_waiter_list_mutex); +- list_add(&waiter->list, &instance->bulk_waiter_list); +- mutex_unlock(&instance->bulk_waiter_list_mutex); +- vchiq_log_info(vchiq_arm_log_level, +- "saved bulk_waiter %x for pid %d", +- (unsigned int)waiter, current->pid); +- +- if (copy_to_user((void __user *) +- &(((VCHIQ_QUEUE_BULK_TRANSFER_T __user *) +- arg)->mode), +- (const void *)&mode_waiting, +- sizeof(mode_waiting)) != 0) +- ret = -EFAULT; +- } +- } break; +- +- case VCHIQ_IOC_AWAIT_COMPLETION: { +- VCHIQ_AWAIT_COMPLETION_T args; +- +- DEBUG_TRACE(AWAIT_COMPLETION_LINE); +- if (!instance->connected) { +- ret = -ENOTCONN; +- break; +- } +- +- if (copy_from_user(&args, (const void __user *)arg, +- sizeof(args)) != 0) { +- ret = -EFAULT; +- break; +- } +- +- mutex_lock(&instance->completion_mutex); +- +- DEBUG_TRACE(AWAIT_COMPLETION_LINE); +- while ((instance->completion_remove == +- instance->completion_insert) +- && !instance->closing) { +- int rc; +- DEBUG_TRACE(AWAIT_COMPLETION_LINE); +- mutex_unlock(&instance->completion_mutex); +- rc = down_interruptible(&instance->insert_event); +- mutex_lock(&instance->completion_mutex); +- if (rc != 0) { +- DEBUG_TRACE(AWAIT_COMPLETION_LINE); +- vchiq_log_info(vchiq_arm_log_level, +- "AWAIT_COMPLETION interrupted"); +- ret = -EINTR; +- break; +- } +- } +- DEBUG_TRACE(AWAIT_COMPLETION_LINE); +- +- /* A read memory barrier is needed to stop prefetch of a stale +- ** completion record +- */ +- rmb(); +- +- if ((ret == 0) && !instance->closing) { +- int msgbufcount = args.msgbufcount; +- for (ret = 0; ret < args.count; ret++) { +- VCHIQ_COMPLETION_DATA_T *completion; +- VCHIQ_SERVICE_T *service; +- USER_SERVICE_T *user_service; +- VCHIQ_HEADER_T *header; +- if (instance->completion_remove == +- instance->completion_insert) +- break; +- completion = &instance->completions[ +- instance->completion_remove & +- (MAX_COMPLETIONS - 1)]; +- +- service = completion->service_userdata; +- user_service = service->base.userdata; +- completion->service_userdata = +- user_service->userdata; +- +- header = completion->header; +- if (header) { +- void __user *msgbuf; +- int msglen; +- +- msglen = header->size + +- sizeof(VCHIQ_HEADER_T); +- /* This must be a VCHIQ-style service */ +- if (args.msgbufsize < msglen) { +- vchiq_log_error( +- vchiq_arm_log_level, +- "header %x: msgbufsize" +- " %x < msglen %x", +- (unsigned int)header, +- args.msgbufsize, +- msglen); +- WARN(1, "invalid message " +- "size\n"); +- if (ret == 0) +- ret = -EMSGSIZE; +- break; +- } +- if (msgbufcount <= 0) +- /* Stall here for lack of a +- ** buffer for the message. */ +- break; +- /* Get the pointer from user space */ +- msgbufcount--; +- if (copy_from_user(&msgbuf, +- (const void __user *) +- &args.msgbufs[msgbufcount], +- sizeof(msgbuf)) != 0) { +- if (ret == 0) +- ret = -EFAULT; +- break; +- } +- +- /* Copy the message to user space */ +- if (copy_to_user(msgbuf, header, +- msglen) != 0) { +- if (ret == 0) +- ret = -EFAULT; +- break; +- } +- +- /* Now it has been copied, the message +- ** can be released. */ +- vchiq_release_message(service->handle, +- header); +- +- /* The completion must point to the +- ** msgbuf. */ +- completion->header = msgbuf; +- } +- +- if (completion->reason == +- VCHIQ_SERVICE_CLOSED) { +- unlock_service(service); +- kfree(user_service); +- } +- +- if (copy_to_user((void __user *)( +- (size_t)args.buf + +- ret * sizeof(VCHIQ_COMPLETION_DATA_T)), +- completion, +- sizeof(VCHIQ_COMPLETION_DATA_T)) != 0) { +- if (ret == 0) +- ret = -EFAULT; +- break; +- } +- +- instance->completion_remove++; +- } +- +- if (msgbufcount != args.msgbufcount) { +- if (copy_to_user((void __user *) +- &((VCHIQ_AWAIT_COMPLETION_T *)arg)-> +- msgbufcount, +- &msgbufcount, +- sizeof(msgbufcount)) != 0) { +- ret = -EFAULT; +- } +- } +- } +- +- if (ret != 0) +- up(&instance->remove_event); +- mutex_unlock(&instance->completion_mutex); +- DEBUG_TRACE(AWAIT_COMPLETION_LINE); +- } break; +- +- case VCHIQ_IOC_DEQUEUE_MESSAGE: { +- VCHIQ_DEQUEUE_MESSAGE_T args; +- USER_SERVICE_T *user_service; +- VCHIQ_HEADER_T *header; +- +- DEBUG_TRACE(DEQUEUE_MESSAGE_LINE); +- if (copy_from_user +- (&args, (const void __user *)arg, +- sizeof(args)) != 0) { +- ret = -EFAULT; +- break; +- } +- service = find_service_for_instance(instance, args.handle); +- if (!service) { +- ret = -EINVAL; +- break; +- } +- user_service = (USER_SERVICE_T *)service->base.userdata; +- if (user_service->is_vchi == 0) { +- ret = -EINVAL; +- break; +- } +- +- spin_lock(&msg_queue_spinlock); +- if (user_service->msg_remove == user_service->msg_insert) { +- if (!args.blocking) { +- spin_unlock(&msg_queue_spinlock); +- DEBUG_TRACE(DEQUEUE_MESSAGE_LINE); +- ret = -EWOULDBLOCK; +- break; +- } +- user_service->dequeue_pending = 1; +- do { +- spin_unlock(&msg_queue_spinlock); +- DEBUG_TRACE(DEQUEUE_MESSAGE_LINE); +- if (down_interruptible( +- &user_service->insert_event) != 0) { +- vchiq_log_info(vchiq_arm_log_level, +- "DEQUEUE_MESSAGE interrupted"); +- ret = -EINTR; +- break; +- } +- spin_lock(&msg_queue_spinlock); +- } while (user_service->msg_remove == +- user_service->msg_insert); +- +- if (ret) +- break; +- } +- +- BUG_ON((int)(user_service->msg_insert - +- user_service->msg_remove) < 0); +- +- header = user_service->msg_queue[user_service->msg_remove & +- (MSG_QUEUE_SIZE - 1)]; +- user_service->msg_remove++; +- spin_unlock(&msg_queue_spinlock); +- +- up(&user_service->remove_event); +- if (header == NULL) +- ret = -ENOTCONN; +- else if (header->size <= args.bufsize) { +- /* Copy to user space if msgbuf is not NULL */ +- if ((args.buf == NULL) || +- (copy_to_user((void __user *)args.buf, +- header->data, +- header->size) == 0)) { +- ret = header->size; +- vchiq_release_message( +- service->handle, +- header); +- } else +- ret = -EFAULT; +- } else { +- vchiq_log_error(vchiq_arm_log_level, +- "header %x: bufsize %x < size %x", +- (unsigned int)header, args.bufsize, +- header->size); +- WARN(1, "invalid size\n"); +- ret = -EMSGSIZE; +- } +- DEBUG_TRACE(DEQUEUE_MESSAGE_LINE); +- } break; +- +- case VCHIQ_IOC_GET_CLIENT_ID: { +- VCHIQ_SERVICE_HANDLE_T handle = (VCHIQ_SERVICE_HANDLE_T)arg; +- +- ret = vchiq_get_client_id(handle); +- } break; +- +- case VCHIQ_IOC_GET_CONFIG: { +- VCHIQ_GET_CONFIG_T args; +- VCHIQ_CONFIG_T config; +- +- if (copy_from_user(&args, (const void __user *)arg, +- sizeof(args)) != 0) { +- ret = -EFAULT; +- break; +- } +- if (args.config_size > sizeof(config)) { +- ret = -EINVAL; +- break; +- } +- status = vchiq_get_config(instance, args.config_size, &config); +- if (status == VCHIQ_SUCCESS) { +- if (copy_to_user((void __user *)args.pconfig, +- &config, args.config_size) != 0) { +- ret = -EFAULT; +- break; +- } +- } +- } break; +- +- case VCHIQ_IOC_SET_SERVICE_OPTION: { +- VCHIQ_SET_SERVICE_OPTION_T args; +- +- if (copy_from_user( +- &args, (const void __user *)arg, +- sizeof(args)) != 0) { +- ret = -EFAULT; +- break; +- } +- +- service = find_service_for_instance(instance, args.handle); +- if (!service) { +- ret = -EINVAL; +- break; +- } +- +- status = vchiq_set_service_option( +- args.handle, args.option, args.value); +- } break; +- +- case VCHIQ_IOC_DUMP_PHYS_MEM: { +- VCHIQ_DUMP_MEM_T args; +- +- if (copy_from_user +- (&args, (const void __user *)arg, +- sizeof(args)) != 0) { +- ret = -EFAULT; +- break; +- } +- dump_phys_mem(args.virt_addr, args.num_bytes); +- } break; +- +- default: +- ret = -ENOTTY; +- break; +- } +- +- if (service) +- unlock_service(service); +- +- if (ret == 0) { +- if (status == VCHIQ_ERROR) +- ret = -EIO; +- else if (status == VCHIQ_RETRY) +- ret = -EINTR; +- } +- +- if ((status == VCHIQ_SUCCESS) && (ret < 0) && (ret != -EINTR) && +- (ret != -EWOULDBLOCK)) +- vchiq_log_info(vchiq_arm_log_level, +- " ioctl instance %lx, cmd %s -> status %d, %ld", +- (unsigned long)instance, +- (_IOC_NR(cmd) <= VCHIQ_IOC_MAX) ? +- ioctl_names[_IOC_NR(cmd)] : +- "", +- status, ret); +- else +- vchiq_log_trace(vchiq_arm_log_level, +- " ioctl instance %lx, cmd %s -> status %d, %ld", +- (unsigned long)instance, +- (_IOC_NR(cmd) <= VCHIQ_IOC_MAX) ? +- ioctl_names[_IOC_NR(cmd)] : +- "", +- status, ret); ++ VCHIQ_INSTANCE_T instance = file->private_data; ++ VCHIQ_STATUS_T status = VCHIQ_SUCCESS; ++ long ret = 0; ++ int i, rc; ++ DEBUG_INITIALISE(g_state.local) ++ ++ vcos_log_trace("vchiq_ioctl - instance %x, cmd %s, arg %lx", ++ (unsigned int)instance, ++ ((_IOC_TYPE(cmd) == VCHIQ_IOC_MAGIC) && (_IOC_NR(cmd) <= VCHIQ_IOC_MAX)) ? ++ ioctl_names[_IOC_NR(cmd)] : "", arg); ++ ++ switch (cmd) { ++ case VCHIQ_IOC_SHUTDOWN: ++ if (!instance->connected) ++ break; ++ ++ /* Remove all services */ ++ for (i = 0; i < MAX_SERVICES; i++) { ++ USER_SERVICE_T *service = &instance->services[i]; ++ if (service->service != NULL) { ++ status = vchiq_remove_service(&service->service->base); ++ if (status != VCHIQ_SUCCESS) ++ break; ++ service->service = NULL; ++ } ++ } ++ ++ if (status == VCHIQ_SUCCESS) { ++ /* Wake the completion thread and ask it to exit */ ++ instance->closing = 1; ++ vcos_event_signal(&instance->insert_event); ++ } ++ ++ break; ++ ++ case VCHIQ_IOC_CONNECT: ++ if (instance->connected) { ++ ret = -EINVAL; ++ break; ++ } ++ if ((rc=vcos_mutex_lock(&instance->state->mutex)) != VCOS_SUCCESS) { ++ vcos_log_error("vchiq: connect: could not lock mutex for state %d: %d", ++ instance->state->id, rc); ++ ret = -EINTR; ++ break; ++ } ++ status = vchiq_connect_internal(instance->state, instance); ++ vcos_mutex_unlock(&instance->state->mutex); ++ ++ if (status == VCHIQ_SUCCESS) ++ instance->connected = 1; ++ else ++ vcos_log_error("vchiq: could not connect: %d", status); ++ break; ++ ++ case VCHIQ_IOC_CREATE_SERVICE: ++ { ++ VCHIQ_CREATE_SERVICE_T args; ++ VCHIQ_SERVICE_T *service = NULL; ++ USER_SERVICE_T *user_service = NULL; ++ void *userdata; ++ int srvstate; ++ ++ if (copy_from_user ++ (&args, (const void __user *)arg, ++ sizeof(args)) != 0) { ++ ret = -EFAULT; ++ break; ++ } ++ ++ for (i = 0; i < MAX_SERVICES; i++) { ++ if (instance->services[i].service == NULL) { ++ user_service = &instance->services[i]; ++ break; ++ } ++ } ++ ++ if (!user_service) { ++ ret = -EMFILE; ++ break; ++ } ++ ++ if (args.is_open) { ++ if (instance->connected) ++ srvstate = VCHIQ_SRVSTATE_OPENING; ++ else { ++ ret = -ENOTCONN; ++ break; ++ } ++ } else { ++ srvstate = ++ instance->connected ? ++ VCHIQ_SRVSTATE_LISTENING : ++ VCHIQ_SRVSTATE_HIDDEN; ++ } ++ ++ vcos_mutex_lock(&instance->state->mutex); ++ ++ userdata = args.params.userdata; ++ args.params.callback = service_callback; ++ args.params.userdata = user_service; ++ service = ++ vchiq_add_service_internal(instance->state, ++ &args.params, srvstate, ++ instance); ++ ++ vcos_mutex_unlock(&instance->state->mutex); ++ ++ if (service != NULL) { ++ user_service->service = service; ++ user_service->userdata = userdata; ++ user_service->instance = instance; ++ user_service->handle = i; ++ user_service->is_vchi = args.is_vchi; ++ user_service->dequeue_pending = 0; ++ user_service->message_available_pos = instance->completion_remove - 1; ++ user_service->msg_insert = 0; ++ user_service->msg_remove = 0; ++ vcos_event_create(&user_service->insert_event, "insert_event"); ++ vcos_event_create(&user_service->remove_event, "remove_event"); ++ ++ if (args.is_open) { ++ status = ++ vchiq_open_service_internal ++ (service, instance->pid); ++ if (status != VCHIQ_SUCCESS) { ++ vchiq_remove_service ++ (&service->base); ++ ret = ++ (status == ++ VCHIQ_RETRY) ? -EINTR : ++ -EIO; ++ user_service->service = NULL; ++ user_service->instance = NULL; ++ vcos_event_delete(&user_service->insert_event); ++ vcos_event_delete(&user_service->remove_event); ++ break; ++ } ++ } ++ ++ if (copy_to_user((void __user *) ++ &(((VCHIQ_CREATE_SERVICE_T __user ++ *) arg)->handle), ++ (const void *)&user_service-> ++ handle, ++ sizeof(user_service-> ++ handle)) != 0) ++ ret = -EFAULT; ++ } else { ++ ret = -EEXIST; ++ } ++ } ++ break; ++ ++ case VCHIQ_IOC_CLOSE_SERVICE: ++ { ++ USER_SERVICE_T *user_service; ++ int handle = (int)arg; ++ ++ user_service = find_service_by_handle(instance, handle); ++ if (user_service != NULL) ++ { ++ int is_server = (user_service->service->public_fourcc != VCHIQ_FOURCC_INVALID); ++ ++ status = ++ vchiq_close_service(&user_service->service->base); ++ if ((status == VCHIQ_SUCCESS) && !is_server) ++ { ++ vcos_event_delete(&user_service->insert_event); ++ vcos_event_delete(&user_service->remove_event); ++ user_service->service = NULL; ++ } ++ } else ++ ret = -EINVAL; ++ } ++ break; ++ ++ case VCHIQ_IOC_REMOVE_SERVICE: ++ { ++ USER_SERVICE_T *user_service; ++ int handle = (int)arg; ++ ++ user_service = find_service_by_handle(instance, handle); ++ if (user_service != NULL) ++ { ++ status = ++ vchiq_remove_service(&user_service->service->base); ++ if (status == VCHIQ_SUCCESS) ++ { ++ vcos_event_delete(&user_service->insert_event); ++ vcos_event_delete(&user_service->remove_event); ++ user_service->service = NULL; ++ } ++ } else ++ ret = -EINVAL; ++ } ++ break; ++ ++ case VCHIQ_IOC_USE_SERVICE: ++ case VCHIQ_IOC_RELEASE_SERVICE: ++ { ++ USER_SERVICE_T *user_service; ++ int handle = (int)arg; ++ ++ user_service = find_service_by_handle(instance, handle); ++ if (user_service != NULL) ++ { ++ status = (cmd == VCHIQ_IOC_USE_SERVICE) ? vchiq_use_service(&user_service->service->base) : vchiq_release_service(&user_service->service->base); ++ if (status != VCHIQ_SUCCESS) ++ { ++ ret = -EINVAL; /* ??? */ ++ } ++ } ++ } ++ break; ++ ++ case VCHIQ_IOC_QUEUE_MESSAGE: ++ { ++ VCHIQ_QUEUE_MESSAGE_T args; ++ USER_SERVICE_T *user_service; ++ ++ if (copy_from_user ++ (&args, (const void __user *)arg, ++ sizeof(args)) != 0) { ++ ret = -EFAULT; ++ break; ++ } ++ user_service = find_service_by_handle(instance, args.handle); ++ if ((user_service != NULL) && (args.count <= MAX_ELEMENTS)) ++ { ++ /* Copy elements into kernel space */ ++ VCHIQ_ELEMENT_T elements[MAX_ELEMENTS]; ++ if (copy_from_user ++ (elements, args.elements, ++ args.count * sizeof(VCHIQ_ELEMENT_T)) == 0) ++ status = ++ vchiq_queue_message ++ (&user_service->service->base, ++ elements, args.count); ++ else ++ ret = -EFAULT; ++ } else { ++ ret = -EINVAL; ++ } ++ } ++ break; ++ ++ case VCHIQ_IOC_QUEUE_BULK_TRANSMIT: ++ case VCHIQ_IOC_QUEUE_BULK_RECEIVE: ++ { ++ VCHIQ_QUEUE_BULK_TRANSFER_T args; ++ USER_SERVICE_T *user_service; ++ VCHIQ_BULK_DIR_T dir = ++ (cmd == VCHIQ_IOC_QUEUE_BULK_TRANSMIT) ? ++ VCHIQ_BULK_TRANSMIT : VCHIQ_BULK_RECEIVE; ++ ++ if (copy_from_user ++ (&args, (const void __user *)arg, ++ sizeof(args)) != 0) { ++ ret = -EFAULT; ++ break; ++ } ++ user_service = find_service_by_handle(instance, args.handle); ++ if (user_service != NULL) ++ { ++ status = ++ vchiq_bulk_transfer ++ ((VCHIQ_SERVICE_T *)user_service->service, ++ VCHI_MEM_HANDLE_INVALID, ++ args.data, args.size, ++ args.userdata, args.mode, ++ dir); ++ } else { ++ ret = -EINVAL; ++ } ++ } ++ break; ++ ++ case VCHIQ_IOC_AWAIT_COMPLETION: ++ { ++ VCHIQ_AWAIT_COMPLETION_T args; ++ ++ DEBUG_TRACE(AWAIT_COMPLETION_LINE); ++ if (!instance->connected) { ++ ret = -ENOTCONN; ++ break; ++ } ++ ++ if (copy_from_user ++ (&args, (const void __user *)arg, ++ sizeof(args)) != 0) { ++ ret = -EFAULT; ++ break; ++ } ++ DEBUG_TRACE(AWAIT_COMPLETION_LINE); ++ while ((instance->completion_remove == ++ instance->completion_insert) ++ && !instance->closing) { ++ DEBUG_TRACE(AWAIT_COMPLETION_LINE); ++ if (vcos_event_wait(&instance->insert_event) != ++ VCOS_SUCCESS) { ++ DEBUG_TRACE(AWAIT_COMPLETION_LINE); ++ vcos_log_info ++ ("AWAIT_COMPLETION interrupted"); ++ ret = -EINTR; ++ break; ++ } ++ } ++ DEBUG_TRACE(AWAIT_COMPLETION_LINE); ++ ++ /* A read memory barrier is needed to stop prefetch of a stale ++ completion record */ ++ vcos_rmb(); ++ ++ if (ret == 0) { ++ int msgbufcount = args.msgbufcount; ++ for (ret = 0; ret < args.count; ret++) { ++ VCHIQ_COMPLETION_DATA_T *completion; ++ USER_SERVICE_T *service; ++ VCHIQ_HEADER_T *header; ++ if (instance->completion_remove == ++ instance->completion_insert) ++ break; ++ completion = ++ &instance-> ++ completions ++ [instance->completion_remove & ++ (MAX_COMPLETIONS - 1)]; ++ ++ service = (USER_SERVICE_T *)completion->service_userdata; ++ completion->service_userdata = service->userdata; ++ ++ header = completion->header; ++ if (header) ++ { ++ void __user *msgbuf; ++ int msglen; ++ ++ msglen = header->size + sizeof(VCHIQ_HEADER_T); ++ /* This must be a VCHIQ-style service */ ++ if (args.msgbufsize < msglen) ++ { ++ vcos_log_error("header %x: msgbufsize %x < msglen %x", ++ (unsigned int)header, args.msgbufsize, msglen); ++ vcos_assert(0); ++ if (ret == 0) ++ ret = -EMSGSIZE; ++ break; ++ } ++ if (msgbufcount <= 0) ++ { ++ /* Stall here for lack of a buffer for the message */ ++ break; ++ } ++ /* Get the pointer from user space */ ++ msgbufcount--; ++ if (copy_from_user(&msgbuf, ++ (const void __user *)&args.msgbufs[msgbufcount], ++ sizeof(msgbuf)) != 0) ++ { ++ if (ret == 0) ++ ret = -EFAULT; ++ break; ++ } ++ ++ /* Copy the message to user space */ ++ if (copy_to_user(msgbuf, header, msglen) != 0) ++ { ++ if (ret == 0) ++ ret = -EFAULT; ++ break; ++ } ++ ++ /* Now it has been copied, the message can be released. */ ++ vchiq_release_message(&service->service->base, header); ++ ++ /* The completion must point to the msgbuf */ ++ completion->header = msgbuf; ++ } ++ ++ if (copy_to_user ++ ((void __user *)((size_t) args.buf + ++ ret * ++ sizeof ++ (VCHIQ_COMPLETION_DATA_T)), ++ completion, ++ sizeof(VCHIQ_COMPLETION_DATA_T)) != ++ 0) { ++ if (ret == 0) ++ ret = -EFAULT; ++ break; ++ } ++ instance->completion_remove++; ++ } ++ ++ if (msgbufcount != args.msgbufcount) ++ { ++ if (copy_to_user((void __user *) ++ &((VCHIQ_AWAIT_COMPLETION_T *)arg)->msgbufcount, ++ &msgbufcount, sizeof(msgbufcount)) != 0) ++ { ++ ret = -EFAULT; ++ break; ++ } ++ } ++ } ++ ++ if (ret != 0) ++ vcos_event_signal(&instance->remove_event); ++ DEBUG_TRACE(AWAIT_COMPLETION_LINE); ++ } ++ break; ++ ++ case VCHIQ_IOC_DEQUEUE_MESSAGE: ++ { ++ VCHIQ_DEQUEUE_MESSAGE_T args; ++ USER_SERVICE_T *user_service; ++ VCHIQ_HEADER_T *header; ++ ++ DEBUG_TRACE(DEQUEUE_MESSAGE_LINE); ++ if (copy_from_user ++ (&args, (const void __user *)arg, ++ sizeof(args)) != 0) { ++ ret = -EFAULT; ++ break; ++ } ++ user_service = &instance->services[args.handle]; ++ if ((args.handle < 0) || (args.handle >= MAX_SERVICES) || ++ (user_service->service == NULL) || ++ (user_service->is_vchi == 0)) { ++ ret = -EINVAL; ++ break; ++ } ++ if (user_service->msg_remove == user_service->msg_insert) ++ { ++ if (!args.blocking) ++ { ++ DEBUG_TRACE(DEQUEUE_MESSAGE_LINE); ++ ret = -EWOULDBLOCK; ++ break; ++ } ++ user_service->dequeue_pending = 1; ++ do { ++ DEBUG_TRACE(DEQUEUE_MESSAGE_LINE); ++ if (vcos_event_wait(&user_service->insert_event) != ++ VCOS_SUCCESS) { ++ vcos_log_info("DEQUEUE_MESSAGE interrupted"); ++ ret = -EINTR; ++ break; ++ } ++ } ++ while (user_service->msg_remove == user_service->msg_insert); ++ } ++ ++ /* A read memory barrier is needed to stop prefetch of a stale ++ header value */ ++ vcos_rmb(); ++ ++ header = user_service->msg_queue[user_service->msg_remove & ++ (MSG_QUEUE_SIZE - 1)]; ++ if (header == NULL) ++ ret = -ENOTCONN; ++ else if (header->size <= args.bufsize) ++ { ++ /* Copy to user space if msgbuf is not NULL */ ++ if ((args.buf == NULL) || ++ (copy_to_user((void __user *)args.buf, header->data, ++ header->size) == 0)) ++ { ++ ret = header->size; ++ vchiq_release_message(&user_service->service->base, ++ header); ++ user_service->msg_remove++; ++ vcos_event_signal(&user_service->remove_event); ++ } ++ else ++ ret = -EFAULT; ++ } ++ else ++ { ++ vcos_log_error("header %x: bufsize %x < size %x", ++ (unsigned int)header, args.bufsize, header->size); ++ vcos_assert(0); ++ ret = -EMSGSIZE; ++ } ++ DEBUG_TRACE(DEQUEUE_MESSAGE_LINE); ++ } ++ break; ++ ++ case VCHIQ_IOC_GET_CLIENT_ID: ++ { ++ USER_SERVICE_T *user_service; ++ int handle = (int)arg; ++ ++ user_service = find_service_by_handle(instance, handle); ++ if (user_service != NULL) ++ ret = vchiq_get_client_id(&user_service->service->base); ++ else ++ ret = 0; ++ } ++ break; ++ ++ case VCHIQ_IOC_GET_CONFIG: ++ { ++ VCHIQ_GET_CONFIG_T args; ++ VCHIQ_CONFIG_T config; ++ ++ if (copy_from_user ++ (&args, (const void __user *)arg, ++ sizeof(args)) != 0) { ++ ret = -EFAULT; ++ break; ++ } ++ if (args.config_size > sizeof(config)) ++ { ++ ret = -EINVAL; ++ break; ++ } ++ status = vchiq_get_config(instance, args.config_size, &config); ++ if (status == VCHIQ_SUCCESS) ++ { ++ if (copy_to_user((void __user *)args.pconfig, ++ &config, args.config_size) != 0) ++ { ++ ret = -EFAULT; ++ break; ++ } ++ } ++ } ++ break; ++ ++ case VCHIQ_IOC_SET_SERVICE_OPTION: ++ { ++ VCHIQ_SET_SERVICE_OPTION_T args; ++ USER_SERVICE_T *user_service; ++ ++ if (copy_from_user( ++ &args, (const void __user *)arg, ++ sizeof(args)) != 0) ++ { ++ ret = -EFAULT; ++ break; ++ } ++ ++ user_service = find_service_by_handle(instance, args.handle); ++ if (user_service != NULL) ++ { ++ status = vchiq_set_service_option( ++ &user_service->service->base, ++ args.option, args.value); ++ } ++ else ++ { ++ ret = -EINVAL; ++ } ++ } ++ break; ++ ++ case VCHIQ_IOC_DUMP_PHYS_MEM: ++ { ++ VCHIQ_DUMP_MEM_T args; ++ ++ if (copy_from_user ++ (&args, (const void __user *)arg, ++ sizeof(args)) != 0) { ++ ret = -EFAULT; ++ break; ++ } ++ dump_phys_mem( args.virt_addr, args.num_bytes ); ++ } ++ break; ++ ++ ++ default: ++ ret = -ENOTTY; ++ break; ++ } ++ ++ if (ret == 0) { ++ if (status == VCHIQ_ERROR) ++ ret = -EIO; ++ else if (status == VCHIQ_RETRY) ++ ret = -EINTR; ++ } ++ ++ if ((ret < 0) && (ret != -EINTR) && (ret != -EWOULDBLOCK)) ++ vcos_log_warn(" ioctl instance %lx, cmd %s -> status %d, %ld", ++ (unsigned long)instance, ++ (_IOC_NR(cmd) <= VCHIQ_IOC_MAX) ? ioctl_names[_IOC_NR(cmd)] : ++ "", status, ret); ++ else ++ vcos_log_trace(" ioctl instance %lx, cmd %s -> status %d, %ld", ++ (unsigned long)instance, ++ (_IOC_NR(cmd) <= VCHIQ_IOC_MAX) ? ioctl_names[_IOC_NR(cmd)] : ++ "", status, ret); + +- return ret; ++ return ret; + } + + /**************************************************************************** +@@ -1005,49 +941,39 @@ + static int + vchiq_open(struct inode *inode, struct file *file) + { +- int dev = iminor(inode) & 0x0f; +- vchiq_log_info(vchiq_arm_log_level, "vchiq_open"); +- switch (dev) { +- case VCHIQ_MINOR: { +- int ret; +- VCHIQ_STATE_T *state = vchiq_get_state(); +- VCHIQ_INSTANCE_T instance; +- +- if (!state) { +- vchiq_log_error(vchiq_arm_log_level, +- "vchiq has no connection to VideoCore"); +- return -ENOTCONN; +- } +- +- instance = kzalloc(sizeof(*instance), GFP_KERNEL); +- if (!instance) +- return -ENOMEM; +- +- instance->state = state; +- instance->pid = current->tgid; +- +- ret = vchiq_proc_add_instance(instance); +- if (ret != 0) { +- kfree(instance); +- return ret; +- } +- +- sema_init(&instance->insert_event, 0); +- sema_init(&instance->remove_event, 0); +- mutex_init(&instance->completion_mutex); +- mutex_init(&instance->bulk_waiter_list_mutex); +- INIT_LIST_HEAD(&instance->bulk_waiter_list); +- +- file->private_data = instance; +- } break; +- +- default: +- vchiq_log_error(vchiq_arm_log_level, +- "Unknown minor device: %d", dev); +- return -ENXIO; +- } ++ int dev = iminor(inode) & 0x0f; ++ vcos_log_info("vchiq_open"); ++ switch (dev) { ++ case VCHIQ_MINOR: ++ { ++ VCHIQ_STATE_T *state = vchiq_get_state(); ++ VCHIQ_INSTANCE_T instance; ++ ++ if (!state) ++ { ++ vcos_log_error( "vchiq has no connection to VideoCore"); ++ return -ENOTCONN; ++ } ++ ++ instance = kzalloc(sizeof(*instance), GFP_KERNEL); ++ if (!instance) ++ return -ENOMEM; ++ ++ instance->state = state; ++ instance->pid = current->tgid; ++ vcos_event_create(&instance->insert_event, DEVICE_NAME); ++ vcos_event_create(&instance->remove_event, DEVICE_NAME); ++ ++ file->private_data = instance; ++ } ++ break; ++ ++ default: ++ vcos_log_error("Unknown minor device: %d", dev); ++ return -ENXIO; ++ } + +- return 0; ++ return 0; + } + + /**************************************************************************** +@@ -1059,131 +985,74 @@ + static int + vchiq_release(struct inode *inode, struct file *file) + { +- int dev = iminor(inode) & 0x0f; +- int ret = 0; +- switch (dev) { +- case VCHIQ_MINOR: { +- VCHIQ_INSTANCE_T instance = file->private_data; +- VCHIQ_STATE_T *state = vchiq_get_state(); +- VCHIQ_SERVICE_T *service; +- int i; +- +- vchiq_log_info(vchiq_arm_log_level, +- "vchiq_release: instance=%lx", +- (unsigned long)instance); +- +- if (state) { +- /* Ensure videocore is awake to allow termination. */ +- vchiq_use_internal(instance->state, NULL, +- USE_TYPE_VCHIQ); +- } +- +- mutex_lock(&instance->completion_mutex); +- +- /* Wake the completion thread and ask it to exit */ +- instance->closing = 1; +- up(&instance->insert_event); +- +- mutex_unlock(&instance->completion_mutex); +- +- /* Wake the slot handler if the completion queue is full. */ +- up(&instance->remove_event); +- +- /* Mark all services for termination... */ +- i = 0; +- while ((service = next_service_by_instance(state, instance, +- &i)) != NULL) { +- USER_SERVICE_T *user_service = service->base.userdata; +- +- /* Wake the slot handler if the msg queue is full. */ +- up(&user_service->remove_event); +- +- vchiq_terminate_service_internal(service); +- unlock_service(service); +- } +- +- /* ...and wait for them to die */ +- i = 0; +- while ((service = next_service_by_instance(state, instance, &i)) +- != NULL) { +- USER_SERVICE_T *user_service = service->base.userdata; +- +- down(&service->remove_event); +- +- BUG_ON(service->srvstate != VCHIQ_SRVSTATE_FREE); +- +- spin_lock(&msg_queue_spinlock); +- +- while (user_service->msg_remove != +- user_service->msg_insert) { +- VCHIQ_HEADER_T *header = user_service-> +- msg_queue[user_service->msg_remove & +- (MSG_QUEUE_SIZE - 1)]; +- user_service->msg_remove++; +- spin_unlock(&msg_queue_spinlock); +- +- if (header) +- vchiq_release_message( +- service->handle, +- header); +- spin_lock(&msg_queue_spinlock); +- } +- +- spin_unlock(&msg_queue_spinlock); +- +- unlock_service(service); +- kfree(user_service); +- } +- +- /* Release any closed services */ +- while (instance->completion_remove != +- instance->completion_insert) { +- VCHIQ_COMPLETION_DATA_T *completion; +- VCHIQ_SERVICE_T *service; +- completion = &instance->completions[ +- instance->completion_remove & +- (MAX_COMPLETIONS - 1)]; +- service = completion->service_userdata; +- if (completion->reason == VCHIQ_SERVICE_CLOSED) +- unlock_service(service); +- instance->completion_remove++; +- } +- +- if (state) { +- /* Release the PEER service count. */ +- vchiq_release_internal(instance->state, NULL); +- } +- +- { +- struct list_head *pos, *next; +- list_for_each_safe(pos, next, +- &instance->bulk_waiter_list) { +- struct bulk_waiter_node *waiter; +- waiter = list_entry(pos, +- struct bulk_waiter_node, +- list); +- list_del(pos); +- vchiq_log_info(vchiq_arm_log_level, +- "bulk_waiter - cleaned up %x " +- "for pid %d", +- (unsigned int)waiter, waiter->pid); +- kfree(waiter); +- } +- } +- +- vchiq_proc_remove_instance(instance); +- +- kfree(instance); +- file->private_data = NULL; +- } break; +- +- default: +- vchiq_log_error(vchiq_arm_log_level, +- "Unknown minor device: %d", dev); +- ret = -ENXIO; +- } ++ int dev = iminor(inode) & 0x0f; ++ int ret = 0; ++ switch (dev) { ++ case VCHIQ_MINOR: ++ { ++ VCHIQ_INSTANCE_T instance = file->private_data; ++ int i; ++ ++ vcos_log_info("vchiq_release: instance=%lx", ++ (unsigned long)instance); ++ ++ instance->closing = 1; ++ ++ /* Wake the slot handler if the completion queue is full */ ++ vcos_event_signal(&instance->remove_event); ++ ++ /* Mark all services for termination... */ ++ ++ for (i = 0; i < MAX_SERVICES; i++) { ++ USER_SERVICE_T *user_service = ++ &instance->services[i]; ++ if (user_service->service != NULL) ++ { ++ /* Wake the slot handler if the msg queue is full */ ++ vcos_event_signal(&user_service->remove_event); ++ ++ if ((user_service->service->srvstate != VCHIQ_SRVSTATE_CLOSEWAIT) && ++ (user_service->service->srvstate != VCHIQ_SRVSTATE_LISTENING)) ++ { ++ vchiq_terminate_service_internal(user_service->service); ++ } ++ } ++ } ++ ++ /* ...and wait for them to die */ ++ ++ for (i = 0; i < MAX_SERVICES; i++) { ++ USER_SERVICE_T *user_service = ++ &instance->services[i]; ++ if (user_service->service != NULL) ++ { ++ /* Wait in this non-portable fashion because interruptible ++ calls will not block in this context. */ ++ while ((user_service->service->srvstate != VCHIQ_SRVSTATE_CLOSEWAIT) && ++ (user_service->service->srvstate != VCHIQ_SRVSTATE_LISTENING)) ++ { ++ down(&user_service->service->remove_event); ++ } ++ ++ vchiq_free_service_internal ++ (user_service->service); ++ } ++ } ++ ++ vcos_event_delete(&instance->insert_event); ++ vcos_event_delete(&instance->remove_event); ++ ++ kfree(instance); ++ file->private_data = NULL; ++ } ++ break; ++ ++ default: ++ vcos_log_error("Unknown minor device: %d", dev); ++ ret = -ENXIO; ++ } + +- return ret; ++ return ret; + } + + /**************************************************************************** +@@ -1195,37 +1064,40 @@ + void + vchiq_dump(void *dump_context, const char *str, int len) + { +- DUMP_CONTEXT_T *context = (DUMP_CONTEXT_T *)dump_context; ++ DUMP_CONTEXT_T *context = (DUMP_CONTEXT_T *)dump_context; + +- if ((context->actual >= 0) && (context->actual < context->space)) { +- int copy_bytes; +- if (context->offset > 0) { +- int skip_bytes = min(len, (int)context->offset); +- str += skip_bytes; +- len -= skip_bytes; +- context->offset -= skip_bytes; +- if (context->offset > 0) +- return; +- } +- copy_bytes = min(len, (int)(context->space - context->actual)); +- if (copy_bytes == 0) +- return; +- if (copy_to_user(context->buf + context->actual, str, +- copy_bytes)) +- context->actual = -EFAULT; +- context->actual += copy_bytes; +- len -= copy_bytes; +- +- /* If tne terminating NUL is included in the length, then it +- ** marks the end of a line and should be replaced with a +- ** carriage return. */ +- if ((len == 0) && (str[copy_bytes - 1] == '\0')) { +- char cr = '\n'; +- if (copy_to_user(context->buf + context->actual - 1, +- &cr, 1)) +- context->actual = -EFAULT; +- } +- } ++ if ((context->actual >= 0) && (context->actual < context->space)) ++ { ++ int copy_bytes; ++ if (context->offset > 0) ++ { ++ int skip_bytes = vcos_min(len, context->offset); ++ str += skip_bytes; ++ len -= skip_bytes; ++ context->offset -= skip_bytes; ++ if (context->offset > 0) ++ return; ++ } ++ copy_bytes = vcos_min(len, context->space - context->actual); ++ if (copy_bytes == 0) ++ return; ++ if (copy_to_user(context->buf + context->actual, str, copy_bytes)) ++ context->actual = -EFAULT; ++ context->actual += copy_bytes; ++ len -= copy_bytes; ++ ++ /* If tne terminating NUL is included in the length, then it marks ++ * the end of a line and should be replaced with a carriage return. ++ */ ++ if ((len == 0) && (str[copy_bytes - 1] == '\0')) ++ { ++ char cr = '\n'; ++ if (copy_to_user(context->buf + context->actual - 1, &cr, 1)) ++ { ++ context->actual = -EFAULT; ++ } ++ } ++ } + } + + /**************************************************************************** +@@ -1237,48 +1109,49 @@ + void + vchiq_dump_platform_instances(void *dump_context) + { +- VCHIQ_STATE_T *state = vchiq_get_state(); +- char buf[80]; +- int len; +- int i; +- +- /* There is no list of instances, so instead scan all services, +- marking those that have been dumped. */ +- +- for (i = 0; i < state->unused_service; i++) { +- VCHIQ_SERVICE_T *service = state->services[i]; +- VCHIQ_INSTANCE_T instance; +- +- if (service && (service->base.callback == service_callback)) { +- instance = service->instance; +- if (instance) +- instance->mark = 0; +- } +- } +- +- for (i = 0; i < state->unused_service; i++) { +- VCHIQ_SERVICE_T *service = state->services[i]; +- VCHIQ_INSTANCE_T instance; +- +- if (service && (service->base.callback == service_callback)) { +- instance = service->instance; +- if (instance && !instance->mark) { +- len = snprintf(buf, sizeof(buf), +- "Instance %x: pid %d,%s completions " +- "%d/%d", +- (unsigned int)instance, instance->pid, +- instance->connected ? " connected, " : +- "", +- instance->completion_insert - +- instance->completion_remove, +- MAX_COMPLETIONS); +- +- vchiq_dump(dump_context, buf, len + 1); +- +- instance->mark = 1; +- } +- } +- } ++ VCHIQ_STATE_T *state = vchiq_get_state(); ++ char buf[80]; ++ int len; ++ int i; ++ ++ /* There is no list of instances, so instead scan all services, ++ marking those that have been dumped. */ ++ ++ for (i = 0; i < state->unused_service; i++) ++ { ++ VCHIQ_SERVICE_T *service = state->services[i]; ++ VCHIQ_INSTANCE_T instance; ++ ++ if (service ++ && ((instance = service->instance) != NULL) ++ && (service->base.callback == service_callback)) ++ instance->mark = 0; ++ } ++ ++ for (i = 0; i < state->unused_service; i++) ++ { ++ VCHIQ_SERVICE_T *service = state->services[i]; ++ VCHIQ_INSTANCE_T instance; ++ ++ if (service ++ && ((instance = service->instance) != NULL) ++ && (service->base.callback == service_callback)) ++ { ++ if (!instance->mark) ++ { ++ len = vcos_snprintf(buf, sizeof(buf), ++ "Instance %x: pid %d,%s completions %d/%d", ++ (unsigned int)instance, instance->pid, ++ instance->connected ? " connected," : "", ++ instance->completion_insert - instance->completion_remove, ++ MAX_COMPLETIONS); ++ ++ vchiq_dump(dump_context, buf, len + 1); ++ ++ instance->mark = 1; ++ } ++ } ++ } + } + + /**************************************************************************** +@@ -1290,26 +1163,26 @@ + void + vchiq_dump_platform_service_state(void *dump_context, VCHIQ_SERVICE_T *service) + { +- USER_SERVICE_T *user_service = (USER_SERVICE_T *)service->base.userdata; +- char buf[80]; +- int len; +- +- len = snprintf(buf, sizeof(buf), " instance %x", +- (unsigned int)service->instance); +- +- if ((service->base.callback == service_callback) && +- user_service->is_vchi) { +- len += snprintf(buf + len, sizeof(buf) - len, +- ", %d/%d messages", +- user_service->msg_insert - user_service->msg_remove, +- MSG_QUEUE_SIZE); +- +- if (user_service->dequeue_pending) +- len += snprintf(buf + len, sizeof(buf) - len, +- " (dequeue pending)"); +- } ++ USER_SERVICE_T *user_service = (USER_SERVICE_T *)service->base.userdata; ++ char buf[80]; ++ int len; ++ ++ len = vcos_snprintf(buf, sizeof(buf), " instance %x", ++ service->instance); ++ ++ if ((service->base.callback == service_callback) && user_service->is_vchi) ++ { ++ len += vcos_snprintf(buf + len, sizeof(buf) - len, ++ ", %d/%d messages", ++ user_service->msg_insert - user_service->msg_remove, ++ MSG_QUEUE_SIZE); ++ ++ if (user_service->dequeue_pending) ++ len += vcos_snprintf(buf + len, sizeof(buf) - len, ++ " (dequeue pending)"); ++ } + +- vchiq_dump(dump_context, buf, len + 1); ++ vchiq_dump(dump_context, buf, len + 1); + } + + /**************************************************************************** +@@ -1319,82 +1192,79 @@ + ***************************************************************************/ + + static void +-dump_phys_mem(void *virt_addr, uint32_t num_bytes) ++dump_phys_mem( void *virt_addr, uint32_t num_bytes ) + { +- int rc; +- uint8_t *end_virt_addr = virt_addr + num_bytes; +- int num_pages; +- int offset; +- int end_offset; +- int page_idx; +- int prev_idx; +- struct page *page; +- struct page **pages; +- uint8_t *kmapped_virt_ptr; +- +- /* Align virtAddr and endVirtAddr to 16 byte boundaries. */ +- +- virt_addr = (void *)((unsigned long)virt_addr & ~0x0fuL); +- end_virt_addr = (void *)(((unsigned long)end_virt_addr + 15uL) & +- ~0x0fuL); +- +- offset = (int)(long)virt_addr & (PAGE_SIZE - 1); +- end_offset = (int)(long)end_virt_addr & (PAGE_SIZE - 1); +- +- num_pages = (offset + num_bytes + PAGE_SIZE - 1) / PAGE_SIZE; +- +- pages = kmalloc(sizeof(struct page *) * num_pages, GFP_KERNEL); +- if (pages == NULL) { +- vchiq_log_error(vchiq_arm_log_level, +- "Unable to allocation memory for %d pages\n", +- num_pages); +- return; +- } +- +- down_read(¤t->mm->mmap_sem); +- rc = get_user_pages(current, /* task */ +- current->mm, /* mm */ +- (unsigned long)virt_addr, /* start */ +- num_pages, /* len */ +- 0, /* write */ +- 0, /* force */ +- pages, /* pages (array of page pointers) */ +- NULL); /* vmas */ +- up_read(¤t->mm->mmap_sem); +- +- prev_idx = -1; +- page = NULL; +- +- while (offset < end_offset) { +- +- page_idx = offset / PAGE_SIZE; +- int page_offset = offset % PAGE_SIZE; +- +- if (page_idx != prev_idx) { +- +- if (page != NULL) +- kunmap(page); +- page = pages[page_idx]; +- kmapped_virt_ptr = kmap(page); +- +- prev_idx = page_idx; +- } +- +- if (vchiq_arm_log_level >= VCHIQ_LOG_TRACE) +- vchiq_log_dump_mem("ph", +- (uint32_t)(unsigned long)&kmapped_virt_ptr[ +- page_offset], +- &kmapped_virt_ptr[page_offset], 16); +- +- offset += 16; +- } +- if (page != NULL) +- kunmap(page); +- +- for (page_idx = 0; page_idx < num_pages; page_idx++) +- page_cache_release(pages[page_idx]); +- +- kfree(pages); ++ int rc; ++ uint8_t *end_virt_addr = virt_addr + num_bytes; ++ int num_pages; ++ int offset; ++ int end_offset; ++ int page_idx; ++ int prev_idx; ++ struct page *page; ++ struct page **pages; ++ uint8_t *kmapped_virt_ptr; ++ ++ // Align virtAddr and endVirtAddr to 16 byte boundaries. ++ ++ virt_addr = (void *)((unsigned long)virt_addr & ~0x0fuL ); ++ end_virt_addr = (void *)(( (unsigned long)end_virt_addr + 15uL ) & ~0x0fuL); ++ ++ offset = (int)(long)virt_addr & ( PAGE_SIZE - 1 ); ++ end_offset = (int)(long)end_virt_addr & ( PAGE_SIZE - 1 ); ++ ++ num_pages = (offset + num_bytes + PAGE_SIZE - 1) / PAGE_SIZE; ++ ++ if (( pages = kmalloc( sizeof( struct page *) * num_pages, GFP_KERNEL )) == NULL ) ++ { ++ printk( KERN_ERR "Unable to allocation memory for %d pages\n", num_pages ); ++ return; ++ } ++ ++ down_read( ¤t->mm->mmap_sem ); ++ rc = get_user_pages( current, /* task */ ++ current->mm, /* mm */ ++ (unsigned long)virt_addr, /* start */ ++ num_pages, /* len */ ++ 0, /* write */ ++ 0, /* force */ ++ pages, /* pages (array of pointers to page) */ ++ NULL ); /* vmas */ ++ up_read( ¤t->mm->mmap_sem ); ++ ++ prev_idx = -1; ++ page = NULL; ++ ++ while ( offset < end_offset ) { ++ ++ int page_offset = offset % PAGE_SIZE; ++ page_idx = offset / PAGE_SIZE; ++ ++ if ( page_idx != prev_idx ) { ++ ++ if (page != NULL) { ++ kunmap( page ); ++ } ++ page = pages[page_idx]; ++ kmapped_virt_ptr = kmap( page ); ++ ++ prev_idx = page_idx; ++ } ++ ++ vcos_log_dump_mem_impl( &vchiq_arm_log_category, "ph", ++ (uint32_t)(unsigned long)&kmapped_virt_ptr[page_offset], ++ &kmapped_virt_ptr[page_offset], 16 ); ++ ++ offset += 16; ++ } ++ if (page != NULL) { ++ kunmap( page ); ++ } ++ ++ for ( page_idx = 0; page_idx < num_pages; page_idx++ ) { ++ page_cache_release( pages[page_idx] ); ++ } ++ kfree( pages ); + } + + /**************************************************************************** +@@ -1404,1182 +1274,548 @@ + ***************************************************************************/ + + static ssize_t +-vchiq_read(struct file *file, char __user *buf, +- size_t count, loff_t *ppos) ++vchiq_read(struct file * file, char __user * buf, ++ size_t count, loff_t *ppos) + { +- DUMP_CONTEXT_T context; +- context.buf = buf; +- context.actual = 0; +- context.space = count; +- context.offset = *ppos; ++ DUMP_CONTEXT_T context; ++ context.buf = buf; ++ context.actual = 0; ++ context.space = count; ++ context.offset = *ppos; + +- vchiq_dump_state(&context, &g_state); ++ vchiq_dump_state(&context, &g_state); + +- if (context.actual >= 0) +- *ppos += context.actual; ++ if (context.actual >= 0) ++ *ppos += context.actual; + +- return context.actual; ++ return context.actual; + } + + VCHIQ_STATE_T * + vchiq_get_state(void) + { + +- if (g_state.remote == NULL) +- printk(KERN_ERR "%s: g_state.remote == NULL\n", __func__); +- else if (g_state.remote->initialised != 1) +- printk(KERN_ERR "%s: g_state.remote->initialised != 1 (%d)\n", +- __func__, g_state.remote->initialised); ++ if (g_state.remote == NULL) ++ { ++ printk( "%s: g_state.remote == NULL\n", __func__ ); ++ } ++ else ++ { ++ if ( g_state.remote->initialised != 1) ++ { ++ printk( "%s: g_state.remote->initialised != 1 (%d)\n", __func__, g_state.remote->initialised ); ++ } ++ } + +- return ((g_state.remote != NULL) && +- (g_state.remote->initialised == 1)) ? &g_state : NULL; ++ return ((g_state.remote != NULL) && ++ (g_state.remote->initialised == 1)) ? &g_state : NULL; + } + + static const struct file_operations + vchiq_fops = { +- .owner = THIS_MODULE, +- .unlocked_ioctl = vchiq_ioctl, +- .open = vchiq_open, +- .release = vchiq_release, +- .read = vchiq_read ++ .owner = THIS_MODULE, ++ .unlocked_ioctl = vchiq_ioctl, ++ .open = vchiq_open, ++ .release = vchiq_release, ++ .read = vchiq_read + }; + + /* + * Autosuspend related functionality + */ + +-int +-vchiq_videocore_wanted(VCHIQ_STATE_T *state) +-{ +- VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state); +- if (!arm_state) +- /* autosuspend not supported - always return wanted */ +- return 1; +- else if (arm_state->blocked_count) +- return 1; +- else if (!arm_state->videocore_use_count) +- /* usage count zero - check for override unless we're forcing */ +- if (arm_state->resume_blocked) +- return 0; +- else +- return vchiq_platform_videocore_wanted(state); +- else +- /* non-zero usage count - videocore still required */ +- return 1; +-} +-static VCHIQ_STATUS_T vchiq_keepalive_vchiq_callback(VCHIQ_REASON_T reason, +- VCHIQ_HEADER_T *header, +- VCHIQ_SERVICE_HANDLE_T service_user, +- void *bulk_user) +-{ +- vchiq_log_error(vchiq_susp_log_level, +- "%s callback reason %d", __func__, reason); +- return 0; +-} +- +-static int +-vchiq_keepalive_thread_func(void *v) ++static int vchiq_videocore_wanted(VCHIQ_STATE_T* state) + { +- VCHIQ_STATE_T *state = (VCHIQ_STATE_T *) v; +- VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state); +- +- VCHIQ_STATUS_T status; +- VCHIQ_INSTANCE_T instance; +- VCHIQ_SERVICE_HANDLE_T ka_handle; +- +- VCHIQ_SERVICE_PARAMS_T params = { +- .fourcc = VCHIQ_MAKE_FOURCC('K', 'E', 'E', 'P'), +- .callback = vchiq_keepalive_vchiq_callback, +- .version = KEEPALIVE_VER, +- .version_min = KEEPALIVE_VER_MIN +- }; +- +- status = vchiq_initialise(&instance); +- if (status != VCHIQ_SUCCESS) { +- vchiq_log_error(vchiq_susp_log_level, +- "%s vchiq_initialise failed %d", __func__, status); +- goto exit; +- } +- +- status = vchiq_connect(instance); +- if (status != VCHIQ_SUCCESS) { +- vchiq_log_error(vchiq_susp_log_level, +- "%s vchiq_connect failed %d", __func__, status); +- goto shutdown; +- } +- +- status = vchiq_add_service(instance, ¶ms, &ka_handle); +- if (status != VCHIQ_SUCCESS) { +- vchiq_log_error(vchiq_susp_log_level, +- "%s vchiq_open_service failed %d", __func__, status); +- goto shutdown; +- } +- +- while (1) { +- long rc = 0, uc = 0; +- if (wait_for_completion_interruptible(&arm_state->ka_evt) +- != 0) { +- vchiq_log_error(vchiq_susp_log_level, +- "%s interrupted", __func__); +- flush_signals(current); +- continue; +- } +- +- /* read and clear counters. Do release_count then use_count to +- * prevent getting more releases than uses */ +- rc = atomic_xchg(&arm_state->ka_release_count, 0); +- uc = atomic_xchg(&arm_state->ka_use_count, 0); +- +- /* Call use/release service the requisite number of times. +- * Process use before release so use counts don't go negative */ +- while (uc--) { +- atomic_inc(&arm_state->ka_use_ack_count); +- status = vchiq_use_service(ka_handle); +- if (status != VCHIQ_SUCCESS) { +- vchiq_log_error(vchiq_susp_log_level, +- "%s vchiq_use_service error %d", +- __func__, status); +- } +- } +- while (rc--) { +- status = vchiq_release_service(ka_handle); +- if (status != VCHIQ_SUCCESS) { +- vchiq_log_error(vchiq_susp_log_level, +- "%s vchiq_release_service error %d", +- __func__, status); +- } +- } +- } +- +-shutdown: +- vchiq_shutdown(instance); +-exit: +- return 0; ++ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state); ++ if(!arm_state) ++ { // autosuspend not supported - always return wanted ++ return 1; ++ } ++ else if(!arm_state->videocore_use_count) ++ { // usage count zero - check for override ++ return vchiq_platform_videocore_wanted(state); ++ } ++ else ++ { // non-zero usage count - videocore still required ++ return 1; ++ } ++} ++ ++ ++/* Called by the lp thread */ ++static void * ++lp_func(void *v) ++{ ++ VCHIQ_STATE_T *state = (VCHIQ_STATE_T *) v; ++ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state); ++ ++ while (1) { ++ vcos_event_wait(&arm_state->lp_evt); ++ ++ vcos_mutex_lock(&arm_state->use_count_mutex); ++ if (!vchiq_videocore_wanted(state)) ++ { ++ arm_state->suspend_pending = 1; ++ } ++ vcos_mutex_unlock(&arm_state->use_count_mutex); ++ ++ vchiq_arm_vcsuspend(state); ++ } ++ return NULL; ++} ++/* Called by the hp thread */ ++static void * ++hp_func(void *v) ++{ ++ VCHIQ_STATE_T *state = (VCHIQ_STATE_T *) v; ++ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state); ++ int send_pending; ++ ++ while (1) { ++ vcos_event_wait(&arm_state->hp_evt); ++ ++ send_pending = 0; ++ ++ vcos_mutex_lock(&arm_state->use_count_mutex); ++ if (vchiq_videocore_wanted(state)) ++ { ++ vchiq_arm_vcresume(state); ++ } ++ if(arm_state->use_notify_pending) ++ { ++ send_pending = arm_state->use_notify_pending; ++ arm_state->use_notify_pending=0; ++ } ++ vcos_mutex_unlock(&arm_state->use_count_mutex); ++ while(send_pending--) ++ { ++ vcos_log_info( "%s sending VCHIQ_MSG_REMOTE_USE_ACTIVE", __func__); ++ if ( vchiq_send_remote_use_active(state) != VCHIQ_SUCCESS) ++ { ++ BUG(); /* vc should be resumed, so shouldn't be a problem sending message */ ++ } ++ } ++ } ++ return NULL; + } + +- + VCHIQ_STATUS_T +-vchiq_arm_init_state(VCHIQ_STATE_T *state, VCHIQ_ARM_STATE_T *arm_state) ++vchiq_arm_init_state(VCHIQ_STATE_T* state, VCHIQ_ARM_STATE_T *arm_state) + { +- VCHIQ_STATUS_T status = VCHIQ_SUCCESS; +- char threadname[10]; +- +- if (arm_state) { +- mutex_init(&arm_state->vc_use_cnt_mutex); +- rwlock_init(&arm_state->susp_res_lock); +- +- init_completion(&arm_state->ka_evt); +- atomic_set(&arm_state->ka_use_count, 0); +- atomic_set(&arm_state->ka_use_ack_count, 0); +- atomic_set(&arm_state->ka_release_count, 0); +- +- init_completion(&arm_state->vc_suspend_complete); +- +- init_completion(&arm_state->vc_resume_complete); +- /* Initialise to 'done' state. We only want to block on resume +- * completion while videocore is suspended. */ +- set_resume_state(arm_state, VC_RESUME_RESUMED); +- +- init_completion(&arm_state->resume_blocker); +- /* Initialise to 'done' state. We only want to block on this +- * completion while resume is blocked */ +- complete_all(&arm_state->resume_blocker); +- +- init_completion(&arm_state->blocked_blocker); +- /* Initialise to 'done' state. We only want to block on this +- * completion while things are waiting on the resume blocker */ +- complete_all(&arm_state->blocked_blocker); +- +- snprintf(threadname, sizeof(threadname), "VCHIQka-%d", +- state->id); +- arm_state->ka_thread = kthread_create( +- &vchiq_keepalive_thread_func, +- (void *)state, +- threadname); +- if (arm_state->ka_thread == NULL) { +- vchiq_log_error(vchiq_susp_log_level, +- "vchiq: FATAL: couldn't create thread %s", +- threadname); +- status = VCHIQ_ERROR; +- } +- +- arm_state->suspend_timer_timeout = SUSPEND_TIMER_TIMEOUT_MS; +- arm_state->suspend_timer_running = 0; +- init_timer(&arm_state->suspend_timer); +- arm_state->suspend_timer.data = (unsigned long)(state); +- arm_state->suspend_timer.function = suspend_timer_callback; +- +- arm_state->first_connect = 0; +- +- } +- return status; ++ VCHIQ_STATUS_T status = VCHIQ_SUCCESS; ++ VCOS_THREAD_ATTR_T attrs; ++ char threadname[10]; ++ ++ if(arm_state) ++ { ++ vcos_mutex_create(&arm_state->use_count_mutex, "v.use_count_mutex"); ++ vcos_mutex_create(&arm_state->suspend_resume_mutex, "v.susp_res_mutex"); ++ ++ vcos_event_create(&arm_state->lp_evt, "LP_EVT"); ++ vcos_event_create(&arm_state->hp_evt, "HP_EVT"); ++ ++ vcos_thread_attr_init(&attrs); ++ vcos_thread_attr_setstacksize(&attrs, VCHIQ_ARM_VCSUSPEND_TASK_STACK); ++ vcos_thread_attr_setpriority(&attrs, VCOS_THREAD_PRI_LOWEST); ++ vcos_snprintf(threadname, sizeof(threadname), "VCHIQl-%d", state->id); ++ if(vcos_thread_create(&arm_state->lp_thread, threadname, &attrs, lp_func, state) != VCOS_SUCCESS) ++ { ++ vcos_log_error("vchiq: FATAL: couldn't create thread %s", threadname); ++ status = VCHIQ_ERROR; ++ } ++ else ++ { ++ vcos_thread_attr_init(&attrs); ++ vcos_thread_attr_setstacksize(&attrs, VCHIQ_ARM_VCSUSPEND_TASK_STACK); ++ vcos_thread_attr_setpriority(&attrs, VCOS_THREAD_PRI_HIGHEST); ++ vcos_snprintf(threadname, sizeof(threadname), "VCHIQh-%d", state->id); ++ ++ if(vcos_thread_create(&arm_state->hp_thread, threadname, &attrs, hp_func, state) != VCOS_SUCCESS) ++ { ++ vcos_log_error("vchiq: FATAL: couldn't create thread %s", threadname); ++ status = VCHIQ_ERROR; ++ } ++ } ++ } ++ return status; + } + +-/* +-** Functions to modify the state variables; +-** set_suspend_state +-** set_resume_state +-** +-** There are more state variables than we might like, so ensure they remain in +-** step. Suspend and resume state are maintained separately, since most of +-** these state machines can operate independently. However, there are a few +-** states where state transitions in one state machine cause a reset to the +-** other state machine. In addition, there are some completion events which +-** need to occur on state machine reset and end-state(s), so these are also +-** dealt with in these functions. +-** +-** In all states we set the state variable according to the input, but in some +-** cases we perform additional steps outlined below; +-** +-** VC_SUSPEND_IDLE - Initialise the suspend completion at the same time. +-** The suspend completion is completed after any suspend +-** attempt. When we reset the state machine we also reset +-** the completion. This reset occurs when videocore is +-** resumed, and also if we initiate suspend after a suspend +-** failure. +-** +-** VC_SUSPEND_IN_PROGRESS - This state is considered the point of no return for +-** suspend - ie from this point on we must try to suspend +-** before resuming can occur. We therefore also reset the +-** resume state machine to VC_RESUME_IDLE in this state. +-** +-** VC_SUSPEND_SUSPENDED - Suspend has completed successfully. Also call +-** complete_all on the suspend completion to notify +-** anything waiting for suspend to happen. +-** +-** VC_SUSPEND_REJECTED - Videocore rejected suspend. Videocore will also +-** initiate resume, so no need to alter resume state. +-** We call complete_all on the suspend completion to notify +-** of suspend rejection. +-** +-** VC_SUSPEND_FAILED - We failed to initiate videocore suspend. We notify the +-** suspend completion and reset the resume state machine. +-** +-** VC_RESUME_IDLE - Initialise the resume completion at the same time. The +-** resume completion is in it's 'done' state whenever +-** videcore is running. Therfore, the VC_RESUME_IDLE state +-** implies that videocore is suspended. +-** Hence, any thread which needs to wait until videocore is +-** running can wait on this completion - it will only block +-** if videocore is suspended. +-** +-** VC_RESUME_RESUMED - Resume has completed successfully. Videocore is running. +-** Call complete_all on the resume completion to unblock +-** any threads waiting for resume. Also reset the suspend +-** state machine to it's idle state. +-** +-** VC_RESUME_FAILED - Currently unused - no mechanism to fail resume exists. +-*/ +- +-inline void +-set_suspend_state(VCHIQ_ARM_STATE_T *arm_state, +- enum vc_suspend_status new_state) +-{ +- /* set the state in all cases */ +- arm_state->vc_suspend_state = new_state; +- +- /* state specific additional actions */ +- switch (new_state) { +- case VC_SUSPEND_FORCE_CANCELED: +- complete_all(&arm_state->vc_suspend_complete); +- break; +- case VC_SUSPEND_REJECTED: +- complete_all(&arm_state->vc_suspend_complete); +- break; +- case VC_SUSPEND_FAILED: +- complete_all(&arm_state->vc_suspend_complete); +- arm_state->vc_resume_state = VC_RESUME_RESUMED; +- complete_all(&arm_state->vc_resume_complete); +- break; +- case VC_SUSPEND_IDLE: +- INIT_COMPLETION(arm_state->vc_suspend_complete); +- break; +- case VC_SUSPEND_REQUESTED: +- break; +- case VC_SUSPEND_IN_PROGRESS: +- set_resume_state(arm_state, VC_RESUME_IDLE); +- break; +- case VC_SUSPEND_SUSPENDED: +- complete_all(&arm_state->vc_suspend_complete); +- break; +- default: +- BUG(); +- break; +- } +-} +- +-inline void +-set_resume_state(VCHIQ_ARM_STATE_T *arm_state, +- enum vc_resume_status new_state) +-{ +- /* set the state in all cases */ +- arm_state->vc_resume_state = new_state; +- +- /* state specific additional actions */ +- switch (new_state) { +- case VC_RESUME_FAILED: +- break; +- case VC_RESUME_IDLE: +- INIT_COMPLETION(arm_state->vc_resume_complete); +- break; +- case VC_RESUME_REQUESTED: +- break; +- case VC_RESUME_IN_PROGRESS: +- break; +- case VC_RESUME_RESUMED: +- complete_all(&arm_state->vc_resume_complete); +- set_suspend_state(arm_state, VC_SUSPEND_IDLE); +- break; +- default: +- BUG(); +- break; +- } +-} +- +- +-/* should be called with the write lock held */ +-inline void +-start_suspend_timer(VCHIQ_ARM_STATE_T *arm_state) +-{ +- del_timer(&arm_state->suspend_timer); +- arm_state->suspend_timer.expires = jiffies + +- msecs_to_jiffies(arm_state-> +- suspend_timer_timeout); +- add_timer(&arm_state->suspend_timer); +- arm_state->suspend_timer_running = 1; +-} +- +-/* should be called with the write lock held */ +-static inline void +-stop_suspend_timer(VCHIQ_ARM_STATE_T *arm_state) +-{ +- if (arm_state->suspend_timer_running) { +- del_timer(&arm_state->suspend_timer); +- arm_state->suspend_timer_running = 0; +- } +-} +- +-static inline int +-need_resume(VCHIQ_STATE_T *state) +-{ +- VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state); +- return (arm_state->vc_suspend_state > VC_SUSPEND_IDLE) && +- (arm_state->vc_resume_state < VC_RESUME_REQUESTED) && +- vchiq_videocore_wanted(state); +-} + +-static int +-block_resume(VCHIQ_ARM_STATE_T *arm_state) +-{ +- int status = VCHIQ_SUCCESS; +- while (arm_state->blocked_count) { +- INIT_COMPLETION(arm_state->blocked_blocker); +- write_unlock_bh(&arm_state->susp_res_lock); +- vchiq_log_info(vchiq_susp_log_level, "%s wait for previously " +- "blocked clients", __func__); +- if (wait_for_completion_interruptible_timeout( +- &arm_state->blocked_blocker, +- msecs_to_jiffies(FORCE_SUSPEND_TIMEOUT_MS)) +- <= 0) { +- vchiq_log_error(vchiq_susp_log_level, "%s wait for " +- "previously blocked clients failed" , __func__); +- status = VCHIQ_ERROR; +- write_lock_bh(&arm_state->susp_res_lock); +- goto out; +- } +- vchiq_log_info(vchiq_susp_log_level, "%s previously blocked " +- "clients resumed", __func__); +- write_lock_bh(&arm_state->susp_res_lock); +- } +- while (arm_state->vc_resume_state != VC_RESUME_RESUMED && +- arm_state->vc_resume_state > VC_RESUME_IDLE) { +- if (!try_wait_for_completion(&arm_state->vc_resume_complete)) { +- write_unlock_bh(&arm_state->susp_res_lock); +- vchiq_log_info(vchiq_susp_log_level, "%s wait for " +- "resume", __func__); +- if (wait_for_completion_interruptible_timeout( +- &arm_state->vc_resume_complete, +- msecs_to_jiffies( +- FORCE_SUSPEND_TIMEOUT_MS)) +- <= 0) { +- vchiq_log_error(vchiq_susp_log_level, "%s wait " +- "for resume failed (%s)", __func__, +- resume_state_names[ +- arm_state->vc_resume_state + +- VC_RESUME_NUM_OFFSET]); +- status = VCHIQ_ERROR; +- write_lock_bh(&arm_state->susp_res_lock); +- goto out; +- } +- vchiq_log_info(vchiq_susp_log_level, "%s resumed", +- __func__); +- write_lock_bh(&arm_state->susp_res_lock); +- } +- } +- INIT_COMPLETION(arm_state->resume_blocker); +- arm_state->resume_blocked = 1; +- +-out: +- return status; +-} +- +-inline static void +-unblock_resume(VCHIQ_ARM_STATE_T *arm_state) +-{ +- complete_all(&arm_state->resume_blocker); +- arm_state->resume_blocked = 0; +-} +- +-/* Initiate suspend via slot handler. Should be called with the write lock +- * held */ + VCHIQ_STATUS_T + vchiq_arm_vcsuspend(VCHIQ_STATE_T *state) + { +- VCHIQ_STATUS_T status = VCHIQ_ERROR; +- VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state); +- +- if (!arm_state) +- goto out; +- +- vchiq_log_trace(vchiq_susp_log_level, "%s", __func__); +- status = VCHIQ_SUCCESS; +- +- +- switch (arm_state->vc_suspend_state) { +- case VC_SUSPEND_REQUESTED: +- vchiq_log_info(vchiq_susp_log_level, "%s: suspend already " +- "requested", __func__); +- break; +- case VC_SUSPEND_IN_PROGRESS: +- vchiq_log_info(vchiq_susp_log_level, "%s: suspend already in " +- "progress", __func__); +- break; +- +- default: +- /* We don't expect to be in other states, so log but continue +- * anyway */ +- vchiq_log_error(vchiq_susp_log_level, +- "%s unexpected suspend state %s", __func__, +- suspend_state_names[arm_state->vc_suspend_state + +- VC_SUSPEND_NUM_OFFSET]); +- /* fall through */ +- case VC_SUSPEND_REJECTED: +- case VC_SUSPEND_FAILED: +- INIT_COMPLETION(arm_state->vc_suspend_complete); +- /* fall through */ +- case VC_SUSPEND_IDLE: +- vchiq_log_info(vchiq_susp_log_level, +- "%s: suspending", __func__); +- set_suspend_state(arm_state, VC_SUSPEND_REQUESTED); +- /* kick the slot handler thread to initiate suspend */ +- request_poll(state, NULL, 0); +- break; +- } +- +-out: +- vchiq_log_trace(vchiq_susp_log_level, "%s exit %d", __func__, status); +- return status; +-} +- +-void +-vchiq_platform_check_suspend(VCHIQ_STATE_T *state) +-{ +- VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state); +- int susp = 0; +- +- if (!arm_state) +- goto out; +- +- vchiq_log_trace(vchiq_susp_log_level, "%s", __func__); +- +- write_lock_bh(&arm_state->susp_res_lock); +- if (arm_state->vc_suspend_state == VC_SUSPEND_REQUESTED && +- arm_state->vc_resume_state == VC_RESUME_RESUMED) { +- set_suspend_state(arm_state, VC_SUSPEND_IN_PROGRESS); +- susp = 1; +- } +- write_unlock_bh(&arm_state->susp_res_lock); ++ VCHIQ_STATUS_T status = VCHIQ_SUCCESS; ++ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state); + +- if (susp) +- vchiq_platform_suspend(state); ++ if (state->conn_state != VCHIQ_CONNSTATE_CONNECTED) ++ return VCHIQ_ERROR; + +-out: +- vchiq_log_trace(vchiq_susp_log_level, "%s exit", __func__); +- return; ++ if(arm_state->suspend_pending) ++ { ++ vcos_mutex_lock(&arm_state->suspend_resume_mutex); ++ if(arm_state->videocore_suspended) ++ { ++ vcos_log_info("%s - already suspended", __func__); ++ } ++ else ++ { ++ vcos_log_info("%s - suspending", __func__); ++ ++ status = vchiq_platform_suspend(state); ++ arm_state->videocore_suspended = (status == VCHIQ_SUCCESS) ? 1 : 0; ++ ++ vcos_mutex_unlock(&arm_state->suspend_resume_mutex); ++ ++ vcos_mutex_lock(&arm_state->use_count_mutex); ++ if(!arm_state->suspend_pending) ++ { /* Something has changed the suspend_pending state while we were suspending. ++ Run the HP task to check if we need to resume */ ++ vcos_log_info( "%s trigger HP task to check resume", __func__); ++ vcos_event_signal(&arm_state->hp_evt); ++ } ++ arm_state->suspend_pending = 0; ++ vcos_mutex_unlock(&arm_state->use_count_mutex); ++ } ++ } ++ else ++ { ++ vchiq_check_resume(state); ++ } ++ return status; + } + + +- +-/* Try to get videocore into suspended state, regardless of autosuspend state. +-** We don't actually force suspend, since videocore may get into a bad state +-** if we force suspend at a bad time. Instead, we wait for autosuspend to +-** determine a good point to suspend. If this doesn't happen within 100ms we +-** report failure. +-** +-** Returns VCHIQ_SUCCESS if videocore suspended successfully, VCHIQ_RETRY if +-** videocore failed to suspend in time or VCHIQ_ERROR if interrupted. +-*/ + VCHIQ_STATUS_T +-vchiq_arm_force_suspend(VCHIQ_STATE_T *state) +-{ +- VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state); +- VCHIQ_STATUS_T status = VCHIQ_ERROR; +- long rc = 0; +- int repeat = -1; +- static int autosuspend_override; +- +- if (!arm_state) +- goto out; +- +- vchiq_log_trace(vchiq_susp_log_level, "%s", __func__); +- +- write_lock_bh(&arm_state->susp_res_lock); +- +- status = block_resume(arm_state); +- if (status != VCHIQ_SUCCESS) +- goto unlock; +- if (arm_state->vc_suspend_state == VC_SUSPEND_SUSPENDED) { +- /* Already suspended - just block resume and exit */ +- vchiq_log_info(vchiq_susp_log_level, "%s already " +- "suspended", __func__); +- status = VCHIQ_SUCCESS; +- goto unlock; +- } else if (arm_state->vc_suspend_state <= VC_SUSPEND_IDLE) { +- /* initiate suspend immediately in the case that we're waiting +- * for the timeout */ +- stop_suspend_timer(arm_state); +- if (!vchiq_videocore_wanted(state)) { +- vchiq_log_info(vchiq_susp_log_level, "%s videocore " +- "idle, initiating suspend", __func__); +- status = vchiq_arm_vcsuspend(state); +- } else if (autosuspend_override < FORCE_SUSPEND_FAIL_MAX) { +- vchiq_log_info(vchiq_susp_log_level, "%s letting " +- "videocore go idle", __func__); +- status = VCHIQ_SUCCESS; +- } else { +- vchiq_log_warning(vchiq_susp_log_level, "%s failed too " +- "many times - no more Mr Nice Guy... " +- "initiating suspend", __func__); +- status = vchiq_arm_vcsuspend(state); +- } +- } else { +- vchiq_log_info(vchiq_susp_log_level, "%s videocore suspend " +- "in progress - wait for completion", __func__); +- status = VCHIQ_SUCCESS; +- } +- +- /* Wait for suspend to happen due to system idle (not forced..) */ +- if (status == VCHIQ_SUCCESS) { +- do { +- write_unlock_bh(&arm_state->susp_res_lock); +- +- rc = wait_for_completion_interruptible_timeout( +- &arm_state->vc_suspend_complete, +- msecs_to_jiffies(FORCE_SUSPEND_TIMEOUT_MS)); +- +- write_lock_bh(&arm_state->susp_res_lock); +- if (rc < 0) { +- vchiq_log_warning(vchiq_susp_log_level, "%s " +- "interrupted waiting for suspend", +- __func__); +- status = VCHIQ_ERROR; +- goto unblock_resume; +- } else if (rc == 0) { +- if (arm_state->vc_suspend_state > +- VC_SUSPEND_IDLE) { +- /* Repeat timeout once if in progress */ +- if (repeat < 0) { +- repeat = 1; +- continue; +- } +- } +- autosuspend_override++; +- vchiq_log_warning(vchiq_susp_log_level, +- "%s timed out waiting for vc suspend " +- "(%d)", __func__, autosuspend_override); +- status = VCHIQ_RETRY; +- goto unblock_resume; +- } +- } while (0 < (repeat--)); +- } else +- goto unblock_resume; +- +- /* Check and report state in case we need to abort ARM suspend */ +- if (arm_state->vc_suspend_state != VC_SUSPEND_SUSPENDED) { +- status = VCHIQ_RETRY; +- vchiq_log_error(vchiq_susp_log_level, +- "%s videocore suspend failed (state %s)", __func__, +- suspend_state_names[arm_state->vc_suspend_state + +- VC_SUSPEND_NUM_OFFSET]); +- /* Reset the state only if it's still in an error state. +- * Something could have already initiated another suspend. */ +- if (arm_state->vc_suspend_state < VC_SUSPEND_IDLE) +- set_suspend_state(arm_state, VC_SUSPEND_IDLE); +- +- goto unblock_resume; +- } +- +- /* successfully suspended - reset override counter, unlock and exit */ +- autosuspend_override = 0; +- goto unlock; +- +-unblock_resume: +- /* all error states need to unblock resume before exit */ +- unblock_resume(arm_state); +- +-unlock: +- write_unlock_bh(&arm_state->susp_res_lock); +- +-out: +- vchiq_log_trace(vchiq_susp_log_level, "%s exit %d", __func__, status); +- return status; +-} +- +-void +-vchiq_check_suspend(VCHIQ_STATE_T *state) +-{ +- VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state); +- +- if (!arm_state) +- goto out; +- +- vchiq_log_trace(vchiq_susp_log_level, "%s", __func__); +- +- write_lock_bh(&arm_state->susp_res_lock); +- if (arm_state->vc_suspend_state != VC_SUSPEND_SUSPENDED && +- arm_state->first_connect && +- !vchiq_videocore_wanted(state)) { +- vchiq_arm_vcsuspend(state); +- } +- write_unlock_bh(&arm_state->susp_res_lock); +- +-out: +- vchiq_log_trace(vchiq_susp_log_level, "%s exit", __func__); +- return; +-} +- +- +-int +-vchiq_arm_allow_resume(VCHIQ_STATE_T *state) ++vchiq_arm_vcresume(VCHIQ_STATE_T *state) + { +- VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state); +- int resume = 0; +- int ret = -1; +- +- if (!arm_state) +- goto out; ++ VCHIQ_STATUS_T status = VCHIQ_SUCCESS; ++ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state); ++ vcos_mutex_lock(&arm_state->suspend_resume_mutex); + +- vchiq_log_trace(vchiq_susp_log_level, "%s", __func__); ++ status = vchiq_platform_resume(state); ++ arm_state->videocore_suspended = (status == VCHIQ_RETRY) ? 1 : 0; + +- write_lock_bh(&arm_state->susp_res_lock); +- unblock_resume(arm_state); +- resume = vchiq_check_resume(state); +- write_unlock_bh(&arm_state->susp_res_lock); ++ vcos_mutex_unlock(&arm_state->suspend_resume_mutex); + +- if (resume) { +- wait_for_completion_interruptible( +- &arm_state->vc_resume_complete); +- } +- +- read_lock_bh(&arm_state->susp_res_lock); +- if (arm_state->vc_suspend_state == VC_SUSPEND_SUSPENDED) { +- vchiq_log_info(vchiq_susp_log_level, +- "%s: Videocore remains suspended", __func__); +- } else { +- vchiq_log_info(vchiq_susp_log_level, +- "%s: Videocore resumed", __func__); +- ret = 0; +- } +- read_unlock_bh(&arm_state->susp_res_lock); +-out: +- vchiq_log_trace(vchiq_susp_log_level, "%s exit %d", __func__, ret); +- return ret; ++ return status; + } + +-/* This function should be called with the write lock held */ +-int +-vchiq_check_resume(VCHIQ_STATE_T *state) ++void ++vchiq_check_resume(VCHIQ_STATE_T* state) + { +- VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state); +- int resume = 0; +- +- if (!arm_state) +- goto out; ++ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state); ++ vcos_mutex_lock(&arm_state->use_count_mutex); + +- vchiq_log_trace(vchiq_susp_log_level, "%s", __func__); ++ if (arm_state->videocore_suspended && vchiq_videocore_wanted(state)) ++ { /* signal high priority task to resume vc */ ++ vcos_event_signal(&arm_state->hp_evt); ++ } + +- if (need_resume(state)) { +- set_resume_state(arm_state, VC_RESUME_REQUESTED); +- request_poll(state, NULL, 0); +- resume = 1; +- } +- +-out: +- vchiq_log_trace(vchiq_susp_log_level, "%s exit", __func__); +- return resume; ++ vcos_mutex_unlock(&arm_state->use_count_mutex); + } + + void +-vchiq_platform_check_resume(VCHIQ_STATE_T *state) ++vchiq_check_suspend(VCHIQ_STATE_T* state) + { +- VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state); +- int res = 0; ++ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state); + +- if (!arm_state) +- goto out; ++ vcos_mutex_lock(&arm_state->use_count_mutex); + +- vchiq_log_trace(vchiq_susp_log_level, "%s", __func__); +- +- write_lock_bh(&arm_state->susp_res_lock); +- if (arm_state->wake_address == 0) { +- vchiq_log_info(vchiq_susp_log_level, +- "%s: already awake", __func__); +- goto unlock; +- } +- if (arm_state->vc_resume_state == VC_RESUME_IN_PROGRESS) { +- vchiq_log_info(vchiq_susp_log_level, +- "%s: already resuming", __func__); +- goto unlock; +- } +- +- if (arm_state->vc_resume_state == VC_RESUME_REQUESTED) { +- set_resume_state(arm_state, VC_RESUME_IN_PROGRESS); +- res = 1; +- } else +- vchiq_log_trace(vchiq_susp_log_level, +- "%s: not resuming (resume state %s)", __func__, +- resume_state_names[arm_state->vc_resume_state + +- VC_RESUME_NUM_OFFSET]); +- +-unlock: +- write_unlock_bh(&arm_state->susp_res_lock); +- +- if (res) +- vchiq_platform_resume(state); +- +-out: +- vchiq_log_trace(vchiq_susp_log_level, "%s exit", __func__); +- return; ++ if (!arm_state->videocore_suspended && !vchiq_videocore_wanted(state)) ++ { /* signal low priority task to suspend vc */ ++ vcos_event_signal(&arm_state->lp_evt); ++ } + ++ vcos_mutex_unlock(&arm_state->use_count_mutex); + } + + + +-VCHIQ_STATUS_T +-vchiq_use_internal(VCHIQ_STATE_T *state, VCHIQ_SERVICE_T *service, +- enum USE_TYPE_E use_type) ++static VCHIQ_STATUS_T ++vchiq_use_internal(VCHIQ_STATE_T *state, VCHIQ_SERVICE_T *service, int block_while_resume) + { +- VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state); +- VCHIQ_STATUS_T ret = VCHIQ_SUCCESS; +- char entity[16]; +- int *entity_uc; +- int local_uc, local_entity_uc; +- +- if (!arm_state) +- goto out; +- +- vchiq_log_trace(vchiq_susp_log_level, "%s", __func__); +- +- if (use_type != USE_TYPE_SERVICE) { +- sprintf(entity, "PEER: "); +- entity_uc = &arm_state->peer_use_count; +- } else if (service) { +- sprintf(entity, "%c%c%c%c:%03d", +- VCHIQ_FOURCC_AS_4CHARS(service->base.fourcc), +- service->client_id); +- entity_uc = &service->service_use_count; +- } else { +- vchiq_log_error(vchiq_susp_log_level, "%s null service " +- "ptr", __func__); +- ret = VCHIQ_ERROR; +- goto out; +- } +- +- write_lock_bh(&arm_state->susp_res_lock); +- while (arm_state->resume_blocked) { +- /* If we call 'use' while force suspend is waiting for suspend, +- * then we're about to block the thread which the force is +- * waiting to complete, so we're bound to just time out. In this +- * case, set the suspend state such that the wait will be +- * canceled, so we can complete as quickly as possible. */ +- if (arm_state->resume_blocked && arm_state->vc_suspend_state == +- VC_SUSPEND_IDLE) { +- set_suspend_state(arm_state, VC_SUSPEND_FORCE_CANCELED); +- break; +- } +- /* If suspend is already in progress then we need to block */ +- if (!try_wait_for_completion(&arm_state->resume_blocker)) { +- /* Indicate that there are threads waiting on the resume +- * blocker. These need to be allowed to complete before +- * a _second_ call to force suspend can complete, +- * otherwise low priority threads might never actually +- * continue */ +- arm_state->blocked_count++; +- write_unlock_bh(&arm_state->susp_res_lock); +- vchiq_log_info(vchiq_susp_log_level, "%s %s resume " +- "blocked - waiting...", __func__, entity); +- if (wait_for_completion_killable( +- &arm_state->resume_blocker) != 0) { +- vchiq_log_error(vchiq_susp_log_level, "%s %s " +- "wait for resume blocker interrupted", +- __func__, entity); +- ret = VCHIQ_ERROR; +- write_lock_bh(&arm_state->susp_res_lock); +- arm_state->blocked_count--; +- write_unlock_bh(&arm_state->susp_res_lock); +- goto out; +- } +- vchiq_log_info(vchiq_susp_log_level, "%s %s resume " +- "unblocked", __func__, entity); +- write_lock_bh(&arm_state->susp_res_lock); +- if (--arm_state->blocked_count == 0) +- complete_all(&arm_state->blocked_blocker); +- } +- } +- +- stop_suspend_timer(arm_state); +- write_unlock_bh(&arm_state->susp_res_lock); +- +- mutex_lock(&arm_state->vc_use_cnt_mutex); +- if (!arm_state->videocore_use_count) +- pm_qos_add_request(&arm_state->qos_request, +- PM_QOS_CPU_DMA_LATENCY, 100); +- +- local_uc = ++arm_state->videocore_use_count; +- local_entity_uc = ++(*entity_uc); +- mutex_unlock(&arm_state->vc_use_cnt_mutex); +- +- write_lock_bh(&arm_state->susp_res_lock); +- +- /* If there's a pending request which hasn't yet been serviced then +- * just clear it. If we're past VC_SUSPEND_REQUESTED state then +- * vc_resume_complete will block until we either resume or fail to +- * suspend */ +- if (arm_state->vc_suspend_state <= VC_SUSPEND_REQUESTED) +- set_suspend_state(arm_state, VC_SUSPEND_IDLE); +- +- if (need_resume(state)) { +- set_resume_state(arm_state, VC_RESUME_REQUESTED); +- vchiq_log_info(vchiq_susp_log_level, +- "%s %s count %d, state count %d", +- __func__, entity, local_entity_uc, local_uc); +- request_poll(state, NULL, 0); +- } else +- vchiq_log_trace(vchiq_susp_log_level, +- "%s %s count %d, state count %d", +- __func__, entity, *entity_uc, local_uc); +- +- +- write_unlock_bh(&arm_state->susp_res_lock); +- +- /* Completion is in a done state when we're not suspended, so this won't +- * block for the non-suspended case. */ +- if (!try_wait_for_completion(&arm_state->vc_resume_complete)) { +- vchiq_log_info(vchiq_susp_log_level, "%s %s wait for resume", +- __func__, entity); +- if (wait_for_completion_killable( +- &arm_state->vc_resume_complete) != 0) { +- vchiq_log_error(vchiq_susp_log_level, "%s %s wait for " +- "resume interrupted", __func__, entity); +- ret = VCHIQ_ERROR; +- goto out; +- } +- vchiq_log_info(vchiq_susp_log_level, "%s %s resumed", __func__, +- entity); +- } +- +- if (ret == VCHIQ_SUCCESS) { +- VCHIQ_STATUS_T status = VCHIQ_SUCCESS; +- long ack_cnt = atomic_xchg(&arm_state->ka_use_ack_count, 0); +- while (ack_cnt && (status == VCHIQ_SUCCESS)) { +- /* Send the use notify to videocore */ +- status = vchiq_send_remote_use_active(state); +- if (status == VCHIQ_SUCCESS) +- ack_cnt--; +- else +- atomic_add(ack_cnt, +- &arm_state->ka_use_ack_count); +- } +- } +- +-out: +- vchiq_log_trace(vchiq_susp_log_level, "%s exit %d", __func__, ret); +- return ret; ++ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state); ++ VCHIQ_STATUS_T ret = VCHIQ_SUCCESS; ++ char entity[10]; ++ int* entity_uc; ++ ++ if(arm_state) ++ { ++ vcos_mutex_lock(&arm_state->use_count_mutex); ++ ++ if (service) ++ { ++ sprintf(entity, "%c%c%c%c:%03d",VCHIQ_FOURCC_AS_4CHARS(service->base.fourcc), service->client_id); ++ entity_uc = &service->service_use_count; ++ } ++ else ++ { ++ sprintf(entity, "PEER: "); ++ entity_uc = &arm_state->peer_use_count; ++ } ++ ++ if (!arm_state->videocore_suspended && !vchiq_videocore_wanted(state)) ++ { ++#if VCOS_HAVE_TIMER ++ if (vchiq_platform_use_suspend_timer()) ++ { ++ vcos_log_trace( "%s %s - cancel suspend timer", __func__, entity); ++ } ++ vcos_timer_cancel(&g_suspend_timer); ++#endif ++ } ++ ++ arm_state->videocore_use_count++; ++ (*entity_uc)++; ++ arm_state->suspend_pending = 0; ++ ++ if (arm_state->videocore_suspended && vchiq_videocore_wanted(state)) ++ { ++ vcos_log_info( "%s %s count %d, state count %d", __func__, entity, *entity_uc, arm_state->videocore_use_count); ++ if(block_while_resume) ++ { ++ ret = vchiq_arm_vcresume(state); ++ } ++ else ++ { ++ vcos_log_info( "%s trigger HP task to do resume", __func__); /* triggering is done below */ ++ } ++ } ++ else ++ { ++ vcos_log_trace( "%s %s count %d, state count %d", __func__, entity, *entity_uc, arm_state->videocore_use_count); ++ } ++ if(!block_while_resume) ++ { ++ arm_state->use_notify_pending++; ++ vcos_event_signal(&arm_state->hp_evt); /* hp task will check if we need to resume and also send use notify */ ++ } ++ ++ if (ret == VCHIQ_RETRY) ++ { /* if we're told to retry, decrement the counters. VCHIQ_ERROR probably means we're already resumed. */ ++ (*entity_uc)--; ++ arm_state->videocore_use_count--; ++ } ++ ++ vcos_mutex_unlock(&arm_state->use_count_mutex); ++ } ++ return ret; + } + +-VCHIQ_STATUS_T ++static VCHIQ_STATUS_T + vchiq_release_internal(VCHIQ_STATE_T *state, VCHIQ_SERVICE_T *service) + { +- VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state); +- VCHIQ_STATUS_T ret = VCHIQ_SUCCESS; +- char entity[16]; +- int *entity_uc; +- int local_uc, local_entity_uc; +- +- if (!arm_state) +- goto out; +- +- vchiq_log_trace(vchiq_susp_log_level, "%s", __func__); +- +- if (service) { +- sprintf(entity, "%c%c%c%c:%03d", +- VCHIQ_FOURCC_AS_4CHARS(service->base.fourcc), +- service->client_id); +- entity_uc = &service->service_use_count; +- } else { +- sprintf(entity, "PEER: "); +- entity_uc = &arm_state->peer_use_count; +- } +- +- write_lock_bh(&arm_state->susp_res_lock); +- if (!arm_state->videocore_use_count || !(*entity_uc)) { +- /* Don't use BUG_ON - don't allow user thread to crash kernel */ +- WARN_ON(!arm_state->videocore_use_count); +- WARN_ON(!(*entity_uc)); +- ret = VCHIQ_ERROR; +- goto unlock; +- } +- write_unlock_bh(&arm_state->susp_res_lock); +- +- mutex_lock(&arm_state->vc_use_cnt_mutex); +- local_uc = --arm_state->videocore_use_count; +- local_entity_uc = --(*entity_uc); +- +- if (!arm_state->videocore_use_count) +- pm_qos_remove_request(&arm_state->qos_request); +- mutex_unlock(&arm_state->vc_use_cnt_mutex); +- +- write_lock_bh(&arm_state->susp_res_lock); +- if (!vchiq_videocore_wanted(state)) { +- if (vchiq_platform_use_suspend_timer() && +- !arm_state->resume_blocked) { +- /* Only use the timer if we're not trying to force +- * suspend (=> resume_blocked) */ +- start_suspend_timer(arm_state); +- } else { +- vchiq_log_info(vchiq_susp_log_level, +- "%s %s count %d, state count %d - suspending", +- __func__, entity, *entity_uc, +- arm_state->videocore_use_count); +- vchiq_arm_vcsuspend(state); +- } +- } else +- vchiq_log_trace(vchiq_susp_log_level, +- "%s %s count %d, state count %d", +- __func__, entity, *entity_uc, +- arm_state->videocore_use_count); +- +-unlock: +- write_unlock_bh(&arm_state->susp_res_lock); +- +-out: +- vchiq_log_trace(vchiq_susp_log_level, "%s exit %d", __func__, ret); +- return ret; ++ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state); ++ VCHIQ_STATUS_T ret = VCHIQ_SUCCESS; ++ char entity[10]; ++ int* entity_uc; ++ ++ if(arm_state) ++ { ++ vcos_mutex_lock(&arm_state->use_count_mutex); ++ ++ if (service) ++ { ++ sprintf(entity, "%c%c%c%c:%03d",VCHIQ_FOURCC_AS_4CHARS(service->base.fourcc), service->client_id); ++ entity_uc = &service->service_use_count; ++ } ++ else ++ { ++ sprintf(entity, "PEER: "); ++ entity_uc = &arm_state->peer_use_count; ++ } ++ ++ if (*entity_uc && arm_state->videocore_use_count) ++ { ++ arm_state->videocore_use_count--; ++ (*entity_uc)--; ++ ++ if (!vchiq_videocore_wanted(state)) ++ { ++#if VCOS_HAVE_TIMER ++ if (vchiq_platform_use_suspend_timer()) ++ { ++ vcos_log_trace( "%s %s count %d, state count %d - starting suspend timer", __func__, entity, *entity_uc, arm_state->videocore_use_count); ++ vcos_timer_cancel(&g_suspend_timer); ++ vcos_timer_set(&g_suspend_timer, SUSPEND_TIMER_TIMEOUT_MS); ++ } ++ else ++#endif ++ { ++ vcos_log_info( "%s %s count %d, state count %d - suspend pending", __func__, entity, *entity_uc, arm_state->videocore_use_count); ++ vcos_event_signal(&arm_state->lp_evt); /* kick the lp thread to do the suspend */ ++ } ++ } ++ else ++ { ++ vcos_log_trace( "%s %s count %d, state count %d", __func__, entity, *entity_uc, arm_state->videocore_use_count); ++ } ++ } ++ else ++ { ++ vcos_log_error( "%s %s ERROR releasing service; count %d, state count %d", __func__, entity, *entity_uc, arm_state->videocore_use_count); ++ ret = VCHIQ_ERROR; ++ } ++ ++ vcos_mutex_unlock(&arm_state->use_count_mutex); ++ } ++ return ret; + } + +-void ++VCHIQ_STATUS_T + vchiq_on_remote_use(VCHIQ_STATE_T *state) + { +- VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state); +- vchiq_log_trace(vchiq_susp_log_level, "%s", __func__); +- atomic_inc(&arm_state->ka_use_count); +- complete(&arm_state->ka_evt); ++ vcos_log_info("%s state %p", __func__, state); ++ return state ? vchiq_use_internal(state, NULL, 0) : VCHIQ_ERROR; + } + +-void ++VCHIQ_STATUS_T + vchiq_on_remote_release(VCHIQ_STATE_T *state) + { +- VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state); +- vchiq_log_trace(vchiq_susp_log_level, "%s", __func__); +- atomic_inc(&arm_state->ka_release_count); +- complete(&arm_state->ka_evt); ++ vcos_log_info("%s state %p", __func__, state); ++ return state ? vchiq_release_internal(state, NULL) : VCHIQ_ERROR; + } + + VCHIQ_STATUS_T + vchiq_use_service_internal(VCHIQ_SERVICE_T *service) + { +- return vchiq_use_internal(service->state, service, USE_TYPE_SERVICE); ++ VCHIQ_STATE_T* state = NULL; ++ ++ if (service) ++ { ++ state = service->state; ++ } ++ ++ if (!service || !state) ++ { ++ return VCHIQ_ERROR; ++ } ++ return vchiq_use_internal(state, service, 1); + } + + VCHIQ_STATUS_T + vchiq_release_service_internal(VCHIQ_SERVICE_T *service) + { +- return vchiq_release_internal(service->state, service); ++ VCHIQ_STATE_T* state = NULL; ++ ++ if (service) ++ { ++ state = service->state; ++ } ++ ++ if (!service || !state) ++ { ++ return VCHIQ_ERROR; ++ } ++ return vchiq_release_internal(state, service); + } + +-static void suspend_timer_callback(unsigned long context) ++ ++#if VCOS_HAVE_TIMER ++static void suspend_timer_callback(void* context) + { +- VCHIQ_STATE_T *state = (VCHIQ_STATE_T *)context; +- VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state); +- if (!arm_state) +- goto out; +- vchiq_log_info(vchiq_susp_log_level, +- "%s - suspend timer expired - check suspend", __func__); +- vchiq_check_suspend(state); +-out: +- return; ++ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state((VCHIQ_STATE_T*)context); ++ vcos_log_info( "%s - suspend pending", __func__); ++ vcos_event_signal(&arm_state->lp_evt); + } ++#endif + + VCHIQ_STATUS_T + vchiq_use_service(VCHIQ_SERVICE_HANDLE_T handle) + { +- VCHIQ_STATUS_T ret = VCHIQ_ERROR; +- VCHIQ_SERVICE_T *service = find_service_by_handle(handle); +- if (service) { +- ret = vchiq_use_internal(service->state, service, +- USE_TYPE_SERVICE); +- unlock_service(service); +- } +- return ret; ++ VCHIQ_STATUS_T ret = VCHIQ_ERROR; ++ VCHIQ_SERVICE_T *service = (VCHIQ_SERVICE_T *) handle; ++ if (service) ++ { ++ ret = vchiq_use_service_internal(service); ++ } ++ return ret; + } + + VCHIQ_STATUS_T + vchiq_release_service(VCHIQ_SERVICE_HANDLE_T handle) + { +- VCHIQ_STATUS_T ret = VCHIQ_ERROR; +- VCHIQ_SERVICE_T *service = find_service_by_handle(handle); +- if (service) { +- ret = vchiq_release_internal(service->state, service); +- unlock_service(service); +- } +- return ret; ++ VCHIQ_STATUS_T ret = VCHIQ_ERROR; ++ VCHIQ_SERVICE_T *service = (VCHIQ_SERVICE_T *) handle; ++ if (service) ++ { ++ ret = vchiq_release_service_internal(service); ++ } ++ return ret; + } + + void + vchiq_dump_service_use_state(VCHIQ_STATE_T *state) + { +- VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state); +- int i, j = 0; +- /* Only dump 64 services */ +- static const int local_max_services = 64; +- /* If there's more than 64 services, only dump ones with +- * non-zero counts */ +- int only_nonzero = 0; +- static const char *nz = "<-- preventing suspend"; +- +- enum vc_suspend_status vc_suspend_state; +- enum vc_resume_status vc_resume_state; +- int peer_count; +- int vc_use_count; +- int active_services; +- struct service_data_struct { +- int fourcc; +- int clientid; +- int use_count; +- } service_data[local_max_services]; +- +- if (!arm_state) +- return; +- +- read_lock_bh(&arm_state->susp_res_lock); +- vc_suspend_state = arm_state->vc_suspend_state; +- vc_resume_state = arm_state->vc_resume_state; +- peer_count = arm_state->peer_use_count; +- vc_use_count = arm_state->videocore_use_count; +- active_services = state->unused_service; +- if (active_services > local_max_services) +- only_nonzero = 1; +- +- for (i = 0; (i < active_services) && (j < local_max_services); i++) { +- VCHIQ_SERVICE_T *service_ptr = state->services[i]; +- if (!service_ptr) +- continue; +- +- if (only_nonzero && !service_ptr->service_use_count) +- continue; +- +- if (service_ptr->srvstate != VCHIQ_SRVSTATE_FREE) { +- service_data[j].fourcc = service_ptr->base.fourcc; +- service_data[j].clientid = service_ptr->client_id; +- service_data[j++].use_count = service_ptr-> +- service_use_count; +- } +- } +- +- read_unlock_bh(&arm_state->susp_res_lock); +- +- vchiq_log_warning(vchiq_susp_log_level, +- "-- Videcore suspend state: %s --", +- suspend_state_names[vc_suspend_state + VC_SUSPEND_NUM_OFFSET]); +- vchiq_log_warning(vchiq_susp_log_level, +- "-- Videcore resume state: %s --", +- resume_state_names[vc_resume_state + VC_RESUME_NUM_OFFSET]); +- +- if (only_nonzero) +- vchiq_log_warning(vchiq_susp_log_level, "Too many active " +- "services (%d). Only dumping up to first %d services " +- "with non-zero use-count", active_services, +- local_max_services); +- +- for (i = 0; i < j; i++) { +- vchiq_log_error(vchiq_arm_log_level, +- "----- %c%c%c%c:%d service count %d %s", +- VCHIQ_FOURCC_AS_4CHARS(service_data[i].fourcc), +- service_data[i].clientid, +- service_data[i].use_count, +- service_data[i].use_count ? nz : ""); +- } +- vchiq_log_warning(vchiq_susp_log_level, +- "----- PEER use count count %d", peer_count); +- vchiq_log_warning(vchiq_susp_log_level, +- "--- Overall vchiq instance use count %d", vc_use_count); ++ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state); ++ int i; ++ if(arm_state) ++ { ++ vcos_mutex_lock(&arm_state->suspend_resume_mutex); ++ if (arm_state->videocore_suspended) ++ { ++ vcos_log_warn("--VIDEOCORE SUSPENDED--"); ++ } ++ else ++ { ++ vcos_log_warn("--VIDEOCORE AWAKE--"); ++ } ++ for (i = 0; i < state->unused_service; i++) { ++ VCHIQ_SERVICE_T *service_ptr = state->services[i]; ++ if (service_ptr && (service_ptr->srvstate != VCHIQ_SRVSTATE_FREE)) ++ { ++ if (service_ptr->service_use_count) ++ vcos_log_error("----- %c%c%c%c:%d service count %d <-- preventing suspend", VCHIQ_FOURCC_AS_4CHARS(service_ptr->base.fourcc), service_ptr->client_id, service_ptr->service_use_count); ++ else ++ vcos_log_warn("----- %c%c%c%c:%d service count 0", VCHIQ_FOURCC_AS_4CHARS(service_ptr->base.fourcc), service_ptr->client_id); ++ } ++ } ++ vcos_log_warn("----- PEER use count count %d", arm_state->peer_use_count); ++ vcos_log_warn("--- Overall vchiq instance use count %d", arm_state->videocore_use_count); ++ ++ vchiq_dump_platform_use_state(state); + +- vchiq_dump_platform_use_state(state); ++ vcos_mutex_unlock(&arm_state->suspend_resume_mutex); ++ } + } + + VCHIQ_STATUS_T +-vchiq_check_service(VCHIQ_SERVICE_T *service) ++vchiq_check_service(VCHIQ_SERVICE_T * service) + { +- VCHIQ_ARM_STATE_T *arm_state = +- vchiq_platform_get_arm_state(service->state); +- VCHIQ_STATUS_T ret = VCHIQ_ERROR; +- +- if (!arm_state || !service) +- goto out; +- +- vchiq_log_trace(vchiq_susp_log_level, "%s", __func__); +- +- read_lock_bh(&arm_state->susp_res_lock); +- if (service->service_use_count) +- ret = VCHIQ_SUCCESS; +- read_unlock_bh(&arm_state->susp_res_lock); +- +- if (ret == VCHIQ_ERROR) { +- vchiq_log_error(vchiq_susp_log_level, +- "%s ERROR - %c%c%c%c:%d service count %d, " +- "state count %d, videocore suspend state %s", __func__, +- VCHIQ_FOURCC_AS_4CHARS(service->base.fourcc), +- service->client_id, service->service_use_count, +- arm_state->videocore_use_count, +- suspend_state_names[arm_state->vc_suspend_state + +- VC_SUSPEND_NUM_OFFSET]); +- vchiq_dump_service_use_state(service->state); +- } +-out: +- return ret; ++ VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(service->state); ++ VCHIQ_STATUS_T ret = VCHIQ_ERROR; ++ /* on 2835 vchiq does not have an arm_state */ ++ if (!arm_state) ++ return VCHIQ_SUCCESS; ++ if (service && arm_state) ++ { ++ vcos_mutex_lock(&arm_state->use_count_mutex); ++ if (!service->service_use_count) ++ { ++ vcos_log_error( "%s ERROR - %c%c%c%c:%d service count %d, state count %d, videocore_suspended %d", __func__,VCHIQ_FOURCC_AS_4CHARS(service->base.fourcc), service->client_id, service->service_use_count, arm_state->videocore_use_count, arm_state->videocore_suspended); ++ vchiq_dump_service_use_state(service->state); ++ vcos_assert(0); // vcos_assert should kill the calling thread, so a user thread shouldn't be able to kill the kernel. ++ } ++ else ++ { ++ ret = VCHIQ_SUCCESS; ++ } ++ vcos_mutex_unlock(&arm_state->use_count_mutex); ++ } ++ return ret; + } + + /* stub functions */ + void vchiq_on_remote_use_active(VCHIQ_STATE_T *state) + { +- (void)state; ++ vcos_unused(state); + } + +-void vchiq_platform_conn_state_changed(VCHIQ_STATE_T *state, +- VCHIQ_CONNSTATE_T oldstate, VCHIQ_CONNSTATE_T newstate) ++void vchiq_platform_conn_state_changed(VCHIQ_STATE_T *state, VCHIQ_CONNSTATE_T oldstate, VCHIQ_CONNSTATE_T newstate) + { +- VCHIQ_ARM_STATE_T *arm_state = vchiq_platform_get_arm_state(state); +- vchiq_log_info(vchiq_susp_log_level, "%d: %s->%s", state->id, +- get_conn_state_name(oldstate), get_conn_state_name(newstate)); +- if (state->conn_state == VCHIQ_CONNSTATE_CONNECTED) { +- write_lock_bh(&arm_state->susp_res_lock); +- if (!arm_state->first_connect) { +- arm_state->first_connect = 1; +- write_unlock_bh(&arm_state->susp_res_lock); +- wake_up_process(arm_state->ka_thread); +- } else +- write_unlock_bh(&arm_state->susp_res_lock); +- } ++ vcos_unused(state); ++ vcos_unused(oldstate); ++ vcos_unused(oldstate); + } + + +@@ -2592,132 +1828,67 @@ + static int __init + vchiq_init(void) + { +- int err; +- void *ptr_err; ++ int err; ++ void *ptr_err; + +- /* create proc entries */ +- err = vchiq_proc_init(); +- if (err != 0) +- goto failed_proc_init; +- +- err = alloc_chrdev_region(&vchiq_devid, VCHIQ_MINOR, 1, DEVICE_NAME); +- if (err != 0) { +- vchiq_log_error(vchiq_arm_log_level, +- "Unable to allocate device number"); +- goto failed_alloc_chrdev; +- } +- cdev_init(&vchiq_cdev, &vchiq_fops); +- vchiq_cdev.owner = THIS_MODULE; +- err = cdev_add(&vchiq_cdev, vchiq_devid, 1); +- if (err != 0) { +- vchiq_log_error(vchiq_arm_log_level, +- "Unable to register device"); +- goto failed_cdev_add; +- } +- +- /* create sysfs entries */ +- vchiq_class = class_create(THIS_MODULE, DEVICE_NAME); +- ptr_err = vchiq_class; +- if (IS_ERR(ptr_err)) +- goto failed_class_create; +- +- vchiq_dev = device_create(vchiq_class, NULL, +- vchiq_devid, NULL, "vchiq"); +- ptr_err = vchiq_dev; +- if (IS_ERR(ptr_err)) +- goto failed_device_create; +- +- err = vchiq_platform_init(&g_state); +- if (err != 0) +- goto failed_platform_init; +- +- vchiq_log_info(vchiq_arm_log_level, +- "vchiq: initialised - version %d (min %d), device %d.%d", +- VCHIQ_VERSION, VCHIQ_VERSION_MIN, +- MAJOR(vchiq_devid), MINOR(vchiq_devid)); ++ err = vchiq_platform_vcos_init(); ++ if (err != 0) ++ goto failed_platform_vcos_init; ++ ++ vcos_log_set_level(VCOS_LOG_CATEGORY, vchiq_default_arm_log_level); ++ vcos_log_register("vchiq_arm", VCOS_LOG_CATEGORY); ++ ++ if ((err = ++ alloc_chrdev_region(&vchiq_devid, VCHIQ_MINOR, 1, ++ DEVICE_NAME)) != 0) { ++ vcos_log_error("Unable to allocate device number"); ++ goto failed_alloc_chrdev; ++ } ++ cdev_init(&vchiq_cdev, &vchiq_fops); ++ vchiq_cdev.owner = THIS_MODULE; ++ if ((err = cdev_add(&vchiq_cdev, vchiq_devid, 1)) != 0) { ++ vcos_log_error("Unable to register device"); ++ goto failed_cdev_add; ++ } ++ ++ /* create sysfs entries */ ++ vchiq_class = class_create(THIS_MODULE, DEVICE_NAME); ++ if (IS_ERR(ptr_err = vchiq_class)) ++ goto failed_class_create; ++ ++ vchiq_dev = device_create(vchiq_class, NULL, ++ vchiq_devid, NULL, "vchiq"); ++ if (IS_ERR(ptr_err = vchiq_dev)) ++ goto failed_device_create; ++ ++ err = vchiq_platform_init(&g_state); ++ if (err != 0) ++ goto failed_platform_init; ++ ++#if VCOS_HAVE_TIMER ++ vcos_timer_create( &g_suspend_timer, "suspend_timer", suspend_timer_callback, (void*)(&g_state)); ++#endif ++ ++ vcos_log_error("vchiq: initialised - version %d (min %d), device %d.%d", ++ VCHIQ_VERSION, VCHIQ_VERSION_MIN, ++ MAJOR(vchiq_devid), MINOR(vchiq_devid)); + +- return 0; ++ return 0; + + failed_platform_init: +- device_destroy(vchiq_class, vchiq_devid); ++ device_destroy(vchiq_class, vchiq_devid); + failed_device_create: +- class_destroy(vchiq_class); ++ class_destroy(vchiq_class); + failed_class_create: +- cdev_del(&vchiq_cdev); +- err = PTR_ERR(ptr_err); ++ cdev_del(&vchiq_cdev); ++ err = PTR_ERR(ptr_err); + failed_cdev_add: +- unregister_chrdev_region(vchiq_devid, 1); ++ unregister_chrdev_region(vchiq_devid, 1); + failed_alloc_chrdev: +- vchiq_proc_deinit(); +-failed_proc_init: +- vchiq_log_warning(vchiq_arm_log_level, "could not load vchiq"); +- return err; ++failed_platform_vcos_init: ++ printk(KERN_WARNING "could not load vchiq\n"); ++ return err; + } +- +-static int vchiq_instance_get_use_count(VCHIQ_INSTANCE_T instance) +-{ +- VCHIQ_SERVICE_T *service; +- int use_count = 0, i; +- i = 0; +- while ((service = next_service_by_instance(instance->state, +- instance, &i)) != NULL) { +- use_count += service->service_use_count; +- unlock_service(service); +- } +- return use_count; +-} +- +-/* read the per-process use-count */ +-static int proc_read_use_count(char *page, char **start, +- off_t off, int count, +- int *eof, void *data) +-{ +- VCHIQ_INSTANCE_T instance = data; +- int len, use_count; +- +- use_count = vchiq_instance_get_use_count(instance); +- len = snprintf(page+off, count, "%d\n", use_count); +- +- return len; +-} +- +-/* add an instance (process) to the proc entries */ +-static int vchiq_proc_add_instance(VCHIQ_INSTANCE_T instance) +-{ +- char pidstr[32]; +- struct proc_dir_entry *top, *use_count; +- struct proc_dir_entry *clients = vchiq_clients_top(); +- int pid = instance->pid; +- +- snprintf(pidstr, sizeof(pidstr), "%d", pid); +- top = proc_mkdir(pidstr, clients); +- if (!top) +- goto fail_top; +- +- use_count = create_proc_read_entry("use_count", +- 0444, top, +- proc_read_use_count, +- instance); +- if (!use_count) +- goto fail_use_count; +- +- instance->proc_entry = top; +- +- return 0; +- +-fail_use_count: +- remove_proc_entry(top->name, clients); +-fail_top: +- return -ENOMEM; +-} +- +-static void vchiq_proc_remove_instance(VCHIQ_INSTANCE_T instance) +-{ +- struct proc_dir_entry *clients = vchiq_clients_top(); +- remove_proc_entry("use_count", instance->proc_entry); +- remove_proc_entry(instance->proc_entry->name, clients); +-} +- + /**************************************************************************** + * + * vchiq_exit - called when the module is unloaded. +@@ -2727,11 +1898,12 @@ + static void __exit + vchiq_exit(void) + { +- vchiq_platform_exit(&g_state); +- device_destroy(vchiq_class, vchiq_devid); +- class_destroy(vchiq_class); +- cdev_del(&vchiq_cdev); +- unregister_chrdev_region(vchiq_devid, 1); ++ vchiq_platform_exit(&g_state); ++ device_destroy(vchiq_class, vchiq_devid); ++ class_destroy(vchiq_class); ++ cdev_del(&vchiq_cdev); ++ unregister_chrdev_region(vchiq_devid, 1); ++ vcos_log_unregister(VCOS_LOG_CATEGORY); + } + + module_init(vchiq_init); +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_arm.h +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_arm.h 2013-07-26 19:36:51.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_arm.h 2013-07-26 19:37:11.000000000 +0000 +@@ -19,101 +19,46 @@ + #ifndef VCHIQ_ARM_H + #define VCHIQ_ARM_H + +-#include +-#include +-//#include +-#define pm_qos_add_request(a,b,c) do {} while (0) +-#define pm_qos_remove_request(a) do {} while (0) +-struct pm_qos_request_list {int dummy;}; +-#include + #include "vchiq_core.h" + + +-enum vc_suspend_status { +- VC_SUSPEND_FORCE_CANCELED = -3, /* Force suspend canceled, too busy */ +- VC_SUSPEND_REJECTED = -2, /* Videocore rejected suspend request */ +- VC_SUSPEND_FAILED = -1, /* Videocore suspend failed */ +- VC_SUSPEND_IDLE = 0, /* VC active, no suspend actions */ +- VC_SUSPEND_REQUESTED, /* User has requested suspend */ +- VC_SUSPEND_IN_PROGRESS, /* Slot handler has recvd suspend request */ +- VC_SUSPEND_SUSPENDED /* Videocore suspend succeeded */ +-}; +- +-enum vc_resume_status { +- VC_RESUME_FAILED = -1, /* Videocore resume failed */ +- VC_RESUME_IDLE = 0, /* VC suspended, no resume actions */ +- VC_RESUME_REQUESTED, /* User has requested resume */ +- VC_RESUME_IN_PROGRESS, /* Slot handler has received resume request */ +- VC_RESUME_RESUMED /* Videocore resumed successfully (active) */ +-}; +- +- +-enum USE_TYPE_E { +- USE_TYPE_SERVICE, +- USE_TYPE_PEER, +- USE_TYPE_VCHIQ +-}; ++typedef struct vchiq_arm_state_struct { + ++ VCOS_THREAD_T lp_thread; /* processes low priority messages (eg suspend) */ ++ VCOS_THREAD_T hp_thread; /* processes high priority messages (eg resume) */ + +-typedef struct vchiq_arm_state_struct { +- /* Keepalive-related data */ +- struct task_struct *ka_thread; +- struct completion ka_evt; +- atomic_t ka_use_count; +- atomic_t ka_use_ack_count; +- atomic_t ka_release_count; +- +- struct completion vc_suspend_complete; +- struct completion vc_resume_complete; +- +- rwlock_t susp_res_lock; +- enum vc_suspend_status vc_suspend_state; +- enum vc_resume_status vc_resume_state; +- +- struct mutex vc_use_cnt_mutex; +- unsigned int wake_address; +- +- struct timer_list suspend_timer; +- int suspend_timer_timeout; +- int suspend_timer_running; +- +- /* Global use count for videocore. +- ** This is equal to the sum of the use counts for all services. When +- ** this hits zero the videocore suspend procedure will be initiated. +- */ +- int videocore_use_count; +- +- /* Use count to track requests from videocore peer. +- ** This use count is not associated with a service, so needs to be +- ** tracked separately with the state. +- */ +- int peer_use_count; +- +- /* Flag to indicate whether resume is blocked. This happens when the +- ** ARM is suspending +- */ +- struct completion resume_blocker; +- int resume_blocked; +- struct completion blocked_blocker; +- int blocked_count; +- +- /* Flag to indicate that the first vchiq connect has made it through. +- ** This means that both sides should be fully ready, and we should +- ** be able to suspend after this point. +- */ +- int first_connect; +- +- struct pm_qos_request_list qos_request; +- +- unsigned long long suspend_start_time; +- unsigned long long sleep_start_time; +- unsigned long long resume_start_time; +- unsigned long long last_wake_time; ++ VCOS_EVENT_T lp_evt; ++ VCOS_EVENT_T hp_evt; ++ ++ VCOS_MUTEX_T use_count_mutex; ++ VCOS_MUTEX_T suspend_resume_mutex; + ++ int suspend_pending; ++ ++ /* Global use count for videocore. ++ * This is equal to the sum of the use counts for all services. When this hits ++ * zero the videocore suspend procedure will be initiated. */ ++ int videocore_use_count; ++ ++ /* Use count to track requests from videocore peer. ++ * This use count is not associated with a service, so needs to be tracked separately ++ * with the state. ++ */ ++ int peer_use_count; ++ ++ /* Flag to indicate whether videocore is currently suspended */ ++ int videocore_suspended; ++ ++ /* Flag to indicate whether a notification is pending back to videocore that it's ++ * "remote use request" has been actioned */ ++ int use_notify_pending; + } VCHIQ_ARM_STATE_T; + +-extern int vchiq_arm_log_level; +-extern int vchiq_susp_log_level; ++ ++extern VCOS_LOG_CAT_T vchiq_arm_log_category; ++ ++extern int __init ++vchiq_platform_vcos_init(void); + + extern int __init + vchiq_platform_init(VCHIQ_STATE_T *state); +@@ -128,22 +73,16 @@ + vchiq_arm_vcsuspend(VCHIQ_STATE_T *state); + + extern VCHIQ_STATUS_T +-vchiq_arm_force_suspend(VCHIQ_STATE_T *state); +- +-extern int +-vchiq_arm_allow_resume(VCHIQ_STATE_T *state); +- +-extern VCHIQ_STATUS_T + vchiq_arm_vcresume(VCHIQ_STATE_T *state); + + extern VCHIQ_STATUS_T + vchiq_arm_init_state(VCHIQ_STATE_T *state, VCHIQ_ARM_STATE_T *arm_state); + +-extern int +-vchiq_check_resume(VCHIQ_STATE_T *state); ++extern void ++vchiq_check_resume(VCHIQ_STATE_T* state); + + extern void +-vchiq_check_suspend(VCHIQ_STATE_T *state); ++vchiq_check_suspend(VCHIQ_STATE_T* state); + + extern VCHIQ_STATUS_T + vchiq_use_service(VCHIQ_SERVICE_HANDLE_T handle); +@@ -152,13 +91,16 @@ + vchiq_release_service(VCHIQ_SERVICE_HANDLE_T handle); + + extern VCHIQ_STATUS_T +-vchiq_check_service(VCHIQ_SERVICE_T *service); ++vchiq_check_service(VCHIQ_SERVICE_T * service); + + extern VCHIQ_STATUS_T + vchiq_platform_suspend(VCHIQ_STATE_T *state); + ++extern VCHIQ_STATUS_T ++vchiq_platform_resume(VCHIQ_STATE_T *state); ++ + extern int +-vchiq_platform_videocore_wanted(VCHIQ_STATE_T *state); ++vchiq_platform_videocore_wanted(VCHIQ_STATE_T* state); + + extern int + vchiq_platform_use_suspend_timer(void); +@@ -172,30 +114,5 @@ + extern VCHIQ_ARM_STATE_T* + vchiq_platform_get_arm_state(VCHIQ_STATE_T *state); + +-extern int +-vchiq_videocore_wanted(VCHIQ_STATE_T *state); +- +-extern VCHIQ_STATUS_T +-vchiq_use_internal(VCHIQ_STATE_T *state, VCHIQ_SERVICE_T *service, +- enum USE_TYPE_E use_type); +-extern VCHIQ_STATUS_T +-vchiq_release_internal(VCHIQ_STATE_T *state, VCHIQ_SERVICE_T *service); +- +-void +-set_suspend_state(VCHIQ_ARM_STATE_T *arm_state, +- enum vc_suspend_status new_state); +- +-void +-set_resume_state(VCHIQ_ARM_STATE_T *arm_state, +- enum vc_resume_status new_state); +- +-void +-start_suspend_timer(VCHIQ_ARM_STATE_T *arm_state); +- +-extern int vchiq_proc_init(void); +-extern void vchiq_proc_deinit(void); +-extern struct proc_dir_entry *vchiq_proc_top(void); +-extern struct proc_dir_entry *vchiq_clients_top(void); +- + + #endif /* VCHIQ_ARM_H */ +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_cfg.h +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_cfg.h 2013-07-26 19:36:51.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_cfg.h 2013-07-26 19:37:11.000000000 +0000 +@@ -19,14 +19,12 @@ + #ifndef VCHIQ_CFG_H + #define VCHIQ_CFG_H + +-#define VCHIQ_MAGIC VCHIQ_MAKE_FOURCC('V', 'C', 'H', 'I') ++#define VCHIQ_MAGIC VCHIQ_MAKE_FOURCC('V','C','H','I') + /* The version of VCHIQ - change with any non-trivial change */ +-#define VCHIQ_VERSION 5 +-/* The minimum compatible version - update to match VCHIQ_VERSION with any +-** incompatible change */ +-#define VCHIQ_VERSION_MIN 3 ++#define VCHIQ_VERSION 2 ++/* The minimum compatible version - update to match VCHIQ_VERSION with any incompatible change */ ++#define VCHIQ_VERSION_MIN 2 + +-#define VCHIQ_MAX_STATES 1 + #define VCHIQ_MAX_SERVICES 4096 + #define VCHIQ_MAX_SLOTS 128 + #define VCHIQ_MAX_SLOTS_PER_SIDE 64 +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_connected.c +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_connected.c 2013-07-26 19:36:51.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_connected.c 2013-07-26 19:37:11.000000000 +0000 +@@ -12,18 +12,20 @@ + * consent. + *****************************************************************************/ + ++#include "vcos.h" + #include "vchiq_connected.h" +-#include "vchiq_core.h" + #include +-#include + + #define MAX_CALLBACKS 10 + +-static int g_connected; ++static int g_connected = 0; + static int g_num_deferred_callbacks; +-static VCHIQ_CONNECTED_CALLBACK_T g_deferred_callback[MAX_CALLBACKS]; +-static int g_once_init; +-static struct mutex g_connected_mutex; ++static VCHIQ_CONNECTED_CALLBACK_T g_deferred_callback[ MAX_CALLBACKS ]; ++static VCOS_ONCE_T g_once_init; ++static VCOS_MUTEX_T g_connected_mutex; ++ ++extern VCOS_LOG_CAT_T vchiq_core_log_category; ++#define VCOS_LOG_CATEGORY (&vchiq_core_log_category) + + /**************************************************************************** + * +@@ -31,12 +33,9 @@ + * + ***************************************************************************/ + +-static void connected_init(void) ++static void connected_init( void ) + { +- if (!g_once_init) { +- mutex_init(&g_connected_mutex); +- g_once_init = 1; +- } ++ vcos_mutex_create( &g_connected_mutex, "connected_mutex"); + } + + /**************************************************************************** +@@ -48,30 +47,32 @@ + * + ***************************************************************************/ + +-void vchiq_add_connected_callback(VCHIQ_CONNECTED_CALLBACK_T callback) ++void vchiq_add_connected_callback( VCHIQ_CONNECTED_CALLBACK_T callback ) + { +- connected_init(); +- +- if (mutex_lock_interruptible(&g_connected_mutex) != 0) +- return; ++ vcos_once( &g_once_init, connected_init ); + +- if (g_connected) +- /* We're already connected. Call the callback immediately. */ ++ vcos_mutex_lock( &g_connected_mutex ); + +- callback(); +- else { +- if (g_num_deferred_callbacks >= MAX_CALLBACKS) +- vchiq_log_error(vchiq_core_log_level, +- "There already %d callback registered - " +- "please increase MAX_CALLBACKS", +- g_num_deferred_callbacks); +- else { +- g_deferred_callback[g_num_deferred_callbacks] = +- callback; +- g_num_deferred_callbacks++; +- } +- } +- mutex_unlock(&g_connected_mutex); ++ if ( g_connected ) ++ { ++ // We're already connected. Call the callback immediately. ++ ++ callback(); ++ } ++ else ++ { ++ if ( g_num_deferred_callbacks >= MAX_CALLBACKS ) ++ { ++ vcos_log_error( "There already %d callback registered - please increase MAX_CALLBACKS", ++ g_num_deferred_callbacks ); ++ } ++ else ++ { ++ g_deferred_callback[ g_num_deferred_callbacks ] = callback; ++ g_num_deferred_callbacks++; ++ } ++ } ++ vcos_mutex_unlock( &g_connected_mutex ); + } + + /**************************************************************************** +@@ -81,20 +82,20 @@ + * + ***************************************************************************/ + +-void vchiq_call_connected_callbacks(void) ++void vchiq_call_connected_callbacks( void ) + { +- int i; +- +- connected_init(); ++ int i; + +- if (mutex_lock_interruptible(&g_connected_mutex) != 0) +- return; ++ vcos_once( &g_once_init, connected_init ); + +- for (i = 0; i < g_num_deferred_callbacks; i++) +- g_deferred_callback[i](); +- +- g_num_deferred_callbacks = 0; +- g_connected = 1; +- mutex_unlock(&g_connected_mutex); ++ vcos_mutex_lock( &g_connected_mutex ); ++ for ( i = 0; i < g_num_deferred_callbacks; i++ )\ ++ { ++ g_deferred_callback[i](); ++ } ++ g_num_deferred_callbacks = 0; ++ g_connected = 1; ++ vcos_mutex_unlock( &g_connected_mutex ); + } +-EXPORT_SYMBOL(vchiq_add_connected_callback); ++ ++EXPORT_SYMBOL( vchiq_add_connected_callback ); +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_connected.h +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_connected.h 2013-07-26 19:36:51.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_connected.h 2013-07-26 19:37:11.000000000 +0000 +@@ -19,14 +19,14 @@ + + /* ---- Constants and Types ---------------------------------------------- */ + +-typedef void (*VCHIQ_CONNECTED_CALLBACK_T)(void); ++typedef void (*VCHIQ_CONNECTED_CALLBACK_T)( void ); + + /* ---- Variable Externs ------------------------------------------------- */ + + /* ---- Function Prototypes ---------------------------------------------- */ + +-void vchiq_add_connected_callback(VCHIQ_CONNECTED_CALLBACK_T callback); +-void vchiq_call_connected_callbacks(void); ++void vchiq_add_connected_callback( VCHIQ_CONNECTED_CALLBACK_T callback ); ++void vchiq_call_connected_callbacks( void ); + + #endif /* VCHIQ_CONNECTED_H */ + +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_core.c +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_core.c 2013-07-26 19:37:05.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_core.c 2013-07-26 19:37:11.000000000 +0000 +@@ -20,3741 +20,2698 @@ + + #define VCHIQ_SLOT_HANDLER_STACK 8192 + +-#define HANDLE_STATE_SHIFT 12 +- + #define SLOT_INFO_FROM_INDEX(state, index) (state->slot_info + (index)) + #define SLOT_DATA_FROM_INDEX(state, index) (state->slot_data + (index)) +-#define SLOT_INDEX_FROM_DATA(state, data) \ +- (((unsigned int)((char *)data - (char *)state->slot_data)) / \ +- VCHIQ_SLOT_SIZE) +-#define SLOT_INDEX_FROM_INFO(state, info) \ +- ((unsigned int)(info - state->slot_info)) +-#define SLOT_QUEUE_INDEX_FROM_POS(pos) \ +- ((int)((unsigned int)(pos) / VCHIQ_SLOT_SIZE)) ++#define SLOT_INDEX_FROM_DATA(state, data) (((unsigned int)((char *)data - (char *)state->slot_data)) / VCHIQ_SLOT_SIZE) ++#define SLOT_INDEX_FROM_INFO(state, info) ((unsigned int)(info - state->slot_info)) ++#define SLOT_QUEUE_INDEX_FROM_POS(pos) ((int)((unsigned int)(pos) / VCHIQ_SLOT_SIZE)) + ++#define VCOS_LOG_CATEGORY (&vchiq_core_log_category) + + #define BULK_INDEX(x) (x & (VCHIQ_NUM_SERVICE_BULKS - 1)) + + +-struct vchiq_open_payload { +- int fourcc; +- int client_id; +- short version; +- short version_min; +-}; ++/* Used to check use counts allow vchiq use. */ ++extern VCHIQ_STATUS_T vchiq_check_service(VCHIQ_SERVICE_T * service); + +-/* we require this for consistency between endpoints */ +-vchiq_static_assert(sizeof(VCHIQ_HEADER_T) == 8); +-vchiq_static_assert(IS_POW2(sizeof(VCHIQ_HEADER_T))); +-vchiq_static_assert(IS_POW2(VCHIQ_NUM_CURRENT_BULKS)); +-vchiq_static_assert(IS_POW2(VCHIQ_NUM_SERVICE_BULKS)); +-vchiq_static_assert(IS_POW2(VCHIQ_MAX_SERVICES)); +-vchiq_static_assert(VCHIQ_VERSION >= VCHIQ_VERSION_MIN); +- +-/* Run time control of log level, based on KERN_XXX level. */ +-int vchiq_core_log_level = VCHIQ_LOG_DEFAULT; +-int vchiq_core_msg_log_level = VCHIQ_LOG_DEFAULT; +-int vchiq_sync_log_level = VCHIQ_LOG_DEFAULT; +- +-static atomic_t pause_bulks_count = ATOMIC_INIT(0); +- +-static DEFINE_SPINLOCK(service_spinlock); +-DEFINE_SPINLOCK(bulk_waiter_spinlock); +-DEFINE_SPINLOCK(quota_spinlock); +- +-VCHIQ_STATE_T *vchiq_states[VCHIQ_MAX_STATES]; +-static unsigned int handle_seq; +- +-static const char *const srvstate_names[] = { +- "FREE", +- "HIDDEN", +- "LISTENING", +- "OPENING", +- "OPEN", +- "OPENSYNC", +- "CLOSESENT", +- "CLOSERECVD", +- "CLOSEWAIT", +- "CLOSED" +-}; + +-static const char *const reason_names[] = { +- "SERVICE_OPENED", +- "SERVICE_CLOSED", +- "MESSAGE_AVAILABLE", +- "BULK_TRANSMIT_DONE", +- "BULK_RECEIVE_DONE", +- "BULK_TRANSMIT_ABORTED", +- "BULK_RECEIVE_ABORTED" ++typedef struct bulk_waiter_struct ++{ ++ VCOS_EVENT_T event; ++ int actual; ++} BULK_WAITER_T; ++ ++typedef struct vchiq_open_payload_struct{ ++ int fourcc; ++ int client_id; ++ short version; ++ short version_min; ++} VCHIQ_OPEN_PAYLOAD_T; ++ ++vcos_static_assert(sizeof(VCHIQ_HEADER_T) == 8); /* we require this for consistency between endpoints */ ++vcos_static_assert(IS_POW2(sizeof(VCHIQ_HEADER_T))); ++vcos_static_assert(IS_POW2(VCHIQ_NUM_CURRENT_BULKS)); ++vcos_static_assert(IS_POW2(VCHIQ_NUM_SERVICE_BULKS)); ++ ++VCOS_LOG_CAT_T vchiq_core_log_category; ++VCOS_LOG_CAT_T vchiq_core_msg_log_category; ++VCOS_LOG_LEVEL_T vchiq_default_core_log_level = VCOS_LOG_WARN; ++VCOS_LOG_LEVEL_T vchiq_default_core_msg_log_level = VCOS_LOG_WARN; ++ ++static const char *const srvstate_names[] = ++{ ++ "FREE", ++ "HIDDEN", ++ "LISTENING", ++ "OPENING", ++ "OPEN", ++ "CLOSESENT", ++ "CLOSING", ++ "CLOSEWAIT" + }; + +-static const char *const conn_state_names[] = { +- "DISCONNECTED", +- "CONNECTING", +- "CONNECTED", +- "PAUSING", +- "PAUSE_SENT", +- "PAUSED", +- "RESUMING" ++static const char *const reason_names[] = ++{ ++ "SERVICE_OPENED", ++ "SERVICE_CLOSED", ++ "MESSAGE_AVAILABLE", ++ "BULK_TRANSMIT_DONE", ++ "BULK_RECEIVE_DONE", ++ "BULK_TRANSMIT_ABORTED", ++ "BULK_RECEIVE_ABORTED" + }; + ++static const char *const conn_state_names[] = ++{ ++ "DISCONNECTED", ++ "CONNECTED", ++ "PAUSING", ++ "PAUSE_SENT", ++ "PAUSED", ++ "RESUMING" ++}; + +-static void +-release_message_sync(VCHIQ_STATE_T *state, VCHIQ_HEADER_T *header); +- +-static const char *msg_type_str(unsigned int msg_type) ++static const char *msg_type_str( unsigned int msg_type ) + { +- switch (msg_type) { +- case VCHIQ_MSG_PADDING: return "PADDING"; +- case VCHIQ_MSG_CONNECT: return "CONNECT"; +- case VCHIQ_MSG_OPEN: return "OPEN"; +- case VCHIQ_MSG_OPENACK: return "OPENACK"; +- case VCHIQ_MSG_CLOSE: return "CLOSE"; +- case VCHIQ_MSG_DATA: return "DATA"; +- case VCHIQ_MSG_BULK_RX: return "BULK_RX"; +- case VCHIQ_MSG_BULK_TX: return "BULK_TX"; +- case VCHIQ_MSG_BULK_RX_DONE: return "BULK_RX_DONE"; +- case VCHIQ_MSG_BULK_TX_DONE: return "BULK_TX_DONE"; +- case VCHIQ_MSG_PAUSE: return "PAUSE"; +- case VCHIQ_MSG_RESUME: return "RESUME"; +- case VCHIQ_MSG_REMOTE_USE: return "REMOTE_USE"; +- case VCHIQ_MSG_REMOTE_RELEASE: return "REMOTE_RELEASE"; +- case VCHIQ_MSG_REMOTE_USE_ACTIVE: return "REMOTE_USE_ACTIVE"; +- } +- return "???"; ++ switch (msg_type) { ++ case VCHIQ_MSG_PADDING: return "PADDING"; ++ case VCHIQ_MSG_CONNECT: return "CONNECT"; ++ case VCHIQ_MSG_OPEN: return "OPEN"; ++ case VCHIQ_MSG_OPENACK: return "OPENACK"; ++ case VCHIQ_MSG_CLOSE: return "CLOSE"; ++ case VCHIQ_MSG_DATA: return "DATA"; ++ case VCHIQ_MSG_BULK_RX: return "BULK_RX"; ++ case VCHIQ_MSG_BULK_TX: return "BULK_TX"; ++ case VCHIQ_MSG_BULK_RX_DONE: return "BULK_RX_DONE"; ++ case VCHIQ_MSG_BULK_TX_DONE: return "BULK_TX_DONE"; ++ case VCHIQ_MSG_PAUSE: return "PAUSE"; ++ case VCHIQ_MSG_RESUME: return "RESUME"; ++ } ++ return "???"; + } + + static inline void + vchiq_set_service_state(VCHIQ_SERVICE_T *service, int newstate) + { +- vchiq_log_info(vchiq_core_log_level, "%d: srv:%d %s->%s", +- service->state->id, service->localport, +- srvstate_names[service->srvstate], +- srvstate_names[newstate]); +- service->srvstate = newstate; +-} +- +-VCHIQ_SERVICE_T * +-find_service_by_handle(VCHIQ_SERVICE_HANDLE_T handle) +-{ +- VCHIQ_SERVICE_T *service; +- +- spin_lock(&service_spinlock); +- service = handle_to_service(handle); +- if (service && (service->srvstate != VCHIQ_SRVSTATE_FREE) && +- (service->handle == handle)) { +- BUG_ON(service->ref_count == 0); +- service->ref_count++; +- } else +- service = NULL; +- spin_unlock(&service_spinlock); +- +- if (!service) +- vchiq_log_info(vchiq_core_log_level, +- "Invalid service handle 0x%x", handle); +- +- return service; +-} +- +-VCHIQ_SERVICE_T * +-find_service_by_port(VCHIQ_STATE_T *state, int localport) +-{ +- VCHIQ_SERVICE_T *service = NULL; +- if ((unsigned int)localport <= VCHIQ_PORT_MAX) { +- spin_lock(&service_spinlock); +- service = state->services[localport]; +- if (service && (service->srvstate != VCHIQ_SRVSTATE_FREE)) { +- BUG_ON(service->ref_count == 0); +- service->ref_count++; +- } else +- service = NULL; +- spin_unlock(&service_spinlock); +- } +- +- if (!service) +- vchiq_log_info(vchiq_core_log_level, +- "Invalid port %d", localport); +- +- return service; +-} +- +-VCHIQ_SERVICE_T * +-find_service_for_instance(VCHIQ_INSTANCE_T instance, +- VCHIQ_SERVICE_HANDLE_T handle) { +- VCHIQ_SERVICE_T *service; +- +- spin_lock(&service_spinlock); +- service = handle_to_service(handle); +- if (service && (service->srvstate != VCHIQ_SRVSTATE_FREE) && +- (service->handle == handle) && +- (service->instance == instance)) { +- BUG_ON(service->ref_count == 0); +- service->ref_count++; +- } else +- service = NULL; +- spin_unlock(&service_spinlock); +- +- if (!service) +- vchiq_log_info(vchiq_core_log_level, +- "Invalid service handle 0x%x", handle); +- +- return service; +-} +- +-VCHIQ_SERVICE_T * +-next_service_by_instance(VCHIQ_STATE_T *state, VCHIQ_INSTANCE_T instance, +- int *pidx) +-{ +- VCHIQ_SERVICE_T *service = NULL; +- int idx = *pidx; +- +- spin_lock(&service_spinlock); +- while (idx < state->unused_service) { +- VCHIQ_SERVICE_T *srv = state->services[idx++]; +- if (srv && (srv->srvstate != VCHIQ_SRVSTATE_FREE) && +- (srv->instance == instance)) { +- service = srv; +- BUG_ON(service->ref_count == 0); +- service->ref_count++; +- break; +- } +- } +- spin_unlock(&service_spinlock); +- +- *pidx = idx; +- +- return service; +-} +- +-void +-lock_service(VCHIQ_SERVICE_T *service) +-{ +- spin_lock(&service_spinlock); +- BUG_ON(!service || (service->ref_count == 0)); +- if (service) +- service->ref_count++; +- spin_unlock(&service_spinlock); +-} +- +-void +-unlock_service(VCHIQ_SERVICE_T *service) +-{ +- VCHIQ_STATE_T *state = service->state; +- spin_lock(&service_spinlock); +- BUG_ON(!service || (service->ref_count == 0)); +- if (service && service->ref_count) { +- service->ref_count--; +- if (!service->ref_count) { +- BUG_ON(service->srvstate != VCHIQ_SRVSTATE_FREE); +- state->services[service->localport] = NULL; +- } +- else +- service = NULL; +- } +- spin_unlock(&service_spinlock); +- +- kfree(service); +-} +- +-int +-vchiq_get_client_id(VCHIQ_SERVICE_HANDLE_T handle) +-{ +- VCHIQ_SERVICE_T *service = find_service_by_handle(handle); +- int id; +- +- id = service ? service->client_id : 0; +- if (service) +- unlock_service(service); +- +- return id; ++ vcos_log_info("%d: srv:%d %s->%s", service->state->id, service->localport, ++ srvstate_names[service->srvstate], ++ srvstate_names[newstate]); ++ service->srvstate = newstate; + } + +-void * +-vchiq_get_service_userdata(VCHIQ_SERVICE_HANDLE_T handle) +-{ +- VCHIQ_SERVICE_T *service = handle_to_service(handle); +- +- return service ? service->base.userdata : NULL; +-} +- +-int +-vchiq_get_service_fourcc(VCHIQ_SERVICE_HANDLE_T handle) +-{ +- VCHIQ_SERVICE_T *service = handle_to_service(handle); +- +- return service ? service->base.fourcc : 0; +-} +- +-static void +-mark_service_closing(VCHIQ_SERVICE_T *service) ++static inline int ++is_valid_service(VCHIQ_SERVICE_T *service) + { +- VCHIQ_STATE_T *state = service->state; +- VCHIQ_SERVICE_QUOTA_T *service_quota; +- +- service->closing = 1; +- +- /* Synchronise with other threads. */ +- mutex_lock(&state->recycle_mutex); +- mutex_unlock(&state->recycle_mutex); +- mutex_lock(&state->slot_mutex); +- mutex_unlock(&state->slot_mutex); +- +- /* Unblock any sending thread. */ +- service_quota = &state->service_quotas[service->localport]; +- up(&service_quota->quota_event); ++ return ((service != NULL) && ++ (service->srvstate != VCHIQ_SRVSTATE_FREE)); + } + + static inline VCHIQ_STATUS_T + make_service_callback(VCHIQ_SERVICE_T *service, VCHIQ_REASON_T reason, +- VCHIQ_HEADER_T *header, void *bulk_userdata) ++ VCHIQ_HEADER_T *header, void *bulk_userdata) + { +- vchiq_log_trace(vchiq_core_log_level, "%d: callback:%d (%s, %x, %x)", +- service->state->id, service->localport, reason_names[reason], +- (unsigned int)header, (unsigned int)bulk_userdata); +- return service->base.callback(reason, header, service->handle, +- bulk_userdata); ++ vcos_log_trace("%d: callback:%d (%s, %x, %x)", service->state->id, ++ service->localport, reason_names[reason], ++ (unsigned int)header, (unsigned int)bulk_userdata); ++ return service->base.callback(reason, header, &service->base, bulk_userdata); + } + + static inline void + vchiq_set_conn_state(VCHIQ_STATE_T *state, VCHIQ_CONNSTATE_T newstate) + { +- VCHIQ_CONNSTATE_T oldstate = state->conn_state; +- vchiq_log_info(vchiq_core_log_level, "%d: %s->%s", state->id, +- conn_state_names[oldstate], +- conn_state_names[newstate]); +- state->conn_state = newstate; +- vchiq_platform_conn_state_changed(state, oldstate, newstate); ++ VCHIQ_CONNSTATE_T oldstate = state->conn_state; ++ vcos_log_info("%d: %s->%s", state->id, ++ conn_state_names[oldstate], ++ conn_state_names[newstate]); ++ state->conn_state = newstate; ++ vchiq_platform_conn_state_changed(state, oldstate, newstate); + } + + static inline void + remote_event_create(REMOTE_EVENT_T *event) + { +- event->armed = 0; +- /* Don't clear the 'fired' flag because it may already have been set +- ** by the other side. */ +- sema_init(event->event, 0); ++ event->armed = 0; ++ /* Don't clear the 'fired' flag because it may already have been set by the other side */ ++ vcos_event_create(event->event, "vchiq"); + } + + static inline void + remote_event_destroy(REMOTE_EVENT_T *event) + { +- (void)event; ++ vcos_event_delete(event->event); + } + + static inline int + remote_event_wait(REMOTE_EVENT_T *event) + { +- if (!event->fired) { +- event->armed = 1; +- dsb(); +- if (!event->fired) { +- if (down_interruptible(event->event) != 0) { +- event->armed = 0; +- return 0; +- } +- } +- event->armed = 0; +- wmb(); +- } ++ if (!event->fired) ++ { ++ event->armed = 1; ++ if (event->fired) /* Also ensures the write has completed */ ++ event->armed = 0; ++ else if (vcos_event_wait(event->event) != VCOS_SUCCESS) ++ return 0; ++ } + +- event->fired = 0; +- return 1; ++ event->fired = 0; ++ return 1; + } + + static inline void + remote_event_signal_local(REMOTE_EVENT_T *event) + { +- event->armed = 0; +- up(event->event); ++ event->armed = 0; ++ vcos_event_signal(event->event); + } + + static inline void + remote_event_poll(REMOTE_EVENT_T *event) + { +- if (event->fired && event->armed) +- remote_event_signal_local(event); ++ if (event->armed) ++ remote_event_signal_local(event); + } + + void + remote_event_pollall(VCHIQ_STATE_T *state) + { +- remote_event_poll(&state->local->sync_trigger); +- remote_event_poll(&state->local->sync_release); +- remote_event_poll(&state->local->trigger); +- remote_event_poll(&state->local->recycle); ++ remote_event_poll(&state->local->trigger); ++ remote_event_poll(&state->local->recycle); + } + + /* Round up message sizes so that any space at the end of a slot is always big +-** enough for a header. This relies on header size being a power of two, which +-** has been verified earlier by a static assertion. */ ++ enough for a header. This relies on header size being a power of two, which ++ has been verified earlier by a static assertion. */ + + static inline unsigned int + calc_stride(unsigned int size) + { +- /* Allow room for the header */ +- size += sizeof(VCHIQ_HEADER_T); ++ /* Allow room for the header */ ++ size += sizeof(VCHIQ_HEADER_T); + +- /* Round up */ +- return (size + sizeof(VCHIQ_HEADER_T) - 1) & ~(sizeof(VCHIQ_HEADER_T) +- - 1); ++ /* Round up */ ++ return (size + sizeof(VCHIQ_HEADER_T) - 1) & ~(sizeof(VCHIQ_HEADER_T) - 1); + } + +-/* Called by the slot handler thread */ + static VCHIQ_SERVICE_T * + get_listening_service(VCHIQ_STATE_T *state, int fourcc) + { +- int i; ++ int i; + +- WARN_ON(fourcc == VCHIQ_FOURCC_INVALID); ++ vcos_assert(fourcc != VCHIQ_FOURCC_INVALID); + +- for (i = 0; i < state->unused_service; i++) { +- VCHIQ_SERVICE_T *service = state->services[i]; +- if (service && +- (service->public_fourcc == fourcc) && +- ((service->srvstate == VCHIQ_SRVSTATE_LISTENING) || +- ((service->srvstate == VCHIQ_SRVSTATE_OPEN) && +- (service->remoteport == VCHIQ_PORT_FREE)))) { +- lock_service(service); +- return service; +- } +- } ++ for (i = 0; i < state->unused_service; i++) ++ { ++ VCHIQ_SERVICE_T *service = state->services[i]; ++ if (service && ++ (service->public_fourcc == fourcc) && ++ ((service->srvstate == VCHIQ_SRVSTATE_LISTENING) || ++ ((service->srvstate == VCHIQ_SRVSTATE_OPEN) && ++ (service->remoteport == VCHIQ_PORT_FREE)))) ++ return service; ++ } + +- return NULL; ++ return NULL; + } + +-/* Called by the slot handler thread */ + static VCHIQ_SERVICE_T * + get_connected_service(VCHIQ_STATE_T *state, unsigned int port) + { +- int i; +- for (i = 0; i < state->unused_service; i++) { +- VCHIQ_SERVICE_T *service = state->services[i]; +- if (service && (service->srvstate == VCHIQ_SRVSTATE_OPEN) +- && (service->remoteport == port)) { +- lock_service(service); +- return service; +- } +- } +- return NULL; ++ int i; ++ for (i = 0; i < state->unused_service; i++) { ++ VCHIQ_SERVICE_T *service = state->services[i]; ++ if (service && (service->srvstate == VCHIQ_SRVSTATE_OPEN) ++ && (service->remoteport == port)) { ++ return service; ++ } ++ } ++ return NULL; + } + +-inline void ++static inline void + request_poll(VCHIQ_STATE_T *state, VCHIQ_SERVICE_T *service, int poll_type) + { +- uint32_t value; +- +- if (service) { +- do { +- value = atomic_read(&service->poll_flags); +- } while (atomic_cmpxchg(&service->poll_flags, value, +- value | (1 << poll_type)) != value); +- +- do { +- value = atomic_read(&state->poll_services[ +- service->localport>>5]); +- } while (atomic_cmpxchg( +- &state->poll_services[service->localport>>5], +- value, value | (1 << (service->localport & 0x1f))) +- != value); +- } ++ if (service) ++ { ++ vcos_atomic_flags_or(&service->poll_flags, (1 << poll_type)); ++ vcos_atomic_flags_or(&state->poll_services[service->localport>>5], ++ (1 <<(service->localport & 0x1f))); ++ } + +- state->poll_needed = 1; +- wmb(); ++ state->poll_needed = 1; ++ vcos_wmb(&state->poll_needed); + +- /* ... and ensure the slot handler runs. */ +- remote_event_signal_local(&state->local->trigger); ++ /* ... and ensure the slot handler runs. */ ++ remote_event_signal_local(&state->local->trigger); + } + + /* Called from queue_message, by the slot handler and application threads, +-** with slot_mutex held */ ++ with slot_mutex held */ + static VCHIQ_HEADER_T * + reserve_space(VCHIQ_STATE_T *state, int space, int is_blocking) + { +- VCHIQ_SHARED_STATE_T *local = state->local; +- int tx_pos = state->local_tx_pos; +- int slot_space = VCHIQ_SLOT_SIZE - (tx_pos & VCHIQ_SLOT_MASK); +- +- if (space > slot_space) { +- VCHIQ_HEADER_T *header; +- /* Fill the remaining space with padding */ +- WARN_ON(state->tx_data == NULL); +- header = (VCHIQ_HEADER_T *) +- (state->tx_data + (tx_pos & VCHIQ_SLOT_MASK)); +- header->msgid = VCHIQ_MSGID_PADDING; +- header->size = slot_space - sizeof(VCHIQ_HEADER_T); +- +- tx_pos += slot_space; +- } +- +- /* If necessary, get the next slot. */ +- if ((tx_pos & VCHIQ_SLOT_MASK) == 0) { +- int slot_index; ++ VCHIQ_SHARED_STATE_T *local = state->local; ++ int tx_pos = state->local_tx_pos; ++ int slot_space = VCHIQ_SLOT_SIZE - (tx_pos & VCHIQ_SLOT_MASK); ++ ++ if (space > slot_space) { ++ VCHIQ_HEADER_T *header; ++ /* Fill the remaining space with padding */ ++ vcos_assert(state->tx_data != NULL); ++ header = (VCHIQ_HEADER_T *) (state->tx_data + (tx_pos & VCHIQ_SLOT_MASK)); ++ header->msgid = VCHIQ_MSGID_PADDING; ++ header->size = slot_space - sizeof(VCHIQ_HEADER_T); ++ ++ tx_pos += slot_space; ++ } ++ ++ /* If necessary, get the next slot. */ ++ if ((tx_pos & VCHIQ_SLOT_MASK) == 0) ++ { ++ int slot_index; ++ ++ /* If there is no free slot... */ ++ if (tx_pos == (state->slot_queue_available * VCHIQ_SLOT_SIZE)) ++ { ++ /* ...wait for one. */ ++ VCHIQ_STATS_INC(state, slot_stalls); ++ ++ /* But first, flush through the last slot. */ ++ local->tx_pos = tx_pos; ++ remote_event_signal(&state->remote->trigger); ++ ++ do { ++ if (!is_blocking || ++ (vcos_event_wait(&state->slot_available_event) != VCOS_SUCCESS)) ++ { ++ return NULL; /* No space available now */ ++ } ++ } ++ while (tx_pos == (state->slot_queue_available * VCHIQ_SLOT_SIZE)); ++ } ++ ++ slot_index = local->slot_queue[SLOT_QUEUE_INDEX_FROM_POS(tx_pos) & VCHIQ_SLOT_QUEUE_MASK]; ++ state->tx_data = (char *)SLOT_DATA_FROM_INDEX(state, slot_index); ++ } + +- /* If there is no free slot... */ ++ state->local_tx_pos = tx_pos + space; + +- if (down_trylock(&state->slot_available_event) != 0) { +- /* ...wait for one. */ +- +- VCHIQ_STATS_INC(state, slot_stalls); +- +- /* But first, flush through the last slot. */ +- state->local_tx_pos = tx_pos; +- local->tx_pos = tx_pos; +- remote_event_signal(&state->remote->trigger); +- +- if (!is_blocking || +- (down_interruptible( +- &state->slot_available_event) != 0)) +- return NULL; /* No space available */ +- } +- +- BUG_ON(tx_pos == +- (state->slot_queue_available * VCHIQ_SLOT_SIZE)); +- +- slot_index = local->slot_queue[ +- SLOT_QUEUE_INDEX_FROM_POS(tx_pos) & +- VCHIQ_SLOT_QUEUE_MASK]; +- state->tx_data = +- (char *)SLOT_DATA_FROM_INDEX(state, slot_index); +- } +- +- state->local_tx_pos = tx_pos + space; +- +- return (VCHIQ_HEADER_T *)(state->tx_data + (tx_pos & VCHIQ_SLOT_MASK)); ++ return (VCHIQ_HEADER_T *)(state->tx_data + (tx_pos & VCHIQ_SLOT_MASK)); + } + +-/* Called by the recycle thread. */ ++/* Called with slot_mutex held */ + static void + process_free_queue(VCHIQ_STATE_T *state) + { +- VCHIQ_SHARED_STATE_T *local = state->local; +- BITSET_T service_found[BITSET_SIZE(VCHIQ_MAX_SERVICES)]; +- int slot_queue_available; +- +- /* Use a read memory barrier to ensure that any state that may have +- ** been modified by another thread is not masked by stale prefetched +- ** values. */ +- rmb(); +- +- /* Find slots which have been freed by the other side, and return them +- ** to the available queue. */ +- slot_queue_available = state->slot_queue_available; +- +- while (slot_queue_available != local->slot_queue_recycle) { +- unsigned int pos; +- int slot_index = local->slot_queue[slot_queue_available++ & +- VCHIQ_SLOT_QUEUE_MASK]; +- char *data = (char *)SLOT_DATA_FROM_INDEX(state, slot_index); +- int data_found = 0; +- +- vchiq_log_trace(vchiq_core_log_level, "%d: pfq %d=%x %x %x", +- state->id, slot_index, (unsigned int)data, +- local->slot_queue_recycle, slot_queue_available); +- +- /* Initialise the bitmask for services which have used this +- ** slot */ +- BITSET_ZERO(service_found); +- +- pos = 0; +- +- while (pos < VCHIQ_SLOT_SIZE) { +- VCHIQ_HEADER_T *header = +- (VCHIQ_HEADER_T *)(data + pos); +- int msgid = header->msgid; +- if (VCHIQ_MSG_TYPE(msgid) == VCHIQ_MSG_DATA) { +- int port = VCHIQ_MSG_SRCPORT(msgid); +- VCHIQ_SERVICE_QUOTA_T *service_quota = +- &state->service_quotas[port]; +- int count; +- spin_lock("a_spinlock); +- count = service_quota->message_use_count; +- if (count > 0) +- service_quota->message_use_count = +- count - 1; +- spin_unlock("a_spinlock); +- +- if (count == service_quota->message_quota) +- /* Signal the service that it +- ** has dropped below its quota +- */ +- up(&service_quota->quota_event); +- else if (count == 0) { +- vchiq_log_error(vchiq_core_log_level, +- "service %d " +- "message_use_count=%d " +- "(header %x, msgid %x, " +- "header->msgid %x, " +- "header->size %x)", +- port, +- service_quota-> +- message_use_count, +- (unsigned int)header, msgid, +- header->msgid, +- header->size); +- WARN(1, "invalid message use count\n"); +- } +- if (!BITSET_IS_SET(service_found, port)) { +- /* Set the found bit for this service */ +- BITSET_SET(service_found, port); +- +- spin_lock("a_spinlock); +- count = service_quota->slot_use_count; +- if (count > 0) +- service_quota->slot_use_count = +- count - 1; +- spin_unlock("a_spinlock); +- +- if (count > 0) { +- /* Signal the service in case +- ** it has dropped below its +- ** quota */ +- up(&service_quota->quota_event); +- vchiq_log_trace( +- vchiq_core_log_level, +- "%d: pfq:%d %x@%x - " +- "slot_use->%d", +- state->id, port, +- header->size, +- (unsigned int)header, +- count - 1); +- } else { +- vchiq_log_error( +- vchiq_core_log_level, +- "service %d " +- "slot_use_count" +- "=%d (header %x" +- ", msgid %x, " +- "header->msgid" +- " %x, header->" +- "size %x)", +- port, count, +- (unsigned int)header, +- msgid, +- header->msgid, +- header->size); +- WARN(1, "bad slot use count\n"); +- } +- } +- +- data_found = 1; +- } +- +- pos += calc_stride(header->size); +- if (pos > VCHIQ_SLOT_SIZE) { +- vchiq_log_error(vchiq_core_log_level, +- "pfq - pos %x: header %x, msgid %x, " +- "header->msgid %x, header->size %x", +- pos, (unsigned int)header, msgid, +- header->msgid, header->size); +- WARN(1, "invalid slot position\n"); +- } +- } +- +- if (data_found) { +- int count; +- spin_lock("a_spinlock); +- count = state->data_use_count; +- if (count > 0) +- state->data_use_count = +- count - 1; +- spin_unlock("a_spinlock); +- if (count == state->data_quota) +- up(&state->data_quota_event); +- } +- +- state->slot_queue_available = slot_queue_available; +- up(&state->slot_available_event); +- } ++ VCHIQ_SHARED_STATE_T *local = state->local; ++ BITSET_T service_found[BITSET_SIZE(VCHIQ_MAX_SERVICES)]; ++ int slot_queue_available; ++ ++ /* Use a read memory barrier to ensure that any state that may have ++ been modified by another thread is not masked by stale prefetched ++ values. */ ++ vcos_rmb(); ++ ++ /* Find slots which have been freed by the other side, and return them to ++ the available queue. */ ++ slot_queue_available = state->slot_queue_available; ++ ++ while (slot_queue_available != local->slot_queue_recycle) ++ { ++ unsigned int pos; ++ int slot_index = local->slot_queue[slot_queue_available++ & VCHIQ_SLOT_QUEUE_MASK]; ++ char *data = (char *)SLOT_DATA_FROM_INDEX(state, slot_index); ++ ++ vcos_log_trace("%d: pfq %d=%x %x %x", state->id, slot_index, ++ (unsigned int)data, local->slot_queue_recycle, ++ slot_queue_available); ++ ++ /* Initialise the bitmask for services which have used this slot */ ++ BITSET_ZERO(service_found); ++ ++ pos = 0; ++ ++ while (pos < VCHIQ_SLOT_SIZE) ++ { ++ VCHIQ_HEADER_T *header = (VCHIQ_HEADER_T *)(data + pos); ++ int msgid = header->msgid; ++ if (VCHIQ_MSG_TYPE(msgid) == VCHIQ_MSG_DATA) ++ { ++ int port = VCHIQ_MSG_SRCPORT(msgid); ++ VCHIQ_SERVICE_QUOTA_T *service_quota = ++ &state->service_quotas[port]; ++ int count; ++ count = service_quota->message_use_count; ++ if (count > 0) ++ { ++ service_quota->message_use_count = count - 1; ++ if (count == service_quota->message_quota) ++ { ++ /* Signal the service that it has dropped below its quota */ ++ vcos_event_signal(&service_quota->quota_event); ++ } ++ } ++ else ++ { ++ vcos_log_error("service %d message_use_count=%d (header %x," ++ " msgid %x, header->msgid %x, header->size %x)", ++ port, service_quota->message_use_count, ++ (unsigned int)header, msgid, header->msgid, ++ header->size); ++ vcos_assert(0); ++ } ++ if (!BITSET_IS_SET(service_found, port)) ++ { ++ /* Set the found bit for this service */ ++ BITSET_SET(service_found, port); ++ ++ count = service_quota->slot_use_count; ++ if (count > 0) ++ { ++ service_quota->slot_use_count = count - 1; ++ /* Signal the service in case it has dropped below its quota */ ++ vcos_event_signal(&service_quota->quota_event); ++ vcos_log_trace("%d: pfq:%d %x@%x - slot_use->%d", ++ state->id, port, ++ header->size, (unsigned int)header, ++ service_quota->slot_use_count); ++ } ++ else ++ { ++ vcos_log_error("service %d slot_use_count=%d (header %x," ++ " msgid %x, header->msgid %x, header->size %x)", ++ port, service_quota->slot_use_count, ++ (unsigned int)header, msgid, header->msgid, ++ header->size); ++ vcos_assert(0); ++ } ++ } ++ } ++ ++ pos += calc_stride(header->size); ++ if (pos > VCHIQ_SLOT_SIZE) ++ { ++ vcos_log_error("pfq - pos %x: header %x, msgid %x, header->msgid %x, header->size %x", ++ pos, (unsigned int)header, msgid, header->msgid, header->size); ++ vcos_assert(0); ++ } ++ } ++ } ++ ++ if (slot_queue_available != state->slot_queue_available) ++ { ++ state->slot_queue_available = slot_queue_available; ++ vcos_wmb(&state->slot_queue_available); ++ vcos_event_signal(&state->slot_available_event); ++ } + } + + /* Called by the slot handler and application threads */ + static VCHIQ_STATUS_T + queue_message(VCHIQ_STATE_T *state, VCHIQ_SERVICE_T *service, +- int msgid, const VCHIQ_ELEMENT_T *elements, +- int count, int size, int is_blocking) ++ int msgid, const VCHIQ_ELEMENT_T *elements, ++ int count, int size, int is_blocking) + { +- VCHIQ_SHARED_STATE_T *local; +- VCHIQ_SERVICE_QUOTA_T *service_quota = NULL; +- VCHIQ_HEADER_T *header; +- int type = VCHIQ_MSG_TYPE(msgid); +- +- unsigned int stride; +- +- local = state->local; +- +- stride = calc_stride(size); +- +- WARN_ON(!(stride <= VCHIQ_SLOT_SIZE)); +- +- if ((type != VCHIQ_MSG_RESUME) && +- (mutex_lock_interruptible(&state->slot_mutex) != 0)) +- return VCHIQ_RETRY; +- +- if (type == VCHIQ_MSG_DATA) { +- int tx_end_index; +- +- BUG_ON(!service); +- +- if (service->closing) { +- /* The service has been closed */ +- mutex_unlock(&state->slot_mutex); +- return VCHIQ_ERROR; +- } +- +- service_quota = &state->service_quotas[service->localport]; +- +- spin_lock("a_spinlock); +- +- /* Ensure this service doesn't use more than its quota of +- ** messages or slots */ +- tx_end_index = SLOT_QUEUE_INDEX_FROM_POS( +- state->local_tx_pos + stride - 1); +- +- /* Ensure data messages don't use more than their quota of +- ** slots */ +- while ((tx_end_index != state->previous_data_index) && +- (state->data_use_count == state->data_quota)) { +- VCHIQ_STATS_INC(state, data_stalls); +- spin_unlock("a_spinlock); +- mutex_unlock(&state->slot_mutex); +- +- if (down_interruptible(&state->data_quota_event) +- != 0) +- return VCHIQ_RETRY; +- +- mutex_lock(&state->slot_mutex); +- spin_lock("a_spinlock); +- tx_end_index = SLOT_QUEUE_INDEX_FROM_POS( +- state->local_tx_pos + stride - 1); +- if ((tx_end_index == state->previous_data_index) || +- (state->data_use_count < state->data_quota)) { +- /* Pass the signal on to other waiters */ +- up(&state->data_quota_event); +- break; +- } +- } +- +- while ((service_quota->message_use_count == +- service_quota->message_quota) || +- ((tx_end_index != service_quota->previous_tx_index) && +- (service_quota->slot_use_count == +- service_quota->slot_quota))) { +- spin_unlock("a_spinlock); +- vchiq_log_trace(vchiq_core_log_level, +- "%d: qm:%d %s,%x - quota stall " +- "(msg %d, slot %d)", +- state->id, service->localport, +- msg_type_str(type), size, +- service_quota->message_use_count, +- service_quota->slot_use_count); +- VCHIQ_SERVICE_STATS_INC(service, quota_stalls); +- mutex_unlock(&state->slot_mutex); +- if (down_interruptible(&service_quota->quota_event) +- != 0) +- return VCHIQ_RETRY; +- if (service->closing) +- return VCHIQ_ERROR; +- if (mutex_lock_interruptible(&state->slot_mutex) != 0) +- return VCHIQ_RETRY; +- if (service->srvstate != VCHIQ_SRVSTATE_OPEN) { +- /* The service has been closed */ +- mutex_unlock(&state->slot_mutex); +- return VCHIQ_ERROR; +- } +- spin_lock("a_spinlock); +- tx_end_index = SLOT_QUEUE_INDEX_FROM_POS( +- state->local_tx_pos + stride - 1); +- } +- +- spin_unlock("a_spinlock); +- } +- +- header = reserve_space(state, stride, is_blocking); +- +- if (!header) { +- if (service) +- VCHIQ_SERVICE_STATS_INC(service, slot_stalls); +- mutex_unlock(&state->slot_mutex); +- return VCHIQ_RETRY; +- } +- +- if (type == VCHIQ_MSG_DATA) { +- int i, pos; +- int tx_end_index; +- int slot_use_count; +- +- vchiq_log_info(vchiq_core_log_level, +- "%d: qm %s@%x,%x (%d->%d)", +- state->id, +- msg_type_str(VCHIQ_MSG_TYPE(msgid)), +- (unsigned int)header, size, +- VCHIQ_MSG_SRCPORT(msgid), +- VCHIQ_MSG_DSTPORT(msgid)); +- +- BUG_ON(!service); +- +- for (i = 0, pos = 0; i < (unsigned int)count; +- pos += elements[i++].size) +- if (elements[i].size) { +- if (vchiq_copy_from_user +- (header->data + pos, elements[i].data, +- (size_t) elements[i].size) != +- VCHIQ_SUCCESS) { +- mutex_unlock(&state->slot_mutex); +- VCHIQ_SERVICE_STATS_INC(service, +- error_count); +- return VCHIQ_ERROR; +- } +- if (i == 0) { +- if (vchiq_core_msg_log_level >= +- VCHIQ_LOG_INFO) +- vchiq_log_dump_mem("Sent", 0, +- header->data + pos, +- min(64, +- elements[0].size)); +- } +- } +- +- spin_lock("a_spinlock); +- service_quota->message_use_count++; +- +- tx_end_index = +- SLOT_QUEUE_INDEX_FROM_POS(state->local_tx_pos - 1); +- +- /* If this transmission can't fit in the last slot used by any +- ** service, the data_use_count must be increased. */ +- if (tx_end_index != state->previous_data_index) { +- state->previous_data_index = tx_end_index; +- state->data_use_count++; +- } +- +- /* If this isn't the same slot last used by this service, +- ** the service's slot_use_count must be increased. */ +- if (tx_end_index != service_quota->previous_tx_index) { +- service_quota->previous_tx_index = tx_end_index; +- slot_use_count = ++service_quota->slot_use_count; +- } else { +- slot_use_count = 0; +- } +- +- spin_unlock("a_spinlock); +- +- if (slot_use_count) +- vchiq_log_trace(vchiq_core_log_level, +- "%d: qm:%d %s,%x - slot_use->%d (hdr %p)", +- state->id, service->localport, +- msg_type_str(VCHIQ_MSG_TYPE(msgid)), size, +- slot_use_count, header); +- +- VCHIQ_SERVICE_STATS_INC(service, ctrl_tx_count); +- VCHIQ_SERVICE_STATS_ADD(service, ctrl_tx_bytes, size); +- } else { +- vchiq_log_info(vchiq_core_log_level, +- "%d: qm %s@%x,%x (%d->%d)", state->id, +- msg_type_str(VCHIQ_MSG_TYPE(msgid)), +- (unsigned int)header, size, +- VCHIQ_MSG_SRCPORT(msgid), +- VCHIQ_MSG_DSTPORT(msgid)); +- if (size != 0) { +- WARN_ON(!((count == 1) && (size == elements[0].size))); +- memcpy(header->data, elements[0].data, +- elements[0].size); +- } +- VCHIQ_STATS_INC(state, ctrl_tx_count); +- } +- +- header->msgid = msgid; +- header->size = size; +- +- { +- int svc_fourcc; +- +- svc_fourcc = service +- ? service->base.fourcc +- : VCHIQ_MAKE_FOURCC('?', '?', '?', '?'); +- +- vchiq_log_info(vchiq_core_msg_log_level, +- "Sent Msg %s(%u) to %c%c%c%c s:%u d:%d len:%d", +- msg_type_str(VCHIQ_MSG_TYPE(msgid)), +- VCHIQ_MSG_TYPE(msgid), +- VCHIQ_FOURCC_AS_4CHARS(svc_fourcc), +- VCHIQ_MSG_SRCPORT(msgid), +- VCHIQ_MSG_DSTPORT(msgid), +- size); +- } +- +- /* Make sure the new header is visible to the peer. */ +- wmb(); +- +- /* Make the new tx_pos visible to the peer. */ +- local->tx_pos = state->local_tx_pos; +- wmb(); +- +- if (service && (type == VCHIQ_MSG_CLOSE)) +- vchiq_set_service_state(service, VCHIQ_SRVSTATE_CLOSESENT); ++ VCHIQ_SHARED_STATE_T *local; ++ VCHIQ_SERVICE_QUOTA_T *service_quota = NULL; ++ VCHIQ_HEADER_T *header; ++ ++ unsigned int stride; ++ ++ local = state->local; ++ ++ stride = calc_stride(size); ++ ++ vcos_assert(stride <= VCHIQ_SLOT_SIZE); ++ ++ /* On platforms where vcos_mutex_lock cannot fail, the return will never ++ be taken and the compiler may optimise out that code. Let Coverity ++ know this is intentional. ++ */ ++ /* coverity[constant_expression_result] */ ++ if ((VCHIQ_MSG_TYPE(msgid) != VCHIQ_MSG_RESUME) && ++ (vcos_mutex_lock(&state->slot_mutex) != VCOS_SUCCESS)) ++ return VCHIQ_RETRY; ++ ++ if (service) ++ { ++ int tx_end_index = SLOT_QUEUE_INDEX_FROM_POS(state->local_tx_pos + stride - 1); ++ ++ if (service->srvstate != VCHIQ_SRVSTATE_OPEN) ++ { ++ /* The service has been closed, probably while waiting for the mutex */ ++ vcos_mutex_unlock(&state->slot_mutex); ++ return VCHIQ_ERROR; ++ } ++ ++ service_quota = &state->service_quotas[service->localport]; ++ ++ /* ...ensure it doesn't use more than its quota of messages or slots */ ++ while ((service_quota->message_use_count == service_quota->message_quota) || ++ ((tx_end_index != service_quota->previous_tx_index) && ++ (service_quota->slot_use_count == service_quota->slot_quota))) ++ { ++ vcos_log_trace("%d: qm:%d %s,%x - quota stall (msg %d, slot %d)", ++ state->id, service->localport, ++ msg_type_str(VCHIQ_MSG_TYPE(msgid)), size, ++ service_quota->message_use_count, service_quota->slot_use_count); ++ VCHIQ_SERVICE_STATS_INC(service, quota_stalls); ++ vcos_mutex_unlock(&state->slot_mutex); ++ if (vcos_event_wait(&service_quota->quota_event) != VCOS_SUCCESS) ++ return VCHIQ_RETRY; ++ if (vcos_mutex_lock(&state->slot_mutex) != VCOS_SUCCESS) ++ return VCHIQ_RETRY; ++ tx_end_index = SLOT_QUEUE_INDEX_FROM_POS(state->local_tx_pos + stride - 1); ++ } ++ } ++ ++ header = reserve_space(state, stride, is_blocking); ++ ++ if (!header) { ++ if (service) ++ VCHIQ_SERVICE_STATS_INC(service, slot_stalls); ++ vcos_mutex_unlock(&state->slot_mutex); ++ return VCHIQ_RETRY; ++ } ++ ++ if (service) { ++ int i, pos; ++ int tx_end_index; ++ ++ vcos_log_info("%d: qm %s@%x,%x (%d->%d)", state->id, ++ msg_type_str(VCHIQ_MSG_TYPE(msgid)), ++ (unsigned int)header, size, ++ VCHIQ_MSG_SRCPORT(msgid), ++ VCHIQ_MSG_DSTPORT(msgid)); ++ ++ for (i = 0, pos = 0; i < (unsigned int)count; ++ pos += elements[i++].size) ++ if (elements[i].size) { ++ if (vchiq_copy_from_user ++ (header->data + pos, elements[i].data, ++ (size_t) elements[i].size) != ++ VCHIQ_SUCCESS) { ++ vcos_mutex_unlock(&state->slot_mutex); ++ VCHIQ_SERVICE_STATS_INC(service, error_count); ++ return VCHIQ_ERROR; ++ } ++ if (i == 0) { ++ vcos_log_dump_mem( &vchiq_core_msg_log_category, ++ "Sent", 0, header->data + pos, ++ vcos_min( 64, elements[0].size )); ++ } ++ } ++ ++ /* If this transmission can't fit in the last slot used by this service... */ ++ tx_end_index = SLOT_QUEUE_INDEX_FROM_POS(state->local_tx_pos - 1); ++ if (tx_end_index != service_quota->previous_tx_index) ++ { ++ service_quota->slot_use_count++; ++ vcos_log_trace("%d: qm:%d %s,%x - slot_use->%d", ++ state->id, service->localport, ++ msg_type_str(VCHIQ_MSG_TYPE(msgid)), size, ++ service_quota->slot_use_count); ++ } ++ ++ service_quota->previous_tx_index = tx_end_index; ++ service_quota->message_use_count++; ++ VCHIQ_SERVICE_STATS_INC(service, ctrl_tx_count); ++ VCHIQ_SERVICE_STATS_ADD(service, ctrl_tx_bytes, size); ++ } else { ++ vcos_log_info("%d: qm %s@%x,%x (%d->%d)", state->id, ++ msg_type_str(VCHIQ_MSG_TYPE(msgid)), ++ (unsigned int)header, size, ++ VCHIQ_MSG_SRCPORT(msgid), ++ VCHIQ_MSG_DSTPORT(msgid)); ++ if (size != 0) ++ { ++ vcos_assert((count == 1) && (size == elements[0].size)); ++ memcpy(header->data, elements[0].data, elements[0].size); ++ } ++ VCHIQ_STATS_INC(state, ctrl_tx_count); ++ } ++ ++ header->msgid = msgid; ++ header->size = size; ++ ++ if (vcos_is_log_enabled( &vchiq_core_msg_log_category, VCOS_LOG_INFO)) ++ { ++ int svc_fourcc; ++ ++ svc_fourcc = service ++ ? service->base.fourcc ++ : VCHIQ_MAKE_FOURCC('?','?','?','?'); ++ ++ vcos_log_impl( &vchiq_core_msg_log_category, ++ VCOS_LOG_INFO, ++ "Sent Msg %s(%u) to %c%c%c%c s:%u d:%d len:%d", ++ msg_type_str(VCHIQ_MSG_TYPE(msgid)), ++ VCHIQ_MSG_TYPE(msgid), ++ VCHIQ_FOURCC_AS_4CHARS(svc_fourcc), ++ VCHIQ_MSG_SRCPORT(msgid), ++ VCHIQ_MSG_DSTPORT(msgid), ++ size ); ++ } ++ ++ /* Make the new tx_pos visible to the peer. */ ++ local->tx_pos = state->local_tx_pos; ++ vcos_wmb(&local->tx_pos); + +- if (VCHIQ_MSG_TYPE(msgid) != VCHIQ_MSG_PAUSE) +- mutex_unlock(&state->slot_mutex); ++ if (VCHIQ_MSG_TYPE(msgid) != VCHIQ_MSG_PAUSE) ++ vcos_mutex_unlock(&state->slot_mutex); + +- remote_event_signal(&state->remote->trigger); ++ remote_event_signal(&state->remote->trigger); + +- return VCHIQ_SUCCESS; +-} +- +-/* Called by the slot handler and application threads */ +-static VCHIQ_STATUS_T +-queue_message_sync(VCHIQ_STATE_T *state, VCHIQ_SERVICE_T *service, +- int msgid, const VCHIQ_ELEMENT_T *elements, +- int count, int size, int is_blocking) +-{ +- VCHIQ_SHARED_STATE_T *local; +- VCHIQ_HEADER_T *header; +- +- local = state->local; +- +- if ((VCHIQ_MSG_TYPE(msgid) != VCHIQ_MSG_RESUME) && +- (mutex_lock_interruptible(&state->sync_mutex) != 0)) +- return VCHIQ_RETRY; +- +- remote_event_wait(&local->sync_release); +- +- rmb(); +- +- header = (VCHIQ_HEADER_T *)SLOT_DATA_FROM_INDEX(state, +- local->slot_sync); +- +- { +- int oldmsgid = header->msgid; +- if (oldmsgid != VCHIQ_MSGID_PADDING) +- vchiq_log_error(vchiq_core_log_level, +- "%d: qms - msgid %x, not PADDING", +- state->id, oldmsgid); +- } +- +- if (service) { +- int i, pos; +- +- vchiq_log_info(vchiq_sync_log_level, +- "%d: qms %s@%x,%x (%d->%d)", state->id, +- msg_type_str(VCHIQ_MSG_TYPE(msgid)), +- (unsigned int)header, size, +- VCHIQ_MSG_SRCPORT(msgid), +- VCHIQ_MSG_DSTPORT(msgid)); +- +- for (i = 0, pos = 0; i < (unsigned int)count; +- pos += elements[i++].size) +- if (elements[i].size) { +- if (vchiq_copy_from_user +- (header->data + pos, elements[i].data, +- (size_t) elements[i].size) != +- VCHIQ_SUCCESS) { +- mutex_unlock(&state->sync_mutex); +- VCHIQ_SERVICE_STATS_INC(service, +- error_count); +- return VCHIQ_ERROR; +- } +- if (i == 0) { +- if (vchiq_sync_log_level >= +- VCHIQ_LOG_TRACE) +- vchiq_log_dump_mem("Sent Sync", +- 0, header->data + pos, +- min(64, +- elements[0].size)); +- } +- } +- +- VCHIQ_SERVICE_STATS_INC(service, ctrl_tx_count); +- VCHIQ_SERVICE_STATS_ADD(service, ctrl_tx_bytes, size); +- } else { +- vchiq_log_info(vchiq_sync_log_level, +- "%d: qms %s@%x,%x (%d->%d)", state->id, +- msg_type_str(VCHIQ_MSG_TYPE(msgid)), +- (unsigned int)header, size, +- VCHIQ_MSG_SRCPORT(msgid), +- VCHIQ_MSG_DSTPORT(msgid)); +- if (size != 0) { +- WARN_ON(!((count == 1) && (size == elements[0].size))); +- memcpy(header->data, elements[0].data, +- elements[0].size); +- } +- VCHIQ_STATS_INC(state, ctrl_tx_count); +- } +- +- header->size = size; +- header->msgid = msgid; +- +- if (vchiq_sync_log_level >= VCHIQ_LOG_TRACE) { +- int svc_fourcc; +- +- svc_fourcc = service +- ? service->base.fourcc +- : VCHIQ_MAKE_FOURCC('?', '?', '?', '?'); +- +- vchiq_log_trace(vchiq_sync_log_level, +- "Sent Sync Msg %s(%u) to %c%c%c%c s:%u d:%d len:%d", +- msg_type_str(VCHIQ_MSG_TYPE(msgid)), +- VCHIQ_MSG_TYPE(msgid), +- VCHIQ_FOURCC_AS_4CHARS(svc_fourcc), +- VCHIQ_MSG_SRCPORT(msgid), +- VCHIQ_MSG_DSTPORT(msgid), +- size); +- } +- +- /* Make sure the new header is visible to the peer. */ +- wmb(); +- +- remote_event_signal(&state->remote->sync_trigger); +- +- if (VCHIQ_MSG_TYPE(msgid) != VCHIQ_MSG_PAUSE) +- mutex_unlock(&state->sync_mutex); +- +- return VCHIQ_SUCCESS; ++ return VCHIQ_SUCCESS; + } + + static inline void + claim_slot(VCHIQ_SLOT_INFO_T *slot) + { +- slot->use_count++; ++ slot->use_count++; + } + + static void +-release_slot(VCHIQ_STATE_T *state, VCHIQ_SLOT_INFO_T *slot_info, +- VCHIQ_HEADER_T *header, VCHIQ_SERVICE_T *service) ++release_slot(VCHIQ_STATE_T *state, VCHIQ_SLOT_INFO_T *slot_info) + { +- int release_count; ++ int release_count; ++ vcos_mutex_lock(&state->recycle_mutex); + +- mutex_lock(&state->recycle_mutex); ++ release_count = slot_info->release_count; ++ slot_info->release_count = ++release_count; + +- if (header) { +- int msgid = header->msgid; +- if (((msgid & VCHIQ_MSGID_CLAIMED) == 0) || +- (service && service->closing)) { +- mutex_unlock(&state->recycle_mutex); +- return; +- } +- +- /* Rewrite the message header to prevent a double +- ** release */ +- header->msgid = msgid & ~VCHIQ_MSGID_CLAIMED; +- } +- +- release_count = slot_info->release_count; +- slot_info->release_count = ++release_count; +- +- if (release_count == slot_info->use_count) { +- int slot_queue_recycle; +- /* Add to the freed queue */ +- +- /* A read barrier is necessary here to prevent speculative +- ** fetches of remote->slot_queue_recycle from overtaking the +- ** mutex. */ +- rmb(); +- +- slot_queue_recycle = state->remote->slot_queue_recycle; +- state->remote->slot_queue[slot_queue_recycle & +- VCHIQ_SLOT_QUEUE_MASK] = +- SLOT_INDEX_FROM_INFO(state, slot_info); +- state->remote->slot_queue_recycle = slot_queue_recycle + 1; +- vchiq_log_info(vchiq_core_log_level, +- "%d: release_slot %d - recycle->%x", +- state->id, SLOT_INDEX_FROM_INFO(state, slot_info), +- state->remote->slot_queue_recycle); +- +- /* A write barrier is necessary, but remote_event_signal +- ** contains one. */ +- remote_event_signal(&state->remote->recycle); +- } ++ if (release_count == slot_info->use_count) ++ { ++ int slot_queue_recycle; ++ /* Add to the freed queue */ ++ ++ /* A read barrier is necessary here to prevent speculative fetches of ++ remote->slot_queue_recycle from overtaking the mutex. */ ++ vcos_rmb(); ++ ++ slot_queue_recycle = state->remote->slot_queue_recycle; ++ state->remote->slot_queue[slot_queue_recycle & VCHIQ_SLOT_QUEUE_MASK] = ++ SLOT_INDEX_FROM_INFO(state, slot_info); ++ state->remote->slot_queue_recycle = slot_queue_recycle + 1; ++ vcos_log_info("%d: release_slot %d - recycle->%x", ++ state->id, SLOT_INDEX_FROM_INFO(state, slot_info), ++ state->remote->slot_queue_recycle); ++ ++ /* A write barrier is necessary, but remote_event_signal contains one. */ ++ remote_event_signal(&state->remote->recycle); ++ } + +- mutex_unlock(&state->recycle_mutex); ++ vcos_mutex_unlock(&state->recycle_mutex); + } + + /* Called by the slot handler - don't hold the bulk mutex */ + static VCHIQ_STATUS_T +-notify_bulks(VCHIQ_SERVICE_T *service, VCHIQ_BULK_QUEUE_T *queue, +- int retry_poll) ++notify_bulks(VCHIQ_SERVICE_T *service, VCHIQ_BULK_QUEUE_T *queue) + { +- VCHIQ_STATUS_T status = VCHIQ_SUCCESS; ++ VCHIQ_STATUS_T status = VCHIQ_SUCCESS; + +- vchiq_log_trace(vchiq_core_log_level, +- "%d: nb:%d %cx - p=%x rn=%x r=%x", +- service->state->id, service->localport, +- (queue == &service->bulk_tx) ? 't' : 'r', +- queue->process, queue->remote_notify, queue->remove); +- +- if (service->state->is_master) { +- while (queue->remote_notify != queue->process) { +- VCHIQ_BULK_T *bulk = +- &queue->bulks[BULK_INDEX(queue->remote_notify)]; +- int msgtype = (bulk->dir == VCHIQ_BULK_TRANSMIT) ? +- VCHIQ_MSG_BULK_RX_DONE : VCHIQ_MSG_BULK_TX_DONE; +- int msgid = VCHIQ_MAKE_MSG(msgtype, service->localport, +- service->remoteport); +- VCHIQ_ELEMENT_T element = { &bulk->actual, 4 }; +- /* Only reply to non-dummy bulk requests */ +- if (bulk->remote_data) { +- status = queue_message(service->state, NULL, +- msgid, &element, 1, 4, 0); +- if (status != VCHIQ_SUCCESS) +- break; +- } +- queue->remote_notify++; +- } +- } else { +- queue->remote_notify = queue->process; +- } +- +- if (status == VCHIQ_SUCCESS) { +- while (queue->remove != queue->remote_notify) { +- VCHIQ_BULK_T *bulk = +- &queue->bulks[BULK_INDEX(queue->remove)]; +- +- /* Only generate callbacks for non-dummy bulk +- ** requests, and non-terminated services */ +- if (bulk->data && service->instance) { +- if (bulk->actual != VCHIQ_BULK_ACTUAL_ABORTED) { +- if (bulk->dir == VCHIQ_BULK_TRANSMIT) { +- VCHIQ_SERVICE_STATS_INC(service, +- bulk_tx_count); +- VCHIQ_SERVICE_STATS_ADD(service, +- bulk_tx_bytes, +- bulk->actual); +- } else { +- VCHIQ_SERVICE_STATS_INC(service, +- bulk_rx_count); +- VCHIQ_SERVICE_STATS_ADD(service, +- bulk_rx_bytes, +- bulk->actual); +- } +- } else { +- VCHIQ_SERVICE_STATS_INC(service, +- bulk_aborted_count); +- } +- if (bulk->mode == VCHIQ_BULK_MODE_BLOCKING) { +- struct bulk_waiter *waiter; +- spin_lock(&bulk_waiter_spinlock); +- waiter = bulk->userdata; +- if (waiter) { +- waiter->actual = bulk->actual; +- up(&waiter->event); +- } +- spin_unlock(&bulk_waiter_spinlock); +- } else if (bulk->mode == +- VCHIQ_BULK_MODE_CALLBACK) { +- VCHIQ_REASON_T reason = (bulk->dir == +- VCHIQ_BULK_TRANSMIT) ? +- ((bulk->actual == +- VCHIQ_BULK_ACTUAL_ABORTED) ? +- VCHIQ_BULK_TRANSMIT_ABORTED : +- VCHIQ_BULK_TRANSMIT_DONE) : +- ((bulk->actual == +- VCHIQ_BULK_ACTUAL_ABORTED) ? +- VCHIQ_BULK_RECEIVE_ABORTED : +- VCHIQ_BULK_RECEIVE_DONE); +- status = make_service_callback(service, +- reason, NULL, bulk->userdata); +- if (status == VCHIQ_RETRY) +- break; +- status = VCHIQ_SUCCESS; +- } +- } +- +- queue->remove++; +- up(&service->bulk_remove_event); +- } +- if (!retry_poll) +- status = VCHIQ_SUCCESS; +- } +- +- if (status == VCHIQ_RETRY) +- request_poll(service->state, service, +- (queue == &service->bulk_tx) ? +- VCHIQ_POLL_TXNOTIFY : VCHIQ_POLL_RXNOTIFY); ++ vcos_log_trace("%d: nb:%d %cx - p=%x rn=%x r=%x", ++ service->state->id, service->localport, ++ (queue == &service->bulk_tx) ? 't' : 'r', ++ queue->process, queue->remote_notify, queue->remove); ++ ++ if (service->state->is_master) ++ { ++ while (queue->remote_notify != queue->process) ++ { ++ VCHIQ_BULK_T *bulk = &queue->bulks[BULK_INDEX(queue->remote_notify)]; ++ int msgtype = (bulk->dir == VCHIQ_BULK_TRANSMIT) ? ++ VCHIQ_MSG_BULK_RX_DONE : VCHIQ_MSG_BULK_TX_DONE; ++ int msgid = VCHIQ_MAKE_MSG(msgtype, service->localport, service->remoteport); ++ VCHIQ_ELEMENT_T element = { &bulk->actual, 4 }; ++ /* Only reply to non-dummy bulk requests */ ++ if (bulk->remote_data) ++ { ++ status = queue_message(service->state, NULL, msgid, &element, 1, 4, 0); ++ if (status != VCHIQ_SUCCESS) ++ break; ++ } ++ queue->remote_notify++; ++ } ++ } ++ else ++ { ++ queue->remote_notify = queue->process; ++ } ++ ++ if (status == VCHIQ_SUCCESS) ++ { ++ while (queue->remove != queue->remote_notify) ++ { ++ VCHIQ_BULK_T *bulk = &queue->bulks[BULK_INDEX(queue->remove)]; ++ ++ /* Only generate callbacks for non-dummy bulk requests */ ++ if (bulk->data) ++ { ++ if (bulk->actual != VCHIQ_BULK_ACTUAL_ABORTED) ++ { ++ if (bulk->dir == VCHIQ_BULK_TRANSMIT) ++ { ++ VCHIQ_SERVICE_STATS_INC(service, bulk_tx_count); ++ VCHIQ_SERVICE_STATS_ADD(service, bulk_tx_bytes, bulk->actual); ++ } ++ else ++ { ++ VCHIQ_SERVICE_STATS_INC(service, bulk_rx_count); ++ VCHIQ_SERVICE_STATS_ADD(service, bulk_rx_bytes, bulk->actual); ++ } ++ } ++ else ++ { ++ VCHIQ_SERVICE_STATS_INC(service, bulk_aborted_count); ++ } ++ if (bulk->mode == VCHIQ_BULK_MODE_BLOCKING) ++ { ++ BULK_WAITER_T *waiter = (BULK_WAITER_T *)bulk->userdata; ++ if (waiter) ++ { ++ waiter->actual = bulk->actual; ++ vcos_event_signal(&waiter->event); ++ } ++ } ++ else if (bulk->mode == VCHIQ_BULK_MODE_CALLBACK) ++ { ++ VCHIQ_REASON_T reason = (bulk->dir == VCHIQ_BULK_TRANSMIT) ? ++ ((bulk->actual == VCHIQ_BULK_ACTUAL_ABORTED) ? ++ VCHIQ_BULK_TRANSMIT_ABORTED : VCHIQ_BULK_TRANSMIT_DONE) : ++ ((bulk->actual == VCHIQ_BULK_ACTUAL_ABORTED) ? ++ VCHIQ_BULK_RECEIVE_ABORTED : VCHIQ_BULK_RECEIVE_DONE); ++ status = make_service_callback(service, reason, ++ NULL, bulk->userdata); ++ if (status == VCHIQ_RETRY) ++ break; ++ } ++ } ++ ++ queue->remove++; ++ vcos_event_signal(&service->bulk_remove_event); ++ } ++ } ++ ++ if (status != VCHIQ_SUCCESS) ++ request_poll(service->state, service, (queue == &service->bulk_tx) ? ++ VCHIQ_POLL_TXNOTIFY : VCHIQ_POLL_RXNOTIFY); + +- return status; ++ return status; + } + + /* Called by the slot handler thread */ + static void + poll_services(VCHIQ_STATE_T *state) + { +- int group, i; ++ int group, i; + +- for (group = 0; group < BITSET_SIZE(state->unused_service); group++) { +- uint32_t flags; +- flags = atomic_xchg(&state->poll_services[group], 0); +- for (i = 0; flags; i++) { +- if (flags & (1 << i)) { +- VCHIQ_SERVICE_T *service = +- find_service_by_port(state, +- (group<<5) + i); +- uint32_t service_flags; +- flags &= ~(1 << i); +- if (!service) +- continue; +- service_flags = +- atomic_xchg(&service->poll_flags, 0); +- if (service_flags & +- (1 << VCHIQ_POLL_TERMINATE)) { +- vchiq_log_info(vchiq_core_log_level, +- "%d: ps - terminate %d<->%d", +- state->id, service->localport, +- service->remoteport); +- if (vchiq_close_service_internal( +- service, 0/*!close_recvd*/) != +- VCHIQ_SUCCESS) +- request_poll(state, service, +- VCHIQ_POLL_TERMINATE); +- } +- if (service_flags & (1 << VCHIQ_POLL_TXNOTIFY)) +- notify_bulks(service, +- &service->bulk_tx, +- 1/*retry_poll*/); +- if (service_flags & (1 << VCHIQ_POLL_RXNOTIFY)) +- notify_bulks(service, +- &service->bulk_rx, +- 1/*retry_poll*/); +- unlock_service(service); +- } +- } +- } ++ for (group = 0; group < BITSET_SIZE(state->unused_service); group++) ++ { ++ uint32_t flags; ++ flags = vcos_atomic_flags_get_and_clear(&state->poll_services[group]); ++ for (i = 0; flags; i++) ++ { ++ if (flags & (1 << i)) ++ { ++ VCHIQ_SERVICE_T *service = state->services[(group<<5) + i]; ++ uint32_t service_flags = ++ vcos_atomic_flags_get_and_clear(&service->poll_flags); ++ if (service_flags & (1 << VCHIQ_POLL_TERMINATE)) ++ { ++ vcos_log_info("%d: ps - terminate %d<->%d", state->id, service->localport, service->remoteport); ++ if (vchiq_close_service_internal(service, 0/*!close_recvd*/) != VCHIQ_SUCCESS) ++ request_poll(state, service, VCHIQ_POLL_TERMINATE); ++ } ++ if (service_flags & (1 << VCHIQ_POLL_TXNOTIFY)) ++ notify_bulks(service, &service->bulk_tx); ++ if (service_flags & (1 << VCHIQ_POLL_RXNOTIFY)) ++ notify_bulks(service, &service->bulk_rx); ++ flags &= ~(1 << i); ++ } ++ } ++ } + } + + /* Called by the slot handler or application threads, holding the bulk mutex. */ + static int + resolve_bulks(VCHIQ_SERVICE_T *service, VCHIQ_BULK_QUEUE_T *queue) + { +- VCHIQ_STATE_T *state = service->state; +- int resolved = 0; ++ VCHIQ_STATE_T *state = service->state; ++ int resolved = 0; + +- while ((queue->process != queue->local_insert) && +- (queue->process != queue->remote_insert)) { +- VCHIQ_BULK_T *bulk = &queue->bulks[BULK_INDEX(queue->process)]; +- +- vchiq_log_trace(vchiq_core_log_level, +- "%d: rb:%d %cx - li=%x ri=%x p=%x", +- state->id, service->localport, +- (queue == &service->bulk_tx) ? 't' : 'r', +- queue->local_insert, queue->remote_insert, +- queue->process); +- +- WARN_ON(!((int)(queue->local_insert - queue->process) > 0)); +- WARN_ON(!((int)(queue->remote_insert - queue->process) > 0)); +- +- mutex_lock(&state->bulk_transfer_mutex); +- vchiq_transfer_bulk(bulk); +- mutex_unlock(&state->bulk_transfer_mutex); +- +- if (vchiq_core_msg_log_level >= VCHIQ_LOG_INFO) { +- const char *header = (queue == &service->bulk_tx) ? +- "Send Bulk to" : "Recv Bulk from"; +- if (bulk->actual != VCHIQ_BULK_ACTUAL_ABORTED) +- vchiq_log_info(vchiq_core_msg_log_level, +- "%s %c%c%c%c d:%d len:%d %x<->%x", +- header, +- VCHIQ_FOURCC_AS_4CHARS( +- service->base.fourcc), +- service->remoteport, +- bulk->size, +- (unsigned int)bulk->data, +- (unsigned int)bulk->remote_data); +- else +- vchiq_log_info(vchiq_core_msg_log_level, +- "%s %c%c%c%c d:%d ABORTED - tx len:%d," +- " rx len:%d %x<->%x", +- header, +- VCHIQ_FOURCC_AS_4CHARS( +- service->base.fourcc), +- service->remoteport, +- bulk->size, +- bulk->remote_size, +- (unsigned int)bulk->data, +- (unsigned int)bulk->remote_data); +- } +- +- vchiq_complete_bulk(bulk); +- queue->process++; +- resolved++; +- } +- return resolved; ++ while ((queue->process != queue->local_insert) && ++ (queue->process != queue->remote_insert)) ++ { ++ VCHIQ_BULK_T *bulk = &queue->bulks[BULK_INDEX(queue->process)]; ++ ++ vcos_log_trace("%d: rb:%d %cx - li=%x ri=%x p=%x", ++ state->id, service->localport, ++ (queue == &service->bulk_tx) ? 't' : 'r', ++ queue->local_insert, queue->remote_insert, ++ queue->process); ++ ++ vcos_assert((int)(queue->local_insert - queue->process) > 0); ++ vcos_assert((int)(queue->remote_insert - queue->process) > 0); ++ vchiq_transfer_bulk(bulk); ++ ++ if (vcos_is_log_enabled( &vchiq_core_msg_log_category, VCOS_LOG_INFO)) ++ { ++ const char *header = (queue == &service->bulk_tx) ? ++ "Send Bulk to" : "Recv Bulk from"; ++ if (bulk->actual != VCHIQ_BULK_ACTUAL_ABORTED) ++ vcos_log_impl( &vchiq_core_msg_log_category, ++ VCOS_LOG_INFO, ++ "%s %c%c%c%c d:%d len:%d %x<->%x", ++ header, ++ VCHIQ_FOURCC_AS_4CHARS(service->base.fourcc), ++ service->remoteport, ++ bulk->size, ++ (unsigned int)bulk->data, ++ (unsigned int)bulk->remote_data ); ++ else ++ vcos_log_impl( &vchiq_core_msg_log_category, ++ VCOS_LOG_INFO, ++ "%s %c%c%c%c d:%d ABORTED - tx len:%d, rx len:%d %x<->%x", ++ header, ++ VCHIQ_FOURCC_AS_4CHARS(service->base.fourcc), ++ service->remoteport, ++ bulk->size, ++ bulk->remote_size, ++ (unsigned int)bulk->data, ++ (unsigned int)bulk->remote_data ); ++ } ++ ++ vchiq_complete_bulk(bulk); ++ queue->process++; ++ resolved++; ++ } ++ return resolved; + } + + /* Called with the bulk_mutex held */ + static void + abort_outstanding_bulks(VCHIQ_SERVICE_T *service, VCHIQ_BULK_QUEUE_T *queue) + { +- int is_tx = (queue == &service->bulk_tx); +- vchiq_log_trace(vchiq_core_log_level, +- "%d: aob:%d %cx - li=%x ri=%x p=%x", +- service->state->id, service->localport, is_tx ? 't' : 'r', +- queue->local_insert, queue->remote_insert, queue->process); +- +- WARN_ON(!((int)(queue->local_insert - queue->process) >= 0)); +- WARN_ON(!((int)(queue->remote_insert - queue->process) >= 0)); +- +- while ((queue->process != queue->local_insert) || +- (queue->process != queue->remote_insert)) { +- VCHIQ_BULK_T *bulk = &queue->bulks[BULK_INDEX(queue->process)]; +- +- if (queue->process == queue->remote_insert) { +- /* fabricate a matching dummy bulk */ +- bulk->remote_data = NULL; +- bulk->remote_size = 0; +- queue->remote_insert++; +- } +- +- if (queue->process != queue->local_insert) { +- vchiq_complete_bulk(bulk); +- +- vchiq_log_info(vchiq_core_msg_log_level, +- "%s %c%c%c%c d:%d ABORTED - tx len:%d, " +- "rx len:%d", +- is_tx ? "Send Bulk to" : "Recv Bulk from", +- VCHIQ_FOURCC_AS_4CHARS(service->base.fourcc), +- service->remoteport, +- bulk->size, +- bulk->remote_size); +- } else { +- /* fabricate a matching dummy bulk */ +- bulk->data = NULL; +- bulk->size = 0; +- bulk->actual = VCHIQ_BULK_ACTUAL_ABORTED; +- bulk->dir = is_tx ? VCHIQ_BULK_TRANSMIT : +- VCHIQ_BULK_RECEIVE; +- queue->local_insert++; +- } ++ int is_tx = (queue == &service->bulk_tx); ++ vcos_log_trace("%d: aob:%d %cx - li=%x ri=%x p=%x", ++ service->state->id, service->localport, is_tx ? 't' : 'r', ++ queue->local_insert, queue->remote_insert, queue->process); ++ ++ vcos_assert((int)(queue->local_insert - queue->process) >= 0); ++ vcos_assert((int)(queue->remote_insert - queue->process) >= 0); ++ ++ while ((queue->process != queue->local_insert) || ++ (queue->process != queue->remote_insert)) ++ { ++ VCHIQ_BULK_T *bulk = &queue->bulks[BULK_INDEX(queue->process)]; ++ ++ if (queue->process == queue->remote_insert) ++ { ++ /* fabricate a matching dummy bulk */ ++ bulk->remote_data = NULL; ++ bulk->remote_size = 0; ++ queue->remote_insert++; ++ } ++ ++ if (queue->process != queue->local_insert) ++ { ++ vchiq_complete_bulk(bulk); ++ ++ if (vcos_is_log_enabled( &vchiq_core_msg_log_category, VCOS_LOG_INFO)) ++ { ++ vcos_log_impl( &vchiq_core_msg_log_category, ++ VCOS_LOG_INFO, ++ "%s %c%c%c%c d:%d ABORTED - tx len:%d, rx len:%d", ++ is_tx ? "Send Bulk to" : "Recv Bulk from", ++ VCHIQ_FOURCC_AS_4CHARS(service->base.fourcc), ++ service->remoteport, ++ bulk->size, ++ bulk->remote_size ); ++ } ++ } ++ else ++ { ++ /* fabricate a matching dummy bulk */ ++ bulk->data = NULL; ++ bulk->size = 0; ++ bulk->actual = VCHIQ_BULK_ACTUAL_ABORTED; ++ bulk->dir = is_tx ? VCHIQ_BULK_TRANSMIT : VCHIQ_BULK_RECEIVE; ++ queue->local_insert++; ++ } + +- queue->process++; +- } ++ queue->process++; ++ } + } + +-/* Called from the slot handler thread */ + static void + pause_bulks(VCHIQ_STATE_T *state) + { +- if (unlikely(atomic_inc_return(&pause_bulks_count) != 1)) { +- WARN_ON_ONCE(1); +- atomic_set(&pause_bulks_count, 1); +- return; +- } ++ int i; + +- /* Block bulk transfers from all services */ +- mutex_lock(&state->bulk_transfer_mutex); ++ /* Block bulk transfers from all services */ ++ for (i = 0; i < state->unused_service; i++) ++ { ++ VCHIQ_SERVICE_T *service = state->services[i]; ++ if (!service || (service->srvstate != VCHIQ_SRVSTATE_OPEN)) ++ continue; ++ ++ vcos_log_trace("locking bulk_mutex for service %d", i); ++ vcos_mutex_lock(&service->bulk_mutex); ++ } + } + +-/* Called from the slot handler thread */ + static void + resume_bulks(VCHIQ_STATE_T *state) + { +- if (unlikely(atomic_dec_return(&pause_bulks_count) != 0)) { +- WARN_ON_ONCE(1); +- atomic_set(&pause_bulks_count, 0); +- return; +- } ++ int i; + +- /* Allow bulk transfers from all services */ +- mutex_unlock(&state->bulk_transfer_mutex); +-} +- +-static int +-parse_open(VCHIQ_STATE_T *state, VCHIQ_HEADER_T *header) +-{ +- VCHIQ_SERVICE_T *service = NULL; +- int msgid, size; +- int type; +- unsigned int localport, remoteport; +- +- msgid = header->msgid; +- size = header->size; +- type = VCHIQ_MSG_TYPE(msgid); +- localport = VCHIQ_MSG_DSTPORT(msgid); +- remoteport = VCHIQ_MSG_SRCPORT(msgid); +- if (size == sizeof(struct vchiq_open_payload)) { +- const struct vchiq_open_payload *payload = +- (struct vchiq_open_payload *)header->data; +- unsigned int fourcc; +- +- fourcc = payload->fourcc; +- vchiq_log_info(vchiq_core_log_level, +- "%d: prs OPEN@%x (%d->'%c%c%c%c')", +- state->id, (unsigned int)header, +- localport, +- VCHIQ_FOURCC_AS_4CHARS(fourcc)); +- +- service = get_listening_service(state, fourcc); +- +- if (service) { +- /* A matching service exists */ +- short version = payload->version; +- short version_min = payload->version_min; +- if ((service->version < version_min) || +- (version < service->version_min)) { +- /* Version mismatch */ +- vchiq_loud_error_header(); +- vchiq_loud_error("%d: service %d (%c%c%c%c) " +- "version mismatch - local (%d, min %d)" +- " vs. remote (%d, min %d)", +- state->id, service->localport, +- VCHIQ_FOURCC_AS_4CHARS(fourcc), +- service->version, service->version_min, +- version, version_min); +- vchiq_loud_error_footer(); +- goto fail_open; +- } +- if (service->srvstate == VCHIQ_SRVSTATE_LISTENING) { +- /* Acknowledge the OPEN */ +- if (service->sync) { +- if (queue_message_sync(state, NULL, +- VCHIQ_MAKE_MSG( +- VCHIQ_MSG_OPENACK, +- service->localport, +- remoteport), +- NULL, 0, 0, 0) == VCHIQ_RETRY) +- goto bail_not_ready; +- } else { +- if (queue_message(state, NULL, +- VCHIQ_MAKE_MSG( +- VCHIQ_MSG_OPENACK, +- service->localport, +- remoteport), +- NULL, 0, 0, 0) == VCHIQ_RETRY) +- goto bail_not_ready; +- } +- +- /* The service is now open */ +- vchiq_set_service_state(service, +- service->sync ? VCHIQ_SRVSTATE_OPENSYNC +- : VCHIQ_SRVSTATE_OPEN); +- } +- +- service->remoteport = remoteport; +- service->client_id = ((int *)header->data)[1]; +- if (make_service_callback(service, VCHIQ_SERVICE_OPENED, +- NULL, NULL) == VCHIQ_RETRY) { +- /* Bail out if not ready */ +- service->remoteport = VCHIQ_PORT_FREE; +- goto bail_not_ready; +- } +- +- /* Success - the message has been dealt with */ +- unlock_service(service); +- return 1; +- } +- } +- +-fail_open: +- /* No available service, or an invalid request - send a CLOSE */ +- if (queue_message(state, NULL, +- VCHIQ_MAKE_MSG(VCHIQ_MSG_CLOSE, 0, VCHIQ_MSG_SRCPORT(msgid)), +- NULL, 0, 0, 0) == VCHIQ_RETRY) +- goto bail_not_ready; +- +- unlock_service(service); +- +- return 1; +- +-bail_not_ready: +- unlock_service(service); +- +- return 0; ++ /* Poll all services in case any bulk transfers have been ++ deferred */ ++ for (i = 0; i < state->unused_service; i++) ++ { ++ VCHIQ_SERVICE_T *service = state->services[i]; ++ if (!service || (service->srvstate != VCHIQ_SRVSTATE_OPEN)) ++ continue; ++ ++ if (resolve_bulks(service, &service->bulk_tx)) ++ request_poll(state, service, VCHIQ_POLL_TXNOTIFY); ++ if (resolve_bulks(service, &service->bulk_rx)) ++ request_poll(state, service, VCHIQ_POLL_RXNOTIFY); ++ vcos_log_trace("unlocking bulk_mutex for service %d", i); ++ vcos_mutex_unlock(&service->bulk_mutex); ++ } + } + + /* Called by the slot handler thread */ + static void + parse_rx_slots(VCHIQ_STATE_T *state) + { +- VCHIQ_SHARED_STATE_T *remote = state->remote; +- VCHIQ_SERVICE_T *service = NULL; +- int tx_pos; +- DEBUG_INITIALISE(state->local) +- +- tx_pos = remote->tx_pos; +- +- while (state->rx_pos != tx_pos) { +- VCHIQ_HEADER_T *header; +- int msgid, size; +- int type; +- unsigned int localport, remoteport; +- +- DEBUG_TRACE(PARSE_LINE); +- if (!state->rx_data) { +- int rx_index; +- WARN_ON(!((state->rx_pos & VCHIQ_SLOT_MASK) == 0)); +- rx_index = remote->slot_queue[ +- SLOT_QUEUE_INDEX_FROM_POS(state->rx_pos) & +- VCHIQ_SLOT_QUEUE_MASK]; +- state->rx_data = (char *)SLOT_DATA_FROM_INDEX(state, +- rx_index); +- state->rx_info = SLOT_INFO_FROM_INDEX(state, rx_index); +- +- /* Initialise use_count to one, and increment +- ** release_count at the end of the slot to avoid +- ** releasing the slot prematurely. */ +- state->rx_info->use_count = 1; +- state->rx_info->release_count = 0; +- } +- +- header = (VCHIQ_HEADER_T *)(state->rx_data + +- (state->rx_pos & VCHIQ_SLOT_MASK)); +- DEBUG_VALUE(PARSE_HEADER, (int)header); +- msgid = header->msgid; +- DEBUG_VALUE(PARSE_MSGID, msgid); +- size = header->size; +- type = VCHIQ_MSG_TYPE(msgid); +- localport = VCHIQ_MSG_DSTPORT(msgid); +- remoteport = VCHIQ_MSG_SRCPORT(msgid); +- +- if (type != VCHIQ_MSG_DATA) +- VCHIQ_STATS_INC(state, ctrl_rx_count); +- +- switch (type) { +- case VCHIQ_MSG_OPENACK: +- case VCHIQ_MSG_CLOSE: +- case VCHIQ_MSG_DATA: +- case VCHIQ_MSG_BULK_RX: +- case VCHIQ_MSG_BULK_TX: +- case VCHIQ_MSG_BULK_RX_DONE: +- case VCHIQ_MSG_BULK_TX_DONE: +- service = find_service_by_port(state, localport); +- if (!service) { +- vchiq_log_error(vchiq_core_log_level, +- "%d: prs %s@%x (%d->%d) - " +- "invalid/closed service %d", +- state->id, msg_type_str(type), +- (unsigned int)header, +- remoteport, localport, localport); +- goto skip_message; +- } +- default: +- break; +- } +- +- if (vchiq_core_msg_log_level >= VCHIQ_LOG_INFO) { +- int svc_fourcc; +- +- svc_fourcc = service +- ? service->base.fourcc +- : VCHIQ_MAKE_FOURCC('?', '?', '?', '?'); +- vchiq_log_info(vchiq_core_msg_log_level, +- "Rcvd Msg %s(%u) from %c%c%c%c s:%d d:%d " +- "len:%d", +- msg_type_str(type), type, +- VCHIQ_FOURCC_AS_4CHARS(svc_fourcc), +- remoteport, localport, size); +- if (size > 0) +- vchiq_log_dump_mem("Rcvd", 0, header->data, +- min(64, size)); +- } +- +- if (((unsigned int)header & VCHIQ_SLOT_MASK) + calc_stride(size) +- > VCHIQ_SLOT_SIZE) { +- vchiq_log_error(vchiq_core_log_level, +- "header %x (msgid %x) - size %x too big for " +- "slot", +- (unsigned int)header, (unsigned int)msgid, +- (unsigned int)size); +- WARN(1, "oversized for slot\n"); +- } +- +- switch (type) { +- case VCHIQ_MSG_OPEN: +- WARN_ON(!(VCHIQ_MSG_DSTPORT(msgid) == 0)); +- if (!parse_open(state, header)) +- goto bail_not_ready; +- break; +- case VCHIQ_MSG_OPENACK: +- vchiq_log_info(vchiq_core_log_level, +- "%d: prs OPENACK@%x (%d->%d)", +- state->id, (unsigned int)header, +- remoteport, localport); +- if (service->srvstate == +- VCHIQ_SRVSTATE_OPENING) { +- service->remoteport = remoteport; +- vchiq_set_service_state(service, +- VCHIQ_SRVSTATE_OPEN); +- up(&service->remove_event); +- } else +- vchiq_log_error(vchiq_core_log_level, +- "OPENACK received in state %s", +- srvstate_names[service->srvstate]); +- break; +- case VCHIQ_MSG_CLOSE: +- WARN_ON(size != 0); /* There should be no data */ +- +- vchiq_log_info(vchiq_core_log_level, +- "%d: prs CLOSE@%x (%d->%d)", +- state->id, (unsigned int)header, +- remoteport, localport); +- +- if ((service->remoteport != remoteport) && +- VCHIQ_PORT_IS_VALID(service->remoteport)) { +- /* This could be from a client which hadn't yet +- ** received the OPENACK - look for the +- ** connected service */ +- service = get_connected_service(state, +- remoteport); +- if (!service) +- break; +- } +- +- mark_service_closing(service); +- +- if (vchiq_close_service_internal(service, +- 1/*close_recvd*/) == VCHIQ_RETRY) +- goto bail_not_ready; +- +- vchiq_log_info(vchiq_core_log_level, +- "Close Service %c%c%c%c s:%u d:%d", +- VCHIQ_FOURCC_AS_4CHARS(service->base.fourcc), +- service->localport, +- service->remoteport); +- break; +- case VCHIQ_MSG_DATA: +- vchiq_log_trace(vchiq_core_log_level, +- "%d: prs DATA@%x,%x (%d->%d)", +- state->id, (unsigned int)header, size, +- remoteport, localport); +- +- if ((service->remoteport == remoteport) +- && (service->srvstate == +- VCHIQ_SRVSTATE_OPEN)) { +- header->msgid = msgid | VCHIQ_MSGID_CLAIMED; +- claim_slot(state->rx_info); +- DEBUG_TRACE(PARSE_LINE); +- if (make_service_callback(service, +- VCHIQ_MESSAGE_AVAILABLE, header, +- NULL) == VCHIQ_RETRY) { +- DEBUG_TRACE(PARSE_LINE); +- goto bail_not_ready; +- } +- VCHIQ_SERVICE_STATS_INC(service, ctrl_rx_count); +- VCHIQ_SERVICE_STATS_ADD(service, ctrl_rx_bytes, +- size); +- } else { +- VCHIQ_STATS_INC(state, error_count); +- } +- break; +- case VCHIQ_MSG_CONNECT: +- vchiq_log_info(vchiq_core_log_level, +- "%d: prs CONNECT@%x", +- state->id, (unsigned int)header); +- up(&state->connect); +- break; +- case VCHIQ_MSG_BULK_RX: +- case VCHIQ_MSG_BULK_TX: { +- VCHIQ_BULK_QUEUE_T *queue; +- WARN_ON(!state->is_master); +- queue = (type == VCHIQ_MSG_BULK_RX) ? +- &service->bulk_tx : &service->bulk_rx; +- if ((service->remoteport == remoteport) +- && (service->srvstate == +- VCHIQ_SRVSTATE_OPEN)) { +- VCHIQ_BULK_T *bulk; +- int resolved; +- +- WARN_ON(!(queue->remote_insert < queue->remove + +- VCHIQ_NUM_SERVICE_BULKS)); +- bulk = &queue->bulks[ +- BULK_INDEX(queue->remote_insert)]; +- bulk->remote_data = +- (void *)((int *)header->data)[0]; +- bulk->remote_size = ((int *)header->data)[1]; +- wmb(); +- +- vchiq_log_info(vchiq_core_log_level, +- "%d: prs %s@%x (%d->%d) %x@%x", +- state->id, msg_type_str(type), +- (unsigned int)header, +- remoteport, localport, +- bulk->remote_size, +- (unsigned int)bulk->remote_data); +- +- queue->remote_insert++; +- +- if (state->conn_state != +- VCHIQ_CONNSTATE_CONNECTED) +- break; +- +- DEBUG_TRACE(PARSE_LINE); +- if (mutex_lock_interruptible( +- &service->bulk_mutex) != 0) { +- DEBUG_TRACE(PARSE_LINE); +- goto bail_not_ready; +- } +- DEBUG_TRACE(PARSE_LINE); +- resolved = resolve_bulks(service, queue); +- mutex_unlock(&service->bulk_mutex); +- if (resolved) +- notify_bulks(service, queue, +- 1/*retry_poll*/); +- } +- } break; +- case VCHIQ_MSG_BULK_RX_DONE: +- case VCHIQ_MSG_BULK_TX_DONE: +- WARN_ON(state->is_master); +- if ((service->remoteport == remoteport) +- && (service->srvstate != +- VCHIQ_SRVSTATE_FREE)) { +- VCHIQ_BULK_QUEUE_T *queue; +- VCHIQ_BULK_T *bulk; +- +- queue = (type == VCHIQ_MSG_BULK_RX_DONE) ? +- &service->bulk_rx : &service->bulk_tx; +- +- if ((int)(queue->remote_insert - +- queue->local_insert) >= 0) { +- vchiq_log_error(vchiq_core_log_level, +- "%d: prs %s@%x (%d->%d) " +- "unexpected", +- state->id, msg_type_str(type), +- (unsigned int)header, +- remoteport, localport); +- break; +- } +- +- BUG_ON(queue->process == queue->local_insert); +- BUG_ON(queue->process != queue->remote_insert); +- +- bulk = &queue->bulks[ +- BULK_INDEX(queue->remote_insert)]; +- bulk->actual = *(int *)header->data; +- queue->remote_insert++; +- +- vchiq_log_info(vchiq_core_log_level, +- "%d: prs %s@%x (%d->%d) %x@%x", +- state->id, msg_type_str(type), +- (unsigned int)header, +- remoteport, localport, +- bulk->actual, (unsigned int)bulk->data); +- +- vchiq_log_trace(vchiq_core_log_level, +- "%d: prs:%d %cx li=%x ri=%x p=%x", +- state->id, localport, +- (type == VCHIQ_MSG_BULK_RX_DONE) ? +- 'r' : 't', +- queue->local_insert, +- queue->remote_insert, queue->process); +- +- DEBUG_TRACE(PARSE_LINE); +- if (mutex_lock_interruptible( +- &service->bulk_mutex) != 0) { +- DEBUG_TRACE(PARSE_LINE); +- goto bail_not_ready; +- } +- DEBUG_TRACE(PARSE_LINE); +- WARN_ON(queue->process == queue->local_insert); +- vchiq_complete_bulk(bulk); +- queue->process++; +- mutex_unlock(&service->bulk_mutex); +- DEBUG_TRACE(PARSE_LINE); +- notify_bulks(service, queue, 1/*retry_poll*/); +- DEBUG_TRACE(PARSE_LINE); +- } +- break; +- case VCHIQ_MSG_PADDING: +- vchiq_log_trace(vchiq_core_log_level, +- "%d: prs PADDING@%x,%x", +- state->id, (unsigned int)header, size); +- break; +- case VCHIQ_MSG_PAUSE: +- /* If initiated, signal the application thread */ +- vchiq_log_trace(vchiq_core_log_level, +- "%d: prs PAUSE@%x,%x", +- state->id, (unsigned int)header, size); +- if (state->conn_state == VCHIQ_CONNSTATE_PAUSED) { +- vchiq_log_error(vchiq_core_log_level, +- "%d: PAUSE received in state PAUSED", +- state->id); +- break; +- } +- if (state->conn_state != VCHIQ_CONNSTATE_PAUSE_SENT) { +- /* Send a PAUSE in response */ +- if (queue_message(state, NULL, +- VCHIQ_MAKE_MSG(VCHIQ_MSG_PAUSE, 0, 0), +- NULL, 0, 0, 0) == VCHIQ_RETRY) +- goto bail_not_ready; +- if (state->is_master) +- pause_bulks(state); +- } +- /* At this point slot_mutex is held */ +- vchiq_set_conn_state(state, VCHIQ_CONNSTATE_PAUSED); +- vchiq_platform_paused(state); +- break; +- case VCHIQ_MSG_RESUME: +- vchiq_log_trace(vchiq_core_log_level, +- "%d: prs RESUME@%x,%x", +- state->id, (unsigned int)header, size); +- /* Release the slot mutex */ +- mutex_unlock(&state->slot_mutex); +- if (state->is_master) +- resume_bulks(state); +- vchiq_set_conn_state(state, VCHIQ_CONNSTATE_CONNECTED); +- vchiq_platform_resumed(state); +- break; +- +- case VCHIQ_MSG_REMOTE_USE: +- vchiq_on_remote_use(state); +- break; +- case VCHIQ_MSG_REMOTE_RELEASE: +- vchiq_on_remote_release(state); +- break; +- case VCHIQ_MSG_REMOTE_USE_ACTIVE: +- vchiq_on_remote_use_active(state); +- break; +- +- default: +- vchiq_log_error(vchiq_core_log_level, +- "%d: prs invalid msgid %x@%x,%x", +- state->id, msgid, (unsigned int)header, size); +- WARN(1, "invalid message\n"); +- break; +- } +- +-skip_message: +- if (service) { +- unlock_service(service); +- service = NULL; +- } +- +- state->rx_pos += calc_stride(size); +- +- DEBUG_TRACE(PARSE_LINE); +- /* Perform some housekeeping when the end of the slot is +- ** reached. */ +- if ((state->rx_pos & VCHIQ_SLOT_MASK) == 0) { +- /* Remove the extra reference count. */ +- release_slot(state, state->rx_info, NULL, NULL); +- state->rx_data = NULL; +- } +- } +- +-bail_not_ready: +- if (service) +- unlock_service(service); ++ VCHIQ_SHARED_STATE_T *remote = state->remote; ++ int tx_pos; ++ DEBUG_INITIALISE(state->local) ++ ++ tx_pos = remote->tx_pos; ++ ++ while (state->rx_pos != tx_pos) { ++ VCHIQ_SERVICE_T *service = NULL; ++ VCHIQ_HEADER_T *header; ++ int msgid, size; ++ int type; ++ unsigned int localport, remoteport; ++ ++ DEBUG_TRACE(PARSE_LINE); ++ if (!state->rx_data) ++ { ++ int rx_index; ++ vcos_assert((state->rx_pos & VCHIQ_SLOT_MASK) == 0); ++ rx_index = remote->slot_queue[SLOT_QUEUE_INDEX_FROM_POS(state->rx_pos) & VCHIQ_SLOT_QUEUE_MASK]; ++ state->rx_data = (char *)SLOT_DATA_FROM_INDEX(state, rx_index); ++ state->rx_info = SLOT_INFO_FROM_INDEX(state, rx_index); ++ ++ /* Initialise use_count to one, and increment release_count at the end ++ of the slot to avoid releasing the slot prematurely. */ ++ state->rx_info->use_count = 1; ++ state->rx_info->release_count = 0; ++ } ++ ++ header = (VCHIQ_HEADER_T *)(state->rx_data + (state->rx_pos & VCHIQ_SLOT_MASK)); ++ DEBUG_VALUE(PARSE_HEADER, (int)header); ++ msgid = header->msgid; ++ DEBUG_VALUE(PARSE_MSGID, msgid); ++ size = header->size; ++ type = VCHIQ_MSG_TYPE(msgid); ++ localport = VCHIQ_MSG_DSTPORT(msgid); ++ remoteport = VCHIQ_MSG_SRCPORT(msgid); ++ ++ if (type != VCHIQ_MSG_DATA) ++ { ++ VCHIQ_STATS_INC(state, ctrl_rx_count); ++ } ++ ++ switch (type) ++ { ++ case VCHIQ_MSG_OPENACK: ++ case VCHIQ_MSG_CLOSE: ++ case VCHIQ_MSG_DATA: ++ case VCHIQ_MSG_BULK_RX: ++ case VCHIQ_MSG_BULK_TX: ++ case VCHIQ_MSG_BULK_RX_DONE: ++ case VCHIQ_MSG_BULK_TX_DONE: ++ if (localport <= VCHIQ_PORT_MAX) ++ { ++ service = state->services[localport]; ++ if (service && (service->srvstate == VCHIQ_SRVSTATE_FREE)) ++ service = NULL; ++ } ++ if (!service) ++ { ++ vcos_log_error( ++ "%d: prs %s@%x (%d->%d) - invalid/closed service %d", ++ state->id, msg_type_str(type), (unsigned int)header, ++ remoteport, localport, localport); ++ goto skip_message; ++ } ++ default: ++ break; ++ } ++ ++ if ( vcos_is_log_enabled( &vchiq_core_msg_log_category, VCOS_LOG_INFO)) ++ { ++ int svc_fourcc; ++ ++ svc_fourcc = service ++ ? service->base.fourcc ++ : VCHIQ_MAKE_FOURCC('?','?','?','?'); ++ vcos_log_impl( &vchiq_core_msg_log_category, ++ VCOS_LOG_INFO, ++ "Rcvd Msg %s(%u) from %c%c%c%c s:%d d:%d len:%d", ++ msg_type_str(type), type, ++ VCHIQ_FOURCC_AS_4CHARS(svc_fourcc), ++ remoteport, localport, size ); ++ if (size > 0) { ++ vcos_log_dump_mem( &vchiq_core_msg_log_category, ++ "Rcvd", 0, header->data, ++ vcos_min( 64, size )); ++ } ++ } ++ ++ if (((unsigned int)header & VCHIQ_SLOT_MASK) + calc_stride(size) > VCHIQ_SLOT_SIZE) ++ { ++ vcos_log_error("header %x (msgid %x) - size %x too big for slot", ++ (unsigned int)header, (unsigned int)msgid, (unsigned int)size); ++ vcos_assert(0); ++ } ++ ++ switch (type) { ++ case VCHIQ_MSG_OPEN: ++ vcos_assert(VCHIQ_MSG_DSTPORT(msgid) == 0); ++ if (vcos_verify(size == sizeof(VCHIQ_OPEN_PAYLOAD_T))) { ++ const VCHIQ_OPEN_PAYLOAD_T *payload = (VCHIQ_OPEN_PAYLOAD_T *)header->data; ++ unsigned int fourcc; ++ ++ fourcc = payload->fourcc; ++ vcos_log_info("%d: prs OPEN@%x (%d->'%c%c%c%c')", ++ state->id, (unsigned int)header, ++ localport, ++ VCHIQ_FOURCC_AS_4CHARS(fourcc)); ++ ++ service = get_listening_service(state, fourcc); ++ ++ if (service) ++ { ++ /* A matching service exists */ ++ short version = payload->version; ++ short version_min = payload->version_min; ++ if ((service->version < version_min) || ++ (version < service->version_min)) ++ { ++ /* Version mismatch */ ++ vcos_log_error("%d: service %d (%c%c%c%c) version mismatch -" ++ " local (%d, min %d) vs. remote (%d, min %d)", ++ state->id, service->localport, ++ VCHIQ_FOURCC_AS_4CHARS(fourcc), ++ service->version, service->version_min, ++ version, version_min); ++ goto fail_open; ++ } ++ if (service->srvstate == VCHIQ_SRVSTATE_LISTENING) ++ { ++ /* Acknowledge the OPEN */ ++ if (queue_message(state, NULL, ++ VCHIQ_MAKE_MSG(VCHIQ_MSG_OPENACK, service->localport, remoteport), ++ NULL, 0, 0, 0) == VCHIQ_RETRY) ++ return; /* Bail out if not ready */ ++ ++ /* The service is now open */ ++ vchiq_set_service_state(service, VCHIQ_SRVSTATE_OPEN); ++ } ++ ++ service->remoteport = remoteport; ++ service->client_id = ((int *)header->data)[1]; ++ if (make_service_callback(service, VCHIQ_SERVICE_OPENED, ++ NULL, NULL) == VCHIQ_RETRY) ++ { ++ /* Bail out if not ready */ ++ service->remoteport = VCHIQ_PORT_FREE; ++ return; ++ } ++ ++ /* Break out, and skip the failure handling */ ++ break; ++ } ++ } ++ fail_open: ++ /* No available service, or an invalid request - send a CLOSE */ ++ if (queue_message(state, NULL, ++ VCHIQ_MAKE_MSG(VCHIQ_MSG_CLOSE, 0, VCHIQ_MSG_SRCPORT(msgid)), ++ NULL, 0, 0, 0) == VCHIQ_RETRY) ++ return; /* Bail out if not ready */ ++ break; ++ case VCHIQ_MSG_OPENACK: ++ { ++ vcos_log_info("%d: prs OPENACK@%x (%d->%d)", ++ state->id, (unsigned int)header, ++ remoteport, localport); ++ if (service->srvstate == VCHIQ_SRVSTATE_OPENING) { ++ service->remoteport = remoteport; ++ vchiq_set_service_state(service, ++ VCHIQ_SRVSTATE_OPEN); ++ vcos_event_signal(&service->remove_event); ++ } ++ } ++ break; ++ case VCHIQ_MSG_CLOSE: ++ { ++ vcos_assert(size == 0); /* There should be no data */ ++ ++ vcos_log_info("%d: prs CLOSE@%x (%d->%d)", ++ state->id, (unsigned int)header, ++ remoteport, localport); ++ ++ if ((service->remoteport != remoteport) && ++ VCHIQ_PORT_IS_VALID(service->remoteport)) { ++ /* This could be from a client which hadn't yet received ++ the OPENACK - look for the connected service */ ++ service = get_connected_service(state, remoteport); ++ if (!service) ++ break; ++ } ++ ++ if (vchiq_close_service_internal(service, ++ 1/*close_recvd*/) == VCHIQ_RETRY) ++ return; /* Bail out if not ready */ ++ ++ if (vcos_is_log_enabled( &vchiq_core_msg_log_category, VCOS_LOG_INFO)) ++ { ++ vcos_log_impl( &vchiq_core_msg_log_category, ++ VCOS_LOG_INFO, ++ "Close Service %c%c%c%c s:%u d:%d", ++ VCHIQ_FOURCC_AS_4CHARS(service->base.fourcc), ++ service->localport, ++ service->remoteport ); ++ } ++ } ++ break; ++ case VCHIQ_MSG_DATA: ++ { ++ vcos_log_trace("%d: prs DATA@%x,%x (%d->%d)", ++ state->id, (unsigned int)header, size, ++ remoteport, localport); ++ ++ if ((service->remoteport == remoteport) ++ && (service->srvstate == ++ VCHIQ_SRVSTATE_OPEN)) { ++ header->msgid = msgid | VCHIQ_MSGID_CLAIMED; ++ claim_slot(state->rx_info); ++ DEBUG_TRACE(PARSE_LINE); ++ if (make_service_callback(service, ++ VCHIQ_MESSAGE_AVAILABLE, header, ++ NULL) == VCHIQ_RETRY) ++ { ++ DEBUG_TRACE(PARSE_LINE); ++ return; /* Bail out if not ready */ ++ } ++ VCHIQ_SERVICE_STATS_INC(service, ctrl_rx_count); ++ VCHIQ_SERVICE_STATS_ADD(service, ctrl_rx_bytes, size); ++ } ++ else ++ { ++ VCHIQ_STATS_INC(state, error_count); ++ } ++ } ++ break; ++ case VCHIQ_MSG_CONNECT: ++ vcos_log_info("%d: prs CONNECT@%x", ++ state->id, (unsigned int)header); ++ vcos_event_signal(&state->connect); ++ break; ++ case VCHIQ_MSG_BULK_RX: ++ case VCHIQ_MSG_BULK_TX: ++ { ++ VCHIQ_BULK_QUEUE_T *queue; ++ vcos_assert(state->is_master); ++ queue = (type == VCHIQ_MSG_BULK_RX) ? ++ &service->bulk_tx : &service->bulk_rx; ++ if ((service->remoteport == remoteport) ++ && (service->srvstate == ++ VCHIQ_SRVSTATE_OPEN)) ++ { ++ VCHIQ_BULK_T *bulk; ++ int resolved; ++ ++ vcos_assert(queue->remote_insert < queue->remove + ++ VCHIQ_NUM_SERVICE_BULKS); ++ bulk = &queue->bulks[BULK_INDEX(queue->remote_insert)]; ++ bulk->remote_data = (void *)((int *)header->data)[0]; ++ bulk->remote_size = ((int *)header->data)[1]; ++ ++ vcos_log_info("%d: prs %s@%x (%d->%d) %x@%x", ++ state->id, msg_type_str(type), ++ (unsigned int)header, ++ remoteport, localport, ++ bulk->remote_size, ++ (unsigned int)bulk->remote_data); ++ ++ queue->remote_insert++; ++ ++ if (state->conn_state != VCHIQ_CONNSTATE_CONNECTED) ++ break; ++ ++ DEBUG_TRACE(PARSE_LINE); ++ if (vcos_mutex_lock(&service->bulk_mutex) != VCOS_SUCCESS) ++ { ++ DEBUG_TRACE(PARSE_LINE); ++ return; ++ } ++ DEBUG_TRACE(PARSE_LINE); ++ resolved = resolve_bulks(service, queue); ++ vcos_mutex_unlock(&service->bulk_mutex); ++ if (resolved) ++ notify_bulks(service, queue); ++ } ++ } ++ break; ++ case VCHIQ_MSG_BULK_RX_DONE: ++ case VCHIQ_MSG_BULK_TX_DONE: ++ { ++ vcos_assert(!state->is_master); ++ if ((service->remoteport == remoteport) ++ && (service->srvstate != ++ VCHIQ_SRVSTATE_FREE)) { ++ VCHIQ_BULK_QUEUE_T *queue; ++ VCHIQ_BULK_T *bulk; ++ ++ queue = (type == VCHIQ_MSG_BULK_RX_DONE) ? ++ &service->bulk_rx : &service->bulk_tx; ++ ++ bulk = &queue->bulks[BULK_INDEX(queue->process)]; ++ bulk->actual = *(int *)header->data; ++ ++ vcos_log_info("%d: prs %s@%x (%d->%d) %x@%x", ++ state->id, msg_type_str(type), ++ (unsigned int)header, ++ remoteport, localport, ++ bulk->actual, (unsigned int)bulk->data); ++ ++ vcos_log_trace("%d: prs:%d %cx li=%x ri=%x p=%x", ++ state->id, localport, ++ (type == VCHIQ_MSG_BULK_RX_DONE) ? 'r' : 't', ++ queue->local_insert, ++ queue->remote_insert, queue->process); ++ ++ DEBUG_TRACE(PARSE_LINE); ++ if (vcos_mutex_lock(&service->bulk_mutex) != VCOS_SUCCESS) ++ { ++ DEBUG_TRACE(PARSE_LINE); ++ return; ++ } ++ DEBUG_TRACE(PARSE_LINE); ++ vcos_assert(queue->process != queue->local_insert); ++ vchiq_complete_bulk(bulk); ++ queue->process++; ++ vcos_mutex_unlock(&service->bulk_mutex); ++ DEBUG_TRACE(PARSE_LINE); ++ notify_bulks(service, queue); ++ DEBUG_TRACE(PARSE_LINE); ++ } ++ } ++ break; ++ case VCHIQ_MSG_PADDING: ++ vcos_log_trace("%d: prs PADDING@%x,%x", ++ state->id, (unsigned int)header, size); ++ break; ++ case VCHIQ_MSG_PAUSE: ++ /* If initiated, signal the application thread */ ++ vcos_log_trace("%d: prs PAUSE@%x,%x", ++ state->id, (unsigned int)header, size); ++ if (state->conn_state != VCHIQ_CONNSTATE_PAUSE_SENT) ++ { ++ /* Send a PAUSE in response */ ++ if (queue_message(state, NULL, ++ VCHIQ_MAKE_MSG(VCHIQ_MSG_PAUSE, 0, 0), ++ NULL, 0, 0, 0) == VCHIQ_RETRY) ++ return; /* Bail out if not ready */ ++ if (state->is_master) ++ pause_bulks(state); ++ } ++ /* At this point slot_mutex is held */ ++ vchiq_set_conn_state(state, VCHIQ_CONNSTATE_PAUSED); ++ vchiq_platform_paused(state); ++ break; ++ case VCHIQ_MSG_RESUME: ++ vcos_log_trace("%d: prs RESUME@%x,%x", ++ state->id, (unsigned int)header, size); ++ /* Release the slot mutex */ ++ vcos_mutex_unlock(&state->slot_mutex); ++ if (state->is_master) ++ resume_bulks(state); ++ vchiq_set_conn_state(state, VCHIQ_CONNSTATE_CONNECTED); ++ vchiq_platform_resumed(state); ++ break; ++ ++ case VCHIQ_MSG_REMOTE_USE: ++ vchiq_on_remote_use(state); ++ break; ++ case VCHIQ_MSG_REMOTE_RELEASE: ++ vchiq_on_remote_release(state); ++ break; ++ case VCHIQ_MSG_REMOTE_USE_ACTIVE: ++ vchiq_on_remote_use_active(state); ++ break; ++ ++ default: ++ vcos_log_error("%d: prs invalid msgid %x@%x,%x", ++ state->id, msgid, (unsigned int)header, size); ++ vcos_assert(0); ++ break; ++ } ++ ++ skip_message: ++ state->rx_pos += calc_stride(size); ++ ++ DEBUG_TRACE(PARSE_LINE); ++ /* Perform some housekeeping when the end of the slot is reached. */ ++ if ((state->rx_pos & VCHIQ_SLOT_MASK) == 0) ++ { ++ /* Remove the extra reference count. */ ++ release_slot(state, state->rx_info); ++ state->rx_data = NULL; ++ } ++ } + } + + /* Called by the slot handler thread */ +-static int ++static void * + slot_handler_func(void *v) + { +- VCHIQ_STATE_T *state = (VCHIQ_STATE_T *) v; +- VCHIQ_SHARED_STATE_T *local = state->local; +- DEBUG_INITIALISE(local) +- +- while (1) { +- DEBUG_COUNT(SLOT_HANDLER_COUNT); +- DEBUG_TRACE(SLOT_HANDLER_LINE); +- remote_event_wait(&local->trigger); +- +- rmb(); +- +- DEBUG_TRACE(SLOT_HANDLER_LINE); +- if (state->poll_needed) { +- /* Check if we need to suspend - may change our +- * conn_state */ +- vchiq_platform_check_suspend(state); +- +- state->poll_needed = 0; +- +- /* Handle service polling and other rare conditions here +- ** out of the mainline code */ +- switch (state->conn_state) { +- case VCHIQ_CONNSTATE_CONNECTED: +- /* Poll the services as requested */ +- poll_services(state); +- break; +- +- case VCHIQ_CONNSTATE_PAUSING: +- if (state->is_master) +- pause_bulks(state); +- if (queue_message(state, NULL, +- VCHIQ_MAKE_MSG(VCHIQ_MSG_PAUSE, 0, 0), +- NULL, 0, 0, 0) != VCHIQ_RETRY) { +- vchiq_set_conn_state(state, +- VCHIQ_CONNSTATE_PAUSE_SENT); +- } else { +- if (state->is_master) +- resume_bulks(state); +- /* Retry later */ +- state->poll_needed = 1; +- } +- break; +- +- case VCHIQ_CONNSTATE_PAUSED: +- vchiq_platform_resume(state); +- break; +- +- case VCHIQ_CONNSTATE_RESUMING: +- if (queue_message(state, NULL, +- VCHIQ_MAKE_MSG(VCHIQ_MSG_RESUME, 0, 0), +- NULL, 0, 0, 0) != VCHIQ_RETRY) { +- if (state->is_master) +- resume_bulks(state); +- vchiq_set_conn_state(state, +- VCHIQ_CONNSTATE_CONNECTED); +- vchiq_platform_resumed(state); +- } else { +- /* This should really be impossible, +- ** since the PAUSE should have flushed +- ** through outstanding messages. */ +- vchiq_log_error(vchiq_core_log_level, +- "Failed to send RESUME " +- "message"); +- BUG(); +- } +- break; +- default: +- break; +- } +- +- +- } +- +- DEBUG_TRACE(SLOT_HANDLER_LINE); +- parse_rx_slots(state); +- } +- return 0; ++ VCHIQ_STATE_T *state = (VCHIQ_STATE_T *) v; ++ VCHIQ_SHARED_STATE_T *local = state->local; ++ DEBUG_INITIALISE(local) ++ ++ while (1) { ++ DEBUG_COUNT(SLOT_HANDLER_COUNT); ++ DEBUG_TRACE(SLOT_HANDLER_LINE); ++ remote_event_wait(&local->trigger); ++ ++ vcos_rmb(); ++ ++ DEBUG_TRACE(SLOT_HANDLER_LINE); ++ if (state->poll_needed) ++ { ++ state->poll_needed = 0; ++ ++ /* Handle service polling and other rare conditions here out ++ of the mainline code */ ++ switch (state->conn_state) ++ { ++ case VCHIQ_CONNSTATE_CONNECTED: ++ /* Poll the services as requested */ ++ poll_services(state); ++ break; ++ ++ case VCHIQ_CONNSTATE_PAUSING: ++ if (queue_message(state, NULL, ++ VCHIQ_MAKE_MSG(VCHIQ_MSG_PAUSE, 0, 0), NULL, 0, 0, 0) ++ != VCHIQ_RETRY) ++ { ++ if (state->is_master) ++ pause_bulks(state); ++ vchiq_set_conn_state(state, VCHIQ_CONNSTATE_PAUSE_SENT); ++ } ++ else ++ { ++ state->poll_needed = 1; /* Retry later */ ++ } ++ break; ++ ++ case VCHIQ_CONNSTATE_RESUMING: ++ if (queue_message(state, NULL, ++ VCHIQ_MAKE_MSG(VCHIQ_MSG_RESUME, 0, 0), NULL, 0, 0, 0) ++ != VCHIQ_RETRY) ++ { ++ if (state->is_master) ++ resume_bulks(state); ++ vchiq_set_conn_state(state, VCHIQ_CONNSTATE_CONNECTED); ++ vchiq_platform_resumed(state); ++ } ++ else ++ { ++ /* This should really be impossible, since the PAUSE should ++ have flushed through outstanding messages. */ ++ vcos_log_error("Failed to send RESUME message"); ++ vcos_demand(0); ++ } ++ break; ++ default: ++ break; ++ } ++ } ++ ++ DEBUG_TRACE(SLOT_HANDLER_LINE); ++ parse_rx_slots(state); ++ } ++ return NULL; + } + + + /* Called by the recycle thread */ +-static int ++static void * + recycle_func(void *v) + { +- VCHIQ_STATE_T *state = (VCHIQ_STATE_T *) v; +- VCHIQ_SHARED_STATE_T *local = state->local; ++ VCHIQ_STATE_T *state = (VCHIQ_STATE_T *) v; ++ VCHIQ_SHARED_STATE_T *local = state->local; + +- while (1) { +- remote_event_wait(&local->recycle); ++ while (1) { ++ remote_event_wait(&local->recycle); + +- process_free_queue(state); +- } +- return 0; +-} +- +- +-/* Called by the sync thread */ +-static int +-sync_func(void *v) +-{ +- VCHIQ_STATE_T *state = (VCHIQ_STATE_T *) v; +- VCHIQ_SHARED_STATE_T *local = state->local; +- VCHIQ_HEADER_T *header = (VCHIQ_HEADER_T *)SLOT_DATA_FROM_INDEX(state, +- state->remote->slot_sync); +- +- while (1) { +- VCHIQ_SERVICE_T *service; +- int msgid, size; +- int type; +- unsigned int localport, remoteport; +- +- remote_event_wait(&local->sync_trigger); +- +- rmb(); +- +- msgid = header->msgid; +- size = header->size; +- type = VCHIQ_MSG_TYPE(msgid); +- localport = VCHIQ_MSG_DSTPORT(msgid); +- remoteport = VCHIQ_MSG_SRCPORT(msgid); +- +- service = find_service_by_port(state, localport); +- +- if (!service) { +- vchiq_log_error(vchiq_sync_log_level, +- "%d: sf %s@%x (%d->%d) - " +- "invalid/closed service %d", +- state->id, msg_type_str(type), +- (unsigned int)header, +- remoteport, localport, localport); +- release_message_sync(state, header); +- continue; +- } +- +- if (vchiq_sync_log_level >= VCHIQ_LOG_TRACE) { +- int svc_fourcc; +- +- svc_fourcc = service +- ? service->base.fourcc +- : VCHIQ_MAKE_FOURCC('?', '?', '?', '?'); +- vchiq_log_trace(vchiq_sync_log_level, +- "Rcvd Msg %s from %c%c%c%c s:%d d:%d len:%d", +- msg_type_str(type), +- VCHIQ_FOURCC_AS_4CHARS(svc_fourcc), +- remoteport, localport, size); +- if (size > 0) +- vchiq_log_dump_mem("Rcvd", 0, header->data, +- min(64, size)); +- } +- +- switch (type) { +- case VCHIQ_MSG_OPENACK: +- vchiq_log_info(vchiq_sync_log_level, +- "%d: sf OPENACK@%x (%d->%d)", +- state->id, (unsigned int)header, +- remoteport, localport); +- if (service->srvstate == VCHIQ_SRVSTATE_OPENING) { +- service->remoteport = remoteport; +- vchiq_set_service_state(service, +- VCHIQ_SRVSTATE_OPENSYNC); +- up(&service->remove_event); +- } +- release_message_sync(state, header); +- break; +- +- case VCHIQ_MSG_DATA: +- vchiq_log_trace(vchiq_sync_log_level, +- "%d: sf DATA@%x,%x (%d->%d)", +- state->id, (unsigned int)header, size, +- remoteport, localport); +- +- if ((service->remoteport == remoteport) && +- (service->srvstate == +- VCHIQ_SRVSTATE_OPENSYNC)) { +- if (make_service_callback(service, +- VCHIQ_MESSAGE_AVAILABLE, header, +- NULL) == VCHIQ_RETRY) +- vchiq_log_error(vchiq_sync_log_level, +- "synchronous callback to " +- "service %d returns " +- "VCHIQ_RETRY", +- localport); +- } +- break; +- +- default: +- vchiq_log_error(vchiq_sync_log_level, +- "%d: sf unexpected msgid %x@%x,%x", +- state->id, msgid, (unsigned int)header, size); +- release_message_sync(state, header); +- break; +- } ++ vcos_mutex_lock(&state->slot_mutex); + +- unlock_service(service); +- } ++ process_free_queue(state); + +- return 0; ++ vcos_mutex_unlock(&state->slot_mutex); ++ } ++ return NULL; + } + + + static void + init_bulk_queue(VCHIQ_BULK_QUEUE_T *queue) + { +- queue->local_insert = 0; +- queue->remote_insert = 0; +- queue->process = 0; +- queue->remote_notify = 0; +- queue->remove = 0; +-} +- +- +-inline const char * +-get_conn_state_name(VCHIQ_CONNSTATE_T conn_state) +-{ +- return conn_state_names[conn_state]; ++ queue->local_insert = 0; ++ queue->remote_insert = 0; ++ queue->process = 0; ++ queue->remote_notify = 0; ++ queue->remove = 0; + } + +- + VCHIQ_SLOT_ZERO_T * + vchiq_init_slots(void *mem_base, int mem_size) + { +- int mem_align = (VCHIQ_SLOT_SIZE - (int)mem_base) & VCHIQ_SLOT_MASK; +- VCHIQ_SLOT_ZERO_T *slot_zero = +- (VCHIQ_SLOT_ZERO_T *)((char *)mem_base + mem_align); +- int num_slots = (mem_size - mem_align)/VCHIQ_SLOT_SIZE; +- int first_data_slot = VCHIQ_SLOT_ZERO_SLOTS; +- +- /* Ensure there is enough memory to run an absolutely minimum system */ +- num_slots -= first_data_slot; +- +- if (num_slots < 4) { +- vchiq_log_error(vchiq_core_log_level, +- "vchiq_init_slots - insufficient memory %x bytes", +- mem_size); +- return NULL; +- } +- +- memset(slot_zero, 0, sizeof(VCHIQ_SLOT_ZERO_T)); +- +- slot_zero->magic = VCHIQ_MAGIC; +- slot_zero->version = VCHIQ_VERSION; +- slot_zero->version_min = VCHIQ_VERSION_MIN; +- slot_zero->slot_zero_size = sizeof(VCHIQ_SLOT_ZERO_T); +- slot_zero->slot_size = VCHIQ_SLOT_SIZE; +- slot_zero->max_slots = VCHIQ_MAX_SLOTS; +- slot_zero->max_slots_per_side = VCHIQ_MAX_SLOTS_PER_SIDE; +- +- slot_zero->master.slot_sync = first_data_slot; +- slot_zero->master.slot_first = first_data_slot + 1; +- slot_zero->master.slot_last = first_data_slot + (num_slots/2) - 1; +- slot_zero->slave.slot_sync = first_data_slot + (num_slots/2); +- slot_zero->slave.slot_first = first_data_slot + (num_slots/2) + 1; +- slot_zero->slave.slot_last = first_data_slot + num_slots - 1; +- +- return slot_zero; +-} +- +-VCHIQ_STATUS_T +-vchiq_init_state(VCHIQ_STATE_T *state, VCHIQ_SLOT_ZERO_T *slot_zero, +- int is_master) +-{ +- VCHIQ_SHARED_STATE_T *local; +- VCHIQ_SHARED_STATE_T *remote; +- VCHIQ_STATUS_T status; +- char threadname[10]; +- static int id; +- int i; +- +- vchiq_log_warning(vchiq_core_log_level, +- "%s: slot_zero = 0x%08lx, is_master = %d", +- __func__, (unsigned long)slot_zero, is_master); +- +- /* Check the input configuration */ +- +- if (slot_zero->magic != VCHIQ_MAGIC) { +- vchiq_loud_error_header(); +- vchiq_loud_error("Invalid VCHIQ magic value found."); +- vchiq_loud_error("slot_zero=%x: magic=%x (expected %x)", +- (unsigned int)slot_zero, slot_zero->magic, VCHIQ_MAGIC); +- vchiq_loud_error_footer(); +- return VCHIQ_ERROR; +- } +- +- if (slot_zero->version < VCHIQ_VERSION_MIN) { +- vchiq_loud_error_header(); +- vchiq_loud_error("Incompatible VCHIQ versions found."); +- vchiq_loud_error("slot_zero=%x: VideoCore version=%d " +- "(minimum %d)", +- (unsigned int)slot_zero, slot_zero->version, +- VCHIQ_VERSION_MIN); +- vchiq_loud_error("Restart with a newer VideoCore image."); +- vchiq_loud_error_footer(); +- return VCHIQ_ERROR; +- } +- +- if (VCHIQ_VERSION < slot_zero->version_min) { +- vchiq_loud_error_header(); +- vchiq_loud_error("Incompatible VCHIQ versions found."); +- vchiq_loud_error("slot_zero=%x: version=%d (VideoCore " +- "minimum %d)", +- (unsigned int)slot_zero, VCHIQ_VERSION, +- slot_zero->version_min); +- vchiq_loud_error("Restart with a newer kernel."); +- vchiq_loud_error_footer(); +- return VCHIQ_ERROR; +- } +- +- if ((slot_zero->slot_zero_size != sizeof(VCHIQ_SLOT_ZERO_T)) || +- (slot_zero->slot_size != VCHIQ_SLOT_SIZE) || +- (slot_zero->max_slots != VCHIQ_MAX_SLOTS) || +- (slot_zero->max_slots_per_side != VCHIQ_MAX_SLOTS_PER_SIDE)) { +- vchiq_loud_error_header(); +- if (slot_zero->slot_zero_size != sizeof(VCHIQ_SLOT_ZERO_T)) +- vchiq_loud_error("slot_zero=%x: slot_zero_size=%x " +- "(expected %x)", +- (unsigned int)slot_zero, +- slot_zero->slot_zero_size, +- sizeof(VCHIQ_SLOT_ZERO_T)); +- if (slot_zero->slot_size != VCHIQ_SLOT_SIZE) +- vchiq_loud_error("slot_zero=%x: slot_size=%d " +- "(expected %d", +- (unsigned int)slot_zero, slot_zero->slot_size, +- VCHIQ_SLOT_SIZE); +- if (slot_zero->max_slots != VCHIQ_MAX_SLOTS) +- vchiq_loud_error("slot_zero=%x: max_slots=%d " +- "(expected %d)", +- (unsigned int)slot_zero, slot_zero->max_slots, +- VCHIQ_MAX_SLOTS); +- if (slot_zero->max_slots_per_side != VCHIQ_MAX_SLOTS_PER_SIDE) +- vchiq_loud_error("slot_zero=%x: max_slots_per_side=%d " +- "(expected %d)", +- (unsigned int)slot_zero, +- slot_zero->max_slots_per_side, +- VCHIQ_MAX_SLOTS_PER_SIDE); +- vchiq_loud_error_footer(); +- return VCHIQ_ERROR; +- } +- +- if (is_master) { +- local = &slot_zero->master; +- remote = &slot_zero->slave; +- } else { +- local = &slot_zero->slave; +- remote = &slot_zero->master; +- } +- +- if (local->initialised) { +- vchiq_loud_error_header(); +- if (remote->initialised) +- vchiq_loud_error("local state has already been " +- "initialised"); +- else +- vchiq_loud_error("master/slave mismatch - two %ss", +- is_master ? "master" : "slave"); +- vchiq_loud_error_footer(); +- return VCHIQ_ERROR; +- } +- +- memset(state, 0, sizeof(VCHIQ_STATE_T)); +- +- state->id = id++; +- state->is_master = is_master; +- +- /* +- initialize shared state pointers +- */ +- +- state->local = local; +- state->remote = remote; +- state->slot_data = (VCHIQ_SLOT_T *)slot_zero; +- +- /* +- initialize events and mutexes +- */ +- +- sema_init(&state->connect, 0); +- mutex_init(&state->mutex); +- sema_init(&state->trigger_event, 0); +- sema_init(&state->recycle_event, 0); +- sema_init(&state->sync_trigger_event, 0); +- sema_init(&state->sync_release_event, 0); +- +- mutex_init(&state->slot_mutex); +- mutex_init(&state->recycle_mutex); +- mutex_init(&state->sync_mutex); +- mutex_init(&state->bulk_transfer_mutex); +- +- sema_init(&state->slot_available_event, 0); +- sema_init(&state->slot_remove_event, 0); +- sema_init(&state->data_quota_event, 0); +- +- state->slot_queue_available = 0; +- +- for (i = 0; i < VCHIQ_MAX_SERVICES; i++) { +- VCHIQ_SERVICE_QUOTA_T *service_quota = +- &state->service_quotas[i]; +- sema_init(&service_quota->quota_event, 0); +- } +- +- for (i = local->slot_first; i <= local->slot_last; i++) { +- local->slot_queue[state->slot_queue_available++] = i; +- up(&state->slot_available_event); +- } +- +- state->default_slot_quota = state->slot_queue_available/2; +- state->default_message_quota = +- min((unsigned short)(state->default_slot_quota * 256), +- (unsigned short)~0); +- +- state->previous_data_index = -1; +- state->data_use_count = 0; +- state->data_quota = state->slot_queue_available - 1; +- +- local->trigger.event = &state->trigger_event; +- remote_event_create(&local->trigger); +- local->tx_pos = 0; +- +- local->recycle.event = &state->recycle_event; +- remote_event_create(&local->recycle); +- local->slot_queue_recycle = state->slot_queue_available; +- +- local->sync_trigger.event = &state->sync_trigger_event; +- remote_event_create(&local->sync_trigger); +- +- local->sync_release.event = &state->sync_release_event; +- remote_event_create(&local->sync_release); +- +- /* At start-of-day, the slot is empty and available */ +- ((VCHIQ_HEADER_T *)SLOT_DATA_FROM_INDEX(state, local->slot_sync))->msgid +- = VCHIQ_MSGID_PADDING; +- remote_event_signal_local(&local->sync_release); +- +- local->debug[DEBUG_ENTRIES] = DEBUG_MAX; +- +- status = vchiq_platform_init_state(state); +- +- /* +- bring up slot handler thread +- */ +- snprintf(threadname, sizeof(threadname), "VCHIQ-%d", state->id); +- state->slot_handler_thread = kthread_create(&slot_handler_func, +- (void *)state, +- threadname); +- +- if (state->slot_handler_thread == NULL) { +- vchiq_loud_error_header(); +- vchiq_loud_error("couldn't create thread %s", threadname); +- vchiq_loud_error_footer(); +- return VCHIQ_ERROR; +- } +- set_user_nice(state->slot_handler_thread, -19); +- wake_up_process(state->slot_handler_thread); +- +- snprintf(threadname, sizeof(threadname), "VCHIQr-%d", state->id); +- state->recycle_thread = kthread_create(&recycle_func, +- (void *)state, +- threadname); +- if (state->recycle_thread == NULL) { +- vchiq_loud_error_header(); +- vchiq_loud_error("couldn't create thread %s", threadname); +- vchiq_loud_error_footer(); +- return VCHIQ_ERROR; +- } +- set_user_nice(state->recycle_thread, -19); +- wake_up_process(state->recycle_thread); +- +- snprintf(threadname, sizeof(threadname), "VCHIQs-%d", state->id); +- state->sync_thread = kthread_create(&sync_func, +- (void *)state, +- threadname); +- if (state->sync_thread == NULL) { +- vchiq_loud_error_header(); +- vchiq_loud_error("couldn't create thread %s", threadname); +- vchiq_loud_error_footer(); +- return VCHIQ_ERROR; +- } +- set_user_nice(state->sync_thread, -20); +- wake_up_process(state->sync_thread); ++ int mem_align = (VCHIQ_SLOT_SIZE - (int)mem_base) & VCHIQ_SLOT_MASK; ++ VCHIQ_SLOT_ZERO_T *slot_zero = (VCHIQ_SLOT_ZERO_T *)((char *)mem_base + mem_align); ++ int num_slots = (mem_size - mem_align)/VCHIQ_SLOT_SIZE; ++ int first_data_slot = VCHIQ_SLOT_ZERO_SLOTS; ++ ++ /* Ensure there is enough memory to run an absolutely minimum system */ ++ num_slots -= first_data_slot; ++ ++ if (num_slots < 4) ++ { ++ vcos_log_error("vchiq_init_slots - insufficient memory %x bytes", mem_size); ++ return NULL; ++ } ++ ++ memset(slot_zero, 0, sizeof(VCHIQ_SLOT_ZERO_T)); ++ ++ slot_zero->magic = VCHIQ_MAGIC; ++ slot_zero->version = VCHIQ_VERSION; ++ slot_zero->version_min = VCHIQ_VERSION_MIN; ++ slot_zero->slot_zero_size = sizeof(VCHIQ_SLOT_ZERO_T); ++ slot_zero->slot_size = VCHIQ_SLOT_SIZE; ++ slot_zero->max_slots = VCHIQ_MAX_SLOTS; ++ slot_zero->max_slots_per_side = VCHIQ_MAX_SLOTS_PER_SIDE; ++ ++ slot_zero->master.slot_first = first_data_slot; ++ slot_zero->slave.slot_first = first_data_slot + (num_slots/2); ++ slot_zero->master.slot_last = slot_zero->slave.slot_first - 1; ++ slot_zero->slave.slot_last = first_data_slot + num_slots - 1; ++ ++ return slot_zero; ++} ++ ++VCHIQ_STATUS_T ++vchiq_init_state(VCHIQ_STATE_T *state, VCHIQ_SLOT_ZERO_T *slot_zero, int is_master) ++{ ++ VCHIQ_SHARED_STATE_T *local; ++ VCHIQ_SHARED_STATE_T *remote; ++ VCOS_THREAD_ATTR_T attrs; ++ VCHIQ_STATUS_T status; ++ char threadname[10]; ++ static int id = 0; ++ int i; ++ ++ vcos_log_set_level(&vchiq_core_log_category, vchiq_default_core_log_level); ++ vcos_log_set_level(&vchiq_core_msg_log_category, vchiq_default_core_msg_log_level); ++ vcos_log_register("vchiq_core", &vchiq_core_log_category); ++ vcos_log_register("vchiq_core_msg", &vchiq_core_msg_log_category); ++ ++ vcos_log_warn( "%s: slot_zero = 0x%08lx, is_master = %d", __func__, (unsigned long)slot_zero, is_master ); ++ ++ /* Check the input configuration */ ++ ++ if (slot_zero->magic != VCHIQ_MAGIC) ++ { ++ vcos_log_error("slot_zero=%x: magic=%x (expected %x)", ++ (unsigned int)slot_zero, slot_zero->magic, VCHIQ_MAGIC); ++ return VCHIQ_ERROR; ++ } ++ ++ if (slot_zero->version < VCHIQ_VERSION_MIN) ++ { ++ vcos_log_error("slot_zero=%x: peer_version=%x (minimum %x)", ++ (unsigned int)slot_zero, slot_zero->version, VCHIQ_VERSION_MIN); ++ return VCHIQ_ERROR; ++ } ++ ++ if (VCHIQ_VERSION < slot_zero->version_min) ++ { ++ vcos_log_error("slot_zero=%x: version=%x (peer minimum %x)", ++ (unsigned int)slot_zero, VCHIQ_VERSION, slot_zero->version_min); ++ return VCHIQ_ERROR; ++ } ++ ++ if (slot_zero->slot_zero_size != sizeof(VCHIQ_SLOT_ZERO_T)) ++ { ++ vcos_log_error("slot_zero=%x: slot_zero_size=%x (expected %x)", ++ (unsigned int)slot_zero, slot_zero->slot_zero_size, sizeof(VCHIQ_SLOT_ZERO_T)); ++ return VCHIQ_ERROR; ++ } ++ ++ if (slot_zero->slot_size != VCHIQ_SLOT_SIZE) ++ { ++ vcos_log_error("slot_zero=%x: slot_size=%d (expected %d", ++ (unsigned int)slot_zero, slot_zero->slot_size, VCHIQ_SLOT_SIZE); ++ return VCHIQ_ERROR; ++ } ++ ++ if (slot_zero->max_slots != VCHIQ_MAX_SLOTS) ++ { ++ vcos_log_error("slot_zero=%x: max_slots=%d (expected %d)", ++ (unsigned int)slot_zero, slot_zero->max_slots, VCHIQ_MAX_SLOTS); ++ return VCHIQ_ERROR; ++ } ++ ++ if (slot_zero->max_slots_per_side != VCHIQ_MAX_SLOTS_PER_SIDE) ++ { ++ vcos_log_error("slot_zero=%x: max_slots_per_side=%d (expected %d)", ++ (unsigned int)slot_zero, slot_zero->max_slots_per_side, ++ VCHIQ_MAX_SLOTS_PER_SIDE); ++ return VCHIQ_ERROR; ++ } ++ ++ if (is_master) ++ { ++ local = &slot_zero->master; ++ remote = &slot_zero->slave; ++ } ++ else ++ { ++ local = &slot_zero->slave; ++ remote = &slot_zero->master; ++ } ++ ++ if (local->initialised) ++ { ++ if (remote->initialised) ++ vcos_log_error("vchiq: FATAL: local state has already been initialised"); ++ else ++ vcos_log_error("vchiq: FATAL: master/slave mismatch - two %ss", is_master ? "master" : "slave"); ++ return VCHIQ_ERROR; ++ } ++ ++ memset(state, 0, sizeof(VCHIQ_STATE_T)); ++ vcos_log_warn( "%s: called", __func__); ++ state->id = id++; ++ state->is_master = is_master; ++ ++ /* ++ initialize shared state pointers ++ */ ++ ++ state->local = local; ++ state->remote = remote; ++ state->slot_data = (VCHIQ_SLOT_T *)slot_zero; ++ ++ /* ++ initialize events and mutexes ++ */ ++ ++ vcos_event_create(&state->connect, "v.connect"); ++ vcos_mutex_create(&state->mutex, "v.mutex"); ++ vcos_event_create(&state->trigger_event, "v.trigger_event"); ++ vcos_event_create(&state->recycle_event, "v.recycle_event"); ++ ++ vcos_mutex_create(&state->slot_mutex, "v.slot_mutex"); ++ vcos_mutex_create(&state->recycle_mutex, "v.recycle_mutex"); ++ ++ vcos_event_create(&state->slot_available_event, "v.slot_available_event"); ++ vcos_event_create(&state->slot_remove_event, "v.slot_remove_event"); ++ ++ state->slot_queue_available = 0; ++ ++ for (i = 0; i < VCHIQ_MAX_SERVICES; i++) ++ { ++ VCHIQ_SERVICE_QUOTA_T *service_quota = &state->service_quotas[i]; ++ vcos_event_create(&service_quota->quota_event, "v.quota_event"); ++ } ++ ++ for (i = local->slot_first; i <= local->slot_last; i++) ++ { ++ local->slot_queue[state->slot_queue_available++] = i; ++ } ++ ++ state->default_slot_quota = state->slot_queue_available/2; ++ state->default_message_quota = vcos_min(state->default_slot_quota * 256, (unsigned short)~0); ++ ++ local->trigger.event = &state->trigger_event; ++ remote_event_create(&local->trigger); ++ local->tx_pos = 0; ++ ++ local->recycle.event = &state->recycle_event; ++ remote_event_create(&local->recycle); ++ local->slot_queue_recycle = state->slot_queue_available; ++ ++ local->debug[DEBUG_ENTRIES] = DEBUG_MAX; ++ ++ /* ++ bring up slot handler thread ++ */ ++ ++ vcos_thread_attr_init(&attrs); ++ vcos_thread_attr_setstacksize(&attrs, VCHIQ_SLOT_HANDLER_STACK); ++ vcos_thread_attr_setpriority(&attrs, VCOS_THREAD_PRI_REALTIME); ++ vcos_snprintf(threadname, sizeof(threadname), "VCHIQ-%d", state->id); ++ if (vcos_thread_create(&state->slot_handler_thread, threadname, ++ &attrs, slot_handler_func, state) != VCOS_SUCCESS) ++ { ++ vcos_log_error("vchiq: FATAL: couldn't create thread %s", threadname); ++ return VCHIQ_ERROR; ++ } ++ ++ vcos_thread_attr_init(&attrs); ++ vcos_thread_attr_setstacksize(&attrs, VCHIQ_SLOT_HANDLER_STACK); ++ vcos_thread_attr_setpriority(&attrs, VCOS_THREAD_PRI_REALTIME); ++ vcos_snprintf(threadname, sizeof(threadname), "VCHIQr-%d", state->id); ++ if (vcos_thread_create(&state->recycle_thread, threadname, ++ &attrs, recycle_func, state) != VCOS_SUCCESS) ++ { ++ vcos_log_error("vchiq: FATAL: couldn't create thread %s", threadname); ++ return VCHIQ_ERROR; ++ } + +- BUG_ON(state->id >= VCHIQ_MAX_STATES); +- vchiq_states[state->id] = state; ++ status = vchiq_platform_init_state(state); + +- /* Indicate readiness to the other side */ +- local->initialised = 1; ++ /* Indicate readiness to the other side */ ++ local->initialised = 1; + +- return status; ++ return status; + } + + /* Called from application thread when a client or server service is created. */ + VCHIQ_SERVICE_T * + vchiq_add_service_internal(VCHIQ_STATE_T *state, +- const VCHIQ_SERVICE_PARAMS_T *params, int srvstate, +- VCHIQ_INSTANCE_T instance) ++ const VCHIQ_SERVICE_PARAMS_T *params, int srvstate, ++ VCHIQ_INSTANCE_T instance) + { +- VCHIQ_SERVICE_T *service; +- +- service = kmalloc(sizeof(VCHIQ_SERVICE_T), GFP_KERNEL); +- if (service) { +- service->base.fourcc = params->fourcc; +- service->base.callback = params->callback; +- service->base.userdata = params->userdata; +- service->handle = VCHIQ_SERVICE_HANDLE_INVALID; +- service->ref_count = 1; +- service->srvstate = VCHIQ_SRVSTATE_FREE; +- service->localport = VCHIQ_PORT_FREE; +- service->remoteport = VCHIQ_PORT_FREE; +- +- service->public_fourcc = (srvstate == VCHIQ_SRVSTATE_OPENING) ? +- VCHIQ_FOURCC_INVALID : params->fourcc; +- service->client_id = 0; +- service->auto_close = 1; +- service->sync = 0; +- service->closing = 0; +- atomic_set(&service->poll_flags, 0); +- service->version = params->version; +- service->version_min = params->version_min; +- service->state = state; +- service->instance = instance; +- service->service_use_count = 0; +- init_bulk_queue(&service->bulk_tx); +- init_bulk_queue(&service->bulk_rx); +- sema_init(&service->remove_event, 0); +- sema_init(&service->bulk_remove_event, 0); +- mutex_init(&service->bulk_mutex); +- memset(&service->stats, 0, sizeof(service->stats)); +- } else { +- vchiq_log_error(vchiq_core_log_level, +- "Out of memory"); +- } +- +- if (service) { +- VCHIQ_SERVICE_T **pservice = NULL; +- int i; +- +- /* Although it is perfectly possible to use service_spinlock +- ** to protect the creation of services, it is overkill as it +- ** disables interrupts while the array is searched. +- ** The only danger is of another thread trying to create a +- ** service - service deletion is safe. +- ** Therefore it is preferable to use state->mutex which, +- ** although slower to claim, doesn't block interrupts while +- ** it is held. +- */ +- +- mutex_lock(&state->mutex); +- +- /* Prepare to use a previously unused service */ +- if (state->unused_service < VCHIQ_MAX_SERVICES) +- pservice = &state->services[state->unused_service]; +- +- if (srvstate == VCHIQ_SRVSTATE_OPENING) { +- for (i = 0; i < state->unused_service; i++) { +- VCHIQ_SERVICE_T *srv = state->services[i]; +- if (!srv) { +- pservice = &state->services[i]; +- break; +- } +- } +- } else { +- for (i = (state->unused_service - 1); i >= 0; i--) { +- VCHIQ_SERVICE_T *srv = state->services[i]; +- if (!srv) +- pservice = &state->services[i]; +- else if ((srv->public_fourcc == params->fourcc) +- && ((srv->instance != instance) || +- (srv->base.callback != +- params->callback))) { +- /* There is another server using this +- ** fourcc which doesn't match. */ +- pservice = NULL; +- break; +- } +- } +- } +- +- if (pservice) { +- service->localport = (pservice - state->services); +- if (!handle_seq) +- handle_seq = VCHIQ_MAX_STATES * +- VCHIQ_MAX_SERVICES; +- service->handle = handle_seq | +- (state->id * VCHIQ_MAX_SERVICES) | +- service->localport; +- handle_seq += VCHIQ_MAX_STATES * VCHIQ_MAX_SERVICES; +- *pservice = service; +- if (pservice == &state->services[state->unused_service]) +- state->unused_service++; +- } +- +- mutex_unlock(&state->mutex); +- +- if (!pservice) { +- kfree(service); +- service = NULL; +- } +- } +- +- if (service) { +- VCHIQ_SERVICE_QUOTA_T *service_quota = +- &state->service_quotas[service->localport]; +- service_quota->slot_quota = state->default_slot_quota; +- service_quota->message_quota = state->default_message_quota; +- if (service_quota->slot_use_count == 0) +- service_quota->previous_tx_index = +- SLOT_QUEUE_INDEX_FROM_POS(state->local_tx_pos) +- - 1; +- +- /* Bring this service online */ +- vchiq_set_service_state(service, srvstate); +- +- vchiq_log_info(vchiq_core_msg_log_level, +- "%s Service %c%c%c%c SrcPort:%d", +- (srvstate == VCHIQ_SRVSTATE_OPENING) +- ? "Open" : "Add", +- VCHIQ_FOURCC_AS_4CHARS(params->fourcc), +- service->localport); +- } +- +- /* Don't unlock the service - leave it with a ref_count of 1. */ ++ VCHIQ_SERVICE_T **pservice = NULL; ++ VCHIQ_SERVICE_T *service = NULL; ++ int i; ++ ++ /* Prepare to use a previously unused service */ ++ if (state->unused_service < VCHIQ_MAX_SERVICES) ++ { ++ pservice = &state->services[state->unused_service]; ++ } ++ ++ if (srvstate == VCHIQ_SRVSTATE_OPENING) { ++ for (i = 0; i < state->unused_service; i++) { ++ VCHIQ_SERVICE_T *srv = state->services[i]; ++ if (!srv) ++ { ++ pservice = &state->services[i]; ++ break; ++ } ++ if (srv->srvstate == VCHIQ_SRVSTATE_FREE) { ++ service = srv; ++ break; ++ } ++ } ++ } else { ++ for (i = (state->unused_service - 1); i >= 0; i--) { ++ VCHIQ_SERVICE_T *srv = state->services[i]; ++ if (!srv) ++ pservice = &state->services[i]; ++ else if (srv->srvstate == VCHIQ_SRVSTATE_FREE) { ++ service = srv; ++ } else if ((srv->public_fourcc == params->fourcc) && ++ ((srv->instance != instance) ++ || (srv->base.callback != params->callback))) { ++ /* There is another server using this fourcc which doesn't match */ ++ pservice = NULL; ++ service = NULL; ++ } ++ } ++ } ++ ++ if (pservice && !service) ++ { ++ service = vcos_malloc(sizeof(VCHIQ_SERVICE_T), "VCHIQ service"); ++ if (service) ++ { ++ service->srvstate = VCHIQ_SRVSTATE_FREE; ++ service->localport = (pservice - state->services); ++ vcos_event_create(&service->remove_event, "v.remove_event"); ++ vcos_event_create(&service->bulk_remove_event, "v.bulk_remove_event"); ++ vcos_mutex_create(&service->bulk_mutex, "v.bulk_mutex"); ++ *pservice = service; ++ } ++ else ++ { ++ vcos_log_error("vchiq: Out of memory"); ++ } ++ } ++ ++ if (service) { ++ VCHIQ_SERVICE_QUOTA_T *service_quota = ++ &state->service_quotas[service->localport]; ++ if (vcos_is_log_enabled( &vchiq_core_msg_log_category, VCOS_LOG_INFO)) { ++ vcos_log_impl( &vchiq_core_msg_log_category, ++ VCOS_LOG_INFO, ++ "%s Service %c%c%c%c SrcPort:%d", ++ ( srvstate == VCHIQ_SRVSTATE_OPENING ) ++ ? "Open" : "Add", ++ VCHIQ_FOURCC_AS_4CHARS(params->fourcc), ++ service->localport ); ++ } ++ service->state = state; ++ service->base.fourcc = params->fourcc; ++ service->base.callback = params->callback; ++ service->base.userdata = params->userdata; ++ service->version = params->version; ++ service->version_min = params->version_min; ++ vchiq_set_service_state(service, srvstate); ++ service->public_fourcc = ++ (srvstate == ++ VCHIQ_SRVSTATE_OPENING) ? VCHIQ_FOURCC_INVALID : params->fourcc; ++ service->instance = instance; ++ service->remoteport = VCHIQ_PORT_FREE; ++ service->client_id = 0; ++ service->auto_close = 1; ++ service->service_use_count = 0; ++ init_bulk_queue(&service->bulk_tx); ++ init_bulk_queue(&service->bulk_rx); ++ service_quota->slot_quota = state->default_slot_quota; ++ service_quota->message_quota = state->default_message_quota; ++ if (service_quota->slot_use_count == 0) ++ service_quota->previous_tx_index = ++ SLOT_QUEUE_INDEX_FROM_POS(state->local_tx_pos) - 1; ++ memset(&service->stats, 0, sizeof(service->stats)); ++ vcos_atomic_flags_create(&service->poll_flags); ++ ++ /* Ensure the events are unsignalled */ ++ while (vcos_event_try(&service->remove_event) == VCOS_SUCCESS) ++ continue; ++ while (vcos_event_try(&service_quota->quota_event) == VCOS_SUCCESS) ++ continue; ++ ++ if (pservice == &state->services[state->unused_service]) ++ state->unused_service++; ++ } + +- return service; ++ return service; + } + + VCHIQ_STATUS_T + vchiq_open_service_internal(VCHIQ_SERVICE_T *service, int client_id) + { +- struct vchiq_open_payload payload = { +- service->base.fourcc, +- client_id, +- service->version, +- service->version_min +- }; +- VCHIQ_ELEMENT_T body = { &payload, sizeof(payload) }; +- VCHIQ_STATUS_T status = VCHIQ_SUCCESS; +- +- service->client_id = client_id; +- vchiq_use_service_internal(service); +- status = queue_message(service->state, NULL, +- VCHIQ_MAKE_MSG(VCHIQ_MSG_OPEN, service->localport, 0), +- &body, 1, sizeof(payload), 1); +- if (status == VCHIQ_SUCCESS) { +- if (down_interruptible(&service->remove_event) != 0) { +- status = VCHIQ_RETRY; +- vchiq_release_service_internal(service); +- } else if ((service->srvstate != VCHIQ_SRVSTATE_OPEN) && +- (service->srvstate != VCHIQ_SRVSTATE_OPENSYNC)) { +- if (service->srvstate != VCHIQ_SRVSTATE_CLOSEWAIT) +- vchiq_log_error(vchiq_core_log_level, +- "%d: osi - srvstate = %s (ref %d)", +- service->state->id, +- srvstate_names[service->srvstate], +- service->ref_count); +- status = VCHIQ_ERROR; +- VCHIQ_SERVICE_STATS_INC(service, error_count); +- vchiq_release_service_internal(service); +- } +- } +- return status; +-} +- +-static void +-release_service_messages(VCHIQ_SERVICE_T *service) +-{ +- VCHIQ_STATE_T *state = service->state; +- int slot_last = state->remote->slot_last; +- int i; +- +- /* Release any claimed messages */ +- for (i = state->remote->slot_first; i <= slot_last; i++) { +- VCHIQ_SLOT_INFO_T *slot_info = +- SLOT_INFO_FROM_INDEX(state, i); +- if (slot_info->release_count != slot_info->use_count) { +- char *data = +- (char *)SLOT_DATA_FROM_INDEX(state, i); +- unsigned int pos, end; +- +- end = VCHIQ_SLOT_SIZE; +- if (data == state->rx_data) +- /* This buffer is still being read from - stop +- ** at the current read position */ +- end = state->rx_pos & VCHIQ_SLOT_MASK; +- +- pos = 0; +- +- while (pos < end) { +- VCHIQ_HEADER_T *header = +- (VCHIQ_HEADER_T *)(data + pos); +- int msgid = header->msgid; +- int port = VCHIQ_MSG_DSTPORT(msgid); +- if ((port == service->localport) && +- (msgid & VCHIQ_MSGID_CLAIMED)) { +- vchiq_log_info(vchiq_core_log_level, +- " fsi - hdr %x", +- (unsigned int)header); +- release_slot(state, slot_info, header, +- NULL); +- } +- pos += calc_stride(header->size); +- if (pos > VCHIQ_SLOT_SIZE) { +- vchiq_log_error(vchiq_core_log_level, +- "fsi - pos %x: header %x, " +- "msgid %x, header->msgid %x, " +- "header->size %x", +- pos, (unsigned int)header, +- msgid, header->msgid, +- header->size); +- WARN(1, "invalid slot position\n"); +- } +- } +- } +- } +-} +- +-static int +-do_abort_bulks(VCHIQ_SERVICE_T *service) +-{ +- VCHIQ_STATUS_T status; +- +- /* Abort any outstanding bulk transfers */ +- if (mutex_lock_interruptible(&service->bulk_mutex) != 0) +- return 0; +- abort_outstanding_bulks(service, &service->bulk_tx); +- abort_outstanding_bulks(service, &service->bulk_rx); +- mutex_unlock(&service->bulk_mutex); +- +- status = notify_bulks(service, &service->bulk_tx, 0/*!retry_poll*/); +- if (status == VCHIQ_SUCCESS) +- status = notify_bulks(service, &service->bulk_rx, +- 0/*!retry_poll*/); +- return (status == VCHIQ_SUCCESS); +-} +- +-static VCHIQ_STATUS_T +-close_service_complete(VCHIQ_SERVICE_T *service, int failstate) +-{ +- VCHIQ_STATUS_T status; +- int is_server = (service->public_fourcc != VCHIQ_FOURCC_INVALID); +- int newstate; +- +- switch (service->srvstate) { +- case VCHIQ_SRVSTATE_OPEN: +- case VCHIQ_SRVSTATE_CLOSESENT: +- case VCHIQ_SRVSTATE_CLOSERECVD: +- if (is_server) +- newstate = (service->auto_close ? +- VCHIQ_SRVSTATE_LISTENING : +- VCHIQ_SRVSTATE_CLOSEWAIT); +- else +- newstate = VCHIQ_SRVSTATE_CLOSED; +- vchiq_set_service_state(service, newstate); +- break; +- default: +- break; +- } +- +- status = make_service_callback(service, +- VCHIQ_SERVICE_CLOSED, NULL, NULL); +- +- if (status != VCHIQ_RETRY) { +- int uc = service->service_use_count; +- int i; +- /* Complete the close process */ +- for (i = 0; i < uc; i++) +- /* cater for cases where close is forced and the +- ** client may not close all it's handles */ +- vchiq_release_service_internal(service); +- +- service->client_id = 0; +- if (status == VCHIQ_ERROR) +- /* Signal an error (fatal, since the other end +- ** will probably have closed) */ +- vchiq_set_service_state(service, VCHIQ_SRVSTATE_OPEN); +- +- if (service->srvstate == VCHIQ_SRVSTATE_CLOSED) +- vchiq_free_service_internal(service); +- else { +- if (is_server) +- service->closing = 0; +- +- up(&service->remove_event); +- } +- } else +- vchiq_set_service_state(service, failstate); +- +- return status; ++ VCHIQ_OPEN_PAYLOAD_T payload = { ++ service->base.fourcc, ++ client_id, ++ service->version, ++ service->version_min ++ }; ++ VCHIQ_ELEMENT_T body = { &payload, sizeof(payload) }; ++ VCHIQ_STATUS_T status = VCHIQ_SUCCESS; ++ ++ service->client_id = client_id; ++ vchiq_use_service(&service->base); ++ status = queue_message(service->state, NULL, ++ VCHIQ_MAKE_MSG(VCHIQ_MSG_OPEN, service->localport, 0), ++ &body, 1, sizeof(payload), 1); ++ if (status == VCHIQ_SUCCESS) { ++ if (vcos_event_wait(&service->remove_event) != VCOS_SUCCESS) { ++ status = VCHIQ_RETRY; ++ vchiq_release_service(&service->base); ++ } else if (service->srvstate != VCHIQ_SRVSTATE_OPEN) { ++ vcos_log_info("%d: osi - srvstate = %d", service->state->id, service->srvstate); ++ vcos_assert(service->srvstate == VCHIQ_SRVSTATE_CLOSEWAIT); ++ status = VCHIQ_ERROR; ++ VCHIQ_SERVICE_STATS_INC(service, error_count); ++ vchiq_release_service(&service->base); ++ } ++ } ++ return status; + } + + /* Called by the slot handler */ + VCHIQ_STATUS_T + vchiq_close_service_internal(VCHIQ_SERVICE_T *service, int close_recvd) + { +- VCHIQ_STATE_T *state = service->state; +- VCHIQ_STATUS_T status = VCHIQ_SUCCESS; ++ VCHIQ_STATE_T *state = service->state; ++ VCHIQ_STATUS_T status = VCHIQ_SUCCESS; + +- vchiq_log_info(vchiq_core_log_level, "%d: csi:%d,%d (%s)", +- service->state->id, service->localport, close_recvd, +- srvstate_names[service->srvstate]); +- +- switch (service->srvstate) { +- case VCHIQ_SRVSTATE_CLOSED: +- case VCHIQ_SRVSTATE_HIDDEN: +- case VCHIQ_SRVSTATE_LISTENING: +- case VCHIQ_SRVSTATE_CLOSEWAIT: +- if (close_recvd) +- vchiq_log_error(vchiq_core_log_level, +- "vchiq_close_service_internal(1) called " +- "in state %s", +- srvstate_names[service->srvstate]); +- else +- vchiq_free_service_internal(service); +- break; +- case VCHIQ_SRVSTATE_OPENING: +- if (close_recvd) { +- /* The open was rejected - tell the user */ +- vchiq_set_service_state(service, +- VCHIQ_SRVSTATE_CLOSEWAIT); +- up(&service->remove_event); +- } else { +- /* Shutdown mid-open - let the other side know */ +- status = queue_message(state, service, +- VCHIQ_MAKE_MSG +- (VCHIQ_MSG_CLOSE, +- service->localport, +- VCHIQ_MSG_DSTPORT(service->remoteport)), +- NULL, 0, 0, 0); +- } +- break; +- +- case VCHIQ_SRVSTATE_OPENSYNC: +- mutex_lock(&state->sync_mutex); +- /* Drop through */ +- +- case VCHIQ_SRVSTATE_OPEN: +- if (state->is_master || close_recvd) { +- if (!do_abort_bulks(service)) +- status = VCHIQ_RETRY; +- } +- +- release_service_messages(service); +- +- if (status == VCHIQ_SUCCESS) +- status = queue_message(state, service, +- VCHIQ_MAKE_MSG +- (VCHIQ_MSG_CLOSE, +- service->localport, +- VCHIQ_MSG_DSTPORT(service->remoteport)), +- NULL, 0, 0, 0); +- +- if (status == VCHIQ_SUCCESS) { +- if (!close_recvd) +- break; +- } else if (service->srvstate == VCHIQ_SRVSTATE_OPENSYNC) { +- mutex_unlock(&state->sync_mutex); +- break; +- } else +- break; +- +- status = close_service_complete(service, +- VCHIQ_SRVSTATE_CLOSERECVD); +- break; +- +- case VCHIQ_SRVSTATE_CLOSESENT: +- if (!close_recvd) +- /* This happens when a process is killed mid-close */ +- break; +- +- if (!state->is_master) { +- if (!do_abort_bulks(service)) { +- status = VCHIQ_RETRY; +- break; +- } +- } +- +- if (status == VCHIQ_SUCCESS) +- status = close_service_complete(service, +- VCHIQ_SRVSTATE_CLOSERECVD); +- break; +- +- case VCHIQ_SRVSTATE_CLOSERECVD: +- if (!close_recvd && +- (service->public_fourcc != VCHIQ_FOURCC_INVALID)) +- /* Force into LISTENING mode */ +- vchiq_set_service_state(service, +- VCHIQ_SRVSTATE_LISTENING); +- status = close_service_complete(service, +- VCHIQ_SRVSTATE_CLOSERECVD); +- break; +- +- default: +- vchiq_log_error(vchiq_core_log_level, +- "vchiq_close_service_internal(%d) called in state %s", +- close_recvd, srvstate_names[service->srvstate]); +- break; +- } ++ vcos_log_trace("%d: csi:%d (%s)", ++ service->state->id, service->localport, ++ srvstate_names[service->srvstate]); ++ ++ switch (service->srvstate) ++ { ++ case VCHIQ_SRVSTATE_OPENING: ++ if (close_recvd) ++ { ++ /* The open was rejected - tell the user */ ++ vchiq_set_service_state(service, VCHIQ_SRVSTATE_CLOSEWAIT); ++ vcos_event_signal(&service->remove_event); ++ } ++ else ++ { ++ /* Shutdown mid-open - let the other side know */ ++ status = queue_message(state, NULL, ++ VCHIQ_MAKE_MSG ++ (VCHIQ_MSG_CLOSE, ++ service->localport, ++ VCHIQ_MSG_DSTPORT(service->remoteport)), ++ NULL, 0, 0, 0); ++ ++ if (status == VCHIQ_SUCCESS) ++ vchiq_set_service_state(service, VCHIQ_SRVSTATE_CLOSESENT); ++ } ++ break; ++ ++ case VCHIQ_SRVSTATE_OPEN: ++ if (state->is_master) ++ { ++ /* Abort any outstanding bulk transfers */ ++ vcos_mutex_lock(&service->bulk_mutex); ++ abort_outstanding_bulks(service, &service->bulk_tx); ++ abort_outstanding_bulks(service, &service->bulk_rx); ++ status = notify_bulks(service, &service->bulk_tx); ++ if (status == VCHIQ_SUCCESS) ++ status = notify_bulks(service, &service->bulk_rx); ++ vcos_mutex_unlock(&service->bulk_mutex); ++ } ++ ++ if (status == VCHIQ_SUCCESS) ++ status = queue_message(state, NULL, ++ VCHIQ_MAKE_MSG ++ (VCHIQ_MSG_CLOSE, ++ service->localport, ++ VCHIQ_MSG_DSTPORT(service->remoteport)), ++ NULL, 0, 0, 0); ++ ++ if (status == VCHIQ_SUCCESS) ++ { ++ if (close_recvd) ++ vchiq_set_service_state(service, VCHIQ_SRVSTATE_CLOSING); ++ else ++ vchiq_set_service_state(service, VCHIQ_SRVSTATE_CLOSESENT); ++ } ++ break; ++ ++ case VCHIQ_SRVSTATE_CLOSESENT: ++ vcos_assert(close_recvd); ++ ++ if (!state->is_master) ++ { ++ /* Abort any outstanding bulk transfers */ ++ vcos_mutex_lock(&service->bulk_mutex); ++ abort_outstanding_bulks(service, &service->bulk_tx); ++ abort_outstanding_bulks(service, &service->bulk_rx); ++ status = notify_bulks(service, &service->bulk_tx); ++ if (status == VCHIQ_SUCCESS) ++ status = notify_bulks(service, &service->bulk_rx); ++ vcos_mutex_unlock(&service->bulk_mutex); ++ } ++ ++ if (status == VCHIQ_SUCCESS) ++ vchiq_set_service_state(service, VCHIQ_SRVSTATE_CLOSING); ++ break; ++ ++ case VCHIQ_SRVSTATE_CLOSING: ++ /* We may come here after a retry */ ++ vcos_assert(!close_recvd); ++ break; ++ ++ default: ++ vcos_log_error("vchiq_close_service_internal(%d) called in state %s", ++ close_recvd, srvstate_names[service->srvstate]); ++ vcos_assert(0); ++ break; ++ } ++ ++ if (service->srvstate == VCHIQ_SRVSTATE_CLOSING) ++ { ++ int i; ++ int uc = service->service_use_count; ++ /* Complete the close process */ ++ for( i=0; iclient_id = 0; ++ ++ /* Now tell the client that the services is closed */ ++ if (service->instance) ++ { ++ int oldstate = service->srvstate; ++ ++ /* Change the service state now for the benefit of the callback */ ++ vchiq_set_service_state(service, ++ ((service->public_fourcc == VCHIQ_FOURCC_INVALID) || ++ !service->auto_close) ? ++ VCHIQ_SRVSTATE_CLOSEWAIT : ++ VCHIQ_SRVSTATE_LISTENING); ++ ++ status = make_service_callback(service, VCHIQ_SERVICE_CLOSED, NULL, NULL); ++ ++ if (status == VCHIQ_RETRY) ++ { ++ /* Restore the old state, to be retried later */ ++ vchiq_set_service_state(service, oldstate); ++ } ++ else ++ { ++ if (status == VCHIQ_ERROR) { ++ /* Signal an error (fatal, since the other end will probably have closed) */ ++ vchiq_set_service_state(service, VCHIQ_SRVSTATE_OPEN); ++ } ++ } ++ } ++ ++ if (status != VCHIQ_RETRY) ++ { ++ if (service->srvstate == VCHIQ_SRVSTATE_CLOSING) ++ vchiq_set_service_state(service, VCHIQ_SRVSTATE_CLOSEWAIT); ++ vcos_event_signal(&service->remove_event); ++ } ++ } + +- return status; ++ return status; + } + + /* Called from the application process upon process death */ + void + vchiq_terminate_service_internal(VCHIQ_SERVICE_T *service) + { +- VCHIQ_STATE_T *state = service->state; ++ VCHIQ_STATE_T *state = service->state; + +- vchiq_log_info(vchiq_core_log_level, "%d: tsi - (%d<->%d)", +- state->id, service->localport, service->remoteport); ++ vcos_log_info("%d: tsi - (%d<->%d)", state->id, service->localport, service->remoteport); + +- /* Make it look like a client, because it must be removed and not +- left in the LISTENING state. */ +- service->public_fourcc = VCHIQ_FOURCC_INVALID; ++ /* Disconnect from the instance, to prevent any callbacks */ ++ service->instance = NULL; + +- mark_service_closing(service); +- +- /* Mark the service for termination by the slot handler */ +- request_poll(state, service, VCHIQ_POLL_TERMINATE); ++ /* Mark the service for termination by the slot handler */ ++ request_poll(state, service, VCHIQ_POLL_TERMINATE); + } + +-/* Called from the slot handler */ ++/* Called from the application process upon process death, and from ++ vchiq_remove_service */ + void + vchiq_free_service_internal(VCHIQ_SERVICE_T *service) + { +- VCHIQ_STATE_T *state = service->state; +- +- vchiq_log_info(vchiq_core_log_level, "%d: fsi - (%d)", +- state->id, service->localport); +- +- switch (service->srvstate) { +- case VCHIQ_SRVSTATE_OPENING: +- case VCHIQ_SRVSTATE_CLOSED: +- case VCHIQ_SRVSTATE_HIDDEN: +- case VCHIQ_SRVSTATE_LISTENING: +- case VCHIQ_SRVSTATE_CLOSEWAIT: +- break; +- default: +- vchiq_log_error(vchiq_core_log_level, +- "%d: fsi - (%d) in state %s", +- state->id, service->localport, +- srvstate_names[service->srvstate]); +- return; +- } +- +- vchiq_set_service_state(service, VCHIQ_SRVSTATE_FREE); +- +- up(&service->remove_event); +- +- /* Release the initial lock */ +- unlock_service(service); ++ VCHIQ_STATE_T *state = service->state; ++ int slot_last = state->remote->slot_last; ++ int i; ++ ++ vcos_log_info("%d: fsi - (%d)", state->id, service->localport); ++ ++ vcos_mutex_lock(&state->mutex); ++ ++ /* Release any claimed messages */ ++ for (i = state->remote->slot_first; i <= slot_last; i++) ++ { ++ VCHIQ_SLOT_INFO_T *slot_info = SLOT_INFO_FROM_INDEX(state, i); ++ if (slot_info->release_count != slot_info->use_count) ++ { ++ char *data = (char *)SLOT_DATA_FROM_INDEX(state, i); ++ unsigned int pos, end; ++ ++ end = VCHIQ_SLOT_SIZE; ++ if (data == state->rx_data) ++ { ++ /* This buffer is still being read from - stop at the current read position */ ++ end = state->rx_pos & VCHIQ_SLOT_MASK; ++ } ++ ++ pos = 0; ++ ++ while (pos < end) ++ { ++ VCHIQ_HEADER_T *header = (VCHIQ_HEADER_T *)(data + pos); ++ int msgid = header->msgid; ++ int port = VCHIQ_MSG_DSTPORT(msgid); ++ if (port == service->localport) ++ { ++ if (msgid & VCHIQ_MSGID_CLAIMED) ++ { ++ header->msgid = msgid & ~VCHIQ_MSGID_CLAIMED; ++ vcos_log_info(" fsi - hdr %x", (unsigned int)header); ++ release_slot(state, slot_info); ++ } ++ } ++ pos += calc_stride(header->size); ++ if (pos > VCHIQ_SLOT_SIZE) ++ { ++ vcos_log_error("fsi - pos %x: header %x, msgid %x, header->msgid %x, header->size %x", ++ pos, (unsigned int)header, msgid, header->msgid, header->size); ++ vcos_assert(0); ++ } ++ } ++ } ++ } ++ ++ vcos_assert(state->services[service->localport] == service); ++ vchiq_set_service_state(service, VCHIQ_SRVSTATE_FREE); ++ state->services[service->localport] = NULL; ++ vcos_free(service); ++ vcos_mutex_unlock(&state->mutex); + } + + VCHIQ_STATUS_T + vchiq_connect_internal(VCHIQ_STATE_T *state, VCHIQ_INSTANCE_T instance) + { +- VCHIQ_SERVICE_T *service; +- int i; ++ int i; ++ ++ /* Find all services registered to this client and enable them. */ ++ for (i = 0; i < state->unused_service; i++) ++ { ++ VCHIQ_SERVICE_T *service = state->services[i]; ++ if (service && (service->instance == instance)) { ++ if (service->srvstate == VCHIQ_SRVSTATE_HIDDEN) ++ vchiq_set_service_state(service, ++ VCHIQ_SRVSTATE_LISTENING); ++ } ++ } ++ ++ if (state->conn_state == VCHIQ_CONNSTATE_DISCONNECTED) { ++ if (queue_message(state, NULL, ++ VCHIQ_MAKE_MSG(VCHIQ_MSG_CONNECT, 0, 0), NULL, 0, ++ 0, 1) == VCHIQ_RETRY) ++ return VCHIQ_RETRY; ++ vcos_event_wait(&state->connect); + +- /* Find all services registered to this client and enable them. */ +- i = 0; +- while ((service = next_service_by_instance(state, instance, +- &i)) != NULL) { +- if (service->srvstate == VCHIQ_SRVSTATE_HIDDEN) +- vchiq_set_service_state(service, +- VCHIQ_SRVSTATE_LISTENING); +- unlock_service(service); +- } +- +- if (state->conn_state == VCHIQ_CONNSTATE_DISCONNECTED) { +- if (queue_message(state, NULL, +- VCHIQ_MAKE_MSG(VCHIQ_MSG_CONNECT, 0, 0), NULL, 0, +- 0, 1) == VCHIQ_RETRY) +- return VCHIQ_RETRY; +- +- vchiq_set_conn_state(state, VCHIQ_CONNSTATE_CONNECTING); +- } +- +- if (state->conn_state == VCHIQ_CONNSTATE_CONNECTING) { +- if (down_interruptible(&state->connect) != 0) +- return VCHIQ_RETRY; +- +- vchiq_set_conn_state(state, VCHIQ_CONNSTATE_CONNECTED); +- up(&state->connect); +- } ++ vchiq_set_conn_state(state, VCHIQ_CONNSTATE_CONNECTED); ++ } + +- return VCHIQ_SUCCESS; ++ return VCHIQ_SUCCESS; + } + + VCHIQ_STATUS_T + vchiq_shutdown_internal(VCHIQ_STATE_T *state, VCHIQ_INSTANCE_T instance) + { +- VCHIQ_SERVICE_T *service; +- int i; ++ VCHIQ_STATUS_T status = VCHIQ_SUCCESS; ++ int i; + +- /* Find all services registered to this client and enable them. */ +- i = 0; +- while ((service = next_service_by_instance(state, instance, +- &i)) != NULL) { +- (void)vchiq_remove_service(service->handle); +- unlock_service(service); +- } ++ /* Find all services registered to this client and close them. */ ++ for (i = 0; i < state->unused_service; i++) ++ { ++ VCHIQ_SERVICE_T *service = state->services[i]; ++ if (service && (service->instance == instance) && ++ ((service->srvstate == VCHIQ_SRVSTATE_OPEN) || ++ (service->srvstate == VCHIQ_SRVSTATE_LISTENING))) ++ { ++ status = vchiq_remove_service(&service->base); ++ if (status != VCHIQ_SUCCESS) ++ break; ++ } ++ } + +- return VCHIQ_SUCCESS; ++ return status; + } + + VCHIQ_STATUS_T + vchiq_pause_internal(VCHIQ_STATE_T *state) + { +- VCHIQ_STATUS_T status = VCHIQ_SUCCESS; ++ VCHIQ_STATUS_T status = VCHIQ_SUCCESS; + +- switch (state->conn_state) { +- case VCHIQ_CONNSTATE_CONNECTED: +- /* Request a pause */ +- vchiq_set_conn_state(state, VCHIQ_CONNSTATE_PAUSING); +- request_poll(state, NULL, 0); +- break; +- default: +- vchiq_log_error(vchiq_core_log_level, +- "vchiq_pause_internal in state %s\n", +- conn_state_names[state->conn_state]); +- status = VCHIQ_ERROR; +- VCHIQ_STATS_INC(state, error_count); +- break; +- } ++ switch (state->conn_state) ++ { ++ case VCHIQ_CONNSTATE_CONNECTED: ++ /* Request a pause */ ++ vchiq_set_conn_state(state, VCHIQ_CONNSTATE_PAUSING); ++ request_poll(state, NULL, 0); ++ break; ++ case VCHIQ_CONNSTATE_PAUSED: ++ break; ++ default: ++ status = VCHIQ_ERROR; ++ VCHIQ_STATS_INC(state, error_count); ++ break; ++ } + +- return status; ++ return status; + } + + VCHIQ_STATUS_T + vchiq_resume_internal(VCHIQ_STATE_T *state) + { +- VCHIQ_STATUS_T status = VCHIQ_SUCCESS; ++ VCHIQ_STATUS_T status = VCHIQ_SUCCESS; + +- if (state->conn_state == VCHIQ_CONNSTATE_PAUSED) { +- vchiq_set_conn_state(state, VCHIQ_CONNSTATE_RESUMING); +- request_poll(state, NULL, 0); +- } else { +- status = VCHIQ_ERROR; +- VCHIQ_STATS_INC(state, error_count); +- } ++ if (state->conn_state == VCHIQ_CONNSTATE_PAUSED) ++ { ++ vchiq_set_conn_state(state, VCHIQ_CONNSTATE_RESUMING); ++ request_poll(state, NULL, 0); ++ } ++ else ++ { ++ status = VCHIQ_ERROR; ++ VCHIQ_STATS_INC(state, error_count); ++ } + +- return status; ++ return status; + } + + VCHIQ_STATUS_T + vchiq_close_service(VCHIQ_SERVICE_HANDLE_T handle) + { +- /* Unregister the service */ +- VCHIQ_SERVICE_T *service = find_service_by_handle(handle); +- VCHIQ_STATUS_T status = VCHIQ_ERROR; +- +- if (!service) +- return VCHIQ_ERROR; +- +- vchiq_log_info(vchiq_core_log_level, +- "%d: close_service:%d", +- service->state->id, service->localport); +- +- mark_service_closing(service); +- +- /* Mark the service for termination by the slot handler */ +- request_poll(service->state, service, VCHIQ_POLL_TERMINATE); +- +- while (1) { +- if (down_interruptible(&service->remove_event) != 0) { +- status = VCHIQ_RETRY; +- break; +- } +- +- if ((service->srvstate == VCHIQ_SRVSTATE_FREE) || +- (service->srvstate == VCHIQ_SRVSTATE_LISTENING) || +- (service->srvstate == VCHIQ_SRVSTATE_OPEN)) +- break; +- +- vchiq_log_warning(vchiq_core_log_level, +- "%d: close_service:%d - waiting in state %s", +- service->state->id, service->localport, +- srvstate_names[service->srvstate]); +- } +- +- if ((status == VCHIQ_SUCCESS) && +- (service->srvstate != VCHIQ_SRVSTATE_FREE) && +- (service->srvstate != VCHIQ_SRVSTATE_LISTENING)) +- status = VCHIQ_ERROR; ++ /* Unregister the service */ ++ VCHIQ_SERVICE_T *service = (VCHIQ_SERVICE_T *) handle; ++ VCHIQ_STATUS_T status = VCHIQ_ERROR; ++ ++ if (!is_valid_service(service)) ++ return VCHIQ_ERROR; ++ ++ vcos_log_info("%d: close_service:%d", service->state->id, service->localport); ++ ++ if (service->public_fourcc != VCHIQ_FOURCC_INVALID) ++ { ++ if (service->srvstate == VCHIQ_SRVSTATE_CLOSEWAIT) ++ { ++ /* This is a non-auto-close server */ ++ vchiq_set_service_state(service, VCHIQ_SRVSTATE_LISTENING); ++ status = VCHIQ_SUCCESS; ++ } ++ } ++ else ++ { ++ /* For clients, make it an alias of vchiq_remove_service */ ++ status = vchiq_remove_service(handle); ++ } + +- unlock_service(service); +- +- return status; ++ return status; + } + + VCHIQ_STATUS_T + vchiq_remove_service(VCHIQ_SERVICE_HANDLE_T handle) + { +- /* Unregister the service */ +- VCHIQ_SERVICE_T *service = find_service_by_handle(handle); +- VCHIQ_STATUS_T status = VCHIQ_SUCCESS; +- +- if (!service) +- return VCHIQ_ERROR; +- +- vchiq_log_info(vchiq_core_log_level, +- "%d: remove_service:%d", +- service->state->id, service->localport); +- +- /* Make it look like a client, because it must be removed and not +- left in the LISTENING state. */ +- service->public_fourcc = VCHIQ_FOURCC_INVALID; +- +- mark_service_closing(service); +- +- /* Mark the service for termination by the slot handler */ +- request_poll(service->state, service, VCHIQ_POLL_TERMINATE); +- +- while (1) { +- if (down_interruptible(&service->remove_event) != 0) { +- status = VCHIQ_RETRY; +- break; +- } +- +- if ((service->srvstate == VCHIQ_SRVSTATE_FREE) || +- (service->srvstate == VCHIQ_SRVSTATE_OPEN)) +- break; +- +- vchiq_log_warning(vchiq_core_log_level, +- "%d: remove_service:%d - waiting in state %s", +- service->state->id, service->localport, +- srvstate_names[service->srvstate]); +- } +- +- if ((status == VCHIQ_SUCCESS) && +- (service->srvstate != VCHIQ_SRVSTATE_FREE)) +- status = VCHIQ_ERROR; +- +- unlock_service(service); +- +- return status; +-} +- +- +-/* This function may be called by kernel threads or user threads. +- * User threads may receive VCHIQ_RETRY to indicate that a signal has been +- * received and the call should be retried after being returned to user +- * context. +- * When called in blocking mode, the userdata field points to a bulk_waiter +- * structure. +- */ +-VCHIQ_STATUS_T +-vchiq_bulk_transfer(VCHIQ_SERVICE_HANDLE_T handle, +- VCHI_MEM_HANDLE_T memhandle, void *offset, int size, void *userdata, +- VCHIQ_BULK_MODE_T mode, VCHIQ_BULK_DIR_T dir) +-{ +- VCHIQ_SERVICE_T *service = find_service_by_handle(handle); +- VCHIQ_BULK_QUEUE_T *queue; +- VCHIQ_BULK_T *bulk; +- VCHIQ_STATE_T *state; +- struct bulk_waiter *bulk_waiter = NULL; +- const char dir_char = (dir == VCHIQ_BULK_TRANSMIT) ? 't' : 'r'; +- const int dir_msgtype = (dir == VCHIQ_BULK_TRANSMIT) ? +- VCHIQ_MSG_BULK_TX : VCHIQ_MSG_BULK_RX; +- VCHIQ_STATUS_T status = VCHIQ_ERROR; +- +- if (!service || +- (service->srvstate != VCHIQ_SRVSTATE_OPEN) || +- ((memhandle == VCHI_MEM_HANDLE_INVALID) && (offset == NULL)) || +- (vchiq_check_service(service) != VCHIQ_SUCCESS)) +- goto error_exit; +- +- switch (mode) { +- case VCHIQ_BULK_MODE_NOCALLBACK: +- case VCHIQ_BULK_MODE_CALLBACK: +- break; +- case VCHIQ_BULK_MODE_BLOCKING: +- bulk_waiter = (struct bulk_waiter *)userdata; +- sema_init(&bulk_waiter->event, 0); +- bulk_waiter->actual = 0; +- bulk_waiter->bulk = NULL; +- break; +- case VCHIQ_BULK_MODE_WAITING: +- bulk_waiter = (struct bulk_waiter *)userdata; +- bulk = bulk_waiter->bulk; +- goto waiting; +- default: +- goto error_exit; +- } +- +- state = service->state; +- +- queue = (dir == VCHIQ_BULK_TRANSMIT) ? +- &service->bulk_tx : &service->bulk_rx; +- +- if (mutex_lock_interruptible(&service->bulk_mutex) != 0) { +- status = VCHIQ_RETRY; +- goto error_exit; +- } +- +- if (queue->local_insert == queue->remove + VCHIQ_NUM_SERVICE_BULKS) { +- VCHIQ_SERVICE_STATS_INC(service, bulk_stalls); +- do { +- mutex_unlock(&service->bulk_mutex); +- if (down_interruptible(&service->bulk_remove_event) +- != 0) { +- status = VCHIQ_RETRY; +- goto error_exit; +- } +- if (mutex_lock_interruptible(&service->bulk_mutex) +- != 0) { +- status = VCHIQ_RETRY; +- goto error_exit; +- } +- } while (queue->local_insert == queue->remove + +- VCHIQ_NUM_SERVICE_BULKS); +- } +- +- bulk = &queue->bulks[BULK_INDEX(queue->local_insert)]; +- +- bulk->mode = mode; +- bulk->dir = dir; +- bulk->userdata = userdata; +- bulk->size = size; +- bulk->actual = VCHIQ_BULK_ACTUAL_ABORTED; +- +- if (vchiq_prepare_bulk_data(bulk, memhandle, offset, size, dir) != +- VCHIQ_SUCCESS) +- goto unlock_error_exit; +- +- wmb(); +- +- vchiq_log_info(vchiq_core_log_level, +- "%d: bt (%d->%d) %cx %x@%x %x", +- state->id, +- service->localport, service->remoteport, dir_char, +- size, (unsigned int)bulk->data, (unsigned int)userdata); +- +- if (state->is_master) { +- queue->local_insert++; +- if (resolve_bulks(service, queue)) +- request_poll(state, service, +- (dir == VCHIQ_BULK_TRANSMIT) ? +- VCHIQ_POLL_TXNOTIFY : VCHIQ_POLL_RXNOTIFY); +- } else { +- int payload[2] = { (int)bulk->data, bulk->size }; +- VCHIQ_ELEMENT_T element = { payload, sizeof(payload) }; +- +- status = queue_message(state, NULL, +- VCHIQ_MAKE_MSG(dir_msgtype, +- service->localport, service->remoteport), +- &element, 1, sizeof(payload), 1); +- if (status != VCHIQ_SUCCESS) { +- vchiq_complete_bulk(bulk); +- goto unlock_error_exit; +- } +- queue->local_insert++; +- } +- +- mutex_unlock(&service->bulk_mutex); +- +- vchiq_log_trace(vchiq_core_log_level, +- "%d: bt:%d %cx li=%x ri=%x p=%x", +- state->id, +- service->localport, dir_char, +- queue->local_insert, queue->remote_insert, queue->process); +- +-waiting: +- unlock_service(service); +- +- status = VCHIQ_SUCCESS; +- +- if (bulk_waiter) { +- bulk_waiter->bulk = bulk; +- if (down_interruptible(&bulk_waiter->event) != 0) +- status = VCHIQ_RETRY; +- else if (bulk_waiter->actual == VCHIQ_BULK_ACTUAL_ABORTED) +- status = VCHIQ_ERROR; +- } ++ /* Unregister the service */ ++ VCHIQ_SERVICE_T *service = (VCHIQ_SERVICE_T *) handle; ++ VCHIQ_STATUS_T status = VCHIQ_SUCCESS; ++ ++ if (!is_valid_service(service)) ++ return VCHIQ_ERROR; ++ ++ vcos_log_info("%d: remove_service:%d", service->state->id, service->localport); ++ ++ switch (service->srvstate) ++ { ++ case VCHIQ_SRVSTATE_OPENING: ++ case VCHIQ_SRVSTATE_OPEN: ++ /* Mark the service for termination by the slot handler */ ++ request_poll(service->state, service, VCHIQ_POLL_TERMINATE); ++ ++ /* Drop through... */ ++ case VCHIQ_SRVSTATE_CLOSESENT: ++ case VCHIQ_SRVSTATE_CLOSING: ++ while ((service->srvstate != VCHIQ_SRVSTATE_CLOSEWAIT) && ++ (service->srvstate != VCHIQ_SRVSTATE_LISTENING)) ++ { ++ if (vcos_event_wait(&service->remove_event) != VCOS_SUCCESS) { ++ status = VCHIQ_RETRY; ++ break; ++ } ++ } ++ break; ++ ++ default: ++ break; ++ } ++ ++ if (status == VCHIQ_SUCCESS) { ++ if (service->srvstate == VCHIQ_SRVSTATE_OPEN) ++ status = VCHIQ_ERROR; ++ else ++ { ++ service->instance = NULL; ++ vchiq_free_service_internal(service); ++ } ++ } ++ ++ return status; ++} ++ ++ ++VCHIQ_STATUS_T ++vchiq_bulk_transfer(VCHIQ_SERVICE_T *service, ++ VCHI_MEM_HANDLE_T memhandle, void *offset, int size, void *userdata, ++ VCHIQ_BULK_MODE_T mode, VCHIQ_BULK_DIR_T dir) ++{ ++ VCHIQ_BULK_QUEUE_T *queue = (dir == VCHIQ_BULK_TRANSMIT) ? ++ &service->bulk_tx : &service->bulk_rx; ++ VCHIQ_BULK_T *bulk; ++ VCHIQ_STATE_T *state; ++ BULK_WAITER_T bulk_waiter; ++ const char dir_char = (dir == VCHIQ_BULK_TRANSMIT) ? 't' : 'r'; ++ const int dir_msgtype = (dir == VCHIQ_BULK_TRANSMIT) ? VCHIQ_MSG_BULK_TX : VCHIQ_MSG_BULK_RX; ++ VCHIQ_STATUS_T status = VCHIQ_ERROR; ++ ++ if (!is_valid_service(service) || ++ (service->srvstate != VCHIQ_SRVSTATE_OPEN) || ++ ((memhandle == VCHI_MEM_HANDLE_INVALID) && (offset == NULL)) || ++ (vchiq_check_service(service) != VCHIQ_SUCCESS)) ++ return VCHIQ_ERROR; ++ ++ state = service->state; ++ ++ if (vcos_mutex_lock(&service->bulk_mutex) != VCOS_SUCCESS) ++ return VCHIQ_RETRY; ++ ++ if (queue->local_insert == queue->remove + VCHIQ_NUM_SERVICE_BULKS) ++ { ++ VCHIQ_SERVICE_STATS_INC(service, bulk_stalls); ++ do { ++ vcos_mutex_unlock(&service->bulk_mutex); ++ if (vcos_event_wait(&service->bulk_remove_event) != VCOS_SUCCESS) ++ return VCHIQ_RETRY; ++ if (vcos_mutex_lock(&service->bulk_mutex) != VCOS_SUCCESS) ++ return VCHIQ_RETRY; ++ } while (queue->local_insert == queue->remove + VCHIQ_NUM_SERVICE_BULKS); ++ } ++ ++ bulk = &queue->bulks[BULK_INDEX(queue->local_insert)]; ++ ++ if (mode == VCHIQ_BULK_MODE_BLOCKING) ++ { ++ vcos_event_create(&bulk_waiter.event, "bulk_waiter"); ++ bulk_waiter.actual = 0; ++ userdata = &bulk_waiter; ++ } ++ ++ bulk->mode = mode; ++ bulk->dir = dir; ++ bulk->userdata = userdata; ++ bulk->size = size; ++ bulk->actual = VCHIQ_BULK_ACTUAL_ABORTED; ++ ++ if (vchiq_prepare_bulk_data(bulk, memhandle, offset, size, dir) != VCHIQ_SUCCESS) ++ { ++ goto error_exit; ++ } ++ ++ vcos_log_info("%d: bt (%d->%d) %cx %x@%x %x", state->id, ++ service->localport, service->remoteport, dir_char, ++ size, (unsigned int)bulk->data, (unsigned int)userdata); ++ ++ if (state->is_master) ++ { ++ queue->local_insert++; ++ if (resolve_bulks(service, queue)) ++ request_poll(state, service, (dir == VCHIQ_BULK_TRANSMIT) ? ++ VCHIQ_POLL_TXNOTIFY : VCHIQ_POLL_RXNOTIFY); ++ } ++ else ++ { ++ int payload[2] = { (int)bulk->data, bulk->size }; ++ VCHIQ_ELEMENT_T element = { payload, sizeof(payload) }; ++ ++ if (queue_message(state, NULL, ++ VCHIQ_MAKE_MSG(dir_msgtype, ++ service->localport, service->remoteport), ++ &element, 1, sizeof(payload), 1) != VCHIQ_SUCCESS) ++ { ++ vchiq_complete_bulk(bulk); ++ goto error_exit; ++ } ++ queue->local_insert++; ++ queue->remote_insert++; ++ } ++ ++ vcos_mutex_unlock(&service->bulk_mutex); ++ ++ vcos_log_trace("%d: bt:%d %cx li=%x ri=%x p=%x", state->id, ++ service->localport, dir_char, ++ queue->local_insert, queue->remote_insert, queue->process); ++ ++ status = VCHIQ_SUCCESS; ++ ++ if (mode == VCHIQ_BULK_MODE_BLOCKING) ++ { ++ if (vcos_event_wait(&bulk_waiter.event) != VCOS_SUCCESS) ++ { ++ vcos_log_info("bulk wait interrupted"); ++ /* Stop notify_bulks signalling a non-existent waiter */ ++ bulk->userdata = NULL; ++ status = VCHIQ_ERROR; ++ } ++ else if (bulk_waiter.actual == VCHIQ_BULK_ACTUAL_ABORTED) ++ status = VCHIQ_ERROR; + +- return status; ++ vcos_event_delete(&bulk_waiter.event); ++ } + +-unlock_error_exit: +- mutex_unlock(&service->bulk_mutex); ++ return status; + + error_exit: +- if (service) +- unlock_service(service); +- return status; ++ if (mode == VCHIQ_BULK_MODE_BLOCKING) ++ vcos_event_delete(&bulk_waiter.event); ++ vcos_mutex_unlock(&service->bulk_mutex); ++ ++ return status; + } + + VCHIQ_STATUS_T + vchiq_queue_bulk_transmit(VCHIQ_SERVICE_HANDLE_T handle, +- const void *data, int size, void *userdata) ++ const void *data, int size, void *userdata) + { +- return vchiq_bulk_transfer(handle, +- VCHI_MEM_HANDLE_INVALID, (void *)data, size, userdata, +- VCHIQ_BULK_MODE_CALLBACK, VCHIQ_BULK_TRANSMIT); ++ return vchiq_bulk_transfer((VCHIQ_SERVICE_T *)handle, ++ VCHI_MEM_HANDLE_INVALID, (void *)data, size, userdata, ++ VCHIQ_BULK_MODE_CALLBACK, VCHIQ_BULK_TRANSMIT); + } + + VCHIQ_STATUS_T + vchiq_queue_bulk_receive(VCHIQ_SERVICE_HANDLE_T handle, void *data, int size, +- void *userdata) ++ void *userdata) + { +- return vchiq_bulk_transfer(handle, +- VCHI_MEM_HANDLE_INVALID, data, size, userdata, +- VCHIQ_BULK_MODE_CALLBACK, VCHIQ_BULK_RECEIVE); ++ return vchiq_bulk_transfer((VCHIQ_SERVICE_T *)handle, ++ VCHI_MEM_HANDLE_INVALID, data, size, userdata, ++ VCHIQ_BULK_MODE_CALLBACK, VCHIQ_BULK_RECEIVE); + } + + VCHIQ_STATUS_T + vchiq_queue_bulk_transmit_handle(VCHIQ_SERVICE_HANDLE_T handle, +- VCHI_MEM_HANDLE_T memhandle, const void *offset, int size, +- void *userdata) ++ VCHI_MEM_HANDLE_T memhandle, const void *offset, int size, void *userdata) + { +- return vchiq_bulk_transfer(handle, +- memhandle, (void *)offset, size, userdata, +- VCHIQ_BULK_MODE_CALLBACK, VCHIQ_BULK_TRANSMIT); ++ return vchiq_bulk_transfer((VCHIQ_SERVICE_T *)handle, ++ memhandle, (void *)offset, size, userdata, ++ VCHIQ_BULK_MODE_CALLBACK, VCHIQ_BULK_TRANSMIT); + } + + VCHIQ_STATUS_T + vchiq_queue_bulk_receive_handle(VCHIQ_SERVICE_HANDLE_T handle, +- VCHI_MEM_HANDLE_T memhandle, void *offset, int size, +- void *userdata) ++ VCHI_MEM_HANDLE_T memhandle, void *offset, int size, void *userdata) + { +- return vchiq_bulk_transfer(handle, +- memhandle, offset, size, userdata, +- VCHIQ_BULK_MODE_CALLBACK, VCHIQ_BULK_RECEIVE); ++ return vchiq_bulk_transfer((VCHIQ_SERVICE_T *)handle, ++ memhandle, offset, size, userdata, ++ VCHIQ_BULK_MODE_CALLBACK, VCHIQ_BULK_RECEIVE); + } + + VCHIQ_STATUS_T + vchiq_bulk_transmit(VCHIQ_SERVICE_HANDLE_T handle, const void *data, int size, +- void *userdata, VCHIQ_BULK_MODE_T mode) ++ void *userdata, VCHIQ_BULK_MODE_T mode) + { +- struct bulk_waiter bulk_waiter; +- VCHIQ_STATUS_T status; +- +- switch (mode) { +- case VCHIQ_BULK_MODE_NOCALLBACK: +- case VCHIQ_BULK_MODE_CALLBACK: +- break; +- case VCHIQ_BULK_MODE_BLOCKING: +- userdata = &bulk_waiter; +- break; +- default: +- return VCHIQ_ERROR; +- } +- +- status = vchiq_bulk_transfer(handle, +- VCHI_MEM_HANDLE_INVALID, (void *)data, size, userdata, +- mode, VCHIQ_BULK_TRANSMIT); +- +- /* This call is for kernel thread use and should not be interrupted */ +- BUG_ON(status == VCHIQ_RETRY); +- return status; ++ return vchiq_bulk_transfer((VCHIQ_SERVICE_T *)handle, ++ VCHI_MEM_HANDLE_INVALID, (void *)data, size, userdata, ++ mode, VCHIQ_BULK_TRANSMIT); + } + + VCHIQ_STATUS_T + vchiq_bulk_receive(VCHIQ_SERVICE_HANDLE_T handle, void *data, int size, +- void *userdata, VCHIQ_BULK_MODE_T mode) ++ void *userdata, VCHIQ_BULK_MODE_T mode) + { +- struct bulk_waiter bulk_waiter; +- VCHIQ_STATUS_T status; +- +- switch (mode) { +- case VCHIQ_BULK_MODE_NOCALLBACK: +- case VCHIQ_BULK_MODE_CALLBACK: +- break; +- case VCHIQ_BULK_MODE_BLOCKING: +- userdata = &bulk_waiter; +- break; +- default: +- return VCHIQ_ERROR; +- } +- +- status = vchiq_bulk_transfer(handle, +- VCHI_MEM_HANDLE_INVALID, data, size, userdata, +- mode, VCHIQ_BULK_RECEIVE); +- +- /* This call is for kernel thread use and should not be interrupted */ +- BUG_ON(status == VCHIQ_RETRY); +- return status; ++ return vchiq_bulk_transfer((VCHIQ_SERVICE_T *)handle, ++ VCHI_MEM_HANDLE_INVALID, data, size, userdata, ++ mode, VCHIQ_BULK_RECEIVE); + } + + VCHIQ_STATUS_T + vchiq_bulk_transmit_handle(VCHIQ_SERVICE_HANDLE_T handle, +- VCHI_MEM_HANDLE_T memhandle, const void *offset, int size, +- void *userdata, VCHIQ_BULK_MODE_T mode) ++ VCHI_MEM_HANDLE_T memhandle, const void *offset, int size, void *userdata, ++ VCHIQ_BULK_MODE_T mode) + { +- struct bulk_waiter bulk_waiter; +- VCHIQ_STATUS_T status; +- +- switch (mode) { +- case VCHIQ_BULK_MODE_NOCALLBACK: +- case VCHIQ_BULK_MODE_CALLBACK: +- break; +- case VCHIQ_BULK_MODE_BLOCKING: +- userdata = &bulk_waiter; +- break; +- default: +- return VCHIQ_ERROR; +- } +- +- status = vchiq_bulk_transfer(handle, +- memhandle, (void *)offset, size, userdata, +- mode, VCHIQ_BULK_TRANSMIT); +- +- /* This call is for kernel thread use and should not be interrupted */ +- BUG_ON(status == VCHIQ_RETRY); +- return status; ++ return vchiq_bulk_transfer((VCHIQ_SERVICE_T *)handle, ++ memhandle, (void *)offset, size, userdata, ++ mode, VCHIQ_BULK_TRANSMIT); + } + + VCHIQ_STATUS_T + vchiq_bulk_receive_handle(VCHIQ_SERVICE_HANDLE_T handle, +- VCHI_MEM_HANDLE_T memhandle, void *offset, int size, void *userdata, +- VCHIQ_BULK_MODE_T mode) ++ VCHI_MEM_HANDLE_T memhandle, void *offset, int size, void *userdata, ++ VCHIQ_BULK_MODE_T mode) + { +- struct bulk_waiter bulk_waiter; +- VCHIQ_STATUS_T status; +- +- switch (mode) { +- case VCHIQ_BULK_MODE_NOCALLBACK: +- case VCHIQ_BULK_MODE_CALLBACK: +- break; +- case VCHIQ_BULK_MODE_BLOCKING: +- userdata = &bulk_waiter; +- break; +- default: +- return VCHIQ_ERROR; +- } +- +- status = vchiq_bulk_transfer(handle, +- memhandle, offset, size, userdata, +- mode, VCHIQ_BULK_RECEIVE); +- +- /* This call is for kernel thread use and should not be interrupted */ +- BUG_ON(status == VCHIQ_RETRY); +- return status; ++ return vchiq_bulk_transfer((VCHIQ_SERVICE_T *)handle, ++ memhandle, offset, size, userdata, ++ mode, VCHIQ_BULK_RECEIVE); + } + + VCHIQ_STATUS_T + vchiq_queue_message(VCHIQ_SERVICE_HANDLE_T handle, +- const VCHIQ_ELEMENT_T *elements, int count) ++ const VCHIQ_ELEMENT_T *elements, int count) + { +- VCHIQ_SERVICE_T *service = find_service_by_handle(handle); +- VCHIQ_STATUS_T status = VCHIQ_ERROR; +- +- unsigned int size = 0; +- unsigned int i; ++ VCHIQ_SERVICE_T *service = (VCHIQ_SERVICE_T *) handle; + +- if (!service || +- (vchiq_check_service(service) != VCHIQ_SUCCESS)) +- goto error_exit; +- +- for (i = 0; i < (unsigned int)count; i++) { +- if (elements[i].size) { +- if (elements[i].data == NULL) { +- VCHIQ_SERVICE_STATS_INC(service, error_count); +- goto error_exit; +- } +- size += elements[i].size; +- } +- } +- +- if (size > VCHIQ_MAX_MSG_SIZE) { +- VCHIQ_SERVICE_STATS_INC(service, error_count); +- goto error_exit; +- } +- +- switch (service->srvstate) { +- case VCHIQ_SRVSTATE_OPEN: +- status = queue_message(service->state, service, +- VCHIQ_MAKE_MSG(VCHIQ_MSG_DATA, +- service->localport, +- service->remoteport), +- elements, count, size, 1); +- break; +- case VCHIQ_SRVSTATE_OPENSYNC: +- status = queue_message_sync(service->state, service, +- VCHIQ_MAKE_MSG(VCHIQ_MSG_DATA, +- service->localport, +- service->remoteport), +- elements, count, size, 1); +- break; +- default: +- status = VCHIQ_ERROR; +- break; +- } +- +-error_exit: +- if (service) +- unlock_service(service); ++ unsigned int size = 0; ++ unsigned int i; + +- return status; ++ if (!is_valid_service(service) || ++ (service->srvstate != VCHIQ_SRVSTATE_OPEN) || ++ (vchiq_check_service(service) != VCHIQ_SUCCESS)) ++ return VCHIQ_ERROR; ++ ++ for (i = 0; i < (unsigned int)count; i++) ++ { ++ if (elements[i].size) ++ { ++ if (elements[i].data == NULL) ++ { ++ VCHIQ_SERVICE_STATS_INC(service, error_count); ++ return VCHIQ_ERROR; ++ } ++ size += elements[i].size; ++ } ++ } ++ ++ if (size > VCHIQ_MAX_MSG_SIZE) ++ { ++ VCHIQ_SERVICE_STATS_INC(service, error_count); ++ return VCHIQ_ERROR; ++ } ++ ++ return queue_message(service->state, service, ++ VCHIQ_MAKE_MSG(VCHIQ_MSG_DATA, service->localport, ++ service->remoteport), elements, count, size, 1); + } + + void + vchiq_release_message(VCHIQ_SERVICE_HANDLE_T handle, VCHIQ_HEADER_T *header) + { +- VCHIQ_SERVICE_T *service = find_service_by_handle(handle); +- VCHIQ_SHARED_STATE_T *remote; +- VCHIQ_STATE_T *state; +- int slot_index; +- +- if (!service) +- return; +- +- state = service->state; +- remote = state->remote; +- +- slot_index = SLOT_INDEX_FROM_DATA(state, (void *)header); +- +- if ((slot_index >= remote->slot_first) && +- (slot_index <= remote->slot_last)) { +- int msgid = header->msgid; +- if (msgid & VCHIQ_MSGID_CLAIMED) { +- VCHIQ_SLOT_INFO_T *slot_info = +- SLOT_INFO_FROM_INDEX(state, slot_index); +- +- release_slot(state, slot_info, header, service); +- } +- } else if (slot_index == remote->slot_sync) +- release_message_sync(state, header); ++ VCHIQ_SERVICE_T *service = (VCHIQ_SERVICE_T *)handle; ++ VCHIQ_STATE_T *state; ++ int slot_index; ++ int msgid; + +- unlock_service(service); ++ if (!is_valid_service(service)) ++ return; ++ ++ state = service->state; ++ ++ slot_index = SLOT_INDEX_FROM_DATA(state, (void *)header); ++ ++ if ((slot_index >= state->remote->slot_first) && ++ (slot_index <= state->remote->slot_last) && ++ ((msgid = header->msgid) & VCHIQ_MSGID_CLAIMED)) ++ { ++ VCHIQ_SLOT_INFO_T *slot_info = SLOT_INFO_FROM_INDEX(state, slot_index); ++ ++ /* Rewrite the message header to prevent a double release */ ++ header->msgid = msgid & ~VCHIQ_MSGID_CLAIMED; ++ ++ release_slot(state, slot_info); ++ } + } + +-static void +-release_message_sync(VCHIQ_STATE_T *state, VCHIQ_HEADER_T *header) ++int ++vchiq_get_client_id(VCHIQ_SERVICE_HANDLE_T handle) + { +- header->msgid = VCHIQ_MSGID_PADDING; +- wmb(); +- remote_event_signal(&state->remote->sync_release); ++ VCHIQ_SERVICE_T *service = (VCHIQ_SERVICE_T *)handle; ++ return service ? service->client_id : 0; + } + + VCHIQ_STATUS_T + vchiq_get_config(VCHIQ_INSTANCE_T instance, +- int config_size, VCHIQ_CONFIG_T *pconfig) ++ int config_size, VCHIQ_CONFIG_T *pconfig) + { +- VCHIQ_CONFIG_T config; ++ VCHIQ_CONFIG_T config; + +- (void)instance; ++ vcos_unused(instance); + +- config.max_msg_size = VCHIQ_MAX_MSG_SIZE; +- config.bulk_threshold = VCHIQ_MAX_MSG_SIZE; +- config.max_outstanding_bulks = VCHIQ_NUM_SERVICE_BULKS; +- config.max_services = VCHIQ_MAX_SERVICES; +- config.version = VCHIQ_VERSION; +- config.version_min = VCHIQ_VERSION_MIN; ++ config.max_msg_size = VCHIQ_MAX_MSG_SIZE; ++ config.bulk_threshold = VCHIQ_MAX_MSG_SIZE; ++ config.max_outstanding_bulks = VCHIQ_NUM_SERVICE_BULKS; ++ config.max_services = VCHIQ_MAX_SERVICES; ++ config.version = VCHIQ_VERSION; ++ config.version_min = VCHIQ_VERSION_MIN; + +- if (config_size > sizeof(VCHIQ_CONFIG_T)) +- return VCHIQ_ERROR; ++ if (config_size > sizeof(VCHIQ_CONFIG_T)) ++ return VCHIQ_ERROR; + +- memcpy(pconfig, &config, +- min(config_size, (int)(sizeof(VCHIQ_CONFIG_T)))); ++ memcpy(pconfig, &config, vcos_min(config_size, sizeof(VCHIQ_CONFIG_T))); + +- return VCHIQ_SUCCESS; ++ return VCHIQ_SUCCESS; + } + + VCHIQ_STATUS_T + vchiq_set_service_option(VCHIQ_SERVICE_HANDLE_T handle, +- VCHIQ_SERVICE_OPTION_T option, int value) ++ VCHIQ_SERVICE_OPTION_T option, int value) + { +- VCHIQ_SERVICE_T *service = find_service_by_handle(handle); +- VCHIQ_STATUS_T status = VCHIQ_ERROR; ++ VCHIQ_SERVICE_T *service = (VCHIQ_SERVICE_T *)handle; ++ VCHIQ_STATUS_T status = VCHIQ_ERROR; + +- if (service) { +- switch (option) { +- case VCHIQ_SERVICE_OPTION_AUTOCLOSE: +- service->auto_close = value; +- status = VCHIQ_SUCCESS; +- break; +- +- case VCHIQ_SERVICE_OPTION_SLOT_QUOTA: { +- VCHIQ_SERVICE_QUOTA_T *service_quota = +- &service->state->service_quotas[ +- service->localport]; +- if (value == 0) +- value = service->state->default_slot_quota; +- if ((value >= service_quota->slot_use_count) && +- (value < (unsigned short)~0)) { +- service_quota->slot_quota = value; +- if ((value >= service_quota->slot_use_count) && +- (service_quota->message_quota >= +- service_quota->message_use_count)) { +- /* Signal the service that it may have +- ** dropped below its quota */ +- up(&service_quota->quota_event); +- } +- status = VCHIQ_SUCCESS; +- } +- } break; +- +- case VCHIQ_SERVICE_OPTION_MESSAGE_QUOTA: { +- VCHIQ_SERVICE_QUOTA_T *service_quota = +- &service->state->service_quotas[ +- service->localport]; +- if (value == 0) +- value = service->state->default_message_quota; +- if ((value >= service_quota->message_use_count) && +- (value < (unsigned short)~0)) { +- service_quota->message_quota = value; +- if ((value >= +- service_quota->message_use_count) && +- (service_quota->slot_quota >= +- service_quota->slot_use_count)) +- /* Signal the service that it may have +- ** dropped below its quota */ +- up(&service_quota->quota_event); +- status = VCHIQ_SUCCESS; +- } +- } break; +- +- case VCHIQ_SERVICE_OPTION_SYNCHRONOUS: +- if ((service->srvstate == VCHIQ_SRVSTATE_HIDDEN) || +- (service->srvstate == +- VCHIQ_SRVSTATE_LISTENING)) { +- service->sync = value; +- status = VCHIQ_SUCCESS; +- } +- break; +- +- default: +- break; +- } +- unlock_service(service); +- } ++ if (is_valid_service(service)) ++ { ++ switch (option) ++ { ++ case VCHIQ_SERVICE_OPTION_AUTOCLOSE: ++ service->auto_close = value; ++ status = VCHIQ_SUCCESS; ++ break; ++ ++ case VCHIQ_SERVICE_OPTION_SLOT_QUOTA: ++ { ++ VCHIQ_SERVICE_QUOTA_T *service_quota = ++ &service->state->service_quotas[service->localport]; ++ if (value == 0) ++ value = service->state->default_slot_quota; ++ if ((value >= service_quota->slot_use_count) && ++ (value < (unsigned short)~0)) ++ { ++ service_quota->slot_quota = value; ++ if ((value >= service_quota->slot_use_count) && ++ (service_quota->message_quota >= service_quota->message_use_count)) ++ { ++ /* Signal the service that it may have dropped below its quota */ ++ vcos_event_signal(&service_quota->quota_event); ++ } ++ status = VCHIQ_SUCCESS; ++ } ++ } ++ break; ++ ++ case VCHIQ_SERVICE_OPTION_MESSAGE_QUOTA: ++ { ++ VCHIQ_SERVICE_QUOTA_T *service_quota = ++ &service->state->service_quotas[service->localport]; ++ if (value == 0) ++ value = service->state->default_message_quota; ++ if ((value >= service_quota->message_use_count) && ++ (value < (unsigned short)~0)) ++ { ++ service_quota->message_quota = value; ++ if ((value >= service_quota->message_use_count) && ++ (service_quota->slot_quota >= service_quota->slot_use_count)) ++ { ++ /* Signal the service that it may have dropped below its quota */ ++ vcos_event_signal(&service_quota->quota_event); ++ } ++ status = VCHIQ_SUCCESS; ++ } ++ } ++ break; ++ ++ default: ++ break; ++ } ++ } + +- return status; ++ return status; + } + + void + vchiq_dump_shared_state(void *dump_context, VCHIQ_STATE_T *state, +- VCHIQ_SHARED_STATE_T *shared, const char *label) ++ VCHIQ_SHARED_STATE_T *shared, const char *label) + { +- static const char *const debug_names[] = { +- "", +- "SLOT_HANDLER_COUNT", +- "SLOT_HANDLER_LINE", +- "PARSE_LINE", +- "PARSE_HEADER", +- "PARSE_MSGID", +- "AWAIT_COMPLETION_LINE", +- "DEQUEUE_MESSAGE_LINE", +- "SERVICE_CALLBACK_LINE", +- "MSG_QUEUE_FULL_COUNT", +- "COMPLETION_QUEUE_FULL_COUNT" +- }; +- int i; +- +- char buf[80]; +- int len; +- len = snprintf(buf, sizeof(buf), +- " %s: slots %d-%d tx_pos=%x recycle=%x", +- label, shared->slot_first, shared->slot_last, +- shared->tx_pos, shared->slot_queue_recycle); +- vchiq_dump(dump_context, buf, len + 1); +- +- len = snprintf(buf, sizeof(buf), +- " Slots claimed:"); +- vchiq_dump(dump_context, buf, len + 1); +- +- for (i = shared->slot_first; i <= shared->slot_last; i++) { +- VCHIQ_SLOT_INFO_T slot_info = *SLOT_INFO_FROM_INDEX(state, i); +- if (slot_info.use_count != slot_info.release_count) { +- len = snprintf(buf, sizeof(buf), +- " %d: %d/%d", i, slot_info.use_count, +- slot_info.release_count); +- vchiq_dump(dump_context, buf, len + 1); +- } +- } +- +- for (i = 1; i < shared->debug[DEBUG_ENTRIES]; i++) { +- len = snprintf(buf, sizeof(buf), " DEBUG: %s = %d(%x)", +- debug_names[i], shared->debug[i], shared->debug[i]); +- vchiq_dump(dump_context, buf, len + 1); +- } ++ static const char *const debug_names[] = ++ { ++ "", ++ "SLOT_HANDLER_COUNT", ++ "SLOT_HANDLER_LINE", ++ "PARSE_LINE", ++ "PARSE_HEADER", ++ "PARSE_MSGID", ++ "AWAIT_COMPLETION_LINE", ++ "DEQUEUE_MESSAGE_LINE", ++ "SERVICE_CALLBACK_LINE", ++ "MSG_QUEUE_FULL_COUNT", ++ "COMPLETION_QUEUE_FULL_COUNT" ++ }; ++ int i; ++ ++ char buf[80]; ++ int len; ++ len = vcos_snprintf(buf, sizeof(buf), ++ " %s: slots %d-%d tx_pos=%x recycle=%x", ++ label, shared->slot_first, shared->slot_last, ++ shared->tx_pos, shared->slot_queue_recycle); ++ vchiq_dump(dump_context, buf, len + 1); ++ ++ len = vcos_snprintf(buf, sizeof(buf), ++ " Slots claimed:"); ++ vchiq_dump(dump_context, buf, len + 1); ++ ++ for (i = shared->slot_first; i <= shared->slot_last; i++) ++ { ++ VCHIQ_SLOT_INFO_T slot_info = *SLOT_INFO_FROM_INDEX(state, i); ++ if (slot_info.use_count != slot_info.release_count) ++ { ++ len = vcos_snprintf(buf, sizeof(buf), ++ " %d: %d/%d", i, slot_info.use_count, slot_info.release_count); ++ vchiq_dump(dump_context, buf, len + 1); ++ } ++ } ++ ++ for (i = 1; i < shared->debug[DEBUG_ENTRIES]; i++) ++ { ++ len = vcos_snprintf(buf, sizeof(buf), " DEBUG: %s = %d(%x)", ++ debug_names[i], shared->debug[i], shared->debug[i]); ++ vchiq_dump(dump_context, buf, len + 1); ++ } + } + + void + vchiq_dump_state(void *dump_context, VCHIQ_STATE_T *state) + { +- char buf[80]; +- int len; +- int i; +- +- len = snprintf(buf, sizeof(buf), "State %d: %s", state->id, +- conn_state_names[state->conn_state]); +- vchiq_dump(dump_context, buf, len + 1); +- +- len = snprintf(buf, sizeof(buf), +- " tx_pos=%x(@%x), rx_pos=%x(@%x)", +- state->local->tx_pos, +- (uint32_t)state->tx_data + +- (state->local_tx_pos & VCHIQ_SLOT_MASK), +- state->rx_pos, +- (uint32_t)state->rx_data + +- (state->rx_pos & VCHIQ_SLOT_MASK)); +- vchiq_dump(dump_context, buf, len + 1); +- +- len = snprintf(buf, sizeof(buf), +- " Version: %d (min %d)", +- VCHIQ_VERSION, VCHIQ_VERSION_MIN); +- vchiq_dump(dump_context, buf, len + 1); +- +- if (VCHIQ_ENABLE_STATS) { +- len = snprintf(buf, sizeof(buf), +- " Stats: ctrl_tx_count=%d, ctrl_rx_count=%d, " +- "error_count=%d", +- state->stats.ctrl_tx_count, state->stats.ctrl_rx_count, +- state->stats.error_count); +- vchiq_dump(dump_context, buf, len + 1); +- } +- +- len = snprintf(buf, sizeof(buf), +- " Slots: %d available (%d data), %d recyclable, %d stalls (%d data)", +- state->slot_queue_available - +- SLOT_QUEUE_INDEX_FROM_POS(state->local_tx_pos), +- state->data_quota - state->data_use_count, +- state->local->slot_queue_recycle - state->slot_queue_available, +- state->stats.slot_stalls, state->stats.data_stalls); +- vchiq_dump(dump_context, buf, len + 1); +- +- vchiq_dump_platform_state(dump_context); +- +- vchiq_dump_shared_state(dump_context, state, state->local, "Local"); +- vchiq_dump_shared_state(dump_context, state, state->remote, "Remote"); +- +- vchiq_dump_platform_instances(dump_context); +- +- for (i = 0; i < state->unused_service; i++) { +- VCHIQ_SERVICE_T *service = find_service_by_port(state, i); +- +- if (service) { +- vchiq_dump_service_state(dump_context, service); +- unlock_service(service); +- } +- } ++ char buf[80]; ++ int len; ++ int i; ++ ++ len = vcos_snprintf(buf, sizeof(buf), "State %d: %s", state->id, ++ conn_state_names[state->conn_state]); ++ vchiq_dump(dump_context, buf, len + 1); ++ ++ len = vcos_snprintf(buf, sizeof(buf), ++ " tx_pos=%x(@%x), rx_pos=%x(@%x)", ++ state->id, state->local->tx_pos, ++ (uint32_t)state->tx_data + (state->local_tx_pos & VCHIQ_SLOT_MASK), ++ state->rx_pos, ++ (uint32_t)state->rx_data + (state->rx_pos & VCHIQ_SLOT_MASK)); ++ vchiq_dump(dump_context, buf, len + 1); ++ ++ len = vcos_snprintf(buf, sizeof(buf), ++ " Version: %d (min %d)", ++ VCHIQ_VERSION, VCHIQ_VERSION_MIN); ++ vchiq_dump(dump_context, buf, len + 1); ++ ++ if (VCHIQ_ENABLE_STATS) ++ { ++ len = vcos_snprintf(buf, sizeof(buf), ++ " Stats: ctrl_tx_count=%d, ctrl_rx_count=%d, error_count=%d", ++ state->stats.ctrl_tx_count, state->stats.ctrl_rx_count, ++ state->stats.slot_stalls); ++ vchiq_dump(dump_context, buf, len + 1); ++ } ++ ++ len = vcos_snprintf(buf, sizeof(buf), ++ " Slots: %d available, %d recyclable, %d stalls", ++ state->slot_queue_available - SLOT_QUEUE_INDEX_FROM_POS(state->local_tx_pos), ++ state->local->slot_queue_recycle - state->slot_queue_available, ++ state->stats.slot_stalls); ++ vchiq_dump(dump_context, buf, len + 1); ++ ++ vchiq_dump_platform_state(dump_context); ++ ++ vchiq_dump_shared_state(dump_context, state, state->local, "Local"); ++ vchiq_dump_shared_state(dump_context, state, state->remote, "Remote"); ++ ++ vchiq_dump_platform_instances(dump_context); ++ ++ for (i = 0; i < state->unused_service; i++) { ++ VCHIQ_SERVICE_T *service = state->services[i]; ++ ++ if (service && (service->srvstate != VCHIQ_SRVSTATE_FREE)) ++ vchiq_dump_service_state(dump_context, service); ++ } + } + + void + vchiq_dump_service_state(void *dump_context, VCHIQ_SERVICE_T *service) + { +- char buf[80]; +- int len; +- +- len = snprintf(buf, sizeof(buf), "Service %d: %s (ref %u)", +- service->localport, srvstate_names[service->srvstate], +- service->ref_count - 1); /*Don't include the lock just taken*/ +- +- if (service->srvstate != VCHIQ_SRVSTATE_FREE) { +- char remoteport[30]; +- VCHIQ_SERVICE_QUOTA_T *service_quota = +- &service->state->service_quotas[service->localport]; +- int fourcc = service->base.fourcc; +- int tx_pending, rx_pending; +- if (service->remoteport != VCHIQ_PORT_FREE) { +- int len2 = snprintf(remoteport, sizeof(remoteport), +- "%d", service->remoteport); +- if (service->public_fourcc != VCHIQ_FOURCC_INVALID) +- snprintf(remoteport + len2, +- sizeof(remoteport) - len2, +- " (client %x)", service->client_id); +- } else +- strcpy(remoteport, "n/a"); +- +- len += snprintf(buf + len, sizeof(buf) - len, +- " '%c%c%c%c' remote %s (msg use %d/%d, slot use %d/%d)", +- VCHIQ_FOURCC_AS_4CHARS(fourcc), +- remoteport, +- service_quota->message_use_count, +- service_quota->message_quota, +- service_quota->slot_use_count, +- service_quota->slot_quota); +- +- vchiq_dump(dump_context, buf, len + 1); +- +- tx_pending = service->bulk_tx.local_insert - +- service->bulk_tx.remote_insert; +- +- rx_pending = service->bulk_rx.local_insert - +- service->bulk_rx.remote_insert; +- +- len = snprintf(buf, sizeof(buf), +- " Bulk: tx_pending=%d (size %d)," +- " rx_pending=%d (size %d)", +- tx_pending, +- tx_pending ? service->bulk_tx.bulks[ +- BULK_INDEX(service->bulk_tx.remove)].size : 0, +- rx_pending, +- rx_pending ? service->bulk_rx.bulks[ +- BULK_INDEX(service->bulk_rx.remove)].size : 0); +- +- if (VCHIQ_ENABLE_STATS) { +- vchiq_dump(dump_context, buf, len + 1); +- +- len = snprintf(buf, sizeof(buf), +- " Ctrl: tx_count=%d, tx_bytes=%llu, " +- "rx_count=%d, rx_bytes=%llu", +- service->stats.ctrl_tx_count, +- service->stats.ctrl_tx_bytes, +- service->stats.ctrl_rx_count, +- service->stats.ctrl_rx_bytes); +- vchiq_dump(dump_context, buf, len + 1); +- +- len = snprintf(buf, sizeof(buf), +- " Bulk: tx_count=%d, tx_bytes=%llu, " +- "rx_count=%d, rx_bytes=%llu", +- service->stats.bulk_tx_count, +- service->stats.bulk_tx_bytes, +- service->stats.bulk_rx_count, +- service->stats.bulk_rx_bytes); +- vchiq_dump(dump_context, buf, len + 1); +- +- len = snprintf(buf, sizeof(buf), +- " %d quota stalls, %d slot stalls, " +- "%d bulk stalls, %d aborted, %d errors", +- service->stats.quota_stalls, +- service->stats.slot_stalls, +- service->stats.bulk_stalls, +- service->stats.bulk_aborted_count, +- service->stats.error_count); +- } +- } ++ char buf[80]; ++ int len; + +- vchiq_dump(dump_context, buf, len + 1); ++ len = vcos_snprintf(buf, sizeof(buf), "Service %d: %s", ++ service->localport, srvstate_names[service->srvstate]); + +- if (service->srvstate != VCHIQ_SRVSTATE_FREE) +- vchiq_dump_platform_service_state(dump_context, service); +-} +- +- +-void +-vchiq_loud_error_header(void) +-{ +- vchiq_log_error(vchiq_core_log_level, +- "============================================================" +- "================"); +- vchiq_log_error(vchiq_core_log_level, +- "============================================================" +- "================"); +- vchiq_log_error(vchiq_core_log_level, "====="); +-} +- +-void +-vchiq_loud_error_footer(void) +-{ +- vchiq_log_error(vchiq_core_log_level, "====="); +- vchiq_log_error(vchiq_core_log_level, +- "============================================================" +- "================"); +- vchiq_log_error(vchiq_core_log_level, +- "============================================================" +- "================"); +-} +- +- +-VCHIQ_STATUS_T vchiq_send_remote_use(VCHIQ_STATE_T *state) +-{ +- VCHIQ_STATUS_T status = VCHIQ_RETRY; +- if (state->conn_state != VCHIQ_CONNSTATE_DISCONNECTED) +- status = queue_message(state, NULL, +- VCHIQ_MAKE_MSG(VCHIQ_MSG_REMOTE_USE, 0, 0), +- NULL, 0, 0, 0); +- return status; +-} +- +-VCHIQ_STATUS_T vchiq_send_remote_release(VCHIQ_STATE_T *state) +-{ +- VCHIQ_STATUS_T status = VCHIQ_RETRY; +- if (state->conn_state != VCHIQ_CONNSTATE_DISCONNECTED) +- status = queue_message(state, NULL, +- VCHIQ_MAKE_MSG(VCHIQ_MSG_REMOTE_RELEASE, 0, 0), +- NULL, 0, 0, 0); +- return status; +-} +- +-VCHIQ_STATUS_T vchiq_send_remote_use_active(VCHIQ_STATE_T *state) +-{ +- VCHIQ_STATUS_T status = VCHIQ_RETRY; +- if (state->conn_state != VCHIQ_CONNSTATE_DISCONNECTED) +- status = queue_message(state, NULL, +- VCHIQ_MAKE_MSG(VCHIQ_MSG_REMOTE_USE_ACTIVE, 0, 0), +- NULL, 0, 0, 0); +- return status; +-} +- +-void vchiq_log_dump_mem(const char *label, uint32_t addr, const void *voidMem, +- size_t numBytes) +-{ +- const uint8_t *mem = (const uint8_t *)voidMem; +- size_t offset; +- char lineBuf[100]; +- char *s; +- +- while (numBytes > 0) { +- s = lineBuf; +- +- for (offset = 0; offset < 16; offset++) { +- if (offset < numBytes) +- s += snprintf(s, 4, "%02x ", mem[offset]); +- else +- s += snprintf(s, 4, " "); +- } +- +- for (offset = 0; offset < 16; offset++) { +- if (offset < numBytes) { +- uint8_t ch = mem[offset]; +- +- if ((ch < ' ') || (ch > '~')) +- ch = '.'; +- *s++ = (char)ch; +- } +- } +- *s++ = '\0'; +- +- if ((label != NULL) && (*label != '\0')) +- vchiq_log_trace(VCHIQ_LOG_TRACE, +- "%s: %08x: %s", label, addr, lineBuf); +- else +- vchiq_log_trace(VCHIQ_LOG_TRACE, +- "%08x: %s", addr, lineBuf); +- +- addr += 16; +- mem += 16; +- if (numBytes > 16) +- numBytes -= 16; +- else +- numBytes = 0; +- } ++ if (service->srvstate != VCHIQ_SRVSTATE_FREE) ++ { ++ char remoteport[30]; ++ VCHIQ_SERVICE_QUOTA_T *service_quota = ++ &service->state->service_quotas[service->localport]; ++ int fourcc = service->base.fourcc; ++ if (service->remoteport != VCHIQ_PORT_FREE) ++ { ++ int len2 = vcos_snprintf(remoteport, sizeof(remoteport), "%d", ++ service->remoteport); ++ if (service->public_fourcc != VCHIQ_FOURCC_INVALID) ++ vcos_snprintf(remoteport + len2, sizeof(remoteport) - len2, ++ " (client %x)", service->client_id); ++ } ++ else ++ vcos_strcpy(remoteport, "n/a"); ++ ++ len += vcos_snprintf(buf + len, sizeof(buf) - len, ++ " '%c%c%c%c' remote %s (msg use %d/%d, slot use %d/%d)", ++ VCHIQ_FOURCC_AS_4CHARS(fourcc), ++ remoteport, ++ service_quota->message_use_count, ++ service_quota->message_quota, ++ service_quota->slot_use_count, ++ service_quota->slot_quota); ++ ++ if (VCHIQ_ENABLE_STATS) ++ { ++ vchiq_dump(dump_context, buf, len + 1); ++ ++ len = vcos_snprintf(buf, sizeof(buf), ++ " Ctrl: tx_count=%d, tx_bytes=%" PRIu64 ", rx_count=%d, rx_bytes=%" PRIu64, ++ service->stats.ctrl_tx_count, service->stats.ctrl_tx_bytes, ++ service->stats.ctrl_rx_count, service->stats.ctrl_rx_bytes); ++ vchiq_dump(dump_context, buf, len + 1); ++ ++ len = vcos_snprintf(buf, sizeof(buf), ++ " Bulk: tx_count=%d, tx_bytes=%" PRIu64 ", rx_count=%d, rx_bytes=%" PRIu64, ++ service->stats.bulk_tx_count, service->stats.bulk_tx_bytes, ++ service->stats.bulk_rx_count, service->stats.bulk_rx_bytes); ++ vchiq_dump(dump_context, buf, len + 1); ++ ++ len = vcos_snprintf(buf, sizeof(buf), ++ " %d quota stalls, %d slot stalls, %d bulk stalls, %d aborted, %d errors", ++ service->stats.quota_stalls, service->stats.slot_stalls, ++ service->stats.bulk_stalls, service->stats.bulk_aborted_count, ++ service->stats.error_count); ++ } ++ } ++ ++ vchiq_dump(dump_context, buf, len + 1); ++ ++ vchiq_dump_platform_service_state(dump_context, service); ++} ++ ++ ++VCHIQ_STATUS_T vchiq_send_remote_use(VCHIQ_STATE_T * state) ++{ ++ VCHIQ_STATUS_T status = VCHIQ_RETRY; ++ if(state->conn_state != VCHIQ_CONNSTATE_DISCONNECTED) ++ { ++ status = queue_message(state, NULL, VCHIQ_MAKE_MSG(VCHIQ_MSG_REMOTE_USE, 0, 0), NULL, 0, 0, 0); ++ } ++ return status; ++} ++ ++VCHIQ_STATUS_T vchiq_send_remote_release(VCHIQ_STATE_T * state) ++{ ++ VCHIQ_STATUS_T status = VCHIQ_RETRY; ++ if(state->conn_state != VCHIQ_CONNSTATE_DISCONNECTED) ++ { ++ status = queue_message(state, NULL, VCHIQ_MAKE_MSG(VCHIQ_MSG_REMOTE_RELEASE, 0, 0), NULL, 0, 0, 0); ++ } ++ return status; ++} ++ ++VCHIQ_STATUS_T vchiq_send_remote_use_active(VCHIQ_STATE_T * state) ++{ ++ VCHIQ_STATUS_T status = VCHIQ_RETRY; ++ if(state->conn_state != VCHIQ_CONNSTATE_DISCONNECTED) ++ { ++ status = queue_message(state, NULL, VCHIQ_MAKE_MSG(VCHIQ_MSG_REMOTE_USE_ACTIVE, 0, 0), NULL, 0, 0, 0); ++ } ++ return status; + } +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_core.h +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_core.h 2013-07-26 19:36:51.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_core.h 2013-07-26 19:37:11.000000000 +0000 +@@ -19,105 +19,58 @@ + #ifndef VCHIQ_CORE_H + #define VCHIQ_CORE_H + +-#include +-#include +-#include +- + #include "vchiq_cfg.h" + + #include "vchiq.h" + +-/* Run time control of log level, based on KERN_XXX level. */ +-#define VCHIQ_LOG_DEFAULT 4 +-#define VCHIQ_LOG_ERROR 3 +-#define VCHIQ_LOG_WARNING 4 +-#define VCHIQ_LOG_INFO 6 +-#define VCHIQ_LOG_TRACE 7 +- +-#define VCHIQ_LOG_PREFIX KERN_INFO "vchiq: " +- +-#ifndef vchiq_log_error +-#define vchiq_log_error(cat, fmt, ...) \ +- do { if (cat >= VCHIQ_LOG_ERROR) \ +- printk(VCHIQ_LOG_PREFIX fmt "\n", ##__VA_ARGS__); } while (0) +-#endif +-#ifndef vchiq_log_warning +-#define vchiq_log_warning(cat, fmt, ...) \ +- do { if (cat >= VCHIQ_LOG_WARNING) \ +- printk(VCHIQ_LOG_PREFIX fmt "\n", ##__VA_ARGS__); } while (0) +-#endif +-#ifndef vchiq_log_info +-#define vchiq_log_info(cat, fmt, ...) \ +- do { if (cat >= VCHIQ_LOG_INFO) \ +- printk(VCHIQ_LOG_PREFIX fmt "\n", ##__VA_ARGS__); } while (0) +-#endif +-#ifndef vchiq_log_trace +-#define vchiq_log_trace(cat, fmt, ...) \ +- do { if (cat >= VCHIQ_LOG_TRACE) \ +- printk(VCHIQ_LOG_PREFIX fmt "\n", ##__VA_ARGS__); } while (0) +-#endif +- +-#define vchiq_loud_error(...) \ +- vchiq_log_error(vchiq_core_log_level, "===== " __VA_ARGS__) +- +-#ifndef vchiq_static_assert +-#define vchiq_static_assert(cond) __attribute__((unused)) \ +- extern int vchiq_static_assert[(cond) ? 1 : -1] +-#endif +- + #define IS_POW2(x) (x && ((x & (x - 1)) == 0)) + + /* Ensure that the slot size and maximum number of slots are powers of 2 */ +-vchiq_static_assert(IS_POW2(VCHIQ_SLOT_SIZE)); +-vchiq_static_assert(IS_POW2(VCHIQ_MAX_SLOTS)); +-vchiq_static_assert(IS_POW2(VCHIQ_MAX_SLOTS_PER_SIDE)); ++vcos_static_assert(IS_POW2(VCHIQ_SLOT_SIZE)); ++vcos_static_assert(IS_POW2(VCHIQ_MAX_SLOTS)); ++vcos_static_assert(IS_POW2(VCHIQ_MAX_SLOTS_PER_SIDE)); + + #define VCHIQ_SLOT_MASK (VCHIQ_SLOT_SIZE - 1) + #define VCHIQ_SLOT_QUEUE_MASK (VCHIQ_MAX_SLOTS_PER_SIDE - 1) + #define VCHIQ_SLOT_ZERO_SLOTS ((sizeof(VCHIQ_SLOT_ZERO_T) + \ +- VCHIQ_SLOT_SIZE - 1) / VCHIQ_SLOT_SIZE) ++ VCHIQ_SLOT_SIZE - 1) / VCHIQ_SLOT_SIZE) + +-#define VCHIQ_MSG_PADDING 0 /* - */ +-#define VCHIQ_MSG_CONNECT 1 /* - */ +-#define VCHIQ_MSG_OPEN 2 /* + (srcport, -), fourcc, client_id */ +-#define VCHIQ_MSG_OPENACK 3 /* + (srcport, dstport) */ +-#define VCHIQ_MSG_CLOSE 4 /* + (srcport, dstport) */ +-#define VCHIQ_MSG_DATA 5 /* + (srcport, dstport) */ +-#define VCHIQ_MSG_BULK_RX 6 /* + (srcport, dstport), data, size */ +-#define VCHIQ_MSG_BULK_TX 7 /* + (srcport, dstport), data, size */ +-#define VCHIQ_MSG_BULK_RX_DONE 8 /* + (srcport, dstport), actual */ +-#define VCHIQ_MSG_BULK_TX_DONE 9 /* + (srcport, dstport), actual */ +-#define VCHIQ_MSG_PAUSE 10 /* - */ +-#define VCHIQ_MSG_RESUME 11 /* - */ +-#define VCHIQ_MSG_REMOTE_USE 12 /* - */ +-#define VCHIQ_MSG_REMOTE_RELEASE 13 /* - */ +-#define VCHIQ_MSG_REMOTE_USE_ACTIVE 14 /* - */ ++#define VCHIQ_MSG_PADDING 0 // - ++#define VCHIQ_MSG_CONNECT 1 // - ++#define VCHIQ_MSG_OPEN 2 // + (srcport, -), fourcc, client_id ++#define VCHIQ_MSG_OPENACK 3 // + (srcport, dstport) ++#define VCHIQ_MSG_CLOSE 4 // + (srcport, dstport) ++#define VCHIQ_MSG_DATA 5 // + (srcport, dstport) ++#define VCHIQ_MSG_BULK_RX 6 // + (srcport, dstport), data, size ++#define VCHIQ_MSG_BULK_TX 7 // + (srcport, dstport), data, size ++#define VCHIQ_MSG_BULK_RX_DONE 8 // + (srcport, dstport), actual ++#define VCHIQ_MSG_BULK_TX_DONE 9 // + (srcport, dstport), actual ++#define VCHIQ_MSG_PAUSE 10 // - ++#define VCHIQ_MSG_RESUME 11 // - ++#define VCHIQ_MSG_REMOTE_USE 12 // - ++#define VCHIQ_MSG_REMOTE_RELEASE 13 // - ++#define VCHIQ_MSG_REMOTE_USE_ACTIVE 14 // - + + #define VCHIQ_PORT_MAX (VCHIQ_MAX_SERVICES - 1) + #define VCHIQ_PORT_FREE 0x1000 + #define VCHIQ_PORT_IS_VALID(port) (port < VCHIQ_PORT_FREE) +-#define VCHIQ_MAKE_MSG(type, srcport, dstport) \ +- ((type<<24) | (srcport<<12) | (dstport<<0)) ++#define VCHIQ_MAKE_MSG(type,srcport,dstport) ((type<<24) | (srcport<<12) | (dstport<<0)) + #define VCHIQ_MSG_TYPE(msgid) ((unsigned int)msgid >> 24) +-#define VCHIQ_MSG_SRCPORT(msgid) \ +- (unsigned short)(((unsigned int)msgid >> 12) & 0xfff) +-#define VCHIQ_MSG_DSTPORT(msgid) \ +- ((unsigned short)msgid & 0xfff) ++#define VCHIQ_MSG_SRCPORT(msgid) (unsigned short)(((unsigned int)msgid >> 12) & 0xfff) ++#define VCHIQ_MSG_DSTPORT(msgid) ((unsigned short)msgid & 0xfff) + + #define VCHIQ_FOURCC_AS_4CHARS(fourcc) \ +- ((fourcc) >> 24) & 0xff, \ +- ((fourcc) >> 16) & 0xff, \ +- ((fourcc) >> 8) & 0xff, \ +- (fourcc) & 0xff ++ ((fourcc) >> 24) & 0xff, \ ++ ((fourcc) >> 16) & 0xff, \ ++ ((fourcc) >> 8) & 0xff, \ ++ ((fourcc) ) & 0xff + + /* Ensure the fields are wide enough */ +-vchiq_static_assert(VCHIQ_MSG_SRCPORT(VCHIQ_MAKE_MSG(0, 0, VCHIQ_PORT_MAX)) +- == 0); +-vchiq_static_assert(VCHIQ_MSG_TYPE(VCHIQ_MAKE_MSG(0, VCHIQ_PORT_MAX, 0)) == 0); +-vchiq_static_assert((unsigned int)VCHIQ_PORT_MAX < +- (unsigned int)VCHIQ_PORT_FREE); ++vcos_static_assert(VCHIQ_MSG_SRCPORT(VCHIQ_MAKE_MSG(0,0,VCHIQ_PORT_MAX)) == 0); ++vcos_static_assert(VCHIQ_MSG_TYPE(VCHIQ_MAKE_MSG(0,VCHIQ_PORT_MAX,0)) == 0); ++vcos_static_assert((unsigned int)VCHIQ_PORT_MAX < (unsigned int)VCHIQ_PORT_FREE); + +-#define VCHIQ_MSGID_PADDING VCHIQ_MAKE_MSG(VCHIQ_MSG_PADDING, 0, 0) ++#define VCHIQ_MSGID_PADDING VCHIQ_MAKE_MSG(VCHIQ_MSG_PADDING,0,0) + #define VCHIQ_MSGID_CLAIMED 0x40000000 + + #define VCHIQ_FOURCC_INVALID 0x00000000 +@@ -127,7 +80,7 @@ + + typedef uint32_t BITSET_T; + +-vchiq_static_assert((sizeof(BITSET_T) * 8) == 32); ++vcos_static_assert((sizeof(BITSET_T) * 8) == 32); + + #define BITSET_SIZE(b) ((b + 31) >> 5) + #define BITSET_WORD(b) (b >> 5) +@@ -138,380 +91,314 @@ + #define BITSET_CLR(bs, b) (bs[BITSET_WORD(b)] &= ~BITSET_BIT(b)) + + #if VCHIQ_ENABLE_STATS +-#define VCHIQ_STATS_INC(state, stat) (state->stats. stat++) +-#define VCHIQ_SERVICE_STATS_INC(service, stat) (service->stats. stat++) +-#define VCHIQ_SERVICE_STATS_ADD(service, stat, addend) \ +- (service->stats. stat += addend) ++#define VCHIQ_STATS_INC(state, stat) (state->stats. stat ++) ++#define VCHIQ_SERVICE_STATS_INC(service, stat) (service->stats. stat ++) ++#define VCHIQ_SERVICE_STATS_ADD(service, stat, addend) (service->stats. stat += addend) + #else + #define VCHIQ_STATS_INC(state, stat) ((void)0) + #define VCHIQ_SERVICE_STATS_INC(service, stat) ((void)0) + #define VCHIQ_SERVICE_STATS_ADD(service, stat, addend) ((void)0) + #endif + +-enum { +- DEBUG_ENTRIES, ++enum ++{ ++ DEBUG_ENTRIES, + #if VCHIQ_ENABLE_DEBUG +- DEBUG_SLOT_HANDLER_COUNT, +- DEBUG_SLOT_HANDLER_LINE, +- DEBUG_PARSE_LINE, +- DEBUG_PARSE_HEADER, +- DEBUG_PARSE_MSGID, +- DEBUG_AWAIT_COMPLETION_LINE, +- DEBUG_DEQUEUE_MESSAGE_LINE, +- DEBUG_SERVICE_CALLBACK_LINE, +- DEBUG_MSG_QUEUE_FULL_COUNT, +- DEBUG_COMPLETION_QUEUE_FULL_COUNT, ++ DEBUG_SLOT_HANDLER_COUNT, ++ DEBUG_SLOT_HANDLER_LINE, ++ DEBUG_PARSE_LINE, ++ DEBUG_PARSE_HEADER, ++ DEBUG_PARSE_MSGID, ++ DEBUG_AWAIT_COMPLETION_LINE, ++ DEBUG_DEQUEUE_MESSAGE_LINE, ++ DEBUG_SERVICE_CALLBACK_LINE, ++ DEBUG_MSG_QUEUE_FULL_COUNT, ++ DEBUG_COMPLETION_QUEUE_FULL_COUNT, + #endif +- DEBUG_MAX ++ DEBUG_MAX + }; + + #if VCHIQ_ENABLE_DEBUG + +-#define DEBUG_INITIALISE(local) int *debug_ptr = (local)->debug; +-#define DEBUG_TRACE(d) \ +- do { debug_ptr[DEBUG_ ## d] = __LINE__; dsb(); } while (0) +-#define DEBUG_VALUE(d, v) \ +- do { debug_ptr[DEBUG_ ## d] = (v); dsb(); } while (0) +-#define DEBUG_COUNT(d) \ +- do { debug_ptr[DEBUG_ ## d]++; dsb(); } while (0) ++#define DEBUG_INITIALISE(local) volatile int *debug_ptr = (local)->debug; ++#define DEBUG_TRACE(d) debug_ptr[DEBUG_ ## d] = __LINE__ ++#define DEBUG_VALUE(d,v) debug_ptr[DEBUG_ ## d] = (v) ++#define DEBUG_COUNT(d) debug_ptr[DEBUG_ ## d]++ + + #else /* VCHIQ_ENABLE_DEBUG */ + + #define DEBUG_INITIALISE(local) + #define DEBUG_TRACE(d) +-#define DEBUG_VALUE(d, v) ++#define DEBUG_VALUE(d,v) + #define DEBUG_COUNT(d) + + #endif /* VCHIQ_ENABLE_DEBUG */ + +-typedef enum { +- VCHIQ_CONNSTATE_DISCONNECTED, +- VCHIQ_CONNSTATE_CONNECTING, +- VCHIQ_CONNSTATE_CONNECTED, +- VCHIQ_CONNSTATE_PAUSING, +- VCHIQ_CONNSTATE_PAUSE_SENT, +- VCHIQ_CONNSTATE_PAUSED, +- VCHIQ_CONNSTATE_RESUMING ++typedef enum ++{ ++ VCHIQ_CONNSTATE_DISCONNECTED, ++ VCHIQ_CONNSTATE_CONNECTED, ++ VCHIQ_CONNSTATE_PAUSING, ++ VCHIQ_CONNSTATE_PAUSE_SENT, ++ VCHIQ_CONNSTATE_PAUSED, ++ VCHIQ_CONNSTATE_RESUMING + } VCHIQ_CONNSTATE_T; + +-enum { +- VCHIQ_SRVSTATE_FREE, +- VCHIQ_SRVSTATE_HIDDEN, +- VCHIQ_SRVSTATE_LISTENING, +- VCHIQ_SRVSTATE_OPENING, +- VCHIQ_SRVSTATE_OPEN, +- VCHIQ_SRVSTATE_OPENSYNC, +- VCHIQ_SRVSTATE_CLOSESENT, +- VCHIQ_SRVSTATE_CLOSERECVD, +- VCHIQ_SRVSTATE_CLOSEWAIT, +- VCHIQ_SRVSTATE_CLOSED ++enum ++{ ++ VCHIQ_SRVSTATE_FREE, ++ VCHIQ_SRVSTATE_HIDDEN, ++ VCHIQ_SRVSTATE_LISTENING, ++ VCHIQ_SRVSTATE_OPENING, ++ VCHIQ_SRVSTATE_OPEN, ++ VCHIQ_SRVSTATE_CLOSESENT, ++ VCHIQ_SRVSTATE_CLOSING, ++ VCHIQ_SRVSTATE_CLOSEWAIT + }; + +-enum { +- VCHIQ_POLL_TERMINATE, +- VCHIQ_POLL_TXNOTIFY, +- VCHIQ_POLL_RXNOTIFY, +- VCHIQ_POLL_COUNT ++enum ++{ ++ VCHIQ_POLL_TERMINATE, ++ VCHIQ_POLL_TXNOTIFY, ++ VCHIQ_POLL_RXNOTIFY, ++ VCHIQ_POLL_COUNT + }; + +-typedef enum { +- VCHIQ_BULK_TRANSMIT, +- VCHIQ_BULK_RECEIVE ++typedef enum ++{ ++ VCHIQ_BULK_TRANSMIT, ++ VCHIQ_BULK_RECEIVE + } VCHIQ_BULK_DIR_T; + + typedef struct vchiq_bulk_struct { +- short mode; +- short dir; +- void *userdata; +- VCHI_MEM_HANDLE_T handle; +- void *data; +- int size; +- void *remote_data; +- int remote_size; +- int actual; ++ short mode; ++ short dir; ++ void *userdata; ++ VCHI_MEM_HANDLE_T handle; ++ void *data; ++ int size; ++ void *remote_data; ++ int remote_size; ++ int actual; + } VCHIQ_BULK_T; + + typedef struct vchiq_bulk_queue_struct { +- int local_insert; /* Where to insert the next local bulk */ +- int remote_insert; /* Where to insert the next remote bulk (master) */ +- int process; /* Bulk to transfer next */ +- int remote_notify; /* Bulk to notify the remote client of next (mstr) */ +- int remove; /* Bulk to notify the local client of, and remove, +- ** next */ +- VCHIQ_BULK_T bulks[VCHIQ_NUM_SERVICE_BULKS]; ++ int local_insert; /* Where to insert the next local bulk */ ++ int remote_insert; /* Where to insert the next remote bulk (master) */ ++ int process; /* Bulk to transfer next */ ++ int remote_notify; /* Bulk to notify the remote client of next (master) */ ++ int remove; /* Bulk to notify the local client of, and remove, next */ ++ VCHIQ_BULK_T bulks[VCHIQ_NUM_SERVICE_BULKS]; + } VCHIQ_BULK_QUEUE_T; + + typedef struct remote_event_struct { +- int armed; +- int fired; +- struct semaphore *event; ++ volatile int armed; ++ volatile int fired; ++ VCOS_EVENT_T * event; + } REMOTE_EVENT_T; + +-typedef struct opaque_platform_state_t *VCHIQ_PLATFORM_STATE_T; ++typedef struct opaque_platform_state_t* VCHIQ_PLATFORM_STATE_T; + + typedef struct vchiq_state_struct VCHIQ_STATE_T; + + typedef struct vchiq_slot_struct { +- char data[VCHIQ_SLOT_SIZE]; ++ char data[VCHIQ_SLOT_SIZE]; + } VCHIQ_SLOT_T; + + typedef struct vchiq_slot_info_struct { +- /* Use two counters rather than one to avoid the need for a mutex. */ +- short use_count; +- short release_count; ++ /* Use two counters rather than one to avoid the need for a mutex. */ ++ volatile short use_count; ++ volatile short release_count; + } VCHIQ_SLOT_INFO_T; + + typedef struct vchiq_service_struct { +- VCHIQ_SERVICE_BASE_T base; +- VCHIQ_SERVICE_HANDLE_T handle; +- unsigned int ref_count; +- int srvstate; +- unsigned int localport; +- unsigned int remoteport; +- int public_fourcc; +- int client_id; +- char auto_close; +- char sync; +- char closing; +- atomic_t poll_flags; +- short version; +- short version_min; +- +- VCHIQ_STATE_T *state; +- VCHIQ_INSTANCE_T instance; +- +- int service_use_count; +- +- VCHIQ_BULK_QUEUE_T bulk_tx; +- VCHIQ_BULK_QUEUE_T bulk_rx; +- +- struct semaphore remove_event; +- struct semaphore bulk_remove_event; +- struct mutex bulk_mutex; +- +- struct service_stats_struct { +- int quota_stalls; +- int slot_stalls; +- int bulk_stalls; +- int error_count; +- int ctrl_tx_count; +- int ctrl_rx_count; +- int bulk_tx_count; +- int bulk_rx_count; +- int bulk_aborted_count; +- uint64_t ctrl_tx_bytes; +- uint64_t ctrl_rx_bytes; +- uint64_t bulk_tx_bytes; +- uint64_t bulk_rx_bytes; +- } stats; ++ VCHIQ_SERVICE_BASE_T base; ++ volatile int srvstate; ++ unsigned int localport; ++ unsigned int remoteport; ++ int public_fourcc; ++ int client_id; ++ int auto_close; ++ VCOS_ATOMIC_FLAGS_T poll_flags; ++ short version; ++ short version_min; ++ ++ VCHIQ_STATE_T *state; ++ VCHIQ_INSTANCE_T instance; ++ ++ int service_use_count; ++ ++ VCHIQ_BULK_QUEUE_T bulk_tx; ++ VCHIQ_BULK_QUEUE_T bulk_rx; ++ ++ VCOS_EVENT_T remove_event; ++ VCOS_EVENT_T bulk_remove_event; ++ VCOS_MUTEX_T bulk_mutex; ++ ++ struct service_stats_struct ++ { ++ int quota_stalls; ++ int slot_stalls; ++ int bulk_stalls; ++ int error_count; ++ int ctrl_tx_count; ++ int ctrl_rx_count; ++ int bulk_tx_count; ++ int bulk_rx_count; ++ int bulk_aborted_count; ++ uint64_t ctrl_tx_bytes; ++ uint64_t ctrl_rx_bytes; ++ uint64_t bulk_tx_bytes; ++ uint64_t bulk_rx_bytes; ++ } stats; + } VCHIQ_SERVICE_T; + + /* The quota information is outside VCHIQ_SERVICE_T so that it can be +- statically allocated, since for accounting reasons a service's slot +- usage is carried over between users of the same port number. ++ statically allocated, since for accounting reasons a service's slot ++ usage is carried over between users of the same port number. + */ + typedef struct vchiq_service_quota_struct { +- unsigned short slot_quota; +- unsigned short slot_use_count; +- unsigned short message_quota; +- unsigned short message_use_count; +- struct semaphore quota_event; +- int previous_tx_index; ++ unsigned short slot_quota; ++ unsigned short slot_use_count; ++ unsigned short message_quota; ++ unsigned short message_use_count; ++ VCOS_EVENT_T quota_event; ++ int previous_tx_index; + } VCHIQ_SERVICE_QUOTA_T; + + typedef struct vchiq_shared_state_struct { + +- /* A non-zero value here indicates that the content is valid. */ +- int initialised; +- +- /* The first and last (inclusive) slots allocated to the owner. */ +- int slot_first; +- int slot_last; +- +- /* The slot allocated to synchronous messages from the owner. */ +- int slot_sync; +- +- /* Signalling this event indicates that owner's slot handler thread +- ** should run. */ +- REMOTE_EVENT_T trigger; ++ /* A non-zero value here indicates that the content is valid. */ ++ int initialised; + +- /* Indicates the byte position within the stream where the next message +- ** will be written. The least significant bits are an index into the +- ** slot. The next bits are the index of the slot in slot_queue. */ +- int tx_pos; ++ /* The first and last (inclusive) slots allocated to the owner. */ ++ int slot_first; ++ int slot_last; + +- /* This event should be signalled when a slot is recycled. */ +- REMOTE_EVENT_T recycle; ++ /* Signalling this event indicates that owner's slot handler thread should ++ run. */ ++ REMOTE_EVENT_T trigger; + +- /* The slot_queue index where the next recycled slot will be written. */ +- int slot_queue_recycle; ++ /* Indicates the byte position within the stream where the next message ++ will be written. The least significant bits are an index into the slot. ++ The next bits are the index of the slot in slot_queue. */ ++ volatile int tx_pos; + +- /* This event should be signalled when a synchronous message is sent. */ +- REMOTE_EVENT_T sync_trigger; ++ /* This event should be signalled when a slot is recycled. */ ++ REMOTE_EVENT_T recycle; + +- /* This event should be signalled when a synchronous message has been +- ** released. */ +- REMOTE_EVENT_T sync_release; ++ /* The slot_queue index where the next recycled slot will be written. */ ++ volatile int slot_queue_recycle; + +- /* A circular buffer of slot indexes. */ +- int slot_queue[VCHIQ_MAX_SLOTS_PER_SIDE]; ++ /* A circular buffer of slot indexes. */ ++ int slot_queue[VCHIQ_MAX_SLOTS_PER_SIDE]; + +- /* Debugging state */ +- int debug[DEBUG_MAX]; ++ /* Debugging state */ ++ volatile int debug[DEBUG_MAX]; + } VCHIQ_SHARED_STATE_T; + + typedef struct vchiq_slot_zero_struct { +- int magic; +- short version; +- short version_min; +- int slot_zero_size; +- int slot_size; +- int max_slots; +- int max_slots_per_side; +- int platform_data[2]; +- VCHIQ_SHARED_STATE_T master; +- VCHIQ_SHARED_STATE_T slave; +- VCHIQ_SLOT_INFO_T slots[VCHIQ_MAX_SLOTS]; ++ int magic; ++ short version; ++ short version_min; ++ int slot_zero_size; ++ int slot_size; ++ int max_slots; ++ int max_slots_per_side; ++ int platform_data[2]; ++ VCHIQ_SHARED_STATE_T master; ++ VCHIQ_SHARED_STATE_T slave; ++ VCHIQ_SLOT_INFO_T slots[VCHIQ_MAX_SLOTS]; + } VCHIQ_SLOT_ZERO_T; + + struct vchiq_state_struct { +- int id; +- int initialised; +- VCHIQ_CONNSTATE_T conn_state; +- int is_master; ++ int id; ++ int initialised; ++ VCHIQ_CONNSTATE_T conn_state; ++ int is_master; + +- VCHIQ_SHARED_STATE_T *local; +- VCHIQ_SHARED_STATE_T *remote; +- VCHIQ_SLOT_T *slot_data; ++ VCHIQ_SHARED_STATE_T *local; ++ VCHIQ_SHARED_STATE_T *remote; ++ VCHIQ_SLOT_T *slot_data; + +- unsigned short default_slot_quota; +- unsigned short default_message_quota; ++ unsigned short default_slot_quota; ++ unsigned short default_message_quota; + +- /* Event indicating connect message received */ +- struct semaphore connect; ++ VCOS_EVENT_T connect; // event indicating connect message received ++ VCOS_MUTEX_T mutex; // mutex protecting services ++ VCHIQ_INSTANCE_T *instance; + +- /* Mutex protecting services */ +- struct mutex mutex; +- VCHIQ_INSTANCE_T *instance; ++ VCOS_THREAD_T slot_handler_thread; // processes incoming messages ++ VCOS_THREAD_T recycle_thread; // processes recycled slots + +- /* Processes incoming messages */ +- struct task_struct *slot_handler_thread; ++ /* Local implementation of the trigger remote event */ ++ VCOS_EVENT_T trigger_event; + +- /* Processes recycled slots */ +- struct task_struct *recycle_thread; ++ /* Local implementation of the recycle remote event */ ++ VCOS_EVENT_T recycle_event; + +- /* Processes synchronous messages */ +- struct task_struct *sync_thread; ++ char *tx_data; ++ char *rx_data; ++ VCHIQ_SLOT_INFO_T *rx_info; + +- /* Local implementation of the trigger remote event */ +- struct semaphore trigger_event; ++ VCOS_MUTEX_T slot_mutex; + +- /* Local implementation of the recycle remote event */ +- struct semaphore recycle_event; ++ VCOS_MUTEX_T recycle_mutex; + +- /* Local implementation of the sync trigger remote event */ +- struct semaphore sync_trigger_event; ++ /* Indicates the byte position within the stream from where the next message ++ will be read. The least significant bits are an index into the slot. ++ The next bits are the index of the slot in remote->slot_queue. */ ++ int rx_pos; + +- /* Local implementation of the sync release remote event */ +- struct semaphore sync_release_event; ++ /* A cached copy of local->tx_pos. Only write to local->tx_pos, and read ++ from remote->tx_pos. */ ++ int local_tx_pos; + +- char *tx_data; +- char *rx_data; +- VCHIQ_SLOT_INFO_T *rx_info; ++ /* The slot_queue index of the slot to become available next. */ ++ int slot_queue_available; + +- struct mutex slot_mutex; ++ /* A flag to indicate if any poll has been requested */ ++ int poll_needed; + +- struct mutex recycle_mutex; ++ /* An array of bit sets indicating which services must be polled. */ ++ VCOS_ATOMIC_FLAGS_T poll_services[BITSET_SIZE(VCHIQ_MAX_SERVICES)]; + +- struct mutex sync_mutex; ++ /* The number of the first unused service */ ++ int unused_service; + +- struct mutex bulk_transfer_mutex; ++ /* Signalled when a free slot becomes available. */ ++ VCOS_EVENT_T slot_available_event; + +- /* Indicates the byte position within the stream from where the next +- ** message will be read. The least significant bits are an index into +- ** the slot.The next bits are the index of the slot in +- ** remote->slot_queue. */ +- int rx_pos; ++ VCOS_EVENT_T slot_remove_event; + +- /* A cached copy of local->tx_pos. Only write to local->tx_pos, and read +- from remote->tx_pos. */ +- int local_tx_pos; ++ struct state_stats_struct ++ { ++ int slot_stalls; ++ int ctrl_tx_count; ++ int ctrl_rx_count; ++ int error_count; ++ } stats; + +- /* The slot_queue index of the slot to become available next. */ +- int slot_queue_available; ++ VCHIQ_SERVICE_T *services[VCHIQ_MAX_SERVICES]; ++ VCHIQ_SERVICE_QUOTA_T service_quotas[VCHIQ_MAX_SERVICES]; ++ VCHIQ_SLOT_INFO_T slot_info[VCHIQ_MAX_SLOTS]; + +- /* A flag to indicate if any poll has been requested */ +- int poll_needed; +- +- /* Ths index of the previous slot used for data messages. */ +- int previous_data_index; +- +- /* The number of slots occupied by data messages. */ +- unsigned short data_use_count; +- +- /* The maximum number of slots to be occupied by data messages. */ +- unsigned short data_quota; +- +- /* An array of bit sets indicating which services must be polled. */ +- atomic_t poll_services[BITSET_SIZE(VCHIQ_MAX_SERVICES)]; +- +- /* The number of the first unused service */ +- int unused_service; +- +- /* Signalled when a free slot becomes available. */ +- struct semaphore slot_available_event; +- +- struct semaphore slot_remove_event; +- +- /* Signalled when a free data slot becomes available. */ +- struct semaphore data_quota_event; +- +- struct state_stats_struct { +- int slot_stalls; +- int data_stalls; +- int ctrl_tx_count; +- int ctrl_rx_count; +- int error_count; +- } stats; +- +- VCHIQ_SERVICE_T * services[VCHIQ_MAX_SERVICES]; +- VCHIQ_SERVICE_QUOTA_T service_quotas[VCHIQ_MAX_SERVICES]; +- VCHIQ_SLOT_INFO_T slot_info[VCHIQ_MAX_SLOTS]; +- +- VCHIQ_PLATFORM_STATE_T platform_state; +-}; +- +-struct bulk_waiter { +- VCHIQ_BULK_T *bulk; +- struct semaphore event; +- int actual; ++ VCHIQ_PLATFORM_STATE_T platform_state; + }; + +-extern spinlock_t bulk_waiter_spinlock; +- +-extern int vchiq_core_log_level; +-extern int vchiq_core_msg_log_level; +-extern int vchiq_sync_log_level; +- +-extern VCHIQ_STATE_T *vchiq_states[VCHIQ_MAX_STATES]; +- +-extern const char * +-get_conn_state_name(VCHIQ_CONNSTATE_T conn_state); +- + extern VCHIQ_SLOT_ZERO_T * + vchiq_init_slots(void *mem_base, int mem_size); + + extern VCHIQ_STATUS_T +-vchiq_init_state(VCHIQ_STATE_T *state, VCHIQ_SLOT_ZERO_T *slot_zero, +- int is_master); ++vchiq_init_state(VCHIQ_STATE_T *state, VCHIQ_SLOT_ZERO_T *slot_zero, int is_master); + + extern VCHIQ_STATUS_T + vchiq_connect_internal(VCHIQ_STATE_T *state, VCHIQ_INSTANCE_T instance); + + extern VCHIQ_SERVICE_T * + vchiq_add_service_internal(VCHIQ_STATE_T *state, +- const VCHIQ_SERVICE_PARAMS_T *params, int srvstate, +- VCHIQ_INSTANCE_T instance); ++ const VCHIQ_SERVICE_PARAMS_T *params, int srvstate, ++ VCHIQ_INSTANCE_T instance); + + extern VCHIQ_STATUS_T + vchiq_open_service_internal(VCHIQ_SERVICE_T *service, int client_id); +@@ -538,9 +425,9 @@ + remote_event_pollall(VCHIQ_STATE_T *state); + + extern VCHIQ_STATUS_T +-vchiq_bulk_transfer(VCHIQ_SERVICE_HANDLE_T handle, +- VCHI_MEM_HANDLE_T memhandle, void *offset, int size, void *userdata, +- VCHIQ_BULK_MODE_T mode, VCHIQ_BULK_DIR_T dir); ++vchiq_bulk_transfer(VCHIQ_SERVICE_T *service, ++ VCHI_MEM_HANDLE_T memhandle, void *offset, int size, void *userdata, ++ VCHIQ_BULK_MODE_T mode, VCHIQ_BULK_DIR_T dir); + + extern void + vchiq_dump_state(void *dump_context, VCHIQ_STATE_T *state); +@@ -548,52 +435,12 @@ + extern void + vchiq_dump_service_state(void *dump_context, VCHIQ_SERVICE_T *service); + +-extern void +-vchiq_loud_error_header(void); +- +-extern void +-vchiq_loud_error_footer(void); +- +-extern void +-request_poll(VCHIQ_STATE_T *state, VCHIQ_SERVICE_T *service, int poll_type); +- +-static inline VCHIQ_SERVICE_T * +-handle_to_service(VCHIQ_SERVICE_HANDLE_T handle) +-{ +- VCHIQ_STATE_T *state = vchiq_states[(handle / VCHIQ_MAX_SERVICES) & +- (VCHIQ_MAX_STATES - 1)]; +- if (!state) +- return NULL; +- +- return state->services[handle & (VCHIQ_MAX_SERVICES - 1)]; +-} +- +-extern VCHIQ_SERVICE_T * +-find_service_by_handle(VCHIQ_SERVICE_HANDLE_T handle); +- +-extern VCHIQ_SERVICE_T * +-find_service_by_port(VCHIQ_STATE_T *state, int localport); +- +-extern VCHIQ_SERVICE_T * +-find_service_for_instance(VCHIQ_INSTANCE_T instance, +- VCHIQ_SERVICE_HANDLE_T handle); +- +-extern VCHIQ_SERVICE_T * +-next_service_by_instance(VCHIQ_STATE_T *state, VCHIQ_INSTANCE_T instance, +- int *pidx); +- +-extern void +-lock_service(VCHIQ_SERVICE_T *service); +- +-extern void +-unlock_service(VCHIQ_SERVICE_T *service); +- + /* The following functions are called from vchiq_core, and external +-** implementations must be provided. */ ++ implementations must be provided. */ + + extern VCHIQ_STATUS_T + vchiq_prepare_bulk_data(VCHIQ_BULK_T *bulk, +- VCHI_MEM_HANDLE_T memhandle, void *offset, int size, int dir); ++ VCHI_MEM_HANDLE_T memhandle, void *offset, int size, int dir); + + extern void + vchiq_transfer_bulk(VCHIQ_BULK_T *bulk); +@@ -607,15 +454,9 @@ + extern void + remote_event_signal(REMOTE_EVENT_T *event); + +-void +-vchiq_platform_check_suspend(VCHIQ_STATE_T *state); +- + extern void + vchiq_platform_paused(VCHIQ_STATE_T *state); + +-extern VCHIQ_STATUS_T +-vchiq_platform_resume(VCHIQ_STATE_T *state); +- + extern void + vchiq_platform_resumed(VCHIQ_STATE_T *state); + +@@ -630,7 +471,7 @@ + + extern void + vchiq_dump_platform_service_state(void *dump_context, +- VCHIQ_SERVICE_T *service); ++ VCHIQ_SERVICE_T *service); + + extern VCHIQ_STATUS_T + vchiq_use_service_internal(VCHIQ_SERVICE_T *service); +@@ -638,36 +479,28 @@ + extern VCHIQ_STATUS_T + vchiq_release_service_internal(VCHIQ_SERVICE_T *service); + +-extern void ++extern VCHIQ_STATUS_T + vchiq_on_remote_use(VCHIQ_STATE_T *state); + +-extern void ++extern VCHIQ_STATUS_T + vchiq_on_remote_release(VCHIQ_STATE_T *state); + + extern VCHIQ_STATUS_T + vchiq_platform_init_state(VCHIQ_STATE_T *state); + +-extern VCHIQ_STATUS_T +-vchiq_check_service(VCHIQ_SERVICE_T *service); +- + extern void + vchiq_on_remote_use_active(VCHIQ_STATE_T *state); + + extern VCHIQ_STATUS_T +-vchiq_send_remote_use(VCHIQ_STATE_T *state); ++vchiq_send_remote_use(VCHIQ_STATE_T * state); + + extern VCHIQ_STATUS_T +-vchiq_send_remote_release(VCHIQ_STATE_T *state); ++vchiq_send_remote_release(VCHIQ_STATE_T * state); + + extern VCHIQ_STATUS_T +-vchiq_send_remote_use_active(VCHIQ_STATE_T *state); +- +-extern void +-vchiq_platform_conn_state_changed(VCHIQ_STATE_T *state, +- VCHIQ_CONNSTATE_T oldstate, VCHIQ_CONNSTATE_T newstate); ++vchiq_send_remote_use_active(VCHIQ_STATE_T * state); + + extern void +-vchiq_log_dump_mem(const char *label, uint32_t addr, const void *voidMem, +- size_t numBytes); ++vchiq_platform_conn_state_changed(VCHIQ_STATE_T* state, VCHIQ_CONNSTATE_T oldstate, VCHIQ_CONNSTATE_T newstate); + + #endif +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_if.h +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_if.h 2013-07-26 19:36:51.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_if.h 2013-07-26 19:37:11.000000000 +0000 +@@ -21,145 +21,135 @@ + + #include "interface/vchi/vchi_mh.h" + +-#define VCHIQ_SERVICE_HANDLE_INVALID 0 +- +-#define VCHIQ_SLOT_SIZE 4096 +-#define VCHIQ_MAX_MSG_SIZE (VCHIQ_SLOT_SIZE - sizeof(VCHIQ_HEADER_T)) +-#define VCHIQ_CHANNEL_SIZE VCHIQ_MAX_MSG_SIZE /* For backwards compatibility */ +- +-#define VCHIQ_MAKE_FOURCC(x0, x1, x2, x3) \ +- (((x0) << 24) | ((x1) << 16) | ((x2) << 8) | (x3)) +-#define VCHIQ_GET_SERVICE_USERDATA(service) vchiq_get_service_userdata(service) +-#define VCHIQ_GET_SERVICE_FOURCC(service) vchiq_get_service_fourcc(service) ++#define VCHIQ_SLOT_SIZE 4096 ++#define VCHIQ_MAX_MSG_SIZE (VCHIQ_SLOT_SIZE - sizeof(VCHIQ_HEADER_T)) ++#define VCHIQ_CHANNEL_SIZE VCHIQ_MAX_MSG_SIZE /* For backwards compatibility */ ++ ++#define VCHIQ_MAKE_FOURCC(x0, x1, x2, x3) (((x0) << 24) | ((x1) << 16) | ((x2) << 8) | (x3)) ++#define VCHIQ_GET_SERVICE_USERDATA(service) (service->userdata) ++#define VCHIQ_GET_SERVICE_FOURCC(service) (service->fourcc) + + typedef enum { +- VCHIQ_SERVICE_OPENED, /* service, -, - */ +- VCHIQ_SERVICE_CLOSED, /* service, -, - */ +- VCHIQ_MESSAGE_AVAILABLE, /* service, header, - */ +- VCHIQ_BULK_TRANSMIT_DONE, /* service, -, bulk_userdata */ +- VCHIQ_BULK_RECEIVE_DONE, /* service, -, bulk_userdata */ +- VCHIQ_BULK_TRANSMIT_ABORTED, /* service, -, bulk_userdata */ +- VCHIQ_BULK_RECEIVE_ABORTED /* service, -, bulk_userdata */ ++ VCHIQ_SERVICE_OPENED, // service, -, - ++ VCHIQ_SERVICE_CLOSED, // service, -, - ++ VCHIQ_MESSAGE_AVAILABLE, // service, header, - ++ VCHIQ_BULK_TRANSMIT_DONE, // service, -, bulk_userdata ++ VCHIQ_BULK_RECEIVE_DONE, // service, -, bulk_userdata ++ VCHIQ_BULK_TRANSMIT_ABORTED, // service, -, bulk_userdata ++ VCHIQ_BULK_RECEIVE_ABORTED // service, -, bulk_userdata + } VCHIQ_REASON_T; + +-typedef enum { +- VCHIQ_ERROR = -1, +- VCHIQ_SUCCESS = 0, +- VCHIQ_RETRY = 1 ++typedef enum ++{ ++ VCHIQ_ERROR = -1, ++ VCHIQ_SUCCESS = 0, ++ VCHIQ_RETRY = 1 + } VCHIQ_STATUS_T; + +-typedef enum { +- VCHIQ_BULK_MODE_CALLBACK, +- VCHIQ_BULK_MODE_BLOCKING, +- VCHIQ_BULK_MODE_NOCALLBACK, +- VCHIQ_BULK_MODE_WAITING /* Reserved for internal use */ ++typedef enum ++{ ++ VCHIQ_BULK_MODE_CALLBACK, ++ VCHIQ_BULK_MODE_BLOCKING, ++ VCHIQ_BULK_MODE_NOCALLBACK + } VCHIQ_BULK_MODE_T; + +-typedef enum { +- VCHIQ_SERVICE_OPTION_AUTOCLOSE, +- VCHIQ_SERVICE_OPTION_SLOT_QUOTA, +- VCHIQ_SERVICE_OPTION_MESSAGE_QUOTA, +- VCHIQ_SERVICE_OPTION_SYNCHRONOUS ++typedef enum ++{ ++ VCHIQ_SERVICE_OPTION_AUTOCLOSE, ++ VCHIQ_SERVICE_OPTION_SLOT_QUOTA, ++ VCHIQ_SERVICE_OPTION_MESSAGE_QUOTA + } VCHIQ_SERVICE_OPTION_T; + ++#ifdef __HIGHC__ ++/* Allow zero-sized arrays without warnings */ ++#pragma warning (push) ++#pragma warning (disable : 4200) ++#endif ++ + typedef struct vchiq_header_struct { +- /* The message identifier - opaque to applications. */ +- int msgid; ++ /* The message identifier - opaque to applications. */ ++ int msgid; + +- /* Size of message data. */ +- unsigned int size; ++ /* Size of message data. */ ++ unsigned int size; + +- char data[0]; /* message */ ++ char data[0]; /* message */ + } VCHIQ_HEADER_T; + ++#ifdef __HIGHC__ ++#pragma warning (pop) ++#endif ++ + typedef struct { +- const void *data; +- int size; ++ const void *data; ++ int size; + } VCHIQ_ELEMENT_T; + +-typedef unsigned int VCHIQ_SERVICE_HANDLE_T; ++typedef const struct vchiq_service_base_struct *VCHIQ_SERVICE_HANDLE_T; + +-typedef VCHIQ_STATUS_T (*VCHIQ_CALLBACK_T)(VCHIQ_REASON_T, VCHIQ_HEADER_T *, +- VCHIQ_SERVICE_HANDLE_T, void *); ++typedef VCHIQ_STATUS_T (*VCHIQ_CALLBACK_T)(VCHIQ_REASON_T, VCHIQ_HEADER_T *, VCHIQ_SERVICE_HANDLE_T, void *); + + typedef struct vchiq_service_base_struct { +- int fourcc; +- VCHIQ_CALLBACK_T callback; +- void *userdata; ++ int fourcc; ++ VCHIQ_CALLBACK_T callback; ++ void *userdata; + } VCHIQ_SERVICE_BASE_T; + + typedef struct vchiq_service_params_struct { +- int fourcc; +- VCHIQ_CALLBACK_T callback; +- void *userdata; +- short version; /* Increment for non-trivial changes */ +- short version_min; /* Update for incompatible changes */ ++ int fourcc; ++ VCHIQ_CALLBACK_T callback; ++ void *userdata; ++ short version; /* Increment for non-trivial changes */ ++ short version_min; /* Update for incompatible changes */ + } VCHIQ_SERVICE_PARAMS_T; + + typedef struct vchiq_config_struct { +- int max_msg_size; +- int bulk_threshold; /* The message size aboce which it is better to use +- a bulk transfer (<= max_msg_size) */ +- int max_outstanding_bulks; +- int max_services; +- short version; /* The version of VCHIQ */ +- short version_min; /* The minimum compatible version of VCHIQ */ ++ int max_msg_size; ++ int bulk_threshold; /* The message size aboce which it is better to use ++ a bulk transfer (<= max_msg_size) */ ++ int max_outstanding_bulks; ++ int max_services; ++ short version; /* The version of VCHIQ */ ++ short version_min; /* The minimum compatible version of VCHIQ */ + } VCHIQ_CONFIG_T; + + typedef struct vchiq_instance_struct *VCHIQ_INSTANCE_T; +-typedef void (*VCHIQ_REMOTE_USE_CALLBACK_T)(void *cb_arg); ++typedef void (*VCHIQ_REMOTE_USE_CALLBACK_T)(void* cb_arg); ++ + + extern VCHIQ_STATUS_T vchiq_initialise(VCHIQ_INSTANCE_T *pinstance); + extern VCHIQ_STATUS_T vchiq_shutdown(VCHIQ_INSTANCE_T instance); + extern VCHIQ_STATUS_T vchiq_connect(VCHIQ_INSTANCE_T instance); +-extern VCHIQ_STATUS_T vchiq_add_service(VCHIQ_INSTANCE_T instance, +- const VCHIQ_SERVICE_PARAMS_T *params, +- VCHIQ_SERVICE_HANDLE_T *pservice); +-extern VCHIQ_STATUS_T vchiq_open_service(VCHIQ_INSTANCE_T instance, +- const VCHIQ_SERVICE_PARAMS_T *params, +- VCHIQ_SERVICE_HANDLE_T *pservice); ++extern VCHIQ_STATUS_T vchiq_add_service(VCHIQ_INSTANCE_T instance, int fourcc, VCHIQ_CALLBACK_T callback, void *userdata, VCHIQ_SERVICE_HANDLE_T *pservice); ++extern VCHIQ_STATUS_T vchiq_open_service(VCHIQ_INSTANCE_T instance, int fourcc, VCHIQ_CALLBACK_T callback, void *userdata, VCHIQ_SERVICE_HANDLE_T *pservice); ++extern VCHIQ_STATUS_T vchiq_add_service_params(VCHIQ_INSTANCE_T instance, ++ const VCHIQ_SERVICE_PARAMS_T *params, ++ VCHIQ_SERVICE_HANDLE_T *pservice); ++extern VCHIQ_STATUS_T vchiq_open_service_params(VCHIQ_INSTANCE_T instance, ++ const VCHIQ_SERVICE_PARAMS_T *params, ++ VCHIQ_SERVICE_HANDLE_T *pservice); + extern VCHIQ_STATUS_T vchiq_close_service(VCHIQ_SERVICE_HANDLE_T service); + extern VCHIQ_STATUS_T vchiq_remove_service(VCHIQ_SERVICE_HANDLE_T service); + extern VCHIQ_STATUS_T vchiq_use_service(VCHIQ_SERVICE_HANDLE_T service); + extern VCHIQ_STATUS_T vchiq_release_service(VCHIQ_SERVICE_HANDLE_T service); + +-extern VCHIQ_STATUS_T vchiq_queue_message(VCHIQ_SERVICE_HANDLE_T service, +- const VCHIQ_ELEMENT_T *elements, int count); +-extern void vchiq_release_message(VCHIQ_SERVICE_HANDLE_T service, +- VCHIQ_HEADER_T *header); +-extern VCHIQ_STATUS_T vchiq_queue_bulk_transmit(VCHIQ_SERVICE_HANDLE_T service, +- const void *data, int size, void *userdata); +-extern VCHIQ_STATUS_T vchiq_queue_bulk_receive(VCHIQ_SERVICE_HANDLE_T service, +- void *data, int size, void *userdata); +-extern VCHIQ_STATUS_T vchiq_queue_bulk_transmit_handle( +- VCHIQ_SERVICE_HANDLE_T service, VCHI_MEM_HANDLE_T handle, +- const void *offset, int size, void *userdata); +-extern VCHIQ_STATUS_T vchiq_queue_bulk_receive_handle( +- VCHIQ_SERVICE_HANDLE_T service, VCHI_MEM_HANDLE_T handle, +- void *offset, int size, void *userdata); +-extern VCHIQ_STATUS_T vchiq_bulk_transmit(VCHIQ_SERVICE_HANDLE_T service, +- const void *data, int size, void *userdata, VCHIQ_BULK_MODE_T mode); +-extern VCHIQ_STATUS_T vchiq_bulk_receive(VCHIQ_SERVICE_HANDLE_T service, +- void *data, int size, void *userdata, VCHIQ_BULK_MODE_T mode); +-extern VCHIQ_STATUS_T vchiq_bulk_transmit_handle(VCHIQ_SERVICE_HANDLE_T service, +- VCHI_MEM_HANDLE_T handle, const void *offset, int size, void *userdata, +- VCHIQ_BULK_MODE_T mode); +-extern VCHIQ_STATUS_T vchiq_bulk_receive_handle(VCHIQ_SERVICE_HANDLE_T service, +- VCHI_MEM_HANDLE_T handle, void *offset, int size, void *userdata, +- VCHIQ_BULK_MODE_T mode); +-extern int vchiq_get_client_id(VCHIQ_SERVICE_HANDLE_T service); +-extern void *vchiq_get_service_userdata(VCHIQ_SERVICE_HANDLE_T service); +-extern int vchiq_get_service_fourcc(VCHIQ_SERVICE_HANDLE_T service); +-extern VCHIQ_STATUS_T vchiq_get_config(VCHIQ_INSTANCE_T instance, +- int config_size, VCHIQ_CONFIG_T *pconfig); +-extern VCHIQ_STATUS_T vchiq_set_service_option(VCHIQ_SERVICE_HANDLE_T service, +- VCHIQ_SERVICE_OPTION_T option, int value); ++extern VCHIQ_STATUS_T vchiq_queue_message(VCHIQ_SERVICE_HANDLE_T service, const VCHIQ_ELEMENT_T *elements, int count); ++extern void vchiq_release_message(VCHIQ_SERVICE_HANDLE_T service, VCHIQ_HEADER_T *header); ++extern VCHIQ_STATUS_T vchiq_queue_bulk_transmit(VCHIQ_SERVICE_HANDLE_T service, const void *data, int size, void *userdata); ++extern VCHIQ_STATUS_T vchiq_queue_bulk_receive(VCHIQ_SERVICE_HANDLE_T service, void *data, int size, void *userdata); ++extern VCHIQ_STATUS_T vchiq_queue_bulk_transmit_handle(VCHIQ_SERVICE_HANDLE_T service, VCHI_MEM_HANDLE_T handle, const void *offset, int size, void *userdata); ++extern VCHIQ_STATUS_T vchiq_queue_bulk_receive_handle(VCHIQ_SERVICE_HANDLE_T service, VCHI_MEM_HANDLE_T handle, void *offset, int size, void *userdata); ++extern VCHIQ_STATUS_T vchiq_bulk_transmit(VCHIQ_SERVICE_HANDLE_T service, const void *data, int size, void *userdata, VCHIQ_BULK_MODE_T mode); ++extern VCHIQ_STATUS_T vchiq_bulk_receive(VCHIQ_SERVICE_HANDLE_T service, void *data, int size, void *userdata, VCHIQ_BULK_MODE_T mode); ++extern VCHIQ_STATUS_T vchiq_bulk_transmit_handle(VCHIQ_SERVICE_HANDLE_T service, VCHI_MEM_HANDLE_T handle, const void *offset, int size, void *userdata, VCHIQ_BULK_MODE_T mode); ++extern VCHIQ_STATUS_T vchiq_bulk_receive_handle(VCHIQ_SERVICE_HANDLE_T service, VCHI_MEM_HANDLE_T handle, void *offset, int size, void *userdata, VCHIQ_BULK_MODE_T mode); ++extern int vchiq_get_client_id(VCHIQ_SERVICE_HANDLE_T service); ++extern VCHIQ_STATUS_T vchiq_get_config(VCHIQ_INSTANCE_T instance, int config_size, VCHIQ_CONFIG_T *pconfig); ++extern VCHIQ_STATUS_T vchiq_set_service_option(VCHIQ_SERVICE_HANDLE_T service, VCHIQ_SERVICE_OPTION_T option, int value); + +-extern VCHIQ_STATUS_T vchiq_remote_use(VCHIQ_INSTANCE_T instance, +- VCHIQ_REMOTE_USE_CALLBACK_T callback, void *cb_arg); ++extern VCHIQ_STATUS_T vchiq_remote_use(VCHIQ_INSTANCE_T instance, VCHIQ_REMOTE_USE_CALLBACK_T callback, void* cb_arg); + extern VCHIQ_STATUS_T vchiq_remote_release(VCHIQ_INSTANCE_T instance); + +-extern VCHIQ_STATUS_T vchiq_dump_phys_mem(VCHIQ_SERVICE_HANDLE_T service, +- void *ptr, size_t num_bytes); ++extern VCHIQ_STATUS_T vchiq_dump_phys_mem( VCHIQ_SERVICE_HANDLE_T service, void *ptr, size_t num_bytes ); + + #endif /* VCHIQ_IF_H */ +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_ioctl.h +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_ioctl.h 2013-07-26 19:36:51.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_ioctl.h 2013-07-26 19:37:11.000000000 +0000 +@@ -26,89 +26,80 @@ + #define VCHIQ_INVALID_HANDLE -1 + + typedef struct { +- VCHIQ_SERVICE_PARAMS_T params; +- int is_open; +- int is_vchi; +- int handle; /* OUT */ ++ VCHIQ_SERVICE_PARAMS_T params; ++ int is_open; ++ int is_vchi; ++ int handle; /* OUT */ + } VCHIQ_CREATE_SERVICE_T; + + typedef struct { +- int handle; +- int count; +- const VCHIQ_ELEMENT_T *elements; ++ int handle; ++ int count; ++ const VCHIQ_ELEMENT_T *elements; + } VCHIQ_QUEUE_MESSAGE_T; + + typedef struct { +- int handle; +- void *data; +- int size; +- void *userdata; +- VCHIQ_BULK_MODE_T mode; ++ int handle; ++ void *data; ++ int size; ++ void *userdata; ++ VCHIQ_BULK_MODE_T mode; + } VCHIQ_QUEUE_BULK_TRANSFER_T; + + typedef struct { +- VCHIQ_REASON_T reason; +- VCHIQ_HEADER_T *header; +- void *service_userdata; +- void *bulk_userdata; ++ VCHIQ_REASON_T reason; ++ VCHIQ_HEADER_T *header; ++ void *service_userdata; ++ void *bulk_userdata; + } VCHIQ_COMPLETION_DATA_T; + + typedef struct { +- int count; +- VCHIQ_COMPLETION_DATA_T *buf; +- int msgbufsize; +- int msgbufcount; /* IN/OUT */ +- void **msgbufs; ++ int count; ++ VCHIQ_COMPLETION_DATA_T *buf; ++ int msgbufsize; ++ int msgbufcount; /* IN/OUT */ ++ void **msgbufs; + } VCHIQ_AWAIT_COMPLETION_T; + + typedef struct { +- int handle; +- int blocking; +- int bufsize; +- void *buf; ++ int handle; ++ int blocking; ++ int bufsize; ++ void *buf; + } VCHIQ_DEQUEUE_MESSAGE_T; + + typedef struct { +- int config_size; +- VCHIQ_CONFIG_T *pconfig; ++ int config_size; ++ VCHIQ_CONFIG_T *pconfig; + } VCHIQ_GET_CONFIG_T; + + typedef struct { +- int handle; +- VCHIQ_SERVICE_OPTION_T option; +- int value; ++ int handle; ++ VCHIQ_SERVICE_OPTION_T option; ++ int value; + } VCHIQ_SET_SERVICE_OPTION_T; + + typedef struct { +- void *virt_addr; +- size_t num_bytes; ++ void *virt_addr; ++ size_t num_bytes; + } VCHIQ_DUMP_MEM_T; + + #define VCHIQ_IOC_CONNECT _IO(VCHIQ_IOC_MAGIC, 0) + #define VCHIQ_IOC_SHUTDOWN _IO(VCHIQ_IOC_MAGIC, 1) +-#define VCHIQ_IOC_CREATE_SERVICE \ +- _IOWR(VCHIQ_IOC_MAGIC, 2, VCHIQ_CREATE_SERVICE_T) ++#define VCHIQ_IOC_CREATE_SERVICE _IOWR(VCHIQ_IOC_MAGIC, 2, VCHIQ_CREATE_SERVICE_T) + #define VCHIQ_IOC_REMOVE_SERVICE _IO(VCHIQ_IOC_MAGIC, 3) +-#define VCHIQ_IOC_QUEUE_MESSAGE \ +- _IOW(VCHIQ_IOC_MAGIC, 4, VCHIQ_QUEUE_MESSAGE_T) +-#define VCHIQ_IOC_QUEUE_BULK_TRANSMIT \ +- _IOWR(VCHIQ_IOC_MAGIC, 5, VCHIQ_QUEUE_BULK_TRANSFER_T) +-#define VCHIQ_IOC_QUEUE_BULK_RECEIVE \ +- _IOWR(VCHIQ_IOC_MAGIC, 6, VCHIQ_QUEUE_BULK_TRANSFER_T) +-#define VCHIQ_IOC_AWAIT_COMPLETION \ +- _IOWR(VCHIQ_IOC_MAGIC, 7, VCHIQ_AWAIT_COMPLETION_T) +-#define VCHIQ_IOC_DEQUEUE_MESSAGE \ +- _IOWR(VCHIQ_IOC_MAGIC, 8, VCHIQ_DEQUEUE_MESSAGE_T) ++#define VCHIQ_IOC_QUEUE_MESSAGE _IOW(VCHIQ_IOC_MAGIC, 4, VCHIQ_QUEUE_MESSAGE_T) ++#define VCHIQ_IOC_QUEUE_BULK_TRANSMIT _IOW(VCHIQ_IOC_MAGIC, 5, VCHIQ_QUEUE_BULK_TRANSFER_T) ++#define VCHIQ_IOC_QUEUE_BULK_RECEIVE _IOW(VCHIQ_IOC_MAGIC, 6, VCHIQ_QUEUE_BULK_TRANSFER_T) ++#define VCHIQ_IOC_AWAIT_COMPLETION _IOWR(VCHIQ_IOC_MAGIC, 7, VCHIQ_AWAIT_COMPLETION_T) ++#define VCHIQ_IOC_DEQUEUE_MESSAGE _IOWR(VCHIQ_IOC_MAGIC, 8, VCHIQ_DEQUEUE_MESSAGE_T) + #define VCHIQ_IOC_GET_CLIENT_ID _IO(VCHIQ_IOC_MAGIC, 9) +-#define VCHIQ_IOC_GET_CONFIG \ +- _IOWR(VCHIQ_IOC_MAGIC, 10, VCHIQ_GET_CONFIG_T) ++#define VCHIQ_IOC_GET_CONFIG _IOWR(VCHIQ_IOC_MAGIC, 10, VCHIQ_GET_CONFIG_T) + #define VCHIQ_IOC_CLOSE_SERVICE _IO(VCHIQ_IOC_MAGIC, 11) + #define VCHIQ_IOC_USE_SERVICE _IO(VCHIQ_IOC_MAGIC, 12) + #define VCHIQ_IOC_RELEASE_SERVICE _IO(VCHIQ_IOC_MAGIC, 13) +-#define VCHIQ_IOC_SET_SERVICE_OPTION \ +- _IOW(VCHIQ_IOC_MAGIC, 14, VCHIQ_SET_SERVICE_OPTION_T) +-#define VCHIQ_IOC_DUMP_PHYS_MEM \ +- _IOW(VCHIQ_IOC_MAGIC, 15, VCHIQ_DUMP_MEM_T) ++#define VCHIQ_IOC_SET_SERVICE_OPTION _IOW(VCHIQ_IOC_MAGIC, 14, VCHIQ_SET_SERVICE_OPTION_T) ++#define VCHIQ_IOC_DUMP_PHYS_MEM _IOW(VCHIQ_IOC_MAGIC, 15, VCHIQ_DUMP_MEM_T) + #define VCHIQ_IOC_MAX 15 + + #endif +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_kern_lib.c +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_kern_lib.c 2013-07-26 19:36:51.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_kern_lib.c 2013-07-26 19:37:11.000000000 +0000 +@@ -16,19 +16,22 @@ + + #include + #include +-#include + + #include "vchiq_core.h" + #include "vchiq_arm.h" ++#include "interface/vcos/vcos_logging.h" + + /* ---- Public Variables ------------------------------------------------- */ + ++extern VCOS_LOG_CAT_T vchiq_core_log_category; ++#define VCOS_LOG_CATEGORY (&vchiq_core_log_category) ++ + /* ---- Private Constants and Types -------------------------------------- */ + + struct vchiq_instance_struct { +- VCHIQ_STATE_T *state; ++ VCHIQ_STATE_T *state; + +- int connected; ++ int connected; + }; + + /**************************************************************************** +@@ -37,42 +40,40 @@ + * + ***************************************************************************/ + +-VCHIQ_STATUS_T vchiq_initialise(VCHIQ_INSTANCE_T *instanceOut) ++VCHIQ_STATUS_T vchiq_initialise( VCHIQ_INSTANCE_T *instanceOut ) + { +- VCHIQ_STATUS_T status = VCHIQ_ERROR; +- VCHIQ_STATE_T *state; +- VCHIQ_INSTANCE_T instance = NULL; +- +- vchiq_log_trace(vchiq_core_log_level, "%s called", __func__); +- +- state = vchiq_get_state(); +- if (!state) { +- vchiq_log_error(vchiq_core_log_level, +- "%s: videocore not initialized\n", __func__); +- goto failed; +- } +- +- instance = kzalloc(sizeof(*instance), GFP_KERNEL); +- if (!instance) { +- vchiq_log_error(vchiq_core_log_level, +- "%s: error allocating vchiq instance\n", __func__); +- goto failed; +- } +- +- instance->connected = 0; +- instance->state = state; +- +- *instanceOut = instance; +- +- status = VCHIQ_SUCCESS; ++ VCHIQ_STATUS_T status = VCHIQ_ERROR; ++ VCHIQ_STATE_T *state; ++ VCHIQ_INSTANCE_T instance = NULL; ++ ++ vcos_log_trace( "%s called", __func__ ); ++ ++ state = vchiq_get_state(); ++ if (!state) ++ { ++ printk( KERN_ERR "%s: videocore not initialized\n", __func__ ); ++ goto failed; ++ } ++ ++ instance = kzalloc( sizeof(*instance), GFP_KERNEL ); ++ if( !instance ) ++ { ++ printk( KERN_ERR "%s: error allocating vchiq instance\n", __func__ ); ++ goto failed; ++ } ++ ++ instance->connected = 0; ++ instance->state = state; ++ ++ *instanceOut = instance; ++ ++ status = VCHIQ_SUCCESS; + + failed: +- vchiq_log_trace(vchiq_core_log_level, +- "%s(%p): returning %d", __func__, instance, status); ++ vcos_log_trace( "%s(%p): returning %d", __func__, instance, status ); + +- return status; ++ return status; + } +-EXPORT_SYMBOL(vchiq_initialise); + + /**************************************************************************** + * +@@ -80,31 +81,27 @@ + * + ***************************************************************************/ + +-VCHIQ_STATUS_T vchiq_shutdown(VCHIQ_INSTANCE_T instance) ++VCHIQ_STATUS_T vchiq_shutdown( VCHIQ_INSTANCE_T instance ) + { +- VCHIQ_STATUS_T status; +- VCHIQ_STATE_T *state = instance->state; ++ VCHIQ_STATUS_T status; ++ VCHIQ_STATE_T *state = instance->state; + +- vchiq_log_trace(vchiq_core_log_level, +- "%s(%p) called", __func__, instance); ++ vcos_log_trace( "%s(%p) called", __func__, instance ); + +- if (mutex_lock_interruptible(&state->mutex) != 0) +- return VCHIQ_RETRY; ++ vcos_mutex_lock(&state->mutex); + +- /* Remove all services */ +- status = vchiq_shutdown_internal(state, instance); ++ /* Remove all services */ ++ status = vchiq_shutdown_internal(state, instance); + +- mutex_unlock(&state->mutex); ++ vcos_mutex_unlock(&state->mutex); + +- if (status == VCHIQ_SUCCESS) +- kfree(instance); ++ if (status == VCHIQ_SUCCESS) ++ kfree(instance); + +- vchiq_log_trace(vchiq_core_log_level, +- "%s(%p): returning %d", __func__, instance, status); ++ vcos_log_trace( "%s(%p): returning %d", __func__, instance, status ); + +- return status; ++ return status; + } +-EXPORT_SYMBOL(vchiq_shutdown); + + /**************************************************************************** + * +@@ -114,7 +111,7 @@ + + int vchiq_is_connected(VCHIQ_INSTANCE_T instance) + { +- return instance->connected; ++ return instance->connected; + } + + /**************************************************************************** +@@ -125,32 +122,28 @@ + + VCHIQ_STATUS_T vchiq_connect(VCHIQ_INSTANCE_T instance) + { +- VCHIQ_STATUS_T status; +- VCHIQ_STATE_T *state = instance->state; ++ VCHIQ_STATUS_T status; ++ VCHIQ_STATE_T *state = instance->state; + +- vchiq_log_trace(vchiq_core_log_level, +- "%s(%p) called", __func__, instance); ++ vcos_log_trace( "%s(%p) called", __func__, instance ); + +- if (mutex_lock_interruptible(&state->mutex) != 0) { +- vchiq_log_trace(vchiq_core_log_level, +- "%s: call to mutex_lock failed", __func__); +- status = VCHIQ_RETRY; +- goto failed; +- } +- status = vchiq_connect_internal(state, instance); ++ if (vcos_mutex_lock(&state->mutex) != VCOS_SUCCESS) { ++ vcos_log_trace( "%s: call to vcos_mutex_lock failed", __func__ ); ++ status = VCHIQ_RETRY; ++ goto failed; ++ } ++ status = vchiq_connect_internal(state, instance); + +- if (status == VCHIQ_SUCCESS) +- instance->connected = 1; ++ if (status == VCHIQ_SUCCESS) ++ instance->connected = 1; + +- mutex_unlock(&state->mutex); ++ vcos_mutex_unlock(&state->mutex); + + failed: +- vchiq_log_trace(vchiq_core_log_level, +- "%s(%p): returning %d", __func__, instance, status); ++ vcos_log_trace( "%s(%p): returning %d", __func__, instance, status ); + +- return status; ++ return status; + } +-EXPORT_SYMBOL(vchiq_connect); + + /**************************************************************************** + * +@@ -159,42 +152,22 @@ + ***************************************************************************/ + + VCHIQ_STATUS_T vchiq_add_service( +- VCHIQ_INSTANCE_T instance, +- const VCHIQ_SERVICE_PARAMS_T *params, +- VCHIQ_SERVICE_HANDLE_T *phandle) +-{ +- VCHIQ_STATUS_T status; +- VCHIQ_STATE_T *state = instance->state; +- VCHIQ_SERVICE_T *service = NULL; +- int srvstate; +- +- vchiq_log_trace(vchiq_core_log_level, +- "%s(%p) called", __func__, instance); +- +- *phandle = VCHIQ_SERVICE_HANDLE_INVALID; +- +- srvstate = vchiq_is_connected(instance) +- ? VCHIQ_SRVSTATE_LISTENING +- : VCHIQ_SRVSTATE_HIDDEN; +- +- service = vchiq_add_service_internal( +- state, +- params, +- srvstate, +- instance); +- +- if (service) { +- *phandle = service->handle; +- status = VCHIQ_SUCCESS; +- } else +- status = VCHIQ_ERROR; ++ VCHIQ_INSTANCE_T instance, ++ int fourcc, ++ VCHIQ_CALLBACK_T callback, ++ void *userdata, ++ VCHIQ_SERVICE_HANDLE_T *pservice) ++{ ++ VCHIQ_SERVICE_PARAMS_T params; + +- vchiq_log_trace(vchiq_core_log_level, +- "%s(%p): returning %d", __func__, instance, status); ++ params.fourcc = fourcc; ++ params.callback = callback; ++ params.userdata = userdata; ++ params.version = 0; ++ params.version_min = 0; + +- return status; ++ return vchiq_add_service_params(instance, ¶ms, pservice); + } +-EXPORT_SYMBOL(vchiq_add_service); + + /**************************************************************************** + * +@@ -203,39 +176,122 @@ + ***************************************************************************/ + + VCHIQ_STATUS_T vchiq_open_service( +- VCHIQ_INSTANCE_T instance, +- const VCHIQ_SERVICE_PARAMS_T *params, +- VCHIQ_SERVICE_HANDLE_T *phandle) +-{ +- VCHIQ_STATUS_T status = VCHIQ_ERROR; +- VCHIQ_STATE_T *state = instance->state; +- VCHIQ_SERVICE_T *service = NULL; +- +- vchiq_log_trace(vchiq_core_log_level, +- "%s(%p) called", __func__, instance); +- +- *phandle = VCHIQ_SERVICE_HANDLE_INVALID; +- +- if (!vchiq_is_connected(instance)) +- goto failed; +- +- service = vchiq_add_service_internal(state, +- params, +- VCHIQ_SRVSTATE_OPENING, +- instance); +- +- if (service) { +- status = vchiq_open_service_internal(service, current->pid); +- if (status == VCHIQ_SUCCESS) +- *phandle = service->handle; +- else +- vchiq_remove_service(service->handle); +- } ++ VCHIQ_INSTANCE_T instance, ++ int fourcc, ++ VCHIQ_CALLBACK_T callback, ++ void *userdata, ++ VCHIQ_SERVICE_HANDLE_T *pservice) ++{ ++ VCHIQ_SERVICE_PARAMS_T params; ++ ++ params.fourcc = fourcc; ++ params.callback = callback; ++ params.userdata = userdata; ++ params.version = 0; ++ params.version_min = 0; ++ ++ return vchiq_open_service_params(instance, ¶ms, pservice); ++} ++ ++/**************************************************************************** ++* ++* vchiq_add_service_params ++* ++***************************************************************************/ ++ ++VCHIQ_STATUS_T vchiq_add_service_params( ++ VCHIQ_INSTANCE_T instance, ++ const VCHIQ_SERVICE_PARAMS_T *params, ++ VCHIQ_SERVICE_HANDLE_T *pservice) ++{ ++ VCHIQ_STATUS_T status; ++ VCHIQ_STATE_T *state = instance->state; ++ VCHIQ_SERVICE_T *service; ++ int srvstate; ++ ++ vcos_log_trace( "%s(%p) called", __func__, instance ); ++ ++ *pservice = NULL; ++ ++ srvstate = vchiq_is_connected( instance ) ++ ? VCHIQ_SRVSTATE_LISTENING ++ : VCHIQ_SRVSTATE_HIDDEN; ++ ++ vcos_mutex_lock(&state->mutex); ++ ++ service = vchiq_add_service_internal( ++ state, ++ params, ++ srvstate, ++ instance); ++ ++ vcos_mutex_unlock(&state->mutex); ++ ++ if ( service ) ++ { ++ *pservice = &service->base; ++ status = VCHIQ_SUCCESS; ++ } ++ else ++ { ++ status = VCHIQ_ERROR; ++ } ++ ++ vcos_log_trace( "%s(%p): returning %d", __func__, instance, status ); ++ ++ return status; ++} ++ ++/**************************************************************************** ++* ++* vchiq_open_service_params ++* ++***************************************************************************/ ++ ++VCHIQ_STATUS_T vchiq_open_service_params( ++ VCHIQ_INSTANCE_T instance, ++ const VCHIQ_SERVICE_PARAMS_T *params, ++ VCHIQ_SERVICE_HANDLE_T *pservice) ++{ ++ VCHIQ_STATUS_T status = VCHIQ_ERROR; ++ VCHIQ_STATE_T *state = instance->state; ++ VCHIQ_SERVICE_T *service; ++ ++ vcos_log_trace( "%s(%p) called", __func__, instance ); ++ ++ *pservice = NULL; ++ ++ if (!vchiq_is_connected(instance)) ++ goto failed; ++ ++ vcos_mutex_lock(&state->mutex); ++ ++ service = vchiq_add_service_internal(state, ++ params, ++ VCHIQ_SRVSTATE_OPENING, ++ instance); ++ ++ vcos_mutex_unlock(&state->mutex); ++ ++ if ( service ) ++ { ++ status = vchiq_open_service_internal(service, current->pid); ++ if ( status == VCHIQ_SUCCESS ) ++ *pservice = &service->base; ++ else ++ vchiq_remove_service(&service->base); ++ } + + failed: +- vchiq_log_trace(vchiq_core_log_level, +- "%s(%p): returning %d", __func__, instance, status); ++ vcos_log_trace( "%s(%p): returning %d", __func__, instance, status ); + +- return status; ++ return status; + } ++ ++EXPORT_SYMBOL(vchiq_initialise); ++EXPORT_SYMBOL(vchiq_shutdown); ++EXPORT_SYMBOL(vchiq_connect); ++EXPORT_SYMBOL(vchiq_add_service); + EXPORT_SYMBOL(vchiq_open_service); ++EXPORT_SYMBOL(vchiq_add_service_params); ++EXPORT_SYMBOL(vchiq_open_service_params); +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_lib.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_lib.c 2013-07-26 19:37:11.000000000 +0000 +@@ -0,0 +1,1628 @@ ++/* ++ * Copyright (c) 2010-2011 Broadcom Corporation. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++#include ++#include ++#include ++#include ++ ++#include "vchiq.h" ++#include "vchiq_cfg.h" ++#include "vchiq_ioctl.h" ++#include "interface/vchi/vchi.h" ++#include "interface/vchi/common/endian.h" ++#include "interface/vcos/vcos.h" ++ ++#define VCHIQ_MAX_INSTANCE_SERVICES 32 ++#define MSGBUF_SIZE (VCHIQ_MAX_MSG_SIZE + sizeof(VCHIQ_HEADER_T)) ++ ++#define RETRY(r,x) do { r = x; } while ((r == -1) && (errno == EINTR)) ++ ++#define VCOS_LOG_CATEGORY (&vchiq_lib_log_category) ++ ++typedef struct vchiq_service_struct ++{ ++ VCHIQ_SERVICE_BASE_T base; ++ int handle; ++ int fd; ++ VCHI_CALLBACK_T vchi_callback; ++ void *peek_buf; ++ int peek_size; ++ int client_id; ++} VCHIQ_SERVICE_T; ++ ++typedef struct vchiq_service_struct VCHI_SERVICE_T; ++ ++struct vchiq_instance_struct ++{ ++ int fd; ++ int initialised; ++ int connected; ++ VCOS_THREAD_T completion_thread; ++ VCOS_MUTEX_T mutex; ++ int used_services; ++ VCHIQ_SERVICE_T services[VCHIQ_MAX_INSTANCE_SERVICES]; ++} vchiq_instance; ++ ++typedef struct vchiq_instance_struct VCHI_STATE_T; ++ ++/* Local data */ ++static VCOS_LOG_LEVEL_T vchiq_default_lib_log_level = VCOS_LOG_WARN; ++static VCOS_LOG_CAT_T vchiq_lib_log_category; ++static VCOS_MUTEX_T vchiq_lib_mutex; ++static void *free_msgbufs; ++ ++ ++/* Local utility functions */ ++static VCHIQ_INSTANCE_T ++vchiq_lib_init(void); ++ ++static void *completion_thread(void *); ++ ++static VCHIQ_STATUS_T ++create_service(VCHIQ_INSTANCE_T instance, ++ const VCHIQ_SERVICE_PARAMS_T *params, ++ VCHI_CALLBACK_T vchi_callback, ++ int is_open, ++ VCHIQ_SERVICE_HANDLE_T *pservice); ++ ++static int ++fill_peek_buf(VCHI_SERVICE_T *service, ++ VCHI_FLAGS_T flags); ++ ++static void * ++alloc_msgbuf(void); ++ ++static void ++free_msgbuf(void *buf); ++ ++static __inline int ++is_valid_instance(VCHIQ_INSTANCE_T instance) ++{ ++ return (instance == &vchiq_instance) && (instance->initialised > 0); ++} ++ ++static __inline int ++is_valid_service(VCHIQ_SERVICE_T *service) ++{ ++ return ((service != NULL) && (service->fd != VCHIQ_INVALID_HANDLE)); ++} ++ ++/* ++ * VCHIQ API ++ */ ++ ++VCHIQ_STATUS_T ++vchiq_initialise(VCHIQ_INSTANCE_T *pinstance) ++{ ++ VCHIQ_INSTANCE_T instance; ++ ++ instance = vchiq_lib_init(); ++ ++ vcos_log_trace( "%s: returning instance handle %p", __func__, instance ); ++ ++ *pinstance = instance; ++ ++ return (instance != NULL) ? VCHIQ_SUCCESS : VCHIQ_ERROR; ++} ++ ++VCHIQ_STATUS_T ++vchiq_shutdown(VCHIQ_INSTANCE_T instance) ++{ ++ vcos_log_trace( "%s called", __func__ ); ++ ++ if (!is_valid_instance(instance)) ++ return VCHIQ_ERROR; ++ ++ vcos_mutex_lock(&instance->mutex); ++ ++ if (instance->initialised == 1) ++ { ++ int i; ++ ++ instance->initialised = -1; /* Enter limbo */ ++ ++ /* Remove all services */ ++ ++ for (i = 0; i < instance->used_services; i++) ++ { ++ if (instance->services[i].handle != VCHIQ_INVALID_HANDLE) ++ { ++ vchiq_remove_service(&instance->services[i].base); ++ instance->services[i].handle = VCHIQ_INVALID_HANDLE; ++ } ++ } ++ ++ if (instance->connected) ++ { ++ int ret; ++ RETRY(ret, ioctl(instance->fd, VCHIQ_IOC_SHUTDOWN, 0)); ++ vcos_assert(ret == 0); ++ vcos_thread_join(&instance->completion_thread, NULL); ++ instance->connected = 0; ++ } ++ ++ close(instance->fd); ++ instance->fd = -1; ++ } ++ else if (instance->initialised > 1) ++ { ++ instance->initialised--; ++ } ++ ++ vcos_mutex_unlock(&instance->mutex); ++ ++ vcos_global_lock(); ++ ++ if (instance->initialised == -1) ++ { ++ vcos_mutex_delete(&instance->mutex); ++ instance->initialised = 0; ++ } ++ ++ vcos_global_unlock(); ++ ++ vcos_log_trace( "%s returning", __func__ ); ++ ++ return VCHIQ_SUCCESS; ++} ++ ++VCHIQ_STATUS_T ++vchiq_connect(VCHIQ_INSTANCE_T instance) ++{ ++ VCHIQ_STATUS_T status = VCHIQ_SUCCESS; ++ ++ vcos_log_trace( "%s called", __func__ ); ++ ++ if (!is_valid_instance(instance)) ++ return VCHIQ_ERROR; ++ ++ vcos_mutex_lock(&instance->mutex); ++ ++ if (!instance->connected) ++ { ++ int ret = ioctl(instance->fd, VCHIQ_IOC_CONNECT, 0); ++ if (ret == 0) ++ { ++ VCOS_THREAD_ATTR_T attrs; ++ instance->connected = 1; ++ vcos_thread_attr_init(&attrs); ++ vcos_thread_create(&instance->completion_thread, "VCHIQ completion", ++ &attrs, completion_thread, instance); ++ } ++ else ++ { ++ status = VCHIQ_ERROR; ++ } ++ } ++ ++ vcos_mutex_unlock(&instance->mutex); ++ ++ return status; ++} ++ ++VCHIQ_STATUS_T ++vchiq_add_service(VCHIQ_INSTANCE_T instance, ++ int fourcc, ++ VCHIQ_CALLBACK_T callback, ++ void *userdata, ++ VCHIQ_SERVICE_HANDLE_T *pservice) ++{ ++ VCHIQ_SERVICE_PARAMS_T params; ++ ++ params.fourcc = fourcc; ++ params.callback = callback; ++ params.userdata = userdata; ++ params.version = 0; ++ params.version_min = 0; ++ ++ return vchiq_add_service_params(instance, ¶ms, pservice); ++} ++ ++VCHIQ_STATUS_T ++vchiq_open_service(VCHIQ_INSTANCE_T instance, ++ int fourcc, ++ VCHIQ_CALLBACK_T callback, ++ void *userdata, ++ VCHIQ_SERVICE_HANDLE_T *pservice) ++{ ++ VCHIQ_SERVICE_PARAMS_T params; ++ ++ params.fourcc = fourcc; ++ params.callback = callback; ++ params.userdata = userdata; ++ params.version = 0; ++ params.version_min = 0; ++ ++ return vchiq_open_service_params(instance, ¶ms, pservice); ++} ++ ++VCHIQ_STATUS_T ++vchiq_add_service_params(VCHIQ_INSTANCE_T instance, ++ const VCHIQ_SERVICE_PARAMS_T *params, ++ VCHIQ_SERVICE_HANDLE_T *pservice) ++{ ++ VCHIQ_STATUS_T status; ++ ++ vcos_log_trace( "%s called fourcc = 0x%08x (%c%c%c%c)", ++ __func__, ++ params->fourcc, ++ (params->fourcc >> 24) & 0xff, ++ (params->fourcc >> 16) & 0xff, ++ (params->fourcc >> 8) & 0xff, ++ (params->fourcc ) & 0xff ); ++ ++ if (!params->callback) ++ return VCHIQ_ERROR; ++ ++ if (!is_valid_instance(instance)) ++ return VCHIQ_ERROR; ++ ++ status = create_service(instance, ++ params, ++ NULL/*vchi_callback*/, ++ 0/*!open*/, ++ pservice); ++ ++ vcos_log_trace( "%s returning service handle = 0x%08x", __func__, (uint32_t)*pservice ); ++ ++ return status; ++} ++ ++VCHIQ_STATUS_T ++vchiq_open_service_params(VCHIQ_INSTANCE_T instance, ++ const VCHIQ_SERVICE_PARAMS_T *params, ++ VCHIQ_SERVICE_HANDLE_T *pservice) ++{ ++ VCHIQ_STATUS_T status; ++ ++ vcos_log_trace( "%s called fourcc = 0x%08x (%c%c%c%c)", ++ __func__, ++ params->fourcc, ++ (params->fourcc >> 24) & 0xff, ++ (params->fourcc >> 16) & 0xff, ++ (params->fourcc >> 8) & 0xff, ++ (params->fourcc ) & 0xff ); ++ ++ if (!params->callback) ++ return VCHIQ_ERROR; ++ ++ if (!is_valid_instance(instance)) ++ return VCHIQ_ERROR; ++ ++ status = create_service(instance, ++ params, ++ NULL/*vchi_callback*/, ++ 1/*open*/, ++ pservice); ++ ++ vcos_log_trace( "%s returning service handle = 0x%08x", __func__, (uint32_t)*pservice ); ++ ++ return status; ++} ++ ++VCHIQ_STATUS_T ++vchiq_close_service(VCHIQ_SERVICE_HANDLE_T handle) ++{ ++ VCHIQ_SERVICE_T *service = (VCHIQ_SERVICE_T *)handle; ++ int ret; ++ ++ vcos_log_trace( "%s called service handle = 0x%08x", __func__, (uint32_t)handle ); ++ ++ if (!is_valid_service(service)) ++ return VCHIQ_ERROR; ++ ++ RETRY(ret,ioctl(service->fd, VCHIQ_IOC_CLOSE_SERVICE, service->handle)); ++ ++ if (ret != 0) ++ return VCHIQ_ERROR; ++ ++ service->handle = VCHIQ_INVALID_HANDLE; ++ return VCHIQ_SUCCESS; ++} ++ ++VCHIQ_STATUS_T ++vchiq_remove_service(VCHIQ_SERVICE_HANDLE_T handle) ++{ ++ VCHIQ_SERVICE_T *service = (VCHIQ_SERVICE_T *)handle; ++ int ret; ++ ++ vcos_log_trace( "%s called service handle = 0x%08x", __func__, (uint32_t)handle ); ++ ++ if (!is_valid_service(service)) ++ return VCHIQ_ERROR; ++ ++ RETRY(ret,ioctl(service->fd, VCHIQ_IOC_REMOVE_SERVICE, service->handle)); ++ ++ if (ret != 0) ++ return VCHIQ_ERROR; ++ ++ service->handle = VCHIQ_INVALID_HANDLE; ++ return VCHIQ_SUCCESS; ++} ++ ++VCHIQ_STATUS_T ++vchiq_queue_message(VCHIQ_SERVICE_HANDLE_T handle, ++ const VCHIQ_ELEMENT_T *elements, ++ int count) ++{ ++ VCHIQ_SERVICE_T *service = (VCHIQ_SERVICE_T *)handle; ++ VCHIQ_QUEUE_MESSAGE_T args; ++ int ret; ++ ++ vcos_log_trace( "%s called service handle = 0x%08x", __func__, (uint32_t)handle ); ++ ++ if (!is_valid_service(service)) ++ return VCHIQ_ERROR; ++ ++ args.handle = service->handle; ++ args.elements = elements; ++ args.count = count; ++ RETRY(ret, ioctl(service->fd, VCHIQ_IOC_QUEUE_MESSAGE, &args)); ++ ++ return (ret >= 0) ? VCHIQ_SUCCESS : VCHIQ_ERROR; ++} ++ ++void ++vchiq_release_message(VCHIQ_SERVICE_HANDLE_T handle, ++ VCHIQ_HEADER_T *header) ++{ ++ vcos_log_trace( "%s handle=%08x, header=%x", __func__, (uint32_t)handle, (uint32_t)header ); ++ ++ free_msgbuf(header); ++} ++ ++VCHIQ_STATUS_T ++vchiq_queue_bulk_transmit(VCHIQ_SERVICE_HANDLE_T handle, ++ const void *data, ++ int size, ++ void *userdata) ++{ ++ VCHIQ_SERVICE_T *service = (VCHIQ_SERVICE_T *)handle; ++ VCHIQ_QUEUE_BULK_TRANSFER_T args; ++ int ret; ++ ++ vcos_log_trace( "%s called service handle = 0x%08x", __func__, (uint32_t)handle ); ++ ++ if (!is_valid_service(service)) ++ return VCHIQ_ERROR; ++ ++ args.handle = service->handle; ++ args.data = (void *)data; ++ args.size = size; ++ args.userdata = userdata; ++ args.mode = VCHIQ_BULK_MODE_CALLBACK; ++ RETRY(ret, ioctl(service->fd, VCHIQ_IOC_QUEUE_BULK_TRANSMIT, &args)); ++ ++ return (ret >= 0) ? VCHIQ_SUCCESS : VCHIQ_ERROR; ++} ++ ++VCHIQ_STATUS_T ++vchiq_queue_bulk_receive(VCHIQ_SERVICE_HANDLE_T handle, ++ void *data, ++ int size, ++ void *userdata) ++{ ++ VCHIQ_SERVICE_T *service = (VCHIQ_SERVICE_T *)handle; ++ VCHIQ_QUEUE_BULK_TRANSFER_T args; ++ int ret; ++ ++ vcos_log_trace( "%s called service handle = 0x%08x", __func__, (uint32_t)handle ); ++ ++ if (!is_valid_service(service)) ++ return VCHIQ_ERROR; ++ ++ args.handle = service->handle; ++ args.data = data; ++ args.size = size; ++ args.userdata = userdata; ++ args.mode = VCHIQ_BULK_MODE_CALLBACK; ++ RETRY(ret, ioctl(service->fd, VCHIQ_IOC_QUEUE_BULK_RECEIVE, &args)); ++ ++ return (ret >= 0) ? VCHIQ_SUCCESS : VCHIQ_ERROR; ++} ++ ++VCHIQ_STATUS_T ++vchiq_queue_bulk_transmit_handle(VCHIQ_SERVICE_HANDLE_T handle, ++ VCHI_MEM_HANDLE_T memhandle, ++ const void *offset, ++ int size, ++ void *userdata) ++{ ++ vcos_assert(memhandle == VCHI_MEM_HANDLE_INVALID); ++ ++ vcos_log_trace( "%s called service handle = 0x%08x", __func__, (uint32_t)handle ); ++ ++ return vchiq_queue_bulk_transmit(handle, offset, size, userdata); ++} ++ ++VCHIQ_STATUS_T ++vchiq_queue_bulk_receive_handle(VCHIQ_SERVICE_HANDLE_T handle, ++ VCHI_MEM_HANDLE_T memhandle, ++ void *offset, ++ int size, ++ void *userdata) ++{ ++ vcos_assert(memhandle == VCHI_MEM_HANDLE_INVALID); ++ ++ vcos_log_trace( "%s called service handle = 0x%08x", __func__, (uint32_t)handle ); ++ ++ return vchiq_queue_bulk_receive(handle, offset, size, userdata); ++} ++ ++VCHIQ_STATUS_T ++vchiq_bulk_transmit(VCHIQ_SERVICE_HANDLE_T handle, ++ const void *data, ++ int size, ++ void *userdata, ++ VCHIQ_BULK_MODE_T mode) ++{ ++ VCHIQ_SERVICE_T *service = (VCHIQ_SERVICE_T *)handle; ++ VCHIQ_QUEUE_BULK_TRANSFER_T args; ++ int ret; ++ ++ vcos_log_trace( "%s called service handle = 0x%08x", __func__, (uint32_t)handle ); ++ ++ if (!is_valid_service(service)) ++ return VCHIQ_ERROR; ++ ++ args.handle = service->handle; ++ args.data = (void *)data; ++ args.size = size; ++ args.userdata = userdata; ++ args.mode = mode; ++ RETRY(ret, ioctl(service->fd, VCHIQ_IOC_QUEUE_BULK_TRANSMIT, &args)); ++ ++ return (ret >= 0) ? VCHIQ_SUCCESS : VCHIQ_ERROR; ++} ++ ++VCHIQ_STATUS_T ++vchiq_bulk_receive(VCHIQ_SERVICE_HANDLE_T handle, ++ void *data, ++ int size, ++ void *userdata, ++ VCHIQ_BULK_MODE_T mode) ++{ ++ VCHIQ_SERVICE_T *service = (VCHIQ_SERVICE_T *)handle; ++ VCHIQ_QUEUE_BULK_TRANSFER_T args; ++ int ret; ++ ++ vcos_log_trace( "%s called service handle = 0x%08x", __func__, (uint32_t)handle ); ++ ++ if (!is_valid_service(service)) ++ return VCHIQ_ERROR; ++ ++ args.handle = service->handle; ++ args.data = data; ++ args.size = size; ++ args.userdata = userdata; ++ args.mode = mode; ++ RETRY(ret, ioctl(service->fd, VCHIQ_IOC_QUEUE_BULK_RECEIVE, &args)); ++ ++ return (ret >= 0) ? VCHIQ_SUCCESS : VCHIQ_ERROR; ++} ++ ++VCHIQ_STATUS_T ++vchiq_bulk_transmit_handle(VCHIQ_SERVICE_HANDLE_T handle, ++ VCHI_MEM_HANDLE_T memhandle, ++ const void *offset, ++ int size, ++ void *userdata, ++ VCHIQ_BULK_MODE_T mode) ++{ ++ vcos_assert(memhandle == VCHI_MEM_HANDLE_INVALID); ++ ++ return vchiq_bulk_transmit(handle, offset, size, userdata, mode); ++} ++ ++VCHIQ_STATUS_T ++vchiq_bulk_receive_handle(VCHIQ_SERVICE_HANDLE_T handle, ++ VCHI_MEM_HANDLE_T memhandle, ++ void *offset, ++ int size, ++ void *userdata, ++ VCHIQ_BULK_MODE_T mode) ++{ ++ vcos_assert(memhandle == VCHI_MEM_HANDLE_INVALID); ++ ++ return vchiq_bulk_receive(handle, offset, size, userdata, mode); ++} ++ ++int ++vchiq_get_client_id(VCHIQ_SERVICE_HANDLE_T handle) ++{ ++ VCHIQ_SERVICE_T *service = (VCHIQ_SERVICE_T *)handle; ++ ++ if (!is_valid_service(service)) ++ return VCHIQ_ERROR; ++ ++ return ioctl(service->fd, VCHIQ_IOC_GET_CLIENT_ID, service->handle); ++} ++ ++VCHIQ_STATUS_T ++vchiq_get_config(VCHIQ_INSTANCE_T instance, ++ int config_size, ++ VCHIQ_CONFIG_T *pconfig) ++{ ++ VCHIQ_GET_CONFIG_T args; ++ int ret; ++ ++ if (!is_valid_instance(instance)) ++ return VCHIQ_ERROR; ++ ++ args.config_size = config_size; ++ args.pconfig = pconfig; ++ ++ RETRY(ret, ioctl(instance->fd, VCHIQ_IOC_GET_CONFIG, &args)); ++ ++ return (ret >= 0) ? VCHIQ_SUCCESS : VCHIQ_ERROR; ++} ++ ++int32_t ++vchiq_use_service( const VCHIQ_SERVICE_HANDLE_T handle ) ++{ ++ VCHIQ_SERVICE_T *service = (VCHIQ_SERVICE_T *)handle; ++ int ret; ++ ++ if (!is_valid_service(service)) ++ return VCHIQ_ERROR; ++ ++ RETRY(ret,ioctl(service->fd, VCHIQ_IOC_USE_SERVICE, service->handle)); ++ return ret; ++} ++ ++int32_t ++vchiq_release_service( const VCHIQ_SERVICE_HANDLE_T handle ) ++{ ++ VCHIQ_SERVICE_T *service = (VCHIQ_SERVICE_T *)handle; ++ int ret; ++ RETRY(ret,ioctl(service->fd, VCHIQ_IOC_RELEASE_SERVICE, service->handle)); ++ return ret; ++} ++ ++VCHIQ_STATUS_T ++vchiq_set_service_option(VCHIQ_SERVICE_HANDLE_T handle, ++ VCHIQ_SERVICE_OPTION_T option, int value) ++{ ++ VCHIQ_SET_SERVICE_OPTION_T args; ++ VCHIQ_SERVICE_T *service = (VCHIQ_SERVICE_T *)handle; ++ int ret; ++ ++ if (!is_valid_service(service)) ++ return VCHIQ_ERROR; ++ ++ args.handle = service->handle; ++ args.option = option; ++ args.value = value; ++ ++ RETRY(ret, ioctl(service->fd, VCHIQ_IOC_SET_SERVICE_OPTION, &args)); ++ ++ return (ret >= 0) ? VCHIQ_SUCCESS : VCHIQ_ERROR; ++} ++ ++/* ++ * VCHI API ++ */ ++ ++/* ---------------------------------------------------------------------- ++ * return pointer to the mphi message driver function table ++ * -------------------------------------------------------------------- */ ++const VCHI_MESSAGE_DRIVER_T * ++vchi_mphi_message_driver_func_table( void ) ++{ ++ return NULL; ++} ++ ++/* ---------------------------------------------------------------------- ++ * return a pointer to the 'single' connection driver fops ++ * -------------------------------------------------------------------- */ ++const VCHI_CONNECTION_API_T * ++single_get_func_table( void ) ++{ ++ return NULL; ++} ++ ++VCHI_CONNECTION_T * ++vchi_create_connection( const VCHI_CONNECTION_API_T * function_table, ++ const VCHI_MESSAGE_DRIVER_T * low_level ) ++{ ++ vcos_unused(function_table); ++ vcos_unused(low_level); ++ ++ return NULL; ++} ++ ++/*********************************************************** ++ * Name: vchi_msg_peek ++ * ++ * Arguments: const VCHI_SERVICE_HANDLE_T handle, ++ * void **data, ++ * uint32_t *msg_size, ++ * VCHI_FLAGS_T flags ++ * ++ * Description: Routine to return a pointer to the current message (to allow in place processing) ++ * The message can be removed using vchi_msg_remove when you're finished ++ * ++ * Returns: int32_t - success == 0 ++ * ++ ***********************************************************/ ++int32_t ++vchi_msg_peek( VCHI_SERVICE_HANDLE_T handle, ++ void **data, ++ uint32_t *msg_size, ++ VCHI_FLAGS_T flags ) ++{ ++ VCHI_SERVICE_T *service = (VCHI_SERVICE_T *)handle; ++ int ret; ++ ++ if (!is_valid_service(service)) ++ return VCHIQ_ERROR; ++ ++ ret = fill_peek_buf(service, flags); ++ ++ if (ret == 0) ++ { ++ *data = service->peek_buf; ++ *msg_size = service->peek_size; ++ } ++ ++ return ret; ++} ++ ++/*********************************************************** ++ * Name: vchi_msg_remove ++ * ++ * Arguments: const VCHI_SERVICE_HANDLE_T handle, ++ * ++ * Description: Routine to remove a message (after it has been read with vchi_msg_peek) ++ * ++ * Returns: int32_t - success == 0 ++ * ++ ***********************************************************/ ++int32_t ++vchi_msg_remove( VCHI_SERVICE_HANDLE_T handle ) ++{ ++ VCHI_SERVICE_T *service = (VCHI_SERVICE_T *)handle; ++ ++ if (!is_valid_service(service)) ++ return VCHIQ_ERROR; ++ ++ /* Why would you call vchi_msg_remove without calling vchi_msg_peek first? */ ++ vcos_assert(service->peek_size >= 0); ++ ++ /* Invalidate the content but reuse the buffer */ ++ service->peek_size = -1; ++ ++ return 0; ++} ++ ++/*********************************************************** ++ * Name: vchi_msg_queue ++ * ++ * Arguments: VCHI_SERVICE_HANDLE_T handle, ++ * const void *data, ++ * uint32_t data_size, ++ * VCHI_FLAGS_T flags, ++ * void *msg_handle, ++ * ++ * Description: Thin wrapper to queue a message onto a connection ++ * ++ * Returns: int32_t - success == 0 ++ * ++ ***********************************************************/ ++int32_t ++vchi_msg_queue( VCHI_SERVICE_HANDLE_T handle, ++ const void * data, ++ uint32_t data_size, ++ VCHI_FLAGS_T flags, ++ void * msg_handle ) ++{ ++ VCHI_SERVICE_T *service = (VCHI_SERVICE_T *)handle; ++ VCHIQ_QUEUE_MESSAGE_T args; ++ VCHIQ_ELEMENT_T element = {data, data_size}; ++ int ret; ++ ++ vcos_unused(msg_handle); ++ vcos_assert(flags == VCHI_FLAGS_BLOCK_UNTIL_QUEUED); ++ ++ if (!is_valid_service(service)) ++ return VCHIQ_ERROR; ++ ++ args.handle = service->handle; ++ args.elements = &element; ++ args.count = 1; ++ RETRY(ret, ioctl(service->fd, VCHIQ_IOC_QUEUE_MESSAGE, &args)); ++ ++ return ret; ++} ++ ++/*********************************************************** ++ * Name: vchi_bulk_queue_receive ++ * ++ * Arguments: VCHI_BULK_HANDLE_T handle, ++ * void *data_dst, ++ * const uint32_t data_size, ++ * VCHI_FLAGS_T flags ++ * void *bulk_handle ++ * ++ * Description: Routine to setup a rcv buffer ++ * ++ * Returns: int32_t - success == 0 ++ * ++ ***********************************************************/ ++int32_t ++vchi_bulk_queue_receive( VCHI_SERVICE_HANDLE_T handle, ++ void * data_dst, ++ uint32_t data_size, ++ VCHI_FLAGS_T flags, ++ void * bulk_handle ) ++{ ++ VCHI_SERVICE_T *service = (VCHI_SERVICE_T *)handle; ++ VCHIQ_QUEUE_BULK_TRANSFER_T args; ++ int ret; ++ ++ if (!is_valid_service(service)) ++ return VCHIQ_ERROR; ++ ++ switch ((int)flags) { ++ case VCHI_FLAGS_CALLBACK_WHEN_OP_COMPLETE | VCHI_FLAGS_BLOCK_UNTIL_QUEUED: ++ args.mode = VCHIQ_BULK_MODE_CALLBACK; ++ break; ++ case VCHI_FLAGS_BLOCK_UNTIL_OP_COMPLETE: ++ args.mode = VCHIQ_BULK_MODE_BLOCKING; ++ break; ++ case VCHI_FLAGS_BLOCK_UNTIL_QUEUED: ++ case VCHI_FLAGS_NONE: ++ args.mode = VCHIQ_BULK_MODE_NOCALLBACK; ++ break; ++ default: ++ vcos_assert(0); ++ break; ++ } ++ ++ args.handle = service->handle; ++ args.data = data_dst; ++ args.size = data_size; ++ args.userdata = bulk_handle; ++ RETRY(ret, ioctl(service->fd, VCHIQ_IOC_QUEUE_BULK_RECEIVE, &args)); ++ ++ return ret; ++} ++ ++/*********************************************************** ++ * Name: vchi_bulk_queue_transmit ++ * ++ * Arguments: VCHI_BULK_HANDLE_T handle, ++ * const void *data_src, ++ * uint32_t data_size, ++ * VCHI_FLAGS_T flags, ++ * void *bulk_handle ++ * ++ * Description: Routine to transmit some data ++ * ++ * Returns: int32_t - success == 0 ++ * ++ ***********************************************************/ ++int32_t ++vchi_bulk_queue_transmit( VCHI_SERVICE_HANDLE_T handle, ++ const void * data_src, ++ uint32_t data_size, ++ VCHI_FLAGS_T flags, ++ void * bulk_handle ) ++{ ++ VCHI_SERVICE_T *service = (VCHI_SERVICE_T *)handle; ++ VCHIQ_QUEUE_BULK_TRANSFER_T args; ++ int ret; ++ ++ if (!is_valid_service(service)) ++ return VCHIQ_ERROR; ++ ++ switch ((int)flags) { ++ case VCHI_FLAGS_CALLBACK_WHEN_OP_COMPLETE | VCHI_FLAGS_BLOCK_UNTIL_QUEUED: ++ args.mode = VCHIQ_BULK_MODE_CALLBACK; ++ break; ++ case VCHI_FLAGS_BLOCK_UNTIL_DATA_READ: ++ case VCHI_FLAGS_BLOCK_UNTIL_OP_COMPLETE: ++ args.mode = VCHIQ_BULK_MODE_BLOCKING; ++ break; ++ case VCHI_FLAGS_BLOCK_UNTIL_QUEUED: ++ case VCHI_FLAGS_NONE: ++ args.mode = VCHIQ_BULK_MODE_NOCALLBACK; ++ break; ++ default: ++ vcos_assert(0); ++ break; ++ } ++ ++ args.handle = service->handle; ++ args.data = (void *)data_src; ++ args.size = data_size; ++ args.userdata = bulk_handle; ++ RETRY(ret, ioctl(service->fd, VCHIQ_IOC_QUEUE_BULK_TRANSMIT, &args)); ++ ++ return ret; ++} ++ ++/*********************************************************** ++ * Name: vchi_msg_dequeue ++ * ++ * Arguments: VCHI_SERVICE_HANDLE_T handle, ++ * void *data, ++ * uint32_t max_data_size_to_read, ++ * uint32_t *actual_msg_size ++ * VCHI_FLAGS_T flags ++ * ++ * Description: Routine to dequeue a message into the supplied buffer ++ * ++ * Returns: int32_t - success == 0 ++ * ++ ***********************************************************/ ++int32_t ++vchi_msg_dequeue( VCHI_SERVICE_HANDLE_T handle, ++ void *data, ++ uint32_t max_data_size_to_read, ++ uint32_t *actual_msg_size, ++ VCHI_FLAGS_T flags ) ++{ ++ VCHI_SERVICE_T *service = (VCHI_SERVICE_T *)handle; ++ VCHIQ_DEQUEUE_MESSAGE_T args; ++ int ret; ++ ++ vcos_assert(flags == VCHI_FLAGS_NONE || flags == VCHI_FLAGS_BLOCK_UNTIL_OP_COMPLETE); ++ ++ if (!is_valid_service(service)) ++ return VCHIQ_ERROR; ++ ++ if (service->peek_size >= 0) ++ { ++ fprintf(stderr, "vchi_msg_dequeue -> using peek buffer\n"); ++ if ((uint32_t)service->peek_size <= max_data_size_to_read) ++ { ++ memcpy(data, service->peek_buf, service->peek_size); ++ *actual_msg_size = service->peek_size; ++ /* Invalidate the peek data, but retain the buffer */ ++ service->peek_size = -1; ++ ret = 0; ++ } ++ else ++ { ++ ret = -1; ++ } ++ } ++ else ++ { ++ args.handle = service->handle; ++ args.blocking = (flags == VCHI_FLAGS_BLOCK_UNTIL_OP_COMPLETE); ++ args.bufsize = max_data_size_to_read; ++ args.buf = data; ++ RETRY(ret, ioctl(service->fd, VCHIQ_IOC_DEQUEUE_MESSAGE, &args)); ++ if (ret >= 0) ++ { ++ *actual_msg_size = ret; ++ ret = 0; ++ } ++ } ++ ++ if ((ret < 0) && (errno != EWOULDBLOCK)) ++ fprintf(stderr, "vchi_msg_dequeue -> %d(%d)\n", ret, errno); ++ ++ return ret; ++} ++ ++/*********************************************************** ++ * Name: vchi_msg_queuev ++ * ++ * Arguments: VCHI_SERVICE_HANDLE_T handle, ++ * const void *data, ++ * uint32_t data_size, ++ * VCHI_FLAGS_T flags, ++ * void *msg_handle ++ * ++ * Description: Thin wrapper to queue a message onto a connection ++ * ++ * Returns: int32_t - success == 0 ++ * ++ ***********************************************************/ ++ ++vcos_static_assert(sizeof(VCHI_MSG_VECTOR_T) == sizeof(VCHIQ_ELEMENT_T)); ++vcos_static_assert(offsetof(VCHI_MSG_VECTOR_T, vec_base) == offsetof(VCHIQ_ELEMENT_T, data)); ++vcos_static_assert(offsetof(VCHI_MSG_VECTOR_T, vec_len) == offsetof(VCHIQ_ELEMENT_T, size)); ++ ++int32_t ++vchi_msg_queuev( VCHI_SERVICE_HANDLE_T handle, ++ VCHI_MSG_VECTOR_T * vector, ++ uint32_t count, ++ VCHI_FLAGS_T flags, ++ void *msg_handle ) ++{ ++ VCHI_SERVICE_T *service = (VCHI_SERVICE_T *)handle; ++ VCHIQ_QUEUE_MESSAGE_T args; ++ int ret; ++ ++ vcos_unused(msg_handle); ++ ++ vcos_assert(flags == VCHI_FLAGS_BLOCK_UNTIL_QUEUED); ++ ++ if (!is_valid_service(service)) ++ return VCHIQ_ERROR; ++ ++ args.handle = service->handle; ++ args.elements = (const VCHIQ_ELEMENT_T *)vector; ++ args.count = count; ++ RETRY(ret, ioctl(service->fd, VCHIQ_IOC_QUEUE_MESSAGE, &args)); ++ ++ return ret; ++} ++ ++/*********************************************************** ++ * Name: vchi_held_msg_release ++ * ++ * Arguments: VCHI_HELD_MSG_T *message ++ * ++ * Description: Routine to release a held message (after it has been read with vchi_msg_hold) ++ * ++ * Returns: int32_t - success == 0 ++ * ++ ***********************************************************/ ++int32_t ++vchi_held_msg_release( VCHI_HELD_MSG_T *message ) ++{ ++ int ret = -1; ++ ++ if (message && message->message && !message->service) ++ { ++ free_msgbuf(message->message); ++ ret = 0; ++ } ++ ++ return ret; ++} ++ ++/*********************************************************** ++ * Name: vchi_msg_hold ++ * ++ * Arguments: VCHI_SERVICE_HANDLE_T handle, ++ * void **data, ++ * uint32_t *msg_size, ++ * VCHI_FLAGS_T flags, ++ * VCHI_HELD_MSG_T *message_handle ++ * ++ * Description: Routine to return a pointer to the current message (to allow in place processing) ++ * The message is dequeued - don't forget to release the message using ++ * vchi_held_msg_release when you're finished ++ * ++ * Returns: int32_t - success == 0 ++ * ++ ***********************************************************/ ++int32_t ++vchi_msg_hold( VCHI_SERVICE_HANDLE_T handle, ++ void **data, ++ uint32_t *msg_size, ++ VCHI_FLAGS_T flags, ++ VCHI_HELD_MSG_T *message_handle ) ++{ ++ VCHI_SERVICE_T *service = (VCHI_SERVICE_T *)handle; ++ int ret; ++ ++ if (!is_valid_service(service)) ++ return VCHIQ_ERROR; ++ ++ ret = fill_peek_buf(service, flags); ++ ++ if (ret == 0) ++ { ++ *data = service->peek_buf; ++ *msg_size = service->peek_size; ++ ++ message_handle->message = service->peek_buf; ++ message_handle->service = NULL; ++ ++ service->peek_size = -1; ++ service->peek_buf = NULL; ++ } ++ ++ return 0; ++} ++ ++/*********************************************************** ++ * Name: vchi_initialise ++ * ++ * Arguments: VCHI_INSTANCE_T *instance_handle ++ * VCHI_CONNECTION_T **connections ++ * const uint32_t num_connections ++ * ++ * Description: Initialises the hardware but does not transmit anything ++ * When run as a Host App this will be called twice hence the need ++ * to malloc the state information ++ * ++ * Returns: 0 if successful, failure otherwise ++ * ++ ***********************************************************/ ++int32_t ++vchi_initialise( VCHI_INSTANCE_T *instance_handle ) ++{ ++ VCHIQ_INSTANCE_T instance; ++ ++ instance = vchiq_lib_init(); ++ ++ vcos_log_trace( "%s: returning instance handle %p", __func__, instance ); ++ ++ *instance_handle = (VCHI_INSTANCE_T)instance; ++ ++ return (instance != NULL) ? 0 : -1; ++} ++ ++/*********************************************************** ++ * Name: vchi_connect ++ * ++ * Arguments: VCHI_CONNECTION_T **connections ++ * const uint32_t num_connections ++ * VCHI_INSTANCE_T instance_handle ) ++ * ++ * Description: Starts the command service on each connection, ++ * causing INIT messages to be pinged back and forth ++ * ++ * Returns: 0 if successful, failure otherwise ++ * ++ ***********************************************************/ ++int32_t ++vchi_connect( VCHI_CONNECTION_T **connections, ++ const uint32_t num_connections, ++ VCHI_INSTANCE_T instance_handle ) ++{ ++ VCHIQ_STATUS_T status; ++ ++ vcos_unused(connections); ++ vcos_unused(num_connections); ++ ++ status = vchiq_connect((VCHIQ_INSTANCE_T)instance_handle); ++ ++ return (status == VCHIQ_SUCCESS) ? 0 : -1; ++} ++ ++ ++/*********************************************************** ++ * Name: vchi_disconnect ++ * ++ * Arguments: VCHI_INSTANCE_T instance_handle ++ * ++ * Description: Stops the command service on each connection, ++ * causing DE-INIT messages to be pinged back and forth ++ * ++ * Returns: 0 if successful, failure otherwise ++ * ++ ***********************************************************/ ++int32_t ++vchi_disconnect( VCHI_INSTANCE_T instance_handle ) ++{ ++ VCHIQ_STATUS_T status; ++ ++ status = vchiq_shutdown((VCHIQ_INSTANCE_T)instance_handle); ++ ++ return (status == VCHIQ_SUCCESS) ? 0 : -1; ++} ++ ++ ++/*********************************************************** ++ * Name: vchi_service_open ++ * Name: vchi_service_create ++ * ++ * Arguments: VCHI_INSTANCE_T *instance_handle ++ * SERVICE_CREATION_T *setup, ++ * VCHI_SERVICE_HANDLE_T *handle ++ * ++ * Description: Routine to open a service ++ * ++ * Returns: int32_t - success == 0 ++ * ++ ***********************************************************/ ++int32_t ++vchi_service_open( VCHI_INSTANCE_T instance_handle, ++ SERVICE_CREATION_T *setup, ++ VCHI_SERVICE_HANDLE_T *handle ) ++{ ++ VCHIQ_SERVICE_PARAMS_T params; ++ VCHIQ_STATUS_T status; ++ ++ memset(¶ms, 0, sizeof(params)); ++ params.fourcc = setup->service_id; ++ params.userdata = setup->callback_param; ++ ++ status = create_service((VCHIQ_INSTANCE_T)instance_handle, ++ ¶ms, ++ setup->callback, ++ 1/*open*/, ++ (VCHIQ_SERVICE_HANDLE_T *)handle); ++ ++ return (status == VCHIQ_SUCCESS) ? 0 : -1; ++} ++ ++int32_t ++vchi_service_create( VCHI_INSTANCE_T instance_handle, ++ SERVICE_CREATION_T *setup, VCHI_SERVICE_HANDLE_T *handle ) ++{ ++ VCHIQ_SERVICE_PARAMS_T params; ++ VCHIQ_STATUS_T status; ++ ++ memset(¶ms, 0, sizeof(params)); ++ params.fourcc = setup->service_id; ++ params.userdata = setup->callback_param; ++ ++ status = create_service((VCHIQ_INSTANCE_T)instance_handle, ++ ¶ms, ++ setup->callback, ++ 0/*!open*/, ++ (VCHIQ_SERVICE_HANDLE_T *)handle); ++ ++ return (status == VCHIQ_SUCCESS) ? 0 : -1; ++} ++ ++int32_t ++vchi_service_close( const VCHI_SERVICE_HANDLE_T handle ) ++{ ++ VCHI_SERVICE_T *service = (VCHI_SERVICE_T *)handle; ++ int ret; ++ ++ if (!is_valid_service(service)) ++ return VCHIQ_ERROR; ++ ++ RETRY(ret,ioctl(service->fd, VCHIQ_IOC_REMOVE_SERVICE, service->handle)); ++ ++ if (ret == 0) ++ service->handle = VCHIQ_INVALID_HANDLE; ++ ++ return ret; ++} ++ ++int32_t ++vchi_service_destroy( const VCHI_SERVICE_HANDLE_T handle ) ++{ ++ VCHI_SERVICE_T *service = (VCHI_SERVICE_T *)handle; ++ int ret; ++ ++ if (!is_valid_service(service)) ++ return VCHIQ_ERROR; ++ ++ RETRY(ret,ioctl(service->fd, VCHIQ_IOC_REMOVE_SERVICE, service->handle)); ++ ++ if (ret == 0) ++ service->handle = VCHIQ_INVALID_HANDLE; ++ ++ return ret; ++} ++ ++/* ---------------------------------------------------------------------- ++ * read a uint32_t from buffer. ++ * network format is defined to be little endian ++ * -------------------------------------------------------------------- */ ++uint32_t ++vchi_readbuf_uint32( const void *_ptr ) ++{ ++ const unsigned char *ptr = _ptr; ++ return ptr[0] | (ptr[1] << 8) | (ptr[2] << 16) | (ptr[3] << 24); ++} ++ ++/* ---------------------------------------------------------------------- ++ * write a uint32_t to buffer. ++ * network format is defined to be little endian ++ * -------------------------------------------------------------------- */ ++void ++vchi_writebuf_uint32( void *_ptr, uint32_t value ) ++{ ++ unsigned char *ptr = _ptr; ++ ptr[0] = (unsigned char)((value >> 0) & 0xFF); ++ ptr[1] = (unsigned char)((value >> 8) & 0xFF); ++ ptr[2] = (unsigned char)((value >> 16) & 0xFF); ++ ptr[3] = (unsigned char)((value >> 24) & 0xFF); ++} ++ ++/* ---------------------------------------------------------------------- ++ * read a uint16_t from buffer. ++ * network format is defined to be little endian ++ * -------------------------------------------------------------------- */ ++uint16_t ++vchi_readbuf_uint16( const void *_ptr ) ++{ ++ const unsigned char *ptr = _ptr; ++ return ptr[0] | (ptr[1] << 8); ++} ++ ++/* ---------------------------------------------------------------------- ++ * write a uint16_t into the buffer. ++ * network format is defined to be little endian ++ * -------------------------------------------------------------------- */ ++void ++vchi_writebuf_uint16( void *_ptr, uint16_t value ) ++{ ++ unsigned char *ptr = _ptr; ++ ptr[0] = (value >> 0) & 0xFF; ++ ptr[1] = (value >> 8) & 0xFF; ++} ++ ++/*********************************************************** ++ * Name: vchi_service_use ++ * ++ * Arguments: const VCHI_SERVICE_HANDLE_T handle ++ * ++ * Description: Routine to increment refcount on a service ++ * ++ * Returns: void ++ * ++ ***********************************************************/ ++int32_t ++vchi_service_use( const VCHI_SERVICE_HANDLE_T handle ) ++{ ++ VCHI_SERVICE_T *service = (VCHI_SERVICE_T *)handle; ++ int ret; ++ ++ if (!is_valid_service(service)) ++ return VCHIQ_ERROR; ++ ++ RETRY(ret,ioctl(service->fd, VCHIQ_IOC_USE_SERVICE, service->handle)); ++ return ret; ++} ++ ++/*********************************************************** ++ * Name: vchi_service_release ++ * ++ * Arguments: const VCHI_SERVICE_HANDLE_T handle ++ * ++ * Description: Routine to decrement refcount on a service ++ * ++ * Returns: void ++ * ++ ***********************************************************/ ++int32_t vchi_service_release( const VCHI_SERVICE_HANDLE_T handle ) ++{ ++ VCHI_SERVICE_T *service = (VCHI_SERVICE_T *)handle; ++ int ret; ++ ++ if (!is_valid_service(service)) ++ return VCHIQ_ERROR; ++ ++ RETRY(ret,ioctl(service->fd, VCHIQ_IOC_RELEASE_SERVICE, service->handle)); ++ return ret; ++} ++ ++/*********************************************************** ++ * Name: vchiq_dump_phys_mem ++ * ++ * Arguments: const VCHI_SERVICE_HANDLE_T handle ++ * void *buffer ++ * size_t num_bytes ++ * ++ * Description: Dumps the physical memory associated with ++ * a buffer. ++ * ++ * Returns: void ++ * ++ ***********************************************************/ ++VCHIQ_STATUS_T vchiq_dump_phys_mem( VCHIQ_SERVICE_HANDLE_T handle, ++ void *ptr, ++ size_t num_bytes ) ++{ ++ VCHIQ_SERVICE_T *service = (VCHIQ_SERVICE_T *)handle; ++ VCHIQ_DUMP_MEM_T dump_mem; ++ int ret; ++ ++ if (!is_valid_service(service)) ++ return VCHIQ_ERROR; ++ ++ dump_mem.virt_addr = ptr; ++ dump_mem.num_bytes = num_bytes; ++ ++ RETRY(ret,ioctl(service->fd, VCHIQ_IOC_DUMP_PHYS_MEM, &dump_mem)); ++ return (ret >= 0) ? VCHIQ_SUCCESS : VCHIQ_ERROR; ++} ++ ++ ++ ++/* ++ * Support functions ++ */ ++ ++static VCHIQ_INSTANCE_T ++vchiq_lib_init(void) ++{ ++ static int mutex_initialised = 0; ++ static VCOS_MUTEX_T vchiq_lib_mutex; ++ VCHIQ_INSTANCE_T instance = &vchiq_instance; ++ ++ vcos_global_lock(); ++ if (!mutex_initialised) ++ { ++ vcos_mutex_create(&vchiq_lib_mutex, "vchiq-init"); ++ ++ vcos_log_set_level( &vchiq_lib_log_category, vchiq_default_lib_log_level ); ++ vcos_log_register( "vchiq_lib", &vchiq_lib_log_category ); ++ ++ mutex_initialised = 1; ++ } ++ vcos_global_unlock(); ++ ++ vcos_mutex_lock(&vchiq_lib_mutex); ++ ++ if (instance->initialised == 0) ++ { ++ instance->fd = open("/dev/vchiq", O_RDWR); ++ if (instance->fd >= 0) ++ { ++ VCHIQ_GET_CONFIG_T args; ++ VCHIQ_CONFIG_T config; ++ int ret; ++ args.config_size = sizeof(config); ++ args.pconfig = &config; ++ RETRY(ret, ioctl(instance->fd, VCHIQ_IOC_GET_CONFIG, &args)); ++ if ((ret == 0) && (config.version >= VCHIQ_VERSION_MIN) && (config.version_min <= VCHIQ_VERSION)) ++ { ++ instance->used_services = 0; ++ vcos_mutex_create(&instance->mutex, "VCHIQ instance"); ++ instance->initialised = 1; ++ } ++ else ++ { ++ if (ret == 0) ++ { ++ vcos_log_error("Incompatible VCHIQ library - driver version %d (min %d), library version %d (min %d)", ++ config.version, config.version_min, VCHIQ_VERSION, VCHIQ_VERSION_MIN); ++ } ++ else ++ { ++ vcos_log_error("Very incompatible VCHIQ library - cannot retrieve driver version"); ++ } ++ close(instance->fd); ++ instance = NULL; ++ } ++ } ++ else ++ { ++ instance = NULL; ++ } ++ } ++ else if (instance->initialised > 0) ++ { ++ instance->initialised++; ++ } ++ ++ vcos_mutex_unlock(&vchiq_lib_mutex); ++ ++ return instance; ++} ++ ++static void * ++completion_thread(void *arg) ++{ ++ VCHIQ_INSTANCE_T instance = (VCHIQ_INSTANCE_T)arg; ++ VCHIQ_AWAIT_COMPLETION_T args; ++ VCHIQ_COMPLETION_DATA_T completions[8]; ++ void *msgbufs[8]; ++ ++ static const VCHI_CALLBACK_REASON_T vchiq_reason_to_vchi[] = ++ { ++ VCHI_CALLBACK_SERVICE_OPENED, // VCHIQ_SERVICE_OPENED ++ VCHI_CALLBACK_SERVICE_CLOSED, // VCHIQ_SERVICE_CLOSED ++ VCHI_CALLBACK_MSG_AVAILABLE, // VCHIQ_MESSAGE_AVAILABLE ++ VCHI_CALLBACK_BULK_SENT, // VCHIQ_BULK_TRANSMIT_DONE ++ VCHI_CALLBACK_BULK_RECEIVED, // VCHIQ_BULK_RECEIVE_DONE ++ VCHI_CALLBACK_BULK_TRANSMIT_ABORTED, // VCHIQ_BULK_TRANSMIT_ABORTED ++ VCHI_CALLBACK_BULK_RECEIVE_ABORTED, // VCHIQ_BULK_RECEIVE_ABORTED ++ }; ++ ++ args.count = vcos_countof(completions); ++ args.buf = completions; ++ args.msgbufsize = MSGBUF_SIZE; ++ args.msgbufcount = 0; ++ args.msgbufs = msgbufs; ++ ++ while (1) ++ { ++ int ret, i; ++ ++ while ((unsigned int)args.msgbufcount < vcos_countof(msgbufs)) ++ { ++ void *msgbuf = alloc_msgbuf(); ++ if (msgbuf) ++ { ++ msgbufs[args.msgbufcount++] = msgbuf; ++ } ++ else ++ { ++ fprintf(stderr, "vchiq_lib: failed to allocate a message buffer\n"); ++ vcos_demand(args.msgbufcount != 0); ++ } ++ } ++ ++ RETRY(ret, ioctl(instance->fd, VCHIQ_IOC_AWAIT_COMPLETION, &args)); ++ ++ if (ret <= 0) ++ break; ++ ++ for (i = 0; i < ret; i++) ++ { ++ VCHIQ_COMPLETION_DATA_T *completion = &completions[i]; ++ VCHIQ_SERVICE_T *service = (VCHIQ_SERVICE_T *)completion->service_userdata; ++ if (service->base.callback) ++ { ++ vcos_log_trace( "callback(%x, %x, %x, %x)", ++ completion->reason, (uint32_t)completion->header, ++ (uint32_t)&service->base, (uint32_t)completion->bulk_userdata ); ++ service->base.callback(completion->reason, completion->header, ++ &service->base, completion->bulk_userdata); ++ } ++ else if (service->vchi_callback) ++ { ++ VCHI_CALLBACK_REASON_T vchi_reason = ++ vchiq_reason_to_vchi[completion->reason]; ++ service->vchi_callback(service->base.userdata, vchi_reason, completion->bulk_userdata); ++ } ++ } ++ } ++ return NULL; ++} ++ ++static VCHIQ_STATUS_T ++create_service(VCHIQ_INSTANCE_T instance, ++ const VCHIQ_SERVICE_PARAMS_T *params, ++ VCHI_CALLBACK_T vchi_callback, ++ int is_open, ++ VCHIQ_SERVICE_HANDLE_T *pservice) ++{ ++ VCHIQ_SERVICE_T *service = NULL; ++ VCHIQ_STATUS_T status = VCHIQ_SUCCESS; ++ int i; ++ ++ if (!is_valid_instance(instance)) ++ return VCHIQ_ERROR; ++ ++ vcos_mutex_lock(&instance->mutex); ++ ++ /* Find a free service */ ++ if (is_open) ++ { ++ /* Find a free service */ ++ for (i = 0; i < instance->used_services; i++) ++ { ++ if (instance->services[i].handle == VCHIQ_INVALID_HANDLE) ++ { ++ service = &instance->services[i]; ++ break; ++ } ++ } ++ } ++ else ++ { ++ for (i = (instance->used_services - 1); i >= 0; i--) ++ { ++ VCHIQ_SERVICE_T *srv = &instance->services[i]; ++ if (srv->handle == VCHIQ_INVALID_HANDLE) ++ { ++ service = srv; ++ } ++ else if ( ++ (srv->base.fourcc == params->fourcc) && ++ ((srv->base.callback != params->callback) || ++ (srv->vchi_callback != vchi_callback))) ++ { ++ /* There is another server using this fourcc which doesn't match */ ++ service = NULL; ++ status = VCHIQ_ERROR; ++ break; ++ } ++ } ++ } ++ ++ if (!service && (status == VCHIQ_SUCCESS) && ++ (instance->used_services < VCHIQ_MAX_INSTANCE_SERVICES)) ++ service = &instance->services[instance->used_services++]; ++ ++ if (service) ++ { ++ VCHIQ_CREATE_SERVICE_T args; ++ int ret; ++ service->base.fourcc = params->fourcc; ++ service->base.callback = params->callback; ++ service->vchi_callback = vchi_callback; ++ service->base.userdata = params->userdata; ++ service->fd = instance->fd; ++ service->peek_size = -1; ++ service->peek_buf = NULL; ++ ++ args.params = *params; ++ args.params.userdata = service; ++ args.is_open = is_open; ++ args.is_vchi = (params->callback == NULL); ++ args.handle = -1; /* OUT parameter */ ++ RETRY(ret, ioctl(instance->fd, VCHIQ_IOC_CREATE_SERVICE, &args)); ++ if (ret == 0) ++ service->handle = args.handle; ++ else ++ status = VCHIQ_ERROR; ++ } ++ ++ *pservice = (status == VCHIQ_SUCCESS) ? &service->base : NULL; ++ ++ vcos_mutex_unlock(&instance->mutex); ++ ++ return status; ++} ++ ++static int ++fill_peek_buf(VCHI_SERVICE_T *service, ++ VCHI_FLAGS_T flags) ++{ ++ VCHIQ_DEQUEUE_MESSAGE_T args; ++ int ret = 0; ++ ++ vcos_assert(flags == VCHI_FLAGS_NONE || flags == VCHI_FLAGS_BLOCK_UNTIL_OP_COMPLETE); ++ ++ if (service->peek_size < 0) ++ { ++ if (!service->peek_buf) ++ service->peek_buf = alloc_msgbuf(); ++ ++ if (service->peek_buf) ++ { ++ args.handle = service->handle; ++ args.blocking = (flags == VCHI_FLAGS_BLOCK_UNTIL_OP_COMPLETE); ++ args.bufsize = MSGBUF_SIZE; ++ args.buf = service->peek_buf; ++ ++ RETRY(ret, ioctl(service->fd, VCHIQ_IOC_DEQUEUE_MESSAGE, &args)); ++ ++ if (ret >= 0) ++ { ++ service->peek_size = ret; ++ ret = 0; ++ } ++ else ++ { ++ ret = -1; ++ } ++ } ++ else ++ { ++ ret = -1; ++ } ++ } ++ ++ return ret; ++} ++ ++ ++static void * ++alloc_msgbuf(void) ++{ ++ void *msgbuf; ++ vcos_mutex_lock(&vchiq_lib_mutex); ++ msgbuf = free_msgbufs; ++ if (msgbuf) ++ free_msgbufs = *(void **)msgbuf; ++ vcos_mutex_unlock(&vchiq_lib_mutex); ++ if (!msgbuf) ++ msgbuf = malloc(MSGBUF_SIZE); ++ return msgbuf; ++} ++ ++static void ++free_msgbuf(void *buf) ++{ ++ vcos_mutex_lock(&vchiq_lib_mutex); ++ *(void **)buf = free_msgbufs; ++ free_msgbufs = buf; ++ vcos_mutex_unlock(&vchiq_lib_mutex); ++} +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_memdrv.h +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_memdrv.h 2013-07-26 19:36:51.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_memdrv.h 2013-07-26 19:37:11.000000000 +0000 +@@ -22,31 +22,24 @@ + + /* ---- Constants and Types ---------------------------------------------- */ + +-typedef struct { +- void *armSharedMemVirt; +- dma_addr_t armSharedMemPhys; +- size_t armSharedMemSize; +- +- void *vcSharedMemVirt; +- dma_addr_t vcSharedMemPhys; +- size_t vcSharedMemSize; ++typedef struct ++{ ++ void *armSharedMemVirt; ++ dma_addr_t armSharedMemPhys; ++ size_t armSharedMemSize; ++ ++ void *vcSharedMemVirt; ++ dma_addr_t vcSharedMemPhys; ++ size_t vcSharedMemSize; ++ + } VCHIQ_SHARED_MEM_INFO_T; + + /* ---- Variable Externs ------------------------------------------------- */ + + /* ---- Function Prototypes ---------------------------------------------- */ + +-void vchiq_get_shared_mem_info(VCHIQ_SHARED_MEM_INFO_T *info); ++void vchiq_get_shared_mem_info( VCHIQ_SHARED_MEM_INFO_T *info ); + + VCHIQ_STATUS_T vchiq_memdrv_initialise(void); + +-VCHIQ_STATUS_T vchiq_userdrv_create_instance( +- const VCHIQ_PLATFORM_DATA_T * platform_data); +- +-VCHIQ_STATUS_T vchiq_userdrv_suspend( +- const VCHIQ_PLATFORM_DATA_T * platform_data); +- +-VCHIQ_STATUS_T vchiq_userdrv_resume( +- const VCHIQ_PLATFORM_DATA_T * platform_data); +- + #endif +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_shim.c +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_shim.c 2013-07-26 19:36:51.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_shim.c 2013-07-26 19:37:11.000000000 +0000 +@@ -15,8 +15,6 @@ + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +-#include +-#include + + #include "interface/vchi/vchi.h" + #include "vchiq.h" +@@ -26,42 +24,56 @@ + + #include + ++#if defined(__KERNEL__) ++#include ++#endif ++ + #define vchiq_status_to_vchi(status) ((int32_t)status) + + typedef struct { +- VCHIQ_SERVICE_HANDLE_T handle; ++ VCHIQ_SERVICE_HANDLE_T handle; + +- VCHIU_QUEUE_T queue; ++ VCHIU_QUEUE_T queue; + +- VCHI_CALLBACK_T callback; +- void *callback_param; ++ VCHI_CALLBACK_T callback; ++ void *callback_param; + } SHIM_SERVICE_T; + + /* ---------------------------------------------------------------------- + * return pointer to the mphi message driver function table + * -------------------------------------------------------------------- */ ++#ifdef WIN32 + const VCHI_MESSAGE_DRIVER_T * +-vchi_mphi_message_driver_func_table(void) ++mphi_get_func_table( void ) + { +- return NULL; ++ return NULL; ++} ++#endif ++ ++/* ---------------------------------------------------------------------- ++ * return pointer to the mphi message driver function table ++ * -------------------------------------------------------------------- */ ++const VCHI_MESSAGE_DRIVER_T * ++vchi_mphi_message_driver_func_table( void ) ++{ ++ return NULL; + } + + /* ---------------------------------------------------------------------- + * return a pointer to the 'single' connection driver fops + * -------------------------------------------------------------------- */ + const VCHI_CONNECTION_API_T * +-single_get_func_table(void) ++single_get_func_table( void ) + { +- return NULL; ++ return NULL; + } + +-VCHI_CONNECTION_T *vchi_create_connection( +- const VCHI_CONNECTION_API_T *function_table, +- const VCHI_MESSAGE_DRIVER_T *low_level) ++VCHI_CONNECTION_T * vchi_create_connection( const VCHI_CONNECTION_API_T * function_table, ++ const VCHI_MESSAGE_DRIVER_T * low_level) + { +- (void)function_table; +- (void)low_level; +- return NULL; ++ vcos_unused(function_table); ++ vcos_unused(low_level); ++ return NULL; + } + + /*********************************************************** +@@ -70,64 +82,57 @@ + * Arguments: const VCHI_SERVICE_HANDLE_T handle, + * void **data, + * uint32_t *msg_size, +- +- + * VCHI_FLAGS_T flags + * +- * Description: Routine to return a pointer to the current message (to allow in +- * place processing). The message can be removed using +- * vchi_msg_remove when you're finished ++ * Description: Routine to return a pointer to the current message (to allow in place processing) ++ * The message can be removed using vchi_msg_remove when you're finished + * + * Returns: int32_t - success == 0 + * + ***********************************************************/ +-int32_t vchi_msg_peek(VCHI_SERVICE_HANDLE_T handle, +- void **data, +- uint32_t *msg_size, +- VCHI_FLAGS_T flags) ++int32_t vchi_msg_peek( VCHI_SERVICE_HANDLE_T handle, ++ void **data, ++ uint32_t *msg_size, ++ VCHI_FLAGS_T flags ) + { +- SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle; +- VCHIQ_HEADER_T *header; ++ SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle; ++ VCHIQ_HEADER_T *header; + +- WARN_ON((flags != VCHI_FLAGS_NONE) && +- (flags != VCHI_FLAGS_BLOCK_UNTIL_OP_COMPLETE)); ++ vcos_assert(flags == VCHI_FLAGS_NONE || flags == VCHI_FLAGS_BLOCK_UNTIL_OP_COMPLETE); + +- if (flags == VCHI_FLAGS_NONE) +- if (vchiu_queue_is_empty(&service->queue)) +- return -1; ++ if (flags == VCHI_FLAGS_NONE) ++ if (vchiu_queue_is_empty(&service->queue)) ++ return -1; + +- header = vchiu_queue_peek(&service->queue); ++ header = vchiu_queue_peek(&service->queue); + +- *data = header->data; +- *msg_size = header->size; ++ *data = header->data; ++ *msg_size = header->size; + +- return 0; ++ return 0; + } +-EXPORT_SYMBOL(vchi_msg_peek); + + /*********************************************************** + * Name: vchi_msg_remove + * + * Arguments: const VCHI_SERVICE_HANDLE_T handle, + * +- * Description: Routine to remove a message (after it has been read with +- * vchi_msg_peek) ++ * Description: Routine to remove a message (after it has been read with vchi_msg_peek) + * + * Returns: int32_t - success == 0 + * + ***********************************************************/ +-int32_t vchi_msg_remove(VCHI_SERVICE_HANDLE_T handle) ++int32_t vchi_msg_remove( VCHI_SERVICE_HANDLE_T handle ) + { +- SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle; +- VCHIQ_HEADER_T *header; ++ SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle; ++ VCHIQ_HEADER_T *header; + +- header = vchiu_queue_pop(&service->queue); ++ header = vchiu_queue_pop(&service->queue); + +- vchiq_release_message(service->handle, header); ++ vchiq_release_message(service->handle, header); + +- return 0; ++ return 0; + } +-EXPORT_SYMBOL(vchi_msg_remove); + + /*********************************************************** + * Name: vchi_msg_queue +@@ -143,34 +148,33 @@ + * Returns: int32_t - success == 0 + * + ***********************************************************/ +-int32_t vchi_msg_queue(VCHI_SERVICE_HANDLE_T handle, +- const void *data, +- uint32_t data_size, +- VCHI_FLAGS_T flags, +- void *msg_handle) +-{ +- SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle; +- VCHIQ_ELEMENT_T element = {data, data_size}; +- VCHIQ_STATUS_T status; +- +- (void)msg_handle; +- +- WARN_ON(flags != VCHI_FLAGS_BLOCK_UNTIL_QUEUED); +- +- status = vchiq_queue_message(service->handle, &element, 1); +- +- /* vchiq_queue_message() may return VCHIQ_RETRY, so we need to +- ** implement a retry mechanism since this function is supposed +- ** to block until queued +- */ +- while (status == VCHIQ_RETRY) { +- msleep(1); +- status = vchiq_queue_message(service->handle, &element, 1); +- } ++int32_t vchi_msg_queue( VCHI_SERVICE_HANDLE_T handle, ++ const void * data, ++ uint32_t data_size, ++ VCHI_FLAGS_T flags, ++ void * msg_handle ) ++{ ++ SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle; ++ VCHIQ_ELEMENT_T element = {data, data_size}; ++ VCHIQ_STATUS_T status; ++ ++ vcos_unused(msg_handle); ++ ++ vcos_assert(flags == VCHI_FLAGS_BLOCK_UNTIL_QUEUED); ++ ++ status = vchiq_queue_message(service->handle, &element, 1); ++ ++ // On some platforms, like linux kernel, vchiq_queue_message() may return ++ // VCHIQ_RETRY, so we need to implment a retry mechanism since this ++ // function is supposed to block until queued ++ while ( status == VCHIQ_RETRY ) ++ { ++ vcos_sleep( 1 ); ++ status = vchiq_queue_message(service->handle, &element, 1); ++ } + +- return vchiq_status_to_vchi(status); ++ return vchiq_status_to_vchi(status); + } +-EXPORT_SYMBOL(vchi_msg_queue); + + /*********************************************************** + * Name: vchi_bulk_queue_receive +@@ -186,50 +190,107 @@ + * Returns: int32_t - success == 0 + * + ***********************************************************/ +-int32_t vchi_bulk_queue_receive(VCHI_SERVICE_HANDLE_T handle, +- void *data_dst, +- uint32_t data_size, +- VCHI_FLAGS_T flags, +- void *bulk_handle) +-{ +- SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle; +- VCHIQ_BULK_MODE_T mode; +- VCHIQ_STATUS_T status; +- +- switch ((int)flags) { +- case VCHI_FLAGS_CALLBACK_WHEN_OP_COMPLETE +- | VCHI_FLAGS_BLOCK_UNTIL_QUEUED: +- WARN_ON(!service->callback); +- mode = VCHIQ_BULK_MODE_CALLBACK; +- break; +- case VCHI_FLAGS_BLOCK_UNTIL_OP_COMPLETE: +- mode = VCHIQ_BULK_MODE_BLOCKING; +- break; +- case VCHI_FLAGS_BLOCK_UNTIL_QUEUED: +- case VCHI_FLAGS_NONE: +- mode = VCHIQ_BULK_MODE_NOCALLBACK; +- break; +- default: +- WARN(1, "unsupported message\n"); +- return vchiq_status_to_vchi(VCHIQ_ERROR); +- } +- +- status = vchiq_bulk_receive(service->handle, data_dst, data_size, +- bulk_handle, mode); +- +- /* vchiq_bulk_receive() may return VCHIQ_RETRY, so we need to +- ** implement a retry mechanism since this function is supposed +- ** to block until queued +- */ +- while (status == VCHIQ_RETRY) { +- msleep(1); +- status = vchiq_bulk_receive(service->handle, data_dst, +- data_size, bulk_handle, mode); +- } ++int32_t vchi_bulk_queue_receive( VCHI_SERVICE_HANDLE_T handle, ++ void * data_dst, ++ uint32_t data_size, ++ VCHI_FLAGS_T flags, ++ void * bulk_handle ) ++{ ++ SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle; ++ VCHIQ_BULK_MODE_T mode; ++ VCHIQ_STATUS_T status; ++ ++ switch ((int)flags) { ++ case VCHI_FLAGS_CALLBACK_WHEN_OP_COMPLETE | VCHI_FLAGS_BLOCK_UNTIL_QUEUED: ++ vcos_assert(service->callback); ++ mode = VCHIQ_BULK_MODE_CALLBACK; ++ break; ++ case VCHI_FLAGS_BLOCK_UNTIL_OP_COMPLETE: ++ mode = VCHIQ_BULK_MODE_BLOCKING; ++ break; ++ case VCHI_FLAGS_BLOCK_UNTIL_QUEUED: ++ case VCHI_FLAGS_NONE: ++ mode = VCHIQ_BULK_MODE_NOCALLBACK; ++ break; ++ default: ++ vcos_assert(0); ++ return vchiq_status_to_vchi(VCHIQ_ERROR); ++ } ++ ++ status = vchiq_bulk_receive(service->handle, data_dst, data_size, ++ bulk_handle, mode); ++ ++ // On some platforms, like linux kernel, vchiq_bulk_receive() may return ++ // VCHIQ_RETRY, so we need to implment a retry mechanism since this ++ // function is supposed to block until queued ++ while ( status == VCHIQ_RETRY ) ++ { ++ vcos_sleep( 1 ); ++ status = vchiq_bulk_receive(service->handle, data_dst, data_size, ++ bulk_handle, mode); ++ } ++ ++ return vchiq_status_to_vchi(status); ++} ++ ++/*********************************************************** ++ * Name: vchi_bulk_queue_receive_reloc ++ * ++ * Arguments: VCHI_BULK_HANDLE_T handle, ++ * VCHI_MEM_HANDLE_T h ++ * uint32_t offset ++ * const uint32_t data_size, ++ * VCHI_FLAGS_T flags ++ * void *bulk_handle ++ * ++ * Description: Routine to setup a relocatable rcv buffer ++ * ++ * Returns: int32_t - success == 0 ++ * ++ ***********************************************************/ ++int32_t vchi_bulk_queue_receive_reloc( const VCHI_SERVICE_HANDLE_T handle, ++ VCHI_MEM_HANDLE_T h, ++ uint32_t offset, ++ uint32_t data_size, ++ const VCHI_FLAGS_T flags, ++ void * const bulk_handle ) ++{ ++ SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle; ++ VCHIQ_BULK_MODE_T mode; ++ VCHIQ_STATUS_T status; ++ ++ switch ((int)flags) { ++ case VCHI_FLAGS_CALLBACK_WHEN_OP_COMPLETE | VCHI_FLAGS_BLOCK_UNTIL_QUEUED: ++ vcos_assert(service->callback); ++ mode = VCHIQ_BULK_MODE_CALLBACK; ++ break; ++ case VCHI_FLAGS_BLOCK_UNTIL_OP_COMPLETE: ++ mode = VCHIQ_BULK_MODE_BLOCKING; ++ break; ++ case VCHI_FLAGS_BLOCK_UNTIL_QUEUED: ++ case VCHI_FLAGS_NONE: ++ mode = VCHIQ_BULK_MODE_NOCALLBACK; ++ break; ++ default: ++ vcos_assert(0); ++ return vchiq_status_to_vchi(VCHIQ_ERROR); ++ } ++ ++ status = vchiq_bulk_receive_handle(service->handle, h, (void*)offset, ++ data_size, bulk_handle, mode); ++ ++ // On some platforms, like linux kernel, vchiq_bulk_receive_handle() may ++ // return VCHIQ_RETRY, so we need to implment a retry mechanism since ++ // this function is supposed to block until queued ++ while ( status == VCHIQ_RETRY ) ++ { ++ vcos_sleep( 1 ); ++ status = vchiq_bulk_receive_handle(service->handle, h, (void*)offset, ++ data_size, bulk_handle, mode); ++ } + +- return vchiq_status_to_vchi(status); ++ return vchiq_status_to_vchi(status); + } +-EXPORT_SYMBOL(vchi_bulk_queue_receive); + + /*********************************************************** + * Name: vchi_bulk_queue_transmit +@@ -245,51 +306,110 @@ + * Returns: int32_t - success == 0 + * + ***********************************************************/ +-int32_t vchi_bulk_queue_transmit(VCHI_SERVICE_HANDLE_T handle, +- const void *data_src, +- uint32_t data_size, +- VCHI_FLAGS_T flags, +- void *bulk_handle) +-{ +- SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle; +- VCHIQ_BULK_MODE_T mode; +- VCHIQ_STATUS_T status; +- +- switch ((int)flags) { +- case VCHI_FLAGS_CALLBACK_WHEN_OP_COMPLETE +- | VCHI_FLAGS_BLOCK_UNTIL_QUEUED: +- WARN_ON(!service->callback); +- mode = VCHIQ_BULK_MODE_CALLBACK; +- break; +- case VCHI_FLAGS_BLOCK_UNTIL_DATA_READ: +- case VCHI_FLAGS_BLOCK_UNTIL_OP_COMPLETE: +- mode = VCHIQ_BULK_MODE_BLOCKING; +- break; +- case VCHI_FLAGS_BLOCK_UNTIL_QUEUED: +- case VCHI_FLAGS_NONE: +- mode = VCHIQ_BULK_MODE_NOCALLBACK; +- break; +- default: +- WARN(1, "unsupported message\n"); +- return vchiq_status_to_vchi(VCHIQ_ERROR); +- } +- +- status = vchiq_bulk_transmit(service->handle, data_src, data_size, +- bulk_handle, mode); +- +- /* vchiq_bulk_transmit() may return VCHIQ_RETRY, so we need to +- ** implement a retry mechanism since this function is supposed +- ** to block until queued +- */ +- while (status == VCHIQ_RETRY) { +- msleep(1); +- status = vchiq_bulk_transmit(service->handle, data_src, +- data_size, bulk_handle, mode); +- } ++int32_t vchi_bulk_queue_transmit( VCHI_SERVICE_HANDLE_T handle, ++ const void * data_src, ++ uint32_t data_size, ++ VCHI_FLAGS_T flags, ++ void * bulk_handle ) ++{ ++ SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle; ++ VCHIQ_BULK_MODE_T mode; ++ VCHIQ_STATUS_T status; ++ ++ switch ((int)flags) { ++ case VCHI_FLAGS_CALLBACK_WHEN_OP_COMPLETE | VCHI_FLAGS_BLOCK_UNTIL_QUEUED: ++ vcos_assert(service->callback); ++ mode = VCHIQ_BULK_MODE_CALLBACK; ++ break; ++ case VCHI_FLAGS_BLOCK_UNTIL_DATA_READ: ++ case VCHI_FLAGS_BLOCK_UNTIL_OP_COMPLETE: ++ mode = VCHIQ_BULK_MODE_BLOCKING; ++ break; ++ case VCHI_FLAGS_BLOCK_UNTIL_QUEUED: ++ case VCHI_FLAGS_NONE: ++ mode = VCHIQ_BULK_MODE_NOCALLBACK; ++ break; ++ default: ++ vcos_assert(0); ++ return vchiq_status_to_vchi(VCHIQ_ERROR); ++ } ++ ++ status = vchiq_bulk_transmit(service->handle, data_src, data_size, ++ bulk_handle, mode); ++ ++ // On some platforms, like linux kernel, vchiq_bulk_transmit() may return ++ // VCHIQ_RETRY, so we need to implment a retry mechanism since this ++ // function is supposed to block until queued ++ while ( status == VCHIQ_RETRY ) ++ { ++ vcos_sleep( 1 ); ++ status = vchiq_bulk_transmit(service->handle, data_src, data_size, ++ bulk_handle, mode); ++ } + +- return vchiq_status_to_vchi(status); ++ return vchiq_status_to_vchi(status); ++} ++ ++/*********************************************************** ++ * Name: vchi_bulk_queue_transmit_reloc ++ * ++ * Arguments: VCHI_BULK_HANDLE_T handle, ++ * VCHI_MEM_HANDLE_T h_src, ++ * uint32_t offset, ++ * uint32_t data_size, ++ * VCHI_FLAGS_T flags, ++ * void *bulk_handle ++ * ++ * Description: Routine to transmit some data from a relocatable buffer ++ * ++ * Returns: int32_t - success == 0 ++ * ++ ***********************************************************/ ++ ++int32_t vchi_bulk_queue_transmit_reloc( VCHI_SERVICE_HANDLE_T handle, ++ VCHI_MEM_HANDLE_T h_src, ++ uint32_t offset, ++ uint32_t data_size, ++ VCHI_FLAGS_T flags, ++ void * const bulk_handle ) ++{ ++ SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle; ++ VCHIQ_BULK_MODE_T mode; ++ VCHIQ_STATUS_T status; ++ ++ switch ((int)flags) { ++ case VCHI_FLAGS_CALLBACK_WHEN_OP_COMPLETE | VCHI_FLAGS_BLOCK_UNTIL_QUEUED: ++ vcos_assert(service->callback); ++ mode = VCHIQ_BULK_MODE_CALLBACK; ++ break; ++ case VCHI_FLAGS_BLOCK_UNTIL_DATA_READ: ++ case VCHI_FLAGS_BLOCK_UNTIL_OP_COMPLETE: ++ mode = VCHIQ_BULK_MODE_BLOCKING; ++ break; ++ case VCHI_FLAGS_BLOCK_UNTIL_QUEUED: ++ case VCHI_FLAGS_NONE: ++ mode = VCHIQ_BULK_MODE_NOCALLBACK; ++ break; ++ default: ++ vcos_assert(0); ++ return vchiq_status_to_vchi(VCHIQ_ERROR); ++ } ++ ++ status = vchiq_bulk_transmit_handle(service->handle, h_src, (void*)offset, ++ data_size, bulk_handle, mode); ++ ++ // On some platforms, like linux kernel, vchiq_bulk_transmit_handle() may ++ // return VCHIQ_RETRY, so we need to implment a retry mechanism since this ++ // function is supposed to block until queued ++ while ( status == VCHIQ_RETRY ) ++ { ++ vcos_sleep( 1 ); ++ status = vchiq_bulk_transmit_handle(service->handle, h_src, (void*)offset, ++ data_size, bulk_handle, mode); ++ } ++ ++ return vchiq_status_to_vchi(status); + } +-EXPORT_SYMBOL(vchi_bulk_queue_transmit); + + /*********************************************************** + * Name: vchi_msg_dequeue +@@ -305,41 +425,38 @@ + * Returns: int32_t - success == 0 + * + ***********************************************************/ +-int32_t vchi_msg_dequeue(VCHI_SERVICE_HANDLE_T handle, +- void *data, +- uint32_t max_data_size_to_read, +- uint32_t *actual_msg_size, +- VCHI_FLAGS_T flags) ++int32_t vchi_msg_dequeue( VCHI_SERVICE_HANDLE_T handle, ++ void *data, ++ uint32_t max_data_size_to_read, ++ uint32_t *actual_msg_size, ++ VCHI_FLAGS_T flags ) + { +- SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle; +- VCHIQ_HEADER_T *header; ++ SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle; ++ VCHIQ_HEADER_T *header; + +- WARN_ON((flags != VCHI_FLAGS_NONE) && +- (flags != VCHI_FLAGS_BLOCK_UNTIL_OP_COMPLETE)); ++ vcos_assert(flags == VCHI_FLAGS_NONE || flags == VCHI_FLAGS_BLOCK_UNTIL_OP_COMPLETE); + +- if (flags == VCHI_FLAGS_NONE) +- if (vchiu_queue_is_empty(&service->queue)) +- return -1; ++ if (flags == VCHI_FLAGS_NONE) ++ if (vchiu_queue_is_empty(&service->queue)) ++ return -1; + +- header = vchiu_queue_pop(&service->queue); ++ header = vchiu_queue_pop(&service->queue); + +- memcpy(data, header->data, header->size < max_data_size_to_read ? +- header->size : max_data_size_to_read); ++ memcpy(data, header->data, header->size < max_data_size_to_read ? header->size : max_data_size_to_read); + +- *actual_msg_size = header->size; ++ *actual_msg_size = header->size; + +- vchiq_release_message(service->handle, header); ++ vchiq_release_message(service->handle, header); + +- return 0; ++ return 0; + } +-EXPORT_SYMBOL(vchi_msg_dequeue); + + /*********************************************************** + * Name: vchi_msg_queuev + * + * Arguments: VCHI_SERVICE_HANDLE_T handle, +- * VCHI_MSG_VECTOR_T *vector, +- * uint32_t count, ++ * const void *data, ++ * uint32_t data_size, + * VCHI_FLAGS_T flags, + * void *msg_handle + * +@@ -349,46 +466,151 @@ + * + ***********************************************************/ + +-vchiq_static_assert(sizeof(VCHI_MSG_VECTOR_T) == sizeof(VCHIQ_ELEMENT_T)); +-vchiq_static_assert(offsetof(VCHI_MSG_VECTOR_T, vec_base) == +- offsetof(VCHIQ_ELEMENT_T, data)); +-vchiq_static_assert(offsetof(VCHI_MSG_VECTOR_T, vec_len) == +- offsetof(VCHIQ_ELEMENT_T, size)); +- +-int32_t vchi_msg_queuev(VCHI_SERVICE_HANDLE_T handle, +- VCHI_MSG_VECTOR_T *vector, +- uint32_t count, +- VCHI_FLAGS_T flags, +- void *msg_handle) ++vcos_static_assert(sizeof(VCHI_MSG_VECTOR_T) == sizeof(VCHIQ_ELEMENT_T)); ++vcos_static_assert(offsetof(VCHI_MSG_VECTOR_T, vec_base) == offsetof(VCHIQ_ELEMENT_T, data)); ++vcos_static_assert(offsetof(VCHI_MSG_VECTOR_T, vec_len) == offsetof(VCHIQ_ELEMENT_T, size)); ++ ++int32_t vchi_msg_queuev( VCHI_SERVICE_HANDLE_T handle, ++ VCHI_MSG_VECTOR_T * vector, ++ uint32_t count, ++ VCHI_FLAGS_T flags, ++ void *msg_handle ) + { +- SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle; ++ SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle; + +- (void)msg_handle; ++ vcos_unused(msg_handle); + +- WARN_ON(flags != VCHI_FLAGS_BLOCK_UNTIL_QUEUED); ++ vcos_assert(flags == VCHI_FLAGS_BLOCK_UNTIL_QUEUED); + +- return vchiq_status_to_vchi(vchiq_queue_message(service->handle, +- (const VCHIQ_ELEMENT_T *)vector, count)); ++ return vchiq_status_to_vchi(vchiq_queue_message(service->handle, (const VCHIQ_ELEMENT_T *)vector, count)); + } +-EXPORT_SYMBOL(vchi_msg_queuev); ++ ++#ifdef USE_MEMMGR ++ ++/*********************************************************** ++ * Name: vchi_msg_queuev_ex ++ * ++ * Arguments: VCHI_SERVICE_HANDLE_T handle, ++ * VCHI_MSG_VECTOR_EX_T *vector ++ * uint32_t count ++ * VCHI_FLAGS_T flags, ++ * void *msg_handle ++ * ++ * Description: Thin wrapper to queue an array of messages onto a connection ++ * Supports resolving MEM_HANDLE's at last possible moment to avoid deadlocks. ++ * ++ * Currently just a shim, so deadlocks are still possible! ++ * ++ * Returns: int32_t - success == 0 ++ * ++ ***********************************************************/ ++int32_t vchi_msg_queuev_ex( const VCHI_SERVICE_HANDLE_T handle, ++ VCHI_MSG_VECTOR_EX_T * const vector, ++ const uint32_t count, ++ const VCHI_FLAGS_T flags, ++ void * const msg_handle ) ++{ ++ int32_t success = -1; ++ // For now, we don't actually support sending anything other than ++ // a pointer, so handles have to be patched up; this is likely ++ // to cause deadlocks. This code is not designed to be either ++ // pretty, efficient, or deadlock-free. ++ ++ #define max_vecs 16 ++ VCHI_MSG_VECTOR_T copy[max_vecs]; ++ const uint8_t *orig[max_vecs]; ++ ++ int i; ++ vcos_unused(msg_handle); ++ ++ if (count > sizeof(copy)/sizeof(copy[0])) ++ { ++ vcos_assert(0); ++ return -1; ++ } ++ ++ for (i=0; iu.ptr.vec_base; ++ copy[i].vec_len = v->u.ptr.vec_len; ++ break; ++ case VCHI_VEC_HANDLE: ++ vcos_assert(v->u.handle.offset+v->u.handle.vec_len <= mem_get_size(v->u.handle.handle)); ++ copy[i].vec_base = (uint8_t*)mem_lock(v->u.handle.handle) + v->u.handle.offset; ++ orig[i] = copy[i].vec_base; ++ copy[i].vec_len = v->u.handle.vec_len; ++ break; ++ case VCHI_VEC_LIST: ++ vcos_assert(0); // FIXME: implement this ++ break; ++ default: ++ vcos_assert(0); ++ } ++ } ++ success = vchi_msg_queuev( handle, ++ copy, ++ count, ++ flags &~ VCHI_FLAGS_INTERNAL, ++ msg_handle ); ++ if (vcos_verify(success == 0)) ++ { ++ // now we need to patch up the vectors if any have been only partially consumed, and ++ // unlock memory handles. ++ ++ for (i=0; iu.ptr.vec_base = copy[i].vec_base; ++ v->u.ptr.vec_len = copy[i].vec_len; ++ } ++ break; ++ case VCHI_VEC_HANDLE: ++ mem_unlock(v->u.handle.handle); ++ if (flags & VCHI_FLAGS_ALLOW_PARTIAL) ++ { ++ const uint8_t *old = orig[i]; ++ uint32_t change = (const uint8_t*)copy[i].vec_base-old; ++ v->u.handle.offset += change; ++ v->u.handle.vec_len -= change; ++ } ++ break; ++ default: ++ vcos_assert(0); ++ } ++ } ++ } ++ ++ return vchiq_status_to_vchi(success); ++} ++ ++#endif + + /*********************************************************** + * Name: vchi_held_msg_release + * + * Arguments: VCHI_HELD_MSG_T *message + * +- * Description: Routine to release a held message (after it has been read with +- * vchi_msg_hold) ++ * Description: Routine to release a held message (after it has been read with vchi_msg_hold) + * + * Returns: int32_t - success == 0 + * + ***********************************************************/ +-int32_t vchi_held_msg_release(VCHI_HELD_MSG_T *message) ++int32_t vchi_held_msg_release( VCHI_HELD_MSG_T *message ) + { +- vchiq_release_message((VCHIQ_SERVICE_HANDLE_T)message->service, +- (VCHIQ_HEADER_T *)message->message); ++ vchiq_release_message((VCHIQ_SERVICE_HANDLE_T)message->service, (VCHIQ_HEADER_T *)message->message); + +- return 0; ++ return 0; + } + + /*********************************************************** +@@ -400,40 +622,37 @@ + * VCHI_FLAGS_T flags, + * VCHI_HELD_MSG_T *message_handle + * +- * Description: Routine to return a pointer to the current message (to allow +- * in place processing). The message is dequeued - don't forget +- * to release the message using vchi_held_msg_release when you're +- * finished. ++ * Description: Routine to return a pointer to the current message (to allow in place processing) ++ * The message is dequeued - don't forget to release the message using ++ * vchi_held_msg_release when you're finished + * + * Returns: int32_t - success == 0 + * + ***********************************************************/ +-int32_t vchi_msg_hold(VCHI_SERVICE_HANDLE_T handle, +- void **data, +- uint32_t *msg_size, +- VCHI_FLAGS_T flags, +- VCHI_HELD_MSG_T *message_handle) ++int32_t vchi_msg_hold( VCHI_SERVICE_HANDLE_T handle, ++ void **data, ++ uint32_t *msg_size, ++ VCHI_FLAGS_T flags, ++ VCHI_HELD_MSG_T *message_handle ) + { +- SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle; +- VCHIQ_HEADER_T *header; ++ SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle; ++ VCHIQ_HEADER_T *header; + +- WARN_ON((flags != VCHI_FLAGS_NONE) && +- (flags != VCHI_FLAGS_BLOCK_UNTIL_OP_COMPLETE)); ++ vcos_assert(flags == VCHI_FLAGS_NONE || flags == VCHI_FLAGS_BLOCK_UNTIL_OP_COMPLETE); + +- if (flags == VCHI_FLAGS_NONE) +- if (vchiu_queue_is_empty(&service->queue)) +- return -1; ++ if (flags == VCHI_FLAGS_NONE) ++ if (vchiu_queue_is_empty(&service->queue)) ++ return -1; + +- header = vchiu_queue_pop(&service->queue); ++ header = vchiu_queue_pop(&service->queue); + +- *data = header->data; +- *msg_size = header->size; ++ *data = header->data; ++ *msg_size = header->size; + +- message_handle->service = +- (struct opaque_vchi_service_t *)service->handle; +- message_handle->message = header; ++ message_handle->service = (struct opaque_vchi_service_t *)service->handle; ++ message_handle->message = header; + +- return 0; ++ return 0; + } + + /*********************************************************** +@@ -451,25 +670,24 @@ + * + ***********************************************************/ + +-int32_t vchi_initialise(VCHI_INSTANCE_T *instance_handle) ++int32_t vchi_initialise( VCHI_INSTANCE_T *instance_handle ) + { +- VCHIQ_INSTANCE_T instance; +- VCHIQ_STATUS_T status; ++ VCHIQ_INSTANCE_T instance; ++ VCHIQ_STATUS_T status; + +- status = vchiq_initialise(&instance); ++ status = vchiq_initialise(&instance); + +- *instance_handle = (VCHI_INSTANCE_T)instance; ++ *instance_handle = (VCHI_INSTANCE_T)instance; + +- return vchiq_status_to_vchi(status); ++ return vchiq_status_to_vchi(status); + } +-EXPORT_SYMBOL(vchi_initialise); + + /*********************************************************** + * Name: vchi_connect + * + * Arguments: VCHI_CONNECTION_T **connections + * const uint32_t num_connections +- * VCHI_INSTANCE_T instance_handle) ++ * VCHI_INSTANCE_T instance_handle ) + * + * Description: Starts the command service on each connection, + * causing INIT messages to be pinged back and forth +@@ -477,18 +695,17 @@ + * Returns: 0 if successful, failure otherwise + * + ***********************************************************/ +-int32_t vchi_connect(VCHI_CONNECTION_T **connections, +- const uint32_t num_connections, +- VCHI_INSTANCE_T instance_handle) ++int32_t vchi_connect( VCHI_CONNECTION_T **connections, ++ const uint32_t num_connections, ++ VCHI_INSTANCE_T instance_handle ) + { +- VCHIQ_INSTANCE_T instance = (VCHIQ_INSTANCE_T)instance_handle; ++ VCHIQ_INSTANCE_T instance = (VCHIQ_INSTANCE_T)instance_handle; + +- (void)connections; +- (void)num_connections; ++ vcos_unused(connections); ++ vcos_unused(num_connections); + +- return vchiq_connect(instance); ++ return vchiq_connect(instance); + } +-EXPORT_SYMBOL(vchi_connect); + + + /*********************************************************** +@@ -502,12 +719,11 @@ + * Returns: 0 if successful, failure otherwise + * + ***********************************************************/ +-int32_t vchi_disconnect(VCHI_INSTANCE_T instance_handle) ++int32_t vchi_disconnect( VCHI_INSTANCE_T instance_handle ) + { +- VCHIQ_INSTANCE_T instance = (VCHIQ_INSTANCE_T)instance_handle; +- return vchiq_status_to_vchi(vchiq_shutdown(instance)); ++ VCHIQ_INSTANCE_T instance = (VCHIQ_INSTANCE_T)instance_handle; ++ return vchiq_status_to_vchi(vchiq_shutdown(instance)); + } +-EXPORT_SYMBOL(vchi_disconnect); + + + /*********************************************************** +@@ -524,188 +740,168 @@ + * + ***********************************************************/ + +-static VCHIQ_STATUS_T shim_callback(VCHIQ_REASON_T reason, +- VCHIQ_HEADER_T *header, VCHIQ_SERVICE_HANDLE_T handle, void *bulk_user) ++static VCHIQ_STATUS_T shim_callback(VCHIQ_REASON_T reason, VCHIQ_HEADER_T *header, VCHIQ_SERVICE_HANDLE_T handle, void *bulk_user) + { +- SHIM_SERVICE_T *service = +- (SHIM_SERVICE_T *)VCHIQ_GET_SERVICE_USERDATA(handle); ++ SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)VCHIQ_GET_SERVICE_USERDATA(handle); + +- switch (reason) { +- case VCHIQ_MESSAGE_AVAILABLE: +- vchiu_queue_push(&service->queue, header); +- +- if (service->callback) +- service->callback(service->callback_param, +- VCHI_CALLBACK_MSG_AVAILABLE, NULL); +- break; +- case VCHIQ_BULK_TRANSMIT_DONE: +- if (service->callback) +- service->callback(service->callback_param, +- VCHI_CALLBACK_BULK_SENT, bulk_user); +- break; +- case VCHIQ_BULK_RECEIVE_DONE: +- if (service->callback) +- service->callback(service->callback_param, +- VCHI_CALLBACK_BULK_RECEIVED, bulk_user); +- break; +- case VCHIQ_SERVICE_CLOSED: +- if (service->callback) +- service->callback(service->callback_param, +- VCHI_CALLBACK_SERVICE_CLOSED, NULL); +- break; +- case VCHIQ_SERVICE_OPENED: +- /* No equivalent VCHI reason */ +- break; +- case VCHIQ_BULK_TRANSMIT_ABORTED: +- if (service->callback) +- service->callback(service->callback_param, +- VCHI_CALLBACK_BULK_TRANSMIT_ABORTED, bulk_user); +- break; +- case VCHIQ_BULK_RECEIVE_ABORTED: +- if (service->callback) +- service->callback(service->callback_param, +- VCHI_CALLBACK_BULK_RECEIVE_ABORTED, bulk_user); +- break; +- default: +- WARN(1, "not supported\n"); +- break; +- } ++ switch (reason) { ++ case VCHIQ_MESSAGE_AVAILABLE: ++ vchiu_queue_push(&service->queue, header); ++ ++ if (service->callback) ++ service->callback(service->callback_param, VCHI_CALLBACK_MSG_AVAILABLE, NULL); ++ break; ++ case VCHIQ_BULK_TRANSMIT_DONE: ++ if (service->callback) ++ service->callback(service->callback_param, VCHI_CALLBACK_BULK_SENT, bulk_user); ++ break; ++ case VCHIQ_BULK_RECEIVE_DONE: ++ if (service->callback) ++ service->callback(service->callback_param, VCHI_CALLBACK_BULK_RECEIVED, bulk_user); ++ break; ++ case VCHIQ_SERVICE_CLOSED: ++ if (service->callback) ++ service->callback(service->callback_param, VCHI_CALLBACK_SERVICE_CLOSED, NULL); ++ break; ++ case VCHIQ_SERVICE_OPENED: ++ /* No equivalent VCHI reason */ ++ break; ++ case VCHIQ_BULK_TRANSMIT_ABORTED: ++ if (service->callback) ++ service->callback(service->callback_param, VCHI_CALLBACK_BULK_TRANSMIT_ABORTED, bulk_user); ++ break; ++ case VCHIQ_BULK_RECEIVE_ABORTED: ++ if (service->callback) ++ service->callback(service->callback_param, VCHI_CALLBACK_BULK_RECEIVE_ABORTED, bulk_user); ++ break; ++ default: ++ vcos_assert(0); ++ break; ++ } + +- return VCHIQ_SUCCESS; ++ return VCHIQ_SUCCESS; + } + + static SHIM_SERVICE_T *service_alloc(VCHIQ_INSTANCE_T instance, +- SERVICE_CREATION_T *setup) ++ SERVICE_CREATION_T *setup) + { +- SHIM_SERVICE_T *service = kzalloc(sizeof(SHIM_SERVICE_T), GFP_KERNEL); ++ SHIM_SERVICE_T *service = vcos_calloc(1, sizeof(SHIM_SERVICE_T), "vchiq_shim"); + +- (void)instance; ++ vcos_unused(instance); + +- if (service) { +- if (vchiu_queue_init(&service->queue, 64)) { +- service->callback = setup->callback; +- service->callback_param = setup->callback_param; +- } else { +- kfree(service); +- service = NULL; +- } +- } ++ if (service) ++ { ++ if (vchiu_queue_init(&service->queue, 64)) ++ { ++ service->callback = setup->callback; ++ service->callback_param = setup->callback_param; ++ } ++ else ++ { ++ vcos_free(service); ++ service = NULL; ++ } ++ } + +- return service; ++ return service; + } + + static void service_free(SHIM_SERVICE_T *service) + { +- if (service) { +- vchiu_queue_delete(&service->queue); +- kfree(service); +- } +-} +- +-int32_t vchi_service_open(VCHI_INSTANCE_T instance_handle, +- SERVICE_CREATION_T *setup, +- VCHI_SERVICE_HANDLE_T *handle) +-{ +- VCHIQ_INSTANCE_T instance = (VCHIQ_INSTANCE_T)instance_handle; +- SHIM_SERVICE_T *service = service_alloc(instance, setup); +- if (service) { +- VCHIQ_SERVICE_PARAMS_T params; +- VCHIQ_STATUS_T status; +- +- memset(¶ms, 0, sizeof(params)); +- params.fourcc = setup->service_id; +- params.callback = shim_callback; +- params.userdata = service; +- params.version = setup->version.version; +- params.version_min = setup->version.version_min; +- +- status = vchiq_open_service(instance, ¶ms, +- &service->handle); +- if (status != VCHIQ_SUCCESS) { +- service_free(service); +- service = NULL; +- } +- } +- +- *handle = (VCHI_SERVICE_HANDLE_T)service; +- +- return (service != NULL) ? 0 : -1; ++ if (service) ++ { ++ vchiu_queue_delete(&service->queue); ++ vcos_free((void*)service); ++ } ++} ++ ++int32_t vchi_service_open( VCHI_INSTANCE_T instance_handle, ++ SERVICE_CREATION_T *setup, ++ VCHI_SERVICE_HANDLE_T *handle) ++{ ++ VCHIQ_INSTANCE_T instance = (VCHIQ_INSTANCE_T)instance_handle; ++ SHIM_SERVICE_T *service = service_alloc(instance, setup); ++ if (service) ++ { ++ VCHIQ_STATUS_T status = vchiq_open_service(instance, setup->service_id, shim_callback, service, &service->handle); ++ if (status != VCHIQ_SUCCESS) ++ { ++ service_free(service); ++ service = NULL; ++ } ++ } ++ ++ *handle = (VCHI_SERVICE_HANDLE_T)service; ++ ++ return (service != NULL) ? 0 : -1; ++} ++ ++int32_t vchi_service_create( VCHI_INSTANCE_T instance_handle, ++ SERVICE_CREATION_T *setup, ++ VCHI_SERVICE_HANDLE_T *handle ) ++{ ++ VCHIQ_INSTANCE_T instance = (VCHIQ_INSTANCE_T)instance_handle; ++ SHIM_SERVICE_T *service = service_alloc(instance, setup); ++ if (service) ++ { ++ VCHIQ_STATUS_T status = vchiq_add_service(instance, setup->service_id, shim_callback, service, &service->handle); ++ if (status != VCHIQ_SUCCESS) ++ { ++ service_free(service); ++ service = NULL; ++ } ++ } ++ ++ *handle = (VCHI_SERVICE_HANDLE_T)service; ++ ++ return (service != NULL) ? 0 : -1; ++} ++ ++int32_t vchi_service_close( const VCHI_SERVICE_HANDLE_T handle ) ++{ ++ int32_t ret = -1; ++ SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle; ++ if(service) ++ { ++ VCHIQ_STATUS_T status = vchiq_close_service(service->handle); ++ if (status == VCHIQ_SUCCESS) ++ { ++ service_free(service); ++ service = NULL; ++ } ++ ++ ret = vchiq_status_to_vchi( status ); ++ } ++ return ret; ++} ++ ++int32_t vchi_service_destroy( const VCHI_SERVICE_HANDLE_T handle ) ++{ ++ int32_t ret = -1; ++ SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle; ++ if(service) ++ { ++ VCHIQ_STATUS_T status = vchiq_remove_service(service->handle); ++ if (status == VCHIQ_SUCCESS) ++ { ++ service_free(service); ++ service = NULL; ++ } ++ ++ ret = vchiq_status_to_vchi( status ); ++ } ++ return ret; + } +-EXPORT_SYMBOL(vchi_service_open); +- +-int32_t vchi_service_create(VCHI_INSTANCE_T instance_handle, +- SERVICE_CREATION_T *setup, +- VCHI_SERVICE_HANDLE_T *handle) +-{ +- VCHIQ_INSTANCE_T instance = (VCHIQ_INSTANCE_T)instance_handle; +- SHIM_SERVICE_T *service = service_alloc(instance, setup); +- if (service) { +- VCHIQ_SERVICE_PARAMS_T params; +- VCHIQ_STATUS_T status; +- +- memset(¶ms, 0, sizeof(params)); +- params.fourcc = setup->service_id; +- params.callback = shim_callback; +- params.userdata = service; +- params.version = setup->version.version; +- params.version_min = setup->version.version_min; +- status = vchiq_add_service(instance, ¶ms, &service->handle); +- +- if (status != VCHIQ_SUCCESS) { +- service_free(service); +- service = NULL; +- } +- } +- +- *handle = (VCHI_SERVICE_HANDLE_T)service; +- +- return (service != NULL) ? 0 : -1; +-} +-EXPORT_SYMBOL(vchi_service_create); +- +-int32_t vchi_service_close(const VCHI_SERVICE_HANDLE_T handle) +-{ +- int32_t ret = -1; +- SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle; +- if (service) { +- VCHIQ_STATUS_T status = vchiq_close_service(service->handle); +- if (status == VCHIQ_SUCCESS) { +- service_free(service); +- service = NULL; +- } +- +- ret = vchiq_status_to_vchi(status); +- } +- return ret; +-} +-EXPORT_SYMBOL(vchi_service_close); +- +-int32_t vchi_service_destroy(const VCHI_SERVICE_HANDLE_T handle) +-{ +- int32_t ret = -1; +- SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle; +- if (service) { +- VCHIQ_STATUS_T status = vchiq_remove_service(service->handle); +- if (status == VCHIQ_SUCCESS) { +- service_free(service); +- service = NULL; +- } +- +- ret = vchiq_status_to_vchi(status); +- } +- return ret; +-} +-EXPORT_SYMBOL(vchi_service_destroy); + + /* ---------------------------------------------------------------------- + * read a uint32_t from buffer. + * network format is defined to be little endian + * -------------------------------------------------------------------- */ + uint32_t +-vchi_readbuf_uint32(const void *_ptr) ++vchi_readbuf_uint32( const void *_ptr ) + { +- const unsigned char *ptr = _ptr; +- return ptr[0] | (ptr[1] << 8) | (ptr[2] << 16) | (ptr[3] << 24); ++ const unsigned char *ptr = _ptr; ++ return ptr[0] | (ptr[1] << 8) | (ptr[2] << 16) | (ptr[3] << 24); + } + + /* ---------------------------------------------------------------------- +@@ -713,13 +909,13 @@ + * network format is defined to be little endian + * -------------------------------------------------------------------- */ + void +-vchi_writebuf_uint32(void *_ptr, uint32_t value) ++vchi_writebuf_uint32( void *_ptr, uint32_t value ) + { +- unsigned char *ptr = _ptr; +- ptr[0] = (unsigned char)((value >> 0) & 0xFF); +- ptr[1] = (unsigned char)((value >> 8) & 0xFF); +- ptr[2] = (unsigned char)((value >> 16) & 0xFF); +- ptr[3] = (unsigned char)((value >> 24) & 0xFF); ++ unsigned char *ptr = _ptr; ++ ptr[0] = (unsigned char)((value >> 0) & 0xFF); ++ ptr[1] = (unsigned char)((value >> 8) & 0xFF); ++ ptr[2] = (unsigned char)((value >> 16) & 0xFF); ++ ptr[3] = (unsigned char)((value >> 24) & 0xFF); + } + + /* ---------------------------------------------------------------------- +@@ -727,10 +923,10 @@ + * network format is defined to be little endian + * -------------------------------------------------------------------- */ + uint16_t +-vchi_readbuf_uint16(const void *_ptr) ++vchi_readbuf_uint16( const void *_ptr ) + { +- const unsigned char *ptr = _ptr; +- return ptr[0] | (ptr[1] << 8); ++ const unsigned char *ptr = _ptr; ++ return ptr[0] | (ptr[1] << 8); + } + + /* ---------------------------------------------------------------------- +@@ -738,11 +934,11 @@ + * network format is defined to be little endian + * -------------------------------------------------------------------- */ + void +-vchi_writebuf_uint16(void *_ptr, uint16_t value) ++vchi_writebuf_uint16( void *_ptr, uint16_t value ) + { +- unsigned char *ptr = _ptr; +- ptr[0] = (value >> 0) & 0xFF; +- ptr[1] = (value >> 8) & 0xFF; ++ unsigned char *ptr = _ptr; ++ ptr[0] = (value >> 0) & 0xFF; ++ ptr[1] = (value >> 8) & 0xFF; + } + + /*********************************************************** +@@ -755,15 +951,16 @@ + * Returns: void + * + ***********************************************************/ +-int32_t vchi_service_use(const VCHI_SERVICE_HANDLE_T handle) ++int32_t vchi_service_use( const VCHI_SERVICE_HANDLE_T handle ) + { +- int32_t ret = -1; +- SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle; +- if (service) +- ret = vchiq_status_to_vchi(vchiq_use_service(service->handle)); +- return ret; ++ int32_t ret = -1; ++ SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle; ++ if(service) ++ { ++ ret = vchiq_status_to_vchi(vchiq_use_service(service->handle)); ++ } ++ return ret; + } +-EXPORT_SYMBOL(vchi_service_use); + + /*********************************************************** + * Name: vchi_service_release +@@ -775,13 +972,30 @@ + * Returns: void + * + ***********************************************************/ +-int32_t vchi_service_release(const VCHI_SERVICE_HANDLE_T handle) ++int32_t vchi_service_release( const VCHI_SERVICE_HANDLE_T handle ) + { +- int32_t ret = -1; +- SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle; +- if (service) +- ret = vchiq_status_to_vchi( +- vchiq_release_service(service->handle)); +- return ret; ++ int32_t ret = -1; ++ SHIM_SERVICE_T *service = (SHIM_SERVICE_T *)handle; ++ if(service) ++ { ++ ret = vchiq_status_to_vchi(vchiq_release_service(service->handle)); ++ } ++ return ret; + } ++ ++#if defined(__KERNEL__) ++EXPORT_SYMBOL(vchi_initialise); ++EXPORT_SYMBOL(vchi_connect); ++EXPORT_SYMBOL(vchi_bulk_queue_transmit); ++EXPORT_SYMBOL(vchi_msg_dequeue); ++EXPORT_SYMBOL(vchi_msg_queue); ++EXPORT_SYMBOL(vchi_msg_queuev); ++EXPORT_SYMBOL(vchi_msg_peek); ++EXPORT_SYMBOL(vchi_msg_remove); ++EXPORT_SYMBOL(vchi_service_close); ++EXPORT_SYMBOL(vchi_service_open); ++EXPORT_SYMBOL(vchi_service_create); ++EXPORT_SYMBOL(vchi_service_destroy); ++EXPORT_SYMBOL(vchi_service_use); + EXPORT_SYMBOL(vchi_service_release); ++#endif +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_util.c +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_util.c 2013-07-26 19:36:51.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_util.c 2013-07-26 19:37:11.000000000 +0000 +@@ -18,88 +18,80 @@ + + #include "vchiq_util.h" + +-static inline int is_pow2(int i) ++#if !defined(__KERNEL__) ++#include ++#endif ++ ++static __inline int is_pow2(int i) + { +- return i && !(i & (i - 1)); ++ return i && !(i & (i - 1)); + } + + int vchiu_queue_init(VCHIU_QUEUE_T *queue, int size) + { +- WARN_ON(!is_pow2(size)); ++ vcos_assert(is_pow2(size)); + +- queue->size = size; +- queue->read = 0; +- queue->write = 0; +- +- sema_init(&queue->pop, 0); +- sema_init(&queue->push, 0); +- +- queue->storage = kzalloc(size * sizeof(VCHIQ_HEADER_T *), GFP_KERNEL); +- if (queue->storage == NULL) { +- vchiu_queue_delete(queue); +- return 0; +- } +- return 1; ++ queue->size = size; ++ queue->read = 0; ++ queue->write = 0; ++ ++ vcos_event_create(&queue->pop, "vchiu"); ++ vcos_event_create(&queue->push, "vchiu"); ++ ++ queue->storage = vcos_malloc(size * sizeof(VCHIQ_HEADER_T *), VCOS_FUNCTION); ++ if (queue->storage == NULL) ++ { ++ vchiu_queue_delete(queue); ++ return 0; ++ } ++ return 1; + } + + void vchiu_queue_delete(VCHIU_QUEUE_T *queue) + { +- if (queue->storage != NULL) +- kfree(queue->storage); ++ vcos_event_delete(&queue->pop); ++ vcos_event_delete(&queue->push); ++ if (queue->storage != NULL) ++ vcos_free(queue->storage); + } + + int vchiu_queue_is_empty(VCHIU_QUEUE_T *queue) + { +- return queue->read == queue->write; +-} +- +-int vchiu_queue_is_full(VCHIU_QUEUE_T *queue) +-{ +- return queue->write == queue->read + queue->size; ++ return queue->read == queue->write; + } + + void vchiu_queue_push(VCHIU_QUEUE_T *queue, VCHIQ_HEADER_T *header) + { +- while (queue->write == queue->read + queue->size) { +- if (down_interruptible(&queue->pop) != 0) { +- flush_signals(current); +- } +- } ++ while (queue->write == queue->read + queue->size) ++ vcos_event_wait(&queue->pop); + +- queue->storage[queue->write & (queue->size - 1)] = header; ++ queue->storage[queue->write & (queue->size - 1)] = header; + +- queue->write++; ++ queue->write++; + +- up(&queue->push); ++ vcos_event_signal(&queue->push); + } + + VCHIQ_HEADER_T *vchiu_queue_peek(VCHIU_QUEUE_T *queue) + { +- while (queue->write == queue->read) { +- if (down_interruptible(&queue->push) != 0) { +- flush_signals(current); +- } +- } ++ while (queue->write == queue->read) ++ vcos_event_wait(&queue->push); + +- up(&queue->push); // We haven't removed anything from the queue. +- return queue->storage[queue->read & (queue->size - 1)]; ++ return queue->storage[queue->read & (queue->size - 1)]; + } + + VCHIQ_HEADER_T *vchiu_queue_pop(VCHIU_QUEUE_T *queue) + { +- VCHIQ_HEADER_T *header; ++ VCHIQ_HEADER_T *header; + +- while (queue->write == queue->read) { +- if (down_interruptible(&queue->push) != 0) { +- flush_signals(current); +- } +- } ++ while (queue->write == queue->read) ++ vcos_event_wait(&queue->push); + +- header = queue->storage[queue->read & (queue->size - 1)]; ++ header = queue->storage[queue->read & (queue->size - 1)]; + +- queue->read++; ++ queue->read++; + +- up(&queue->pop); ++ vcos_event_signal(&queue->pop); + +- return header; ++ return header; + } +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_util.h +=================================================================== +--- linux-3.2.46.orig/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_util.h 2013-07-26 19:36:51.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vchiq_arm/vchiq_util.h 2013-07-26 19:37:11.000000000 +0000 +@@ -19,44 +19,24 @@ + #ifndef VCHIQ_UTIL_H + #define VCHIQ_UTIL_H + +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include +-#include /* for time_t */ +-#include +-#include +- + #include "vchiq_if.h" ++#include "interface/vcos/vcos.h" + + typedef struct { +- int size; +- int read; +- int write; ++ int size; ++ int read; ++ int write; + +- struct semaphore pop; +- struct semaphore push; ++ VCOS_EVENT_T pop; ++ VCOS_EVENT_T push; + +- VCHIQ_HEADER_T **storage; ++ VCHIQ_HEADER_T **storage; + } VCHIU_QUEUE_T; + + extern int vchiu_queue_init(VCHIU_QUEUE_T *queue, int size); + extern void vchiu_queue_delete(VCHIU_QUEUE_T *queue); + + extern int vchiu_queue_is_empty(VCHIU_QUEUE_T *queue); +-extern int vchiu_queue_is_full(VCHIU_QUEUE_T *queue); + + extern void vchiu_queue_push(VCHIU_QUEUE_T *queue, VCHIQ_HEADER_T *header); + +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/generic/vcos_cmd.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/generic/vcos_cmd.c 2013-07-26 19:37:11.000000000 +0000 +@@ -0,0 +1,681 @@ ++/***************************************************************************** ++* Copyright 2009 - 2011 Broadcom Corporation. All rights reserved. ++* ++* Unless you and Broadcom execute a separate written software license ++* agreement governing use of this software, this software is licensed to you ++* under the terms of the GNU General Public License version 2, available at ++* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). ++* ++* Notwithstanding the above, under no circumstances may you combine this ++* software in any way with any other Broadcom software provided under a ++* license other than the GPL, without Broadcom's express prior written ++* consent. ++*****************************************************************************/ ++ ++/***************************************************************************** ++* ++* This file provides a generic command line interface which allows ++* vcos internals to be manipulated and/or displayed. ++* ++*****************************************************************************/ ++ ++/* ---- Include Files ---------------------------------------------------- */ ++ ++#include "interface/vcos/vcos.h" ++ ++#ifdef HAVE_VCOS_VERSION ++#include "interface/vcos/vcos_build_info.h" ++#endif ++ ++ #ifdef _VIDEOCORE ++#include vcfw/logging/logging.h ++#endif ++ ++/* ---- Public Variables ------------------------------------------------- */ ++ ++/* ---- Private Constants and Types -------------------------------------- */ ++ ++#define VCOS_LOG_CATEGORY (&vcos_cmd_log_category) ++VCOS_LOG_CAT_T vcos_cmd_log_category; ++ ++/* ---- Private Variables ------------------------------------------------ */ ++ ++static struct VCOS_CMD_GLOBALS_T ++{ ++ VCOS_MUTEX_T lock; ++ VCOS_ONCE_T initialized; ++ ++ unsigned num_cmd_entries; ++ unsigned num_cmd_alloc; ++ VCOS_CMD_T *cmd_entry; ++ ++ VCOS_LOG_CAT_T *log_category; ++} cmd_globals; ++ ++/* ---- Private Function Prototypes -------------------------------------- */ ++ ++static VCOS_STATUS_T help_cmd( VCOS_CMD_PARAM_T *param ); ++ ++/* ---- Functions ------------------------------------------------------- */ ++ ++/***************************************************************************** ++* ++* Walks through the commands looking for a particular command ++* ++*****************************************************************************/ ++ ++static VCOS_CMD_T *find_cmd( VCOS_CMD_T *cmd_entry, const char *name ) ++{ ++ VCOS_CMD_T *scan_entry = cmd_entry; ++ ++ while ( scan_entry->name != NULL ) ++ { ++ if ( vcos_strcmp( scan_entry->name, name ) == 0 ) ++ { ++ return scan_entry; ++ } ++ scan_entry++; ++ } ++ ++ return NULL; ++} ++ ++/***************************************************************************** ++* ++* Saves away ++* each line individually. ++* ++*****************************************************************************/ ++ ++void vcos_cmd_always_log_output( VCOS_LOG_CAT_T *log_category ) ++{ ++ cmd_globals.log_category = log_category; ++} ++ ++/***************************************************************************** ++* ++* Walks through a buffer containing newline separated lines, and logs ++* each line individually. ++* ++*****************************************************************************/ ++ ++static void cmd_log_results( VCOS_CMD_PARAM_T *param ) ++{ ++ char *start; ++ char *end; ++ ++ start = end = param->result_buf; ++ ++ while ( *start != '\0' ) ++ { ++ while (( *end != '\0' ) && ( *end != '\n' )) ++ end++; ++ ++ if ( *end == '\n' ) ++ { ++ *end++ = '\0'; ++ } ++ ++ if ( cmd_globals.log_category != NULL ) ++ { ++ if ( vcos_is_log_enabled( cmd_globals.log_category, VCOS_LOG_INFO )) ++ { ++ vcos_log_impl( cmd_globals.log_category, VCOS_LOG_INFO, "%s", start ); ++ } ++ } ++ else ++ { ++ vcos_log_info( "%s", start ); ++ } ++ ++ start = end; ++ } ++ ++ /* Since we logged the buffer, reset the pointer back to the beginning. */ ++ ++ param->result_ptr = param->result_buf; ++ param->result_buf[0] = '\0'; ++} ++ ++/***************************************************************************** ++* ++* Since we may have limited output space, we create a generic routine ++* which tries to use the result space, but will switch over to using ++* logging if the output is too large. ++* ++*****************************************************************************/ ++ ++void vcos_cmd_vprintf( VCOS_CMD_PARAM_T *param, const char *fmt, va_list args ) ++{ ++ int bytes_written; ++ int bytes_remaining; ++ ++ bytes_remaining = (int)(param->result_size - ( param->result_ptr - param->result_buf )); ++ ++ bytes_written = vcos_vsnprintf( param->result_ptr, bytes_remaining, fmt, args ); ++ ++ if ( cmd_globals.log_category != NULL ) ++ { ++ /* We're going to log each line as we encounter it. If the buffer ++ * doesn't end in a newline, then we'll wait for one first. ++ */ ++ ++ if ( (( bytes_written + 1 ) >= bytes_remaining ) ++ || ( param->result_ptr[ bytes_written - 1 ] == '\n' )) ++ { ++ cmd_log_results( param ); ++ } ++ else ++ { ++ param->result_ptr += bytes_written; ++ } ++ } ++ else ++ { ++ if (( bytes_written + 1 ) >= bytes_remaining ) ++ { ++ /* Output doesn't fit - switch over to logging */ ++ ++ param->use_log = 1; ++ ++ *param->result_ptr = '\0'; /* Zap the partial line that didn't fit above. */ ++ ++ cmd_log_results( param ); /* resets result_ptr */ ++ ++ bytes_written = vcos_vsnprintf( param->result_ptr, bytes_remaining, fmt, args ); ++ } ++ param->result_ptr += bytes_written; ++ } ++} ++ ++/***************************************************************************** ++* ++* Prints the output. ++* ++*****************************************************************************/ ++ ++void vcos_cmd_printf( VCOS_CMD_PARAM_T *param, const char *fmt, ... ) ++{ ++ va_list args; ++ ++ va_start( args, fmt ); ++ vcos_cmd_vprintf( param, fmt, args ); ++ va_end( args ); ++} ++ ++/***************************************************************************** ++* ++* Prints the arguments which were on the command line prior to ours. ++* ++*****************************************************************************/ ++ ++static void print_argument_prefix( VCOS_CMD_PARAM_T *param ) ++{ ++ int arg_idx; ++ ++ for ( arg_idx = 0; ¶m->argv_orig[arg_idx] != param->argv; arg_idx++ ) ++ { ++ vcos_cmd_printf( param, "%s ", param->argv_orig[arg_idx] ); ++ } ++} ++ ++/***************************************************************************** ++* ++* Prints an error message, prefixed by the command chain required to get ++* to where we're at. ++* ++*****************************************************************************/ ++ ++void vcos_cmd_error( VCOS_CMD_PARAM_T *param, const char *fmt, ... ) ++{ ++ va_list args; ++ ++ print_argument_prefix( param ); ++ ++ va_start( args, fmt ); ++ vcos_cmd_vprintf( param, fmt, args ); ++ va_end( args ); ++ vcos_cmd_printf( param, "\n" ); ++} ++ ++/**************************************************************************** ++* ++* usage - prints command usage for an array of commands. ++* ++***************************************************************************/ ++ ++static void usage( VCOS_CMD_PARAM_T *param, VCOS_CMD_T *cmd_entry ) ++{ ++ int cmd_idx; ++ int nameWidth = 0; ++ int argsWidth = 0; ++ VCOS_CMD_T *scan_entry; ++ ++ vcos_cmd_printf( param, "Usage: " ); ++ print_argument_prefix( param ); ++ vcos_cmd_printf( param, "command [args ...]\n" ); ++ vcos_cmd_printf( param, "\n" ); ++ vcos_cmd_printf( param, "Where command is one of the following:\n" ); ++ ++ for ( cmd_idx = 0; cmd_entry[cmd_idx].name != NULL; cmd_idx++ ) ++ { ++ int aw; ++ int nw; ++ ++ scan_entry = &cmd_entry[cmd_idx]; ++ ++ nw = vcos_strlen( scan_entry->name ); ++ aw = vcos_strlen( scan_entry->args ); ++ ++ if ( nw > nameWidth ) ++ { ++ nameWidth = nw; ++ } ++ if ( aw > argsWidth ) ++ { ++ argsWidth = aw; ++ } ++ } ++ ++ for ( cmd_idx = 0; cmd_entry[cmd_idx].name != NULL; cmd_idx++ ) ++ { ++ scan_entry = &cmd_entry[cmd_idx]; ++ ++ vcos_cmd_printf( param, " %-*s %-*s - %s\n", ++ nameWidth, scan_entry->name, ++ argsWidth, scan_entry->args, ++ scan_entry->descr ); ++ } ++} ++ ++/**************************************************************************** ++* ++* Prints the usage for the current command. ++* ++***************************************************************************/ ++ ++void vcos_cmd_usage( VCOS_CMD_PARAM_T *param ) ++{ ++ VCOS_CMD_T *cmd_entry; ++ ++ cmd_entry = param->cmd_entry; ++ ++ if ( cmd_entry->sub_cmd_entry != NULL ) ++ { ++ /* This command is command with sub-commands */ ++ ++ usage( param, param->cmd_entry->sub_cmd_entry ); ++ } ++ else ++ { ++ vcos_cmd_printf( param, "Usage: " ); ++ print_argument_prefix( param ); ++ vcos_cmd_printf( param, "%s - %s\n", ++ param->cmd_entry->args, ++ param->cmd_entry->descr ); ++ } ++} ++ ++/***************************************************************************** ++* ++* Command to print out the help ++* ++* This help command is only called from the main menu. ++* ++*****************************************************************************/ ++ ++static VCOS_STATUS_T help_cmd( VCOS_CMD_PARAM_T *param ) ++{ ++ VCOS_CMD_T *found_entry; ++ ++#if 0 ++ { ++ int arg_idx; ++ ++ vcos_log_trace( "%s: argc = %d", __func__, param->argc ); ++ for ( arg_idx = 0; arg_idx < param->argc; arg_idx++ ) ++ { ++ vcos_log_trace( "%s: argv[%d] = '%s'", __func__, arg_idx, param->argv[arg_idx] ); ++ } ++ } ++#endif ++ ++ /* If there is an argument after the word help, then we want to print ++ * help for that command. ++ */ ++ ++ if ( param->argc == 1 ) ++ { ++ if ( param->cmd_parent_entry == cmd_globals.cmd_entry ) ++ { ++ /* Bare help - print the command usage for the root */ ++ ++ usage( param, cmd_globals.cmd_entry ); ++ return VCOS_SUCCESS; ++ } ++ ++ /* For all other cases help requires an argument */ ++ ++ vcos_cmd_error( param, "%s requires an argument", param->argv[0] ); ++ return VCOS_EINVAL; ++ } ++ ++ /* We were given an argument. */ ++ ++ if (( found_entry = find_cmd( param->cmd_parent_entry, param->argv[1] )) != NULL ) ++ { ++ /* Make it look like the command that was specified is the one that's ++ * currently running ++ */ ++ ++ param->cmd_entry = found_entry; ++ param->argv[0] = param->argv[1]; ++ param->argv++; ++ param->argc--; ++ ++ vcos_cmd_usage( param ); ++ return VCOS_SUCCESS; ++ } ++ ++ vcos_cmd_error( param, "- unrecognized command: '%s'", param->argv[1] ); ++ return VCOS_ENOENT; ++} ++ ++/***************************************************************************** ++* ++* Command to print out the version/build information. ++* ++*****************************************************************************/ ++ ++#ifdef HAVE_VCOS_VERSION ++ ++static VCOS_STATUS_T version_cmd( VCOS_CMD_PARAM_T *param ) ++{ ++ static const char* copyright = "Copyright (c) 2011 Broadcom"; ++ ++ vcos_cmd_printf( param, "%s %s\n%s\nversion %s\n", ++ vcos_get_build_date(), ++ vcos_get_build_time(), ++ copyright, ++ vcos_get_build_version() ); ++ ++ return VCOS_SUCCESS; ++} ++ ++#endif ++ ++/***************************************************************************** ++* ++* Internal commands ++* ++*****************************************************************************/ ++ ++static VCOS_CMD_T cmd_help = { "help", "[command]", help_cmd, NULL, "Prints command help information" }; ++ ++#ifdef HAVE_VCOS_VERSION ++static VCOS_CMD_T cmd_version = { "version", "", version_cmd, NULL, "Prints build/version information" }; ++#endif ++ ++/***************************************************************************** ++* ++* Walks the command table and executes the commands ++* ++*****************************************************************************/ ++ ++static VCOS_STATUS_T execute_cmd( VCOS_CMD_PARAM_T *param, VCOS_CMD_T *cmd_entry ) ++{ ++ const char *cmdStr; ++ VCOS_CMD_T *found_entry; ++ ++#if 0 ++ { ++ int arg_idx; ++ ++ vcos_cmd_printf( param, "%s: argc = %d", __func__, param->argc ); ++ for ( arg_idx = 0; arg_idx < param->argc; arg_idx++ ) ++ { ++ vcos_cmd_printf( param, " argv[%d] = '%s'", arg_idx, param->argv[arg_idx] ); ++ } ++ vcos_cmd_printf( param, "\n" ); ++ } ++#endif ++ ++ if ( param->argc <= 1 ) ++ { ++ /* No command specified */ ++ ++ vcos_cmd_error( param, "%s - no command specified", param->argv[0] ); ++ return VCOS_EINVAL; ++ } ++ ++ /* argv[0] is the command/program that caused us to get invoked, so we strip ++ * it off. ++ */ ++ ++ param->argc--; ++ param->argv++; ++ param->cmd_parent_entry = cmd_entry; ++ ++ /* Not the help command, scan for the command and execute it. */ ++ ++ cmdStr = param->argv[0]; ++ ++ if (( found_entry = find_cmd( cmd_entry, cmdStr )) != NULL ) ++ { ++ if ( found_entry->sub_cmd_entry != NULL ) ++ { ++ return execute_cmd( param, found_entry->sub_cmd_entry ); ++ } ++ ++ param->cmd_entry = found_entry; ++ return found_entry->cmd_fn( param ); ++ } ++ ++ /* Unrecognized command - check to see if it was the help command */ ++ ++ if ( vcos_strcmp( cmdStr, cmd_help.name ) == 0 ) ++ { ++ return help_cmd( param ); ++ } ++ ++ vcos_cmd_error( param, "- unrecognized command: '%s'", cmdStr ); ++ return VCOS_ENOENT; ++} ++ ++/***************************************************************************** ++* ++* Initializes the command line parser. ++* ++*****************************************************************************/ ++ ++static void vcos_cmd_init( void ) ++{ ++ vcos_mutex_create( &cmd_globals.lock, "vcos_cmd" ); ++ ++ cmd_globals.num_cmd_entries = 0; ++ cmd_globals.num_cmd_alloc = 0; ++ cmd_globals.cmd_entry = NULL; ++} ++ ++/***************************************************************************** ++* ++* Command line processor. ++* ++*****************************************************************************/ ++ ++VCOS_STATUS_T vcos_cmd_execute( int argc, char **argv, size_t result_size, char *result_buf ) ++{ ++ VCOS_STATUS_T rc = VCOS_EINVAL; ++ VCOS_CMD_PARAM_T param; ++ ++ vcos_once( &cmd_globals.initialized, vcos_cmd_init ); ++ ++ param.argc = argc; ++ param.argv = param.argv_orig = argv; ++ ++ param.use_log = 0; ++ param.result_size = result_size; ++ param.result_ptr = result_buf; ++ param.result_buf = result_buf; ++ ++ result_buf[0] = '\0'; ++ ++ vcos_mutex_lock( &cmd_globals.lock ); ++ ++ rc = execute_cmd( ¶m, cmd_globals.cmd_entry ); ++ ++ if ( param.use_log ) ++ { ++ cmd_log_results( ¶m ); ++ vcos_snprintf( result_buf, result_size, "results logged" ); ++ } ++ else ++ if ( cmd_globals.log_category != NULL ) ++ { ++ if ( result_buf[0] != '\0' ) ++ { ++ /* There is a partial line still buffered. */ ++ ++ vcos_cmd_printf( ¶m, "\n" ); ++ } ++ } ++ ++ vcos_mutex_unlock( &cmd_globals.lock ); ++ ++ return rc; ++} ++ ++/***************************************************************************** ++* ++* Registers a command entry with the command line processor ++* ++*****************************************************************************/ ++ ++VCOS_STATUS_T vcos_cmd_register( VCOS_CMD_T *cmd_entry ) ++{ ++ VCOS_STATUS_T rc; ++ VCOS_UNSIGNED new_num_cmd_alloc; ++ VCOS_CMD_T *new_cmd_entry; ++ VCOS_CMD_T *old_cmd_entry; ++ VCOS_CMD_T *scan_entry; ++ ++ vcos_once( &cmd_globals.initialized, vcos_cmd_init ); ++ ++ vcos_assert( cmd_entry != NULL ); ++ vcos_assert( cmd_entry->name != NULL ); ++ ++ vcos_log_trace( "%s: cmd '%s'", __FUNCTION__, cmd_entry->name ); ++ ++ vcos_assert( cmd_entry->args != NULL ); ++ vcos_assert(( cmd_entry->cmd_fn != NULL ) || ( cmd_entry->sub_cmd_entry != NULL )); ++ vcos_assert( cmd_entry->descr != NULL ); ++ ++ /* We expect vcos_cmd_init to be called before vcos_logging_init, so we ++ * need to defer registering our logging category until someplace ++ * like right here. ++ */ ++ ++ if ( vcos_cmd_log_category.name == NULL ) ++ { ++ /* ++ * If you're using the command interface, you pretty much always want ++ * log messages from this file to show up. So we change the default ++ * from ERROR to be the more reasonable INFO level. ++ */ ++ ++ vcos_log_set_level(&vcos_cmd_log_category, VCOS_LOG_INFO); ++ vcos_log_register("vcos_cmd", &vcos_cmd_log_category); ++ ++ /* We register a help command so that it shows up in the usage. */ ++ ++ vcos_cmd_register( &cmd_help ); ++#ifdef HAVE_VCOS_VERSION ++ vcos_cmd_register( &cmd_version ); ++#endif ++ } ++ ++ vcos_mutex_lock( &cmd_globals.lock ); ++ ++ if ( cmd_globals.num_cmd_entries >= cmd_globals.num_cmd_alloc ) ++ { ++ if ( cmd_globals.num_cmd_alloc == 0 ) ++ { ++ /* We haven't allocated a table yet */ ++ } ++ ++ /* The number 8 is rather arbitrary. */ ++ ++ new_num_cmd_alloc = cmd_globals.num_cmd_alloc + 8; ++ ++ /* The + 1 is to ensure that we always have a NULL entry at the end. */ ++ ++ new_cmd_entry = (VCOS_CMD_T *)vcos_calloc( new_num_cmd_alloc + 1, sizeof( *cmd_entry ), "vcos_cmd_entries" ); ++ if ( new_cmd_entry == NULL ) ++ { ++ rc = VCOS_ENOMEM; ++ goto out; ++ } ++ memcpy( new_cmd_entry, cmd_globals.cmd_entry, cmd_globals.num_cmd_entries * sizeof( *cmd_entry )); ++ cmd_globals.num_cmd_alloc = new_num_cmd_alloc; ++ old_cmd_entry = cmd_globals.cmd_entry; ++ cmd_globals.cmd_entry = new_cmd_entry; ++ vcos_free( old_cmd_entry ); ++ } ++ ++ if ( cmd_globals.num_cmd_entries == 0 ) ++ { ++ /* This is the first command being registered */ ++ ++ cmd_globals.cmd_entry[0] = *cmd_entry; ++ } ++ else ++ { ++ /* Keep the list in alphabetical order. We start at the end and work backwards ++ * shuffling entries up one until we find an insertion point. ++ */ ++ ++ for ( scan_entry = &cmd_globals.cmd_entry[cmd_globals.num_cmd_entries - 1]; ++ scan_entry >= cmd_globals.cmd_entry; scan_entry-- ) ++ { ++ if ( vcos_strcmp( cmd_entry->name, scan_entry->name ) > 0 ) ++ { ++ /* We found an insertion point. */ ++ ++ break; ++ } ++ ++ scan_entry[1] = scan_entry[0]; ++ } ++ scan_entry[1] = *cmd_entry; ++ } ++ cmd_globals.num_cmd_entries++; ++ ++ rc = VCOS_SUCCESS; ++ ++out: ++ ++ vcos_mutex_unlock( &cmd_globals.lock ); ++ return rc; ++} ++ ++/***************************************************************************** ++* ++* Registers multiple commands. ++* ++*****************************************************************************/ ++ ++VCOS_STATUS_T vcos_cmd_register_multiple( VCOS_CMD_T *cmd_entry ) ++{ ++ VCOS_STATUS_T status; ++ ++ while ( cmd_entry->name != NULL ) ++ { ++ if (( status = vcos_cmd_register( cmd_entry )) != VCOS_SUCCESS ) ++ { ++ return status; ++ } ++ cmd_entry++; ++ } ++ return VCOS_SUCCESS; ++} ++ +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/generic/vcos_common.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/generic/vcos_common.h 2013-07-26 19:37:11.000000000 +0000 +@@ -0,0 +1,87 @@ ++/* ++ * Copyright (c) 2010-2011 Broadcom. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++/*============================================================================= ++VideoCore OS Abstraction Layer - common postamble code ++=============================================================================*/ ++ ++/** \file ++ * ++ * Postamble code included by the platform-specific header files ++ */ ++ ++#define VCOS_THREAD_PRI_DEFAULT VCOS_THREAD_PRI_NORMAL ++ ++#if !defined(VCOS_THREAD_PRI_INCREASE) ++#error Which way to thread priorities go? ++#endif ++ ++#if VCOS_THREAD_PRI_INCREASE < 0 ++/* smaller numbers are higher priority */ ++#define VCOS_THREAD_PRI_LESS(x) ((x)VCOS_THREAD_PRI_MIN?(x)-1:VCOS_THREAD_PRI_MIN) ++#else ++/* bigger numbers are lower priority */ ++#define VCOS_THREAD_PRI_MORE(x) ((x)VCOS_THREAD_PRI_MIN?(x)-1:VCOS_THREAD_PRI_MIN) ++#endif ++ ++/* Convenience for Brits: */ ++#define VCOS_APPLICATION_INITIALISE VCOS_APPLICATION_INITIALIZE ++ ++/* ++ * Check for constant definitions ++ */ ++#ifndef VCOS_TICKS_PER_SECOND ++#error VCOS_TICKS_PER_SECOND not defined ++#endif ++ ++#if !defined(VCOS_THREAD_PRI_MIN) || !defined(VCOS_THREAD_PRI_MAX) ++#error Priority range not defined ++#endif ++ ++#if !defined(VCOS_THREAD_PRI_HIGHEST) || !defined(VCOS_THREAD_PRI_LOWEST) || !defined(VCOS_THREAD_PRI_NORMAL) ++#error Priority ordering not defined ++#endif ++ ++#if !defined(VCOS_CAN_SET_STACK_ADDR) ++#error Can stack addresses be set on this platform? Please set this macro to either 0 or 1. ++#endif ++ ++#if (_VCOS_AFFINITY_CPU0|_VCOS_AFFINITY_CPU1) & (~_VCOS_AFFINITY_MASK) ++#error _VCOS_AFFINITY_CPUxxx values are not consistent with _VCOS_AFFINITY_MASK ++#endif ++ ++/** Append to the end of a singly-linked queue, O(1). Works with ++ * any structure where list has members 'head' and 'tail' and ++ * item has a 'next' pointer. ++ */ ++#define VCOS_QUEUE_APPEND_TAIL(list, item) {\ ++ (item)->next = NULL;\ ++ if (!(list)->head) {\ ++ (list)->head = (list)->tail = (item); \ ++ } else {\ ++ (list)->tail->next = (item); \ ++ (list)->tail = (item); \ ++ } \ ++} ++ ++#ifndef VCOS_HAVE_TIMER ++VCOSPRE_ void VCOSPOST_ vcos_timer_init(void); ++#endif ++ +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/generic/vcos_generic_blockpool.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/generic/vcos_generic_blockpool.h 2013-07-26 19:37:11.000000000 +0000 +@@ -0,0 +1,271 @@ ++/* ++ * Copyright (c) 2010-2011 Broadcom. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++/*============================================================================= ++VideoCore OS Abstraction Layer - event flags implemented via a semaphore ++=============================================================================*/ ++ ++#ifndef VCOS_GENERIC_BLOCKPOOL_H ++#define VCOS_GENERIC_BLOCKPOOL_H ++ ++/** ++ * \file ++ * ++ * This provides a generic, thread safe implementation of a VCOS block pool ++ * fixed size memory allocator. ++ */ ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++#include "interface/vcos/vcos_types.h" ++ ++/** Bits 0 to (VCOS_BLOCKPOOL_SUBPOOL_BITS - 1) are used to store the ++ * subpool id. */ ++#define VCOS_BLOCKPOOL_SUBPOOL_BITS 3 ++#define VCOS_BLOCKPOOL_MAX_SUBPOOLS (1 << VCOS_BLOCKPOOL_SUBPOOL_BITS) ++ ++/* Make zero an invalid handle at the cost of decreasing the maximum ++ * number of blocks (2^28) by 1. Alternatively, a spare bit could be ++ * used to indicated valid blocks but there are likely to be better ++ * uses for spare bits. e.g. allowing more subpools ++ */ ++#define INDEX_OFFSET 1 ++ ++#define VCOS_BLOCKPOOL_HANDLE_GET_INDEX(h) \ ++ (((h) >> VCOS_BLOCKPOOL_SUBPOOL_BITS) - INDEX_OFFSET) ++ ++#define VCOS_BLOCKPOOL_HANDLE_GET_SUBPOOL(h) \ ++ ((h) & ((1 << VCOS_BLOCKPOOL_SUBPOOL_BITS) - 1)) ++ ++#define VCOS_BLOCKPOOL_HANDLE_CREATE(i,s) \ ++ ((((i) + INDEX_OFFSET) << VCOS_BLOCKPOOL_SUBPOOL_BITS) | (s)) ++ ++#define VCOS_BLOCKPOOL_INVALID_HANDLE 0 ++ ++typedef struct VCOS_BLOCKPOOL_HEADER_TAG ++{ ++ /* Blocks either refer to to the pool if they are allocated ++ * or the free list if they are available. ++ */ ++ union { ++ struct VCOS_BLOCKPOOL_HEADER_TAG *next; ++ struct VCOS_BLOCKPOOL_SUBPOOL_TAG* subpool; ++ } owner; ++} VCOS_BLOCKPOOL_HEADER_T; ++ ++typedef struct VCOS_BLOCKPOOL_SUBPOOL_TAG ++{ ++ /** VCOS_BLOCKPOOL_SUBPOOL_MAGIC */ ++ uint32_t magic; ++ VCOS_BLOCKPOOL_HEADER_T* free_list; ++ /* The start of the pool memory */ ++ void *mem; ++ /* Address of the first block header */ ++ void *start; ++ /** The number of blocks in this sub-pool */ ++ VCOS_UNSIGNED num_blocks; ++ /** Current number of available blocks in this sub-pool */ ++ VCOS_UNSIGNED available_blocks; ++ /** Pointers to the pool that owns this sub-pool */ ++ struct VCOS_BLOCKPOOL_TAG* owner; ++ /** Define properties such as memory ownership */ ++ uint32_t flags; ++} VCOS_BLOCKPOOL_SUBPOOL_T; ++ ++typedef struct VCOS_BLOCKPOOL_TAG ++{ ++ /** VCOS_BLOCKPOOL_MAGIC */ ++ uint32_t magic; ++ /** Thread safety for Alloc, Free, Delete, Stats */ ++ VCOS_MUTEX_T mutex; ++ /** The size of the block data */ ++ size_t block_data_size; ++ /** Block size inc overheads */ ++ size_t block_size; ++ /** Name for debugging */ ++ const char *name; ++ /* The number of subpools that may be used */ ++ VCOS_UNSIGNED num_subpools; ++ /** Number of blocks in each dynamically allocated subpool */ ++ VCOS_UNSIGNED num_extension_blocks; ++ /** Array of subpools. Subpool zero is is not deleted until the pool is ++ * destroed. If the index of the pool is < num_subpools and ++ * subpool[index.mem] is null then the subpool entry is valid but ++ * "not currently allocated" */ ++ VCOS_BLOCKPOOL_SUBPOOL_T subpools[VCOS_BLOCKPOOL_MAX_SUBPOOLS]; ++} VCOS_BLOCKPOOL_T; ++ ++#define VCOS_BLOCKPOOL_ROUND_UP(x,s) (((x) + ((s) - 1)) & ~((s) - 1)) ++/** ++ * Calculates the size in bytes required for a block pool containing ++ * num_blocks of size block_size plus any overheads. ++ * ++ * The block pool header (VCOS_BLOCKPOOL_T) is allocated separately ++ * ++ * Overheads: ++ * block_size + header must be a multiple of sizeof(void*) ++ * The start of the first block may need to be up to wordsize - 1 bytes ++ * into the given buffer because statically allocated buffers within structures ++ * are not guaranteed to be word aligned. ++ */ ++#define VCOS_BLOCKPOOL_SIZE(num_blocks, block_size) \ ++ ((VCOS_BLOCKPOOL_ROUND_UP((block_size) + sizeof(VCOS_BLOCKPOOL_HEADER_T), \ ++ sizeof(void*)) * (num_blocks)) + sizeof(void*)) ++ ++/** ++ * Sanity check to verify whether a handle is potentially a blockpool handle ++ * when the pool pointer is not available. ++ * ++ * If the pool pointer is availabe use vcos_blockpool_elem_to_handle instead. ++ * ++ * @param handle the handle to verify ++ * @param max_blocks the expected maximum number of block in the pool ++ * that the handle belongs to. ++ */ ++#define VCOS_BLOCKPOOL_IS_VALID_HANDLE_FORMAT(handle, max_blocks) \ ++ ((handle) != VCOS_BLOCKPOOL_INVALID_HANDLE \ ++ && VCOS_BLOCKPOOL_HANDLE_GET_INDEX((handle)) < (max_blocks)) ++ ++VCOSPRE_ ++ VCOS_STATUS_T VCOSPOST_ vcos_generic_blockpool_init(VCOS_BLOCKPOOL_T *pool, ++ VCOS_UNSIGNED num_blocks, VCOS_UNSIGNED block_size, ++ void *start, VCOS_UNSIGNED pool_size, const char *name); ++ ++VCOSPRE_ ++ VCOS_STATUS_T VCOSPOST_ vcos_generic_blockpool_create_on_heap( ++ VCOS_BLOCKPOOL_T *pool, VCOS_UNSIGNED num_blocks, ++ VCOS_UNSIGNED block_size, const char *name); ++ ++VCOSPRE_ ++ VCOS_STATUS_T VCOSPOST_ vcos_generic_blockpool_extend(VCOS_BLOCKPOOL_T *pool, ++ VCOS_UNSIGNED num_extensions, VCOS_UNSIGNED num_blocks); ++ ++VCOSPRE_ void VCOSPOST_ *vcos_generic_blockpool_alloc(VCOS_BLOCKPOOL_T *pool); ++ ++VCOSPRE_ void VCOSPOST_ *vcos_generic_blockpool_calloc(VCOS_BLOCKPOOL_T *pool); ++ ++VCOSPRE_ void VCOSPOST_ vcos_generic_blockpool_free(void *block); ++ ++VCOSPRE_ ++ VCOS_UNSIGNED VCOSPOST_ vcos_generic_blockpool_available_count( ++ VCOS_BLOCKPOOL_T *pool); ++ ++VCOSPRE_ ++ VCOS_UNSIGNED VCOSPOST_ vcos_generic_blockpool_used_count( ++ VCOS_BLOCKPOOL_T *pool); ++ ++VCOSPRE_ void VCOSPOST_ vcos_generic_blockpool_delete(VCOS_BLOCKPOOL_T *pool); ++ ++VCOSPRE_ uint32_t VCOSPOST_ vcos_generic_blockpool_elem_to_handle(void *block); ++ ++VCOSPRE_ void VCOSPOST_ ++ *vcos_generic_blockpool_elem_from_handle( ++ VCOS_BLOCKPOOL_T *pool, uint32_t handle); ++ ++VCOSPRE_ uint32_t VCOSPOST_ ++ vcos_generic_blockpool_is_valid_elem( ++ VCOS_BLOCKPOOL_T *pool, const void *block); ++#if defined(VCOS_INLINE_BODIES) ++ ++VCOS_INLINE_IMPL ++VCOS_STATUS_T vcos_blockpool_init(VCOS_BLOCKPOOL_T *pool, ++ VCOS_UNSIGNED num_blocks, VCOS_UNSIGNED block_size, ++ void *start, VCOS_UNSIGNED pool_size, const char *name) ++{ ++ return vcos_generic_blockpool_init(pool, num_blocks, block_size, ++ start, pool_size, name); ++} ++ ++VCOS_INLINE_IMPL ++VCOS_STATUS_T vcos_blockpool_create_on_heap(VCOS_BLOCKPOOL_T *pool, ++ VCOS_UNSIGNED num_blocks, VCOS_UNSIGNED block_size, const char *name) ++{ ++ return vcos_generic_blockpool_create_on_heap( ++ pool, num_blocks, block_size, name); ++} ++ ++VCOS_INLINE_IMPL ++ VCOS_STATUS_T VCOSPOST_ vcos_blockpool_extend(VCOS_BLOCKPOOL_T *pool, ++ VCOS_UNSIGNED num_extensions, VCOS_UNSIGNED num_blocks) ++{ ++ return vcos_generic_blockpool_extend(pool, num_extensions, num_blocks); ++} ++ ++VCOS_INLINE_IMPL ++void *vcos_blockpool_alloc(VCOS_BLOCKPOOL_T *pool) ++{ ++ return vcos_generic_blockpool_alloc(pool); ++} ++ ++VCOS_INLINE_IMPL ++void *vcos_blockpool_calloc(VCOS_BLOCKPOOL_T *pool) ++{ ++ return vcos_generic_blockpool_calloc(pool); ++} ++ ++VCOS_INLINE_IMPL ++void vcos_blockpool_free(void *block) ++{ ++ vcos_generic_blockpool_free(block); ++} ++ ++VCOS_INLINE_IMPL ++VCOS_UNSIGNED vcos_blockpool_available_count(VCOS_BLOCKPOOL_T *pool) ++{ ++ return vcos_generic_blockpool_available_count(pool); ++} ++ ++VCOS_INLINE_IMPL ++VCOS_UNSIGNED vcos_blockpool_used_count(VCOS_BLOCKPOOL_T *pool) ++{ ++ return vcos_generic_blockpool_used_count(pool); ++} ++ ++VCOS_INLINE_IMPL ++void vcos_blockpool_delete(VCOS_BLOCKPOOL_T *pool) ++{ ++ vcos_generic_blockpool_delete(pool); ++} ++ ++VCOS_INLINE_IMPL ++uint32_t vcos_blockpool_elem_to_handle(void *block) ++{ ++ return vcos_generic_blockpool_elem_to_handle(block); ++} ++ ++VCOS_INLINE_IMPL ++void *vcos_blockpool_elem_from_handle(VCOS_BLOCKPOOL_T *pool, uint32_t handle) ++{ ++ return vcos_generic_blockpool_elem_from_handle(pool, handle); ++} ++ ++VCOS_INLINE_IMPL ++uint32_t vcos_blockpool_is_valid_elem(VCOS_BLOCKPOOL_T *pool, const void *block) ++{ ++ return vcos_generic_blockpool_is_valid_elem(pool, block); ++} ++#endif /* VCOS_INLINE_BODIES */ ++ ++ ++#ifdef __cplusplus ++} ++#endif ++#endif /* VCOS_GENERIC_BLOCKPOOL_H */ ++ +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/generic/vcos_generic_event_flags.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/generic/vcos_generic_event_flags.c 2013-07-26 19:37:11.000000000 +0000 +@@ -0,0 +1,311 @@ ++/* ++ * Copyright (c) 2010-2011 Broadcom. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++/*============================================================================= ++VideoCore OS Abstraction Layer - event flags implemented via mutexes ++=============================================================================*/ ++ ++#include "interface/vcos/vcos.h" ++#include "interface/vcos/generic/vcos_generic_event_flags.h" ++ ++#include ++ ++/** A structure created by a thread that waits on the event flags ++ * for a particular combination of flags to arrive. ++ */ ++typedef struct VCOS_EVENT_WAITER_T ++{ ++ VCOS_UNSIGNED requested_events; /**< The events wanted */ ++ VCOS_UNSIGNED actual_events; /**< Actual events found */ ++ VCOS_UNSIGNED op; /**< The event operation to be used */ ++ VCOS_STATUS_T return_status; /**< The return status the waiter should pass back */ ++ VCOS_EVENT_FLAGS_T *flags; /**< Pointer to the original 'flags' structure */ ++ VCOS_THREAD_T *thread; /**< Thread waiting */ ++ struct VCOS_EVENT_WAITER_T *next; ++} VCOS_EVENT_WAITER_T; ++ ++#ifndef NDEBUG ++static int waiter_list_valid(VCOS_EVENT_FLAGS_T *flags); ++#endif ++static void event_flags_timer_expired(void *cxt); ++ ++VCOS_STATUS_T vcos_generic_event_flags_create(VCOS_EVENT_FLAGS_T *flags, const char *name) ++{ ++ VCOS_STATUS_T rc; ++ if ((rc=vcos_mutex_create(&flags->lock, name)) != VCOS_SUCCESS) ++ { ++ return rc; ++ } ++ ++ flags->events = 0; ++ flags->waiters.head = flags->waiters.tail = 0; ++ return rc; ++} ++ ++void vcos_generic_event_flags_set(VCOS_EVENT_FLAGS_T *flags, ++ VCOS_UNSIGNED bitmask, ++ VCOS_OPTION op) ++{ ++ vcos_assert(flags); ++ vcos_mutex_lock(&flags->lock); ++ if (op == VCOS_OR) ++ { ++ flags->events |= bitmask; ++ } ++ else if (op == VCOS_AND) ++ { ++ flags->events &= bitmask; ++ } ++ else ++ { ++ vcos_assert(0); ++ } ++ ++ /* Now wake up any threads that have now become signalled. */ ++ if (flags->waiters.head != NULL) ++ { ++ VCOS_UNSIGNED consumed_events = 0; ++ VCOS_EVENT_WAITER_T **pcurrent_waiter = &flags->waiters.head; ++ VCOS_EVENT_WAITER_T *prev_waiter = NULL; ++ ++ /* Walk the chain of tasks suspend on this event flag group to determine ++ * if any of their requests can be satisfied. ++ */ ++ while ((*pcurrent_waiter) != NULL) ++ { ++ VCOS_EVENT_WAITER_T *curr_waiter = *pcurrent_waiter; ++ ++ /* Determine if this request has been satisfied */ ++ ++ /* First, find the event flags in common. */ ++ VCOS_UNSIGNED waiter_satisfied = flags->events & curr_waiter->requested_events; ++ ++ /* Second, determine if all the event flags must match */ ++ if (curr_waiter->op & VCOS_AND) ++ { ++ /* All requested events must be present */ ++ waiter_satisfied = (waiter_satisfied == curr_waiter->requested_events); ++ } ++ ++ /* Wake this one up? */ ++ if (waiter_satisfied) ++ { ++ ++ if (curr_waiter->op & VCOS_CONSUME) ++ { ++ consumed_events |= curr_waiter->requested_events; ++ } ++ ++ /* remove this block from the list, taking care at the end */ ++ *pcurrent_waiter = curr_waiter->next; ++ if (curr_waiter->next == NULL) ++ flags->waiters.tail = prev_waiter; ++ ++ vcos_assert(waiter_list_valid(flags)); ++ ++ curr_waiter->return_status = VCOS_SUCCESS; ++ curr_waiter->actual_events = flags->events; ++ ++ _vcos_thread_sem_post(curr_waiter->thread); ++ } ++ else ++ { ++ /* move to next element in the list */ ++ prev_waiter = *pcurrent_waiter; ++ pcurrent_waiter = &(curr_waiter->next); ++ } ++ } ++ ++ flags->events &= ~consumed_events; ++ ++ } ++ ++ vcos_mutex_unlock(&flags->lock); ++} ++ ++void vcos_generic_event_flags_delete(VCOS_EVENT_FLAGS_T *flags) ++{ ++ vcos_mutex_delete(&flags->lock); ++} ++ ++extern VCOS_STATUS_T vcos_generic_event_flags_get(VCOS_EVENT_FLAGS_T *flags, ++ VCOS_UNSIGNED bitmask, ++ VCOS_OPTION op, ++ VCOS_UNSIGNED suspend, ++ VCOS_UNSIGNED *retrieved_bits) ++{ ++ VCOS_EVENT_WAITER_T waitreq; ++ VCOS_STATUS_T rc = VCOS_EAGAIN; ++ int satisfied = 0; ++ ++ vcos_assert(flags); ++ ++ /* default retrieved bits to 0 */ ++ *retrieved_bits = 0; ++ ++ vcos_mutex_lock(&flags->lock); ++ switch (op & VCOS_EVENT_FLAG_OP_MASK) ++ { ++ case VCOS_AND: ++ if ((flags->events & bitmask) == bitmask) ++ { ++ *retrieved_bits = flags->events; ++ rc = VCOS_SUCCESS; ++ satisfied = 1; ++ if (op & VCOS_CONSUME) ++ flags->events &= ~bitmask; ++ } ++ break; ++ ++ case VCOS_OR: ++ if (flags->events & bitmask) ++ { ++ *retrieved_bits = flags->events; ++ rc = VCOS_SUCCESS; ++ satisfied = 1; ++ if (op & VCOS_CONSUME) ++ flags->events &= ~bitmask; ++ } ++ break; ++ ++ default: ++ vcos_assert(0); ++ rc = VCOS_EINVAL; ++ break; ++ } ++ ++ if (!satisfied && suspend) ++ { ++ /* Have to go to sleep. ++ * ++ * Append to tail so we get FIFO ordering. ++ */ ++ waitreq.requested_events = bitmask; ++ waitreq.op = op; ++ waitreq.return_status = VCOS_EAGAIN; ++ waitreq.flags = flags; ++ waitreq.actual_events = 0; ++ waitreq.thread = vcos_thread_current(); ++ waitreq.next = 0; ++ vcos_assert(waitreq.thread != (VCOS_THREAD_T*)-1); ++ VCOS_QUEUE_APPEND_TAIL(&flags->waiters, &waitreq); ++ ++ if (suspend != (VCOS_UNSIGNED)-1) ++ _vcos_task_timer_set(event_flags_timer_expired, &waitreq, suspend); ++ ++ vcos_mutex_unlock(&flags->lock); ++ /* go to sleep and wait to be signalled or timeout */ ++ ++ _vcos_thread_sem_wait(); ++ ++ *retrieved_bits = waitreq.actual_events; ++ rc = waitreq.return_status; ++ ++ /* cancel the timer - do not do this while holding the mutex as it ++ * might be waiting for the timeout function to complete, which will ++ * try to take the mutex. ++ */ ++ if (suspend != (VCOS_UNSIGNED)-1) ++ _vcos_task_timer_cancel(); ++ } ++ else ++ { ++ vcos_mutex_unlock(&flags->lock); ++ } ++ ++ return rc; ++} ++ ++ ++/** Called when a get call times out. Remove this thread's ++ * entry from the waiting queue, then resume the thread. ++ */ ++static void event_flags_timer_expired(void *cxt) ++{ ++ VCOS_EVENT_WAITER_T *waitreq = (VCOS_EVENT_WAITER_T *)cxt; ++ VCOS_EVENT_FLAGS_T *flags = waitreq->flags; ++ VCOS_EVENT_WAITER_T **plist; ++ VCOS_EVENT_WAITER_T *prev = NULL; ++ VCOS_THREAD_T *thread = 0; ++ ++ vcos_assert(flags); ++ ++ vcos_mutex_lock(&flags->lock); ++ ++ /* walk the list of waiting threads on this event group, and remove ++ * the one that has expired. ++ * ++ * FIXME: could use doubly-linked list if lots of threads are found ++ * to be waiting on a single event flag instance. ++ */ ++ plist = &flags->waiters.head; ++ while (*plist != NULL) ++ { ++ if (*plist == waitreq) ++ { ++ int at_end; ++ /* found it */ ++ thread = (*plist)->thread; ++ at_end = ((*plist)->next == NULL); ++ ++ /* link past */ ++ *plist = (*plist)->next; ++ if (at_end) ++ flags->waiters.tail = prev; ++ ++ break; ++ } ++ prev = *plist; ++ plist = &(*plist)->next; ++ } ++ vcos_assert(waiter_list_valid(flags)); ++ ++ vcos_mutex_unlock(&flags->lock); ++ ++ if (thread) ++ { ++ _vcos_thread_sem_post(thread); ++ } ++} ++ ++#ifndef NDEBUG ++ ++static int waiter_list_valid(VCOS_EVENT_FLAGS_T *flags) ++{ ++ int valid; ++ /* Either both head and tail are NULL, or neither are NULL */ ++ if (flags->waiters.head == NULL) ++ { ++ valid = (flags->waiters.tail == NULL); ++ } ++ else ++ { ++ valid = (flags->waiters.tail != NULL); ++ } ++ ++ /* If head and tail point at the same non-NULL element, then there ++ * is only one element in the list. ++ */ ++ if (flags->waiters.head && (flags->waiters.head == flags->waiters.tail)) ++ { ++ valid = (flags->waiters.head->next == NULL); ++ } ++ return valid; ++} ++ ++#endif +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/generic/vcos_generic_event_flags.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/generic/vcos_generic_event_flags.h 2013-07-26 19:37:11.000000000 +0000 +@@ -0,0 +1,118 @@ ++/* ++ * Copyright (c) 2010-2011 Broadcom. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++/*============================================================================= ++VideoCore OS Abstraction Layer - event flags implemented via a semaphore ++=============================================================================*/ ++ ++#ifndef VCOS_GENERIC_EVENT_FLAGS_H ++#define VCOS_GENERIC_EVENT_FLAGS_H ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++#include "interface/vcos/vcos_types.h" ++ ++/** ++ * \file ++ * ++ * This provides event flags (as per Nucleus Event Groups) based on a ++ * mutex, a semaphore (per waiting thread) and a timer (per waiting ++ * thread). ++ * ++ * The data structure is a 32 bit unsigned int (the current set of ++ * flags) and a linked list of clients waiting to be 'satisfied'. ++ * ++ * The mutex merely locks access to the data structure. If a client ++ * calls vcos_event_flags_get() and the requested bits are not already ++ * present, it then sleeps on its per-thread semaphore after adding ++ * this semaphore to the queue waiting. It also sets up a timer. ++ * ++ * The per-thread semaphore and timer are actually stored in the ++ * thread context (joinable thread). In future it may become necessary ++ * to support non-VCOS threads by using thread local storage to ++ * create these objects and associate them with the thread. ++ */ ++ ++struct VCOS_EVENT_WAITER_T; ++ ++typedef struct VCOS_EVENT_FLAGS_T ++{ ++ VCOS_UNSIGNED events; /**< Events currently set */ ++ VCOS_MUTEX_T lock; /**< Serialize access */ ++ struct ++ { ++ struct VCOS_EVENT_WAITER_T *head; /**< List of threads waiting */ ++ struct VCOS_EVENT_WAITER_T *tail; /**< List of threads waiting */ ++ } waiters; ++} VCOS_EVENT_FLAGS_T; ++ ++#define VCOS_OR 1 ++#define VCOS_AND 2 ++#define VCOS_CONSUME 4 ++#define VCOS_OR_CONSUME (VCOS_OR | VCOS_CONSUME) ++#define VCOS_AND_CONSUME (VCOS_AND | VCOS_CONSUME) ++#define VCOS_EVENT_FLAG_OP_MASK (VCOS_OR|VCOS_AND) ++ ++VCOSPRE_ VCOS_STATUS_T VCOSPOST_ vcos_generic_event_flags_create(VCOS_EVENT_FLAGS_T *flags, const char *name); ++VCOSPRE_ void VCOSPOST_ vcos_generic_event_flags_set(VCOS_EVENT_FLAGS_T *flags, ++ VCOS_UNSIGNED events, ++ VCOS_OPTION op); ++VCOSPRE_ void VCOSPOST_ vcos_generic_event_flags_delete(VCOS_EVENT_FLAGS_T *); ++VCOSPRE_ VCOS_STATUS_T VCOSPOST_ vcos_generic_event_flags_get(VCOS_EVENT_FLAGS_T *flags, ++ VCOS_UNSIGNED requested_events, ++ VCOS_OPTION op, ++ VCOS_UNSIGNED suspend, ++ VCOS_UNSIGNED *retrieved_events); ++ ++#ifdef VCOS_INLINE_BODIES ++ ++VCOS_INLINE_IMPL ++VCOS_STATUS_T vcos_event_flags_create(VCOS_EVENT_FLAGS_T *flags, const char *name) { ++ return vcos_generic_event_flags_create(flags, name); ++} ++ ++VCOS_INLINE_IMPL ++void vcos_event_flags_set(VCOS_EVENT_FLAGS_T *flags, ++ VCOS_UNSIGNED events, ++ VCOS_OPTION op) { ++ vcos_generic_event_flags_set(flags, events, op); ++} ++ ++VCOS_INLINE_IMPL ++void vcos_event_flags_delete(VCOS_EVENT_FLAGS_T *f) { ++ vcos_generic_event_flags_delete(f); ++} ++ ++VCOS_INLINE_IMPL ++VCOS_STATUS_T vcos_event_flags_get(VCOS_EVENT_FLAGS_T *flags, ++ VCOS_UNSIGNED requested_events, ++ VCOS_OPTION op, ++ VCOS_UNSIGNED suspend, ++ VCOS_UNSIGNED *retrieved_events) { ++ return vcos_generic_event_flags_get(flags, requested_events, op, suspend, retrieved_events); ++} ++ ++#endif /* VCOS_INLINE_BODIES */ ++ ++#ifdef __cplusplus ++} ++#endif ++#endif ++ +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/generic/vcos_generic_named_sem.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/generic/vcos_generic_named_sem.h 2013-07-26 19:37:11.000000000 +0000 +@@ -0,0 +1,92 @@ ++/* ++ * Copyright (c) 2010-2011 Broadcom. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++/*============================================================================= ++VideoCore OS Abstraction Layer - named semaphores ++=============================================================================*/ ++ ++#ifndef VCOS_GENERIC_NAMED_SEM_H ++#define VCOS_GENERIC_NAMED_SEM_H ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++#include "interface/vcos/vcos_types.h" ++ ++/** ++ * \file ++ * ++ * Generic support for named semaphores, using regular ones. This is only ++ * suitable for emulating them on an embedded MMUless system, since there is ++ * no support for opening semaphores across process boundaries. ++ * ++ */ ++ ++#define VCOS_NAMED_SEMAPHORE_NAMELEN 64 ++ ++/* In theory we could use the name facility provided within Nucleus. However, this ++ * is hard to do as semaphores are constantly being created and destroyed; we ++ * would need to stop everything while allocating the memory for the semaphore ++ * list and then walking it. So keep our own list. ++ */ ++typedef struct VCOS_NAMED_SEMAPHORE_T ++{ ++ struct VCOS_NAMED_SEMAPHORE_IMPL_T *actual; /**< There are 'n' named semaphores per 1 actual semaphore */ ++ VCOS_SEMAPHORE_T *sem; /**< Pointer to actual underlying semaphore */ ++} VCOS_NAMED_SEMAPHORE_T; ++ ++VCOSPRE_ VCOS_STATUS_T VCOSPOST_ ++vcos_generic_named_semaphore_create(VCOS_NAMED_SEMAPHORE_T *sem, const char *name, VCOS_UNSIGNED count); ++ ++VCOSPRE_ void VCOSPOST_ vcos_named_semaphore_delete(VCOS_NAMED_SEMAPHORE_T *sem); ++ ++VCOSPRE_ VCOS_STATUS_T VCOSPOST_ _vcos_named_semaphore_init(void); ++VCOSPRE_ void VCOSPOST_ _vcos_named_semaphore_deinit(void); ++ ++#if defined(VCOS_INLINE_BODIES) ++ ++VCOS_INLINE_IMPL ++VCOS_STATUS_T vcos_named_semaphore_create(VCOS_NAMED_SEMAPHORE_T *sem, const char *name, VCOS_UNSIGNED count) { ++ return vcos_generic_named_semaphore_create(sem, name, count); ++} ++ ++VCOS_INLINE_IMPL ++void vcos_named_semaphore_wait(VCOS_NAMED_SEMAPHORE_T *sem) { ++ vcos_semaphore_wait(sem->sem); ++} ++ ++VCOS_INLINE_IMPL ++VCOS_STATUS_T vcos_named_semaphore_trywait(VCOS_NAMED_SEMAPHORE_T *sem) { ++ return vcos_semaphore_trywait(sem->sem); ++} ++ ++VCOS_INLINE_IMPL ++void vcos_named_semaphore_post(VCOS_NAMED_SEMAPHORE_T *sem) { ++ vcos_semaphore_post(sem->sem); ++} ++ ++ ++#endif ++ ++#ifdef __cplusplus ++} ++#endif ++#endif ++ ++ +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/generic/vcos_generic_quickslow_mutex.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/generic/vcos_generic_quickslow_mutex.h 2013-07-26 19:37:11.000000000 +0000 +@@ -0,0 +1,86 @@ ++/* ++ * Copyright (c) 2010-2011 Broadcom. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++/*============================================================================= ++VideoCore OS Abstraction Layer - reentrant mutexes created from regular ones. ++=============================================================================*/ ++ ++#ifndef VCOS_GENERIC_QUICKSLOW_MUTEX_H ++#define VCOS_GENERIC_QUICKSLOW_MUTEX_H ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++#include "interface/vcos/vcos_types.h" ++ ++/** ++ * \file ++ * ++ * Quickslow Mutexes implemented as regular ones (i.e. quick and slow modes are the same). ++ * ++ */ ++ ++typedef VCOS_MUTEX_T VCOS_QUICKSLOW_MUTEX_T; ++ ++#if defined(VCOS_INLINE_BODIES) ++VCOS_INLINE_IMPL ++VCOS_STATUS_T vcos_quickslow_mutex_create(VCOS_QUICKSLOW_MUTEX_T *m, const char *name) ++{ ++ return vcos_mutex_create(m, name); ++} ++ ++VCOS_INLINE_IMPL ++void vcos_quickslow_mutex_delete(VCOS_QUICKSLOW_MUTEX_T *m) ++{ ++ vcos_mutex_delete(m); ++} ++ ++VCOS_INLINE_IMPL ++void vcos_quickslow_mutex_lock(VCOS_QUICKSLOW_MUTEX_T *m) ++{ ++ while (vcos_mutex_lock(m) == VCOS_EAGAIN); ++} ++ ++VCOS_INLINE_IMPL ++void vcos_quickslow_mutex_unlock(VCOS_QUICKSLOW_MUTEX_T *m) ++{ ++ vcos_mutex_unlock(m); ++} ++ ++VCOS_INLINE_IMPL ++void vcos_quickslow_mutex_lock_quick(VCOS_QUICKSLOW_MUTEX_T *m) ++{ ++ while (vcos_mutex_lock(m) == VCOS_EAGAIN); ++} ++ ++VCOS_INLINE_IMPL ++void vcos_quickslow_mutex_unlock_quick(VCOS_QUICKSLOW_MUTEX_T *m) ++{ ++ vcos_mutex_unlock(m); ++} ++ ++#endif ++ ++ ++#ifdef __cplusplus ++} ++#endif ++#endif ++ ++ +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/generic/vcos_generic_reentrant_mtx.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/generic/vcos_generic_reentrant_mtx.h 2013-07-26 19:37:11.000000000 +0000 +@@ -0,0 +1,86 @@ ++/* ++ * Copyright (c) 2010-2011 Broadcom. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++/*============================================================================= ++VideoCore OS Abstraction Layer - reentrant mutexes created from regular ones. ++=============================================================================*/ ++ ++#ifndef VCOS_GENERIC_REENTRANT_MUTEX_H ++#define VCOS_GENERIC_REENTRANT_MUTEX_H ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++#include "interface/vcos/vcos_types.h" ++ ++/** ++ * \file ++ * ++ * Reentrant Mutexes from regular ones. ++ * ++ */ ++ ++typedef struct VCOS_REENTRANT_MUTEX_T ++{ ++ VCOS_MUTEX_T mutex; ++ VCOS_THREAD_T *owner; ++ unsigned count; ++} VCOS_REENTRANT_MUTEX_T; ++ ++/* Extern definitions of functions that do the actual work */ ++ ++VCOSPRE_ VCOS_STATUS_T VCOSPOST_ vcos_generic_reentrant_mutex_create(VCOS_REENTRANT_MUTEX_T *m, const char *name); ++ ++VCOSPRE_ void VCOSPOST_ vcos_generic_reentrant_mutex_delete(VCOS_REENTRANT_MUTEX_T *m); ++ ++VCOSPRE_ void VCOSPOST_ vcos_generic_reentrant_mutex_lock(VCOS_REENTRANT_MUTEX_T *m); ++ ++VCOSPRE_ void VCOSPOST_ vcos_generic_reentrant_mutex_unlock(VCOS_REENTRANT_MUTEX_T *m); ++ ++/* Inline forwarding functions */ ++ ++#if defined(VCOS_INLINE_BODIES) ++ ++VCOS_INLINE_IMPL ++VCOS_STATUS_T vcos_reentrant_mutex_create(VCOS_REENTRANT_MUTEX_T *m, const char *name) { ++ return vcos_generic_reentrant_mutex_create(m,name); ++} ++ ++VCOS_INLINE_IMPL ++void vcos_reentrant_mutex_delete(VCOS_REENTRANT_MUTEX_T *m) { ++ vcos_generic_reentrant_mutex_delete(m); ++} ++ ++VCOS_INLINE_IMPL ++void vcos_reentrant_mutex_lock(VCOS_REENTRANT_MUTEX_T *m) { ++ vcos_generic_reentrant_mutex_lock(m); ++} ++ ++VCOS_INLINE_IMPL ++void vcos_reentrant_mutex_unlock(VCOS_REENTRANT_MUTEX_T *m) { ++ vcos_generic_reentrant_mutex_unlock(m); ++} ++#endif ++ ++#ifdef __cplusplus ++} ++#endif ++#endif ++ ++ +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/generic/vcos_generic_tls.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/generic/vcos_generic_tls.h 2013-07-26 19:37:11.000000000 +0000 +@@ -0,0 +1,155 @@ ++/* ++ * Copyright (c) 2010-2011 Broadcom. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++/*============================================================================= ++VideoCore OS Abstraction Layer - generic thread local storage ++=============================================================================*/ ++ ++#ifndef VCOS_GENERIC_TLS_H ++#define VCOS_GENERIC_TLS_H ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++#include "interface/vcos/vcos_types.h" ++ ++/** ++ * \file ++ * ++ * Do an emulation of Thread Local Storage. The platform needs to ++ * provide a way to set and get a per-thread pointer which is ++ * where the TLS data itself is stored. ++ * ++ * ++ * Each thread that wants to join in this scheme needs to call ++ * vcos_tls_thread_register(). ++ * ++ * The platform needs to support the macros/functions ++ * _vcos_tls_thread_ptr_set() and _vcos_tls_thread_ptr_get(). ++ */ ++ ++#ifndef VCOS_WANT_TLS_EMULATION ++#error Should not be included unless TLS emulation is defined ++#endif ++ ++/** Number of slots to reserve per thread. This results in an overhead ++ * of this many words per thread. ++ */ ++#define VCOS_TLS_MAX_SLOTS 4 ++ ++/** TLS key. Allocating one of these reserves the client one of the ++ * available slots. ++ */ ++typedef VCOS_UNSIGNED VCOS_TLS_KEY_T; ++ ++/** TLS per-thread structure. Each thread gets one of these ++ * if TLS emulation (rather than native TLS support) is ++ * being used. ++ */ ++typedef struct VCOS_TLS_THREAD_T ++{ ++ void *slots[VCOS_TLS_MAX_SLOTS]; ++} VCOS_TLS_THREAD_T; ++ ++/* ++ * Internal APIs ++ */ ++ ++/** Register this thread's TLS storage area. */ ++VCOSPRE_ void VCOSPOST_ vcos_tls_thread_register(VCOS_TLS_THREAD_T *); ++ ++/** Create a new TLS key */ ++VCOSPRE_ VCOS_STATUS_T VCOSPOST_ vcos_generic_tls_create(VCOS_TLS_KEY_T *key); ++ ++/** Delete a TLS key */ ++VCOSPRE_ void VCOSPOST_ vcos_generic_tls_delete(VCOS_TLS_KEY_T tls); ++ ++/** Initialise the TLS library */ ++VCOSPRE_ VCOS_STATUS_T VCOSPOST_ vcos_tls_init(void); ++ ++/** Deinitialise the TLS library */ ++VCOSPRE_ void VCOSPOST_ vcos_tls_deinit(void); ++ ++#if defined(VCOS_INLINE_BODIES) ++ ++#undef VCOS_ASSERT_LOGGING_DISABLE ++#define VCOS_ASSERT_LOGGING_DISABLE 1 ++ ++/* ++ * Implementations of public API functions ++ */ ++ ++/** Set the given value. Since everything is per-thread, there is no need ++ * for any locking. ++ */ ++VCOS_INLINE_IMPL ++VCOS_STATUS_T vcos_tls_set(VCOS_TLS_KEY_T tls, void *v) { ++ VCOS_TLS_THREAD_T *tlsdata = _vcos_tls_thread_ptr_get(); ++ vcos_assert(tlsdata); /* Fires if this thread has not been registered */ ++ if (tlsslots[tls] = v; ++ return VCOS_SUCCESS; ++ } ++ else ++ { ++ vcos_assert(0); ++ return VCOS_EINVAL; ++ } ++} ++ ++/** Get the given value. No locking required. ++ */ ++VCOS_INLINE_IMPL ++void *vcos_tls_get(VCOS_TLS_KEY_T tls) { ++ VCOS_TLS_THREAD_T *tlsdata = _vcos_tls_thread_ptr_get(); ++ vcos_assert(tlsdata); /* Fires if this thread has not been registered */ ++ if (tlsslots[tls]; ++ } ++ else ++ { ++ vcos_assert(0); ++ return NULL; ++ } ++} ++ ++VCOS_INLINE_IMPL ++VCOS_STATUS_T vcos_tls_create(VCOS_TLS_KEY_T *key) { ++ return vcos_generic_tls_create(key); ++} ++ ++VCOS_INLINE_IMPL ++void vcos_tls_delete(VCOS_TLS_KEY_T tls) { ++ vcos_generic_tls_delete(tls); ++} ++ ++#undef VCOS_ASSERT_LOGGING_DISABLE ++#define VCOS_ASSERT_LOGGING_DISABLE 0 ++ ++#endif /* VCOS_INLINE_BODIES */ ++ ++#ifdef __cplusplus ++} ++#endif ++ ++#endif ++ ++ +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/generic/vcos_joinable_thread_from_plain.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/generic/vcos_joinable_thread_from_plain.h 2013-07-26 19:37:11.000000000 +0000 +@@ -0,0 +1,214 @@ ++/* ++ * Copyright (c) 2010-2011 Broadcom. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++/*============================================================================= ++VideoCore OS Abstraction Layer - implementation: joinable thread from plain ++=============================================================================*/ ++ ++/** \file ++ * ++ * Header file for platforms creating the joinable thread from a lowlevel ++ * thread. ++ * ++ * In addition to the actual thread, the following are also created: ++ * ++ * - a semaphore to wait on when joining the thread ++ * - a semaphore to support counted suspend/resume (used by event group) ++ * - a per-thread timer (used by event group, but could be removed) ++ */ ++ ++#ifndef VCOS_JOINABLE_THREAD_FROM_PLAIN_H ++#define VCOS_JOINABLE_THREAD_FROM_PLAIN_H ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++#include "interface/vcos/vcos_semaphore.h" ++#include "interface/vcos/vcos_lowlevel_thread.h" ++#include "interface/vcos/vcos_timer.h" ++ ++#ifdef VCOS_WANT_TLS_EMULATION ++#include "interface/vcos/generic/vcos_generic_tls.h" ++#endif ++ ++#define VCOS_THREAD_MAGIC 0x56436a74 ++ ++#define VCOS_THREAD_VALID(t) (t->magic == VCOS_THREAD_MAGIC) ++#define VCOS_HAVE_THREAD_AT_EXIT 1 ++ ++/** Thread attribute structure. Clients should not manipulate this directly, but ++ * should instead use the provided functions. ++ */ ++typedef struct VCOS_THREAD_ATTR_T ++{ ++ void *ta_stackaddr; ++ VCOS_UNSIGNED ta_stacksz; ++ VCOS_UNSIGNED ta_priority; ++ VCOS_UNSIGNED ta_affinity; ++ VCOS_UNSIGNED ta_timeslice; ++ VCOS_UNSIGNED legacy; ++ VCOS_UNSIGNED ta_autostart; ++} VCOS_THREAD_ATTR_T; ++ ++/** Each thread gets a timer, which is for internal VCOS use. ++ */ ++typedef struct _VCOS_THREAD_TIMER_T ++{ ++ VCOS_TIMER_T timer; ++ void (*pfn)(void *); ++ void *cxt; ++} _VCOS_THREAD_TIMER_T; ++ ++typedef void (*VCOS_THREAD_EXIT_HANDLER_T)(void *); ++/** Called at thread exit. ++ */ ++typedef struct VCOS_THREAD_EXIT_T ++{ ++ VCOS_THREAD_EXIT_HANDLER_T pfn; ++ void *cxt; ++} VCOS_THREAD_EXIT_T; ++#define VCOS_MAX_EXIT_HANDLERS 8 ++ ++/* The name field isn't used for anything, so we can just copy the ++ * the pointer. Nucleus makes its own copy. ++ */ ++typedef const char * VCOS_LLTHREAD_T_NAME; ++#define _VCOS_LLTHREAD_NAME(dst,src) (dst)=(src) ++ ++/* ++ * Simulated TLS support ++ */ ++ ++ ++/** Thread structure. ++ * ++ * \warning Do not access the members of this structure directly! ++ */ ++typedef struct VCOS_THREAD_T ++{ ++ VCOS_LLTHREAD_T thread; /**< The underlying thread */ ++ char name[16]; /**< The name */ ++ unsigned int magic; /**< For debug */ ++ void *exit_data; /**< Exit data passed out in vcos_joinable_thread_exit() */ ++ void *stack; /**< Stack, if not supplied by caller */ ++ VCOS_SEMAPHORE_T wait; /**< Semaphore to wait on at join */ ++ VCOS_SEMAPHORE_T suspend; /**< Semaphore to wait on for counted suspend */ ++ int16_t joined; /**< Joined yet? For debug. */ ++ VCOS_UNSIGNED legacy; /**< Use (argc,argv) for entry point arguments */ ++ void *(*entry)(void*); /**< Entry point */ ++ void *arg; /**< Argument passed to entry point */ ++ void *(*term)(void*); /**< Termination function, used by reaper */ ++ void *term_arg; /**< Argument passed to termination function */ ++ _VCOS_THREAD_TIMER_T _timer; /**< Internal timer, mainly for event groups */ ++#ifdef VCOS_WANT_TLS_EMULATION ++ VCOS_TLS_THREAD_T _tls; /**< TLS data when native TLS not available, or NULL */ ++#endif ++ /** Array of functions to call at thread exit */ ++ VCOS_THREAD_EXIT_T at_exit[VCOS_MAX_EXIT_HANDLERS]; ++ ++ struct VCOS_THREAD_T *next; /**< For linked lists of threads */ ++} VCOS_THREAD_T; ++ ++#if defined(VCOS_INLINE_BODIES) ++ ++VCOS_INLINE_IMPL ++void vcos_thread_attr_setstack(VCOS_THREAD_ATTR_T *attrs, void *addr, VCOS_UNSIGNED stacksz) { ++ attrs->ta_stackaddr = addr; ++ attrs->ta_stacksz = stacksz; ++} ++ ++VCOS_INLINE_IMPL ++void vcos_thread_attr_setstacksize(VCOS_THREAD_ATTR_T *attrs, VCOS_UNSIGNED stacksz) { ++ attrs->ta_stacksz = stacksz; ++} ++ ++VCOS_INLINE_IMPL ++void vcos_thread_attr_setpriority(VCOS_THREAD_ATTR_T *attrs, VCOS_UNSIGNED pri) { ++ attrs->ta_priority = pri; ++} ++ ++VCOS_INLINE_IMPL ++void vcos_thread_attr_setaffinity(VCOS_THREAD_ATTR_T *attrs, VCOS_UNSIGNED affinity) { ++ attrs->ta_affinity = affinity; ++} ++ ++VCOS_INLINE_IMPL ++void vcos_thread_attr_settimeslice(VCOS_THREAD_ATTR_T *attrs, VCOS_UNSIGNED ts) { ++ attrs->ta_timeslice = ts; ++} ++ ++VCOS_INLINE_IMPL ++void _vcos_thread_attr_setlegacyapi(VCOS_THREAD_ATTR_T *attrs, VCOS_UNSIGNED legacy) { ++ attrs->legacy = legacy; ++} ++ ++VCOS_INLINE_IMPL ++void vcos_thread_attr_setautostart(VCOS_THREAD_ATTR_T *attrs, VCOS_UNSIGNED autostart) { ++ attrs->ta_autostart = autostart; ++} ++ ++VCOS_INLINE_IMPL ++VCOS_THREAD_T *vcos_thread_current(void) { ++ VCOS_THREAD_T *ret = (VCOS_THREAD_T*)vcos_llthread_current(); ++ /*If we're called from a non-vcos thread, this assert will fail. ++ *XXX FIXME why is this commented out? ++ *vcos_assert(ret->magic == VCOS_THREAD_MAGIC); ++ */ ++ return ret; ++} ++ ++VCOS_INLINE_IMPL ++int vcos_thread_running(VCOS_THREAD_T *thread) { ++ return vcos_llthread_running(&thread->thread); ++} ++ ++VCOS_INLINE_IMPL ++void vcos_thread_resume(VCOS_THREAD_T *thread) { ++ vcos_llthread_resume(&thread->thread); ++} ++ ++#endif /* VCOS_INLINE_BODIES */ ++ ++/** ++ * \brief Create a VCOS_THREAD_T for the current thread. This is so we can have ++ * VCOS_THREAD_Ts even for threads not originally created by VCOS (eg the ++ * thread that calls vcos_init) ++ */ ++extern VCOS_STATUS_T _vcos_thread_create_attach(VCOS_THREAD_T *thread, ++ const char *name); ++ ++/** ++ * \brief Deletes the VCOS_THREAD_T, but does not wait for the underlying ++ * thread to exit. This will cleanup everything created by ++ * _vcos_thread_create_attach ++ */ ++extern void _vcos_thread_delete(VCOS_THREAD_T *thread); ++ ++/** Register a function to be called when the current thread exits. ++ */ ++extern VCOS_STATUS_T vcos_thread_at_exit(void (*pfn)(void*), void *cxt); ++ ++/** Deregister a previously registered at-exit function. ++ */ ++extern void vcos_thread_deregister_at_exit(void (*pfn)(void*), void *cxt); ++ ++#ifdef __cplusplus ++} ++#endif ++#endif /* VCOS_JOINABLE_THREAD_FROM_PLAIN_H */ +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/generic/vcos_latch_from_sem.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/generic/vcos_latch_from_sem.h 2013-07-26 19:37:11.000000000 +0000 +@@ -0,0 +1,59 @@ ++/* ++ * Copyright (c) 2010-2011 Broadcom. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++/*============================================================================= ++VideoCore OS Abstraction Layer - Construct a latch from a semaphore ++=============================================================================*/ ++ ++/** FIXME: rename to vcos_mutex_from_sem.c ++ */ ++ ++typedef struct VCOS_MUTEX_T { ++ VCOS_SEMAPHORE_T sem; ++ struct VCOS_THREAD_T *owner; ++} VCOS_MUTEX_T; ++ ++extern VCOS_STATUS_T vcos_generic_mutex_create(VCOS_MUTEX_T *latch, const char *name); ++extern void vcos_generic_mutex_delete(VCOS_MUTEX_T *latch); ++extern VCOS_STATUS_T vcos_generic_mutex_lock(VCOS_MUTEX_T *latch); ++extern void vcos_generic_mutex_unlock(VCOS_MUTEX_T *latch); ++ ++#if defined(VCOS_INLINE_BODIES) ++ ++VCOS_INLINE_IMPL ++VCOS_STATUS_T vcos_mutex_create(VCOS_MUTEX_T *latch, const char *name) { ++ return vcos_generic_mutex_create(latch,name); ++} ++ ++VCOS_INLINE_IMPL ++void vcos_mutex_delete(VCOS_MUTEX_T *latch) { ++ vcos_generic_mutex_delete(latch); ++} ++ ++VCOS_INLINE_IMPL ++VCOS_STATUS_T vcos_mutex_lock(VCOS_MUTEX_T *latch) { ++ return vcos_generic_mutex_lock(latch); ++} ++ ++VCOS_INLINE_IMPL ++void vcos_mutex_unlock(VCOS_MUTEX_T *latch) { ++ vcos_generic_mutex_unlock(latch); ++} ++ ++#endif /* VCOS_INLINE_BODIES */ ++ +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/generic/vcos_logcat.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/generic/vcos_logcat.c 2013-07-26 19:37:11.000000000 +0000 +@@ -0,0 +1,560 @@ ++/* ++ * Copyright (c) 2010-2011 Broadcom. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++/*============================================================================= ++Categorized logging for VCOS - a generic implementation. ++=============================================================================*/ ++ ++#include "interface/vcos/vcos.h" ++#include "interface/vcos/vcos_ctype.h" ++#include "interface/vcos/vcos_string.h" ++ ++static VCOS_MUTEX_T lock; ++static int warned_loglevel; /* only warn about invalid log level once */ ++static VCOS_VLOG_IMPL_FUNC_T vcos_vlog_impl_func = vcos_vlog_default_impl; ++ ++#define VCOS_LOG_CATEGORY (&dflt_log_category) ++static VCOS_LOG_CAT_T dflt_log_category; ++VCOS_LOG_CAT_T *vcos_logging_categories = NULL; ++static int inited; ++ ++#if VCOS_HAVE_CMD ++ ++/* ++ * For kernel or videocore purposes, we generally want the log command. For ++ * user-space apps, they might want to provide their own log command, so we ++ * don't include the built in on. ++ * ++ * So pthreads/vcos_platform.h defines VCOS_WANT_LOG_CMD to be 0. It is ++ * undefined elsewhere. ++ */ ++ ++# if !defined( VCOS_WANT_LOG_CMD ) ++# define VCOS_WANT_LOG_CMD 1 ++# endif ++#else ++# define VCOS_WANT_LOG_CMD 0 ++#endif ++ ++#if VCOS_WANT_LOG_CMD ++ ++/***************************************************************************** ++* ++* Does a vcos_assert(0), which is useful to test logging. ++* ++*****************************************************************************/ ++ ++VCOS_STATUS_T vcos_log_assert_cmd( VCOS_CMD_PARAM_T *param ) ++{ ++ (void)param; ++ ++#if defined( NDEBUG ) && !defined( VCOS_RELEASE_ASSERTS ) ++ vcos_log_error( "vcos_asserts have been compiled out" ); ++ vcos_cmd_printf( param, "vcos_asserts have been compiled out - did a vcos_log_error instead\n" ); ++#else ++ vcos_assert(0); ++ vcos_cmd_printf( param, "Executed vcos_assert(0)\n" ); ++#endif ++ ++ return VCOS_SUCCESS; ++} ++ ++/***************************************************************************** ++* ++* Sets a vcos logging level ++* ++*****************************************************************************/ ++ ++VCOS_STATUS_T vcos_log_set_cmd( VCOS_CMD_PARAM_T *param ) ++{ ++ VCOS_LOG_CAT_T *cat; ++ char *name; ++ char *levelStr; ++ VCOS_LOG_LEVEL_T level; ++ VCOS_STATUS_T status; ++ ++ if ( param->argc != 3 ) ++ { ++ vcos_cmd_usage( param ); ++ return VCOS_EINVAL; ++ } ++ ++ name = param->argv[1]; ++ levelStr = param->argv[2]; ++ ++ if ( vcos_string_to_log_level( levelStr, &level ) != VCOS_SUCCESS ) ++ { ++ vcos_cmd_printf( param, "Unrecognized logging level: '%s'\n", levelStr ); ++ return VCOS_EINVAL; ++ } ++ ++ vcos_mutex_lock(&lock); ++ ++ status = VCOS_SUCCESS; ++ for ( cat = vcos_logging_categories; cat != NULL; cat = cat->next ) ++ { ++ if ( vcos_strcmp( name, cat->name ) == 0 ) ++ { ++ cat->level = level; ++ vcos_cmd_printf( param, "Category %s level set to %s\n", name, levelStr ); ++ break; ++ } ++ } ++ if ( cat == NULL ) ++ { ++ vcos_cmd_printf( param, "Unrecognized category: '%s'\n", name ); ++ status = VCOS_ENOENT; ++ } ++ ++ vcos_mutex_unlock(&lock); ++ ++ return status; ++} ++ ++/***************************************************************************** ++* ++* Prints out the current settings for a given category (or all cvategories) ++* ++*****************************************************************************/ ++ ++VCOS_STATUS_T vcos_log_status_cmd( VCOS_CMD_PARAM_T *param ) ++{ ++ VCOS_LOG_CAT_T *cat; ++ VCOS_STATUS_T status; ++ ++ vcos_mutex_lock(&lock); ++ ++ if ( param->argc == 1) ++ { ++ int nw; ++ int nameWidth = 0; ++ ++ /* Print information about all of the categories. */ ++ ++ for ( cat = vcos_logging_categories; cat != NULL; cat = cat->next ) ++ { ++ nw = (int)strlen( cat->name ); ++ ++ if ( nw > nameWidth ) ++ { ++ nameWidth = nw; ++ } ++ } ++ ++ for ( cat = vcos_logging_categories; cat != NULL; cat = cat->next ) ++ { ++ vcos_cmd_printf( param, "%-*s - %s\n", nameWidth, cat->name, vcos_log_level_to_string( cat->level )); ++ } ++ } ++ else ++ { ++ /* Print information about a particular category */ ++ ++ for ( cat = vcos_logging_categories; cat != NULL; cat = cat->next ) ++ { ++ if ( vcos_strcmp( cat->name, param->argv[1] ) == 0 ) ++ { ++ vcos_cmd_printf( param, "%s - %s\n", cat->name, vcos_log_level_to_string( cat->level )); ++ break; ++ } ++ } ++ if ( cat == NULL ) ++ { ++ vcos_cmd_printf( param, "Unrecognized logging category: '%s'\n", param->argv[1] ); ++ status = VCOS_ENOENT; ++ goto out; ++ } ++ } ++ ++ status = VCOS_SUCCESS; ++out: ++ vcos_mutex_unlock(&lock); ++ ++ return status; ++} ++ ++/***************************************************************************** ++* ++* Prints out the current settings for a given category (or all cvategories) ++* ++*****************************************************************************/ ++ ++VCOS_STATUS_T vcos_log_test_cmd( VCOS_CMD_PARAM_T *param ) ++{ ++ if ( param->argc == 1 ) ++ { ++ static int seq_num = 100; ++ ++ /* No additional arguments - generate a message with an incrementing number */ ++ ++ vcos_log_error( "Test message %d", seq_num ); ++ ++ seq_num++; ++ vcos_cmd_printf( param, "Logged 'Test message %d'\n", seq_num ); ++ } ++ else ++ { ++ int arg_idx; ++ ++ /* Arguments supplied - log these */ ++ ++ for ( arg_idx = 0; arg_idx < param->argc; arg_idx++ ) ++ { ++ vcos_log_error( "argv[%d] = '%s'", arg_idx, param->argv[arg_idx] ); ++ } ++ vcos_cmd_printf( param, "Logged %d line(s) of test data\n", param->argc ); ++ } ++ return VCOS_SUCCESS; ++} ++ ++/***************************************************************************** ++* ++* Internal commands ++* ++*****************************************************************************/ ++ ++static VCOS_CMD_T log_cmd_entry[] = ++{ ++ { "assert", "", vcos_log_assert_cmd, NULL, "Does a vcos_assert(0) to test logging" }, ++ { "set", "category level", vcos_log_set_cmd, NULL, "Sets the vcos logging level for a category" }, ++ { "status", "[category]", vcos_log_status_cmd, NULL, "Prints the vcos log status for a (or all) categories" }, ++ { "test", "[arbitrary text]", vcos_log_test_cmd, NULL, "Does a vcos_log to test logging" }, ++ ++ { NULL, NULL, NULL, NULL, NULL } ++}; ++ ++static VCOS_CMD_T cmd_log = ++ { "log", "command [args]", NULL, log_cmd_entry, "Commands related to vcos logging" }; ++ ++#endif ++ ++void vcos_logging_init(void) ++{ ++ if (inited) ++ { ++ /* FIXME: should print a warning or something here */ ++ return; ++ } ++ vcos_mutex_create(&lock, "vcos_log"); ++ ++ vcos_log_platform_init(); ++ ++ vcos_log_register("default", &dflt_log_category); ++ ++#if VCOS_WANT_LOG_CMD ++ vcos_cmd_register( &cmd_log ); ++#endif ++ ++ vcos_assert(!inited); ++ inited = 1; ++} ++ ++/** Read an alphanumeric token, returning True if we succeeded. ++ */ ++ ++static int read_tok(char *tok, size_t toklen, const char **pstr, char sep) ++{ ++ const char *str = *pstr; ++ size_t n = 0; ++ char ch; ++ ++ /* skip past any whitespace */ ++ while (str[0] && isspace((int)(str[0]))) ++ str++; ++ ++ while ((ch = *str) != '\0' && ++ ch != sep && ++ (isalnum((int)ch) || (ch == '_')) && ++ n != toklen-1) ++ { ++ tok[n++] = ch; ++ str++; ++ } ++ ++ /* did it work out? */ ++ if (ch == '\0' || ch == sep) ++ { ++ if (ch) str++; /* move to next token if not at end */ ++ /* yes */ ++ tok[n] = '\0'; ++ *pstr = str; ++ return 1; ++ } ++ else ++ { ++ /* no */ ++ return 0; ++ } ++} ++ ++const char *vcos_log_level_to_string( VCOS_LOG_LEVEL_T level ) ++{ ++ switch (level) ++ { ++ case VCOS_LOG_UNINITIALIZED: return "uninit"; ++ case VCOS_LOG_NEVER: return "never"; ++ case VCOS_LOG_ERROR: return "error"; ++ case VCOS_LOG_WARN: return "warn"; ++ case VCOS_LOG_INFO: return "info"; ++ case VCOS_LOG_TRACE: return "trace"; ++ } ++ return "???"; ++} ++ ++VCOS_STATUS_T vcos_string_to_log_level( const char *str, VCOS_LOG_LEVEL_T *level ) ++{ ++ if (strcmp(str,"error") == 0) ++ *level = VCOS_LOG_ERROR; ++ else if (strcmp(str,"never") == 0) ++ *level = VCOS_LOG_NEVER; ++ else if (strcmp(str,"warn") == 0) ++ *level = VCOS_LOG_WARN; ++ else if (strcmp(str,"warning") == 0) ++ *level = VCOS_LOG_WARN; ++ else if (strcmp(str,"info") == 0) ++ *level = VCOS_LOG_INFO; ++ else if (strcmp(str,"trace") == 0) ++ *level = VCOS_LOG_TRACE; ++ else ++ return VCOS_EINVAL; ++ ++ return VCOS_SUCCESS; ++} ++ ++static int read_level(VCOS_LOG_LEVEL_T *level, const char **pstr, char sep) ++{ ++ char buf[16]; ++ int ret = 1; ++ if (read_tok(buf,sizeof(buf),pstr,sep)) ++ { ++ if (vcos_string_to_log_level(buf,level) != VCOS_SUCCESS) ++ { ++ vcos_log("Invalid trace level '%s'\n", buf); ++ ret = 0; ++ } ++ } ++ else ++ { ++ ret = 0; ++ } ++ return ret; ++} ++ ++void vcos_log_register(const char *name, VCOS_LOG_CAT_T *category) ++{ ++ const char *env; ++ VCOS_LOG_CAT_T *i; ++ ++ category->name = name; ++ if ( category->level == VCOS_LOG_UNINITIALIZED ) ++ { ++ category->level = VCOS_LOG_ERROR; ++ } ++ category->flags.want_prefix = (category != &dflt_log_category ); ++ ++ vcos_mutex_lock(&lock); ++ ++ /* is it already registered? */ ++ for (i = vcos_logging_categories; i ; i = i->next ) ++ { ++ if (i == category) ++ { ++ i->refcount++; ++ break; ++ } ++ } ++ ++ if (!i) ++ { ++ /* not yet registered */ ++ category->next = vcos_logging_categories; ++ vcos_logging_categories = category; ++ category->refcount++; ++ ++ vcos_log_platform_register(category); ++ } ++ ++ vcos_mutex_unlock(&lock); ++ ++ /* Check to see if this log level has been enabled. Look for ++ * (,)* ++ * ++ * VC_LOGLEVEL=ilcs:info,vchiq:warn ++ */ ++ ++ env = _VCOS_LOG_LEVEL(); ++ if (env) ++ { ++ do ++ { ++ char env_name[64]; ++ VCOS_LOG_LEVEL_T level; ++ if (read_tok(env_name, sizeof(env_name), &env, ':') && ++ read_level(&level, &env, ',')) ++ { ++ if (strcmp(env_name, name) == 0) ++ { ++ category->level = level; ++ break; ++ } ++ } ++ else ++ { ++ if (!warned_loglevel) ++ { ++ vcos_log("VC_LOGLEVEL format invalid at %s\n", env); ++ warned_loglevel = 1; ++ } ++ return; ++ } ++ } while (env[0] != '\0'); ++ } ++ ++ vcos_log_info( "Registered log category '%s' with level %s", ++ category->name, ++ vcos_log_level_to_string( category->level )); ++} ++ ++void vcos_log_unregister(VCOS_LOG_CAT_T *category) ++{ ++ VCOS_LOG_CAT_T **pcat; ++ vcos_mutex_lock(&lock); ++ category->refcount--; ++ if (category->refcount == 0) ++ { ++ pcat = &vcos_logging_categories; ++ while (*pcat != category) ++ { ++ if (!*pcat) ++ break; /* possibly deregistered twice? */ ++ if ((*pcat)->next == NULL) ++ { ++ vcos_assert(0); /* already removed! */ ++ vcos_mutex_unlock(&lock); ++ return; ++ } ++ pcat = &(*pcat)->next; ++ } ++ if (*pcat) ++ *pcat = category->next; ++ ++ vcos_log_platform_unregister(category); ++ } ++ vcos_mutex_unlock(&lock); ++} ++ ++VCOSPRE_ const VCOS_LOG_CAT_T * VCOSPOST_ vcos_log_get_default_category(void) ++{ ++ return &dflt_log_category; ++} ++ ++void vcos_set_log_options(const char *opt) ++{ ++ (void)opt; ++} ++ ++void vcos_log_dump_mem_impl( const VCOS_LOG_CAT_T *cat, ++ const char *label, ++ uint32_t addr, ++ const void *voidMem, ++ size_t numBytes ) ++{ ++ const uint8_t *mem = (const uint8_t *)voidMem; ++ size_t offset; ++ char lineBuf[ 100 ]; ++ char *s; ++ ++ while ( numBytes > 0 ) ++ { ++ s = lineBuf; ++ ++ for ( offset = 0; offset < 16; offset++ ) ++ { ++ if ( offset < numBytes ) ++ { ++ s += vcos_snprintf( s, 4, "%02x ", mem[ offset ]); ++ } ++ else ++ { ++ s += vcos_snprintf( s, 4, " " ); ++ } ++ } ++ ++ for ( offset = 0; offset < 16; offset++ ) ++ { ++ if ( offset < numBytes ) ++ { ++ uint8_t ch = mem[ offset ]; ++ ++ if (( ch < ' ' ) || ( ch > '~' )) ++ { ++ ch = '.'; ++ } ++ *s++ = (char)ch; ++ } ++ } ++ *s++ = '\0'; ++ ++ if (( label != NULL ) && ( *label != '\0' )) ++ { ++ vcos_log_impl( cat, VCOS_LOG_INFO, "%s: %08x: %s", label, addr, lineBuf ); ++ } ++ else ++ { ++ vcos_log_impl( cat, VCOS_LOG_INFO, "%08x: %s", addr, lineBuf ); ++ } ++ ++ addr += 16; ++ mem += 16; ++ if ( numBytes > 16 ) ++ { ++ numBytes -= 16; ++ } ++ else ++ { ++ numBytes = 0; ++ } ++ } ++ ++} ++ ++void vcos_log_impl(const VCOS_LOG_CAT_T *cat, VCOS_LOG_LEVEL_T _level, const char *fmt, ...) ++{ ++ va_list ap; ++ va_start(ap,fmt); ++ vcos_vlog_impl( cat, _level, fmt, ap ); ++ va_end(ap); ++} ++ ++void vcos_vlog_impl(const VCOS_LOG_CAT_T *cat, VCOS_LOG_LEVEL_T _level, const char *fmt, va_list args) ++{ ++ vcos_vlog_impl_func( cat, _level, fmt, args ); ++} ++ ++void vcos_set_vlog_impl( VCOS_VLOG_IMPL_FUNC_T vlog_impl_func ) ++{ ++ if ( vlog_impl_func == NULL ) ++ { ++ vcos_vlog_impl_func = vcos_vlog_default_impl; ++ } ++ else ++ { ++ vcos_vlog_impl_func = vlog_impl_func; ++ } ++} ++ +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/generic/vcos_mem_from_malloc.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/generic/vcos_mem_from_malloc.c 2013-07-26 19:37:11.000000000 +0000 +@@ -0,0 +1,84 @@ ++/* ++ * Copyright (c) 2010-2011 Broadcom. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++/*============================================================================= ++VideoCore OS Abstraction Layer - memory alloc implementation ++=============================================================================*/ ++ ++#include "interface/vcos/vcos.h" ++ ++#ifndef _vcos_platform_malloc ++#include ++#define _vcos_platform_malloc malloc ++#define _vcos_platform_free free ++#endif ++ ++typedef struct malloc_header_s { ++ uint32_t guardword; ++ uint32_t size; ++ const char *description; ++ void *ptr; ++} MALLOC_HEADER_T; ++ ++ ++#define MIN_ALIGN sizeof(MALLOC_HEADER_T) ++ ++#define GUARDWORDHEAP 0xa55a5aa5 ++ ++void *vcos_generic_mem_alloc_aligned(VCOS_UNSIGNED size, VCOS_UNSIGNED align, const char *desc) ++{ ++ int local_align = align == 0 ? 1 : align; ++ int required_size = size + local_align + sizeof(MALLOC_HEADER_T); ++ void *ptr = _vcos_platform_malloc(required_size); ++ void *ret = (void *)VCOS_ALIGN_UP(((char *)ptr)+sizeof(MALLOC_HEADER_T), local_align); ++ MALLOC_HEADER_T *h = ((MALLOC_HEADER_T *)ret)-1; ++ ++ h->size = size; ++ h->description = desc; ++ h->guardword = GUARDWORDHEAP; ++ h->ptr = ptr; ++ ++ return ret; ++} ++ ++void *vcos_generic_mem_alloc(VCOS_UNSIGNED size, const char *desc) ++{ ++ return vcos_generic_mem_alloc_aligned(size,MIN_ALIGN,desc); ++} ++ ++void *vcos_generic_mem_calloc(VCOS_UNSIGNED count, VCOS_UNSIGNED sz, const char *desc) ++{ ++ uint32_t size = count*sz; ++ void *ptr = vcos_generic_mem_alloc_aligned(size,MIN_ALIGN,desc); ++ if (ptr) ++ { ++ memset(ptr, 0, size); ++ } ++ return ptr; ++} ++ ++void vcos_generic_mem_free(void *ptr) ++{ ++ MALLOC_HEADER_T *h; ++ if (! ptr) return; ++ ++ h = ((MALLOC_HEADER_T *)ptr)-1; ++ vcos_assert(h->guardword == GUARDWORDHEAP); ++ _vcos_platform_free(h->ptr); ++} ++ +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/generic/vcos_mem_from_malloc.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/generic/vcos_mem_from_malloc.h 2013-07-26 19:37:11.000000000 +0000 +@@ -0,0 +1,65 @@ ++/* ++ * Copyright (c) 2010-2011 Broadcom. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++/*============================================================================= ++Create the vcos_malloc API from the regular system malloc/free ++=============================================================================*/ ++ ++/** ++ * \file ++ * ++ * Create the vcos malloc API from a regular system malloc/free library. ++ * ++ * The API lets callers specify an alignment. ++ * ++ * Under VideoCore this is not needed, as we can simply use the rtos_malloc routines. ++ * But on host platforms that won't be the case. ++ * ++ */ ++ ++VCOSPRE_ void * VCOSPOST_ vcos_generic_mem_alloc(VCOS_UNSIGNED sz, const char *desc); ++VCOSPRE_ void * VCOSPOST_ vcos_generic_mem_calloc(VCOS_UNSIGNED count, VCOS_UNSIGNED sz, const char *descr); ++VCOSPRE_ void VCOSPOST_ vcos_generic_mem_free(void *ptr); ++VCOSPRE_ void * VCOSPOST_ vcos_generic_mem_alloc_aligned(VCOS_UNSIGNED sz, VCOS_UNSIGNED align, const char *desc); ++ ++#ifdef VCOS_INLINE_BODIES ++ ++VCOS_INLINE_IMPL ++void *vcos_malloc(VCOS_UNSIGNED size, const char *description) { ++ return vcos_generic_mem_alloc(size, description); ++} ++ ++VCOS_INLINE_IMPL ++void *vcos_calloc(VCOS_UNSIGNED num, VCOS_UNSIGNED size, const char *description) { ++ return vcos_generic_mem_calloc(num, size, description); ++} ++ ++VCOS_INLINE_IMPL ++void vcos_free(void *ptr) { ++ vcos_generic_mem_free(ptr); ++} ++ ++VCOS_INLINE_IMPL ++void * vcos_malloc_aligned(VCOS_UNSIGNED size, VCOS_UNSIGNED align, const char *description) { ++ return vcos_generic_mem_alloc_aligned(size, align, description); ++} ++ ++ ++#endif /* VCOS_INLINE_BODIES */ ++ ++ +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/generic/vcos_mutexes_are_reentrant.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/generic/vcos_mutexes_are_reentrant.h 2013-07-26 19:37:11.000000000 +0000 +@@ -0,0 +1,79 @@ ++/* ++ * Copyright (c) 2010-2011 Broadcom. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++/*============================================================================= ++VideoCore OS Abstraction Layer - reentrant mutexes mapped directly to regular ones ++=============================================================================*/ ++ ++#ifndef VCOS_GENERIC_REENTRANT_MUTEX_H ++#define VCOS_GENERIC_REENTRANT_MUTEX_H ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++#include "interface/vcos/vcos_types.h" ++#include "interface/vcos/vcos_mutex.h" ++ ++/** ++ * \file ++ * ++ * Reentrant Mutexes directly using the native re-entrant mutex. ++ * ++ */ ++ ++typedef VCOS_MUTEX_T VCOS_REENTRANT_MUTEX_T; ++ ++/* Inline forwarding functions */ ++ ++#if defined(VCOS_INLINE_BODIES) ++ ++VCOS_INLINE_IMPL ++VCOS_STATUS_T vcos_reentrant_mutex_create(VCOS_REENTRANT_MUTEX_T *m, const char *name) { ++ return vcos_mutex_create(m,name); ++} ++ ++VCOS_INLINE_IMPL ++void vcos_reentrant_mutex_delete(VCOS_REENTRANT_MUTEX_T *m) { ++ vcos_mutex_delete(m); ++} ++ ++VCOS_INLINE_IMPL ++void vcos_reentrant_mutex_lock(VCOS_REENTRANT_MUTEX_T *m) { ++ vcos_mutex_lock(m); ++} ++ ++VCOS_INLINE_IMPL ++void vcos_reentrant_mutex_unlock(VCOS_REENTRANT_MUTEX_T *m) { ++ vcos_mutex_unlock(m); ++} ++ ++VCOS_INLINE_IMPL ++int vcos_reentrant_mutex_is_locked(VCOS_REENTRANT_MUTEX_T *m) { ++ return vcos_mutex_is_locked(m); ++} ++ ++#endif ++ ++#ifdef __cplusplus ++} ++#endif ++#endif ++ ++ ++ +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/generic/vcos_thread_reaper.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/generic/vcos_thread_reaper.h 2013-07-26 19:37:11.000000000 +0000 +@@ -0,0 +1,46 @@ ++/* ++ * Copyright (c) 2010-2011 Broadcom. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++/*============================================================================= ++VideoCore OS Abstraction Layer - thread reaping ++=============================================================================*/ ++ ++#ifndef VCOS_THREAD_REAPER_H ++#define VCOS_THREAD_REAPER_H ++ ++#define VCOS_HAVE_THREAD_REAPER ++ ++/** Initialise the thread reaper. ++ */ ++VCOS_STATUS_T vcos_thread_reaper_init(void); ++ ++/** Reap a thread. Arranges for the thread to be automatically ++ * joined. ++ * ++ * @sa vcos_thread_join(). ++ * ++ * @param thread the thread to terminate ++ * @param on_terminated called after the thread has exited ++ * @param cxt pass back to the callback ++ * ++ */ ++void vcos_thread_reap(VCOS_THREAD_T *thread, void (*on_terminated)(void*), void *cxt); ++ ++#endif ++ ++ +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/linuxkernel/stdint.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/linuxkernel/stdint.h 2013-07-26 19:37:11.000000000 +0000 +@@ -0,0 +1,31 @@ ++/* ++ * Copyright (c) 2010-2011 Broadcom. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++/*============================================================================= ++VideoCore OS fAbstraction Layer - stdint.h C standard header ++=============================================================================*/ ++ ++#ifndef _VCOS_PLATFORM_LINUX_STDINT_H ++#define _VCOS_PLATFORM_LINUX_STDINT_H ++ ++/* The Linux kernel does not have a so we have to provide one of ++ our own. */ ++ ++#include /* includes integer types */ ++ ++#endif /* _VCOS_PLATFORM_LINUX_STDINT_H */ +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/linuxkernel/vcos_linuxkernel.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/linuxkernel/vcos_linuxkernel.c 2013-07-26 19:37:11.000000000 +0000 +@@ -0,0 +1,627 @@ ++/* ++ * Copyright (c) 2010-2011 Broadcom. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++/*============================================================================= ++VideoCore OS Abstraction Layer - pthreads types ++=============================================================================*/ ++ ++#define VCOS_INLINE_BODIES ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#if defined( CONFIG_BCM_KNLLOG_SUPPORT ) ++#include ++#endif ++#include "interface/vcos/vcos.h" ++#ifdef HAVE_VCOS_VERSION ++#include "interface/vcos/vcos_build_info.h" ++#endif ++ ++VCOS_CFG_ENTRY_T vcos_cfg_dir; ++VCOS_CFG_ENTRY_T vcos_logging_cfg_dir; ++VCOS_CFG_ENTRY_T vcos_version_cfg; ++ ++#ifndef VCOS_DEFAULT_STACK_SIZE ++#define VCOS_DEFAULT_STACK_SIZE 4096 ++#endif ++ ++static VCOS_THREAD_ATTR_T default_attrs = { ++ 0, ++ VCOS_DEFAULT_STACK_SIZE, ++}; ++ ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,36) ++static DEFINE_SEMAPHORE(lock); ++#else ++static DECLARE_MUTEX(lock); ++#endif ++ ++typedef void (*LEGACY_ENTRY_FN_T)(int, void *); ++ ++/** Wrapper function around the real thread function. Posts the semaphore ++ * when completed. ++ */ ++static int vcos_thread_wrapper(void *arg) ++{ ++ void *ret; ++ VCOS_THREAD_T *thread = arg; ++ ++ vcos_assert(thread->magic == VCOS_THREAD_MAGIC); ++ ++ thread->thread.thread = current; ++ ++ vcos_add_thread(thread); ++ ++#ifdef VCOS_WANT_TLS_EMULATION ++ vcos_tls_thread_register(&thread->_tls); ++#endif ++ ++ if (thread->legacy) ++ { ++ LEGACY_ENTRY_FN_T fn = (LEGACY_ENTRY_FN_T)thread->entry; ++ fn(0,thread->arg); ++ ret = 0; ++ } ++ else ++ { ++ ret = thread->entry(thread->arg); ++ } ++ ++ thread->exit_data = ret; ++ ++ vcos_remove_thread(current); ++ ++ /* For join and cleanup */ ++ vcos_semaphore_post(&thread->wait); ++ ++ return 0; ++} ++ ++VCOS_STATUS_T vcos_thread_create(VCOS_THREAD_T *thread, ++ const char *name, ++ VCOS_THREAD_ATTR_T *attrs, ++ VCOS_THREAD_ENTRY_FN_T entry, ++ void *arg) ++{ ++ VCOS_STATUS_T st; ++ struct task_struct *kthread; ++ ++ memset(thread, 0, sizeof(*thread)); ++ thread->magic = VCOS_THREAD_MAGIC; ++ strlcpy( thread->name, name, sizeof( thread->name )); ++ thread->legacy = attrs ? attrs->legacy : 0; ++ thread->entry = entry; ++ thread->arg = arg; ++ ++ if (!name) ++ { ++ vcos_assert(0); ++ return VCOS_EINVAL; ++ } ++ ++ st = vcos_semaphore_create(&thread->wait, NULL, 0); ++ if (st != VCOS_SUCCESS) ++ { ++ return st; ++ } ++ ++ st = vcos_semaphore_create(&thread->suspend, NULL, 0); ++ if (st != VCOS_SUCCESS) ++ { ++ return st; ++ } ++ ++ /*required for event groups */ ++ vcos_timer_create(&thread->_timer.timer, thread->name, NULL, NULL); ++ ++ kthread = kthread_create((int (*)(void *))vcos_thread_wrapper, (void*)thread, name); ++ vcos_assert(kthread != NULL); ++ set_user_nice(kthread, attrs->ta_priority); ++ thread->thread.thread = kthread; ++ wake_up_process(kthread); ++ return VCOS_SUCCESS; ++} ++ ++void vcos_thread_join(VCOS_THREAD_T *thread, ++ void **pData) ++{ ++ vcos_assert(thread); ++ vcos_assert(thread->magic == VCOS_THREAD_MAGIC); ++ ++ thread->joined = 1; ++ ++ vcos_semaphore_wait(&thread->wait); ++ ++ if (pData) ++ { ++ *pData = thread->exit_data; ++ } ++ ++ /* Clean up */ ++ if (thread->stack) ++ vcos_free(thread->stack); ++ ++ vcos_semaphore_delete(&thread->wait); ++ vcos_semaphore_delete(&thread->suspend); ++ ++} ++ ++uint32_t vcos_getmicrosecs( void ) ++{ ++ struct timeval tv; ++/*XXX FIX ME! switch to ktime_get_ts to use MONOTONIC clock */ ++ do_gettimeofday(&tv); ++ return (tv.tv_sec*1000000) + tv.tv_usec; ++} ++ ++VCOS_STATUS_T vcos_timer_init(void) ++{ ++ return VCOS_SUCCESS; ++} ++ ++static const char *log_prefix[] = ++{ ++ "", /* VCOS_LOG_UNINITIALIZED */ ++ "", /* VCOS_LOG_NEVER */ ++ KERN_ERR, /* VCOS_LOG_ERROR */ ++ KERN_WARNING, /* VCOS_LOG_WARN */ ++ KERN_INFO, /* VCOS_LOG_INFO */ ++ KERN_INFO /* VCOS_LOG_TRACE */ ++}; ++ ++void vcos_vlog_default_impl(const VCOS_LOG_CAT_T *cat, VCOS_LOG_LEVEL_T _level, const char *fmt, va_list args) ++{ ++ char *newline = strchr( fmt, '\n' ); ++ const char *prefix; ++ const char *real_fmt; ++ ++ preempt_disable(); ++ { ++ if ( *fmt == '<' ) ++ { ++ prefix = fmt; ++ real_fmt= &fmt[3]; ++ } ++ else ++ { ++ prefix = log_prefix[_level]; ++ real_fmt = fmt; ++ } ++#if defined( CONFIG_BCM_KNLLOG_SUPPORT ) ++ knllog_ventry( "vcos", real_fmt, args ); ++#endif ++ printk( "%.3svcos: [%d]: ", prefix, current->pid ); ++ vprintk( real_fmt, args ); ++ ++ if ( newline == NULL ) ++ { ++ printk("\n"); ++ } ++ } ++ preempt_enable(); ++} ++ ++ ++const char * _vcos_log_level(void) ++{ ++ return NULL; ++} ++ ++/***************************************************************************** ++* ++* Displays the version information in /proc/vcos/version ++* ++*****************************************************************************/ ++ ++#ifdef HAVE_VCOS_VERSION ++ ++static void show_version( VCOS_CFG_BUF_T buf, void *data ) ++{ ++ static const char* copyright = "Copyright (c) 2011 Broadcom"; ++ ++ vcos_cfg_buf_printf( buf, "Built %s %s on %s\n%s\nversion %s\n", ++ vcos_get_build_date(), ++ vcos_get_build_time(), ++ vcos_get_build_hostname(), ++ copyright, ++ vcos_get_build_version() ); ++} ++ ++#endif ++ ++/***************************************************************************** ++* ++* Initialises vcos ++* ++*****************************************************************************/ ++ ++VCOS_STATUS_T vcos_init(void) ++{ ++ if ( vcos_cfg_mkdir( &vcos_cfg_dir, NULL, "vcos" ) != VCOS_SUCCESS ) ++ { ++ printk( KERN_ERR "%s: Unable to create vcos cfg entry\n", __func__ ); ++ } ++ vcos_logging_init(); ++ ++#ifdef HAVE_VCOS_VERSION ++ if ( vcos_cfg_create_entry( &vcos_version_cfg, &vcos_cfg_dir, "version", ++ show_version, NULL, NULL ) != VCOS_SUCCESS ) ++ { ++ printk( KERN_ERR "%s: Unable to create vcos cfg entry 'version'\n", __func__ ); ++ } ++#endif ++ ++ return VCOS_SUCCESS; ++} ++ ++/***************************************************************************** ++* ++* Deinitializes vcos ++* ++*****************************************************************************/ ++ ++void vcos_deinit(void) ++{ ++#ifdef HAVE_VCOS_VERSION ++ vcos_cfg_remove_entry( &vcos_version_cfg ); ++#endif ++ vcos_cfg_remove_entry( &vcos_cfg_dir ); ++} ++ ++void vcos_global_lock(void) ++{ ++ down(&lock); ++} ++ ++void vcos_global_unlock(void) ++{ ++ up(&lock); ++} ++ ++/* vcos_thread_exit() doesn't really stop this thread here ++ * ++ * At the moment, call to do_exit() will leak task_struct for ++ * current thread, so we let the vcos_thread_wrapper() do the ++ * cleanup and exit job, and we return w/o actually stopping the thread. ++ * ++ * ToDo: Kernel v2.6.31 onwards, it is considered safe to call do_exit() ++ * from kthread, the implementation of which is combined in 2 patches ++ * with commit-ids "63706172" and "cdd140bd" in oss Linux kernel tree ++ */ ++ ++void vcos_thread_exit(void *arg) ++{ ++ VCOS_THREAD_T *thread = vcos_thread_current(); ++ ++ vcos_assert(thread); ++ vcos_assert(thread->magic == VCOS_THREAD_MAGIC); ++ ++ thread->exit_data = arg; ++} ++ ++void vcos_thread_attr_init(VCOS_THREAD_ATTR_T *attrs) ++{ ++ *attrs = default_attrs; ++} ++ ++void _vcos_task_timer_set(void (*pfn)(void *), void *cxt, VCOS_UNSIGNED ms) ++{ ++ VCOS_THREAD_T *self = vcos_thread_current(); ++ vcos_assert(self); ++ vcos_assert(self->_timer.pfn == NULL); ++ ++ vcos_timer_create( &self->_timer.timer, "TaskTimer", pfn, cxt ); ++ vcos_timer_set(&self->_timer.timer, ms); ++} ++ ++void _vcos_task_timer_cancel(void) ++{ ++ VCOS_THREAD_T *self = vcos_thread_current(); ++ if (self->_timer.timer.linux_timer.function) ++ { ++ vcos_timer_cancel(&self->_timer.timer); ++ vcos_timer_delete(&self->_timer.timer); ++ } ++} ++ ++int vcos_vsnprintf( char *buf, size_t buflen, const char *fmt, va_list ap ) ++{ ++ return vsnprintf( buf, buflen, fmt, ap ); ++} ++ ++int vcos_snprintf(char *buf, size_t buflen, const char *fmt, ...) ++{ ++ int ret; ++ va_list ap; ++ va_start(ap,fmt); ++ ret = vsnprintf(buf, buflen, fmt, ap); ++ va_end(ap); ++ return ret; ++} ++ ++int vcos_llthread_running(VCOS_LLTHREAD_T *t) { ++ vcos_assert(0); /* this function only exists as a nasty hack for the video codecs! */ ++ return 1; ++} ++ ++static int vcos_verify_bkpts = 1; ++ ++int vcos_verify_bkpts_enabled(void) ++{ ++ return vcos_verify_bkpts; ++} ++ ++/***************************************************************************** ++* ++* _vcos_log_platform_init is called from vcos_logging_init ++* ++*****************************************************************************/ ++ ++void _vcos_log_platform_init(void) ++{ ++ if ( vcos_cfg_mkdir( &vcos_logging_cfg_dir, &vcos_cfg_dir, "logging" ) != VCOS_SUCCESS ) ++ { ++ printk( KERN_ERR "%s: Unable to create logging cfg entry\n", __func__ ); ++ } ++} ++ ++/***************************************************************************** ++* ++* Called to display the contents of a logging category. ++* ++*****************************************************************************/ ++ ++static void logging_show_category( VCOS_CFG_BUF_T buf, void *data ) ++{ ++ VCOS_LOG_CAT_T *category = data; ++ ++ vcos_cfg_buf_printf( buf, "%s\n", vcos_log_level_to_string( category->level )); ++} ++ ++/***************************************************************************** ++* ++* Called to parse content for a logging category. ++* ++*****************************************************************************/ ++ ++static void logging_parse_category( VCOS_CFG_BUF_T buf, void *data ) ++{ ++ VCOS_LOG_CAT_T *category = data; ++ const char *str = vcos_cfg_buf_get_str( buf ); ++ VCOS_LOG_LEVEL_T level; ++ ++ if ( vcos_string_to_log_level( str, &level ) == VCOS_SUCCESS ) ++ { ++ category->level = level; ++ } ++ else ++ { ++ printk( KERN_ERR "%s: Unrecognized logging level: '%s'\n", ++ __func__, str ); ++ } ++} ++ ++/***************************************************************************** ++* ++* _vcos_log_platform_register is called from vcos_log_register whenever ++* a new category is registered. ++* ++*****************************************************************************/ ++ ++void _vcos_log_platform_register(VCOS_LOG_CAT_T *category) ++{ ++ VCOS_CFG_ENTRY_T entry; ++ ++ if ( vcos_cfg_create_entry( &entry, &vcos_logging_cfg_dir, category->name, ++ logging_show_category, logging_parse_category, ++ category ) != VCOS_SUCCESS ) ++ { ++ printk( KERN_ERR "%s: Unable to create cfg entry for logging category '%s'\n", ++ __func__, category->name ); ++ category->platform_data = NULL; ++ } ++ else ++ { ++ category->platform_data = entry; ++ } ++} ++ ++/***************************************************************************** ++* ++* _vcos_log_platform_unregister is called from vcos_log_unregister whenever ++* a new category is unregistered. ++* ++*****************************************************************************/ ++ ++void _vcos_log_platform_unregister(VCOS_LOG_CAT_T *category) ++{ ++ VCOS_CFG_ENTRY_T entry; ++ ++ entry = category->platform_data; ++ if ( entry != NULL ) ++ { ++ if ( vcos_cfg_remove_entry( &entry ) != VCOS_SUCCESS ) ++ { ++ printk( KERN_ERR "%s: Unable to remove cfg entry for logging category '%s'\n", ++ __func__, category->name ); ++ } ++ } ++} ++ ++/***************************************************************************** ++* ++* Allocate memory. ++* ++*****************************************************************************/ ++ ++void *vcos_platform_malloc( VCOS_UNSIGNED required_size ) ++{ ++ if ( required_size >= ( 2 * PAGE_SIZE )) ++ { ++ /* For larger allocations, use vmalloc, whose underlying allocator ++ * returns pages ++ */ ++ ++ return vmalloc( required_size ); ++ } ++ ++ /* For smaller allocation, use kmalloc */ ++ ++ return kmalloc( required_size, GFP_KERNEL ); ++} ++ ++/***************************************************************************** ++* ++* Free previously allocated memory ++* ++*****************************************************************************/ ++ ++void vcos_platform_free( void *ptr ) ++{ ++ if (((unsigned long)ptr >= VMALLOC_START ) ++ && ((unsigned long)ptr < VMALLOC_END )) ++ { ++ vfree( ptr ); ++ } ++ else ++ { ++ kfree( ptr ); ++ } ++} ++ ++/***************************************************************************** ++* ++* Execute a routine exactly once. ++* ++*****************************************************************************/ ++ ++VCOS_STATUS_T vcos_once(VCOS_ONCE_T *once_control, ++ void (*init_routine)(void)) ++{ ++ /* In order to be thread-safe we need to re-test *once_control ++ * inside the lock. The outer test is basically an optimization ++ * so that once it is initialized we don't need to waste time ++ * trying to acquire the lock. ++ */ ++ ++ if ( *once_control == 0 ) ++ { ++ vcos_global_lock(); ++ if ( *once_control == 0 ) ++ { ++ init_routine(); ++ *once_control = 1; ++ } ++ vcos_global_unlock(); ++ } ++ ++ return VCOS_SUCCESS; ++} ++ ++/***************************************************************************** ++* ++* String duplication routine. ++* ++*****************************************************************************/ ++ ++char *vcos_strdup(const char *str) ++{ ++ return kstrdup(str, GFP_KERNEL); ++} ++ ++ ++/* Export functions for modules to use */ ++EXPORT_SYMBOL( vcos_init ); ++ ++EXPORT_SYMBOL( vcos_semaphore_trywait ); ++EXPORT_SYMBOL( vcos_semaphore_post ); ++EXPORT_SYMBOL( vcos_semaphore_create ); ++EXPORT_SYMBOL( vcos_semaphore_wait ); ++EXPORT_SYMBOL( vcos_semaphore_delete ); ++ ++EXPORT_SYMBOL( vcos_log_impl ); ++EXPORT_SYMBOL( vcos_vlog_impl ); ++EXPORT_SYMBOL( vcos_vlog_default_impl ); ++EXPORT_SYMBOL( vcos_log_get_default_category ); ++EXPORT_SYMBOL( vcos_log_register ); ++EXPORT_SYMBOL( vcos_log_unregister ); ++EXPORT_SYMBOL( vcos_logging_init ); ++EXPORT_SYMBOL( vcos_log_level_to_string ); ++EXPORT_SYMBOL( vcos_string_to_log_level ); ++EXPORT_SYMBOL( vcos_log_dump_mem_impl ); ++ ++EXPORT_SYMBOL( vcos_event_create ); ++EXPORT_SYMBOL( vcos_event_delete ); ++EXPORT_SYMBOL( vcos_event_flags_set ); ++EXPORT_SYMBOL( vcos_event_signal ); ++EXPORT_SYMBOL( vcos_event_wait ); ++EXPORT_SYMBOL( vcos_event_try ); ++ ++EXPORT_SYMBOL( vcos_getmicrosecs ); ++ ++EXPORT_SYMBOL( vcos_strcasecmp ); ++EXPORT_SYMBOL( vcos_snprintf ); ++EXPORT_SYMBOL( vcos_vsnprintf ); ++ ++EXPORT_SYMBOL( vcos_thread_current ); ++EXPORT_SYMBOL( vcos_thread_join ); ++EXPORT_SYMBOL( vcos_thread_create ); ++EXPORT_SYMBOL( vcos_thread_set_priority ); ++EXPORT_SYMBOL( vcos_thread_exit ); ++EXPORT_SYMBOL( vcos_once ); ++ ++EXPORT_SYMBOL( vcos_thread_attr_init ); ++EXPORT_SYMBOL( vcos_thread_attr_setpriority ); ++EXPORT_SYMBOL( vcos_thread_attr_settimeslice ); ++EXPORT_SYMBOL( vcos_thread_attr_setstacksize ); ++EXPORT_SYMBOL( _vcos_thread_attr_setlegacyapi ); ++ ++EXPORT_SYMBOL( vcos_event_flags_create ); ++EXPORT_SYMBOL( vcos_event_flags_delete ); ++EXPORT_SYMBOL( vcos_event_flags_get ); ++ ++EXPORT_SYMBOL( vcos_sleep ); ++ ++EXPORT_SYMBOL( vcos_calloc ); ++EXPORT_SYMBOL( vcos_malloc ); ++EXPORT_SYMBOL( vcos_malloc_aligned ); ++EXPORT_SYMBOL( vcos_free ); ++ ++EXPORT_SYMBOL( vcos_mutex_create ); ++EXPORT_SYMBOL( vcos_mutex_delete ); ++EXPORT_SYMBOL( vcos_mutex_lock ); ++EXPORT_SYMBOL( vcos_mutex_unlock ); ++EXPORT_SYMBOL( vcos_mutex_trylock ); ++ ++EXPORT_SYMBOL( vcos_timer_cancel ); ++EXPORT_SYMBOL( vcos_timer_create ); ++EXPORT_SYMBOL( vcos_timer_delete ); ++EXPORT_SYMBOL( vcos_timer_set ); ++ ++EXPORT_SYMBOL( vcos_atomic_flags_create ); ++EXPORT_SYMBOL( vcos_atomic_flags_delete ); ++EXPORT_SYMBOL( vcos_atomic_flags_or ); ++EXPORT_SYMBOL( vcos_atomic_flags_get_and_clear ); ++ ++EXPORT_SYMBOL( vcos_verify_bkpts_enabled ); ++ ++EXPORT_SYMBOL( vcos_strdup ); +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/linuxkernel/vcos_linuxkernel_cfg.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/linuxkernel/vcos_linuxkernel_cfg.c 2013-07-26 19:37:11.000000000 +0000 +@@ -0,0 +1,332 @@ ++/***************************************************************************** ++* Copyright 2009 - 2010 Broadcom Corporation. All rights reserved. ++* ++* Unless you and Broadcom execute a separate written software license ++* agreement governing use of this software, this software is licensed to you ++* under the terms of the GNU General Public License version 2, available at ++* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). ++* ++* Notwithstanding the above, under no circumstances may you combine this ++* software in any way with any other Broadcom software provided under a ++* license other than the GPL, without Broadcom's express prior written ++* consent. ++*****************************************************************************/ ++ ++#include "interface/vcos/vcos.h" ++#include ++#include ++#include ++#include ++ ++struct opaque_vcos_cfg_buf_t ++{ ++ struct seq_file *seq; ++ char *charBuf; ++}; ++ ++struct opaque_vcos_cfg_entry_t ++{ ++ struct proc_dir_entry *pde; ++ struct proc_dir_entry *parent_pde; ++ VCOS_CFG_SHOW_FPTR showFunc; ++ VCOS_CFG_PARSE_FPTR parseFunc; ++ void *data; ++ const char *name; ++}; ++ ++/***************************************************************************** ++* ++* cfg_proc_show ++* ++*****************************************************************************/ ++ ++static int cfg_proc_show( struct seq_file *s, void *v ) ++{ ++ VCOS_CFG_ENTRY_T entry; ++ struct opaque_vcos_cfg_buf_t buf; ++ ++ entry = s->private; ++ ++ if ( entry->showFunc ) ++ { ++ memset( &buf, 0, sizeof( buf )); ++ buf.seq = s; ++ ++ entry->showFunc( &buf, entry->data ); ++ } ++ ++ return 0; ++} ++ ++/***************************************************************************** ++* ++* cfg_proc_write ++* ++*****************************************************************************/ ++ ++static ssize_t cfg_proc_write( struct file *file, const char __user *buffer, size_t count, loff_t *ppos) ++{ ++ VCOS_CFG_ENTRY_T entry = PDE(file->f_path.dentry->d_inode)->data; ++ char *charBuf; ++ struct opaque_vcos_cfg_buf_t buf; ++ size_t len; ++ ++ if ( entry->parseFunc != NULL ) ++ { ++ /* The number 4000 is rather arbitrary. It just needs to be bigger than any input ++ * string we expect to use. ++ */ ++ ++ len = count; ++ if ( count > 4000 ) ++ { ++ len = 4000; ++ } ++ ++ /* Allocate a kernel buffer to contain the string being written. */ ++ ++ charBuf = kmalloc( len + 1, GFP_KERNEL ); ++ if ( copy_from_user( charBuf, buffer, len )) ++ { ++ kfree( charBuf ); ++ return -EFAULT; ++ } ++ ++ /* echo puts a trailing newline in the buffer - strip it out. */ ++ ++ if (( len > 0 ) && ( charBuf[ len - 1 ] == '\n' )) ++ { ++ len--; ++ } ++ charBuf[len] = '\0'; ++ ++ memset( &buf, 0, sizeof( buf )); ++ buf.charBuf = charBuf; ++ ++ entry->parseFunc( &buf, entry->data ); ++ kfree( charBuf ); ++ } ++ return count; ++} ++ ++/***************************************************************************** ++* ++* cfg_proc_open ++* ++*****************************************************************************/ ++ ++static int cfg_proc_open( struct inode *inode, struct file *file ) ++{ ++ return single_open( file, cfg_proc_show, PDE(inode)->data ); ++} ++ ++static const struct file_operations cfg_proc_fops = ++{ ++ .open = cfg_proc_open, ++ .read = seq_read, ++ .llseek = seq_lseek, ++ .release = single_release, ++ .write = cfg_proc_write, ++}; ++ ++/***************************************************************************** ++* ++* vcos_cfg_mkdir ++* ++*****************************************************************************/ ++ ++VCOS_STATUS_T vcos_cfg_mkdir( VCOS_CFG_ENTRY_T *entryp, ++ VCOS_CFG_ENTRY_T *parent, ++ const char *dirName ) ++{ ++ VCOS_CFG_ENTRY_T entry; ++ ++ if (( entry = kzalloc( sizeof( *entry ), GFP_KERNEL )) == NULL ) ++ { ++ return VCOS_ENOMEM; ++ } ++ ++ if ( parent == NULL ) ++ { ++ entry->pde = proc_mkdir( dirName, NULL ); ++ } ++ else ++ { ++ entry->pde = proc_mkdir( dirName, (*parent)->pde ); ++ entry->parent_pde = (*parent)->pde; ++ } ++ if ( entry->pde == NULL ) ++ { ++ kfree( entry ); ++ return VCOS_ENOMEM; ++ } ++ ++ entry->name = dirName; ++ ++ *entryp = entry; ++ return VCOS_SUCCESS; ++} ++ ++/***************************************************************************** ++* ++* vcos_cfg_create_entry ++* ++*****************************************************************************/ ++ ++VCOS_STATUS_T vcos_cfg_create_entry( VCOS_CFG_ENTRY_T *entryp, ++ VCOS_CFG_ENTRY_T *parent, ++ const char *entryName, ++ VCOS_CFG_SHOW_FPTR showFunc, ++ VCOS_CFG_PARSE_FPTR parseFunc, ++ void *data ) ++{ ++ VCOS_CFG_ENTRY_T entry; ++ mode_t mode; ++ ++ *entryp = NULL; ++ ++ if (( entry = kzalloc( sizeof( *entry ), GFP_KERNEL )) == NULL ) ++ { ++ return VCOS_ENOMEM; ++ } ++ ++ mode = 0; ++ if ( showFunc != NULL ) ++ { ++ mode |= 0444; ++ } ++ if ( parseFunc != NULL ) ++ { ++ mode |= 0200; ++ } ++ ++ if ( parent == NULL ) ++ { ++ entry->pde = create_proc_entry( entryName, mode, NULL ); ++ } ++ else ++ { ++ entry->pde = create_proc_entry( entryName, mode, (*parent)->pde ); ++ entry->parent_pde = (*parent)->pde; ++ } ++ if ( entry->pde == NULL ) ++ { ++ kfree( entry ); ++ return -ENOMEM; ++ } ++ entry->showFunc = showFunc; ++ entry->parseFunc = parseFunc; ++ entry->data = data; ++ entry->name = entryName; ++ ++ entry->pde->data = entry; ++ entry->pde->proc_fops = &cfg_proc_fops; ++ ++ *entryp = entry; ++ return VCOS_SUCCESS; ++} ++ ++/***************************************************************************** ++* ++* vcos_cfg_remove_entry ++* ++*****************************************************************************/ ++ ++VCOS_STATUS_T vcos_cfg_remove_entry( VCOS_CFG_ENTRY_T *entryp ) ++{ ++ if (( entryp != NULL ) && ( *entryp != NULL )) ++ { ++ remove_proc_entry( (*entryp)->name, (*entryp)->parent_pde ); ++ ++ kfree( *entryp ); ++ *entryp = NULL; ++ } ++ ++ return VCOS_SUCCESS; ++} ++ ++/***************************************************************************** ++* ++* vcos_cfg_is_entry_created ++* ++*****************************************************************************/ ++ ++int vcos_cfg_is_entry_created( VCOS_CFG_ENTRY_T entry ) ++{ ++ return ( entry != NULL ) && ( entry->pde != NULL ); ++} ++ ++/***************************************************************************** ++* ++* vcos_cfg_buf_printf ++* ++*****************************************************************************/ ++ ++void vcos_cfg_buf_printf( VCOS_CFG_BUF_T buf, const char *fmt, ... ) ++{ ++ struct seq_file *m = buf->seq; ++ ++ /* Bah - there is no seq_vprintf */ ++ ++ va_list args; ++ int len; ++ ++ if (m->count < m->size) { ++ va_start(args, fmt); ++ len = vsnprintf(m->buf + m->count, m->size - m->count, fmt, args); ++ va_end(args); ++ if (m->count + len < m->size) { ++ m->count += len; ++ return; ++ } ++ } ++ m->count = m->size; ++} ++ ++/***************************************************************************** ++* ++* vcos_cfg_buf_get_str ++* ++*****************************************************************************/ ++ ++char *vcos_cfg_buf_get_str( VCOS_CFG_BUF_T buf ) ++{ ++ return buf->charBuf; ++} ++ ++/***************************************************************************** ++* ++* vcos_cfg_get_proc_entry ++* ++* This function is only created for a couple of backwards compatibility ' ++* issues and shouldn't normally be used. ++* ++*****************************************************************************/ ++ ++void *vcos_cfg_get_proc_entry( VCOS_CFG_ENTRY_T entry ) ++{ ++ return entry->pde; ++} ++ ++/***************************************************************************** ++* ++* vcos_cfg_get_entry_name ++* ++*****************************************************************************/ ++ ++const char *vcos_cfg_get_entry_name( VCOS_CFG_ENTRY_T entry ) ++{ ++ return entry->pde->name; ++} ++ ++ ++EXPORT_SYMBOL( vcos_cfg_mkdir ); ++EXPORT_SYMBOL( vcos_cfg_create_entry ); ++EXPORT_SYMBOL( vcos_cfg_remove_entry ); ++EXPORT_SYMBOL( vcos_cfg_get_entry_name ); ++EXPORT_SYMBOL( vcos_cfg_is_entry_created ); ++EXPORT_SYMBOL( vcos_cfg_buf_printf ); ++EXPORT_SYMBOL( vcos_cfg_buf_get_str ); ++ ++EXPORT_SYMBOL_GPL( vcos_cfg_get_proc_entry ); ++ +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/linuxkernel/vcos_linuxkernel_misc.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/linuxkernel/vcos_linuxkernel_misc.c 2013-07-26 19:37:11.000000000 +0000 +@@ -0,0 +1,111 @@ ++/***************************************************************************** ++* Copyright 2009 - 2010 Broadcom Corporation. All rights reserved. ++* ++* Unless you and Broadcom execute a separate written software license ++* agreement governing use of this software, this software is licensed to you ++* under the terms of the GNU General Public License version 2, available at ++* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). ++* ++* Notwithstanding the above, under no circumstances may you combine this ++* software in any way with any other Broadcom software provided under a ++* license other than the GPL, without Broadcom's express prior written ++* consent. ++*****************************************************************************/ ++ ++#include "interface/vcos/vcos.h" ++#include ++#include ++#include ++#include ++#include ++ ++/***************************************************************************** ++* ++* vcos_semaphore_wait_freezable ++* ++*****************************************************************************/ ++ ++VCOS_STATUS_T vcos_semaphore_wait_freezable(VCOS_SEMAPHORE_T *sem) ++{ ++ int rval, sig_pended = 0; ++ unsigned long flags; ++ struct task_struct *task = current; ++ ++ while (1) { ++ rval = down_interruptible((struct semaphore *)sem); ++ if (rval == 0) { /* down now */ ++ break; ++ } else { ++ if (freezing(current)) { ++ try_to_freeze(); ++ } else { ++ spin_lock_irqsave(&task->sighand->siglock, flags); ++ if (test_tsk_thread_flag(task, TIF_SIGPENDING)) { ++ clear_tsk_thread_flag(task, TIF_SIGPENDING); ++ sig_pended = 1; ++ } ++ spin_unlock_irqrestore(&task->sighand->siglock, flags); ++ } ++ } ++ } ++ ++ if (sig_pended) { ++ spin_lock_irqsave(&task->sighand->siglock, flags); ++ set_tsk_thread_flag(task, TIF_SIGPENDING); ++ spin_unlock_irqrestore(&task->sighand->siglock, flags); ++ } ++ ++ return 0; ++} ++ ++EXPORT_SYMBOL( vcos_semaphore_wait_freezable ); ++ ++/***************************************************************************** ++* ++* vcos_kmalloc ++* ++* We really need to convert malloc to do kmalloc or vmalloc based on the ++* size, but for now we'll add a separate function. ++* ++*****************************************************************************/ ++ ++void *vcos_kmalloc(VCOS_UNSIGNED size, const char *description) ++{ ++ (void)description; ++ ++ return kmalloc( size, GFP_KERNEL ); ++} ++ ++/***************************************************************************** ++* ++* vcos_kmalloc ++* ++* We really need to convert malloc to do kmalloc or vmalloc based on the ++* size, but for now we'll add a separate function. ++* ++*****************************************************************************/ ++ ++void *vcos_kcalloc(VCOS_UNSIGNED num, VCOS_UNSIGNED size, const char *description) ++{ ++ (void)description; ++ ++ return kzalloc( num * size, GFP_KERNEL ); ++} ++ ++/***************************************************************************** ++* ++* vcos_kfree ++* ++*****************************************************************************/ ++ ++void vcos_kfree(void *ptr) ++{ ++ kfree( ptr ); ++} ++ ++EXPORT_SYMBOL( vcos_kmalloc ); ++EXPORT_SYMBOL( vcos_kcalloc ); ++EXPORT_SYMBOL( vcos_kfree ); ++ ++// END ######################################################################### ++// ############################################################################# +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/linuxkernel/vcos_mod_init.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/linuxkernel/vcos_mod_init.c 2013-07-26 19:37:11.000000000 +0000 +@@ -0,0 +1,64 @@ ++/***************************************************************************** ++* Copyright 2006 - 2008 Broadcom Corporation. All rights reserved. ++* ++* Unless you and Broadcom execute a separate written software license ++* agreement governing use of this software, this software is licensed to you ++* under the terms of the GNU General Public License version 2, available at ++* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). ++* ++* Notwithstanding the above, under no circumstances may you combine this ++* software in any way with any other Broadcom software provided under a ++* license other than the GPL, without Broadcom's express prior written ++* consent. ++****************************************************************************/ ++ ++/* ---- Include Files ---------------------------------------------------- */ ++ ++#include "interface/vcos/vcos.h" ++#include ++ ++/* ---- Public Variables ------------------------------------------------- */ ++ ++/* ---- Private Constants and Types -------------------------------------- */ ++ ++/* ---- Private Variables ------------------------------------------------ */ ++ ++/* ---- Private Function Prototypes -------------------------------------- */ ++ ++/* ---- Functions -------------------------------------------------------- */ ++ ++/**************************************************************************** ++* ++* Called to perform module initialization when the module is loaded ++* ++***************************************************************************/ ++ ++static int __init vcos_mod_init( void ) ++{ ++ printk( KERN_INFO "VCOS Module\n" ); ++ ++ vcos_init(); ++ return 0; ++} ++ ++/**************************************************************************** ++* ++* Called to perform module cleanup when the module is unloaded. ++* ++***************************************************************************/ ++ ++static void __exit vcos_mod_exit( void ) ++{ ++ vcos_deinit(); ++} ++ ++/****************************************************************************/ ++ ++module_init( vcos_mod_init ); ++module_exit( vcos_mod_exit ); ++ ++MODULE_AUTHOR("Broadcom"); ++MODULE_DESCRIPTION( "VCOS Module Functions" ); ++MODULE_LICENSE( "GPL" ); ++MODULE_VERSION( "1.0" ); ++ +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/linuxkernel/vcos_platform.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/linuxkernel/vcos_platform.h 2013-07-26 19:37:11.000000000 +0000 +@@ -0,0 +1,507 @@ ++/* ++ * Copyright (c) 2010-2011 Broadcom. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++/*============================================================================= ++VideoCore OS Abstraction Layer - Linux kernel (partial) implementation. ++=============================================================================*/ ++ ++/* Do not include this file directly - instead include it via vcos.h */ ++ ++/** @file ++ * ++ * Linux kernel (partial) implementation of VCOS. ++ * ++ */ ++ ++#ifndef VCOS_PLATFORM_H ++#define VCOS_PLATFORM_H ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include /* for time_t */ ++#include ++#include ++ ++#define VCOS_HAVE_RTOS 1 ++#define VCOS_HAVE_SEMAPHORE 1 ++#define VCOS_HAVE_EVENT 1 ++#define VCOS_HAVE_QUEUE 0 ++#define VCOS_HAVE_LEGACY_ISR 0 ++#define VCOS_HAVE_TIMER 1 ++#define VCOS_HAVE_CANCELLATION_SAFE_TIMER 0 ++#define VCOS_HAVE_MEMPOOL 0 ++#define VCOS_HAVE_ISR 0 ++#define VCOS_HAVE_ATOMIC_FLAGS 1 ++#define VCOS_HAVE_BLOCK_POOL 0 ++#define VCOS_HAVE_ONCE 1 ++#define VCOS_HAVE_FILE 0 ++#define VCOS_HAVE_USER_BUF 0 ++#define VCOS_HAVE_CFG 1 ++#define VCOS_HAVE_SPINLOCK 0 ++#define VCOS_HAVE_CMD 1 ++#define VCOS_HAVE_EVENT_FLAGS 1 ++ ++/* Exclude many VCOS classes which don't have predicates */ ++#define VCOS_TLS_H ++#define VCOS_NAMED_MUTEX_H ++#define VCOS_REENTRANT_MUTEX_H ++#define VCOS_NAMED_SEMAPHORE_H ++#define VCOS_QUICKSLOW_MUTEX_H ++/*#define VCOS_INIT_H */ ++/*#define VCOS_MEM_H */ ++/*#define VCOS_STRING_H */ ++ ++typedef struct semaphore VCOS_SEMAPHORE_T; ++typedef struct semaphore VCOS_EVENT_T; ++typedef struct mutex VCOS_MUTEX_T; ++typedef volatile int VCOS_ONCE_T; ++ ++typedef unsigned int VCOS_UNSIGNED; ++typedef unsigned int VCOS_OPTION; ++typedef atomic_t VCOS_ATOMIC_FLAGS_T; ++ ++typedef struct ++{ ++ struct timer_list linux_timer; ++ void *context; ++ void (*expiration_routine)(void *context); ++ ++} VCOS_TIMER_T; ++ ++typedef struct VCOS_LLTHREAD_T ++{ ++ struct task_struct *thread; /**< The thread itself */ ++ VCOS_SEMAPHORE_T suspend; /**< For support event groups and similar - a per thread semaphore */ ++} VCOS_LLTHREAD_T; ++ ++typedef enum ++{ ++ VCOS_O_RDONLY = 00000000, ++ VCOS_O_WRONLY = 00000001, ++ VCOS_O_RDWR = 00000002, ++ VCOS_O_TRUNC = 00001000, ++} VCOS_FILE_FLAGS_T; ++ ++typedef struct file *VCOS_FILE_T; ++ ++#define VCOS_SUSPEND -1 ++#define VCOS_NO_SUSPEND 0 ++ ++#define VCOS_START 1 ++#define VCOS_NO_START 0 ++ ++#define VCOS_THREAD_PRI_MIN -20 ++#define VCOS_THREAD_PRI_MAX 19 ++ ++#define VCOS_THREAD_PRI_INCREASE -1 ++#define VCOS_THREAD_PRI_HIGHEST VCOS_THREAD_PRI_MIN ++#define VCOS_THREAD_PRI_LOWEST VCOS_THREAD_PRI_MAX ++#define VCOS_THREAD_PRI_NORMAL ((VCOS_THREAD_PRI_MAX+VCOS_THREAD_PRI_MIN)/2) ++#define VCOS_THREAD_PRI_ABOVE_NORMAL (VCOS_THREAD_PRI_NORMAL + VCOS_THREAD_PRI_INCREASE) ++#define VCOS_THREAD_PRI_REALTIME VCOS_THREAD_PRI_HIGHEST ++ ++#define _VCOS_AFFINITY_DEFAULT 0 ++#define _VCOS_AFFINITY_CPU0 0 ++#define _VCOS_AFFINITY_CPU1 0 ++#define _VCOS_AFFINITY_MASK 0 ++#define VCOS_CAN_SET_STACK_ADDR 0 ++ ++#define VCOS_TICKS_PER_SECOND HZ ++ ++#include "interface/vcos/generic/vcos_generic_event_flags.h" ++#include "interface/vcos/generic/vcos_mem_from_malloc.h" ++#include "interface/vcos/generic/vcos_joinable_thread_from_plain.h" ++ ++/*********************************************************** ++ * ++ * Memory allcoation ++ * ++ ***********************************************************/ ++ ++#define _vcos_platform_malloc vcos_platform_malloc ++#define _vcos_platform_free vcos_platform_free ++ ++void *vcos_platform_malloc( VCOS_UNSIGNED required_size ); ++void vcos_platform_free( void *ptr ); ++ ++#if defined(VCOS_INLINE_BODIES) ++ ++#undef VCOS_ASSERT_LOGGING_DISABLE ++#define VCOS_ASSERT_LOGGING_DISABLE 1 ++ ++/*********************************************************** ++ * ++ * Counted Semaphores ++ * ++ ***********************************************************/ ++ ++VCOS_INLINE_IMPL ++VCOS_STATUS_T vcos_semaphore_wait(VCOS_SEMAPHORE_T *sem) { ++ int ret = down_interruptible(sem); ++ if ( ret == 0 ) ++ /* Success */ ++ return VCOS_SUCCESS; ++ else if ( ret == -EINTR ) ++ /* Interrupted */ ++ return VCOS_EINTR; ++ else ++ /* Default (timeout) */ ++ return VCOS_EAGAIN; ++} ++ ++VCOS_INLINE_IMPL ++VCOS_STATUS_T vcos_semaphore_trywait(VCOS_SEMAPHORE_T *sem) { ++ if (down_trylock(sem) != 0) ++ return VCOS_EAGAIN; ++ return VCOS_SUCCESS; ++} ++ ++VCOS_INLINE_IMPL ++VCOS_STATUS_T vcos_semaphore_create(VCOS_SEMAPHORE_T *sem, ++ const char *name, ++ VCOS_UNSIGNED initial_count) { ++ sema_init(sem, initial_count); ++ return VCOS_SUCCESS; ++} ++ ++VCOS_INLINE_IMPL ++void vcos_semaphore_delete(VCOS_SEMAPHORE_T *sem) { ++} ++ ++VCOS_INLINE_IMPL ++VCOS_STATUS_T vcos_semaphore_post(VCOS_SEMAPHORE_T *sem) { ++ up(sem); ++ return VCOS_SUCCESS; ++} ++ ++/*********************************************************** ++ * ++ * Threads ++ * ++ ***********************************************************/ ++ ++#include "vcos_thread_map.h" ++ ++VCOS_INLINE_IMPL ++VCOS_LLTHREAD_T *vcos_llthread_current(void) { ++ return &vcos_kthread_current()->thread; ++} ++ ++VCOS_INLINE_IMPL ++void vcos_llthread_resume(VCOS_LLTHREAD_T *thread) { ++ vcos_assert(0); ++} ++ ++VCOS_INLINE_IMPL ++void vcos_sleep(uint32_t ms) { ++ msleep(ms); ++} ++ ++VCOS_INLINE_IMPL ++void vcos_thread_set_priority(VCOS_THREAD_T *thread, VCOS_UNSIGNED p) { ++ /* not implemented */ ++} ++VCOS_INLINE_IMPL ++VCOS_UNSIGNED vcos_thread_get_priority(VCOS_THREAD_T *thread) { ++ /* not implemented */ ++ return 0; ++} ++ ++/*********************************************************** ++ * ++ * Miscellaneous ++ * ++ ***********************************************************/ ++ ++VCOS_INLINE_IMPL ++int vcos_strcasecmp(const char *s1, const char *s2) { ++ return strcasecmp(s1,s2); ++} ++ ++ ++/*********************************************************** ++ * ++ * Mutexes ++ * ++ ***********************************************************/ ++ ++VCOS_INLINE_IMPL ++VCOS_STATUS_T vcos_mutex_create(VCOS_MUTEX_T *m, const char *name) { ++ mutex_init(m); ++ return VCOS_SUCCESS; ++} ++ ++VCOS_INLINE_IMPL ++void vcos_mutex_delete(VCOS_MUTEX_T *m) { ++} ++ ++VCOS_INLINE_IMPL ++VCOS_STATUS_T vcos_mutex_lock(VCOS_MUTEX_T *m) { ++ int ret = mutex_lock_interruptible(m); ++ if ( ret == 0 ) ++ /* Success */ ++ return VCOS_SUCCESS; ++ else if ( ret == -EINTR ) ++ /* Interrupted */ ++ return VCOS_EINTR; ++ else ++ /* Default */ ++ return VCOS_EAGAIN; ++} ++ ++VCOS_INLINE_IMPL ++void vcos_mutex_unlock(VCOS_MUTEX_T *m) { ++ mutex_unlock(m); ++} ++ ++VCOS_INLINE_IMPL ++int vcos_mutex_is_locked(VCOS_MUTEX_T *m) { ++ if (mutex_trylock(m) != 0) ++ return 1; /* it was locked */ ++ mutex_unlock(m); ++ /* it wasn't locked */ ++ return 0; ++} ++ ++VCOS_INLINE_IMPL ++VCOS_STATUS_T vcos_mutex_trylock(VCOS_MUTEX_T *m) { ++ if (mutex_trylock(m) == 0) ++ return VCOS_SUCCESS; ++ else ++ return VCOS_EAGAIN; ++} ++ ++/* For supporting event groups - per thread semaphore */ ++VCOS_INLINE_IMPL ++void _vcos_thread_sem_wait(void) { ++ VCOS_THREAD_T *t = vcos_thread_current(); ++ vcos_semaphore_wait(&t->suspend); ++} ++ ++VCOS_INLINE_IMPL ++void _vcos_thread_sem_post(VCOS_THREAD_T *target) { ++ vcos_semaphore_post(&target->suspend); ++} ++ ++/*********************************************************** ++ * ++ * Events ++ * ++ ***********************************************************/ ++ ++VCOS_INLINE_IMPL ++VCOS_STATUS_T vcos_event_create(VCOS_EVENT_T *event, const char *debug_name) ++{ ++ sema_init(event, 0); ++ return VCOS_SUCCESS; ++} ++ ++VCOS_INLINE_IMPL ++void vcos_event_signal(VCOS_EVENT_T *event) ++{ ++ up(event); ++} ++ ++VCOS_INLINE_IMPL ++VCOS_STATUS_T vcos_event_wait(VCOS_EVENT_T *event) ++{ ++ int ret = down_interruptible(event); ++ if ( ret == -EINTR ) ++ /* Interrupted */ ++ return VCOS_EINTR; ++ else if (ret != 0) ++ /* Default (timeout) */ ++ return VCOS_EAGAIN; ++ /* Emulate a maximum count of 1 by removing any extra upness */ ++ while (down_trylock(event) == 0) continue; ++ return VCOS_SUCCESS; ++} ++ ++VCOS_INLINE_DECL ++VCOS_STATUS_T vcos_event_try(VCOS_EVENT_T *event) ++{ ++ return (down_trylock(event) == 0) ? VCOS_SUCCESS : VCOS_EAGAIN; ++} ++ ++VCOS_INLINE_IMPL ++void vcos_event_delete(VCOS_EVENT_T *event) ++{ ++} ++ ++/*********************************************************** ++ * ++ * Timers ++ * ++ ***********************************************************/ ++ ++VCOS_INLINE_DECL ++void vcos_timer_linux_func(unsigned long data) ++{ ++ VCOS_TIMER_T *vcos_timer = (VCOS_TIMER_T *)data; ++ ++ vcos_timer->expiration_routine( vcos_timer->context ); ++} ++ ++VCOS_INLINE_DECL ++VCOS_STATUS_T vcos_timer_create(VCOS_TIMER_T *timer, ++ const char *name, ++ void (*expiration_routine)(void *context), ++ void *context) { ++ init_timer(&timer->linux_timer); ++ timer->linux_timer.data = (unsigned long)timer; ++ timer->linux_timer.function = vcos_timer_linux_func; ++ ++ timer->context = context; ++ timer->expiration_routine = expiration_routine; ++ ++ return VCOS_SUCCESS; ++} ++ ++VCOS_INLINE_IMPL ++void vcos_timer_set(VCOS_TIMER_T *timer, VCOS_UNSIGNED delay_ms) { ++ timer->linux_timer.expires = jiffies + msecs_to_jiffies(delay_ms); ++ add_timer(&timer->linux_timer); ++} ++ ++VCOS_INLINE_IMPL ++void vcos_timer_cancel(VCOS_TIMER_T *timer) { ++ del_timer(&timer->linux_timer); ++} ++ ++VCOS_INLINE_IMPL ++void vcos_timer_reset(VCOS_TIMER_T *timer, VCOS_UNSIGNED delay_ms) { ++ del_timer_sync(&timer->linux_timer); ++ timer->linux_timer.expires = jiffies + msecs_to_jiffies(delay_ms); ++ add_timer(&timer->linux_timer); ++} ++ ++VCOS_INLINE_IMPL ++void vcos_timer_delete(VCOS_TIMER_T *timer) { ++ timer->context = NULL; ++ timer->expiration_routine = NULL; ++ timer->linux_timer.function = NULL; ++ timer->linux_timer.data = 0; ++ return; ++} ++ ++VCOS_INLINE_IMPL ++VCOS_UNSIGNED vcos_process_id_current(void) { ++ return (VCOS_UNSIGNED)current->pid; ++} ++ ++ ++VCOS_INLINE_IMPL ++int vcos_in_interrupt(void) { ++ return in_interrupt(); ++} ++ ++/*********************************************************** ++ * ++ * Atomic flags ++ * ++ ***********************************************************/ ++ ++VCOS_INLINE_IMPL ++VCOS_STATUS_T vcos_atomic_flags_create(VCOS_ATOMIC_FLAGS_T *atomic_flags) ++{ ++ atomic_set(atomic_flags, 0); ++ return VCOS_SUCCESS; ++} ++ ++VCOS_INLINE_IMPL ++void vcos_atomic_flags_or(VCOS_ATOMIC_FLAGS_T *atomic_flags, uint32_t flags) ++{ ++ uint32_t value; ++ do { ++ value = atomic_read(atomic_flags); ++ } while (atomic_cmpxchg(atomic_flags, value, value | flags) != value); ++} ++ ++VCOS_INLINE_IMPL ++uint32_t vcos_atomic_flags_get_and_clear(VCOS_ATOMIC_FLAGS_T *atomic_flags) ++{ ++ return atomic_xchg(atomic_flags, 0); ++} ++ ++VCOS_INLINE_IMPL ++void vcos_atomic_flags_delete(VCOS_ATOMIC_FLAGS_T *atomic_flags) ++{ ++} ++ ++#undef VCOS_ASSERT_LOGGING_DISABLE ++#define VCOS_ASSERT_LOGGING_DISABLE 0 ++ ++#endif /* VCOS_INLINE_BODIES */ ++ ++VCOS_INLINE_DECL void _vcos_thread_sem_wait(void); ++VCOS_INLINE_DECL void _vcos_thread_sem_post(VCOS_THREAD_T *); ++ ++/*********************************************************** ++ * ++ * Misc ++ * ++ ***********************************************************/ ++VCOS_INLINE_DECL char *vcos_strdup(const char *str); ++ ++/*********************************************************** ++ * ++ * Logging ++ * ++ ***********************************************************/ ++ ++VCOSPRE_ const char * VCOSPOST_ _vcos_log_level(void); ++#define _VCOS_LOG_LEVEL() _vcos_log_level() ++ ++#define vcos_log_platform_init() _vcos_log_platform_init() ++#define vcos_log_platform_register(category) _vcos_log_platform_register(category) ++#define vcos_log_platform_unregister(category) _vcos_log_platform_unregister(category) ++ ++struct VCOS_LOG_CAT_T; /* Forward declaration since vcos_logging.h hasn't been included yet */ ++ ++void _vcos_log_platform_init(void); ++void _vcos_log_platform_register(struct VCOS_LOG_CAT_T *category); ++void _vcos_log_platform_unregister(struct VCOS_LOG_CAT_T *category); ++ ++/*********************************************************** ++ * ++ * Memory barriers ++ * ++ ***********************************************************/ ++ ++#define vcos_wmb(x) wmb() ++#define vcos_rmb() rmb() ++ ++#include "interface/vcos/generic/vcos_common.h" ++/*#include "interface/vcos/generic/vcos_generic_quickslow_mutex.h" */ ++ ++#endif /* VCOS_PLATFORM_H */ ++ +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/linuxkernel/vcos_platform_types.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/linuxkernel/vcos_platform_types.h 2013-07-26 19:37:11.000000000 +0000 +@@ -0,0 +1,59 @@ ++/* ++ * Copyright (c) 2010-2011 Broadcom. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++/*============================================================================= ++VideoCore OS Abstraction Layer - platform-specific types and defines ++=============================================================================*/ ++ ++#ifndef VCOS_PLATFORM_TYPES_H ++#define VCOS_PLATFORM_TYPES_H ++ ++#include ++#include ++#include ++#include ++ ++#define VCOSPRE_ extern ++#define VCOSPOST_ ++ ++#if defined(__GNUC__) && (( __GNUC__ > 2 ) || (( __GNUC__ == 2 ) && ( __GNUC_MINOR__ >= 3 ))) ++#define VCOS_FORMAT_ATTR_(ARCHETYPE, STRING_INDEX, FIRST_TO_CHECK) __attribute__ ((format (ARCHETYPE, STRING_INDEX, FIRST_TO_CHECK))) ++#else ++#define VCOS_FORMAT_ATTR_(ARCHETYPE, STRING_INDEX, FIRST_TO_CHECK) ++#endif ++ ++#if !defined( __STDC_VERSION__ ) ++#define __STDC_VERSION__ 199901L ++#endif ++ ++#if !defined( __STDC_VERSION ) ++#define __STDC_VERSION __STDC_VERSION__ ++#endif ++ ++static inline void __vcos_bkpt( void ) { BUG(); } ++#define VCOS_BKPT __vcos_bkpt() ++ ++#define VCOS_ASSERT_MSG(...) printk( KERN_ERR "vcos_assert: " __VA_ARGS__ ) ++ ++#define PRId64 "lld" ++#define PRIi64 "lli" ++#define PRIo64 "llo" ++#define PRIu64 "llu" ++#define PRIx64 "llx" ++ ++#endif +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/linuxkernel/vcos_thread_map.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/linuxkernel/vcos_thread_map.c 2013-07-26 19:37:11.000000000 +0000 +@@ -0,0 +1,129 @@ ++/***************************************************************************** ++* Copyright 2009 - 2010 Broadcom Corporation. All rights reserved. ++* ++* Unless you and Broadcom execute a separate written software license ++* agreement governing use of this software, this software is licensed to you ++* under the terms of the GNU General Public License version 2, available at ++* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). ++* ++* Notwithstanding the above, under no circumstances may you combine this ++* software in any way with any other Broadcom software provided under a ++* license other than the GPL, without Broadcom's express prior written ++* consent. ++*****************************************************************************/ ++ ++/** Support to allow VCOS thread-related functions to be called from ++ * threads that were not created by VCOS. ++ */ ++ ++#include ++#include ++#include ++#include ++ ++#include "vcos_thread_map.h" ++#include "interface/vcos/vcos_logging.h" ++ ++/* ++ * Store the vcos_thread pointer at the end of ++ * current kthread stack, right after the thread_info ++ * structure. ++ * ++ * I belive we should be safe here to steal these 4 bytes ++ * from the stack, as long as the vcos thread does not use up ++ * all the stack available ++ * ++ * NOTE: This scheme will not work on architectures with stack growing up ++ */ ++ ++/* Shout, if we are not being compiled for ARM kernel */ ++ ++#ifndef CONFIG_ARM ++#error " **** The vcos kthread implementation may not work for non-ARM kernel ****" ++#endif ++ ++static inline void *to_current_vcos_thread(void) ++{ ++ unsigned long *vcos_data; ++ ++ vcos_data = (unsigned long *)((char *)current_thread_info() + sizeof(struct thread_info)); ++ ++ return (void *)vcos_data; ++} ++ ++ ++static inline void *to_vcos_thread(struct task_struct *tsk) ++{ ++ unsigned long *vcos_data; ++ ++ vcos_data = (unsigned long *)((char *)tsk->stack + sizeof(struct thread_info)); ++ ++ return (void *)vcos_data; ++} ++ ++/** ++ @fn uint32_t vcos_add_thread(THREAD_MAP_T *vcos_thread); ++*/ ++uint32_t vcos_add_thread(VCOS_THREAD_T *vcos_thread) ++{ ++ VCOS_THREAD_T **vcos_thread_storage = (VCOS_THREAD_T **)to_current_vcos_thread(); ++ ++ *vcos_thread_storage = vcos_thread; ++ ++ return(0); ++} ++ ++ ++/** ++ @fn uint32_t vcos_remove_thread(struct task_struct * thread_id); ++*/ ++uint32_t vcos_remove_thread(struct task_struct *thread_id) ++{ ++ /* Remove thread_id -> VCOS_THREAD_T relationship */ ++ VCOS_THREAD_T **vcos_thread_storage; ++ ++ /* ++ * We want to be able to build vcos as a loadable module, which ++ * means that we can't call get_task_struct. So we assert if we're ++ * ever called with thread_id != current. ++ */ ++ ++ BUG_ON( thread_id != current ); ++ ++ vcos_thread_storage = (VCOS_THREAD_T **)to_vcos_thread(thread_id); ++ ++ *(unsigned long *)vcos_thread_storage = 0xCAFEBABE; ++ ++ return(0); ++} ++ ++ ++VCOS_THREAD_T *vcos_kthread_current(void) ++{ ++ VCOS_THREAD_T **vcos_thread_storage = (VCOS_THREAD_T **)to_current_vcos_thread(); ++ ++ /* If we find this, either the thread is already dead or stack pages of a ++ * dead vcos thread are re-allocated to this one. ++ * ++ * Since there's no way to differentiate between these 2 cases, we just dump ++ * the current task name to the log. ++ * ++ * If the current thread is created using VCOS API, you should *never* see this ++ * print. ++ * ++ * If its a non-VCOS thread, just let it go ... ++ * ++ * To debug VCOS, uncomment printk's under the "if" condition below ++ * ++ */ ++ if (*vcos_thread_storage == (void *)0xCAFEBABE) ++ { ++ #if 0 ++ printk(KERN_DEBUG"****************************************************\n"); ++ printk(KERN_DEBUG"%s : You have a problem, if \"%s\" is a VCOS thread\n",__func__, current->comm); ++ printk(KERN_DEBUG"****************************************************\n"); ++ #endif ++ } ++ ++ return *vcos_thread_storage; ++} +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/linuxkernel/vcos_thread_map.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/linuxkernel/vcos_thread_map.h 2013-07-26 19:37:11.000000000 +0000 +@@ -0,0 +1,39 @@ ++/***************************************************************************** ++* Copyright 2009 - 2010 Broadcom Corporation. All rights reserved. ++* ++* Unless you and Broadcom execute a separate written software license ++* agreement governing use of this software, this software is licensed to you ++* under the terms of the GNU General Public License version 2, available at ++* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). ++* ++* Notwithstanding the above, under no circumstances may you combine this ++* software in any way with any other Broadcom software provided under a ++* license other than the GPL, without Broadcom's express prior written ++* consent. ++*****************************************************************************/ ++ ++ ++#ifndef VCOS_THREAD_MAP_H ++#define VCOS_THREAD_MAP_H ++ ++#include ++ ++#include "vcos_platform.h" ++ ++static inline void vcos_thread_map_init(void) ++{ ++ return; ++} ++ ++static inline void vcos_thread_map_cleanup(void) ++{ ++ return; ++} ++ ++uint32_t vcos_add_thread(VCOS_THREAD_T *vcos_thread); ++ ++uint32_t vcos_remove_thread(struct task_struct *thread_id); ++ ++VCOS_THREAD_T *vcos_kthread_current(void); ++ ++#endif /*VCOS_THREAD_MAP_H */ +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos.h 2013-07-26 19:37:11.000000000 +0000 +@@ -0,0 +1,212 @@ ++/* ++ * Copyright (c) 2010-2011 Broadcom. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++/*============================================================================= ++VideoCore OS Abstraction Layer - public header file ++=============================================================================*/ ++ ++/** ++ * \mainpage OS Abstraction Layer ++ * ++ * \section intro Introduction ++ * ++ * This abstraction layer is here to allow the underlying OS to be easily changed (e.g. from ++ * Nucleus to ThreadX) and to aid in porting host applications to new targets. ++ * ++ * \subsection error Error handling ++ * ++ * Wherever possible, VCOS functions assert internally and return void. The only exceptions ++ * are creation functions (which might fail due to lack of resources) and functions that ++ * might timeout or fail due to lack of space. Errors that might be reported by the underlying ++ * OS API (e.g. invalid mutex) are treated as a programming error, and are merely asserted on. ++ * ++ * \section thread_synch Threads and synchronisation ++ * ++ * \subsection thread Threads ++ * ++ * The thread API is somewhat different to that found in Nucleus. In particular, threads ++ * cannot just be destroyed at arbitrary times and nor can they merely exit. This is so ++ * that the same API can be implemented across all interesting platforms without too much ++ * difficulty. See vcos_thread.h for details. Thread attributes are configured via ++ * the VCOS_THREAD_ATTR_T structure, found in vcos_thread_attr.h. ++ * ++ * \subsection sema Semaphores ++ * ++ * Counted semaphores (c.f. Nucleus NU_SEMAPHORE) are created with VCOS_SEMAPHORE_T. ++ * Under ThreadX on VideoCore, semaphores are implemented using VideoCore spinlocks, and ++ * so are quite a lot faster than ordinary ThreadX semaphores. See vcos_semaphore.h. ++ * ++ * \subsection mtx Mutexes ++ * ++ * Mutexes are used for locking. Attempts to take a mutex twice, or to unlock it ++ * in a different thread to the one in which it was locked should be expected to fail. ++ * Mutexes are not re-entrant (see vcos_reentrant_mutex.h for a slightly slower ++ * re-entrant mutex). ++ * ++ * \subsection evflags Event flags ++ * ++ * Event flags (the ThreadX name - also known as event groups under Nucleus) provide ++ * 32 flags which can be waited on by multiple clients, and signalled by multiple clients. ++ * A timeout can be specified. See vcos_event_flags.h. An alternative to this is the ++ * VCOS_EVENT_T (see vcos_event.h) which is akin to the Win32 auto-reset event, or a ++ * saturating counted semaphore. ++ * ++ * \subsection event Events ++ * ++ * A VCOS_EVENT_T is a bit like a saturating semaphore. No matter how many times it ++ * is signalled, the waiter will only wake up once. See vcos_event.h. You might think this ++ * is useful if you suspect that the cost of reading the semaphore count (perhaps via a ++ * system call) is expensive on your platform. ++ * ++ * \subsection tls Thread local storage ++ * ++ * Thread local storage is supported using vcos_tls.h. This is emulated on Nucleus ++ * and ThreadX. ++ * ++ * \section int Interrupts ++ * ++ * The legacy LISR/HISR scheme found in Nucleus is supported via the legacy ISR API, ++ * which is also supported on ThreadX. New code should avoid this, and old code should ++ * be migrated away from it, since it is slow. See vcos_legacy_isr.h. ++ * ++ * Registering an interrupt handler, and disabling/restoring interrupts, is handled ++ * using the functions in vcos_isr.h. ++ * ++ */ ++ ++/** ++ * \file vcos.h ++ * ++ * This is the top level header file. Clients include this. It pulls in the platform-specific ++ * header file (vcos_platform.h) together with header files defining the expected APIs, such ++ * as vcos_mutex.h, vcos_semaphore.h, etc. It is also possible to include these header files ++ * directly. ++ * ++ */ ++ ++#ifndef VCOS_H ++#define VCOS_H ++ ++#include "interface/vcos/vcos_assert.h" ++#include "vcos_types.h" ++#include "vcos_platform.h" ++ ++#ifndef VCOS_INIT_H ++#include "interface/vcos/vcos_init.h" ++#endif ++ ++#ifndef VCOS_SEMAPHORE_H ++#include "interface/vcos/vcos_semaphore.h" ++#endif ++ ++#ifndef VCOS_THREAD_H ++#include "interface/vcos/vcos_thread.h" ++#endif ++ ++#ifndef VCOS_MUTEX_H ++#include "interface/vcos/vcos_mutex.h" ++#endif ++ ++#ifndef VCOS_MEM_H ++#include "interface/vcos/vcos_mem.h" ++#endif ++ ++#ifndef VCOS_LOGGING_H ++#include "interface/vcos/vcos_logging.h" ++#endif ++ ++#ifndef VCOS_STRING_H ++#include "interface/vcos/vcos_string.h" ++#endif ++ ++#ifndef VCOS_EVENT_H ++#include "interface/vcos/vcos_event.h" ++#endif ++ ++#ifndef VCOS_THREAD_ATTR_H ++#include "interface/vcos/vcos_thread_attr.h" ++#endif ++ ++#ifndef VCOS_TLS_H ++#include "interface/vcos/vcos_tls.h" ++#endif ++ ++#ifndef VCOS_REENTRANT_MUTEX_H ++#include "interface/vcos/vcos_reentrant_mutex.h" ++#endif ++ ++#ifndef VCOS_NAMED_SEMAPHORE_H ++#include "interface/vcos/vcos_named_semaphore.h" ++#endif ++ ++#ifndef VCOS_QUICKSLOW_MUTEX_H ++#include "interface/vcos/vcos_quickslow_mutex.h" ++#endif ++ ++/* Headers with predicates */ ++ ++#if VCOS_HAVE_EVENT_FLAGS ++#include "interface/vcos/vcos_event_flags.h" ++#endif ++ ++#if VCOS_HAVE_QUEUE ++#include "interface/vcos/vcos_queue.h" ++#endif ++ ++#if VCOS_HAVE_LEGACY_ISR ++#include "interface/vcos/vcos_legacy_isr.h" ++#endif ++ ++#if VCOS_HAVE_TIMER ++#include "interface/vcos/vcos_timer.h" ++#endif ++ ++#if VCOS_HAVE_MEMPOOL ++#include "interface/vcos/vcos_mempool.h" ++#endif ++ ++#if VCOS_HAVE_ISR ++#include "interface/vcos/vcos_isr.h" ++#endif ++ ++#if VCOS_HAVE_ATOMIC_FLAGS ++#include "interface/vcos/vcos_atomic_flags.h" ++#endif ++ ++#if VCOS_HAVE_ONCE ++#include "interface/vcos/vcos_once.h" ++#endif ++ ++#if VCOS_HAVE_BLOCK_POOL ++#include "interface/vcos/vcos_blockpool.h" ++#endif ++ ++#if VCOS_HAVE_FILE ++#include "interface/vcos/vcos_file.h" ++#endif ++ ++#if VCOS_HAVE_CFG ++#include "interface/vcos/vcos_cfg.h" ++#endif ++ ++#if VCOS_HAVE_CMD ++#include "interface/vcos/vcos_cmd.h" ++#endif ++ ++#endif /* VCOS_H */ ++ +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_assert.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_assert.h 2013-07-26 19:37:11.000000000 +0000 +@@ -0,0 +1,280 @@ ++/* ++ * Copyright (c) 2010-2011 Broadcom. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++/*============================================================================= ++VideoCore OS Abstraction Layer - Assertion and error-handling macros. ++=============================================================================*/ ++ ++ ++#ifndef VCOS_ASSERT_H ++#define VCOS_ASSERT_H ++ ++/* ++ * Macro: ++ * vcos_assert(cond) ++ * vcos_assert_msg(cond, fmt, ...) ++ * Use: ++ * Detecting programming errors by ensuring that assumptions are correct. ++ * On failure: ++ * Performs a platform-dependent "breakpoint", usually with an assert-style ++ * message. The '_msg' variant expects a printf-style format string and ++ * parameters. ++ * If a failure is detected, the code should be fixed and rebuilt. ++ * In release builds: ++ * Generates no code, i.e. does not evaluate 'cond'. ++ * Returns: ++ * Nothing. ++ * ++ * Macro: ++ * vcos_demand(cond) ++ * vcos_demand_msg(cond, fmt, ...) ++ * Use: ++ * Detecting fatal system errors that require a reboot. ++ * On failure: ++ * Performs a platform-dependent "breakpoint", usually with an assert-style ++ * message, then calls vcos_abort (see below). ++ * In release builds: ++ * Calls vcos_abort() if 'cond' is false. ++ * Returns: ++ * Nothing (never, on failure). ++ * ++ * Macro: ++ * vcos_verify(cond) ++ * vcos_verify_msg(cond, fmt, ...) ++ * Use: ++ * Detecting run-time errors and interesting conditions, normally within an ++ * 'if' statement to catch the failures, i.e. ++ * if (!vcos_verify(cond)) handle_error(); ++ * On failure: ++ * Generates a message and optionally stops at a platform-dependent ++ * "breakpoint" (usually disabled). See vcos_verify_bkpts_enable below. ++ * In release builds: ++ * Just evaluates and returns 'cond'. ++ * Returns: ++ * Non-zero if 'cond' is true, otherwise zero. ++ * ++ * Macro: ++ * vcos_static_assert(cond) ++ * Use: ++ * Detecting compile-time errors. ++ * On failure: ++ * Generates a compiler error. ++ * In release builds: ++ * Generates a compiler error. ++ * ++ * Function: ++ * void vcos_abort(void) ++ * Use: ++ * Invokes the fatal error handling mechanism, alerting the host where ++ * applicable. ++ * Returns: ++ * Never. ++ * ++ * Macro: ++ * VCOS_VERIFY_BKPTS ++ * Use: ++ * Define in a module (before including vcos.h) to specify an alternative ++ * flag to control breakpoints on vcos_verify() failures. ++ * Returns: ++ * Non-zero values enable breakpoints. ++ * ++ * Function: ++ * int vcos_verify_bkpts_enable(int enable); ++ * Use: ++ * Sets the global flag controlling breakpoints on vcos_verify failures, ++ * enabling the breakpoints iff 'enable' is non-zero. ++ * Returns: ++ * The previous state of the flag. ++ * ++ * Function: ++ * int vcos_verify_bkpts_enabled(void); ++ * Use: ++ * Queries the state of the global flag enabling breakpoints on vcos_verify ++ * failures. ++ * Returns: ++ * The current state of the flag. ++ * ++ * Examples: ++ * ++ * int my_breakpoint_enable_flag = 1; ++ * ++ * #define VCOS_VERIFY_BKPTS my_breakpoint_enable_flag ++ * ++ * #include "interface/vcos/vcos.h" ++ * ++ * vcos_static_assert((sizeof(object) % 32) == 0); ++ * ++ * // ... ++ * ++ * vcos_assert_msg(postcondition_is_true, "Coding error"); ++ * ++ * if (!vcos_verify_msg(buf, "Buffer allocation failed (%d bytes)", size)) ++ * { ++ * // Tidy up ++ * // ... ++ * return OUT_OF_MEMORY; ++ * } ++ * ++ * vcos_demand(*p++==GUARDWORDHEAP); ++ */ ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++#include "interface/vcos/vcos_types.h" ++ ++#ifdef __COVERITY__ ++#undef VCOS_ASSERT_BKPT ++#define VCOS_ASSERT_BKPT __coverity_panic__() ++#endif ++ ++#ifndef VCOS_VERIFY_BKPTS ++#define VCOS_VERIFY_BKPTS vcos_verify_bkpts_enabled() ++#endif ++ ++#ifndef VCOS_BKPT ++#if defined(__VIDEOCORE__) && !defined(VCOS_ASSERT_NO_BKPTS) ++#define VCOS_BKPT _bkpt() ++#else ++#define VCOS_BKPT (void )0 ++#endif ++#endif ++ ++#ifndef VCOS_ASSERT_BKPT ++#define VCOS_ASSERT_BKPT VCOS_BKPT ++#endif ++ ++#ifndef VCOS_VERIFY_BKPT ++#define VCOS_VERIFY_BKPT (VCOS_VERIFY_BKPTS ? VCOS_BKPT : (void)0) ++#endif ++ ++VCOSPRE_ int VCOSPOST_ vcos_verify_bkpts_enabled(void); ++VCOSPRE_ int VCOSPOST_ vcos_verify_bkpts_enable(int enable); ++VCOSPRE_ void VCOSPOST_ vcos_abort(void); ++ ++#ifndef VCOS_ASSERT_MSG ++#ifdef LOGGING ++extern void logging_assert(const char *file, const char *func, int line, const char *format, ...); ++#define VCOS_ASSERT_MSG(...) ((VCOS_ASSERT_LOGGING && !VCOS_ASSERT_LOGGING_DISABLE) ? logging_assert(__FILE__, __func__, __LINE__, __VA_ARGS__) : (void)0) ++#else ++#define VCOS_ASSERT_MSG(...) ((void)0) ++#endif ++#endif ++ ++#ifndef VCOS_VERIFY_MSG ++#define VCOS_VERIFY_MSG(...) VCOS_ASSERT_MSG(__VA_ARGS__) ++#endif ++ ++#ifndef VCOS_ASSERT_LOGGING ++#define VCOS_ASSERT_LOGGING 0 ++#endif ++ ++#ifndef VCOS_ASSERT_LOGGING_DISABLE ++#define VCOS_ASSERT_LOGGING_DISABLE 0 ++#endif ++ ++#if !defined(NDEBUG) || defined(VCOS_RELEASE_ASSERTS) ++ ++#ifndef vcos_assert ++#define vcos_assert(cond) \ ++ ( (cond) ? (void)0 : (VCOS_ASSERT_MSG("%s", #cond), VCOS_ASSERT_BKPT) ) ++#endif ++ ++#ifndef vcos_assert_msg ++#define vcos_assert_msg(cond, ...) \ ++ ( (cond) ? (void)0 : (VCOS_ASSERT_MSG(__VA_ARGS__), VCOS_ASSERT_BKPT) ) ++#endif ++ ++#else /* !defined(NDEBUG) || defined(VCOS_RELEASE_ASSERTS) */ ++ ++#ifndef vcos_assert ++#define vcos_assert(cond) (void)0 ++#endif ++ ++#ifndef vcos_assert_msg ++#define vcos_assert_msg(cond, ...) (void)0 ++#endif ++ ++#endif /* !defined(NDEBUG) || defined(VCOS_RELEASE_ASSERTS) */ ++ ++#if !defined(NDEBUG) ++ ++#ifndef vcos_demand ++#define vcos_demand(cond) \ ++ ( (cond) ? (void)0 : (VCOS_ASSERT_MSG("%s", #cond), VCOS_ASSERT_BKPT, vcos_abort()) ) ++#endif ++ ++#ifndef vcos_demand_msg ++#define vcos_demand_msg(cond, ...) \ ++ ( (cond) ? (void)0 : (VCOS_ASSERT_MSG(__VA_ARGS__), VCOS_ASSERT_BKPT, vcos_abort()) ) ++#endif ++ ++#ifndef vcos_verify ++#define vcos_verify(cond) \ ++ ( (cond) ? 1 : (VCOS_VERIFY_MSG("%s", #cond), VCOS_VERIFY_BKPT, 0) ) ++#endif ++ ++#ifndef vcos_verify_msg ++#define vcos_verify_msg(cond, ...) \ ++ ( (cond) ? 1 : (VCOS_VERIFY_MSG(__VA_ARGS__), VCOS_VERIFY_BKPT, 0) ) ++#endif ++ ++#else /* !defined(NDEBUG) */ ++ ++#ifndef vcos_demand ++#define vcos_demand(cond) \ ++ ( (cond) ? (void)0 : vcos_abort() ) ++#endif ++ ++#ifndef vcos_demand_msg ++#define vcos_demand_msg(cond, ...) \ ++ ( (cond) ? (void)0 : vcos_abort() ) ++#endif ++ ++#ifndef vcos_verify ++#define vcos_verify(cond) (cond) ++#endif ++ ++#ifndef vcos_verify_msg ++#define vcos_verify_msg(cond, ...) (cond) ++#endif ++ ++#endif /* !defined(NDEBUG) */ ++ ++#ifndef vcos_static_assert ++#if defined(__GNUC__) ++#define vcos_static_assert(cond) __attribute__((unused)) extern int vcos_static_assert[(cond)?1:-1] ++#else ++#define vcos_static_assert(cond) extern int vcos_static_assert[(cond)?1:-1] ++#endif ++#endif ++ ++#ifndef vc_assert ++#define vc_assert(cond) vcos_assert(cond) ++#endif ++ ++/** Print out a backtrace, on supported platforms. ++ */ ++extern void vcos_backtrace_self(void); ++ ++#ifdef __cplusplus ++} ++#endif ++ ++#endif /* VCOS_ASSERT_H */ +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_atomic_flags.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_atomic_flags.h 2013-07-26 19:37:11.000000000 +0000 +@@ -0,0 +1,83 @@ ++/* ++ * Copyright (c) 2010-2011 Broadcom. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++/*============================================================================= ++VideoCore OS Abstraction Layer - public header file ++=============================================================================*/ ++ ++#ifndef VCOS_ATOMIC_FLAGS_H ++#define VCOS_ATOMIC_FLAGS_H ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++#include "interface/vcos/vcos_types.h" ++#include "vcos_platform.h" ++ ++/** ++ * \file vcos_atomic_flags.h ++ * ++ * Defines atomic flags API. ++ * ++ * 32 flags. Atomic "or" and "get and clear" operations ++ */ ++ ++/** ++ * Create an atomic flags instance. ++ * ++ * @param atomic_flags Pointer to atomic flags instance, filled in on return ++ * ++ * @return VCOS_SUCCESS if succeeded. ++ */ ++VCOS_INLINE_DECL ++VCOS_STATUS_T vcos_atomic_flags_create(VCOS_ATOMIC_FLAGS_T *atomic_flags); ++ ++/** ++ * Atomically set the specified flags. ++ * ++ * @param atomic_flags Instance to set flags on ++ * @param flags Mask of flags to set ++ */ ++VCOS_INLINE_DECL ++void vcos_atomic_flags_or(VCOS_ATOMIC_FLAGS_T *atomic_flags, uint32_t flags); ++ ++/** ++ * Retrieve the current flags and then clear them. The entire operation is ++ * atomic. ++ * ++ * @param atomic_flags Instance to get/clear flags from/on ++ * ++ * @return Mask of flags which were set (and we cleared) ++ */ ++VCOS_INLINE_DECL ++uint32_t vcos_atomic_flags_get_and_clear(VCOS_ATOMIC_FLAGS_T *atomic_flags); ++ ++/** ++ * Delete an atomic flags instance. ++ * ++ * @param atomic_flags Instance to delete ++ */ ++VCOS_INLINE_DECL ++void vcos_atomic_flags_delete(VCOS_ATOMIC_FLAGS_T *atomic_flags); ++ ++#ifdef __cplusplus ++} ++#endif ++ ++#endif +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_build_info.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_build_info.h 2013-07-26 19:37:11.000000000 +0000 +@@ -0,0 +1,23 @@ ++/* ++ * Copyright (c) 2010-2011 Broadcom. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++const char *vcos_get_build_hostname( void ); ++const char *vcos_get_build_version( void ); ++const char *vcos_get_build_time( void ); ++const char *vcos_get_build_date( void ); ++ +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_cfg.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_cfg.h 2013-07-26 19:37:11.000000000 +0000 +@@ -0,0 +1,113 @@ ++/***************************************************************************** ++* Copyright 2009 - 2011 Broadcom Corporation. All rights reserved. ++* ++* Unless you and Broadcom execute a separate written software license ++* agreement governing use of this software, this software is licensed to you ++* under the terms of the GNU General Public License version 2, available at ++* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). ++* ++* Notwithstanding the above, under no circumstances may you combine this ++* software in any way with any other Broadcom software provided under a ++* license other than the GPL, without Broadcom's express prior written ++* consent. ++*****************************************************************************/ ++ ++#if !defined( VCOS_CFG_H ) ++#define VCOS_CFG_H ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++#include "interface/vcos/vcos_types.h" ++#include "vcos_platform.h" ++ ++typedef struct opaque_vcos_cfg_buf_t *VCOS_CFG_BUF_T; ++typedef struct opaque_vcos_cfg_entry_t *VCOS_CFG_ENTRY_T; ++ ++/** \file vcos_file.h ++ * ++ * API for accessing configuration/statistics information. This ++ * is loosely modelled on the linux proc entries. ++ */ ++ ++typedef void (*VCOS_CFG_SHOW_FPTR)( VCOS_CFG_BUF_T buf, void *data ); ++typedef void (*VCOS_CFG_PARSE_FPTR)( VCOS_CFG_BUF_T buf, void *data ); ++ ++/** Create a configuration directory. ++ * ++ * @param entry Place to store the created config entry. ++ * @param parent Parent entry (for directory like config ++ * options). ++ * @param entryName Name of the directory. ++ */ ++ ++VCOS_STATUS_T vcos_cfg_mkdir( VCOS_CFG_ENTRY_T *entry, ++ VCOS_CFG_ENTRY_T *parent, ++ const char *dirName ); ++ ++/** Create a configuration entry. ++ * ++ * @param entry Place to store the created config entry. ++ * @param parent Parent entry (for directory like config ++ * options). ++ * @param entryName Name of the configuration entry. ++ * @param showFunc Function pointer to show configuration ++ * data. ++ * @param parseFunc Function pointer to parse new data. ++ */ ++ ++VCOS_STATUS_T vcos_cfg_create_entry( VCOS_CFG_ENTRY_T *entry, ++ VCOS_CFG_ENTRY_T *parent, ++ const char *entryName, ++ VCOS_CFG_SHOW_FPTR showFunc, ++ VCOS_CFG_PARSE_FPTR parseFunc, ++ void *data ); ++ ++/** Determines if a configuration entry has been created or not. ++ * ++ * @param entry Configuration entry to query. ++ */ ++ ++int vcos_cfg_is_entry_created( VCOS_CFG_ENTRY_T entry ); ++ ++/** Returns the name of a configuration entry. ++ * ++ * @param entry Configuration entry to query. ++ */ ++ ++const char *vcos_cfg_get_entry_name( VCOS_CFG_ENTRY_T entry ); ++ ++/** Removes a configuration entry. ++ * ++ * @param entry Configuration entry to remove. ++ */ ++ ++VCOS_STATUS_T vcos_cfg_remove_entry( VCOS_CFG_ENTRY_T *entry ); ++ ++ ++/** Writes data into a configuration buffer. Only valid inside ++ * the show function. ++ * ++ * @param buf Buffer to write data into. ++ * @param fmt printf style format string. ++ */ ++ ++void vcos_cfg_buf_printf( VCOS_CFG_BUF_T buf, const char *fmt, ... ); ++ ++/** Retrieves a null terminated string of the data associated ++ * with the buffer. Only valid inside the parse function. ++ * ++ * @param buf Buffer to get data from. ++ * @param fmt printf style format string. ++ */ ++ ++char *vcos_cfg_buf_get_str( VCOS_CFG_BUF_T buf ); ++ ++void *vcos_cfg_get_proc_entry( VCOS_CFG_ENTRY_T entry ); ++ ++#ifdef __cplusplus ++} ++#endif ++#endif ++ +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_cmd.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_cmd.h 2013-07-26 19:37:11.000000000 +0000 +@@ -0,0 +1,98 @@ ++/***************************************************************************** ++* Copyright 2009 - 2011 Broadcom Corporation. All rights reserved. ++* ++* Unless you and Broadcom execute a separate written software license ++* agreement governing use of this software, this software is licensed to you ++* under the terms of the GNU General Public License version 2, available at ++* http://www.broadcom.com/licenses/GPLv2.php (the "GPL"). ++* ++* Notwithstanding the above, under no circumstances may you combine this ++* software in any way with any other Broadcom software provided under a ++* license other than the GPL, without Broadcom's express prior written ++* consent. ++*****************************************************************************/ ++ ++#if !defined( VCOS_CMD_H ) ++#define VCOS_CMD_H ++ ++/* ---- Include Files ----------------------------------------------------- */ ++ ++#include "interface/vcos/vcos.h" ++#include "interface/vcos/vcos_stdint.h" ++ ++ ++/* ---- Constants and Types ---------------------------------------------- */ ++ ++struct VCOS_CMD_S; ++typedef struct VCOS_CMD_S VCOS_CMD_T; ++ ++typedef struct ++{ ++ int argc; /* Number of arguments (includes the command/sub-command) */ ++ char **argv; /* Array of arguments */ ++ char **argv_orig; /* Original array of arguments */ ++ ++ VCOS_CMD_T *cmd_entry; ++ VCOS_CMD_T *cmd_parent_entry; ++ ++ int use_log; /* Output being logged? */ ++ size_t result_size; /* Size of result buffer. */ ++ char *result_ptr; /* Next place to put output. */ ++ char *result_buf; /* Start of the buffer. */ ++ ++} VCOS_CMD_PARAM_T; ++ ++typedef VCOS_STATUS_T (*VCOS_CMD_FUNC_T)( VCOS_CMD_PARAM_T *param ); ++ ++struct VCOS_CMD_S ++{ ++ const char *name; ++ const char *args; ++ VCOS_CMD_FUNC_T cmd_fn; ++ VCOS_CMD_T *sub_cmd_entry; ++ const char *descr; ++ ++}; ++ ++/* ---- Variable Externs ------------------------------------------------- */ ++ ++/* ---- Function Prototypes ---------------------------------------------- */ ++ ++/* ++ * Common printing routine for generating command output. ++ */ ++VCOSPRE_ void VCOSPOST_ vcos_cmd_error( VCOS_CMD_PARAM_T *param, const char *fmt, ... ) VCOS_FORMAT_ATTR_(printf, 2, 3); ++VCOSPRE_ void VCOSPOST_ vcos_cmd_printf( VCOS_CMD_PARAM_T *param, const char *fmt, ... ) VCOS_FORMAT_ATTR_(printf, 2, 3); ++VCOSPRE_ void VCOSPOST_ vcos_cmd_vprintf( VCOS_CMD_PARAM_T *param, const char *fmt, va_list args ) VCOS_FORMAT_ATTR_(printf, 2, 0); ++ ++/* ++ * Cause vcos_cmd_error, printf and vprintf to always log to the provided ++ * category. When this call is made, the results buffer passed into ++ * vcos_cmd_execute is used as a line buffer and does not need to be ++ * output by the caller. ++ */ ++VCOSPRE_ void VCOSPOST_ vcos_cmd_always_log_output( VCOS_LOG_CAT_T *log_category ); ++ ++/* ++ * Prints command usage for the current command. ++ */ ++VCOSPRE_ void VCOSPOST_ vcos_cmd_usage( VCOS_CMD_PARAM_T *param ); ++ ++/* ++ * Register commands to be processed ++ */ ++VCOSPRE_ VCOS_STATUS_T VCOSPOST_ vcos_cmd_register( VCOS_CMD_T *cmd_entry ); ++ ++/* ++ * Registers multiple commands to be processed. The array should ++ * be terminated by an entry with all zeros. ++ */ ++VCOSPRE_ VCOS_STATUS_T VCOSPOST_ vcos_cmd_register_multiple( VCOS_CMD_T *cmd_entry ); ++ ++/* ++ * Executes a command based on a command line. ++ */ ++VCOSPRE_ VCOS_STATUS_T VCOSPOST_ vcos_cmd_execute( int argc, char **argv, size_t result_size, char *result_buf ); ++ ++#endif /* VCOS_CMD_H */ ++ +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_ctype.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_ctype.h 2013-07-26 19:37:11.000000000 +0000 +@@ -0,0 +1,40 @@ ++/* ++ * Copyright (c) 2010-2011 Broadcom. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++/*============================================================================= ++VideoCore OS Abstraction Layer - public header file ++=============================================================================*/ ++ ++#ifndef VCOS_CTYPE_H ++#define VCOS_CTYPE_H ++ ++/** ++ * \file ++ * ++ * ctype functions. ++ * ++ */ ++ ++#ifdef __KERNEL__ ++#include ++#else ++#include ++#endif ++ ++#endif ++ +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_dlfcn.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_dlfcn.h 2013-07-26 19:37:11.000000000 +0000 +@@ -0,0 +1,80 @@ ++/* ++ * Copyright (c) 2010-2011 Broadcom. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++/*============================================================================= ++VCOS - abstraction over dynamic library opening ++=============================================================================*/ ++ ++#ifndef VCOS_DLFCN_H ++#define VCOS_DLFCN_H ++ ++#include "interface/vcos/vcos_types.h" ++#include "vcos_platform.h" ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++#define VCOS_DL_LAZY 1 ++#define VCOS_DL_NOW 2 ++ ++/** ++ * \file ++ * ++ * Loading dynamic libraries. See also dlfcn.h. ++ */ ++ ++/** Open a dynamic library. ++ * ++ * @param name name of the library ++ * @param mode Load lazily or immediately (VCOS_DL_LAZY, VCOS_DL_NOW). ++ * ++ * @return A handle for use in subsequent calls. ++ */ ++VCOSPRE_ void * VCOSPOST_ vcos_dlopen(const char *name, int mode); ++ ++/** Look up a symbol. ++ * ++ * @param handle Handle to open ++ * @param name Name of function ++ * ++ * @return Function pointer, or NULL. ++ */ ++VCOSPRE_ void VCOSPOST_ (*vcos_dlsym(void *handle, const char *name))(void); ++ ++/** Close a library ++ * ++ * @param handle Handle to close ++ */ ++VCOSPRE_ int VCOSPOST_ vcos_dlclose (void *handle); ++ ++/** Return error message from library. ++ * ++ * @param err On return, set to non-zero if an error has occurred ++ * @param buf Buffer to write error to ++ * @param len Size of buffer (including terminating NUL). ++ */ ++VCOSPRE_ int VCOSPOST_ vcos_dlerror(int *err, char *buf, size_t buflen); ++ ++ ++#ifdef __cplusplus ++} ++#endif ++#endif ++ ++ +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_event.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_event.h 2013-07-26 19:37:11.000000000 +0000 +@@ -0,0 +1,108 @@ ++/* ++ * Copyright (c) 2010-2011 Broadcom. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++/*============================================================================= ++VideoCore OS Abstraction Layer - public header file for events ++=============================================================================*/ ++ ++#ifndef VCOS_EVENT_H ++#define VCOS_EVENT_H ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++#include "interface/vcos/vcos_types.h" ++#include "vcos_platform.h" ++ ++/** ++ * \file ++ * ++ * An event is akin to the Win32 auto-reset event. ++ * ++ * ++ * Signalling an event will wake up one waiting thread only. Once one ++ * thread has been woken the event atomically returns to the unsignalled ++ * state. ++ * ++ * If no threads are waiting on the event when it is signalled it remains ++ * signalled. ++ * ++ * This is almost, but not quite, completely unlike the "event flags" ++ * object based on Nucleus event groups and ThreadX event flags. ++ * ++ * In particular, it should be similar in speed to a semaphore, unlike ++ * the event flags. ++ */ ++ ++/** ++ * Create an event instance. ++ * ++ * @param event Filled in with constructed event. ++ * @param name Name of the event (for debugging) ++ * ++ * @return VCOS_SUCCESS on success, or error code. ++ */ ++VCOS_INLINE_DECL ++VCOS_STATUS_T vcos_event_create(VCOS_EVENT_T *event, const char *name); ++ ++#ifndef vcos_event_signal ++ ++/** ++ * Signal the event. The event will return to being unsignalled ++ * after exactly one waiting thread has been woken up. If no ++ * threads are waiting it remains signalled. ++ * ++ * @param event The event to signal ++ */ ++VCOS_INLINE_DECL ++void vcos_event_signal(VCOS_EVENT_T *event); ++ ++/** ++ * Wait for the event. ++ * ++ * @param event The event to wait for ++ * @return VCOS_SUCCESS on success, VCOS_EAGAIN if the wait was interrupted. ++ */ ++VCOS_INLINE_DECL ++VCOS_STATUS_T vcos_event_wait(VCOS_EVENT_T *event); ++ ++/** ++ * Try event, but don't block. ++ * ++ * @param event The event to try ++ * @return VCOS_SUCCESS on success, VCOS_EAGAIN if the event is not currently signalled ++ */ ++VCOS_INLINE_DECL ++VCOS_STATUS_T vcos_event_try(VCOS_EVENT_T *event); ++ ++#endif ++ ++/* ++ * Destroy an event. ++ */ ++VCOS_INLINE_DECL ++void vcos_event_delete(VCOS_EVENT_T *event); ++ ++#ifdef __cplusplus ++} ++#endif ++ ++#endif ++ ++ +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_event_flags.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_event_flags.h 2013-07-26 19:37:11.000000000 +0000 +@@ -0,0 +1,109 @@ ++/* ++ * Copyright (c) 2010-2011 Broadcom. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++/*============================================================================= ++VideoCore OS Abstraction Layer - public header file ++=============================================================================*/ ++ ++#ifndef VCOS_EVENT_FLAGS_H ++#define VCOS_EVENT_FLAGS_H ++ ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++#include "interface/vcos/vcos_types.h" ++#include "vcos_platform.h" ++ ++#define VCOS_EVENT_FLAGS_SUSPEND VCOS_SUSPEND ++#define VCOS_EVENT_FLAGS_NO_SUSPEND VCOS_NO_SUSPEND ++typedef VCOS_OPTION VCOS_EVENTGROUP_OPERATION_T; ++ ++/** ++ * \file vcos_event_flags.h ++ * ++ * Defines event flags API. ++ * ++ * Similar to Nucleus event groups. ++ * ++ * These have the same semantics as Nucleus event groups and ThreadX event ++ * flags. As such, they are quite complex internally; if speed is important ++ * they might not be your best choice. ++ * ++ */ ++ ++/** ++ * Create an event flags instance. ++ * ++ * @param flags Pointer to event flags instance, filled in on return. ++ * @param name Name for the event flags, used for debug. ++ * ++ * @return VCOS_SUCCESS if succeeded. ++ */ ++ ++VCOS_INLINE_DECL ++VCOS_STATUS_T vcos_event_flags_create(VCOS_EVENT_FLAGS_T *flags, const char *name); ++ ++/** ++ * Set some events. ++ * ++ * @param flags Instance to set flags on ++ * @param events Bitmask of the flags to actually set ++ * @param op How the flags should be set. VCOS_OR will OR in the flags; VCOS_AND ++ * will AND them in, possibly clearing existing flags. ++ */ ++VCOS_INLINE_DECL ++void vcos_event_flags_set(VCOS_EVENT_FLAGS_T *flags, ++ VCOS_UNSIGNED events, ++ VCOS_OPTION op); ++ ++/** ++ * Retrieve some events. ++ * ++ * Waits until the specified events have been set. ++ * ++ * @param flags Instance to wait on ++ * @param requested_events The bitmask to wait for ++ * @param op VCOS_OR - get any; VCOS_AND - get all. ++ * @param ms_suspend How long to wait, in milliseconds ++ * @param retrieved_events the events actually retrieved. ++ * ++ * @return VCOS_SUCCESS if events were retrieved. VCOS_EAGAIN if the ++ * timeout expired. ++ */ ++VCOS_INLINE_DECL ++VCOS_STATUS_T vcos_event_flags_get(VCOS_EVENT_FLAGS_T *flags, ++ VCOS_UNSIGNED requested_events, ++ VCOS_OPTION op, ++ VCOS_UNSIGNED ms_suspend, ++ VCOS_UNSIGNED *retrieved_events); ++ ++ ++/** ++ * Delete an event flags instance. ++ */ ++VCOS_INLINE_DECL ++void vcos_event_flags_delete(VCOS_EVENT_FLAGS_T *); ++ ++#ifdef __cplusplus ++} ++#endif ++ ++#endif ++ +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_init.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_init.h 2013-07-26 19:37:11.000000000 +0000 +@@ -0,0 +1,54 @@ ++/* ++ * Copyright (c) 2010-2011 Broadcom. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++/*============================================================================= ++VideoCore OS Abstraction Layer - initialization routines ++=============================================================================*/ ++ ++ ++#include "interface/vcos/vcos_types.h" ++#include "vcos_platform.h" ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/** \file ++ * ++ * Some OS support libraries need some initialization. To support this, call this ++ * function at the start of day. ++ */ ++ ++VCOSPRE_ VCOS_STATUS_T VCOSPOST_ vcos_init(void); ++VCOSPRE_ void VCOSPOST_ vcos_deinit(void); ++VCOSPRE_ void VCOSPOST_ vcos_global_lock(void); ++VCOSPRE_ void VCOSPOST_ vcos_global_unlock(void); ++ ++/** Pass in the argv/argc arguments passed to main() */ ++VCOSPRE_ void VCOSPOST_ vcos_set_args(int argc, const char **argv); ++ ++/** Return argc. */ ++VCOSPRE_ int VCOSPOST_ vcos_get_argc(void); ++ ++/** Return argv. */ ++VCOSPRE_ const char ** VCOSPOST_ vcos_get_argv(void); ++ ++#ifdef __cplusplus ++} ++#endif ++ +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_logging.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_logging.h 2013-07-26 19:37:11.000000000 +0000 +@@ -0,0 +1,290 @@ ++/* ++ * Copyright (c) 2010-2011 Broadcom. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++/*============================================================================= ++VideoCore OS Abstraction Layer - logging support ++=============================================================================*/ ++ ++#ifndef VCOS_LOGGING_H ++#define VCOS_LOGGING_H ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++#include ++ ++#include "interface/vcos/vcos_types.h" ++#include "vcos_platform.h" ++ ++/** ++ * \file ++ * ++ * Logging support ++ * ++ * This provides categorised logging. Clients register ++ * a category, and then get a number of logging levels for ++ * that category. ++ * ++ * The logging level flag is tested using a flag *before* the ++ * function call, which makes logging very fast when disabled - there ++ * is no function call overhead just to find out that this log ++ * message is disabled. ++ * ++ * \section VCOS_LOG_CATEGORY ++ * ++ * As a convenience, clients define VCOS_LOG_CATEGORY to point to ++ * their category; the various vcos_log_xxx() macros then expand to ++ * use this. ++ * ++ * e.g. ++ * ++ * #define VCOS_LOG_CATEGORY (&my_category) ++ * ++ * #include ++ * ++ * VCOS_LOG_CAT_T my_category; ++ * ++ * .... ++ * ++ * vcos_log_trace("Stuff happened: %d", n_stuff); ++ * ++ */ ++ ++/** Logging levels */ ++typedef enum VCOS_LOG_LEVEL_T ++{ ++ VCOS_LOG_UNINITIALIZED = 0, ++ VCOS_LOG_NEVER, ++ VCOS_LOG_ERROR, ++ VCOS_LOG_WARN, ++ VCOS_LOG_INFO, ++ VCOS_LOG_TRACE, ++} VCOS_LOG_LEVEL_T; ++ ++ ++/** Initialize a logging category without going through vcos_log_register(). ++ * ++ * This is useful for the case where there is no obvious point to do the ++ * registration (no initialization function for the module). However, it ++ * means that your logging category is not registered, so cannot be easily ++ * changed at run-time. ++ */ ++#define VCOS_LOG_INIT(n,l) { l, n, 0, {0}, 0, 0 } ++ ++/** A registered logging category. ++ */ ++typedef struct VCOS_LOG_CAT_T ++{ ++ VCOS_LOG_LEVEL_T level; /** Which levels are enabled for this category */ ++ const char *name; /** Name for this category. */ ++ struct VCOS_LOG_CAT_T *next; ++ struct { ++ unsigned int want_prefix:1; ++ } flags; ++ unsigned int refcount; ++ void *platform_data; /** platform specific data */ ++} VCOS_LOG_CAT_T; ++ ++typedef void (*VCOS_VLOG_IMPL_FUNC_T)(const VCOS_LOG_CAT_T *cat, VCOS_LOG_LEVEL_T _level, const char *fmt, va_list args); ++ ++/** Convert a VCOS_LOG_LEVEL_T into a printable string. ++ * The platform needs to implement this function. ++ */ ++VCOSPRE_ const char * VCOSPOST_ vcos_log_level_to_string( VCOS_LOG_LEVEL_T level ); ++ ++/** Convert a string into a VCOS_LOG_LEVEL_T ++ * The platform needs to implement this function. ++ */ ++VCOSPRE_ VCOS_STATUS_T VCOSPOST_ vcos_string_to_log_level( const char *str, VCOS_LOG_LEVEL_T *level ); ++ ++/** Log a message. Basic API. Normal code should not use this. ++ * The platform needs to implement this function. ++ */ ++VCOSPRE_ void VCOSPOST_ vcos_log_impl(const VCOS_LOG_CAT_T *cat, VCOS_LOG_LEVEL_T _level, const char *fmt, ...) VCOS_FORMAT_ATTR_(printf, 3, 4); ++ ++/** Log a message using a varargs parameter list. Normal code should ++ * not use this. ++ */ ++VCOSPRE_ void VCOSPOST_ vcos_vlog_impl(const VCOS_LOG_CAT_T *cat, VCOS_LOG_LEVEL_T _level, const char *fmt, va_list args) VCOS_FORMAT_ATTR_(printf, 3, 0); ++ ++/** Set the function which does the actual logging output. ++ * Passing in NULL causes the default logging function to be ++ * used. ++ */ ++VCOSPRE_ void VCOSPOST_ vcos_set_vlog_impl( VCOS_VLOG_IMPL_FUNC_T vlog_impl_func ); ++ ++/** The default logging function, which is provided by each ++ * platform. ++ */ ++ ++VCOSPRE_ void VCOSPOST_ vcos_vlog_default_impl(const VCOS_LOG_CAT_T *cat, VCOS_LOG_LEVEL_T _level, const char *fmt, va_list args) VCOS_FORMAT_ATTR_(printf, 3, 0); ++ ++/* ++ * Initialise the logging subsystem. This is called from ++ * vcos_init() so you don't normally need to call it. ++ */ ++VCOSPRE_ void VCOSPOST_ vcos_logging_init(void); ++ ++/** Register a logging category. ++ * ++ * @param name the name of this category. ++ * @param category the category to register. ++ */ ++VCOSPRE_ void VCOSPOST_ vcos_log_register(const char *name, VCOS_LOG_CAT_T *category); ++ ++/** Unregister a logging category. ++ */ ++VCOSPRE_ void VCOSPOST_ vcos_log_unregister(VCOS_LOG_CAT_T *category); ++ ++/** Return a default logging category, for people too lazy to create their own. ++ * ++ * Using the default category will be slow (there's an extra function ++ * call overhead). Don't do this in normal code. ++ */ ++VCOSPRE_ const VCOS_LOG_CAT_T * VCOSPOST_ vcos_log_get_default_category(void); ++ ++VCOSPRE_ void VCOSPOST_ vcos_set_log_options(const char *opt); ++ ++/** Set the logging level for a category at run time. Without this, the level ++ * will be that set by vcos_log_register from a platform-specific source. ++ * ++ * @param category the category to modify. ++ * @param level the new logging level for this category. ++ */ ++VCOS_STATIC_INLINE void vcos_log_set_level(VCOS_LOG_CAT_T *category, VCOS_LOG_LEVEL_T level) ++{ ++ category->level = level; ++} ++ ++#define vcos_log_dump_mem(cat,label,addr,voidMem,numBytes) do { if (vcos_is_log_enabled(cat,VCOS_LOG_TRACE)) vcos_log_dump_mem_impl(cat,label,addr,voidMem,numBytes); } while (0) ++ ++void vcos_log_dump_mem_impl( const VCOS_LOG_CAT_T *cat, ++ const char *label, ++ uint32_t addr, ++ const void *voidMem, ++ size_t numBytes ); ++ ++/* ++ * Platform specific hooks (optional). ++ */ ++#ifndef vcos_log_platform_init ++#define vcos_log_platform_init() (void)0 ++#endif ++ ++#ifndef vcos_log_platform_register ++#define vcos_log_platform_register(category) (void)0 ++#endif ++ ++#ifndef vcos_log_platform_unregister ++#define vcos_log_platform_unregister(category) (void)0 ++#endif ++ ++/* VCOS_TRACE() - deprecated macro which just outputs in a debug build and ++ * is a no-op in a release build. ++ * ++ * _VCOS_LOG_X() - internal macro which outputs if the current level for the ++ * particular category is higher than the supplied message level. ++ */ ++ ++#define VCOS_LOG_DFLT_CATEGORY vcos_log_get_default_category() ++ ++#define _VCOS_LEVEL(x) (x) ++ ++#define vcos_is_log_enabled(cat,_level) (_VCOS_LEVEL((cat)->level) >= _VCOS_LEVEL(_level)) ++ ++#if defined(_VCOS_METAWARE) || defined(__GNUC__) ++ ++# if !defined(NDEBUG) || defined(VCOS_ALWAYS_WANT_LOGGING) ++# define VCOS_LOGGING_ENABLED ++# define _VCOS_LOG_X(cat, _level, fmt...) do { if (vcos_is_log_enabled(cat,_level)) vcos_log_impl(cat,_level,fmt); } while (0) ++# define _VCOS_VLOG_X(cat, _level, fmt, ap) do { if (vcos_is_log_enabled(cat,_level)) vcos_vlog_impl(cat,_level,fmt,ap); } while (0) ++# else ++# define _VCOS_LOG_X(cat, _level, fmt...) (void)0 ++# define _VCOS_VLOG_X(cat, _level, fmt, ap) (void)0 ++# endif ++ ++ ++ ++# define vcos_log_error(...) _VCOS_LOG_X(VCOS_LOG_CATEGORY, VCOS_LOG_ERROR, __VA_ARGS__) ++# define vcos_log_warn(...) _VCOS_LOG_X(VCOS_LOG_CATEGORY, VCOS_LOG_WARN, __VA_ARGS__) ++# define vcos_log_info(...) _VCOS_LOG_X(VCOS_LOG_CATEGORY, VCOS_LOG_INFO, __VA_ARGS__) ++# define vcos_log_trace(...) _VCOS_LOG_X(VCOS_LOG_CATEGORY, VCOS_LOG_TRACE, __VA_ARGS__) ++ ++# define vcos_vlog_error(fmt,ap) _VCOS_VLOG_X(VCOS_LOG_CATEGORY, VCOS_LOG_ERROR, fmt, ap) ++# define vcos_vlog_warn(fmt,ap) _VCOS_VLOG_X(VCOS_LOG_CATEGORY, VCOS_LOG_WARN, fmt, ap) ++# define vcos_vlog_info(fmt,ap) _VCOS_VLOG_X(VCOS_LOG_CATEGORY, VCOS_LOG_INFO, fmt, ap) ++# define vcos_vlog_trace(fmt,ap) _VCOS_VLOG_X(VCOS_LOG_CATEGORY, VCOS_LOG_TRACE, fmt, ap) ++ ++# define vcos_log(...) _VCOS_LOG_X(VCOS_LOG_DFLT_CATEGORY, VCOS_LOG_INFO, __VA_ARGS__) ++# define vcos_vlog(fmt,ap) _VCOS_VLOG_X(VCOS_LOG_DFLT_CATEGORY, VCOS_LOG_INFO, fmt, ap) ++# define VCOS_ALERT(...) _VCOS_LOG_X(VCOS_LOG_DFLT_CATEGORY, VCOS_LOG_ERROR, __VA_ARGS__) ++# define VCOS_TRACE(...) _VCOS_LOG_X(VCOS_LOG_DFLT_CATEGORY, VCOS_LOG_INFO, __VA_ARGS__) ++ ++/* ++ * MS Visual Studio - pre 2005 does not grok variadic macros ++ */ ++#elif defined(_MSC_VER) ++ ++# if _MSC_VER >= 1400 ++ ++# if !defined(NDEBUG) || defined(VCOS_ALWAYS_WANT_LOGGING) ++# define VCOS_LOGGING_ENABLED ++# define _VCOS_LOG_X(cat, _level, fmt,...) do { if (vcos_is_log_enabled(cat,_level)) vcos_log_impl(cat, _level, fmt, __VA_ARGS__); } while (0) ++# else ++# define _VCOS_LOG_X(cat, _level, fmt,...) (void)0 ++# endif ++ ++# define vcos_log_error(fmt,...) _VCOS_LOG_X(VCOS_LOG_CATEGORY, VCOS_LOG_ERROR, fmt, __VA_ARGS__) ++# define vcos_log_warn(fmt,...) _VCOS_LOG_X(VCOS_LOG_CATEGORY, VCOS_LOG_WARN, fmt, __VA_ARGS__) ++# define vcos_log_info(fmt,...) _VCOS_LOG_X(VCOS_LOG_CATEGORY, VCOS_LOG_INFO, fmt, __VA_ARGS__) ++# define vcos_log_trace(fmt,...) _VCOS_LOG_X(VCOS_LOG_CATEGORY, VCOS_LOG_TRACE, fmt, __VA_ARGS__) ++ ++# define vcos_log(fmt,...) _VCOS_LOG_X(VCOS_LOG_DFLT_CATEGORY, VCOS_LOG_INFO, fmt) ++# define VCOS_ALERT(fmt,...) _VCOS_LOG_X(VCOS_LOG_DFLT_CATEGORY, VCOS_LOG_ERROR, fmt) ++# define VCOS_TRACE(fmt,...) _VCOS_LOG_X(VCOS_LOG_DFLT_CATEGORY, VCOS_LOG_INFO, fmt) ++ ++# else /* _MSC_VER >= 1400 */ ++ ++/* do not define these */ ++ ++# endif /* _MSC_VER >= 1400 */ ++ ++#endif ++ ++#if VCOS_HAVE_CMD ++ ++#include "interface/vcos/vcos_cmd.h" ++ ++/* ++ * These are the log sub-commands. They're exported here for user-mode apps which ++ * may want to call these, since the "log" command isn't registered for user-mode ++ * apps (vcdbg for example, has its own log command). ++ */ ++VCOSPRE_ VCOS_STATUS_T VCOSPOST_ vcos_log_assert_cmd( VCOS_CMD_PARAM_T *param ); ++VCOSPRE_ VCOS_STATUS_T VCOSPOST_ vcos_log_set_cmd( VCOS_CMD_PARAM_T *param ); ++VCOSPRE_ VCOS_STATUS_T VCOSPOST_ vcos_log_status_cmd( VCOS_CMD_PARAM_T *param ); ++VCOSPRE_ VCOS_STATUS_T VCOSPOST_ vcos_log_test_cmd( VCOS_CMD_PARAM_T *param ); ++#endif ++ ++#ifdef __cplusplus ++} ++#endif ++#endif /* VCOS_LOGGING_H */ ++ ++ +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_lowlevel_thread.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_lowlevel_thread.h 2013-07-26 19:37:11.000000000 +0000 +@@ -0,0 +1,118 @@ ++/* ++ * Copyright (c) 2010-2011 Broadcom. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++/*============================================================================= ++VideoCore OS Abstraction Layer - low level thread support ++=============================================================================*/ ++ ++#ifndef VCOS_LOWLEVEL_THREAD_H ++#define VCOS_LOWLEVEL_THREAD_H ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++#include "interface/vcos/vcos_types.h" ++#include "vcos_platform.h" ++ ++/** ++ * \file ++ * ++ * This defines a low level thread API that is supported by *some* operating systems ++ * and can be used to construct the regular "joinable thread" API on those operating ++ * systems. ++ * ++ * Most clients will not need to use this code. ++ * ++ * \sa vcos_joinable_thread.h ++ */ ++ ++/** ++ * \brief Create a thread. ++ * ++ * This creates a thread which can be stopped either by returning from the ++ * entry point function or by calling vcos_llthread_exit from within the entry ++ * point function. The thread must be cleaned up by calling ++ * vcos_llthread_delete. vcos_llthread_delete may or may not terminate the ++ * thread. ++ * ++ * The preemptible parameter familiar from Nucleus is removed, as it is unused in ++ * VideoCore code. Affinity is added, since we do use this. ++ * ++ * @param thread Filled in with thread instance ++ * @param name An optional name for the thread. "" may be used (but ++ * a name will aid in debugging). ++ * @param entry Entry point ++ * @param arg A single argument passed to the entry point function ++ * @param stack Pointer to stack address ++ * @param stacksz Size of stack in bytes ++ * @param priority Priority of task, between VCOS_PRI_LOW and VCOS_PRI_HIGH ++ * @param affinity CPU affinity ++ * ++ * @sa vcos_llthread_terminate vcos_llthread_delete ++ */ ++VCOSPRE_ VCOS_STATUS_T VCOSPOST_ vcos_llthread_create(VCOS_LLTHREAD_T *thread, ++ const char *name, ++ VCOS_LLTHREAD_ENTRY_FN_T entry, ++ void *arg, ++ void *stack, ++ VCOS_UNSIGNED stacksz, ++ VCOS_UNSIGNED priority, ++ VCOS_UNSIGNED affinity, ++ VCOS_UNSIGNED timeslice, ++ VCOS_UNSIGNED autostart); ++ ++/** ++ * \brief Exits the current thread. ++ */ ++VCOSPRE_ void VCOSPOST_ vcos_llthread_exit(void); ++ ++/** ++ * \brief Delete a thread. This must be called to cleanup after ++ * vcos_llthread_create. This may or may not terminate the thread. ++ * It does not clean up any resources that may have been ++ * allocated by the thread. ++ */ ++VCOSPRE_ void VCOSPOST_ vcos_llthread_delete(VCOS_LLTHREAD_T *thread); ++ ++/** ++ * \brief Return current lowlevel thread pointer. ++ */ ++VCOS_INLINE_DECL ++VCOS_LLTHREAD_T *vcos_llthread_current(void); ++ ++/** ++ * Resume a thread. ++ */ ++VCOS_INLINE_DECL ++void vcos_llthread_resume(VCOS_LLTHREAD_T *thread); ++ ++VCOSPRE_ int VCOSPOST_ vcos_llthread_running(VCOS_LLTHREAD_T *thread); ++ ++/** ++ * \brief Create a VCOS_LLTHREAD_T for the current thread. This is so we can ++ * have VCOS_LLTHREAD_Ts even for threads not originally created by VCOS (eg ++ * the thread that calls vcos_init). ++ */ ++extern VCOS_STATUS_T _vcos_llthread_create_attach(VCOS_LLTHREAD_T *thread); ++ ++#ifdef __cplusplus ++} ++#endif ++#endif ++ +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_mem.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_mem.h 2013-07-26 19:37:11.000000000 +0000 +@@ -0,0 +1,92 @@ ++/* ++ * Copyright (c) 2010-2011 Broadcom. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++/*============================================================================= ++VideoCore OS Abstraction Layer - memory support ++=============================================================================*/ ++ ++#ifndef VCOS_MEM_H ++#define VCOS_MEM_H ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++#include "interface/vcos/vcos_types.h" ++#include "vcos_platform.h" ++ ++/** \file ++ * ++ * Memory allocation api (malloc/free equivalents) is for benefit of host ++ * applications. VideoCore code should use rtos_XXX functions. ++ * ++ */ ++ ++ ++/** Allocate memory ++ * ++ * @param size Size of memory to allocate ++ * @param description Description, to aid in debugging. May be ignored internally on some platforms. ++ */ ++VCOS_INLINE_DECL ++void *vcos_malloc(VCOS_UNSIGNED size, const char *description); ++ ++void *vcos_kmalloc(VCOS_UNSIGNED size, const char *description); ++void *vcos_kcalloc(VCOS_UNSIGNED num, VCOS_UNSIGNED size, const char *description); ++ ++/** Allocate cleared memory ++ * ++ * @param num Number of items to allocate. ++ * @param size Size of each item in bytes. ++ * @param description Description, to aid in debugging. May be ignored internally on some platforms. ++ */ ++VCOS_INLINE_DECL ++void *vcos_calloc(VCOS_UNSIGNED num, VCOS_UNSIGNED size, const char *description); ++ ++/** Free memory ++ * ++ * Free memory that has been allocated. ++ */ ++VCOS_INLINE_DECL ++void vcos_free(void *ptr); ++ ++void vcos_kfree(void *ptr); ++ ++/** Allocate aligned memory ++ * ++ * Allocate memory aligned on the specified boundary. ++ * ++ * @param size Size of memory to allocate ++ * @param description Description, to aid in debugging. May be ignored internally on some platforms. ++ */ ++VCOS_INLINE_DECL ++void *vcos_malloc_aligned(VCOS_UNSIGNED size, VCOS_UNSIGNED align, const char *description); ++ ++/** Return the amount of free heap memory ++ * ++ */ ++VCOS_INLINE_DECL ++unsigned long vcos_get_free_mem(void); ++ ++#ifdef __cplusplus ++} ++#endif ++ ++#endif ++ ++ +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_msgqueue.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_msgqueue.h 2013-07-26 19:37:11.000000000 +0000 +@@ -0,0 +1,168 @@ ++/* ++ * Copyright (c) 2010-2011 Broadcom. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++/*============================================================================= ++VCOS - packet-like messages, based loosely on those found in TRIPOS. ++=============================================================================*/ ++ ++#ifndef VCOS_MSGQUEUE_H ++#define VCOS_MSGQUEUE_H ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++#include "interface/vcos/vcos_types.h" ++#include "vcos_platform.h" ++ ++/** ++ * \file ++ * ++ * Packet-like messages, based loosely on those found in TRIPOS and ++ * derivatives thereof. ++ * ++ * A task can send a message *pointer* to another task, where it is ++ * queued on a linked list and the task woken up. The receiving task ++ * consumes all of the messages on its input queue, and optionally ++ * sends back replies using the original message memory. ++ * ++ * A caller can wait for the reply to a specific message - any other ++ * messages that arrive in the meantime are queued separately. ++ * ++ * ++ * All messages have a standard common layout, but the payload area can ++ * be used freely to extend this. ++ */ ++ ++/** Map the payload portion of a message to a structure pointer. ++ */ ++#define VCOS_MSG_DATA(_msg) (void*)((_msg)->data) ++ ++/** Standard message ids - FIXME - these need to be done properly! */ ++#define VCOS_MSG_N_QUIT 1 ++#define VCOS_MSG_N_OPEN 2 ++#define VCOS_MSG_N_CLOSE 3 ++#define VCOS_MSG_N_PRIVATE (1<<20) ++ ++#define VCOS_MSG_REPLY_BIT (1<<31) ++ ++/** Make gnuc compiler be happy about pointer punning */ ++#ifdef __GNUC__ ++#define __VCOS_MAY_ALIAS __attribute__((__may_alias__)) ++#else ++#define __VCOS_MAY_ALIAS ++#endif ++ ++/** A single message queue. ++ */ ++typedef struct VCOS_MSGQUEUE_T ++{ ++ struct VCOS_MSG_T *head; /**< head of linked list of messages waiting on this queue */ ++ struct VCOS_MSG_T *tail; /**< tail of message queue */ ++ VCOS_SEMAPHORE_T sem; /**< thread waits on this for new messages */ ++ VCOS_MUTEX_T lock; /**< locks the messages list */ ++} VCOS_MSGQUEUE_T; ++ ++/** A single message ++ */ ++typedef struct VCOS_MSG_T ++{ ++ uint32_t code; /**< message code */ ++ int error; /**< error status signalled back to caller */ ++ VCOS_MSGQUEUE_T *dst; /**< destination queue */ ++ VCOS_MSGQUEUE_T *src; /**< source; replies go back to here */ ++ struct VCOS_MSG_T *next; /**< next in queue */ ++ VCOS_THREAD_T *src_thread; /**< for debug */ ++ uint32_t data[25]; /**< payload area */ ++} VCOS_MSG_T; ++ ++/** An endpoint ++ */ ++typedef struct VCOS_MSG_ENDPOINT_T ++{ ++ VCOS_MSGQUEUE_T primary; /**< incoming messages */ ++ VCOS_MSGQUEUE_T secondary; /**< this is used for waitspecific */ ++ char name[32]; /**< name of this endpoint, for find() */ ++ struct VCOS_MSG_ENDPOINT_T *next; /**< next in global list of endpoints */ ++} VCOS_MSG_ENDPOINT_T; ++#define MSG_REPLY_BIT (1<<31) ++ ++/** Initalise the library. Normally called from vcos_init(). ++ */ ++extern VCOS_STATUS_T vcos_msgq_init(void); ++ ++/** Find a message queue by name and get a handle to it. ++ * ++ * @param name the name of the queue to find ++ * ++ * @return The message queue, or NULL if not found. ++ */ ++VCOSPRE_ VCOS_MSGQUEUE_T VCOSPOST_ *vcos_msgq_find(const char *name); ++ ++/** Wait for a message queue to come into existence. If it already exists, ++ * return immediately, otherwise block. ++ * ++ * On the whole, if you find yourself using this, it is probably a sign ++ * of poor design, since you should create all the server threads first, ++ * and then the client threads. But it is sometimes useful. ++ * ++ * @param name the name of the queue to find ++ * @return The message queue ++ */ ++VCOSPRE_ VCOS_MSGQUEUE_T VCOSPOST_ *vcos_msgq_wait(const char *name); ++ ++/** Send a message. ++ */ ++VCOSPRE_ void VCOSPOST_ vcos_msg_send(VCOS_MSGQUEUE_T *dest, uint32_t code, VCOS_MSG_T *msg); ++ ++/** Send a message and wait for a reply. ++ */ ++VCOSPRE_ void VCOSPOST_ vcos_msg_sendwait(VCOS_MSGQUEUE_T *queue, uint32_t code, VCOS_MSG_T *msg); ++ ++/** Wait for a message on this thread's endpoint. ++ */ ++VCOSPRE_ VCOS_MSG_T * VCOSPOST_ vcos_msg_wait(void); ++ ++/** Wait for a specific message. ++ */ ++VCOS_MSG_T * vcos_msg_wait_specific(VCOS_MSGQUEUE_T *queue, VCOS_MSG_T *msg); ++ ++/** Peek for a message on this thread's endpoint, if a message is not available, NULL is ++ returned. If a message is available it will be removed from the endpoint and returned. ++ */ ++VCOSPRE_ VCOS_MSG_T * VCOSPOST_ vcos_msg_peek(void); ++ ++/** Send a reply to a message ++ */ ++VCOSPRE_ void VCOSPOST_ vcos_msg_reply(VCOS_MSG_T *msg); ++ ++/** Create an endpoint. Each thread should need no more than one of these - if you ++ * find yourself needing a second one, you've done something wrong. ++ */ ++VCOSPRE_ VCOS_STATUS_T VCOSPOST_ vcos_msgq_endpoint_create(VCOS_MSG_ENDPOINT_T *ep, const char *name); ++ ++/** Destroy an endpoint. ++ */ ++VCOSPRE_ void VCOSPOST_ vcos_msgq_endpoint_delete(VCOS_MSG_ENDPOINT_T *ep); ++ ++#ifdef __cplusplus ++} ++#endif ++#endif ++ ++ +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_mutex.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_mutex.h 2013-07-26 19:37:11.000000000 +0000 +@@ -0,0 +1,103 @@ ++/* ++ * Copyright (c) 2010-2011 Broadcom. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++/*============================================================================= ++VideoCore OS Abstraction Layer - mutex public header file ++=============================================================================*/ ++ ++#ifndef VCOS_MUTEX_H ++#define VCOS_MUTEX_H ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++#include "interface/vcos/vcos_types.h" ++#include "vcos_platform.h" ++ ++/** ++ * \file vcos_mutex.h ++ * ++ * Mutex API. Mutexes are not re-entrant, as supporting this adds extra code ++ * that slows down clients which have been written sensibly. ++ * ++ * \sa vcos_reentrant_mutex.h ++ * ++ */ ++ ++/** Create a mutex. ++ * ++ * @param m Filled in with mutex on return ++ * @param name A non-null name for the mutex, used for diagnostics. ++ * ++ * @return VCOS_SUCCESS if mutex was created, or error code. ++ */ ++VCOS_INLINE_DECL ++VCOS_STATUS_T vcos_mutex_create(VCOS_MUTEX_T *m, const char *name); ++ ++/** Delete the mutex. ++ */ ++VCOS_INLINE_DECL ++void vcos_mutex_delete(VCOS_MUTEX_T *m); ++ ++/** ++ * \brief Wait to claim the mutex. ++ * ++ * On most platforms this always returns VCOS_SUCCESS, and so would ideally be ++ * a void function, however some platforms allow a wait to be interrupted so ++ * it remains non-void. ++ * ++ * Try to obtain the mutex. ++ * @param m Mutex to wait on ++ * @return VCOS_SUCCESS - mutex was taken. ++ * VCOS_EAGAIN - could not take mutex. ++ */ ++#ifndef vcos_mutex_lock ++VCOS_INLINE_DECL ++VCOS_STATUS_T vcos_mutex_lock(VCOS_MUTEX_T *m); ++ ++/** Release the mutex. ++ */ ++VCOS_INLINE_DECL ++void vcos_mutex_unlock(VCOS_MUTEX_T *m); ++#endif ++ ++/** Test if the mutex is already locked. ++ * ++ * @return 1 if mutex is locked, 0 if it is unlocked. ++ */ ++VCOS_INLINE_DECL ++int vcos_mutex_is_locked(VCOS_MUTEX_T *m); ++ ++/** Obtain the mutex if possible. ++ * ++ * @param m the mutex to try to obtain ++ * ++ * @return VCOS_SUCCESS if mutex is succesfully obtained, or VCOS_EAGAIN ++ * if it is already in use by another thread. ++ */ ++#ifndef vcos_mutex_trylock ++VCOS_INLINE_DECL ++VCOS_STATUS_T vcos_mutex_trylock(VCOS_MUTEX_T *m); ++#endif ++ ++ ++#ifdef __cplusplus ++} ++#endif ++#endif +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_once.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_once.h 2013-07-26 19:37:11.000000000 +0000 +@@ -0,0 +1,53 @@ ++/* ++ * Copyright (c) 2010-2011 Broadcom. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++/*============================================================================= ++VideoCore OS Abstraction Layer - 'once' ++=============================================================================*/ ++ ++#ifndef VCOS_ONCE_H ++#define VCOS_ONCE_H ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++#include "interface/vcos/vcos_types.h" ++#include "vcos_platform.h" ++ ++/** ++ * \file vcos_once.h ++ * ++ * Ensure something is called only once. ++ * ++ * Initialize once_control to VCOS_ONCE_INIT. The first ++ * time this is called, the init_routine will be called. Thereafter ++ * it won't. ++ * ++ * \sa pthread_once() ++ * ++ */ ++ ++VCOS_STATUS_T vcos_once(VCOS_ONCE_T *once_control, ++ void (*init_routine)(void)); ++ ++#ifdef __cplusplus ++} ++#endif ++#endif ++ +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_semaphore.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_semaphore.h 2013-07-26 19:37:11.000000000 +0000 +@@ -0,0 +1,126 @@ ++/* ++ * Copyright (c) 2010-2011 Broadcom. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++/*============================================================================= ++VideoCore OS Abstraction Layer - public header file ++=============================================================================*/ ++ ++#ifndef VCOS_SEMAPHORE_H ++#define VCOS_SEMAPHORE_H ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++#include "interface/vcos/vcos_types.h" ++#include "vcos_platform.h" ++ ++/** ++ * \file vcos_semaphore.h ++ * ++ * \section sem Semaphores ++ * ++ * This provides counting semaphores. Semaphores are not re-entrant. On sensible ++ * operating systems a semaphore can always be posted but can only be taken in ++ * thread (not interrupt) context. Under Nucleus, a LISR cannot post a semaphore, ++ * although it would not be hard to lift this restriction. ++ * ++ * \subsection timeout Timeout ++ * ++ * On both Nucleus and ThreadX a semaphore can be taken with a timeout. This is ++ * not supported by VCOS because it makes the non-timeout code considerably more ++ * complicated (and hence slower). In the unlikely event that you need a timeout ++ * with a semaphore, and you cannot simply redesign your code to avoid it, use ++ * an event flag (vcos_event_flags.h). ++ * ++ * \subsection sem_nucleus Changes from Nucleus: ++ * ++ * Semaphores are always "FIFO" - i.e. sleeping threads are woken in FIFO order. That's ++ * because: ++ * \arg there's no support for NU_PRIORITY in threadx (though it can be emulated, slowly) ++ * \arg we don't appear to actually consciously use it - for example, Dispmanx uses ++ * it, but all threads waiting are the same priority. ++ * ++ */ ++ ++/** ++ * \brief Create a semaphore. ++ * ++ * Create a semaphore. ++ * ++ * @param sem Pointer to memory to be initialized ++ * @param name A name for this semaphore. The name may be truncated internally. ++ * @param count The initial count for the semaphore. ++ * ++ * @return VCOS_SUCCESS if the semaphore was created. ++ * ++ */ ++VCOS_INLINE_DECL ++VCOS_STATUS_T vcos_semaphore_create(VCOS_SEMAPHORE_T *sem, const char *name, VCOS_UNSIGNED count); ++ ++/** ++ * \brief Wait on a semaphore. ++ * ++ * There is no timeout option on a semaphore, as adding this will slow down ++ * implementations on some platforms. If you need that kind of behaviour, use ++ * an event group. ++ * ++ * On most platforms this always returns VCOS_SUCCESS, and so would ideally be ++ * a void function, however some platforms allow a wait to be interrupted so ++ * it remains non-void. ++ * ++ * @param sem Semaphore to wait on ++ * @return VCOS_SUCCESS - semaphore was taken. ++ * VCOS_EAGAIN - could not take semaphore ++ * ++ */ ++VCOS_INLINE_DECL ++VCOS_STATUS_T vcos_semaphore_wait(VCOS_SEMAPHORE_T *sem); ++ ++/** ++ * \brief Try to wait for a semaphore. ++ * ++ * Try to obtain the semaphore. If it is already taken, return VCOS_TIMEOUT. ++ * @param sem Semaphore to wait on ++ * @return VCOS_SUCCESS - semaphore was taken. ++ * VCOS_EAGAIN - could not take semaphore ++ */ ++VCOS_INLINE_DECL ++VCOS_STATUS_T vcos_semaphore_trywait(VCOS_SEMAPHORE_T *sem); ++ ++/** ++ * \brief Post a semaphore. ++ * ++ * @param sem Semaphore to wait on ++ */ ++VCOS_INLINE_DECL ++VCOS_STATUS_T vcos_semaphore_post(VCOS_SEMAPHORE_T *sem); ++ ++/** ++ * \brief Delete a semaphore, releasing any resources consumed by it. ++ * ++ * @param sem Semaphore to wait on ++ */ ++VCOS_INLINE_DECL ++void vcos_semaphore_delete(VCOS_SEMAPHORE_T *sem); ++ ++#ifdef __cplusplus ++} ++#endif ++#endif ++ +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_stdbool.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_stdbool.h 2013-07-26 19:37:11.000000000 +0000 +@@ -0,0 +1,34 @@ ++/* ++ * Copyright (c) 2010-2011 Broadcom. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++#ifndef VCOS_STDBOOL_H ++#define VCOS_STDBOOL_H ++ ++#ifndef __cplusplus ++ ++#if defined(__STDC__) && (__STDC_VERSION__ >= 199901L) ++#include ++#else ++typedef enum { ++ false, ++ true ++} bool; ++#endif ++ ++#endif /* __cplusplus */ ++ ++#endif +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_stdint.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_stdint.h 2013-07-26 19:37:11.000000000 +0000 +@@ -0,0 +1,203 @@ ++/* ++ * Copyright (c) 2010-2011 Broadcom. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++#ifndef VCOS_STDINT_H ++#define VCOS_STDINT_H ++ ++/* Attempt to provide the types defined in stdint.h. ++ * ++ * Ideally this would either call out to a platform-specific ++ * header file (e.g. stdint.h) or define the types on a ++ * per-architecture/compiler basis. But for now we just ++ * use #ifdefs. ++ */ ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++#ifdef __SYMBIAN32__ ++ ++typedef signed char int8_t; ++typedef unsigned char uint8_t; ++ ++typedef signed short int16_t; ++typedef unsigned short uint16_t; ++ ++typedef int16_t int_least16_t; ++ ++typedef signed long int32_t; ++typedef unsigned long uint32_t; ++ ++typedef signed long long int64_t; ++typedef unsigned long long uint64_t; ++ ++typedef int32_t intptr_t; ++typedef uint32_t uintptr_t; ++ ++typedef int64_t intmax_t; ++typedef uint64_t uintmax_t; ++ ++#define INT8_MIN SCHAR_MIN ++#define INT8_MAX SCHAR_MAX ++#define UINT8_MAX UCHAR_MAX ++#define INT16_MIN SHRT_MIN ++#define INT16_MAX SHRT_MAX ++#define UINT16_MAX USHRT_MAX ++#define INT32_MIN LONG_MIN ++#define INT32_MAX LONG_MAX ++#define UINT32_MAX ULONG_MAX ++#define INT64_MIN LLONG_MIN ++#define INT64_MAX LLONG_MAX ++#define UINT64_MAX ULLONG_MAX ++ ++#define INTPTR_MIN INT32_MIN ++#define INTPTR_MAX INT32_MAX ++#define UINTPTR_MAX UINT32_MAX ++#define INTMAX_MIN INT64_MIN ++#define INTMAX_MAX INT64_MAX ++#define INT_LEAST16_MAX INT16_MAX ++#define INT_LEAST16_MAX INT16_MAX ++ ++/*{{{ C99 types - THIS WHOLE SECTION IS INCOMPATIBLE WITH C99. IT SHOULD RESIDE IN A STDINT.H SINCE THIS FILE GETS USED ON HOST SIDE */ ++ ++#elif defined( __STDC__ ) && __STDC_VERSION__ >= 199901L ++ ++#include ++ ++#elif defined( __GNUC__ ) ++ ++#include ++ ++#elif defined(_MSC_VER) /* Visual C define equivalent types */ ++ ++#include /* Avoids intptr_t being defined in vadefs.h */ ++ ++typedef __int8 int8_t; ++typedef unsigned __int8 uint8_t; ++ ++typedef __int16 int16_t; ++typedef unsigned __int16 uint16_t; ++ ++typedef __int32 int32_t; ++typedef unsigned __int32 uint32_t; ++ ++typedef __int64 int64_t; ++typedef unsigned __int64 uint64_t; ++typedef uint32_t uintptr_t; ++typedef int64_t intmax_t; ++typedef uint64_t uintmax_t; ++typedef int16_t int_least16_t; ++ ++#elif defined (VCMODS_LCC) ++#include ++ ++typedef signed char int8_t; ++typedef unsigned char uint8_t; ++ ++typedef signed short int16_t; ++typedef unsigned short uint16_t; ++ ++typedef signed long int32_t; ++typedef unsigned long uint32_t; ++ ++typedef signed long int64_t; /*!!!! PFCD, this means code using 64bit numbers will be broken on the VCE */ ++typedef unsigned long uint64_t; /* !!!! PFCD */ ++ ++typedef int32_t intptr_t; ++typedef uint32_t uintptr_t; ++typedef int64_t intmax_t; ++typedef uint64_t uintmax_t; ++typedef int16_t int_least16_t; ++ ++#define INT8_MIN SCHAR_MIN ++#define INT8_MAX SCHAR_MAX ++#define UINT8_MAX UCHAR_MAX ++#define INT16_MIN SHRT_MIN ++#define INT16_MAX SHRT_MAX ++#define UINT16_MAX USHRT_MAX ++#define INT32_MIN LONG_MIN ++#define INT32_MAX LONG_MAX ++#define UINT32_MAX ULONG_MAX ++#define INT64_MIN LONG_MIN /* !!!! PFCD */ ++#define INT64_MAX LONG_MAX /* !!!! PFCD */ ++#define UINT64_MAX ULONG_MAX /* !!!! PFCD */ ++ ++#define INTPTR_MIN INT32_MIN ++#define INTPTR_MAX INT32_MAX ++#define UINTPTR_MAX UINT32_MAX ++#define INTMAX_MIN INT64_MIN ++#define INTMAX_MIN INT64_MIN ++#define INT_LEAST16_MAX INT16_MAX ++#define INT_LEAST16_MAX INT16_MAX ++ ++#elif defined(__VIDEOCORE__) ++ ++typedef signed char int8_t; ++typedef unsigned char uint8_t; ++ ++typedef signed short int16_t; ++typedef unsigned short uint16_t; ++ ++typedef signed long int32_t; ++typedef unsigned long uint32_t; ++ ++typedef signed long long int64_t; ++typedef unsigned long long uint64_t; ++ ++typedef int32_t intptr_t; ++typedef uint32_t uintptr_t; ++typedef int64_t intmax_t; ++typedef uint64_t uintmax_t; ++typedef int16_t int_least16_t; ++ ++#define INT8_MIN SCHAR_MIN ++#define INT8_MAX SCHAR_MAX ++#define UINT8_MAX UCHAR_MAX ++#define INT16_MIN SHRT_MIN ++#define INT16_MAX SHRT_MAX ++#define UINT16_MAX USHRT_MAX ++#define INT32_MIN LONG_MIN ++#define INT32_MAX LONG_MAX ++#define UINT32_MAX ULONG_MAX ++#define INT64_MIN LLONG_MIN ++#define INT64_MAX LLONG_MAX ++#define UINT64_MAX ULLONG_MAX ++ ++#define INTPTR_MIN INT32_MIN ++#define INTPTR_MAX INT32_MAX ++#define UINTPTR_MAX UINT32_MAX ++#define INTMAX_MIN INT64_MIN ++#define INTMAX_MAX INT64_MAX ++#define INT_LEAST16_MAX INT16_MAX ++#define INT_LEAST16_MAX INT16_MAX ++ ++#elif defined (__HIGHC__) && defined(_I386) ++ ++#include ++ ++#else ++#error Unknown platform ++#endif ++ ++#ifdef __cplusplus ++} ++#endif ++#endif /* VCOS_STDINT_H */ ++ ++ +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_string.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_string.h 2013-07-26 19:37:11.000000000 +0000 +@@ -0,0 +1,84 @@ ++/* ++ * Copyright (c) 2010-2011 Broadcom. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++/*============================================================================= ++VideoCore OS Abstraction Layer - public header file ++=============================================================================*/ ++ ++#ifndef VCOS_STRING_H ++#define VCOS_STRING_H ++ ++/** ++ * \file ++ * ++ * String functions. ++ * ++ */ ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++#include "interface/vcos/vcos_types.h" ++#include "vcos_platform.h" ++ ++#ifdef __KERNEL__ ++#include ++#else ++#include ++#endif ++ ++/** Case insensitive string comparison. ++ * ++ */ ++ ++VCOS_INLINE_DECL ++int vcos_strcasecmp(const char *s1, const char *s2); ++ ++VCOS_INLINE_DECL ++int vcos_strncasecmp(const char *s1, const char *s2, size_t n); ++ ++VCOSPRE_ int VCOSPOST_ vcos_vsnprintf( char *buf, size_t buflen, const char *fmt, va_list ap ); ++ ++VCOSPRE_ int VCOSPOST_ vcos_snprintf(char *buf, size_t buflen, const char *fmt, ...); ++ ++VCOS_STATIC_INLINE ++int vcos_strlen(const char *s) { return (int)strlen(s); } ++ ++VCOS_STATIC_INLINE ++int vcos_strcmp(const char *s1, const char *s2) { return strcmp(s1,s2); } ++ ++VCOS_STATIC_INLINE ++int vcos_strncmp(const char *cs, const char *ct, size_t count) { return strncmp(cs, ct, count); } ++ ++VCOS_STATIC_INLINE ++char *vcos_strcpy(char *dst, const char *src) { return strcpy(dst, src); } ++ ++VCOS_STATIC_INLINE ++char *vcos_strncpy(char *dst, const char *src, size_t count) { return strncpy(dst, src, count); } ++ ++VCOS_STATIC_INLINE ++void *vcos_memcpy(void *dst, const void *src, size_t n) { memcpy(dst, src, n); return dst; } ++ ++VCOS_STATIC_INLINE ++void *vcos_memset(void *p, int c, size_t n) { return memset(p, c, n); } ++ ++#ifdef __cplusplus ++} ++#endif ++#endif +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_thread.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_thread.h 2013-07-26 19:37:11.000000000 +0000 +@@ -0,0 +1,270 @@ ++/* ++ * Copyright (c) 2010-2011 Broadcom. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++/*============================================================================= ++VideoCore OS Abstraction Layer - public header file ++=============================================================================*/ ++ ++#ifndef VCOS_THREAD_H ++#define VCOS_THREAD_H ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++#include "interface/vcos/vcos_types.h" ++#include "vcos_platform.h" ++ ++/** ++ * \file vcos_thread.h ++ * ++ * \section thread Threads ++ * ++ * Under Nucleus, a thread is created by NU_Create_Task, passing in the stack ++ * and various other parameters. To stop the thread, NU_Terminate_Thread() and ++ * NU_Delete_Thread() are called. ++ * ++ * Unfortunately it's not possible to emulate this API under some fairly common ++ * operating systems. Under Windows you can't pass in the stack, and you can't ++ * safely terminate a thread. ++ * ++ * Therefore, an API which is similar to the pthreads API is used instead. This ++ * API can (mostly) be emulated under all interesting operating systems. ++ * ++ * Obviously this makes the code somewhat more complicated on VideoCore than it ++ * would otherwise be - we end up with an extra mutex per thread, and some code ++ * that waits for it. The benefit is that we have a single way of creating ++ * threads that works consistently on all platforms (apart from stack supplying). ++ * ++ * \subsection stack Stack ++ * ++ * It's still not possible to pass in the stack address, but this can be made ++ * much more obvious in the API: the relevant function is missing and the ++ * CPP symbol VCOS_CAN_SET_STACK_ADDR is zero rather than one. ++ * ++ * \subsection thr_create Creating a thread ++ * ++ * The simplest way to create a thread is with vcos_thread_create() passing in a ++ * NULL thread parameter argument. To wait for the thread to exit, call ++ * vcos_thread_join(). ++ * ++ * \subsection back Backward compatibility ++ * ++ * To ease migration, a "classic" thread creation API is provided for code ++ * that used to make use of Nucleus, vcos_thread_create_classic(). The ++ * arguments are not exactly the same, as the PREEMPT parameter is dropped. ++ * ++ */ ++ ++#define VCOS_AFFINITY_CPU0 _VCOS_AFFINITY_CPU0 ++#define VCOS_AFFINITY_CPU1 _VCOS_AFFINITY_CPU1 ++#define VCOS_AFFINITY_MASK _VCOS_AFFINITY_MASK ++#define VCOS_AFFINITY_DEFAULT _VCOS_AFFINITY_DEFAULT ++#define VCOS_AFFINITY_THISCPU _VCOS_AFFINITY_THISCPU ++ ++/** Report whether or not we have an RTOS at all, and hence the ability to ++ * create threads. ++ */ ++VCOSPRE_ int VCOSPOST_ vcos_have_rtos(void); ++ ++/** Create a thread. It must be cleaned up by calling vcos_thread_join(). ++ * ++ * @param thread Filled in on return with thread ++ * @param name A name for the thread. May be the empty string. ++ * @param attrs Attributes; default attributes will be used if this is NULL. ++ * @param entry Entry point. ++ * @param arg Argument passed to the entry point. ++ */ ++VCOSPRE_ VCOS_STATUS_T VCOSPOST_ vcos_thread_create(VCOS_THREAD_T *thread, ++ const char *name, ++ VCOS_THREAD_ATTR_T *attrs, ++ VCOS_THREAD_ENTRY_FN_T entry, ++ void *arg); ++ ++/** Exit the thread from within the thread function itself. ++ * Resources must still be cleaned up via a call to thread_join(). ++ * ++ * The thread can also be terminated by simply exiting the thread function. ++ * ++ * @param data Data passed to thread_join. May be NULL. ++ */ ++VCOSPRE_ void VCOSPOST_ vcos_thread_exit(void *data); ++ ++/** Wait for a thread to terminate and then clean up its resources. ++ * ++ * @param thread Thread to wait for ++ * @param pData Updated to point at data provided in vcos_thread_exit or exit ++ * code of thread function. ++ */ ++VCOSPRE_ void VCOSPOST_ vcos_thread_join(VCOS_THREAD_T *thread, ++ void **pData); ++ ++ ++/** ++ * \brief Create a thread using an API similar to the one "traditionally" ++ * used under Nucleus. ++ * ++ * This creates a thread which must be cleaned up by calling vcos_thread_join(). ++ * The thread cannot be simply terminated (as in Nucleus and ThreadX) as thread ++ * termination is not universally supported. ++ * ++ * @param thread Filled in with thread instance ++ * @param name An optional name for the thread. NULL or "" may be used (but ++ * a name will aid in debugging). ++ * @param entry Entry point ++ * @param arg A single argument passed to the entry point function ++ * @param stack Pointer to stack address ++ * @param stacksz Size of stack in bytes ++ * @param priaff Priority of task, between VCOS_PRI_LOW and VCOS_PRI_HIGH, ORed with the CPU affinity ++ * @param autostart If non-zero the thread will start immediately. ++ * @param timeslice Timeslice (system ticks) for this thread. ++ * ++ * @sa vcos_thread_terminate vcos_thread_delete ++ */ ++VCOSPRE_ VCOS_STATUS_T VCOSPOST_ vcos_thread_create_classic(VCOS_THREAD_T *thread, ++ const char *name, ++ void *(*entry)(void *arg), ++ void *arg, ++ void *stack, ++ VCOS_UNSIGNED stacksz, ++ VCOS_UNSIGNED priaff, ++ VCOS_UNSIGNED timeslice, ++ VCOS_UNSIGNED autostart); ++ ++/** ++ * \brief Set a thread's priority ++ * ++ * Set the priority for a thread. ++ * ++ * @param thread The thread ++ * @param pri Thread priority in VCOS_PRI_MASK bits; affinity in VCOS_AFFINITY_MASK bits. ++ */ ++VCOS_INLINE_DECL ++void vcos_thread_set_priority(VCOS_THREAD_T *thread, VCOS_UNSIGNED pri); ++ ++/** ++ * \brief Return the currently executing thread. ++ * ++ */ ++VCOS_INLINE_DECL ++VCOS_THREAD_T *vcos_thread_current(void); ++ ++/** ++ * \brief Return the thread's priority. ++ */ ++VCOS_INLINE_DECL ++VCOS_UNSIGNED vcos_thread_get_priority(VCOS_THREAD_T *thread); ++ ++/** ++ * \brief Return the thread's cpu affinity. ++ */ ++VCOS_INLINE_DECL ++VCOS_UNSIGNED vcos_thread_get_affinity(VCOS_THREAD_T *thread); ++ ++/** ++ * \brief Set the thread's cpu affinity. ++ */ ++ ++VCOS_INLINE_DECL ++void vcos_thread_set_affinity(VCOS_THREAD_T *thread, VCOS_UNSIGNED affinity); ++ ++/** ++ * \brief Query whether we are in an interrupt. ++ * ++ * @return 1 if in interrupt context. ++ */ ++VCOS_INLINE_DECL ++int vcos_in_interrupt(void); ++ ++/** ++ * \brief Sleep a while. ++ * ++ * @param ms Number of milliseconds to sleep for ++ * ++ * This may actually sleep a whole number of ticks. ++ */ ++VCOS_INLINE_DECL ++void vcos_sleep(uint32_t ms); ++ ++/** ++ * \brief Return the value of the hardware microsecond counter. ++ * ++ */ ++VCOS_INLINE_DECL ++uint32_t vcos_getmicrosecs(void); ++ ++#define vcos_get_ms() (vcos_getmicrosecs()/1000) ++ ++/** ++ * \brief Return a unique identifier for the current process ++ * ++ */ ++VCOS_INLINE_DECL ++VCOS_UNSIGNED vcos_process_id_current(void); ++ ++/** Relinquish this time slice. */ ++VCOS_INLINE_DECL ++void vcos_thread_relinquish(void); ++ ++/** Return the name of the given thread. ++ */ ++VCOSPRE_ const char * VCOSPOST_ vcos_thread_get_name(const VCOS_THREAD_T *thread); ++ ++/** Change preemption. This is almost certainly not what you want, as it won't ++ * work reliably in a multicore system: although you can affect the preemption ++ * on *this* core, you won't affect what's happening on the other core(s). ++ * ++ * It's mainly here to ease migration. If you're using it in new code, you ++ * probably need to think again. ++ * ++ * @param pe New preemption, VCOS_PREEMPT or VCOS_NO_PREEMPT ++ * @return Old value of preemption. ++ */ ++VCOS_INLINE_DECL ++VCOS_UNSIGNED vcos_change_preemption(VCOS_UNSIGNED pe); ++ ++/** Is a thread still running, or has it exited? ++ * ++ * Note: this exists for some fairly scary code in the video codec tests. Don't ++ * try to use it for anything else, as it may well not do what you expect. ++ * ++ * @param thread thread to query ++ * @return non-zero if thread is running, or zero if it has exited. ++ */ ++VCOS_INLINE_DECL ++int vcos_thread_running(VCOS_THREAD_T *thread); ++ ++/** Resume a thread. ++ * ++ * @param thread thread to resume ++ */ ++VCOS_INLINE_DECL ++void vcos_thread_resume(VCOS_THREAD_T *thread); ++ ++/* ++ * Internal APIs - may not always be present and should not be used in ++ * client code. ++ */ ++ ++extern void _vcos_task_timer_set(void (*pfn)(void*), void *, VCOS_UNSIGNED ms); ++extern void _vcos_task_timer_cancel(void); ++ ++#ifdef __cplusplus ++} ++#endif ++#endif +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_thread_attr.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_thread_attr.h 2013-07-26 19:37:11.000000000 +0000 +@@ -0,0 +1,87 @@ ++/* ++ * Copyright (c) 2010-2011 Broadcom. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++/*============================================================================= ++VideoCore OS Abstraction Layer - thread attributes ++=============================================================================*/ ++ ++#ifndef VCOS_THREAD_ATTR_H ++#define VCOS_THREAD_ATTR_H ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/** ++ * \file ++ * ++ * Attributes for thread creation. ++ * ++ */ ++ ++/** Initialize thread attribute struct. This call does not allocate memory, ++ * and so cannot fail. ++ * ++ */ ++VCOSPRE_ void VCOSPOST_ vcos_thread_attr_init(VCOS_THREAD_ATTR_T *attrs); ++ ++/** Set the stack address and size. If not set, a stack will be allocated automatically. ++ * ++ * This can only be set on some platforms. It will always be possible to set the stack ++ * address on VideoCore, but on host platforms, support may well not be available. ++ */ ++#if VCOS_CAN_SET_STACK_ADDR ++VCOS_INLINE_DECL ++void vcos_thread_attr_setstack(VCOS_THREAD_ATTR_T *attrs, void *addr, VCOS_UNSIGNED sz); ++#endif ++ ++/** Set the stack size. If not set, a default size will be used. Attempting to call this after having ++ * set the stack location with vcos_thread_attr_setstack() will result in undefined behaviour. ++ */ ++VCOS_INLINE_DECL ++void vcos_thread_attr_setstacksize(VCOS_THREAD_ATTR_T *attrs, VCOS_UNSIGNED sz); ++ ++/** Set the task priority. If not set, a default value will be used. ++ */ ++VCOS_INLINE_DECL ++void vcos_thread_attr_setpriority(VCOS_THREAD_ATTR_T *attrs, VCOS_UNSIGNED pri); ++ ++/** Set the task cpu affinity. If not set, the default will be used. ++ */ ++VCOS_INLINE_DECL ++void vcos_thread_attr_setaffinity(VCOS_THREAD_ATTR_T *attrs, VCOS_UNSIGNED aff); ++ ++/** Set the timeslice. If not set the default will be used. ++ */ ++VCOS_INLINE_DECL ++void vcos_thread_attr_settimeslice(VCOS_THREAD_ATTR_T *attrs, VCOS_UNSIGNED ts); ++ ++/** The thread entry function takes (argc,argv), as per Nucleus, with ++ * argc being 0. This may be withdrawn in a future release and should not ++ * be used in new code. ++ */ ++VCOS_INLINE_DECL ++void _vcos_thread_attr_setlegacyapi(VCOS_THREAD_ATTR_T *attrs, VCOS_UNSIGNED legacy); ++ ++VCOS_INLINE_DECL ++void vcos_thread_attr_setautostart(VCOS_THREAD_ATTR_T *attrs, VCOS_UNSIGNED autostart); ++ ++#ifdef __cplusplus ++} ++#endif ++#endif +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_timer.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_timer.h 2013-07-26 19:37:11.000000000 +0000 +@@ -0,0 +1,106 @@ ++/* ++ * Copyright (c) 2010-2011 Broadcom. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++/*============================================================================= ++VideoCore OS Abstraction Layer - timer support ++=============================================================================*/ ++ ++#ifndef VCOS_TIMER_H ++#define VCOS_TIMER_H ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++#include "interface/vcos/vcos_types.h" ++#include "vcos_platform.h" ++ ++/** \file vcos_timer.h ++ * ++ * Timers are single shot. ++ * ++ * Timer times are in milliseconds. ++ * ++ * \note that timer callback functions are called from an arbitrary thread ++ * context. The expiration function should do its work as quickly as possible; ++ * blocking should be avoided. ++ * ++ * \note On Windows, the separate function vcos_timer_init() must be called ++ * as timer initialization from DllMain is not possible. ++ */ ++ ++/** Perform timer subsystem initialization. This function is not needed ++ * on non-Windows platforms but is still present so that it can be ++ * called. On Windows it is needed because vcos_init() gets called ++ * from DLL initialization where it is not possible to create a ++ * time queue (deadlock occurs if you try). ++ * ++ * @return VCOS_SUCCESS on success. VCOS_EEXIST if this has already been called ++ * once. VCOS_ENOMEM if resource allocation failed. ++ */ ++VCOSPRE_ VCOS_STATUS_T VCOSPOST_ vcos_timer_init(void); ++ ++/** Create a timer in a disabled state. ++ * ++ * The timer is initially disabled. ++ * ++ * @param timer timer handle ++ * @param name name for timer ++ * @param expiration_routine function to call when timer expires ++ * @param context context passed to expiration routine ++ * ++ */ ++VCOS_INLINE_DECL ++VCOS_STATUS_T vcos_timer_create(VCOS_TIMER_T *timer, ++ const char *name, ++ void (*expiration_routine)(void *context), ++ void *context); ++ ++ ++ ++/** Start a timer running. ++ * ++ * Timer must be stopped. ++ * ++ * @param timer timer handle ++ * @param delay Delay to wait for, in ms ++ */ ++VCOS_INLINE_DECL ++void vcos_timer_set(VCOS_TIMER_T *timer, VCOS_UNSIGNED delay); ++ ++/** Stop an already running timer. ++ * ++ * @param timer timer handle ++ */ ++VCOS_INLINE_DECL ++void vcos_timer_cancel(VCOS_TIMER_T *timer); ++ ++/** Stop a timer and restart it. ++ * @param timer timer handle ++ * @param delay delay in ms ++ */ ++VCOS_INLINE_DECL ++void vcos_timer_reset(VCOS_TIMER_T *timer, VCOS_UNSIGNED delay); ++ ++VCOS_INLINE_DECL ++void vcos_timer_delete(VCOS_TIMER_T *timer); ++ ++#ifdef __cplusplus ++} ++#endif ++#endif +Index: linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_types.h +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/misc/vc04_services/interface/vcos/vcos_types.h 2013-07-26 19:37:11.000000000 +0000 +@@ -0,0 +1,211 @@ ++/* ++ * Copyright (c) 2010-2011 Broadcom. All rights reserved. ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++/*============================================================================= ++VideoCore OS Abstraction Layer - basic types ++=============================================================================*/ ++ ++#ifndef VCOS_TYPES_H ++#define VCOS_TYPES_H ++ ++#define VCOS_VERSION 1 ++ ++#include "vcos_platform_types.h" ++ ++#if !defined(VCOSPRE_) || !defined(VCOSPOST_) ++#error VCOSPRE_ and VCOSPOST_ not defined! ++#endif ++ ++/* Redefine these here; this means that existing header files can carry on ++ * using the VCHPOST/VCHPRE macros rather than having huge changes, which ++ * could cause nasty merge problems. ++ */ ++#ifndef VCHPOST_ ++#define VCHPOST_ VCOSPOST_ ++#endif ++#ifndef VCHPRE_ ++#define VCHPRE_ VCOSPRE_ ++#endif ++ ++/** Entry function for a lowlevel thread. ++ * ++ * Returns void for consistency with Nucleus/ThreadX. ++ */ ++typedef void (*VCOS_LLTHREAD_ENTRY_FN_T)(void *); ++ ++/** Thread entry point. Returns a void* for consistency ++ * with pthreads. ++ */ ++typedef void *(*VCOS_THREAD_ENTRY_FN_T)(void*); ++ ++ ++/* Error return codes - chosen to be similar to errno values */ ++typedef enum ++{ ++ VCOS_SUCCESS, ++ VCOS_EAGAIN, ++ VCOS_ENOENT, ++ VCOS_ENOSPC, ++ VCOS_EINVAL, ++ VCOS_EACCESS, ++ VCOS_ENOMEM, ++ VCOS_ENOSYS, ++ VCOS_EEXIST, ++ VCOS_ENXIO, ++ VCOS_EINTR ++} VCOS_STATUS_T; ++ ++/* Some compilers (MetaWare) won't inline with -g turned on, which then results ++ * in a lot of code bloat. To overcome this, inline functions are forward declared ++ * with the prefix VCOS_INLINE_DECL, and implemented with the prefix VCOS_INLINE_IMPL. ++ * ++ * That then means that in a release build, "static inline" can be used in the obvious ++ * way, but in a debug build the implementations can be skipped in all but one file, ++ * by using VCOS_INLINE_BODIES. ++ * ++ * VCOS_INLINE_DECL - put this at the start of an inline forward declaration of a VCOS ++ * function. ++ * ++ * VCOS_INLINE_IMPL - put this at the start of an inlined implementation of a VCOS ++ * function. ++ * ++ */ ++ ++/* VCOS_EXPORT - it turns out that in some circumstances we need the implementation of ++ * a function even if it is usually inlined. ++ * ++ * In particular, if we have a codec that is usually provided in object form, if it ++ * was built for a debug build it will be full of calls to vcos_XXX(). If this is used ++ * in a *release* build, then there won't be any of these calls around in the main image ++ * as they will all have been inlined. The problem also exists for vcos functions called ++ * from assembler. ++ * ++ * VCOS_EXPORT ensures that the named function will be emitted as a regular (not static-inline) ++ * function inside vcos_.c so that it can be linked against. Doing this for every ++ * VCOS function would be a bit code-bloat-tastic, so it is only done for those that need it. ++ * ++ */ ++ ++#ifdef __cplusplus ++#define _VCOS_INLINE inline ++#else ++#define _VCOS_INLINE __inline ++#endif ++ ++#if defined(NDEBUG) ++ ++#ifdef __GNUC__ ++# define VCOS_INLINE_DECL extern __inline__ ++# define VCOS_INLINE_IMPL static __inline__ ++#else ++# define VCOS_INLINE_DECL static _VCOS_INLINE /* declare a func */ ++# define VCOS_INLINE_IMPL static _VCOS_INLINE /* implement a func inline */ ++#endif ++ ++# if defined(VCOS_WANT_IMPL) ++# define VCOS_EXPORT ++# else ++# define VCOS_EXPORT VCOS_INLINE_IMPL ++# endif /* VCOS_WANT_IMPL */ ++ ++#define VCOS_INLINE_BODIES ++ ++#else /* NDEBUG */ ++ ++#if !defined(VCOS_INLINE_DECL) ++ #define VCOS_INLINE_DECL extern ++#endif ++#if !defined(VCOS_INLINE_IMPL) ++ #define VCOS_INLINE_IMPL ++#endif ++#define VCOS_EXPORT VCOS_INLINE_IMPL ++#endif ++ ++#define VCOS_STATIC_INLINE static _VCOS_INLINE ++ ++#if defined(__HIGHC__) || defined(__HIGHC_ANSI__) ++#define _VCOS_METAWARE ++#endif ++ ++/** It seems that __FUNCTION__ isn't standard! ++ */ ++#if __STDC_VERSION__ < 199901L ++# if __GNUC__ >= 2 || defined(__VIDEOCORE__) ++# define VCOS_FUNCTION __FUNCTION__ ++# else ++# define VCOS_FUNCTION "" ++# endif ++#else ++# define VCOS_FUNCTION __func__ ++#endif ++ ++#define _VCOS_MS_PER_TICK (1000/VCOS_TICKS_PER_SECOND) ++ ++/* Convert a number of milliseconds to a tick count. Internal use only - fails to ++ * convert VCOS_SUSPEND correctly. ++ */ ++#define _VCOS_MS_TO_TICKS(ms) (((ms)+_VCOS_MS_PER_TICK-1)/_VCOS_MS_PER_TICK) ++ ++#define VCOS_TICKS_TO_MS(ticks) ((ticks) * _VCOS_MS_PER_TICK) ++ ++/** VCOS version of DATESTR, from pcdisk.h. Used by the hostreq service. ++ */ ++typedef struct vcos_datestr ++{ ++ uint8_t cmsec; /**< Centesimal mili second */ ++ uint16_t date; /**< Date */ ++ uint16_t time; /**< Time */ ++ ++} VCOS_DATESTR; ++ ++/* Compile-time assert - declares invalid array length if condition ++ * not met, or array of length one if OK. ++ */ ++#define VCOS_CASSERT(e) extern char vcos_compile_time_check[1/(e)] ++ ++#define vcos_min(x,y) ((x) < (y) ? (x) : (y)) ++#define vcos_max(x,y) ((x) > (y) ? (x) : (y)) ++ ++/** Return the count of an array. FIXME: under gcc we could make ++ * this report an error for pointers using __builtin_types_compatible(). ++ */ ++#define vcos_countof(x) (sizeof((x)) / sizeof((x)[0])) ++ ++/* for backward compatibility */ ++#define countof(x) (sizeof((x)) / sizeof((x)[0])) ++ ++#define VCOS_ALIGN_DOWN(p,n) (((ptrdiff_t)(p)) & ~((n)-1)) ++#define VCOS_ALIGN_UP(p,n) VCOS_ALIGN_DOWN((ptrdiff_t)(p)+(n)-1,(n)) ++ ++/** bool_t is not a POSIX type so cannot rely on it. Define it here. ++ * It's not even defined in stdbool.h. ++ */ ++typedef int32_t vcos_bool_t; ++typedef int32_t vcos_fourcc_t; ++ ++#define VCOS_FALSE 0 ++#define VCOS_TRUE (!VCOS_FALSE) ++ ++/** Mark unused arguments to keep compilers quiet */ ++#define vcos_unused(x) (void)(x) ++ ++/** For backward compatibility */ ++typedef vcos_fourcc_t fourcc_t; ++typedef vcos_fourcc_t FOURCC_T; ++ ++#endif +Index: linux-3.2.46/sound/arm/bcm2835-vchiq.c +=================================================================== +--- linux-3.2.46.orig/sound/arm/bcm2835-vchiq.c 2013-07-26 19:36:51.000000000 +0000 ++++ linux-3.2.46/sound/arm/bcm2835-vchiq.c 2013-07-26 19:37:11.000000000 +0000 +@@ -226,7 +226,6 @@ + /* Open the VCHI service connections */ + for (i = 0; i < num_connections; i++) { + SERVICE_CREATION_T params = { +- VCHI_VERSION(VC_AUDIOSERV_VER), // version + VC_AUDIO_SERVER_NAME, // 4cc service code + vchi_connections[i], // passed in fn pointers + 0, // rx fifo size (unused) +Index: linux-3.2.46/sound/arm/vc_vchi_audioserv_defs.h +=================================================================== +--- linux-3.2.46.orig/sound/arm/vc_vchi_audioserv_defs.h 2013-07-26 19:36:51.000000000 +0000 ++++ linux-3.2.46/sound/arm/vc_vchi_audioserv_defs.h 2013-07-26 19:37:11.000000000 +0000 +@@ -15,8 +15,6 @@ + #ifndef _VC_AUDIO_DEFS_H_ + #define _VC_AUDIO_DEFS_H_ + +-#define VC_AUDIOSERV_VER 1 +- + // FourCC code used for VCHI connection + #define VC_AUDIO_SERVER_NAME MAKE_FOURCC("AUDS") + diff -Nru linux-3.2.46/debian/patches/rpi/rpi_269_42a864b123a47542aa0db530e0f4fe10851faaf2.patch linux-3.2.46/debian/patches/rpi/rpi_269_42a864b123a47542aa0db530e0f4fe10851faaf2.patch --- linux-3.2.46/debian/patches/rpi/rpi_269_42a864b123a47542aa0db530e0f4fe10851faaf2.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_269_42a864b123a47542aa0db530e0f4fe10851faaf2.patch 2013-07-26 19:37:18.000000000 +0000 @@ -0,0 +1,19 @@ +commit 42a864b123a47542aa0db530e0f4fe10851faaf2 +Author: Gordon Hollingworth +Date: Sun Nov 4 15:55:01 2012 +0000 + + Make sure we wait for the reset to finish + +Index: linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c +=================================================================== +--- linux-3.2.46.orig/drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c 2013-07-26 19:36:32.000000000 +0000 ++++ linux-3.2.46/drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c 2013-07-26 19:37:18.000000000 +0000 +@@ -232,6 +232,8 @@ + if (mphi_int_count >= 60) + { + DWC_WRITE_REG32(c_mphi_regs.ctrl, ((1<<31) + (1<<16))); ++ while(!(DWC_READ_REG32(c_mphi_regs.ctrl) & (1 << 17))) ++ ; + DWC_WRITE_REG32(c_mphi_regs.ctrl, (1<<31)); + mphi_int_count = 0; + } diff -Nru linux-3.2.46/debian/patches/rpi/rpi_270_fc155d9d85bfc936a9c04798ffa04fa7dc73ca3b.patch linux-3.2.46/debian/patches/rpi/rpi_270_fc155d9d85bfc936a9c04798ffa04fa7dc73ca3b.patch --- linux-3.2.46/debian/patches/rpi/rpi_270_fc155d9d85bfc936a9c04798ffa04fa7dc73ca3b.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_270_fc155d9d85bfc936a9c04798ffa04fa7dc73ca3b.patch 2013-07-26 19:37:20.000000000 +0000 @@ -0,0 +1,27 @@ +commit fc155d9d85bfc936a9c04798ffa04fa7dc73ca3b +Author: popcornmix +Date: Sun Nov 4 17:02:59 2012 +0000 + + Add missing pctv452e DVB module + +Index: linux-3.2.46/arch/arm/configs/bcmrpi_defconfig +=================================================================== +--- linux-3.2.46.orig/arch/arm/configs/bcmrpi_defconfig 2013-07-26 19:36:39.000000000 +0000 ++++ linux-3.2.46/arch/arm/configs/bcmrpi_defconfig 2013-07-26 19:37:19.000000000 +0000 +@@ -585,6 +585,7 @@ + CONFIG_DVB_USB_OPERA1=m + CONFIG_DVB_USB_AF9005=m + CONFIG_DVB_USB_AF9005_REMOTE=m ++CONFIG_DVB_USB_PCTV452E=m + CONFIG_DVB_USB_DW2102=m + CONFIG_DVB_USB_CINERGY_T2=m + CONFIG_DVB_USB_ANYSEE=m +@@ -596,6 +597,8 @@ + CONFIG_DVB_USB_AZ6027=m + CONFIG_DVB_USB_LME2510=m + CONFIG_DVB_USB_TECHNISAT_USB2=m ++CONFIG_DVB_USB_IT913X=m ++CONFIG_DVB_USB_MXL111SF=m + CONFIG_SMS_SIANO_MDTV=m + CONFIG_SMS_USB_DRV=m + CONFIG_DVB_B2C2_FLEXCOP=m diff -Nru linux-3.2.46/debian/patches/rpi/rpi_271_df41b42914892c539de4ec16a6d9184d031ae0bf.patch linux-3.2.46/debian/patches/rpi/rpi_271_df41b42914892c539de4ec16a6d9184d031ae0bf.patch --- linux-3.2.46/debian/patches/rpi/rpi_271_df41b42914892c539de4ec16a6d9184d031ae0bf.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_271_df41b42914892c539de4ec16a6d9184d031ae0bf.patch 2013-07-26 19:37:21.000000000 +0000 @@ -0,0 +1,41 @@ +commit df41b42914892c539de4ec16a6d9184d031ae0bf +Author: Kamal Mostafa +Date: Mon Oct 22 15:52:44 2012 -0700 + + spi/spi-bcm2708: respect per-transfer SPI clock speed_hz value + + The bcm2708 SPI driver's bcm2708_process_transfer() was ignoring the + per-transfer speed_hz value even when it was provided (it always just + used the spi device's max_speed_hz value). Now, per-transfer speed_hz + values are respected. + + Also added debug print to bcm2708_setup_state() to help keep an eye on + the configured SPI parameters. + + Signed-off-by: Kamal Mostafa + +Index: linux-3.2.46/drivers/spi/spi-bcm2708.c +=================================================================== +--- linux-3.2.46.orig/drivers/spi/spi-bcm2708.c 2013-07-26 19:33:55.000000000 +0000 ++++ linux-3.2.46/drivers/spi/spi-bcm2708.c 2013-07-26 19:37:20.000000000 +0000 +@@ -259,6 +259,10 @@ + if (state) { + state->cs = cs; + state->cdiv = cdiv; ++ dev_dbg(dev, "setup: want %d Hz; " ++ "bus_hz=%lu / cdiv=%u == %lu Hz; " ++ "mode %u: cs 0x%08X\n", ++ hz, bus_hz, cdiv, bus_hz/cdiv, mode, cs); + } + + return 0; +@@ -277,7 +281,8 @@ + + if (xfer->bits_per_word || xfer->speed_hz) { + ret = bcm2708_setup_state(spi->master, &spi->dev, &state, +- spi->max_speed_hz, spi->chip_select, spi->mode, ++ xfer->speed_hz ? xfer->speed_hz : spi->max_speed_hz, ++ spi->chip_select, spi->mode, + spi->bits_per_word); + if (ret) + return ret; diff -Nru linux-3.2.46/debian/patches/rpi/rpi_272_91abd8700cc73dff72332135c4bdf4cdf7afe2b1.patch linux-3.2.46/debian/patches/rpi/rpi_272_91abd8700cc73dff72332135c4bdf4cdf7afe2b1.patch --- linux-3.2.46/debian/patches/rpi/rpi_272_91abd8700cc73dff72332135c4bdf4cdf7afe2b1.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_272_91abd8700cc73dff72332135c4bdf4cdf7afe2b1.patch 2013-07-26 19:37:23.000000000 +0000 @@ -0,0 +1,727 @@ +commit 91abd8700cc73dff72332135c4bdf4cdf7afe2b1 +Author: Aron Szabo +Date: Sat Jun 16 12:15:55 2012 +0200 + + lirc: added support for RaspberryPi GPIO + +Index: linux-3.2.46/drivers/staging/media/lirc/Kconfig +=================================================================== +--- linux-3.2.46.orig/drivers/staging/media/lirc/Kconfig 2013-05-30 13:35:16.000000000 +0000 ++++ linux-3.2.46/drivers/staging/media/lirc/Kconfig 2013-07-26 19:37:22.000000000 +0000 +@@ -38,6 +38,12 @@ + help + Driver for Homebrew Parallel Port Receivers + ++config LIRC_RPI ++ tristate "Homebrew GPIO Port Receiver/Transmitter for the RaspberryPi" ++ depends on LIRC ++ help ++ Driver for Homebrew GPIO Port Receiver/Transmitter for the RaspberryPi ++ + config LIRC_SASEM + tristate "Sasem USB IR Remote" + depends on LIRC && USB +Index: linux-3.2.46/drivers/staging/media/lirc/Makefile +=================================================================== +--- linux-3.2.46.orig/drivers/staging/media/lirc/Makefile 2013-05-30 13:35:16.000000000 +0000 ++++ linux-3.2.46/drivers/staging/media/lirc/Makefile 2013-07-26 19:37:22.000000000 +0000 +@@ -7,6 +7,7 @@ + obj-$(CONFIG_LIRC_IGORPLUGUSB) += lirc_igorplugusb.o + obj-$(CONFIG_LIRC_IMON) += lirc_imon.o + obj-$(CONFIG_LIRC_PARALLEL) += lirc_parallel.o ++obj-$(CONFIG_LIRC_RPI) += lirc_rpi.o + obj-$(CONFIG_LIRC_SASEM) += lirc_sasem.o + obj-$(CONFIG_LIRC_SERIAL) += lirc_serial.o + obj-$(CONFIG_LIRC_SIR) += lirc_sir.o +Index: linux-3.2.46/drivers/staging/media/lirc/lirc_rpi.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/drivers/staging/media/lirc/lirc_rpi.c 2013-07-26 19:37:22.000000000 +0000 +@@ -0,0 +1,687 @@ ++/* ++ * lirc_rpi.c ++ * ++ * lirc_rpi - Device driver that records pulse- and pause-lengths ++ * (space-lengths) (just like the lirc_serial driver does) ++ * between GPIO interrupt events on the Raspberry Pi. ++ * Lots of code has been taken from the lirc_serial module, ++ * so I would like say thanks to the authors. ++ * ++ * Copyright (C) 2012 Aron Robert Szabo , ++ * Michael Bishop ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define LIRC_DRIVER_NAME "lirc_rpi" ++#define RBUF_LEN 256 ++#define LIRC_TRANSMITTER_LATENCY 256 ++ ++#ifndef MAX_UDELAY_MS ++#define MAX_UDELAY_US 5000 ++#else ++#define MAX_UDELAY_US (MAX_UDELAY_MS*1000) ++#endif ++ ++#define dprintk(fmt, args...) \ ++ do { \ ++ if (debug) \ ++ printk(KERN_DEBUG LIRC_DRIVER_NAME ": " \ ++ fmt, ## args); \ ++ } while (0) ++ ++/* module parameters */ ++ ++/* set the default GPIO input pin */ ++static int gpio_in_pin = 18; ++/* set the default GPIO output pin */ ++static int gpio_out_pin = 17; ++/* enable debugging messages */ ++static int debug; ++/* -1 = auto, 0 = active high, 1 = active low */ ++static int sense = -1; ++/* use softcarrier by default */ ++static int softcarrier = 1; ++ ++struct gpio_chip *gpiochip; ++struct irq_chip *irqchip; ++struct irq_data *irqdata; ++ ++/* forward declarations */ ++static long send_pulse(unsigned long length); ++static void send_space(long length); ++static void lirc_rpi_exit(void); ++ ++int valid_gpio_pins[] = { 0, 1, 4, 8, 7, 9, 10, 11, 14, 15, 17, 18, 21, 22, 23, ++ 24, 25 }; ++ ++static struct platform_device *lirc_rpi_dev; ++static struct timeval lasttv = { 0, 0 }; ++static struct lirc_buffer rbuf; ++static spinlock_t lock; ++ ++/* initialized/set in init_timing_params() */ ++static unsigned int freq = 38000; ++static unsigned int duty_cycle = 50; ++static unsigned long period; ++static unsigned long pulse_width; ++static unsigned long space_width; ++ ++static void safe_udelay(unsigned long usecs) ++{ ++ while (usecs > MAX_UDELAY_US) { ++ udelay(MAX_UDELAY_US); ++ usecs -= MAX_UDELAY_US; ++ } ++ udelay(usecs); ++} ++ ++static int init_timing_params(unsigned int new_duty_cycle, ++ unsigned int new_freq) ++{ ++ /* ++ * period, pulse/space width are kept with 8 binary places - ++ * IE multiplied by 256. ++ */ ++ if (256 * 1000000L / new_freq * new_duty_cycle / 100 <= ++ LIRC_TRANSMITTER_LATENCY) ++ return -EINVAL; ++ if (256 * 1000000L / new_freq * (100 - new_duty_cycle) / 100 <= ++ LIRC_TRANSMITTER_LATENCY) ++ return -EINVAL; ++ duty_cycle = new_duty_cycle; ++ freq = new_freq; ++ period = 256 * 1000000L / freq; ++ pulse_width = period * duty_cycle / 100; ++ space_width = period - pulse_width; ++ dprintk("in init_timing_params, freq=%d pulse=%ld, " ++ "space=%ld\n", freq, pulse_width, space_width); ++ return 0; ++} ++ ++static long send_pulse_softcarrier(unsigned long length) ++{ ++ int flag; ++ unsigned long actual, target, d; ++ ++ length <<= 8; ++ ++ actual = 0; target = 0; flag = 0; ++ while (actual < length) { ++ if (flag) { ++ gpiochip->set(gpiochip, gpio_out_pin, 0); ++ target += space_width; ++ } else { ++ gpiochip->set(gpiochip, gpio_out_pin, 1); ++ target += pulse_width; ++ } ++ d = (target - actual - ++ LIRC_TRANSMITTER_LATENCY + 128) >> 8; ++ /* ++ * Note - we've checked in ioctl that the pulse/space ++ * widths are big enough so that d is > 0 ++ */ ++ udelay(d); ++ actual += (d << 8) + LIRC_TRANSMITTER_LATENCY; ++ flag = !flag; ++ } ++ return (actual-length) >> 8; ++} ++ ++static long send_pulse(unsigned long length) ++{ ++ if (length <= 0) ++ return 0; ++ ++ if (softcarrier) { ++ return send_pulse_softcarrier(length); ++ } else { ++ gpiochip->set(gpiochip, gpio_out_pin, 1); ++ safe_udelay(length); ++ return 0; ++ } ++} ++ ++static void send_space(long length) ++{ ++ gpiochip->set(gpiochip, gpio_out_pin, 0); ++ if (length <= 0) ++ return; ++ safe_udelay(length); ++} ++ ++static void rbwrite(int l) ++{ ++ if (lirc_buffer_full(&rbuf)) { ++ /* no new signals will be accepted */ ++ dprintk("Buffer overrun\n"); ++ return; ++ } ++ lirc_buffer_write(&rbuf, (void *)&l); ++} ++ ++static void frbwrite(int l) ++{ ++ /* simple noise filter */ ++ static int pulse, space; ++ static unsigned int ptr; ++ ++ if (ptr > 0 && (l & PULSE_BIT)) { ++ pulse += l & PULSE_MASK; ++ if (pulse > 250) { ++ rbwrite(space); ++ rbwrite(pulse | PULSE_BIT); ++ ptr = 0; ++ pulse = 0; ++ } ++ return; ++ } ++ if (!(l & PULSE_BIT)) { ++ if (ptr == 0) { ++ if (l > 20000) { ++ space = l; ++ ptr++; ++ return; ++ } ++ } else { ++ if (l > 20000) { ++ space += pulse; ++ if (space > PULSE_MASK) ++ space = PULSE_MASK; ++ space += l; ++ if (space > PULSE_MASK) ++ space = PULSE_MASK; ++ pulse = 0; ++ return; ++ } ++ rbwrite(space); ++ rbwrite(pulse | PULSE_BIT); ++ ptr = 0; ++ pulse = 0; ++ } ++ } ++ rbwrite(l); ++} ++ ++static irqreturn_t irq_handler(int i, void *blah, struct pt_regs *regs) ++{ ++ struct timeval tv; ++ long deltv; ++ int data; ++ int signal; ++ ++ /* use the GPIO signal level */ ++ signal = gpiochip->get(gpiochip, gpio_in_pin); ++ ++ /* unmask the irq */ ++ irqchip->irq_unmask(irqdata); ++ ++ if (sense != -1) { ++ /* get current time */ ++ do_gettimeofday(&tv); ++ ++ /* calc time since last interrupt in microseconds */ ++ deltv = tv.tv_sec-lasttv.tv_sec; ++ if (tv.tv_sec < lasttv.tv_sec || ++ (tv.tv_sec == lasttv.tv_sec && ++ tv.tv_usec < lasttv.tv_usec)) { ++ printk(KERN_WARNING LIRC_DRIVER_NAME ++ ": AIEEEE: your clock just jumped backwards\n"); ++ printk(KERN_WARNING LIRC_DRIVER_NAME ++ ": %d %d %lx %lx %lx %lx\n", signal, sense, ++ tv.tv_sec, lasttv.tv_sec, ++ tv.tv_usec, lasttv.tv_usec); ++ data = PULSE_MASK; ++ } else if (deltv > 15) { ++ data = PULSE_MASK; /* really long time */ ++ if (!(signal^sense)) { ++ /* sanity check */ ++ printk(KERN_WARNING LIRC_DRIVER_NAME ++ ": AIEEEE: %d %d %lx %lx %lx %lx\n", ++ signal, sense, tv.tv_sec, lasttv.tv_sec, ++ tv.tv_usec, lasttv.tv_usec); ++ /* ++ * detecting pulse while this ++ * MUST be a space! ++ */ ++ sense = sense ? 0 : 1; ++ } ++ } else { ++ data = (int) (deltv*1000000 + ++ (tv.tv_usec - lasttv.tv_usec)); ++ } ++ frbwrite(signal^sense ? data : (data|PULSE_BIT)); ++ lasttv = tv; ++ wake_up_interruptible(&rbuf.wait_poll); ++ } ++ ++ return IRQ_HANDLED; ++} ++ ++static int is_right_chip(struct gpio_chip *chip, void *data) ++{ ++ dprintk("is_right_chip %s %d\n", chip->label, strcmp(data, chip->label)); ++ ++ if (strcmp(data, chip->label) == 0) ++ return 1; ++ return 0; ++} ++ ++static int init_port(void) ++{ ++ int i, nlow, nhigh, ret, irq; ++ ++ gpiochip = gpiochip_find("bcm2708_gpio", is_right_chip); ++ ++ if (!gpiochip) ++ return -ENODEV; ++ ++ if (gpio_request(gpio_out_pin, LIRC_DRIVER_NAME " ir/out")) { ++ printk(KERN_ALERT LIRC_DRIVER_NAME ++ ": cant claim gpio pin %d\n", gpio_out_pin); ++ ret = -ENODEV; ++ goto exit_init_port; ++ } ++ ++ if (gpio_request(gpio_in_pin, LIRC_DRIVER_NAME " ir/in")) { ++ printk(KERN_ALERT LIRC_DRIVER_NAME ++ ": cant claim gpio pin %d\n", gpio_in_pin); ++ ret = -ENODEV; ++ goto exit_gpio_free_out_pin; ++ } ++ ++ gpiochip->direction_input(gpiochip, gpio_in_pin); ++ gpiochip->direction_output(gpiochip, gpio_out_pin, 1); ++ gpiochip->set(gpiochip, gpio_out_pin, 0); ++ ++ irq = gpiochip->to_irq(gpiochip, gpio_in_pin); ++ dprintk("to_irq %d\n", irq); ++ irqdata = irq_get_irq_data(irq); ++ ++ if (irqdata && irqdata->chip) { ++ irqchip = irqdata->chip; ++ } else { ++ ret = -ENODEV; ++ goto exit_gpio_free_in_pin; ++ } ++ ++ /* if pin is high, then this must be an active low receiver. */ ++ if (sense == -1) { ++ /* wait 1/2 sec for the power supply */ ++ msleep(500); ++ ++ /* ++ * probe 9 times every 0.04s, collect "votes" for ++ * active high/low ++ */ ++ nlow = 0; ++ nhigh = 0; ++ for (i = 0; i < 9; i++) { ++ if (gpiochip->get(gpiochip, gpio_in_pin)) ++ nlow++; ++ else ++ nhigh++; ++ msleep(40); ++ } ++ sense = (nlow >= nhigh ? 1 : 0); ++ printk(KERN_INFO LIRC_DRIVER_NAME ++ ": auto-detected active %s receiver on GPIO pin %d\n", ++ sense ? "low" : "high", gpio_in_pin); ++ } else { ++ printk(KERN_INFO LIRC_DRIVER_NAME ++ ": manually using active %s receiver on GPIO pin %d\n", ++ sense ? "low" : "high", gpio_in_pin); ++ } ++ ++ return 0; ++ ++ exit_gpio_free_in_pin: ++ gpio_free(gpio_in_pin); ++ ++ exit_gpio_free_out_pin: ++ gpio_free(gpio_out_pin); ++ ++ exit_init_port: ++ return ret; ++} ++ ++// called when the character device is opened ++static int set_use_inc(void *data) ++{ ++ int result; ++ unsigned long flags; ++ ++ /* initialize timestamp */ ++ do_gettimeofday(&lasttv); ++ ++ result = request_irq(gpiochip->to_irq(gpiochip, gpio_in_pin), ++ (irq_handler_t) irq_handler, 0, ++ LIRC_DRIVER_NAME, (void*) 0); ++ ++ switch (result) { ++ case -EBUSY: ++ printk(KERN_ERR LIRC_DRIVER_NAME ++ ": IRQ %d is busy\n", ++ gpiochip->to_irq(gpiochip, gpio_in_pin)); ++ return -EBUSY; ++ case -EINVAL: ++ printk(KERN_ERR LIRC_DRIVER_NAME ++ ": Bad irq number or handler\n"); ++ return -EINVAL; ++ default: ++ dprintk("Interrupt %d obtained\n", ++ gpiochip->to_irq(gpiochip, gpio_in_pin)); ++ break; ++ }; ++ ++ /* initialize pulse/space widths */ ++ init_timing_params(duty_cycle, freq); ++ ++ spin_lock_irqsave(&lock, flags); ++ ++ /* GPIO Pin Falling/Rising Edge Detect Enable */ ++ irqchip->irq_set_type(irqdata, ++ IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING); ++ ++ /* unmask the irq */ ++ irqchip->irq_unmask(irqdata); ++ ++ spin_unlock_irqrestore(&lock, flags); ++ ++ return 0; ++} ++ ++static void set_use_dec(void *data) ++{ ++ unsigned long flags; ++ ++ spin_lock_irqsave(&lock, flags); ++ ++ /* GPIO Pin Falling/Rising Edge Detect Disable */ ++ irqchip->irq_set_type(irqdata, 0); ++ irqchip->irq_mask(irqdata); ++ ++ spin_unlock_irqrestore(&lock, flags); ++ ++ free_irq(gpiochip->to_irq(gpiochip, gpio_in_pin), (void *) 0); ++ ++ dprintk(KERN_INFO LIRC_DRIVER_NAME ++ ": freed IRQ %d\n", gpiochip->to_irq(gpiochip, gpio_in_pin)); ++} ++ ++static ssize_t lirc_write(struct file *file, const char *buf, ++ size_t n, loff_t *ppos) ++{ ++ int i, count; ++ unsigned long flags; ++ long delta = 0; ++ int *wbuf; ++ ++ count = n / sizeof(int); ++ if (n % sizeof(int) || count % 2 == 0) ++ return -EINVAL; ++ wbuf = memdup_user(buf, n); ++ if (IS_ERR(wbuf)) ++ return PTR_ERR(wbuf); ++ spin_lock_irqsave(&lock, flags); ++ ++ for (i = 0; i < count; i++) { ++ if (i%2) ++ send_space(wbuf[i] - delta); ++ else ++ delta = send_pulse(wbuf[i]); ++ } ++ gpiochip->set(gpiochip, gpio_out_pin, 0); ++ ++ spin_unlock_irqrestore(&lock, flags); ++ kfree(wbuf); ++ return n; ++} ++ ++static long lirc_ioctl(struct file *filep, unsigned int cmd, unsigned long arg) ++{ ++ int result; ++ __u32 value; ++ ++ switch (cmd) { ++ case LIRC_GET_SEND_MODE: ++ return -ENOIOCTLCMD; ++ break; ++ ++ case LIRC_SET_SEND_MODE: ++ result = get_user(value, (__u32 *) arg); ++ if (result) ++ return result; ++ /* only LIRC_MODE_PULSE supported */ ++ if (value != LIRC_MODE_PULSE) ++ return -ENOSYS; ++ break; ++ ++ case LIRC_GET_LENGTH: ++ return -ENOSYS; ++ break; ++ ++ case LIRC_SET_SEND_DUTY_CYCLE: ++ dprintk("SET_SEND_DUTY_CYCLE\n"); ++ result = get_user(value, (__u32 *) arg); ++ if (result) ++ return result; ++ if (value <= 0 || value > 100) ++ return -EINVAL; ++ return init_timing_params(value, freq); ++ break; ++ ++ case LIRC_SET_SEND_CARRIER: ++ dprintk("SET_SEND_CARRIER\n"); ++ result = get_user(value, (__u32 *) arg); ++ if (result) ++ return result; ++ if (value > 500000 || value < 20000) ++ return -EINVAL; ++ return init_timing_params(duty_cycle, value); ++ break; ++ ++ default: ++ return lirc_dev_fop_ioctl(filep, cmd, arg); ++ } ++ return 0; ++} ++ ++static const struct file_operations lirc_fops = { ++ .owner = THIS_MODULE, ++ .write = lirc_write, ++ .unlocked_ioctl = lirc_ioctl, ++ .read = lirc_dev_fop_read, ++ .poll = lirc_dev_fop_poll, ++ .open = lirc_dev_fop_open, ++ .release = lirc_dev_fop_close, ++ .llseek = no_llseek, ++}; ++ ++static struct lirc_driver driver = { ++ .name = LIRC_DRIVER_NAME, ++ .minor = -1, ++ .code_length = 1, ++ .sample_rate = 0, ++ .data = NULL, ++ .add_to_buf = NULL, ++ .rbuf = &rbuf, ++ .set_use_inc = set_use_inc, ++ .set_use_dec = set_use_dec, ++ .fops = &lirc_fops, ++ .dev = NULL, ++ .owner = THIS_MODULE, ++}; ++ ++static struct platform_driver lirc_rpi_driver = { ++ .driver = { ++ .name = LIRC_DRIVER_NAME, ++ .owner = THIS_MODULE, ++ }, ++}; ++ ++static int __init lirc_rpi_init(void) ++{ ++ int result; ++ ++ /* Init read buffer. */ ++ result = lirc_buffer_init(&rbuf, sizeof(int), RBUF_LEN); ++ if (result < 0) ++ return -ENOMEM; ++ ++ result = platform_driver_register(&lirc_rpi_driver); ++ if (result) { ++ printk(KERN_ERR LIRC_DRIVER_NAME ++ ": lirc register returned %d\n", result); ++ goto exit_buffer_free; ++ } ++ ++ lirc_rpi_dev = platform_device_alloc(LIRC_DRIVER_NAME, 0); ++ if (!lirc_rpi_dev) { ++ result = -ENOMEM; ++ goto exit_driver_unregister; ++ } ++ ++ result = platform_device_add(lirc_rpi_dev); ++ if (result) ++ goto exit_device_put; ++ ++ return 0; ++ ++ exit_device_put: ++ platform_device_put(lirc_rpi_dev); ++ ++ exit_driver_unregister: ++ platform_driver_unregister(&lirc_rpi_driver); ++ ++ exit_buffer_free: ++ lirc_buffer_free(&rbuf); ++ ++ return result; ++} ++ ++static void lirc_rpi_exit(void) ++{ ++ gpio_free(gpio_out_pin); ++ gpio_free(gpio_in_pin); ++ platform_device_unregister(lirc_rpi_dev); ++ platform_driver_unregister(&lirc_rpi_driver); ++ lirc_buffer_free(&rbuf); ++} ++ ++static int __init lirc_rpi_init_module(void) ++{ ++ int result, i; ++ ++ result = lirc_rpi_init(); ++ if (result) ++ return result; ++ ++ /* check if the module received valid gpio pin numbers */ ++ result = 0; ++ if (gpio_in_pin != gpio_out_pin) { ++ for(i = 0; (i < ARRAY_SIZE(valid_gpio_pins)) && (result != 2); i++) { ++ if (gpio_in_pin == valid_gpio_pins[i] || ++ gpio_out_pin == valid_gpio_pins[i]) { ++ result++; ++ } ++ } ++ } ++ ++ if (result != 2) { ++ result = -EINVAL; ++ printk(KERN_ERR LIRC_DRIVER_NAME ++ ": invalid GPIO pin(s) specified!\n"); ++ goto exit_rpi; ++ } ++ ++ driver.features = LIRC_CAN_SET_SEND_DUTY_CYCLE | ++ LIRC_CAN_SET_SEND_CARRIER | ++ LIRC_CAN_SEND_PULSE | ++ LIRC_CAN_REC_MODE2; ++ ++ driver.dev = &lirc_rpi_dev->dev; ++ driver.minor = lirc_register_driver(&driver); ++ ++ if (driver.minor < 0) { ++ printk(KERN_ERR LIRC_DRIVER_NAME ++ ": device registration failed with %d\n", result); ++ result = -EIO; ++ goto exit_rpi; ++ } ++ ++ printk(KERN_INFO LIRC_DRIVER_NAME ": driver registered!\n"); ++ ++ result = init_port(); ++ if (result < 0) ++ goto exit_rpi; ++ ++ return 0; ++ ++ exit_rpi: ++ lirc_rpi_exit(); ++ ++ return result; ++} ++ ++static void __exit lirc_rpi_exit_module(void) ++{ ++ lirc_rpi_exit(); ++ ++ lirc_unregister_driver(driver.minor); ++ printk(KERN_INFO LIRC_DRIVER_NAME ": cleaned up module\n"); ++} ++ ++module_init(lirc_rpi_init_module); ++module_exit(lirc_rpi_exit_module); ++ ++MODULE_DESCRIPTION("Infra-red receiver and blaster driver for Raspberry Pi GPIO."); ++MODULE_AUTHOR("Aron Robert Szabo "); ++MODULE_AUTHOR("Michael Bishop "); ++MODULE_LICENSE("GPL"); ++ ++module_param(gpio_out_pin, int, S_IRUGO); ++MODULE_PARM_DESC(gpio_out_pin, "GPIO output/transmitter pin number of the BCM" ++ " processor. Valid pin numbers are: 0, 1, 4, 8, 7, 9, 10, 11," ++ " 14, 15, 17, 18, 21, 22, 23, 24, 25, default 17"); ++ ++module_param(gpio_in_pin, int, S_IRUGO); ++MODULE_PARM_DESC(gpio_in_pin, "GPIO input pin number of the BCM processor." ++ " Valid pin numbers are: 0, 1, 4, 8, 7, 9, 10, 11, 14, 15," ++ " 17, 18, 21, 22, 23, 24, 25, default 18"); ++ ++module_param(sense, bool, S_IRUGO); ++MODULE_PARM_DESC(sense, "Override autodetection of IR receiver circuit" ++ " (0 = active high, 1 = active low )"); ++ ++module_param(softcarrier, bool, S_IRUGO); ++MODULE_PARM_DESC(softcarrier, "Software carrier (0 = off, 1 = on, default on)"); ++ ++module_param(debug, bool, S_IRUGO | S_IWUSR); ++MODULE_PARM_DESC(debug, "Enable debugging messages"); diff -Nru linux-3.2.46/debian/patches/rpi/rpi_273_036c94eeefd3abf93cc18ff0fdf689fce00df59b.patch linux-3.2.46/debian/patches/rpi/rpi_273_036c94eeefd3abf93cc18ff0fdf689fce00df59b.patch --- linux-3.2.46/debian/patches/rpi/rpi_273_036c94eeefd3abf93cc18ff0fdf689fce00df59b.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_273_036c94eeefd3abf93cc18ff0fdf689fce00df59b.patch 2013-07-26 19:37:24.000000000 +0000 @@ -0,0 +1,61 @@ +commit 036c94eeefd3abf93cc18ff0fdf689fce00df59b +Author: Emeric Vigier +Date: Mon Jul 9 17:44:45 2012 -0400 + + smsc95xx: support ethtool get_regs + + Inspired by implementation in smsc911x.c and smsc9420.c + Tested on ARM/pandaboard running android + + Signed-off-by: Emeric Vigier + Signed-off-by: David S. Miller + +Index: linux-3.2.46/drivers/net/usb/smsc95xx.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/usb/smsc95xx.c 2013-07-26 19:32:54.000000000 +0000 ++++ linux-3.2.46/drivers/net/usb/smsc95xx.c 2013-07-26 19:37:23.000000000 +0000 +@@ -582,6 +582,35 @@ + return smsc95xx_write_eeprom(dev, ee->offset, ee->len, data); + } + ++static int smsc95xx_ethtool_getregslen(struct net_device *netdev) ++{ ++ /* all smsc95xx registers */ ++ return COE_CR - ID_REV + 1; ++} ++ ++static void ++smsc95xx_ethtool_getregs(struct net_device *netdev, struct ethtool_regs *regs, ++ void *buf) ++{ ++ struct usbnet *dev = netdev_priv(netdev); ++ unsigned int i, j, retval; ++ u32 *data = buf; ++ ++ retval = smsc95xx_read_reg(dev, ID_REV, ®s->version); ++ if (retval < 0) { ++ netdev_warn(netdev, "REGS: cannot read ID_REV\n"); ++ return; ++ } ++ ++ for (i = ID_REV, j = 0; i <= COE_CR; i += (sizeof(u32)), j++) { ++ retval = smsc95xx_read_reg(dev, i, &data[j]); ++ if (retval < 0) { ++ netdev_warn(netdev, "REGS: cannot read reg[%x]\n", i); ++ return; ++ } ++ } ++} ++ + static const struct ethtool_ops smsc95xx_ethtool_ops = { + .get_link = usbnet_get_link, + .nway_reset = usbnet_nway_reset, +@@ -593,6 +622,8 @@ + .get_eeprom_len = smsc95xx_ethtool_get_eeprom_len, + .get_eeprom = smsc95xx_ethtool_get_eeprom, + .set_eeprom = smsc95xx_ethtool_set_eeprom, ++ .get_regs_len = smsc95xx_ethtool_getregslen, ++ .get_regs = smsc95xx_ethtool_getregs, + }; + + static int smsc95xx_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd) diff -Nru linux-3.2.46/debian/patches/rpi/rpi_274_ac7c9291f72c6f54a3afb6268c312b106b07d525.patch linux-3.2.46/debian/patches/rpi/rpi_274_ac7c9291f72c6f54a3afb6268c312b106b07d525.patch --- linux-3.2.46/debian/patches/rpi/rpi_274_ac7c9291f72c6f54a3afb6268c312b106b07d525.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_274_ac7c9291f72c6f54a3afb6268c312b106b07d525.patch 2013-07-26 19:37:25.000000000 +0000 @@ -0,0 +1,25 @@ +commit ac7c9291f72c6f54a3afb6268c312b106b07d525 +Author: Dan Carpenter +Date: Tue Jul 10 20:32:51 2012 +0000 + + smsc95xx: signedness bug in get_regs() + + "retval" has to be a signed integer for the error handling to work. + + Signed-off-by: Dan Carpenter + Signed-off-by: David S. Miller + +Index: linux-3.2.46/drivers/net/usb/smsc95xx.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/usb/smsc95xx.c 2013-07-26 19:37:23.000000000 +0000 ++++ linux-3.2.46/drivers/net/usb/smsc95xx.c 2013-07-26 19:37:24.000000000 +0000 +@@ -593,7 +593,8 @@ + void *buf) + { + struct usbnet *dev = netdev_priv(netdev); +- unsigned int i, j, retval; ++ unsigned int i, j; ++ int retval; + u32 *data = buf; + + retval = smsc95xx_read_reg(dev, ID_REV, ®s->version); diff -Nru linux-3.2.46/debian/patches/rpi/rpi_275_00b8a332c633a6ee52994672ea2558d1f8199fa9.patch linux-3.2.46/debian/patches/rpi/rpi_275_00b8a332c633a6ee52994672ea2558d1f8199fa9.patch --- linux-3.2.46/debian/patches/rpi/rpi_275_00b8a332c633a6ee52994672ea2558d1f8199fa9.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_275_00b8a332c633a6ee52994672ea2558d1f8199fa9.patch 2013-07-26 19:37:27.000000000 +0000 @@ -0,0 +1,44 @@ +commit 00b8a332c633a6ee52994672ea2558d1f8199fa9 +Author: Steve Glendinning +Date: Fri Sep 28 00:07:07 2012 +0000 + + smsc95xx: sleep before read for lengthy operations + + During init, the device reset is unexpected to complete immediately, + so sleep before testing the condition rather than after it. + + Signed-off-by: Steve Glendinning + Signed-off-by: David S. Miller + +Index: linux-3.2.46/drivers/net/usb/smsc95xx.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/usb/smsc95xx.c 2013-07-26 19:37:24.000000000 +0000 ++++ linux-3.2.46/drivers/net/usb/smsc95xx.c 2013-07-26 19:37:26.000000000 +0000 +@@ -818,12 +818,12 @@ + + timeout = 0; + do { ++ msleep(10); + ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf); + if (ret < 0) { + netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret); + return ret; + } +- msleep(10); + timeout++; + } while ((read_buf & HW_CFG_LRST_) && (timeout < 100)); + +@@ -841,12 +841,12 @@ + + timeout = 0; + do { ++ msleep(10); + ret = smsc95xx_read_reg(dev, PM_CTRL, &read_buf); + if (ret < 0) { + netdev_warn(dev->net, "Failed to read PM_CTRL: %d\n", ret); + return ret; + } +- msleep(10); + timeout++; + } while ((read_buf & PM_CTL_PHY_RST_) && (timeout < 100)); + diff -Nru linux-3.2.46/debian/patches/rpi/rpi_276_a01b0af50cd95d5254ff3450e59477a707bede22.patch linux-3.2.46/debian/patches/rpi/rpi_276_a01b0af50cd95d5254ff3450e59477a707bede22.patch --- linux-3.2.46/debian/patches/rpi/rpi_276_a01b0af50cd95d5254ff3450e59477a707bede22.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_276_a01b0af50cd95d5254ff3450e59477a707bede22.patch 2013-07-26 19:37:28.000000000 +0000 @@ -0,0 +1,131 @@ +commit a01b0af50cd95d5254ff3450e59477a707bede22 +Author: Steve Glendinning +Date: Fri Sep 28 00:07:08 2012 +0000 + + smsc95xx: remove unnecessary variables + + Removes unnecessary variables as smsc95xx_write_reg takes its + value by parameter. Early versions passed this parameter by + reference. + + Also replace hardcoded interrupt status value with a #define + + Signed-off-by: Steve Glendinning + Signed-off-by: David S. Miller + +Index: linux-3.2.46/drivers/net/usb/smsc95xx.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/usb/smsc95xx.c 2013-07-26 19:37:26.000000000 +0000 ++++ linux-3.2.46/drivers/net/usb/smsc95xx.c 2013-07-26 19:37:27.000000000 +0000 +@@ -465,12 +465,10 @@ + struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET }; + unsigned long flags; + u16 lcladv, rmtadv; +- u32 intdata; + + /* clear interrupt status */ + smsc95xx_mdio_read(dev->net, mii->phy_id, PHY_INT_SRC); +- intdata = 0xFFFFFFFF; +- smsc95xx_write_reg(dev, INT_STS, intdata); ++ smsc95xx_write_reg(dev, INT_STS, INT_STS_CLEAR_ALL_); + + mii_check_media(mii, 1, 1); + mii_ethtool_gset(&dev->mii, &ecmd); +@@ -732,7 +730,6 @@ + { + struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]); + unsigned long flags; +- u32 reg_val; + + /* Enable Tx at MAC */ + spin_lock_irqsave(&pdata->mac_cr_lock, flags); +@@ -742,8 +739,7 @@ + smsc95xx_write_reg(dev, MAC_CR, pdata->mac_cr); + + /* Enable Tx at SCSRs */ +- reg_val = TX_CFG_ON_; +- smsc95xx_write_reg(dev, TX_CFG, reg_val); ++ smsc95xx_write_reg(dev, TX_CFG, TX_CFG_ON_); + } + + /* Starts the Receive path */ +@@ -808,8 +804,7 @@ + + netif_dbg(dev, ifup, dev->net, "entering smsc95xx_reset\n"); + +- write_buf = HW_CFG_LRST_; +- ret = smsc95xx_write_reg(dev, HW_CFG, write_buf); ++ ret = smsc95xx_write_reg(dev, HW_CFG, HW_CFG_LRST_); + if (ret < 0) { + netdev_warn(dev->net, "Failed to write HW_CFG_LRST_ bit in HW_CFG register, ret = %d\n", + ret); +@@ -832,8 +827,7 @@ + return ret; + } + +- write_buf = PM_CTL_PHY_RST_; +- ret = smsc95xx_write_reg(dev, PM_CTRL, write_buf); ++ ret = smsc95xx_write_reg(dev, PM_CTRL, PM_CTL_PHY_RST_); + if (ret < 0) { + netdev_warn(dev->net, "Failed to write PM_CTRL: %d\n", ret); + return ret; +@@ -918,8 +912,7 @@ + "Read Value from BURST_CAP after writing: 0x%08x\n", + read_buf); + +- read_buf = DEFAULT_BULK_IN_DELAY; +- ret = smsc95xx_write_reg(dev, BULK_IN_DLY, read_buf); ++ ret = smsc95xx_write_reg(dev, BULK_IN_DLY, DEFAULT_BULK_IN_DELAY); + if (ret < 0) { + netdev_warn(dev->net, "ret = %d\n", ret); + return ret; +@@ -965,8 +958,7 @@ + netif_dbg(dev, ifup, dev->net, + "Read Value from HW_CFG after writing: 0x%08x\n", read_buf); + +- write_buf = 0xFFFFFFFF; +- ret = smsc95xx_write_reg(dev, INT_STS, write_buf); ++ ret = smsc95xx_write_reg(dev, INT_STS, INT_STS_CLEAR_ALL_); + if (ret < 0) { + netdev_warn(dev->net, "Failed to write INT_STS register, ret=%d\n", + ret); +@@ -991,15 +983,13 @@ + } + + /* Init Tx */ +- write_buf = 0; +- ret = smsc95xx_write_reg(dev, FLOW, write_buf); ++ ret = smsc95xx_write_reg(dev, FLOW, 0); + if (ret < 0) { + netdev_warn(dev->net, "Failed to write FLOW: %d\n", ret); + return ret; + } + +- read_buf = AFC_CFG_DEFAULT; +- ret = smsc95xx_write_reg(dev, AFC_CFG, read_buf); ++ ret = smsc95xx_write_reg(dev, AFC_CFG, AFC_CFG_DEFAULT); + if (ret < 0) { + netdev_warn(dev->net, "Failed to write AFC_CFG: %d\n", ret); + return ret; +@@ -1014,8 +1004,7 @@ + + /* Init Rx */ + /* Set Vlan */ +- write_buf = (u32)ETH_P_8021Q; +- ret = smsc95xx_write_reg(dev, VLAN1, write_buf); ++ ret = smsc95xx_write_reg(dev, VLAN1, (u32)ETH_P_8021Q); + if (ret < 0) { + netdev_warn(dev->net, "Failed to write VAN1: %d\n", ret); + return ret; +Index: linux-3.2.46/drivers/net/usb/smsc95xx.h +=================================================================== +--- linux-3.2.46.orig/drivers/net/usb/smsc95xx.h 2013-05-30 13:35:16.000000000 +0000 ++++ linux-3.2.46/drivers/net/usb/smsc95xx.h 2013-07-26 19:37:27.000000000 +0000 +@@ -63,6 +63,7 @@ + #define INT_STS_TDFO_ (0x00001000) + #define INT_STS_RXDF_ (0x00000800) + #define INT_STS_GPIOS_ (0x000007FF) ++#define INT_STS_CLEAR_ALL_ (0xFFFFFFFF) + + #define RX_CFG (0x0C) + #define RX_FIFO_FLUSH_ (0x00000001) diff -Nru linux-3.2.46/debian/patches/rpi/rpi_277_15c02e28bb98b7b40e898ec0d72bc86b2e263498.patch linux-3.2.46/debian/patches/rpi/rpi_277_15c02e28bb98b7b40e898ec0d72bc86b2e263498.patch --- linux-3.2.46/debian/patches/rpi/rpi_277_15c02e28bb98b7b40e898ec0d72bc86b2e263498.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_277_15c02e28bb98b7b40e898ec0d72bc86b2e263498.patch 2013-07-26 19:37:29.000000000 +0000 @@ -0,0 +1,701 @@ +commit 15c02e28bb98b7b40e898ec0d72bc86b2e263498 +Author: Steve Glendinning +Date: Fri Sep 28 00:07:09 2012 +0000 + + smsc95xx: check return code from control messages + + This patch adds additional checks of the values returned by + smsc95xx_(read|write)_reg, and wraps their common patterns + in macros. + + Signed-off-by: Steve Glendinning + Signed-off-by: David S. Miller + +Index: linux-3.2.46/drivers/net/usb/smsc95xx.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/usb/smsc95xx.c 2013-07-26 19:37:27.000000000 +0000 ++++ linux-3.2.46/drivers/net/usb/smsc95xx.c 2013-07-26 19:37:28.000000000 +0000 +@@ -48,6 +48,15 @@ + #define SMSC95XX_TX_OVERHEAD_CSUM (12) + #define MAC_ADDR_LEN (6) + ++#define check_warn(ret, fmt, args...) \ ++ ({ if (ret < 0) netdev_warn(dev->net, fmt, ##args); }) ++ ++#define check_warn_return(ret, fmt, args...) \ ++ ({ if (ret < 0) { netdev_warn(dev->net, fmt, ##args); return ret; } }) ++ ++#define check_warn_goto_done(ret, fmt, args...) \ ++ ({ if (ret < 0) { netdev_warn(dev->net, fmt, ##args); goto done; } }) ++ + struct smsc95xx_priv { + u32 mac_cr; + u32 hash_hi; +@@ -68,7 +77,8 @@ + module_param(macaddr, charp, 0); + MODULE_PARM_DESC(macaddr, "MAC address"); + +-static int smsc95xx_read_reg(struct usbnet *dev, u32 index, u32 *data) ++static int __must_check smsc95xx_read_reg(struct usbnet *dev, u32 index, ++ u32 *data) + { + u32 *buf = kmalloc(4, GFP_KERNEL); + int ret; +@@ -93,7 +103,8 @@ + return ret; + } + +-static int smsc95xx_write_reg(struct usbnet *dev, u32 index, u32 data) ++static int __must_check smsc95xx_write_reg(struct usbnet *dev, u32 index, ++ u32 data) + { + u32 *buf = kmalloc(4, GFP_KERNEL); + int ret; +@@ -121,13 +132,15 @@ + + /* Loop until the read is completed with timeout + * called with phy_mutex held */ +-static int smsc95xx_phy_wait_not_busy(struct usbnet *dev) ++static int __must_check smsc95xx_phy_wait_not_busy(struct usbnet *dev) + { + unsigned long start_time = jiffies; + u32 val; ++ int ret; + + do { +- smsc95xx_read_reg(dev, MII_ADDR, &val); ++ ret = smsc95xx_read_reg(dev, MII_ADDR, &val); ++ check_warn_return(ret, "Error reading MII_ACCESS"); + if (!(val & MII_BUSY_)) + return 0; + } while (!time_after(jiffies, start_time + HZ)); +@@ -139,33 +152,32 @@ + { + struct usbnet *dev = netdev_priv(netdev); + u32 val, addr; ++ int ret; + + mutex_lock(&dev->phy_mutex); + + /* confirm MII not busy */ +- if (smsc95xx_phy_wait_not_busy(dev)) { +- netdev_warn(dev->net, "MII is busy in smsc95xx_mdio_read\n"); +- mutex_unlock(&dev->phy_mutex); +- return -EIO; +- } ++ ret = smsc95xx_phy_wait_not_busy(dev); ++ check_warn_goto_done(ret, "MII is busy in smsc95xx_mdio_read"); + + /* set the address, index & direction (read from PHY) */ + phy_id &= dev->mii.phy_id_mask; + idx &= dev->mii.reg_num_mask; + addr = (phy_id << 11) | (idx << 6) | MII_READ_; +- smsc95xx_write_reg(dev, MII_ADDR, addr); ++ ret = smsc95xx_write_reg(dev, MII_ADDR, addr); ++ check_warn_goto_done(ret, "Error writing MII_ADDR"); + +- if (smsc95xx_phy_wait_not_busy(dev)) { +- netdev_warn(dev->net, "Timed out reading MII reg %02X\n", idx); +- mutex_unlock(&dev->phy_mutex); +- return -EIO; +- } ++ ret = smsc95xx_phy_wait_not_busy(dev); ++ check_warn_goto_done(ret, "Timed out reading MII reg %02X", idx); + +- smsc95xx_read_reg(dev, MII_DATA, &val); ++ ret = smsc95xx_read_reg(dev, MII_DATA, &val); ++ check_warn_goto_done(ret, "Error reading MII_DATA"); + +- mutex_unlock(&dev->phy_mutex); ++ ret = (u16)(val & 0xFFFF); + +- return (u16)(val & 0xFFFF); ++done: ++ mutex_unlock(&dev->phy_mutex); ++ return ret; + } + + static void smsc95xx_mdio_write(struct net_device *netdev, int phy_id, int idx, +@@ -173,38 +185,41 @@ + { + struct usbnet *dev = netdev_priv(netdev); + u32 val, addr; ++ int ret; + + mutex_lock(&dev->phy_mutex); + + /* confirm MII not busy */ +- if (smsc95xx_phy_wait_not_busy(dev)) { +- netdev_warn(dev->net, "MII is busy in smsc95xx_mdio_write\n"); +- mutex_unlock(&dev->phy_mutex); +- return; +- } ++ ret = smsc95xx_phy_wait_not_busy(dev); ++ check_warn_goto_done(ret, "MII is busy in smsc95xx_mdio_write"); + + val = regval; +- smsc95xx_write_reg(dev, MII_DATA, val); ++ ret = smsc95xx_write_reg(dev, MII_DATA, val); ++ check_warn_goto_done(ret, "Error writing MII_DATA"); + + /* set the address, index & direction (write to PHY) */ + phy_id &= dev->mii.phy_id_mask; + idx &= dev->mii.reg_num_mask; + addr = (phy_id << 11) | (idx << 6) | MII_WRITE_; +- smsc95xx_write_reg(dev, MII_ADDR, addr); ++ ret = smsc95xx_write_reg(dev, MII_ADDR, addr); ++ check_warn_goto_done(ret, "Error writing MII_ADDR"); + +- if (smsc95xx_phy_wait_not_busy(dev)) +- netdev_warn(dev->net, "Timed out writing MII reg %02X\n", idx); ++ ret = smsc95xx_phy_wait_not_busy(dev); ++ check_warn_goto_done(ret, "Timed out writing MII reg %02X", idx); + ++done: + mutex_unlock(&dev->phy_mutex); + } + +-static int smsc95xx_wait_eeprom(struct usbnet *dev) ++static int __must_check smsc95xx_wait_eeprom(struct usbnet *dev) + { + unsigned long start_time = jiffies; + u32 val; ++ int ret; + + do { +- smsc95xx_read_reg(dev, E2P_CMD, &val); ++ ret = smsc95xx_read_reg(dev, E2P_CMD, &val); ++ check_warn_return(ret, "Error reading E2P_CMD"); + if (!(val & E2P_CMD_BUSY_) || (val & E2P_CMD_TIMEOUT_)) + break; + udelay(40); +@@ -218,13 +233,15 @@ + return 0; + } + +-static int smsc95xx_eeprom_confirm_not_busy(struct usbnet *dev) ++static int __must_check smsc95xx_eeprom_confirm_not_busy(struct usbnet *dev) + { + unsigned long start_time = jiffies; + u32 val; ++ int ret; + + do { +- smsc95xx_read_reg(dev, E2P_CMD, &val); ++ ret = smsc95xx_read_reg(dev, E2P_CMD, &val); ++ check_warn_return(ret, "Error reading E2P_CMD"); + + if (!(val & E2P_CMD_BUSY_)) + return 0; +@@ -251,13 +268,15 @@ + + for (i = 0; i < length; i++) { + val = E2P_CMD_BUSY_ | E2P_CMD_READ_ | (offset & E2P_CMD_ADDR_); +- smsc95xx_write_reg(dev, E2P_CMD, val); ++ ret = smsc95xx_write_reg(dev, E2P_CMD, val); ++ check_warn_return(ret, "Error writing E2P_CMD"); + + ret = smsc95xx_wait_eeprom(dev); + if (ret < 0) + return ret; + +- smsc95xx_read_reg(dev, E2P_DATA, &val); ++ ret = smsc95xx_read_reg(dev, E2P_DATA, &val); ++ check_warn_return(ret, "Error reading E2P_DATA"); + + data[i] = val & 0xFF; + offset++; +@@ -281,7 +300,8 @@ + + /* Issue write/erase enable command */ + val = E2P_CMD_BUSY_ | E2P_CMD_EWEN_; +- smsc95xx_write_reg(dev, E2P_CMD, val); ++ ret = smsc95xx_write_reg(dev, E2P_CMD, val); ++ check_warn_return(ret, "Error writing E2P_DATA"); + + ret = smsc95xx_wait_eeprom(dev); + if (ret < 0) +@@ -291,11 +311,13 @@ + + /* Fill data register */ + val = data[i]; +- smsc95xx_write_reg(dev, E2P_DATA, val); ++ ret = smsc95xx_write_reg(dev, E2P_DATA, val); ++ check_warn_return(ret, "Error writing E2P_DATA"); + + /* Send "write" command */ + val = E2P_CMD_BUSY_ | E2P_CMD_WRITE_ | (offset & E2P_CMD_ADDR_); +- smsc95xx_write_reg(dev, E2P_CMD, val); ++ ret = smsc95xx_write_reg(dev, E2P_CMD, val); ++ check_warn_return(ret, "Error writing E2P_CMD"); + + ret = smsc95xx_wait_eeprom(dev); + if (ret < 0) +@@ -313,14 +335,14 @@ + struct usbnet *dev = usb_context->dev; + int status = urb->status; + +- if (status < 0) +- netdev_warn(dev->net, "async callback failed with %d\n", status); ++ check_warn(status, "async callback failed with %d\n", status); + + kfree(usb_context); + usb_free_urb(urb); + } + +-static int smsc95xx_write_reg_async(struct usbnet *dev, u16 index, u32 *data) ++static int __must_check smsc95xx_write_reg_async(struct usbnet *dev, u16 index, ++ u32 *data) + { + struct usb_context *usb_context; + int status; +@@ -376,6 +398,7 @@ + struct usbnet *dev = netdev_priv(netdev); + struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]); + unsigned long flags; ++ int ret; + + pdata->hash_hi = 0; + pdata->hash_lo = 0; +@@ -416,21 +439,23 @@ + spin_unlock_irqrestore(&pdata->mac_cr_lock, flags); + + /* Initiate async writes, as we can't wait for completion here */ +- smsc95xx_write_reg_async(dev, HASHH, &pdata->hash_hi); +- smsc95xx_write_reg_async(dev, HASHL, &pdata->hash_lo); +- smsc95xx_write_reg_async(dev, MAC_CR, &pdata->mac_cr); ++ ret = smsc95xx_write_reg_async(dev, HASHH, &pdata->hash_hi); ++ check_warn(ret, "failed to initiate async write to HASHH"); ++ ++ ret = smsc95xx_write_reg_async(dev, HASHL, &pdata->hash_lo); ++ check_warn(ret, "failed to initiate async write to HASHL"); ++ ++ ret = smsc95xx_write_reg_async(dev, MAC_CR, &pdata->mac_cr); ++ check_warn(ret, "failed to initiate async write to MAC_CR"); + } + +-static void smsc95xx_phy_update_flowcontrol(struct usbnet *dev, u8 duplex, +- u16 lcladv, u16 rmtadv) ++static int smsc95xx_phy_update_flowcontrol(struct usbnet *dev, u8 duplex, ++ u16 lcladv, u16 rmtadv) + { + u32 flow, afc_cfg = 0; + + int ret = smsc95xx_read_reg(dev, AFC_CFG, &afc_cfg); +- if (ret < 0) { +- netdev_warn(dev->net, "error reading AFC_CFG\n"); +- return; +- } ++ check_warn_return(ret, "Error reading AFC_CFG"); + + if (duplex == DUPLEX_FULL) { + u8 cap = mii_resolve_flowctrl_fdx(lcladv, rmtadv); +@@ -454,8 +479,13 @@ + afc_cfg |= 0xF; + } + +- smsc95xx_write_reg(dev, FLOW, flow); +- smsc95xx_write_reg(dev, AFC_CFG, afc_cfg); ++ ret = smsc95xx_write_reg(dev, FLOW, flow); ++ check_warn_return(ret, "Error writing FLOW"); ++ ++ ret = smsc95xx_write_reg(dev, AFC_CFG, afc_cfg); ++ check_warn_return(ret, "Error writing AFC_CFG"); ++ ++ return 0; + } + + static int smsc95xx_link_reset(struct usbnet *dev) +@@ -465,10 +495,14 @@ + struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET }; + unsigned long flags; + u16 lcladv, rmtadv; ++ int ret; + + /* clear interrupt status */ +- smsc95xx_mdio_read(dev->net, mii->phy_id, PHY_INT_SRC); +- smsc95xx_write_reg(dev, INT_STS, INT_STS_CLEAR_ALL_); ++ ret = smsc95xx_mdio_read(dev->net, mii->phy_id, PHY_INT_SRC); ++ check_warn_return(ret, "Error reading PHY_INT_SRC"); ++ ++ ret = smsc95xx_write_reg(dev, INT_STS, INT_STS_CLEAR_ALL_); ++ check_warn_return(ret, "Error writing INT_STS"); + + mii_check_media(mii, 1, 1); + mii_ethtool_gset(&dev->mii, &ecmd); +@@ -489,9 +523,11 @@ + } + spin_unlock_irqrestore(&pdata->mac_cr_lock, flags); + +- smsc95xx_write_reg(dev, MAC_CR, pdata->mac_cr); ++ ret = smsc95xx_write_reg(dev, MAC_CR, pdata->mac_cr); ++ check_warn_return(ret, "Error writing MAC_CR"); + +- smsc95xx_phy_update_flowcontrol(dev, ecmd.duplex, lcladv, rmtadv); ++ ret = smsc95xx_phy_update_flowcontrol(dev, ecmd.duplex, lcladv, rmtadv); ++ check_warn_return(ret, "Error updating PHY flow control"); + + return 0; + } +@@ -526,10 +562,7 @@ + int ret; + + ret = smsc95xx_read_reg(dev, COE_CR, &read_buf); +- if (ret < 0) { +- netdev_warn(dev->net, "Failed to read COE_CR: %d\n", ret); +- return ret; +- } ++ check_warn_return(ret, "Failed to read COE_CR: %d\n", ret); + + if (features & NETIF_F_HW_CSUM) + read_buf |= Tx_COE_EN_; +@@ -542,10 +575,7 @@ + read_buf &= ~Rx_COE_EN_; + + ret = smsc95xx_write_reg(dev, COE_CR, read_buf); +- if (ret < 0) { +- netdev_warn(dev->net, "Failed to write COE_CR: %d\n", ret); +- return ret; +- } ++ check_warn_return(ret, "Failed to write COE_CR: %d\n", ret); + + netif_dbg(dev, hw, dev->net, "COE_CR = 0x%08x\n", read_buf); + return 0; +@@ -711,53 +741,56 @@ + int ret; + + ret = smsc95xx_write_reg(dev, ADDRL, addr_lo); +- if (ret < 0) { +- netdev_warn(dev->net, "Failed to write ADDRL: %d\n", ret); +- return ret; +- } ++ check_warn_return(ret, "Failed to write ADDRL: %d\n", ret); + + ret = smsc95xx_write_reg(dev, ADDRH, addr_hi); +- if (ret < 0) { +- netdev_warn(dev->net, "Failed to write ADDRH: %d\n", ret); +- return ret; +- } ++ check_warn_return(ret, "Failed to write ADDRH: %d\n", ret); + + return 0; + } + + /* starts the TX path */ +-static void smsc95xx_start_tx_path(struct usbnet *dev) ++static int smsc95xx_start_tx_path(struct usbnet *dev) + { + struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]); + unsigned long flags; ++ int ret; + + /* Enable Tx at MAC */ + spin_lock_irqsave(&pdata->mac_cr_lock, flags); + pdata->mac_cr |= MAC_CR_TXEN_; + spin_unlock_irqrestore(&pdata->mac_cr_lock, flags); + +- smsc95xx_write_reg(dev, MAC_CR, pdata->mac_cr); ++ ret = smsc95xx_write_reg(dev, MAC_CR, pdata->mac_cr); ++ check_warn_return(ret, "Failed to write MAC_CR: %d\n", ret); + + /* Enable Tx at SCSRs */ +- smsc95xx_write_reg(dev, TX_CFG, TX_CFG_ON_); ++ ret = smsc95xx_write_reg(dev, TX_CFG, TX_CFG_ON_); ++ check_warn_return(ret, "Failed to write TX_CFG: %d\n", ret); ++ ++ return 0; + } + + /* Starts the Receive path */ +-static void smsc95xx_start_rx_path(struct usbnet *dev) ++static int smsc95xx_start_rx_path(struct usbnet *dev) + { + struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]); + unsigned long flags; ++ int ret; + + spin_lock_irqsave(&pdata->mac_cr_lock, flags); + pdata->mac_cr |= MAC_CR_RXEN_; + spin_unlock_irqrestore(&pdata->mac_cr_lock, flags); + +- smsc95xx_write_reg(dev, MAC_CR, pdata->mac_cr); ++ ret = smsc95xx_write_reg(dev, MAC_CR, pdata->mac_cr); ++ check_warn_return(ret, "Failed to write MAC_CR: %d\n", ret); ++ ++ return 0; + } + + static int smsc95xx_phy_initialize(struct usbnet *dev) + { +- int bmcr, timeout = 0; ++ int bmcr, ret, timeout = 0; + + /* Initialize MII structure */ + dev->mii.dev = dev->net; +@@ -786,7 +819,8 @@ + ADVERTISE_PAUSE_ASYM); + + /* read to clear */ +- smsc95xx_mdio_read(dev->net, dev->mii.phy_id, PHY_INT_SRC); ++ ret = smsc95xx_mdio_read(dev->net, dev->mii.phy_id, PHY_INT_SRC); ++ check_warn_return(ret, "Failed to read PHY_INT_SRC during init"); + + smsc95xx_mdio_write(dev->net, dev->mii.phy_id, PHY_INT_MASK, + PHY_INT_MASK_DEFAULT_); +@@ -805,20 +839,13 @@ + netif_dbg(dev, ifup, dev->net, "entering smsc95xx_reset\n"); + + ret = smsc95xx_write_reg(dev, HW_CFG, HW_CFG_LRST_); +- if (ret < 0) { +- netdev_warn(dev->net, "Failed to write HW_CFG_LRST_ bit in HW_CFG register, ret = %d\n", +- ret); +- return ret; +- } ++ check_warn_return(ret, "Failed to write HW_CFG_LRST_ bit in HW_CFG\n"); + + timeout = 0; + do { + msleep(10); + ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf); +- if (ret < 0) { +- netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret); +- return ret; +- } ++ check_warn_return(ret, "Failed to read HW_CFG: %d\n", ret); + timeout++; + } while ((read_buf & HW_CFG_LRST_) && (timeout < 100)); + +@@ -828,19 +855,13 @@ + } + + ret = smsc95xx_write_reg(dev, PM_CTRL, PM_CTL_PHY_RST_); +- if (ret < 0) { +- netdev_warn(dev->net, "Failed to write PM_CTRL: %d\n", ret); +- return ret; +- } ++ check_warn_return(ret, "Failed to write PM_CTRL: %d\n", ret); + + timeout = 0; + do { + msleep(10); + ret = smsc95xx_read_reg(dev, PM_CTRL, &read_buf); +- if (ret < 0) { +- netdev_warn(dev->net, "Failed to read PM_CTRL: %d\n", ret); +- return ret; +- } ++ check_warn_return(ret, "Failed to read PM_CTRL: %d\n", ret); + timeout++; + } while ((read_buf & PM_CTL_PHY_RST_) && (timeout < 100)); + +@@ -857,10 +878,7 @@ + "MAC Address: %pM\n", dev->net->dev_addr); + + ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf); +- if (ret < 0) { +- netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret); +- return ret; +- } ++ check_warn_return(ret, "Failed to read HW_CFG: %d\n", ret); + + netif_dbg(dev, ifup, dev->net, + "Read Value from HW_CFG : 0x%08x\n", read_buf); +@@ -868,17 +886,10 @@ + read_buf |= HW_CFG_BIR_; + + ret = smsc95xx_write_reg(dev, HW_CFG, read_buf); +- if (ret < 0) { +- netdev_warn(dev->net, "Failed to write HW_CFG_BIR_ bit in HW_CFG register, ret = %d\n", +- ret); +- return ret; +- } ++ check_warn_return(ret, "Failed to write HW_CFG_BIR_ bit in HW_CFG\n"); + + ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf); +- if (ret < 0) { +- netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret); +- return ret; +- } ++ check_warn_return(ret, "Failed to read HW_CFG: %d\n", ret); + netif_dbg(dev, ifup, dev->net, + "Read Value from HW_CFG after writing HW_CFG_BIR_: 0x%08x\n", + read_buf); +@@ -898,40 +909,28 @@ + "rx_urb_size=%ld\n", (ulong)dev->rx_urb_size); + + ret = smsc95xx_write_reg(dev, BURST_CAP, burst_cap); +- if (ret < 0) { +- netdev_warn(dev->net, "Failed to write BURST_CAP: %d\n", ret); +- return ret; +- } ++ check_warn_return(ret, "Failed to write BURST_CAP: %d\n", ret); + + ret = smsc95xx_read_reg(dev, BURST_CAP, &read_buf); +- if (ret < 0) { +- netdev_warn(dev->net, "Failed to read BURST_CAP: %d\n", ret); +- return ret; +- } ++ check_warn_return(ret, "Failed to read BURST_CAP: %d\n", ret); ++ + netif_dbg(dev, ifup, dev->net, + "Read Value from BURST_CAP after writing: 0x%08x\n", + read_buf); + + ret = smsc95xx_write_reg(dev, BULK_IN_DLY, DEFAULT_BULK_IN_DELAY); +- if (ret < 0) { +- netdev_warn(dev->net, "ret = %d\n", ret); +- return ret; +- } ++ check_warn_return(ret, "Failed to write BULK_IN_DLY: %d\n", ret); + + ret = smsc95xx_read_reg(dev, BULK_IN_DLY, &read_buf); +- if (ret < 0) { +- netdev_warn(dev->net, "Failed to read BULK_IN_DLY: %d\n", ret); +- return ret; +- } ++ check_warn_return(ret, "Failed to read BULK_IN_DLY: %d\n", ret); ++ + netif_dbg(dev, ifup, dev->net, + "Read Value from BULK_IN_DLY after writing: 0x%08x\n", + read_buf); + + ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf); +- if (ret < 0) { +- netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret); +- return ret; +- } ++ check_warn_return(ret, "Failed to read HW_CFG: %d\n", ret); ++ + netif_dbg(dev, ifup, dev->net, + "Read Value from HW_CFG: 0x%08x\n", read_buf); + +@@ -944,97 +943,66 @@ + read_buf |= NET_IP_ALIGN << 9; + + ret = smsc95xx_write_reg(dev, HW_CFG, read_buf); +- if (ret < 0) { +- netdev_warn(dev->net, "Failed to write HW_CFG register, ret=%d\n", +- ret); +- return ret; +- } ++ check_warn_return(ret, "Failed to write HW_CFG: %d\n", ret); + + ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf); +- if (ret < 0) { +- netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret); +- return ret; +- } ++ check_warn_return(ret, "Failed to read HW_CFG: %d\n", ret); ++ + netif_dbg(dev, ifup, dev->net, + "Read Value from HW_CFG after writing: 0x%08x\n", read_buf); + + ret = smsc95xx_write_reg(dev, INT_STS, INT_STS_CLEAR_ALL_); +- if (ret < 0) { +- netdev_warn(dev->net, "Failed to write INT_STS register, ret=%d\n", +- ret); +- return ret; +- } ++ check_warn_return(ret, "Failed to write INT_STS: %d\n", ret); + + ret = smsc95xx_read_reg(dev, ID_REV, &read_buf); +- if (ret < 0) { +- netdev_warn(dev->net, "Failed to read ID_REV: %d\n", ret); +- return ret; +- } ++ check_warn_return(ret, "Failed to read ID_REV: %d\n", ret); + netif_dbg(dev, ifup, dev->net, "ID_REV = 0x%08x\n", read_buf); + + /* Configure GPIO pins as LED outputs */ + write_buf = LED_GPIO_CFG_SPD_LED | LED_GPIO_CFG_LNK_LED | + LED_GPIO_CFG_FDX_LED; + ret = smsc95xx_write_reg(dev, LED_GPIO_CFG, write_buf); +- if (ret < 0) { +- netdev_warn(dev->net, "Failed to write LED_GPIO_CFG register, ret=%d\n", +- ret); +- return ret; +- } ++ check_warn_return(ret, "Failed to write LED_GPIO_CFG: %d\n", ret); + + /* Init Tx */ + ret = smsc95xx_write_reg(dev, FLOW, 0); +- if (ret < 0) { +- netdev_warn(dev->net, "Failed to write FLOW: %d\n", ret); +- return ret; +- } ++ check_warn_return(ret, "Failed to write FLOW: %d\n", ret); + + ret = smsc95xx_write_reg(dev, AFC_CFG, AFC_CFG_DEFAULT); +- if (ret < 0) { +- netdev_warn(dev->net, "Failed to write AFC_CFG: %d\n", ret); +- return ret; +- } ++ check_warn_return(ret, "Failed to write AFC_CFG: %d\n", ret); + + /* Don't need mac_cr_lock during initialisation */ + ret = smsc95xx_read_reg(dev, MAC_CR, &pdata->mac_cr); +- if (ret < 0) { +- netdev_warn(dev->net, "Failed to read MAC_CR: %d\n", ret); +- return ret; +- } ++ check_warn_return(ret, "Failed to read MAC_CR: %d\n", ret); + + /* Init Rx */ + /* Set Vlan */ + ret = smsc95xx_write_reg(dev, VLAN1, (u32)ETH_P_8021Q); +- if (ret < 0) { +- netdev_warn(dev->net, "Failed to write VAN1: %d\n", ret); +- return ret; +- } ++ check_warn_return(ret, "Failed to write VLAN1: %d\n", ret); + + /* Enable or disable checksum offload engines */ +- smsc95xx_set_features(dev->net, dev->net->features); ++ ret = smsc95xx_set_features(dev->net, dev->net->features); ++ check_warn_return(ret, "Failed to set checksum offload features"); + + smsc95xx_set_multicast(dev->net); + +- if (smsc95xx_phy_initialize(dev) < 0) +- return -EIO; ++ ret = smsc95xx_phy_initialize(dev); ++ check_warn_return(ret, "Failed to init PHY"); + + ret = smsc95xx_read_reg(dev, INT_EP_CTL, &read_buf); +- if (ret < 0) { +- netdev_warn(dev->net, "Failed to read INT_EP_CTL: %d\n", ret); +- return ret; +- } ++ check_warn_return(ret, "Failed to read INT_EP_CTL: %d\n", ret); + + /* enable PHY interrupts */ + read_buf |= INT_EP_CTL_PHY_INT_; + + ret = smsc95xx_write_reg(dev, INT_EP_CTL, read_buf); +- if (ret < 0) { +- netdev_warn(dev->net, "Failed to write INT_EP_CTL: %d\n", ret); +- return ret; +- } ++ check_warn_return(ret, "Failed to write INT_EP_CTL: %d\n", ret); + +- smsc95xx_start_tx_path(dev); +- smsc95xx_start_rx_path(dev); ++ ret = smsc95xx_start_tx_path(dev); ++ check_warn_return(ret, "Failed to start TX path"); ++ ++ ret = smsc95xx_start_rx_path(dev); ++ check_warn_return(ret, "Failed to start RX path"); + + netif_dbg(dev, ifup, dev->net, "smsc95xx_reset, return 0\n"); + return 0; +@@ -1061,10 +1029,7 @@ + printk(KERN_INFO SMSC_CHIPNAME " v" SMSC_DRIVER_VERSION "\n"); + + ret = usbnet_get_endpoints(dev, intf); +- if (ret < 0) { +- netdev_warn(dev->net, "usbnet_get_endpoints failed: %d\n", ret); +- return ret; +- } ++ check_warn_return(ret, "usbnet_get_endpoints failed: %d\n", ret); + + dev->data[0] = (unsigned long)kzalloc(sizeof(struct smsc95xx_priv), + GFP_KERNEL); diff -Nru linux-3.2.46/debian/patches/rpi/rpi_278_a6555c21fded3da6784456c10d4971a3b68aa21f.patch linux-3.2.46/debian/patches/rpi/rpi_278_a6555c21fded3da6784456c10d4971a3b68aa21f.patch --- linux-3.2.46/debian/patches/rpi/rpi_278_a6555c21fded3da6784456c10d4971a3b68aa21f.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_278_a6555c21fded3da6784456c10d4971a3b68aa21f.patch 2013-07-26 19:37:31.000000000 +0000 @@ -0,0 +1,24 @@ +commit a6555c21fded3da6784456c10d4971a3b68aa21f +Author: Steve Glendinning +Date: Fri Sep 28 00:07:10 2012 +0000 + + smsc95xx: fix resume when usb device is reset + + This patch fixes an issue on some systems, where after suspend the + link is re-established but the ethernet interface does not resume. + + Signed-off-by: Steve Glendinning + Signed-off-by: David S. Miller + +Index: linux-3.2.46/drivers/net/usb/smsc95xx.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/usb/smsc95xx.c 2013-07-26 19:37:28.000000000 +0000 ++++ linux-3.2.46/drivers/net/usb/smsc95xx.c 2013-07-26 19:37:30.000000000 +0000 +@@ -1337,6 +1337,7 @@ + .probe = usbnet_probe, + .suspend = usbnet_suspend, + .resume = usbnet_resume, ++ .reset_resume = usbnet_resume, + .disconnect = usbnet_disconnect, + }; + diff -Nru linux-3.2.46/debian/patches/rpi/rpi_279_efdb0b084f8188babe4c8b1f169c4acbd4f618fa.patch linux-3.2.46/debian/patches/rpi/rpi_279_efdb0b084f8188babe4c8b1f169c4acbd4f618fa.patch --- linux-3.2.46/debian/patches/rpi/rpi_279_efdb0b084f8188babe4c8b1f169c4acbd4f618fa.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_279_efdb0b084f8188babe4c8b1f169c4acbd4f618fa.patch 2013-07-26 19:37:32.000000000 +0000 @@ -0,0 +1,84 @@ +commit efdb0b084f8188babe4c8b1f169c4acbd4f618fa +Author: Steve Glendinning +Date: Fri Sep 28 00:07:11 2012 +0000 + + smsc95xx: enable power saving mode during system suspend + + This patch enables the device to enter its lowest power SUSPEND2 + state during system suspend, instead of staying up using full power. + + Patch updated to not add two pointers to .suspend & .resume. + + Patch updated to replace BUG_ON with WARN_ON_ONCE and return. + + Signed-off-by: Steve Glendinning + Signed-off-by: David S. Miller + +Index: linux-3.2.46/drivers/net/usb/smsc95xx.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/usb/smsc95xx.c 2013-07-26 19:37:30.000000000 +0000 ++++ linux-3.2.46/drivers/net/usb/smsc95xx.c 2013-07-26 19:37:31.000000000 +0000 +@@ -1073,6 +1073,32 @@ + } + } + ++static int smsc95xx_suspend(struct usb_interface *intf, pm_message_t message) ++{ ++ struct usbnet *dev = usb_get_intfdata(intf); ++ int ret; ++ u32 val; ++ ++ if (WARN_ON_ONCE(!dev)) ++ return -EINVAL; ++ ++ ret = usbnet_suspend(intf, message); ++ check_warn_return(ret, "usbnet_suspend error"); ++ ++ netdev_info(dev->net, "entering SUSPEND2 mode"); ++ ++ ret = smsc95xx_read_reg(dev, PM_CTRL, &val); ++ check_warn_return(ret, "Error reading PM_CTRL"); ++ ++ val &= ~(PM_CTL_SUS_MODE_ | PM_CTL_WUPS_ | PM_CTL_PHY_RST_); ++ val |= PM_CTL_SUS_MODE_2; ++ ++ ret = smsc95xx_write_reg(dev, PM_CTRL, val); ++ check_warn_return(ret, "Error writing PM_CTRL"); ++ ++ return 0; ++} ++ + static void smsc95xx_rx_csum_offload(struct sk_buff *skb) + { + skb->csum = *(u16 *)(skb_tail_pointer(skb) - 2); +@@ -1335,7 +1361,7 @@ + .name = "smsc95xx", + .id_table = products, + .probe = usbnet_probe, +- .suspend = usbnet_suspend, ++ .suspend = smsc95xx_suspend, + .resume = usbnet_resume, + .reset_resume = usbnet_resume, + .disconnect = usbnet_disconnect, +Index: linux-3.2.46/drivers/net/usb/smsc95xx.h +=================================================================== +--- linux-3.2.46.orig/drivers/net/usb/smsc95xx.h 2013-07-26 19:37:27.000000000 +0000 ++++ linux-3.2.46/drivers/net/usb/smsc95xx.h 2013-07-26 19:37:31.000000000 +0000 +@@ -84,12 +84,16 @@ + #define HW_CFG_BCE_ (0x00000002) + #define HW_CFG_SRST_ (0x00000001) + ++#define RX_FIFO_INF (0x18) ++ + #define PM_CTRL (0x20) ++#define PM_CTL_RES_CLR_WKP_STS (0x00000200) + #define PM_CTL_DEV_RDY_ (0x00000080) + #define PM_CTL_SUS_MODE_ (0x00000060) + #define PM_CTL_SUS_MODE_0 (0x00000000) + #define PM_CTL_SUS_MODE_1 (0x00000020) +-#define PM_CTL_SUS_MODE_2 (0x00000060) ++#define PM_CTL_SUS_MODE_2 (0x00000040) ++#define PM_CTL_SUS_MODE_3 (0x00000060) + #define PM_CTL_PHY_RST_ (0x00000010) + #define PM_CTL_WOL_EN_ (0x00000008) + #define PM_CTL_ED_EN_ (0x00000004) diff -Nru linux-3.2.46/debian/patches/rpi/rpi_280_70b722a642e607891e302195ad970d39f30325e5.patch linux-3.2.46/debian/patches/rpi/rpi_280_70b722a642e607891e302195ad970d39f30325e5.patch --- linux-3.2.46/debian/patches/rpi/rpi_280_70b722a642e607891e302195ad970d39f30325e5.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_280_70b722a642e607891e302195ad970d39f30325e5.patch 2013-07-26 19:37:33.000000000 +0000 @@ -0,0 +1,281 @@ +commit 70b722a642e607891e302195ad970d39f30325e5 +Author: Steve Glendinning +Date: Fri Sep 28 00:07:12 2012 +0000 + + smsc95xx: add wol magic packet support + + This patch enables wake from system suspend on magic packet. + + Patch updated to replace BUG_ON with WARN_ON_ONCE and return. + + Signed-off-by: Steve Glendinning + Signed-off-by: David S. Miller + +Index: linux-3.2.46/drivers/net/usb/smsc95xx.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/usb/smsc95xx.c 2013-07-26 19:37:31.000000000 +0000 ++++ linux-3.2.46/drivers/net/usb/smsc95xx.c 2013-07-26 19:37:32.000000000 +0000 +@@ -47,6 +47,7 @@ + #define SMSC95XX_TX_OVERHEAD (8) + #define SMSC95XX_TX_OVERHEAD_CSUM (12) + #define MAC_ADDR_LEN (6) ++#define SUPPORTED_WAKE (WAKE_MAGIC) + + #define check_warn(ret, fmt, args...) \ + ({ if (ret < 0) netdev_warn(dev->net, fmt, ##args); }) +@@ -61,6 +62,7 @@ + u32 mac_cr; + u32 hash_hi; + u32 hash_lo; ++ u32 wolopts; + spinlock_t mac_cr_lock; + }; + +@@ -130,6 +132,30 @@ + return ret; + } + ++static int smsc95xx_set_feature(struct usbnet *dev, u32 feature) ++{ ++ if (WARN_ON_ONCE(!dev)) ++ return -EINVAL; ++ ++ cpu_to_le32s(&feature); ++ ++ return usb_control_msg(dev->udev, usb_sndctrlpipe(dev->udev, 0), ++ USB_REQ_SET_FEATURE, USB_RECIP_DEVICE, feature, 0, NULL, 0, ++ USB_CTRL_SET_TIMEOUT); ++} ++ ++static int smsc95xx_clear_feature(struct usbnet *dev, u32 feature) ++{ ++ if (WARN_ON_ONCE(!dev)) ++ return -EINVAL; ++ ++ cpu_to_le32s(&feature); ++ ++ return usb_control_msg(dev->udev, usb_sndctrlpipe(dev->udev, 0), ++ USB_REQ_CLEAR_FEATURE, USB_RECIP_DEVICE, feature, 0, NULL, 0, ++ USB_CTRL_SET_TIMEOUT); ++} ++ + /* Loop until the read is completed with timeout + * called with phy_mutex held */ + static int __must_check smsc95xx_phy_wait_not_busy(struct usbnet *dev) +@@ -640,6 +666,26 @@ + } + } + ++static void smsc95xx_ethtool_get_wol(struct net_device *net, ++ struct ethtool_wolinfo *wolinfo) ++{ ++ struct usbnet *dev = netdev_priv(net); ++ struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]); ++ ++ wolinfo->supported = SUPPORTED_WAKE; ++ wolinfo->wolopts = pdata->wolopts; ++} ++ ++static int smsc95xx_ethtool_set_wol(struct net_device *net, ++ struct ethtool_wolinfo *wolinfo) ++{ ++ struct usbnet *dev = netdev_priv(net); ++ struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]); ++ ++ pdata->wolopts = wolinfo->wolopts & SUPPORTED_WAKE; ++ return 0; ++} ++ + static const struct ethtool_ops smsc95xx_ethtool_ops = { + .get_link = usbnet_get_link, + .nway_reset = usbnet_nway_reset, +@@ -653,6 +699,8 @@ + .set_eeprom = smsc95xx_ethtool_set_eeprom, + .get_regs_len = smsc95xx_ethtool_getregslen, + .get_regs = smsc95xx_ethtool_getregs, ++ .get_wol = smsc95xx_ethtool_get_wol, ++ .set_wol = smsc95xx_ethtool_set_wol, + }; + + static int smsc95xx_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd) +@@ -1076,26 +1124,147 @@ + static int smsc95xx_suspend(struct usb_interface *intf, pm_message_t message) + { + struct usbnet *dev = usb_get_intfdata(intf); ++ struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]); + int ret; + u32 val; + +- if (WARN_ON_ONCE(!dev)) +- return -EINVAL; +- + ret = usbnet_suspend(intf, message); + check_warn_return(ret, "usbnet_suspend error"); + +- netdev_info(dev->net, "entering SUSPEND2 mode"); ++ /* if no wol options set, enter lowest power SUSPEND2 mode */ ++ if (!(pdata->wolopts & SUPPORTED_WAKE)) { ++ netdev_info(dev->net, "entering SUSPEND2 mode"); ++ ++ /* disable energy detect (link up) & wake up events */ ++ ret = smsc95xx_read_reg(dev, WUCSR, &val); ++ check_warn_return(ret, "Error reading WUCSR"); ++ ++ val &= ~(WUCSR_MPEN_ | WUCSR_WAKE_EN_); ++ ++ ret = smsc95xx_write_reg(dev, WUCSR, val); ++ check_warn_return(ret, "Error writing WUCSR"); ++ ++ ret = smsc95xx_read_reg(dev, PM_CTRL, &val); ++ check_warn_return(ret, "Error reading PM_CTRL"); ++ ++ val &= ~(PM_CTL_ED_EN_ | PM_CTL_WOL_EN_); ++ ++ ret = smsc95xx_write_reg(dev, PM_CTRL, val); ++ check_warn_return(ret, "Error writing PM_CTRL"); ++ ++ /* enter suspend2 mode */ ++ ret = smsc95xx_read_reg(dev, PM_CTRL, &val); ++ check_warn_return(ret, "Error reading PM_CTRL"); ++ ++ val &= ~(PM_CTL_SUS_MODE_ | PM_CTL_WUPS_ | PM_CTL_PHY_RST_); ++ val |= PM_CTL_SUS_MODE_2; ++ ++ ret = smsc95xx_write_reg(dev, PM_CTRL, val); ++ check_warn_return(ret, "Error writing PM_CTRL"); ++ ++ return 0; ++ } ++ ++ if (pdata->wolopts & WAKE_MAGIC) { ++ /* clear any pending magic packet status */ ++ ret = smsc95xx_read_reg(dev, WUCSR, &val); ++ check_warn_return(ret, "Error reading WUCSR"); ++ ++ val |= WUCSR_MPR_; ++ ++ ret = smsc95xx_write_reg(dev, WUCSR, val); ++ check_warn_return(ret, "Error writing WUCSR"); ++ } ++ ++ /* enable/disable magic packup wake */ ++ ret = smsc95xx_read_reg(dev, WUCSR, &val); ++ check_warn_return(ret, "Error reading WUCSR"); ++ ++ if (pdata->wolopts & WAKE_MAGIC) { ++ netdev_info(dev->net, "enabling magic packet wakeup"); ++ val |= WUCSR_MPEN_; ++ } else { ++ netdev_info(dev->net, "disabling magic packet wakeup"); ++ val &= ~WUCSR_MPEN_; ++ } ++ ++ ret = smsc95xx_write_reg(dev, WUCSR, val); ++ check_warn_return(ret, "Error writing WUCSR"); ++ ++ /* enable wol wakeup source */ ++ ret = smsc95xx_read_reg(dev, PM_CTRL, &val); ++ check_warn_return(ret, "Error reading PM_CTRL"); ++ ++ val |= PM_CTL_WOL_EN_; ++ ++ ret = smsc95xx_write_reg(dev, PM_CTRL, val); ++ check_warn_return(ret, "Error writing PM_CTRL"); ++ ++ /* enable receiver */ ++ smsc95xx_start_rx_path(dev); ++ ++ /* some wol options are enabled, so enter SUSPEND0 */ ++ netdev_info(dev->net, "entering SUSPEND0 mode"); + + ret = smsc95xx_read_reg(dev, PM_CTRL, &val); + check_warn_return(ret, "Error reading PM_CTRL"); + +- val &= ~(PM_CTL_SUS_MODE_ | PM_CTL_WUPS_ | PM_CTL_PHY_RST_); +- val |= PM_CTL_SUS_MODE_2; ++ val &= (~(PM_CTL_SUS_MODE_ | PM_CTL_WUPS_ | PM_CTL_PHY_RST_)); ++ val |= PM_CTL_SUS_MODE_0; + + ret = smsc95xx_write_reg(dev, PM_CTRL, val); + check_warn_return(ret, "Error writing PM_CTRL"); + ++ /* clear wol status */ ++ val &= ~PM_CTL_WUPS_; ++ val |= PM_CTL_WUPS_WOL_; ++ ret = smsc95xx_write_reg(dev, PM_CTRL, val); ++ check_warn_return(ret, "Error writing PM_CTRL"); ++ ++ /* read back PM_CTRL */ ++ ret = smsc95xx_read_reg(dev, PM_CTRL, &val); ++ check_warn_return(ret, "Error reading PM_CTRL"); ++ ++ smsc95xx_set_feature(dev, USB_DEVICE_REMOTE_WAKEUP); ++ ++ return 0; ++} ++ ++static int smsc95xx_resume(struct usb_interface *intf) ++{ ++ struct usbnet *dev = usb_get_intfdata(intf); ++ struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]); ++ int ret; ++ u32 val; ++ ++ BUG_ON(!dev); ++ ++ if (pdata->wolopts & WAKE_MAGIC) { ++ smsc95xx_clear_feature(dev, USB_DEVICE_REMOTE_WAKEUP); ++ ++ /* Disable magic packup wake */ ++ ret = smsc95xx_read_reg(dev, WUCSR, &val); ++ check_warn_return(ret, "Error reading WUCSR"); ++ ++ val &= ~WUCSR_MPEN_; ++ ++ ret = smsc95xx_write_reg(dev, WUCSR, val); ++ check_warn_return(ret, "Error writing WUCSR"); ++ ++ /* clear wake-up status */ ++ ret = smsc95xx_read_reg(dev, PM_CTRL, &val); ++ check_warn_return(ret, "Error reading PM_CTRL"); ++ ++ val &= ~PM_CTL_WOL_EN_; ++ val |= PM_CTL_WUPS_; ++ ++ ret = smsc95xx_write_reg(dev, PM_CTRL, val); ++ check_warn_return(ret, "Error writing PM_CTRL"); ++ } ++ ++ return usbnet_resume(intf); ++ check_warn_return(ret, "usbnet_resume error"); ++ + return 0; + } + +@@ -1362,8 +1531,8 @@ + .id_table = products, + .probe = usbnet_probe, + .suspend = smsc95xx_suspend, +- .resume = usbnet_resume, +- .reset_resume = usbnet_resume, ++ .resume = smsc95xx_resume, ++ .reset_resume = smsc95xx_resume, + .disconnect = usbnet_disconnect, + }; + +Index: linux-3.2.46/drivers/net/usb/smsc95xx.h +=================================================================== +--- linux-3.2.46.orig/drivers/net/usb/smsc95xx.h 2013-07-26 19:37:31.000000000 +0000 ++++ linux-3.2.46/drivers/net/usb/smsc95xx.h 2013-07-26 19:37:32.000000000 +0000 +@@ -205,6 +205,11 @@ + #define WUFF (0x128) + + #define WUCSR (0x12C) ++#define WUCSR_GUE_ (0x00000200) ++#define WUCSR_WUFR_ (0x00000040) ++#define WUCSR_MPR_ (0x00000020) ++#define WUCSR_WAKE_EN_ (0x00000004) ++#define WUCSR_MPEN_ (0x00000002) + + #define COE_CR (0x130) + #define Tx_COE_EN_ (0x00010000) diff -Nru linux-3.2.46/debian/patches/rpi/rpi_281_59b43cdfbaf44e701761891dcf77cf40969232a4.patch linux-3.2.46/debian/patches/rpi/rpi_281_59b43cdfbaf44e701761891dcf77cf40969232a4.patch --- linux-3.2.46/debian/patches/rpi/rpi_281_59b43cdfbaf44e701761891dcf77cf40969232a4.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_281_59b43cdfbaf44e701761891dcf77cf40969232a4.patch 2013-07-26 19:37:34.000000000 +0000 @@ -0,0 +1,32 @@ +commit 59b43cdfbaf44e701761891dcf77cf40969232a4 +Author: Steve Glendinning +Date: Fri Nov 2 00:44:20 2012 +0000 + + smsc95xx: fix tx checksum offload for big endian + + f7b2927 introduced tx checksum offload support for smsc95xx, + and enabled it by default. This feature doesn't take + endianness into account, so causes most tx to fail on + those platforms. + + This patch fixes the problem fully by adding the missing + conversion. + + An alternate workaround is to disable TX checksum offload + on those platforms. The cpu impact of this feature is very low. + + Signed-off-by: Steve Glendinning + Signed-off-by: David S. Miller + +Index: linux-3.2.46/drivers/net/usb/smsc95xx.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/usb/smsc95xx.c 2013-07-26 19:37:32.000000000 +0000 ++++ linux-3.2.46/drivers/net/usb/smsc95xx.c 2013-07-26 19:37:34.000000000 +0000 +@@ -1399,6 +1399,7 @@ + } else { + u32 csum_preamble = smsc95xx_calc_csum_preamble(skb); + skb_push(skb, 4); ++ cpu_to_le32s(&csum_preamble); + memcpy(skb->data, &csum_preamble, 4); + } + } diff -Nru linux-3.2.46/debian/patches/rpi/rpi_282_6f2064cb6807ac4a4d9edf258424db99f41b4f2b.patch linux-3.2.46/debian/patches/rpi/rpi_282_6f2064cb6807ac4a4d9edf258424db99f41b4f2b.patch --- linux-3.2.46/debian/patches/rpi/rpi_282_6f2064cb6807ac4a4d9edf258424db99f41b4f2b.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_282_6f2064cb6807ac4a4d9edf258424db99f41b4f2b.patch 2013-07-26 19:37:36.000000000 +0000 @@ -0,0 +1,23 @@ +commit 6f2064cb6807ac4a4d9edf258424db99f41b4f2b +Author: popcornmix +Date: Thu Nov 8 00:00:18 2012 +0000 + + Enable building of lirc-rpi + +Index: linux-3.2.46/arch/arm/configs/bcmrpi_defconfig +=================================================================== +--- linux-3.2.46.orig/arch/arm/configs/bcmrpi_defconfig 2013-07-26 19:37:19.000000000 +0000 ++++ linux-3.2.46/arch/arm/configs/bcmrpi_defconfig 2013-07-26 19:37:35.000000000 +0000 +@@ -812,6 +812,12 @@ + CONFIG_PRISM2_USB=m + CONFIG_R8712U=m + CONFIG_ZRAM=m ++CONFIG_STAGING_MEDIA=y ++CONFIG_LIRC_STAGING=y ++CONFIG_LIRC_IGORPLUGUSB=m ++CONFIG_LIRC_RPI=m ++CONFIG_LIRC_SASEM=m ++CONFIG_LIRC_TTUSBIR=m + # CONFIG_IOMMU_SUPPORT is not set + CONFIG_EXT4_FS=y + CONFIG_EXT4_FS_POSIX_ACL=y diff -Nru linux-3.2.46/debian/patches/rpi/rpi_283_22e8df63d48443cb7fc4feb2762fdf17200f955c.patch linux-3.2.46/debian/patches/rpi/rpi_283_22e8df63d48443cb7fc4feb2762fdf17200f955c.patch --- linux-3.2.46/debian/patches/rpi/rpi_283_22e8df63d48443cb7fc4feb2762fdf17200f955c.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_283_22e8df63d48443cb7fc4feb2762fdf17200f955c.patch 2013-07-26 19:37:37.000000000 +0000 @@ -0,0 +1,227 @@ +commit 22e8df63d48443cb7fc4feb2762fdf17200f955c +Author: dero +Date: Mon Nov 19 12:46:06 2012 +0100 + + Lazy CRC quirk: Implemented retrying mechanisms for SD SSR and SCR, disabled missing_status and spurious CRC ACMD51 quirks by default (should be fixed by the retrying-mechanishm) + +Index: linux-3.2.46/drivers/mmc/core/sd.c +=================================================================== +--- linux-3.2.46.orig/drivers/mmc/core/sd.c 2013-05-30 13:35:16.000000000 +0000 ++++ linux-3.2.46/drivers/mmc/core/sd.c 2013-07-26 19:37:36.000000000 +0000 +@@ -13,6 +13,8 @@ + #include + #include + #include ++#include ++#include + + #include + #include +@@ -58,6 +60,15 @@ + __res & __mask; \ + }) + ++// timeout for tries ++static const unsigned long retry_timeout_ms= 10*1000; ++ ++// try at least 10 times, even if timeout is reached ++static const int retry_min_tries= 10; ++ ++// delay between tries ++static const unsigned long retry_delay_ms= 10; ++ + /* + * Given the decoded CSD structure, decode the raw CID to our CID structure. + */ +@@ -210,12 +221,62 @@ + } + + /* +- * Fetch and process SD Status register. ++ * Fetch and process SD Configuration Register. ++ */ ++static int mmc_read_scr(struct mmc_card *card) ++{ ++ unsigned long timeout_at; ++ int err, tries; ++ ++ timeout_at= jiffies + msecs_to_jiffies( retry_timeout_ms ); ++ tries= 0; ++ ++ while( tries < retry_min_tries || time_before( jiffies, timeout_at ) ) ++ { ++ unsigned long delay_at; ++ tries++; ++ ++ err = mmc_app_send_scr(card, card->raw_scr); ++ if( !err ) ++ break; // sucess!!! ++ ++ touch_nmi_watchdog(); // we are still alive! ++ ++ // delay ++ delay_at= jiffies + msecs_to_jiffies( retry_delay_ms ); ++ while( time_before( jiffies, delay_at ) ) ++ { ++ mdelay( 1 ); ++ touch_nmi_watchdog(); // we are still alive! ++ } ++ } ++ ++ if( err) ++ { ++ pr_err("%s: failed to read SD Configuration register (SCR) after %d tries during %lu ms, error %d\n", mmc_hostname(card->host), tries, retry_timeout_ms, err ); ++ return err; ++ } ++ ++ if( tries > 1 ) ++ { ++ pr_info("%s: could read SD Configuration register (SCR) at the %dth attempt\n", mmc_hostname(card->host), tries ); ++ } ++ ++ err = mmc_decode_scr(card); ++ if (err) ++ return err; ++ ++ return err; ++} ++ ++/* ++ * Fetch and process SD Status Register. + */ + static int mmc_read_ssr(struct mmc_card *card) + { ++ unsigned long timeout_at; + unsigned int au, es, et, eo; +- int err, i; ++ int err, i, tries; + u32 *ssr; + + if (!(card->csd.cmdclass & CCC_APP_SPEC)) { +@@ -227,15 +288,41 @@ + ssr = kmalloc(64, GFP_KERNEL); + if (!ssr) + return -ENOMEM; +- +- err = mmc_app_sd_status(card, ssr); +- if (err) { +- pr_warning("%s: problem reading SD Status " +- "register.\n", mmc_hostname(card->host)); +- err = 0; ++ ++ timeout_at= jiffies + msecs_to_jiffies( retry_timeout_ms ); ++ tries= 0; ++ ++ while( tries < retry_min_tries || time_before( jiffies, timeout_at ) ) ++ { ++ unsigned long delay_at; ++ tries++; ++ ++ err= mmc_app_sd_status(card, ssr); ++ if( !err ) ++ break; // sucess!!! ++ ++ touch_nmi_watchdog(); // we are still alive! ++ ++ // delay ++ delay_at= jiffies + msecs_to_jiffies( retry_delay_ms ); ++ while( time_before( jiffies, delay_at ) ) ++ { ++ mdelay( 1 ); ++ touch_nmi_watchdog(); // we are still alive! ++ } ++ } ++ ++ if( err) ++ { ++ pr_err("%s: failed to read SD Status register (SSR) after %d tries during %lu ms, error %d\n", mmc_hostname(card->host), tries, retry_timeout_ms, err ); + goto out; + } + ++ if( tries > 1 ) ++ { ++ pr_info("%s: could read SD Status register (SSR) at the %dth attempt\n", mmc_hostname(card->host), tries ); ++ } ++ + for (i = 0; i < 16; i++) + ssr[i] = be32_to_cpu(ssr[i]); + +@@ -803,15 +890,11 @@ + + if (!reinit) { + /* +- * Fetch SCR from card. ++ * Fetch and decode SD Configuration register. + */ +- err = mmc_app_send_scr(card, card->raw_scr); +- if (err) +- return err; +- +- err = mmc_decode_scr(card); +- if (err) +- return err; ++ err = mmc_read_scr(card); ++ if( err ) ++ return err; + + /* + * Fetch and process SD Status register. +Index: linux-3.2.46/drivers/mmc/host/sdhci-bcm2708.c +=================================================================== +--- linux-3.2.46.orig/drivers/mmc/host/sdhci-bcm2708.c 2013-07-26 19:36:48.000000000 +0000 ++++ linux-3.2.46/drivers/mmc/host/sdhci-bcm2708.c 2013-07-26 19:37:36.000000000 +0000 +@@ -141,7 +141,8 @@ + static bool allow_highspeed = 1; + static int emmc_clock_freq = BCM2708_EMMC_CLOCK_FREQ; + static bool sync_after_dma = 1; +-static bool missing_status = 1; ++static bool missing_status = 0; ++static bool spurious_crc_acmd51 = 0; + bool enable_llm = 1; + + #if 0 +@@ -1220,7 +1221,7 @@ + return 1; + } + +-static unsigned int sdhci_bcm2708_quirk_spurious_crc(struct sdhci_host *host) ++static unsigned int sdhci_bcm2708_quirk_spurious_crc_acmd51(struct sdhci_host *host) + { + return 1; + } +@@ -1270,7 +1271,6 @@ + .pdma_reset = sdhci_bcm2708_platdma_reset, + #endif + .extra_ints = sdhci_bcm2708_quirk_extra_ints, +- .spurious_crc_acmd51 = sdhci_bcm2708_quirk_spurious_crc, + .voltage_broken = sdhci_bcm2708_quirk_voltage_broken, + .uhs_broken = sdhci_bcm2708_uhs_broken, + }; +@@ -1315,6 +1315,11 @@ + sdhci_bcm2708_ops.missing_status = sdhci_bcm2708_missing_status; + } + ++ if( spurious_crc_acmd51 ) { ++ sdhci_bcm2708_ops.spurious_crc_acmd51 = sdhci_bcm2708_quirk_spurious_crc_acmd51; ++ } ++ ++ + printk("sdhci: %s low-latency mode\n",enable_llm?"Enable":"Disable"); + + host->hw_name = "BCM2708_Arasan"; +@@ -1518,6 +1523,7 @@ + module_param(emmc_clock_freq, int, 0444); + module_param(sync_after_dma, bool, 0444); + module_param(missing_status, bool, 0444); ++module_param(spurious_crc_acmd51, bool, 0444); + module_param(enable_llm, bool, 0444); + module_param(cycle_delay, int, 0444); + +@@ -1530,6 +1536,7 @@ + MODULE_PARM_DESC(emmc_clock_freq, "Specify the speed of emmc clock"); + MODULE_PARM_DESC(sync_after_dma, "Block in driver until dma complete"); + MODULE_PARM_DESC(missing_status, "Use the missing status quirk"); ++MODULE_PARM_DESC(spurious_crc_acmd51, "Use the spurious crc quirk for reading SCR (ACMD51)"); + MODULE_PARM_DESC(enable_llm, "Enable low-latency mode"); + + diff -Nru linux-3.2.46/debian/patches/rpi/rpi_284_71f3b547b9b54dc33604909090d0b44ec6abbb67.patch linux-3.2.46/debian/patches/rpi/rpi_284_71f3b547b9b54dc33604909090d0b44ec6abbb67.patch --- linux-3.2.46/debian/patches/rpi/rpi_284_71f3b547b9b54dc33604909090d0b44ec6abbb67.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_284_71f3b547b9b54dc33604909090d0b44ec6abbb67.patch 2013-07-26 19:37:39.000000000 +0000 @@ -0,0 +1,792 @@ +commit 71f3b547b9b54dc33604909090d0b44ec6abbb67 +Author: popcornmix +Date: Mon Nov 19 18:27:05 2012 +0000 + + Add Simon Hall's dma helper module, useful in future for X acceleration + +Index: linux-3.2.46/arch/arm/mach-bcm2708/Kconfig +=================================================================== +--- linux-3.2.46.orig/arch/arm/mach-bcm2708/Kconfig 2013-07-26 19:32:20.000000000 +0000 ++++ linux-3.2.46/arch/arm/mach-bcm2708/Kconfig 2013-07-26 19:37:38.000000000 +0000 +@@ -29,4 +29,11 @@ + help + Do not allow ARM to use GPU's L2 cache. Requires disable_l2cache in config.txt. + ++config BCM2708_DMAER ++ tristate "BCM2708 DMA helper" ++ depends on MACH_BCM2708 ++ default n ++ help ++ Enable DMA helper for accelerating X composition ++ + endmenu +Index: linux-3.2.46/arch/arm/mach-bcm2708/Makefile +=================================================================== +--- linux-3.2.46.orig/arch/arm/mach-bcm2708/Makefile 2013-07-26 19:36:45.000000000 +0000 ++++ linux-3.2.46/arch/arm/mach-bcm2708/Makefile 2013-07-26 19:37:38.000000000 +0000 +@@ -5,4 +5,5 @@ + obj-$(CONFIG_MACH_BCM2708) += clock.o bcm2708.o armctrl.o vcio.o power.o dma.o delay.o + obj-$(CONFIG_BCM2708_GPIO) += bcm2708_gpio.o + obj-$(CONFIG_BCM2708_VCMEM) += vc_mem.o ++obj-$(CONFIG_BCM2708_DMAER) += dmaer.o + +Index: linux-3.2.46/arch/arm/mach-bcm2708/dmaer.c +=================================================================== +--- /dev/null 1970-01-01 00:00:00.000000000 +0000 ++++ linux-3.2.46/arch/arm/mach-bcm2708/dmaer.c 2013-07-26 19:37:38.000000000 +0000 +@@ -0,0 +1,755 @@ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++ ++#include ++ ++MODULE_LICENSE("Dual BSD/GPL"); ++ ++//#define inline ++ ++/***** TYPES ****/ ++#define PAGES_PER_LIST 500 ++struct PageList ++{ ++ struct page *m_pPages[PAGES_PER_LIST]; ++ unsigned int m_used; ++ struct PageList *m_pNext; ++}; ++ ++struct VmaPageList ++{ ++ //each vma has a linked list of pages associated with it ++ struct PageList *m_pPageHead; ++ struct PageList *m_pPageTail; ++ unsigned int m_refCount; ++}; ++struct DmaControlBlock ++{ ++ unsigned int m_transferInfo; ++ void __user *m_pSourceAddr; ++ void __user *m_pDestAddr; ++ unsigned int m_xferLen; ++ unsigned int m_tdStride; ++ struct DmaControlBlock *m_pNext; ++ unsigned int m_blank1, m_blank2; ++}; ++ ++/***** DEFINES ******/ ++//magic number defining the module ++#define DMA_MAGIC 0xdd ++ ++//do user virtual to physical translation of the CB chain ++#define DMA_PREPARE _IOWR(DMA_MAGIC, 0, struct DmaControlBlock *) ++ ++//kick the pre-prepared CB chain ++#define DMA_KICK _IOW(DMA_MAGIC, 1, struct DmaControlBlock *) ++ ++//prepare it, kick it, wait for it ++#define DMA_PREPARE_KICK_WAIT _IOWR(DMA_MAGIC, 2, struct DmaControlBlock *) ++ ++//prepare it, kick it, don't wait for it ++#define DMA_PREPARE_KICK _IOWR(DMA_MAGIC, 3, struct DmaControlBlock *) ++ ++//not currently implemented ++#define DMA_WAIT_ONE _IO(DMA_MAGIC, 4, struct DmaControlBlock *) ++ ++//wait on all kicked CB chains ++#define DMA_WAIT_ALL _IO(DMA_MAGIC, 5) ++ ++//in order to discover the largest AXI burst that should be programmed into the transfer params ++#define DMA_MAX_BURST _IO(DMA_MAGIC, 6) ++ ++//set the address range through which the user address is assumed to already by a physical address ++#define DMA_SET_MIN_PHYS _IOW(DMA_MAGIC, 7, unsigned long) ++#define DMA_SET_MAX_PHYS _IOW(DMA_MAGIC, 8, unsigned long) ++ ++#define VIRT_TO_BUS_CACHE_SIZE 8 ++ ++/***** FILE OPS *****/ ++static int Open(struct inode *pInode, struct file *pFile); ++static int Release(struct inode *pInode, struct file *pFile); ++static long Ioctl(struct file *pFile, unsigned int cmd, unsigned long arg); ++static ssize_t Read(struct file *pFile, char __user *pUser, size_t count, loff_t *offp); ++static int Mmap(struct file *pFile, struct vm_area_struct *pVma); ++ ++/***** VMA OPS ****/ ++static void VmaOpen(struct vm_area_struct *pVma); ++static void VmaClose(struct vm_area_struct *pVma); ++static int VmaFault(struct vm_area_struct *pVma, struct vm_fault *pVmf); ++ ++/**** GENERIC ****/ ++static int __init dmaer_init(void); ++static void __exit dmaer_exit(void); ++ ++/*** OPS ***/ ++static struct vm_operations_struct g_vmOps = { ++ .open = VmaOpen, ++ .close = VmaClose, ++ .fault = VmaFault, ++}; ++ ++static struct file_operations g_fOps = { ++ .owner = THIS_MODULE, ++ .llseek = 0, ++ .read = Read, ++ .write = 0, ++ .unlocked_ioctl = Ioctl, ++ .open = Open, ++ .release = Release, ++ .mmap = Mmap, ++}; ++ ++/***** GLOBALS ******/ ++static dev_t g_majorMinor; ++static atomic_t g_oneLock = ATOMIC_INIT(1); ++static struct cdev g_cDev; ++static int g_trackedPages = 0; ++static unsigned int *g_pDmaChanBase; ++static int g_dmaIrq; ++static int g_dmaChan; ++ ++static unsigned long g_virtAddr[VIRT_TO_BUS_CACHE_SIZE]; ++static unsigned long g_busAddr[VIRT_TO_BUS_CACHE_SIZE]; ++static unsigned long g_cbVirtAddr; ++static unsigned long g_cbBusAddr; ++static int g_cacheInsertAt; ++static int g_cacheHit, g_cacheMiss; ++ ++//off by default ++static void __user *g_pMinPhys = (void __user *)-1; ++static void __user *g_pMaxPhys = (void __user *)0; ++ ++/****** CACHE OPERATIONS ********/ ++static inline void FlushAddrCache(void) ++{ ++ int count = 0; ++ for (count = 0; count < VIRT_TO_BUS_CACHE_SIZE; count++) ++ g_virtAddr[count] = 0xffffffff; //never going to match as we always chop the bottom bits anyway ++ ++ g_cbVirtAddr = 0xffffffff; ++ ++ g_cacheInsertAt = 0; ++} ++ ++//translate from a user virtual address to a bus address by mapping the page ++//NB this won't lock a page in memory, so to avoid potential paging issues using kernel logical addresses ++static inline void __iomem *UserVirtualToBus(void __user *pUser) ++{ ++ int mapped; ++ struct page *pPage; ++ void *phys; ++ ++ //map it (requiring that the pointer points to something that does not hang off the page boundary) ++ mapped = get_user_pages(current, current->mm, ++ (unsigned long)pUser, 1, ++ 1, 0, ++ &pPage, ++ 0); ++ ++ if (mapped <= 0) //error ++ return 0; ++ ++ //get the arm physical address ++ phys = page_address(pPage) + offset_in_page(pUser); ++ page_cache_release(pPage); ++ ++ //and now the bus address ++ return (void __iomem *)__virt_to_bus(phys); ++} ++ ++static inline void __iomem *UserVirtualToBusViaCbCache(void __user *pUser) ++{ ++ unsigned long virtual_page = (unsigned long)pUser & ~4095; ++ unsigned long page_offset = (unsigned long)pUser & 4095; ++ unsigned long bus_addr; ++ ++ if (g_cbVirtAddr == virtual_page) ++ { ++ bus_addr = g_cbBusAddr + page_offset; ++ g_cacheHit++; ++ return (void __iomem *)bus_addr; ++ } ++ else ++ { ++ bus_addr = (unsigned long)UserVirtualToBus(pUser); ++ ++ if (!bus_addr) ++ return 0; ++ ++ g_cbVirtAddr = virtual_page; ++ g_cbBusAddr = bus_addr & ~4095; ++ g_cacheMiss++; ++ ++ return (void __iomem *)bus_addr; ++ } ++} ++ ++//do the same as above, by query our virt->bus cache ++static inline void __iomem *UserVirtualToBusViaCache(void __user *pUser) ++{ ++ int count; ++ //get the page and its offset ++ unsigned long virtual_page = (unsigned long)pUser & ~4095; ++ unsigned long page_offset = (unsigned long)pUser & 4095; ++ unsigned long bus_addr; ++ ++ if (pUser >= g_pMinPhys && pUser < g_pMaxPhys) ++ { ++// printk(KERN_DEBUG "user->phys passthrough on %p\n", pUser); ++ return (void __iomem *)__virt_to_bus(pUser); ++ } ++ ++ //check the cache for our entry ++ for (count = 0; count < VIRT_TO_BUS_CACHE_SIZE; count++) ++ if (g_virtAddr[count] == virtual_page) ++ { ++ bus_addr = g_busAddr[count] + page_offset; ++ g_cacheHit++; ++ return (void __iomem *)bus_addr; ++ } ++ ++ //not found, look up manually and then insert its page address ++ bus_addr = (unsigned long)UserVirtualToBus(pUser); ++ ++ if (!bus_addr) ++ return 0; ++ ++ g_virtAddr[g_cacheInsertAt] = virtual_page; ++ g_busAddr[g_cacheInsertAt] = bus_addr & ~4095; ++ ++ //round robin ++ g_cacheInsertAt++; ++ if (g_cacheInsertAt == VIRT_TO_BUS_CACHE_SIZE) ++ g_cacheInsertAt = 0; ++ ++ g_cacheMiss++; ++ ++ return (void __iomem *)bus_addr; ++} ++ ++/***** FILE OPERATIONS ****/ ++static int Open(struct inode *pInode, struct file *pFile) ++{ ++ printk(KERN_DEBUG "file opening\n"); ++ ++ //only one at a time ++ if (!atomic_dec_and_test(&g_oneLock)) ++ { ++ atomic_inc(&g_oneLock); ++ return -EBUSY; ++ } ++ ++ return 0; ++} ++ ++static int Release(struct inode *pInode, struct file *pFile) ++{ ++ printk(KERN_DEBUG "file closing, %d pages tracked\n", g_trackedPages); ++ if (g_trackedPages) ++ printk(KERN_ERR "we\'re leaking memory!\n"); ++ ++ atomic_inc(&g_oneLock); ++ return 0; ++} ++ ++static struct DmaControlBlock __user *DmaPrepare(struct DmaControlBlock __user *pUserCB, int *pError) ++{ ++ struct DmaControlBlock kernCB; ++ struct DmaControlBlock __user *pUNext; ++ void __iomem *pSourceBus, __iomem *pDestBus; ++ ++ ++ //get the control block into kernel memory so we can work on it ++ if (copy_from_user(&kernCB, pUserCB, sizeof(struct DmaControlBlock)) != 0) ++ { ++ printk(KERN_ERR "copy_from_user failed for user cb %p\n", pUserCB); ++ *pError = 1; ++ return 0; ++ } ++ ++ if (kernCB.m_pSourceAddr == 0 || kernCB.m_pDestAddr == 0) ++ { ++ printk(KERN_ERR "faulty source (%p) dest (%p) addresses for user cb %p\n", ++ kernCB.m_pSourceAddr, kernCB.m_pDestAddr, pUserCB); ++ *pError = 1; ++ return 0; ++ } ++ ++ pSourceBus = UserVirtualToBusViaCache(kernCB.m_pSourceAddr); ++ pDestBus = UserVirtualToBusViaCache(kernCB.m_pDestAddr); ++ ++ if (!pSourceBus || !pDestBus) ++ { ++ printk(KERN_ERR "virtual to bus translation failure for source/dest\n"); ++ *pError = 1; ++ return 0; ++ } ++ ++ //update the user structure with the new bus addresses ++ kernCB.m_pSourceAddr = pSourceBus; ++ kernCB.m_pDestAddr = pDestBus; ++ ++ //sort out the bus address for the next block ++ pUNext = kernCB.m_pNext; ++ ++ if (kernCB.m_pNext) ++ { ++ void __iomem *pNextBus; ++ pNextBus = UserVirtualToBusViaCbCache(kernCB.m_pNext); ++ ++ if (!pNextBus) ++ { ++ printk(KERN_ERR "virtual to bus translation failure for m_pNext\n"); ++ *pError = 1; ++ return 0; ++ } ++ ++ //update the pointer with the bus address ++ kernCB.m_pNext = pNextBus; ++ } ++ ++ //write it back to user space ++ if (copy_to_user(pUserCB, &kernCB, sizeof(struct DmaControlBlock)) != 0) ++ { ++ printk(KERN_ERR "copy_to_user failed for cb %p\n", pUserCB); ++ *pError = 1; ++ return 0; ++ } ++ ++ __cpuc_flush_dcache_area(pUserCB, 32); ++ ++ *pError = 0; ++ return pUNext; ++} ++ ++static int DmaKick(struct DmaControlBlock __user *pUserCB) ++{ ++ void __iomem *pBusCB; ++ ++ pBusCB = UserVirtualToBusViaCbCache(pUserCB); ++ if (!pBusCB) ++ { ++ printk(KERN_ERR "virtual to bus translation failure for cb\n"); ++ return 1; ++ } ++ ++ //flush_cache_all(); ++ ++ bcm_dma_start(g_pDmaChanBase, (dma_addr_t)pBusCB); ++ ++ return 0; ++} ++ ++static void DmaWaitAll(void) ++{ ++ int counter = 0; ++ volatile int inner_count; ++ volatile unsigned int cs; ++ //unsigned long time_before, time_after; ++ ++ //time_before = jiffies; ++ //bcm_dma_wait_idle(g_pDmaChanBase); ++ dsb(); ++ ++ cs = readl(g_pDmaChanBase); ++ ++ while ((cs & 1) == 1) ++ { ++ cs = readl(g_pDmaChanBase); ++ counter++; ++ ++ for (inner_count = 0; inner_count < 32; inner_count++); ++ ++ asm volatile ("MCR p15,0,r0,c7,c0,4 \n"); ++ //cpu_do_idle(); ++ if (counter >= 1000000) ++ { ++ printk(KERN_WARNING "DMA failed to finish in a timely fashion\n"); ++ break; ++ } ++ } ++ //time_after = jiffies; ++ //printk(KERN_DEBUG "done, counter %d, cs %08x", counter, cs); ++ //printk(KERN_DEBUG "took %ld jiffies, %d HZ\n", time_after - time_before, HZ); ++} ++ ++static long Ioctl(struct file *pFile, unsigned int cmd, unsigned long arg) ++{ ++ int error = 0; ++ //printk(KERN_DEBUG "ioctl cmd %x arg %lx\n", cmd, arg); ++ ++ switch (cmd) ++ { ++ case DMA_PREPARE: ++ case DMA_PREPARE_KICK: ++ case DMA_PREPARE_KICK_WAIT: ++ { ++ struct DmaControlBlock __user *pUCB = (struct DmaControlBlock *)arg; ++ int steps = 0; ++ //unsigned long start_time = jiffies; ++ ++ //flush our address cache ++ FlushAddrCache(); ++ ++// printk(KERN_DEBUG "dma prepare\n"); ++ ++ //do virtual to bus translation for each entry ++ do ++ { ++ pUCB = DmaPrepare(pUCB, &error); ++ } while (error == 0 && ++steps && pUCB); ++ //printk(KERN_DEBUG "prepare done in %d steps, %ld\n", steps, jiffies - start_time); ++ ++ //carry straight on if we want to kick too ++ if (cmd == DMA_PREPARE || error) ++ { ++// printk(KERN_DEBUG "falling out\n"); ++ break; ++ } ++ }; ++ case DMA_KICK: ++// printk(KERN_DEBUG "dma begin\n"); ++ ++ if (cmd == DMA_KICK) ++ FlushAddrCache(); ++ ++ DmaKick((struct DmaControlBlock __user *)arg); ++ ++ if (cmd != DMA_PREPARE_KICK_WAIT) ++ break; ++/* case DMA_WAIT_ONE: ++ //printk(KERN_DEBUG "dma wait one\n"); ++ break;*/ ++ case DMA_WAIT_ALL: ++ //printk(KERN_DEBUG "dma wait all\n"); ++ DmaWaitAll(); ++ break; ++ case DMA_MAX_BURST: ++ if (g_dmaChan == 0) ++ return 10; ++ else ++ return 5; ++ case DMA_SET_MIN_PHYS: ++ g_pMinPhys = (void __user *)arg; ++ printk("min/max user/phys bypass set to %p %p\n", g_pMinPhys, g_pMaxPhys); ++ break; ++ case DMA_SET_MAX_PHYS: ++ g_pMaxPhys = (void __user *)arg; ++ printk("min/max user/phys bypass set to %p %p\n", g_pMinPhys, g_pMaxPhys); ++ break; ++ default: ++ printk(KERN_DEBUG "unknown ioctl: %d\n", cmd); ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++static ssize_t Read(struct file *pFile, char __user *pUser, size_t count, loff_t *offp) ++{ ++ /*printk(KERN_DEBUG "file read pFile %p pUser %p count %ld offp %p\n", ++ pFile, pUser, count, offp); ++ printk(KERN_DEBUG "phys pFile %lx pUser %lx offp %lx\n", ++ __pa(pFile), __pa(pUser), __pa(offp)); ++ printk(KERN_DEBUG "bus pFile %lx pUser %lx offp %lx\n", ++ virt_to_bus(pFile), virt_to_bus(pUser), virt_to_bus(offp));*/ ++ return -EIO; ++} ++ ++static int Mmap(struct file *pFile, struct vm_area_struct *pVma) ++{ ++ struct PageList *pPages; ++ struct VmaPageList *pVmaList; ++ ++// printk(KERN_DEBUG "MMAP vma %p, length %ld (%s %d)\n", ++// pVma, pVma->vm_end - pVma->vm_start, ++// current->comm, current->pid); ++// printk(KERN_DEBUG "MMAP %p %d (tracked %d)\n", pVma, current->pid, g_trackedPages); ++ ++ //make a new page list ++ pPages = (struct PageList *)kmalloc(sizeof(struct PageList), GFP_KERNEL); ++ if (!pPages) ++ { ++ printk(KERN_ERR "couldn\'t allocate a new page list (%s %d)\n", ++ current->comm, current->pid); ++ return -ENOMEM; ++ } ++ ++ //clear the page list ++ pPages->m_used = 0; ++ pPages->m_pNext = 0; ++ ++ //insert our vma and new page list somewhere ++ if (!pVma->vm_private_data) ++ { ++ struct VmaPageList *pList; ++ ++// printk(KERN_DEBUG "new vma list, making new one (%s %d)\n", ++// current->comm, current->pid); ++ ++ //make a new vma list ++ pList = (struct VmaPageList *)kmalloc(sizeof(struct VmaPageList), GFP_KERNEL); ++ if (!pList) ++ { ++ printk(KERN_ERR "couldn\'t allocate vma page list (%s %d)\n", ++ current->comm, current->pid); ++ kfree(pPages); ++ return -ENOMEM; ++ } ++ ++ //clear this list ++ pVma->vm_private_data = (void *)pList; ++ pList->m_refCount = 0; ++ } ++ ++ pVmaList = (struct VmaPageList *)pVma->vm_private_data; ++ ++ //add it to the vma list ++ pVmaList->m_pPageHead = pPages; ++ pVmaList->m_pPageTail = pPages; ++ ++ pVma->vm_ops = &g_vmOps; ++ pVma->vm_flags |= VM_RESERVED; ++ ++ VmaOpen(pVma); ++ ++ return 0; ++} ++ ++/****** VMA OPERATIONS ******/ ++ ++static void VmaOpen(struct vm_area_struct *pVma) ++{ ++ struct VmaPageList *pVmaList; ++ ++// printk(KERN_DEBUG "vma open %p private %p (%s %d), %d live pages\n", pVma, pVma->vm_private_data, current->comm, current->pid, g_trackedPages); ++// printk(KERN_DEBUG "OPEN %p %d %ld pages (tracked pages %d)\n", ++// pVma, current->pid, (pVma->vm_end - pVma->vm_start) >> 12, ++// g_trackedPages); ++ ++ pVmaList = (struct VmaPageList *)pVma->vm_private_data; ++ ++ if (pVmaList) ++ { ++ pVmaList->m_refCount++; ++// printk(KERN_DEBUG "ref count is now %d\n", pVmaList->m_refCount); ++ } ++// else ++// printk(KERN_DEBUG "err, open but no vma page list\n"); ++} ++ ++static void VmaClose(struct vm_area_struct *pVma) ++{ ++ struct VmaPageList *pVmaList; ++ int freed = 0; ++ ++// printk(KERN_DEBUG "vma close %p private %p (%s %d)\n", pVma, pVma->vm_private_data, current->comm, current->pid); ++ ++ //find our vma in the list ++ pVmaList = (struct VmaPageList *)pVma->vm_private_data; ++ ++ //may be a fork ++ if (pVmaList) ++ { ++ struct PageList *pPages; ++ ++ pVmaList->m_refCount--; ++ ++ if (pVmaList->m_refCount == 0) ++ { ++// printk(KERN_DEBUG "found vma, freeing pages (%s %d)\n", ++// current->comm, current->pid); ++ ++ pPages = pVmaList->m_pPageHead; ++ ++ if (!pPages) ++ { ++ printk(KERN_ERR "no page list (%s %d)!\n", ++ current->comm, current->pid); ++ return; ++ } ++ ++ while (pPages) ++ { ++ struct PageList *next; ++ int count; ++ ++// printk(KERN_DEBUG "page list (%s %d)\n", ++// current->comm, current->pid); ++ ++ next = pPages->m_pNext; ++ for (count = 0; count < pPages->m_used; count++) ++ { ++// printk(KERN_DEBUG "freeing page %p (%s %d)\n", ++// pPages->m_pPages[count], ++// current->comm, current->pid); ++ __free_pages(pPages->m_pPages[count], 0); ++ g_trackedPages--; ++ freed++; ++ } ++ ++// printk(KERN_DEBUG "freeing page list (%s %d)\n", ++// current->comm, current->pid); ++ kfree(pPages); ++ pPages = next; ++ } ++ ++ //remove our vma from the list ++ kfree(pVmaList); ++ pVma->vm_private_data = 0; ++ } ++// else ++// printk(KERN_DEBUG "ref count is %d, not closing\n", pVmaList->m_refCount); ++ } ++ else ++ { ++// printk(KERN_ERR "uh-oh, vma %p not found (%s %d)!\n", pVma, current->comm, current->pid); ++// printk(KERN_ERR "CLOSE ERR\n"); ++ } ++ ++// printk(KERN_DEBUG "CLOSE %p %d %d pages (tracked pages %d)", ++// pVma, current->pid, freed, g_trackedPages); ++ ++// printk(KERN_DEBUG "%d pages open\n", g_trackedPages); ++} ++ ++static int VmaFault(struct vm_area_struct *pVma, struct vm_fault *pVmf) ++{ ++// printk(KERN_DEBUG "vma fault for vma %p private %p at offset %ld (%s %d)\n", pVma, pVma->vm_private_data, pVmf->pgoff, ++// current->comm, current->pid); ++ //printk(KERN_DEBUG "FAULT\n"); ++ pVmf->page = alloc_page(GFP_KERNEL); ++ /*if (pVmf->page) ++ printk(KERN_DEBUG "alloc page virtual %p\n", page_address(pVmf->page));*/ ++ ++ if (!pVmf->page) ++ { ++ printk(KERN_ERR "vma fault oom (%s %d)\n", current->comm, current->pid); ++ return VM_FAULT_OOM; ++ } ++ else ++ { ++ struct VmaPageList *pVmaList; ++ ++ get_page(pVmf->page); ++ g_trackedPages++; ++ ++ //find our vma in the list ++ pVmaList = (struct VmaPageList *)pVma->vm_private_data; ++ ++ if (pVmaList) ++ { ++// printk(KERN_DEBUG "vma found (%s %d)\n", current->comm, current->pid); ++ ++ if (pVmaList->m_pPageTail->m_used == PAGES_PER_LIST) ++ { ++// printk(KERN_DEBUG "making new page list (%s %d)\n", current->comm, current->pid); ++ //making a new page list ++ pVmaList->m_pPageTail->m_pNext = (struct PageList *)kmalloc(sizeof(struct PageList), GFP_KERNEL); ++ if (!pVmaList->m_pPageTail->m_pNext) ++ return -ENOMEM; ++ ++ //update the tail pointer ++ pVmaList->m_pPageTail = pVmaList->m_pPageTail->m_pNext; ++ pVmaList->m_pPageTail->m_used = 0; ++ pVmaList->m_pPageTail->m_pNext = 0; ++ } ++ ++// printk(KERN_DEBUG "adding page to list (%s %d)\n", current->comm, current->pid); ++ ++ pVmaList->m_pPageTail->m_pPages[pVmaList->m_pPageTail->m_used] = pVmf->page; ++ pVmaList->m_pPageTail->m_used++; ++ } ++ else ++ printk(KERN_ERR "returned page for vma we don\'t know %p (%s %d)\n", pVma, current->comm, current->pid); ++ ++ return 0; ++ } ++} ++ ++/****** GENERIC FUNCTIONS ******/ ++static int __init dmaer_init(void) ++{ ++ int result = alloc_chrdev_region(&g_majorMinor, 0, 1, "dmaer"); ++ if (result < 0) ++ { ++ printk(KERN_ERR "unable to get major device number\n"); ++ return result; ++ } ++ else ++ printk(KERN_DEBUG "major device number %d\n", MAJOR(g_majorMinor)); ++ ++ printk(KERN_DEBUG "vma list size %d, page list size %d, page size %ld\n", ++ sizeof(struct VmaPageList), sizeof(struct PageList), PAGE_SIZE); ++ ++ ++ //get a dma channel to work with ++ result = bcm_dma_chan_alloc(BCM_DMA_FEATURE_FAST, (void **)&g_pDmaChanBase, &g_dmaIrq); ++ //result = 0; ++ //g_pDmaChanBase = 0xce808000; ++ ++ if (result < 0) ++ { ++ printk(KERN_ERR "failed to allocate dma channel\n"); ++ cdev_del(&g_cDev); ++ unregister_chrdev_region(g_majorMinor, 1); ++ } ++ ++ //reset the channel ++ printk(KERN_DEBUG "allocated dma channel %d (%p), initial state %08x\n", result, g_pDmaChanBase, *g_pDmaChanBase); ++ *g_pDmaChanBase = 1 << 31; ++ printk(KERN_DEBUG "post-reset %08x\n", *g_pDmaChanBase); ++ ++ g_dmaChan = result; ++ ++ //clear the cache stats ++ g_cacheHit = 0; ++ g_cacheMiss = 0; ++ ++ //register our device - after this we are go go go ++ cdev_init(&g_cDev, &g_fOps); ++ g_cDev.owner = THIS_MODULE; ++ g_cDev.ops = &g_fOps; ++ ++ result = cdev_add(&g_cDev, g_majorMinor, 1); ++ if (result < 0) ++ { ++ printk(KERN_ERR "failed to add character device\n"); ++ unregister_chrdev_region(g_majorMinor, 1); ++ bcm_dma_chan_free(g_dmaChan); ++ return result; ++ } ++ ++ return 0; ++} ++ ++static void __exit dmaer_exit(void) ++{ ++ printk(KERN_INFO "closing dmaer device, cache stats: %d hits %d misses\n", g_cacheHit, g_cacheMiss); ++ //unregister the device ++ cdev_del(&g_cDev); ++ unregister_chrdev_region(g_majorMinor, 1); ++ //free the dma channel ++ bcm_dma_chan_free(g_dmaChan); ++} ++ ++MODULE_AUTHOR("Simon Hall"); ++module_init(dmaer_init); ++module_exit(dmaer_exit); ++ diff -Nru linux-3.2.46/debian/patches/rpi/rpi_285_4b61eadbaacaa6b64d8366df0bef41ec88adec1d.patch linux-3.2.46/debian/patches/rpi/rpi_285_4b61eadbaacaa6b64d8366df0bef41ec88adec1d.patch --- linux-3.2.46/debian/patches/rpi/rpi_285_4b61eadbaacaa6b64d8366df0bef41ec88adec1d.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_285_4b61eadbaacaa6b64d8366df0bef41ec88adec1d.patch 2013-07-26 19:37:40.000000000 +0000 @@ -0,0 +1,32 @@ +commit 4b61eadbaacaa6b64d8366df0bef41ec88adec1d +Author: popcornmix +Date: Mon Nov 19 19:28:22 2012 +0000 + + Enable DMA helper module and iSCSI modules + +Index: linux-3.2.46/arch/arm/configs/bcmrpi_defconfig +=================================================================== +--- linux-3.2.46.orig/arch/arm/configs/bcmrpi_defconfig 2013-07-26 19:37:35.000000000 +0000 ++++ linux-3.2.46/arch/arm/configs/bcmrpi_defconfig 2013-07-26 19:37:39.000000000 +0000 +@@ -31,10 +31,10 @@ + CONFIG_MODULE_UNLOAD=y + CONFIG_MODVERSIONS=y + CONFIG_MODULE_SRCVERSION_ALL=y +-# CONFIG_BLK_DEV_BSG is not set + CONFIG_BLK_DEV_THROTTLING=y + CONFIG_CFQ_GROUP_IOSCHED=y + CONFIG_ARCH_BCM2708=y ++CONFIG_BCM2708_DMAER=m + CONFIG_NO_HZ=y + CONFIG_HIGH_RES_TIMERS=y + CONFIG_PREEMPT=y +@@ -345,7 +345,8 @@ + CONFIG_CHR_DEV_OSST=m + CONFIG_BLK_DEV_SR=m + CONFIG_SCSI_MULTI_LUN=y +-# CONFIG_SCSI_LOWLEVEL is not set ++CONFIG_SCSI_ISCSI_ATTRS=y ++CONFIG_ISCSI_TCP=m + CONFIG_MD=y + CONFIG_BLK_DEV_DM=m + CONFIG_DM_CRYPT=m diff -Nru linux-3.2.46/debian/patches/rpi/rpi_286_00c4bfd2adebd7d856198540395aa9dd97be5d54.patch linux-3.2.46/debian/patches/rpi/rpi_286_00c4bfd2adebd7d856198540395aa9dd97be5d54.patch --- linux-3.2.46/debian/patches/rpi/rpi_286_00c4bfd2adebd7d856198540395aa9dd97be5d54.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_286_00c4bfd2adebd7d856198540395aa9dd97be5d54.patch 2013-07-26 19:37:41.000000000 +0000 @@ -0,0 +1,39 @@ +commit 00c4bfd2adebd7d856198540395aa9dd97be5d54 +Author: Steve Glendinning +Date: Thu Nov 8 06:26:21 2012 +0000 + + usbnet: ratelimit kevent may have been dropped warnings + + when something goes wrong, a flood of these messages can be + generated by usbnet (thousands per second). This doesn't + generally *help* the condition so this patch ratelimits the + rate of their generation. + + There's an underlying problem in usbnet's kevent deferral + mechanism which needs fixing, specifically that events *can* + get dropped and not handled. This patch doesn't address this, + but just mitigates fallout caused by the current implemention. + + Signed-off-by: Steve Glendinning + Signed-off-by: David S. Miller + +Index: linux-3.2.46/drivers/net/usb/usbnet.c +=================================================================== +--- linux-3.2.46.orig/drivers/net/usb/usbnet.c 2013-05-30 13:35:16.000000000 +0000 ++++ linux-3.2.46/drivers/net/usb/usbnet.c 2013-07-26 19:37:40.000000000 +0000 +@@ -325,10 +325,12 @@ + void usbnet_defer_kevent (struct usbnet *dev, int work) + { + set_bit (work, &dev->flags); +- if (!schedule_work (&dev->kevent)) +- netdev_err(dev->net, "kevent %d may have been dropped\n", work); +- else ++ if (!schedule_work (&dev->kevent)) { ++ if (net_ratelimit()) ++ netdev_err(dev->net, "kevent %d may have been dropped\n", work); ++ } else { + netdev_dbg(dev->net, "kevent %d scheduled\n", work); ++ } + } + EXPORT_SYMBOL_GPL(usbnet_defer_kevent); + diff -Nru linux-3.2.46/debian/patches/rpi/rpi_287_ada8b4415ff44d535d63e4291a0eca733bc2ad0f.patch linux-3.2.46/debian/patches/rpi/rpi_287_ada8b4415ff44d535d63e4291a0eca733bc2ad0f.patch --- linux-3.2.46/debian/patches/rpi/rpi_287_ada8b4415ff44d535d63e4291a0eca733bc2ad0f.patch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/patches/rpi/rpi_287_ada8b4415ff44d535d63e4291a0eca733bc2ad0f.patch 2013-07-26 19:37:43.000000000 +0000 @@ -0,0 +1,19 @@ +commit ada8b4415ff44d535d63e4291a0eca733bc2ad0f +Author: popcornmix +Date: Mon Nov 26 21:40:34 2012 +0000 + + Leave missing_status enabled for now. + +Index: linux-3.2.46/drivers/mmc/host/sdhci-bcm2708.c +=================================================================== +--- linux-3.2.46.orig/drivers/mmc/host/sdhci-bcm2708.c 2013-07-26 19:37:36.000000000 +0000 ++++ linux-3.2.46/drivers/mmc/host/sdhci-bcm2708.c 2013-07-26 19:37:42.000000000 +0000 +@@ -141,7 +141,7 @@ + static bool allow_highspeed = 1; + static int emmc_clock_freq = BCM2708_EMMC_CLOCK_FREQ; + static bool sync_after_dma = 1; +-static bool missing_status = 0; ++static bool missing_status = 1; + static bool spurious_crc_acmd51 = 0; + bool enable_llm = 1; + diff -Nru linux-3.2.46/debian/patches/series linux-3.2.46/debian/patches/series --- linux-3.2.46/debian/patches/series 2013-06-08 17:46:13.000000000 +0000 +++ linux-3.2.46/debian/patches/series 2013-07-26 19:16:40.000000000 +0000 @@ -655,3 +655,191 @@ bugfix/all/kbuild-Fix-missing-n-for-NEW-symbols-in-yes-make-old.patch bugfix/x86/viafb-autoload-on-olpc-xo1.5-only.patch bugfix/all/cifs-fix-potential-buffer-overrun-when-composing-a-new-options.patch +rpi/rpi_100_ec2ea6bacf5427a2cebac2aae4c359db286510c9.patch +rpi/rpi_101_031ee3ef3d0db7aa9b704650300e20f274b2047b.patch +rpi/rpi_102_7ff2699415531e8cc583921d5ee9b48f8df25b82.patch +rpi/rpi_103_c6f535332605987ba9391c92e22647351bc1f592.patch +rpi/rpi_104_2669f2ed70b39a30fe5a870b4ca0b04494805d60.patch +rpi/rpi_105_b102abd4d519186f3ed132242c896308e853c509.patch +rpi/rpi_106_2aa2155925a3989285a9cc0f804d57a2420bd28f.patch +rpi/rpi_107_92568ccbcfab09713e3748cd128b88d3313c346b.patch +rpi/rpi_108_637034a7c44631ea517b24f5bb2eab54b663fea9.patch +rpi/rpi_109_a9d4e49ac9ffdc8cef37485d72f894385486309a.patch +rpi/rpi_110_b3c82c8d884f1b1bd062d475d66eec965cd49625.patch +rpi/rpi_111_620c7805675cea7e398f8d210906685a09c27b1c.patch +rpi/rpi_112_4b461106c4c4d61682a1cc0d7dd200623e5649ec.patch +rpi/rpi_113_05dc3103a587232b58a0ba175a07a780ba8a3ac0.patch +rpi/rpi_114_bcf011fb144a3a90ed0aacc9042e7c548cb5edca.patch +rpi/rpi_115_da305c719abe61fb7e7a1ac8a6a3ae1b8633bf89.patch +rpi/rpi_116_c6b198bad4cbd38214a7604fbf71f7b915e30b8d.patch +rpi/rpi_117_59615740bc33035372330bad54fa4b88e4e94ef7.patch +rpi/rpi_118_8a93b2aa9309fe8495c17cc549c71827d6bd3dc3.patch +rpi/rpi_119_f7f1991dc6b5db3310d6fb2e310e69fad769b492.patch +rpi/rpi_120_e81b5a8e4b0cc9e9658562d598572aff538ae407.patch +rpi/rpi_121_2b4c39f7d2bb2d0b47ddd4c40250d54f1f3551aa.patch +rpi/rpi_122_6496fce7ba616b8d8bbada9deb5505e013cbb46d.patch +rpi/rpi_123_6a0c53faa0c37afbd224750ed4df073785fc5b04.patch +rpi/rpi_124_0294940099820f8a9169dd52a3c807436db2fc35.patch +rpi/rpi_125_8816606c25ea723e67efd182d9efe538db519557.patch +rpi/rpi_126_c5d6cb6ab072e555d8747056a1d44156cded3b31.patch +rpi/rpi_127_369b60fd9ad144b91503c915d4952ee73cc01b91.patch +rpi/rpi_128_2456b9f1f160f9e67ba140beab23494cb03afcf5.patch +rpi/rpi_129_7cb77d373f70f28b5b1ee9eb9746ee99a6c52715.patch +rpi/rpi_130_4fc04b92fcafa7c8719e8f3c4f9fe5771dc78287.patch +rpi/rpi_131_7487b3f7f684e829ad3e9eb1b835ac937ad63690.patch +rpi/rpi_132_0cc4514a13187219f561aaba71a88edb65a7fbf4.patch +rpi/rpi_133_06009f05c407b1b5333c9bec4fb390b440f36a16.patch +rpi/rpi_134_2c9450dceac031d05daa8b5dc292a1b1f775c767.patch +rpi/rpi_135_c86a03f8e6a874735feeead31385686ef66fdf14.patch +rpi/rpi_136_3352a69ac1bcc36c689c7908b3a5cd4613354984.patch +rpi/rpi_137_f8c99b57a05b626bf706edddf61f86c89232b213.patch +rpi/rpi_138_0c184a6618f4817030af0bbfdc7d55911e2b14ed.patch +rpi/rpi_139_e9382f7c0690b2ae17972c64c2cecaca6a1ec87d.patch +rpi/rpi_140_dc0b877bf55f4d3a969015101d3bf9e738c4f0a9.patch +rpi/rpi_141_4b0ecd93e82e32453b25fec1dc59bcedfd2958fd.patch +rpi/rpi_142_b4f35d9f2a6284e8075bd1c6020a1bc55a8a7975.patch +rpi/rpi_143_bd396799fb1289cb7acd59762ac6431bd3fec0ad.patch +rpi/rpi_144_45dced6ad22bee4458b53c3ff7d3d79a4368bdcf.patch +rpi/rpi_145_2d05297654e1c0e119deeb365585df4e904bcfe3.patch +rpi/rpi_146_21e287c2206a7a43c1546c8bb5abf0a7ced3dd5e.patch +rpi/rpi_147_06cd09122641b2cc97bd56b8c22bd70905caceff.patch +rpi/rpi_148_b7d47f6a347c56d20a75343e71ce5bda75e035d7.patch +rpi/rpi_149_cb17d60512da813af29a0315585caf32f19d3c77.patch +rpi/rpi_150_025a245c362b4ad3d8ca8b93512464d94247a182.patch +rpi/rpi_151_9c7a53428ac1ec88d250a0fd284e372e50b2b45d.patch +rpi/rpi_152_69020137b6172a263b77b98f4509293cfb9a202f.patch +rpi/rpi_153_999b9c7a9cb1d7cbb8b4407ddfa33a2a39ee09b2.patch +rpi/rpi_154_eec485b89354fcfd8acb2f6c9943aad5496b467c.patch +rpi/rpi_155_0d390569262bfc90538ea3d3454916f866f06071.patch +rpi/rpi_156_48b347a6fe008dab487fb54327ed602a88602d7e.patch +rpi/rpi_157_8390fb8da8954332f546508e6d51906cb93c6e70.patch +rpi/rpi_158_6ab6d02f9aaf7b35d941969a1ec8a7aff582ef2f.patch +rpi/rpi_159_8f82daa37d8734496e94a6a5c5ead20254abaa84.patch +rpi/rpi_160_d7156c5567a90e0fe4d3a503968968d32b7ededd.patch +rpi/rpi_161_70b125d750757b0ba3c2853268b8f8dbac1a5192.patch +rpi/rpi_162_84042ac41b3492df487acd35de058de1656d2a2a.patch +rpi/rpi_163_d7afba1425d968e0675434215f04b3fac0213dec.patch +rpi/rpi_164_d34d49ef34fee0adae557b960bee4737220588be.patch +rpi/rpi_165_63aa16776175617687923466aae543b2528d4600.patch +rpi/rpi_166_c5592fc5ae6c0b26e327809d0f572093284c2956.patch +rpi/rpi_167_fe2e727883a371f21e02454ad6b58eed407aa7b9.patch +rpi/rpi_168_02b4b932b8119d0fb68d83873967497e050fb960.patch +rpi/rpi_169_6dac22fdd8f0a510aa1c1a007eac118d99d86a3f.patch +rpi/rpi_170_2415c98cf5c0ab0521621e6759432e04f2891619.patch +rpi/rpi_171_f1da243c55dd220600f56899b770c25b77d572a6.patch +rpi/rpi_172_8f32eb69851e137c04e225cc3fab42a89566d7f0.patch +rpi/rpi_173_8544300faae04c4fb4e3e1acc5ff9a9733f1acce.patch +rpi/rpi_174_973ebad9feb981465994f88448d2fb25d9bee941.patch +rpi/rpi_175_2f3523e91e1cdbfbb5871f0943333620b139e032.patch +rpi/rpi_176_887af3c7add637e26c39bccc9156a65260721d69.patch +rpi/rpi_177_8825835abbe587ef23e2eb64114ce67dfd391c44.patch +rpi/rpi_178_56afa5ae9400b1948da1fd28b3f54787b13fa555.patch +rpi/rpi_179_13d7000c574bdc16681c01b23a79169984ecfe9e.patch +rpi/rpi_180_105858e4506975bfb3e293f2e815d14eae40958c.patch +rpi/rpi_181_269b48f50f4fd07067c9b47c557c20e524cbca71.patch +rpi/rpi_182_6ba3db85388405df0b71da744943a7129827491f.patch +rpi/rpi_183_d32ab7b3e6d8c203543750dbc5c76980baaa17c3.patch +rpi/rpi_184_4c1987976a7498bf12bbf9840f9199af03a08993.patch +rpi/rpi_185_61923058dee45d1da0d90fe1c1a7848ba72dab81.patch +rpi/rpi_186_f9b5246fd33f96fe2a31dbd74dce8d6da7df0fbc.patch +rpi/rpi_187_b3df416a54a7892e80f65d80b0c14dc7514bf26d.patch +rpi/rpi_188_005ab728605baa7dc15c7050644cc4163642f9ad.patch +rpi/rpi_189_56c44908b2860bb551aaf532c232bcc63d4e584d.patch +rpi/rpi_190_0bf26691a6ba1d82581f03508f3836f16d6df0bf.patch +rpi/rpi_191_b7f136eba5ca61d42fbdd71e184cfadc4e87f9a3.patch +rpi/rpi_192_e76b20accf3be6b4ddd63dee9313771bdd8ff4b1.patch +rpi/rpi_193_44987f59e8aa873338071637dea24ef125e329a9.patch +rpi/rpi_194_1ad0baa517925ef794728f8446b9e63b34b1a9d1.patch +rpi/rpi_195_622a46ff94cc76cb4557dabb65c6752e32c0f11f.patch +rpi/rpi_196_f193e284f60382b90584520ab6787a4652626eaa.patch +rpi/rpi_197_93afe723635802e875da48e526c754c13860d537.patch +rpi/rpi_198_5f77a992eedc7ad8254195c9becbaccf112e592f.patch +rpi/rpi_199_2674477a4805b63b695e012b2c653869ae08302b.patch +rpi/rpi_200_ac15023c8b298c38d8def9c1ca3b21bed9fd9238.patch +rpi/rpi_201_89816b2638f7232913df85499592d1422e0fb453.patch +rpi/rpi_202_7a681f9eb4fa7484956ea347e2c35f12d151aba4.patch +rpi/rpi_203_11fd94ce307965b3ae9574343059fb5c2ffbfc65.patch +rpi/rpi_204_1574e957d51afddc59ae0912e41b57320dedc0c9.patch +rpi/rpi_205_04e71eb30083d387cdaabb046bedb3174999f7cd.patch +rpi/rpi_206_3a475430169654ef1beaf475d122ade24433ae16.patch +rpi/rpi_207_31c350f3e5f77dfd7b36d7428420c545a255a1cc.patch +rpi/rpi_208_147779ede8bf936e37b6337458d531d5738c5a06.patch +rpi/rpi_209_adebc4f82e2fcb7268e7e14f576648fcf6921217.patch +rpi/rpi_210_2c671b98f0d33b8416a55c50f8057a4067484bb0.patch +rpi/rpi_211_4cdeb7b0ca4bb80b68057108cf747a4a642e47b6.patch +rpi/rpi_212_7880df43b92e1a99acf14ac421b4a233a1a687ec.patch +rpi/rpi_213_f599001496e2bbacd54e11fb9fbabda694d308f2.patch +rpi/rpi_214_5cc98c1e75700e51e4a31d8a05b4a55a7d29648c.patch +rpi/rpi_215_0872b20fbea2377c6286c39cbc60d3bd83a814aa.patch +rpi/rpi_216_d6911d65886f2db4d0966879102e13c130ec8515.patch +rpi/rpi_217_d52d21b77c3e120afde1c7c298307ce176e21a94.patch +rpi/rpi_218_e5c8bb0e76069d9afefcc9d96d8faca384cc67d2.patch +rpi/rpi_219_d47734bbc53386d08c6a5a6a5bc4219e881cc778.patch +rpi/rpi_220_cbc60c791cb6fafea5ddae0d8429ac0923237128.patch +rpi/rpi_221_4a0a5565a02b84d1061bc3dccc5384b4b6829851.patch +rpi/rpi_222_b1eebb494f955fe2a772394b17720386460f60ba.patch +rpi/rpi_223_ddebe4dc47bf1d6e95cb478ce3d4a72a99a4e677.patch +rpi/rpi_224_e6b8622bffcc4823913f491b40904a7f27710569.patch +rpi/rpi_225_2b039107863998de874b555a9e5af921792370e5.patch +rpi/rpi_226_091073bcab483b976ee33dfe914c28df87914a3b.patch +rpi/rpi_227_a915a4f6e8969a599627ca6b3e2cd7714608d222.patch +rpi/rpi_228_5412f282ae16b8872e0da31b576122d5b3440228.patch +rpi/rpi_229_afe58ac9e71636ff2f46e231c9d5fcd615ef933d.patch +rpi/rpi_230_e886b451281bfd198e36078048d8775b8c8ef5c9.patch +rpi/rpi_231_307d9fbb18900c17bc9deeb4020c5ed599053947.patch +rpi/rpi_232_c1e6924f2ddb697ecf4157ce53e850a38439aa79.patch +rpi/rpi_233_46d14862c3e91a866883c93be8c6c78ffd149439.patch +rpi/rpi_234_70428950df6af8fb89531dd970d0bca03a36fc1b.patch +rpi/rpi_235_1259e0ca243421307b9eb6eb45baca90abfb90a7.patch +rpi/rpi_236_906508b90bc237cd73d5c3237f20d582d44b8fa7.patch +rpi/rpi_237_1625539436b4965c445fff708eb28d3d55af7685.patch +rpi/rpi_238_78f82bc5324ac5032d33c4b718982e32e7c76c6b.patch +rpi/rpi_239_202a7792fbdf8763e8c50805b2bc15f007484f04.patch +rpi/rpi_240_55549f3998e7f8196dd6401933d895823a026ce5.patch +rpi/rpi_241_adae199d13754b7c0e61c14eac2a92a3a3f6afc1.patch +rpi/rpi_242_fe1a4d0713cdcccd7f13b0df552f0bd65281d15d.patch +rpi/rpi_243_87d5bc10fb0876be295314213ef4478a94c0e7bb.patch +rpi/rpi_244_c8edb2381f299d9cc56ce99234f4e8d7061be3b2.patch +rpi/rpi_245_e33263e7eab2d05349b438f6a4a8d1924686a824.patch +rpi/rpi_246_ce4ab6222b47270b1597ce3cd7c0a354346d348d.patch +rpi/rpi_247_d8a00ed27f71d12d5ba02d18f53c8834e5b2b319.patch +rpi/rpi_248_807223a562933b1906c70f1c5249db7635dd4574.patch +rpi/rpi_249_0875260c9a74e5b46a1a5052dd8472cfec8d1d22.patch +rpi/rpi_250_2be55e6cc980ce2473052f071902b7379b7344b9.patch +rpi/rpi_251_965b922076edccc530bd2a05e2fbabc1dd8b06a8.patch +rpi/rpi_252_c14ddd05972ac5aa822a9e9f487cf2c4a1b958a0.patch +rpi/rpi_253_9245b4c35b99b3870e1f7dc598c5692b3c66a6f0.patch +rpi/rpi_254_358395ed00fbb2854c0b7d6166888f3aff524ca4.patch +rpi/rpi_255_118e2d362a8dd0c1e6e4f5c4694ba193f77092ce.patch +rpi/rpi_256_2843e37f77f0b01001f5659906166c92ba3801d0.patch +rpi/rpi_257_eb0c5608f3fd94fa316135e71edfb2d359b73203.patch +rpi/rpi_258_a542809e00a8e14984866a73547e0f1efcce57c3.patch +rpi/rpi_259_63bbe8a30dadec5dc1c0bd59e93ae3b83b931d14.patch +rpi/rpi_260_22cb6e26206c3e0e7bfb8e2adf86e9b10f9187a6.patch +rpi/rpi_261_8bccc7a0340404cc14f831dd9c06d3528b5ebcff.patch +rpi/rpi_262_7aa8d823bd9feb758c2e0755d7d3589481bf6b36.patch +rpi/rpi_263_3cb5f1d392bef25dd965b71ca881f4c50beec59c.patch +rpi/rpi_264_d14d37193873888b207a992abe4a5848a5023ff6.patch +rpi/rpi_265_fb241d04df64152a6d85d16b47ad978d8015a61c.patch +rpi/rpi_266_6a84a910cb0564a3581ee7764bb255126657c4cb.patch +rpi/rpi_267_91f1cdccb0b70e2bed1ab68a237ba1629c5af5f8.patch +rpi/rpi_268_10182a3bc434b27740f81c2b836a1af943060241.patch +rpi/rpi_269_42a864b123a47542aa0db530e0f4fe10851faaf2.patch +rpi/rpi_270_fc155d9d85bfc936a9c04798ffa04fa7dc73ca3b.patch +rpi/rpi_271_df41b42914892c539de4ec16a6d9184d031ae0bf.patch +rpi/rpi_272_91abd8700cc73dff72332135c4bdf4cdf7afe2b1.patch +rpi/rpi_273_036c94eeefd3abf93cc18ff0fdf689fce00df59b.patch +rpi/rpi_274_ac7c9291f72c6f54a3afb6268c312b106b07d525.patch +rpi/rpi_275_00b8a332c633a6ee52994672ea2558d1f8199fa9.patch +rpi/rpi_276_a01b0af50cd95d5254ff3450e59477a707bede22.patch +rpi/rpi_277_15c02e28bb98b7b40e898ec0d72bc86b2e263498.patch +rpi/rpi_278_a6555c21fded3da6784456c10d4971a3b68aa21f.patch +rpi/rpi_279_efdb0b084f8188babe4c8b1f169c4acbd4f618fa.patch +rpi/rpi_280_70b722a642e607891e302195ad970d39f30325e5.patch +rpi/rpi_281_59b43cdfbaf44e701761891dcf77cf40969232a4.patch +rpi/rpi_282_6f2064cb6807ac4a4d9edf258424db99f41b4f2b.patch +rpi/rpi_283_22e8df63d48443cb7fc4feb2762fdf17200f955c.patch +rpi/rpi_284_71f3b547b9b54dc33604909090d0b44ec6abbb67.patch +rpi/rpi_285_4b61eadbaacaa6b64d8366df0bef41ec88adec1d.patch +rpi/rpi_286_00c4bfd2adebd7d856198540395aa9dd97be5d54.patch +rpi/rpi_287_ada8b4415ff44d535d63e4291a0eca733bc2ad0f.patch diff -Nru linux-3.2.46/debian/patches/series-rt linux-3.2.46/debian/patches/series-rt --- linux-3.2.46/debian/patches/series-rt 2013-06-08 17:33:45.000000000 +0000 +++ linux-3.2.46/debian/patches/series-rt 2013-07-26 18:03:40.000000000 +0000 @@ -69,7 +69,7 @@ features/all/rt/0069-wait-Provide-__wake_up_all_locked.patch features/all/rt/0070-pci-Use-__wake_up_all_locked-pci_unblock_user_cfg_ac.patch features/all/rt/0071-latency-hist.patch.patch -features/all/rt/0072-hwlatdetect.patch.patch +#features/all/rt/0072-hwlatdetect.patch.patch features/all/rt/0073-localversion.patch.patch features/all/rt/0074-early-printk-consolidate.patch.patch features/all/rt/0075-printk-kill.patch.patch diff -Nru linux-3.2.46/debian/rpi-branch linux-3.2.46/debian/rpi-branch --- linux-3.2.46/debian/rpi-branch 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/rpi-branch 2013-07-26 19:08:08.000000000 +0000 @@ -0,0 +1,19 @@ +commit ada8b4415ff44d535d63e4291a0eca733bc2ad0f +Author: popcornmix +Date: Mon Nov 26 21:40:34 2012 +0000 + + Leave missing_status enabled for now. + +diff --git a/drivers/mmc/host/sdhci-bcm2708.c b/drivers/mmc/host/sdhci-bcm2708.c +index 861b0f4..4d6c616 100644 +--- a/drivers/mmc/host/sdhci-bcm2708.c ++++ b/drivers/mmc/host/sdhci-bcm2708.c +@@ -141,7 +141,7 @@ static inline unsigned long int since_ns(hptime_t t) + static bool allow_highspeed = 1; + static int emmc_clock_freq = BCM2708_EMMC_CLOCK_FREQ; + static bool sync_after_dma = 1; +-static bool missing_status = 0; ++static bool missing_status = 1; + static bool spurious_crc_acmd51 = 0; + bool enable_llm = 1; + diff -Nru linux-3.2.46/debian/rules.gen linux-3.2.46/debian/rules.gen --- linux-3.2.46/debian/rules.gen 2013-06-08 21:44:19.000000000 +0000 +++ linux-3.2.46/debian/rules.gen 2013-07-26 21:15:07.000000000 +0000 @@ -4,561 +4,549 @@ binary-arch_alpha_none: binary-arch_alpha_none_alpha-generic binary-arch_alpha_none_alpha-legacy binary-arch_alpha_none_alpha-smp binary-arch_alpha_none_real binary-arch_alpha_none_alpha-generic: binary-arch_alpha_none_alpha-generic_real binary-arch_alpha_none_alpha-generic_real:: - $(MAKE) -f debian/rules.real binary-arch-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='alpha' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='alpha-generic' KCONFIG='debian/config/config debian/config/alpha/config debian/config/alpha/config.alpha-generic' KERNEL_ARCH='alpha' LOCALVERSION='-alpha-generic' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-alpha-generic' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real binary-arch-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='alpha' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='alpha-generic' KCONFIG='debian/config/config debian/config/alpha/config debian/config/alpha/config.alpha-generic' KERNEL_ARCH='alpha' LOCALVERSION='-alpha-generic' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-alpha-generic' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' binary-arch_alpha_none_alpha-legacy: binary-arch_alpha_none_alpha-legacy_real binary-arch_alpha_none_alpha-legacy_real:: - $(MAKE) -f debian/rules.real binary-arch-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='alpha' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='alpha-legacy' KCONFIG='debian/config/config debian/config/alpha/config debian/config/alpha/config.alpha-legacy' KERNEL_ARCH='alpha' LOCALVERSION='-alpha-legacy' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-alpha-legacy' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real binary-arch-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='alpha' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='alpha-legacy' KCONFIG='debian/config/config debian/config/alpha/config debian/config/alpha/config.alpha-legacy' KERNEL_ARCH='alpha' LOCALVERSION='-alpha-legacy' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-alpha-legacy' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' binary-arch_alpha_none_alpha-smp: binary-arch_alpha_none_alpha-smp_real binary-arch_alpha_none_alpha-smp_real:: - $(MAKE) -f debian/rules.real binary-arch-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='alpha' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='alpha-smp' KCONFIG='debian/config/config debian/config/alpha/config debian/config/alpha/config.alpha-smp' KERNEL_ARCH='alpha' LOCALVERSION='-alpha-smp' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-alpha-smp' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real binary-arch-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='alpha' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='alpha-smp' KCONFIG='debian/config/config debian/config/alpha/config debian/config/alpha/config.alpha-smp' KERNEL_ARCH='alpha' LOCALVERSION='-alpha-smp' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-alpha-smp' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' binary-arch_alpha_none_real:: - $(MAKE) -f debian/rules.real binary-arch-featureset ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='alpha' FEATURESET='none' KERNEL_ARCH='alpha' LOCALVERSION_HEADERS='' SOURCEVERSION='3.2.46-1' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real binary-arch-featureset ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='alpha' FEATURESET='none' KERNEL_ARCH='alpha' LOCALVERSION_HEADERS='' SOURCEVERSION='3.2.46-1+rpi1' UPSTREAMVERSION='3.2' VERSION='3.2' binary-arch_alpha_real:: - $(MAKE) -f debian/rules.real binary-arch-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='alpha' KERNEL_ARCH='alpha' SOURCEVERSION='3.2.46-1' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real binary-arch-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='alpha' KERNEL_ARCH='alpha' SOURCEVERSION='3.2.46-1+rpi1' UPSTREAMVERSION='3.2' VERSION='3.2' binary-arch_amd64:: binary-arch_amd64_none binary-arch_amd64_real binary-arch_amd64_rt binary-arch_amd64:: - $(MAKE) -f debian/rules.real install-udeb_amd64 ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='amd64' KERNEL_ARCH='x86' SOURCEVERSION='3.2.46-1' UPSTREAMVERSION='3.2' VERSION='3.2' PACKAGE_NAMES='kernel-image-3.2.0-4-amd64-di nic-modules-3.2.0-4-amd64-di nic-extra-modules-3.2.0-4-amd64-di nic-wireless-modules-3.2.0-4-amd64-di nic-shared-modules-3.2.0-4-amd64-di serial-modules-3.2.0-4-amd64-di usb-serial-modules-3.2.0-4-amd64-di ppp-modules-3.2.0-4-amd64-di pata-modules-3.2.0-4-amd64-di cdrom-core-modules-3.2.0-4-amd64-di firewire-core-modules-3.2.0-4-amd64-di scsi-core-modules-3.2.0-4-amd64-di scsi-modules-3.2.0-4-amd64-di scsi-common-modules-3.2.0-4-amd64-di scsi-extra-modules-3.2.0-4-amd64-di plip-modules-3.2.0-4-amd64-di floppy-modules-3.2.0-4-amd64-di loop-modules-3.2.0-4-amd64-di btrfs-modules-3.2.0-4-amd64-di ext2-modules-3.2.0-4-amd64-di ext3-modules-3.2.0-4-amd64-di ext4-modules-3.2.0-4-amd64-di isofs-modules-3.2.0-4-amd64-di jfs-modules-3.2.0-4-amd64-di ntfs-modules-3.2.0-4-amd64-di reiserfs-modules-3.2.0-4-amd64-di xfs-modules-3.2.0-4-amd64-di fat-modules-3.2.0-4-amd64-di ufs-modules-3.2.0-4-amd64-di qnx4-modules-3.2.0-4-amd64-di md-modules-3.2.0-4-amd64-di multipath-modules-3.2.0-4-amd64-di usb-modules-3.2.0-4-amd64-di usb-storage-modules-3.2.0-4-amd64-di pcmcia-storage-modules-3.2.0-4-amd64-di fb-modules-3.2.0-4-amd64-di input-modules-3.2.0-4-amd64-di event-modules-3.2.0-4-amd64-di mouse-modules-3.2.0-4-amd64-di irda-modules-3.2.0-4-amd64-di parport-modules-3.2.0-4-amd64-di nic-pcmcia-modules-3.2.0-4-amd64-di pcmcia-modules-3.2.0-4-amd64-di nic-usb-modules-3.2.0-4-amd64-di sata-modules-3.2.0-4-amd64-di core-modules-3.2.0-4-amd64-di acpi-modules-3.2.0-4-amd64-di i2c-modules-3.2.0-4-amd64-di crc-modules-3.2.0-4-amd64-di crypto-modules-3.2.0-4-amd64-di crypto-dm-modules-3.2.0-4-amd64-di efi-modules-3.2.0-4-amd64-di ata-modules-3.2.0-4-amd64-di mmc-core-modules-3.2.0-4-amd64-di mmc-modules-3.2.0-4-amd64-di nbd-modules-3.2.0-4-amd64-di squashfs-modules-3.2.0-4-amd64-di speakup-modules-3.2.0-4-amd64-di virtio-modules-3.2.0-4-amd64-di uinput-modules-3.2.0-4-amd64-di sound-modules-3.2.0-4-amd64-di zlib-modules-3.2.0-4-amd64-di hyperv-modules-3.2.0-4-amd64-di udf-modules-3.2.0-4-amd64-di fuse-modules-3.2.0-4-amd64-di' + $(MAKE) -f debian/rules.real install-udeb_amd64 ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='amd64' KERNEL_ARCH='x86' SOURCEVERSION='3.2.46-1+rpi1' UPSTREAMVERSION='3.2' VERSION='3.2' PACKAGE_NAMES='kernel-image-3.2.0-4-amd64-di nic-modules-3.2.0-4-amd64-di nic-extra-modules-3.2.0-4-amd64-di nic-wireless-modules-3.2.0-4-amd64-di nic-shared-modules-3.2.0-4-amd64-di serial-modules-3.2.0-4-amd64-di usb-serial-modules-3.2.0-4-amd64-di ppp-modules-3.2.0-4-amd64-di pata-modules-3.2.0-4-amd64-di cdrom-core-modules-3.2.0-4-amd64-di firewire-core-modules-3.2.0-4-amd64-di scsi-core-modules-3.2.0-4-amd64-di scsi-modules-3.2.0-4-amd64-di scsi-common-modules-3.2.0-4-amd64-di scsi-extra-modules-3.2.0-4-amd64-di plip-modules-3.2.0-4-amd64-di floppy-modules-3.2.0-4-amd64-di loop-modules-3.2.0-4-amd64-di btrfs-modules-3.2.0-4-amd64-di ext2-modules-3.2.0-4-amd64-di ext3-modules-3.2.0-4-amd64-di ext4-modules-3.2.0-4-amd64-di isofs-modules-3.2.0-4-amd64-di jfs-modules-3.2.0-4-amd64-di ntfs-modules-3.2.0-4-amd64-di reiserfs-modules-3.2.0-4-amd64-di xfs-modules-3.2.0-4-amd64-di fat-modules-3.2.0-4-amd64-di ufs-modules-3.2.0-4-amd64-di qnx4-modules-3.2.0-4-amd64-di md-modules-3.2.0-4-amd64-di multipath-modules-3.2.0-4-amd64-di usb-modules-3.2.0-4-amd64-di usb-storage-modules-3.2.0-4-amd64-di pcmcia-storage-modules-3.2.0-4-amd64-di fb-modules-3.2.0-4-amd64-di input-modules-3.2.0-4-amd64-di event-modules-3.2.0-4-amd64-di mouse-modules-3.2.0-4-amd64-di irda-modules-3.2.0-4-amd64-di parport-modules-3.2.0-4-amd64-di nic-pcmcia-modules-3.2.0-4-amd64-di pcmcia-modules-3.2.0-4-amd64-di nic-usb-modules-3.2.0-4-amd64-di sata-modules-3.2.0-4-amd64-di core-modules-3.2.0-4-amd64-di acpi-modules-3.2.0-4-amd64-di i2c-modules-3.2.0-4-amd64-di crc-modules-3.2.0-4-amd64-di crypto-modules-3.2.0-4-amd64-di crypto-dm-modules-3.2.0-4-amd64-di efi-modules-3.2.0-4-amd64-di ata-modules-3.2.0-4-amd64-di mmc-core-modules-3.2.0-4-amd64-di mmc-modules-3.2.0-4-amd64-di nbd-modules-3.2.0-4-amd64-di squashfs-modules-3.2.0-4-amd64-di speakup-modules-3.2.0-4-amd64-di virtio-modules-3.2.0-4-amd64-di uinput-modules-3.2.0-4-amd64-di sound-modules-3.2.0-4-amd64-di zlib-modules-3.2.0-4-amd64-di hyperv-modules-3.2.0-4-amd64-di udf-modules-3.2.0-4-amd64-di fuse-modules-3.2.0-4-amd64-di' binary-arch_amd64_none: binary-arch_amd64_none_amd64 binary-arch_amd64_none_real binary-arch_amd64_none_amd64: binary-arch_amd64_none_amd64_real binary-arch_amd64_none_amd64_real:: - $(MAKE) -f debian/rules.real binary-arch-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='amd64' COMPILER='gcc-4.6' DEBUG='True' FEATURESET='none' FLAVOUR='amd64' KCONFIG='debian/config/config debian/config/kernelarch-x86/config debian/config/kernelarch-x86/config-arch-64' KCONFIG_OPTIONS='-o DEBUG_INFO=y' KERNEL_ARCH='x86' LOCALVERSION='-amd64' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-amd64' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' - $(MAKE) -f debian/rules.real install-dummy DH_OPTIONS='-pxen-linux-system-3.2.0-4-amd64' ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='amd64' COMPILER='gcc-4.6' DEBUG='True' FEATURESET='none' FLAVOUR='amd64' KCONFIG='debian/config/config debian/config/kernelarch-x86/config debian/config/kernelarch-x86/config-arch-64' KCONFIG_OPTIONS='-o DEBUG_INFO=y' KERNEL_ARCH='x86' LOCALVERSION='-amd64' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-amd64' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real binary-arch-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='amd64' COMPILER='gcc-4.6' DEBUG='True' FEATURESET='none' FLAVOUR='amd64' KCONFIG='debian/config/config debian/config/kernelarch-x86/config debian/config/kernelarch-x86/config-arch-64' KCONFIG_OPTIONS='-o DEBUG_INFO=y' KERNEL_ARCH='x86' LOCALVERSION='-amd64' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-amd64' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real install-dummy DH_OPTIONS='-pxen-linux-system-3.2.0-4-amd64' ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='amd64' COMPILER='gcc-4.6' DEBUG='True' FEATURESET='none' FLAVOUR='amd64' KCONFIG='debian/config/config debian/config/kernelarch-x86/config debian/config/kernelarch-x86/config-arch-64' KCONFIG_OPTIONS='-o DEBUG_INFO=y' KERNEL_ARCH='x86' LOCALVERSION='-amd64' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-amd64' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' binary-arch_amd64_none_real:: - $(MAKE) -f debian/rules.real binary-arch-featureset ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='amd64' FEATURESET='none' KERNEL_ARCH='x86' LOCALVERSION_HEADERS='' SOURCEVERSION='3.2.46-1' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real binary-arch-featureset ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='amd64' FEATURESET='none' KERNEL_ARCH='x86' LOCALVERSION_HEADERS='' SOURCEVERSION='3.2.46-1+rpi1' UPSTREAMVERSION='3.2' VERSION='3.2' binary-arch_amd64_real:: - $(MAKE) -f debian/rules.real binary-arch-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='amd64' KERNEL_ARCH='x86' SOURCEVERSION='3.2.46-1' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real binary-arch-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='amd64' KERNEL_ARCH='x86' SOURCEVERSION='3.2.46-1+rpi1' UPSTREAMVERSION='3.2' VERSION='3.2' binary-arch_amd64_rt: binary-arch_amd64_rt_amd64 binary-arch_amd64_rt_real binary-arch_amd64_rt_amd64: binary-arch_amd64_rt_amd64_real binary-arch_amd64_rt_amd64_real:: - $(MAKE) -f debian/rules.real binary-arch-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='amd64' COMPILER='gcc-4.6' DEBUG='True' FEATURESET='rt' FLAVOUR='amd64' KCONFIG='debian/config/config debian/config/kernelarch-x86/config debian/config/kernelarch-x86/config-arch-64 debian/config/featureset-rt/config' KCONFIG_OPTIONS='-o DEBUG_INFO=y' KERNEL_ARCH='x86' LOCALVERSION='-rt-amd64' LOCALVERSION_HEADERS='-rt' LOCALVERSION_IMAGE='-rt-amd64' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real binary-arch-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='amd64' COMPILER='gcc-4.6' DEBUG='True' FEATURESET='rt' FLAVOUR='amd64' KCONFIG='debian/config/config debian/config/kernelarch-x86/config debian/config/kernelarch-x86/config-arch-64 debian/config/featureset-rt/config' KCONFIG_OPTIONS='-o DEBUG_INFO=y' KERNEL_ARCH='x86' LOCALVERSION='-rt-amd64' LOCALVERSION_HEADERS='-rt' LOCALVERSION_IMAGE='-rt-amd64' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' binary-arch_amd64_rt_real:: - $(MAKE) -f debian/rules.real binary-arch-featureset ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='amd64' FEATURESET='rt' KERNEL_ARCH='x86' LOCALVERSION_HEADERS='-rt' SOURCEVERSION='3.2.46-1' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real binary-arch-featureset ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='amd64' FEATURESET='rt' KERNEL_ARCH='x86' LOCALVERSION_HEADERS='-rt' SOURCEVERSION='3.2.46-1+rpi1' UPSTREAMVERSION='3.2' VERSION='3.2' binary-arch_armel:: binary-arch_armel_none binary-arch_armel_real binary-arch_armel:: - $(MAKE) -f debian/rules.real install-udeb_armel ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='armel' KERNEL_ARCH='arm' SOURCEVERSION='3.2.46-1' UPSTREAMVERSION='3.2' VERSION='3.2' PACKAGE_NAMES='kernel-image-3.2.0-4-iop32x-di nic-modules-3.2.0-4-iop32x-di nic-shared-modules-3.2.0-4-iop32x-di usb-serial-modules-3.2.0-4-iop32x-di ppp-modules-3.2.0-4-iop32x-di pata-modules-3.2.0-4-iop32x-di cdrom-core-modules-3.2.0-4-iop32x-di scsi-core-modules-3.2.0-4-iop32x-di loop-modules-3.2.0-4-iop32x-di ipv6-modules-3.2.0-4-iop32x-di btrfs-modules-3.2.0-4-iop32x-di ext2-modules-3.2.0-4-iop32x-di ext3-modules-3.2.0-4-iop32x-di ext4-modules-3.2.0-4-iop32x-di isofs-modules-3.2.0-4-iop32x-di jffs2-modules-3.2.0-4-iop32x-di jfs-modules-3.2.0-4-iop32x-di reiserfs-modules-3.2.0-4-iop32x-di fat-modules-3.2.0-4-iop32x-di md-modules-3.2.0-4-iop32x-di multipath-modules-3.2.0-4-iop32x-di usb-modules-3.2.0-4-iop32x-di usb-storage-modules-3.2.0-4-iop32x-di event-modules-3.2.0-4-iop32x-di nic-usb-modules-3.2.0-4-iop32x-di sata-modules-3.2.0-4-iop32x-di core-modules-3.2.0-4-iop32x-di crc-modules-3.2.0-4-iop32x-di crypto-modules-3.2.0-4-iop32x-di crypto-dm-modules-3.2.0-4-iop32x-di ata-modules-3.2.0-4-iop32x-di nbd-modules-3.2.0-4-iop32x-di squashfs-modules-3.2.0-4-iop32x-di zlib-modules-3.2.0-4-iop32x-di udf-modules-3.2.0-4-iop32x-di fuse-modules-3.2.0-4-iop32x-di kernel-image-3.2.0-4-kirkwood-di nic-modules-3.2.0-4-kirkwood-di nic-shared-modules-3.2.0-4-kirkwood-di usb-serial-modules-3.2.0-4-kirkwood-di ppp-modules-3.2.0-4-kirkwood-di cdrom-core-modules-3.2.0-4-kirkwood-di scsi-core-modules-3.2.0-4-kirkwood-di loop-modules-3.2.0-4-kirkwood-di ipv6-modules-3.2.0-4-kirkwood-di btrfs-modules-3.2.0-4-kirkwood-di ext2-modules-3.2.0-4-kirkwood-di ext3-modules-3.2.0-4-kirkwood-di ext4-modules-3.2.0-4-kirkwood-di isofs-modules-3.2.0-4-kirkwood-di jfs-modules-3.2.0-4-kirkwood-di reiserfs-modules-3.2.0-4-kirkwood-di fat-modules-3.2.0-4-kirkwood-di minix-modules-3.2.0-4-kirkwood-di md-modules-3.2.0-4-kirkwood-di multipath-modules-3.2.0-4-kirkwood-di usb-modules-3.2.0-4-kirkwood-di usb-storage-modules-3.2.0-4-kirkwood-di fb-modules-3.2.0-4-kirkwood-di input-modules-3.2.0-4-kirkwood-di event-modules-3.2.0-4-kirkwood-di mouse-modules-3.2.0-4-kirkwood-di nic-usb-modules-3.2.0-4-kirkwood-di sata-modules-3.2.0-4-kirkwood-di core-modules-3.2.0-4-kirkwood-di crc-modules-3.2.0-4-kirkwood-di crypto-modules-3.2.0-4-kirkwood-di crypto-dm-modules-3.2.0-4-kirkwood-di mmc-modules-3.2.0-4-kirkwood-di nbd-modules-3.2.0-4-kirkwood-di squashfs-modules-3.2.0-4-kirkwood-di uinput-modules-3.2.0-4-kirkwood-di leds-modules-3.2.0-4-kirkwood-di udf-modules-3.2.0-4-kirkwood-di fuse-modules-3.2.0-4-kirkwood-di kernel-image-3.2.0-4-orion5x-di nic-modules-3.2.0-4-orion5x-di nic-shared-modules-3.2.0-4-orion5x-di usb-serial-modules-3.2.0-4-orion5x-di ppp-modules-3.2.0-4-orion5x-di cdrom-core-modules-3.2.0-4-orion5x-di scsi-core-modules-3.2.0-4-orion5x-di loop-modules-3.2.0-4-orion5x-di ipv6-modules-3.2.0-4-orion5x-di btrfs-modules-3.2.0-4-orion5x-di ext2-modules-3.2.0-4-orion5x-di ext3-modules-3.2.0-4-orion5x-di ext4-modules-3.2.0-4-orion5x-di isofs-modules-3.2.0-4-orion5x-di jffs2-modules-3.2.0-4-orion5x-di jfs-modules-3.2.0-4-orion5x-di reiserfs-modules-3.2.0-4-orion5x-di fat-modules-3.2.0-4-orion5x-di minix-modules-3.2.0-4-orion5x-di md-modules-3.2.0-4-orion5x-di multipath-modules-3.2.0-4-orion5x-di usb-modules-3.2.0-4-orion5x-di usb-storage-modules-3.2.0-4-orion5x-di event-modules-3.2.0-4-orion5x-di nic-usb-modules-3.2.0-4-orion5x-di sata-modules-3.2.0-4-orion5x-di core-modules-3.2.0-4-orion5x-di crc-modules-3.2.0-4-orion5x-di crypto-modules-3.2.0-4-orion5x-di crypto-dm-modules-3.2.0-4-orion5x-di nbd-modules-3.2.0-4-orion5x-di squashfs-modules-3.2.0-4-orion5x-di zlib-modules-3.2.0-4-orion5x-di udf-modules-3.2.0-4-orion5x-di fuse-modules-3.2.0-4-orion5x-di kernel-image-3.2.0-4-versatile-di nic-modules-3.2.0-4-versatile-di nic-shared-modules-3.2.0-4-versatile-di usb-serial-modules-3.2.0-4-versatile-di ppp-modules-3.2.0-4-versatile-di cdrom-core-modules-3.2.0-4-versatile-di scsi-core-modules-3.2.0-4-versatile-di scsi-common-modules-3.2.0-4-versatile-di loop-modules-3.2.0-4-versatile-di ipv6-modules-3.2.0-4-versatile-di btrfs-modules-3.2.0-4-versatile-di ext2-modules-3.2.0-4-versatile-di ext3-modules-3.2.0-4-versatile-di ext4-modules-3.2.0-4-versatile-di isofs-modules-3.2.0-4-versatile-di reiserfs-modules-3.2.0-4-versatile-di fat-modules-3.2.0-4-versatile-di md-modules-3.2.0-4-versatile-di multipath-modules-3.2.0-4-versatile-di usb-modules-3.2.0-4-versatile-di usb-storage-modules-3.2.0-4-versatile-di nic-usb-modules-3.2.0-4-versatile-di sata-modules-3.2.0-4-versatile-di core-modules-3.2.0-4-versatile-di crc-modules-3.2.0-4-versatile-di crypto-modules-3.2.0-4-versatile-di crypto-dm-modules-3.2.0-4-versatile-di nbd-modules-3.2.0-4-versatile-di squashfs-modules-3.2.0-4-versatile-di virtio-modules-3.2.0-4-versatile-di zlib-modules-3.2.0-4-versatile-di udf-modules-3.2.0-4-versatile-di fuse-modules-3.2.0-4-versatile-di' + $(MAKE) -f debian/rules.real install-udeb_armel ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='armel' KERNEL_ARCH='arm' SOURCEVERSION='3.2.46-1+rpi1' UPSTREAMVERSION='3.2' VERSION='3.2' PACKAGE_NAMES='kernel-image-3.2.0-4-iop32x-di nic-modules-3.2.0-4-iop32x-di nic-shared-modules-3.2.0-4-iop32x-di usb-serial-modules-3.2.0-4-iop32x-di ppp-modules-3.2.0-4-iop32x-di pata-modules-3.2.0-4-iop32x-di cdrom-core-modules-3.2.0-4-iop32x-di scsi-core-modules-3.2.0-4-iop32x-di loop-modules-3.2.0-4-iop32x-di ipv6-modules-3.2.0-4-iop32x-di btrfs-modules-3.2.0-4-iop32x-di ext2-modules-3.2.0-4-iop32x-di ext3-modules-3.2.0-4-iop32x-di ext4-modules-3.2.0-4-iop32x-di isofs-modules-3.2.0-4-iop32x-di jffs2-modules-3.2.0-4-iop32x-di jfs-modules-3.2.0-4-iop32x-di reiserfs-modules-3.2.0-4-iop32x-di fat-modules-3.2.0-4-iop32x-di md-modules-3.2.0-4-iop32x-di multipath-modules-3.2.0-4-iop32x-di usb-modules-3.2.0-4-iop32x-di usb-storage-modules-3.2.0-4-iop32x-di event-modules-3.2.0-4-iop32x-di nic-usb-modules-3.2.0-4-iop32x-di sata-modules-3.2.0-4-iop32x-di core-modules-3.2.0-4-iop32x-di crc-modules-3.2.0-4-iop32x-di crypto-modules-3.2.0-4-iop32x-di crypto-dm-modules-3.2.0-4-iop32x-di ata-modules-3.2.0-4-iop32x-di nbd-modules-3.2.0-4-iop32x-di squashfs-modules-3.2.0-4-iop32x-di zlib-modules-3.2.0-4-iop32x-di udf-modules-3.2.0-4-iop32x-di fuse-modules-3.2.0-4-iop32x-di kernel-image-3.2.0-4-kirkwood-di nic-modules-3.2.0-4-kirkwood-di nic-shared-modules-3.2.0-4-kirkwood-di usb-serial-modules-3.2.0-4-kirkwood-di ppp-modules-3.2.0-4-kirkwood-di cdrom-core-modules-3.2.0-4-kirkwood-di scsi-core-modules-3.2.0-4-kirkwood-di loop-modules-3.2.0-4-kirkwood-di ipv6-modules-3.2.0-4-kirkwood-di btrfs-modules-3.2.0-4-kirkwood-di ext2-modules-3.2.0-4-kirkwood-di ext3-modules-3.2.0-4-kirkwood-di ext4-modules-3.2.0-4-kirkwood-di isofs-modules-3.2.0-4-kirkwood-di jfs-modules-3.2.0-4-kirkwood-di reiserfs-modules-3.2.0-4-kirkwood-di fat-modules-3.2.0-4-kirkwood-di minix-modules-3.2.0-4-kirkwood-di md-modules-3.2.0-4-kirkwood-di multipath-modules-3.2.0-4-kirkwood-di usb-modules-3.2.0-4-kirkwood-di usb-storage-modules-3.2.0-4-kirkwood-di fb-modules-3.2.0-4-kirkwood-di input-modules-3.2.0-4-kirkwood-di event-modules-3.2.0-4-kirkwood-di mouse-modules-3.2.0-4-kirkwood-di nic-usb-modules-3.2.0-4-kirkwood-di sata-modules-3.2.0-4-kirkwood-di core-modules-3.2.0-4-kirkwood-di crc-modules-3.2.0-4-kirkwood-di crypto-modules-3.2.0-4-kirkwood-di crypto-dm-modules-3.2.0-4-kirkwood-di mmc-modules-3.2.0-4-kirkwood-di nbd-modules-3.2.0-4-kirkwood-di squashfs-modules-3.2.0-4-kirkwood-di uinput-modules-3.2.0-4-kirkwood-di leds-modules-3.2.0-4-kirkwood-di udf-modules-3.2.0-4-kirkwood-di fuse-modules-3.2.0-4-kirkwood-di kernel-image-3.2.0-4-orion5x-di nic-modules-3.2.0-4-orion5x-di nic-shared-modules-3.2.0-4-orion5x-di usb-serial-modules-3.2.0-4-orion5x-di ppp-modules-3.2.0-4-orion5x-di cdrom-core-modules-3.2.0-4-orion5x-di scsi-core-modules-3.2.0-4-orion5x-di loop-modules-3.2.0-4-orion5x-di ipv6-modules-3.2.0-4-orion5x-di btrfs-modules-3.2.0-4-orion5x-di ext2-modules-3.2.0-4-orion5x-di ext3-modules-3.2.0-4-orion5x-di ext4-modules-3.2.0-4-orion5x-di isofs-modules-3.2.0-4-orion5x-di jffs2-modules-3.2.0-4-orion5x-di jfs-modules-3.2.0-4-orion5x-di reiserfs-modules-3.2.0-4-orion5x-di fat-modules-3.2.0-4-orion5x-di minix-modules-3.2.0-4-orion5x-di md-modules-3.2.0-4-orion5x-di multipath-modules-3.2.0-4-orion5x-di usb-modules-3.2.0-4-orion5x-di usb-storage-modules-3.2.0-4-orion5x-di event-modules-3.2.0-4-orion5x-di nic-usb-modules-3.2.0-4-orion5x-di sata-modules-3.2.0-4-orion5x-di core-modules-3.2.0-4-orion5x-di crc-modules-3.2.0-4-orion5x-di crypto-modules-3.2.0-4-orion5x-di crypto-dm-modules-3.2.0-4-orion5x-di nbd-modules-3.2.0-4-orion5x-di squashfs-modules-3.2.0-4-orion5x-di zlib-modules-3.2.0-4-orion5x-di udf-modules-3.2.0-4-orion5x-di fuse-modules-3.2.0-4-orion5x-di kernel-image-3.2.0-4-versatile-di nic-modules-3.2.0-4-versatile-di nic-shared-modules-3.2.0-4-versatile-di usb-serial-modules-3.2.0-4-versatile-di ppp-modules-3.2.0-4-versatile-di cdrom-core-modules-3.2.0-4-versatile-di scsi-core-modules-3.2.0-4-versatile-di scsi-common-modules-3.2.0-4-versatile-di loop-modules-3.2.0-4-versatile-di ipv6-modules-3.2.0-4-versatile-di btrfs-modules-3.2.0-4-versatile-di ext2-modules-3.2.0-4-versatile-di ext3-modules-3.2.0-4-versatile-di ext4-modules-3.2.0-4-versatile-di isofs-modules-3.2.0-4-versatile-di reiserfs-modules-3.2.0-4-versatile-di fat-modules-3.2.0-4-versatile-di md-modules-3.2.0-4-versatile-di multipath-modules-3.2.0-4-versatile-di usb-modules-3.2.0-4-versatile-di usb-storage-modules-3.2.0-4-versatile-di nic-usb-modules-3.2.0-4-versatile-di sata-modules-3.2.0-4-versatile-di core-modules-3.2.0-4-versatile-di crc-modules-3.2.0-4-versatile-di crypto-modules-3.2.0-4-versatile-di crypto-dm-modules-3.2.0-4-versatile-di nbd-modules-3.2.0-4-versatile-di squashfs-modules-3.2.0-4-versatile-di virtio-modules-3.2.0-4-versatile-di zlib-modules-3.2.0-4-versatile-di udf-modules-3.2.0-4-versatile-di fuse-modules-3.2.0-4-versatile-di' binary-arch_armel_none: binary-arch_armel_none_iop32x binary-arch_armel_none_ixp4xx binary-arch_armel_none_kirkwood binary-arch_armel_none_mv78xx0 binary-arch_armel_none_orion5x binary-arch_armel_none_real binary-arch_armel_none_versatile binary-arch_armel_none_iop32x: binary-arch_armel_none_iop32x_real binary-arch_armel_none_iop32x_real:: - $(MAKE) -f debian/rules.real binary-arch-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='armel' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='iop32x' KCONFIG='debian/config/config debian/config/armel/config debian/config/armel/config.iop32x' KERNEL_ARCH='arm' LOCALVERSION='-iop32x' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-iop32x' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real binary-arch-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='armel' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='iop32x' KCONFIG='debian/config/config debian/config/armel/config debian/config/armel/config.iop32x' KERNEL_ARCH='arm' LOCALVERSION='-iop32x' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-iop32x' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' binary-arch_armel_none_ixp4xx: binary-arch_armel_none_ixp4xx_real binary-arch_armel_none_ixp4xx_real:: - $(MAKE) -f debian/rules.real binary-arch-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='armel' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='ixp4xx' KCONFIG='debian/config/config debian/config/armel/config debian/config/armel/config.ixp4xx' KERNEL_ARCH='arm' LOCALVERSION='-ixp4xx' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-ixp4xx' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real binary-arch-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='armel' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='ixp4xx' KCONFIG='debian/config/config debian/config/armel/config debian/config/armel/config.ixp4xx' KERNEL_ARCH='arm' LOCALVERSION='-ixp4xx' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-ixp4xx' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' binary-arch_armel_none_kirkwood: binary-arch_armel_none_kirkwood_real binary-arch_armel_none_kirkwood_real:: - $(MAKE) -f debian/rules.real binary-arch-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='armel' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='kirkwood' KCONFIG='debian/config/config debian/config/armel/config debian/config/armel/config.kirkwood' KERNEL_ARCH='arm' LOCALVERSION='-kirkwood' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-kirkwood' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real binary-arch-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='armel' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='kirkwood' KCONFIG='debian/config/config debian/config/armel/config debian/config/armel/config.kirkwood' KERNEL_ARCH='arm' LOCALVERSION='-kirkwood' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-kirkwood' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' binary-arch_armel_none_mv78xx0: binary-arch_armel_none_mv78xx0_real binary-arch_armel_none_mv78xx0_real:: - $(MAKE) -f debian/rules.real binary-arch-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='armel' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='mv78xx0' KCONFIG='debian/config/config debian/config/armel/config debian/config/armel/config.mv78xx0' KERNEL_ARCH='arm' LOCALVERSION='-mv78xx0' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-mv78xx0' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real binary-arch-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='armel' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='mv78xx0' KCONFIG='debian/config/config debian/config/armel/config debian/config/armel/config.mv78xx0' KERNEL_ARCH='arm' LOCALVERSION='-mv78xx0' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-mv78xx0' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' binary-arch_armel_none_orion5x: binary-arch_armel_none_orion5x_real binary-arch_armel_none_orion5x_real:: - $(MAKE) -f debian/rules.real binary-arch-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='armel' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='orion5x' KCONFIG='debian/config/config debian/config/armel/config debian/config/armel/config.orion5x' KERNEL_ARCH='arm' LOCALVERSION='-orion5x' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-orion5x' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real binary-arch-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='armel' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='orion5x' KCONFIG='debian/config/config debian/config/armel/config debian/config/armel/config.orion5x' KERNEL_ARCH='arm' LOCALVERSION='-orion5x' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-orion5x' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' binary-arch_armel_none_real:: - $(MAKE) -f debian/rules.real binary-arch-featureset ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='armel' FEATURESET='none' KERNEL_ARCH='arm' LOCALVERSION_HEADERS='' SOURCEVERSION='3.2.46-1' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real binary-arch-featureset ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='armel' FEATURESET='none' KERNEL_ARCH='arm' LOCALVERSION_HEADERS='' SOURCEVERSION='3.2.46-1+rpi1' UPSTREAMVERSION='3.2' VERSION='3.2' binary-arch_armel_none_versatile: binary-arch_armel_none_versatile_real binary-arch_armel_none_versatile_real:: - $(MAKE) -f debian/rules.real binary-arch-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='armel' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='versatile' KCONFIG='debian/config/config debian/config/armel/config debian/config/armel/config.versatile' KERNEL_ARCH='arm' LOCALVERSION='-versatile' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-versatile' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real binary-arch-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='armel' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='versatile' KCONFIG='debian/config/config debian/config/armel/config debian/config/armel/config.versatile' KERNEL_ARCH='arm' LOCALVERSION='-versatile' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-versatile' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' binary-arch_armel_real:: - $(MAKE) -f debian/rules.real binary-arch-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='armel' KERNEL_ARCH='arm' SOURCEVERSION='3.2.46-1' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real binary-arch-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='armel' KERNEL_ARCH='arm' SOURCEVERSION='3.2.46-1+rpi1' UPSTREAMVERSION='3.2' VERSION='3.2' binary-arch_armhf:: binary-arch_armhf_none binary-arch_armhf_real binary-arch_armhf:: - $(MAKE) -f debian/rules.real install-udeb_armhf ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='armhf' KERNEL_ARCH='arm' SOURCEVERSION='3.2.46-1' UPSTREAMVERSION='3.2' VERSION='3.2' PACKAGE_NAMES='kernel-image-3.2.0-4-mx5-di nic-wireless-modules-3.2.0-4-mx5-di nic-shared-modules-3.2.0-4-mx5-di pata-modules-3.2.0-4-mx5-di scsi-core-modules-3.2.0-4-mx5-di loop-modules-3.2.0-4-mx5-di ipv6-modules-3.2.0-4-mx5-di btrfs-modules-3.2.0-4-mx5-di ext2-modules-3.2.0-4-mx5-di ext3-modules-3.2.0-4-mx5-di ext4-modules-3.2.0-4-mx5-di isofs-modules-3.2.0-4-mx5-di jfs-modules-3.2.0-4-mx5-di reiserfs-modules-3.2.0-4-mx5-di fat-modules-3.2.0-4-mx5-di minix-modules-3.2.0-4-mx5-di md-modules-3.2.0-4-mx5-di multipath-modules-3.2.0-4-mx5-di usb-storage-modules-3.2.0-4-mx5-di input-modules-3.2.0-4-mx5-di nic-usb-modules-3.2.0-4-mx5-di sata-modules-3.2.0-4-mx5-di core-modules-3.2.0-4-mx5-di crc-modules-3.2.0-4-mx5-di crypto-modules-3.2.0-4-mx5-di crypto-dm-modules-3.2.0-4-mx5-di ata-modules-3.2.0-4-mx5-di mmc-modules-3.2.0-4-mx5-di nbd-modules-3.2.0-4-mx5-di squashfs-modules-3.2.0-4-mx5-di uinput-modules-3.2.0-4-mx5-di udf-modules-3.2.0-4-mx5-di fuse-modules-3.2.0-4-mx5-di mtd-modules-3.2.0-4-mx5-di kernel-image-3.2.0-4-vexpress-di nic-modules-3.2.0-4-vexpress-di nic-wireless-modules-3.2.0-4-vexpress-di nic-shared-modules-3.2.0-4-vexpress-di scsi-core-modules-3.2.0-4-vexpress-di loop-modules-3.2.0-4-vexpress-di ipv6-modules-3.2.0-4-vexpress-di btrfs-modules-3.2.0-4-vexpress-di ext2-modules-3.2.0-4-vexpress-di ext3-modules-3.2.0-4-vexpress-di ext4-modules-3.2.0-4-vexpress-di isofs-modules-3.2.0-4-vexpress-di jfs-modules-3.2.0-4-vexpress-di fat-modules-3.2.0-4-vexpress-di md-modules-3.2.0-4-vexpress-di multipath-modules-3.2.0-4-vexpress-di usb-modules-3.2.0-4-vexpress-di usb-storage-modules-3.2.0-4-vexpress-di input-modules-3.2.0-4-vexpress-di nic-usb-modules-3.2.0-4-vexpress-di core-modules-3.2.0-4-vexpress-di crc-modules-3.2.0-4-vexpress-di crypto-modules-3.2.0-4-vexpress-di crypto-dm-modules-3.2.0-4-vexpress-di mmc-modules-3.2.0-4-vexpress-di nbd-modules-3.2.0-4-vexpress-di squashfs-modules-3.2.0-4-vexpress-di uinput-modules-3.2.0-4-vexpress-di udf-modules-3.2.0-4-vexpress-di fuse-modules-3.2.0-4-vexpress-di' -binary-arch_armhf_none: binary-arch_armhf_none_mx5 binary-arch_armhf_none_omap binary-arch_armhf_none_real binary-arch_armhf_none_vexpress -binary-arch_armhf_none_mx5: binary-arch_armhf_none_mx5_real -binary-arch_armhf_none_mx5_real:: - $(MAKE) -f debian/rules.real binary-arch-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='armhf' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='mx5' KCONFIG='debian/config/config debian/config/armel/config debian/config/armhf/config debian/config/armhf/config.mx5' KERNEL_ARCH='arm' LOCALVERSION='-mx5' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-mx5' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' -binary-arch_armhf_none_omap: binary-arch_armhf_none_omap_real -binary-arch_armhf_none_omap_real:: - $(MAKE) -f debian/rules.real binary-arch-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='armhf' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='omap' KCONFIG='debian/config/config debian/config/armel/config debian/config/armhf/config debian/config/armhf/config.omap' KERNEL_ARCH='arm' LOCALVERSION='-omap' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-omap' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real install-udeb_armhf ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='armhf' KERNEL_ARCH='arm' SOURCEVERSION='3.2.46-1+rpi1' UPSTREAMVERSION='3.2' VERSION='3.2' PACKAGE_NAMES='kernel-image-3.2.0-4-rpi-di scsi-core-modules-3.2.0-4-rpi-di loop-modules-3.2.0-4-rpi-di ipv6-modules-3.2.0-4-rpi-di btrfs-modules-3.2.0-4-rpi-di ext2-modules-3.2.0-4-rpi-di ext3-modules-3.2.0-4-rpi-di isofs-modules-3.2.0-4-rpi-di jfs-modules-3.2.0-4-rpi-di reiserfs-modules-3.2.0-4-rpi-di fat-modules-3.2.0-4-rpi-di minix-modules-3.2.0-4-rpi-di md-modules-3.2.0-4-rpi-di multipath-modules-3.2.0-4-rpi-di usb-storage-modules-3.2.0-4-rpi-di input-modules-3.2.0-4-rpi-di nic-usb-modules-3.2.0-4-rpi-di crc-modules-3.2.0-4-rpi-di crypto-modules-3.2.0-4-rpi-di crypto-dm-modules-3.2.0-4-rpi-di nbd-modules-3.2.0-4-rpi-di squashfs-modules-3.2.0-4-rpi-di uinput-modules-3.2.0-4-rpi-di udf-modules-3.2.0-4-rpi-di fuse-modules-3.2.0-4-rpi-di' +binary-arch_armhf_none: binary-arch_armhf_none_real binary-arch_armhf_none_rpi binary-arch_armhf_none_real:: - $(MAKE) -f debian/rules.real binary-arch-featureset ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='armhf' FEATURESET='none' KERNEL_ARCH='arm' LOCALVERSION_HEADERS='' SOURCEVERSION='3.2.46-1' UPSTREAMVERSION='3.2' VERSION='3.2' -binary-arch_armhf_none_vexpress: binary-arch_armhf_none_vexpress_real -binary-arch_armhf_none_vexpress_real:: - $(MAKE) -f debian/rules.real binary-arch-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='armhf' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='vexpress' KCONFIG='debian/config/config debian/config/armel/config debian/config/armhf/config debian/config/armhf/config.vexpress' KERNEL_ARCH='arm' LOCALVERSION='-vexpress' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-vexpress' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real binary-arch-featureset ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='armhf' FEATURESET='none' KERNEL_ARCH='arm' LOCALVERSION_HEADERS='' SOURCEVERSION='3.2.46-1+rpi1' UPSTREAMVERSION='3.2' VERSION='3.2' +binary-arch_armhf_none_rpi: binary-arch_armhf_none_rpi_real +binary-arch_armhf_none_rpi_real:: + $(MAKE) -f debian/rules.real binary-arch-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='armhf' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='rpi' KCONFIG='debian/config/config debian/config/armel/config debian/config/armhf/config debian/config/armhf/config.rpi' KERNEL_ARCH='arm' LOCALVERSION='-rpi' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-rpi' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' binary-arch_armhf_real:: - $(MAKE) -f debian/rules.real binary-arch-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='armhf' KERNEL_ARCH='arm' SOURCEVERSION='3.2.46-1' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real binary-arch-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='armhf' KERNEL_ARCH='arm' SOURCEVERSION='3.2.46-1+rpi1' UPSTREAMVERSION='3.2' VERSION='3.2' binary-arch_hppa:: binary-arch_hppa_none binary-arch_hppa_real binary-arch_hppa:: - $(MAKE) -f debian/rules.real install-udeb_hppa ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='hppa' KERNEL_ARCH='parisc' SOURCEVERSION='3.2.46-1' UPSTREAMVERSION='3.2' VERSION='3.2' PACKAGE_NAMES='kernel-image-3.2.0-4-parisc-di nic-modules-3.2.0-4-parisc-di ppp-modules-3.2.0-4-parisc-di pata-modules-3.2.0-4-parisc-di cdrom-core-modules-3.2.0-4-parisc-di scsi-core-modules-3.2.0-4-parisc-di scsi-modules-3.2.0-4-parisc-di loop-modules-3.2.0-4-parisc-di ipv6-modules-3.2.0-4-parisc-di btrfs-modules-3.2.0-4-parisc-di ext3-modules-3.2.0-4-parisc-di ext4-modules-3.2.0-4-parisc-di fat-modules-3.2.0-4-parisc-di md-modules-3.2.0-4-parisc-di multipath-modules-3.2.0-4-parisc-di usb-modules-3.2.0-4-parisc-di usb-storage-modules-3.2.0-4-parisc-di input-modules-3.2.0-4-parisc-di crypto-modules-3.2.0-4-parisc-di crypto-dm-modules-3.2.0-4-parisc-di nbd-modules-3.2.0-4-parisc-di zlib-modules-3.2.0-4-parisc-di fuse-modules-3.2.0-4-parisc-di kernel-image-3.2.0-4-parisc64-di nic-modules-3.2.0-4-parisc64-di ppp-modules-3.2.0-4-parisc64-di pata-modules-3.2.0-4-parisc64-di cdrom-core-modules-3.2.0-4-parisc64-di scsi-core-modules-3.2.0-4-parisc64-di scsi-modules-3.2.0-4-parisc64-di loop-modules-3.2.0-4-parisc64-di ipv6-modules-3.2.0-4-parisc64-di btrfs-modules-3.2.0-4-parisc64-di ext3-modules-3.2.0-4-parisc64-di ext4-modules-3.2.0-4-parisc64-di fat-modules-3.2.0-4-parisc64-di md-modules-3.2.0-4-parisc64-di multipath-modules-3.2.0-4-parisc64-di usb-modules-3.2.0-4-parisc64-di usb-storage-modules-3.2.0-4-parisc64-di input-modules-3.2.0-4-parisc64-di crypto-modules-3.2.0-4-parisc64-di crypto-dm-modules-3.2.0-4-parisc64-di nbd-modules-3.2.0-4-parisc64-di zlib-modules-3.2.0-4-parisc64-di fuse-modules-3.2.0-4-parisc64-di' + $(MAKE) -f debian/rules.real install-udeb_hppa ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='hppa' KERNEL_ARCH='parisc' SOURCEVERSION='3.2.46-1+rpi1' UPSTREAMVERSION='3.2' VERSION='3.2' PACKAGE_NAMES='kernel-image-3.2.0-4-parisc-di nic-modules-3.2.0-4-parisc-di ppp-modules-3.2.0-4-parisc-di pata-modules-3.2.0-4-parisc-di cdrom-core-modules-3.2.0-4-parisc-di scsi-core-modules-3.2.0-4-parisc-di scsi-modules-3.2.0-4-parisc-di loop-modules-3.2.0-4-parisc-di ipv6-modules-3.2.0-4-parisc-di btrfs-modules-3.2.0-4-parisc-di ext3-modules-3.2.0-4-parisc-di ext4-modules-3.2.0-4-parisc-di fat-modules-3.2.0-4-parisc-di md-modules-3.2.0-4-parisc-di multipath-modules-3.2.0-4-parisc-di usb-modules-3.2.0-4-parisc-di usb-storage-modules-3.2.0-4-parisc-di input-modules-3.2.0-4-parisc-di crypto-modules-3.2.0-4-parisc-di crypto-dm-modules-3.2.0-4-parisc-di nbd-modules-3.2.0-4-parisc-di zlib-modules-3.2.0-4-parisc-di fuse-modules-3.2.0-4-parisc-di kernel-image-3.2.0-4-parisc64-di nic-modules-3.2.0-4-parisc64-di ppp-modules-3.2.0-4-parisc64-di pata-modules-3.2.0-4-parisc64-di cdrom-core-modules-3.2.0-4-parisc64-di scsi-core-modules-3.2.0-4-parisc64-di scsi-modules-3.2.0-4-parisc64-di loop-modules-3.2.0-4-parisc64-di ipv6-modules-3.2.0-4-parisc64-di btrfs-modules-3.2.0-4-parisc64-di ext3-modules-3.2.0-4-parisc64-di ext4-modules-3.2.0-4-parisc64-di fat-modules-3.2.0-4-parisc64-di md-modules-3.2.0-4-parisc64-di multipath-modules-3.2.0-4-parisc64-di usb-modules-3.2.0-4-parisc64-di usb-storage-modules-3.2.0-4-parisc64-di input-modules-3.2.0-4-parisc64-di crypto-modules-3.2.0-4-parisc64-di crypto-dm-modules-3.2.0-4-parisc64-di nbd-modules-3.2.0-4-parisc64-di zlib-modules-3.2.0-4-parisc64-di fuse-modules-3.2.0-4-parisc64-di' binary-arch_hppa_none: binary-arch_hppa_none_parisc binary-arch_hppa_none_parisc-smp binary-arch_hppa_none_parisc64 binary-arch_hppa_none_parisc64-smp binary-arch_hppa_none_real binary-arch_hppa_none_parisc: binary-arch_hppa_none_parisc_real binary-arch_hppa_none_parisc-smp: binary-arch_hppa_none_parisc-smp_real binary-arch_hppa_none_parisc-smp_real:: - $(MAKE) -f debian/rules.real binary-arch-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='hppa' COMPILER='gcc-4.4' FEATURESET='none' FLAVOUR='parisc-smp' KCONFIG='debian/config/config debian/config/hppa/config debian/config/hppa/config.parisc-smp' KERNEL_ARCH='parisc' LOCALVERSION='-parisc-smp' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-parisc-smp' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real binary-arch-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='hppa' COMPILER='gcc-4.4' FEATURESET='none' FLAVOUR='parisc-smp' KCONFIG='debian/config/config debian/config/hppa/config debian/config/hppa/config.parisc-smp' KERNEL_ARCH='parisc' LOCALVERSION='-parisc-smp' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-parisc-smp' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' binary-arch_hppa_none_parisc64: binary-arch_hppa_none_parisc64_real binary-arch_hppa_none_parisc64-smp: binary-arch_hppa_none_parisc64-smp_real binary-arch_hppa_none_parisc64-smp_real:: - $(MAKE) -f debian/rules.real binary-arch-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='hppa' CFLAGS_KERNEL='-fno-cse-follow-jumps' COMPILER='gcc-4.4' FEATURESET='none' FLAVOUR='parisc64-smp' KCONFIG='debian/config/config debian/config/hppa/config debian/config/hppa/config.parisc64-smp' KERNEL_ARCH='parisc' LOCALVERSION='-parisc64-smp' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-parisc64-smp' MODULES='True' OVERRIDE_HOST_TYPE='hppa64-linux-gnu' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real binary-arch-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='hppa' CFLAGS_KERNEL='-fno-cse-follow-jumps' COMPILER='gcc-4.4' FEATURESET='none' FLAVOUR='parisc64-smp' KCONFIG='debian/config/config debian/config/hppa/config debian/config/hppa/config.parisc64-smp' KERNEL_ARCH='parisc' LOCALVERSION='-parisc64-smp' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-parisc64-smp' MODULES='True' OVERRIDE_HOST_TYPE='hppa64-linux-gnu' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' binary-arch_hppa_none_parisc64_real:: - $(MAKE) -f debian/rules.real binary-arch-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='hppa' CFLAGS_KERNEL='-fno-cse-follow-jumps' COMPILER='gcc-4.4' FEATURESET='none' FLAVOUR='parisc64' KCONFIG='debian/config/config debian/config/hppa/config debian/config/hppa/config.parisc64' KERNEL_ARCH='parisc' LOCALVERSION='-parisc64' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-parisc64' MODULES='True' OVERRIDE_HOST_TYPE='hppa64-linux-gnu' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real binary-arch-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='hppa' CFLAGS_KERNEL='-fno-cse-follow-jumps' COMPILER='gcc-4.4' FEATURESET='none' FLAVOUR='parisc64' KCONFIG='debian/config/config debian/config/hppa/config debian/config/hppa/config.parisc64' KERNEL_ARCH='parisc' LOCALVERSION='-parisc64' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-parisc64' MODULES='True' OVERRIDE_HOST_TYPE='hppa64-linux-gnu' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' binary-arch_hppa_none_parisc_real:: - $(MAKE) -f debian/rules.real binary-arch-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='hppa' COMPILER='gcc-4.4' FEATURESET='none' FLAVOUR='parisc' KCONFIG='debian/config/config debian/config/hppa/config debian/config/hppa/config.parisc' KERNEL_ARCH='parisc' LOCALVERSION='-parisc' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-parisc' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real binary-arch-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='hppa' COMPILER='gcc-4.4' FEATURESET='none' FLAVOUR='parisc' KCONFIG='debian/config/config debian/config/hppa/config debian/config/hppa/config.parisc' KERNEL_ARCH='parisc' LOCALVERSION='-parisc' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-parisc' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' binary-arch_hppa_none_real:: - $(MAKE) -f debian/rules.real binary-arch-featureset ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='hppa' FEATURESET='none' KERNEL_ARCH='parisc' LOCALVERSION_HEADERS='' SOURCEVERSION='3.2.46-1' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real binary-arch-featureset ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='hppa' FEATURESET='none' KERNEL_ARCH='parisc' LOCALVERSION_HEADERS='' SOURCEVERSION='3.2.46-1+rpi1' UPSTREAMVERSION='3.2' VERSION='3.2' binary-arch_hppa_real:: - $(MAKE) -f debian/rules.real binary-arch-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='hppa' KERNEL_ARCH='parisc' SOURCEVERSION='3.2.46-1' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real binary-arch-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='hppa' KERNEL_ARCH='parisc' SOURCEVERSION='3.2.46-1+rpi1' UPSTREAMVERSION='3.2' VERSION='3.2' binary-arch_i386:: binary-arch_i386_none binary-arch_i386_real binary-arch_i386_rt binary-arch_i386:: - $(MAKE) -f debian/rules.real install-udeb_i386 ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='i386' KERNEL_ARCH='x86' SOURCEVERSION='3.2.46-1' UPSTREAMVERSION='3.2' VERSION='3.2' PACKAGE_NAMES='kernel-image-3.2.0-4-486-di nic-modules-3.2.0-4-486-di nic-extra-modules-3.2.0-4-486-di nic-wireless-modules-3.2.0-4-486-di nic-shared-modules-3.2.0-4-486-di serial-modules-3.2.0-4-486-di usb-serial-modules-3.2.0-4-486-di ppp-modules-3.2.0-4-486-di pata-modules-3.2.0-4-486-di cdrom-core-modules-3.2.0-4-486-di firewire-core-modules-3.2.0-4-486-di scsi-core-modules-3.2.0-4-486-di scsi-modules-3.2.0-4-486-di scsi-common-modules-3.2.0-4-486-di scsi-extra-modules-3.2.0-4-486-di plip-modules-3.2.0-4-486-di floppy-modules-3.2.0-4-486-di loop-modules-3.2.0-4-486-di btrfs-modules-3.2.0-4-486-di ext2-modules-3.2.0-4-486-di ext3-modules-3.2.0-4-486-di ext4-modules-3.2.0-4-486-di isofs-modules-3.2.0-4-486-di jfs-modules-3.2.0-4-486-di ntfs-modules-3.2.0-4-486-di reiserfs-modules-3.2.0-4-486-di xfs-modules-3.2.0-4-486-di fat-modules-3.2.0-4-486-di ufs-modules-3.2.0-4-486-di qnx4-modules-3.2.0-4-486-di md-modules-3.2.0-4-486-di multipath-modules-3.2.0-4-486-di usb-modules-3.2.0-4-486-di usb-storage-modules-3.2.0-4-486-di pcmcia-storage-modules-3.2.0-4-486-di fb-modules-3.2.0-4-486-di input-modules-3.2.0-4-486-di event-modules-3.2.0-4-486-di mouse-modules-3.2.0-4-486-di irda-modules-3.2.0-4-486-di parport-modules-3.2.0-4-486-di nic-pcmcia-modules-3.2.0-4-486-di pcmcia-modules-3.2.0-4-486-di nic-usb-modules-3.2.0-4-486-di sata-modules-3.2.0-4-486-di core-modules-3.2.0-4-486-di acpi-modules-3.2.0-4-486-di i2c-modules-3.2.0-4-486-di crc-modules-3.2.0-4-486-di crypto-modules-3.2.0-4-486-di crypto-dm-modules-3.2.0-4-486-di efi-modules-3.2.0-4-486-di ata-modules-3.2.0-4-486-di mmc-core-modules-3.2.0-4-486-di mmc-modules-3.2.0-4-486-di nbd-modules-3.2.0-4-486-di squashfs-modules-3.2.0-4-486-di speakup-modules-3.2.0-4-486-di virtio-modules-3.2.0-4-486-di uinput-modules-3.2.0-4-486-di sound-modules-3.2.0-4-486-di zlib-modules-3.2.0-4-486-di hyperv-modules-3.2.0-4-486-di udf-modules-3.2.0-4-486-di fuse-modules-3.2.0-4-486-di kernel-image-3.2.0-4-686-pae-di nic-modules-3.2.0-4-686-pae-di nic-extra-modules-3.2.0-4-686-pae-di nic-wireless-modules-3.2.0-4-686-pae-di nic-shared-modules-3.2.0-4-686-pae-di serial-modules-3.2.0-4-686-pae-di usb-serial-modules-3.2.0-4-686-pae-di ppp-modules-3.2.0-4-686-pae-di pata-modules-3.2.0-4-686-pae-di cdrom-core-modules-3.2.0-4-686-pae-di firewire-core-modules-3.2.0-4-686-pae-di scsi-core-modules-3.2.0-4-686-pae-di scsi-modules-3.2.0-4-686-pae-di scsi-common-modules-3.2.0-4-686-pae-di scsi-extra-modules-3.2.0-4-686-pae-di plip-modules-3.2.0-4-686-pae-di floppy-modules-3.2.0-4-686-pae-di loop-modules-3.2.0-4-686-pae-di btrfs-modules-3.2.0-4-686-pae-di ext2-modules-3.2.0-4-686-pae-di ext3-modules-3.2.0-4-686-pae-di ext4-modules-3.2.0-4-686-pae-di isofs-modules-3.2.0-4-686-pae-di jfs-modules-3.2.0-4-686-pae-di ntfs-modules-3.2.0-4-686-pae-di reiserfs-modules-3.2.0-4-686-pae-di xfs-modules-3.2.0-4-686-pae-di fat-modules-3.2.0-4-686-pae-di ufs-modules-3.2.0-4-686-pae-di qnx4-modules-3.2.0-4-686-pae-di md-modules-3.2.0-4-686-pae-di multipath-modules-3.2.0-4-686-pae-di usb-modules-3.2.0-4-686-pae-di usb-storage-modules-3.2.0-4-686-pae-di pcmcia-storage-modules-3.2.0-4-686-pae-di fb-modules-3.2.0-4-686-pae-di input-modules-3.2.0-4-686-pae-di event-modules-3.2.0-4-686-pae-di mouse-modules-3.2.0-4-686-pae-di irda-modules-3.2.0-4-686-pae-di parport-modules-3.2.0-4-686-pae-di nic-pcmcia-modules-3.2.0-4-686-pae-di pcmcia-modules-3.2.0-4-686-pae-di nic-usb-modules-3.2.0-4-686-pae-di sata-modules-3.2.0-4-686-pae-di core-modules-3.2.0-4-686-pae-di acpi-modules-3.2.0-4-686-pae-di i2c-modules-3.2.0-4-686-pae-di crc-modules-3.2.0-4-686-pae-di crypto-modules-3.2.0-4-686-pae-di crypto-dm-modules-3.2.0-4-686-pae-di efi-modules-3.2.0-4-686-pae-di ata-modules-3.2.0-4-686-pae-di mmc-core-modules-3.2.0-4-686-pae-di mmc-modules-3.2.0-4-686-pae-di nbd-modules-3.2.0-4-686-pae-di squashfs-modules-3.2.0-4-686-pae-di speakup-modules-3.2.0-4-686-pae-di virtio-modules-3.2.0-4-686-pae-di uinput-modules-3.2.0-4-686-pae-di sound-modules-3.2.0-4-686-pae-di zlib-modules-3.2.0-4-686-pae-di hyperv-modules-3.2.0-4-686-pae-di udf-modules-3.2.0-4-686-pae-di fuse-modules-3.2.0-4-686-pae-di' + $(MAKE) -f debian/rules.real install-udeb_i386 ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='i386' KERNEL_ARCH='x86' SOURCEVERSION='3.2.46-1+rpi1' UPSTREAMVERSION='3.2' VERSION='3.2' PACKAGE_NAMES='kernel-image-3.2.0-4-486-di nic-modules-3.2.0-4-486-di nic-extra-modules-3.2.0-4-486-di nic-wireless-modules-3.2.0-4-486-di nic-shared-modules-3.2.0-4-486-di serial-modules-3.2.0-4-486-di usb-serial-modules-3.2.0-4-486-di ppp-modules-3.2.0-4-486-di pata-modules-3.2.0-4-486-di cdrom-core-modules-3.2.0-4-486-di firewire-core-modules-3.2.0-4-486-di scsi-core-modules-3.2.0-4-486-di scsi-modules-3.2.0-4-486-di scsi-common-modules-3.2.0-4-486-di scsi-extra-modules-3.2.0-4-486-di plip-modules-3.2.0-4-486-di floppy-modules-3.2.0-4-486-di loop-modules-3.2.0-4-486-di btrfs-modules-3.2.0-4-486-di ext2-modules-3.2.0-4-486-di ext3-modules-3.2.0-4-486-di ext4-modules-3.2.0-4-486-di isofs-modules-3.2.0-4-486-di jfs-modules-3.2.0-4-486-di ntfs-modules-3.2.0-4-486-di reiserfs-modules-3.2.0-4-486-di xfs-modules-3.2.0-4-486-di fat-modules-3.2.0-4-486-di ufs-modules-3.2.0-4-486-di qnx4-modules-3.2.0-4-486-di md-modules-3.2.0-4-486-di multipath-modules-3.2.0-4-486-di usb-modules-3.2.0-4-486-di usb-storage-modules-3.2.0-4-486-di pcmcia-storage-modules-3.2.0-4-486-di fb-modules-3.2.0-4-486-di input-modules-3.2.0-4-486-di event-modules-3.2.0-4-486-di mouse-modules-3.2.0-4-486-di irda-modules-3.2.0-4-486-di parport-modules-3.2.0-4-486-di nic-pcmcia-modules-3.2.0-4-486-di pcmcia-modules-3.2.0-4-486-di nic-usb-modules-3.2.0-4-486-di sata-modules-3.2.0-4-486-di core-modules-3.2.0-4-486-di acpi-modules-3.2.0-4-486-di i2c-modules-3.2.0-4-486-di crc-modules-3.2.0-4-486-di crypto-modules-3.2.0-4-486-di crypto-dm-modules-3.2.0-4-486-di efi-modules-3.2.0-4-486-di ata-modules-3.2.0-4-486-di mmc-core-modules-3.2.0-4-486-di mmc-modules-3.2.0-4-486-di nbd-modules-3.2.0-4-486-di squashfs-modules-3.2.0-4-486-di speakup-modules-3.2.0-4-486-di virtio-modules-3.2.0-4-486-di uinput-modules-3.2.0-4-486-di sound-modules-3.2.0-4-486-di zlib-modules-3.2.0-4-486-di hyperv-modules-3.2.0-4-486-di udf-modules-3.2.0-4-486-di fuse-modules-3.2.0-4-486-di kernel-image-3.2.0-4-686-pae-di nic-modules-3.2.0-4-686-pae-di nic-extra-modules-3.2.0-4-686-pae-di nic-wireless-modules-3.2.0-4-686-pae-di nic-shared-modules-3.2.0-4-686-pae-di serial-modules-3.2.0-4-686-pae-di usb-serial-modules-3.2.0-4-686-pae-di ppp-modules-3.2.0-4-686-pae-di pata-modules-3.2.0-4-686-pae-di cdrom-core-modules-3.2.0-4-686-pae-di firewire-core-modules-3.2.0-4-686-pae-di scsi-core-modules-3.2.0-4-686-pae-di scsi-modules-3.2.0-4-686-pae-di scsi-common-modules-3.2.0-4-686-pae-di scsi-extra-modules-3.2.0-4-686-pae-di plip-modules-3.2.0-4-686-pae-di floppy-modules-3.2.0-4-686-pae-di loop-modules-3.2.0-4-686-pae-di btrfs-modules-3.2.0-4-686-pae-di ext2-modules-3.2.0-4-686-pae-di ext3-modules-3.2.0-4-686-pae-di ext4-modules-3.2.0-4-686-pae-di isofs-modules-3.2.0-4-686-pae-di jfs-modules-3.2.0-4-686-pae-di ntfs-modules-3.2.0-4-686-pae-di reiserfs-modules-3.2.0-4-686-pae-di xfs-modules-3.2.0-4-686-pae-di fat-modules-3.2.0-4-686-pae-di ufs-modules-3.2.0-4-686-pae-di qnx4-modules-3.2.0-4-686-pae-di md-modules-3.2.0-4-686-pae-di multipath-modules-3.2.0-4-686-pae-di usb-modules-3.2.0-4-686-pae-di usb-storage-modules-3.2.0-4-686-pae-di pcmcia-storage-modules-3.2.0-4-686-pae-di fb-modules-3.2.0-4-686-pae-di input-modules-3.2.0-4-686-pae-di event-modules-3.2.0-4-686-pae-di mouse-modules-3.2.0-4-686-pae-di irda-modules-3.2.0-4-686-pae-di parport-modules-3.2.0-4-686-pae-di nic-pcmcia-modules-3.2.0-4-686-pae-di pcmcia-modules-3.2.0-4-686-pae-di nic-usb-modules-3.2.0-4-686-pae-di sata-modules-3.2.0-4-686-pae-di core-modules-3.2.0-4-686-pae-di acpi-modules-3.2.0-4-686-pae-di i2c-modules-3.2.0-4-686-pae-di crc-modules-3.2.0-4-686-pae-di crypto-modules-3.2.0-4-686-pae-di crypto-dm-modules-3.2.0-4-686-pae-di efi-modules-3.2.0-4-686-pae-di ata-modules-3.2.0-4-686-pae-di mmc-core-modules-3.2.0-4-686-pae-di mmc-modules-3.2.0-4-686-pae-di nbd-modules-3.2.0-4-686-pae-di squashfs-modules-3.2.0-4-686-pae-di speakup-modules-3.2.0-4-686-pae-di virtio-modules-3.2.0-4-686-pae-di uinput-modules-3.2.0-4-686-pae-di sound-modules-3.2.0-4-686-pae-di zlib-modules-3.2.0-4-686-pae-di hyperv-modules-3.2.0-4-686-pae-di udf-modules-3.2.0-4-686-pae-di fuse-modules-3.2.0-4-686-pae-di' binary-arch_i386_none: binary-arch_i386_none_486 binary-arch_i386_none_686-pae binary-arch_i386_none_amd64 binary-arch_i386_none_real binary-arch_i386_none_486: binary-arch_i386_none_486_real binary-arch_i386_none_486_real:: - $(MAKE) -f debian/rules.real binary-arch-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='i386' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='486' KCONFIG='debian/config/config debian/config/kernelarch-x86/config debian/config/kernelarch-x86/config-arch-32 debian/config/i386/none/config.486' KERNEL_ARCH='x86' LOCALVERSION='-486' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-486' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real binary-arch-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='i386' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='486' KCONFIG='debian/config/config debian/config/kernelarch-x86/config debian/config/kernelarch-x86/config-arch-32 debian/config/i386/none/config.486' KERNEL_ARCH='x86' LOCALVERSION='-486' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-486' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' binary-arch_i386_none_686-pae: binary-arch_i386_none_686-pae_real binary-arch_i386_none_686-pae_real:: - $(MAKE) -f debian/rules.real binary-arch-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='i386' COMPILER='gcc-4.6' DEBUG='True' FEATURESET='none' FLAVOUR='686-pae' KCONFIG='debian/config/config debian/config/kernelarch-x86/config debian/config/kernelarch-x86/config-arch-32 debian/config/i386/none/config.686-pae' KCONFIG_OPTIONS='-o DEBUG_INFO=y' KERNEL_ARCH='x86' LOCALVERSION='-686-pae' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-686-pae' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' - $(MAKE) -f debian/rules.real install-dummy DH_OPTIONS='-pxen-linux-system-3.2.0-4-686-pae' ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='i386' COMPILER='gcc-4.6' DEBUG='True' FEATURESET='none' FLAVOUR='686-pae' KCONFIG='debian/config/config debian/config/kernelarch-x86/config debian/config/kernelarch-x86/config-arch-32 debian/config/i386/none/config.686-pae' KCONFIG_OPTIONS='-o DEBUG_INFO=y' KERNEL_ARCH='x86' LOCALVERSION='-686-pae' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-686-pae' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real binary-arch-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='i386' COMPILER='gcc-4.6' DEBUG='True' FEATURESET='none' FLAVOUR='686-pae' KCONFIG='debian/config/config debian/config/kernelarch-x86/config debian/config/kernelarch-x86/config-arch-32 debian/config/i386/none/config.686-pae' KCONFIG_OPTIONS='-o DEBUG_INFO=y' KERNEL_ARCH='x86' LOCALVERSION='-686-pae' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-686-pae' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real install-dummy DH_OPTIONS='-pxen-linux-system-3.2.0-4-686-pae' ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='i386' COMPILER='gcc-4.6' DEBUG='True' FEATURESET='none' FLAVOUR='686-pae' KCONFIG='debian/config/config debian/config/kernelarch-x86/config debian/config/kernelarch-x86/config-arch-32 debian/config/i386/none/config.686-pae' KCONFIG_OPTIONS='-o DEBUG_INFO=y' KERNEL_ARCH='x86' LOCALVERSION='-686-pae' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-686-pae' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' binary-arch_i386_none_amd64: binary-arch_i386_none_amd64_real binary-arch_i386_none_amd64_real:: - $(MAKE) -f debian/rules.real binary-arch-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='i386' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='amd64' KCONFIG='debian/config/config debian/config/kernelarch-x86/config debian/config/kernelarch-x86/config-arch-64' KERNEL_ARCH='x86' LOCALVERSION='-amd64' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-amd64' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' - $(MAKE) -f debian/rules.real install-dummy DH_OPTIONS='-pxen-linux-system-3.2.0-4-amd64' ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='i386' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='amd64' KCONFIG='debian/config/config debian/config/kernelarch-x86/config debian/config/kernelarch-x86/config-arch-64' KERNEL_ARCH='x86' LOCALVERSION='-amd64' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-amd64' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real binary-arch-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='i386' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='amd64' KCONFIG='debian/config/config debian/config/kernelarch-x86/config debian/config/kernelarch-x86/config-arch-64' KERNEL_ARCH='x86' LOCALVERSION='-amd64' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-amd64' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real install-dummy DH_OPTIONS='-pxen-linux-system-3.2.0-4-amd64' ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='i386' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='amd64' KCONFIG='debian/config/config debian/config/kernelarch-x86/config debian/config/kernelarch-x86/config-arch-64' KERNEL_ARCH='x86' LOCALVERSION='-amd64' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-amd64' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' binary-arch_i386_none_real:: - $(MAKE) -f debian/rules.real binary-arch-featureset ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='i386' FEATURESET='none' KERNEL_ARCH='x86' LOCALVERSION_HEADERS='' SOURCEVERSION='3.2.46-1' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real binary-arch-featureset ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='i386' FEATURESET='none' KERNEL_ARCH='x86' LOCALVERSION_HEADERS='' SOURCEVERSION='3.2.46-1+rpi1' UPSTREAMVERSION='3.2' VERSION='3.2' binary-arch_i386_real:: - $(MAKE) -f debian/rules.real binary-arch-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='i386' KERNEL_ARCH='x86' SOURCEVERSION='3.2.46-1' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real binary-arch-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='i386' KERNEL_ARCH='x86' SOURCEVERSION='3.2.46-1+rpi1' UPSTREAMVERSION='3.2' VERSION='3.2' binary-arch_i386_rt: binary-arch_i386_rt_686-pae binary-arch_i386_rt_real binary-arch_i386_rt_686-pae: binary-arch_i386_rt_686-pae_real binary-arch_i386_rt_686-pae_real:: - $(MAKE) -f debian/rules.real binary-arch-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='i386' COMPILER='gcc-4.6' DEBUG='True' FEATURESET='rt' FLAVOUR='686-pae' KCONFIG='debian/config/config debian/config/kernelarch-x86/config debian/config/kernelarch-x86/config-arch-32 debian/config/featureset-rt/config debian/config/i386/rt/config.686-pae' KCONFIG_OPTIONS='-o DEBUG_INFO=y' KERNEL_ARCH='x86' LOCALVERSION='-rt-686-pae' LOCALVERSION_HEADERS='-rt' LOCALVERSION_IMAGE='-rt-686-pae' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real binary-arch-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='i386' COMPILER='gcc-4.6' DEBUG='True' FEATURESET='rt' FLAVOUR='686-pae' KCONFIG='debian/config/config debian/config/kernelarch-x86/config debian/config/kernelarch-x86/config-arch-32 debian/config/featureset-rt/config debian/config/i386/rt/config.686-pae' KCONFIG_OPTIONS='-o DEBUG_INFO=y' KERNEL_ARCH='x86' LOCALVERSION='-rt-686-pae' LOCALVERSION_HEADERS='-rt' LOCALVERSION_IMAGE='-rt-686-pae' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' binary-arch_i386_rt_real:: - $(MAKE) -f debian/rules.real binary-arch-featureset ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='i386' FEATURESET='rt' KERNEL_ARCH='x86' LOCALVERSION_HEADERS='-rt' SOURCEVERSION='3.2.46-1' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real binary-arch-featureset ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='i386' FEATURESET='rt' KERNEL_ARCH='x86' LOCALVERSION_HEADERS='-rt' SOURCEVERSION='3.2.46-1+rpi1' UPSTREAMVERSION='3.2' VERSION='3.2' binary-arch_ia64:: binary-arch_ia64_none binary-arch_ia64_real binary-arch_ia64:: - $(MAKE) -f debian/rules.real install-udeb_ia64 ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='ia64' KERNEL_ARCH='ia64' SOURCEVERSION='3.2.46-1' UPSTREAMVERSION='3.2' VERSION='3.2' PACKAGE_NAMES='kernel-image-3.2.0-4-itanium-di nic-modules-3.2.0-4-itanium-di nic-shared-modules-3.2.0-4-itanium-di serial-modules-3.2.0-4-itanium-di ppp-modules-3.2.0-4-itanium-di ide-modules-3.2.0-4-itanium-di pata-modules-3.2.0-4-itanium-di ide-core-modules-3.2.0-4-itanium-di cdrom-core-modules-3.2.0-4-itanium-di firewire-core-modules-3.2.0-4-itanium-di scsi-core-modules-3.2.0-4-itanium-di scsi-modules-3.2.0-4-itanium-di plip-modules-3.2.0-4-itanium-di loop-modules-3.2.0-4-itanium-di btrfs-modules-3.2.0-4-itanium-di ext2-modules-3.2.0-4-itanium-di ext3-modules-3.2.0-4-itanium-di ext4-modules-3.2.0-4-itanium-di isofs-modules-3.2.0-4-itanium-di jfs-modules-3.2.0-4-itanium-di ntfs-modules-3.2.0-4-itanium-di reiserfs-modules-3.2.0-4-itanium-di xfs-modules-3.2.0-4-itanium-di fat-modules-3.2.0-4-itanium-di ufs-modules-3.2.0-4-itanium-di md-modules-3.2.0-4-itanium-di multipath-modules-3.2.0-4-itanium-di usb-modules-3.2.0-4-itanium-di usb-storage-modules-3.2.0-4-itanium-di fb-modules-3.2.0-4-itanium-di input-modules-3.2.0-4-itanium-di event-modules-3.2.0-4-itanium-di mouse-modules-3.2.0-4-itanium-di irda-modules-3.2.0-4-itanium-di parport-modules-3.2.0-4-itanium-di pcmcia-modules-3.2.0-4-itanium-di nic-usb-modules-3.2.0-4-itanium-di sata-modules-3.2.0-4-itanium-di core-modules-3.2.0-4-itanium-di crc-modules-3.2.0-4-itanium-di crypto-modules-3.2.0-4-itanium-di crypto-dm-modules-3.2.0-4-itanium-di ata-modules-3.2.0-4-itanium-di nbd-modules-3.2.0-4-itanium-di squashfs-modules-3.2.0-4-itanium-di uinput-modules-3.2.0-4-itanium-di zlib-modules-3.2.0-4-itanium-di udf-modules-3.2.0-4-itanium-di fuse-modules-3.2.0-4-itanium-di sn-modules-3.2.0-4-itanium-di' + $(MAKE) -f debian/rules.real install-udeb_ia64 ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='ia64' KERNEL_ARCH='ia64' SOURCEVERSION='3.2.46-1+rpi1' UPSTREAMVERSION='3.2' VERSION='3.2' PACKAGE_NAMES='kernel-image-3.2.0-4-itanium-di nic-modules-3.2.0-4-itanium-di nic-shared-modules-3.2.0-4-itanium-di serial-modules-3.2.0-4-itanium-di ppp-modules-3.2.0-4-itanium-di ide-modules-3.2.0-4-itanium-di pata-modules-3.2.0-4-itanium-di ide-core-modules-3.2.0-4-itanium-di cdrom-core-modules-3.2.0-4-itanium-di firewire-core-modules-3.2.0-4-itanium-di scsi-core-modules-3.2.0-4-itanium-di scsi-modules-3.2.0-4-itanium-di plip-modules-3.2.0-4-itanium-di loop-modules-3.2.0-4-itanium-di btrfs-modules-3.2.0-4-itanium-di ext2-modules-3.2.0-4-itanium-di ext3-modules-3.2.0-4-itanium-di ext4-modules-3.2.0-4-itanium-di isofs-modules-3.2.0-4-itanium-di jfs-modules-3.2.0-4-itanium-di ntfs-modules-3.2.0-4-itanium-di reiserfs-modules-3.2.0-4-itanium-di xfs-modules-3.2.0-4-itanium-di fat-modules-3.2.0-4-itanium-di ufs-modules-3.2.0-4-itanium-di md-modules-3.2.0-4-itanium-di multipath-modules-3.2.0-4-itanium-di usb-modules-3.2.0-4-itanium-di usb-storage-modules-3.2.0-4-itanium-di fb-modules-3.2.0-4-itanium-di input-modules-3.2.0-4-itanium-di event-modules-3.2.0-4-itanium-di mouse-modules-3.2.0-4-itanium-di irda-modules-3.2.0-4-itanium-di parport-modules-3.2.0-4-itanium-di pcmcia-modules-3.2.0-4-itanium-di nic-usb-modules-3.2.0-4-itanium-di sata-modules-3.2.0-4-itanium-di core-modules-3.2.0-4-itanium-di crc-modules-3.2.0-4-itanium-di crypto-modules-3.2.0-4-itanium-di crypto-dm-modules-3.2.0-4-itanium-di ata-modules-3.2.0-4-itanium-di nbd-modules-3.2.0-4-itanium-di squashfs-modules-3.2.0-4-itanium-di uinput-modules-3.2.0-4-itanium-di zlib-modules-3.2.0-4-itanium-di udf-modules-3.2.0-4-itanium-di fuse-modules-3.2.0-4-itanium-di sn-modules-3.2.0-4-itanium-di' binary-arch_ia64_none: binary-arch_ia64_none_itanium binary-arch_ia64_none_mckinley binary-arch_ia64_none_real binary-arch_ia64_none_itanium: binary-arch_ia64_none_itanium_real binary-arch_ia64_none_itanium_real:: - $(MAKE) -f debian/rules.real binary-arch-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='ia64' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='itanium' KCONFIG='debian/config/config debian/config/ia64/config debian/config/ia64/config.itanium' KERNEL_ARCH='ia64' LOCALVERSION='-itanium' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-itanium' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real binary-arch-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='ia64' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='itanium' KCONFIG='debian/config/config debian/config/ia64/config debian/config/ia64/config.itanium' KERNEL_ARCH='ia64' LOCALVERSION='-itanium' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-itanium' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' binary-arch_ia64_none_mckinley: binary-arch_ia64_none_mckinley_real binary-arch_ia64_none_mckinley_real:: - $(MAKE) -f debian/rules.real binary-arch-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='ia64' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='mckinley' KCONFIG='debian/config/config debian/config/ia64/config debian/config/ia64/config.mckinley' KERNEL_ARCH='ia64' LOCALVERSION='-mckinley' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-mckinley' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real binary-arch-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='ia64' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='mckinley' KCONFIG='debian/config/config debian/config/ia64/config debian/config/ia64/config.mckinley' KERNEL_ARCH='ia64' LOCALVERSION='-mckinley' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-mckinley' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' binary-arch_ia64_none_real:: - $(MAKE) -f debian/rules.real binary-arch-featureset ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='ia64' FEATURESET='none' KERNEL_ARCH='ia64' LOCALVERSION_HEADERS='' SOURCEVERSION='3.2.46-1' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real binary-arch-featureset ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='ia64' FEATURESET='none' KERNEL_ARCH='ia64' LOCALVERSION_HEADERS='' SOURCEVERSION='3.2.46-1+rpi1' UPSTREAMVERSION='3.2' VERSION='3.2' binary-arch_ia64_real:: - $(MAKE) -f debian/rules.real binary-arch-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='ia64' KERNEL_ARCH='ia64' SOURCEVERSION='3.2.46-1' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real binary-arch-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='ia64' KERNEL_ARCH='ia64' SOURCEVERSION='3.2.46-1+rpi1' UPSTREAMVERSION='3.2' VERSION='3.2' binary-arch_m68k:: binary-arch_m68k_none binary-arch_m68k_real binary-arch_m68k:: - $(MAKE) -f debian/rules.real install-udeb_m68k ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='m68k' KERNEL_ARCH='m68k' SOURCEVERSION='3.2.46-1' UPSTREAMVERSION='3.2' VERSION='3.2' PACKAGE_NAMES='kernel-image-3.2.0-4-amiga-di nic-shared-modules-3.2.0-4-amiga-di ppp-modules-3.2.0-4-amiga-di cdrom-core-modules-3.2.0-4-amiga-di scsi-modules-3.2.0-4-amiga-di ipv6-modules-3.2.0-4-amiga-di btrfs-modules-3.2.0-4-amiga-di isofs-modules-3.2.0-4-amiga-di jfs-modules-3.2.0-4-amiga-di reiserfs-modules-3.2.0-4-amiga-di fat-modules-3.2.0-4-amiga-di md-modules-3.2.0-4-amiga-di crypto-modules-3.2.0-4-amiga-di nbd-modules-3.2.0-4-amiga-di squashfs-modules-3.2.0-4-amiga-di zlib-modules-3.2.0-4-amiga-di udf-modules-3.2.0-4-amiga-di fuse-modules-3.2.0-4-amiga-di kernel-image-3.2.0-4-atari-di nic-shared-modules-3.2.0-4-atari-di ppp-modules-3.2.0-4-atari-di cdrom-core-modules-3.2.0-4-atari-di scsi-modules-3.2.0-4-atari-di ipv6-modules-3.2.0-4-atari-di btrfs-modules-3.2.0-4-atari-di isofs-modules-3.2.0-4-atari-di jfs-modules-3.2.0-4-atari-di reiserfs-modules-3.2.0-4-atari-di fat-modules-3.2.0-4-atari-di md-modules-3.2.0-4-atari-di crypto-modules-3.2.0-4-atari-di nbd-modules-3.2.0-4-atari-di squashfs-modules-3.2.0-4-atari-di zlib-modules-3.2.0-4-atari-di udf-modules-3.2.0-4-atari-di fuse-modules-3.2.0-4-atari-di kernel-image-3.2.0-4-mac-di nic-shared-modules-3.2.0-4-mac-di ppp-modules-3.2.0-4-mac-di cdrom-core-modules-3.2.0-4-mac-di scsi-modules-3.2.0-4-mac-di ipv6-modules-3.2.0-4-mac-di btrfs-modules-3.2.0-4-mac-di isofs-modules-3.2.0-4-mac-di jfs-modules-3.2.0-4-mac-di reiserfs-modules-3.2.0-4-mac-di fat-modules-3.2.0-4-mac-di md-modules-3.2.0-4-mac-di crypto-modules-3.2.0-4-mac-di nbd-modules-3.2.0-4-mac-di squashfs-modules-3.2.0-4-mac-di zlib-modules-3.2.0-4-mac-di udf-modules-3.2.0-4-mac-di fuse-modules-3.2.0-4-mac-di' + $(MAKE) -f debian/rules.real install-udeb_m68k ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='m68k' KERNEL_ARCH='m68k' SOURCEVERSION='3.2.46-1+rpi1' UPSTREAMVERSION='3.2' VERSION='3.2' PACKAGE_NAMES='kernel-image-3.2.0-4-amiga-di nic-shared-modules-3.2.0-4-amiga-di ppp-modules-3.2.0-4-amiga-di cdrom-core-modules-3.2.0-4-amiga-di scsi-modules-3.2.0-4-amiga-di ipv6-modules-3.2.0-4-amiga-di btrfs-modules-3.2.0-4-amiga-di isofs-modules-3.2.0-4-amiga-di jfs-modules-3.2.0-4-amiga-di reiserfs-modules-3.2.0-4-amiga-di fat-modules-3.2.0-4-amiga-di md-modules-3.2.0-4-amiga-di crypto-modules-3.2.0-4-amiga-di nbd-modules-3.2.0-4-amiga-di squashfs-modules-3.2.0-4-amiga-di zlib-modules-3.2.0-4-amiga-di udf-modules-3.2.0-4-amiga-di fuse-modules-3.2.0-4-amiga-di kernel-image-3.2.0-4-atari-di nic-shared-modules-3.2.0-4-atari-di ppp-modules-3.2.0-4-atari-di cdrom-core-modules-3.2.0-4-atari-di scsi-modules-3.2.0-4-atari-di ipv6-modules-3.2.0-4-atari-di btrfs-modules-3.2.0-4-atari-di isofs-modules-3.2.0-4-atari-di jfs-modules-3.2.0-4-atari-di reiserfs-modules-3.2.0-4-atari-di fat-modules-3.2.0-4-atari-di md-modules-3.2.0-4-atari-di crypto-modules-3.2.0-4-atari-di nbd-modules-3.2.0-4-atari-di squashfs-modules-3.2.0-4-atari-di zlib-modules-3.2.0-4-atari-di udf-modules-3.2.0-4-atari-di fuse-modules-3.2.0-4-atari-di kernel-image-3.2.0-4-mac-di nic-shared-modules-3.2.0-4-mac-di ppp-modules-3.2.0-4-mac-di cdrom-core-modules-3.2.0-4-mac-di scsi-modules-3.2.0-4-mac-di ipv6-modules-3.2.0-4-mac-di btrfs-modules-3.2.0-4-mac-di isofs-modules-3.2.0-4-mac-di jfs-modules-3.2.0-4-mac-di reiserfs-modules-3.2.0-4-mac-di fat-modules-3.2.0-4-mac-di md-modules-3.2.0-4-mac-di crypto-modules-3.2.0-4-mac-di nbd-modules-3.2.0-4-mac-di squashfs-modules-3.2.0-4-mac-di zlib-modules-3.2.0-4-mac-di udf-modules-3.2.0-4-mac-di fuse-modules-3.2.0-4-mac-di' binary-arch_m68k_none: binary-arch_m68k_none_amiga binary-arch_m68k_none_atari binary-arch_m68k_none_bvme6000 binary-arch_m68k_none_mac binary-arch_m68k_none_mvme147 binary-arch_m68k_none_mvme16x binary-arch_m68k_none_real binary-arch_m68k_none_amiga: binary-arch_m68k_none_amiga_real binary-arch_m68k_none_amiga_real:: - $(MAKE) -f debian/rules.real binary-arch-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='m68k' CFLAGS_KERNEL='-ffreestanding' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='amiga' INITRAMFS='False' KCONFIG='debian/config/config debian/config/m68k/config debian/config/m68k/config.amiga' KERNEL_ARCH='m68k' LOCALVERSION='-amiga' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-amiga' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real binary-arch-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='m68k' CFLAGS_KERNEL='-ffreestanding' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='amiga' INITRAMFS='False' KCONFIG='debian/config/config debian/config/m68k/config debian/config/m68k/config.amiga' KERNEL_ARCH='m68k' LOCALVERSION='-amiga' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-amiga' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' binary-arch_m68k_none_atari: binary-arch_m68k_none_atari_real binary-arch_m68k_none_atari_real:: - $(MAKE) -f debian/rules.real binary-arch-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='m68k' CFLAGS_KERNEL='-ffreestanding' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='atari' INITRAMFS='False' KCONFIG='debian/config/config debian/config/m68k/config debian/config/m68k/config.atari' KERNEL_ARCH='m68k' LOCALVERSION='-atari' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-atari' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real binary-arch-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='m68k' CFLAGS_KERNEL='-ffreestanding' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='atari' INITRAMFS='False' KCONFIG='debian/config/config debian/config/m68k/config debian/config/m68k/config.atari' KERNEL_ARCH='m68k' LOCALVERSION='-atari' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-atari' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' binary-arch_m68k_none_bvme6000: binary-arch_m68k_none_bvme6000_real binary-arch_m68k_none_bvme6000_real:: - $(MAKE) -f debian/rules.real binary-arch-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='m68k' CFLAGS_KERNEL='-ffreestanding' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='bvme6000' INITRAMFS='False' KCONFIG='debian/config/config debian/config/m68k/config debian/config/m68k/config.bvme6000' KERNEL_ARCH='m68k' LOCALVERSION='-bvme6000' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-bvme6000' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real binary-arch-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='m68k' CFLAGS_KERNEL='-ffreestanding' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='bvme6000' INITRAMFS='False' KCONFIG='debian/config/config debian/config/m68k/config debian/config/m68k/config.bvme6000' KERNEL_ARCH='m68k' LOCALVERSION='-bvme6000' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-bvme6000' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' binary-arch_m68k_none_mac: binary-arch_m68k_none_mac_real binary-arch_m68k_none_mac_real:: - $(MAKE) -f debian/rules.real binary-arch-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='m68k' CFLAGS_KERNEL='-ffreestanding' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='mac' INITRAMFS='False' KCONFIG='debian/config/config debian/config/m68k/config debian/config/m68k/config.mac' KERNEL_ARCH='m68k' LOCALVERSION='-mac' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-mac' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real binary-arch-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='m68k' CFLAGS_KERNEL='-ffreestanding' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='mac' INITRAMFS='False' KCONFIG='debian/config/config debian/config/m68k/config debian/config/m68k/config.mac' KERNEL_ARCH='m68k' LOCALVERSION='-mac' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-mac' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' binary-arch_m68k_none_mvme147: binary-arch_m68k_none_mvme147_real binary-arch_m68k_none_mvme147_real:: - $(MAKE) -f debian/rules.real binary-arch-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='m68k' CFLAGS_KERNEL='-ffreestanding' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='mvme147' INITRAMFS='False' KCONFIG='debian/config/config debian/config/m68k/config debian/config/m68k/config.mvme147' KERNEL_ARCH='m68k' LOCALVERSION='-mvme147' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-mvme147' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real binary-arch-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='m68k' CFLAGS_KERNEL='-ffreestanding' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='mvme147' INITRAMFS='False' KCONFIG='debian/config/config debian/config/m68k/config debian/config/m68k/config.mvme147' KERNEL_ARCH='m68k' LOCALVERSION='-mvme147' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-mvme147' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' binary-arch_m68k_none_mvme16x: binary-arch_m68k_none_mvme16x_real binary-arch_m68k_none_mvme16x_real:: - $(MAKE) -f debian/rules.real binary-arch-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='m68k' CFLAGS_KERNEL='-ffreestanding' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='mvme16x' INITRAMFS='False' KCONFIG='debian/config/config debian/config/m68k/config debian/config/m68k/config.mvme16x' KERNEL_ARCH='m68k' LOCALVERSION='-mvme16x' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-mvme16x' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real binary-arch-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='m68k' CFLAGS_KERNEL='-ffreestanding' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='mvme16x' INITRAMFS='False' KCONFIG='debian/config/config debian/config/m68k/config debian/config/m68k/config.mvme16x' KERNEL_ARCH='m68k' LOCALVERSION='-mvme16x' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-mvme16x' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' binary-arch_m68k_none_real:: - $(MAKE) -f debian/rules.real binary-arch-featureset ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='m68k' FEATURESET='none' KERNEL_ARCH='m68k' LOCALVERSION_HEADERS='' SOURCEVERSION='3.2.46-1' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real binary-arch-featureset ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='m68k' FEATURESET='none' KERNEL_ARCH='m68k' LOCALVERSION_HEADERS='' SOURCEVERSION='3.2.46-1+rpi1' UPSTREAMVERSION='3.2' VERSION='3.2' binary-arch_m68k_real:: - $(MAKE) -f debian/rules.real binary-arch-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='m68k' KERNEL_ARCH='m68k' SOURCEVERSION='3.2.46-1' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real binary-arch-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='m68k' KERNEL_ARCH='m68k' SOURCEVERSION='3.2.46-1+rpi1' UPSTREAMVERSION='3.2' VERSION='3.2' binary-arch_mips:: binary-arch_mips_none binary-arch_mips_real binary-arch_mips:: - $(MAKE) -f debian/rules.real install-udeb_mips ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='mips' KERNEL_ARCH='mips' SOURCEVERSION='3.2.46-1' UPSTREAMVERSION='3.2' VERSION='3.2' PACKAGE_NAMES='kernel-image-3.2.0-4-sb1-bcm91250a-di nic-shared-modules-3.2.0-4-sb1-bcm91250a-di ppp-modules-3.2.0-4-sb1-bcm91250a-di cdrom-core-modules-3.2.0-4-sb1-bcm91250a-di scsi-core-modules-3.2.0-4-sb1-bcm91250a-di scsi-modules-3.2.0-4-sb1-bcm91250a-di scsi-common-modules-3.2.0-4-sb1-bcm91250a-di loop-modules-3.2.0-4-sb1-bcm91250a-di ipv6-modules-3.2.0-4-sb1-bcm91250a-di btrfs-modules-3.2.0-4-sb1-bcm91250a-di isofs-modules-3.2.0-4-sb1-bcm91250a-di jfs-modules-3.2.0-4-sb1-bcm91250a-di reiserfs-modules-3.2.0-4-sb1-bcm91250a-di xfs-modules-3.2.0-4-sb1-bcm91250a-di fat-modules-3.2.0-4-sb1-bcm91250a-di md-modules-3.2.0-4-sb1-bcm91250a-di multipath-modules-3.2.0-4-sb1-bcm91250a-di usb-modules-3.2.0-4-sb1-bcm91250a-di usb-storage-modules-3.2.0-4-sb1-bcm91250a-di fb-modules-3.2.0-4-sb1-bcm91250a-di input-modules-3.2.0-4-sb1-bcm91250a-di sata-modules-3.2.0-4-sb1-bcm91250a-di crypto-modules-3.2.0-4-sb1-bcm91250a-di crypto-dm-modules-3.2.0-4-sb1-bcm91250a-di nbd-modules-3.2.0-4-sb1-bcm91250a-di squashfs-modules-3.2.0-4-sb1-bcm91250a-di rtc-modules-3.2.0-4-sb1-bcm91250a-di zlib-modules-3.2.0-4-sb1-bcm91250a-di udf-modules-3.2.0-4-sb1-bcm91250a-di fuse-modules-3.2.0-4-sb1-bcm91250a-di kernel-image-3.2.0-4-r4k-ip22-di nic-shared-modules-3.2.0-4-r4k-ip22-di loop-modules-3.2.0-4-r4k-ip22-di ipv6-modules-3.2.0-4-r4k-ip22-di btrfs-modules-3.2.0-4-r4k-ip22-di isofs-modules-3.2.0-4-r4k-ip22-di jfs-modules-3.2.0-4-r4k-ip22-di reiserfs-modules-3.2.0-4-r4k-ip22-di xfs-modules-3.2.0-4-r4k-ip22-di md-modules-3.2.0-4-r4k-ip22-di multipath-modules-3.2.0-4-r4k-ip22-di crypto-modules-3.2.0-4-r4k-ip22-di crypto-dm-modules-3.2.0-4-r4k-ip22-di nbd-modules-3.2.0-4-r4k-ip22-di squashfs-modules-3.2.0-4-r4k-ip22-di zlib-modules-3.2.0-4-r4k-ip22-di udf-modules-3.2.0-4-r4k-ip22-di fuse-modules-3.2.0-4-r4k-ip22-di kernel-image-3.2.0-4-r5k-ip32-di nic-shared-modules-3.2.0-4-r5k-ip32-di loop-modules-3.2.0-4-r5k-ip32-di ipv6-modules-3.2.0-4-r5k-ip32-di btrfs-modules-3.2.0-4-r5k-ip32-di isofs-modules-3.2.0-4-r5k-ip32-di jfs-modules-3.2.0-4-r5k-ip32-di reiserfs-modules-3.2.0-4-r5k-ip32-di xfs-modules-3.2.0-4-r5k-ip32-di md-modules-3.2.0-4-r5k-ip32-di multipath-modules-3.2.0-4-r5k-ip32-di crypto-modules-3.2.0-4-r5k-ip32-di crypto-dm-modules-3.2.0-4-r5k-ip32-di nbd-modules-3.2.0-4-r5k-ip32-di squashfs-modules-3.2.0-4-r5k-ip32-di zlib-modules-3.2.0-4-r5k-ip32-di udf-modules-3.2.0-4-r5k-ip32-di fuse-modules-3.2.0-4-r5k-ip32-di kernel-image-3.2.0-4-4kc-malta-di ppp-modules-3.2.0-4-4kc-malta-di cdrom-core-modules-3.2.0-4-4kc-malta-di loop-modules-3.2.0-4-4kc-malta-di ipv6-modules-3.2.0-4-4kc-malta-di btrfs-modules-3.2.0-4-4kc-malta-di isofs-modules-3.2.0-4-4kc-malta-di jfs-modules-3.2.0-4-4kc-malta-di reiserfs-modules-3.2.0-4-4kc-malta-di xfs-modules-3.2.0-4-4kc-malta-di fat-modules-3.2.0-4-4kc-malta-di md-modules-3.2.0-4-4kc-malta-di multipath-modules-3.2.0-4-4kc-malta-di usb-modules-3.2.0-4-4kc-malta-di usb-storage-modules-3.2.0-4-4kc-malta-di input-modules-3.2.0-4-4kc-malta-di sata-modules-3.2.0-4-4kc-malta-di crypto-modules-3.2.0-4-4kc-malta-di crypto-dm-modules-3.2.0-4-4kc-malta-di nbd-modules-3.2.0-4-4kc-malta-di squashfs-modules-3.2.0-4-4kc-malta-di virtio-modules-3.2.0-4-4kc-malta-di zlib-modules-3.2.0-4-4kc-malta-di udf-modules-3.2.0-4-4kc-malta-di fuse-modules-3.2.0-4-4kc-malta-di' + $(MAKE) -f debian/rules.real install-udeb_mips ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='mips' KERNEL_ARCH='mips' SOURCEVERSION='3.2.46-1+rpi1' UPSTREAMVERSION='3.2' VERSION='3.2' PACKAGE_NAMES='kernel-image-3.2.0-4-sb1-bcm91250a-di nic-shared-modules-3.2.0-4-sb1-bcm91250a-di ppp-modules-3.2.0-4-sb1-bcm91250a-di cdrom-core-modules-3.2.0-4-sb1-bcm91250a-di scsi-core-modules-3.2.0-4-sb1-bcm91250a-di scsi-modules-3.2.0-4-sb1-bcm91250a-di scsi-common-modules-3.2.0-4-sb1-bcm91250a-di loop-modules-3.2.0-4-sb1-bcm91250a-di ipv6-modules-3.2.0-4-sb1-bcm91250a-di btrfs-modules-3.2.0-4-sb1-bcm91250a-di isofs-modules-3.2.0-4-sb1-bcm91250a-di jfs-modules-3.2.0-4-sb1-bcm91250a-di reiserfs-modules-3.2.0-4-sb1-bcm91250a-di xfs-modules-3.2.0-4-sb1-bcm91250a-di fat-modules-3.2.0-4-sb1-bcm91250a-di md-modules-3.2.0-4-sb1-bcm91250a-di multipath-modules-3.2.0-4-sb1-bcm91250a-di usb-modules-3.2.0-4-sb1-bcm91250a-di usb-storage-modules-3.2.0-4-sb1-bcm91250a-di fb-modules-3.2.0-4-sb1-bcm91250a-di input-modules-3.2.0-4-sb1-bcm91250a-di sata-modules-3.2.0-4-sb1-bcm91250a-di crypto-modules-3.2.0-4-sb1-bcm91250a-di crypto-dm-modules-3.2.0-4-sb1-bcm91250a-di nbd-modules-3.2.0-4-sb1-bcm91250a-di squashfs-modules-3.2.0-4-sb1-bcm91250a-di rtc-modules-3.2.0-4-sb1-bcm91250a-di zlib-modules-3.2.0-4-sb1-bcm91250a-di udf-modules-3.2.0-4-sb1-bcm91250a-di fuse-modules-3.2.0-4-sb1-bcm91250a-di kernel-image-3.2.0-4-r4k-ip22-di nic-shared-modules-3.2.0-4-r4k-ip22-di loop-modules-3.2.0-4-r4k-ip22-di ipv6-modules-3.2.0-4-r4k-ip22-di btrfs-modules-3.2.0-4-r4k-ip22-di isofs-modules-3.2.0-4-r4k-ip22-di jfs-modules-3.2.0-4-r4k-ip22-di reiserfs-modules-3.2.0-4-r4k-ip22-di xfs-modules-3.2.0-4-r4k-ip22-di md-modules-3.2.0-4-r4k-ip22-di multipath-modules-3.2.0-4-r4k-ip22-di crypto-modules-3.2.0-4-r4k-ip22-di crypto-dm-modules-3.2.0-4-r4k-ip22-di nbd-modules-3.2.0-4-r4k-ip22-di squashfs-modules-3.2.0-4-r4k-ip22-di zlib-modules-3.2.0-4-r4k-ip22-di udf-modules-3.2.0-4-r4k-ip22-di fuse-modules-3.2.0-4-r4k-ip22-di kernel-image-3.2.0-4-r5k-ip32-di nic-shared-modules-3.2.0-4-r5k-ip32-di loop-modules-3.2.0-4-r5k-ip32-di ipv6-modules-3.2.0-4-r5k-ip32-di btrfs-modules-3.2.0-4-r5k-ip32-di isofs-modules-3.2.0-4-r5k-ip32-di jfs-modules-3.2.0-4-r5k-ip32-di reiserfs-modules-3.2.0-4-r5k-ip32-di xfs-modules-3.2.0-4-r5k-ip32-di md-modules-3.2.0-4-r5k-ip32-di multipath-modules-3.2.0-4-r5k-ip32-di crypto-modules-3.2.0-4-r5k-ip32-di crypto-dm-modules-3.2.0-4-r5k-ip32-di nbd-modules-3.2.0-4-r5k-ip32-di squashfs-modules-3.2.0-4-r5k-ip32-di zlib-modules-3.2.0-4-r5k-ip32-di udf-modules-3.2.0-4-r5k-ip32-di fuse-modules-3.2.0-4-r5k-ip32-di kernel-image-3.2.0-4-4kc-malta-di ppp-modules-3.2.0-4-4kc-malta-di cdrom-core-modules-3.2.0-4-4kc-malta-di loop-modules-3.2.0-4-4kc-malta-di ipv6-modules-3.2.0-4-4kc-malta-di btrfs-modules-3.2.0-4-4kc-malta-di isofs-modules-3.2.0-4-4kc-malta-di jfs-modules-3.2.0-4-4kc-malta-di reiserfs-modules-3.2.0-4-4kc-malta-di xfs-modules-3.2.0-4-4kc-malta-di fat-modules-3.2.0-4-4kc-malta-di md-modules-3.2.0-4-4kc-malta-di multipath-modules-3.2.0-4-4kc-malta-di usb-modules-3.2.0-4-4kc-malta-di usb-storage-modules-3.2.0-4-4kc-malta-di input-modules-3.2.0-4-4kc-malta-di sata-modules-3.2.0-4-4kc-malta-di crypto-modules-3.2.0-4-4kc-malta-di crypto-dm-modules-3.2.0-4-4kc-malta-di nbd-modules-3.2.0-4-4kc-malta-di squashfs-modules-3.2.0-4-4kc-malta-di virtio-modules-3.2.0-4-4kc-malta-di zlib-modules-3.2.0-4-4kc-malta-di udf-modules-3.2.0-4-4kc-malta-di fuse-modules-3.2.0-4-4kc-malta-di' binary-arch_mips_none: binary-arch_mips_none_4kc-malta binary-arch_mips_none_5kc-malta binary-arch_mips_none_octeon binary-arch_mips_none_r4k-ip22 binary-arch_mips_none_r5k-ip32 binary-arch_mips_none_real binary-arch_mips_none_sb1-bcm91250a binary-arch_mips_none_sb1a-bcm91480b binary-arch_mips_none_4kc-malta: binary-arch_mips_none_4kc-malta_real binary-arch_mips_none_4kc-malta_real:: - $(MAKE) -f debian/rules.real binary-arch-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='mips' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='4kc-malta' INITRAMFS='False' KCONFIG='debian/config/config debian/config/kernelarch-mips/config debian/config/mips/config debian/config/mips/config.4kc-malta' KERNEL_ARCH='mips' LOCALVERSION='-4kc-malta' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-4kc-malta' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real binary-arch-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='mips' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='4kc-malta' INITRAMFS='False' KCONFIG='debian/config/config debian/config/kernelarch-mips/config debian/config/mips/config debian/config/mips/config.4kc-malta' KERNEL_ARCH='mips' LOCALVERSION='-4kc-malta' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-4kc-malta' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' binary-arch_mips_none_5kc-malta: binary-arch_mips_none_5kc-malta_real binary-arch_mips_none_5kc-malta_real:: - $(MAKE) -f debian/rules.real binary-arch-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='mips' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='5kc-malta' INITRAMFS='False' KCONFIG='debian/config/config debian/config/kernelarch-mips/config debian/config/mips/config debian/config/mips/config.5kc-malta' KERNEL_ARCH='mips' LOCALVERSION='-5kc-malta' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-5kc-malta' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real binary-arch-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='mips' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='5kc-malta' INITRAMFS='False' KCONFIG='debian/config/config debian/config/kernelarch-mips/config debian/config/mips/config debian/config/mips/config.5kc-malta' KERNEL_ARCH='mips' LOCALVERSION='-5kc-malta' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-5kc-malta' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' binary-arch_mips_none_octeon: binary-arch_mips_none_octeon_real binary-arch_mips_none_octeon_real:: - $(MAKE) -f debian/rules.real binary-arch-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='mips' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='octeon' INITRAMFS='False' KCONFIG='debian/config/config debian/config/kernelarch-mips/config debian/config/mips/config debian/config/mips/config.octeon' KERNEL_ARCH='mips' LOCALVERSION='-octeon' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-octeon' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real binary-arch-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='mips' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='octeon' INITRAMFS='False' KCONFIG='debian/config/config debian/config/kernelarch-mips/config debian/config/mips/config debian/config/mips/config.octeon' KERNEL_ARCH='mips' LOCALVERSION='-octeon' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-octeon' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' binary-arch_mips_none_r4k-ip22: binary-arch_mips_none_r4k-ip22_real binary-arch_mips_none_r4k-ip22_real:: - $(MAKE) -f debian/rules.real binary-arch-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='mips' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='r4k-ip22' INITRAMFS='False' KCONFIG='debian/config/config debian/config/kernelarch-mips/config debian/config/mips/config debian/config/mips/config.r4k-ip22' KERNEL_ARCH='mips' LOCALVERSION='-r4k-ip22' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-r4k-ip22' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real binary-arch-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='mips' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='r4k-ip22' INITRAMFS='False' KCONFIG='debian/config/config debian/config/kernelarch-mips/config debian/config/mips/config debian/config/mips/config.r4k-ip22' KERNEL_ARCH='mips' LOCALVERSION='-r4k-ip22' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-r4k-ip22' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' binary-arch_mips_none_r5k-ip32: binary-arch_mips_none_r5k-ip32_real binary-arch_mips_none_r5k-ip32_real:: - $(MAKE) -f debian/rules.real binary-arch-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='mips' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='r5k-ip32' INITRAMFS='False' KCONFIG='debian/config/config debian/config/kernelarch-mips/config debian/config/mips/config debian/config/mips/config.r5k-ip32' KERNEL_ARCH='mips' LOCALVERSION='-r5k-ip32' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-r5k-ip32' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real binary-arch-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='mips' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='r5k-ip32' INITRAMFS='False' KCONFIG='debian/config/config debian/config/kernelarch-mips/config debian/config/mips/config debian/config/mips/config.r5k-ip32' KERNEL_ARCH='mips' LOCALVERSION='-r5k-ip32' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-r5k-ip32' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' binary-arch_mips_none_real:: - $(MAKE) -f debian/rules.real binary-arch-featureset ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='mips' FEATURESET='none' KERNEL_ARCH='mips' LOCALVERSION_HEADERS='' SOURCEVERSION='3.2.46-1' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real binary-arch-featureset ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='mips' FEATURESET='none' KERNEL_ARCH='mips' LOCALVERSION_HEADERS='' SOURCEVERSION='3.2.46-1+rpi1' UPSTREAMVERSION='3.2' VERSION='3.2' binary-arch_mips_none_sb1-bcm91250a: binary-arch_mips_none_sb1-bcm91250a_real binary-arch_mips_none_sb1-bcm91250a_real:: - $(MAKE) -f debian/rules.real binary-arch-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='mips' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='sb1-bcm91250a' INITRAMFS='False' KCONFIG='debian/config/config debian/config/kernelarch-mips/config debian/config/mips/config debian/config/mips/config.sb1-bcm91250a' KERNEL_ARCH='mips' LOCALVERSION='-sb1-bcm91250a' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-sb1-bcm91250a' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real binary-arch-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='mips' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='sb1-bcm91250a' INITRAMFS='False' KCONFIG='debian/config/config debian/config/kernelarch-mips/config debian/config/mips/config debian/config/mips/config.sb1-bcm91250a' KERNEL_ARCH='mips' LOCALVERSION='-sb1-bcm91250a' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-sb1-bcm91250a' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' binary-arch_mips_none_sb1a-bcm91480b: binary-arch_mips_none_sb1a-bcm91480b_real binary-arch_mips_none_sb1a-bcm91480b_real:: - $(MAKE) -f debian/rules.real binary-arch-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='mips' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='sb1a-bcm91480b' INITRAMFS='False' KCONFIG='debian/config/config debian/config/kernelarch-mips/config debian/config/mips/config debian/config/mips/config.sb1a-bcm91480b' KERNEL_ARCH='mips' LOCALVERSION='-sb1a-bcm91480b' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-sb1a-bcm91480b' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real binary-arch-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='mips' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='sb1a-bcm91480b' INITRAMFS='False' KCONFIG='debian/config/config debian/config/kernelarch-mips/config debian/config/mips/config debian/config/mips/config.sb1a-bcm91480b' KERNEL_ARCH='mips' LOCALVERSION='-sb1a-bcm91480b' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-sb1a-bcm91480b' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' binary-arch_mips_real:: - $(MAKE) -f debian/rules.real binary-arch-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='mips' KERNEL_ARCH='mips' SOURCEVERSION='3.2.46-1' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real binary-arch-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='mips' KERNEL_ARCH='mips' SOURCEVERSION='3.2.46-1+rpi1' UPSTREAMVERSION='3.2' VERSION='3.2' binary-arch_mipsel:: binary-arch_mipsel_none binary-arch_mipsel_real binary-arch_mipsel:: - $(MAKE) -f debian/rules.real install-udeb_mipsel ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='mipsel' KERNEL_ARCH='mips' SOURCEVERSION='3.2.46-1' UPSTREAMVERSION='3.2' VERSION='3.2' PACKAGE_NAMES='kernel-image-3.2.0-4-sb1-bcm91250a-di nic-shared-modules-3.2.0-4-sb1-bcm91250a-di ppp-modules-3.2.0-4-sb1-bcm91250a-di cdrom-core-modules-3.2.0-4-sb1-bcm91250a-di scsi-core-modules-3.2.0-4-sb1-bcm91250a-di scsi-modules-3.2.0-4-sb1-bcm91250a-di scsi-common-modules-3.2.0-4-sb1-bcm91250a-di loop-modules-3.2.0-4-sb1-bcm91250a-di ipv6-modules-3.2.0-4-sb1-bcm91250a-di btrfs-modules-3.2.0-4-sb1-bcm91250a-di isofs-modules-3.2.0-4-sb1-bcm91250a-di jfs-modules-3.2.0-4-sb1-bcm91250a-di reiserfs-modules-3.2.0-4-sb1-bcm91250a-di xfs-modules-3.2.0-4-sb1-bcm91250a-di fat-modules-3.2.0-4-sb1-bcm91250a-di md-modules-3.2.0-4-sb1-bcm91250a-di multipath-modules-3.2.0-4-sb1-bcm91250a-di usb-modules-3.2.0-4-sb1-bcm91250a-di usb-storage-modules-3.2.0-4-sb1-bcm91250a-di fb-modules-3.2.0-4-sb1-bcm91250a-di input-modules-3.2.0-4-sb1-bcm91250a-di sata-modules-3.2.0-4-sb1-bcm91250a-di crypto-modules-3.2.0-4-sb1-bcm91250a-di crypto-dm-modules-3.2.0-4-sb1-bcm91250a-di nbd-modules-3.2.0-4-sb1-bcm91250a-di squashfs-modules-3.2.0-4-sb1-bcm91250a-di rtc-modules-3.2.0-4-sb1-bcm91250a-di zlib-modules-3.2.0-4-sb1-bcm91250a-di udf-modules-3.2.0-4-sb1-bcm91250a-di fuse-modules-3.2.0-4-sb1-bcm91250a-di kernel-image-3.2.0-4-r5k-cobalt-di nic-shared-modules-3.2.0-4-r5k-cobalt-di ppp-modules-3.2.0-4-r5k-cobalt-di loop-modules-3.2.0-4-r5k-cobalt-di ipv6-modules-3.2.0-4-r5k-cobalt-di btrfs-modules-3.2.0-4-r5k-cobalt-di jfs-modules-3.2.0-4-r5k-cobalt-di reiserfs-modules-3.2.0-4-r5k-cobalt-di xfs-modules-3.2.0-4-r5k-cobalt-di fat-modules-3.2.0-4-r5k-cobalt-di nfs-modules-3.2.0-4-r5k-cobalt-di md-modules-3.2.0-4-r5k-cobalt-di multipath-modules-3.2.0-4-r5k-cobalt-di crypto-modules-3.2.0-4-r5k-cobalt-di crypto-dm-modules-3.2.0-4-r5k-cobalt-di nbd-modules-3.2.0-4-r5k-cobalt-di squashfs-modules-3.2.0-4-r5k-cobalt-di zlib-modules-3.2.0-4-r5k-cobalt-di fuse-modules-3.2.0-4-r5k-cobalt-di kernel-image-3.2.0-4-4kc-malta-di ppp-modules-3.2.0-4-4kc-malta-di cdrom-core-modules-3.2.0-4-4kc-malta-di loop-modules-3.2.0-4-4kc-malta-di ipv6-modules-3.2.0-4-4kc-malta-di btrfs-modules-3.2.0-4-4kc-malta-di isofs-modules-3.2.0-4-4kc-malta-di jfs-modules-3.2.0-4-4kc-malta-di reiserfs-modules-3.2.0-4-4kc-malta-di xfs-modules-3.2.0-4-4kc-malta-di fat-modules-3.2.0-4-4kc-malta-di md-modules-3.2.0-4-4kc-malta-di multipath-modules-3.2.0-4-4kc-malta-di usb-modules-3.2.0-4-4kc-malta-di usb-storage-modules-3.2.0-4-4kc-malta-di input-modules-3.2.0-4-4kc-malta-di sata-modules-3.2.0-4-4kc-malta-di crypto-modules-3.2.0-4-4kc-malta-di crypto-dm-modules-3.2.0-4-4kc-malta-di nbd-modules-3.2.0-4-4kc-malta-di squashfs-modules-3.2.0-4-4kc-malta-di virtio-modules-3.2.0-4-4kc-malta-di zlib-modules-3.2.0-4-4kc-malta-di udf-modules-3.2.0-4-4kc-malta-di fuse-modules-3.2.0-4-4kc-malta-di kernel-image-3.2.0-4-loongson-2f-di nic-modules-3.2.0-4-loongson-2f-di nic-shared-modules-3.2.0-4-loongson-2f-di ppp-modules-3.2.0-4-loongson-2f-di cdrom-core-modules-3.2.0-4-loongson-2f-di loop-modules-3.2.0-4-loongson-2f-di ipv6-modules-3.2.0-4-loongson-2f-di btrfs-modules-3.2.0-4-loongson-2f-di isofs-modules-3.2.0-4-loongson-2f-di jfs-modules-3.2.0-4-loongson-2f-di reiserfs-modules-3.2.0-4-loongson-2f-di xfs-modules-3.2.0-4-loongson-2f-di fat-modules-3.2.0-4-loongson-2f-di md-modules-3.2.0-4-loongson-2f-di multipath-modules-3.2.0-4-loongson-2f-di usb-modules-3.2.0-4-loongson-2f-di usb-storage-modules-3.2.0-4-loongson-2f-di input-modules-3.2.0-4-loongson-2f-di nic-usb-modules-3.2.0-4-loongson-2f-di sata-modules-3.2.0-4-loongson-2f-di crypto-modules-3.2.0-4-loongson-2f-di crypto-dm-modules-3.2.0-4-loongson-2f-di nbd-modules-3.2.0-4-loongson-2f-di squashfs-modules-3.2.0-4-loongson-2f-di virtio-modules-3.2.0-4-loongson-2f-di zlib-modules-3.2.0-4-loongson-2f-di udf-modules-3.2.0-4-loongson-2f-di fuse-modules-3.2.0-4-loongson-2f-di' + $(MAKE) -f debian/rules.real install-udeb_mipsel ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='mipsel' KERNEL_ARCH='mips' SOURCEVERSION='3.2.46-1+rpi1' UPSTREAMVERSION='3.2' VERSION='3.2' PACKAGE_NAMES='kernel-image-3.2.0-4-sb1-bcm91250a-di nic-shared-modules-3.2.0-4-sb1-bcm91250a-di ppp-modules-3.2.0-4-sb1-bcm91250a-di cdrom-core-modules-3.2.0-4-sb1-bcm91250a-di scsi-core-modules-3.2.0-4-sb1-bcm91250a-di scsi-modules-3.2.0-4-sb1-bcm91250a-di scsi-common-modules-3.2.0-4-sb1-bcm91250a-di loop-modules-3.2.0-4-sb1-bcm91250a-di ipv6-modules-3.2.0-4-sb1-bcm91250a-di btrfs-modules-3.2.0-4-sb1-bcm91250a-di isofs-modules-3.2.0-4-sb1-bcm91250a-di jfs-modules-3.2.0-4-sb1-bcm91250a-di reiserfs-modules-3.2.0-4-sb1-bcm91250a-di xfs-modules-3.2.0-4-sb1-bcm91250a-di fat-modules-3.2.0-4-sb1-bcm91250a-di md-modules-3.2.0-4-sb1-bcm91250a-di multipath-modules-3.2.0-4-sb1-bcm91250a-di usb-modules-3.2.0-4-sb1-bcm91250a-di usb-storage-modules-3.2.0-4-sb1-bcm91250a-di fb-modules-3.2.0-4-sb1-bcm91250a-di input-modules-3.2.0-4-sb1-bcm91250a-di sata-modules-3.2.0-4-sb1-bcm91250a-di crypto-modules-3.2.0-4-sb1-bcm91250a-di crypto-dm-modules-3.2.0-4-sb1-bcm91250a-di nbd-modules-3.2.0-4-sb1-bcm91250a-di squashfs-modules-3.2.0-4-sb1-bcm91250a-di rtc-modules-3.2.0-4-sb1-bcm91250a-di zlib-modules-3.2.0-4-sb1-bcm91250a-di udf-modules-3.2.0-4-sb1-bcm91250a-di fuse-modules-3.2.0-4-sb1-bcm91250a-di kernel-image-3.2.0-4-r5k-cobalt-di nic-shared-modules-3.2.0-4-r5k-cobalt-di ppp-modules-3.2.0-4-r5k-cobalt-di loop-modules-3.2.0-4-r5k-cobalt-di ipv6-modules-3.2.0-4-r5k-cobalt-di btrfs-modules-3.2.0-4-r5k-cobalt-di jfs-modules-3.2.0-4-r5k-cobalt-di reiserfs-modules-3.2.0-4-r5k-cobalt-di xfs-modules-3.2.0-4-r5k-cobalt-di fat-modules-3.2.0-4-r5k-cobalt-di nfs-modules-3.2.0-4-r5k-cobalt-di md-modules-3.2.0-4-r5k-cobalt-di multipath-modules-3.2.0-4-r5k-cobalt-di crypto-modules-3.2.0-4-r5k-cobalt-di crypto-dm-modules-3.2.0-4-r5k-cobalt-di nbd-modules-3.2.0-4-r5k-cobalt-di squashfs-modules-3.2.0-4-r5k-cobalt-di zlib-modules-3.2.0-4-r5k-cobalt-di fuse-modules-3.2.0-4-r5k-cobalt-di kernel-image-3.2.0-4-4kc-malta-di ppp-modules-3.2.0-4-4kc-malta-di cdrom-core-modules-3.2.0-4-4kc-malta-di loop-modules-3.2.0-4-4kc-malta-di ipv6-modules-3.2.0-4-4kc-malta-di btrfs-modules-3.2.0-4-4kc-malta-di isofs-modules-3.2.0-4-4kc-malta-di jfs-modules-3.2.0-4-4kc-malta-di reiserfs-modules-3.2.0-4-4kc-malta-di xfs-modules-3.2.0-4-4kc-malta-di fat-modules-3.2.0-4-4kc-malta-di md-modules-3.2.0-4-4kc-malta-di multipath-modules-3.2.0-4-4kc-malta-di usb-modules-3.2.0-4-4kc-malta-di usb-storage-modules-3.2.0-4-4kc-malta-di input-modules-3.2.0-4-4kc-malta-di sata-modules-3.2.0-4-4kc-malta-di crypto-modules-3.2.0-4-4kc-malta-di crypto-dm-modules-3.2.0-4-4kc-malta-di nbd-modules-3.2.0-4-4kc-malta-di squashfs-modules-3.2.0-4-4kc-malta-di virtio-modules-3.2.0-4-4kc-malta-di zlib-modules-3.2.0-4-4kc-malta-di udf-modules-3.2.0-4-4kc-malta-di fuse-modules-3.2.0-4-4kc-malta-di kernel-image-3.2.0-4-loongson-2f-di nic-modules-3.2.0-4-loongson-2f-di nic-shared-modules-3.2.0-4-loongson-2f-di ppp-modules-3.2.0-4-loongson-2f-di cdrom-core-modules-3.2.0-4-loongson-2f-di loop-modules-3.2.0-4-loongson-2f-di ipv6-modules-3.2.0-4-loongson-2f-di btrfs-modules-3.2.0-4-loongson-2f-di isofs-modules-3.2.0-4-loongson-2f-di jfs-modules-3.2.0-4-loongson-2f-di reiserfs-modules-3.2.0-4-loongson-2f-di xfs-modules-3.2.0-4-loongson-2f-di fat-modules-3.2.0-4-loongson-2f-di md-modules-3.2.0-4-loongson-2f-di multipath-modules-3.2.0-4-loongson-2f-di usb-modules-3.2.0-4-loongson-2f-di usb-storage-modules-3.2.0-4-loongson-2f-di input-modules-3.2.0-4-loongson-2f-di nic-usb-modules-3.2.0-4-loongson-2f-di sata-modules-3.2.0-4-loongson-2f-di crypto-modules-3.2.0-4-loongson-2f-di crypto-dm-modules-3.2.0-4-loongson-2f-di nbd-modules-3.2.0-4-loongson-2f-di squashfs-modules-3.2.0-4-loongson-2f-di virtio-modules-3.2.0-4-loongson-2f-di zlib-modules-3.2.0-4-loongson-2f-di udf-modules-3.2.0-4-loongson-2f-di fuse-modules-3.2.0-4-loongson-2f-di' binary-arch_mipsel_none: binary-arch_mipsel_none_4kc-malta binary-arch_mipsel_none_5kc-malta binary-arch_mipsel_none_loongson-2f binary-arch_mipsel_none_r5k-cobalt binary-arch_mipsel_none_real binary-arch_mipsel_none_sb1-bcm91250a binary-arch_mipsel_none_sb1a-bcm91480b binary-arch_mipsel_none_4kc-malta: binary-arch_mipsel_none_4kc-malta_real binary-arch_mipsel_none_4kc-malta_real:: - $(MAKE) -f debian/rules.real binary-arch-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='mipsel' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='4kc-malta' INITRAMFS='False' KCONFIG='debian/config/config debian/config/kernelarch-mips/config debian/config/mipsel/config debian/config/mips/config.4kc-malta' KERNEL_ARCH='mips' LOCALVERSION='-4kc-malta' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-4kc-malta' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real binary-arch-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='mipsel' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='4kc-malta' INITRAMFS='False' KCONFIG='debian/config/config debian/config/kernelarch-mips/config debian/config/mipsel/config debian/config/mips/config.4kc-malta' KERNEL_ARCH='mips' LOCALVERSION='-4kc-malta' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-4kc-malta' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' binary-arch_mipsel_none_5kc-malta: binary-arch_mipsel_none_5kc-malta_real binary-arch_mipsel_none_5kc-malta_real:: - $(MAKE) -f debian/rules.real binary-arch-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='mipsel' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='5kc-malta' INITRAMFS='False' KCONFIG='debian/config/config debian/config/kernelarch-mips/config debian/config/mipsel/config debian/config/mips/config.5kc-malta' KERNEL_ARCH='mips' LOCALVERSION='-5kc-malta' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-5kc-malta' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real binary-arch-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='mipsel' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='5kc-malta' INITRAMFS='False' KCONFIG='debian/config/config debian/config/kernelarch-mips/config debian/config/mipsel/config debian/config/mips/config.5kc-malta' KERNEL_ARCH='mips' LOCALVERSION='-5kc-malta' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-5kc-malta' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' binary-arch_mipsel_none_loongson-2f: binary-arch_mipsel_none_loongson-2f_real binary-arch_mipsel_none_loongson-2f_real:: - $(MAKE) -f debian/rules.real binary-arch-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='mipsel' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='loongson-2f' INITRAMFS='False' KCONFIG='debian/config/config debian/config/kernelarch-mips/config debian/config/mipsel/config debian/config/mipsel/config.loongson-2f' KERNEL_ARCH='mips' LOCALVERSION='-loongson-2f' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-loongson-2f' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real binary-arch-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='mipsel' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='loongson-2f' INITRAMFS='False' KCONFIG='debian/config/config debian/config/kernelarch-mips/config debian/config/mipsel/config debian/config/mipsel/config.loongson-2f' KERNEL_ARCH='mips' LOCALVERSION='-loongson-2f' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-loongson-2f' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' binary-arch_mipsel_none_r5k-cobalt: binary-arch_mipsel_none_r5k-cobalt_real binary-arch_mipsel_none_r5k-cobalt_real:: - $(MAKE) -f debian/rules.real binary-arch-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='mipsel' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='r5k-cobalt' INITRAMFS='False' KCONFIG='debian/config/config debian/config/kernelarch-mips/config debian/config/mipsel/config debian/config/mipsel/config.r5k-cobalt' KERNEL_ARCH='mips' LOCALVERSION='-r5k-cobalt' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-r5k-cobalt' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real binary-arch-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='mipsel' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='r5k-cobalt' INITRAMFS='False' KCONFIG='debian/config/config debian/config/kernelarch-mips/config debian/config/mipsel/config debian/config/mipsel/config.r5k-cobalt' KERNEL_ARCH='mips' LOCALVERSION='-r5k-cobalt' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-r5k-cobalt' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' binary-arch_mipsel_none_real:: - $(MAKE) -f debian/rules.real binary-arch-featureset ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='mipsel' FEATURESET='none' KERNEL_ARCH='mips' LOCALVERSION_HEADERS='' SOURCEVERSION='3.2.46-1' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real binary-arch-featureset ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='mipsel' FEATURESET='none' KERNEL_ARCH='mips' LOCALVERSION_HEADERS='' SOURCEVERSION='3.2.46-1+rpi1' UPSTREAMVERSION='3.2' VERSION='3.2' binary-arch_mipsel_none_sb1-bcm91250a: binary-arch_mipsel_none_sb1-bcm91250a_real binary-arch_mipsel_none_sb1-bcm91250a_real:: - $(MAKE) -f debian/rules.real binary-arch-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='mipsel' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='sb1-bcm91250a' INITRAMFS='False' KCONFIG='debian/config/config debian/config/kernelarch-mips/config debian/config/mipsel/config debian/config/mips/config.sb1-bcm91250a' KERNEL_ARCH='mips' LOCALVERSION='-sb1-bcm91250a' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-sb1-bcm91250a' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real binary-arch-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='mipsel' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='sb1-bcm91250a' INITRAMFS='False' KCONFIG='debian/config/config debian/config/kernelarch-mips/config debian/config/mipsel/config debian/config/mips/config.sb1-bcm91250a' KERNEL_ARCH='mips' LOCALVERSION='-sb1-bcm91250a' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-sb1-bcm91250a' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' binary-arch_mipsel_none_sb1a-bcm91480b: binary-arch_mipsel_none_sb1a-bcm91480b_real binary-arch_mipsel_none_sb1a-bcm91480b_real:: - $(MAKE) -f debian/rules.real binary-arch-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='mipsel' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='sb1a-bcm91480b' INITRAMFS='False' KCONFIG='debian/config/config debian/config/kernelarch-mips/config debian/config/mipsel/config debian/config/mips/config.sb1a-bcm91480b' KERNEL_ARCH='mips' LOCALVERSION='-sb1a-bcm91480b' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-sb1a-bcm91480b' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real binary-arch-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='mipsel' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='sb1a-bcm91480b' INITRAMFS='False' KCONFIG='debian/config/config debian/config/kernelarch-mips/config debian/config/mipsel/config debian/config/mips/config.sb1a-bcm91480b' KERNEL_ARCH='mips' LOCALVERSION='-sb1a-bcm91480b' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-sb1a-bcm91480b' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' binary-arch_mipsel_real:: - $(MAKE) -f debian/rules.real binary-arch-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='mipsel' KERNEL_ARCH='mips' SOURCEVERSION='3.2.46-1' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real binary-arch-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='mipsel' KERNEL_ARCH='mips' SOURCEVERSION='3.2.46-1+rpi1' UPSTREAMVERSION='3.2' VERSION='3.2' binary-arch_powerpc:: binary-arch_powerpc_none binary-arch_powerpc_real binary-arch_powerpc:: - $(MAKE) -f debian/rules.real install-udeb_powerpc ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='powerpc' KERNEL_ARCH='powerpc' SOURCEVERSION='3.2.46-1' UPSTREAMVERSION='3.2' VERSION='3.2' PACKAGE_NAMES='kernel-image-3.2.0-4-powerpc-di nic-modules-3.2.0-4-powerpc-di nic-extra-modules-3.2.0-4-powerpc-di nic-shared-modules-3.2.0-4-powerpc-di serial-modules-3.2.0-4-powerpc-di usb-serial-modules-3.2.0-4-powerpc-di ppp-modules-3.2.0-4-powerpc-di pata-modules-3.2.0-4-powerpc-di cdrom-core-modules-3.2.0-4-powerpc-di firewire-core-modules-3.2.0-4-powerpc-di scsi-core-modules-3.2.0-4-powerpc-di scsi-modules-3.2.0-4-powerpc-di scsi-common-modules-3.2.0-4-powerpc-di scsi-extra-modules-3.2.0-4-powerpc-di floppy-modules-3.2.0-4-powerpc-di loop-modules-3.2.0-4-powerpc-di btrfs-modules-3.2.0-4-powerpc-di ext2-modules-3.2.0-4-powerpc-di ext3-modules-3.2.0-4-powerpc-di ext4-modules-3.2.0-4-powerpc-di isofs-modules-3.2.0-4-powerpc-di jfs-modules-3.2.0-4-powerpc-di reiserfs-modules-3.2.0-4-powerpc-di xfs-modules-3.2.0-4-powerpc-di fat-modules-3.2.0-4-powerpc-di hfs-modules-3.2.0-4-powerpc-di affs-modules-3.2.0-4-powerpc-di ufs-modules-3.2.0-4-powerpc-di md-modules-3.2.0-4-powerpc-di multipath-modules-3.2.0-4-powerpc-di usb-modules-3.2.0-4-powerpc-di usb-storage-modules-3.2.0-4-powerpc-di pcmcia-storage-modules-3.2.0-4-powerpc-di input-modules-3.2.0-4-powerpc-di event-modules-3.2.0-4-powerpc-di mouse-modules-3.2.0-4-powerpc-di irda-modules-3.2.0-4-powerpc-di nic-pcmcia-modules-3.2.0-4-powerpc-di pcmcia-modules-3.2.0-4-powerpc-di sata-modules-3.2.0-4-powerpc-di core-modules-3.2.0-4-powerpc-di crc-modules-3.2.0-4-powerpc-di crypto-modules-3.2.0-4-powerpc-di crypto-dm-modules-3.2.0-4-powerpc-di ata-modules-3.2.0-4-powerpc-di nbd-modules-3.2.0-4-powerpc-di squashfs-modules-3.2.0-4-powerpc-di virtio-modules-3.2.0-4-powerpc-di uinput-modules-3.2.0-4-powerpc-di zlib-modules-3.2.0-4-powerpc-di udf-modules-3.2.0-4-powerpc-di fuse-modules-3.2.0-4-powerpc-di kernel-image-3.2.0-4-powerpc64-di nic-modules-3.2.0-4-powerpc64-di nic-extra-modules-3.2.0-4-powerpc64-di nic-shared-modules-3.2.0-4-powerpc64-di serial-modules-3.2.0-4-powerpc64-di usb-serial-modules-3.2.0-4-powerpc64-di ppp-modules-3.2.0-4-powerpc64-di pata-modules-3.2.0-4-powerpc64-di cdrom-core-modules-3.2.0-4-powerpc64-di firewire-core-modules-3.2.0-4-powerpc64-di scsi-core-modules-3.2.0-4-powerpc64-di scsi-modules-3.2.0-4-powerpc64-di scsi-common-modules-3.2.0-4-powerpc64-di scsi-extra-modules-3.2.0-4-powerpc64-di floppy-modules-3.2.0-4-powerpc64-di loop-modules-3.2.0-4-powerpc64-di btrfs-modules-3.2.0-4-powerpc64-di ext2-modules-3.2.0-4-powerpc64-di ext3-modules-3.2.0-4-powerpc64-di ext4-modules-3.2.0-4-powerpc64-di isofs-modules-3.2.0-4-powerpc64-di jfs-modules-3.2.0-4-powerpc64-di reiserfs-modules-3.2.0-4-powerpc64-di xfs-modules-3.2.0-4-powerpc64-di fat-modules-3.2.0-4-powerpc64-di hfs-modules-3.2.0-4-powerpc64-di affs-modules-3.2.0-4-powerpc64-di ufs-modules-3.2.0-4-powerpc64-di md-modules-3.2.0-4-powerpc64-di multipath-modules-3.2.0-4-powerpc64-di usb-modules-3.2.0-4-powerpc64-di usb-storage-modules-3.2.0-4-powerpc64-di pcmcia-storage-modules-3.2.0-4-powerpc64-di input-modules-3.2.0-4-powerpc64-di event-modules-3.2.0-4-powerpc64-di mouse-modules-3.2.0-4-powerpc64-di irda-modules-3.2.0-4-powerpc64-di nic-pcmcia-modules-3.2.0-4-powerpc64-di pcmcia-modules-3.2.0-4-powerpc64-di sata-modules-3.2.0-4-powerpc64-di core-modules-3.2.0-4-powerpc64-di crc-modules-3.2.0-4-powerpc64-di crypto-modules-3.2.0-4-powerpc64-di crypto-dm-modules-3.2.0-4-powerpc64-di ata-modules-3.2.0-4-powerpc64-di nbd-modules-3.2.0-4-powerpc64-di squashfs-modules-3.2.0-4-powerpc64-di virtio-modules-3.2.0-4-powerpc64-di uinput-modules-3.2.0-4-powerpc64-di udf-modules-3.2.0-4-powerpc64-di fuse-modules-3.2.0-4-powerpc64-di hypervisor-modules-3.2.0-4-powerpc64-di fancontrol-modules-3.2.0-4-powerpc64-di' + $(MAKE) -f debian/rules.real install-udeb_powerpc ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='powerpc' KERNEL_ARCH='powerpc' SOURCEVERSION='3.2.46-1+rpi1' UPSTREAMVERSION='3.2' VERSION='3.2' PACKAGE_NAMES='kernel-image-3.2.0-4-powerpc-di nic-modules-3.2.0-4-powerpc-di nic-extra-modules-3.2.0-4-powerpc-di nic-shared-modules-3.2.0-4-powerpc-di serial-modules-3.2.0-4-powerpc-di usb-serial-modules-3.2.0-4-powerpc-di ppp-modules-3.2.0-4-powerpc-di pata-modules-3.2.0-4-powerpc-di cdrom-core-modules-3.2.0-4-powerpc-di firewire-core-modules-3.2.0-4-powerpc-di scsi-core-modules-3.2.0-4-powerpc-di scsi-modules-3.2.0-4-powerpc-di scsi-common-modules-3.2.0-4-powerpc-di scsi-extra-modules-3.2.0-4-powerpc-di floppy-modules-3.2.0-4-powerpc-di loop-modules-3.2.0-4-powerpc-di btrfs-modules-3.2.0-4-powerpc-di ext2-modules-3.2.0-4-powerpc-di ext3-modules-3.2.0-4-powerpc-di ext4-modules-3.2.0-4-powerpc-di isofs-modules-3.2.0-4-powerpc-di jfs-modules-3.2.0-4-powerpc-di reiserfs-modules-3.2.0-4-powerpc-di xfs-modules-3.2.0-4-powerpc-di fat-modules-3.2.0-4-powerpc-di hfs-modules-3.2.0-4-powerpc-di affs-modules-3.2.0-4-powerpc-di ufs-modules-3.2.0-4-powerpc-di md-modules-3.2.0-4-powerpc-di multipath-modules-3.2.0-4-powerpc-di usb-modules-3.2.0-4-powerpc-di usb-storage-modules-3.2.0-4-powerpc-di pcmcia-storage-modules-3.2.0-4-powerpc-di input-modules-3.2.0-4-powerpc-di event-modules-3.2.0-4-powerpc-di mouse-modules-3.2.0-4-powerpc-di irda-modules-3.2.0-4-powerpc-di nic-pcmcia-modules-3.2.0-4-powerpc-di pcmcia-modules-3.2.0-4-powerpc-di sata-modules-3.2.0-4-powerpc-di core-modules-3.2.0-4-powerpc-di crc-modules-3.2.0-4-powerpc-di crypto-modules-3.2.0-4-powerpc-di crypto-dm-modules-3.2.0-4-powerpc-di ata-modules-3.2.0-4-powerpc-di nbd-modules-3.2.0-4-powerpc-di squashfs-modules-3.2.0-4-powerpc-di virtio-modules-3.2.0-4-powerpc-di uinput-modules-3.2.0-4-powerpc-di zlib-modules-3.2.0-4-powerpc-di udf-modules-3.2.0-4-powerpc-di fuse-modules-3.2.0-4-powerpc-di kernel-image-3.2.0-4-powerpc64-di nic-modules-3.2.0-4-powerpc64-di nic-extra-modules-3.2.0-4-powerpc64-di nic-shared-modules-3.2.0-4-powerpc64-di serial-modules-3.2.0-4-powerpc64-di usb-serial-modules-3.2.0-4-powerpc64-di ppp-modules-3.2.0-4-powerpc64-di pata-modules-3.2.0-4-powerpc64-di cdrom-core-modules-3.2.0-4-powerpc64-di firewire-core-modules-3.2.0-4-powerpc64-di scsi-core-modules-3.2.0-4-powerpc64-di scsi-modules-3.2.0-4-powerpc64-di scsi-common-modules-3.2.0-4-powerpc64-di scsi-extra-modules-3.2.0-4-powerpc64-di floppy-modules-3.2.0-4-powerpc64-di loop-modules-3.2.0-4-powerpc64-di btrfs-modules-3.2.0-4-powerpc64-di ext2-modules-3.2.0-4-powerpc64-di ext3-modules-3.2.0-4-powerpc64-di ext4-modules-3.2.0-4-powerpc64-di isofs-modules-3.2.0-4-powerpc64-di jfs-modules-3.2.0-4-powerpc64-di reiserfs-modules-3.2.0-4-powerpc64-di xfs-modules-3.2.0-4-powerpc64-di fat-modules-3.2.0-4-powerpc64-di hfs-modules-3.2.0-4-powerpc64-di affs-modules-3.2.0-4-powerpc64-di ufs-modules-3.2.0-4-powerpc64-di md-modules-3.2.0-4-powerpc64-di multipath-modules-3.2.0-4-powerpc64-di usb-modules-3.2.0-4-powerpc64-di usb-storage-modules-3.2.0-4-powerpc64-di pcmcia-storage-modules-3.2.0-4-powerpc64-di input-modules-3.2.0-4-powerpc64-di event-modules-3.2.0-4-powerpc64-di mouse-modules-3.2.0-4-powerpc64-di irda-modules-3.2.0-4-powerpc64-di nic-pcmcia-modules-3.2.0-4-powerpc64-di pcmcia-modules-3.2.0-4-powerpc64-di sata-modules-3.2.0-4-powerpc64-di core-modules-3.2.0-4-powerpc64-di crc-modules-3.2.0-4-powerpc64-di crypto-modules-3.2.0-4-powerpc64-di crypto-dm-modules-3.2.0-4-powerpc64-di ata-modules-3.2.0-4-powerpc64-di nbd-modules-3.2.0-4-powerpc64-di squashfs-modules-3.2.0-4-powerpc64-di virtio-modules-3.2.0-4-powerpc64-di uinput-modules-3.2.0-4-powerpc64-di udf-modules-3.2.0-4-powerpc64-di fuse-modules-3.2.0-4-powerpc64-di hypervisor-modules-3.2.0-4-powerpc64-di fancontrol-modules-3.2.0-4-powerpc64-di' binary-arch_powerpc_none: binary-arch_powerpc_none_powerpc binary-arch_powerpc_none_powerpc-smp binary-arch_powerpc_none_powerpc64 binary-arch_powerpc_none_real binary-arch_powerpc_none_powerpc: binary-arch_powerpc_none_powerpc_real binary-arch_powerpc_none_powerpc-smp: binary-arch_powerpc_none_powerpc-smp_real binary-arch_powerpc_none_powerpc-smp_real:: - $(MAKE) -f debian/rules.real binary-arch-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='powerpc' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='powerpc-smp' KCONFIG='debian/config/config debian/config/powerpc/config debian/config/powerpc/config.powerpc debian/config/powerpc/config.powerpc-smp' KERNEL_ARCH='powerpc' LOCALVERSION='-powerpc-smp' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-powerpc-smp' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real binary-arch-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='powerpc' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='powerpc-smp' KCONFIG='debian/config/config debian/config/powerpc/config debian/config/powerpc/config.powerpc debian/config/powerpc/config.powerpc-smp' KERNEL_ARCH='powerpc' LOCALVERSION='-powerpc-smp' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-powerpc-smp' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' binary-arch_powerpc_none_powerpc64: binary-arch_powerpc_none_powerpc64_real binary-arch_powerpc_none_powerpc64_real:: - $(MAKE) -f debian/rules.real binary-arch-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='powerpc' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='powerpc64' KCONFIG='debian/config/config debian/config/powerpc/config debian/config/powerpc/config.powerpc64' KERNEL_ARCH='powerpc' LOCALVERSION='-powerpc64' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-powerpc64' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real binary-arch-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='powerpc' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='powerpc64' KCONFIG='debian/config/config debian/config/powerpc/config debian/config/powerpc/config.powerpc64' KERNEL_ARCH='powerpc' LOCALVERSION='-powerpc64' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-powerpc64' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' binary-arch_powerpc_none_powerpc_real:: - $(MAKE) -f debian/rules.real binary-arch-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='powerpc' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='powerpc' KCONFIG='debian/config/config debian/config/powerpc/config debian/config/powerpc/config.powerpc' KERNEL_ARCH='powerpc' LOCALVERSION='-powerpc' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-powerpc' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real binary-arch-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='powerpc' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='powerpc' KCONFIG='debian/config/config debian/config/powerpc/config debian/config/powerpc/config.powerpc' KERNEL_ARCH='powerpc' LOCALVERSION='-powerpc' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-powerpc' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' binary-arch_powerpc_none_real:: - $(MAKE) -f debian/rules.real binary-arch-featureset ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='powerpc' FEATURESET='none' KERNEL_ARCH='powerpc' LOCALVERSION_HEADERS='' SOURCEVERSION='3.2.46-1' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real binary-arch-featureset ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='powerpc' FEATURESET='none' KERNEL_ARCH='powerpc' LOCALVERSION_HEADERS='' SOURCEVERSION='3.2.46-1+rpi1' UPSTREAMVERSION='3.2' VERSION='3.2' binary-arch_powerpc_real:: - $(MAKE) -f debian/rules.real binary-arch-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='powerpc' KERNEL_ARCH='powerpc' SOURCEVERSION='3.2.46-1' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real binary-arch-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='powerpc' KERNEL_ARCH='powerpc' SOURCEVERSION='3.2.46-1+rpi1' UPSTREAMVERSION='3.2' VERSION='3.2' binary-arch_ppc64:: binary-arch_ppc64_none binary-arch_ppc64_real binary-arch_ppc64:: - $(MAKE) -f debian/rules.real install-udeb_ppc64 ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='ppc64' KERNEL_ARCH='powerpc' SOURCEVERSION='3.2.46-1' UPSTREAMVERSION='3.2' VERSION='3.2' PACKAGE_NAMES='kernel-image-3.2.0-4-powerpc64-di nic-modules-3.2.0-4-powerpc64-di nic-extra-modules-3.2.0-4-powerpc64-di nic-shared-modules-3.2.0-4-powerpc64-di serial-modules-3.2.0-4-powerpc64-di usb-serial-modules-3.2.0-4-powerpc64-di ppp-modules-3.2.0-4-powerpc64-di pata-modules-3.2.0-4-powerpc64-di cdrom-core-modules-3.2.0-4-powerpc64-di firewire-core-modules-3.2.0-4-powerpc64-di scsi-core-modules-3.2.0-4-powerpc64-di scsi-modules-3.2.0-4-powerpc64-di scsi-common-modules-3.2.0-4-powerpc64-di scsi-extra-modules-3.2.0-4-powerpc64-di floppy-modules-3.2.0-4-powerpc64-di loop-modules-3.2.0-4-powerpc64-di btrfs-modules-3.2.0-4-powerpc64-di ext2-modules-3.2.0-4-powerpc64-di ext3-modules-3.2.0-4-powerpc64-di ext4-modules-3.2.0-4-powerpc64-di isofs-modules-3.2.0-4-powerpc64-di jfs-modules-3.2.0-4-powerpc64-di reiserfs-modules-3.2.0-4-powerpc64-di xfs-modules-3.2.0-4-powerpc64-di fat-modules-3.2.0-4-powerpc64-di hfs-modules-3.2.0-4-powerpc64-di affs-modules-3.2.0-4-powerpc64-di ufs-modules-3.2.0-4-powerpc64-di md-modules-3.2.0-4-powerpc64-di multipath-modules-3.2.0-4-powerpc64-di usb-modules-3.2.0-4-powerpc64-di usb-storage-modules-3.2.0-4-powerpc64-di pcmcia-storage-modules-3.2.0-4-powerpc64-di input-modules-3.2.0-4-powerpc64-di event-modules-3.2.0-4-powerpc64-di mouse-modules-3.2.0-4-powerpc64-di irda-modules-3.2.0-4-powerpc64-di nic-pcmcia-modules-3.2.0-4-powerpc64-di pcmcia-modules-3.2.0-4-powerpc64-di sata-modules-3.2.0-4-powerpc64-di core-modules-3.2.0-4-powerpc64-di crc-modules-3.2.0-4-powerpc64-di crypto-modules-3.2.0-4-powerpc64-di crypto-dm-modules-3.2.0-4-powerpc64-di ata-modules-3.2.0-4-powerpc64-di nbd-modules-3.2.0-4-powerpc64-di squashfs-modules-3.2.0-4-powerpc64-di virtio-modules-3.2.0-4-powerpc64-di uinput-modules-3.2.0-4-powerpc64-di udf-modules-3.2.0-4-powerpc64-di fuse-modules-3.2.0-4-powerpc64-di hypervisor-modules-3.2.0-4-powerpc64-di fancontrol-modules-3.2.0-4-powerpc64-di' + $(MAKE) -f debian/rules.real install-udeb_ppc64 ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='ppc64' KERNEL_ARCH='powerpc' SOURCEVERSION='3.2.46-1+rpi1' UPSTREAMVERSION='3.2' VERSION='3.2' PACKAGE_NAMES='kernel-image-3.2.0-4-powerpc64-di nic-modules-3.2.0-4-powerpc64-di nic-extra-modules-3.2.0-4-powerpc64-di nic-shared-modules-3.2.0-4-powerpc64-di serial-modules-3.2.0-4-powerpc64-di usb-serial-modules-3.2.0-4-powerpc64-di ppp-modules-3.2.0-4-powerpc64-di pata-modules-3.2.0-4-powerpc64-di cdrom-core-modules-3.2.0-4-powerpc64-di firewire-core-modules-3.2.0-4-powerpc64-di scsi-core-modules-3.2.0-4-powerpc64-di scsi-modules-3.2.0-4-powerpc64-di scsi-common-modules-3.2.0-4-powerpc64-di scsi-extra-modules-3.2.0-4-powerpc64-di floppy-modules-3.2.0-4-powerpc64-di loop-modules-3.2.0-4-powerpc64-di btrfs-modules-3.2.0-4-powerpc64-di ext2-modules-3.2.0-4-powerpc64-di ext3-modules-3.2.0-4-powerpc64-di ext4-modules-3.2.0-4-powerpc64-di isofs-modules-3.2.0-4-powerpc64-di jfs-modules-3.2.0-4-powerpc64-di reiserfs-modules-3.2.0-4-powerpc64-di xfs-modules-3.2.0-4-powerpc64-di fat-modules-3.2.0-4-powerpc64-di hfs-modules-3.2.0-4-powerpc64-di affs-modules-3.2.0-4-powerpc64-di ufs-modules-3.2.0-4-powerpc64-di md-modules-3.2.0-4-powerpc64-di multipath-modules-3.2.0-4-powerpc64-di usb-modules-3.2.0-4-powerpc64-di usb-storage-modules-3.2.0-4-powerpc64-di pcmcia-storage-modules-3.2.0-4-powerpc64-di input-modules-3.2.0-4-powerpc64-di event-modules-3.2.0-4-powerpc64-di mouse-modules-3.2.0-4-powerpc64-di irda-modules-3.2.0-4-powerpc64-di nic-pcmcia-modules-3.2.0-4-powerpc64-di pcmcia-modules-3.2.0-4-powerpc64-di sata-modules-3.2.0-4-powerpc64-di core-modules-3.2.0-4-powerpc64-di crc-modules-3.2.0-4-powerpc64-di crypto-modules-3.2.0-4-powerpc64-di crypto-dm-modules-3.2.0-4-powerpc64-di ata-modules-3.2.0-4-powerpc64-di nbd-modules-3.2.0-4-powerpc64-di squashfs-modules-3.2.0-4-powerpc64-di virtio-modules-3.2.0-4-powerpc64-di uinput-modules-3.2.0-4-powerpc64-di udf-modules-3.2.0-4-powerpc64-di fuse-modules-3.2.0-4-powerpc64-di hypervisor-modules-3.2.0-4-powerpc64-di fancontrol-modules-3.2.0-4-powerpc64-di' binary-arch_ppc64_none: binary-arch_ppc64_none_powerpc64 binary-arch_ppc64_none_real binary-arch_ppc64_none_powerpc64: binary-arch_ppc64_none_powerpc64_real binary-arch_ppc64_none_powerpc64_real:: - $(MAKE) -f debian/rules.real binary-arch-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='ppc64' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='powerpc64' KCONFIG='debian/config/config debian/config/powerpc/config debian/config/powerpc/config.powerpc64' KERNEL_ARCH='powerpc' LOCALVERSION='-powerpc64' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-powerpc64' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real binary-arch-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='ppc64' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='powerpc64' KCONFIG='debian/config/config debian/config/powerpc/config debian/config/powerpc/config.powerpc64' KERNEL_ARCH='powerpc' LOCALVERSION='-powerpc64' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-powerpc64' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' binary-arch_ppc64_none_real:: - $(MAKE) -f debian/rules.real binary-arch-featureset ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='ppc64' FEATURESET='none' KERNEL_ARCH='powerpc' LOCALVERSION_HEADERS='' SOURCEVERSION='3.2.46-1' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real binary-arch-featureset ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='ppc64' FEATURESET='none' KERNEL_ARCH='powerpc' LOCALVERSION_HEADERS='' SOURCEVERSION='3.2.46-1+rpi1' UPSTREAMVERSION='3.2' VERSION='3.2' binary-arch_ppc64_real:: - $(MAKE) -f debian/rules.real binary-arch-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='ppc64' KERNEL_ARCH='powerpc' SOURCEVERSION='3.2.46-1' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real binary-arch-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='ppc64' KERNEL_ARCH='powerpc' SOURCEVERSION='3.2.46-1+rpi1' UPSTREAMVERSION='3.2' VERSION='3.2' binary-arch_s390:: binary-arch_s390_none binary-arch_s390_real binary-arch_s390:: - $(MAKE) -f debian/rules.real install-udeb_s390 ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='s390' KERNEL_ARCH='s390' SOURCEVERSION='3.2.46-1' UPSTREAMVERSION='3.2' VERSION='3.2' PACKAGE_NAMES='kernel-image-3.2.0-4-s390x-di nic-modules-3.2.0-4-s390x-di scsi-core-modules-3.2.0-4-s390x-di scsi-modules-3.2.0-4-s390x-di ext2-modules-3.2.0-4-s390x-di ext3-modules-3.2.0-4-s390x-di ext4-modules-3.2.0-4-s390x-di xfs-modules-3.2.0-4-s390x-di fat-modules-3.2.0-4-s390x-di md-modules-3.2.0-4-s390x-di multipath-modules-3.2.0-4-s390x-di core-modules-3.2.0-4-s390x-di crypto-modules-3.2.0-4-s390x-di crypto-dm-modules-3.2.0-4-s390x-di nbd-modules-3.2.0-4-s390x-di virtio-modules-3.2.0-4-s390x-di fuse-modules-3.2.0-4-s390x-di dasd-modules-3.2.0-4-s390x-di dasd-extra-modules-3.2.0-4-s390x-di kernel-image-3.2.0-4-s390x-tape-di' + $(MAKE) -f debian/rules.real install-udeb_s390 ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='s390' KERNEL_ARCH='s390' SOURCEVERSION='3.2.46-1+rpi1' UPSTREAMVERSION='3.2' VERSION='3.2' PACKAGE_NAMES='kernel-image-3.2.0-4-s390x-di nic-modules-3.2.0-4-s390x-di scsi-core-modules-3.2.0-4-s390x-di scsi-modules-3.2.0-4-s390x-di ext2-modules-3.2.0-4-s390x-di ext3-modules-3.2.0-4-s390x-di ext4-modules-3.2.0-4-s390x-di xfs-modules-3.2.0-4-s390x-di fat-modules-3.2.0-4-s390x-di md-modules-3.2.0-4-s390x-di multipath-modules-3.2.0-4-s390x-di core-modules-3.2.0-4-s390x-di crypto-modules-3.2.0-4-s390x-di crypto-dm-modules-3.2.0-4-s390x-di nbd-modules-3.2.0-4-s390x-di virtio-modules-3.2.0-4-s390x-di fuse-modules-3.2.0-4-s390x-di dasd-modules-3.2.0-4-s390x-di dasd-extra-modules-3.2.0-4-s390x-di kernel-image-3.2.0-4-s390x-tape-di' binary-arch_s390_none: binary-arch_s390_none_real binary-arch_s390_none_s390x binary-arch_s390_none_s390x-tape binary-arch_s390_none_real:: - $(MAKE) -f debian/rules.real binary-arch-featureset ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='s390' FEATURESET='none' KERNEL_ARCH='s390' LOCALVERSION_HEADERS='' SOURCEVERSION='3.2.46-1' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real binary-arch-featureset ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='s390' FEATURESET='none' KERNEL_ARCH='s390' LOCALVERSION_HEADERS='' SOURCEVERSION='3.2.46-1+rpi1' UPSTREAMVERSION='3.2' VERSION='3.2' binary-arch_s390_none_s390x: binary-arch_s390_none_s390x_real binary-arch_s390_none_s390x-tape: binary-arch_s390_none_s390x-tape_real binary-arch_s390_none_s390x-tape_real:: - $(MAKE) -f debian/rules.real binary-arch-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='s390' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='s390x-tape' INITRAMFS='False' KCONFIG='debian/config/config debian/config/s390/config debian/config/s390/config.s390x-tape' KERNEL_ARCH='s390' LOCALVERSION='-s390x-tape' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-s390x' SOURCEVERSION='3.2.46-1' TYPE='plain-s390-tape' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real binary-arch-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='s390' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='s390x-tape' INITRAMFS='False' KCONFIG='debian/config/config debian/config/s390/config debian/config/s390/config.s390x-tape' KERNEL_ARCH='s390' LOCALVERSION='-s390x-tape' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-s390x' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain-s390-tape' UPSTREAMVERSION='3.2' VERSION='3.2' binary-arch_s390_none_s390x_real:: - $(MAKE) -f debian/rules.real binary-arch-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='s390' COMPILER='gcc-4.6' DEBUG='True' FEATURESET='none' FLAVOUR='s390x' KCONFIG='debian/config/config debian/config/s390/config debian/config/s390/config.s390x' KCONFIG_OPTIONS='-o DEBUG_INFO=y' KERNEL_ARCH='s390' LOCALVERSION='-s390x' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-s390x' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real binary-arch-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='s390' COMPILER='gcc-4.6' DEBUG='True' FEATURESET='none' FLAVOUR='s390x' KCONFIG='debian/config/config debian/config/s390/config debian/config/s390/config.s390x' KCONFIG_OPTIONS='-o DEBUG_INFO=y' KERNEL_ARCH='s390' LOCALVERSION='-s390x' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-s390x' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' binary-arch_s390_real:: - $(MAKE) -f debian/rules.real binary-arch-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='s390' KERNEL_ARCH='s390' SOURCEVERSION='3.2.46-1' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real binary-arch-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='s390' KERNEL_ARCH='s390' SOURCEVERSION='3.2.46-1+rpi1' UPSTREAMVERSION='3.2' VERSION='3.2' binary-arch_s390x:: binary-arch_s390x_none binary-arch_s390x_real binary-arch_s390x:: - $(MAKE) -f debian/rules.real install-udeb_s390x ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='s390x' KERNEL_ARCH='s390' SOURCEVERSION='3.2.46-1' UPSTREAMVERSION='3.2' VERSION='3.2' PACKAGE_NAMES='kernel-image-3.2.0-4-s390x-di nic-modules-3.2.0-4-s390x-di scsi-core-modules-3.2.0-4-s390x-di scsi-modules-3.2.0-4-s390x-di ext2-modules-3.2.0-4-s390x-di ext3-modules-3.2.0-4-s390x-di ext4-modules-3.2.0-4-s390x-di xfs-modules-3.2.0-4-s390x-di fat-modules-3.2.0-4-s390x-di md-modules-3.2.0-4-s390x-di multipath-modules-3.2.0-4-s390x-di core-modules-3.2.0-4-s390x-di crypto-modules-3.2.0-4-s390x-di crypto-dm-modules-3.2.0-4-s390x-di nbd-modules-3.2.0-4-s390x-di virtio-modules-3.2.0-4-s390x-di fuse-modules-3.2.0-4-s390x-di dasd-modules-3.2.0-4-s390x-di dasd-extra-modules-3.2.0-4-s390x-di kernel-image-3.2.0-4-s390x-tape-di' + $(MAKE) -f debian/rules.real install-udeb_s390x ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='s390x' KERNEL_ARCH='s390' SOURCEVERSION='3.2.46-1+rpi1' UPSTREAMVERSION='3.2' VERSION='3.2' PACKAGE_NAMES='kernel-image-3.2.0-4-s390x-di nic-modules-3.2.0-4-s390x-di scsi-core-modules-3.2.0-4-s390x-di scsi-modules-3.2.0-4-s390x-di ext2-modules-3.2.0-4-s390x-di ext3-modules-3.2.0-4-s390x-di ext4-modules-3.2.0-4-s390x-di xfs-modules-3.2.0-4-s390x-di fat-modules-3.2.0-4-s390x-di md-modules-3.2.0-4-s390x-di multipath-modules-3.2.0-4-s390x-di core-modules-3.2.0-4-s390x-di crypto-modules-3.2.0-4-s390x-di crypto-dm-modules-3.2.0-4-s390x-di nbd-modules-3.2.0-4-s390x-di virtio-modules-3.2.0-4-s390x-di fuse-modules-3.2.0-4-s390x-di dasd-modules-3.2.0-4-s390x-di dasd-extra-modules-3.2.0-4-s390x-di kernel-image-3.2.0-4-s390x-tape-di' binary-arch_s390x_none: binary-arch_s390x_none_real binary-arch_s390x_none_s390x binary-arch_s390x_none_s390x-tape binary-arch_s390x_none_real:: - $(MAKE) -f debian/rules.real binary-arch-featureset ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='s390x' FEATURESET='none' KERNEL_ARCH='s390' LOCALVERSION_HEADERS='' SOURCEVERSION='3.2.46-1' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real binary-arch-featureset ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='s390x' FEATURESET='none' KERNEL_ARCH='s390' LOCALVERSION_HEADERS='' SOURCEVERSION='3.2.46-1+rpi1' UPSTREAMVERSION='3.2' VERSION='3.2' binary-arch_s390x_none_s390x: binary-arch_s390x_none_s390x_real binary-arch_s390x_none_s390x-tape: binary-arch_s390x_none_s390x-tape_real binary-arch_s390x_none_s390x-tape_real:: - $(MAKE) -f debian/rules.real binary-arch-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='s390x' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='s390x-tape' INITRAMFS='False' KCONFIG='debian/config/config debian/config/s390/config debian/config/s390/config.s390x-tape' KERNEL_ARCH='s390' LOCALVERSION='-s390x-tape' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-s390x' SOURCEVERSION='3.2.46-1' TYPE='plain-s390-tape' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real binary-arch-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='s390x' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='s390x-tape' INITRAMFS='False' KCONFIG='debian/config/config debian/config/s390/config debian/config/s390/config.s390x-tape' KERNEL_ARCH='s390' LOCALVERSION='-s390x-tape' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-s390x' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain-s390-tape' UPSTREAMVERSION='3.2' VERSION='3.2' binary-arch_s390x_none_s390x_real:: - $(MAKE) -f debian/rules.real binary-arch-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='s390x' COMPILER='gcc-4.6' DEBUG='True' FEATURESET='none' FLAVOUR='s390x' KCONFIG='debian/config/config debian/config/s390/config debian/config/s390/config.s390x' KCONFIG_OPTIONS='-o DEBUG_INFO=y' KERNEL_ARCH='s390' LOCALVERSION='-s390x' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-s390x' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real binary-arch-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='s390x' COMPILER='gcc-4.6' DEBUG='True' FEATURESET='none' FLAVOUR='s390x' KCONFIG='debian/config/config debian/config/s390/config debian/config/s390/config.s390x' KCONFIG_OPTIONS='-o DEBUG_INFO=y' KERNEL_ARCH='s390' LOCALVERSION='-s390x' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-s390x' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' binary-arch_s390x_real:: - $(MAKE) -f debian/rules.real binary-arch-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='s390x' KERNEL_ARCH='s390' SOURCEVERSION='3.2.46-1' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real binary-arch-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='s390x' KERNEL_ARCH='s390' SOURCEVERSION='3.2.46-1+rpi1' UPSTREAMVERSION='3.2' VERSION='3.2' binary-arch_sh4:: binary-arch_sh4_none binary-arch_sh4_real binary-arch_sh4:: - $(MAKE) -f debian/rules.real install-udeb_sh4 ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='sh4' KERNEL_ARCH='sh' SOURCEVERSION='3.2.46-1' UPSTREAMVERSION='3.2' VERSION='3.2' PACKAGE_NAMES='kernel-image-3.2.0-4-sh7751r-di nic-modules-3.2.0-4-sh7751r-di usb-serial-modules-3.2.0-4-sh7751r-di ppp-modules-3.2.0-4-sh7751r-di pata-modules-3.2.0-4-sh7751r-di cdrom-core-modules-3.2.0-4-sh7751r-di firewire-core-modules-3.2.0-4-sh7751r-di scsi-core-modules-3.2.0-4-sh7751r-di loop-modules-3.2.0-4-sh7751r-di ipv6-modules-3.2.0-4-sh7751r-di btrfs-modules-3.2.0-4-sh7751r-di ext2-modules-3.2.0-4-sh7751r-di ext4-modules-3.2.0-4-sh7751r-di isofs-modules-3.2.0-4-sh7751r-di jfs-modules-3.2.0-4-sh7751r-di reiserfs-modules-3.2.0-4-sh7751r-di xfs-modules-3.2.0-4-sh7751r-di fat-modules-3.2.0-4-sh7751r-di ufs-modules-3.2.0-4-sh7751r-di minix-modules-3.2.0-4-sh7751r-di md-modules-3.2.0-4-sh7751r-di multipath-modules-3.2.0-4-sh7751r-di usb-storage-modules-3.2.0-4-sh7751r-di parport-modules-3.2.0-4-sh7751r-di nic-usb-modules-3.2.0-4-sh7751r-di sata-modules-3.2.0-4-sh7751r-di i2c-modules-3.2.0-4-sh7751r-di crc-modules-3.2.0-4-sh7751r-di crypto-modules-3.2.0-4-sh7751r-di crypto-dm-modules-3.2.0-4-sh7751r-di nbd-modules-3.2.0-4-sh7751r-di squashfs-modules-3.2.0-4-sh7751r-di speakup-modules-3.2.0-4-sh7751r-di virtio-modules-3.2.0-4-sh7751r-di sound-modules-3.2.0-4-sh7751r-di zlib-modules-3.2.0-4-sh7751r-di udf-modules-3.2.0-4-sh7751r-di fuse-modules-3.2.0-4-sh7751r-di kernel-image-3.2.0-4-sh7785lcr-di nic-modules-3.2.0-4-sh7785lcr-di usb-serial-modules-3.2.0-4-sh7785lcr-di ppp-modules-3.2.0-4-sh7785lcr-di pata-modules-3.2.0-4-sh7785lcr-di cdrom-core-modules-3.2.0-4-sh7785lcr-di firewire-core-modules-3.2.0-4-sh7785lcr-di scsi-core-modules-3.2.0-4-sh7785lcr-di loop-modules-3.2.0-4-sh7785lcr-di ipv6-modules-3.2.0-4-sh7785lcr-di btrfs-modules-3.2.0-4-sh7785lcr-di ext2-modules-3.2.0-4-sh7785lcr-di ext4-modules-3.2.0-4-sh7785lcr-di isofs-modules-3.2.0-4-sh7785lcr-di jfs-modules-3.2.0-4-sh7785lcr-di reiserfs-modules-3.2.0-4-sh7785lcr-di xfs-modules-3.2.0-4-sh7785lcr-di fat-modules-3.2.0-4-sh7785lcr-di ufs-modules-3.2.0-4-sh7785lcr-di minix-modules-3.2.0-4-sh7785lcr-di md-modules-3.2.0-4-sh7785lcr-di multipath-modules-3.2.0-4-sh7785lcr-di parport-modules-3.2.0-4-sh7785lcr-di nic-usb-modules-3.2.0-4-sh7785lcr-di sata-modules-3.2.0-4-sh7785lcr-di crc-modules-3.2.0-4-sh7785lcr-di crypto-modules-3.2.0-4-sh7785lcr-di crypto-dm-modules-3.2.0-4-sh7785lcr-di nbd-modules-3.2.0-4-sh7785lcr-di squashfs-modules-3.2.0-4-sh7785lcr-di speakup-modules-3.2.0-4-sh7785lcr-di sound-modules-3.2.0-4-sh7785lcr-di zlib-modules-3.2.0-4-sh7785lcr-di udf-modules-3.2.0-4-sh7785lcr-di fuse-modules-3.2.0-4-sh7785lcr-di' + $(MAKE) -f debian/rules.real install-udeb_sh4 ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='sh4' KERNEL_ARCH='sh' SOURCEVERSION='3.2.46-1+rpi1' UPSTREAMVERSION='3.2' VERSION='3.2' PACKAGE_NAMES='kernel-image-3.2.0-4-sh7751r-di nic-modules-3.2.0-4-sh7751r-di usb-serial-modules-3.2.0-4-sh7751r-di ppp-modules-3.2.0-4-sh7751r-di pata-modules-3.2.0-4-sh7751r-di cdrom-core-modules-3.2.0-4-sh7751r-di firewire-core-modules-3.2.0-4-sh7751r-di scsi-core-modules-3.2.0-4-sh7751r-di loop-modules-3.2.0-4-sh7751r-di ipv6-modules-3.2.0-4-sh7751r-di btrfs-modules-3.2.0-4-sh7751r-di ext2-modules-3.2.0-4-sh7751r-di ext4-modules-3.2.0-4-sh7751r-di isofs-modules-3.2.0-4-sh7751r-di jfs-modules-3.2.0-4-sh7751r-di reiserfs-modules-3.2.0-4-sh7751r-di xfs-modules-3.2.0-4-sh7751r-di fat-modules-3.2.0-4-sh7751r-di ufs-modules-3.2.0-4-sh7751r-di minix-modules-3.2.0-4-sh7751r-di md-modules-3.2.0-4-sh7751r-di multipath-modules-3.2.0-4-sh7751r-di usb-storage-modules-3.2.0-4-sh7751r-di parport-modules-3.2.0-4-sh7751r-di nic-usb-modules-3.2.0-4-sh7751r-di sata-modules-3.2.0-4-sh7751r-di i2c-modules-3.2.0-4-sh7751r-di crc-modules-3.2.0-4-sh7751r-di crypto-modules-3.2.0-4-sh7751r-di crypto-dm-modules-3.2.0-4-sh7751r-di nbd-modules-3.2.0-4-sh7751r-di squashfs-modules-3.2.0-4-sh7751r-di speakup-modules-3.2.0-4-sh7751r-di virtio-modules-3.2.0-4-sh7751r-di sound-modules-3.2.0-4-sh7751r-di zlib-modules-3.2.0-4-sh7751r-di udf-modules-3.2.0-4-sh7751r-di fuse-modules-3.2.0-4-sh7751r-di kernel-image-3.2.0-4-sh7785lcr-di nic-modules-3.2.0-4-sh7785lcr-di usb-serial-modules-3.2.0-4-sh7785lcr-di ppp-modules-3.2.0-4-sh7785lcr-di pata-modules-3.2.0-4-sh7785lcr-di cdrom-core-modules-3.2.0-4-sh7785lcr-di firewire-core-modules-3.2.0-4-sh7785lcr-di scsi-core-modules-3.2.0-4-sh7785lcr-di loop-modules-3.2.0-4-sh7785lcr-di ipv6-modules-3.2.0-4-sh7785lcr-di btrfs-modules-3.2.0-4-sh7785lcr-di ext2-modules-3.2.0-4-sh7785lcr-di ext4-modules-3.2.0-4-sh7785lcr-di isofs-modules-3.2.0-4-sh7785lcr-di jfs-modules-3.2.0-4-sh7785lcr-di reiserfs-modules-3.2.0-4-sh7785lcr-di xfs-modules-3.2.0-4-sh7785lcr-di fat-modules-3.2.0-4-sh7785lcr-di ufs-modules-3.2.0-4-sh7785lcr-di minix-modules-3.2.0-4-sh7785lcr-di md-modules-3.2.0-4-sh7785lcr-di multipath-modules-3.2.0-4-sh7785lcr-di parport-modules-3.2.0-4-sh7785lcr-di nic-usb-modules-3.2.0-4-sh7785lcr-di sata-modules-3.2.0-4-sh7785lcr-di crc-modules-3.2.0-4-sh7785lcr-di crypto-modules-3.2.0-4-sh7785lcr-di crypto-dm-modules-3.2.0-4-sh7785lcr-di nbd-modules-3.2.0-4-sh7785lcr-di squashfs-modules-3.2.0-4-sh7785lcr-di speakup-modules-3.2.0-4-sh7785lcr-di sound-modules-3.2.0-4-sh7785lcr-di zlib-modules-3.2.0-4-sh7785lcr-di udf-modules-3.2.0-4-sh7785lcr-di fuse-modules-3.2.0-4-sh7785lcr-di' binary-arch_sh4_none: binary-arch_sh4_none_real binary-arch_sh4_none_sh7751r binary-arch_sh4_none_sh7785lcr binary-arch_sh4_none_real:: - $(MAKE) -f debian/rules.real binary-arch-featureset ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='sh4' FEATURESET='none' KERNEL_ARCH='sh' LOCALVERSION_HEADERS='' SOURCEVERSION='3.2.46-1' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real binary-arch-featureset ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='sh4' FEATURESET='none' KERNEL_ARCH='sh' LOCALVERSION_HEADERS='' SOURCEVERSION='3.2.46-1+rpi1' UPSTREAMVERSION='3.2' VERSION='3.2' binary-arch_sh4_none_sh7751r: binary-arch_sh4_none_sh7751r_real binary-arch_sh4_none_sh7751r_real:: - $(MAKE) -f debian/rules.real binary-arch-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='sh4' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='sh7751r' KCONFIG='debian/config/config debian/config/sh4/config debian/config/sh4/config.sh7751r' KERNEL_ARCH='sh' LOCALVERSION='-sh7751r' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-sh7751r' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real binary-arch-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='sh4' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='sh7751r' KCONFIG='debian/config/config debian/config/sh4/config debian/config/sh4/config.sh7751r' KERNEL_ARCH='sh' LOCALVERSION='-sh7751r' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-sh7751r' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' binary-arch_sh4_none_sh7785lcr: binary-arch_sh4_none_sh7785lcr_real binary-arch_sh4_none_sh7785lcr_real:: - $(MAKE) -f debian/rules.real binary-arch-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='sh4' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='sh7785lcr' KCONFIG='debian/config/config debian/config/sh4/config debian/config/sh4/config.sh7785lcr' KERNEL_ARCH='sh' LOCALVERSION='-sh7785lcr' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-sh7785lcr' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real binary-arch-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='sh4' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='sh7785lcr' KCONFIG='debian/config/config debian/config/sh4/config debian/config/sh4/config.sh7785lcr' KERNEL_ARCH='sh' LOCALVERSION='-sh7785lcr' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-sh7785lcr' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' binary-arch_sh4_real:: - $(MAKE) -f debian/rules.real binary-arch-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='sh4' KERNEL_ARCH='sh' SOURCEVERSION='3.2.46-1' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real binary-arch-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='sh4' KERNEL_ARCH='sh' SOURCEVERSION='3.2.46-1+rpi1' UPSTREAMVERSION='3.2' VERSION='3.2' binary-arch_sparc:: binary-arch_sparc_none binary-arch_sparc_real binary-arch_sparc:: - $(MAKE) -f debian/rules.real install-udeb_sparc ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='sparc' KERNEL_ARCH='sparc' SOURCEVERSION='3.2.46-1' UPSTREAMVERSION='3.2' VERSION='3.2' PACKAGE_NAMES='kernel-image-3.2.0-4-sparc64-di nic-modules-3.2.0-4-sparc64-di ppp-modules-3.2.0-4-sparc64-di pata-modules-3.2.0-4-sparc64-di cdrom-core-modules-3.2.0-4-sparc64-di scsi-core-modules-3.2.0-4-sparc64-di scsi-modules-3.2.0-4-sparc64-di scsi-common-modules-3.2.0-4-sparc64-di plip-modules-3.2.0-4-sparc64-di btrfs-modules-3.2.0-4-sparc64-di ext2-modules-3.2.0-4-sparc64-di ext3-modules-3.2.0-4-sparc64-di ext4-modules-3.2.0-4-sparc64-di isofs-modules-3.2.0-4-sparc64-di jfs-modules-3.2.0-4-sparc64-di reiserfs-modules-3.2.0-4-sparc64-di xfs-modules-3.2.0-4-sparc64-di fat-modules-3.2.0-4-sparc64-di md-modules-3.2.0-4-sparc64-di multipath-modules-3.2.0-4-sparc64-di usb-modules-3.2.0-4-sparc64-di usb-storage-modules-3.2.0-4-sparc64-di input-modules-3.2.0-4-sparc64-di sata-modules-3.2.0-4-sparc64-di core-modules-3.2.0-4-sparc64-di crypto-modules-3.2.0-4-sparc64-di crypto-dm-modules-3.2.0-4-sparc64-di ata-modules-3.2.0-4-sparc64-di nbd-modules-3.2.0-4-sparc64-di squashfs-modules-3.2.0-4-sparc64-di virtio-modules-3.2.0-4-sparc64-di zlib-modules-3.2.0-4-sparc64-di udf-modules-3.2.0-4-sparc64-di fuse-modules-3.2.0-4-sparc64-di' + $(MAKE) -f debian/rules.real install-udeb_sparc ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='sparc' KERNEL_ARCH='sparc' SOURCEVERSION='3.2.46-1+rpi1' UPSTREAMVERSION='3.2' VERSION='3.2' PACKAGE_NAMES='kernel-image-3.2.0-4-sparc64-di nic-modules-3.2.0-4-sparc64-di ppp-modules-3.2.0-4-sparc64-di pata-modules-3.2.0-4-sparc64-di cdrom-core-modules-3.2.0-4-sparc64-di scsi-core-modules-3.2.0-4-sparc64-di scsi-modules-3.2.0-4-sparc64-di scsi-common-modules-3.2.0-4-sparc64-di plip-modules-3.2.0-4-sparc64-di btrfs-modules-3.2.0-4-sparc64-di ext2-modules-3.2.0-4-sparc64-di ext3-modules-3.2.0-4-sparc64-di ext4-modules-3.2.0-4-sparc64-di isofs-modules-3.2.0-4-sparc64-di jfs-modules-3.2.0-4-sparc64-di reiserfs-modules-3.2.0-4-sparc64-di xfs-modules-3.2.0-4-sparc64-di fat-modules-3.2.0-4-sparc64-di md-modules-3.2.0-4-sparc64-di multipath-modules-3.2.0-4-sparc64-di usb-modules-3.2.0-4-sparc64-di usb-storage-modules-3.2.0-4-sparc64-di input-modules-3.2.0-4-sparc64-di sata-modules-3.2.0-4-sparc64-di core-modules-3.2.0-4-sparc64-di crypto-modules-3.2.0-4-sparc64-di crypto-dm-modules-3.2.0-4-sparc64-di ata-modules-3.2.0-4-sparc64-di nbd-modules-3.2.0-4-sparc64-di squashfs-modules-3.2.0-4-sparc64-di virtio-modules-3.2.0-4-sparc64-di zlib-modules-3.2.0-4-sparc64-di udf-modules-3.2.0-4-sparc64-di fuse-modules-3.2.0-4-sparc64-di' binary-arch_sparc64:: binary-arch_sparc64_none binary-arch_sparc64_real binary-arch_sparc64:: - $(MAKE) -f debian/rules.real install-udeb_sparc64 ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='sparc64' KERNEL_ARCH='sparc' SOURCEVERSION='3.2.46-1' UPSTREAMVERSION='3.2' VERSION='3.2' PACKAGE_NAMES='kernel-image-3.2.0-4-sparc64-di nic-modules-3.2.0-4-sparc64-di ppp-modules-3.2.0-4-sparc64-di pata-modules-3.2.0-4-sparc64-di cdrom-core-modules-3.2.0-4-sparc64-di scsi-core-modules-3.2.0-4-sparc64-di scsi-modules-3.2.0-4-sparc64-di scsi-common-modules-3.2.0-4-sparc64-di plip-modules-3.2.0-4-sparc64-di btrfs-modules-3.2.0-4-sparc64-di ext2-modules-3.2.0-4-sparc64-di ext3-modules-3.2.0-4-sparc64-di ext4-modules-3.2.0-4-sparc64-di isofs-modules-3.2.0-4-sparc64-di jfs-modules-3.2.0-4-sparc64-di reiserfs-modules-3.2.0-4-sparc64-di xfs-modules-3.2.0-4-sparc64-di fat-modules-3.2.0-4-sparc64-di md-modules-3.2.0-4-sparc64-di multipath-modules-3.2.0-4-sparc64-di usb-modules-3.2.0-4-sparc64-di usb-storage-modules-3.2.0-4-sparc64-di input-modules-3.2.0-4-sparc64-di sata-modules-3.2.0-4-sparc64-di core-modules-3.2.0-4-sparc64-di crypto-modules-3.2.0-4-sparc64-di crypto-dm-modules-3.2.0-4-sparc64-di ata-modules-3.2.0-4-sparc64-di nbd-modules-3.2.0-4-sparc64-di squashfs-modules-3.2.0-4-sparc64-di virtio-modules-3.2.0-4-sparc64-di zlib-modules-3.2.0-4-sparc64-di udf-modules-3.2.0-4-sparc64-di fuse-modules-3.2.0-4-sparc64-di' + $(MAKE) -f debian/rules.real install-udeb_sparc64 ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='sparc64' KERNEL_ARCH='sparc' SOURCEVERSION='3.2.46-1+rpi1' UPSTREAMVERSION='3.2' VERSION='3.2' PACKAGE_NAMES='kernel-image-3.2.0-4-sparc64-di nic-modules-3.2.0-4-sparc64-di ppp-modules-3.2.0-4-sparc64-di pata-modules-3.2.0-4-sparc64-di cdrom-core-modules-3.2.0-4-sparc64-di scsi-core-modules-3.2.0-4-sparc64-di scsi-modules-3.2.0-4-sparc64-di scsi-common-modules-3.2.0-4-sparc64-di plip-modules-3.2.0-4-sparc64-di btrfs-modules-3.2.0-4-sparc64-di ext2-modules-3.2.0-4-sparc64-di ext3-modules-3.2.0-4-sparc64-di ext4-modules-3.2.0-4-sparc64-di isofs-modules-3.2.0-4-sparc64-di jfs-modules-3.2.0-4-sparc64-di reiserfs-modules-3.2.0-4-sparc64-di xfs-modules-3.2.0-4-sparc64-di fat-modules-3.2.0-4-sparc64-di md-modules-3.2.0-4-sparc64-di multipath-modules-3.2.0-4-sparc64-di usb-modules-3.2.0-4-sparc64-di usb-storage-modules-3.2.0-4-sparc64-di input-modules-3.2.0-4-sparc64-di sata-modules-3.2.0-4-sparc64-di core-modules-3.2.0-4-sparc64-di crypto-modules-3.2.0-4-sparc64-di crypto-dm-modules-3.2.0-4-sparc64-di ata-modules-3.2.0-4-sparc64-di nbd-modules-3.2.0-4-sparc64-di squashfs-modules-3.2.0-4-sparc64-di virtio-modules-3.2.0-4-sparc64-di zlib-modules-3.2.0-4-sparc64-di udf-modules-3.2.0-4-sparc64-di fuse-modules-3.2.0-4-sparc64-di' binary-arch_sparc64_none: binary-arch_sparc64_none_real binary-arch_sparc64_none_sparc64 binary-arch_sparc64_none_sparc64-smp binary-arch_sparc64_none_real:: - $(MAKE) -f debian/rules.real binary-arch-featureset ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='sparc64' FEATURESET='none' KERNEL_ARCH='sparc' LOCALVERSION_HEADERS='' SOURCEVERSION='3.2.46-1' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real binary-arch-featureset ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='sparc64' FEATURESET='none' KERNEL_ARCH='sparc' LOCALVERSION_HEADERS='' SOURCEVERSION='3.2.46-1+rpi1' UPSTREAMVERSION='3.2' VERSION='3.2' binary-arch_sparc64_none_sparc64: binary-arch_sparc64_none_sparc64_real binary-arch_sparc64_none_sparc64-smp: binary-arch_sparc64_none_sparc64-smp_real binary-arch_sparc64_none_sparc64-smp_real:: - $(MAKE) -f debian/rules.real binary-arch-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='sparc64' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='sparc64-smp' KCONFIG='debian/config/config debian/config/sparc/config debian/config/sparc/config.sparc64-smp' KERNEL_ARCH='sparc' LOCALVERSION='-sparc64-smp' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-sparc64-smp' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real binary-arch-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='sparc64' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='sparc64-smp' KCONFIG='debian/config/config debian/config/sparc/config debian/config/sparc/config.sparc64-smp' KERNEL_ARCH='sparc' LOCALVERSION='-sparc64-smp' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-sparc64-smp' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' binary-arch_sparc64_none_sparc64_real:: - $(MAKE) -f debian/rules.real binary-arch-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='sparc64' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='sparc64' KCONFIG='debian/config/config debian/config/sparc/config debian/config/sparc/config.sparc64' KERNEL_ARCH='sparc' LOCALVERSION='-sparc64' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-sparc64' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real binary-arch-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='sparc64' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='sparc64' KCONFIG='debian/config/config debian/config/sparc/config debian/config/sparc/config.sparc64' KERNEL_ARCH='sparc' LOCALVERSION='-sparc64' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-sparc64' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' binary-arch_sparc64_real:: - $(MAKE) -f debian/rules.real binary-arch-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='sparc64' KERNEL_ARCH='sparc' SOURCEVERSION='3.2.46-1' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real binary-arch-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='sparc64' KERNEL_ARCH='sparc' SOURCEVERSION='3.2.46-1+rpi1' UPSTREAMVERSION='3.2' VERSION='3.2' binary-arch_sparc_none: binary-arch_sparc_none_real binary-arch_sparc_none_sparc64 binary-arch_sparc_none_sparc64-smp binary-arch_sparc_none_real:: - $(MAKE) -f debian/rules.real binary-arch-featureset ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='sparc' FEATURESET='none' KERNEL_ARCH='sparc' LOCALVERSION_HEADERS='' SOURCEVERSION='3.2.46-1' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real binary-arch-featureset ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='sparc' FEATURESET='none' KERNEL_ARCH='sparc' LOCALVERSION_HEADERS='' SOURCEVERSION='3.2.46-1+rpi1' UPSTREAMVERSION='3.2' VERSION='3.2' binary-arch_sparc_none_sparc64: binary-arch_sparc_none_sparc64_real binary-arch_sparc_none_sparc64-smp: binary-arch_sparc_none_sparc64-smp_real binary-arch_sparc_none_sparc64-smp_real:: - $(MAKE) -f debian/rules.real binary-arch-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='sparc' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='sparc64-smp' KCONFIG='debian/config/config debian/config/sparc/config debian/config/sparc/config.sparc64-smp' KERNEL_ARCH='sparc' LOCALVERSION='-sparc64-smp' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-sparc64-smp' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real binary-arch-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='sparc' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='sparc64-smp' KCONFIG='debian/config/config debian/config/sparc/config debian/config/sparc/config.sparc64-smp' KERNEL_ARCH='sparc' LOCALVERSION='-sparc64-smp' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-sparc64-smp' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' binary-arch_sparc_none_sparc64_real:: - $(MAKE) -f debian/rules.real binary-arch-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='sparc' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='sparc64' KCONFIG='debian/config/config debian/config/sparc/config debian/config/sparc/config.sparc64' KERNEL_ARCH='sparc' LOCALVERSION='-sparc64' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-sparc64' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real binary-arch-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='sparc' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='sparc64' KCONFIG='debian/config/config debian/config/sparc/config debian/config/sparc/config.sparc64' KERNEL_ARCH='sparc' LOCALVERSION='-sparc64' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-sparc64' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' binary-arch_sparc_real:: - $(MAKE) -f debian/rules.real binary-arch-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='sparc' KERNEL_ARCH='sparc' SOURCEVERSION='3.2.46-1' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real binary-arch-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='sparc' KERNEL_ARCH='sparc' SOURCEVERSION='3.2.46-1+rpi1' UPSTREAMVERSION='3.2' VERSION='3.2' binary-indep:: - $(MAKE) -f debian/rules.real binary-indep ABINAME='3.2.0-4' ABINAME_PART='-4' ALL_FEATURESETS='none rt' SOURCEVERSION='3.2.46-1' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real binary-indep ABINAME='3.2.0-4' ABINAME_PART='-4' ALL_FEATURESETS='none rt' SOURCEVERSION='3.2.46-1+rpi1' UPSTREAMVERSION='3.2' VERSION='3.2' binary-libc-dev_alpha:: source_none_real binary-libc-dev_alpha:: - $(MAKE) -f debian/rules.real install-libc-dev_alpha ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='alpha' KERNEL_ARCH='alpha' SOURCEVERSION='3.2.46-1' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real install-libc-dev_alpha ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='alpha' KERNEL_ARCH='alpha' SOURCEVERSION='3.2.46-1+rpi1' UPSTREAMVERSION='3.2' VERSION='3.2' binary-libc-dev_amd64:: source_none_real binary-libc-dev_amd64:: - $(MAKE) -f debian/rules.real install-libc-dev_amd64 ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='amd64' KERNEL_ARCH='x86' SOURCEVERSION='3.2.46-1' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real install-libc-dev_amd64 ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='amd64' KERNEL_ARCH='x86' SOURCEVERSION='3.2.46-1+rpi1' UPSTREAMVERSION='3.2' VERSION='3.2' binary-libc-dev_armel:: source_none_real binary-libc-dev_armel:: - $(MAKE) -f debian/rules.real install-libc-dev_armel ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='armel' KERNEL_ARCH='arm' SOURCEVERSION='3.2.46-1' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real install-libc-dev_armel ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='armel' KERNEL_ARCH='arm' SOURCEVERSION='3.2.46-1+rpi1' UPSTREAMVERSION='3.2' VERSION='3.2' binary-libc-dev_armhf:: source_none_real binary-libc-dev_armhf:: - $(MAKE) -f debian/rules.real install-libc-dev_armhf ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='armhf' KERNEL_ARCH='arm' SOURCEVERSION='3.2.46-1' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real install-libc-dev_armhf ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='armhf' KERNEL_ARCH='arm' SOURCEVERSION='3.2.46-1+rpi1' UPSTREAMVERSION='3.2' VERSION='3.2' binary-libc-dev_hppa:: source_none_real binary-libc-dev_hppa:: - $(MAKE) -f debian/rules.real install-libc-dev_hppa ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='hppa' KERNEL_ARCH='parisc' SOURCEVERSION='3.2.46-1' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real install-libc-dev_hppa ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='hppa' KERNEL_ARCH='parisc' SOURCEVERSION='3.2.46-1+rpi1' UPSTREAMVERSION='3.2' VERSION='3.2' binary-libc-dev_i386:: source_none_real binary-libc-dev_i386:: - $(MAKE) -f debian/rules.real install-libc-dev_i386 ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='i386' KERNEL_ARCH='x86' SOURCEVERSION='3.2.46-1' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real install-libc-dev_i386 ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='i386' KERNEL_ARCH='x86' SOURCEVERSION='3.2.46-1+rpi1' UPSTREAMVERSION='3.2' VERSION='3.2' binary-libc-dev_ia64:: source_none_real binary-libc-dev_ia64:: - $(MAKE) -f debian/rules.real install-libc-dev_ia64 ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='ia64' KERNEL_ARCH='ia64' SOURCEVERSION='3.2.46-1' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real install-libc-dev_ia64 ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='ia64' KERNEL_ARCH='ia64' SOURCEVERSION='3.2.46-1+rpi1' UPSTREAMVERSION='3.2' VERSION='3.2' binary-libc-dev_m68k:: source_none_real binary-libc-dev_m68k:: - $(MAKE) -f debian/rules.real install-libc-dev_m68k ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='m68k' KERNEL_ARCH='m68k' SOURCEVERSION='3.2.46-1' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real install-libc-dev_m68k ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='m68k' KERNEL_ARCH='m68k' SOURCEVERSION='3.2.46-1+rpi1' UPSTREAMVERSION='3.2' VERSION='3.2' binary-libc-dev_mips:: source_none_real binary-libc-dev_mips:: - $(MAKE) -f debian/rules.real install-libc-dev_mips ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='mips' KERNEL_ARCH='mips' SOURCEVERSION='3.2.46-1' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real install-libc-dev_mips ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='mips' KERNEL_ARCH='mips' SOURCEVERSION='3.2.46-1+rpi1' UPSTREAMVERSION='3.2' VERSION='3.2' binary-libc-dev_mipsel:: source_none_real binary-libc-dev_mipsel:: - $(MAKE) -f debian/rules.real install-libc-dev_mipsel ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='mipsel' KERNEL_ARCH='mips' SOURCEVERSION='3.2.46-1' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real install-libc-dev_mipsel ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='mipsel' KERNEL_ARCH='mips' SOURCEVERSION='3.2.46-1+rpi1' UPSTREAMVERSION='3.2' VERSION='3.2' binary-libc-dev_powerpc:: source_none_real binary-libc-dev_powerpc:: - $(MAKE) -f debian/rules.real install-libc-dev_powerpc ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='powerpc' KERNEL_ARCH='powerpc' SOURCEVERSION='3.2.46-1' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real install-libc-dev_powerpc ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='powerpc' KERNEL_ARCH='powerpc' SOURCEVERSION='3.2.46-1+rpi1' UPSTREAMVERSION='3.2' VERSION='3.2' binary-libc-dev_ppc64:: source_none_real binary-libc-dev_ppc64:: - $(MAKE) -f debian/rules.real install-libc-dev_ppc64 ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='ppc64' KERNEL_ARCH='powerpc' SOURCEVERSION='3.2.46-1' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real install-libc-dev_ppc64 ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='ppc64' KERNEL_ARCH='powerpc' SOURCEVERSION='3.2.46-1+rpi1' UPSTREAMVERSION='3.2' VERSION='3.2' binary-libc-dev_s390:: source_none_real binary-libc-dev_s390:: - $(MAKE) -f debian/rules.real install-libc-dev_s390 ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='s390' KERNEL_ARCH='s390' SOURCEVERSION='3.2.46-1' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real install-libc-dev_s390 ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='s390' KERNEL_ARCH='s390' SOURCEVERSION='3.2.46-1+rpi1' UPSTREAMVERSION='3.2' VERSION='3.2' binary-libc-dev_s390x:: source_none_real binary-libc-dev_s390x:: - $(MAKE) -f debian/rules.real install-libc-dev_s390x ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='s390x' KERNEL_ARCH='s390' SOURCEVERSION='3.2.46-1' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real install-libc-dev_s390x ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='s390x' KERNEL_ARCH='s390' SOURCEVERSION='3.2.46-1+rpi1' UPSTREAMVERSION='3.2' VERSION='3.2' binary-libc-dev_sh4:: source_none_real binary-libc-dev_sh4:: - $(MAKE) -f debian/rules.real install-libc-dev_sh4 ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='sh4' KERNEL_ARCH='sh' SOURCEVERSION='3.2.46-1' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real install-libc-dev_sh4 ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='sh4' KERNEL_ARCH='sh' SOURCEVERSION='3.2.46-1+rpi1' UPSTREAMVERSION='3.2' VERSION='3.2' binary-libc-dev_sparc:: source_none_real binary-libc-dev_sparc:: - $(MAKE) -f debian/rules.real install-libc-dev_sparc ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='sparc' KERNEL_ARCH='sparc' SOURCEVERSION='3.2.46-1' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real install-libc-dev_sparc ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='sparc' KERNEL_ARCH='sparc' SOURCEVERSION='3.2.46-1+rpi1' UPSTREAMVERSION='3.2' VERSION='3.2' binary-libc-dev_sparc64:: source_none_real binary-libc-dev_sparc64:: - $(MAKE) -f debian/rules.real install-libc-dev_sparc64 ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='sparc64' KERNEL_ARCH='sparc' SOURCEVERSION='3.2.46-1' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real install-libc-dev_sparc64 ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='sparc64' KERNEL_ARCH='sparc' SOURCEVERSION='3.2.46-1+rpi1' UPSTREAMVERSION='3.2' VERSION='3.2' build-arch: build-arch_alpha build-arch_amd64 build-arch_armel build-arch_armhf build-arch_hppa build-arch_i386 build-arch_ia64 build-arch_m68k build-arch_mips build-arch_mipsel build-arch_powerpc build-arch_ppc64 build-arch_s390 build-arch_s390x build-arch_sh4 build-arch_sparc build-arch_sparc64 build-arch_alpha: build-arch_alpha_none build-arch_alpha_real build-arch_alpha_none: build-arch_alpha_none_alpha-generic build-arch_alpha_none_alpha-legacy build-arch_alpha_none_alpha-smp build-arch_alpha_none_real build-arch_alpha_none_alpha-generic: build-arch_alpha_none_alpha-generic_real build-arch_alpha_none_alpha-generic_real:: - $(MAKE) -f debian/rules.real build-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='alpha' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='alpha-generic' KCONFIG='debian/config/config debian/config/alpha/config debian/config/alpha/config.alpha-generic' KERNEL_ARCH='alpha' LOCALVERSION='-alpha-generic' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-alpha-generic' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real build-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='alpha' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='alpha-generic' KCONFIG='debian/config/config debian/config/alpha/config debian/config/alpha/config.alpha-generic' KERNEL_ARCH='alpha' LOCALVERSION='-alpha-generic' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-alpha-generic' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' build-arch_alpha_none_alpha-legacy: build-arch_alpha_none_alpha-legacy_real build-arch_alpha_none_alpha-legacy_real:: - $(MAKE) -f debian/rules.real build-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='alpha' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='alpha-legacy' KCONFIG='debian/config/config debian/config/alpha/config debian/config/alpha/config.alpha-legacy' KERNEL_ARCH='alpha' LOCALVERSION='-alpha-legacy' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-alpha-legacy' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real build-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='alpha' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='alpha-legacy' KCONFIG='debian/config/config debian/config/alpha/config debian/config/alpha/config.alpha-legacy' KERNEL_ARCH='alpha' LOCALVERSION='-alpha-legacy' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-alpha-legacy' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' build-arch_alpha_none_alpha-smp: build-arch_alpha_none_alpha-smp_real build-arch_alpha_none_alpha-smp_real:: - $(MAKE) -f debian/rules.real build-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='alpha' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='alpha-smp' KCONFIG='debian/config/config debian/config/alpha/config debian/config/alpha/config.alpha-smp' KERNEL_ARCH='alpha' LOCALVERSION='-alpha-smp' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-alpha-smp' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real build-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='alpha' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='alpha-smp' KCONFIG='debian/config/config debian/config/alpha/config debian/config/alpha/config.alpha-smp' KERNEL_ARCH='alpha' LOCALVERSION='-alpha-smp' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-alpha-smp' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' build-arch_alpha_none_real: build-arch_alpha_real: build-arch_amd64: build-arch_amd64_none build-arch_amd64_real build-arch_amd64_rt build-arch_amd64_none: build-arch_amd64_none_amd64 build-arch_amd64_none_real build-arch_amd64_none_amd64: build-arch_amd64_none_amd64_real build-arch_amd64_none_amd64_real:: - $(MAKE) -f debian/rules.real build-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='amd64' COMPILER='gcc-4.6' DEBUG='True' FEATURESET='none' FLAVOUR='amd64' KCONFIG='debian/config/config debian/config/kernelarch-x86/config debian/config/kernelarch-x86/config-arch-64' KCONFIG_OPTIONS='-o DEBUG_INFO=y' KERNEL_ARCH='x86' LOCALVERSION='-amd64' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-amd64' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real build-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='amd64' COMPILER='gcc-4.6' DEBUG='True' FEATURESET='none' FLAVOUR='amd64' KCONFIG='debian/config/config debian/config/kernelarch-x86/config debian/config/kernelarch-x86/config-arch-64' KCONFIG_OPTIONS='-o DEBUG_INFO=y' KERNEL_ARCH='x86' LOCALVERSION='-amd64' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-amd64' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' build-arch_amd64_none_real: build-arch_amd64_real: build-arch_amd64_rt: build-arch_amd64_rt_amd64 build-arch_amd64_rt_real build-arch_amd64_rt_amd64: build-arch_amd64_rt_amd64_real build-arch_amd64_rt_amd64_real:: - $(MAKE) -f debian/rules.real build-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='amd64' COMPILER='gcc-4.6' DEBUG='True' FEATURESET='rt' FLAVOUR='amd64' KCONFIG='debian/config/config debian/config/kernelarch-x86/config debian/config/kernelarch-x86/config-arch-64 debian/config/featureset-rt/config' KCONFIG_OPTIONS='-o DEBUG_INFO=y' KERNEL_ARCH='x86' LOCALVERSION='-rt-amd64' LOCALVERSION_HEADERS='-rt' LOCALVERSION_IMAGE='-rt-amd64' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real build-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='amd64' COMPILER='gcc-4.6' DEBUG='True' FEATURESET='rt' FLAVOUR='amd64' KCONFIG='debian/config/config debian/config/kernelarch-x86/config debian/config/kernelarch-x86/config-arch-64 debian/config/featureset-rt/config' KCONFIG_OPTIONS='-o DEBUG_INFO=y' KERNEL_ARCH='x86' LOCALVERSION='-rt-amd64' LOCALVERSION_HEADERS='-rt' LOCALVERSION_IMAGE='-rt-amd64' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' build-arch_amd64_rt_real: build-arch_armel: build-arch_armel_none build-arch_armel_real build-arch_armel_none: build-arch_armel_none_iop32x build-arch_armel_none_ixp4xx build-arch_armel_none_kirkwood build-arch_armel_none_mv78xx0 build-arch_armel_none_orion5x build-arch_armel_none_real build-arch_armel_none_versatile build-arch_armel_none_iop32x: build-arch_armel_none_iop32x_real build-arch_armel_none_iop32x_real:: - $(MAKE) -f debian/rules.real build-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='armel' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='iop32x' KCONFIG='debian/config/config debian/config/armel/config debian/config/armel/config.iop32x' KERNEL_ARCH='arm' LOCALVERSION='-iop32x' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-iop32x' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real build-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='armel' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='iop32x' KCONFIG='debian/config/config debian/config/armel/config debian/config/armel/config.iop32x' KERNEL_ARCH='arm' LOCALVERSION='-iop32x' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-iop32x' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' build-arch_armel_none_ixp4xx: build-arch_armel_none_ixp4xx_real build-arch_armel_none_ixp4xx_real:: - $(MAKE) -f debian/rules.real build-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='armel' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='ixp4xx' KCONFIG='debian/config/config debian/config/armel/config debian/config/armel/config.ixp4xx' KERNEL_ARCH='arm' LOCALVERSION='-ixp4xx' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-ixp4xx' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real build-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='armel' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='ixp4xx' KCONFIG='debian/config/config debian/config/armel/config debian/config/armel/config.ixp4xx' KERNEL_ARCH='arm' LOCALVERSION='-ixp4xx' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-ixp4xx' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' build-arch_armel_none_kirkwood: build-arch_armel_none_kirkwood_real build-arch_armel_none_kirkwood_real:: - $(MAKE) -f debian/rules.real build-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='armel' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='kirkwood' KCONFIG='debian/config/config debian/config/armel/config debian/config/armel/config.kirkwood' KERNEL_ARCH='arm' LOCALVERSION='-kirkwood' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-kirkwood' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real build-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='armel' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='kirkwood' KCONFIG='debian/config/config debian/config/armel/config debian/config/armel/config.kirkwood' KERNEL_ARCH='arm' LOCALVERSION='-kirkwood' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-kirkwood' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' build-arch_armel_none_mv78xx0: build-arch_armel_none_mv78xx0_real build-arch_armel_none_mv78xx0_real:: - $(MAKE) -f debian/rules.real build-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='armel' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='mv78xx0' KCONFIG='debian/config/config debian/config/armel/config debian/config/armel/config.mv78xx0' KERNEL_ARCH='arm' LOCALVERSION='-mv78xx0' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-mv78xx0' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real build-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='armel' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='mv78xx0' KCONFIG='debian/config/config debian/config/armel/config debian/config/armel/config.mv78xx0' KERNEL_ARCH='arm' LOCALVERSION='-mv78xx0' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-mv78xx0' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' build-arch_armel_none_orion5x: build-arch_armel_none_orion5x_real build-arch_armel_none_orion5x_real:: - $(MAKE) -f debian/rules.real build-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='armel' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='orion5x' KCONFIG='debian/config/config debian/config/armel/config debian/config/armel/config.orion5x' KERNEL_ARCH='arm' LOCALVERSION='-orion5x' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-orion5x' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real build-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='armel' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='orion5x' KCONFIG='debian/config/config debian/config/armel/config debian/config/armel/config.orion5x' KERNEL_ARCH='arm' LOCALVERSION='-orion5x' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-orion5x' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' build-arch_armel_none_real: build-arch_armel_none_versatile: build-arch_armel_none_versatile_real build-arch_armel_none_versatile_real:: - $(MAKE) -f debian/rules.real build-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='armel' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='versatile' KCONFIG='debian/config/config debian/config/armel/config debian/config/armel/config.versatile' KERNEL_ARCH='arm' LOCALVERSION='-versatile' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-versatile' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real build-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='armel' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='versatile' KCONFIG='debian/config/config debian/config/armel/config debian/config/armel/config.versatile' KERNEL_ARCH='arm' LOCALVERSION='-versatile' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-versatile' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' build-arch_armel_real: build-arch_armhf: build-arch_armhf_none build-arch_armhf_real -build-arch_armhf_none: build-arch_armhf_none_mx5 build-arch_armhf_none_omap build-arch_armhf_none_real build-arch_armhf_none_vexpress -build-arch_armhf_none_mx5: build-arch_armhf_none_mx5_real -build-arch_armhf_none_mx5_real:: - $(MAKE) -f debian/rules.real build-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='armhf' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='mx5' KCONFIG='debian/config/config debian/config/armel/config debian/config/armhf/config debian/config/armhf/config.mx5' KERNEL_ARCH='arm' LOCALVERSION='-mx5' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-mx5' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' -build-arch_armhf_none_omap: build-arch_armhf_none_omap_real -build-arch_armhf_none_omap_real:: - $(MAKE) -f debian/rules.real build-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='armhf' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='omap' KCONFIG='debian/config/config debian/config/armel/config debian/config/armhf/config debian/config/armhf/config.omap' KERNEL_ARCH='arm' LOCALVERSION='-omap' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-omap' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' +build-arch_armhf_none: build-arch_armhf_none_real build-arch_armhf_none_rpi build-arch_armhf_none_real: -build-arch_armhf_none_vexpress: build-arch_armhf_none_vexpress_real -build-arch_armhf_none_vexpress_real:: - $(MAKE) -f debian/rules.real build-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='armhf' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='vexpress' KCONFIG='debian/config/config debian/config/armel/config debian/config/armhf/config debian/config/armhf/config.vexpress' KERNEL_ARCH='arm' LOCALVERSION='-vexpress' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-vexpress' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' +build-arch_armhf_none_rpi: build-arch_armhf_none_rpi_real +build-arch_armhf_none_rpi_real:: + $(MAKE) -f debian/rules.real build-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='armhf' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='rpi' KCONFIG='debian/config/config debian/config/armel/config debian/config/armhf/config debian/config/armhf/config.rpi' KERNEL_ARCH='arm' LOCALVERSION='-rpi' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-rpi' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' build-arch_armhf_real: build-arch_hppa: build-arch_hppa_none build-arch_hppa_real build-arch_hppa_none: build-arch_hppa_none_parisc build-arch_hppa_none_parisc-smp build-arch_hppa_none_parisc64 build-arch_hppa_none_parisc64-smp build-arch_hppa_none_real build-arch_hppa_none_parisc: build-arch_hppa_none_parisc_real build-arch_hppa_none_parisc-smp: build-arch_hppa_none_parisc-smp_real build-arch_hppa_none_parisc-smp_real:: - $(MAKE) -f debian/rules.real build-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='hppa' COMPILER='gcc-4.4' FEATURESET='none' FLAVOUR='parisc-smp' KCONFIG='debian/config/config debian/config/hppa/config debian/config/hppa/config.parisc-smp' KERNEL_ARCH='parisc' LOCALVERSION='-parisc-smp' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-parisc-smp' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real build-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='hppa' COMPILER='gcc-4.4' FEATURESET='none' FLAVOUR='parisc-smp' KCONFIG='debian/config/config debian/config/hppa/config debian/config/hppa/config.parisc-smp' KERNEL_ARCH='parisc' LOCALVERSION='-parisc-smp' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-parisc-smp' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' build-arch_hppa_none_parisc64: build-arch_hppa_none_parisc64_real build-arch_hppa_none_parisc64-smp: build-arch_hppa_none_parisc64-smp_real build-arch_hppa_none_parisc64-smp_real:: - $(MAKE) -f debian/rules.real build-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='hppa' CFLAGS_KERNEL='-fno-cse-follow-jumps' COMPILER='gcc-4.4' FEATURESET='none' FLAVOUR='parisc64-smp' KCONFIG='debian/config/config debian/config/hppa/config debian/config/hppa/config.parisc64-smp' KERNEL_ARCH='parisc' LOCALVERSION='-parisc64-smp' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-parisc64-smp' MODULES='True' OVERRIDE_HOST_TYPE='hppa64-linux-gnu' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real build-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='hppa' CFLAGS_KERNEL='-fno-cse-follow-jumps' COMPILER='gcc-4.4' FEATURESET='none' FLAVOUR='parisc64-smp' KCONFIG='debian/config/config debian/config/hppa/config debian/config/hppa/config.parisc64-smp' KERNEL_ARCH='parisc' LOCALVERSION='-parisc64-smp' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-parisc64-smp' MODULES='True' OVERRIDE_HOST_TYPE='hppa64-linux-gnu' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' build-arch_hppa_none_parisc64_real:: - $(MAKE) -f debian/rules.real build-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='hppa' CFLAGS_KERNEL='-fno-cse-follow-jumps' COMPILER='gcc-4.4' FEATURESET='none' FLAVOUR='parisc64' KCONFIG='debian/config/config debian/config/hppa/config debian/config/hppa/config.parisc64' KERNEL_ARCH='parisc' LOCALVERSION='-parisc64' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-parisc64' MODULES='True' OVERRIDE_HOST_TYPE='hppa64-linux-gnu' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real build-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='hppa' CFLAGS_KERNEL='-fno-cse-follow-jumps' COMPILER='gcc-4.4' FEATURESET='none' FLAVOUR='parisc64' KCONFIG='debian/config/config debian/config/hppa/config debian/config/hppa/config.parisc64' KERNEL_ARCH='parisc' LOCALVERSION='-parisc64' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-parisc64' MODULES='True' OVERRIDE_HOST_TYPE='hppa64-linux-gnu' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' build-arch_hppa_none_parisc_real:: - $(MAKE) -f debian/rules.real build-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='hppa' COMPILER='gcc-4.4' FEATURESET='none' FLAVOUR='parisc' KCONFIG='debian/config/config debian/config/hppa/config debian/config/hppa/config.parisc' KERNEL_ARCH='parisc' LOCALVERSION='-parisc' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-parisc' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real build-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='hppa' COMPILER='gcc-4.4' FEATURESET='none' FLAVOUR='parisc' KCONFIG='debian/config/config debian/config/hppa/config debian/config/hppa/config.parisc' KERNEL_ARCH='parisc' LOCALVERSION='-parisc' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-parisc' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' build-arch_hppa_none_real: build-arch_hppa_real: build-arch_i386: build-arch_i386_none build-arch_i386_real build-arch_i386_rt build-arch_i386_none: build-arch_i386_none_486 build-arch_i386_none_686-pae build-arch_i386_none_amd64 build-arch_i386_none_real build-arch_i386_none_486: build-arch_i386_none_486_real build-arch_i386_none_486_real:: - $(MAKE) -f debian/rules.real build-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='i386' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='486' KCONFIG='debian/config/config debian/config/kernelarch-x86/config debian/config/kernelarch-x86/config-arch-32 debian/config/i386/none/config.486' KERNEL_ARCH='x86' LOCALVERSION='-486' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-486' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real build-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='i386' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='486' KCONFIG='debian/config/config debian/config/kernelarch-x86/config debian/config/kernelarch-x86/config-arch-32 debian/config/i386/none/config.486' KERNEL_ARCH='x86' LOCALVERSION='-486' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-486' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' build-arch_i386_none_686-pae: build-arch_i386_none_686-pae_real build-arch_i386_none_686-pae_real:: - $(MAKE) -f debian/rules.real build-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='i386' COMPILER='gcc-4.6' DEBUG='True' FEATURESET='none' FLAVOUR='686-pae' KCONFIG='debian/config/config debian/config/kernelarch-x86/config debian/config/kernelarch-x86/config-arch-32 debian/config/i386/none/config.686-pae' KCONFIG_OPTIONS='-o DEBUG_INFO=y' KERNEL_ARCH='x86' LOCALVERSION='-686-pae' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-686-pae' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real build-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='i386' COMPILER='gcc-4.6' DEBUG='True' FEATURESET='none' FLAVOUR='686-pae' KCONFIG='debian/config/config debian/config/kernelarch-x86/config debian/config/kernelarch-x86/config-arch-32 debian/config/i386/none/config.686-pae' KCONFIG_OPTIONS='-o DEBUG_INFO=y' KERNEL_ARCH='x86' LOCALVERSION='-686-pae' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-686-pae' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' build-arch_i386_none_amd64: build-arch_i386_none_amd64_real build-arch_i386_none_amd64_real:: - $(MAKE) -f debian/rules.real build-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='i386' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='amd64' KCONFIG='debian/config/config debian/config/kernelarch-x86/config debian/config/kernelarch-x86/config-arch-64' KERNEL_ARCH='x86' LOCALVERSION='-amd64' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-amd64' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real build-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='i386' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='amd64' KCONFIG='debian/config/config debian/config/kernelarch-x86/config debian/config/kernelarch-x86/config-arch-64' KERNEL_ARCH='x86' LOCALVERSION='-amd64' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-amd64' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' build-arch_i386_none_real: build-arch_i386_real: build-arch_i386_rt: build-arch_i386_rt_686-pae build-arch_i386_rt_real build-arch_i386_rt_686-pae: build-arch_i386_rt_686-pae_real build-arch_i386_rt_686-pae_real:: - $(MAKE) -f debian/rules.real build-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='i386' COMPILER='gcc-4.6' DEBUG='True' FEATURESET='rt' FLAVOUR='686-pae' KCONFIG='debian/config/config debian/config/kernelarch-x86/config debian/config/kernelarch-x86/config-arch-32 debian/config/featureset-rt/config debian/config/i386/rt/config.686-pae' KCONFIG_OPTIONS='-o DEBUG_INFO=y' KERNEL_ARCH='x86' LOCALVERSION='-rt-686-pae' LOCALVERSION_HEADERS='-rt' LOCALVERSION_IMAGE='-rt-686-pae' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real build-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='i386' COMPILER='gcc-4.6' DEBUG='True' FEATURESET='rt' FLAVOUR='686-pae' KCONFIG='debian/config/config debian/config/kernelarch-x86/config debian/config/kernelarch-x86/config-arch-32 debian/config/featureset-rt/config debian/config/i386/rt/config.686-pae' KCONFIG_OPTIONS='-o DEBUG_INFO=y' KERNEL_ARCH='x86' LOCALVERSION='-rt-686-pae' LOCALVERSION_HEADERS='-rt' LOCALVERSION_IMAGE='-rt-686-pae' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' build-arch_i386_rt_real: build-arch_ia64: build-arch_ia64_none build-arch_ia64_real build-arch_ia64_none: build-arch_ia64_none_itanium build-arch_ia64_none_mckinley build-arch_ia64_none_real build-arch_ia64_none_itanium: build-arch_ia64_none_itanium_real build-arch_ia64_none_itanium_real:: - $(MAKE) -f debian/rules.real build-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='ia64' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='itanium' KCONFIG='debian/config/config debian/config/ia64/config debian/config/ia64/config.itanium' KERNEL_ARCH='ia64' LOCALVERSION='-itanium' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-itanium' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real build-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='ia64' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='itanium' KCONFIG='debian/config/config debian/config/ia64/config debian/config/ia64/config.itanium' KERNEL_ARCH='ia64' LOCALVERSION='-itanium' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-itanium' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' build-arch_ia64_none_mckinley: build-arch_ia64_none_mckinley_real build-arch_ia64_none_mckinley_real:: - $(MAKE) -f debian/rules.real build-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='ia64' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='mckinley' KCONFIG='debian/config/config debian/config/ia64/config debian/config/ia64/config.mckinley' KERNEL_ARCH='ia64' LOCALVERSION='-mckinley' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-mckinley' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real build-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='ia64' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='mckinley' KCONFIG='debian/config/config debian/config/ia64/config debian/config/ia64/config.mckinley' KERNEL_ARCH='ia64' LOCALVERSION='-mckinley' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-mckinley' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' build-arch_ia64_none_real: build-arch_ia64_real: build-arch_m68k: build-arch_m68k_none build-arch_m68k_real build-arch_m68k_none: build-arch_m68k_none_amiga build-arch_m68k_none_atari build-arch_m68k_none_bvme6000 build-arch_m68k_none_mac build-arch_m68k_none_mvme147 build-arch_m68k_none_mvme16x build-arch_m68k_none_real build-arch_m68k_none_amiga: build-arch_m68k_none_amiga_real build-arch_m68k_none_amiga_real:: - $(MAKE) -f debian/rules.real build-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='m68k' CFLAGS_KERNEL='-ffreestanding' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='amiga' INITRAMFS='False' KCONFIG='debian/config/config debian/config/m68k/config debian/config/m68k/config.amiga' KERNEL_ARCH='m68k' LOCALVERSION='-amiga' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-amiga' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real build-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='m68k' CFLAGS_KERNEL='-ffreestanding' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='amiga' INITRAMFS='False' KCONFIG='debian/config/config debian/config/m68k/config debian/config/m68k/config.amiga' KERNEL_ARCH='m68k' LOCALVERSION='-amiga' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-amiga' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' build-arch_m68k_none_atari: build-arch_m68k_none_atari_real build-arch_m68k_none_atari_real:: - $(MAKE) -f debian/rules.real build-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='m68k' CFLAGS_KERNEL='-ffreestanding' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='atari' INITRAMFS='False' KCONFIG='debian/config/config debian/config/m68k/config debian/config/m68k/config.atari' KERNEL_ARCH='m68k' LOCALVERSION='-atari' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-atari' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real build-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='m68k' CFLAGS_KERNEL='-ffreestanding' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='atari' INITRAMFS='False' KCONFIG='debian/config/config debian/config/m68k/config debian/config/m68k/config.atari' KERNEL_ARCH='m68k' LOCALVERSION='-atari' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-atari' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' build-arch_m68k_none_bvme6000: build-arch_m68k_none_bvme6000_real build-arch_m68k_none_bvme6000_real:: - $(MAKE) -f debian/rules.real build-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='m68k' CFLAGS_KERNEL='-ffreestanding' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='bvme6000' INITRAMFS='False' KCONFIG='debian/config/config debian/config/m68k/config debian/config/m68k/config.bvme6000' KERNEL_ARCH='m68k' LOCALVERSION='-bvme6000' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-bvme6000' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real build-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='m68k' CFLAGS_KERNEL='-ffreestanding' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='bvme6000' INITRAMFS='False' KCONFIG='debian/config/config debian/config/m68k/config debian/config/m68k/config.bvme6000' KERNEL_ARCH='m68k' LOCALVERSION='-bvme6000' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-bvme6000' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' build-arch_m68k_none_mac: build-arch_m68k_none_mac_real build-arch_m68k_none_mac_real:: - $(MAKE) -f debian/rules.real build-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='m68k' CFLAGS_KERNEL='-ffreestanding' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='mac' INITRAMFS='False' KCONFIG='debian/config/config debian/config/m68k/config debian/config/m68k/config.mac' KERNEL_ARCH='m68k' LOCALVERSION='-mac' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-mac' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real build-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='m68k' CFLAGS_KERNEL='-ffreestanding' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='mac' INITRAMFS='False' KCONFIG='debian/config/config debian/config/m68k/config debian/config/m68k/config.mac' KERNEL_ARCH='m68k' LOCALVERSION='-mac' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-mac' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' build-arch_m68k_none_mvme147: build-arch_m68k_none_mvme147_real build-arch_m68k_none_mvme147_real:: - $(MAKE) -f debian/rules.real build-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='m68k' CFLAGS_KERNEL='-ffreestanding' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='mvme147' INITRAMFS='False' KCONFIG='debian/config/config debian/config/m68k/config debian/config/m68k/config.mvme147' KERNEL_ARCH='m68k' LOCALVERSION='-mvme147' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-mvme147' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real build-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='m68k' CFLAGS_KERNEL='-ffreestanding' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='mvme147' INITRAMFS='False' KCONFIG='debian/config/config debian/config/m68k/config debian/config/m68k/config.mvme147' KERNEL_ARCH='m68k' LOCALVERSION='-mvme147' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-mvme147' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' build-arch_m68k_none_mvme16x: build-arch_m68k_none_mvme16x_real build-arch_m68k_none_mvme16x_real:: - $(MAKE) -f debian/rules.real build-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='m68k' CFLAGS_KERNEL='-ffreestanding' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='mvme16x' INITRAMFS='False' KCONFIG='debian/config/config debian/config/m68k/config debian/config/m68k/config.mvme16x' KERNEL_ARCH='m68k' LOCALVERSION='-mvme16x' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-mvme16x' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real build-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='m68k' CFLAGS_KERNEL='-ffreestanding' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='mvme16x' INITRAMFS='False' KCONFIG='debian/config/config debian/config/m68k/config debian/config/m68k/config.mvme16x' KERNEL_ARCH='m68k' LOCALVERSION='-mvme16x' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-mvme16x' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' build-arch_m68k_none_real: build-arch_m68k_real: build-arch_mips: build-arch_mips_none build-arch_mips_real build-arch_mips_none: build-arch_mips_none_4kc-malta build-arch_mips_none_5kc-malta build-arch_mips_none_octeon build-arch_mips_none_r4k-ip22 build-arch_mips_none_r5k-ip32 build-arch_mips_none_real build-arch_mips_none_sb1-bcm91250a build-arch_mips_none_sb1a-bcm91480b build-arch_mips_none_4kc-malta: build-arch_mips_none_4kc-malta_real build-arch_mips_none_4kc-malta_real:: - $(MAKE) -f debian/rules.real build-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='mips' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='4kc-malta' INITRAMFS='False' KCONFIG='debian/config/config debian/config/kernelarch-mips/config debian/config/mips/config debian/config/mips/config.4kc-malta' KERNEL_ARCH='mips' LOCALVERSION='-4kc-malta' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-4kc-malta' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real build-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='mips' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='4kc-malta' INITRAMFS='False' KCONFIG='debian/config/config debian/config/kernelarch-mips/config debian/config/mips/config debian/config/mips/config.4kc-malta' KERNEL_ARCH='mips' LOCALVERSION='-4kc-malta' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-4kc-malta' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' build-arch_mips_none_5kc-malta: build-arch_mips_none_5kc-malta_real build-arch_mips_none_5kc-malta_real:: - $(MAKE) -f debian/rules.real build-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='mips' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='5kc-malta' INITRAMFS='False' KCONFIG='debian/config/config debian/config/kernelarch-mips/config debian/config/mips/config debian/config/mips/config.5kc-malta' KERNEL_ARCH='mips' LOCALVERSION='-5kc-malta' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-5kc-malta' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real build-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='mips' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='5kc-malta' INITRAMFS='False' KCONFIG='debian/config/config debian/config/kernelarch-mips/config debian/config/mips/config debian/config/mips/config.5kc-malta' KERNEL_ARCH='mips' LOCALVERSION='-5kc-malta' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-5kc-malta' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' build-arch_mips_none_octeon: build-arch_mips_none_octeon_real build-arch_mips_none_octeon_real:: - $(MAKE) -f debian/rules.real build-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='mips' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='octeon' INITRAMFS='False' KCONFIG='debian/config/config debian/config/kernelarch-mips/config debian/config/mips/config debian/config/mips/config.octeon' KERNEL_ARCH='mips' LOCALVERSION='-octeon' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-octeon' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real build-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='mips' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='octeon' INITRAMFS='False' KCONFIG='debian/config/config debian/config/kernelarch-mips/config debian/config/mips/config debian/config/mips/config.octeon' KERNEL_ARCH='mips' LOCALVERSION='-octeon' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-octeon' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' build-arch_mips_none_r4k-ip22: build-arch_mips_none_r4k-ip22_real build-arch_mips_none_r4k-ip22_real:: - $(MAKE) -f debian/rules.real build-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='mips' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='r4k-ip22' INITRAMFS='False' KCONFIG='debian/config/config debian/config/kernelarch-mips/config debian/config/mips/config debian/config/mips/config.r4k-ip22' KERNEL_ARCH='mips' LOCALVERSION='-r4k-ip22' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-r4k-ip22' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real build-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='mips' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='r4k-ip22' INITRAMFS='False' KCONFIG='debian/config/config debian/config/kernelarch-mips/config debian/config/mips/config debian/config/mips/config.r4k-ip22' KERNEL_ARCH='mips' LOCALVERSION='-r4k-ip22' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-r4k-ip22' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' build-arch_mips_none_r5k-ip32: build-arch_mips_none_r5k-ip32_real build-arch_mips_none_r5k-ip32_real:: - $(MAKE) -f debian/rules.real build-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='mips' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='r5k-ip32' INITRAMFS='False' KCONFIG='debian/config/config debian/config/kernelarch-mips/config debian/config/mips/config debian/config/mips/config.r5k-ip32' KERNEL_ARCH='mips' LOCALVERSION='-r5k-ip32' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-r5k-ip32' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real build-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='mips' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='r5k-ip32' INITRAMFS='False' KCONFIG='debian/config/config debian/config/kernelarch-mips/config debian/config/mips/config debian/config/mips/config.r5k-ip32' KERNEL_ARCH='mips' LOCALVERSION='-r5k-ip32' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-r5k-ip32' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' build-arch_mips_none_real: build-arch_mips_none_sb1-bcm91250a: build-arch_mips_none_sb1-bcm91250a_real build-arch_mips_none_sb1-bcm91250a_real:: - $(MAKE) -f debian/rules.real build-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='mips' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='sb1-bcm91250a' INITRAMFS='False' KCONFIG='debian/config/config debian/config/kernelarch-mips/config debian/config/mips/config debian/config/mips/config.sb1-bcm91250a' KERNEL_ARCH='mips' LOCALVERSION='-sb1-bcm91250a' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-sb1-bcm91250a' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real build-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='mips' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='sb1-bcm91250a' INITRAMFS='False' KCONFIG='debian/config/config debian/config/kernelarch-mips/config debian/config/mips/config debian/config/mips/config.sb1-bcm91250a' KERNEL_ARCH='mips' LOCALVERSION='-sb1-bcm91250a' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-sb1-bcm91250a' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' build-arch_mips_none_sb1a-bcm91480b: build-arch_mips_none_sb1a-bcm91480b_real build-arch_mips_none_sb1a-bcm91480b_real:: - $(MAKE) -f debian/rules.real build-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='mips' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='sb1a-bcm91480b' INITRAMFS='False' KCONFIG='debian/config/config debian/config/kernelarch-mips/config debian/config/mips/config debian/config/mips/config.sb1a-bcm91480b' KERNEL_ARCH='mips' LOCALVERSION='-sb1a-bcm91480b' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-sb1a-bcm91480b' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real build-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='mips' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='sb1a-bcm91480b' INITRAMFS='False' KCONFIG='debian/config/config debian/config/kernelarch-mips/config debian/config/mips/config debian/config/mips/config.sb1a-bcm91480b' KERNEL_ARCH='mips' LOCALVERSION='-sb1a-bcm91480b' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-sb1a-bcm91480b' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' build-arch_mips_real: build-arch_mipsel: build-arch_mipsel_none build-arch_mipsel_real build-arch_mipsel_none: build-arch_mipsel_none_4kc-malta build-arch_mipsel_none_5kc-malta build-arch_mipsel_none_loongson-2f build-arch_mipsel_none_r5k-cobalt build-arch_mipsel_none_real build-arch_mipsel_none_sb1-bcm91250a build-arch_mipsel_none_sb1a-bcm91480b build-arch_mipsel_none_4kc-malta: build-arch_mipsel_none_4kc-malta_real build-arch_mipsel_none_4kc-malta_real:: - $(MAKE) -f debian/rules.real build-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='mipsel' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='4kc-malta' INITRAMFS='False' KCONFIG='debian/config/config debian/config/kernelarch-mips/config debian/config/mipsel/config debian/config/mips/config.4kc-malta' KERNEL_ARCH='mips' LOCALVERSION='-4kc-malta' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-4kc-malta' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real build-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='mipsel' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='4kc-malta' INITRAMFS='False' KCONFIG='debian/config/config debian/config/kernelarch-mips/config debian/config/mipsel/config debian/config/mips/config.4kc-malta' KERNEL_ARCH='mips' LOCALVERSION='-4kc-malta' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-4kc-malta' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' build-arch_mipsel_none_5kc-malta: build-arch_mipsel_none_5kc-malta_real build-arch_mipsel_none_5kc-malta_real:: - $(MAKE) -f debian/rules.real build-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='mipsel' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='5kc-malta' INITRAMFS='False' KCONFIG='debian/config/config debian/config/kernelarch-mips/config debian/config/mipsel/config debian/config/mips/config.5kc-malta' KERNEL_ARCH='mips' LOCALVERSION='-5kc-malta' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-5kc-malta' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real build-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='mipsel' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='5kc-malta' INITRAMFS='False' KCONFIG='debian/config/config debian/config/kernelarch-mips/config debian/config/mipsel/config debian/config/mips/config.5kc-malta' KERNEL_ARCH='mips' LOCALVERSION='-5kc-malta' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-5kc-malta' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' build-arch_mipsel_none_loongson-2f: build-arch_mipsel_none_loongson-2f_real build-arch_mipsel_none_loongson-2f_real:: - $(MAKE) -f debian/rules.real build-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='mipsel' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='loongson-2f' INITRAMFS='False' KCONFIG='debian/config/config debian/config/kernelarch-mips/config debian/config/mipsel/config debian/config/mipsel/config.loongson-2f' KERNEL_ARCH='mips' LOCALVERSION='-loongson-2f' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-loongson-2f' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real build-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='mipsel' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='loongson-2f' INITRAMFS='False' KCONFIG='debian/config/config debian/config/kernelarch-mips/config debian/config/mipsel/config debian/config/mipsel/config.loongson-2f' KERNEL_ARCH='mips' LOCALVERSION='-loongson-2f' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-loongson-2f' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' build-arch_mipsel_none_r5k-cobalt: build-arch_mipsel_none_r5k-cobalt_real build-arch_mipsel_none_r5k-cobalt_real:: - $(MAKE) -f debian/rules.real build-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='mipsel' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='r5k-cobalt' INITRAMFS='False' KCONFIG='debian/config/config debian/config/kernelarch-mips/config debian/config/mipsel/config debian/config/mipsel/config.r5k-cobalt' KERNEL_ARCH='mips' LOCALVERSION='-r5k-cobalt' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-r5k-cobalt' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real build-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='mipsel' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='r5k-cobalt' INITRAMFS='False' KCONFIG='debian/config/config debian/config/kernelarch-mips/config debian/config/mipsel/config debian/config/mipsel/config.r5k-cobalt' KERNEL_ARCH='mips' LOCALVERSION='-r5k-cobalt' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-r5k-cobalt' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' build-arch_mipsel_none_real: build-arch_mipsel_none_sb1-bcm91250a: build-arch_mipsel_none_sb1-bcm91250a_real build-arch_mipsel_none_sb1-bcm91250a_real:: - $(MAKE) -f debian/rules.real build-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='mipsel' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='sb1-bcm91250a' INITRAMFS='False' KCONFIG='debian/config/config debian/config/kernelarch-mips/config debian/config/mipsel/config debian/config/mips/config.sb1-bcm91250a' KERNEL_ARCH='mips' LOCALVERSION='-sb1-bcm91250a' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-sb1-bcm91250a' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real build-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='mipsel' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='sb1-bcm91250a' INITRAMFS='False' KCONFIG='debian/config/config debian/config/kernelarch-mips/config debian/config/mipsel/config debian/config/mips/config.sb1-bcm91250a' KERNEL_ARCH='mips' LOCALVERSION='-sb1-bcm91250a' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-sb1-bcm91250a' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' build-arch_mipsel_none_sb1a-bcm91480b: build-arch_mipsel_none_sb1a-bcm91480b_real build-arch_mipsel_none_sb1a-bcm91480b_real:: - $(MAKE) -f debian/rules.real build-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='mipsel' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='sb1a-bcm91480b' INITRAMFS='False' KCONFIG='debian/config/config debian/config/kernelarch-mips/config debian/config/mipsel/config debian/config/mips/config.sb1a-bcm91480b' KERNEL_ARCH='mips' LOCALVERSION='-sb1a-bcm91480b' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-sb1a-bcm91480b' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real build-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='mipsel' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='sb1a-bcm91480b' INITRAMFS='False' KCONFIG='debian/config/config debian/config/kernelarch-mips/config debian/config/mipsel/config debian/config/mips/config.sb1a-bcm91480b' KERNEL_ARCH='mips' LOCALVERSION='-sb1a-bcm91480b' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-sb1a-bcm91480b' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' build-arch_mipsel_real: build-arch_powerpc: build-arch_powerpc_none build-arch_powerpc_real build-arch_powerpc_none: build-arch_powerpc_none_powerpc build-arch_powerpc_none_powerpc-smp build-arch_powerpc_none_powerpc64 build-arch_powerpc_none_real build-arch_powerpc_none_powerpc: build-arch_powerpc_none_powerpc_real build-arch_powerpc_none_powerpc-smp: build-arch_powerpc_none_powerpc-smp_real build-arch_powerpc_none_powerpc-smp_real:: - $(MAKE) -f debian/rules.real build-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='powerpc' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='powerpc-smp' KCONFIG='debian/config/config debian/config/powerpc/config debian/config/powerpc/config.powerpc debian/config/powerpc/config.powerpc-smp' KERNEL_ARCH='powerpc' LOCALVERSION='-powerpc-smp' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-powerpc-smp' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real build-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='powerpc' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='powerpc-smp' KCONFIG='debian/config/config debian/config/powerpc/config debian/config/powerpc/config.powerpc debian/config/powerpc/config.powerpc-smp' KERNEL_ARCH='powerpc' LOCALVERSION='-powerpc-smp' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-powerpc-smp' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' build-arch_powerpc_none_powerpc64: build-arch_powerpc_none_powerpc64_real build-arch_powerpc_none_powerpc64_real:: - $(MAKE) -f debian/rules.real build-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='powerpc' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='powerpc64' KCONFIG='debian/config/config debian/config/powerpc/config debian/config/powerpc/config.powerpc64' KERNEL_ARCH='powerpc' LOCALVERSION='-powerpc64' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-powerpc64' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real build-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='powerpc' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='powerpc64' KCONFIG='debian/config/config debian/config/powerpc/config debian/config/powerpc/config.powerpc64' KERNEL_ARCH='powerpc' LOCALVERSION='-powerpc64' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-powerpc64' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' build-arch_powerpc_none_powerpc_real:: - $(MAKE) -f debian/rules.real build-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='powerpc' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='powerpc' KCONFIG='debian/config/config debian/config/powerpc/config debian/config/powerpc/config.powerpc' KERNEL_ARCH='powerpc' LOCALVERSION='-powerpc' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-powerpc' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real build-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='powerpc' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='powerpc' KCONFIG='debian/config/config debian/config/powerpc/config debian/config/powerpc/config.powerpc' KERNEL_ARCH='powerpc' LOCALVERSION='-powerpc' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-powerpc' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' build-arch_powerpc_none_real: build-arch_powerpc_real: build-arch_ppc64: build-arch_ppc64_none build-arch_ppc64_real build-arch_ppc64_none: build-arch_ppc64_none_powerpc64 build-arch_ppc64_none_real build-arch_ppc64_none_powerpc64: build-arch_ppc64_none_powerpc64_real build-arch_ppc64_none_powerpc64_real:: - $(MAKE) -f debian/rules.real build-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='ppc64' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='powerpc64' KCONFIG='debian/config/config debian/config/powerpc/config debian/config/powerpc/config.powerpc64' KERNEL_ARCH='powerpc' LOCALVERSION='-powerpc64' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-powerpc64' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real build-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='ppc64' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='powerpc64' KCONFIG='debian/config/config debian/config/powerpc/config debian/config/powerpc/config.powerpc64' KERNEL_ARCH='powerpc' LOCALVERSION='-powerpc64' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-powerpc64' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' build-arch_ppc64_none_real: build-arch_ppc64_real: build-arch_s390: build-arch_s390_none build-arch_s390_real @@ -567,9 +555,9 @@ build-arch_s390_none_s390x: build-arch_s390_none_s390x_real build-arch_s390_none_s390x-tape: build-arch_s390_none_s390x-tape_real build-arch_s390_none_s390x-tape_real:: - $(MAKE) -f debian/rules.real build-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='s390' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='s390x-tape' INITRAMFS='False' KCONFIG='debian/config/config debian/config/s390/config debian/config/s390/config.s390x-tape' KERNEL_ARCH='s390' LOCALVERSION='-s390x-tape' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-s390x' SOURCEVERSION='3.2.46-1' TYPE='plain-s390-tape' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real build-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='s390' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='s390x-tape' INITRAMFS='False' KCONFIG='debian/config/config debian/config/s390/config debian/config/s390/config.s390x-tape' KERNEL_ARCH='s390' LOCALVERSION='-s390x-tape' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-s390x' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain-s390-tape' UPSTREAMVERSION='3.2' VERSION='3.2' build-arch_s390_none_s390x_real:: - $(MAKE) -f debian/rules.real build-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='s390' COMPILER='gcc-4.6' DEBUG='True' FEATURESET='none' FLAVOUR='s390x' KCONFIG='debian/config/config debian/config/s390/config debian/config/s390/config.s390x' KCONFIG_OPTIONS='-o DEBUG_INFO=y' KERNEL_ARCH='s390' LOCALVERSION='-s390x' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-s390x' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real build-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='s390' COMPILER='gcc-4.6' DEBUG='True' FEATURESET='none' FLAVOUR='s390x' KCONFIG='debian/config/config debian/config/s390/config debian/config/s390/config.s390x' KCONFIG_OPTIONS='-o DEBUG_INFO=y' KERNEL_ARCH='s390' LOCALVERSION='-s390x' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-s390x' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' build-arch_s390_real: build-arch_s390x: build-arch_s390x_none build-arch_s390x_real build-arch_s390x_none: build-arch_s390x_none_real build-arch_s390x_none_s390x build-arch_s390x_none_s390x-tape @@ -577,19 +565,19 @@ build-arch_s390x_none_s390x: build-arch_s390x_none_s390x_real build-arch_s390x_none_s390x-tape: build-arch_s390x_none_s390x-tape_real build-arch_s390x_none_s390x-tape_real:: - $(MAKE) -f debian/rules.real build-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='s390x' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='s390x-tape' INITRAMFS='False' KCONFIG='debian/config/config debian/config/s390/config debian/config/s390/config.s390x-tape' KERNEL_ARCH='s390' LOCALVERSION='-s390x-tape' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-s390x' SOURCEVERSION='3.2.46-1' TYPE='plain-s390-tape' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real build-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='s390x' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='s390x-tape' INITRAMFS='False' KCONFIG='debian/config/config debian/config/s390/config debian/config/s390/config.s390x-tape' KERNEL_ARCH='s390' LOCALVERSION='-s390x-tape' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-s390x' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain-s390-tape' UPSTREAMVERSION='3.2' VERSION='3.2' build-arch_s390x_none_s390x_real:: - $(MAKE) -f debian/rules.real build-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='s390x' COMPILER='gcc-4.6' DEBUG='True' FEATURESET='none' FLAVOUR='s390x' KCONFIG='debian/config/config debian/config/s390/config debian/config/s390/config.s390x' KCONFIG_OPTIONS='-o DEBUG_INFO=y' KERNEL_ARCH='s390' LOCALVERSION='-s390x' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-s390x' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real build-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='s390x' COMPILER='gcc-4.6' DEBUG='True' FEATURESET='none' FLAVOUR='s390x' KCONFIG='debian/config/config debian/config/s390/config debian/config/s390/config.s390x' KCONFIG_OPTIONS='-o DEBUG_INFO=y' KERNEL_ARCH='s390' LOCALVERSION='-s390x' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-s390x' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' build-arch_s390x_real: build-arch_sh4: build-arch_sh4_none build-arch_sh4_real build-arch_sh4_none: build-arch_sh4_none_real build-arch_sh4_none_sh7751r build-arch_sh4_none_sh7785lcr build-arch_sh4_none_real: build-arch_sh4_none_sh7751r: build-arch_sh4_none_sh7751r_real build-arch_sh4_none_sh7751r_real:: - $(MAKE) -f debian/rules.real build-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='sh4' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='sh7751r' KCONFIG='debian/config/config debian/config/sh4/config debian/config/sh4/config.sh7751r' KERNEL_ARCH='sh' LOCALVERSION='-sh7751r' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-sh7751r' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real build-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='sh4' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='sh7751r' KCONFIG='debian/config/config debian/config/sh4/config debian/config/sh4/config.sh7751r' KERNEL_ARCH='sh' LOCALVERSION='-sh7751r' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-sh7751r' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' build-arch_sh4_none_sh7785lcr: build-arch_sh4_none_sh7785lcr_real build-arch_sh4_none_sh7785lcr_real:: - $(MAKE) -f debian/rules.real build-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='sh4' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='sh7785lcr' KCONFIG='debian/config/config debian/config/sh4/config debian/config/sh4/config.sh7785lcr' KERNEL_ARCH='sh' LOCALVERSION='-sh7785lcr' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-sh7785lcr' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real build-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='sh4' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='sh7785lcr' KCONFIG='debian/config/config debian/config/sh4/config debian/config/sh4/config.sh7785lcr' KERNEL_ARCH='sh' LOCALVERSION='-sh7785lcr' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-sh7785lcr' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' build-arch_sh4_real: build-arch_sparc: build-arch_sparc_none build-arch_sparc_real build-arch_sparc64: build-arch_sparc64_none build-arch_sparc64_real @@ -598,213 +586,207 @@ build-arch_sparc64_none_sparc64: build-arch_sparc64_none_sparc64_real build-arch_sparc64_none_sparc64-smp: build-arch_sparc64_none_sparc64-smp_real build-arch_sparc64_none_sparc64-smp_real:: - $(MAKE) -f debian/rules.real build-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='sparc64' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='sparc64-smp' KCONFIG='debian/config/config debian/config/sparc/config debian/config/sparc/config.sparc64-smp' KERNEL_ARCH='sparc' LOCALVERSION='-sparc64-smp' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-sparc64-smp' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real build-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='sparc64' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='sparc64-smp' KCONFIG='debian/config/config debian/config/sparc/config debian/config/sparc/config.sparc64-smp' KERNEL_ARCH='sparc' LOCALVERSION='-sparc64-smp' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-sparc64-smp' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' build-arch_sparc64_none_sparc64_real:: - $(MAKE) -f debian/rules.real build-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='sparc64' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='sparc64' KCONFIG='debian/config/config debian/config/sparc/config debian/config/sparc/config.sparc64' KERNEL_ARCH='sparc' LOCALVERSION='-sparc64' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-sparc64' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real build-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='sparc64' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='sparc64' KCONFIG='debian/config/config debian/config/sparc/config debian/config/sparc/config.sparc64' KERNEL_ARCH='sparc' LOCALVERSION='-sparc64' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-sparc64' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' build-arch_sparc64_real: build-arch_sparc_none: build-arch_sparc_none_real build-arch_sparc_none_sparc64 build-arch_sparc_none_sparc64-smp build-arch_sparc_none_real: build-arch_sparc_none_sparc64: build-arch_sparc_none_sparc64_real build-arch_sparc_none_sparc64-smp: build-arch_sparc_none_sparc64-smp_real build-arch_sparc_none_sparc64-smp_real:: - $(MAKE) -f debian/rules.real build-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='sparc' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='sparc64-smp' KCONFIG='debian/config/config debian/config/sparc/config debian/config/sparc/config.sparc64-smp' KERNEL_ARCH='sparc' LOCALVERSION='-sparc64-smp' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-sparc64-smp' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real build-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='sparc' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='sparc64-smp' KCONFIG='debian/config/config debian/config/sparc/config debian/config/sparc/config.sparc64-smp' KERNEL_ARCH='sparc' LOCALVERSION='-sparc64-smp' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-sparc64-smp' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' build-arch_sparc_none_sparc64_real:: - $(MAKE) -f debian/rules.real build-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='sparc' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='sparc64' KCONFIG='debian/config/config debian/config/sparc/config debian/config/sparc/config.sparc64' KERNEL_ARCH='sparc' LOCALVERSION='-sparc64' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-sparc64' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real build-arch ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='sparc' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='sparc64' KCONFIG='debian/config/config debian/config/sparc/config debian/config/sparc/config.sparc64' KERNEL_ARCH='sparc' LOCALVERSION='-sparc64' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-sparc64' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' build-arch_sparc_real: build-indep:: - $(MAKE) -f debian/rules.real build-indep ABINAME='3.2.0-4' ABINAME_PART='-4' ALL_FEATURESETS='none rt' SOURCEVERSION='3.2.46-1' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real build-indep ABINAME='3.2.0-4' ABINAME_PART='-4' ALL_FEATURESETS='none rt' SOURCEVERSION='3.2.46-1+rpi1' UPSTREAMVERSION='3.2' VERSION='3.2' setup: setup_alpha setup_amd64 setup_armel setup_armhf setup_hppa setup_i386 setup_ia64 setup_m68k setup_mips setup_mipsel setup_powerpc setup_ppc64 setup_s390 setup_s390x setup_sh4 setup_sparc setup_sparc64 setup_alpha: setup_alpha_none setup_alpha_real setup_alpha_none: setup_alpha_none_alpha-generic setup_alpha_none_alpha-legacy setup_alpha_none_alpha-smp setup_alpha_none_real setup_alpha_none_alpha-generic: setup_alpha_none_alpha-generic_real setup_alpha_none_alpha-generic_real:: - $(MAKE) -f debian/rules.real setup-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='alpha' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='alpha-generic' KCONFIG='debian/config/config debian/config/alpha/config debian/config/alpha/config.alpha-generic' KERNEL_ARCH='alpha' LOCALVERSION='-alpha-generic' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-alpha-generic' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real setup-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='alpha' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='alpha-generic' KCONFIG='debian/config/config debian/config/alpha/config debian/config/alpha/config.alpha-generic' KERNEL_ARCH='alpha' LOCALVERSION='-alpha-generic' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-alpha-generic' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' setup_alpha_none_alpha-legacy: setup_alpha_none_alpha-legacy_real setup_alpha_none_alpha-legacy_real:: - $(MAKE) -f debian/rules.real setup-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='alpha' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='alpha-legacy' KCONFIG='debian/config/config debian/config/alpha/config debian/config/alpha/config.alpha-legacy' KERNEL_ARCH='alpha' LOCALVERSION='-alpha-legacy' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-alpha-legacy' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real setup-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='alpha' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='alpha-legacy' KCONFIG='debian/config/config debian/config/alpha/config debian/config/alpha/config.alpha-legacy' KERNEL_ARCH='alpha' LOCALVERSION='-alpha-legacy' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-alpha-legacy' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' setup_alpha_none_alpha-smp: setup_alpha_none_alpha-smp_real setup_alpha_none_alpha-smp_real:: - $(MAKE) -f debian/rules.real setup-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='alpha' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='alpha-smp' KCONFIG='debian/config/config debian/config/alpha/config debian/config/alpha/config.alpha-smp' KERNEL_ARCH='alpha' LOCALVERSION='-alpha-smp' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-alpha-smp' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real setup-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='alpha' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='alpha-smp' KCONFIG='debian/config/config debian/config/alpha/config debian/config/alpha/config.alpha-smp' KERNEL_ARCH='alpha' LOCALVERSION='-alpha-smp' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-alpha-smp' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' setup_alpha_none_real: setup_alpha_real: setup_amd64: setup_amd64_none setup_amd64_real setup_amd64_rt setup_amd64_none: setup_amd64_none_amd64 setup_amd64_none_real setup_amd64_none_amd64: setup_amd64_none_amd64_real setup_amd64_none_amd64_real:: - $(MAKE) -f debian/rules.real setup-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='amd64' COMPILER='gcc-4.6' DEBUG='True' FEATURESET='none' FLAVOUR='amd64' KCONFIG='debian/config/config debian/config/kernelarch-x86/config debian/config/kernelarch-x86/config-arch-64' KCONFIG_OPTIONS='-o DEBUG_INFO=y' KERNEL_ARCH='x86' LOCALVERSION='-amd64' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-amd64' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real setup-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='amd64' COMPILER='gcc-4.6' DEBUG='True' FEATURESET='none' FLAVOUR='amd64' KCONFIG='debian/config/config debian/config/kernelarch-x86/config debian/config/kernelarch-x86/config-arch-64' KCONFIG_OPTIONS='-o DEBUG_INFO=y' KERNEL_ARCH='x86' LOCALVERSION='-amd64' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-amd64' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' setup_amd64_none_real: setup_amd64_real: setup_amd64_rt: setup_amd64_rt_amd64 setup_amd64_rt_real setup_amd64_rt_amd64: setup_amd64_rt_amd64_real setup_amd64_rt_amd64_real:: - $(MAKE) -f debian/rules.real setup-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='amd64' COMPILER='gcc-4.6' DEBUG='True' FEATURESET='rt' FLAVOUR='amd64' KCONFIG='debian/config/config debian/config/kernelarch-x86/config debian/config/kernelarch-x86/config-arch-64 debian/config/featureset-rt/config' KCONFIG_OPTIONS='-o DEBUG_INFO=y' KERNEL_ARCH='x86' LOCALVERSION='-rt-amd64' LOCALVERSION_HEADERS='-rt' LOCALVERSION_IMAGE='-rt-amd64' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real setup-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='amd64' COMPILER='gcc-4.6' DEBUG='True' FEATURESET='rt' FLAVOUR='amd64' KCONFIG='debian/config/config debian/config/kernelarch-x86/config debian/config/kernelarch-x86/config-arch-64 debian/config/featureset-rt/config' KCONFIG_OPTIONS='-o DEBUG_INFO=y' KERNEL_ARCH='x86' LOCALVERSION='-rt-amd64' LOCALVERSION_HEADERS='-rt' LOCALVERSION_IMAGE='-rt-amd64' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' setup_amd64_rt_real: setup_armel: setup_armel_none setup_armel_real setup_armel_none: setup_armel_none_iop32x setup_armel_none_ixp4xx setup_armel_none_kirkwood setup_armel_none_mv78xx0 setup_armel_none_orion5x setup_armel_none_real setup_armel_none_versatile setup_armel_none_iop32x: setup_armel_none_iop32x_real setup_armel_none_iop32x_real:: - $(MAKE) -f debian/rules.real setup-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='armel' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='iop32x' KCONFIG='debian/config/config debian/config/armel/config debian/config/armel/config.iop32x' KERNEL_ARCH='arm' LOCALVERSION='-iop32x' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-iop32x' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real setup-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='armel' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='iop32x' KCONFIG='debian/config/config debian/config/armel/config debian/config/armel/config.iop32x' KERNEL_ARCH='arm' LOCALVERSION='-iop32x' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-iop32x' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' setup_armel_none_ixp4xx: setup_armel_none_ixp4xx_real setup_armel_none_ixp4xx_real:: - $(MAKE) -f debian/rules.real setup-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='armel' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='ixp4xx' KCONFIG='debian/config/config debian/config/armel/config debian/config/armel/config.ixp4xx' KERNEL_ARCH='arm' LOCALVERSION='-ixp4xx' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-ixp4xx' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real setup-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='armel' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='ixp4xx' KCONFIG='debian/config/config debian/config/armel/config debian/config/armel/config.ixp4xx' KERNEL_ARCH='arm' LOCALVERSION='-ixp4xx' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-ixp4xx' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' setup_armel_none_kirkwood: setup_armel_none_kirkwood_real setup_armel_none_kirkwood_real:: - $(MAKE) -f debian/rules.real setup-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='armel' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='kirkwood' KCONFIG='debian/config/config debian/config/armel/config debian/config/armel/config.kirkwood' KERNEL_ARCH='arm' LOCALVERSION='-kirkwood' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-kirkwood' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real setup-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='armel' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='kirkwood' KCONFIG='debian/config/config debian/config/armel/config debian/config/armel/config.kirkwood' KERNEL_ARCH='arm' LOCALVERSION='-kirkwood' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-kirkwood' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' setup_armel_none_mv78xx0: setup_armel_none_mv78xx0_real setup_armel_none_mv78xx0_real:: - $(MAKE) -f debian/rules.real setup-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='armel' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='mv78xx0' KCONFIG='debian/config/config debian/config/armel/config debian/config/armel/config.mv78xx0' KERNEL_ARCH='arm' LOCALVERSION='-mv78xx0' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-mv78xx0' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real setup-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='armel' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='mv78xx0' KCONFIG='debian/config/config debian/config/armel/config debian/config/armel/config.mv78xx0' KERNEL_ARCH='arm' LOCALVERSION='-mv78xx0' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-mv78xx0' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' setup_armel_none_orion5x: setup_armel_none_orion5x_real setup_armel_none_orion5x_real:: - $(MAKE) -f debian/rules.real setup-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='armel' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='orion5x' KCONFIG='debian/config/config debian/config/armel/config debian/config/armel/config.orion5x' KERNEL_ARCH='arm' LOCALVERSION='-orion5x' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-orion5x' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real setup-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='armel' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='orion5x' KCONFIG='debian/config/config debian/config/armel/config debian/config/armel/config.orion5x' KERNEL_ARCH='arm' LOCALVERSION='-orion5x' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-orion5x' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' setup_armel_none_real: setup_armel_none_versatile: setup_armel_none_versatile_real setup_armel_none_versatile_real:: - $(MAKE) -f debian/rules.real setup-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='armel' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='versatile' KCONFIG='debian/config/config debian/config/armel/config debian/config/armel/config.versatile' KERNEL_ARCH='arm' LOCALVERSION='-versatile' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-versatile' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real setup-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='armel' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='versatile' KCONFIG='debian/config/config debian/config/armel/config debian/config/armel/config.versatile' KERNEL_ARCH='arm' LOCALVERSION='-versatile' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-versatile' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' setup_armel_real: setup_armhf: setup_armhf_none setup_armhf_real -setup_armhf_none: setup_armhf_none_mx5 setup_armhf_none_omap setup_armhf_none_real setup_armhf_none_vexpress -setup_armhf_none_mx5: setup_armhf_none_mx5_real -setup_armhf_none_mx5_real:: - $(MAKE) -f debian/rules.real setup-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='armhf' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='mx5' KCONFIG='debian/config/config debian/config/armel/config debian/config/armhf/config debian/config/armhf/config.mx5' KERNEL_ARCH='arm' LOCALVERSION='-mx5' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-mx5' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' -setup_armhf_none_omap: setup_armhf_none_omap_real -setup_armhf_none_omap_real:: - $(MAKE) -f debian/rules.real setup-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='armhf' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='omap' KCONFIG='debian/config/config debian/config/armel/config debian/config/armhf/config debian/config/armhf/config.omap' KERNEL_ARCH='arm' LOCALVERSION='-omap' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-omap' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' +setup_armhf_none: setup_armhf_none_real setup_armhf_none_rpi setup_armhf_none_real: -setup_armhf_none_vexpress: setup_armhf_none_vexpress_real -setup_armhf_none_vexpress_real:: - $(MAKE) -f debian/rules.real setup-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='armhf' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='vexpress' KCONFIG='debian/config/config debian/config/armel/config debian/config/armhf/config debian/config/armhf/config.vexpress' KERNEL_ARCH='arm' LOCALVERSION='-vexpress' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-vexpress' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' +setup_armhf_none_rpi: setup_armhf_none_rpi_real +setup_armhf_none_rpi_real:: + $(MAKE) -f debian/rules.real setup-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='armhf' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='rpi' KCONFIG='debian/config/config debian/config/armel/config debian/config/armhf/config debian/config/armhf/config.rpi' KERNEL_ARCH='arm' LOCALVERSION='-rpi' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-rpi' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' setup_armhf_real: setup_hppa: setup_hppa_none setup_hppa_real setup_hppa_none: setup_hppa_none_parisc setup_hppa_none_parisc-smp setup_hppa_none_parisc64 setup_hppa_none_parisc64-smp setup_hppa_none_real setup_hppa_none_parisc: setup_hppa_none_parisc_real setup_hppa_none_parisc-smp: setup_hppa_none_parisc-smp_real setup_hppa_none_parisc-smp_real:: - $(MAKE) -f debian/rules.real setup-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='hppa' COMPILER='gcc-4.4' FEATURESET='none' FLAVOUR='parisc-smp' KCONFIG='debian/config/config debian/config/hppa/config debian/config/hppa/config.parisc-smp' KERNEL_ARCH='parisc' LOCALVERSION='-parisc-smp' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-parisc-smp' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real setup-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='hppa' COMPILER='gcc-4.4' FEATURESET='none' FLAVOUR='parisc-smp' KCONFIG='debian/config/config debian/config/hppa/config debian/config/hppa/config.parisc-smp' KERNEL_ARCH='parisc' LOCALVERSION='-parisc-smp' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-parisc-smp' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' setup_hppa_none_parisc64: setup_hppa_none_parisc64_real setup_hppa_none_parisc64-smp: setup_hppa_none_parisc64-smp_real setup_hppa_none_parisc64-smp_real:: - $(MAKE) -f debian/rules.real setup-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='hppa' CFLAGS_KERNEL='-fno-cse-follow-jumps' COMPILER='gcc-4.4' FEATURESET='none' FLAVOUR='parisc64-smp' KCONFIG='debian/config/config debian/config/hppa/config debian/config/hppa/config.parisc64-smp' KERNEL_ARCH='parisc' LOCALVERSION='-parisc64-smp' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-parisc64-smp' MODULES='True' OVERRIDE_HOST_TYPE='hppa64-linux-gnu' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real setup-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='hppa' CFLAGS_KERNEL='-fno-cse-follow-jumps' COMPILER='gcc-4.4' FEATURESET='none' FLAVOUR='parisc64-smp' KCONFIG='debian/config/config debian/config/hppa/config debian/config/hppa/config.parisc64-smp' KERNEL_ARCH='parisc' LOCALVERSION='-parisc64-smp' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-parisc64-smp' MODULES='True' OVERRIDE_HOST_TYPE='hppa64-linux-gnu' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' setup_hppa_none_parisc64_real:: - $(MAKE) -f debian/rules.real setup-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='hppa' CFLAGS_KERNEL='-fno-cse-follow-jumps' COMPILER='gcc-4.4' FEATURESET='none' FLAVOUR='parisc64' KCONFIG='debian/config/config debian/config/hppa/config debian/config/hppa/config.parisc64' KERNEL_ARCH='parisc' LOCALVERSION='-parisc64' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-parisc64' MODULES='True' OVERRIDE_HOST_TYPE='hppa64-linux-gnu' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real setup-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='hppa' CFLAGS_KERNEL='-fno-cse-follow-jumps' COMPILER='gcc-4.4' FEATURESET='none' FLAVOUR='parisc64' KCONFIG='debian/config/config debian/config/hppa/config debian/config/hppa/config.parisc64' KERNEL_ARCH='parisc' LOCALVERSION='-parisc64' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-parisc64' MODULES='True' OVERRIDE_HOST_TYPE='hppa64-linux-gnu' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' setup_hppa_none_parisc_real:: - $(MAKE) -f debian/rules.real setup-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='hppa' COMPILER='gcc-4.4' FEATURESET='none' FLAVOUR='parisc' KCONFIG='debian/config/config debian/config/hppa/config debian/config/hppa/config.parisc' KERNEL_ARCH='parisc' LOCALVERSION='-parisc' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-parisc' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real setup-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='hppa' COMPILER='gcc-4.4' FEATURESET='none' FLAVOUR='parisc' KCONFIG='debian/config/config debian/config/hppa/config debian/config/hppa/config.parisc' KERNEL_ARCH='parisc' LOCALVERSION='-parisc' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-parisc' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' setup_hppa_none_real: setup_hppa_real: setup_i386: setup_i386_none setup_i386_real setup_i386_rt setup_i386_none: setup_i386_none_486 setup_i386_none_686-pae setup_i386_none_amd64 setup_i386_none_real setup_i386_none_486: setup_i386_none_486_real setup_i386_none_486_real:: - $(MAKE) -f debian/rules.real setup-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='i386' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='486' KCONFIG='debian/config/config debian/config/kernelarch-x86/config debian/config/kernelarch-x86/config-arch-32 debian/config/i386/none/config.486' KERNEL_ARCH='x86' LOCALVERSION='-486' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-486' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real setup-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='i386' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='486' KCONFIG='debian/config/config debian/config/kernelarch-x86/config debian/config/kernelarch-x86/config-arch-32 debian/config/i386/none/config.486' KERNEL_ARCH='x86' LOCALVERSION='-486' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-486' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' setup_i386_none_686-pae: setup_i386_none_686-pae_real setup_i386_none_686-pae_real:: - $(MAKE) -f debian/rules.real setup-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='i386' COMPILER='gcc-4.6' DEBUG='True' FEATURESET='none' FLAVOUR='686-pae' KCONFIG='debian/config/config debian/config/kernelarch-x86/config debian/config/kernelarch-x86/config-arch-32 debian/config/i386/none/config.686-pae' KCONFIG_OPTIONS='-o DEBUG_INFO=y' KERNEL_ARCH='x86' LOCALVERSION='-686-pae' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-686-pae' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real setup-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='i386' COMPILER='gcc-4.6' DEBUG='True' FEATURESET='none' FLAVOUR='686-pae' KCONFIG='debian/config/config debian/config/kernelarch-x86/config debian/config/kernelarch-x86/config-arch-32 debian/config/i386/none/config.686-pae' KCONFIG_OPTIONS='-o DEBUG_INFO=y' KERNEL_ARCH='x86' LOCALVERSION='-686-pae' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-686-pae' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' setup_i386_none_amd64: setup_i386_none_amd64_real setup_i386_none_amd64_real:: - $(MAKE) -f debian/rules.real setup-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='i386' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='amd64' KCONFIG='debian/config/config debian/config/kernelarch-x86/config debian/config/kernelarch-x86/config-arch-64' KERNEL_ARCH='x86' LOCALVERSION='-amd64' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-amd64' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real setup-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='i386' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='amd64' KCONFIG='debian/config/config debian/config/kernelarch-x86/config debian/config/kernelarch-x86/config-arch-64' KERNEL_ARCH='x86' LOCALVERSION='-amd64' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-amd64' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' setup_i386_none_real: setup_i386_real: setup_i386_rt: setup_i386_rt_686-pae setup_i386_rt_real setup_i386_rt_686-pae: setup_i386_rt_686-pae_real setup_i386_rt_686-pae_real:: - $(MAKE) -f debian/rules.real setup-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='i386' COMPILER='gcc-4.6' DEBUG='True' FEATURESET='rt' FLAVOUR='686-pae' KCONFIG='debian/config/config debian/config/kernelarch-x86/config debian/config/kernelarch-x86/config-arch-32 debian/config/featureset-rt/config debian/config/i386/rt/config.686-pae' KCONFIG_OPTIONS='-o DEBUG_INFO=y' KERNEL_ARCH='x86' LOCALVERSION='-rt-686-pae' LOCALVERSION_HEADERS='-rt' LOCALVERSION_IMAGE='-rt-686-pae' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real setup-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='i386' COMPILER='gcc-4.6' DEBUG='True' FEATURESET='rt' FLAVOUR='686-pae' KCONFIG='debian/config/config debian/config/kernelarch-x86/config debian/config/kernelarch-x86/config-arch-32 debian/config/featureset-rt/config debian/config/i386/rt/config.686-pae' KCONFIG_OPTIONS='-o DEBUG_INFO=y' KERNEL_ARCH='x86' LOCALVERSION='-rt-686-pae' LOCALVERSION_HEADERS='-rt' LOCALVERSION_IMAGE='-rt-686-pae' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' setup_i386_rt_real: setup_ia64: setup_ia64_none setup_ia64_real setup_ia64_none: setup_ia64_none_itanium setup_ia64_none_mckinley setup_ia64_none_real setup_ia64_none_itanium: setup_ia64_none_itanium_real setup_ia64_none_itanium_real:: - $(MAKE) -f debian/rules.real setup-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='ia64' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='itanium' KCONFIG='debian/config/config debian/config/ia64/config debian/config/ia64/config.itanium' KERNEL_ARCH='ia64' LOCALVERSION='-itanium' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-itanium' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real setup-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='ia64' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='itanium' KCONFIG='debian/config/config debian/config/ia64/config debian/config/ia64/config.itanium' KERNEL_ARCH='ia64' LOCALVERSION='-itanium' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-itanium' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' setup_ia64_none_mckinley: setup_ia64_none_mckinley_real setup_ia64_none_mckinley_real:: - $(MAKE) -f debian/rules.real setup-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='ia64' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='mckinley' KCONFIG='debian/config/config debian/config/ia64/config debian/config/ia64/config.mckinley' KERNEL_ARCH='ia64' LOCALVERSION='-mckinley' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-mckinley' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real setup-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='ia64' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='mckinley' KCONFIG='debian/config/config debian/config/ia64/config debian/config/ia64/config.mckinley' KERNEL_ARCH='ia64' LOCALVERSION='-mckinley' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-mckinley' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' setup_ia64_none_real: setup_ia64_real: setup_m68k: setup_m68k_none setup_m68k_real setup_m68k_none: setup_m68k_none_amiga setup_m68k_none_atari setup_m68k_none_bvme6000 setup_m68k_none_mac setup_m68k_none_mvme147 setup_m68k_none_mvme16x setup_m68k_none_real setup_m68k_none_amiga: setup_m68k_none_amiga_real setup_m68k_none_amiga_real:: - $(MAKE) -f debian/rules.real setup-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='m68k' CFLAGS_KERNEL='-ffreestanding' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='amiga' INITRAMFS='False' KCONFIG='debian/config/config debian/config/m68k/config debian/config/m68k/config.amiga' KERNEL_ARCH='m68k' LOCALVERSION='-amiga' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-amiga' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real setup-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='m68k' CFLAGS_KERNEL='-ffreestanding' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='amiga' INITRAMFS='False' KCONFIG='debian/config/config debian/config/m68k/config debian/config/m68k/config.amiga' KERNEL_ARCH='m68k' LOCALVERSION='-amiga' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-amiga' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' setup_m68k_none_atari: setup_m68k_none_atari_real setup_m68k_none_atari_real:: - $(MAKE) -f debian/rules.real setup-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='m68k' CFLAGS_KERNEL='-ffreestanding' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='atari' INITRAMFS='False' KCONFIG='debian/config/config debian/config/m68k/config debian/config/m68k/config.atari' KERNEL_ARCH='m68k' LOCALVERSION='-atari' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-atari' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real setup-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='m68k' CFLAGS_KERNEL='-ffreestanding' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='atari' INITRAMFS='False' KCONFIG='debian/config/config debian/config/m68k/config debian/config/m68k/config.atari' KERNEL_ARCH='m68k' LOCALVERSION='-atari' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-atari' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' setup_m68k_none_bvme6000: setup_m68k_none_bvme6000_real setup_m68k_none_bvme6000_real:: - $(MAKE) -f debian/rules.real setup-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='m68k' CFLAGS_KERNEL='-ffreestanding' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='bvme6000' INITRAMFS='False' KCONFIG='debian/config/config debian/config/m68k/config debian/config/m68k/config.bvme6000' KERNEL_ARCH='m68k' LOCALVERSION='-bvme6000' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-bvme6000' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real setup-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='m68k' CFLAGS_KERNEL='-ffreestanding' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='bvme6000' INITRAMFS='False' KCONFIG='debian/config/config debian/config/m68k/config debian/config/m68k/config.bvme6000' KERNEL_ARCH='m68k' LOCALVERSION='-bvme6000' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-bvme6000' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' setup_m68k_none_mac: setup_m68k_none_mac_real setup_m68k_none_mac_real:: - $(MAKE) -f debian/rules.real setup-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='m68k' CFLAGS_KERNEL='-ffreestanding' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='mac' INITRAMFS='False' KCONFIG='debian/config/config debian/config/m68k/config debian/config/m68k/config.mac' KERNEL_ARCH='m68k' LOCALVERSION='-mac' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-mac' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real setup-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='m68k' CFLAGS_KERNEL='-ffreestanding' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='mac' INITRAMFS='False' KCONFIG='debian/config/config debian/config/m68k/config debian/config/m68k/config.mac' KERNEL_ARCH='m68k' LOCALVERSION='-mac' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-mac' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' setup_m68k_none_mvme147: setup_m68k_none_mvme147_real setup_m68k_none_mvme147_real:: - $(MAKE) -f debian/rules.real setup-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='m68k' CFLAGS_KERNEL='-ffreestanding' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='mvme147' INITRAMFS='False' KCONFIG='debian/config/config debian/config/m68k/config debian/config/m68k/config.mvme147' KERNEL_ARCH='m68k' LOCALVERSION='-mvme147' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-mvme147' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real setup-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='m68k' CFLAGS_KERNEL='-ffreestanding' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='mvme147' INITRAMFS='False' KCONFIG='debian/config/config debian/config/m68k/config debian/config/m68k/config.mvme147' KERNEL_ARCH='m68k' LOCALVERSION='-mvme147' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-mvme147' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' setup_m68k_none_mvme16x: setup_m68k_none_mvme16x_real setup_m68k_none_mvme16x_real:: - $(MAKE) -f debian/rules.real setup-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='m68k' CFLAGS_KERNEL='-ffreestanding' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='mvme16x' INITRAMFS='False' KCONFIG='debian/config/config debian/config/m68k/config debian/config/m68k/config.mvme16x' KERNEL_ARCH='m68k' LOCALVERSION='-mvme16x' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-mvme16x' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real setup-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='m68k' CFLAGS_KERNEL='-ffreestanding' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='mvme16x' INITRAMFS='False' KCONFIG='debian/config/config debian/config/m68k/config debian/config/m68k/config.mvme16x' KERNEL_ARCH='m68k' LOCALVERSION='-mvme16x' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-mvme16x' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' setup_m68k_none_real: setup_m68k_real: setup_mips: setup_mips_none setup_mips_real setup_mips_none: setup_mips_none_4kc-malta setup_mips_none_5kc-malta setup_mips_none_octeon setup_mips_none_r4k-ip22 setup_mips_none_r5k-ip32 setup_mips_none_real setup_mips_none_sb1-bcm91250a setup_mips_none_sb1a-bcm91480b setup_mips_none_4kc-malta: setup_mips_none_4kc-malta_real setup_mips_none_4kc-malta_real:: - $(MAKE) -f debian/rules.real setup-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='mips' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='4kc-malta' INITRAMFS='False' KCONFIG='debian/config/config debian/config/kernelarch-mips/config debian/config/mips/config debian/config/mips/config.4kc-malta' KERNEL_ARCH='mips' LOCALVERSION='-4kc-malta' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-4kc-malta' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real setup-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='mips' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='4kc-malta' INITRAMFS='False' KCONFIG='debian/config/config debian/config/kernelarch-mips/config debian/config/mips/config debian/config/mips/config.4kc-malta' KERNEL_ARCH='mips' LOCALVERSION='-4kc-malta' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-4kc-malta' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' setup_mips_none_5kc-malta: setup_mips_none_5kc-malta_real setup_mips_none_5kc-malta_real:: - $(MAKE) -f debian/rules.real setup-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='mips' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='5kc-malta' INITRAMFS='False' KCONFIG='debian/config/config debian/config/kernelarch-mips/config debian/config/mips/config debian/config/mips/config.5kc-malta' KERNEL_ARCH='mips' LOCALVERSION='-5kc-malta' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-5kc-malta' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real setup-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='mips' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='5kc-malta' INITRAMFS='False' KCONFIG='debian/config/config debian/config/kernelarch-mips/config debian/config/mips/config debian/config/mips/config.5kc-malta' KERNEL_ARCH='mips' LOCALVERSION='-5kc-malta' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-5kc-malta' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' setup_mips_none_octeon: setup_mips_none_octeon_real setup_mips_none_octeon_real:: - $(MAKE) -f debian/rules.real setup-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='mips' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='octeon' INITRAMFS='False' KCONFIG='debian/config/config debian/config/kernelarch-mips/config debian/config/mips/config debian/config/mips/config.octeon' KERNEL_ARCH='mips' LOCALVERSION='-octeon' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-octeon' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real setup-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='mips' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='octeon' INITRAMFS='False' KCONFIG='debian/config/config debian/config/kernelarch-mips/config debian/config/mips/config debian/config/mips/config.octeon' KERNEL_ARCH='mips' LOCALVERSION='-octeon' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-octeon' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' setup_mips_none_r4k-ip22: setup_mips_none_r4k-ip22_real setup_mips_none_r4k-ip22_real:: - $(MAKE) -f debian/rules.real setup-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='mips' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='r4k-ip22' INITRAMFS='False' KCONFIG='debian/config/config debian/config/kernelarch-mips/config debian/config/mips/config debian/config/mips/config.r4k-ip22' KERNEL_ARCH='mips' LOCALVERSION='-r4k-ip22' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-r4k-ip22' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real setup-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='mips' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='r4k-ip22' INITRAMFS='False' KCONFIG='debian/config/config debian/config/kernelarch-mips/config debian/config/mips/config debian/config/mips/config.r4k-ip22' KERNEL_ARCH='mips' LOCALVERSION='-r4k-ip22' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-r4k-ip22' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' setup_mips_none_r5k-ip32: setup_mips_none_r5k-ip32_real setup_mips_none_r5k-ip32_real:: - $(MAKE) -f debian/rules.real setup-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='mips' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='r5k-ip32' INITRAMFS='False' KCONFIG='debian/config/config debian/config/kernelarch-mips/config debian/config/mips/config debian/config/mips/config.r5k-ip32' KERNEL_ARCH='mips' LOCALVERSION='-r5k-ip32' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-r5k-ip32' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real setup-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='mips' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='r5k-ip32' INITRAMFS='False' KCONFIG='debian/config/config debian/config/kernelarch-mips/config debian/config/mips/config debian/config/mips/config.r5k-ip32' KERNEL_ARCH='mips' LOCALVERSION='-r5k-ip32' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-r5k-ip32' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' setup_mips_none_real: setup_mips_none_sb1-bcm91250a: setup_mips_none_sb1-bcm91250a_real setup_mips_none_sb1-bcm91250a_real:: - $(MAKE) -f debian/rules.real setup-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='mips' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='sb1-bcm91250a' INITRAMFS='False' KCONFIG='debian/config/config debian/config/kernelarch-mips/config debian/config/mips/config debian/config/mips/config.sb1-bcm91250a' KERNEL_ARCH='mips' LOCALVERSION='-sb1-bcm91250a' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-sb1-bcm91250a' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real setup-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='mips' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='sb1-bcm91250a' INITRAMFS='False' KCONFIG='debian/config/config debian/config/kernelarch-mips/config debian/config/mips/config debian/config/mips/config.sb1-bcm91250a' KERNEL_ARCH='mips' LOCALVERSION='-sb1-bcm91250a' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-sb1-bcm91250a' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' setup_mips_none_sb1a-bcm91480b: setup_mips_none_sb1a-bcm91480b_real setup_mips_none_sb1a-bcm91480b_real:: - $(MAKE) -f debian/rules.real setup-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='mips' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='sb1a-bcm91480b' INITRAMFS='False' KCONFIG='debian/config/config debian/config/kernelarch-mips/config debian/config/mips/config debian/config/mips/config.sb1a-bcm91480b' KERNEL_ARCH='mips' LOCALVERSION='-sb1a-bcm91480b' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-sb1a-bcm91480b' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real setup-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='mips' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='sb1a-bcm91480b' INITRAMFS='False' KCONFIG='debian/config/config debian/config/kernelarch-mips/config debian/config/mips/config debian/config/mips/config.sb1a-bcm91480b' KERNEL_ARCH='mips' LOCALVERSION='-sb1a-bcm91480b' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-sb1a-bcm91480b' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' setup_mips_real: setup_mipsel: setup_mipsel_none setup_mipsel_real setup_mipsel_none: setup_mipsel_none_4kc-malta setup_mipsel_none_5kc-malta setup_mipsel_none_loongson-2f setup_mipsel_none_r5k-cobalt setup_mipsel_none_real setup_mipsel_none_sb1-bcm91250a setup_mipsel_none_sb1a-bcm91480b setup_mipsel_none_4kc-malta: setup_mipsel_none_4kc-malta_real setup_mipsel_none_4kc-malta_real:: - $(MAKE) -f debian/rules.real setup-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='mipsel' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='4kc-malta' INITRAMFS='False' KCONFIG='debian/config/config debian/config/kernelarch-mips/config debian/config/mipsel/config debian/config/mips/config.4kc-malta' KERNEL_ARCH='mips' LOCALVERSION='-4kc-malta' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-4kc-malta' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real setup-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='mipsel' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='4kc-malta' INITRAMFS='False' KCONFIG='debian/config/config debian/config/kernelarch-mips/config debian/config/mipsel/config debian/config/mips/config.4kc-malta' KERNEL_ARCH='mips' LOCALVERSION='-4kc-malta' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-4kc-malta' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' setup_mipsel_none_5kc-malta: setup_mipsel_none_5kc-malta_real setup_mipsel_none_5kc-malta_real:: - $(MAKE) -f debian/rules.real setup-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='mipsel' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='5kc-malta' INITRAMFS='False' KCONFIG='debian/config/config debian/config/kernelarch-mips/config debian/config/mipsel/config debian/config/mips/config.5kc-malta' KERNEL_ARCH='mips' LOCALVERSION='-5kc-malta' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-5kc-malta' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real setup-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='mipsel' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='5kc-malta' INITRAMFS='False' KCONFIG='debian/config/config debian/config/kernelarch-mips/config debian/config/mipsel/config debian/config/mips/config.5kc-malta' KERNEL_ARCH='mips' LOCALVERSION='-5kc-malta' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-5kc-malta' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' setup_mipsel_none_loongson-2f: setup_mipsel_none_loongson-2f_real setup_mipsel_none_loongson-2f_real:: - $(MAKE) -f debian/rules.real setup-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='mipsel' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='loongson-2f' INITRAMFS='False' KCONFIG='debian/config/config debian/config/kernelarch-mips/config debian/config/mipsel/config debian/config/mipsel/config.loongson-2f' KERNEL_ARCH='mips' LOCALVERSION='-loongson-2f' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-loongson-2f' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real setup-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='mipsel' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='loongson-2f' INITRAMFS='False' KCONFIG='debian/config/config debian/config/kernelarch-mips/config debian/config/mipsel/config debian/config/mipsel/config.loongson-2f' KERNEL_ARCH='mips' LOCALVERSION='-loongson-2f' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-loongson-2f' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' setup_mipsel_none_r5k-cobalt: setup_mipsel_none_r5k-cobalt_real setup_mipsel_none_r5k-cobalt_real:: - $(MAKE) -f debian/rules.real setup-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='mipsel' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='r5k-cobalt' INITRAMFS='False' KCONFIG='debian/config/config debian/config/kernelarch-mips/config debian/config/mipsel/config debian/config/mipsel/config.r5k-cobalt' KERNEL_ARCH='mips' LOCALVERSION='-r5k-cobalt' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-r5k-cobalt' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real setup-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='mipsel' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='r5k-cobalt' INITRAMFS='False' KCONFIG='debian/config/config debian/config/kernelarch-mips/config debian/config/mipsel/config debian/config/mipsel/config.r5k-cobalt' KERNEL_ARCH='mips' LOCALVERSION='-r5k-cobalt' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-r5k-cobalt' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' setup_mipsel_none_real: setup_mipsel_none_sb1-bcm91250a: setup_mipsel_none_sb1-bcm91250a_real setup_mipsel_none_sb1-bcm91250a_real:: - $(MAKE) -f debian/rules.real setup-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='mipsel' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='sb1-bcm91250a' INITRAMFS='False' KCONFIG='debian/config/config debian/config/kernelarch-mips/config debian/config/mipsel/config debian/config/mips/config.sb1-bcm91250a' KERNEL_ARCH='mips' LOCALVERSION='-sb1-bcm91250a' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-sb1-bcm91250a' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real setup-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='mipsel' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='sb1-bcm91250a' INITRAMFS='False' KCONFIG='debian/config/config debian/config/kernelarch-mips/config debian/config/mipsel/config debian/config/mips/config.sb1-bcm91250a' KERNEL_ARCH='mips' LOCALVERSION='-sb1-bcm91250a' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-sb1-bcm91250a' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' setup_mipsel_none_sb1a-bcm91480b: setup_mipsel_none_sb1a-bcm91480b_real setup_mipsel_none_sb1a-bcm91480b_real:: - $(MAKE) -f debian/rules.real setup-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='mipsel' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='sb1a-bcm91480b' INITRAMFS='False' KCONFIG='debian/config/config debian/config/kernelarch-mips/config debian/config/mipsel/config debian/config/mips/config.sb1a-bcm91480b' KERNEL_ARCH='mips' LOCALVERSION='-sb1a-bcm91480b' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-sb1a-bcm91480b' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real setup-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='mipsel' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='sb1a-bcm91480b' INITRAMFS='False' KCONFIG='debian/config/config debian/config/kernelarch-mips/config debian/config/mipsel/config debian/config/mips/config.sb1a-bcm91480b' KERNEL_ARCH='mips' LOCALVERSION='-sb1a-bcm91480b' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-sb1a-bcm91480b' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' setup_mipsel_real: setup_powerpc: setup_powerpc_none setup_powerpc_real setup_powerpc_none: setup_powerpc_none_powerpc setup_powerpc_none_powerpc-smp setup_powerpc_none_powerpc64 setup_powerpc_none_real setup_powerpc_none_powerpc: setup_powerpc_none_powerpc_real setup_powerpc_none_powerpc-smp: setup_powerpc_none_powerpc-smp_real setup_powerpc_none_powerpc-smp_real:: - $(MAKE) -f debian/rules.real setup-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='powerpc' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='powerpc-smp' KCONFIG='debian/config/config debian/config/powerpc/config debian/config/powerpc/config.powerpc debian/config/powerpc/config.powerpc-smp' KERNEL_ARCH='powerpc' LOCALVERSION='-powerpc-smp' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-powerpc-smp' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real setup-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='powerpc' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='powerpc-smp' KCONFIG='debian/config/config debian/config/powerpc/config debian/config/powerpc/config.powerpc debian/config/powerpc/config.powerpc-smp' KERNEL_ARCH='powerpc' LOCALVERSION='-powerpc-smp' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-powerpc-smp' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' setup_powerpc_none_powerpc64: setup_powerpc_none_powerpc64_real setup_powerpc_none_powerpc64_real:: - $(MAKE) -f debian/rules.real setup-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='powerpc' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='powerpc64' KCONFIG='debian/config/config debian/config/powerpc/config debian/config/powerpc/config.powerpc64' KERNEL_ARCH='powerpc' LOCALVERSION='-powerpc64' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-powerpc64' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real setup-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='powerpc' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='powerpc64' KCONFIG='debian/config/config debian/config/powerpc/config debian/config/powerpc/config.powerpc64' KERNEL_ARCH='powerpc' LOCALVERSION='-powerpc64' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-powerpc64' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' setup_powerpc_none_powerpc_real:: - $(MAKE) -f debian/rules.real setup-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='powerpc' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='powerpc' KCONFIG='debian/config/config debian/config/powerpc/config debian/config/powerpc/config.powerpc' KERNEL_ARCH='powerpc' LOCALVERSION='-powerpc' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-powerpc' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real setup-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='powerpc' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='powerpc' KCONFIG='debian/config/config debian/config/powerpc/config debian/config/powerpc/config.powerpc' KERNEL_ARCH='powerpc' LOCALVERSION='-powerpc' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-powerpc' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' setup_powerpc_none_real: setup_powerpc_real: setup_ppc64: setup_ppc64_none setup_ppc64_real setup_ppc64_none: setup_ppc64_none_powerpc64 setup_ppc64_none_real setup_ppc64_none_powerpc64: setup_ppc64_none_powerpc64_real setup_ppc64_none_powerpc64_real:: - $(MAKE) -f debian/rules.real setup-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='ppc64' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='powerpc64' KCONFIG='debian/config/config debian/config/powerpc/config debian/config/powerpc/config.powerpc64' KERNEL_ARCH='powerpc' LOCALVERSION='-powerpc64' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-powerpc64' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real setup-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='ppc64' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='powerpc64' KCONFIG='debian/config/config debian/config/powerpc/config debian/config/powerpc/config.powerpc64' KERNEL_ARCH='powerpc' LOCALVERSION='-powerpc64' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-powerpc64' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' setup_ppc64_none_real: setup_ppc64_real: setup_s390: setup_s390_none setup_s390_real @@ -813,9 +795,9 @@ setup_s390_none_s390x: setup_s390_none_s390x_real setup_s390_none_s390x-tape: setup_s390_none_s390x-tape_real setup_s390_none_s390x-tape_real:: - $(MAKE) -f debian/rules.real setup-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='s390' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='s390x-tape' INITRAMFS='False' KCONFIG='debian/config/config debian/config/s390/config debian/config/s390/config.s390x-tape' KERNEL_ARCH='s390' LOCALVERSION='-s390x-tape' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-s390x' SOURCEVERSION='3.2.46-1' TYPE='plain-s390-tape' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real setup-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='s390' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='s390x-tape' INITRAMFS='False' KCONFIG='debian/config/config debian/config/s390/config debian/config/s390/config.s390x-tape' KERNEL_ARCH='s390' LOCALVERSION='-s390x-tape' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-s390x' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain-s390-tape' UPSTREAMVERSION='3.2' VERSION='3.2' setup_s390_none_s390x_real:: - $(MAKE) -f debian/rules.real setup-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='s390' COMPILER='gcc-4.6' DEBUG='True' FEATURESET='none' FLAVOUR='s390x' KCONFIG='debian/config/config debian/config/s390/config debian/config/s390/config.s390x' KCONFIG_OPTIONS='-o DEBUG_INFO=y' KERNEL_ARCH='s390' LOCALVERSION='-s390x' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-s390x' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real setup-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='s390' COMPILER='gcc-4.6' DEBUG='True' FEATURESET='none' FLAVOUR='s390x' KCONFIG='debian/config/config debian/config/s390/config debian/config/s390/config.s390x' KCONFIG_OPTIONS='-o DEBUG_INFO=y' KERNEL_ARCH='s390' LOCALVERSION='-s390x' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-s390x' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' setup_s390_real: setup_s390x: setup_s390x_none setup_s390x_real setup_s390x_none: setup_s390x_none_real setup_s390x_none_s390x setup_s390x_none_s390x-tape @@ -823,19 +805,19 @@ setup_s390x_none_s390x: setup_s390x_none_s390x_real setup_s390x_none_s390x-tape: setup_s390x_none_s390x-tape_real setup_s390x_none_s390x-tape_real:: - $(MAKE) -f debian/rules.real setup-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='s390x' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='s390x-tape' INITRAMFS='False' KCONFIG='debian/config/config debian/config/s390/config debian/config/s390/config.s390x-tape' KERNEL_ARCH='s390' LOCALVERSION='-s390x-tape' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-s390x' SOURCEVERSION='3.2.46-1' TYPE='plain-s390-tape' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real setup-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='s390x' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='s390x-tape' INITRAMFS='False' KCONFIG='debian/config/config debian/config/s390/config debian/config/s390/config.s390x-tape' KERNEL_ARCH='s390' LOCALVERSION='-s390x-tape' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-s390x' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain-s390-tape' UPSTREAMVERSION='3.2' VERSION='3.2' setup_s390x_none_s390x_real:: - $(MAKE) -f debian/rules.real setup-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='s390x' COMPILER='gcc-4.6' DEBUG='True' FEATURESET='none' FLAVOUR='s390x' KCONFIG='debian/config/config debian/config/s390/config debian/config/s390/config.s390x' KCONFIG_OPTIONS='-o DEBUG_INFO=y' KERNEL_ARCH='s390' LOCALVERSION='-s390x' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-s390x' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real setup-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='s390x' COMPILER='gcc-4.6' DEBUG='True' FEATURESET='none' FLAVOUR='s390x' KCONFIG='debian/config/config debian/config/s390/config debian/config/s390/config.s390x' KCONFIG_OPTIONS='-o DEBUG_INFO=y' KERNEL_ARCH='s390' LOCALVERSION='-s390x' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-s390x' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' setup_s390x_real: setup_sh4: setup_sh4_none setup_sh4_real setup_sh4_none: setup_sh4_none_real setup_sh4_none_sh7751r setup_sh4_none_sh7785lcr setup_sh4_none_real: setup_sh4_none_sh7751r: setup_sh4_none_sh7751r_real setup_sh4_none_sh7751r_real:: - $(MAKE) -f debian/rules.real setup-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='sh4' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='sh7751r' KCONFIG='debian/config/config debian/config/sh4/config debian/config/sh4/config.sh7751r' KERNEL_ARCH='sh' LOCALVERSION='-sh7751r' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-sh7751r' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real setup-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='sh4' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='sh7751r' KCONFIG='debian/config/config debian/config/sh4/config debian/config/sh4/config.sh7751r' KERNEL_ARCH='sh' LOCALVERSION='-sh7751r' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-sh7751r' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' setup_sh4_none_sh7785lcr: setup_sh4_none_sh7785lcr_real setup_sh4_none_sh7785lcr_real:: - $(MAKE) -f debian/rules.real setup-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='sh4' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='sh7785lcr' KCONFIG='debian/config/config debian/config/sh4/config debian/config/sh4/config.sh7785lcr' KERNEL_ARCH='sh' LOCALVERSION='-sh7785lcr' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-sh7785lcr' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real setup-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='sh4' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='sh7785lcr' KCONFIG='debian/config/config debian/config/sh4/config debian/config/sh4/config.sh7785lcr' KERNEL_ARCH='sh' LOCALVERSION='-sh7785lcr' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-sh7785lcr' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' setup_sh4_real: setup_sparc: setup_sparc_none setup_sparc_real setup_sparc64: setup_sparc64_none setup_sparc64_real @@ -844,23 +826,23 @@ setup_sparc64_none_sparc64: setup_sparc64_none_sparc64_real setup_sparc64_none_sparc64-smp: setup_sparc64_none_sparc64-smp_real setup_sparc64_none_sparc64-smp_real:: - $(MAKE) -f debian/rules.real setup-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='sparc64' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='sparc64-smp' KCONFIG='debian/config/config debian/config/sparc/config debian/config/sparc/config.sparc64-smp' KERNEL_ARCH='sparc' LOCALVERSION='-sparc64-smp' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-sparc64-smp' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real setup-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='sparc64' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='sparc64-smp' KCONFIG='debian/config/config debian/config/sparc/config debian/config/sparc/config.sparc64-smp' KERNEL_ARCH='sparc' LOCALVERSION='-sparc64-smp' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-sparc64-smp' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' setup_sparc64_none_sparc64_real:: - $(MAKE) -f debian/rules.real setup-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='sparc64' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='sparc64' KCONFIG='debian/config/config debian/config/sparc/config debian/config/sparc/config.sparc64' KERNEL_ARCH='sparc' LOCALVERSION='-sparc64' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-sparc64' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real setup-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='sparc64' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='sparc64' KCONFIG='debian/config/config debian/config/sparc/config debian/config/sparc/config.sparc64' KERNEL_ARCH='sparc' LOCALVERSION='-sparc64' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-sparc64' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' setup_sparc64_real: setup_sparc_none: setup_sparc_none_real setup_sparc_none_sparc64 setup_sparc_none_sparc64-smp setup_sparc_none_real: setup_sparc_none_sparc64: setup_sparc_none_sparc64_real setup_sparc_none_sparc64-smp: setup_sparc_none_sparc64-smp_real setup_sparc_none_sparc64-smp_real:: - $(MAKE) -f debian/rules.real setup-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='sparc' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='sparc64-smp' KCONFIG='debian/config/config debian/config/sparc/config debian/config/sparc/config.sparc64-smp' KERNEL_ARCH='sparc' LOCALVERSION='-sparc64-smp' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-sparc64-smp' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real setup-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='sparc' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='sparc64-smp' KCONFIG='debian/config/config debian/config/sparc/config debian/config/sparc/config.sparc64-smp' KERNEL_ARCH='sparc' LOCALVERSION='-sparc64-smp' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-sparc64-smp' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' setup_sparc_none_sparc64_real:: - $(MAKE) -f debian/rules.real setup-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='sparc' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='sparc64' KCONFIG='debian/config/config debian/config/sparc/config debian/config/sparc/config.sparc64' KERNEL_ARCH='sparc' LOCALVERSION='-sparc64' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-sparc64' MODULES='True' SOURCEVERSION='3.2.46-1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real setup-flavour ABINAME='3.2.0-4' ABINAME_PART='-4' ARCH='sparc' COMPILER='gcc-4.6' FEATURESET='none' FLAVOUR='sparc64' KCONFIG='debian/config/config debian/config/sparc/config debian/config/sparc/config.sparc64' KERNEL_ARCH='sparc' LOCALVERSION='-sparc64' LOCALVERSION_HEADERS='' LOCALVERSION_IMAGE='-sparc64' MODULES='True' SOURCEVERSION='3.2.46-1+rpi1' TYPE='plain' UPSTREAMVERSION='3.2' VERSION='3.2' setup_sparc_real: source: source_none source_rt source_none: source_none_real source_none_real:: - $(MAKE) -f debian/rules.real source-featureset ABINAME='3.2.0-4' ABINAME_PART='-4' FEATURESET='none' SOURCEVERSION='3.2.46-1' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real source-featureset ABINAME='3.2.0-4' ABINAME_PART='-4' FEATURESET='none' SOURCEVERSION='3.2.46-1+rpi1' UPSTREAMVERSION='3.2' VERSION='3.2' source_rt: source_rt_real source_rt_real:: - $(MAKE) -f debian/rules.real source-featureset ABINAME='3.2.0-4' ABINAME_PART='-4' FEATURESET='rt' SOURCEVERSION='3.2.46-1' UPSTREAMVERSION='3.2' VERSION='3.2' + $(MAKE) -f debian/rules.real source-featureset ABINAME='3.2.0-4' ABINAME_PART='-4' FEATURESET='rt' SOURCEVERSION='3.2.46-1+rpi1' UPSTREAMVERSION='3.2' VERSION='3.2' diff -Nru linux-3.2.46/debian/splitseries.php linux-3.2.46/debian/splitseries.php --- linux-3.2.46/debian/splitseries.php 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/splitseries.php 2013-07-26 18:03:40.000000000 +0000 @@ -0,0 +1,22 @@ +#!/usr/bin/php + \ No newline at end of file diff -Nru linux-3.2.46/debian/templates/temp.image.plain/postinst linux-3.2.46/debian/templates/temp.image.plain/postinst --- linux-3.2.46/debian/templates/temp.image.plain/postinst 2013-02-24 03:53:13.000000000 +0000 +++ linux-3.2.46/debian/templates/temp.image.plain/postinst 2013-07-26 18:03:40.000000000 +0000 @@ -37,6 +37,10 @@ # Ignore all invocations except when called on to configure. exit 0 unless $ARGV[0] =~ /configure/; +system("dpkg-divert --package rpikernelhack --remove --rename /boot/$kimage-$version"); +system("dpkg-divert --package rpikernelhack --remove --rename /boot/config-$version"); +system("dpkg-divert --package rpikernelhack --remove --rename /boot/System.map-$version"); + my $DEBUG = 0; # Do some preliminary sanity checks here to ensure we actually have an diff -Nru linux-3.2.46/debian/templates/temp.image.plain/preinst linux-3.2.46/debian/templates/temp.image.plain/preinst --- linux-3.2.46/debian/templates/temp.image.plain/preinst 2013-02-24 03:53:13.000000000 +0000 +++ linux-3.2.46/debian/templates/temp.image.plain/preinst 2013-07-26 18:03:40.000000000 +0000 @@ -119,6 +119,13 @@ die "Failed to process /etc/kernel/preinst.d/$version"; } +# Rpi diversion hack +system("mkdir -p /usr/share/rpikernelhack"); +system("dpkg-divert --package rpikernelhack --divert /usr/share/rpikernelhack/$kimage-$version --rename /boot/$kimage-$version"); +system("dpkg-divert --package rpikernelhack --divert /usr/share/rpikernelhack/config-$version --rename /boot/config-$version"); +system("dpkg-divert --package rpikernelhack --divert /usr/share/rpikernelhack/System.map-$version --rename /boot/System.map-$version"); + + exit 0; __END__ diff -Nru linux-3.2.46/debian/update-rpi-patches linux-3.2.46/debian/update-rpi-patches --- linux-3.2.46/debian/update-rpi-patches 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/update-rpi-patches 2013-07-26 18:10:24.000000000 +0000 @@ -0,0 +1,85 @@ +#!/bin/bash -ev +set -x +set -e +debdir=`pwd` +upstream_tag=v3.2.41 +rpi_branch=rpi-3.2.27 +patch_dir=${debdir}/debian/patches +rpi_patches=${patch_dir}/rpi + +export QUILT_PATCHES=debian/patches +quilt pop -a || [ $? == 2 ] + + # add rempote repositories, and update (needs a around 500M) +rm -rf linuxgit +git clone -o linux-stable --reference ../linuxgit git://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-stable.git linuxgit +cd linuxgit +git remote add rpi https://github.com/raspberrypi/linux.git +git remote update + + # create branch from tag and switch to it +git checkout -b target-version ${upstream_tag} + +# record commits used to base patches on +git show ${upstream_tag} > ../debian/upstream-tag-used-to-generate-rpi-patches +git show rpi/${rpi_branch} > ../debian/rpi-branch + +# merge the changes from the rpi branch +git merge --no-edit rpi/${rpi_branch} + +# get a list of commits not present upstream +git_commits=$(git cherry ${upstream_tag} | awk '/^\+/{print $2}') + +# generate one patch per commit, including comments, with an ordered sequence +# to preserve patch ordering. +i=100 +mkdir -p ${rpi_patches} +rm ${rpi_patches}/* +for c in $git_commits ; do + git show ${c} > ${rpi_patches}/rpi_${i}_${c}.patch + i=$((${i}+1)) +done + +git diff ${upstream_tag} > ../merged.diff +export QUILT_PATCHES=../debian/patches + +# split quilt series and remove pi patches +cd .. +chmod 755 debian/splitseries.php +debian/splitseries.php +cd linuxgit + +# create new quilt series, use just the new series for now for testing +ls ${rpi_patches} | sed s_^_rpi/_ > ${patch_dir}/series.fromgit +cp ${patch_dir}/series.fromgit ${patch_dir}/series + +git reset --hard ${upstream_tag} +cd .. + +rm -rf linuxtest linuxclean + +rsync -a --exclude .git linuxgit/ linuxtest/ +cp -al linuxgit linuxclean +rm -rf linuxclean/.git + +cd linuxtest +export QUILT_PATCHES=../debian/patches +quilt push -a +cd .. + +diff -urN linuxclean linuxtest | filterdiff -p1 -x '.pc/*' > patched.diff || [ $? == 1 ] +interdiff -p1 merged.diff patched.diff > mergecheck.diff + +#reassemble full quilt series +cat ${patch_dir}/series.prefix ${patch_dir}/series.fromgit ${patch_dir}/series.suffix > ${patch_dir}/series + + + +export QUILT_PATCHES=debian/patches +while quilt push; do quilt refresh; done + +rm -rf linuxgit linuxclean linuxtest +rm merged.diff patched.diff +rm debian/patches/series.* + +echo finished sucessfully \ No newline at end of file diff -Nru linux-3.2.46/debian/upstream-tag-used-to-generate-rpi-patches linux-3.2.46/debian/upstream-tag-used-to-generate-rpi-patches --- linux-3.2.46/debian/upstream-tag-used-to-generate-rpi-patches 1970-01-01 00:00:00.000000000 +0000 +++ linux-3.2.46/debian/upstream-tag-used-to-generate-rpi-patches 2013-07-26 19:08:08.000000000 +0000 @@ -0,0 +1,41 @@ +tag v3.2.41 +Tagger: Ben Hutchings +Date: Wed Mar 20 15:03:42 2013 +0000 + +This is the 3.2.41 stable release +-----BEGIN PGP SIGNATURE----- +Version: GnuPG v1.4.12 (GNU/Linux) + +iQIVAwUAUUnPzue/yOyVhhEJAQq4vw//fTGCfGRANXWiMFKCdR0BvNnPvSK0BXWO +CHnwOrCbvyViKfM/O6vx7i72JguhGSiUQ82OLjSv3UK9+S1SmRUDeJH6eHDomliZ +Jz13RXVX6zC0K1Q26ELkWAnNOH1yiI3eDKp8WKNXjRvlA7TvYu+O8Kx8mj0vHZpN +fLpkRgMw+7S71s7+H1JPfndE6/qELaRQ49WjKQWE+yDRDDYGLR0lUsbPFwZ5q0ZS +fl+VSSXDhc31ADAjFEvy5cdxbbEGRBNL6to5RmcQIhrbGjyIpm4bOz0XaeyCbIuf +pirjVvwj0I5tLsUO24Li1cvqMjOLJ3xZOSIh0QHs1wMlUrC6gP77gAv4fhT/0Gdv +n+JMUtPJHS5J+40brvkLv735n7n7XUX0MGD5l/QeZyZn0+SviGrebWX57bsQaHdu +n24aUF+d6GEbKzfEIV7BMPvxdpZO1iCKEBvZEbyB6y81ltuO7n34nyRr9HLzvdkL +oH6wv4N93GTRZH66tN2xDGPKsGnO4AcZ5E8A4ALVqnwchOzs1A+icdaqPD5NCcuK +8oZ3Tavb5M9e6KHgWlh6ZvSdybub69iZqJsHCfkwk/dlVUhNWL57vDAwNgDqfos5 +E4PrbOvFY865qlOdM5StLSpvM8Qet6PzshJrqvTO2hjdpDCEYdCE3q5et8cjEg6q +4B8Vn68IWz8= +=M0Vt +-----END PGP SIGNATURE----- + +commit 1c08ea4b7c527e2b951d9315f88de24f3d46b0ca +Author: Ben Hutchings +Date: Wed Mar 20 15:03:42 2013 +0000 + + Linux 3.2.41 + +diff --git a/Makefile b/Makefile +index 47af1e9..95e6220 100644 +--- a/Makefile ++++ b/Makefile +@@ -1,6 +1,6 @@ + VERSION = 3 + PATCHLEVEL = 2 +-SUBLEVEL = 40 ++SUBLEVEL = 41 + EXTRAVERSION = + NAME = Saber-toothed Squirrel +